diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/FreeRTOSConfig.h index 626493a2b..3bf65213d 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/FreeRTOSConfig.h @@ -117,6 +117,7 @@ to exclude the API function. */ #define INCLUDE_eTaskGetState 1 #define INCLUDE_xTaskAbortDelay 1 #define INCLUDE_xTaskGetHandle 1 +#define INCLUDE_xSemaphoreGetMutexHolder 1 /* This demo makes use of one or more example stats formatting functions. These format the raw data provided by the uxTaskGetSystemState() function in to human diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/FreeRTOS_asm_vectors.S b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/FreeRTOS_asm_vectors.S index da7065510..0e5b7a637 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/FreeRTOS_asm_vectors.S +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/FreeRTOS_asm_vectors.S @@ -53,85 +53,21 @@ -.org 0 -.text - -.globl _boot -.globl _vector_table .globl _freertos_vector_table - .globl FIQInterrupt .globl IRQInterrupt .globl SErrorInterrupt .globl SynchronousInterrupt -.org 0 - -.section .vectors, "a" - -_vector_table: - -.set VBAR, _vector_table - -.org VBAR - b _boot - -.org (VBAR + 0x80) - b . - -.org (VBAR + 0x100) - b . - -.org (VBAR + 0x180) - b . - - -.org (VBAR + 0x200) - b . - -.org (VBAR + 0x280) - b . - -.org (VBAR + 0x300) - b . - -.org (VBAR + 0x380) - b . - - - -.org (VBAR + 0x400) - b . - -.org (VBAR + 0x480) - b . - -.org (VBAR + 0x500) - b . - -.org (VBAR + 0x580) - b . - -.org (VBAR + 0x600) - b . - -.org (VBAR + 0x680) - b . - -.org (VBAR + 0x700) - b . - -.org (VBAR + 0x780) - b . - - /****************************************************************************** * Vector table to use when FreeRTOS is running. *****************************************************************************/ -.set FREERTOS_VBAR, (VBAR+0x1000) - +.text +.section .freertos_vectors +.align 8 +.set FREERTOS_VBAR, . .org(FREERTOS_VBAR) _freertos_vector_table: b FreeRTOS_SWI_Handler diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/lscript.ld b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/lscript.ld index 4e2ff8a27..0ff6bab67 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/lscript.ld +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/lscript.ld @@ -40,6 +40,7 @@ SECTIONS { .text : { KEEP (*(.vectors)) + KEEP (*(.freertos_vectors)) *(.boot) *(.text) *(.text.*) diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/.cproject b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/.cproject index d46760bba..6f2169939 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/.cproject +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/.cproject @@ -1,8 +1,8 @@ - - + + diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/.project b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/.project index 4261c804c..a764f13fd 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/.project +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/.project @@ -1,7 +1,7 @@ RTOSDemo_A53_bsp - Created by SDK v2016.4 + Created by SDK v2018.1 diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/Makefile b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/Makefile index 71f250e6a..e6a3e6c6b 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/Makefile +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/Makefile @@ -16,16 +16,20 @@ include: $(addsuffix /make.include,$(SUBDIRS)) libs: $(addsuffix /make.libs,$(SUBDIRS)) +clean: $(addsuffix /make.clean,$(SUBDIRS)) + $(PROCESSOR)/lib/libxil.a: $(PROCESSOR)/lib/libxil_init.a cp -f $< $@ %/make.include: $(if $(wildcard $(PROCESSOR)/lib/libxil_init.a),$(PROCESSOR)/lib/libxil.a,) @echo "Running Make include in $(subst /make.include,,$@)" - $(MAKE) -C $(subst /make.include,,$@) -s include "SHELL=$(SHELL)" "COMPILER=aarch64-none-elf-gcc" "ARCHIVER=aarch64-none-elf-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-g" + $(MAKE) -C $(subst /make.include,,$@) -s include "SHELL=$(SHELL)" "COMPILER=aarch64-none-elf-gcc" "ARCHIVER=aarch64-none-elf-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-g -Wall -Wextra" %/make.libs: include @echo "Running Make libs in $(subst /make.libs,,$@)" - $(MAKE) -C $(subst /make.libs,,$@) -s libs "SHELL=$(SHELL)" "COMPILER=aarch64-none-elf-gcc" "ARCHIVER=aarch64-none-elf-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-g" + $(MAKE) -C $(subst /make.libs,,$@) -s libs "SHELL=$(SHELL)" "COMPILER=aarch64-none-elf-gcc" "ARCHIVER=aarch64-none-elf-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-g -Wall -Wextra" +%/make.clean: + $(MAKE) -C $(subst /make.clean,,$@) -s clean clean: rm -f ${PROCESSOR}/lib/libxil.a diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xparameters.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xparameters.h index 8401c40c1..afb049d71 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xparameters.h +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/include/xparameters.h @@ -1,22 +1,25 @@ +#ifndef XPARAMETERS_H /* prevent circular inclusions */ +#define XPARAMETERS_H /* by using protection macros */ + /* Definition for CPU ID */ -#define XPAR_CPU_ID 0 +#define XPAR_CPU_ID 0U /* Definitions for peripheral PSU_CORTEXA53_0 */ -#define XPAR_PSU_CORTEXA53_0_CPU_CLK_FREQ_HZ 1099989014 -#define XPAR_PSU_CORTEXA53_0_TIMESTAMP_CLK_FREQ 99998999 +#define XPAR_PSU_CORTEXA53_0_CPU_CLK_FREQ_HZ 1199880000 +#define XPAR_PSU_CORTEXA53_0_TIMESTAMP_CLK_FREQ 99990000 /******************************************************************/ /* Canonical definitions for peripheral PSU_CORTEXA53_0 */ -#define XPAR_CPU_CORTEXA53_0_CPU_CLK_FREQ_HZ 1099989014 -#define XPAR_CPU_CORTEXA53_0_TIMESTAMP_CLK_FREQ 99998999 +#define XPAR_CPU_CORTEXA53_0_CPU_CLK_FREQ_HZ 1199880000 +#define XPAR_CPU_CORTEXA53_0_TIMESTAMP_CLK_FREQ 99990000 /******************************************************************/ /* Definition for PSS REF CLK FREQUENCY */ -#define XPAR_PSU_PSS_REF_CLK_FREQ_HZ 33333000U +#define XPAR_PSU_PSS_REF_CLK_FREQ_HZ 33330000U #include "xparameters_ps.h" @@ -29,192 +32,219 @@ #define STDIN_BASEADDRESS 0xFF000000 #define STDOUT_BASEADDRESS 0xFF000000 +/******************************************************************/ + +/* Platform specific definitions */ +#define PLATFORM_ZYNQMP + +/* Definitions for sleep timer configuration */ +#define XSLEEP_TIMER_IS_DEFAULT_TIMER + + +/******************************************************************/ +/* Definitions for driver AVBUF */ +#define XPAR_XAVBUF_NUM_INSTANCES 1 + +/* Definitions for peripheral PSU_DP */ +#define XPAR_PSU_DP_DEVICE_ID 0 +#define XPAR_PSU_DP_BASEADDR 0xFD4A0000 +#define XPAR_PSU_DP_HIGHADDR 0xFD4AFFFF + + +/******************************************************************/ + +/* Canonical definitions for peripheral PSU_DP */ +#define XPAR_XAVBUF_0_DEVICE_ID XPAR_PSU_DP_DEVICE_ID +#define XPAR_XAVBUF_0_BASEADDR 0xFD4A0000 +#define XPAR_XAVBUF_0_HIGHADDR 0xFD4AFFFF + + /******************************************************************/ /* Definitions for driver AXIPMON */ -#define XPAR_XAXIPMON_NUM_INSTANCES 4 +#define XPAR_XAXIPMON_NUM_INSTANCES 4U /* Definitions for peripheral PSU_APM_0 */ -#define XPAR_PSU_APM_0_DEVICE_ID 0 -#define XPAR_PSU_APM_0_BASEADDR 0xFD0B0000 -#define XPAR_PSU_APM_0_HIGHADDR 0xFD0BFFFF -#define XPAR_PSU_APM_0_GLOBAL_COUNT_WIDTH 32 -#define XPAR_PSU_APM_0_METRICS_SAMPLE_COUNT_WIDTH 32 -#define XPAR_PSU_APM_0_ENABLE_EVENT_COUNT 1 -#define XPAR_PSU_APM_0_NUM_MONITOR_SLOTS 6 -#define XPAR_PSU_APM_0_NUM_OF_COUNTERS 10 -#define XPAR_PSU_APM_0_HAVE_SAMPLED_METRIC_CNT 1 -#define XPAR_PSU_APM_0_ENABLE_EVENT_LOG 0 -#define XPAR_PSU_APM_0_FIFO_AXIS_DEPTH 32 -#define XPAR_PSU_APM_0_FIFO_AXIS_TDATA_WIDTH 56 -#define XPAR_PSU_APM_0_FIFO_AXIS_TID_WIDTH 1 -#define XPAR_PSU_APM_0_METRIC_COUNT_SCALE 1 -#define XPAR_PSU_APM_0_ENABLE_ADVANCED 1 -#define XPAR_PSU_APM_0_ENABLE_PROFILE 0 -#define XPAR_PSU_APM_0_ENABLE_TRACE 0 -#define XPAR_PSU_APM_0_S_AXI4_BASEADDR 0x00000000 -#define XPAR_PSU_APM_0_S_AXI4_HIGHADDR 0x00000000 -#define XPAR_PSU_APM_0_ENABLE_32BIT_FILTER_ID 1 +#define XPAR_PSU_APM_0_DEVICE_ID 0U +#define XPAR_PSU_APM_0_BASEADDR 0xFD0B0000U +#define XPAR_PSU_APM_0_HIGHADDR 0xFD0BFFFFU +#define XPAR_PSU_APM_0_GLOBAL_COUNT_WIDTH 32U +#define XPAR_PSU_APM_0_METRICS_SAMPLE_COUNT_WIDTH 32U +#define XPAR_PSU_APM_0_ENABLE_EVENT_COUNT 1U +#define XPAR_PSU_APM_0_NUM_MONITOR_SLOTS 6U +#define XPAR_PSU_APM_0_NUM_OF_COUNTERS 10U +#define XPAR_PSU_APM_0_HAVE_SAMPLED_METRIC_CNT 1U +#define XPAR_PSU_APM_0_ENABLE_EVENT_LOG 0U +#define XPAR_PSU_APM_0_FIFO_AXIS_DEPTH 32U +#define XPAR_PSU_APM_0_FIFO_AXIS_TDATA_WIDTH 56U +#define XPAR_PSU_APM_0_FIFO_AXIS_TID_WIDTH 1U +#define XPAR_PSU_APM_0_METRIC_COUNT_SCALE 1U +#define XPAR_PSU_APM_0_ENABLE_ADVANCED 1U +#define XPAR_PSU_APM_0_ENABLE_PROFILE 0U +#define XPAR_PSU_APM_0_ENABLE_TRACE 0U +#define XPAR_PSU_APM_0_S_AXI4_BASEADDR 0x00000000U +#define XPAR_PSU_APM_0_S_AXI4_HIGHADDR 0x00000000U +#define XPAR_PSU_APM_0_ENABLE_32BIT_FILTER_ID 1U /* Definitions for peripheral PSU_APM_1 */ -#define XPAR_PSU_APM_1_DEVICE_ID 1 -#define XPAR_PSU_APM_1_BASEADDR 0xFFA00000 -#define XPAR_PSU_APM_1_HIGHADDR 0xFFA0FFFF -#define XPAR_PSU_APM_1_GLOBAL_COUNT_WIDTH 32 -#define XPAR_PSU_APM_1_METRICS_SAMPLE_COUNT_WIDTH 32 -#define XPAR_PSU_APM_1_ENABLE_EVENT_COUNT 1 -#define XPAR_PSU_APM_1_NUM_MONITOR_SLOTS 1 -#define XPAR_PSU_APM_1_NUM_OF_COUNTERS 3 -#define XPAR_PSU_APM_1_HAVE_SAMPLED_METRIC_CNT 1 -#define XPAR_PSU_APM_1_ENABLE_EVENT_LOG 0 -#define XPAR_PSU_APM_1_FIFO_AXIS_DEPTH 32 -#define XPAR_PSU_APM_1_FIFO_AXIS_TDATA_WIDTH 56 -#define XPAR_PSU_APM_1_FIFO_AXIS_TID_WIDTH 1 -#define XPAR_PSU_APM_1_METRIC_COUNT_SCALE 1 -#define XPAR_PSU_APM_1_ENABLE_ADVANCED 1 -#define XPAR_PSU_APM_1_ENABLE_PROFILE 0 -#define XPAR_PSU_APM_1_ENABLE_TRACE 0 -#define XPAR_PSU_APM_1_S_AXI4_BASEADDR 0x00000000 -#define XPAR_PSU_APM_1_S_AXI4_HIGHADDR 0x00000000 -#define XPAR_PSU_APM_1_ENABLE_32BIT_FILTER_ID 1 +#define XPAR_PSU_APM_1_DEVICE_ID 1U +#define XPAR_PSU_APM_1_BASEADDR 0xFFA00000U +#define XPAR_PSU_APM_1_HIGHADDR 0xFFA0FFFFU +#define XPAR_PSU_APM_1_GLOBAL_COUNT_WIDTH 32U +#define XPAR_PSU_APM_1_METRICS_SAMPLE_COUNT_WIDTH 32U +#define XPAR_PSU_APM_1_ENABLE_EVENT_COUNT 1U +#define XPAR_PSU_APM_1_NUM_MONITOR_SLOTS 1U +#define XPAR_PSU_APM_1_NUM_OF_COUNTERS 3U +#define XPAR_PSU_APM_1_HAVE_SAMPLED_METRIC_CNT 1U +#define XPAR_PSU_APM_1_ENABLE_EVENT_LOG 0U +#define XPAR_PSU_APM_1_FIFO_AXIS_DEPTH 32U +#define XPAR_PSU_APM_1_FIFO_AXIS_TDATA_WIDTH 56U +#define XPAR_PSU_APM_1_FIFO_AXIS_TID_WIDTH 1U +#define XPAR_PSU_APM_1_METRIC_COUNT_SCALE 1U +#define XPAR_PSU_APM_1_ENABLE_ADVANCED 1U +#define XPAR_PSU_APM_1_ENABLE_PROFILE 0U +#define XPAR_PSU_APM_1_ENABLE_TRACE 0U +#define XPAR_PSU_APM_1_S_AXI4_BASEADDR 0x00000000U +#define XPAR_PSU_APM_1_S_AXI4_HIGHADDR 0x00000000U +#define XPAR_PSU_APM_1_ENABLE_32BIT_FILTER_ID 1U /* Definitions for peripheral PSU_APM_2 */ -#define XPAR_PSU_APM_2_DEVICE_ID 2 -#define XPAR_PSU_APM_2_BASEADDR 0xFFA10000 -#define XPAR_PSU_APM_2_HIGHADDR 0xFFA1FFFF -#define XPAR_PSU_APM_2_GLOBAL_COUNT_WIDTH 32 -#define XPAR_PSU_APM_2_METRICS_SAMPLE_COUNT_WIDTH 32 -#define XPAR_PSU_APM_2_ENABLE_EVENT_COUNT 1 -#define XPAR_PSU_APM_2_NUM_MONITOR_SLOTS 1 -#define XPAR_PSU_APM_2_NUM_OF_COUNTERS 3 -#define XPAR_PSU_APM_2_HAVE_SAMPLED_METRIC_CNT 1 -#define XPAR_PSU_APM_2_ENABLE_EVENT_LOG 0 -#define XPAR_PSU_APM_2_FIFO_AXIS_DEPTH 32 -#define XPAR_PSU_APM_2_FIFO_AXIS_TDATA_WIDTH 56 -#define XPAR_PSU_APM_2_FIFO_AXIS_TID_WIDTH 1 -#define XPAR_PSU_APM_2_METRIC_COUNT_SCALE 1 -#define XPAR_PSU_APM_2_ENABLE_ADVANCED 1 -#define XPAR_PSU_APM_2_ENABLE_PROFILE 0 -#define XPAR_PSU_APM_2_ENABLE_TRACE 0 -#define XPAR_PSU_APM_2_S_AXI4_BASEADDR 0x00000000 -#define XPAR_PSU_APM_2_S_AXI4_HIGHADDR 0x00000000 -#define XPAR_PSU_APM_2_ENABLE_32BIT_FILTER_ID 1 +#define XPAR_PSU_APM_2_DEVICE_ID 2U +#define XPAR_PSU_APM_2_BASEADDR 0xFFA10000U +#define XPAR_PSU_APM_2_HIGHADDR 0xFFA1FFFFU +#define XPAR_PSU_APM_2_GLOBAL_COUNT_WIDTH 32U +#define XPAR_PSU_APM_2_METRICS_SAMPLE_COUNT_WIDTH 32U +#define XPAR_PSU_APM_2_ENABLE_EVENT_COUNT 1U +#define XPAR_PSU_APM_2_NUM_MONITOR_SLOTS 1U +#define XPAR_PSU_APM_2_NUM_OF_COUNTERS 3U +#define XPAR_PSU_APM_2_HAVE_SAMPLED_METRIC_CNT 1U +#define XPAR_PSU_APM_2_ENABLE_EVENT_LOG 0U +#define XPAR_PSU_APM_2_FIFO_AXIS_DEPTH 32U +#define XPAR_PSU_APM_2_FIFO_AXIS_TDATA_WIDTH 56U +#define XPAR_PSU_APM_2_FIFO_AXIS_TID_WIDTH 1U +#define XPAR_PSU_APM_2_METRIC_COUNT_SCALE 1U +#define XPAR_PSU_APM_2_ENABLE_ADVANCED 1U +#define XPAR_PSU_APM_2_ENABLE_PROFILE 0U +#define XPAR_PSU_APM_2_ENABLE_TRACE 0U +#define XPAR_PSU_APM_2_S_AXI4_BASEADDR 0x00000000U +#define XPAR_PSU_APM_2_S_AXI4_HIGHADDR 0x00000000U +#define XPAR_PSU_APM_2_ENABLE_32BIT_FILTER_ID 1U /* Definitions for peripheral PSU_APM_5 */ -#define XPAR_PSU_APM_5_DEVICE_ID 3 -#define XPAR_PSU_APM_5_BASEADDR 0xFD490000 -#define XPAR_PSU_APM_5_HIGHADDR 0xFD49FFFF -#define XPAR_PSU_APM_5_GLOBAL_COUNT_WIDTH 32 -#define XPAR_PSU_APM_5_METRICS_SAMPLE_COUNT_WIDTH 32 -#define XPAR_PSU_APM_5_ENABLE_EVENT_COUNT 1 -#define XPAR_PSU_APM_5_NUM_MONITOR_SLOTS 1 -#define XPAR_PSU_APM_5_NUM_OF_COUNTERS 3 -#define XPAR_PSU_APM_5_HAVE_SAMPLED_METRIC_CNT 1 -#define XPAR_PSU_APM_5_ENABLE_EVENT_LOG 0 -#define XPAR_PSU_APM_5_FIFO_AXIS_DEPTH 32 -#define XPAR_PSU_APM_5_FIFO_AXIS_TDATA_WIDTH 56 -#define XPAR_PSU_APM_5_FIFO_AXIS_TID_WIDTH 1 -#define XPAR_PSU_APM_5_METRIC_COUNT_SCALE 1 -#define XPAR_PSU_APM_5_ENABLE_ADVANCED 1 -#define XPAR_PSU_APM_5_ENABLE_PROFILE 0 -#define XPAR_PSU_APM_5_ENABLE_TRACE 0 -#define XPAR_PSU_APM_5_S_AXI4_BASEADDR 0x00000000 -#define XPAR_PSU_APM_5_S_AXI4_HIGHADDR 0x00000000 -#define XPAR_PSU_APM_5_ENABLE_32BIT_FILTER_ID 1 +#define XPAR_PSU_APM_5_DEVICE_ID 3U +#define XPAR_PSU_APM_5_BASEADDR 0xFD490000U +#define XPAR_PSU_APM_5_HIGHADDR 0xFD49FFFFU +#define XPAR_PSU_APM_5_GLOBAL_COUNT_WIDTH 32U +#define XPAR_PSU_APM_5_METRICS_SAMPLE_COUNT_WIDTH 32U +#define XPAR_PSU_APM_5_ENABLE_EVENT_COUNT 1U +#define XPAR_PSU_APM_5_NUM_MONITOR_SLOTS 1U +#define XPAR_PSU_APM_5_NUM_OF_COUNTERS 3U +#define XPAR_PSU_APM_5_HAVE_SAMPLED_METRIC_CNT 1U +#define XPAR_PSU_APM_5_ENABLE_EVENT_LOG 0U +#define XPAR_PSU_APM_5_FIFO_AXIS_DEPTH 32U +#define XPAR_PSU_APM_5_FIFO_AXIS_TDATA_WIDTH 56U +#define XPAR_PSU_APM_5_FIFO_AXIS_TID_WIDTH 1U +#define XPAR_PSU_APM_5_METRIC_COUNT_SCALE 1U +#define XPAR_PSU_APM_5_ENABLE_ADVANCED 1U +#define XPAR_PSU_APM_5_ENABLE_PROFILE 0U +#define XPAR_PSU_APM_5_ENABLE_TRACE 0U +#define XPAR_PSU_APM_5_S_AXI4_BASEADDR 0x00000000U +#define XPAR_PSU_APM_5_S_AXI4_HIGHADDR 0x00000000U +#define XPAR_PSU_APM_5_ENABLE_32BIT_FILTER_ID 1U /******************************************************************/ /* Canonical definitions for peripheral PSU_APM_0 */ #define XPAR_AXIPMON_0_DEVICE_ID XPAR_PSU_APM_0_DEVICE_ID -#define XPAR_AXIPMON_0_BASEADDR 0xFD0B0000 -#define XPAR_AXIPMON_0_HIGHADDR 0xFD0BFFFF -#define XPAR_AXIPMON_0_GLOBAL_COUNT_WIDTH 32 -#define XPAR_AXIPMON_0_METRICS_SAMPLE_COUNT_WIDTH 32 -#define XPAR_AXIPMON_0_ENABLE_EVENT_COUNT 1 -#define XPAR_AXIPMON_0_NUM_MONITOR_SLOTS 6 -#define XPAR_AXIPMON_0_NUM_OF_COUNTERS 10 -#define XPAR_AXIPMON_0_HAVE_SAMPLED_METRIC_CNT 1 -#define XPAR_AXIPMON_0_ENABLE_EVENT_LOG 0 -#define XPAR_AXIPMON_0_FIFO_AXIS_DEPTH 32 -#define XPAR_AXIPMON_0_FIFO_AXIS_TDATA_WIDTH 56 -#define XPAR_AXIPMON_0_FIFO_AXIS_TID_WIDTH 1 -#define XPAR_AXIPMON_0_METRIC_COUNT_SCALE 1 -#define XPAR_AXIPMON_0_ENABLE_ADVANCED 1 -#define XPAR_AXIPMON_0_ENABLE_PROFILE 0 -#define XPAR_AXIPMON_0_ENABLE_TRACE 0 -#define XPAR_AXIPMON_0_S_AXI4_BASEADDR 0x00000000 -#define XPAR_AXIPMON_0_S_AXI4_HIGHADDR 0x00000000 -#define XPAR_AXIPMON_0_ENABLE_32BIT_FILTER_ID 1 +#define XPAR_AXIPMON_0_BASEADDR 0xFD0B0000U +#define XPAR_AXIPMON_0_HIGHADDR 0xFD0BFFFFU +#define XPAR_AXIPMON_0_GLOBAL_COUNT_WIDTH 32U +#define XPAR_AXIPMON_0_METRICS_SAMPLE_COUNT_WIDTH 32U +#define XPAR_AXIPMON_0_ENABLE_EVENT_COUNT 1U +#define XPAR_AXIPMON_0_NUM_MONITOR_SLOTS 6U +#define XPAR_AXIPMON_0_NUM_OF_COUNTERS 10U +#define XPAR_AXIPMON_0_HAVE_SAMPLED_METRIC_CNT 1U +#define XPAR_AXIPMON_0_ENABLE_EVENT_LOG 0U +#define XPAR_AXIPMON_0_FIFO_AXIS_DEPTH 32U +#define XPAR_AXIPMON_0_FIFO_AXIS_TDATA_WIDTH 56U +#define XPAR_AXIPMON_0_FIFO_AXIS_TID_WIDTH 1U +#define XPAR_AXIPMON_0_METRIC_COUNT_SCALE 1U +#define XPAR_AXIPMON_0_ENABLE_ADVANCED 1U +#define XPAR_AXIPMON_0_ENABLE_PROFILE 0U +#define XPAR_AXIPMON_0_ENABLE_TRACE 0U +#define XPAR_AXIPMON_0_S_AXI4_BASEADDR 0x00000000U +#define XPAR_AXIPMON_0_S_AXI4_HIGHADDR 0x00000000U +#define XPAR_AXIPMON_0_ENABLE_32BIT_FILTER_ID 1U /* Canonical definitions for peripheral PSU_APM_1 */ #define XPAR_AXIPMON_1_DEVICE_ID XPAR_PSU_APM_1_DEVICE_ID -#define XPAR_AXIPMON_1_BASEADDR 0xFFA00000 -#define XPAR_AXIPMON_1_HIGHADDR 0xFFA0FFFF -#define XPAR_AXIPMON_1_GLOBAL_COUNT_WIDTH 32 -#define XPAR_AXIPMON_1_METRICS_SAMPLE_COUNT_WIDTH 32 -#define XPAR_AXIPMON_1_ENABLE_EVENT_COUNT 1 -#define XPAR_AXIPMON_1_NUM_MONITOR_SLOTS 1 -#define XPAR_AXIPMON_1_NUM_OF_COUNTERS 3 -#define XPAR_AXIPMON_1_HAVE_SAMPLED_METRIC_CNT 1 -#define XPAR_AXIPMON_1_ENABLE_EVENT_LOG 0 -#define XPAR_AXIPMON_1_FIFO_AXIS_DEPTH 32 -#define XPAR_AXIPMON_1_FIFO_AXIS_TDATA_WIDTH 56 -#define XPAR_AXIPMON_1_FIFO_AXIS_TID_WIDTH 1 -#define XPAR_AXIPMON_1_METRIC_COUNT_SCALE 1 -#define XPAR_AXIPMON_1_ENABLE_ADVANCED 1 -#define XPAR_AXIPMON_1_ENABLE_PROFILE 0 -#define XPAR_AXIPMON_1_ENABLE_TRACE 0 -#define XPAR_AXIPMON_1_S_AXI4_BASEADDR 0x00000000 -#define XPAR_AXIPMON_1_S_AXI4_HIGHADDR 0x00000000 -#define XPAR_AXIPMON_1_ENABLE_32BIT_FILTER_ID 1 +#define XPAR_AXIPMON_1_BASEADDR 0xFFA00000U +#define XPAR_AXIPMON_1_HIGHADDR 0xFFA0FFFFU +#define XPAR_AXIPMON_1_GLOBAL_COUNT_WIDTH 32U +#define XPAR_AXIPMON_1_METRICS_SAMPLE_COUNT_WIDTH 32U +#define XPAR_AXIPMON_1_ENABLE_EVENT_COUNT 1U +#define XPAR_AXIPMON_1_NUM_MONITOR_SLOTS 1U +#define XPAR_AXIPMON_1_NUM_OF_COUNTERS 3U +#define XPAR_AXIPMON_1_HAVE_SAMPLED_METRIC_CNT 1U +#define XPAR_AXIPMON_1_ENABLE_EVENT_LOG 0U +#define XPAR_AXIPMON_1_FIFO_AXIS_DEPTH 32U +#define XPAR_AXIPMON_1_FIFO_AXIS_TDATA_WIDTH 56U +#define XPAR_AXIPMON_1_FIFO_AXIS_TID_WIDTH 1U +#define XPAR_AXIPMON_1_METRIC_COUNT_SCALE 1U +#define XPAR_AXIPMON_1_ENABLE_ADVANCED 1U +#define XPAR_AXIPMON_1_ENABLE_PROFILE 0U +#define XPAR_AXIPMON_1_ENABLE_TRACE 0U +#define XPAR_AXIPMON_1_S_AXI4_BASEADDR 0x00000000U +#define XPAR_AXIPMON_1_S_AXI4_HIGHADDR 0x00000000U +#define XPAR_AXIPMON_1_ENABLE_32BIT_FILTER_ID 1U /* Canonical definitions for peripheral PSU_APM_2 */ #define XPAR_AXIPMON_2_DEVICE_ID XPAR_PSU_APM_2_DEVICE_ID -#define XPAR_AXIPMON_2_BASEADDR 0xFFA10000 -#define XPAR_AXIPMON_2_HIGHADDR 0xFFA1FFFF -#define XPAR_AXIPMON_2_GLOBAL_COUNT_WIDTH 32 -#define XPAR_AXIPMON_2_METRICS_SAMPLE_COUNT_WIDTH 32 -#define XPAR_AXIPMON_2_ENABLE_EVENT_COUNT 1 -#define XPAR_AXIPMON_2_NUM_MONITOR_SLOTS 1 -#define XPAR_AXIPMON_2_NUM_OF_COUNTERS 3 -#define XPAR_AXIPMON_2_HAVE_SAMPLED_METRIC_CNT 1 -#define XPAR_AXIPMON_2_ENABLE_EVENT_LOG 0 -#define XPAR_AXIPMON_2_FIFO_AXIS_DEPTH 32 -#define XPAR_AXIPMON_2_FIFO_AXIS_TDATA_WIDTH 56 -#define XPAR_AXIPMON_2_FIFO_AXIS_TID_WIDTH 1 -#define XPAR_AXIPMON_2_METRIC_COUNT_SCALE 1 -#define XPAR_AXIPMON_2_ENABLE_ADVANCED 1 -#define XPAR_AXIPMON_2_ENABLE_PROFILE 0 -#define XPAR_AXIPMON_2_ENABLE_TRACE 0 -#define XPAR_AXIPMON_2_S_AXI4_BASEADDR 0x00000000 -#define XPAR_AXIPMON_2_S_AXI4_HIGHADDR 0x00000000 -#define XPAR_AXIPMON_2_ENABLE_32BIT_FILTER_ID 1 +#define XPAR_AXIPMON_2_BASEADDR 0xFFA10000U +#define XPAR_AXIPMON_2_HIGHADDR 0xFFA1FFFFU +#define XPAR_AXIPMON_2_GLOBAL_COUNT_WIDTH 32U +#define XPAR_AXIPMON_2_METRICS_SAMPLE_COUNT_WIDTH 32U +#define XPAR_AXIPMON_2_ENABLE_EVENT_COUNT 1U +#define XPAR_AXIPMON_2_NUM_MONITOR_SLOTS 1U +#define XPAR_AXIPMON_2_NUM_OF_COUNTERS 3U +#define XPAR_AXIPMON_2_HAVE_SAMPLED_METRIC_CNT 1U +#define XPAR_AXIPMON_2_ENABLE_EVENT_LOG 0U +#define XPAR_AXIPMON_2_FIFO_AXIS_DEPTH 32U +#define XPAR_AXIPMON_2_FIFO_AXIS_TDATA_WIDTH 56U +#define XPAR_AXIPMON_2_FIFO_AXIS_TID_WIDTH 1U +#define XPAR_AXIPMON_2_METRIC_COUNT_SCALE 1U +#define XPAR_AXIPMON_2_ENABLE_ADVANCED 1U +#define XPAR_AXIPMON_2_ENABLE_PROFILE 0U +#define XPAR_AXIPMON_2_ENABLE_TRACE 0U +#define XPAR_AXIPMON_2_S_AXI4_BASEADDR 0x00000000U +#define XPAR_AXIPMON_2_S_AXI4_HIGHADDR 0x00000000U +#define XPAR_AXIPMON_2_ENABLE_32BIT_FILTER_ID 1U /* Canonical definitions for peripheral PSU_APM_5 */ #define XPAR_AXIPMON_3_DEVICE_ID XPAR_PSU_APM_5_DEVICE_ID -#define XPAR_AXIPMON_3_BASEADDR 0xFD490000 -#define XPAR_AXIPMON_3_HIGHADDR 0xFD49FFFF -#define XPAR_AXIPMON_3_GLOBAL_COUNT_WIDTH 32 -#define XPAR_AXIPMON_3_METRICS_SAMPLE_COUNT_WIDTH 32 -#define XPAR_AXIPMON_3_ENABLE_EVENT_COUNT 1 -#define XPAR_AXIPMON_3_NUM_MONITOR_SLOTS 1 -#define XPAR_AXIPMON_3_NUM_OF_COUNTERS 3 -#define XPAR_AXIPMON_3_HAVE_SAMPLED_METRIC_CNT 1 -#define XPAR_AXIPMON_3_ENABLE_EVENT_LOG 0 -#define XPAR_AXIPMON_3_FIFO_AXIS_DEPTH 32 -#define XPAR_AXIPMON_3_FIFO_AXIS_TDATA_WIDTH 56 -#define XPAR_AXIPMON_3_FIFO_AXIS_TID_WIDTH 1 -#define XPAR_AXIPMON_3_METRIC_COUNT_SCALE 1 -#define XPAR_AXIPMON_3_ENABLE_ADVANCED 1 -#define XPAR_AXIPMON_3_ENABLE_PROFILE 0 -#define XPAR_AXIPMON_3_ENABLE_TRACE 0 -#define XPAR_AXIPMON_3_S_AXI4_BASEADDR 0x00000000 -#define XPAR_AXIPMON_3_S_AXI4_HIGHADDR 0x00000000 -#define XPAR_AXIPMON_3_ENABLE_32BIT_FILTER_ID 1 +#define XPAR_AXIPMON_3_BASEADDR 0xFD490000U +#define XPAR_AXIPMON_3_HIGHADDR 0xFD49FFFFU +#define XPAR_AXIPMON_3_GLOBAL_COUNT_WIDTH 32U +#define XPAR_AXIPMON_3_METRICS_SAMPLE_COUNT_WIDTH 32U +#define XPAR_AXIPMON_3_ENABLE_EVENT_COUNT 1U +#define XPAR_AXIPMON_3_NUM_MONITOR_SLOTS 1U +#define XPAR_AXIPMON_3_NUM_OF_COUNTERS 3U +#define XPAR_AXIPMON_3_HAVE_SAMPLED_METRIC_CNT 1U +#define XPAR_AXIPMON_3_ENABLE_EVENT_LOG 0U +#define XPAR_AXIPMON_3_FIFO_AXIS_DEPTH 32U +#define XPAR_AXIPMON_3_FIFO_AXIS_TDATA_WIDTH 56U +#define XPAR_AXIPMON_3_FIFO_AXIS_TID_WIDTH 1U +#define XPAR_AXIPMON_3_METRIC_COUNT_SCALE 1U +#define XPAR_AXIPMON_3_ENABLE_ADVANCED 1U +#define XPAR_AXIPMON_3_ENABLE_PROFILE 0U +#define XPAR_AXIPMON_3_ENABLE_TRACE 0U +#define XPAR_AXIPMON_3_S_AXI4_BASEADDR 0x00000000U +#define XPAR_AXIPMON_3_S_AXI4_HIGHADDR 0x00000000U +#define XPAR_AXIPMON_3_ENABLE_32BIT_FILTER_ID 1U /******************************************************************/ @@ -226,7 +256,7 @@ #define XPAR_PSU_CAN_1_DEVICE_ID 0 #define XPAR_PSU_CAN_1_BASEADDR 0xFF070000 #define XPAR_PSU_CAN_1_HIGHADDR 0xFF07FFFF -#define XPAR_PSU_CAN_1_CAN_CLK_FREQ_HZ 99998999 +#define XPAR_PSU_CAN_1_CAN_CLK_FREQ_HZ 99990000 /******************************************************************/ @@ -235,7 +265,7 @@ #define XPAR_XCANPS_0_DEVICE_ID XPAR_PSU_CAN_1_DEVICE_ID #define XPAR_XCANPS_0_BASEADDR 0xFF070000 #define XPAR_XCANPS_0_HIGHADDR 0xFF07FFFF -#define XPAR_XCANPS_0_CAN_CLK_FREQ_HZ 99998999 +#define XPAR_XCANPS_0_CAN_CLK_FREQ_HZ 99990000 /******************************************************************/ @@ -269,7 +299,7 @@ #define XPAR_PSU_DDRC_0_BASEADDR 0xFD070000 #define XPAR_PSU_DDRC_0_HIGHADDR 0xFD070FFF #define XPAR_PSU_DDRC_0_HAS_ECC 0 -#define XPAR_PSU_DDRC_0_DDRC_CLK_FREQ_HZ 533328002 +#define XPAR_PSU_DDRC_0_DDRC_CLK_FREQ_HZ 533280000 /******************************************************************/ @@ -278,7 +308,26 @@ #define XPAR_DDRCPSU_0_DEVICE_ID XPAR_PSU_DDRC_0_DEVICE_ID #define XPAR_DDRCPSU_0_BASEADDR 0xFD070000 #define XPAR_DDRCPSU_0_HIGHADDR 0xFD070FFF -#define XPAR_DDRCPSU_0_DDRC_CLK_FREQ_HZ 533328002 +#define XPAR_DDRCPSU_0_DDRC_CLK_FREQ_HZ 533280000 + + +/******************************************************************/ + +/* Definitions for driver DPDMA */ +#define XPAR_XDPDMA_NUM_INSTANCES 1 + +/* Definitions for peripheral PSU_DPDMA */ +#define XPAR_PSU_DPDMA_DEVICE_ID 0 +#define XPAR_PSU_DPDMA_BASEADDR 0xFD4C0000 +#define XPAR_PSU_DPDMA_HIGHADDR 0xFD4CFFFF + + +/******************************************************************/ + +/* Canonical definitions for peripheral PSU_DPDMA */ +#define XPAR_XDPDMA_0_DEVICE_ID XPAR_PSU_DPDMA_DEVICE_ID +#define XPAR_XDPDMA_0_BASEADDR 0xFD4C0000 +#define XPAR_XDPDMA_0_HIGHADDR 0xFD4CFFFF /******************************************************************/ @@ -290,28 +339,31 @@ #define XPAR_PSU_ETHERNET_3_DEVICE_ID 0 #define XPAR_PSU_ETHERNET_3_BASEADDR 0xFF0E0000 #define XPAR_PSU_ETHERNET_3_HIGHADDR 0xFF0EFFFF -#define XPAR_PSU_ETHERNET_3_ENET_CLK_FREQ_HZ 124998749 +#define XPAR_PSU_ETHERNET_3_ENET_CLK_FREQ_HZ 124987500 #define XPAR_PSU_ETHERNET_3_ENET_SLCR_1000MBPS_DIV0 12 #define XPAR_PSU_ETHERNET_3_ENET_SLCR_1000MBPS_DIV1 1 #define XPAR_PSU_ETHERNET_3_ENET_SLCR_100MBPS_DIV0 60 #define XPAR_PSU_ETHERNET_3_ENET_SLCR_100MBPS_DIV1 1 #define XPAR_PSU_ETHERNET_3_ENET_SLCR_10MBPS_DIV0 60 #define XPAR_PSU_ETHERNET_3_ENET_SLCR_10MBPS_DIV1 10 +#define XPAR_PSU_ETHERNET_3_ENET_TSU_CLK_FREQ_HZ 249975000 /******************************************************************/ +#define XPAR_PSU_ETHERNET_3_IS_CACHE_COHERENT 0 /* Canonical definitions for peripheral PSU_ETHERNET_3 */ #define XPAR_XEMACPS_0_DEVICE_ID XPAR_PSU_ETHERNET_3_DEVICE_ID #define XPAR_XEMACPS_0_BASEADDR 0xFF0E0000 #define XPAR_XEMACPS_0_HIGHADDR 0xFF0EFFFF -#define XPAR_XEMACPS_0_ENET_CLK_FREQ_HZ 124998749 +#define XPAR_XEMACPS_0_ENET_CLK_FREQ_HZ 124987500 #define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV0 12 #define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV1 1 #define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV0 60 #define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV1 1 #define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV0 60 #define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV1 10 +#define XPAR_XEMACPS_0_ENET_TSU_CLK_FREQ_HZ 249975000 /******************************************************************/ @@ -367,24 +419,24 @@ #define XPAR_PSU_CCI_REG_S_AXI_HIGHADDR 0xFD5EFFFF -/* Definitions for peripheral PSU_CRF_APB */ -#define XPAR_PSU_CRF_APB_S_AXI_BASEADDR 0xFD1A0000 -#define XPAR_PSU_CRF_APB_S_AXI_HIGHADDR 0xFD2DFFFF - - /* Definitions for peripheral PSU_CRL_APB */ #define XPAR_PSU_CRL_APB_S_AXI_BASEADDR 0xFF5E0000 #define XPAR_PSU_CRL_APB_S_AXI_HIGHADDR 0xFF85FFFF +/* Definitions for peripheral PSU_CTRL_IPI */ +#define XPAR_PSU_CTRL_IPI_S_AXI_BASEADDR 0xFF380000 +#define XPAR_PSU_CTRL_IPI_S_AXI_HIGHADDR 0xFF3FFFFF + + /* Definitions for peripheral PSU_DDR_0 */ #define XPAR_PSU_DDR_0_S_AXI_BASEADDR 0x00000000 -#define XPAR_PSU_DDR_0_S_AXI_HIGHADDR 0xFFFFFFFF +#define XPAR_PSU_DDR_0_S_AXI_HIGHADDR 0x7FFFFFFF /* Definitions for peripheral PSU_DDR_1 */ -#define XPAR_PSU_DDR_1_S_AXI_BASEADDR 0x00000000 -#define XPAR_PSU_DDR_1_S_AXI_HIGHADDR 0x7FFFFFFF +#define XPAR_PSU_DDR_1_S_AXI_BASEADDR 0x800000000 +#define XPAR_PSU_DDR_1_S_AXI_HIGHADDR 0x87FFFFFFF /* Definitions for peripheral PSU_DDR_PHY */ @@ -427,16 +479,6 @@ #define XPAR_PSU_DDR_XMPU5_CFG_S_AXI_HIGHADDR 0xFD05FFFF -/* Definitions for peripheral PSU_DP */ -#define XPAR_PSU_DP_S_AXI_BASEADDR 0xFD4A0000 -#define XPAR_PSU_DP_S_AXI_HIGHADDR 0xFD4AFFFF - - -/* Definitions for peripheral PSU_DPDMA */ -#define XPAR_PSU_DPDMA_S_AXI_BASEADDR 0xFD4C0000 -#define XPAR_PSU_DPDMA_S_AXI_HIGHADDR 0xFD4CFFFF - - /* Definitions for peripheral PSU_EFUSE */ #define XPAR_PSU_EFUSE_S_AXI_BASEADDR 0xFFCC0000 #define XPAR_PSU_EFUSE_S_AXI_HIGHADDR 0xFFCCFFFF @@ -517,6 +559,11 @@ #define XPAR_PSU_MBISTJTAG_S_AXI_HIGHADDR 0xFFCFFFFF +/* Definitions for peripheral PSU_MESSAGE_BUFFERS */ +#define XPAR_PSU_MESSAGE_BUFFERS_S_AXI_BASEADDR 0xFF990000 +#define XPAR_PSU_MESSAGE_BUFFERS_S_AXI_HIGHADDR 0xFF99FFFF + + /* Definitions for peripheral PSU_OCM */ #define XPAR_PSU_OCM_S_AXI_BASEADDR 0xFF960000 #define XPAR_PSU_OCM_S_AXI_HIGHADDR 0xFF96FFFF @@ -524,7 +571,7 @@ /* Definitions for peripheral PSU_OCM_RAM_0 */ #define XPAR_PSU_OCM_RAM_0_S_AXI_BASEADDR 0xFFFC0000 -#define XPAR_PSU_OCM_RAM_0_S_AXI_HIGHADDR 0xFFFEFFFF +#define XPAR_PSU_OCM_RAM_0_S_AXI_HIGHADDR 0xFFFFFFFF /* Definitions for peripheral PSU_OCM_XMPU_CFG */ @@ -547,9 +594,14 @@ #define XPAR_PSU_PCIE_DMA_S_AXI_HIGHADDR 0xFD0FFFFF -/* Definitions for peripheral PSU_PCIE_HIGH */ -#define XPAR_PSU_PCIE_HIGH_S_AXI_BASEADDR 0x00000000 -#define XPAR_PSU_PCIE_HIGH_S_AXI_HIGHADDR 0xFFFFFFFF +/* Definitions for peripheral PSU_PCIE_HIGH1 */ +#define XPAR_PSU_PCIE_HIGH1_S_AXI_BASEADDR 0x600000000 +#define XPAR_PSU_PCIE_HIGH1_S_AXI_HIGHADDR 0x7FFFFFFFF + + +/* Definitions for peripheral PSU_PCIE_HIGH2 */ +#define XPAR_PSU_PCIE_HIGH2_S_AXI_BASEADDR 0x8000000000 +#define XPAR_PSU_PCIE_HIGH2_S_AXI_HIGHADDR 0xBFFFFFFFFF /* Definitions for peripheral PSU_PCIE_LOW */ @@ -562,11 +614,6 @@ #define XPAR_PSU_PMU_GLOBAL_0_S_AXI_HIGHADDR 0xFFDBFFFF -/* Definitions for peripheral PSU_PMU_IOMODULE */ -#define XPAR_PSU_PMU_IOMODULE_S_AXI_BASEADDR 0xFFD40000 -#define XPAR_PSU_PMU_IOMODULE_S_AXI_HIGHADDR 0xFFD5FFFF - - /* Definitions for peripheral PSU_QSPI_LINEAR_0 */ #define XPAR_PSU_QSPI_LINEAR_0_S_AXI_BASEADDR 0xC0000000 #define XPAR_PSU_QSPI_LINEAR_0_S_AXI_HIGHADDR 0xDFFFFFFF @@ -632,6 +679,11 @@ #define XPAR_PSU_SMMU_REG_S_AXI_HIGHADDR 0xFD5FFFFF +/* Definitions for peripheral PSU_USB_0 */ +#define XPAR_PSU_USB_0_S_AXI_BASEADDR 0xFF9D0000 +#define XPAR_PSU_USB_0_S_AXI_HIGHADDR 0xFF9DFFFF + + /******************************************************************/ /* Definitions for driver GPIOPS */ @@ -660,14 +712,14 @@ #define XPAR_PSU_I2C_0_DEVICE_ID 0 #define XPAR_PSU_I2C_0_BASEADDR 0xFF020000 #define XPAR_PSU_I2C_0_HIGHADDR 0xFF02FFFF -#define XPAR_PSU_I2C_0_I2C_CLK_FREQ_HZ 99998999 +#define XPAR_PSU_I2C_0_I2C_CLK_FREQ_HZ 99990000 /* Definitions for peripheral PSU_I2C_1 */ #define XPAR_PSU_I2C_1_DEVICE_ID 1 #define XPAR_PSU_I2C_1_BASEADDR 0xFF030000 #define XPAR_PSU_I2C_1_HIGHADDR 0xFF03FFFF -#define XPAR_PSU_I2C_1_I2C_CLK_FREQ_HZ 99998999 +#define XPAR_PSU_I2C_1_I2C_CLK_FREQ_HZ 99990000 /******************************************************************/ @@ -676,25 +728,25 @@ #define XPAR_XIICPS_0_DEVICE_ID XPAR_PSU_I2C_0_DEVICE_ID #define XPAR_XIICPS_0_BASEADDR 0xFF020000 #define XPAR_XIICPS_0_HIGHADDR 0xFF02FFFF -#define XPAR_XIICPS_0_I2C_CLK_FREQ_HZ 99998999 +#define XPAR_XIICPS_0_I2C_CLK_FREQ_HZ 99990000 /* Canonical definitions for peripheral PSU_I2C_1 */ #define XPAR_XIICPS_1_DEVICE_ID XPAR_PSU_I2C_1_DEVICE_ID #define XPAR_XIICPS_1_BASEADDR 0xFF030000 #define XPAR_XIICPS_1_HIGHADDR 0xFF03FFFF -#define XPAR_XIICPS_1_I2C_CLK_FREQ_HZ 99998999 +#define XPAR_XIICPS_1_I2C_CLK_FREQ_HZ 99990000 /******************************************************************/ -#define XPAR_XIPIPSU_NUM_INSTANCES 1 +#define XPAR_XIPIPSU_NUM_INSTANCES 1U /* Parameter definitions for peripheral psu_ipi_0 */ -#define XPAR_PSU_IPI_0_DEVICE_ID 0 -#define XPAR_PSU_IPI_0_BASE_ADDRESS 0xFF300000 -#define XPAR_PSU_IPI_0_BIT_MASK 0x00000001 -#define XPAR_PSU_IPI_0_BUFFER_INDEX 2 -#define XPAR_PSU_IPI_0_INT_ID 67 +#define XPAR_PSU_IPI_0_DEVICE_ID 0U +#define XPAR_PSU_IPI_0_BASE_ADDRESS 0xFF300000U +#define XPAR_PSU_IPI_0_BIT_MASK 0x00000001U +#define XPAR_PSU_IPI_0_BUFFER_INDEX 2U +#define XPAR_PSU_IPI_0_INT_ID 67U /* Canonical definitions for peripheral psu_ipi_0 */ #define XPAR_XIPIPSU_0_DEVICE_ID XPAR_PSU_IPI_0_DEVICE_ID @@ -703,58 +755,50 @@ #define XPAR_XIPIPSU_0_BUFFER_INDEX XPAR_PSU_IPI_0_BUFFER_INDEX #define XPAR_XIPIPSU_0_INT_ID XPAR_PSU_IPI_0_INT_ID -#define XPAR_XIPIPSU_NUM_TARGETS 11 +#define XPAR_XIPIPSU_NUM_TARGETS 7U -#define XPAR_PSU_IPI_0_BIT_MASK 0x00000001 -#define XPAR_PSU_IPI_0_BUFFER_INDEX 2 -#define XPAR_PSU_IPI_1_BIT_MASK 0x00000100 -#define XPAR_PSU_IPI_1_BUFFER_INDEX 0 -#define XPAR_PSU_IPI_2_BIT_MASK 0x00000200 -#define XPAR_PSU_IPI_2_BUFFER_INDEX 1 -#define XPAR_PSU_IPI_3_BIT_MASK 0x00010000 -#define XPAR_PSU_IPI_3_BUFFER_INDEX 7 -#define XPAR_PSU_IPI_4_BIT_MASK 0x00020000 -#define XPAR_PSU_IPI_4_BUFFER_INDEX 7 -#define XPAR_PSU_IPI_5_BIT_MASK 0x00040000 -#define XPAR_PSU_IPI_5_BUFFER_INDEX 7 -#define XPAR_PSU_IPI_6_BIT_MASK 0x00080000 -#define XPAR_PSU_IPI_6_BUFFER_INDEX 7 -#define XPAR_PSU_IPI_7_BIT_MASK 0x01000000 -#define XPAR_PSU_IPI_7_BUFFER_INDEX 3 -#define XPAR_PSU_IPI_8_BIT_MASK 0x02000000 -#define XPAR_PSU_IPI_8_BUFFER_INDEX 4 -#define XPAR_PSU_IPI_9_BIT_MASK 0x04000000 -#define XPAR_PSU_IPI_9_BUFFER_INDEX 5 -#define XPAR_PSU_IPI_10_BIT_MASK 0x08000000 -#define XPAR_PSU_IPI_10_BUFFER_INDEX 6 +#define XPAR_PSU_IPI_0_BIT_MASK 0x00000001U +#define XPAR_PSU_IPI_0_BUFFER_INDEX 2U +#define XPAR_PSU_IPI_1_BIT_MASK 0x00000100U +#define XPAR_PSU_IPI_1_BUFFER_INDEX 0U +#define XPAR_PSU_IPI_2_BIT_MASK 0x00000200U +#define XPAR_PSU_IPI_2_BUFFER_INDEX 1U +#define XPAR_PSU_IPI_3_BIT_MASK 0x00010000U +#define XPAR_PSU_IPI_3_BUFFER_INDEX 7U +#define XPAR_PSU_IPI_4_BIT_MASK 0x00020000U +#define XPAR_PSU_IPI_4_BUFFER_INDEX 7U +#define XPAR_PSU_IPI_5_BIT_MASK 0x00040000U +#define XPAR_PSU_IPI_5_BUFFER_INDEX 7U +#define XPAR_PSU_IPI_6_BIT_MASK 0x00080000U +#define XPAR_PSU_IPI_6_BUFFER_INDEX 7U /* Target List for referring to processor IPI Targets */ #define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH0_MASK XPAR_PSU_IPI_0_BIT_MASK -#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH0_INDEX 0 +#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH0_INDEX 0U #define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH0_MASK XPAR_PSU_IPI_0_BIT_MASK -#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH0_INDEX 0 +#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH0_INDEX 0U #define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH0_MASK XPAR_PSU_IPI_0_BIT_MASK -#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH0_INDEX 0 +#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH0_INDEX 0U #define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH0_MASK XPAR_PSU_IPI_0_BIT_MASK -#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH0_INDEX 0 +#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH0_INDEX 0U #define XPAR_XIPIPS_TARGET_PSU_CORTEXR5_0_CH0_MASK XPAR_PSU_IPI_1_BIT_MASK -#define XPAR_XIPIPS_TARGET_PSU_CORTEXR5_0_CH0_INDEX 1 +#define XPAR_XIPIPS_TARGET_PSU_CORTEXR5_0_CH0_INDEX 1U #define XPAR_XIPIPS_TARGET_PSU_CORTEXR5_1_CH0_MASK XPAR_PSU_IPI_2_BIT_MASK -#define XPAR_XIPIPS_TARGET_PSU_CORTEXR5_1_CH0_INDEX 2 +#define XPAR_XIPIPS_TARGET_PSU_CORTEXR5_1_CH0_INDEX 2U #define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH0_MASK XPAR_PSU_IPI_3_BIT_MASK -#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH0_INDEX 3 +#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH0_INDEX 3U #define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH1_MASK XPAR_PSU_IPI_4_BIT_MASK -#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH1_INDEX 4 +#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH1_INDEX 4U #define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH2_MASK XPAR_PSU_IPI_5_BIT_MASK -#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH2_INDEX 5 +#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH2_INDEX 5U #define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH3_MASK XPAR_PSU_IPI_6_BIT_MASK -#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH3_INDEX 6 +#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH3_INDEX 6U /* Definitions for driver QSPIPSU */ #define XPAR_XQSPIPSU_NUM_INSTANCES 1 @@ -763,22 +807,31 @@ #define XPAR_PSU_QSPI_0_DEVICE_ID 0 #define XPAR_PSU_QSPI_0_BASEADDR 0xFF0F0000 #define XPAR_PSU_QSPI_0_HIGHADDR 0xFF0FFFFF -#define XPAR_PSU_QSPI_0_QSPI_CLK_FREQ_HZ 124998749 +#define XPAR_PSU_QSPI_0_QSPI_CLK_FREQ_HZ 124987500 #define XPAR_PSU_QSPI_0_QSPI_MODE 2 #define XPAR_PSU_QSPI_0_QSPI_BUS_WIDTH 2 /******************************************************************/ +#define XPAR_PSU_QSPI_0_IS_CACHE_COHERENT 0 /* Canonical definitions for peripheral PSU_QSPI_0 */ #define XPAR_XQSPIPSU_0_DEVICE_ID XPAR_PSU_QSPI_0_DEVICE_ID #define XPAR_XQSPIPSU_0_BASEADDR 0xFF0F0000 #define XPAR_XQSPIPSU_0_HIGHADDR 0xFF0FFFFF -#define XPAR_XQSPIPSU_0_QSPI_CLK_FREQ_HZ 124998749 +#define XPAR_XQSPIPSU_0_QSPI_CLK_FREQ_HZ 124987500 #define XPAR_XQSPIPSU_0_QSPI_MODE 2 #define XPAR_XQSPIPSU_0_QSPI_BUS_WIDTH 2 +/******************************************************************/ + +/* Definitions for driver RESETPS */ +#define XPAR_XRESETPS_NUM_INSTANCES 1U +/* Definitions for peripheral RESETPS */ +#define XPAR_XRESETPS_DEVICE_ID 0 +#define XPAR_XRESETPS_BASEADDR 0xFFFFFFFFU + /******************************************************************/ /* Definitions for driver RTCPSU */ @@ -801,22 +854,22 @@ /******************************************************************/ /* Definitions for driver SCUGIC */ -#define XPAR_XSCUGIC_NUM_INSTANCES 1 +#define XPAR_XSCUGIC_NUM_INSTANCES 1U /* Definitions for peripheral PSU_ACPU_GIC */ -#define XPAR_PSU_ACPU_GIC_DEVICE_ID 0 -#define XPAR_PSU_ACPU_GIC_BASEADDR 0xF9020000 -#define XPAR_PSU_ACPU_GIC_HIGHADDR 0xF9020FFF -#define XPAR_PSU_ACPU_GIC_DIST_BASEADDR 0xF9010000 +#define XPAR_PSU_ACPU_GIC_DEVICE_ID 0U +#define XPAR_PSU_ACPU_GIC_BASEADDR 0xF9020000U +#define XPAR_PSU_ACPU_GIC_HIGHADDR 0xF9020FFFU +#define XPAR_PSU_ACPU_GIC_DIST_BASEADDR 0xF9010000U /******************************************************************/ /* Canonical definitions for peripheral PSU_ACPU_GIC */ -#define XPAR_SCUGIC_0_DEVICE_ID 0 -#define XPAR_SCUGIC_0_CPU_BASEADDR 0xF9020000 -#define XPAR_SCUGIC_0_CPU_HIGHADDR 0xF9020FFF -#define XPAR_SCUGIC_0_DIST_BASEADDR 0xF9010000 +#define XPAR_SCUGIC_0_DEVICE_ID 0U +#define XPAR_SCUGIC_0_CPU_BASEADDR 0xF9020000U +#define XPAR_SCUGIC_0_CPU_HIGHADDR 0xF9020FFFU +#define XPAR_SCUGIC_0_DIST_BASEADDR 0xF9010000U /******************************************************************/ @@ -828,24 +881,25 @@ #define XPAR_PSU_SD_1_DEVICE_ID 0 #define XPAR_PSU_SD_1_BASEADDR 0xFF170000 #define XPAR_PSU_SD_1_HIGHADDR 0xFF17FFFF -#define XPAR_PSU_SD_1_SDIO_CLK_FREQ_HZ 199998006 +#define XPAR_PSU_SD_1_SDIO_CLK_FREQ_HZ 187481250 #define XPAR_PSU_SD_1_HAS_CD 1 #define XPAR_PSU_SD_1_HAS_WP 1 -#define XPAR_PSU_SD_1_BUS_WIDTH 4 +#define XPAR_PSU_SD_1_BUS_WIDTH 8 #define XPAR_PSU_SD_1_MIO_BANK 1 #define XPAR_PSU_SD_1_HAS_EMIO 0 /******************************************************************/ +#define XPAR_PSU_SD_1_IS_CACHE_COHERENT 0 /* Canonical definitions for peripheral PSU_SD_1 */ #define XPAR_XSDPS_0_DEVICE_ID XPAR_PSU_SD_1_DEVICE_ID #define XPAR_XSDPS_0_BASEADDR 0xFF170000 #define XPAR_XSDPS_0_HIGHADDR 0xFF17FFFF -#define XPAR_XSDPS_0_SDIO_CLK_FREQ_HZ 199998006 +#define XPAR_XSDPS_0_SDIO_CLK_FREQ_HZ 187481250 #define XPAR_XSDPS_0_HAS_CD 1 #define XPAR_XSDPS_0_HAS_WP 1 -#define XPAR_XSDPS_0_BUS_WIDTH 4 +#define XPAR_XSDPS_0_BUS_WIDTH 8 #define XPAR_XSDPS_0_MIO_BANK 1 #define XPAR_XSDPS_0_HAS_EMIO 0 @@ -863,6 +917,7 @@ /******************************************************************/ +#define XPAR_PSU_AMS_REF_FREQMHZ 49.995 /* Canonical definitions for peripheral PSU_AMS */ #define XPAR_XSYSMONPSU_0_DEVICE_ID XPAR_PSU_AMS_DEVICE_ID #define XPAR_XSYSMONPSU_0_BASEADDR 0xFFA50000 @@ -872,133 +927,133 @@ /******************************************************************/ /* Definitions for driver TTCPS */ -#define XPAR_XTTCPS_NUM_INSTANCES 12 +#define XPAR_XTTCPS_NUM_INSTANCES 12U /* Definitions for peripheral PSU_TTC_0 */ -#define XPAR_PSU_TTC_0_DEVICE_ID 0 -#define XPAR_PSU_TTC_0_BASEADDR 0XFF110000 -#define XPAR_PSU_TTC_0_TTC_CLK_FREQ_HZ 100000000 -#define XPAR_PSU_TTC_0_TTC_CLK_CLKSRC 0 -#define XPAR_PSU_TTC_1_DEVICE_ID 1 -#define XPAR_PSU_TTC_1_BASEADDR 0XFF110004 -#define XPAR_PSU_TTC_1_TTC_CLK_FREQ_HZ 100000000 -#define XPAR_PSU_TTC_1_TTC_CLK_CLKSRC 0 -#define XPAR_PSU_TTC_2_DEVICE_ID 2 -#define XPAR_PSU_TTC_2_BASEADDR 0XFF110008 -#define XPAR_PSU_TTC_2_TTC_CLK_FREQ_HZ 100000000 -#define XPAR_PSU_TTC_2_TTC_CLK_CLKSRC 0 +#define XPAR_PSU_TTC_0_DEVICE_ID 0U +#define XPAR_PSU_TTC_0_BASEADDR 0XFF110000U +#define XPAR_PSU_TTC_0_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_PSU_TTC_0_TTC_CLK_CLKSRC 0U +#define XPAR_PSU_TTC_1_DEVICE_ID 1U +#define XPAR_PSU_TTC_1_BASEADDR 0XFF110004U +#define XPAR_PSU_TTC_1_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_PSU_TTC_1_TTC_CLK_CLKSRC 0U +#define XPAR_PSU_TTC_2_DEVICE_ID 2U +#define XPAR_PSU_TTC_2_BASEADDR 0XFF110008U +#define XPAR_PSU_TTC_2_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_PSU_TTC_2_TTC_CLK_CLKSRC 0U /* Definitions for peripheral PSU_TTC_1 */ -#define XPAR_PSU_TTC_3_DEVICE_ID 3 -#define XPAR_PSU_TTC_3_BASEADDR 0XFF120000 -#define XPAR_PSU_TTC_3_TTC_CLK_FREQ_HZ 100000000 -#define XPAR_PSU_TTC_3_TTC_CLK_CLKSRC 0 -#define XPAR_PSU_TTC_4_DEVICE_ID 4 -#define XPAR_PSU_TTC_4_BASEADDR 0XFF120004 -#define XPAR_PSU_TTC_4_TTC_CLK_FREQ_HZ 100000000 -#define XPAR_PSU_TTC_4_TTC_CLK_CLKSRC 0 -#define XPAR_PSU_TTC_5_DEVICE_ID 5 -#define XPAR_PSU_TTC_5_BASEADDR 0XFF120008 -#define XPAR_PSU_TTC_5_TTC_CLK_FREQ_HZ 100000000 -#define XPAR_PSU_TTC_5_TTC_CLK_CLKSRC 0 +#define XPAR_PSU_TTC_3_DEVICE_ID 3U +#define XPAR_PSU_TTC_3_BASEADDR 0XFF120000U +#define XPAR_PSU_TTC_3_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_PSU_TTC_3_TTC_CLK_CLKSRC 0U +#define XPAR_PSU_TTC_4_DEVICE_ID 4U +#define XPAR_PSU_TTC_4_BASEADDR 0XFF120004U +#define XPAR_PSU_TTC_4_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_PSU_TTC_4_TTC_CLK_CLKSRC 0U +#define XPAR_PSU_TTC_5_DEVICE_ID 5U +#define XPAR_PSU_TTC_5_BASEADDR 0XFF120008U +#define XPAR_PSU_TTC_5_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_PSU_TTC_5_TTC_CLK_CLKSRC 0U /* Definitions for peripheral PSU_TTC_2 */ -#define XPAR_PSU_TTC_6_DEVICE_ID 6 -#define XPAR_PSU_TTC_6_BASEADDR 0XFF130000 -#define XPAR_PSU_TTC_6_TTC_CLK_FREQ_HZ 100000000 -#define XPAR_PSU_TTC_6_TTC_CLK_CLKSRC 0 -#define XPAR_PSU_TTC_7_DEVICE_ID 7 -#define XPAR_PSU_TTC_7_BASEADDR 0XFF130004 -#define XPAR_PSU_TTC_7_TTC_CLK_FREQ_HZ 100000000 -#define XPAR_PSU_TTC_7_TTC_CLK_CLKSRC 0 -#define XPAR_PSU_TTC_8_DEVICE_ID 8 -#define XPAR_PSU_TTC_8_BASEADDR 0XFF130008 -#define XPAR_PSU_TTC_8_TTC_CLK_FREQ_HZ 100000000 -#define XPAR_PSU_TTC_8_TTC_CLK_CLKSRC 0 +#define XPAR_PSU_TTC_6_DEVICE_ID 6U +#define XPAR_PSU_TTC_6_BASEADDR 0XFF130000U +#define XPAR_PSU_TTC_6_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_PSU_TTC_6_TTC_CLK_CLKSRC 0U +#define XPAR_PSU_TTC_7_DEVICE_ID 7U +#define XPAR_PSU_TTC_7_BASEADDR 0XFF130004U +#define XPAR_PSU_TTC_7_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_PSU_TTC_7_TTC_CLK_CLKSRC 0U +#define XPAR_PSU_TTC_8_DEVICE_ID 8U +#define XPAR_PSU_TTC_8_BASEADDR 0XFF130008U +#define XPAR_PSU_TTC_8_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_PSU_TTC_8_TTC_CLK_CLKSRC 0U /* Definitions for peripheral PSU_TTC_3 */ -#define XPAR_PSU_TTC_9_DEVICE_ID 9 -#define XPAR_PSU_TTC_9_BASEADDR 0XFF140000 -#define XPAR_PSU_TTC_9_TTC_CLK_FREQ_HZ 100000000 -#define XPAR_PSU_TTC_9_TTC_CLK_CLKSRC 0 -#define XPAR_PSU_TTC_10_DEVICE_ID 10 -#define XPAR_PSU_TTC_10_BASEADDR 0XFF140004 -#define XPAR_PSU_TTC_10_TTC_CLK_FREQ_HZ 100000000 -#define XPAR_PSU_TTC_10_TTC_CLK_CLKSRC 0 -#define XPAR_PSU_TTC_11_DEVICE_ID 11 -#define XPAR_PSU_TTC_11_BASEADDR 0XFF140008 -#define XPAR_PSU_TTC_11_TTC_CLK_FREQ_HZ 100000000 -#define XPAR_PSU_TTC_11_TTC_CLK_CLKSRC 0 +#define XPAR_PSU_TTC_9_DEVICE_ID 9U +#define XPAR_PSU_TTC_9_BASEADDR 0XFF140000U +#define XPAR_PSU_TTC_9_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_PSU_TTC_9_TTC_CLK_CLKSRC 0U +#define XPAR_PSU_TTC_10_DEVICE_ID 10U +#define XPAR_PSU_TTC_10_BASEADDR 0XFF140004U +#define XPAR_PSU_TTC_10_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_PSU_TTC_10_TTC_CLK_CLKSRC 0U +#define XPAR_PSU_TTC_11_DEVICE_ID 11U +#define XPAR_PSU_TTC_11_BASEADDR 0XFF140008U +#define XPAR_PSU_TTC_11_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_PSU_TTC_11_TTC_CLK_CLKSRC 0U /******************************************************************/ /* Canonical definitions for peripheral PSU_TTC_0 */ #define XPAR_XTTCPS_0_DEVICE_ID XPAR_PSU_TTC_0_DEVICE_ID -#define XPAR_XTTCPS_0_BASEADDR 0xFF110000 -#define XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ 100000000 -#define XPAR_XTTCPS_0_TTC_CLK_CLKSRC 0 +#define XPAR_XTTCPS_0_BASEADDR 0xFF110000U +#define XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_XTTCPS_0_TTC_CLK_CLKSRC 0U #define XPAR_XTTCPS_1_DEVICE_ID XPAR_PSU_TTC_1_DEVICE_ID -#define XPAR_XTTCPS_1_BASEADDR 0xFF110004 -#define XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ 100000000 -#define XPAR_XTTCPS_1_TTC_CLK_CLKSRC 0 +#define XPAR_XTTCPS_1_BASEADDR 0xFF110004U +#define XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_XTTCPS_1_TTC_CLK_CLKSRC 0U #define XPAR_XTTCPS_2_DEVICE_ID XPAR_PSU_TTC_2_DEVICE_ID -#define XPAR_XTTCPS_2_BASEADDR 0xFF110008 -#define XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ 100000000 -#define XPAR_XTTCPS_2_TTC_CLK_CLKSRC 0 +#define XPAR_XTTCPS_2_BASEADDR 0xFF110008U +#define XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_XTTCPS_2_TTC_CLK_CLKSRC 0U /* Canonical definitions for peripheral PSU_TTC_1 */ #define XPAR_XTTCPS_3_DEVICE_ID XPAR_PSU_TTC_3_DEVICE_ID -#define XPAR_XTTCPS_3_BASEADDR 0xFF120000 -#define XPAR_XTTCPS_3_TTC_CLK_FREQ_HZ 100000000 -#define XPAR_XTTCPS_3_TTC_CLK_CLKSRC 0 +#define XPAR_XTTCPS_3_BASEADDR 0xFF120000U +#define XPAR_XTTCPS_3_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_XTTCPS_3_TTC_CLK_CLKSRC 0U #define XPAR_XTTCPS_4_DEVICE_ID XPAR_PSU_TTC_4_DEVICE_ID -#define XPAR_XTTCPS_4_BASEADDR 0xFF120004 -#define XPAR_XTTCPS_4_TTC_CLK_FREQ_HZ 100000000 -#define XPAR_XTTCPS_4_TTC_CLK_CLKSRC 0 +#define XPAR_XTTCPS_4_BASEADDR 0xFF120004U +#define XPAR_XTTCPS_4_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_XTTCPS_4_TTC_CLK_CLKSRC 0U #define XPAR_XTTCPS_5_DEVICE_ID XPAR_PSU_TTC_5_DEVICE_ID -#define XPAR_XTTCPS_5_BASEADDR 0xFF120008 -#define XPAR_XTTCPS_5_TTC_CLK_FREQ_HZ 100000000 -#define XPAR_XTTCPS_5_TTC_CLK_CLKSRC 0 +#define XPAR_XTTCPS_5_BASEADDR 0xFF120008U +#define XPAR_XTTCPS_5_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_XTTCPS_5_TTC_CLK_CLKSRC 0U /* Canonical definitions for peripheral PSU_TTC_2 */ #define XPAR_XTTCPS_6_DEVICE_ID XPAR_PSU_TTC_6_DEVICE_ID -#define XPAR_XTTCPS_6_BASEADDR 0xFF130000 -#define XPAR_XTTCPS_6_TTC_CLK_FREQ_HZ 100000000 -#define XPAR_XTTCPS_6_TTC_CLK_CLKSRC 0 +#define XPAR_XTTCPS_6_BASEADDR 0xFF130000U +#define XPAR_XTTCPS_6_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_XTTCPS_6_TTC_CLK_CLKSRC 0U #define XPAR_XTTCPS_7_DEVICE_ID XPAR_PSU_TTC_7_DEVICE_ID -#define XPAR_XTTCPS_7_BASEADDR 0xFF130004 -#define XPAR_XTTCPS_7_TTC_CLK_FREQ_HZ 100000000 -#define XPAR_XTTCPS_7_TTC_CLK_CLKSRC 0 +#define XPAR_XTTCPS_7_BASEADDR 0xFF130004U +#define XPAR_XTTCPS_7_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_XTTCPS_7_TTC_CLK_CLKSRC 0U #define XPAR_XTTCPS_8_DEVICE_ID XPAR_PSU_TTC_8_DEVICE_ID -#define XPAR_XTTCPS_8_BASEADDR 0xFF130008 -#define XPAR_XTTCPS_8_TTC_CLK_FREQ_HZ 100000000 -#define XPAR_XTTCPS_8_TTC_CLK_CLKSRC 0 +#define XPAR_XTTCPS_8_BASEADDR 0xFF130008U +#define XPAR_XTTCPS_8_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_XTTCPS_8_TTC_CLK_CLKSRC 0U /* Canonical definitions for peripheral PSU_TTC_3 */ #define XPAR_XTTCPS_9_DEVICE_ID XPAR_PSU_TTC_9_DEVICE_ID -#define XPAR_XTTCPS_9_BASEADDR 0xFF140000 -#define XPAR_XTTCPS_9_TTC_CLK_FREQ_HZ 100000000 -#define XPAR_XTTCPS_9_TTC_CLK_CLKSRC 0 +#define XPAR_XTTCPS_9_BASEADDR 0xFF140000U +#define XPAR_XTTCPS_9_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_XTTCPS_9_TTC_CLK_CLKSRC 0U #define XPAR_XTTCPS_10_DEVICE_ID XPAR_PSU_TTC_10_DEVICE_ID -#define XPAR_XTTCPS_10_BASEADDR 0xFF140004 -#define XPAR_XTTCPS_10_TTC_CLK_FREQ_HZ 100000000 -#define XPAR_XTTCPS_10_TTC_CLK_CLKSRC 0 +#define XPAR_XTTCPS_10_BASEADDR 0xFF140004U +#define XPAR_XTTCPS_10_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_XTTCPS_10_TTC_CLK_CLKSRC 0U #define XPAR_XTTCPS_11_DEVICE_ID XPAR_PSU_TTC_11_DEVICE_ID -#define XPAR_XTTCPS_11_BASEADDR 0xFF140008 -#define XPAR_XTTCPS_11_TTC_CLK_FREQ_HZ 100000000 -#define XPAR_XTTCPS_11_TTC_CLK_CLKSRC 0 +#define XPAR_XTTCPS_11_BASEADDR 0xFF140008U +#define XPAR_XTTCPS_11_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_XTTCPS_11_TTC_CLK_CLKSRC 0U /******************************************************************/ @@ -1010,7 +1065,7 @@ #define XPAR_PSU_UART_0_DEVICE_ID 0 #define XPAR_PSU_UART_0_BASEADDR 0xFF000000 #define XPAR_PSU_UART_0_HIGHADDR 0xFF00FFFF -#define XPAR_PSU_UART_0_UART_CLK_FREQ_HZ 99998999 +#define XPAR_PSU_UART_0_UART_CLK_FREQ_HZ 99990000 #define XPAR_PSU_UART_0_HAS_MODEM 0 @@ -1018,7 +1073,7 @@ #define XPAR_PSU_UART_1_DEVICE_ID 1 #define XPAR_PSU_UART_1_BASEADDR 0xFF010000 #define XPAR_PSU_UART_1_HIGHADDR 0xFF01FFFF -#define XPAR_PSU_UART_1_UART_CLK_FREQ_HZ 99998999 +#define XPAR_PSU_UART_1_UART_CLK_FREQ_HZ 99990000 #define XPAR_PSU_UART_1_HAS_MODEM 0 @@ -1028,14 +1083,14 @@ #define XPAR_XUARTPS_0_DEVICE_ID XPAR_PSU_UART_0_DEVICE_ID #define XPAR_XUARTPS_0_BASEADDR 0xFF000000 #define XPAR_XUARTPS_0_HIGHADDR 0xFF00FFFF -#define XPAR_XUARTPS_0_UART_CLK_FREQ_HZ 99998999 +#define XPAR_XUARTPS_0_UART_CLK_FREQ_HZ 99990000 #define XPAR_XUARTPS_0_HAS_MODEM 0 /* Canonical definitions for peripheral PSU_UART_1 */ #define XPAR_XUARTPS_1_DEVICE_ID XPAR_PSU_UART_1_DEVICE_ID #define XPAR_XUARTPS_1_BASEADDR 0xFF010000 #define XPAR_XUARTPS_1_HIGHADDR 0xFF01FFFF -#define XPAR_XUARTPS_1_UART_CLK_FREQ_HZ 99998999 +#define XPAR_XUARTPS_1_UART_CLK_FREQ_HZ 99990000 #define XPAR_XUARTPS_1_HAS_MODEM 0 @@ -1044,16 +1099,17 @@ /* Definitions for driver USBPSU */ #define XPAR_XUSBPSU_NUM_INSTANCES 1 -/* Definitions for peripheral PSU_USB_0 */ -#define XPAR_PSU_USB_0_DEVICE_ID 0 -#define XPAR_PSU_USB_0_BASEADDR 0xFE200000 -#define XPAR_PSU_USB_0_HIGHADDR 0xFE20FFFF +/* Definitions for peripheral PSU_USB_XHCI_0 */ +#define XPAR_PSU_USB_XHCI_0_DEVICE_ID 0 +#define XPAR_PSU_USB_XHCI_0_BASEADDR 0xFE200000 +#define XPAR_PSU_USB_XHCI_0_HIGHADDR 0xFE20FFFF /******************************************************************/ -/* Canonical definitions for peripheral PSU_USB_0 */ -#define XPAR_XUSBPSU_0_DEVICE_ID XPAR_PSU_USB_0_DEVICE_ID +#define XPAR_PSU_USB_XHCI_0_IS_CACHE_COHERENT 0 +/* Canonical definitions for peripheral PSU_USB_XHCI_0 */ +#define XPAR_XUSBPSU_0_DEVICE_ID XPAR_PSU_USB_XHCI_0_DEVICE_ID #define XPAR_XUSBPSU_0_BASEADDR 0xFE200000 #define XPAR_XUSBPSU_0_HIGHADDR 0xFE20FFFF @@ -1067,14 +1123,14 @@ #define XPAR_PSU_WDT_0_DEVICE_ID 0 #define XPAR_PSU_WDT_0_BASEADDR 0xFF150000 #define XPAR_PSU_WDT_0_HIGHADDR 0xFF15FFFF -#define XPAR_PSU_WDT_0_WDT_CLK_FREQ_HZ 99999001 +#define XPAR_PSU_WDT_0_WDT_CLK_FREQ_HZ 99989998 /* Definitions for peripheral PSU_WDT_1 */ #define XPAR_PSU_WDT_1_DEVICE_ID 1 #define XPAR_PSU_WDT_1_BASEADDR 0xFD4D0000 #define XPAR_PSU_WDT_1_HIGHADDR 0xFD4DFFFF -#define XPAR_PSU_WDT_1_WDT_CLK_FREQ_HZ 99999001 +#define XPAR_PSU_WDT_1_WDT_CLK_FREQ_HZ 99989998 /******************************************************************/ @@ -1083,13 +1139,13 @@ #define XPAR_XWDTPS_0_DEVICE_ID XPAR_PSU_WDT_0_DEVICE_ID #define XPAR_XWDTPS_0_BASEADDR 0xFF150000 #define XPAR_XWDTPS_0_HIGHADDR 0xFF15FFFF -#define XPAR_XWDTPS_0_WDT_CLK_FREQ_HZ 99999001 +#define XPAR_XWDTPS_0_WDT_CLK_FREQ_HZ 99989998 /* Canonical definitions for peripheral PSU_WDT_1 */ #define XPAR_XWDTPS_1_DEVICE_ID XPAR_PSU_WDT_1_DEVICE_ID #define XPAR_XWDTPS_1_BASEADDR 0xFD4D0000 #define XPAR_XWDTPS_1_HIGHADDR 0xFD4DFFFF -#define XPAR_XWDTPS_1_WDT_CLK_FREQ_HZ 99999001 +#define XPAR_XWDTPS_1_WDT_CLK_FREQ_HZ 99989998 /******************************************************************/ @@ -1227,6 +1283,22 @@ /******************************************************************/ +#define XPAR_PSU_ADMA_0_IS_CACHE_COHERENT 0 +#define XPAR_PSU_ADMA_1_IS_CACHE_COHERENT 0 +#define XPAR_PSU_ADMA_2_IS_CACHE_COHERENT 0 +#define XPAR_PSU_ADMA_3_IS_CACHE_COHERENT 0 +#define XPAR_PSU_ADMA_4_IS_CACHE_COHERENT 0 +#define XPAR_PSU_ADMA_5_IS_CACHE_COHERENT 0 +#define XPAR_PSU_ADMA_6_IS_CACHE_COHERENT 0 +#define XPAR_PSU_ADMA_7_IS_CACHE_COHERENT 0 +#define XPAR_PSU_GDMA_0_IS_CACHE_COHERENT 0 +#define XPAR_PSU_GDMA_1_IS_CACHE_COHERENT 0 +#define XPAR_PSU_GDMA_2_IS_CACHE_COHERENT 0 +#define XPAR_PSU_GDMA_3_IS_CACHE_COHERENT 0 +#define XPAR_PSU_GDMA_4_IS_CACHE_COHERENT 0 +#define XPAR_PSU_GDMA_5_IS_CACHE_COHERENT 0 +#define XPAR_PSU_GDMA_6_IS_CACHE_COHERENT 0 +#define XPAR_PSU_GDMA_7_IS_CACHE_COHERENT 0 /* Canonical definitions for peripheral PSU_ADMA_0 */ #define XPAR_XZDMA_0_DEVICE_ID XPAR_PSU_ADMA_0_DEVICE_ID #define XPAR_XZDMA_0_BASEADDR 0xFFA80000 @@ -1342,3 +1414,4 @@ /******************************************************************/ +#endif /* end of protection macro */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/avbuf_v2_1/src/Makefile b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/avbuf_v2_1/src/Makefile new file mode 100644 index 000000000..2a2195c4d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/avbuf_v2_1/src/Makefile @@ -0,0 +1,40 @@ +COMPILER= +ARCHIVER= +CP=cp +COMPILER_FLAGS= +EXTRA_COMPILER_FLAGS= +LIB=libxil.a + +CC_FLAGS = $(COMPILER_FLAGS) +ECC_FLAGS = $(EXTRA_COMPILER_FLAGS) + +RELEASEDIR=../../../lib +INCLUDEDIR=../../../include +INCLUDES=-I./. -I${INCLUDEDIR} + +OUTS = *.o + +LIBSOURCES:=*.c +INCLUDEFILES:=*.h + +OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c))) + +libs: banner avbuf_libs clean + +%.o: %.c + ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $< + +banner: + echo "Compiling avbuf" + +avbuf_libs: ${OBJECTS} + $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS} + +.PHONY: include +include: avbuf_includes + +avbuf_includes: + ${CP} ${INCLUDEFILES} ${INCLUDEDIR} + +clean: + rm -rf ${OBJECTS} diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/avbuf_v2_1/src/xavbuf.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/avbuf_v2_1/src/xavbuf.c new file mode 100644 index 000000000..34e841ff5 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/avbuf_v2_1/src/xavbuf.c @@ -0,0 +1,1092 @@ +/******************************************************************************* + * + * Copyright (C) 2017 Xilinx, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * Use of the Software is limited solely to applications: + * (a) running on a Xilinx device, or + * (b) that interact with a Xilinx device through a bus or interconnect. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of the Xilinx shall not be used + * in advertising or otherwise to promote the sale, use or other dealings in + * this Software without prior written authorization from Xilinx. + * +*******************************************************************************/ +/******************************************************************************/ +/** + * + * @file xavbuf.c + * + * This file implements all the functions related to the Video Pipeline of the + * DisplayPort Subsystem. See xavbuf.h for the detailed description of the + * driver. + * + * @note None. + * + * 
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -----------------------------------------------
+ * 1.0   aad  06/24/17 Initial release.
+ * 2.0   aad  10/08/17 Some APIs to use enums instead of Macros.
+ *		       Some bug fixes.
+ *
+ * +*******************************************************************************/ +/******************************* Include Files ********************************/ +#include "xavbuf.h" +#include "xstatus.h" + +/**************************** Constant Definitions ****************************/ +const XAVBuf_VideoAttribute XAVBuf_SupportedFormats[XAVBUF_NUM_SUPPORTED]; + +/******************************************************************************/ +/** + * This function sets the scaling factors depending on the source video stream. + * + * @param InstancePtr is a pointer to the XAVBuf instance. + * @param RegOffset is the register offset of the SF0 register from the + * DP BaseAddress. + * @param Scaling Factors is a pointer to the scaling factors needed for + * scaling colors to 12 BPC. + * + * @return None. + * + * @note None. + * +*******************************************************************************/ +static void XAVBuf_SetScalingFactors(XAVBuf *InstancePtr, u32 RegOffset, + u32 *ScalingFactors) +{ + u32 Index = 0; + for (Index = 0; Index < 3; Index++) { + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, + RegOffset + (Index * 4), ScalingFactors[Index]); + } + +} + +/******************************************************************************/ +/** + * This function sets the Layer Control for Video and Graphics layers. + * + * @param InstancePtr is a pointer to the XAVBuf instance. + * @param RegOffset is the register offset of Video Layer or Graphics + * Layer from the base address + * @param Video is a pointer to the XAVBuf_VideoAttribute struct which + * has been configured for the particular layer + * + * @return None. + * + * @note None. + * +*******************************************************************************/ +static void XAVBuf_SetLayerControl(XAVBuf *InstancePtr, u32 RegOffset, + XAVBuf_VideoAttribute *Video) +{ + u32 RegVal = 0; + + RegVal = (Video->IsRGB << + XAVBUF_V_BLEND_LAYER0_CONTROL_RGB_MODE_SHIFT) | + Video->SamplingEn; + + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, RegOffset, RegVal); +} + +/******************************************************************************/ +/** + * This function applies Attributes for Live source(Video/Graphics). + * + * @param InstancePtr is an pointer to the XAVBuf Instance. + * @param RegConfig is a register offset for Video or Graphics config + * register + * @param Video is a pointer to the attributes of the video to be applied + * + * @return None. + * + * @note Live source can be live Video or Live Graphics. +******************************************************************************/ +static void XAVBuf_SetLiveVideoAttributes(XAVBuf *InstancePtr, u32 RegConfig, + XAVBuf_VideoAttribute *Video) +{ + u32 RegVal = 0; + + RegVal |= Video->Value << XAVBUF_BUF_LIVE_VID_CFG_FORMAT_SHIFT; + RegVal |= Video->BPP/6 - 3; + RegVal |= Video->Swap << XAVBUF_BUF_LIVE_VID_CFG_CB_FIRST_SHIFT; + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, RegConfig, RegVal); +} + +/******************************************************************************/ +/** + * This function applies Attributes for Non - Live source(Video/Graphics). + * + * @param InstancePtr is an pointer to the XAVBuf Instance. + * @param VideoSrc is the source of the Non-Live Video + * @param Video is a pointer to the attributes of the video to be applied + * + * @return None. + * + * @note Non Live source can be Non Live Video or Non Live Graphics. +******************************************************************************/ +static void XAVBuf_SetNonLiveVideoAttributes(XAVBuf *InstancePtr, u32 VideoSrc, + XAVBuf_VideoAttribute *Video) +{ + u32 RegVal = 0; + + RegVal = XAVBuf_ReadReg(InstancePtr->Config.BaseAddr, + XAVBUF_BUF_FORMAT); + if(VideoSrc == XAVBUF_VIDSTREAM1_NONLIVE) { + RegVal &= ~XAVBUF_BUF_FORMAT_NL_VID_FORMAT_MASK; + RegVal |= Video->Value; + } + else if (VideoSrc == XAVBUF_VIDSTREAM2_NONLIVE_GFX) { + RegVal &= ~XAVBUF_BUF_FORMAT_NL_GRAPHX_FORMAT_MASK; + RegVal |= (Video->Value) << + XAVBUF_BUF_FORMAT_NL_GRAPHX_FORMAT_SHIFT; + } + + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, XAVBUF_BUF_FORMAT, + RegVal); +} + +/******************************************************************************/ +/** + * This function programs the coeffitients for Color Space Conversion. + * + * @param InstancePtr is an pointer to the XAVBuf Instance. + * @param RegOffset is a register offset for Video or Graphics config + * register + * @param Video is a pointer to the XAVBuf_Attribute structure + * + * @return None. + * + * @note None. +******************************************************************************/ +static void XAVBuf_InConvertToRGB(XAVBuf *InstancePtr, u32 RegOffset, + XAVBuf_VideoAttribute *Video) +{ + u16 Index; + u16 *CSCMatrix; + u16 *OffsetMatrix; + + /* SDTV Coefficients */ + u16 CSCCoeffs[] = { 0x1000, 0x0000, 0x166F, + 0x1000, 0x7A7F, 0x7493, + 0x1000, 0x1C5A, 0x0000 }; + u16 CSCOffset[] = { 0x0000, 0x1800, 0x1800 }; + u16 RGBCoeffs[] = { 0x1000, 0x0000, 0x0000, + 0x0000, 0x1000, 0x0000, + 0x0000, 0x0000, 0x1000 }; + u16 RGBOffset[] = { 0x0000, 0x0000, 0x0000 }; + if(Video->IsRGB) { + CSCMatrix = RGBCoeffs; + OffsetMatrix = RGBOffset; + } + else { + CSCMatrix = CSCCoeffs; + OffsetMatrix = CSCOffset; + } + /* Program Colorspace conversion coefficients */ + for (Index = 9; Index < 12; Index++) { + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, + RegOffset + (Index * 4), + OffsetMatrix[Index - 9]); + } + + /* Program Colorspace conversion matrix */ + for (Index = 0; Index < 9; Index++) { + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, + RegOffset + (Index * 4), CSCMatrix[Index]); + } + +} + +/******************************************************************************/ +/** + * This function converts the Blender output to the desired output format. + * + * @param InstancePtr is an pointer to the XAVBuf Instance. + * @param RegConfig is a register offset for Video or Graphics config + * register + * @param Video is a pointer to the XAVBuf_Attribute structure + * + * @return None. + * + * @note None. +******************************************************************************/ +static void XAVBuf_InConvertToOutputFormat(XAVBuf *InstancePtr, + XAVBuf_VideoAttribute *Video) + +{ u32 Index = 0; + u32 RegOffset = XAVBUF_V_BLEND_RGB2YCBCR_COEFF0; + u32 ColorOffset = XAVBUF_V_BLEND_LUMA_OUTCSC_OFFSET; + u8 Value = Video->Value; + u16 *MatrixCoeff; + u16 *MatrixOffset; + + /* SDTV Coeffitients */ + u16 CSCCoeffs[] = { 0x04C8, 0x0964, 0x01D3, + 0x7D4C, 0x7AB4, 0x0800, + 0x0800, 0x7945, 0x7EB5 }; + u16 CSCOffset[] = { 0x0000, 0x800, 0x800 }; + u16 RGBCoeffs[] = { 0x1000, 0x0000, 0x0000, + 0x0000, 0x1000, 0x0000, + 0x0000, 0x0000, 0x1000 }; + u16 RGBOffset[] = { 0x0000, 0x0000, 0x0000 }; + + + if(Value) { + MatrixCoeff = CSCCoeffs; + MatrixOffset = CSCOffset; + + } + else { + MatrixCoeff = RGBCoeffs; + MatrixOffset = RGBOffset; + } + + for (Index = 0; Index < 9; Index++) { + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, + RegOffset + (Index * 4), MatrixCoeff[Index]); + } + for (Index = 0; Index < 3; Index++) { + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, + ColorOffset + (Index * 4), + (MatrixOffset[Index] << + XAVBUF_V_BLEND_LUMA_IN1CSC_OFFSET_POST_OFFSET_SHIFT)); + } +} +/******************************************************************************/ +/** + * This function configures the Video Pipeline for the selected source + * + * @param InstancePtr is an pointer to the XAVBuf Instance. + * @param VideoSrc is a parameter which indicates which Video Source + * selected + * + * @return None. + * + * @note None. +******************************************************************************/ +static int XAVBuf_ConfigureVideo(XAVBuf *InstancePtr, u8 VideoSrc) +{ + + u32 RegConfig = 0; + u32 ScalingOffset = 0; + u32 LayerOffset = 0; + u32 CSCOffset = 0; + XAVBuf_VideoAttribute *Video = NULL; + u32 *ScalingFactors = NULL; + + Xil_AssertNonvoid(InstancePtr != NULL); + switch(VideoSrc) { + case XAVBUF_VIDSTREAM1_LIVE: + RegConfig = XAVBUF_BUF_LIVE_VID_CFG; + ScalingOffset = XAVBUF_BUF_LIVE_VID_COMP0_SF; + LayerOffset = XAVBUF_V_BLEND_LAYER0_CONTROL; + CSCOffset = XAVBUF_V_BLEND_IN1CSC_COEFF0; + Video = InstancePtr->AVMode.LiveVideo; + ScalingFactors = Video->SF; + + /* Set the Video Attributes */ + XAVBuf_SetLiveVideoAttributes(InstancePtr, RegConfig, + Video); + break; + + case XAVBUF_VIDSTREAM2_LIVE_GFX: + RegConfig = XAVBUF_BUF_LIVE_GFX_CFG; + ScalingOffset = XAVBUF_BUF_LIVE_GFX_COMP0_SF; + LayerOffset = XAVBUF_V_BLEND_LAYER1_CONTROL; + CSCOffset = XAVBUF_V_BLEND_IN2CSC_COEFF0; + Video = InstancePtr->AVMode.LiveGraphics; + ScalingFactors = Video->SF; + + /* Set the Video Attributes */ + XAVBuf_SetLiveVideoAttributes(InstancePtr, RegConfig, + Video); + break; + + case XAVBUF_VIDSTREAM1_NONLIVE: + RegConfig = XAVBUF_BUF_LIVE_GFX_CFG; + ScalingOffset = XAVBUF_BUF_VID_COMP0_SCALE_FACTOR; + LayerOffset = XAVBUF_V_BLEND_LAYER0_CONTROL; + CSCOffset = XAVBUF_V_BLEND_IN1CSC_COEFF0; + Video = InstancePtr->AVMode.NonLiveVideo; + ScalingFactors = Video->SF; + + /* Set the Video Attributes */ + XAVBuf_SetNonLiveVideoAttributes(InstancePtr, VideoSrc, + Video); + break; + + case XAVBUF_VIDSTREAM2_NONLIVE_GFX: + RegConfig = XAVBUF_BUF_LIVE_GFX_CFG; + ScalingOffset = XAVBUF_BUF_GRAPHICS_COMP0_SCALE_FACTOR; + LayerOffset = XAVBUF_V_BLEND_LAYER1_CONTROL; + CSCOffset = XAVBUF_V_BLEND_IN2CSC_COEFF0; + Video = InstancePtr->AVMode.NonLiveGraphics; + ScalingFactors = Video->SF; + + /* Set the Video Attributes */ + XAVBuf_SetNonLiveVideoAttributes(InstancePtr, VideoSrc, + Video); + break; + case XAVBUF_VIDSTREAM1_TPG: + RegConfig |= 1 << + XAVBUF_V_BLEND_LAYER0_CONTROL_RGB_MODE_SHIFT; + RegConfig |= 1 << + XAVBUF_V_BLEND_LAYER0_CONTROL_BYPASS_SHIFT; + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, + XAVBUF_V_BLEND_LAYER0_CONTROL, + RegConfig); + break; + default: + return XST_FAILURE; + } + /* Setting the scaling factors */ + XAVBuf_SetScalingFactors(InstancePtr, ScalingOffset, ScalingFactors); + /* Layer Control */ + XAVBuf_SetLayerControl(InstancePtr, LayerOffset, Video); + /* Colorspace conversion */ + XAVBuf_InConvertToRGB(InstancePtr, CSCOffset, Video); + return XST_SUCCESS; +} + +/******************************************************************************/ +/** + * This function intializes the configuration for the AVBuf Instance. + * + * @param InstancePtr is a pointer to the XAVBuf instance. + * @param BaseAddr sets the base address of the AVBuf instance + * @param Deviceid is the id of the device from the design. + * + * @return None. + * + * @note Base address and DeviceId is same as the DP Core driver. + * +*******************************************************************************/ +void XAVBuf_CfgInitialize(XAVBuf *InstancePtr, u32 BaseAddr, u16 DeviceId) +{ + Xil_AssertVoid(InstancePtr != NULL); + + InstancePtr->Config.DeviceId = DeviceId; + InstancePtr->Config.BaseAddr = BaseAddr; +} + +/******************************************************************************/ +/** + * This function initializes all the data structures of the XAVBuf Instance. + * + * @param InstancePtr is a pointer to the XAVBuf instance. + * + * @return None. + * + * @note None. + * +*******************************************************************************/ +void XAVBuf_Initialize(XAVBuf *InstancePtr) +{ + Xil_AssertVoid(InstancePtr != NULL); + + InstancePtr->AVMode.NonLiveVideo = NULL; + InstancePtr->AVMode.LiveVideo = NULL; + InstancePtr->AVMode.LiveGraphics = NULL; + InstancePtr->AVMode.NonLiveGraphics = NULL; + InstancePtr->AVMode.VideoSrc = XAVBUF_VIDSTREAM1_NONE; + InstancePtr->AVMode.GraphicsSrc = XAVBUF_VIDSTREAM2_NONE; + InstancePtr->AVMode.Audio = NULL; + InstancePtr->AVMode.GraphicsAudio = NULL; + InstancePtr->AVMode.AudioSrc1 = XAVBUF_AUDSTREAM1_NO_AUDIO; + InstancePtr->AVMode.AudioSrc2 = XAVBUF_AUDSTREAM2_NO_AUDIO; + + InstancePtr->Blender.GlobalAlphaEn = 0; + InstancePtr->Blender.Alpha = 0; + InstancePtr->Blender.OutputVideo = NULL; + + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, XAVBUF_AUD_SOFT_RST, 0); +} + +/******************************************************************************/ +/** + * This function selects the source for the Video and Graphics streams that are + * passed on to the blender block. + * + * @param InstancePtr is a pointer to the XAVBuf instance. + * @param VidStream selects the stream coming from the video sources + * @param GfxStream selects the stream coming from the graphics sources + * + * @return None. + * + * @note None. + * +*******************************************************************************/ +void XAVBuf_InputVideoSelect(XAVBuf *InstancePtr, XAVBuf_VideoStream VidStream, + XAVBuf_GfxStream GfxStream) +{ + + + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid((VidStream != XAVBUF_VIDSTREAM1_LIVE) | + (VidStream != XAVBUF_VIDSTREAM1_NONLIVE) | + (VidStream != XAVBUF_VIDSTREAM1_TPG) | + (VidStream != XAVBUF_VIDSTREAM1_NONE)); + Xil_AssertVoid((GfxStream != XAVBUF_VIDSTREAM2_DISABLEGFX) | + (GfxStream != XAVBUF_VIDSTREAM2_NONLIVE_GFX) | + (GfxStream != XAVBUF_VIDSTREAM2_LIVE_GFX) | + (GfxStream != XAVBUF_VIDSTREAM2_NONE)); + + InstancePtr->AVMode.VideoSrc = VidStream; + InstancePtr->AVMode.GraphicsSrc = GfxStream; + u32 RegVal; + RegVal = XAVBuf_ReadReg(InstancePtr->Config.BaseAddr, + XAVBUF_BUF_OUTPUT_AUD_VID_SELECT); + RegVal &= ~(XAVBUF_BUF_OUTPUT_AUD_VID_SELECT_VID_STREAM2_SEL_MASK | + XAVBUF_BUF_OUTPUT_AUD_VID_SELECT_VID_STREAM1_SEL_MASK); + RegVal |= VidStream | GfxStream; + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, + XAVBUF_BUF_OUTPUT_AUD_VID_SELECT, RegVal); +} + +/******************************************************************************/ +/** + * This function sets the video format for the non-live video + * + * @param InstancePtr is a pointer to the XAVBuf instance. + * @param Format is the enum for the non-live video format + * + * @return XST_SUCCESS if the correct format has been set. + * XST_FAILURE if the format is invalid. + * + * @note None. +*******************************************************************************/ +int XAVBuf_SetInputNonLiveVideoFormat(XAVBuf *InstancePtr, + XAVBuf_VideoFormat Format) +{ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid((Format >= CbY0CrY1) | (Format <= YV16Ci2_420_10BPC)); + + InstancePtr->AVMode.NonLiveVideo = + XAVBuf_GetNLiveVideoAttribute(Format); + if(InstancePtr->AVMode.NonLiveVideo == NULL) + return XST_FAILURE; + + return XST_SUCCESS; +} + +/******************************************************************************/ +/** + * This function sets the graphics format for the non-live video + * + * @param InstancePtr is a pointer to the XAVBuf instance. + * @param Format is the enum for the non-live video format + * + * @return XST_SUCCESS if the correct format has been set. + * XST_FAILURE if the format is invalid. + * + * @note None. +*******************************************************************************/ +int XAVBuf_SetInputNonLiveGraphicsFormat(XAVBuf *InstancePtr, + XAVBuf_VideoFormat Format) +{ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid((Format >= RGBA8888) |( Format <= YOnly)); + + InstancePtr->AVMode.NonLiveGraphics = + XAVBuf_GetNLGraphicsAttribute(Format); + if(InstancePtr->AVMode.NonLiveGraphics == NULL) + return XST_FAILURE; + + return XST_SUCCESS; +} + +/******************************************************************************/ +/** + * This function sets the video format for the live video + * + * @param InstancePtr is a pointer to the XAVBuf instance. + * @param Format is the enum for the non-live video format + * + * @return XST_SUCCESS if the correct format has been set. + * XST_FAILURE if the format is invalid. + * + * @note None. +*******************************************************************************/ +int XAVBuf_SetInputLiveVideoFormat(XAVBuf *InstancePtr, + XAVBuf_VideoFormat Format) +{ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid((Format >= RGB_6BPC) | (Format <= YOnly_12BPC)); + + InstancePtr->AVMode.LiveVideo = XAVBuf_GetLiveVideoAttribute(Format); + if(InstancePtr->AVMode.LiveVideo == NULL) + return XST_FAILURE; + + return XST_SUCCESS; +} + +/******************************************************************************/ +/** + * This function sets the graphics format for the live video + * + * @param InstancePtr is a pointer to the XAVBuf instance. + * @param Format is the enum for the non-live video format + * + * @return XST_SUCCESS if the correct format has been set. + * XST_FAILURE if the format is invalid. + * + * @note None. +*******************************************************************************/ +int XAVBuf_SetInputLiveGraphicsFormat(XAVBuf *InstancePtr, + XAVBuf_VideoFormat Format) +{ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid((Format >= RGB_6BPC) | (Format <= YOnly_12BPC)); + + InstancePtr->AVMode.LiveGraphics = + XAVBuf_GetLiveVideoAttribute(Format); + if(InstancePtr->AVMode.LiveGraphics == NULL) + return XST_FAILURE; + + return XST_SUCCESS; +} + +/******************************************************************************/ +/** + * This function sets the Output Video Format + * + * @param InstancePtr is a pointer to the XAVBuf instance. + * @param Format is the enum for the non-live video format + * + * @return XST_SUCCESS if the correct format has been set. + * XST_FAILURE if the format is invalid. + * + * @note None. +*******************************************************************************/ +int XAVBuf_SetOutputVideoFormat(XAVBuf *InstancePtr, XAVBuf_VideoFormat Format) +{ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid((Format >= RGB_6BPC) | (Format <= YOnly_12BPC)); + + InstancePtr->Blender.OutputVideo = + XAVBuf_GetLiveVideoAttribute(Format); + if(InstancePtr->Blender.OutputVideo == NULL) + return XST_FAILURE; + else + return XST_SUCCESS; +} + +/******************************************************************************/ +/** + * This function sets the Audio and Video Clock Source and the video timing + * source. + * + * @param InstancePtr is a pointer to the XAVBuf instance. + * @param VideoClk selects the Video Clock Source + * @param AudioClk selects the Audio Clock Source + * + * @return None. + * + * @note System uses PL Clock for Video when Live source is in use. + * +*******************************************************************************/ +void XAVBuf_SetAudioVideoClkSrc(XAVBuf *InstancePtr, u8 VideoClk, u8 AudioClk) +{ + + u32 RegVal = 0; + + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid((VideoClk != XAVBUF_PS_CLK) | + (VideoClk!= XAVBUF_PL_CLK)); + Xil_AssertVoid((AudioClk != XAVBUF_PS_CLK) | + (AudioClk!= XAVBUF_PL_CLK)); + + if((InstancePtr->AVMode.VideoSrc != XAVBUF_VIDSTREAM1_LIVE) && + (InstancePtr->AVMode.GraphicsSrc != XAVBUF_VIDSTREAM2_LIVE_GFX)) { + RegVal = 1 << + XAVBUF_BUF_AUD_VID_CLK_SOURCE_VID_TIMING_SRC_SHIFT; + } + else if((InstancePtr->AVMode.VideoSrc == XAVBUF_VIDSTREAM1_LIVE) || + (InstancePtr->AVMode.GraphicsSrc == + XAVBUF_VIDSTREAM2_LIVE_GFX)) { + VideoClk = XAVBUF_PL_CLK; + } + + RegVal |= (VideoClk << + XAVBUF_BUF_AUD_VID_CLK_SOURCE_VID_CLK_SRC_SHIFT) | + (AudioClk << + XAVBUF_BUF_AUD_VID_CLK_SOURCE_AUD_CLK_SRC_SHIFT); + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, + XAVBUF_BUF_AUD_VID_CLK_SOURCE, RegVal); + /*Soft Reset VideoPipeline when changing the clock source*/ + XAVBuf_SoftReset(InstancePtr); +} + +/******************************************************************************/ +/** + * This function applies a soft reset to the Audio Video pipeline. + * + * @param InstancePtr is a pointer to the XAVBuf instance. + * + * @return None. + * + * @note None. + * +*******************************************************************************/ +void XAVBuf_SoftReset(XAVBuf *InstancePtr) +{ + Xil_AssertVoid(InstancePtr != NULL); + + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, XAVBUF_BUF_SRST_REG, + XAVBUF_BUF_SRST_REG_VID_RST_MASK); + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, XAVBUF_BUF_SRST_REG, 0); +} + +/******************************************************************************/ +/** + * This function looks up if the video format is valid or not for the non-live + * video datapath and returns a pointer to the attributes of the video. + * + * @param Format takes in the video format for which attributes are being + * requested. + * + * @return A pointer to the structure XAVBuf_VideoAttribute if the video + * format is valid, else returns NULL. + * @note None. +*******************************************************************************/ +XAVBuf_VideoAttribute *XAVBuf_GetLiveVideoAttribute(XAVBuf_VideoFormat Format) +{ + u8 Index = 0; + XAVBuf_VideoAttribute *VideoAttribute; + Xil_AssertNonvoid((Format >= RGB_6BPC) | (Format <= YOnly_12BPC)); + + for (Index = RGB_6BPC; Index <= YOnly_12BPC; Index++) { + VideoAttribute = (XAVBuf_VideoAttribute *) + &XAVBuf_SupportedFormats[Index]; + if(Format == VideoAttribute->VideoFormat) { + return VideoAttribute; + } + } + return NULL; +} + +/******************************************************************************/ +/** + * This function looks up if the video format is valid or not and returns a + * pointer to the attributes of the video. + * + * @param Format takes in the video format for which attributes are being + * requested. + * + * @return A pointer to the structure XAVBuf_VideoAttribute if the video + * format is valid, else returns NULL. + * @note None. +*******************************************************************************/ +XAVBuf_VideoAttribute *XAVBuf_GetNLiveVideoAttribute(XAVBuf_VideoFormat Format) +{ + u8 Index = 0; + XAVBuf_VideoAttribute *VideoAttribute; + + Xil_AssertNonvoid((Format >= CbY0CrY1) | (Format <= YV16Ci2_420_10BPC)); + + for (Index = CbY0CrY1; Index <= YV16Ci2_420_10BPC; Index++) { + VideoAttribute = (XAVBuf_VideoAttribute *) + &XAVBuf_SupportedFormats[Index]; + if(Format == VideoAttribute->VideoFormat) { + return VideoAttribute; + } + } + return NULL; +} + +/******************************************************************************/ +/** + * This function looks up if the video format is valid or not and returns a + * pointer to the attributes of the video. + * + * @param Format takes in the video format for which attributes are being + * requested. + * + * @return A pointer to the structure XAVBuf_VideoAttribute if the video + * format is valid, else returns NULL. + * @note None. +*******************************************************************************/ +XAVBuf_VideoAttribute *XAVBuf_GetNLGraphicsAttribute(XAVBuf_VideoFormat Format) +{ + u32 Index = 0; + XAVBuf_VideoAttribute *VideoAttribute; + + Xil_AssertNonvoid((Format >= RGBA8888) | (Format <= YOnly)); + + for(Index = RGBA8888; Index <= YOnly; Index++) { + VideoAttribute = (XAVBuf_VideoAttribute *) + &XAVBuf_SupportedFormats[Index]; + if(Format == VideoAttribute->VideoFormat) { + return VideoAttribute; + } + } + return NULL; +} + +/******************************************************************************/ +/** + * This function configures the Video Pipeline + * + * @param InstancePtr is an pointer to the XAVBuf Instance. + * + * @return None. + * + * @note None. +******************************************************************************/ +void XAVBuf_ConfigureVideoPipeline(XAVBuf *InstancePtr) +{ + Xil_AssertVoid(InstancePtr != NULL); + + XAVBuf_ConfigureVideo(InstancePtr, InstancePtr->AVMode.VideoSrc); +} + +/******************************************************************************/ +/** + * This function configures the Graphics Pipeline + * + * @param InstancePtr is an pointer to the XAVBuf Instance. + * + * @return None. + * + * @note None. +******************************************************************************/ +void XAVBuf_ConfigureGraphicsPipeline(XAVBuf *InstancePtr) +{ + Xil_AssertVoid(InstancePtr != NULL); + XAVBuf_ConfigureVideo(InstancePtr, InstancePtr->AVMode.GraphicsSrc); +} + +/******************************************************************************/ +/** + * This function sets the blender background color + * + * @param InstancePtr is an pointer to the XAVBuf Instance. + * @param Color is a pointer to the structure XAVBuf_BlenderBgClr + * + * @return None. + * + * @note None. +******************************************************************************/ +void XAVBuf_BlendSetBgColor(XAVBuf *InstancePtr, XAVBuf_BlenderBgClr *Color) +{ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(Color != NULL); + + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, XAVBUF_V_BLEND_BG_CLR_0, + Color->RCr); + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, XAVBUF_V_BLEND_BG_CLR_1, + Color->GY); + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, XAVBUF_V_BLEND_BG_CLR_2, + Color->BCb); +} + +/******************************************************************************/ +/** + * This function enables or disables global alpha + * + * @param InstancePtr is an pointer to the XAVBuf Instance. + * @param Enable sets a software flag for global alpha + * @param Alpha sets the value for the global alpha blending + * + * @return None. + * + * @note GlobalAlphaEn = 1, enables the global alpha. + * GlobalAlphaEn = 0, disables the global alpha. + * Alpha = 0, passes stream2 + * Alpha = 255, passes stream1 +******************************************************************************/ +void XAVBuf_SetBlenderAlpha(XAVBuf *InstancePtr, u8 Alpha, u8 Enable) +{ + u32 RegVal; + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid((Enable !=0) | (Enable != 1)); + + InstancePtr->Blender.GlobalAlphaEn = Enable; + InstancePtr->Blender.Alpha = Alpha; + + RegVal = Enable; + RegVal |= Alpha << XAVBUF_V_BLEND_SET_GLOBAL_ALPHA_REG_VALUE_SHIFT; + + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, + XAVBUF_V_BLEND_SET_GLOBAL_ALPHA_REG, RegVal); +} + +/******************************************************************************/ +/** + * This function configures the Output of the Video Pipeline + * + * @param InstancePtr is an pointer to the XAVBuf Instance. + * @param OutputVideo is a pointer to the XAVBuf_VideoAttribute. + * + * @return None. + * + * @note None. +******************************************************************************/ +void XAVBuf_ConfigureOutputVideo(XAVBuf *InstancePtr) +{ + u32 RegVal = 0; + XAVBuf_VideoAttribute *OutputVideo = InstancePtr->Blender.OutputVideo; + + RegVal |= OutputVideo->SamplingEn << + XAVBUF_V_BLEND_OUTPUT_VID_FORMAT_EN_DOWNSAMPLE_SHIFT; + RegVal |= OutputVideo->Value; + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, + XAVBUF_V_BLEND_OUTPUT_VID_FORMAT, RegVal); + + XAVBuf_InConvertToOutputFormat(InstancePtr, OutputVideo); +} + +/******************************************************************************/ +/** + * This function selects the source for audio streams corresponding to the + * Video and Graphics streams that are passed on to the blender + * + * @param InstancePtr is a pointer to the XAVBuf instance. + * @param AudStream1 selects the audio stream source corresponding to + * the video source selected + * @param AudStream2 selects the audio stream source corresponding to + * the graphics source selected. + * + * @return None. + * + * @note None. + * +*******************************************************************************/ +void XAVBuf_InputAudioSelect(XAVBuf *InstancePtr, XAVBuf_AudioStream1 AudStream1, + XAVBuf_AudioStream2 AudStream2) +{ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid((AudStream1 != XAVBUF_AUDSTREAM1_NONLIVE) | + (AudStream1 != XAVBUF_AUDSTREAM1_LIVE) | + (AudStream1 != XAVBUF_AUDSTREAM1_TPG)); + Xil_AssertVoid((AudStream2 != XAVBUF_AUDSTREAM2_NO_AUDIO) | + (AudStream2 != XAVBUF_AUDSTREAM2_AUDIOGFX)); + + u32 RegVal; + RegVal = XAVBuf_ReadReg(InstancePtr->Config.BaseAddr, + XAVBUF_BUF_OUTPUT_AUD_VID_SELECT); + RegVal &= ~(XAVBUF_BUF_OUTPUT_AUD_VID_SELECT_AUD_STREAM2_SEL_MASK | + XAVBUF_BUF_OUTPUT_AUD_VID_SELECT_AUD_STREAM1_SEL_MASK); + RegVal |= AudStream1 | AudStream2; + + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, + XAVBUF_BUF_OUTPUT_AUD_VID_SELECT, RegVal); +} + +/******************************************************************************/ +/** + * This function sets up the scaling factor for Audio Mixer Volume Control. + * + * @param InstancePtr is a pointer to the XAVBuf instance. + * @param Channel0Volume is the volume to be set for Audio from Channel0 + * @param Channel1Volume is the volume to be set for Audio from Channel1 + * + * + * @return None. + * + * @note None. + * +*******************************************************************************/ +void XAVBuf_AudioMixerVolumeControl(XAVBuf *InstancePtr, u8 Channel0Volume, + u8 Channel1Volume) +{ + u32 Val; + Xil_AssertVoid(InstancePtr != NULL); + Val = Channel1Volume << + XAVBUF_AUD_MIXER_VOLUME_CONTROL_VOL_CTRL_CH1_SHIFT; + Val |= Channel0Volume; + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, + XAVBUF_AUD_MIXER_VOLUME_CONTROL, Val); +} + +/******************************************************************************/ +/** + * This function resets the Audio Pipe. + * + * @param InstancePtr is a pointer to the XAVBuf Instance. + * + * @returns None. + * + * @note Needed when non-live audio is disabled. + * + * + ******************************************************************************/ +void XAVBuf_AudioSoftReset(XAVBuf *InstancePtr) +{ + u32 RegVal = 0; + Xil_AssertVoid(InstancePtr != NULL); + RegVal = XAVBuf_ReadReg(InstancePtr->Config.BaseAddr, + XAVBUF_AUD_SOFT_RST); + RegVal |= XAVBUF_AUD_SOFT_RST_AUD_SRST_MASK; + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, XAVBUF_AUD_SOFT_RST, + RegVal); + RegVal &= ~XAVBUF_AUD_SOFT_RST_AUD_SRST_MASK; + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, XAVBUF_AUD_SOFT_RST, 0); + +} + +/******************************************************************************/ +/** + * This function enables End of Line Reset for reduced blanking resolutions. + * + * @param InstancePtr is a pointer to the XAVBuf Instance. + * @param Disable is to be set while using Reduced Blanking Resolutions. + * + * @returns None. + * + * @note None. + * + ******************************************************************************/ +void XABuf_LineResetDisable(XAVBuf *InstancePtr, u8 Disable) +{ + u32 RegVal = 0; + Xil_AssertVoid(InstancePtr != NULL); + RegVal = XAVBuf_ReadReg(InstancePtr->Config.BaseAddr, + XAVBUF_AUD_SOFT_RST); + if(Disable) + RegVal |= XAVBUF_AUD_SOFT_RST_LINE_RST_DISABLE_MASK; + else + RegVal &= ~XAVBUF_AUD_SOFT_RST_LINE_RST_DISABLE_MASK; + + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, XAVBUF_AUD_SOFT_RST, + RegVal); +} + +/******************************************************************************/ +/** + * This function enables the video channel interface between the DPDMA and the + * AVBuf + * + * @param InstancePtr is a pointer to the XAVBuf Instance. + * @param Enable sets the corresponding buffers. + * + * @returns None. + * + * @note None. + * + ******************************************************************************/ +void XAVBuf_EnableVideoBuffers(XAVBuf *InstancePtr, u8 Enable) +{ + u8 Index; + u32 RegVal = 0; + u8 NumPlanes = InstancePtr->AVMode.NonLiveVideo->Mode; + + RegVal = (0xF << XAVBUF_CHBUF0_BURST_LEN_SHIFT) | + (XAVBUF_CHBUF0_FLUSH_MASK); + + for (Index = 0; Index <= NumPlanes; Index++) { + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, + XAVBUF_CHBUF0 + (Index * 4), RegVal); + } + if(Enable) { + RegVal = (0xF << XAVBUF_CHBUF0_BURST_LEN_SHIFT) | + XAVBUF_CHBUF0_EN_MASK; + for (Index = 0; Index <= NumPlanes; Index++) { + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, + XAVBUF_CHBUF0 + (Index * 4), RegVal); + } + } +} +/******************************************************************************/ +/** + * This function enables the graphics interface between the DPDMA and the AVBuf. + * + * @param InstancePtr is a pointer to the XAVBuf Instance. + * @param Enable sets the corresponding buffers. + * + * @returns None. + * + * @note None. + * + ******************************************************************************/ +void XAVBuf_EnableGraphicsBuffers(XAVBuf *InstancePtr, u8 Enable) +{ + u32 RegVal = 0; + + RegVal = (0xF << XAVBUF_CHBUF3_BURST_LEN_SHIFT) | + XAVBUF_CHBUF3_FLUSH_MASK; + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, XAVBUF_CHBUF3, RegVal); + if(Enable) { + RegVal = (0xF << XAVBUF_CHBUF3_BURST_LEN_SHIFT) | + XAVBUF_CHBUF0_EN_MASK; + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, XAVBUF_CHBUF3, + RegVal); + } +} + +/******************************************************************************/ +/** + * This function enables the audio interface between the DPDMA and the AVBuf + * + * @param InstancePtr is a pointer to the XAVBuf Instance. + * @param Enable sets the corresponding buffers. + * + * @returns None. + * + * @note None. + * + ******************************************************************************/ +void XAVBuf_EnableAudio0Buffers(XAVBuf *InstancePtr, u8 Enable) +{ + u32 RegVal = 0; + + RegVal = (0x3 << XAVBUF_CHBUF4_BURST_LEN_SHIFT) | + XAVBUF_CHBUF4_FLUSH_MASK; + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, XAVBUF_CHBUF4, RegVal); + if(Enable) { + RegVal = (0x3 << XAVBUF_CHBUF4_BURST_LEN_SHIFT) | + XAVBUF_CHBUF4_EN_MASK; + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, XAVBUF_CHBUF4, + RegVal); + } +} + +/******************************************************************************/ +/** + * This function enables the audio interface between the DPDMA and the AVBuf + * + * @param InstancePtr is a pointer to the XAVBuf Instance. + * @param Enable sets the corresponding buffers. + * + * @returns None. + * + * @note None. + * + ******************************************************************************/ +void XAVBuf_EnableAudio1Buffers(XAVBuf *InstancePtr, u8 Enable) +{ + u32 RegVal = 0; + + RegVal = (0x3 << XAVBUF_CHBUF5_BURST_LEN_SHIFT) | + XAVBUF_CHBUF5_FLUSH_MASK; + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, XAVBUF_CHBUF5, RegVal); + if(Enable) { + RegVal = (0x3 << XAVBUF_CHBUF5_BURST_LEN_SHIFT) | + XAVBUF_CHBUF5_EN_MASK; + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, XAVBUF_CHBUF5, + RegVal); + } +} diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/avbuf_v2_1/src/xavbuf.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/avbuf_v2_1/src/xavbuf.h new file mode 100644 index 000000000..386bfbaa9 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/avbuf_v2_1/src/xavbuf.h @@ -0,0 +1,302 @@ +/******************************************************************************* + * + * Copyright (C) 2017 Xilinx, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * Use of the Software is limited solely to applications: + * (a) running on a Xilinx device, or + * (b) that interact with a Xilinx device through a bus or interconnect. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of the Xilinx shall not be used + * in advertising or otherwise to promote the sale, use or other dealings in + * this Software without prior written authorization from Xilinx. + * +*******************************************************************************/ +/******************************************************************************/ +/** + * + * @file xavbuf.h + * + * This file implements all the functions related to the Video Pipeline of the + * DisplayPort Subsystem. + * + * Features supported by this driver + * - Live Video and Graphics input. + * - Non-Live Video Graphics input. + * - Output Formats Supported - RGB, YUV444, YUV4222. + * + * + * 
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -----------------------------------------------
+ * 1.0   aad  06/24/17 Initial release.
+ * 2.0   aad  10/07/17 Added Enums for Video and Audio sources.
+ *
+ * +*******************************************************************************/ +#ifndef XAVBUF_H_ +/* Prevent circular inclusions by using protection macros. */ +#define XAVBUF_H_ + + +/******************************* Include Files ********************************/ +#include "xavbuf_hw.h" +#include "sleep.h" +/****************************** Type Definitions ******************************/ +/** + * This typedef describes all the Video Formats supported by the driver + */ +typedef enum { + //Non-Live Video Formats + CbY0CrY1, + CrY0CbY1, + Y0CrY1Cb, + Y0CbY1Cr, + YV16, + YV24, + YV16Ci, + MONOCHROME, + YV16Ci2, + YUV444, + RGB888, + RGBA8880, + RGB888_10BPC, + YUV444_10BPC, + YV16Ci2_10BPC, + YV16Ci_10BPC, + YV16_10BPC, + YV24_10BPC, + MONOCHROME_10BPC, + YV16_420, + YV16Ci_420, + YV16Ci2_420, + YV16_420_10BPC, + YV16Ci_420_10BPC, + YV16Ci2_420_10BPC, + + // Non-Live Graphics formats + RGBA8888, + ABGR8888, + RGB888_GFX, + BGR888, + RGBA5551, + RGBA4444, + RGB565, + BPP8, + BPP4, + BPP2, + BPP1, + YUV422, + YOnly, + + //Live Input/Output Video/Graphics Formats + RGB_6BPC, + RGB_8BPC, + RGB_10BPC, + RGB_12BPC, + YCbCr444_6BPC, + YCbCr444_8BPC, + YCbCr444_10BPC, + YCbCr444_12BPC, + YCbCr422_8BPC, + YCbCr422_10BPC, + YCbCr422_12BPC, + YOnly_8BPC, + YOnly_10BPC, + YOnly_12BPC, +} XAVBuf_VideoFormat; + +/** + * This data structure describes video planes. + */ +typedef enum { + Interleaved, + SemiPlanar, + Planar +} XAVBuf_VideoModes; + +/** + * This typedef describes the video source list + */ +typedef enum { + XAVBUF_VIDSTREAM1_LIVE, + XAVBUF_VIDSTREAM1_NONLIVE, + XAVBUF_VIDSTREAM1_TPG, + XAVBUF_VIDSTREAM1_NONE, +} XAVBuf_VideoStream; + +/** + * This typedef describes the graphics source list + */ +typedef enum { + XAVBUF_VIDSTREAM2_DISABLEGFX = 0x0, + XAVBUF_VIDSTREAM2_NONLIVE_GFX = 0x4, + XAVBUF_VIDSTREAM2_LIVE_GFX = 0x8, + XAVBUF_VIDSTREAM2_NONE = 0xC0, +} XAVBuf_GfxStream; + +/** + * This typedef describes the audio stream 1 source list + */ +typedef enum { + XAVBUF_AUDSTREAM1_LIVE = 0x00, + XAVBUF_AUDSTREAM1_NONLIVE = 0x10, + XAVBUF_AUDSTREAM1_TPG = 0x20, + XAVBUF_AUDSTREAM1_NO_AUDIO = 0x30, +} XAVBuf_AudioStream1; + +/** + * This typedef describes the audio stream 2 source list + */ +typedef enum { + XAVBUF_AUDSTREAM2_NO_AUDIO = 0X00, + XAVBUF_AUDSTREAM2_AUDIOGFX = 0X40, +} XAVBuf_AudioStream2; + +/** + * This typedef describes the attributes associated with the video formats. + */ +typedef struct { + XAVBuf_VideoFormat VideoFormat; + u8 Value; + XAVBuf_VideoModes Mode; + u32 SF[3]; + u8 SamplingEn; + u8 IsRGB; + u8 Swap; + u8 BPP; +} XAVBuf_VideoAttribute; + +/** + * This typedef stores the attributes of an audio stream + */ +typedef struct { + u32 Volume; + u8 SwapLR; +} XAVBuf_AudioAttribute; + +/** + * This typedef stores the data associated with the Audio Video input modes. + */ +typedef struct { + XAVBuf_VideoAttribute *NonLiveVideo, *NonLiveGraphics; + XAVBuf_VideoAttribute *LiveVideo, *LiveGraphics; + XAVBuf_AudioAttribute *Audio, *GraphicsAudio; + XAVBuf_VideoStream VideoSrc; + XAVBuf_GfxStream GraphicsSrc; + XAVBuf_AudioStream1 AudioSrc1; + XAVBuf_AudioStream2 AudioSrc2; + u8 AudioClk, VideoClk; +} XAVBuf_AVModes; + +/** + * This structure stores the background color information. + */ +typedef struct { + u16 RCr; + u16 GY; + u16 BCb; +} XAVBuf_BlenderBgClr; + +/** + * This typedef stores the AVBuf Configuration information. + */ +typedef struct { + u16 DeviceId; + u32 BaseAddr; +} XAVBuf_Config; + +/** + * This typedef stores all the attributes associated to the Blender block of the + * DisplayPort Subsystem + */ +typedef struct { + u8 GlobalAlphaEn; + u8 Alpha; + XAVBuf_VideoAttribute *OutputVideo; +} XAVBuf_Blender; + +/** + * The XAVBuf driver instance data. The user is required to allocate a variable + * of this type for every XAVBUF instance in the system. A pointer to this type + * is then passed to the driver API functions + */ +typedef struct { + XAVBuf_Config Config; + XAVBuf_AVModes AVMode; + XAVBuf_Blender Blender; +} XAVBuf; + + +/**************************** Function Prototypes *****************************/ + +/* xavbuf.c: Setup and initialization functions. */ +void XAVBuf_CfgInitialize(XAVBuf *InstancePtr, u32 BaseAddr, u16 DeviceId); + +/* xavbuf.c: Functions to setup the Input Video and Audio sources */ +void XAVBuf_InputVideoSelect(XAVBuf *InstancePtr, XAVBuf_VideoStream VidStream, + XAVBuf_GfxStream GfxStream); +void XAVBuf_InputAudioSelect(XAVBuf *InstancePtr, XAVBuf_AudioStream1 AudStream, + XAVBuf_AudioStream2 AudioStream2); + +/* xavbuf.c: Functions to setup the Video Format attributes */ +int XAVBuf_SetInputNonLiveVideoFormat(XAVBuf *InstancePtr, + XAVBuf_VideoFormat Format); +int XAVBuf_SetInputNonLiveGraphicsFormat(XAVBuf *InstancePtr, + XAVBuf_VideoFormat Format); +int XAVBuf_SetInputLiveVideoFormat(XAVBuf *InstancePtr, + XAVBuf_VideoFormat Format); +int XAVBuf_SetInputLiveGraphicsFormat(XAVBuf *InstancePtr, + XAVBuf_VideoFormat Format); +int XAVBuf_SetOutputVideoFormat(XAVBuf *InstancePtr, XAVBuf_VideoFormat Format); +XAVBuf_VideoAttribute *XAVBuf_GetLiveVideoAttribute(XAVBuf_VideoFormat Format); +XAVBuf_VideoAttribute *XAVBuf_GetNLiveVideoAttribute(XAVBuf_VideoFormat Format); +XAVBuf_VideoAttribute *XAVBuf_GetNLGraphicsAttribute(XAVBuf_VideoFormat Format); + +/* xavbuf.c: Functions to setup the clock sources for video and audio */ +void XAVBuf_SetAudioVideoClkSrc(XAVBuf *InstancePtr, u8 VideoClk, u8 AudioClk); + +/* xavbuf.c: Functions that setup Video and Graphics pipeline depending on the + * sources and format selected. + */ +void XAVBuf_ConfigureVideoPipeline(XAVBuf *InstancePtr); +void XAVBuf_ConfigureGraphicsPipeline(XAVBuf *InstancePtr); + +/* Functions to setup Blender Properties */ +void XAVBuf_BlendSetBgColor(XAVBuf *InstancePtr, XAVBuf_BlenderBgClr *Color); +void XAVBuf_SetBlenderAlpha(XAVBuf *InstancePtr, u8 Alpha, u8 Enable); +void XAVBuf_SoftReset(XAVBuf *InstancePtr); +void XABuf_LineResetDisable(XAVBuf *InstancePtr, u8 Disable); +void XAVBuf_ConfigureOutputVideo(XAVBuf *InstancePtr); + +/* Audio Configuration functions */ +void XAVBuf_AudioSoftReset(XAVBuf *InstancePtr); +void XAVBuf_AudioMixerVolumeControl(XAVBuf *InstancePtr, u8 Channel0Volume, + u8 Channel1Volume); + +/* DPDMA Interface functions */ +void XAVBuf_EnableGraphicsBuffers(XAVBuf *InstancePtr, u8 Enable); +void XAVBuf_EnableVideoBuffers(XAVBuf *InstancePtr, u8 Enable); +void XAVBuf_EnableAudio0Buffers(XAVBuf *InstancePtr, u8 Enable); +void XAVBuf_EnableAudio1Buffers(XAVBuf *InstancePtr, u8 Enable); + +#endif //XAVBUF_H_ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/avbuf_v2_1/src/xavbuf_clk.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/avbuf_v2_1/src/xavbuf_clk.c new file mode 100644 index 000000000..6ef5d7089 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/avbuf_v2_1/src/xavbuf_clk.c @@ -0,0 +1,561 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/******************************************************************************/ +/** + * + * @file xavbuf.c + * + * This header file contains PLL configuring functions. These Functions + * calculates and configures the PLL depending on desired frequency. + * + * @note None. + * + * 
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -----------------------------------------------
+ * 1.0   mh  06/24/17 Initial release.
+ * 2.1   tu  12/29/17 LPD and FPD offsets adjusted
+ *
+ * +*******************************************************************************/ +/******************************* Include Files ********************************/ +#include "xavbuf_clk.h" + +/**************************** Constant Definitions ****************************/ +/*Input Frequency for the PLL with precision upto two decimals*/ +#define XAVBUF_INPUT_REF_CLK 3333333333 + +/*Frequency of VCO before divider to meet jitter requirement*/ +#define XAVBUF_PLL_OUT_FREQ 1450000000 + +/* Precision of Input Ref Frequency for PLL*/ +#define XAVBUF_INPUT_FREQ_PRECISION 100 + +/* 16 bit fractional shift to get Integer */ +#define XAVBUF_PRECISION 16 +#define XAVBUF_SHIFT_DECIMAL (1 << XAVBUF_PRECISION) +#define XAVBUF_DECIMAL (XAVBUF_SHIFT_DECIMAL - 1) +#define XDPSSU_MAX_VIDEO_FREQ 300000000 + +#define XAVBUF_AUDIO_SAMPLES 512 +#define XAVBUF_AUDIO_SAMPLE_RATE_44_1 44100 +#define XAVBUF_AUDIO_SAMPLE_RATE_48_0 48000 +#define XAVBUF_EXTERNAL_DIVIDER 2 + +/* Register offsets for address manipulation */ +#define XAVBUF_REG_OFFSET 4 +#define XAVBUF_FPD_CTRL_OFFSET 12 +#define XAVBUF_LPD_CTRL_OFFSET 16 +#define MOD_3(a) ((a) % (3)) + +/*************************** Constant Variable Definitions ********************/ +/** + * This typedef enumerates capacitor resistor and lock values to be programmed. + */ +typedef struct{ + u16 cp; + u16 res; + u16 lfhf; + u16 lock_dly; + u16 lock_cnt; +}PllConfig; + +/* PLL fractional divide programming table*/ +static const PllConfig PllFracDivideTable[] = { + {3, 5, 3, 63, 1000}, + {3, 5, 3, 63, 1000}, + {3, 9, 3, 63, 1000}, + {3, 9, 3, 63, 1000}, + {3, 9, 3, 63, 1000}, + {3, 9, 3, 63, 1000}, + {3, 14, 3, 63, 1000}, + {3, 14, 3, 63, 1000}, + {3, 14, 3, 63, 1000}, + {3, 14, 3, 63, 1000}, + {3, 14, 3, 63, 1000}, + {3, 14, 3, 63, 1000}, + {3, 14, 3, 63, 1000}, + {3, 14, 3, 63, 975}, + {3, 14, 3, 63, 950}, + {3, 14, 3, 63, 925}, + {3, 1, 3, 63, 900}, + {3, 1, 3, 63, 875}, + {3, 1, 3, 63, 850}, + {3, 1, 3, 63, 850}, + {3, 1, 3, 63, 825}, + {3, 1, 3, 63, 800}, + {3, 1, 3, 63, 775}, + {3, 6, 3, 63, 775}, + {3, 6, 3, 63, 750}, + {3, 6, 3, 63, 725}, + {3, 6, 3, 63, 700}, + {3, 6, 3, 63, 700}, + {3, 6, 3, 63, 675}, + {3, 6, 3, 63, 675}, + {3, 6, 3, 63, 650}, + {3, 6, 3, 63, 650}, + {3, 6, 3, 63, 625}, + {3, 6, 3, 63, 625}, + {3, 6, 3, 63, 625}, + {3, 6, 3, 63, 600}, + {3, 6, 3, 63, 600}, + {3, 6, 3, 63, 600}, + {3, 6, 3, 63, 600}, + {3, 6, 3, 63, 600}, + {3, 10, 3, 63, 600}, + {3, 10, 3, 63, 600}, + {3, 10, 3, 63, 600}, + {3, 10, 3, 63, 600}, + {3, 10, 3, 63, 600}, + {3, 10, 3, 63, 600}, + {3, 10, 3, 63, 600}, + {3, 10, 3, 63, 600}, + {3, 10, 3, 63, 600}, + {3, 10, 3, 63, 600}, + {3, 10, 3, 63, 600}, + {3, 10, 3, 63, 600}, + {3, 10, 3, 63, 600}, + {3, 10, 3, 63, 600}, + {3, 10, 3, 63, 600}, + {3, 10, 3, 63, 600}, + {4, 6, 3, 63, 600}, + {4, 6, 3, 63, 600}, + {4, 6, 3, 63, 600}, + {4, 6, 3, 63, 600}, + {4, 6, 3, 63, 600}, + {4, 6, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600} +}; + +/******************************************************************************/ +/** + * This function initializes the parameters required to configure PLL. + * + * @param PllInstancePtr is pointer to the XAVBuf_Pll instance. + * @param Pll is the PLL chosen to be configured. + * @param Pll is the PLL chosen to be configured. + * @param CrossDomain is the bool which is used to mention if the PLL + * outputs in other domain. + * @param ExtDividerCnt is number of external divider out of VCO. + * + * @return XST_SUCCESS if PLL is configured without an error. + * XST_FAILURE otherwise. + * + * @note In order to avoid floating point usage we have a 16bit + * fractional fixed point arithmetic implementation + * +*******************************************************************************/ +static void XAVBuf_PllInitialize(XAVBuf_Pll *PllInstancePtr, + u8 Pll, u8 CrossDomain , u8 ExtDividerCnt) +{ + /* Instantiate input frequency. */ + PllInstancePtr->InputRefClk = XAVBUF_Pss_Ref_Clk; + PllInstancePtr->RefClkFreqhz = XAVBUF_INPUT_REF_CLK; + /* Turn on internal Divider*/ + PllInstancePtr->Divider = 1; + PllInstancePtr->Pll = Pll; + PllInstancePtr->ExtDividerCnt = ExtDividerCnt; + + //Check if CrossDomain is requested + if(CrossDomain) + PllInstancePtr->DomainSwitchDiv = 6; + else + PllInstancePtr->DomainSwitchDiv = 1; + //Check where PLL falls + if (Pll>2){ + PllInstancePtr->Fpd = 0; + PllInstancePtr->BaseAddress = XAVBUF_CLK_LPD_BASEADDR; + PllInstancePtr->Offset = XAVBUF_LPD_CTRL_OFFSET; + } + else{ + PllInstancePtr->Fpd = 1; + PllInstancePtr->BaseAddress = XAVBUF_CLK_FPD_BASEADDR; + PllInstancePtr->Offset = XAVBUF_FPD_CTRL_OFFSET; + } + +} + +/******************************************************************************/ +/** + * This function calculates the parameters which are required to configure PLL + * depending upon the requested frequency. + * + * @param PllInstancePtr is pointer to the XAVBuf_Pll instance + * @param FreqHz is the requested frequency to DP in Hz + * + * @return XST_SUCCESS if parameters are calculated + * XST_FAILURE otherwise. + * + * @note In order to avoid floating point usage we have a 16bit + * fractional fixed point arithmetic implementation + * +*******************************************************************************/ +static int XAVBuf_PllCalcParameterValues(XAVBuf_Pll *PllInstancePtr, + u64 FreqHz) +{ + u64 ExtDivider, Vco, VcoIntFrac; + + /* Instantiate input frequency. */ + PllInstancePtr->InputRefClk = XAVBUF_Pss_Ref_Clk; + PllInstancePtr->RefClkFreqhz = XAVBUF_INPUT_REF_CLK ; + /* Turn on internal Divider*/ + PllInstancePtr->Divider = 1; + PllInstancePtr->DomainSwitchDiv = 1; + + /* Estimate the total divider. */ + ExtDivider = (XAVBUF_PLL_OUT_FREQ / FreqHz) / + PllInstancePtr->DomainSwitchDiv; + if(ExtDivider > 63 && PllInstancePtr->ExtDividerCnt == 2){ + PllInstancePtr->ExtDivider0 = 63; + PllInstancePtr->ExtDivider1 = ExtDivider / 63; + } + else if(ExtDivider < 63){ + PllInstancePtr->ExtDivider0 = ExtDivider; + PllInstancePtr->ExtDivider1 = 1; + } + else + return XST_FAILURE; + + Vco = FreqHz *(PllInstancePtr->ExtDivider1 * + PllInstancePtr->ExtDivider0 * 2) * + PllInstancePtr->DomainSwitchDiv; + /* Calculate integer and fractional part. */ + VcoIntFrac = (Vco * XAVBUF_INPUT_FREQ_PRECISION * + XAVBUF_SHIFT_DECIMAL) / + PllInstancePtr->RefClkFreqhz ; + PllInstancePtr->Fractional = VcoIntFrac & XAVBUF_DECIMAL; + PllInstancePtr->FracIntegerFBDIV = VcoIntFrac >> XAVBUF_PRECISION; + + return XST_SUCCESS; +} + +/******************************************************************************/ +/** + * This function will Read modify and write into corresponding registers. + * + * @param BaseAddress is the base address to which the value has to be + * written. + * @param RegOffset is the relative offset from Base address. + * @param Mask is used to select the number of bits to be modified. + * @param Shift is the number bits to be shifted from LSB. + * @param Data is the Data to be written. + * + * @return None. + * + * @note None. + * +*******************************************************************************/ +static void XAVBuf_ReadModifyWriteReg(u32 BaseAddress, u32 RegOffset, u32 Mask, + u32 Shift, u32 Data) +{ + u32 RegValue; + + RegValue = XAVBuf_ReadReg(BaseAddress, RegOffset); + RegValue = (RegValue & ~Mask) | (Data << Shift); + XAVBuf_WriteReg(BaseAddress, RegOffset, RegValue); +} + +/******************************************************************************/ +/** + * This function configures PLL. + * + * @param PllInstancePtr is pointer to the XAVBuf_Pll instance. + * + * @return XST_SUCCESS if PLL is configured without an error. + * XST_FAILURE otherwise. + * + * @note None. + * +*******************************************************************************/ +static int XAVBuf_ConfigurePll(XAVBuf_Pll *PllInstancePtr) +{ + u64 BaseAddress = PllInstancePtr->BaseAddress; + u64 timer = 0; + u32 RegPll = 0; + u8 Pll = PllInstancePtr->Pll; + + RegPll |= XAVBUF_ENABLE_BIT << XAVBUF_PLL_CTRL_BYPASS_SHIFT; + RegPll |= PllInstancePtr->FracIntegerFBDIV << + XAVBUF_PLL_CTRL_FBDIV_SHIFT; + RegPll |= PllInstancePtr->Divider << XAVBUF_PLL_CTRL_DIV2_SHIFT; + RegPll |= PllInstancePtr->InputRefClk << XAVBUF_PLL_CTRL_PRE_SRC_SHIFT; + XAVBuf_WriteReg(BaseAddress, XAVBUF_PLL_CTRL + (MOD_3(Pll) * + PllInstancePtr->Offset), RegPll); + RegPll = 0; + /* Set the values for lock dly, lock counter, capacitor and resistor. */ + RegPll |= + PllFracDivideTable[PllInstancePtr->FracIntegerFBDIV -25].cp + << XAVBUF_PLL_CFG_CP_SHIFT; + RegPll |= + PllFracDivideTable[PllInstancePtr->FracIntegerFBDIV -25].res + << XAVBUF_PLL_CFG_RES_SHIFT; + RegPll |= + PllFracDivideTable[PllInstancePtr->FracIntegerFBDIV -25].lfhf + << XAVBUF_PLL_CFG_LFHF_SHIFT; + RegPll |= + PllFracDivideTable[PllInstancePtr->FracIntegerFBDIV -25].lock_dly + << XAVBUF_PLL_CFG_LOCK_DLY_SHIFT; + RegPll |= + PllFracDivideTable[PllInstancePtr->FracIntegerFBDIV -25].lock_cnt + << XAVBUF_PLL_CFG_LOCK_CNT_SHIFT; + XAVBuf_WriteReg(BaseAddress, XAVBUF_PLL_CFG + (MOD_3(Pll) * + PllInstancePtr->Offset), RegPll); + /* Enable and set Fractional Data. */ + XAVBuf_WriteReg(BaseAddress, XAVBUF_PLL_FRAC_CFG + (MOD_3(Pll) * + PllInstancePtr->Offset), (1 << XAVBUF_PLL_FRAC_CFG_ENABLED_SHIFT) | + (PllInstancePtr->Fractional << + XAVBUF_PLL_FRAC_CFG_DATA_SHIFT)); + /* Assert reset to the PLL. */ + XAVBuf_ReadModifyWriteReg(BaseAddress, XAVBUF_PLL_CTRL + (MOD_3(Pll) * + PllInstancePtr->Offset), + XAVBUF_PLL_CTRL_RESET_MASK, XAVBUF_PLL_CTRL_RESET_SHIFT, + XAVBUF_ENABLE_BIT); + + /* Deassert reset to the PLL. */ + XAVBuf_ReadModifyWriteReg(BaseAddress, XAVBUF_PLL_CTRL + (MOD_3(Pll) * + PllInstancePtr->Offset), + XAVBUF_PLL_CTRL_RESET_MASK, XAVBUF_PLL_CTRL_RESET_SHIFT, + XAVBUF_DISABLE_BIT); + + while(!(XAVBuf_ReadReg(BaseAddress, XAVBUF_PLL_STATUS - + ((1 - PllInstancePtr->Fpd) * XAVBUF_REG_OFFSET)) & + (1 << MOD_3(Pll)))) + if(++timer > 1000) + return XST_FAILURE; + + /* Deassert Bypass. */ + XAVBuf_ReadModifyWriteReg(BaseAddress, XAVBUF_PLL_CTRL + (MOD_3(Pll) * + PllInstancePtr->Offset), + XAVBUF_PLL_CTRL_BYPASS_MASK, XAVBUF_PLL_CTRL_BYPASS_SHIFT, + XAVBUF_DISABLE_BIT); + + if(PllInstancePtr->DomainSwitchDiv != 1) + XAVBuf_ReadModifyWriteReg(BaseAddress, (XAVBUF_DOMAIN_SWITCH_CTRL + + (MOD_3(Pll) * XAVBUF_REG_OFFSET) - ((1 - PllInstancePtr->Fpd) + * XAVBUF_REG_OFFSET)), + XAVBUF_DOMAIN_SWITCH_DIVISOR0_MASK, + XAVBUF_DOMAIN_SWITCH_DIVISOR0_SHIFT, + PllInstancePtr->DomainSwitchDiv); + usleep(1); + + return XST_SUCCESS; + +} + +/******************************************************************************/ +/** + * This function configures Configures external divider. + * + * @param PllInstancePtr is pointer to the XAVBuf_Pll instance. + * + * @return None. + * + * @note None. + * +*******************************************************************************/ +static void XAVBuf_ConfigureExtDivider(XAVBuf_Pll *PllInstancePtr, + u64 BaseAddress, u32 Offset) +{ + XAVBuf_ReadModifyWriteReg(BaseAddress, Offset, + XAVBUF_VIDEO_REF_CTRL_CLKACT_MASK, + XAVBUF_VIDEO_REF_CTRL_CLKACT_SHIFT, XAVBUF_DISABLE_BIT); + XAVBuf_ReadModifyWriteReg(BaseAddress, Offset, + XAVBUF_VIDEO_REF_CTRL_DIVISOR1_MASK, + XAVBUF_VIDEO_REF_CTRL_DIVISOR1_SHIFT, + PllInstancePtr->ExtDivider1); + XAVBuf_ReadModifyWriteReg(BaseAddress, Offset, + XAVBUF_VIDEO_REF_CTRL_DIVISOR0_MASK, + XAVBUF_VIDEO_REF_CTRL_DIVISOR0_SHIFT, + PllInstancePtr->ExtDivider0); + XAVBuf_ReadModifyWriteReg(BaseAddress, Offset, + XAVBUF_VIDEO_REF_CTRL_CLKACT_MASK, + XAVBUF_VIDEO_REF_CTRL_CLKACT_SHIFT, XAVBUF_ENABLE_BIT); + XAVBuf_WriteReg(BaseAddress, Offset, 0x1011003); +} + +/******************************************************************************/ +/** + * This function calls API to calculate and configure PLL with desired frequency + * for Video. + * + * @param FreqHz is the desired frequency in Hz. + * + * @return XST_SUCCESS if PLL is configured without an error. + * XST_FAILURE otherwise. + * + * @note The Pll used is design specific. + * +*******************************************************************************/ +int XAVBuf_SetPixelClock(u64 FreqHz) +{ + u32 PllAssigned; + XAVBuf_Pll PllInstancePtr; + u8 Pll, CrossDomain, Flag; + + /*Verify Input Arguments*/ + Xil_AssertNonvoid(FreqHz < XDPSSU_MAX_VIDEO_FREQ); + + PllAssigned = XAVBuf_ReadReg(XAVBUF_CLK_FPD_BASEADDR, + XAVBUF_VIDEO_REF_CTRL) & XAVBUF_VIDEO_REF_CTRL_SRCSEL_MASK; + + switch (PllAssigned) { + case XAVBUF_VPLL_SRC_SEL: + Pll = VPLL; + CrossDomain = 0; + break; + case XAVBUF_DPLL_SRC_SEL: + Pll = DPLL; + CrossDomain = 0; + break; + case XAVBUF_RPLL_TO_FPD_SRC_SEL: + Pll = RPLL; + CrossDomain = 1; + break; + default: + return XST_FAILURE; + } + + /*Calculate configure PLL and External Divider*/ + XAVBuf_PllInitialize(&PllInstancePtr, Pll, CrossDomain, + XAVBUF_EXTERNAL_DIVIDER); + Flag = XAVBuf_PllCalcParameterValues(&PllInstancePtr, FreqHz); + if(Flag != 0) + return XST_FAILURE; + Flag = XAVBuf_ConfigurePll(&PllInstancePtr); + if(Flag != 0) + return XST_FAILURE; + XAVBuf_ConfigureExtDivider(&PllInstancePtr, XAVBUF_CLK_FPD_BASEADDR, + XAVBUF_VIDEO_REF_CTRL); + + return XST_SUCCESS; +} + +/******************************************************************************/ +/** + * This function calls API to calculate and configure PLL with desired + * frequency for Audio. + * + * @param FreqHz is the desired frequency in Hz. + * + * @return XST_SUCCESS if PLL is configured without an error. + * XST_FAILURE otherwise. + * + * @note The Pll used is design specific. + * +*******************************************************************************/ +int XAVBuf_SetAudioClock(u64 FreqHz) +{ + u32 Flag, PllAssigned; + u8 Pll, CrossDomain; + XAVBuf_Pll XAVBuf_RPllInstancePtr; + + /*Verify Input Arguments*/ + Flag = (FreqHz == (XAVBUF_AUDIO_SAMPLE_RATE_44_1 * + XAVBUF_AUDIO_SAMPLES)) || + (FreqHz == (XAVBUF_AUDIO_SAMPLE_RATE_48_0 * + XAVBUF_AUDIO_SAMPLES)); + Xil_AssertNonvoid(Flag); + + PllAssigned = XAVBuf_ReadReg(XAVBUF_CLK_FPD_BASEADDR, + XAVBUF_AUDIO_REF_CTRL) & + XAVBUF_AUDIO_REF_CTRL_SRCSEL_MASK; + + switch (PllAssigned) { + case XAVBUF_VPLL_SRC_SEL: + Pll = VPLL; + CrossDomain = 0; + break; + case XAVBUF_DPLL_SRC_SEL: + Pll = DPLL; + CrossDomain = 0; + break; + case XAVBUF_RPLL_TO_FPD_SRC_SEL: + Pll = RPLL; + CrossDomain = 1; + break; + default: + return XST_FAILURE; + } + + /*Calculate configure PLL and External Divider*/ + XAVBuf_PllInitialize(&XAVBuf_RPllInstancePtr, Pll, CrossDomain, + XAVBUF_EXTERNAL_DIVIDER); + Flag = XAVBuf_PllCalcParameterValues(&XAVBuf_RPllInstancePtr, FreqHz); + if(Flag != 0) + return XST_FAILURE; + Flag = XAVBuf_ConfigurePll(&XAVBuf_RPllInstancePtr); + if(Flag != 0) + return XST_FAILURE; + XAVBuf_ConfigureExtDivider(&XAVBuf_RPllInstancePtr, + XAVBUF_CLK_FPD_BASEADDR, XAVBUF_AUDIO_REF_CTRL); + + return XST_SUCCESS; +} diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/avbuf_v2_1/src/xavbuf_clk.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/avbuf_v2_1/src/xavbuf_clk.h new file mode 100644 index 000000000..91ca3b5ed --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/avbuf_v2_1/src/xavbuf_clk.h @@ -0,0 +1,97 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/******************************************************************************/ +/** + * + * @file xavbuf_clk.h + * + * This header file contains the identifiers and low-level driver functions (or + * macros) that can be used to configure PLL to generate required frequency. + * + * @note None. + * + * 
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -----------------------------------------------
+ * 1.0   mh  06/24/17 Initial release.
+ * 2.1   tu  12/29/17 LPD and FPD offsets adjusted
+ *
+ * +*******************************************************************************/ + +#ifndef XAVBUF_CLK_H_ +#define XAVBUF_CLK_H_ + +/******************************* Include Files ********************************/ +#include "xavbuf_hw.h" +#include "xstatus.h" +#include "sleep.h" + +/****************************** Type Definitions ******************************/ +/** + * This enum enumerates various PLL + */ +enum PLL{ + APLL = 0, + DPLL = 1, + VPLL = 2, + IOPLL = 3, + RPLL = 4 +}; + +/** + * This typedef enumerates various variables used to configure Pll + */ +typedef struct { + u64 BaseAddress; + u64 Fractional; + u64 RefClkFreqhz; + u32 Divider; + u8 Offset; + u8 ClkDividBy2; + u8 ExtDivider0; + u8 ExtDivider1; + u8 ExtDividerCnt; + u8 DomainSwitchDiv; + u8 FracIntegerFBDIV; + u8 IntegerFBDIV; + u8 InputRefClk; + u8 Fpd; + u8 Pll; +}XAVBuf_Pll; + +/**************************** Function Prototypes *****************************/ +int XAVBuf_SetPixelClock(u64 FreqHz); +int XAVBuf_SetAudioClock(u64 FreqHz); +#endif /* XAVBUF_CLK_H_ */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_3/src/xemacps_g.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/avbuf_v2_1/src/xavbuf_g.c similarity index 87% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_3/src/xemacps_g.c rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/avbuf_v2_1/src/xavbuf_g.c index db734b924..325e01b47 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_3/src/xemacps_g.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/avbuf_v2_1/src/xavbuf_g.c @@ -5,7 +5,7 @@ * Version: * DO NOT EDIT. * -* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.* +* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.* *Permission is hereby granted, free of charge, to any person obtaining a copy *of this software and associated documentation files (the Software), to deal *in the Software without restriction, including without limitation the rights @@ -38,17 +38,17 @@ *******************************************************************/ #include "xparameters.h" -#include "xemacps.h" +#include "xavbuf.h" /* * The configuration table for devices */ -XEmacPs_Config XEmacPs_ConfigTable[] = +XAVBuf_Config XAVBuf_ConfigTable[XPAR_XAVBUF_NUM_INSTANCES] = { { - XPAR_PSU_ETHERNET_3_DEVICE_ID, - XPAR_PSU_ETHERNET_3_BASEADDR + XPAR_PSU_DP_DEVICE_ID, + XPAR_PSU_DP_BASEADDR } }; diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/avbuf_v2_1/src/xavbuf_hw.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/avbuf_v2_1/src/xavbuf_hw.h new file mode 100644 index 000000000..3454fa071 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/avbuf_v2_1/src/xavbuf_hw.h @@ -0,0 +1,1675 @@ +/******************************************************************************* + * + * Copyright C 2014 Xilinx, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * Use of the Software is limited solely to applications: + * (a) running on a Xilinx device, or + * (b) that interact with a Xilinx device through a bus or interconnect. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of the Xilinx shall not be used + * in advertising or otherwise to promote the sale, use or other dealings in + * this Software without prior written authorization from Xilinx. + * +*******************************************************************************/ +/******************************************************************************/ +/** + * + * @file xavbuf_hw.h + * + * This header file contains macros that can be used to access the device + * + * @note None. + * + * 
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -----------------------------------------------
+ * 1.0	 aad 02/24/17	Initial Release
+ * 1.0   mh  06/24/17	Added Clock related register information
+ * 2.0   aad 10/07/17   Removed Macros related to Video and Audio Src
+ *
+ * +*******************************************************************************/ +#ifndef XAVBUF_HW_H_ +/* Prevent circular inclusions by using protection macros. */ +#define XAVBUF_HW_H_ + +#ifdef __cplusplus +extern "C" { +#endif +/***************************** Include Files **********************************/ + +#include "xil_io.h" +#include "xil_types.h" + +/************************** Constant Definitions ******************************/ + +/******************************************************************************/ +/** + * Address mapping for the DisplayPort TX core. + * +*******************************************************************************/ + +#define XAVBUF_BASEADDR 0xFD4A0000 +/** + * * Register: XAVBUF_V_BLEND_BG_CLR_0 + * */ +#define XAVBUF_V_BLEND_BG_CLR_0 0X0000A000 + +#define XAVBUF_V_BLEND_BG_CLR_0_CLR0_SHIFT 0 +#define XAVBUF_V_BLEND_BG_CLR_0_CLR0_WIDTH 12 +#define XAVBUF_V_BLEND_BG_CLR_0_CLR0_MASK 0X00000FFF + +/** + * * Register: XAVBUF_V_BLEND_BG_CLR_1 + * */ +#define XAVBUF_V_BLEND_BG_CLR_1 0X0000A004 + +#define XAVBUF_V_BLEND_BG_CLR_1_CLR1_SHIFT 0 +#define XAVBUF_V_BLEND_BG_CLR_1_CLR1_WIDTH 12 +#define XAVBUF_V_BLEND_BG_CLR_1_CLR1_MASK 0X00000FFF + +/** + * * Register: XAVBUF_V_BLEND_BG_CLR_2 + * */ +#define XAVBUF_V_BLEND_BG_CLR_2 0X0000A008 + +#define XAVBUF_V_BLEND_BG_CLR_2_CLR2_SHIFT 0 +#define XAVBUF_V_BLEND_BG_CLR_2_CLR2_WIDTH 12 +#define XAVBUF_V_BLEND_BG_CLR_2_CLR2_MASK 0X00000FFF + +/** + * * Register: XAVBUF_V_BLEND_SET_GLOBAL_ALPHA_REG + * */ +#define XAVBUF_V_BLEND_SET_GLOBAL_ALPHA_REG 0X0000A00C + +#define XAVBUF_V_BLEND_SET_GLOBAL_ALPHA_REG_VALUE_SHIFT 1 +#define XAVBUF_V_BLEND_SET_GLOBAL_ALPHA_REG_VALUE_WIDTH 8 +#define XAVBUF_V_BLEND_SET_GLOBAL_ALPHA_REG_VALUE_MASK 0X000001FE + +#define XAVBUF_V_BLEND_SET_GLOBAL_ALPHA_REG_EN_SHIFT 0 +#define XAVBUF_V_BLEND_SET_GLOBAL_ALPHA_REG_EN_WIDTH 1 +#define XAVBUF_V_BLEND_SET_GLOBAL_ALPHA_REG_EN_MASK 0X00000001 + +/** + * * Register: XAVBUF_V_BLEND_OUTPUT_VID_FORMAT + * */ +#define XAVBUF_V_BLEND_OUTPUT_VID_FORMAT 0X0000A014 + +#define XAVBUF_V_BLEND_OUTPUT_VID_FORMAT_EN_DOWNSAMPLE_SHIFT 4 +#define XAVBUF_V_BLEND_OUTPUT_VID_FORMAT_EN_DOWNSAMPLE_WIDTH 1 +#define XAVBUF_V_BLEND_OUTPUT_VID_FORMAT_EN_DOWNSAMPLE_MASK 0X00000010 + +#define XAVBUF_V_BLEND_OUTPUT_VID_FORMAT_VID_FORMAT_SHIFT 0 +#define XAVBUF_V_BLEND_OUTPUT_VID_FORMAT_VID_FORMAT_WIDTH 3 +#define XAVBUF_V_BLEND_OUTPUT_VID_FORMAT_VID_FORMAT_MASK 0X00000007 + +/** + * * Register: XAVBUF_V_BLEND_LAYER0_CONTROL + * */ +#define XAVBUF_V_BLEND_LAYER0_CONTROL 0X0000A018 + +#define XAVBUF_V_BLEND_LAYER0_CONTROL_BYPASS_SHIFT 8 +#define XAVBUF_V_BLEND_LAYER0_CONTROL_BYPASS_WIDTH 1 +#define XAVBUF_V_BLEND_LAYER0_CONTROL_BYPASS_MASK 0X00000100 + +#define XAVBUF_V_BLEND_LAYER0_CONTROL_RGB_MODE_SHIFT 1 +#define XAVBUF_V_BLEND_LAYER0_CONTROL_RGB_MODE_WIDTH 1 +#define XAVBUF_V_BLEND_LAYER0_CONTROL_RGB_MODE_MASK 0X00000002 + +#define XAVBUF_V_BLEND_LAYER0_CONTROL_EN_US_SHIFT 0 +#define XAVBUF_V_BLEND_LAYER0_CONTROL_EN_US_WIDTH 1 +#define XAVBUF_V_BLEND_LAYER0_CONTROL_EN_US_MASK 0X00000001 + +/** + * * Register: XAVBUF_V_BLEND_LAYER1_CONTROL + * */ +#define XAVBUF_V_BLEND_LAYER1_CONTROL 0X0000A01C + +#define XAVBUF_V_BLEND_LAYER1_CONTROL_BYPASS_SHIFT 8 +#define XAVBUF_V_BLEND_LAYER1_CONTROL_BYPASS_WIDTH 1 +#define XAVBUF_V_BLEND_LAYER1_CONTROL_BYPASS_MASK 0X00000100 + +#define XAVBUF_V_BLEND_LAYER1_CONTROL_RGB_MODE_SHIFT 1 +#define XAVBUF_V_BLEND_LAYER1_CONTROL_RGB_MODE_WIDTH 1 +#define XAVBUF_V_BLEND_LAYER1_CONTROL_RGB_MODE_MASK 0X00000002 + +#define XAVBUF_V_BLEND_LAYER1_CONTROL_EN_US_SHIFT 0 +#define XAVBUF_V_BLEND_LAYER1_CONTROL_EN_US_WIDTH 1 +#define XAVBUF_V_BLEND_LAYER1_CONTROL_EN_US_MASK 0X00000001 + +/** + * * Register: XAVBUF_V_BLEND_RGB2YCBCR_COEFF0 + * */ +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF0 0X0000A020 + +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF0_RGB2Y_C0_SHIFT 0 +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF0_RGB2Y_C0_WIDTH 15 +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF0_RGB2Y_C0_MASK 0X00007FFF + +/** + * * Register: XAVBUF_V_BLEND_RGB2YCBCR_COEFF1 + * */ +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF1 0X0000A024 + +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF1_RGB2Y_C1_SHIFT 0 +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF1_RGB2Y_C1_WIDTH 15 +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF1_RGB2Y_C1_MASK 0X00007FFF + +/** + * * Register: XAVBUF_V_BLEND_RGB2YCBCR_COEFF2 + * */ +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF2 0X0000A028 + +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF2_RGB2Y_C2_SHIFT 0 +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF2_RGB2Y_C2_WIDTH 15 +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF2_RGB2Y_C2_MASK 0X00007FFF + +/** + * * Register: XAVBUF_V_BLEND_RGB2YCBCR_COEFF3 + * */ +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF3 0X0000A02C + +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF3_RGB2Y_C3_SHIFT 0 +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF3_RGB2Y_C3_WIDTH 15 +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF3_RGB2Y_C3_MASK 0X00007FFF + +/** + * * Register: XAVBUF_V_BLEND_RGB2YCBCR_COEFF4 + * */ +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF4 0X0000A030 + +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF4_RGB2Y_C4_SHIFT 0 +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF4_RGB2Y_C4_WIDTH 15 +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF4_RGB2Y_C4_MASK 0X00007FFF + +/** + * * Register: XAVBUF_V_BLEND_RGB2YCBCR_COEFF5 + * */ +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF5 0X0000A034 + +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF5_RGB2Y_C5_SHIFT 0 +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF5_RGB2Y_C5_WIDTH 15 +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF5_RGB2Y_C5_MASK 0X00007FFF + +/** + * * Register: XAVBUF_V_BLEND_RGB2YCBCR_COEFF6 + * */ +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF6 0X0000A038 + +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF6_RGB2Y_C6_SHIFT 0 +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF6_RGB2Y_C6_WIDTH 15 +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF6_RGB2Y_C6_MASK 0X00007FFF + +/** + * * Register: XAVBUF_V_BLEND_RGB2YCBCR_COEFF7 + * */ +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF7 0X0000A03C + +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF7_RGB2Y_C7_SHIFT 0 +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF7_RGB2Y_C7_WIDTH 15 +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF7_RGB2Y_C7_MASK 0X00007FFF + +/** + * * Register: XAVBUF_V_BLEND_RGB2YCBCR_COEFF8 + * */ +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF8 0X0000A040 + +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF8_RGB2Y_C8_SHIFT 0 +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF8_RGB2Y_C8_WIDTH 15 +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF8_RGB2Y_C8_MASK 0X00007FFF + +/** + * * Register: XAVBUF_V_BLEND_IN1CSC_COEFF0 + * */ +#define XAVBUF_V_BLEND_IN1CSC_COEFF0 0X0000A044 + +#define XAVBUF_V_BLEND_IN1CSC_COEFF0_Y2R_C0_SHIFT 0 +#define XAVBUF_V_BLEND_IN1CSC_COEFF0_Y2R_C0_WIDTH 15 +#define XAVBUF_V_BLEND_IN1CSC_COEFF0_Y2R_C0_MASK 0X00007FFF + +/** + * * Register: XAVBUF_V_BLEND_IN1CSC_COEFF1 + * */ +#define XAVBUF_V_BLEND_IN1CSC_COEFF1 0X0000A048 + +#define XAVBUF_V_BLEND_IN1CSC_COEFF1_Y2R_C1_SHIFT 0 +#define XAVBUF_V_BLEND_IN1CSC_COEFF1_Y2R_C1_WIDTH 15 +#define XAVBUF_V_BLEND_IN1CSC_COEFF1_Y2R_C1_MASK 0X00007FFF + +/** + * * Register: XAVBUF_V_BLEND_IN1CSC_COEFF2 + * */ +#define XAVBUF_V_BLEND_IN1CSC_COEFF2 0X0000A04C + +#define XAVBUF_V_BLEND_IN1CSC_COEFF2_Y2R_C2_SHIFT 0 +#define XAVBUF_V_BLEND_IN1CSC_COEFF2_Y2R_C2_WIDTH 15 +#define XAVBUF_V_BLEND_IN1CSC_COEFF2_Y2R_C2_MASK 0X00007FFF + +/** + * * Register: XAVBUF_V_BLEND_IN1CSC_COEFF3 + * */ +#define XAVBUF_V_BLEND_IN1CSC_COEFF3 0X0000A050 + +#define XAVBUF_V_BLEND_IN1CSC_COEFF3_Y2R_C3_SHIFT 0 +#define XAVBUF_V_BLEND_IN1CSC_COEFF3_Y2R_C3_WIDTH 15 +#define XAVBUF_V_BLEND_IN1CSC_COEFF3_Y2R_C3_MASK 0X00007FFF + +/** + * * Register: XAVBUF_V_BLEND_IN1CSC_COEFF4 + * */ +#define XAVBUF_V_BLEND_IN1CSC_COEFF4 0X0000A054 + +#define XAVBUF_V_BLEND_IN1CSC_COEFF4_Y2R_C4_SHIFT 0 +#define XAVBUF_V_BLEND_IN1CSC_COEFF4_Y2R_C4_WIDTH 15 +#define XAVBUF_V_BLEND_IN1CSC_COEFF4_Y2R_C4_MASK 0X00007FFF + +/** + * * Register: XAVBUF_V_BLEND_IN1CSC_COEFF5 + * */ +#define XAVBUF_V_BLEND_IN1CSC_COEFF5 0X0000A058 + +#define XAVBUF_V_BLEND_IN1CSC_COEFF5_Y2R_C5_SHIFT 0 +#define XAVBUF_V_BLEND_IN1CSC_COEFF5_Y2R_C5_WIDTH 15 +#define XAVBUF_V_BLEND_IN1CSC_COEFF5_Y2R_C5_MASK 0X00007FFF + +/** + * * Register: XAVBUF_V_BLEND_IN1CSC_COEFF6 + * */ +#define XAVBUF_V_BLEND_IN1CSC_COEFF6 0X0000A05C + +#define XAVBUF_V_BLEND_IN1CSC_COEFF6_Y2R_C6_SHIFT 0 +#define XAVBUF_V_BLEND_IN1CSC_COEFF6_Y2R_C6_WIDTH 15 +#define XAVBUF_V_BLEND_IN1CSC_COEFF6_Y2R_C6_MASK 0X00007FFF + +/** + * * Register: XAVBUF_V_BLEND_IN1CSC_COEFF7 + * */ +#define XAVBUF_V_BLEND_IN1CSC_COEFF7 0X0000A060 + +#define XAVBUF_V_BLEND_IN1CSC_COEFF7_Y2R_C7_SHIFT 0 +#define XAVBUF_V_BLEND_IN1CSC_COEFF7_Y2R_C7_WIDTH 15 +#define XAVBUF_V_BLEND_IN1CSC_COEFF7_Y2R_C7_MASK 0X00007FFF + +/** + * * Register: XAVBUF_V_BLEND_IN1CSC_COEFF8 + * */ +#define XAVBUF_V_BLEND_IN1CSC_COEFF8 0X0000A064 + +#define XAVBUF_V_BLEND_IN1CSC_COEFF8_Y2R_C8_SHIFT 0 +#define XAVBUF_V_BLEND_IN1CSC_COEFF8_Y2R_C8_WIDTH 15 +#define XAVBUF_V_BLEND_IN1CSC_COEFF8_Y2R_C8_MASK 0X00007FFF + +/** + * * Register: XAVBUF_V_BLEND_LUMA_IN1CSC_OFFSET + * */ +#define XAVBUF_V_BLEND_LUMA_IN1CSC_OFFSET 0X0000A068 + +#define XAVBUF_V_BLEND_LUMA_IN1CSC_OFFSET_POST_OFFSET_SHIFT 16 +#define XAVBUF_V_BLEND_LUMA_IN1CSC_OFFSET_POST_OFFSET_WIDTH 13 +#define XAVBUF_V_BLEND_LUMA_IN1CSC_OFFSET_POST_OFFSET_MASK 0X1FFF0000 + +#define XAVBUF_V_BLEND_LUMA_IN1CSC_OFFSET_PRE_OFFSET_SHIFT 0 +#define XAVBUF_V_BLEND_LUMA_IN1CSC_OFFSET_PRE_OFFSET_WIDTH 13 +#define XAVBUF_V_BLEND_LUMA_IN1CSC_OFFSET_PRE_OFFSET_MASK 0X00001FFF + +/** + * * Register: XAVBUF_V_BLEND_CR_IN1CSC_OFFSET + * */ +#define XAVBUF_V_BLEND_CR_IN1CSC_OFFSET 0X0000A06C + +#define XAVBUF_V_BLEND_CR_IN1CSC_OFFSET_POST_OFFSET_SHIFT 16 +#define XAVBUF_V_BLEND_CR_IN1CSC_OFFSET_POST_OFFSET_WIDTH 13 +#define XAVBUF_V_BLEND_CR_IN1CSC_OFFSET_POST_OFFSET_MASK 0X1FFF0000 + +#define XAVBUF_V_BLEND_CR_IN1CSC_OFFSET_PRE_OFFSET_SHIFT 0 +#define XAVBUF_V_BLEND_CR_IN1CSC_OFFSET_PRE_OFFSET_WIDTH 13 +#define XAVBUF_V_BLEND_CR_IN1CSC_OFFSET_PRE_OFFSET_MASK 0X00001FFF + +/** + * * Register: XAVBUF_V_BLEND_CB_IN1CSC_OFFSET + * */ +#define XAVBUF_V_BLEND_CB_IN1CSC_OFFSET 0X0000A070 + +#define XAVBUF_V_BLEND_CB_IN1CSC_OFFSET_POST_OFFSET_SHIFT 16 +#define XAVBUF_V_BLEND_CB_IN1CSC_OFFSET_POST_OFFSET_WIDTH 13 +#define XAVBUF_V_BLEND_CB_IN1CSC_OFFSET_POST_OFFSET_MASK 0X1FFF0000 + +#define XAVBUF_V_BLEND_CB_IN1CSC_OFFSET_PRE_OFFSET_SHIFT 0 +#define XAVBUF_V_BLEND_CB_IN1CSC_OFFSET_PRE_OFFSET_WIDTH 13 +#define XAVBUF_V_BLEND_CB_IN1CSC_OFFSET_PRE_OFFSET_MASK 0X00001FFF + +/** + * * Register: XAVBUF_V_BLEND_LUMA_OUTCSC_OFFSET + * */ +#define XAVBUF_V_BLEND_LUMA_OUTCSC_OFFSET 0X0000A074 + +#define XAVBUF_V_BLEND_LUMA_OUTCSC_OFFSET_POST_OFFSET_SHIFT 16 +#define XAVBUF_V_BLEND_LUMA_OUTCSC_OFFSET_POST_OFFSET_WIDTH 13 +#define XAVBUF_V_BLEND_LUMA_OUTCSC_OFFSET_POST_OFFSET_MASK 0X1FFF0000 + +#define XAVBUF_V_BLEND_LUMA_OUTCSC_OFFSET_PRE_OFFSET_SHIFT 0 +#define XAVBUF_V_BLEND_LUMA_OUTCSC_OFFSET_PRE_OFFSET_WIDTH 13 +#define XAVBUF_V_BLEND_LUMA_OUTCSC_OFFSET_PRE_OFFSET_MASK 0X00001FFF + +/** + * * Register: XAVBUF_V_BLEND_CR_OUTCSC_OFFSET + * */ +#define XAVBUF_V_BLEND_CR_OUTCSC_OFFSET 0X0000A078 + +#define XAVBUF_V_BLEND_CR_OUTCSC_OFFSET_POST_OFFSET_SHIFT 16 +#define XAVBUF_V_BLEND_CR_OUTCSC_OFFSET_POST_OFFSET_WIDTH 13 +#define XAVBUF_V_BLEND_CR_OUTCSC_OFFSET_POST_OFFSET_MASK 0X1FFF0000 + +#define XAVBUF_V_BLEND_CR_OUTCSC_OFFSET_PRE_OFFSET_SHIFT 0 +#define XAVBUF_V_BLEND_CR_OUTCSC_OFFSET_PRE_OFFSET_WIDTH 13 +#define XAVBUF_V_BLEND_CR_OUTCSC_OFFSET_PRE_OFFSET_MASK 0X00001FFF + +/** + * * Register: XAVBUF_V_BLEND_CB_OUTCSC_OFFSET + * */ +#define XAVBUF_V_BLEND_CB_OUTCSC_OFFSET 0X0000A07C + +#define XAVBUF_V_BLEND_CB_OUTCSC_OFFSET_POST_OFFSET_SHIFT 16 +#define XAVBUF_V_BLEND_CB_OUTCSC_OFFSET_POST_OFFSET_WIDTH 13 +#define XAVBUF_V_BLEND_CB_OUTCSC_OFFSET_POST_OFFSET_MASK 0X1FFF0000 + +#define XAVBUF_V_BLEND_CB_OUTCSC_OFFSET_PRE_OFFSET_SHIFT 0 +#define XAVBUF_V_BLEND_CB_OUTCSC_OFFSET_PRE_OFFSET_WIDTH 13 +#define XAVBUF_V_BLEND_CB_OUTCSC_OFFSET_PRE_OFFSET_MASK 0X00001FFF + +/** + * * Register: XAVBUF_V_BLEND_IN2CSC_COEFF0 + * */ +#define XAVBUF_V_BLEND_IN2CSC_COEFF0 0X0000A080 + +#define XAVBUF_V_BLEND_IN2CSC_COEFF0_Y2R_C0_SHIFT 0 +#define XAVBUF_V_BLEND_IN2CSC_COEFF0_Y2R_C0_WIDTH 15 +#define XAVBUF_V_BLEND_IN2CSC_COEFF0_Y2R_C0_MASK 0X00007FFF + +/** + * * Register: XAVBUF_V_BLEND_IN2CSC_COEFF1 + * */ +#define XAVBUF_V_BLEND_IN2CSC_COEFF1 0X0000A084 + +#define XAVBUF_V_BLEND_IN2CSC_COEFF1_Y2R_C1_SHIFT 0 +#define XAVBUF_V_BLEND_IN2CSC_COEFF1_Y2R_C1_WIDTH 15 +#define XAVBUF_V_BLEND_IN2CSC_COEFF1_Y2R_C1_MASK 0X00007FFF + +/** + * * Register: XAVBUF_V_BLEND_IN2CSC_COEFF2 + * */ +#define XAVBUF_V_BLEND_IN2CSC_COEFF2 0X0000A088 + +#define XAVBUF_V_BLEND_IN2CSC_COEFF2_Y2R_C2_SHIFT 0 +#define XAVBUF_V_BLEND_IN2CSC_COEFF2_Y2R_C2_WIDTH 15 +#define XAVBUF_V_BLEND_IN2CSC_COEFF2_Y2R_C2_MASK 0X00007FFF + +/** + * * Register: XAVBUF_V_BLEND_IN2CSC_COEFF3 + * */ +#define XAVBUF_V_BLEND_IN2CSC_COEFF3 0X0000A08C + +#define XAVBUF_V_BLEND_IN2CSC_COEFF3_Y2R_C3_SHIFT 0 +#define XAVBUF_V_BLEND_IN2CSC_COEFF3_Y2R_C3_WIDTH 15 +#define XAVBUF_V_BLEND_IN2CSC_COEFF3_Y2R_C3_MASK 0X00007FFF + +/** + * * Register: XAVBUF_V_BLEND_IN2CSC_COEFF4 + * */ +#define XAVBUF_V_BLEND_IN2CSC_COEFF4 0X0000A090 + +#define XAVBUF_V_BLEND_IN2CSC_COEFF4_Y2R_C4_SHIFT 0 +#define XAVBUF_V_BLEND_IN2CSC_COEFF4_Y2R_C4_WIDTH 15 +#define XAVBUF_V_BLEND_IN2CSC_COEFF4_Y2R_C4_MASK 0X00007FFF + +/** + * * Register: XAVBUF_V_BLEND_IN2CSC_COEFF5 + * */ +#define XAVBUF_V_BLEND_IN2CSC_COEFF5 0X0000A094 + +#define XAVBUF_V_BLEND_IN2CSC_COEFF5_Y2R_C5_SHIFT 0 +#define XAVBUF_V_BLEND_IN2CSC_COEFF5_Y2R_C5_WIDTH 15 +#define XAVBUF_V_BLEND_IN2CSC_COEFF5_Y2R_C5_MASK 0X00007FFF + +/** + * * Register: XAVBUF_V_BLEND_IN2CSC_COEFF6 + * */ +#define XAVBUF_V_BLEND_IN2CSC_COEFF6 0X0000A098 + +#define XAVBUF_V_BLEND_IN2CSC_COEFF6_Y2R_C6_SHIFT 0 +#define XAVBUF_V_BLEND_IN2CSC_COEFF6_Y2R_C6_WIDTH 15 +#define XAVBUF_V_BLEND_IN2CSC_COEFF6_Y2R_C6_MASK 0X00007FFF + +/** + * * Register: XAVBUF_V_BLEND_IN2CSC_COEFF7 + * */ +#define XAVBUF_V_BLEND_IN2CSC_COEFF7 0X0000A09C + +#define XAVBUF_V_BLEND_IN2CSC_COEFF7_Y2R_C7_SHIFT 0 +#define XAVBUF_V_BLEND_IN2CSC_COEFF7_Y2R_C7_WIDTH 15 +#define XAVBUF_V_BLEND_IN2CSC_COEFF7_Y2R_C7_MASK 0X00007FFF + +/** + * * Register: XAVBUF_V_BLEND_IN2CSC_COEFF8 + * */ +#define XAVBUF_V_BLEND_IN2CSC_COEFF8 0X0000A0A0 + +#define XAVBUF_V_BLEND_IN2CSC_COEFF8_Y2R_C8_SHIFT 0 +#define XAVBUF_V_BLEND_IN2CSC_COEFF8_Y2R_C8_WIDTH 15 +#define XAVBUF_V_BLEND_IN2CSC_COEFF8_Y2R_C8_MASK 0X00007FFF + +/** + * * Register: XAVBUF_V_BLEND_LUMA_IN2CSC_OFFSET + * */ +#define XAVBUF_V_BLEND_LUMA_IN2CSC_OFFSET 0X0000A0A4 + +#define XAVBUF_V_BLEND_LUMA_IN2CSC_OFFSET_POST_OFFSET_SHIFT 16 +#define XAVBUF_V_BLEND_LUMA_IN2CSC_OFFSET_POST_OFFSET_WIDTH 13 +#define XAVBUF_V_BLEND_LUMA_IN2CSC_OFFSET_POST_OFFSET_MASK 0X1FFF0000 + +#define XAVBUF_V_BLEND_LUMA_IN2CSC_OFFSET_PRE_OFFSET_SHIFT 0 +#define XAVBUF_V_BLEND_LUMA_IN2CSC_OFFSET_PRE_OFFSET_WIDTH 13 +#define XAVBUF_V_BLEND_LUMA_IN2CSC_OFFSET_PRE_OFFSET_MASK 0X00001FFF + +/** + * * Register: XAVBUF_V_BLEND_CR_IN2CSC_OFFSET + * */ +#define XAVBUF_V_BLEND_CR_IN2CSC_OFFSET 0X0000A0A8 + +#define XAVBUF_V_BLEND_CR_IN2CSC_OFFSET_POST_OFFSET_SHIFT 16 +#define XAVBUF_V_BLEND_CR_IN2CSC_OFFSET_POST_OFFSET_WIDTH 13 +#define XAVBUF_V_BLEND_CR_IN2CSC_OFFSET_POST_OFFSET_MASK 0X1FFF0000 + +#define XAVBUF_V_BLEND_CR_IN2CSC_OFFSET_PRE_OFFSET_SHIFT 0 +#define XAVBUF_V_BLEND_CR_IN2CSC_OFFSET_PRE_OFFSET_WIDTH 13 +#define XAVBUF_V_BLEND_CR_IN2CSC_OFFSET_PRE_OFFSET_MASK 0X00001FFF + +/** + * * Register: XAVBUF_V_BLEND_CB_IN2CSC_OFFSET + * */ +#define XAVBUF_V_BLEND_CB_IN2CSC_OFFSET 0X0000A0AC + +#define XAVBUF_V_BLEND_CB_IN2CSC_OFFSET_POST_OFFSET_SHIFT 16 +#define XAVBUF_V_BLEND_CB_IN2CSC_OFFSET_POST_OFFSET_WIDTH 13 +#define XAVBUF_V_BLEND_CB_IN2CSC_OFFSET_POST_OFFSET_MASK 0X1FFF0000 + +#define XAVBUF_V_BLEND_CB_IN2CSC_OFFSET_PRE_OFFSET_SHIFT 0 +#define XAVBUF_V_BLEND_CB_IN2CSC_OFFSET_PRE_OFFSET_WIDTH 13 +#define XAVBUF_V_BLEND_CB_IN2CSC_OFFSET_PRE_OFFSET_MASK 0X00001FFF + +/** + * * Register: XAVBUF_V_BLEND_CHROMA_KEY_ENABLE + * */ +#define XAVBUF_V_BLEND_CHROMA_KEY_ENABLE 0X0000A1D0 + +#define XAVBUF_V_BLEND_CHROMA_KEY_ENABLE_M_SEL_SHIFT 1 +#define XAVBUF_V_BLEND_CHROMA_KEY_ENABLE_M_SEL_WIDTH 1 +#define XAVBUF_V_BLEND_CHROMA_KEY_ENABLE_M_SEL_MASK 0X00000002 + +#define XAVBUF_V_BLEND_CHROMA_KEY_ENABLE_EN_SHIFT 0 +#define XAVBUF_V_BLEND_CHROMA_KEY_ENABLE_EN_WIDTH 1 +#define XAVBUF_V_BLEND_CHROMA_KEY_ENABLE_EN_MASK 0X00000001 + +/** + * * Register: XAVBUF_V_BLEND_CHROMA_KEY_COMP1 + * */ +#define XAVBUF_V_BLEND_CHROMA_KEY_COMP1 0X0000A1D4 + +#define XAVBUF_V_BLEND_CHROMA_KEY_COMP1_MAX_SHIFT 16 +#define XAVBUF_V_BLEND_CHROMA_KEY_COMP1_MAX_WIDTH 12 +#define XAVBUF_V_BLEND_CHROMA_KEY_COMP1_MAX_MASK 0X0FFF0000 + +#define XAVBUF_V_BLEND_CHROMA_KEY_COMP1_MIN_SHIFT 0 +#define XAVBUF_V_BLEND_CHROMA_KEY_COMP1_MIN_WIDTH 12 +#define XAVBUF_V_BLEND_CHROMA_KEY_COMP1_MIN_MASK 0X00000FFF + +/** + * * Register: XAVBUF_V_BLEND_CHROMA_KEY_COMP2 + * */ +#define XAVBUF_V_BLEND_CHROMA_KEY_COMP2 0X0000A1D8 + +#define XAVBUF_V_BLEND_CHROMA_KEY_COMP2_MAX_SHIFT 16 +#define XAVBUF_V_BLEND_CHROMA_KEY_COMP2_MAX_WIDTH 12 +#define XAVBUF_V_BLEND_CHROMA_KEY_COMP2_MAX_MASK 0X0FFF0000 + +#define XAVBUF_V_BLEND_CHROMA_KEY_COMP2_MIN_SHIFT 0 +#define XAVBUF_V_BLEND_CHROMA_KEY_COMP2_MIN_WIDTH 12 +#define XAVBUF_V_BLEND_CHROMA_KEY_COMP2_MIN_MASK 0X00000FFF + +/** + * * Register: XAVBUF_V_BLEND_CHROMA_KEY_COMP3 + * */ +#define XAVBUF_V_BLEND_CHROMA_KEY_COMP3 0X0000A1DC + +#define XAVBUF_V_BLEND_CHROMA_KEY_COMP3_MAX_SHIFT 16 +#define XAVBUF_V_BLEND_CHROMA_KEY_COMP3_MAX_WIDTH 12 +#define XAVBUF_V_BLEND_CHROMA_KEY_COMP3_MAX_MASK 0X0FFF0000 + +#define XAVBUF_V_BLEND_CHROMA_KEY_COMP3_MIN_SHIFT 0 +#define XAVBUF_V_BLEND_CHROMA_KEY_COMP3_MIN_WIDTH 12 +#define XAVBUF_V_BLEND_CHROMA_KEY_COMP3_MIN_MASK 0X00000FFF + +/** + * * Register: XAVBUF_BUF_FORMAT + * */ +#define XAVBUF_BUF_FORMAT 0X0000B000 + +#define XAVBUF_BUF_FORMAT_NL_GRAPHX_FORMAT_SHIFT 8 +#define XAVBUF_BUF_FORMAT_NL_GRAPHX_FORMAT_WIDTH 4 +#define XAVBUF_BUF_FORMAT_NL_GRAPHX_FORMAT_MASK 0X00000F00 + +#define XAVBUF_BUF_FORMAT_NL_VID_FORMAT_SHIFT 0 +#define XAVBUF_BUF_FORMAT_NL_VID_FORMAT_WIDTH 5 +#define XAVBUF_BUF_FORMAT_NL_VID_FORMAT_MASK 0X0000001F + +/** + * * Register: XAVBUF_BUF_NON_LIVE_LATENCY + * */ +#define XAVBUF_BUF_NON_LIVE_LATENCY 0X0000B008 + +#define XAVBUF_BUF_NON_LIVE_LATENCY_NL_LATENCY_SHIFT 0 +#define XAVBUF_BUF_NON_LIVE_LATENCY_NL_LATENCY_WIDTH 10 +#define XAVBUF_BUF_NON_LIVE_LATENCY_NL_LATENCY_MASK 0X000003FF + +/** + * * Register: XAVBUF_CHBUF0 + * */ +#define XAVBUF_CHBUF0 0X0000B010 + +#define XAVBUF_CHBUF0_BURST_LEN_SHIFT 2 +#define XAVBUF_CHBUF0_BURST_LEN_WIDTH 5 +#define XAVBUF_CHBUF0_BURST_LEN_MASK 0X0000007C + +#define XAVBUF_CHBUF0_FLUSH_SHIFT 1 +#define XAVBUF_CHBUF0_FLUSH_WIDTH 1 +#define XAVBUF_CHBUF0_FLUSH_MASK 0X00000002 + +#define XAVBUF_CHBUF0_EN_SHIFT 0 +#define XAVBUF_CHBUF0_EN_WIDTH 1 +#define XAVBUF_CHBUF0_EN_MASK 0X00000001 + +/** + * * Register: XAVBUF_CHBUF1 + * */ +#define XAVBUF_CHBUF1 0X0000B014 + +#define XAVBUF_CHBUF1_BURST_LEN_SHIFT 2 +#define XAVBUF_CHBUF1_BURST_LEN_WIDTH 5 +#define XAVBUF_CHBUF1_BURST_LEN_MASK 0X0000007C + +#define XAVBUF_CHBUF1_FLUSH_SHIFT 1 +#define XAVBUF_CHBUF1_FLUSH_WIDTH 1 +#define XAVBUF_CHBUF1_FLUSH_MASK 0X00000002 + +#define XAVBUF_CHBUF1_EN_SHIFT 0 +#define XAVBUF_CHBUF1_EN_WIDTH 1 +#define XAVBUF_CHBUF1_EN_MASK 0X00000001 + +/** + * * Register: XAVBUF_CHBUF2 + * */ +#define XAVBUF_CHBUF2 0X0000B018 + +#define XAVBUF_CHBUF2_BURST_LEN_SHIFT 2 +#define XAVBUF_CHBUF2_BURST_LEN_WIDTH 5 +#define XAVBUF_CHBUF2_BURST_LEN_MASK 0X0000007C + +#define XAVBUF_CHBUF2_FLUSH_SHIFT 1 +#define XAVBUF_CHBUF2_FLUSH_WIDTH 1 +#define XAVBUF_CHBUF2_FLUSH_MASK 0X00000002 + +#define XAVBUF_CHBUF2_EN_SHIFT 0 +#define XAVBUF_CHBUF2_EN_WIDTH 1 +#define XAVBUF_CHBUF2_EN_MASK 0X00000001 + +/** + * * Register: XAVBUF_CHBUF3 + * */ +#define XAVBUF_CHBUF3 0X0000B01C + +#define XAVBUF_CHBUF3_BURST_LEN_SHIFT 2 +#define XAVBUF_CHBUF3_BURST_LEN_WIDTH 5 +#define XAVBUF_CHBUF3_BURST_LEN_MASK 0X0000007C + +#define XAVBUF_CHBUF3_FLUSH_SHIFT 1 +#define XAVBUF_CHBUF3_FLUSH_WIDTH 1 +#define XAVBUF_CHBUF3_FLUSH_MASK 0X00000002 + +#define XAVBUF_CHBUF3_EN_SHIFT 0 +#define XAVBUF_CHBUF3_EN_WIDTH 1 +#define XAVBUF_CHBUF3_EN_MASK 0X00000001 + +/** + * * Register: XAVBUF_CHBUF4 + * */ +#define XAVBUF_CHBUF4 0X0000B020 + +#define XAVBUF_CHBUF4_BURST_LEN_SHIFT 2 +#define XAVBUF_CHBUF4_BURST_LEN_WIDTH 5 +#define XAVBUF_CHBUF4_BURST_LEN_MASK 0X0000007C + +#define XAVBUF_CHBUF4_FLUSH_SHIFT 1 +#define XAVBUF_CHBUF4_FLUSH_WIDTH 1 +#define XAVBUF_CHBUF4_FLUSH_MASK 0X00000002 + +#define XAVBUF_CHBUF4_EN_SHIFT 0 +#define XAVBUF_CHBUF4_EN_WIDTH 1 +#define XAVBUF_CHBUF4_EN_MASK 0X00000001 + +/** + * * Register: XAVBUF_CHBUF5 + * */ +#define XAVBUF_CHBUF5 0X0000B024 + +#define XAVBUF_CHBUF5_BURST_LEN_SHIFT 2 +#define XAVBUF_CHBUF5_BURST_LEN_WIDTH 5 +#define XAVBUF_CHBUF5_BURST_LEN_MASK 0X0000007C + +#define XAVBUF_CHBUF5_FLUSH_SHIFT 1 +#define XAVBUF_CHBUF5_FLUSH_WIDTH 1 +#define XAVBUF_CHBUF5_FLUSH_MASK 0X00000002 + +#define XAVBUF_CHBUF5_EN_SHIFT 0 +#define XAVBUF_CHBUF5_EN_WIDTH 1 +#define XAVBUF_CHBUF5_EN_MASK 0X00000001 + +/** + * * Register: XAVBUF_BUF_STC_CONTROL + * */ +#define XAVBUF_BUF_STC_CONTROL 0X0000B02C + +#define XAVBUF_BUF_STC_CONTROL_EN_SHIFT 0 +#define XAVBUF_BUF_STC_CONTROL_EN_WIDTH 1 +#define XAVBUF_BUF_STC_CONTROL_EN_MASK 0X00000001 + +/** + * * Register: XAVBUF_BUF_STC_INIT_VALUE0 + * */ +#define XAVBUF_BUF_STC_INIT_VALUE0 0X0000B030 + +#define XAVBUF_BUF_STC_INIT_VALUE0_INIT_VALUE0_SHIFT 0 +#define XAVBUF_BUF_STC_INIT_VALUE0_INIT_VALUE0_WIDTH 32 +#define XAVBUF_BUF_STC_INIT_VALUE0_INIT_VALUE0_MASK 0XFFFFFFFF + +/** + * * Register: XAVBUF_BUF_STC_INIT_VALUE1 + * */ +#define XAVBUF_BUF_STC_INIT_VALUE1 0X0000B034 + +#define XAVBUF_BUF_STC_INIT_VALUE1_INIT_VALUE1_SHIFT 0 +#define XAVBUF_BUF_STC_INIT_VALUE1_INIT_VALUE1_WIDTH 10 +#define XAVBUF_BUF_STC_INIT_VALUE1_INIT_VALUE1_MASK 0X000003FF + +/** + * * Register: XAVBUF_BUF_STC_ADJ + * */ +#define XAVBUF_BUF_STC_ADJ 0X0000B038 + +#define XAVBUF_BUF_STC_ADJ_SIGN_SHIFT 31 +#define XAVBUF_BUF_STC_ADJ_SIGN_WIDTH 1 +#define XAVBUF_BUF_STC_ADJ_SIGN_MASK 0X80000000 + +#define XAVBUF_BUF_STC_ADJ_VALUE_SHIFT 0 +#define XAVBUF_BUF_STC_ADJ_VALUE_WIDTH 31 +#define XAVBUF_BUF_STC_ADJ_VALUE_MASK 0X7FFFFFFF + +/** + * * Register: XAVBUF_BUF_STC_VID_VSYNC_TS_REG0 + * */ +#define XAVBUF_BUF_STC_VID_VSYNC_TS_REG0 0X0000B03C + +#define XAVBUF_BUF_STC_VID_VSYNC_TS_REG0_VSYNC_TS0_SHIFT 0 +#define XAVBUF_BUF_STC_VID_VSYNC_TS_REG0_VSYNC_TS0_WIDTH 32 +#define XAVBUF_BUF_STC_VID_VSYNC_TS_REG0_VSYNC_TS0_MASK 0XFFFFFFFF + +/** + * * Register: XAVBUF_BUF_STC_VID_VSYNC_TS_REG1 + * */ +#define XAVBUF_BUF_STC_VID_VSYNC_TS_REG1 0X0000B040 + +#define XAVBUF_BUF_STC_VID_VSYNC_TS_REG1_VSYNC_TS1_SHIFT 0 +#define XAVBUF_BUF_STC_VID_VSYNC_TS_REG1_VSYNC_TS1_WIDTH 10 +#define XAVBUF_BUF_STC_VID_VSYNC_TS_REG1_VSYNC_TS1_MASK 0X000003FF + +/** + * * Register: XAVBUF_BUF_STC_EXT_VSYNC_TS_REG0 + * */ +#define XAVBUF_BUF_STC_EXT_VSYNC_TS_REG0 0X0000B044 + +#define XAVBUF_BUF_STC_EXT_VSYNC_TS_REG0_EXT_VSYNC_TS0_SHIFT 0 +#define XAVBUF_BUF_STC_EXT_VSYNC_TS_REG0_EXT_VSYNC_TS0_WIDTH 32 +#define XAVBUF_BUF_STC_EXT_VSYNC_TS_REG0_EXT_VSYNC_TS0_MASK 0XFFFFFFFF + +/** + * * Register: XAVBUF_BUF_STC_EXT_VSYNC_TS_REG1 + * */ +#define XAVBUF_BUF_STC_EXT_VSYNC_TS_REG1 0X0000B048 + +#define XAVBUF_BUF_STC_EXT_VSYNC_TS_REG1_EXT_VSYNC_TS1_SHIFT 0 +#define XAVBUF_BUF_STC_EXT_VSYNC_TS_REG1_EXT_VSYNC_TS1_WIDTH 10 +#define XAVBUF_BUF_STC_EXT_VSYNC_TS_REG1_EXT_VSYNC_TS1_MASK 0X000003FF + +/** + * * Register: XAVBUF_BUF_STC_CUSTOM_EVENT_TS_REG0 + * */ +#define XAVBUF_BUF_STC_CUSTOM_EVENT_TS_REG0 0X0000B04C + +#define XAVBUF_BUF_STC_CUSTOM_EVENT_TS_REG0_CUST_EVENT_TS0_SHIFT 0 +#define XAVBUF_BUF_STC_CUSTOM_EVENT_TS_REG0_CUST_EVENT_TS0_WIDTH 32 +#define XAVBUF_BUF_STC_CUSTOM_EVENT_TS_REG0_CUST_EVENT_TS0_MASK 0XFFFFFFFF + +/** + * * Register: XAVBUF_BUF_STC_CUSTOM_EVENT_TS_REG1 + * */ +#define XAVBUF_BUF_STC_CUSTOM_EVENT_TS_REG1 0X0000B050 + +#define XAVBUF_BUF_STC_CUSTOM_EVENT_TS_REG1_CUST_EVENT_TS1_SHIFT 0 +#define XAVBUF_BUF_STC_CUSTOM_EVENT_TS_REG1_CUST_EVENT_TS1_WIDTH 10 +#define XAVBUF_BUF_STC_CUSTOM_EVENT_TS_REG1_CUST_EVENT_TS1_MASK 0X000003FF + +/** + * * Register: XAVBUF_BUF_STC_CUSTOM_EVENT2_TS_REG0 + * */ +#define XAVBUF_BUF_STC_CUSTOM_EVENT2_TS_REG0 0X0000B054 + +#define XAVBUF_BUF_STC_CUSTOM_EVENT2_TS_REG0_CUST_EVENT2_TS0_SHIFT 0 +#define XAVBUF_BUF_STC_CUSTOM_EVENT2_TS_REG0_CUST_EVENT2_TS0_WIDTH 32 +#define XAVBUF_BUF_STC_CUSTOM_EVENT2_TS_REG0_CUST_EVENT2_TS0_MASK 0XFFFFFFFF + +/** + * * Register: XAVBUF_BUF_STC_CUSTOM_EVENT2_TS_REG1 + * */ +#define XAVBUF_BUF_STC_CUSTOM_EVENT2_TS_REG1 0X0000B058 + +#define XAVBUF_BUF_STC_CUSTOM_EVENT2_TS_REG1_CUST_EVENT2_TS1_SHIFT 0 +#define XAVBUF_BUF_STC_CUSTOM_EVENT2_TS_REG1_CUST_EVENT2_TS1_WIDTH 10 +#define XAVBUF_BUF_STC_CUSTOM_EVENT2_TS_REG1_CUST_EVENT2_TS1_MASK 0X000003FF + +/** + * * Register: XAVBUF_BUF_STC_SNAPSHOT0 + * */ +#define XAVBUF_BUF_STC_SNAPSHOT0 0X0000B060 + +#define XAVBUF_BUF_STC_SNAPSHOT0_STC0_SHIFT 0 +#define XAVBUF_BUF_STC_SNAPSHOT0_STC0_WIDTH 32 +#define XAVBUF_BUF_STC_SNAPSHOT0_STC0_MASK 0XFFFFFFFF + +/** + * * Register: XAVBUF_BUF_STC_SNAPSHOT1 + * */ +#define XAVBUF_BUF_STC_SNAPSHOT1 0X0000B064 + +#define XAVBUF_BUF_STC_SNAPSHOT1_STC1_SHIFT 0 +#define XAVBUF_BUF_STC_SNAPSHOT1_STC1_WIDTH 10 +#define XAVBUF_BUF_STC_SNAPSHOT1_STC1_MASK 0X000003FF + +/** + * * Register: XAVBUF_BUF_OUTPUT_AUD_VID_SELECT + * */ +#define XAVBUF_BUF_OUTPUT_AUD_VID_SELECT 0X0000B070 + +#define XAVBUF_BUF_OUTPUT_AUD_VID_SELECT_AUD_STREAM2_SEL_SHIFT 6 +#define XAVBUF_BUF_OUTPUT_AUD_VID_SELECT_AUD_STREAM2_SEL_WIDTH 1 +#define XAVBUF_BUF_OUTPUT_AUD_VID_SELECT_AUD_STREAM2_SEL_MASK 0X00000040 + +#define XAVBUF_BUF_OUTPUT_AUD_VID_SELECT_AUD_STREAM1_SEL_SHIFT 4 +#define XAVBUF_BUF_OUTPUT_AUD_VID_SELECT_AUD_STREAM1_SEL_WIDTH 2 +#define XAVBUF_BUF_OUTPUT_AUD_VID_SELECT_AUD_STREAM1_SEL_MASK 0X00000030 + +#define XAVBUF_BUF_OUTPUT_AUD_VID_SELECT_VID_STREAM2_SEL_SHIFT 2 +#define XAVBUF_BUF_OUTPUT_AUD_VID_SELECT_VID_STREAM2_SEL_WIDTH 2 +#define XAVBUF_BUF_OUTPUT_AUD_VID_SELECT_VID_STREAM2_SEL_MASK 0X0000000C + +#define XAVBUF_BUF_OUTPUT_AUD_VID_SELECT_VID_STREAM1_SEL_SHIFT 0 +#define XAVBUF_BUF_OUTPUT_AUD_VID_SELECT_VID_STREAM1_SEL_WIDTH 2 +#define XAVBUF_BUF_OUTPUT_AUD_VID_SELECT_VID_STREAM1_SEL_MASK 0X00000003 + +/** + * * Register: XAVBUF_BUF_HCOUNT_VCOUNT_INT0 + * */ +#define XAVBUF_BUF_HCOUNT_VCOUNT_INT0 0X0000B074 + +#define XAVBUF_BUF_HCOUNT_VCOUNT_INT0_HCOUNT_SHIFT 16 +#define XAVBUF_BUF_HCOUNT_VCOUNT_INT0_HCOUNT_WIDTH 14 +#define XAVBUF_BUF_HCOUNT_VCOUNT_INT0_HCOUNT_MASK 0X3FFF0000 + +#define XAVBUF_BUF_HCOUNT_VCOUNT_INT0_VCOUNT_SHIFT 0 +#define XAVBUF_BUF_HCOUNT_VCOUNT_INT0_VCOUNT_WIDTH 14 +#define XAVBUF_BUF_HCOUNT_VCOUNT_INT0_VCOUNT_MASK 0X00003FFF + +/** + * * Register: XAVBUF_BUF_HCOUNT_VCOUNT_INT1 + * */ +#define XAVBUF_BUF_HCOUNT_VCOUNT_INT1 0X0000B078 + +#define XAVBUF_BUF_HCOUNT_VCOUNT_INT1_HCOUNT_SHIFT 16 +#define XAVBUF_BUF_HCOUNT_VCOUNT_INT1_HCOUNT_WIDTH 14 +#define XAVBUF_BUF_HCOUNT_VCOUNT_INT1_HCOUNT_MASK 0X3FFF0000 + +#define XAVBUF_BUF_HCOUNT_VCOUNT_INT1_VCOUNT_SHIFT 0 +#define XAVBUF_BUF_HCOUNT_VCOUNT_INT1_VCOUNT_WIDTH 14 +#define XAVBUF_BUF_HCOUNT_VCOUNT_INT1_VCOUNT_MASK 0X00003FFF + +/** + * * Register: XAVBUF_BUF_DITHER_CFG + * */ +#define XAVBUF_BUF_DITHER_CFG 0X0000B07C + +#define XAVBUF_BUF_DITHER_CFG_TAP_MSB_SHIFT 10 +#define XAVBUF_BUF_DITHER_CFG_TAP_MSB_WIDTH 1 +#define XAVBUF_BUF_DITHER_CFG_TAP_MSB_MASK 0X00000400 + +#define XAVBUF_BUF_DITHER_CFG_DW_SEL_SHIFT 9 +#define XAVBUF_BUF_DITHER_CFG_DW_SEL_WIDTH 1 +#define XAVBUF_BUF_DITHER_CFG_DW_SEL_MASK 0X00000200 + +#define XAVBUF_BUF_DITHER_CFG_LD_SHIFT 8 +#define XAVBUF_BUF_DITHER_CFG_LD_WIDTH 1 +#define XAVBUF_BUF_DITHER_CFG_LD_MASK 0X00000100 + +#define XAVBUF_BUF_DITHER_CFG_TRUNC_PT_SHIFT 5 +#define XAVBUF_BUF_DITHER_CFG_TRUNC_PT_WIDTH 3 +#define XAVBUF_BUF_DITHER_CFG_TRUNC_PT_MASK 0X000000E0 + +#define XAVBUF_BUF_DITHER_CFG_MODE_SHIFT 3 +#define XAVBUF_BUF_DITHER_CFG_MODE_WIDTH 2 +#define XAVBUF_BUF_DITHER_CFG_MODE_MASK 0X00000018 + +#define XAVBUF_BUF_DITHER_CFG_SIZE_SHIFT 0 +#define XAVBUF_BUF_DITHER_CFG_SIZE_WIDTH 3 +#define XAVBUF_BUF_DITHER_CFG_SIZE_MASK 0X00000007 + +/** + * * Register: XAVBUF_DITHER_CFG_SEED0 + * */ +#define XAVBUF_DITHER_CFG_SEED0 0X0000B080 + +#define XAVBUF_DITHER_CFG_SEED0_COLR0_SHIFT 0 +#define XAVBUF_DITHER_CFG_SEED0_COLR0_WIDTH 16 +#define XAVBUF_DITHER_CFG_SEED0_COLR0_MASK 0X0000FFFF + +/** + * * Register: XAVBUF_DITHER_CFG_SEED1 + * */ +#define XAVBUF_DITHER_CFG_SEED1 0X0000B084 + +#define XAVBUF_DITHER_CFG_SEED1_COLR1_SHIFT 0 +#define XAVBUF_DITHER_CFG_SEED1_COLR1_WIDTH 16 +#define XAVBUF_DITHER_CFG_SEED1_COLR1_MASK 0X0000FFFF + +/** + * * Register: XAVBUF_DITHER_CFG_SEED2 + * */ +#define XAVBUF_DITHER_CFG_SEED2 0X0000B088 + +#define XAVBUF_DITHER_CFG_SEED2_COLR2_SHIFT 0 +#define XAVBUF_DITHER_CFG_SEED2_COLR2_WIDTH 16 +#define XAVBUF_DITHER_CFG_SEED2_COLR2_MASK 0X0000FFFF + +/** + * * Register: XAVBUF_DITHER_CFG_MAX + * */ +#define XAVBUF_DITHER_CFG_MAX 0X0000B08C + +#define XAVBUF_DITHER_CFG_MAX_COLR_MAX_SHIFT 0 +#define XAVBUF_DITHER_CFG_MAX_COLR_MAX_WIDTH 12 +#define XAVBUF_DITHER_CFG_MAX_COLR_MAX_MASK 0X00000FFF + +/** + * * Register: XAVBUF_DITHER_CFG_MIN + * */ +#define XAVBUF_DITHER_CFG_MIN 0X0000B090 + +#define XAVBUF_DITHER_CFG_MIN_COLR_MIN_SHIFT 0 +#define XAVBUF_DITHER_CFG_MIN_COLR_MIN_WIDTH 12 +#define XAVBUF_DITHER_CFG_MIN_COLR_MIN_MASK 0X00000FFF + +/** + * * Register: XAVBUF_PATTERN_GEN_SELECT + * */ +#define XAVBUF_PATTERN_GEN_SELECT 0X0000B100 + +#define XAVBUF_PATTERN_GEN_SELECT_OFFSET_EQ_SHIFT 8 +#define XAVBUF_PATTERN_GEN_SELECT_OFFSET_EQ_WIDTH 24 +#define XAVBUF_PATTERN_GEN_SELECT_OFFSET_EQ_MASK 0XFFFFFF00 + +#define XAVBUF_PATTERN_GEN_SELECT_AUD_RATE_SEL_SHIFT 0 +#define XAVBUF_PATTERN_GEN_SELECT_AUD_RATE_SEL_WIDTH 2 +#define XAVBUF_PATTERN_GEN_SELECT_AUD_RATE_SEL_MASK 0X00000003 + +/** + * * Register: XAVBUF_AUD_PATTERN_SELECT1 + * */ +#define XAVBUF_AUD_PATTERN_SELECT1 0X0000B104 + +#define XAVBUF_AUD_PATTERN_SELECT1_PATTERN_SHIFT 0 +#define XAVBUF_AUD_PATTERN_SELECT1_PATTERN_WIDTH 2 +#define XAVBUF_AUD_PATTERN_SELECT1_PATTERN_MASK 0X00000003 + +/** + * * Register: XAVBUF_AUD_PATTERN_SELECT2 + * */ +#define XAVBUF_AUD_PATTERN_SELECT2 0X0000B108 + +#define XAVBUF_AUD_PATTERN_SELECT2_PATTERN_SHIFT 0 +#define XAVBUF_AUD_PATTERN_SELECT2_PATTERN_WIDTH 2 +#define XAVBUF_AUD_PATTERN_SELECT2_PATTERN_MASK 0X00000003 + +/** + * * Register: XAVBUF_BUF_AUD_VID_CLK_SOURCE + * */ +#define XAVBUF_BUF_AUD_VID_CLK_SOURCE 0X0000B120 + +#define XAVBUF_BUF_AUD_VID_CLK_SOURCE_VID_TIMING_SRC_SHIFT 2 +#define XAVBUF_BUF_AUD_VID_CLK_SOURCE_VID_TIMING_SRC_WIDTH 1 +#define XAVBUF_BUF_AUD_VID_CLK_SOURCE_VID_TIMING_SRC_MASK 0X00000004 + +#define XAVBUF_BUF_AUD_VID_CLK_SOURCE_AUD_CLK_SRC_SHIFT 1 +#define XAVBUF_BUF_AUD_VID_CLK_SOURCE_AUD_CLK_SRC_WIDTH 1 +#define XAVBUF_BUF_AUD_VID_CLK_SOURCE_AUD_CLK_SRC_MASK 0X00000002 + +#define XAVBUF_BUF_AUD_VID_CLK_SOURCE_VID_CLK_SRC_SHIFT 0 +#define XAVBUF_BUF_AUD_VID_CLK_SOURCE_VID_CLK_SRC_WIDTH 1 +#define XAVBUF_BUF_AUD_VID_CLK_SOURCE_VID_CLK_SRC_MASK 0X00000001 + +/** + * * Register: XAVBUF_BUF_SRST_REG + * */ +#define XAVBUF_BUF_SRST_REG 0X0000B124 + +#define XAVBUF_BUF_SRST_REG_VID_RST_SHIFT 1 +#define XAVBUF_BUF_SRST_REG_VID_RST_WIDTH 1 +#define XAVBUF_BUF_SRST_REG_VID_RST_MASK 0X00000002 + +/** + * * Register: XAVBUF_BUF_AUD_RDY_INTERVAL + * */ +#define XAVBUF_BUF_AUD_RDY_INTERVAL 0X0000B128 + +#define XAVBUF_BUF_AUD_RDY_INTERVAL_CH1_INT_SHIFT 16 +#define XAVBUF_BUF_AUD_RDY_INTERVAL_CH1_INT_WIDTH 16 +#define XAVBUF_BUF_AUD_RDY_INTERVAL_CH1_INT_MASK 0XFFFF0000 + +#define XAVBUF_BUF_AUD_RDY_INTERVAL_CH0_INT_SHIFT 0 +#define XAVBUF_BUF_AUD_RDY_INTERVAL_CH0_INT_WIDTH 16 +#define XAVBUF_BUF_AUD_RDY_INTERVAL_CH0_INT_MASK 0X0000FFFF + +/** + * * Register: XAVBUF_BUF_AUD_CH_CFG + * */ +#define XAVBUF_BUF_AUD_CH_CFG 0X0000B12C + +#define XAVBUF_BUF_AUD_CH_CFG_AUD_CH_ID_SHIFT 0 +#define XAVBUF_BUF_AUD_CH_CFG_AUD_CH_ID_WIDTH 2 +#define XAVBUF_BUF_AUD_CH_CFG_AUD_CH_ID_MASK 0X00000003 + +/** + * * Register: XAVBUF_BUF_GRAPHICS_COMP0_SCALE_FACTOR + * */ +#define XAVBUF_BUF_GRAPHICS_COMP0_SCALE_FACTOR 0X0000B200 + +#define XAVBUF_BUF_GRAPHICS_COMP0_SCALE_FACTOR_GRAPHICS_SCALE_FACTOR0_SHIFT 0 +#define XAVBUF_BUF_GRAPHICS_COMP0_SCALE_FACTOR_GRAPHICS_SCALE_FACTOR0_WIDTH 17 +#define XAVBUF_BUF_GRAPHICS_COMP0_SCALE_FACTOR_GRAPHICS_SCALE_FACTOR0_MASK 0X0001FFFF + +/** + * * Register: XAVBUF_BUF_GRAPHICS_COMP1_SCALE_FACTOR + * */ +#define XAVBUF_BUF_GRAPHICS_COMP1_SCALE_FACTOR 0X0000B204 + +#define XAVBUF_BUF_GRAPHICS_COMP1_SCALE_FACTOR_GRAPHICS_SCALE_FACTOR1_SHIFT 0 +#define XAVBUF_BUF_GRAPHICS_COMP1_SCALE_FACTOR_GRAPHICS_SCALE_FACTOR1_WIDTH 17 +#define XAVBUF_BUF_GRAPHICS_COMP1_SCALE_FACTOR_GRAPHICS_SCALE_FACTOR1_MASK 0X0001FFFF + +/** + * * Register: XAVBUF_BUF_GRAPHICS_COMP2_SCALE_FACTOR + * */ +#define XAVBUF_BUF_GRAPHICS_COMP2_SCALE_FACTOR 0X0000B208 + +#define XAVBUF_BUF_GRAPHICS_COMP2_SCALE_FACTOR_GRAPHICS_SCALE_FACTOR2_SHIFT 0 +#define XAVBUF_BUF_GRAPHICS_COMP2_SCALE_FACTOR_GRAPHICS_SCALE_FACTOR2_WIDTH 17 +#define XAVBUF_BUF_GRAPHICS_COMP2_SCALE_FACTOR_GRAPHICS_SCALE_FACTOR2_MASK 0X0001FFFF + +/** + * * Register: XAVBUF_BUF_VID_COMP0_SCALE_FACTOR + * */ +#define XAVBUF_BUF_VID_COMP0_SCALE_FACTOR 0X0000B20C + +#define XAVBUF_BUF_VID_COMP0_SCALE_FACTOR_VID_SCA_FACT0_SHIFT 0 +#define XAVBUF_BUF_VID_COMP0_SCALE_FACTOR_VID_SCA_FACT0_WIDTH 17 +#define XAVBUF_BUF_VID_COMP0_SCALE_FACTOR_VID_SCA_FACT0_MASK 0X0001FFFF + +/** + * * Register: XAVBUF_BUF_VID_COMP1_SCALE_FACTOR + * */ +#define XAVBUF_BUF_VID_COMP1_SCALE_FACTOR 0X0000B210 + +#define XAVBUF_BUF_VID_COMP1_SCALE_FACTOR_VID_SCA_FACT1_SHIFT 0 +#define XAVBUF_BUF_VID_COMP1_SCALE_FACTOR_VID_SCA_FACT1_WIDTH 17 +#define XAVBUF_BUF_VID_COMP1_SCALE_FACTOR_VID_SCA_FACT1_MASK 0X0001FFFF + +/** + * * Register: XAVBUF_BUF_VID_COMP2_SCALE_FACTOR + * */ +#define XAVBUF_BUF_VID_COMP2_SCALE_FACTOR 0X0000B214 + +#define XAVBUF_BUF_VID_COMP2_SCALE_FACTOR_VID_SCA_FACT2_SHIFT 0 +#define XAVBUF_BUF_VID_COMP2_SCALE_FACTOR_VID_SCA_FACT2_WIDTH 17 +#define XAVBUF_BUF_VID_COMP2_SCALE_FACTOR_VID_SCA_FACT2_MASK 0X0001FFFF + +/** + * * Register: XAVBUF_BUF_LIVE_VID_COMP0_SF + * */ +#define XAVBUF_BUF_LIVE_VID_COMP0_SF 0X0000B218 + +#define XAVBUF_BUF_LIVE_VID_COMP0_SF_LIV_VID_SCA_FACT0_SHIFT 0 +#define XAVBUF_BUF_LIVE_VID_COMP0_SF_LIV_VID_SCA_FACT0_WIDTH 17 +#define XAVBUF_BUF_LIVE_VID_COMP0_SF_LIV_VID_SCA_FACT0_MASK 0X0001FFFF + +/** + * * Register: XAVBUF_BUF_LIVE_VID_COMP1_SF + * */ +#define XAVBUF_BUF_LIVE_VID_COMP1_SF 0X0000B21C + +#define XAVBUF_BUF_LIVE_VID_COMP1_SF_LIV_VID_SCA_FACT1_SHIFT 0 +#define XAVBUF_BUF_LIVE_VID_COMP1_SF_LIV_VID_SCA_FACT1_WIDTH 17 +#define XAVBUF_BUF_LIVE_VID_COMP1_SF_LIV_VID_SCA_FACT1_MASK 0X0001FFFF + +/** + * * Register: XAVBUF_BUF_LIVE_VID_COMP2_SF + * */ +#define XAVBUF_BUF_LIVE_VID_COMP2_SF 0X0000B220 + +#define XAVBUF_BUF_LIVE_VID_COMP2_SF_LIV_VID_SCA_FACT2_SHIFT 0 +#define XAVBUF_BUF_LIVE_VID_COMP2_SF_LIV_VID_SCA_FACT2_WIDTH 17 +#define XAVBUF_BUF_LIVE_VID_COMP2_SF_LIV_VID_SCA_FACT2_MASK 0X0001FFFF + +/** + * * Register: XAVBUF_BUF_LIVE_VID_CFG + * */ +#define XAVBUF_BUF_LIVE_VID_CFG 0X0000B224 + +#define XAVBUF_BUF_LIVE_VID_CFG_CB_FIRST_SHIFT 8 +#define XAVBUF_BUF_LIVE_VID_CFG_CB_FIRST_WIDTH 1 +#define XAVBUF_BUF_LIVE_VID_CFG_CB_FIRST_MASK 0X00000100 + +#define XAVBUF_BUF_LIVE_VID_CFG_FORMAT_SHIFT 4 +#define XAVBUF_BUF_LIVE_VID_CFG_FORMAT_WIDTH 2 +#define XAVBUF_BUF_LIVE_VID_CFG_FORMAT_MASK 0X00000030 + +#define XAVBUF_BUF_LIVE_VID_CFG_BPC_SHIFT 0 +#define XAVBUF_BUF_LIVE_VID_CFG_BPC_WIDTH 3 +#define XAVBUF_BUF_LIVE_VID_CFG_BPC_MASK 0X00000007 + +/** + * * Register: XAVBUF_BUF_LIVE_GFX_COMP0_SF + * */ +#define XAVBUF_BUF_LIVE_GFX_COMP0_SF 0X0000B228 + +#define XAVBUF_BUF_LIVE_GFX_COMP0_SF_LIV_VID_SCA_FACT0_SHIFT 0 +#define XAVBUF_BUF_LIVE_GFX_COMP0_SF_LIV_VID_SCA_FACT0_WIDTH 17 +#define XAVBUF_BUF_LIVE_GFX_COMP0_SF_LIV_VID_SCA_FACT0_MASK 0X0001FFFF + +/** + * * Register: XAVBUF_BUF_LIVE_GFX_COMP1_SF + * */ +#define XAVBUF_BUF_LIVE_GFX_COMP1_SF 0X0000B22C + +#define XAVBUF_BUF_LIVE_GFX_COMP1_SF_LIV_VID_SCA_FACT1_SHIFT 0 +#define XAVBUF_BUF_LIVE_GFX_COMP1_SF_LIV_VID_SCA_FACT1_WIDTH 17 +#define XAVBUF_BUF_LIVE_GFX_COMP1_SF_LIV_VID_SCA_FACT1_MASK 0X0001FFFF + +/** + * * Register: XAVBUF_BUF_LIVE_GFX_COMP2_SF + * */ +#define XAVBUF_BUF_LIVE_GFX_COMP2_SF 0X0000B230 + +#define XAVBUF_BUF_LIVE_GFX_COMP2_SF_LIV_VID_SCA_FACT2_SHIFT 0 +#define XAVBUF_BUF_LIVE_GFX_COMP2_SF_LIV_VID_SCA_FACT2_WIDTH 17 +#define XAVBUF_BUF_LIVE_GFX_COMP2_SF_LIV_VID_SCA_FACT2_MASK 0X0001FFFF + +/** + * * Register: XAVBUF_BUF_LIVE_GFX_CFG + * */ +#define XAVBUF_BUF_LIVE_GFX_CFG 0X0000B234 + +#define XAVBUF_BUF_LIVE_GFX_CFG_CB_FIRST_SHIFT 8 +#define XAVBUF_BUF_LIVE_GFX_CFG_CB_FIRST_WIDTH 1 +#define XAVBUF_BUF_LIVE_GFX_CFG_CB_FIRST_MASK 0X00000100 + +#define XAVBUF_BUF_LIVE_GFX_CFG_FORMAT_SHIFT 4 +#define XAVBUF_BUF_LIVE_GFX_CFG_FORMAT_WIDTH 2 +#define XAVBUF_BUF_LIVE_GFX_CFG_FORMAT_MASK 0X00000030 + +#define XAVBUF_BUF_LIVE_GFX_CFG_BPC_SHIFT 0 +#define XAVBUF_BUF_LIVE_GFX_CFG_BPC_WIDTH 3 +#define XAVBUF_BUF_LIVE_GFX_CFG_BPC_MASK 0X00000007 + +/** + * * Register: XAVBUF_AUD_MIXER_VOLUME_CONTROL + * */ +#define XAVBUF_AUD_MIXER_VOLUME_CONTROL 0X0000C000 + +#define XAVBUF_AUD_MIXER_VOLUME_CONTROL_VOL_CTRL_CH1_SHIFT 16 +#define XAVBUF_AUD_MIXER_VOLUME_CONTROL_VOL_CTRL_CH1_WIDTH 16 +#define XAVBUF_AUD_MIXER_VOLUME_CONTROL_VOL_CTRL_CH1_MASK 0XFFFF0000 + +#define XAVBUF_AUD_MIXER_VOLUME_CONTROL_VOL_CTRL_CH0_SHIFT 0 +#define XAVBUF_AUD_MIXER_VOLUME_CONTROL_VOL_CTRL_CH0_WIDTH 16 +#define XAVBUF_AUD_MIXER_VOLUME_CONTROL_VOL_CTRL_CH0_MASK 0X0000FFFF + +/** + * * Register: XAVBUF_AUD_MIXER_META_DATA + * */ +#define XAVBUF_AUD_MIXER_META_DATA 0X0000C004 + +#define XAVBUF_AUD_MIXER_META_DATA_AUD_META_DATA_SEL_SHIFT 0 +#define XAVBUF_AUD_MIXER_META_DATA_AUD_META_DATA_SEL_WIDTH 1 +#define XAVBUF_AUD_MIXER_META_DATA_AUD_META_DATA_SEL_MASK 0X00000001 + +/** + * * Register: XAVBUF_AUD_CH_STATUS_REG0 + * */ +#define XAVBUF_AUD_CH_STATUS_REG0 0X0000C008 + +#define XAVBUF_AUD_CH_STATUS_REG0_STATUS0_SHIFT 0 +#define XAVBUF_AUD_CH_STATUS_REG0_STATUS0_WIDTH 32 +#define XAVBUF_AUD_CH_STATUS_REG0_STATUS0_MASK 0XFFFFFFFF + +/** + * * Register: XAVBUF_AUD_CH_STATUS_REG1 + * */ +#define XAVBUF_AUD_CH_STATUS_REG1 0X0000C00C + +#define XAVBUF_AUD_CH_STATUS_REG1_STATUS1_SHIFT 0 +#define XAVBUF_AUD_CH_STATUS_REG1_STATUS1_WIDTH 32 +#define XAVBUF_AUD_CH_STATUS_REG1_STATUS1_MASK 0XFFFFFFFF + +/** + * * Register: XAVBUF_AUD_CH_STATUS_REG2 + * */ +#define XAVBUF_AUD_CH_STATUS_REG2 0X0000C010 + +#define XAVBUF_AUD_CH_STATUS_REG2_STATUS2_SHIFT 0 +#define XAVBUF_AUD_CH_STATUS_REG2_STATUS2_WIDTH 32 +#define XAVBUF_AUD_CH_STATUS_REG2_STATUS2_MASK 0XFFFFFFFF + +/** + * * Register: XAVBUF_AUD_CH_STATUS_REG3 + * */ +#define XAVBUF_AUD_CH_STATUS_REG3 0X0000C014 + +#define XAVBUF_AUD_CH_STATUS_REG3_STATUS3_SHIFT 0 +#define XAVBUF_AUD_CH_STATUS_REG3_STATUS3_WIDTH 32 +#define XAVBUF_AUD_CH_STATUS_REG3_STATUS3_MASK 0XFFFFFFFF + +/** + * * Register: XAVBUF_AUD_CH_STATUS_REG4 + * */ +#define XAVBUF_AUD_CH_STATUS_REG4 0X0000C018 + +#define XAVBUF_AUD_CH_STATUS_REG4_STATUS4_SHIFT 0 +#define XAVBUF_AUD_CH_STATUS_REG4_STATUS4_WIDTH 32 +#define XAVBUF_AUD_CH_STATUS_REG4_STATUS4_MASK 0XFFFFFFFF + +/** + * * Register: XAVBUF_AUD_CH_STATUS_REG5 + * */ +#define XAVBUF_AUD_CH_STATUS_REG5 0X0000C01C + +#define XAVBUF_AUD_CH_STATUS_REG5_STATUS5_SHIFT 0 +#define XAVBUF_AUD_CH_STATUS_REG5_STATUS5_WIDTH 32 +#define XAVBUF_AUD_CH_STATUS_REG5_STATUS5_MASK 0XFFFFFFFF + +/** + * * Register: XAVBUF_AUD_CH_A_DATA_REG0 + * */ +#define XAVBUF_AUD_CH_A_DATA_REG0 0X0000C020 + +#define XAVBUF_AUD_CH_A_DATA_REG0_USER_DATA0_SHIFT 0 +#define XAVBUF_AUD_CH_A_DATA_REG0_USER_DATA0_WIDTH 32 +#define XAVBUF_AUD_CH_A_DATA_REG0_USER_DATA0_MASK 0XFFFFFFFF + +/** + * * Register: XAVBUF_AUD_CH_A_DATA_REG1 + * */ +#define XAVBUF_AUD_CH_A_DATA_REG1 0X0000C024 + +#define XAVBUF_AUD_CH_A_DATA_REG1_USER_DATA1_SHIFT 0 +#define XAVBUF_AUD_CH_A_DATA_REG1_USER_DATA1_WIDTH 32 +#define XAVBUF_AUD_CH_A_DATA_REG1_USER_DATA1_MASK 0XFFFFFFFF + +/** + * * Register: XAVBUF_AUD_CH_A_DATA_REG2 + * */ +#define XAVBUF_AUD_CH_A_DATA_REG2 0X0000C028 + +#define XAVBUF_AUD_CH_A_DATA_REG2_USER_DATA2_SHIFT 0 +#define XAVBUF_AUD_CH_A_DATA_REG2_USER_DATA2_WIDTH 32 +#define XAVBUF_AUD_CH_A_DATA_REG2_USER_DATA2_MASK 0XFFFFFFFF + +/** + * * Register: XAVBUF_AUD_CH_A_DATA_REG3 + * */ +#define XAVBUF_AUD_CH_A_DATA_REG3 0X0000C02C + +#define XAVBUF_AUD_CH_A_DATA_REG3_USER_DATA3_SHIFT 0 +#define XAVBUF_AUD_CH_A_DATA_REG3_USER_DATA3_WIDTH 32 +#define XAVBUF_AUD_CH_A_DATA_REG3_USER_DATA3_MASK 0XFFFFFFFF + +/** + * * Register: XAVBUF_AUD_CH_A_DATA_REG4 + * */ +#define XAVBUF_AUD_CH_A_DATA_REG4 0X0000C030 + +#define XAVBUF_AUD_CH_A_DATA_REG4_USER_DATA4_SHIFT 0 +#define XAVBUF_AUD_CH_A_DATA_REG4_USER_DATA4_WIDTH 32 +#define XAVBUF_AUD_CH_A_DATA_REG4_USER_DATA4_MASK 0XFFFFFFFF + +/** + * * Register: XAVBUF_AUD_CH_A_DATA_REG5 + * */ +#define XAVBUF_AUD_CH_A_DATA_REG5 0X0000C034 + +#define XAVBUF_AUD_CH_A_DATA_REG5_USER_DATA5_SHIFT 0 +#define XAVBUF_AUD_CH_A_DATA_REG5_USER_DATA5_WIDTH 32 +#define XAVBUF_AUD_CH_A_DATA_REG5_USER_DATA5_MASK 0XFFFFFFFF + +/** + * * Register: XAVBUF_AUD_CH_B_DATA_REG0 + * */ +#define XAVBUF_AUD_CH_B_DATA_REG0 0X0000C038 + +#define XAVBUF_AUD_CH_B_DATA_REG0_USER_DATA0_SHIFT 0 +#define XAVBUF_AUD_CH_B_DATA_REG0_USER_DATA0_WIDTH 32 +#define XAVBUF_AUD_CH_B_DATA_REG0_USER_DATA0_MASK 0XFFFFFFFF + +/** + * * Register: XAVBUF_AUD_CH_B_DATA_REG1 + * */ +#define XAVBUF_AUD_CH_B_DATA_REG1 0X0000C03C + +#define XAVBUF_AUD_CH_B_DATA_REG1_USER_DATA1_SHIFT 0 +#define XAVBUF_AUD_CH_B_DATA_REG1_USER_DATA1_WIDTH 32 +#define XAVBUF_AUD_CH_B_DATA_REG1_USER_DATA1_MASK 0XFFFFFFFF + +/** + * * Register: XAVBUF_AUD_CH_B_DATA_REG2 + * */ +#define XAVBUF_AUD_CH_B_DATA_REG2 0X0000C040 + +#define XAVBUF_AUD_CH_B_DATA_REG2_USER_DATA2_SHIFT 0 +#define XAVBUF_AUD_CH_B_DATA_REG2_USER_DATA2_WIDTH 32 +#define XAVBUF_AUD_CH_B_DATA_REG2_USER_DATA2_MASK 0XFFFFFFFF + +/** + * * Register: XAVBUF_AUD_CH_B_DATA_REG3 + * */ +#define XAVBUF_AUD_CH_B_DATA_REG3 0X0000C044 + +#define XAVBUF_AUD_CH_B_DATA_REG3_USER_DATA3_SHIFT 0 +#define XAVBUF_AUD_CH_B_DATA_REG3_USER_DATA3_WIDTH 32 +#define XAVBUF_AUD_CH_B_DATA_REG3_USER_DATA3_MASK 0XFFFFFFFF + +/** + * * Register: XAVBUF_AUD_CH_B_DATA_REG4 + * */ +#define XAVBUF_AUD_CH_B_DATA_REG4 0X0000C048 + +#define XAVBUF_AUD_CH_B_DATA_REG4_USER_DATA4_SHIFT 0 +#define XAVBUF_AUD_CH_B_DATA_REG4_USER_DATA4_WIDTH 32 +#define XAVBUF_AUD_CH_B_DATA_REG4_USER_DATA4_MASK 0XFFFFFFFF + +/** + * * Register: XAVBUF_AUD_CH_B_DATA_REG5 + * */ +#define XAVBUF_AUD_CH_B_DATA_REG5 0X0000C04C + +#define XAVBUF_AUD_CH_B_DATA_REG5_USER_DATA5_SHIFT 0 +#define XAVBUF_AUD_CH_B_DATA_REG5_USER_DATA5_WIDTH 32 +#define XAVBUF_AUD_CH_B_DATA_REG5_USER_DATA5_MASK 0XFFFFFFFF + +/** + * * Register: XAVBUF_AUD_SOFT_RST + * */ +#define XAVBUF_AUD_SOFT_RST 0X0000CC00 + +#define XAVBUF_AUD_SOFT_RST_EXTRA_BS_CONTROL_SHIFT 2 +#define XAVBUF_AUD_SOFT_RST_EXTRA_BS_CONTROL_WIDTH 1 +#define XAVBUF_AUD_SOFT_RST_EXTRA_BS_CONTROL_MASK 0X00000004 + +#define XAVBUF_AUD_SOFT_RST_LINE_RST_DISABLE_SHIFT 1 +#define XAVBUF_AUD_SOFT_RST_LINE_RST_DISABLE_WIDTH 1 +#define XAVBUF_AUD_SOFT_RST_LINE_RST_DISABLE_MASK 0X00000002 + +#define XAVBUF_AUD_SOFT_RST_AUD_SRST_SHIFT 0 +#define XAVBUF_AUD_SOFT_RST_AUD_SRST_WIDTH 1 +#define XAVBUF_AUD_SOFT_RST_AUD_SRST_MASK 0X00000001 + +/** + * * Register: XAVBUF_PATGEN_CRC_R + * */ +#define XAVBUF_PATGEN_CRC_R 0X0000CC10 + +#define XAVBUF_PATGEN_CRC_R_CRC_R_SHIFT 0 +#define XAVBUF_PATGEN_CRC_R_CRC_R_WIDTH 16 +#define XAVBUF_PATGEN_CRC_R_CRC_R_MASK 0X0000FFFF + +/** + * * Register: XAVBUF_PATGEN_CRC_G + * */ +#define XAVBUF_PATGEN_CRC_G 0X0000CC14 + +#define XAVBUF_PATGEN_CRC_G_CRC_G_SHIFT 0 +#define XAVBUF_PATGEN_CRC_G_CRC_G_WIDTH 16 +#define XAVBUF_PATGEN_CRC_G_CRC_G_MASK 0X0000FFFF + +/** + * * Register: XAVBUF_PATGEN_CRC_B + * */ +#define XAVBUF_PATGEN_CRC_B 0X0000CC18 + +#define XAVBUF_PATGEN_CRC_B_CRC_B_SHIFT 0 +#define XAVBUF_PATGEN_CRC_B_CRC_B_WIDTH 16 +#define XAVBUF_PATGEN_CRC_B_CRC_B_MASK 0X0000FFFF + +#define XAVBUF_NUM_SUPPORTED 52 + +#define XAVBUF_BUF_4BIT_SF 0x11111 +#define XAVBUF_BUF_5BIT_SF 0x10842 +#define XAVBUF_BUF_6BIT_SF 0x10410 +#define XAVBUF_BUF_8BIT_SF 0x10101 +#define XAVBUF_BUF_10BIT_SF 0x10040 +#define XAVBUF_BUF_12BIT_SF 0x10000 + +#define XAVBUF_BUF_6BPC 0x000 +#define XAVBUF_BUF_8BPC 0x001 +#define XAVBUF_BUF_10BPC 0x010 +#define XAVBUF_BUF_12BPC 0x011 + +#define XAVBUF_CHBUF_V_BURST_LEN 0xF +#define XAVBUF_CHBUF_A_BURST_LEN 0x3 + +#define XAVBUF_PL_CLK 0x0 +#define XAVBUF_PS_CLK 0x1 + +#define XAVBUF_NUM_SUPPORTED_NLVID 25 +#define XAVBUF_NUM_SUPPORTED_NLGFX 14 +#define XAVBUF_NUM_SUPPORTED_LIVE 14 +#define XAVBUF_NUM_OUTPUT_FORMATS 14 + +/** + * Address mapping for PLL (CRF and CRL) + */ + +/* Base Address for CLOCK in FPD. */ +#define XAVBUF_CLK_FPD_BASEADDR 0XFD1A0000 + +/* Base Address for CLOCK in LPD. */ +#define XAVBUF_CLK_LPD_BASEADDR 0XFF5E0000 + +/** + * The following constants define values to manipulate + * the bits of the VPLL control register. + */ +#define XAVBUF_PLL_CTRL 0X00000020 + +#define XAVBUF_PLL_CTRL_POST_SRC_SHIFT 24 +#define XAVBUF_PLL_CTRL_POST_SRC_WIDTH 3 +#define XAVBUF_PLL_CTRL_POST_SRC_MASK 0X07000000 + +#define XAVBUF_PLL_CTRL_PRE_SRC_SHIFT 20 +#define XAVBUF_VPLL_CTRL_PRE_SRC_WIDTH 3 +#define XAVBUF_VPLL_CTRL_PRE_SRC_MASK 0X00700000 + +#define XAVBUF_PLL_CTRL_CLKOUTDIV_SHIFT 17 +#define XAVBUF_PLL_CTRL_CLKOUTDIV_WIDTH 1 +#define XAVBUF_PLL_CTRL_CLKOUTDIV_MASK 0X00020000 + +#define XAVBUF_PLL_CTRL_DIV2_SHIFT 16 +#define XAVBUF_PLL_CTRL_DIV2_WIDTH 1 +#define XAVBUF_PLL_CTRL_DIV2_MASK 0X00010000 + +#define XAVBUF_PLL_CTRL_FBDIV_SHIFT 8 +#define XAVBUF_PLL_CTRL_FBDIV_WIDTH 7 +#define XAVBUF_PLL_CTRL_FBDIV_MASK 0X00007F00 + +#define XAVBUF_PLL_CTRL_BYPASS_SHIFT 3 +#define XAVBUF_PLL_CTRL_BYPASS_WIDTH 1 +#define XAVBUF_PLL_CTRL_BYPASS_MASK 0X00000008 + +#define XAVBUF_PLL_CTRL_RESET_SHIFT 0 +#define XAVBUF_PLL_CTRL_RESET_WIDTH 1 +#define XAVBUF_PLL_CTRL_RESET_MASK 0X00000001 + +/** + * The following constants define values to manipulate + * the bits of the PLL config register. + */ +#define XAVBUF_PLL_CFG 0X00000024 + +#define XAVBUF_PLL_CFG_LOCK_DLY_SHIFT 25 +#define XAVBUF_PLL_CFG_LOCK_DLY_WIDTH 7 +#define XAVBUF_PLL_CFG_LOCK_DLY_MASK 0XFE000000 + +#define XAVBUF_PLL_CFG_LOCK_CNT_SHIFT 13 +#define XAVBUF_PLL_CFG_LOCK_CNT_WIDTH 10 +#define XAVBUF_PLL_CFG_LOCK_CNT_MASK 0X007FE000 + +#define XAVBUF_PLL_CFG_LFHF_SHIFT 10 +#define XAVBUF_PLL_CFG_LFHF_WIDTH 2 +#define XAVBUF_PLL_CFG_LFHF_MASK 0X00000C00 + +#define XAVBUF_PLL_CFG_CP_SHIFT 5 +#define XAVBUF_PLL_CFG_CP_WIDTH 4 +#define XAVBUF_PLL_CFG_CP_MASK 0X000001E0 + +#define XAVBUF_PLL_CFG_RES_SHIFT 0 +#define XAVBUF_PLL_CFG_RES_WIDTH 4 +#define XAVBUF_PLL_CFG_RES_MASK 0X0000000F + +/** + * The following constants define values to manipulate + * the bits of the VPLL fractional config register. + */ +#define XAVBUF_PLL_FRAC_CFG 0X00000028 + +#define XAVBUF_PLL_FRAC_CFG_ENABLED_SHIFT 31 +#define XAVBUF_PLL_FRAC_CFG_ENABLED_WIDTH 1 +#define XAVBUF_PLL_FRAC_CFG_ENABLED_MASK 0X80000000 + +#define XAVBUF_PLL_FRAC_CFG_SEED_SHIFT 22 +#define XAVBUF_PLL_FRAC_CFG_SEED_WIDTH 3 +#define XAVBUF_PLL_FRAC_CFG_SEED_MASK 0X01C00000 + +#define XAVBUF_PLL_FRAC_CFG_ALGRTHM_SHIFT 19 +#define XAVBUF_PLL_FRAC_CFG_ALGRTHM_WIDTH 1 +#define XAVBUF_PLL_FRAC_CFG_ALGRTHM_MASK 0X00080000 + +#define XAVBUF_PLL_FRAC_CFG_ORDER_SHIFT 18 +#define XAVBUF_PLL_FRAC_CFG_ORDER_WIDTH 1 +#define XAVBUF_PLL_FRAC_CFG_ORDER_MASK 0X00040000 + +#define XAVBUF_PLL_FRAC_CFG_DATA_SHIFT 0 +#define XAVBUF_PLL_FRAC_CFG_DATA_WIDTH 16 +#define XAVBUF_PLL_FRAC_CFG_DATA_MASK 0X0000FFFF + +/** + * The following constants define values to manipulate + * the bits of the PLL STATUS register. + */ +#define XAVBUF_PLL_STATUS 0X00000044 + +#define XAVBUF_PLL_STATUS_VPLL_STABLE_SHIFT 5 +#define XAVBUF_PLL_STATUS_VPLL_STABLE_WIDTH 1 +#define XAVBUF_PLL_STATUS_VPLL_STABLE_MASK 0X00000020 + +#define XAVBUF_PLL_STATUS_DPLL_STABLE_SHIFT 4 +#define XAVBUF_PLL_STATUS_DPLL_STABLE_WIDTH 1 +#define XAVBUF_PLL_STATUS_DPLL_STABLE_MASK 0X00000010 + +#define XAVBUF_PLL_STATUS_APLL_STABLE_SHIFT 3 +#define XAVBUF_PLL_STATUS_APLL_STABLE_WIDTH 1 +#define XAVBUF_PLL_STATUS_APLL_STABLE_MASK 0X00000008 + +#define XAVBUF_PLL_STATUS_VPLL_LOCK_SHIFT 2 +#define XAVBUF_PLL_STATUS_VPLL_LOCK_WIDTH 1 +#define XAVBUF_PLL_STATUS_VPLL_LOCK_MASK 0X00000004 + +#define XAVBUF_PLL_STATUS_DPLL_LOCK_SHIFT 1 +#define XAVBUF_PLL_STATUS_DPLL_LOCK_WIDTH 1 +#define XAVBUF_PLL_STATUS_DPLL_LOCK_MASK 0X00000002 + +#define XAVBUF_PLL_STATUS_APLL_LOCK_SHIFT 0 +#define XAVBUF_PLL_STATUS_APLL_LOCK_WIDTH 1 +#define XAVBUF_PLL_STATUS_APLL_LOCK_MASK 0X00000001 + +/** + * The following constants define values to manipulate + * the bits of the VIDEO reference control register. + */ +#define XAVBUF_VIDEO_REF_CTRL 0X00000070 + +#define XAVBUF_VIDEO_REF_CTRL_CLKACT_SHIFT 24 +#define XAVBUF_VIDEO_REF_CTRL_CLKACT_WIDTH 1 +#define XAVBUF_VIDEO_REF_CTRL_CLKACT_MASK 0X01000000 + +#define XAVBUF_VIDEO_REF_CTRL_DIVISOR1_SHIFT 16 +#define XAVBUF_VIDEO_REF_CTRL_DIVISOR1_WIDTH 6 +#define XAVBUF_VIDEO_REF_CTRL_DIVISOR1_MASK 0X003F0000 + +#define XAVBUF_VIDEO_REF_CTRL_DIVISOR0_SHIFT 8 +#define XAVBUF_VIDEO_REF_CTRL_DIVISOR0_WIDTH 6 +#define XAVBUF_VIDEO_REF_CTRL_DIVISOR0_MASK 0X00003F00 + +#define XAVBUF_VIDEO_REF_CTRL_SRCSEL_SHIFT 0 +#define XAVBUF_VIDEO_REF_CTRL_SRCSEL_WIDTH 3 +#define XAVBUF_VIDEO_REF_CTRL_SRCSEL_MASK 0X00000007 + +/** + * The following constants define values to manipulate + * the bits of the AUDIO reference control register. + */ +#define XAVBUF_AUDIO_REF_CTRL 0X00000074 + +#define XAVBUF_AUDIO_REF_CTRL_CLKACT_SHIFT 24 +#define XAVBUF_AUDIO_REF_CTRL_CLKACT_WIDTH 1 +#define XAVBUF_AUDIO_REF_CTRL_CLKACT_MASK 0X01000000 + +#define XAVBUF_AUDIO_REF_CTRL_DIVISOR1_SHIFT 16 +#define XAVBUF_AUDIO_REF_CTRL_DIVISOR1_WIDTH 6 +#define XAVBUF_AUDIO_REF_CTRL_DIVISOR1_MASK 0X003F0000 + +#define XAVBUF_AUDIO_REF_CTRL_DIVISOR0_SHIFT 8 +#define XAVBUF_AUDIO_REF_CTRL_DIVISOR0_WIDTH 6 +#define XAVBUF_AUDIO_REF_CTRL_DIVISOR0_MASK 0X00003F00 + +#define XAVBUF_AUDIO_REF_CTRL_SRCSEL_SHIFT 0 +#define XAVBUF_AUDIO_REF_CTRL_SRCSEL_WIDTH 3 +#define XAVBUF_AUDIO_REF_CTRL_SRCSEL_MASK 0X00000007 + +/** + * The following constants define values to manipulate + * the bits of the Domain Switch register. + * For eg. FPD to LPD. + */ +#define XAVBUF_DOMAIN_SWITCH_CTRL 0X00000044 + +#define XAVBUF_DOMAIN_SWITCH_DIVISOR0_SHIFT 8 +#define XAVBUF_DOMAIN_SWITCH_DIVISOR0_WIDTH 6 +#define XAVBUF_DOMAIN_SWITCH_DIVISOR0_MASK 0X00003F00 + +/** + * The following constants define values to Reference + * clock. + */ +#define XAVBUF_Pss_Ref_Clk 0 +#define XAVBUF_Video_Clk 4 +#define XAVBUF_Pss_alt_Ref_Clk 5 +#define XAVBUF_Aux_Ref_clk 6 +#define XAVBUF_Gt_Crx_Ref_Clk 7 + +/** + * The following constants define values to manipulate + * the bits of any register. + */ +#define XAVBUF_ENABLE_BIT 1 +#define XAVBUF_DISABLE_BIT 0 + +/** + * The following constants define values available + * PLL source to Audio and Video. + */ +#define XAVBUF_VPLL_SRC_SEL 0 +#define XAVBUF_DPLL_SRC_SEL 2 +#define XAVBUF_RPLL_TO_FPD_SRC_SEL 3 + +/******************* Macros (Inline Functions) Definitions ********************/ + +/** @name Register access macro definitions. + * @{ + */ +#define XAVBuf_In32 Xil_In32 +#define XAVBuf_Out32 Xil_Out32 +/* @} */ + +/******************************************************************************/ +/** + * This is a low-level function that reads from the specified register. + * + * @param BaseAddress is the base address of the device. + * @param RegOffset is the register offset to be read from. + * + * @return The 32-bit value of the specified register. + * + * @note C-style signature: + * u32 XAVBuf_ReadReg(u32 BaseAddress, u32 RegOffset) + * +*******************************************************************************/ +#define XAVBuf_ReadReg(BaseAddress, RegOffset) \ + XAVBuf_In32((BaseAddress) + (RegOffset)) + +/******************************************************************************/ +/** + * This is a low-level function that writes to the specified register. + * + * @param BaseAddress is the base address of the device. + * @param RegOffset is the register offset to write to. + * @param Data is the 32-bit data to write to the specified register. + * + * @return None. + * + * @note C-style signature: + * void XAVBuf_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data) + * +*******************************************************************************/ +#define XAVBuf_WriteReg(BaseAddress, RegOffset, Data) \ + XAVBuf_Out32((BaseAddress) + (RegOffset), (Data)) + + +#ifdef __cplusplus +} +#endif + + +#endif //XAVBUF_H_ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/avbuf_v2_1/src/xavbuf_videoformats.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/avbuf_v2_1/src/xavbuf_videoformats.c new file mode 100644 index 000000000..4651cd8d4 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/avbuf_v2_1/src/xavbuf_videoformats.c @@ -0,0 +1,227 @@ +/******************************************************************************* + * + * Copyright (C) 2017 Xilinx, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * Use of the Software is limited solely to applications: + * (a) running on a Xilinx device, or + * (b) that interact with a Xilinx device through a bus or interconnect. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of the Xilinx shall not be used + * in advertising or otherwise to promote the sale, use or other dealings in + * this Software without prior written authorization from Xilinx. + * +*******************************************************************************/ +/******************************************************************************/ +/** + * + * @file xavbuf_videoformats.c + * @addtogroup xavbuf_v2_1 + * @{ + * + * Contains attributes of the video formats mapped to the hardware + * + * @note None. + * + * 
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -----------------------------------------------
+ * 1.0   aad  03/10/17 Initial release.
+ * 2.0   aad  02/22/18 Fixed scaling factors and bits per pixel
+ *
+ * +*******************************************************************************/ + +/******************************* Include Files ********************************/ + +#include "xavbuf.h" + + +/**************************** Variable Definitions ****************************/ +#ifdef __cplusplus +extern "C" +#endif + +const XAVBuf_VideoAttribute XAVBuf_SupportedFormats[XAVBUF_NUM_SUPPORTED] = +{ + /* Non - Live Video Formats */ + { CbY0CrY1, 0, Interleaved, + {XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF}, + TRUE, FALSE, FALSE, 16}, + { CrY0CbY1, 1, Interleaved, + {XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF}, + TRUE, FALSE, FALSE, 16}, + { Y0CrY1Cb, 2, Interleaved, + {XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF}, + TRUE, FALSE, FALSE, 16}, + { Y0CbY1Cr, 3, Interleaved, + {XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF}, + TRUE, FALSE, FALSE, 16}, + { YV16, 4, Planar, + {XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF}, + TRUE, FALSE, FALSE, 16}, + { YV24, 5, Planar, + {XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF}, + FALSE, FALSE, FALSE, 24}, + { YV16Ci, 6, SemiPlanar, + {XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF}, + TRUE, FALSE, FALSE, 16}, + { MONOCHROME, 7, Interleaved, + {XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF}, + TRUE, FALSE, FALSE, 8}, + { YV16Ci2, 8, SemiPlanar, + {XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF}, + TRUE, FALSE, TRUE, 16}, + { YUV444, 9, Interleaved, + {XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF}, + FALSE, FALSE, FALSE, 24}, + { RGB888, 10, Interleaved, + {XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF}, + FALSE, TRUE, FALSE, 24}, + { RGBA8880, 11, Interleaved, + {XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF}, + FALSE, TRUE, FALSE, 32}, + { RGB888_10BPC, 12, Interleaved, + {XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF}, + FALSE, TRUE, FALSE, 30}, + { YUV444_10BPC, 13, Interleaved, + {XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF}, + FALSE, FALSE, FALSE, 30}, + { YV16Ci2_10BPC, 14, SemiPlanar, + {XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF}, + TRUE, FALSE, TRUE, 20}, + { YV16Ci_10BPC, 15, SemiPlanar, + {XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF}, + TRUE, FALSE, FALSE, 20}, + { YV16_10BPC, 16, Planar, + {XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF}, + TRUE, FALSE, FALSE, 20}, + { YV24_10BPC, 17, Planar, + {XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF}, + FALSE, FALSE, FALSE, 30}, + { MONOCHROME_10BPC, 18, Interleaved, + {XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF}, + TRUE, FALSE, FALSE, 10}, + { YV16_420, 19, Planar, + {XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF}, + TRUE, FALSE, FALSE, 16}, + { YV16Ci_420, 20, SemiPlanar, + {XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF}, + TRUE, FALSE, FALSE, 16}, + { YV16Ci2_420, 21, SemiPlanar, + {XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF}, + TRUE, FALSE, TRUE, 16}, + { YV16_420_10BPC, 22, Planar, + {XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF}, + TRUE, FALSE, FALSE, 20}, + { YV16Ci_420_10BPC, 23, SemiPlanar, + {XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF}, + TRUE, FALSE, FALSE, 20}, + { YV16Ci2_420_10BPC, 24, SemiPlanar, + {XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF}, + TRUE, FALSE, TRUE, 20}, + + /* Non-Live Graphics formats */ + { RGBA8888, 0, Interleaved, + {XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF}, + FALSE, TRUE, FALSE, 32}, + { ABGR8888, 1, Interleaved, + {XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF}, + FALSE, TRUE, FALSE, 32}, + { RGB888_GFX, 2, Interleaved, + {XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF}, + FALSE, TRUE, FALSE, 24}, + { BGR888, 3, Interleaved, + {XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF}, + FALSE, TRUE, FALSE, 24}, + { RGBA5551, 4, Interleaved, + {XAVBUF_BUF_5BIT_SF, XAVBUF_BUF_5BIT_SF, XAVBUF_BUF_5BIT_SF}, + FALSE, TRUE, FALSE, 16}, + { RGBA4444, 5, Interleaved, + {XAVBUF_BUF_4BIT_SF, XAVBUF_BUF_4BIT_SF, XAVBUF_BUF_4BIT_SF}, + FALSE, TRUE, FALSE, 16}, + { RGB565, 6, Interleaved, + {XAVBUF_BUF_5BIT_SF, XAVBUF_BUF_6BIT_SF, XAVBUF_BUF_5BIT_SF}, + FALSE, TRUE, FALSE, 16}, + { BPP8, 7, Interleaved, + {XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF}, + FALSE, TRUE, FALSE, 8}, + { BPP4, 8, Interleaved, + {XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF}, + FALSE, TRUE, FALSE, 4}, + { BPP2, 9, Interleaved, + {XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF}, + FALSE, TRUE, FALSE, 2}, + { BPP1, 10, Interleaved, + {XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF}, + FALSE, TRUE, FALSE, 1}, + { YUV422, 11, Interleaved, + {XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF}, + FALSE, FALSE, FALSE, 24}, + + /* Video Formats for Live Video/Graphics input and output sources */ + { RGB_6BPC, 0, Interleaved, + {XAVBUF_BUF_6BIT_SF, XAVBUF_BUF_6BIT_SF, XAVBUF_BUF_6BIT_SF}, + FALSE, TRUE, FALSE, 18}, + { RGB_8BPC, 0, Interleaved, + {XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF}, + FALSE, TRUE, FALSE, 24}, + { RGB_10BPC, 0, Interleaved, + {XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF}, + FALSE, TRUE, FALSE, 30}, + { RGB_12BPC, 0, Interleaved, + {XAVBUF_BUF_12BIT_SF, XAVBUF_BUF_12BIT_SF, XAVBUF_BUF_12BIT_SF}, + FALSE, TRUE, FALSE, 36}, + { YCbCr444_6BPC, 1, Interleaved, + {XAVBUF_BUF_6BIT_SF, XAVBUF_BUF_6BIT_SF, XAVBUF_BUF_6BIT_SF}, + FALSE, FALSE, FALSE, 18}, + { YCbCr444_8BPC, 1, Interleaved, + {XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF}, + FALSE, FALSE, FALSE, 24}, + { YCbCr444_10BPC, 1, Interleaved, + {XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF}, + FALSE, FALSE, FALSE, 30}, + { YCbCr444_12BPC, 1, Interleaved, + {XAVBUF_BUF_12BIT_SF, XAVBUF_BUF_12BIT_SF, XAVBUF_BUF_12BIT_SF}, + FALSE, FALSE, FALSE, 36}, + { YCbCr422_8BPC, 2, Interleaved, + {XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF}, + TRUE, FALSE, FALSE, 24}, + { YCbCr422_10BPC, 2, Interleaved, + {XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF}, + TRUE, FALSE, FALSE, 30}, + { YCbCr422_12BPC, 2, Interleaved, + {XAVBUF_BUF_12BIT_SF, XAVBUF_BUF_12BIT_SF, XAVBUF_BUF_12BIT_SF}, + TRUE, FALSE, FALSE, 36}, + { YOnly_8BPC, 3, Interleaved, + {XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF}, + TRUE, FALSE, FALSE, 24}, + { YOnly_10BPC, 3, Interleaved, + {XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF}, + TRUE, FALSE, FALSE, 30}, + { YOnly_12BPC, 3, Interleaved, + {XAVBUF_BUF_12BIT_SF, XAVBUF_BUF_12BIT_SF, XAVBUF_BUF_12BIT_SF}, + TRUE, FALSE, FALSE, 36}, + +}; + +/** @} */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/axipmon_v6_5/src/Makefile b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/axipmon_v6_5/src/Makefile deleted file mode 100644 index 926b20c4e..000000000 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/axipmon_v6_5/src/Makefile +++ /dev/null @@ -1,27 +0,0 @@ -COMPILER= -ARCHIVER= -CP=cp -COMPILER_FLAGS= -EXTRA_COMPILER_FLAGS= -LIB=libxil.a - -RELEASEDIR=../../../lib -INCLUDEDIR=../../../include -INCLUDES=-I./. -I${INCLUDEDIR} - -INCLUDEFILES=*.h -LIBSOURCES=*.c -OUTS = *.o - - -libs: - echo "Compiling axipmon" - $(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES) - $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS} - make clean - -include: - ${CP} ${INCLUDEFILES} ${INCLUDEDIR} - -clean: - rm -rf ${OUTS} diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/axipmon_v6_6/src/Makefile b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/axipmon_v6_6/src/Makefile new file mode 100644 index 000000000..8c401268f --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/axipmon_v6_6/src/Makefile @@ -0,0 +1,40 @@ +COMPILER= +ARCHIVER= +CP=cp +COMPILER_FLAGS= +EXTRA_COMPILER_FLAGS= +LIB=libxil.a + +CC_FLAGS = $(COMPILER_FLAGS) +ECC_FLAGS = $(EXTRA_COMPILER_FLAGS) + +RELEASEDIR=../../../lib +INCLUDEDIR=../../../include +INCLUDES=-I./. -I${INCLUDEDIR} + +OUTS = *.o + +LIBSOURCES:=*.c +INCLUDEFILES:=*.h + +OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c))) + +libs: banner xaxipmon_libs clean + +%.o: %.c + ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $< + +banner: + echo "Compiling axipmon" + +xaxipmon_libs: ${OBJECTS} + $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS} + +.PHONY: include +include: xaxipmon_includes + +xaxipmon_includes: + ${CP} ${INCLUDEFILES} ${INCLUDEDIR} + +clean: + rm -rf ${OBJECTS} diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_5/src/xaxipmon.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/axipmon_v6_6/src/xaxipmon.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_5/src/xaxipmon.c rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/axipmon_v6_6/src/xaxipmon.c index fbb867839..fc5d99fd2 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_5/src/xaxipmon.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/axipmon_v6_6/src/xaxipmon.c @@ -33,7 +33,7 @@ /** * * @file xaxipmon.c -* @addtogroup axipmon_v6_3 +* @addtogroup axipmon_v6_6 * @{ * * This file contains the driver API functions that can be used to access diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/axipmon_v6_5/src/xaxipmon.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/axipmon_v6_6/src/xaxipmon.h similarity index 98% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/axipmon_v6_5/src/xaxipmon.h rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/axipmon_v6_6/src/xaxipmon.h index f8d4d6467..ea347e07c 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/axipmon_v6_5/src/xaxipmon.h +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/axipmon_v6_6/src/xaxipmon.h @@ -33,7 +33,7 @@ /** * * @file xaxipmon.h -* @addtogroup axipmon_v6_3 +* @addtogroup axipmon_v6_6 * @{ * @details * @@ -253,6 +253,14 @@ * 6.3 kvn 07/02/15 Modified code according to MISRA-C:2012 guidelines. * 6.4 sk 11/10/15 Used UINTPTR instead of u32 for Baseaddress CR# 867425. * Changed the prototype of XAxiPmon_CfgInitialize API. +* 6.5 ms 01/23/17 Modified xil_printf statement in main function for all +* examples to ensure that "Successfully ran" and "Failed" +* strings are available in all examples. This is a fix +* for CR-965028. +* ms 03/17/17 Added readme.txt file in examples folder for doxygen +* generation. +* 6.6 ms 04/18/17 Modified tcl file to add suffix U for all macro +* definitions of axipmon in xparameters.h * * *****************************************************************************/ diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_5/src/xaxipmon_g.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/axipmon_v6_6/src/xaxipmon_g.c similarity index 94% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_5/src/xaxipmon_g.c rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/axipmon_v6_6/src/xaxipmon_g.c index 2bd473dd5..b54becbef 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_5/src/xaxipmon_g.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/axipmon_v6_6/src/xaxipmon_g.c @@ -5,7 +5,7 @@ * Version: * DO NOT EDIT. * -* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.* +* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.* *Permission is hereby granted, free of charge, to any person obtaining a copy *of this software and associated documentation files (the Software), to deal *in the Software without restriction, including without limitation the rights @@ -44,7 +44,7 @@ * The configuration table for devices */ -XAxiPmon_Config XAxiPmon_ConfigTable[] = +XAxiPmon_Config XAxiPmon_ConfigTable[XPAR_XAXIPMON_NUM_INSTANCES] = { { XPAR_PSU_APM_0_DEVICE_ID, diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/axipmon_v6_5/src/xaxipmon_hw.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/axipmon_v6_6/src/xaxipmon_hw.h similarity index 99% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/axipmon_v6_5/src/xaxipmon_hw.h rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/axipmon_v6_6/src/xaxipmon_hw.h index 68ed57aaf..b5d20f57f 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/axipmon_v6_5/src/xaxipmon_hw.h +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/axipmon_v6_6/src/xaxipmon_hw.h @@ -33,7 +33,7 @@ /** * * @file xaxipmon_hw.h -* @addtogroup axipmon_v6_3 +* @addtogroup axipmon_v6_6 * @{ * * This header file contains identifiers and basic driver functions (or diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/axipmon_v6_5/src/xaxipmon_selftest.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/axipmon_v6_6/src/xaxipmon_selftest.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/axipmon_v6_5/src/xaxipmon_selftest.c rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/axipmon_v6_6/src/xaxipmon_selftest.c index df2a9da66..7a6679140 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/axipmon_v6_5/src/xaxipmon_selftest.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/axipmon_v6_6/src/xaxipmon_selftest.c @@ -33,7 +33,7 @@ /** * * @file xaxipmon_selftest.c -* @addtogroup axipmon_v6_3 +* @addtogroup axipmon_v6_6 * @{ * * This file contains a diagnostic self test function for the XAxiPmon driver. diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/axipmon_v6_5/src/xaxipmon_sinit.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/axipmon_v6_6/src/xaxipmon_sinit.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/axipmon_v6_5/src/xaxipmon_sinit.c rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/axipmon_v6_6/src/xaxipmon_sinit.c index 737d80b48..2494aea8c 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/axipmon_v6_5/src/xaxipmon_sinit.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/axipmon_v6_6/src/xaxipmon_sinit.c @@ -33,7 +33,7 @@ /** * * @file xaxipmon_sinit.c -* @addtogroup axipmon_v6_3 +* @addtogroup axipmon_v6_6 * @{ * * This file contains the implementation of the XAxiPmon driver's static diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/canps_v3_2/src/xcanps.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/canps_v3_2/src/xcanps.c index 243b3a81b..f852de4e6 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/canps_v3_2/src/xcanps.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/canps_v3_2/src/xcanps.c @@ -33,7 +33,7 @@ /** * * @file xcanps.c -* @addtogroup canps_v3_0 +* @addtogroup canps_v3_2 * @{ * * Functions in this file are the minimum required functions for the XCanPs diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/canps_v3_2/src/xcanps.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/canps_v3_2/src/xcanps.h index b180e37ec..9feb45eea 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/canps_v3_2/src/xcanps.h +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/canps_v3_2/src/xcanps.h @@ -33,7 +33,7 @@ /** * * @file xcanps.h -* @addtogroup canps_v3_0 +* @addtogroup canps_v3_2 * @{ * @details * @@ -204,6 +204,8 @@ * Data mismatch while sending data less than 8 bytes. * 3.1 nsk 12/21/15 Updated XCanPs_IntrHandler in xcanps_intr.c to handle * error interrupts correctly. CR#925615 +* ms 03/17/17 Added readme.txt file in examples folder for doxygen +* generation. * * ******************************************************************************/ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/canps_v3_2/src/xcanps_g.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/canps_v3_2/src/xcanps_g.c index 4063a44eb..0ed8cd17c 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/canps_v3_2/src/xcanps_g.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/canps_v3_2/src/xcanps_g.c @@ -5,7 +5,7 @@ * Version: * DO NOT EDIT. * -* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.* +* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.* *Permission is hereby granted, free of charge, to any person obtaining a copy *of this software and associated documentation files (the Software), to deal *in the Software without restriction, including without limitation the rights @@ -44,7 +44,7 @@ * The configuration table for devices */ -XCanPs_Config XCanPs_ConfigTable[] = +XCanPs_Config XCanPs_ConfigTable[XPAR_XCANPS_NUM_INSTANCES] = { { XPAR_PSU_CAN_1_DEVICE_ID, diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/canps_v3_2/src/xcanps_hw.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/canps_v3_2/src/xcanps_hw.c index bbb96120a..7ca2f81eb 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/canps_v3_2/src/xcanps_hw.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/canps_v3_2/src/xcanps_hw.c @@ -33,7 +33,7 @@ /** * * @file xcanps_hw.c -* @addtogroup canps_v3_0 +* @addtogroup canps_v3_2 * @{ * * This file contains the implementation of the canps interface reset sequence diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/canps_v3_2/src/xcanps_hw.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/canps_v3_2/src/xcanps_hw.h index 9fe681aaf..30ec68ab9 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/canps_v3_2/src/xcanps_hw.h +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/canps_v3_2/src/xcanps_hw.h @@ -33,7 +33,7 @@ /** * * @file xcanps_hw.h -* @addtogroup canps_v3_0 +* @addtogroup canps_v3_2 * @{ * * This header file contains the identifiers and basic driver functions (or diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/canps_v3_2/src/xcanps_intr.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/canps_v3_2/src/xcanps_intr.c index f6721ca75..715b35eb2 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/canps_v3_2/src/xcanps_intr.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/canps_v3_2/src/xcanps_intr.c @@ -33,7 +33,7 @@ /** * * @file xcanps_intr.c -* @addtogroup canps_v3_0 +* @addtogroup canps_v3_2 * @{ * * This file contains functions related to CAN interrupt handling. diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/canps_v3_2/src/xcanps_selftest.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/canps_v3_2/src/xcanps_selftest.c index 48a6f4031..26c9fcb68 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/canps_v3_2/src/xcanps_selftest.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/canps_v3_2/src/xcanps_selftest.c @@ -33,7 +33,7 @@ /** * * @file xcanps_selftest.c -* @addtogroup canps_v3_0 +* @addtogroup canps_v3_2 * @{ * * This file contains a diagnostic self-test function for the XCanPs driver. diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/canps_v3_2/src/xcanps_sinit.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/canps_v3_2/src/xcanps_sinit.c index 230c429b3..5321669d7 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/canps_v3_2/src/xcanps_sinit.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/canps_v3_2/src/xcanps_sinit.c @@ -33,7 +33,7 @@ /** * * @file xcanps_sinit.c -* @addtogroup canps_v3_0 +* @addtogroup canps_v3_2 * @{ * * This file contains the implementation of the XCanPs driver's static diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/coresightps_dcc_v1_3/src/Makefile b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/coresightps_dcc_v1_4/src/Makefile similarity index 100% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/coresightps_dcc_v1_3/src/Makefile rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/coresightps_dcc_v1_4/src/Makefile diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/coresightps_dcc_v1_3/src/xcoresightpsdcc.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/coresightps_dcc_v1_4/src/xcoresightpsdcc.c similarity index 98% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/coresightps_dcc_v1_3/src/xcoresightpsdcc.c rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/coresightps_dcc_v1_4/src/xcoresightpsdcc.c index 4bad57094..fca26ca2e 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/coresightps_dcc_v1_3/src/xcoresightpsdcc.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/coresightps_dcc_v1_4/src/xcoresightpsdcc.c @@ -33,7 +33,7 @@ /** * * @file xcoresightpsdcc.c -* @addtogroup coresightps_dcc_v1_1 +* @addtogroup coresightps_dcc_v1_4 * @{ * * Functions in this file are the minimum required functions for the @@ -132,7 +132,7 @@ void XCoresightPs_DccSendByte(u32 BaseAddress, u8 Data) ******************************************************************************/ u8 XCoresightPs_DccRecvByte(u32 BaseAddress) { - u8 Data; + u8 Data = 0U; (void) BaseAddress; while (!(XCoresightPs_DccGetStatus() & XCORESIGHTPS_DCC_STATUS_RX)) @@ -169,7 +169,7 @@ u8 XCoresightPs_DccRecvByte(u32 BaseAddress) ******************************************************************************/ static INLINE u32 XCoresightPs_DccGetStatus(void) { - u32 Status; + u32 Status = 0U; #ifdef __aarch64__ asm volatile ("mrs %0, mdccsr_el0" : "=r" (Status)); diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/coresightps_dcc_v1_3/src/xcoresightpsdcc.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/coresightps_dcc_v1_4/src/xcoresightpsdcc.h similarity index 98% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/coresightps_dcc_v1_3/src/xcoresightpsdcc.h rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/coresightps_dcc_v1_4/src/xcoresightpsdcc.h index a732b235d..67959e327 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/coresightps_dcc_v1_3/src/xcoresightpsdcc.h +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/coresightps_dcc_v1_4/src/xcoresightpsdcc.h @@ -33,7 +33,7 @@ /** * * @file xcoresightpsdcc.h -* @addtogroup coresightps_dcc_v1_1 +* @addtogroup coresightps_dcc_v1_4 * @{ * @details * diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/cpu_cortexa53_v1_2/src/Makefile b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/cpu_cortexa53_v1_5/src/Makefile similarity index 78% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/cpu_cortexa53_v1_2/src/Makefile rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/cpu_cortexa53_v1_5/src/Makefile index 747a7a10d..4a326767b 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/cpu_cortexa53_v1_2/src/Makefile +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/cpu_cortexa53_v1_5/src/Makefile @@ -10,7 +10,7 @@ INCLUDEDIR=../../../include INCLUDES=-I${INCLUDEDIR} OUTS = *.o - +OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c))) LIBSOURCES=*.c INCLUDEFILES=*.h @@ -20,3 +20,6 @@ libs: .PHONY: include include: ${CP} $(INCLUDEFILES) $(INCLUDEDIR) + +clean: + rm -rf ${OBJECTS} diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/cpu_cortexa53_v1_2/src/xcpu_cortexa53.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/cpu_cortexa53_v1_5/src/xcpu_cortexa53.h similarity index 86% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/cpu_cortexa53_v1_2/src/xcpu_cortexa53.h rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/cpu_cortexa53_v1_5/src/xcpu_cortexa53.h index 6083206d0..62a4a3247 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/cpu_cortexa53_v1_2/src/xcpu_cortexa53.h +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/cpu_cortexa53_v1_5/src/xcpu_cortexa53.h @@ -33,11 +33,16 @@ /** * * @file xcpu_cortexa53.h -* @addtogroup cpu_cortexa53_v1_0 +* @addtogroup cpu_cortexa53_v1_5 * @{ * @details * * dummy file +* MODIFICATION HISTORY: * +* Ver Who Date Changes +* ----- ---- -------- --------------------------------------------------------- +* 1.4 ms 04/18/17 Modified tcl file to add suffix U for XPAR_CPU_ID +* parameter of cpu_cortexa53 in xparameters.h ******************************************************************************/ /** @} */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_1/src/Makefile b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_2/src/Makefile similarity index 100% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_1/src/Makefile rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_2/src/Makefile diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/xcsudma.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_2/src/xcsudma.c similarity index 90% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/xcsudma.c rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_2/src/xcsudma.c index 4ed4dd60b..9aa4beedb 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/xcsudma.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_2/src/xcsudma.c @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2014-2018 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -34,7 +34,7 @@ /** * * @file xcsudma.c -* @addtogroup csudma_v1_0 +* @addtogroup csudma_v1_2 * @{ * * This file contains the implementation of the interface functions for CSU_DMA @@ -188,6 +188,80 @@ void XCsuDma_Transfer(XCsuDma *InstancePtr, XCsuDma_Channel Channel, } } +/*****************************************************************************/ +/** +* +* This function sets the starting address and amount(size) of the data to be +* transfered from/to the memory through the AXI interface. +* This function is useful for pmu processor when it wishes to do +* a 64-bit DMA transfer. +* +* @param InstancePtr is a pointer to XCsuDma instance to be worked on. +* @param Channel represents the type of channel either it is Source or +* Destination. +* Source channel - XCSUDMA_SRC_CHANNEL +* Destination Channel - XCSUDMA_DST_CHANNEL +* @param AddrLow is a 32 bit variable which holds the starting lower address of +* data which needs to write into the memory(DST) (or read from +* the memory(SRC)). +* @param AddrHigh is a 32 bit variable which holds the higher address of data +* which needs to write into the memory(DST) (or read from +* the memroy(SRC)). +* @param Size is a 32 bit variable which represents the number of 4 byte +* words needs to be transfered from starting address. +* @param EnDataLast is to trigger an end of message. It will enable or +* disable data_inp_last signal to stream interface when current +* command is completed. It is applicable only to source channel +* and neglected for destination channel. +* - 1 - Asserts data_inp_last signal. +* - 0 - data_inp_last will not be asserted. +* +* @return None. +* +* @note Data_inp_last signal is asserted simultaneously with the +* data_inp_valid signal associated with the final 32-bit word +* transfer +* This API won't do flush/invalidation for the DMA buffer. +* It is recommened to call this API only through PMU processor. +* +******************************************************************************/ +void XCsuDma_64BitTransfer(XCsuDma *InstancePtr, XCsuDma_Channel Channel, + u32 AddrLow, u32 AddrHigh, u32 Size, u8 EnDataLast) +{ + /* Verify arguments */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid((Channel == (XCSUDMA_SRC_CHANNEL)) || + (Channel == (XCSUDMA_DST_CHANNEL))); + Xil_AssertVoid(Size <= (u32)(XCSUDMA_SIZE_MAX)); + Xil_AssertVoid(InstancePtr->IsReady == (u32)(XIL_COMPONENT_IS_READY)); + + + XCsuDma_WriteReg(InstancePtr->Config.BaseAddress, + ((u32)(XCSUDMA_ADDR_OFFSET) + + ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))), + (AddrLow & XCSUDMA_ADDR_MASK)); + + XCsuDma_WriteReg(InstancePtr->Config.BaseAddress, + ((u32)(XCSUDMA_ADDR_MSB_OFFSET) + + ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))), + (AddrHigh & XCSUDMA_MSB_ADDR_MASK)); + + if (EnDataLast == (u8)(XCSUDMA_LAST_WORD_MASK)) { + XCsuDma_WriteReg(InstancePtr->Config.BaseAddress, + ((u32)(XCSUDMA_SIZE_OFFSET) + + ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))), + ((Size << (u32)(XCSUDMA_SIZE_SHIFT)) | + (u32)(XCSUDMA_LAST_WORD_MASK))); + } + else { + XCsuDma_WriteReg(InstancePtr->Config.BaseAddress, + ((u32)(XCSUDMA_SIZE_OFFSET) + + ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))), + (Size << (u32)(XCSUDMA_SIZE_SHIFT))); + } +} + +/*****************************************************************************/ /*****************************************************************************/ /** * diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_1/src/xcsudma.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_2/src/xcsudma.h similarity index 95% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_1/src/xcsudma.h rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_2/src/xcsudma.h index 03a32c1ce..fc675a13c 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_1/src/xcsudma.h +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_2/src/xcsudma.h @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2014-2018 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -82,7 +82,7 @@ * to build and link only those parts of the driver that are necessary. * * @file xcsudma.h -* @addtogroup csudma_v1_0 +* @addtogroup csudma_v1_2 * @{ * @details * @@ -99,6 +99,13 @@ * 1.0 vnsld 22/10/14 First release * 1.1 adk 10/05/16 Fixed CR#951040 race condition in the recv path when * source and destination points to the same buffer. +* ms 03/17/17 Added readme.txt file in examples folder for doxygen +* generation. +* ms 04/10/17 Modified filename tag in xcsudma_selftest_example.c to +* include the file in doxygen examples. +* 1.2 adk 11/22/17 Added peripheral test app support for CSUDMA driver. +* adk 09/03/18 Added new API XCsuDma_64BitTransfer() useful for 64-bit +* dma transfers through PMU processor(CR#996201). * * ******************************************************************************/ @@ -373,6 +380,8 @@ s32 XCsuDma_CfgInitialize(XCsuDma *InstancePtr, XCsuDma_Config *CfgPtr, u32 EffectiveAddr); void XCsuDma_Transfer(XCsuDma *InstancePtr, XCsuDma_Channel Channel, UINTPTR Addr, u32 Size, u8 EnDataLast); +void XCsuDma_64BitTransfer(XCsuDma *InstancePtr, XCsuDma_Channel Channel, + u32 AddrLow, u32 AddrHigh, u32 Size, u8 EnDataLast); void XCsuDma_LoopBackTransfer(XCsuDma *InstancePtr, u64 SrcAddr, u64 DstAddr, u32 Size); u64 XCsuDma_GetAddr(XCsuDma *InstancePtr, XCsuDma_Channel Channel); diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/xcsudma_g.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_2/src/xcsudma_g.c similarity index 90% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/xcsudma_g.c rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_2/src/xcsudma_g.c index 09e7f739a..1c2317e8e 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/xcsudma_g.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_2/src/xcsudma_g.c @@ -5,7 +5,7 @@ * Version: * DO NOT EDIT. * -* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.* +* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.* *Permission is hereby granted, free of charge, to any person obtaining a copy *of this software and associated documentation files (the Software), to deal *in the Software without restriction, including without limitation the rights @@ -44,7 +44,7 @@ * The configuration table for devices */ -XCsuDma_Config XCsuDma_ConfigTable[] = +XCsuDma_Config XCsuDma_ConfigTable[XPAR_XCSUDMA_NUM_INSTANCES] = { { XPAR_PSU_CSUDMA_DEVICE_ID, diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/xcsudma_hw.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_2/src/xcsudma_hw.h similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/xcsudma_hw.h rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_2/src/xcsudma_hw.h index 6b2c2cdb8..031c13458 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/xcsudma_hw.h +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_2/src/xcsudma_hw.h @@ -33,7 +33,7 @@ /** * * @file xcsudma_hw.h -* @addtogroup csudma_v1_0 +* @addtogroup csudma_v1_2 * @{ * * This header file contains identifiers and register-level driver functions (or diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/xcsudma_intr.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_2/src/xcsudma_intr.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/xcsudma_intr.c rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_2/src/xcsudma_intr.c index 9f37e4582..b45d6cf29 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/xcsudma_intr.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_2/src/xcsudma_intr.c @@ -34,7 +34,7 @@ /** * * @file xcsudma_intr.c -* @addtogroup csudma_v1_0 +* @addtogroup csudma_v1_2 * @{ * * This file contains interrupt related functions of Xilinx CSU_DMA core. diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/xcsudma_selftest.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_2/src/xcsudma_selftest.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/xcsudma_selftest.c rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_2/src/xcsudma_selftest.c index f61910fd4..00f35e145 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/xcsudma_selftest.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_2/src/xcsudma_selftest.c @@ -34,7 +34,7 @@ /** * * @file xcsudma_selftest.c -* @addtogroup csudma_v1_0 +* @addtogroup csudma_v1_2 * @{ * * This file contains a diagnostic self-test function for the CSU_DMA driver. diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_1/src/xcsudma_sinit.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_2/src/xcsudma_sinit.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_1/src/xcsudma_sinit.c rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_2/src/xcsudma_sinit.c index 10e5c14f6..be962e298 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_1/src/xcsudma_sinit.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_2/src/xcsudma_sinit.c @@ -34,7 +34,7 @@ /** * * @file xcsudma_sinit.c -* @addtogroup csudma_v1_0 +* @addtogroup csudma_v1_2 * @{ * * This file contains static initialization methods for Xilinx CSU_DMA core. diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ddrcpsu_v1_1/src/xddrcpsu.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ddrcpsu_v1_1/src/xddrcpsu.h index 2640a9462..412f335e4 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ddrcpsu_v1_1/src/xddrcpsu.h +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ddrcpsu_v1_1/src/xddrcpsu.h @@ -18,15 +18,14 @@ * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * * Except as contained in this notice, the name of the Xilinx shall not be used * in advertising or otherwise to promote the sale, use or other dealings in - * in advertising or otherwise to promote the sale, use or other dealings in * this Software without prior written authorization from Xilinx. * *******************************************************************************/ @@ -34,7 +33,7 @@ /** * * @file xddcrpsu.h - * @addtogroup ddrcpsu_v1_0 + * @addtogroup ddrcpsu_v1_1 * @{ * @details * diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/dpdma_v1_0/src/Makefile b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/dpdma_v1_0/src/Makefile new file mode 100644 index 000000000..f5944f9d2 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/dpdma_v1_0/src/Makefile @@ -0,0 +1,40 @@ +COMPILER= +ARCHIVER= +CP=cp +COMPILER_FLAGS= +EXTRA_COMPILER_FLAGS= +LIB=libxil.a + +CC_FLAGS = $(COMPILER_FLAGS) +ECC_FLAGS = $(EXTRA_COMPILER_FLAGS) + +RELEASEDIR=../../../lib +INCLUDEDIR=../../../include +INCLUDES=-I./. -I${INCLUDEDIR} + +OUTS = *.o + +LIBSOURCES:=*.c +INCLUDEFILES:=*.h + +OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c))) + +libs: banner dpdma_libs clean + +%.o: %.c + ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $< + +banner: + echo "Compiling dpdma" + +dpdma_libs: ${OBJECTS} + $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS} + +.PHONY: include +include: dpdma_includes + +dpdma_includes: + ${CP} ${INCLUDEFILES} ${INCLUDEDIR} + +clean: + rm -rf ${OBJECTS} diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/dpdma_v1_0/src/xdpdma.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/dpdma_v1_0/src/xdpdma.c new file mode 100644 index 000000000..92eaad2cd --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/dpdma_v1_0/src/xdpdma.c @@ -0,0 +1,966 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* + +*******************************************************************************/ +/*****************************************************************************/ +/** + * + * @file xdpdma.c + * + * This file contains the implementation of the interface functions of the + * XDpDma driver. Refer to xdpdma.h for detailed information. + * + * @note None. + * + * 
+ * MODIFICATION HISTORY:
+ *
+ * Ver	Who   Date     Changes
+ * ---- ----- -------- ----------------------------------------------------
+ * 1.0  aad   04/12/16 Initial release.
+ *
+ *****************************************************************************/
+
+/***************************** Include Files **********************************/
+#include "xdpdma.h"
+#include "xavbuf.h"
+
+/************************** Constant Definitions ******************************/
+#define XDPDMA_CH_OFFSET		0x100
+#define XDPDMA_WAIT_TIMEOUT		10000
+
+#define XDPDMA_AUDIO_ALIGNMENT		128
+
+#define XDPDMA_VIDEO_CHANNEL0		0
+#define XDPDMA_VIDEO_CHANNEL1		1
+#define XDPDMA_VIDEO_CHANNEL2		2
+#define XDPDMA_GRAPHICS_CHANNEL		3
+#define XDPDMA_AUDIO_CHANNEL0		4
+#define XDPDMA_AUDIO_CHANNEL1		5
+
+#define XDPDMA_DESC_PREAMBLE		0xA5
+#define XDPDMA_DESC_IGNR_DONE		0x400
+#define XDPDMA_DESC_UPDATE		0x200
+#define XDPDMA_DESC_COMP_INTR		0x100
+#define XDPDMA_DESC_LAST_FRAME		0x200000
+#define XDPDMA_DESC_DONE_SHIFT		31
+#define XDPDMA_QOS_MIN			4
+#define XDPDMA_QOS_MAX			11
+
+/*************************************************************************/
+/**
+ *
+ * This function returns the number of outstanding transactions on a given
+ * channel.
+ *
+ * @param    InstancePtr is a pointer to the driver instance.
+ * @param    ChannelNum is the channel number on which the operation is
+ *	     being carried out.
+ *
+ * @return   Number of pending transactions.
+ *
+ * @note     None.
+ *
+ * **************************************************************************/
+static int XDpDma_GetPendingTransaction(XDpDma *InstancePtr, u32 ChannelNum)
+{
+	u32 RegVal;
+	RegVal = XDpDma_ReadReg(InstancePtr->Config.BaseAddr,
+				XDPDMA_CH0_STATUS + 0x100 * ChannelNum);
+	return (RegVal & XDPDMA_CH_STATUS_OTRAN_CNT_MASK);
+}
+
+/*************************************************************************/
+/**
+ *
+ * This function waits until the outstanding transactions are completed.
+ *
+ * @param    InstancePtr is a pointer to the driver instance.
+ * @param    ChannelNum is the channel number on which the operation is
+ *	     being carried out.
+ *
+ * @return   XST_SUCCESS when all the pending transactions are complete
+ *	     before timeout.
+ *	     XST_FAILURE if timeout occurs before pending transactions are
+ *	     completed.
+ *
+ * @note     None.
+ *
+ * **************************************************************************/
+static int XDpDma_WaitPendingTransaction(XDpDma *InstancePtr, u8 ChannelNum)
+{
+	/* Verify arguments. */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(ChannelNum <= XDPDMA_AUDIO_CHANNEL1);
+
+	u32 Timeout = 0;
+	u32 Count;
+	do {
+		Count = XDpDma_GetPendingTransaction(InstancePtr, ChannelNum);
+		Timeout++;
+	} while((Timeout != XDPDMA_WAIT_TIMEOUT) && Count);
+
+	if(Timeout ==  XDPDMA_WAIT_TIMEOUT) {
+		return XST_FAILURE;
+	}
+
+	return XST_SUCCESS;
+}
+
+/*************************************************************************/
+/**
+ *
+ * This function controls the hardware channels of the DPDMA.
+ *
+ *
+ * @param    InstancePtr is a pointer to the driver instance.
+ * @param    ChannelNum is the physical channel number of the DPDMA.
+ * @param    ChannelState is an enum of type XDpDma_ChannelState.
+ *
+ * @return   XST_SUCCESS when the mentioned channel is enabled successfully.
+ *	     XST_FAILURE when the mentioned channel fails to be enabled.
+ *
+ * @note     None.
+ *
+ * **************************************************************************/
+static int XDpDma_ConfigChannelState(XDpDma *InstancePtr, u8 ChannelNum,
+				     XDpDma_ChannelState Enable)
+{
+	u32 Mask = 0;
+	u32 RegVal = 0;
+	u32 Status = 0;
+	/* Verify arguments. */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(ChannelNum <= XDPDMA_AUDIO_CHANNEL1);
+
+	Mask = XDPDMA_CH_CNTL_EN_MASK | XDPDMA_CH_CNTL_PAUSE_MASK;
+	switch(Enable) {
+		case XDPDMA_ENABLE:
+			RegVal = XDPDMA_CH_CNTL_EN_MASK;
+			break;
+		case XDPDMA_DISABLE:
+			XDpDma_ConfigChannelState(InstancePtr, ChannelNum,
+						  XDPDMA_PAUSE);
+			Status = XDpDma_WaitPendingTransaction(InstancePtr,
+							       ChannelNum);
+			if(Status == XST_FAILURE) {
+				return XST_FAILURE;
+			}
+
+			RegVal = XDPDMA_DISABLE;
+			Mask = XDPDMA_CH_CNTL_EN_MASK;
+			break;
+		case XDPDMA_IDLE:
+			Status = XDpDma_ConfigChannelState(InstancePtr,
+							   ChannelNum,
+							   XDPDMA_DISABLE);
+			if(Status == XST_FAILURE) {
+				return XST_FAILURE;
+			}
+
+			RegVal = 0;
+			break;
+		case XDPDMA_PAUSE:
+			RegVal = XDPDMA_PAUSE;
+			break;
+	}
+	XDpDma_ReadModifyWrite(InstancePtr->Config.BaseAddr,
+			       XDPDMA_CH0_CNTL + XDPDMA_CH_OFFSET * ChannelNum,
+			       RegVal, Mask);
+	return XST_SUCCESS;
+}
+
+/*************************************************************************/
+/**
+ *
+ * This function updates the descriptor that is not currently active on a
+ * Video/Graphics channel.
+ *
+ * @param    InstancePtr is a pointer to the driver instance.
+ * @param    Channel is a pointer to the channel on which the operation is
+ *	     to be carried out.
+ *
+ * @return   Descriptor for next operation.
+ *
+ * @note     None.
+ *
+ * **************************************************************************/
+static XDpDma_Descriptor *XDpDma_UpdateVideoDescriptor(XDpDma_Channel *Channel)
+{
+	if(Channel->Current == NULL) {
+		Channel->Current = &Channel->Descriptor0;
+	}
+	else if(Channel->Current == &Channel->Descriptor0) {
+		Channel->Current = &Channel->Descriptor1;
+	}
+	else if(Channel->Current == &Channel->Descriptor1) {
+		Channel->Current = &Channel->Descriptor0;
+	}
+	return Channel->Current;
+}
+
+/*************************************************************************/
+/**
+ * This function programs the address of the descriptor about to be active
+ *
+ * @param    InstancePtr is a pointer to the DPDMA instance.
+ * @param    Channel is an enum of the channel for which the descriptor
+ *	     address is to be set.
+ *
+ * @return   Descriptor for next operation.
+ *
+ * @note     None.
+ *
+ * **************************************************************************/
+static void XDpDma_SetDescriptorAddress(XDpDma *InstancePtr, u8 ChannelNum)
+{
+	u32 AddrOffset;
+	u32 AddrEOffset;
+	Xil_AssertVoid(ChannelNum <= XDPDMA_AUDIO_CHANNEL1);
+	AddrOffset = XDPDMA_CH0_DSCR_STRT_ADDR +
+					(XDPDMA_CH_OFFSET * ChannelNum);
+	AddrEOffset = XDPDMA_CH0_DSCR_STRT_ADDRE +
+					(XDPDMA_CH_OFFSET * ChannelNum);
+
+	XDpDma_Descriptor *Descriptor = NULL;
+	switch(ChannelNum) {
+	case XDPDMA_VIDEO_CHANNEL0:
+		Descriptor = InstancePtr->Video.Channel[ChannelNum].Current;
+		break;
+	case XDPDMA_VIDEO_CHANNEL1:
+		Descriptor = InstancePtr->Video.Channel[ChannelNum].Current;
+		break;
+	case XDPDMA_VIDEO_CHANNEL2:
+		Descriptor = InstancePtr->Video.Channel[ChannelNum].Current;
+		break;
+	case XDPDMA_GRAPHICS_CHANNEL:
+		Descriptor = InstancePtr->Gfx.Channel.Current;
+		break;
+	case XDPDMA_AUDIO_CHANNEL0:
+		Descriptor = InstancePtr->Audio[0].Current;
+		break;
+	case XDPDMA_AUDIO_CHANNEL1:
+		Descriptor = InstancePtr->Audio[1].Current;
+		break;
+	}
+
+	XDpDma_WriteReg(InstancePtr->Config.BaseAddr, AddrEOffset,
+			(INTPTR) Descriptor >> 32);
+	XDpDma_WriteReg(InstancePtr->Config.BaseAddr, AddrOffset,
+			(INTPTR) Descriptor);
+}
+
+/*************************************************************************/
+/**
+ *
+ * This functions sets the Audio Descriptor for Data Transfer.
+ *
+ * @param    CurrDesc is a pointer to the descriptor to be initialized
+ * @param    DataSize is the payload size of the buffer to be transferred
+ * @param    BuffAddr is the payload address
+ *
+ * @return   None.
+ *
+ * @note     None.
+ *
+ * **************************************************************************/
+static void XDpDma_SetupAudioDescriptor(XDpDma_Descriptor *CurrDesc,
+					u64 DataSize, u64 BuffAddr,
+					XDpDma_Descriptor *NextDesc)
+{
+	Xil_AssertVoid(CurrDesc != NULL);
+	Xil_AssertVoid(DataSize != 0);
+	Xil_AssertVoid(BuffAddr != 0);
+
+	if(NextDesc == NULL) {
+		CurrDesc->Control = XDPDMA_DESC_PREAMBLE |
+			XDPDMA_DESC_UPDATE | XDPDMA_DESC_IGNR_DONE |
+			XDPDMA_DESC_COMP_INTR;
+
+	}
+	else {
+		CurrDesc->Control = XDPDMA_DESC_PREAMBLE |
+			XDPDMA_DESC_UPDATE | XDPDMA_DESC_IGNR_DONE;
+	}
+	CurrDesc->DSCR_ID = 0;
+	CurrDesc->XFER_SIZE = DataSize;
+	CurrDesc->LINE_SIZE_STRIDE = 0;
+	CurrDesc->LSB_Timestamp = 0;
+	CurrDesc->MSB_Timestamp = 0;
+	CurrDesc->ADDR_EXT = ((BuffAddr >> XDPDMA_DESCRIPTOR_SRC_ADDR_WIDTH) <<
+			      XDPDMA_DESCRIPTOR_ADDR_EXT_SRC_ADDR_EXT_SHIFT) |
+			     ((INTPTR) NextDesc >>
+			      XDPDMA_DESCRIPTOR_NEXT_DESR_WIDTH);
+	CurrDesc->NEXT_DESR = (INTPTR) NextDesc;
+	CurrDesc->SRC_ADDR =  BuffAddr;
+}
+
+/*************************************************************************/
+/**
+ *
+ * This functions retrieves the configuration for this DPDMA driver and
+ * fills in the InstancePtr->Config structure.
+ *
+ * @param    InstancePtr is a pointer to the driver instance.
+ * @param    ConfigPtr is a pointer to the configuration structure that will
+ *           be used to copy the settings from.
+ *
+ * @return   None.
+ *
+ * @note     None.
+ *
+ * **************************************************************************/
+void XDpDma_CfgInitialize(XDpDma *InstancePtr, XDpDma_Config *CfgPtr)
+{
+	InstancePtr->Config.DeviceId = CfgPtr->DeviceId;
+	InstancePtr->Config.BaseAddr = CfgPtr->BaseAddr;
+
+	InstancePtr->Video.Channel[XDPDMA_VIDEO_CHANNEL0].Current = NULL;
+	InstancePtr->Video.Channel[XDPDMA_VIDEO_CHANNEL1].Current = NULL;
+	InstancePtr->Video.Channel[XDPDMA_VIDEO_CHANNEL2].Current = NULL;
+	InstancePtr->Video.TriggerStatus = XDPDMA_TRIGGER_DONE;
+	InstancePtr->Video.VideoInfo = NULL;
+	InstancePtr->Video.FrameBuffer[XDPDMA_VIDEO_CHANNEL0] = NULL;
+	InstancePtr->Video.FrameBuffer[XDPDMA_VIDEO_CHANNEL1] = NULL;
+	InstancePtr->Video.FrameBuffer[XDPDMA_VIDEO_CHANNEL2] = NULL;
+
+	InstancePtr->Gfx.Channel.Current = NULL;
+	InstancePtr->Gfx.TriggerStatus = XDPDMA_TRIGGER_DONE;
+	InstancePtr->Gfx.VideoInfo = NULL;
+	InstancePtr->Gfx.FrameBuffer = NULL;
+}
+
+/*************************************************************************/
+/**
+ *
+ * This functions controls the states in which a channel should go into.
+ *
+ * @param    InstancePtr is a pointer to the driver instance.
+ * @param    ChannelType is an enum of XDpDma_ChannelType.
+ * @param    ChannelState is an enum of type XDpDma_ChannelState.
+ *
+ * @return   XST_SUCCESS when the mentioned channel is enabled successfully.
+ *	     XST_FAILURE when the mentioned channel fails to be enabled.
+ *
+ * @note     None.
+ *
+ * **************************************************************************/
+int XDpDma_SetChannelState(XDpDma *InstancePtr, XDpDma_ChannelType Channel,
+					XDpDma_ChannelState ChannelState)
+{
+	u32 Index = 0;
+	u32 NumPlanes = 0;
+	u32 Status = 0;
+	/* Verify arguments. */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	switch(Channel) {
+	case VideoChan:
+		if(InstancePtr->Video.VideoInfo == NULL) {
+			return XST_FAILURE;
+		}
+		else {
+			NumPlanes = InstancePtr->Video.VideoInfo->Mode;
+			for(Index = 0; Index <= NumPlanes; Index++) {
+				Status = XDpDma_ConfigChannelState(InstancePtr,
+								Index,
+								ChannelState);
+				if(Status == XST_FAILURE) {
+					return XST_FAILURE;
+				}
+			}
+		}
+		break;
+	case GraphicsChan:
+		if(InstancePtr->Gfx.VideoInfo == NULL) {
+			return XST_FAILURE;
+		}
+		else {
+			return	XDpDma_ConfigChannelState(InstancePtr,
+					      XDPDMA_GRAPHICS_CHANNEL,
+					      ChannelState);
+		}
+		break;
+	case AudioChan0:
+		return	XDpDma_ConfigChannelState(InstancePtr,
+						  XDPDMA_AUDIO_CHANNEL0,
+						  ChannelState);
+		break;
+	case AudioChan1:
+		return XDpDma_ConfigChannelState(InstancePtr,
+						 XDPDMA_AUDIO_CHANNEL1,
+						 ChannelState);
+		break;
+	default:
+		return XST_FAILURE;
+		break;
+	}
+
+	return XST_SUCCESS;
+}
+
+/*************************************************************************/
+/**
+ *
+ * This function allocates DPDMA Video Channels depending on the number of
+ * planes in the video
+ *
+ * @param	InstancePtr is a pointer to the driver instance.
+ * @params	Format is the video format to be used for the DPDMA transfer
+ *
+ * @return	XST_SUCCESS, When the format is valid Video Format.
+ *		XST_FAILURE, When the format is not valid Video Format
+ *
+ * @note	None.
+ *
+ * **************************************************************************/
+int XDpDma_SetVideoFormat(XDpDma *InstancePtr, XAVBuf_VideoFormat Format)
+{
+	/* Verify arguments. */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	InstancePtr->Video.VideoInfo = XAVBuf_GetNLiveVideoAttribute(Format);
+	if(InstancePtr->Video.VideoInfo == NULL) {
+		return XST_FAILURE;
+	}
+
+	return XST_SUCCESS;
+}
+
+/*************************************************************************/
+/**
+ *
+ * This function allocates DPDMA Graphics Channels.
+ *
+ * @param	InstancePtr is a pointer to the driver instance.
+ * @params	Format is the video format to be used for the DPDMA transfer
+ *
+ * @return	XST_SUCCESS, When the format is a valid Graphics Format.
+ *		XST_FAILURE, When the format is not valid Graphics Format.
+ *
+ * @note	None.
+ *
+ * **************************************************************************/
+int XDpDma_SetGraphicsFormat(XDpDma *InstancePtr, XAVBuf_VideoFormat Format)
+{
+
+	/* Verify arguments. */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	InstancePtr->Gfx.VideoInfo = XAVBuf_GetNLGraphicsAttribute(Format);
+	if(InstancePtr->Gfx.VideoInfo == NULL) {
+		return XST_FAILURE;
+	}
+
+	return XST_SUCCESS;
+}
+
+/*************************************************************************/
+/**
+ *
+ * This function starts the operation on the a given channel
+ *
+ * @param    InstancePtr is a pointer to the driver instance.
+ * @param    QOS is the Quality of Service value to be selected.
+ *
+ * @return   None.
+ *
+ * @note     .
+ *
+ * **************************************************************************/
+void XDpDma_SetQOS(XDpDma *InstancePtr, u8 QOS)
+{
+	u8 Index;
+	u32 RegVal = 0;
+
+	Xil_AssertVoid(QOS >= XDPDMA_QOS_MIN && QOS <= XDPDMA_QOS_MAX);
+
+	RegVal = ((QOS << XDPDMA_CH_CNTL_QOS_DATA_RD_SHIFT) |
+		   (QOS << XDPDMA_CH_CNTL_QOS_DSCR_RD_SHIFT) |
+		   (QOS << XDPDMA_CH_CNTL_QOS_DSCR_WR_SHIFT));
+
+	u32 Mask = XDPDMA_CH_CNTL_QOS_DATA_RD_MASK |
+		XDPDMA_CH_CNTL_QOS_DSCR_RD_MASK |
+		XDPDMA_CH_CNTL_QOS_DSCR_WR_MASK;
+
+	for(Index = 0; Index <= XDPDMA_AUDIO_CHANNEL1; Index++) {
+		XDpDma_ReadModifyWrite(InstancePtr->Config.BaseAddr,
+				XDPDMA_CH0_CNTL + (XDPDMA_CH_OFFSET * Index),
+			        RegVal, Mask);
+	}
+
+}
+
+/*************************************************************************/
+/**
+ *
+ * This function Triggers DPDMA to start the transaction.
+ *
+ * @param	InstancePtr is a pointer to the XDpDma instance.
+ * @param	Channel is the XDpDma_ChannelType on which the transaction
+ *		is to be triggered.
+ *
+ * @return	XST_SUCCESS The channel has successfully been Triggered.
+ *		XST_FAILURE When the triggering Video and Graphics channel
+ *		without setting the Video Formats.
+ *
+ * @note	None.
+ *
+ * **************************************************************************/
+int XDpDma_Trigger(XDpDma *InstancePtr, XDpDma_ChannelType Channel)
+{
+	u32 Trigger = 0;
+	u8 Index = 0;
+	u8 NumPlanes = 0;
+	switch(Channel) {
+	case VideoChan:
+		if(InstancePtr->Video.VideoInfo == NULL) {
+			return XST_FAILURE;
+		}
+		else {
+			NumPlanes = InstancePtr->Video.VideoInfo->Mode;
+			for(Index = 0; Index <= NumPlanes; Index++) {
+				Trigger |= XDPDMA_GBL_TRG_CH0_MASK << Index;
+				InstancePtr->Video.TriggerStatus =
+					XDPDMA_TRIGGER_DONE;
+			}
+		}
+		break;
+	case GraphicsChan:
+		if(InstancePtr->Gfx.VideoInfo == NULL) {
+			return XST_FAILURE;
+		}
+		Trigger = XDPDMA_GBL_TRG_CH3_MASK;
+		InstancePtr->Gfx.TriggerStatus = XDPDMA_TRIGGER_DONE;
+		break;
+	case AudioChan0:
+		Trigger = XDPDMA_GBL_TRG_CH4_MASK;
+		InstancePtr->Audio[0].TriggerStatus = XDPDMA_TRIGGER_DONE;
+		break;
+	case AudioChan1:
+		Trigger = XDPDMA_GBL_TRG_CH5_MASK;
+		InstancePtr->Audio[1].TriggerStatus = XDPDMA_TRIGGER_DONE;
+		break;
+	}
+	XDpDma_WriteReg(InstancePtr->Config.BaseAddr, XDPDMA_GBL, Trigger);
+
+	return XST_SUCCESS;
+
+}
+
+/*************************************************************************/
+/**
+ *
+ * This function Retriggers DPDMA to fetch data from new descriptor.
+ *
+ * @param	InstancePtr is a pointer to the XDpDma instance.
+ * @param	Channel is the XDpDma_ChannelType on which the transaction
+ *		is to be retriggered.
+ *
+ * @return	XST_SUCCESS The channel has successfully been Triggered.
+ *		XST_FAILURE When the triggering Video and Graphics channel
+ *		without setting the Video Formats.
+ *
+ * @note	None.
+ *
+ * **************************************************************************/
+int XDpDma_ReTrigger(XDpDma *InstancePtr, XDpDma_ChannelType Channel)
+{
+	u32 Trigger = 0;
+	u8 NumPlanes;
+	u8 Index;
+	switch(Channel) {
+	case VideoChan:
+		if(InstancePtr->Video.VideoInfo == NULL) {
+			return XST_FAILURE;
+		}
+		else {
+			NumPlanes = InstancePtr->Video.VideoInfo->Mode;
+			for(Index = 0; Index <= NumPlanes; Index++) {
+				Trigger |= XDPDMA_GBL_RTRG_CH0_MASK << Index;
+				InstancePtr->Video.TriggerStatus =
+					XDPDMA_RETRIGGER_DONE;
+			}
+		}
+		break;
+	case GraphicsChan:
+		if(InstancePtr->Gfx.VideoInfo == NULL) {
+			return XST_FAILURE;
+		}
+		Trigger = XDPDMA_GBL_RTRG_CH3_MASK;
+		InstancePtr->Gfx.TriggerStatus = XDPDMA_RETRIGGER_DONE;
+		break;
+	case AudioChan0:
+		Trigger = XDPDMA_GBL_RTRG_CH4_MASK;
+		InstancePtr->Audio[0].TriggerStatus = XDPDMA_RETRIGGER_DONE;
+		break;
+	case AudioChan1:
+		Trigger = XDPDMA_GBL_RTRG_CH5_MASK;
+		InstancePtr->Audio[1].TriggerStatus = XDPDMA_RETRIGGER_DONE;
+		break;
+	}
+	XDpDma_WriteReg(InstancePtr->Config.BaseAddr, XDPDMA_GBL, Trigger);
+
+	return XST_SUCCESS;
+}
+
+/*************************************************************************/
+/**
+ *
+ * This function intializes Video Descriptor for Video and Graphics channel
+ *
+ * @param    Channel is a pointer to the current Descriptor of Video or
+ *	     Graphics Channel.
+ * @param    FrameBuffer is a pointer to the Frame Buffer structure
+ *
+ * @return   None.
+ *
+ * @note     None.
+ *
+ * **************************************************************************/
+void XDpDma_InitVideoDescriptor(XDpDma_Descriptor *CurrDesc,
+				XDpDma_FrameBuffer *FrameBuffer)
+{
+	Xil_AssertVoid(CurrDesc != NULL);
+	Xil_AssertVoid(FrameBuffer != NULL);
+	Xil_AssertVoid((FrameBuffer->Stride) % XDPDMA_DESCRIPTOR_ALIGN == 0);
+	CurrDesc->Control = XDPDMA_DESC_PREAMBLE | XDPDMA_DESC_IGNR_DONE |
+			    XDPDMA_DESC_LAST_FRAME;
+	CurrDesc->DSCR_ID = 0;
+	CurrDesc->XFER_SIZE = FrameBuffer->Size;
+	CurrDesc->LINE_SIZE_STRIDE = ((FrameBuffer->Stride >> 4) <<
+				XDPDMA_DESCRIPTOR_LINE_SIZE_STRIDE_SHIFT) |
+				(FrameBuffer->LineSize);
+	CurrDesc->ADDR_EXT = (((FrameBuffer->Address >>
+				XDPDMA_DESCRIPTOR_SRC_ADDR_WIDTH) <<
+			       XDPDMA_DESCRIPTOR_ADDR_EXT_SRC_ADDR_EXT_SHIFT) |
+				((INTPTR) CurrDesc >>
+				 XDPDMA_DESCRIPTOR_NEXT_DESR_WIDTH));
+	CurrDesc->NEXT_DESR = (INTPTR) CurrDesc;
+	CurrDesc->SRC_ADDR = FrameBuffer->Address;
+}
+
+/*************************************************************************/
+/**
+ *
+ * This function intializes Descriptors for transactions on Audio Channel
+ *
+ * @param    Channel is a pointer to the XDpDma_AudioChannel instance
+ *
+ * @param    AudioBuffer is a pointer to the Audio Buffer structure
+ *
+ * @return   None.
+ *
+ * @note     None.
+ *
+ * **************************************************************************/
+void XDpDma_InitAudioDescriptor(XDpDma_AudioChannel *Channel,
+			       XDpDma_AudioBuffer *AudioBuffer)
+{
+	u32 Size;
+	u64 Address;
+	Xil_AssertVoid(Channel != NULL);
+	Xil_AssertVoid(AudioBuffer != NULL);
+	Xil_AssertVoid((AudioBuffer->Size) % XDPDMA_AUDIO_ALIGNMENT == 0);
+	Xil_AssertVoid((AudioBuffer->Address) % XDPDMA_AUDIO_ALIGNMENT == 0);
+
+	Size = AudioBuffer->Size / 4;
+	Address = AudioBuffer->Address;
+	if(Channel->Current == &Channel->Descriptor4) {
+		XDpDma_SetupAudioDescriptor(&Channel->Descriptor4, Size,
+					    Address,
+					    &Channel->Descriptor5);
+		XDpDma_SetupAudioDescriptor(&Channel->Descriptor5, Size,
+					    Address + Size,
+					    &Channel->Descriptor6);
+		XDpDma_SetupAudioDescriptor(&Channel->Descriptor6, Size,
+					    Address + (Size * 2),
+					    &Channel->Descriptor7);
+		XDpDma_SetupAudioDescriptor(&Channel->Descriptor7, Size,
+					    Address + (Size * 3), NULL);
+	}
+
+	else if(Channel->Current == &Channel->Descriptor0) {
+		XDpDma_SetupAudioDescriptor(&Channel->Descriptor0, Size,
+					    Address,
+					    &Channel->Descriptor1);
+		XDpDma_SetupAudioDescriptor(&Channel->Descriptor1, Size,
+					    Address + Size,
+					    &Channel->Descriptor2);
+		XDpDma_SetupAudioDescriptor(&Channel->Descriptor2, Size,
+					    Address + (Size * 2),
+					    &Channel->Descriptor3);
+		XDpDma_SetupAudioDescriptor(&Channel->Descriptor3, Size,
+					    Address + (Size * 3), NULL);
+
+	}
+}
+
+/*************************************************************************/
+/**
+ *
+ * This function sets the next Frame Buffers to be displayed on the Video
+ * Channel.
+ *
+ * @param    InstancePtr is pointer to the instance of DPDMA.
+ * @param    Plane0 is a pointer to the Frame Buffer structure.
+ * @param    Plane1 is a pointer to the Frame Buffer structure.
+ * @param    Plane2 is a pointer to the Frame Buffer structure.
+ *
+ * @return   None.
+ *
+ * @note     For interleaved mode use Plane0.
+ *	     For semi-planar mode use Plane0 and Plane1.
+ *	     For planar mode use Plane0, Plane1 and Plane2
+ *
+ * **************************************************************************/
+void  XDpDma_DisplayVideoFrameBuffer(XDpDma *InstancePtr,
+				     XDpDma_FrameBuffer *Plane0,
+				     XDpDma_FrameBuffer *Plane1,
+				     XDpDma_FrameBuffer *Plane2)
+{
+	u8 NumPlanes;
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->Video.VideoInfo != NULL);
+
+	NumPlanes = InstancePtr->Video.VideoInfo->Mode;
+
+	switch(NumPlanes) {
+		case XDPDMA_VIDEO_CHANNEL2:
+			Xil_AssertVoid(Plane2 != NULL);
+			InstancePtr->Video.FrameBuffer[XDPDMA_VIDEO_CHANNEL2] =
+				Plane2;
+		case XDPDMA_VIDEO_CHANNEL1:
+			Xil_AssertVoid(Plane1 != NULL);
+			InstancePtr->Video.FrameBuffer[XDPDMA_VIDEO_CHANNEL1] =
+				Plane1;
+		case XDPDMA_VIDEO_CHANNEL0:
+			Xil_AssertVoid(Plane0 != NULL);
+			InstancePtr->Video.FrameBuffer[XDPDMA_VIDEO_CHANNEL0] =
+				Plane0;
+			break;
+	}
+
+	if(InstancePtr->Video.Channel[XDPDMA_VIDEO_CHANNEL0].Current == NULL) {
+		InstancePtr->Video.TriggerStatus = XDPDMA_TRIGGER_EN;
+	}
+	else {
+		InstancePtr->Video.TriggerStatus = XDPDMA_RETRIGGER_EN;
+	}
+}
+
+/*************************************************************************/
+/**
+ *
+ * This function sets the next Frame Buffers to be displayed on the Graphics
+ * Channel.
+ *
+ * @param    InstancePtr is pointer to the instance of DPDMA.
+ * @param    Plane is a pointer to the Frame Buffer structure.
+ *
+ * @return   None.
+ *
+ * @note     None.
+ *
+ **************************************************************************/
+void XDpDma_DisplayGfxFrameBuffer(XDpDma *InstancePtr,
+				  XDpDma_FrameBuffer *Plane)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Plane != NULL);
+
+	InstancePtr->Gfx.FrameBuffer = Plane;
+
+	if(InstancePtr->Gfx.Channel.Current == NULL) {
+		InstancePtr->Gfx.TriggerStatus = XDPDMA_TRIGGER_EN;
+	}
+	else {
+		InstancePtr->Gfx.TriggerStatus = XDPDMA_RETRIGGER_EN;
+	}
+}
+/*************************************************************************/
+/**
+ *
+ * This function sets the next Audio Buffer to be played on Audio Channel 0
+ *
+ * @param    InstancePtr is pointer to the instance of DPDMA.
+ * @param    Buffer is a pointer to the attributes of the Audio information
+ *	     to be played.
+ * @param    ChannelNum selects between Audio Channel 0 and Audio Channel 1
+ *
+ * @return   XST_SUCCESS when the play audio request is successful.
+ *	     XST_FAILURE when the play audio request fails, user has to
+ *	     retry to play the audio.
+ *
+ * @note     The user has to schedule new audio buffer before half the audio
+ *	     information is consumed by DPDMA to have a seamless playback.
+ *
+ **************************************************************************/
+int XDpDma_PlayAudio(XDpDma *InstancePtr, XDpDma_AudioBuffer *Buffer,
+		      u8 ChannelNum)
+{
+	XDpDma_AudioChannel *Channel;
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(Buffer != NULL);
+	Xil_AssertNonvoid(Buffer->Size >= 512);
+	Xil_AssertNonvoid(Buffer->Size % 128 == 0);
+	Xil_AssertNonvoid(Buffer->Address % 128 == 0);
+
+	Channel = &InstancePtr->Audio[ChannelNum];
+	Channel->Buffer = Buffer;
+
+	if(Channel->Current == NULL) {
+		Channel->TriggerStatus = XDPDMA_TRIGGER_EN;
+		Channel->Current = &Channel->Descriptor0;
+		Channel->Used = 0;
+	}
+
+else if(Channel->Current == &Channel->Descriptor0) {
+		/* Check if descriptor chain can be updated */
+		if(Channel->Descriptor1.MSB_Timestamp >>
+		   XDPDMA_DESC_DONE_SHIFT) {
+			Channel->Current = NULL;
+			return XST_FAILURE;
+		}
+		else if(Channel->Descriptor7.MSB_Timestamp >>
+			XDPDMA_DESC_DONE_SHIFT || !(Channel->Used)) {
+			Channel->Descriptor3.Control = XDPDMA_DESC_PREAMBLE |
+				XDPDMA_DESC_UPDATE | XDPDMA_DESC_IGNR_DONE;
+			Channel->Descriptor3.NEXT_DESR =
+				(INTPTR) &Channel->Descriptor4;
+			Channel->Descriptor3.ADDR_EXT &=
+				~XDPDMA_DESCRIPTOR_ADDR_EXT_DSC_NXT_MASK;
+			Channel->Descriptor3.ADDR_EXT |=
+				(INTPTR) &Channel->Descriptor4 >> 32;
+			Channel->Current = &Channel->Descriptor4;
+			Channel->Used = 1;
+			XDpDma_InitAudioDescriptor(Channel, Buffer);
+		}
+		else {
+			return XST_FAILURE;
+		}
+	}
+
+	else if(Channel->Current == &Channel->Descriptor4)  {
+		/* Check if descriptor chain can be updated */
+		if(Channel->Descriptor5.MSB_Timestamp >>
+		   XDPDMA_DESC_DONE_SHIFT) {
+			Channel->Current = NULL;
+			return XST_FAILURE;
+		}
+		else if(Channel->Descriptor3.MSB_Timestamp >>
+			XDPDMA_DESC_DONE_SHIFT) {
+			Channel->Descriptor7.Control = XDPDMA_DESC_PREAMBLE |
+				XDPDMA_DESC_UPDATE | XDPDMA_DESC_IGNR_DONE;
+			Channel->Descriptor7.NEXT_DESR =
+				(INTPTR) &Channel->Descriptor0;
+			Channel->Descriptor7.ADDR_EXT &=
+				~XDPDMA_DESCRIPTOR_ADDR_EXT_DSC_NXT_MASK;
+			Channel->Descriptor7.ADDR_EXT |=
+				(INTPTR) &Channel->Descriptor0 >> 32;
+			Channel->Current = &Channel->Descriptor0;
+			XDpDma_InitAudioDescriptor(Channel, Buffer);
+		}
+		else {
+			return XST_FAILURE;
+		}
+	}
+
+	return XST_SUCCESS;
+
+}
+/*************************************************************************/
+/**
+ *
+ * This function sets the channel with the latest framebuffer and the
+ * available descriptor for transfer on the next Vsync.
+ *
+ * @param    InstancePtr is pointer to the instance of DPDMA.
+ * @param    Channel indicates which channels are being setup for transfer.
+ *
+ * @return   None.
+ *
+ * @note     None.
+ *
+ **************************************************************************/
+void XDpDma_SetupChannel(XDpDma *InstancePtr, XDpDma_ChannelType Channel)
+{
+	XDpDma_Channel *Chan;
+	XDpDma_AudioChannel *AudChan;
+	XDpDma_FrameBuffer *FB;
+	XDpDma_AudioBuffer *AudioBuffer;
+	u8 Index, NumPlanes;
+	Xil_AssertVoid(InstancePtr != NULL);
+
+	switch(Channel) {
+		case VideoChan:
+			Xil_AssertVoid(InstancePtr->Video.VideoInfo != NULL);
+			Xil_AssertVoid(InstancePtr->Video.FrameBuffer != NULL);
+			NumPlanes = InstancePtr->Video.VideoInfo->Mode;
+			for(Index = 0; Index <= NumPlanes; Index++) {
+				Chan = &InstancePtr->Video.Channel[Index];
+				FB = InstancePtr->Video.FrameBuffer[Index];
+				XDpDma_UpdateVideoDescriptor(Chan);
+				XDpDma_InitVideoDescriptor(Chan->Current, FB);
+				XDpDma_SetDescriptorAddress(InstancePtr,
+							    Index);
+			}
+			break;
+
+		case GraphicsChan:
+			Xil_AssertVoid(InstancePtr->Gfx.VideoInfo != NULL);
+			Xil_AssertVoid(InstancePtr->Gfx.FrameBuffer != NULL);
+			Chan = &InstancePtr->Gfx.Channel;
+			FB = InstancePtr->Gfx.FrameBuffer;
+			XDpDma_UpdateVideoDescriptor(Chan);
+			XDpDma_InitVideoDescriptor(Chan->Current, FB);
+			XDpDma_SetDescriptorAddress(InstancePtr,
+						    XDPDMA_GRAPHICS_CHANNEL);
+			break;
+
+		case AudioChan0:
+			Xil_AssertVoid(InstancePtr->Audio[0].Buffer != NULL);
+			AudChan = &InstancePtr->Audio[0];
+			AudioBuffer = InstancePtr->Audio[0].Buffer;
+			XDpDma_InitAudioDescriptor(AudChan, AudioBuffer);
+			XDpDma_SetDescriptorAddress(InstancePtr,
+						    XDPDMA_AUDIO_CHANNEL0);
+			break;
+		case AudioChan1:
+			Xil_AssertVoid(InstancePtr->Audio[1].Buffer != NULL);
+			AudChan = &InstancePtr->Audio[1];
+			AudioBuffer = InstancePtr->Audio[1].Buffer;
+			XDpDma_InitAudioDescriptor(AudChan, AudioBuffer);
+			XDpDma_SetDescriptorAddress(InstancePtr,
+						    XDPDMA_AUDIO_CHANNEL1);
+			break;
+	}
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/dpdma_v1_0/src/xdpdma.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/dpdma_v1_0/src/xdpdma.h
new file mode 100644
index 000000000..95315b058
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/dpdma_v1_0/src/xdpdma.h
@@ -0,0 +1,283 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2017 Xilinx, Inc. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * Use of the Software is limited solely to applications:
+ * (a) running on a Xilinx device, or
+ * (b) that interact with a Xilinx device through a bus or interconnect.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+ * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Except as contained in this notice, the name of the Xilinx shall not be used
+ * in advertising or otherwise to promote the sale, use or other dealings in
+ * this Software without prior written authorization from Xilinx.
+ *
+ ******************************************************************************/
+
+/*****************************************************************************/
+/**
+ *
+ * @file xdpdma.h
+ *
+ * This file defines the functions implemented by the DPDMA driver present
+ * in the Zynq Ultrascale MP.
+ *
+ * @note	None.
+ *
+ * 
+ * MODIFICATION HISTORY:
+ *
+ * Ver	Who   Date     Changes
+ * ---- ----- -------- ----------------------------------------------------
+ * 1.0  aad   04/12/16 Initial release.
+ *
+ *****************************************************************************/
+
+
+#ifndef XDPDMA_H_
+/* Prevent circular inclusions by using protection macros. */
+#define XDPDMA_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files **********************************/
+
+#include "xdpdma_hw.h"
+#include "xvidc.h"
+#include "xil_io.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xavbuf.h"
+/************************** Constant Definitions ******************************/
+
+/* Alignment for DPDMA Descriptor and Payload */
+#define XDPDMA_DESCRIPTOR_ALIGN 256
+/* DPDMA preamble field */
+#define XDPDMA_DESCRIPTOR_PREAMBLE 0xA5
+/**************************** Type Definitions ********************************/
+
+/**
+ *  This typedef describes the DPDMA descriptor structure and its internals
+ *  which will be used when fetching data from a nonlive path
+ */
+typedef struct {
+	u32 Control;			/**<	[7:0] Descriptor Preamble
+						[8] Enable completion Interrupt
+						[9] Enable descriptor update
+						[10] Ignore Done
+						[11] AXI burst type
+						[15:12] AXACHE
+						[17:16] AXPROT
+						[18] Descriptor mode
+						[19] Last Descriptor
+						[20] Enable CRC
+						[21] Last descriptor frame
+						[31:22] Reserved */
+	u32 DSCR_ID;			/**<	[15:0] Descriptor ID
+						[31:16] Reserved */
+	u32 XFER_SIZE;			/**<	Size of transfer in bytes */
+	u32 LINE_SIZE_STRIDE;		/**<	[17:0] Horizontal Resolution
+						[31:18] Stride */
+	u32 LSB_Timestamp;		/**<	LSB of the Timestamp */
+	u32 MSB_Timestamp;		/**<	MSB of the Timestamp */
+	u32 ADDR_EXT;			/**<	[15:0] Next descriptor
+						extenstion
+						[31:16] SRC address extemsion */
+	u32 NEXT_DESR;			/**<	Address of next descriptor */
+	u32 SRC_ADDR;			/**<	Source Address */
+	u32 ADDR_EXT_23;		/**<	[15:0] Address extension for SRC
+						Address2
+						[31:16] Address extension for
+						SRC Address 3 */
+	u32 ADDR_EXT_45;		/**<	[15:0] Address extension for SRC
+						Address4
+						[31:16] Address extension for
+						SRC Address 5 */
+	u32 SRC_ADDR2;			/**<	Source address of 2nd page */
+	u32 SRC_ADDR3;			/**<	Source address of 3rd page */
+	u32 SRC_ADDR4;			/**<	Source address of 4th page */
+	u32 SRC_ADDR5;			/**<	Source address of 5th page */
+	u32 CRC;			/**<	Reserved */
+
+} XDpDma_Descriptor __attribute__ ((aligned(XDPDMA_DESCRIPTOR_ALIGN)));
+
+/**
+ * This typedef contains configuration information for the DPDMA.
+ */
+typedef struct {
+	u16 DeviceId;			/**< Device ID */
+	u32 BaseAddr;			/**< Base Address */
+} XDpDma_Config;
+
+/**
+ * The following data structure enumerates the types of
+ * DPDMA channels
+ */
+typedef enum {
+	VideoChan,
+	GraphicsChan,
+	AudioChan0,
+	AudioChan1,
+} XDpDma_ChannelType;
+
+/**
+ * This typedef lists the channel status.
+ */
+typedef enum {
+	XDPDMA_DISABLE,
+	XDPDMA_ENABLE,
+	XDPDMA_IDLE,
+	XDPDMA_PAUSE
+} XDpDma_ChannelState;
+
+/**
+ * This typedef is the information needed to transfer video info.
+ */
+typedef struct {
+	u64 Address;
+	u32 Size;
+	u32 Stride;
+	u32 LineSize;
+} XDpDma_FrameBuffer;
+/**
+ * This typedef is the information needed to transfer audio info.
+ */
+typedef struct {
+	u64 Address;
+	u64 Size;
+} XDpDma_AudioBuffer;
+
+/**
+ * This typedef defines the Video/Graphics Channel attributes.
+ */
+typedef struct {
+	XDpDma_Descriptor Descriptor0;
+	XDpDma_Descriptor Descriptor1;
+	XDpDma_Descriptor *Current;
+} XDpDma_Channel;
+
+/**
+ * This typedef defines the Video Channel attributes.
+ */
+typedef struct {
+	XDpDma_Channel Channel[3];
+	u8 TriggerStatus;
+	u8 AVBufEn;
+	XAVBuf_VideoAttribute *VideoInfo;
+	XDpDma_FrameBuffer *FrameBuffer[3];
+} XDpDma_VideoChannel;
+
+/**
+ * This typedef defines the Graphics Channel attributes.
+ */
+typedef struct {
+	XDpDma_Channel Channel;
+	u8 TriggerStatus;
+	u8 AVBufEn;
+	XAVBuf_VideoAttribute *VideoInfo;
+	XDpDma_FrameBuffer *FrameBuffer;
+} XDpDma_GfxChannel;
+
+/**
+ * This typedef defines the Audio Channel attributes.
+ */
+typedef struct {
+	XDpDma_Descriptor Descriptor0, Descriptor1, Descriptor2;
+	XDpDma_Descriptor Descriptor3, Descriptor4, Descriptor5;
+	XDpDma_Descriptor Descriptor6, Descriptor7;
+	XDpDma_Descriptor *Current;
+	u8 TriggerStatus;
+	XDpDma_AudioBuffer *Buffer;
+	u8 Used;
+} XDpDma_AudioChannel;
+/*************************************************************************/
+/**
+ * This callback type represents the handler for a DPDMA VSync interrupt.
+ *
+ * @param	InstancePtr is a pointer to the XDpDma instance.
+ *
+ * @note	None.
+ *
+**************************************************************************/
+typedef void (*XDpDma_VSyncInterruptHandler)(void *InstancePtr);
+
+/*************************************************************************/
+/**
+ * This callback type represents the handler for a DPDMA Done interrupt.
+ *
+ * @param	InstancePtr is a pointer to the XDpDma instance.
+ *
+ * @note	None.
+ *
+**************************************************************************/
+typedef void (*XDpDma_DoneInterruptHandler)(void *InstancePtr);
+
+/**
+ * The XDpDma driver instance data representing the DPDMA operation.
+ */
+typedef struct {
+	XDpDma_Config Config;
+	XDpDma_VideoChannel Video;
+	XDpDma_GfxChannel Gfx;
+	XDpDma_AudioChannel Audio[2];
+	XVidC_VideoTiming *Timing;
+	u8 QOS;
+
+	XDpDma_VSyncInterruptHandler VSyncHandler;
+	void * VSyncInterruptHandler;
+
+	XDpDma_DoneInterruptHandler DoneHandler;
+	void * DoneInterruptHandler;
+
+} XDpDma;
+
+void XDpDma_CfgInitialize(XDpDma *InstancePtr, XDpDma_Config *CfgPtr);
+XDpDma_Config *XDpDma_LookupConfig(u16 DeviceId);
+int XDpDma_SetChannelState(XDpDma *InstancePtr, XDpDma_ChannelType Channel,
+					XDpDma_ChannelState ChannelState);
+void XDpDma_SetQOS(XDpDma *InstancePtr, u8 QOS);
+void XDpDma_SetupChannel(XDpDma *InstancePtr, XDpDma_ChannelType Channel);
+int XDpDma_SetVideoFormat(XDpDma *InstancePtr, XAVBuf_VideoFormat Format);
+int XDpDma_SetGraphicsFormat(XDpDma *InstancePtr, XAVBuf_VideoFormat Format);
+void XDpDma_SetVideoTiming(XDpDma *InstancePtr, XVidC_VideoTiming *Timing);
+int XDpDma_Trigger(XDpDma *InstancePtr, XDpDma_ChannelType Channel);
+int XDpDma_ReTrigger(XDpDma *InstancePtr, XDpDma_ChannelType Channel);
+void XDpDma_InterruptEnable(XDpDma *InstancePtr, u32 Mask);
+void XDpDma_InterruptHandler(XDpDma *InstancePtr);
+void XDpDma_VSyncHandler(XDpDma *InstancePtr);
+void XDpDma_DoneHandler(XDpDma *InstancePtr);
+void XDpDma_InitVideoDescriptor(XDpDma_Descriptor *CurrDesc,
+				XDpDma_FrameBuffer *FrameBuffer);
+void  XDpDma_DisplayVideoFrameBuffer(XDpDma *InstancePtr,
+				   XDpDma_FrameBuffer *Plane1,
+				   XDpDma_FrameBuffer *Plane2,
+				   XDpDma_FrameBuffer *Plane3);
+void XDpDma_DisplayGfxFrameBuffer(XDpDma *InstancePtr,
+				   XDpDma_FrameBuffer *Plane);
+void XDpDma_InitAudioDescriptor(XDpDma_AudioChannel *Channel,
+			       XDpDma_AudioBuffer *AudioBuffer);
+int XDpDma_PlayAudio(XDpDma *InstancePtr, XDpDma_AudioBuffer *Buffer,
+		      u8 ChannelNum);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _XDPDMA_H_ */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/dpdma_v1_0/src/xdpdma_g.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/dpdma_v1_0/src/xdpdma_g.c
new file mode 100644
index 000000000..5bedc6c8b
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/dpdma_v1_0/src/xdpdma_g.c
@@ -0,0 +1,55 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xdpdma.h"
+
+/*
+* The configuration table for devices
+*/
+
+XDpDma_Config XDpDma_ConfigTable[XPAR_XDPDMA_NUM_INSTANCES] =
+{
+	{
+		XPAR_PSU_DPDMA_DEVICE_ID,
+		XPAR_PSU_DPDMA_BASEADDR
+	}
+};
+
+
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/dpdma_v1_0/src/xdpdma_hw.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/dpdma_v1_0/src/xdpdma_hw.h
new file mode 100644
index 000000000..14ebce221
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/dpdma_v1_0/src/xdpdma_hw.h
@@ -0,0 +1,1811 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * Use of the Software is limited solely to applications:
+ * (a) running on a Xilinx device, or
+ * (b) that interact with a Xilinx device through a bus or interconnect.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+ * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ *
+ * Except as contained in this notice, the name of the Xilinx shall not be used
+ * in advertising or otherwise to promote the sale, use or other dealings in
+ * this Software without prior written authorization from Xilinx.
+ *
+ ******************************************************************************/
+
+/*****************************************************************************/
+/**
+ *
+ * @file xdpdma_hw.h
+ *
+ * This header file contains identifiers and low-level driver functions (or
+ * macros) that can be used to access the device. High-level driver functions
+ * are defined in xdpdma.h
+ *
+ * @note	None.
+ *
+ * 
+ * MODIFICATION HISTORY:
+ *
+ * Ver	Who   Date     Changes
+ * ---- ----- -------- ----------------------------------------------------
+ * 1.0  aad   04/12/16 Initial release.
+ *
+ *****************************************************************************/
+
+
+#ifndef XDPDMAHW_H_
+/* Prevent circular inclusions by using protection macros. */
+#define XDPDMAHW_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files **********************************/
+
+#include "xil_io.h"
+
+/************************** Constant Definitions ******************************/
+
+/******************************************************************************/
+/**
+ * Address mapping for the DPDMA.
+ */
+/******************************************************************************/
+/** @name DPDMA registers
+ *  @{
+ */
+
+#define XDPDMA_BASEADDR					0XFD4C0000
+
+/**
+ * Register: XDPDMA_ERR_CTRL
+ */
+#define XDPDMA_ERR_CTRL					0X0000
+
+#define XDPDMA_ERR_CTRL_APB_ERR_RES_SHIFT		0
+#define XDPDMA_ERR_CTRL_APB_ERR_RES_WIDTH		1
+#define XDPDMA_ERR_CTRL_APB_ERR_RES_MASK		0X1
+
+/**
+ * Register: XDPDMA_ISR
+ */
+#define XDPDMA_ISR					0X0004
+
+#define XDPDMA_ISR_VSYNC_INT_SHIFT			27
+#define XDPDMA_ISR_VSYNC_INT_WIDTH			1
+#define XDPDMA_ISR_VSYNC_INT_MASK			0X08000000
+
+#define XDPDMA_ISR_AXI_RD_4K_CROSS_SHIFT		26
+#define XDPDMA_ISR_AXI_RD_4K_CROSS_WIDTH		1
+#define XDPDMA_ISR_AXI_RD_4K_CROSS_MASK			0X04000000
+
+#define XDPDMA_ISR_WR_DATA_FIFO_FULL_SHIFT		25
+#define XDPDMA_ISR_WR_DATA_FIFO_FULL_WIDTH		1
+#define XDPDMA_ISR_WR_DATA_FIFO_FULL_MASK		0X02000000
+
+#define XDPDMA_ISR_WR_CMD_FIFO_FULL_SHIFT		24
+#define XDPDMA_ISR_WR_CMD_FIFO_FULL_WIDTH		1
+#define XDPDMA_ISR_WR_CMD_FIFO_FULL_MASK		0X01000000
+
+#define XDPDMA_ISR_DSCR_ERR5_SHIFT			23
+#define XDPDMA_ISR_DSCR_ERR5_WIDTH			1
+#define XDPDMA_ISR_DSCR_ERR5_MASK			0X800000
+
+#define XDPDMA_ISR_DSCR_ERR4_SHIFT			22
+#define XDPDMA_ISR_DSCR_ERR4_WIDTH			1
+#define XDPDMA_ISR_DSCR_ERR4_MASK			0X400000
+
+#define XDPDMA_ISR_DSCR_ERR3_SHIFT			21
+#define XDPDMA_ISR_DSCR_ERR3_WIDTH			1
+#define XDPDMA_ISR_DSCR_ERR3_MASK			0X200000
+
+#define XDPDMA_ISR_DSCR_ERR2_SHIFT			20
+#define XDPDMA_ISR_DSCR_ERR2_WIDTH			1
+#define XDPDMA_ISR_DSCR_ERR2_MASK			0X100000
+
+#define XDPDMA_ISR_DSCR_ERR1_SHIFT			19
+#define XDPDMA_ISR_DSCR_ERR1_WIDTH			1
+#define XDPDMA_ISR_DSCR_ERR1_MASK			0X80000
+
+#define XDPDMA_ISR_DSCR_ERR0_SHIFT			18
+#define XDPDMA_ISR_DSCR_ERR0_WIDTH			1
+#define XDPDMA_ISR_DSCR_ERR0_MASK			0X40000
+
+#define XDPDMA_ISR_DATA_AXI_ERR5_SHIFT			17
+#define XDPDMA_ISR_DATA_AXI_ERR5_WIDTH			1
+#define XDPDMA_ISR_DATA_AXI_ERR5_MASK			0X20000
+
+#define XDPDMA_ISR_DATA_AXI_ERR4_SHIFT			16
+#define XDPDMA_ISR_DATA_AXI_ERR4_WIDTH			1
+#define XDPDMA_ISR_DATA_AXI_ERR4_MASK			0X10000
+
+#define XDPDMA_ISR_DATA_AXI_ERR3_SHIFT			15
+#define XDPDMA_ISR_DATA_AXI_ERR3_WIDTH			1
+#define XDPDMA_ISR_DATA_AXI_ERR3_MASK			0X8000
+
+#define XDPDMA_ISR_DATA_AXI_ERR2_SHIFT			14
+#define XDPDMA_ISR_DATA_AXI_ERR2_WIDTH			1
+#define XDPDMA_ISR_DATA_AXI_ERR2_MASK			0X4000
+
+#define XDPDMA_ISR_DATA_AXI_ERR1_SHIFT			13
+#define XDPDMA_ISR_DATA_AXI_ERR1_WIDTH			1
+#define XDPDMA_ISR_DATA_AXI_ERR1_MASK			0X2000
+
+#define XDPDMA_ISR_DATA_AXI_ERR0_SHIFT			12
+#define XDPDMA_ISR_DATA_AXI_ERR0_WIDTH			1
+#define XDPDMA_ISR_DATA_AXI_ERR0_MASK			0X1000
+
+#define XDPDMA_ISR_NO_OSTAND_TRAN5_SHIFT		11
+#define XDPDMA_ISR_NO_OSTAND_TRAN5_WIDTH		1
+#define XDPDMA_ISR_NO_OSTAND_TRAN5_MASK			0X0800
+
+#define XDPDMA_ISR_NO_OSTAND_TRAN4_SHIFT		10
+#define XDPDMA_ISR_NO_OSTAND_TRAN4_WIDTH		1
+#define XDPDMA_ISR_NO_OSTAND_TRAN4_MASK			0X0400
+
+#define XDPDMA_ISR_NO_OSTAND_TRAN3_SHIFT		9
+#define XDPDMA_ISR_NO_OSTAND_TRAN3_WIDTH		1
+#define XDPDMA_ISR_NO_OSTAND_TRAN3_MASK			0X0200
+
+#define XDPDMA_ISR_NO_OSTAND_TRAN2_SHIFT		8
+#define XDPDMA_ISR_NO_OSTAND_TRAN2_WIDTH		1
+#define XDPDMA_ISR_NO_OSTAND_TRAN2_MASK			0X0100
+
+#define XDPDMA_ISR_NO_OSTAND_TRAN1_SHIFT		7
+#define XDPDMA_ISR_NO_OSTAND_TRAN1_WIDTH		1
+#define XDPDMA_ISR_NO_OSTAND_TRAN1_MASK			0X80
+
+#define XDPDMA_ISR_NO_OSTAND_TRAN0_SHIFT		6
+#define XDPDMA_ISR_NO_OSTAND_TRAN0_WIDTH		1
+#define XDPDMA_ISR_NO_OSTAND_TRAN0_MASK			0X40
+
+#define XDPDMA_ISR_DSCR_DONE5_SHIFT			5
+#define XDPDMA_ISR_DSCR_DONE5_WIDTH			1
+#define XDPDMA_ISR_DSCR_DONE5_MASK			0X20
+
+#define XDPDMA_ISR_DSCR_DONE4_SHIFT			4
+#define XDPDMA_ISR_DSCR_DONE4_WIDTH			1
+#define XDPDMA_ISR_DSCR_DONE4_MASK			0X10
+
+#define XDPDMA_ISR_DSCR_DONE3_SHIFT			3
+#define XDPDMA_ISR_DSCR_DONE3_WIDTH			1
+#define XDPDMA_ISR_DSCR_DONE3_MASK			0X8
+
+#define XDPDMA_ISR_DSCR_DONE2_SHIFT			2
+#define XDPDMA_ISR_DSCR_DONE2_WIDTH			1
+#define XDPDMA_ISR_DSCR_DONE2_MASK			0X4
+
+#define XDPDMA_ISR_DSCR_DONE1_SHIFT			1
+#define XDPDMA_ISR_DSCR_DONE1_WIDTH			1
+#define XDPDMA_ISR_DSCR_DONE1_MASK			0X2
+
+#define XDPDMA_ISR_DSCR_DONE0_SHIFT			0
+#define XDPDMA_ISR_DSCR_DONE0_WIDTH			1
+#define XDPDMA_ISR_DSCR_DONE0_MASK			0X1
+
+/**
+ * Register: XDPDMA_IMR
+ */
+#define XDPDMA_IMR					0X0008
+
+#define XDPDMA_IMR_VSYNC_INT_SHIFT			27
+#define XDPDMA_IMR_VSYNC_INT_WIDTH			1
+#define XDPDMA_IMR_VSYNC_INT_MASK			0X08000000
+
+#define XDPDMA_IMR_AXI_RD_4K_CROSS_SHIFT		26
+#define XDPDMA_IMR_AXI_RD_4K_CROSS_WIDTH		1
+#define XDPDMA_IMR_AXI_RD_4K_CROSS_MASK			0X04000000
+
+#define XDPDMA_IMR_WR_DATA_FIFO_FULL_SHIFT		25
+#define XDPDMA_IMR_WR_DATA_FIFO_FULL_WIDTH		1
+#define XDPDMA_IMR_WR_DATA_FIFO_FULL_MASK		0X02000000
+
+#define XDPDMA_IMR_WR_CMD_FIFO_FULL_SHIFT		24
+#define XDPDMA_IMR_WR_CMD_FIFO_FULL_WIDTH		1
+#define XDPDMA_IMR_WR_CMD_FIFO_FULL_MASK		0X01000000
+
+#define XDPDMA_IMR_DSCR_ERR5_SHIFT			23
+#define XDPDMA_IMR_DSCR_ERR5_WIDTH			1
+#define XDPDMA_IMR_DSCR_ERR5_MASK			0X800000
+
+#define XDPDMA_IMR_DSCR_ERR4_SHIFT			22
+#define XDPDMA_IMR_DSCR_ERR4_WIDTH			1
+#define XDPDMA_IMR_DSCR_ERR4_MASK			0X400000
+
+#define XDPDMA_IMR_DSCR_ERR3_SHIFT			21
+#define XDPDMA_IMR_DSCR_ERR3_WIDTH			1
+#define XDPDMA_IMR_DSCR_ERR3_MASK			0X200000
+
+#define XDPDMA_IMR_DSCR_ERR2_SHIFT			20
+#define XDPDMA_IMR_DSCR_ERR2_WIDTH			1
+#define XDPDMA_IMR_DSCR_ERR2_MASK			0X100000
+
+#define XDPDMA_IMR_DSCR_ERR1_SHIFT			19
+#define XDPDMA_IMR_DSCR_ERR1_WIDTH			1
+#define XDPDMA_IMR_DSCR_ERR1_MASK			0X80000
+
+#define XDPDMA_IMR_DSCR_ERR0_SHIFT			18
+#define XDPDMA_IMR_DSCR_ERR0_WIDTH			1
+#define XDPDMA_IMR_DSCR_ERR0_MASK			0X40000
+
+#define XDPDMA_IMR_DATA_AXI_ERR5_SHIFT			17
+#define XDPDMA_IMR_DATA_AXI_ERR5_WIDTH			1
+#define XDPDMA_IMR_DATA_AXI_ERR5_MASK			0X20000
+
+#define XDPDMA_IMR_DATA_AXI_ERR4_SHIFT			16
+#define XDPDMA_IMR_DATA_AXI_ERR4_WIDTH			1
+#define XDPDMA_IMR_DATA_AXI_ERR4_MASK			0X10000
+
+#define XDPDMA_IMR_DATA_AXI_ERR3_SHIFT			15
+#define XDPDMA_IMR_DATA_AXI_ERR3_WIDTH			1
+#define XDPDMA_IMR_DATA_AXI_ERR3_MASK			0X8000
+
+#define XDPDMA_IMR_DATA_AXI_ERR2_SHIFT			14
+#define XDPDMA_IMR_DATA_AXI_ERR2_WIDTH			1
+#define XDPDMA_IMR_DATA_AXI_ERR2_MASK			0X4000
+
+#define XDPDMA_IMR_DATA_AXI_ERR1_SHIFT			13
+#define XDPDMA_IMR_DATA_AXI_ERR1_WIDTH			1
+#define XDPDMA_IMR_DATA_AXI_ERR1_MASK			0X2000
+
+#define XDPDMA_IMR_DATA_AXI_ERR0_SHIFT			12
+#define XDPDMA_IMR_DATA_AXI_ERR0_WIDTH			1
+#define XDPDMA_IMR_DATA_AXI_ERR0_MASK			0X1000
+
+#define XDPDMA_IMR_NO_OSTAND_TRAN5_SHIFT		11
+#define XDPDMA_IMR_NO_OSTAND_TRAN5_WIDTH		1
+#define XDPDMA_IMR_NO_OSTAND_TRAN5_MASK			0X0800
+
+#define XDPDMA_IMR_NO_OSTAND_TRAN4_SHIFT		10
+#define XDPDMA_IMR_NO_OSTAND_TRAN4_WIDTH		1
+#define XDPDMA_IMR_NO_OSTAND_TRAN4_MASK			0X0400
+
+#define XDPDMA_IMR_NO_OSTAND_TRAN3_SHIFT		9
+#define XDPDMA_IMR_NO_OSTAND_TRAN3_WIDTH		1
+#define XDPDMA_IMR_NO_OSTAND_TRAN3_MASK			0X0200
+
+#define XDPDMA_IMR_NO_OSTAND_TRAN2_SHIFT		8
+#define XDPDMA_IMR_NO_OSTAND_TRAN2_WIDTH		1
+#define XDPDMA_IMR_NO_OSTAND_TRAN2_MASK			0X0100
+
+#define XDPDMA_IMR_NO_OSTAND_TRAN1_SHIFT		7
+#define XDPDMA_IMR_NO_OSTAND_TRAN1_WIDTH		1
+#define XDPDMA_IMR_NO_OSTAND_TRAN1_MASK			0X80
+
+#define XDPDMA_IMR_NO_OSTAND_TRAN0_SHIFT		6
+#define XDPDMA_IMR_NO_OSTAND_TRAN0_WIDTH		1
+#define XDPDMA_IMR_NO_OSTAND_TRAN0_MASK			0X40
+
+#define XDPDMA_IMR_DSCR_DONE5_SHIFT			5
+#define XDPDMA_IMR_DSCR_DONE5_WIDTH			1
+#define XDPDMA_IMR_DSCR_DONE5_MASK			0X20
+
+#define XDPDMA_IMR_DSCR_DONE4_SHIFT			4
+#define XDPDMA_IMR_DSCR_DONE4_WIDTH			1
+#define XDPDMA_IMR_DSCR_DONE4_MASK			0X10
+
+#define XDPDMA_IMR_DSCR_DONE3_SHIFT			3
+#define XDPDMA_IMR_DSCR_DONE3_WIDTH			1
+#define XDPDMA_IMR_DSCR_DONE3_MASK			0X8
+
+#define XDPDMA_IMR_DSCR_DONE2_SHIFT			2
+#define XDPDMA_IMR_DSCR_DONE2_WIDTH			1
+#define XDPDMA_IMR_DSCR_DONE2_MASK			0X4
+
+#define XDPDMA_IMR_DSCR_DONE1_SHIFT			1
+#define XDPDMA_IMR_DSCR_DONE1_WIDTH			1
+#define XDPDMA_IMR_DSCR_DONE1_MASK			0X2
+
+#define XDPDMA_IMR_DSCR_DONE0_SHIFT			0
+#define XDPDMA_IMR_DSCR_DONE0_WIDTH			1
+#define XDPDMA_IMR_DSCR_DONE0_MASK			0X1
+
+/**
+ * Register: XDPDMA_IEN
+ */
+#define XDPDMA_IEN					0X000C
+
+#define XDPDMA_IEN_VSYNC_INT_SHIFT			27
+#define XDPDMA_IEN_VSYNC_INT_WIDTH			1
+#define XDPDMA_IEN_VSYNC_INT_MASK			0X08000000
+
+#define XDPDMA_IEN_AXI_RD_4K_CROSS_SHIFT		26
+#define XDPDMA_IEN_AXI_RD_4K_CROSS_WIDTH		1
+#define XDPDMA_IEN_AXI_RD_4K_CROSS_MASK			0X04000000
+
+#define XDPDMA_IEN_WR_DATA_FIFO_FULL_SHIFT		25
+#define XDPDMA_IEN_WR_DATA_FIFO_FULL_WIDTH		1
+#define XDPDMA_IEN_WR_DATA_FIFO_FULL_MASK		0X02000000
+
+#define XDPDMA_IEN_WR_CMD_FIFO_FULL_SHIFT		24
+#define XDPDMA_IEN_WR_CMD_FIFO_FULL_WIDTH		1
+#define XDPDMA_IEN_WR_CMD_FIFO_FULL_MASK		0X01000000
+
+#define XDPDMA_IEN_DSCR_ERR5_SHIFT			23
+#define XDPDMA_IEN_DSCR_ERR5_WIDTH			1
+#define XDPDMA_IEN_DSCR_ERR5_MASK			0X800000
+
+#define XDPDMA_IEN_DSCR_ERR4_SHIFT			22
+#define XDPDMA_IEN_DSCR_ERR4_WIDTH			1
+#define XDPDMA_IEN_DSCR_ERR4_MASK			0X400000
+
+#define XDPDMA_IEN_DSCR_ERR3_SHIFT			21
+#define XDPDMA_IEN_DSCR_ERR3_WIDTH			1
+#define XDPDMA_IEN_DSCR_ERR3_MASK			0X200000
+
+#define XDPDMA_IEN_DSCR_ERR2_SHIFT			20
+#define XDPDMA_IEN_DSCR_ERR2_WIDTH			1
+#define XDPDMA_IEN_DSCR_ERR2_MASK			0X100000
+
+#define XDPDMA_IEN_DSCR_ERR1_SHIFT			19
+#define XDPDMA_IEN_DSCR_ERR1_WIDTH			1
+#define XDPDMA_IEN_DSCR_ERR1_MASK			0X80000
+
+#define XDPDMA_IEN_DSCR_ERR0_SHIFT			18
+#define XDPDMA_IEN_DSCR_ERR0_WIDTH			1
+#define XDPDMA_IEN_DSCR_ERR0_MASK			0X40000
+
+#define XDPDMA_IEN_DATA_AXI_ERR5_SHIFT			17
+#define XDPDMA_IEN_DATA_AXI_ERR5_WIDTH			1
+#define XDPDMA_IEN_DATA_AXI_ERR5_MASK			0X20000
+
+#define XDPDMA_IEN_DATA_AXI_ERR4_SHIFT			16
+#define XDPDMA_IEN_DATA_AXI_ERR4_WIDTH			1
+#define XDPDMA_IEN_DATA_AXI_ERR4_MASK			0X10000
+
+#define XDPDMA_IEN_DATA_AXI_ERR3_SHIFT			15
+#define XDPDMA_IEN_DATA_AXI_ERR3_WIDTH			1
+#define XDPDMA_IEN_DATA_AXI_ERR3_MASK			0X8000
+
+#define XDPDMA_IEN_DATA_AXI_ERR2_SHIFT			14
+#define XDPDMA_IEN_DATA_AXI_ERR2_WIDTH			1
+#define XDPDMA_IEN_DATA_AXI_ERR2_MASK			0X4000
+
+#define XDPDMA_IEN_DATA_AXI_ERR1_SHIFT			13
+#define XDPDMA_IEN_DATA_AXI_ERR1_WIDTH			1
+#define XDPDMA_IEN_DATA_AXI_ERR1_MASK			0X2000
+
+#define XDPDMA_IEN_DATA_AXI_ERR0_SHIFT			12
+#define XDPDMA_IEN_DATA_AXI_ERR0_WIDTH			1
+#define XDPDMA_IEN_DATA_AXI_ERR0_MASK			0X1000
+
+#define XDPDMA_IEN_NO_OSTAND_TRAN5_SHIFT		11
+#define XDPDMA_IEN_NO_OSTAND_TRAN5_WIDTH		1
+#define XDPDMA_IEN_NO_OSTAND_TRAN5_MASK			0X0800
+
+#define XDPDMA_IEN_NO_OSTAND_TRAN4_SHIFT		10
+#define XDPDMA_IEN_NO_OSTAND_TRAN4_WIDTH		1
+#define XDPDMA_IEN_NO_OSTAND_TRAN4_MASK			0X0400
+
+#define XDPDMA_IEN_NO_OSTAND_TRAN3_SHIFT		9
+#define XDPDMA_IEN_NO_OSTAND_TRAN3_WIDTH		1
+#define XDPDMA_IEN_NO_OSTAND_TRAN3_MASK			0X0200
+
+#define XDPDMA_IEN_NO_OSTAND_TRAN2_SHIFT		8
+#define XDPDMA_IEN_NO_OSTAND_TRAN2_WIDTH		1
+#define XDPDMA_IEN_NO_OSTAND_TRAN2_MASK			0X0100
+
+#define XDPDMA_IEN_NO_OSTAND_TRAN1_SHIFT		7
+#define XDPDMA_IEN_NO_OSTAND_TRAN1_WIDTH		1
+#define XDPDMA_IEN_NO_OSTAND_TRAN1_MASK			0X80
+
+#define XDPDMA_IEN_NO_OSTAND_TRAN0_SHIFT		6
+#define XDPDMA_IEN_NO_OSTAND_TRAN0_WIDTH		1
+#define XDPDMA_IEN_NO_OSTAND_TRAN0_MASK			0X40
+
+#define XDPDMA_IEN_DSCR_DONE5_SHIFT			5
+#define XDPDMA_IEN_DSCR_DONE5_WIDTH			1
+#define XDPDMA_IEN_DSCR_DONE5_MASK			0X20
+
+#define XDPDMA_IEN_DSCR_DONE4_SHIFT			4
+#define XDPDMA_IEN_DSCR_DONE4_WIDTH			1
+#define XDPDMA_IEN_DSCR_DONE4_MASK			0X10
+
+#define XDPDMA_IEN_DSCR_DONE3_SHIFT			3
+#define XDPDMA_IEN_DSCR_DONE3_WIDTH			1
+#define XDPDMA_IEN_DSCR_DONE3_MASK			0X8
+
+#define XDPDMA_IEN_DSCR_DONE2_SHIFT			2
+#define XDPDMA_IEN_DSCR_DONE2_WIDTH			1
+#define XDPDMA_IEN_DSCR_DONE2_MASK			0X4
+
+#define XDPDMA_IEN_DSCR_DONE1_SHIFT			1
+#define XDPDMA_IEN_DSCR_DONE1_WIDTH			1
+#define XDPDMA_IEN_DSCR_DONE1_MASK			0X2
+
+#define XDPDMA_IEN_DSCR_DONE0_SHIFT			0
+#define XDPDMA_IEN_DSCR_DONE0_WIDTH			1
+#define XDPDMA_IEN_DSCR_DONE0_MASK			0X1
+
+/**
+ * Register: XDPDMA_IDS
+ */
+#define XDPDMA_IDS					0X0010
+
+#define XDPDMA_IDS_VSYNC_INT_SHIFT			27
+#define XDPDMA_IDS_VSYNC_INT_WIDTH			1
+#define XDPDMA_IDS_VSYNC_INT_MASK			0X08000000
+
+#define XDPDMA_IDS_AXI_RD_4K_CROSS_SHIFT		26
+#define XDPDMA_IDS_AXI_RD_4K_CROSS_WIDTH		1
+#define XDPDMA_IDS_AXI_RD_4K_CROSS_MASK		0X04000000
+
+#define XDPDMA_IDS_WR_DATA_FIFO_FULL_SHIFT		25
+#define XDPDMA_IDS_WR_DATA_FIFO_FULL_WIDTH		1
+#define XDPDMA_IDS_WR_DATA_FIFO_FULL_MASK		0X02000000
+
+#define XDPDMA_IDS_WR_CMD_FIFO_FULL_SHIFT		24
+#define XDPDMA_IDS_WR_CMD_FIFO_FULL_WIDTH		1
+#define XDPDMA_IDS_WR_CMD_FIFO_FULL_MASK		0X01000000
+
+#define XDPDMA_IDS_DSCR_ERR5_SHIFT			23
+#define XDPDMA_IDS_DSCR_ERR5_WIDTH			1
+#define XDPDMA_IDS_DSCR_ERR5_MASK			0X800000
+
+#define XDPDMA_IDS_DSCR_ERR4_SHIFT			22
+#define XDPDMA_IDS_DSCR_ERR4_WIDTH			1
+#define XDPDMA_IDS_DSCR_ERR4_MASK			0X400000
+
+#define XDPDMA_IDS_DSCR_ERR3_SHIFT			21
+#define XDPDMA_IDS_DSCR_ERR3_WIDTH			1
+#define XDPDMA_IDS_DSCR_ERR3_MASK			0X200000
+
+#define XDPDMA_IDS_DSCR_ERR2_SHIFT			20
+#define XDPDMA_IDS_DSCR_ERR2_WIDTH			1
+#define XDPDMA_IDS_DSCR_ERR2_MASK			0X100000
+
+#define XDPDMA_IDS_DSCR_ERR1_SHIFT			19
+#define XDPDMA_IDS_DSCR_ERR1_WIDTH			1
+#define XDPDMA_IDS_DSCR_ERR1_MASK			0X80000
+
+#define XDPDMA_IDS_DSCR_ERR0_SHIFT			18
+#define XDPDMA_IDS_DSCR_ERR0_WIDTH			1
+#define XDPDMA_IDS_DSCR_ERR0_MASK			0X40000
+
+#define XDPDMA_IDS_DATA_AXI_ERR5_SHIFT			17
+#define XDPDMA_IDS_DATA_AXI_ERR5_WIDTH			1
+#define XDPDMA_IDS_DATA_AXI_ERR5_MASK			0X20000
+
+#define XDPDMA_IDS_DATA_AXI_ERR4_SHIFT			16
+#define XDPDMA_IDS_DATA_AXI_ERR4_WIDTH			1
+#define XDPDMA_IDS_DATA_AXI_ERR4_MASK			0X10000
+
+#define XDPDMA_IDS_DATA_AXI_ERR3_SHIFT			15
+#define XDPDMA_IDS_DATA_AXI_ERR3_WIDTH			1
+#define XDPDMA_IDS_DATA_AXI_ERR3_MASK			0X8000
+
+#define XDPDMA_IDS_DATA_AXI_ERR2_SHIFT			14
+#define XDPDMA_IDS_DATA_AXI_ERR2_WIDTH			1
+#define XDPDMA_IDS_DATA_AXI_ERR2_MASK			0X4000
+
+#define XDPDMA_IDS_DATA_AXI_ERR1_SHIFT			13
+#define XDPDMA_IDS_DATA_AXI_ERR1_WIDTH			1
+#define XDPDMA_IDS_DATA_AXI_ERR1_MASK			0X2000
+
+#define XDPDMA_IDS_DATA_AXI_ERR0_SHIFT			12
+#define XDPDMA_IDS_DATA_AXI_ERR0_WIDTH			1
+#define XDPDMA_IDS_DATA_AXI_ERR0_MASK			0X1000
+
+#define XDPDMA_IDS_NO_OSTAND_TRAN5_SHIFT		11
+#define XDPDMA_IDS_NO_OSTAND_TRAN5_WIDTH		1
+#define XDPDMA_IDS_NO_OSTAND_TRAN5_MASK			0X0800
+
+#define XDPDMA_IDS_NO_OSTAND_TRAN4_SHIFT		10
+#define XDPDMA_IDS_NO_OSTAND_TRAN4_WIDTH		1
+#define XDPDMA_IDS_NO_OSTAND_TRAN4_MASK			0X0400
+
+#define XDPDMA_IDS_NO_OSTAND_TRAN3_SHIFT		9
+#define XDPDMA_IDS_NO_OSTAND_TRAN3_WIDTH		1
+#define XDPDMA_IDS_NO_OSTAND_TRAN3_MASK			0X0200
+
+#define XDPDMA_IDS_NO_OSTAND_TRAN2_SHIFT		8
+#define XDPDMA_IDS_NO_OSTAND_TRAN2_WIDTH		1
+#define XDPDMA_IDS_NO_OSTAND_TRAN2_MASK			0X0100
+
+#define XDPDMA_IDS_NO_OSTAND_TRAN1_SHIFT		7
+#define XDPDMA_IDS_NO_OSTAND_TRAN1_WIDTH		1
+#define XDPDMA_IDS_NO_OSTAND_TRAN1_MASK			0X80
+
+#define XDPDMA_IDS_NO_OSTAND_TRAN0_SHIFT		6
+#define XDPDMA_IDS_NO_OSTAND_TRAN0_WIDTH		1
+#define XDPDMA_IDS_NO_OSTAND_TRAN0_MASK			0X40
+
+#define XDPDMA_IDS_DSCR_DONE5_SHIFT			5
+#define XDPDMA_IDS_DSCR_DONE5_WIDTH			1
+#define XDPDMA_IDS_DSCR_DONE5_MASK			0X20
+
+#define XDPDMA_IDS_DSCR_DONE4_SHIFT			4
+#define XDPDMA_IDS_DSCR_DONE4_WIDTH			1
+#define XDPDMA_IDS_DSCR_DONE4_MASK			0X10
+
+#define XDPDMA_IDS_DSCR_DONE3_SHIFT			3
+#define XDPDMA_IDS_DSCR_DONE3_WIDTH			1
+#define XDPDMA_IDS_DSCR_DONE3_MASK			0X8
+
+#define XDPDMA_IDS_DSCR_DONE2_SHIFT			2
+#define XDPDMA_IDS_DSCR_DONE2_WIDTH			1
+#define XDPDMA_IDS_DSCR_DONE2_MASK			0X4
+
+#define XDPDMA_IDS_DSCR_DONE1_SHIFT			1
+#define XDPDMA_IDS_DSCR_DONE1_WIDTH			1
+#define XDPDMA_IDS_DSCR_DONE1_MASK			0X2
+
+#define XDPDMA_IDS_DSCR_DONE0_SHIFT			0
+#define XDPDMA_IDS_DSCR_DONE0_WIDTH			1
+#define XDPDMA_IDS_DSCR_DONE0_MASK			0X1
+
+/**
+ * Register: XDPDMA_EISR
+ */
+#define XDPDMA_EISR					0X0014
+
+#define XDPDMA_EISR_RD_CMD_FIFO_FULL_SHIFT		31
+#define XDPDMA_EISR_RD_CMD_FIFO_FULL_WIDTH		1
+#define XDPDMA_EISR_RD_CMD_FIFO_FULL_MASK		0X80000000
+
+#define XDPDMA_EISR_DSCR_DONE_ERR5_SHIFT		30
+#define XDPDMA_EISR_DSCR_DONE_ERR5_WIDTH		1
+#define XDPDMA_EISR_DSCR_DONE_ERR5_MASK			0X40000000
+
+#define XDPDMA_EISR_DSCR_DONE_ERR4_SHIFT		29
+#define XDPDMA_EISR_DSCR_DONE_ERR4_WIDTH		1
+#define XDPDMA_EISR_DSCR_DONE_ERR4_MASK			0X20000000
+
+#define XDPDMA_EISR_DSCR_DONE_ERR3_SHIFT		28
+#define XDPDMA_EISR_DSCR_DONE_ERR3_WIDTH		1
+#define XDPDMA_EISR_DSCR_DONE_ERR3_MASK			0X10000000
+
+#define XDPDMA_EISR_DSCR_DONE_ERR2_SHIFT		27
+#define XDPDMA_EISR_DSCR_DONE_ERR2_WIDTH		1
+#define XDPDMA_EISR_DSCR_DONE_ERR2_MASK			0X08000000
+
+#define XDPDMA_EISR_DSCR_DONE_ERR1_SHIFT		26
+#define XDPDMA_EISR_DSCR_DONE_ERR1_WIDTH		1
+#define XDPDMA_EISR_DSCR_DONE_ERR1_MASK			0X04000000
+
+#define XDPDMA_EISR_DSCR_DONE_ERR0_SHIFT		25
+#define XDPDMA_EISR_DSCR_DONE_ERR0_WIDTH		1
+#define XDPDMA_EISR_DSCR_DONE_ERR0_MASK			0X02000000
+
+#define XDPDMA_EISR_DSCR_WR_AXI_ERR5_SHIFT		24
+#define XDPDMA_EISR_DSCR_WR_AXI_ERR5_WIDTH		1
+#define XDPDMA_EISR_DSCR_WR_AXI_ERR5_MASK		0X01000000
+
+#define XDPDMA_EISR_DSCR_WR_AXI_ERR4_SHIFT		23
+#define XDPDMA_EISR_DSCR_WR_AXI_ERR4_WIDTH		1
+#define XDPDMA_EISR_DSCR_WR_AXI_ERR4_MASK		0X800000
+
+#define XDPDMA_EISR_DSCR_WR_AXI_ERR3_SHIFT		22
+#define XDPDMA_EISR_DSCR_WR_AXI_ERR3_WIDTH		1
+#define XDPDMA_EISR_DSCR_WR_AXI_ERR3_MASK		0X400000
+
+#define XDPDMA_EISR_DSCR_WR_AXI_ERR2_SHIFT		21
+#define XDPDMA_EISR_DSCR_WR_AXI_ERR2_WIDTH		1
+#define XDPDMA_EISR_DSCR_WR_AXI_ERR2_MASK		0X200000
+
+#define XDPDMA_EISR_DSCR_WR_AXI_ERR1_SHIFT		20
+#define XDPDMA_EISR_DSCR_WR_AXI_ERR1_WIDTH		1
+#define XDPDMA_EISR_DSCR_WR_AXI_ERR1_MASK		0X100000
+
+#define XDPDMA_EISR_DSCR_WR_AXI_ERR0_SHIFT		19
+#define XDPDMA_EISR_DSCR_WR_AXI_ERR0_WIDTH		1
+#define XDPDMA_EISR_DSCR_WR_AXI_ERR0_MASK		0X80000
+
+#define XDPDMA_EISR_DSCR_CRC_ERR5_SHIFT			18
+#define XDPDMA_EISR_DSCR_CRC_ERR5_WIDTH			1
+#define XDPDMA_EISR_DSCR_CRC_ERR5_MASK			0X40000
+
+#define XDPDMA_EISR_DSCR_CRC_ERR4_SHIFT			17
+#define XDPDMA_EISR_DSCR_CRC_ERR4_WIDTH			1
+#define XDPDMA_EISR_DSCR_CRC_ERR4_MASK			0X20000
+
+#define XDPDMA_EISR_DSCR_CRC_ERR3_SHIFT			16
+#define XDPDMA_EISR_DSCR_CRC_ERR3_WIDTH			1
+#define XDPDMA_EISR_DSCR_CRC_ERR3_MASK			0X10000
+
+#define XDPDMA_EISR_DSCR_CRC_ERR2_SHIFT			15
+#define XDPDMA_EISR_DSCR_CRC_ERR2_WIDTH			1
+#define XDPDMA_EISR_DSCR_CRC_ERR2_MASK			0X8000
+
+#define XDPDMA_EISR_DSCR_CRC_ERR1_SHIFT			14
+#define XDPDMA_EISR_DSCR_CRC_ERR1_WIDTH			1
+#define XDPDMA_EISR_DSCR_CRC_ERR1_MASK			0X4000
+
+#define XDPDMA_EISR_DSCR_CRC_ERR0_SHIFT			13
+#define XDPDMA_EISR_DSCR_CRC_ERR0_WIDTH			1
+#define XDPDMA_EISR_DSCR_CRC_ERR0_MASK			0X2000
+
+#define XDPDMA_EISR_DSCR_PRE_ERR5_SHIFT			12
+#define XDPDMA_EISR_DSCR_PRE_ERR5_WIDTH			1
+#define XDPDMA_EISR_DSCR_PRE_ERR5_MASK			0X1000
+
+#define XDPDMA_EISR_DSCR_PRE_ERR4_SHIFT			11
+#define XDPDMA_EISR_DSCR_PRE_ERR4_WIDTH			1
+#define XDPDMA_EISR_DSCR_PRE_ERR4_MASK			0X0800
+
+#define XDPDMA_EISR_DSCR_PRE_ERR3_SHIFT			10
+#define XDPDMA_EISR_DSCR_PRE_ERR3_WIDTH			1
+#define XDPDMA_EISR_DSCR_PRE_ERR3_MASK			0X0400
+
+#define XDPDMA_EISR_DSCR_PRE_ERR2_SHIFT			9
+#define XDPDMA_EISR_DSCR_PRE_ERR2_WIDTH			1
+#define XDPDMA_EISR_DSCR_PRE_ERR2_MASK			0X0200
+
+#define XDPDMA_EISR_DSCR_PRE_ERR1_SHIFT			8
+#define XDPDMA_EISR_DSCR_PRE_ERR1_WIDTH			1
+#define XDPDMA_EISR_DSCR_PRE_ERR1_MASK			0X0100
+
+#define XDPDMA_EISR_DSCR_PRE_ERR0_SHIFT			7
+#define XDPDMA_EISR_DSCR_PRE_ERR0_WIDTH			1
+#define XDPDMA_EISR_DSCR_PRE_ERR0_MASK			0X80
+
+#define XDPDMA_EISR_DSCR_RD_AXI_ERR5_SHIFT		6
+#define XDPDMA_EISR_DSCR_RD_AXI_ERR5_WIDTH		1
+#define XDPDMA_EISR_DSCR_RD_AXI_ERR5_MASK		0X40
+
+#define XDPDMA_EISR_DSCR_RD_AXI_ERR4_SHIFT		5
+#define XDPDMA_EISR_DSCR_RD_AXI_ERR4_WIDTH		1
+#define XDPDMA_EISR_DSCR_RD_AXI_ERR4_MASK		0X20
+
+#define XDPDMA_EISR_DSCR_RD_AXI_ERR3_SHIFT		4
+#define XDPDMA_EISR_DSCR_RD_AXI_ERR3_WIDTH		1
+#define XDPDMA_EISR_DSCR_RD_AXI_ERR3_MASK		0X10
+
+#define XDPDMA_EISR_DSCR_RD_AXI_ERR2_SHIFT		3
+#define XDPDMA_EISR_DSCR_RD_AXI_ERR2_WIDTH		1
+#define XDPDMA_EISR_DSCR_RD_AXI_ERR2_MASK		0X8
+
+#define XDPDMA_EISR_DSCR_RD_AXI_ERR1_SHIFT		2
+#define XDPDMA_EISR_DSCR_RD_AXI_ERR1_WIDTH		1
+#define XDPDMA_EISR_DSCR_RD_AXI_ERR1_MASK		0X4
+
+#define XDPDMA_EISR_DSCR_RD_AXI_ERR0_SHIFT		1
+#define XDPDMA_EISR_DSCR_RD_AXI_ERR0_WIDTH		1
+#define XDPDMA_EISR_DSCR_RD_AXI_ERR0_MASK		0X2
+
+#define XDPDMA_EISR_INV_APB_SHIFT			0
+#define XDPDMA_EISR_INV_APB_WIDTH			1
+#define XDPDMA_EISR_INV_APB_MASK			0X1
+
+/**
+ * Register: XDPDMA_EIMR
+ */
+#define XDPDMA_EIMR					0X0018
+
+#define XDPDMA_EIMR_RD_CMD_FIFO_FULL_SHIFT		31
+#define XDPDMA_EIMR_RD_CMD_FIFO_FULL_WIDTH		1
+#define XDPDMA_EIMR_RD_CMD_FIFO_FULL_MASK		0X80000000
+
+#define XDPDMA_EIMR_DSCR_DONE_ERR5_SHIFT		30
+#define XDPDMA_EIMR_DSCR_DONE_ERR5_WIDTH		1
+#define XDPDMA_EIMR_DSCR_DONE_ERR5_MASK			0X40000000
+
+#define XDPDMA_EIMR_DSCR_DONE_ERR4_SHIFT		29
+#define XDPDMA_EIMR_DSCR_DONE_ERR4_WIDTH		1
+#define XDPDMA_EIMR_DSCR_DONE_ERR4_MASK			0X20000000
+
+#define XDPDMA_EIMR_DSCR_DONE_ERR3_SHIFT		28
+#define XDPDMA_EIMR_DSCR_DONE_ERR3_WIDTH		1
+#define XDPDMA_EIMR_DSCR_DONE_ERR3_MASK			0X10000000
+
+#define XDPDMA_EIMR_DSCR_DONE_ERR2_SHIFT		27
+#define XDPDMA_EIMR_DSCR_DONE_ERR2_WIDTH		1
+#define XDPDMA_EIMR_DSCR_DONE_ERR2_MASK			0X08000000
+
+#define XDPDMA_EIMR_DSCR_DONE_ERR1_SHIFT		26
+#define XDPDMA_EIMR_DSCR_DONE_ERR1_WIDTH		1
+#define XDPDMA_EIMR_DSCR_DONE_ERR1_MASK			0X04000000
+
+#define XDPDMA_EIMR_DSCR_DONE_ERR0_SHIFT		25
+#define XDPDMA_EIMR_DSCR_DONE_ERR0_WIDTH		1
+#define XDPDMA_EIMR_DSCR_DONE_ERR0_MASK			0X02000000
+
+#define XDPDMA_EIMR_DSCR_WR_AXI_ERR5_SHIFT		24
+#define XDPDMA_EIMR_DSCR_WR_AXI_ERR5_WIDTH		1
+#define XDPDMA_EIMR_DSCR_WR_AXI_ERR5_MASK		0X01000000
+
+#define XDPDMA_EIMR_DSCR_WR_AXI_ERR4_SHIFT		23
+#define XDPDMA_EIMR_DSCR_WR_AXI_ERR4_WIDTH		1
+#define XDPDMA_EIMR_DSCR_WR_AXI_ERR4_MASK		0X800000
+
+#define XDPDMA_EIMR_DSCR_WR_AXI_ERR3_SHIFT		22
+#define XDPDMA_EIMR_DSCR_WR_AXI_ERR3_WIDTH		1
+#define XDPDMA_EIMR_DSCR_WR_AXI_ERR3_MASK		0X400000
+
+#define XDPDMA_EIMR_DSCR_WR_AXI_ERR2_SHIFT		21
+#define XDPDMA_EIMR_DSCR_WR_AXI_ERR2_WIDTH		1
+#define XDPDMA_EIMR_DSCR_WR_AXI_ERR2_MASK		0X200000
+
+#define XDPDMA_EIMR_DSCR_WR_AXI_ERR1_SHIFT		20
+#define XDPDMA_EIMR_DSCR_WR_AXI_ERR1_WIDTH		1
+#define XDPDMA_EIMR_DSCR_WR_AXI_ERR1_MASK		0X100000
+
+#define XDPDMA_EIMR_DSCR_WR_AXI_ERR0_SHIFT		19
+#define XDPDMA_EIMR_DSCR_WR_AXI_ERR0_WIDTH		1
+#define XDPDMA_EIMR_DSCR_WR_AXI_ERR0_MASK		0X80000
+
+#define XDPDMA_EIMR_DSCR_CRC_ERR5_SHIFT			18
+#define XDPDMA_EIMR_DSCR_CRC_ERR5_WIDTH			1
+#define XDPDMA_EIMR_DSCR_CRC_ERR5_MASK			0X40000
+
+#define XDPDMA_EIMR_DSCR_CRC_ERR4_SHIFT			17
+#define XDPDMA_EIMR_DSCR_CRC_ERR4_WIDTH			1
+#define XDPDMA_EIMR_DSCR_CRC_ERR4_MASK			0X20000
+
+#define XDPDMA_EIMR_DSCR_CRC_ERR3_SHIFT			16
+#define XDPDMA_EIMR_DSCR_CRC_ERR3_WIDTH			1
+#define XDPDMA_EIMR_DSCR_CRC_ERR3_MASK			0X10000
+
+#define XDPDMA_EIMR_DSCR_CRC_ERR2_SHIFT			15
+#define XDPDMA_EIMR_DSCR_CRC_ERR2_WIDTH			1
+#define XDPDMA_EIMR_DSCR_CRC_ERR2_MASK			0X8000
+
+#define XDPDMA_EIMR_DSCR_CRC_ERR1_SHIFT			14
+#define XDPDMA_EIMR_DSCR_CRC_ERR1_WIDTH			1
+#define XDPDMA_EIMR_DSCR_CRC_ERR1_MASK			0X4000
+
+#define XDPDMA_EIMR_DSCR_CRC_ERR0_SHIFT			13
+#define XDPDMA_EIMR_DSCR_CRC_ERR0_WIDTH			1
+#define XDPDMA_EIMR_DSCR_CRC_ERR0_MASK			0X2000
+
+#define XDPDMA_EIMR_DSCR_PRE_ERR5_SHIFT			12
+#define XDPDMA_EIMR_DSCR_PRE_ERR5_WIDTH			1
+#define XDPDMA_EIMR_DSCR_PRE_ERR5_MASK			0X1000
+
+#define XDPDMA_EIMR_DSCR_PRE_ERR4_SHIFT			11
+#define XDPDMA_EIMR_DSCR_PRE_ERR4_WIDTH			1
+#define XDPDMA_EIMR_DSCR_PRE_ERR4_MASK			0X0800
+
+#define XDPDMA_EIMR_DSCR_PRE_ERR3_SHIFT			10
+#define XDPDMA_EIMR_DSCR_PRE_ERR3_WIDTH			1
+#define XDPDMA_EIMR_DSCR_PRE_ERR3_MASK			0X0400
+
+#define XDPDMA_EIMR_DSCR_PRE_ERR2_SHIFT			9
+#define XDPDMA_EIMR_DSCR_PRE_ERR2_WIDTH			1
+#define XDPDMA_EIMR_DSCR_PRE_ERR2_MASK			0X0200
+
+#define XDPDMA_EIMR_DSCR_PRE_ERR1_SHIFT			8
+#define XDPDMA_EIMR_DSCR_PRE_ERR1_WIDTH			1
+#define XDPDMA_EIMR_DSCR_PRE_ERR1_MASK			0X0100
+
+#define XDPDMA_EIMR_DSCR_PRE_ERR0_SHIFT			7
+#define XDPDMA_EIMR_DSCR_PRE_ERR0_WIDTH			1
+#define XDPDMA_EIMR_DSCR_PRE_ERR0_MASK			0X80
+
+#define XDPDMA_EIMR_DSCR_RD_AXI_ERR5_SHIFT		6
+#define XDPDMA_EIMR_DSCR_RD_AXI_ERR5_WIDTH		1
+#define XDPDMA_EIMR_DSCR_RD_AXI_ERR5_MASK		0X40
+
+#define XDPDMA_EIMR_DSCR_RD_AXI_ERR4_SHIFT		5
+#define XDPDMA_EIMR_DSCR_RD_AXI_ERR4_WIDTH		1
+#define XDPDMA_EIMR_DSCR_RD_AXI_ERR4_MASK		0X20
+
+#define XDPDMA_EIMR_DSCR_RD_AXI_ERR3_SHIFT		4
+#define XDPDMA_EIMR_DSCR_RD_AXI_ERR3_WIDTH		1
+#define XDPDMA_EIMR_DSCR_RD_AXI_ERR3_MASK		0X10
+
+#define XDPDMA_EIMR_DSCR_RD_AXI_ERR2_SHIFT		3
+#define XDPDMA_EIMR_DSCR_RD_AXI_ERR2_WIDTH		1
+#define XDPDMA_EIMR_DSCR_RD_AXI_ERR2_MASK		0X8
+
+#define XDPDMA_EIMR_DSCR_RD_AXI_ERR1_SHIFT		2
+#define XDPDMA_EIMR_DSCR_RD_AXI_ERR1_WIDTH		1
+#define XDPDMA_EIMR_DSCR_RD_AXI_ERR1_MASK		0X4
+
+#define XDPDMA_EIMR_DSCR_RD_AXI_ERR0_SHIFT		1
+#define XDPDMA_EIMR_DSCR_RD_AXI_ERR0_WIDTH		1
+#define XDPDMA_EIMR_DSCR_RD_AXI_ERR0_MASK		0X2
+
+#define XDPDMA_EIMR_INV_APB_SHIFT			0
+#define XDPDMA_EIMR_INV_APB_WIDTH			1
+#define XDPDMA_EIMR_INV_APB_MASK			0X1
+
+/**
+ * Register: XDPDMA_EIEN
+ */
+#define XDPDMA_EIEN					0X001C
+
+#define XDPDMA_EIEN_RD_CMD_FIFO_FULL_SHIFT		31
+#define XDPDMA_EIEN_RD_CMD_FIFO_FULL_WIDTH		1
+#define XDPDMA_EIEN_RD_CMD_FIFO_FULL_MASK		0X80000000
+
+#define XDPDMA_EIEN_DSCR_DONE_ERR5_SHIFT		30
+#define XDPDMA_EIEN_DSCR_DONE_ERR5_WIDTH		1
+#define XDPDMA_EIEN_DSCR_DONE_ERR5_MASK			0X40000000
+
+#define XDPDMA_EIEN_DSCR_DONE_ERR4_SHIFT		29
+#define XDPDMA_EIEN_DSCR_DONE_ERR4_WIDTH		1
+#define XDPDMA_EIEN_DSCR_DONE_ERR4_MASK			0X20000000
+
+#define XDPDMA_EIEN_DSCR_DONE_ERR3_SHIFT		28
+#define XDPDMA_EIEN_DSCR_DONE_ERR3_WIDTH		1
+#define XDPDMA_EIEN_DSCR_DONE_ERR3_MASK			0X10000000
+
+#define XDPDMA_EIEN_DSCR_DONE_ERR2_SHIFT		27
+#define XDPDMA_EIEN_DSCR_DONE_ERR2_WIDTH		1
+#define XDPDMA_EIEN_DSCR_DONE_ERR2_MASK			0X08000000
+
+#define XDPDMA_EIEN_DSCR_DONE_ERR1_SHIFT		26
+#define XDPDMA_EIEN_DSCR_DONE_ERR1_WIDTH		1
+#define XDPDMA_EIEN_DSCR_DONE_ERR1_MASK			0X04000000
+
+#define XDPDMA_EIEN_DSCR_DONE_ERR0_SHIFT		25
+#define XDPDMA_EIEN_DSCR_DONE_ERR0_WIDTH		1
+#define XDPDMA_EIEN_DSCR_DONE_ERR0_MASK			0X02000000
+
+#define XDPDMA_EIEN_DSCR_WR_AXI_ERR5_SHIFT		24
+#define XDPDMA_EIEN_DSCR_WR_AXI_ERR5_WIDTH		1
+#define XDPDMA_EIEN_DSCR_WR_AXI_ERR5_MASK		0X01000000
+
+#define XDPDMA_EIEN_DSCR_WR_AXI_ERR4_SHIFT		23
+#define XDPDMA_EIEN_DSCR_WR_AXI_ERR4_WIDTH		1
+#define XDPDMA_EIEN_DSCR_WR_AXI_ERR4_MASK		0X800000
+
+#define XDPDMA_EIEN_DSCR_WR_AXI_ERR3_SHIFT		22
+#define XDPDMA_EIEN_DSCR_WR_AXI_ERR3_WIDTH		1
+#define XDPDMA_EIEN_DSCR_WR_AXI_ERR3_MASK		0X400000
+
+#define XDPDMA_EIEN_DSCR_WR_AXI_ERR2_SHIFT		21
+#define XDPDMA_EIEN_DSCR_WR_AXI_ERR2_WIDTH		1
+#define XDPDMA_EIEN_DSCR_WR_AXI_ERR2_MASK		0X200000
+
+#define XDPDMA_EIEN_DSCR_WR_AXI_ERR1_SHIFT		20
+#define XDPDMA_EIEN_DSCR_WR_AXI_ERR1_WIDTH		1
+#define XDPDMA_EIEN_DSCR_WR_AXI_ERR1_MASK		0X100000
+
+#define XDPDMA_EIEN_DSCR_WR_AXI_ERR0_SHIFT		19
+#define XDPDMA_EIEN_DSCR_WR_AXI_ERR0_WIDTH		1
+#define XDPDMA_EIEN_DSCR_WR_AXI_ERR0_MASK		0X80000
+
+#define XDPDMA_EIEN_DSCR_CRC_ERR5_SHIFT			18
+#define XDPDMA_EIEN_DSCR_CRC_ERR5_WIDTH			1
+#define XDPDMA_EIEN_DSCR_CRC_ERR5_MASK			0X40000
+
+#define XDPDMA_EIEN_DSCR_CRC_ERR4_SHIFT			17
+#define XDPDMA_EIEN_DSCR_CRC_ERR4_WIDTH			1
+#define XDPDMA_EIEN_DSCR_CRC_ERR4_MASK			0X20000
+
+#define XDPDMA_EIEN_DSCR_CRC_ERR3_SHIFT			16
+#define XDPDMA_EIEN_DSCR_CRC_ERR3_WIDTH			1
+#define XDPDMA_EIEN_DSCR_CRC_ERR3_MASK			0X10000
+
+#define XDPDMA_EIEN_DSCR_CRC_ERR2_SHIFT			15
+#define XDPDMA_EIEN_DSCR_CRC_ERR2_WIDTH			1
+#define XDPDMA_EIEN_DSCR_CRC_ERR2_MASK			0X8000
+
+#define XDPDMA_EIEN_DSCR_CRC_ERR1_SHIFT			14
+#define XDPDMA_EIEN_DSCR_CRC_ERR1_WIDTH			1
+#define XDPDMA_EIEN_DSCR_CRC_ERR1_MASK			0X4000
+
+#define XDPDMA_EIEN_DSCR_CRC_ERR0_SHIFT			13
+#define XDPDMA_EIEN_DSCR_CRC_ERR0_WIDTH			1
+#define XDPDMA_EIEN_DSCR_CRC_ERR0_MASK			0X2000
+
+#define XDPDMA_EIEN_DSCR_PRE_ERR5_SHIFT			12
+#define XDPDMA_EIEN_DSCR_PRE_ERR5_WIDTH			1
+#define XDPDMA_EIEN_DSCR_PRE_ERR5_MASK			0X1000
+
+#define XDPDMA_EIEN_DSCR_PRE_ERR4_SHIFT			11
+#define XDPDMA_EIEN_DSCR_PRE_ERR4_WIDTH			1
+#define XDPDMA_EIEN_DSCR_PRE_ERR4_MASK			0X0800
+
+#define XDPDMA_EIEN_DSCR_PRE_ERR3_SHIFT			10
+#define XDPDMA_EIEN_DSCR_PRE_ERR3_WIDTH			1
+#define XDPDMA_EIEN_DSCR_PRE_ERR3_MASK			0X0400
+
+#define XDPDMA_EIEN_DSCR_PRE_ERR2_SHIFT			9
+#define XDPDMA_EIEN_DSCR_PRE_ERR2_WIDTH			1
+#define XDPDMA_EIEN_DSCR_PRE_ERR2_MASK			0X0200
+
+#define XDPDMA_EIEN_DSCR_PRE_ERR1_SHIFT			8
+#define XDPDMA_EIEN_DSCR_PRE_ERR1_WIDTH			1
+#define XDPDMA_EIEN_DSCR_PRE_ERR1_MASK			0X0100
+
+#define XDPDMA_EIEN_DSCR_PRE_ERR0_SHIFT			7
+#define XDPDMA_EIEN_DSCR_PRE_ERR0_WIDTH			1
+#define XDPDMA_EIEN_DSCR_PRE_ERR0_MASK			0X80
+
+#define XDPDMA_EIEN_DSCR_RD_AXI_ERR5_SHIFT		6
+#define XDPDMA_EIEN_DSCR_RD_AXI_ERR5_WIDTH		1
+#define XDPDMA_EIEN_DSCR_RD_AXI_ERR5_MASK		0X40
+
+#define XDPDMA_EIEN_DSCR_RD_AXI_ERR4_SHIFT		5
+#define XDPDMA_EIEN_DSCR_RD_AXI_ERR4_WIDTH		1
+#define XDPDMA_EIEN_DSCR_RD_AXI_ERR4_MASK		0X20
+
+#define XDPDMA_EIEN_DSCR_RD_AXI_ERR3_SHIFT		4
+#define XDPDMA_EIEN_DSCR_RD_AXI_ERR3_WIDTH		1
+#define XDPDMA_EIEN_DSCR_RD_AXI_ERR3_MASK		0X10
+
+#define XDPDMA_EIEN_DSCR_RD_AXI_ERR2_SHIFT		3
+#define XDPDMA_EIEN_DSCR_RD_AXI_ERR2_WIDTH		1
+#define XDPDMA_EIEN_DSCR_RD_AXI_ERR2_MASK		0X8
+
+#define XDPDMA_EIEN_DSCR_RD_AXI_ERR1_SHIFT		2
+#define XDPDMA_EIEN_DSCR_RD_AXI_ERR1_WIDTH		1
+#define XDPDMA_EIEN_DSCR_RD_AXI_ERR1_MASK		0X4
+
+#define XDPDMA_EIEN_DSCR_RD_AXI_ERR0_SHIFT		1
+#define XDPDMA_EIEN_DSCR_RD_AXI_ERR0_WIDTH		1
+#define XDPDMA_EIEN_DSCR_RD_AXI_ERR0_MASK		0X2
+
+#define XDPDMA_EIEN_INV_APB_SHIFT			0
+#define XDPDMA_EIEN_INV_APB_WIDTH			1
+#define XDPDMA_EIEN_INV_APB_MASK			0X1
+
+/**
+ * Register: XDPDMA_EIDS
+ */
+#define XDPDMA_EIDS					0X0020
+
+#define XDPDMA_EIDS_RD_CMD_FIFO_FULL_SHIFT		31
+#define XDPDMA_EIDS_RD_CMD_FIFO_FULL_WIDTH		1
+#define XDPDMA_EIDS_RD_CMD_FIFO_FULL_MASK		0X80000000
+
+#define XDPDMA_EIDS_DSCR_DONE_ERR5_SHIFT		30
+#define XDPDMA_EIDS_DSCR_DONE_ERR5_WIDTH		1
+#define XDPDMA_EIDS_DSCR_DONE_ERR5_MASK			0X40000000
+
+#define XDPDMA_EIDS_DSCR_DONE_ERR4_SHIFT		29
+#define XDPDMA_EIDS_DSCR_DONE_ERR4_WIDTH		1
+#define XDPDMA_EIDS_DSCR_DONE_ERR4_MASK			0X20000000
+
+#define XDPDMA_EIDS_DSCR_DONE_ERR3_SHIFT		28
+#define XDPDMA_EIDS_DSCR_DONE_ERR3_WIDTH		1
+#define XDPDMA_EIDS_DSCR_DONE_ERR3_MASK			0X10000000
+
+#define XDPDMA_EIDS_DSCR_DONE_ERR2_SHIFT		27
+#define XDPDMA_EIDS_DSCR_DONE_ERR2_WIDTH		1
+#define XDPDMA_EIDS_DSCR_DONE_ERR2_MASK			0X08000000
+
+#define XDPDMA_EIDS_DSCR_DONE_ERR1_SHIFT		26
+#define XDPDMA_EIDS_DSCR_DONE_ERR1_WIDTH		1
+#define XDPDMA_EIDS_DSCR_DONE_ERR1_MASK			0X04000000
+
+#define XDPDMA_EIDS_DSCR_DONE_ERR0_SHIFT		25
+#define XDPDMA_EIDS_DSCR_DONE_ERR0_WIDTH		1
+#define XDPDMA_EIDS_DSCR_DONE_ERR0_MASK			0X02000000
+
+#define XDPDMA_EIDS_DSCR_WR_AXI_ERR5_SHIFT		24
+#define XDPDMA_EIDS_DSCR_WR_AXI_ERR5_WIDTH		1
+#define XDPDMA_EIDS_DSCR_WR_AXI_ERR5_MASK		0X01000000
+
+#define XDPDMA_EIDS_DSCR_WR_AXI_ERR4_SHIFT		23
+#define XDPDMA_EIDS_DSCR_WR_AXI_ERR4_WIDTH		1
+#define XDPDMA_EIDS_DSCR_WR_AXI_ERR4_MASK		0X800000
+
+#define XDPDMA_EIDS_DSCR_WR_AXI_ERR3_SHIFT		22
+#define XDPDMA_EIDS_DSCR_WR_AXI_ERR3_WIDTH		1
+#define XDPDMA_EIDS_DSCR_WR_AXI_ERR3_MASK		0X400000
+
+#define XDPDMA_EIDS_DSCR_WR_AXI_ERR2_SHIFT		21
+#define XDPDMA_EIDS_DSCR_WR_AXI_ERR2_WIDTH		1
+#define XDPDMA_EIDS_DSCR_WR_AXI_ERR2_MASK		0X200000
+
+#define XDPDMA_EIDS_DSCR_WR_AXI_ERR1_SHIFT		20
+#define XDPDMA_EIDS_DSCR_WR_AXI_ERR1_WIDTH		1
+#define XDPDMA_EIDS_DSCR_WR_AXI_ERR1_MASK		0X100000
+
+#define XDPDMA_EIDS_DSCR_WR_AXI_ERR0_SHIFT		19
+#define XDPDMA_EIDS_DSCR_WR_AXI_ERR0_WIDTH		1
+#define XDPDMA_EIDS_DSCR_WR_AXI_ERR0_MASK		0X80000
+
+#define XDPDMA_EIDS_DSCR_CRC_ERR5_SHIFT			18
+#define XDPDMA_EIDS_DSCR_CRC_ERR5_WIDTH			1
+#define XDPDMA_EIDS_DSCR_CRC_ERR5_MASK			0X40000
+
+#define XDPDMA_EIDS_DSCR_CRC_ERR4_SHIFT			17
+#define XDPDMA_EIDS_DSCR_CRC_ERR4_WIDTH			1
+#define XDPDMA_EIDS_DSCR_CRC_ERR4_MASK			0X20000
+
+#define XDPDMA_EIDS_DSCR_CRC_ERR3_SHIFT			16
+#define XDPDMA_EIDS_DSCR_CRC_ERR3_WIDTH			1
+#define XDPDMA_EIDS_DSCR_CRC_ERR3_MASK			0X10000
+
+#define XDPDMA_EIDS_DSCR_CRC_ERR2_SHIFT			15
+#define XDPDMA_EIDS_DSCR_CRC_ERR2_WIDTH			1
+#define XDPDMA_EIDS_DSCR_CRC_ERR2_MASK			0X8000
+
+#define XDPDMA_EIDS_DSCR_CRC_ERR1_SHIFT			14
+#define XDPDMA_EIDS_DSCR_CRC_ERR1_WIDTH			1
+#define XDPDMA_EIDS_DSCR_CRC_ERR1_MASK			0X4000
+
+#define XDPDMA_EIDS_DSCR_CRC_ERR0_SHIFT			13
+#define XDPDMA_EIDS_DSCR_CRC_ERR0_WIDTH			1
+#define XDPDMA_EIDS_DSCR_CRC_ERR0_MASK			0X2000
+
+#define XDPDMA_EIDS_DSCR_PRE_ERR5_SHIFT			12
+#define XDPDMA_EIDS_DSCR_PRE_ERR5_WIDTH			1
+#define XDPDMA_EIDS_DSCR_PRE_ERR5_MASK			0X1000
+
+#define XDPDMA_EIDS_DSCR_PRE_ERR4_SHIFT			11
+#define XDPDMA_EIDS_DSCR_PRE_ERR4_WIDTH			1
+#define XDPDMA_EIDS_DSCR_PRE_ERR4_MASK			0X0800
+
+#define XDPDMA_EIDS_DSCR_PRE_ERR3_SHIFT			10
+#define XDPDMA_EIDS_DSCR_PRE_ERR3_WIDTH			1
+#define XDPDMA_EIDS_DSCR_PRE_ERR3_MASK			0X0400
+
+#define XDPDMA_EIDS_DSCR_PRE_ERR2_SHIFT			9
+#define XDPDMA_EIDS_DSCR_PRE_ERR2_WIDTH			1
+#define XDPDMA_EIDS_DSCR_PRE_ERR2_MASK			0X0200
+
+#define XDPDMA_EIDS_DSCR_PRE_ERR1_SHIFT			8
+#define XDPDMA_EIDS_DSCR_PRE_ERR1_WIDTH			1
+#define XDPDMA_EIDS_DSCR_PRE_ERR1_MASK			0X0100
+
+#define XDPDMA_EIDS_DSCR_PRE_ERR0_SHIFT			7
+#define XDPDMA_EIDS_DSCR_PRE_ERR0_WIDTH			1
+#define XDPDMA_EIDS_DSCR_PRE_ERR0_MASK			0X80
+
+#define XDPDMA_EIDS_DSCR_RD_AXI_ERR5_SHIFT		6
+#define XDPDMA_EIDS_DSCR_RD_AXI_ERR5_WIDTH		1
+#define XDPDMA_EIDS_DSCR_RD_AXI_ERR5_MASK		0X40
+
+#define XDPDMA_EIDS_DSCR_RD_AXI_ERR4_SHIFT		5
+#define XDPDMA_EIDS_DSCR_RD_AXI_ERR4_WIDTH		1
+#define XDPDMA_EIDS_DSCR_RD_AXI_ERR4_MASK		0X20
+
+#define XDPDMA_EIDS_DSCR_RD_AXI_ERR3_SHIFT		4
+#define XDPDMA_EIDS_DSCR_RD_AXI_ERR3_WIDTH		1
+#define XDPDMA_EIDS_DSCR_RD_AXI_ERR3_MASK		0X10
+
+#define XDPDMA_EIDS_DSCR_RD_AXI_ERR2_SHIFT		3
+#define XDPDMA_EIDS_DSCR_RD_AXI_ERR2_WIDTH		1
+#define XDPDMA_EIDS_DSCR_RD_AXI_ERR2_MASK		0X8
+
+#define XDPDMA_EIDS_DSCR_RD_AXI_ERR1_SHIFT		2
+#define XDPDMA_EIDS_DSCR_RD_AXI_ERR1_WIDTH		1
+#define XDPDMA_EIDS_DSCR_RD_AXI_ERR1_MASK		0X4
+
+#define XDPDMA_EIDS_DSCR_RD_AXI_ERR0_SHIFT		1
+#define XDPDMA_EIDS_DSCR_RD_AXI_ERR0_WIDTH		1
+#define XDPDMA_EIDS_DSCR_RD_AXI_ERR0_MASK		0X2
+
+#define XDPDMA_EIDS_INV_APB_SHIFT			0
+#define XDPDMA_EIDS_INV_APB_WIDTH			1
+#define XDPDMA_EIDS_INV_APB_MASK			0X1
+
+/**
+ * Register: XDPDMA_CNTL
+ */
+#define XDPDMA_CNTL					0X0100
+
+/**
+ * Register: XDPDMA_GBL
+ */
+#define XDPDMA_GBL					0X0104
+
+#define XDPDMA_GBL_RTRG_CH5_SHIFT			11
+#define XDPDMA_GBL_RTRG_CH5_WIDTH			1
+#define XDPDMA_GBL_RTRG_CH5_MASK			0X0800
+
+#define XDPDMA_GBL_RTRG_CH4_SHIFT			10
+#define XDPDMA_GBL_RTRG_CH4_WIDTH			1
+#define XDPDMA_GBL_RTRG_CH4_MASK			0X0400
+
+#define XDPDMA_GBL_RTRG_CH3_SHIFT			9
+#define XDPDMA_GBL_RTRG_CH3_WIDTH			1
+#define XDPDMA_GBL_RTRG_CH3_MASK			0X0200
+
+#define XDPDMA_GBL_RTRG_CH2_SHIFT			8
+#define XDPDMA_GBL_RTRG_CH2_WIDTH			1
+#define XDPDMA_GBL_RTRG_CH2_MASK			0X0100
+
+#define XDPDMA_GBL_RTRG_CH1_SHIFT			7
+#define XDPDMA_GBL_RTRG_CH1_WIDTH			1
+#define XDPDMA_GBL_RTRG_CH1_MASK			0X80
+
+#define XDPDMA_GBL_RTRG_CH0_SHIFT			6
+#define XDPDMA_GBL_RTRG_CH0_WIDTH			1
+#define XDPDMA_GBL_RTRG_CH0_MASK			0X40
+
+#define XDPDMA_GBL_TRG_CH5_SHIFT			5
+#define XDPDMA_GBL_TRG_CH5_WIDTH			1
+#define XDPDMA_GBL_TRG_CH5_MASK				0X20
+
+#define XDPDMA_GBL_TRG_CH4_SHIFT			4
+#define XDPDMA_GBL_TRG_CH4_WIDTH			1
+#define XDPDMA_GBL_TRG_CH4_MASK				0X10
+
+#define XDPDMA_GBL_TRG_CH3_SHIFT			3
+#define XDPDMA_GBL_TRG_CH3_WIDTH			1
+#define XDPDMA_GBL_TRG_CH3_MASK				0X8
+
+#define XDPDMA_GBL_TRG_CH2_SHIFT			2
+#define XDPDMA_GBL_TRG_CH2_WIDTH			1
+#define XDPDMA_GBL_TRG_CH2_MASK				0X4
+
+#define XDPDMA_GBL_TRG_CH1_SHIFT			1
+#define XDPDMA_GBL_TRG_CH1_WIDTH			1
+#define XDPDMA_GBL_TRG_CH1_MASK				0X2
+
+#define XDPDMA_GBL_TRG_CH0_SHIFT			0
+#define XDPDMA_GBL_TRG_CH0_WIDTH			1
+#define XDPDMA_GBL_TRG_CH0_MASK				0X1
+
+/**
+ * Register: XDPDMA_CH0_DSCR_STRT_ADDRE
+ */
+#define XDPDMA_CH0_DSCR_STRT_ADDRE			0X0200
+
+/**
+ * Register: XDPDMA_CH0_DSCR_STRT_ADDR
+ */
+#define XDPDMA_CH0_DSCR_STRT_ADDR			0X0204
+
+/**
+ * Register: XDPDMA_CH0_DSCR_NEXT_ADDRE
+ */
+#define XDPDMA_CH0_DSCR_NEXT_ADDRE			0X0208
+
+/**
+ * Register: XDPDMA_CH0_DSCR_NEXT_ADDR
+ */
+#define XDPDMA_CH0_DSCR_NEXT_ADDR			0X020C
+
+/**
+ * Register: XDPDMA_CH0_PYLD_CUR_ADDRE
+ */
+#define XDPDMA_CH0_PYLD_CUR_ADDRE			0X0210
+
+/**
+ * Register: XDPDMA_CH0_PYLD_CUR_ADDR
+ */
+#define XDPDMA_CH0_PYLD_CUR_ADDR			0X0214
+
+/**
+ * Register: XDPDMA_CH0_CNTL
+ */
+#define XDPDMA_CH0_CNTL					0X0218
+
+#define XDPDMA_CNTL_QOS_VIDEO				0x11
+
+/**
+ * Register: XDPDMA_CH0_STATUS
+ */
+#define XDPDMA_CH0_STATUS				0X021C
+
+/**
+ * Register: XDPDMA_CH0_VDO
+ */
+#define XDPDMA_CH0_VDO					0X0220
+
+/**
+ * Register: XDPDMA_CH0_PYLD_SZ
+ */
+#define XDPDMA_CH0_PYLD_SZ				0X0224
+
+/**
+ * Register: XDPDMA_CH0_DSCR_ID
+ */
+#define XDPDMA_CH0_DSCR_ID				0X0228
+
+/**
+ * Register: XDPDMA_CH1_DSCR_STRT_ADDRE
+ */
+#define XDPDMA_CH1_DSCR_STRT_ADDRE			0X0300
+
+/**
+ * Register: XDPDMA_CH1_DSCR_STRT_ADDR
+ */
+#define XDPDMA_CH1_DSCR_STRT_ADDR			0X0304
+
+/**
+ * Register: XDPDMA_CH1_DSCR_NEXT_ADDRE
+ */
+#define XDPDMA_CH1_DSCR_NEXT_ADDRE			0X0308
+
+/**
+ * Register: XDPDMA_CH1_DSCR_NEXT_ADDR
+ */
+#define XDPDMA_CH1_DSCR_NEXT_ADDR			0X030C
+
+/**
+ * Register: XDPDMA_CH1_PYLD_CUR_ADDRE
+ */
+#define XDPDMA_CH1_PYLD_CUR_ADDRE			0X0310
+
+/**
+ * Register: XDPDMA_CH1_PYLD_CUR_ADDR
+ */
+#define XDPDMA_CH1_PYLD_CUR_ADDR			0X0314
+
+/**
+ * Register: XDPDMA_CH1_CNTL
+ */
+#define XDPDMA_CH1_CNTL					0X0318
+/**
+ * Register: XDPDMA_CH1_STATUS
+ */
+#define XDPDMA_CH1_STATUS				0X031C
+
+/**
+ * Register: XDPDMA_CH1_VDO
+ */
+#define XDPDMA_CH1_VDO					0X0320
+
+/**
+ * Register: XDPDMA_CH1_PYLD_SZ
+ */
+#define XDPDMA_CH1_PYLD_SZ				0X0324
+
+/**
+ * Register: XDPDMA_CH1_DSCR_ID
+ */
+#define XDPDMA_CH1_DSCR_ID				0X0328
+
+/**
+ * Register: XDPDMA_CH2_DSCR_STRT_ADDRE
+ */
+#define XDPDMA_CH2_DSCR_STRT_ADDRE			0X0400
+
+/**
+ * Register: XDPDMA_CH2_DSCR_STRT_ADDR
+ */
+#define XDPDMA_CH2_DSCR_STRT_ADDR			0X0404
+
+/**
+ * Register: XDPDMA_CH2_DSCR_NEXT_ADDRE
+ */
+#define XDPDMA_CH2_DSCR_NEXT_ADDRE			0X0408
+
+/**
+ * Register: XDPDMA_CH2_DSCR_NEXT_ADDR
+ */
+#define XDPDMA_CH2_DSCR_NEXT_ADDR			0X040C
+
+/**
+ * Register: XDPDMA_CH2_PYLD_CUR_ADDRE
+ */
+#define XDPDMA_CH2_PYLD_CUR_ADDRE			0X0410
+
+/**
+ * Register: XDPDMA_CH2_PYLD_CUR_ADDR
+ */
+#define XDPDMA_CH2_PYLD_CUR_ADDR			0X0414
+
+/**
+ * Register: XDPDMA_CH2_CNTL
+ */
+#define XDPDMA_CH2_CNTL					0X0418
+
+/**
+ * Register: XDPDMA_CH2_STATUS
+ */
+#define XDPDMA_CH2_STATUS				0X041C
+
+/**
+ * Register: XDPDMA_CH2_VDO
+ */
+#define XDPDMA_CH2_VDO					0X0420
+
+/**
+ * Register: XDPDMA_CH2_PYLD_SZ
+ */
+#define XDPDMA_CH2_PYLD_SZ				0X0424
+
+/**
+ * Register: XDPDMA_CH2_DSCR_ID
+ */
+#define XDPDMA_CH2_DSCR_ID				0X0428
+
+/**
+ * Register: XDPDMA_CH3_DSCR_STRT_ADDRE
+ */
+#define XDPDMA_CH3_DSCR_STRT_ADDRE			0X0500
+
+/**
+ * Register: XDPDMA_CH3_DSCR_STRT_ADDR
+ */
+#define XDPDMA_CH3_DSCR_STRT_ADDR			0X0504
+
+/**
+ * Register: XDPDMA_CH3_DSCR_NEXT_ADDRE
+ */
+#define XDPDMA_CH3_DSCR_NEXT_ADDRE			0X0508
+
+/**
+ * Register: XDPDMA_CH3_DSCR_NEXT_ADDR
+ */
+#define XDPDMA_CH3_DSCR_NEXT_ADDR			0X050C
+
+/**
+ * Register: XDPDMA_CH3_PYLD_CUR_ADDRE
+ */
+#define XDPDMA_CH3_PYLD_CUR_ADDRE			0X0510
+
+/**
+ * Register: XDPDMA_CH3_PYLD_CUR_ADDR
+ */
+#define XDPDMA_CH3_PYLD_CUR_ADDR			0X0514
+
+/**
+ * Register: XDPDMA_CH3_CNTL
+ */
+#define XDPDMA_CH3_CNTL					0X0518
+/**
+ * Register: XDPDMA_CH3_STATUS
+ */
+#define XDPDMA_CH3_STATUS				0X051C
+
+/**
+ * Register: XDPDMA_CH3_VDO
+ */
+#define XDPDMA_CH3_VDO					0X0520
+
+/**
+ * Register: XDPDMA_CH3_PYLD_SZ
+ */
+#define XDPDMA_CH3_PYLD_SZ				0X0524
+
+/**
+ * Register: XDPDMA_CH3_DSCR_ID
+ */
+#define XDPDMA_CH3_DSCR_ID				0X0528
+
+/**
+ * Register: XDPDMA_CH4_DSCR_STRT_ADDRE
+ */
+#define XDPDMA_CH4_DSCR_STRT_ADDRE			0X0600
+
+/**
+ * Register: XDPDMA_CH4_DSCR_STRT_ADDR
+ */
+#define XDPDMA_CH4_DSCR_STRT_ADDR			0X0604
+/**
+ * Register: XDPDMA_CH4_DSCR_NEXT_ADDRE
+ */
+#define XDPDMA_CH4_DSCR_NEXT_ADDRE			0X0608
+
+/**
+ * Register: XDPDMA_CH4_DSCR_NEXT_ADDR
+ */
+#define XDPDMA_CH4_DSCR_NEXT_ADDR			0X060C
+
+/**
+ * Register: XDPDMA_CH4_PYLD_CUR_ADDRE
+ */
+#define XDPDMA_CH4_PYLD_CUR_ADDRE			0X0610
+
+/**
+ * Register: XDPDMA_CH4_PYLD_CUR_ADDR
+ */
+#define XDPDMA_CH4_PYLD_CUR_ADDR			0X0614
+
+/**
+ * Register: XDPDMA_CH4_CNTL
+ */
+#define XDPDMA_CH4_CNTL					0X0618
+
+/**
+ * Register: XDPDMA_CH4_STATUS
+ */
+#define XDPDMA_CH4_STATUS				0X061C
+
+/**
+ * Register: XDPDMA_CH4_VDO
+ */
+#define XDPDMA_CH4_VDO					0X0620
+
+/**
+ * Register: XDPDMA_CH4_PYLD_SZ
+ */
+#define XDPDMA_CH4_PYLD_SZ				0X0624
+
+/**
+ * Register: XDPDMA_CH4_DSCR_ID
+ */
+#define XDPDMA_CH4_DSCR_ID				0X0628
+
+/**
+ * Register: XDPDMA_CH5_DSCR_STRT_ADDRE
+ */
+#define XDPDMA_CH5_DSCR_STRT_ADDRE			0X0700
+
+/**
+ * Register: XDPDMA_CH5_DSCR_STRT_ADDR
+ */
+#define XDPDMA_CH5_DSCR_STRT_ADDR			0X0704
+
+/**
+ * Register: XDPDMA_CH5_DSCR_NEXT_ADDRE
+ */
+#define XDPDMA_CH5_DSCR_NEXT_ADDRE			0X0708
+
+/**
+ * Register: XDPDMA_CH5_DSCR_NEXT_ADDR
+ */
+#define XDPDMA_CH5_DSCR_NEXT_ADDR			0X070C
+
+/**
+ * Register: XDPDMA_CH5_PYLD_CUR_ADDRE
+ */
+#define XDPDMA_CH5_PYLD_CUR_ADDRE			0X0710
+
+/**
+ * Register: XDPDMA_CH5_PYLD_CUR_ADDR
+ */
+#define XDPDMA_CH5_PYLD_CUR_ADDR			0X0714
+
+/**
+ * Register: XDPDMA_CH5_CNTL
+ */
+#define XDPDMA_CH5_CNTL					0X0718
+
+/**
+ * Register: XDPDMA_CH5_STATUS
+ */
+#define XDPDMA_CH5_STATUS				0X071C
+
+/**
+ * Register: XDPDMA_CH5_VDO
+ */
+#define XDPDMA_CH5_VDO					0X0720
+
+/**
+ * Register: XDPDMA_CH5_PYLD_SZ
+ */
+#define XDPDMA_CH5_PYLD_SZ				0X0724
+
+/**
+ * Register: XDPDMA_CH5_DSCR_ID
+ */
+#define XDPDMA_CH5_DSCR_ID				0X0728
+
+
+#define XDPDMA_CH_DSCR_STRT_ADDRE_MSB_SHIFT		0
+#define XDPDMA_CH_DSCR_STRT_ADDRE_MSB_WIDTH		16
+#define XDPDMA_CH_DSCR_STRT_ADDRE_MSB_MASK		0XFFFF
+
+
+#define XDPDMA_CH_DSCR_STRT_ADDR_LSB_SHIFT		0
+#define XDPDMA_CH_DSCR_STRT_ADDR_LSB_WIDTH		32
+#define XDPDMA_CH_DSCR_STRT_ADDR_LSB_MASK		0XFFFFFFFF
+
+
+#define XDPDMA_CH_DSCR_NEXT_ADDRE_MSB_SHIFT		0
+#define XDPDMA_CH_DSCR_NEXT_ADDRE_MSB_WIDTH		16
+#define XDPDMA_CH_DSCR_NEXT_ADDRE_MSB_MASK		0XFFFF
+
+
+#define XDPDMA_CH_DSCR_NEXT_ADDR_LSB_SHIFT		0
+#define XDPDMA_CH_DSCR_NEXT_ADDR_LSB_WIDTH		32
+#define XDPDMA_CH_DSCR_NEXT_ADDR_LSB_MASK		0XFFFFFFFF
+
+
+#define XDPDMA_CH_PYLD_CUR_ADDRE_MSB_SHIFT		0
+#define XDPDMA_CH_PYLD_CUR_ADDRE_MSB_WIDTH		16
+#define XDPDMA_CH_PYLD_CUR_ADDRE_MSB_MASK		0XFFFF
+
+#define XDPDMA_CH_PYLD_CUR_ADDR_LSB_SHIFT		0
+#define XDPDMA_CH_PYLD_CUR_ADDR_LSB_WIDTH		32
+#define XDPDMA_CH_PYLD_CUR_ADDR_LSB_MASK		0XFFFFFFFF
+
+#define XDPDMA_CH_CNTL_DSCR_AXCACHE_SHIFT		16
+#define XDPDMA_CH_CNTL_DSCR_AXCACHE_WIDTH		4
+#define XDPDMA_CH_CNTL_DSCR_AXCACHE_MASK		0XF0000
+
+#define XDPDMA_CH_CNTL_DSCR_AXPROT_SHIFT		14
+#define XDPDMA_CH_CNTL_DSCR_AXPROT_WIDTH		2
+#define XDPDMA_CH_CNTL_DSCR_AXPROT_MASK			0XC000
+
+#define XDPDMA_CH_CNTL_QOS_DATA_RD_SHIFT		10
+#define XDPDMA_CH_CNTL_QOS_DATA_RD_WIDTH		4
+#define XDPDMA_CH_CNTL_QOS_DATA_RD_MASK			0X3C00
+
+#define XDPDMA_CH_CNTL_QOS_DSCR_RD_SHIFT		6
+#define XDPDMA_CH_CNTL_QOS_DSCR_RD_WIDTH		4
+#define XDPDMA_CH_CNTL_QOS_DSCR_RD_MASK			0X03C0
+
+#define XDPDMA_CH_CNTL_QOS_DSCR_WR_SHIFT		2
+#define XDPDMA_CH_CNTL_QOS_DSCR_WR_WIDTH		4
+#define XDPDMA_CH_CNTL_QOS_DSCR_WR_MASK			0X3C
+
+#define XDPDMA_CH_CNTL_PAUSE_SHIFT			1
+#define XDPDMA_CH_CNTL_PAUSE_WIDTH			1
+#define XDPDMA_CH_CNTL_PAUSE_MASK			0X2
+
+#define XDPDMA_CH_CNTL_EN_SHIFT				0
+#define XDPDMA_CH_CNTL_EN_WIDTH				1
+#define XDPDMA_CH_CNTL_EN_MASK				0X1
+
+
+#define XDPDMA_CH_STATUS_OTRAN_CNT_SHIFT		21
+#define XDPDMA_CH_STATUS_OTRAN_CNT_WIDTH		4
+#define XDPDMA_CH_STATUS_OTRAN_CNT_MASK			0X01E00000
+
+#define XDPDMA_CH_STATUS_PREAMBLE_SHIFT			13
+#define XDPDMA_CH_STATUS_PREAMBLE_WIDTH			8
+#define XDPDMA_CH_STATUS_PREAMBLE_MASK			0X1FE000
+
+#define XDPDMA_CH_STATUS_EN_DSCR_INTR_SHIFT		12
+#define XDPDMA_CH_STATUS_EN_DSCR_INTR_WIDTH		1
+#define XDPDMA_CH_STATUS_EN_DSCR_INTR_MASK		0X1000
+
+#define XDPDMA_CH_STATUS_EN_DSCR_UP_SHIFT		11
+#define XDPDMA_CH_STATUS_EN_DSCR_UP_WIDTH		1
+#define XDPDMA_CH_STATUS_EN_DSCR_UP_MASK		0X0800
+
+#define XDPDMA_CH_STATUS_DSCR_DONE_SHIFT		10
+#define XDPDMA_CH_STATUS_DSCR_DONE_WIDTH		1
+#define XDPDMA_CH_STATUS_DSCR_DONE_MASK			0X0400
+
+#define XDPDMA_CH_STATUS_IGNR_DONE_SHIFT		9
+#define XDPDMA_CH_STATUS_IGNR_DONE_WIDTH		1
+#define XDPDMA_CH_STATUS_IGNR_DONE_MASK			0X0200
+
+#define XDPDMA_CH_STATUS_LDSCR_FRAME_SHIFT		8
+#define XDPDMA_CH_STATUS_LDSCR_FRAME_WIDTH		1
+#define XDPDMA_CH_STATUS_LDSCR_FRAME_MASK		0X0100
+
+#define XDPDMA_CH_STATUS_LAST_DSCR_SHIFT		7
+#define XDPDMA_CH_STATUS_LAST_DSCR_WIDTH		1
+#define XDPDMA_CH_STATUS_LAST_DSCR_MASK			0X80
+
+#define XDPDMA_CH_STATUS_EN_CRC_SHIFT			6
+#define XDPDMA_CH_STATUS_EN_CRC_WIDTH			1
+#define XDPDMA_CH_STATUS_EN_CRC_MASK			0X40
+
+#define XDPDMA_CH_STATUS_MODE_SHIFT			5
+#define XDPDMA_CH_STATUS_MODE_WIDTH			1
+#define XDPDMA_CH_STATUS_MODE_MASK			0X20
+
+#define XDPDMA_CH_STATUS_BURST_TYPE_SHIFT		4
+#define XDPDMA_CH_STATUS_BURST_TYPE_WIDTH		1
+#define XDPDMA_CH_STATUS_BURST_TYPE_MASK		0X10
+
+#define XDPDMA_CH_STATUS_BURST_LEN_SHIFT		0
+#define XDPDMA_CH_STATUS_BURST_LEN_WIDTH		4
+#define XDPDMA_CH_STATUS_BURST_LEN_MASK			0XF
+
+
+#define XDPDMA_CH_VDO_LINE_LENGTH_SHIFT			14
+#define XDPDMA_CH_VDO_LINE_LENGTH_WIDTH			18
+#define XDPDMA_CH_VDO_LINE_LENGTH_MASK			0XFFFFC000
+
+#define XDPDMA_CH_VDO_STRIDE_SHIFT			0
+#define XDPDMA_CH_VDO_STRIDE_WIDTH			14
+#define XDPDMA_CH_VDO_STRIDE_MASK			0X3FFF
+
+#define XDPDMA_CH_PYLD_SZ_BYTE_SHIFT			0
+#define XDPDMA_CH_PYLD_SZ_BYTE_WIDTH			32
+#define XDPDMA_CH_PYLD_SZ_BYTE_MASK			0XFFFFFFFF
+
+#define XDPDMA_CH_DSCR_ID_VAL_SHIFT			0
+#define XDPDMA_CH_DSCR_ID_VAL_WIDTH			16
+#define XDPDMA_CH_DSCR_ID_VAL_MASK			0XFFFF
+
+/**
+ * Register: XDPDMA_ECO
+ */
+#define XDPDMA_ECO					0X0FFC
+
+#define XDPDMA_ECO_VAL_SHIFT				0
+#define XDPDMA_ECO_VAL_WIDTH				32
+#define XDPDMA_ECO_VAL_MASK				0XFFFFFFFF
+
+/**
+ * DPDMA descriptor
+ */
+
+#define XDPDMA_DESCRIPTOR_CONTROL_PREAMBLE_SHIFT		0
+#define XDPDMA_DESCRIPTOR_CONTROL_PREAMBLE_WIDTH		8
+#define XDPDMA_DESCRIPTOR_CONTROL_PREAMBLE_MASK			0XFF
+
+#define XDPDMA_DESCRIPTOR_CONTROL_EN_COMP_INTR_SHIFT		8
+#define XDPDMA_DESCRIPTOR_CONTROL_EN_COMP_INTR_WIDTH		1
+#define XDPDMA_DESCRIPTOR_CONTROL_EN_COMP_INTR_MASK		0X0100
+
+#define XDPDMA_DESCRIPTOR_CONTROL_EN_DESC_UPDATE_SHIFT		9
+#define XDPDMA_DESCRIPTOR_CONTROL_EN_DESC_UPDATE_WIDTH		1
+#define XDPDMA_DESCRIPTOR_CONTROL_EN_DESC_UPDATE_MASK		0X0200
+
+#define XDPDMA_DESCRIPTOR_CONTROL_IGNORE_DONE_SHIFT		10
+#define XDPDMA_DESCRIPTOR_CONTROL_IGNORE_DONE_WIDTH		1
+#define XDPDMA_DESCRIPTOR_CONTROL_IGNORE_DONE_MASK		0X0400
+
+#define XDPDMA_DESCRIPTOR_CONTROL_AXI_BURST_TYPE_SHIFT		11
+#define XDPDMA_DESCRIPTOR_CONTROL_AXI_BURST_TYPE_WIDTH		1
+#define XDPDMA_DESCRIPTOR_CONTROL_AXI_BURST_TYPE_MASK		0X0800
+
+#define XDPDMA_DESCRIPTOR_CONTROL_AXACACHE_SHIFT		12
+#define XDPDMA_DESCRIPTOR_CONTROL_AXACACHE_WIDTH		4
+#define XDPDMA_DESCRIPTOR_CONTROL_AXACACHE_MASK			0XF000
+
+#define XDPDMA_DESCRIPTOR_CONTROL_AXPROT_SHIFT			16
+#define XDPDMA_DESCRIPTOR_CONTROL_AXPROT_WIDTH			2
+#define XDPDMA_DESCRIPTOR_CONTROL_AXPROT_MASK			0X30000
+
+#define XDPDMA_DESCRIPTOR_CONTROL_MODE_SHIFT			18
+#define XDPDMA_DESCRIPTOR_CONTROL_MODE_WIDTH			1
+#define XDPDMA_DESCRIPTOR_CONTROL_MODE_MASK			0X40000
+
+#define XDPDMA_DESCRIPTOR_CONTROL_LAST_DESC_SHIFT		19
+#define XDPDMA_DESCRIPTOR_CONTROL_LAST_DESC_WIDTH		1
+#define XDPDMA_DESCRIPTOR_CONTROL_LAST_DESC_MASK		0X80000
+
+#define XDPDMA_DESCRIPTOR_CONTROL_ENABLE_CRC_SHIFT		20
+#define XDPDMA_DESCRIPTOR_CONTROL_ENABLE_CRC_WIDTH		1
+#define XDPDMA_DESCRIPTOR_CONTROL_ENABLE_CRC_MASK		0x00100000
+
+#define XDPDMA_DESCRIPTOR_CONTROL_LAST_DESC_FRAME_SHIFT		21
+#define XDPDMA_DESCRIPTOR_CONTROL_LAST_DESC_FRAME_WIDTH		1
+#define XDPDMA_DESCRIPTOR_CONTROL_LAST_DESC_FRAME_MASK		0X200000
+
+#define XDPDMA_DESCRIPTOR_DSCR_ID_SHIFT				0
+#define XDPDMA_DESCRIPTOR_DSCR_ID_WIDTH				16
+#define XDPDMA_DESCRIPTOR_DSCR_ID_MASK				0XFFFF
+
+#define XDPDMA_DESCRIPTOR_XFER_SIZE_SHIFT			0
+#define XDPDMA_DESCRIPTOR_XFER_SIZE_WIDTH			32
+#define XDPDMA_DESCRIPTOR_XFER_SIZE_MASK			0x0000FFFF
+
+#define XDPDMA_DESCRIPTOR_LINE_SIZE_HZ_RES_SHIFT		0
+#define XDPDMA_DESCRIPTOR_LINE_SIZE_HZ_RES_WIDTH		18
+#define XDPDMA_DESCRIPTOR_LINE_SIZE_HZ_RES_MASK			0X3FFFF
+
+#define XDPDMA_DESCRIPTOR_LINE_SIZE_STRIDE_SHIFT		18
+#define XDPDMA_DESCRIPTOR_LINE_SIZE_STRIDE_WIDTH		14
+#define XDPDMA_DESCRIPTOR_LINE_SIZE_STRIDE_MASK			0XFFFC0000
+
+#define XDPDMA_DESCRIPTOR_TS_LSB_SHIFT				0
+#define XDPDMA_DESCRIPTOR_TS_LSB_WIDTH				32
+#define XDPDMA_DESCRIPTOR_TS_LSB_MASK				0XFFFFFFFF
+
+#define XDPDMA_DESCRIPTOR_TS_MSB_SHIFT				0
+#define XDPDMA_DESCRIPTOR_TS_MSB_WIDTH				32
+#define XDPDMA_DESCRIPTOR_TS_MSB_MASK				0XFFFFFFFF
+
+#define XDPDMA_DESCRIPTOR_TS_MSB_TS_SHIFT			0
+#define XDPDMA_DESCRIPTOR_TS_MSB_TS_WIDTH			9
+#define XDPDMA_DESCRIPTOR_TS_MSB_TS_MASK			0X01FF
+
+#define XDPDMA_DESCRIPTOR_TS_MSB_STATUS_SHIFT			31
+#define XDPDMA_DESCRIPTOR_TS_MSB_STATUS_WIDTH			1
+#define XDPDMA_DESCRIPTOR_TS_MSB_STATUS_MASK			0X80000000
+
+#define XDPDMA_DESCRIPTOR_ADDR_EXT_DSC_NXT_SHIFT		0
+#define XDPDMA_DESCRIPTOR_ADDR_EXT_DSC_NXT_WIDTH		16
+#define XDPDMA_DESCRIPTOR_ADDR_EXT_DSC_NXT_MASK			0XFFFF
+
+#define XDPDMA_DESCRIPTOR_ADDR_EXT_SRC_ADDR_EXT_SHIFT		16
+#define XDPDMA_DESCRIPTOR_ADDR_EXT_SRC_ADDR_EXT_WIDTH		16
+#define XDPDMA_DESCRIPTOR_ADDR_EXT_SRC_ADDR_EXT_MASK		0XFFFF0000
+
+#define XDPDMA_DESCRIPTOR_ADDR_EXT23_2_SHIFT			0
+#define XDPDMA_DESCRIPTOR_ADDR_EXT23_2_WIDTH			16
+#define XDPDMA_DESCRIPTOR_ADDR_EXT23_2_MASK			0XFFFF
+
+#define XDPDMA_DESCRIPTOR_ADDR_EXT23_3_SHIFT			16
+#define XDPDMA_DESCRIPTOR_ADDR_EXT23_3_WIDTH			16
+#define XDPDMA_DESCRIPTOR_ADDR_EXT23_3_MASK			0xFFFF0000
+
+#define XDPDMA_DESCRIPTOR_ADDR_EXT45_4_SHIFT			0
+#define XDPDMA_DESCRIPTOR_ADDR_EXT45_4_WIDTH			16
+#define XDPDMA_DESCRIPTOR_ADDR_EXT45_4_MASK			0XFFFF
+
+#define XDPDMA_DESCRIPTOR_ADDR_EXT45_5_SHIFT			16
+#define XDPDMA_DESCRIPTOR_ADDR_EXT45_5_WIDTH			16
+#define XDPDMA_DESCRIPTOR_ADDR_EXT45_5_MASK			0XFFFF0000
+
+#define XDPDMA_DESCRIPTOR_NEXT_DESR_SHIFT			0
+#define XDPDMA_DESCRIPTOR_NEXT_DESR_WIDTH			32
+#define XDPDMA_DESCRIPTOR_NEXT_DESR_MASK			0XFFFFFFFF
+
+#define XDPDMA_DESCRIPTOR_SRC_ADDR_SHIFT			0
+#define XDPDMA_DESCRIPTOR_SRC_ADDR_WIDTH			32
+#define XDPDMA_DESCRIPTOR_SRC_ADDR_MASK				0XFFFFFFFF
+
+#define XDPDMA_DESCRIPTOR_SRC_ADDR2_SHIFT			0
+#define XDPDMA_DESCRIPTOR_SRC_ADDR2_WIDTH			32
+#define XDPDMA_DESCRIPTOR_SRC_ADDR2_MASK			0XFFFFFFFF
+
+#define XDPDMA_DESCRIPTOR_SRC_ADDR3_SHIFT			0
+#define XDPDMA_DESCRIPTOR_SRC_ADDR3_WIDTH			32
+#define XDPDMA_DESCRIPTOR_SRC_ADDR3_MASK			0XFFFFFFFF
+
+#define XDPDMA_DESCRIPTOR_SRC_ADDR4_SHIFT			0
+#define XDPDMA_DESCRIPTOR_SRC_ADDR4_WIDTH			32
+#define XDPDMA_DESCRIPTOR_SRC_ADDR4_MASK			0XFFFFFFFF
+
+#define XDPDMA_DESCRIPTOR_SRC_ADDR5_SHIFT			0
+#define XDPDMA_DESCRIPTOR_SRC_ADDR5_WIDTH			32
+#define XDPDMA_DESCRIPTOR_SRC_ADDR5_MASK			0XFFFFFFFF
+
+#define XDPDMA_TRIGGER_EN					1
+#define XDPDMA_RETRIGGER_EN					2
+#define XDPDMA_TRIGGER_DONE					0
+#define XDPDMA_RETRIGGER_DONE					0
+/* @} */
+
+/******************* Macros (Inline Functions Definitions ********************/
+
+/** @name Register access macro definitions.
+  * @{
+  */
+#define XDpDma_In32 Xil_In32
+#define XDpDma_Out32 Xil_Out32
+/* @} */
+
+/******************************************************************************/
+/**
+ * This is a low-level function that reads from the specified register.
+ *
+ * @param	BaseAddress is the base address of the device.
+ * @param	RegOffset is the register offset to be read from.
+ *
+ * @return	The 32-bit value of the specified register.
+ *
+ * @note	C-style signature:
+ *		u32 XDpDma_ReadReg(u32 BaseAddress, u32 RegOffset
+ *
+*******************************************************************************/
+#define XDpDma_ReadReg(BaseAddress, RegOffset) \
+					XDpDma_In32((BaseAddress) + (RegOffset))
+
+/******************************************************************************/
+/**
+ * This is a low-level function that writes to the specified register.
+ *
+ * @param	BaseAddress is the base address of the device.
+ * @param	RegOffset is the register offset to write to.
+ * @param	Data is the 32-bit data to write to the specified register.
+ *
+ * @return	None.
+ *
+ * @note	C-style signature:
+ *		void XDpDma_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
+ *
+*******************************************************************************/
+#define XDpDma_WriteReg(BaseAddress, RegOffset, Data) \
+				XDpDma_Out32((BaseAddress) + (RegOffset), (Data))
+
+
+/******************************************************************************/
+/**
+ * This is a low-level function that writes to the specified register.
+ *
+ * @param	BaseAddress is the base address of the device.
+ * @param	RegOffset is the register offset to write to.
+ * @param	Data is the 32-bit data to write to the specified register.
+ * @param	Mask is the 32-bit field to which data is to be written
+ *
+ * @return	None.
+ *
+ * @note	C-style signature:
+ *		void XDpDma_ReadModifyWrite(u32 BaseAddress,
+ *							u32 RegOffset, u32 Data)
+ *
+*******************************************************************************/
+#define XDpDma_ReadModifyWrite(BaseAddress, RegOffset, Data, Mask) \
+				XDpDma_WriteReg((BaseAddress), (RegOffset), \
+				((XDpDma_ReadReg(BaseAddress, RegOffset) &  \
+				 ~(Mask)) | Data))
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* _XDPDMAHW_H_ */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/dpdma_v1_0/src/xdpdma_intr.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/dpdma_v1_0/src/xdpdma_intr.c
new file mode 100644
index 000000000..80b175db6
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/dpdma_v1_0/src/xdpdma_intr.c
@@ -0,0 +1,166 @@
+/*******************************************************************************
+ *
+ * Copyright (C) 2017 Xilinx, Inc.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * Use of the Software is limited solely to applications:
+ * (a) running on a Xilinx device, or
+ * (b) that interact with a Xilinx device through a bus or interconnect.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+ * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Except as contained in this notice, the name of the Xilinx shall not be used
+ * in advertising or otherwise to promote the sale, use or other dealings in
+ * this Software without prior written authorization from Xilinx.
+ *
+*******************************************************************************/
+/******************************************************************************/
+/**
+ *
+ * @file xdppsu_intr.c
+ *
+ * This file contains functions related to XDpPsu interrupt handling.
+ *
+ * @note	None.
+ *
+ * 
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -----------------------------------------------
+ * 1.0   aad  01/17/17 Initial release.
+ * 

+ *
+*******************************************************************************/
+
+/******************************* Include Files ********************************/
+#include "xdpdma.h"
+
+
+/*************************************************************************/
+/**
+ *
+ * This function enables the interrupts that are required.
+ *
+ * @param    InstancePtr is pointer to the instance of DPDMA
+ *
+ * @return   None.
+ *
+ * @note     None.
+ *
+ * **************************************************************************/
+void XDpDma_InterruptEnable(XDpDma *InstancePtr, u32 Mask)
+{
+	XDpDma_WriteReg(InstancePtr->Config.BaseAddr, XDPDMA_IEN, Mask);
+}
+
+/*************************************************************************/
+/**
+ *
+ * This function handles the interrupts generated by DPDMA
+ *
+ * @param    InstancePtr is pointer to the instance of the DPDMA
+ *
+ * @return   None.
+ *
+ * @note     None.
+ *
+ * **************************************************************************/
+void XDpDma_InterruptHandler(XDpDma *InstancePtr)
+{
+	u32 RegVal;
+	RegVal = XDpDma_ReadReg(InstancePtr->Config.BaseAddr,
+				XDPDMA_ISR);
+	if(RegVal & XDPDMA_ISR_VSYNC_INT_MASK) {
+		XDpDma_VSyncHandler(InstancePtr);
+	}
+
+	if(RegVal & XDPDMA_ISR_DSCR_DONE4_MASK) {
+		XDpDma_SetChannelState(InstancePtr, AudioChan0, XDPDMA_DISABLE);
+		InstancePtr->Audio[0].Current = NULL;
+		XDpDma_WriteReg(InstancePtr->Config.BaseAddr, XDPDMA_ISR,
+				XDPDMA_ISR_DSCR_DONE4_MASK);
+	}
+
+	if(RegVal & XDPDMA_ISR_DSCR_DONE5_MASK) {
+		XDpDma_SetChannelState(InstancePtr, AudioChan1, XDPDMA_DISABLE);
+		InstancePtr->Audio[1].Current = NULL;
+		XDpDma_WriteReg(InstancePtr->Config.BaseAddr, XDPDMA_ISR,
+				XDPDMA_ISR_DSCR_DONE5_MASK);
+	}
+}
+
+/*************************************************************************/
+/**
+ *
+ * This function handles frame new frames on VSync
+ *
+ * @param    InstancePtr is pointer to the instance of the driver.
+ *
+ * @return   None.
+ *
+ * @note     None.
+ *
+ * **************************************************************************/
+void XDpDma_VSyncHandler(XDpDma *InstancePtr)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+
+	/* Video Channel Trigger/Retrigger Handler */
+	if(InstancePtr->Video.TriggerStatus == XDPDMA_TRIGGER_EN) {
+		XDpDma_SetupChannel(InstancePtr, VideoChan);
+		XDpDma_SetChannelState(InstancePtr, VideoChan,
+				       XDPDMA_ENABLE);
+		XDpDma_Trigger(InstancePtr, VideoChan);
+	}
+	else if(InstancePtr->Video.TriggerStatus == XDPDMA_RETRIGGER_EN) {
+		XDpDma_SetupChannel(InstancePtr, VideoChan);
+		XDpDma_ReTrigger(InstancePtr, VideoChan);
+	}
+
+	/* Graphics Channel Trigger/Retrigger Handler */
+	if(InstancePtr->Gfx.TriggerStatus == XDPDMA_TRIGGER_EN) {
+		XDpDma_SetupChannel(InstancePtr, GraphicsChan);
+		XDpDma_SetChannelState(InstancePtr, GraphicsChan,
+				       XDPDMA_ENABLE);
+		XDpDma_Trigger(InstancePtr, GraphicsChan);
+	}
+	else if(InstancePtr->Gfx.TriggerStatus == XDPDMA_RETRIGGER_EN) {
+		XDpDma_SetupChannel(InstancePtr, GraphicsChan);
+		XDpDma_ReTrigger(InstancePtr, GraphicsChan);
+	}
+
+	/* Audio Channel 0 Trigger Handler */
+	if(InstancePtr->Audio[0].TriggerStatus == XDPDMA_TRIGGER_EN) {
+		XDpDma_SetupChannel(InstancePtr, AudioChan0);
+		XDpDma_SetChannelState(InstancePtr, AudioChan0,
+				       XDPDMA_ENABLE);
+		XDpDma_Trigger(InstancePtr, AudioChan0);
+	}
+
+	/* Audio Channel 1 Trigger Handler */
+	if(InstancePtr->Audio[1].TriggerStatus == XDPDMA_TRIGGER_EN) {
+		XDpDma_SetupChannel(InstancePtr, AudioChan1);
+		XDpDma_SetChannelState(InstancePtr, AudioChan1,
+				       XDPDMA_ENABLE);
+		XDpDma_Trigger(InstancePtr, AudioChan1);
+	}
+	/* Clear VSync Interrupt */
+	XDpDma_WriteReg(InstancePtr->Config.BaseAddr, XDPDMA_ISR,
+			XDPDMA_ISR_VSYNC_INT_MASK);
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/dpdma_v1_0/src/xdpdma_sinit.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/dpdma_v1_0/src/xdpdma_sinit.c
new file mode 100644
index 000000000..8f062681b
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/dpdma_v1_0/src/xdpdma_sinit.c
@@ -0,0 +1,96 @@
+/*******************************************************************************
+ *
+ * Copyright (C) 2017 Xilinx, Inc.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * Use of the Software is limited solely to applications:
+ * (a) running on a Xilinx device, or
+ * (b) that interact with a Xilinx device through a bus or interconnect.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+ * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Except as contained in this notice, the name of the Xilinx shall not be used
+ * in advertising or otherwise to promote the sale, use or other dealings in
+ * this Software without prior written authorization from Xilinx.
+ *
+*******************************************************************************/
+/******************************************************************************/
+/**
+ *
+ * @file xdpdma_sinit.c
+ * @addtogroup dpdma_v1_0
+ * @{
+ *
+ * This file contains static initialization methods for the XDpDma driver.
+ *
+ * @note	None.
+ *
+ * 
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -----------------------------------------------
+ * 1.0   aad  01/20/15 Initial release.
+ * 

+ *
+*******************************************************************************/
+
+/******************************* Include Files ********************************/
+
+#include "xdpdma.h"
+#include "xparameters.h"
+
+/*************************** Variable Declarations ****************************/
+
+/**
+ * A table of configuration structures containing the configuration information
+ * for each DisplayPort TX core in the system.
+ */
+extern XDpDma_Config XDpDma_ConfigTable[XPAR_XDPDMA_NUM_INSTANCES];
+
+/**************************** Function Definitions ****************************/
+
+/******************************************************************************/
+/**
+ * This function looks for the device configuration based on the unique device
+ * ID. The table XDpDma_ConfigTable[] contains the configuration information for
+ * each device in the system.
+ *
+ * @param	DeviceId is the unique device ID of the device being looked up.
+ *
+ * @return	A pointer to the configuration table entry corresponding to the
+ *		given device ID, or NULL if no match is found.
+ *
+ * @note	None.
+ *
+*******************************************************************************/
+XDpDma_Config *XDpDma_LookupConfig(u16 DeviceId)
+{
+	XDpDma_Config *CfgPtr;
+	u32 Index;
+
+	for (Index = 0; Index < XPAR_XDPDMA_NUM_INSTANCES; Index++) {
+		if (XDpDma_ConfigTable[Index].DeviceId == DeviceId) {
+			CfgPtr = &XDpDma_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return CfgPtr;
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_3/src/Makefile b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_7/src/Makefile
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_3/src/Makefile
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_7/src/Makefile
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v3_2/src/xemacps.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_7/src/xemacps.c
similarity index 98%
rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v3_2/src/xemacps.c
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_7/src/xemacps.c
index 26df03c3d..c013c4946 100644
--- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v3_2/src/xemacps.c
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_7/src/xemacps.c
@@ -33,7 +33,7 @@
 /**
 *
 * @file xemacps.c
-* @addtogroup emacps_v3_1
+* @addtogroup emacps_v3_7
 * @{
 *
 * The XEmacPs driver. Functions in this file are the minimum required functions
@@ -52,6 +52,8 @@
 *                    Disable extended mode. Perform all 64 bit changes under
 *                    check for arch64.
 * 3.1  hk   08/10/15 Update upper 32 bit tx and rx queue ptr registers
+* 3.5  hk   08/14/17 Update cache coherency information of the interface in
+*                    its config structure.
 *
 * 

 ******************************************************************************/
@@ -107,6 +109,7 @@ LONG XEmacPs_CfgInitialize(XEmacPs *InstancePtr, XEmacPs_Config * CfgPtr,
 	/* Set device base address and ID */
 	InstancePtr->Config.DeviceId = CfgPtr->DeviceId;
 	InstancePtr->Config.BaseAddress = EffectiveAddress;
+	InstancePtr->Config.IsCacheCoherent = CfgPtr->IsCacheCoherent;
 
 	/* Set callbacks to an initial stub routine */
 	InstancePtr->SendHandler = ((XEmacPs_Handler)((void*)XEmacPs_StubHandler));
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_3/src/xemacps.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_7/src/xemacps.h
similarity index 97%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_3/src/xemacps.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_7/src/xemacps.h
index f12092bec..6d4b15b24 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_3/src/xemacps.h
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_7/src/xemacps.h
@@ -33,7 +33,7 @@
 /**
  *
  * @file xemacps.h
-* @addtogroup emacps_v3_1
+* @addtogroup emacps_v3_7
 * @{
 * @details
  *
@@ -316,6 +316,21 @@
  *                     there is no error. CR# 869403
  *            08/10/15 Update upper 32 bit tx and rx queue ptr registers.
  * 3.2   hk   02/22/16 Added SGMII support for Zynq Ultrascale+ MPSoC.
+ * 3.4   ms   01/23/17 Modified xil_printf statement in main function for all
+ *                     examples to ensure that "Successfully ran" and "Failed"
+ *                     strings are available in all examples. This is a fix
+ *                     for CR-965028.
+ *       ms   03/17/17 Modified text file in examples folder for doxygen
+ *                     generation.
+ *       ms   04/05/17 Added tabspace for return statements in functions of
+ *                     xemacps_ieee1588_example.c for proper documentation
+ *                     while generating doxygen.
+ * 3.5   hk   08/14/17 Update cache coherency information of the interface in
+ *                     its config structure.
+ * 3.6   rb   09/08/17 HwCnt variable (in XEmacPs_BdRing structure) is
+ *		       changed to volatile.
+ *		       Add API XEmacPs_BdRingPtrReset() to reset pointers
+ *
  * 

  *
  ****************************************************************************/
@@ -513,6 +528,8 @@ typedef void (*XEmacPs_ErrHandler) (void *CallBackRef, u8 Direction,
 typedef struct {
 	u16 DeviceId;	/**< Unique ID  of device */
 	UINTPTR BaseAddress;/**< Physical base address of IPIF registers */
+	u8 IsCacheCoherent; /**< Applicable only to A53 in EL1 mode;
+				* describes whether Cache Coherent or not */
 } XEmacPs_Config;
 
 
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v3_2/src/xemacps_bd.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_7/src/xemacps_bd.h
similarity index 99%
rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v3_2/src/xemacps_bd.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_7/src/xemacps_bd.h
index 52c5f7e7e..83f9a87fc 100644
--- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v3_2/src/xemacps_bd.h
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_7/src/xemacps_bd.h
@@ -33,7 +33,7 @@
 /**
  *
  * @file xemacps_bd.h
-* @addtogroup emacps_v3_1
+* @addtogroup emacps_v3_7
 * @{
  *
  * This header provides operations to manage buffer descriptors in support
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_3/src/xemacps_bdring.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_7/src/xemacps_bdring.c
similarity index 97%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_3/src/xemacps_bdring.c
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_7/src/xemacps_bdring.c
index d837e1df1..3536873dc 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_3/src/xemacps_bdring.c
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_7/src/xemacps_bdring.c
@@ -33,7 +33,7 @@
 /**
 *
 * @file xemacps_bdring.c
-* @addtogroup emacps_v3_1
+* @addtogroup emacps_v3_7
 * @{
 *
 * This file implements buffer descriptor ring related functions.
@@ -57,6 +57,8 @@
 *		      from uncached area. Fix for CR #663885.
 * 2.1   srt  07/15/14 Add support for Zynq Ultrascale Mp architecture.
 * 3.0   kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.6   rb   09/08/17 Add XEmacPs_BdRingPtrReset() API to reset BD ring
+* 		      pointers
 *
 *
******************************************************************************/ @@ -505,7 +507,7 @@ LONG XEmacPs_BdRingUnAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd, XEmacPs_Bd * BdSetPtr) { LONG Status; - (void *)BdSetPtr; + (void) BdSetPtr; Xil_AssertNonvoid(RingPtr != NULL); Xil_AssertNonvoid(BdSetPtr != NULL); @@ -1072,4 +1074,29 @@ static void XEmacPs_BdSetTxWrap(UINTPTR BdPtr) *TempPtr = DataValueTx; } } + +/*****************************************************************************/ +/** + * Reset BD ring head and tail pointers. + * + * @param RingPtr is the instance to be worked on. + * @param VirtAddr is the virtual base address of the user memory region. + * + * @note + * Should be called after XEmacPs_Stop() + * + * @note + * C-style signature: + * void XEmacPs_BdRingPtrReset(XEmacPs_BdRing * RingPtr, void *virtaddrloc) + * + *****************************************************************************/ +void XEmacPs_BdRingPtrReset(XEmacPs_BdRing * RingPtr, void *virtaddrloc) +{ + RingPtr->FreeHead = virtaddrloc; + RingPtr->PreHead = virtaddrloc; + RingPtr->HwHead = virtaddrloc; + RingPtr->HwTail = virtaddrloc; + RingPtr->PostHead = virtaddrloc; +} + /** @} */ diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_bdring.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_7/src/xemacps_bdring.h similarity index 97% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_bdring.h rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_7/src/xemacps_bdring.h index de78cf28f..b89e89885 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_bdring.h +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_7/src/xemacps_bdring.h @@ -33,7 +33,7 @@ /** * * @file xemacps_bdring.h -* @addtogroup emacps_v3_1 +* @addtogroup emacps_v3_7 * @{ * * The Xiline EmacPs Buffer Descriptor ring driver. This is part of EmacPs @@ -47,6 +47,8 @@ * 1.00a wsy 01/10/10 First release * 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp architecture. * 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance. +* 3.6 rb 09/08/17 HwCnt variable (in XEmacPs_BdRing structure) is +* changed to volatile. * * * @@ -81,7 +83,7 @@ typedef struct { XEmacPs_Bd *BdaRestart; /**< BDA to load when channel is started */ - u32 HwCnt; /**< Number of BDs in work group */ + volatile u32 HwCnt; /**< Number of BDs in work group */ u32 PreCnt; /**< Number of BDs in pre-work group */ u32 FreeCnt; /**< Number of allocatable BDs in the free group */ u32 PostCnt; /**< Number of BDs in post-work group */ @@ -228,6 +230,7 @@ u32 XEmacPs_BdRingFromHwRx(XEmacPs_BdRing * RingPtr, u32 BdLimit, XEmacPs_Bd ** BdSetPtr); LONG XEmacPs_BdRingCheck(XEmacPs_BdRing * RingPtr, u8 Direction); +void XEmacPs_BdRingPtrReset(XEmacPs_BdRing * RingPtr, void *virtaddrloc); #ifdef __cplusplus } diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_control.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_7/src/xemacps_control.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_control.c rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_7/src/xemacps_control.c index f52451a8c..8217a4521 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_control.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_7/src/xemacps_control.c @@ -33,7 +33,7 @@ /** * * @file xemacps_control.c -* @addtogroup emacps_v3_1 +* @addtogroup emacps_v3_7 * @{ * * Functions in this file implement general purpose command and control related diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_g.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_7/src/xemacps_g.c similarity index 87% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_g.c rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_7/src/xemacps_g.c index db734b924..e58610f57 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_g.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_7/src/xemacps_g.c @@ -5,7 +5,7 @@ * Version: * DO NOT EDIT. * -* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.* +* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.* *Permission is hereby granted, free of charge, to any person obtaining a copy *of this software and associated documentation files (the Software), to deal *in the Software without restriction, including without limitation the rights @@ -44,11 +44,12 @@ * The configuration table for devices */ -XEmacPs_Config XEmacPs_ConfigTable[] = +XEmacPs_Config XEmacPs_ConfigTable[XPAR_XEMACPS_NUM_INSTANCES] = { { XPAR_PSU_ETHERNET_3_DEVICE_ID, - XPAR_PSU_ETHERNET_3_BASEADDR + XPAR_PSU_ETHERNET_3_BASEADDR, + XPAR_PSU_ETHERNET_3_IS_CACHE_COHERENT } }; diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_3/src/xemacps_hw.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_7/src/xemacps_hw.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_3/src/xemacps_hw.c rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_7/src/xemacps_hw.c index daba38397..00e79a58d 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_3/src/xemacps_hw.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_7/src/xemacps_hw.c @@ -33,7 +33,7 @@ /** * * @file xemacps_hw.c -* @addtogroup emacps_v3_1 +* @addtogroup emacps_v3_7 * @{ * * This file contains the implementation of the ethernet interface reset sequence diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_hw.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_7/src/xemacps_hw.h similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_hw.h rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_7/src/xemacps_hw.h index 953cc6265..e535470c2 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_hw.h +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_7/src/xemacps_hw.h @@ -33,7 +33,7 @@ /** * * @file xemacps_hw.h -* @addtogroup emacps_v3_1 +* @addtogroup emacps_v3_7 * @{ * * This header file contains identifiers and low-level driver functions (or diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v3_2/src/xemacps_intr.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_7/src/xemacps_intr.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v3_2/src/xemacps_intr.c rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_7/src/xemacps_intr.c index 59636c4ef..9c355a163 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v3_2/src/xemacps_intr.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_7/src/xemacps_intr.c @@ -33,7 +33,7 @@ /** * * @file xemacps_intr.c -* @addtogroup emacps_v3_1 +* @addtogroup emacps_v3_7 * @{ * * Functions in this file implement general purpose interrupt processing related diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_sinit.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_7/src/xemacps_sinit.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_sinit.c rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_7/src/xemacps_sinit.c index 1bc5b3b19..e2d2078af 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_sinit.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_7/src/xemacps_sinit.c @@ -33,7 +33,7 @@ /** * * @file xemacps_sinit.c -* @addtogroup emacps_v3_1 +* @addtogroup emacps_v3_7 * @{ * * This file contains lookup method by device ID when success, it returns diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_1/src/Makefile b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_3/src/Makefile similarity index 100% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_1/src/Makefile rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_3/src/Makefile diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_3/src/xgpiops.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops.c rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_3/src/xgpiops.c index 90eedb87d..7b6fe2e46 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_3/src/xgpiops.c @@ -33,7 +33,7 @@ /** * * @file xgpiops.c -* @addtogroup gpiops_v3_1 +* @addtogroup gpiops_v3_3 * @{ * * The XGpioPs driver. Functions in this file are the minimum required functions diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_3/src/xgpiops.h similarity index 94% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops.h rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_3/src/xgpiops.h index 102615572..fda562d91 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops.h +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_3/src/xgpiops.h @@ -1,3 +1,4 @@ + /****************************************************************************** * * Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. @@ -33,7 +34,7 @@ /** * * @file xgpiops.h -* @addtogroup gpiops_v3_1 +* @addtogroup gpiops_v3_3 * @{ * @details * @@ -97,7 +98,15 @@ * passed to APIs. CR# 822636 * 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance. * 3.1 kvn 04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980. -* +* ms 03/17/17 Added readme.txt file in examples folder for doxygen +* generation. +* ms 04/05/17 Added tabspace for return statements in functions of +* gpiops examples for proper documentation while +* generating doxygen. +* 3.3 ms 04/17/17 Added notes about gpio input and output pin description +* for zcu102 and zc702 boards in polled and interrupt +* example, configured Interrupt pin to input pin for +* proper functioning of interrupt example. * * ******************************************************************************/ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_1/src/xgpiops_g.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_3/src/xgpiops_g.c similarity index 90% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_1/src/xgpiops_g.c rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_3/src/xgpiops_g.c index 38a5b9355..a518a700e 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_1/src/xgpiops_g.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_3/src/xgpiops_g.c @@ -5,7 +5,7 @@ * Version: * DO NOT EDIT. * -* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.* +* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.* *Permission is hereby granted, free of charge, to any person obtaining a copy *of this software and associated documentation files (the Software), to deal *in the Software without restriction, including without limitation the rights @@ -44,7 +44,7 @@ * The configuration table for devices */ -XGpioPs_Config XGpioPs_ConfigTable[] = +XGpioPs_Config XGpioPs_ConfigTable[XPAR_XGPIOPS_NUM_INSTANCES] = { { XPAR_PSU_GPIO_0_DEVICE_ID, diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops_hw.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_3/src/xgpiops_hw.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops_hw.c rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_3/src/xgpiops_hw.c index d7a5e00f0..8961c4287 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops_hw.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_3/src/xgpiops_hw.c @@ -33,7 +33,7 @@ /** * * @file xgpiops_hw.c -* @addtogroup gpiops_v3_1 +* @addtogroup gpiops_v3_3 * @{ * * This file contains low level GPIO functions. diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops_hw.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_3/src/xgpiops_hw.h similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops_hw.h rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_3/src/xgpiops_hw.h index 81e8d6a9f..ff0190675 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops_hw.h +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_3/src/xgpiops_hw.h @@ -33,7 +33,7 @@ /** * * @file xgpiops_hw.h -* @addtogroup gpiops_v3_1 +* @addtogroup gpiops_v3_3 * @{ * * This header file contains the identifiers and basic driver functions (or diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_1/src/xgpiops_intr.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_3/src/xgpiops_intr.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_1/src/xgpiops_intr.c rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_3/src/xgpiops_intr.c index c07381be6..a8b0a5626 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_1/src/xgpiops_intr.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_3/src/xgpiops_intr.c @@ -33,7 +33,7 @@ /** * * @file xgpiops_intr.c -* @addtogroup gpiops_v3_1 +* @addtogroup gpiops_v3_3 * @{ * * This file contains functions related to GPIO interrupt handling. @@ -722,7 +722,7 @@ void XGpioPs_IntrHandler(XGpioPs *InstancePtr) ******************************************************************************/ void StubHandler(void *CallBackRef, u32 Bank, u32 Status) { - (void*) CallBackRef; + (void) CallBackRef; (void) Bank; (void) Status; diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops_selftest.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_3/src/xgpiops_selftest.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops_selftest.c rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_3/src/xgpiops_selftest.c index da1973a2d..378524c14 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops_selftest.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_3/src/xgpiops_selftest.c @@ -33,7 +33,7 @@ /** * * @file xgpiops_selftest.c -* @addtogroup gpiops_v3_1 +* @addtogroup gpiops_v3_3 * @{ * * This file contains a diagnostic self-test function for the XGpioPs driver. diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops_sinit.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_3/src/xgpiops_sinit.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops_sinit.c rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_3/src/xgpiops_sinit.c index 2ca008373..4cc0c390f 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops_sinit.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_3/src/xgpiops_sinit.c @@ -33,7 +33,7 @@ /** * * @file xgpiops_sinit.c -* @addtogroup gpiops_v3_1 +* @addtogroup gpiops_v3_3 * @{ * * This file contains the implementation of the XGpioPs driver's static diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_4/src/Makefile b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_6/src/Makefile similarity index 100% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_4/src/Makefile rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_6/src/Makefile diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_4/src/xiicps.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_6/src/xiicps.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_4/src/xiicps.c rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_6/src/xiicps.c index 1c6819152..4f2b592e7 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_4/src/xiicps.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_6/src/xiicps.c @@ -33,7 +33,7 @@ /** * * @file xiicps.c -* @addtogroup iicps_v3_0 +* @addtogroup iicps_v3_5 * @{ * * Contains implementation of required functions for the XIicPs driver. diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_6/src/xiicps.h similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps.h rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_6/src/xiicps.h index b26193486..cc837a14c 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps.h +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_6/src/xiicps.h @@ -33,7 +33,7 @@ /** * * @file xiicps.h -* @addtogroup iicps_v3_0 +* @addtogroup iicps_v3_5 * @{ * @details * @@ -184,6 +184,8 @@ * 02/18/15 Implemented larger data transfer using repeated start * in Zynq UltraScale MP. * 3.3 kvn 05/05/16 Modified latest code for MISRA-C:2012 Compliance. +* ms 03/17/17 Added readme.txt file in examples folder for doxygen +* generation. * * * diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_4/src/xiicps_g.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_6/src/xiicps_g.c similarity index 91% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_4/src/xiicps_g.c rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_6/src/xiicps_g.c index f449e0ed6..1a469d08c 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_4/src/xiicps_g.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_6/src/xiicps_g.c @@ -5,7 +5,7 @@ * Version: * DO NOT EDIT. * -* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.* +* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.* *Permission is hereby granted, free of charge, to any person obtaining a copy *of this software and associated documentation files (the Software), to deal *in the Software without restriction, including without limitation the rights @@ -44,7 +44,7 @@ * The configuration table for devices */ -XIicPs_Config XIicPs_ConfigTable[] = +XIicPs_Config XIicPs_ConfigTable[XPAR_XIICPS_NUM_INSTANCES] = { { XPAR_PSU_I2C_0_DEVICE_ID, diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_4/src/xiicps_hw.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_6/src/xiicps_hw.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_4/src/xiicps_hw.c rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_6/src/xiicps_hw.c index a1dba8e62..2d85e1436 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_4/src/xiicps_hw.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_6/src/xiicps_hw.c @@ -33,7 +33,7 @@ /** * * @file xiicps_hw.c -* @addtogroup iicps_v3_0 +* @addtogroup iicps_v3_5 * @{ * * Contains implementation of required functions for providing the reset sequence diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_4/src/xiicps_hw.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_6/src/xiicps_hw.h similarity index 99% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_4/src/xiicps_hw.h rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_6/src/xiicps_hw.h index 3b00cf8b1..d1eee82f2 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_4/src/xiicps_hw.h +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_6/src/xiicps_hw.h @@ -33,7 +33,7 @@ /** * * @file xiicps_hw.h -* @addtogroup iicps_v3_0 +* @addtogroup iicps_v3_5 * @{ * * This header file contains the hardware definition for an IIC device. diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_4/src/xiicps_intr.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_6/src/xiicps_intr.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_4/src/xiicps_intr.c rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_6/src/xiicps_intr.c index 5231049c7..7f385918f 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_4/src/xiicps_intr.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_6/src/xiicps_intr.c @@ -33,7 +33,7 @@ /** * * @file xiicps_intr.c -* @addtogroup iicps_v3_0 +* @addtogroup iicps_v3_5 * @{ * * Contains functions of the XIicPs driver for interrupt-driven transfers. diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_4/src/xiicps_master.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_6/src/xiicps_master.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_4/src/xiicps_master.c rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_6/src/xiicps_master.c index 7824d86b6..faa852826 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_4/src/xiicps_master.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_6/src/xiicps_master.c @@ -33,7 +33,7 @@ /** * * @file xiicps_master.c -* @addtogroup iicps_v3_0 +* @addtogroup iicps_v3_5 * @{ * * Handles master mode transfers. @@ -63,7 +63,8 @@ * 02/18/15 Implemented larger data transfer using repeated start * in Zynq UltraScale MP. * 3.3 kvn 05/05/16 Modified latest code for MISRA-C:2012 Compliance. -* +* 3.6 ask 09/03/18 In XIicPs_MasterRecvPolled, set transfer size register +* before slave address. Fix for CR996440. * * ******************************************************************************/ @@ -424,7 +425,6 @@ s32 XIicPs_MasterRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr, IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET); XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg); - XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, SlaveAddr); /* * Set up the transfer size register so the slave knows how much @@ -440,6 +440,9 @@ s32 XIicPs_MasterRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr, ByteCountVar); } + + XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, SlaveAddr); + /* * Intrs keeps all the error-related interrupts. */ @@ -632,6 +635,11 @@ void XIicPs_DisableSlaveMonitor(XIicPs *InstancePtr) XIicPs_ReadReg(BaseAddr, XIICPS_CR_OFFSET) & (~XIICPS_CR_SLVMON_MASK)); + /* + * wait for slv monitor control bit to be clear + */ + while (XIicPs_ReadReg(BaseAddr, XIICPS_CR_OFFSET) + & XIICPS_CR_SLVMON_MASK); /* * Clear interrupt flag for slave monitor interrupt. */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_4/src/xiicps_options.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_6/src/xiicps_options.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_4/src/xiicps_options.c rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_6/src/xiicps_options.c index 1ebd78673..c9237dbb0 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_4/src/xiicps_options.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_6/src/xiicps_options.c @@ -33,7 +33,7 @@ /** * * @file xiicps_options.c -* @addtogroup iicps_v3_0 +* @addtogroup iicps_v3_5 * @{ * * Contains functions for the configuration of the XIccPs driver. diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_selftest.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_6/src/xiicps_selftest.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_selftest.c rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_6/src/xiicps_selftest.c index dd57a1a51..31e02b56f 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_selftest.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_6/src/xiicps_selftest.c @@ -33,7 +33,7 @@ /** * * @file xiicps_selftest.c -* @addtogroup iicps_v3_0 +* @addtogroup iicps_v3_5 * @{ * * This component contains the implementation of selftest functions for the diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_4/src/xiicps_sinit.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_6/src/xiicps_sinit.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_4/src/xiicps_sinit.c rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_6/src/xiicps_sinit.c index 7d7dadaa8..d8fbc4cd5 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_4/src/xiicps_sinit.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_6/src/xiicps_sinit.c @@ -33,7 +33,7 @@ /** * * @file xiicps_sinit.c -* @addtogroup iicps_v3_0 +* @addtogroup iicps_v3_5 * @{ * * The implementation of the XIicPs component's static initialization diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_slave.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_6/src/xiicps_slave.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_slave.c rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_6/src/xiicps_slave.c index fef640b77..adc40a435 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_slave.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_6/src/xiicps_slave.c @@ -32,7 +32,7 @@ /*****************************************************************************/ /** * @file xiicps_slave.c -* @addtogroup iicps_v3_0 +* @addtogroup iicps_v3_5 * @{ * * Handles slave transfers diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ipipsu_v2_1/src/Makefile b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ipipsu_v2_3/src/Makefile similarity index 100% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ipipsu_v2_1/src/Makefile rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ipipsu_v2_3/src/Makefile diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ipipsu_v2_1/src/xipipsu.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ipipsu_v2_3/src/xipipsu.c similarity index 87% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ipipsu_v2_1/src/xipipsu.c rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ipipsu_v2_3/src/xipipsu.c index 7c9d98ab0..06d9ced3c 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ipipsu_v2_1/src/xipipsu.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ipipsu_v2_3/src/xipipsu.c @@ -33,7 +33,7 @@ /** * * @file xipipsu.c -* @addtogroup ipipsu_v1_0 +* @addtogroup ipipsu_v2_3 * @{ * * This file contains the implementation of the interface functions for XIpiPsu @@ -48,6 +48,7 @@ * 2.0 mjr 01/22/16 Fixed response buffer address * calculation. CR# 932582. * 2.1 kvn 05/05/16 Modified code for MISRA-C:2012 Compliance +* 2.2 kvn 02/17/17 Add support for updating ConfigTable at run time * * *****************************************************************************/ @@ -56,6 +57,9 @@ #include "xipipsu.h" #include "xipipsu_hw.h" +/************************** Variable Definitions *****************************/ +extern XIpiPsu_Config XIpiPsu_ConfigTable[XPAR_XIPIPSU_NUM_INSTANCES]; + /****************************************************************************/ /** * Initialize the Instance pointer based on a given Config Pointer @@ -350,4 +354,39 @@ XStatus XIpiPsu_WriteMessage(XIpiPsu *InstancePtr, u32 DestCpuMask, u32 *MsgPtr, return Status; } + +/*****************************************************************************/ +/** +* +* Set up the device configuration based on the unique device ID. A table +* contains the configuration info for each device in the system. +* +* @param DeviceId contains the ID of the device to set up the +* configuration for. +* +* @return A pointer to the device configuration for the specified +* device ID. See xipipsu.h for the definition of +* XIpiPsu_Config. +* +* @note This is for safety use case where in this function has to +* be called before CfgInitialize. So that driver will be +* initialized with the provided configuration. For non-safe +* use cases, this is not needed. +* +******************************************************************************/ +void XIpiPsu_SetConfigTable(u32 DeviceId, XIpiPsu_Config *ConfigTblPtr) +{ + u32 Index; + + Xil_AssertVoid(ConfigTblPtr != NULL); + + for (Index = 0U; Index < XPAR_XIPIPSU_NUM_INSTANCES; Index++) { + if (XIpiPsu_ConfigTable[Index].DeviceId == DeviceId) { + XIpiPsu_ConfigTable[Index].BaseAddress = ConfigTblPtr->BaseAddress; + XIpiPsu_ConfigTable[Index].BitMask = ConfigTblPtr->BitMask; + XIpiPsu_ConfigTable[Index].BufferIndex = ConfigTblPtr->BufferIndex; + XIpiPsu_ConfigTable[Index].IntId = ConfigTblPtr->IntId; + } + } +} /** @} */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ipipsu_v2_1/src/xipipsu.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ipipsu_v2_3/src/xipipsu.h similarity index 92% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ipipsu_v2_1/src/xipipsu.h rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ipipsu_v2_3/src/xipipsu.h index 0253b9a68..83701f46e 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ipipsu_v2_1/src/xipipsu.h +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ipipsu_v2_3/src/xipipsu.h @@ -32,7 +32,7 @@ /*****************************************************************************/ /** * @file xipipsu.h -* @addtogroup ipipsu_v1_0 +* @addtogroup ipipsu_v2_3 * @{ * @details * @@ -76,7 +76,23 @@ * @note XIpiPsu_Reset can be used at startup to clear the status and * disable all sources * - */ + * 
+ * MODIFICATION HISTORY:
+ *
+ * Ver  Who Date     Changes
+ * ---- --- -------- --------------------------------------------------
+ * 2.2  ms  01/23/17 Modified xil_printf statement in main function for all
+ *                    examples to ensure that "Successfully ran" and "Failed"
+ *                    strings are available in all examples. This is a fix
+ *                    for CR-965028.
+ *  	kvn 02/17/17  Add support for updating ConfigTable at run time
+ *      ms  03/17/17  Added readme.txt file in examples folder for doxygen
+ *                    generation.
+ * 2.3  ms  04/11/17  Modified tcl file to add suffix U for all macro
+ *                    definitions of ipipsu in xparameters.h
+ *
+ * + *****************************************************************************/ /*****************************************************************************/ #ifndef XIPIPSU_H_ #define XIPIPSU_H_ @@ -276,6 +292,7 @@ XStatus XIpiPsu_ReadMessage(XIpiPsu *InstancePtr, u32 SrcCpuMask, u32 *MsgPtr, XStatus XIpiPsu_WriteMessage(XIpiPsu *InstancePtr, u32 DestCpuMask, u32 *MsgPtr, u32 MsgLength, u8 BufferType); +void XIpiPsu_SetConfigTable(u32 DeviceId, XIpiPsu_Config *ConfigTblPtr); #endif /* XIPIPSU_H_ */ /** @} */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ipipsu_v2_1/src/xipipsu_g.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ipipsu_v2_3/src/xipipsu_g.c similarity index 83% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ipipsu_v2_1/src/xipipsu_g.c rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ipipsu_v2_3/src/xipipsu_g.c index af7941c14..635069b52 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ipipsu_v2_1/src/xipipsu_g.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ipipsu_v2_3/src/xipipsu_g.c @@ -5,7 +5,7 @@ * Version: * DO NOT EDIT. * -* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.* +* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.* *Permission is hereby granted, free of charge, to any person obtaining a copy *of this software and associated documentation files (the Software), to deal *in the Software without restriction, including without limitation the rights @@ -44,7 +44,7 @@ * The configuration table for devices */ -XIpiPsu_Config XIpiPsu_ConfigTable[] = +XIpiPsu_Config XIpiPsu_ConfigTable[XPAR_XIPIPSU_NUM_INSTANCES] = { { @@ -83,22 +83,6 @@ XIpiPsu_Config XIpiPsu_ConfigTable[] = { XPAR_PSU_IPI_6_BIT_MASK, XPAR_PSU_IPI_6_BUFFER_INDEX - }, - { - XPAR_PSU_IPI_7_BIT_MASK, - XPAR_PSU_IPI_7_BUFFER_INDEX - }, - { - XPAR_PSU_IPI_8_BIT_MASK, - XPAR_PSU_IPI_8_BUFFER_INDEX - }, - { - XPAR_PSU_IPI_9_BIT_MASK, - XPAR_PSU_IPI_9_BUFFER_INDEX - }, - { - XPAR_PSU_IPI_10_BIT_MASK, - XPAR_PSU_IPI_10_BUFFER_INDEX } } } diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ipipsu_v2_1/src/xipipsu_hw.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ipipsu_v2_3/src/xipipsu_hw.h similarity index 95% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ipipsu_v2_1/src/xipipsu_hw.h rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ipipsu_v2_3/src/xipipsu_hw.h index b4c02b6e1..5a3202192 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ipipsu_v2_1/src/xipipsu_hw.h +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ipipsu_v2_3/src/xipipsu_hw.h @@ -32,7 +32,7 @@ /** * * @file xipipsu_hw.h -* @addtogroup ipipsu_v1_0 +* @addtogroup ipipsu_v2_3 * @{ * * This file contains macro definitions for low level HW related params @@ -62,8 +62,8 @@ #define XIPIPSU_BUFFER_OFFSET_TARGET (32U * 2U) #define XIPIPSU_BUFFER_OFFSET_RESPONSE (32U) -/* Max Number of IPI slots on the device */ -#define XIPIPSU_MAX_TARGETS 11 +/* Number of IPI slots enabled on the device */ +#define XIPIPSU_MAX_TARGETS XPAR_XIPIPSU_NUM_TARGETS /* Register Offsets for each member of IPI Register Set */ #define XIPIPSU_TRIG_OFFSET 0x00U diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_1/src/xipipsu_sinit.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ipipsu_v2_3/src/xipipsu_sinit.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_1/src/xipipsu_sinit.c rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ipipsu_v2_3/src/xipipsu_sinit.c index ae0900498..6f52a63e0 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_1/src/xipipsu_sinit.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ipipsu_v2_3/src/xipipsu_sinit.c @@ -32,7 +32,7 @@ /** * * @file xipipsu_sinit.c -* @addtogroup ipipsu_v1_0 +* @addtogroup ipipsu_v2_3 * @{ * * The implementation of the XIpiPsu component's static initialization diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/qspipsu_v1_3/src/Makefile b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/qspipsu_v1_7/src/Makefile similarity index 100% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/qspipsu_v1_3/src/Makefile rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/qspipsu_v1_7/src/Makefile diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_3/src/xqspipsu.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/qspipsu_v1_7/src/xqspipsu.c similarity index 96% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_3/src/xqspipsu.c rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/qspipsu_v1_7/src/xqspipsu.c index 93fa53f75..60eee53ea 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_3/src/xqspipsu.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/qspipsu_v1_7/src/xqspipsu.c @@ -33,7 +33,7 @@ /** * * @file xqspipsu.c -* @addtogroup qspipsu_v1_0 +* @addtogroup qspipsu_v1_7 * @{ * * This file implements the functions required to use the QSPIPSU hardware to @@ -60,6 +60,10 @@ * 1.3 nsk 09/16/16 Update PollData and PollTimeout support for dual * parallel configurations, modified XQspiPsu_PollData() * and XQspiPsu_Create_PollConfigData() +* 1,5 nsk 08/14/17 Added CCI support +* 1.7 tjs 01/16/18 Removed the check for DMA MSB to be written. (CR#992560) +* 1.7 tjs 01/17/18 Added a support to toggle WP pin of the flash. +* 1.7 tjs 03/14/18 Added support in EL1 NS mode (CR#974882) * * * @@ -150,6 +154,7 @@ s32 XQspiPsu_CfgInitialize(XQspiPsu *InstancePtr, XQspiPsu_Config *ConfigPtr, InstancePtr->StatusHandler = StubStatusHandler; InstancePtr->Config.BusWidth = ConfigPtr->BusWidth; InstancePtr->Config.InputClockHz = ConfigPtr->InputClockHz; + InstancePtr->Config.IsCacheCoherent = ConfigPtr->IsCacheCoherent; /* Other instance variable initializations */ InstancePtr->SendBufferPtr = NULL; InstancePtr->RecvBufferPtr = NULL; @@ -928,7 +933,7 @@ void XQspiPsu_SetStatusHandler(XQspiPsu *InstancePtr, void *CallBackRef, static void StubStatusHandler(void *CallBackRef, u32 StatusEvent, u32 ByteCount) { - (void *) CallBackRef; + (void) CallBackRef; (void) StatusEvent; (void) ByteCount; @@ -1136,13 +1141,13 @@ static inline void XQspiPsu_SetupRxDma(XQspiPsu *InstancePtr, XQSPIPSU_QSPIDMA_DST_ADDR_OFFSET, (u32)AddrTemp); - AddrTemp = AddrTemp >> 32; - if ((AddrTemp & 0xFFFU) != FALSE) { - XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress, - XQSPIPSU_QSPIDMA_DST_ADDR_MSB_OFFSET, - (u32)AddrTemp & - XQSPIPSU_QSPIDMA_DST_ADDR_MSB_MASK); - } +#ifdef __aarch64__ + AddrTemp = (u64)((INTPTR)(Msg->RxBfrPtr) >> 32); + XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress, + XQSPIPSU_QSPIDMA_DST_ADDR_MSB_OFFSET, + (u32)AddrTemp & + XQSPIPSU_QSPIDMA_DST_ADDR_MSB_MASK); +#endif Remainder = InstancePtr->RxBytes % 4; DmaRxBytes = InstancePtr->RxBytes; @@ -1151,8 +1156,10 @@ static inline void XQspiPsu_SetupRxDma(XQspiPsu *InstancePtr, DmaRxBytes = InstancePtr->RxBytes - Remainder; Msg->ByteCount = (u32)DmaRxBytes; } - - Xil_DCacheInvalidateRange((INTPTR)InstancePtr->RecvBufferPtr, Msg->ByteCount); + if (InstancePtr->Config.IsCacheCoherent == 0) { + Xil_DCacheInvalidateRange((INTPTR)InstancePtr->RecvBufferPtr, + Msg->ByteCount); + } /* Write no. of words to DMA DST SIZE */ XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress, @@ -1511,4 +1518,37 @@ static inline u32 XQspiPsu_Create_PollConfigData(XQspiPsu *QspiPsuPtr, & XQSPIPSU_POLL_CFG_DATA_VALUE_MASK); return ConfigData; } + +/*****************************************************************************/ +/** +* @brief +* This API enables/ disables Write Protect pin on the flash parts. +* +* @param QspiPtr is a pointer to the QSPIPSU driver component to use. +* +* @return None +* +* @note By default WP pin as per the QSPI controller is driven High +* which means no write protection. Calling this function once +* will enable the protection. +* +******************************************************************************/ +void XQspiPsu_WriteProtectToggle(XQspiPsu *QspiPsuPtr, u32 Toggle) +{ + /* For Single and Stacked flash configuration with x1 or x2 mode*/ + if (QspiPsuPtr->Config.ConnectionMode == XQSPIPSU_CONNECTION_MODE_SINGLE) { + /* Enable */ + XQspiPsu_Enable(QspiPsuPtr); + + /* Select slave */ + XQspiPsu_GenFifoEntryCSAssert(QspiPsuPtr); + + XQspiPsu_WriteReg(QspiPsuPtr->Config.BaseAddress, XQSPIPSU_GPIO_OFFSET, + Toggle); + + } else if (QspiPsuPtr->Config.ConnectionMode == XQSPIPSU_CONNECTION_MODE_PARALLEL || + QspiPsuPtr->Config.ConnectionMode == XQSPIPSU_CONNECTION_MODE_STACKED) { + xil_printf("Dual Parallel/Stacked configuration is not supported by this API\r\n"); + } +} /** @} */ diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_3/src/xqspipsu.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/qspipsu_v1_7/src/xqspipsu.h similarity index 85% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_3/src/xqspipsu.h rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/qspipsu_v1_7/src/xqspipsu.h index 94801949c..b73b72293 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_3/src/xqspipsu.h +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/qspipsu_v1_7/src/xqspipsu.h @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2018 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -33,7 +33,7 @@ /** * * @file xqspipsu.h -* @addtogroup qspipsu_v1_0 +* @addtogroup qspipsu_v1_7 * @{ * @details * @@ -112,7 +112,33 @@ * configuration. Updated XQspiPsu_PollData() and * XQspiPsu_Create_PollConfigData() functions in xqspipsu.c * and also modified the polldata example -* +* ms 03/17/17 Added readme.txt file in examples folder for doxygen +* generation. +* ms 04/05/17 Modified Comment lines in functions of qspipsu +* examples to recognize it as documentation block +* and modified filename tag to include them in +* doxygen examples. +* 1.4 tjs 05/26/17 Added support for accessing upper DDR (0x800000000) +* while booting images from QSPI +* 1.5 tjs 08/08/17 Added index.html file for importing examples from system.mss +* 1.5 nsk 08/14/17 Added CCI support +* 1.5 tjs 09/14/17 Modified the checks for 4 byte addressing and commands. +* 1.6 tjs 10/16/17 Flow for accessing flash is made similar to u-boot and linux +* For CR-984966 +* 1.6 tjs 11/02/17 Resolved the compilation errors for ICCARM. CR-988625 +* 1.7 tjs 11/16/17 Removed the unsupported 4 Byte write and sector erase +* commands. +* 1.7 tjs 12/01/17 Added support for MT25QL02G Flash from Micron. CR-990642 +* 1.7 tjs 12/19/17 Added support for S25FL064L from Spansion. CR-990724 +* 1.7 tjs 01/11/18 Added support for MX66L1G45G flash from Macronix CR-992367 +* 1.7 tjs 01/16/18 Removed the check for DMA MSB to be written. (CR#992560) +* 1.7 tjs 01/17/18 Added support to toggle the WP pin of flash. (PR#2448) +* Added XQspiPsu_SetWP() in xqspipsu_options.c +* Added XQspiPsu_WriteProtectToggle() in xqspipsu.c and +* also added write protect example. +* 1.7 tjs 03/14/18 Added support in EL1 NS mode (CR#974882) +* 1.7 tjs 26/03/18 In dual parallel mode enable both CS when issuing Write +* enable command. CR-998478 * * ******************************************************************************/ @@ -175,6 +201,7 @@ typedef struct { u32 InputClockHz; /**< Input clock frequency */ u8 ConnectionMode; /**< Single, Stacked and Parallel mode */ u8 BusWidth; /**< Bus width available on board */ + u8 IsCacheCoherent; /**< Describes whether Cache Coherent or not */ } XQspiPsu_Config; /** @@ -259,6 +286,9 @@ typedef struct { #define XQSPIPSU_MSG_FLAG_TX 0x4U #define XQSPIPSU_MSG_FLAG_POLL 0x8U +/* GQSPI configuration to toggle WP of flash*/ +#define XQSPIPSU_SET_WP 1 + #define XQspiPsu_Select(InstancePtr, Mask) XQspiPsu_Out32(((InstancePtr)->Config.BaseAddress) + XQSPIPSU_SEL_OFFSET, Mask) #define XQspiPsu_Enable(InstancePtr) XQspiPsu_Out32(((InstancePtr)->Config.BaseAddress) + XQSPIPSU_EN_OFFSET, XQSPIPSU_EN_MASK) @@ -267,6 +297,7 @@ typedef struct { #define XQspiPsu_GetLqspiConfigReg(InstancePtr) XQspiPsu_In32((XQSPIPS_BASEADDR) + XQSPIPSU_LQSPI_CR_OFFSET) + /************************** Function Prototypes ******************************/ /* Initialization and reset */ @@ -292,6 +323,8 @@ s32 XQspiPsu_SetOptions(XQspiPsu *InstancePtr, u32 Options); s32 XQspiPsu_ClearOptions(XQspiPsu *InstancePtr, u32 Options); u32 XQspiPsu_GetOptions(XQspiPsu *InstancePtr); s32 XQspiPsu_SetReadMode(XQspiPsu *InstancePtr, u32 Mode); +void XQspiPsu_SetWP(XQspiPsu *InstancePtr, u8 Value); +void XQspiPsu_WriteProtectToggle(XQspiPsu *InstancePtr, u32 Toggle); #ifdef __cplusplus } diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/qspipsu_v1_3/src/xqspipsu_g.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/qspipsu_v1_7/src/xqspipsu_g.c similarity index 88% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/qspipsu_v1_3/src/xqspipsu_g.c rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/qspipsu_v1_7/src/xqspipsu_g.c index 969fa96b0..a6df4f5b8 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/qspipsu_v1_3/src/xqspipsu_g.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/qspipsu_v1_7/src/xqspipsu_g.c @@ -5,7 +5,7 @@ * Version: * DO NOT EDIT. * -* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.* +* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.* *Permission is hereby granted, free of charge, to any person obtaining a copy *of this software and associated documentation files (the Software), to deal *in the Software without restriction, including without limitation the rights @@ -44,14 +44,15 @@ * The configuration table for devices */ -XQspiPsu_Config XQspiPsu_ConfigTable[] = +XQspiPsu_Config XQspiPsu_ConfigTable[XPAR_XQSPIPSU_NUM_INSTANCES] = { { XPAR_PSU_QSPI_0_DEVICE_ID, XPAR_PSU_QSPI_0_BASEADDR, XPAR_PSU_QSPI_0_QSPI_CLK_FREQ_HZ, XPAR_PSU_QSPI_0_QSPI_MODE, - XPAR_PSU_QSPI_0_QSPI_BUS_WIDTH + XPAR_PSU_QSPI_0_QSPI_BUS_WIDTH, + XPAR_PSU_QSPI_0_IS_CACHE_COHERENT } }; diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_3/src/xqspipsu_hw.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/qspipsu_v1_7/src/xqspipsu_hw.h similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_3/src/xqspipsu_hw.h rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/qspipsu_v1_7/src/xqspipsu_hw.h index 40314d6e1..a7e856310 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_3/src/xqspipsu_hw.h +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/qspipsu_v1_7/src/xqspipsu_hw.h @@ -33,7 +33,7 @@ /** * * @file xqspipsu_hw.h -* @addtogroup qspipsu_v1_0 +* @addtogroup qspipsu_v1_7 * @{ * * This file contains low level access funcitons using the base address @@ -49,6 +49,7 @@ * sk 04/24/15 Modified the code according to MISRAC-2012. * 1.2 nsk 07/01/16 Added LQSPI supported Masks * rk 07/15/16 Added support for TapDelays at different frequencies. +* 1.7 tjs 03/14/18 Added support in EL1 NS mode. * * * @@ -147,6 +148,7 @@ extern "C" { or quad I/O */ #define XQSPIPS_LQSPI_CR_INST_MASK 0x000000FF /**< Read instr code */ #define XQSPIPS_LQSPI_CR_RST_STATE 0x80000003 /**< Default LQSPI CR value */ +#define XQSPIPS_LQSPI_CR_4_BYTE_STATE 0x88000013 /**< Default 4 Byte LQSPI CR value */ #define XQSPIPS_LQSPI_CFG_RST_STATE 0x800238C1 /**< Default LQSPI CFG value */ /** * Register: XQSPIPSU_ISR @@ -828,6 +830,7 @@ extern "C" { #define IOU_TAPDLY_BYPASS_LQSPI_RX_SHIFT 0X02 #define IOU_TAPDLY_BYPASS_LQSPI_RX_WIDTH 0X01 #define IOU_TAPDLY_BYPASS_LQSPI_RX_MASK 0x00000004 +#define IOU_TAPDLY_RESET_STATE 0x7 /***************** Macros (Inline Functions) Definitions *********************/ diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_3/src/xqspipsu_options.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/qspipsu_v1_7/src/xqspipsu_options.c similarity index 92% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_3/src/xqspipsu_options.c rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/qspipsu_v1_7/src/xqspipsu_options.c index 2c77a0881..e943e52ae 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_3/src/xqspipsu_options.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/qspipsu_v1_7/src/xqspipsu_options.c @@ -33,7 +33,7 @@ /** * * @file xqspipsu_options.c -* @addtogroup qspipsu_v1_0 +* @addtogroup qspipsu_v1_7 * @{ * * This file implements funcitons to configure the QSPIPSU component, @@ -51,6 +51,8 @@ * 1.2 nsk 07/01/16 Modified XQspiPsu_SetOptions() to support * LQSPI options and updated OptionsTable * rk 07/15/16 Added support for TapDelays at different frequencies. +* 1.7 tjs 01/17/18 Added support to toggle the WP pin of flash. (PR#2448) +* 1.7 tjs 03/14/18 Added support in EL1 NS mode. (CR#974882) * * * @@ -59,6 +61,9 @@ /***************************** Include Files *********************************/ #include "xqspipsu.h" +#if defined (__aarch64__) +#include "xil_smc.h" +#endif /************************** Constant Definitions *****************************/ @@ -179,7 +184,7 @@ s32 XQspiPsu_SetOptions(XQspiPsu *InstancePtr, u32 Options) ConfigReg = XQspiPsu_ReadReg(XQSPIPS_BASEADDR,XQSPIPSU_LQSPI_CR_OFFSET); if (QspiPsuOptions & XQSPIPSU_LQSPI_MODE_OPTION) { - XQspiPsu_WriteReg(XQSPIPS_BASEADDR,XQSPIPSU_LQSPI_CR_OFFSET,XQSPIPS_LQSPI_CR_RST_STATE); + XQspiPsu_WriteReg(XQSPIPS_BASEADDR,XQSPIPSU_LQSPI_CR_OFFSET,XQSPIPS_LQSPI_CR_4_BYTE_STATE); XQspiPsu_WriteReg(XQSPIPS_BASEADDR,XQSPIPSU_CFG_OFFSET,XQSPIPS_LQSPI_CFG_RST_STATE); /* Enable the QSPI controller */ XQspiPsu_WriteReg(XQSPIPS_BASEADDR,XQSPIPSU_EN_OFFSET,XQSPIPSU_EN_MASK); @@ -344,8 +349,15 @@ s32 XQspi_Set_TapDelay(XQspiPsu * InstancePtr,u32 TapdelayBypass, if (InstancePtr->IsBusy == TRUE) { Status = XST_DEVICE_BUSY; } else { +#if EL1_NONSECURE && defined (__aarch64__) + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + IOU_TAPDLY_BYPASS_OFFSET) | + ((u64)(0x4) << 32), + (u64)TapdelayBypass, 0, 0, 0, 0, 0); +#else XQspiPsu_WriteReg(XPS_SYS_CTRL_BASEADDR,IOU_TAPDLY_BYPASS_OFFSET, TapdelayBypass); +#endif XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPSU_LPBK_DLY_ADJ_OFFSET,LPBKDelay); XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress, @@ -380,8 +392,12 @@ static s32 XQspipsu_Calculate_Tapdelay(XQspiPsu *InstancePtr, u8 Prescaler) Divider = (1 << (Prescaler+1)); FreqDiv = (InstancePtr->Config.InputClockHz)/Divider; +#if EL1_NONSECURE && defined (__aarch64__) + Tapdelay = IOU_TAPDLY_RESET_STATE; +#else Tapdelay = XQspiPsu_ReadReg(XPS_SYS_CTRL_BASEADDR, - IOU_TAPDLY_BYPASS_OFFSET); + IOU_TAPDLY_BYPASS_OFFSET); +#endif Tapdelay = Tapdelay & (~IOU_TAPDLY_BYPASS_LQSPI_RX_MASK); @@ -618,4 +634,33 @@ s32 XQspiPsu_SetReadMode(XQspiPsu *InstancePtr, u32 Mode) #endif return Status; } + +/*****************************************************************************/ +/** +* +* This function sets the Write Protect and Hold options for the QSPIPSU device +* driver.The device must be idle rather than busy transferring data before +* setting Write Protect and Hold options. +* +* @param InstancePtr is a pointer to the XQspiPsu instance. +* @param Value of the WP_HOLD bit in configuration register +* +* @return None +* +* @note +* This function is not thread-safe. This function can only be used with single +* flash configuration and x1/x2 data mode. This function cannot be used with +* x4 data mode and dual parallel and stacked flash configuration. +* +******************************************************************************/ +void XQspiPsu_SetWP(XQspiPsu *InstancePtr, u8 Value) +{ + u32 ConfigReg; + + ConfigReg = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress, + XQSPIPSU_CFG_OFFSET); + ConfigReg |= Value << XQSPIPSU_CFG_WP_HOLD_SHIFT; + XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPSU_CFG_OFFSET, + ConfigReg); +} /** @} */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/qspipsu_v1_3/src/xqspipsu_sinit.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/qspipsu_v1_7/src/xqspipsu_sinit.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/qspipsu_v1_3/src/xqspipsu_sinit.c rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/qspipsu_v1_7/src/xqspipsu_sinit.c index 63aaed0bb..3869167d8 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/qspipsu_v1_3/src/xqspipsu_sinit.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/qspipsu_v1_7/src/xqspipsu_sinit.c @@ -33,7 +33,7 @@ /** * * @file xqspipsu_sinit.c -* @addtogroup qspipsu_v1_0 +* @addtogroup qspipsu_v1_7 * @{ * * The implementation of the XQspiPsu component's static initialization diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/resetps_v1_0/src/Makefile b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/resetps_v1_0/src/Makefile new file mode 100644 index 000000000..67ab3d8a9 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/resetps_v1_0/src/Makefile @@ -0,0 +1,40 @@ +COMPILER= +ARCHIVER= +CP=cp +COMPILER_FLAGS= +EXTRA_COMPILER_FLAGS= +LIB=libxil.a + +CC_FLAGS = $(COMPILER_FLAGS) +ECC_FLAGS = $(EXTRA_COMPILER_FLAGS) + +RELEASEDIR=../../../lib +INCLUDEDIR=../../../include +INCLUDES=-I./. -I${INCLUDEDIR} + +OUTS = *.o + +LIBSOURCES:=*.c +INCLUDEFILES:=*.h + +OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c))) + +libs: banner resetps_libs clean + +%.o: %.c + ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $< + +banner: + echo "Compiling resetps" + +resetps_libs: ${OBJECTS} + $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS} + +.PHONY: include +include: resetps_includes + +resetps_includes: + ${CP} ${INCLUDEFILES} ${INCLUDEDIR} + +clean: + rm -rf ${OBJECTS} diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/resetps_v1_0/src/xresetps.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/resetps_v1_0/src/xresetps.c new file mode 100644 index 000000000..626ec54d7 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/resetps_v1_0/src/xresetps.c @@ -0,0 +1,1030 @@ +/****************************************************************************** +* +* Copyright (C) 2017 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xresetps.c +* @addtogroup xresetps_v1_0 +* @{ +* +* Contains the implementation of interface functions of the XResetPs driver. +* See xresetps.h for a description of the driver. +* +* 
+* MODIFICATION HISTORY:
+* Ver   Who    Date     Changes
+* ----- ------ -------- ---------------------------------------------
+* 1.00  cjp    09/05/17 First release
+*
+* +******************************************************************************/ + +/***************************** Include Files *********************************/ +#include "xresetps.h" +#include "xresetps_hw.h" +#include "xil_types.h" + +/************************** Constant Definitions *****************************/ +#define XRESETPS_RSTID_BASE (1000) +#define XRESETPS_REGADDR_INVALID (0xFFFFFFFFU) +#define XRESETPS_BM_INVALID (0xFFFFFFFFU) + +/**************************** Type Definitions *******************************/ +typedef struct { + const u32 SlcrregAddr; + const u32 SlcrregBitmask; + const u32 PwrStateBitmask; + const XResetPs_PulseTypes PulseType; + const u8 SupportedActions; +} XResetPs_Lookup; + +/************************** Variable Definitions *****************************/ +#if !EL1_NONSECURE +const static XResetPs_Lookup ResetMap[] = { + /* + * {Control Register, Control Bitmask, + * Power State Bitask, Pulse Type, + * Supported Actions}, + */ + {XRESETPS_CRF_APB_RST_FPD_TOP, PCIE_CFG_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_RST_FPD_TOP, PCIE_BRIDGE_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_RST_FPD_TOP, PCIE_CTRL_RESET_MASK, + PCIE_CTRL_PSCHK_MASK, XRESETPS_PT_DLY_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_RST_FPD_TOP, DP_RESET_MASK, + DP_PSCHK_MASK, XRESETPS_PT_DLY_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_RST_FPD_TOP, SWDT_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_RST_FPD_TOP, AFI_FM5_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_RST_FPD_TOP, AFI_FM4_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_RST_FPD_TOP, AFI_FM3_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_RST_FPD_TOP, AFI_FM2_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_RST_FPD_TOP, AFI_FM1_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_RST_FPD_TOP, AFI_FM0_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_RST_FPD_TOP, GDMA_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_RST_FPD_TOP, GPU_PP1_RESET_MASK, + GPU_PP1_PSCHK_MASK, XRESETPS_PT_DLY_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_RST_FPD_TOP, GPU_PP0_RESET_MASK, + GPU_PP0_PSCHK_MASK, XRESETPS_PT_DLY_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_RST_FPD_TOP, GPU_RESET_MASK, + GPU_PSCHK_MASK, XRESETPS_PT_DLY_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_RST_FPD_TOP, GT_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_RST_FPD_TOP, SATA_RESET_MASK, + SATA_PSCHK_MASK, XRESETPS_PT_DLY_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_RST_FPD_APU, ACPU3_PWRON_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_RST_FPD_APU, ACPU2_PWRON_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_RST_FPD_APU, ACPU1_PWRON_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_RST_FPD_APU, ACPU0_PWRON_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_RST_FPD_APU, APU_L2_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_RST_FPD_APU, ACPU3_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_RST_FPD_APU, ACPU2_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_RST_FPD_APU, ACPU1_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_RST_FPD_APU, ACPU0_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_RST_DDR_SS, DDR_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_RST_DDR_SS, DDR_APM_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RESET_CTRL, SOFT_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_IOU0, GEM0_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_IOU0, GEM1_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_IOU0, GEM2_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_IOU0, GEM3_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_IOU2, QSPI_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_IOU2, UART0_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_IOU2, UART1_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_IOU2, SPI0_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_IOU2, SPI1_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_IOU2, SDIO0_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_IOU2, SDIO1_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_IOU2, CAN0_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_IOU2, CAN1_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_IOU2, I2C0_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_IOU2, I2C1_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_IOU2, TTC0_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_IOU2, TTC1_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_IOU2, TTC2_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_IOU2, TTC3_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_IOU2, SWDT_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_IOU2, NAND_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_IOU2, ADMA_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_IOU2, GPIO_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_IOU2, IOU_CC_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_IOU2, TIMESTAMP_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_TOP, RPU_R50_RESET_MASK, + R50_PSCHK_MASK, XRESETPS_PT_DLY_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_TOP, RPU_R51_RESET_MASK, + R51_PSCHK_MASK, XRESETPS_PT_DLY_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_TOP, RPU_AMBA_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_TOP, OCM_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_TOP, RPU_PGE_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_TOP, USB0_CORERESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_TOP, USB1_CORERESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_TOP, USB0_HIBERRESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_TOP, USB1_HIBERRESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_TOP, USB0_APB_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_TOP, USB1_APB_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_TOP, IPI_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_TOP, APM_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_TOP, RTC_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_TOP, SYSMON_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_TOP, AFI_FM6_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_TOP, LPD_SWDT_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_TOP, FPD_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_DBG, RPU_DBG1_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_DBG, RPU_DBG0_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_DBG, DBG_LPD_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_DBG, DBG_FPD_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_APLL_CTRL, APLL_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_DPLL_CTRL, DPLL_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_VPLL_CTRL, VPLL_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_IOPLL_CTRL, IOPLL_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RPLL_CTRL, RPLL_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL0_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL1_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL2_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL3_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL4_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL5_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL6_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL7_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL8_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL9_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL10_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL11_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL12_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL13_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL14_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL15_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL16_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL17_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL18_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL19_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL20_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL21_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL22_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL23_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL24_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL25_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL26_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL27_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL28_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL29_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL30_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL31_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_GLB_RST_CTRL, RPU_LS_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_GLB_RST_CTRL, PS_ONLY_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_NOSUP)}, + /* All fields invalidated for PL since not supported */ + {XRESETPS_REGADDR_INVALID, XRESETPS_BM_INVALID, + XRESETPS_BM_INVALID, XRESETPS_PT_INVALID, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, +}; +#endif + +/***************** Macros (Inline Functions) Definitions *********************/ + +/****************************************************************************/ +/** +* +* Initialize a specific reset controller instance/driver. This function +* must be called before other functions of the driver are called. +* +* @param InstancePtr is a pointer to the XResetPs instance. +* @param ConfigPtr is the config structure. +* @param EffectiveAddress is the base address for the device. It could be +* a virtual address if address translation is supported in the +* system, otherwise it is the physical address. +* +* @return +* - XST_SUCCESS if initialization was successful. +* +* @note None. +* +******************************************************************************/ +XStatus XResetPs_CfgInitialize(XResetPs *InstancePtr, + XResetPs_Config *ConfigPtr, u32 EffectiveAddress) +{ + /* Arguments validation */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(ConfigPtr != NULL); + + /* Copying instance */ + InstancePtr->Config.DeviceId = ConfigPtr->DeviceId; + InstancePtr->Config.BaseAddress = EffectiveAddress; + + return XST_SUCCESS; +} + +#if !EL1_NONSECURE +/****************************************************************************/ +/** +* +* Pulse Reset RPU. +* +* @param None. +* +* @return +* - XST_SUCCESS if successful else error code. +* +* @note The pulse reset sequence is referred from ug1085(v1.3) +* chapter-38. Few changes to the sequence are adpoted from PMUFW. +* +******************************************************************************/ +static XStatus XResetPs_PulseResetRpuLs(void) +{ + u32 TimeOut; + u32 RegValue; + + /* Block Cortex-R5 master interface */ + RegValue = XResetPs_ReadReg(XRESETPS_LPD_SCR_AXIISO_REQ_CTRL); + RegValue &= (~RPU_MASTER_ISO_MASK); + RegValue |= RPU_MASTER_ISO_MASK; + XResetPs_WriteReg(XRESETPS_LPD_SCR_AXIISO_REQ_CTRL, RegValue); + + /* Wait for acknowledgment from AIB until timeout */ + TimeOut = XRESETPS_AIB_PSPL_DELAY; + RegValue = XResetPs_ReadReg(XRESETPS_LPD_SCR_AXIISO_ACK_CTRL); + while ((TimeOut > 0U) && + ((RegValue & RPU_MASTER_ISO_MASK) != RPU_MASTER_ISO_MASK)) { + RegValue = XResetPs_ReadReg(XRESETPS_LPD_SCR_AXIISO_ACK_CTRL); + TimeOut--; + } + + if (TimeOut == 0U) { + /* + * @NOTE: + * AIB ack Timed Out. + * As per ug1085(v1.3), nothing is to be done on timeout, hence + * continuing with reset sequence. + */ + } + + /* Block Cortex-R5 slave interface */ + RegValue = XResetPs_ReadReg(XRESETPS_LPD_SCR_AXIISO_REQ_CTRL); + RegValue &= (~RPU_SLAVE_ISO_MASK); + RegValue |= RPU_SLAVE_ISO_MASK; + XResetPs_WriteReg(XRESETPS_LPD_SCR_AXIISO_REQ_CTRL, RegValue); + + /* Wait for acknowledgment from AIB until timeout */ + TimeOut = XRESETPS_AIB_PSPL_DELAY; + RegValue = XResetPs_ReadReg(XRESETPS_LPD_SCR_AXIISO_ACK_CTRL); + while ((TimeOut > 0U) && + ((RegValue & RPU_SLAVE_ISO_MASK) != RPU_SLAVE_ISO_MASK)) { + RegValue = XResetPs_ReadReg(XRESETPS_LPD_SCR_AXIISO_ACK_CTRL); + TimeOut--; + } + + if (TimeOut == 0U) { + /* + * @NOTE: + * AIB ack Timed Out. + * As per ug1085(v1.3), nothing is to be done on timeout, hence + * continuing with reset sequence. + */ + } + + /* Unblock Cortex-R5 master interface */ + RegValue = XResetPs_ReadReg(XRESETPS_LPD_SCR_AXIISO_REQ_CTRL); + RegValue &= (~RPU_MASTER_ISO_MASK); + XResetPs_WriteReg(XRESETPS_LPD_SCR_AXIISO_REQ_CTRL, RegValue); + + /* Initiate Cortex-R5 LockStep reset */ + RegValue = XResetPs_ReadReg(XRESETPS_PMU_GLB_RST_CTRL); + RegValue |= RPU_LS_RESET_MASK; + XResetPs_WriteReg(XRESETPS_PMU_GLB_RST_CTRL, RegValue); + + /* Wait */ + TimeOut = XRESETPS_RST_PROP_DELAY; + while (TimeOut > 0U) { + TimeOut--; + } + + /* Release Cortex-R5 from Reset */ + RegValue = XResetPs_ReadReg(XRESETPS_PMU_GLB_RST_CTRL); + RegValue &= (~RPU_LS_RESET_MASK); + XResetPs_WriteReg(XRESETPS_PMU_GLB_RST_CTRL, RegValue); + + /* Wait */ + TimeOut = XRESETPS_RST_PROP_DELAY; + while (TimeOut > 0U) { + TimeOut--; + } + + /* Unblock Cortex-R5 slave interface */ + RegValue = XResetPs_ReadReg(XRESETPS_LPD_SCR_AXIISO_REQ_CTRL); + RegValue &= (~RPU_SLAVE_ISO_MASK); + XResetPs_WriteReg(XRESETPS_LPD_SCR_AXIISO_REQ_CTRL, RegValue); + + return XST_SUCCESS; +} + +/****************************************************************************/ +/** +* +* Pulse Reset PS only. +* +* @param None. +* +* @return +* - XST_SUCCESS if successful else error code. +* +* @note The pulse reset sequence is referred from ug1085(v1.3) +* chapter-38. Few changes to the sequence are adpoted from PMUFW. +* +******************************************************************************/ +static XStatus XResetPs_PulseResetPsOnly(void) +{ + + u32 RegValue; + u32 TimeOut; + u8 ReconfirmAckCnt; + + /* TODO: Set PMU Error to indicate to PL */ + + /* Block FPD to PL and LPD to PL interfaces with AIB (in PS) */ + XResetPs_WriteReg(XRESETPS_PMU_GLB_AIB_CTRL, AIB_ISO_CTRL_MASK); + + /* + * @NOTE: Updated referring PMUFW + * There is a possibility of glitch in AIB ack signal to PMU, hence ack + * needs reconfirmation. + */ + /* Wait for AIB ack or Timeout */ + ReconfirmAckCnt = XRESETPS_AIB_PSPL_RECONFIRM_CNT; + do { + TimeOut = XRESETPS_AIB_PSPL_DELAY; + RegValue = XResetPs_ReadReg(XRESETPS_PMU_GLB_AIB_STATUS); + while ((TimeOut > 0U) && + ((RegValue & AIB_ISO_STATUS_MASK) != AIB_ISO_STATUS_MASK)) { + RegValue = + XResetPs_ReadReg(XRESETPS_PMU_GLB_AIB_STATUS); + TimeOut--; + } + + if (TimeOut == 0U) { + /* + * @NOTE: + * AIB ack Timed Out. + * As per ug1085(v1.3), nothing is to be done on + * timeout, hence continuing with reset sequence. + */ + ReconfirmAckCnt = 0U; + } else { + ReconfirmAckCnt--; + } + } + while (ReconfirmAckCnt > 0U); + + /* + * @NOTE: Updated referring PMUFW. + * Check if we are running Silicon version 1.0. If so, + * bypass the RPLL before initiating the reset. This is + * due to a bug in 1.0 Silicon wherein the PS hangs on a + * reset if the RPLL is in use. + */ + RegValue = XResetPs_ReadReg(XRESETPS_CSU_VERSION_REG); + if (XRESETPS_PLATFORM_PS_VER1 == (RegValue & PS_VERSION_MASK)) { + RegValue = XResetPs_ReadReg(XRESETPS_CRL_APB_RPLL_CTRL); + RegValue |= RPLL_BYPASS_MASK; + XResetPs_WriteReg(XRESETPS_CRL_APB_RPLL_CTRL, RegValue); + } + + /* Block the propagation of the PROG signal to the PL */ + RegValue = XResetPs_ReadReg(XRESETPS_PMU_GLB_PS_CTRL); + RegValue &= (~PROG_ENABLE_MASK); + XResetPs_WriteReg(XRESETPS_PMU_GLB_PS_CTRL, RegValue); + + RegValue = XResetPs_ReadReg(XRESETPS_PMU_GLB_PS_CTRL); + RegValue |= PROG_GATE_MASK; + XResetPs_WriteReg(XRESETPS_PMU_GLB_PS_CTRL, RegValue); + + /* Initiate PS-only reset */ + RegValue = XResetPs_ReadReg(XRESETPS_PMU_GLB_RST_CTRL); + RegValue |= PS_ONLY_RESET_MASK; + XResetPs_WriteReg(XRESETPS_PMU_GLB_RST_CTRL, RegValue); + + return XST_SUCCESS; +} + +/****************************************************************************/ +/** +* +* Pulse Reset FPD. +* +* @param None. +* +* @return +* - XST_SUCCESS if successful else error code. +* +* @note The pulse reset sequence is referred from ug1085(v1.3) +* chapter-38. Few changes to the sequence are adpoted from PMUFW. +* +******************************************************************************/ +static XStatus XResetPs_PulseResetFpd(void) +{ + u32 TimeOut; + u32 RegValue; + + /* Enable FPD to LPD isolations */ + RegValue = XResetPs_ReadReg(XRESETPS_LPD_SCR_AXIISO_REQ_CTRL); + RegValue &= (~FPD_TO_LPD_ISO_MASK); + RegValue |= FPD_TO_LPD_ISO_MASK; + XResetPs_WriteReg(XRESETPS_LPD_SCR_AXIISO_REQ_CTRL, RegValue); + + RegValue = XResetPs_ReadReg(XRESETPS_LPD_SLCR_APBISO_REQ_CTRL); + RegValue |= GPU_ISO_MASK; + XResetPs_WriteReg(XRESETPS_LPD_SLCR_APBISO_REQ_CTRL, RegValue); + + /* Enable LPD to FPD isolations */ + RegValue = XResetPs_ReadReg(XRESETPS_LPD_SCR_AXIISO_REQ_CTRL); + RegValue &= (~LPD_TO_FPD_ISO_MASK); + RegValue |= LPD_TO_FPD_ISO_MASK; + XResetPs_WriteReg(XRESETPS_LPD_SCR_AXIISO_REQ_CTRL, RegValue); + + /* + * Here we need to check for AIB ack, since nothing is done incase + * ack is not received, we are just waiting for specified timeout + * and continuing + */ + TimeOut = XRESETPS_AIB_ISO_DELAY; + while (TimeOut > 0U) { + TimeOut--; + } + + /* Initiate FPD reset */ + RegValue = XResetPs_ReadReg(XRESETPS_PMU_GLB_RST_CTRL); + RegValue |= FPD_APU_RESET_MASK; + XResetPs_WriteReg(XRESETPS_PMU_GLB_RST_CTRL, RegValue); + + /* Wait till reset propagates */ + TimeOut = XRESETPS_RST_PROP_DELAY; + while (TimeOut > 0U) { + TimeOut--; + } + + /* Disable FPD to LPD isolations */ + RegValue = XResetPs_ReadReg(XRESETPS_LPD_SCR_AXIISO_REQ_CTRL); + RegValue &= (~FPD_TO_LPD_ISO_MASK); + XResetPs_WriteReg(XRESETPS_LPD_SCR_AXIISO_REQ_CTRL, RegValue); + + RegValue = XResetPs_ReadReg(XRESETPS_LPD_SLCR_APBISO_REQ_CTRL); + RegValue &= (~GPU_ISO_MASK); + XResetPs_WriteReg(XRESETPS_LPD_SLCR_APBISO_REQ_CTRL, RegValue); + + /* Release from Reset and wait till it propagates */ + RegValue = XResetPs_ReadReg(XRESETPS_PMU_GLB_RST_CTRL); + RegValue &= (~FPD_APU_RESET_MASK); + XResetPs_WriteReg(XRESETPS_PMU_GLB_RST_CTRL, RegValue); + + /* Wait till reset propagates */ + TimeOut = XRESETPS_RST_PROP_DELAY; + while (TimeOut > 0U) { + TimeOut--; + } + + /* Disable LPD to FPD isolations */ + RegValue = XResetPs_ReadReg(XRESETPS_LPD_SCR_AXIISO_REQ_CTRL); + RegValue &= (~LPD_TO_FPD_ISO_MASK); + XResetPs_WriteReg(XRESETPS_LPD_SCR_AXIISO_REQ_CTRL, RegValue); + + return XST_SUCCESS; +} +#endif + +/****************************************************************************/ +/** +* +* Assert reset for specific peripheral based on reset ID. +* +* @param InstancePtr is a pointer to the XResetPs instance. +* @param ResetID is the ID of the peripheral. +* +* @return +* - XST_SUCCESS if reset assertion was successful. +* - Error Code otherwise. +* +* @note None. +* +******************************************************************************/ +XStatus XResetPs_ResetAssert(XResetPs *InstancePtr, + const XResetPs_RstId ResetID) +{ + /* Arguments validation */ + Xil_AssertNonvoid(InstancePtr != NULL); + if ((ResetID > XRESETPS_RSTID_END) || + (ResetID < XRESETPS_RSTID_START)) { + return XST_INVALID_PARAM; + } + +#if EL1_NONSECURE + /* Assert reset via PMUFW */ + u64 SmcArgs; + XSmc_OutVar out; + + SmcArgs = (u64)XRESETPS_RSTACT_ASSERT << 32; + SmcArgs |= ((u64)(ResetID + XRESETPS_RSTID_BASE)); + + out = Xil_Smc(PM_ASSERT_SMC_FID, SmcArgs, 0, 0, 0, 0, 0, 0); + + return ((u32)out.Arg0); +#else + u32 RegAddr; + u32 RegBitmask; + u32 RegValue; + + /* Ignoring Nodes that doesnot support assert */ + if (!XRESETPS_CHK_ASSERT_SUPPORT(ResetMap[ResetID].SupportedActions)) { + return XST_NO_FEATURE; + } + + RegAddr = ResetMap[ResetID].SlcrregAddr; + RegBitmask = ResetMap[ResetID].SlcrregBitmask; + + /* Enable bit to assert reset */ + RegValue = XResetPs_ReadReg(RegAddr); + RegValue |= RegBitmask; + XResetPs_WriteReg(RegAddr, RegValue); + + return XST_SUCCESS; +#endif +} + +/****************************************************************************/ +/** +* +* Deassert reset for specific peripheral based on reset ID. +* +* @param InstancePtr is a pointer to the XResetPs instance. +* @param ResetID is the ID of the peripheral. +* +* @return +* - XST_SUCCESS if reset deassertion was successful. +* - Error Code otherwise. +* +* @note None. +* +******************************************************************************/ +XStatus XResetPs_ResetDeassert(XResetPs *InstancePtr, + const XResetPs_RstId ResetID) +{ + /* Arguments validation */ + Xil_AssertNonvoid(InstancePtr != NULL); + if ((ResetID > XRESETPS_RSTID_END) || + (ResetID < XRESETPS_RSTID_START)) { + return XST_INVALID_PARAM; + } + +#if EL1_NONSECURE + /* Deassert reset via PMUFW */ + u64 SmcArgs; + XSmc_OutVar out; + + SmcArgs = (u64)XRESETPS_RSTACT_RELEASE << 32; + SmcArgs |= ((u64)(ResetID + XRESETPS_RSTID_BASE)); + + out = Xil_Smc(PM_ASSERT_SMC_FID, SmcArgs, 0, 0, 0, 0, 0, 0); + + return ((u32)out.Arg0); +#else + u32 RegAddr; + u32 RegBitmask; + u32 RegValue; + + /* Ignoring Nodes that does not support deassert */ + if (!XRESETPS_CHK_ASSERT_SUPPORT(ResetMap[ResetID].SupportedActions)) { + return XST_NO_FEATURE; + } + + RegAddr = ResetMap[ResetID].SlcrregAddr; + RegBitmask = ResetMap[ResetID].SlcrregBitmask; + + /* Disable bit to deassert reset */ + RegValue = XResetPs_ReadReg(RegAddr); + RegValue &= (~RegBitmask); + XResetPs_WriteReg(RegAddr, RegValue); + + return XST_SUCCESS; +#endif +} + +/****************************************************************************/ +/** +* +* Pulse reset for specific peripheral based on reset ID. +* +* @param InstancePtr is a pointer to the XResetPs instance. +* @param ResetID is the ID of the peripheral. +* +* @return +* - XST_SUCCESS if pulse reset was successful. +* - Error Code otherwise. +* +* @note None. +* +******************************************************************************/ +XStatus XResetPs_ResetPulse(XResetPs *InstancePtr, const XResetPs_RstId ResetID) +{ + /* Arguments validation */ + Xil_AssertNonvoid(InstancePtr != NULL); + if ((ResetID > XRESETPS_RSTID_END) || + (ResetID < XRESETPS_RSTID_START)) { + return XST_INVALID_PARAM; + } + +#if EL1_NONSECURE + /* Pulse reset via PMUFW */ + u64 SmcArgs; + XSmc_OutVar out; + + SmcArgs = (u64)XRESETPS_RSTACT_PULSE << 32; + SmcArgs |= ((u64)(ResetID + XRESETPS_RSTID_BASE)); + + out = Xil_Smc(PM_ASSERT_SMC_FID, SmcArgs, 0, 0, 0, 0, 0, 0); + + return ((u32)out.Arg0); +#else + u32 RegAddr; + u32 RegBitmask; + u32 RegValue; + u32 TimeOut; + + /* Ignoring Nodes that donot support pulse reset */ + if (!XRESETPS_CHK_PULSE_SUPPORT(ResetMap[ResetID].SupportedActions)) { + return XST_NO_FEATURE; + } + + /* Handling specific pulse resets */ + switch (ResetID) { + case XRESETPS_RSTID_FPD: + return XResetPs_PulseResetFpd(); + case XRESETPS_RSTID_RPU_LS: + return XResetPs_PulseResetRpuLs(); + case XRESETPS_RSTID_PS_ONLY: + return XResetPs_PulseResetPsOnly(); + default: + break; + } + + RegAddr = ResetMap[ResetID].SlcrregAddr; + RegBitmask = ResetMap[ResetID].SlcrregBitmask; + + /* Power state mask validation */ + if ((ResetMap[ResetID].PulseType == XRESETPS_PT_DLY_PSCHK) && + (ResetMap[ResetID].PwrStateBitmask != XRESETPS_BM_INVALID)) { + RegValue = XResetPs_ReadReg(XRESETPS_PMU_GLB_PWR_STATUS); + if (ResetMap[ResetID].PwrStateBitmask != + (RegValue && ResetMap[ResetID].PwrStateBitmask )) { + return XST_REGISTER_ERROR; + } + } + + /* Enable bit to assert reset */ + RegValue = XResetPs_ReadReg(RegAddr); + RegValue |= RegBitmask; + XResetPs_WriteReg(RegAddr, RegValue); + + /* Wait for assert propogation */ + if (ResetMap[ResetID].PulseType != XRESETPS_PT_NO_DLY_NO_PSCHK) { + TimeOut = XRESETPS_PULSE_PROP_DELAY; + while (TimeOut > 0U) { + TimeOut--; + } + } + + /* Disable bit to deassert reset */ + RegValue = XResetPs_ReadReg(RegAddr); + RegValue &= (~RegBitmask); + XResetPs_WriteReg(RegAddr, RegValue); + + /* Wait for release propogation */ + if (ResetMap[ResetID].PulseType != XRESETPS_PT_NO_DLY_NO_PSCHK) { + TimeOut = XRESETPS_PULSE_PROP_DELAY; + while (TimeOut > 0U) { + TimeOut--; + } + } + + return XST_SUCCESS; +#endif +} + +/****************************************************************************/ +/** +* +* Get reset status for specific peripheral based on reset ID. +* +* @param InstancePtr is a pointer to the XResetPs instance. +* @param ResetID is the ID of the peripheral. +* @param Status is the status of reset for ResetID. +* 1 if asserted and 0 if released +* +* @return +* - XST_SUCCESS if status fetched successful. +* - Error Code otherwise. +* +* @note None. +* +******************************************************************************/ +XStatus XResetPs_ResetStatus(XResetPs *InstancePtr, + const XResetPs_RstId ResetID, XResetPs_RstStatus *Status) +{ + /* Arguments validation */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(Status != NULL); + if ((ResetID > XRESETPS_RSTID_END) || + (ResetID < XRESETPS_RSTID_START)) { + return XST_INVALID_PARAM; + } + +#if EL1_NONSECURE + /* Get reset status via PMUFW */ + XSmc_OutVar out; + + out = Xil_Smc(PM_GETSTATUS_SMC_FID, + ((u64)(ResetID + XRESETPS_RSTID_BASE)), 0, 0, 0, 0, 0, 0); + *Status = ((u32)(out.Arg0 >> 32)); + + return ((u32)out.Arg0); +#else + u32 RegAddr; + u32 RegBitmask; + u32 RegValue; + + /* Ignoring Nodes that donot support reset status */ + if (!XRESETPS_CHK_STATUS_SUPPORT(ResetMap[ResetID].SupportedActions)) { + return XST_NO_FEATURE; + } + + /* + * @NOTE: + * This will always move to else part as GPO3 are ignored because + * XRESETPS_PMU_LCL_READ_CTRL is not accessible. + */ + /* GPO3PL have status address different from control address */ + if ((ResetID >= XRESETPS_RSTID_GPO3PL0) && + (ResetID <= XRESETPS_RSTID_GPO3PL31)) { + RegAddr = XRESETPS_PMU_LCL_READ_CTRL; + } else { + RegAddr = ResetMap[ResetID].SlcrregAddr; + } + + RegBitmask = ResetMap[ResetID].SlcrregBitmask; + + RegValue = XResetPs_ReadReg(RegAddr); + if ((RegValue & RegBitmask) == RegBitmask) { + *Status = XRESETPS_RESETASSERTED; + } else { + *Status = XRESETPS_RESETRELEASED; + } + + return XST_SUCCESS; +#endif +} + +/** @} */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/resetps_v1_0/src/xresetps.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/resetps_v1_0/src/xresetps.h new file mode 100644 index 000000000..f6a632b4e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/resetps_v1_0/src/xresetps.h @@ -0,0 +1,382 @@ +/****************************************************************************** +* +* Copyright (C) 2017 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xresetps.h +* @addtogroup xresetps_v1_0 +* @{ +* @details +* +* The Xilinx Reset Controller driver supports the following features: +* - Assert reset for specific peripheral. +* - Deassert reset for specific peripheral. +* - Pulse reset for specific peripheral. +* - Get reset status for specific peripheral. +* +* This driver is intended to be RTOS and processor independent. It works with +* physical addresses only. Any needs for dynamic memory management, threads +* or thread mutual exclusion, virtual memory, or cache control must be +* satisfied by the layer above this driver. +* +* 
+* MODIFICATION HISTORY:
+* Ver   Who    Date     Changes
+* ----- ------ -------- -----------------------------------------------
+* 1.00  cjp    09/05/17 First release
+*
+* +******************************************************************************/ +#ifndef XRESETPS_H /* prevent circular inclusions */ +#define XRESETPS_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ +#include "xil_types.h" +#include "xil_assert.h" +#include "xstatus.h" +#include "xresetps_hw.h" + +#if defined (__aarch64__) +#include "xil_smc.h" +#endif + +/************************** Constant Definitions *****************************/ +/* + * Constants for supported/Not supported reset actions + */ +#define XRESETPS_SUP 1 +#define XRESETPS_NOSUP 0 + +/**************************** Type Definitions *******************************/ +/** + * This typedef contains configuration information for the device. + */ +typedef struct { + u16 DeviceId; /**< Unique ID of device */ + u32 BaseAddress; /**< Base address of the device */ +} XResetPs_Config; + +/** + * The XResetPs driver instance data. The user is required to allocate a + * variable of this type for every reset controller device in the system. + * A pointer to a variable of this type is then passed to the driver API + * functions. + */ +typedef struct { + XResetPs_Config Config; /**< Hardware Configuration */ +} XResetPs; + +/** + * This typedef defines type of pulse reset to be executed for peripherals. + * 3 type of pulse reset are possible: + * 1. Pulse with no delay and no power state validation + * 2. Pulse with delay but no power state validation + * 3. Pulse with delay and power state validation + */ +typedef enum { + XRESETPS_PT_NO_DLY_NO_PSCHK, /**< No delay, no power state check */ + XRESETPS_PT_DLY_NO_PSCHK, /**< Delay, no power state check */ + XRESETPS_PT_DLY_PSCHK, /**< Delay, power state check */ + XRESETPS_PT_INVALID, /**< Invalid pulse type */ +} XResetPs_PulseTypes; + +/** + * This typedef defines reset actions on the peripherals. + */ +typedef enum { + XRESETPS_RSTACT_RELEASE, + XRESETPS_RSTACT_ASSERT, + XRESETPS_RSTACT_PULSE, +} XresetPs_ResetAction; + +/** + * This typedef defines resetIDs of peripherals maps to PMUFW resetIDs. This + * resetIDs are not offseted by 1000 and are relative. + */ +typedef enum { + XRESETPS_RSTID_START, + XRESETPS_RSTID_PCIE_CFG = XRESETPS_RSTID_START, + XRESETPS_RSTID_PCIE_BRIDGE, + XRESETPS_RSTID_PCIE_CTRL, + XRESETPS_RSTID_DP, + XRESETPS_RSTID_SWDT_CRF, + XRESETPS_RSTID_AFI_FM5, + XRESETPS_RSTID_AFI_FM4, + XRESETPS_RSTID_AFI_FM3, + XRESETPS_RSTID_AFI_FM2, + XRESETPS_RSTID_AFI_FM1, + XRESETPS_RSTID_AFI_FM0, + XRESETPS_RSTID_GDMA, + XRESETPS_RSTID_GPU_PP1, + XRESETPS_RSTID_GPU_PP0, + XRESETPS_RSTID_GPU, + XRESETPS_RSTID_GT, + XRESETPS_RSTID_SATA, + XRESETPS_RSTID_ACPU3_PWRON, + XRESETPS_RSTID_ACPU2_PWRON, + XRESETPS_RSTID_ACPU1_PWRON, + XRESETPS_RSTID_ACPU0_PWRON, + XRESETPS_RSTID_APU_L2, + XRESETPS_RSTID_ACPU3, + XRESETPS_RSTID_ACPU2, + XRESETPS_RSTID_ACPU1, + XRESETPS_RSTID_ACPU0, + XRESETPS_RSTID_DDR, + XRESETPS_RSTID_APM_FPD, + XRESETPS_RSTID_SOFT, + XRESETPS_RSTID_GEM0, + XRESETPS_RSTID_GEM1, + XRESETPS_RSTID_GEM2, + XRESETPS_RSTID_GEM3, + XRESETPS_RSTID_QSPI, + XRESETPS_RSTID_UART0, + XRESETPS_RSTID_UART1, + XRESETPS_RSTID_SPI0, + XRESETPS_RSTID_SPI1, + XRESETPS_RSTID_SDIO0, + XRESETPS_RSTID_SDIO1, + XRESETPS_RSTID_CAN0, + XRESETPS_RSTID_CAN1, + XRESETPS_RSTID_I2C0, + XRESETPS_RSTID_I2C1, + XRESETPS_RSTID_TTC0, + XRESETPS_RSTID_TTC1, + XRESETPS_RSTID_TTC2, + XRESETPS_RSTID_TTC3, + XRESETPS_RSTID_SWDT_CRL, + XRESETPS_RSTID_NAND, + XRESETPS_RSTID_ADMA, + XRESETPS_RSTID_GPIO, + XRESETPS_RSTID_IOU_CC, + XRESETPS_RSTID_TIMESTAMP, + XRESETPS_RSTID_RPU_R50, + XRESETPS_RSTID_RPU_R51, + XRESETPS_RSTID_RPU_AMBA, + XRESETPS_RSTID_OCM, + XRESETPS_RSTID_RPU_PGE, + XRESETPS_RSTID_USB0_CORERESET, + XRESETPS_RSTID_USB1_CORERESET, + XRESETPS_RSTID_USB0_HIBERRESET, + XRESETPS_RSTID_USB1_HIBERRESET, + XRESETPS_RSTID_USB0_APB, + XRESETPS_RSTID_USB1_APB, + XRESETPS_RSTID_IPI, + XRESETPS_RSTID_APM_LPD, + XRESETPS_RSTID_RTC, + XRESETPS_RSTID_SYSMON, + XRESETPS_RSTID_AFI_FM6, + XRESETPS_RSTID_LPD_SWDT, + XRESETPS_RSTID_FPD, + XRESETPS_RSTID_RPU_DBG1, + XRESETPS_RSTID_RPU_DBG0, + XRESETPS_RSTID_DBG_LPD, + XRESETPS_RSTID_DBG_FPD, + XRESETPS_RSTID_APLL, + XRESETPS_RSTID_DPLL, + XRESETPS_RSTID_VPLL, + XRESETPS_RSTID_IOPLL, + XRESETPS_RSTID_RPLL, + XRESETPS_RSTID_GPO3PL0, + XRESETPS_RSTID_GPO3PL1, + XRESETPS_RSTID_GPO3PL2, + XRESETPS_RSTID_GPO3PL3, + XRESETPS_RSTID_GPO3PL4, + XRESETPS_RSTID_GPO3PL5, + XRESETPS_RSTID_GPO3PL6, + XRESETPS_RSTID_GPO3PL7, + XRESETPS_RSTID_GPO3PL8, + XRESETPS_RSTID_GPO3PL9, + XRESETPS_RSTID_GPO3PL10, + XRESETPS_RSTID_GPO3PL11, + XRESETPS_RSTID_GPO3PL12, + XRESETPS_RSTID_GPO3PL13, + XRESETPS_RSTID_GPO3PL14, + XRESETPS_RSTID_GPO3PL15, + XRESETPS_RSTID_GPO3PL16, + XRESETPS_RSTID_GPO3PL17, + XRESETPS_RSTID_GPO3PL18, + XRESETPS_RSTID_GPO3PL19, + XRESETPS_RSTID_GPO3PL20, + XRESETPS_RSTID_GPO3PL21, + XRESETPS_RSTID_GPO3PL22, + XRESETPS_RSTID_GPO3PL23, + XRESETPS_RSTID_GPO3PL24, + XRESETPS_RSTID_GPO3PL25, + XRESETPS_RSTID_GPO3PL26, + XRESETPS_RSTID_GPO3PL27, + XRESETPS_RSTID_GPO3PL28, + XRESETPS_RSTID_GPO3PL29, + XRESETPS_RSTID_GPO3PL30, + XRESETPS_RSTID_GPO3PL31, + XRESETPS_RSTID_RPU_LS, + XRESETPS_RSTID_PS_ONLY, + XRESETPS_RSTID_PL, + XRESETPS_RSTID_END = XRESETPS_RSTID_PL, +} XResetPs_RstId; + +/** + * This typedef defines possible values for reset status of peripherals. + */ +typedef enum { + XRESETPS_RESETRELEASED, + XRESETPS_RESETASSERTED +} XResetPs_RstStatus; + +/***************** Macros (Inline Functions) Definitions *********************/ +/****************************************************************************/ +/** +* +* Set supported reset action. +* +* @param StatusSupport indicates if reset status check is supported +* @param PulseSupport indicates if pulse reset action is supported +* @param AssertSupport indicates if reset assert/deassert is supported +* +* @return Supported reset actions +* +* @note Here bit fields are used decide supported actions as defined +* below: +* BIT 1 - Assert/Deassert +* BIT 2 - Pulse +* BIT 3 - Reset status +* Bit set indicates corresponding action is supported and +* vice versa. +******************************************************************************/ +#define XRESETPS_SUPPORTED_ACT(ResetSupport, PulseSupport, AssertSupport) \ + ((ResetSupport << 2) | (PulseSupport << 1) | AssertSupport) + +/****************************************************************************/ +/** +* +* Check if assert/dessert reset is supported. +* +* @param Actions is supported reset actions +* +* @return 1 - Supported +* 0 - Not Supported +* +* @note None. +* +******************************************************************************/ +#define XRESETPS_CHK_ASSERT_SUPPORT(Actions) ((Actions & 0x1)) + +/****************************************************************************/ +/** +* +* Check if pulse reset is supported. +* +* @param Actions is supported reset actions +* +* @return 1 - Supported +* 0 - Not Supported +* +* @note None. +* +******************************************************************************/ +#define XRESETPS_CHK_PULSE_SUPPORT(Actions) ((Actions & 0x2) >> 1) + +/****************************************************************************/ +/** +* +* Check if Status check is supported. +* +* @param Actions is supported reset actions +* +* @return 1 - Supported +* 0 - Not Supported +* +* @note None. +* +******************************************************************************/ +#define XRESETPS_CHK_STATUS_SUPPORT(Actions) ((Actions & 0x4) >> 2) + +/****************************************************************************/ +/** +* +* Read the given register. +* +* @param RegAddress is the address of the register to read +* +* @return The 32-bit value of the register +* +* @note None. +* +******************************************************************************/ +#define XResetPs_ReadReg(RegAddress) \ + Xil_In32((u32)RegAddress) + +/****************************************************************************/ +/** +* +* Write the given register. +* +* @param RegAddress is the address of the register to write +* @param Data is the 32-bit value to write to the register +* +* @return None. +* +* @note None. +* +******************************************************************************/ +#define XResetPs_WriteReg(RegAddress, Data) \ + Xil_Out32((u32)RegAddress, (u32)Data) + +/************************** Function Prototypes ******************************/ + +/* + * Lookup configuration in xresetps_sinit.c. + */ +XResetPs_Config *XResetPs_LookupConfig(u16 DeviceId); + +/* + * Interface functions in xresetps.c + */ +XStatus XResetPs_CfgInitialize(XResetPs *InstancePtr, + XResetPs_Config *ConfigPtr, u32 EffectiveAddress); +XStatus XResetPs_ResetAssert(XResetPs *InstancePtr, + const XResetPs_RstId ResetID); +XStatus XResetPs_ResetDeassert(XResetPs *InstancePtr, + const XResetPs_RstId ResetID); +XStatus XResetPs_ResetPulse(XResetPs *InstancePtr, + const XResetPs_RstId ResetID); +XStatus XResetPs_ResetStatus(XResetPs *InstancePtr, + const XResetPs_RstId ResetID, XResetPs_RstStatus *Status); + +#ifdef __cplusplus +} +#endif +#endif /* end of protection macro */ +/** @} */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/resetps_v1_0/src/xresetps_g.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/resetps_v1_0/src/xresetps_g.c new file mode 100644 index 000000000..529215d65 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/resetps_v1_0/src/xresetps_g.c @@ -0,0 +1,53 @@ + +/******************************************************************* +* +* CAUTION: This file is automatically generated by HSI. +* Version: +* DO NOT EDIT. +* +* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.* +*Permission is hereby granted, free of charge, to any person obtaining a copy +*of this software and associated documentation files (the Software), to deal +*in the Software without restriction, including without limitation the rights +*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +*copies of the Software, and to permit persons to whom the Software is +*furnished to do so, subject to the following conditions: +* +*The above copyright notice and this permission notice shall be included in +*all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +*(a) running on a Xilinx device, or +*(b) that interact with a Xilinx device through a bus or interconnect. +* +*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +* +*Except as contained in this notice, the name of the Xilinx shall not be used +*in advertising or otherwise to promote the sale, use or other dealings in +*this Software without prior written authorization from Xilinx. +* + +* +* Description: Driver configuration +* +*******************************************************************/ + +#include "xparameters.h" +#include "xresetps.h" + +/* +* The configuration table for devices +*/ + +XResetPs_Config XResetPs_ConfigTable[XPAR_XRESETPS_NUM_INSTANCES] = +{ + { + XPAR_XRESETPS_DEVICE_ID, + XPAR_XRESETPS_BASEADDR, + } +}; diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/resetps_v1_0/src/xresetps_hw.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/resetps_v1_0/src/xresetps_hw.h new file mode 100644 index 000000000..a97162d75 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/resetps_v1_0/src/xresetps_hw.h @@ -0,0 +1,327 @@ +/****************************************************************************** +* +* Copyright (C) 2017 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xresetps_hw.h +* @addtogroup xresetps_v1_0 +* @{ +* +* This file contains the hardware interface to the System Reset controller. +* +* 
+* MODIFICATION HISTORY:
+* Ver   Who    Date     Changes
+* ----- ------ -------- ---------------------------------------------
+* 1.00  cjp    09/05/17 First release
+*
+* +******************************************************************************/ +#ifndef XRESETPS_HW_H /* prevent circular inclusions */ +#define XRESETPS_HW_H /* by using protection macros */ + +/***************************** Include Files *********************************/ +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_io.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/************************** Constant Definitions *****************************/ +/* Register address defines */ +/* CRF_APB defines */ +#define XRESETPS_CRF_APB_BASE (0XFD1A0000U) +/* RST_FPD_TOP Address and mask definations */ +#define XRESETPS_CRF_APB_RST_FPD_TOP \ + ((XRESETPS_CRF_APB_BASE) + ((u32)0X00000100U)) +#define PCIE_CFG_RESET_MASK ((u32)0X00080000U) +#define PCIE_BRIDGE_RESET_MASK ((u32)0X00040000U) +#define PCIE_CTRL_RESET_MASK ((u32)0X00020000U) +#define DP_RESET_MASK ((u32)0X00010000U) +#define SWDT_RESET_MASK ((u32)0X00008000U) +#define AFI_FM5_RESET_MASK ((u32)0X00001000U) +#define AFI_FM4_RESET_MASK ((u32)0X00000800U) +#define AFI_FM3_RESET_MASK ((u32)0X00000400U) +#define AFI_FM2_RESET_MASK ((u32)0X00000200U) +#define AFI_FM1_RESET_MASK ((u32)0X00000100U) +#define AFI_FM0_RESET_MASK ((u32)0X00000080U) +#define GDMA_RESET_MASK ((u32)0X00000040U) +#define GPU_PP1_RESET_MASK ((u32)0X00000020U) +#define GPU_PP0_RESET_MASK ((u32)0X00000010U) +#define GPU_RESET_MASK ((u32)0X00000008U) +#define GT_RESET_MASK ((u32)0X00000004U) +#define SATA_RESET_MASK ((u32)0X00000002U) +/* RST_FPD_APU Address and mask definations */ +#define XRESETPS_CRF_APB_RST_FPD_APU \ + ((XRESETPS_CRF_APB_BASE) + ((u32)0X00000104U)) +#define ACPU3_PWRON_RESET_MASK ((u32)0X00002000U) +#define ACPU2_PWRON_RESET_MASK ((u32)0X00001000U) +#define ACPU1_PWRON_RESET_MASK ((u32)0X00000800U) +#define ACPU0_PWRON_RESET_MASK ((u32)0X00000400U) +#define APU_L2_RESET_MASK ((u32)0X00000100U) +#define ACPU3_RESET_MASK ((u32)0X00000008U) +#define ACPU2_RESET_MASK ((u32)0X00000004U) +#define ACPU1_RESET_MASK ((u32)0X00000002U) +#define ACPU0_RESET_MASK ((u32)0X00000001U) +/* RST_DDR_SS Address and mask definations */ +#define XRESETPS_CRF_APB_RST_DDR_SS \ + ((XRESETPS_CRF_APB_BASE) + ((u32)0X00000108U)) +#define DDR_RESET_MASK ((u32)0X00000008U) +#define DDR_APM_RESET_MASK ((u32)0X00000004U) +/* APLL_CTRL Address and mask definations */ +#define XRESETPS_CRF_APB_APLL_CTRL \ + ((XRESETPS_CRF_APB_BASE) + ((u32)0X00000020U)) +#define APLL_RESET_MASK ((u32)0X00000001U) +/* DPLL_CTRL Address and mask definations */ +#define XRESETPS_CRF_APB_DPLL_CTRL \ + ((XRESETPS_CRF_APB_BASE) + ((u32)0X0000002CU)) +#define DPLL_RESET_MASK ((u32)0X00000001U) +/* VPLL_CTRL Address and mask definations */ +#define XRESETPS_CRF_APB_VPLL_CTRL \ + ((XRESETPS_CRF_APB_BASE) + ((u32)0X00000038U)) +#define VPLL_RESET_MASK ((u32)0X00000001U) + +/* CRL_APB defines */ +#define XRESETPS_CRL_APB_BASE (0XFF5E0000U) +/* RESET_CTRL Address and mask definations */ +#define XRESETPS_CRL_APB_RESET_CTRL \ + ((XRESETPS_CRL_APB_BASE) + ((u32)0X00000218U)) +#define SOFT_RESET_MASK ((u32)0X00000010U) +/* RST_LPD_IOU0 Address and mask definations */ +#define XRESETPS_CRL_APB_RST_LPD_IOU0 \ + ((XRESETPS_CRL_APB_BASE) + ((u32)0X00000230U)) +#define GEM0_RESET_MASK ((u32)0X00000001U) +#define GEM1_RESET_MASK ((u32)0X00000002U) +#define GEM2_RESET_MASK ((u32)0X00000004U) +#define GEM3_RESET_MASK ((u32)0X00000008U) +/* RST_LPD_IOU2 Address and mask definations */ +#define XRESETPS_CRL_APB_RST_LPD_IOU2 \ + ((XRESETPS_CRL_APB_BASE) + ((u32)0X00000238U)) +#define QSPI_RESET_MASK ((u32)0X00000001U) +#define UART0_RESET_MASK ((u32)0X00000002U) +#define UART1_RESET_MASK ((u32)0X00000004U) +#define SPI0_RESET_MASK ((u32)0X00000008U) +#define SPI1_RESET_MASK ((u32)0X00000010U) +#define SDIO0_RESET_MASK ((u32)0X00000020U) +#define SDIO1_RESET_MASK ((u32)0X00000040U) +#define CAN0_RESET_MASK ((u32)0X00000080U) +#define CAN1_RESET_MASK ((u32)0X00000100U) +#define I2C0_RESET_MASK ((u32)0X00000200U) +#define I2C1_RESET_MASK ((u32)0X00000400U) +#define TTC0_RESET_MASK ((u32)0X00000800U) +#define TTC1_RESET_MASK ((u32)0X00001000U) +#define TTC2_RESET_MASK ((u32)0X00002000U) +#define TTC3_RESET_MASK ((u32)0X00004000U) +#define SWDT_RESET_MASK ((u32)0X00008000U) +#define NAND_RESET_MASK ((u32)0X00010000U) +#define ADMA_RESET_MASK ((u32)0X00020000U) +#define GPIO_RESET_MASK ((u32)0X00040000U) +#define IOU_CC_RESET_MASK ((u32)0X00080000U) +#define TIMESTAMP_RESET_MASK ((u32)0X00100000U) +/* RST_LPD_TOP Address and mask definations */ +#define XRESETPS_CRL_APB_RST_LPD_TOP \ + ((XRESETPS_CRL_APB_BASE) + ((u32)0X0000023CU)) +#define RPU_R50_RESET_MASK ((u32)0X00000001U) +#define RPU_R51_RESET_MASK ((u32)0X00000002U) +#define RPU_AMBA_RESET_MASK ((u32)0X00000004U) +#define OCM_RESET_MASK ((u32)0X00000008U) +#define RPU_PGE_RESET_MASK ((u32)0X00000010U) +#define USB0_CORERESET_MASK ((u32)0X00000040U) +#define USB1_CORERESET_MASK ((u32)0X00000080U) +#define USB0_HIBERRESET_MASK ((u32)0X00000100U) +#define USB1_HIBERRESET_MASK ((u32)0X00000200U) +#define USB0_APB_RESET_MASK ((u32)0X00000400U) +#define USB1_APB_RESET_MASK ((u32)0X00000800U) +#define IPI_RESET_MASK ((u32)0X00004000U) +#define APM_RESET_MASK ((u32)0X00008000U) +#define RTC_RESET_MASK ((u32)0X00010000U) +#define SYSMON_RESET_MASK ((u32)0X00020000U) +#define AFI_FM6_RESET_MASK ((u32)0X00080000U) +#define LPD_SWDT_RESET_MASK ((u32)0X00100000U) +#define FPD_RESET_MASK ((u32)0X00800000U) +/* RST_LPD_DBG Address and mask definations */ +#define XRESETPS_CRL_APB_RST_LPD_DBG \ + ((XRESETPS_CRL_APB_BASE) + ((u32)0X00000240U)) +#define RPU_DBG1_RESET_MASK ((u32)0X00000020U) +#define RPU_DBG0_RESET_MASK ((u32)0X00000010U) +#define DBG_LPD_RESET_MASK ((u32)0X00000002U) +#define DBG_FPD_RESET_MASK ((u32)0X00000001U) +/* IOPLL_CTRL Address and mask definations */ +#define XRESETPS_CRL_APB_IOPLL_CTRL \ + ((XRESETPS_CRL_APB_BASE) + ((u32)0X00000020U)) +#define IOPLL_RESET_MASK ((u32)0X00000001U) +/* RPLL_CTRL Address and mask definations */ +#define XRESETPS_CRL_APB_RPLL_CTRL \ + ((XRESETPS_CRL_APB_BASE) + ((u32)0X00000030U)) +#define RPLL_RESET_MASK ((u32)0X00000001U) +#define RPLL_BYPASS_MASK ((u32)0X00000008U) + +/* PMU_IOM defines */ +#define XRESETPS_PMU_IOM_BASE (0XFFD40000U) +/* PMU_IOM_GPO3 Address and mask definations */ +#define XRESETPS_PMU_IOM_GPO3_CTRL \ + ((XRESETPS_PMU_IOM_BASE) + ((u32)0X0000001CU)) +#define GPO3_PL0_RESET_MASK ((u32)0X00000001U) +#define GPO3_PL1_RESET_MASK ((u32)0X00000002U) +#define GPO3_PL2_RESET_MASK ((u32)0X00000004U) +#define GPO3_PL3_RESET_MASK ((u32)0X00000008U) +#define GPO3_PL4_RESET_MASK ((u32)0X00000010U) +#define GPO3_PL5_RESET_MASK ((u32)0X00000020U) +#define GPO3_PL6_RESET_MASK ((u32)0X00000040U) +#define GPO3_PL7_RESET_MASK ((u32)0X00000080U) +#define GPO3_PL8_RESET_MASK ((u32)0X00000100U) +#define GPO3_PL9_RESET_MASK ((u32)0X00000200U) +#define GPO3_PL10_RESET_MASK ((u32)0X00000400U) +#define GPO3_PL11_RESET_MASK ((u32)0X00000800U) +#define GPO3_PL12_RESET_MASK ((u32)0X00001000U) +#define GPO3_PL13_RESET_MASK ((u32)0X00002000U) +#define GPO3_PL14_RESET_MASK ((u32)0X00004000U) +#define GPO3_PL15_RESET_MASK ((u32)0X00008000U) +#define GPO3_PL16_RESET_MASK ((u32)0X00010000U) +#define GPO3_PL17_RESET_MASK ((u32)0X00020000U) +#define GPO3_PL18_RESET_MASK ((u32)0X00040000U) +#define GPO3_PL19_RESET_MASK ((u32)0X00080000U) +#define GPO3_PL20_RESET_MASK ((u32)0X00100000U) +#define GPO3_PL21_RESET_MASK ((u32)0X00200000U) +#define GPO3_PL22_RESET_MASK ((u32)0X00400000U) +#define GPO3_PL23_RESET_MASK ((u32)0X00800000U) +#define GPO3_PL24_RESET_MASK ((u32)0X01000000U) +#define GPO3_PL25_RESET_MASK ((u32)0X02000000U) +#define GPO3_PL26_RESET_MASK ((u32)0X04000000U) +#define GPO3_PL27_RESET_MASK ((u32)0X08000000U) +#define GPO3_PL28_RESET_MASK ((u32)0X10000000U) +#define GPO3_PL29_RESET_MASK ((u32)0X20000000U) +#define GPO3_PL30_RESET_MASK ((u32)0X40000000U) +#define GPO3_PL31_RESET_MASK ((u32)0X80000000U) + +/* PMU_LCL defines */ +#define XRESETPS_PMU_LCL_BASE (0XFFD60000U) +/* GPO Read control address */ +#define XRESETPS_PMU_LCL_READ_CTRL \ + ((XRESETPS_PMU_LCL_BASE) + ((u32)0X0000021CU)) + +/* PMU_GLB defines */ +#define XRESETPS_PMU_GLB_BASE (0XFFD80000U) +/* PMU_GLB_RST Address and mask definations */ +#define XRESETPS_PMU_GLB_RST_CTRL ((XRESETPS_PMU_GLB_BASE) + ((u32)0X00000608U)) +#define RPU_LS_RESET_MASK ((u32)0X00000100U) +#define FPD_APU_RESET_MASK ((u32)0X00000200U) +#define PS_ONLY_RESET_MASK ((u32)0X00000400U) +/* PMU_GLB_PS Address and mask definations */ +#define XRESETPS_PMU_GLB_PS_CTRL ((XRESETPS_PMU_GLB_BASE) + ((u32)0X00000004U)) +#define PROG_ENABLE_MASK ((u32)0X00000002U) +#define PROG_GATE_MASK ((u32)0X00000001U) +/* PMU_GLB_AIB Address and mask definations */ +#define XRESETPS_PMU_GLB_AIB_CTRL ((XRESETPS_PMU_GLB_BASE) + ((u32)0X00000600U)) +#define LPD_AFI_FM_ISO_MASK ((u32)0X00000001U) +#define LPD_AFI_FS_ISO_MASK ((u32)0X00000002U) +#define FPD_AFI_FM_ISO_MASK ((u32)0X00000004U) +#define FPD_AFI_FS_ISO_MASK ((u32)0X00000008U) +#define AIB_ISO_CTRL_MASK (LPD_AFI_FM_ISO_MASK | LPD_AFI_FS_ISO_MASK | \ + FPD_AFI_FM_ISO_MASK | FPD_AFI_FS_ISO_MASK) +/* PMU_GLB_AIB status Address and mask definations */ +#define XRESETPS_PMU_GLB_AIB_STATUS \ + ((XRESETPS_PMU_GLB_BASE) + ((u32)0X00000604U)) +#define AIB_ISO_STATUS_MASK (AIB_ISO_CTRL_MASK) +/* PMU_GLB_PWR status Address and mask definations */ +#define XRESETPS_PMU_GLB_PWR_STATUS \ + ((XRESETPS_PMU_GLB_BASE) + ((u32)0X00000100U)) +#define FPD_PSCHK_MASK ((u32)0x00400000U) +#define PCIE_CTRL_PSCHK_MASK (FPD_PSCHK_MASK) +#define DP_PSCHK_MASK (FPD_PSCHK_MASK) +#define SATA_PSCHK_MASK (FPD_PSCHK_MASK) +#define R50_PSCHK_MASK ((u32)0x00000400U) +#define R51_PSCHK_MASK ((u32)0x00000800U) +#define GPU_PP0_PSCHK_MASK (((u32)0x00000010U) | (FPD_PSCHK_MASK)) +#define GPU_PP1_PSCHK_MASK (((u32)0x00000020U) | (FPD_PSCHK_MASK)) +#define GPU_PSCHK_MASK ((GPU_PP0_PSCHK_MASK) | \ + (GPU_PP1_PSCHK_MASK) | (FPD_PSCHK_MASK)) + +/* LPD_SLCR defines */ +#define XRESETPS_LPD_SCR_BASE (0XFF410000U) +/* LPD_SCR_AXIISO_REQ and LPD_SCR_AXIISO_ACK Address and mask definations */ +#define XRESETPS_LPD_SCR_AXIISO_REQ_CTRL \ + ((XRESETPS_LPD_SCR_BASE) + ((u32)0X00003030U)) +#define XRESETPS_LPD_SCR_AXIISO_ACK_CTRL \ + ((XRESETPS_LPD_SCR_BASE) + ((u32)0X00003040U)) +#define RPU0_MASTER_ISO_MASK ((u32)0X00010000U) +#define RPU1_MASTER_ISO_MASK ((u32)0X00020000U) +#define RPU_MASTER_ISO_MASK (RPU0_MASTER_ISO_MASK | RPU1_MASTER_ISO_MASK) +#define RPU0_SLAVE_ISO_MASK ((u32)0X00040000U) +#define RPU1_SLAVE_ISO_MASK ((u32)0X00080000U) +#define RPU_SLAVE_ISO_MASK (RPU0_SLAVE_ISO_MASK | RPU1_SLAVE_ISO_MASK) +#define FPD_OCM_ISO_MASK ((u32)0X00000008U) +#define FPD_LPDIBS_ISO_MASK ((u32)0X00000004U) +#define AFIFS1_ISO_MASK ((u32)0X00000002U) +#define AFIFS0_ISO_MASK ((u32)0X00000001U) +#define FPD_TO_LPD_ISO_MASK (FPD_LPDIBS_ISO_MASK | FPD_OCM_ISO_MASK | \ + AFIFS0_ISO_MASK | AFIFS1_ISO_MASK) +#define LPD_DDR_ISO_MASK ((u32)0X08000000U) +#define FPD_MAIN_ISO_MASK ((u32)0X01000000U) +#define LPD_TO_FPD_ISO_MASK (LPD_DDR_ISO_MASK | FPD_MAIN_ISO_MASK) +/* LPD_SLCR_APBISO_REQ Address and mask definations */ +#define XRESETPS_LPD_SLCR_APBISO_REQ_CTRL \ + ((XRESETPS_LPD_SCR_BASE) + ((u32)0X00003048U)) +#define GPU_ISO_MASK ((u32)0X00000001U) + +/* CSU defines */ +#define XRESETPS_CSU_BASE (0xFFCA0000U) +#define XRESETPS_CSU_VERSION_REG ((XRESETPS_CSU_BASE) + ((u32)0x00000044U)) +#define XRESETPS_PLATFORM_PS_VER1 ((u32)0x00000000U) +#define PS_VERSION_MASK ((u32)0x0000000FU) + +/* Timeout delay defines */ +#define XRESETPS_RST_PROP_DELAY (0xFU) +#define XRESETPS_AIB_ISO_DELAY (0xFU) +#define XRESETPS_AIB_PSPL_DELAY (0xFU) +#define XRESETPS_PULSE_PROP_DELAY (0xFU) + +/* AIB ack reconfirmation count */ +#define XRESETPS_AIB_PSPL_RECONFIRM_CNT \ + (0x2U) + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ + + +/************************** Variable Definitions *****************************/ + +#ifdef __cplusplus +} +#endif +#endif /* end of protection macro */ +/** @} */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/resetps_v1_0/src/xresetps_sinit.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/resetps_v1_0/src/xresetps_sinit.c new file mode 100644 index 000000000..eebdc9d1c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/resetps_v1_0/src/xresetps_sinit.c @@ -0,0 +1,94 @@ +/****************************************************************************** +* +* Copyright (C) 2017 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xresetps_sinit.c +* @addtogroup xresetps_v1_0 +* @{ +* +* This file contains method for static initialization (compile-time) of the +* driver. +* +* 
+* MODIFICATION HISTORY:
+* Ver   Who    Date     Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00  cjp    09/05/17 First release
+*
+* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xresetps.h" +#include "xparameters.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + + +/***************** Macros (Inline Functions) Definitions *********************/ + +/*************************** Variable Definitions ****************************/ +extern XResetPs_Config XResetPs_ConfigTable[XPAR_XRESETPS_NUM_INSTANCES]; + +/************************** Function Prototypes ******************************/ + +/*****************************************************************************/ +/** +* Lookup the device configuration based on the unique device ID. The table +* contains the configuration info for each device in the system. +* +* @param DeviceId is the unique device ID of the device being looked up. +* +* @return A pointer to the configuration table entry corresponding to the +* given device ID, or NULL if no match is found. +* +* @note None. +* +******************************************************************************/ +XResetPs_Config *XResetPs_LookupConfig(u16 DeviceId) +{ + XResetPs_Config *CfgPtr = NULL; + u32 Index; + + for (Index = 0U; Index < (u32)XPAR_XRESETPS_NUM_INSTANCES; Index++) { + if (XResetPs_ConfigTable[Index].DeviceId == DeviceId) { + CfgPtr = &XResetPs_ConfigTable[Index]; + break; + } + } + return (XResetPs_Config *)CfgPtr; +} +/** @} */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/rtcpsu_v1_3/src/Makefile b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/rtcpsu_v1_5/src/Makefile similarity index 100% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/rtcpsu_v1_3/src/Makefile rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/rtcpsu_v1_5/src/Makefile diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/rtcpsu_v1_5/src/xrtcpsu.c similarity index 96% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu.c rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/rtcpsu_v1_5/src/xrtcpsu.c index c91f61279..c09d1e73c 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/rtcpsu_v1_5/src/xrtcpsu.c @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* Copyright (C) 2015 - 2017 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -18,8 +18,8 @@ * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. @@ -33,7 +33,7 @@ /** * * @file xrtcpsu.c -* @addtogroup rtcpsu_v1_0 +* @addtogroup rtcpsu_v1_5 * @{ * * Functions in this file are the minimum required functions for the XRtcPsu @@ -53,6 +53,8 @@ * 1.2 02/15/16 Corrected Calibration mask and Fractional * mask in CalculateCalibration API. * 1.3 vak 04/25/16 Corrected the RTC read and write time logic(cr#948833). +* 1.5 ms 08/27/17 Fixed compilation warnings. +* ms 08/29/17 Updated code as per source code style. * * ******************************************************************************/ @@ -166,7 +168,7 @@ s32 XRtcPsu_CfgInitialize(XRtcPsu *InstancePtr, XRtcPsu_Config *ConfigPtr, *****************************************************************************/ static void XRtcPsu_StubHandler(void *CallBackRef, u32 Event) { - (void *) CallBackRef; + (void) CallBackRef; (void) Event; /* Assert occurs always since this is a stub and should never be called */ Xil_AssertVoidAlways(); @@ -218,7 +220,9 @@ void XRtcPsu_SetTime(XRtcPsu *InstancePtr,u32 Time) *****************************************************************************/ u32 XRtcPsu_GetCurrentTime(XRtcPsu *InstancePtr) { - u32 Status, IntMask, CurrTime; + u32 Status; + u32 IntMask; + u32 CurrTime; IntMask = XRtcPsu_ReadReg(InstancePtr->RtcConfig.BaseAddr + XRTC_INT_MSK_OFFSET); @@ -294,9 +298,9 @@ void XRtcPsu_SetAlarm(XRtcPsu *InstancePtr, u32 Alarm, u32 Periodic) * format and saves it in the DT structure variable. It also reports the weekday. * * @param Seconds is the time value that has to be shown in DateTime -* format. +* format. * @param dt is the DateTime format variable that stores the translated -* time. +* time. * * @return None. * @@ -305,7 +309,10 @@ void XRtcPsu_SetAlarm(XRtcPsu *InstancePtr, u32 Alarm, u32 Periodic) *****************************************************************************/ void XRtcPsu_SecToDateTime(u32 Seconds, XRtcPsu_DT *dt) { - u32 CurrentTime, TempDays, Leap, DaysPerMonth; + u32 CurrentTime; + u32 TempDays; + u32 DaysPerMonth; + u32 Leap = 0U; CurrentTime = Seconds; dt->Sec = CurrentTime % 60U; @@ -364,7 +371,8 @@ void XRtcPsu_SecToDateTime(u32 Seconds, XRtcPsu_DT *dt) *****************************************************************************/ u32 XRtcPsu_DateTimeToSec(XRtcPsu_DT *dt) { - u32 i, Days; + u32 i; + u32 Days; u32 Seconds; Xil_AssertNonvoid(dt != NULL); @@ -414,8 +422,14 @@ u32 XRtcPsu_DateTimeToSec(XRtcPsu_DT *dt) void XRtcPsu_CalculateCalibration(XRtcPsu *InstancePtr,u32 TimeReal, u32 CrystalOscFreq) { - u32 ReadTime, SetTime; - u32 Cprev,Fprev,Cnew,Fnew,Xf,Calibration; + u32 ReadTime; + u32 SetTime; + u32 Cprev; + u32 Fprev; + u32 Cnew; + u32 Fnew; + u32 Calibration; + float Xf; Xil_AssertVoid(TimeReal != 0U); Xil_AssertVoid(CrystalOscFreq != 0U); diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/rtcpsu_v1_5/src/xrtcpsu.h similarity index 95% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu.h rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/rtcpsu_v1_5/src/xrtcpsu.h index 164ddf64a..832047030 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu.h +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/rtcpsu_v1_5/src/xrtcpsu.h @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* Copyright (C) 2015 - 2017 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -18,8 +18,8 @@ * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. @@ -32,7 +32,7 @@ /*****************************************************************************/ /** * @file xrtcpsu.h -* @addtogroup rtcpsu_v1_0 +* @addtogroup rtcpsu_v1_5 * @{ * @details * @@ -101,6 +101,14 @@ * 1.1 kvn 09/25/15 Modify control register to enable battery * switching when vcc_psaux is not available. * 1.3 vak 04/25/16 Corrected the RTC read and write time logic(cr#948833). +* 1.4 MNK 01/27/17 Corrected calibration and frequency macros based on +* rtc input oscillator frequency ( 32.768Khz). +* ms 03/17/17 Added readme.txt file in examples folder for doxygen +* generation. +* ms 04/10/17 Modified filename tag in examples to include them in +* doxygen examples. +* 1.5 ms 08/27/17 Fixed compilation warnings in xrtcpsu.c file. +* ms 08/29/17 Updated the code as per source code style. * * ******************************************************************************/ @@ -203,8 +211,8 @@ typedef struct { /***************** Macros (Inline Functions) Definitions *********************/ -#define XRTC_CALIBRATION_VALUE 0x00198231U -#define XRTC_TYPICAL_OSC_FREQ 33330U +#define XRTC_CALIBRATION_VALUE 0x8000U +#define XRTC_TYPICAL_OSC_FREQ 32768U /****************************************************************************/ /** diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/rtcpsu_v1_3/src/xrtcpsu_g.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/rtcpsu_v1_5/src/xrtcpsu_g.c similarity index 90% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/rtcpsu_v1_3/src/xrtcpsu_g.c rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/rtcpsu_v1_5/src/xrtcpsu_g.c index 5913cd8d4..ef49025c7 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/rtcpsu_v1_3/src/xrtcpsu_g.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/rtcpsu_v1_5/src/xrtcpsu_g.c @@ -5,7 +5,7 @@ * Version: * DO NOT EDIT. * -* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.* +* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.* *Permission is hereby granted, free of charge, to any person obtaining a copy *of this software and associated documentation files (the Software), to deal *in the Software without restriction, including without limitation the rights @@ -44,7 +44,7 @@ * The configuration table for devices */ -XRtcPsu_Config XRtcPsu_ConfigTable[] = +XRtcPsu_Config XRtcPsu_ConfigTable[XPAR_XRTCPSU_NUM_INSTANCES] = { { XPAR_PSU_RTC_DEVICE_ID, diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/rtcpsu_v1_3/src/xrtcpsu_hw.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/rtcpsu_v1_5/src/xrtcpsu_hw.h similarity index 98% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/rtcpsu_v1_3/src/xrtcpsu_hw.h rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/rtcpsu_v1_5/src/xrtcpsu_hw.h index 532ef7e3c..b535359eb 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/rtcpsu_v1_3/src/xrtcpsu_hw.h +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/rtcpsu_v1_5/src/xrtcpsu_hw.h @@ -18,8 +18,8 @@ * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. @@ -33,7 +33,7 @@ /** * * @file xrtcpsu_hw.h -* @addtogroup rtcpsu_v1_0 +* @addtogroup rtcpsu_v1_5 * @{ * * This header file contains the identifiers and basic driver functions (or diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/rtcpsu_v1_3/src/xrtcpsu_intr.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/rtcpsu_v1_5/src/xrtcpsu_intr.c similarity index 98% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/rtcpsu_v1_3/src/xrtcpsu_intr.c rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/rtcpsu_v1_5/src/xrtcpsu_intr.c index 89d3cd990..1f5f831f7 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/rtcpsu_v1_3/src/xrtcpsu_intr.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/rtcpsu_v1_5/src/xrtcpsu_intr.c @@ -18,8 +18,8 @@ * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. @@ -33,7 +33,7 @@ /** * * @file xrtcpsu_intr.c -* @addtogroup rtcpsu_v1_0 +* @addtogroup rtcpsu_v1_5 * @{ * * This file contains functions related to RTC interrupt handling. diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu_selftest.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/rtcpsu_v1_5/src/xrtcpsu_selftest.c similarity index 97% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu_selftest.c rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/rtcpsu_v1_5/src/xrtcpsu_selftest.c index 67c562c64..2678d8149 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu_selftest.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/rtcpsu_v1_5/src/xrtcpsu_selftest.c @@ -18,8 +18,8 @@ * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. @@ -33,7 +33,7 @@ /** * * @file xrtcpsu_selftest.c -* @addtogroup rtcpsu_v1_0 +* @addtogroup rtcpsu_v1_5 * @{ * * This file contains the self-test functions for the XRtcPsu driver. diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/rtcpsu_v1_3/src/xrtcpsu_sinit.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/rtcpsu_v1_5/src/xrtcpsu_sinit.c similarity index 96% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/rtcpsu_v1_3/src/xrtcpsu_sinit.c rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/rtcpsu_v1_5/src/xrtcpsu_sinit.c index d3a8b7dfc..32ea4e596 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/rtcpsu_v1_3/src/xrtcpsu_sinit.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/rtcpsu_v1_5/src/xrtcpsu_sinit.c @@ -18,8 +18,8 @@ * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. @@ -33,7 +33,7 @@ /** * * @file xrtcpsu_sinit.c -* @addtogroup rtcpsu_v1_0 +* @addtogroup rtcpsu_v1_5 * @{ * * This file contains the implementation of the XRtcPsu driver's static diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/scugic_v3_5/src/Makefile b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/scugic_v3_9/src/Makefile similarity index 100% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/scugic_v3_5/src/Makefile rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/scugic_v3_9/src/Makefile diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/xscugic.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/scugic_v3_9/src/xscugic.c similarity index 82% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/xscugic.c rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/scugic_v3_9/src/xscugic.c index bf7ac12e8..f6afc0e5a 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/xscugic.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/scugic_v3_9/src/xscugic.c @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2010 - 2016 Xilinx, Inc. All rights reserved. +* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -33,7 +33,7 @@ /** * * @file xscugic.c -* @addtogroup scugic_v3_1 +* @addtogroup scugic_v3_8 * @{ * * Contains required functions for the XScuGic driver for the Interrupt @@ -107,7 +107,17 @@ * and properly mask interrupt target processor value to modify * interrupt target processor register for a given interrupt ID * and cpu ID -* +* 3.6 pkp 20/01/17 Added new API XScuGic_Stop to Disable distributor and +* interrupts in case they are being used only by current cpu. +* It also removes current cpu from interrupt target registers +* for all interrupts. +* kvn 02/17/17 Add support for changing GIC CPU master at run time. +* kvn 02/28/17 Make the CpuId as static variable and Added new +* XScugiC_GetCpuId to access CpuId. +* 3.9 mus 02/21/18 Added new API's XScuGic_UnmapAllInterruptsFromCpu and +* XScuGic_InterruptUnmapFromCpu, These API's can be used +* by applications to unmap specific/all interrupts from +* target CPU. It fixes CR#992490. * * * @@ -127,6 +137,7 @@ /***************** Macros (Inline Functions) Definitions *********************/ /************************** Variable Definitions *****************************/ +static u32 CpuId = XPAR_CPU_ID; /**< CPU Core identifier */ /************************** Function Prototypes ******************************/ @@ -254,7 +265,7 @@ static void DistributorInit(XScuGic *InstancePtr, u32 CpuID) #endif RegValue = XScuGic_DistReadReg(InstancePtr, XSCUGIC_DIST_EN_OFFSET); - if (!(RegValue & XSCUGIC_EN_INT_MASK)) { + if ((RegValue & XSCUGIC_EN_INT_MASK) == 0U) { Xil_AssertVoid(InstancePtr != NULL); DoDistributorInit(InstancePtr, CpuID); return; @@ -353,7 +364,7 @@ s32 XScuGic_CfgInitialize(XScuGic *InstancePtr, u32 EffectiveAddr) { u32 Int_Id; - u32 Cpu_Id = (u32)XPAR_CPU_ID + (u32)1; + u32 Cpu_Id = CpuId + (u32)1; (void) EffectiveAddr; Xil_AssertNonvoid(InstancePtr != NULL); @@ -392,7 +403,7 @@ s32 XScuGic_CfgInitialize(XScuGic *InstancePtr, InstancePtr->Config->HandlerTable[Int_Id].CallBackRef = InstancePtr; } - + XScuGic_Stop(InstancePtr); DistributorInit(InstancePtr, Cpu_Id); CPUInitialize(InstancePtr); @@ -827,4 +838,183 @@ void XScuGic_InterruptMaptoCpu(XScuGic *InstancePtr, u8 Cpu_Id, u32 Int_Id) XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id), RegValue); } +/****************************************************************************/ +/** +* Unmaps specific SPI interrupt from the target CPU +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param Cpu_Id is a CPU number from which the interrupt has to be +* unmapped +* @param Int_Id is the IRQ source number to modify +* +* @return None. +* +* @note None +* +*****************************************************************************/ +void XScuGic_InterruptUnmapFromCpu(XScuGic *InstancePtr, u8 Cpu_Id, u32 Int_Id) +{ + u32 RegValue; + u8 BitPos; + + Xil_AssertVoid(InstancePtr != NULL); + + RegValue = XScuGic_DistReadReg(InstancePtr, + XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id)); + + /* + * Identify bit position corresponding to Int_Id and Cpu_Id, + * in interrupt target register and clear it + */ + BitPos = ((Int_Id % 4U) * 8U) + Cpu_Id; + RegValue &= (~ ( 1U << BitPos )); + XScuGic_DistWriteReg(InstancePtr, + XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id), + RegValue); +} +/****************************************************************************/ +/** +* Unmaps all SPI interrupts from the target CPU +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param Cpu_Id is a CPU number from which the interrupts has to be +* unmapped +* +* @return None. +* +* @note None +* +*****************************************************************************/ +void XScuGic_UnmapAllInterruptsFromCpu(XScuGic *InstancePtr, u8 Cpu_Id) +{ + u32 Int_Id; + u32 Target_Cpu; + u32 LocalCpuID = (1U << Cpu_Id); + + Xil_AssertVoid(InstancePtr != NULL); + + LocalCpuID |= LocalCpuID << 8U; + LocalCpuID |= LocalCpuID << 16U; + + for (Int_Id = 32U; Int_Id * @@ -322,6 +344,11 @@ void XScuGic_GetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id, void XScuGic_SetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id, u8 Priority, u8 Trigger); void XScuGic_InterruptMaptoCpu(XScuGic *InstancePtr, u8 Cpu_Id, u32 Int_Id); +void XScuGic_InterruptUnmapFromCpu(XScuGic *InstancePtr, u8 Cpu_Id, u32 Int_Id); +void XScuGic_UnmapAllInterruptsFromCpu(XScuGic *InstancePtr, u8 Cpu_Id); +void XScuGic_Stop(XScuGic *InstancePtr); +void XScuGic_SetCpuID(u32 CpuCoreId); +u32 XScuGic_GetCpuID(void); /* * Initialization functions in xscugic_sinit.c */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/scugic_v3_5/src/xscugic_g.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/scugic_v3_9/src/xscugic_g.c similarity index 87% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/scugic_v3_5/src/xscugic_g.c rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/scugic_v3_9/src/xscugic_g.c index ff1955d3a..19959e4bf 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/scugic_v3_5/src/xscugic_g.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/scugic_v3_9/src/xscugic_g.c @@ -5,7 +5,7 @@ * Version: * DO NOT EDIT. * -* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.* +* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.* *Permission is hereby granted, free of charge, to any person obtaining a copy *of this software and associated documentation files (the Software), to deal *in the Software without restriction, including without limitation the rights @@ -44,12 +44,13 @@ * The configuration table for devices */ -XScuGic_Config XScuGic_ConfigTable[] = +XScuGic_Config XScuGic_ConfigTable[XPAR_XSCUGIC_NUM_INSTANCES] = { { XPAR_PSU_ACPU_GIC_DEVICE_ID, XPAR_PSU_ACPU_GIC_BASEADDR, - XPAR_PSU_ACPU_GIC_DIST_BASEADDR + XPAR_PSU_ACPU_GIC_DIST_BASEADDR, + {{0}} /**< Initialize the HandlerTable to 0 */ } }; diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/xscugic_hw.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/scugic_v3_9/src/xscugic_hw.c similarity index 88% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/xscugic_hw.c rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/scugic_v3_9/src/xscugic_hw.c index 626779720..6604e3a55 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/xscugic_hw.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/scugic_v3_9/src/xscugic_hw.c @@ -33,7 +33,7 @@ /** * * @file xscugic_hw.c -* @addtogroup scugic_v3_1 +* @addtogroup scugic_v3_8 * @{ * * This file contains low-level driver functions that can be used to access the @@ -62,6 +62,13 @@ * XScuGic_SetPriTrigTypeByDistAddr and * XScuGic_GetPriTrigTypeByDistAddr here from xscugic.c * 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance. +* 3.6 kvn 02/17/17 Add support for changing GIC CPU master at run time. +* kvn 02/28/17 Make the CpuId as static variable and Added new +* XScugiC_GetCpuId to access CpuId. +* 3.9 mus 02/21/18 Added new API's XScuGic_InterruptUnmapFromCpuByDistAddr +* and XScuGic_UnmapAllInterruptsFromCpuByDistAddr, These +* API's can be used by applications to unmap specific/all +* interrupts from target CPU. It fixes CR#992490. * * * @@ -90,6 +97,7 @@ static XScuGic_Config *LookupConfigByBaseAddress(u32 CpuBaseAddress); /************************** Variable Definitions *****************************/ extern XScuGic_Config XScuGic_ConfigTable[XPAR_XSCUGIC_NUM_INSTANCES]; +extern u32 CpuId; /*****************************************************************************/ /** @@ -274,7 +282,7 @@ static void CPUInit(XScuGic_Config *Config) s32 XScuGic_DeviceInitialize(u32 DeviceId) { XScuGic_Config *Config; - u32 Cpu_Id = (u32)XPAR_CPU_ID + (u32)1; + u32 Cpu_Id = XScuGic_GetCpuID() + (u32)1; Config = &XScuGic_ConfigTable[(u32 )DeviceId]; @@ -567,4 +575,75 @@ void XScuGic_GetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id, *Trigger = (u8)(RegValue & XSCUGIC_INT_CFG_MASK); } + +/****************************************************************************/ +/** +* Unmaps specific SPI interrupt from the target CPU +* +* @param DistBaseAddress is the device base address +* @param Cpu_Id is a CPU number from which the interrupt has to be +* unmapped +* @param Int_Id is the IRQ source number to modify +* +* @return None. +* +* @note None +* +*****************************************************************************/ +void XScuGic_InterruptUnmapFromCpuByDistAddr(u32 DistBaseAddress, + u8 Cpu_Id, u32 Int_Id) +{ + u32 RegValue; + u8 BitPos; + + Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS); + + RegValue = XScuGic_ReadReg(DistBaseAddress, + XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id)); + + /* + * Identify bit position corresponding to Int_Id and Cpu_Id, + * in interrupt target register and clear it + */ + BitPos = ((Int_Id % 4U) * 8U) + Cpu_Id; + RegValue &= (~ ( 1U << BitPos )); + XScuGic_WriteReg(DistBaseAddress, + XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id), RegValue); +} + +/****************************************************************************/ +/** +* Unmaps all SPI interrupts from the target CPU +* +* @param DistBaseAddress is the device base address +* @param Cpu_Id is a CPU number from which the interrupts has to be +* unmapped +* +* @return None. +* +* @note None +* +*****************************************************************************/ +void XScuGic_UnmapAllInterruptsFromCpuByDistAddr(u32 DistBaseAddress, + u8 Cpu_Id) +{ + u32 Int_Id; + u32 Target_Cpu; + u32 LocalCpuID = (1U << Cpu_Id); + + LocalCpuID |= LocalCpuID << 8U; + LocalCpuID |= LocalCpuID << 16U; + + for (Int_Id = 32U; Int_Id * ******************************************************************************/ @@ -633,6 +637,10 @@ void XScuGic_SetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id, u8 Priority, u8 Trigger); void XScuGic_GetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id, u8 *Priority, u8 *Trigger); +void XScuGic_InterruptUnmapFromCpuByDistAddr(u32 DistBaseAddress, + u8 Cpu_Id, u32 Int_Id); +void XScuGic_UnmapAllInterruptsFromCpuByDistAddr(u32 DistBaseAddress, + u8 Cpu_Id); /************************** Variable Definitions *****************************/ #ifdef __cplusplus } diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scugic_v3_2/src/xscugic_intr.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/scugic_v3_9/src/xscugic_intr.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scugic_v3_2/src/xscugic_intr.c rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/scugic_v3_9/src/xscugic_intr.c index d05a51c5e..d82a60b9e 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scugic_v3_2/src/xscugic_intr.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/scugic_v3_9/src/xscugic_intr.c @@ -33,7 +33,7 @@ /** * * @file xscugic_intr.c -* @addtogroup scugic_v3_1 +* @addtogroup scugic_v3_8 * @{ * * This file contains the interrupt processing for the driver for the Xilinx diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/xscugic_selftest.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/scugic_v3_9/src/xscugic_selftest.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/xscugic_selftest.c rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/scugic_v3_9/src/xscugic_selftest.c index 47620d644..7b1028f9f 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/xscugic_selftest.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/scugic_v3_9/src/xscugic_selftest.c @@ -33,7 +33,7 @@ /** * * @file xscugic_selftest.c -* @addtogroup scugic_v3_1 +* @addtogroup scugic_v3_8 * @{ * * Contains diagnostic self-test functions for the XScuGic driver. diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/xscugic_sinit.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/scugic_v3_9/src/xscugic_sinit.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/xscugic_sinit.c rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/scugic_v3_9/src/xscugic_sinit.c index d30390ab8..842f31812 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/xscugic_sinit.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/scugic_v3_9/src/xscugic_sinit.c @@ -33,7 +33,7 @@ /** * * @file xscugic_sinit.c -* @addtogroup scugic_v3_1 +* @addtogroup scugic_v3_8 * @{ * * Contains static init functions for the XScuGic driver for the Interrupt diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sdps_v3_1/src/Makefile b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sdps_v3_4/src/Makefile similarity index 100% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sdps_v3_1/src/Makefile rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sdps_v3_4/src/Makefile diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sdps_v3_1/src/xsdps.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sdps_v3_4/src/xsdps.c similarity index 81% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sdps_v3_1/src/xsdps.c rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sdps_v3_4/src/xsdps.c index ac3f9469e..65f1b2237 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sdps_v3_1/src/xsdps.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sdps_v3_4/src/xsdps.c @@ -33,7 +33,7 @@ /** * * @file xsdps.c -* @addtogroup sdps_v2_5 +* @addtogroup sdps_v3_4 * @{ * * Contains the interface functions of the XSdPs driver. @@ -74,6 +74,22 @@ * sk 10/13/16 Reduced the delay during power cycle to 1ms as per spec * sk 10/19/16 Used emmc_hwreset pin to reset eMMC. * sk 11/07/16 Enable Rst_n bit in ext_csd reg if not enabled. +* 3.2 sk 11/30/16 Modified the voltage switching sequence as per spec. +* sk 02/01/17 Added HSD and DDR mode support for eMMC. +* vns 02/09/17 Added ARMA53_32 support for ZynqMP CR#968397 +* sk 03/20/17 Add support for EL1 non-secure mode. +* 3.3 mn 05/17/17 Add support for 64bit DMA addressing +* mn 07/17/17 Add support for running SD at 200MHz +* mn 07/26/17 Fixed compilation warnings +* mn 08/07/17 Modify driver to support 64-bit DMA in arm64 only +* mn 08/17/17 Added CCI support for A53 and disabled data cache +* operations when it is enabled. +* mn 08/22/17 Updated for Word Access System support +* mn 09/06/17 Resolved compilation errors with IAR toolchain +* mn 09/26/17 Added UHS_MODE_ENABLE macro to enable UHS mode +* 3.4 mn 10/17/17 Use different commands for single and multi block +* transfers +* mn 03/02/18 Move UHS macro check to SD card initialization routine * * ******************************************************************************/ @@ -90,21 +106,23 @@ #define XSDPS_CMD1_HIGH_VOL 0x00FF8000U #define XSDPS_CMD1_DUAL_VOL 0x00FF8010U #define HIGH_SPEED_SUPPORT 0x2U +#define UHS_SDR50_SUPPORT 0x4U #define WIDTH_4_BIT_SUPPORT 0x4U #define SD_CLK_25_MHZ 25000000U #define SD_CLK_19_MHZ 19000000U #define SD_CLK_26_MHZ 26000000U #define EXT_CSD_DEVICE_TYPE_BYTE 196U -#define EXT_CSD_SEC_COUNT 212U +#define EXT_CSD_SEC_COUNT_BYTE1 212U +#define EXT_CSD_SEC_COUNT_BYTE2 213U +#define EXT_CSD_SEC_COUNT_BYTE3 214U +#define EXT_CSD_SEC_COUNT_BYTE4 215U #define EXT_CSD_DEVICE_TYPE_HIGH_SPEED 0x2U #define EXT_CSD_DEVICE_TYPE_DDR_1V8_HIGH_SPEED 0x4U #define EXT_CSD_DEVICE_TYPE_DDR_1V2_HIGH_SPEED 0x8U #define EXT_CSD_DEVICE_TYPE_SDR_1V8_HS200 0x10U #define EXT_CSD_DEVICE_TYPE_SDR_1V2_HS200 0x20U #define CSD_SPEC_VER_3 0x3U - -/* Note: Remove this once fixed */ -#define UHS_BROKEN +#define SCR_SPEC_VER_3 0x80U /**************************** Type Definitions *******************************/ @@ -116,10 +134,9 @@ s32 XSdPs_CmdTransfer(XSdPs *InstancePtr, u32 Cmd, u32 Arg, u32 BlkCnt); void XSdPs_SetupADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff); extern s32 XSdPs_Uhs_ModeInit(XSdPs *InstancePtr, u8 Mode); static s32 XSdPs_IdentifyCard(XSdPs *InstancePtr); -#ifndef UHS_BROKEN static s32 XSdPs_Switch_Voltage(XSdPs *InstancePtr); -#endif +u16 TransferMode; /*****************************************************************************/ /** * @@ -172,6 +189,7 @@ s32 XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr, InstancePtr->Config.BusWidth = ConfigPtr->BusWidth; InstancePtr->Config.BankNumber = ConfigPtr->BankNumber; InstancePtr->Config.HasEMIO = ConfigPtr->HasEMIO; + InstancePtr->Config.IsCacheCoherent = ConfigPtr->IsCacheCoherent; InstancePtr->SectorCount = 0; InstancePtr->Mode = XSDPS_DEFAULT_SPEED_MODE; InstancePtr->Config_TapDelay = NULL; @@ -250,10 +268,18 @@ s32 XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr, XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, XSDPS_POWER_CTRL_OFFSET, PowerLevel | XSDPS_PC_BUS_PWR_MASK); + +#ifdef __aarch64__ /* Enable ADMA2 in 64bit mode. */ + XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, + XSDPS_HOST_CTRL1_OFFSET, + XSDPS_HC_DMA_ADMA2_64_MASK); +#else + /* Enable ADMA2 in 32bit mode. */ XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL1_OFFSET, XSDPS_HC_DMA_ADMA2_32_MASK); +#endif /* Enable all interrupt status except card interrupt initially */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, @@ -274,10 +300,8 @@ s32 XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr, * Transfer mode register - default value * DMA enabled, block count enabled, data direction card to host(read) */ - XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, - XSDPS_XFER_MODE_OFFSET, - XSDPS_TM_DMA_EN_MASK | XSDPS_TM_BLK_CNT_EN_MASK | - XSDPS_TM_DAT_DIR_SEL_MASK); + TransferMode = XSDPS_TM_DMA_EN_MASK | XSDPS_TM_BLK_CNT_EN_MASK | + XSDPS_TM_DAT_DIR_SEL_MASK; /* Set block size to 512 by default */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, @@ -328,6 +352,10 @@ s32 XSdPs_SdCardInitialize(XSdPs *InstancePtr) Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); +#ifndef UHS_MODE_ENABLE + InstancePtr->Config.BusWidth = XSDPS_WIDTH_4; +#endif + if ((InstancePtr->HC_Version != XSDPS_HC_SPEC_V3) || ((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK) != XSDPS_CAPS_EMB_SLOT)) { @@ -395,9 +423,17 @@ s32 XSdPs_SdCardInitialize(XSdPs *InstancePtr) goto RETURN_PATH; } - Arg = XSDPS_ACMD41_HCS | XSDPS_ACMD41_3V3 | (0x1FFU << 15U); - if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) { - Arg |= XSDPS_OCR_S18; + Arg = XSDPS_ACMD41_HCS | XSDPS_ACMD41_3V3 | (0x1FFU << 15U); + /* + * There is no support to switch to 1.8V and use UHS mode on + * 1.0 silicon + */ + if ((InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) && +#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) || (PSU_PMU) + (XGetPSVersion_Info() > XPS_VERSION_1) && +#endif + (InstancePtr->Config.BusWidth == XSDPS_WIDTH_8)) { + Arg |= XSDPS_OCR_S18; } /* 0x40300000 - Host High Capacity support & 3.3V window */ @@ -419,18 +455,14 @@ s32 XSdPs_SdCardInitialize(XSdPs *InstancePtr) InstancePtr->HCS = 1U; } - /* There is no support to switch to 1.8V and use UHS mode on 1.0 silicon */ -#ifndef UHS_BROKEN - if ((RespOCR & XSDPS_OCR_S18) != 0U) { + if ((RespOCR & XSDPS_OCR_S18) != 0U) { InstancePtr->Switch1v8 = 1U; Status = XSdPs_Switch_Voltage(InstancePtr); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } - } -#endif /* CMD2 for Card ID */ Status = XSdPs_CmdTransfer(InstancePtr, CMD2, 0U, 0U); @@ -528,12 +560,13 @@ s32 XSdPs_CardInitialize(XSdPs *InstancePtr) { #ifdef __ICCARM__ #pragma data_alignment = 32 -static u8 ExtCsd[512]; + static u8 ExtCsd[512]; + u8 SCR[8] = { 0U }; #pragma data_alignment = 4 #else -static u8 ExtCsd[512] __attribute__ ((aligned(32))); + static u8 ExtCsd[512] __attribute__ ((aligned(32))); + u8 SCR[8] __attribute__ ((aligned(32))) = { 0U }; #endif - u8 SCR[8] = { 0U }; u8 ReadBuff[64] = { 0U }; s32 Status; u32 Arg; @@ -641,9 +674,68 @@ static u8 ExtCsd[512] __attribute__ ((aligned(32))); goto RETURN_PATH; } -#if defined (ARMR5) || defined (__aarch64__) - if ((InstancePtr->Switch1v8 != 0U) && - (InstancePtr->BusWidth == XSDPS_4_BIT_WIDTH)) { + if (((SCR[2] & SCR_SPEC_VER_3) != 0U) && + (ReadBuff[13] >= UHS_SDR50_SUPPORT) && + (InstancePtr->Config.BusWidth == XSDPS_WIDTH_8) && +#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) || (PSU_PMU) + (XGetPSVersion_Info() > XPS_VERSION_1) && +#endif + (InstancePtr->Switch1v8 == 0U)) { + u16 CtrlReg, ClockReg; + + /* Stop the clock */ + CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_CLK_CTRL_OFFSET); + CtrlReg &= ~(XSDPS_CC_SD_CLK_EN_MASK | XSDPS_CC_INT_CLK_EN_MASK); + XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_CLK_CTRL_OFFSET, + CtrlReg); + + /* Enabling 1.8V in controller */ + CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_HOST_CTRL2_OFFSET); + CtrlReg |= XSDPS_HC2_1V8_EN_MASK; + XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL2_OFFSET, + CtrlReg); + + /* Wait minimum 5mSec */ + (void)usleep(5000U); + + /* Check for 1.8V signal enable bit is cleared by Host */ + CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_HOST_CTRL2_OFFSET); + if ((CtrlReg & XSDPS_HC2_1V8_EN_MASK) == 0U) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + + /* Wait for internal clock to stabilize */ + ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_CLK_CTRL_OFFSET); + XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, + XSDPS_CLK_CTRL_OFFSET, + ClockReg | XSDPS_CC_INT_CLK_EN_MASK); + ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_CLK_CTRL_OFFSET); + while((ClockReg & XSDPS_CC_INT_CLK_STABLE_MASK) == 0U) { + ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_CLK_CTRL_OFFSET); + } + + /* Enable SD clock */ + ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_CLK_CTRL_OFFSET); + XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, + XSDPS_CLK_CTRL_OFFSET, + ClockReg | XSDPS_CC_SD_CLK_EN_MASK); + + /* Wait for 1mSec */ + (void)usleep(1000U); + + InstancePtr->Switch1v8 = 1U; + } + +#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) + if (InstancePtr->Switch1v8 != 0U) { /* Identify the UHS mode supported by card */ XSdPs_Identify_UhsMode(InstancePtr, ReadBuff); @@ -663,9 +755,10 @@ static u8 ExtCsd[512] __attribute__ ((aligned(32))); */ if (SCR[0] != 0U) { /* Check for high speed support */ - if ((ReadBuff[13] & HIGH_SPEED_SUPPORT) != 0U) { + if (((ReadBuff[13] & HIGH_SPEED_SUPPORT) != 0U) && + (InstancePtr->BusWidth >= XSDPS_4_BIT_WIDTH)) { InstancePtr->Mode = XSDPS_HIGH_SPEED_MODE; -#if defined (ARMR5) || defined (__aarch64__) +#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) InstancePtr->Config_TapDelay = XSdPs_hsd_sdr25_tapdelay; #endif Status = XSdPs_Change_BusSpeed(InstancePtr); @@ -675,7 +768,7 @@ static u8 ExtCsd[512] __attribute__ ((aligned(32))); } } } -#if defined (ARMR5) || defined (__aarch64__) +#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) } #endif @@ -695,10 +788,14 @@ static u8 ExtCsd[512] __attribute__ ((aligned(32))); goto RETURN_PATH; } - InstancePtr->SectorCount = *(u32 *)&ExtCsd[EXT_CSD_SEC_COUNT]; + InstancePtr->SectorCount = ((u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE4]) << 24; + InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE3] << 16; + InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE2] << 8; + InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE1]; - if ((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] & - EXT_CSD_DEVICE_TYPE_HIGH_SPEED) != 0U) { + if (((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] & + EXT_CSD_DEVICE_TYPE_HIGH_SPEED) != 0U) && + (InstancePtr->BusWidth >= XSDPS_4_BIT_WIDTH)) { InstancePtr->Mode = XSDPS_HIGH_SPEED_MODE; Status = XSdPs_Change_BusSpeed(InstancePtr); if (Status != XST_SUCCESS) { @@ -732,15 +829,39 @@ static u8 ExtCsd[512] __attribute__ ((aligned(32))); goto RETURN_PATH; } - InstancePtr->SectorCount = *(u32 *)&ExtCsd[EXT_CSD_SEC_COUNT]; + InstancePtr->SectorCount = ((u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE4]) << 24; + InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE3] << 16; + InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE2] << 8; + InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE1]; - if ((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] & + /* Check for card supported speed */ + if (((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] & (EXT_CSD_DEVICE_TYPE_SDR_1V8_HS200 | - EXT_CSD_DEVICE_TYPE_SDR_1V2_HS200)) != 0U) { + EXT_CSD_DEVICE_TYPE_SDR_1V2_HS200)) != 0U) && + (InstancePtr->BusWidth >= XSDPS_4_BIT_WIDTH)) { InstancePtr->Mode = XSDPS_HS200_MODE; -#if defined (ARMR5) || defined (__aarch64__) +#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) InstancePtr->Config_TapDelay = XSdPs_sdr104_hs200_tapdelay; #endif + } else if (((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] & + (EXT_CSD_DEVICE_TYPE_DDR_1V8_HIGH_SPEED | + EXT_CSD_DEVICE_TYPE_DDR_1V2_HIGH_SPEED)) != 0U) && + (InstancePtr->BusWidth >= XSDPS_4_BIT_WIDTH)) { + InstancePtr->Mode = XSDPS_DDR52_MODE; +#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) + InstancePtr->Config_TapDelay = XSdPs_ddr50_tapdelay; +#endif + } else if (((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] & + EXT_CSD_DEVICE_TYPE_HIGH_SPEED) != 0U) && + (InstancePtr->BusWidth >= XSDPS_4_BIT_WIDTH)) { + InstancePtr->Mode = XSDPS_HIGH_SPEED_MODE; +#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) + InstancePtr->Config_TapDelay = XSdPs_hsd_sdr25_tapdelay; +#endif + } else + InstancePtr->Mode = XSDPS_DEFAULT_SPEED_MODE; + + if (InstancePtr->Mode != XSDPS_DEFAULT_SPEED_MODE) { Status = XSdPs_Change_BusSpeed(InstancePtr); if (Status != XST_SUCCESS) { Status = XST_FAILURE; @@ -753,9 +874,27 @@ static u8 ExtCsd[512] __attribute__ ((aligned(32))); goto RETURN_PATH; } - if (ExtCsd[EXT_CSD_HS_TIMING_BYTE] != EXT_CSD_HS_TIMING_HS200) { - Status = XST_FAILURE; - goto RETURN_PATH; + if (InstancePtr->Mode == XSDPS_HS200_MODE) { + if (ExtCsd[EXT_CSD_HS_TIMING_BYTE] != EXT_CSD_HS_TIMING_HS200) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + } + + if ((InstancePtr->Mode == XSDPS_HIGH_SPEED_MODE) || + InstancePtr->Mode == XSDPS_DDR52_MODE) { + if (ExtCsd[EXT_CSD_HS_TIMING_BYTE] != EXT_CSD_HS_TIMING_HIGH) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + + if (InstancePtr->Mode == XSDPS_DDR52_MODE) { + Status = XSdPs_Change_BusWidth(InstancePtr); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + } } } @@ -769,11 +908,13 @@ static u8 ExtCsd[512] __attribute__ ((aligned(32))); } } } - - Status = XSdPs_SetBlkSize(InstancePtr, XSDPS_BLK_SIZE_512_MASK); - if (Status != XST_SUCCESS) { - Status = XST_FAILURE; - goto RETURN_PATH; + if ((InstancePtr->Mode != XSDPS_DDR52_MODE) || + (InstancePtr->CardType == XSDPS_CARD_SD)) { + Status = XSdPs_SetBlkSize(InstancePtr, XSDPS_BLK_SIZE_512_MASK); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } } RETURN_PATH: @@ -839,7 +980,6 @@ RETURN_PATH: return Status; } -#ifndef UHS_BROKEN /*****************************************************************************/ /** * @@ -853,7 +993,7 @@ static s32 XSdPs_Switch_Voltage(XSdPs *InstancePtr) { s32 Status; u16 CtrlReg; - u32 ReadReg; + u32 ReadReg, ClockReg; /* Send switch voltage command */ Status = XSdPs_CmdTransfer(InstancePtr, CMD11, 0U, 0U); @@ -877,9 +1017,6 @@ static s32 XSdPs_Switch_Voltage(XSdPs *InstancePtr) XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_CLK_CTRL_OFFSET, CtrlReg); - /* Wait minimum 5mSec */ - (void)usleep(5000U); - /* Enabling 1.8V in controller */ CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL2_OFFSET); @@ -887,13 +1024,40 @@ static s32 XSdPs_Switch_Voltage(XSdPs *InstancePtr) XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL2_OFFSET, CtrlReg); - /* Start clock */ - Status = XSdPs_Change_ClkFreq(InstancePtr, XSDPS_CLK_400_KHZ); - if (Status != XST_SUCCESS) { + /* Wait minimum 5mSec */ + (void)usleep(5000U); + + /* Check for 1.8V signal enable bit is cleared by Host */ + CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_HOST_CTRL2_OFFSET); + if ((CtrlReg & XSDPS_HC2_1V8_EN_MASK) == 0U) { Status = XST_FAILURE; goto RETURN_PATH; } + /* Wait for internal clock to stabilize */ + ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_CLK_CTRL_OFFSET); + XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, + XSDPS_CLK_CTRL_OFFSET, + ClockReg | XSDPS_CC_INT_CLK_EN_MASK); + ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_CLK_CTRL_OFFSET); + while((ClockReg & XSDPS_CC_INT_CLK_STABLE_MASK) == 0U) { + ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_CLK_CTRL_OFFSET); + } + + /* Enable SD clock */ + ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_CLK_CTRL_OFFSET); + XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, + XSDPS_CLK_CTRL_OFFSET, + ClockReg | XSDPS_CC_SD_CLK_EN_MASK); + + /* Wait for 1mSec */ + (void)usleep(1000U); + /* Wait for CMD and DATA line to go high */ ReadReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_PRES_STATE_OFFSET); @@ -906,7 +1070,6 @@ static s32 XSdPs_Switch_Voltage(XSdPs *InstancePtr) RETURN_PATH: return Status; } -#endif /*****************************************************************************/ /** @@ -986,8 +1149,8 @@ s32 XSdPs_CmdTransfer(XSdPs *InstancePtr, u32 Cmd, u32 Arg, u32 BlkCnt) } } - XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_CMD_OFFSET, - (u16)CommandReg); + XSdPs_WriteReg(InstancePtr->Config.BaseAddress, XSDPS_XFER_MODE_OFFSET, + (CommandReg << 16) | TransferMode); /* Polling for response for now */ do { @@ -1178,20 +1341,32 @@ s32 XSdPs_ReadPolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff) } XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, Buff); + if (InstancePtr->Config.IsCacheCoherent == 0) { + Xil_DCacheInvalidateRange((INTPTR)Buff, + BlkCnt * XSDPS_BLK_SIZE_512_MASK); + } - XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, - XSDPS_XFER_MODE_OFFSET, - XSDPS_TM_AUTO_CMD12_EN_MASK | + if (BlkCnt == 1U) { + TransferMode = XSDPS_TM_BLK_CNT_EN_MASK | + XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK; + + /* Send single block read command */ + Status = XSdPs_CmdTransfer(InstancePtr, CMD17, Arg, BlkCnt); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + } else { + TransferMode = XSDPS_TM_AUTO_CMD12_EN_MASK | XSDPS_TM_BLK_CNT_EN_MASK | XSDPS_TM_DAT_DIR_SEL_MASK | - XSDPS_TM_DMA_EN_MASK | XSDPS_TM_MUL_SIN_BLK_SEL_MASK); + XSDPS_TM_DMA_EN_MASK | XSDPS_TM_MUL_SIN_BLK_SEL_MASK; - Xil_DCacheInvalidateRange((INTPTR)Buff, BlkCnt * XSDPS_BLK_SIZE_512_MASK); - - /* Send block read command */ - Status = XSdPs_CmdTransfer(InstancePtr, CMD18, Arg, BlkCnt); - if (Status != XST_SUCCESS) { - Status = XST_FAILURE; - goto RETURN_PATH; + /* Send multiple blocks read command */ + Status = XSdPs_CmdTransfer(InstancePtr, CMD18, Arg, BlkCnt); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } } /* Check for transfer complete */ @@ -1269,19 +1444,31 @@ s32 XSdPs_WritePolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, const u8 *Buff) } XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, Buff); - Xil_DCacheFlushRange((INTPTR)Buff, BlkCnt * XSDPS_BLK_SIZE_512_MASK); + if (InstancePtr->Config.IsCacheCoherent == 0) { + Xil_DCacheFlushRange((INTPTR)Buff, + BlkCnt * XSDPS_BLK_SIZE_512_MASK); + } - XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, - XSDPS_XFER_MODE_OFFSET, - XSDPS_TM_AUTO_CMD12_EN_MASK | + if (BlkCnt == 1U) { + TransferMode = XSDPS_TM_BLK_CNT_EN_MASK | XSDPS_TM_DMA_EN_MASK; + + /* Send single block write command */ + Status = XSdPs_CmdTransfer(InstancePtr, CMD24, Arg, BlkCnt); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + } else { + TransferMode = XSDPS_TM_AUTO_CMD12_EN_MASK | XSDPS_TM_BLK_CNT_EN_MASK | - XSDPS_TM_MUL_SIN_BLK_SEL_MASK | XSDPS_TM_DMA_EN_MASK); + XSDPS_TM_MUL_SIN_BLK_SEL_MASK | XSDPS_TM_DMA_EN_MASK; - /* Send block write command */ - Status = XSdPs_CmdTransfer(InstancePtr, CMD25, Arg, BlkCnt); - if (Status != XST_SUCCESS) { - Status = XST_FAILURE; - goto RETURN_PATH; + /* Send multiple blocks write command */ + Status = XSdPs_CmdTransfer(InstancePtr, CMD25, Arg, BlkCnt); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } } /* @@ -1383,8 +1570,13 @@ void XSdPs_SetupADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff) } for (DescNum = 0U; DescNum < (TotalDescLines-1); DescNum++) { +#ifdef __aarch64__ + InstancePtr->Adma2_DescrTbl[DescNum].Address = + (u64)((UINTPTR)Buff + (DescNum*XSDPS_DESC_MAX_LENGTH)); +#else InstancePtr->Adma2_DescrTbl[DescNum].Address = (u32)((UINTPTR)Buff + (DescNum*XSDPS_DESC_MAX_LENGTH)); +#endif InstancePtr->Adma2_DescrTbl[DescNum].Attribute = XSDPS_DESC_TRAN | XSDPS_DESC_VALID; /* This will write '0' to length field which indicates 65536 */ @@ -1392,8 +1584,13 @@ void XSdPs_SetupADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff) (u16)XSDPS_DESC_MAX_LENGTH; } +#ifdef __aarch64__ + InstancePtr->Adma2_DescrTbl[TotalDescLines-1].Address = + (u64)((UINTPTR)Buff + (DescNum*XSDPS_DESC_MAX_LENGTH)); +#else InstancePtr->Adma2_DescrTbl[TotalDescLines-1].Address = (u32)((UINTPTR)Buff + (DescNum*XSDPS_DESC_MAX_LENGTH)); +#endif InstancePtr->Adma2_DescrTbl[TotalDescLines-1].Attribute = XSDPS_DESC_TRAN | XSDPS_DESC_END | XSDPS_DESC_VALID; @@ -1401,13 +1598,18 @@ void XSdPs_SetupADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff) InstancePtr->Adma2_DescrTbl[TotalDescLines-1].Length = (u16)((BlkCnt*BlkSize) - (DescNum*XSDPS_DESC_MAX_LENGTH)); +#ifdef __aarch64__ + XSdPs_WriteReg(InstancePtr->Config.BaseAddress, XSDPS_ADMA_SAR_EXT_OFFSET, + (u32)(((u64)&(InstancePtr->Adma2_DescrTbl[0]))>>32)); +#endif XSdPs_WriteReg(InstancePtr->Config.BaseAddress, XSDPS_ADMA_SAR_OFFSET, (u32)(UINTPTR)&(InstancePtr->Adma2_DescrTbl[0])); - Xil_DCacheFlushRange((INTPTR)&(InstancePtr->Adma2_DescrTbl[0]), + if (InstancePtr->Config.IsCacheCoherent == 0) { + Xil_DCacheFlushRange((INTPTR)&(InstancePtr->Adma2_DescrTbl[0]), sizeof(XSdPs_Adma2Descriptor) * 32U); - + } } /*****************************************************************************/ diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_1/src/xsdps.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sdps_v3_4/src/xsdps.h similarity index 90% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_1/src/xsdps.h rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sdps_v3_4/src/xsdps.h index 46fe545d9..3f9ffd202 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_1/src/xsdps.h +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sdps_v3_4/src/xsdps.h @@ -33,7 +33,7 @@ /** * * @file xsdps.h -* @addtogroup sdps_v2_5 +* @addtogroup sdps_v3_4 * @{ * @details * @@ -139,6 +139,16 @@ * sk 10/19/16 Used emmc_hwreset pin to reset eMMC. * sk 11/07/16 Enable Rst_n bit in ext_csd reg if not enabled. * sk 11/16/16 Issue DLL reset at 31 iteration to load new zero value. +* 3.2 sk 11/30/16 Modified the voltage switching sequence as per spec. +* sk 02/01/17 Added HSD and DDR mode support for eMMC. +* sk 02/01/17 Consider bus width parameter from design for switching +* vns 02/09/17 Added ARMA53_32 support for ZynqMP CR#968397 +* sk 03/20/17 Add support for EL1 non-secure mode. +* 3.3 mn 05/17/17 Add support for 64bit DMA addressing +* mn 08/07/17 Modify driver to support 64-bit DMA in arm64 only +* mn 08/17/17 Enabled CCI support for A53 by adding cache coherency +* information. +* mn 09/06/17 Resolved compilation errors with IAR toolchain * * * @@ -156,6 +166,7 @@ extern "C" { #include "xil_cache.h" #include "xstatus.h" #include "xsdps_hw.h" +#include "xplatform_info.h" #include /************************** Constant Definitions *****************************/ @@ -179,14 +190,25 @@ typedef struct { u32 BusWidth; /**< Bus Width */ u32 BankNumber; /**< MIO Bank selection for SD */ u32 HasEMIO; /**< If SD is connected to EMIO */ + u8 IsCacheCoherent; /**< If SD is Cache Coherent or not */ } XSdPs_Config; /* ADMA2 descriptor table */ typedef struct { u16 Attribute; /**< Attributes of descriptor */ u16 Length; /**< Length of current dma transfer */ +#ifdef __aarch64__ + u64 Address; /**< Address of current dma transfer */ +#else u32 Address; /**< Address of current dma transfer */ +#endif +#ifdef __ICCARM__ +#pragma data_alignment = 32 } XSdPs_Adma2Descriptor; +#pragma data_alignment = 4 +#else +} __attribute__((__packed__))XSdPs_Adma2Descriptor; +#endif /** * The XSdPs driver instance data. The user is required to allocate a @@ -243,8 +265,9 @@ s32 XSdPs_MmcCardInitialize(XSdPs *InstancePtr); s32 XSdPs_CardInitialize(XSdPs *InstancePtr); s32 XSdPs_Get_Mmc_ExtCsd(XSdPs *InstancePtr, u8 *ReadBuff); s32 XSdPs_Set_Mmc_ExtCsd(XSdPs *InstancePtr, u32 Arg); -#if defined (ARMR5) || defined (__aarch64__) +#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) void XSdPs_Identify_UhsMode(XSdPs *InstancePtr, u8 *ReadBuff); +void XSdPs_ddr50_tapdelay(u32 Bank, u32 DeviceId, u32 CardType); void XSdPs_hsd_sdr25_tapdelay(u32 Bank, u32 DeviceId, u32 CardType); void XSdPs_sdr104_hs200_tapdelay(u32 Bank, u32 DeviceId, u32 CardType); #endif diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sdps_v3_1/src/xsdps_g.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sdps_v3_4/src/xsdps_g.c similarity index 89% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sdps_v3_1/src/xsdps_g.c rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sdps_v3_4/src/xsdps_g.c index 72981b551..de9be71b8 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sdps_v3_1/src/xsdps_g.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sdps_v3_4/src/xsdps_g.c @@ -5,7 +5,7 @@ * Version: * DO NOT EDIT. * -* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.* +* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.* *Permission is hereby granted, free of charge, to any person obtaining a copy *of this software and associated documentation files (the Software), to deal *in the Software without restriction, including without limitation the rights @@ -44,7 +44,7 @@ * The configuration table for devices */ -XSdPs_Config XSdPs_ConfigTable[] = +XSdPs_Config XSdPs_ConfigTable[XPAR_XSDPS_NUM_INSTANCES] = { { XPAR_PSU_SD_1_DEVICE_ID, @@ -54,7 +54,8 @@ XSdPs_Config XSdPs_ConfigTable[] = XPAR_PSU_SD_1_HAS_WP, XPAR_PSU_SD_1_BUS_WIDTH, XPAR_PSU_SD_1_MIO_BANK, - XPAR_PSU_SD_1_HAS_EMIO + XPAR_PSU_SD_1_HAS_EMIO, + XPAR_PSU_SD_1_IS_CACHE_COHERENT } }; diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_1/src/xsdps_hw.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sdps_v3_4/src/xsdps_hw.h similarity index 95% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_1/src/xsdps_hw.h rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sdps_v3_4/src/xsdps_hw.h index 2c5d712d2..8d190efa0 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_1/src/xsdps_hw.h +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sdps_v3_4/src/xsdps_hw.h @@ -33,7 +33,7 @@ /** * * @file xsdps_hw.h -* @addtogroup sdps_v2_5 +* @addtogroup sdps_v3_4 * @{ * * This header file contains the identifiers and basic HW access driver @@ -56,6 +56,11 @@ * sk 07/16/16 Added Tap delays accordingly to different SD/eMMC * operating modes. * 3.1 sk 11/07/16 Enable Rst_n bit in ext_csd reg if not enabled. +* 3.2 sk 03/20/17 Add support for EL1 non-secure mode. +* 3.3 mn 08/22/17 Updated for Word Access System support +* mn 09/06/17 Added support for ARMCC toolchain +* 3.4 mn 01/22/18 Separated out SDR104 and HS200 clock defines +* * * ******************************************************************************/ @@ -953,6 +958,7 @@ extern "C" { #define XSDPS_HIGH_SPEED_MODE 0x5U #define XSDPS_DEFAULT_SPEED_MODE 0x6U #define XSDPS_HS200_MODE 0x7U +#define XSDPS_DDR52_MODE 0x4U #define XSDPS_SWITCH_CMD_BLKCNT 1U #define XSDPS_SWITCH_CMD_BLKSIZE 64U #define XSDPS_SWITCH_CMD_HS_GET 0x00FFFFF0U @@ -993,7 +999,16 @@ extern "C" { #define XSDPS_SD_SDR50_MAX_CLK 100000000U #define XSDPS_SD_DDR50_MAX_CLK 50000000U #define XSDPS_SD_SDR104_MAX_CLK 208000000U +/* + * XSDPS_SD_INPUT_MAX_CLK is set to 175000000 in order to keep it smaller + * than the clock value coming from the core. This value is kept to safely + * switch to SDR104 mode if the SD card supports it. + */ +#define XSDPS_SD_INPUT_MAX_CLK 175000000U + #define XSDPS_MMC_HS200_MAX_CLK 200000000U +#define XSDPS_MMC_HSD_MAX_CLK 52000000U +#define XSDPS_MMC_DDR_MAX_CLK 52000000U #define XSDPS_CARD_STATE_IDLE 0U #define XSDPS_CARD_STATE_RDY 1U @@ -1010,7 +1025,15 @@ extern "C" { #define XSDPS_SLOT_REM 0U #define XSDPS_SLOT_EMB 1U -#if defined (ARMR5) || defined (__aarch64__) +#define XSDPS_WIDTH_8 8U +#define XSDPS_WIDTH_4 4U + + +#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) +#define SD0_ITAPDLY_SEL_MASK 0x000000FFU +#define SD0_OTAPDLY_SEL_MASK 0x0000003FU +#define SD1_ITAPDLY_SEL_MASK 0x00FF0000U +#define SD1_OTAPDLY_SEL_MASK 0x003F0000U #define SD_DLL_CTRL 0x00000358U #define SD_ITAPDLY 0x00000314U #define SD_OTAPDLY 0x00000318U @@ -1151,8 +1174,18 @@ extern "C" { * u16 XSdPs_ReadReg(u32 BaseAddress. int RegOffset) * ******************************************************************************/ -#define XSdPs_ReadReg16(BaseAddress, RegOffset) \ - XSdPs_In16((BaseAddress) + (RegOffset)) +static INLINE u16 XSdPs_ReadReg16(u32 BaseAddress, u8 RegOffset) +{ +#if defined (__MICROBLAZE__) + u32 Reg; + BaseAddress += RegOffset & 0xFC; + Reg = XSdPs_In32(BaseAddress); + Reg >>= ((RegOffset & 0x3)*8); + return (u16)Reg; +#else + return XSdPs_In16((BaseAddress) + (RegOffset)); +#endif +} /***************************************************************************/ /** @@ -1170,8 +1203,20 @@ extern "C" { * u16 RegisterValue) * ******************************************************************************/ -#define XSdPs_WriteReg16(BaseAddress, RegOffset, RegisterValue) \ - XSdPs_Out16((BaseAddress) + (RegOffset), (RegisterValue)) + +static INLINE void XSdPs_WriteReg16(u32 BaseAddress, u8 RegOffset, u16 RegisterValue) +{ +#if defined (__MICROBLAZE__) + u32 Reg; + BaseAddress += RegOffset & 0xFC; + Reg = XSdPs_In32(BaseAddress); + Reg &= ~(0xFFFF<<((RegOffset & 0x3)*8)); + Reg |= RegisterValue <<((RegOffset & 0x3)*8); + XSdPs_Out32(BaseAddress, Reg); +#else + XSdPs_Out16((BaseAddress) + (RegOffset), (RegisterValue)); +#endif +} /****************************************************************************/ /** @@ -1187,9 +1232,18 @@ extern "C" { * u8 XSdPs_ReadReg(u32 BaseAddress. int RegOffset) * ******************************************************************************/ -#define XSdPs_ReadReg8(BaseAddress, RegOffset) \ - XSdPs_In8((BaseAddress) + (RegOffset)) - +static INLINE u8 XSdPs_ReadReg8(u32 BaseAddress, u8 RegOffset) +{ +#if defined (__MICROBLAZE__) + u32 Reg; + BaseAddress += RegOffset & 0xFC; + Reg = XSdPs_In32(BaseAddress); + Reg >>= ((RegOffset & 0x3)*8); + return (u8)Reg; +#else + return XSdPs_In8((BaseAddress) + (RegOffset)); +#endif +} /***************************************************************************/ /** * Write to a register. @@ -1206,9 +1260,19 @@ extern "C" { * u8 RegisterValue) * ******************************************************************************/ -#define XSdPs_WriteReg8(BaseAddress, RegOffset, RegisterValue) \ - XSdPs_Out8((BaseAddress) + (RegOffset), (RegisterValue)) - +static INLINE void XSdPs_WriteReg8(u32 BaseAddress, u8 RegOffset, u8 RegisterValue) +{ +#if defined (__MICROBLAZE__) + u32 Reg; + BaseAddress += RegOffset & 0xFC; + Reg = XSdPs_In32(BaseAddress); + Reg &= ~(0xFF<<((RegOffset & 0x3)*8)); + Reg |= RegisterValue <<((RegOffset & 0x3)*8); + XSdPs_Out32(BaseAddress, Reg); +#else + XSdPs_Out8((BaseAddress) + (RegOffset), (RegisterValue)); +#endif +} /***************************************************************************/ /** * Macro to get present status register diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_1/src/xsdps_options.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sdps_v3_4/src/xsdps_options.c similarity index 77% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_1/src/xsdps_options.c rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sdps_v3_4/src/xsdps_options.c index 7dbc772f3..bcd7c689b 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_1/src/xsdps_options.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sdps_v3_4/src/xsdps_options.c @@ -33,7 +33,7 @@ /** * * @file xsdps_options.c -* @addtogroup sdps_v2_5 +* @addtogroup sdps_v3_4 * @{ * * Contains API's for changing the various options in host and card. @@ -63,6 +63,18 @@ * 3.1 mi 09/07/16 Removed compilation warnings with extra compiler flags. * sk 11/07/16 Enable Rst_n bit in ext_csd reg if not enabled. * sk 11/16/16 Issue DLL reset at 31 iteration to load new zero value. +* 3.2 sk 02/01/17 Added HSD and DDR mode support for eMMC. +* sk 02/01/17 Consider bus width parameter from design for switching +* vns 02/09/17 Added ARMA53_32 support for ZynqMP CR#968397 +* vns 03/13/17 Fixed MISRAC mandatory violation +* sk 03/20/17 Add support for EL1 non-secure mode. +* 3.3 mn 07/25/17 Removed SD0_OTAPDLYENA and SD1_OTAPDLYENA bits +* mn 08/07/17 Properly set OTAPDLY value by clearing previous bit +* settings +* mn 08/17/17 Added CCI support for A53 and disabled data cache +* operations when it is enabled. +* mn 08/22/17 Updated for Word Access System support +* 3.4 mn 01/22/18 Separated out SDR104 and HS200 clock defines * * * @@ -71,7 +83,9 @@ /***************************** Include Files *********************************/ #include "xsdps.h" #include "sleep.h" - +#if defined (__aarch64__) +#include "xil_smc.h" +#endif /************************** Constant Definitions *****************************/ #define UHS_SDR12_SUPPORT 0x1U #define UHS_SDR25_SUPPORT 0x2U @@ -86,14 +100,14 @@ s32 XSdPs_CmdTransfer(XSdPs *InstancePtr, u32 Cmd, u32 Arg, u32 BlkCnt); void XSdPs_SetupADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff); static s32 XSdPs_Execute_Tuning(XSdPs *InstancePtr); -#if defined (ARMR5) || defined (__aarch64__) +#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) s32 XSdPs_Uhs_ModeInit(XSdPs *InstancePtr, u8 Mode); static void XSdPs_sdr50_tapdelay(u32 Bank, u32 DeviceId, u32 CardType); -static void XSdPs_ddr50_tapdelay(u32 Bank, u32 DeviceId, u32 CardType); void XSdPs_SetTapDelay(XSdPs *InstancePtr); static void XSdPs_DllReset(XSdPs *InstancePtr); #endif +extern u16 TransferMode; /*****************************************************************************/ /** * Update Block size for read/write operations. @@ -193,11 +207,11 @@ s32 XSdPs_Get_BusWidth(XSdPs *InstancePtr, u8 *SCR) XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, SCR); - XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, - XSDPS_XFER_MODE_OFFSET, - XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK); + TransferMode = XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK; - Xil_DCacheInvalidateRange((INTPTR)SCR, 8); + if (InstancePtr->Config.IsCacheCoherent == 0) { + Xil_DCacheInvalidateRange((INTPTR)SCR, 8); + } Status = XSdPs_CmdTransfer(InstancePtr, ACMD51, 0U, BlkCnt); if (Status != XST_SUCCESS) { @@ -261,6 +275,16 @@ s32 XSdPs_Change_BusWidth(XSdPs *InstancePtr) Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + /* + * check for bus width for 3.0 controller and return if + * bus width is <4 + */ + if ((InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) && + (InstancePtr->Config.BusWidth < XSDPS_WIDTH_4)) { + Status = XST_SUCCESS; + goto RETURN_PATH; + } + if (InstancePtr->CardType == XSDPS_CARD_SD) { Status = XSdPs_CmdTransfer(InstancePtr, CMD55, InstancePtr->RelCardAddr, @@ -282,7 +306,8 @@ s32 XSdPs_Change_BusWidth(XSdPs *InstancePtr) } else { if ((InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) - && (InstancePtr->CardType == XSDPS_CHIP_EMMC)) { + && (InstancePtr->CardType == XSDPS_CHIP_EMMC) && + (InstancePtr->Config.BusWidth == XSDPS_WIDTH_8)) { /* in case of eMMC data width 8-bit */ InstancePtr->BusWidth = XSDPS_8_BIT_WIDTH; } else { @@ -290,9 +315,15 @@ s32 XSdPs_Change_BusWidth(XSdPs *InstancePtr) } if (InstancePtr->BusWidth == XSDPS_8_BIT_WIDTH) { - Arg = XSDPS_MMC_8_BIT_BUS_ARG; + if (InstancePtr->Mode == XSDPS_DDR52_MODE) + Arg = XSDPS_MMC_DDR_8_BIT_BUS_ARG; + else + Arg = XSDPS_MMC_8_BIT_BUS_ARG; } else { - Arg = XSDPS_MMC_4_BIT_BUS_ARG; + if (InstancePtr->Mode == XSDPS_DDR52_MODE) + Arg = XSDPS_MMC_DDR_4_BIT_BUS_ARG; + else + Arg = XSDPS_MMC_4_BIT_BUS_ARG; } Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 0U); @@ -336,6 +367,15 @@ s32 XSdPs_Change_BusWidth(XSdPs *InstancePtr) XSDPS_HOST_CTRL1_OFFSET, (u8)StatusReg); + if (InstancePtr->Mode == XSDPS_DDR52_MODE) { + StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_HOST_CTRL2_OFFSET); + StatusReg &= (u16)(~XSDPS_HC2_UHS_MODE_MASK); + StatusReg |= InstancePtr->Mode; + XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, + XSDPS_HOST_CTRL2_OFFSET, StatusReg); + } + Status = (s32)XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_RESP0_OFFSET); @@ -387,13 +427,13 @@ s32 XSdPs_Get_BusSpeed(XSdPs *InstancePtr, u8 *ReadBuff) XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff); - XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, - XSDPS_XFER_MODE_OFFSET, - XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK); + TransferMode = XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK; Arg = XSDPS_SWITCH_CMD_HS_GET; - Xil_DCacheInvalidateRange((INTPTR)ReadBuff, 64); + if (InstancePtr->Config.IsCacheCoherent == 0) { + Xil_DCacheInvalidateRange((INTPTR)ReadBuff, 64); + } Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 1U); if (Status != XST_SUCCESS) { @@ -454,7 +494,7 @@ s32 XSdPs_Change_BusSpeed(XSdPs *InstancePtr) u32 Arg; u16 BlkCnt; u16 BlkSize; - u8 ReadBuff[64]; + u8 ReadBuff[64] = {0U}; Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); @@ -469,11 +509,11 @@ s32 XSdPs_Change_BusSpeed(XSdPs *InstancePtr) XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff); - Xil_DCacheFlushRange((INTPTR)ReadBuff, 64); + if (InstancePtr->Config.IsCacheCoherent == 0) { + Xil_DCacheFlushRange((INTPTR)ReadBuff, 64); + } - XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, - XSDPS_XFER_MODE_OFFSET, - XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK); + TransferMode = XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK; Arg = XSDPS_SWITCH_CMD_HS_SET; @@ -553,7 +593,16 @@ s32 XSdPs_Change_BusSpeed(XSdPs *InstancePtr) goto RETURN_PATH; } } else { - Arg = XSDPS_MMC_HS200_ARG; + if (InstancePtr->Mode == XSDPS_HS200_MODE) { + Arg = XSDPS_MMC_HS200_ARG; + InstancePtr->BusSpeed = XSDPS_MMC_HS200_MAX_CLK; + } else if (InstancePtr->Mode == XSDPS_DDR52_MODE) { + Arg = XSDPS_MMC_HIGH_SPEED_ARG; + InstancePtr->BusSpeed = XSDPS_MMC_DDR_MAX_CLK; + } else { + Arg = XSDPS_MMC_HIGH_SPEED_ARG; + InstancePtr->BusSpeed = XSDPS_MMC_HSD_MAX_CLK; + } Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 0U); if (Status != XST_SUCCESS) { @@ -585,18 +634,18 @@ s32 XSdPs_Change_BusSpeed(XSdPs *InstancePtr) XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK); - /* Change the clock frequency to 200 MHz */ - InstancePtr->BusSpeed = XSDPS_MMC_HS200_MAX_CLK; - Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } - Status = XSdPs_Execute_Tuning(InstancePtr); - if (Status != XST_SUCCESS) { - Status = XST_FAILURE; - goto RETURN_PATH; + + if (InstancePtr->Mode == XSDPS_HS200_MODE) { + Status = XSdPs_Execute_Tuning(InstancePtr); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } } } @@ -654,7 +703,7 @@ s32 XSdPs_Change_ClkFreq(XSdPs *InstancePtr, u32 SelFreq) XSDPS_CLK_CTRL_OFFSET, ClockReg); if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) { -#if defined (ARMR5) || defined (__aarch64__) +#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) if ((InstancePtr->Mode != XSDPS_DEFAULT_SPEED_MODE) && (InstancePtr->Mode != XSDPS_UHS_SPEED_MODE_SDR12)) /* Program the Tap delays */ @@ -823,12 +872,11 @@ s32 XSdPs_Get_Mmc_ExtCsd(XSdPs *InstancePtr, u8 *ReadBuff) XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff); - Xil_DCacheInvalidateRange((INTPTR)ReadBuff, 512U); - - XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, - XSDPS_XFER_MODE_OFFSET, - XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK); + if (InstancePtr->Config.IsCacheCoherent == 0) { + Xil_DCacheInvalidateRange((INTPTR)ReadBuff, 512U); + } + TransferMode = XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK; /* Send SEND_EXT_CSD command */ Status = XSdPs_CmdTransfer(InstancePtr, CMD8, Arg, 1U); @@ -927,7 +975,7 @@ s32 XSdPs_Set_Mmc_ExtCsd(XSdPs *InstancePtr, u32 Arg) } -#if defined (ARMR5) || defined (__aarch64__) +#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) /*****************************************************************************/ /** * @@ -950,7 +998,7 @@ void XSdPs_Identify_UhsMode(XSdPs *InstancePtr, u8 *ReadBuff) Xil_AssertVoid(InstancePtr != NULL); if (((ReadBuff[13] & UHS_SDR104_SUPPORT) != 0U) && - (InstancePtr->Config.InputClockHz >= XSDPS_MMC_HS200_MAX_CLK)) { + (InstancePtr->Config.InputClockHz >= XSDPS_SD_INPUT_MAX_CLK)) { InstancePtr->Mode = XSDPS_UHS_SPEED_MODE_SDR104; InstancePtr->Config_TapDelay = XSdPs_sdr104_hs200_tapdelay; } @@ -997,7 +1045,7 @@ s32 XSdPs_Uhs_ModeInit(XSdPs *InstancePtr, u8 Mode) u32 Arg; u16 BlkCnt; u16 BlkSize; - u8 ReadBuff[64]; + u8 ReadBuff[64] = {0U}; Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); @@ -1013,10 +1061,11 @@ s32 XSdPs_Uhs_ModeInit(XSdPs *InstancePtr, u8 Mode) XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff); - Xil_DCacheFlushRange((INTPTR)ReadBuff, 64); + if (InstancePtr->Config.IsCacheCoherent == 0) { + Xil_DCacheFlushRange((INTPTR)ReadBuff, 64); + } - XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_XFER_MODE_OFFSET, - XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK); + TransferMode = XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK; switch (Mode) { case 0U: @@ -1125,8 +1174,7 @@ static s32 XSdPs_Execute_Tuning(XSdPs *InstancePtr) XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_BLK_SIZE_OFFSET, BlkSize); - XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_XFER_MODE_OFFSET, - XSDPS_TM_DAT_DIR_SEL_MASK); + TransferMode = XSDPS_TM_DAT_DIR_SEL_MASK; CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL2_OFFSET); @@ -1141,7 +1189,7 @@ static s32 XSdPs_Execute_Tuning(XSdPs *InstancePtr) /* Wait for ~60 clock cycles to reset the tap values */ (void)usleep(1U); -#if defined (ARMR5) || defined (__aarch64__) +#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) /* Issue DLL Reset to load new SDHC tuned tap values */ XSdPs_DllReset(InstancePtr); #endif @@ -1165,7 +1213,7 @@ static s32 XSdPs_Execute_Tuning(XSdPs *InstancePtr) } if (TuningCount == 31) { -#if defined (ARMR5) || defined (__aarch64__) +#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) /* Issue DLL Reset to load new SDHC tuned tap values */ XSdPs_DllReset(InstancePtr); #endif @@ -1181,7 +1229,7 @@ static s32 XSdPs_Execute_Tuning(XSdPs *InstancePtr) /* Wait for ~12 clock cycles to synchronize the new tap values */ (void)usleep(1U); -#if defined (ARMR5) || defined (__aarch64__) +#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) /* Issue DLL Reset to load new SDHC tuned tap values */ XSdPs_DllReset(InstancePtr); #endif @@ -1192,7 +1240,7 @@ static s32 XSdPs_Execute_Tuning(XSdPs *InstancePtr) } -#if defined (ARMR5) || defined (__aarch64__) +#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) /*****************************************************************************/ /** * @@ -1213,25 +1261,48 @@ void XSdPs_sdr104_hs200_tapdelay(u32 Bank, u32 DeviceId, u32 CardType) #ifdef XPAR_PSU_SD_0_DEVICE_ID if (DeviceId == 0U) { +#if EL1_NONSECURE && defined (__aarch64__) + (void)TapDelay; + if (Bank == 2) + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_OTAPDLY) | ((u64)SD0_OTAPDLY_SEL_MASK << 32), + (u64)SD0_OTAPDLYSEL_HS200_B2, 0, 0, 0, 0, 0); + else + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_OTAPDLY) | ((u64)SD0_OTAPDLY_SEL_MASK << 32), + (u64)SD0_OTAPDLYSEL_HS200_B0, 0, 0, 0, 0, 0); +#else /* Program the OTAPDLY */ TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY); - TapDelay |= SD0_OTAPDLYENA; - XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay); + TapDelay &= ~SD0_OTAPDLY_SEL_MASK; if (Bank == 2) TapDelay |= SD0_OTAPDLYSEL_HS200_B2; else TapDelay |= SD0_OTAPDLYSEL_HS200_B0; XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay); +#endif } else { #endif + (void) DeviceId; +#if EL1_NONSECURE && defined (__aarch64__) + (void)TapDelay; + if (Bank == 2) + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_OTAPDLY) | ((u64)SD1_OTAPDLY_SEL_MASK << 32), + (u64)SD1_OTAPDLYSEL_HS200_B2, 0, 0, 0, 0, 0); + else + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_OTAPDLY) | ((u64)SD1_OTAPDLY_SEL_MASK << 32), + (u64)SD1_OTAPDLYSEL_HS200_B0, 0, 0, 0, 0, 0); +#else TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY); - TapDelay |= SD1_OTAPDLYENA; - XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay); + TapDelay &= ~SD1_OTAPDLY_SEL_MASK; if (Bank == 2) TapDelay |= SD1_OTAPDLYSEL_HS200_B2; else TapDelay |= SD1_OTAPDLYSEL_HS200_B0; XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay); +#endif #ifdef XPAR_PSU_SD_0_DEVICE_ID } #endif @@ -1258,19 +1329,32 @@ void XSdPs_sdr50_tapdelay(u32 Bank, u32 DeviceId, u32 CardType) #ifdef XPAR_PSU_SD_0_DEVICE_ID if (DeviceId == 0U) { +#if EL1_NONSECURE && defined (__aarch64__) + (void)TapDelay; + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_OTAPDLY) | + ((u64)SD0_OTAPDLY_SEL_MASK << 32), (u64)SD0_OTAPDLYSEL_SD50, + 0, 0, 0, 0, 0); +#else /* Program the OTAPDLY */ TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY); - TapDelay |= SD0_OTAPDLYENA; - XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay); + TapDelay &= ~SD0_OTAPDLY_SEL_MASK; TapDelay |= SD0_OTAPDLYSEL_SD50; XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay); +#endif } else { #endif + (void) DeviceId; +#if EL1_NONSECURE && defined (__aarch64__) + (void)TapDelay; + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_OTAPDLY) | + ((u64)SD1_OTAPDLY_SEL_MASK << 32), (u64)SD1_OTAPDLYSEL_SD50, + 0, 0, 0, 0, 0); +#else TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY); - TapDelay |= SD1_OTAPDLYENA; - XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay); + TapDelay &= ~SD1_OTAPDLY_SEL_MASK; TapDelay |= SD1_OTAPDLYSEL_SD50; XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay); +#endif #ifdef XPAR_PSU_SD_0_DEVICE_ID } #endif @@ -1296,6 +1380,33 @@ void XSdPs_ddr50_tapdelay(u32 Bank, u32 DeviceId, u32 CardType) #ifdef XPAR_PSU_SD_0_DEVICE_ID if (DeviceId == 0U) { +#if EL1_NONSECURE && defined (__aarch64__) + (void)TapDelay; + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) | + ((u64)SD0_ITAPCHGWIN << 32), (u64)SD0_ITAPCHGWIN, + 0, 0, 0, 0, 0); + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) | + ((u64)SD0_ITAPDLYENA << 32), (u64)SD0_ITAPDLYENA, + 0, 0, 0, 0, 0); + if (CardType== XSDPS_CARD_SD) + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_ITAPDLY) | ((u64)SD0_ITAPDLY_SEL_MASK << 32), + (u64)SD0_ITAPDLYSEL_SD_DDR50, 0, 0, 0, 0, 0); + else + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_ITAPDLY) | ((u64)SD0_ITAPDLY_SEL_MASK << 32), + (u64)SD0_ITAPDLYSEL_EMMC_DDR50, 0, 0, 0, 0, 0); + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) | + ((u64)SD0_ITAPCHGWIN << 32), (u64)0x0, 0, 0, 0, 0, 0); + if (CardType == XSDPS_CARD_SD) + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_OTAPDLY) | ((u64)SD0_OTAPDLY_SEL_MASK << 32), + (u64)SD0_OTAPDLYSEL_SD_DDR50, 0, 0, 0, 0, 0); + else + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_OTAPDLY) | ((u64)SD0_OTAPDLY_SEL_MASK << 32), + (u64)SD0_OTAPDLYSEL_EMMC_DDR50, 0, 0, 0, 0, 0); +#else TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY); TapDelay |= SD0_ITAPCHGWIN; XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay); @@ -1311,15 +1422,44 @@ void XSdPs_ddr50_tapdelay(u32 Bank, u32 DeviceId, u32 CardType) XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay); /* Program the OTAPDLY */ TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY); - TapDelay |= SD0_OTAPDLYENA; - XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay); + TapDelay &= ~SD0_OTAPDLY_SEL_MASK; if (CardType == XSDPS_CARD_SD) TapDelay |= SD0_OTAPDLYSEL_SD_DDR50; else TapDelay |= SD0_OTAPDLYSEL_EMMC_DDR50; XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay); +#endif } else { #endif + (void) DeviceId; +#if EL1_NONSECURE && defined (__aarch64__) + (void)TapDelay; + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) | + ((u64)SD1_ITAPCHGWIN << 32), (u64)SD1_ITAPCHGWIN, + 0, 0, 0, 0, 0); + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) | + ((u64)SD1_ITAPDLYENA << 32), (u64)SD1_ITAPDLYENA, + 0, 0, 0, 0, 0); + if (CardType== XSDPS_CARD_SD) + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_ITAPDLY) | ((u64)SD1_ITAPDLY_SEL_MASK << 32), + (u64)SD1_ITAPDLYSEL_SD_DDR50, 0, 0, 0, 0, 0); + else + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_ITAPDLY) | ((u64)SD1_ITAPDLY_SEL_MASK << 32), + (u64)SD1_ITAPDLYSEL_EMMC_DDR50, 0, 0, 0, 0, 0); + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_ITAPDLY) | ((u64)SD1_ITAPCHGWIN << 32), + (u64)0x0, 0, 0, 0, 0, 0); + if (CardType == XSDPS_CARD_SD) + Xil_Smc(MMIO_WRITE_SMC_FID,(u64)(XPS_SYS_CTRL_BASEADDR + + SD_OTAPDLY) | ((u64)SD1_OTAPDLY_SEL_MASK << 32), + (u64)SD1_OTAPDLYSEL_SD_DDR50, 0, 0, 0, 0, 0); + else + Xil_Smc(MMIO_WRITE_SMC_FID,(u64)(XPS_SYS_CTRL_BASEADDR + + SD_OTAPDLY) | ((u64)SD1_OTAPDLY_SEL_MASK << 32), + (u64)SD1_OTAPDLYSEL_EMMC_DDR50, 0, 0, 0, 0, 0); +#else TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY); TapDelay |= SD1_ITAPCHGWIN; XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay); @@ -1335,13 +1475,13 @@ void XSdPs_ddr50_tapdelay(u32 Bank, u32 DeviceId, u32 CardType) XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay); /* Program the OTAPDLY */ TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY); - TapDelay |= SD1_OTAPDLYENA; - XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay); + TapDelay &= ~SD1_OTAPDLY_SEL_MASK; if (CardType == XSDPS_CARD_SD) TapDelay |= SD1_OTAPDLYSEL_SD_DDR50; else TapDelay |= SD1_OTAPDLYSEL_EMMC_DDR50; XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay); +#endif #ifdef XPAR_PSU_SD_0_DEVICE_ID } #endif @@ -1367,6 +1507,28 @@ void XSdPs_hsd_sdr25_tapdelay(u32 Bank, u32 DeviceId, u32 CardType) #ifdef XPAR_PSU_SD_0_DEVICE_ID if (DeviceId == 0U) { +#if EL1_NONSECURE && defined (__aarch64__) + (void)TapDelay; + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) | + ((u64)SD0_ITAPCHGWIN << 32), (u64)SD0_ITAPCHGWIN, + 0, 0, 0, 0, 0); + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) | + ((u64)SD0_ITAPDLYENA << 32), (u64)SD0_ITAPDLYENA, + 0, 0, 0, 0, 0); + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) | + ((u64)SD0_ITAPDLY_SEL_MASK << 32), (u64)SD0_ITAPDLYSEL_HSD, + 0, 0, 0, 0, 0); + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) | + ((u64)SD0_ITAPCHGWIN << 32), (u64)0x0, 0, 0, 0, 0, 0); + if (CardType == XSDPS_CARD_SD) + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_OTAPDLY) | ((u64)SD0_OTAPDLY_SEL_MASK << 32), + (u64)SD0_OTAPDLYSEL_SD_HSD, 0, 0, 0, 0, 0); + else + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_OTAPDLY) | ((u64)SD0_OTAPDLY_SEL_MASK << 32), + (u64)SD0_OTAPDLYSEL_EMMC_HSD, 0, 0, 0, 0, 0); +#else TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY); TapDelay |= SD0_ITAPCHGWIN; XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay); @@ -1379,15 +1541,38 @@ void XSdPs_hsd_sdr25_tapdelay(u32 Bank, u32 DeviceId, u32 CardType) XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay); /* Program the OTAPDLY */ TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY); - TapDelay |= SD0_OTAPDLYENA; - XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay); + TapDelay &= ~SD0_OTAPDLY_SEL_MASK; if (CardType == XSDPS_CARD_SD) TapDelay |= SD0_OTAPDLYSEL_SD_HSD; else TapDelay |= SD0_OTAPDLYSEL_EMMC_HSD; XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay); +#endif } else { #endif + (void) DeviceId; +#if EL1_NONSECURE && defined (__aarch64__) + (void)TapDelay; + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) | + ((u64)SD1_ITAPCHGWIN << 32), (u64)SD1_ITAPCHGWIN, + 0, 0, 0, 0, 0); + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) | + ((u64)SD1_ITAPDLYENA << 32), (u64)SD1_ITAPDLYENA, + 0, 0, 0, 0, 0); + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) | + ((u64)SD1_ITAPDLY_SEL_MASK << 32), (u64)SD1_ITAPDLYSEL_HSD, + 0, 0, 0, 0, 0); + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) | + ((u64)SD1_ITAPCHGWIN << 32), (u64)0x0, 0, 0, 0, 0, 0); + if (CardType == XSDPS_CARD_SD) + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_OTAPDLY) | ((u64)SD1_OTAPDLY_SEL_MASK << 32), + (u64)SD1_OTAPDLYSEL_SD_HSD, 0, 0, 0, 0, 0); + else + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_OTAPDLY) | ((u64)SD1_OTAPDLY_SEL_MASK << 32), + (u64)SD1_OTAPDLYSEL_EMMC_HSD, 0, 0, 0, 0, 0); +#else TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY); TapDelay |= SD1_ITAPCHGWIN; XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay); @@ -1400,13 +1585,13 @@ void XSdPs_hsd_sdr25_tapdelay(u32 Bank, u32 DeviceId, u32 CardType) XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay); /* Program the OTAPDLY */ TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY); - TapDelay |= SD1_OTAPDLYENA; - XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay); + TapDelay &= ~SD1_OTAPDLY_SEL_MASK; if (CardType == XSDPS_CARD_SD) TapDelay |= SD1_OTAPDLYSEL_SD_HSD; else TapDelay |= SD1_OTAPDLYSEL_EMMC_HSD; XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay); +#endif #ifdef XPAR_PSU_SD_0_DEVICE_ID } #endif @@ -1434,20 +1619,48 @@ void XSdPs_SetTapDelay(XSdPs *InstancePtr) CardType = InstancePtr->CardType ; #ifdef XPAR_PSU_SD_0_DEVICE_ID if (DeviceId == 0U) { +#if EL1_NONSECURE && defined (__aarch64__) + (void)DllCtrl; + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_DLL_CTRL) | ((u64)SD0_DLL_RST << 32), + (u64)SD0_DLL_RST, 0, 0, 0, 0, 0); +#else DllCtrl = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL); DllCtrl |= SD0_DLL_RST; XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl); +#endif InstancePtr->Config_TapDelay(BankNum, DeviceId, CardType); +#if EL1_NONSECURE && defined (__aarch64__) + (void)DllCtrl; + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_DLL_CTRL) | ((u64)SD0_DLL_RST << 32), + (u64)0x0, 0, 0, 0, 0, 0); +#else DllCtrl &= ~SD0_DLL_RST; XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl); +#endif } else { #endif +#if EL1_NONSECURE && defined (__aarch64__) + (void)DllCtrl; + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_DLL_CTRL) | ((u64)SD1_DLL_RST << 32), + (u64)SD1_DLL_RST, 0, 0, 0, 0, 0); +#else DllCtrl = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL); DllCtrl |= SD1_DLL_RST; XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl); +#endif InstancePtr->Config_TapDelay(BankNum, DeviceId, CardType); +#if EL1_NONSECURE && defined (__aarch64__) + (void)DllCtrl; + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_DLL_CTRL) | ((u64)SD1_DLL_RST << 32), + (u64)0x0, 0, 0, 0, 0, 0); +#else DllCtrl &= ~SD1_DLL_RST; XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl); +#endif #ifdef XPAR_PSU_SD_0_DEVICE_ID } #endif @@ -1480,11 +1693,26 @@ static void XSdPs_DllReset(XSdPs *InstancePtr) /* Issue DLL Reset to load zero tap values */ DllCtrl = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL); if (InstancePtr->Config.DeviceId == 0U) { +#if EL1_NONSECURE && defined (__aarch64__) + (void)DllCtrl; + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_DLL_CTRL) | ((u64)SD0_DLL_RST << 32), + (u64)SD0_DLL_RST, 0, 0, 0, 0, 0); +#else DllCtrl |= SD0_DLL_RST; + XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl); +#endif } else { +#if EL1_NONSECURE && defined (__aarch64__) + (void)DllCtrl; + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_DLL_CTRL) | ((u64)SD1_DLL_RST << 32), + (u64)SD1_DLL_RST, 0, 0, 0, 0, 0); +#else DllCtrl |= SD1_DLL_RST; + XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl); +#endif } - XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl); /* Wait for 2 micro seconds */ (void)usleep(2U); @@ -1492,11 +1720,26 @@ static void XSdPs_DllReset(XSdPs *InstancePtr) /* Release the DLL out of reset */ DllCtrl = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL); if (InstancePtr->Config.DeviceId == 0U) { +#if EL1_NONSECURE && defined (__aarch64__) + (void)DllCtrl; + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_DLL_CTRL) | ((u64)SD0_DLL_RST << 32), + (u64)0x0, 0, 0, 0, 0, 0); +#else DllCtrl &= ~SD0_DLL_RST; + XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl); +#endif } else { +#if EL1_NONSECURE && defined (__aarch64__) + (void)DllCtrl; + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_DLL_CTRL) | ((u64)SD1_DLL_RST << 32), + (u64)0x0, 0, 0, 0, 0, 0); +#else DllCtrl &= ~SD1_DLL_RST; + XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl); +#endif } - XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl); /* Wait for internal clock to stabilize */ ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_1/src/xsdps_sinit.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sdps_v3_4/src/xsdps_sinit.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_1/src/xsdps_sinit.c rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sdps_v3_4/src/xsdps_sinit.c index e0936b308..b49a0064c 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_1/src/xsdps_sinit.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sdps_v3_4/src/xsdps_sinit.c @@ -33,7 +33,7 @@ /** * * @file xsdps_sinit.c -* @addtogroup sdps_v2_5 +* @addtogroup sdps_v3_4 * @{ * * The implementation of the XSdPs component's static initialization diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/asm_vectors.S b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/asm_vectors.S deleted file mode 100644 index a08867a16..000000000 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/asm_vectors.S +++ /dev/null @@ -1,208 +0,0 @@ -/****************************************************************************** -* -* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved. -* -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: -* -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. -* -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. -* -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* @file asm_vectors.s -* -* This file contains the initial vector table for the Cortex A53 processor -* Currently NEON registers are not saved on stack if interrupt is taken. -* It will be implemented. -* -* 
-* MODIFICATION HISTORY:
-*
-* Ver   Who     Date     Changes
-* ----- ------- -------- ---------------------------------------------------
-* 5.00	pkp	5/21/14 Initial version
-*
-* -* @note -* -* None. -* -******************************************************************************/ - - - -.org 0 -.text - -.globl _boot -.globl _vector_table - -.globl FIQInterrupt -.globl IRQInterrupt -.globl SErrorInterrupt -.globl SynchronousInterrupt - - -.org 0 - -.section .vectors, "a" - -_vector_table: - -.set VBAR, _vector_table -.org VBAR - b _boot -.org (VBAR + 0x200) - b SynchronousInterruptHandler - -.org (VBAR + 0x280) - b IRQInterruptHandler - -.org (VBAR + 0x300) - b FIQInterruptHandler - -.org (VBAR + 0x380) - b SErrorInterruptHandler - - -SynchronousInterruptHandler: - stp X0,X1, [sp,#-0x10]! - stp X2,X3, [sp,#-0x10]! - stp X4,X5, [sp,#-0x10]! - stp X6,X7, [sp,#-0x10]! - stp X8,X9, [sp,#-0x10]! - stp X10,X11, [sp,#-0x10]! - stp X12,X13, [sp,#-0x10]! - stp X14,X15, [sp,#-0x10]! - stp X16,X17, [sp,#-0x10]! - stp X18,X19, [sp,#-0x10]! - stp X29,X30, [sp,#-0x10]! - - bl SynchronousInterrupt - - ldp X29,X30, [sp], #0x10 - ldp X18,X19, [sp], #0x10 - ldp X16,X17, [sp], #0x10 - ldp X14,X15, [sp], #0x10 - ldp X12,X13, [sp], #0x10 - ldp X10,X11, [sp], #0x10 - ldp X8,X9, [sp], #0x10 - ldp X6,X7, [sp], #0x10 - ldp X4,X5, [sp], #0x10 - ldp X2,X3, [sp], #0x10 - ldp X0,X1, [sp], #0x10 - - eret - -IRQInterruptHandler: - stp X0,X1, [sp,#-0x10]! - stp X2,X3, [sp,#-0x10]! - stp X4,X5, [sp,#-0x10]! - stp X6,X7, [sp,#-0x10]! - stp X8,X9, [sp,#-0x10]! - stp X10,X11, [sp,#-0x10]! - stp X12,X13, [sp,#-0x10]! - stp X14,X15, [sp,#-0x10]! - stp X16,X17, [sp,#-0x10]! - stp X18,X19, [sp,#-0x10]! - stp X29,X30, [sp,#-0x10]! - - bl IRQInterrupt - - ldp X29,X30, [sp], #0x10 - ldp X18,X19, [sp], #0x10 - ldp X16,X17, [sp], #0x10 - ldp X14,X15, [sp], #0x10 - ldp X12,X13, [sp], #0x10 - ldp X10,X11, [sp], #0x10 - ldp X8,X9, [sp], #0x10 - ldp X6,X7, [sp], #0x10 - ldp X4,X5, [sp], #0x10 - ldp X2,X3, [sp], #0x10 - ldp X0,X1, [sp], #0x10 - - eret - -FIQInterruptHandler: - - stp X0,X1, [sp,#-0x10]! - stp X2,X3, [sp,#-0x10]! - stp X4,X5, [sp,#-0x10]! - stp X6,X7, [sp,#-0x10]! - stp X8,X9, [sp,#-0x10]! - stp X10,X11, [sp,#-0x10]! - stp X12,X13, [sp,#-0x10]! - stp X14,X15, [sp,#-0x10]! - stp X16,X17, [sp,#-0x10]! - stp X18,X19, [sp,#-0x10]! - stp X29,X30, [sp,#-0x10]! - - bl FIQInterrupt - - ldp X29,X30, [sp], #0x10 - ldp X18,X19, [sp], #0x10 - ldp X16,X17, [sp], #0x10 - ldp X14,X15, [sp], #0x10 - ldp X12,X13, [sp], #0x10 - ldp X10,X11, [sp], #0x10 - ldp X8,X9, [sp], #0x10 - ldp X6,X7, [sp], #0x10 - ldp X4,X5, [sp], #0x10 - ldp X2,X3, [sp], #0x10 - ldp X0,X1, [sp], #0x10 - - eret - -SErrorInterruptHandler: - - stp X0,X1, [sp,#-0x10]! - stp X2,X3, [sp,#-0x10]! - stp X4,X5, [sp,#-0x10]! - stp X6,X7, [sp,#-0x10]! - stp X8,X9, [sp,#-0x10]! - stp X10,X11, [sp,#-0x10]! - stp X12,X13, [sp,#-0x10]! - stp X14,X15, [sp,#-0x10]! - stp X16,X17, [sp,#-0x10]! - stp X18,X19, [sp,#-0x10]! - stp X29,X30, [sp,#-0x10]! - - bl SErrorInterrupt - - ldp X29,X30, [sp], #0x10 - ldp X18,X19, [sp], #0x10 - ldp X16,X17, [sp], #0x10 - ldp X14,X15, [sp], #0x10 - ldp X12,X13, [sp], #0x10 - ldp X10,X11, [sp], #0x10 - ldp X8,X9, [sp], #0x10 - ldp X6,X7, [sp], #0x10 - ldp X4,X5, [sp], #0x10 - ldp X2,X3, [sp], #0x10 - ldp X0,X1, [sp], #0x10 - - eret - -.end diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/sleep.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/sleep.h deleted file mode 100644 index 27add6605..000000000 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/sleep.h +++ /dev/null @@ -1,50 +0,0 @@ -/****************************************************************************** -* -* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved. -* -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: -* -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. -* -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. -* -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. -* -******************************************************************************/ - -#ifndef SLEEP_H -#define SLEEP_H - -#include "xil_types.h" -#include "xil_io.h" - -#ifdef __cplusplus -extern "C" { -#endif - -int usleep(unsigned long useconds); -unsigned sleep(unsigned int seconds); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xstatus.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xstatus.h deleted file mode 100644 index 4873e85eb..000000000 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xstatus.h +++ /dev/null @@ -1,432 +0,0 @@ -/****************************************************************************** -* -* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved. -* -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: -* -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. -* -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. -* -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xstatus.h -* -* This file contains Xilinx software status codes. Status codes have their -* own data type called int. These codes are used throughout the Xilinx -* device drivers. -* -******************************************************************************/ - -#ifndef XSTATUS_H /* prevent circular inclusions */ -#define XSTATUS_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************** Include Files *********************************/ - -#include "xil_types.h" -#include "xil_assert.h" - -/************************** Constant Definitions *****************************/ - -/*********************** Common statuses 0 - 500 *****************************/ - -#define XST_SUCCESS 0L -#define XST_FAILURE 1L -#define XST_DEVICE_NOT_FOUND 2L -#define XST_DEVICE_BLOCK_NOT_FOUND 3L -#define XST_INVALID_VERSION 4L -#define XST_DEVICE_IS_STARTED 5L -#define XST_DEVICE_IS_STOPPED 6L -#define XST_FIFO_ERROR 7L /* an error occurred during an - operation with a FIFO such as - an underrun or overrun, this - error requires the device to - be reset */ -#define XST_RESET_ERROR 8L /* an error occurred which requires - the device to be reset */ -#define XST_DMA_ERROR 9L /* a DMA error occurred, this error - typically requires the device - using the DMA to be reset */ -#define XST_NOT_POLLED 10L /* the device is not configured for - polled mode operation */ -#define XST_FIFO_NO_ROOM 11L /* a FIFO did not have room to put - the specified data into */ -#define XST_BUFFER_TOO_SMALL 12L /* the buffer is not large enough - to hold the expected data */ -#define XST_NO_DATA 13L /* there was no data available */ -#define XST_REGISTER_ERROR 14L /* a register did not contain the - expected value */ -#define XST_INVALID_PARAM 15L /* an invalid parameter was passed - into the function */ -#define XST_NOT_SGDMA 16L /* the device is not configured for - scatter-gather DMA operation */ -#define XST_LOOPBACK_ERROR 17L /* a loopback test failed */ -#define XST_NO_CALLBACK 18L /* a callback has not yet been - registered */ -#define XST_NO_FEATURE 19L /* device is not configured with - the requested feature */ -#define XST_NOT_INTERRUPT 20L /* device is not configured for - interrupt mode operation */ -#define XST_DEVICE_BUSY 21L /* device is busy */ -#define XST_ERROR_COUNT_MAX 22L /* the error counters of a device - have maxed out */ -#define XST_IS_STARTED 23L /* used when part of device is - already started i.e. - sub channel */ -#define XST_IS_STOPPED 24L /* used when part of device is - already stopped i.e. - sub channel */ -#define XST_DATA_LOST 26L /* driver defined error */ -#define XST_RECV_ERROR 27L /* generic receive error */ -#define XST_SEND_ERROR 28L /* generic transmit error */ -#define XST_NOT_ENABLED 29L /* a requested service is not - available because it has not - been enabled */ - -/***************** Utility Component statuses 401 - 500 *********************/ - -#define XST_MEMTEST_FAILED 401L /* memory test failed */ - - -/***************** Common Components statuses 501 - 1000 *********************/ - -/********************* Packet Fifo statuses 501 - 510 ************************/ - -#define XST_PFIFO_LACK_OF_DATA 501L /* not enough data in FIFO */ -#define XST_PFIFO_NO_ROOM 502L /* not enough room in FIFO */ -#define XST_PFIFO_BAD_REG_VALUE 503L /* self test, a register value - was invalid after reset */ -#define XST_PFIFO_ERROR 504L /* generic packet FIFO error */ -#define XST_PFIFO_DEADLOCK 505L /* packet FIFO is reporting - * empty and full simultaneously - */ - -/************************** DMA statuses 511 - 530 ***************************/ - -#define XST_DMA_TRANSFER_ERROR 511L /* self test, DMA transfer - failed */ -#define XST_DMA_RESET_REGISTER_ERROR 512L /* self test, a register value - was invalid after reset */ -#define XST_DMA_SG_LIST_EMPTY 513L /* scatter gather list contains - no buffer descriptors ready - to be processed */ -#define XST_DMA_SG_IS_STARTED 514L /* scatter gather not stopped */ -#define XST_DMA_SG_IS_STOPPED 515L /* scatter gather not running */ -#define XST_DMA_SG_LIST_FULL 517L /* all the buffer desciptors of - the scatter gather list are - being used */ -#define XST_DMA_SG_BD_LOCKED 518L /* the scatter gather buffer - descriptor which is to be - copied over in the scatter - list is locked */ -#define XST_DMA_SG_NOTHING_TO_COMMIT 519L /* no buffer descriptors have been - put into the scatter gather - list to be commited */ -#define XST_DMA_SG_COUNT_EXCEEDED 521L /* the packet count threshold - specified was larger than the - total # of buffer descriptors - in the scatter gather list */ -#define XST_DMA_SG_LIST_EXISTS 522L /* the scatter gather list has - already been created */ -#define XST_DMA_SG_NO_LIST 523L /* no scatter gather list has - been created */ -#define XST_DMA_SG_BD_NOT_COMMITTED 524L /* the buffer descriptor which was - being started was not committed - to the list */ -#define XST_DMA_SG_NO_DATA 525L /* the buffer descriptor to start - has already been used by the - hardware so it can't be reused - */ -#define XST_DMA_SG_LIST_ERROR 526L /* general purpose list access - error */ -#define XST_DMA_BD_ERROR 527L /* general buffer descriptor - error */ - -/************************** IPIF statuses 531 - 550 ***************************/ - -#define XST_IPIF_REG_WIDTH_ERROR 531L /* an invalid register width - was passed into the function */ -#define XST_IPIF_RESET_REGISTER_ERROR 532L /* the value of a register at - reset was not valid */ -#define XST_IPIF_DEVICE_STATUS_ERROR 533L /* a write to the device interrupt - status register did not read - back correctly */ -#define XST_IPIF_DEVICE_ACK_ERROR 534L /* the device interrupt status - register did not reset when - acked */ -#define XST_IPIF_DEVICE_ENABLE_ERROR 535L /* the device interrupt enable - register was not updated when - other registers changed */ -#define XST_IPIF_IP_STATUS_ERROR 536L /* a write to the IP interrupt - status register did not read - back correctly */ -#define XST_IPIF_IP_ACK_ERROR 537L /* the IP interrupt status register - did not reset when acked */ -#define XST_IPIF_IP_ENABLE_ERROR 538L /* IP interrupt enable register was - not updated correctly when other - registers changed */ -#define XST_IPIF_DEVICE_PENDING_ERROR 539L /* The device interrupt pending - register did not indicate the - expected value */ -#define XST_IPIF_DEVICE_ID_ERROR 540L /* The device interrupt ID register - did not indicate the expected - value */ -#define XST_IPIF_ERROR 541L /* generic ipif error */ - -/****************** Device specific statuses 1001 - 4095 *********************/ - -/********************* Ethernet statuses 1001 - 1050 *************************/ - -#define XST_EMAC_MEMORY_SIZE_ERROR 1001L /* Memory space is not big enough - * to hold the minimum number of - * buffers or descriptors */ -#define XST_EMAC_MEMORY_ALLOC_ERROR 1002L /* Memory allocation failed */ -#define XST_EMAC_MII_READ_ERROR 1003L /* MII read error */ -#define XST_EMAC_MII_BUSY 1004L /* An MII operation is in progress */ -#define XST_EMAC_OUT_OF_BUFFERS 1005L /* Driver is out of buffers */ -#define XST_EMAC_PARSE_ERROR 1006L /* Invalid driver init string */ -#define XST_EMAC_COLLISION_ERROR 1007L /* Excess deferral or late - * collision on polled send */ - -/*********************** UART statuses 1051 - 1075 ***************************/ -#define XST_UART - -#define XST_UART_INIT_ERROR 1051L -#define XST_UART_START_ERROR 1052L -#define XST_UART_CONFIG_ERROR 1053L -#define XST_UART_TEST_FAIL 1054L -#define XST_UART_BAUD_ERROR 1055L -#define XST_UART_BAUD_RANGE 1056L - - -/************************ IIC statuses 1076 - 1100 ***************************/ - -#define XST_IIC_SELFTEST_FAILED 1076 /* self test failed */ -#define XST_IIC_BUS_BUSY 1077 /* bus found busy */ -#define XST_IIC_GENERAL_CALL_ADDRESS 1078 /* mastersend attempted with */ - /* general call address */ -#define XST_IIC_STAND_REG_RESET_ERROR 1079 /* A non parameterizable reg */ - /* value after reset not valid */ -#define XST_IIC_TX_FIFO_REG_RESET_ERROR 1080 /* Tx fifo included in design */ - /* value after reset not valid */ -#define XST_IIC_RX_FIFO_REG_RESET_ERROR 1081 /* Rx fifo included in design */ - /* value after reset not valid */ -#define XST_IIC_TBA_REG_RESET_ERROR 1082 /* 10 bit addr incl in design */ - /* value after reset not valid */ -#define XST_IIC_CR_READBACK_ERROR 1083 /* Read of the control register */ - /* didn't return value written */ -#define XST_IIC_DTR_READBACK_ERROR 1084 /* Read of the data Tx reg */ - /* didn't return value written */ -#define XST_IIC_DRR_READBACK_ERROR 1085 /* Read of the data Receive reg */ - /* didn't return value written */ -#define XST_IIC_ADR_READBACK_ERROR 1086 /* Read of the data Tx reg */ - /* didn't return value written */ -#define XST_IIC_TBA_READBACK_ERROR 1087 /* Read of the 10 bit addr reg */ - /* didn't return written value */ -#define XST_IIC_NOT_SLAVE 1088 /* The device isn't a slave */ - -/*********************** ATMC statuses 1101 - 1125 ***************************/ - -#define XST_ATMC_ERROR_COUNT_MAX 1101L /* the error counters in the ATM - controller hit the max value - which requires the statistics - to be cleared */ - -/*********************** Flash statuses 1126 - 1150 **************************/ - -#define XST_FLASH_BUSY 1126L /* Flash is erasing or programming - */ -#define XST_FLASH_READY 1127L /* Flash is ready for commands */ -#define XST_FLASH_ERROR 1128L /* Flash had detected an internal - error. Use XFlash_DeviceControl - to retrieve device specific codes - */ -#define XST_FLASH_ERASE_SUSPENDED 1129L /* Flash is in suspended erase state - */ -#define XST_FLASH_WRITE_SUSPENDED 1130L /* Flash is in suspended write state - */ -#define XST_FLASH_PART_NOT_SUPPORTED 1131L /* Flash type not supported by - driver */ -#define XST_FLASH_NOT_SUPPORTED 1132L /* Operation not supported */ -#define XST_FLASH_TOO_MANY_REGIONS 1133L /* Too many erase regions */ -#define XST_FLASH_TIMEOUT_ERROR 1134L /* Programming or erase operation - aborted due to a timeout */ -#define XST_FLASH_ADDRESS_ERROR 1135L /* Accessed flash outside its - addressible range */ -#define XST_FLASH_ALIGNMENT_ERROR 1136L /* Write alignment error */ -#define XST_FLASH_BLOCKING_CALL_ERROR 1137L /* Couldn't return immediately from - write/erase function with - XFL_NON_BLOCKING_WRITE/ERASE - option cleared */ -#define XST_FLASH_CFI_QUERY_ERROR 1138L /* Failed to query the device */ - -/*********************** SPI statuses 1151 - 1175 ****************************/ - -#define XST_SPI_MODE_FAULT 1151 /* master was selected as slave */ -#define XST_SPI_TRANSFER_DONE 1152 /* data transfer is complete */ -#define XST_SPI_TRANSMIT_UNDERRUN 1153 /* slave underruns transmit register */ -#define XST_SPI_RECEIVE_OVERRUN 1154 /* device overruns receive register */ -#define XST_SPI_NO_SLAVE 1155 /* no slave has been selected yet */ -#define XST_SPI_TOO_MANY_SLAVES 1156 /* more than one slave is being - * selected */ -#define XST_SPI_NOT_MASTER 1157 /* operation is valid only as master */ -#define XST_SPI_SLAVE_ONLY 1158 /* device is configured as slave-only - */ -#define XST_SPI_SLAVE_MODE_FAULT 1159 /* slave was selected while disabled */ -#define XST_SPI_SLAVE_MODE 1160 /* device has been addressed as slave */ -#define XST_SPI_RECEIVE_NOT_EMPTY 1161 /* device received data in slave mode */ - -#define XST_SPI_COMMAND_ERROR 1162 /* unrecognised command - qspi only */ -#define XST_SPI_POLL_DONE 1163 /* controller completed polling the - device for status */ - -/********************** OPB Arbiter statuses 1176 - 1200 *********************/ - -#define XST_OPBARB_INVALID_PRIORITY 1176 /* the priority registers have either - * one master assigned to two or more - * priorities, or one master not - * assigned to any priority - */ -#define XST_OPBARB_NOT_SUSPENDED 1177 /* an attempt was made to modify the - * priority levels without first - * suspending the use of priority - * levels - */ -#define XST_OPBARB_PARK_NOT_ENABLED 1178 /* bus parking by id was enabled but - * bus parking was not enabled - */ -#define XST_OPBARB_NOT_FIXED_PRIORITY 1179 /* the arbiter must be in fixed - * priority mode to allow the - * priorities to be changed - */ - -/************************ Intc statuses 1201 - 1225 **************************/ - -#define XST_INTC_FAIL_SELFTEST 1201 /* self test failed */ -#define XST_INTC_CONNECT_ERROR 1202 /* interrupt already in use */ - -/********************** TmrCtr statuses 1226 - 1250 **************************/ - -#define XST_TMRCTR_TIMER_FAILED 1226 /* self test failed */ - -/********************** WdtTb statuses 1251 - 1275 ***************************/ - -#define XST_WDTTB_TIMER_FAILED 1251L - -/********************** PlbArb statuses 1276 - 1300 **************************/ - -#define XST_PLBARB_FAIL_SELFTEST 1276L - -/********************** Plb2Opb statuses 1301 - 1325 *************************/ - -#define XST_PLB2OPB_FAIL_SELFTEST 1301L - -/********************** Opb2Plb statuses 1326 - 1350 *************************/ - -#define XST_OPB2PLB_FAIL_SELFTEST 1326L - -/********************** SysAce statuses 1351 - 1360 **************************/ - -#define XST_SYSACE_NO_LOCK 1351L /* No MPU lock has been granted */ - -/********************** PCI Bridge statuses 1361 - 1375 **********************/ - -#define XST_PCI_INVALID_ADDRESS 1361L - -/********************** FlexRay constants 1400 - 1409 *************************/ - -#define XST_FR_TX_ERROR 1400 -#define XST_FR_TX_BUSY 1401 -#define XST_FR_BUF_LOCKED 1402 -#define XST_FR_NO_BUF 1403 - -/****************** USB constants 1410 - 1420 *******************************/ - -#define XST_USB_ALREADY_CONFIGURED 1410 -#define XST_USB_BUF_ALIGN_ERROR 1411 -#define XST_USB_NO_DESC_AVAILABLE 1412 -#define XST_USB_BUF_TOO_BIG 1413 -#define XST_USB_NO_BUF 1414 - -/****************** HWICAP constants 1421 - 1429 *****************************/ - -#define XST_HWICAP_WRITE_DONE 1421 - - -/****************** AXI VDMA constants 1430 - 1440 *****************************/ - -#define XST_VDMA_MISMATCH_ERROR 1430 - -/*********************** NAND Flash statuses 1441 - 1459 *********************/ - -#define XST_NAND_BUSY 1441L /* Flash is erasing or - * programming - */ -#define XST_NAND_READY 1442L /* Flash is ready for commands - */ -#define XST_NAND_ERROR 1443L /* Flash had detected an - * internal error. - */ -#define XST_NAND_PART_NOT_SUPPORTED 1444L /* Flash type not supported by - * driver - */ -#define XST_NAND_OPT_NOT_SUPPORTED 1445L /* Operation not supported - */ -#define XST_NAND_TIMEOUT_ERROR 1446L /* Programming or erase - * operation aborted due to a - * timeout - */ -#define XST_NAND_ADDRESS_ERROR 1447L /* Accessed flash outside its - * addressible range - */ -#define XST_NAND_ALIGNMENT_ERROR 1448L /* Write alignment error - */ -#define XST_NAND_PARAM_PAGE_ERROR 1449L /* Failed to read parameter - * page of the device - */ -#define XST_NAND_CACHE_ERROR 1450L /* Flash page buffer error - */ - -#define XST_NAND_WRITE_PROTECTED 1451L /* Flash is write protected - */ - -/**************************** Type Definitions *******************************/ - -typedef s32 XStatus; - -/***************** Macros (Inline Functions) Definitions *********************/ - - -/************************** Function Prototypes ******************************/ - -#ifdef __cplusplus -} -#endif - -#endif /* end of protection macro */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/Makefile b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/Makefile similarity index 82% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/Makefile rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/Makefile index 0425bf6c1..a97e121ed 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/Makefile +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/Makefile @@ -40,7 +40,10 @@ LIB=libxil.a CC_FLAGS = $(subst -pg, -DPROFILING, $(COMPILER_FLAGS)) ECC_FLAGS = $(subst -pg, -DPROFILING, $(EXTRA_COMPILER_FLAGS)) -ECC_FLAGS += -march=armv8-a +ECC_FLAGS += -nostartfiles\ + -march=armv8-a +ECC_FLAGS_NO_FLTO1 = $(subst -flto,,$(ECC_FLAGS)) +ECC_FLAGS_NO_FLTO = $(subst -ffat-lto-objects,,$(ECC_FLAGS_NO_FLTO1)) RELEASEDIR=../../../lib @@ -48,14 +51,16 @@ INCLUDEDIR=../../../include INCLUDES=-I./. -I${INCLUDEDIR} OUTS = *.o - +OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c))) +ASSEMBLY_OBJECTS = $(addsuffix .o, $(basename $(wildcard *.S))) INCLUDEFILES=*.h INCLUDEFILES+=includes_ps/*.h libs: $(LIBS) standalone_libs: $(LIBSOURCES) echo "Compiling standalone A53" - $(CC) $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $^ + $(CC) $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $(filter-out _exit.c, $^) + $(CC) $(CC_FLAGS) $(ECC_FLAGS_NO_FLTO) $(INCLUDES) _exit.c $(AR) -r ${RELEASEDIR}/${LIB} ${OUTS} .PHONY: include @@ -65,5 +70,5 @@ standalone_includes: ${CP} ${INCLUDEFILES} ${INCLUDEDIR} clean: - rm -rf ${OUTS} - $(MAKE) -C COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(CC)" ARCHIVER="$(AR)" clean + rm -rf ${OBJECTS} + rm -rf ${ASSEMBLY_OBJECTS} diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/_exit.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/_exit.c similarity index 100% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/_exit.c rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/_exit.c diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/_open.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/_open.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/_open.c rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/_open.c index 9b5a23adf..a108b7716 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/_open.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/_open.c @@ -45,7 +45,7 @@ extern "C" { */ __attribute__((weak)) s32 _open(const char8 *buf, s32 flags, s32 mode) { - (void *)buf; + (void)buf; (void)flags; (void)mode; errno = EIO; diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/_sbrk.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/_sbrk.c similarity index 95% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/_sbrk.c rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/_sbrk.c index 2a069ec06..967bdfc5b 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/_sbrk.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/_sbrk.c @@ -54,15 +54,10 @@ __attribute__((weak)) caddr_t _sbrk ( s32 incr ) } prev_heap = heap; + if (((heap + incr) <= HeapEndPtr) && (prev_heap != NULL)) { heap += incr; - - if (heap > HeapEndPtr){ - Status = (caddr_t) -1; - } - else if (prev_heap != NULL) { Status = (caddr_t) ((void *)prev_heap); - } - else { + } else { Status = (caddr_t) -1; } diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/abort.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/abort.c similarity index 100% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/abort.c rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/abort.c diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/asm_vectors.S b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/asm_vectors.S new file mode 100644 index 000000000..56bb9aec2 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/asm_vectors.S @@ -0,0 +1,374 @@ +/****************************************************************************** +* +* Copyright (C) 2014 - 2018 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file asm_vectors.s +* +* This file contains the initial vector table for the Cortex A53 processor +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------- -------- ---------------------------------------------------
+* 5.00	pkp	05/21/14 Initial version
+* 6.02  pkp	12/21/16 Added support for floating point access
+* 6.02  pkp	01/22/17 Added support for EL1 non-secure and hypervisor
+*			 baremetal guest
+* 6.4   mus     06/14/17 Fixed bug in IRQInterruptHandler code snippet,
+*                        which checks for the FPEN bit of CPACR_EL1
+* 6.6   mus     01/19/18 Added isb after writing to the cpacr_el1/cptr_el3,
+*                        to ensure enabling/disabling of floating-point unit
+*                        is completed, before any subsequent instruction.
+*
+*
+* +* @note +* +* None. +* +******************************************************************************/ + +#include "bspconfig.h" + +.org 0 +.text + +.globl _boot +.globl _vector_table + +.globl FIQInterrupt +.globl IRQInterrupt +.globl SErrorInterrupt +.globl SynchronousInterrupt +.globl FPUStatus + +/* + * FPUContextSize is the size of the array where floating point registers are + * stored when required. The default size corresponds to the case when there is no + * nested interrupt. If there are nested interrupts in application which are using + * floating point operation, the size of FPUContextSize need to be increased as per + * requirement + */ + +.set FPUContextSize, 528 + +.macro saveregister + stp X0,X1, [sp,#-0x10]! + stp X2,X3, [sp,#-0x10]! + stp X4,X5, [sp,#-0x10]! + stp X6,X7, [sp,#-0x10]! + stp X8,X9, [sp,#-0x10]! + stp X10,X11, [sp,#-0x10]! + stp X12,X13, [sp,#-0x10]! + stp X14,X15, [sp,#-0x10]! + stp X16,X17, [sp,#-0x10]! + stp X18,X19, [sp,#-0x10]! + stp X29,X30, [sp,#-0x10]! +.endm + +.macro restoreregister + ldp X29,X30, [sp], #0x10 + ldp X18,X19, [sp], #0x10 + ldp X16,X17, [sp], #0x10 + ldp X14,X15, [sp], #0x10 + ldp X12,X13, [sp], #0x10 + ldp X10,X11, [sp], #0x10 + ldp X8,X9, [sp], #0x10 + ldp X6,X7, [sp], #0x10 + ldp X4,X5, [sp], #0x10 + ldp X2,X3, [sp], #0x10 + ldp X0,X1, [sp], #0x10 +.endm + +.macro savefloatregister + +/* Load the floating point context array address from FPUContextBase */ + ldr x1,=FPUContextBase + ldr x0, [x1] + +/* Save all the floating point register to the array */ + stp q0,q1, [x0], #0x20 + stp q2,q3, [x0], #0x20 + stp q4,q5, [x0], #0x20 + stp q6,q7, [x0], #0x20 + stp q8,q9, [x0], #0x20 + stp q10,q11, [x0], #0x20 + stp q12,q13, [x0], #0x20 + stp q14,q15, [x0], #0x20 + stp q16,q17, [x0], #0x20 + stp q18,q19, [x0], #0x20 + stp q20,q21, [x0], #0x20 + stp q22,q23, [x0], #0x20 + stp q24,q25, [x0], #0x20 + stp q26,q27, [x0], #0x20 + stp q28,q29, [x0], #0x20 + stp q30,q31, [x0], #0x20 + mrs x2, FPCR + mrs x3, FPSR + stp x2, x3, [x0], #0x10 + +/* Save current address of floating point context array to FPUContextBase */ + str x0, [x1] +.endm + +.macro restorefloatregister + +/* Restore the address of floating point context array from FPUContextBase */ + ldr x1,=FPUContextBase + ldr x0, [x1] + +/* Restore all the floating point register from the array */ + ldp x2, x3, [x0,#-0x10]! + msr FPCR, x2 + msr FPSR, x3 + ldp q30,q31, [x0,#-0x20]! + ldp q28,q29, [x0,#-0x20]! + ldp q26,q27, [x0,#-0x20]! + ldp q24,q25, [x0,#-0x20]! + ldp q22,q23, [x0,#-0x20]! + ldp q20,q21, [x0,#-0x20]! + ldp q18,q19, [x0,#-0x20]! + ldp q16,q17, [x0,#-0x20]! + ldp q14,q15, [x0,#-0x20]! + ldp q12,q13, [x0,#-0x20]! + ldp q10,q11, [x0,#-0x20]! + ldp q8,q9, [x0,#-0x20]! + ldp q6,q7, [x0,#-0x20]! + ldp q4,q5, [x0,#-0x20]! + ldp q2,q3, [x0,#-0x20]! + ldp q0,q1, [x0,#-0x20]! + +/* Save current address of floating point context array to FPUContextBase */ + str x0, [x1] +.endm + + +.org 0 + +.section .vectors, "a" + +_vector_table: +.set VBAR, _vector_table +.org VBAR +/* + * if application is built for XEN GUEST as EL1 Non-secure following image + * header is required by XEN. + */ +.if (HYP_GUEST == 1) + + /* Valid Image header. */ + /* HW reset vector. */ + ldr x16, =_boot + br x16 + + /* text offset. */ + .dword 0 + /* image size. */ + .dword 0 + /* flags. */ + .dword 8 + /* RES0 */ + .dword 0 + .dword 0 + .dword 0 + + /* magic */ + .dword 0x644d5241 + /* RES0 */ + .dword 0 + /* End of Image header. */ +.endif + + b _boot +.org (VBAR + 0x200) + b SynchronousInterruptHandler + +.org (VBAR + 0x280) + b IRQInterruptHandler + +.org (VBAR + 0x300) + b FIQInterruptHandler + +.org (VBAR + 0x380) + b SErrorInterruptHandler + + +SynchronousInterruptHandler: + saveregister + +/* Check if the Synchronous abort is occured due to floating point access. */ +.if (EL3 == 1) + mrs x0, ESR_EL3 +.else + mrs x0, ESR_EL1 +.endif + and x0, x0, #(0x3F << 26) + mov x1, #(0x7 << 26) + cmp x0, x1 +/* If exception is not due to floating point access go to synchronous handler */ + bne synchronoushandler + +/* + * If excpetion occured due to floating point access, Enable the floating point + * access i.e. do not trap floating point instruction + */ + .if (EL3 == 1) + mrs x1,CPTR_EL3 + bic x1, x1, #(0x1<<10) + msr CPTR_EL3, x1 +.else + mrs x1,CPACR_EL1 + orr x1, x1, #(0x1<<20) + msr CPACR_EL1, x1 +.endif + isb + +/* If the floating point access was previously enabled, store FPU context + * registers(storefloat). + */ + ldr x0, =FPUStatus + ldrb w1,[x0] + cbnz w1, storefloat +/* + * If the floating point access was not enabled previously, save the status of + * floating point accessibility i.e. enabled and store floating point context + * array address(FPUContext) to FPUContextBase. + */ + mov w1, #0x1 + strb w1, [x0] + ldr x0, =FPUContext + ldr x1, =FPUContextBase + str x0,[x1] + b restorecontext +storefloat: + savefloatregister + b restorecontext +synchronoushandler: + bl SynchronousInterrupt +restorecontext: + restoreregister + eret + +IRQInterruptHandler: + + saveregister +/* Save the status of SPSR, ELR and CPTR to stack */ + .if (EL3 == 1) + mrs x0, CPTR_EL3 + mrs x1, ELR_EL3 + mrs x2, SPSR_EL3 +.else + mrs x0, CPACR_EL1 + mrs x1, ELR_EL1 + mrs x2, SPSR_EL1 +.endif + stp x0, x1, [sp,#-0x10]! + str x2, [sp,#-0x10]! + +/* Trap floating point access */ + .if (EL3 == 1) + mrs x1,CPTR_EL3 + orr x1, x1, #(0x1<<10) + msr CPTR_EL3, x1 +.else + mrs x1,CPACR_EL1 + bic x1, x1, #(0x1<<20) + msr CPACR_EL1, x1 +.endif + isb + + bl IRQInterrupt +/* + * If floating point access is enabled during interrupt handling, + * restore floating point registers. + */ + + .if (EL3 == 1) + mrs x0, CPTR_EL3 + ands x0, x0, #(0x1<<10) + bne RestorePrevState +.else + mrs x0,CPACR_EL1 + ands x0, x0, #(0x1<<20) + beq RestorePrevState +.endif + + restorefloatregister + +/* Restore the status of SPSR, ELR and CPTR from stack */ +RestorePrevState: + ldr x2,[sp],0x10 + ldp x0, x1, [sp],0x10 + .if (EL3 == 1) + msr CPTR_EL3, x0 + msr ELR_EL3, x1 + msr SPSR_EL3, x2 +.else + msr CPACR_EL1, x0 + msr ELR_EL1, x1 + msr SPSR_EL1, x2 +.endif + restoreregister + eret + +FIQInterruptHandler: + + saveregister + + bl FIQInterrupt + + restoreregister + + eret + +SErrorInterruptHandler: + + saveregister + + bl SErrorInterrupt + + restoreregister + + eret + + +.align 8 +/* Array to store floating point registers */ +FPUContext: .skip FPUContextSize + +/* Stores address for floating point context array */ +FPUContextBase: .skip 8 + +FPUStatus: .skip 1 + +.end diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/boot.S b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/boot.S similarity index 58% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/boot.S rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/boot.S index ed2d09843..760994948 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/boot.S +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/boot.S @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved. +* Copyright (C) 2014 - 2018 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -33,14 +33,40 @@ /** * @file boot.S * -* This file contains the initial startup code for the Cortex A53 processor -* It checks the current exception level and if it matches with selected -* exception level, then only it initializes the required system registers and -* executes the code further, otherwise it will loop busy loop around error. -* If the selected exception level is EL3, execution of the processor has to -* be in EL3. If the selected exception level is EL1 non-secure, execution of -* the processor can be EL2 or EL1. +* @addtogroup a53_64_boot_code Cortex A53 64bit Processor Boot Code +* @{ +*

boot.S

* +* The boot code performs minimum configuration which is required for an +* application. Cortex-A53 starts by checking current exception level. If the +* current exception level is EL3 and BSP is built for EL3, it will do +* initialization required for application execution at EL3. Below is a +* sequence illustrating what all configuration is performed before control +* reaches to main function for EL3 execution. +* +* 1. Program vector table base for exception handling +* 2. Set reset vector table base address +* 3. Program stack pointer for EL3 +* 4. Routing of interrupts to EL3 +* 5. Enable ECC protection +* 6. Program generic counter frequency +* 7. Invalidate instruction cache, data cache and TLBs +* 8. Configure MMU registers and program base address of translation table +* 9. Transfer control to _start which clears BSS sections and runs global +* constructor before jumping to main application +* +* If the current exception level is EL1 and BSP is also built for EL1_NONSECURE +* it will perform initialization required for application execution at EL1 +* non-secure. For all other combination, the execution will go into infinite +* loop. Below is a sequence illustrating what all configuration is performed +* before control reaches to main function for EL1 execution. +* +* 1. Program vector table base for exception handling +* 2. Program stack pointer for EL1 +* 3. Invalidate instruction cache, data cache and TLBs +* 4. Configure MMU registers and program base address of translation table +* 5. Transfer control to _start which clears BSS sections and runs global +* constructor before jumping to main application * * 
 * MODIFICATION HISTORY:
@@ -49,15 +75,25 @@
 * ----- ------- -------- ---------------------------------------------------
 * 5.00  pkp	05/21/14 Initial version
 * 6.00	pkp     07/25/16 Program the counter frequency
+* 6.02  pkp	01/22/17 Added support for EL1 non-secure
+* 6.02	pkp	01/24/17 Clearing status of FPUStatus variable to ensure it
+*			 holds correct value.
+* 6.3   mus 04/20/17 CPU Cache protection bit in the L2CTLR_EL1 will be in
+*                    set state on reset. So, setting that bit through boot
+*                    code is redundant, hence removed the code which sets
+*                    CPU cache protection bit.
+* 6.4   mus      08/11/17 Implemented ARM erratum 855873.It fixes
+*                         CR#982209.
+* 6.6   mus      01/19/18 Added isb after writing to the cpacr_el1/cptr_el3,
+*                         to ensure floating-point unit is disabled, before
+*                         any subsequent instruction.
 *
-* @note
-*
-* None.
 *
 ******************************************************************************/
 
 #include "xparameters.h"
 #include "bspconfig.h"
+#include "xil_errata.h"
 
 .globl MMUTableL0
 .globl MMUTableL1
@@ -139,6 +175,16 @@ EndlessLoop0:
 #endif
 OKToRun:
 
+	mrs	x0, currentEL
+	cmp	x0, #0xC
+	beq	InitEL3
+
+	cmp	x0, #0x4
+	beq	InitEL1
+
+	b 	error			// go to error if current exception level is neither EL3 nor EL1
+InitEL3:
+.if (EL3 == 1)
 	/*Set vector table base address*/
 	ldr	x1, =vector_base
 	msr	VBAR_EL3,x1
@@ -160,10 +206,24 @@ OKToRun:
 	ldr	 x2,=EL3_stack
 	mov	 sp,x2
 
-	/* Disable trapping of CPTR_EL3 accesses or use of Adv.SIMD/FPU*/
-	mov      x0, #0                 // Clear all trap bits
+	/* Enable Trapping of SIMD/FPU register for standalone BSP */
+	mov      x0, #0
+#ifndef FREERTOS_BSP
+	orr      x0, x0, #(0x1 << 10)
+#endif
 	msr      CPTR_EL3, x0
+	isb
 
+	/*
+	 * Clear FPUStatus variable to make sure that it contains current
+	 * status of FPU i.e. disabled. In case of a warm restart execution
+	 * when bss sections are not cleared, it may contain previously updated
+	 * value which does not hold true now.
+	 */
+#ifndef FREERTOS_BSP
+	 ldr x0,=FPUStatus
+	 str xzr, [x0]
+#endif
 	/* Configure SCR_EL3 */
 	mov      w1, #0              	//; Initial value of register is unknown
 	orr      w1, w1, #(1 << 11)  	//; Set ST bit (Secure EL1 can access CNTPS_TVAL_EL1, CNTPS_CTL_EL1 & CNTPS_CVAL_EL1)
@@ -173,12 +233,16 @@ OKToRun:
 	orr      w1, w1, #(1 << 1)   	//; Set IRQ bit (IRQs routed to EL3)
 	msr      SCR_EL3, x1
 
-	/*Enable ECC protection*/
-	mrs	x0, S3_1_C11_C0_2  	// register L2CTLR_EL1
-	orr	x0, x0, #(1<<22)
-	msr	S3_1_C11_C0_2, x0
 	/*configure cpu auxiliary control register EL1 */
 	ldr	x0,=0x80CA000 		// L1 Data prefetch control - 5, Enable device split throttle, 2 independent data prefetch streams
+#if CONFIG_ARM_ERRATA_855873
+        /*
+	 *  Set ENDCCASCI bit in CPUACTLR_EL1 register, to execute data
+	 *  cache clean operations as data cache clean and invalidate
+	 *
+	 */
+        orr     x0, x0, #(1 << 44)      //; Set ENDCCASCI bit
+#endif
 	msr	S3_1_C15_C2_0, x0 	//CPUACTLR_EL1
 
 	/* program the counter frequency */
@@ -238,8 +302,94 @@ OKToRun:
 	isb
 
 	b 	 _startup		//jump to start
+.else
+	b 	error			// present exception level and selected exception level mismatch
+.endif
+
+InitEL1:
+.if (EL1_NONSECURE == 1)
+	/*Set vector table base address*/
+	ldr	x1, =vector_base
+	msr	VBAR_EL1,x1
+
+	mrs	x0, CPACR_EL1
+	bic	x0, x0, #(0x3 << 0x20)
+	msr	CPACR_EL1, x0
+	isb
+
+	/*
+	 * Clear FPUStatus variable to make sure that it contains current
+	 * status of FPU i.e. disabled. In case of a warm restart execution
+	 * when bss sections are not cleared, it may contain previously updated
+	 * value which does not hold true now.
+	 */
+#ifndef FREERTOS_BSP
+	 ldr x0,=FPUStatus
+	 str xzr, [x0]
+#endif
+	/*Define stack pointer for current exception level*/
+	ldr	 x2,=EL1_stack
+	mov	 sp,x2
+
+	/* Disable MMU first */
+	mov	x1,#0x0
+	msr     SCTLR_EL1, x1
+	isb
+
+	TLBI    VMALLE1
+
+	ic      IALLU                  	//; Invalidate I cache to PoU
+	bl 	invalidate_dcaches
+	dsb	 sy
+	isb
+
+	ldr      x1, =L0Table 		//; Get address of level 0 for TTBR0_EL1
+	msr      TTBR0_EL1, x1		//; Set TTBR0_EL1
+
+	/**********************************************
+	* Set up memory attributes
+	* This equates to:
+	* 0 = b01000100 = Normal, Inner/Outer Non-Cacheable
+	* 1 = b11111111 = Normal, Inner/Outer WB/WA/RA
+	* 2 = b00000000 = Device-nGnRnE
+	* 3 = b00000100 = Device-nGnRE
+	* 4 = b10111011 = Normal, Inner/Outer WT/WA/RA
+	**********************************************/
+	ldr      x1, =0x000000BB0400FF44
+	msr      MAIR_EL1, x1
+
+        /**********************************************
+        * Set up TCR_EL1
+	* Physical Address Size PS =  010 -> 40bits 1TB
+	* Granual Size TG0 = 00 -> 4KB
+        * size offset of the memory region T0SZ = 24 -> (region size 2^(64-24) = 2^40)
+        ***************************************************/
+        ldr     x1,=0x285800518
+        msr     TCR_EL1, x1
+        isb
+	/* Enable SError Exception for asynchronous abort */
+	mrs 	x1,DAIF
+        bic	x1,x1,#(0x1<<8)
+        msr	DAIF,x1
+
+	//; Enable MMU
+	mov	x1,#0x0
+	orr     x1, x1, #(1 << 18)    // ; Set WFE non trapping
+	orr     x1, x1, #(1 << 17)    // ; Set WFI non trapping
+	orr     x1, x1, #(1 << 5)    // ; Set CP15 barrier enabled
+	orr     x1, x1, #(1 << 12)    // ; Set I bit
+	orr     x1, x1, #(1 << 2)    // ; Set C bit
+	orr     x1, x1, #(1 << 0)    // ; Set M bit
+	msr     SCTLR_EL1, x1
+	isb
+
+	bl 	 _startup		//jump to start
+.else
+	b 	error			// present exception level and selected exception level mismatch
+.endif
+
+error: 	b	error
 
-loop:	b	loop
 
 invalidate_dcaches:
 
@@ -290,4 +440,7 @@ invalidateCaches_next_level:
 invalidateCaches_end:
 	ret
 
-.end
\ No newline at end of file
+.end
+/**
+* @} End of "addtogroup a53_64_boot_code".
+*/
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/bspconfig.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/bspconfig.h
similarity index 84%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/bspconfig.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/bspconfig.h
index 8671e3fbe..aaf4af14c 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/bspconfig.h
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/bspconfig.h
@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights
@@ -37,4 +37,12 @@
 *
 *******************************************************************/
 
+#ifndef BSPCONFIG_H /* prevent circular inclusions */
+#define BSPCONFIG_H /* by using protection macros */
+
 #define MICROBLAZE_PVR_NONE
+#define EL3 1
+#define EL1_NONSECURE 0
+#define HYP_GUEST 0
+
+#endif /*end of __BSPCONFIG_H_*/
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/changelog.txt b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/changelog.txt
similarity index 71%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/changelog.txt
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/changelog.txt
index f663af134..64144403a 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/changelog.txt
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/changelog.txt
@@ -399,4 +399,141 @@
  *                     ::hsi::utils::handle_stdin and ::hsi::utils::handle_stdout are taken as a base for
  *                     these APIs and modifications are done on top of it to handle stdout/stdin
  *                     parameters for design which doesnt have UART.It fixes CR#953681
+ * 6.1 nsk   11/07/16  Added two new files xil_mem.c and xil_mem.h for xil_memcpy
+ * 6.2 pkp   12/14/16  Updated cortexa53/64bit/translation_table.S for upper ps DDR. The 0x800000000 -
+ *		       0xFFFFFFFFF range is marked normal memory for the DDR size defined in hdf
+ *		       and rest of the memory in that 32GB region is marked as reserved to avoid
+ *		       any speculative access
+ * 6.2 pkp   12/23/16  Added support for floating point operation to Cortex-A53 64bit mode. It modified
+ *		       asm_vectors.S to implement lazy floating point context saving i.e. floating point
+ *		       access is enabled if there is any floating point operation, it is disabled by
+ *		       default. Also FPU is initally disabled for IRQ and none of the floating point
+ *		       registers are saved during normal context saving. If IRQ handler does not require
+ *		       floating point operation, the floating point registers are untouched and no need
+ *		       for saving/restoring. If IRQ handler uses any floating point operation, then floating
+ *		       point registers are saved and FPU is enabled for IRQ handler. Then floating point
+ *		       registers are restored back after servicing IRQ during normal context restoring.
+ * 6.2 mus   01/01/17  Updated makefiles of R5 and a53 64 bit/32 bit processors to fix error in clean
+ *                     target.It fixes the CR#966900
+ * 6.2 pkp   01/22/17  Added support for EL1 non-secure execution and Hypervisor Baremetal for Cortex-A53
+ *		       64bit Mode. If Hypervisor_guest is selected as true in BSP settings, BSP will be built
+ *		       for EL1 Non-secure, else BSP will be built for EL3. By default hypervisor_guest is
+ *		       as false i.e. default bsp is EL3.
+ * 6.2 pkp   01/24/17  Updated cortexa53/64bit/boot.S to clear FPUStatus variable to make sure that it
+ *		       contains initial status of FPU i.e. disabled. In case of a warm restart execution
+ *		       when bss sections are not cleared, it may contain previously updated value which
+ *		       does not hold true once processor resumes. This fixes CR#966826.
+ * 6.2 asa   01/31/17  The existing Xil_DCacheDisable API first flushes the
+ *		       D caches and then disables it. The problem with that is,
+ *		       potentially there will be a small window after the cache
+ *		       flush operation and before the we disable D caches where
+ *		       we might have valid data in cache lines. In such a
+ *		       scenario disabling the D cache can lead to unknown behavior.
+ *		       The ideal solution to this is to use assembly code for
+ *		       the complete API and avoid any memory accesses. But with
+ *		       that we will end up having a huge amount on assembly code
+ *		       which is not maintainable. Changes are done to use a mix
+ *		       of assembly and C code. All local variables are put in
+ *		       registers. Also function calls are avoided in the API to
+ *		       avoid using stack memory.
+ * 6.2 mus   02/13/17 A53 CPU cache system can pre-fetch catch lines.So there are
+ *                    scenarios when an invalidated cache line can get pre fetched to cache.
+ *                    If that happens, the coherency between cache and memory is lost
+ *                    resulting in lost data. To avoid this kind of issue either
+ *                    user has to use dsb() or disable pre-fetching for L1 cache
+ *                    or else reduce maximum number of outstanding data prefetches allowed.
+ *                    Using dsb() while comparing data costing more performance compared to
+ *                    disabling pre-fetching/reducing maximum number of outstanding data
+ *                    prefetches for L1 Cache.The new api Xil_ConfigureL1Prefetch is added
+ *                    to disable pre-fetching/configure maximum number of outstanding data
+ *                    prefetches allowed in L1 cache system.This fixes CR#967864.
+ * 6.2 pkp   02/16/17 Added xil_smc.c file to provide a C wrapper for smc calling which can be
+ *		      used by cortex-A53 64bit EL1 Non-secure application.
+ * 6.2 kvn   03/03/17 Added support thumb mode
+ * 6.2 mus   03/13/17 Fixed MISRA C mandatory standard violations in ARM cortexr5 and cortexa53 BSP.
+ *                    It fixes CR#970543
+ * 6.2 asa   03/16/17 Fix for CR#970859. For Mcroblaze BSP, when we enable intrusive
+ *                    profiling we see a crash. That is because the the tcl uses invalid
+ *                    HSI command. This change fixes it.
+ * 6.2 mus   03/22/17 Updated standalone tcl to generate xparameter XPAR_FPD_IS_CACHE_COHERENT, if
+ *                    any FPD peripheral is configured to use CCI.It fixes CR#972638
+ * 6.3 mus   03/20/17 Updated cortex-r5 BSP, to add hard floating point support.
+ * 6.3 mus   04/17/17 Updated Cortex-a53 32 bit BSP boot code to fix bug in
+ *                    the HW coherency enablement. It fixes the CR#973287
+ * 6.3 mus   04/20/17 Updated Cortex-A53 64 bit BSP boot code, to remove redundant write to the
+ *                    L2CTLR_EL1 register. It fixes the CR#974698
+ * 6.4 mus   06/08/17 Updated arm/common/xil_exception.c to fix warnings in C level exception handlers
+ *                    of ARM 32 bit processor's.
+ * 6.4 mus   06/14/17 Updated cortexa53/64bit/gcc/asm_vectors.S to fix bug in  IRQInterruptHandler code
+ *                    snippet, which checks for the FPEN bit of CPACR_EL1 register.
+ * 6.4 ms    05/23/17 Added PSU_PMU macro in xplatform_info.c, xparameters.h to support
+ *                    XGetPSVersion_Info function for PMUFW.
+ *     ms    06/13/17 Added PSU_PMU macro in xplatform_info.c to support XGetPlatform_Info
+ *                    function for PMUFW.
+ * 6.4 mus   07/05/17 Updated Xil_In32BE function in xil_io.h to fix bug.It fixes CR#979740.
+ * 6.4 mus   07/25/17 Updated a53 32 bit boot code and vectors to support hard floating point
+ *                    operations.Now,VFP is being enabled in FPEXC register, through boot code
+ *                    and FPU registers are being saved/restored when irq/fiq vector is invoked.
+ * 6.4 adk   08/01/17 Updated standalone tcl to generate xparameter XPAR_PL_IS_CACHE_COHERENT,
+ * 		      if h/w design configured with HPC port.
+ * 6.4 mus   08/10/17 Updated a53 64 bit translation table to mark  memory as a outer shareable for
+ *                    EL1 NS execution. This change has been done to support CCI enabled IP's.
+ * 6.4 mus   08/11/17 Updated a53 64 bit boot code to implement ARM erratum 855873.This fixes
+ *                    CR#982209.
+ * 6.4 asa   08/16/17 Made several changes in the R5 MPU handling logic. Added new APIs to
+ *                    make RPU MPU handling user-friendly. This also fixes the CR-981028.
+ * 6.4 mus   08/17/17 Updated XGet_Zynq_UltraMp_Platform_info and XGetPSVersion_Info APIs to read
+ *                    version register through SMC call, over EL1 NS mode. This change has been done to
+ *                    support these APIs over EL1 NS mode.
+ * 6.5 mus   10/20/17 Updated standalone.tcl to fix bug in mb_can_handle_exceptions_in_delay_slots proc,
+ *                    it fixes CR#987464.
+ * 6.6 mus   12/07/17 Updated cortexa9/xil_errata.h and cortexa9/xil_cache.c to remove Errata 753970.
+ *                    It fixes CR#989132.
+ *     srm   10/18/17 Updated all the sleep routines in a9,a53,R5,microblaze. Now the sleep routines
+ *		      will use the timer specified by the user to provide delay. A9 and A53 can use
+ *                    Global timer or TTC. R5 can use TTC or the machine cycles. Microblaze can use
+ *                    machine cycles or Axi timer. Updated standalone.tcl and standalone.mld files
+ *		      to support the sleep configuration Added new API's for the Axi timer in
+ *		      microblaze and TTC in ARM. Added two new files, xil_sleeptimer.c and
+ *		      xil_sleeptimer.h in ARM for the common sleep routines and 1 new file,
+ *		      xil_sleepcommon.c in Standalone-common for sleep/usleep API's.
+ * 6.6 hk    12/15/17 Export platform macros to bspconfig.h based on the processor.
+ * 6.6 asa   1/16/18  Ensure C stack information for A9 are flushed out from L1 D cache
+ *                    or L2 cache only when the respective caches are enabled. This fixes CR-922023.
+ * 6.6 mus   01/19/18 Updated asm_vectors.S and boot.S in Cortexa53 64 bit BSP, to add isb
+ *                    after writing to cpacr_el1/cptr_el3 registers. It would ensure
+ *                    disabling/enabling of floating-point unit, before any subsequent
+ *                    instruction.
+ * 6.6 mus   01/30/18 Updated hypervisor enabled Cortexa53 64 bit BSP, to add xen PV console
+ *                    support. Now, xil_printf would use PV console instead of UART in case of
+ *                    hypervisor enabled BSP.
+ * 6.6 mus   02/02/18 Updated get_connected_if proc in standalone tcl to detect the HPC port 
+ *                    configured with smart interconnect.It fixes CR#990318.
+ * 6.6 srm   02/10/18 Updated csu_wdt interrupt to the correct value. Fixes CR#992229
+ * 6.6 asa   02/12/18 Fix for heap handling for ARM platforms. CR#993932.
+ * 6.6 mus   02/19/18 Updated standalone.tcl to fix bug in handle_profile_opbtimer proc,
+ *                    CR#995014.
+ * 6.6 mus   02/23/18 Presently Cortex R5 BSP boot code is disabling the debug logic in
+*		      non-JTAG boot mode, when processor is in lockstep configuration.
+*		      This behavior is restricting application debugging in non-JTAG boot
+*		      mode.  To get rid of this restriction, added new mld parameter 
+*		      "lockstep_mode_debug", to enable/disable debug logic from BSP 
+*		      settings. Now, debug logic can be enabled through BSP settings, 
+*		      by modifying value of parameter "lockstep_mode_debug" as "true".
+*		      It fixes CR#993896.
+ * 6.6.mus   02/27/18  Updated Xil_DCacheInvalidateRange and
+*		       Xil_ICacheInvalidateRange APIs in Cortexa53 64 bit BSP, to fix  bug
+*		       in handling upper DDR addresses.It fixes CR#995581.
+* 6.6 mus    03/12/18  Updated makefile of Cortexa53 32bit BSP to add includes_ps directory
+*		       in the list of include paths. This change allows applications/BSP
+*		       files to include .h files in include_ps directory.
+* 6.6 mus    03/16/18  By default CPUACTLR_EL1 is accessible only from EL3, it
+*		       results into abort if accessed from EL1 non secure privilege
+*		       level. Updated Xil_ConfigureL1Prefetch function in Cortexa53 64 bit BSP
+*		       to avoid CPUACTLR_EL1 access from privile levels other than EL3.
+* 6.6 mus    03/16/18  Updated hypervisor enabled BSP to use PV console, based on the
+*		       XEN_USE_PV_CONSOLE flag. By deafault hypervisor enabled BSP would
+*		       use UART console, PV console can be enabled by appending
+		       "-DXEN_USE_PV_CONSOLE" to the BSP extra compiler flags.
+ *
  *****************************************************************************************/
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/close.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/close.c
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/close.c
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/close.c
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/config.make b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/config.make
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/config.make
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/config.make
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/errno.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/errno.c
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/errno.c
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/errno.c
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/fcntl.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/fcntl.c
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/fcntl.c
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/fcntl.c
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/fstat.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/fstat.c
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/fstat.c
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/fstat.c
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/getpid.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/getpid.c
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/getpid.c
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/getpid.c
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/inbyte.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/inbyte.c
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/inbyte.c
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/inbyte.c
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/includes_ps/xddr_xmpu0_cfg.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/includes_ps/xddr_xmpu0_cfg.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/includes_ps/xddr_xmpu0_cfg.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/includes_ps/xddr_xmpu0_cfg.h
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/includes_ps/xddr_xmpu1_cfg.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/includes_ps/xddr_xmpu1_cfg.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/includes_ps/xddr_xmpu1_cfg.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/includes_ps/xddr_xmpu1_cfg.h
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/includes_ps/xddr_xmpu2_cfg.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/includes_ps/xddr_xmpu2_cfg.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/includes_ps/xddr_xmpu2_cfg.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/includes_ps/xddr_xmpu2_cfg.h
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/includes_ps/xddr_xmpu3_cfg.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/includes_ps/xddr_xmpu3_cfg.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/includes_ps/xddr_xmpu3_cfg.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/includes_ps/xddr_xmpu3_cfg.h
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/includes_ps/xddr_xmpu4_cfg.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/includes_ps/xddr_xmpu4_cfg.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/includes_ps/xddr_xmpu4_cfg.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/includes_ps/xddr_xmpu4_cfg.h
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/includes_ps/xddr_xmpu5_cfg.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/includes_ps/xddr_xmpu5_cfg.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/includes_ps/xddr_xmpu5_cfg.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/includes_ps/xddr_xmpu5_cfg.h
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/includes_ps/xfpd_slcr.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/includes_ps/xfpd_slcr.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/includes_ps/xfpd_slcr.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/includes_ps/xfpd_slcr.h
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/includes_ps/xfpd_slcr_secure.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/includes_ps/xfpd_slcr_secure.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/includes_ps/xfpd_slcr_secure.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/includes_ps/xfpd_slcr_secure.h
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/includes_ps/xfpd_xmpu_cfg.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/includes_ps/xfpd_xmpu_cfg.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/includes_ps/xfpd_xmpu_cfg.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/includes_ps/xfpd_xmpu_cfg.h
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/includes_ps/xfpd_xmpu_sink.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/includes_ps/xfpd_xmpu_sink.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/includes_ps/xfpd_xmpu_sink.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/includes_ps/xfpd_xmpu_sink.h
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/includes_ps/xiou_secure_slcr.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/includes_ps/xiou_secure_slcr.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/includes_ps/xiou_secure_slcr.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/includes_ps/xiou_secure_slcr.h
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/includes_ps/xiou_slcr.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/includes_ps/xiou_slcr.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/includes_ps/xiou_slcr.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/includes_ps/xiou_slcr.h
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/includes_ps/xlpd_slcr.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/includes_ps/xlpd_slcr.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/includes_ps/xlpd_slcr.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/includes_ps/xlpd_slcr.h
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/includes_ps/xlpd_slcr_secure.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/includes_ps/xlpd_slcr_secure.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/includes_ps/xlpd_slcr_secure.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/includes_ps/xlpd_slcr_secure.h
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/includes_ps/xlpd_xppu.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/includes_ps/xlpd_xppu.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/includes_ps/xlpd_xppu.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/includes_ps/xlpd_xppu.h
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/includes_ps/xlpd_xppu_sink.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/includes_ps/xlpd_xppu_sink.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/includes_ps/xlpd_xppu_sink.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/includes_ps/xlpd_xppu_sink.h
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/includes_ps/xocm_xmpu_cfg.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/includes_ps/xocm_xmpu_cfg.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/includes_ps/xocm_xmpu_cfg.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/includes_ps/xocm_xmpu_cfg.h
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/initialise_monitor_handles.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/initialise_monitor_handles.c
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/initialise_monitor_handles.c
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/initialise_monitor_handles.c
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/isatty.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/isatty.c
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/isatty.c
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/isatty.c
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/kill.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/kill.c
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/kill.c
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/kill.c
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/lseek.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/lseek.c
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/lseek.c
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/lseek.c
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/open.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/open.c
similarity index 99%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/open.c
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/open.c
index 4b51839fd..85e9ce402 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/open.c
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/open.c
@@ -44,7 +44,7 @@ extern "C" {
  */
 __attribute__((weak)) s32 open(char8 *buf, s32 flags, s32 mode)
 {
-  (void *)buf;
+  (void)buf;
   (void)flags;
   (void)mode;
   errno = EIO;
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/outbyte.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/outbyte.c
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/outbyte.c
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/outbyte.c
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/print.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/print.c
similarity index 90%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/print.c
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/print.c
index 74d70ee4a..da7e768d0 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/print.c
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/print.c
@@ -21,6 +21,9 @@
 
 void print(const char8 *ptr)
 {
+#if HYP_GUEST && EL1_NONSECURE && XEN_USE_PV_CONSOLE
+	XPVXenConsole_Write(ptr);
+#else
 #ifdef STDOUT_BASEADDRESS
   while (*ptr != (char8)0) {
     outbyte (*ptr);
@@ -29,4 +32,5 @@ void print(const char8 *ptr)
 #else
 (void)ptr;
 #endif
+#endif
 }
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/putnum.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/putnum.c
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/putnum.c
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/putnum.c
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/read.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/read.c
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/read.c
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/read.c
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/sbrk.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/sbrk.c
similarity index 94%
rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/sbrk.c
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/sbrk.c
index 64d5156af..87a753d49 100644
--- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/sbrk.c
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/sbrk.c
@@ -51,12 +51,8 @@ __attribute__((weak)) char8 *sbrk (s32 nbytes)
   static char8 *heap_ptr = HeapBase;
 
   base = heap_ptr;
-  if(heap_ptr != NULL) {
+	if((heap_ptr != NULL) && (heap_ptr + nbytes <= (char8 *)&HeapLimit + 1)) {
 	heap_ptr += nbytes;
-  }
-
-/*  if (heap_ptr <= ((char8 *)&_heap_end + 1)) */
-  if (heap_ptr <= ((char8 *)&HeapLimit + 1)) {
     return base;
   }	else {
     errno = ENOMEM;
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/sleep.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/sleep.c
similarity index 79%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/sleep.c
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/sleep.c
index c1df66bcf..c3c65dc43 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/sleep.c
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/sleep.c
@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2014 - 2017 Xilinx, Inc. All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
@@ -50,6 +50,10 @@
 *						  read counter value directly from register instead
 *						  of calling XTime_GetTime for optimization
 * 6.0   asa      08/15/16 Updated the sleep/usleep signature. Fix for CR#956899.
+* 6.6	srm      10/18/17 Updated sleep routines to support user configurable
+*                         implementation. Now sleep routines will use Timer
+*                         specified by the user (i.e. Global timer/TTC timer)
+*       srm      01/11/18 Fixed the compilation warning.
 *
* ******************************************************************************/ @@ -59,9 +63,20 @@ #include "xtime_l.h" #include "xparameters.h" +#if defined (SLEEP_TIMER_BASEADDR) +#include "xil_sleeptimer.h" +#endif +/**************************** Constant Definitions ************************/ + +#if defined (SLEEP_TIMER_BASEADDR) +#define COUNTS_PER_USECOND (COUNTS_PER_SECOND / 1000000 ) +#else /* Global Timer is always clocked at half of the CPU frequency */ #define COUNTS_PER_USECOND (COUNTS_PER_SECOND / 1000000 ) +#endif +/************************************************************************/ +#if !defined (SLEEP_TIMER_BASEADDR) static void sleep_common(u32 n, u32 count) { XTime tEnd, tCur; @@ -74,7 +89,7 @@ static void sleep_common(u32 n, u32 count) tCur = mfcp(CNTPCT_EL0); } while (tCur < tEnd); } - +#endif /*****************************************************************************/ /** * @@ -88,9 +103,13 @@ static void sleep_common(u32 n, u32 count) * @note None. * ****************************************************************************/ -int usleep(unsigned long useconds) +int usleep_A53(unsigned long useconds) { +#if defined (SLEEP_TIMER_BASEADDR) + Xil_SleepTTCCommon(useconds, COUNTS_PER_USECOND); +#else sleep_common((u32)useconds, COUNTS_PER_USECOND); +#endif return 0; } @@ -107,9 +126,13 @@ int usleep(unsigned long useconds) * @note None. * ****************************************************************************/ -unsigned sleep(unsigned int seconds) +unsigned sleep_A53(unsigned int seconds) { +#if defined (SLEEP_TIMER_BASEADDR) + Xil_SleepTTCCommon(seconds, COUNTS_PER_SECOND); +#else sleep_common(seconds, COUNTS_PER_SECOND); +#endif return 0; } diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/sleep.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/sleep.h new file mode 100644 index 000000000..f53b2d8c8 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/sleep.h @@ -0,0 +1,119 @@ +/****************************************************************************** +* +* Copyright (C) 2014 - 2017 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +/*****************************************************************************/ +/** +* @file sleep.h +* +* This header file contains ARM Cortex A53,A9,R5,Microblaze specific sleep +* related APIs. +* +* 
+* MODIFICATION HISTORY :
+*
+* Ver   Who  Date	 Changes
+* ----- ---- -------- -------------------------------------------------------
+* 6.6   srm  11/02/17 Added processor specific sleep rountines
+*								 function prototypes.
+*
+*
+* +******************************************************************************/ + +#ifndef SLEEP_H +#define SLEEP_H + +#include "xil_types.h" +#include "xil_io.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/*****************************************************************************/ +/** +* +* This macro polls an address periodically until a condition is met or till the +* timeout occurs. +* The minimum timeout for calling this macro is 100us. If the timeout is less +* than 100us, it still waits for 100us. Also the unit for the timeout is 100us. +* If the timeout is not a multiple of 100us, it waits for a timeout of +* the next usec value which is a multiple of 100us. +* +* @param IO_func - accessor function to read the register contents. +* Depends on the register width. +* @param ADDR - Address to be polled +* @param VALUE - variable to read the value +* @param COND - Condition to checked (usually involves VALUE) +* @param TIMEOUT_US - timeout in micro seconds +* +* @return 0 - when the condition is met +* -1 - when the condition is not met till the timeout period +* +* @note none +* +*****************************************************************************/ +#define Xil_poll_timeout(IO_func, ADDR, VALUE, COND, TIMEOUT_US) \ + ( { \ + u64 timeout = TIMEOUT_US/100; \ + if(TIMEOUT_US%100!=0) \ + timeout++; \ + for(;;) { \ + VALUE = IO_func(ADDR); \ + if(COND) \ + break; \ + else { \ + usleep(100); \ + timeout--; \ + if(timeout==0) \ + break; \ + } \ + } \ + (timeout>0) ? 0 : -1; \ + } ) + +void usleep(unsigned long useconds); +void sleep(unsigned int seconds); +int usleep_R5(unsigned long useconds); +unsigned sleep_R5(unsigned int seconds); +int usleep_MB(unsigned long useconds); +unsigned sleep_MB(unsigned int seconds); +int usleep_A53(unsigned long useconds); +unsigned sleep_A53(unsigned int seconds); +int usleep_A9(unsigned long useconds); +unsigned sleep_A9(unsigned int seconds); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/translation_table.S b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/translation_table.S similarity index 54% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/translation_table.S rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/translation_table.S index 49b3dcf35..b72abe07c 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/translation_table.S +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/translation_table.S @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved. +* Copyright (C) 2014 - 2017 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -33,8 +33,43 @@ /** * @file translation_table.s * -* This file contains the initialization for the MMU table in RAM -* needed by the Cortex A53 processor +* @addtogroup a53_64_boot_code +* @{ +*

translation_table.S

+* translation_table.S contains a static page table required by MMU for +* cortex-A53. This translation table is flat mapped (input address = output +* address) with default memory attributes defined for zynq ultrascale+ +* architecture. It utilizes translation granual size of 4KB with 2MB section +* size for initial 4GB memory and 1GB section size for memory after 4GB. +* The overview of translation table memory attributes is described below. +* +*| | Memory Range | Definition in Translation Table | +*|-----------------------|-----------------------------|-----------------------------------| +*| DDR | 0x0000000000 - 0x007FFFFFFF | Normal write-back Cacheable | +*| PL | 0x0080000000 - 0x00BFFFFFFF | Strongly Ordered | +*| QSPI, lower PCIe | 0x00C0000000 - 0x00EFFFFFFF | Strongly Ordere | +*| Reserved | 0x00F0000000 - 0x00F7FFFFFF | Unassigned | +*| STM Coresight | 0x00F8000000 - 0x00F8FFFFFF | Strongly Ordered | +*| GIC | 0x00F9000000 - 0x00F91FFFFF | Strongly Ordered | +*| Reserved | 0x00F9200000 - 0x00FCFFFFFF | Unassigned | +*| FPS, LPS slaves | 0x00FD000000 - 0x00FFBFFFFF | Strongly Ordered | +*| CSU, PMU | 0x00FFC00000 - 0x00FFDFFFFF | Strongly Ordered | +*| TCM, OCM | 0x00FFE00000 - 0x00FFFFFFFF | Normal inner write-back cacheable | +*| Reserved | 0x0100000000 - 0x03FFFFFFFF | Unassigned | +*| PL, PCIe | 0x0400000000 - 0x07FFFFFFFF | Strongly Ordered | +*| DDR | 0x0800000000 - 0x0FFFFFFFFF | Normal inner write-back cacheable | +*| PL, PCIe | 0x1000000000 - 0xBFFFFFFFFF | Strongly Ordered | +*| Reserved | 0xC000000000 - 0xFFFFFFFFFF | Unassigned | +* +* @note +* +* For DDR region 0x0000000000 - 0x007FFFFFFF, a system where DDR is less than +* 2GB, region after DDR and before PL is marked as undefined/reserved in +* translation table. Region 0xF9100000 - 0xF91FFFFF is reserved memory in +* 0x00F9000000 - 0x00F91FFFFF range, but it is marked as strongly ordered +* because minimum section size in translation table section is 2MB. Region +* 0x00FFC00000 - 0x00FFDFFFFF contains CSU and PMU memory which are marked as +* Device since it is less than 1MB and falls in a region with device memory. * * 
 * MODIFICATION HISTORY:
@@ -44,20 +79,27 @@
 * 5.00  pkp  05/21/14 Initial version
 * 5.04	pkp  12/18/15 Updated the address map according to proper address map
 * 6.0   mus  07/20/16 Added warning for ddrless HW design CR-954977
+* 6.2	pkp  12/14/16 DDR memory in 0x800000000 - 0xFFFFFFFFF range is marked
+*		      as normal writeback for the size defined in hdf and rest
+*		      of the memory in that 32GB range is marked as reserved.
+* 6.4   mus  08/10/17 Marked memory as a outer shareable for EL1 NS execution,
+*                     to support CCI enabled IP's.
 *
-* @note
-*
-* None.
 *
 ******************************************************************************/
 #include "xparameters.h"
+#include "bspconfig.h"
 
 	.globl  MMUTableL0
 	.globl  MMUTableL1
 	.globl  MMUTableL2
 
 	.set reserved,	0x0 					/* Fault*/
+	#if EL1_NONSECURE
+	.set Memory,	0x405 | (2 << 8) | (0x0)		/* normal writeback write allocate outer shared read write */
+	#else
 	.set Memory,	0x405 | (3 << 8) | (0x0)		/* normal writeback write allocate inner shared read write */
+	#endif
 	.set Device,	0x409 | (1 << 53)| (1 << 54) |(0x0)	/* strongly ordered read write non executable*/
 	.section .mmu_tbl0,"a"
 
@@ -91,9 +133,32 @@ MMUTableL1:
 .set SECT, SECT + 0x40000000
 .endr
 
-.rept	0x20			/* 0x0008_0000_0000 - 0x000F_FFFF_FFFF */
-.8byte	SECT + Memory		/* 32GB DDR */
-.set SECT, SECT + 0x40000000
+
+#ifdef XPAR_PSU_DDR_1_S_AXI_BASEADDR
+.set DDR_1_START, XPAR_PSU_DDR_1_S_AXI_BASEADDR
+.set DDR_1_END, XPAR_PSU_DDR_1_S_AXI_HIGHADDR
+.set DDR_1_SIZE, (DDR_1_END - DDR_1_START)+1
+.if DDR_1_SIZE > 0x800000000
+/* If DDR size is larger than 32GB, truncate to 32GB */
+.set DDR_1_REG, 0x20
+.else
+.set DDR_1_REG, DDR_1_SIZE/0x40000000
+.endif
+#else
+.set DDR_1_REG, 0
+#warning "There's no DDR_1 in the HW design. MMU translation table marks 32 GB DDR address space as undefined"
+#endif
+
+.set UNDEF_1_REG, 0x20 - DDR_1_REG
+
+.rept	DDR_1_REG			/* DDR based on size in hdf*/
+.8byte	SECT + Memory
+.set	SECT, SECT+0x40000000
+.endr
+
+.rept	UNDEF_1_REG		/* reserved for region where ddr is absent */
+.8byte	SECT + reserved
+.set	SECT, SECT+0x40000000
 .endr
 
 .rept	0x1C0			/* 0x0010_0000_0000 - 0x007F_FFFF_FFFF */
@@ -121,28 +186,28 @@ MMUTableL2:
 .set SECT, 0
 
 #ifdef XPAR_PSU_DDR_0_S_AXI_BASEADDR
-.set DDR_START, XPAR_PSU_DDR_0_S_AXI_BASEADDR
-.set DDR_END, XPAR_PSU_DDR_0_S_AXI_HIGHADDR
-.set DDR_SIZE, (DDR_END - DDR_START)+1
-.if DDR_SIZE > 0x80000000
+.set DDR_0_START, XPAR_PSU_DDR_0_S_AXI_BASEADDR
+.set DDR_0_END, XPAR_PSU_DDR_0_S_AXI_HIGHADDR
+.set DDR_0_SIZE, (DDR_0_END - DDR_0_START)+1
+.if DDR_0_SIZE > 0x80000000
 /* If DDR size is larger than 2GB, truncate to 2GB */
-.set DDR_REG, 0x400
+.set DDR_0_REG, 0x400
 .else
-.set DDR_REG, DDR_SIZE/0x200000
+.set DDR_0_REG, DDR_0_SIZE/0x200000
 .endif
 #else
-.set DDR_REG, 0
-#warning "There's no DDR in the HW design. MMU translation table marks 2 GB DDR address space as undefined"
+.set DDR_0_REG, 0
+#warning "There's no DDR_0 in the HW design. MMU translation table marks 2 GB DDR address space as undefined"
 #endif
 
-.set UNDEF_REG, 0x400 - DDR_REG
+.set UNDEF_0_REG, 0x400 - DDR_0_REG
 
-.rept	DDR_REG			/* DDR based on size in hdf*/
+.rept	DDR_0_REG			/* DDR based on size in hdf*/
 .8byte	SECT + Memory
 .set	SECT, SECT+0x200000
 .endr
 
-.rept	UNDEF_REG		/* reserved for region where ddr is absent */
+.rept	UNDEF_0_REG		/* reserved for region where ddr is absent */
 .8byte	SECT + reserved
 .set	SECT, SECT+0x200000
 .endr
@@ -203,3 +268,6 @@ MMUTableL2:
 .8byte  SECT + Memory		/*2MB OCM/TCM*/
 
 .end
+/**
+* @} End of "addtogroup a53_64_boot_code".
+*/
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/uart.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/uart.c
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/uart.c
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/uart.c
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/unlink.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/unlink.c
similarity index 99%
rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/unlink.c
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/unlink.c
index 84e44a47c..d0cc6807b 100644
--- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/unlink.c
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/unlink.c
@@ -44,7 +44,7 @@ extern "C" {
  */
 __attribute__((weak)) sint32 unlink(char8 *path)
 {
-  (void *)path;
+  (void) path;
   errno = EIO;
   return (-1);
 }
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/vectors.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/vectors.c
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/vectors.c
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/vectors.c
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/vectors.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/vectors.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/vectors.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/vectors.h
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/write.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/write.c
similarity index 93%
rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/write.c
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/write.c
index aaa879e73..9389f610a 100644
--- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/write.c
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/write.c
@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2009 - 2018 Xilinx, Inc.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
@@ -82,6 +82,14 @@ write (sint32 fd, char8* buf, sint32 nbytes)
 __attribute__((weak)) sint32
 _write (sint32 fd, char8* buf, sint32 nbytes)
 {
+#if HYP_GUEST && EL1_NONSECURE && XEN_USE_PV_CONSOLE
+	sint32 length;
+
+	(void)fd;
+	(void)nbytes;
+	length = XPVXenConsole_Write(buf);
+	return length;
+#else
 #ifdef STDOUT_BASEADDRESS
   s32 i;
   char8* LocalBuf = buf;
@@ -108,5 +116,6 @@ _write (sint32 fd, char8* buf, sint32 nbytes)
   (void)nbytes;
   return 0;
 #endif
+#endif
 }
 #endif
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xbasic_types.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xbasic_types.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xbasic_types.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xbasic_types.h
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xdebug.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xdebug.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xdebug.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xdebug.h
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xenv.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xenv.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xenv.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xenv.h
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xenv_standalone.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xenv_standalone.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xenv_standalone.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xenv_standalone.h
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil-crt0.S b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil-crt0.S
similarity index 83%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil-crt0.S
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil-crt0.S
index 38ca6511c..7ac77b650 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil-crt0.S
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil-crt0.S
@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2014 - 2017 Xilinx, Inc. All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
@@ -42,6 +42,12 @@
 * 5.04  pkp  12/18/15 Initialized global constructor for C++ applications
 * 5.04	pkp  01/05/16 Set the reset vector register RVBAR equivalent to
 *		      vector table base address
+* 6.02  pkp  01/22/17 Added support for EL1 non-secure
+* 6.6   srm  10/18/17 Added timer configuration using XTime_StartTTCTimer API.
+*		      Now the TTC instance as specified by the user will be
+*	              started.
+* 6.6   mus  01/29/18 Initialized the xen PV console for Cortexa53 64 bit
+*                     EL1 NS BSP.
 *
* * @note @@ -49,7 +55,8 @@ * None. * ******************************************************************************/ - +#include "xparameters.h" +#include "bspconfig.h" .file "xil-crt0.S" .section ".got2","aw" .align 2 @@ -74,7 +81,7 @@ _startup: mov x0, #0 - +.if (EL3 == 1) /* Check whether the clearing of bss sections shall be skipped */ ldr x10, =APU_PWRCTL /* Load PWRCTRL address */ ldr w11, [x10] /* Read PWRCTRL register */ @@ -84,7 +91,7 @@ _startup: lsl w2, w1, w2 /* Shift CPU ID to get one-hot ID */ ands w11, w11, w2 /* Get PWRCTRL bit for this core */ bne .Lenclbss /* Skip BSS and SBSS clearing */ - +.endif /* clear sbss */ ldr x1,.Lsbss_start /* calculate beginning of the SBSS */ ldr x2,.Lsbss_end /* calculate end of the SBSS */ @@ -110,6 +117,15 @@ _startup: /* run global constructors */ bl __libc_init_array + /* Reset and start Triple Timer Counter */ + #if defined (SLEEP_TIMER_BASEADDR) + bl XTime_StartTTCTimer + #endif + + .if (EL1_NONSECURE == 1 && HYP_GUEST == 1 && \ + XEN_USE_PV_CONSOLE == 1) + bl XPVXenConsole_Init + .endif /* make sure argc and argv are valid */ mov x0, #0 mov x1, #0 @@ -125,4 +141,4 @@ _startup: b .Lexit .Lstart: - .size _startup,.Lstart-_startup \ No newline at end of file + .size _startup,.Lstart-_startup diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_assert.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_assert.c similarity index 83% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_assert.c rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_assert.c index 3087fe80f..59b3c1c98 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_assert.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_assert.c @@ -82,12 +82,13 @@ static Xil_AssertCallback Xil_AssertCallbackRoutine = NULL; /*****************************************************************************/ /** * -* Implement assert. Currently, it calls a user-defined callback function -* if one has been set. Then, it potentially enters an infinite loop depending -* on the value of the Xil_AssertWait variable. +* @brief Implement assert. Currently, it calls a user-defined callback +* function if one has been set. Then, it potentially enters an +* infinite loop depending on the value of the Xil_AssertWait +* variable. * -* @param file is the name of the filename of the source -* @param line is the linenumber within File +* @param file: filename of the source +* @param line: linenumber within File * * @return None. * @@ -111,10 +112,10 @@ void Xil_Assert(const char8 *File, s32 Line) /*****************************************************************************/ /** * -* Set up a callback function to be invoked when an assert occurs. If there -* was already a callback installed, then it is replaced. +* @brief Set up a callback function to be invoked when an assert occurs. +* If a callback is already installed, then it will be replaced. * -* @param routine is the callback to be invoked when an assert is taken +* @param routine: callback to be invoked when an assert is taken * * @return None. * @@ -129,11 +130,11 @@ void Xil_AssertSetCallback(Xil_AssertCallback Routine) /*****************************************************************************/ /** * -* Null handler function. This follows the XInterruptHandler signature for -* interrupt handlers. It can be used to assign a null handler (a stub) to an -* interrupt controller vector table. +* @brief Null handler function. This follows the XInterruptHandler +* signature for interrupt handlers. It can be used to assign a null +* handler (a stub) to an interrupt controller vector table. * -* @param NullParameter is an arbitrary void pointer and not used. +* @param NullParameter: arbitrary void pointer and not used. * * @return None. * @@ -142,5 +143,5 @@ void Xil_AssertSetCallback(Xil_AssertCallback Routine) ******************************************************************************/ void XNullHandler(void *NullParameter) { - (void *) NullParameter; + (void) NullParameter; } diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_assert.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_assert.h similarity index 77% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_assert.h rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_assert.h index 1e3c17b50..add4124e2 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_assert.h +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_assert.h @@ -34,8 +34,15 @@ * * @file xil_assert.h * -* This file contains assert related functions. +* @addtogroup common_assert_apis Assert APIs and Macros * +* The xil_assert.h file contains assert related functions and macros. +* Assert APIs/Macros specifies that a application program satisfies certain +* conditions at particular points in its execution. These function can be +* used by application programs to ensure that, application code is satisfying +* certain conditions. +* +* @{ * 
 * MODIFICATION HISTORY:
 *
@@ -83,18 +90,17 @@ typedef void (*Xil_AssertCallback) (const char8 *File, s32 Line);
 
 /*****************************************************************************/
 /**
-* This assert macro is to be used for functions that do not return anything
-* (void). This in conjunction with the Xil_AssertWait boolean can be used to
-* accomodate tests so that asserts which fail allow execution to continue.
+* @brief    This assert macro is to be used for void functions. This in
+*           conjunction with the Xil_AssertWait boolean can be used to
+*           accomodate tests so that asserts which fail allow execution to
+*           continue.
 *
-* @param    Expression is the expression to evaluate. If it evaluates to
+* @param    Expression: expression to be evaluated. If it evaluates to
 *           false, the assert occurs.
 *
 * @return   Returns void unless the Xil_AssertWait variable is true, in which
 *           case no return is made and an infinite loop is entered.
 *
-* @note     None.
-*
 ******************************************************************************/
 #define Xil_AssertVoid(Expression)                \
 {                                                  \
@@ -109,17 +115,16 @@ typedef void (*Xil_AssertCallback) (const char8 *File, s32 Line);
 
 /*****************************************************************************/
 /**
-* This assert macro is to be used for functions that do return a value. This in
-* conjunction with the Xil_AssertWait boolean can be used to accomodate tests
-* so that asserts which fail allow execution to continue.
+* @brief    This assert macro is to be used for functions that do return a
+*           value. This in conjunction with the Xil_AssertWait boolean can be
+*           used to accomodate tests so that asserts which fail allow execution
+*           to continue.
 *
-* @param    Expression is the expression to evaluate. If it evaluates to false,
+* @param    Expression: expression to be evaluated. If it evaluates to false,
 *           the assert occurs.
 *
 * @return   Returns 0 unless the Xil_AssertWait variable is true, in which
-* 	    case no return is made and an infinite loop is entered.
-*
-* @note     None.
+* 	        case no return is made and an infinite loop is entered.
 *
 ******************************************************************************/
 #define Xil_AssertNonvoid(Expression)             \
@@ -135,14 +140,11 @@ typedef void (*Xil_AssertCallback) (const char8 *File, s32 Line);
 
 /*****************************************************************************/
 /**
-* Always assert. This assert macro is to be used for functions that do not
-* return anything (void). Use for instances where an assert should always
-* occur.
+* @brief     Always assert. This assert macro is to be used for void functions.
+*            Use for instances where an assert should always occur.
 *
-* @return Returns void unless the Xil_AssertWait variable is true, in which
-*	  case no return is made and an infinite loop is entered.
-*
-* @note   None.
+* @return    Returns void unless the Xil_AssertWait variable is true, in which
+*	         case no return is made and an infinite loop is entered.
 *
 ******************************************************************************/
 #define Xil_AssertVoidAlways()                   \
@@ -154,13 +156,12 @@ typedef void (*Xil_AssertCallback) (const char8 *File, s32 Line);
 
 /*****************************************************************************/
 /**
-* Always assert. This assert macro is to be used for functions that do return
-* a value. Use for instances where an assert should always occur.
+* @brief   Always assert. This assert macro is to be used for functions that
+*          do return a value. Use for instances where an assert should always
+*          occur.
 *
 * @return Returns void unless the Xil_AssertWait variable is true, in which
-*	  case no return is made and an infinite loop is entered.
-*
-* @note   None.
+*	      case no return is made and an infinite loop is entered.
 *
 ******************************************************************************/
 #define Xil_AssertNonvoidAlways()                \
@@ -189,3 +190,6 @@ void Xil_AssertSetCallback(Xil_AssertCallback Routine);
 #endif
 
 #endif	/* end of protection macro */
+/**
+* @} End of "addtogroup common_assert_apis".
+*/
\ No newline at end of file
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_cache.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_cache.c
similarity index 61%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_cache.c
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_cache.c
index 8a1f82881..312b7b096 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_cache.c
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_cache.c
@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2014 - 2017 Xilinx, Inc. All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
@@ -34,18 +34,44 @@
 *
 * @file xil_cache.c
 *
-* Contains required functions for the ARM cache functionality. Cache APIs are
-* yet to be implemented. They are left blank to avoid any compilation error
+* Contains required functions for the ARM cache functionality.
 *
 * 
 * MODIFICATION HISTORY:
 *
 * Ver    Who Date     Changes
 * ----- ---- -------- -----------------------------------------------
-* 5.00 	pkp  05/29/14 First release
-* 5.05	pkp	 04/15/16 Updated the Xil_DCacheInvalidate,
+* 5.0 	pkp  05/29/14 First release
+* 5.5	pkp	 04/15/16 Updated the Xil_DCacheInvalidate,
 *					  Xil_DCacheInvalidateLine and Xil_DCacheInvalidateRange
 *					  functions description for proper explaination
+* 6.2   pkp	 01/22/17 Added support for EL1 non-secure
+* 6.2   asa  01/31/17 The existing Xil_DCacheDisable API first flushes the
+*					  D caches and then disables it. The problem with that is,
+*					  potentially there will be a small window after the cache
+*					  flush operation and before the we disable D caches where
+*					  we might have valid data in cache lines. In such a
+*					  scenario disabling the D cache can lead to unknown behavior.
+*					  The ideal solution to this is to use assembly code for
+*					  the complete API and avoid any memory accesses. But with
+*					  that we will end up having a huge amount on assembly code
+*					  which is not maintainable. Changes are done to use a mix
+*					  of assembly and C code. All local variables are put in
+*					  registers. Also function calls are avoided in the API to
+*					  avoid using stack memory.
+*					  These changes fix CR#966220.
+* 6.2  mus  02/13/17  The new api Xil_ConfigureL1Prefetch is added to disable pre-fetching/configure
+*                     the maximum number of outstanding data prefetches allowed in
+*                     L1 cache system.It fixes CR#967864.
+* 6.6  mus  02/27/18  Updated Xil_DCacheInvalidateRange and 
+*					  Xil_ICacheInvalidateRange APIs to change the data type of 
+*					  "cacheline" variable as "INTPTR", This change has been done
+*					  to avoid the truncation of upper DDR addreses to 32 bit.It
+*					  fixes CR#995581.
+* 6.6  mus  03/15/18  By default CPUACTLR_EL1 is accessible only from EL3, it
+*					  results into abort if accessed from EL1 non secure privilege
+*					  level. Updated Xil_ConfigureL1Prefetch function to access
+*					  CPUACTLR_EL1 only for EL3.
 *
 * 

 *
@@ -66,9 +92,9 @@
 /************************** Variable Definitions *****************************/
 #define IRQ_FIQ_MASK 0xC0U	/* Mask IRQ and FIQ interrupts in cpsr */
 
-/****************************************************************************
-*
-* Enable the Data cache.
+/****************************************************************************/
+/**
+* @brief	Enable the Data cache.
 *
 * @param	None.
 *
@@ -77,12 +103,15 @@
 * @note		None.
 *
 ****************************************************************************/
-
 void Xil_DCacheEnable(void)
 {
 	u32 CtrlReg;
 
-	CtrlReg = mfcp(SCTLR_EL3);
+	if (EL3 == 1) {
+		CtrlReg = mfcp(SCTLR_EL3);
+	} else if (EL1_NONSECURE == 1) {
+		CtrlReg = mfcp(SCTLR_EL1);
+	}
 
 	/* enable caches only if they are disabled */
 	if((CtrlReg & XREG_CONTROL_DCACHE_BIT) == 0X00000000U){
@@ -92,14 +121,19 @@ void Xil_DCacheEnable(void)
 
 		CtrlReg |= XREG_CONTROL_DCACHE_BIT;
 
-		/* enable the Data cache for el3*/
-		mtcp(SCTLR_EL3,CtrlReg);
+		if (EL3 == 1) {
+			/* enable the Data cache for el3*/
+			mtcp(SCTLR_EL3,CtrlReg);
+		} else if (EL1_NONSECURE == 1) {
+			/* enable the Data cache for el1*/
+			mtcp(SCTLR_EL1,CtrlReg);
+		}
 	}
 }
 
-/****************************************************************************
-*
-* Disable the Data cache.
+/****************************************************************************/
+/**
+* @brief	Disable the Data cache.
 *
 * @param	None.
 *
@@ -110,22 +144,122 @@ void Xil_DCacheEnable(void)
 ****************************************************************************/
 void Xil_DCacheDisable(void)
 {
-	u32 CtrlReg;
-	/* clean and invalidate the Data cache */
-	Xil_DCacheFlush();
+	register u32 CsidReg;
+	register u32 C7Reg;
+	register u32 LineSize;
+	register u32 NumWays;
+	register u32 Way;
+	register u32 WayIndex;
+	register u32 WayAdjust;
+	register u32 Set;
+	register u32 SetIndex;
+	register u32 NumSet;
+	register u32 CacheLevel;
 
-	CtrlReg = mfcp(SCTLR_EL3);
+	dsb();
+	asm(
+	"mov 	x0, #0\n\t"
+#if EL3==1
+	"mrs	x0, sctlr_el3 \n\t"
+	"and	w0, w0, #0xfffffffb\n\t"
+	"msr	sctlr_el3, x0\n\t"
+#elif EL1_NONSECURE==1
+	"mrs	x0, sctlr_el1 \n\t"
+	"and	w0, w0, #0xfffffffb\n\t"
+	"msr	sctlr_el1, x0\n\t"
+#endif
+	"dsb sy\n\t"
+	);
 
-	CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
+	/* Number of level of cache*/
+	CacheLevel = 0U;
+	/* Select cache level 0 and D cache in CSSR */
+	mtcp(CSSELR_EL1,CacheLevel);
+	isb();
 
-	/* disable the Data cache for el3*/
-	mtcp(SCTLR_EL3,CtrlReg);
+	CsidReg = mfcp(CCSIDR_EL1);
+
+	/* Get the cacheline size, way size, index size from csidr */
+	LineSize = (CsidReg & 0x00000007U) + 0x00000004U;
+
+	/* Number of Ways */
+	NumWays = (CsidReg & 0x00001FFFU) >> 3U;
+	NumWays += 0x00000001U;
+
+	/*Number of Set*/
+	NumSet = (CsidReg >> 13U) & 0x00007FFFU;
+	NumSet += 0x00000001U;
+
+	WayAdjust = clz(NumWays) - (u32)0x0000001FU;
+
+	Way = 0U;
+	Set = 0U;
+
+	/* Flush all the cachelines */
+	for (WayIndex = 0U; WayIndex < NumWays; WayIndex++) {
+		for (SetIndex = 0U; SetIndex < NumSet; SetIndex++) {
+			C7Reg = Way | Set | CacheLevel;
+			mtcpdc(CISW,C7Reg);
+			Set += (0x00000001U << LineSize);
+		}
+		Set = 0U;
+		Way += (0x00000001U << WayAdjust);
+	}
+
+	/* Wait for Flush to complete */
+	dsb();
+
+	/* Select cache level 1 and D cache in CSSR */
+	CacheLevel += (0x00000001U << 1U);
+	mtcp(CSSELR_EL1,CacheLevel);
+	isb();
+
+	CsidReg = mfcp(CCSIDR_EL1);
+
+	/* Get the cacheline size, way size, index size from csidr */
+	LineSize = (CsidReg & 0x00000007U) + 0x00000004U;
+
+	/* Number of Ways */
+	NumWays = (CsidReg & 0x00001FFFU) >> 3U;
+	NumWays += 0x00000001U;
+
+	/* Number of Sets */
+	NumSet = (CsidReg >> 13U) & 0x00007FFFU;
+	NumSet += 0x00000001U;
+
+	WayAdjust=clz(NumWays) - (u32)0x0000001FU;
+
+	Way = 0U;
+	Set = 0U;
+
+	/* Flush all the cachelines */
+	for (WayIndex =0U; WayIndex < NumWays; WayIndex++) {
+		for (SetIndex =0U; SetIndex < NumSet; SetIndex++) {
+			C7Reg = Way | Set | CacheLevel;
+			mtcpdc(CISW,C7Reg);
+			Set += (0x00000001U << LineSize);
+		}
+		Set=0U;
+		Way += (0x00000001U<
 * MODIFICATION HISTORY:
@@ -54,6 +61,11 @@
 extern "C" {
 #endif
 
+/************************** Constant Definitions *****************************/
+#define L1_DATA_PREFETCH_CONTROL_MASK  0xE000
+#define L1_DATA_PREFETCH_CONTROL_SHIFT  13
+
+/************************** Function Prototypes ******************************/
 void Xil_DCacheEnable(void);
 void Xil_DCacheDisable(void);
 void Xil_DCacheInvalidate(void);
@@ -68,8 +80,12 @@ void Xil_ICacheDisable(void);
 void Xil_ICacheInvalidate(void);
 void Xil_ICacheInvalidateRange(INTPTR adr, INTPTR len);
 void Xil_ICacheInvalidateLine(INTPTR adr);
+void Xil_ConfigureL1Prefetch(u8 num);
 #ifdef __cplusplus
 }
 #endif
 
 #endif
+/**
+* @} End of "addtogroup a53_64_cache_apis".
+*/
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_cache_vxworks.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_cache_vxworks.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_cache_vxworks.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_cache_vxworks.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_mpu.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_errata.h
similarity index 64%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_mpu.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_errata.h
index a55be916e..bab74ba37 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_mpu.h
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_errata.h
@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2017 Xilinx, Inc.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
@@ -31,50 +31,55 @@
 ******************************************************************************/
 /*****************************************************************************/
 /**
-* @file xil_mmu.h
 *
+* @file xil_errata.h
 *
+* @addtogroup a53_errata Cortex A53 64 bit Processor Errata Support
+* @{
+* Various ARM errata are handled in the standalone BSP. The implementation for
+* errata handling follows ARM guidelines and is based on the open source Linux
+* support for these errata.
+*
+* @note
+* The errata handling is enabled by default. To disable handling of all the
+* errata globally, un-define the macro ENABLE_ARM_ERRATA in xil_errata.h. To
+* disable errata on a per-erratum basis, un-define relevant macros in
+* xil_errata.h.
 *
 * 
 * MODIFICATION HISTORY:
 *
 * Ver   Who  Date     Changes
-* ----- ---- -------- ---------------------------------------------------
-* 5.00  pkp  02/10/14 Initial version
+* ----- ---- -------- -----------------------------------------------
+* 6.4   mus  08/11/17 First release
 * 

 *
-* @note
-*
-* None.
-*
 ******************************************************************************/
+#ifndef XIL_ERRATA_H
+#define XIL_ERRATA_H
 
-#ifndef XIL_MPU_H
-#define XIL_MPU_H
+/**
+ * @name errata_definitions
+ *
+ * The errata conditions handled in the standalone BSP are listed below
+ * @{
+ */
 
-#ifdef __cplusplus
-extern "C" {
-#endif /* __cplusplus */
-#include "xil_types.h"
-/***************************** Include Files *********************************/
+#define ENABLE_ARM_ERRATA 1
 
-/***************** Macros (Inline Functions) Definitions *********************/
+#ifdef ENABLE_ARM_ERRATA
 
-/**************************** Type Definitions *******************************/
+/**
+ *  Errata No: 855873
+ *  Description: An eviction might overtake a cache clean operation
+ */
+#define CONFIG_ARM_ERRATA_855873 1
 
-/************************** Constant Definitions *****************************/
 
-/************************** Variable Definitions *****************************/
+/*@}*/
+#endif  /* ENABLE_ARM_ERRATA */
 
-/************************** Function Prototypes ******************************/
-
-void Xil_SetTlbAttributes(INTPTR Addr, u32 attrib);
-void Xil_EnableMPU(void);
-void Xil_DisableMPU(void);
-void Xil_SetMPURegion(INTPTR addr, u64 size, u32 attrib);
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* XIL_MPU_H */
+#endif  /* XIL_ERRATA_H */
+/**
+* @} End of "addtogroup a53_errata".
+*/
\ No newline at end of file
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_exception.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_exception.c
similarity index 85%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_exception.c
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_exception.c
index 66f722d92..4a2f2cfdf 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_exception.c
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_exception.c
@@ -46,6 +46,8 @@
 * 6.0   mus      27/07/16 Consolidated exceptions for a53,a9 and r5
 *                         processors and added Xil_UndefinedExceptionHandler
 *                         for a53 32 bit and r5 as well.
+* 6.4   mus      08/06/17 Updated debug prints to replace %x with the %lx, to
+*                         fix the warnings.
 *
* *****************************************************************************/ @@ -122,19 +124,19 @@ u32 UndefinedExceptionAddr; /* Address of instruction causing Undefined *****************************************************************************/ static void Xil_ExceptionNullHandler(void *Data) { - (void *)Data; + (void) Data; DieLoop: goto DieLoop; } /****************************************************************************/ /** -* The function is a common API used to initialize exception handlers across all -* processors supported. For ARM CortexA53,R5,A9, the exception handlers are being -* initialized statically and hence this function does not do anything. -* However, it is still present to avoid any compilation issues in case an -* application uses this API and also to take care of backward compatibility -* issues (in earlier versions of BSPs, this API was being used to initialize -* exception handlers). +* @brief The function is a common API used to initialize exception handlers +* across all supported arm processors. For ARM Cortex-A53, Cortex-R5, +* and Cortex-A9, the exception handlers are being initialized +* statically and this function does not do anything. +* However, it is still present to take care of backward compatibility +* issues (in earlier versions of BSPs, this API was being used to +* initialize exception handlers). * * @param None. * @@ -150,18 +152,15 @@ void Xil_ExceptionInit(void) /*****************************************************************************/ /** -* -* Makes the connection between the Id of the exception source and the -* associated Handler that is to run when the exception is recognized. The -* argument provided in this call as the Data is used as the argument -* for the Handler when it is called. +* @brief Register a handler for a specific exception. This handler is being +* called when the processor encounters the specified exception. * * @param exception_id contains the ID of the exception source and should -* be in the range of 0 to XIL_EXCEPTION_ID_LAST. - See xil_exception_l.h for further information. +* be in the range of 0 to XIL_EXCEPTION_ID_LAST. +* See xil_exception.h for further information. * @param Handler to the Handler for that exception. * @param Data is a reference to Data that will be passed to the -* Handler when it gets called. +* Handler when it gets called. * * @return None. * @@ -179,13 +178,13 @@ void Xil_ExceptionRegisterHandler(u32 Exception_id, /*****************************************************************************/ /** * -* Removes the Handler for a specific exception Id. The stub Handler is then -* registered for this exception Id. +* @brief Removes the Handler for a specific exception Id. The stub Handler +* is then registered for this exception Id. * * @param exception_id contains the ID of the exception source and should -* be in the range of 0 to XIL_EXCEPTION_ID_LAST. -* See xil_exception_l.h for further information. - +* be in the range of 0 to XIL_EXCEPTION_ID_LAST. +* See xil_exception.h for further information. +* * @return None. * * @note None. @@ -214,6 +213,7 @@ void Xil_ExceptionRemoveHandler(u32 Exception_id) ****************************************************************************/ void Xil_SyncAbortHandler(void *CallBackRef){ + (void) CallBackRef; xdbg_printf(XDBG_DEBUG_ERROR, "Synchronous abort \n"); while(1) { ; @@ -234,6 +234,7 @@ void Xil_SyncAbortHandler(void *CallBackRef){ * ****************************************************************************/ void Xil_SErrorAbortHandler(void *CallBackRef){ + (void) CallBackRef; xdbg_printf(XDBG_DEBUG_ERROR, "Synchronous abort \n"); while(1) { ; @@ -241,7 +242,7 @@ void Xil_SErrorAbortHandler(void *CallBackRef){ } #else /*****************************************************************************/ -/** +/* * * Default Data abort handler which prints data fault status register through * which information about data fault can be acquired @@ -255,6 +256,7 @@ void Xil_SErrorAbortHandler(void *CallBackRef){ ****************************************************************************/ void Xil_DataAbortHandler(void *CallBackRef){ + (void) CallBackRef; #ifdef DEBUG u32 FaultStatus; @@ -267,8 +269,8 @@ void Xil_DataAbortHandler(void *CallBackRef){ { volatile register u32 Reg __asm(XREG_CP15_DATA_FAULT_STATUS); FaultStatus = Reg; } #endif - xdbg_printf(XDBG_DEBUG_GENERAL, "Data abort with Data Fault Status Register %x\n",FaultStatus); - xdbg_printf(XDBG_DEBUG_GENERAL, "Address of Instrcution causing Data abort %x\n",DataAbortAddr); + xdbg_printf(XDBG_DEBUG_GENERAL, "Data abort with Data Fault Status Register %lx\n",FaultStatus); + xdbg_printf(XDBG_DEBUG_GENERAL, "Address of Instruction causing Data abort %lx\n",DataAbortAddr); #endif while(1) { ; @@ -276,7 +278,7 @@ void Xil_DataAbortHandler(void *CallBackRef){ } /*****************************************************************************/ -/** +/* * * Default Prefetch abort handler which prints prefetch fault status register through * which information about instruction prefetch fault can be acquired @@ -289,6 +291,7 @@ void Xil_DataAbortHandler(void *CallBackRef){ * ****************************************************************************/ void Xil_PrefetchAbortHandler(void *CallBackRef){ + (void) CallBackRef; #ifdef DEBUG u32 FaultStatus; @@ -301,15 +304,15 @@ void Xil_PrefetchAbortHandler(void *CallBackRef){ { volatile register u32 Reg __asm(XREG_CP15_INST_FAULT_STATUS); FaultStatus = Reg; } #endif - xdbg_printf(XDBG_DEBUG_GENERAL, "Prefetch abort with Instruction Fault Status Register %x\n",FaultStatus); - xdbg_printf(XDBG_DEBUG_GENERAL, "Address of Instrcution causing Prefetch abort %x\n",PrefetchAbortAddr); + xdbg_printf(XDBG_DEBUG_GENERAL, "Prefetch abort with Instruction Fault Status Register %lx\n",FaultStatus); + xdbg_printf(XDBG_DEBUG_GENERAL, "Address of Instruction causing Prefetch abort %lx\n",PrefetchAbortAddr); #endif while(1) { ; } } /*****************************************************************************/ -/** +/* * * Default undefined exception handler which prints address of the undefined * instruction if debug prints are enabled @@ -322,8 +325,8 @@ void Xil_PrefetchAbortHandler(void *CallBackRef){ * ****************************************************************************/ void Xil_UndefinedExceptionHandler(void *CallBackRef){ - - xdbg_printf(XDBG_DEBUG_GENERAL, "Address of the undefined instruction %x\n",UndefinedExceptionAddr); + (void) CallBackRef; + xdbg_printf(XDBG_DEBUG_GENERAL, "Address of the undefined instruction %lx\n",UndefinedExceptionAddr); while(1) { ; } diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_exception.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_exception.h similarity index 90% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_exception.h rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_exception.h index 434ef2a6a..ad4822205 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_exception.h +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_exception.h @@ -38,6 +38,12 @@ * For exception related functions that can be used across all Xilinx supported * processors, please use xil_exception.h. * +* @addtogroup arm_exception_apis ARM Processor Exception Handling +* @{ +* ARM processors specific exception related APIs for cortex A53,A9 and R5 can +* utilized for enabling/disabling IRQ, registering/removing handler for +* exceptions or initializing exception vector table with null handler. +* * 
 * MODIFICATION HISTORY:
 *
@@ -102,14 +108,14 @@ typedef void (*Xil_InterruptHandler)(void *data);
 
 /****************************************************************************/
 /**
-* Enable Exceptions.
+* @brief	Enable Exceptions.
 *
-* @param	Mask for exceptions to be enabled.
+* @param	Mask: Value for enabling the exceptions.
 *
 * @return	None.
 *
 * @note		If bit is 0, exception is enabled.
-*		C-Style signature: void Xil_ExceptionEnableMask(Mask)
+*			C-Style signature: void Xil_ExceptionEnableMask(Mask)
 *
 ******************************************************************************/
 #if defined (__GNUC__) || defined (__ICCARM__)
@@ -124,7 +130,7 @@ typedef void (*Xil_InterruptHandler)(void *data);
 #endif
 /****************************************************************************/
 /**
-* Enable the IRQ exception.
+* @brief	Enable the IRQ exception.
 *
 * @return   None.
 *
@@ -136,14 +142,14 @@ typedef void (*Xil_InterruptHandler)(void *data);
 
 /****************************************************************************/
 /**
-* Disable Exceptions.
+* @brief	Disable Exceptions.
 *
-* @param	Mask for exceptions to be enabled.
+* @param	Mask: Value for disabling the exceptions.
 *
 * @return	None.
 *
 * @note		If bit is 1, exception is disabled.
-*		C-Style signature: Xil_ExceptionDisableMask(Mask)
+*			C-Style signature: Xil_ExceptionDisableMask(Mask)
 *
 ******************************************************************************/
 #if defined (__GNUC__) || defined (__ICCARM__)
@@ -171,7 +177,8 @@ typedef void (*Xil_InterruptHandler)(void *data);
 #if !defined (__aarch64__) && !defined (ARMA53_32)
 /****************************************************************************/
 /**
-* Enable nested interrupts by clearing the I and F bits it CPSR
+* @brief	Enable nested interrupts by clearing the I and F bits in CPSR. This
+* 			API is defined for cortex-a9 and cortex-r5.
 *
 * @return   None.
 *
@@ -197,7 +204,8 @@ typedef void (*Xil_InterruptHandler)(void *data);
 
 /****************************************************************************/
 /**
-* Disable the nested interrupts by setting the I and F bits.
+* @brief	Disable the nested interrupts by setting the I and F bits. This API
+*			is defined for cortex-a9 and cortex-r5.
 *
 * @return   None.
 *
@@ -243,3 +251,6 @@ extern void Xil_UndefinedExceptionHandler(void *CallBackRef);
 #endif /* __cplusplus */
 
 #endif /* XIL_EXCEPTION_H */
+/**
+* @} End of "addtogroup arm_exception_apis".
+*/
\ No newline at end of file
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_hal.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_hal.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_hal.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_hal.h
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_io.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_io.c
similarity index 90%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_io.c
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_io.c
index 31de05581..90bfc81dc 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_io.c
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_io.c
@@ -35,8 +35,7 @@
 * @file xil_io.c
 *
 * Contains I/O functions for memory-mapped or non-memory-mapped I/O
-* architectures.  These functions encapsulate Cortex A53 architecture-specific
-* I/O requirements.
+* architectures.
 *
 * @note
 *
@@ -60,13 +59,11 @@
 /*****************************************************************************/
 /**
 *
-* Perform a 16-bit endian converion.
+* @brief    Perform a 16-bit endian converion.
 *
-* @param	Data contains the value to be converted.
+* @param	Data: 16 bit value to be converted
 *
-* @return	converted value.
-*
-* @note		None.
+* @return	16 bit Data with converted endianess
 *
 ******************************************************************************/
 u16 Xil_EndianSwap16(u16 Data)
@@ -77,13 +74,11 @@ u16 Xil_EndianSwap16(u16 Data)
 /*****************************************************************************/
 /**
 *
-* Perform a 32-bit endian converion.
+* @brief    Perform a 32-bit endian converion.
 *
-* @param	Data contains the value to be converted.
+* @param	Data: 32 bit value to be converted
 *
-* @return	converted value.
-*
-* @note		None.
+* @return	32 bit data with converted endianess
 *
 ******************************************************************************/
 u32 Xil_EndianSwap32(u32 Data)
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_io.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_io.h
similarity index 74%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_io.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_io.h
index 06d89dcc3..9c5aa43c7 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_io.h
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_io.h
@@ -34,11 +34,13 @@
 *
 * @file xil_io.h
 *
-* This file contains the interface for the general IO component, which
-* encapsulates the Input/Output functions for processors that do not
+* @addtogroup common_io_interfacing_apis Register IO interfacing APIs
+*
+* The xil_io.h file contains the interface for the general I/O component, which
+* encapsulates the Input/Output functions for the processors that do not
 * require any special I/O handling.
 *
-*
+* @{
 * 
 * MODIFICATION HISTORY:
 *
@@ -71,6 +73,9 @@ extern "C" {
 /************************** Function Prototypes ******************************/
 u16 Xil_EndianSwap16(u16 Data);
 u32 Xil_EndianSwap32(u32 Data);
+#ifdef ENABLE_SAFETY
+extern u32 XStl_RegUpdate(u32 RegAddr, u32 RegVal);
+#endif
 
 /***************** Macros (Inline Functions) Definitions *********************/
 #if defined __GNUC__
@@ -99,15 +104,14 @@ u32 Xil_EndianSwap32(u32 Data);
 /*****************************************************************************/
 /**
 *
-* Performs an input operation for an 8-bit memory location by reading from the
-* specified address and returning the Value read from that address.
+* @brief    Performs an input operation for a memory location by reading
+*           from the specified address and returning the 8 bit Value read from
+*            that address.
 *
-* @param	Addr contains the address to perform the input operation
-*		at.
+* @param	Addr: contains the address to perform the input operation
 *
-* @return	The Value read from the specified input address.
-*
-* @note		None.
+* @return	The 8 bit Value read from the specified input address.
+
 *
 ******************************************************************************/
 static INLINE u8 Xil_In8(UINTPTR Addr)
@@ -118,15 +122,13 @@ static INLINE u8 Xil_In8(UINTPTR Addr)
 /*****************************************************************************/
 /**
 *
-* Performs an input operation for a 16-bit memory location by reading from the
-* specified address and returning the Value read from that address.
+* @brief    Performs an input operation for a memory location by reading from
+*           the specified address and returning the 16 bit Value read from that
+*           address.
 *
-* @param	Addr contains the address to perform the input operation
-*		at.
+* @param	Addr: contains the address to perform the input operation
 *
-* @return	The Value read from the specified input address.
-*
-* @note		None.
+* @return	The 16 bit Value read from the specified input address.
 *
 ******************************************************************************/
 static INLINE u16 Xil_In16(UINTPTR Addr)
@@ -137,15 +139,13 @@ static INLINE u16 Xil_In16(UINTPTR Addr)
 /*****************************************************************************/
 /**
 *
-* Performs an input operation for a 32-bit memory location by reading from the
-* specified address and returning the Value read from that address.
+* @brief    Performs an input operation for a memory location by
+*           reading from the specified address and returning the 32 bit Value
+*           read  from that address.
 *
-* @param	Addr contains the address to perform the input operation
-*		at.
+* @param	Addr: contains the address to perform the input operation
 *
-* @return	The Value read from the specified input address.
-*
-* @note		None.
+* @return	The 32 bit Value read from the specified input address.
 *
 ******************************************************************************/
 static INLINE u32 Xil_In32(UINTPTR Addr)
@@ -156,16 +156,13 @@ static INLINE u32 Xil_In32(UINTPTR Addr)
 /*****************************************************************************/
 /**
 *
-* Performs an input operation for a 64-bit memory location by reading the
-* specified Value to the the specified address.
+* @brief     Performs an input operation for a memory location by reading the
+*            64 bit Value read  from that address.
 *
-* @param	OutAddress contains the address to perform the output operation
-*		at.
-* @param	Value contains the Value to be output at the specified address.
 *
-* @return	None.
+* @param	Addr: contains the address to perform the input operation
 *
-* @note		None.
+* @return	The 64 bit Value read from the specified input address.
 *
 ******************************************************************************/
 static INLINE u64 Xil_In64(UINTPTR Addr)
@@ -176,17 +173,15 @@ static INLINE u64 Xil_In64(UINTPTR Addr)
 /*****************************************************************************/
 /**
 *
-* Performs an output operation for an 8-bit memory location by writing the
-* specified Value to the the specified address.
+* @brief    Performs an output operation for an memory location by
+*           writing the 8 bit Value to the the specified address.
 *
-* @param	Addr contains the address to perform the output operation
-*		at.
-* @param	Value contains the Value to be output at the specified address.
+* @param	Addr: contains the address to perform the output operation
+* @param	Value: contains the 8 bit Value to be written at the specified
+*           address.
 *
 * @return	None.
 *
-* @note		None.
-*
 ******************************************************************************/
 static INLINE void Xil_Out8(UINTPTR Addr, u8 Value)
 {
@@ -197,17 +192,14 @@ static INLINE void Xil_Out8(UINTPTR Addr, u8 Value)
 /*****************************************************************************/
 /**
 *
-* Performs an output operation for a 16-bit memory location by writing the
-* specified Value to the the specified address.
+* @brief    Performs an output operation for a memory location by writing the
+*            16 bit Value to the the specified address.
 *
 * @param	Addr contains the address to perform the output operation
-*		at.
-* @param	Value contains the Value to be output at the specified address.
+* @param	Value contains the Value to be written at the specified address.
 *
 * @return	None.
 *
-* @note		None.
-*
 ******************************************************************************/
 static INLINE void Xil_Out16(UINTPTR Addr, u16 Value)
 {
@@ -218,38 +210,37 @@ static INLINE void Xil_Out16(UINTPTR Addr, u16 Value)
 /*****************************************************************************/
 /**
 *
-* Performs an output operation for a 32-bit memory location by writing the
-* specified Value to the the specified address.
+* @brief    Performs an output operation for a memory location by writing the
+*           32 bit Value to the the specified address.
 *
 * @param	Addr contains the address to perform the output operation
-*		at.
-* @param	Value contains the Value to be output at the specified address.
+* @param	Value contains the 32 bit Value to be written at the specified
+*           address.
 *
 * @return	None.
 *
-* @note		None.
-*
 ******************************************************************************/
 static INLINE void Xil_Out32(UINTPTR Addr, u32 Value)
 {
+#ifndef ENABLE_SAFETY
 	volatile u32 *LocalAddr = (volatile u32 *)Addr;
 	*LocalAddr = Value;
+#else
+	XStl_RegUpdate(Addr, Value);
+#endif
 }
 
 /*****************************************************************************/
 /**
 *
-* Performs an output operation for a 64-bit memory location by writing the
-* specified Value to the the specified address.
+* @brief    Performs an output operation for a memory location by writing the
+*           64 bit Value to the the specified address.
 *
 * @param	Addr contains the address to perform the output operation
-*		at.
-* @param	Value contains the Value to be output at the specified address.
+* @param	Value contains 64 bit Value to be written at the specified address.
 *
 * @return	None.
 *
-* @note		None.
-*
 ******************************************************************************/
 static INLINE void Xil_Out64(UINTPTR Addr, u64 Value)
 {
@@ -312,7 +303,7 @@ static INLINE u32 Xil_In32LE(UINTPTR Addr)
 static INLINE u32 Xil_In32BE(UINTPTR Addr)
 #endif
 {
-	u16 value = Xil_In32(Addr);
+	u32 value = Xil_In32(Addr);
 	return Xil_EndianSwap32(value);
 }
 
@@ -349,3 +340,6 @@ static INLINE void Xil_Out32BE(UINTPTR Addr, u32 Value)
 #endif
 
 #endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_io_interfacing_apis".
+*/
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_macroback.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_macroback.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_macroback.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_macroback.h
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_mem.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_mem.c
new file mode 100644
index 000000000..0929a6878
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_mem.c
@@ -0,0 +1,83 @@
+/******************************************************************************/
+/**
+* Copyright (C) 2015 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+* @file xil_mem.c
+*
+* This file contains xil mem copy function to use in case of word aligned
+* data copies.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 6.1   nsk      11/07/16 First release.
+*
+* 

+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+
+/***************** Inline Functions Definitions ********************/
+/*****************************************************************************/
+/**
+* @brief       This  function copies memory from once location to other.
+*
+* @param       dst: pointer pointing to destination memory
+*
+* @param       src: pointer pointing to source memory
+*
+* @param       cnt: 32 bit length of bytes to be copied
+*
+*****************************************************************************/
+void Xil_MemCpy(void* dst, const void* src, u32 cnt)
+{
+	char *d = (char*)(void *)dst;
+	const char *s = src;
+
+	while (cnt >= sizeof (int)) {
+		*(int*)d = *(int*)s;
+		d += sizeof (int);
+		s += sizeof (int);
+		cnt -= sizeof (int);
+	}
+	while ((cnt) > 0U){
+		*d = *s;
+		d += 1U;
+		s += 1U;
+		cnt -= 1U;
+	}
+}
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_mem.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_mem.h
new file mode 100644
index 000000000..a2d5e6681
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_mem.h
@@ -0,0 +1,59 @@
+/******************************************************************************/
+/**
+* Copyright (C) 2015 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+* @file xil_mem.h
+*
+* @addtogroup common_mem_operation_api Customized APIs for Memory Operations
+*
+* The xil_mem.h file contains prototype for functions related
+* to memory operations. These APIs are applicable for all processors supported
+* by Xilinx.
+*
+* @{
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 6.1   nsk      11/07/16 First release.
+*
+* 

+*
+*****************************************************************************/
+
+/************************** Function Prototypes *****************************/
+
+void Xil_MemCpy(void* dst, const void* src, u32 cnt);
+/**
+* @} End of "addtogroup common_mem_operation_api".
+*/
\ No newline at end of file
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_mmu.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_mmu.c
similarity index 82%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_mmu.c
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_mmu.c
index 1e28b699c..87b9886f4 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_mmu.c
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_mmu.c
@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2014 - 2017 Xilinx, Inc. All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
@@ -44,6 +44,7 @@
 * Ver   Who  Date     Changes
 * ----- ---- -------- ---------------------------------------------------
 * 5.00 	pkp  05/29/14 First release
+* 6.02  pkp	 01/22/17 Added support for EL1 non-secure
 * 

 *
 * @note
@@ -75,12 +76,18 @@ extern INTPTR MMUTableL1;
 extern INTPTR MMUTableL2;
 
 /************************** Function Prototypes ******************************/
-/*****************************************************************************
+/*****************************************************************************/
+/**
+* brief		It sets the memory attributes for a section, in the translation
+* 			table. If the address (defined by Addr) is less than 4GB, the
+*			memory attribute(attrib) is set for a section of 2MB memory. If the
+*			address (defined by Addr) is greater than 4GB, the memory attribute
+*			(attrib) is set for a section of 1GB memory.
 *
-* Set the memory attributes for a section, in the translation table.
-*
-* @param	addr is the address for which attributes are to be set.
-* @param	attrib specifies the attributes for that memory region.
+* @param	Addr: 64-bit address for which attributes are to be set.
+* @param	attrib: Attribute for the specified memory region. xil_mmu.h
+*			contains commonly used memory attributes definitions which can be
+*			utilized for this function.
 *
 * @return	None.
 *
@@ -88,8 +95,7 @@ extern INTPTR MMUTableL2;
 *			translation table attribute.
 *
 ******************************************************************************/
-
-void Xil_SetTlbAttributes(INTPTR Addr, u64 attrib)
+void Xil_SetTlbAttributes(UINTPTR Addr, u64 attrib)
 {
 	INTPTR *ptr;
 	INTPTR section;
@@ -112,7 +118,10 @@ void Xil_SetTlbAttributes(INTPTR Addr, u64 attrib)
 
 	Xil_DCacheFlush();
 
-	mtcptlbi(ALLE3);
+	if (EL3 == 1)
+		mtcptlbi(ALLE3);
+	else if (EL1_NONSECURE == 1)
+		mtcptlbi(VMALLE1);
 
 	dsb(); /* ensure completion of the BP and TLB invalidation */
     isb(); /* synchronize context on this processor */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_mmu.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_mmu.h
similarity index 92%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_mmu.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_mmu.h
index 8c3215fd7..0f2db84a8 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_mmu.h
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_mmu.h
@@ -33,7 +33,12 @@
 /**
 * @file xil_mmu.h
 *
+* @addtogroup a53_64_mmu_apis Cortex A53 64bit Processor MMU Handling
 *
+* MMU function equip users to modify default memory attributes of MMU table as
+* per the need.
+*
+* @{
 *
 * 
 * MODIFICATION HISTORY:
@@ -96,10 +101,13 @@ extern "C" {
 
 /************************** Function Prototypes ******************************/
 
-void Xil_SetTlbAttributes(INTPTR Addr, u64 attrib);
+void Xil_SetTlbAttributes(UINTPTR Addr, u64 attrib);
 
 #ifdef __cplusplus
 }
 #endif /* __cplusplus */
 
 #endif /* XIL_MMU_H */
+/**
+* @} End of "addtogroup a53_64_mmu_apis".
+*/
\ No newline at end of file
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_printf.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_printf.c
similarity index 98%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_printf.c
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_printf.c
index 9dffed148..dc0897f0d 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_printf.c
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_printf.c
@@ -75,8 +75,8 @@ static void outs(const charptr lp, struct params_s *par)
 		(par->num2)--;
 #ifdef STDOUT_BASEADDRESS
         outbyte(*LocalPtr);
-		LocalPtr += 1;
 #endif
+		LocalPtr += 1;
 }
 
     /* Pad on right if needed                        */
@@ -135,8 +135,8 @@ static void outnum( const s32 n, const s32 base, struct params_s *par)
     while (&outbuf[i] >= outbuf) {
 #ifdef STDOUT_BASEADDRESS
 	outbyte( outbuf[i] );
-		i--;
 #endif
+		i--;
 }
     padding( par->left_flag, par);
 }
@@ -239,6 +239,11 @@ static s32 getnum( charptr* linep)
 
 /* void esp_printf( const func_ptr f_ptr,
    const charptr ctrl1, ...) */
+#if HYP_GUEST && EL1_NONSECURE && XEN_USE_PV_CONSOLE
+void xil_printf( const char8 *ctrl1, ...){
+	XPVXenConsole_Printf(ctrl1);
+}
+#else
 void xil_printf( const char8 *ctrl1, ...)
 {
 	s32 Check;
@@ -262,8 +267,8 @@ void xil_printf( const char8 *ctrl1, ...)
         if (*ctrl != '%') {
 #ifdef STDOUT_BASEADDRESS
             outbyte(*ctrl);
-			ctrl += 1;
 #endif
+			ctrl += 1;
             continue;
         }
 
@@ -434,5 +439,5 @@ void xil_printf( const char8 *ctrl1, ...)
     }
     va_end( argp);
 }
-
+#endif
 /*---------------------------------------------------*/
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_printf.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_printf.h
similarity index 91%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_printf.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_printf.h
index 2be5c5734..016ae3b2f 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_printf.h
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_printf.h
@@ -10,6 +10,10 @@ extern "C" {
 #include 
 #include "xil_types.h"
 #include "xparameters.h"
+#include "bspconfig.h"
+#if HYP_GUEST && EL1_NONSECURE && XEN_USE_PV_CONSOLE
+#include "xen_console.h"
+#endif
 
 /*----------------------------------------------------*/
 /* Use the following parameter passing structure to   */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_sleepcommon.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_sleepcommon.c
new file mode 100644
index 000000000..972a310a8
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_sleepcommon.c
@@ -0,0 +1,106 @@
+/******************************************************************************
+*
+* Copyright (C) 2017 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+*@file xil_sleepcommon.c
+*
+* This file contains the sleep API's
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 6.6 	srm  	 11/02/17 First release
+* 

+******************************************************************************/
+
+
+/***************************** Include Files *********************************/
+#include "xil_io.h"
+#include "sleep.h"
+
+/****************************  Constant Definitions  *************************/
+
+
+/*****************************************************************************/
+/**
+*
+* This API gives delay in sec
+*
+* @param            seconds - delay time in seconds
+*
+* @return           none
+*
+* @note             none
+*
+*****************************************************************************/
+ void sleep(unsigned int seconds)
+ {
+#if defined (ARMR5)
+	sleep_R5(seconds);
+#elif defined (__aarch64__) || defined (ARMA53_32)
+	sleep_A53(seconds);
+#elif defined (__MICROBLAZE__)
+	sleep_MB(seconds);
+#else
+	sleep_A9(seconds);
+#endif
+
+ }
+
+/****************************************************************************/
+/**
+*
+* This API gives delay in usec
+*
+* @param            useconds - delay time in useconds
+*
+* @return           none
+*
+* @note             none
+*
+*****************************************************************************/
+ void usleep(unsigned long useconds)
+ {
+#if defined (ARMR5)
+	usleep_R5(useconds);
+#elif defined (__aarch64__) || defined (ARMA53_32)
+	usleep_A53(useconds);
+#elif defined (__MICROBLAZE__)
+	usleep_MB(useconds);
+#else
+	usleep_A9(useconds);
+#endif
+
+ }
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_sleeptimer.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_sleeptimer.c
new file mode 100644
index 000000000..477260676
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_sleeptimer.c
@@ -0,0 +1,161 @@
+/******************************************************************************
+*
+* Copyright (C) 2017 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+/*****************************************************************************/
+/**
+*
+* @file xil_sleeptimer.c
+*
+* This file provides the common helper routines for the sleep API's
+*
+* 
+* MODIFICATION HISTORY :
+*
+* Ver   Who  Date	 Changes
+* ----- ---- -------- -------------------------------------------------------
+* 6.6	srm  10/18/17 First Release.
+*
+* 

+*****************************************************************************/
+
+/****************************  Include Files  ********************************/
+
+#include "xil_io.h"
+#include "xil_sleeptimer.h"
+#include "xtime_l.h"
+
+/****************************  Constant Definitions  *************************/
+
+
+/* Function definitions are applicable only when TTC3 is present*/
+#if defined (SLEEP_TIMER_BASEADDR)
+/****************************************************************************/
+/**
+*
+* This is a helper function used by sleep/usleep APIs to
+* have delay in sec/usec
+*
+* @param            delay - delay time in seconds/micro seconds
+*
+* @param            frequency - Number of counts per second/micro second
+*
+* @return           none
+*
+* @note             none
+*
+*****************************************************************************/
+void Xil_SleepTTCCommon(u32 delay, u64 frequency)
+{
+	INTPTR tEnd = 0U;
+	INTPTR tCur = 0U;
+	XCntrVal TimeHighVal = 0U;
+	XCntrVal TimeLowVal1 = 0U;
+	XCntrVal TimeLowVal2 = 0U;
+
+	TimeLowVal1 = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR +
+			XSLEEP_TIMER_TTC_COUNT_VALUE_OFFSET);
+	tEnd = (INTPTR)TimeLowVal1 + ((INTPTR)(delay) * frequency);
+	do
+	{
+		TimeLowVal2 = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR +
+				                  XSLEEP_TIMER_TTC_COUNT_VALUE_OFFSET);
+		if (TimeLowVal2 < TimeLowVal1) {
+			TimeHighVal++;
+		}
+		TimeLowVal1 = TimeLowVal2;
+		tCur = (((INTPTR) TimeHighVal) << XSLEEP_TIMER_REG_SHIFT) |
+								(INTPTR)TimeLowVal2;
+	}while (tCur < tEnd);
+}
+
+
+/*****************************************************************************/
+/**
+*
+* This API starts the Triple Timer Counter
+*
+* @param            none
+*
+* @return           none
+*
+* @note             none
+*
+*****************************************************************************/
+void XTime_StartTTCTimer()
+{
+	u32 TimerPrescalar;
+	u32 TimerCntrl;
+
+#if (defined (__aarch64__) && EL3==1) || defined (ARMR5) || defined (ARMA53_32)
+	u32 LpdRst;
+
+	LpdRst = XSleep_ReadCounterVal(RST_LPD_IOU2);
+
+	/* check if the timer is reset */
+	if (((LpdRst & (RST_LPD_IOU2_TTC_BASE_RESET_MASK <<
+					       XSLEEP_TTC_INSTANCE)) != 0 )) {
+		LpdRst = LpdRst & (~(RST_LPD_IOU2_TTC_BASE_RESET_MASK <<
+							XSLEEP_TTC_INSTANCE));
+		Xil_Out32(RST_LPD_IOU2, LpdRst);
+	} else {
+#endif
+		TimerCntrl = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR +
+					XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET);
+		/* check if Timer is disabled */
+		if ((TimerCntrl & XSLEEP_TIMER_TTC_CNT_CNTRL_DIS_MASK) == 0) {
+		    TimerPrescalar = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR +
+					       XSLEEP_TIMER_TTC_CLK_CNTRL_OFFSET);
+		/* check if Timer is configured with proper functionalty for sleep */
+		   if ((TimerPrescalar & XSLEEP_TIMER_TTC_CLK_CNTRL_PS_EN_MASK) == 0)
+						return;
+		}
+#if (defined (__aarch64__) && EL3==1) || defined (ARMR5) || defined (ARMA53_32)
+	}
+#endif
+	/* Disable the timer to configure */
+	TimerCntrl = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR +
+					XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET);
+	TimerCntrl = TimerCntrl | XSLEEP_TIMER_TTC_CNT_CNTRL_DIS_MASK;
+	Xil_Out32(SLEEP_TIMER_BASEADDR + XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET,
+			                 TimerCntrl);
+	/* Disable the prescalar */
+	TimerPrescalar = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR +
+			XSLEEP_TIMER_TTC_CLK_CNTRL_OFFSET);
+	TimerPrescalar = TimerPrescalar & (~XSLEEP_TIMER_TTC_CLK_CNTRL_PS_EN_MASK);
+	Xil_Out32(SLEEP_TIMER_BASEADDR + XSLEEP_TIMER_TTC_CLK_CNTRL_OFFSET,
+								TimerPrescalar);
+	/* Enable the Timer */
+	TimerCntrl = TimerCntrl & (~XSLEEP_TIMER_TTC_CNT_CNTRL_DIS_MASK);
+	Xil_Out32(SLEEP_TIMER_BASEADDR + XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET,
+								TimerCntrl);
+}
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_sleeptimer.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_sleeptimer.h
new file mode 100644
index 000000000..4bfac0ac4
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_sleeptimer.h
@@ -0,0 +1,116 @@
+/******************************************************************************
+*
+* Copyright (C) 2017 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_sleeptimer.h
+*
+* This header file contains ARM Cortex A53,A9,R5 specific sleep related APIs.
+* For sleep related functions that can be used across all Xilinx supported
+* processors, please use xil_sleeptimer.h.
+*
+*
+* 
+* MODIFICATION HISTORY :
+*
+* Ver   Who  Date	 Changes
+* ----- ---- -------- -------------------------------------------------------
+* 6.6	srm  10/18/17 First Release.
+*
+* 

+*****************************************************************************/
+
+#ifndef XIL_SLEEPTIMER_H		/* prevent circular inclusions */
+#define XIL_SLEEPTIMER_H		/* by using protection macros */
+/****************************  Include Files  ********************************/
+
+#include "xil_io.h"
+#include "xparameters.h"
+#include "bspconfig.h"
+
+/************************** Constant Definitions *****************************/
+
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32)
+#define XSLEEP_TIMER_REG_SHIFT  32U
+#define XSleep_ReadCounterVal   Xil_In32
+#define XCntrVal 			    u32
+#else
+#define XSLEEP_TIMER_REG_SHIFT  16U
+#define XSleep_ReadCounterVal   Xil_In16
+#define XCntrVal 			    u16
+#endif
+
+#if defined(ARMR5) || (defined (__aarch64__) && EL3==1) || defined (ARMA53_32)
+#define RST_LPD_IOU2 					    0xFF5E0238U
+#define RST_LPD_IOU2_TTC_BASE_RESET_MASK 	0x00000800U
+#endif
+
+#if defined (SLEEP_TIMER_BASEADDR)
+/** @name Register Map
+*
+* Register offsets from the base address of the TTC device
+*
+* @{
+*/
+ #define XSLEEP_TIMER_TTC_CLK_CNTRL_OFFSET		0x00000000U
+					     /**< Clock Control Register */
+ #define XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET		0x0000000CU
+	                                     /**< Counter Control Register*/
+ #define XSLEEP_TIMER_TTC_COUNT_VALUE_OFFSET	0x00000018U
+					     /**< Current Counter Value */
+/* @} */
+/** @name Clock Control Register
+* Clock Control Register definitions of TTC
+* @{
+*/
+ #define XSLEEP_TIMER_TTC_CLK_CNTRL_PS_EN_MASK		0x00000001U
+						   /**< Prescale enable */
+/* @} */
+/** @name Counter Control Register
+* Counter Control Register definitions of TTC
+* @{
+*/
+#define XSLEEP_TIMER_TTC_CNT_CNTRL_DIS_MASK		0x00000001U
+						/**< Disable the counter */
+#define XSLEEP_TIMER_TTC_CNT_CNTRL_RST_MASK		0x00000010U
+						  /**< Reset counter */
+/* @} */
+
+/**************************** Type Definitions *******************************/
+
+/************************** Function Prototypes ******************************/
+
+void Xil_SleepTTCCommon(u32 delay, u64 frequency);
+void XTime_StartTTCTimer();
+
+#endif
+#endif /* XIL_SLEEPTIMER_H */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_smc.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_smc.c
new file mode 100644
index 000000000..7d9ee9b9d
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_smc.c
@@ -0,0 +1,110 @@
+/******************************************************************************
+*
+* Copyright (C) 2017 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xil_smc.c
+*
+* This file contains function for initiating SMC call
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 6.2 	pkp  	 02/16/17 First release
+* 

+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+#include "xil_types.h"
+#include "xil_smc.h"
+
+#if EL1_NONSECURE
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Function Prototypes *****************************/
+
+/************************** Variable Definitions *****************************/
+XSmc_OutVar SmcResult;
+
+/*****************************************************************************/
+/**
+* @brief	Initiate SMC call to EL3 secure monitor to request for secure
+*			service. This function is only applicable for EL1 Non-secure bsp.
+*
+* @param	FunctionID is the SMC identifier for a particular secure service
+*			request
+* @param	Arg1 to Arg6 is the arguements passed to EL3 secure monitor
+* @param	Arg7 is Hypervisor Client ID register
+*
+* @return	Result from secure payload service
+* @note		FunctionID and Arg1-Arg7 should be as per SMC calling convention
+*
+******************************************************************************/
+XSmc_OutVar Xil_Smc(u64 FunctionID, u64 Arg1, u64 Arg2, u64 Arg3, u64 Arg4,
+					u64 Arg5, u64 Arg6, u64 Arg7){
+
+	/*
+	 * Since registers x8 to x17 are not saved by secure monitor during SMC
+	 * it must be preserved.
+	 */
+	XSave_X8toX17();
+
+	/* Moving to EL3 secure monitor with smc call. */
+
+	__asm__ __volatile__ ("smc #0x0");
+
+	/*
+	 * The result of the secure services are stored in x0 - x3. They are
+	 * moved to SmcResult to return the result.
+	 */
+	__asm__ __volatile__("mov	x8, x0");
+	__asm__ __volatile__("mov	x9, x1");
+	__asm__ __volatile__("mov	x10, x2");
+	__asm__ __volatile__("mov	x11, x3");
+
+	__asm__ __volatile__("mov	%0, x8" : "=r" (SmcResult.Arg0));
+	__asm__ __volatile__("mov	%0, x9" : "=r" (SmcResult.Arg1));
+	__asm__ __volatile__("mov	%0, x10" : "=r" (SmcResult.Arg2));
+	__asm__ __volatile__("mov	%0, x11" : "=r" (SmcResult.Arg3));
+
+	XRestore_X8toX17();
+
+	return SmcResult;
+}
+#endif
\ No newline at end of file
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_smc.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_smc.h
new file mode 100644
index 000000000..4f0738c1e
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_smc.h
@@ -0,0 +1,118 @@
+/******************************************************************************
+*
+* Copyright (C) 2017 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_smc.h
+*
+* @addtogroup a53_64_smc_api Cortex A53 64bit EL1 Non-secure SMC Call
+*
+* Cortex A53 64bit EL1 Non-secure SMC Call provides a C wrapper for calling
+* SMC from EL1 Non-secure application to request Secure monitor for secure
+* services. SMC calling conventions should be followed.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 6.2 	pkp  	 02/16/17 First release
+* 6.4   mus      08/17/17 Added constant define for SMC ID , which is
+*                         intended to read the version/idcode of the
+*                         platform
+*
+*
+* 

+*
+******************************************************************************/
+
+#ifndef XIL_SMC_H /* prevent circular inclusions */
+#define XIL_SMC_H /* by using protection macros */
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "bspconfig.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#if EL1_NONSECURE
+/************************** Constant Definitions ****************************/
+#define SMC_FID_START	0xF2000000
+#define SMC_FID_END	0xFF00FFFF
+
+#define XILSP_INIT_DONE 0xF2000000
+#define	ARITH_SMC_FID	0xF2000001
+
+#define PM_ASSERT_SMC_FID       0xC2000011
+#define PM_GETSTATUS_SMC_FID    0xC2000012
+#define MMIO_WRITE_SMC_FID	0xC2000013
+#define MMIO_READ_SMC_FID	0xC2000014
+#define GET_CHIPID_SMC_FID      0xC2000018
+/**************************** Type Definitions ******************************/
+typedef struct {
+	u64 Arg0;
+	u64 Arg1;
+	u64 Arg2;
+	u64 Arg3;
+} XSmc_OutVar;
+/***************** Macros (Inline Functions) Definitions ********************/
+
+#define XSave_X8toX17() \
+	__asm__ __volatile__ ("stp X8, X9, [sp,#-0x10]!");\
+	__asm__ __volatile__ ("stp X10, X11, [sp,#-0x10]!");\
+	__asm__ __volatile__ ("stp X12, X13, [sp,#-0x10]!");\
+	__asm__ __volatile__ ("stp X14, X15, [sp,#-0x10]!");\
+	__asm__ __volatile__ ("stp X16, X17, [sp,#-0x10]!");
+
+#define XRestore_X8toX17() \
+	__asm__ __volatile__ ("ldp X16, X17, [sp], #0x10");\
+	__asm__ __volatile__ ("ldp X14, X15, [sp], #0x10");\
+	__asm__ __volatile__ ("ldp X12, X13, [sp], #0x10");\
+	__asm__ __volatile__ ("ldp X10, X11, [sp], #0x10");\
+	__asm__ __volatile__ ("ldp X8, X9, [sp], #0x10");
+
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+XSmc_OutVar Xil_Smc(u64 FunctionID, u64 Arg1, u64 Arg2, u64 Arg3, u64 Arg4,
+					u64 Arg5, u64 Arg6, u64 Arg7);
+#endif
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XIL_SMC_H */
+/**
+* @} End of "addtogroup a53_64_smc_api".
+*/
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_testcache.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_testcache.c
similarity index 83%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_testcache.c
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_testcache.c
index a2c4b0bbf..157ad0836 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_testcache.c
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_testcache.c
@@ -47,7 +47,6 @@
 * 

 *
 * @note
-*
 * This file contain functions that all operate on HAL.
 *
 ******************************************************************************/
@@ -74,17 +73,21 @@ static INTPTR Data[DATA_LENGTH] __attribute__ ((aligned(64)));
 static INTPTR Data[DATA_LENGTH] __attribute__ ((aligned(32)));
 #endif
 
+
+/*****************************************************************************/
 /**
-* Perform DCache range related API test such as Xil_DCacheFlushRange and
-* Xil_DCacheInvalidateRange. This test function writes a constant value
-* to the Data array, flushes the range, writes a new value, then invalidates
-* the corresponding range.
+*
+* @brief    Perform DCache range related API test such as Xil_DCacheFlushRange
+*           and Xil_DCacheInvalidateRange. This test function writes a constant
+*           value to the Data array, flushes the range, writes a new value, then
+*           invalidates the corresponding range.
+* @param	None
 *
 * @return
+*      - -1 is returned for a failure
+*      - 0 is returned for a pass
 *
-*     - 0 is returned for a pass
-*     - -1 is returned for a failure
-*/
+*****************************************************************************/
 s32 Xil_TestDCacheRange(void)
 {
 	s32 Index;
@@ -204,16 +207,17 @@ s32 Xil_TestDCacheRange(void)
 
 }
 
+/*****************************************************************************/
 /**
-* Perform DCache all related API test such as Xil_DCacheFlush and
-* Xil_DCacheInvalidate. This test function writes a constant value
-* to the Data array, flushes the DCache, writes a new value, then invalidates
-* the DCache.
+* @brief    Perform DCache all related API test such as Xil_DCacheFlush and
+*           Xil_DCacheInvalidate. This test function writes a constant value
+*           to the Data array, flushes the DCache, writes a new value,
+*           then invalidates the DCache.
 *
 * @return
-*     - 0 is returned for a pass
-*     - -1 is returned for a failure
-*/
+*          - 0 is returned for a pass
+*          - -1 is returned for a failure
+*****************************************************************************/
 s32 Xil_TestDCacheAll(void)
 {
 	s32 Index;
@@ -328,15 +332,15 @@ s32 Xil_TestDCacheAll(void)
 	return Status;
 }
 
-
+/*****************************************************************************/
 /**
-* Perform Xil_ICacheInvalidateRange() on a few function pointers.
+* @brief   Perform Xil_ICacheInvalidateRange() on a few function pointers.
 *
 * @return
-*
 *     - 0 is returned for a pass
+* @note
 *     The function will hang if it fails.
-*/
+*****************************************************************************/
 s32 Xil_TestICacheRange(void)
 {
 
@@ -349,14 +353,15 @@ s32 Xil_TestICacheRange(void)
 	return 0;
 }
 
+/*****************************************************************************/
 /**
-* Perform Xil_ICacheInvalidate().
+* @brief     Perform Xil_ICacheInvalidate() on a few function pointers.
 *
 * @return
-*
-*     - 0 is returned for a pass
-*     The function will hang if it fails.
-*/
+*           - 0 is returned for a pass
+* @note
+* The function will hang if it fails.
+*****************************************************************************/
 s32 Xil_TestICacheAll(void)
 {
 	Xil_ICacheInvalidate();
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_testcache.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_testcache.h
similarity index 92%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_testcache.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_testcache.h
index b3c416cd0..c35e9a463 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_testcache.h
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_testcache.h
@@ -34,11 +34,16 @@
 *
 * @file xil_testcache.h
 *
-* This file contains utility functions to test cache.
+* @addtogroup common_test_utils
+* 
Cache test 

+* The xil_testcache.h file contains utility functions to test cache.
 *
+* @{
+* 
 * Ver    Who    Date    Changes
 * ----- ---- -------- -----------------------------------------------
 * 1.00a hbm  07/29/09 First release
+* 

 *
 ******************************************************************************/
 
@@ -61,3 +66,6 @@ extern s32 Xil_TestICacheAll(void);
 #endif
 
 #endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_test_utils".
+*/
\ No newline at end of file
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_testio.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_testio.c
similarity index 70%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_testio.c
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_testio.c
index a68d7652f..e6a36807b 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_testio.c
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_testio.c
@@ -32,7 +32,7 @@
 /*****************************************************************************/
 /**
 *
-* @file xil_testmemend.c
+* @file xil_testio.c
 *
 * Contains the memory test utility functions.
 *
@@ -95,18 +95,17 @@ static u32 Swap32(u32 Data)
 /*****************************************************************************/
 /**
 *
-* Perform a destructive 8-bit wide register IO test where the register is
-* accessed using Xil_Out8 and Xil_In8, and comparing the reading and writing
-* values.
+* @brief    Perform a destructive 8-bit wide register IO test where the
+*           register is accessed using Xil_Out8 and Xil_In8, and comparing
+*           the written values by reading them back.
 *
-* @param	Addr is a pointer to the region of memory to be tested.
-* @param	Length is the Length of the block.
-* @param	Value is the constant used for writting the memory.
+* @param	Addr: a pointer to the region of memory to be tested.
+* @param	Length: Length of the block.
+* @param	Value: constant used for writting the memory.
 *
 * @return
-*
-* - -1 is returned for a failure
-* - 0 is returned for a pass
+*           - -1 is returned for a failure
+*           - 0 is returned for a pass
 *
 *****************************************************************************/
 
@@ -133,24 +132,24 @@ s32 Xil_TestIO8(u8 *Addr, s32 Length, u8 Value)
 /*****************************************************************************/
 /**
 *
-* Perform a destructive 16-bit wide register IO test. Each location is tested
-* by sequentially writing a 16-bit wide register, reading the register, and
-* comparing value. This function tests three kinds of register IO functions,
-* normal register IO, little-endian register IO, and big-endian register IO.
-* When testing little/big-endian IO, the function performs the following
-* sequence, Xil_Out16LE/Xil_Out16BE, Xil_In16, Compare In-Out values,
-* Xil_Out16, Xil_In16LE/Xil_In16BE, Compare In-Out values. Whether to swap the
-* read-in value before comparing is controlled by the 5th argument.
+* @brief   Perform a destructive 16-bit wide register IO test. Each location
+*          is tested by sequentially writing a 16-bit wide register, reading
+*          the register, and comparing value. This function tests three kinds
+*          of register IO functions, normal register IO, little-endian register
+*          IO, and big-endian register IO. When testing little/big-endian IO,
+*          the function performs the following sequence, Xil_Out16LE/Xil_Out16BE,
+*          Xil_In16, Compare In-Out values, Xil_Out16, Xil_In16LE/Xil_In16BE,
+*          Compare In-Out values. Whether to swap the read-in value before
+*          comparing is controlled by the 5th argument.
 *
-* @param	Addr is a pointer to the region of memory to be tested.
-* @param	Length is the Length of the block.
-* @param	Value is the constant used for writting the memory.
-* @param	Kind is the test kind. Acceptable values are:
-*		XIL_TESTIO_DEFAULT, XIL_TESTIO_LE, XIL_TESTIO_BE.
-* @param	Swap indicates whether to byte swap the read-in value.
+* @param	Addr: a pointer to the region of memory to be tested.
+* @param	Length: Length of the block.
+* @param	Value: constant used for writting the memory.
+* @param	Kind: Type of test. Acceptable values are:
+*		    XIL_TESTIO_DEFAULT, XIL_TESTIO_LE, XIL_TESTIO_BE.
+* @param	Swap: indicates whether to byte swap the read-in value.
 *
 * @return
-*
 * - -1 is returned for a failure
 * - 0 is returned for a pass
 *
@@ -219,26 +218,25 @@ s32 Xil_TestIO16(u16 *Addr, s32 Length, u16 Value, s32 Kind, s32 Swap)
 /*****************************************************************************/
 /**
 *
-* Perform a destructive 32-bit wide register IO test. Each location is tested
-* by sequentially writing a 32-bit wide regsiter, reading the register, and
-* comparing value. This function tests three kinds of register IO functions,
-* normal register IO, little-endian register IO, and big-endian register IO.
-* When testing little/big-endian IO, the function perform the following
-* sequence, Xil_Out32LE/Xil_Out32BE, Xil_In32, Compare,
-* Xil_Out32, Xil_In32LE/Xil_In32BE, Compare. Whether to swap the read-in value
-* before comparing is controlled by the 5th argument.
-*
-* @param	Addr is a pointer to the region of memory to be tested.
-* @param	Length is the Length of the block.
-* @param	Value is the constant used for writting the memory.
-* @param	Kind is the test kind. Acceptable values are:
-*		XIL_TESTIO_DEFAULT, XIL_TESTIO_LE, XIL_TESTIO_BE.
-* @param	Swap indicates whether to byte swap the read-in value.
+* @brief    Perform a destructive 32-bit wide register IO test. Each location
+*           is tested by sequentially writing a 32-bit wide regsiter, reading
+*           the register, and comparing value. This function tests three kinds
+*           of register IO functions, normal register IO, little-endian register IO,
+*           and big-endian register IO. When testing little/big-endian IO,
+*           the function perform the following sequence, Xil_Out32LE/
+*           Xil_Out32BE, Xil_In32, Compare, Xil_Out32, Xil_In32LE/Xil_In32BE, Compare.
+*           Whether to swap the read-in value *before comparing is controlled
+*           by the 5th argument.
+* @param	Addr: a pointer to the region of memory to be tested.
+* @param	Length: Length of the block.
+* @param	Value: constant used for writting the memory.
+* @param	Kind: type of test. Acceptable values are:
+*		    XIL_TESTIO_DEFAULT, XIL_TESTIO_LE, XIL_TESTIO_BE.
+* @param	Swap: indicates whether to byte swap the read-in value.
 *
 * @return
-*
-* - -1 is returned for a failure
-* - 0 is returned for a pass
+*           - -1 is returned for a failure
+*           - 0 is returned for a pass
 *
 *****************************************************************************/
 s32 Xil_TestIO32(u32 *Addr, s32 Length, u32 Value, s32 Kind, s32 Swap)
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_testio.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_testio.h
similarity index 93%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_testio.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_testio.h
index fba0c1060..ad68ead64 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_testio.h
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_testio.h
@@ -32,19 +32,19 @@
 /*****************************************************************************/
 /**
 *
-* @file xil_testmemend.h
+* @file xil_testio.h
 *
-* This file contains utility functions to teach endian related memory
+* @addtogroup common_test_utils Test Utilities
+* 
I/O test 

+* The xil_testio.h file contains utility functions to test endian related memory
 * IO functions.
 *
-* Memory test description
-*
 * A subset of the memory tests can be selected or all of the tests can be run
 * in order. If there is an error detected by a subtest, the test stops and the
 * failure code is returned. Further tests are not run even if all of the tests
 * are selected.
 *
-*
+* @{
 * 
 * MODIFICATION HISTORY:
 *
@@ -89,3 +89,6 @@ extern s32 Xil_TestIO32(u32 *Addr, s32 Length, u32 Value, s32 Kind, s32 Swap);
 #endif
 
 #endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_test_utils".
+*/
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xil_testmem.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_testmem.c
similarity index 92%
rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xil_testmem.c
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_testmem.c
index 19a3b6608..87426d17a 100644
--- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xil_testmem.c
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_testmem.c
@@ -66,22 +66,20 @@ static u32 RotateRight(u32 Input, u8 Width);
 /*****************************************************************************/
 /**
 *
-* Perform a destructive 32-bit wide memory test.
+* @brief    Perform a destructive 32-bit wide memory test.
 *
-* @param    Addr is a pointer to the region of memory to be tested.
-* @param    Words is the length of the block.
-* @param    Pattern is the constant used for the constant pattern test, if 0,
+* @param    Addr: pointer to the region of memory to be tested.
+* @param    Words: length of the block.
+* @param    Pattern: constant used for the constant pattern test, if 0,
 *           0xDEADBEEF is used.
-* @param    Subtest is the test selected. See xil_testmem.h for possible
-*	    values.
+* @param    Subtest: test type selected. See xil_testmem.h for possible
+*	        values.
 *
 * @return
-*
-* - 0 is returned for a pass
-* - -1 is returned for a failure
+*           - 0 is returned for a pass
+*           - 1 is returned for a failure
 *
 * @note
-*
 * Used for spaces where the address range of the region is smaller than
 * the data width. If the memory range is greater than 2 ** Width,
 * the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
@@ -315,22 +313,21 @@ End_Label:
 /*****************************************************************************/
 /**
 *
-* Perform a destructive 16-bit wide memory test.
+* @brief    Perform a destructive 16-bit wide memory test.
 *
-* @param    Addr is a pointer to the region of memory to be tested.
-* @param    Words is the length of the block.
-* @param    Pattern is the constant used for the constant Pattern test, if 0,
+* @param    Addr: pointer to the region of memory to be tested.
+* @param    Words: length of the block.
+* @param    Pattern: constant used for the constant Pattern test, if 0,
 *           0xDEADBEEF is used.
-* @param    Subtest is the test selected. See xil_testmem.h for possible
-*	    values.
+* @param    Subtest: type of test selected. See xil_testmem.h for possible
+*	        values.
 *
 * @return
 *
-* - -1 is returned for a failure
-* - 0 is returned for a pass
+*           - -1 is returned for a failure
+*           - 0 is returned for a pass
 *
 * @note
-*
 * Used for spaces where the address range of the region is smaller than
 * the data width. If the memory range is greater than 2 ** Width,
 * the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
@@ -549,22 +546,20 @@ End_Label:
 /*****************************************************************************/
 /**
 *
-* Perform a destructive 8-bit wide memory test.
+* @brief    Perform a destructive 8-bit wide memory test.
 *
-* @param    Addr is a pointer to the region of memory to be tested.
-* @param    Words is the length of the block.
-* @param    Pattern is the constant used for the constant pattern test, if 0,
+* @param    Addr: pointer to the region of memory to be tested.
+* @param    Words: length of the block.
+* @param    Pattern: constant used for the constant pattern test, if 0,
 *           0xDEADBEEF is used.
-* @param    Subtest is the test selected. See xil_testmem.h for possible
-*	    values.
+* @param    Subtest: type of test selected. See xil_testmem.h for possible
+*	        values.
 *
 * @return
-*
-* - -1 is returned for a failure
-* - 0 is returned for a pass
+*           - -1 is returned for a failure
+*           - 0 is returned for a pass
 *
 * @note
-*
 * Used for spaces where the address range of the region is smaller than
 * the data width. If the memory range is greater than 2 ** Width,
 * the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
@@ -777,18 +772,14 @@ End_Label:
 /*****************************************************************************/
 /**
 *
-* Rotates the provided value to the left one bit position
+* @brief   Rotates the provided value to the left one bit position
 *
 * @param    Input is value to be rotated to the left
 * @param    Width is the number of bits in the input data
 *
 * @return
+*           The resulting unsigned long value of the rotate left
 *
-* The resulting unsigned long value of the rotate left
-*
-* @note
-*
-* None.
 *
 *****************************************************************************/
 static u32 RotateLeft(u32 Input, u8 Width)
@@ -831,18 +822,13 @@ static u32 RotateLeft(u32 Input, u8 Width)
 /*****************************************************************************/
 /**
 *
-* Rotates the provided value to the right one bit position
+* @brief    Rotates the provided value to the right one bit position
 *
-* @param    Input is value to be rotated to the right
-* @param    Width is the number of bits in the input data
+* @param    Input: value to be rotated to the right
+* @param    Width: number of bits in the input data
 *
 * @return
-*
-* The resulting u32 value of the rotate right
-*
-* @note
-*
-* None.
+*           The resulting u32 value of the rotate right
 *
 *****************************************************************************/
 static u32 RotateRight(u32 Input, u8 Width)
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_testmem.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_testmem.h
similarity index 79%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_testmem.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_testmem.h
index 4cbfd878b..c20472822 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_testmem.h
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_testmem.h
@@ -33,64 +33,57 @@
 /**
 *
 * @file xil_testmem.h
+* @addtogroup common_test_utils
 *
-* This file contains utility functions to test memory.
-*
-* Memory test description
+* 
Memory test

 *
+* The xil_testmem.h file contains utility functions to test memory.
 * A subset of the memory tests can be selected or all of the tests can be run
 * in order. If there is an error detected by a subtest, the test stops and the
 * failure code is returned. Further tests are not run even if all of the tests
 * are selected.
+* Following list describes the supported memory tests:
 *
-* Subtest descriptions:
-* 
-* XIL_TESTMEM_ALLMEMTESTS:
-*       Runs all of the following tests
+*  - XIL_TESTMEM_ALLMEMTESTS: This test runs all of the subtests.
 *
-* XIL_TESTMEM_INCREMENT:
-*       Incrementing Value Test.
-*       This test starts at 'XIL_TESTMEM_INIT_VALUE' and uses the
-*	incrementing value as the test value for memory.
+*  - XIL_TESTMEM_INCREMENT: This test
+* starts at 'XIL_TESTMEM_INIT_VALUE' and uses the incrementing value as the
+* test value for memory.
 *
-* XIL_TESTMEM_WALKONES:
-*       Walking Ones Test.
-*       This test uses a walking '1' as the test value for memory.
-*       location 1 = 0x00000001
-*       location 2 = 0x00000002
-*       ...
+*  - XIL_TESTMEM_WALKONES: Also known as the Walking ones test. This test
+* uses a walking '1' as the test value for memory.
+* @code
+*          location 1 = 0x00000001
+*          location 2 = 0x00000002
+*          ...
+* @endcode
 *
-* XIL_TESTMEM_WALKZEROS:
-*       Walking Zero's Test.
-*       This test uses the inverse value of the walking ones test
-*       as the test value for memory.
+*  - XIL_TESTMEM_WALKZEROS: Also known as the Walking zero's test.
+* This test uses the inverse value of the walking ones test
+* as the test value for memory.
+* @code
 *       location 1 = 0xFFFFFFFE
 *       location 2 = 0xFFFFFFFD
 *       ...
+*@endcode
 *
-* XIL_TESTMEM_INVERSEADDR:
-*       Inverse Address Test.
-*       This test uses the inverse of the address of the location under test
-*       as the test value for memory.
+*  - XIL_TESTMEM_INVERSEADDR: Also known as the inverse address test.
+* This test uses the inverse of the address of the location under test
+* as the test value for memory.
 *
-* XIL_TESTMEM_FIXEDPATTERN:
-*       Fixed Pattern Test.
-*       This test uses the provided patters as the test value for memory.
-*       If zero is provided as the pattern the test uses '0xDEADBEEF".
-* 

-*
-* WARNING
+*  - XIL_TESTMEM_FIXEDPATTERN: Also known as the fixed pattern test.
+* This test uses the provided patters as the test value for memory.
+* If zero is provided as the pattern the test uses '0xDEADBEEF".
 *
+* @warning
 * The tests are DESTRUCTIVE. Run before any initialized memory spaces
 * have been set up.
-*
 * The address provided to the memory tests is not checked for
 * validity except for the NULL case. It is possible to provide a code-space
 * pointer for this test to start with and ultimately destroy executable code
 * causing random failures.
 *
 * @note
-*
 * Used for spaces where the address range of the region is smaller than
 * the data width. If the memory range is greater than 2 ** width,
 * the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
@@ -160,3 +153,6 @@ extern s32 Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest);
 #endif
 
 #endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_test_utils".
+*/
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_types.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_types.h
similarity index 76%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_types.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_types.h
index e8b78b7c6..8143aff1e 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_types.h
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xil_types.h
@@ -34,9 +34,11 @@
 *
 * @file xil_types.h
 *
-* This file contains basic types for Xilinx software IP.
-
+* @addtogroup common_types Basic Data types for Xilinx® Software IP
 *
+* The xil_types.h file contains basic types for Xilinx software IP. These data types
+* are applicable for all processors supported by Xilinx.
+* @{
 * 
 * MODIFICATION HISTORY:
 *
@@ -71,22 +73,28 @@
 #define NULL		0U
 #endif
 
-#define XIL_COMPONENT_IS_READY     0x11111111U  /**< component has been initialized */
-#define XIL_COMPONENT_IS_STARTED   0x22222222U  /**< component has been started */
+#define XIL_COMPONENT_IS_READY     0x11111111U  /**< In device drivers, This macro will be
+                                                 assigend to "IsReady" member of driver
+												 instance to indicate that driver
+												 instance is initialized and ready to use. */
+#define XIL_COMPONENT_IS_STARTED   0x22222222U  /**< In device drivers, This macro will be assigend to
+                                                 "IsStarted" member of driver instance
+												 to indicate that driver instance is
+												 started and it can be enabled. */
 
-/** @name New types
+/* @name New types
  * New simple types.
  * @{
  */
 #ifndef __KERNEL__
 #ifndef XBASIC_TYPES_H
-/**
+/*
  * guarded against xbasic_types.h.
  */
 typedef uint8_t u8;
 typedef uint16_t u16;
 typedef uint32_t u32;
-
+/** @}*/
 #define __XUINT64__
 typedef struct
 {
@@ -97,36 +105,32 @@ typedef struct
 
 /*****************************************************************************/
 /**
-* Return the most significant half of the 64 bit data type.
+* @brief    Return the most significant half of the 64 bit data type.
 *
 * @param    x is the 64 bit word.
 *
 * @return   The upper 32 bits of the 64 bit word.
 *
-* @note     None.
-*
 ******************************************************************************/
 #define XUINT64_MSW(x) ((x).Upper)
 
 /*****************************************************************************/
 /**
-* Return the least significant half of the 64 bit data type.
+* @brief    Return the least significant half of the 64 bit data type.
 *
 * @param    x is the 64 bit word.
 *
 * @return   The lower 32 bits of the 64 bit word.
 *
-* @note     None.
-*
 ******************************************************************************/
 #define XUINT64_LSW(x) ((x).Lower)
 
 #endif /* XBASIC_TYPES_H */
 
-/**
+/*
  * xbasic_types.h does not typedef s* or u64
  */
-
+/** @{ */
 typedef char char8;
 typedef int8_t s8;
 typedef int16_t s16;
@@ -138,7 +142,7 @@ typedef int sint32;
 typedef intptr_t INTPTR;
 typedef uintptr_t UINTPTR;
 typedef ptrdiff_t PTRDIFF;
-
+/** @}*/
 #if !defined(LONG) || !defined(ULONG)
 typedef long LONG;
 typedef unsigned long ULONG;
@@ -151,7 +155,7 @@ typedef unsigned long ULONG;
 #include 
 #endif
 
-
+/** @{ */
 /**
  * This data type defines an interrupt handler for a device.
  * The argument points to the instance of the component
@@ -165,22 +169,24 @@ typedef void (*XInterruptHandler) (void *InstancePtr);
 typedef void (*XExceptionHandler) (void *InstancePtr);
 
 /**
- * UPPER_32_BITS - return bits 32-63 of a number
- * @n: the number we're accessing
+ * @brief  Returns 32-63 bits of a number.
+ * @param  n : Number being accessed.
+ * @return Bits 32-63 of number.
  *
- * A basic shift-right of a 64- or 32-bit quantity.  Use this to suppress
- * the "right shift count >= width of type" warning when that quantity is
- * 32-bits.
+ * @note    A basic shift-right of a 64- or 32-bit quantity.
+ *          Use this to suppress the "right shift count >= width of type"
+ *          warning when that quantity is 32-bits.
  */
 #define UPPER_32_BITS(n) ((u32)(((n) >> 16) >> 16))
 
 /**
- * LOWER_32_BITS - return bits 0-31 of a number
- * @n: the number we're accessing
+ * @brief  Returns 0-31 bits of a number
+ * @param  n : Number being accessed.
+ * @return Bits 0-31 of number
  */
 #define LOWER_32_BITS(n) ((u32)(n))
 
-/*@}*/
+
 
 
 /************************** Constant Definitions *****************************/
@@ -198,3 +204,6 @@ typedef void (*XExceptionHandler) (void *InstancePtr);
 #endif
 
 #endif	/* end of protection macro */
+/**
+* @} End of "addtogroup common_types".
+*/
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xparameters_ps.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xparameters_ps.h
similarity index 91%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xparameters_ps.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xparameters_ps.h
index 708160962..a19e172e5 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xparameters_ps.h
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xparameters_ps.h
@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2014 - 2017 Xilinx, Inc. All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
@@ -57,6 +57,9 @@
 extern "C" {
 #endif
 
+/***************************** Include Files *********************************/
+
+
 /************************** Constant Definitions *****************************/
 
 /*
@@ -114,6 +117,15 @@ extern "C" {
 #define XPAR_XADMAPS_6_INTR 		XPS_ADMA_CH6_INT_ID
 #define XPAR_XADMAPS_7_INTR 		XPS_ADMA_CH7_INT_ID
 #define XPAR_XCSUDMA_INTR 		XPS_CSU_DMA_INT_ID
+#define XPAR_PSU_ADMA_0_INTR 		XPS_ADMA_CH0_INT_ID
+#define XPAR_PSU_ADMA_1_INTR 		XPS_ADMA_CH1_INT_ID
+#define XPAR_PSU_ADMA_2_INTR		XPS_ADMA_CH2_INT_ID
+#define XPAR_PSU_ADMA_3_INTR 		XPS_ADMA_CH3_INT_ID
+#define XPAR_PSU_ADMA_4_INTR		XPS_ADMA_CH4_INT_ID
+#define XPAR_PSU_ADMA_5_INTR 		XPS_ADMA_CH5_INT_ID
+#define XPAR_PSU_ADMA_6_INTR 		XPS_ADMA_CH6_INT_ID
+#define XPAR_PSU_ADMA_7_INTR 		XPS_ADMA_CH7_INT_ID
+#define XPAR_PSU_CSUDMA_INTR 		XPS_CSU_DMA_INT_ID
 #define XPAR_XMPU_LPD_INTR 		XPS_XMPU_LPD_INT_ID
 #define XPAR_XZDMAPS_0_INTR		XPS_ZDMA_CH0_INT_ID
 #define XPAR_XZDMAPS_1_INTR		XPS_ZDMA_CH1_INT_ID
@@ -123,11 +135,21 @@ extern "C" {
 #define XPAR_XZDMAPS_5_INTR 		XPS_ZDMA_CH5_INT_ID
 #define XPAR_XZDMAPS_6_INTR 		XPS_ZDMA_CH6_INT_ID
 #define XPAR_XZDMAPS_7_INTR 		XPS_ZDMA_CH7_INT_ID
+#define XPAR_PSU_GDMA_0_INTR		XPS_ZDMA_CH0_INT_ID
+#define XPAR_PSU_GDMA_1_INTR		XPS_ZDMA_CH1_INT_ID
+#define XPAR_PSU_GDMA_2_INTR 		XPS_ZDMA_CH2_INT_ID
+#define XPAR_PSU_GDMA_3_INTR 		XPS_ZDMA_CH3_INT_ID
+#define XPAR_PSU_GDMA_4_INTR		XPS_ZDMA_CH4_INT_ID
+#define XPAR_PSU_GDMA_5_INTR 		XPS_ZDMA_CH5_INT_ID
+#define XPAR_PSU_GDMA_6_INTR 		XPS_ZDMA_CH6_INT_ID
+#define XPAR_PSU_GDMA_7_INTR 		XPS_ZDMA_CH7_INT_ID
 #define XPAR_XMPU_FPD_INTR 		XPS_XMPU_FPD_INT_ID
 #define XPAR_XCCI_FPD_INTR 		XPS_FPD_CCI_INT_ID
 #define XPAR_XSMMU_FPD_INTR 		XPS_FPD_SMMU_INT_ID
 #define XPAR_XUSBPS_0_INTR		XPS_USB3_0_ENDPT_INT_ID
 #define XPAR_XUSBPS_1_INTR		XPS_USB3_1_ENDPT_INT_ID
+#define XPAR_XUSBPS_0_WAKE_INTR		XPS_USB3_0_WAKE_INT_ID
+#define XPAR_XUSBPS_1_WAKE_INTR		XPS_USB3_1_WAKE_INT_ID
 #define	XPAR_XRTCPSU_ALARM_INTR 	XPS_RTC_ALARM_INT_ID
 #define	XPAR_XRTCPSU_SECONDS_INTR	XPS_RTC_SEC_INT_ID
 #define XPAR_XAPMPS_0_INTR		XPS_APM0_INT_ID
@@ -217,6 +239,8 @@ extern "C" {
 #define XPS_GEM3_WAKE_INT_ID		(64U + 32U)
 #define XPS_USB3_0_ENDPT_INT_ID		(65U + 32U)
 #define XPS_USB3_1_ENDPT_INT_ID		(70U + 32U)
+#define XPS_USB3_0_WAKE_INT_ID		(75U + 32U)
+#define XPS_USB3_1_WAKE_INT_ID		(76U + 32U)
 #define XPS_ADMA_CH0_INT_ID		(77U + 32U)
 #define XPS_ADMA_CH1_INT_ID		(78U + 32U)
 #define XPS_ADMA_CH2_INT_ID		(79U + 32U)
@@ -279,6 +303,7 @@ extern "C" {
 #define XPAR_PSU_TTC_9_INTR			XPS_TTC3_0_INT_ID
 #define XPAR_PSU_TTC_10_INTR		XPS_TTC3_1_INT_ID
 #define XPAR_PSU_TTC_11_INTR		XPS_TTC3_2_INT_ID
+#define XPAR_PSU_AMS_INTR			XPS_AMS_INT_ID
 
 #define XPAR_XADCPS_NUM_INSTANCES 1U
 #define XPAR_XADCPS_0_DEVICE_ID   0U
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xplatform_info.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xplatform_info.c
similarity index 73%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xplatform_info.c
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xplatform_info.c
index 9d4560a98..2c08e5f2e 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xplatform_info.c
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xplatform_info.c
@@ -45,6 +45,13 @@
 * 5.04  pkp  01/12/16 Added platform information support for Cortex-A53 32bit
 *					  mode
 * 6.00  mus  17/08/16 Removed unused variable from XGetPlatform_Info
+* 6.4   ms   05/23/17 Added PSU_PMU macro to support XGetPSVersion_Info
+*                     function for PMUFW.
+*       ms   06/13/17 Added PSU_PMU macro to provide support of
+*                     XGetPlatform_Info function for PMUFW.
+*       mus  08/17/17 Add EL1 NS mode support for
+*                     XGet_Zynq_UltraMp_Platform_info and XGetPSVersion_Info
+*                     APIs.
 * 

 *
 ******************************************************************************/
@@ -54,7 +61,10 @@
 #include "xil_types.h"
 #include "xil_io.h"
 #include "xplatform_info.h"
-
+#if defined (__aarch64__)
+#include "bspconfig.h"
+#include "xil_smc.h"
+#endif
 /************************** Constant Definitions *****************************/
 
 /**************************** Type Definitions *******************************/
@@ -69,19 +79,17 @@
 /*****************************************************************************/
 /**
 *
-* This API is used to provide information about platform
+* @brief    This API is used to provide information about platform
 *
 * @param    None.
 *
 * @return   The information about platform defined in xplatform_info.h
 *
-* @note     None.
-*
 ******************************************************************************/
 u32 XGetPlatform_Info()
 {
 
-#if defined (ARMR5) || (__aarch64__) || (ARMA53_32)
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) || (PSU_PMU)
 	return XPLAT_ZYNQ_ULTRA_MP;
 #elif (__microblaze__)
 	return XPLAT_MICROBLAZE;
@@ -93,43 +101,61 @@ u32 XGetPlatform_Info()
 /*****************************************************************************/
 /**
 *
-* This API is used to provide information about zynq ultrascale MP platform
+* @brief    This API is used to provide information about zynq ultrascale MP platform
 *
 * @param    None.
 *
 * @return   The information about zynq ultrascale MP platform defined in
 *			xplatform_info.h
 *
-* @note     None.
-*
 ******************************************************************************/
 #if defined (ARMR5) || (__aarch64__) || (ARMA53_32)
 u32 XGet_Zynq_UltraMp_Platform_info()
 {
+#if EL1_NONSECURE
+	XSmc_OutVar reg;
+    /*
+	 * This SMC call will return,
+     *  idcode - upper 32 bits of reg.Arg0
+     *  version - lower 32 bits of reg.Arg1
+	 */
+	reg = Xil_Smc(GET_CHIPID_SMC_FID,0,0, 0, 0, 0, 0, 0);
+	return (u32)((reg.Arg1 >> XPLAT_INFO_SHIFT) & XPLAT_INFO_MASK);
+#else
 	u32 reg;
 	reg = ((Xil_In32(XPAR_CSU_BASEADDR + XPAR_CSU_VER_OFFSET) >> 12U )& XPLAT_INFO_MASK);
 	return reg;
+#endif
 }
 #endif
 
 /*****************************************************************************/
 /**
 *
-* This API is used to provide information about PS Silicon version
+* @brief    This API is used to provide information about PS Silicon version
 *
 * @param    None.
 *
 * @return   The information about PS Silicon version.
 *
-* @note     None.
-*
 ******************************************************************************/
-#if defined (ARMR5) || (__aarch64__) || (ARMA53_32)
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) || (PSU_PMU)
 u32 XGetPSVersion_Info()
 {
+#if EL1_NONSECURE
+        /*
+         * This SMC call will return,
+         *  idcode - upper 32 bits of reg.Arg0
+         *  version - lower 32 bits of reg.Arg1
+         */
+        XSmc_OutVar reg;
+        reg = Xil_Smc(GET_CHIPID_SMC_FID,0,0, 0, 0, 0, 0, 0);
+        return (u32)(reg.Arg1 &  XPS_VERSION_INFO_MASK);
+#else
 	u32 reg;
 	reg = (Xil_In32(XPAR_CSU_BASEADDR + XPAR_CSU_VER_OFFSET)
 			& XPS_VERSION_INFO_MASK);
 	return reg;
+#endif
 }
 #endif
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xplatform_info.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xplatform_info.h
similarity index 80%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xplatform_info.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xplatform_info.h
index 7028a83af..0582222bc 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xplatform_info.h
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xplatform_info.h
@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2014 - 2015 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2014 - 2017 Xilinx, Inc.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
@@ -34,7 +34,21 @@
 *
 * @file xplatform_info.h
 *
-* This file contains definitions for various platforms available
+* @addtogroup common_platform_info APIs to Get Platform Information
+*
+* The xplatform_info.h file contains definitions for various available Xilinx®
+* platforms. Also, it contains prototype of APIs, which can be used to get the
+* platform information.
+*
+* @{
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date    Changes
+* ----- ---- --------- -------------------------------------------------------
+* 6.4    ms   05/23/17 Added PSU_PMU macro to support XGetPSVersion_Info
+*                      function for PMUFW.
+* 

 *
 ******************************************************************************/
 
@@ -65,6 +79,7 @@ extern "C" {
 #define XPS_VERSION_2 0x1
 
 #define XPLAT_INFO_MASK (0xF)
+#define XPLAT_INFO_SHIFT (0xC)
 #define XPS_VERSION_INFO_MASK (0xF)
 
 /**************************** Type Definitions *******************************/
@@ -74,7 +89,7 @@ extern "C" {
 
 u32 XGetPlatform_Info();
 
-#if defined (ARMR5) || (__aarch64__) || (ARMA53_32)
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) || (PSU_PMU)
 u32 XGetPSVersion_Info();
 #endif
 
@@ -89,3 +104,6 @@ u32 XGet_Zynq_UltraMp_Platform_info();
 #endif
 
 #endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_platform_info".
+*/
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xpseudo_asm.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xpseudo_asm.h
similarity index 74%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xpseudo_asm.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xpseudo_asm.h
index 29862f251..48e180ef9 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xpseudo_asm.h
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xpseudo_asm.h
@@ -34,7 +34,20 @@
 *
 * @file xpseudo_asm.h
 *
-* This header file contains macros for using inline assembler code.
+* @addtogroup a53_64_specific Cortex A53 64bit Processor Specific Include Files
+*
+* The xpseudo_asm.h includes xreg_cortexa53.h and xpseudo_asm_gcc.h.
+* The xreg_cortexa53.h file contains definitions for inline assembler code.
+* It provides inline definitions for Cortex A53 GPRs, SPRs and floating point
+* registers.
+*
+* The xpseudo_asm_gcc.h contains the definitions for the most often used inline
+* assembler instructions, available as macros. These can be very useful for
+* tasks such as setting or getting special purpose registers, synchronization,
+* or cache manipulation etc. These inline assembler instructions can be used
+* from drivers and user applications written in C.
+*
+* @{
 *
 * 
 * MODIFICATION HISTORY:
@@ -51,3 +64,6 @@
 #include "xpseudo_asm_gcc.h"
 
 #endif /* XPSEUDO_ASM_H */
+/**
+* @} End of "addtogroup a53_64_specific".
+*/
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xpseudo_asm_gcc.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xpseudo_asm_gcc.h
similarity index 97%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xpseudo_asm_gcc.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xpseudo_asm_gcc.h
index b475c90e7..1b6726394 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xpseudo_asm_gcc.h
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xpseudo_asm_gcc.h
@@ -71,7 +71,7 @@ extern "C" {
 
 #if defined (__aarch64__)
 /* pseudo assembler instructions */
-#define mfcpsr()	({u32 rval; \
+#define mfcpsr()	({u32 rval = 0U; \
 			   asm volatile("mrs %0,  DAIF" : "=r" (rval));\
 			  rval;\
 			 })
@@ -123,7 +123,7 @@ extern "C" {
 #else
 
 /* pseudo assembler instructions */
-#define mfcpsr()	({u32 rval; \
+#define mfcpsr()	({u32 rval = 0U; \
 			  __asm__ __volatile__(\
 			    "mrs	%0, cpsr\n"\
 			    : "=r" (rval)\
@@ -215,7 +215,7 @@ extern "C" {
 #define mtcptlbi(reg)	__asm__ __volatile__("tlbi " #reg)
 #define mtcpat(reg,val)	__asm__ __volatile__("at " #reg ",%0"  : : "r" (val))
 /* CP15 operations */
-#define mfcp(reg)	({u64 rval;\
+#define mfcp(reg)	({u64 rval = 0U;\
 			__asm__ __volatile__("mrs	%0, " #reg : "=r" (rval));\
 			rval;\
 			})
@@ -229,7 +229,7 @@ extern "C" {
 			 : : "r" (v)\
 			);
 
-#define mfcp(rn)	({u32 rval; \
+#define mfcp(rn)	({u32 rval = 0U; \
 			 __asm__ __volatile__(\
 			   "mrc " rn "\n"\
 			   : "=r" (rval)\
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xreg_cortexa53.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xreg_cortexa53.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xreg_cortexa53.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xreg_cortexa53.h
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xstatus.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xstatus.h
new file mode 100644
index 000000000..993747588
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xstatus.h
@@ -0,0 +1,535 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xstatus.h
+*
+* @addtogroup common_status_codes Xilinx® software status codes
+*
+* The xstatus.h file contains the Xilinx® software status codes.These codes are
+* used throughout the Xilinx device drivers.
+*
+* @{
+******************************************************************************/
+
+#ifndef XSTATUS_H		/* prevent circular inclusions */
+#define XSTATUS_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+
+/************************** Constant Definitions *****************************/
+
+/*********************** Common statuses 0 - 500 *****************************/
+/**
+@name Common Status Codes for All Device Drivers
+@{
+*/
+#define XST_SUCCESS                     0L
+#define XST_FAILURE                     1L
+#define XST_DEVICE_NOT_FOUND            2L
+#define XST_DEVICE_BLOCK_NOT_FOUND      3L
+#define XST_INVALID_VERSION             4L
+#define XST_DEVICE_IS_STARTED           5L
+#define XST_DEVICE_IS_STOPPED           6L
+#define XST_FIFO_ERROR                  7L	/*!< An error occurred during an
+						   operation with a FIFO such as
+						   an underrun or overrun, this
+						   error requires the device to
+						   be reset */
+#define XST_RESET_ERROR                 8L	/*!< An error occurred which requires
+						   the device to be reset */
+#define XST_DMA_ERROR                   9L	/*!< A DMA error occurred, this error
+						   typically requires the device
+						   using the DMA to be reset */
+#define XST_NOT_POLLED                  10L	/*!< The device is not configured for
+						   polled mode operation */
+#define XST_FIFO_NO_ROOM                11L	/*!< A FIFO did not have room to put
+						   the specified data into */
+#define XST_BUFFER_TOO_SMALL            12L	/*!< The buffer is not large enough
+						   to hold the expected data */
+#define XST_NO_DATA                     13L	/*!< There was no data available */
+#define XST_REGISTER_ERROR              14L	/*!< A register did not contain the
+						   expected value */
+#define XST_INVALID_PARAM               15L	/*!< An invalid parameter was passed
+						   into the function */
+#define XST_NOT_SGDMA                   16L	/*!< The device is not configured for
+						   scatter-gather DMA operation */
+#define XST_LOOPBACK_ERROR              17L	/*!< A loopback test failed */
+#define XST_NO_CALLBACK                 18L	/*!< A callback has not yet been
+						   registered */
+#define XST_NO_FEATURE                  19L	/*!< Device is not configured with
+						   the requested feature */
+#define XST_NOT_INTERRUPT               20L	/*!< Device is not configured for
+						   interrupt mode operation */
+#define XST_DEVICE_BUSY                 21L	/*!< Device is busy */
+#define XST_ERROR_COUNT_MAX             22L	/*!< The error counters of a device
+						   have maxed out */
+#define XST_IS_STARTED                  23L	/*!< Used when part of device is
+						   already started i.e.
+						   sub channel */
+#define XST_IS_STOPPED                  24L	/*!< Used when part of device is
+						   already stopped i.e.
+						   sub channel */
+#define XST_DATA_LOST                   26L	/*!< Driver defined error */
+#define XST_RECV_ERROR                  27L	/*!< Generic receive error */
+#define XST_SEND_ERROR                  28L	/*!< Generic transmit error */
+#define XST_NOT_ENABLED                 29L	/*!< A requested service is not
+						   available because it has not
+						   been enabled */
+/** @} */
+/***************** Utility Component statuses 401 - 500  *********************/
+/**
+@name Utility Component Status Codes 401 - 500
+@{
+*/
+#define XST_MEMTEST_FAILED              401L	/*!< Memory test failed */
+
+/** @} */
+/***************** Common Components statuses 501 - 1000 *********************/
+/**
+@name Packet Fifo Status Codes 501 - 510
+@{
+*/
+/********************* Packet Fifo statuses 501 - 510 ************************/
+
+#define XST_PFIFO_LACK_OF_DATA          501L	/*!< Not enough data in FIFO   */
+#define XST_PFIFO_NO_ROOM               502L	/*!< Not enough room in FIFO   */
+#define XST_PFIFO_BAD_REG_VALUE         503L	/*!< Self test, a register value
+						   was invalid after reset */
+#define XST_PFIFO_ERROR                 504L	/*!< Generic packet FIFO error */
+#define XST_PFIFO_DEADLOCK              505L	/*!< Packet FIFO is reporting
+						 * empty and full simultaneously
+						 */
+/** @} */
+/**
+@name DMA Status Codes 511 - 530
+@{
+*/
+/************************** DMA statuses 511 - 530 ***************************/
+
+#define XST_DMA_TRANSFER_ERROR          511L	/*!< Self test, DMA transfer
+						   failed */
+#define XST_DMA_RESET_REGISTER_ERROR    512L	/*!< Self test, a register value
+						   was invalid after reset */
+#define XST_DMA_SG_LIST_EMPTY           513L	/*!< Scatter gather list contains
+						   no buffer descriptors ready
+						   to be processed */
+#define XST_DMA_SG_IS_STARTED           514L	/*!< Scatter gather not stopped */
+#define XST_DMA_SG_IS_STOPPED           515L	/*!< Scatter gather not running */
+#define XST_DMA_SG_LIST_FULL            517L	/*!< All the buffer desciptors of
+						   the scatter gather list are
+						   being used */
+#define XST_DMA_SG_BD_LOCKED            518L	/*!< The scatter gather buffer
+						   descriptor which is to be
+						   copied over in the scatter
+						   list is locked */
+#define XST_DMA_SG_NOTHING_TO_COMMIT    519L	/*!< No buffer descriptors have been
+						   put into the scatter gather
+						   list to be commited */
+#define XST_DMA_SG_COUNT_EXCEEDED       521L	/*!< The packet count threshold
+						   specified was larger than the
+						   total # of buffer descriptors
+						   in the scatter gather list */
+#define XST_DMA_SG_LIST_EXISTS          522L	/*!< The scatter gather list has
+						   already been created */
+#define XST_DMA_SG_NO_LIST              523L	/*!< No scatter gather list has
+						   been created */
+#define XST_DMA_SG_BD_NOT_COMMITTED     524L	/*!< The buffer descriptor which was
+						   being started was not committed
+						   to the list */
+#define XST_DMA_SG_NO_DATA              525L	/*!< The buffer descriptor to start
+						   has already been used by the
+						   hardware so it can't be reused
+						 */
+#define XST_DMA_SG_LIST_ERROR           526L	/*!< General purpose list access
+						   error */
+#define XST_DMA_BD_ERROR                527L	/*!< General buffer descriptor
+						   error */
+/** @} */
+/**
+@name IPIF Status Codes Codes 531 - 550
+@{
+*/
+/************************** IPIF statuses 531 - 550 ***************************/
+
+#define XST_IPIF_REG_WIDTH_ERROR        531L	/*!< An invalid register width
+						   was passed into the function */
+#define XST_IPIF_RESET_REGISTER_ERROR   532L	/*!< The value of a register at
+						   reset was not valid */
+#define XST_IPIF_DEVICE_STATUS_ERROR    533L	/*!< A write to the device interrupt
+						   status register did not read
+						   back correctly */
+#define XST_IPIF_DEVICE_ACK_ERROR       534L	/*!< The device interrupt status
+						   register did not reset when
+						   acked */
+#define XST_IPIF_DEVICE_ENABLE_ERROR    535L	/*!< The device interrupt enable
+						   register was not updated when
+						   other registers changed */
+#define XST_IPIF_IP_STATUS_ERROR        536L	/*!< A write to the IP interrupt
+						   status register did not read
+						   back correctly */
+#define XST_IPIF_IP_ACK_ERROR           537L	/*!< The IP interrupt status register
+						   did not reset when acked */
+#define XST_IPIF_IP_ENABLE_ERROR        538L	/*!< IP interrupt enable register was
+						   not updated correctly when other
+						   registers changed */
+#define XST_IPIF_DEVICE_PENDING_ERROR   539L	/*!< The device interrupt pending
+						   register did not indicate the
+						   expected value */
+#define XST_IPIF_DEVICE_ID_ERROR        540L	/*!< The device interrupt ID register
+						   did not indicate the expected
+						   value */
+#define XST_IPIF_ERROR                  541L	/*!< Generic ipif error */
+/** @} */
+
+/****************** Device specific statuses 1001 - 4095 *********************/
+/**
+@name Ethernet Status Codes 1001 - 1050
+@{
+*/
+/********************* Ethernet statuses 1001 - 1050 *************************/
+
+#define XST_EMAC_MEMORY_SIZE_ERROR  1001L	/*!< Memory space is not big enough
+						 * to hold the minimum number of
+						 * buffers or descriptors */
+#define XST_EMAC_MEMORY_ALLOC_ERROR 1002L	/*!< Memory allocation failed */
+#define XST_EMAC_MII_READ_ERROR     1003L	/*!< MII read error */
+#define XST_EMAC_MII_BUSY           1004L	/*!< An MII operation is in progress */
+#define XST_EMAC_OUT_OF_BUFFERS     1005L	/*!< Driver is out of buffers */
+#define XST_EMAC_PARSE_ERROR        1006L	/*!< Invalid driver init string */
+#define XST_EMAC_COLLISION_ERROR    1007L	/*!< Excess deferral or late
+						 * collision on polled send */
+/** @} */
+/**
+@name UART Status Codes 1051 - 1075
+@{
+*/
+/*********************** UART statuses 1051 - 1075 ***************************/
+#define XST_UART
+
+#define XST_UART_INIT_ERROR         1051L
+#define XST_UART_START_ERROR        1052L
+#define XST_UART_CONFIG_ERROR       1053L
+#define XST_UART_TEST_FAIL          1054L
+#define XST_UART_BAUD_ERROR         1055L
+#define XST_UART_BAUD_RANGE         1056L
+
+/** @} */
+/**
+@name IIC Status Codes 1076 - 1100
+@{
+*/
+/************************ IIC statuses 1076 - 1100 ***************************/
+
+#define XST_IIC_SELFTEST_FAILED         1076	/*!< self test failed            */
+#define XST_IIC_BUS_BUSY                1077	/*!< bus found busy              */
+#define XST_IIC_GENERAL_CALL_ADDRESS    1078	/*!< mastersend attempted with   */
+					     /* general call address        */
+#define XST_IIC_STAND_REG_RESET_ERROR   1079	/*!< A non parameterizable reg   */
+					     /* value after reset not valid */
+#define XST_IIC_TX_FIFO_REG_RESET_ERROR 1080	/*!< Tx fifo included in design  */
+					     /* value after reset not valid */
+#define XST_IIC_RX_FIFO_REG_RESET_ERROR 1081	/*!< Rx fifo included in design  */
+					     /* value after reset not valid */
+#define XST_IIC_TBA_REG_RESET_ERROR     1082	/*!< 10 bit addr incl in design  */
+					     /* value after reset not valid */
+#define XST_IIC_CR_READBACK_ERROR       1083	/*!< Read of the control register */
+					     /* didn't return value written */
+#define XST_IIC_DTR_READBACK_ERROR      1084	/*!< Read of the data Tx reg     */
+					     /* didn't return value written */
+#define XST_IIC_DRR_READBACK_ERROR      1085	/*!< Read of the data Receive reg */
+					     /* didn't return value written */
+#define XST_IIC_ADR_READBACK_ERROR      1086	/*!< Read of the data Tx reg     */
+					     /* didn't return value written */
+#define XST_IIC_TBA_READBACK_ERROR      1087	/*!< Read of the 10 bit addr reg */
+					     /* didn't return written value */
+#define XST_IIC_NOT_SLAVE               1088	/*!< The device isn't a slave    */
+/** @} */
+/**
+@name ATMC Status Codes 1101 - 1125
+@{
+*/
+/*********************** ATMC statuses 1101 - 1125 ***************************/
+
+#define XST_ATMC_ERROR_COUNT_MAX    1101L	/*!< the error counters in the ATM
+						   controller hit the max value
+						   which requires the statistics
+						   to be cleared */
+/** @} */
+/**
+@name Flash Status Codes 1126 - 1150
+@{
+*/
+/*********************** Flash statuses 1126 - 1150 **************************/
+
+#define XST_FLASH_BUSY                1126L	/*!< Flash is erasing or programming
+						 */
+#define XST_FLASH_READY               1127L	/*!< Flash is ready for commands */
+#define XST_FLASH_ERROR               1128L	/*!< Flash had detected an internal
+						   error. Use XFlash_DeviceControl
+						   to retrieve device specific codes
+						 */
+#define XST_FLASH_ERASE_SUSPENDED     1129L	/*!< Flash is in suspended erase state
+						 */
+#define XST_FLASH_WRITE_SUSPENDED     1130L	/*!< Flash is in suspended write state
+						 */
+#define XST_FLASH_PART_NOT_SUPPORTED  1131L	/*!< Flash type not supported by
+						   driver */
+#define XST_FLASH_NOT_SUPPORTED       1132L	/*!< Operation not supported */
+#define XST_FLASH_TOO_MANY_REGIONS    1133L	/*!< Too many erase regions */
+#define XST_FLASH_TIMEOUT_ERROR       1134L	/*!< Programming or erase operation
+						   aborted due to a timeout */
+#define XST_FLASH_ADDRESS_ERROR       1135L	/*!< Accessed flash outside its
+						   addressible range */
+#define XST_FLASH_ALIGNMENT_ERROR     1136L	/*!< Write alignment error */
+#define XST_FLASH_BLOCKING_CALL_ERROR 1137L	/*!< Couldn't return immediately from
+						   write/erase function with
+						   XFL_NON_BLOCKING_WRITE/ERASE
+						   option cleared */
+#define XST_FLASH_CFI_QUERY_ERROR     1138L	/*!< Failed to query the device */
+/** @} */
+/**
+@name SPI Status Codes 1151 - 1175
+@{
+*/
+/*********************** SPI statuses 1151 - 1175 ****************************/
+
+#define XST_SPI_MODE_FAULT          1151	/*!< master was selected as slave */
+#define XST_SPI_TRANSFER_DONE       1152	/*!< data transfer is complete */
+#define XST_SPI_TRANSMIT_UNDERRUN   1153	/*!< slave underruns transmit register */
+#define XST_SPI_RECEIVE_OVERRUN     1154	/*!< device overruns receive register */
+#define XST_SPI_NO_SLAVE            1155	/*!< no slave has been selected yet */
+#define XST_SPI_TOO_MANY_SLAVES     1156	/*!< more than one slave is being
+						 * selected */
+#define XST_SPI_NOT_MASTER          1157	/*!< operation is valid only as master */
+#define XST_SPI_SLAVE_ONLY          1158	/*!< device is configured as slave-only
+						 */
+#define XST_SPI_SLAVE_MODE_FAULT    1159	/*!< slave was selected while disabled */
+#define XST_SPI_SLAVE_MODE          1160	/*!< device has been addressed as slave */
+#define XST_SPI_RECEIVE_NOT_EMPTY   1161	/*!< device received data in slave mode */
+
+#define XST_SPI_COMMAND_ERROR       1162	/*!< unrecognised command - qspi only */
+#define XST_SPI_POLL_DONE           1163        /*!< controller completed polling the
+						   device for status */
+/** @} */
+/**
+@name OPB Arbiter Status Codes 1176 - 1200
+@{
+*/
+/********************** OPB Arbiter statuses 1176 - 1200 *********************/
+
+#define XST_OPBARB_INVALID_PRIORITY  1176	/*!< the priority registers have either
+						 * one master assigned to two or more
+						 * priorities, or one master not
+						 * assigned to any priority
+						 */
+#define XST_OPBARB_NOT_SUSPENDED     1177	/*!< an attempt was made to modify the
+						 * priority levels without first
+						 * suspending the use of priority
+						 * levels
+						 */
+#define XST_OPBARB_PARK_NOT_ENABLED  1178	/*!< bus parking by id was enabled but
+						 * bus parking was not enabled
+						 */
+#define XST_OPBARB_NOT_FIXED_PRIORITY 1179	/*!< the arbiter must be in fixed
+						 * priority mode to allow the
+						 * priorities to be changed
+						 */
+/** @} */
+/**
+@name INTC Status Codes 1201 - 1225
+@{
+*/
+/************************ Intc statuses 1201 - 1225 **************************/
+
+#define XST_INTC_FAIL_SELFTEST      1201	/*!< self test failed */
+#define XST_INTC_CONNECT_ERROR      1202	/*!< interrupt already in use */
+/** @} */
+/**
+@name TmrCtr Status Codes 1226 - 1250
+@{
+*/
+/********************** TmrCtr statuses 1226 - 1250 **************************/
+
+#define XST_TMRCTR_TIMER_FAILED     1226	/*!< self test failed */
+/** @} */
+/**
+@name WdtTb Status Codes 1251 - 1275
+@{
+*/
+/********************** WdtTb statuses 1251 - 1275 ***************************/
+
+#define XST_WDTTB_TIMER_FAILED      1251L
+/** @} */
+/**
+@name PlbArb status Codes 1276 - 1300
+@{
+*/
+/********************** PlbArb statuses 1276 - 1300 **************************/
+
+#define XST_PLBARB_FAIL_SELFTEST    1276L
+/** @} */
+/**
+@name Plb2Opb Status Codes 1301 - 1325
+@{
+*/
+/********************** Plb2Opb statuses 1301 - 1325 *************************/
+
+#define XST_PLB2OPB_FAIL_SELFTEST   1301L
+/** @} */
+/**
+@name Opb2Plb Status 1326 - 1350
+@{
+*/
+/********************** Opb2Plb statuses 1326 - 1350 *************************/
+
+#define XST_OPB2PLB_FAIL_SELFTEST   1326L
+/** @} */
+/**
+@name SysAce Status Codes 1351 - 1360
+@{
+*/
+/********************** SysAce statuses 1351 - 1360 **************************/
+
+#define XST_SYSACE_NO_LOCK          1351L	/*!< No MPU lock has been granted */
+/** @} */
+/**
+@name PCI Bridge Status Codes 1361 - 1375
+@{
+*/
+/********************** PCI Bridge statuses 1361 - 1375 **********************/
+
+#define XST_PCI_INVALID_ADDRESS     1361L
+/** @} */
+/**
+@name FlexRay Constants 1400 - 1409
+@{
+*/
+/********************** FlexRay constants 1400 - 1409 *************************/
+
+#define XST_FR_TX_ERROR			1400
+#define XST_FR_TX_BUSY			1401
+#define XST_FR_BUF_LOCKED		1402
+#define XST_FR_NO_BUF			1403
+/** @} */
+/**
+@name USB constants 1410 - 1420
+@{
+*/
+/****************** USB constants 1410 - 1420  *******************************/
+
+#define XST_USB_ALREADY_CONFIGURED	1410
+#define XST_USB_BUF_ALIGN_ERROR		1411
+#define XST_USB_NO_DESC_AVAILABLE	1412
+#define XST_USB_BUF_TOO_BIG		1413
+#define XST_USB_NO_BUF			1414
+/** @} */
+/**
+@name HWICAP constants 1421 - 1429
+@{
+*/
+/****************** HWICAP constants 1421 - 1429  *****************************/
+
+#define XST_HWICAP_WRITE_DONE		1421
+
+/** @} */
+/**
+@name AXI VDMA constants 1430 - 1440
+@{
+*/
+/****************** AXI VDMA constants 1430 - 1440  *****************************/
+
+#define XST_VDMA_MISMATCH_ERROR		1430
+/** @} */
+/**
+@name NAND Flash Status Codes 1441 - 1459
+@{
+*/
+/*********************** NAND Flash statuses 1441 - 1459  *********************/
+
+#define XST_NAND_BUSY			1441L	/*!< Flash is erasing or
+						 * programming
+						 */
+#define XST_NAND_READY			1442L	/*!< Flash is ready for commands
+						 */
+#define XST_NAND_ERROR			1443L	/*!< Flash had detected an
+						 * internal error.
+						 */
+#define XST_NAND_PART_NOT_SUPPORTED	1444L	/*!< Flash type not supported by
+						 * driver
+						 */
+#define XST_NAND_OPT_NOT_SUPPORTED	1445L	/*!< Operation not supported
+						 */
+#define XST_NAND_TIMEOUT_ERROR		1446L	/*!< Programming or erase
+						 * operation aborted due to a
+						 * timeout
+						 */
+#define XST_NAND_ADDRESS_ERROR		1447L	/*!< Accessed flash outside its
+						 * addressible range
+						 */
+#define XST_NAND_ALIGNMENT_ERROR	1448L	/*!< Write alignment error
+						 */
+#define XST_NAND_PARAM_PAGE_ERROR	1449L	/*!< Failed to read parameter
+						 * page of the device
+						 */
+#define XST_NAND_CACHE_ERROR		1450L	/*!< Flash page buffer error
+						 */
+
+#define XST_NAND_WRITE_PROTECTED	1451L	/*!< Flash is write protected
+						 */
+/** @} */
+
+/**************************** Type Definitions *******************************/
+
+typedef s32 XStatus;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_status_codes".
+*/
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xtime_l.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xtime_l.c
similarity index 70%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xtime_l.c
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xtime_l.c
index e9998969c..b04adefd0 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xtime_l.c
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xtime_l.c
@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2014 - 2017 Xilinx, Inc. All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
@@ -45,6 +45,7 @@
 * 5.05	pkp	   04/13/16 Added XTime_StartTimer API to start the global timer
 *						counter if it is disabled. Also XTime_GetTime calls
 *						this API to ensure the global timer counter is enabled
+* 6.02  pkp	   01/22/17 Added support for EL1 non-secure
 * 

 *
 * @note		None.
@@ -69,54 +70,64 @@
 
 /************************** Function Prototypes ******************************/
 
-/****************************************************************************
-*
-* Start the Global Timer Counter.
+/****************************************************************************/
+/**
+* @brief	Start the 64-bit physical timer counter.
 *
 * @param	None.
 *
 * @return	None.
 *
+* @note		The timer is initialized only if it is disabled. If the timer is
+*			already running this function does not perform any operation. This
+*			API is effective only if BSP is built for EL3. For EL1 Non-secure,
+*			it simply exits.
+*
+****************************************************************************/
+void XTime_StartTimer(void)
+{
+	if (EL3 == 1){
+		/* Enable the global timer counter only if it is disabled */
+		if(((Xil_In32(XIOU_SCNTRS_BASEADDR + XIOU_SCNTRS_CNT_CNTRL_REG_OFFSET))
+					& XIOU_SCNTRS_CNT_CNTRL_REG_EN_MASK) !=
+					XIOU_SCNTRS_CNT_CNTRL_REG_EN){
+			/*write frequency to System Time Stamp Generator Register*/
+			Xil_Out32((XIOU_SCNTRS_BASEADDR + XIOU_SCNTRS_FREQ_REG_OFFSET),
+					XIOU_SCNTRS_FREQ);
+			/*Enable the timer/counter*/
+			Xil_Out32((XIOU_SCNTRS_BASEADDR + XIOU_SCNTRS_CNT_CNTRL_REG_OFFSET)
+						,XIOU_SCNTRS_CNT_CNTRL_REG_EN);
+		}
+	}
+}
+/****************************************************************************/
+/**
+* @brief	Timer of A53 runs continuously and the time can not be set as
+*			desired. This API doesn't contain anything. It is defined to have
+*			uniformity across platforms.
+*
+* @param	Xtime_Global: 64bit value to be written to the physical timer
+*			counter register. Since API does not do anything, the value is
+*			not utilized.
+*
+* @return	None.
+*
 * @note		None.
 *
 ****************************************************************************/
-void XTime_StartTimer(void)
-{
-	/* Enable the global timer counter only if it is disabled */
-	if(((Xil_In32(XIOU_SCNTRS_BASEADDR + XIOU_SCNTRS_CNT_CNTRL_REG_OFFSET))
-				& XIOU_SCNTRS_CNT_CNTRL_REG_EN_MASK) !=
-				XIOU_SCNTRS_CNT_CNTRL_REG_EN){
-		/*write frequency to System Time Stamp Generator Register*/
-		Xil_Out32((XIOU_SCNTRS_BASEADDR + XIOU_SCNTRS_FREQ_REG_OFFSET),
-				XIOU_SCNTRS_FREQ);
-		/*Enable the timer/counter*/
-		Xil_Out32((XIOU_SCNTRS_BASEADDR + XIOU_SCNTRS_CNT_CNTRL_REG_OFFSET),
-					XIOU_SCNTRS_CNT_CNTRL_REG_EN);
-	}
-}
-/****************************************************************************
-*
-* Set the time in the Global Timer Counter Register.
-*
-* @param	Value to be written to the Global Timer Counter Register.
-*
-* @return	None.
-*
-* @note		In multiprocessor environment reference time will reset/lost for
-*		all processors, when this function called by any one processor.
-*
-****************************************************************************/
 void XTime_SetTime(XTime Xtime_Global)
 {
+	(void) Xtime_Global;
 /*As the generic timer of A53 runs constantly time can not be set as desired
 so the API is left unimplemented*/
 }
 
-/****************************************************************************
+/****************************************************************************/
+/**
+* @brief	Get the time from the physical timer counter register.
 *
-* Get the time from the Global Timer Counter Register.
-*
-* @param	Pointer to the location to be updated with the time.
+* @param	Xtime_Global: Pointer to the 64-bit location to be updated with the
+*			current value of physical timer counter register.
 *
 * @return	None.
 *
@@ -125,8 +136,9 @@ so the API is left unimplemented*/
 ****************************************************************************/
 void XTime_GetTime(XTime *Xtime_Global)
 {
+	if (EL3 == 1)
 	/* Start global timer counter, it will only be enabled if it is disabled */
-	XTime_StartTimer();
+		XTime_StartTimer();
 
 	*Xtime_Global = mfcp(CNTPCT_EL0);
 }
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xtime_l.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xtime_l.h
similarity index 76%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xtime_l.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xtime_l.h
index 489be3559..a36d7fabc 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xtime_l.h
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_6/src/xtime_l.h
@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2014 - 2017 Xilinx, Inc. All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
@@ -33,15 +33,21 @@
 /**
 * @file xtime_l.h
 *
+* @addtogroup a53_64_time_apis Cortex A53 64bit Mode Time Functions
+* xtime_l.h provides access to the 64-bit physical timer counter.
+*
+* @{
+*
 * 
 * MODIFICATION HISTORY:
 *
 * Ver   Who    Date     Changes
 * ----- ------ -------- ---------------------------------------------------
 * 5.00 	pkp	   05/29/14 First release
+* 6.6   srm    10/23/17 Updated the macros to support user configurable sleep
+*		        implementation
 * 

 *
-* @note		None.
 *
 ******************************************************************************/
 
@@ -65,12 +71,21 @@ typedef u64 XTime;
 
 /************************** Constant Definitions *****************************/
 
-#define COUNTS_PER_SECOND          			XPAR_CPU_CORTEXA53_0_TIMESTAMP_CLK_FREQ
-#define XIOU_SCNTRS_BASEADDR      			0xFF260000U
+#if defined (SLEEP_TIMER_BASEADDR)
+#define COUNTS_PER_SECOND     SLEEP_TIMER_FREQUENCY
+#else
+#define COUNTS_PER_SECOND     XPAR_CPU_CORTEXA53_0_TIMESTAMP_CLK_FREQ
+#endif
+
+#if defined (XSLEEP_TIMER_IS_DEFAULT_TIMER)
+#pragma message ("For the sleep routines, Global timer is being used")
+#endif
+
+#define XIOU_SCNTRS_BASEADDR      	    0xFF260000U
 #define XIOU_SCNTRS_CNT_CNTRL_REG_OFFSET    0x00000000U
-#define XIOU_SCNTRS_FREQ_REG_OFFSET    		0x00000020U
-#define XIOU_SCNTRS_FREQ					XPAR_CPU_CORTEXA53_0_TIMESTAMP_CLK_FREQ
-#define XIOU_SCNTRS_CNT_CNTRL_REG_EN    	0x00000001U
+#define XIOU_SCNTRS_FREQ_REG_OFFSET    	    0x00000020U
+#define XIOU_SCNTRS_FREQ		    XPAR_CPU_CORTEXA53_0_TIMESTAMP_CLK_FREQ
+#define XIOU_SCNTRS_CNT_CNTRL_REG_EN        0x00000001U
 #define XIOU_SCNTRS_CNT_CNTRL_REG_EN_MASK   0x00000001U
 /************************** Variable Definitions *****************************/
 
@@ -85,3 +100,6 @@ void XTime_GetTime(XTime *Xtime_Global);
 #endif /* __cplusplus */
 
 #endif /* XTIME_H */
+/**
+* @} End of "addtogroup a53_64_time_apis".
+*/
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v2_0/src/Makefile b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v2_3/src/Makefile
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v2_0/src/Makefile
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v2_3/src/Makefile
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v2_3/src/xsysmonpsu.c
similarity index 96%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu.c
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v2_3/src/xsysmonpsu.c
index b047a4599..4c2545c9e 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu.c
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v2_3/src/xsysmonpsu.c
@@ -18,8 +18,8 @@
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
@@ -61,6 +61,9 @@
 *                       XSysMonPsu_SetSeqAcqTime
 *                       and XSysMonPsu_GetSeqAcqTime to provide support for
 *                       set/get 64 bit value.
+* 2.1   sk     03/03/16 Check for PL reset before doing PL Sysmon reset.
+* 2.3   mn     12/13/17 Correct the AMS block channel numbers
+*       mn     03/08/18 Update Clock Divisor to the proper value
 *
 * 

 *
@@ -109,6 +112,7 @@ s32 XSysMonPsu_CfgInitialize(XSysMonPsu *InstancePtr, XSysMonPsu_Config *ConfigP
 {
 	u32 PsSysmonControlStatus;
 	u32 PlSysmonControlStatus;
+	u32 IntrStatus;
 
 	/* Assert the input arguments. */
 	Xil_AssertNonvoid(InstancePtr != NULL);
@@ -117,11 +121,14 @@ s32 XSysMonPsu_CfgInitialize(XSysMonPsu *InstancePtr, XSysMonPsu_Config *ConfigP
 	/* Set the values read from the device config and the base address. */
 	InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
 	InstancePtr->Config.BaseAddress = EffectiveAddr;
-
+	InstancePtr->Config.InputClockMHz = ConfigPtr->InputClockMHz;
 
 	/* Set all handlers to stub values, let user configure this data later. */
 	InstancePtr->Handler = XSysMonPsu_StubHandler;
 
+	XSysMonPsu_UpdateAdcClkDivisor(InstancePtr, XSYSMON_PS);
+	XSysMonPsu_UpdateAdcClkDivisor(InstancePtr, XSYSMON_PL);
+
 	/* Reset the device such that it is in a known state. */
 	XSysMonPsu_Reset(InstancePtr);
 
@@ -147,6 +154,10 @@ s32 XSysMonPsu_CfgInitialize(XSysMonPsu *InstancePtr, XSysMonPsu_Config *ConfigP
 	/* Indicate the instance is now ready to use, initialized without error */
 	InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
 
+	/* Clear any bits set in the Interrupt Status Register. */
+	IntrStatus = XSysMonPsu_IntrGetStatus(InstancePtr);
+	XSysMonPsu_IntrClear(InstancePtr, IntrStatus);
+
 	return XST_SUCCESS;
 }
 
@@ -166,7 +177,7 @@ s32 XSysMonPsu_CfgInitialize(XSysMonPsu *InstancePtr, XSysMonPsu_Config *ConfigP
 *****************************************************************************/
 static void XSysMonPsu_StubHandler(void *CallBackRef)
 {
-	(void *) CallBackRef;
+	(void) CallBackRef;
 
 	/* Assert occurs always since this is a stub and should never be called */
 	Xil_AssertVoidAlways();
@@ -189,6 +200,7 @@ static void XSysMonPsu_StubHandler(void *CallBackRef)
 ******************************************************************************/
 void XSysMonPsu_Reset(XSysMonPsu *InstancePtr)
 {
+	u8 IsPlReset;
 	/* Assert the arguments. */
 	Xil_AssertVoid(InstancePtr != NULL);
 
@@ -196,9 +208,14 @@ void XSysMonPsu_Reset(XSysMonPsu *InstancePtr)
 	XSysmonPsu_WriteReg(InstancePtr->Config.BaseAddress + XPS_BA_OFFSET +
 			XSYSMONPSU_VP_VN_OFFSET, XSYSMONPSU_VP_VN_MASK);
 
-	/* RESET the PL SYSMON */
-	XSysmonPsu_WriteReg(InstancePtr->Config.BaseAddress + XPL_BA_OFFSET +
-			XSYSMONPSU_VP_VN_OFFSET, XSYSMONPSU_VP_VN_MASK);
+	/* Check for PL is under reset or not */
+	IsPlReset = (XSysmonPsu_ReadReg(CSU_BASEADDR + PCAP_STATUS_OFFSET) &
+						PL_CFG_RESET_MASK) >> PL_CFG_RESET_SHIFT;
+	if (IsPlReset != 0U) {
+		/* RESET the PL SYSMON */
+		XSysmonPsu_WriteReg(InstancePtr->Config.BaseAddress + XPL_BA_OFFSET +
+				XSYSMONPSU_VP_VN_OFFSET, XSYSMONPSU_VP_VN_MASK);
+	}
 
 }
 
@@ -576,7 +593,9 @@ s32 XSysMonPsu_SetSingleChParams(XSysMonPsu *InstancePtr, u8 Channel,
 			  ((Channel >= XSM_CH_SUPPLY_CALIB) &&
 			  (Channel <= XSM_CH_GAINERR_CALIB)) ||
 			  ((Channel >= XSM_CH_SUPPLY4) &&
-			  (Channel <= XSM_CH_TEMP_REMTE)));
+			  (Channel <= XSM_CH_TEMP_REMTE)) ||
+			  ((Channel >= XSM_CH_VCC_PSLL0) &&
+			  (Channel <= XSM_CH_RESERVE1)));
 	Xil_AssertNonvoid((IncreaseAcqCycles == TRUE) ||
 			  (IncreaseAcqCycles == FALSE));
 	Xil_AssertNonvoid((IsEventMode == TRUE) || (IsEventMode == FALSE));
@@ -1163,6 +1182,60 @@ u8 XSysMonPsu_GetAdcClkDivisor(XSysMonPsu *InstancePtr, u32 SysmonBlk)
 	return (u8) (Divisor >> XSYSMONPSU_CFG_REG2_CLK_DVDR_SHIFT);
 }
 
+u8 XSysMonPsu_UpdateAdcClkDivisor(XSysMonPsu *InstancePtr, u32 SysmonBlk)
+{
+	u16 Divisor;
+	u32 EffectiveBaseAddress;
+	u32 RegValue;
+	u32 InputFreq = InstancePtr->Config.InputClockMHz;
+
+	/* Assert the arguments. */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
+
+	/* Calculate the effective baseaddress based on the Sysmon instance. */
+	EffectiveBaseAddress =
+			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
+					SysmonBlk);
+
+	/* Read the divisor value from the Configuration Register 2. */
+	Divisor = (u16) XSysmonPsu_ReadReg(EffectiveBaseAddress +
+							XSYSMONPSU_CFG_REG2_OFFSET);
+	Divisor = Divisor >> XSYSMONPSU_CFG_REG2_CLK_DVDR_SHIFT;
+
+	while (1) {
+		if (!Divisor) {
+			if ((SysmonBlk == XSYSMON_PS) &&
+			(InputFreq/8 >= 1) && (InputFreq/8 <= 26)) {
+				break;
+			} else if ((SysmonBlk == XSYSMON_PL) &&
+			(InputFreq/2 >= 1) && (InputFreq/2 <= 26)) {
+				break;
+			}
+		} else if ((InputFreq/Divisor >= 1) &&
+				(InputFreq/Divisor <= 26)) {
+			break;
+		} else {
+			Divisor += 1;
+		}
+	}
+
+	/*
+	 * Read the Configuration Register 2 and the clear the clock divisor
+	 * bits.
+	 */
+	RegValue = XSysmonPsu_ReadReg(EffectiveBaseAddress +
+					XSYSMONPSU_CFG_REG2_OFFSET);
+	RegValue &= ~(XSYSMONPSU_CFG_REG2_CLK_DVDR_MASK);
+
+	/* Write the divisor value into the Configuration Register 2. */
+	RegValue |= ((u32)Divisor << XSYSMONPSU_CFG_REG2_CLK_DVDR_SHIFT) &
+					XSYSMONPSU_CFG_REG2_CLK_DVDR_MASK;
+	XSysmonPsu_WriteReg(EffectiveBaseAddress + XSYSMONPSU_CFG_REG2_OFFSET,
+			 RegValue);
+
+	return (u8)Divisor;
+}
 /****************************************************************************/
 /**
 *
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v2_3/src/xsysmonpsu.h
similarity index 86%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu.h
rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v2_3/src/xsysmonpsu.h
index ba090c5aa..8fcaa19fe 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu.h
+++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v2_3/src/xsysmonpsu.h
@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2016 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2016-2017 Xilinx, Inc.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
@@ -18,8 +18,8 @@
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
@@ -163,6 +163,21 @@
 *                       set/get 64 bit value.
 *                       Added constants XSM_CFR_ALM_SUPPLY*(8-31)_MASKs to
 *                       provide support for enabling extra PS alarams.
+* 2.1   sk     03/03/16 Check for PL reset before doing PL Sysmon reset.
+*       ms     03/17/17 Added readme.txt file in examples folder for doxygen
+*                       generation.
+*       ms     04/05/17 Modified Comment lines in functions of sysmonpsu
+*                       examples to recognize it as documentation block
+*                       for doxygen generation.
+* 2.2   sk     04/14/17 Corrected temperature conversion formulas.
+* 2.3   mn     12/11/17 Added missing closing bracket error when C++ is used
+*       mn     12/12/17 Added Conversion Support for voltages having Range of
+*                       1 Volt
+*       mn     12/13/17 Correct the AMS block channel numbers
+*       ms     12/15/17 Added peripheral test support.
+*       ms     01/04/18 Provided conditional checks for interrupt example
+*                       in sysmonpsu_header.h
+*       mn     03/08/18 Update Clock Divisor to the proper value
 *
 *
* @@ -211,22 +226,14 @@ extern "C" { #define XSM_CH_SUPPLY10 35U /**< SUPPLY10 PS_MGTRAVTT */ #define XSM_CH_VCCAMS 36U /**< VCCAMS */ #define XSM_CH_TEMP_REMTE 37U /**< Temperature Remote */ -#define XSM_CH_VCC_PSLL0 38U /**< VCC_PSLL0 */ -#define XSM_CH_VCC_PSLL1 39U /**< VCC_PSLL1 */ -#define XSM_CH_VCC_PSLL2 40U /**< VCC_PSLL2 */ -#define XSM_CH_VCC_PSLL3 41U /**< VCC_PSLL3 */ -#define XSM_CH_VCC_PSLL4 42U /**< VCC_PSLL4 */ -#define XSM_CH_VCC_PSBATT 43U /**< VCC_PSBATT */ -#define XSM_CH_VCCINT 44U /**< VCCINT */ -#define XSM_CH_VCCBRAM 45U /**< VCCBRAM */ -#define XSM_CH_VCCAUX 46U /**< VCCAUX */ -#define XSM_CH_VCC_PSDDRPLL 47U /**< VCC_PSDDRPLL */ -#define XSM_CH_DDRPHY_VREF 48U /**< DDRPHY_VREF */ -#define XSM_CH_DDRPHY_AT0 49U /**< DDRPHY_AT0 */ -#define XSM_CH_PSGT_AT0 50U /**< PSGT_AT0 */ -#define XSM_CH_PSGT_AT1 51U /**< PSGT_AT0 */ -#define XSM_CH_RESERVE0 52U /**< PSGT_AT0 */ -#define XSM_CH_RESERVE1 53U /**< PSGT_AT0 */ +#define XSM_CH_VCC_PSLL0 48U /**< VCC_PSLL0 */ +#define XSM_CH_VCC_PSLL3 51U /**< VCC_PSLL3 */ +#define XSM_CH_VCCINT 54U /**< VCCINT */ +#define XSM_CH_VCCBRAM 55U /**< VCCBRAM */ +#define XSM_CH_VCCAUX 56U /**< VCCAUX */ +#define XSM_CH_VCC_PSDDRPLL 57U /**< VCC_PSDDRPLL */ +#define XSM_CH_DDRPHY_VREF 58U /**< DDRPHY_VREF */ +#define XSM_CH_RESERVE1 63U /**< PSGT_AT0 */ /*@}*/ @@ -381,7 +388,8 @@ typedef void (*XSysMonPsu_Handler) (void *CallBackRef); */ typedef struct { u16 DeviceId; /**< Unique ID of device */ - u32 BaseAddress; /**< Register base address */ + u32 BaseAddress; /**< Register base address */ + u16 InputClockMHz; /**< Input clock frequency */ } XSysMonPsu_Config; /** @@ -425,7 +433,7 @@ typedef struct { * *****************************************************************************/ #define XSysMonPsu_RawToTemperature_OnChip(AdcData) \ - ((((float)(AdcData)/65536.0f)/0.00199451786f ) - 273.6777f) + ((((float)(AdcData)/65536.0f)/0.00196342531f ) - 280.2309f) /****************************************************************************/ /** @@ -442,12 +450,30 @@ typedef struct { * *****************************************************************************/ #define XSysMonPsu_RawToTemperature_ExternalRef(AdcData) \ - ((((float)(AdcData)/65536.0f)/0.00198842814f ) - 273.8195f) + ((((float)(AdcData)/65536.0f)/0.00197008621f ) - 279.4266f) /****************************************************************************/ /** * -* This macro converts System Monitor Raw Data to Voltage(volts). +* This macro converts System Monitor Raw Data to Voltage(volts) for VpVn +* supply. +* +* @param AdcData is the System Monitor ADC Raw Data. +* +* @return The Voltage in volts. +* +* @note C-Style signature: +* float XSysMon_VpVnRawToVoltage(u32 AdcData) +* +*****************************************************************************/ +#define XSysMonPsu_VpVnRawToVoltage(AdcData) \ + ((((float)(AdcData))* (1.0f))/65536.0f) + +/****************************************************************************/ +/** +* +* This macro converts System Monitor Raw Data to Voltage(volts) other than +* VCCO_PSIO supply. * * @param AdcData is the System Monitor ADC Raw Data. * @@ -460,6 +486,23 @@ typedef struct { #define XSysMonPsu_RawToVoltage(AdcData) \ ((((float)(AdcData))* (3.0f))/65536.0f) +/****************************************************************************/ +/** +* +* This macro converts System Monitor Raw Data to Voltage(volts) for +* VCCO_PSIO supply. +* +* @param AdcData is the System Monitor ADC Raw Data. +* +* @return The Voltage in volts. +* +* @note C-Style signature: +* float XSysMon_RawToVoltage(u32 AdcData) +* +*****************************************************************************/ +#define XSysMonPsu_VccopsioRawToVoltage(AdcData) \ + ((((float)(AdcData))* (6.0f))/65536.0f) + /****************************************************************************/ /** * @@ -476,7 +519,7 @@ typedef struct { * *****************************************************************************/ #define XSysMonPsu_TemperatureToRaw_OnChip(Temperature) \ - ((s32)(((Temperature) + 273.6777f)*65536.0f*0.00199451786f)) + ((s32)(((Temperature) + 280.2309f)*65536.0f*0.00196342531f)) /****************************************************************************/ /** @@ -494,12 +537,13 @@ typedef struct { * *****************************************************************************/ #define XSysMonPsu_TemperatureToRaw_ExternalRef(Temperature) \ - ((s32)(((Temperature) + 273.8195f)*65536.0f*0.00198842814f)) + ((s32)(((Temperature) + 279.4266f)*65536.0f*0.00197008621f)) /****************************************************************************/ /** * -* This macro converts Voltage in Volts to System Monitor Raw Data. +* This macro converts Voltage in Volts to System Monitor Raw Data other than +* VCCO_PSIO supply * * @param Voltage is the Voltage in volts to be converted to * System Monitor/ADC Raw Data. @@ -513,6 +557,24 @@ typedef struct { #define XSysMonPsu_VoltageToRaw(Voltage) \ ((s32)((Voltage)*65536.0f/3.0f)) +/****************************************************************************/ +/** +* +* This macro converts Voltage in Volts to System Monitor Raw Data for +* VCCO_PSIO supply +* +* @param Voltage is the Voltage in volts to be converted to +* System Monitor/ADC Raw Data. +* +* @return The System Monitor ADC Raw Data. +* +* @note C-Style signature: +* int XSysMon_VoltageToRaw(float Voltage) +* +*****************************************************************************/ +#define XSysMonPsu_VccopsioVoltageToRaw(Voltage) \ + ((s32)((Voltage)*65536.0f/6.0f)) + /****************************************************************************/ /** * @@ -574,6 +636,7 @@ void XSysMonPsu_SetExtenalMux(XSysMonPsu *InstancePtr, u8 Channel, u32 SysmonBlk u32 XSysMonPsu_GetExtenalMux(XSysMonPsu *InstancePtr, u32 SysmonBlk); void XSysMonPsu_SetAdcClkDivisor(XSysMonPsu *InstancePtr, u8 Divisor, u32 SysmonBlk); u8 XSysMonPsu_GetAdcClkDivisor(XSysMonPsu *InstancePtr, u32 SysmonBlk); +u8 XSysMonPsu_UpdateAdcClkDivisor(XSysMonPsu *InstancePtr, u32 SysmonBlk); s32 XSysMonPsu_SetSeqChEnables(XSysMonPsu *InstancePtr, u64 ChEnableMask, u32 SysmonBlk); u64 XSysMonPsu_GetSeqAvgEnables(XSysMonPsu *InstancePtr, u32 SysmonBlk); @@ -607,4 +670,8 @@ s32 XSysMonPsu_SelfTest(XSysMonPsu *InstancePtr); XSysMonPsu_Config *XSysMonPsu_LookupConfig(u16 DeviceId); +#ifdef __cplusplus +} +#endif + #endif /* XSYSMONPSU_H_ */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_g.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v2_3/src/xsysmonpsu_g.c similarity index 88% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_g.c rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v2_3/src/xsysmonpsu_g.c index b692531ad..34bd80b34 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_g.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v2_3/src/xsysmonpsu_g.c @@ -5,7 +5,7 @@ * Version: * DO NOT EDIT. * -* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.* +* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.* *Permission is hereby granted, free of charge, to any person obtaining a copy *of this software and associated documentation files (the Software), to deal *in the Software without restriction, including without limitation the rights @@ -44,11 +44,12 @@ * The configuration table for devices */ -XSysMonPsu_Config XSysMonPsu_ConfigTable[] = +XSysMonPsu_Config XSysMonPsu_ConfigTable[XPAR_XSYSMONPSU_NUM_INSTANCES] = { { XPAR_PSU_AMS_DEVICE_ID, - XPAR_PSU_AMS_BASEADDR + XPAR_PSU_AMS_BASEADDR, + XPAR_PSU_AMS_REF_FREQMHZ } }; diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_hw.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v2_3/src/xsysmonpsu_hw.h similarity index 99% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_hw.h rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v2_3/src/xsysmonpsu_hw.h index 80266ebf9..20082773c 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_hw.h +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v2_3/src/xsysmonpsu_hw.h @@ -18,8 +18,8 @@ * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. @@ -46,6 +46,7 @@ * 1.0 kvn 12/15/15 First release * 2.0 vns 08/14/16 Added CFG_REG3, SEQ_INPUT_MODE2, SEQ_ACQ2, * SEQ_CH2 and SEQ_AVG2 offsets and bit masks +* 2.1 sk 03/03/16 Check for PL reset before doing PL Sysmon reset. * * * @@ -2281,6 +2282,11 @@ extern "C" { #define XSYSMONPSU_MIN_TEMP_REMTE_WIDTH 16U #define XSYSMONPSU_MIN_TEMP_REMTE_MASK 0x0000ffffU +#define CSU_BASEADDR 0xFFCA0000U +#define PCAP_STATUS_OFFSET 0x00003010U +#define PL_CFG_RESET_MASK 0x00000040U +#define PL_CFG_RESET_SHIFT 6U + /***************** Macros (Inline Functions) Definitions *********************/ /****************************************************************************/ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_intr.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v2_3/src/xsysmonpsu_intr.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_intr.c rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v2_3/src/xsysmonpsu_intr.c index b178c2e11..12d921913 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_intr.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v2_3/src/xsysmonpsu_intr.c @@ -18,8 +18,8 @@ * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_selftest.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v2_3/src/xsysmonpsu_selftest.c similarity index 98% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_selftest.c rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v2_3/src/xsysmonpsu_selftest.c index 5b709be14..9b68b887e 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_selftest.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v2_3/src/xsysmonpsu_selftest.c @@ -18,8 +18,8 @@ * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_sinit.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v2_3/src/xsysmonpsu_sinit.c similarity index 97% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_sinit.c rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v2_3/src/xsysmonpsu_sinit.c index 34249a209..32e17ab59 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_sinit.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v2_3/src/xsysmonpsu_sinit.c @@ -18,8 +18,8 @@ * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_2/src/Makefile b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_5/src/Makefile similarity index 100% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_2/src/Makefile rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_5/src/Makefile diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_5/src/xttcps.c similarity index 95% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps.c rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_5/src/xttcps.c index 394262868..b2382f1b2 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_5/src/xttcps.c @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -33,7 +33,7 @@ /** * * @file xttcps.c -* @addtogroup ttcps_v3_0 +* @addtogroup ttcps_v3_5 * @{ * * This file contains the implementation of the XTtcPs driver. This driver @@ -52,7 +52,10 @@ * to stop the timer before configuring * 3.2 mus 10/28/16 Modified XTtcPs_CalcIntervalFromFreq to calculate * 32 bit interval count for zynq ultrascale+mpsoc -* +* 3.5 srm 10/06/17 Updated XTtcPs_GetMatchValue and XTtcPs_SetMatchValue +* APIs to use correct match register width for zynq +* (i.e. 16 bit) and zynq ultrascale+mpsoc (i.e. 32 bit). +* It fixes CR# 986617 * * ******************************************************************************/ @@ -196,7 +199,7 @@ s32 XTtcPs_CfgInitialize(XTtcPs *InstancePtr, XTtcPs_Config *ConfigPtr, * @note None * ****************************************************************************/ -void XTtcPs_SetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex, u16 Value) +void XTtcPs_SetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex, XMatchRegValue Value) { /* * Assert to validate input arguments. @@ -222,12 +225,12 @@ void XTtcPs_SetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex, u16 Value) * @param MatchIndex is the index to the match register to be set. * Valid values are 0, 1, or 2. * -* @return None +* @return The match register value * * @note None * ****************************************************************************/ -u16 XTtcPs_GetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex) +XMatchRegValue XTtcPs_GetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex) { u32 MatchReg; @@ -241,7 +244,7 @@ u16 XTtcPs_GetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex) MatchReg = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress, XTtcPs_Match_N_Offset(MatchIndex)); - return (u16) MatchReg; + return (XMatchRegValue) MatchReg; } /*****************************************************************************/ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_2/src/xttcps.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_5/src/xttcps.h similarity index 93% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_2/src/xttcps.h rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_5/src/xttcps.h index be266d9b3..b7b4e1950 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_2/src/xttcps.h +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_5/src/xttcps.h @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -33,7 +33,7 @@ /** * * @file xttcps.h -* @addtogroup ttcps_v3_0 +* @addtogroup ttcps_v3_5 * @{ * @details * @@ -93,6 +93,16 @@ * modified for MISRA-C:2012 compliance. * 3.2 mus 10/28/16 Modified XTtcPs_GetCounterValue and XTtcPs_SetInterval * macros to return 32 bit values for zynq ultrascale+mpsoc +* ms 01/23/17 Modified xil_printf statement in main function for all +* examples to ensure that "Successfully ran" and "Failed" +* strings are available in all examples. This is a fix +* for CR-965028. +* ms 03/17/17 Added readme.txt file in examples folder for doxygen +* generation. +* 3.4 ms 04/18/17 Modified tcl file to add suffix U for all macros +* definitions of ttcps in xparameters.h +* 3.5 srm 10/06/17 Added new typedef XMatchRegValue for match register width +* * * ******************************************************************************/ @@ -110,12 +120,7 @@ extern "C" { #include "xstatus.h" /************************** Constant Definitions *****************************/ -/* - * Flag for a9 processor - */ - #if !defined (ARMR5) && !defined (__aarch64__) && !defined (ARMA53_32) - #define ARMA9 - #endif + /* * Maximum Value for interval counter @@ -165,12 +170,14 @@ typedef struct { } XTtcPs; /** - * This typedef contains interval count + * This typedef contains interval count and Match register value */ #if defined(ARMA9) typedef u16 XInterval; +typedef u16 XMatchRegValue; #else typedef u32 XInterval; +typedef u32 XMatchRegValue; #endif /***************** Macros (Inline Functions) Definitions *********************/ @@ -279,7 +286,7 @@ typedef u32 XInterval; * @return None * * @note C-style signature: -* void XTtcPs_SetInterval(XTtcPs *InstancePtr, u16 Value) +* void XTtcPs_SetInterval(XTtcPs *InstancePtr, XInterval Value) * ****************************************************************************/ #define XTtcPs_SetInterval(InstancePtr, Value) \ @@ -432,8 +439,8 @@ XTtcPs_Config *XTtcPs_LookupConfig(u16 DeviceId); s32 XTtcPs_CfgInitialize(XTtcPs *InstancePtr, XTtcPs_Config * ConfigPtr, u32 EffectiveAddr); -void XTtcPs_SetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex, u16 Value); -u16 XTtcPs_GetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex); +void XTtcPs_SetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex, XMatchRegValue Value); +XMatchRegValue XTtcPs_GetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex); void XTtcPs_SetPrescaler(XTtcPs *InstancePtr, u8 PrescalerValue); u8 XTtcPs_GetPrescaler(XTtcPs *InstancePtr); diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_2/src/xttcps_g.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_5/src/xttcps_g.c similarity index 94% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_2/src/xttcps_g.c rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_5/src/xttcps_g.c index 28d356092..571cb366a 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_2/src/xttcps_g.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_5/src/xttcps_g.c @@ -5,7 +5,7 @@ * Version: * DO NOT EDIT. * -* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.* +* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.* *Permission is hereby granted, free of charge, to any person obtaining a copy *of this software and associated documentation files (the Software), to deal *in the Software without restriction, including without limitation the rights diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_1/src/xttcps_hw.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_5/src/xttcps_hw.h similarity index 90% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_1/src/xttcps_hw.h rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_5/src/xttcps_hw.h index af78bcd67..b1fa545bd 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_1/src/xttcps_hw.h +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_5/src/xttcps_hw.h @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -33,7 +33,7 @@ /** * * @file xttcps_hw.h -* @addtogroup ttcps_v3_0 +* @addtogroup ttcps_v3_5 * @{ * * This file defines the hardware interface to one of the three timer counters @@ -47,7 +47,10 @@ * ----- ------ -------- ------------------------------------------------- * 1.00a drg/jz 01/21/10 First release * 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance. -* +* 3.5 srm 10/06/17 Updated XTTCPS_COUNT_VALUE_MASK, +* XTTCPS_INTERVAL_VAL_MASK, XTTCPS_MATCH_MASK macros to +* mask 16 bit values for zynq and 32 bit values for +* zynq ultrascale+mpsoc " * * ******************************************************************************/ @@ -66,6 +69,12 @@ extern "C" { #include "xil_io.h" /************************** Constant Definitions *****************************/ +/* + * Flag for a9 processor + */ + #if !defined (ARMR5) && !defined (__aarch64__) && !defined (ARMA53_32) + #define ARMA9 + #endif /** @name Register Map * @@ -114,7 +123,11 @@ extern "C" { * Current Counter Value Register definitions * @{ */ +#if defined(ARMA9) #define XTTCPS_COUNT_VALUE_MASK 0x0000FFFFU /**< 16-bit counter value */ +#else +#define XTTCPS_COUNT_VALUE_MASK 0xFFFFFFFFU /**< 32-bit counter value */ +#endif /* @} */ /** @name Interval Value Register @@ -122,7 +135,11 @@ extern "C" { * down to. * @{ */ +#if defined(ARMA9) #define XTTCPS_INTERVAL_VAL_MASK 0x0000FFFFU /**< 16-bit Interval value*/ +#else +#define XTTCPS_INTERVAL_VAL_MASK 0xFFFFFFFFU /**< 32-bit Interval value*/ +#endif /* @} */ /** @name Match Registers @@ -130,7 +147,11 @@ extern "C" { * registers. * @{ */ +#if defined(ARMA9) #define XTTCPS_MATCH_MASK 0x0000FFFFU /**< 16-bit Match value */ +#else +#define XTTCPS_MATCH_MASK 0xFFFFFFFFU /**< 32-bit Match value */ +#endif #define XTTCPS_NUM_MATCH_REG 3U /**< Num of Match reg */ /* @} */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_1/src/xttcps_options.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_5/src/xttcps_options.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_1/src/xttcps_options.c rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_5/src/xttcps_options.c index 532b235c5..01dd9efb3 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_1/src/xttcps_options.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_5/src/xttcps_options.c @@ -33,7 +33,7 @@ /** * * @file xttcps_options.c -* @addtogroup ttcps_v3_0 +* @addtogroup ttcps_v3_5 * @{ * * This file contains functions to get or set option features for the device. diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_1/src/xttcps_selftest.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_5/src/xttcps_selftest.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_1/src/xttcps_selftest.c rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_5/src/xttcps_selftest.c index 4923df667..b1dd7d0a2 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_1/src/xttcps_selftest.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_5/src/xttcps_selftest.c @@ -33,7 +33,7 @@ /** * * @file xttcps_selftest.c -* @addtogroup ttcps_v3_0 +* @addtogroup ttcps_v3_5 * @{ * * This file contains the implementation of self test function for the diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_2/src/xttcps_sinit.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_5/src/xttcps_sinit.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_2/src/xttcps_sinit.c rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_5/src/xttcps_sinit.c index ef3c6ea6b..4684c8a9c 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_2/src/xttcps_sinit.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_5/src/xttcps_sinit.c @@ -33,7 +33,7 @@ /** * * @file xttcps_sinit.c -* @addtogroup ttcps_v3_0 +* @addtogroup ttcps_v3_5 * @{ * * The implementation of the XTtcPs driver's static initialization functionality. diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_3/src/Makefile b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_6/src/Makefile similarity index 100% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_3/src/Makefile rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_6/src/Makefile diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v3_1/src/xuartps.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_6/src/xuartps.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v3_1/src/xuartps.c rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_6/src/xuartps.c index a338d1f09..c33ec5481 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v3_1/src/xuartps.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_6/src/xuartps.c @@ -33,7 +33,7 @@ /** * * @file xuartps.c -* @addtogroup uartps_v3_1 +* @addtogroup uartps_v3_5 * @{ * * This file contains the implementation of the interface functions for XUartPs @@ -49,6 +49,7 @@ * baud rate. CR# 804281. * 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance. * 3.1 kvn 04/10/15 Modified code for latest RTL changes. +* 3.5 NK 09/26/17 Fix the RX Buffer Overflow issue. * * *****************************************************************************/ @@ -463,7 +464,7 @@ u32 XUartPs_ReceiveBuffer(XUartPs *InstancePtr) * Loop until there is no more data in RX FIFO or the specified * number of bytes has been received */ - while((ReceivedCount <= InstancePtr->ReceiveBuffer.RemainingBytes)&& + while((ReceivedCount < InstancePtr->ReceiveBuffer.RemainingBytes)&& (((CsrRegister & XUARTPS_SR_RXEMPTY) == (u32)0))){ if (InstancePtr->is_rxbs_error) { @@ -635,7 +636,7 @@ s32 XUartPs_SetBaudRate(XUartPs *InstancePtr, u32 BaudRate) static void XUartPs_StubHandler(void *CallBackRef, u32 Event, u32 ByteCount) { - (void *) CallBackRef; + (void) CallBackRef; (void) Event; (void) ByteCount; /* Assert occurs always since this is a stub and should never be called */ diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_6/src/xuartps.h similarity index 96% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps.h rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_6/src/xuartps.h index d915917bb..33758c23b 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps.h +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_6/src/xuartps.h @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -33,7 +33,7 @@ /** * * @file xuartps.h -* @addtogroup uartps_v3_1 +* @addtogroup uartps_v3_5 * @{ * @details * @@ -162,6 +162,14 @@ * 3.1 adk 14/03/16 Include interrupt examples in the peripheral test when * uart is connected to a valid interrupt controller CR#946803. * 3.2 rk 07/20/16 Modified the logic for transmission break bit set +* 3.4 ms 01/23/17 Added xil_printf statement in main function for all +* examples to ensure that "Successfully ran" and "Failed" +* strings are available in all examples. This is a fix +* for CR-965028. +* ms 03/17/17 Added readme.txt file in examples folder for doxygen +* generation. +* 3.6 ms 02/16/18 Updates the flow control mode offset value in modem +* control register. * * * diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_g.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_6/src/xuartps_g.c similarity index 91% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_g.c rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_6/src/xuartps_g.c index d4a8e5ab9..6abb20e4d 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_g.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_6/src/xuartps_g.c @@ -5,7 +5,7 @@ * Version: * DO NOT EDIT. * -* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.* +* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.* *Permission is hereby granted, free of charge, to any person obtaining a copy *of this software and associated documentation files (the Software), to deal *in the Software without restriction, including without limitation the rights @@ -44,7 +44,7 @@ * The configuration table for devices */ -XUartPs_Config XUartPs_ConfigTable[] = +XUartPs_Config XUartPs_ConfigTable[XPAR_XUARTPS_NUM_INSTANCES] = { { XPAR_PSU_UART_0_DEVICE_ID, diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_hw.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_6/src/xuartps_hw.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_hw.c rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_6/src/xuartps_hw.c index 299dd35ae..724c3cb40 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_hw.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_6/src/xuartps_hw.c @@ -33,7 +33,7 @@ /** * * @file xuartps_hw.c -* @addtogroup uartps_v3_1 +* @addtogroup uartps_v3_5 * @{ * * diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_3/src/xuartps_hw.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_6/src/xuartps_hw.h similarity index 98% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_3/src/xuartps_hw.h rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_6/src/xuartps_hw.h index 9f5f0b700..9a2bc4305 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_3/src/xuartps_hw.h +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_6/src/xuartps_hw.h @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -33,7 +33,7 @@ /** * * @file xuartps_hw.h -* @addtogroup uartps_v3_1 +* @addtogroup uartps_v3_5 * @{ * * This header file contains the hardware interface of an XUartPs device. @@ -55,6 +55,8 @@ * constant definitions. * 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance. * 3.1 kvn 04/10/15 Modified code for latest RTL changes. +* 3.6 ms 02/16/18 Updates flow control mode offset value in +* modem control register. * * * @@ -256,7 +258,7 @@ extern "C" { * * @{ */ -#define XUARTPS_MODEMCR_FCM 0x00000010U /**< Flow control mode */ +#define XUARTPS_MODEMCR_FCM 0x00000020U /**< Flow control mode */ #define XUARTPS_MODEMCR_RTS 0x00000002U /**< Request to send */ #define XUARTPS_MODEMCR_DTR 0x00000001U /**< Data terminal ready */ /* @} */ diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_intr.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_6/src/xuartps_intr.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_intr.c rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_6/src/xuartps_intr.c index 3068ee795..dff02fd63 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_intr.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_6/src/xuartps_intr.c @@ -33,7 +33,7 @@ /** * * @file xuartps_intr.c -* @addtogroup uartps_v3_1 +* @addtogroup uartps_v3_5 * @{ * * This file contains the functions for interrupt handling diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_options.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_6/src/xuartps_options.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_options.c rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_6/src/xuartps_options.c index 9a699afa1..5d8d3017c 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_options.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_6/src/xuartps_options.c @@ -33,7 +33,7 @@ /** * * @file xuartps_options.c -* @addtogroup uartps_v3_1 +* @addtogroup uartps_v3_5 * @{ * * The implementation of the options functions for the XUartPs driver. diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_selftest.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_6/src/xuartps_selftest.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_selftest.c rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_6/src/xuartps_selftest.c index a1a7dd366..de58201a1 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_selftest.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_6/src/xuartps_selftest.c @@ -33,7 +33,7 @@ /** * * @file xuartps_selftest.c -* @addtogroup uartps_v3_1 +* @addtogroup uartps_v3_5 * @{ * * This file contains the self-test functions for the XUartPs driver. diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_sinit.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_6/src/xuartps_sinit.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_sinit.c rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_6/src/xuartps_sinit.c index 8dc87dae3..22e2f7a83 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_sinit.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_6/src/xuartps_sinit.c @@ -33,7 +33,7 @@ /** * * @file xuartps_sinit.c -* @addtogroup uartps_v3_1 +* @addtogroup uartps_v3_5 * @{ * * The implementation of the XUartPs driver's static initialzation diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_1/src/Makefile b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_4/src/Makefile similarity index 100% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_1/src/Makefile rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_4/src/Makefile diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_4/src/xusb_wrapper.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_4/src/xusb_wrapper.c new file mode 100644 index 000000000..57f859d81 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_4/src/xusb_wrapper.c @@ -0,0 +1,329 @@ +/****************************************************************************** + * + * Copyright (C) 2017 Xilinx, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * Use of the Software is limited solely to applications: + * (a) running on a Xilinx device, or + * (b) that interact with a Xilinx device through a bus or interconnect. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of the Xilinx shall not be used + * in advertising or otherwise to promote the sale, use or other dealings in + * this Software without prior written authorization from Xilinx. + * + ******************************************************************************/ +/*****************************************************************************/ +/** + * + * @file xusb_wrapper.c + * + * This file contains implementation of USBPSU Driver wrappers. + * + * 
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  	Date     Changes
+ * ----- ---- 	-------- -------------------------------------------------------
+ * 1.0   BK 	12/01/18 First release
+ *	 MYK	12/01/18 Added hibernation support for device mode
+ *	 vak	13/03/18 Moved the setup interrupt system calls from driver to
+ *			 example.
+ *
+ *
+ * + *****************************************************************************/ + +/***************************** Include Files *********************************/ +#include "xusb_wrapper.h" + +/************************** Variable Definitions *****************************/ + +/************************** Function Prototypes ******************************/ +Usb_Config* LookupConfig(u16 DeviceId) +{ + return XUsbPsu_LookupConfig(DeviceId); +} + +void CacheInit(void) +{ + +} + +s32 CfgInitialize(struct Usb_DevData *InstancePtr, + Usb_Config *ConfigPtr, u32 BaseAddress) +{ + PrivateData.AppData = InstancePtr; + InstancePtr->PrivateData = (void *)&PrivateData; + + return XUsbPsu_CfgInitialize((struct XUsbPsu *)InstancePtr->PrivateData, + ConfigPtr, BaseAddress); +} + +void Set_Ch9Handler( + void *InstancePtr, + void (*func)(struct Usb_DevData *, SetupPacket *)) +{ + XUsbPsu_set_ch9handler((struct XUsbPsu *)InstancePtr, func); +} + +void Set_RstHandler(void *InstancePtr, void (*func)(struct Usb_DevData *)) +{ + XUsbPsu_set_rsthandler((struct XUsbPsu *)InstancePtr, func); +} + +void Set_Disconnect(void *InstancePtr, void (*func)(struct Usb_DevData *)) +{ + XUsbPsu_set_disconnect((struct XUsbPsu *)InstancePtr, func); +} + +void EpConfigure(void *UsbInstance, u8 EndpointNo, u8 dir, u32 Type) +{ + (void)UsbInstance; + (void)EndpointNo; + (void)dir; + (void)Type; +} + +s32 ConfigureDevice(void *UsbInstance, u8 *MemPtr, u32 memSize) +{ + (void)UsbInstance; + (void)MemPtr; + (void)memSize; + return XST_SUCCESS; +} + +void SetEpHandler(void *InstancePtr, u8 Epnum, + u8 Dir, void (*Handler)(void *, u32, u32)) +{ + XUsbPsu_SetEpHandler((struct XUsbPsu *)InstancePtr, Epnum, Dir, Handler); +} + +s32 Usb_Start(void *InstancePtr) +{ + return XUsbPsu_Start((struct XUsbPsu *)InstancePtr); +} + +void *Get_DrvData(void *InstancePtr) +{ + return XUsbPsu_get_drvdata((struct XUsbPsu *)InstancePtr); +} + +void Set_DrvData(void *InstancePtr, void *data) +{ + XUsbPsu_set_drvdata((struct XUsbPsu *)InstancePtr, data); +} + +s32 IsEpStalled(void *InstancePtr, u8 Epnum, u8 Dir) +{ + return XUsbPsu_IsEpStalled((struct XUsbPsu *)InstancePtr, Epnum, Dir); +} + +void EpClearStall(void *InstancePtr, u8 Epnum, u8 Dir) +{ + XUsbPsu_EpClearStall((struct XUsbPsu *)InstancePtr, Epnum, Dir); +} + +s32 EpBufferSend(void *InstancePtr, u8 UsbEp, + u8 *BufferPtr, u32 BufferLen) +{ + if (UsbEp == 0 && BufferLen == 0) + return XST_SUCCESS; + else + return XUsbPsu_EpBufferSend((struct XUsbPsu *)InstancePtr, + UsbEp, BufferPtr, BufferLen); + +} + +s32 EpBufferRecv(void *InstancePtr, u8 UsbEp, + u8 *BufferPtr, u32 Length) +{ + return XUsbPsu_EpBufferRecv((struct XUsbPsu *)InstancePtr, UsbEp, + BufferPtr, Length); +} + +void EpSetStall(void *InstancePtr, u8 Epnum, u8 Dir) +{ + XUsbPsu_EpSetStall((struct XUsbPsu *)InstancePtr, Epnum, Dir); +} + +void SetBits(void *InstancePtr, u32 TestSel) +{ + (void)InstancePtr; + (void)TestSel; +} + +s32 SetDeviceAddress(void *InstancePtr, u16 Addr) +{ + return XUsbPsu_SetDeviceAddress((struct XUsbPsu *)InstancePtr, Addr); +} + +s32 SetU1SleepTimeout(void *InstancePtr, u8 Sleep) +{ + return XUsbPsu_SetU1SleepTimeout((struct XUsbPsu *)InstancePtr, Sleep); +} + +s32 SetU2SleepTimeout(void *InstancePtr, u8 Sleep) +{ + return XUsbPsu_SetU2SleepTimeout((struct XUsbPsu *)InstancePtr, Sleep); +} + +s32 AcceptU1U2Sleep(void *InstancePtr) +{ + return XUsbPsu_AcceptU1U2Sleep((struct XUsbPsu *)InstancePtr); + +} + +s32 U1SleepEnable(void *InstancePtr) +{ + return XUsbPsu_U1SleepEnable((struct XUsbPsu *)InstancePtr); +} + +s32 U2SleepEnable(void *InstancePtr) +{ + return XUsbPsu_U2SleepEnable((struct XUsbPsu *)InstancePtr); +} + +s32 U1SleepDisable(void *InstancePtr) +{ + return XUsbPsu_U1SleepDisable((struct XUsbPsu *)InstancePtr); +} + +s32 U2SleepDisable(void *InstancePtr) +{ + return XUsbPsu_U2SleepDisable((struct XUsbPsu *)InstancePtr); +} + +s32 EpEnable(void *InstancePtr, u8 UsbEpNum, u8 Dir, u16 Maxsize, u8 Type) +{ + return XUsbPsu_EpEnable((struct XUsbPsu *)InstancePtr, UsbEpNum, Dir, + Maxsize, Type, FALSE); +} + +s32 EpDisable(void *InstancePtr, u8 UsbEpNum, u8 Dir) +{ + return XUsbPsu_EpDisable((struct XUsbPsu *)InstancePtr, UsbEpNum, Dir); +} + +void Usb_SetSpeed(void *InstancePtr, u32 Speed) +{ + XUsbPsu_SetSpeed((struct XUsbPsu *)InstancePtr, Speed); +} + +/****************************************************************************/ +/** +* Sets speed of the Core for connecting to Host +* +* @param InstancePtr is a pointer to the Usb_DevData instance. +* +* @return XST_SUCCESS else XST_FAILURE +* +* @note None. +* +*****************************************************************************/ +s32 IsSuperSpeed(struct Usb_DevData *InstancePtr) +{ + if (InstancePtr->Speed != XUSBPSU_SPEED_SUPER) { + return XST_FAILURE; + } + + return XST_SUCCESS; +} + +/****************************************************************************/ +/** +* Set the Config state +* +* @param InstancePtr is a private member of Usb_DevData instance. +* @param Flag is the config value. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void SetConfigDone(void *InstancePtr, u8 Flag) +{ + ((struct XUsbPsu *)InstancePtr)->IsConfigDone = Flag; +} + +/****************************************************************************/ +/** +* Get the Config state +* +* @param InstancePtr is a private member of Usb_DevData instance. +* +* @return Current configuration value +* +* @note None. +* +*****************************************************************************/ +u8 GetConfigDone(void *InstancePtr) +{ + return (((struct XUsbPsu *)InstancePtr)->IsConfigDone); +} + +void Ep0StallRestart(void *InstancePtr) +{ + XUsbPsu_Ep0StallRestart((struct XUsbPsu *)InstancePtr); +} + +/******************************************************************************/ +/** + * This function sets Endpoint Interval. + * + * @param InstancePtr is a private member of Usb_DevData instance. + * @param UsbEpnum is Endpoint Number. + * @param Dir is Endpoint Direction(In/Out). + * @param Interval is the data transfer service interval + * + * @return None. + * + * @note None. + * + ******************************************************************************/ +void SetEpInterval(void *InstancePtr, u8 UsbEpNum, u8 Dir, u32 Interval) +{ + u32 PhyEpNum; + struct XUsbPsu_Ep *Ept; + + PhyEpNum = PhysicalEp(UsbEpNum, Dir); + Ept = &((struct XUsbPsu *)InstancePtr)->eps[PhyEpNum]; + Ept->Interval = Interval; +} + +void StopTransfer(void *InstancePtr, u8 EpNum, u8 Dir) +{ + XUsbPsu_StopTransfer((struct XUsbPsu *)InstancePtr, EpNum, Dir, TRUE); +} + +s32 StreamOn(void *InstancePtr, u8 EpNum, u8 Dir, u8 *BufferPtr) +{ + (void)InstancePtr; + (void)EpNum; + (void)Dir; + (void)BufferPtr; + /* Streaming will start on TxferNotReady Event */ + return XST_SUCCESS; +} + +void StreamOff(void *InstancePtr, u8 EpNum, u8 Dir) +{ + StopTransfer((struct XUsbPsu *)InstancePtr, EpNum, Dir); +} diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_4/src/xusb_wrapper.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_4/src/xusb_wrapper.h new file mode 100644 index 000000000..d21072bcd --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_4/src/xusb_wrapper.h @@ -0,0 +1,190 @@ +/****************************************************************************** + * + * Copyright (C) 2017 Xilinx, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * Use of the Software is limited solely to applications: + * (a) running on a Xilinx device, or + * (b) that interact with a Xilinx device through a bus or interconnect. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of the Xilinx shall not be used + * in advertising or otherwise to promote the sale, use or other dealings in + * this Software without prior written authorization from Xilinx. + * + ******************************************************************************/ +/*****************************************************************************/ +/** + * + * @file xusb_wrapper.h + * + * This file contains declarations for USBPSU Driver wrappers. + * + * 
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  	Date     Changes
+ * ----- ---- 	-------- -------------------------------------------------------
+ *  1.0  BK	12/01/18 First release
+ *	 MYK	12/01/18 Added hibernation support for device mode
+ *	 vak	22/01/18 Added Microblaze support for usbpsu driver
+ *	 vak	13/03/18 Moved the setup interrupt system calls from driver to
+ *			 example.
+ *
+ *
+ * + *****************************************************************************/ + +#ifndef XUSB_WRAPPER_H /* Prevent circular inclusions */ +#define XUSB_WRAPPER_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files ********************************/ +#include "xusbpsu.h" + +/************************** Constant Definitions ****************************/ +#define USB_DEVICE_ID XPAR_XUSBPSU_0_DEVICE_ID + +#define USB_EP_DIR_IN XUSBPSU_EP_DIR_IN +#define USB_EP_DIR_OUT XUSBPSU_EP_DIR_OUT + +#define USB_DIR_OUT 0U /* to device */ +#define USB_DIR_IN 0x80U /* to host */ + +/** + * @name Endpoint Address + * @{ + */ +#define USB_EP1_IN 0x81 +#define USB_EP1_OUT 0x01 +#define USB_EP2_IN 0x82 +#define USB_EP2_OUT 0x02 +/* @} */ + +/** + * @name Endpoint Type + * @{ + */ +#define USB_EP_TYPE_CONTROL XUSBPSU_ENDPOINT_XFER_CONTROL +#define USB_EP_TYPE_ISOCHRONOUS XUSBPSU_ENDPOINT_XFER_ISOC +#define USB_EP_TYPE_BULK XUSBPSU_ENDPOINT_XFER_BULK +#define USB_EP_TYPE_INTERRUPT XUSBPSU_ENDPOINT_XFER_INT +/* @} */ + +#define USB_ENDPOINT_NUMBER_MASK 0x0f /* in bEndpointAddress */ +#define USB_ENDPOINT_DIR_MASK 0x80 + +/* + * Device States + */ +#define USB_STATE_ATTACHED XUSBPSU_STATE_ATTACHED +#define USB_STATE_POWERED XUSBPSU_STATE_POWERED +#define USB_STATE_DEFAULT XUSBPSU_STATE_DEFAULT +#define USB_STATE_ADDRESS XUSBPSU_STATE_ADDRESS +#define USB_STATE_CONFIGURED XUSBPSU_STATE_CONFIGURED +#define USB_STATE_SUSPENDED XUSBPSU_STATE_SUSPENDED + +#define XUSBPSU_REQ_REPLY_LEN 1024 /**< Max size of reply buffer. */ +#define USB_REQ_REPLY_LEN XUSBPSU_REQ_REPLY_LEN + +/* + * Device Speeds + */ +#define USB_SPEED_UNKNOWN XUSBPSU_SPEED_UNKNOWN +#define USB_SPEED_LOW XUSBPSU_SPEED_LOW +#define USB_SPEED_FULL XUSBPSU_SPEED_FULL +#define USB_SPEED_HIGH XUSBPSU_SPEED_HIGH +#define USB_SPEED_SUPER XUSBPSU_SPEED_SUPER + +/* Device Configuration Speed */ +#define USB_DCFG_SPEED_MASK XUSBPSU_DCFG_SPEED_MASK +#define USB_DCFG_SUPERSPEED XUSBPSU_DCFG_SUPERSPEED +#define USB_DCFG_HIGHSPEED XUSBPSU_DCFG_HIGHSPEED +#define USB_DCFG_FULLSPEED2 XUSBPSU_DCFG_FULLSPEED2 +#define USB_DCFG_LOWSPEED XUSBPSU_DCFG_LOWSPEED +#define USB_DCFG_FULLSPEED1 XUSBPSU_DCFG_FULLSPEED1 + +#define USB_TEST_J XUSBPSU_TEST_J +#define USB_TEST_K XUSBPSU_TEST_K +#define USB_TEST_SE0_NAK XUSBPSU_TEST_SE0_NAK +#define USB_TEST_PACKET XUSBPSU_TEST_PACKET +#define USB_TEST_FORCE_ENABLE XUSBPSU_TEST_FORCE_ENABLE + +/* TODO: If we enable this macro, reconnection is failed with 2017.3 */ +#define USB_LPM_MODE XUSBPSU_LPM_MODE + +/* + * return Physical EP number as dwc3 mapping + */ +#define PhysicalEp(epnum, direction) (((epnum) << 1 ) | (direction)) + +/**************************** Type Definitions ******************************/ + +/************************** Variable Definitions *****************************/ +struct XUsbPsu PrivateData; + +/***************** Macros (Inline Functions) Definitions *********************/ +Usb_Config* LookupConfig(u16 DeviceId); +void CacheInit(void); +s32 CfgInitialize(struct Usb_DevData *InstancePtr, + Usb_Config *ConfigPtr, u32 BaseAddress); +void Set_Ch9Handler(void *InstancePtr, + void (*func)(struct Usb_DevData *, SetupPacket *)); +void Set_RstHandler(void *InstancePtr, void (*func)(struct Usb_DevData *)); +void Set_Disconnect(void *InstancePtr, void (*func)(struct Usb_DevData *)); +void EpConfigure(void *UsbInstance, u8 EndpointNo, u8 dir, u32 Type); +s32 ConfigureDevice(void *UsbInstance, u8 *MemPtr, u32 memSize); +void SetEpHandler(void *InstancePtr, u8 Epnum, + u8 Dir, void (*Handler)(void *, u32, u32)); +s32 Usb_Start(void *InstancePtr); +void *Get_DrvData(void *InstancePtr); +void Set_DrvData(void *InstancePtr, void *data); +s32 IsEpStalled(void *InstancePtr, u8 Epnum, u8 Dir); +void EpClearStall(void *InstancePtr, u8 Epnum, u8 Dir); +s32 EpBufferSend(void *InstancePtr, u8 UsbEp, + u8 *BufferPtr, u32 BufferLen); +s32 EpBufferRecv(void *InstancePtr, u8 UsbEp, + u8 *BufferPtr, u32 Length); +void EpSetStall(void *InstancePtr, u8 Epnum, u8 Dir); +void SetBits(void *InstancePtr, u32 TestSel); +s32 SetDeviceAddress(void *InstancePtr, u16 Addr); +s32 SetU1SleepTimeout(void *InstancePtr, u8 Sleep); +s32 SetU2SleepTimeout(void *InstancePtr, u8 Sleep); +s32 AcceptU1U2Sleep(void *InstancePtr); +s32 U1SleepEnable(void *InstancePtr); +s32 U2SleepEnable(void *InstancePtr); +s32 U1SleepDisable(void *InstancePtr); +s32 U2SleepDisable(void *InstancePtr); +s32 EpEnable(void *InstancePtr, u8 UsbEpNum, u8 Dir, u16 Maxsize, u8 Type); +s32 EpDisable(void *InstancePtr, u8 UsbEpNum, u8 Dir); +void Usb_SetSpeed(void *InstancePtr, u32 Speed); +s32 IsSuperSpeed(struct Usb_DevData *InstancePtr); +void SetConfigDone(void *InstancePtr, u8 Flag); +u8 GetConfigDone(void *InstancePtr); +void Ep0StallRestart(void *InstancePtr); +void SetEpInterval(void *InstancePtr, u8 UsbEpNum, u8 Dir, u32 Interval); +void StopTransfer(void *InstancePtr, u8 EpNum, u8 Dir); +s32 StreamOn(void *InstancePtr, u8 EpNum, u8 Dir, u8 *BufferPtr); +void StreamOff(void *InstancePtr, u8 EpNum, u8 Dir); + +#endif /* End of protection macro. */ +/** @} */ diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_4/src/xusbpsu.c similarity index 95% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu.c rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_4/src/xusbpsu.c index c39d11a2f..245fba272 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_4/src/xusbpsu.c @@ -33,7 +33,7 @@ /** * * @file xusbpsu.c -* @addtogroup usbpsu_v1_0 +* @addtogroup usbpsu_v1_3 * @{ * * 
@@ -44,14 +44,16 @@
 * ----- -----  -------- -----------------------------------------------------
 * 1.0   sg    06/16/16 First release
 * 1.1   sg    10/24/16 Added new function XUsbPsu_IsSuperSpeed
-*
+* 1.4	bk    12/01/18 Modify USBPSU driver code to fit USB common example code
+*		       for all USB IPs.
+*	myk   12/01/18 Added hibernation support for device mode
 *
* *****************************************************************************/ /***************************** Include Files ********************************/ -#include "xusbpsu.h" +#include "xusb_wrapper.h" /************************** Constant Definitions *****************************/ @@ -226,19 +228,20 @@ void XUsbPsu_PhyReset(struct XUsbPsu *InstancePtr) ******************************************************************************/ void XUsbPsu_EventBuffersSetup(struct XUsbPsu *InstancePtr) { - struct XUsbPsu_EvtBuffer *Evt; + struct XUsbPsu_EvtBuffer *Evt; Xil_AssertVoid(InstancePtr != NULL); Evt = &InstancePtr->Evt; Evt->BuffAddr = (void *)InstancePtr->EventBuffer; + Evt->Offset = 0; XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTADRLO(0), - (UINTPTR)InstancePtr->EventBuffer); + (UINTPTR)InstancePtr->EventBuffer); XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTADRHI(0), - ((UINTPTR)(InstancePtr->EventBuffer) >> 16U) >> 16U); + ((UINTPTR)(InstancePtr->EventBuffer) >> 16U) >> 16U); XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTSIZ(0), - XUSBPSU_GEVNTSIZ_SIZE(sizeof(InstancePtr->EventBuffer))); + XUSBPSU_GEVNTSIZ_SIZE(sizeof(InstancePtr->EventBuffer))); XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTCOUNT(0), 0); } @@ -321,9 +324,9 @@ s32 XUsbPsu_CoreInit(struct XUsbPsu *InstancePtr) XUsbPsu_PhyReset(InstancePtr); RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GCTL); - RegVal &= ~XUSBPSU_GCTL_SCALEDOWN_MASK; - RegVal &= ~XUSBPSU_GCTL_DISSCRAMBLE; - RegVal |= XUSBPSU_GCTL_U2EXIT_LFPS; + RegVal &= ~XUSBPSU_GCTL_SCALEDOWN_MASK; + RegVal &= ~XUSBPSU_GCTL_DISSCRAMBLE; + RegVal |= XUSBPSU_GCTL_U2EXIT_LFPS; Hwparams1 = XUsbPsu_ReadHwParams(InstancePtr, 1U); @@ -333,7 +336,11 @@ s32 XUsbPsu_CoreInit(struct XUsbPsu *InstancePtr) break; case XUSBPSU_GHWPARAMS1_EN_PWROPT_HIB: - /* enable hibernation here */ + /* enable hibernation here */ +#ifdef XUSBPSU_HIBERNATION_ENABLE + RegVal |= XUSBPSU_GCTL_GBLHIBERNATIONEN; + InstancePtr->HasHibernation = 1; +#endif break; default: @@ -343,6 +350,11 @@ s32 XUsbPsu_CoreInit(struct XUsbPsu *InstancePtr) XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GCTL, RegVal); +#ifdef XUSBPSU_HIBERNATION_ENABLE + if (InstancePtr->HasHibernation) + XUsbPsu_InitHibernation(InstancePtr); +#endif + return XST_SUCCESS; } @@ -441,7 +453,7 @@ void XUsbPsu_DisableIntr(struct XUsbPsu *InstancePtr, u32 Mask) s32 XUsbPsu_CfgInitialize(struct XUsbPsu *InstancePtr, XUsbPsu_Config *ConfigPtr, u32 BaseAddress) { - int Status; + s32 Status; u32 RegVal; @@ -471,10 +483,10 @@ s32 XUsbPsu_CfgInitialize(struct XUsbPsu *InstancePtr, XUsbPsu_SetMode(InstancePtr, XUSBPSU_GCTL_PRTCAP_DEVICE); - /* - * Setting to max speed to support SS and HS - */ - XUsbPsu_SetSpeed(InstancePtr, XUSBPSU_DCFG_SUPERSPEED); + /* + * Setting to max speed to support SS and HS + */ + XUsbPsu_SetSpeed(InstancePtr, XUSBPSU_DCFG_SUPERSPEED); (void)XUsbPsu_SetDeviceAddress(InstancePtr, 0U); @@ -694,7 +706,7 @@ s32 XUsbPsu_SetDeviceAddress(struct XUsbPsu *InstancePtr, u16 Addr) Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(Addr <= 127U); - if (InstancePtr->State == XUSBPSU_STATE_CONFIGURED) { + if (InstancePtr->AppData->State == XUSBPSU_STATE_CONFIGURED) { return XST_FAILURE; } @@ -704,30 +716,10 @@ s32 XUsbPsu_SetDeviceAddress(struct XUsbPsu *InstancePtr, u16 Addr) XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCFG, RegVal); if (Addr) { - InstancePtr->State = XUSBPSU_STATE_ADDRESS; + InstancePtr->AppData->State = XUSBPSU_STATE_ADDRESS; } else { - InstancePtr->State = XUSBPSU_STATE_DEFAULT; - } - - return XST_SUCCESS; -} - -/****************************************************************************/ -/** -* Sets speed of the Core for connecting to Host -* -* @param InstancePtr is a pointer to the XUsbPsu instance. -* -* @return XST_SUCCESS else XST_FAILURE -* -* @note None. -* -*****************************************************************************/ -s32 XUsbPsu_IsSuperSpeed(struct XUsbPsu *InstancePtr) -{ - if (InstancePtr->Speed != XUSBPSU_SPEED_SUPER) { - return XST_FAILURE; + InstancePtr->AppData->State = XUSBPSU_STATE_DEFAULT; } return XST_SUCCESS; diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_1/src/xusbpsu.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_4/src/xusbpsu.h similarity index 78% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_1/src/xusbpsu.h rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_4/src/xusbpsu.h index a1366487b..2d1498ac1 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_1/src/xusbpsu.h +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_4/src/xusbpsu.h @@ -33,7 +33,7 @@ /** * * @file xusbpsu.h -* @addtogroup usbpsu_v1_0 +* @addtogroup usbpsu_v1_3 * @{ * @details * @@ -46,6 +46,22 @@ * 1.0 sg 06/06/16 First release * 1.1 sg 10/24/16 Update for backward compatability * Added XUsbPsu_IsSuperSpeed function in xusbpsu.c +* 1.2 mn 01/20/17 removed unnecessary declaration of +* XUsbPsu_SetConfiguration in xusbpsu.h +* 1.2 mn 01/30/17 Corrected InstancePtr->UnalignedTx with +* Ept->UnalignedTx in xusbpsu_controltransfers.c +* 1.2 mus 02/10/17 Updated data structures to fix compilation errors for IAR +* compiler +* ms 03/17/17 Added readme.txt file in examples folder for doxygen +* generation. +* ms 04/10/17 Modified filename tag to include the file in doxygen +* examples. +* 1.4 bk 12/01/18 Modify USBPSU driver code to fit USB common example code +* for all USB IPs. +* myk 12/01/18 Added hibernation support for device mode +* vak 22/01/18 Added changes for supporting microblaze platform +* vak 13/03/18 Moved the setup interrupt system calls from driver to +* example. * * * @@ -58,17 +74,22 @@ extern "C" { #endif /***************************** Include Files ********************************/ + +/* Enable XUSBPSU_HIBERNATION_ENABLE to enable hibernation */ +//#define XUSBPSU_HIBERNATION_ENABLE 1 + #include "xparameters.h" #include "xil_types.h" #include "xil_assert.h" #include "xstatus.h" #include "xusbpsu_hw.h" #include "xil_io.h" + /* * The header sleep.h and API usleep() can only be used with an arm design. * MB_Sleep() is used for microblaze design. */ -#if defined (__arm__) || defined (__aarch64__) +#if defined (__arm__) || defined (__aarch64__) || (__ICCARM__) #include "sleep.h" #endif @@ -79,16 +100,19 @@ extern "C" { /************************** Constant Definitions ****************************/ +#define NO_OF_TRB_PER_EP 2 + +#ifdef PLATFORM_ZYNQMP #define ALIGNMENT_CACHELINE __attribute__ ((aligned(64))) +#else +#define ALIGNMENT_CACHELINE __attribute__ ((aligned(32))) +#endif #define XUSBPSU_PHY_TIMEOUT 5000U /* in micro seconds */ #define XUSBPSU_EP_DIR_IN 1U #define XUSBPSU_EP_DIR_OUT 0U -#define XUSBPSU_ENDPOINT_NUMBER_MASK 0x0f /* in bEndpointAddress */ -#define XUSBPSU_ENDPOINT_DIR_MASK 0x80 - #define XUSBPSU_ENDPOINT_XFERTYPE_MASK 0x03 /* in bmAttributes */ #define XUSBPSU_ENDPOINT_XFER_CONTROL 0U #define XUSBPSU_ENDPOINT_XFER_ISOC 1U @@ -253,15 +277,6 @@ typedef enum { /**************************** Type Definitions ******************************/ -/** - * This typedef contains configuration information for the XUSBPSU - * device. - */ -typedef struct { - u16 DeviceId; /**< Unique ID of controller */ - u32 BaseAddress; /**< Core register base address */ -} XUsbPsu_Config; - /** * Software Event buffer representation */ @@ -275,13 +290,20 @@ struct XUsbPsu_EvtBuffer { /** * Transfer Request Block - Hardware format */ +#if defined (__ICCARM__) +#pragma pack(push, 1) +#endif struct XUsbPsu_Trb { u32 BufferPtrLow; u32 BufferPtrHigh; u32 Size; u32 Ctrl; +#if defined (__ICCARM__) +}; +#pragma pack(pop) +#else } __attribute__((packed)); - +#endif /* * Endpoint Parameters @@ -295,13 +317,21 @@ struct XUsbPsu_EpParams { /** * USB Standard Control Request */ +#if defined (__ICCARM__) +#pragma pack(push, 1) +#endif typedef struct { u8 bRequestType; u8 bRequest; u16 wValue; u16 wIndex; u16 wLength; +#if defined (__ICCARM__) +}SetupPacket; +#pragma pack(pop) +#else } __attribute__ ((packed)) SetupPacket; +#endif /** * Endpoint representation @@ -312,11 +342,22 @@ struct XUsbPsu_Ep { * when data is sent for IN Ep * and received for OUT Ep */ - struct XUsbPsu_Trb EpTrb ALIGNMENT_CACHELINE;/**< TRB used by endpoint */ +#if defined (__ICCARM__) + #pragma data_alignment = 64 + struct XUsbPsu_Trb EpTrb[NO_OF_TRB_PER_EP + 1]; /**< One extra Trb is for Link Trb */ + #pragma data_alignment = 4 +#else + struct XUsbPsu_Trb EpTrb[NO_OF_TRB_PER_EP + 1] ALIGNMENT_CACHELINE;/**< TRB used by endpoint */ +#endif u32 EpStatus; /**< Flags to represent Endpoint status */ + u32 EpSavedState; /**< Endpoint status saved at the time of hibernation */ u32 RequestedBytes; /**< RequestedBytes for transfer */ u32 BytesTxed; /**< Actual Bytes transferred */ + u32 Interval; /**< Data transfer service interval */ + u32 TrbEnqueue; + u32 TrbDequeue; u16 MaxSize; /**< Size of endpoint */ + u16 CurUf; /**< current microframe */ u8 *BufferPtr; /**< Buffer location */ u8 ResourceIndex; /**< Resource Index assigned to * Endpoint by core @@ -330,13 +371,39 @@ struct XUsbPsu_Ep { u8 UnalignedTx; }; +/** + * This typedef contains configuration information for the USB + * device. + */ +typedef struct { + u16 DeviceId; /**< Unique ID of controller */ + u32 BaseAddress; /**< Core register base address */ + u8 IsCacheCoherent; /**< Describes whether Cache Coherent or not */ +} XUsbPsu_Config; + +typedef XUsbPsu_Config Usb_Config; + +struct Usb_DevData { + u8 Speed; + u8 State; + + void *PrivateData; +}; + /** * USB Device Controller representation */ struct XUsbPsu { +#if defined (__ICCARM__) + #pragma data_alignment = 64 + SetupPacket SetupData; + struct XUsbPsu_Trb Ep0_Trb; + #pragma data_alignment = 4 +#else SetupPacket SetupData ALIGNMENT_CACHELINE; /**< Setup Packet buffer */ struct XUsbPsu_Trb Ep0_Trb ALIGNMENT_CACHELINE; +#endif /**< TRB for control transfers */ XUsbPsu_Config *ConfigPtr; /**< Configuration info pointer */ struct XUsbPsu_Ep eps[XUSBPSU_ENDPOINTS_NUM]; /**< Endpoints */ @@ -345,32 +412,48 @@ struct XUsbPsu { u32 BaseAddress; /**< Core register base address */ u32 DevDescSize; u32 ConfigDescSize; - void (*Chapter9)(struct XUsbPsu *, SetupPacket *); - void (*ClassHandler)(struct XUsbPsu *, SetupPacket *); + struct Usb_DevData *AppData; + void (*Chapter9)(struct Usb_DevData *, SetupPacket *); + void (*ResetIntrHandler)(struct Usb_DevData *); + void (*DisconnectIntrHandler)(struct Usb_DevData *); void *DevDesc; void *ConfigDesc; +#if defined(__ICCARM__) + #pragma data_alignment = XUSBPSU_EVENT_BUFFERS_SIZE + u8 EventBuffer[XUSBPSU_EVENT_BUFFERS_SIZE]; + #pragma data_alignment = 4 +#else u8 EventBuffer[XUSBPSU_EVENT_BUFFERS_SIZE] __attribute__((aligned(XUSBPSU_EVENT_BUFFERS_SIZE))); +#endif u8 NumOutEps; u8 NumInEps; u8 ControlDir; u8 IsInTestMode; u8 TestMode; - u8 Speed; - u8 State; u8 Ep0State; u8 LinkState; u8 UnalignedTx; u8 IsConfigDone; u8 IsThreeStage; + u8 IsHibernated; /**< Hibernated state */ + u8 HasHibernation; /**< Has hibernation support */ + void *data_ptr; /* pointer for storing applications data */ }; +#if defined (__ICCARM__) +#pragma pack(push, 1) +#endif struct XUsbPsu_Event_Type { u32 Is_DevEvt:1; u32 Type:7; u32 Reserved8_31:24; +#if defined (__ICCARM__) +}; +#pragma pack(pop) +#else } __attribute__((packed)); - +#endif /** * struct XUsbPsu_event_depvt - Device Endpoint Events * @Is_EpEvt: indicates this is an endpoint event @@ -390,6 +473,9 @@ struct XUsbPsu_Event_Type { * @Parameters: Parameters of the current event. Refer to databook for * more information. */ +#if defined (__ICCARM__) +#pragma pack(push, 1) +#endif struct XUsbPsu_Event_Epevt { u32 Is_EpEvt:1; u32 Epnumber:5; @@ -397,8 +483,12 @@ struct XUsbPsu_Event_Epevt { u32 Reserved11_10:2; u32 Status:4; u32 Parameters:16; +#if defined (__ICCARM__) +}; +#pragma pack(pop) +#else } __attribute__((packed)); - +#endif /** * struct XUsbPsu_event_devt - Device Events * @Is_DevEvt: indicates this is a non-endpoint event @@ -421,6 +511,9 @@ struct XUsbPsu_Event_Epevt { * @Event_Info: Information about this event * @Reserved31_25: Reserved, not used */ +#if defined (__ICCARM__) +#pragma pack(push, 1) +#endif struct XUsbPsu_Event_Devt { u32 Is_DevEvt:1; u32 Device_Event:7; @@ -428,8 +521,12 @@ struct XUsbPsu_Event_Devt { u32 Reserved15_12:4; u32 Event_Info:9; u32 Reserved31_25:7; +#if defined (__ICCARM__) +}; +#pragma pack(pop) +#else } __attribute__((packed)); - +#endif /** * struct XUsbPsu_event_gevt - Other Core Events * @one_bit: indicates this is a non-endpoint event (not used) @@ -437,13 +534,20 @@ struct XUsbPsu_Event_Devt { * @phy_port_number: self-explanatory * @reserved31_12: Reserved, not used. */ +#if defined (__ICCARM__) +#pragma pack(push, 1) +#endif struct XUsbPsu_Event_Gevt { u32 Is_GlobalEvt:1; u32 Device_Event:7; u32 Phy_Port_Number:4; u32 Reserved31_12:20; +#if defined (__ICCARM__) +}; +#pragma pack(pop) +#else } __attribute__((packed)); - +#endif /** * union XUsbPsu_event - representation of Event Buffer contents * @raw: raw 32-bit event @@ -461,16 +565,22 @@ union XUsbPsu_Event { }; /***************** Macros (Inline Functions) Definitions *********************/ - +#if defined (__ICCARM__) +#define IS_ALIGNED(x, a) (((x) & ((u32)(a) - 1)) == 0U) +#else #define IS_ALIGNED(x, a) (((x) & ((typeof(x))(a) - 1)) == 0U) +#endif +#if defined (__ICCARM__) +#define roundup(x, y) (((((x) + (u32)(y - 1)) / (u32)y) * (u32)y)) + +#else #define roundup(x, y) ( \ -{ \ - const typeof(y) y__ = (y); \ - (((x) + (u32)(y__ - 1)) / (u32)y__) * (u32)y__; \ -} \ + (((x) + (u32)((const typeof(y))y - 1)) / \ + (u32)((const typeof(y))y)) * \ + (u32)((const typeof(y))y) \ ) - +#endif #define DECLARE_DEV_DESC(Instance, desc) \ (Instance).DevDesc = &(desc); \ (Instance).DevDescSize = sizeof((desc)) @@ -479,6 +589,32 @@ union XUsbPsu_Event { (Instance).ConfigDesc = &(desc); \ (Instance).ConfigDescSize = sizeof((desc)) +static inline void *XUsbPsu_get_drvdata(struct XUsbPsu *InstancePtr) { + return InstancePtr->data_ptr; +} + +static inline void XUsbPsu_set_drvdata(struct XUsbPsu *InstancePtr, void *data) { + InstancePtr->data_ptr = data; +} + +static inline void XUsbPsu_set_ch9handler( + struct XUsbPsu *InstancePtr, + void (*func)(struct Usb_DevData *, SetupPacket *)) { + InstancePtr->Chapter9 = func; +} + +static inline void XUsbPsu_set_rsthandler( + struct XUsbPsu *InstancePtr, + void (*func)(struct Usb_DevData *)) { + InstancePtr->ResetIntrHandler = func; +} + +static inline void XUsbPsu_set_disconnect( + struct XUsbPsu *InstancePtr, + void (*func)(struct Usb_DevData *)) { + InstancePtr->DisconnectIntrHandler = func; +} + /************************** Function Prototypes ******************************/ /* @@ -510,7 +646,6 @@ s32 XUsbPsu_SendGenericCmd(struct XUsbPsu *InstancePtr, s32 Cmd, u32 Param); void XUsbPsu_SetSpeed(struct XUsbPsu *InstancePtr, u32 Speed); s32 XUsbPsu_SetDeviceAddress(struct XUsbPsu *InstancePtr, u16 Addr); -s32 XUsbPsu_IsSuperSpeed(struct XUsbPsu *InstancePtr); s32 XUsbPsu_SetU1SleepTimeout(struct XUsbPsu *InstancePtr, u8 Sleep); s32 XUsbPsu_SetU2SleepTimeout(struct XUsbPsu *InstancePtr, u8 Sleep); s32 XUsbPsu_AcceptU1U2Sleep(struct XUsbPsu *InstancePtr); @@ -525,23 +660,25 @@ s32 XUsbPsu_U2SleepDisable(struct XUsbPsu *InstancePtr); struct XUsbPsu_EpParams *XUsbPsu_GetEpParams(struct XUsbPsu *InstancePtr); u32 XUsbPsu_EpGetTransferIndex(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir); -const char *XUsbPsu_EpCmdString(u8 Cmd); s32 XUsbPsu_SendEpCmd(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir, u32 Cmd, struct XUsbPsu_EpParams *Params); s32 XUsbPsu_StartEpConfig(struct XUsbPsu *InstancePtr, u32 UsbEpNum, u8 Dir); s32 XUsbPsu_SetEpConfig(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir, - u16 Size, u8 Type); + u16 Size, u8 Type, u8 Restore); s32 XUsbPsu_SetXferResource(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir); s32 XUsbPsu_EpEnable(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir, - u16 Maxsize, u8 Type); + u16 Maxsize, u8 Type, u8 Restore); s32 XUsbPsu_EpDisable(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir); s32 XUsbPsu_EnableControlEp(struct XUsbPsu *InstancePtr, u16 Size); void XUsbPsu_InitializeEps(struct XUsbPsu *InstancePtr); -void XUsbPsu_StopTransfer(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir); +void XUsbPsu_StopTransfer(struct XUsbPsu *InstancePtr, u8 UsbEpNum, + u8 Dir, u8 Force); +void XUsbPsu_SaveEndpointState(struct XUsbPsu *InstancePtr, + struct XUsbPsu_Ep *Ept); void XUsbPsu_ClearStalls(struct XUsbPsu *InstancePtr); s32 XUsbPsu_EpBufferSend(struct XUsbPsu *InstancePtr, u8 UsbEp, - u8 *BufferPtr, u32 BufferLen); + u8 *BufferPtr, u32 BufferLen); s32 XUsbPsu_EpBufferRecv(struct XUsbPsu *InstancePtr, u8 UsbEp, u8 *BufferPtr, u32 Length); void XUsbPsu_EpSetStall(struct XUsbPsu *InstancePtr, u8 Epnum, u8 Dir); @@ -551,14 +688,14 @@ void XUsbPsu_SetEpHandler(struct XUsbPsu *InstancePtr, u8 Epnum, s32 XUsbPsu_IsEpStalled(struct XUsbPsu *InstancePtr, u8 Epnum, u8 Dir); void XUsbPsu_EpXferComplete(struct XUsbPsu *InstancePtr, const struct XUsbPsu_Event_Epevt *Event); +void XUsbPsu_EpXferNotReady(struct XUsbPsu *InstancePtr, + const struct XUsbPsu_Event_Epevt *Event); /* * Functions in xusbpsu_controltransfers.c */ s32 XUsbPsu_RecvSetup(struct XUsbPsu *InstancePtr); void XUsbPsu_Ep0StallRestart(struct XUsbPsu *InstancePtr); -s32 XUsbPsu_SetConfiguration(struct XUsbPsu *InstancePtr, - SetupPacket *Ctrl); void XUsbPsu_Ep0DataDone(struct XUsbPsu *InstancePtr, const struct XUsbPsu_Event_Epevt *Event); void XUsbPsu_Ep0StatusDone(struct XUsbPsu *InstancePtr, @@ -595,6 +732,14 @@ void XUsbPsu_EventHandler(struct XUsbPsu *InstancePtr, void XUsbPsu_EventBufferHandler(struct XUsbPsu *InstancePtr); void XUsbPsu_IntrHandler(void *XUsbPsuInstancePtr); +#ifdef XUSBPSU_HIBERNATION_ENABLE +void XUsbPsu_InitHibernation(struct XUsbPsu *InstancePtr); +void Xusbpsu_HibernationIntr(struct XUsbPsu *InstancePtr); +void XUsbPsu_WakeUpIntrHandler(void *XUsbPsuInstancePtr); +void XUsbPsu_WakeupIntr(struct XUsbPsu *InstancePtr); +s32 XUsbPsu_SetupScratchpad(struct XUsbPsu *InstancePtr); +#endif + /* * Functions in xusbpsu_sinit.c */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_1/src/xusbpsu_controltransfers.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_4/src/xusbpsu_controltransfers.c similarity index 90% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_1/src/xusbpsu_controltransfers.c rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_4/src/xusbpsu_controltransfers.c index b3a93dc63..19be417fb 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_1/src/xusbpsu_controltransfers.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_4/src/xusbpsu_controltransfers.c @@ -42,19 +42,20 @@ * Ver Who Date Changes * ----- ---- -------- ------------------------------------------------------- * 1.0 sg 06/06/16 First release +* 1.3 vak 04/03/17 Added CCI support for USB +* 1.4 bk 12/01/18 Modify USBPSU driver code to fit USB common example code +* for all USB IPs. * * * *****************************************************************************/ /***************************** Include Files *********************************/ - -#include "xusbpsu.h" #include "xusbpsu_endpoint.h" -/************************** Constant Definitions *****************************/ +#include "sleep.h" +#include "xusb_wrapper.h" -#define USB_DIR_OUT 0U /* to device */ -#define USB_DIR_IN 0x80U /* to host */ +/************************** Constant Definitions *****************************/ /**************************** Type Definitions *******************************/ @@ -62,10 +63,8 @@ /************************** Function Prototypes ******************************/ - /************************** Variable Definitions *****************************/ - /****************************************************************************/ /** * Initiates DMA on Control Endpoint 0 to receive Setup packet. @@ -92,7 +91,7 @@ s32 XUsbPsu_RecvSetup(struct XUsbPsu *InstancePtr) /* Setup packet always on EP0 */ Ept = &InstancePtr->eps[0]; if ((Ept->EpStatus & XUSBPSU_EP_BUSY) != 0U) { - return XST_FAILURE; + return (s32)XST_FAILURE; } TrbPtr = &InstancePtr->Ep0_Trb; @@ -107,7 +106,10 @@ s32 XUsbPsu_RecvSetup(struct XUsbPsu *InstancePtr) | XUSBPSU_TRB_CTRL_IOC | XUSBPSU_TRB_CTRL_ISP_IMI); - Xil_DCacheFlushRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb)); + if (InstancePtr->ConfigPtr->IsCacheCoherent == 0) { + Xil_DCacheFlushRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb)); + Xil_DCacheFlushRange((UINTPTR)&InstancePtr->SetupData, sizeof(SetupPacket)); + } Params->Param0 = 0U; Params->Param1 = (UINTPTR)TrbPtr; @@ -117,7 +119,7 @@ s32 XUsbPsu_RecvSetup(struct XUsbPsu *InstancePtr) Ret = XUsbPsu_SendEpCmd(InstancePtr, 0U, XUSBPSU_EP_DIR_OUT, XUSBPSU_DEPCMD_STARTTRANSFER, Params); if (Ret != XST_SUCCESS) { - return XST_FAILURE; + return (s32)XST_FAILURE; } Ept->EpStatus |= XUSBPSU_EP_BUSY; @@ -187,7 +189,8 @@ void XUsbPsu_Ep0DataDone(struct XUsbPsu *InstancePtr, Ept = &InstancePtr->eps[Epnum]; TrbPtr = &InstancePtr->Ep0_Trb; - Xil_DCacheInvalidateRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb)); + if (InstancePtr->ConfigPtr->IsCacheCoherent == 0) + Xil_DCacheInvalidateRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb)); Status = XUSBPSU_TRB_SIZE_TRBSTS(TrbPtr->Size); if (Status == XUSBPSU_TRBSTS_SETUP_PENDING) { @@ -201,21 +204,22 @@ void XUsbPsu_Ep0DataDone(struct XUsbPsu *InstancePtr, } else { if (Dir == XUSBPSU_EP_DIR_IN) { Ept->BytesTxed = Ept->RequestedBytes - Length; - } else if (Dir == XUSBPSU_EP_DIR_OUT) { - if (Ept->UnalignedTx == 1U) { - Ept->BytesTxed = Ept->RequestedBytes; - Ept->UnalignedTx = 0U; + } else { + if ((Dir == XUSBPSU_EP_DIR_OUT) && (Ept->UnalignedTx == 1U)) { + Ept->BytesTxed = Ept->RequestedBytes; + Ept->UnalignedTx = 0U; } } } if (Dir == XUSBPSU_EP_DIR_OUT) { /* Invalidate Cache */ - Xil_DCacheInvalidateRange((INTPTR)Ept->BufferPtr, Ept->BytesTxed); + if (InstancePtr->ConfigPtr->IsCacheCoherent == 0) + Xil_DCacheInvalidateRange((INTPTR)Ept->BufferPtr, Ept->BytesTxed); } if (Ept->Handler != NULL) { - Ept->Handler(InstancePtr, Ept->RequestedBytes, Ept->BytesTxed); + Ept->Handler(InstancePtr->AppData, Ept->RequestedBytes, Ept->BytesTxed); } } @@ -251,7 +255,8 @@ void XUsbPsu_Ep0StatusDone(struct XUsbPsu *InstancePtr, return; } } - Xil_DCacheInvalidateRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb)); + if (InstancePtr->ConfigPtr->IsCacheCoherent == 0) + Xil_DCacheInvalidateRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb)); (void)XUsbPsu_RecvSetup(InstancePtr); } @@ -286,8 +291,10 @@ void XUsbPsu_Ep0XferComplete(struct XUsbPsu *InstancePtr, switch (InstancePtr->Ep0State) { case XUSBPSU_EP0_SETUP_PHASE: - Xil_DCacheInvalidateRange((INTPTR)&InstancePtr->SetupData, + if (InstancePtr->ConfigPtr->IsCacheCoherent == 0) { + Xil_DCacheInvalidateRange((INTPTR)&InstancePtr->SetupData, sizeof(InstancePtr->SetupData)); + } Length = Ctrl->wLength; if (Length == 0U) { InstancePtr->IsThreeStage = 0U; @@ -300,7 +307,7 @@ void XUsbPsu_Ep0XferComplete(struct XUsbPsu *InstancePtr, Xil_AssertVoid(InstancePtr->Chapter9 != NULL); - InstancePtr->Chapter9(InstancePtr, + InstancePtr->Chapter9(InstancePtr->AppData, &InstancePtr->SetupData); break; @@ -347,7 +354,7 @@ s32 XUsbPsu_Ep0StartStatus(struct XUsbPsu *InstancePtr, Params = XUsbPsu_GetEpParams(InstancePtr); Xil_AssertNonvoid(Params != NULL); if ((Ept->EpStatus & XUSBPSU_EP_BUSY) != 0U) { - return XST_FAILURE; + return (s32)XST_FAILURE; } Type = (InstancePtr->IsThreeStage != 0U) ? XUSBPSU_TRBCTL_CONTROL_STATUS3 @@ -364,7 +371,9 @@ s32 XUsbPsu_Ep0StartStatus(struct XUsbPsu *InstancePtr, | XUSBPSU_TRB_CTRL_IOC | XUSBPSU_TRB_CTRL_ISP_IMI); - Xil_DCacheFlushRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb)); + if (InstancePtr->ConfigPtr->IsCacheCoherent == 0) { + Xil_DCacheFlushRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb)); + } Params->Param0 = 0U; Params->Param1 = (UINTPTR)TrbPtr; @@ -380,7 +389,7 @@ s32 XUsbPsu_Ep0StartStatus(struct XUsbPsu *InstancePtr, Ret = XUsbPsu_SendEpCmd(InstancePtr, 0U, Dir, XUSBPSU_DEPCMD_STARTTRANSFER, Params); if (Ret != XST_SUCCESS) { - return XST_FAILURE; + return (s32)XST_FAILURE; } Ept->EpStatus |= XUSBPSU_EP_BUSY; @@ -543,7 +552,7 @@ s32 XUsbPsu_Ep0Send(struct XUsbPsu *InstancePtr, u8 *BufferPtr, u32 BufferLen) Xil_AssertNonvoid(Params != NULL); if ((Ept->EpStatus & XUSBPSU_EP_BUSY) != 0U) { - return XST_FAILURE; + return (s32)XST_FAILURE; } Ept->RequestedBytes = BufferLen; @@ -565,15 +574,17 @@ s32 XUsbPsu_Ep0Send(struct XUsbPsu *InstancePtr, u8 *BufferPtr, u32 BufferLen) Params->Param0 = 0U; Params->Param1 = (UINTPTR)TrbPtr; - Xil_DCacheFlushRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb)); - Xil_DCacheFlushRange((INTPTR)BufferPtr, BufferLen); + if (InstancePtr->ConfigPtr->IsCacheCoherent == 0) { + Xil_DCacheFlushRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb)); + Xil_DCacheFlushRange((INTPTR)BufferPtr, BufferLen); + } InstancePtr->Ep0State = XUSBPSU_EP0_DATA_PHASE; Ret = XUsbPsu_SendEpCmd(InstancePtr, 0U, XUSBPSU_EP_DIR_IN, XUSBPSU_DEPCMD_STARTTRANSFER, Params); if (Ret != XST_SUCCESS) { - return XST_FAILURE; + return (s32)XST_FAILURE; } Ept->EpStatus |= XUSBPSU_EP_BUSY; @@ -612,7 +623,7 @@ s32 XUsbPsu_Ep0Recv(struct XUsbPsu *InstancePtr, u8 *BufferPtr, u32 Length) Xil_AssertNonvoid(Params != NULL); if ((Ept->EpStatus & XUSBPSU_EP_BUSY) != 0U) { - return XST_FAILURE; + return (s32)XST_FAILURE; } Ept->RequestedBytes = Length; @@ -627,7 +638,7 @@ s32 XUsbPsu_Ep0Recv(struct XUsbPsu *InstancePtr, u8 *BufferPtr, u32 Length) */ if (!IS_ALIGNED(Length, Ept->MaxSize)) { Size = (u32)roundup(Length, Ept->MaxSize); - InstancePtr->UnalignedTx = 1U; + Ept->UnalignedTx = 1U; } TrbPtr = &InstancePtr->Ep0_Trb; @@ -642,8 +653,10 @@ s32 XUsbPsu_Ep0Recv(struct XUsbPsu *InstancePtr, u8 *BufferPtr, u32 Length) | XUSBPSU_TRB_CTRL_IOC | XUSBPSU_TRB_CTRL_ISP_IMI); - Xil_DCacheFlushRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb)); - Xil_DCacheInvalidateRange((INTPTR)BufferPtr, Length); + if (InstancePtr->ConfigPtr->IsCacheCoherent == 0) { + Xil_DCacheFlushRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb)); + Xil_DCacheInvalidateRange((INTPTR)BufferPtr, Length); + } Params->Param0 = 0U; Params->Param1 = (UINTPTR)TrbPtr; @@ -653,7 +666,7 @@ s32 XUsbPsu_Ep0Recv(struct XUsbPsu *InstancePtr, u8 *BufferPtr, u32 Length) Ret = XUsbPsu_SendEpCmd(InstancePtr, 0U, XUSBPSU_EP_DIR_OUT, XUSBPSU_DEPCMD_STARTTRANSFER, Params); if (Ret != XST_SUCCESS) { - return XST_FAILURE; + return (s32)XST_FAILURE; } Ept->EpStatus |= XUSBPSU_EP_BUSY; diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_endpoint.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_4/src/xusbpsu_endpoint.c similarity index 72% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_endpoint.c rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_4/src/xusbpsu_endpoint.c index 41368e526..42e4108c6 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_endpoint.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_4/src/xusbpsu_endpoint.c @@ -33,7 +33,7 @@ /** * * @file xusbpsu_endpoint.c -* @addtogroup usbpsu_v1_0 +* @addtogroup usbpsu_v1_3 * @{ * * @@ -43,32 +43,27 @@ * Ver Who Date Changes * ----- ---- -------- ------------------------------------------------------- * 1.0 sg 06/06/16 First release -* +* 1.3 vak 04/03/17 Added CCI support for USB +* 1.4 bk 12/01/18 Modify USBPSU driver code to fit USB common example code +* for all USB IPs +* myk 12/01/18 Added hibernation support for device mode * * *****************************************************************************/ /***************************** Include Files *********************************/ - -#include "xusbpsu.h" #include "xusbpsu_endpoint.h" -/************************** Constant Definitions *****************************/ +/************************** Constant Definitions *****************************/ /**************************** Type Definitions *******************************/ -/* return Physical EP number as dwc3 mapping */ -#define PhysicalEp(epnum, direction) (((epnum) << 1 ) | (direction)) - /***************** Macros (Inline Functions) Definitions *********************/ - /************************** Function Prototypes ******************************/ - /************************** Variable Definitions *****************************/ - /****************************************************************************/ /** * Returns zeroed parameters to be used by Endpoint commands @@ -233,6 +228,8 @@ s32 XUsbPsu_StartEpConfig(struct XUsbPsu *InstancePtr, u32 UsbEpNum, u8 Dir) * @param Dir is direction of endpoint - XUSBPSU_EP_DIR_IN/XUSBPSU_EP_DIR_OUT. * @param Size is size of Endpoint size. * @param Type is Endpoint type Control/Bulk/Interrupt/Isoc. +* @param Restore should be true if saved state should be restored; +* typically this would be false * * @return XST_SUCCESS else XST_FAILURE. * @@ -240,8 +237,9 @@ s32 XUsbPsu_StartEpConfig(struct XUsbPsu *InstancePtr, u32 UsbEpNum, u8 Dir) * *****************************************************************************/ s32 XUsbPsu_SetEpConfig(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir, - u16 Size, u8 Type) + u16 Size, u8 Type, u8 Restore) { + struct XUsbPsu_Ep *Ept; struct XUsbPsu_EpParams *Params; u8 PhyEpNum; @@ -255,6 +253,7 @@ s32 XUsbPsu_SetEpConfig(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir, Xil_AssertNonvoid(Params != NULL); PhyEpNum = PhysicalEp(UsbEpNum , Dir); + Ept = &InstancePtr->eps[PhyEpNum]; Params->Param0 = XUSBPSU_DEPCFG_EP_TYPE(Type) | XUSBPSU_DEPCFG_MAX_PACKET_SIZE(Size); @@ -262,11 +261,18 @@ s32 XUsbPsu_SetEpConfig(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir, /* * Set burst size to 1 as recommended */ - Params->Param0 |= XUSBPSU_DEPCFG_BURST_SIZE(1); + if (InstancePtr->AppData->Speed == XUSBPSU_SPEED_SUPER) { + Params->Param0 |= XUSBPSU_DEPCFG_BURST_SIZE(1); + } Params->Param1 = XUSBPSU_DEPCFG_XFER_COMPLETE_EN | XUSBPSU_DEPCFG_XFER_NOT_READY_EN; + if (Restore) { + Params->Param0 |= XUSBPSU_DEPCFG_ACTION_RESTORE; + Params->Param2 = Ept->EpSavedState; + } + /* * We are doing 1:1 mapping for endpoints, meaning * Physical Endpoints 2 maps to Logical Endpoint 2 and @@ -279,6 +285,11 @@ s32 XUsbPsu_SetEpConfig(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir, Params->Param0 |= XUSBPSU_DEPCFG_FIFO_NUMBER((u32)PhyEpNum >> 1); } + if (Ept->Type == XUSBPSU_ENDPOINT_XFER_ISOC) { + Params->Param1 |= XUSBPSU_DEPCFG_BINTERVAL_M1(Ept->Interval - 1); + Params->Param1 |= XUSBPSU_DEPCFG_XFER_IN_PROGRESS_EN; + } + return XUsbPsu_SendEpCmd(InstancePtr, UsbEpNum, Dir, XUSBPSU_DEPCMD_SETEPCONFIG, Params); } @@ -325,6 +336,8 @@ s32 XUsbPsu_SetXferResource(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir) * @param Dir is direction of endpoint - XUSBPSU_EP_DIR_IN/XUSBPSU_EP_DIR_OUT. * @param Maxsize is size of Endpoint size. * @param Type is Endpoint type Control/Bulk/Interrupt/Isoc. +* @param Restore should be true if saved state should be restored; +* typically this would be false * * @return XST_SUCCESS else XST_FAILURE. * @@ -332,9 +345,10 @@ s32 XUsbPsu_SetXferResource(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir) * ****************************************************************************/ s32 XUsbPsu_EpEnable(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir, - u16 Maxsize, u8 Type) + u16 Maxsize, u8 Type, u8 Restore) { struct XUsbPsu_Ep *Ept; + struct XUsbPsu_Trb *TrbStHw, *TrbLink; u32 RegVal; s32 Ret = (s32)XST_FAILURE; u32 PhyEpNum; @@ -353,20 +367,28 @@ s32 XUsbPsu_EpEnable(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir, Ept->Type = Type; Ept->MaxSize = Maxsize; Ept->PhyEpNum = (u8)PhyEpNum; + Ept->CurUf = 0; + if (!InstancePtr->IsHibernated) { + Ept->TrbEnqueue = 0; + Ept->TrbDequeue = 0; + } - if ((Ept->EpStatus & XUSBPSU_EP_ENABLED) == 0U) { + if (((Ept->EpStatus & XUSBPSU_EP_ENABLED) == 0U) + || (InstancePtr->IsHibernated)) { Ret = XUsbPsu_StartEpConfig(InstancePtr, UsbEpNum, Dir); if (Ret != 0) { return Ret; } } - Ret = XUsbPsu_SetEpConfig(InstancePtr, UsbEpNum, Dir, Maxsize, Type); + Ret = XUsbPsu_SetEpConfig(InstancePtr, UsbEpNum, Dir, Maxsize, + Type, Restore); if (Ret != 0) { return Ret; } - if ((Ept->EpStatus & XUSBPSU_EP_ENABLED) == 0U) { + if (((Ept->EpStatus & XUSBPSU_EP_ENABLED) == 0U) + || (InstancePtr->IsHibernated)) { Ret = XUsbPsu_SetXferResource(InstancePtr, UsbEpNum, Dir); if (Ret != 0) { return Ret; @@ -377,6 +399,18 @@ s32 XUsbPsu_EpEnable(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir, RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DALEPENA); RegVal |= XUSBPSU_DALEPENA_EP(Ept->PhyEpNum); XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DALEPENA, RegVal); + + /* Following code is only applicable for ISO XFER */ + TrbStHw = &Ept->EpTrb[0]; + + /* Link TRB. The HWO bit is never reset */ + TrbLink = &Ept->EpTrb[NO_OF_TRB_PER_EP]; + memset(TrbLink, 0x00, sizeof(struct XUsbPsu_Trb)); + + TrbLink->BufferPtrLow = (UINTPTR)TrbStHw; + TrbLink->BufferPtrHigh = ((UINTPTR)TrbStHw >> 16) >> 16; + TrbLink->Ctrl |= XUSBPSU_TRBCTL_LINK_TRB; + TrbLink->Ctrl |= XUSBPSU_TRB_CTRL_HWO; } return XST_SUCCESS; @@ -410,6 +444,10 @@ s32 XUsbPsu_EpDisable(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir) PhyEpNum = PhysicalEp(UsbEpNum , Dir); Ept = &InstancePtr->eps[PhyEpNum]; + /* make sure HW endpoint isn't stalled */ + if (Ept->EpStatus & XUSBPSU_EP_STALL) + XUsbPsu_EpClearStall(InstancePtr, Ept->UsbEpNum, Ept->Direction); + RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DALEPENA); RegVal &= ~XUSBPSU_DALEPENA_EP(PhyEpNum); XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DALEPENA, RegVal); @@ -417,6 +455,8 @@ s32 XUsbPsu_EpDisable(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir) Ept->Type = 0U; Ept->EpStatus = 0U; Ept->MaxSize = 0U; + Ept->TrbEnqueue = 0U; + Ept->TrbDequeue = 0U; return XST_SUCCESS; } @@ -441,13 +481,13 @@ s32 XUsbPsu_EnableControlEp(struct XUsbPsu *InstancePtr, u16 Size) Xil_AssertNonvoid((Size >= 64U) && (Size <= 512U)); RetVal = XUsbPsu_EpEnable(InstancePtr, 0U, XUSBPSU_EP_DIR_OUT, Size, - XUSBPSU_ENDPOINT_XFER_CONTROL); + XUSBPSU_ENDPOINT_XFER_CONTROL, FALSE); if (RetVal != 0) { return XST_FAILURE; } RetVal = XUsbPsu_EpEnable(InstancePtr, 0U, XUSBPSU_EP_DIR_IN, Size, - XUSBPSU_ENDPOINT_XFER_CONTROL); + XUSBPSU_ENDPOINT_XFER_CONTROL, FALSE); if (RetVal != 0) { return XST_FAILURE; } @@ -479,11 +519,13 @@ void XUsbPsu_InitializeEps(struct XUsbPsu *InstancePtr) Epnum = (i << 1U) | XUSBPSU_EP_DIR_OUT; InstancePtr->eps[Epnum].PhyEpNum = Epnum; InstancePtr->eps[Epnum].Direction = XUSBPSU_EP_DIR_OUT; + InstancePtr->eps[Epnum].ResourceIndex = 0; } for (i = 0U; i < InstancePtr->NumInEps; i++) { Epnum = (i << 1U) | XUSBPSU_EP_DIR_IN; InstancePtr->eps[Epnum].PhyEpNum = Epnum; InstancePtr->eps[Epnum].Direction = XUSBPSU_EP_DIR_IN; + InstancePtr->eps[Epnum].ResourceIndex = 0; } } @@ -494,13 +536,15 @@ void XUsbPsu_InitializeEps(struct XUsbPsu *InstancePtr) * @param InstancePtr is a pointer to the XUsbPsu instance. * @param UsbEpNum is USB endpoint number. * @param Dir is direction of endpoint - XUSBPSU_EP_DIR_IN/XUSBPSU_EP_DIR_OUT. +* @Force Force flag to stop/pause transfer. * * @return None. * * @note None. * ****************************************************************************/ -void XUsbPsu_StopTransfer(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir) +void XUsbPsu_StopTransfer(struct XUsbPsu *InstancePtr, u8 UsbEpNum, + u8 Dir, u8 Force) { struct XUsbPsu_Ep *Ept; struct XUsbPsu_EpParams *Params; @@ -526,15 +570,37 @@ void XUsbPsu_StopTransfer(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir) * - Wait 100us */ Cmd = XUSBPSU_DEPCMD_ENDTRANSFER; + Cmd |= Force ? XUSBPSU_DEPCMD_HIPRI_FORCERM : 0; Cmd |= XUSBPSU_DEPCMD_CMDIOC; Cmd |= XUSBPSU_DEPCMD_PARAM(Ept->ResourceIndex); - (void)XUsbPsu_SendEpCmd(InstancePtr, Ept->PhyEpNum, Ept->Direction, + (void)XUsbPsu_SendEpCmd(InstancePtr, Ept->UsbEpNum, Ept->Direction, Cmd, Params); - Ept->ResourceIndex = 0U; + if (Force) + Ept->ResourceIndex = 0U; Ept->EpStatus &= ~XUSBPSU_EP_BUSY; XUsbSleep(100U); } +/****************************************************************************/ +/** +* Query endpoint state and save it in EpSavedState +* +* @param InstancePtr is a pointer to the XUsbPsu instance. +* @param Ept is a pointer to the XUsbPsu pointer structure. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void XUsbPsu_SaveEndpointState(struct XUsbPsu *InstancePtr, struct XUsbPsu_Ep *Ept) +{ + struct XUsbPsu_EpParams *Params = XUsbPsu_GetEpParams(InstancePtr); + XUsbPsu_SendEpCmd(InstancePtr, Ept->UsbEpNum, Ept->Direction, + XUSBPSU_DEPCMD_GETEPSTATE, Params); + Ept->EpSavedState = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DEPCMDPAR2(Ept->PhyEpNum)); +} + /****************************************************************************/ /** * Clears Stall on all endpoints. @@ -570,7 +636,7 @@ void XUsbPsu_ClearStalls(struct XUsbPsu *InstancePtr) Ept->EpStatus &= ~XUSBPSU_EP_STALL; - (void)XUsbPsu_SendEpCmd(InstancePtr, Ept->PhyEpNum, + (void)XUsbPsu_SendEpCmd(InstancePtr, Ept->UsbEpNum, Ept->Direction, XUSBPSU_DEPCMD_CLEARSTALL, Params); } @@ -594,6 +660,7 @@ s32 XUsbPsu_EpBufferSend(struct XUsbPsu *InstancePtr, u8 UsbEp, u8 *BufferPtr, u32 BufferLen) { u8 PhyEpNum; + u32 cmd; s32 RetVal; struct XUsbPsu_Trb *TrbPtr; struct XUsbPsu_Ep *Ept; @@ -619,35 +686,98 @@ s32 XUsbPsu_EpBufferSend(struct XUsbPsu *InstancePtr, u8 UsbEp, Ept->BytesTxed = 0U; Ept->BufferPtr = BufferPtr; - TrbPtr = &Ept->EpTrb; + TrbPtr = &Ept->EpTrb[Ept->TrbEnqueue]; Xil_AssertNonvoid(TrbPtr != NULL); + Ept->TrbEnqueue++; + if (Ept->TrbEnqueue == NO_OF_TRB_PER_EP) + Ept->TrbEnqueue = 0; TrbPtr->BufferPtrLow = (UINTPTR)BufferPtr; TrbPtr->BufferPtrHigh = ((UINTPTR)BufferPtr >> 16) >> 16; TrbPtr->Size = BufferLen & XUSBPSU_TRB_SIZE_MASK; - TrbPtr->Ctrl = XUSBPSU_TRBCTL_NORMAL; + + switch (Ept->Type) { + case XUSBPSU_ENDPOINT_XFER_ISOC: + /* + * According to DWC3 datasheet, XUSBPSU_TRBCTL_ISOCHRONOUS and + * XUSBPSU_TRBCTL_CHN fields are only set when request has + * scattered list so these fields are not set over here. + */ + TrbPtr->Ctrl = (XUSBPSU_TRBCTL_ISOCHRONOUS_FIRST + | XUSBPSU_TRB_CTRL_CSP); + + break; + case XUSBPSU_ENDPOINT_XFER_INT: + case XUSBPSU_ENDPOINT_XFER_BULK: + TrbPtr->Ctrl = (XUSBPSU_TRBCTL_NORMAL + | XUSBPSU_TRB_CTRL_LST); + + break; + } TrbPtr->Ctrl |= (XUSBPSU_TRB_CTRL_HWO - | XUSBPSU_TRB_CTRL_LST - | XUSBPSU_TRB_CTRL_IOC - | XUSBPSU_TRB_CTRL_ISP_IMI); + | XUSBPSU_TRB_CTRL_IOC + | XUSBPSU_TRB_CTRL_ISP_IMI); - Xil_DCacheFlushRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb)); - Xil_DCacheFlushRange((INTPTR)BufferPtr, BufferLen); + if (InstancePtr->ConfigPtr->IsCacheCoherent == 0) { + Xil_DCacheFlushRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb)); + Xil_DCacheFlushRange((INTPTR)BufferPtr, BufferLen); + } Params = XUsbPsu_GetEpParams(InstancePtr); Xil_AssertNonvoid(Params != NULL); Params->Param0 = 0U; Params->Param1 = (UINTPTR)TrbPtr; + if (Ept->EpStatus & XUSBPSU_EP_BUSY) { + cmd = XUSBPSU_DEPCMD_UPDATETRANSFER; + cmd |= XUSBPSU_DEPCMD_PARAM(Ept->ResourceIndex); + } else { + if (Ept->Type == XUSBPSU_ENDPOINT_XFER_ISOC) { + BufferPtr += BufferLen; + struct XUsbPsu_Trb *TrbTempNext; + TrbTempNext = &Ept->EpTrb[Ept->TrbEnqueue]; + Xil_AssertNonvoid(TrbTempNext != NULL); + + Ept->TrbEnqueue++; + if (Ept->TrbEnqueue == NO_OF_TRB_PER_EP) + Ept->TrbEnqueue = 0; + TrbTempNext->BufferPtrLow = (UINTPTR)BufferPtr; + TrbTempNext->BufferPtrHigh = ((UINTPTR)BufferPtr >> 16) >> 16; + TrbTempNext->Size = BufferLen & XUSBPSU_TRB_SIZE_MASK; + + TrbTempNext->Ctrl = (XUSBPSU_TRBCTL_ISOCHRONOUS_FIRST + | XUSBPSU_TRB_CTRL_CSP + | XUSBPSU_TRB_CTRL_HWO + | XUSBPSU_TRB_CTRL_IOC + | XUSBPSU_TRB_CTRL_ISP_IMI); + + if (InstancePtr->ConfigPtr->IsCacheCoherent == 0) { + Xil_DCacheFlushRange((INTPTR)TrbTempNext, + sizeof(struct XUsbPsu_Trb)); + Xil_DCacheFlushRange((INTPTR)BufferPtr, BufferLen); + } + + } + + cmd = XUSBPSU_DEPCMD_STARTTRANSFER; + cmd |= XUSBPSU_DEPCMD_PARAM(Ept->CurUf); + } + RetVal = XUsbPsu_SendEpCmd(InstancePtr, UsbEp, Ept->Direction, - XUSBPSU_DEPCMD_STARTTRANSFER, Params); + cmd, Params); if (RetVal != XST_SUCCESS) { return XST_FAILURE; } - Ept->ResourceIndex = (u8)XUsbPsu_EpGetTransferIndex(InstancePtr, - Ept->UsbEpNum, - Ept->Direction); + + if (!(Ept->EpStatus & XUSBPSU_EP_BUSY)) { + Ept->ResourceIndex = (u8)XUsbPsu_EpGetTransferIndex(InstancePtr, + Ept->UsbEpNum, + Ept->Direction); + + Ept->EpStatus |= XUSBPSU_EP_BUSY; + } + return XST_SUCCESS; } @@ -656,7 +786,7 @@ s32 XUsbPsu_EpBufferSend(struct XUsbPsu *InstancePtr, u8 UsbEp, * Initiates DMA to receive data on Endpoint from Host. * * @param InstancePtr is a pointer to the XUsbPsu instance. -* @param EpNum is USB endpoint number. +* @param UsbEp is USB endpoint number. * @param BufferPtr is pointer to data. * @param Length is length of data to be received. * @@ -669,7 +799,8 @@ s32 XUsbPsu_EpBufferRecv(struct XUsbPsu *InstancePtr, u8 UsbEp, u8 *BufferPtr, u32 Length) { u8 PhyEpNum; - u32 Size; + u32 cmd; + u32 Size; s32 RetVal; struct XUsbPsu_Trb *TrbPtr; struct XUsbPsu_Ep *Ept; @@ -706,36 +837,100 @@ s32 XUsbPsu_EpBufferRecv(struct XUsbPsu *InstancePtr, u8 UsbEp, Ept->UnalignedTx = 1U; } - TrbPtr = &Ept->EpTrb; + TrbPtr = &Ept->EpTrb[Ept->TrbEnqueue]; Xil_AssertNonvoid(TrbPtr != NULL); + Ept->TrbEnqueue++; + if (Ept->TrbEnqueue == NO_OF_TRB_PER_EP) + Ept->TrbEnqueue = 0; + TrbPtr->BufferPtrLow = (UINTPTR)BufferPtr; TrbPtr->BufferPtrHigh = ((UINTPTR)BufferPtr >> 16) >> 16; TrbPtr->Size = Size; - TrbPtr->Ctrl = XUSBPSU_TRBCTL_NORMAL; + + switch (Ept->Type) { + case XUSBPSU_ENDPOINT_XFER_ISOC: + /* + * According to Linux driver, XUSBPSU_TRBCTL_ISOCHRONOUS and + * XUSBPSU_TRBCTL_CHN fields are only set when request has + * scattered list so these fields are not set over here. + */ + TrbPtr->Ctrl = (XUSBPSU_TRBCTL_ISOCHRONOUS_FIRST + | XUSBPSU_TRB_CTRL_CSP); + + break; + case XUSBPSU_ENDPOINT_XFER_INT: + case XUSBPSU_ENDPOINT_XFER_BULK: + TrbPtr->Ctrl = (XUSBPSU_TRBCTL_NORMAL + | XUSBPSU_TRB_CTRL_LST); + + break; + } TrbPtr->Ctrl |= (XUSBPSU_TRB_CTRL_HWO - | XUSBPSU_TRB_CTRL_LST - | XUSBPSU_TRB_CTRL_IOC - | XUSBPSU_TRB_CTRL_ISP_IMI); + | XUSBPSU_TRB_CTRL_IOC + | XUSBPSU_TRB_CTRL_ISP_IMI); - Xil_DCacheFlushRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb)); - Xil_DCacheInvalidateRange((INTPTR)BufferPtr, Length); + if (InstancePtr->ConfigPtr->IsCacheCoherent == 0) { + Xil_DCacheFlushRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb)); + Xil_DCacheInvalidateRange((INTPTR)BufferPtr, Length); + } Params = XUsbPsu_GetEpParams(InstancePtr); Xil_AssertNonvoid(Params != NULL); Params->Param0 = 0U; Params->Param1 = (UINTPTR)TrbPtr; + if (Ept->EpStatus & XUSBPSU_EP_BUSY) { + cmd = XUSBPSU_DEPCMD_UPDATETRANSFER; + cmd |= XUSBPSU_DEPCMD_PARAM(Ept->ResourceIndex); + } else { + if (Ept->Type == XUSBPSU_ENDPOINT_XFER_ISOC) { + BufferPtr += Length; + struct XUsbPsu_Trb *TrbTempNext; + TrbTempNext = &Ept->EpTrb[Ept->TrbEnqueue]; + Xil_AssertNonvoid(TrbTempNext != NULL); + + Ept->TrbEnqueue++; + if (Ept->TrbEnqueue == NO_OF_TRB_PER_EP) + Ept->TrbEnqueue = 0; + TrbTempNext->BufferPtrLow = (UINTPTR)BufferPtr; + TrbTempNext->BufferPtrHigh = ((UINTPTR)BufferPtr >> 16) >> 16; + TrbTempNext->Size = Length & XUSBPSU_TRB_SIZE_MASK; + + TrbTempNext->Ctrl = (XUSBPSU_TRBCTL_ISOCHRONOUS_FIRST + | XUSBPSU_TRB_CTRL_CSP + | XUSBPSU_TRB_CTRL_HWO + | XUSBPSU_TRB_CTRL_IOC + | XUSBPSU_TRB_CTRL_ISP_IMI); + + if (InstancePtr->ConfigPtr->IsCacheCoherent == 0) { + Xil_DCacheFlushRange((INTPTR)TrbTempNext, + sizeof(struct XUsbPsu_Trb)); + Xil_DCacheFlushRange((INTPTR)BufferPtr, Length); + } + + } + + cmd = XUSBPSU_DEPCMD_STARTTRANSFER; + cmd |= XUSBPSU_DEPCMD_PARAM(Ept->CurUf); + } + RetVal = XUsbPsu_SendEpCmd(InstancePtr, UsbEp, Ept->Direction, - XUSBPSU_DEPCMD_STARTTRANSFER, Params); + cmd, Params); if (RetVal != XST_SUCCESS) { return XST_FAILURE; } - Ept->ResourceIndex = (u8)XUsbPsu_EpGetTransferIndex(InstancePtr, - Ept->UsbEpNum, - Ept->Direction); + + if (!(Ept->EpStatus & XUSBPSU_EP_BUSY)) { + Ept->ResourceIndex = (u8)XUsbPsu_EpGetTransferIndex(InstancePtr, + Ept->UsbEpNum, + Ept->Direction); + + Ept->EpStatus |= XUSBPSU_EP_BUSY; + } + return XST_SUCCESS; } @@ -744,7 +939,7 @@ s32 XUsbPsu_EpBufferRecv(struct XUsbPsu *InstancePtr, u8 UsbEp, * Stalls an Endpoint. * * @param InstancePtr is a pointer to the XUsbPsu instance. -* @param EpNum is USB endpoint number. +* @param Epnum is USB endpoint number. * @param Dir is direction. * * @return None. @@ -768,7 +963,7 @@ void XUsbPsu_EpSetStall(struct XUsbPsu *InstancePtr, u8 Epnum, u8 Dir) Params = XUsbPsu_GetEpParams(InstancePtr); Xil_AssertVoid(Params != NULL); - (void)XUsbPsu_SendEpCmd(InstancePtr, Ept->PhyEpNum, Ept->Direction, + (void)XUsbPsu_SendEpCmd(InstancePtr, Ept->UsbEpNum, Ept->Direction, XUSBPSU_DEPCMD_SETSTALL, Params); Ept->EpStatus |= XUSBPSU_EP_STALL; @@ -803,7 +998,7 @@ void XUsbPsu_EpClearStall(struct XUsbPsu *InstancePtr, u8 Epnum, u8 Dir) Params = XUsbPsu_GetEpParams(InstancePtr); Xil_AssertVoid(Params != NULL); - (void)XUsbPsu_SendEpCmd(InstancePtr, Ept->PhyEpNum, Ept->Direction, + (void)XUsbPsu_SendEpCmd(InstancePtr, Ept->UsbEpNum, Ept->Direction, XUSBPSU_DEPCMD_CLEARSTALL, Params); Ept->EpStatus &= ~XUSBPSU_EP_STALL; @@ -895,10 +1090,20 @@ void XUsbPsu_EpXferComplete(struct XUsbPsu *InstancePtr, Epnum = Event->Epnumber; Ept = &InstancePtr->eps[Epnum]; Dir = Ept->Direction; - TrbPtr = &Ept->EpTrb; + TrbPtr = &Ept->EpTrb[Ept->TrbDequeue]; Xil_AssertVoid(TrbPtr != NULL); - Xil_DCacheInvalidateRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb)); + Ept->TrbDequeue++; + if (Ept->TrbDequeue == NO_OF_TRB_PER_EP) + Ept->TrbDequeue = 0; + + if (InstancePtr->ConfigPtr->IsCacheCoherent == 0) + Xil_DCacheInvalidateRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb)); + + if (Event->Endpoint_Event == XUSBPSU_DEPEVT_XFERCOMPLETE) { + Ept->EpStatus &= ~(XUSBPSU_EP_BUSY); + Ept->ResourceIndex = 0; + } Length = TrbPtr->Size & XUSBPSU_TRB_SIZE_MASK; @@ -909,19 +1114,64 @@ void XUsbPsu_EpXferComplete(struct XUsbPsu *InstancePtr, Ept->BytesTxed = Ept->RequestedBytes - Length; } else if (Dir == XUSBPSU_EP_DIR_OUT) { if (Ept->UnalignedTx == 1U) { - Ept->BytesTxed = Ept->RequestedBytes; + Ept->BytesTxed = (u32)roundup(Ept->RequestedBytes, + Ept->MaxSize); + Ept->BytesTxed -= Length; Ept->UnalignedTx = 0U; + } else { + /* + * Get the actual number of bytes transmitted + * by host + */ + Ept->BytesTxed = Ept->RequestedBytes - Length; } } } if (Dir == XUSBPSU_EP_DIR_OUT) { /* Invalidate Cache */ - Xil_DCacheInvalidateRange((INTPTR)Ept->BufferPtr, Ept->BytesTxed); + if (InstancePtr->ConfigPtr->IsCacheCoherent == 0) + Xil_DCacheInvalidateRange((INTPTR)Ept->BufferPtr, Ept->BytesTxed); } if (Ept->Handler != NULL) { - Ept->Handler(InstancePtr, Ept->RequestedBytes, Ept->BytesTxed); + Ept->Handler(InstancePtr->AppData, Ept->RequestedBytes, Ept->BytesTxed); + } +} + +/****************************************************************************/ +/** +* For Isochronous transfer, get the microframe time and calls respective Endpoint +* handler. +* +* @param InstancePtr is a pointer to the XUsbPsu instance. +* @param Event is a pointer to the Endpoint event occurred in core. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void XUsbPsu_EpXferNotReady(struct XUsbPsu *InstancePtr, + const struct XUsbPsu_Event_Epevt *Event) +{ + struct XUsbPsu_Ep *Ept; + u32 Epnum; + u32 CurUf, Mask; + + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(Event != NULL); + + Epnum = Event->Epnumber; + Ept = &InstancePtr->eps[Epnum]; + + if (Ept->Type == XUSBPSU_ENDPOINT_XFER_ISOC) { + Mask = ~(1 << (Ept->Interval - 1)); + CurUf = Event->Parameters & Mask; + Ept->CurUf = CurUf + (Ept->Interval * 4); + if (Ept->Handler != NULL) { + Ept->Handler(InstancePtr->AppData, 0, 0); + } } } /** @} */ diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_endpoint.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_4/src/xusbpsu_endpoint.h similarity index 98% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_endpoint.h rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_4/src/xusbpsu_endpoint.h index 299837862..b80da4832 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_endpoint.h +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_4/src/xusbpsu_endpoint.h @@ -33,7 +33,7 @@ /** * * @file xusbps_endpoint.h -* @addtogroup usbpsu_v1_0 +* @addtogroup usbpsu_v1_3 * @{ * * This is an internal file containing the definitions for endpoints. It is @@ -46,6 +46,9 @@ * Ver Who Date Changes * ----- ---- -------- -------------------------------------------------------- * 1.0 sg 06/06/16 First release + * 1.4 bk 12/01/18 Modify USBPSU driver code to fit USB common example code + * for all USB IPs. + * * * ******************************************************************************/ @@ -59,7 +62,7 @@ extern "C" { /***************************** Include Files *********************************/ #include "xil_cache.h" -#include "xusbpsu.h" +#include "xusb_wrapper.h" #include "xil_types.h" /**************************** Type Definitions *******************************/ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_1/src/xusbpsu_g.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_4/src/xusbpsu_g.c similarity index 86% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_1/src/xusbpsu_g.c rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_4/src/xusbpsu_g.c index 41a9b8c7a..4019d76df 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_1/src/xusbpsu_g.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_4/src/xusbpsu_g.c @@ -5,7 +5,7 @@ * Version: * DO NOT EDIT. * -* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.* +* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.* *Permission is hereby granted, free of charge, to any person obtaining a copy *of this software and associated documentation files (the Software), to deal *in the Software without restriction, including without limitation the rights @@ -44,11 +44,12 @@ * The configuration table for devices */ -XUsbPsu_Config XUsbPsu_ConfigTable[] = +XUsbPsu_Config XUsbPsu_ConfigTable[XPAR_XUSBPSU_NUM_INSTANCES] = { { - XPAR_PSU_USB_0_DEVICE_ID, - XPAR_PSU_USB_0_BASEADDR + XPAR_PSU_USB_XHCI_0_DEVICE_ID, + XPAR_PSU_USB_XHCI_0_BASEADDR, + XPAR_PSU_USB_XHCI_0_IS_CACHE_COHERENT } }; diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_4/src/xusbpsu_hibernation.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_4/src/xusbpsu_hibernation.c new file mode 100644 index 000000000..20f53c974 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_4/src/xusbpsu_hibernation.c @@ -0,0 +1,688 @@ +/****************************************************************************** +* +* Copyright (C) 2017 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xusbpsu_hibernation.c +* +* This patch adds hibernation support to usbpsu driver when dwc3 is operating +* as a gadget +* +* 
+*
+* MODIFICATION HISTORY:
+*
+* Ver    Who    Date     Changes
+* ----- -----  -------- -----------------------------------------------------
+* 1.0   Mayank 12/01/18 First release
+*
+*
+* +*****************************************************************************/ + +/***************************** Include Files ********************************/ + +#include "xusbpsu.h" +#include "xusbpsu_hw.h" +#include "xusbpsu_endpoint.h" + +/************************** Constant Definitions *****************************/ + +#define NUM_OF_NONSTICKY_REGS 27 + +#define XUSBPSU_HIBER_SCRATCHBUF_SIZE 4096U + +#define XUSBPSU_NON_STICKY_SAVE_RETRIES 500U +#define XUSBPSU_PWR_STATE_RETRIES 1500U +#define XUSBPSU_CTRL_RDY_RETRIES 5000U +#define XUSBPSU_TIMEOUT 1000U + +/**************************** Type Definitions *******************************/ + + +/***************** Macros (Inline Functions) Definitions *********************/ + + +/************************** Function Prototypes ******************************/ + + +/************************** Variable Definitions *****************************/ + +static u8 ScratchBuf[XUSBPSU_HIBER_SCRATCHBUF_SIZE]; + +/* Registers saved during hibernation and restored at wakeup */ +static u32 save_reg_addr[] = { + XUSBPSU_DCTL, + XUSBPSU_DCFG, + XUSBPSU_DEVTEN, + XUSBPSU_GSBUSCFG0, + XUSBPSU_GSBUSCFG1, + XUSBPSU_GCTL, + XUSBPSU_GTXTHRCFG, + XUSBPSU_GRXTHRCFG, + XUSBPSU_GTXFIFOSIZ(0), + XUSBPSU_GTXFIFOSIZ(1), + XUSBPSU_GTXFIFOSIZ(2), + XUSBPSU_GTXFIFOSIZ(3), + XUSBPSU_GTXFIFOSIZ(4), + XUSBPSU_GTXFIFOSIZ(5), + XUSBPSU_GTXFIFOSIZ(6), + XUSBPSU_GTXFIFOSIZ(7), + XUSBPSU_GTXFIFOSIZ(8), + XUSBPSU_GTXFIFOSIZ(9), + XUSBPSU_GTXFIFOSIZ(10), + XUSBPSU_GTXFIFOSIZ(11), + XUSBPSU_GTXFIFOSIZ(12), + XUSBPSU_GTXFIFOSIZ(13), + XUSBPSU_GTXFIFOSIZ(14), + XUSBPSU_GTXFIFOSIZ(15), + XUSBPSU_GRXFIFOSIZ(0), + XUSBPSU_GUSB3PIPECTL(0), + XUSBPSU_GUSB2PHYCFG(0), +}; +static u32 saved_regs[NUM_OF_NONSTICKY_REGS]; + +/*****************************************************************************/ +/** +* Save non sticky registers +* +* @param InstancePtr is a pointer to the XUsbPsu instance to be worked +* on. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +static void save_regs(struct XUsbPsu *InstancePtr) +{ + u32 i; + + for (i = 0; i < NUM_OF_NONSTICKY_REGS; i++) + saved_regs[i] = XUsbPsu_ReadReg(InstancePtr, save_reg_addr[i]); +} + +/*****************************************************************************/ +/** +* Restore non sticky registers +* +* @param InstancePtr is a pointer to the XUsbPsu instance to be worked +* on. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +static void restore_regs(struct XUsbPsu *InstancePtr) +{ + u32 i; + + for (i = 0; i < NUM_OF_NONSTICKY_REGS; i++) + XUsbPsu_WriteReg(InstancePtr, save_reg_addr[i], saved_regs[i]); +} + +/*****************************************************************************/ +/** +* Send generic command for gadget +* +* @param InstancePtr is a pointer to the XUsbPsu instance to be worked +* on. +* @param cmd is command to be sent +* @param param is parameter for the command, to be written in DGCMDPAR +* register +* +* @return +* - XST_SUCCESS on success +* - XST_FAILURE on timeout +* - XST_REGISTER_ERROR on status error +* +* @note None. +* +******************************************************************************/ +s32 XUsbPsu_SendGadgetGenericCmd(struct XUsbPsu *InstancePtr, u32 cmd, + u32 param) +{ + u32 RegVal, retry = 500; + XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DGCMDPAR, param); + XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DGCMD, cmd | XUSBPSU_DGCMD_CMDACT); + + do { + RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DGCMD); + if (!(RegVal & XUSBPSU_DGCMD_CMDACT)) { + if (XUSBPSU_DGCMD_STATUS(RegVal)) + return XST_REGISTER_ERROR; + return 0; + } + } while (--retry); + + return XST_FAILURE; +} + +/*****************************************************************************/ +/** +* Sets scratchpad buffers +* +* @param InstancePtr is a pointer to the XUsbPsu instance to be worked +* on. +* +* @return XST_SUCCESS on success or else error code +* +* @note None. +* +******************************************************************************/ +s32 XUsbPsu_SetupScratchpad(struct XUsbPsu *InstancePtr) +{ + s32 Ret; + Ret = XUsbPsu_SendGadgetGenericCmd(InstancePtr, + XUSBPSU_DGCMD_SET_SCRATCHPAD_ADDR_LO, (UINTPTR)ScratchBuf & 0xffffffff); + if (Ret) { + xil_printf("Failed to set scratchpad low addr: %d\n", Ret); + return Ret; + } + + Ret = XUsbPsu_SendGadgetGenericCmd(InstancePtr, + XUSBPSU_DGCMD_SET_SCRATCHPAD_ADDR_HI, ((UINTPTR)ScratchBuf >> 16) >> 16); + if (Ret) { + xil_printf("Failed to set scratchpad high addr: %d\n", Ret); + return Ret; + } + + return XST_SUCCESS; +} + +/*****************************************************************************/ +/** +* Initialize to handle hibernation event when it comes +* +* @param InstancePtr is a pointer to the XUsbPsu instance to be worked +* on. +* +* @return none +* +* @note None. +* +******************************************************************************/ +void XUsbPsu_InitHibernation(struct XUsbPsu *InstancePtr) +{ + u32 RegVal; + + InstancePtr->IsHibernated = 0; + + memset(ScratchBuf, 0, sizeof(ScratchBuf)); + if (InstancePtr->ConfigPtr->IsCacheCoherent == 0) + Xil_DCacheFlushRange((INTPTR)ScratchBuf, XUSBPSU_HIBER_SCRATCHBUF_SIZE); + + XUsbPsu_SetupScratchpad(InstancePtr); + + /* enable PHY suspend */ + RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GUSB2PHYCFG(0)); + RegVal |= XUSBPSU_GUSB2PHYCFG_SUSPHY; + XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GUSB2PHYCFG(0), RegVal); + + RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GUSB3PIPECTL(0)); + RegVal |= XUSBPSU_GUSB3PIPECTL_SUSPHY; + XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GUSB3PIPECTL(0), RegVal); +} + +/*****************************************************************************/ +/** +* Handle hibernation event +* +* @param InstancePtr is a pointer to the XUsbPsu instance to be worked +* on. +* +* @return none +* +* @note None. +* +******************************************************************************/ +void Xusbpsu_HibernationIntr(struct XUsbPsu *InstancePtr) +{ + u8 EpNum; + u32 RegVal; + s32 retries; + XusbPsuLinkState LinkState; + + /* sanity check */ + switch(XUsbPsu_GetLinkState(InstancePtr)) { + case XUSBPSU_LINK_STATE_SS_DIS: + case XUSBPSU_LINK_STATE_U3: + break; + default: + /* fake hiber interrupt */ + xil_printf("got fake interrupt\r\n"); + return; + }; + + if (InstancePtr->Ep0State == XUSBPSU_EP0_SETUP_PHASE) { + XUsbPsu_StopTransfer(InstancePtr, 0, XUSBPSU_EP_DIR_OUT, TRUE); + XUsbPsu_RecvSetup(InstancePtr); + } + + /* stop active transfers for all endpoints including control + * endpoints force rm bit should be 0 when we do this */ + for (EpNum = 0; EpNum < XUSBPSU_ENDPOINTS_NUM; EpNum++) { + struct XUsbPsu_Ep *Ept; + + Ept = &InstancePtr->eps[EpNum]; + if (!Ept) + continue; + + if (!(Ept->EpStatus & XUSBPSU_EP_ENABLED)) + continue; + + /* save srsource index for later use */ + XUsbPsu_StopTransfer(InstancePtr, Ept->UsbEpNum, + Ept->Direction, FALSE); + + XUsbPsu_SaveEndpointState(InstancePtr, Ept); + } + + /* + * ack events, don't process them; h/w decrements the count by the value + * written + */ + RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GEVNTCOUNT(0)); + XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTCOUNT(0), RegVal); + InstancePtr->Evt.Count = 0; + InstancePtr->Evt.Flags &= ~XUSBPSU_EVENT_PENDING; + + if (XUsbPsu_Stop(InstancePtr)) { + xil_printf("Failed to stop USB core\r\n"); + return; + } + + RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL); + + /* Check the link state and if it is disconnected, set + * KEEP_CONNECT to 0 + */ + LinkState = XUsbPsu_GetLinkState(InstancePtr); + if (LinkState == XUSBPSU_LINK_STATE_SS_DIS) { + RegVal &= ~XUSBPSU_DCTL_KEEP_CONNECT; + XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal); + + /* update LinkState to be used while wakeup */ + InstancePtr->LinkState = XUSBPSU_LINK_STATE_SS_DIS; + } + + save_regs(InstancePtr); + + /* ask core to save state */ + RegVal |= XUSBPSU_DCTL_CSS; + XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal); + + /* wait till core saves */ + if (XUsbPsu_Wait_Clear_Timeout(InstancePtr, XUSBPSU_DSTS, + XUSBPSU_DSTS_SSS, XUSBPSU_NON_STICKY_SAVE_RETRIES) == XST_FAILURE) { + xil_printf("Failed to save core state\r\n"); + return; + } + + /* Enable PME to wakeup from hibernation */ + XUsbPsu_WriteVendorReg(XIL_PME_ENABLE, XIL_PME_ENABLE_SIG_GEN); + + /* change power state to D3 */ + XUsbPsu_WriteVendorReg(XIL_REQ_PWR_STATE, XIL_REQ_PWR_STATE_D3); + + /* wait till current state is changed to D3 */ + retries = XUSBPSU_PWR_STATE_RETRIES; + do { + RegVal = XUsbPsu_ReadVendorReg(XIL_CUR_PWR_STATE); + if ((RegVal & XIL_CUR_PWR_STATE_BITMASK) == XIL_CUR_PWR_STATE_D3) + break; + + XUsbSleep(XUSBPSU_TIMEOUT); + } while (--retries); + + if (retries < 0) { + xil_printf("Failed to change power state to D3\r\n"); + return; + } + XUsbSleep(XUSBPSU_TIMEOUT); + + RegVal = XUsbPsu_ReadLpdReg(RST_LPD_TOP); + if (InstancePtr->ConfigPtr->DeviceId == XPAR_XUSBPSU_0_DEVICE_ID) + XUsbPsu_WriteLpdReg(RST_LPD_TOP, RegVal | USB0_CORE_RST); + + InstancePtr->IsHibernated = 1; + xil_printf("Hibernated!\r\n"); +} + +/*****************************************************************************/ +/** +* Restarts transfer for active endpoint +* +* @param InstancePtr is a pointer to the XUsbPsu instance to be worked +* on. +* @param EpNum is an endpoint number. +* +* @return XST_SUCCESS on success or else XST_FAILURE. +* +* @note None. +* +******************************************************************************/ +static s32 XUsbPsu_RestartEp(struct XUsbPsu *InstancePtr, u8 EpNum) +{ + struct XUsbPsu_EpParams *Params; + struct XUsbPsu_Trb *TrbPtr; + struct XUsbPsu_Ep *Ept; + u32 Cmd; + s32 Ret; + + Xil_AssertNonvoid(InstancePtr != NULL); + + Params = XUsbPsu_GetEpParams(InstancePtr); + Xil_AssertNonvoid(Params != NULL); + + Ept = &InstancePtr->eps[EpNum]; + + /* check if we need to restart transfer */ + if (!Ept->ResourceIndex && Ept->PhyEpNum) + return XST_SUCCESS; + + if (Ept->UsbEpNum) { + TrbPtr = &Ept->EpTrb[Ept->TrbDequeue]; + } else { + TrbPtr = &InstancePtr->Ep0_Trb; + } + + Xil_AssertNonvoid(TrbPtr != NULL); + + TrbPtr->Ctrl |= XUSBPSU_TRB_CTRL_HWO; + + if (InstancePtr->ConfigPtr->IsCacheCoherent == 0) { + Xil_DCacheFlushRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb)); + Xil_DCacheInvalidateRange((INTPTR)Ept->BufferPtr, Ept->RequestedBytes); + } + + Params->Param0 = 0U; + Params->Param1 = (UINTPTR)TrbPtr; + + Cmd = XUSBPSU_DEPCMD_STARTTRANSFER; + + Ret = XUsbPsu_SendEpCmd(InstancePtr, Ept->UsbEpNum, Ept->Direction, + Cmd, Params); + if (Ret) + return XST_FAILURE; + + Ept->EpStatus |= XUSBPSU_EP_BUSY; + Ept->ResourceIndex = (u8)XUsbPsu_EpGetTransferIndex(InstancePtr, + Ept->UsbEpNum, Ept->Direction); + + return XST_SUCCESS; +} + +/*****************************************************************************/ +/** +* Restarts EP0 endpoint +* +* @param InstancePtr is a pointer to the XUsbPsu instance to be worked +* on. +* +* @return XST_SUCCESS on success or else XST_FAILURE. +* +* @note None. +* +******************************************************************************/ +static s32 XUsbPsu_RestoreEp0(struct XUsbPsu *InstancePtr) +{ + struct XUsbPsu_Ep *Ept; + s32 Ret; + u8 EpNum; + + for (EpNum = 0; EpNum < 2; EpNum++) { + Ept = &InstancePtr->eps[EpNum]; + + if (!Ept) + continue; + + if (!(Ept->EpStatus & XUSBPSU_EP_ENABLED)) + continue; + + Ret = XUsbPsu_EpEnable(InstancePtr, Ept->UsbEpNum, + Ept->Direction, Ept->MaxSize, Ept->Type, TRUE); + if (Ret) { + xil_printf("Failed to enable EP %d on wakeup: %d\r\n", + EpNum, Ret); + return XST_FAILURE; + } + + if (Ept->EpStatus & XUSBPSU_EP_STALL) { + XUsbPsu_Ep0StallRestart(InstancePtr); + } else { + Ret = XUsbPsu_RestartEp(InstancePtr, Ept->PhyEpNum); + if (Ret) { + xil_printf("Failed to restart EP %d on wakeup: %d\r\n", + EpNum, Ret); + return XST_FAILURE; + } + } + } + + return XST_SUCCESS; +} + +/*****************************************************************************/ +/** +* Restarts non EP0 endpoints +* +* @param InstancePtr is a pointer to the XUsbPsu instance to be worked +* on. +* +* @return XST_SUCCESS on success or else XST_FAILURE. +* +* @note None. +* +******************************************************************************/ +static s32 XUsbPsu_RestoreEps(struct XUsbPsu *InstancePtr) +{ + struct XUsbPsu_Ep *Ept; + s32 Ret; + u8 EpNum; + + for (EpNum = 2; EpNum < XUSBPSU_ENDPOINTS_NUM; EpNum++) { + Ept = &InstancePtr->eps[EpNum]; + + if (!Ept) + continue; + + if (!(Ept->EpStatus & XUSBPSU_EP_ENABLED)) + continue; + + Ret = XUsbPsu_EpEnable(InstancePtr, Ept->UsbEpNum, + Ept->Direction, Ept->MaxSize, Ept->Type, TRUE); + if (Ret) { + xil_printf("Failed to enable EP %d on wakeup: %d\r\n", + EpNum, Ret); + return XST_FAILURE; + } + } + + for (EpNum = 2; EpNum < XUSBPSU_ENDPOINTS_NUM; EpNum++) { + Ept = &InstancePtr->eps[EpNum]; + + if (!Ept) + continue; + + if (!(Ept->EpStatus & XUSBPSU_EP_ENABLED)) + continue; + + if (Ept->EpStatus & XUSBPSU_EP_STALL) { + XUsbPsu_EpSetStall(InstancePtr, Ept->UsbEpNum, Ept->Direction); + } else { + Ret = XUsbPsu_RestartEp(InstancePtr, Ept->PhyEpNum); + if (Ret) { + xil_printf("Failed to restart EP %d on wakeup: %d\r\n", + EpNum, Ret); + return XST_FAILURE; + } + } + } + + return XST_SUCCESS; +} + +/*****************************************************************************/ +/** +* Handle wakeup event +* +* @param InstancePtr is a pointer to the XUsbPsu instance to be worked +* on. +* +* @return none +* +* @note None. +* +******************************************************************************/ +void XUsbPsu_WakeupIntr(struct XUsbPsu *InstancePtr) +{ + u32 RegVal, link_state; + s32 retries; + char enter_hiber; + + RegVal = XUsbPsu_ReadLpdReg(RST_LPD_TOP); + if (InstancePtr->ConfigPtr->DeviceId == XPAR_XUSBPSU_0_DEVICE_ID) + XUsbPsu_WriteLpdReg(RST_LPD_TOP, RegVal & ~USB0_CORE_RST); + + /* change power state to D0 */ + XUsbPsu_WriteVendorReg(XIL_REQ_PWR_STATE, XIL_REQ_PWR_STATE_D0); + + /* wait till current state is changed to D0 */ + retries = XUSBPSU_PWR_STATE_RETRIES; + do { + RegVal = XUsbPsu_ReadVendorReg(XIL_CUR_PWR_STATE); + if ((RegVal & XIL_CUR_PWR_STATE_BITMASK) == XIL_CUR_PWR_STATE_D0) + break; + + XUsbSleep(XUSBPSU_TIMEOUT); + } while (--retries); + + if (retries < 0) { + xil_printf("Failed to change power state to D0\r\n"); + return; + } + + /* ask core to restore non-sticky registers */ + XUsbPsu_SetupScratchpad(InstancePtr); + + RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL); + RegVal |= XUSBPSU_DCTL_CRS; + XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal); + + /* wait till non-sticky registers are restored */ + if (XUsbPsu_Wait_Clear_Timeout(InstancePtr, XUSBPSU_DSTS, + XUSBPSU_DSTS_RSS, XUSBPSU_NON_STICKY_SAVE_RETRIES) == XST_FAILURE) { + xil_printf("Failed to restore USB core\r\n"); + return; + } + + restore_regs(InstancePtr); + + /* setup event buffers */ + XUsbPsu_EventBuffersSetup(InstancePtr); + + /* nothing to do when in OTG host mode */ + if (XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GSTS) & XUSBPSU_GSTS_CUR_MODE) + return; + + if (XUsbPsu_RestoreEp0(InstancePtr)) { + xil_printf("Failed to restore EP0\r\n"); + return; + } + + /* start controller */ + if (XUsbPsu_Start(InstancePtr)) { + xil_printf("Failed to start core on wakeup\r\n"); + return; + } + + /* Wait until device controller is ready */ + if (XUsbPsu_Wait_Clear_Timeout(InstancePtr, XUSBPSU_DSTS, + XUSBPSU_DSTS_DCNRD, XUSBPSU_CTRL_RDY_RETRIES) == XST_FAILURE) { + xil_printf("Failed to ready device controller\r\n"); + return; + } + + /* + * there can be suprious wakeup events , so wait for some time and check + * the link state + */ + XUsbSleep(XUSBPSU_TIMEOUT * 10); + + link_state = XUsbPsu_GetLinkState(InstancePtr); + + switch(link_state) { + case XUSBPSU_LINK_STATE_RESET: + RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DSTS); + RegVal &= ~XUSBPSU_DCFG_DEVADDR_MASK; + XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DSTS, RegVal); + + if (XUsbPsu_SetLinkState(InstancePtr, XUSBPSU_LINK_STATE_RECOV)) { + xil_printf("Failed to put link in Recovery\r\n"); + return; + } + break; + case XUSBPSU_LINK_STATE_SS_DIS: + RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL); + RegVal &= ~XUSBPSU_DCTL_KEEP_CONNECT; + XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal); + + /* fall Through */ + case XUSBPSU_LINK_STATE_U3: + /* enter hibernation again */ + enter_hiber = 1; + break; + default: + if (XUsbPsu_SetLinkState(InstancePtr, XUSBPSU_LINK_STATE_RECOV)) { + xil_printf("Failed to put link in Recovery\r\n"); + return; + } + break; + }; + + if (XUsbPsu_RestoreEps(InstancePtr)) { + xil_printf("Failed to restore EPs\r\n"); + return; + } + + InstancePtr->IsHibernated = 0; + + if (enter_hiber) { + Xusbpsu_HibernationIntr(InstancePtr); + return; + } + + xil_printf("We are back from hibernation!\r\n"); +} +/** @} */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_1/src/xusbpsu_hw.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_4/src/xusbpsu_hw.h similarity index 83% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_1/src/xusbpsu_hw.h rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_4/src/xusbpsu_hw.h index db612b00f..344f919f3 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_1/src/xusbpsu_hw.h +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_4/src/xusbpsu_hw.h @@ -33,7 +33,7 @@ /** * * @file xusbpsu_hw.h -* @addtogroup usbpsu_v1_0 +* @addtogroup usbpsu_v1_3 * @{ * * 
@@ -43,6 +43,7 @@
 * Ver   Who    Date     Changes
 * ----- -----  -------- -----------------------------------------------------
 * 1.0   sg    06/06/16 First release
+* 1.4   myk   12/01/18 Added support of hibernation
 *
 *
* @@ -174,6 +175,7 @@ extern "C" { /* Global Status Register Device Interrupt Mask */ #define XUSBPSU_GSTS_DEVICE_IP_MASK 0x00000040 +#define XUSBPSU_GSTS_CUR_MODE (0x00000001U << 0) /* Global USB2 PHY Configuration Register */ #define XUSBPSU_GUSB2PHYCFG_PHYSOFTRST (0x00000001U << 31) @@ -308,8 +310,28 @@ extern "C" { #define XUSBPSU_PORTMSC_30_U1_TIMEOUT_MASK (0xffU << 0) #define XUSBPSU_PORTMSC_30_U1_TIMEOUT_SHIFT (0U) +/* Register for LPD block */ +#define RST_LPD_TOP 0x23C +#define USB0_CORE_RST (1 << 6) +#define USB1_CORE_RST (1 << 7) -/*@}*/ +/* Vendor registers for Xilinx */ +#define XIL_CUR_PWR_STATE 0x00 +#define XIL_PME_ENABLE 0x34 +#define XIL_REQ_PWR_STATE 0x3c +#define XIL_PWR_CONFIG_USB3 0x48 + +#define XIL_REQ_PWR_STATE_D0 0 +#define XIL_REQ_PWR_STATE_D3 3 +#define XIL_PME_ENABLE_SIG_GEN 1 +#define XIL_CUR_PWR_STATE_D0 0 +#define XIL_CUR_PWR_STATE_D3 3 +#define XIL_CUR_PWR_STATE_BITMASK 0x03 + +#define VENDOR_BASE_ADDRESS 0xFF9D0000 +#define LPD_BASE_ADDRESS 0xFF5E0000 + + /*@}*/ /**************************** Type Definitions *******************************/ @@ -353,6 +375,76 @@ extern "C" { #define XUsbPsu_WriteReg(InstancePtr, Offset, Data) \ Xil_Out32((InstancePtr)->ConfigPtr->BaseAddress + (u32)(Offset), (u32)(Data)) +/*****************************************************************************/ +/** +* +* Read a vendor register of the USBPS8 device. +* +* @param Offset is the offset of the register to read. +* +* @return The contents of the register. +* +* @note C-style Signature: +* u32 XUsbPsu_ReadVendorReg(struct XUsbPsu *InstancePtr, u32 Offset); +* +******************************************************************************/ +#define XUsbPsu_ReadVendorReg(Offset) \ + Xil_In32(VENDOR_BASE_ADDRESS + (u32)(Offset)) + +/*****************************************************************************/ +/** +* +* Write a Vendor register of the USBPS8 device. +* +* @param RegOffset is the offset of the register to write. +* @param Data is the value to write to the register. +* +* @return None. +* +* @note C-style Signature: +* void XUsbPsu_WriteVendorReg(struct XUsbPsu *InstancePtr, +* u32 Offset,u32 Data) +* +******************************************************************************/ +#define XUsbPsu_WriteVendorReg(Offset, Data) \ + Xil_Out32(VENDOR_BASE_ADDRESS + (u32)(Offset), (u32)(Data)) + +/*****************************************************************************/ +/** +* +* Read a LPD register of the USBPS8 device. +* +* @param InstancePtr is a pointer to the XUsbPsu instance. +* @param Offset is the offset of the register to read. +* +* @return The contents of the register. +* +* @note C-style Signature: +* u32 XUsbPsu_ReadLpdReg(struct XUsbPsu *InstancePtr, u32 Offset); +* +******************************************************************************/ +#define XUsbPsu_ReadLpdReg(Offset) \ + Xil_In32(LPD_BASE_ADDRESS + (u32)(Offset)) + +/*****************************************************************************/ +/** +* +* Write a LPD register of the USBPS8 device. +* +* @param InstancePtr is a pointer to the XUsbPsu instance. +* @param RegOffset is the offset of the register to write. +* @param Data is the value to write to the register. +* +* @return None. +* +* @note C-style Signature: +* void XUsbPsu_WriteLpdReg(struct XUsbPsu *InstancePtr, +* u32 Offset,u32 Data) +* +******************************************************************************/ +#define XUsbPsu_WriteLpdReg(Offset, Data) \ + Xil_Out32(LPD_BASE_ADDRESS + (u32)(Offset), (u32)(Data)) + /************************** Function Prototypes ******************************/ #ifdef __cplusplus diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_intr.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_4/src/xusbpsu_intr.c similarity index 70% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_intr.c rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_4/src/xusbpsu_intr.c index 85baab0f8..6124783fc 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_intr.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_4/src/xusbpsu_intr.c @@ -33,7 +33,7 @@ /** * * @file xusbpsu_intr.c -* @addtogroup usbpsu_v1_0 +* @addtogroup usbpsu_v1_3 * @{ * * @@ -43,6 +43,13 @@ * Ver Who Date Changes * ----- ---- -------- ------------------------------------------------------- * 1.0 sg 06/06/16 First release +* 1.3 vak 04/03/17 Added CCI support for USB +* 1.4 bk 12/01/18 Modify USBPSU driver code to fit USB common example code +* for all USB IPs +* myk 12/01/18 Added hibernation support +* vak 22/01/18 Added changes for supporting microblaze platform +* vak 13/03/18 Moved the setup interrupt system calls from driver to +* example. * * * @@ -50,7 +57,7 @@ /***************************** Include Files ********************************/ -#include "xusbpsu.h" +#include "xusb_wrapper.h" /************************** Constant Definitions *****************************/ @@ -95,10 +102,12 @@ void XUsbPsu_EpInterrupt(struct XUsbPsu *InstancePtr, /* Handle other end point events */ switch (Event->Endpoint_Event) { case XUSBPSU_DEPEVT_XFERCOMPLETE: + case XUSBPSU_DEPEVT_XFERINPROGRESS: XUsbPsu_EpXferComplete(InstancePtr, Event); break; case XUSBPSU_DEPEVT_XFERNOTREADY: + XUsbPsu_EpXferNotReady(InstancePtr, Event); break; default: @@ -130,7 +139,87 @@ void XUsbPsu_DisconnectIntr(struct XUsbPsu *InstancePtr) XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal); InstancePtr->IsConfigDone = 0U; - InstancePtr->Speed = XUSBPSU_SPEED_UNKNOWN; + InstancePtr->AppData->Speed = XUSBPSU_SPEED_UNKNOWN; + +#ifdef XUSBPSU_HIBERNATION_ENABLE + /* In USB 2.0, to avoid hibernation interrupt at the time of connection + * clear KEEP_CONNECT bit. + */ + if (InstancePtr->HasHibernation) { + RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL); + if (RegVal & XUSBPSU_DCTL_KEEP_CONNECT) { + RegVal &= ~XUSBPSU_DCTL_KEEP_CONNECT; + XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal); + } + } +#endif + + /* Call the handler if necessary */ + if (InstancePtr->DisconnectIntrHandler != NULL) { + InstancePtr->DisconnectIntrHandler(InstancePtr->AppData); + } +} + +/****************************************************************************/ +/** +* Stops any active transfer. +* +* @param InstancePtr is a pointer to the XUsbPsu instance. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +static void XUsbPsu_stop_active_transfers(struct XUsbPsu *InstancePtr) +{ + u32 Epnum; + + for (Epnum = 2; Epnum < XUSBPSU_ENDPOINTS_NUM; Epnum++) { + struct XUsbPsu_Ep *Ept; + + Ept = &InstancePtr->eps[Epnum]; + if (!Ept) + continue; + + if (!(Ept->EpStatus & XUSBPSU_EP_ENABLED)) + continue; + + XUsbPsu_StopTransfer(InstancePtr, Ept->UsbEpNum, + Ept->Direction, TRUE); + } +} + +/****************************************************************************/ +/** +* Clears stall on all stalled Eps. +* +* @param InstancePtr is a pointer to the XUsbPsu instance. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +static void XUsbPsu_clear_stall_all_ep(struct XUsbPsu *InstancePtr) +{ + u32 Epnum; + + for (Epnum = 1; Epnum < XUSBPSU_ENDPOINTS_NUM; Epnum++) { + struct XUsbPsu_Ep *Ept; + + Ept = &InstancePtr->eps[Epnum]; + if (!Ept) + continue; + + if (!(Ept->EpStatus & XUSBPSU_EP_ENABLED)) + continue; + + if (!(Ept->EpStatus & XUSBPSU_EP_STALL)) + continue; + + XUsbPsu_EpClearStall(InstancePtr, Ept->UsbEpNum, Ept->Direction); + } } /****************************************************************************/ @@ -149,13 +238,16 @@ void XUsbPsu_ResetIntr(struct XUsbPsu *InstancePtr) u32 RegVal; u32 Index; - InstancePtr->State = XUSBPSU_STATE_DEFAULT; + InstancePtr->AppData->State = XUSBPSU_STATE_DEFAULT; RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL); RegVal &= ~XUSBPSU_DCTL_TSTCTRL_MASK; XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal); InstancePtr->TestMode = 0U; + XUsbPsu_stop_active_transfers(InstancePtr); + XUsbPsu_clear_stall_all_ep(InstancePtr); + for (Index = 0U; Index < (InstancePtr->NumInEps + InstancePtr->NumOutEps); Index++) { @@ -168,6 +260,11 @@ void XUsbPsu_ResetIntr(struct XUsbPsu *InstancePtr) RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCFG); RegVal &= ~(XUSBPSU_DCFG_DEVADDR_MASK); XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCFG, RegVal); + + /* Call the handler if necessary */ + if (InstancePtr->ResetIntrHandler != NULL) { + InstancePtr->ResetIntrHandler(InstancePtr->AppData); + } } /****************************************************************************/ @@ -189,7 +286,7 @@ void XUsbPsu_ConnDoneIntr(struct XUsbPsu *InstancePtr) RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DSTS); Speed = (u8)(RegVal & XUSBPSU_DSTS_CONNECTSPD); - InstancePtr->Speed = Speed; + InstancePtr->AppData->Speed = Speed; switch (Speed) { case XUSBPSU_DCFG_SUPERSPEED: @@ -197,7 +294,7 @@ void XUsbPsu_ConnDoneIntr(struct XUsbPsu *InstancePtr) xil_printf("Super Speed\r\n"); #endif Size = 512U; - InstancePtr->Speed = XUSBPSU_SPEED_SUPER; + InstancePtr->AppData->Speed = XUSBPSU_SPEED_SUPER; break; case XUSBPSU_DCFG_HIGHSPEED: @@ -205,7 +302,7 @@ void XUsbPsu_ConnDoneIntr(struct XUsbPsu *InstancePtr) xil_printf("High Speed\r\n"); #endif Size = 64U; - InstancePtr->Speed = XUSBPSU_SPEED_HIGH; + InstancePtr->AppData->Speed = XUSBPSU_SPEED_HIGH; break; case XUSBPSU_DCFG_FULLSPEED2: @@ -214,7 +311,7 @@ void XUsbPsu_ConnDoneIntr(struct XUsbPsu *InstancePtr) xil_printf("Full Speed\r\n"); #endif Size = 64U; - InstancePtr->Speed = XUSBPSU_SPEED_FULL; + InstancePtr->AppData->Speed = XUSBPSU_SPEED_FULL; break; case XUSBPSU_DCFG_LOWSPEED: @@ -222,15 +319,34 @@ void XUsbPsu_ConnDoneIntr(struct XUsbPsu *InstancePtr) xil_printf("Low Speed\r\n"); #endif Size = 64U; - InstancePtr->Speed = XUSBPSU_SPEED_LOW; + InstancePtr->AppData->Speed = XUSBPSU_SPEED_LOW; break; default : Size = 64U; break; } + if (InstancePtr->AppData->Speed == XUSBPSU_SPEED_SUPER) { + RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL); + RegVal &= ~XUSBPSU_DCTL_HIRD_THRES_MASK; + XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal); + } + (void)XUsbPsu_EnableControlEp(InstancePtr, Size); (void)XUsbPsu_RecvSetup(InstancePtr); + +#ifdef XUSBPSU_HIBERNATION_ENABLE + /* In USB 2.0, to avoid hibernation interrupt at the time of connection + * clear KEEP_CONNECT bit. + */ + if (InstancePtr->HasHibernation) { + RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL); + if (!(RegVal & XUSBPSU_DCTL_KEEP_CONNECT)) { + RegVal |= XUSBPSU_DCTL_KEEP_CONNECT; + XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal); + } + } +#endif } /****************************************************************************/ @@ -284,6 +400,10 @@ void XUsbPsu_DevInterrupt(struct XUsbPsu *InstancePtr, break; case XUSBPSU_DEVICE_EVENT_HIBER_REQ: +#ifdef XUSBPSU_HIBERNATION_ENABLE + if (InstancePtr->HasHibernation) + Xusbpsu_HibernationIntr(InstancePtr); +#endif break; case XUSBPSU_DEVICE_EVENT_LINK_STATUS_CHANGE: @@ -362,26 +482,39 @@ void XUsbPsu_EventBufferHandler(struct XUsbPsu *InstancePtr) { struct XUsbPsu_EvtBuffer *Evt; union XUsbPsu_Event Event = {0}; + u32 RegVal; Evt = &InstancePtr->Evt; - Xil_DCacheInvalidateRange((INTPTR)Evt->BuffAddr, + if (InstancePtr->ConfigPtr->IsCacheCoherent == 0) { + Xil_DCacheInvalidateRange((INTPTR)Evt->BuffAddr, (u32)XUSBPSU_EVENT_BUFFERS_SIZE); + } while (Evt->Count > 0) { - Event.Raw = *(UINTPTR *)(Evt->BuffAddr + Evt->Offset); + Event.Raw = *(UINTPTR *)((UINTPTR)Evt->BuffAddr + Evt->Offset); /* - * Process the event received - */ - XUsbPsu_EventHandler(InstancePtr, &Event); + * Process the event received + */ + XUsbPsu_EventHandler(InstancePtr, &Event); + + /* don't process anymore events if core is hibernated */ + if (InstancePtr->IsHibernated) + return; Evt->Offset = (Evt->Offset + 4U) % XUSBPSU_EVENT_BUFFERS_SIZE; Evt->Count -= 4; XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTCOUNT(0), 4U); } + Evt->Count = 0; Evt->Flags &= ~XUSBPSU_EVENT_PENDING; + + /* Unmask event interrupt */ + RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GEVNTSIZ(0)); + RegVal &= ~XUSBPSU_GEVNTSIZ_INTMASK; + XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTSIZ(0), RegVal); } /****************************************************************************/ @@ -424,11 +557,24 @@ void XUsbPsu_IntrHandler(void *XUsbPsuInstancePtr) /* Processes events in an Event Buffer */ XUsbPsu_EventBufferHandler(InstancePtr); - - /* Unmask event interrupt */ - RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GEVNTSIZ(0)); - RegVal &= ~XUSBPSU_GEVNTSIZ_INTMASK; - XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTSIZ(0), RegVal); } +#ifdef XUSBPSU_HIBERNATION_ENABLE +/****************************************************************************/ +/** +* Wakeup Interrupt Handler. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void XUsbPsu_WakeUpIntrHandler(void *XUsbPsuInstancePtr) +{ + struct XUsbPsu *InstancePtr = (struct XUsbPsu *)XUsbPsuInstancePtr; + + XUsbPsu_WakeupIntr(InstancePtr); +} +#endif + /** @} */ diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_sinit.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_4/src/xusbpsu_sinit.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_sinit.c rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_4/src/xusbpsu_sinit.c index c172c5d69..bee46bc4c 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_sinit.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_4/src/xusbpsu_sinit.c @@ -33,7 +33,7 @@ /** * * @file xusbpsu_sinit.h -* @addtogroup usbpsu_v1_0 +* @addtogroup usbpsu_v1_3 * @{ * * diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/video_common_v4_3/src/Makefile b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/video_common_v4_3/src/Makefile new file mode 100644 index 000000000..9cb03a481 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/video_common_v4_3/src/Makefile @@ -0,0 +1,40 @@ +COMPILER= +ARCHIVER= +CP=cp +COMPILER_FLAGS=-ffunction-sections -fdata-sections +EXTRA_COMPILER_FLAGS=-Wall -Wextra +LIB=libxil.a + +CC_FLAGS = $(COMPILER_FLAGS) +ECC_FLAGS = $(EXTRA_COMPILER_FLAGS) + +RELEASEDIR=../../../lib +INCLUDEDIR=../../../include +INCLUDES=-I./. -I${INCLUDEDIR} + +OUTS = *.o + +LIBSOURCES:=*.c +INCLUDEFILES:=*.h + +OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c))) + +libs: banner video_common_libs clean + +%.o: %.c + ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $< + +banner: + echo "Compiling video_common" + +video_common_libs: ${OBJECTS} + $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS} + +.PHONY: include +include: video_common_includes + +video_common_includes: + ${CP} ${INCLUDEFILES} ${INCLUDEDIR} + +clean: + rm -rf ${OBJECTS} diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/video_common_v4_3/src/xvidc.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/video_common_v4_3/src/xvidc.c new file mode 100644 index 000000000..ba4f789b0 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/video_common_v4_3/src/xvidc.c @@ -0,0 +1,1204 @@ +/******************************************************************************* + * + * Copyright (C) 2017 Xilinx, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * Use of the Software is limited solely to applications: + * (a) running on a Xilinx device, or + * (b) that interact with a Xilinx device through a bus or interconnect. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of the Xilinx shall not be used + * in advertising or otherwise to promote the sale, use or other dealings in + * this Software without prior written authorization from Xilinx. + * +*******************************************************************************/ +/******************************************************************************/ +/** + * + * @file xvidc.c + * @addtogroup video_common_v4_3 + * @{ + * + * Contains common utility functions that are typically used by video-related + * drivers and applications. + * + * @note None. + * + * 
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -----------------------------------------------
+ * 1.0   rc,  01/10/15 Initial release.
+ *       als
+ * 2.2   als  02/01/16 Functions with pointer arguments that don't modify
+ *                     contents now const.
+ *                     Added ability to insert a custom video timing table.
+ *       yh            Added 3D support.
+ * 3.0   aad  05/13/16 Added API to search for RB video modes.
+ * 3.1   rco  07/26/16 Added extern definition for timing table array
+ *                     Added video-in-memory color formats
+ *                     Updated XVidC_RegisterCustomTimingModes API signature
+ * 4.1   rco  11/23/16 Added new memory formats
+ *                     Added new API to get video mode id that matches exactly
+ *                     with provided timing information
+ *                     Fix c++ warnings
+ * 4.2	 jsr  07/22/17 Added new framerates and color formats to support SDI
+ *                     Reordered YCBCR422 colorforamt and removed other formats
+ *                     that are not needed for SDI which were added earlier.
+ *       vyc  10/04/17 Added new streaming alpha formats and new memory formats
+ * 4.3   eb   26/01/18 Added API XVidC_GetVideoModeIdExtensive
+ *       jsr  02/22/18 Added XVIDC_CSF_YCBCR_420 color space format
+ *       vyc  04/04/18 Added BGR8 memory format
+ *
+ * +*******************************************************************************/ + +/******************************* Include Files ********************************/ + +#include "xil_assert.h" +#include "xstatus.h" +#include "xvidc.h" + +/*************************** Variable Declarations ****************************/ +extern const XVidC_VideoTimingMode XVidC_VideoTimingModes[XVIDC_VM_NUM_SUPPORTED]; + +const XVidC_VideoTimingMode *XVidC_CustomTimingModes = NULL; +int XVidC_NumCustomModes = 0; + +/**************************** Function Prototypes *****************************/ + +static const XVidC_VideoTimingMode *XVidC_GetCustomVideoModeData( + XVidC_VideoMode VmId); +static u8 XVidC_IsVtmRb(const char *VideoModeStr, u8 RbN); + +/*************************** Function Definitions *****************************/ + +/******************************************************************************/ +/** + * This function registers a user-defined custom video mode timing table with + * video_common. Functions which search the available video modes, or take VmId + * as an input, will operate on or check the custom video mode timing table in + * addition to the pre-defined video mode timing table (XVidC_VideoTimingModes). + * + * @param CustomTable is a pointer to the user-defined custom vide mode + * timing table to register. + * @param NumElems is the number of video modes supported by CustomTable. + * + * @return + * - XST_SUCCESS if the custom table was successfully registered. + * - XST_FAILURE if an existing custom table is already present. + * + * @note IDs in the custom table may not conflict with IDs reserved by + * the XVidC_VideoMode enum. + * +*******************************************************************************/ +u32 XVidC_RegisterCustomTimingModes(const XVidC_VideoTimingMode *CustomTable, + u16 NumElems) +{ + u16 Index; + + /* Verify arguments. */ + Xil_AssertNonvoid(CustomTable != NULL); + for (Index = 0; Index < NumElems; Index++) { + Xil_AssertNonvoid((CustomTable[Index].VmId > XVIDC_VM_CUSTOM)); + /* The IDs of each video mode in the custom table must not + * conflict with IDs reserved by video_common. */ + } + + /* Fail if a custom table is currently already registered. */ + if (XVidC_CustomTimingModes) { + return XST_FAILURE; + } + + XVidC_CustomTimingModes = CustomTable; + XVidC_NumCustomModes = NumElems; + + return XST_SUCCESS; +} + +/******************************************************************************/ +/** + * This function unregisters the user-defined custom video mode timing table + * previously registered by XVidC_RegisterCustomTimingModes(). + * + * @return None. + * + * @note None. + * +*******************************************************************************/ +void XVidC_UnregisterCustomTimingModes(void) +{ + XVidC_CustomTimingModes = NULL; + XVidC_NumCustomModes = 0; +} + +/******************************************************************************/ +/** + * This function calculates pixel clock based on the inputs. + * + * @param HTotal specifies horizontal total. + * @param VTotal specifies vertical total. + * @param FrameRate specifies rate at which frames are generated. + * + * @return Pixel clock in Hz. + * + * @note None. + * +*******************************************************************************/ +u32 XVidC_GetPixelClockHzByHVFr(u32 HTotal, u32 VTotal, u8 FrameRate) +{ + return (HTotal * VTotal * FrameRate); +} + +/******************************************************************************/ +/** + * This function calculates pixel clock from video mode. + * + * @param VmId specifies the resolution id. + * + * @return Pixel clock in Hz. + * + * @note None. + * +*******************************************************************************/ +u32 XVidC_GetPixelClockHzByVmId(XVidC_VideoMode VmId) +{ + u32 ClkHz; + const XVidC_VideoTimingMode *VmPtr; + + VmPtr = XVidC_GetVideoModeData(VmId); + if (!VmPtr) { + return 0; + } + + if (XVidC_IsInterlaced(VmId)) { + /* For interlaced mode, use both frame 0 and frame 1 vertical + * totals. */ + ClkHz = VmPtr->Timing.F0PVTotal + VmPtr->Timing.F1VTotal; + + /* Multiply the number of pixels by the frame rate of each + * individual frame (half of the total frame rate). */ + ClkHz *= VmPtr->FrameRate / 2; + } + else { + /* For progressive mode, use only frame 0 vertical total. */ + ClkHz = VmPtr->Timing.F0PVTotal; + + /* Multiply the number of pixels by the frame rate. */ + ClkHz *= VmPtr->FrameRate; + } + + /* Multiply the vertical total by the horizontal total for number of + * pixels. */ + ClkHz *= VmPtr->Timing.HTotal; + + return ClkHz; +} + +/******************************************************************************/ +/** + * This function checks if the input video mode is interlaced/progressive based + * on its ID from the video timings table. + * + * @param VmId specifies the resolution ID from the video timings table. + * + * @return Video format. + * - XVIDC_VF_PROGRESSIVE + * - XVIDC_VF_INTERLACED + * + * @note None. + * +*******************************************************************************/ +XVidC_VideoFormat XVidC_GetVideoFormat(XVidC_VideoMode VmId) +{ + const XVidC_VideoTimingMode *VmPtr; + + VmPtr = XVidC_GetVideoModeData(VmId); + if (!VmPtr) { + return XVIDC_VF_UNKNOWN; + } + + if (VmPtr->Timing.F1VTotal == 0) { + return (XVIDC_VF_PROGRESSIVE); + } + + return (XVIDC_VF_INTERLACED); +} + +/******************************************************************************/ +/** + * This function checks if the input video mode is interlaced based on its ID + * from the video timings table. + * + * @param VmId specifies the resolution ID from the video timings table. + * + * @return + * - 1 if the video timing with the supplied table ID is + * interlaced. + * - 0 if the video timing is progressive. + * + * @note None. + * +*******************************************************************************/ +u8 XVidC_IsInterlaced(XVidC_VideoMode VmId) +{ + if (XVidC_GetVideoFormat(VmId) == XVIDC_VF_INTERLACED) { + return 1; + } + + return 0; +} + +/******************************************************************************/ +/** + * This function returns the Video Mode ID that matches the detected input + * timing, frame rate and I/P flag + * + * @param Timing is the pointer to timing parameters to match + * @param FrameRate specifies refresh rate in HZ + * @param IsInterlaced is flag. + * - 0 = Progressive + * - 1 = Interlaced. + * + * @return Id of a supported video mode. + * + * @note This is an extension of XVidC_GetVideoModeId API to include + * blanking information in match process. No attempt is made to + * search for reduced blanking entries, if any. + * +*******************************************************************************/ +XVidC_VideoMode XVidC_GetVideoModeIdWBlanking(const XVidC_VideoTiming *Timing, + u32 FrameRate, u8 IsInterlaced) +{ + XVidC_VideoMode VmId; + XVidC_VideoTiming const *StdTiming = NULL; + + /* First search for ID with matching Width & Height */ + VmId = XVidC_GetVideoModeId(Timing->HActive, Timing->VActive, FrameRate, + IsInterlaced); + + if(VmId == XVIDC_VM_NOT_SUPPORTED) { + return(VmId); + } else { + + /* Get standard timing info from default timing table */ + StdTiming = XVidC_GetTimingInfo(VmId); + + /* Match against detected timing parameters */ + if((Timing->HActive == StdTiming->HActive) && + (Timing->VActive == StdTiming->VActive) && + (Timing->HTotal == StdTiming->HTotal) && + (Timing->F0PVTotal == StdTiming->F0PVTotal) && + (Timing->HFrontPorch == StdTiming->HFrontPorch) && + (Timing->HSyncWidth == StdTiming->HSyncWidth) && + (Timing->HBackPorch == StdTiming->HBackPorch) && + (Timing->F0PVFrontPorch == StdTiming->F0PVFrontPorch) && + (Timing->F0PVSyncWidth == StdTiming->F0PVSyncWidth) && + (Timing->F0PVBackPorch == StdTiming->F0PVBackPorch)) { + return(VmId); + } else { + return(XVIDC_VM_NOT_SUPPORTED); + } + } +} + +/******************************************************************************/ +/** + * This function returns the Video Mode ID that matches the detected input + * width, height, frame rate and I/P flag + * + * @param Width specifies the number pixels per scanline. + * @param Height specifies the number of scanline's. + * @param FrameRate specifies refresh rate in HZ + * @param IsInterlaced is flag. + * - 0 = Progressive + * - 1 = Interlaced. + * + * @return Id of a supported video mode. + * + * @note None. + * +*******************************************************************************/ +XVidC_VideoMode XVidC_GetVideoModeId(u32 Width, u32 Height, u32 FrameRate, + u8 IsInterlaced) +{ + u32 Low; + u32 High; + u32 Mid; + u32 HActive; + u32 VActive; + u32 Rate; + u32 ResFound = (FALSE); + XVidC_VideoMode Mode; + u16 Index; + + /* First, attempt a linear search on the custom video timing table. */ + if(XVidC_CustomTimingModes) { + for (Index = 0; Index < XVidC_NumCustomModes; Index++) { + HActive = XVidC_CustomTimingModes[Index].Timing.HActive; + VActive = XVidC_CustomTimingModes[Index].Timing.VActive; + Rate = XVidC_CustomTimingModes[Index].FrameRate; + if ((Width == HActive) && + (Height == VActive) && + (FrameRate == Rate)) { + return XVidC_CustomTimingModes[Index].VmId; + } + } + } + + if (IsInterlaced) { + Low = (XVIDC_VM_INTL_START); + High = (XVIDC_VM_INTL_END); + } + else { + Low = (XVIDC_VM_PROG_START); + High = (XVIDC_VM_PROG_END); + } + + HActive = VActive = Rate = 0; + + /* Binary search finds item in sorted array. + * And returns index (zero based) of item + * If item is not found returns flag remains + * FALSE. Search key is "width or HActive" + */ + while (Low <= High) { + Mid = (Low + High) / 2; + HActive = XVidC_VideoTimingModes[Mid].Timing.HActive; + if (Width == HActive) { + ResFound = (TRUE); + break; + } + else if (Width < HActive) { + if (Mid == 0) { + break; + } + else { + High = Mid - 1; + } + } + else { + Low = Mid + 1; + } + } + + /* HActive matched at middle */ + if (ResFound) { + /* Rewind to start index of mode with matching width */ + while ((Mid > 0) && + (XVidC_VideoTimingModes[Mid - 1].Timing.HActive == + Width)) { + --Mid; + } + + ResFound = (FALSE); + VActive = XVidC_VideoTimingModes[Mid].Timing.VActive; + Rate = XVidC_VideoTimingModes[Mid].FrameRate; + + /* Now do a linear search for matching VActive and Frame + * Rate + */ + while (HActive == Width) { + /* check current entry */ + if ((VActive == Height) && (Rate == FrameRate)) { + ResFound = (TRUE); + break; + } + /* Check next entry */ + else { + Mid = Mid + 1; + HActive = + XVidC_VideoTimingModes[Mid].Timing.HActive; + VActive = + XVidC_VideoTimingModes[Mid].Timing.VActive; + Rate = XVidC_VideoTimingModes[Mid].FrameRate; + } + } + Mode = + (ResFound) ? (XVidC_VideoMode)Mid : (XVIDC_VM_NOT_SUPPORTED); + } + else { + Mode = (XVIDC_VM_NOT_SUPPORTED); + } + + return (Mode); +} + +/******************************************************************************/ +/** + * This function returns the Video Mode ID that matches the detected input + * timing, frame rate and I/P flag + * + * @param Timing is the pointer to timing parameters to match + * @param FrameRate specifies refresh rate in HZ + * @param IsInterlaced is flag. + * - 0 = Progressive + * - 1 = Interlaced. + * @param IsExtensive is flag. + * - 0 = Basic matching of timing parameters + * - 1 = Extensive matching of timing parameters + * + * @return Id of a supported video mode. + * + * @note This function attempts to search for reduced blanking entries, if + * any. + * +*******************************************************************************/ +XVidC_VideoMode XVidC_GetVideoModeIdExtensive(XVidC_VideoTiming *Timing, + u32 FrameRate, + u8 IsInterlaced, + u8 IsExtensive) +{ + u32 Low; + u32 High; + u32 Mid; + u32 HActive; + u32 VActive; + u32 Rate; + u32 ResFound = (FALSE); + XVidC_VideoMode Mode; + u16 Index; + + /* First, attempt a linear search on the custom video timing table. */ + if(XVidC_CustomTimingModes) { + for (Index = 0; Index < XVidC_NumCustomModes; Index++) { + HActive = XVidC_CustomTimingModes[Index].Timing.HActive; + VActive = XVidC_CustomTimingModes[Index].Timing.VActive; + Rate = XVidC_CustomTimingModes[Index].FrameRate; + if ((HActive == Timing->HActive) && (VActive == Timing->VActive) && + (Rate == FrameRate) && (IsExtensive == 0 || ( + XVidC_CustomTimingModes[Index].Timing.HTotal == Timing->HTotal && + XVidC_CustomTimingModes[Index].Timing.F0PVTotal == + Timing->F0PVTotal && + XVidC_CustomTimingModes[Index].Timing.HFrontPorch == + Timing->HFrontPorch && + XVidC_CustomTimingModes[Index].Timing.F0PVFrontPorch == + Timing->F0PVFrontPorch && + XVidC_CustomTimingModes[Index].Timing.HSyncWidth == + Timing->HSyncWidth && + XVidC_CustomTimingModes[Index].Timing.F0PVSyncWidth == + Timing->F0PVSyncWidth && + XVidC_CustomTimingModes[Index].Timing.VSyncPolarity == + Timing->VSyncPolarity))) { + if (!IsInterlaced || IsExtensive == 0 || ( + XVidC_CustomTimingModes[Index].Timing.F1VTotal == + Timing->F1VTotal && + XVidC_CustomTimingModes[Index].Timing.F1VFrontPorch == + Timing->F1VFrontPorch && + XVidC_CustomTimingModes[Index].Timing.F1VSyncWidth == + Timing->F1VSyncWidth)) { + return XVidC_CustomTimingModes[Index].VmId; + } + } + } + } + + if (IsInterlaced) { + Low = (XVIDC_VM_INTL_START); + High = (XVIDC_VM_INTL_END); + } + else { + Low = (XVIDC_VM_PROG_START); + High = (XVIDC_VM_PROG_END); + } + + HActive = VActive = Rate = 0; + + /* Binary search finds item in sorted array. + * And returns index (zero based) of item + * If item is not found returns flag remains + * FALSE. Search key is "Timing->HActive or HActive" + */ + while (Low <= High) { + Mid = (Low + High) / 2; + HActive = XVidC_VideoTimingModes[Mid].Timing.HActive; + if (Timing->HActive == HActive) { + ResFound = (TRUE); + break; + } + else if (Timing->HActive < HActive) { + if (Mid == 0) { + break; + } + else { + High = Mid - 1; + } + } + else { + Low = Mid + 1; + } + } + + /* HActive matched at middle */ + if (ResFound) { + /* Rewind to start index of mode with matching Timing->HActive */ + while ((Mid > 0) && + (XVidC_VideoTimingModes[Mid - 1].Timing.HActive == + Timing->HActive)) { + --Mid; + } + + ResFound = (FALSE); + VActive = XVidC_VideoTimingModes[Mid].Timing.VActive; + Rate = XVidC_VideoTimingModes[Mid].FrameRate; + + /* Now do a linear search for matching VActive and Frame + * Rate + */ + while (HActive == Timing->HActive) { + /* check current entry */ + if ((VActive == Timing->VActive) && (Rate == FrameRate) && + (IsExtensive == 0 || + (XVidC_VideoTimingModes[Mid].Timing.HTotal == + Timing->HTotal && + XVidC_VideoTimingModes[Mid].Timing.F0PVTotal == + Timing->F0PVTotal && + XVidC_VideoTimingModes[Mid].Timing.HFrontPorch == + Timing->HFrontPorch && + XVidC_VideoTimingModes[Mid].Timing.F0PVFrontPorch == + Timing->F0PVFrontPorch && + XVidC_VideoTimingModes[Mid].Timing.HSyncWidth == + Timing->HSyncWidth && + XVidC_VideoTimingModes[Mid].Timing.F0PVSyncWidth == + Timing->F0PVSyncWidth && + XVidC_VideoTimingModes[Mid].Timing.VSyncPolarity == + Timing->VSyncPolarity))) { + if (!IsInterlaced || IsExtensive == 0 || ( + XVidC_VideoTimingModes[Mid].Timing.F1VTotal == + Timing->F1VTotal && + XVidC_VideoTimingModes[Mid].Timing.F1VFrontPorch == + Timing->F1VFrontPorch && + XVidC_VideoTimingModes[Mid].Timing.F1VSyncWidth == + Timing->F1VSyncWidth)) { + ResFound = (TRUE); + break; + } + } + /* Check next entry */ + else { + Mid = Mid + 1; + HActive = + XVidC_VideoTimingModes[Mid].Timing.HActive; + VActive = + XVidC_VideoTimingModes[Mid].Timing.VActive; + Rate = XVidC_VideoTimingModes[Mid].FrameRate; + } + } + Mode = + (ResFound) ? (XVidC_VideoMode)Mid : (XVIDC_VM_NOT_SUPPORTED); + } + else { + Mode = (XVIDC_VM_NOT_SUPPORTED); + } + + return (Mode); +} + +/******************************************************************************/ +/** + * This function returns the video mode ID that matches the detected input + * width, height, frame rate, interlaced or progressive, and reduced blanking. + * + * @param Width specifies the number pixels per scanline. + * @param Height specifies the number of scanline's. + * @param FrameRate specifies refresh rate in HZ + * @param IsInterlaced specifies interlaced or progressive mode: + * - 0 = Progressive + * - 1 = Interlaced. + * @param RbN specifies the type of reduced blanking: + * - 0 = No reduced blanking + * - 1 = RB + * - 2 = RB2 + * + * @return ID of a supported video mode. + * + * @note None. + * +*******************************************************************************/ +XVidC_VideoMode XVidC_GetVideoModeIdRb(u32 Width, u32 Height, + u32 FrameRate, u8 IsInterlaced, u8 RbN) +{ + XVidC_VideoMode VmId; + const XVidC_VideoTimingMode *VtmPtr; + u8 Found = 0; + + VmId = XVidC_GetVideoModeId(Width, Height, FrameRate, + IsInterlaced); + + VtmPtr = XVidC_GetVideoModeData(VmId); + if (!VtmPtr) { + return XVIDC_VM_NOT_SUPPORTED; + } + + while (!Found) { + VtmPtr = XVidC_GetVideoModeData(VmId); + if ((Height != VtmPtr->Timing.VActive) || + (Width != VtmPtr->Timing.HActive) || + (FrameRate != VtmPtr->FrameRate) || + (IsInterlaced && !XVidC_IsInterlaced(VmId))) { + VmId = XVIDC_VM_NOT_SUPPORTED; + break; + } + Found = XVidC_IsVtmRb(XVidC_GetVideoModeStr(VmId), RbN); + if (Found) { + break; + } + VmId = (XVidC_VideoMode)((int)VmId + 1); + } + + return VmId; +} + +/******************************************************************************/ +/** + * This function returns the pointer to video mode data at index provided. + * + * @param VmId specifies the resolution id. + * + * @return Pointer to XVidC_VideoTimingMode structure based on the given + * video mode. + * + * @note None. + * +*******************************************************************************/ +const XVidC_VideoTimingMode *XVidC_GetVideoModeData(XVidC_VideoMode VmId) +{ + if (VmId < XVIDC_VM_NUM_SUPPORTED) { + return &XVidC_VideoTimingModes[VmId]; + } + + return XVidC_GetCustomVideoModeData(VmId); +} + +/******************************************************************************/ +/** + * + * This function returns the resolution name for index specified. + * + * @param VmId specifies the resolution id. + * + * @return Pointer to a resolution name string. + * + * @note None. + * +*******************************************************************************/ +const char *XVidC_GetVideoModeStr(XVidC_VideoMode VmId) +{ + const XVidC_VideoTimingMode *VmPtr; + + if (VmId == XVIDC_VM_CUSTOM) { + return ("Custom video mode"); + } + + VmPtr = XVidC_GetVideoModeData(VmId); + if (!VmPtr) { + return ("Video mode not supported"); + } + + return VmPtr->Name; +} + +/******************************************************************************/ +/** + * This function returns the frame rate name for index specified. + * + * @param VmId specifies the resolution id. + * + * @return Pointer to a frame rate name string. + * + * @note None. + * +*******************************************************************************/ +const char *XVidC_GetFrameRateStr(XVidC_VideoMode VmId) +{ + const XVidC_VideoTimingMode *VmPtr; + + VmPtr = XVidC_GetVideoModeData(VmId); + if (!VmPtr) { + return ("Video mode not supported"); + } + + switch (VmPtr->FrameRate) { + case (XVIDC_FR_24HZ): return ("24Hz"); + case (XVIDC_FR_25HZ): return ("25Hz"); + case (XVIDC_FR_30HZ): return ("30Hz"); + case (XVIDC_FR_48HZ): return ("48Hz"); + case (XVIDC_FR_50HZ): return ("50Hz"); + case (XVIDC_FR_56HZ): return ("56Hz"); + case (XVIDC_FR_60HZ): return ("60Hz"); + case (XVIDC_FR_65HZ): return ("65Hz"); + case (XVIDC_FR_67HZ): return ("67Hz"); + case (XVIDC_FR_70HZ): return ("70Hz"); + case (XVIDC_FR_72HZ): return ("72Hz"); + case (XVIDC_FR_75HZ): return ("75Hz"); + case (XVIDC_FR_85HZ): return ("85Hz"); + case (XVIDC_FR_87HZ): return ("87Hz"); + case (XVIDC_FR_88HZ): return ("88Hz"); + case (XVIDC_FR_96HZ): return ("96Hz"); + case (XVIDC_FR_100HZ): return ("100Hz"); + case (XVIDC_FR_120HZ): return ("120Hz"); + + default: + return ("Frame rate not supported"); + } +} + +/******************************************************************************/ +/** + * This function returns a string representation of the enumerated type, + * XVidC_3DFormat. + * + * @param Format specifies the value to convert. + * + * @return Pointer to the converted string. + * + * @note None. + * +*******************************************************************************/ +const char *XVidC_Get3DFormatStr(XVidC_3DFormat Format) +{ + switch (Format) { + case XVIDC_3D_FRAME_PACKING: + return ("Frame Packing"); + + case XVIDC_3D_FIELD_ALTERNATIVE: + return ("Field Alternative"); + + case XVIDC_3D_LINE_ALTERNATIVE: + return ("Line Alternative"); + + case XVIDC_3D_SIDE_BY_SIDE_FULL: + return ("Side-by-Side(full)"); + + case XVIDC_3D_TOP_AND_BOTTOM_HALF: + return ("Top-and-Bottom(half)"); + + case XVIDC_3D_SIDE_BY_SIDE_HALF: + return ("Side-by-Side(half)"); + + default: + return ("Unknown"); + } +} + +/******************************************************************************/ +/** + * This function returns the color format name for index specified. + * + * @param ColorFormatId specifies the index of color format space. + * + * @return Pointer to a color space name string. + * + * @note None. + * +*******************************************************************************/ +const char *XVidC_GetColorFormatStr(XVidC_ColorFormat ColorFormatId) +{ + switch (ColorFormatId) { + case XVIDC_CSF_RGB: return ("RGB"); + case XVIDC_CSF_YCRCB_444: return ("YUV_444"); + case XVIDC_CSF_YCRCB_422: return ("YUV_422"); + case XVIDC_CSF_YCRCB_420: return ("YUV_420"); + case XVIDC_CSF_YONLY: return ("Y_ONLY"); + case XVIDC_CSF_RGBA: return ("RGBA"); + case XVIDC_CSF_YCRCBA_444: return ("YUVA_444"); + case XVIDC_CSF_MEM_RGBX8: return ("RGBX8"); + case XVIDC_CSF_MEM_YUVX8: return ("YUVX8"); + case XVIDC_CSF_MEM_YUYV8: return ("YUYV8"); + case XVIDC_CSF_MEM_RGBA8: return ("RGBA8"); + case XVIDC_CSF_MEM_YUVA8: return ("YUVA8"); + case XVIDC_CSF_MEM_RGBX10: return ("RGBX10"); + case XVIDC_CSF_MEM_YUVX10: return ("YUVX10"); + case XVIDC_CSF_MEM_RGB565: return ("RGB565"); + case XVIDC_CSF_MEM_Y_UV8: return ("Y_UV8"); + case XVIDC_CSF_MEM_Y_UV8_420: return ("Y_UV8_420"); + case XVIDC_CSF_MEM_RGB8: return ("RGB8"); + case XVIDC_CSF_MEM_YUV8: return ("YUV8"); + case XVIDC_CSF_MEM_Y_UV10: return ("Y_UV10"); + case XVIDC_CSF_MEM_Y_UV10_420: return ("Y_UV10_420"); + case XVIDC_CSF_MEM_Y8: return ("Y8"); + case XVIDC_CSF_MEM_Y10: return ("Y10"); + case XVIDC_CSF_MEM_BGRA8: return ("BGRA8"); + case XVIDC_CSF_MEM_BGRX8: return ("BGRX8"); + case XVIDC_CSF_MEM_UYVY8: return ("UYVY8"); + case XVIDC_CSF_MEM_BGR8: return ("BGR8"); + case XVIDC_CSF_YCBCR_422: return ("YCBCR_422"); + case XVIDC_CSF_YCBCR_420: return ("YCBCR_420"); + default: + return ("Color space format not supported"); + } +} + +/******************************************************************************/ +/** + * This function returns the frame rate for index specified. + * + * @param VmId specifies the resolution id. + * + * @return Frame rate in Hz. + * + * @note None. + * +*******************************************************************************/ +XVidC_FrameRate XVidC_GetFrameRate(XVidC_VideoMode VmId) +{ + const XVidC_VideoTimingMode *VmPtr; + + VmPtr = XVidC_GetVideoModeData(VmId); + if (!VmPtr) { + return XVIDC_FR_NUM_SUPPORTED; + } + + return VmPtr->FrameRate; +} + +/******************************************************************************/ +/** + * This function returns the timing parameters for specified resolution. + * + * @param VmId specifies the resolution id. + * + * @return Pointer to a XVidC_VideoTiming structure. + * + * @note None. + * +*******************************************************************************/ +const XVidC_VideoTiming *XVidC_GetTimingInfo(XVidC_VideoMode VmId) +{ + const XVidC_VideoTimingMode *VmPtr; + + VmPtr = XVidC_GetVideoModeData(VmId); + if (!VmPtr) { + return NULL; + } + + return &VmPtr->Timing; +} + +/******************************************************************************/ +/** + * This function sets the VideoStream structure for the specified video format. + * + * @param VidStrmPtr is a pointer to the XVidC_VideoStream structure to be + * set. + * @param VmId specifies the resolution ID. + * @param ColorFormat specifies the color format type. + * @param Bpc specifies the color depth/bits per color component. + * @param Ppc specifies the pixels per clock. + * + * @return + * - XST_SUCCESS if the timing for the supplied ID was found. + * - XST_FAILURE, otherwise. + * + * @note None. + * +*******************************************************************************/ +u32 XVidC_SetVideoStream(XVidC_VideoStream *VidStrmPtr, XVidC_VideoMode VmId, + XVidC_ColorFormat ColorFormat, XVidC_ColorDepth Bpc, + XVidC_PixelsPerClock Ppc) +{ + const XVidC_VideoTiming *TimingPtr; + + /* Verify arguments. */ + Xil_AssertNonvoid(VidStrmPtr != NULL); + Xil_AssertNonvoid(ColorFormat < XVIDC_CSF_NUM_SUPPORTED); + Xil_AssertNonvoid((Bpc == XVIDC_BPC_6) || + (Bpc == XVIDC_BPC_8) || + (Bpc == XVIDC_BPC_10) || + (Bpc == XVIDC_BPC_12) || + (Bpc == XVIDC_BPC_14) || + (Bpc == XVIDC_BPC_16) || + (Bpc == XVIDC_BPC_UNKNOWN)); + Xil_AssertNonvoid((Ppc == XVIDC_PPC_1) || + (Ppc == XVIDC_PPC_2) || + (Ppc == XVIDC_PPC_4)); + + /* Get the timing from the video timing table. */ + TimingPtr = XVidC_GetTimingInfo(VmId); + if (!TimingPtr) { + return XST_FAILURE; + } + VidStrmPtr->VmId = VmId; + VidStrmPtr->Timing = *TimingPtr; + VidStrmPtr->FrameRate = XVidC_GetFrameRate(VmId); + VidStrmPtr->IsInterlaced = XVidC_IsInterlaced(VmId); + VidStrmPtr->ColorFormatId = ColorFormat; + VidStrmPtr->ColorDepth = Bpc; + VidStrmPtr->PixPerClk = Ppc; + + /* Set stream to 2D. */ + VidStrmPtr->Is3D = FALSE; + VidStrmPtr->Info_3D.Format = XVIDC_3D_UNKNOWN; + VidStrmPtr->Info_3D.Sampling.Method = XVIDC_3D_SAMPLING_UNKNOWN; + VidStrmPtr->Info_3D.Sampling.Position = XVIDC_3D_SAMPPOS_UNKNOWN; + + return XST_SUCCESS; +} + +/******************************************************************************/ +/** + * This function sets the VideoStream structure for the specified 3D video + * format. + * + * @param VidStrmPtr is a pointer to the XVidC_VideoStream structure to be + * set. + * @param VmId specifies the resolution ID. + * @param ColorFormat specifies the color format type. + * @param Bpc specifies the color depth/bits per color component. + * @param Ppc specifies the pixels per clock. + * @param Info3DPtr is a pointer to a XVidC_3DInfo structure. + * + * @return + * - XST_SUCCESS if the timing for the supplied ID was found. + * - XST_FAILURE, otherwise. + * + * @return + * - XST_SUCCESS + * - XST_FAILURE + * + * @note None. + * +*******************************************************************************/ +u32 XVidC_Set3DVideoStream(XVidC_VideoStream *VidStrmPtr, XVidC_VideoMode VmId, + XVidC_ColorFormat ColorFormat, XVidC_ColorDepth Bpc, + XVidC_PixelsPerClock Ppc, XVidC_3DInfo *Info3DPtr) +{ + u32 Status; + u16 Vblank0; + u16 Vblank1; + + /* Verify arguments */ + Xil_AssertNonvoid(Info3DPtr != NULL); + + /* Initialize with info for 2D frame. */ + Status = XVidC_SetVideoStream(VidStrmPtr, VmId, ColorFormat, Bpc, Ppc); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + + /* Set stream to 3D. */ + VidStrmPtr->Is3D = TRUE; + VidStrmPtr->Info_3D = *Info3DPtr; + + /* Only 3D format supported is frame packing. */ + if (Info3DPtr->Format != XVIDC_3D_FRAME_PACKING) { + return XST_FAILURE; + } + + /* Update the timing based on the 3D format. */ + + /* An interlaced format is converted to a progressive frame: */ + /* 3D VActive = (2D VActive * 4) + (2D VBlank field0) + + (2D Vblank field1 * 2) */ + if (VidStrmPtr->IsInterlaced) { + Vblank0 = VidStrmPtr->Timing.F0PVTotal - + VidStrmPtr->Timing.VActive; + Vblank1 = VidStrmPtr->Timing.F1VTotal - + VidStrmPtr->Timing.VActive; + VidStrmPtr->Timing.VActive = (VidStrmPtr->Timing.VActive * 4) + + Vblank0 + (Vblank1 * 2); + + /* Set VTotal */ + VidStrmPtr->Timing.F0PVTotal *= 2; + VidStrmPtr->Timing.F0PVTotal += VidStrmPtr->Timing.F1VTotal * 2; + + /* Clear field 1 values. */ + VidStrmPtr->Timing.F1VFrontPorch = 0; + VidStrmPtr->Timing.F1VSyncWidth = 0; + VidStrmPtr->Timing.F1VBackPorch = 0; + VidStrmPtr->Timing.F1VTotal = 0; + + /* Set format to progressive */ + VidStrmPtr->IsInterlaced = FALSE; + } + /* Progressive */ + else { + /* 3D Vactive = (2D VActive * 2) + (2D VBlank) */ + Vblank0 = VidStrmPtr->Timing.F0PVTotal - + VidStrmPtr->Timing.VActive; + VidStrmPtr->Timing.VActive = (VidStrmPtr->Timing.VActive * 2) + + Vblank0; + + /* Set VTotal. */ + VidStrmPtr->Timing.F0PVTotal = VidStrmPtr->Timing.F0PVTotal * 2; + } + + return XST_SUCCESS; +} + +/******************************************************************************/ +/** + * This function prints the stream information on STDIO/UART console. + * + * @param Stream is a pointer to video stream. + * + * @return None. + * + * @note None. + * +*******************************************************************************/ +void XVidC_ReportStreamInfo(const XVidC_VideoStream *Stream) +{ + if (!XVidC_GetVideoModeData(Stream->VmId) && + (Stream->VmId != XVIDC_VM_CUSTOM)) { + xil_printf("\tThe stream ID (%d) is not supported.\r\n", + Stream->VmId); + return; + } + + xil_printf("\tColor Format: %s\r\n", + XVidC_GetColorFormatStr(Stream->ColorFormatId)); + xil_printf("\tColor Depth: %d\r\n", Stream->ColorDepth); + xil_printf("\tPixels Per Clock: %d\r\n", Stream->PixPerClk); + xil_printf("\tMode: %s\r\n", + Stream->IsInterlaced ? "Interlaced" : "Progressive"); + + if (Stream->Is3D) { + xil_printf("\t3D Format: %s\r\n", + XVidC_Get3DFormatStr(Stream->Info_3D.Format)); + } + + if (Stream->VmId == XVIDC_VM_CUSTOM) { + xil_printf("\tFrame Rate: %dHz\r\n", + Stream->FrameRate); + xil_printf("\tResolution: %dx%d [Custom Mode]\r\n", + Stream->Timing.HActive, Stream->Timing.VActive); + xil_printf("\tPixel Clock: %d\r\n", + XVidC_GetPixelClockHzByHVFr( + Stream->Timing.HTotal, + Stream->Timing.F0PVTotal, + Stream->FrameRate)); + } + else { + xil_printf("\tFrame Rate: %s\r\n", + XVidC_GetFrameRateStr(Stream->VmId)); + xil_printf("\tResolution: %s\r\n", + XVidC_GetVideoModeStr(Stream->VmId)); + xil_printf("\tPixel Clock: %d\r\n", + XVidC_GetPixelClockHzByVmId(Stream->VmId)); + } +} + +/******************************************************************************/ +/** + * This function prints timing information on STDIO/Uart console. + * + * @param Timing is a pointer to Video Timing structure of the stream. + * @param IsInterlaced is a TRUE/FALSE flag that denotes the timing + * parameter is for interlaced/progressive stream. + * + * @return None. + * + * @note None. + * +*******************************************************************************/ +void XVidC_ReportTiming(const XVidC_VideoTiming *Timing, u8 IsInterlaced) +{ + xil_printf("\r\n\tHSYNC Timing: hav=%04d, hfp=%02d, hsw=%02d(hsp=%d), " + "hbp=%03d, htot=%04d \n\r", Timing->HActive, + Timing->HFrontPorch, Timing->HSyncWidth, + Timing->HSyncPolarity, + Timing->HBackPorch, Timing->HTotal); + + /* Interlaced */ + if (IsInterlaced) { + xil_printf("\tVSYNC Timing (Field 0): vav=%04d, vfp=%02d, " + "vsw=%02d(vsp=%d), vbp=%03d, vtot=%04d\n\r", + Timing->VActive, Timing->F0PVFrontPorch, + Timing->F0PVSyncWidth, Timing->VSyncPolarity, + Timing->F0PVBackPorch, Timing->F0PVTotal); + xil_printf("\tVSYNC Timing (Field 1): vav=%04d, vfp=%02d, " + "vsw=%02d(vsp=%d), vbp=%03d, vtot=%04d\n\r", + Timing->VActive, Timing->F1VFrontPorch, + Timing->F1VSyncWidth, Timing->VSyncPolarity, + Timing->F1VBackPorch, Timing->F1VTotal); + } + /* Progressive */ + else { + xil_printf("\tVSYNC Timing: vav=%04d, vfp=%02d, " + "vsw=%02d(vsp=%d), vbp=%03d, vtot=%04d\n\r", + Timing->VActive, Timing->F0PVFrontPorch, + Timing->F0PVSyncWidth, Timing->VSyncPolarity, + Timing->F0PVBackPorch, Timing->F0PVTotal); + } +} + +/******************************************************************************/ +/** + * This function returns the pointer to video mode data at the provided index + * of the custom video mode table. + * + * @param VmId specifies the resolution ID. + * + * @return Pointer to XVidC_VideoTimingMode structure based on the given + * video mode. + * + * @note None. + * +*******************************************************************************/ +static const XVidC_VideoTimingMode *XVidC_GetCustomVideoModeData( + XVidC_VideoMode VmId) +{ + u16 Index; + + for (Index = 0; Index < XVidC_NumCustomModes; Index++) { + if (VmId == (XVidC_CustomTimingModes[Index].VmId)) { + return &(XVidC_CustomTimingModes[Index]); + } + } + + /* ID not found within the custom video mode table. */ + return NULL; +} + +/******************************************************************************/ +/** + * This function returns whether or not the video timing mode is a reduced + * blanking mode or not. + * + * @param VideoModeStr specifies the resolution name string. + * @param RbN specifies the type of reduced blanking: + * - 0 = No Reduced Blanking + * - 1 = RB + * - 2 = RB2 + * + * @return If the reduced blanking type is compatible with the video mode: + * - 0 = Not supported + * - 1 = Video mode supports the RB type + * + * @note None. + * +*******************************************************************************/ +static u8 XVidC_IsVtmRb(const char *VideoModeStr, u8 RbN) +{ + while ((*VideoModeStr !='\0') && (*VideoModeStr != 'R')) { + VideoModeStr++; + } + + if (*(VideoModeStr + 2) == ')') { + return RbN == 1; + } + if (*(VideoModeStr + 2) == '2') { + return RbN == 2; + } + return 0; +} +/** @} */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/video_common_v4_3/src/xvidc.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/video_common_v4_3/src/xvidc.h new file mode 100644 index 000000000..bcd3d0b7a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/video_common_v4_3/src/xvidc.h @@ -0,0 +1,621 @@ +/******************************************************************************* + * + * Copyright (C) 2017 Xilinx, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * Use of the Software is limited solely to applications: + * (a) running on a Xilinx device, or + * (b) that interact with a Xilinx device through a bus or interconnect. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of the Xilinx shall not be used + * in advertising or otherwise to promote the sale, use or other dealings in + * this Software without prior written authorization from Xilinx. + * +*******************************************************************************/ +/******************************************************************************/ +/** + * + * @file xvidc.h + * @addtogroup video_common_v4_3 + * @{ + * @details + * + * Contains common structures, definitions, macros, and utility functions that + * are typically used by video-related drivers and applications. + * + * @note None. + * + * 
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -----------------------------------------------
+ * 1.0   rc,  01/10/15 Initial release.
+ *       als
+ * 2.0   als  08/14/15 Added new video timings.
+ * 2.2   als  02/01/16 Functions with pointer arguments that don't modify
+ *                     contents now const.
+ *                     Added ability to insert a custom video timing table:
+ *                         XVidC_RegisterCustomTimingModes
+ *                         XVidC_UnregisterCustomTimingMode
+ *       yh            Added 3D support.
+ * 3.0   aad  05/13/16 Added API to search for RB video modes.
+ *       als  05/16/16 Added Y-only to color format enum.
+ * 3.1   rco  07/26/17 Moved timing table extern definition to xvidc.c
+ *                     Added video-in-memory color formats
+ *                     Updated XVidC_RegisterCustomTimingModes API signature
+ * 4.1   rco  11/23/17 Added new memory formats
+ *                     Added xil_printf include statement
+ *                     Added new API XVidC_GetVideoModeIdWBlanking
+ *                     Fix C++ warnings
+ * 4.2   jsr  07/22/17 Added new video modes, framerates, color formats for SDI
+ *                     New member AspectRatio is added to video stream structure
+ *                     Reordered XVidC_VideoMode enum variables and corrected the
+ *                     memory format enums
+ *       aad  07/10/17 Add XVIDC_VM_3840x2160_60_P_RB video format
+ *       vyc  10/04/17 Added new streaming alpha formats and new memory formats
+ *       aad  09/05/17 Add XVIDC_VM_1366x768_60_P_RB resolution
+ * 4.3   eb   26/01/18 Added API XVidC_GetVideoModeIdExtensive
+ *       jsr  02/22/18 Added XVIDC_CSF_YCBCR_420 color space format
+ *       vyc  04/04/18 Added BGR8 memory format
+ *
+ * +*******************************************************************************/ + +#ifndef XVIDC_H_ /* Prevent circular inclusions by using protection macros. */ +#define XVIDC_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************* Include Files ********************************/ + +#include "xil_types.h" +#include "xil_printf.h" + +/************************** Constant Definitions ******************************/ + +/** + * This typedef enumerates the list of available standard display monitor + * timings as specified in the xvidc_timings_table.c file. The naming format is: + * + * XVIDC_VM___(_RB) + * + * Where RB stands for reduced blanking. + */ +typedef enum { + /* Interlaced modes. */ + XVIDC_VM_720x480_60_I = 0, + XVIDC_VM_720x576_50_I, + XVIDC_VM_1440x480_60_I, + XVIDC_VM_1440x576_50_I, + XVIDC_VM_1920x1080_48_I, + XVIDC_VM_1920x1080_50_I, + XVIDC_VM_1920x1080_60_I, + XVIDC_VM_1920x1080_96_I, + XVIDC_VM_1920x1080_100_I, + XVIDC_VM_1920x1080_120_I, + XVIDC_VM_2048x1080_48_I, + XVIDC_VM_2048x1080_50_I, + XVIDC_VM_2048x1080_60_I, + XVIDC_VM_2048x1080_96_I, + XVIDC_VM_2048x1080_100_I, + XVIDC_VM_2048x1080_120_I, + + + /* Progressive modes. */ + XVIDC_VM_640x350_85_P, + XVIDC_VM_640x480_60_P, + XVIDC_VM_640x480_72_P, + XVIDC_VM_640x480_75_P, + XVIDC_VM_640x480_85_P, + XVIDC_VM_720x400_85_P, + XVIDC_VM_720x480_60_P, + XVIDC_VM_720x576_50_P, + XVIDC_VM_800x600_56_P, + XVIDC_VM_800x600_60_P, + XVIDC_VM_800x600_72_P, + XVIDC_VM_800x600_75_P, + XVIDC_VM_800x600_85_P, + XVIDC_VM_800x600_120_P_RB, + XVIDC_VM_848x480_60_P, + XVIDC_VM_1024x768_60_P, + XVIDC_VM_1024x768_70_P, + XVIDC_VM_1024x768_75_P, + XVIDC_VM_1024x768_85_P, + XVIDC_VM_1024x768_120_P_RB, + XVIDC_VM_1152x864_75_P, + XVIDC_VM_1280x720_24_P, + XVIDC_VM_1280x720_25_P, + XVIDC_VM_1280x720_30_P, + XVIDC_VM_1280x720_50_P, + XVIDC_VM_1280x720_60_P, + XVIDC_VM_1280x768_60_P, + XVIDC_VM_1280x768_60_P_RB, + XVIDC_VM_1280x768_75_P, + XVIDC_VM_1280x768_85_P, + XVIDC_VM_1280x768_120_P_RB, + XVIDC_VM_1280x800_60_P, + XVIDC_VM_1280x800_60_P_RB, + XVIDC_VM_1280x800_75_P, + XVIDC_VM_1280x800_85_P, + XVIDC_VM_1280x800_120_P_RB, + XVIDC_VM_1280x960_60_P, + XVIDC_VM_1280x960_85_P, + XVIDC_VM_1280x960_120_P_RB, + XVIDC_VM_1280x1024_60_P, + XVIDC_VM_1280x1024_75_P, + XVIDC_VM_1280x1024_85_P, + XVIDC_VM_1280x1024_120_P_RB, + XVIDC_VM_1360x768_60_P, + XVIDC_VM_1360x768_120_P_RB, + XVIDC_VM_1366x768_60_P, + XVIDC_VM_1366x768_60_P_RB, + XVIDC_VM_1400x1050_60_P, + XVIDC_VM_1400x1050_60_P_RB, + XVIDC_VM_1400x1050_75_P, + XVIDC_VM_1400x1050_85_P, + XVIDC_VM_1400x1050_120_P_RB, + XVIDC_VM_1440x240_60_P, + XVIDC_VM_1440x900_60_P, + XVIDC_VM_1440x900_60_P_RB, + XVIDC_VM_1440x900_75_P, + XVIDC_VM_1440x900_85_P, + XVIDC_VM_1440x900_120_P_RB, + XVIDC_VM_1600x1200_60_P, + XVIDC_VM_1600x1200_65_P, + XVIDC_VM_1600x1200_70_P, + XVIDC_VM_1600x1200_75_P, + XVIDC_VM_1600x1200_85_P, + XVIDC_VM_1600x1200_120_P_RB, + XVIDC_VM_1680x720_50_P, + XVIDC_VM_1680x720_60_P, + XVIDC_VM_1680x720_100_P, + XVIDC_VM_1680x720_120_P, + XVIDC_VM_1680x1050_50_P, + XVIDC_VM_1680x1050_60_P, + XVIDC_VM_1680x1050_60_P_RB, + XVIDC_VM_1680x1050_75_P, + XVIDC_VM_1680x1050_85_P, + XVIDC_VM_1680x1050_120_P_RB, + XVIDC_VM_1792x1344_60_P, + XVIDC_VM_1792x1344_75_P, + XVIDC_VM_1792x1344_120_P_RB, + XVIDC_VM_1856x1392_60_P, + XVIDC_VM_1856x1392_75_P, + XVIDC_VM_1856x1392_120_P_RB, + XVIDC_VM_1920x1080_24_P, + XVIDC_VM_1920x1080_25_P, + XVIDC_VM_1920x1080_30_P, + XVIDC_VM_1920x1080_48_P, + XVIDC_VM_1920x1080_50_P, + XVIDC_VM_1920x1080_60_P, + XVIDC_VM_1920x1080_100_P, + XVIDC_VM_1920x1080_120_P, + XVIDC_VM_1920x1200_60_P, + XVIDC_VM_1920x1200_60_P_RB, + XVIDC_VM_1920x1200_75_P, + XVIDC_VM_1920x1200_85_P, + XVIDC_VM_1920x1200_120_P_RB, + XVIDC_VM_1920x1440_60_P, + XVIDC_VM_1920x1440_75_P, + XVIDC_VM_1920x1440_120_P_RB, + XVIDC_VM_1920x2160_60_P, + XVIDC_VM_2048x1080_24_P, + XVIDC_VM_2048x1080_25_P, + XVIDC_VM_2048x1080_30_P, + XVIDC_VM_2048x1080_48_P, + XVIDC_VM_2048x1080_50_P, + XVIDC_VM_2048x1080_60_P, + XVIDC_VM_2048x1080_100_P, + XVIDC_VM_2048x1080_120_P, + XVIDC_VM_2560x1080_50_P, + XVIDC_VM_2560x1080_60_P, + XVIDC_VM_2560x1080_100_P, + XVIDC_VM_2560x1080_120_P, + XVIDC_VM_2560x1600_60_P, + XVIDC_VM_2560x1600_60_P_RB, + XVIDC_VM_2560x1600_75_P, + XVIDC_VM_2560x1600_85_P, + XVIDC_VM_2560x1600_120_P_RB, + XVIDC_VM_3840x2160_24_P, + XVIDC_VM_3840x2160_25_P, + XVIDC_VM_3840x2160_30_P, + XVIDC_VM_3840x2160_48_P, + XVIDC_VM_3840x2160_50_P, + XVIDC_VM_3840x2160_60_P, + XVIDC_VM_3840x2160_60_P_RB, + XVIDC_VM_4096x2160_24_P, + XVIDC_VM_4096x2160_25_P, + XVIDC_VM_4096x2160_30_P, + XVIDC_VM_4096x2160_48_P, + XVIDC_VM_4096x2160_50_P, + XVIDC_VM_4096x2160_60_P, + XVIDC_VM_4096x2160_60_P_RB, + + XVIDC_VM_NUM_SUPPORTED, + XVIDC_VM_USE_EDID_PREFERRED, + XVIDC_VM_NO_INPUT, + XVIDC_VM_NOT_SUPPORTED, + XVIDC_VM_CUSTOM, + + /* Marks beginning/end of interlaced/progressive modes in the table. */ + XVIDC_VM_INTL_START = XVIDC_VM_720x480_60_I, + XVIDC_VM_PROG_START = XVIDC_VM_640x350_85_P, + XVIDC_VM_INTL_END = (XVIDC_VM_PROG_START - 1), + XVIDC_VM_PROG_END = (XVIDC_VM_NUM_SUPPORTED - 1), + + /* Common naming. */ + XVIDC_VM_480_60_I = XVIDC_VM_720x480_60_I, + XVIDC_VM_576_50_I = XVIDC_VM_720x576_50_I, + XVIDC_VM_1080_50_I = XVIDC_VM_1920x1080_50_I, + XVIDC_VM_1080_60_I = XVIDC_VM_1920x1080_60_I, + XVIDC_VM_VGA_60_P = XVIDC_VM_640x480_60_P, + XVIDC_VM_480_60_P = XVIDC_VM_720x480_60_P, + XVIDC_VM_SVGA_60_P = XVIDC_VM_800x600_60_P, + XVIDC_VM_XGA_60_P = XVIDC_VM_1024x768_60_P, + XVIDC_VM_720_50_P = XVIDC_VM_1280x720_50_P, + XVIDC_VM_720_60_P = XVIDC_VM_1280x720_60_P, + XVIDC_VM_WXGA_60_P = XVIDC_VM_1366x768_60_P, + XVIDC_VM_UXGA_60_P = XVIDC_VM_1600x1200_60_P, + XVIDC_VM_WSXGA_60_P = XVIDC_VM_1680x1050_60_P, + XVIDC_VM_1080_24_P = XVIDC_VM_1920x1080_24_P, + XVIDC_VM_1080_25_P = XVIDC_VM_1920x1080_25_P, + XVIDC_VM_1080_30_P = XVIDC_VM_1920x1080_30_P, + XVIDC_VM_1080_50_P = XVIDC_VM_1920x1080_50_P, + XVIDC_VM_1080_60_P = XVIDC_VM_1920x1080_60_P, + XVIDC_VM_WUXGA_60_P = XVIDC_VM_1920x1200_60_P, + XVIDC_VM_UHD2_60_P = XVIDC_VM_1920x2160_60_P, + XVIDC_VM_UHD_24_P = XVIDC_VM_3840x2160_24_P, + XVIDC_VM_UHD_25_P = XVIDC_VM_3840x2160_25_P, + XVIDC_VM_UHD_30_P = XVIDC_VM_3840x2160_30_P, + XVIDC_VM_UHD_60_P = XVIDC_VM_3840x2160_60_P, + XVIDC_VM_4K2K_60_P = XVIDC_VM_4096x2160_60_P, + XVIDC_VM_4K2K_60_P_RB = XVIDC_VM_4096x2160_60_P_RB, +} XVidC_VideoMode; + +/** + * Progressive/interlaced video format. + */ +typedef enum { + XVIDC_VF_PROGRESSIVE = 0, + XVIDC_VF_INTERLACED, + XVIDC_VF_UNKNOWN +} XVidC_VideoFormat; + +/** + * Frame rate. + */ +typedef enum { + XVIDC_FR_24HZ = 24, + XVIDC_FR_25HZ = 25, + XVIDC_FR_30HZ = 30, + XVIDC_FR_48HZ = 48, + XVIDC_FR_50HZ = 50, + XVIDC_FR_56HZ = 56, + XVIDC_FR_60HZ = 60, + XVIDC_FR_65HZ = 65, + XVIDC_FR_67HZ = 67, + XVIDC_FR_70HZ = 70, + XVIDC_FR_72HZ = 72, + XVIDC_FR_75HZ = 75, + XVIDC_FR_85HZ = 85, + XVIDC_FR_87HZ = 87, + XVIDC_FR_88HZ = 88, + XVIDC_FR_96HZ = 96, + XVIDC_FR_100HZ = 100, + XVIDC_FR_120HZ = 120, + XVIDC_FR_NUM_SUPPORTED = 18, + XVIDC_FR_UNKNOWN +} XVidC_FrameRate; + +/** + * Color depth - bits per color component. + */ +typedef enum { + XVIDC_BPC_6 = 6, + XVIDC_BPC_8 = 8, + XVIDC_BPC_10 = 10, + XVIDC_BPC_12 = 12, + XVIDC_BPC_14 = 14, + XVIDC_BPC_16 = 16, + XVIDC_BPC_NUM_SUPPORTED = 6, + XVIDC_BPC_UNKNOWN +} XVidC_ColorDepth; + +/** + * Pixels per clock. + */ +typedef enum { + XVIDC_PPC_1 = 1, + XVIDC_PPC_2 = 2, + XVIDC_PPC_4 = 4, + XVIDC_PPC_8 = 8, + XVIDC_PPC_NUM_SUPPORTED = 4, +} XVidC_PixelsPerClock; + +/** + * Color space format. + */ +typedef enum { + /* Streaming video formats */ + XVIDC_CSF_RGB = 0, + XVIDC_CSF_YCRCB_444, + XVIDC_CSF_YCRCB_422, + XVIDC_CSF_YCRCB_420, + XVIDC_CSF_YONLY, + XVIDC_CSF_RGBA, + XVIDC_CSF_YCRCBA_444, + + /* 6 empty slots reserved for video formats for future + * extension + */ + + /* Video in memory formats */ + XVIDC_CSF_MEM_RGBX8 = 10, // [31:0] x:B:G:R 8:8:8:8 + XVIDC_CSF_MEM_YUVX8, // [31:0] x:V:U:Y 8:8:8:8 + XVIDC_CSF_MEM_YUYV8, // [31:0] V:Y:U:Y 8:8:8:8 + XVIDC_CSF_MEM_RGBA8, // [31:0] A:B:G:R 8:8:8:8 + XVIDC_CSF_MEM_YUVA8, // [31:0] A:V:U:Y 8:8:8:8 + XVIDC_CSF_MEM_RGBX10, // [31:0] x:B:G:R 2:10:10:10 + XVIDC_CSF_MEM_YUVX10, // [31:0] x:V:U:Y 2:10:10:10 + XVIDC_CSF_MEM_RGB565, // [15:0] B:G:R 5:6:5 + XVIDC_CSF_MEM_Y_UV8, // [15:0] Y:Y 8:8, [15:0] V:U 8:8 + XVIDC_CSF_MEM_Y_UV8_420, // [15:0] Y:Y 8:8, [15:0] V:U 8:8 + XVIDC_CSF_MEM_RGB8, // [23:0] B:G:R 8:8:8 + XVIDC_CSF_MEM_YUV8, // [24:0] V:U:Y 8:8:8 + XVIDC_CSF_MEM_Y_UV10, // [31:0] x:Y:Y:Y 2:10:10:10 [31:0] x:U:V:U 2:10:10:10 + XVIDC_CSF_MEM_Y_UV10_420, // [31:0] x:Y:Y:Y 2:10:10:10 [31:0] x:U:V:U 2:10:10:10 + XVIDC_CSF_MEM_Y8, // [31:0] Y:Y:Y:Y 8:8:8:8 + XVIDC_CSF_MEM_Y10, // [31:0] x:Y:Y:Y 2:10:10:10 + XVIDC_CSF_MEM_BGRA8, // [31:0] A:R:G:B 8:8:8:8 + XVIDC_CSF_MEM_BGRX8, // [31:0] X:R:G:B 8:8:8:8 + XVIDC_CSF_MEM_UYVY8, // [31:0] Y:V:Y:U 8:8:8:8 + XVIDC_CSF_MEM_BGR8, // [23:0] R:G:B 8:8:8 + XVIDC_CSF_MEM_END, // End of memory formats + + /* Streaming formats with components re-ordered */ + XVIDC_CSF_YCBCR_422 = 64, + XVIDC_CSF_YCBCR_420, + + + XVIDC_CSF_NUM_SUPPORTED, // includes the reserved slots + XVIDC_CSF_UNKNOWN, + XVIDC_CSF_STRM_START = XVIDC_CSF_RGB, + XVIDC_CSF_STRM_END = XVIDC_CSF_YONLY, + XVIDC_CSF_MEM_START = XVIDC_CSF_MEM_RGBX8, + XVIDC_CSF_NUM_STRM = (XVIDC_CSF_STRM_END - XVIDC_CSF_STRM_START + 1), + XVIDC_CSF_NUM_MEM = (XVIDC_CSF_MEM_END - XVIDC_CSF_MEM_START) +} XVidC_ColorFormat; + + +/** + * Image Aspect Ratio. + */ +typedef enum { + XVIDC_AR_4_3 = 0, + XVIDC_AR_16_9 = 1 +} XVidC_AspectRatio; + +/** + * Color space conversion standard. + */ +typedef enum { + XVIDC_BT_2020 = 0, + XVIDC_BT_709, + XVIDC_BT_601, + XVIDC_BT_NUM_SUPPORTED, + XVIDC_BT_UNKNOWN +} XVidC_ColorStd; + +/** + * Color conversion output range. + */ +typedef enum { + XVIDC_CR_16_235 = 0, + XVIDC_CR_16_240, + XVIDC_CR_0_255, + XVIDC_CR_NUM_SUPPORTED, + XVIDC_CR_UNKNOWN_RANGE +} XVidC_ColorRange; + +/** + * 3D formats. + */ +typedef enum { + XVIDC_3D_FRAME_PACKING = 0, /**< Frame packing. */ + XVIDC_3D_FIELD_ALTERNATIVE, /**< Field alternative. */ + XVIDC_3D_LINE_ALTERNATIVE, /**< Line alternative. */ + XVIDC_3D_SIDE_BY_SIDE_FULL, /**< Side-by-side (full). */ + XVIDC_3D_TOP_AND_BOTTOM_HALF, /**< Top-and-bottom (half). */ + XVIDC_3D_SIDE_BY_SIDE_HALF, /**< Side-by-side (half). */ + XVIDC_3D_UNKNOWN +} XVidC_3DFormat; + +/** + * 3D Sub-sampling methods. + */ +typedef enum { + XVIDC_3D_SAMPLING_HORIZONTAL = 0, /**< Horizontal sub-sampling. */ + XVIDC_3D_SAMPLING_QUINCUNX, /**< Quincunx matrix. */ + XVIDC_3D_SAMPLING_UNKNOWN +} XVidC_3DSamplingMethod; + +/** + * 3D Sub-sampling positions. + */ +typedef enum { + XVIDC_3D_SAMPPOS_OLOR = 0, /**< Odd/Left, Odd/Right. */ + XVIDC_3D_SAMPPOS_OLER, /**< Odd/Left, Even/Right. */ + XVIDC_3D_SAMPPOS_ELOR, /**< Even/Left, Odd/Right. */ + XVIDC_3D_SAMPPOS_ELER, /**< Even/Left, Even/Right. */ + XVIDC_3D_SAMPPOS_UNKNOWN +} XVidC_3DSamplingPosition; + +/****************************** Type Definitions ******************************/ + +/** + * Video timing structure. + */ +typedef struct { + u16 HActive; + u16 HFrontPorch; + u16 HSyncWidth; + u16 HBackPorch; + u16 HTotal; + u8 HSyncPolarity; + u16 VActive; + u16 F0PVFrontPorch; + u16 F0PVSyncWidth; + u16 F0PVBackPorch; + u16 F0PVTotal; + u16 F1VFrontPorch; + u16 F1VSyncWidth; + u16 F1VBackPorch; + u16 F1VTotal; + u8 VSyncPolarity; +} XVidC_VideoTiming; + +/** + * 3D Sampling info structure. + */ +typedef struct { + XVidC_3DSamplingMethod Method; + XVidC_3DSamplingPosition Position; +} XVidC_3DSamplingInfo; + +/** + * 3D info structure. + */ +typedef struct { + XVidC_3DFormat Format; + XVidC_3DSamplingInfo Sampling; +} XVidC_3DInfo; + +/** + * Video stream structure. + */ +typedef struct { + XVidC_ColorFormat ColorFormatId; + XVidC_ColorDepth ColorDepth; + XVidC_PixelsPerClock PixPerClk; + XVidC_FrameRate FrameRate; + XVidC_AspectRatio AspectRatio; + u8 IsInterlaced; + u8 Is3D; + XVidC_3DInfo Info_3D; + XVidC_VideoMode VmId; + XVidC_VideoTiming Timing; +} XVidC_VideoStream; + +/** + * Video window structure. + */ +typedef struct { + u32 StartX; + u32 StartY; + u32 Width; + u32 Height; +} XVidC_VideoWindow; + +/** + * Video timing mode from the video timing table. + */ +typedef struct { + XVidC_VideoMode VmId; + const char Name[21]; + XVidC_FrameRate FrameRate; + XVidC_VideoTiming Timing; +} XVidC_VideoTimingMode; + +/** + * Callback type which represents a custom timer wait handler. This is only + * used for Microblaze since it doesn't have a native sleep function. To avoid + * dependency on a hardware timer, the default wait functionality is implemented + * using loop iterations; this isn't too accurate. Therefore a custom timer + * handler is used, the user may implement their own wait implementation. + * + * @param TimerPtr is a pointer to the timer instance. + * @param Delay is the duration (msec/usec) to be passed to the timer + * function. + * +*******************************************************************************/ +typedef void (*XVidC_DelayHandler)(void *TimerPtr, u32 Delay); + +/**************************** Function Prototypes *****************************/ + +u32 XVidC_RegisterCustomTimingModes(const XVidC_VideoTimingMode *CustomTable, + u16 NumElems); +void XVidC_UnregisterCustomTimingModes(void); +u32 XVidC_GetPixelClockHzByHVFr(u32 HTotal, u32 VTotal, u8 FrameRate); +u32 XVidC_GetPixelClockHzByVmId(XVidC_VideoMode VmId); +XVidC_VideoFormat XVidC_GetVideoFormat(XVidC_VideoMode VmId); +u8 XVidC_IsInterlaced(XVidC_VideoMode VmId); +const XVidC_VideoTimingMode* XVidC_GetVideoModeData(XVidC_VideoMode VmId); +const char *XVidC_GetVideoModeStr(XVidC_VideoMode VmId); +const char *XVidC_GetFrameRateStr(XVidC_VideoMode VmId); +const char *XVidC_GetColorFormatStr(XVidC_ColorFormat ColorFormatId); +XVidC_FrameRate XVidC_GetFrameRate(XVidC_VideoMode VmId); +const XVidC_VideoTiming* XVidC_GetTimingInfo(XVidC_VideoMode VmId); +void XVidC_ReportStreamInfo(const XVidC_VideoStream *Stream); +void XVidC_ReportTiming(const XVidC_VideoTiming *Timing, u8 IsInterlaced); +const char *XVidC_Get3DFormatStr(XVidC_3DFormat Format); +u32 XVidC_SetVideoStream(XVidC_VideoStream *VidStrmPtr, XVidC_VideoMode VmId, + XVidC_ColorFormat ColorFormat, XVidC_ColorDepth Bpc, + XVidC_PixelsPerClock Ppc); +u32 XVidC_Set3DVideoStream(XVidC_VideoStream *VidStrmPtr, XVidC_VideoMode VmId, + XVidC_ColorFormat ColorFormat, XVidC_ColorDepth Bpc, + XVidC_PixelsPerClock Ppc, XVidC_3DInfo *Info3DPtr); +XVidC_VideoMode XVidC_GetVideoModeId(u32 Width, u32 Height, u32 FrameRate, + u8 IsInterlaced); +XVidC_VideoMode XVidC_GetVideoModeIdExtensive(XVidC_VideoTiming *Timing, + u32 FrameRate, + u8 IsInterlaced, + u8 IsExtensive); +XVidC_VideoMode XVidC_GetVideoModeIdRb(u32 Width, u32 Height, u32 FrameRate, + u8 IsInterlaced, u8 RbN); +XVidC_VideoMode XVidC_GetVideoModeIdWBlanking(const XVidC_VideoTiming *Timing, + u32 FrameRate, u8 IsInterlaced); + +/******************* Macros (Inline Functions) Definitions ********************/ + +/*****************************************************************************/ +/** + * This macro check if video stream is 3D or 2D. + * + * @param VidStreamPtr is a pointer to the XVidC_VideoStream structure. + * + * @return 3D(1)/2D(0) + * + * @note C-style signature: + * u8 XDp_IsStream3D(XVidC_VideoStream *VidStreamPtr) + * + *****************************************************************************/ +#define XVidC_IsStream3D(VidStreamPtr) ((VidStreamPtr)->Is3D) + +/*************************** Variable Declarations ****************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* XVIDC_H_ */ +/** @} */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/video_common_v4_3/src/xvidc_cea861.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/video_common_v4_3/src/xvidc_cea861.h new file mode 100644 index 000000000..9e50b9d4b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/video_common_v4_3/src/xvidc_cea861.h @@ -0,0 +1,399 @@ +/* vim: set et fde fdm=syntax ft=c.doxygen ts=4 sts=4 sw=4 : */ +/* + * Copyright © 2010-2011 Saleem Abdulrasool . + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO + * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef xvidc_cea861_h +#define xvidc_cea861_h + +#define XVIDC_EDID_VERBOSITY 0 + +#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof(arr[0])) + +#define XVIDC_CEA861_NO_DTDS_PRESENT (0x04) + +#define HDMI_VSDB_EXTENSION_FLAGS_OFFSET (0x06) +#define HDMI_VSDB_MAX_TMDS_OFFSET (0x07) +#define HDMI_VSDB_LATENCY_FIELDS_OFFSET (0x08) + +static const u8 HDMI_OUI[] = { 0x00, 0x0C, 0x03 }; +static const u8 HDMI_OUI_HF[] = { 0xC4, 0x5D, 0xD8 }; + +enum xvidc_cea861_data_block_type { + XVIDC_CEA861_DATA_BLOCK_TYPE_RESERVED0, + XVIDC_CEA861_DATA_BLOCK_TYPE_AUDIO, + XVIDC_CEA861_DATA_BLOCK_TYPE_VIDEO, + XVIDC_CEA861_DATA_BLOCK_TYPE_VENDOR_SPECIFIC, + XVIDC_CEA861_DATA_BLOCK_TYPE_SPEAKER_ALLOCATION, + XVIDC_CEA861_DATA_BLOCK_TYPE_VESA_DTC, + XVIDC_CEA861_DATA_BLOCK_TYPE_RESERVED6, + XVIDC_CEA861_DATA_BLOCK_TYPE_EXTENDED, +}; + +enum xvidc_cea861_extended_tag_type_data_block { + XVIDC_CEA861_EXT_TAG_TYPE_VIDEO_CAPABILITY, + XVIDC_CEA861_EXT_TAG_TYPE_VENDOR_SPECIFIC, + XVIDC_CEA861_EXT_TAG_TYPE_VESA_DISPLAY_DEVICE, + XVIDC_CEA861_EXT_TAG_TYPE_VESA_VIDEO_TIMING_BLOCK_EXT, + XVIDC_CEA861_EXT_TAG_TYPE_RESERVED_FOR_HDMI_VIDEO_DATA_BLOCK, + XVIDC_CEA861_EXT_TAG_TYPE_COLORIMETRY, + XVIDC_CEA861_EXT_TAG_TYPE_HDR_STATIC_METADATA, + XVIDC_CEA861_EXT_TAG_TYPE_HDR_DYNAMIC_METADATA, + XVIDC_CEA861_EXT_TAG_TYPE_RESERVED2, + XVIDC_CEA861_EXT_TAG_TYPE_RESERVED3, + XVIDC_CEA861_EXT_TAG_TYPE_RESERVED4, + XVIDC_CEA861_EXT_TAG_TYPE_RESERVED5, + XVIDC_CEA861_EXT_TAG_TYPE_RESERVED6, + XVIDC_CEA861_EXT_TAG_TYPE_VIDEO_FRMT_PREFERENCE, + XVIDC_CEA861_EXT_TAG_TYPE_YCBCR420_VIDEO, + XVIDC_CEA861_EXT_TAG_TYPE_YCBCR420_CAPABILITY_MAP, + XVIDC_CEA861_EXT_TAG_TYPE_CEA_MISC_AUDIO_FIELDS, + XVIDC_CEA861_EXT_TAG_TYPE_VENDOR_SPECIFC_AUDIO, + XVIDC_CEA861_EXT_TAG_TYPE_HDMI_AUDIO, + XVIDC_CEA861_EXT_TAG_TYPE_ROOM_CONFIGURATION, + XVIDC_CEA861_EXT_TAG_TYPE_SPEAKER_LOCATION, + XVIDC_CEA861_EXT_TAG_TYPE_INFOFRAME = 32, +/* Can be extend to 255, refer table 46 cea data block tag codes cea-861-f */ +}; + +enum xvidc_cea861_audio_format { + XVIDC_CEA861_AUDIO_FORMAT_RESERVED, + XVIDC_CEA861_AUDIO_FORMAT_LPCM, + XVIDC_CEA861_AUDIO_FORMAT_AC_3, + XVIDC_CEA861_AUDIO_FORMAT_MPEG_1, + XVIDC_CEA861_AUDIO_FORMAT_MP3, + XVIDC_CEA861_AUDIO_FORMAT_MPEG2, + XVIDC_CEA861_AUDIO_FORMAT_AAC_LC, + XVIDC_CEA861_AUDIO_FORMAT_DTS, + XVIDC_CEA861_AUDIO_FORMAT_ATRAC, + XVIDC_CEA861_AUDIO_FORMAT_DSD, + XVIDC_CEA861_AUDIO_FORMAT_E_AC_3, + XVIDC_CEA861_AUDIO_FORMAT_DTS_HD, + XVIDC_CEA861_AUDIO_FORMAT_MLP, + XVIDC_CEA861_AUDIO_FORMAT_DST, + XVIDC_CEA861_AUDIO_FORMAT_WMA_PRO, + XVIDC_CEA861_AUDIO_FORMAT_EXTENDED, +}; + +struct __attribute__ (( packed )) xvidc_cea861_timing_block { + /* CEA Extension Header */ + u8 tag; + u8 revision; + u8 dtd_offset; + + /* Global Declarations */ + unsigned native_dtds : 4; + unsigned yuv_422_supported : 1; + unsigned yuv_444_supported : 1; + unsigned basic_audio_supported : 1; + unsigned underscan_supported : 1; + + u8 data[123]; + + u8 checksum; +}; + +struct __attribute__ (( packed )) xvidc_cea861_data_block_header { + unsigned length : 5; + unsigned tag : 3; +}; + +struct __attribute__ (( packed )) xvidc_cea861_short_video_descriptor { + unsigned video_identification_code : 7; + unsigned native : 1; +}; +#if XVIDC_EDID_VERBOSITY > 1 +struct __attribute__ (( packed )) xvidc_cea861_video_data_block { + struct xvidc_cea861_data_block_header header; + struct xvidc_cea861_short_video_descriptor svd[]; +}; +#endif +struct __attribute__ (( packed )) xvidc_cea861_short_audio_descriptor { + unsigned channels : 3; /* = value + 1 */ + unsigned audio_format : 4; + unsigned : 1; + + unsigned sample_rate_32_kHz : 1; + unsigned sample_rate_44_1_kHz : 1; + unsigned sample_rate_48_kHz : 1; + unsigned sample_rate_88_2_kHz : 1; + unsigned sample_rate_96_kHz : 1; + unsigned sample_rate_176_4_kHz : 1; + unsigned sample_rate_192_kHz : 1; + unsigned : 1; + + union { + struct __attribute__ (( packed )) { + unsigned bitrate_16_bit : 1; + unsigned bitrate_20_bit : 1; + unsigned bitrate_24_bit : 1; + unsigned : 5; + } lpcm; + + u8 maximum_bit_rate; /* formats 2-8; = value * 8 kHz */ + + u8 format_dependent; /* formats 9-13; */ + + struct __attribute__ (( packed )) { + unsigned profile : 3; + unsigned : 5; + } wma_pro; + + struct __attribute__ (( packed )) { + unsigned : 3; + unsigned code : 5; + } extension; + } flags; +}; +#if XVIDC_EDID_VERBOSITY > 1 +struct __attribute__ (( packed )) xvidc_cea861_audio_data_block { + struct xvidc_cea861_data_block_header header; + struct xvidc_cea861_short_audio_descriptor sad[]; +}; +#endif +#if XVIDC_EDID_VERBOSITY > 1 +struct __attribute__ (( packed )) xvidc_cea861_speaker_allocation { + unsigned front_left_right : 1; + unsigned front_lfe : 1; /* low frequency effects */ + unsigned front_center : 1; + unsigned rear_left_right : 1; + unsigned rear_center : 1; + unsigned front_left_right_center : 1; + unsigned rear_left_right_center : 1; + unsigned front_left_right_wide : 1; + + unsigned front_left_right_high : 1; + unsigned top_center : 1; + unsigned front_center_high : 1; + unsigned : 5; + + unsigned : 8; +}; +#endif +#if XVIDC_EDID_VERBOSITY > 1 +struct __attribute__ (( packed )) xvidc_cea861_speaker_allocation_data_block { + struct xvidc_cea861_data_block_header header; + struct xvidc_cea861_speaker_allocation payload; +}; +#endif +struct __attribute__ (( packed )) xvidc_cea861_vendor_specific_data_block { + struct xvidc_cea861_data_block_header header; + u8 ieee_registration[3]; + u8 data[30]; +}; + +struct __attribute__ (( packed )) xvidc_cea861_extended_data_block { + struct xvidc_cea861_data_block_header header; + u8 xvidc_cea861_extended_tag_codes; + u8 data[30]; +}; + +#if XVIDC_EDID_VERBOSITY > 1 +static const struct xvidc_cea861_timing { + const u16 hactive; + const u16 vactive; + const enum { + INTERLACED, + PROGRESSIVE, + } mode; + const u16 htotal; + const u16 hblank; + const u16 vtotal; + const double vblank; + const double hfreq; + const double vfreq; + const double pixclk; +} xvidc_cea861_timings[] = { + [ 1] = { 640, 480, PROGRESSIVE, 800, 160, 525, 45.0, 31.469, 59.940, 25.175 }, + [ 2] = { 720, 480, PROGRESSIVE, 858, 138, 525, 45.0, 31.469, 59.940, 27.000 }, + [ 3] = { 720, 480, PROGRESSIVE, 858, 138, 525, 45.0, 31.469, 59.940, 27.000 }, + [ 4] = { 1280, 720, PROGRESSIVE, 1650, 370, 750, 30.0, 45.000, 60.000, 74.250 }, + [ 5] = { 1920,1080, INTERLACED, 2200, 280, 1125, 22.5, 33.750, 60.000, 72.250 }, + [ 6] = { 1440, 480, INTERLACED, 1716, 276, 525, 22.5, 15.734, 59.940, 27.000 }, + [ 7] = { 1440, 480, INTERLACED, 1716, 276, 525, 22.5, 15.734, 59.940, 27.000 }, + [ 8] = { 1440, 240, PROGRESSIVE, 1716, 276, 262, 22.0, 15.734, 60.054, 27.000 }, + [ 9] = { 1440, 240, PROGRESSIVE, 1716, 276, 262, 22.0, 15.734, 59.826, 27.000 }, + [ 10] = { 2880, 480, INTERLACED, 3432, 552, 525, 22.5, 15.734, 59.940, 54.000 }, + [ 11] = { 2880, 480, INTERLACED, 3432, 552, 525, 22.5, 15.734, 59.940, 54.000 }, + [ 12] = { 2880, 240, PROGRESSIVE, 3432, 552, 262, 22.0, 15.734, 60.054, 54.000 }, + [ 13] = { 2880, 240, PROGRESSIVE, 3432, 552, 262, 22.0, 15.734, 59.826, 54.000 }, + [ 14] = { 1440, 480, PROGRESSIVE, 1716, 276, 525, 45.0, 31.469, 59.940, 54.000 }, + [ 15] = { 1440, 480, PROGRESSIVE, 1716, 276, 525, 45.0, 31.469, 59.940, 54.000 }, + [ 16] = { 1920, 1080, PROGRESSIVE, 2200, 280, 1125, 45.0, 67.500, 60.000, 148.500 }, + [ 17] = { 720, 576, PROGRESSIVE, 864, 144, 625, 49.0, 31.250, 50.000, 27.000 }, + [ 18] = { 720, 576, PROGRESSIVE, 864, 144, 625, 49.0, 31.250, 50.000, 27.000 }, + [ 19] = { 1280, 720, PROGRESSIVE, 1980, 700, 750, 30.0, 37.500, 50.000, 74.250 }, + [ 20] = { 1920, 1080, INTERLACED, 2640, 720, 1125, 22.5, 28.125, 50.000, 74.250 }, + [ 21] = { 1440, 576, INTERLACED, 1728, 288, 625, 24.5, 15.625, 50.000, 27.000 }, + [ 22] = { 1440, 576, INTERLACED, 1728, 288, 625, 24.5, 15.625, 50.000, 27.000 }, + [ 23] = { 1440, 288, PROGRESSIVE, 1728, 288, 312, 24.0, 15.625, 50.080, 27.000 }, + [ 24] = { 1440, 288, PROGRESSIVE, 1728, 288, 313, 25.0, 15.625, 49.920, 27.000 }, + [ 25] = { 2880, 576, INTERLACED, 3456, 576, 625, 24.5, 15.625, 50.000, 54.000 }, + [ 26] = { 2880, 576, INTERLACED, 3456, 576, 625, 24.5, 15.625, 50.000, 54.000 }, + [ 27] = { 2880, 288, PROGRESSIVE, 3456, 576, 312, 24.0, 15.625, 50.080, 54.000 }, + [ 28] = { 2880, 288, PROGRESSIVE, 3456, 576, 313, 25.0, 15.625, 49.920, 54.000 }, + [ 29] = { 1440, 576, PROGRESSIVE, 1728, 288, 625, 49.0, 31.250, 50.000, 54.000 }, + [ 30] = { 1440, 576, PROGRESSIVE, 1728, 288, 625, 49.0, 31.250, 50.000, 54.000 }, + [ 31] = { 1920, 1080, PROGRESSIVE, 2640, 720, 1125, 45.0, 56.250, 50.000, 148.500 }, + [ 32] = { 1920, 1080, PROGRESSIVE, 2750, 830, 1125, 45.0, 27.000, 24.000, 74.250 }, + [ 33] = { 1920, 1080, PROGRESSIVE, 2640, 720, 1125, 45.0, 28.125, 25.000, 74.250 }, + [ 34] = { 1920, 1080, PROGRESSIVE, 2200, 280, 1125, 45.0, 33.750, 30.000, 74.250 }, + [ 35] = { 2880, 480, PROGRESSIVE, 3432, 552, 525, 45.0, 31.469, 59.940, 108.500 }, + [ 36] = { 2880, 480, PROGRESSIVE, 3432, 552, 525, 45.0, 31.469, 59.940, 108.500 }, + [ 37] = { 2880, 576, PROGRESSIVE, 3456, 576, 625, 49.0, 31.250, 50.000, 108.000 }, + [ 38] = { 2880, 576, PROGRESSIVE, 3456, 576, 625, 49.0, 31.250, 50.000, 108.000 }, + [ 39] = { 1920, 1080, INTERLACED, 2304, 384, 1250, 85.0, 31.250, 50.000, 72.000 }, + [ 40] = { 1920, 1080, INTERLACED, 2640, 720, 1125, 22.5, 56.250, 100.000, 148.500 }, + [ 41] = { 1280, 720, PROGRESSIVE, 1980, 700, 750, 30.0, 75.000, 100.000, 148.500 }, + [ 42] = { 720, 576, PROGRESSIVE, 864, 144, 625, 49.0, 62.500, 100.000, 54.000 }, + [ 43] = { 720, 576, PROGRESSIVE, 864, 144, 625, 49.0, 62.500, 100.000, 54.000 }, + [ 44] = { 1440, 576, INTERLACED, 1728, 288, 625, 24.5, 31.250, 100.000, 54.000 }, + [ 45] = { 1440, 576, INTERLACED, 1728, 288, 625, 24.5, 31.250, 100.000, 54.000 }, + [ 46] = { 1920, 1080, INTERLACED, 2200, 280, 1125, 22.5, 67.500, 120.000, 148.500 }, + [ 47] = { 1280, 720, PROGRESSIVE, 1650, 370, 750, 30.0, 90.000, 120.000, 148.500 }, + [ 48] = { 720, 480, PROGRESSIVE, 858, 138, 525, 45.0, 62.937, 119.880, 54.000 }, + [ 49] = { 720, 480, PROGRESSIVE, 858, 138, 525, 45.0, 62.937, 119.880, 54.000 }, + [ 50] = { 1440, 480, INTERLACED, 1716, 276, 525, 22.5, 31.469, 119.880, 54.000 }, + [ 51] = { 1440, 480, INTERLACED, 1716, 276, 525, 22.5, 31.469, 119.880, 54.000 }, + [ 52] = { 720, 576, PROGRESSIVE, 864, 144, 625, 49.0, 125.000, 200.000, 108.000 }, + [ 53] = { 720, 576, PROGRESSIVE, 864, 144, 625, 49.0, 125.000, 200.000, 108.000 }, + [ 54] = { 1440, 576, INTERLACED, 1728, 288, 625, 24.5, 62.500, 200.000, 108.000 }, + [ 55] = { 1440, 576, INTERLACED, 1728, 288, 625, 24.5, 62.500, 200.000, 108.000 }, + [ 56] = { 720, 480, PROGRESSIVE, 858, 138, 525, 45.0, 125.874, 239.760, 108.000 }, + [ 57] = { 720, 480, PROGRESSIVE, 858, 138, 525, 45.0, 125.874, 239.760, 108.000 }, + [ 58] = { 1440, 480, INTERLACED, 1716, 276, 525, 22.5, 62.937, 239.760, 108.000 }, + [ 59] = { 1440, 480, INTERLACED, 1716, 276, 525, 22.5, 62.937, 239.760, 108.000 }, + [60 ] = {1280, 720 , PROGRESSIVE, 3300, 2020, 750 , 30 , 18 , 24.0003, 59.4 }, + [61 ] = {1280, 720 , PROGRESSIVE, 3960, 2680, 750 , 30 , 18.75 , 25 , 74.25 }, + [62 ] = {1280, 720 , PROGRESSIVE, 3300, 2020, 750 , 30 , 22.5 , 30.0003, 74.25 }, + [63 ] = {1920, 1080, PROGRESSIVE, 2200, 280 , 1125, 45 , 135 , 120.003, 297 }, + [64 ] = {1920, 1080, PROGRESSIVE, 2640, 720 , 1125, 45 , 112.5 , 100 , 297 }, + [65 ] = {1280, 720 , PROGRESSIVE, 3300, 2020, 750 , 30 , 18 , 24.0003, 59.4 }, + [66 ] = {1280, 720 , PROGRESSIVE, 3960, 2680, 750 , 30 , 18.75 , 25 , 74.25 }, + [67 ] = {1280, 720 , PROGRESSIVE, 3300, 2020, 750 , 30 , 22.5 , 30.0003, 74.25 }, + [68 ] = {1280, 720 , PROGRESSIVE, 1980, 700 , 750 , 30 , 37.5 , 50 , 74.25 }, + [69 ] = {1280, 720 , PROGRESSIVE, 1650, 370 , 750 , 30 , 45 , 60.0003, 74.25 }, + [70 ] = {1280, 720 , PROGRESSIVE, 1980, 700 , 750 , 30 , 75 , 100 , 148.5 }, + [71 ] = {1280, 720 , PROGRESSIVE, 1650, 370 , 750 , 30 , 90 , 120.003, 148.5 }, + [72 ] = {1920, 1080, PROGRESSIVE, 2750, 830 , 1125, 45 , 27 , 24.0003, 74.25 }, + [73 ] = {1920, 1080, PROGRESSIVE, 2640, 720 , 1125, 45 , 28.125 , 25 , 74.25 }, + [74 ] = {1920, 1080, PROGRESSIVE, 2200, 280 , 1125, 45 , 33.75 , 30.0003, 74.25 }, + [75 ] = {1920, 1080, PROGRESSIVE, 2640, 720 , 1125, 45 , 56.25 , 50 , 148.5 }, + [76 ] = {1920, 1080, PROGRESSIVE, 2200, 280 , 1125, 45 , 67.5 , 60.0003, 148.5 }, + [77 ] = {1920, 1080, PROGRESSIVE, 2640, 720 , 1125, 45 , 112.5 , 100 , 297 }, + [78 ] = {1920, 1080, PROGRESSIVE, 2200, 280 , 1125, 45 , 135 , 120.003, 297 }, + [79 ] = {1680, 720 , PROGRESSIVE, 3300, 1620, 750 , 30 , 18 , 24.0003, 59.4 }, + [80 ] = {1680, 720 , PROGRESSIVE, 3168, 1488, 750 , 30 , 18.75 , 25 , 59.4 }, + [81 ] = {1680, 720 , PROGRESSIVE, 2640, 960 , 750 , 30 , 22.5 , 30.0003, 59.4 }, + [82 ] = {1680, 720 , PROGRESSIVE, 2200, 520 , 750 , 30 , 37.5 , 50 , 82.5 }, + [83 ] = {1680, 720 , PROGRESSIVE, 2200, 520 , 750 , 30 , 45 , 60.0003, 99 }, + [84 ] = {1680, 720 , PROGRESSIVE, 2000, 320 , 825 , 105 , 82.5 , 100 , 165 }, + [85 ] = {1680, 720 , PROGRESSIVE, 2000, 320 , 825 , 105 , 99 , 120.003, 198 }, + [86 ] = {2560, 1080, PROGRESSIVE, 3750, 1190, 1100, 20 , 26.4 , 24.0003, 99 }, + [87 ] = {2560, 1080, PROGRESSIVE, 3200, 640 , 1125, 45 , 28.125 , 25 , 90 }, + [88 ] = {2560, 1080, PROGRESSIVE, 3520, 960 , 1125, 45 , 33.75 , 30.0003, 118.8 }, + [89 ] = {2560, 1080, PROGRESSIVE, 3300, 740 , 1125, 45 , 56.25 , 50 , 185.625 }, + [90 ] = {2560, 1080, PROGRESSIVE, 3000, 440 , 1100, 20 , 66 , 60.0003, 198 }, + [91 ] = {2560, 1080, PROGRESSIVE, 2970, 410 , 1250, 170 , 125 , 100 , 371.25 }, + [92 ] = {2560, 1080, PROGRESSIVE, 3300, 740 , 1250, 170 , 150 , 120.003, 495 }, + [93 ] = {3840, 2160, PROGRESSIVE, 5500, 1660, 2250, 90 , 54 , 24.0003, 297 }, + [94 ] = {3840, 2160, PROGRESSIVE, 5280, 1440, 2250, 90 , 56.25 , 25 , 297 }, + [95 ] = {3840, 2160, PROGRESSIVE, 4400, 560 , 2250, 90 , 67.5 , 30.0003, 297 }, + [96 ] = {3840, 2160, PROGRESSIVE, 5280, 1440, 2250, 90 , 112.5 , 50 , 594 }, + [97 ] = {3840, 2160, PROGRESSIVE, 4400, 560 , 2250, 90 , 135 , 60.0003, 594 }, + [98 ] = {4096, 2160, PROGRESSIVE, 5500, 1404, 2250, 90 , 54 , 24.0003, 297 }, + [99 ] = {4096, 2160, PROGRESSIVE, 5280, 1184, 2250, 90 , 56.25 , 25 , 297 }, + [100] = {4096, 2160, PROGRESSIVE, 4400, 304 , 2250, 90 , 67.5 , 30.0003, 297 }, + [101] = {4096, 2160, PROGRESSIVE, 5280, 1184, 2250, 90 , 112.5 , 50 , 594 }, + [102] = {4096, 2160, PROGRESSIVE, 4400, 304 , 2250, 90 , 135 , 60.0003, 594 }, + [103] = {3840, 2160, PROGRESSIVE, 5500, 1660, 2250, 90 , 54 , 24.0003, 297 }, + [104] = {3840, 2160, PROGRESSIVE, 5280, 1440, 2250, 90 , 56.25 , 25 , 297 }, + [105] = {3840, 2160, PROGRESSIVE, 4400, 560 , 2250, 90 , 67.5 , 30.0003, 297 }, + [106] = {3840, 2160, PROGRESSIVE, 5280, 1440, 2250, 90 , 112.5 , 50 , 594 }, + [107] = {3840, 2160, PROGRESSIVE, 4400, 560 , 2250, 90 , 135 , 60.0003, 594 }, +}; +#endif + +struct __attribute__ (( packed )) xvidc_cea861_hdmi_vendor_specific_data_block { + struct xvidc_cea861_data_block_header header; + + u8 ieee_registration_id[3]; /* LSB */ + + unsigned port_configuration_b : 4; + unsigned port_configuration_a : 4; + unsigned port_configuration_d : 4; + unsigned port_configuration_c : 4; + + /* extension fields */ + unsigned dvi_dual_link : 1; + unsigned : 2; + unsigned yuv_444_supported : 1; + unsigned colour_depth_30_bit : 1; + unsigned colour_depth_36_bit : 1; + unsigned colour_depth_48_bit : 1; + unsigned audio_info_frame : 1; + + u8 max_tmds_clock; /* = value * 5 */ + + unsigned : 6; + unsigned interlaced_latency_fields : 1; + unsigned latency_fields : 1; + + u8 video_latency; /* = (value - 1) * 2 */ + u8 audio_latency; /* = (value - 1) * 2 */ + u8 interlaced_video_latency; + u8 interlaced_audio_latency; + + u8 reserved[]; +}; + +struct __attribute__ (( packed )) xvidc_cea861_hdmi_hf_vendor_specific_data_block { + struct xvidc_cea861_data_block_header header; + + u8 ieee_registration_id[3]; /* LSB */ + + u8 version; + u8 max_tmds_char_rate; + + unsigned osd_disparity_3d : 1; + unsigned dual_view_3d : 1; + unsigned independent_view_3d : 1; + unsigned lte_340mcsc_scramble : 1; + + unsigned : 2; + + unsigned rr_capable : 1; + unsigned scdc_present : 1; + unsigned dc_30bit_yuv420 : 1; + unsigned dc_36bit_yuv420 : 1; + unsigned dc_48bit_yuv420 : 1; + + u8 reserved[]; +}; + +#endif diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/video_common_v4_3/src/xvidc_edid.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/video_common_v4_3/src/xvidc_edid.c new file mode 100644 index 000000000..585f7b8a3 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/video_common_v4_3/src/xvidc_edid.c @@ -0,0 +1,707 @@ +/******************************************************************************* + * + * Copyright (C) 2017 Xilinx, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * Use of the Software is limited solely to applications: + * (a) running on a Xilinx device, or + * (b) that interact with a Xilinx device through a bus or interconnect. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of the Xilinx shall not be used + * in advertising or otherwise to promote the sale, use or other dealings in + * this Software without prior written authorization from Xilinx. + * +*******************************************************************************/ +/******************************************************************************/ +/** + * + * @file xvidc_edid.c + * @addtogroup video_common_v4_2 + * @{ + * + * Contains function definitions related to the Extended Display Identification + * Data (EDID) structure which is present in all monitors. All content in this + * file is agnostic of communication interface protocol. + * + * @note None. + * + * 
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -----------------------------------------------
+ * 1.0   als  11/09/14 Initial release.
+ * 2.2   als  02/01/16 Functions with pointer arguments that don't modify
+ *                     contents now const.
+ * 4.0   aad  10/26/16 Added API for colormetry which returns fixed point
+ *		       in Q0.10 format instead of float.
+ *
+ * +*******************************************************************************/ + +/******************************* Include Files ********************************/ + +#include "xvidc_edid.h" + +/**************************** Function Prototypes *****************************/ + +static u32 XVidC_EdidIsVideoTimingSupportedPreferredTiming(const u8 *EdidRaw, + const XVidC_VideoTimingMode *VtMode); +static u32 XVidC_EdidIsVideoTimingSupportedEstablishedTimings(const u8 *EdidRaw, + const XVidC_VideoTimingMode *VtMode); +static u32 XVidC_EdidIsVideoTimingSupportedStandardTimings(const u8 *EdidRaw, + const XVidC_VideoTimingMode *VtMode); +static int XVidC_CalculatePower(u8 Base, u8 Power); +static int XVidC_CalculateBinaryFraction_QFormat(u16 Val, u8 DecPtIndex); + +/**************************** Function Definitions ****************************/ + +/******************************************************************************/ +/** + * Get the manufacturer name as specified in the vendor and product ID field of + * the supplied base Extended Display Identification Data (EDID). + * + * @param EdidRaw is the supplied base EDID to retrieve the manufacturer + * name from. + * @param ManName is the string that will be modified to hold the + * retrieved manufacturer name. + * + * @return None. + * + * @note The ManName argument is modified with the manufacturer name. + * +*******************************************************************************/ +void XVidC_EdidGetManName(const u8 *EdidRaw, char ManName[4]) +{ + ManName[0] = 0x40 + ((EdidRaw[XVIDC_EDID_VPI_ID_MAN_NAME0] & + XVIDC_EDID_VPI_ID_MAN_NAME0_CHAR0_MASK) >> + XVIDC_EDID_VPI_ID_MAN_NAME0_CHAR0_SHIFT); + ManName[1] = 0x40 + (((EdidRaw[XVIDC_EDID_VPI_ID_MAN_NAME0] & + XVIDC_EDID_VPI_ID_MAN_NAME0_CHAR1_MASK) << + XVIDC_EDID_VPI_ID_MAN_NAME0_CHAR1_POS) | + (EdidRaw[XVIDC_EDID_VPI_ID_MAN_NAME1] >> + XVIDC_EDID_VPI_ID_MAN_NAME1_CHAR1_SHIFT)); + ManName[2] = 0x40 + (EdidRaw[XVIDC_EDID_VPI_ID_MAN_NAME1] & + XVIDC_EDID_VPI_ID_MAN_NAME1_CHAR2_MASK); + ManName[3] = '\0'; +} + +/******************************************************************************/ +/** + * Get the color bit depth (bits per primary color) as specified in the basic + * display parameters and features, video input definition field of the supplied + * base Extended Display Identification Data (EDID). + * + * @param EdidRaw is the supplied base EDID to retrieve color depth + * information from. + * + * @return The number of bits per primary color as specified by the + * supplied base EDID. + * + * @note None. + * +*******************************************************************************/ +XVidC_ColorDepth XVidC_EdidGetColorDepth(const u8 *EdidRaw) +{ + XVidC_ColorDepth Bpc; + + switch (((EdidRaw[XVIDC_EDID_BDISP_VID] & + XVIDC_EDID_BDISP_VID_DIG_BPC_MASK) >> + XVIDC_EDID_BDISP_VID_DIG_BPC_SHIFT)) { + case XVIDC_EDID_BDISP_VID_DIG_BPC_6: + Bpc = XVIDC_BPC_6; + break; + + case XVIDC_EDID_BDISP_VID_DIG_BPC_8: + Bpc = XVIDC_BPC_8; + break; + + case XVIDC_EDID_BDISP_VID_DIG_BPC_10: + Bpc = XVIDC_BPC_10; + break; + + case XVIDC_EDID_BDISP_VID_DIG_BPC_12: + Bpc = XVIDC_BPC_12; + break; + + case XVIDC_EDID_BDISP_VID_DIG_BPC_14: + Bpc = XVIDC_BPC_14; + break; + + case XVIDC_EDID_BDISP_VID_DIG_BPC_16: + Bpc = XVIDC_BPC_16; + break; + + default: + Bpc = XVIDC_BPC_UNKNOWN; + break; + } + + return Bpc; +} + +/******************************************************************************/ +/** + * Calculates the x chromaticity coordinate for red by converting a 10 bit + * binary fraction representation from the supplied base Extended Display + * Identification Data (EDID) to a integer in Q0.10 Format. To convert back + * to float divide the fixed point value by 2^10. + * + * @param EdidRaw is the supplied base EDID to retrieve chromaticity + * information from. + * + * @return The x chromatacity coordinate for red. + * + * @note All values will be accurate to +/-0.0005. + * +*******************************************************************************/ +int XVidC_EdidGetCcRedX(const u8 *EdidRaw) +{ + return XVidC_CalculateBinaryFraction_QFormat( + (EdidRaw[XVIDC_EDID_CC_REDX_HIGH] << + XVIDC_EDID_CC_HIGH_SHIFT) | (EdidRaw[XVIDC_EDID_CC_RG_LOW] >> + XVIDC_EDID_CC_RBX_LOW_SHIFT), 10); +} + +/******************************************************************************/ +/** + * Calculates the y chromaticity coordinate for red by converting a 10 bit + * binary fraction representation from the supplied base Extended Display + * Identification Data (EDID) to a integer in Q0.10 Format. To convert back + * to float divide the fixed point value by 2^10. + * + * @param EdidRaw is the supplied base EDID to retrieve chromaticity + * information from. + * + * @return The y chromatacity coordinate for red. + * + * @note All values will be accurate to +/-0.0005. + * +*******************************************************************************/ +int XVidC_EdidGetCcRedY(const u8 *EdidRaw) +{ + return XVidC_CalculateBinaryFraction_QFormat( + (EdidRaw[XVIDC_EDID_CC_REDY_HIGH] << + XVIDC_EDID_CC_HIGH_SHIFT) | ((EdidRaw[XVIDC_EDID_CC_RG_LOW] & + XVIDC_EDID_CC_RBY_LOW_MASK) >> + XVIDC_EDID_CC_RBY_LOW_SHIFT), 10); +} + +/******************************************************************************/ +/** + * Calculates the x chromaticity coordinate for green by converting a 10 bit + * binary fraction representation from the supplied base Extended Display + * Identification Data (EDID) to a integer in Q0.10 Format. To convert back + * to float divide the fixed point value by 2^10. + * + * @param EdidRaw is the supplied base EDID to retrieve chromaticity + * information from. + * + * @return The x chromatacity coordinate for green. + * + * @note All values will be accurate to +/-0.0005. + * +*******************************************************************************/ +int XVidC_EdidGetCcGreenX(const u8 *EdidRaw) +{ + return XVidC_CalculateBinaryFraction_QFormat( + (EdidRaw[XVIDC_EDID_CC_GREENX_HIGH] << + XVIDC_EDID_CC_HIGH_SHIFT) | ((EdidRaw[XVIDC_EDID_CC_RG_LOW] & + XVIDC_EDID_CC_GWX_LOW_MASK) >> + XVIDC_EDID_CC_GWX_LOW_SHIFT), 10); +} + +/******************************************************************************/ +/** + * Calculates the y chromaticity coordinate for green by converting a 10 bit + * binary fraction representation from the supplied base Extended Display + * Identification Data (EDID) to a integer in Q0.10 Format. To convert back + * to float divide the fixed point value by 2^10. + * + * @param EdidRaw is the supplied base EDID to retrieve chromaticity + * information from. + * + * @return The y chromatacity coordinate for green. + * + * @note All values will be accurate to +/-0.0005. + * +*******************************************************************************/ +int XVidC_EdidGetCcGreenY(const u8 *EdidRaw) +{ + return XVidC_CalculateBinaryFraction_QFormat( + (EdidRaw[XVIDC_EDID_CC_GREENY_HIGH] << + XVIDC_EDID_CC_HIGH_SHIFT) | (EdidRaw[XVIDC_EDID_CC_RG_LOW] & + XVIDC_EDID_CC_GWY_LOW_MASK), 10); +} + +/******************************************************************************/ +/** + * Calculates the x chromaticity coordinate for blue by converting a 10 bit + * binary fraction representation from the supplied base Extended Display + * Identification Data (EDID) to a integer in Q0.10 Format. To convert back + * to float divide the fixed point value by 2^10. + * + * @param EdidRaw is the supplied base EDID to retrieve chromaticity + * information from. + * + * @return The x chromatacity coordinate for blue. + * + * @note All values will be accurate to +/-0.0005. + * +*******************************************************************************/ +int XVidC_EdidGetCcBlueX(const u8 *EdidRaw) +{ + return XVidC_CalculateBinaryFraction_QFormat( + (EdidRaw[XVIDC_EDID_CC_BLUEX_HIGH] << + XVIDC_EDID_CC_HIGH_SHIFT) | (EdidRaw[XVIDC_EDID_CC_BW_LOW] >> + XVIDC_EDID_CC_RBX_LOW_SHIFT), 10); +} + +/******************************************************************************/ +/** + * Calculates the y chromaticity coordinate for blue by converting a 10 bit + * binary fraction representation from the supplied base Extended Display + * Identification Data (EDID) to a integer in Q0.10 Format. To convert back + * to float divide the fixed point value by 2^10. + * + * @param EdidRaw is the supplied base EDID to retrieve chromaticity + * information from. + * + * @return The y chromatacity coordinate for blue. + * + * @note All values will be accurate to +/-0.0005. + * +*******************************************************************************/ +int XVidC_EdidGetCcBlueY(const u8 *EdidRaw) +{ + return XVidC_CalculateBinaryFraction_QFormat( + (EdidRaw[XVIDC_EDID_CC_BLUEY_HIGH] << + XVIDC_EDID_CC_HIGH_SHIFT) | ((EdidRaw[XVIDC_EDID_CC_BW_LOW] & + XVIDC_EDID_CC_RBY_LOW_MASK) >> + XVIDC_EDID_CC_RBY_LOW_SHIFT), 10); +} + +/******************************************************************************/ +/** + * Calculates the x chromaticity coordinate for white by converting a 10 bit + * binary fraction representation from the supplied base Extended Display + * Identification Data (EDID) to a integer in Q0.10 Format. To convert back + * to float divide the fixed point value by 2^10. + * + * @param EdidRaw is the supplied base EDID to retrieve chromaticity + * information from. + * + * @return The x chromatacity coordinate for white. + * + * @note All values will be accurate to +/-0.0005. + * +*******************************************************************************/ +int XVidC_EdidGetCcWhiteX(const u8 *EdidRaw) +{ + return XVidC_CalculateBinaryFraction_QFormat( + (EdidRaw[XVIDC_EDID_CC_WHITEX_HIGH] << + XVIDC_EDID_CC_HIGH_SHIFT) | ((EdidRaw[XVIDC_EDID_CC_BW_LOW] & + XVIDC_EDID_CC_GWX_LOW_MASK) >> XVIDC_EDID_CC_GWX_LOW_SHIFT), 10); +} + +/******************************************************************************/ +/** + * Calculates the y chromaticity coordinate for white by converting a 10 bit + * binary fraction representation from the supplied base Extended Display + * Identification Data (EDID) to an integer in Q0.10 Format. To convert back + * to float divide the fixed point value by 2^10. + * + * @param EdidRaw is the supplied base EDID to retrieve chromaticity + * information from. + * + * @return The y chromatacity coordinate for white. + * + * @note All values will be accurate to +/-0.0005. + * +*******************************************************************************/ +int XVidC_EdidGetCcWhiteY(const u8 *EdidRaw) +{ + return XVidC_CalculateBinaryFraction_QFormat( + (EdidRaw[XVIDC_EDID_CC_WHITEY_HIGH] << + XVIDC_EDID_CC_HIGH_SHIFT) | (EdidRaw[XVIDC_EDID_CC_BW_LOW] & + XVIDC_EDID_CC_GWY_LOW_MASK), 10); +} + +/******************************************************************************/ +/** + * Retrieves the active vertical resolution from the standard timings field of + * the supplied base Extended Display Identification Data (EDID). + * + * @param EdidRaw is the supplied base EDID to check the timing against. + * @param StdTimingsNum specifies which one of the standard timings to + * retrieve from the standard timings field. + * + * @return The vertical active resolution of the specified standard timing + * from the supplied base EDID. + * + * @note StdTimingsNum is an index 1-8. + * +*******************************************************************************/ +u16 XVidC_EdidGetStdTimingsV(const u8 *EdidRaw, u8 StdTimingsNum) +{ + u16 V; + + switch (XVidC_EdidGetStdTimingsAr(EdidRaw, StdTimingsNum)) { + case XVIDC_EDID_STD_TIMINGS_AR_16_10: + V = (10 * XVidC_EdidGetStdTimingsH(EdidRaw, + StdTimingsNum)) / 16; + break; + + case XVIDC_EDID_STD_TIMINGS_AR_4_3: + V = (3 * XVidC_EdidGetStdTimingsH(EdidRaw, + StdTimingsNum)) / 4; + break; + + case XVIDC_EDID_STD_TIMINGS_AR_5_4: + V = (4 * XVidC_EdidGetStdTimingsH(EdidRaw, + StdTimingsNum)) / 5; + break; + + case XVIDC_EDID_STD_TIMINGS_AR_16_9: + V = (9 * XVidC_EdidGetStdTimingsH(EdidRaw, + StdTimingsNum)) / 16; + break; + default: + V = 0; + break; + } + + return V; +} + +/******************************************************************************/ +/** + * Checks whether or not a specified video timing mode is supported as specified + * in the supplied base Extended Display Identification Data (EDID). The + * preferred timing, established timings (I, II, II), and the standard timings + * fields are checked for support. + * + * @param EdidRaw is the supplied base EDID to check the timing against. + * @param VtMode is the video timing mode to check for support. + * + * @return + * - XST_SUCCESS if the video timing mode is supported as specified + * in the supplied base EDID. + * - XST_FAILURE otherwise. + * + * @note None. + * +*******************************************************************************/ +u32 XVidC_EdidIsVideoTimingSupported(const u8 *EdidRaw, + const XVidC_VideoTimingMode *VtMode) +{ + u32 Status; + + /* Check if the video mode is the preferred timing. */ + Status = XVidC_EdidIsVideoTimingSupportedPreferredTiming(EdidRaw, + VtMode); + if (Status == XST_SUCCESS) { + return Status; + } + + /* Check established timings I, II, and III. */ + Status = XVidC_EdidIsVideoTimingSupportedEstablishedTimings(EdidRaw, + VtMode); + if (Status == XST_SUCCESS) { + return Status; + } + + /* Check in standard timings support. */ + Status = XVidC_EdidIsVideoTimingSupportedStandardTimings(EdidRaw, + VtMode); + + return Status; +} + +/******************************************************************************/ +/** + * Checks whether or not a specified video timing mode is the preferred timing + * of the supplied base Extended Display Identification Data (EDID). + * + * @param EdidRaw is the supplied base EDID to check the timing against. + * @param VtMode is the video timing mode to check for support. + * + * @return + * - XST_SUCCESS if the video timing mode is the preferred timing + * as specified in the base EDID. + * - XST_FAILURE otherwise. + * + * @note None. + * +*******************************************************************************/ +static u32 XVidC_EdidIsVideoTimingSupportedPreferredTiming(const u8 *EdidRaw, + const XVidC_VideoTimingMode *VtMode) +{ + const u8 *Ptm; + + Ptm = &EdidRaw[XVIDC_EDID_PTM]; + + u32 HActive = (((Ptm[XVIDC_EDID_DTD_PTM_HRES_HBLANK_U4] & + XVIDC_EDID_DTD_PTM_XRES_XBLANK_U4_XRES_MASK) >> + XVIDC_EDID_DTD_PTM_XRES_XBLANK_U4_XRES_SHIFT) << 8) | + Ptm[XVIDC_EDID_DTD_PTM_HRES_LSB]; + + u32 VActive = (((Ptm[XVIDC_EDID_DTD_PTM_VRES_VBLANK_U4] & + XVIDC_EDID_DTD_PTM_XRES_XBLANK_U4_XRES_MASK) >> + XVIDC_EDID_DTD_PTM_XRES_XBLANK_U4_XRES_SHIFT) << 8) | + Ptm[XVIDC_EDID_DTD_PTM_VRES_LSB]; + + if (VtMode->Timing.F1VTotal != XVidC_EdidIsDtdPtmInterlaced(EdidRaw)) { + return (XST_FAILURE); + } + else if ((VtMode->Timing.HActive == HActive) && + (VtMode->Timing.VActive == VActive)) { + return (XST_SUCCESS); + } + + return XST_FAILURE; +} + +/******************************************************************************/ +/** + * Checks whether or not a specified video timing mode is supported in the + * established timings field of the supplied base Extended Display + * Identification Data (EDID). + * + * @param EdidRaw is the supplied base EDID to check the timing against. + * @param VtMode is the video timing mode to check for support. + * + * @return + * - XST_SUCCESS if the video timing mode is supported in the + * base EDID's established timings field. + * - XST_FAILURE otherwise. + * + * @note None. + * +*******************************************************************************/ +static u32 XVidC_EdidIsVideoTimingSupportedEstablishedTimings(const u8 *EdidRaw, + const XVidC_VideoTimingMode *VtMode) +{ + u32 Status = XST_FAILURE; + + /* Check established timings I, II, and III. */ + if ((VtMode->Timing.HActive == 800) && + (VtMode->Timing.VActive == 640) && + (VtMode->FrameRate == XVIDC_FR_56HZ) && + XVidC_EdidSuppEstTimings800x600_56(EdidRaw)) { + Status = XST_SUCCESS; + } + else if ((VtMode->Timing.HActive == 640) && + (VtMode->Timing.VActive == 480) && + (VtMode->FrameRate == XVIDC_FR_60HZ) && + XVidC_EdidSuppEstTimings640x480_60(EdidRaw)) { + Status = XST_SUCCESS; + } + else if ((VtMode->Timing.HActive == 800) && + (VtMode->Timing.VActive == 600) && + (VtMode->FrameRate == XVIDC_FR_60HZ) && + XVidC_EdidSuppEstTimings800x600_60(EdidRaw)) { + Status = XST_SUCCESS; + } + else if ((VtMode->Timing.HActive == 1024) && + (VtMode->Timing.VActive == 768) && + (VtMode->FrameRate == XVIDC_FR_60HZ) && + XVidC_EdidSuppEstTimings1024x768_60(EdidRaw)) { + Status = XST_SUCCESS; + } + else if ((VtMode->Timing.HActive == 640) && + (VtMode->Timing.VActive == 480) && + (VtMode->FrameRate == XVIDC_FR_67HZ) && + XVidC_EdidSuppEstTimings640x480_67(EdidRaw)) { + Status = XST_SUCCESS; + } + else if ((VtMode->Timing.HActive == 720) && + (VtMode->Timing.VActive == 400) && + (VtMode->FrameRate == XVIDC_FR_70HZ) && + XVidC_EdidSuppEstTimings720x400_70(EdidRaw)) { + Status = XST_SUCCESS; + } + else if ((VtMode->Timing.HActive == 1024) && + (VtMode->Timing.VActive == 768) && + (VtMode->FrameRate == XVIDC_FR_70HZ) && + XVidC_EdidSuppEstTimings1024x768_70(EdidRaw)) { + Status = XST_SUCCESS; + } + else if ((VtMode->Timing.HActive == 640) && + (VtMode->Timing.VActive == 480) && + (VtMode->FrameRate == XVIDC_FR_72HZ) && + XVidC_EdidSuppEstTimings640x480_72(EdidRaw)) { + Status = XST_SUCCESS; + } + else if ((VtMode->Timing.HActive == 800) && + (VtMode->Timing.VActive == 600) && + (VtMode->FrameRate == XVIDC_FR_72HZ) && + XVidC_EdidSuppEstTimings800x600_72(EdidRaw)) { + Status = XST_SUCCESS; + } + else if ((VtMode->Timing.HActive == 640) && + (VtMode->Timing.VActive == 480) && + (VtMode->FrameRate == XVIDC_FR_75HZ) && + XVidC_EdidSuppEstTimings640x480_75(EdidRaw)) { + Status = XST_SUCCESS; + } + else if ((VtMode->Timing.HActive == 800) && + (VtMode->Timing.VActive == 600) && + (VtMode->FrameRate == XVIDC_FR_75HZ) && + XVidC_EdidSuppEstTimings800x600_75(EdidRaw)) { + Status = XST_SUCCESS; + } + else if ((VtMode->Timing.HActive == 832) && + (VtMode->Timing.VActive == 624) && + (VtMode->FrameRate == XVIDC_FR_75HZ) && + XVidC_EdidSuppEstTimings832x624_75(EdidRaw)) { + Status = XST_SUCCESS; + } + else if ((VtMode->Timing.HActive == 1024) && + (VtMode->Timing.VActive == 768) && + (VtMode->FrameRate == XVIDC_FR_75HZ) && + XVidC_EdidSuppEstTimings1024x768_75(EdidRaw)) { + Status = XST_SUCCESS; + } + else if ((VtMode->Timing.HActive == 1152) && + (VtMode->Timing.VActive == 870) && + (VtMode->FrameRate == XVIDC_FR_75HZ) && + XVidC_EdidSuppEstTimings1152x870_75(EdidRaw)) { + Status = XST_SUCCESS; + } + else if ((VtMode->Timing.HActive == 1280) && + (VtMode->Timing.VActive == 1024) && + (VtMode->FrameRate == XVIDC_FR_75HZ) && + XVidC_EdidSuppEstTimings1280x1024_75(EdidRaw)) { + Status = XST_SUCCESS; + } + else if ((VtMode->Timing.HActive == 1024) && + (VtMode->Timing.VActive == 768) && + (VtMode->FrameRate == XVIDC_FR_87HZ) && + XVidC_EdidSuppEstTimings1024x768_87(EdidRaw)) { + Status = XST_SUCCESS; + } + else if ((VtMode->Timing.HActive == 720) && + (VtMode->Timing.VActive == 400) && + (VtMode->FrameRate == XVIDC_FR_88HZ) && + XVidC_EdidSuppEstTimings720x400_88(EdidRaw)) { + Status = XST_SUCCESS; + } + + return Status; +} + +/******************************************************************************/ +/** + * Checks whether or not a specified video timing mode is supported in the + * standard timings field of the supplied base Extended Display Identification + * Data (EDID). + * + * @param EdidRaw is the supplied base EDID to check the timing against. + * @param VtMode is the video timing mode to check for support. + * + * @return + * - XST_SUCCESS if the video timing mode is supported in the + * base EDID's standard timings fields. + * - XST_FAILURE otherwise. + * + * @note None. + * +*******************************************************************************/ +static u32 XVidC_EdidIsVideoTimingSupportedStandardTimings(const u8 *EdidRaw, + const XVidC_VideoTimingMode *VtMode) +{ + u8 Index; + + for (Index = 0; Index < 8; Index++) { + if ((VtMode->Timing.HActive == + XVidC_EdidGetStdTimingsH(EdidRaw, Index + 1)) && + (VtMode->Timing.VActive == + XVidC_EdidGetStdTimingsV(EdidRaw, Index + 1)) && + (VtMode->FrameRate == (u8)XVidC_EdidGetStdTimingsFrr( + EdidRaw, Index + 1))) { + return XST_SUCCESS; + } + } + + return XST_FAILURE; +} + +/******************************************************************************/ +/** + * Perform a power operation. + * + * @param Base is b in the power operation, b^n. + * @param Power is n in the power operation, b^n. + * + * @return Base^Power (Base to the power of Power). + * + * @note None. + * +*******************************************************************************/ +static int XVidC_CalculatePower(u8 Base, u8 Power) +{ + u8 Index; + u32 Res = 1; + + for (Index = 0; Index < Power; Index++) { + Res *= Base; + } + + return Res; +} + + +/******************************************************************************/ +/** + * Convert a fractional binary number into a fixed point Q0.DecPtIndex number + * Binary digits to the right of the decimal point represent 2^-1 to + * 2^-(DecPtIndex+1). Binary digits to the left of the decimal point represent + * 2^0, 2^1, etc. For a given Q format, using an unsigned integer container with + * n fractional bits: + * its range is [0, 2^-n] + * its resolution is 2^n + * + * @param Val is the binary representation of the fraction. + * @param DecPtIndex is the index of the decimal point in the binary + * number. The decimal point is between the binary digits at Val's + * indices (DecPtIndex -1) and (DecPtIndex). DecPtIndex will + * determine the Q format resolution. + * + * @return Fixed point representation of the fractional part of the binary + * number in Q format. + * + * @note None. + * +*******************************************************************************/ +static int XVidC_CalculateBinaryFraction_QFormat(u16 Val, u8 DecPtIndex) +{ + int Index; + u32 Res; + + for (Index = DecPtIndex - 1, Res = 0; Index >= 0; Index--) { + if (((Val >> Index) & 0x1) == 1) { + Res += XVidC_CalculatePower(2 , Index); + } + } + + return Res; +} +/** @} */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/video_common_v4_3/src/xvidc_edid.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/video_common_v4_3/src/xvidc_edid.h new file mode 100644 index 000000000..347b4f362 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/video_common_v4_3/src/xvidc_edid.h @@ -0,0 +1,484 @@ +/******************************************************************************* + * + * Copyright (C) 2017 Xilinx, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * Use of the Software is limited solely to applications: + * (a) running on a Xilinx device, or + * (b) that interact with a Xilinx device through a bus or interconnect. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of the Xilinx shall not be used + * in advertising or otherwise to promote the sale, use or other dealings in + * this Software without prior written authorization from Xilinx. + * +*******************************************************************************/ +/******************************************************************************/ +/** + * + * @file xvidc_edid.h + * @addtogroup video_common_v4_2 + * @{ + * + * Contains macros, definitions, and function declarations related to the + * Extended Display Identification Data (EDID) structure which is present in all + * monitors. All content in this file is agnostic of communication interface + * protocol. + * + * @note None. + * + * 
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -----------------------------------------------
+ * 1.0   als  11/09/14 Initial release.
+ * 2.2   als  02/01/16 Functions with pointer arguments that don't modify
+ *                     contents now const.
+ * 4.0   aad  10/26/16 Functions which return fixed point values instead of
+ *		       float
+ *
+ * +*******************************************************************************/ + +#ifndef XVIDC_EDID_H_ +/* Prevent circular inclusions by using protection macros. */ +#define XVIDC_EDID_H_ + +#ifdef __cplusplus +extern "C" { +#endif +/******************************* Include Files ********************************/ + +#include "xstatus.h" +#include "xvidc.h" + +/************************** Constant Definitions ******************************/ + +/** @name Address mapping for the base EDID block. + * @{ + */ +#define XVIDC_EDID_HEADER 0x00 +/* Vendor and product identification. */ +#define XVIDC_EDID_VPI_ID_MAN_NAME0 0x08 +#define XVIDC_EDID_VPI_ID_MAN_NAME1 0x09 +#define XVIDC_EDID_VPI_ID_PROD_CODE_LSB 0x0A +#define XVIDC_EDID_VPI_ID_PROD_CODE_MSB 0x0B +#define XVIDC_EDID_VPI_ID_SN0 0x0C +#define XVIDC_EDID_VPI_ID_SN1 0x0D +#define XVIDC_EDID_VPI_ID_SN2 0x0E +#define XVIDC_EDID_VPI_ID_SN3 0x0F +#define XVIDC_EDID_VPI_WEEK_MAN 0x10 +#define XVIDC_EDID_VPI_YEAR 0x11 +/* EDID structure version and revision. */ +#define XVIDC_EDID_STRUCT_VER 0x12 +#define XVIDC_EDID_STRUCT_REV 0x13 +/* Basic display parameters and features. */ +#define XVIDC_EDID_BDISP_VID 0x14 +#define XVIDC_EDID_BDISP_H_SSAR 0x15 +#define XVIDC_EDID_BDISP_V_SSAR 0x16 +#define XVIDC_EDID_BDISP_GAMMA 0x17 +#define XVIDC_EDID_BDISP_FEATURE 0x18 +/* Color characteristics (display x,y chromaticity coordinates). */ +#define XVIDC_EDID_CC_RG_LOW 0x19 +#define XVIDC_EDID_CC_BW_LOW 0x1A +#define XVIDC_EDID_CC_REDX_HIGH 0x1B +#define XVIDC_EDID_CC_REDY_HIGH 0x1C +#define XVIDC_EDID_CC_GREENX_HIGH 0x1D +#define XVIDC_EDID_CC_GREENY_HIGH 0x1E +#define XVIDC_EDID_CC_BLUEX_HIGH 0x1F +#define XVIDC_EDID_CC_BLUEY_HIGH 0x20 +#define XVIDC_EDID_CC_WHITEX_HIGH 0x21 +#define XVIDC_EDID_CC_WHITEY_HIGH 0x22 +/* Established timings. */ +#define XVIDC_EDID_EST_TIMINGS_I 0x23 +#define XVIDC_EDID_EST_TIMINGS_II 0x24 +#define XVIDC_EDID_EST_TIMINGS_MAN 0x25 +/* Standard timings. */ +#define XVIDC_EDID_STD_TIMINGS_H(N) (0x26 + 2 * (N - 1)) +#define XVIDC_EDID_STD_TIMINGS_AR_FRR(N) (0x27 + 2 * (N - 1)) +/* 18 byte descriptors. */ +#define XVIDC_EDID_18BYTE_DESCRIPTOR(N) (0x36 + 18 * (N - 1)) +#define XVIDC_EDID_PTM (XVIDC_EDID_18BYTE_DESCRIPTOR(1)) +/* - Detailed timing descriptor (DTD) / Preferred timing mode (PTM). */ +#define XVIDC_EDID_DTD_PTM_PIXEL_CLK_KHZ_LSB 0x00 +#define XVIDC_EDID_DTD_PTM_PIXEL_CLK_KHZ_MSB 0x01 +#define XVIDC_EDID_DTD_PTM_HRES_LSB 0x02 +#define XVIDC_EDID_DTD_PTM_HBLANK_LSB 0x03 +#define XVIDC_EDID_DTD_PTM_HRES_HBLANK_U4 0x04 +#define XVIDC_EDID_DTD_PTM_VRES_LSB 0x05 +#define XVIDC_EDID_DTD_PTM_VBLANK_LSB 0x06 +#define XVIDC_EDID_DTD_PTM_VRES_VBLANK_U4 0x07 +#define XVIDC_EDID_DTD_PTM_HFPORCH_LSB 0x08 +#define XVIDC_EDID_DTD_PTM_HSPW_LSB 0x09 +#define XVIDC_EDID_DTD_PTM_VFPORCH_VSPW_L4 0x0A +#define XVIDC_EDID_DTD_PTM_XFPORCH_XSPW_U2 0x0B +#define XVIDC_EDID_DTD_PTM_HIMGSIZE_MM_LSB 0x0C +#define XVIDC_EDID_DTD_PTM_VIMGSIZE_MM_LSB 0x0D +#define XVIDC_EDID_DTD_PTM_XIMGSIZE_MM_U4 0x0E +#define XVIDC_EDID_DTD_PTM_HBORDER 0x0F +#define XVIDC_EDID_DTD_PTM_VBORDER 0x10 +#define XVIDC_EDID_DTD_PTM_SIGNAL 0x11 + +/* Extension block count. */ +#define XVIDC_EDID_EXT_BLK_COUNT 0x7E +/* Checksum. */ +#define XVIDC_EDID_CHECKSUM 0x7F +/* @} */ + +/******************************************************************************/ + +/** @name Extended Display Identification Data: Masks, shifts, and values. + * @{ + */ +#define XVIDC_EDID_VPI_ID_MAN_NAME0_CHAR0_SHIFT 2 +#define XVIDC_EDID_VPI_ID_MAN_NAME0_CHAR0_MASK (0x1F << 2) +#define XVIDC_EDID_VPI_ID_MAN_NAME0_CHAR1_MASK 0x03 +#define XVIDC_EDID_VPI_ID_MAN_NAME0_CHAR1_POS 3 +#define XVIDC_EDID_VPI_ID_MAN_NAME1_CHAR1_SHIFT 5 +#define XVIDC_EDID_VPI_ID_MAN_NAME1_CHAR2_MASK 0x1F + +/* Basic display parameters and features: Video input definition. */ +#define XVIDC_EDID_BDISP_VID_VSI_SHIFT 7 +#define XVIDC_EDID_BDISP_VID_VSI_MASK (0x01 << 7) +#define XVIDC_EDID_BDISP_VID_ANA_SLS_SHIFT 5 +#define XVIDC_EDID_BDISP_VID_ANA_SLS_MASK (0x03 << 5) +#define XVIDC_EDID_BDISP_VID_ANA_SLS_0700_0300_1000 0x0 +#define XVIDC_EDID_BDISP_VID_ANA_SLS_0714_0286_1000 0x1 +#define XVIDC_EDID_BDISP_VID_ANA_SLS_1000_0400_1400 0x2 +#define XVIDC_EDID_BDISP_VID_ANA_SLS_0700_0000_0700 0x3 +#define XVIDC_EDID_BDISP_VID_ANA_VID_SETUP_MASK (0x01 << 4) +#define XVIDC_EDID_BDISP_VID_ANA_SEP_SYNC_HV_MASK (0x01 << 3) +#define XVIDC_EDID_BDISP_VID_ANA_COMP_SYNC_H_MASK (0x01 << 2) +#define XVIDC_EDID_BDISP_VID_ANA_COMP_SYNC_G_MASK (0x01 << 1) +#define XVIDC_EDID_BDISP_VID_ANA_SERR_V_SYNC_MASK (0x01) +#define XVIDC_EDID_BDISP_VID_DIG_BPC_SHIFT 4 +#define XVIDC_EDID_BDISP_VID_DIG_BPC_MASK (0x7 << 4) +#define XVIDC_EDID_BDISP_VID_DIG_BPC_UNDEF 0x0 +#define XVIDC_EDID_BDISP_VID_DIG_BPC_6 0x1 +#define XVIDC_EDID_BDISP_VID_DIG_BPC_8 0x2 +#define XVIDC_EDID_BDISP_VID_DIG_BPC_10 0x3 +#define XVIDC_EDID_BDISP_VID_DIG_BPC_12 0x4 +#define XVIDC_EDID_BDISP_VID_DIG_BPC_14 0x5 +#define XVIDC_EDID_BDISP_VID_DIG_BPC_16 0x6 +#define XVIDC_EDID_BDISP_VID_DIG_VIS_MASK 0xF +#define XVIDC_EDID_BDISP_VID_DIG_VIS_UNDEF 0x0 +#define XVIDC_EDID_BDISP_VID_DIG_VIS_DVI 0x1 +#define XVIDC_EDID_BDISP_VID_DIG_VIS_HDMIA 0x2 +#define XVIDC_EDID_BDISP_VID_DIG_VIS_HDMIB 0x3 +#define XVIDC_EDID_BDISP_VID_DIG_VIS_MDDI 0x4 +#define XVIDC_EDID_BDISP_VID_DIG_VIS_DP 0x5 + +/* Basic display parameters and features: Feature support. */ +#define XVIDC_EDID_BDISP_FEATURE_PM_STANDBY_MASK (0x1 << 7) +#define XVIDC_EDID_BDISP_FEATURE_PM_SUSPEND_MASK (0x1 << 6) +#define XVIDC_EDID_BDISP_FEATURE_PM_OFF_VLP_MASK (0x1 << 5) +#define XVIDC_EDID_BDISP_FEATURE_ANA_COLORTYPE_SHIFT 3 +#define XVIDC_EDID_BDISP_FEATURE_ANA_COLORTYPE_MASK (0x3 << 3) +#define XVIDC_EDID_BDISP_FEATURE_ANA_COLORTYPE_MCG 0x0 +#define XVIDC_EDID_BDISP_FEATURE_ANA_COLORTYPE_RGB 0x1 +#define XVIDC_EDID_BDISP_FEATURE_ANA_COLORTYPE_NRGB 0x2 +#define XVIDC_EDID_BDISP_FEATURE_ANA_COLORTYPE_UNDEF 0x3 +#define XVIDC_EDID_BDISP_FEATURE_DIG_COLORENC_YCRCB444_MASK (0x1 << 3) +#define XVIDC_EDID_BDISP_FEATURE_DIG_COLORENC_YCRCB422_MASK (0x1 << 4) +#define XVIDC_EDID_BDISP_FEATURE_SRGB_DEF_MASK (0x1 << 2) +#define XVIDC_EDID_BDISP_FEATURE_PTM_INC_MASK (0x1 << 1) +#define XVIDC_EDID_BDISP_FEATURE_CONTFREQ_MASK (0x1) + +/* Color characteristics (display x,y chromaticity coordinates). */ +#define XVIDC_EDID_CC_HIGH_SHIFT 2 +#define XVIDC_EDID_CC_RBX_LOW_SHIFT 6 +#define XVIDC_EDID_CC_RBY_LOW_SHIFT 4 +#define XVIDC_EDID_CC_RBY_LOW_MASK (0x3 << 4) +#define XVIDC_EDID_CC_GWX_LOW_SHIFT 2 +#define XVIDC_EDID_CC_GWX_LOW_MASK (0x3 << 2) +#define XVIDC_EDID_CC_GWY_LOW_MASK (0x3) +#define XVIDC_EDID_CC_GREENY_HIGH 0x1E +#define XVIDC_EDID_CC_BLUEX_HIGH 0x1F +#define XVIDC_EDID_CC_BLUEY_HIGH 0x20 +#define XVIDC_EDID_CC_WHITEX_HIGH 0x21 +#define XVIDC_EDID_CC_WHITEY_HIGH 0x22 + +/* Established timings. */ +#define XVIDC_EDID_EST_TIMINGS_I_720x400_70_MASK (0x1 << 7) +#define XVIDC_EDID_EST_TIMINGS_I_720x400_88_MASK (0x1 << 6) +#define XVIDC_EDID_EST_TIMINGS_I_640x480_60_MASK (0x1 << 5) +#define XVIDC_EDID_EST_TIMINGS_I_640x480_67_MASK (0x1 << 4) +#define XVIDC_EDID_EST_TIMINGS_I_640x480_72_MASK (0x1 << 3) +#define XVIDC_EDID_EST_TIMINGS_I_640x480_75_MASK (0x1 << 2) +#define XVIDC_EDID_EST_TIMINGS_I_800x600_56_MASK (0x1 << 1) +#define XVIDC_EDID_EST_TIMINGS_I_800x600_60_MASK (0x1) +#define XVIDC_EDID_EST_TIMINGS_II_800x600_72_MASK (0x1 << 7) +#define XVIDC_EDID_EST_TIMINGS_II_800x600_75_MASK (0x1 << 6) +#define XVIDC_EDID_EST_TIMINGS_II_832x624_75_MASK (0x1 << 5) +#define XVIDC_EDID_EST_TIMINGS_II_1024x768_87_MASK (0x1 << 4) +#define XVIDC_EDID_EST_TIMINGS_II_1024x768_60_MASK (0x1 << 3) +#define XVIDC_EDID_EST_TIMINGS_II_1024x768_70_MASK (0x1 << 2) +#define XVIDC_EDID_EST_TIMINGS_II_1024x768_75_MASK (0x1 << 1) +#define XVIDC_EDID_EST_TIMINGS_II_1280x1024_75_MASK (0x1) +#define XVIDC_EDID_EST_TIMINGS_MAN_1152x870_75_MASK (0x1 << 7) +#define XVIDC_EDID_EST_TIMINGS_MAN_MASK (0x7F) + +/* Standard timings. */ +#define XVIDC_EDID_STD_TIMINGS_AR_SHIFT 6 +#define XVIDC_EDID_STD_TIMINGS_AR_16_10 0x0 +#define XVIDC_EDID_STD_TIMINGS_AR_4_3 0x1 +#define XVIDC_EDID_STD_TIMINGS_AR_5_4 0x2 +#define XVIDC_EDID_STD_TIMINGS_AR_16_9 0x3 +#define XVIDC_EDID_STD_TIMINGS_FRR_MASK (0x3F) + +/* Detailed timing descriptor (DTD) / Preferred timing mode (PTM). */ +#define XVIDC_EDID_DTD_PTM_XRES_XBLANK_U4_XBLANK_MASK 0x0F +#define XVIDC_EDID_DTD_PTM_XRES_XBLANK_U4_XRES_MASK 0xF0 +#define XVIDC_EDID_DTD_PTM_XRES_XBLANK_U4_XRES_SHIFT 4 +#define XVIDC_EDID_DTD_PTM_VFPORCH_VSPW_L4_VSPW_MASK 0x0F +#define XVIDC_EDID_DTD_PTM_VFPORCH_VSPW_L4_VFPORCH_MASK 0xF0 +#define XVIDC_EDID_DTD_PTM_VFPORCH_VSPW_L4_VFPORCH_SHIFT 4 +#define XVIDC_EDID_DTD_PTM_XFPORCH_XSPW_U2_HFPORCH_MASK 0xC0 +#define XVIDC_EDID_DTD_PTM_XFPORCH_XSPW_U2_HSPW_MASK 0x30 +#define XVIDC_EDID_DTD_PTM_XFPORCH_XSPW_U2_VFPORCH_MASK 0x0C +#define XVIDC_EDID_DTD_PTM_XFPORCH_XSPW_U2_VSPW_MASK 0x03 +#define XVIDC_EDID_DTD_PTM_XFPORCH_XSPW_U2_HFPORCH_SHIFT 6 +#define XVIDC_EDID_DTD_PTM_XFPORCH_XSPW_U2_HSPW_SHIFT 4 +#define XVIDC_EDID_DTD_PTM_XFPORCH_XSPW_U2_VFPORCH_SHIFT 2 +#define XVIDC_EDID_DTD_PTM_XIMGSIZE_MM_U4_VIMGSIZE_MM_MASK 0x0F +#define XVIDC_EDID_DTD_PTM_XIMGSIZE_MM_U4_HIMGSIZE_MM_MASK 0xF0 +#define XVIDC_EDID_DTD_PTM_XIMGSIZE_MM_U4_HIMGSIZE_MM_SHIFT 4 +#define XVIDC_EDID_DTD_PTM_SIGNAL_INTERLACED_MASK 0x80 +#define XVIDC_EDID_DTD_PTM_SIGNAL_INTERLACED_SHIFT 7 +#define XVIDC_EDID_DTD_PTM_SIGNAL_HPOLARITY_MASK 0x02 +#define XVIDC_EDID_DTD_PTM_SIGNAL_VPOLARITY_MASK 0x04 +#define XVIDC_EDID_DTD_PTM_SIGNAL_HPOLARITY_SHIFT 1 +#define XVIDC_EDID_DTD_PTM_SIGNAL_VPOLARITY_SHIFT 2 +/* @} */ + +/******************* Macros (Inline Functions) Definitions ********************/ + +#define XVidC_EdidIsHeaderValid(E) \ + !memcmp(E, "\x00\xFF\xFF\xFF\xFF\xFF\xFF\x00", 8) + +/* Vendor and product identification: ID manufacturer name. */ +/* void XVidC_EdidGetManName(const u8 *EdidRaw, char ManName[4]); */ + +/* Vendor and product identification: ID product code. */ +#define XVidC_EdidGetIdProdCode(E) \ + ((u16)((E[XVIDC_EDID_VPI_ID_PROD_CODE_MSB] << 8) | \ + E[XVIDC_EDID_VPI_ID_PROD_CODE_LSB])) + +/* Vendor and product identification: ID serial number. */ +#define XVidC_EdidGetIdSn(E) \ + ((u32)((E[XVIDC_EDID_VPI_ID_SN3] << 24) | \ + (E[XVIDC_EDID_VPI_ID_SN2] << 16) | (E[XVIDC_EDID_VPI_ID_SN1] << 8) | \ + E[XVIDC_EDID_VPI_ID_SN0])) + +/* Vendor and product identification: Week and year of manufacture or model + * year. */ +#define XVidC_EdidGetManWeek(E) (E[XVIDC_EDID_VPI_WEEK_MAN]) +#define XVidC_EdidGetModManYear(E) (E[XVIDC_EDID_VPI_YEAR] + 1990) +#define XVidC_EdidIsYearModel(E) (XVidC_EdidGetManWeek(E) == 0xFF) +#define XVidC_EdidIsYearMan(E) (XVidC_EdidGetManWeek(E) != 0xFF) + +/* EDID structure version and revision. */ +#define XVidC_EdidGetStructVer(E) (E[XVIDC_EDID_STRUCT_VER]) +#define XVidC_EdidGetStructRev(E) (E[XVIDC_EDID_STRUCT_REV]) + +/* Basic display parameters and features: Video input definition. */ +#define XVidC_EdidIsDigitalSig(E) \ + ((E[XVIDC_EDID_BDISP_VID] & XVIDC_EDID_BDISP_VID_VSI_MASK) != 0) +#define XVidC_EdidIsAnalogSig(E) \ + ((E[XVIDC_EDID_BDISP_VID] & XVIDC_EDID_BDISP_VID_VSI_MASK) == 0) +#define XVidC_EdidGetAnalogSigLvlStd(E) \ + ((E[XVIDC_EDID_BDISP_VID] & XVIDC_EDID_BDISP_VID_ANA_SLS_MASK) >> \ + XVIDC_EDID_BDISP_VID_ANA_SLS_SHIFT) +#define XVidC_EdidGetAnalogSigVidSetup(E) \ + ((E[XVIDC_EDID_BDISP_VID] & \ + XVIDC_EDID_BDISP_VID_ANA_VID_SETUP_MASK) != 0) +#define XVidC_EdidSuppAnalogSigSepSyncHv(E) \ + ((E[XVIDC_EDID_BDISP_VID] & \ + XVIDC_EDID_BDISP_VID_ANA_SEP_SYNC_HV_MASK) != 0) +#define XVidC_EdidSuppAnalogSigCompSyncH(E) \ + ((E[XVIDC_EDID_BDISP_VID] & \ + XVIDC_EDID_BDISP_VID_ANA_COMP_SYNC_H_MASK) != 0) +#define XVidC_EdidSuppAnalogSigCompSyncG(E) \ + ((E[XVIDC_EDID_BDISP_VID] & \ + XVIDC_EDID_BDISP_VID_ANA_COMP_SYNC_G_MASK) != 0) +#define XVidC_EdidSuppAnalogSigSerrVsync(E) \ + ((E[XVIDC_EDID_BDISP_VID] & \ + XVIDC_EDID_BDISP_VID_ANA_SERR_V_SYNC_MASK) != 0) +/* XVidC_ColorDepth XVidC_EdidGetColorDepth(const u8 *EdidRaw); */ +#define XVidC_EdidGetDigitalSigIfaceStd(E) \ + (E[XVIDC_EDID_BDISP_VID] & XVIDC_EDID_BDISP_VID_DIG_VIS_MASK) + +/* Basic display parameters and features: Horizontal and vertical screen size or + * aspect ratio. */ +#define XVidC_EdidIsSsArDefined(E) \ + ((E[XVIDC_EDID_BDISP_H_SSAR] | E[XVIDC_EDID_BDISP_V_SSAR]) != 0) +#define XVidC_EdidGetSsArH(E) E[XVIDC_EDID_BDISP_H_SSAR] +#define XVidC_EdidGetSsArV(E) E[XVIDC_EDID_BDISP_V_SSAR] +#define XVidC_EdidIsSsArSs(E) \ + ((XVidC_EdidGetSsArH(E) != 0) && (XVidC_EdidGetSsArV(E) != 0)) +#define XVidC_EdidIsSsArArL(E) \ + ((XVidC_EdidGetSsArH(E) != 0) && (XVidC_EdidGetSsArV(E) == 0)) +#define XVidC_EdidIsSsArArP(E) \ + ((XVidC_EdidGetSsArH(E) == 0) && (XVidC_EdidGetSsArV(E) != 0)) +#define XVidC_EdidGetSsArArL(E) \ + ((float)((XVidC_EdidGetSsArH(E) + 99.0) / 100.0)) +#define XVidC_EdidGetSsArArP(E) \ + ((float)(100.0 / (XVidC_EdidGetSsArV(E) + 99.0))) + +/* Basic display parameters and features: Gamma. */ +#define XVidC_EdidIsGammaInExt(E) (E[XVIDC_EDID_BDISP_GAMMA] == 0xFF) +#define XVidC_EdidGetGamma(E) \ + ((float)((E[XVIDC_EDID_BDISP_GAMMA] + 100.0) / 100.0)) + +/* Basic display parameters and features: Feature support. */ +#define XVidC_EdidSuppFeaturePmStandby(E) \ + ((E[XVIDC_EDID_BDISP_FEATURE] & \ + XVIDC_EDID_BDISP_FEATURE_PM_STANDBY_MASK) != 0) +#define XVidC_EdidSuppFeaturePmSuspend(E) \ + ((E[XVIDC_EDID_BDISP_FEATURE] & \ + XVIDC_EDID_BDISP_FEATURE_PM_SUSPEND_MASK) != 0) +#define XVidC_EdidSuppFeaturePmOffVlp(E) \ + ((E[XVIDC_EDID_BDISP_FEATURE] & \ + XVIDC_EDID_BDISP_FEATURE_PM_OFF_VLP_MASK) != 0) +#define XVidC_EdidGetFeatureAnaColorType(E) \ + ((E[XVIDC_EDID_BDISP_FEATURE] & \ + XVIDC_EDID_BDISP_FEATURE_ANA_COLORTYPE_MASK) >> \ + XVIDC_EDID_BDISP_FEATURE_ANA_COLORTYPE_SHIFT) +#define XVidC_EdidSuppFeatureDigColorEncYCrCb444(E) \ + ((E[XVIDC_EDID_BDISP_FEATURE] & \ + XVIDC_EDID_BDISP_FEATURE_DIG_COLORENC_YCRCB444_MASK) != 0) +#define XVidC_EdidSuppFeatureDigColorEncYCrCb422(E) \ + ((E[XVIDC_EDID_BDISP_FEATURE] & \ + XVIDC_EDID_BDISP_FEATURE_DIG_COLORENC_YCRCB422_MASK) != 0) +#define XVidC_EdidIsFeatureSrgbDef(E) \ + ((E[XVIDC_EDID_BDISP_FEATURE] & \ + XVIDC_EDID_BDISP_FEATURE_SRGB_DEF_MASK) != 0) +#define XVidC_EdidIsFeaturePtmInc(E) \ + ((E[XVIDC_EDID_BDISP_FEATURE] & \ + XVIDC_EDID_BDISP_FEATURE_PTM_INC_MASK) != 0) +#define XVidC_EdidIsFeatureContFreq(E) \ + ((E[XVIDC_EDID_BDISP_FEATURE] & \ + XVIDC_EDID_BDISP_FEATURE_CONTFREQ_MASK) != 0) + +/* Established timings. */ +#define XVidC_EdidSuppEstTimings720x400_70(E) \ + ((E[XVIDC_EDID_EST_TIMINGS_I] & \ + XVIDC_EDID_EST_TIMINGS_I_720x400_70_MASK) != 0) +#define XVidC_EdidSuppEstTimings720x400_88(E) \ + ((E[XVIDC_EDID_EST_TIMINGS_I] & \ + XVIDC_EDID_EST_TIMINGS_I_720x400_88_MASK) != 0) +#define XVidC_EdidSuppEstTimings640x480_60(E) \ + ((E[XVIDC_EDID_EST_TIMINGS_I] & \ + XVIDC_EDID_EST_TIMINGS_I_640x480_60_MASK) != 0) +#define XVidC_EdidSuppEstTimings640x480_67(E) \ + ((E[XVIDC_EDID_EST_TIMINGS_I] & \ + XVIDC_EDID_EST_TIMINGS_I_640x480_67_MASK) != 0) +#define XVidC_EdidSuppEstTimings640x480_72(E) \ + ((E[XVIDC_EDID_EST_TIMINGS_I] & \ + XVIDC_EDID_EST_TIMINGS_I_640x480_72_MASK) != 0) +#define XVidC_EdidSuppEstTimings640x480_75(E) \ + ((E[XVIDC_EDID_EST_TIMINGS_I] & \ + XVIDC_EDID_EST_TIMINGS_I_640x480_75_MASK) != 0) +#define XVidC_EdidSuppEstTimings800x600_56(E) \ + ((E[XVIDC_EDID_EST_TIMINGS_I] & \ + XVIDC_EDID_EST_TIMINGS_I_800x600_56_MASK) != 0) +#define XVidC_EdidSuppEstTimings800x600_60(E) \ + ((E[XVIDC_EDID_EST_TIMINGS_I] & \ + XVIDC_EDID_EST_TIMINGS_I_800x600_60_MASK) != 0) +#define XVidC_EdidSuppEstTimings800x600_72(E) \ + ((E[XVIDC_EDID_EST_TIMINGS_II] & \ + XVIDC_EDID_EST_TIMINGS_II_800x600_72_MASK) != 0) +#define XVidC_EdidSuppEstTimings800x600_75(E) \ + ((E[XVIDC_EDID_EST_TIMINGS_II] & \ + XVIDC_EDID_EST_TIMINGS_II_800x600_75_MASK) != 0) +#define XVidC_EdidSuppEstTimings832x624_75(E) \ + ((E[XVIDC_EDID_EST_TIMINGS_II] & \ + XVIDC_EDID_EST_TIMINGS_II_832x624_75_MASK) != 0) +#define XVidC_EdidSuppEstTimings1024x768_87(E) \ + ((E[XVIDC_EDID_EST_TIMINGS_II] & \ + XVIDC_EDID_EST_TIMINGS_II_1024x768_87_MASK) != 0) +#define XVidC_EdidSuppEstTimings1024x768_60(E) \ + ((E[XVIDC_EDID_EST_TIMINGS_II] & \ + XVIDC_EDID_EST_TIMINGS_II_1024x768_60_MASK) != 0) +#define XVidC_EdidSuppEstTimings1024x768_70(E) \ + ((E[XVIDC_EDID_EST_TIMINGS_II] & \ + XVIDC_EDID_EST_TIMINGS_II_1024x768_70_MASK) != 0) +#define XVidC_EdidSuppEstTimings1024x768_75(E) \ + ((E[XVIDC_EDID_EST_TIMINGS_II] & \ + XVIDC_EDID_EST_TIMINGS_II_1024x768_75_MASK) != 0) +#define XVidC_EdidSuppEstTimings1280x1024_75(E) \ + ((E[XVIDC_EDID_EST_TIMINGS_II] & \ + XVIDC_EDID_EST_TIMINGS_II_1280x1024_75_MASK) != 0) +#define XVidC_EdidSuppEstTimings1152x870_75(E) \ + ((E[XVIDC_EDID_EST_TIMINGS_MAN] & \ + XVIDC_EDID_EST_TIMINGS_MAN_1152x870_75_MASK) != 0) +#define XVidC_EdidGetTimingsMan(E) \ + (E[XVIDC_EDID_EST_TIMINGS_MAN] & XVIDC_EDID_EST_TIMINGS_MAN_MASK) + +/* Standard timings. */ +#define XVidC_EdidGetStdTimingsH(E, N) \ + ((E[XVIDC_EDID_STD_TIMINGS_H(N)] + 31) * 8) +#define XVidC_EdidGetStdTimingsAr(E, N) \ + (E[XVIDC_EDID_STD_TIMINGS_AR_FRR(N)] >> XVIDC_EDID_STD_TIMINGS_AR_SHIFT) +#define XVidC_EdidGetStdTimingsFrr(E, N) \ + ((E[XVIDC_EDID_STD_TIMINGS_AR_FRR(N)] & \ + XVIDC_EDID_STD_TIMINGS_FRR_MASK) + 60) +/* u16 XVidC_EdidGetStdTimingsV(const u8 *EdidRaw, u8 StdTimingsNum); */ +#define XVidC_EdidIsDtdPtmInterlaced(E) \ + ((E[XVIDC_EDID_PTM + XVIDC_EDID_DTD_PTM_SIGNAL] & \ + XVIDC_EDID_DTD_PTM_SIGNAL_INTERLACED_MASK) >> \ + XVIDC_EDID_DTD_PTM_SIGNAL_INTERLACED_SHIFT) + +/* Extension block count. */ +#define XVidC_EdidGetExtBlkCount(E) (E[XVIDC_EDID_EXT_BLK_COUNT]) + +/* Checksum. */ +#define XVidC_EdidGetChecksum(E) (E[XVIDC_EDID_CHECKSUM]) + +/**************************** Function Prototypes *****************************/ + +/* Vendor and product identification: ID manufacturer name. */ +void XVidC_EdidGetManName(const u8 *EdidRaw, char ManName[4]); + +/* Basic display parameters and features: Video input definition. */ +XVidC_ColorDepth XVidC_EdidGetColorDepth(const u8 *EdidRaw); + +/* Color characteristics (display x,y chromaticity coordinates). */ +int XVidC_EdidGetCcRedX(const u8 *EdidRaw); +int XVidC_EdidGetCcRedY(const u8 *EdidRaw); +int XVidC_EdidGetCcGreenX(const u8 *EdidRaw); +int XVidC_EdidGetCcGreenY(const u8 *EdidRaw); +int XVidC_EdidGetCcBlueX(const u8 *EdidRaw); +int XVidC_EdidGetCcBlueY(const u8 *EdidRaw); +int XVidC_EdidGetCcWhiteX(const u8 *EdidRaw); +int XVidC_EdidGetCcWhiteY(const u8 *EdidRaw); + +/* Standard timings. */ +u16 XVidC_EdidGetStdTimingsV(const u8 *EdidRaw, u8 StdTimingsNum); + +/* Utility functions. */ +u32 XVidC_EdidIsVideoTimingSupported(const u8 *EdidRaw, + const XVidC_VideoTimingMode *VtMode); + +#ifdef __cplusplus +} +#endif +#endif /* XVIDC_EDID_H_ */ +/** @} */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/video_common_v4_3/src/xvidc_edid_ext.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/video_common_v4_3/src/xvidc_edid_ext.c new file mode 100644 index 000000000..c8ce9f125 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/video_common_v4_3/src/xvidc_edid_ext.c @@ -0,0 +1,174 @@ +/****************************************************************************** +* +* Copyright (C) 2017 - 2018 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xhdmi_edid.h +* +* Software Initalization & Configuration +* +* Interrupts +* +* Virtual Memory +* +* This driver supports Virtual Memory. The RTOS is responsible for calculating +* the correct device base address in Virtual Memory space. +* +* Threads +* +* This driver is not thread safe. Any needs for threads or thread mutual +* exclusion must be satisfied by the layer above this driver. +* +* Asserts +* +* Asserts are used within all Xilinx drivers to enforce constraints on argument +* values. Asserts can be turned off on a system-wide basis by defining at +* compile time, the NDEBUG identifier. By default, asserts are turned on and it +* is recommended that users leave asserts on during development. +* +* Building the driver +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date       Changes
+* ----- ---- ---------- --------------------------------------------------
+* 1.0   mmo  24-01-2017 EDID Parser capability
+*
+* +******************************************************************************/ +#include "stdio.h" +#include "string.h" +#include "stdlib.h" +#include "stdbool.h" +#include "xil_types.h" +#include "xstatus.h" +#include "xil_exception.h" +#include "xvidc_edid_ext.h" + +static XV_VidC_PicAspectRatio xv_vidc_getPicAspectRatio(u16 hres, u16 vres); + +static XV_VidC_PicAspectRatio xv_vidc_getPicAspectRatio(u16 hres, u16 vres) { + XV_VidC_PicAspectRatio ar; +#define HAS_RATIO_OF(x, y) (hres == (vres*(x)/(y))&&!((vres*(x))%(y))) + if (HAS_RATIO_OF(16, 10)) { + ar.width = 16; + ar.height = 10; + return ar; + } + if (HAS_RATIO_OF(4, 3)) { + ar.width = 4; + ar.height = 3; + return ar; + } + if (HAS_RATIO_OF(5, 4)) { + ar.width = 5; + ar.height = 4; + return ar; + } + if (HAS_RATIO_OF(16, 9)) { + ar.width = 16; + ar.height = 9; + return ar; +#undef HAS_RATIO + } else { + ar.width = 0; + ar.height = 0; + return ar; + } +} + + +void XV_VidC_EdidCtrlParamInit (XV_VidC_EdidCntrlParam *EdidCtrlParam) { + + /* Verify arguments. */ + Xil_AssertVoid(EdidCtrlParam != NULL); + + (void)memset((void *)EdidCtrlParam, 0, + sizeof(XV_VidC_EdidCntrlParam)); + + EdidCtrlParam->IsHdmi = XVIDC_ISDVI; + EdidCtrlParam->IsYCbCr444Supp = XVIDC_NOT_SUPPORTED; + EdidCtrlParam->IsYCbCr420Supp = XVIDC_NOT_SUPPORTED; + EdidCtrlParam->IsYCbCr422Supp = XVIDC_NOT_SUPPORTED; + EdidCtrlParam->IsYCbCr444DeepColSupp = XVIDC_NOT_SUPPORTED; + EdidCtrlParam->Is30bppSupp = XVIDC_NOT_SUPPORTED; + EdidCtrlParam->Is36bppSupp = XVIDC_NOT_SUPPORTED; + EdidCtrlParam->Is48bppSupp = XVIDC_NOT_SUPPORTED; + EdidCtrlParam->IsYCbCr420dc30bppSupp = XVIDC_NOT_SUPPORTED; + EdidCtrlParam->IsYCbCr420dc36bppSupp = XVIDC_NOT_SUPPORTED; + EdidCtrlParam->IsYCbCr420dc48bppSupp = XVIDC_NOT_SUPPORTED; + EdidCtrlParam->IsSCDCReadRequestReady= XVIDC_NOT_SUPPORTED; + EdidCtrlParam->IsSCDCPresent = XVIDC_NOT_SUPPORTED; + EdidCtrlParam->MaxFrameRateSupp = 0; + EdidCtrlParam->MaxTmdsMhz = 0; +} + +XV_VidC_TimingParam +XV_VidC_timing + (const struct xvidc_edid_detailed_timing_descriptor * const dtb) +{ + XV_VidC_TimingParam timing; + + timing.hres = xvidc_edid_detailed_timing_horizontal_active(dtb); + timing.vres = xvidc_edid_detailed_timing_vertical_active(dtb); + timing.htotal = timing.hres + + xvidc_edid_detailed_timing_horizontal_blanking(dtb); + timing.vtotal = timing.vres + + xvidc_edid_detailed_timing_vertical_blanking(dtb); + timing.hfp = xvidc_edid_detailed_timing_horizontal_sync_offset(dtb); + timing.vfp = xvidc_edid_detailed_timing_vertical_sync_offset(dtb); + timing.hsync_width = + xvidc_edid_detailed_timing_horizontal_sync_pulse_width(dtb); + timing.vsync_width = + xvidc_edid_detailed_timing_vertical_sync_pulse_width(dtb); + timing.pixclk = xvidc_edid_detailed_timing_pixel_clock(dtb); + timing.vfreq = (timing.pixclk / (timing.vtotal * timing.htotal)); + timing.vidfrmt = (XVidC_VideoFormat) dtb->interlaced; + timing.aspect_ratio = + xv_vidc_getPicAspectRatio (timing.hres, timing.vres); + timing.hsync_polarity = dtb->signal_pulse_polarity; + timing.vsync_polarity = dtb->signal_serration_polarity; + + return timing; +} + +#if XVIDC_EDID_VERBOSITY > 1 +XV_VidC_DoubleRep Double2Int (double in_val) { + XV_VidC_DoubleRep DR; + + DR.Integer = in_val; + DR.Decimal = (in_val - DR.Integer) * 10000; + + return (DR); +} +#endif diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/video_common_v4_3/src/xvidc_edid_ext.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/video_common_v4_3/src/xvidc_edid_ext.h new file mode 100644 index 000000000..d685723f5 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/video_common_v4_3/src/xvidc_edid_ext.h @@ -0,0 +1,626 @@ +/* vim: set et fde fdm=syntax ft=c.doxygen ts=4 sts=4 sw=4 : */ +/* + * Copyright © 2010-2011 Saleem Abdulrasool . + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO + * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef xvidc_edid_h +#define xvidc_edid_h + +#include "stdbool.h" +#include "xvidc.h" +#include "xil_assert.h" +#include "xvidc_cea861.h" + +#define XVIDC_EDID_BLOCK_SIZE (0x80) +#define XVIDC_EDID_MAX_EXTENSIONS (0xFE) + + +static const u8 XVIDC_EDID_EXT_HEADER[] = + { 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 }; +static const u8 XVIDC_EDID_STANDARD_TIMING_DESCRIPTOR_INVALID[] = + { 0x01, 0x01 }; + +enum xvidc_edid_extension_type { + XVIDC_EDID_EXTENSION_TIMING = 0x01, /* Timing Extension */ + XVIDC_EDID_EXTENSION_CEA = 0x02, /* Additional Timing Block + Data (CEA EDID Timing Extension)*/ + XVIDC_EDID_EXTENSION_VTB = 0x10, /* Video Timing Block + Extension (VTB-EXT)*/ + XVIDC_EDID_EXTENSION_XVIDC_EDID_2_0= 0x20, /* EDID 2.0 Extension */ + XVIDC_EDID_EXTENSION_DI = 0x40, /* Display Information + Extension (DI-EXT) */ + XVIDC_EDID_EXTENSION_LS = 0x50, /* Localised String + Extension (LS-EXT) */ + XVIDC_EDID_EXTENSION_MI = 0x60, /* Microdisplay Interface + Extension (MI-EXT) */ + XVIDC_EDID_EXTENSION_DTCDB_1 = 0xA7, /* Display Transfer + Characteristics Data Block (DTCDB) */ + XVIDC_EDID_EXTENSION_DTCDB_2 = 0xAF, + XVIDC_EDID_EXTENSION_DTCDB_3 = 0xBF, + XVIDC_EDID_EXTENSION_BLOCK_MAP = 0xF0, /* Block Map*/ + XVIDC_EDID_EXTENSION_DDDB = 0xFF, /* Display Device Data + Block (DDDB)*/ +}; + +enum xvidc_edid_display_type { + XVIDC_EDID_DISPLAY_TYPE_MONOCHROME, + XVIDC_EDID_DISPLAY_TYPE_RGB, + XVIDC_EDID_DISPLAY_TYPE_NON_RGB, + XVIDC_EDID_DISPLAY_TYPE_UNDEFINED, +}; + +enum xvidc_edid_aspect_ratio { + XVIDC_EDID_ASPECT_RATIO_16_10, + XVIDC_EDID_ASPECT_RATIO_4_3, + XVIDC_EDID_ASPECT_RATIO_5_4, + XVIDC_EDID_ASPECT_RATIO_16_9, +}; + +enum xvidc_edid_signal_sync { + XVIDC_EDID_SIGNAL_SYNC_ANALOG_COMPOSITE, + XVIDC_EDID_SIGNAL_SYNC_BIPOLAR_ANALOG_COMPOSITE, + XVIDC_EDID_SIGNAL_SYNC_DIGITAL_COMPOSITE, + XVIDC_EDID_SIGNAL_SYNC_DIGITAL_SEPARATE, +}; + +enum xvidc_edid_stereo_mode { + XVIDC_EDID_STEREO_MODE_NONE, + XVIDC_EDID_STEREO_MODE_RESERVED, + XVIDC_EDID_STEREO_MODE_FIELD_SEQUENTIAL_RIGHT, + XVIDC_EDID_STEREO_MODE_2_WAY_INTERLEAVED_RIGHT, + XVIDC_EDID_STEREO_MODE_FIELD_SEQUENTIAL_LEFT, + XVIDC_EDID_STEREO_MODE_2_WAY_INTERLEAVED_LEFT, + XVIDC_EDID_STEREO_MODE_4_WAY_INTERLEAVED, + XVIDC_EDID_STEREO_MODE_SIDE_BY_SIDE_INTERLEAVED, +}; + +enum xvidc_edid_monitor_descriptor_type { + XVIDC_EDID_MONTIOR_DESCRIPTOR_MANUFACTURER_DEFINED = 0x0F, + XVIDC_EDID_MONITOR_DESCRIPTOR_STANDARD_TIMING_IDENTIFIERS = 0xFA, + XVIDC_EDID_MONITOR_DESCRIPTOR_COLOR_POINT = 0xFB, + XVIDC_EDID_MONITOR_DESCRIPTOR_MONITOR_NAME = 0xFC, + XVIDC_EDID_MONITOR_DESCRIPTOR_MONITOR_RANGE_LIMITS = 0xFD, + XVIDC_EDID_MONITOR_DESCRIPTOR_ASCII_STRING = 0xFE, + XVIDC_EDID_MONITOR_DESCRIPTOR_MONITOR_SERIAL_NUMBER = 0xFF, +}; + +enum xvidc_edid_secondary_timing_support { + XVIDC_EDID_SECONDARY_TIMING_NOT_SUPPORTED, + XVIDC_EDID_SECONDARY_TIMING_GFT = 0x02, +}; + + +struct __attribute__ (( packed )) xvidc_edid_detailed_timing_descriptor { + u16 pixel_clock; /* = value * 10000 */ + + u8 horizontal_active_lo; + u8 horizontal_blanking_lo; + + unsigned horizontal_blanking_hi : 4; + unsigned horizontal_active_hi : 4; + + u8 vertical_active_lo; + u8 vertical_blanking_lo; + + unsigned vertical_blanking_hi : 4; + unsigned vertical_active_hi : 4; + + u8 horizontal_sync_offset_lo; + u8 horizontal_sync_pulse_width_lo; + + unsigned vertical_sync_pulse_width_lo : 4; + unsigned vertical_sync_offset_lo : 4; + + unsigned vertical_sync_pulse_width_hi : 2; + unsigned vertical_sync_offset_hi : 2; + unsigned horizontal_sync_pulse_width_hi : 2; + unsigned horizontal_sync_offset_hi : 2; + + u8 horizontal_image_size_lo; + u8 vertical_image_size_lo; + + unsigned vertical_image_size_hi : 4; + unsigned horizontal_image_size_hi : 4; + + u8 horizontal_border; + u8 vertical_border; + + unsigned stereo_mode_lo : 1; + unsigned signal_pulse_polarity : 1; /* pulse on sync, + composite/horizontal polarity */ + unsigned signal_serration_polarity : 1; /* serrate on sync, vertical + polarity */ + unsigned signal_sync : 2; + unsigned stereo_mode_hi : 2; + unsigned interlaced : 1; +}; + +static inline u32 +xvidc_edid_detailed_timing_pixel_clock + (const struct xvidc_edid_detailed_timing_descriptor * const dtb) +{ + return dtb->pixel_clock * 10000; +} + +static inline u16 +xvidc_edid_detailed_timing_horizontal_blanking + (const struct xvidc_edid_detailed_timing_descriptor * const dtb) +{ + return (dtb->horizontal_blanking_hi << 8) | dtb->horizontal_blanking_lo; +} + +static inline u16 +xvidc_edid_detailed_timing_horizontal_active + (const struct xvidc_edid_detailed_timing_descriptor * const dtb) +{ + return (dtb->horizontal_active_hi << 8) | dtb->horizontal_active_lo; +} + +static inline u16 +xvidc_edid_detailed_timing_vertical_blanking + (const struct xvidc_edid_detailed_timing_descriptor * const dtb) +{ + return (dtb->vertical_blanking_hi << 8) | dtb->vertical_blanking_lo; +} + +static inline u16 +xvidc_edid_detailed_timing_vertical_active + (const struct xvidc_edid_detailed_timing_descriptor * const dtb) +{ + return (dtb->vertical_active_hi << 8) | dtb->vertical_active_lo; +} + +static inline u8 +xvidc_edid_detailed_timing_vertical_sync_offset + (const struct xvidc_edid_detailed_timing_descriptor * const dtb) +{ + return (dtb->vertical_sync_offset_hi << 4) | dtb->vertical_sync_offset_lo; +} + +static inline u8 +xvidc_edid_detailed_timing_vertical_sync_pulse_width + (const struct xvidc_edid_detailed_timing_descriptor * const dtb) +{ + return (dtb->vertical_sync_pulse_width_hi << 4) | + dtb->vertical_sync_pulse_width_lo; +} + +static inline u8 +xvidc_edid_detailed_timing_horizontal_sync_offset + (const struct xvidc_edid_detailed_timing_descriptor * const dtb) +{ + return (dtb->horizontal_sync_offset_hi << 4) | + dtb->horizontal_sync_offset_lo; +} + +static inline u8 +xvidc_edid_detailed_timing_horizontal_sync_pulse_width + (const struct xvidc_edid_detailed_timing_descriptor * const dtb) +{ + return (dtb->horizontal_sync_pulse_width_hi << 4) | + dtb->horizontal_sync_pulse_width_lo; +} + +static inline u16 +xvidc_edid_detailed_timing_horizontal_image_size + (const struct xvidc_edid_detailed_timing_descriptor * const dtb) +{ + return + (dtb->horizontal_image_size_hi << 8) | dtb->horizontal_image_size_lo; +} + +static inline u16 +xvidc_edid_detailed_timing_vertical_image_size + (const struct xvidc_edid_detailed_timing_descriptor * const dtb) +{ + return (dtb->vertical_image_size_hi << 8) | dtb->vertical_image_size_lo; +} + +static inline u8 +xvidc_edid_detailed_timing_stereo_mode + (const struct xvidc_edid_detailed_timing_descriptor * const dtb) +{ + return (dtb->stereo_mode_hi << 2 | dtb->stereo_mode_lo); +} + + +struct __attribute__ (( packed )) xvidc_edid_monitor_descriptor { + u16 flag0; + u8 flag1; + u8 tag; + u8 flag2; + u8 data[13]; +}; + +typedef char xvidc_edid_monitor_descriptor_string + [sizeof(((struct xvidc_edid_monitor_descriptor *)0)->data) + 1]; + + +struct __attribute__ (( packed )) xvidc_edid_monitor_range_limits { + u8 minimum_vertical_rate; /* Hz */ + u8 maximum_vertical_rate; /* Hz */ + u8 minimum_horizontal_rate; /* kHz */ + u8 maximum_horizontal_rate; /* kHz */ + u8 maximum_supported_pixel_clock; /* = (value * 10) Mhz + (round to 10 MHz) */ + + /* secondary timing formula */ + u8 secondary_timing_support; + u8 reserved; + u8 secondary_curve_start_frequency; /* horizontal frequency / 2 kHz */ + u8 c; /* = (value >> 1) */ + u16 m; + u8 k; + u8 j; /* = (value >> 1) */ +}; + + +struct __attribute__ (( packed )) xvidc_edid_standard_timing_descriptor { + u8 horizontal_active_pixels; /* = (value + 31) * 8 */ + + unsigned refresh_rate : 6; /* = value + 60 */ + unsigned image_aspect_ratio : 2; +}; + +inline u32 +xvidc_edid_standard_timing_horizontal_active +(const struct xvidc_edid_standard_timing_descriptor * const desc) { + return ((desc->horizontal_active_pixels + 31) << 3); +} + +inline u32 +xvidc_edid_standard_timing_vertical_active +(const struct xvidc_edid_standard_timing_descriptor * const desc) { + const u32 hres = xvidc_edid_standard_timing_horizontal_active(desc); + + switch (desc->image_aspect_ratio) { + case XVIDC_EDID_ASPECT_RATIO_16_10: + return ((hres * 10) >> 4); + case XVIDC_EDID_ASPECT_RATIO_4_3: + return ((hres * 3) >> 2); + case XVIDC_EDID_ASPECT_RATIO_5_4: + return ((hres << 2) / 5); + case XVIDC_EDID_ASPECT_RATIO_16_9: + return ((hres * 9) >> 4); + } + + return hres; +} + +inline u32 +xvidc_edid_standard_timing_refresh_rate +(const struct xvidc_edid_standard_timing_descriptor * const desc) { + return (desc->refresh_rate + 60); +} + + +struct __attribute__ (( packed )) edid { + /* header information */ + u8 header[8]; + + /* vendor/product identification */ + u16 manufacturer; + union { + u16 product_u16; + u8 product[2]; + }; + union { + u32 serial_number_u32; + u8 serial_number[4]; + }; + u8 manufacture_week; + u8 manufacture_year; /* = value + 1990 */ + + /* EDID version */ + u8 version; + u8 revision; + + /* basic display parameters and features */ + union { + struct __attribute__ (( packed )) { + unsigned dfp_1x : 1; /* VESA DFP 1.x */ + unsigned : 6; + unsigned digital : 1; + } digital; + struct __attribute__ (( packed )) { + unsigned vsync_serration : 1; + unsigned green_video_sync : 1; + unsigned composite_sync : 1; + unsigned separate_sync : 1; + unsigned blank_to_black_setup : 1; + unsigned signal_level_standard : 2; + unsigned digital : 1; + } analog; + } video_input_definition; + + u8 maximum_horizontal_image_size; /* cm */ + u8 maximum_vertical_image_size; /* cm */ + + u8 display_transfer_characteristics; /* gamma = (value + 100) / 100 */ + + struct __attribute__ (( packed )) { + unsigned default_gtf : 1; /* generalised timing + formula */ + unsigned preferred_timing_mode : 1; + unsigned standard_default_color_space : 1; + unsigned display_type : 2; + unsigned active_off : 1; + unsigned suspend : 1; + unsigned standby : 1; + } feature_support; + + /* color characteristics block */ + unsigned green_y_low : 2; + unsigned green_x_low : 2; + unsigned red_y_low : 2; + unsigned red_x_low : 2; + + unsigned white_y_low : 2; + unsigned white_x_low : 2; + unsigned blue_y_low : 2; + unsigned blue_x_low : 2; + + u8 red_x; + u8 red_y; + u8 green_x; + u8 green_y; + u8 blue_x; + u8 blue_y; + u8 white_x; + u8 white_y; + + /* established timings */ + struct __attribute__ (( packed )) { + unsigned timing_800x600_60 : 1; + unsigned timing_800x600_56 : 1; + unsigned timing_640x480_75 : 1; + unsigned timing_640x480_72 : 1; + unsigned timing_640x480_67 : 1; + unsigned timing_640x480_60 : 1; + unsigned timing_720x400_88 : 1; + unsigned timing_720x400_70 : 1; + + unsigned timing_1280x1024_75 : 1; + unsigned timing_1024x768_75 : 1; + unsigned timing_1024x768_70 : 1; + unsigned timing_1024x768_60 : 1; + unsigned timing_1024x768_87 : 1; + unsigned timing_832x624_75 : 1; + unsigned timing_800x600_75 : 1; + unsigned timing_800x600_72 : 1; + } established_timings; + + struct __attribute__ (( packed )) { + unsigned reserved : 7; + unsigned timing_1152x870_75 : 1; + } manufacturer_timings; + + /* standard timing id */ + struct xvidc_edid_standard_timing_descriptor standard_timing_id[8]; + + /* detailed timing */ + union { + struct xvidc_edid_monitor_descriptor monitor; + struct xvidc_edid_detailed_timing_descriptor timing; + } detailed_timings[4]; + + u8 extensions; + u8 checksum; +}; + +static inline void +xvidc_edid_manufacturer(const struct edid * const edid, char manufacturer[4]) +{ + manufacturer[0] = '@' + ((edid->manufacturer & 0x007c) >> 2); + manufacturer[1] = '@' + ((((edid->manufacturer & 0x0003) >> 00) << 3) | (((edid->manufacturer & 0xe000) >> 13) << 0)); + manufacturer[2] = '@' + ((edid->manufacturer & 0x1f00) >> 8); + manufacturer[3] = '\0'; +} + +static inline double +xvidc_edid_gamma(const struct edid * const edid) +{ + return (edid->display_transfer_characteristics + 100) / 100.0; +} + +static inline bool +xvidc_edid_detailed_timing_is_monitor_descriptor(const struct edid * const edid, + const u8 timing) +{ + const struct xvidc_edid_monitor_descriptor * const mon = + &edid->detailed_timings[timing].monitor; + + Xil_AssertNonvoid(timing < ARRAY_SIZE(edid->detailed_timings)); + + return mon->flag0 == 0x0000 && mon->flag1 == 0x00 && mon->flag2 == 0x00; +} + + +struct __attribute__ (( packed )) xvidc_edid_color_characteristics_data { + struct { + u16 x; + u16 y; + } red, green, blue, white; +}; + +static inline struct xvidc_edid_color_characteristics_data +xvidc_edid_color_characteristics(const struct edid * const edid) +{ + const struct xvidc_edid_color_characteristics_data characteristics = { + .red = { + .x = (edid->red_x << 2) | edid->red_x_low, + .y = (edid->red_y << 2) | edid->red_y_low, + }, + .green = { + .x = (edid->green_x << 2) | edid->green_x_low, + .y = (edid->green_y << 2) | edid->green_y_low, + }, + .blue = { + .x = (edid->blue_x << 2) | edid->blue_x_low, + .y = (edid->blue_y << 2) | edid->blue_y_low, + }, + .white = { + .x = (edid->white_x << 2) | edid->white_x_low, + .y = (edid->white_y << 2) | edid->white_y_low, + }, + }; + + return characteristics; +} + + +struct __attribute__ (( packed )) xvidc_edid_block_map { + u8 tag; + u8 extension_tag[126]; + u8 checksum; +}; + + +struct __attribute__ (( packed )) xvidc_edid_extension { + u8 tag; + u8 revision; + u8 extension_data[125]; + u8 checksum; +}; + + +static inline bool +xvidc_edid_verify_checksum(const u8 * const block) +{ + u8 checksum = 0; + int i; + + for (i = 0; i < XVIDC_EDID_BLOCK_SIZE; i++) + checksum += block[i]; + + return (checksum == 0); +} + +static inline double +xvidc_edid_decode_fixed_point(u16 value) +{ + double result = 0.0; + + Xil_AssertNonvoid((~value & 0xfc00) == 0xfc00); + /* edid fraction is 10 bits */ + + for (u8 i = 0; value && (i < 10); i++, value >>= 1) + result = result + ((value & 0x1) * (1.0 / (1 << (10 - i)))); + + return result; +} + +typedef enum { + XVIDC_VERBOSE_DISABLE, + XVIDC_VERBOSE_ENABLE +} XV_VidC_Verbose; + +typedef enum { + XVIDC_ISDVI, + XVIDC_ISHDMI +} XV_VidC_IsHdmi; + +typedef enum { + XVIDC_NOT_SUPPORTED, + XVIDC_SUPPORTED +} XV_VidC_Supp; +#if XVIDC_EDID_VERBOSITY > 1 +typedef struct { + u32 Integer; + u32 Decimal; +} XV_VidC_DoubleRep; +#endif + +typedef struct { + u8 width; + u8 height; +} XV_VidC_PicAspectRatio; + +typedef struct { + u16 hres; + u16 vres; + u16 htotal; + u16 vtotal; + XVidC_VideoFormat vidfrmt; + u32 pixclk; + u16 hsync_width; + u16 vsync_width; + u16 hfp; + u16 vfp; + u8 vfreq; + XV_VidC_PicAspectRatio aspect_ratio; + unsigned hsync_polarity : 1; + unsigned vsync_polarity : 1; +} XV_VidC_TimingParam; + +typedef struct { + /*Checks whether Sink able to support HDMI*/ + XV_VidC_IsHdmi IsHdmi; + /*Color Space Support*/ + XV_VidC_Supp IsYCbCr444Supp; + XV_VidC_Supp IsYCbCr420Supp; + XV_VidC_Supp IsYCbCr422Supp; + /*YCbCr444/YCbCr422/RGB444 Deep Color Support*/ + XV_VidC_Supp IsYCbCr444DeepColSupp; + XV_VidC_Supp Is30bppSupp; + XV_VidC_Supp Is36bppSupp; + XV_VidC_Supp Is48bppSupp; + /*YCbCr420 Deep Color Support*/ + XV_VidC_Supp IsYCbCr420dc30bppSupp; + XV_VidC_Supp IsYCbCr420dc36bppSupp; + XV_VidC_Supp IsYCbCr420dc48bppSupp; + /*SCDC and SCDC ReadRequest Support*/ + XV_VidC_Supp IsSCDCReadRequestReady; + XV_VidC_Supp IsSCDCPresent; + /*Sink Capability Support*/ + u8 MaxFrameRateSupp; + u16 MaxTmdsMhz; + /*CEA 861 Supported VIC Support*/ + u8 SuppCeaVIC[32]; + /*VESA Sink Preffered Timing Support*/ + XV_VidC_TimingParam PreferedTiming[4]; +} XV_VidC_EdidCntrlParam; + + +XV_VidC_TimingParam +XV_VidC_timing + (const struct xvidc_edid_detailed_timing_descriptor * const dtb); +#if XVIDC_EDID_VERBOSITY > 1 +XV_VidC_DoubleRep Double2Int (double in_val); +#endif +void XV_VidC_EdidCtrlParamInit (XV_VidC_EdidCntrlParam *EdidCtrlParam); + +void +XV_VidC_parse_edid(const u8 * const data, + XV_VidC_EdidCntrlParam *EdidCtrlParam, + XV_VidC_Verbose VerboseEn); + +#ifdef __cplusplus +} +#endif +#endif diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/video_common_v4_3/src/xvidc_parse_edid.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/video_common_v4_3/src/xvidc_parse_edid.c new file mode 100644 index 000000000..6b0edb61c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/video_common_v4_3/src/xvidc_parse_edid.c @@ -0,0 +1,1332 @@ +/* vim: set et fde fdm=syntax ft=c.doxygen ts=4 sts=4 sw=4 : */ +/* + * Copyright © 2011 Saleem Abdulrasool . + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO + * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include "string.h" +#include "stdlib.h" +#include "stddef.h" + +#include "xil_types.h" +#include "xstatus.h" +#include "xil_exception.h" + +#include "xvidc_edid_ext.h" + +#if XVIDC_EDID_VERBOSITY > 1 +#include "math.h" + +#define CM_2_MM(cm) ((cm) * 10) +#define CM_2_IN(cm) ((cm) * 0.3937) +#endif +#if XVIDC_EDID_VERBOSITY > 0 +#define HZ_2_MHZ(hz) ((hz) / 1000000) +#endif +#if XVIDC_EDID_VERBOSITY > 1 +static void +xvidc_disp_cea861_audio_data( + const struct xvidc_cea861_audio_data_block * const adb, + XV_VidC_EdidCntrlParam *EdidCtrlParam, + XV_VidC_Verbose VerboseEn); + +static void +xvidc_disp_cea861_speaker_allocation_data( + const struct xvidc_cea861_speaker_allocation_data_block * const sadb, + XV_VidC_EdidCntrlParam *EdidCtrlParam, + XV_VidC_Verbose VerboseEn); + +static void +xvidc_disp_cea861_video_data( + const struct xvidc_cea861_video_data_block * const vdb, + XV_VidC_EdidCntrlParam *EdidCtrlParam, + XV_VidC_Verbose VerboseEn); +#endif + +static void +xvidc_disp_cea861_extended_data( + const struct xvidc_cea861_extended_data_block * const edb, + XV_VidC_EdidCntrlParam *EdidCtrlParam, + XV_VidC_Verbose VerboseEn); + +static void +xvidc_disp_cea861_vendor_data( + const struct xvidc_cea861_vendor_specific_data_block * vsdb, + XV_VidC_EdidCntrlParam *EdidCtrlParam, + XV_VidC_Verbose VerboseEn); + +static void +xvidc_disp_cea861(const struct xvidc_edid_extension * const ext, + XV_VidC_EdidCntrlParam *EdidCtrlParam, + XV_VidC_Verbose VerboseEn); + +static void +xvidc_disp_edid1(const struct edid * const edid, + XV_VidC_EdidCntrlParam *EdidCtrlParam, + XV_VidC_Verbose VerboseEn); + +/*****************************************************************************/ +/** +* +* This function parse EDID on General Data & VESA Data +* +* @param data is a pointer to the EDID array. +* @param EdidCtrlParam is a pointer the EDID Control parameter +* @param VerboseEn is a pointer to the XV_HdmiTxSs core instance. +* +* @return None +* +* @note API Define below here are CEA861 routines +* +******************************************************************************/ +static void +xvidc_disp_edid1(const struct edid * const edid, + XV_VidC_EdidCntrlParam *EdidCtrlParam, + XV_VidC_Verbose VerboseEn) +{ + const struct xvidc_edid_monitor_range_limits *monitor_range_limits = NULL; + xvidc_edid_monitor_descriptor_string monitor_serial_number = {0}; + xvidc_edid_monitor_descriptor_string monitor_model_name = {0}; + bool has_ascii_string = false; + char manufacturer[4] = {0}; +#if XVIDC_EDID_VERBOSITY > 1 + XV_VidC_DoubleRep min_doubleval; + XV_VidC_DoubleRep max_doubleval; +#endif + + u8 i; +#if XVIDC_EDID_VERBOSITY > 0 + //add by mmo + XV_VidC_TimingParam timing_params; +#endif + +#if XVIDC_EDID_VERBOSITY > 1 + struct xvidc_edid_color_characteristics_data characteristics; + const u8 vlen = edid->maximum_vertical_image_size; + const u8 hlen = edid->maximum_horizontal_image_size; + + + static const char * const display_type[] = { + [XVIDC_EDID_DISPLAY_TYPE_MONOCHROME] = "Monochrome or greyscale", + [XVIDC_EDID_DISPLAY_TYPE_RGB] = "sRGB colour", + [XVIDC_EDID_DISPLAY_TYPE_NON_RGB] = "Non-sRGB colour", + [XVIDC_EDID_DISPLAY_TYPE_UNDEFINED] = "Undefined", + }; +#endif + xvidc_edid_manufacturer(edid, manufacturer); + + for (i = 0; i < ARRAY_SIZE(edid->detailed_timings); i++) { + const struct xvidc_edid_monitor_descriptor * const mon = + &edid->detailed_timings[i].monitor; + + if (!xvidc_edid_detailed_timing_is_monitor_descriptor(edid, i)) + continue; + + switch (mon->tag) { + case XVIDC_EDID_MONTIOR_DESCRIPTOR_MANUFACTURER_DEFINED: + /* This is arbitrary data, just silently ignore it. */ + break; + case XVIDC_EDID_MONITOR_DESCRIPTOR_ASCII_STRING: + has_ascii_string = true; + break; + case XVIDC_EDID_MONITOR_DESCRIPTOR_MONITOR_NAME: + strncpy(monitor_model_name, (char *) mon->data, + sizeof(monitor_model_name) - 1); + break; + case XVIDC_EDID_MONITOR_DESCRIPTOR_MONITOR_RANGE_LIMITS: + monitor_range_limits = + (struct xvidc_edid_monitor_range_limits *) &mon->data; + break; + case XVIDC_EDID_MONITOR_DESCRIPTOR_MONITOR_SERIAL_NUMBER: + strncpy(monitor_serial_number, (char *) mon->data, + sizeof(monitor_serial_number) - 1); + break; + default: + if (VerboseEn) { + xil_printf("unknown monitor descriptor type 0x%02x\n", + mon->tag); + } + break; + } + } + +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { + xil_printf("Sink Information\r\n"); + + xil_printf(" Model name............... %s\r\n", + *monitor_model_name ? monitor_model_name : "n/a"); +#if XVIDC_EDID_VERBOSITY > 1 + xil_printf(" Manufacturer............. %s\r\n", + manufacturer); + + xil_printf(" Product code............. %u\r\n", + (u16) edid->product_u16); + + if (*(u32 *) edid->serial_number_u32) + xil_printf(" Module serial number..... %u\r\n", + (u32) edid->serial_number_u32); +#endif +#if defined(DISPLAY_UNKNOWN) + xil_printf(" Plug and Play ID......... %s\r\n", NULL); +#endif +#if XVIDC_EDID_VERBOSITY > 1 + xil_printf(" Serial number............ %s\r\n", + *monitor_serial_number ? monitor_serial_number : "n/a"); + + xil_printf(" Manufacture date......... %u", + edid->manufacture_year + 1990); + if (edid->manufacture_week <= 52) + xil_printf(", ISO week %u", edid->manufacture_week); + xil_printf("\r\n"); +#endif + xil_printf(" EDID revision............ %u.%u\r\n", + edid->version, edid->revision); +#if XVIDC_EDID_VERBOSITY > 1 + xil_printf(" Input signal type........ %s\r\n", + edid->video_input_definition.digital.digital ? "Digital" : "Analog"); + + if (edid->video_input_definition.digital.digital) { + xil_printf(" VESA DFP 1.x supported... %s\r\n", + edid->video_input_definition.digital.dfp_1x ? "Yes" : "No"); + } else { + /* Missing Piece: To print analog flags */ + } +#endif +#if defined(DISPLAY_UNKNOWN) + xil_printf(" Color bit depth.......... %s\r\n", NULL); +#endif +#if XVIDC_EDID_VERBOSITY > 1 + xil_printf(" Display type............. %s\r\n", + display_type[edid->feature_support.display_type]); + + xil_printf(" Screen size.............. %u mm x %u mm (%.1f in)\r\n", + CM_2_MM(hlen), CM_2_MM(vlen), + CM_2_IN(sqrt(hlen * hlen + vlen * vlen))); + + xil_printf(" Power management......... %s%s%s%s\r\n", + edid->feature_support.active_off ? "Active off, " : "", + edid->feature_support.suspend ? "Suspend, " : "", + edid->feature_support.standby ? "Standby, " : "", + + (edid->feature_support.active_off || + edid->feature_support.suspend || + edid->feature_support.standby) ? "\b\b " : "n/a"); +#endif + xil_printf(" Extension blocks......... %u\r\n", + edid->extensions); + +#if defined(DISPLAY_UNKNOWN) + xil_printf(" DDC/CI................... %s\r\n", NULL); +#endif + + xil_printf("\r\n"); + } +#endif + if (has_ascii_string) { + if (VerboseEn) { +#if XVIDC_EDID_VERBOSITY > 1 + xil_printf("General purpose ASCII string\r\n"); +#endif + } + + for (i = 0; i < ARRAY_SIZE(edid->detailed_timings); i++) { + if (!xvidc_edid_detailed_timing_is_monitor_descriptor(edid, i)) + continue; + } + + if (VerboseEn) { +#if XVIDC_EDID_VERBOSITY > 1 + xil_printf("\r\n"); +#endif + } + } +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { + xil_printf("Color characteristics\r\n"); + + xil_printf(" Default color space...... %ssRGB\r\n", + edid->feature_support.standard_default_color_space ? "":"Non-"); +#if XVIDC_EDID_VERBOSITY > 1 + min_doubleval = + Double2Int(xvidc_edid_gamma(edid)); + xil_printf(" Display gamma............ %d.%03d\r\n", + min_doubleval.Integer, min_doubleval.Decimal); + + characteristics = xvidc_edid_color_characteristics(edid); + + min_doubleval = + Double2Int(xvidc_edid_decode_fixed_point(characteristics.red.x)); + max_doubleval = + Double2Int(xvidc_edid_decode_fixed_point(characteristics.red.y)); + + xil_printf(" Red chromaticity......... Rx %d.%03d - Ry %d.%03d\r\n", + min_doubleval.Integer, min_doubleval.Decimal, + max_doubleval.Integer, max_doubleval.Decimal); + + min_doubleval = + Double2Int(xvidc_edid_decode_fixed_point(characteristics.green.x)); + max_doubleval = + Double2Int(xvidc_edid_decode_fixed_point(characteristics.green.y)); + + xil_printf(" Green chromaticity....... Gx %d.%03d - Gy %d.%03d\r\n", + min_doubleval.Integer, min_doubleval.Decimal, + max_doubleval.Integer, max_doubleval.Decimal); + + min_doubleval = + Double2Int(xvidc_edid_decode_fixed_point(characteristics.blue.x)); + max_doubleval = + Double2Int(xvidc_edid_decode_fixed_point(characteristics.blue.y)); + + xil_printf(" Blue chromaticity........ Bx %d.%03d - By %d.%03d\r\n", + min_doubleval.Integer, min_doubleval.Decimal, + max_doubleval.Integer, max_doubleval.Decimal); + + min_doubleval = + Double2Int(xvidc_edid_decode_fixed_point(characteristics.white.x)); + max_doubleval = + Double2Int(xvidc_edid_decode_fixed_point(characteristics.white.y)); + + xil_printf(" White point (default).... Wx %d.%03d - Wy %d.%03d\r\n", + min_doubleval.Integer, min_doubleval.Decimal, + max_doubleval.Integer, max_doubleval.Decimal); +#endif +#if defined(DISPLAY_UNKNOWN) + xil_printf(" Additional descriptors... %s\r\n", NULL); +#endif + xil_printf("\r\n"); + + xil_printf("VESA Timing characteristics\r\n"); + } +#endif + if (monitor_range_limits) { +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { + xil_printf(" Horizontal scan range.... %u - %u kHz\r\n", + monitor_range_limits->minimum_horizontal_rate, + monitor_range_limits->maximum_horizontal_rate); + + xil_printf(" Vertical scan range...... %u - %u Hz\r\n", + monitor_range_limits->minimum_vertical_rate, + monitor_range_limits->maximum_vertical_rate); + + xil_printf(" Video bandwidth.......... %u MHz\r\n", + monitor_range_limits->maximum_supported_pixel_clock * 10); + } +#endif + EdidCtrlParam->MaxFrameRateSupp = + monitor_range_limits->maximum_vertical_rate; + EdidCtrlParam->MaxTmdsMhz = + (monitor_range_limits->maximum_supported_pixel_clock * 10); + } + +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { +#if defined(DISPLAY_UNKNOWN) + xil_printf(" CVT standard............. %s\r\n", NULL); +#endif +#if XVIDC_EDID_VERBOSITY > 1 + xil_printf(" GTF standard............. %sSupported\r\n", + edid->feature_support.default_gtf ? "" : "Not "); +#endif +#if defined(DISPLAY_UNKNOWN) + xil_printf(" Additional descriptors... %s\r\n", NULL); +#endif +#if XVIDC_EDID_VERBOSITY > 0 + xil_printf(" Preferred timing......... %s\r\n", + edid->feature_support.preferred_timing_mode ? "Yes" : "No"); +#endif + for (i = 0; i < ARRAY_SIZE(edid->detailed_timings); i++) { + if (xvidc_edid_detailed_timing_is_monitor_descriptor(edid, i)) + continue; + + timing_params = XV_VidC_timing(&edid->detailed_timings[i].timing); + EdidCtrlParam->PreferedTiming[i] = + XV_VidC_timing(&edid->detailed_timings[i].timing); +#if XVIDC_EDID_VERBOSITY > 0 + if (edid->feature_support.preferred_timing_mode) { + xil_printf(" Native/preferred timing.. %ux%u%c at %uHz" + " (%u:%u)\r\n", + timing_params.hres, + timing_params.vres, + timing_params.vidfrmt ? 'i' : 'p', + timing_params.vfreq, + timing_params.aspect_ratio.width, + timing_params.aspect_ratio.height); + xil_printf(" Modeline............... \"%ux%u\" %u %u %u %u" + " %u %u %u %u %u %chsync %cvsync\r\n", + timing_params.hres, + timing_params.vres, + HZ_2_MHZ (timing_params.pixclk), + (timing_params.hres), + (timing_params.hres + timing_params.hfp), + (timing_params.hres + timing_params.hfp + + timing_params.hsync_width), + (timing_params.htotal), + (timing_params.vres), + (timing_params.vres + timing_params.vfp), + (timing_params.vres + timing_params.vfp + + timing_params.vsync_width), + (timing_params.vtotal), + timing_params.hsync_polarity ? '+' : '-', + timing_params.vsync_polarity ? '+' : '-'); + } else { + xil_printf(" Native/preferred timing.. n/a\r\n"); + } +#endif + } +#if XVIDC_EDID_VERBOSITY > 0 + xil_printf("\r\n"); +#endif +#if XVIDC_EDID_VERBOSITY > 1 + xil_printf("Established Timings supported\r\n"); + if (edid->established_timings.timing_720x400_70) + xil_printf(" 720 x 400p @ 70Hz - IBM VGA\r\n"); + if (edid->established_timings.timing_720x400_88) + xil_printf(" 720 x 400p @ 88Hz - IBM XGA2\r\n"); + if (edid->established_timings.timing_640x480_60) + xil_printf(" 640 x 480p @ 60Hz - IBM VGA\r\n"); + if (edid->established_timings.timing_640x480_67) + xil_printf(" 640 x 480p @ 67Hz - Apple Mac II\r\n"); + if (edid->established_timings.timing_640x480_72) + xil_printf(" 640 x 480p @ 72Hz - VESA\r\n"); + if (edid->established_timings.timing_640x480_75) + xil_printf(" 640 x 480p @ 75Hz - VESA\r\n"); + if (edid->established_timings.timing_800x600_56) + xil_printf(" 800 x 600p @ 56Hz - VESA\r\n"); + if (edid->established_timings.timing_800x600_60) + xil_printf(" 800 x 600p @ 60Hz - VESA\r\n"); + + if (edid->established_timings.timing_800x600_72) + xil_printf(" 800 x 600p @ 72Hz - VESA\r\n"); + if (edid->established_timings.timing_800x600_75) + xil_printf(" 800 x 600p @ 75Hz - VESA\r\n"); + if (edid->established_timings.timing_832x624_75) + xil_printf(" 832 x 624p @ 75Hz - Apple Mac II\r\n"); + if (edid->established_timings.timing_1024x768_87) + xil_printf(" 1024 x 768i @ 87Hz - VESA\r\n"); + if (edid->established_timings.timing_1024x768_60) + xil_printf(" 1024 x 768p @ 60Hz - VESA\r\n"); + if (edid->established_timings.timing_1024x768_70) + xil_printf(" 1024 x 768p @ 70Hz - VESA\r\n"); + if (edid->established_timings.timing_1024x768_75) + xil_printf(" 1024 x 768p @ 75Hz - VESA\r\n"); + if (edid->established_timings.timing_1280x1024_75) + xil_printf(" 1280 x 1024p @ 75Hz - VESA\r\n"); +#endif + } +#endif + +#if XVIDC_EDID_VERBOSITY > 1 + if (VerboseEn) { + xil_printf("Standard Timings supported\r\n"); + for (i = 0; i < ARRAY_SIZE(edid->standard_timing_id); i++) { + const struct xvidc_edid_standard_timing_descriptor * const desc = + &edid->standard_timing_id[i]; + + if (!memcmp(desc, XVIDC_EDID_STANDARD_TIMING_DESCRIPTOR_INVALID, + sizeof(*desc))) + { + continue; + } else { + if (((desc->horizontal_active_pixels + 31)* 8) >= 1000) { + xil_printf(" %u x",(desc->horizontal_active_pixels + 31)* 8); + } else { + xil_printf(" %u x",(desc->horizontal_active_pixels + 31)* 8); + } + switch (desc->image_aspect_ratio) { + case 0: //Aspect Ratio = 16:10 + xil_printf(" %up ", + (((desc->horizontal_active_pixels + 31)* 8) * 10) / 16); + break; + case 1: //Aspect Ratio = 4:3 + xil_printf(" %up ", + (((desc->horizontal_active_pixels + 31)* 8) * 3) / 4); + break; + case 2: //Aspect Ratio = 5:4 + xil_printf(" %up ", + (((desc->horizontal_active_pixels + 31)* 8) * 4) / 5); + break; + case 3: //Aspect Ratio = 16:9 + xil_printf(" %up ", + (((desc->horizontal_active_pixels + 31)* 8) * 9) / 16); + break; + default: //Aspect Ratio = 16:10 + xil_printf(" %up ", + (((desc->horizontal_active_pixels + 31)* 8) * 10) / 16); + break; + } + xil_printf("@ %uHz\r\n",(desc->refresh_rate + 60)); + } + } + } +#endif +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { + xil_printf("\r\n"); + } +#endif +} + + + +/*****************************************************************************/ +/** +* +* This function parse EDID on CEA 861 Audio Data +* +* @param data is a pointer to the EDID array. +* @param EdidCtrlParam is a pointer the EDID Control parameter +* @param VerboseEn is a pointer to the XV_HdmiTxSs core instance. +* +* @return None +* +* @note API Define below here are CEA861 routines +* +******************************************************************************/ +#if XVIDC_EDID_VERBOSITY > 1 +static void +xvidc_disp_cea861_audio_data( + const struct xvidc_cea861_audio_data_block * const adb, + XV_VidC_EdidCntrlParam *EdidCtrlParam, + XV_VidC_Verbose VerboseEn) { + /* For Future Usage */ + EdidCtrlParam = EdidCtrlParam; + + const u8 descriptors = adb->header.length / sizeof(*adb->sad); +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { + xil_printf("CE audio data (formats supported)\r\n"); + } +#endif + for (u8 i = 0; i < descriptors; i++) { + const struct xvidc_cea861_short_audio_descriptor * const sad = + (struct xvidc_cea861_short_audio_descriptor *) &adb->sad[i]; + + switch (sad->audio_format) { + case XVIDC_CEA861_AUDIO_FORMAT_LPCM: +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { + xil_printf(" LPCM %u-channel, %s%s%s\b%s", + sad->channels + 1, + sad->flags.lpcm.bitrate_16_bit ? "16/" : "", + sad->flags.lpcm.bitrate_20_bit ? "20/" : "", + sad->flags.lpcm.bitrate_24_bit ? "24/" : "", + + ((sad->flags.lpcm.bitrate_16_bit + + sad->flags.lpcm.bitrate_20_bit + + sad->flags.lpcm.bitrate_24_bit) > 1) ? + " bit depths" : "-bit"); + } +#endif + break; + case XVIDC_CEA861_AUDIO_FORMAT_AC_3: +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { + xil_printf(" AC-3 %u-channel, %4uk max. bit rate", + sad->channels + 1, + (sad->flags.maximum_bit_rate << 3)); + } +#endif + break; + default: +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { + xil_printf("Unknown audio format 0x%02x\r\n", + sad->audio_format); + } +#endif + continue; + } +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { + xil_printf(" at %s%s%s%s%s%s%s\b kHz\r\n", + sad->sample_rate_32_kHz ? "32/" : "", + sad->sample_rate_44_1_kHz ? "44.1/" : "", + sad->sample_rate_48_kHz ? "48/" : "", + sad->sample_rate_88_2_kHz ? "88.2/" : "", + sad->sample_rate_96_kHz ? "96/" : "", + sad->sample_rate_176_4_kHz ? "176.4/" : "", + sad->sample_rate_192_kHz ? "192/" : ""); + } +#endif + } +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { + xil_printf("\r\n"); + } +#endif +} +#endif + +/*****************************************************************************/ +/** +* +* This function parse EDID on CEA 861 Extended Data +* +* @param data is a pointer to the EDID array. +* @param EdidCtrlParam is a pointer the EDID Control parameter +* @param VerboseEn is a pointer to the XV_HdmiTxSs core instance. +* +* @return None +* +* @note None. +* +******************************************************************************/ +static void +xvidc_disp_cea861_extended_data( + const struct xvidc_cea861_extended_data_block * const edb, + XV_VidC_EdidCntrlParam *EdidCtrlParam, + XV_VidC_Verbose VerboseEn) { + + /* During Verbosity 0, VerboseEn won't be used */ + /* To avoid compilation warnings */ + VerboseEn = VerboseEn; + +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { + xil_printf("CEA Extended Tags\r\n"); + } +#endif + switch(edb->xvidc_cea861_extended_tag_codes) { +#if XVIDC_EDID_VERBOSITY > 1 + case XVIDC_CEA861_EXT_TAG_TYPE_VIDEO_CAPABILITY: + if (VerboseEn) { + xil_printf(" Video capability data block\r\n"); + } + break; + + case XVIDC_CEA861_EXT_TAG_TYPE_VENDOR_SPECIFIC: + if (VerboseEn) { + xil_printf(" Vendor-specific video data block\r\n"); + } + break; + + case XVIDC_CEA861_EXT_TAG_TYPE_VESA_DISPLAY_DEVICE: + if (VerboseEn) { + xil_printf(" VESA video display device data block\r\n"); + } + break; + + case XVIDC_CEA861_EXT_TAG_TYPE_VESA_VIDEO_TIMING_BLOCK_EXT: + if (VerboseEn) { + xil_printf("VESA video timing block extension\r\n"); + } + break; + + case XVIDC_CEA861_EXT_TAG_TYPE_RESERVED_FOR_HDMI_VIDEO_DATA_BLOCK: + if (VerboseEn) { + xil_printf("Reserved for HDMI video data block\r\n"); + } + break; + + case XVIDC_CEA861_EXT_TAG_TYPE_COLORIMETRY: + if (VerboseEn) { + xil_printf(" Colorimetry data block\r\n"); + } + break; + + case XVIDC_CEA861_EXT_TAG_TYPE_HDR_STATIC_METADATA: + if (VerboseEn) { + xil_printf("HDR static metadata data block\r\n"); + } + break; + + case XVIDC_CEA861_EXT_TAG_TYPE_HDR_DYNAMIC_METADATA: + if (VerboseEn) { + xil_printf(" HDR dynamic metadata data block\r\n"); + } + break; + + case XVIDC_CEA861_EXT_TAG_TYPE_VIDEO_FRMT_PREFERENCE: + if (VerboseEn) { + xil_printf(" Video format preference data block\r\n"); + } + break; + + case XVIDC_CEA861_EXT_TAG_TYPE_CEA_MISC_AUDIO_FIELDS: + if (VerboseEn) { + xil_printf("Reserved for CEA miscellaneous audio fields\r\n"); + } + break; + + case XVIDC_CEA861_EXT_TAG_TYPE_VENDOR_SPECIFC_AUDIO: + if (VerboseEn) { + xil_printf(" Vendor-specific audio data block\r\n\r\n"); + } + break; + + case XVIDC_CEA861_EXT_TAG_TYPE_HDMI_AUDIO: + if (VerboseEn) { + xil_printf(" HDMI audio data block\r\n"); + } + break; + + case XVIDC_CEA861_EXT_TAG_TYPE_ROOM_CONFIGURATION: + if (VerboseEn) { + xil_printf(" Room configuration data block\r\n"); + } + break; + + case XVIDC_CEA861_EXT_TAG_TYPE_SPEAKER_LOCATION: + if (VerboseEn) { + xil_printf(" Speaker location data block\r\n"); + } + break; + + case XVIDC_CEA861_EXT_TAG_TYPE_INFOFRAME: + if (VerboseEn) { + xil_printf(" Video capability data block\r\n"); + } + break; +#endif + case XVIDC_CEA861_EXT_TAG_TYPE_YCBCR420_VIDEO: +#if XVIDC_EDID_VERBOSITY > 1 + if (VerboseEn) { + xil_printf(" YCbCr 4:2:0 video data block\r\n"); + xil_printf(" YCbCr 4:2:0.............. Supported\r\n"); + } +#endif + EdidCtrlParam->IsYCbCr420Supp = XVIDC_SUPPORTED; + +#if XVIDC_EDID_VERBOSITY > 1 + if (VerboseEn) { + xil_printf(" CE video identifiers (VICs) - " + " timing/formats supported\r\n"); + } + for (u8 i = 0; i < edb->header.length - 1; i++) { + u8 vic; + u8 native=0; + if ((edb->data[i] & 0x7F) == 0) { + continue; + } else if (((edb->data[i]) >= 1) && ((edb->data[i]) <= 64)){ + vic = (edb->data[i]) & 0x7F; + } else if (((edb->data[i]) >= 65) && ((edb->data[i]) <= 127)){ + vic = (edb->data[i]); + } else if (((edb->data[i]) >= 129) && ((edb->data[i]) <= 192)){ + vic = (edb->data[i]) & 0x7F; + native = 1; + } else if (((edb->data[i]) >= 193) && ((edb->data[i]) <= 253)){ + vic = (edb->data[i]); + } else { + continue; + } + + const struct xvidc_cea861_timing * const timing = + &xvidc_cea861_timings[vic]; + + if (VerboseEn) { + xil_printf(" %s CEA Mode %02u: %4u x %4u%c @ %dHz\r\n", + native ? "*" : " ", + vic, + timing->hactive, timing->vactive, + (timing->mode == INTERLACED) ? 'i' : 'p', + (u32)(timing->vfreq)); + } + } + if (VerboseEn) { + xil_printf("\r\n"); + } +#endif + break; + + case XVIDC_CEA861_EXT_TAG_TYPE_YCBCR420_CAPABILITY_MAP: +#if XVIDC_EDID_VERBOSITY > 1 + if (VerboseEn) { + xil_printf(" YCbCr 4:2:0 capability map data block\r\n"); + xil_printf(" YCbCr 4:2:0.............. Supported\r\n"); + } +#endif + EdidCtrlParam->IsYCbCr420Supp = XVIDC_SUPPORTED; +#if XVIDC_EDID_VERBOSITY > 1 + for (u8 i = 0; i < edb->header.length - 1; i++) { + u8 v = edb->data[i]; + + for (u8 j = 0; j < 8; j++) { + if (v & (1 << j)) { + if (VerboseEn) { + const struct xvidc_cea861_timing * const timing = + &xvidc_cea861_timings[EdidCtrlParam->SuppCeaVIC[(i * 8) + j]]; + xil_printf(" CEA Mode %02u: %4u x %4u%c" + "@ %dHz\r\n", + EdidCtrlParam->SuppCeaVIC[(i * 8) + j], + timing->hactive, timing->vactive, + (timing->mode == INTERLACED) ? 'i' : 'p', + (u32)(timing->vfreq)); + } + } + } + } +#endif +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { + xil_printf("\r\n"); + } +#endif + break; + + default : +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { +#if XVIDC_EDID_VERBOSITY > 1 + xil_printf(" Not Supported: Ext Tag: %03x\r\n", + edb->xvidc_cea861_extended_tag_codes); +#endif + xil_printf("\r\n"); + } +#endif + break; + } +} +#if XVIDC_EDID_VERBOSITY > 1 +static void +xvidc_disp_cea861_video_data( + const struct xvidc_cea861_video_data_block * const vdb, + XV_VidC_EdidCntrlParam *EdidCtrlParam, + XV_VidC_Verbose VerboseEn) { + /* For Future Usage */ + EdidCtrlParam = EdidCtrlParam; + + if (VerboseEn) { + xil_printf("CE video identifiers (VICs) - timing/formats" + " supported\r\n"); + } + + for (u8 i = 0; i < vdb->header.length; i++) { + + const struct xvidc_cea861_timing * const timing = + &xvidc_cea861_timings[vdb->svd[i].video_identification_code]; + + EdidCtrlParam->SuppCeaVIC[i] = vdb->svd[i].video_identification_code; + if (VerboseEn) { + xil_printf(" %s CEA Mode %02u: %4u x %4u%c @ %dHz\r\n", + vdb->svd[i].native ? "*" : " ", + vdb->svd[i].video_identification_code, + timing->hactive, timing->vactive, + (timing->mode == INTERLACED) ? 'i' : 'p', + (u32)(timing->vfreq)); + } + } + if (VerboseEn) { + xil_printf("\r\n"); + } +} +#endif + +/*****************************************************************************/ +/** +* +* This function parse EDID on CEA 861 Vendor Specific Data +* +* @param data is a pointer to the EDID array. +* @param EdidCtrlParam is a pointer the EDID Control parameter +* @param VerboseEn is a pointer to the XV_HdmiTxSs core instance. +* +* @return None +* +* @note None. +* +******************************************************************************/ +static void +xvidc_disp_cea861_vendor_data( + const struct xvidc_cea861_vendor_specific_data_block * vsdb, + XV_VidC_EdidCntrlParam *EdidCtrlParam, + XV_VidC_Verbose VerboseEn) { + + /* During Verbosity 0, VerboseEn won't be used */ + /* To avoid compilation warnings */ + VerboseEn = VerboseEn; + + const u8 oui[] = { vsdb->ieee_registration[2], + vsdb->ieee_registration[1], + vsdb->ieee_registration[0] }; +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { + xil_printf("CEA vendor specific data (VSDB)\r\n"); + xil_printf(" IEEE registration number. 0x"); + for (u8 i = 0; i < ARRAY_SIZE(oui); i++) + xil_printf("%02X", oui[i]); + xil_printf("\r\n"); + } +#endif + if (!memcmp(oui, HDMI_OUI, sizeof(oui))) { + const struct xvidc_cea861_hdmi_vendor_specific_data_block * const hdmi = + (struct xvidc_cea861_hdmi_vendor_specific_data_block *) vsdb; +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { + xil_printf(" CEC physical address..... %u.%u.%u.%u\r\n", + hdmi->port_configuration_a, + hdmi->port_configuration_b, + hdmi->port_configuration_c, + hdmi->port_configuration_d); + } +#endif + + if (hdmi->header.length >= HDMI_VSDB_EXTENSION_FLAGS_OFFSET) { +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { +#if XVIDC_EDID_VERBOSITY > 1 + xil_printf(" Supports AI (ACP, ISRC).. %s\r\n", + hdmi->audio_info_frame ? "Yes" : "No"); +#endif + xil_printf(" Supports 48bpp........... %s\r\n", + hdmi->colour_depth_48_bit ? "Yes" : "No"); + xil_printf(" Supports 36bpp........... %s\r\n", + hdmi->colour_depth_36_bit ? "Yes" : "No"); + xil_printf(" Supports 30bpp........... %s\r\n", + hdmi->colour_depth_30_bit ? "Yes" : "No"); + xil_printf(" Supp. YUV444 Deep Color.. %s\r\n", + hdmi->yuv_444_supported ? "Yes" : "No"); +#if XVIDC_EDID_VERBOSITY > 1 + xil_printf(" Supports dual-link DVI... %s\r\n", + hdmi->dvi_dual_link ? "Yes" : "No"); +#endif + } +#endif + EdidCtrlParam->Is30bppSupp = hdmi->colour_depth_30_bit; + EdidCtrlParam->Is36bppSupp = hdmi->colour_depth_36_bit; + EdidCtrlParam->Is48bppSupp = hdmi->colour_depth_48_bit; + EdidCtrlParam->IsYCbCr444DeepColSupp = hdmi->yuv_444_supported; + } + + if (hdmi->header.length >= HDMI_VSDB_MAX_TMDS_OFFSET) { + if (hdmi->max_tmds_clock) { +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { + xil_printf(" Maximum TMDS clock....... %uMHz\r\n", + hdmi->max_tmds_clock * 5); + } +#endif + EdidCtrlParam->MaxTmdsMhz = (hdmi->max_tmds_clock * 5); + } else { +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { + xil_printf(" Maximum TMDS clock....... n/a\r\n"); + } +#endif + } + } + + if (hdmi->header.length >= HDMI_VSDB_LATENCY_FIELDS_OFFSET) { + if (hdmi->latency_fields) { +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { + xil_printf(" Video latency %s........ %ums\r\n", + hdmi->interlaced_latency_fields ? "(p)" : "...", + (hdmi->video_latency - 1) << 1); + xil_printf(" Audio latency %s........ %ums\r\n", + hdmi->interlaced_latency_fields ? "(p)" : "...", + (hdmi->audio_latency - 1) << 1); + } +#endif + } + + if (hdmi->interlaced_latency_fields) { +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { + xil_printf(" Video latency (i)........ %ums\r\n", + hdmi->interlaced_video_latency); + xil_printf(" Audio latency (i)........ %ums\r\n", + hdmi->interlaced_audio_latency); + } +#endif + } + } + } else if (!memcmp(oui, HDMI_OUI_HF, sizeof(oui))) { + const struct xvidc_cea861_hdmi_hf_vendor_specific_data_block * const hdmi = + (struct xvidc_cea861_hdmi_hf_vendor_specific_data_block *) vsdb; + +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { + xil_printf(" Version.................. %d\r\n",hdmi->version); + } +#endif + + if (hdmi->max_tmds_char_rate) { +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { + xil_printf(" Maximum TMDS clock....... %uMHz\r\n", + hdmi->max_tmds_char_rate * 5); + } +#endif + EdidCtrlParam->MaxTmdsMhz = (hdmi->max_tmds_char_rate * 5); + } else { +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { + xil_printf(" Max. Supp. TMDS clock (<=340MHz)\r\n"); + } +#endif + } + + if (hdmi->header.length >= HDMI_VSDB_EXTENSION_FLAGS_OFFSET) { +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { +#if XVIDC_EDID_VERBOSITY > 1 + xil_printf(" RRC Capable Support...... %s\r\n", + hdmi->rr_capable ? "Yes" : "No"); + xil_printf(" SCDC Present............. %s\r\n", + hdmi->scdc_present ? "Yes" : "No"); + xil_printf(" HDMI1.4 Scramble Support. %s\r\n", + hdmi->lte_340mcsc_scramble ? "Yes" : "No"); +#endif + xil_printf(" YUV 420 Deep.C. Support..\r\n"); + xil_printf(" Supports 48bpp......... %s\r\n", + hdmi->dc_48bit_yuv420 ? "Yes" : "No"); + xil_printf(" Supports 36bpp......... %s\r\n", + hdmi->dc_36bit_yuv420 ? "Yes" : "No"); + xil_printf(" Supports 30bpp......... %s\r\n", + hdmi->dc_30bit_yuv420 ? "Yes" : "No"); + } +#endif + EdidCtrlParam->IsYCbCr420dc30bppSupp = hdmi->dc_30bit_yuv420; + EdidCtrlParam->IsYCbCr420dc36bppSupp = hdmi->dc_36bit_yuv420; + EdidCtrlParam->IsYCbCr420dc48bppSupp = hdmi->dc_48bit_yuv420; + EdidCtrlParam->IsSCDCReadRequestReady = hdmi->rr_capable; + EdidCtrlParam->IsSCDCPresent = hdmi->scdc_present; + } + } +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { + xil_printf("\r\n"); + } +#endif +} + +#if XVIDC_EDID_VERBOSITY > 1 +/*****************************************************************************/ +/** +* +* This function parse EDID on CEA 861 Speaker Allocation +* +* @param data is a pointer to the EDID array. +* @param EdidCtrlParam is a pointer the EDID Control parameter +* @param VerboseEn is a pointer to the XV_HdmiTxSs core instance. +* +* @return None +* +* @note None. +* +******************************************************************************/ +static void +xvidc_disp_cea861_speaker_allocation_data( + const struct xvidc_cea861_speaker_allocation_data_block * const sadb, + XV_VidC_EdidCntrlParam *EdidCtrlParam, + XV_VidC_Verbose VerboseEn) { + /* For Future Usage */ + EdidCtrlParam = EdidCtrlParam; + + const struct xvidc_cea861_speaker_allocation * const sa = &sadb->payload; + const u8 * const channel_configuration = (u8 *) sa; + + if (VerboseEn) { + xil_printf("CEA speaker allocation data\r\n"); + xil_printf(" Channel configuration.... %u.%u\r\n", + (__builtin_popcountll(channel_configuration[0] & 0xe9) << 1) + + (__builtin_popcountll(channel_configuration[0] & 0x14) << 0) + + (__builtin_popcountll(channel_configuration[1] & 0x01) << 1) + + (__builtin_popcountll(channel_configuration[1] & 0x06) << 0), + (channel_configuration[0] & 0x02)); + xil_printf(" Front left/right......... %s\r\n", + sa->front_left_right ? "Yes" : "No"); + xil_printf(" Front LFE................ %s\r\n", + sa->front_lfe ? "Yes" : "No"); + xil_printf(" Front center............. %s\r\n", + sa->front_center ? "Yes" : "No"); + xil_printf(" Rear left/right.......... %s\r\n", + sa->rear_left_right ? "Yes" : "No"); + xil_printf(" Rear center.............. %s\r\n", + sa->rear_center ? "Yes" : "No"); + xil_printf(" Front left/right center.. %s\r\n", + sa->front_left_right_center ? "Yes" : "No"); + xil_printf(" Rear left/right center... %s\r\n", + sa->rear_left_right_center ? "Yes" : "No"); + xil_printf(" Front left/right wide.... %s\r\n", + sa->front_left_right_wide ? "Yes" : "No"); + xil_printf(" Front left/right high.... %s\r\n", + sa->front_left_right_high ? "Yes" : "No"); + xil_printf(" Top center............... %s\r\n", + sa->top_center ? "Yes" : "No"); + xil_printf(" Front center high........ %s\r\n", + sa->front_center_high ? "Yes" : "No"); + + xil_printf("\r\n"); + } + +} +#endif + +/*****************************************************************************/ +/** +* +* This function Parse and Display the CEA-861 +* +* @param data is a pointer to the EDID array. +* @param EdidCtrlParam is a pointer the EDID Control parameter +* @param VerboseEn is a pointer to the XV_HdmiTxSs core instance. +* +* @return None +* +* @note None. +* +******************************************************************************/ +static void +xvidc_disp_cea861(const struct xvidc_edid_extension * const ext, + XV_VidC_EdidCntrlParam *EdidCtrlParam, + XV_VidC_Verbose VerboseEn) { + + const struct xvidc_cea861_timing_block * const ctb = + (struct xvidc_cea861_timing_block *) ext; + const u8 offset = offsetof(struct xvidc_cea861_timing_block, data); + u8 index = 0; + +#if XVIDC_EDID_VERBOSITY > 1 + const struct xvidc_edid_detailed_timing_descriptor *dtd = NULL; + u8 i; + + XV_VidC_TimingParam timing_params; +#endif + +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { + + xil_printf("CEA-861 Information\r\n"); + xil_printf(" Revision number.......... %u\r\n", + ctb->revision); + } +#endif + + if (ctb->revision >= 2) { +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { +#if XVIDC_EDID_VERBOSITY > 1 + xil_printf(" IT underscan............. %supported\r\n", + ctb->underscan_supported ? "S" : "Not s"); +#endif + xil_printf(" Basic audio.............. %supported\r\n", + ctb->basic_audio_supported ? "S" : "Not s"); + xil_printf(" YCbCr 4:4:4.............. %supported\r\n", + ctb->yuv_444_supported ? "S" : "Not s"); + xil_printf(" YCbCr 4:2:2.............. %supported\r\n", + ctb->yuv_422_supported ? "S" : "Not s"); +#if XVIDC_EDID_VERBOSITY > 1 + xil_printf(" Native formats........... %u\r\n", + ctb->native_dtds); +#endif + } +#endif + EdidCtrlParam->IsYCbCr444Supp = ctb->yuv_444_supported; + EdidCtrlParam->IsYCbCr422Supp = ctb->yuv_422_supported; + } + +#if XVIDC_EDID_VERBOSITY > 1 + dtd = (struct xvidc_edid_detailed_timing_descriptor *) + ((u8 *) ctb + ctb->dtd_offset); + for (i = 0; dtd->pixel_clock; i++, dtd++) { + + timing_params = XV_VidC_timing(dtd); + if (VerboseEn) { + xil_printf(" Detailed timing #%u....... %ux%u%c at %uHz " + "(%u:%u)\r\n", + i + 1, + timing_params.hres, + timing_params.vres, + timing_params.vidfrmt ? 'i' : 'p', + timing_params.vfreq, + timing_params.aspect_ratio.width, + timing_params.aspect_ratio.height); + + xil_printf( + " Modeline............... \"%ux%u\" %u %u %u %u %u %u %u %u %u" + " %chsync %cvsync\r\n", + timing_params.hres, + timing_params.vres, + HZ_2_MHZ (timing_params.pixclk), + (timing_params.hres), + (timing_params.hres + timing_params.hfp), + (timing_params.hres + timing_params.hfp + + timing_params.hsync_width), + (timing_params.htotal), + (timing_params.vres), + (timing_params.vres + timing_params.vfp), + (timing_params.vres + timing_params.vfp + + timing_params.vsync_width), + (timing_params.vtotal), + timing_params.hsync_polarity ? '+' : '-', + timing_params.vsync_polarity ? '+' : '-'); + } + } +#endif +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { + xil_printf("\r\n"); + } +#endif + + if (ctb->revision >= 3) { + do { + const struct xvidc_cea861_data_block_header * const header = + (struct xvidc_cea861_data_block_header *) &ctb->data[index]; + + switch (header->tag) { + + case XVIDC_CEA861_DATA_BLOCK_TYPE_AUDIO: + { +#if XVIDC_EDID_VERBOSITY > 1 + const struct xvidc_cea861_audio_data_block * const db = + (struct xvidc_cea861_audio_data_block *) header; + + xvidc_disp_cea861_audio_data(db,EdidCtrlParam,VerboseEn); +#endif + } + break; + + case XVIDC_CEA861_DATA_BLOCK_TYPE_VIDEO: + { +#if XVIDC_EDID_VERBOSITY > 1 + const struct xvidc_cea861_video_data_block * const db = + (struct xvidc_cea861_video_data_block *) header; + + xvidc_disp_cea861_video_data(db,EdidCtrlParam,VerboseEn); +#endif + } + break; + + case XVIDC_CEA861_DATA_BLOCK_TYPE_VENDOR_SPECIFIC: + { + const struct + xvidc_cea861_vendor_specific_data_block * const db = + (struct xvidc_cea861_vendor_specific_data_block *) header; + + xvidc_disp_cea861_vendor_data(db,EdidCtrlParam,VerboseEn); + } + break; + + case XVIDC_CEA861_DATA_BLOCK_TYPE_SPEAKER_ALLOCATION: + { +#if XVIDC_EDID_VERBOSITY > 1 + const struct + xvidc_cea861_speaker_allocation_data_block * const db = + (struct xvidc_cea861_speaker_allocation_data_block *) header; + + xvidc_disp_cea861_speaker_allocation_data(db, + EdidCtrlParam,VerboseEn); +#endif + } + break; + + case XVIDC_CEA861_DATA_BLOCK_TYPE_EXTENDED: + { + const struct xvidc_cea861_extended_data_block * const db = + (struct xvidc_cea861_extended_data_block *) header; + + xvidc_disp_cea861_extended_data(db,EdidCtrlParam,VerboseEn); + } + break; + + default: +#if XVIDC_EDID_VERBOSITY > 1 + if (VerboseEn) { + xil_printf("Unknown CEA-861 data block type 0x%02x\r\n", + header->tag); + } +#endif + break; + } + + index = index + header->length + sizeof(*header); + } while (index < ctb->dtd_offset - offset); + } +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { + xil_printf("\r\n"); + } +#endif +} + + +/*****************************************************************************/ +/** +* +* This structure parse parse EDID routines +* +* +* @note None. +* +******************************************************************************/ +static const struct xvidc_edid_extension_handler { + void (* const inf_disp)(const struct xvidc_edid_extension * const, + XV_VidC_EdidCntrlParam *EdidCtrlParam, XV_VidC_Verbose VerboseEn); +} xvidc_edid_extension_handlers[] = { + [XVIDC_EDID_EXTENSION_CEA] = { xvidc_disp_cea861 }, +}; + + +/*****************************************************************************/ +/** +* +* This function parse and print the EDID of the Sink +* +* @param data is a pointer to the EDID array. +* @param EdidCtrlParam is a pointer the EDID Control parameter +* @param VerboseEn is a pointer to the XV_HdmiTxSs core instance. +* +* @return None +* +* @note None. +* +******************************************************************************/ +void +XV_VidC_parse_edid(const u8 * const data, + XV_VidC_EdidCntrlParam *EdidCtrlParam, + XV_VidC_Verbose VerboseEn) { + const struct edid * const edid = (struct edid *) data; + const struct xvidc_edid_extension * const extensions = + (struct xvidc_edid_extension *) (data + sizeof(*edid)); + + XV_VidC_EdidCtrlParamInit(EdidCtrlParam); + + xvidc_disp_edid1(edid,EdidCtrlParam,VerboseEn); + + for (u8 i = 0; i < edid->extensions; i++) { + const struct xvidc_edid_extension * const extension = &extensions[i]; + const struct xvidc_edid_extension_handler * const handler = + &xvidc_edid_extension_handlers[extension->tag]; + + if (!handler) { +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { + xil_printf("WARNING: block %u contains unknown extension " + " (%#04x)\r\n", i, extensions[i].tag); + } +#endif + continue; + } + + if (handler->inf_disp) { + (*handler->inf_disp)(extension,EdidCtrlParam,VerboseEn); + } + } +} diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/video_common_v4_3/src/xvidc_timings_table.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/video_common_v4_3/src/xvidc_timings_table.c new file mode 100644 index 000000000..ee1cb4f28 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/video_common_v4_3/src/xvidc_timings_table.c @@ -0,0 +1,534 @@ +/******************************************************************************* + * + * Copyright (C) 2017 Xilinx, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * Use of the Software is limited solely to applications: + * (a) running on a Xilinx device, or + * (b) that interact with a Xilinx device through a bus or interconnect. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of the Xilinx shall not be used + * in advertising or otherwise to promote the sale, use or other dealings in + * this Software without prior written authorization from Xilinx. + * +*******************************************************************************/ +/******************************************************************************/ +/** + * + * @file xvidc_timings_table.c + * @addtogroup video_common_v4_2 + * @{ + * + * Contains video timings for various standard resolutions. + * + * @note None. + * + * 
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -----------------------------------------------
+ * 1.0   als, 01/10/15 Initial release.
+ *       rc
+ * 2.0   als  08/14/15 Added new video timings.
+ * 2.1   als  11/04/15 Fixed video timings for some resolutions.
+ *       rco  02/09/17 Fix c++ compilation warnings
+ * 4.2   jsr  07/08/17 Added new video timings for SDI supported resolutions
+ *       aad  07/10/17 Add XVIDC_VM_3840x2160_60_P_RB video format
+ *       aad  09/05/17 Fixed timings for 1366x768_60_P
+ *       aad  09/05/17 Added 1366x768_60_P_RB
+ *
+ * +*******************************************************************************/ + +/******************************* Include Files ********************************/ + +#include "xvidc.h" + +/**************************** Variable Definitions ****************************/ + +/** + * This table contains the main stream attributes for various standard + * resolutions. Each entry is of the format: + * 1) ID: XVIDC_VM_x__(_RB = Reduced Blanking) + * 2) Resolution naming: "x@" + * 3) Frame rate: XVIDC_FR_ + * 4) Video timing structure: + * 1) Horizontal active resolution (pixels) + * 2) Horizontal front porch (pixels) + * 3) Horizontal sync width (pixels) + * 4) Horizontal back porch (pixels) + * 5) Horizontal total (pixels) + * 6) Horizontal sync polarity (0=negative|1=positive) + * 7) Vertical active resolution (lines) + * 8) Frame 0: Vertical front porch (lines) + * 9) Frame 0: Vertical sync width (lines) + * 10) Frame 0: Vertical back porch (lines) + * 11) Frame 0: Vertical total (lines) + * 12) Frame 1: Vertical front porch (lines) + * 13) Frame 1: Vertical sync width (lines) + * 14) Frame 1: Vertical back porch (lines) + * 15) Frame 1: Vertical total (lines) + * 16) Vertical sync polarity (0=negative|1=positive) + */ +#ifdef __cplusplus +extern "C" +#endif +const XVidC_VideoTimingMode XVidC_VideoTimingModes[XVIDC_VM_NUM_SUPPORTED] = +{ + /* Interlaced modes. */ + { XVIDC_VM_720x480_60_I, "720x480@60Hz (I)", XVIDC_FR_60HZ, + {720, 19, 62, 57, 858, 0, + 240, 4, 3, 15, 262, 5, 3, 15, 263, 0} }, + { XVIDC_VM_720x576_50_I, "720x576@50Hz (I)", XVIDC_FR_50HZ, + {720, 12, 63, 69, 864, 0, + 288, 2, 3, 19, 312, 3, 3, 19, 313, 0} }, + { XVIDC_VM_1440x480_60_I, "1440x480@60Hz (I)", XVIDC_FR_60HZ, + {1440, 38, 124, 114, 1716, 0, + 240, 4, 3, 15, 262, 5, 3, 15, 263, 0} }, + { XVIDC_VM_1440x576_50_I, "1440x576@50Hz (I)", XVIDC_FR_50HZ, + {1440, 24, 126, 138, 1728, 0, + 288, 2, 3, 19, 312, 3, 3, 19, 313, 0} }, + { XVIDC_VM_1920x1080_48_I, "1920x1080@48Hz (I)", XVIDC_FR_48HZ, + {1920, 371, 88, 371, 2750, 1, + 540, 2, 5, 15, 562, 3, 5, 15, 563, 1} }, + { XVIDC_VM_1920x1080_50_I, "1920x1080@50Hz (I)", XVIDC_FR_50HZ, + {1920, 528, 44, 148, 2640, 1, + 540, 2, 5, 15, 562, 3, 5, 15, 563, 1} }, + { XVIDC_VM_1920x1080_60_I, "1920x1080@60Hz (I)", XVIDC_FR_60HZ, + {1920, 88, 44, 148, 2200, 1, + 540, 2, 5, 15, 562, 3, 5, 15, 563, 1} }, + { XVIDC_VM_1920x1080_96_I, "1920x1080@96Hz (I)", XVIDC_FR_96HZ, + {1920, 371, 88, 371, 2750, 1, + 1080, 4, 10, 30, 1124, 6, 10, 30, 1126, 1} }, + { XVIDC_VM_1920x1080_100_I, "1920x1080@100Hz (I)", XVIDC_FR_100HZ, + {1920, 528, 44, 148, 2640, 1, + 1080, 4, 10, 30, 1124, 6, 10, 30, 1126, 1} }, + { XVIDC_VM_1920x1080_120_I, "1920x1080@120Hz (I)", XVIDC_FR_120HZ, + {1920, 88, 44, 148, 2200, 1, + 1080, 4, 10, 30, 1124, 6, 10, 30, 1126, 1} }, + { XVIDC_VM_2048x1080_48_I, "2048x1080@48Hz (I)", XVIDC_FR_48HZ, + {2048, 329, 44, 329, 2750, 1, + 540, 2, 5, 15, 562, 3, 5, 15, 563, 1} }, + { XVIDC_VM_2048x1080_50_I, "2048x1080@50Hz (I)", XVIDC_FR_50HZ, + {2048, 274, 44, 274, 2640, 1, + 540, 2, 5, 15, 562, 3, 5, 15, 563, 1} }, + { XVIDC_VM_2048x1080_60_I, "2048x1080@60Hz (I)", XVIDC_FR_60HZ, + {2048, 66, 20, 66, 2200, 1, + 540, 2, 5, 15, 562, 3, 5, 15, 563, 1} }, + { XVIDC_VM_2048x1080_96_I, "2048x1080@96Hz (I)", XVIDC_FR_96HZ, + {2048, 329, 44, 329, 2750, 1, + 1080, 4, 10, 30, 1124, 6, 10, 30, 1126, 1} }, + { XVIDC_VM_2048x1080_100_I, "2048x1080@100Hz (I)", XVIDC_FR_100HZ, + {2048, 274, 44, 274, 2640, 1, + 1080, 4, 10, 30, 1124, 6, 10, 30, 1126, 1} }, + { XVIDC_VM_2048x1080_120_I, "2048x1080@120Hz (I)", XVIDC_FR_120HZ, + {2048, 66, 20, 66, 2200, 1, + 1080, 4, 10, 30, 1124, 6, 10, 30, 1126, 1} }, + + + /* Progressive modes. */ + { XVIDC_VM_640x350_85_P, "640x350@85Hz", XVIDC_FR_85HZ, + {640, 32, 64, 96, 832, 1, + 350, 32, 3, 60, 445, 0, 0, 0, 0, 0} }, + { XVIDC_VM_640x480_60_P, "640x480@60Hz", XVIDC_FR_60HZ, + {640, 8+8, 96, 40+8, 800, 0, + 480, 2+8, 2, 25+8, 525, 0, 0, 0, 0, 0} }, + { XVIDC_VM_640x480_72_P, "640x480@72Hz", XVIDC_FR_72HZ, + {640, 8+16, 40, 120+8, 832, 0, + 480, 8+1, 3, 20+8, 520, 0, 0, 0, 0, 0} }, + { XVIDC_VM_640x480_75_P, "640x480@75Hz", XVIDC_FR_75HZ, + {640, 16, 64, 120, 840, 0, + 480, 1, 3, 16, 500, 0, 0, 0, 0, 0} }, + { XVIDC_VM_640x480_85_P, "640x480@85Hz", XVIDC_FR_85HZ, + {640, 56, 56, 80, 832, 0, + 480, 1, 3, 25, 509, 0, 0, 0, 0, 0} }, + { XVIDC_VM_720x400_85_P, "720x400@85Hz", XVIDC_FR_85HZ, + {720, 36, 72, 108, 936, 0, + 400, 1, 3, 42, 446, 0, 0, 0, 0, 1} }, + { XVIDC_VM_720x480_60_P, "720x480@60Hz", XVIDC_FR_60HZ, + {720, 16, 62, 60, 858, 0, + 480, 9, 6, 30, 525, 0, 0, 0, 0, 0} }, + { XVIDC_VM_720x576_50_P, "720x576@50Hz", XVIDC_FR_50HZ, + {720, 12, 64, 68, 864, 0, + 576, 5, 5, 39, 625, 0, 0, 0, 0, 0} }, + { XVIDC_VM_800x600_56_P, "800x600@56Hz", XVIDC_FR_56HZ, + {800, 24, 72, 128, 1024, 1, + 600, 1, 2, 22, 625, 0, 0, 0, 0, 1} }, + { XVIDC_VM_800x600_60_P, "800x600@60Hz", XVIDC_FR_60HZ, + {800, 40, 128, 88, 1056, 1, + 600, 1, 4, 23, 628, 0, 0, 0, 0, 1} }, + { XVIDC_VM_800x600_72_P, "800x600@72Hz", XVIDC_FR_72HZ, + {800, 56, 120, 64, 1040, 1, + 600, 37, 6, 23, 666, 0, 0, 0, 0, 1} }, + { XVIDC_VM_800x600_75_P, "800x600@75Hz", XVIDC_FR_75HZ, + {800, 16, 80, 160, 1056, 1, + 600, 1, 3, 21, 625, 0, 0, 0, 0, 1} }, + { XVIDC_VM_800x600_85_P, "800x600@85Hz", XVIDC_FR_85HZ, + {800, 32, 64, 152, 1048, 1, + 600, 1, 3, 27, 631, 0, 0, 0, 0, 1} }, + { XVIDC_VM_800x600_120_P_RB, "800x600@120Hz (RB)", XVIDC_FR_120HZ, + {800, 48, 32, 80, 960, 1, + 600, 3, 4, 29, 636, 0, 0, 0, 0, 0} }, + { XVIDC_VM_848x480_60_P, "848x480@60Hz", XVIDC_FR_60HZ, + {848, 16, 112, 112, 1088, 1, + 480, 6, 8, 23, 517, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1024x768_60_P, "1024x768@60Hz", XVIDC_FR_60HZ, + {1024, 24, 136, 160, 1344, 0, + 768, 3, 6, 29, 806, 0, 0, 0, 0, 0} }, + { XVIDC_VM_1024x768_70_P, "1024x768@70Hz", XVIDC_FR_70HZ, + {1024, 24, 136, 144, 1328, 0, + 768, 3, 6, 29, 806, 0, 0, 0, 0, 0} }, + { XVIDC_VM_1024x768_75_P, "1024x768@75Hz", XVIDC_FR_75HZ, + {1024, 16, 96, 176, 1312, 1, + 768, 1, 3, 28, 800, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1024x768_85_P, "1024x768@85Hz", XVIDC_FR_85HZ, + {1024, 48, 96, 208, 1376, 1, + 768, 1, 3, 36, 808, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1024x768_120_P_RB, "1024x768@120Hz (RB)", XVIDC_FR_120HZ, + {1024, 48, 32, 80, 1184, 1, + 768, 3, 4, 38, 813, 0, 0, 0, 0, 0} }, + { XVIDC_VM_1152x864_75_P, "1152x864@75Hz", XVIDC_FR_75HZ, + {1152, 64, 128, 256, 1600, 1, + 864, 1, 3, 32, 900, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1280x720_24_P, "1280x720@24Hz", XVIDC_FR_24HZ, + {1280, 970, 905, 970, 4125, 1, + 720, 5, 5, 20, 750, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1280x720_25_P, "1280x720@25Hz", XVIDC_FR_25HZ, + {1280, 970, 740, 970, 3960, 1, + 720, 5, 5, 20, 750, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1280x720_30_P, "1280x720@30Hz", XVIDC_FR_30HZ, + {1280, 970, 80, 970, 3300, 1, + 720, 5, 5, 20, 750, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1280x720_50_P, "1280x720@50Hz", XVIDC_FR_50HZ, + {1280, 440, 40, 220, 1980, 1, + 720, 5, 5, 20, 750, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1280x720_60_P, "1280x720@60Hz", XVIDC_FR_60HZ, + {1280, 110, 40, 220, 1650, 1, + 720, 5, 5, 20, 750, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1280x768_60_P, "1280x768@60Hz", XVIDC_FR_60HZ, + {1280, 64, 128, 192, 1664, 0, + 768, 3, 7, 20, 798, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1280x768_60_P_RB, "1280x768@60Hz (RB)", XVIDC_FR_60HZ, + {1280, 48, 32, 80, 1440, 1, + 768, 3, 7, 12, 790, 0, 0, 0, 0, 0} }, + { XVIDC_VM_1280x768_75_P, "1280x768@75Hz", XVIDC_FR_75HZ, + {1280, 80, 128, 208, 1696, 0, + 768, 3, 7, 27, 805, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1280x768_85_P, "1280x768@85Hz", XVIDC_FR_85HZ, + {1280, 80, 136, 216, 1712, 0, + 768, 3, 7, 31, 809, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1280x768_120_P_RB, "1280x768@120Hz (RB)", XVIDC_FR_120HZ, + {1280, 48, 32, 80, 1440, 1, + 768, 3, 7, 35, 813, 0, 0, 0, 0, 0} }, + { XVIDC_VM_1280x800_60_P, "1280x800@60Hz", XVIDC_FR_60HZ, + {1280, 72, 128, 200, 1680, 0, + 800, 3, 6, 22, 831, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1280x800_60_P_RB, "1280x800@60Hz (RB)", XVIDC_FR_60HZ, + {1280, 48, 32, 80, 1440, 1, + 800, 3, 6, 14, 823, 0, 0, 0, 0, 0} }, + { XVIDC_VM_1280x800_75_P, "1280x800@75Hz", XVIDC_FR_75HZ, + {1280, 80, 128, 208, 1696, 0, + 800, 3, 6, 29, 838, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1280x800_85_P, "1280x800@85Hz", XVIDC_FR_85HZ, + {1280, 80, 136, 216, 1712, 0, + 800, 3, 6, 34, 843, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1280x800_120_P_RB, "1280x800@120Hz (RB)", XVIDC_FR_120HZ, + {1280, 48, 32, 80, 1440, 1, + 800, 3, 6, 38, 847, 0, 0, 0, 0, 0} }, + { XVIDC_VM_1280x960_60_P, "1280x960@60Hz", XVIDC_FR_60HZ, + {1280, 96, 112, 312, 1800, 1, + 960, 1, 3, 36, 1000, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1280x960_85_P, "1280x960@85Hz", XVIDC_FR_85HZ, + {1280, 64, 160, 224, 1728, 1, + 960, 1, 3, 47, 1011, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1280x960_120_P_RB, "1280x960@120Hz (RB)", XVIDC_FR_120HZ, + {1280, 48, 32, 80, 1440, 1, + 960, 3, 4, 50, 1017, 0, 0, 0, 0, 0} }, + { XVIDC_VM_1280x1024_60_P, "1280x1024@60Hz", XVIDC_FR_60HZ, + {1280, 48, 112, 248, 1688, 1, + 1024, 1, 3, 38, 1066, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1280x1024_75_P, "1280x1024@75Hz", XVIDC_FR_75HZ, + {1280, 16, 144, 248, 1688, 1, + 1024, 1, 3, 38, 1066, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1280x1024_85_P, "1280x1024@85Hz", XVIDC_FR_85HZ, + {1280, 64, 160, 224, 1728, 1, + 1024, 1, 3, 44, 1072, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1280x1024_120_P_RB, "1280x1024@120Hz (RB)", XVIDC_FR_120HZ, + {1280, 48, 32, 80, 1440, 1, + 1024, 3, 7, 50, 1084, 0, 0, 0, 0, 0} }, + { XVIDC_VM_1360x768_60_P, "1360x768@60Hz", XVIDC_FR_60HZ, + {1360, 64, 112, 256, 1792, 1, + 768, 3, 6, 18, 795, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1360x768_120_P_RB, "1360x768@120Hz (RB)", XVIDC_FR_120HZ, + {1360, 48, 32, 80, 1520, 1, + 768, 3, 5, 37, 813, 0, 0, 0, 0, 0} }, + { XVIDC_VM_1366x768_60_P, "1366x768@60Hz", XVIDC_FR_60HZ, + {1366, 70, 143, 213, 1792, 1, + 768, 3, 3, 24, 798, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1366x768_60_P_RB, "1366x768@60Hz (RB)", XVIDC_FR_60HZ, + {1366, 14, 56, 64, 1500, 1, + 768, 1, 3, 28, 800, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1400x1050_60_P, "1400x1050@60Hz", XVIDC_FR_60HZ, + {1400, 88, 144, 232, 1864, 0, + 1050, 3, 4, 32, 1089, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1400x1050_60_P_RB, "1400x1050@60Hz (RB)", XVIDC_FR_60HZ, + {1400, 48, 32, 80, 1560, 1, + 1050, 3, 4, 23, 1080, 0, 0, 0, 0, 0} }, + { XVIDC_VM_1400x1050_75_P, "1400x1050@75Hz", XVIDC_FR_75HZ, + {1400, 104, 144, 248, 1896, 0, + 1050, 3, 4, 42, 1099, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1400x1050_85_P, "1400x1050@85Hz", XVIDC_FR_85HZ, + {1400, 104, 152, 256, 1912, 0, + 1050, 3, 4, 48, 1105, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1400x1050_120_P_RB, "1400x1050@120Hz (RB)", XVIDC_FR_120HZ, + {1400, 48, 32, 80, 1560, 1, + 1050, 3, 4, 55, 1112, 0, 0, 0, 0, 0} }, + { XVIDC_VM_1440x240_60_P, "1440x240@60Hz", XVIDC_FR_60HZ, + {1440, 38, 124, 114, 1716, 0, + 240, 14, 3, 4, 262, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1440x900_60_P, "1440x900@60Hz", XVIDC_FR_60HZ, + {1440, 80, 152, 232, 1904, 0, + 900, 3, 6, 25, 934, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1440x900_60_P_RB, "1440x900@60Hz (RB)", XVIDC_FR_60HZ, + {1440, 48, 32, 80, 1600, 1, + 900, 3, 6, 17, 926, 0, 0, 0, 0, 0} }, + { XVIDC_VM_1440x900_75_P, "1440x900@75Hz", XVIDC_FR_75HZ, + {1440, 96, 152, 248, 1936, 0, + 900, 3, 6, 33, 942, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1440x900_85_P, "1440x900@85Hz", XVIDC_FR_85HZ, + {1440, 104, 152, 256, 1952, 0, + 900, 3, 6, 39, 948, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1440x900_120_P_RB, "1440x900@120Hz (RB)", XVIDC_FR_120HZ, + {1440, 48, 32, 80, 1600, 1, + 900, 3, 6, 44, 953, 0, 0, 0, 0, 0} }, + { XVIDC_VM_1600x1200_60_P, "1600x1200@60Hz", XVIDC_FR_60HZ, + {1600, 64, 192, 304, 2160, 1, + 1200, 1, 3, 46, 1250, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1600x1200_65_P, "1600x1200@65Hz", XVIDC_FR_65HZ, + {1600, 64, 192, 304, 2160, 1, + 1200, 1, 3, 46, 1250, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1600x1200_70_P, "1600x1200@70Hz", XVIDC_FR_70HZ, + {1600, 64, 192, 304, 2160, 1, + 1200, 1, 3, 46, 1250, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1600x1200_75_P, "1600x1200@75Hz", XVIDC_FR_75HZ, + {1600, 64, 192, 304, 2160, 1, + 1200, 1, 3, 46, 1250, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1600x1200_85_P, "1600x1200@85Hz", XVIDC_FR_85HZ, + {1600, 64, 192, 304, 2160, 1, + 1200, 1, 3, 46, 1250, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1600x1200_120_P_RB, "1600x1200@120Hz (RB)", XVIDC_FR_120HZ, + {1600, 48, 32, 80, 1760, 1, + 1200, 3, 4, 64, 1271, 0, 0, 0, 0, 0} }, + { XVIDC_VM_1680x720_50_P, "1680x720@50Hz", XVIDC_FR_50HZ, + {1680, 260, 40, 220, 2200, 1, + 720, 5, 5, 20, 750, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1680x720_60_P, "1680x720@60Hz", XVIDC_FR_60HZ, + {1680, 260, 40, 220, 2200, 1, + 720, 5, 5, 20, 750, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1680x720_100_P, "1680x720@100Hz", XVIDC_FR_100HZ, + {1680, 60, 40, 220, 2000, 1, + 720, 5, 5, 95, 825, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1680x720_120_P, "1680x720@120Hz", XVIDC_FR_120HZ, + {1680, 60, 40, 220, 2000, 1, + 720, 5, 5, 95, 825, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1680x1050_50_P, "1680x1050@50Hz", XVIDC_FR_50HZ, + {1680, 88, 176, 264, 2208, 0, + 1050, 3, 6, 24, 1083, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1680x1050_60_P, "1680x1050@60Hz", XVIDC_FR_60HZ, + {1680, 104, 176, 280, 2240, 0, + 1050, 3, 6, 30, 1089, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1680x1050_60_P_RB, "1680x1050@60Hz (RB)", XVIDC_FR_60HZ, + {1680, 48, 32, 80, 1840, 1, + 1050, 3, 6, 21, 1080, 0, 0, 0, 0, 0} }, + { XVIDC_VM_1680x1050_75_P, "1680x1050@75Hz", XVIDC_FR_75HZ, + {1680, 120, 176, 296, 2272, 0, + 1050, 3, 6, 40, 1099, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1680x1050_85_P, "1680x1050@85Hz", XVIDC_FR_85HZ, + {1680, 128, 176, 304, 2288, 0, + 1050, 3, 6, 46, 1105, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1680x1050_120_P_RB, "1680x1050@120Hz (RB)", XVIDC_FR_120HZ, + {1680, 48, 32, 80, 1840, 1, + 1050, 3, 6, 53, 1112, 0, 0, 0, 0, 0} }, + { XVIDC_VM_1792x1344_60_P, "1792x1344@60Hz", XVIDC_FR_60HZ, + {1792, 128, 200, 328, 2448, 0, + 1344, 1, 3, 46, 1394, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1792x1344_75_P, "1792x1344@75Hz", XVIDC_FR_75HZ, + {1792, 96, 216, 352, 2456, 0, + 1344, 1, 3, 69, 1417, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1792x1344_120_P_RB, "1792x1344@120Hz (RB)", XVIDC_FR_120HZ, + {1792, 48, 32, 80, 1952, 1, + 1344, 3, 4, 72, 1423, 0, 0, 0, 0, 0} }, + { XVIDC_VM_1856x1392_60_P, "1856x1392@60Hz", XVIDC_FR_60HZ, + {1856, 96, 224, 352, 2528, 0, + 1392, 1, 3, 43, 1439, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1856x1392_75_P, "1856x1392@75Hz", XVIDC_FR_75HZ, + {1856, 128, 224, 352, 2560, 0, + 1392, 1, 3, 104, 1500, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1856x1392_120_P_RB, "1856x1392@120Hz (RB)", XVIDC_FR_120HZ, + {1856, 48, 32, 80, 2016, 1, + 1392, 3, 4, 75, 1474, 0, 0, 0, 0, 0} }, + { XVIDC_VM_1920x1080_24_P, "1920x1080@24Hz", XVIDC_FR_24HZ, + {1920, 638, 44, 148, 2750, 1, + 1080, 4, 5, 36, 1125, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1920x1080_25_P, "1920x1080@25Hz", XVIDC_FR_25HZ, + {1920, 528, 44, 148, 2640, 1, + 1080, 4, 5, 36, 1125, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1920x1080_30_P, "1920x1080@30Hz", XVIDC_FR_30HZ, + {1920, 88, 44, 148, 2200, 1, + 1080, 4, 5, 36, 1125, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1920x1080_48_P, "1920x1080@48Hz", XVIDC_FR_48HZ, + {1920, 638, 44, 148, 2750, 1, + 1080, 4, 5, 36, 1125, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1920x1080_50_P, "1920x1080@50Hz", XVIDC_FR_50HZ, + {1920, 528, 44, 148, 2640, 1, + 1080, 4, 5, 36, 1125, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1920x1080_60_P, "1920x1080@60Hz", XVIDC_FR_60HZ, + {1920, 88, 44, 148, 2200, 1, + 1080, 4, 5, 36, 1125, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1920x1080_100_P, "1920x1080@100Hz", XVIDC_FR_100HZ, + {1920, 528, 44, 148, 2640, 1, + 1080, 4, 5, 36, 1125, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1920x1080_120_P, "1920x1080@120Hz", XVIDC_FR_120HZ, + {1920, 88, 44, 148, 2200, 1, + 1080, 4, 5, 36, 1125, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1920x1200_60_P, "1920x1200@60Hz", XVIDC_FR_60HZ, + {1920, 136, 200, 336, 2592, 0, + 1200, 3, 6, 36, 1245, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1920x1200_60_P_RB, "1920x1200@60Hz (RB)", XVIDC_FR_60HZ, + {1920, 48, 32, 80, 2080, 1, + 1200, 3, 6, 26, 1235, 0, 0, 0, 0, 0} }, + { XVIDC_VM_1920x1200_75_P, "1920x1200@75Hz", XVIDC_FR_75HZ, + {1920, 136, 208, 344, 2608, 0, + 1200, 3, 6, 46, 1255, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1920x1200_85_P, "1920x1200@85Hz", XVIDC_FR_85HZ, + {1920, 144, 208, 352, 2624, 0, + 1200, 3, 6, 53, 1262, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1920x1200_120_P_RB, "1920x1200@120Hz (RB)", XVIDC_FR_120HZ, + {1920, 48, 32, 80, 2080, 1, + 1200, 3, 6, 62, 1271, 0, 0, 0, 0, 0} }, + { XVIDC_VM_1920x1440_60_P, "1920x1440@60Hz", XVIDC_FR_60HZ, + {1920, 128, 208, 344, 2600, 0, + 1440, 1, 3, 56, 1500, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1920x1440_75_P, "1920x1440@75Hz", XVIDC_FR_75HZ, + {1920, 144, 224, 352, 2640, 0, + 1440, 1, 3, 56, 1500, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1920x1440_120_P_RB, "1920x1440@120Hz (RB)", XVIDC_FR_120HZ, + {1920, 48, 32, 80, 2080, 1, + 1440, 3, 4, 78, 1525, 0, 0, 0, 0, 0} }, + { XVIDC_VM_1920x2160_60_P, "1920x2160@60Hz", XVIDC_FR_60HZ, + {1920, 88, 44, 148, 2200, 1, + 2160, 20, 10, 60, 2250, 0, 0, 0, 0, 0} }, + { XVIDC_VM_2048x1080_24_P, "2048x1080@24Hz", XVIDC_FR_24HZ, + {2048, 510, 44, 148, 2750, 1, + 1080, 4, 5, 36, 1125, 0, 0, 0, 0, 1} }, + { XVIDC_VM_2048x1080_25_P, "2048x1080@25Hz", XVIDC_FR_25HZ, + {2048, 400, 44, 148, 2640, 1, + 1080, 4, 5, 36, 1125, 0, 0, 0, 0, 1} }, + { XVIDC_VM_2048x1080_30_P, "2048x1080@30Hz", XVIDC_FR_30HZ, + {2048, 66, 20, 66, 2200, 1, + 1080, 4, 5, 36, 1125, 0, 0, 0, 0, 1} }, + { XVIDC_VM_2048x1080_48_P, "2048x1080@48Hz", XVIDC_FR_48HZ, + {2048, 510, 44, 148, 2750, 1, + 1080, 4, 5, 36, 1125, 0, 0, 0, 0, 1} }, + { XVIDC_VM_2048x1080_50_P, "2048x1080@50Hz", XVIDC_FR_50HZ, + {2048, 400, 44, 148, 2640, 1, + 1080, 4, 5, 36, 1125, 0, 0, 0, 0, 1} }, + { XVIDC_VM_2048x1080_60_P, "2048x1080@60Hz", XVIDC_FR_60HZ, + {2048, 88, 44, 20, 2200, 1, + 1080, 4, 5, 36, 1125, 0, 0, 0, 0, 1} }, + { XVIDC_VM_2048x1080_100_P, "2048x1080@100Hz", XVIDC_FR_100HZ, + {2048, 528, 44, 148, 2640, 1, + 1080, 4, 5, 36, 1125, 0, 0, 0, 0, 1} }, + { XVIDC_VM_2048x1080_120_P, "2048x1080@120Hz", XVIDC_FR_120HZ, + {2048, 88, 44, 148, 2200, 1, + 1080, 4, 5, 36, 1125, 0, 0, 0, 0, 1} }, + { XVIDC_VM_2560x1080_50_P, "2560x1080@50Hz", XVIDC_FR_50HZ, + {2560, 548, 44, 148, 3300, 1, + 1080, 4, 5, 36, 1125, 0, 0, 0, 0, 1} }, + { XVIDC_VM_2560x1080_60_P, "2560x1080@60Hz", XVIDC_FR_60HZ, + {2560, 248, 44, 148, 3000, 1, + 1080, 4, 5, 11, 1100, 0, 0, 0, 0, 1} }, + { XVIDC_VM_2560x1080_100_P, "2560x1080@100Hz", XVIDC_FR_100HZ, + {2560, 218, 44, 148, 2970, 1, + 1080, 4, 5, 161, 1250, 0, 0, 0, 0, 1} }, + { XVIDC_VM_2560x1080_120_P, "2560x1080@120Hz", XVIDC_FR_120HZ, + {2560, 548, 44, 148, 3300, 1, + 1080, 4, 5, 161, 1250, 0, 0, 0, 0, 1} }, + { XVIDC_VM_2560x1600_60_P, "2560x1600@60Hz", XVIDC_FR_60HZ, + {2560, 192, 280, 472, 3504, 0, + 1600, 3, 6, 49, 1658, 0, 0, 0, 0, 1} }, + { XVIDC_VM_2560x1600_60_P_RB, "2560x1600@60Hz (RB)", XVIDC_FR_60HZ, + {2560, 48, 32, 80, 2720, 1, + 1600, 3, 6, 37, 1646, 0, 0, 0, 0, 0} }, + { XVIDC_VM_2560x1600_75_P, "2560x1600@75Hz", XVIDC_FR_75HZ, + {2560, 208, 280, 488, 3536, 0, + 1600, 3, 6, 63, 1672, 0, 0, 0, 0, 1} }, + { XVIDC_VM_2560x1600_85_P, "2560x1600@85Hz", XVIDC_FR_85HZ, + {2560, 208, 280, 488, 3536, 0, + 1600, 3, 6, 73, 1682, 0, 0, 0, 0, 1} }, + { XVIDC_VM_2560x1600_120_P_RB, "2560x1600@120Hz (RB)", XVIDC_FR_120HZ, + {2560, 48, 32, 80, 2720, 1, + 1600, 3, 6, 85, 1694, 0, 0, 0, 0, 0} }, + { XVIDC_VM_3840x2160_24_P, "3840x2160@24Hz", XVIDC_FR_24HZ, + {3840, 1276, 88, 296, 5500, 1, + 2160, 8, 10, 72, 2250, 0, 0, 0, 0, 1} }, + { XVIDC_VM_3840x2160_25_P, "3840x2160@25Hz", XVIDC_FR_25HZ, + {3840, 1056, 88, 296, 5280, 1, + 2160, 8, 10, 72, 2250, 0, 0, 0, 0, 1} }, + { XVIDC_VM_3840x2160_30_P, "3840x2160@30Hz", XVIDC_FR_30HZ, + {3840, 176, 88, 296, 4400, 1, + 2160, 8, 10, 72, 2250, 0, 0, 0, 0, 1} }, + { XVIDC_VM_3840x2160_48_P, "3840x2160@48Hz", XVIDC_FR_48HZ, + {3840, 1276, 88, 296, 5500, 1, + 2160, 8, 10, 72, 2250, 0, 0, 0, 0, 1} }, + { XVIDC_VM_3840x2160_50_P, "3840x2160@50Hz", XVIDC_FR_50HZ, + {3840, 1056, 88, 296, 5280, 1, + 2160, 8, 10, 72, 2250, 0, 0, 0, 0, 1} }, + { XVIDC_VM_3840x2160_60_P, "3840x2160@60Hz", XVIDC_FR_60HZ, + {3840, 176, 88, 296, 4400, 1, + 2160, 8, 10, 72, 2250, 0, 0, 0, 0, 1} }, + { XVIDC_VM_3840x2160_60_P_RB, "3840x2160@60Hz (RB)", XVIDC_FR_60HZ, + {3840, 48, 32, 80, 4000, 1, + 2160, 3, 5, 54, 2222, 0, 0, 0, 0, 0} }, + { XVIDC_VM_4096x2160_24_P, "4096x2160@24Hz", XVIDC_FR_24HZ, + {4096, 1020, 88, 296, 5500, 1, + 2160, 8, 10, 72, 2250, 0, 0, 0, 0, 1} }, + { XVIDC_VM_4096x2160_25_P, "4096x2160@25Hz", XVIDC_FR_25HZ, + {4096, 968, 88, 128, 5280, 1, + 2160, 8, 10, 72, 2250, 0, 0, 0, 0, 1} }, + { XVIDC_VM_4096x2160_30_P, "4096x2160@30Hz", XVIDC_FR_30HZ, + {4096, 88, 88, 128, 4400, 1, + 2160, 8, 10, 72, 2250, 0, 0, 0, 0, 1} }, + { XVIDC_VM_4096x2160_48_P, "4096x2160@48Hz", XVIDC_FR_48HZ, + {4096, 1020, 88, 296, 5500, 1, + 2160, 8, 10, 72, 2250, 0, 0, 0, 0, 1} }, + { XVIDC_VM_4096x2160_50_P, "4096x2160@50Hz", XVIDC_FR_50HZ, + {4096, 968, 88, 128, 5280, 1, + 2160, 8, 10, 72, 2250, 0, 0, 0, 0, 1} }, + { XVIDC_VM_4096x2160_60_P, "4096x2160@60Hz", XVIDC_FR_60HZ, + {4096, 88, 88, 128, 4400, 1, + 2160, 8, 10, 72, 2250, 0, 0, 0, 0, 1} }, + { XVIDC_VM_4096x2160_60_P_RB, "4096x2160@60Hz (RB)", XVIDC_FR_60HZ, + {4096, 8, 32, 40, 4176, 1, + 2160, 48, 8, 6, 2222, 0, 0, 0, 0, 0} }, +}; + +/** @} */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/wdtps_v3_0/src/xwdtps.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/wdtps_v3_0/src/xwdtps.h index 893d516e7..58e559635 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/wdtps_v3_0/src/xwdtps.h +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/wdtps_v3_0/src/xwdtps.h @@ -88,6 +88,8 @@ * for CR 658287 * 3.0 pkp 12/09/14 Added support for Zynq Ultrascale Mp.Also * modified code for MISRA-C:2012 compliance. +* ms 03/17/17 Added readme.txt file in examples folder for doxygen +* generation. * * ******************************************************************************/ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/wdtps_v3_0/src/xwdtps_g.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/wdtps_v3_0/src/xwdtps_g.c index 6ea6b192b..2ad200861 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/wdtps_v3_0/src/xwdtps_g.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/wdtps_v3_0/src/xwdtps_g.c @@ -5,7 +5,7 @@ * Version: * DO NOT EDIT. * -* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.* +* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.* *Permission is hereby granted, free of charge, to any person obtaining a copy *of this software and associated documentation files (the Software), to deal *in the Software without restriction, including without limitation the rights @@ -44,7 +44,7 @@ * The configuration table for devices */ -XWdtPs_Config XWdtPs_ConfigTable[] = +XWdtPs_Config XWdtPs_ConfigTable[XPAR_XWDTPS_NUM_INSTANCES] = { { XPAR_PSU_WDT_0_DEVICE_ID, diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/zdma_v1_1/src/Makefile b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/zdma_v1_5/src/Makefile similarity index 100% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/zdma_v1_1/src/Makefile rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/zdma_v1_5/src/Makefile diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/xzdma.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/zdma_v1_5/src/xzdma.c similarity index 98% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/xzdma.c rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/zdma_v1_5/src/xzdma.c index c203f585d..8cad941f8 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/xzdma.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/zdma_v1_5/src/xzdma.c @@ -33,7 +33,7 @@ /** * * @file xzdma.c -* @addtogroup zdma_v1_0 +* @addtogroup zdma_v1_5 * @{ * * This file contains the implementation of the interface functions for ZDMA @@ -52,6 +52,7 @@ * scatter gather mode data transfer and corrected * XZDma_SetChDataConfig API to set over fetch and * src issue parameters correctly. +* 1.3 mus 08/14/17 Add CCI support for A53 in EL1 NS * * ******************************************************************************/ @@ -117,6 +118,7 @@ s32 XZDma_CfgInitialize(XZDma *InstancePtr, XZDma_Config *CfgPtr, InstancePtr->Config.BaseAddress = CfgPtr->BaseAddress; InstancePtr->Config.DeviceId = CfgPtr->DeviceId; InstancePtr->Config.DmaType = CfgPtr->DmaType; + InstancePtr->Config.IsCacheCoherent = CfgPtr->IsCacheCoherent; InstancePtr->Config.BaseAddress = EffectiveAddr; @@ -279,8 +281,9 @@ u32 XZDma_CreateBDList(XZDma *InstancePtr, XZDma_DscrType TypeOfDscr, (NoOfBytes >> 1) / Size; InstancePtr->Descriptor.SrcDscrPtr = (void *)Dscr_MemPtr; InstancePtr->Descriptor.DstDscrPtr = - (void *)Dscr_MemPtr + (Size * InstancePtr->Descriptor.DscrCount); + (void *)(Dscr_MemPtr + (Size * InstancePtr->Descriptor.DscrCount)); + if (!InstancePtr->Config.IsCacheCoherent) Xil_DCacheInvalidateRange((INTPTR)Dscr_MemPtr, NoOfBytes); return (InstancePtr->Descriptor.DscrCount); @@ -701,6 +704,17 @@ void XZDma_Reset(XZDma *InstancePtr) (void)XZDma_GetSrcIntrCnt(InstancePtr); (void)XZDma_GetDstIntrCnt(InstancePtr); + if (InstancePtr->Config.IsCacheCoherent) { + XZDma_WriteReg((InstancePtr->Config.BaseAddress), + XZDMA_CH_DSCR_ATTR_OFFSET, + InstancePtr->Config.IsCacheCoherent << XZDMA_DSCR_ATTR_AXCOHRNT_SHIFT); + XZDma_WriteReg((InstancePtr->Config.BaseAddress), + XZDMA_CH_SRC_DSCR_WORD3_OFFSET, + InstancePtr->Config.IsCacheCoherent & XZDMA_WORD3_COHRNT_MASK); + XZDma_WriteReg((InstancePtr->Config.BaseAddress), + XZDMA_CH_DST_DSCR_WORD3_OFFSET, + InstancePtr->Config.IsCacheCoherent & XZDMA_WORD3_COHRNT_MASK); + } InstancePtr->ChannelState = XZDMA_IDLE; } diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/zdma_v1_1/src/xzdma.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/zdma_v1_5/src/xzdma.h similarity index 93% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/zdma_v1_1/src/xzdma.h rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/zdma_v1_5/src/xzdma.h index 1f268d43c..9ff690795 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/zdma_v1_1/src/xzdma.h +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/zdma_v1_5/src/xzdma.h @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2014-2017 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -33,12 +33,12 @@ /** * * @file xzdma.h -* @addtogroup zdma_v1_0 +* @addtogroup zdma_v1_5 * @{ * @details * * ZDMA is a general purpose DMA designed to support memory to memory and memory -* to IO buffer transfers. ALTO has two instance of general purpose ZDMA. +* to IO buffer transfers. ZynqMP has two instance of general purpose ZDMA. * One is located in FPD (full power domain) which is GDMA and other is located * in LPD (low power domain) which is ADMA. * @@ -115,7 +115,20 @@ * scatter gather mode data transfer and corrected * XZDma_SetChDataConfig API to set over fetch and * src issue parameters correctly. - +* ms 03/17/17 Added readme.txt file in examples folder for doxygen +* generation. +* ms 04/05/17 Modified comment lines notation in functions of zdma +* examples to avoid unnecessary description to get +* displayed while generating doxygen and also changed +* filename tag to include the readonly mode example file +* in doxygen. +* 1.3 mus 08/14/17 Update cache coherency information of the interface in +* its config structure. +* 1.4 adk 11/02/17 Updated examples to fix compilation errors for IAR +* compiler. +* 1.5 adk 11/22/17 Added peripheral test app support for ZDMA driver. +* 12/11/17 Fixed peripheral test app generation issues when dma +* buffers are configured on OCM memory(CR#990806). * * ******************************************************************************/ @@ -132,6 +145,7 @@ extern "C" { #include "xil_assert.h" #include "xstatus.h" #include "xil_cache.h" +#include "bspconfig.h" /************************** Constant Definitions *****************************/ @@ -202,24 +216,38 @@ typedef struct { /** * This typedef contains scatter gather descriptor fields for ZDMA core. */ +#if defined (__ICCARM__) +#pragma pack(push, 1) +#endif typedef struct { u64 Address; /**< Address */ u32 Size; /**< Word2, Size of data */ u32 Cntl; /**< Word3 Control data */ u64 NextDscr; /**< Address of next descriptor */ u64 Reserved; /**< Reserved address */ +#if defined (__ICCARM__) +} XZDma_LlDscr ; +#pragma pack(pop) +#else } __attribute__ ((packed)) XZDma_LlDscr; - +#endif /******************************************************************************/ /** * This typedef contains Linear descriptor fields for ZDMA core. */ +#if defined (__ICCARM__) +#pragma pack(push, 1) +#endif typedef struct { u64 Address; /**< Address */ u32 Size; /**< Word3, Size of data */ u32 Cntl; /**< Word4, control data */ +#if defined (__ICCARM__) +}XZDma_LiDscr; +#pragma pack(pop) +#else } __attribute__ ((packed)) XZDma_LiDscr; - +#endif /******************************************************************************/ /** * @@ -282,6 +310,8 @@ typedef struct { u16 DeviceId; /**< Device Id of ZDMA */ u32 BaseAddress; /**< BaseAddress of ZDMA */ u8 DmaType; /**< Type of DMA */ + u8 IsCacheCoherent; /**< Describes whether Cache Coherent or not; + * Applicable only to A53 in EL1 NS mode */ } XZDma_Config; /******************************************************************************/ @@ -300,6 +330,8 @@ typedef struct { XZDma_Mode Mode; /**< Mode of ZDMA core to be operated */ u8 IsSgDma; /**< Is ZDMA core is in scatter gather or * not will be specified */ + u32 Slcr_adma; /**< Used to hold SLCR ADMA register + * contents */ XZDma_Descriptor Descriptor; /**< It contains information about * descriptors */ diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/xzdma_g.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/zdma_v1_5/src/xzdma_g.c similarity index 68% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/xzdma_g.c rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/zdma_v1_5/src/xzdma_g.c index 194aac12e..984bf9cbb 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/xzdma_g.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/zdma_v1_5/src/xzdma_g.c @@ -5,7 +5,7 @@ * Version: * DO NOT EDIT. * -* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.* +* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.* *Permission is hereby granted, free of charge, to any person obtaining a copy *of this software and associated documentation files (the Software), to deal *in the Software without restriction, including without limitation the rights @@ -44,87 +44,103 @@ * The configuration table for devices */ -XZDma_Config XZDma_ConfigTable[] = +XZDma_Config XZDma_ConfigTable[XPAR_XZDMA_NUM_INSTANCES] = { { XPAR_PSU_ADMA_0_DEVICE_ID, XPAR_PSU_ADMA_0_BASEADDR, - XPAR_PSU_ADMA_0_DMA_MODE + XPAR_PSU_ADMA_0_DMA_MODE, + XPAR_PSU_ADMA_0_IS_CACHE_COHERENT }, { XPAR_PSU_ADMA_1_DEVICE_ID, XPAR_PSU_ADMA_1_BASEADDR, - XPAR_PSU_ADMA_1_DMA_MODE + XPAR_PSU_ADMA_1_DMA_MODE, + XPAR_PSU_ADMA_1_IS_CACHE_COHERENT }, { XPAR_PSU_ADMA_2_DEVICE_ID, XPAR_PSU_ADMA_2_BASEADDR, - XPAR_PSU_ADMA_2_DMA_MODE + XPAR_PSU_ADMA_2_DMA_MODE, + XPAR_PSU_ADMA_2_IS_CACHE_COHERENT }, { XPAR_PSU_ADMA_3_DEVICE_ID, XPAR_PSU_ADMA_3_BASEADDR, - XPAR_PSU_ADMA_3_DMA_MODE + XPAR_PSU_ADMA_3_DMA_MODE, + XPAR_PSU_ADMA_3_IS_CACHE_COHERENT }, { XPAR_PSU_ADMA_4_DEVICE_ID, XPAR_PSU_ADMA_4_BASEADDR, - XPAR_PSU_ADMA_4_DMA_MODE + XPAR_PSU_ADMA_4_DMA_MODE, + XPAR_PSU_ADMA_4_IS_CACHE_COHERENT }, { XPAR_PSU_ADMA_5_DEVICE_ID, XPAR_PSU_ADMA_5_BASEADDR, - XPAR_PSU_ADMA_5_DMA_MODE + XPAR_PSU_ADMA_5_DMA_MODE, + XPAR_PSU_ADMA_5_IS_CACHE_COHERENT }, { XPAR_PSU_ADMA_6_DEVICE_ID, XPAR_PSU_ADMA_6_BASEADDR, - XPAR_PSU_ADMA_6_DMA_MODE + XPAR_PSU_ADMA_6_DMA_MODE, + XPAR_PSU_ADMA_6_IS_CACHE_COHERENT }, { XPAR_PSU_ADMA_7_DEVICE_ID, XPAR_PSU_ADMA_7_BASEADDR, - XPAR_PSU_ADMA_7_DMA_MODE + XPAR_PSU_ADMA_7_DMA_MODE, + XPAR_PSU_ADMA_7_IS_CACHE_COHERENT }, { XPAR_PSU_GDMA_0_DEVICE_ID, XPAR_PSU_GDMA_0_BASEADDR, - XPAR_PSU_GDMA_0_DMA_MODE + XPAR_PSU_GDMA_0_DMA_MODE, + XPAR_PSU_GDMA_0_IS_CACHE_COHERENT }, { XPAR_PSU_GDMA_1_DEVICE_ID, XPAR_PSU_GDMA_1_BASEADDR, - XPAR_PSU_GDMA_1_DMA_MODE + XPAR_PSU_GDMA_1_DMA_MODE, + XPAR_PSU_GDMA_1_IS_CACHE_COHERENT }, { XPAR_PSU_GDMA_2_DEVICE_ID, XPAR_PSU_GDMA_2_BASEADDR, - XPAR_PSU_GDMA_2_DMA_MODE + XPAR_PSU_GDMA_2_DMA_MODE, + XPAR_PSU_GDMA_2_IS_CACHE_COHERENT }, { XPAR_PSU_GDMA_3_DEVICE_ID, XPAR_PSU_GDMA_3_BASEADDR, - XPAR_PSU_GDMA_3_DMA_MODE + XPAR_PSU_GDMA_3_DMA_MODE, + XPAR_PSU_GDMA_3_IS_CACHE_COHERENT }, { XPAR_PSU_GDMA_4_DEVICE_ID, XPAR_PSU_GDMA_4_BASEADDR, - XPAR_PSU_GDMA_4_DMA_MODE + XPAR_PSU_GDMA_4_DMA_MODE, + XPAR_PSU_GDMA_4_IS_CACHE_COHERENT }, { XPAR_PSU_GDMA_5_DEVICE_ID, XPAR_PSU_GDMA_5_BASEADDR, - XPAR_PSU_GDMA_5_DMA_MODE + XPAR_PSU_GDMA_5_DMA_MODE, + XPAR_PSU_GDMA_5_IS_CACHE_COHERENT }, { XPAR_PSU_GDMA_6_DEVICE_ID, XPAR_PSU_GDMA_6_BASEADDR, - XPAR_PSU_GDMA_6_DMA_MODE + XPAR_PSU_GDMA_6_DMA_MODE, + XPAR_PSU_GDMA_6_IS_CACHE_COHERENT }, { XPAR_PSU_GDMA_7_DEVICE_ID, XPAR_PSU_GDMA_7_BASEADDR, - XPAR_PSU_GDMA_7_DMA_MODE + XPAR_PSU_GDMA_7_DMA_MODE, + XPAR_PSU_GDMA_7_IS_CACHE_COHERENT } }; diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/xzdma_hw.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/zdma_v1_5/src/xzdma_hw.h similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/xzdma_hw.h rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/zdma_v1_5/src/xzdma_hw.h index 85f630228..046921cf5 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/xzdma_hw.h +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/zdma_v1_5/src/xzdma_hw.h @@ -33,7 +33,7 @@ /** * * @file xzdma_hw.h -* @addtogroup zdma_v1_0 +* @addtogroup zdma_v1_5 * @{ * * This header file contains identifiers and register-level driver functions (or @@ -107,6 +107,7 @@ extern "C" { #define XZDMA_CH_CTRL2_OFFSET (0x200U) /*@}*/ +#define XZDMA_SLCR_SECURE_OFFSET (0xff4b0024) /** @name Interrupt Enable/Disable/Mask/Status registers bit masks and shifts * @{ */ @@ -240,7 +241,7 @@ extern "C" { * mask */ #define XZDMA_DSCR_ATTR_AXCOHRNT_SHIFT (8U) /**< Descriptor coherent shift */ -#define XZDMA_DSCR_ATTR_AXCACHE_SHIFT (7U) /**< Descriptor cache shift */ +#define XZDMA_DSCR_ATTR_AXCACHE_SHIFT (4U) /**< Descriptor cache shift */ #define XZDMA_DSCR_ATTR_RESET_VALUE (0x00000000U) /**< Dscr Attributes * reset value */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/zdma_v1_1/src/xzdma_intr.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/zdma_v1_5/src/xzdma_intr.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/zdma_v1_1/src/xzdma_intr.c rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/zdma_v1_5/src/xzdma_intr.c index e828d16a4..0e6af86e0 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/zdma_v1_1/src/xzdma_intr.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/zdma_v1_5/src/xzdma_intr.c @@ -33,7 +33,7 @@ /** * * @file xzdma_intr.c -* @addtogroup zdma_v1_0 +* @addtogroup zdma_v1_5 * @{ * * This file contains interrupt related functions of Xilinx ZDMA core. diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/xzdma_selftest.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/zdma_v1_5/src/xzdma_selftest.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/xzdma_selftest.c rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/zdma_v1_5/src/xzdma_selftest.c index 893a5402f..9e8b9dcad 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/xzdma_selftest.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/zdma_v1_5/src/xzdma_selftest.c @@ -33,7 +33,7 @@ /** * * @file xzdma_selftest.c -* @addtogroup zdma_v1_0 +* @addtogroup zdma_v1_5 * @{ * * This file contains the self-test function for the ZDMA core. diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/zdma_v1_1/src/xzdma_sinit.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/zdma_v1_5/src/xzdma_sinit.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/zdma_v1_1/src/xzdma_sinit.c rename to FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/zdma_v1_5/src/xzdma_sinit.c index ae2c44d1c..b033d46b5 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/zdma_v1_1/src/xzdma_sinit.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/zdma_v1_5/src/xzdma_sinit.c @@ -33,7 +33,7 @@ /** * * @file xzdma_sinit.c -* @addtogroup zdma_v1_0 +* @addtogroup zdma_v1_5 * @{ * * This file contains static initialization methods for Xilinx ZDMA core. diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/system.mss b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/system.mss index 664a10efe..7b11cbdd3 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/system.mss +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/system.mss @@ -4,7 +4,7 @@ BEGIN OS PARAMETER OS_NAME = standalone - PARAMETER OS_VER = 6.1 + PARAMETER OS_VER = 6.6 PARAMETER PROC_INSTANCE = psu_cortexa53_0 PARAMETER stdin = psu_uart_0 PARAMETER stdout = psu_uart_0 @@ -13,62 +13,62 @@ END BEGIN PROCESSOR PARAMETER DRIVER_NAME = cpu_cortexa53 - PARAMETER DRIVER_VER = 1.2 + PARAMETER DRIVER_VER = 1.5 PARAMETER HW_INSTANCE = psu_cortexa53_0 END BEGIN DRIVER PARAMETER DRIVER_NAME = scugic - PARAMETER DRIVER_VER = 3.5 + PARAMETER DRIVER_VER = 3.9 PARAMETER HW_INSTANCE = psu_acpu_gic END BEGIN DRIVER PARAMETER DRIVER_NAME = zdma - PARAMETER DRIVER_VER = 1.1 + PARAMETER DRIVER_VER = 1.5 PARAMETER HW_INSTANCE = psu_adma_0 END BEGIN DRIVER PARAMETER DRIVER_NAME = zdma - PARAMETER DRIVER_VER = 1.1 + PARAMETER DRIVER_VER = 1.5 PARAMETER HW_INSTANCE = psu_adma_1 END BEGIN DRIVER PARAMETER DRIVER_NAME = zdma - PARAMETER DRIVER_VER = 1.1 + PARAMETER DRIVER_VER = 1.5 PARAMETER HW_INSTANCE = psu_adma_2 END BEGIN DRIVER PARAMETER DRIVER_NAME = zdma - PARAMETER DRIVER_VER = 1.1 + PARAMETER DRIVER_VER = 1.5 PARAMETER HW_INSTANCE = psu_adma_3 END BEGIN DRIVER PARAMETER DRIVER_NAME = zdma - PARAMETER DRIVER_VER = 1.1 + PARAMETER DRIVER_VER = 1.5 PARAMETER HW_INSTANCE = psu_adma_4 END BEGIN DRIVER PARAMETER DRIVER_NAME = zdma - PARAMETER DRIVER_VER = 1.1 + PARAMETER DRIVER_VER = 1.5 PARAMETER HW_INSTANCE = psu_adma_5 END BEGIN DRIVER PARAMETER DRIVER_NAME = zdma - PARAMETER DRIVER_VER = 1.1 + PARAMETER DRIVER_VER = 1.5 PARAMETER HW_INSTANCE = psu_adma_6 END BEGIN DRIVER PARAMETER DRIVER_NAME = zdma - PARAMETER DRIVER_VER = 1.1 + PARAMETER DRIVER_VER = 1.5 PARAMETER HW_INSTANCE = psu_adma_7 END @@ -116,31 +116,31 @@ END BEGIN DRIVER PARAMETER DRIVER_NAME = sysmonpsu - PARAMETER DRIVER_VER = 2.0 + PARAMETER DRIVER_VER = 2.3 PARAMETER HW_INSTANCE = psu_ams END BEGIN DRIVER PARAMETER DRIVER_NAME = axipmon - PARAMETER DRIVER_VER = 6.5 + PARAMETER DRIVER_VER = 6.6 PARAMETER HW_INSTANCE = psu_apm_0 END BEGIN DRIVER PARAMETER DRIVER_NAME = axipmon - PARAMETER DRIVER_VER = 6.5 + PARAMETER DRIVER_VER = 6.6 PARAMETER HW_INSTANCE = psu_apm_1 END BEGIN DRIVER PARAMETER DRIVER_NAME = axipmon - PARAMETER DRIVER_VER = 6.5 + PARAMETER DRIVER_VER = 6.6 PARAMETER HW_INSTANCE = psu_apm_2 END BEGIN DRIVER PARAMETER DRIVER_NAME = axipmon - PARAMETER DRIVER_VER = 6.5 + PARAMETER DRIVER_VER = 6.6 PARAMETER HW_INSTANCE = psu_apm_5 END @@ -170,13 +170,13 @@ END BEGIN DRIVER PARAMETER DRIVER_NAME = coresightps_dcc - PARAMETER DRIVER_VER = 1.3 + PARAMETER DRIVER_VER = 1.4 PARAMETER HW_INSTANCE = psu_coresight_0 END BEGIN DRIVER - PARAMETER DRIVER_NAME = generic - PARAMETER DRIVER_VER = 2.0 + PARAMETER DRIVER_NAME = resetps + PARAMETER DRIVER_VER = 1.0 PARAMETER HW_INSTANCE = psu_crf_apb END @@ -188,10 +188,16 @@ END BEGIN DRIVER PARAMETER DRIVER_NAME = csudma - PARAMETER DRIVER_VER = 1.1 + PARAMETER DRIVER_VER = 1.2 PARAMETER HW_INSTANCE = psu_csudma END +BEGIN DRIVER + PARAMETER DRIVER_NAME = generic + PARAMETER DRIVER_VER = 2.0 + PARAMETER HW_INSTANCE = psu_ctrl_ipi +END + BEGIN DRIVER PARAMETER DRIVER_NAME = generic PARAMETER DRIVER_VER = 2.0 @@ -259,14 +265,14 @@ BEGIN DRIVER END BEGIN DRIVER - PARAMETER DRIVER_NAME = generic - PARAMETER DRIVER_VER = 2.0 + PARAMETER DRIVER_NAME = avbuf + PARAMETER DRIVER_VER = 2.1 PARAMETER HW_INSTANCE = psu_dp END BEGIN DRIVER - PARAMETER DRIVER_NAME = generic - PARAMETER DRIVER_VER = 2.0 + PARAMETER DRIVER_NAME = dpdma + PARAMETER DRIVER_VER = 1.0 PARAMETER HW_INSTANCE = psu_dpdma END @@ -278,7 +284,7 @@ END BEGIN DRIVER PARAMETER DRIVER_NAME = emacps - PARAMETER DRIVER_VER = 3.3 + PARAMETER DRIVER_VER = 3.7 PARAMETER HW_INSTANCE = psu_ethernet_3 END @@ -314,55 +320,55 @@ END BEGIN DRIVER PARAMETER DRIVER_NAME = zdma - PARAMETER DRIVER_VER = 1.1 + PARAMETER DRIVER_VER = 1.5 PARAMETER HW_INSTANCE = psu_gdma_0 END BEGIN DRIVER PARAMETER DRIVER_NAME = zdma - PARAMETER DRIVER_VER = 1.1 + PARAMETER DRIVER_VER = 1.5 PARAMETER HW_INSTANCE = psu_gdma_1 END BEGIN DRIVER PARAMETER DRIVER_NAME = zdma - PARAMETER DRIVER_VER = 1.1 + PARAMETER DRIVER_VER = 1.5 PARAMETER HW_INSTANCE = psu_gdma_2 END BEGIN DRIVER PARAMETER DRIVER_NAME = zdma - PARAMETER DRIVER_VER = 1.1 + PARAMETER DRIVER_VER = 1.5 PARAMETER HW_INSTANCE = psu_gdma_3 END BEGIN DRIVER PARAMETER DRIVER_NAME = zdma - PARAMETER DRIVER_VER = 1.1 + PARAMETER DRIVER_VER = 1.5 PARAMETER HW_INSTANCE = psu_gdma_4 END BEGIN DRIVER PARAMETER DRIVER_NAME = zdma - PARAMETER DRIVER_VER = 1.1 + PARAMETER DRIVER_VER = 1.5 PARAMETER HW_INSTANCE = psu_gdma_5 END BEGIN DRIVER PARAMETER DRIVER_NAME = zdma - PARAMETER DRIVER_VER = 1.1 + PARAMETER DRIVER_VER = 1.5 PARAMETER HW_INSTANCE = psu_gdma_6 END BEGIN DRIVER PARAMETER DRIVER_NAME = zdma - PARAMETER DRIVER_VER = 1.1 + PARAMETER DRIVER_VER = 1.5 PARAMETER HW_INSTANCE = psu_gdma_7 END BEGIN DRIVER PARAMETER DRIVER_NAME = gpiops - PARAMETER DRIVER_VER = 3.1 + PARAMETER DRIVER_VER = 3.3 PARAMETER HW_INSTANCE = psu_gpio_0 END @@ -374,13 +380,13 @@ END BEGIN DRIVER PARAMETER DRIVER_NAME = iicps - PARAMETER DRIVER_VER = 3.4 + PARAMETER DRIVER_VER = 3.6 PARAMETER HW_INSTANCE = psu_i2c_0 END BEGIN DRIVER PARAMETER DRIVER_NAME = iicps - PARAMETER DRIVER_VER = 3.4 + PARAMETER DRIVER_VER = 3.6 PARAMETER HW_INSTANCE = psu_i2c_1 END @@ -410,7 +416,7 @@ END BEGIN DRIVER PARAMETER DRIVER_NAME = ipipsu - PARAMETER DRIVER_VER = 2.1 + PARAMETER DRIVER_VER = 2.3 PARAMETER HW_INSTANCE = psu_ipi_0 END @@ -444,6 +450,12 @@ BEGIN DRIVER PARAMETER HW_INSTANCE = psu_mbistjtag END +BEGIN DRIVER + PARAMETER DRIVER_NAME = generic + PARAMETER DRIVER_VER = 2.0 + PARAMETER HW_INSTANCE = psu_message_buffers +END + BEGIN DRIVER PARAMETER DRIVER_NAME = generic PARAMETER DRIVER_VER = 2.0 @@ -483,7 +495,13 @@ END BEGIN DRIVER PARAMETER DRIVER_NAME = generic PARAMETER DRIVER_VER = 2.0 - PARAMETER HW_INSTANCE = psu_pcie_high + PARAMETER HW_INSTANCE = psu_pcie_high1 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = generic + PARAMETER DRIVER_VER = 2.0 + PARAMETER HW_INSTANCE = psu_pcie_high2 END BEGIN DRIVER @@ -498,15 +516,9 @@ BEGIN DRIVER PARAMETER HW_INSTANCE = psu_pmu_global_0 END -BEGIN DRIVER - PARAMETER DRIVER_NAME = generic - PARAMETER DRIVER_VER = 2.0 - PARAMETER HW_INSTANCE = psu_pmu_iomodule -END - BEGIN DRIVER PARAMETER DRIVER_NAME = qspipsu - PARAMETER DRIVER_VER = 1.3 + PARAMETER DRIVER_VER = 1.7 PARAMETER HW_INSTANCE = psu_qspi_0 END @@ -548,7 +560,7 @@ END BEGIN DRIVER PARAMETER DRIVER_NAME = scugic - PARAMETER DRIVER_VER = 3.5 + PARAMETER DRIVER_VER = 3.9 PARAMETER HW_INSTANCE = psu_rcpu_gic END @@ -566,7 +578,7 @@ END BEGIN DRIVER PARAMETER DRIVER_NAME = rtcpsu - PARAMETER DRIVER_VER = 1.3 + PARAMETER DRIVER_VER = 1.5 PARAMETER HW_INSTANCE = psu_rtc END @@ -578,7 +590,7 @@ END BEGIN DRIVER PARAMETER DRIVER_NAME = sdps - PARAMETER DRIVER_VER = 3.1 + PARAMETER DRIVER_VER = 3.4 PARAMETER HW_INSTANCE = psu_sd_1 END @@ -608,46 +620,52 @@ END BEGIN DRIVER PARAMETER DRIVER_NAME = ttcps - PARAMETER DRIVER_VER = 3.2 + PARAMETER DRIVER_VER = 3.5 PARAMETER HW_INSTANCE = psu_ttc_0 END BEGIN DRIVER PARAMETER DRIVER_NAME = ttcps - PARAMETER DRIVER_VER = 3.2 + PARAMETER DRIVER_VER = 3.5 PARAMETER HW_INSTANCE = psu_ttc_1 END BEGIN DRIVER PARAMETER DRIVER_NAME = ttcps - PARAMETER DRIVER_VER = 3.2 + PARAMETER DRIVER_VER = 3.5 PARAMETER HW_INSTANCE = psu_ttc_2 END BEGIN DRIVER PARAMETER DRIVER_NAME = ttcps - PARAMETER DRIVER_VER = 3.2 + PARAMETER DRIVER_VER = 3.5 PARAMETER HW_INSTANCE = psu_ttc_3 END BEGIN DRIVER PARAMETER DRIVER_NAME = uartps - PARAMETER DRIVER_VER = 3.3 + PARAMETER DRIVER_VER = 3.6 PARAMETER HW_INSTANCE = psu_uart_0 END BEGIN DRIVER PARAMETER DRIVER_NAME = uartps - PARAMETER DRIVER_VER = 3.3 + PARAMETER DRIVER_VER = 3.6 PARAMETER HW_INSTANCE = psu_uart_1 END BEGIN DRIVER - PARAMETER DRIVER_NAME = usbpsu - PARAMETER DRIVER_VER = 1.1 + PARAMETER DRIVER_NAME = generic + PARAMETER DRIVER_VER = 2.0 PARAMETER HW_INSTANCE = psu_usb_0 END +BEGIN DRIVER + PARAMETER DRIVER_NAME = usbpsu + PARAMETER DRIVER_VER = 1.4 + PARAMETER HW_INSTANCE = psu_usb_xhci_0 +END + BEGIN DRIVER PARAMETER DRIVER_NAME = wdtps PARAMETER DRIVER_VER = 3.0 diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init.c index f206bc7bf..5331ca872 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init.c @@ -34,21100 +34,21787 @@ * * @file psu_init.c * -* This file is automatically generated +* This file is automatically generated * *****************************************************************************/ #include #include #include "psu_init.h" +#define DPLL_CFG_LOCK_DLY 63 +#define DPLL_CFG_LOCK_CNT 625 +#define DPLL_CFG_LFHF 3 +#define DPLL_CFG_CP 3 +#define DPLL_CFG_RES 2 -int mask_pollOnValue(u32 add , u32 mask, u32 value ); +static int mask_pollOnValue(u32 add, u32 mask, u32 value); -int mask_poll(u32 add , u32 mask ); +static int mask_poll(u32 add, u32 mask); -void mask_delay(u32 delay); +static void mask_delay(u32 delay); -u32 mask_read(u32 add , u32 mask ); +static u32 mask_read(u32 add, u32 mask); -static void PSU_Mask_Write (unsigned long offset, unsigned long mask, unsigned long val) +static void dpll_prog(int ddr_pll_fbdiv, int d_lock_dly, + int d_lock_cnt, int d_lfhf, int d_cp, int d_res); + +static +void PSU_Mask_Write(unsigned long offset, unsigned long mask, + unsigned long val) { unsigned long RegVal = 0x0; - RegVal = Xil_In32 (offset); + + RegVal = Xil_In32(offset); RegVal &= ~(mask); RegVal |= (val & mask); - Xil_Out32 (offset, RegVal); + Xil_Out32(offset, RegVal); } - void prog_reg (unsigned long addr, unsigned long mask, unsigned long shift, unsigned long value) { - int rdata =0; + void prog_reg(unsigned long addr, unsigned long mask, + unsigned long shift, unsigned long value) { + int rdata = 0; + rdata = Xil_In32(addr); rdata = rdata & (~mask); rdata = rdata | (value << shift); - Xil_Out32(addr,rdata); - } - -unsigned long psu_pll_init_data() { - // : RPLL INIT - /*Register : RPLL_CFG @ 0XFF5E0034

- - PLL loop filter resistor control - PSU_CRL_APB_RPLL_CFG_RES 0x2 - - PLL charge pump control - PSU_CRL_APB_RPLL_CFG_CP 0x3 - - PLL loop filter high frequency capacitor control - PSU_CRL_APB_RPLL_CFG_LFHF 0x3 - - Lock circuit counter setting - PSU_CRL_APB_RPLL_CFG_LOCK_CNT 0x258 - - Lock circuit configuration settings for lock windowsize - PSU_CRL_APB_RPLL_CFG_LOCK_DLY 0x3f - - Helper data. Values are to be looked up in a table from Data Sheet - (OFFSET, MASK, VALUE) (0XFF5E0034, 0xFE7FEDEFU ,0x7E4B0C62U) - RegMask = (CRL_APB_RPLL_CFG_RES_MASK | CRL_APB_RPLL_CFG_CP_MASK | CRL_APB_RPLL_CFG_LFHF_MASK | CRL_APB_RPLL_CFG_LOCK_CNT_MASK | CRL_APB_RPLL_CFG_LOCK_DLY_MASK | 0 ); - - RegVal = ((0x00000002U << CRL_APB_RPLL_CFG_RES_SHIFT - | 0x00000003U << CRL_APB_RPLL_CFG_CP_SHIFT - | 0x00000003U << CRL_APB_RPLL_CFG_LFHF_SHIFT - | 0x00000258U << CRL_APB_RPLL_CFG_LOCK_CNT_SHIFT - | 0x0000003FU << CRL_APB_RPLL_CFG_LOCK_DLY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RPLL_CFG_OFFSET ,0xFE7FEDEFU ,0x7E4B0C62U); - /*############################################################################################################################ */ - - // : UPDATE FB_DIV - /*Register : RPLL_CTRL @ 0XFF5E0030

- - Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_ - ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source - PSU_CRL_APB_RPLL_CTRL_PRE_SRC 0x0 - - The integer portion of the feedback divider to the PLL - PSU_CRL_APB_RPLL_CTRL_FBDIV 0x48 - - This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency - PSU_CRL_APB_RPLL_CTRL_DIV2 0x1 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFF5E0030, 0x00717F00U ,0x00014800U) - RegMask = (CRL_APB_RPLL_CTRL_PRE_SRC_MASK | CRL_APB_RPLL_CTRL_FBDIV_MASK | CRL_APB_RPLL_CTRL_DIV2_MASK | 0 ); - - RegVal = ((0x00000000U << CRL_APB_RPLL_CTRL_PRE_SRC_SHIFT - | 0x00000048U << CRL_APB_RPLL_CTRL_FBDIV_SHIFT - | 0x00000001U << CRL_APB_RPLL_CTRL_DIV2_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RPLL_CTRL_OFFSET ,0x00717F00U ,0x00014800U); - /*############################################################################################################################ */ - - // : BY PASS PLL - /*Register : RPLL_CTRL @ 0XFF5E0030

- - Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_RPLL_CTRL_BYPASS 1 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFF5E0030, 0x00000008U ,0x00000008U) - RegMask = (CRL_APB_RPLL_CTRL_BYPASS_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_RPLL_CTRL_BYPASS_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RPLL_CTRL_OFFSET ,0x00000008U ,0x00000008U); - /*############################################################################################################################ */ - - // : ASSERT RESET - /*Register : RPLL_CTRL @ 0XFF5E0030

- - Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS. - PSU_CRL_APB_RPLL_CTRL_RESET 1 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFF5E0030, 0x00000001U ,0x00000001U) - RegMask = (CRL_APB_RPLL_CTRL_RESET_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_RPLL_CTRL_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RPLL_CTRL_OFFSET ,0x00000001U ,0x00000001U); - /*############################################################################################################################ */ - - // : DEASSERT RESET - /*Register : RPLL_CTRL @ 0XFF5E0030

- - Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS. - PSU_CRL_APB_RPLL_CTRL_RESET 0 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFF5E0030, 0x00000001U ,0x00000000U) - RegMask = (CRL_APB_RPLL_CTRL_RESET_MASK | 0 ); - - RegVal = ((0x00000000U << CRL_APB_RPLL_CTRL_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RPLL_CTRL_OFFSET ,0x00000001U ,0x00000000U); - /*############################################################################################################################ */ - - // : CHECK PLL STATUS - /*Register : PLL_STATUS @ 0XFF5E0040

- - RPLL is locked - PSU_CRL_APB_PLL_STATUS_RPLL_LOCK 1 - (OFFSET, MASK, VALUE) (0XFF5E0040, 0x00000002U ,0x00000002U) */ - mask_poll(CRL_APB_PLL_STATUS_OFFSET,0x00000002U); - - /*############################################################################################################################ */ - - // : REMOVE PLL BY PASS - /*Register : RPLL_CTRL @ 0XFF5E0030

- - Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_RPLL_CTRL_BYPASS 0 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFF5E0030, 0x00000008U ,0x00000000U) - RegMask = (CRL_APB_RPLL_CTRL_BYPASS_MASK | 0 ); - - RegVal = ((0x00000000U << CRL_APB_RPLL_CTRL_BYPASS_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RPLL_CTRL_OFFSET ,0x00000008U ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : RPLL_TO_FPD_CTRL @ 0XFF5E0048

- - Divisor value for this clock. - PSU_CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0 0x3 - - Control for a clock that will be generated in the LPD, but used in the FPD as a clock source for the peripheral clock muxes. - (OFFSET, MASK, VALUE) (0XFF5E0048, 0x00003F00U ,0x00000300U) - RegMask = (CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_MASK | 0 ); - - RegVal = ((0x00000003U << CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RPLL_TO_FPD_CTRL_OFFSET ,0x00003F00U ,0x00000300U); - /*############################################################################################################################ */ - - // : RPLL FRAC CFG - /*Register : RPLL_FRAC_CFG @ 0XFF5E0038

- - Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona - mode and uses DATA of this register for the fractional portion of the feedback divider. - PSU_CRL_APB_RPLL_FRAC_CFG_ENABLED 0x0 - - Fractional value for the Feedback value. - PSU_CRL_APB_RPLL_FRAC_CFG_DATA 0x0 - - Fractional control for the PLL - (OFFSET, MASK, VALUE) (0XFF5E0038, 0x8000FFFFU ,0x00000000U) - RegMask = (CRL_APB_RPLL_FRAC_CFG_ENABLED_MASK | CRL_APB_RPLL_FRAC_CFG_DATA_MASK | 0 ); - - RegVal = ((0x00000000U << CRL_APB_RPLL_FRAC_CFG_ENABLED_SHIFT - | 0x00000000U << CRL_APB_RPLL_FRAC_CFG_DATA_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RPLL_FRAC_CFG_OFFSET ,0x8000FFFFU ,0x00000000U); - /*############################################################################################################################ */ - - // : IOPLL INIT - /*Register : IOPLL_CFG @ 0XFF5E0024

- - PLL loop filter resistor control - PSU_CRL_APB_IOPLL_CFG_RES 0xc - - PLL charge pump control - PSU_CRL_APB_IOPLL_CFG_CP 0x3 - - PLL loop filter high frequency capacitor control - PSU_CRL_APB_IOPLL_CFG_LFHF 0x3 - - Lock circuit counter setting - PSU_CRL_APB_IOPLL_CFG_LOCK_CNT 0x339 - - Lock circuit configuration settings for lock windowsize - PSU_CRL_APB_IOPLL_CFG_LOCK_DLY 0x3f - - Helper data. Values are to be looked up in a table from Data Sheet - (OFFSET, MASK, VALUE) (0XFF5E0024, 0xFE7FEDEFU ,0x7E672C6CU) - RegMask = (CRL_APB_IOPLL_CFG_RES_MASK | CRL_APB_IOPLL_CFG_CP_MASK | CRL_APB_IOPLL_CFG_LFHF_MASK | CRL_APB_IOPLL_CFG_LOCK_CNT_MASK | CRL_APB_IOPLL_CFG_LOCK_DLY_MASK | 0 ); - - RegVal = ((0x0000000CU << CRL_APB_IOPLL_CFG_RES_SHIFT - | 0x00000003U << CRL_APB_IOPLL_CFG_CP_SHIFT - | 0x00000003U << CRL_APB_IOPLL_CFG_LFHF_SHIFT - | 0x00000339U << CRL_APB_IOPLL_CFG_LOCK_CNT_SHIFT - | 0x0000003FU << CRL_APB_IOPLL_CFG_LOCK_DLY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_IOPLL_CFG_OFFSET ,0xFE7FEDEFU ,0x7E672C6CU); - /*############################################################################################################################ */ - - // : UPDATE FB_DIV - /*Register : IOPLL_CTRL @ 0XFF5E0020

- - Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_ - ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source - PSU_CRL_APB_IOPLL_CTRL_PRE_SRC 0x0 - - The integer portion of the feedback divider to the PLL - PSU_CRL_APB_IOPLL_CTRL_FBDIV 0x2d - - This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency - PSU_CRL_APB_IOPLL_CTRL_DIV2 0x0 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFF5E0020, 0x00717F00U ,0x00002D00U) - RegMask = (CRL_APB_IOPLL_CTRL_PRE_SRC_MASK | CRL_APB_IOPLL_CTRL_FBDIV_MASK | CRL_APB_IOPLL_CTRL_DIV2_MASK | 0 ); - - RegVal = ((0x00000000U << CRL_APB_IOPLL_CTRL_PRE_SRC_SHIFT - | 0x0000002DU << CRL_APB_IOPLL_CTRL_FBDIV_SHIFT - | 0x00000000U << CRL_APB_IOPLL_CTRL_DIV2_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_IOPLL_CTRL_OFFSET ,0x00717F00U ,0x00002D00U); - /*############################################################################################################################ */ - - // : BY PASS PLL - /*Register : IOPLL_CTRL @ 0XFF5E0020

- - Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_IOPLL_CTRL_BYPASS 1 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFF5E0020, 0x00000008U ,0x00000008U) - RegMask = (CRL_APB_IOPLL_CTRL_BYPASS_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_IOPLL_CTRL_BYPASS_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_IOPLL_CTRL_OFFSET ,0x00000008U ,0x00000008U); - /*############################################################################################################################ */ - - // : ASSERT RESET - /*Register : IOPLL_CTRL @ 0XFF5E0020

- - Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS. - PSU_CRL_APB_IOPLL_CTRL_RESET 1 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFF5E0020, 0x00000001U ,0x00000001U) - RegMask = (CRL_APB_IOPLL_CTRL_RESET_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_IOPLL_CTRL_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_IOPLL_CTRL_OFFSET ,0x00000001U ,0x00000001U); - /*############################################################################################################################ */ - - // : DEASSERT RESET - /*Register : IOPLL_CTRL @ 0XFF5E0020

- - Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS. - PSU_CRL_APB_IOPLL_CTRL_RESET 0 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFF5E0020, 0x00000001U ,0x00000000U) - RegMask = (CRL_APB_IOPLL_CTRL_RESET_MASK | 0 ); - - RegVal = ((0x00000000U << CRL_APB_IOPLL_CTRL_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_IOPLL_CTRL_OFFSET ,0x00000001U ,0x00000000U); - /*############################################################################################################################ */ - - // : CHECK PLL STATUS - /*Register : PLL_STATUS @ 0XFF5E0040

- - IOPLL is locked - PSU_CRL_APB_PLL_STATUS_IOPLL_LOCK 1 - (OFFSET, MASK, VALUE) (0XFF5E0040, 0x00000001U ,0x00000001U) */ - mask_poll(CRL_APB_PLL_STATUS_OFFSET,0x00000001U); - - /*############################################################################################################################ */ - - // : REMOVE PLL BY PASS - /*Register : IOPLL_CTRL @ 0XFF5E0020

- - Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_IOPLL_CTRL_BYPASS 0 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFF5E0020, 0x00000008U ,0x00000000U) - RegMask = (CRL_APB_IOPLL_CTRL_BYPASS_MASK | 0 ); - - RegVal = ((0x00000000U << CRL_APB_IOPLL_CTRL_BYPASS_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_IOPLL_CTRL_OFFSET ,0x00000008U ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : IOPLL_TO_FPD_CTRL @ 0XFF5E0044

- - Divisor value for this clock. - PSU_CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0 0x3 - - Control for a clock that will be generated in the LPD, but used in the FPD as a clock source for the peripheral clock muxes. - (OFFSET, MASK, VALUE) (0XFF5E0044, 0x00003F00U ,0x00000300U) - RegMask = (CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_MASK | 0 ); - - RegVal = ((0x00000003U << CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_IOPLL_TO_FPD_CTRL_OFFSET ,0x00003F00U ,0x00000300U); - /*############################################################################################################################ */ - - // : IOPLL FRAC CFG - /*Register : IOPLL_FRAC_CFG @ 0XFF5E0028

- - Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona - mode and uses DATA of this register for the fractional portion of the feedback divider. - PSU_CRL_APB_IOPLL_FRAC_CFG_ENABLED 0x0 - - Fractional value for the Feedback value. - PSU_CRL_APB_IOPLL_FRAC_CFG_DATA 0x0 - - Fractional control for the PLL - (OFFSET, MASK, VALUE) (0XFF5E0028, 0x8000FFFFU ,0x00000000U) - RegMask = (CRL_APB_IOPLL_FRAC_CFG_ENABLED_MASK | CRL_APB_IOPLL_FRAC_CFG_DATA_MASK | 0 ); - - RegVal = ((0x00000000U << CRL_APB_IOPLL_FRAC_CFG_ENABLED_SHIFT - | 0x00000000U << CRL_APB_IOPLL_FRAC_CFG_DATA_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_IOPLL_FRAC_CFG_OFFSET ,0x8000FFFFU ,0x00000000U); - /*############################################################################################################################ */ - - // : APU_PLL INIT - /*Register : APLL_CFG @ 0XFD1A0024

- - PLL loop filter resistor control - PSU_CRF_APB_APLL_CFG_RES 0x2 - - PLL charge pump control - PSU_CRF_APB_APLL_CFG_CP 0x3 - - PLL loop filter high frequency capacitor control - PSU_CRF_APB_APLL_CFG_LFHF 0x3 - - Lock circuit counter setting - PSU_CRF_APB_APLL_CFG_LOCK_CNT 0x258 - - Lock circuit configuration settings for lock windowsize - PSU_CRF_APB_APLL_CFG_LOCK_DLY 0x3f - - Helper data. Values are to be looked up in a table from Data Sheet - (OFFSET, MASK, VALUE) (0XFD1A0024, 0xFE7FEDEFU ,0x7E4B0C62U) - RegMask = (CRF_APB_APLL_CFG_RES_MASK | CRF_APB_APLL_CFG_CP_MASK | CRF_APB_APLL_CFG_LFHF_MASK | CRF_APB_APLL_CFG_LOCK_CNT_MASK | CRF_APB_APLL_CFG_LOCK_DLY_MASK | 0 ); - - RegVal = ((0x00000002U << CRF_APB_APLL_CFG_RES_SHIFT - | 0x00000003U << CRF_APB_APLL_CFG_CP_SHIFT - | 0x00000003U << CRF_APB_APLL_CFG_LFHF_SHIFT - | 0x00000258U << CRF_APB_APLL_CFG_LOCK_CNT_SHIFT - | 0x0000003FU << CRF_APB_APLL_CFG_LOCK_DLY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_APLL_CFG_OFFSET ,0xFE7FEDEFU ,0x7E4B0C62U); - /*############################################################################################################################ */ - - // : UPDATE FB_DIV - /*Register : APLL_CTRL @ 0XFD1A0020

- - Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_ - ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source - PSU_CRF_APB_APLL_CTRL_PRE_SRC 0x0 - - The integer portion of the feedback divider to the PLL - PSU_CRF_APB_APLL_CTRL_FBDIV 0x42 - - This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency - PSU_CRF_APB_APLL_CTRL_DIV2 0x1 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFD1A0020, 0x00717F00U ,0x00014200U) - RegMask = (CRF_APB_APLL_CTRL_PRE_SRC_MASK | CRF_APB_APLL_CTRL_FBDIV_MASK | CRF_APB_APLL_CTRL_DIV2_MASK | 0 ); - - RegVal = ((0x00000000U << CRF_APB_APLL_CTRL_PRE_SRC_SHIFT - | 0x00000042U << CRF_APB_APLL_CTRL_FBDIV_SHIFT - | 0x00000001U << CRF_APB_APLL_CTRL_DIV2_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_APLL_CTRL_OFFSET ,0x00717F00U ,0x00014200U); - /*############################################################################################################################ */ - - // : BY PASS PLL - /*Register : APLL_CTRL @ 0XFD1A0020

- - Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.) - PSU_CRF_APB_APLL_CTRL_BYPASS 1 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFD1A0020, 0x00000008U ,0x00000008U) - RegMask = (CRF_APB_APLL_CTRL_BYPASS_MASK | 0 ); - - RegVal = ((0x00000001U << CRF_APB_APLL_CTRL_BYPASS_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_APLL_CTRL_OFFSET ,0x00000008U ,0x00000008U); - /*############################################################################################################################ */ - - // : ASSERT RESET - /*Register : APLL_CTRL @ 0XFD1A0020

- - Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS. - PSU_CRF_APB_APLL_CTRL_RESET 1 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFD1A0020, 0x00000001U ,0x00000001U) - RegMask = (CRF_APB_APLL_CTRL_RESET_MASK | 0 ); - - RegVal = ((0x00000001U << CRF_APB_APLL_CTRL_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_APLL_CTRL_OFFSET ,0x00000001U ,0x00000001U); - /*############################################################################################################################ */ - - // : DEASSERT RESET - /*Register : APLL_CTRL @ 0XFD1A0020

- - Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS. - PSU_CRF_APB_APLL_CTRL_RESET 0 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFD1A0020, 0x00000001U ,0x00000000U) - RegMask = (CRF_APB_APLL_CTRL_RESET_MASK | 0 ); - - RegVal = ((0x00000000U << CRF_APB_APLL_CTRL_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_APLL_CTRL_OFFSET ,0x00000001U ,0x00000000U); - /*############################################################################################################################ */ - - // : CHECK PLL STATUS - /*Register : PLL_STATUS @ 0XFD1A0044

- - APLL is locked - PSU_CRF_APB_PLL_STATUS_APLL_LOCK 1 - (OFFSET, MASK, VALUE) (0XFD1A0044, 0x00000001U ,0x00000001U) */ - mask_poll(CRF_APB_PLL_STATUS_OFFSET,0x00000001U); - - /*############################################################################################################################ */ - - // : REMOVE PLL BY PASS - /*Register : APLL_CTRL @ 0XFD1A0020

- - Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.) - PSU_CRF_APB_APLL_CTRL_BYPASS 0 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFD1A0020, 0x00000008U ,0x00000000U) - RegMask = (CRF_APB_APLL_CTRL_BYPASS_MASK | 0 ); - - RegVal = ((0x00000000U << CRF_APB_APLL_CTRL_BYPASS_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_APLL_CTRL_OFFSET ,0x00000008U ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : APLL_TO_LPD_CTRL @ 0XFD1A0048

- - Divisor value for this clock. - PSU_CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0 0x3 - - Control for a clock that will be generated in the FPD, but used in the LPD as a clock source for the peripheral clock muxes. - (OFFSET, MASK, VALUE) (0XFD1A0048, 0x00003F00U ,0x00000300U) - RegMask = (CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_MASK | 0 ); - - RegVal = ((0x00000003U << CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_APLL_TO_LPD_CTRL_OFFSET ,0x00003F00U ,0x00000300U); - /*############################################################################################################################ */ - - // : APLL FRAC CFG - /*Register : APLL_FRAC_CFG @ 0XFD1A0028

- - Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona - mode and uses DATA of this register for the fractional portion of the feedback divider. - PSU_CRF_APB_APLL_FRAC_CFG_ENABLED 0x0 - - Fractional value for the Feedback value. - PSU_CRF_APB_APLL_FRAC_CFG_DATA 0x0 - - Fractional control for the PLL - (OFFSET, MASK, VALUE) (0XFD1A0028, 0x8000FFFFU ,0x00000000U) - RegMask = (CRF_APB_APLL_FRAC_CFG_ENABLED_MASK | CRF_APB_APLL_FRAC_CFG_DATA_MASK | 0 ); - - RegVal = ((0x00000000U << CRF_APB_APLL_FRAC_CFG_ENABLED_SHIFT - | 0x00000000U << CRF_APB_APLL_FRAC_CFG_DATA_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_APLL_FRAC_CFG_OFFSET ,0x8000FFFFU ,0x00000000U); - /*############################################################################################################################ */ - - // : DDR_PLL INIT - /*Register : DPLL_CFG @ 0XFD1A0030

- - PLL loop filter resistor control - PSU_CRF_APB_DPLL_CFG_RES 0x2 - - PLL charge pump control - PSU_CRF_APB_DPLL_CFG_CP 0x3 - - PLL loop filter high frequency capacitor control - PSU_CRF_APB_DPLL_CFG_LFHF 0x3 - - Lock circuit counter setting - PSU_CRF_APB_DPLL_CFG_LOCK_CNT 0x258 - - Lock circuit configuration settings for lock windowsize - PSU_CRF_APB_DPLL_CFG_LOCK_DLY 0x3f - - Helper data. Values are to be looked up in a table from Data Sheet - (OFFSET, MASK, VALUE) (0XFD1A0030, 0xFE7FEDEFU ,0x7E4B0C62U) - RegMask = (CRF_APB_DPLL_CFG_RES_MASK | CRF_APB_DPLL_CFG_CP_MASK | CRF_APB_DPLL_CFG_LFHF_MASK | CRF_APB_DPLL_CFG_LOCK_CNT_MASK | CRF_APB_DPLL_CFG_LOCK_DLY_MASK | 0 ); - - RegVal = ((0x00000002U << CRF_APB_DPLL_CFG_RES_SHIFT - | 0x00000003U << CRF_APB_DPLL_CFG_CP_SHIFT - | 0x00000003U << CRF_APB_DPLL_CFG_LFHF_SHIFT - | 0x00000258U << CRF_APB_DPLL_CFG_LOCK_CNT_SHIFT - | 0x0000003FU << CRF_APB_DPLL_CFG_LOCK_DLY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_DPLL_CFG_OFFSET ,0xFE7FEDEFU ,0x7E4B0C62U); - /*############################################################################################################################ */ - - // : UPDATE FB_DIV - /*Register : DPLL_CTRL @ 0XFD1A002C

- - Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_ - ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source - PSU_CRF_APB_DPLL_CTRL_PRE_SRC 0x0 - - The integer portion of the feedback divider to the PLL - PSU_CRF_APB_DPLL_CTRL_FBDIV 0x40 - - This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency - PSU_CRF_APB_DPLL_CTRL_DIV2 0x1 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFD1A002C, 0x00717F00U ,0x00014000U) - RegMask = (CRF_APB_DPLL_CTRL_PRE_SRC_MASK | CRF_APB_DPLL_CTRL_FBDIV_MASK | CRF_APB_DPLL_CTRL_DIV2_MASK | 0 ); - - RegVal = ((0x00000000U << CRF_APB_DPLL_CTRL_PRE_SRC_SHIFT - | 0x00000040U << CRF_APB_DPLL_CTRL_FBDIV_SHIFT - | 0x00000001U << CRF_APB_DPLL_CTRL_DIV2_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_DPLL_CTRL_OFFSET ,0x00717F00U ,0x00014000U); - /*############################################################################################################################ */ - - // : BY PASS PLL - /*Register : DPLL_CTRL @ 0XFD1A002C

- - Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.) - PSU_CRF_APB_DPLL_CTRL_BYPASS 1 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFD1A002C, 0x00000008U ,0x00000008U) - RegMask = (CRF_APB_DPLL_CTRL_BYPASS_MASK | 0 ); - - RegVal = ((0x00000001U << CRF_APB_DPLL_CTRL_BYPASS_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_DPLL_CTRL_OFFSET ,0x00000008U ,0x00000008U); - /*############################################################################################################################ */ - - // : ASSERT RESET - /*Register : DPLL_CTRL @ 0XFD1A002C

- - Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS. - PSU_CRF_APB_DPLL_CTRL_RESET 1 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFD1A002C, 0x00000001U ,0x00000001U) - RegMask = (CRF_APB_DPLL_CTRL_RESET_MASK | 0 ); - - RegVal = ((0x00000001U << CRF_APB_DPLL_CTRL_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_DPLL_CTRL_OFFSET ,0x00000001U ,0x00000001U); - /*############################################################################################################################ */ - - // : DEASSERT RESET - /*Register : DPLL_CTRL @ 0XFD1A002C

- - Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS. - PSU_CRF_APB_DPLL_CTRL_RESET 0 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFD1A002C, 0x00000001U ,0x00000000U) - RegMask = (CRF_APB_DPLL_CTRL_RESET_MASK | 0 ); - - RegVal = ((0x00000000U << CRF_APB_DPLL_CTRL_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_DPLL_CTRL_OFFSET ,0x00000001U ,0x00000000U); - /*############################################################################################################################ */ - - // : CHECK PLL STATUS - /*Register : PLL_STATUS @ 0XFD1A0044

- - DPLL is locked - PSU_CRF_APB_PLL_STATUS_DPLL_LOCK 1 - (OFFSET, MASK, VALUE) (0XFD1A0044, 0x00000002U ,0x00000002U) */ - mask_poll(CRF_APB_PLL_STATUS_OFFSET,0x00000002U); - - /*############################################################################################################################ */ - - // : REMOVE PLL BY PASS - /*Register : DPLL_CTRL @ 0XFD1A002C

- - Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.) - PSU_CRF_APB_DPLL_CTRL_BYPASS 0 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFD1A002C, 0x00000008U ,0x00000000U) - RegMask = (CRF_APB_DPLL_CTRL_BYPASS_MASK | 0 ); - - RegVal = ((0x00000000U << CRF_APB_DPLL_CTRL_BYPASS_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_DPLL_CTRL_OFFSET ,0x00000008U ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : DPLL_TO_LPD_CTRL @ 0XFD1A004C

- - Divisor value for this clock. - PSU_CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0 0x3 - - Control for a clock that will be generated in the FPD, but used in the LPD as a clock source for the peripheral clock muxes. - (OFFSET, MASK, VALUE) (0XFD1A004C, 0x00003F00U ,0x00000300U) - RegMask = (CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_MASK | 0 ); - - RegVal = ((0x00000003U << CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_DPLL_TO_LPD_CTRL_OFFSET ,0x00003F00U ,0x00000300U); - /*############################################################################################################################ */ - - // : DPLL FRAC CFG - /*Register : DPLL_FRAC_CFG @ 0XFD1A0034

- - Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona - mode and uses DATA of this register for the fractional portion of the feedback divider. - PSU_CRF_APB_DPLL_FRAC_CFG_ENABLED 0x0 - - Fractional value for the Feedback value. - PSU_CRF_APB_DPLL_FRAC_CFG_DATA 0x0 - - Fractional control for the PLL - (OFFSET, MASK, VALUE) (0XFD1A0034, 0x8000FFFFU ,0x00000000U) - RegMask = (CRF_APB_DPLL_FRAC_CFG_ENABLED_MASK | CRF_APB_DPLL_FRAC_CFG_DATA_MASK | 0 ); - - RegVal = ((0x00000000U << CRF_APB_DPLL_FRAC_CFG_ENABLED_SHIFT - | 0x00000000U << CRF_APB_DPLL_FRAC_CFG_DATA_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_DPLL_FRAC_CFG_OFFSET ,0x8000FFFFU ,0x00000000U); - /*############################################################################################################################ */ - - // : VIDEO_PLL INIT - /*Register : VPLL_CFG @ 0XFD1A003C

- - PLL loop filter resistor control - PSU_CRF_APB_VPLL_CFG_RES 0x2 - - PLL charge pump control - PSU_CRF_APB_VPLL_CFG_CP 0x3 - - PLL loop filter high frequency capacitor control - PSU_CRF_APB_VPLL_CFG_LFHF 0x3 - - Lock circuit counter setting - PSU_CRF_APB_VPLL_CFG_LOCK_CNT 0x28a - - Lock circuit configuration settings for lock windowsize - PSU_CRF_APB_VPLL_CFG_LOCK_DLY 0x3f - - Helper data. Values are to be looked up in a table from Data Sheet - (OFFSET, MASK, VALUE) (0XFD1A003C, 0xFE7FEDEFU ,0x7E514C62U) - RegMask = (CRF_APB_VPLL_CFG_RES_MASK | CRF_APB_VPLL_CFG_CP_MASK | CRF_APB_VPLL_CFG_LFHF_MASK | CRF_APB_VPLL_CFG_LOCK_CNT_MASK | CRF_APB_VPLL_CFG_LOCK_DLY_MASK | 0 ); - - RegVal = ((0x00000002U << CRF_APB_VPLL_CFG_RES_SHIFT - | 0x00000003U << CRF_APB_VPLL_CFG_CP_SHIFT - | 0x00000003U << CRF_APB_VPLL_CFG_LFHF_SHIFT - | 0x0000028AU << CRF_APB_VPLL_CFG_LOCK_CNT_SHIFT - | 0x0000003FU << CRF_APB_VPLL_CFG_LOCK_DLY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_VPLL_CFG_OFFSET ,0xFE7FEDEFU ,0x7E514C62U); - /*############################################################################################################################ */ - - // : UPDATE FB_DIV - /*Register : VPLL_CTRL @ 0XFD1A0038

- - Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_ - ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source - PSU_CRF_APB_VPLL_CTRL_PRE_SRC 0x0 - - The integer portion of the feedback divider to the PLL - PSU_CRF_APB_VPLL_CTRL_FBDIV 0x39 - - This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency - PSU_CRF_APB_VPLL_CTRL_DIV2 0x1 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFD1A0038, 0x00717F00U ,0x00013900U) - RegMask = (CRF_APB_VPLL_CTRL_PRE_SRC_MASK | CRF_APB_VPLL_CTRL_FBDIV_MASK | CRF_APB_VPLL_CTRL_DIV2_MASK | 0 ); - - RegVal = ((0x00000000U << CRF_APB_VPLL_CTRL_PRE_SRC_SHIFT - | 0x00000039U << CRF_APB_VPLL_CTRL_FBDIV_SHIFT - | 0x00000001U << CRF_APB_VPLL_CTRL_DIV2_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_VPLL_CTRL_OFFSET ,0x00717F00U ,0x00013900U); - /*############################################################################################################################ */ - - // : BY PASS PLL - /*Register : VPLL_CTRL @ 0XFD1A0038

- - Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.) - PSU_CRF_APB_VPLL_CTRL_BYPASS 1 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFD1A0038, 0x00000008U ,0x00000008U) - RegMask = (CRF_APB_VPLL_CTRL_BYPASS_MASK | 0 ); - - RegVal = ((0x00000001U << CRF_APB_VPLL_CTRL_BYPASS_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_VPLL_CTRL_OFFSET ,0x00000008U ,0x00000008U); - /*############################################################################################################################ */ - - // : ASSERT RESET - /*Register : VPLL_CTRL @ 0XFD1A0038

- - Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS. - PSU_CRF_APB_VPLL_CTRL_RESET 1 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFD1A0038, 0x00000001U ,0x00000001U) - RegMask = (CRF_APB_VPLL_CTRL_RESET_MASK | 0 ); - - RegVal = ((0x00000001U << CRF_APB_VPLL_CTRL_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_VPLL_CTRL_OFFSET ,0x00000001U ,0x00000001U); - /*############################################################################################################################ */ - - // : DEASSERT RESET - /*Register : VPLL_CTRL @ 0XFD1A0038

- - Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS. - PSU_CRF_APB_VPLL_CTRL_RESET 0 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFD1A0038, 0x00000001U ,0x00000000U) - RegMask = (CRF_APB_VPLL_CTRL_RESET_MASK | 0 ); - - RegVal = ((0x00000000U << CRF_APB_VPLL_CTRL_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_VPLL_CTRL_OFFSET ,0x00000001U ,0x00000000U); - /*############################################################################################################################ */ - - // : CHECK PLL STATUS - /*Register : PLL_STATUS @ 0XFD1A0044

- - VPLL is locked - PSU_CRF_APB_PLL_STATUS_VPLL_LOCK 1 - (OFFSET, MASK, VALUE) (0XFD1A0044, 0x00000004U ,0x00000004U) */ - mask_poll(CRF_APB_PLL_STATUS_OFFSET,0x00000004U); - - /*############################################################################################################################ */ - - // : REMOVE PLL BY PASS - /*Register : VPLL_CTRL @ 0XFD1A0038

- - Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.) - PSU_CRF_APB_VPLL_CTRL_BYPASS 0 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFD1A0038, 0x00000008U ,0x00000000U) - RegMask = (CRF_APB_VPLL_CTRL_BYPASS_MASK | 0 ); - - RegVal = ((0x00000000U << CRF_APB_VPLL_CTRL_BYPASS_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_VPLL_CTRL_OFFSET ,0x00000008U ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : VPLL_TO_LPD_CTRL @ 0XFD1A0050

- - Divisor value for this clock. - PSU_CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0 0x3 - - Control for a clock that will be generated in the FPD, but used in the LPD as a clock source for the peripheral clock muxes. - (OFFSET, MASK, VALUE) (0XFD1A0050, 0x00003F00U ,0x00000300U) - RegMask = (CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_MASK | 0 ); - - RegVal = ((0x00000003U << CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_VPLL_TO_LPD_CTRL_OFFSET ,0x00003F00U ,0x00000300U); - /*############################################################################################################################ */ - - // : VIDEO FRAC CFG - /*Register : VPLL_FRAC_CFG @ 0XFD1A0040

- - Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona - mode and uses DATA of this register for the fractional portion of the feedback divider. - PSU_CRF_APB_VPLL_FRAC_CFG_ENABLED 0x1 - - Fractional value for the Feedback value. - PSU_CRF_APB_VPLL_FRAC_CFG_DATA 0x820c - - Fractional control for the PLL - (OFFSET, MASK, VALUE) (0XFD1A0040, 0x8000FFFFU ,0x8000820CU) - RegMask = (CRF_APB_VPLL_FRAC_CFG_ENABLED_MASK | CRF_APB_VPLL_FRAC_CFG_DATA_MASK | 0 ); - - RegVal = ((0x00000001U << CRF_APB_VPLL_FRAC_CFG_ENABLED_SHIFT - | 0x0000820CU << CRF_APB_VPLL_FRAC_CFG_DATA_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_VPLL_FRAC_CFG_OFFSET ,0x8000FFFFU ,0x8000820CU); - /*############################################################################################################################ */ - - - return 1; + Xil_Out32(addr, rdata); + } + +unsigned long psu_pll_init_data(void) +{ + /* + * RPLL INIT + */ + /* + * Register : RPLL_CFG @ 0XFF5E0034 + + * PLL loop filter resistor control + * PSU_CRL_APB_RPLL_CFG_RES 0xc + + * PLL charge pump control + * PSU_CRL_APB_RPLL_CFG_CP 0x3 + + * PLL loop filter high frequency capacitor control + * PSU_CRL_APB_RPLL_CFG_LFHF 0x3 + + * Lock circuit counter setting + * PSU_CRL_APB_RPLL_CFG_LOCK_CNT 0x339 + + * Lock circuit configuration settings for lock windowsize + * PSU_CRL_APB_RPLL_CFG_LOCK_DLY 0x3f + + * Helper data. Values are to be looked up in a table from Data Sheet + * (OFFSET, MASK, VALUE) (0XFF5E0034, 0xFE7FEDEFU ,0x7E672C6CU) + */ + PSU_Mask_Write(CRL_APB_RPLL_CFG_OFFSET, 0xFE7FEDEFU, 0x7E672C6CU); +/*##################################################################### */ + + /* + * UPDATE FB_DIV + */ + /* + * Register : RPLL_CTRL @ 0XFF5E0030 + + * Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i + * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour + * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source + * PSU_CRL_APB_RPLL_CTRL_PRE_SRC 0x0 + + * The integer portion of the feedback divider to the PLL + * PSU_CRL_APB_RPLL_CTRL_FBDIV 0x2d + + * This turns on the divide by 2 that is inside of the PLL. This does not c + * hange the VCO frequency, just the output frequency + * PSU_CRL_APB_RPLL_CTRL_DIV2 0x1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFF5E0030, 0x00717F00U ,0x00012D00U) + */ + PSU_Mask_Write(CRL_APB_RPLL_CTRL_OFFSET, 0x00717F00U, 0x00012D00U); +/*##################################################################### */ + + /* + * BY PASS PLL + */ + /* + * Register : RPLL_CTRL @ 0XFF5E0030 + + * Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) + * PSU_CRL_APB_RPLL_CTRL_BYPASS 1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFF5E0030, 0x00000008U ,0x00000008U) + */ + PSU_Mask_Write(CRL_APB_RPLL_CTRL_OFFSET, 0x00000008U, 0x00000008U); +/*##################################################################### */ + + /* + * ASSERT RESET + */ + /* + * Register : RPLL_CTRL @ 0XFF5E0030 + + * Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. + * PSU_CRL_APB_RPLL_CTRL_RESET 1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFF5E0030, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(CRL_APB_RPLL_CTRL_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * DEASSERT RESET + */ + /* + * Register : RPLL_CTRL @ 0XFF5E0030 + + * Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. + * PSU_CRL_APB_RPLL_CTRL_RESET 0 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFF5E0030, 0x00000001U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RPLL_CTRL_OFFSET, 0x00000001U, 0x00000000U); +/*##################################################################### */ + + /* + * CHECK PLL STATUS + */ + /* + * Register : PLL_STATUS @ 0XFF5E0040 + + * RPLL is locked + * PSU_CRL_APB_PLL_STATUS_RPLL_LOCK 1 + * (OFFSET, MASK, VALUE) (0XFF5E0040, 0x00000002U ,0x00000002U) + */ + mask_poll(CRL_APB_PLL_STATUS_OFFSET, 0x00000002U); + +/*##################################################################### */ + + /* + * REMOVE PLL BY PASS + */ + /* + * Register : RPLL_CTRL @ 0XFF5E0030 + + * Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) + * PSU_CRL_APB_RPLL_CTRL_BYPASS 0 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFF5E0030, 0x00000008U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RPLL_CTRL_OFFSET, 0x00000008U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : RPLL_TO_FPD_CTRL @ 0XFF5E0048 + + * Divisor value for this clock. + * PSU_CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0 0x2 + + * Control for a clock that will be generated in the LPD, but used in the F + * PD as a clock source for the peripheral clock muxes. + * (OFFSET, MASK, VALUE) (0XFF5E0048, 0x00003F00U ,0x00000200U) + */ + PSU_Mask_Write(CRL_APB_RPLL_TO_FPD_CTRL_OFFSET, + 0x00003F00U, 0x00000200U); +/*##################################################################### */ + + /* + * RPLL FRAC CFG + */ + /* + * IOPLL INIT + */ + /* + * Register : IOPLL_CFG @ 0XFF5E0024 + + * PLL loop filter resistor control + * PSU_CRL_APB_IOPLL_CFG_RES 0x2 + + * PLL charge pump control + * PSU_CRL_APB_IOPLL_CFG_CP 0x4 + + * PLL loop filter high frequency capacitor control + * PSU_CRL_APB_IOPLL_CFG_LFHF 0x3 + + * Lock circuit counter setting + * PSU_CRL_APB_IOPLL_CFG_LOCK_CNT 0x258 + + * Lock circuit configuration settings for lock windowsize + * PSU_CRL_APB_IOPLL_CFG_LOCK_DLY 0x3f + + * Helper data. Values are to be looked up in a table from Data Sheet + * (OFFSET, MASK, VALUE) (0XFF5E0024, 0xFE7FEDEFU ,0x7E4B0C82U) + */ + PSU_Mask_Write(CRL_APB_IOPLL_CFG_OFFSET, 0xFE7FEDEFU, 0x7E4B0C82U); +/*##################################################################### */ + + /* + * UPDATE FB_DIV + */ + /* + * Register : IOPLL_CTRL @ 0XFF5E0020 + + * Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i + * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour + * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source + * PSU_CRL_APB_IOPLL_CTRL_PRE_SRC 0x0 + + * The integer portion of the feedback divider to the PLL + * PSU_CRL_APB_IOPLL_CTRL_FBDIV 0x5a + + * This turns on the divide by 2 that is inside of the PLL. This does not c + * hange the VCO frequency, just the output frequency + * PSU_CRL_APB_IOPLL_CTRL_DIV2 0x1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFF5E0020, 0x00717F00U ,0x00015A00U) + */ + PSU_Mask_Write(CRL_APB_IOPLL_CTRL_OFFSET, 0x00717F00U, 0x00015A00U); +/*##################################################################### */ + + /* + * BY PASS PLL + */ + /* + * Register : IOPLL_CTRL @ 0XFF5E0020 + + * Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) + * PSU_CRL_APB_IOPLL_CTRL_BYPASS 1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFF5E0020, 0x00000008U ,0x00000008U) + */ + PSU_Mask_Write(CRL_APB_IOPLL_CTRL_OFFSET, 0x00000008U, 0x00000008U); +/*##################################################################### */ + + /* + * ASSERT RESET + */ + /* + * Register : IOPLL_CTRL @ 0XFF5E0020 + + * Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. + * PSU_CRL_APB_IOPLL_CTRL_RESET 1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFF5E0020, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(CRL_APB_IOPLL_CTRL_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * DEASSERT RESET + */ + /* + * Register : IOPLL_CTRL @ 0XFF5E0020 + + * Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. + * PSU_CRL_APB_IOPLL_CTRL_RESET 0 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFF5E0020, 0x00000001U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_IOPLL_CTRL_OFFSET, 0x00000001U, 0x00000000U); +/*##################################################################### */ + + /* + * CHECK PLL STATUS + */ + /* + * Register : PLL_STATUS @ 0XFF5E0040 + + * IOPLL is locked + * PSU_CRL_APB_PLL_STATUS_IOPLL_LOCK 1 + * (OFFSET, MASK, VALUE) (0XFF5E0040, 0x00000001U ,0x00000001U) + */ + mask_poll(CRL_APB_PLL_STATUS_OFFSET, 0x00000001U); + +/*##################################################################### */ + + /* + * REMOVE PLL BY PASS + */ + /* + * Register : IOPLL_CTRL @ 0XFF5E0020 + + * Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) + * PSU_CRL_APB_IOPLL_CTRL_BYPASS 0 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFF5E0020, 0x00000008U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_IOPLL_CTRL_OFFSET, 0x00000008U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : IOPLL_TO_FPD_CTRL @ 0XFF5E0044 + + * Divisor value for this clock. + * PSU_CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0 0x3 + + * Control for a clock that will be generated in the LPD, but used in the F + * PD as a clock source for the peripheral clock muxes. + * (OFFSET, MASK, VALUE) (0XFF5E0044, 0x00003F00U ,0x00000300U) + */ + PSU_Mask_Write(CRL_APB_IOPLL_TO_FPD_CTRL_OFFSET, + 0x00003F00U, 0x00000300U); +/*##################################################################### */ + + /* + * IOPLL FRAC CFG + */ + /* + * APU_PLL INIT + */ + /* + * Register : APLL_CFG @ 0XFD1A0024 + + * PLL loop filter resistor control + * PSU_CRF_APB_APLL_CFG_RES 0x2 + + * PLL charge pump control + * PSU_CRF_APB_APLL_CFG_CP 0x3 + + * PLL loop filter high frequency capacitor control + * PSU_CRF_APB_APLL_CFG_LFHF 0x3 + + * Lock circuit counter setting + * PSU_CRF_APB_APLL_CFG_LOCK_CNT 0x258 + + * Lock circuit configuration settings for lock windowsize + * PSU_CRF_APB_APLL_CFG_LOCK_DLY 0x3f + + * Helper data. Values are to be looked up in a table from Data Sheet + * (OFFSET, MASK, VALUE) (0XFD1A0024, 0xFE7FEDEFU ,0x7E4B0C62U) + */ + PSU_Mask_Write(CRF_APB_APLL_CFG_OFFSET, 0xFE7FEDEFU, 0x7E4B0C62U); +/*##################################################################### */ + + /* + * UPDATE FB_DIV + */ + /* + * Register : APLL_CTRL @ 0XFD1A0020 + + * Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i + * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour + * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source + * PSU_CRF_APB_APLL_CTRL_PRE_SRC 0x0 + + * The integer portion of the feedback divider to the PLL + * PSU_CRF_APB_APLL_CTRL_FBDIV 0x48 + + * This turns on the divide by 2 that is inside of the PLL. This does not c + * hange the VCO frequency, just the output frequency + * PSU_CRF_APB_APLL_CTRL_DIV2 0x1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A0020, 0x00717F00U ,0x00014800U) + */ + PSU_Mask_Write(CRF_APB_APLL_CTRL_OFFSET, 0x00717F00U, 0x00014800U); +/*##################################################################### */ + + /* + * BY PASS PLL + */ + /* + * Register : APLL_CTRL @ 0XFD1A0020 + + * Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) + * PSU_CRF_APB_APLL_CTRL_BYPASS 1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A0020, 0x00000008U ,0x00000008U) + */ + PSU_Mask_Write(CRF_APB_APLL_CTRL_OFFSET, 0x00000008U, 0x00000008U); +/*##################################################################### */ + + /* + * ASSERT RESET + */ + /* + * Register : APLL_CTRL @ 0XFD1A0020 + + * Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. + * PSU_CRF_APB_APLL_CTRL_RESET 1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A0020, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(CRF_APB_APLL_CTRL_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * DEASSERT RESET + */ + /* + * Register : APLL_CTRL @ 0XFD1A0020 + + * Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. + * PSU_CRF_APB_APLL_CTRL_RESET 0 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A0020, 0x00000001U ,0x00000000U) + */ + PSU_Mask_Write(CRF_APB_APLL_CTRL_OFFSET, 0x00000001U, 0x00000000U); +/*##################################################################### */ + + /* + * CHECK PLL STATUS + */ + /* + * Register : PLL_STATUS @ 0XFD1A0044 + + * APLL is locked + * PSU_CRF_APB_PLL_STATUS_APLL_LOCK 1 + * (OFFSET, MASK, VALUE) (0XFD1A0044, 0x00000001U ,0x00000001U) + */ + mask_poll(CRF_APB_PLL_STATUS_OFFSET, 0x00000001U); + +/*##################################################################### */ + + /* + * REMOVE PLL BY PASS + */ + /* + * Register : APLL_CTRL @ 0XFD1A0020 + + * Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) + * PSU_CRF_APB_APLL_CTRL_BYPASS 0 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A0020, 0x00000008U ,0x00000000U) + */ + PSU_Mask_Write(CRF_APB_APLL_CTRL_OFFSET, 0x00000008U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : APLL_TO_LPD_CTRL @ 0XFD1A0048 + + * Divisor value for this clock. + * PSU_CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0 0x3 + + * Control for a clock that will be generated in the FPD, but used in the L + * PD as a clock source for the peripheral clock muxes. + * (OFFSET, MASK, VALUE) (0XFD1A0048, 0x00003F00U ,0x00000300U) + */ + PSU_Mask_Write(CRF_APB_APLL_TO_LPD_CTRL_OFFSET, + 0x00003F00U, 0x00000300U); +/*##################################################################### */ + + /* + * APLL FRAC CFG + */ + /* + * DDR_PLL INIT + */ + /* + * Register : DPLL_CFG @ 0XFD1A0030 + + * PLL loop filter resistor control + * PSU_CRF_APB_DPLL_CFG_RES 0x2 + + * PLL charge pump control + * PSU_CRF_APB_DPLL_CFG_CP 0x3 + + * PLL loop filter high frequency capacitor control + * PSU_CRF_APB_DPLL_CFG_LFHF 0x3 + + * Lock circuit counter setting + * PSU_CRF_APB_DPLL_CFG_LOCK_CNT 0x258 + + * Lock circuit configuration settings for lock windowsize + * PSU_CRF_APB_DPLL_CFG_LOCK_DLY 0x3f + + * Helper data. Values are to be looked up in a table from Data Sheet + * (OFFSET, MASK, VALUE) (0XFD1A0030, 0xFE7FEDEFU ,0x7E4B0C62U) + */ + PSU_Mask_Write(CRF_APB_DPLL_CFG_OFFSET, 0xFE7FEDEFU, 0x7E4B0C62U); +/*##################################################################### */ + + /* + * UPDATE FB_DIV + */ + /* + * Register : DPLL_CTRL @ 0XFD1A002C + + * Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i + * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour + * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source + * PSU_CRF_APB_DPLL_CTRL_PRE_SRC 0x0 + + * The integer portion of the feedback divider to the PLL + * PSU_CRF_APB_DPLL_CTRL_FBDIV 0x40 + + * This turns on the divide by 2 that is inside of the PLL. This does not c + * hange the VCO frequency, just the output frequency + * PSU_CRF_APB_DPLL_CTRL_DIV2 0x1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A002C, 0x00717F00U ,0x00014000U) + */ + PSU_Mask_Write(CRF_APB_DPLL_CTRL_OFFSET, 0x00717F00U, 0x00014000U); +/*##################################################################### */ + + /* + * BY PASS PLL + */ + /* + * Register : DPLL_CTRL @ 0XFD1A002C + + * Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) + * PSU_CRF_APB_DPLL_CTRL_BYPASS 1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A002C, 0x00000008U ,0x00000008U) + */ + PSU_Mask_Write(CRF_APB_DPLL_CTRL_OFFSET, 0x00000008U, 0x00000008U); +/*##################################################################### */ + + /* + * ASSERT RESET + */ + /* + * Register : DPLL_CTRL @ 0XFD1A002C + + * Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. + * PSU_CRF_APB_DPLL_CTRL_RESET 1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A002C, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(CRF_APB_DPLL_CTRL_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * DEASSERT RESET + */ + /* + * Register : DPLL_CTRL @ 0XFD1A002C + + * Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. + * PSU_CRF_APB_DPLL_CTRL_RESET 0 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A002C, 0x00000001U ,0x00000000U) + */ + PSU_Mask_Write(CRF_APB_DPLL_CTRL_OFFSET, 0x00000001U, 0x00000000U); +/*##################################################################### */ + + /* + * CHECK PLL STATUS + */ + /* + * Register : PLL_STATUS @ 0XFD1A0044 + + * DPLL is locked + * PSU_CRF_APB_PLL_STATUS_DPLL_LOCK 1 + * (OFFSET, MASK, VALUE) (0XFD1A0044, 0x00000002U ,0x00000002U) + */ + mask_poll(CRF_APB_PLL_STATUS_OFFSET, 0x00000002U); + +/*##################################################################### */ + + /* + * REMOVE PLL BY PASS + */ + /* + * Register : DPLL_CTRL @ 0XFD1A002C + + * Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) + * PSU_CRF_APB_DPLL_CTRL_BYPASS 0 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A002C, 0x00000008U ,0x00000000U) + */ + PSU_Mask_Write(CRF_APB_DPLL_CTRL_OFFSET, 0x00000008U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : DPLL_TO_LPD_CTRL @ 0XFD1A004C + + * Divisor value for this clock. + * PSU_CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0 0x2 + + * Control for a clock that will be generated in the FPD, but used in the L + * PD as a clock source for the peripheral clock muxes. + * (OFFSET, MASK, VALUE) (0XFD1A004C, 0x00003F00U ,0x00000200U) + */ + PSU_Mask_Write(CRF_APB_DPLL_TO_LPD_CTRL_OFFSET, + 0x00003F00U, 0x00000200U); +/*##################################################################### */ + + /* + * DPLL FRAC CFG + */ + /* + * VIDEO_PLL INIT + */ + /* + * Register : VPLL_CFG @ 0XFD1A003C + + * PLL loop filter resistor control + * PSU_CRF_APB_VPLL_CFG_RES 0x2 + + * PLL charge pump control + * PSU_CRF_APB_VPLL_CFG_CP 0x4 + + * PLL loop filter high frequency capacitor control + * PSU_CRF_APB_VPLL_CFG_LFHF 0x3 + + * Lock circuit counter setting + * PSU_CRF_APB_VPLL_CFG_LOCK_CNT 0x258 + + * Lock circuit configuration settings for lock windowsize + * PSU_CRF_APB_VPLL_CFG_LOCK_DLY 0x3f + + * Helper data. Values are to be looked up in a table from Data Sheet + * (OFFSET, MASK, VALUE) (0XFD1A003C, 0xFE7FEDEFU ,0x7E4B0C82U) + */ + PSU_Mask_Write(CRF_APB_VPLL_CFG_OFFSET, 0xFE7FEDEFU, 0x7E4B0C82U); +/*##################################################################### */ + + /* + * UPDATE FB_DIV + */ + /* + * Register : VPLL_CTRL @ 0XFD1A0038 + + * Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i + * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour + * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source + * PSU_CRF_APB_VPLL_CTRL_PRE_SRC 0x0 + + * The integer portion of the feedback divider to the PLL + * PSU_CRF_APB_VPLL_CTRL_FBDIV 0x5a + + * This turns on the divide by 2 that is inside of the PLL. This does not c + * hange the VCO frequency, just the output frequency + * PSU_CRF_APB_VPLL_CTRL_DIV2 0x1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A0038, 0x00717F00U ,0x00015A00U) + */ + PSU_Mask_Write(CRF_APB_VPLL_CTRL_OFFSET, 0x00717F00U, 0x00015A00U); +/*##################################################################### */ + + /* + * BY PASS PLL + */ + /* + * Register : VPLL_CTRL @ 0XFD1A0038 + + * Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) + * PSU_CRF_APB_VPLL_CTRL_BYPASS 1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A0038, 0x00000008U ,0x00000008U) + */ + PSU_Mask_Write(CRF_APB_VPLL_CTRL_OFFSET, 0x00000008U, 0x00000008U); +/*##################################################################### */ + + /* + * ASSERT RESET + */ + /* + * Register : VPLL_CTRL @ 0XFD1A0038 + + * Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. + * PSU_CRF_APB_VPLL_CTRL_RESET 1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A0038, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(CRF_APB_VPLL_CTRL_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * DEASSERT RESET + */ + /* + * Register : VPLL_CTRL @ 0XFD1A0038 + + * Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. + * PSU_CRF_APB_VPLL_CTRL_RESET 0 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A0038, 0x00000001U ,0x00000000U) + */ + PSU_Mask_Write(CRF_APB_VPLL_CTRL_OFFSET, 0x00000001U, 0x00000000U); +/*##################################################################### */ + + /* + * CHECK PLL STATUS + */ + /* + * Register : PLL_STATUS @ 0XFD1A0044 + + * VPLL is locked + * PSU_CRF_APB_PLL_STATUS_VPLL_LOCK 1 + * (OFFSET, MASK, VALUE) (0XFD1A0044, 0x00000004U ,0x00000004U) + */ + mask_poll(CRF_APB_PLL_STATUS_OFFSET, 0x00000004U); + +/*##################################################################### */ + + /* + * REMOVE PLL BY PASS + */ + /* + * Register : VPLL_CTRL @ 0XFD1A0038 + + * Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) + * PSU_CRF_APB_VPLL_CTRL_BYPASS 0 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A0038, 0x00000008U ,0x00000000U) + */ + PSU_Mask_Write(CRF_APB_VPLL_CTRL_OFFSET, 0x00000008U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : VPLL_TO_LPD_CTRL @ 0XFD1A0050 + + * Divisor value for this clock. + * PSU_CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0 0x3 + + * Control for a clock that will be generated in the FPD, but used in the L + * PD as a clock source for the peripheral clock muxes. + * (OFFSET, MASK, VALUE) (0XFD1A0050, 0x00003F00U ,0x00000300U) + */ + PSU_Mask_Write(CRF_APB_VPLL_TO_LPD_CTRL_OFFSET, + 0x00003F00U, 0x00000300U); +/*##################################################################### */ + + /* + * VIDEO FRAC CFG + */ + + return 1; } -unsigned long psu_clock_init_data() { - // : CLOCK CONTROL SLCR REGISTER - /*Register : GEM3_REF_CTRL @ 0XFF5E005C

+unsigned long psu_clock_init_data(void) +{ + /* + * CLOCK CONTROL SLCR REGISTER + */ + /* + * Register : GEM3_REF_CTRL @ 0XFF5E005C + + * Clock active for the RX channel + * PSU_CRL_APB_GEM3_REF_CTRL_RX_CLKACT 0x1 - Clock active for the RX channel - PSU_CRL_APB_GEM3_REF_CTRL_RX_CLKACT 0x1 + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_GEM3_REF_CTRL_CLKACT 0x1 - Clock active signal. Switch to 0 to disable the clock - PSU_CRL_APB_GEM3_REF_CTRL_CLKACT 0x1 + * 6 bit divider + * PSU_CRL_APB_GEM3_REF_CTRL_DIVISOR1 0x1 - 6 bit divider - PSU_CRL_APB_GEM3_REF_CTRL_DIVISOR1 0x1 + * 6 bit divider + * PSU_CRL_APB_GEM3_REF_CTRL_DIVISOR0 0xc + + * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_GEM3_REF_CTRL_SRCSEL 0x0 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E005C, 0x063F3F07U ,0x06010C00U) + */ + PSU_Mask_Write(CRL_APB_GEM3_REF_CTRL_OFFSET, + 0x063F3F07U, 0x06010C00U); +/*##################################################################### */ + + /* + * Register : GEM_TSU_REF_CTRL @ 0XFF5E0100 - 6 bit divider - PSU_CRL_APB_GEM3_REF_CTRL_DIVISOR0 0xc + * 6 bit divider + * PSU_CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0 0x6 - 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_GEM3_REF_CTRL_SRCSEL 0x0 + * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_GEM_TSU_REF_CTRL_SRCSEL 0x0 - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E005C, 0x063F3F07U ,0x06010C00U) - RegMask = (CRL_APB_GEM3_REF_CTRL_RX_CLKACT_MASK | CRL_APB_GEM3_REF_CTRL_CLKACT_MASK | CRL_APB_GEM3_REF_CTRL_DIVISOR1_MASK | CRL_APB_GEM3_REF_CTRL_DIVISOR0_MASK | CRL_APB_GEM3_REF_CTRL_SRCSEL_MASK | 0 ); + * 6 bit divider + * PSU_CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1 0x1 - RegVal = ((0x00000001U << CRL_APB_GEM3_REF_CTRL_RX_CLKACT_SHIFT - | 0x00000001U << CRL_APB_GEM3_REF_CTRL_CLKACT_SHIFT - | 0x00000001U << CRL_APB_GEM3_REF_CTRL_DIVISOR1_SHIFT - | 0x0000000CU << CRL_APB_GEM3_REF_CTRL_DIVISOR0_SHIFT - | 0x00000000U << CRL_APB_GEM3_REF_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_GEM3_REF_CTRL_OFFSET ,0x063F3F07U ,0x06010C00U); - /*############################################################################################################################ */ + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_GEM_TSU_REF_CTRL_CLKACT 0x1 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E0100, 0x013F3F07U ,0x01010600U) + */ + PSU_Mask_Write(CRL_APB_GEM_TSU_REF_CTRL_OFFSET, + 0x013F3F07U, 0x01010600U); +/*##################################################################### */ + + /* + * Register : USB0_BUS_REF_CTRL @ 0XFF5E0060 - /*Register : USB0_BUS_REF_CTRL @ 0XFF5E0060

+ * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_USB0_BUS_REF_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1 0x1 + + * 6 bit divider + * PSU_CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0 0x6 + + * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_USB0_BUS_REF_CTRL_SRCSEL 0x0 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E0060, 0x023F3F07U ,0x02010600U) + */ + PSU_Mask_Write(CRL_APB_USB0_BUS_REF_CTRL_OFFSET, + 0x023F3F07U, 0x02010600U); +/*##################################################################### */ + + /* + * Register : USB3_DUAL_REF_CTRL @ 0XFF5E004C - Clock active signal. Switch to 0 to disable the clock - PSU_CRL_APB_USB0_BUS_REF_CTRL_CLKACT 0x1 + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_USB3_DUAL_REF_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1 0x3 + + * 6 bit divider + * PSU_CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0 0x19 + + * 000 = IOPLL; 010 = RPLL; 011 = DPLL. (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL 0x0 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E004C, 0x023F3F07U ,0x02031900U) + */ + PSU_Mask_Write(CRL_APB_USB3_DUAL_REF_CTRL_OFFSET, + 0x023F3F07U, 0x02031900U); +/*##################################################################### */ - 6 bit divider - PSU_CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1 0x1 + /* + * Register : QSPI_REF_CTRL @ 0XFF5E0068 - 6 bit divider - PSU_CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0 0x6 + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_QSPI_REF_CTRL_CLKACT 0x1 - 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_USB0_BUS_REF_CTRL_SRCSEL 0x0 + * 6 bit divider + * PSU_CRL_APB_QSPI_REF_CTRL_DIVISOR1 0x1 + + * 6 bit divider + * PSU_CRL_APB_QSPI_REF_CTRL_DIVISOR0 0xc + + * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_QSPI_REF_CTRL_SRCSEL 0x0 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E0068, 0x013F3F07U ,0x01010C00U) + */ + PSU_Mask_Write(CRL_APB_QSPI_REF_CTRL_OFFSET, + 0x013F3F07U, 0x01010C00U); +/*##################################################################### */ - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E0060, 0x023F3F07U ,0x02010600U) - RegMask = (CRL_APB_USB0_BUS_REF_CTRL_CLKACT_MASK | CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_MASK | CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_MASK | CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_MASK | 0 ); + /* + * Register : SDIO1_REF_CTRL @ 0XFF5E0070 - RegVal = ((0x00000001U << CRL_APB_USB0_BUS_REF_CTRL_CLKACT_SHIFT - | 0x00000001U << CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_SHIFT - | 0x00000006U << CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_SHIFT - | 0x00000000U << CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_USB0_BUS_REF_CTRL_OFFSET ,0x023F3F07U ,0x02010600U); - /*############################################################################################################################ */ + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_SDIO1_REF_CTRL_CLKACT 0x1 - /*Register : USB3_DUAL_REF_CTRL @ 0XFF5E004C

+ * 6 bit divider + * PSU_CRL_APB_SDIO1_REF_CTRL_DIVISOR1 0x1 + + * 6 bit divider + * PSU_CRL_APB_SDIO1_REF_CTRL_DIVISOR0 0x8 + + * 000 = IOPLL; 010 = RPLL; 011 = VPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_SDIO1_REF_CTRL_SRCSEL 0x0 - Clock active signal. Switch to 0 to disable the clock - PSU_CRL_APB_USB3_DUAL_REF_CTRL_CLKACT 0x1 + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E0070, 0x013F3F07U ,0x01010800U) + */ + PSU_Mask_Write(CRL_APB_SDIO1_REF_CTRL_OFFSET, + 0x013F3F07U, 0x01010800U); +/*##################################################################### */ - 6 bit divider - PSU_CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1 0xf + /* + * Register : SDIO_CLK_CTRL @ 0XFF18030C - 6 bit divider - PSU_CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0 0x5 + * MIO pad selection for sdio1_rx_clk (feedback clock from the PAD) 0: MIO + * [51] 1: MIO [76] + * PSU_IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL 0 - 000 = IOPLL; 010 = RPLL; 011 = DPLL. (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL 0x0 + * SoC Debug Clock Control + * (OFFSET, MASK, VALUE) (0XFF18030C, 0x00020000U ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_SDIO_CLK_CTRL_OFFSET, + 0x00020000U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : UART0_REF_CTRL @ 0XFF5E0074 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_UART0_REF_CTRL_CLKACT 0x1 - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E004C, 0x023F3F07U ,0x020F0500U) - RegMask = (CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_MASK | CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_MASK | CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_MASK | CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_MASK | 0 ); + * 6 bit divider + * PSU_CRL_APB_UART0_REF_CTRL_DIVISOR1 0x1 - RegVal = ((0x00000001U << CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_SHIFT - | 0x0000000FU << CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_SHIFT - | 0x00000005U << CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_SHIFT - | 0x00000000U << CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_USB3_DUAL_REF_CTRL_OFFSET ,0x023F3F07U ,0x020F0500U); - /*############################################################################################################################ */ + * 6 bit divider + * PSU_CRL_APB_UART0_REF_CTRL_DIVISOR0 0xf - /*Register : QSPI_REF_CTRL @ 0XFF5E0068

+ * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_UART0_REF_CTRL_SRCSEL 0x0 - Clock active signal. Switch to 0 to disable the clock - PSU_CRL_APB_QSPI_REF_CTRL_CLKACT 0x1 + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E0074, 0x013F3F07U ,0x01010F00U) + */ + PSU_Mask_Write(CRL_APB_UART0_REF_CTRL_OFFSET, + 0x013F3F07U, 0x01010F00U); +/*##################################################################### */ + + /* + * Register : UART1_REF_CTRL @ 0XFF5E0078 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_UART1_REF_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_UART1_REF_CTRL_DIVISOR1 0x1 + + * 6 bit divider + * PSU_CRL_APB_UART1_REF_CTRL_DIVISOR0 0xf - 6 bit divider - PSU_CRL_APB_QSPI_REF_CTRL_DIVISOR1 0x1 + * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_UART1_REF_CTRL_SRCSEL 0x0 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E0078, 0x013F3F07U ,0x01010F00U) + */ + PSU_Mask_Write(CRL_APB_UART1_REF_CTRL_OFFSET, + 0x013F3F07U, 0x01010F00U); +/*##################################################################### */ + + /* + * Register : I2C0_REF_CTRL @ 0XFF5E0120 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_I2C0_REF_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_I2C0_REF_CTRL_DIVISOR1 0x1 + + * 6 bit divider + * PSU_CRL_APB_I2C0_REF_CTRL_DIVISOR0 0xf + + * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_I2C0_REF_CTRL_SRCSEL 0x0 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E0120, 0x013F3F07U ,0x01010F00U) + */ + PSU_Mask_Write(CRL_APB_I2C0_REF_CTRL_OFFSET, + 0x013F3F07U, 0x01010F00U); +/*##################################################################### */ + + /* + * Register : I2C1_REF_CTRL @ 0XFF5E0124 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_I2C1_REF_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_I2C1_REF_CTRL_DIVISOR1 0x1 + + * 6 bit divider + * PSU_CRL_APB_I2C1_REF_CTRL_DIVISOR0 0xf + + * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_I2C1_REF_CTRL_SRCSEL 0x0 - 6 bit divider - PSU_CRL_APB_QSPI_REF_CTRL_DIVISOR0 0xc + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E0124, 0x013F3F07U ,0x01010F00U) + */ + PSU_Mask_Write(CRL_APB_I2C1_REF_CTRL_OFFSET, + 0x013F3F07U, 0x01010F00U); +/*##################################################################### */ + + /* + * Register : CAN1_REF_CTRL @ 0XFF5E0088 - 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_QSPI_REF_CTRL_SRCSEL 0x0 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E0068, 0x013F3F07U ,0x01010C00U) - RegMask = (CRL_APB_QSPI_REF_CTRL_CLKACT_MASK | CRL_APB_QSPI_REF_CTRL_DIVISOR1_MASK | CRL_APB_QSPI_REF_CTRL_DIVISOR0_MASK | CRL_APB_QSPI_REF_CTRL_SRCSEL_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_QSPI_REF_CTRL_CLKACT_SHIFT - | 0x00000001U << CRL_APB_QSPI_REF_CTRL_DIVISOR1_SHIFT - | 0x0000000CU << CRL_APB_QSPI_REF_CTRL_DIVISOR0_SHIFT - | 0x00000000U << CRL_APB_QSPI_REF_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_QSPI_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010C00U); - /*############################################################################################################################ */ - - /*Register : SDIO1_REF_CTRL @ 0XFF5E0070

- - Clock active signal. Switch to 0 to disable the clock - PSU_CRL_APB_SDIO1_REF_CTRL_CLKACT 0x1 - - 6 bit divider - PSU_CRL_APB_SDIO1_REF_CTRL_DIVISOR1 0x1 - - 6 bit divider - PSU_CRL_APB_SDIO1_REF_CTRL_DIVISOR0 0x6 - - 000 = IOPLL; 010 = RPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_SDIO1_REF_CTRL_SRCSEL 0x2 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E0070, 0x013F3F07U ,0x01010602U) - RegMask = (CRL_APB_SDIO1_REF_CTRL_CLKACT_MASK | CRL_APB_SDIO1_REF_CTRL_DIVISOR1_MASK | CRL_APB_SDIO1_REF_CTRL_DIVISOR0_MASK | CRL_APB_SDIO1_REF_CTRL_SRCSEL_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_SDIO1_REF_CTRL_CLKACT_SHIFT - | 0x00000001U << CRL_APB_SDIO1_REF_CTRL_DIVISOR1_SHIFT - | 0x00000006U << CRL_APB_SDIO1_REF_CTRL_DIVISOR0_SHIFT - | 0x00000002U << CRL_APB_SDIO1_REF_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_SDIO1_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010602U); - /*############################################################################################################################ */ - - /*Register : SDIO_CLK_CTRL @ 0XFF18030C

- - MIO pad selection for sdio1_rx_clk (feedback clock from the PAD) 0: MIO [51] 1: MIO [76] - PSU_IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL 0 - - SoC Debug Clock Control - (OFFSET, MASK, VALUE) (0XFF18030C, 0x00020000U ,0x00000000U) - RegMask = (IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_SDIO_CLK_CTRL_OFFSET ,0x00020000U ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : UART0_REF_CTRL @ 0XFF5E0074

- - Clock active signal. Switch to 0 to disable the clock - PSU_CRL_APB_UART0_REF_CTRL_CLKACT 0x1 - - 6 bit divider - PSU_CRL_APB_UART0_REF_CTRL_DIVISOR1 0x1 - - 6 bit divider - PSU_CRL_APB_UART0_REF_CTRL_DIVISOR0 0xf - - 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_UART0_REF_CTRL_SRCSEL 0x0 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E0074, 0x013F3F07U ,0x01010F00U) - RegMask = (CRL_APB_UART0_REF_CTRL_CLKACT_MASK | CRL_APB_UART0_REF_CTRL_DIVISOR1_MASK | CRL_APB_UART0_REF_CTRL_DIVISOR0_MASK | CRL_APB_UART0_REF_CTRL_SRCSEL_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_UART0_REF_CTRL_CLKACT_SHIFT - | 0x00000001U << CRL_APB_UART0_REF_CTRL_DIVISOR1_SHIFT - | 0x0000000FU << CRL_APB_UART0_REF_CTRL_DIVISOR0_SHIFT - | 0x00000000U << CRL_APB_UART0_REF_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_UART0_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010F00U); - /*############################################################################################################################ */ - - /*Register : UART1_REF_CTRL @ 0XFF5E0078

- - Clock active signal. Switch to 0 to disable the clock - PSU_CRL_APB_UART1_REF_CTRL_CLKACT 0x1 - - 6 bit divider - PSU_CRL_APB_UART1_REF_CTRL_DIVISOR1 0x1 - - 6 bit divider - PSU_CRL_APB_UART1_REF_CTRL_DIVISOR0 0xf - - 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_UART1_REF_CTRL_SRCSEL 0x0 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E0078, 0x013F3F07U ,0x01010F00U) - RegMask = (CRL_APB_UART1_REF_CTRL_CLKACT_MASK | CRL_APB_UART1_REF_CTRL_DIVISOR1_MASK | CRL_APB_UART1_REF_CTRL_DIVISOR0_MASK | CRL_APB_UART1_REF_CTRL_SRCSEL_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_UART1_REF_CTRL_CLKACT_SHIFT - | 0x00000001U << CRL_APB_UART1_REF_CTRL_DIVISOR1_SHIFT - | 0x0000000FU << CRL_APB_UART1_REF_CTRL_DIVISOR0_SHIFT - | 0x00000000U << CRL_APB_UART1_REF_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_UART1_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010F00U); - /*############################################################################################################################ */ - - /*Register : I2C0_REF_CTRL @ 0XFF5E0120

- - Clock active signal. Switch to 0 to disable the clock - PSU_CRL_APB_I2C0_REF_CTRL_CLKACT 0x1 - - 6 bit divider - PSU_CRL_APB_I2C0_REF_CTRL_DIVISOR1 0x1 - - 6 bit divider - PSU_CRL_APB_I2C0_REF_CTRL_DIVISOR0 0xf - - 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_I2C0_REF_CTRL_SRCSEL 0x0 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E0120, 0x013F3F07U ,0x01010F00U) - RegMask = (CRL_APB_I2C0_REF_CTRL_CLKACT_MASK | CRL_APB_I2C0_REF_CTRL_DIVISOR1_MASK | CRL_APB_I2C0_REF_CTRL_DIVISOR0_MASK | CRL_APB_I2C0_REF_CTRL_SRCSEL_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_I2C0_REF_CTRL_CLKACT_SHIFT - | 0x00000001U << CRL_APB_I2C0_REF_CTRL_DIVISOR1_SHIFT - | 0x0000000FU << CRL_APB_I2C0_REF_CTRL_DIVISOR0_SHIFT - | 0x00000000U << CRL_APB_I2C0_REF_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_I2C0_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010F00U); - /*############################################################################################################################ */ - - /*Register : I2C1_REF_CTRL @ 0XFF5E0124

- - Clock active signal. Switch to 0 to disable the clock - PSU_CRL_APB_I2C1_REF_CTRL_CLKACT 0x1 - - 6 bit divider - PSU_CRL_APB_I2C1_REF_CTRL_DIVISOR1 0x1 - - 6 bit divider - PSU_CRL_APB_I2C1_REF_CTRL_DIVISOR0 0xf - - 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_I2C1_REF_CTRL_SRCSEL 0x0 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E0124, 0x013F3F07U ,0x01010F00U) - RegMask = (CRL_APB_I2C1_REF_CTRL_CLKACT_MASK | CRL_APB_I2C1_REF_CTRL_DIVISOR1_MASK | CRL_APB_I2C1_REF_CTRL_DIVISOR0_MASK | CRL_APB_I2C1_REF_CTRL_SRCSEL_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_I2C1_REF_CTRL_CLKACT_SHIFT - | 0x00000001U << CRL_APB_I2C1_REF_CTRL_DIVISOR1_SHIFT - | 0x0000000FU << CRL_APB_I2C1_REF_CTRL_DIVISOR0_SHIFT - | 0x00000000U << CRL_APB_I2C1_REF_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_I2C1_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010F00U); - /*############################################################################################################################ */ - - /*Register : CAN1_REF_CTRL @ 0XFF5E0088

- - Clock active signal. Switch to 0 to disable the clock - PSU_CRL_APB_CAN1_REF_CTRL_CLKACT 0x1 - - 6 bit divider - PSU_CRL_APB_CAN1_REF_CTRL_DIVISOR1 0x1 - - 6 bit divider - PSU_CRL_APB_CAN1_REF_CTRL_DIVISOR0 0xf - - 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_CAN1_REF_CTRL_SRCSEL 0x0 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E0088, 0x013F3F07U ,0x01010F00U) - RegMask = (CRL_APB_CAN1_REF_CTRL_CLKACT_MASK | CRL_APB_CAN1_REF_CTRL_DIVISOR1_MASK | CRL_APB_CAN1_REF_CTRL_DIVISOR0_MASK | CRL_APB_CAN1_REF_CTRL_SRCSEL_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_CAN1_REF_CTRL_CLKACT_SHIFT - | 0x00000001U << CRL_APB_CAN1_REF_CTRL_DIVISOR1_SHIFT - | 0x0000000FU << CRL_APB_CAN1_REF_CTRL_DIVISOR0_SHIFT - | 0x00000000U << CRL_APB_CAN1_REF_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_CAN1_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010F00U); - /*############################################################################################################################ */ - - /*Register : CPU_R5_CTRL @ 0XFF5E0090

- - Turing this off will shut down the OCM, some parts of the APM, and prevent transactions going from the FPD to the LPD and cou - d lead to system hang - PSU_CRL_APB_CPU_R5_CTRL_CLKACT 0x1 - - 6 bit divider - PSU_CRL_APB_CPU_R5_CTRL_DIVISOR0 0x3 - - 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_CPU_R5_CTRL_SRCSEL 0x2 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E0090, 0x01003F07U ,0x01000302U) - RegMask = (CRL_APB_CPU_R5_CTRL_CLKACT_MASK | CRL_APB_CPU_R5_CTRL_DIVISOR0_MASK | CRL_APB_CPU_R5_CTRL_SRCSEL_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_CPU_R5_CTRL_CLKACT_SHIFT - | 0x00000003U << CRL_APB_CPU_R5_CTRL_DIVISOR0_SHIFT - | 0x00000002U << CRL_APB_CPU_R5_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_CPU_R5_CTRL_OFFSET ,0x01003F07U ,0x01000302U); - /*############################################################################################################################ */ - - /*Register : IOU_SWITCH_CTRL @ 0XFF5E009C

- - Clock active signal. Switch to 0 to disable the clock - PSU_CRL_APB_IOU_SWITCH_CTRL_CLKACT 0x1 - - 6 bit divider - PSU_CRL_APB_IOU_SWITCH_CTRL_DIVISOR0 0x6 - - 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_IOU_SWITCH_CTRL_SRCSEL 0x2 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E009C, 0x01003F07U ,0x01000602U) - RegMask = (CRL_APB_IOU_SWITCH_CTRL_CLKACT_MASK | CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_MASK | CRL_APB_IOU_SWITCH_CTRL_SRCSEL_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_IOU_SWITCH_CTRL_CLKACT_SHIFT - | 0x00000006U << CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_SHIFT - | 0x00000002U << CRL_APB_IOU_SWITCH_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_IOU_SWITCH_CTRL_OFFSET ,0x01003F07U ,0x01000602U); - /*############################################################################################################################ */ - - /*Register : PCAP_CTRL @ 0XFF5E00A4

- - Clock active signal. Switch to 0 to disable the clock - PSU_CRL_APB_PCAP_CTRL_CLKACT 0x1 - - 6 bit divider - PSU_CRL_APB_PCAP_CTRL_DIVISOR0 0x6 - - 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_PCAP_CTRL_SRCSEL 0x2 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E00A4, 0x01003F07U ,0x01000602U) - RegMask = (CRL_APB_PCAP_CTRL_CLKACT_MASK | CRL_APB_PCAP_CTRL_DIVISOR0_MASK | CRL_APB_PCAP_CTRL_SRCSEL_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_PCAP_CTRL_CLKACT_SHIFT - | 0x00000006U << CRL_APB_PCAP_CTRL_DIVISOR0_SHIFT - | 0x00000002U << CRL_APB_PCAP_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_PCAP_CTRL_OFFSET ,0x01003F07U ,0x01000602U); - /*############################################################################################################################ */ - - /*Register : LPD_SWITCH_CTRL @ 0XFF5E00A8

- - Clock active signal. Switch to 0 to disable the clock - PSU_CRL_APB_LPD_SWITCH_CTRL_CLKACT 0x1 - - 6 bit divider - PSU_CRL_APB_LPD_SWITCH_CTRL_DIVISOR0 0x3 - - 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_LPD_SWITCH_CTRL_SRCSEL 0x2 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E00A8, 0x01003F07U ,0x01000302U) - RegMask = (CRL_APB_LPD_SWITCH_CTRL_CLKACT_MASK | CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_MASK | CRL_APB_LPD_SWITCH_CTRL_SRCSEL_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_LPD_SWITCH_CTRL_CLKACT_SHIFT - | 0x00000003U << CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_SHIFT - | 0x00000002U << CRL_APB_LPD_SWITCH_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_LPD_SWITCH_CTRL_OFFSET ,0x01003F07U ,0x01000302U); - /*############################################################################################################################ */ - - /*Register : LPD_LSBUS_CTRL @ 0XFF5E00AC

- - Clock active signal. Switch to 0 to disable the clock - PSU_CRL_APB_LPD_LSBUS_CTRL_CLKACT 0x1 - - 6 bit divider - PSU_CRL_APB_LPD_LSBUS_CTRL_DIVISOR0 0xf - - 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_LPD_LSBUS_CTRL_SRCSEL 0x2 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E00AC, 0x01003F07U ,0x01000F02U) - RegMask = (CRL_APB_LPD_LSBUS_CTRL_CLKACT_MASK | CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_MASK | CRL_APB_LPD_LSBUS_CTRL_SRCSEL_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_LPD_LSBUS_CTRL_CLKACT_SHIFT - | 0x0000000FU << CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_SHIFT - | 0x00000002U << CRL_APB_LPD_LSBUS_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_LPD_LSBUS_CTRL_OFFSET ,0x01003F07U ,0x01000F02U); - /*############################################################################################################################ */ - - /*Register : DBG_LPD_CTRL @ 0XFF5E00B0

- - Clock active signal. Switch to 0 to disable the clock - PSU_CRL_APB_DBG_LPD_CTRL_CLKACT 0x1 - - 6 bit divider - PSU_CRL_APB_DBG_LPD_CTRL_DIVISOR0 0x6 - - 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_DBG_LPD_CTRL_SRCSEL 0x2 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E00B0, 0x01003F07U ,0x01000602U) - RegMask = (CRL_APB_DBG_LPD_CTRL_CLKACT_MASK | CRL_APB_DBG_LPD_CTRL_DIVISOR0_MASK | CRL_APB_DBG_LPD_CTRL_SRCSEL_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_DBG_LPD_CTRL_CLKACT_SHIFT - | 0x00000006U << CRL_APB_DBG_LPD_CTRL_DIVISOR0_SHIFT - | 0x00000002U << CRL_APB_DBG_LPD_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_DBG_LPD_CTRL_OFFSET ,0x01003F07U ,0x01000602U); - /*############################################################################################################################ */ - - /*Register : ADMA_REF_CTRL @ 0XFF5E00B8

- - Clock active signal. Switch to 0 to disable the clock - PSU_CRL_APB_ADMA_REF_CTRL_CLKACT 0x1 - - 6 bit divider - PSU_CRL_APB_ADMA_REF_CTRL_DIVISOR0 0x3 - - 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_ADMA_REF_CTRL_SRCSEL 0x2 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E00B8, 0x01003F07U ,0x01000302U) - RegMask = (CRL_APB_ADMA_REF_CTRL_CLKACT_MASK | CRL_APB_ADMA_REF_CTRL_DIVISOR0_MASK | CRL_APB_ADMA_REF_CTRL_SRCSEL_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_ADMA_REF_CTRL_CLKACT_SHIFT - | 0x00000003U << CRL_APB_ADMA_REF_CTRL_DIVISOR0_SHIFT - | 0x00000002U << CRL_APB_ADMA_REF_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_ADMA_REF_CTRL_OFFSET ,0x01003F07U ,0x01000302U); - /*############################################################################################################################ */ - - /*Register : PL0_REF_CTRL @ 0XFF5E00C0

- - Clock active signal. Switch to 0 to disable the clock - PSU_CRL_APB_PL0_REF_CTRL_CLKACT 0x1 - - 6 bit divider - PSU_CRL_APB_PL0_REF_CTRL_DIVISOR1 0x1 - - 6 bit divider - PSU_CRL_APB_PL0_REF_CTRL_DIVISOR0 0xf - - 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_PL0_REF_CTRL_SRCSEL 0x0 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E00C0, 0x013F3F07U ,0x01010F00U) - RegMask = (CRL_APB_PL0_REF_CTRL_CLKACT_MASK | CRL_APB_PL0_REF_CTRL_DIVISOR1_MASK | CRL_APB_PL0_REF_CTRL_DIVISOR0_MASK | CRL_APB_PL0_REF_CTRL_SRCSEL_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_PL0_REF_CTRL_CLKACT_SHIFT - | 0x00000001U << CRL_APB_PL0_REF_CTRL_DIVISOR1_SHIFT - | 0x0000000FU << CRL_APB_PL0_REF_CTRL_DIVISOR0_SHIFT - | 0x00000000U << CRL_APB_PL0_REF_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_PL0_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010F00U); - /*############################################################################################################################ */ - - /*Register : PL1_REF_CTRL @ 0XFF5E00C4

- - Clock active signal. Switch to 0 to disable the clock - PSU_CRL_APB_PL1_REF_CTRL_CLKACT 0x1 - - 6 bit divider - PSU_CRL_APB_PL1_REF_CTRL_DIVISOR1 0x4 - - 6 bit divider - PSU_CRL_APB_PL1_REF_CTRL_DIVISOR0 0xf - - 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_PL1_REF_CTRL_SRCSEL 0x0 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E00C4, 0x013F3F07U ,0x01040F00U) - RegMask = (CRL_APB_PL1_REF_CTRL_CLKACT_MASK | CRL_APB_PL1_REF_CTRL_DIVISOR1_MASK | CRL_APB_PL1_REF_CTRL_DIVISOR0_MASK | CRL_APB_PL1_REF_CTRL_SRCSEL_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_PL1_REF_CTRL_CLKACT_SHIFT - | 0x00000004U << CRL_APB_PL1_REF_CTRL_DIVISOR1_SHIFT - | 0x0000000FU << CRL_APB_PL1_REF_CTRL_DIVISOR0_SHIFT - | 0x00000000U << CRL_APB_PL1_REF_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_PL1_REF_CTRL_OFFSET ,0x013F3F07U ,0x01040F00U); - /*############################################################################################################################ */ - - /*Register : PL2_REF_CTRL @ 0XFF5E00C8

- - Clock active signal. Switch to 0 to disable the clock - PSU_CRL_APB_PL2_REF_CTRL_CLKACT 0x1 - - 6 bit divider - PSU_CRL_APB_PL2_REF_CTRL_DIVISOR1 0x1 - - 6 bit divider - PSU_CRL_APB_PL2_REF_CTRL_DIVISOR0 0x4 - - 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_PL2_REF_CTRL_SRCSEL 0x2 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E00C8, 0x013F3F07U ,0x01010402U) - RegMask = (CRL_APB_PL2_REF_CTRL_CLKACT_MASK | CRL_APB_PL2_REF_CTRL_DIVISOR1_MASK | CRL_APB_PL2_REF_CTRL_DIVISOR0_MASK | CRL_APB_PL2_REF_CTRL_SRCSEL_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_PL2_REF_CTRL_CLKACT_SHIFT - | 0x00000001U << CRL_APB_PL2_REF_CTRL_DIVISOR1_SHIFT - | 0x00000004U << CRL_APB_PL2_REF_CTRL_DIVISOR0_SHIFT - | 0x00000002U << CRL_APB_PL2_REF_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_PL2_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010402U); - /*############################################################################################################################ */ - - /*Register : PL3_REF_CTRL @ 0XFF5E00CC

- - Clock active signal. Switch to 0 to disable the clock - PSU_CRL_APB_PL3_REF_CTRL_CLKACT 0x1 - - 6 bit divider - PSU_CRL_APB_PL3_REF_CTRL_DIVISOR1 0x1 - - 6 bit divider - PSU_CRL_APB_PL3_REF_CTRL_DIVISOR0 0x3 - - 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_PL3_REF_CTRL_SRCSEL 0x2 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E00CC, 0x013F3F07U ,0x01010302U) - RegMask = (CRL_APB_PL3_REF_CTRL_CLKACT_MASK | CRL_APB_PL3_REF_CTRL_DIVISOR1_MASK | CRL_APB_PL3_REF_CTRL_DIVISOR0_MASK | CRL_APB_PL3_REF_CTRL_SRCSEL_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_PL3_REF_CTRL_CLKACT_SHIFT - | 0x00000001U << CRL_APB_PL3_REF_CTRL_DIVISOR1_SHIFT - | 0x00000003U << CRL_APB_PL3_REF_CTRL_DIVISOR0_SHIFT - | 0x00000002U << CRL_APB_PL3_REF_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_PL3_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010302U); - /*############################################################################################################################ */ - - /*Register : AMS_REF_CTRL @ 0XFF5E0108

- - 6 bit divider - PSU_CRL_APB_AMS_REF_CTRL_DIVISOR1 0x1 - - 6 bit divider - PSU_CRL_APB_AMS_REF_CTRL_DIVISOR0 0x1d - - 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_AMS_REF_CTRL_SRCSEL 0x2 - - Clock active signal. Switch to 0 to disable the clock - PSU_CRL_APB_AMS_REF_CTRL_CLKACT 0x1 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E0108, 0x013F3F07U ,0x01011D02U) - RegMask = (CRL_APB_AMS_REF_CTRL_DIVISOR1_MASK | CRL_APB_AMS_REF_CTRL_DIVISOR0_MASK | CRL_APB_AMS_REF_CTRL_SRCSEL_MASK | CRL_APB_AMS_REF_CTRL_CLKACT_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_AMS_REF_CTRL_DIVISOR1_SHIFT - | 0x0000001DU << CRL_APB_AMS_REF_CTRL_DIVISOR0_SHIFT - | 0x00000002U << CRL_APB_AMS_REF_CTRL_SRCSEL_SHIFT - | 0x00000001U << CRL_APB_AMS_REF_CTRL_CLKACT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_AMS_REF_CTRL_OFFSET ,0x013F3F07U ,0x01011D02U); - /*############################################################################################################################ */ - - /*Register : DLL_REF_CTRL @ 0XFF5E0104

- - 000 = IOPLL; 001 = RPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This - is not usually an issue, but designers must be aware.) - PSU_CRL_APB_DLL_REF_CTRL_SRCSEL 0 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E0104, 0x00000007U ,0x00000000U) - RegMask = (CRL_APB_DLL_REF_CTRL_SRCSEL_MASK | 0 ); - - RegVal = ((0x00000000U << CRL_APB_DLL_REF_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_DLL_REF_CTRL_OFFSET ,0x00000007U ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : TIMESTAMP_REF_CTRL @ 0XFF5E0128

- - 6 bit divider - PSU_CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0 0xf - - 1XX = pss_ref_clk; 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and - cycles of the new clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL 0x0 - - Clock active signal. Switch to 0 to disable the clock - PSU_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT 0x1 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E0128, 0x01003F07U ,0x01000F00U) - RegMask = (CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_MASK | CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_MASK | CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_MASK | 0 ); - - RegVal = ((0x0000000FU << CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_SHIFT - | 0x00000000U << CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_SHIFT - | 0x00000001U << CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_TIMESTAMP_REF_CTRL_OFFSET ,0x01003F07U ,0x01000F00U); - /*############################################################################################################################ */ - - /*Register : SATA_REF_CTRL @ 0XFD1A00A0

- - 000 = IOPLL_TO_FPD; 010 = APLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of - he new clock. This is not usually an issue, but designers must be aware.) - PSU_CRF_APB_SATA_REF_CTRL_SRCSEL 0x0 - - Clock active signal. Switch to 0 to disable the clock - PSU_CRF_APB_SATA_REF_CTRL_CLKACT 0x1 - - 6 bit divider - PSU_CRF_APB_SATA_REF_CTRL_DIVISOR0 0x2 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFD1A00A0, 0x01003F07U ,0x01000200U) - RegMask = (CRF_APB_SATA_REF_CTRL_SRCSEL_MASK | CRF_APB_SATA_REF_CTRL_CLKACT_MASK | CRF_APB_SATA_REF_CTRL_DIVISOR0_MASK | 0 ); - - RegVal = ((0x00000000U << CRF_APB_SATA_REF_CTRL_SRCSEL_SHIFT - | 0x00000001U << CRF_APB_SATA_REF_CTRL_CLKACT_SHIFT - | 0x00000002U << CRF_APB_SATA_REF_CTRL_DIVISOR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_SATA_REF_CTRL_OFFSET ,0x01003F07U ,0x01000200U); - /*############################################################################################################################ */ - - /*Register : PCIE_REF_CTRL @ 0XFD1A00B4

- - 000 = IOPLL_TO_FPD; 010 = RPLL_TO_FPD; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cyc - es of the new clock. This is not usually an issue, but designers must be aware.) - PSU_CRF_APB_PCIE_REF_CTRL_SRCSEL 0x0 - - Clock active signal. Switch to 0 to disable the clock - PSU_CRF_APB_PCIE_REF_CTRL_CLKACT 0x1 - - 6 bit divider - PSU_CRF_APB_PCIE_REF_CTRL_DIVISOR0 0x2 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFD1A00B4, 0x01003F07U ,0x01000200U) - RegMask = (CRF_APB_PCIE_REF_CTRL_SRCSEL_MASK | CRF_APB_PCIE_REF_CTRL_CLKACT_MASK | CRF_APB_PCIE_REF_CTRL_DIVISOR0_MASK | 0 ); - - RegVal = ((0x00000000U << CRF_APB_PCIE_REF_CTRL_SRCSEL_SHIFT - | 0x00000001U << CRF_APB_PCIE_REF_CTRL_CLKACT_SHIFT - | 0x00000002U << CRF_APB_PCIE_REF_CTRL_DIVISOR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_PCIE_REF_CTRL_OFFSET ,0x01003F07U ,0x01000200U); - /*############################################################################################################################ */ - - /*Register : DP_VIDEO_REF_CTRL @ 0XFD1A0070

- - 6 bit divider - PSU_CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1 0x1 - - 6 bit divider - PSU_CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0 0x3 - - 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (This signal may only be toggled after 4 cycles of the - ld clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.) - PSU_CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL 0x3 - - Clock active signal. Switch to 0 to disable the clock - PSU_CRF_APB_DP_VIDEO_REF_CTRL_CLKACT 0x1 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFD1A0070, 0x013F3F07U ,0x01010303U) - RegMask = (CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_MASK | CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_MASK | CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_MASK | CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_MASK | 0 ); - - RegVal = ((0x00000001U << CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_SHIFT - | 0x00000003U << CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_SHIFT - | 0x00000003U << CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_SHIFT - | 0x00000001U << CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_DP_VIDEO_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010303U); - /*############################################################################################################################ */ - - /*Register : DP_AUDIO_REF_CTRL @ 0XFD1A0074

- - 6 bit divider - PSU_CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1 0x1 - - 6 bit divider - PSU_CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0 0x27 - - 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (This signal may only be toggled after 4 cycles of the - ld clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.) - PSU_CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL 0x0 - - Clock active signal. Switch to 0 to disable the clock - PSU_CRF_APB_DP_AUDIO_REF_CTRL_CLKACT 0x1 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFD1A0074, 0x013F3F07U ,0x01012700U) - RegMask = (CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_MASK | CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_MASK | CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_MASK | CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_MASK | 0 ); - - RegVal = ((0x00000001U << CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_SHIFT - | 0x00000027U << CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_SHIFT - | 0x00000000U << CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_SHIFT - | 0x00000001U << CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_DP_AUDIO_REF_CTRL_OFFSET ,0x013F3F07U ,0x01012700U); - /*############################################################################################################################ */ - - /*Register : DP_STC_REF_CTRL @ 0XFD1A007C

- - 6 bit divider - PSU_CRF_APB_DP_STC_REF_CTRL_DIVISOR1 0x1 - - 6 bit divider - PSU_CRF_APB_DP_STC_REF_CTRL_DIVISOR0 0x11 - - 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of t - e new clock. This is not usually an issue, but designers must be aware.) - PSU_CRF_APB_DP_STC_REF_CTRL_SRCSEL 0x3 - - Clock active signal. Switch to 0 to disable the clock - PSU_CRF_APB_DP_STC_REF_CTRL_CLKACT 0x1 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFD1A007C, 0x013F3F07U ,0x01011103U) - RegMask = (CRF_APB_DP_STC_REF_CTRL_DIVISOR1_MASK | CRF_APB_DP_STC_REF_CTRL_DIVISOR0_MASK | CRF_APB_DP_STC_REF_CTRL_SRCSEL_MASK | CRF_APB_DP_STC_REF_CTRL_CLKACT_MASK | 0 ); - - RegVal = ((0x00000001U << CRF_APB_DP_STC_REF_CTRL_DIVISOR1_SHIFT - | 0x00000011U << CRF_APB_DP_STC_REF_CTRL_DIVISOR0_SHIFT - | 0x00000003U << CRF_APB_DP_STC_REF_CTRL_SRCSEL_SHIFT - | 0x00000001U << CRF_APB_DP_STC_REF_CTRL_CLKACT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_DP_STC_REF_CTRL_OFFSET ,0x013F3F07U ,0x01011103U); - /*############################################################################################################################ */ - - /*Register : ACPU_CTRL @ 0XFD1A0060

- - 6 bit divider - PSU_CRF_APB_ACPU_CTRL_DIVISOR0 0x1 - - 000 = APLL; 010 = DPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - lock. This is not usually an issue, but designers must be aware.) - PSU_CRF_APB_ACPU_CTRL_SRCSEL 0x0 - - Clock active signal. Switch to 0 to disable the clock. For the half speed APU Clock - PSU_CRF_APB_ACPU_CTRL_CLKACT_HALF 0x1 - - Clock active signal. Switch to 0 to disable the clock. For the full speed ACPUX Clock. This will shut off the high speed cloc - to the entire APU - PSU_CRF_APB_ACPU_CTRL_CLKACT_FULL 0x1 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFD1A0060, 0x03003F07U ,0x03000100U) - RegMask = (CRF_APB_ACPU_CTRL_DIVISOR0_MASK | CRF_APB_ACPU_CTRL_SRCSEL_MASK | CRF_APB_ACPU_CTRL_CLKACT_HALF_MASK | CRF_APB_ACPU_CTRL_CLKACT_FULL_MASK | 0 ); - - RegVal = ((0x00000001U << CRF_APB_ACPU_CTRL_DIVISOR0_SHIFT - | 0x00000000U << CRF_APB_ACPU_CTRL_SRCSEL_SHIFT - | 0x00000001U << CRF_APB_ACPU_CTRL_CLKACT_HALF_SHIFT - | 0x00000001U << CRF_APB_ACPU_CTRL_CLKACT_FULL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_ACPU_CTRL_OFFSET ,0x03003F07U ,0x03000100U); - /*############################################################################################################################ */ - - /*Register : DBG_TRACE_CTRL @ 0XFD1A0064

- - 6 bit divider - PSU_CRF_APB_DBG_TRACE_CTRL_DIVISOR0 0x2 - - 000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of - he new clock. This is not usually an issue, but designers must be aware.) - PSU_CRF_APB_DBG_TRACE_CTRL_SRCSEL 0x0 - - Clock active signal. Switch to 0 to disable the clock - PSU_CRF_APB_DBG_TRACE_CTRL_CLKACT 0x1 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFD1A0064, 0x01003F07U ,0x01000200U) - RegMask = (CRF_APB_DBG_TRACE_CTRL_DIVISOR0_MASK | CRF_APB_DBG_TRACE_CTRL_SRCSEL_MASK | CRF_APB_DBG_TRACE_CTRL_CLKACT_MASK | 0 ); - - RegVal = ((0x00000002U << CRF_APB_DBG_TRACE_CTRL_DIVISOR0_SHIFT - | 0x00000000U << CRF_APB_DBG_TRACE_CTRL_SRCSEL_SHIFT - | 0x00000001U << CRF_APB_DBG_TRACE_CTRL_CLKACT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_DBG_TRACE_CTRL_OFFSET ,0x01003F07U ,0x01000200U); - /*############################################################################################################################ */ - - /*Register : DBG_FPD_CTRL @ 0XFD1A0068

- - 6 bit divider - PSU_CRF_APB_DBG_FPD_CTRL_DIVISOR0 0x2 - - 000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of - he new clock. This is not usually an issue, but designers must be aware.) - PSU_CRF_APB_DBG_FPD_CTRL_SRCSEL 0x0 - - Clock active signal. Switch to 0 to disable the clock - PSU_CRF_APB_DBG_FPD_CTRL_CLKACT 0x1 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFD1A0068, 0x01003F07U ,0x01000200U) - RegMask = (CRF_APB_DBG_FPD_CTRL_DIVISOR0_MASK | CRF_APB_DBG_FPD_CTRL_SRCSEL_MASK | CRF_APB_DBG_FPD_CTRL_CLKACT_MASK | 0 ); - - RegVal = ((0x00000002U << CRF_APB_DBG_FPD_CTRL_DIVISOR0_SHIFT - | 0x00000000U << CRF_APB_DBG_FPD_CTRL_SRCSEL_SHIFT - | 0x00000001U << CRF_APB_DBG_FPD_CTRL_CLKACT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_DBG_FPD_CTRL_OFFSET ,0x01003F07U ,0x01000200U); - /*############################################################################################################################ */ - - /*Register : DDR_CTRL @ 0XFD1A0080

- - 6 bit divider - PSU_CRF_APB_DDR_CTRL_DIVISOR0 0x2 - - 000 = DPLL; 001 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This - s not usually an issue, but designers must be aware.) - PSU_CRF_APB_DDR_CTRL_SRCSEL 0x0 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFD1A0080, 0x00003F07U ,0x00000200U) - RegMask = (CRF_APB_DDR_CTRL_DIVISOR0_MASK | CRF_APB_DDR_CTRL_SRCSEL_MASK | 0 ); - - RegVal = ((0x00000002U << CRF_APB_DDR_CTRL_DIVISOR0_SHIFT - | 0x00000000U << CRF_APB_DDR_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_DDR_CTRL_OFFSET ,0x00003F07U ,0x00000200U); - /*############################################################################################################################ */ - - /*Register : GPU_REF_CTRL @ 0XFD1A0084

- - 6 bit divider - PSU_CRF_APB_GPU_REF_CTRL_DIVISOR0 0x1 - - 000 = IOPLL_TO_FPD; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of - he new clock. This is not usually an issue, but designers must be aware.) - PSU_CRF_APB_GPU_REF_CTRL_SRCSEL 0x0 - - Clock active signal. Switch to 0 to disable the clock, which will stop clock for GPU (and both Pixel Processors). - PSU_CRF_APB_GPU_REF_CTRL_CLKACT 0x1 - - Clock active signal for Pixel Processor. Switch to 0 to disable the clock only to this Pixel Processor - PSU_CRF_APB_GPU_REF_CTRL_PP0_CLKACT 0x1 - - Clock active signal for Pixel Processor. Switch to 0 to disable the clock only to this Pixel Processor - PSU_CRF_APB_GPU_REF_CTRL_PP1_CLKACT 0x1 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFD1A0084, 0x07003F07U ,0x07000100U) - RegMask = (CRF_APB_GPU_REF_CTRL_DIVISOR0_MASK | CRF_APB_GPU_REF_CTRL_SRCSEL_MASK | CRF_APB_GPU_REF_CTRL_CLKACT_MASK | CRF_APB_GPU_REF_CTRL_PP0_CLKACT_MASK | CRF_APB_GPU_REF_CTRL_PP1_CLKACT_MASK | 0 ); - - RegVal = ((0x00000001U << CRF_APB_GPU_REF_CTRL_DIVISOR0_SHIFT - | 0x00000000U << CRF_APB_GPU_REF_CTRL_SRCSEL_SHIFT - | 0x00000001U << CRF_APB_GPU_REF_CTRL_CLKACT_SHIFT - | 0x00000001U << CRF_APB_GPU_REF_CTRL_PP0_CLKACT_SHIFT - | 0x00000001U << CRF_APB_GPU_REF_CTRL_PP1_CLKACT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_GPU_REF_CTRL_OFFSET ,0x07003F07U ,0x07000100U); - /*############################################################################################################################ */ - - /*Register : GDMA_REF_CTRL @ 0XFD1A00B8

- - 6 bit divider - PSU_CRF_APB_GDMA_REF_CTRL_DIVISOR0 0x2 - - 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - lock. This is not usually an issue, but designers must be aware.) - PSU_CRF_APB_GDMA_REF_CTRL_SRCSEL 0x0 - - Clock active signal. Switch to 0 to disable the clock - PSU_CRF_APB_GDMA_REF_CTRL_CLKACT 0x1 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFD1A00B8, 0x01003F07U ,0x01000200U) - RegMask = (CRF_APB_GDMA_REF_CTRL_DIVISOR0_MASK | CRF_APB_GDMA_REF_CTRL_SRCSEL_MASK | CRF_APB_GDMA_REF_CTRL_CLKACT_MASK | 0 ); - - RegVal = ((0x00000002U << CRF_APB_GDMA_REF_CTRL_DIVISOR0_SHIFT - | 0x00000000U << CRF_APB_GDMA_REF_CTRL_SRCSEL_SHIFT - | 0x00000001U << CRF_APB_GDMA_REF_CTRL_CLKACT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_GDMA_REF_CTRL_OFFSET ,0x01003F07U ,0x01000200U); - /*############################################################################################################################ */ - - /*Register : DPDMA_REF_CTRL @ 0XFD1A00BC

- - 6 bit divider - PSU_CRF_APB_DPDMA_REF_CTRL_DIVISOR0 0x2 - - 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - lock. This is not usually an issue, but designers must be aware.) - PSU_CRF_APB_DPDMA_REF_CTRL_SRCSEL 0x0 - - Clock active signal. Switch to 0 to disable the clock - PSU_CRF_APB_DPDMA_REF_CTRL_CLKACT 0x1 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFD1A00BC, 0x01003F07U ,0x01000200U) - RegMask = (CRF_APB_DPDMA_REF_CTRL_DIVISOR0_MASK | CRF_APB_DPDMA_REF_CTRL_SRCSEL_MASK | CRF_APB_DPDMA_REF_CTRL_CLKACT_MASK | 0 ); - - RegVal = ((0x00000002U << CRF_APB_DPDMA_REF_CTRL_DIVISOR0_SHIFT - | 0x00000000U << CRF_APB_DPDMA_REF_CTRL_SRCSEL_SHIFT - | 0x00000001U << CRF_APB_DPDMA_REF_CTRL_CLKACT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_DPDMA_REF_CTRL_OFFSET ,0x01003F07U ,0x01000200U); - /*############################################################################################################################ */ - - /*Register : TOPSW_MAIN_CTRL @ 0XFD1A00C0

- - 6 bit divider - PSU_CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0 0x2 - - 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - lock. This is not usually an issue, but designers must be aware.) - PSU_CRF_APB_TOPSW_MAIN_CTRL_SRCSEL 0x2 - - Clock active signal. Switch to 0 to disable the clock - PSU_CRF_APB_TOPSW_MAIN_CTRL_CLKACT 0x1 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFD1A00C0, 0x01003F07U ,0x01000202U) - RegMask = (CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_MASK | CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_MASK | CRF_APB_TOPSW_MAIN_CTRL_CLKACT_MASK | 0 ); - - RegVal = ((0x00000002U << CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_SHIFT - | 0x00000002U << CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_SHIFT - | 0x00000001U << CRF_APB_TOPSW_MAIN_CTRL_CLKACT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_TOPSW_MAIN_CTRL_OFFSET ,0x01003F07U ,0x01000202U); - /*############################################################################################################################ */ - - /*Register : TOPSW_LSBUS_CTRL @ 0XFD1A00C4

- - 6 bit divider - PSU_CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0 0x5 - - 000 = APLL; 010 = IOPLL_TO_FPD; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of - he new clock. This is not usually an issue, but designers must be aware.) - PSU_CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL 0x2 - - Clock active signal. Switch to 0 to disable the clock - PSU_CRF_APB_TOPSW_LSBUS_CTRL_CLKACT 0x1 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFD1A00C4, 0x01003F07U ,0x01000502U) - RegMask = (CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_MASK | CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_MASK | CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_MASK | 0 ); - - RegVal = ((0x00000005U << CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_SHIFT - | 0x00000002U << CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_SHIFT - | 0x00000001U << CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_TOPSW_LSBUS_CTRL_OFFSET ,0x01003F07U ,0x01000502U); - /*############################################################################################################################ */ - - /*Register : DBG_TSTMP_CTRL @ 0XFD1A00F8

- - 6 bit divider - PSU_CRF_APB_DBG_TSTMP_CTRL_DIVISOR0 0x2 - - 000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of - he new clock. This is not usually an issue, but designers must be aware.) - PSU_CRF_APB_DBG_TSTMP_CTRL_SRCSEL 0x0 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFD1A00F8, 0x00003F07U ,0x00000200U) - RegMask = (CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_MASK | CRF_APB_DBG_TSTMP_CTRL_SRCSEL_MASK | 0 ); - - RegVal = ((0x00000002U << CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_SHIFT - | 0x00000000U << CRF_APB_DBG_TSTMP_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_DBG_TSTMP_CTRL_OFFSET ,0x00003F07U ,0x00000200U); - /*############################################################################################################################ */ - - /*Register : IOU_TTC_APB_CLK @ 0XFF180380

- - 00" = Select the APB switch clock for the APB interface of TTC0'01" = Select the PLL ref clock for the APB interface of TTC0' - 0" = Select the R5 clock for the APB interface of TTC0 - PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL 0 - - 00" = Select the APB switch clock for the APB interface of TTC1'01" = Select the PLL ref clock for the APB interface of TTC1' - 0" = Select the R5 clock for the APB interface of TTC1 - PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL 0 - - 00" = Select the APB switch clock for the APB interface of TTC2'01" = Select the PLL ref clock for the APB interface of TTC2' - 0" = Select the R5 clock for the APB interface of TTC2 - PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL 0 - - 00" = Select the APB switch clock for the APB interface of TTC3'01" = Select the PLL ref clock for the APB interface of TTC3' - 0" = Select the R5 clock for the APB interface of TTC3 - PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL 0 - - TTC APB clock select - (OFFSET, MASK, VALUE) (0XFF180380, 0x000000FFU ,0x00000000U) - RegMask = (IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_MASK | IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_MASK | IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_MASK | IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_IOU_TTC_APB_CLK_OFFSET ,0x000000FFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : WDT_CLK_SEL @ 0XFD610100

- - System watchdog timer clock source selection: 0: Internal APB clock 1: External (PL clock via EMIO or Pinout clock via MIO) - PSU_FPD_SLCR_WDT_CLK_SEL_SELECT 0 - - SWDT clock source select - (OFFSET, MASK, VALUE) (0XFD610100, 0x00000001U ,0x00000000U) - RegMask = (FPD_SLCR_WDT_CLK_SEL_SELECT_MASK | 0 ); - - RegVal = ((0x00000000U << FPD_SLCR_WDT_CLK_SEL_SELECT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (FPD_SLCR_WDT_CLK_SEL_OFFSET ,0x00000001U ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : WDT_CLK_SEL @ 0XFF180300

- - System watchdog timer clock source selection: 0: internal clock APB clock 1: external clock from PL via EMIO, or from pinout - ia MIO - PSU_IOU_SLCR_WDT_CLK_SEL_SELECT 0 - - SWDT clock source select - (OFFSET, MASK, VALUE) (0XFF180300, 0x00000001U ,0x00000000U) - RegMask = (IOU_SLCR_WDT_CLK_SEL_SELECT_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_WDT_CLK_SEL_SELECT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_WDT_CLK_SEL_OFFSET ,0x00000001U ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : CSUPMU_WDT_CLK_SEL @ 0XFF410050

- - System watchdog timer clock source selection: 0: internal clock APB clock 1: external clock pss_ref_clk - PSU_LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT 0 - - SWDT clock source select - (OFFSET, MASK, VALUE) (0XFF410050, 0x00000001U ,0x00000000U) - RegMask = (LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_MASK | 0 ); - - RegVal = ((0x00000000U << LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (LPD_SLCR_CSUPMU_WDT_CLK_SEL_OFFSET ,0x00000001U ,0x00000000U); - /*############################################################################################################################ */ - - - return 1; + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_CAN1_REF_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_CAN1_REF_CTRL_DIVISOR1 0x1 + + * 6 bit divider + * PSU_CRL_APB_CAN1_REF_CTRL_DIVISOR0 0xf + + * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_CAN1_REF_CTRL_SRCSEL 0x0 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E0088, 0x013F3F07U ,0x01010F00U) + */ + PSU_Mask_Write(CRL_APB_CAN1_REF_CTRL_OFFSET, + 0x013F3F07U, 0x01010F00U); +/*##################################################################### */ + + /* + * Register : CPU_R5_CTRL @ 0XFF5E0090 + + * Turing this off will shut down the OCM, some parts of the APM, and preve + * nt transactions going from the FPD to the LPD and could lead to system h + * ang + * PSU_CRL_APB_CPU_R5_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_CPU_R5_CTRL_DIVISOR0 0x3 + + * 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_CPU_R5_CTRL_SRCSEL 0x2 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E0090, 0x01003F07U ,0x01000302U) + */ + PSU_Mask_Write(CRL_APB_CPU_R5_CTRL_OFFSET, 0x01003F07U, 0x01000302U); +/*##################################################################### */ + + /* + * Register : IOU_SWITCH_CTRL @ 0XFF5E009C + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_IOU_SWITCH_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_IOU_SWITCH_CTRL_DIVISOR0 0x6 + + * 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_IOU_SWITCH_CTRL_SRCSEL 0x2 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E009C, 0x01003F07U ,0x01000602U) + */ + PSU_Mask_Write(CRL_APB_IOU_SWITCH_CTRL_OFFSET, + 0x01003F07U, 0x01000602U); +/*##################################################################### */ + + /* + * Register : PCAP_CTRL @ 0XFF5E00A4 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_PCAP_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_PCAP_CTRL_DIVISOR0 0x8 + + * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_PCAP_CTRL_SRCSEL 0x0 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E00A4, 0x01003F07U ,0x01000800U) + */ + PSU_Mask_Write(CRL_APB_PCAP_CTRL_OFFSET, 0x01003F07U, 0x01000800U); +/*##################################################################### */ + + /* + * Register : LPD_SWITCH_CTRL @ 0XFF5E00A8 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_LPD_SWITCH_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_LPD_SWITCH_CTRL_DIVISOR0 0x3 + + * 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_LPD_SWITCH_CTRL_SRCSEL 0x2 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E00A8, 0x01003F07U ,0x01000302U) + */ + PSU_Mask_Write(CRL_APB_LPD_SWITCH_CTRL_OFFSET, + 0x01003F07U, 0x01000302U); +/*##################################################################### */ + + /* + * Register : LPD_LSBUS_CTRL @ 0XFF5E00AC + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_LPD_LSBUS_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_LPD_LSBUS_CTRL_DIVISOR0 0xf + + * 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_LPD_LSBUS_CTRL_SRCSEL 0x2 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E00AC, 0x01003F07U ,0x01000F02U) + */ + PSU_Mask_Write(CRL_APB_LPD_LSBUS_CTRL_OFFSET, + 0x01003F07U, 0x01000F02U); +/*##################################################################### */ + + /* + * Register : DBG_LPD_CTRL @ 0XFF5E00B0 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_DBG_LPD_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_DBG_LPD_CTRL_DIVISOR0 0x6 + + * 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_DBG_LPD_CTRL_SRCSEL 0x2 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E00B0, 0x01003F07U ,0x01000602U) + */ + PSU_Mask_Write(CRL_APB_DBG_LPD_CTRL_OFFSET, + 0x01003F07U, 0x01000602U); +/*##################################################################### */ + + /* + * Register : ADMA_REF_CTRL @ 0XFF5E00B8 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_ADMA_REF_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_ADMA_REF_CTRL_DIVISOR0 0x3 + + * 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_ADMA_REF_CTRL_SRCSEL 0x2 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E00B8, 0x01003F07U ,0x01000302U) + */ + PSU_Mask_Write(CRL_APB_ADMA_REF_CTRL_OFFSET, + 0x01003F07U, 0x01000302U); +/*##################################################################### */ + + /* + * Register : PL0_REF_CTRL @ 0XFF5E00C0 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_PL0_REF_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_PL0_REF_CTRL_DIVISOR1 0x1 + + * 6 bit divider + * PSU_CRL_APB_PL0_REF_CTRL_DIVISOR0 0xf + + * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_PL0_REF_CTRL_SRCSEL 0x0 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E00C0, 0x013F3F07U ,0x01010F00U) + */ + PSU_Mask_Write(CRL_APB_PL0_REF_CTRL_OFFSET, + 0x013F3F07U, 0x01010F00U); +/*##################################################################### */ + + /* + * Register : AMS_REF_CTRL @ 0XFF5E0108 + + * 6 bit divider + * PSU_CRL_APB_AMS_REF_CTRL_DIVISOR1 0x1 + + * 6 bit divider + * PSU_CRL_APB_AMS_REF_CTRL_DIVISOR0 0x1e + + * 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_AMS_REF_CTRL_SRCSEL 0x2 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_AMS_REF_CTRL_CLKACT 0x1 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E0108, 0x013F3F07U ,0x01011E02U) + */ + PSU_Mask_Write(CRL_APB_AMS_REF_CTRL_OFFSET, + 0x013F3F07U, 0x01011E02U); +/*##################################################################### */ + + /* + * Register : DLL_REF_CTRL @ 0XFF5E0104 + + * 000 = IOPLL; 001 = RPLL; (This signal may only be toggled after 4 cycles + * of the old clock and 4 cycles of the new clock. This is not usually an + * issue, but designers must be aware.) + * PSU_CRL_APB_DLL_REF_CTRL_SRCSEL 0 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E0104, 0x00000007U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_DLL_REF_CTRL_OFFSET, + 0x00000007U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : TIMESTAMP_REF_CTRL @ 0XFF5E0128 + + * 6 bit divider + * PSU_CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0 0xf + + * 1XX = pss_ref_clk; 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may + * only be toggled after 4 cycles of the old clock and 4 cycles of the new + * clock. This is not usually an issue, but designers must be aware.) + * PSU_CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL 0x0 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT 0x1 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E0128, 0x01003F07U ,0x01000F00U) + */ + PSU_Mask_Write(CRL_APB_TIMESTAMP_REF_CTRL_OFFSET, + 0x01003F07U, 0x01000F00U); +/*##################################################################### */ + + /* + * Register : SATA_REF_CTRL @ 0XFD1A00A0 + + * 000 = IOPLL_TO_FPD; 010 = APLL; 011 = DPLL; (This signal may only be tog + * gled after 4 cycles of the old clock and 4 cycles of the new clock. This + * is not usually an issue, but designers must be aware.) + * PSU_CRF_APB_SATA_REF_CTRL_SRCSEL 0x0 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRF_APB_SATA_REF_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRF_APB_SATA_REF_CTRL_DIVISOR0 0x2 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFD1A00A0, 0x01003F07U ,0x01000200U) + */ + PSU_Mask_Write(CRF_APB_SATA_REF_CTRL_OFFSET, + 0x01003F07U, 0x01000200U); +/*##################################################################### */ + + /* + * Register : PCIE_REF_CTRL @ 0XFD1A00B4 + + * 000 = IOPLL_TO_FPD; 010 = RPLL_TO_FPD; 011 = DPLL; (This signal may only + * be toggled after 4 cycles of the old clock and 4 cycles of the new cloc + * k. This is not usually an issue, but designers must be aware.) + * PSU_CRF_APB_PCIE_REF_CTRL_SRCSEL 0x0 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRF_APB_PCIE_REF_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRF_APB_PCIE_REF_CTRL_DIVISOR0 0x2 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFD1A00B4, 0x01003F07U ,0x01000200U) + */ + PSU_Mask_Write(CRF_APB_PCIE_REF_CTRL_OFFSET, + 0x01003F07U, 0x01000200U); +/*##################################################################### */ + + /* + * Register : DP_VIDEO_REF_CTRL @ 0XFD1A0070 + + * 6 bit divider + * PSU_CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1 0x1 + + * 6 bit divider + * PSU_CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0 0x5 + + * 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (T + * his signal may only be toggled after 4 cycles of the old clock and 4 cyc + * les of the new clock. This is not usually an issue, but designers must b + * e aware.) + * PSU_CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL 0x0 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRF_APB_DP_VIDEO_REF_CTRL_CLKACT 0x1 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFD1A0070, 0x013F3F07U ,0x01010500U) + */ + PSU_Mask_Write(CRF_APB_DP_VIDEO_REF_CTRL_OFFSET, + 0x013F3F07U, 0x01010500U); +/*##################################################################### */ + + /* + * Register : DP_AUDIO_REF_CTRL @ 0XFD1A0074 + + * 6 bit divider + * PSU_CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1 0x1 + + * 6 bit divider + * PSU_CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0 0xf + + * 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (T + * his signal may only be toggled after 4 cycles of the old clock and 4 cyc + * les of the new clock. This is not usually an issue, but designers must b + * e aware.) + * PSU_CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL 0x3 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRF_APB_DP_AUDIO_REF_CTRL_CLKACT 0x1 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFD1A0074, 0x013F3F07U ,0x01010F03U) + */ + PSU_Mask_Write(CRF_APB_DP_AUDIO_REF_CTRL_OFFSET, + 0x013F3F07U, 0x01010F03U); +/*##################################################################### */ + + /* + * Register : DP_STC_REF_CTRL @ 0XFD1A007C + + * 6 bit divider + * PSU_CRF_APB_DP_STC_REF_CTRL_DIVISOR1 0x1 + + * 6 bit divider + * PSU_CRF_APB_DP_STC_REF_CTRL_DIVISOR0 0xe + + * 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD; (This signal may only be togg + * led after 4 cycles of the old clock and 4 cycles of the new clock. This + * is not usually an issue, but designers must be aware.) + * PSU_CRF_APB_DP_STC_REF_CTRL_SRCSEL 0x3 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRF_APB_DP_STC_REF_CTRL_CLKACT 0x1 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFD1A007C, 0x013F3F07U ,0x01010E03U) + */ + PSU_Mask_Write(CRF_APB_DP_STC_REF_CTRL_OFFSET, + 0x013F3F07U, 0x01010E03U); +/*##################################################################### */ + + /* + * Register : ACPU_CTRL @ 0XFD1A0060 + + * 6 bit divider + * PSU_CRF_APB_ACPU_CTRL_DIVISOR0 0x1 + + * 000 = APLL; 010 = DPLL; 011 = VPLL; (This signal may only be toggled aft + * er 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRF_APB_ACPU_CTRL_SRCSEL 0x0 + + * Clock active signal. Switch to 0 to disable the clock. For the half spee + * d APU Clock + * PSU_CRF_APB_ACPU_CTRL_CLKACT_HALF 0x1 + + * Clock active signal. Switch to 0 to disable the clock. For the full spee + * d ACPUX Clock. This will shut off the high speed clock to the entire APU + * PSU_CRF_APB_ACPU_CTRL_CLKACT_FULL 0x1 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFD1A0060, 0x03003F07U ,0x03000100U) + */ + PSU_Mask_Write(CRF_APB_ACPU_CTRL_OFFSET, 0x03003F07U, 0x03000100U); +/*##################################################################### */ + + /* + * Register : DBG_FPD_CTRL @ 0XFD1A0068 + + * 6 bit divider + * PSU_CRF_APB_DBG_FPD_CTRL_DIVISOR0 0x2 + + * 000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be tog + * gled after 4 cycles of the old clock and 4 cycles of the new clock. This + * is not usually an issue, but designers must be aware.) + * PSU_CRF_APB_DBG_FPD_CTRL_SRCSEL 0x0 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRF_APB_DBG_FPD_CTRL_CLKACT 0x1 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFD1A0068, 0x01003F07U ,0x01000200U) + */ + PSU_Mask_Write(CRF_APB_DBG_FPD_CTRL_OFFSET, + 0x01003F07U, 0x01000200U); +/*##################################################################### */ + + /* + * Register : DDR_CTRL @ 0XFD1A0080 + + * 6 bit divider + * PSU_CRF_APB_DDR_CTRL_DIVISOR0 0x2 + + * 000 = DPLL; 001 = VPLL; (This signal may only be toggled after 4 cycles + * of the old clock and 4 cycles of the new clock. This is not usually an i + * ssue, but designers must be aware.) + * PSU_CRF_APB_DDR_CTRL_SRCSEL 0x0 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFD1A0080, 0x00003F07U ,0x00000200U) + */ + PSU_Mask_Write(CRF_APB_DDR_CTRL_OFFSET, 0x00003F07U, 0x00000200U); +/*##################################################################### */ + + /* + * Register : GPU_REF_CTRL @ 0XFD1A0084 + + * 6 bit divider + * PSU_CRF_APB_GPU_REF_CTRL_DIVISOR0 0x1 + + * 000 = IOPLL_TO_FPD; 010 = VPLL; 011 = DPLL; (This signal may only be tog + * gled after 4 cycles of the old clock and 4 cycles of the new clock. This + * is not usually an issue, but designers must be aware.) + * PSU_CRF_APB_GPU_REF_CTRL_SRCSEL 0x0 + + * Clock active signal. Switch to 0 to disable the clock, which will stop c + * lock for GPU (and both Pixel Processors). + * PSU_CRF_APB_GPU_REF_CTRL_CLKACT 0x1 + + * Clock active signal for Pixel Processor. Switch to 0 to disable the cloc + * k only to this Pixel Processor + * PSU_CRF_APB_GPU_REF_CTRL_PP0_CLKACT 0x1 + + * Clock active signal for Pixel Processor. Switch to 0 to disable the cloc + * k only to this Pixel Processor + * PSU_CRF_APB_GPU_REF_CTRL_PP1_CLKACT 0x1 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFD1A0084, 0x07003F07U ,0x07000100U) + */ + PSU_Mask_Write(CRF_APB_GPU_REF_CTRL_OFFSET, + 0x07003F07U, 0x07000100U); +/*##################################################################### */ + + /* + * Register : GDMA_REF_CTRL @ 0XFD1A00B8 + + * 6 bit divider + * PSU_CRF_APB_GDMA_REF_CTRL_DIVISOR0 0x2 + + * 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled aft + * er 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRF_APB_GDMA_REF_CTRL_SRCSEL 0x0 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRF_APB_GDMA_REF_CTRL_CLKACT 0x1 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFD1A00B8, 0x01003F07U ,0x01000200U) + */ + PSU_Mask_Write(CRF_APB_GDMA_REF_CTRL_OFFSET, + 0x01003F07U, 0x01000200U); +/*##################################################################### */ + + /* + * Register : DPDMA_REF_CTRL @ 0XFD1A00BC + + * 6 bit divider + * PSU_CRF_APB_DPDMA_REF_CTRL_DIVISOR0 0x2 + + * 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled aft + * er 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRF_APB_DPDMA_REF_CTRL_SRCSEL 0x0 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRF_APB_DPDMA_REF_CTRL_CLKACT 0x1 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFD1A00BC, 0x01003F07U ,0x01000200U) + */ + PSU_Mask_Write(CRF_APB_DPDMA_REF_CTRL_OFFSET, + 0x01003F07U, 0x01000200U); +/*##################################################################### */ + + /* + * Register : TOPSW_MAIN_CTRL @ 0XFD1A00C0 + + * 6 bit divider + * PSU_CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0 0x2 + + * 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled aft + * er 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRF_APB_TOPSW_MAIN_CTRL_SRCSEL 0x3 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRF_APB_TOPSW_MAIN_CTRL_CLKACT 0x1 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFD1A00C0, 0x01003F07U ,0x01000203U) + */ + PSU_Mask_Write(CRF_APB_TOPSW_MAIN_CTRL_OFFSET, + 0x01003F07U, 0x01000203U); +/*##################################################################### */ + + /* + * Register : TOPSW_LSBUS_CTRL @ 0XFD1A00C4 + + * 6 bit divider + * PSU_CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0 0x5 + + * 000 = APLL; 010 = IOPLL_TO_FPD; 011 = DPLL; (This signal may only be tog + * gled after 4 cycles of the old clock and 4 cycles of the new clock. This + * is not usually an issue, but designers must be aware.) + * PSU_CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL 0x2 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRF_APB_TOPSW_LSBUS_CTRL_CLKACT 0x1 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFD1A00C4, 0x01003F07U ,0x01000502U) + */ + PSU_Mask_Write(CRF_APB_TOPSW_LSBUS_CTRL_OFFSET, + 0x01003F07U, 0x01000502U); +/*##################################################################### */ + + /* + * Register : DBG_TSTMP_CTRL @ 0XFD1A00F8 + + * 6 bit divider + * PSU_CRF_APB_DBG_TSTMP_CTRL_DIVISOR0 0x2 + + * 000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be tog + * gled after 4 cycles of the old clock and 4 cycles of the new clock. This + * is not usually an issue, but designers must be aware.) + * PSU_CRF_APB_DBG_TSTMP_CTRL_SRCSEL 0x0 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFD1A00F8, 0x00003F07U ,0x00000200U) + */ + PSU_Mask_Write(CRF_APB_DBG_TSTMP_CTRL_OFFSET, + 0x00003F07U, 0x00000200U); +/*##################################################################### */ + + /* + * Register : IOU_TTC_APB_CLK @ 0XFF180380 + + * 00" = Select the APB switch clock for the APB interface of TTC0'01" = Se + * lect the PLL ref clock for the APB interface of TTC0'10" = Select the R5 + * clock for the APB interface of TTC0 + * PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL 0 + + * 00" = Select the APB switch clock for the APB interface of TTC1'01" = Se + * lect the PLL ref clock for the APB interface of TTC1'10" = Select the R5 + * clock for the APB interface of TTC1 + * PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL 0 + + * 00" = Select the APB switch clock for the APB interface of TTC2'01" = Se + * lect the PLL ref clock for the APB interface of TTC2'10" = Select the R5 + * clock for the APB interface of TTC2 + * PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL 0 + + * 00" = Select the APB switch clock for the APB interface of TTC3'01" = Se + * lect the PLL ref clock for the APB interface of TTC3'10" = Select the R5 + * clock for the APB interface of TTC3 + * PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL 0 + + * TTC APB clock select + * (OFFSET, MASK, VALUE) (0XFF180380, 0x000000FFU ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_IOU_TTC_APB_CLK_OFFSET, + 0x000000FFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : WDT_CLK_SEL @ 0XFD610100 + + * System watchdog timer clock source selection: 0: Internal APB clock 1: E + * xternal (PL clock via EMIO or Pinout clock via MIO) + * PSU_FPD_SLCR_WDT_CLK_SEL_SELECT 0 + + * SWDT clock source select + * (OFFSET, MASK, VALUE) (0XFD610100, 0x00000001U ,0x00000000U) + */ + PSU_Mask_Write(FPD_SLCR_WDT_CLK_SEL_OFFSET, + 0x00000001U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : WDT_CLK_SEL @ 0XFF180300 + + * System watchdog timer clock source selection: 0: internal clock APB cloc + * k 1: external clock from PL via EMIO, or from pinout via MIO + * PSU_IOU_SLCR_WDT_CLK_SEL_SELECT 0 + + * SWDT clock source select + * (OFFSET, MASK, VALUE) (0XFF180300, 0x00000001U ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_WDT_CLK_SEL_OFFSET, + 0x00000001U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : CSUPMU_WDT_CLK_SEL @ 0XFF410050 + + * System watchdog timer clock source selection: 0: internal clock APB cloc + * k 1: external clock pss_ref_clk + * PSU_LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT 0 + + * SWDT clock source select + * (OFFSET, MASK, VALUE) (0XFF410050, 0x00000001U ,0x00000000U) + */ + PSU_Mask_Write(LPD_SLCR_CSUPMU_WDT_CLK_SEL_OFFSET, + 0x00000001U, 0x00000000U); +/*##################################################################### */ + + + return 1; } -unsigned long psu_ddr_init_data() { - // : DDR INITIALIZATION - // : DDR CONTROLLER RESET - /*Register : RST_DDR_SS @ 0XFD1A0108

- - DDR block level reset inside of the DDR Sub System - PSU_CRF_APB_RST_DDR_SS_DDR_RESET 0X1 - - DDR sub system block level reset - (OFFSET, MASK, VALUE) (0XFD1A0108, 0x00000008U ,0x00000008U) - RegMask = (CRF_APB_RST_DDR_SS_DDR_RESET_MASK | 0 ); - - RegVal = ((0x00000001U << CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_RST_DDR_SS_OFFSET ,0x00000008U ,0x00000008U); - /*############################################################################################################################ */ - - /*Register : MSTR @ 0XFD070000

- - Indicates the configuration of the device used in the system. - 00 - x4 device - 01 - x8 device - 10 - x16 device - 11 - x32 - evice - PSU_DDRC_MSTR_DEVICE_CONFIG 0x1 - - Choose which registers are used. - 0 - Original registers - 1 - Shadow registers - PSU_DDRC_MSTR_FREQUENCY_MODE 0x0 - - Only present for multi-rank configurations. Each bit represents one rank. For two-rank configurations, only bits[25:24] are p - esent. - 1 - populated - 0 - unpopulated LSB is the lowest rank number. For 2 ranks following combinations are legal: - 01 - - ne rank - 11 - Two ranks - Others - Reserved. For 4 ranks following combinations are legal: - 0001 - One rank - 0011 - Two ra - ks - 1111 - Four ranks - PSU_DDRC_MSTR_ACTIVE_RANKS 0x1 - - SDRAM burst length used: - 0001 - Burst length of 2 (only supported for mDDR) - 0010 - Burst length of 4 - 0100 - Burst lengt - of 8 - 1000 - Burst length of 16 (only supported for mDDR, LPDDR2, and LPDDR4) All other values are reserved. This controls - he burst size used to access the SDRAM. This must match the burst length mode register setting in the SDRAM. (For BC4/8 on-th - -fly mode of DDR3 and DDR4, set this field to 0x0100) Burst length of 2 is not supported with AXI ports when MEMC_BURST_LENGT - is 8. Burst length of 2 is only supported with MEMC_FREQ_RATIO = 1 - PSU_DDRC_MSTR_BURST_RDWR 0x4 - - Set to 1 when the uMCTL2 and DRAM has to be put in DLL-off mode for low frequency operation. Set to 0 to put uMCTL2 and DRAM - n DLL-on mode for normal frequency operation. If DDR4 CRC/parity retry is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), d - l_off_mode is not supported, and this bit must be set to '0'. - PSU_DDRC_MSTR_DLL_OFF_MODE 0x0 - - Selects proportion of DQ bus width that is used by the SDRAM - 00 - Full DQ bus width to SDRAM - 01 - Half DQ bus width to SD - AM - 10 - Quarter DQ bus width to SDRAM - 11 - Reserved. Note that half bus width mode is only supported when the SDRAM bus w - dth is a multiple of 16, and quarter bus width mode is only supported when the SDRAM bus width is a multiple of 32 and the co - figuration parameter MEMC_QBUS_SUPPORT is set. Bus width refers to DQ bus width (excluding any ECC width). - PSU_DDRC_MSTR_DATA_BUS_WIDTH 0x0 - - 1 indicates put the DRAM in geardown mode (2N) and 0 indicates put the DRAM in normal mode (1N). This register can be changed - only when the Controller is in self-refresh mode. This signal must be set the same value as MR3 bit A3. Note: Geardown mode - s not supported if the configuration parameter MEMC_CMD_RTN2IDLE is set - PSU_DDRC_MSTR_GEARDOWN_MODE 0x0 - - If 1, then uMCTL2 uses 2T timing. Otherwise, uses 1T timing. In 2T timing, all command signals (except chip select) are held - or 2 clocks on the SDRAM bus. Chip select is asserted on the second cycle of the command Note: 2T timing is not supported in - PDDR2/LPDDR3/LPDDR4 mode Note: 2T timing is not supported if the configuration parameter MEMC_CMD_RTN2IDLE is set Note: 2T ti - ing is not supported in DDR4 geardown mode. - PSU_DDRC_MSTR_EN_2T_TIMING_MODE 0x0 - - When set, enable burst-chop in DDR3/DDR4. Burst Chop for Reads is exercised only in HIF configurations (UMCTL2_INCL_ARB not s - t) and if in full bus width mode (MSTR.data_bus_width = 00). Burst Chop for Writes is exercised only if Partial Writes enable - (UMCTL2_PARTIAL_WR=1) and if CRC is disabled (CRCPARCTL1.crc_enable = 0). If DDR4 CRC/parity retry is enabled (CRCPARCTL1.cr - _parity_retry_enable = 1), burst chop is not supported, and this bit must be set to '0' - PSU_DDRC_MSTR_BURSTCHOP 0x0 - - Select LPDDR4 SDRAM - 1 - LPDDR4 SDRAM device in use. - 0 - non-LPDDR4 device in use Present only in designs configured to su - port LPDDR4. - PSU_DDRC_MSTR_LPDDR4 0x0 - - Select DDR4 SDRAM - 1 - DDR4 SDRAM device in use. - 0 - non-DDR4 device in use Present only in designs configured to support - DR4. - PSU_DDRC_MSTR_DDR4 0x1 - - Select LPDDR3 SDRAM - 1 - LPDDR3 SDRAM device in use. - 0 - non-LPDDR3 device in use Present only in designs configured to su - port LPDDR3. - PSU_DDRC_MSTR_LPDDR3 0x0 - - Select LPDDR2 SDRAM - 1 - LPDDR2 SDRAM device in use. - 0 - non-LPDDR2 device in use Present only in designs configured to su - port LPDDR2. - PSU_DDRC_MSTR_LPDDR2 0x0 - - Select DDR3 SDRAM - 1 - DDR3 SDRAM device in use - 0 - non-DDR3 SDRAM device in use Only present in designs that support DDR3 - - PSU_DDRC_MSTR_DDR3 0x0 - - Master Register - (OFFSET, MASK, VALUE) (0XFD070000, 0xE30FBE3DU ,0x41040010U) - RegMask = (DDRC_MSTR_DEVICE_CONFIG_MASK | DDRC_MSTR_FREQUENCY_MODE_MASK | DDRC_MSTR_ACTIVE_RANKS_MASK | DDRC_MSTR_BURST_RDWR_MASK | DDRC_MSTR_DLL_OFF_MODE_MASK | DDRC_MSTR_DATA_BUS_WIDTH_MASK | DDRC_MSTR_GEARDOWN_MODE_MASK | DDRC_MSTR_EN_2T_TIMING_MODE_MASK | DDRC_MSTR_BURSTCHOP_MASK | DDRC_MSTR_LPDDR4_MASK | DDRC_MSTR_DDR4_MASK | DDRC_MSTR_LPDDR3_MASK | DDRC_MSTR_LPDDR2_MASK | DDRC_MSTR_DDR3_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_MSTR_DEVICE_CONFIG_SHIFT - | 0x00000000U << DDRC_MSTR_FREQUENCY_MODE_SHIFT - | 0x00000001U << DDRC_MSTR_ACTIVE_RANKS_SHIFT - | 0x00000004U << DDRC_MSTR_BURST_RDWR_SHIFT - | 0x00000000U << DDRC_MSTR_DLL_OFF_MODE_SHIFT - | 0x00000000U << DDRC_MSTR_DATA_BUS_WIDTH_SHIFT - | 0x00000000U << DDRC_MSTR_GEARDOWN_MODE_SHIFT - | 0x00000000U << DDRC_MSTR_EN_2T_TIMING_MODE_SHIFT - | 0x00000000U << DDRC_MSTR_BURSTCHOP_SHIFT - | 0x00000000U << DDRC_MSTR_LPDDR4_SHIFT - | 0x00000001U << DDRC_MSTR_DDR4_SHIFT - | 0x00000000U << DDRC_MSTR_LPDDR3_SHIFT - | 0x00000000U << DDRC_MSTR_LPDDR2_SHIFT - | 0x00000000U << DDRC_MSTR_DDR3_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_MSTR_OFFSET ,0xE30FBE3DU ,0x41040010U); - /*############################################################################################################################ */ - - /*Register : MRCTRL0 @ 0XFD070010

- - Setting this register bit to 1 triggers a mode register read or write operation. When the MR operation is complete, the uMCTL - automatically clears this bit. The other register fields of this register must be written in a separate APB transaction, bef - re setting this mr_wr bit. It is recommended NOT to set this signal if in Init, Deep power-down or MPSM operating modes. - PSU_DDRC_MRCTRL0_MR_WR 0x0 - - Address of the mode register that is to be written to. - 0000 - MR0 - 0001 - MR1 - 0010 - MR2 - 0011 - MR3 - 0100 - MR4 - 010 - - MR5 - 0110 - MR6 - 0111 - MR7 Don't Care for LPDDR2/LPDDR3/LPDDR4 (see MRCTRL1.mr_data for mode register addressing in LPD - R2/LPDDR3/LPDDR4) This signal is also used for writing to control words of RDIMMs. In that case, it corresponds to the bank a - dress bits sent to the RDIMM In case of DDR4, the bit[3:2] corresponds to the bank group bits. Therefore, the bit[3] as well - s the bit[2:0] must be set to an appropriate value which is considered both the Address Mirroring of UDIMMs/RDIMMs and the Ou - put Inversion of RDIMMs. - PSU_DDRC_MRCTRL0_MR_ADDR 0x0 - - Controls which rank is accessed by MRCTRL0.mr_wr. Normally, it is desired to access all ranks, so all bits should be set to 1 - However, for multi-rank UDIMMs/RDIMMs which implement address mirroring, it may be necessary to access ranks individually. E - amples (assume uMCTL2 is configured for 4 ranks): - 0x1 - select rank 0 only - 0x2 - select rank 1 only - 0x5 - select ranks - and 2 - 0xA - select ranks 1 and 3 - 0xF - select ranks 0, 1, 2 and 3 - PSU_DDRC_MRCTRL0_MR_RANK 0x3 - - Indicates whether Software intervention is allowed via MRCTRL0/MRCTRL1 before automatic SDRAM initialization routine or not. - or DDR4, this bit can be used to initialize the DDR4 RCD (MR7) before automatic SDRAM initialization. For LPDDR4, this bit ca - be used to program additional mode registers before automatic SDRAM initialization if necessary. Note: This must be cleared - o 0 after completing Software operation. Otherwise, SDRAM initialization routine will not re-start. - 0 - Software interventi - n is not allowed - 1 - Software intervention is allowed - PSU_DDRC_MRCTRL0_SW_INIT_INT 0x0 - - Indicates whether the mode register operation is MRS in PDA mode or not - 0 - MRS - 1 - MRS in Per DRAM Addressability mode - PSU_DDRC_MRCTRL0_PDA_EN 0x0 - - Indicates whether the mode register operation is MRS or WR/RD for MPR (only supported for DDR4) - 0 - MRS - 1 - WR/RD for MPR - PSU_DDRC_MRCTRL0_MPR_EN 0x0 - - Indicates whether the mode register operation is read or write. Only used for LPDDR2/LPDDR3/LPDDR4/DDR4. - 0 - Write - 1 - Re - d - PSU_DDRC_MRCTRL0_MR_TYPE 0x0 - - Mode Register Read/Write Control Register 0. Note: Do not enable more than one of the following fields simultaneously: - sw_i - it_int - pda_en - mpr_en - (OFFSET, MASK, VALUE) (0XFD070010, 0x8000F03FU ,0x00000030U) - RegMask = (DDRC_MRCTRL0_MR_WR_MASK | DDRC_MRCTRL0_MR_ADDR_MASK | DDRC_MRCTRL0_MR_RANK_MASK | DDRC_MRCTRL0_SW_INIT_INT_MASK | DDRC_MRCTRL0_PDA_EN_MASK | DDRC_MRCTRL0_MPR_EN_MASK | DDRC_MRCTRL0_MR_TYPE_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_MRCTRL0_MR_WR_SHIFT - | 0x00000000U << DDRC_MRCTRL0_MR_ADDR_SHIFT - | 0x00000003U << DDRC_MRCTRL0_MR_RANK_SHIFT - | 0x00000000U << DDRC_MRCTRL0_SW_INIT_INT_SHIFT - | 0x00000000U << DDRC_MRCTRL0_PDA_EN_SHIFT - | 0x00000000U << DDRC_MRCTRL0_MPR_EN_SHIFT - | 0x00000000U << DDRC_MRCTRL0_MR_TYPE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_MRCTRL0_OFFSET ,0x8000F03FU ,0x00000030U); - /*############################################################################################################################ */ - - /*Register : DERATEEN @ 0XFD070020

- - Derate value of tRC for LPDDR4 - 0 - Derating uses +1. - 1 - Derating uses +2. - 2 - Derating uses +3. - 3 - Derating uses +4 - Present only in designs configured to support LPDDR4. The required number of cycles for derating can be determined by dividi - g 3.75ns by the core_ddrc_core_clk period, and rounding up the next integer. - PSU_DDRC_DERATEEN_RC_DERATE_VALUE 0x3 - - Derate byte Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4 Indicates which byte of the MRR data is used f - r derating. The maximum valid value depends on MEMC_DRAM_TOTAL_DATA_WIDTH. - PSU_DDRC_DERATEEN_DERATE_BYTE 0x0 - - Derate value - 0 - Derating uses +1. - 1 - Derating uses +2. Present only in designs configured to support LPDDR2/LPDDR3/LPDD - 4 Set to 0 for all LPDDR2 speed grades as derating value of +1.875 ns is less than a core_ddrc_core_clk period. Can be 0 or 1 - for LPDDR3/LPDDR4, depending if +1.875 ns is less than a core_ddrc_core_clk period or not. - PSU_DDRC_DERATEEN_DERATE_VALUE 0x0 - - Enables derating - 0 - Timing parameter derating is disabled - 1 - Timing parameter derating is enabled using MR4 read value. - Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4 This field must be set to '0' for non-LPDDR2/LPDDR3/LPDDR4 - mode. - PSU_DDRC_DERATEEN_DERATE_ENABLE 0x0 - - Temperature Derate Enable Register - (OFFSET, MASK, VALUE) (0XFD070020, 0x000003F3U ,0x00000300U) - RegMask = (DDRC_DERATEEN_RC_DERATE_VALUE_MASK | DDRC_DERATEEN_DERATE_BYTE_MASK | DDRC_DERATEEN_DERATE_VALUE_MASK | DDRC_DERATEEN_DERATE_ENABLE_MASK | 0 ); - - RegVal = ((0x00000003U << DDRC_DERATEEN_RC_DERATE_VALUE_SHIFT - | 0x00000000U << DDRC_DERATEEN_DERATE_BYTE_SHIFT - | 0x00000000U << DDRC_DERATEEN_DERATE_VALUE_SHIFT - | 0x00000000U << DDRC_DERATEEN_DERATE_ENABLE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DERATEEN_OFFSET ,0x000003F3U ,0x00000300U); - /*############################################################################################################################ */ - - /*Register : DERATEINT @ 0XFD070024

- - Interval between two MR4 reads, used to derate the timing parameters. Present only in designs configured to support LPDDR2/LP - DR3/LPDDR4. This register must not be set to zero - PSU_DDRC_DERATEINT_MR4_READ_INTERVAL 0x800000 - - Temperature Derate Interval Register - (OFFSET, MASK, VALUE) (0XFD070024, 0xFFFFFFFFU ,0x00800000U) - RegMask = (DDRC_DERATEINT_MR4_READ_INTERVAL_MASK | 0 ); - - RegVal = ((0x00800000U << DDRC_DERATEINT_MR4_READ_INTERVAL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DERATEINT_OFFSET ,0xFFFFFFFFU ,0x00800000U); - /*############################################################################################################################ */ - - /*Register : PWRCTL @ 0XFD070030

- - Self refresh state is an intermediate state to enter to Self refresh power down state or exit Self refresh power down state f - r LPDDR4. This register controls transition from the Self refresh state. - 1 - Prohibit transition from Self refresh state - - - Allow transition from Self refresh state - PSU_DDRC_PWRCTL_STAY_IN_SELFREF 0x0 - - A value of 1 to this register causes system to move to Self Refresh state immediately, as long as it is not in INIT or DPD/MP - M operating_mode. This is referred to as Software Entry/Exit to Self Refresh. - 1 - Software Entry to Self Refresh - 0 - Soft - are Exit from Self Refresh - PSU_DDRC_PWRCTL_SELFREF_SW 0x0 - - When this is 1, the uMCTL2 puts the SDRAM into maximum power saving mode when the transaction store is empty. This register m - st be reset to '0' to bring uMCTL2 out of maximum power saving mode. Present only in designs configured to support DDR4. For - on-DDR4, this register should not be set to 1. Note that MPSM is not supported when using a DWC DDR PHY, if the PHY parameter - DWC_AC_CS_USE is disabled, as the MPSM exit sequence requires the chip-select signal to toggle. FOR PERFORMANCE ONLY. - PSU_DDRC_PWRCTL_MPSM_EN 0x0 - - Enable the assertion of dfi_dram_clk_disable whenever a clock is not required by the SDRAM. If set to 0, dfi_dram_clk_disable - is never asserted. Assertion of dfi_dram_clk_disable is as follows: In DDR2/DDR3, can only be asserted in Self Refresh. In DD - 4, can be asserted in following: - in Self Refresh. - in Maximum Power Saving Mode In mDDR/LPDDR2/LPDDR3, can be asserted in - ollowing: - in Self Refresh - in Power Down - in Deep Power Down - during Normal operation (Clock Stop) In LPDDR4, can be ass - rted in following: - in Self Refresh Power Down - in Power Down - during Normal operation (Clock Stop) - PSU_DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE 0x0 - - When this is 1, uMCTL2 puts the SDRAM into deep power-down mode when the transaction store is empty. This register must be re - et to '0' to bring uMCTL2 out of deep power-down mode. Controller performs automatic SDRAM initialization on deep power-down - xit. Present only in designs configured to support mDDR or LPDDR2 or LPDDR3. For non-mDDR/non-LPDDR2/non-LPDDR3, this registe - should not be set to 1. FOR PERFORMANCE ONLY. - PSU_DDRC_PWRCTL_DEEPPOWERDOWN_EN 0x0 - - If true then the uMCTL2 goes into power-down after a programmable number of cycles 'maximum idle clocks before power down' (P - RTMG.powerdown_to_x32). This register bit may be re-programmed during the course of normal operation. - PSU_DDRC_PWRCTL_POWERDOWN_EN 0x0 - - If true then the uMCTL2 puts the SDRAM into Self Refresh after a programmable number of cycles 'maximum idle clocks before Se - f Refresh (PWRTMG.selfref_to_x32)'. This register bit may be re-programmed during the course of normal operation. - PSU_DDRC_PWRCTL_SELFREF_EN 0x0 - - Low Power Control Register - (OFFSET, MASK, VALUE) (0XFD070030, 0x0000007FU ,0x00000000U) - RegMask = (DDRC_PWRCTL_STAY_IN_SELFREF_MASK | DDRC_PWRCTL_SELFREF_SW_MASK | DDRC_PWRCTL_MPSM_EN_MASK | DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_MASK | DDRC_PWRCTL_DEEPPOWERDOWN_EN_MASK | DDRC_PWRCTL_POWERDOWN_EN_MASK | DDRC_PWRCTL_SELFREF_EN_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_PWRCTL_STAY_IN_SELFREF_SHIFT - | 0x00000000U << DDRC_PWRCTL_SELFREF_SW_SHIFT - | 0x00000000U << DDRC_PWRCTL_MPSM_EN_SHIFT - | 0x00000000U << DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_SHIFT - | 0x00000000U << DDRC_PWRCTL_DEEPPOWERDOWN_EN_SHIFT - | 0x00000000U << DDRC_PWRCTL_POWERDOWN_EN_SHIFT - | 0x00000000U << DDRC_PWRCTL_SELFREF_EN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PWRCTL_OFFSET ,0x0000007FU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : PWRTMG @ 0XFD070034

- - After this many clocks of NOP or deselect the uMCTL2 automatically puts the SDRAM into Self Refresh. This must be enabled in - he PWRCTL.selfref_en. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY. - PSU_DDRC_PWRTMG_SELFREF_TO_X32 0x40 - - Minimum deep power-down time. For mDDR, value from the JEDEC specification is 0 as mDDR exits from deep power-down mode immed - ately after PWRCTL.deeppowerdown_en is de-asserted. For LPDDR2/LPDDR3, value from the JEDEC specification is 500us. Unit: Mul - iples of 4096 clocks. Present only in designs configured to support mDDR, LPDDR2 or LPDDR3. FOR PERFORMANCE ONLY. - PSU_DDRC_PWRTMG_T_DPD_X4096 0x84 - - After this many clocks of NOP or deselect the uMCTL2 automatically puts the SDRAM into power-down. This must be enabled in th - PWRCTL.powerdown_en. Unit: Multiples of 32 clocks FOR PERFORMANCE ONLY. - PSU_DDRC_PWRTMG_POWERDOWN_TO_X32 0x10 - - Low Power Timing Register - (OFFSET, MASK, VALUE) (0XFD070034, 0x00FFFF1FU ,0x00408410U) - RegMask = (DDRC_PWRTMG_SELFREF_TO_X32_MASK | DDRC_PWRTMG_T_DPD_X4096_MASK | DDRC_PWRTMG_POWERDOWN_TO_X32_MASK | 0 ); - - RegVal = ((0x00000040U << DDRC_PWRTMG_SELFREF_TO_X32_SHIFT - | 0x00000084U << DDRC_PWRTMG_T_DPD_X4096_SHIFT - | 0x00000010U << DDRC_PWRTMG_POWERDOWN_TO_X32_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PWRTMG_OFFSET ,0x00FFFF1FU ,0x00408410U); - /*############################################################################################################################ */ - - /*Register : RFSHCTL0 @ 0XFD070050

- - Threshold value in number of clock cycles before the critical refresh or page timer expires. A critical refresh is to be issu - d before this threshold is reached. It is recommended that this not be changed from the default value, currently shown as 0x2 - It must always be less than internally used t_rfc_nom_x32. Note that, in LPDDR2/LPDDR3/LPDDR4, internally used t_rfc_nom_x32 - may be equal to RFSHTMG.t_rfc_nom_x32>>2 if derating is enabled (DERATEEN.derate_enable=1). Otherwise, internally used t_rfc_ - om_x32 will be equal to RFSHTMG.t_rfc_nom_x32. Unit: Multiples of 32 clocks. - PSU_DDRC_RFSHCTL0_REFRESH_MARGIN 0x2 - - If the refresh timer (tRFCnom, also known as tREFI) has expired at least once, but it has not expired (RFSHCTL0.refresh_burst - 1) times yet, then a speculative refresh may be performed. A speculative refresh is a refresh performed at a time when refres - would be useful, but before it is absolutely required. When the SDRAM bus is idle for a period of time determined by this RF - HCTL0.refresh_to_x32 and the refresh timer has expired at least once since the last refresh, then a speculative refresh is pe - formed. Speculative refreshes continues successively until there are no refreshes pending or until new reads or writes are is - ued to the uMCTL2. FOR PERFORMANCE ONLY. - PSU_DDRC_RFSHCTL0_REFRESH_TO_X32 0x10 - - The programmed value + 1 is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the re - reshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of re - reshes. Therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for - RFSHCTL.refresh_burst slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshe - . - 0 - single refresh - 1 - burst-of-2 refresh - 7 - burst-of-8 refresh For information on burst refresh feature refer to se - tion 3.9 of DDR2 JEDEC specification - JESD79-2F.pdf. For DDR2/3, the refresh is always per-rank and not per-bank. The rank r - fresh can be accumulated over 8*tREFI cycles using the burst refresh feature. In DDR4 mode, according to Fine Granularity fea - ure, 8 refreshes can be postponed in 1X mode, 16 refreshes in 2X mode and 32 refreshes in 4X mode. If using PHY-initiated upd - tes, care must be taken in the setting of RFSHCTL0.refresh_burst, to ensure that tRFCmax is not violated due to a PHY-initiat - d update occurring shortly before a refresh burst was due. In this situation, the refresh burst will be delayed until the PHY - initiated update is complete. - PSU_DDRC_RFSHCTL0_REFRESH_BURST 0x0 - - - 1 - Per bank refresh; - 0 - All bank refresh. Per bank refresh allows traffic to flow to other banks. Per bank refresh is n - t supported by all LPDDR2 devices but should be supported by all LPDDR3/LPDDR4 devices. Present only in designs configured to - support LPDDR2/LPDDR3/LPDDR4 - PSU_DDRC_RFSHCTL0_PER_BANK_REFRESH 0x0 - - Refresh Control Register 0 - (OFFSET, MASK, VALUE) (0XFD070050, 0x00F1F1F4U ,0x00210000U) - RegMask = (DDRC_RFSHCTL0_REFRESH_MARGIN_MASK | DDRC_RFSHCTL0_REFRESH_TO_X32_MASK | DDRC_RFSHCTL0_REFRESH_BURST_MASK | DDRC_RFSHCTL0_PER_BANK_REFRESH_MASK | 0 ); - - RegVal = ((0x00000002U << DDRC_RFSHCTL0_REFRESH_MARGIN_SHIFT - | 0x00000010U << DDRC_RFSHCTL0_REFRESH_TO_X32_SHIFT - | 0x00000000U << DDRC_RFSHCTL0_REFRESH_BURST_SHIFT - | 0x00000000U << DDRC_RFSHCTL0_PER_BANK_REFRESH_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_RFSHCTL0_OFFSET ,0x00F1F1F4U ,0x00210000U); - /*############################################################################################################################ */ - - /*Register : RFSHCTL3 @ 0XFD070060

- - Fine Granularity Refresh Mode - 000 - Fixed 1x (Normal mode) - 001 - Fixed 2x - 010 - Fixed 4x - 101 - Enable on the fly 2x ( - ot supported) - 110 - Enable on the fly 4x (not supported) - Everything else - reserved Note: The on-the-fly modes is not sup - orted in this version of the uMCTL2. Note: This must be set up while the Controller is in reset or while the Controller is in - self-refresh mode. Changing this during normal operation is not allowed. Making this a dynamic register will be supported in - uture version of the uMCTL2. - PSU_DDRC_RFSHCTL3_REFRESH_MODE 0x0 - - Toggle this signal (either from 0 to 1 or from 1 to 0) to indicate that the refresh register(s) have been updated. The value - s automatically updated when exiting reset, so it does not need to be toggled initially. - PSU_DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL 0x0 - - When '1', disable auto-refresh generated by the uMCTL2. When auto-refresh is disabled, the SoC core must generate refreshes u - ing the registers reg_ddrc_rank0_refresh, reg_ddrc_rank1_refresh, reg_ddrc_rank2_refresh and reg_ddrc_rank3_refresh. When dis - auto_refresh transitions from 0 to 1, any pending refreshes are immediately scheduled by the uMCTL2. If DDR4 CRC/parity retry - is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), disable auto-refresh is not supported, and this bit must be set to '0'. - his register field is changeable on the fly. - PSU_DDRC_RFSHCTL3_DIS_AUTO_REFRESH 0x1 - - Refresh Control Register 3 - (OFFSET, MASK, VALUE) (0XFD070060, 0x00000073U ,0x00000001U) - RegMask = (DDRC_RFSHCTL3_REFRESH_MODE_MASK | DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_MASK | DDRC_RFSHCTL3_DIS_AUTO_REFRESH_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_RFSHCTL3_REFRESH_MODE_SHIFT - | 0x00000000U << DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_SHIFT - | 0x00000001U << DDRC_RFSHCTL3_DIS_AUTO_REFRESH_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_RFSHCTL3_OFFSET ,0x00000073U ,0x00000001U); - /*############################################################################################################################ */ - - /*Register : RFSHTMG @ 0XFD070064

- - tREFI: Average time interval between refreshes per rank (Specification: 7.8us for DDR2, DDR3 and DDR4. See JEDEC specificatio - for mDDR, LPDDR2, LPDDR3 and LPDDR4). For LPDDR2/LPDDR3/LPDDR4: - if using all-bank refreshes (RFSHCTL0.per_bank_refresh = 0 - , this register should be set to tREFIab - if using per-bank refreshes (RFSHCTL0.per_bank_refresh = 1), this register should - e set to tREFIpb For configurations with MEMC_FREQ_RATIO=2, program this to (tREFI/2), no rounding up. In DDR4 mode, tREFI va - ue is different depending on the refresh mode. The user should program the appropriate value from the spec based on the value - programmed in the refresh mode register. Note that RFSHTMG.t_rfc_nom_x32 * 32 must be greater than RFSHTMG.t_rfc_min, and RFS - TMG.t_rfc_nom_x32 must be greater than 0x1. Unit: Multiples of 32 clocks. - PSU_DDRC_RFSHTMG_T_RFC_NOM_X32 0x82 - - Used only when LPDDR3 memory type is connected. Should only be changed when uMCTL2 is in reset. Specifies whether to use the - REFBW parameter (required by some LPDDR3 devices which comply with earlier versions of the LPDDR3 JEDEC specification) or not - - 0 - tREFBW parameter not used - 1 - tREFBW parameter used - PSU_DDRC_RFSHTMG_LPDDR3_TREFBW_EN 0x1 - - tRFC (min): Minimum time from refresh to refresh or activate. For MEMC_FREQ_RATIO=1 configurations, t_rfc_min should be set t - RoundUp(tRFCmin/tCK). For MEMC_FREQ_RATIO=2 configurations, t_rfc_min should be set to RoundUp(RoundUp(tRFCmin/tCK)/2). In L - DDR2/LPDDR3/LPDDR4 mode: - if using all-bank refreshes, the tRFCmin value in the above equations is equal to tRFCab - if usin - per-bank refreshes, the tRFCmin value in the above equations is equal to tRFCpb In DDR4 mode, the tRFCmin value in the above - equations is different depending on the refresh mode (fixed 1X,2X,4X) and the device density. The user should program the app - opriate value from the spec based on the 'refresh_mode' and the device density that is used. Unit: Clocks. - PSU_DDRC_RFSHTMG_T_RFC_MIN 0x8b - - Refresh Timing Register - (OFFSET, MASK, VALUE) (0XFD070064, 0x0FFF83FFU ,0x0082808BU) - RegMask = (DDRC_RFSHTMG_T_RFC_NOM_X32_MASK | DDRC_RFSHTMG_LPDDR3_TREFBW_EN_MASK | DDRC_RFSHTMG_T_RFC_MIN_MASK | 0 ); - - RegVal = ((0x00000082U << DDRC_RFSHTMG_T_RFC_NOM_X32_SHIFT - | 0x00000001U << DDRC_RFSHTMG_LPDDR3_TREFBW_EN_SHIFT - | 0x0000008BU << DDRC_RFSHTMG_T_RFC_MIN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_RFSHTMG_OFFSET ,0x0FFF83FFU ,0x0082808BU); - /*############################################################################################################################ */ - - /*Register : ECCCFG0 @ 0XFD070070

- - Disable ECC scrubs. Valid only when ECCCFG0.ecc_mode = 3'b100 and MEMC_USE_RMW is defined - PSU_DDRC_ECCCFG0_DIS_SCRUB 0x1 - - ECC mode indicator - 000 - ECC disabled - 100 - ECC enabled - SEC/DED over 1 beat - all other settings are reserved for futur - use - PSU_DDRC_ECCCFG0_ECC_MODE 0x0 - - ECC Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD070070, 0x00000017U ,0x00000010U) - RegMask = (DDRC_ECCCFG0_DIS_SCRUB_MASK | DDRC_ECCCFG0_ECC_MODE_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_ECCCFG0_DIS_SCRUB_SHIFT - | 0x00000000U << DDRC_ECCCFG0_ECC_MODE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_ECCCFG0_OFFSET ,0x00000017U ,0x00000010U); - /*############################################################################################################################ */ - - /*Register : ECCCFG1 @ 0XFD070074

- - Selects whether to poison 1 or 2 bits - if 0 -> 2-bit (uncorrectable) data poisoning, if 1 -> 1-bit (correctable) data poison - ng, if ECCCFG1.data_poison_en=1 - PSU_DDRC_ECCCFG1_DATA_POISON_BIT 0x0 - - Enable ECC data poisoning - introduces ECC errors on writes to address specified by the ECCPOISONADDR0/1 registers - PSU_DDRC_ECCCFG1_DATA_POISON_EN 0x0 - - ECC Configuration Register 1 - (OFFSET, MASK, VALUE) (0XFD070074, 0x00000003U ,0x00000000U) - RegMask = (DDRC_ECCCFG1_DATA_POISON_BIT_MASK | DDRC_ECCCFG1_DATA_POISON_EN_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_ECCCFG1_DATA_POISON_BIT_SHIFT - | 0x00000000U << DDRC_ECCCFG1_DATA_POISON_EN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_ECCCFG1_OFFSET ,0x00000003U ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : CRCPARCTL1 @ 0XFD0700C4

- - The maximum number of DFI PHY clock cycles allowed from the assertion of the dfi_rddata_en signal to the assertion of each of - the corresponding bits of the dfi_rddata_valid signal. This corresponds to the DFI timing parameter tphy_rdlat. Refer to PHY - pecification for correct value. This value it only used for detecting read data timeout when DDR4 retry is enabled by CRCPARC - L1.crc_parity_retry_enable=1. Maximum supported value: - 1:1 Frequency mode : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_ - dlat < 'd114 - 1:2 Frequency mode ANDAND DFITMG0.dfi_rddata_use_sdr == 1 : CRCPARCTL1.dfi_t_phy_rdlat < 64 - 1:2 Frequency mo - e ANDAND DFITMG0.dfi_rddata_use_sdr == 0 : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_rdlat < 'd114 Unit: DFI Clocks - PSU_DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT 0x10 - - After a Parity or CRC error is flagged on dfi_alert_n signal, the software has an option to read the mode registers in the DR - M before the hardware begins the retry process - 1: Wait for software to read/write the mode registers before hardware begins - the retry. After software is done with its operations, it will clear the alert interrupt register bit - 0: Hardware can begin - the retry right away after the dfi_alert_n pulse goes away. The value on this register is valid only when retry is enabled (P - RCTRL.crc_parity_retry_enable = 1) If this register is set to 1 and if the software doesn't clear the interrupt register afte - handling the parity/CRC error, then the hardware will not begin the retry process and the system will hang. In the case of P - rity/CRC error, there are two possibilities when the software doesn't reset MR5[4] to 0. - (i) If 'Persistent parity' mode re - ister bit is NOT set: the commands sent during retry and normal operation are executed without parity checking. The value in - he Parity error log register MPR Page 1 is valid. - (ii) If 'Persistent parity' mode register bit is SET: Parity checking is - one for commands sent during retry and normal operation. If multiple errors occur before MR5[4] is cleared, the error log in - PR Page 1 should be treated as 'Don't care'. - PSU_DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW 0x1 - - - 1: Enable command retry mechanism in case of C/A Parity or CRC error - 0: Disable command retry mechanism when C/A Parity o - CRC features are enabled. Note that retry functionality is not supported if burst chop is enabled (MSTR.burstchop = 1) and/o - disable auto-refresh is enabled (RFSHCTL3.dis_auto_refresh = 1) - PSU_DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE 0x0 - - CRC Calculation setting register - 1: CRC includes DM signal - 0: CRC not includes DM signal Present only in designs configur - d to support DDR4. - PSU_DDRC_CRCPARCTL1_CRC_INC_DM 0x0 - - CRC enable Register - 1: Enable generation of CRC - 0: Disable generation of CRC The setting of this register should match th - CRC mode register setting in the DRAM. - PSU_DDRC_CRCPARCTL1_CRC_ENABLE 0x0 - - C/A Parity enable register - 1: Enable generation of C/A parity and detection of C/A parity error - 0: Disable generation of - /A parity and disable detection of C/A parity error If RCD's parity error detection or SDRAM's parity detection is enabled, t - is register should be 1. - PSU_DDRC_CRCPARCTL1_PARITY_ENABLE 0x0 - - CRC Parity Control Register1 - (OFFSET, MASK, VALUE) (0XFD0700C4, 0x3F000391U ,0x10000200U) - RegMask = (DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_MASK | DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_MASK | DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_MASK | DDRC_CRCPARCTL1_CRC_INC_DM_MASK | DDRC_CRCPARCTL1_CRC_ENABLE_MASK | DDRC_CRCPARCTL1_PARITY_ENABLE_MASK | 0 ); - - RegVal = ((0x00000010U << DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_SHIFT - | 0x00000001U << DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_SHIFT - | 0x00000000U << DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_SHIFT - | 0x00000000U << DDRC_CRCPARCTL1_CRC_INC_DM_SHIFT - | 0x00000000U << DDRC_CRCPARCTL1_CRC_ENABLE_SHIFT - | 0x00000000U << DDRC_CRCPARCTL1_PARITY_ENABLE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_CRCPARCTL1_OFFSET ,0x3F000391U ,0x10000200U); - /*############################################################################################################################ */ - - /*Register : CRCPARCTL2 @ 0XFD0700C8

- - Value from the DRAM spec indicating the maximum width of the dfi_alert_n pulse when a parity error occurs. Recommended values - - tPAR_ALERT_PW.MAX For configurations with MEMC_FREQ_RATIO=2, program this to tPAR_ALERT_PW.MAX/2 and round up to next inte - er value. Values of 0, 1 and 2 are illegal. This value must be greater than CRCPARCTL2.t_crc_alert_pw_max. - PSU_DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX 0x40 - - Value from the DRAM spec indicating the maximum width of the dfi_alert_n pulse when a CRC error occurs. Recommended values: - - tCRC_ALERT_PW.MAX For configurations with MEMC_FREQ_RATIO=2, program this to tCRC_ALERT_PW.MAX/2 and round up to next integer - value. Values of 0, 1 and 2 are illegal. This value must be less than CRCPARCTL2.t_par_alert_pw_max. - PSU_DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX 0x5 - - Indicates the maximum duration in number of DRAM clock cycles for which a command should be held in the Command Retry FIFO be - ore it is popped out. Every location in the Command Retry FIFO has an associated down counting timer that will use this regis - er as the start value. The down counting starts when a command is loaded into the FIFO. The timer counts down every 4 DRAM cy - les. When the counter reaches zero, the entry is popped from the FIFO. All the counters are frozen, if a C/A Parity or CRC er - or occurs before the counter reaches zero. The counter is reset to 0, after all the commands in the FIFO are retried. Recomme - ded(minimum) values: - Only C/A Parity is enabled. RoundUp((PHY Command Latency(DRAM CLK) + CAL + RDIMM delay + tPAR_ALERT_ON - max + tPAR_UNKNOWN + PHY Alert Latency(DRAM CLK) + board delay) / 4) + 2 - Both C/A Parity and CRC is enabled/ Only CRC is en - bled. RoundUp((PHY Command Latency(DRAM CLK) + CAL + RDIMM delay + WL + 5(BL10)+ tCRC_ALERT.max + PHY Alert Latency(DRAM CLK) - + board delay) / 4) + 2 Note 1: All value (e.g. tPAR_ALERT_ON) should be in terms of DRAM Clock and round up Note 2: Board de - ay(Command/Alert_n) should be considered. Note 3: Use the worst case(longer) value for PHY Latencies/Board delay Note 4: The - ecommended values are minimum value to be set. For mode detail, See 'Calculation of FIFO Depth' section. Max value can be set - to this register is defined below: - MEMC_BURST_LENGTH == 16 Full bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH- - Full bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Half bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_D - PTH-4 Half bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-6 Quarter bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CM - _FIFO_DEPTH-8 Quarter bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-12 - MEMC_BURST_LENGTH != 16 Full bus Mode (C - C=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-1 Full bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mo - e (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Quarte - bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-4 Quarter bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEP - H-6 Values of 0, 1 and 2 are illegal. - PSU_DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4 0x1f - - CRC Parity Control Register2 - (OFFSET, MASK, VALUE) (0XFD0700C8, 0x01FF1F3FU ,0x0040051FU) - RegMask = (DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_MASK | DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_MASK | DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_MASK | 0 ); - - RegVal = ((0x00000040U << DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_SHIFT - | 0x00000005U << DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_SHIFT - | 0x0000001FU << DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_CRCPARCTL2_OFFSET ,0x01FF1F3FU ,0x0040051FU); - /*############################################################################################################################ */ - - /*Register : INIT0 @ 0XFD0700D0

- - If lower bit is enabled the SDRAM initialization routine is skipped. The upper bit decides what state the controller starts u - in when reset is removed - 00 - SDRAM Intialization routine is run after power-up - 01 - SDRAM Intialization routine is skip - ed after power-up. Controller starts up in Normal Mode - 11 - SDRAM Intialization routine is skipped after power-up. Controll - r starts up in Self-refresh Mode - 10 - SDRAM Intialization routine is run after power-up. Note: The only 2'b00 is supported - or LPDDR4 in this version of the uMCTL2. - PSU_DDRC_INIT0_SKIP_DRAM_INIT 0x0 - - Cycles to wait after driving CKE high to start the SDRAM initialization sequence. Unit: 1024 clocks. DDR2 typically requires - 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2/LPDDR3 typically requires this to be pr - grammed for a delay of 200 us. LPDDR4 typically requires this to be programmed for a delay of 2 us. For configurations with M - MC_FREQ_RATIO=2, program this to JEDEC spec value divided by 2, and round it up to next integer value. - PSU_DDRC_INIT0_POST_CKE_X1024 0x2 - - Cycles to wait after reset before driving CKE high to start the SDRAM initialization sequence. Unit: 1024 clock cycles. DDR2 - pecifications typically require this to be programmed for a delay of >= 200 us. LPDDR2/LPDDR3: tINIT1 of 100 ns (min) LPDDR4: - tINIT3 of 2 ms (min) For configurations with MEMC_FREQ_RATIO=2, program this to JEDEC spec value divided by 2, and round it u - to next integer value. - PSU_DDRC_INIT0_PRE_CKE_X1024 0x106 - - SDRAM Initialization Register 0 - (OFFSET, MASK, VALUE) (0XFD0700D0, 0xC3FF0FFFU ,0x00020106U) - RegMask = (DDRC_INIT0_SKIP_DRAM_INIT_MASK | DDRC_INIT0_POST_CKE_X1024_MASK | DDRC_INIT0_PRE_CKE_X1024_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_INIT0_SKIP_DRAM_INIT_SHIFT - | 0x00000002U << DDRC_INIT0_POST_CKE_X1024_SHIFT - | 0x00000106U << DDRC_INIT0_PRE_CKE_X1024_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_INIT0_OFFSET ,0xC3FF0FFFU ,0x00020106U); - /*############################################################################################################################ */ - - /*Register : INIT1 @ 0XFD0700D4

- - Number of cycles to assert SDRAM reset signal during init sequence. This is only present for designs supporting DDR3, DDR4 or - LPDDR4 devices. For use with a DDR PHY, this should be set to a minimum of 1 - PSU_DDRC_INIT1_DRAM_RSTN_X1024 0x2 - - Cycles to wait after completing the SDRAM initialization sequence before starting the dynamic scheduler. Unit: Counts of a gl - bal timer that pulses every 32 clock cycles. There is no known specific requirement for this; it may be set to zero. - PSU_DDRC_INIT1_FINAL_WAIT_X32 0x0 - - Wait period before driving the OCD complete command to SDRAM. Unit: Counts of a global timer that pulses every 32 clock cycle - . There is no known specific requirement for this; it may be set to zero. - PSU_DDRC_INIT1_PRE_OCD_X32 0x0 - - SDRAM Initialization Register 1 - (OFFSET, MASK, VALUE) (0XFD0700D4, 0x01FF7F0FU ,0x00020000U) - RegMask = (DDRC_INIT1_DRAM_RSTN_X1024_MASK | DDRC_INIT1_FINAL_WAIT_X32_MASK | DDRC_INIT1_PRE_OCD_X32_MASK | 0 ); - - RegVal = ((0x00000002U << DDRC_INIT1_DRAM_RSTN_X1024_SHIFT - | 0x00000000U << DDRC_INIT1_FINAL_WAIT_X32_SHIFT - | 0x00000000U << DDRC_INIT1_PRE_OCD_X32_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_INIT1_OFFSET ,0x01FF7F0FU ,0x00020000U); - /*############################################################################################################################ */ - - /*Register : INIT2 @ 0XFD0700D8

- - Idle time after the reset command, tINIT4. Present only in designs configured to support LPDDR2. Unit: 32 clock cycles. - PSU_DDRC_INIT2_IDLE_AFTER_RESET_X32 0x23 - - Time to wait after the first CKE high, tINIT2. Present only in designs configured to support LPDDR2/LPDDR3. Unit: 1 clock cyc - e. LPDDR2/LPDDR3 typically requires 5 x tCK delay. - PSU_DDRC_INIT2_MIN_STABLE_CLOCK_X1 0x5 - - SDRAM Initialization Register 2 - (OFFSET, MASK, VALUE) (0XFD0700D8, 0x0000FF0FU ,0x00002305U) - RegMask = (DDRC_INIT2_IDLE_AFTER_RESET_X32_MASK | DDRC_INIT2_MIN_STABLE_CLOCK_X1_MASK | 0 ); - - RegVal = ((0x00000023U << DDRC_INIT2_IDLE_AFTER_RESET_X32_SHIFT - | 0x00000005U << DDRC_INIT2_MIN_STABLE_CLOCK_X1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_INIT2_OFFSET ,0x0000FF0FU ,0x00002305U); - /*############################################################################################################################ */ - - /*Register : INIT3 @ 0XFD0700DC

- - DDR2: Value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The uMCTL2 sets this bit appropriately - DDR3/DDR4: Value loaded into MR0 register. mDDR: Value to write to MR register. LPDDR2/LPDDR3/LPDDR4 - Value to write to MR1 - register - PSU_DDRC_INIT3_MR 0x930 - - DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setting in this register is ignored. The uMCTL2 sets those - bits appropriately. DDR3/DDR4: Value to write to MR1 register Set bit 7 to 0. If PHY-evaluation mode training is enabled, thi - bit is set appropriately by the uMCTL2 during write leveling. mDDR: Value to write to EMR register. LPDDR2/LPDDR3/LPDDR4 - V - lue to write to MR2 register - PSU_DDRC_INIT3_EMR 0x301 - - SDRAM Initialization Register 3 - (OFFSET, MASK, VALUE) (0XFD0700DC, 0xFFFFFFFFU ,0x09300301U) - RegMask = (DDRC_INIT3_MR_MASK | DDRC_INIT3_EMR_MASK | 0 ); - - RegVal = ((0x00000930U << DDRC_INIT3_MR_SHIFT - | 0x00000301U << DDRC_INIT3_EMR_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_INIT3_OFFSET ,0xFFFFFFFFU ,0x09300301U); - /*############################################################################################################################ */ - - /*Register : INIT4 @ 0XFD0700E0

- - DDR2: Value to write to EMR2 register. DDR3/DDR4: Value to write to MR2 register LPDDR2/LPDDR3/LPDDR4: Value to write to MR3 - egister mDDR: Unused - PSU_DDRC_INIT4_EMR2 0x20 - - DDR2: Value to write to EMR3 register. DDR3/DDR4: Value to write to MR3 register mDDR/LPDDR2/LPDDR3: Unused LPDDR4: Value to - rite to MR13 register - PSU_DDRC_INIT4_EMR3 0x200 - - SDRAM Initialization Register 4 - (OFFSET, MASK, VALUE) (0XFD0700E0, 0xFFFFFFFFU ,0x00200200U) - RegMask = (DDRC_INIT4_EMR2_MASK | DDRC_INIT4_EMR3_MASK | 0 ); - - RegVal = ((0x00000020U << DDRC_INIT4_EMR2_SHIFT - | 0x00000200U << DDRC_INIT4_EMR3_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_INIT4_OFFSET ,0xFFFFFFFFU ,0x00200200U); - /*############################################################################################################################ */ - - /*Register : INIT5 @ 0XFD0700E4

- - ZQ initial calibration, tZQINIT. Present only in designs configured to support DDR3 or DDR4 or LPDDR2/LPDDR3. Unit: 32 clock - ycles. DDR3 typically requires 512 clocks. DDR4 requires 1024 clocks. LPDDR2/LPDDR3 requires 1 us. - PSU_DDRC_INIT5_DEV_ZQINIT_X32 0x21 - - Maximum duration of the auto initialization, tINIT5. Present only in designs configured to support LPDDR2/LPDDR3. LPDDR2/LPDD - 3 typically requires 10 us. - PSU_DDRC_INIT5_MAX_AUTO_INIT_X1024 0x4 - - SDRAM Initialization Register 5 - (OFFSET, MASK, VALUE) (0XFD0700E4, 0x00FF03FFU ,0x00210004U) - RegMask = (DDRC_INIT5_DEV_ZQINIT_X32_MASK | DDRC_INIT5_MAX_AUTO_INIT_X1024_MASK | 0 ); - - RegVal = ((0x00000021U << DDRC_INIT5_DEV_ZQINIT_X32_SHIFT - | 0x00000004U << DDRC_INIT5_MAX_AUTO_INIT_X1024_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_INIT5_OFFSET ,0x00FF03FFU ,0x00210004U); - /*############################################################################################################################ */ - - /*Register : INIT6 @ 0XFD0700E8

- - DDR4- Value to be loaded into SDRAM MR4 registers. Used in DDR4 designs only. - PSU_DDRC_INIT6_MR4 0x0 - - DDR4- Value to be loaded into SDRAM MR5 registers. Used in DDR4 designs only. - PSU_DDRC_INIT6_MR5 0x6c0 - - SDRAM Initialization Register 6 - (OFFSET, MASK, VALUE) (0XFD0700E8, 0xFFFFFFFFU ,0x000006C0U) - RegMask = (DDRC_INIT6_MR4_MASK | DDRC_INIT6_MR5_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_INIT6_MR4_SHIFT - | 0x000006C0U << DDRC_INIT6_MR5_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_INIT6_OFFSET ,0xFFFFFFFFU ,0x000006C0U); - /*############################################################################################################################ */ - - /*Register : INIT7 @ 0XFD0700EC

- - DDR4- Value to be loaded into SDRAM MR6 registers. Used in DDR4 designs only. - PSU_DDRC_INIT7_MR6 0x819 - - SDRAM Initialization Register 7 - (OFFSET, MASK, VALUE) (0XFD0700EC, 0xFFFF0000U ,0x08190000U) - RegMask = (DDRC_INIT7_MR6_MASK | 0 ); - - RegVal = ((0x00000819U << DDRC_INIT7_MR6_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_INIT7_OFFSET ,0xFFFF0000U ,0x08190000U); - /*############################################################################################################################ */ - - /*Register : DIMMCTL @ 0XFD0700F0

- - Disabling Address Mirroring for BG bits. When this is set to 1, BG0 and BG1 are NOT swapped even if Address Mirroring is enab - ed. This will be required for DDR4 DIMMs with x16 devices. - 1 - BG0 and BG1 are NOT swapped. - 0 - BG0 and BG1 are swapped i - address mirroring is enabled. - PSU_DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING 0x0 - - Enable for BG1 bit of MRS command. BG1 bit of the mode register address is specified as RFU (Reserved for Future Use) and mus - be programmed to 0 during MRS. In case where DRAMs which do not have BG1 are attached and both the CA parity and the Output - nversion are enabled, this must be set to 0, so that the calculation of CA parity will not include BG1 bit. Note: This has no - effect on the address of any other memory accesses, or of software-driven mode register accesses. If address mirroring is ena - led, this is applied to BG1 of even ranks and BG0 of odd ranks. - 1 - Enabled - 0 - Disabled - PSU_DDRC_DIMMCTL_MRS_BG1_EN 0x1 - - Enable for A17 bit of MRS command. A17 bit of the mode register address is specified as RFU (Reserved for Future Use) and mus - be programmed to 0 during MRS. In case where DRAMs which do not have A17 are attached and the Output Inversion are enabled, - his must be set to 0, so that the calculation of CA parity will not include A17 bit. Note: This has no effect on the address - f any other memory accesses, or of software-driven mode register accesses. - 1 - Enabled - 0 - Disabled - PSU_DDRC_DIMMCTL_MRS_A17_EN 0x0 - - Output Inversion Enable (for DDR4 RDIMM implementations only). DDR4 RDIMM implements the Output Inversion feature by default, - which means that the following address, bank address and bank group bits of B-side DRAMs are inverted: A3-A9, A11, A13, A17, - A0-BA1, BG0-BG1. Setting this bit ensures that, for mode register accesses generated by the uMCTL2 during the automatic initi - lization routine and enabling of a particular DDR4 feature, separate A-side and B-side mode register accesses are generated. - or B-side mode register accesses, these bits are inverted within the uMCTL2 to compensate for this RDIMM inversion. Note: Thi - has no effect on the address of any other memory accesses, or of software-driven mode register accesses. - 1 - Implement out - ut inversion for B-side DRAMs. - 0 - Do not implement output inversion for B-side DRAMs. - PSU_DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN 0x0 - - Address Mirroring Enable (for multi-rank UDIMM implementations and multi-rank DDR4 RDIMM implementations). Some UDIMMs and DD - 4 RDIMMs implement address mirroring for odd ranks, which means that the following address, bank address and bank group bits - re swapped: (A3, A4), (A5, A6), (A7, A8), (BA0, BA1) and also (A11, A13), (BG0, BG1) for the DDR4. Setting this bit ensures t - at, for mode register accesses during the automatic initialization routine, these bits are swapped within the uMCTL2 to compe - sate for this UDIMM/RDIMM swapping. In addition to the automatic initialization routine, in case of DDR4 UDIMM/RDIMM, they ar - swapped during the automatic MRS access to enable/disable of a particular DDR4 feature. Note: This has no effect on the addr - ss of any other memory accesses, or of software-driven mode register accesses. This is not supported for mDDR, LPDDR2, LPDDR3 - or LPDDR4 SDRAMs. Note: In case of x16 DDR4 DIMMs, BG1 output of MRS for the odd ranks is same as BG0 because BG1 is invalid, - hence dimm_dis_bg_mirroring register must be set to 1. - 1 - For odd ranks, implement address mirroring for MRS commands to d - ring initialization and for any automatic DDR4 MRS commands (to be used if UDIMM/RDIMM implements address mirroring) - 0 - Do - not implement address mirroring - PSU_DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN 0x0 - - Staggering enable for multi-rank accesses (for multi-rank UDIMM and RDIMM implementations only). This is not supported for mD - R, LPDDR2, LPDDR3 or LPDDR4 SDRAMs. Note: Even if this bit is set it does not take care of software driven MR commands (via M - CTRL0/MRCTRL1), where software is responsible to send them to seperate ranks as appropriate. - 1 - (DDR4) Send MRS commands t - each ranks seperately - 1 - (non-DDR4) Send all commands to even and odd ranks seperately - 0 - Do not stagger accesses - PSU_DDRC_DIMMCTL_DIMM_STAGGER_CS_EN 0x0 - - DIMM Control Register - (OFFSET, MASK, VALUE) (0XFD0700F0, 0x0000003FU ,0x00000010U) - RegMask = (DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_MASK | DDRC_DIMMCTL_MRS_BG1_EN_MASK | DDRC_DIMMCTL_MRS_A17_EN_MASK | DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_MASK | DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_MASK | DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_SHIFT - | 0x00000001U << DDRC_DIMMCTL_MRS_BG1_EN_SHIFT - | 0x00000000U << DDRC_DIMMCTL_MRS_A17_EN_SHIFT - | 0x00000000U << DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_SHIFT - | 0x00000000U << DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_SHIFT - | 0x00000000U << DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DIMMCTL_OFFSET ,0x0000003FU ,0x00000010U); - /*############################################################################################################################ */ - - /*Register : RANKCTL @ 0XFD0700F4

- - Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecuti - e writes to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This value should c - nsider both PHY requirement and ODT requirement. - PHY requirement: tphy_wrcsgap + 1 (see PHY databook for value of tphy_wrcs - ap) If CRC feature is enabled, should be increased by 1. If write preamble is set to 2tCK(DDR4/LPDDR4 only), should be increa - ed by 1. If write postamble is set to 1.5tCK(LPDDR4 only), should be increased by 1. - ODT requirement: The value programmed - n this register takes care of the ODT switch off timing requirement when switching ranks during writes. For LPDDR4, the requi - ement is ODTLoff - ODTLon - BL/2 + 1 For configurations with MEMC_FREQ_RATIO=1, program this to the larger of PHY requirement - or ODT requirement. For configurations with MEMC_FREQ_RATIO=2, program this to the larger value divided by two and round it u - to the next integer. - PSU_DDRC_RANKCTL_DIFF_RANK_WR_GAP 0x6 - - Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecuti - e reads to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This value should co - sider both PHY requirement and ODT requirement. - PHY requirement: tphy_rdcsgap + 1 (see PHY databook for value of tphy_rdcsg - p) If read preamble is set to 2tCK(DDR4/LPDDR4 only), should be increased by 1. If read postamble is set to 1.5tCK(LPDDR4 onl - ), should be increased by 1. - ODT requirement: The value programmed in this register takes care of the ODT switch off timing - requirement when switching ranks during reads. For configurations with MEMC_FREQ_RATIO=1, program this to the larger of PHY r - quirement or ODT requirement. For configurations with MEMC_FREQ_RATIO=2, program this to the larger value divided by two and - ound it up to the next integer. - PSU_DDRC_RANKCTL_DIFF_RANK_RD_GAP 0x6 - - Only present for multi-rank configurations. Background: Reads to the same rank can be performed back-to-back. Reads to differ - nt ranks require additional gap dictated by the register RANKCTL.diff_rank_rd_gap. This is to avoid possible data bus content - on as well as to give PHY enough time to switch the delay when changing ranks. The uMCTL2 arbitrates for bus access on a cycl - -by-cycle basis; therefore after a read is scheduled, there are few clock cycles (determined by the value on RANKCTL.diff_ran - _rd_gap register) in which only reads from the same rank are eligible to be scheduled. This prevents reads from other ranks f - om having fair access to the data bus. This parameter represents the maximum number of reads that can be scheduled consecutiv - ly to the same rank. After this number is reached, a delay equal to RANKCTL.diff_rank_rd_gap is inserted by the scheduler to - llow all ranks a fair opportunity to be scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fair - ess. This feature can be DISABLED by setting this register to 0. When set to 0, the Controller will stay on the same rank as - ong as commands are available for it. Minimum programmable value is 0 (feature disabled) and maximum programmable value is 0x - . FOR PERFORMANCE ONLY. - PSU_DDRC_RANKCTL_MAX_RANK_RD 0xf - - Rank Control Register - (OFFSET, MASK, VALUE) (0XFD0700F4, 0x00000FFFU ,0x0000066FU) - RegMask = (DDRC_RANKCTL_DIFF_RANK_WR_GAP_MASK | DDRC_RANKCTL_DIFF_RANK_RD_GAP_MASK | DDRC_RANKCTL_MAX_RANK_RD_MASK | 0 ); - - RegVal = ((0x00000006U << DDRC_RANKCTL_DIFF_RANK_WR_GAP_SHIFT - | 0x00000006U << DDRC_RANKCTL_DIFF_RANK_RD_GAP_SHIFT - | 0x0000000FU << DDRC_RANKCTL_MAX_RANK_RD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_RANKCTL_OFFSET ,0x00000FFFU ,0x0000066FU); - /*############################################################################################################################ */ - - /*Register : DRAMTMG0 @ 0XFD070100

- - Minimum time between write and precharge to same bank. Unit: Clocks Specifications: WL + BL/2 + tWR = approximately 8 cycles - 15 ns = 14 clocks @400MHz and less for lower frequencies where: - WL = write latency - BL = burst length. This must match th - value programmed in the BL bit of the mode register to the SDRAM. BST (burst terminate) is not supported at present. - tWR = - Write recovery time. This comes directly from the SDRAM specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 for this - arameter. For configurations with MEMC_FREQ_RATIO=2, 1T mode, divide the above value by 2. No rounding up. For configurations - with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, divide the above value by 2 and round it up to the next integer value. - PSU_DDRC_DRAMTMG0_WR2PRE 0x11 - - tFAW Valid only when 8 or more banks(or banks x bank groups) are present. In 8-bank design, at most 4 banks must be activated - in a rolling window of tFAW cycles. For configurations with MEMC_FREQ_RATIO=2, program this to (tFAW/2) and round up to next - nteger value. In a 4-bank design, set this register to 0x1 independent of the MEMC_FREQ_RATIO configuration. Unit: Clocks - PSU_DDRC_DRAMTMG0_T_FAW 0xc - - tRAS(max): Maximum time between activate and precharge to same bank. This is the maximum time that a page can be kept open Mi - imum value of this register is 1. Zero is invalid. For configurations with MEMC_FREQ_RATIO=2, program this to (tRAS(max)-1)/2 - No rounding up. Unit: Multiples of 1024 clocks. - PSU_DDRC_DRAMTMG0_T_RAS_MAX 0x24 - - tRAS(min): Minimum time between activate and precharge to the same bank. For configurations with MEMC_FREQ_RATIO=2, 1T mode, - rogram this to tRAS(min)/2. No rounding up. For configurations with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, program this t - (tRAS(min)/2) and round it up to the next integer value. Unit: Clocks - PSU_DDRC_DRAMTMG0_T_RAS_MIN 0x12 - - SDRAM Timing Register 0 - (OFFSET, MASK, VALUE) (0XFD070100, 0x7F3F7F3FU ,0x110C2412U) - RegMask = (DDRC_DRAMTMG0_WR2PRE_MASK | DDRC_DRAMTMG0_T_FAW_MASK | DDRC_DRAMTMG0_T_RAS_MAX_MASK | DDRC_DRAMTMG0_T_RAS_MIN_MASK | 0 ); - - RegVal = ((0x00000011U << DDRC_DRAMTMG0_WR2PRE_SHIFT - | 0x0000000CU << DDRC_DRAMTMG0_T_FAW_SHIFT - | 0x00000024U << DDRC_DRAMTMG0_T_RAS_MAX_SHIFT - | 0x00000012U << DDRC_DRAMTMG0_T_RAS_MIN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DRAMTMG0_OFFSET ,0x7F3F7F3FU ,0x110C2412U); - /*############################################################################################################################ */ - - /*Register : DRAMTMG1 @ 0XFD070104

- - tXP: Minimum time after power-down exit to any operation. For DDR3, this should be programmed to tXPDLL if slow powerdown exi - is selected in MR0[12]. If C/A parity for DDR4 is used, set to (tXP+PL) instead. For configurations with MEMC_FREQ_RATIO=2, - rogram this to (tXP/2) and round it up to the next integer value. Units: Clocks - PSU_DDRC_DRAMTMG1_T_XP 0x4 - - tRTP: Minimum time from read to precharge of same bank. - DDR2: tAL + BL/2 + max(tRTP, 2) - 2 - DDR3: tAL + max (tRTP, 4) - D - R4: Max of following two equations: tAL + max (tRTP, 4) or, RL + BL/2 - tRP. - mDDR: BL/2 - LPDDR2: Depends on if it's LPDDR2 - S2 or LPDDR2-S4: LPDDR2-S2: BL/2 + tRTP - 1. LPDDR2-S4: BL/2 + max(tRTP,2) - 2. - LPDDR3: BL/2 + max(tRTP,4) - 4 - LPDDR4: BL - 2 + max(tRTP,8) - 8 For configurations with MEMC_FREQ_RATIO=2, 1T mode, divide the above value by 2. No rounding up. For conf - gurations with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, divide the above value by 2 and round it up to the next integer val - e. Unit: Clocks. - PSU_DDRC_DRAMTMG1_RD2PRE 0x4 - - tRC: Minimum time between activates to same bank. For configurations with MEMC_FREQ_RATIO=2, program this to (tRC/2) and roun - up to next integer value. Unit: Clocks. - PSU_DDRC_DRAMTMG1_T_RC 0x19 - - SDRAM Timing Register 1 - (OFFSET, MASK, VALUE) (0XFD070104, 0x001F1F7FU ,0x00040419U) - RegMask = (DDRC_DRAMTMG1_T_XP_MASK | DDRC_DRAMTMG1_RD2PRE_MASK | DDRC_DRAMTMG1_T_RC_MASK | 0 ); - - RegVal = ((0x00000004U << DDRC_DRAMTMG1_T_XP_SHIFT - | 0x00000004U << DDRC_DRAMTMG1_RD2PRE_SHIFT - | 0x00000019U << DDRC_DRAMTMG1_T_RC_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DRAMTMG1_OFFSET ,0x001F1F7FU ,0x00040419U); - /*############################################################################################################################ */ - - /*Register : DRAMTMG2 @ 0XFD070108

- - Set to WL Time from write command to write data on SDRAM interface. This must be set to WL. For mDDR, it should normally be s - t to 1. Note that, depending on the PHY, if using RDIMM, it may be necessary to use a value of WL + 1 to compensate for the e - tra cycle of latency through the RDIMM For configurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above - equation by 2, and round it up to next integer. This register field is not required for DDR2 and DDR3 (except if MEMC_TRAININ - is set), as the DFI read and write latencies defined in DFITMG0 and DFITMG1 are sufficient for those protocols Unit: clocks - PSU_DDRC_DRAMTMG2_WRITE_LATENCY 0x7 - - Set to RL Time from read command to read data on SDRAM interface. This must be set to RL. Note that, depending on the PHY, if - using RDIMM, it mat be necessary to use a value of RL + 1 to compensate for the extra cycle of latency through the RDIMM For - onfigurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next inte - er. This register field is not required for DDR2 and DDR3 (except if MEMC_TRAINING is set), as the DFI read and write latenci - s defined in DFITMG0 and DFITMG1 are sufficient for those protocols Unit: clocks - PSU_DDRC_DRAMTMG2_READ_LATENCY 0x8 - - DDR2/3/mDDR: RL + BL/2 + 2 - WL DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL LPDDR2/LPDDR3: RL + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL - PDDR4(DQ ODT is Disabled): RL + BL/2 + RU(tDQSCKmax/tCK) + WR_PREAMBLE + RD_POSTAMBLE - WL LPDDR4(DQ ODT is Enabled) : RL + B - /2 + RU(tDQSCKmax/tCK) + RD_POSTAMBLE - ODTLon - RU(tODTon(min)/tCK) Minimum time from read command to write command. Include - time for bus turnaround and all per-bank, per-rank, and global constraints. Unit: Clocks. Where: - WL = write latency - BL = - urst length. This must match the value programmed in the BL bit of the mode register to the SDRAM - RL = read latency = CAS l - tency - WR_PREAMBLE = write preamble. This is unique to DDR4 and LPDDR4. - RD_POSTAMBLE = read postamble. This is unique to L - DDR4. For LPDDR2/LPDDR3/LPDDR4, if derating is enabled (DERATEEN.derate_enable=1), derated tDQSCKmax should be used. For conf - gurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next integer. - PSU_DDRC_DRAMTMG2_RD2WR 0x6 - - DDR4: CWL + PL + BL/2 + tWTR_L Others: CWL + BL/2 + tWTR In DDR4, minimum time from write command to read command for same ba - k group. In others, minimum time from write command to read command. Includes time for bus turnaround, recovery times, and al - per-bank, per-rank, and global constraints. Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity latency - BL = burs - length. This must match the value programmed in the BL bit of the mode register to the SDRAM - tWTR_L = internal write to re - d command delay for same bank group. This comes directly from the SDRAM specification. - tWTR = internal write to read comman - delay. This comes directly from the SDRAM specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 operation. For configu - ations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next integer. - PSU_DDRC_DRAMTMG2_WR2RD 0xe - - SDRAM Timing Register 2 - (OFFSET, MASK, VALUE) (0XFD070108, 0x3F3F3F3FU ,0x0708060EU) - RegMask = (DDRC_DRAMTMG2_WRITE_LATENCY_MASK | DDRC_DRAMTMG2_READ_LATENCY_MASK | DDRC_DRAMTMG2_RD2WR_MASK | DDRC_DRAMTMG2_WR2RD_MASK | 0 ); - - RegVal = ((0x00000007U << DDRC_DRAMTMG2_WRITE_LATENCY_SHIFT - | 0x00000008U << DDRC_DRAMTMG2_READ_LATENCY_SHIFT - | 0x00000006U << DDRC_DRAMTMG2_RD2WR_SHIFT - | 0x0000000EU << DDRC_DRAMTMG2_WR2RD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DRAMTMG2_OFFSET ,0x3F3F3F3FU ,0x0708060EU); - /*############################################################################################################################ */ - - /*Register : DRAMTMG3 @ 0XFD07010C

- - Time to wait after a mode register write or read (MRW or MRR). Present only in designs configured to support LPDDR2, LPDDR3 o - LPDDR4. LPDDR2 typically requires value of 5. LPDDR3 typically requires value of 10. LPDDR4: Set this to the larger of tMRW - nd tMRWCKEL. For LPDDR2, this register is used for the time from a MRW/MRR to all other commands. For LDPDR3, this register i - used for the time from a MRW/MRR to a MRW/MRR. - PSU_DDRC_DRAMTMG3_T_MRW 0x5 - - tMRD: Cycles to wait after a mode register write or read. Depending on the connected SDRAM, tMRD represents: DDR2/mDDR: Time - rom MRS to any command DDR3/4: Time from MRS to MRS command LPDDR2: not used LPDDR3/4: Time from MRS to non-MRS command For c - nfigurations with MEMC_FREQ_RATIO=2, program this to (tMRD/2) and round it up to the next integer value. If C/A parity for DD - 4 is used, set to tMRD_PAR(tMOD+PL) instead. - PSU_DDRC_DRAMTMG3_T_MRD 0x4 - - tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode command and following non-load mode command. If C/A pari - y for DDR4 is used, set to tMOD_PAR(tMOD+PL) instead. Set to tMOD if MEMC_FREQ_RATIO=1, or tMOD/2 (rounded up to next integer - if MEMC_FREQ_RATIO=2. Note that if using RDIMM, depending on the PHY, it may be necessary to use a value of tMOD + 1 or (tMO - + 1)/2 to compensate for the extra cycle of latency applied to mode register writes by the RDIMM chip. - PSU_DDRC_DRAMTMG3_T_MOD 0xc - - SDRAM Timing Register 3 - (OFFSET, MASK, VALUE) (0XFD07010C, 0x3FF3F3FFU ,0x0050400CU) - RegMask = (DDRC_DRAMTMG3_T_MRW_MASK | DDRC_DRAMTMG3_T_MRD_MASK | DDRC_DRAMTMG3_T_MOD_MASK | 0 ); - - RegVal = ((0x00000005U << DDRC_DRAMTMG3_T_MRW_SHIFT - | 0x00000004U << DDRC_DRAMTMG3_T_MRD_SHIFT - | 0x0000000CU << DDRC_DRAMTMG3_T_MOD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DRAMTMG3_OFFSET ,0x3FF3F3FFU ,0x0050400CU); - /*############################################################################################################################ */ - - /*Register : DRAMTMG4 @ 0XFD070110

- - tRCD - tAL: Minimum time from activate to read or write command to same bank. For configurations with MEMC_FREQ_RATIO=2, prog - am this to ((tRCD - tAL)/2) and round it up to the next integer value. Minimum value allowed for this register is 1, which im - lies minimum (tRCD - tAL) value to be 2 in configurations with MEMC_FREQ_RATIO=2. Unit: Clocks. - PSU_DDRC_DRAMTMG4_T_RCD 0x8 - - DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank group. Others: tCCD: This is the minimum - time between two reads or two writes. For configurations with MEMC_FREQ_RATIO=2, program this to (tCCD_L/2 or tCCD/2) and rou - d it up to the next integer value. Unit: clocks. - PSU_DDRC_DRAMTMG4_T_CCD 0x3 - - DDR4: tRRD_L: Minimum time between activates from bank 'a' to bank 'b' for same bank group. Others: tRRD: Minimum time betwee - activates from bank 'a' to bank 'b'For configurations with MEMC_FREQ_RATIO=2, program this to (tRRD_L/2 or tRRD/2) and round - it up to the next integer value. Unit: Clocks. - PSU_DDRC_DRAMTMG4_T_RRD 0x3 - - tRP: Minimum time from precharge to activate of same bank. For MEMC_FREQ_RATIO=1 configurations, t_rp should be set to RoundU - (tRP/tCK). For MEMC_FREQ_RATIO=2 configurations, t_rp should be set to RoundDown(RoundUp(tRP/tCK)/2) + 1. For MEMC_FREQ_RATIO - 2 configurations in LPDDR4, t_rp should be set to RoundUp(RoundUp(tRP/tCK)/2). Unit: Clocks. - PSU_DDRC_DRAMTMG4_T_RP 0x9 - - SDRAM Timing Register 4 - (OFFSET, MASK, VALUE) (0XFD070110, 0x1F0F0F1FU ,0x08030309U) - RegMask = (DDRC_DRAMTMG4_T_RCD_MASK | DDRC_DRAMTMG4_T_CCD_MASK | DDRC_DRAMTMG4_T_RRD_MASK | DDRC_DRAMTMG4_T_RP_MASK | 0 ); - - RegVal = ((0x00000008U << DDRC_DRAMTMG4_T_RCD_SHIFT - | 0x00000003U << DDRC_DRAMTMG4_T_CCD_SHIFT - | 0x00000003U << DDRC_DRAMTMG4_T_RRD_SHIFT - | 0x00000009U << DDRC_DRAMTMG4_T_RP_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DRAMTMG4_OFFSET ,0x1F0F0F1FU ,0x08030309U); - /*############################################################################################################################ */ - - /*Register : DRAMTMG5 @ 0XFD070114

- - This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stab - e time before SRX. Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEH - DDR2: 1 - DDR3: tCKSRX - DDR4: - tCKSRX For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it up to next in - eger. - PSU_DDRC_DRAMTMG5_T_CKSRX 0x6 - - This is the time after Self Refresh Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay afte - SRE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL - DDR2: 1 - DDR3: max (10 ns, 5 tCK) - DDR4: - ax (10 ns, 5 tCK) For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it up - to next integer. - PSU_DDRC_DRAMTMG5_T_CKSRE 0x6 - - Minimum CKE low width for Self refresh or Self refresh power down entry to exit timing in memory clock cycles. Recommended se - tings: - mDDR: tRFC - LPDDR2: tCKESR - LPDDR3: tCKESR - LPDDR4: max(tCKELPD, tSR) - DDR2: tCKE - DDR3: tCKE + 1 - DDR4: tCKE - 1 For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it up to next intege - . - PSU_DDRC_DRAMTMG5_T_CKESR 0x4 - - Minimum number of cycles of CKE HIGH/LOW during power-down and self refresh. - LPDDR2/LPDDR3 mode: Set this to the larger of - CKE or tCKESR - LPDDR4 mode: Set this to the larger of tCKE, tCKELPD or tSR. - Non-LPDDR2/non-LPDDR3/non-LPDDR4 designs: Set - his to tCKE value. For configurations with MEMC_FREQ_RATIO=2, program this to (value described above)/2 and round it up to th - next integer value. Unit: Clocks. - PSU_DDRC_DRAMTMG5_T_CKE 0x3 - - SDRAM Timing Register 5 - (OFFSET, MASK, VALUE) (0XFD070114, 0x0F0F3F1FU ,0x06060403U) - RegMask = (DDRC_DRAMTMG5_T_CKSRX_MASK | DDRC_DRAMTMG5_T_CKSRE_MASK | DDRC_DRAMTMG5_T_CKESR_MASK | DDRC_DRAMTMG5_T_CKE_MASK | 0 ); - - RegVal = ((0x00000006U << DDRC_DRAMTMG5_T_CKSRX_SHIFT - | 0x00000006U << DDRC_DRAMTMG5_T_CKSRE_SHIFT - | 0x00000004U << DDRC_DRAMTMG5_T_CKESR_SHIFT - | 0x00000003U << DDRC_DRAMTMG5_T_CKE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DRAMTMG5_OFFSET ,0x0F0F3F1FU ,0x06060403U); - /*############################################################################################################################ */ - - /*Register : DRAMTMG6 @ 0XFD070118

- - This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after - PDE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 For configurations with MEMC_FREQ_RATIO=2, program this to recom - ended value divided by two and round it up to next integer. This is only present for designs supporting mDDR or LPDDR2/LPDDR3 - devices. - PSU_DDRC_DRAMTMG6_T_CKDPDE 0x1 - - This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock - table time before DPDX. Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 For configurations with MEMC_FREQ_RATIO=2, pr - gram this to recommended value divided by two and round it up to next integer. This is only present for designs supporting mD - R or LPDDR2 devices. - PSU_DDRC_DRAMTMG6_T_CKDPDX 0x1 - - This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing Clock Stop Exit. Specifies the - lock stable time before next command after Clock Stop Exit. Recommended settings: - mDDR: 1 - LPDDR2: tXP + 2 - LPDDR3: tXP + - 2 - LPDDR4: tXP + 2 For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it - p to next integer. This is only present for designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices. - PSU_DDRC_DRAMTMG6_T_CKCSX 0x4 - - SDRAM Timing Register 6 - (OFFSET, MASK, VALUE) (0XFD070118, 0x0F0F000FU ,0x01010004U) - RegMask = (DDRC_DRAMTMG6_T_CKDPDE_MASK | DDRC_DRAMTMG6_T_CKDPDX_MASK | DDRC_DRAMTMG6_T_CKCSX_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_DRAMTMG6_T_CKDPDE_SHIFT - | 0x00000001U << DDRC_DRAMTMG6_T_CKDPDX_SHIFT - | 0x00000004U << DDRC_DRAMTMG6_T_CKCSX_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DRAMTMG6_OFFSET ,0x0F0F000FU ,0x01010004U); - /*############################################################################################################################ */ - - /*Register : DRAMTMG7 @ 0XFD07011C

- - This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. - ecommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL For configurations with MEMC_FREQ_RATIO=2, program t - is to recommended value divided by two and round it up to next integer. This is only present for designs supporting mDDR or L - DDR2/LPDDR3/LPDDR4 devices. - PSU_DDRC_DRAMTMG7_T_CKPDE 0x6 - - This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable - time before PDX. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: 2 For configurations with MEMC_FREQ_RATIO= - , program this to recommended value divided by two and round it up to next integer. This is only present for designs supporti - g mDDR or LPDDR2/LPDDR3/LPDDR4 devices. - PSU_DDRC_DRAMTMG7_T_CKPDX 0x6 - - SDRAM Timing Register 7 - (OFFSET, MASK, VALUE) (0XFD07011C, 0x00000F0FU ,0x00000606U) - RegMask = (DDRC_DRAMTMG7_T_CKPDE_MASK | DDRC_DRAMTMG7_T_CKPDX_MASK | 0 ); - - RegVal = ((0x00000006U << DDRC_DRAMTMG7_T_CKPDE_SHIFT - | 0x00000006U << DDRC_DRAMTMG7_T_CKPDX_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DRAMTMG7_OFFSET ,0x00000F0FU ,0x00000606U); - /*############################################################################################################################ */ - - /*Register : DRAMTMG8 @ 0XFD070120

- - tXS_FAST: Exit Self Refresh to ZQCL, ZQCS and MRS (only CL, WR, RTP and Geardown mode). For configurations with MEMC_FREQ_RAT - O=2, program this to the above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: Thi - is applicable to only ZQCL/ZQCS commands. Note: Ensure this is less than or equal to t_xs_x32. - PSU_DDRC_DRAMTMG8_T_XS_FAST_X32 0x4 - - tXS_ABORT: Exit Self Refresh to commands not requiring a locked DLL in Self Refresh Abort. For configurations with MEMC_FREQ_ - ATIO=2, program this to the above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: - nsure this is less than or equal to t_xs_x32. - PSU_DDRC_DRAMTMG8_T_XS_ABORT_X32 0x4 - - tXSDLL: Exit Self Refresh to commands requiring a locked DLL. For configurations with MEMC_FREQ_RATIO=2, program this to the - bove value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: Used only for DDR2, DDR3 and - DR4 SDRAMs. - PSU_DDRC_DRAMTMG8_T_XS_DLL_X32 0xd - - tXS: Exit Self Refresh to commands not requiring a locked DLL. For configurations with MEMC_FREQ_RATIO=2, program this to the - above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: Used only for DDR2, DDR3 and - DDR4 SDRAMs. - PSU_DDRC_DRAMTMG8_T_XS_X32 0x6 - - SDRAM Timing Register 8 - (OFFSET, MASK, VALUE) (0XFD070120, 0x7F7F7F7FU ,0x04040D06U) - RegMask = (DDRC_DRAMTMG8_T_XS_FAST_X32_MASK | DDRC_DRAMTMG8_T_XS_ABORT_X32_MASK | DDRC_DRAMTMG8_T_XS_DLL_X32_MASK | DDRC_DRAMTMG8_T_XS_X32_MASK | 0 ); - - RegVal = ((0x00000004U << DDRC_DRAMTMG8_T_XS_FAST_X32_SHIFT - | 0x00000004U << DDRC_DRAMTMG8_T_XS_ABORT_X32_SHIFT - | 0x0000000DU << DDRC_DRAMTMG8_T_XS_DLL_X32_SHIFT - | 0x00000006U << DDRC_DRAMTMG8_T_XS_X32_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DRAMTMG8_OFFSET ,0x7F7F7F7FU ,0x04040D06U); - /*############################################################################################################################ */ - - /*Register : DRAMTMG9 @ 0XFD070124

- - DDR4 Write preamble mode - 0: 1tCK preamble - 1: 2tCK preamble Present only with MEMC_FREQ_RATIO=2 - PSU_DDRC_DRAMTMG9_DDR4_WR_PREAMBLE 0x0 - - tCCD_S: This is the minimum time between two reads or two writes for different bank group. For bank switching (from bank 'a' - o bank 'b'), the minimum time is this value + 1. For configurations with MEMC_FREQ_RATIO=2, program this to (tCCD_S/2) and ro - nd it up to the next integer value. Present only in designs configured to support DDR4. Unit: clocks. - PSU_DDRC_DRAMTMG9_T_CCD_S 0x2 - - tRRD_S: Minimum time between activates from bank 'a' to bank 'b' for different bank group. For configurations with MEMC_FREQ_ - ATIO=2, program this to (tRRD_S/2) and round it up to the next integer value. Present only in designs configured to support D - R4. Unit: Clocks. - PSU_DDRC_DRAMTMG9_T_RRD_S 0x2 - - CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command for different bank group. Includes time for bus turn - round, recovery times, and all per-bank, per-rank, and global constraints. Present only in designs configured to support DDR4 - Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity latency - BL = burst length. This must match the value programm - d in the BL bit of the mode register to the SDRAM - tWTR_S = internal write to read command delay for different bank group. T - is comes directly from the SDRAM specification. For configurations with MEMC_FREQ_RATIO=2, divide the value calculated using - he above equation by 2, and round it up to next integer. - PSU_DDRC_DRAMTMG9_WR2RD_S 0xb - - SDRAM Timing Register 9 - (OFFSET, MASK, VALUE) (0XFD070124, 0x40070F3FU ,0x0002020BU) - RegMask = (DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_MASK | DDRC_DRAMTMG9_T_CCD_S_MASK | DDRC_DRAMTMG9_T_RRD_S_MASK | DDRC_DRAMTMG9_WR2RD_S_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_SHIFT - | 0x00000002U << DDRC_DRAMTMG9_T_CCD_S_SHIFT - | 0x00000002U << DDRC_DRAMTMG9_T_RRD_S_SHIFT - | 0x0000000BU << DDRC_DRAMTMG9_WR2RD_S_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DRAMTMG9_OFFSET ,0x40070F3FU ,0x0002020BU); - /*############################################################################################################################ */ - - /*Register : DRAMTMG11 @ 0XFD07012C

- - tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DLL. For configurations with MEMC_FREQ_RATIO=2, program - this to (tXMPDLL/2) and round it up to the next integer value. Present only in designs configured to support DDR4. Unit: Mult - ples of 32 clocks. - PSU_DDRC_DRAMTMG11_POST_MPSM_GAP_X32 0x6f - - tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge. For configurations with MEMC_FREQ_RATIO=2, program this t - RoundUp(tMPX_LH/2)+1. Present only in designs configured to support DDR4. Unit: clocks. - PSU_DDRC_DRAMTMG11_T_MPX_LH 0x7 - - tMPX_S: Minimum time CS setup time to CKE. For configurations with MEMC_FREQ_RATIO=2, program this to (tMPX_S/2) and round it - up to the next integer value. Present only in designs configured to support DDR4. Unit: Clocks. - PSU_DDRC_DRAMTMG11_T_MPX_S 0x1 - - tCKMPE: Minimum valid clock requirement after MPSM entry. Present only in designs configured to support DDR4. Unit: Clocks. F - r configurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next i - teger. - PSU_DDRC_DRAMTMG11_T_CKMPE 0xe - - SDRAM Timing Register 11 - (OFFSET, MASK, VALUE) (0XFD07012C, 0x7F1F031FU ,0x6F07010EU) - RegMask = (DDRC_DRAMTMG11_POST_MPSM_GAP_X32_MASK | DDRC_DRAMTMG11_T_MPX_LH_MASK | DDRC_DRAMTMG11_T_MPX_S_MASK | DDRC_DRAMTMG11_T_CKMPE_MASK | 0 ); - - RegVal = ((0x0000006FU << DDRC_DRAMTMG11_POST_MPSM_GAP_X32_SHIFT - | 0x00000007U << DDRC_DRAMTMG11_T_MPX_LH_SHIFT - | 0x00000001U << DDRC_DRAMTMG11_T_MPX_S_SHIFT - | 0x0000000EU << DDRC_DRAMTMG11_T_CKMPE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DRAMTMG11_OFFSET ,0x7F1F031FU ,0x6F07010EU); - /*############################################################################################################################ */ - - /*Register : DRAMTMG12 @ 0XFD070130

- - tCMDCKE: Delay from valid command to CKE input LOW. Set this to the larger of tESCKE or tCMDCKE For configurations with MEMC_ - REQ_RATIO=2, program this to (max(tESCKE, tCMDCKE)/2) and round it up to next integer value. - PSU_DDRC_DRAMTMG12_T_CMDCKE 0x2 - - tCKEHCMD: Valid command requirement after CKE input HIGH. For configurations with MEMC_FREQ_RATIO=2, program this to (tCKEHCM - /2) and round it up to next integer value. - PSU_DDRC_DRAMTMG12_T_CKEHCMD 0x6 - - tMRD_PDA: This is the Mode Register Set command cycle time in PDA mode. For configurations with MEMC_FREQ_RATIO=2, program th - s to (tMRD_PDA/2) and round it up to next integer value. - PSU_DDRC_DRAMTMG12_T_MRD_PDA 0x8 - - SDRAM Timing Register 12 - (OFFSET, MASK, VALUE) (0XFD070130, 0x00030F1FU ,0x00020608U) - RegMask = (DDRC_DRAMTMG12_T_CMDCKE_MASK | DDRC_DRAMTMG12_T_CKEHCMD_MASK | DDRC_DRAMTMG12_T_MRD_PDA_MASK | 0 ); - - RegVal = ((0x00000002U << DDRC_DRAMTMG12_T_CMDCKE_SHIFT - | 0x00000006U << DDRC_DRAMTMG12_T_CKEHCMD_SHIFT - | 0x00000008U << DDRC_DRAMTMG12_T_MRD_PDA_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DRAMTMG12_OFFSET ,0x00030F1FU ,0x00020608U); - /*############################################################################################################################ */ - - /*Register : ZQCTL0 @ 0XFD070180

- - - 1 - Disable uMCTL2 generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used instead to is - ue ZQ calibration request from APB module. - 0 - Internally generate ZQCS/MPC(ZQ calibration) commands based on ZQCTL1.t_zq_s - ort_interval_x1024. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. - PSU_DDRC_ZQCTL0_DIS_AUTO_ZQ 0x1 - - - 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable when run in DDR3 - or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. - 0 - Enable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Power - own exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. This is only present for designs suppo - ting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. - PSU_DDRC_ZQCTL0_DIS_SRX_ZQCL 0x0 - - - 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are sent to one r - nk at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to different ranks do not ov - rlap. - 0 - ZQ resistor is not shared. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. - PSU_DDRC_ZQCTL0_ZQ_RESISTOR_SHARED 0x0 - - - 1 - Disable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode. - 0 - Enable - ssuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode. This is only present for des - gns supporting DDR4 devices. - PSU_DDRC_ZQCTL0_DIS_MPSMX_ZQCL 0x0 - - tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Number of cycles of NOP required after a ZQCL (ZQ calibrat - on long)/MPC(ZQ Start) command is issued to SDRAM. For configurations with MEMC_FREQ_RATIO=2: DDR3/DDR4: program this to tZQo - er/2 and round it up to the next integer value. LPDDR2/LPDDR3: program this to tZQCL/2 and round it up to the next integer va - ue. LPDDR4: program this to tZQCAL/2 and round it up to the next integer value. Unit: Clock cycles. This is only present for - esigns supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. - PSU_DDRC_ZQCTL0_T_ZQ_LONG_NOP 0x100 - - tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of cycles of NOP required after a ZQCS (ZQ calibration short)/MPC - ZQ Latch) command is issued to SDRAM. For configurations with MEMC_FREQ_RATIO=2, program this to tZQCS/2 and round it up to t - e next integer value. Unit: Clock cycles. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devic - s. - PSU_DDRC_ZQCTL0_T_ZQ_SHORT_NOP 0x40 - - ZQ Control Register 0 - (OFFSET, MASK, VALUE) (0XFD070180, 0xF7FF03FFU ,0x81000040U) - RegMask = (DDRC_ZQCTL0_DIS_AUTO_ZQ_MASK | DDRC_ZQCTL0_DIS_SRX_ZQCL_MASK | DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_MASK | DDRC_ZQCTL0_DIS_MPSMX_ZQCL_MASK | DDRC_ZQCTL0_T_ZQ_LONG_NOP_MASK | DDRC_ZQCTL0_T_ZQ_SHORT_NOP_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_ZQCTL0_DIS_AUTO_ZQ_SHIFT - | 0x00000000U << DDRC_ZQCTL0_DIS_SRX_ZQCL_SHIFT - | 0x00000000U << DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_SHIFT - | 0x00000000U << DDRC_ZQCTL0_DIS_MPSMX_ZQCL_SHIFT - | 0x00000100U << DDRC_ZQCTL0_T_ZQ_LONG_NOP_SHIFT - | 0x00000040U << DDRC_ZQCTL0_T_ZQ_SHORT_NOP_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_ZQCTL0_OFFSET ,0xF7FF03FFU ,0x81000040U); - /*############################################################################################################################ */ - - /*Register : ZQCTL1 @ 0XFD070184

- - tZQReset: Number of cycles of NOP required after a ZQReset (ZQ calibration Reset) command is issued to SDRAM. For configurati - ns with MEMC_FREQ_RATIO=2, program this to tZQReset/2 and round it up to the next integer value. Unit: Clock cycles. This is - nly present for designs supporting LPDDR2/LPDDR3/LPDDR4 devices. - PSU_DDRC_ZQCTL1_T_ZQ_RESET_NOP 0x20 - - Average interval to wait between automatically issuing ZQCS (ZQ calibration short)/MPC(ZQ calibration) commands to DDR3/DDR4/ - PDDR2/LPDDR3/LPDDR4 devices. Meaningless, if ZQCTL0.dis_auto_zq=1. Unit: 1024 clock cycles. This is only present for designs - upporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. - PSU_DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024 0x19707 - - ZQ Control Register 1 - (OFFSET, MASK, VALUE) (0XFD070184, 0x3FFFFFFFU ,0x02019707U) - RegMask = (DDRC_ZQCTL1_T_ZQ_RESET_NOP_MASK | DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_MASK | 0 ); - - RegVal = ((0x00000020U << DDRC_ZQCTL1_T_ZQ_RESET_NOP_SHIFT - | 0x00019707U << DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_ZQCTL1_OFFSET ,0x3FFFFFFFU ,0x02019707U); - /*############################################################################################################################ */ - - /*Register : DFITMG0 @ 0XFD070190

- - Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signa - s at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligne - , this timing parameter should be rounded up to the next integer value. Note that if using RDIMM, it is necessary to incremen - this parameter by RDIMM's extra cycle of latency in terms of DFI clock. - PSU_DDRC_DFITMG0_DFI_T_CTRL_DELAY 0x4 - - Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR or SDR values Selects whether value in DFITM - 0.dfi_t_rddata_en is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles R - fer to PHY specification for correct value. - PSU_DDRC_DFITMG0_DFI_RDDATA_USE_SDR 0x1 - - Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. Refer to PHY spe - ification for correct value. This corresponds to the DFI parameter trddata_en. Note that, depending on the PHY, if using RDIM - , it may be necessary to use the value (CL + 1) in the calculation of trddata_en. This is to compensate for the extra cycle o - latency through the RDIMM. Unit: Clocks - PSU_DDRC_DFITMG0_DFI_T_RDDATA_EN 0xb - - Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using HDR or SDR values Selects whether value in DFITMG - .dfi_tphy_wrlat is in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.dfi_tphy_wrdata is in terms of SDR or - HDR clock cycles - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles Refer to PHY specification for correct val - e. - PSU_DDRC_DFITMG0_DFI_WRDATA_USE_SDR 0x1 - - Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on th - dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. N - te, max supported value is 8. Unit: Clocks - PSU_DDRC_DFITMG0_DFI_TPHY_WRDATA 0x2 - - Write latency Number of clocks from the write command to write data enable (dfi_wrdata_en). This corresponds to the DFI timin - parameter tphy_wrlat. Refer to PHY specification for correct value.Note that, depending on the PHY, if using RDIMM, it may b - necessary to use the value (CL + 1) in the calculation of tphy_wrlat. This is to compensate for the extra cycle of latency t - rough the RDIMM. - PSU_DDRC_DFITMG0_DFI_TPHY_WRLAT 0xb - - DFI Timing Register 0 - (OFFSET, MASK, VALUE) (0XFD070190, 0x1FBFBF3FU ,0x048B820BU) - RegMask = (DDRC_DFITMG0_DFI_T_CTRL_DELAY_MASK | DDRC_DFITMG0_DFI_RDDATA_USE_SDR_MASK | DDRC_DFITMG0_DFI_T_RDDATA_EN_MASK | DDRC_DFITMG0_DFI_WRDATA_USE_SDR_MASK | DDRC_DFITMG0_DFI_TPHY_WRDATA_MASK | DDRC_DFITMG0_DFI_TPHY_WRLAT_MASK | 0 ); - - RegVal = ((0x00000004U << DDRC_DFITMG0_DFI_T_CTRL_DELAY_SHIFT - | 0x00000001U << DDRC_DFITMG0_DFI_RDDATA_USE_SDR_SHIFT - | 0x0000000BU << DDRC_DFITMG0_DFI_T_RDDATA_EN_SHIFT - | 0x00000001U << DDRC_DFITMG0_DFI_WRDATA_USE_SDR_SHIFT - | 0x00000002U << DDRC_DFITMG0_DFI_TPHY_WRDATA_SHIFT - | 0x0000000BU << DDRC_DFITMG0_DFI_TPHY_WRLAT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DFITMG0_OFFSET ,0x1FBFBF3FU ,0x048B820BU); - /*############################################################################################################################ */ - - /*Register : DFITMG1 @ 0XFD070194

- - Specifies the number of DFI PHY clocks between when the dfi_cs signal is asserted and when the associated command is driven. - his field is used for CAL mode, should be set to '0' or the value which matches the CAL mode register setting in the DRAM. If - the PHY can add the latency for CAL mode, this should be set to '0'. Valid Range: 0, 3, 4, 5, 6, and 8 - PSU_DDRC_DFITMG1_DFI_T_CMD_LAT 0x0 - - Specifies the number of DFI PHY clocks between when the dfi_cs signal is asserted and when the associated dfi_parity_in signa - is driven. - PSU_DDRC_DFITMG1_DFI_T_PARIN_LAT 0x0 - - Specifies the number of DFI clocks between when the dfi_wrdata_en signal is asserted and when the corresponding write data tr - nsfer is completed on the DRAM bus. This corresponds to the DFI timing parameter twrdata_delay. Refer to PHY specification fo - correct value. For DFI 3.0 PHY, set to twrdata_delay, a new timing parameter introduced in DFI 3.0. For DFI 2.1 PHY, set to - phy_wrdata + (delay of DFI write data to the DRAM). Value to be programmed is in terms of DFI clocks, not PHY clocks. In FREQ - RATIO=2, divide PHY's value by 2 and round up to next integer. If using DFITMG0.dfi_wrdata_use_sdr=1, add 1 to the value. Uni - : Clocks - PSU_DDRC_DFITMG1_DFI_T_WRDATA_DELAY 0x3 - - Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to - he DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase - ligned, this timing parameter should be rounded up to the next integer value. - PSU_DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE 0x3 - - Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first - alid rising edge of the clock to the DRAM memory devices, at the PHY-DRAM boundary. If the DFI clock and the memory clock are - not phase aligned, this timing parameter should be rounded up to the next integer value. - PSU_DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE 0x4 - - DFI Timing Register 1 - (OFFSET, MASK, VALUE) (0XFD070194, 0xF31F0F0FU ,0x00030304U) - RegMask = (DDRC_DFITMG1_DFI_T_CMD_LAT_MASK | DDRC_DFITMG1_DFI_T_PARIN_LAT_MASK | DDRC_DFITMG1_DFI_T_WRDATA_DELAY_MASK | DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_MASK | DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_DFITMG1_DFI_T_CMD_LAT_SHIFT - | 0x00000000U << DDRC_DFITMG1_DFI_T_PARIN_LAT_SHIFT - | 0x00000003U << DDRC_DFITMG1_DFI_T_WRDATA_DELAY_SHIFT - | 0x00000003U << DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_SHIFT - | 0x00000004U << DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DFITMG1_OFFSET ,0xF31F0F0FU ,0x00030304U); - /*############################################################################################################################ */ - - /*Register : DFILPCFG0 @ 0XFD070198

- - Setting for DFI's tlp_resp time. Same value is used for both Power Down, Self Refresh, Deep Power Down and Maximum Power Savi - g modes. DFI 2.1 specification onwards, recommends using a fixed value of 7 always. - PSU_DDRC_DFILPCFG0_DFI_TLP_RESP 0x7 - - Value to drive on dfi_lp_wakeup signal when Deep Power Down mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 - cycles - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles - 0x7 - - 2048 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0xD - - 31072 cycles - 0xE - 262144 cycles - 0xF - Unlimited This is only present for designs supporting mDDR or LPDDR2/LPDDR3 device - . - PSU_DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD 0x0 - - Enables DFI Low Power interface handshaking during Deep Power Down Entry/Exit. - 0 - Disabled - 1 - Enabled This is only pres - nt for designs supporting mDDR or LPDDR2/LPDDR3 devices. - PSU_DDRC_DFILPCFG0_DFI_LP_EN_DPD 0x0 - - Value to drive on dfi_lp_wakeup signal when Self Refresh mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cy - les - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles - 0x7 - - 048 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0xD - 131 - 72 cycles - 0xE - 262144 cycles - 0xF - Unlimited - PSU_DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR 0x0 - - Enables DFI Low Power interface handshaking during Self Refresh Entry/Exit. - 0 - Disabled - 1 - Enabled - PSU_DDRC_DFILPCFG0_DFI_LP_EN_SR 0x1 - - Value to drive on dfi_lp_wakeup signal when Power Down mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycl - s - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles - 0x7 - 20 - 8 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0xD - 13107 - cycles - 0xE - 262144 cycles - 0xF - Unlimited - PSU_DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD 0x0 - - Enables DFI Low Power interface handshaking during Power Down Entry/Exit. - 0 - Disabled - 1 - Enabled - PSU_DDRC_DFILPCFG0_DFI_LP_EN_PD 0x1 - - DFI Low Power Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD070198, 0x0FF1F1F1U ,0x07000101U) - RegMask = (DDRC_DFILPCFG0_DFI_TLP_RESP_MASK | DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_MASK | DDRC_DFILPCFG0_DFI_LP_EN_DPD_MASK | DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_MASK | DDRC_DFILPCFG0_DFI_LP_EN_SR_MASK | DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_MASK | DDRC_DFILPCFG0_DFI_LP_EN_PD_MASK | 0 ); - - RegVal = ((0x00000007U << DDRC_DFILPCFG0_DFI_TLP_RESP_SHIFT - | 0x00000000U << DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_SHIFT - | 0x00000000U << DDRC_DFILPCFG0_DFI_LP_EN_DPD_SHIFT - | 0x00000000U << DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_SHIFT - | 0x00000001U << DDRC_DFILPCFG0_DFI_LP_EN_SR_SHIFT - | 0x00000000U << DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_SHIFT - | 0x00000001U << DDRC_DFILPCFG0_DFI_LP_EN_PD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DFILPCFG0_OFFSET ,0x0FF1F1F1U ,0x07000101U); - /*############################################################################################################################ */ - - /*Register : DFILPCFG1 @ 0XFD07019C

- - Value to drive on dfi_lp_wakeup signal when Maximum Power Saving Mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - - 16 cycles - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0 - D - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited This is only present for designs supporting DDR4 devices. - PSU_DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM 0x2 - - Enables DFI Low Power interface handshaking during Maximum Power Saving Mode Entry/Exit. - 0 - Disabled - 1 - Enabled This is - only present for designs supporting DDR4 devices. - PSU_DDRC_DFILPCFG1_DFI_LP_EN_MPSM 0x1 - - DFI Low Power Configuration Register 1 - (OFFSET, MASK, VALUE) (0XFD07019C, 0x000000F1U ,0x00000021U) - RegMask = (DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_MASK | DDRC_DFILPCFG1_DFI_LP_EN_MPSM_MASK | 0 ); - - RegVal = ((0x00000002U << DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_SHIFT - | 0x00000001U << DDRC_DFILPCFG1_DFI_LP_EN_MPSM_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DFILPCFG1_OFFSET ,0x000000F1U ,0x00000021U); - /*############################################################################################################################ */ - - /*Register : DFIUPD1 @ 0XFD0701A4

- - This is the minimum amount of time between uMCTL2 initiated DFI update requests (which is executed whenever the uMCTL2 is idl - ). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the fir - t read request when the uMCTL2 is idle. Unit: 1024 clocks - PSU_DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024 0x41 - - This is the maximum amount of time between uMCTL2 initiated DFI update requests. This timer resets with each update request; - hen the timer expires dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd_ackx is received. PHY can use this - idle time to recalibrate the delay lines to the DLLs. The DFI controller update is also used to reset PHY FIFO pointers in ca - e of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. - Note: Value programmed for DFIUPD1.dfi_t_ctrlupd_interval_max_x1024 must be greater than DFIUPD1.dfi_t_ctrlupd_interval_min_x - 024. Unit: 1024 clocks - PSU_DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024 0xe2 - - DFI Update Register 1 - (OFFSET, MASK, VALUE) (0XFD0701A4, 0x00FF00FFU ,0x004100E2U) - RegMask = (DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_MASK | DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_MASK | 0 ); - - RegVal = ((0x00000041U << DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_SHIFT - | 0x000000E2U << DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DFIUPD1_OFFSET ,0x00FF00FFU ,0x004100E2U); - /*############################################################################################################################ */ - - /*Register : DFIMISC @ 0XFD0701B0

- - Defines polarity of dfi_wrdata_cs and dfi_rddata_cs signals. - 0: Signals are active low - 1: Signals are active high - PSU_DDRC_DFIMISC_DFI_DATA_CS_POLARITY 0x0 - - DBI implemented in DDRC or PHY. - 0 - DDRC implements DBI functionality. - 1 - PHY implements DBI functionality. Present only - in designs configured to support DDR4 and LPDDR4. - PSU_DDRC_DFIMISC_PHY_DBI_MODE 0x0 - - PHY initialization complete enable signal. When asserted the dfi_init_complete signal can be used to trigger SDRAM initialisa - ion - PSU_DDRC_DFIMISC_DFI_INIT_COMPLETE_EN 0x0 - - DFI Miscellaneous Control Register - (OFFSET, MASK, VALUE) (0XFD0701B0, 0x00000007U ,0x00000000U) - RegMask = (DDRC_DFIMISC_DFI_DATA_CS_POLARITY_MASK | DDRC_DFIMISC_PHY_DBI_MODE_MASK | DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_DFIMISC_DFI_DATA_CS_POLARITY_SHIFT - | 0x00000000U << DDRC_DFIMISC_PHY_DBI_MODE_SHIFT - | 0x00000000U << DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DFIMISC_OFFSET ,0x00000007U ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : DFITMG2 @ 0XFD0701B4

- - >Number of clocks between when a read command is sent on the DFI control interface and when the associated dfi_rddata_cs sign - l is asserted. This corresponds to the DFI timing parameter tphy_rdcslat. Refer to PHY specification for correct value. - PSU_DDRC_DFITMG2_DFI_TPHY_RDCSLAT 0x9 - - Number of clocks between when a write command is sent on the DFI control interface and when the associated dfi_wrdata_cs sign - l is asserted. This corresponds to the DFI timing parameter tphy_wrcslat. Refer to PHY specification for correct value. - PSU_DDRC_DFITMG2_DFI_TPHY_WRCSLAT 0x6 - - DFI Timing Register 2 - (OFFSET, MASK, VALUE) (0XFD0701B4, 0x00003F3FU ,0x00000906U) - RegMask = (DDRC_DFITMG2_DFI_TPHY_RDCSLAT_MASK | DDRC_DFITMG2_DFI_TPHY_WRCSLAT_MASK | 0 ); - - RegVal = ((0x00000009U << DDRC_DFITMG2_DFI_TPHY_RDCSLAT_SHIFT - | 0x00000006U << DDRC_DFITMG2_DFI_TPHY_WRCSLAT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DFITMG2_OFFSET ,0x00003F3FU ,0x00000906U); - /*############################################################################################################################ */ - - /*Register : DBICTL @ 0XFD0701C0

- - Read DBI enable signal in DDRC. - 0 - Read DBI is disabled. - 1 - Read DBI is enabled. This signal must be set the same value - as DRAM's mode register. - DDR4: MR5 bit A12. When x4 devices are used, this signal must be set to 0. - LPDDR4: MR3[6] - PSU_DDRC_DBICTL_RD_DBI_EN 0x0 - - Write DBI enable signal in DDRC. - 0 - Write DBI is disabled. - 1 - Write DBI is enabled. This signal must be set the same va - ue as DRAM's mode register. - DDR4: MR5 bit A11. When x4 devices are used, this signal must be set to 0. - LPDDR4: MR3[7] - PSU_DDRC_DBICTL_WR_DBI_EN 0x0 - - DM enable signal in DDRC. - 0 - DM is disabled. - 1 - DM is enabled. This signal must be set the same logical value as DRAM's - mode register. - DDR4: Set this to same value as MR5 bit A10. When x4 devices are used, this signal must be set to 0. - LPDDR - : Set this to inverted value of MR13[5] which is opposite polarity from this signal - PSU_DDRC_DBICTL_DM_EN 0x1 - - DM/DBI Control Register - (OFFSET, MASK, VALUE) (0XFD0701C0, 0x00000007U ,0x00000001U) - RegMask = (DDRC_DBICTL_RD_DBI_EN_MASK | DDRC_DBICTL_WR_DBI_EN_MASK | DDRC_DBICTL_DM_EN_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_DBICTL_RD_DBI_EN_SHIFT - | 0x00000000U << DDRC_DBICTL_WR_DBI_EN_SHIFT - | 0x00000001U << DDRC_DBICTL_DM_EN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DBICTL_OFFSET ,0x00000007U ,0x00000001U); - /*############################################################################################################################ */ - - /*Register : ADDRMAP0 @ 0XFD070200

- - Selects the HIF address bit used as rank address bit 0. Valid Range: 0 to 27, and 31 Internal Base: 6 The selected HIF addres - bit is determined by adding the internal base to the value of this field. If set to 31, rank address bit 0 is set to 0. - PSU_DDRC_ADDRMAP0_ADDRMAP_CS_BIT0 0x1f - - Address Map Register 0 - (OFFSET, MASK, VALUE) (0XFD070200, 0x0000001FU ,0x0000001FU) - RegMask = (DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_MASK | 0 ); - - RegVal = ((0x0000001FU << DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_ADDRMAP0_OFFSET ,0x0000001FU ,0x0000001FU); - /*############################################################################################################################ */ - - /*Register : ADDRMAP1 @ 0XFD070204

- - Selects the HIF address bit used as bank address bit 2. Valid Range: 0 to 29 and 31 Internal Base: 4 The selected HIF address - bit is determined by adding the internal base to the value of this field. If set to 31, bank address bit 2 is set to 0. - PSU_DDRC_ADDRMAP1_ADDRMAP_BANK_B2 0x1f - - Selects the HIF address bits used as bank address bit 1. Valid Range: 0 to 30 Internal Base: 3 The selected HIF address bit f - r each of the bank address bits is determined by adding the internal base to the value of this field. - PSU_DDRC_ADDRMAP1_ADDRMAP_BANK_B1 0xa - - Selects the HIF address bits used as bank address bit 0. Valid Range: 0 to 30 Internal Base: 2 The selected HIF address bit f - r each of the bank address bits is determined by adding the internal base to the value of this field. - PSU_DDRC_ADDRMAP1_ADDRMAP_BANK_B0 0xa - - Address Map Register 1 - (OFFSET, MASK, VALUE) (0XFD070204, 0x001F1F1FU ,0x001F0A0AU) - RegMask = (DDRC_ADDRMAP1_ADDRMAP_BANK_B2_MASK | DDRC_ADDRMAP1_ADDRMAP_BANK_B1_MASK | DDRC_ADDRMAP1_ADDRMAP_BANK_B0_MASK | 0 ); - - RegVal = ((0x0000001FU << DDRC_ADDRMAP1_ADDRMAP_BANK_B2_SHIFT - | 0x0000000AU << DDRC_ADDRMAP1_ADDRMAP_BANK_B1_SHIFT - | 0x0000000AU << DDRC_ADDRMAP1_ADDRMAP_BANK_B0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_ADDRMAP1_OFFSET ,0x001F1F1FU ,0x001F0A0AU); - /*############################################################################################################################ */ - - /*Register : ADDRMAP2 @ 0XFD070208

- - - Full bus width mode: Selects the HIF address bit used as column address bit 5. - Half bus width mode: Selects the HIF addre - s bit used as column address bit 6. - Quarter bus width mode: Selects the HIF address bit used as column address bit 7 . Vali - Range: 0 to 7, and 15 Internal Base: 5 The selected HIF address bit is determined by adding the internal base to the value o - this field. If set to 15, this column address bit is set to 0. - PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B5 0x0 - - - Full bus width mode: Selects the HIF address bit used as column address bit 4. - Half bus width mode: Selects the HIF addre - s bit used as column address bit 5. - Quarter bus width mode: Selects the HIF address bit used as column address bit 6. Valid - Range: 0 to 7, and 15 Internal Base: 4 The selected HIF address bit is determined by adding the internal base to the value of - this field. If set to 15, this column address bit is set to 0. - PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B4 0x0 - - - Full bus width mode: Selects the HIF address bit used as column address bit 3. - Half bus width mode: Selects the HIF addre - s bit used as column address bit 4. - Quarter bus width mode: Selects the HIF address bit used as column address bit 5. Valid - Range: 0 to 7 Internal Base: 3 The selected HIF address bit is determined by adding the internal base to the value of this fi - ld. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=16, it is required to program this to 0, hence register does not exist i - this case. - PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B3 0x0 - - - Full bus width mode: Selects the HIF address bit used as column address bit 2. - Half bus width mode: Selects the HIF addre - s bit used as column address bit 3. - Quarter bus width mode: Selects the HIF address bit used as column address bit 4. Valid - Range: 0 to 7 Internal Base: 2 The selected HIF address bit is determined by adding the internal base to the value of this fi - ld. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=8 or 16, it is required to program this to 0. - PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B2 0x0 - - Address Map Register 2 - (OFFSET, MASK, VALUE) (0XFD070208, 0x0F0F0F0FU ,0x00000000U) - RegMask = (DDRC_ADDRMAP2_ADDRMAP_COL_B5_MASK | DDRC_ADDRMAP2_ADDRMAP_COL_B4_MASK | DDRC_ADDRMAP2_ADDRMAP_COL_B3_MASK | DDRC_ADDRMAP2_ADDRMAP_COL_B2_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_ADDRMAP2_ADDRMAP_COL_B5_SHIFT - | 0x00000000U << DDRC_ADDRMAP2_ADDRMAP_COL_B4_SHIFT - | 0x00000000U << DDRC_ADDRMAP2_ADDRMAP_COL_B3_SHIFT - | 0x00000000U << DDRC_ADDRMAP2_ADDRMAP_COL_B2_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_ADDRMAP2_OFFSET ,0x0F0F0F0FU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : ADDRMAP3 @ 0XFD07020C

- - - Full bus width mode: Selects the HIF address bit used as column address bit 9. - Half bus width mode: Selects the HIF addre - s bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). - Quarter bus width mode: Selects the HIF address bit used as - column address bit 13 (11 in LPDDR2/LPDDR3 mode). Valid Range: 0 to 7, and 15 Internal Base: 9 The selected HIF address bit i - determined by adding the internal base to the value of this field. If set to 15, this column address bit is set to 0. Note: - er JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source addr - ss bit can be mapped to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus an - hence column bit 10 is used. - PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B9 0x0 - - - Full bus width mode: Selects the HIF address bit used as column address bit 8. - Half bus width mode: Selects the HIF addre - s bit used as column address bit 9. - Quarter bus width mode: Selects the HIF address bit used as column address bit 11 (10 i - LPDDR2/LPDDR3 mode). Valid Range: 0 to 7, and 15 Internal Base: 8 The selected HIF address bit is determined by adding the i - ternal base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specif - cation, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to col - mn address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and hence column bit 10 is use - . - PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B8 0x0 - - - Full bus width mode: Selects the HIF address bit used as column address bit 7. - Half bus width mode: Selects the HIF addre - s bit used as column address bit 8. - Quarter bus width mode: Selects the HIF address bit used as column address bit 9. Valid - Range: 0 to 7, and 15 Internal Base: 7 The selected HIF address bit is determined by adding the internal base to the value of - this field. If set to 15, this column address bit is set to 0. - PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B7 0x0 - - - Full bus width mode: Selects the HIF address bit used as column address bit 6. - Half bus width mode: Selects the HIF addre - s bit used as column address bit 7. - Quarter bus width mode: Selects the HIF address bit used as column address bit 8. Valid - Range: 0 to 7, and 15 Internal Base: 6 The selected HIF address bit is determined by adding the internal base to the value of - this field. If set to 15, this column address bit is set to 0. - PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B6 0x0 - - Address Map Register 3 - (OFFSET, MASK, VALUE) (0XFD07020C, 0x0F0F0F0FU ,0x00000000U) - RegMask = (DDRC_ADDRMAP3_ADDRMAP_COL_B9_MASK | DDRC_ADDRMAP3_ADDRMAP_COL_B8_MASK | DDRC_ADDRMAP3_ADDRMAP_COL_B7_MASK | DDRC_ADDRMAP3_ADDRMAP_COL_B6_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_ADDRMAP3_ADDRMAP_COL_B9_SHIFT - | 0x00000000U << DDRC_ADDRMAP3_ADDRMAP_COL_B8_SHIFT - | 0x00000000U << DDRC_ADDRMAP3_ADDRMAP_COL_B7_SHIFT - | 0x00000000U << DDRC_ADDRMAP3_ADDRMAP_COL_B6_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_ADDRMAP3_OFFSET ,0x0F0F0F0FU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : ADDRMAP4 @ 0XFD070210

- - - Full bus width mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode). - Half bus width - mode: Unused. To make it unused, this should be tied to 4'hF. - Quarter bus width mode: Unused. To make it unused, this must - e tied to 4'hF. Valid Range: 0 to 7, and 15 Internal Base: 11 The selected HIF address bit is determined by adding the intern - l base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specificati - n, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column a - dress bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and hence column bit 10 is used. - PSU_DDRC_ADDRMAP4_ADDRMAP_COL_B11 0xf - - - Full bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). - Half bus width - mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode). - Quarter bus width mode: UNUSED. - To make it unused, this must be tied to 4'hF. Valid Range: 0 to 7, and 15 Internal Base: 10 The selected HIF address bit is d - termined by adding the internal base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per - JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source address - bit can be mapped to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and h - nce column bit 10 is used. - PSU_DDRC_ADDRMAP4_ADDRMAP_COL_B10 0xf - - Address Map Register 4 - (OFFSET, MASK, VALUE) (0XFD070210, 0x00000F0FU ,0x00000F0FU) - RegMask = (DDRC_ADDRMAP4_ADDRMAP_COL_B11_MASK | DDRC_ADDRMAP4_ADDRMAP_COL_B10_MASK | 0 ); - - RegVal = ((0x0000000FU << DDRC_ADDRMAP4_ADDRMAP_COL_B11_SHIFT - | 0x0000000FU << DDRC_ADDRMAP4_ADDRMAP_COL_B10_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_ADDRMAP4_OFFSET ,0x00000F0FU ,0x00000F0FU); - /*############################################################################################################################ */ - - /*Register : ADDRMAP5 @ 0XFD070214

- - Selects the HIF address bit used as row address bit 11. Valid Range: 0 to 11, and 15 Internal Base: 17 The selected HIF addre - s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 11 is set to 0. - PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B11 0x8 - - Selects the HIF address bits used as row address bits 2 to 10. Valid Range: 0 to 11, and 15 Internal Base: 8 (for row address - bit 2), 9 (for row address bit 3), 10 (for row address bit 4) etc increasing to 16 (for row address bit 10) The selected HIF - ddress bit for each of the row address bits is determined by adding the internal base to the value of this field. When value - 5 is used the values of row address bits 2 to 10 are defined by registers ADDRMAP9, ADDRMAP10, ADDRMAP11. - PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10 0xf - - Selects the HIF address bits used as row address bit 1. Valid Range: 0 to 11 Internal Base: 7 The selected HIF address bit fo - each of the row address bits is determined by adding the internal base to the value of this field. - PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B1 0x8 - - Selects the HIF address bits used as row address bit 0. Valid Range: 0 to 11 Internal Base: 6 The selected HIF address bit fo - each of the row address bits is determined by adding the internal base to the value of this field. - PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B0 0x8 - - Address Map Register 5 - (OFFSET, MASK, VALUE) (0XFD070214, 0x0F0F0F0FU ,0x080F0808U) - RegMask = (DDRC_ADDRMAP5_ADDRMAP_ROW_B11_MASK | DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_MASK | DDRC_ADDRMAP5_ADDRMAP_ROW_B1_MASK | DDRC_ADDRMAP5_ADDRMAP_ROW_B0_MASK | 0 ); - - RegVal = ((0x00000008U << DDRC_ADDRMAP5_ADDRMAP_ROW_B11_SHIFT - | 0x0000000FU << DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_SHIFT - | 0x00000008U << DDRC_ADDRMAP5_ADDRMAP_ROW_B1_SHIFT - | 0x00000008U << DDRC_ADDRMAP5_ADDRMAP_ROW_B0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_ADDRMAP5_OFFSET ,0x0F0F0F0FU ,0x080F0808U); - /*############################################################################################################################ */ - - /*Register : ADDRMAP6 @ 0XFD070218

- - Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use. - 1 - LPDDR3 SDRAM 6Gb/12Gb device in use. Every address - having row[14:13]==2'b11 is considered as invalid - 0 - non-LPDDR3 6Gb/12Gb device in use. All addresses are valid Present on - y in designs configured to support LPDDR3. - PSU_DDRC_ADDRMAP6_LPDDR3_6GB_12GB 0x0 - - Selects the HIF address bit used as row address bit 15. Valid Range: 0 to 11, and 15 Internal Base: 21 The selected HIF addre - s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 15 is set to 0. - PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B15 0xf - - Selects the HIF address bit used as row address bit 14. Valid Range: 0 to 11, and 15 Internal Base: 20 The selected HIF addre - s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 14 is set to 0. - PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B14 0x8 - - Selects the HIF address bit used as row address bit 13. Valid Range: 0 to 11, and 15 Internal Base: 19 The selected HIF addre - s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 13 is set to 0. - PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B13 0x8 - - Selects the HIF address bit used as row address bit 12. Valid Range: 0 to 11, and 15 Internal Base: 18 The selected HIF addre - s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 12 is set to 0. - PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B12 0x8 - - Address Map Register 6 - (OFFSET, MASK, VALUE) (0XFD070218, 0x8F0F0F0FU ,0x0F080808U) - RegMask = (DDRC_ADDRMAP6_LPDDR3_6GB_12GB_MASK | DDRC_ADDRMAP6_ADDRMAP_ROW_B15_MASK | DDRC_ADDRMAP6_ADDRMAP_ROW_B14_MASK | DDRC_ADDRMAP6_ADDRMAP_ROW_B13_MASK | DDRC_ADDRMAP6_ADDRMAP_ROW_B12_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_ADDRMAP6_LPDDR3_6GB_12GB_SHIFT - | 0x0000000FU << DDRC_ADDRMAP6_ADDRMAP_ROW_B15_SHIFT - | 0x00000008U << DDRC_ADDRMAP6_ADDRMAP_ROW_B14_SHIFT - | 0x00000008U << DDRC_ADDRMAP6_ADDRMAP_ROW_B13_SHIFT - | 0x00000008U << DDRC_ADDRMAP6_ADDRMAP_ROW_B12_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_ADDRMAP6_OFFSET ,0x8F0F0F0FU ,0x0F080808U); - /*############################################################################################################################ */ - - /*Register : ADDRMAP7 @ 0XFD07021C

- - Selects the HIF address bit used as row address bit 17. Valid Range: 0 to 10, and 15 Internal Base: 23 The selected HIF addre - s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 17 is set to 0. - PSU_DDRC_ADDRMAP7_ADDRMAP_ROW_B17 0xf - - Selects the HIF address bit used as row address bit 16. Valid Range: 0 to 11, and 15 Internal Base: 22 The selected HIF addre - s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 16 is set to 0. - PSU_DDRC_ADDRMAP7_ADDRMAP_ROW_B16 0xf - - Address Map Register 7 - (OFFSET, MASK, VALUE) (0XFD07021C, 0x00000F0FU ,0x00000F0FU) - RegMask = (DDRC_ADDRMAP7_ADDRMAP_ROW_B17_MASK | DDRC_ADDRMAP7_ADDRMAP_ROW_B16_MASK | 0 ); - - RegVal = ((0x0000000FU << DDRC_ADDRMAP7_ADDRMAP_ROW_B17_SHIFT - | 0x0000000FU << DDRC_ADDRMAP7_ADDRMAP_ROW_B16_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_ADDRMAP7_OFFSET ,0x00000F0FU ,0x00000F0FU); - /*############################################################################################################################ */ - - /*Register : ADDRMAP8 @ 0XFD070220

- - Selects the HIF address bits used as bank group address bit 1. Valid Range: 0 to 30, and 31 Internal Base: 3 The selected HIF - address bit for each of the bank group address bits is determined by adding the internal base to the value of this field. If - et to 31, bank group address bit 1 is set to 0. - PSU_DDRC_ADDRMAP8_ADDRMAP_BG_B1 0x8 - - Selects the HIF address bits used as bank group address bit 0. Valid Range: 0 to 30 Internal Base: 2 The selected HIF address - bit for each of the bank group address bits is determined by adding the internal base to the value of this field. - PSU_DDRC_ADDRMAP8_ADDRMAP_BG_B0 0x8 - - Address Map Register 8 - (OFFSET, MASK, VALUE) (0XFD070220, 0x00001F1FU ,0x00000808U) - RegMask = (DDRC_ADDRMAP8_ADDRMAP_BG_B1_MASK | DDRC_ADDRMAP8_ADDRMAP_BG_B0_MASK | 0 ); - - RegVal = ((0x00000008U << DDRC_ADDRMAP8_ADDRMAP_BG_B1_SHIFT - | 0x00000008U << DDRC_ADDRMAP8_ADDRMAP_BG_B0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_ADDRMAP8_OFFSET ,0x00001F1FU ,0x00000808U); - /*############################################################################################################################ */ - - /*Register : ADDRMAP9 @ 0XFD070224

- - Selects the HIF address bits used as row address bit 5. Valid Range: 0 to 11 Internal Base: 11 The selected HIF address bit f - r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u - ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15. - PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B5 0x8 - - Selects the HIF address bits used as row address bit 4. Valid Range: 0 to 11 Internal Base: 10 The selected HIF address bit f - r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u - ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15. - PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B4 0x8 - - Selects the HIF address bits used as row address bit 3. Valid Range: 0 to 11 Internal Base: 9 The selected HIF address bit fo - each of the row address bits is determined by adding the internal base to the value of this field. This register field is us - d only when ADDRMAP5.addrmap_row_b2_10 is set to value 15. - PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B3 0x8 - - Selects the HIF address bits used as row address bit 2. Valid Range: 0 to 11 Internal Base: 8 The selected HIF address bit fo - each of the row address bits is determined by adding the internal base to the value of this field. This register field is us - d only when ADDRMAP5.addrmap_row_b2_10 is set to value 15. - PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B2 0x8 - - Address Map Register 9 - (OFFSET, MASK, VALUE) (0XFD070224, 0x0F0F0F0FU ,0x08080808U) - RegMask = (DDRC_ADDRMAP9_ADDRMAP_ROW_B5_MASK | DDRC_ADDRMAP9_ADDRMAP_ROW_B4_MASK | DDRC_ADDRMAP9_ADDRMAP_ROW_B3_MASK | DDRC_ADDRMAP9_ADDRMAP_ROW_B2_MASK | 0 ); - - RegVal = ((0x00000008U << DDRC_ADDRMAP9_ADDRMAP_ROW_B5_SHIFT - | 0x00000008U << DDRC_ADDRMAP9_ADDRMAP_ROW_B4_SHIFT - | 0x00000008U << DDRC_ADDRMAP9_ADDRMAP_ROW_B3_SHIFT - | 0x00000008U << DDRC_ADDRMAP9_ADDRMAP_ROW_B2_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_ADDRMAP9_OFFSET ,0x0F0F0F0FU ,0x08080808U); - /*############################################################################################################################ */ - - /*Register : ADDRMAP10 @ 0XFD070228

- - Selects the HIF address bits used as row address bit 9. Valid Range: 0 to 11 Internal Base: 15 The selected HIF address bit f - r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u - ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15. - PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B9 0x8 - - Selects the HIF address bits used as row address bit 8. Valid Range: 0 to 11 Internal Base: 14 The selected HIF address bit f - r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u - ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15. - PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B8 0x8 - - Selects the HIF address bits used as row address bit 7. Valid Range: 0 to 11 Internal Base: 13 The selected HIF address bit f - r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u - ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15. - PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B7 0x8 - - Selects the HIF address bits used as row address bit 6. Valid Range: 0 to 11 Internal Base: 12 The selected HIF address bit f - r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u - ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15. - PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B6 0x8 - - Address Map Register 10 - (OFFSET, MASK, VALUE) (0XFD070228, 0x0F0F0F0FU ,0x08080808U) - RegMask = (DDRC_ADDRMAP10_ADDRMAP_ROW_B9_MASK | DDRC_ADDRMAP10_ADDRMAP_ROW_B8_MASK | DDRC_ADDRMAP10_ADDRMAP_ROW_B7_MASK | DDRC_ADDRMAP10_ADDRMAP_ROW_B6_MASK | 0 ); - - RegVal = ((0x00000008U << DDRC_ADDRMAP10_ADDRMAP_ROW_B9_SHIFT - | 0x00000008U << DDRC_ADDRMAP10_ADDRMAP_ROW_B8_SHIFT - | 0x00000008U << DDRC_ADDRMAP10_ADDRMAP_ROW_B7_SHIFT - | 0x00000008U << DDRC_ADDRMAP10_ADDRMAP_ROW_B6_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_ADDRMAP10_OFFSET ,0x0F0F0F0FU ,0x08080808U); - /*############################################################################################################################ */ - - /*Register : ADDRMAP11 @ 0XFD07022C

- - Selects the HIF address bits used as row address bit 10. Valid Range: 0 to 11 Internal Base: 16 The selected HIF address bit - or each of the row address bits is determined by adding the internal base to the value of this field. This register field is - sed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15. - PSU_DDRC_ADDRMAP11_ADDRMAP_ROW_B10 0x8 - - Address Map Register 11 - (OFFSET, MASK, VALUE) (0XFD07022C, 0x0000000FU ,0x00000008U) - RegMask = (DDRC_ADDRMAP11_ADDRMAP_ROW_B10_MASK | 0 ); - - RegVal = ((0x00000008U << DDRC_ADDRMAP11_ADDRMAP_ROW_B10_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_ADDRMAP11_OFFSET ,0x0000000FU ,0x00000008U); - /*############################################################################################################################ */ - - /*Register : ODTCFG @ 0XFD070240

- - Cycles to hold ODT for a write command. The minimum supported value is 2. Recommended values: DDR2: - BL8: 0x5 (DDR2-400/533/ - 67), 0x6 (DDR2-800), 0x7 (DDR2-1066) - BL4: 0x3 (DDR2-400/533/667), 0x4 (DDR2-800), 0x5 (DDR2-1066) DDR3: - BL8: 0x6 DDR4: - - L8: 5 + WR_PREAMBLE + CRC_MODE WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) CRC_MODE = 0 (not CRC mode), 1 - CRC mode) LPDDR3: - BL8: 7 + RU(tODTon(max)/tCK) - PSU_DDRC_ODTCFG_WR_ODT_HOLD 0x6 - - The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting must - remain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: - CWL + AL - 3 (DDR2-400/533/ - 67), CWL + AL - 4 (DDR2-800), CWL + AL - 5 (DDR2-1066) If (CWL + AL - 3 < 0), uMCTL2 does not support ODT for write operation - DDR3: - 0x0 DDR4: - DFITMG1.dfi_t_cmd_lat (to adjust for CAL mode) LPDDR3: - WL - 1 - RU(tODTon(max)/tCK)) - PSU_DDRC_ODTCFG_WR_ODT_DELAY 0x0 - - Cycles to hold ODT for a read command. The minimum supported value is 2. Recommended values: DDR2: - BL8: 0x6 (not DDR2-1066) - 0x7 (DDR2-1066) - BL4: 0x4 (not DDR2-1066), 0x5 (DDR2-1066) DDR3: - BL8 - 0x6 DDR4: - BL8: 5 + RD_PREAMBLE RD_PREAMBLE = 1 ( - tCK write preamble), 2 (2tCK write preamble) LPDDR3: - BL8: 5 + RU(tDQSCK(max)/tCK) - RD(tDQSCK(min)/tCK) + RU(tODTon(max)/tC - ) - PSU_DDRC_ODTCFG_RD_ODT_HOLD 0x6 - - The delay, in clock cycles, from issuing a read command to setting ODT values associated with that command. ODT setting must - emain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: - CL + AL - 4 (not DDR2-1066), - CL + AL - 5 (DDR2-1066) If (CL + AL - 4 < 0), uMCTL2 does not support ODT for read operation. DDR3: - CL - CWL DDR4: - CL - C - L - RD_PREAMBLE + WR_PREAMBLE + DFITMG1.dfi_t_cmd_lat (to adjust for CAL mode) WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK - write preamble) RD_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) If (CL - CWL - RD_PREAMBLE + WR_PREAMBLE) < 0, - uMCTL2 does not support ODT for read operation. LPDDR3: - RL + RD(tDQSCK(min)/tCK) - 1 - RU(tODTon(max)/tCK) - PSU_DDRC_ODTCFG_RD_ODT_DELAY 0x0 - - ODT Configuration Register - (OFFSET, MASK, VALUE) (0XFD070240, 0x0F1F0F7CU ,0x06000600U) - RegMask = (DDRC_ODTCFG_WR_ODT_HOLD_MASK | DDRC_ODTCFG_WR_ODT_DELAY_MASK | DDRC_ODTCFG_RD_ODT_HOLD_MASK | DDRC_ODTCFG_RD_ODT_DELAY_MASK | 0 ); - - RegVal = ((0x00000006U << DDRC_ODTCFG_WR_ODT_HOLD_SHIFT - | 0x00000000U << DDRC_ODTCFG_WR_ODT_DELAY_SHIFT - | 0x00000006U << DDRC_ODTCFG_RD_ODT_HOLD_SHIFT - | 0x00000000U << DDRC_ODTCFG_RD_ODT_DELAY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_ODTCFG_OFFSET ,0x0F1F0F7CU ,0x06000600U); - /*############################################################################################################################ */ - - /*Register : ODTMAP @ 0XFD070244

- - Indicates which remote ODTs must be turned on during a read from rank 1. Each rank has a remote ODT (in the SDRAM) which can - e turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB - etc. For each rank, set its bit to 1 to enable its ODT. Present only in configurations that have 2 or more ranks - PSU_DDRC_ODTMAP_RANK1_RD_ODT 0x0 - - Indicates which remote ODTs must be turned on during a write to rank 1. Each rank has a remote ODT (in the SDRAM) which can b - turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB, - etc. For each rank, set its bit to 1 to enable its ODT. Present only in configurations that have 2 or more ranks - PSU_DDRC_ODTMAP_RANK1_WR_ODT 0x0 - - Indicates which remote ODTs must be turned on during a read from rank 0. Each rank has a remote ODT (in the SDRAM) which can - e turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB - etc. For each rank, set its bit to 1 to enable its ODT. - PSU_DDRC_ODTMAP_RANK0_RD_ODT 0x0 - - Indicates which remote ODTs must be turned on during a write to rank 0. Each rank has a remote ODT (in the SDRAM) which can b - turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB, - etc. For each rank, set its bit to 1 to enable its ODT. - PSU_DDRC_ODTMAP_RANK0_WR_ODT 0x1 - - ODT/Rank Map Register - (OFFSET, MASK, VALUE) (0XFD070244, 0x00003333U ,0x00000001U) - RegMask = (DDRC_ODTMAP_RANK1_RD_ODT_MASK | DDRC_ODTMAP_RANK1_WR_ODT_MASK | DDRC_ODTMAP_RANK0_RD_ODT_MASK | DDRC_ODTMAP_RANK0_WR_ODT_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_ODTMAP_RANK1_RD_ODT_SHIFT - | 0x00000000U << DDRC_ODTMAP_RANK1_WR_ODT_SHIFT - | 0x00000000U << DDRC_ODTMAP_RANK0_RD_ODT_SHIFT - | 0x00000001U << DDRC_ODTMAP_RANK0_WR_ODT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_ODTMAP_OFFSET ,0x00003333U ,0x00000001U); - /*############################################################################################################################ */ - - /*Register : SCHED @ 0XFD070250

- - When the preferred transaction store is empty for these many clock cycles, switch to the alternate transaction store if it is - non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write t - ansaction store is the alternative store. When prefer write over read is set this is reversed. 0x0 is a legal value for this - egister. When set to 0x0, the transaction store switching will happen immediately when the switching conditions become true. - OR PERFORMANCE ONLY - PSU_DDRC_SCHED_RDWR_IDLE_GAP 0x1 - - UNUSED - PSU_DDRC_SCHED_GO2CRITICAL_HYSTERESIS 0x0 - - Number of entries in the low priority transaction store is this value + 1. (MEMC_NO_OF_ENTRY - (SCHED.lpr_num_entries + 1)) i - the number of entries available for the high priority transaction store. Setting this to maximum value allocates all entries - to low priority transaction store. Setting this to 0 allocates 1 entry to low priority transaction store and the rest to high - priority transaction store. Note: In ECC configurations, the numbers of write and low priority read credits issued is one les - than in the non-ECC case. One entry each is reserved in the write and low-priority read CAMs for storing the RMW requests ar - sing out of single bit error correction RMW operation. - PSU_DDRC_SCHED_LPR_NUM_ENTRIES 0x20 - - If true, bank is kept open only while there are page hit transactions available in the CAM to that bank. The last read or wri - e command in the CAM with a bank and page hit will be executed with auto-precharge if SCHED1.pageclose_timer=0. Even if this - egister set to 1 and SCHED1.pageclose_timer is set to 0, explicit precharge (and not auto-precharge) may be issued in some ca - es where there is a mode switch between Write and Read or between LPR and HPR. The Read and Write commands that are executed - s part of the ECC scrub requests are also executed without auto-precharge. If false, the bank remains open until there is a n - ed to close it (to open a different page, or for page timeout or refresh timeout) - also known as open page policy. The open - age policy can be overridden by setting the per-command-autopre bit on the HIF interface (hif_cmd_autopre). The pageclose fea - ure provids a midway between Open and Close page policies. FOR PERFORMANCE ONLY. - PSU_DDRC_SCHED_PAGECLOSE 0x0 - - If set then the bank selector prefers writes over reads. FOR DEBUG ONLY. - PSU_DDRC_SCHED_PREFER_WRITE 0x0 - - Active low signal. When asserted ('0'), all incoming transactions are forced to low priority. This implies that all High Prio - ity Read (HPR) and Variable Priority Read commands (VPR) will be treated as Low Priority Read (LPR) commands. On the write si - e, all Variable Priority Write (VPW) commands will be treated as Normal Priority Write (NPW) commands. Forcing the incoming t - ansactions to low priority implicitly turns off Bypass path for read commands. FOR PERFORMANCE ONLY. - PSU_DDRC_SCHED_FORCE_LOW_PRI_N 0x1 - - Scheduler Control Register - (OFFSET, MASK, VALUE) (0XFD070250, 0x7FFF3F07U ,0x01002001U) - RegMask = (DDRC_SCHED_RDWR_IDLE_GAP_MASK | DDRC_SCHED_GO2CRITICAL_HYSTERESIS_MASK | DDRC_SCHED_LPR_NUM_ENTRIES_MASK | DDRC_SCHED_PAGECLOSE_MASK | DDRC_SCHED_PREFER_WRITE_MASK | DDRC_SCHED_FORCE_LOW_PRI_N_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_SCHED_RDWR_IDLE_GAP_SHIFT - | 0x00000000U << DDRC_SCHED_GO2CRITICAL_HYSTERESIS_SHIFT - | 0x00000020U << DDRC_SCHED_LPR_NUM_ENTRIES_SHIFT - | 0x00000000U << DDRC_SCHED_PAGECLOSE_SHIFT - | 0x00000000U << DDRC_SCHED_PREFER_WRITE_SHIFT - | 0x00000001U << DDRC_SCHED_FORCE_LOW_PRI_N_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_SCHED_OFFSET ,0x7FFF3F07U ,0x01002001U); - /*############################################################################################################################ */ - - /*Register : PERFLPR1 @ 0XFD070264

- - Number of transactions that are serviced once the LPR queue goes critical is the smaller of: - (a) This number - (b) Number o - transactions available. Unit: Transaction. FOR PERFORMANCE ONLY. - PSU_DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH 0x8 - - Number of clocks that the LPR queue can be starved before it goes critical. The minimum valid functional value for this regis - er is 0x1. Programming it to 0x0 will disable the starvation functionality; during normal operation, this function should not - be disabled as it will cause excessive latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY. - PSU_DDRC_PERFLPR1_LPR_MAX_STARVE 0x40 - - Low Priority Read CAM Register 1 - (OFFSET, MASK, VALUE) (0XFD070264, 0xFF00FFFFU ,0x08000040U) - RegMask = (DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_MASK | DDRC_PERFLPR1_LPR_MAX_STARVE_MASK | 0 ); - - RegVal = ((0x00000008U << DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_SHIFT - | 0x00000040U << DDRC_PERFLPR1_LPR_MAX_STARVE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PERFLPR1_OFFSET ,0xFF00FFFFU ,0x08000040U); - /*############################################################################################################################ */ - - /*Register : PERFWR1 @ 0XFD07026C

- - Number of transactions that are serviced once the WR queue goes critical is the smaller of: - (a) This number - (b) Number of - transactions available. Unit: Transaction. FOR PERFORMANCE ONLY. - PSU_DDRC_PERFWR1_W_XACT_RUN_LENGTH 0x8 - - Number of clocks that the WR queue can be starved before it goes critical. The minimum valid functional value for this regist - r is 0x1. Programming it to 0x0 will disable the starvation functionality; during normal operation, this function should not - e disabled as it will cause excessive latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY. - PSU_DDRC_PERFWR1_W_MAX_STARVE 0x40 - - Write CAM Register 1 - (OFFSET, MASK, VALUE) (0XFD07026C, 0xFF00FFFFU ,0x08000040U) - RegMask = (DDRC_PERFWR1_W_XACT_RUN_LENGTH_MASK | DDRC_PERFWR1_W_MAX_STARVE_MASK | 0 ); - - RegVal = ((0x00000008U << DDRC_PERFWR1_W_XACT_RUN_LENGTH_SHIFT - | 0x00000040U << DDRC_PERFWR1_W_MAX_STARVE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PERFWR1_OFFSET ,0xFF00FFFFU ,0x08000040U); - /*############################################################################################################################ */ - - /*Register : DQMAP5 @ 0XFD070294

- - All even ranks have the same DQ mapping controled by DQMAP0-4 register as rank 0. This register provides DQ swap function for - all odd ranks to support CRC feature. rank based DQ swapping is: swap bit 0 with 1, swap bit 2 with 3, swap bit 4 with 5 and - wap bit 6 with 7. 1: Disable rank based DQ swapping 0: Enable rank based DQ swapping Present only in designs configured to su - port DDR4. - PSU_DDRC_DQMAP5_DIS_DQ_RANK_SWAP 0x1 - - DQ Map Register 5 - (OFFSET, MASK, VALUE) (0XFD070294, 0x00000001U ,0x00000001U) - RegMask = (DDRC_DQMAP5_DIS_DQ_RANK_SWAP_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_DQMAP5_DIS_DQ_RANK_SWAP_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DQMAP5_OFFSET ,0x00000001U ,0x00000001U); - /*############################################################################################################################ */ - - /*Register : DBG0 @ 0XFD070300

- - When this is set to '0', auto-precharge is disabled for the flushed command in a collision case. Collision cases are write fo - lowed by read to same address, read followed by write to same address, or write followed by write to same address with DBG0.d - s_wc bit = 1 (where same address comparisons exclude the two address bits representing critical word). FOR DEBUG ONLY. - PSU_DDRC_DBG0_DIS_COLLISION_PAGE_OPT 0x0 - - When 1, disable write combine. FOR DEBUG ONLY - PSU_DDRC_DBG0_DIS_WC 0x0 - - Debug Register 0 - (OFFSET, MASK, VALUE) (0XFD070300, 0x00000011U ,0x00000000U) - RegMask = (DDRC_DBG0_DIS_COLLISION_PAGE_OPT_MASK | DDRC_DBG0_DIS_WC_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_DBG0_DIS_COLLISION_PAGE_OPT_SHIFT - | 0x00000000U << DDRC_DBG0_DIS_WC_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DBG0_OFFSET ,0x00000011U ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : DBGCMD @ 0XFD07030C

- - Setting this register bit to 1 allows refresh and ZQCS commands to be triggered from hardware via the IOs ext_*. If set to 1, - the fields DBGCMD.zq_calib_short and DBGCMD.rank*_refresh have no function, and are ignored by the uMCTL2 logic. Setting this - register bit to 0 allows refresh and ZQCS to be triggered from software, via the fields DBGCMD.zq_calib_short and DBGCMD.rank - _refresh. If set to 0, the hardware pins ext_* have no function, and are ignored by the uMCTL2 logic. This register is static - and may only be changed when the DDRC reset signal, core_ddrc_rstn, is asserted (0). - PSU_DDRC_DBGCMD_HW_REF_ZQ_EN 0x0 - - Setting this register bit to 1 indicates to the uMCTL2 to issue a dfi_ctrlupd_req to the PHY. When this request is stored in - he uMCTL2, the bit is automatically cleared. This operation must only be performed when DFIUPD0.dis_auto_ctrlupd=1. - PSU_DDRC_DBGCMD_CTRLUPD 0x0 - - Setting this register bit to 1 indicates to the uMCTL2 to issue a ZQCS (ZQ calibration short)/MPC(ZQ calibration) command to - he SDRAM. When this request is stored in the uMCTL2, the bit is automatically cleared. This operation can be performed only w - en ZQCTL0.dis_auto_zq=1. It is recommended NOT to set this register bit if in Init operating mode. This register bit is ignor - d when in Self-Refresh(except LPDDR4) and SR-Powerdown(LPDDR4) and Deep power-down operating modes and Maximum Power Saving M - de. - PSU_DDRC_DBGCMD_ZQ_CALIB_SHORT 0x0 - - Setting this register bit to 1 indicates to the uMCTL2 to issue a refresh to rank 1. Writing to this bit causes DBGSTAT.rank1 - refresh_busy to be set. When DBGSTAT.rank1_refresh_busy is cleared, the command has been stored in uMCTL2. This operation can - be performed only when RFSHCTL3.dis_auto_refresh=1. It is recommended NOT to set this register bit if in Init or Deep power-d - wn operating modes or Maximum Power Saving Mode. - PSU_DDRC_DBGCMD_RANK1_REFRESH 0x0 - - Setting this register bit to 1 indicates to the uMCTL2 to issue a refresh to rank 0. Writing to this bit causes DBGSTAT.rank0 - refresh_busy to be set. When DBGSTAT.rank0_refresh_busy is cleared, the command has been stored in uMCTL2. This operation can - be performed only when RFSHCTL3.dis_auto_refresh=1. It is recommended NOT to set this register bit if in Init or Deep power-d - wn operating modes or Maximum Power Saving Mode. - PSU_DDRC_DBGCMD_RANK0_REFRESH 0x0 - - Command Debug Register - (OFFSET, MASK, VALUE) (0XFD07030C, 0x80000033U ,0x00000000U) - RegMask = (DDRC_DBGCMD_HW_REF_ZQ_EN_MASK | DDRC_DBGCMD_CTRLUPD_MASK | DDRC_DBGCMD_ZQ_CALIB_SHORT_MASK | DDRC_DBGCMD_RANK1_REFRESH_MASK | DDRC_DBGCMD_RANK0_REFRESH_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_DBGCMD_HW_REF_ZQ_EN_SHIFT - | 0x00000000U << DDRC_DBGCMD_CTRLUPD_SHIFT - | 0x00000000U << DDRC_DBGCMD_ZQ_CALIB_SHORT_SHIFT - | 0x00000000U << DDRC_DBGCMD_RANK1_REFRESH_SHIFT - | 0x00000000U << DDRC_DBGCMD_RANK0_REFRESH_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DBGCMD_OFFSET ,0x80000033U ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : SWCTL @ 0XFD070320

- - Enable quasi-dynamic register programming outside reset. Program register to 0 to enable quasi-dynamic programming. Set back - egister to 1 once programming is done. - PSU_DDRC_SWCTL_SW_DONE 0x0 - - Software register programming control enable - (OFFSET, MASK, VALUE) (0XFD070320, 0x00000001U ,0x00000000U) - RegMask = (DDRC_SWCTL_SW_DONE_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_SWCTL_SW_DONE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_SWCTL_OFFSET ,0x00000001U ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : PCCFG @ 0XFD070400

- - Burst length expansion mode. By default (i.e. bl_exp_mode==0) XPI expands every AXI burst into multiple HIF commands, using t - e memory burst length as a unit. If set to 1, then XPI will use half of the memory burst length as a unit. This applies to bo - h reads and writes. When MSTR.data_bus_width==00, setting bl_exp_mode to 1 has no effect. This can be used in cases where Par - ial Writes is enabled (UMCTL2_PARTIAL_WR=1) and DBG0.dis_wc=1, in order to avoid or minimize t_ccd_l penalty in DDR4 and t_cc - _mw penalty in LPDDR4. Note that if DBICTL.reg_ddrc_dm_en=0, functionality is not supported in the following cases: - UMCTL2_ - ARTIAL_WR=0 - UMCTL2_PARTIAL_WR=1, MSTR.reg_ddrc_data_bus_width=01, MEMC_BURST_LENGTH=8 and MSTR.reg_ddrc_burst_rdwr=1000 (LP - DR4 only) - UMCTL2_PARTIAL_WR=1, MSTR.reg_ddrc_data_bus_width=01, MEMC_BURST_LENGTH=4 and MSTR.reg_ddrc_burst_rdwr=0100 (DDR4 - only), with either MSTR.reg_ddrc_burstchop=0 or CRCPARCTL1.reg_ddrc_crc_enable=1 Functionality is also not supported if Share - -AC is enabled - PSU_DDRC_PCCFG_BL_EXP_MODE 0x0 - - Page match four limit. If set to 1, limits the number of consecutive same page DDRC transactions that can be granted by the P - rt Arbiter to four when Page Match feature is enabled. If set to 0, there is no limit imposed on number of consecutive same p - ge DDRC transactions. - PSU_DDRC_PCCFG_PAGEMATCH_LIMIT 0x0 - - If set to 1 (enabled), sets co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals going to DDRC based - n urgent input (awurgent, arurgent) coming from AXI master. If set to 0 (disabled), co_gs_go2critical_wr and co_gs_go2critica - _lpr/co_gs_go2critical_hpr signals at DDRC are driven to 1b'0. - PSU_DDRC_PCCFG_GO2CRITICAL_EN 0x1 - - Port Common Configuration Register - (OFFSET, MASK, VALUE) (0XFD070400, 0x00000111U ,0x00000001U) - RegMask = (DDRC_PCCFG_BL_EXP_MODE_MASK | DDRC_PCCFG_PAGEMATCH_LIMIT_MASK | DDRC_PCCFG_GO2CRITICAL_EN_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_PCCFG_BL_EXP_MODE_SHIFT - | 0x00000000U << DDRC_PCCFG_PAGEMATCH_LIMIT_SHIFT - | 0x00000001U << DDRC_PCCFG_GO2CRITICAL_EN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCCFG_OFFSET ,0x00000111U ,0x00000001U); - /*############################################################################################################################ */ - - /*Register : PCFGR_0 @ 0XFD070404

- - If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register. - PSU_DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN 0x0 - - If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG. - o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add - ess handshaking (it is not associated with any particular command). - PSU_DDRC_PCFGR_0_RD_PORT_URGENT_EN 0x1 - - If set to 1, enables aging function for the read channel of the port. - PSU_DDRC_PCFGR_0_RD_PORT_AGING_EN 0x0 - - Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g - ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority - will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre - ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the - aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st - ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w - ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D - RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: - he two LSBs of this register field are tied internally to 2'b00. - PSU_DDRC_PCFGR_0_RD_PORT_PRIORITY 0xf - - Port n Configuration Read Register - (OFFSET, MASK, VALUE) (0XFD070404, 0x000073FFU ,0x0000200FU) - RegMask = (DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGR_0_RD_PORT_URGENT_EN_MASK | DDRC_PCFGR_0_RD_PORT_AGING_EN_MASK | DDRC_PCFGR_0_RD_PORT_PRIORITY_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_SHIFT - | 0x00000001U << DDRC_PCFGR_0_RD_PORT_URGENT_EN_SHIFT - | 0x00000000U << DDRC_PCFGR_0_RD_PORT_AGING_EN_SHIFT - | 0x0000000FU << DDRC_PCFGR_0_RD_PORT_PRIORITY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGR_0_OFFSET ,0x000073FFU ,0x0000200FU); - /*############################################################################################################################ */ - - /*Register : PCFGW_0 @ 0XFD070408

- - If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register. - PSU_DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN 0x1 - - If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register - Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is - not associated with any particular command). - PSU_DDRC_PCFGW_0_WR_PORT_URGENT_EN 0x1 - - If set to 1, enables aging function for the write channel of the port. - PSU_DDRC_PCFGW_0_WR_PORT_AGING_EN 0x0 - - Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each - rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port - s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0 - the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno - be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For - ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch - ng. Note: The two LSBs of this register field are tied internally to 2'b00. - PSU_DDRC_PCFGW_0_WR_PORT_PRIORITY 0xf - - Port n Configuration Write Register - (OFFSET, MASK, VALUE) (0XFD070408, 0x000073FFU ,0x0000600FU) - RegMask = (DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGW_0_WR_PORT_URGENT_EN_MASK | DDRC_PCFGW_0_WR_PORT_AGING_EN_MASK | DDRC_PCFGW_0_WR_PORT_PRIORITY_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_SHIFT - | 0x00000001U << DDRC_PCFGW_0_WR_PORT_URGENT_EN_SHIFT - | 0x00000000U << DDRC_PCFGW_0_WR_PORT_AGING_EN_SHIFT - | 0x0000000FU << DDRC_PCFGW_0_WR_PORT_PRIORITY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGW_0_OFFSET ,0x000073FFU ,0x0000600FU); - /*############################################################################################################################ */ - - /*Register : PCTRL_0 @ 0XFD070490

- - Enables port n. - PSU_DDRC_PCTRL_0_PORT_EN 0x1 - - Port n Control Register - (OFFSET, MASK, VALUE) (0XFD070490, 0x00000001U ,0x00000001U) - RegMask = (DDRC_PCTRL_0_PORT_EN_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_PCTRL_0_PORT_EN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCTRL_0_OFFSET ,0x00000001U ,0x00000001U); - /*############################################################################################################################ */ - - /*Register : PCFGQOS0_0 @ 0XFD070494

- - This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf - gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is - disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. - PSU_DDRC_PCFGQOS0_0_RQOS_MAP_REGION1 0x2 - - This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi - urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i - disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. - PSU_DDRC_PCFGQOS0_0_RQOS_MAP_REGION0 0x0 - - Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d - al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio - ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc - values. - PSU_DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1 0xb - - Port n Read QoS Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD070494, 0x0033000FU ,0x0020000BU) - RegMask = (DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_MASK | DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_MASK | DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_MASK | 0 ); - - RegVal = ((0x00000002U << DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_SHIFT - | 0x00000000U << DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_SHIFT - | 0x0000000BU << DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGQOS0_0_OFFSET ,0x0033000FU ,0x0020000BU); - /*############################################################################################################################ */ - - /*Register : PCFGQOS1_0 @ 0XFD070498

- - Specifies the timeout value for transactions mapped to the red address queue. - PSU_DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR 0x0 - - Specifies the timeout value for transactions mapped to the blue address queue. - PSU_DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB 0x0 - - Port n Read QoS Configuration Register 1 - (OFFSET, MASK, VALUE) (0XFD070498, 0x07FF07FFU ,0x00000000U) - RegMask = (DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_MASK | DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_SHIFT - | 0x00000000U << DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGQOS1_0_OFFSET ,0x07FF07FFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : PCFGR_1 @ 0XFD0704B4

- - If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register. - PSU_DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN 0x0 - - If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG. - o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add - ess handshaking (it is not associated with any particular command). - PSU_DDRC_PCFGR_1_RD_PORT_URGENT_EN 0x1 - - If set to 1, enables aging function for the read channel of the port. - PSU_DDRC_PCFGR_1_RD_PORT_AGING_EN 0x0 - - Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g - ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority - will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre - ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the - aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st - ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w - ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D - RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: - he two LSBs of this register field are tied internally to 2'b00. - PSU_DDRC_PCFGR_1_RD_PORT_PRIORITY 0xf - - Port n Configuration Read Register - (OFFSET, MASK, VALUE) (0XFD0704B4, 0x000073FFU ,0x0000200FU) - RegMask = (DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGR_1_RD_PORT_URGENT_EN_MASK | DDRC_PCFGR_1_RD_PORT_AGING_EN_MASK | DDRC_PCFGR_1_RD_PORT_PRIORITY_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_SHIFT - | 0x00000001U << DDRC_PCFGR_1_RD_PORT_URGENT_EN_SHIFT - | 0x00000000U << DDRC_PCFGR_1_RD_PORT_AGING_EN_SHIFT - | 0x0000000FU << DDRC_PCFGR_1_RD_PORT_PRIORITY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGR_1_OFFSET ,0x000073FFU ,0x0000200FU); - /*############################################################################################################################ */ - - /*Register : PCFGW_1 @ 0XFD0704B8

- - If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register. - PSU_DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN 0x1 - - If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register - Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is - not associated with any particular command). - PSU_DDRC_PCFGW_1_WR_PORT_URGENT_EN 0x1 - - If set to 1, enables aging function for the write channel of the port. - PSU_DDRC_PCFGW_1_WR_PORT_AGING_EN 0x0 - - Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each - rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port - s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0 - the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno - be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For - ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch - ng. Note: The two LSBs of this register field are tied internally to 2'b00. - PSU_DDRC_PCFGW_1_WR_PORT_PRIORITY 0xf - - Port n Configuration Write Register - (OFFSET, MASK, VALUE) (0XFD0704B8, 0x000073FFU ,0x0000600FU) - RegMask = (DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGW_1_WR_PORT_URGENT_EN_MASK | DDRC_PCFGW_1_WR_PORT_AGING_EN_MASK | DDRC_PCFGW_1_WR_PORT_PRIORITY_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_SHIFT - | 0x00000001U << DDRC_PCFGW_1_WR_PORT_URGENT_EN_SHIFT - | 0x00000000U << DDRC_PCFGW_1_WR_PORT_AGING_EN_SHIFT - | 0x0000000FU << DDRC_PCFGW_1_WR_PORT_PRIORITY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGW_1_OFFSET ,0x000073FFU ,0x0000600FU); - /*############################################################################################################################ */ - - /*Register : PCTRL_1 @ 0XFD070540

- - Enables port n. - PSU_DDRC_PCTRL_1_PORT_EN 0x1 - - Port n Control Register - (OFFSET, MASK, VALUE) (0XFD070540, 0x00000001U ,0x00000001U) - RegMask = (DDRC_PCTRL_1_PORT_EN_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_PCTRL_1_PORT_EN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCTRL_1_OFFSET ,0x00000001U ,0x00000001U); - /*############################################################################################################################ */ - - /*Register : PCFGQOS0_1 @ 0XFD070544

- - This bitfield indicates the traffic class of region2. For dual address queue configurations, region2 maps to the red address - ueue. Valid values are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and traffic class of region2 - s set to 1 (VPR), VPR traffic is aliased to LPR traffic. - PSU_DDRC_PCFGQOS0_1_RQOS_MAP_REGION2 0x2 - - This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf - gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is - disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. - PSU_DDRC_PCFGQOS0_1_RQOS_MAP_REGION1 0x0 - - This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi - urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i - disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. - PSU_DDRC_PCFGQOS0_1_RQOS_MAP_REGION0 0x0 - - Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (le - el1 + 1) to 14 which corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note that for PA, arqos values are used - directly as port priorities, where the higher the value corresponds to higher port priority. All of the map_level* registers - ust be set to distinct values. - PSU_DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2 0xb - - Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d - al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio - ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc - values. - PSU_DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1 0x3 - - Port n Read QoS Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD070544, 0x03330F0FU ,0x02000B03U) - RegMask = (DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_MASK | DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_MASK | DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_MASK | DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_MASK | DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_MASK | 0 ); - - RegVal = ((0x00000002U << DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_SHIFT - | 0x00000000U << DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_SHIFT - | 0x00000000U << DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_SHIFT - | 0x0000000BU << DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_SHIFT - | 0x00000003U << DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGQOS0_1_OFFSET ,0x03330F0FU ,0x02000B03U); - /*############################################################################################################################ */ - - /*Register : PCFGQOS1_1 @ 0XFD070548

- - Specifies the timeout value for transactions mapped to the red address queue. - PSU_DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR 0x0 - - Specifies the timeout value for transactions mapped to the blue address queue. - PSU_DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB 0x0 - - Port n Read QoS Configuration Register 1 - (OFFSET, MASK, VALUE) (0XFD070548, 0x07FF07FFU ,0x00000000U) - RegMask = (DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_MASK | DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_SHIFT - | 0x00000000U << DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGQOS1_1_OFFSET ,0x07FF07FFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : PCFGR_2 @ 0XFD070564

- - If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register. - PSU_DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN 0x0 - - If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG. - o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add - ess handshaking (it is not associated with any particular command). - PSU_DDRC_PCFGR_2_RD_PORT_URGENT_EN 0x1 - - If set to 1, enables aging function for the read channel of the port. - PSU_DDRC_PCFGR_2_RD_PORT_AGING_EN 0x0 - - Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g - ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority - will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre - ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the - aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st - ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w - ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D - RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: - he two LSBs of this register field are tied internally to 2'b00. - PSU_DDRC_PCFGR_2_RD_PORT_PRIORITY 0xf - - Port n Configuration Read Register - (OFFSET, MASK, VALUE) (0XFD070564, 0x000073FFU ,0x0000200FU) - RegMask = (DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGR_2_RD_PORT_URGENT_EN_MASK | DDRC_PCFGR_2_RD_PORT_AGING_EN_MASK | DDRC_PCFGR_2_RD_PORT_PRIORITY_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_SHIFT - | 0x00000001U << DDRC_PCFGR_2_RD_PORT_URGENT_EN_SHIFT - | 0x00000000U << DDRC_PCFGR_2_RD_PORT_AGING_EN_SHIFT - | 0x0000000FU << DDRC_PCFGR_2_RD_PORT_PRIORITY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGR_2_OFFSET ,0x000073FFU ,0x0000200FU); - /*############################################################################################################################ */ - - /*Register : PCFGW_2 @ 0XFD070568

- - If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register. - PSU_DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN 0x1 - - If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register - Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is - not associated with any particular command). - PSU_DDRC_PCFGW_2_WR_PORT_URGENT_EN 0x1 - - If set to 1, enables aging function for the write channel of the port. - PSU_DDRC_PCFGW_2_WR_PORT_AGING_EN 0x0 - - Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each - rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port - s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0 - the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno - be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For - ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch - ng. Note: The two LSBs of this register field are tied internally to 2'b00. - PSU_DDRC_PCFGW_2_WR_PORT_PRIORITY 0xf - - Port n Configuration Write Register - (OFFSET, MASK, VALUE) (0XFD070568, 0x000073FFU ,0x0000600FU) - RegMask = (DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGW_2_WR_PORT_URGENT_EN_MASK | DDRC_PCFGW_2_WR_PORT_AGING_EN_MASK | DDRC_PCFGW_2_WR_PORT_PRIORITY_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_SHIFT - | 0x00000001U << DDRC_PCFGW_2_WR_PORT_URGENT_EN_SHIFT - | 0x00000000U << DDRC_PCFGW_2_WR_PORT_AGING_EN_SHIFT - | 0x0000000FU << DDRC_PCFGW_2_WR_PORT_PRIORITY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGW_2_OFFSET ,0x000073FFU ,0x0000600FU); - /*############################################################################################################################ */ - - /*Register : PCTRL_2 @ 0XFD0705F0

- - Enables port n. - PSU_DDRC_PCTRL_2_PORT_EN 0x1 - - Port n Control Register - (OFFSET, MASK, VALUE) (0XFD0705F0, 0x00000001U ,0x00000001U) - RegMask = (DDRC_PCTRL_2_PORT_EN_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_PCTRL_2_PORT_EN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCTRL_2_OFFSET ,0x00000001U ,0x00000001U); - /*############################################################################################################################ */ - - /*Register : PCFGQOS0_2 @ 0XFD0705F4

- - This bitfield indicates the traffic class of region2. For dual address queue configurations, region2 maps to the red address - ueue. Valid values are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and traffic class of region2 - s set to 1 (VPR), VPR traffic is aliased to LPR traffic. - PSU_DDRC_PCFGQOS0_2_RQOS_MAP_REGION2 0x2 - - This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf - gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is - disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. - PSU_DDRC_PCFGQOS0_2_RQOS_MAP_REGION1 0x0 - - This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi - urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i - disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. - PSU_DDRC_PCFGQOS0_2_RQOS_MAP_REGION0 0x0 - - Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (le - el1 + 1) to 14 which corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note that for PA, arqos values are used - directly as port priorities, where the higher the value corresponds to higher port priority. All of the map_level* registers - ust be set to distinct values. - PSU_DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2 0xb - - Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d - al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio - ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc - values. - PSU_DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1 0x3 - - Port n Read QoS Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD0705F4, 0x03330F0FU ,0x02000B03U) - RegMask = (DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_MASK | DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_MASK | DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_MASK | DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_MASK | DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_MASK | 0 ); - - RegVal = ((0x00000002U << DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_SHIFT - | 0x00000000U << DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_SHIFT - | 0x00000000U << DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_SHIFT - | 0x0000000BU << DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_SHIFT - | 0x00000003U << DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGQOS0_2_OFFSET ,0x03330F0FU ,0x02000B03U); - /*############################################################################################################################ */ - - /*Register : PCFGQOS1_2 @ 0XFD0705F8

- - Specifies the timeout value for transactions mapped to the red address queue. - PSU_DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR 0x0 - - Specifies the timeout value for transactions mapped to the blue address queue. - PSU_DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB 0x0 - - Port n Read QoS Configuration Register 1 - (OFFSET, MASK, VALUE) (0XFD0705F8, 0x07FF07FFU ,0x00000000U) - RegMask = (DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_MASK | DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_SHIFT - | 0x00000000U << DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGQOS1_2_OFFSET ,0x07FF07FFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : PCFGR_3 @ 0XFD070614

- - If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register. - PSU_DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN 0x0 - - If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG. - o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add - ess handshaking (it is not associated with any particular command). - PSU_DDRC_PCFGR_3_RD_PORT_URGENT_EN 0x1 - - If set to 1, enables aging function for the read channel of the port. - PSU_DDRC_PCFGR_3_RD_PORT_AGING_EN 0x0 - - Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g - ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority - will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre - ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the - aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st - ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w - ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D - RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: - he two LSBs of this register field are tied internally to 2'b00. - PSU_DDRC_PCFGR_3_RD_PORT_PRIORITY 0xf - - Port n Configuration Read Register - (OFFSET, MASK, VALUE) (0XFD070614, 0x000073FFU ,0x0000200FU) - RegMask = (DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGR_3_RD_PORT_URGENT_EN_MASK | DDRC_PCFGR_3_RD_PORT_AGING_EN_MASK | DDRC_PCFGR_3_RD_PORT_PRIORITY_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_SHIFT - | 0x00000001U << DDRC_PCFGR_3_RD_PORT_URGENT_EN_SHIFT - | 0x00000000U << DDRC_PCFGR_3_RD_PORT_AGING_EN_SHIFT - | 0x0000000FU << DDRC_PCFGR_3_RD_PORT_PRIORITY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGR_3_OFFSET ,0x000073FFU ,0x0000200FU); - /*############################################################################################################################ */ - - /*Register : PCFGW_3 @ 0XFD070618

- - If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register. - PSU_DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN 0x1 - - If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register - Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is - not associated with any particular command). - PSU_DDRC_PCFGW_3_WR_PORT_URGENT_EN 0x1 - - If set to 1, enables aging function for the write channel of the port. - PSU_DDRC_PCFGW_3_WR_PORT_AGING_EN 0x0 - - Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each - rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port - s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0 - the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno - be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For - ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch - ng. Note: The two LSBs of this register field are tied internally to 2'b00. - PSU_DDRC_PCFGW_3_WR_PORT_PRIORITY 0xf - - Port n Configuration Write Register - (OFFSET, MASK, VALUE) (0XFD070618, 0x000073FFU ,0x0000600FU) - RegMask = (DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGW_3_WR_PORT_URGENT_EN_MASK | DDRC_PCFGW_3_WR_PORT_AGING_EN_MASK | DDRC_PCFGW_3_WR_PORT_PRIORITY_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_SHIFT - | 0x00000001U << DDRC_PCFGW_3_WR_PORT_URGENT_EN_SHIFT - | 0x00000000U << DDRC_PCFGW_3_WR_PORT_AGING_EN_SHIFT - | 0x0000000FU << DDRC_PCFGW_3_WR_PORT_PRIORITY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGW_3_OFFSET ,0x000073FFU ,0x0000600FU); - /*############################################################################################################################ */ - - /*Register : PCTRL_3 @ 0XFD0706A0

- - Enables port n. - PSU_DDRC_PCTRL_3_PORT_EN 0x1 - - Port n Control Register - (OFFSET, MASK, VALUE) (0XFD0706A0, 0x00000001U ,0x00000001U) - RegMask = (DDRC_PCTRL_3_PORT_EN_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_PCTRL_3_PORT_EN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCTRL_3_OFFSET ,0x00000001U ,0x00000001U); - /*############################################################################################################################ */ - - /*Register : PCFGQOS0_3 @ 0XFD0706A4

- - This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf - gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is - disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. - PSU_DDRC_PCFGQOS0_3_RQOS_MAP_REGION1 0x1 - - This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi - urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i - disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. - PSU_DDRC_PCFGQOS0_3_RQOS_MAP_REGION0 0x0 - - Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d - al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio - ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc - values. - PSU_DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1 0x3 - - Port n Read QoS Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD0706A4, 0x0033000FU ,0x00100003U) - RegMask = (DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_MASK | DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_MASK | DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_SHIFT - | 0x00000000U << DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_SHIFT - | 0x00000003U << DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGQOS0_3_OFFSET ,0x0033000FU ,0x00100003U); - /*############################################################################################################################ */ - - /*Register : PCFGQOS1_3 @ 0XFD0706A8

- - Specifies the timeout value for transactions mapped to the red address queue. - PSU_DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR 0x0 - - Specifies the timeout value for transactions mapped to the blue address queue. - PSU_DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB 0x4f - - Port n Read QoS Configuration Register 1 - (OFFSET, MASK, VALUE) (0XFD0706A8, 0x07FF07FFU ,0x0000004FU) - RegMask = (DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_MASK | DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_SHIFT - | 0x0000004FU << DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGQOS1_3_OFFSET ,0x07FF07FFU ,0x0000004FU); - /*############################################################################################################################ */ - - /*Register : PCFGWQOS0_3 @ 0XFD0706AC

- - This bitfield indicates the traffic class of region 1. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2 - VPW_EN = 0) and traffic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW traffic. - PSU_DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1 0x1 - - This bitfield indicates the traffic class of region 0. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2 - VPW_EN = 0) and traffic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW traffic. - PSU_DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0 0x0 - - Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 14 which c - rresponds to awqos. Note that for PA, awqos values are used directly as port priorities, where the higher the value correspon - s to higher port priority. - PSU_DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL 0x3 - - Port n Write QoS Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD0706AC, 0x0033000FU ,0x00100003U) - RegMask = (DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_MASK | DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_MASK | DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_SHIFT - | 0x00000000U << DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_SHIFT - | 0x00000003U << DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGWQOS0_3_OFFSET ,0x0033000FU ,0x00100003U); - /*############################################################################################################################ */ - - /*Register : PCFGWQOS1_3 @ 0XFD0706B0

- - Specifies the timeout value for write transactions. - PSU_DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT 0x4f - - Port n Write QoS Configuration Register 1 - (OFFSET, MASK, VALUE) (0XFD0706B0, 0x000007FFU ,0x0000004FU) - RegMask = (DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_MASK | 0 ); - - RegVal = ((0x0000004FU << DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGWQOS1_3_OFFSET ,0x000007FFU ,0x0000004FU); - /*############################################################################################################################ */ - - /*Register : PCFGR_4 @ 0XFD0706C4

- - If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register. - PSU_DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN 0x1 - - If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG. - o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add - ess handshaking (it is not associated with any particular command). - PSU_DDRC_PCFGR_4_RD_PORT_URGENT_EN 0x1 - - If set to 1, enables aging function for the read channel of the port. - PSU_DDRC_PCFGR_4_RD_PORT_AGING_EN 0x0 - - Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g - ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority - will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre - ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the - aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st - ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w - ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D - RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: - he two LSBs of this register field are tied internally to 2'b00. - PSU_DDRC_PCFGR_4_RD_PORT_PRIORITY 0xf - - Port n Configuration Read Register - (OFFSET, MASK, VALUE) (0XFD0706C4, 0x000073FFU ,0x0000600FU) - RegMask = (DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGR_4_RD_PORT_URGENT_EN_MASK | DDRC_PCFGR_4_RD_PORT_AGING_EN_MASK | DDRC_PCFGR_4_RD_PORT_PRIORITY_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_SHIFT - | 0x00000001U << DDRC_PCFGR_4_RD_PORT_URGENT_EN_SHIFT - | 0x00000000U << DDRC_PCFGR_4_RD_PORT_AGING_EN_SHIFT - | 0x0000000FU << DDRC_PCFGR_4_RD_PORT_PRIORITY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGR_4_OFFSET ,0x000073FFU ,0x0000600FU); - /*############################################################################################################################ */ - - /*Register : PCFGW_4 @ 0XFD0706C8

- - If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register. - PSU_DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN 0x1 - - If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register - Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is - not associated with any particular command). - PSU_DDRC_PCFGW_4_WR_PORT_URGENT_EN 0x1 - - If set to 1, enables aging function for the write channel of the port. - PSU_DDRC_PCFGW_4_WR_PORT_AGING_EN 0x0 - - Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each - rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port - s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0 - the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno - be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For - ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch - ng. Note: The two LSBs of this register field are tied internally to 2'b00. - PSU_DDRC_PCFGW_4_WR_PORT_PRIORITY 0xf - - Port n Configuration Write Register - (OFFSET, MASK, VALUE) (0XFD0706C8, 0x000073FFU ,0x0000600FU) - RegMask = (DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGW_4_WR_PORT_URGENT_EN_MASK | DDRC_PCFGW_4_WR_PORT_AGING_EN_MASK | DDRC_PCFGW_4_WR_PORT_PRIORITY_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_SHIFT - | 0x00000001U << DDRC_PCFGW_4_WR_PORT_URGENT_EN_SHIFT - | 0x00000000U << DDRC_PCFGW_4_WR_PORT_AGING_EN_SHIFT - | 0x0000000FU << DDRC_PCFGW_4_WR_PORT_PRIORITY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGW_4_OFFSET ,0x000073FFU ,0x0000600FU); - /*############################################################################################################################ */ - - /*Register : PCTRL_4 @ 0XFD070750

- - Enables port n. - PSU_DDRC_PCTRL_4_PORT_EN 0x1 - - Port n Control Register - (OFFSET, MASK, VALUE) (0XFD070750, 0x00000001U ,0x00000001U) - RegMask = (DDRC_PCTRL_4_PORT_EN_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_PCTRL_4_PORT_EN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCTRL_4_OFFSET ,0x00000001U ,0x00000001U); - /*############################################################################################################################ */ - - /*Register : PCFGQOS0_4 @ 0XFD070754

- - This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf - gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is - disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. - PSU_DDRC_PCFGQOS0_4_RQOS_MAP_REGION1 0x1 - - This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi - urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i - disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. - PSU_DDRC_PCFGQOS0_4_RQOS_MAP_REGION0 0x0 - - Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d - al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio - ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc - values. - PSU_DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1 0x3 - - Port n Read QoS Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD070754, 0x0033000FU ,0x00100003U) - RegMask = (DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_MASK | DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_MASK | DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_SHIFT - | 0x00000000U << DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_SHIFT - | 0x00000003U << DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGQOS0_4_OFFSET ,0x0033000FU ,0x00100003U); - /*############################################################################################################################ */ - - /*Register : PCFGQOS1_4 @ 0XFD070758

- - Specifies the timeout value for transactions mapped to the red address queue. - PSU_DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR 0x0 - - Specifies the timeout value for transactions mapped to the blue address queue. - PSU_DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB 0x4f - - Port n Read QoS Configuration Register 1 - (OFFSET, MASK, VALUE) (0XFD070758, 0x07FF07FFU ,0x0000004FU) - RegMask = (DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_MASK | DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_SHIFT - | 0x0000004FU << DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGQOS1_4_OFFSET ,0x07FF07FFU ,0x0000004FU); - /*############################################################################################################################ */ - - /*Register : PCFGWQOS0_4 @ 0XFD07075C

- - This bitfield indicates the traffic class of region 1. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2 - VPW_EN = 0) and traffic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW traffic. - PSU_DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1 0x1 - - This bitfield indicates the traffic class of region 0. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2 - VPW_EN = 0) and traffic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW traffic. - PSU_DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0 0x0 - - Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 14 which c - rresponds to awqos. Note that for PA, awqos values are used directly as port priorities, where the higher the value correspon - s to higher port priority. - PSU_DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL 0x3 - - Port n Write QoS Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD07075C, 0x0033000FU ,0x00100003U) - RegMask = (DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_MASK | DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_MASK | DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_SHIFT - | 0x00000000U << DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_SHIFT - | 0x00000003U << DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGWQOS0_4_OFFSET ,0x0033000FU ,0x00100003U); - /*############################################################################################################################ */ - - /*Register : PCFGWQOS1_4 @ 0XFD070760

- - Specifies the timeout value for write transactions. - PSU_DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT 0x4f - - Port n Write QoS Configuration Register 1 - (OFFSET, MASK, VALUE) (0XFD070760, 0x000007FFU ,0x0000004FU) - RegMask = (DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_MASK | 0 ); - - RegVal = ((0x0000004FU << DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGWQOS1_4_OFFSET ,0x000007FFU ,0x0000004FU); - /*############################################################################################################################ */ - - /*Register : PCFGR_5 @ 0XFD070774

- - If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register. - PSU_DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN 0x0 - - If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG. - o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add - ess handshaking (it is not associated with any particular command). - PSU_DDRC_PCFGR_5_RD_PORT_URGENT_EN 0x1 - - If set to 1, enables aging function for the read channel of the port. - PSU_DDRC_PCFGR_5_RD_PORT_AGING_EN 0x0 - - Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g - ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority - will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre - ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the - aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st - ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w - ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D - RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: - he two LSBs of this register field are tied internally to 2'b00. - PSU_DDRC_PCFGR_5_RD_PORT_PRIORITY 0xf - - Port n Configuration Read Register - (OFFSET, MASK, VALUE) (0XFD070774, 0x000073FFU ,0x0000200FU) - RegMask = (DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGR_5_RD_PORT_URGENT_EN_MASK | DDRC_PCFGR_5_RD_PORT_AGING_EN_MASK | DDRC_PCFGR_5_RD_PORT_PRIORITY_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_SHIFT - | 0x00000001U << DDRC_PCFGR_5_RD_PORT_URGENT_EN_SHIFT - | 0x00000000U << DDRC_PCFGR_5_RD_PORT_AGING_EN_SHIFT - | 0x0000000FU << DDRC_PCFGR_5_RD_PORT_PRIORITY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGR_5_OFFSET ,0x000073FFU ,0x0000200FU); - /*############################################################################################################################ */ - - /*Register : PCFGW_5 @ 0XFD070778

- - If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register. - PSU_DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN 0x1 - - If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register - Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is - not associated with any particular command). - PSU_DDRC_PCFGW_5_WR_PORT_URGENT_EN 0x1 - - If set to 1, enables aging function for the write channel of the port. - PSU_DDRC_PCFGW_5_WR_PORT_AGING_EN 0x0 - - Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each - rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port - s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0 - the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno - be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For - ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch - ng. Note: The two LSBs of this register field are tied internally to 2'b00. - PSU_DDRC_PCFGW_5_WR_PORT_PRIORITY 0xf - - Port n Configuration Write Register - (OFFSET, MASK, VALUE) (0XFD070778, 0x000073FFU ,0x0000600FU) - RegMask = (DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGW_5_WR_PORT_URGENT_EN_MASK | DDRC_PCFGW_5_WR_PORT_AGING_EN_MASK | DDRC_PCFGW_5_WR_PORT_PRIORITY_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_SHIFT - | 0x00000001U << DDRC_PCFGW_5_WR_PORT_URGENT_EN_SHIFT - | 0x00000000U << DDRC_PCFGW_5_WR_PORT_AGING_EN_SHIFT - | 0x0000000FU << DDRC_PCFGW_5_WR_PORT_PRIORITY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGW_5_OFFSET ,0x000073FFU ,0x0000600FU); - /*############################################################################################################################ */ - - /*Register : PCTRL_5 @ 0XFD070800

- - Enables port n. - PSU_DDRC_PCTRL_5_PORT_EN 0x1 - - Port n Control Register - (OFFSET, MASK, VALUE) (0XFD070800, 0x00000001U ,0x00000001U) - RegMask = (DDRC_PCTRL_5_PORT_EN_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_PCTRL_5_PORT_EN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCTRL_5_OFFSET ,0x00000001U ,0x00000001U); - /*############################################################################################################################ */ - - /*Register : PCFGQOS0_5 @ 0XFD070804

- - This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf - gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is - disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. - PSU_DDRC_PCFGQOS0_5_RQOS_MAP_REGION1 0x1 - - This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi - urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i - disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. - PSU_DDRC_PCFGQOS0_5_RQOS_MAP_REGION0 0x0 - - Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d - al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio - ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc - values. - PSU_DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1 0x3 - - Port n Read QoS Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD070804, 0x0033000FU ,0x00100003U) - RegMask = (DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_MASK | DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_MASK | DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_SHIFT - | 0x00000000U << DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_SHIFT - | 0x00000003U << DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGQOS0_5_OFFSET ,0x0033000FU ,0x00100003U); - /*############################################################################################################################ */ - - /*Register : PCFGQOS1_5 @ 0XFD070808

- - Specifies the timeout value for transactions mapped to the red address queue. - PSU_DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR 0x0 - - Specifies the timeout value for transactions mapped to the blue address queue. - PSU_DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB 0x4f - - Port n Read QoS Configuration Register 1 - (OFFSET, MASK, VALUE) (0XFD070808, 0x07FF07FFU ,0x0000004FU) - RegMask = (DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_MASK | DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_SHIFT - | 0x0000004FU << DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGQOS1_5_OFFSET ,0x07FF07FFU ,0x0000004FU); - /*############################################################################################################################ */ - - /*Register : PCFGWQOS0_5 @ 0XFD07080C

- - This bitfield indicates the traffic class of region 1. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2 - VPW_EN = 0) and traffic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW traffic. - PSU_DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1 0x1 - - This bitfield indicates the traffic class of region 0. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2 - VPW_EN = 0) and traffic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW traffic. - PSU_DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0 0x0 - - Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 14 which c - rresponds to awqos. Note that for PA, awqos values are used directly as port priorities, where the higher the value correspon - s to higher port priority. - PSU_DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL 0x3 - - Port n Write QoS Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD07080C, 0x0033000FU ,0x00100003U) - RegMask = (DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_MASK | DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_MASK | DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_SHIFT - | 0x00000000U << DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_SHIFT - | 0x00000003U << DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGWQOS0_5_OFFSET ,0x0033000FU ,0x00100003U); - /*############################################################################################################################ */ - - /*Register : PCFGWQOS1_5 @ 0XFD070810

- - Specifies the timeout value for write transactions. - PSU_DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT 0x4f - - Port n Write QoS Configuration Register 1 - (OFFSET, MASK, VALUE) (0XFD070810, 0x000007FFU ,0x0000004FU) - RegMask = (DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_MASK | 0 ); - - RegVal = ((0x0000004FU << DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGWQOS1_5_OFFSET ,0x000007FFU ,0x0000004FU); - /*############################################################################################################################ */ - - /*Register : SARBASE0 @ 0XFD070F04

- - Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x] and araddr[UMCTL2_A_ADDRW-1:x] where x is determine - by the minimum block size parameter UMCTL2_SARMINSIZE: (x=log2(block size)). - PSU_DDRC_SARBASE0_BASE_ADDR 0x0 - - SAR Base Address Register n - (OFFSET, MASK, VALUE) (0XFD070F04, 0x000001FFU ,0x00000000U) - RegMask = (DDRC_SARBASE0_BASE_ADDR_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_SARBASE0_BASE_ADDR_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_SARBASE0_OFFSET ,0x000001FFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : SARSIZE0 @ 0XFD070F08

- - Number of blocks for address region n. This register determines the total size of the region in multiples of minimum block si - e as specified by the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded as number of blocks = nblocks + 1. - or example, if register is programmed to 0, region will have 1 block. - PSU_DDRC_SARSIZE0_NBLOCKS 0x0 - - SAR Size Register n - (OFFSET, MASK, VALUE) (0XFD070F08, 0x000000FFU ,0x00000000U) - RegMask = (DDRC_SARSIZE0_NBLOCKS_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_SARSIZE0_NBLOCKS_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_SARSIZE0_OFFSET ,0x000000FFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : SARBASE1 @ 0XFD070F0C

- - Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x] and araddr[UMCTL2_A_ADDRW-1:x] where x is determine - by the minimum block size parameter UMCTL2_SARMINSIZE: (x=log2(block size)). - PSU_DDRC_SARBASE1_BASE_ADDR 0x10 - - SAR Base Address Register n - (OFFSET, MASK, VALUE) (0XFD070F0C, 0x000001FFU ,0x00000010U) - RegMask = (DDRC_SARBASE1_BASE_ADDR_MASK | 0 ); - - RegVal = ((0x00000010U << DDRC_SARBASE1_BASE_ADDR_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_SARBASE1_OFFSET ,0x000001FFU ,0x00000010U); - /*############################################################################################################################ */ - - /*Register : SARSIZE1 @ 0XFD070F10

- - Number of blocks for address region n. This register determines the total size of the region in multiples of minimum block si - e as specified by the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded as number of blocks = nblocks + 1. - or example, if register is programmed to 0, region will have 1 block. - PSU_DDRC_SARSIZE1_NBLOCKS 0xf - - SAR Size Register n - (OFFSET, MASK, VALUE) (0XFD070F10, 0x000000FFU ,0x0000000FU) - RegMask = (DDRC_SARSIZE1_NBLOCKS_MASK | 0 ); +unsigned long psu_ddr_init_data(void) +{ + /* + * DDR INITIALIZATION + */ + /* + * DDR CONTROLLER RESET + */ + /* + * Register : RST_DDR_SS @ 0XFD1A0108 + + * DDR block level reset inside of the DDR Sub System + * PSU_CRF_APB_RST_DDR_SS_DDR_RESET 0X1 + + * DDR sub system block level reset + * (OFFSET, MASK, VALUE) (0XFD1A0108, 0x00000008U ,0x00000008U) + */ + PSU_Mask_Write(CRF_APB_RST_DDR_SS_OFFSET, 0x00000008U, 0x00000008U); +/*##################################################################### */ + + /* + * Register : MSTR @ 0XFD070000 + + * Indicates the configuration of the device used in the system. - 00 - x4 + * device - 01 - x8 device - 10 - x16 device - 11 - x32 device + * PSU_DDRC_MSTR_DEVICE_CONFIG 0x1 + + * Choose which registers are used. - 0 - Original registers - 1 - Shadow r + * egisters + * PSU_DDRC_MSTR_FREQUENCY_MODE 0x0 + + * Only present for multi-rank configurations. Each bit represents one rank + * . For two-rank configurations, only bits[25:24] are present. - 1 - popul + * ated - 0 - unpopulated LSB is the lowest rank number. For 2 ranks follow + * ing combinations are legal: - 01 - One rank - 11 - Two ranks - Others - + * Reserved. For 4 ranks following combinations are legal: - 0001 - One ran + * k - 0011 - Two ranks - 1111 - Four ranks + * PSU_DDRC_MSTR_ACTIVE_RANKS 0x1 + + * SDRAM burst length used: - 0001 - Burst length of 2 (only supported for + * mDDR) - 0010 - Burst length of 4 - 0100 - Burst length of 8 - 1000 - Bur + * st length of 16 (only supported for mDDR, LPDDR2, and LPDDR4) All other + * values are reserved. This controls the burst size used to access the SDR + * AM. This must match the burst length mode register setting in the SDRAM. + * (For BC4/8 on-the-fly mode of DDR3 and DDR4, set this field to 0x0100) + * Burst length of 2 is not supported with AXI ports when MEMC_BURST_LENGTH + * is 8. Burst length of 2 is only supported with MEMC_FREQ_RATIO = 1 + * PSU_DDRC_MSTR_BURST_RDWR 0x4 + + * Set to 1 when the uMCTL2 and DRAM has to be put in DLL-off mode for low + * frequency operation. Set to 0 to put uMCTL2 and DRAM in DLL-on mode for + * normal frequency operation. If DDR4 CRC/parity retry is enabled (CRCPARC + * TL1.crc_parity_retry_enable = 1), dll_off_mode is not supported, and thi + * s bit must be set to '0'. + * PSU_DDRC_MSTR_DLL_OFF_MODE 0x0 + + * Selects proportion of DQ bus width that is used by the SDRAM - 00 - Full + * DQ bus width to SDRAM - 01 - Half DQ bus width to SDRAM - 10 - Quarter + * DQ bus width to SDRAM - 11 - Reserved. Note that half bus width mode is + * only supported when the SDRAM bus width is a multiple of 16, and quarter + * bus width mode is only supported when the SDRAM bus width is a multiple + * of 32 and the configuration parameter MEMC_QBUS_SUPPORT is set. Bus wid + * th refers to DQ bus width (excluding any ECC width). + * PSU_DDRC_MSTR_DATA_BUS_WIDTH 0x0 + + * 1 indicates put the DRAM in geardown mode (2N) and 0 indicates put the D + * RAM in normal mode (1N). This register can be changed, only when the Con + * troller is in self-refresh mode. This signal must be set the same value + * as MR3 bit A3. Note: Geardown mode is not supported if the configuration + * parameter MEMC_CMD_RTN2IDLE is set + * PSU_DDRC_MSTR_GEARDOWN_MODE 0x0 + + * If 1, then uMCTL2 uses 2T timing. Otherwise, uses 1T timing. In 2T timin + * g, all command signals (except chip select) are held for 2 clocks on the + * SDRAM bus. Chip select is asserted on the second cycle of the command N + * ote: 2T timing is not supported in LPDDR2/LPDDR3/LPDDR4 mode Note: 2T ti + * ming is not supported if the configuration parameter MEMC_CMD_RTN2IDLE i + * s set Note: 2T timing is not supported in DDR4 geardown mode. + * PSU_DDRC_MSTR_EN_2T_TIMING_MODE 0x0 + + * When set, enable burst-chop in DDR3/DDR4. Burst Chop for Reads is exerci + * sed only in HIF configurations (UMCTL2_INCL_ARB not set) and if in full + * bus width mode (MSTR.data_bus_width = 00). Burst Chop for Writes is exer + * cised only if Partial Writes enabled (UMCTL2_PARTIAL_WR=1) and if CRC is + * disabled (CRCPARCTL1.crc_enable = 0). If DDR4 CRC/parity retry is enabl + * ed (CRCPARCTL1.crc_parity_retry_enable = 1), burst chop is not supported + * , and this bit must be set to '0' + * PSU_DDRC_MSTR_BURSTCHOP 0x0 + + * Select LPDDR4 SDRAM - 1 - LPDDR4 SDRAM device in use. - 0 - non-LPDDR4 d + * evice in use Present only in designs configured to support LPDDR4. + * PSU_DDRC_MSTR_LPDDR4 0x0 + + * Select DDR4 SDRAM - 1 - DDR4 SDRAM device in use. - 0 - non-DDR4 device + * in use Present only in designs configured to support DDR4. + * PSU_DDRC_MSTR_DDR4 0x1 + + * Select LPDDR3 SDRAM - 1 - LPDDR3 SDRAM device in use. - 0 - non-LPDDR3 d + * evice in use Present only in designs configured to support LPDDR3. + * PSU_DDRC_MSTR_LPDDR3 0x0 + + * Select LPDDR2 SDRAM - 1 - LPDDR2 SDRAM device in use. - 0 - non-LPDDR2 d + * evice in use Present only in designs configured to support LPDDR2. + * PSU_DDRC_MSTR_LPDDR2 0x0 + + * Select DDR3 SDRAM - 1 - DDR3 SDRAM device in use - 0 - non-DDR3 SDRAM de + * vice in use Only present in designs that support DDR3. + * PSU_DDRC_MSTR_DDR3 0x0 + + * Master Register + * (OFFSET, MASK, VALUE) (0XFD070000, 0xE30FBE3DU ,0x41040010U) + */ + PSU_Mask_Write(DDRC_MSTR_OFFSET, 0xE30FBE3DU, 0x41040010U); +/*##################################################################### */ + + /* + * Register : MRCTRL0 @ 0XFD070010 + + * Setting this register bit to 1 triggers a mode register read or write op + * eration. When the MR operation is complete, the uMCTL2 automatically cle + * ars this bit. The other register fields of this register must be written + * in a separate APB transaction, before setting this mr_wr bit. It is rec + * ommended NOT to set this signal if in Init, Deep power-down or MPSM oper + * ating modes. + * PSU_DDRC_MRCTRL0_MR_WR 0x0 + + * Address of the mode register that is to be written to. - 0000 - MR0 - 00 + * 01 - MR1 - 0010 - MR2 - 0011 - MR3 - 0100 - MR4 - 0101 - MR5 - 0110 - MR + * 6 - 0111 - MR7 Don't Care for LPDDR2/LPDDR3/LPDDR4 (see MRCTRL1.mr_data + * for mode register addressing in LPDDR2/LPDDR3/LPDDR4) This signal is als + * o used for writing to control words of RDIMMs. In that case, it correspo + * nds to the bank address bits sent to the RDIMM In case of DDR4, the bit[ + * 3:2] corresponds to the bank group bits. Therefore, the bit[3] as well a + * s the bit[2:0] must be set to an appropriate value which is considered b + * oth the Address Mirroring of UDIMMs/RDIMMs and the Output Inversion of R + * DIMMs. + * PSU_DDRC_MRCTRL0_MR_ADDR 0x0 + + * Controls which rank is accessed by MRCTRL0.mr_wr. Normally, it is desire + * d to access all ranks, so all bits should be set to 1. However, for mult + * i-rank UDIMMs/RDIMMs which implement address mirroring, it may be necess + * ary to access ranks individually. Examples (assume uMCTL2 is configured + * for 4 ranks): - 0x1 - select rank 0 only - 0x2 - select rank 1 only - 0x + * 5 - select ranks 0 and 2 - 0xA - select ranks 1 and 3 - 0xF - select ran + * ks 0, 1, 2 and 3 + * PSU_DDRC_MRCTRL0_MR_RANK 0x3 + + * Indicates whether Software intervention is allowed via MRCTRL0/MRCTRL1 b + * efore automatic SDRAM initialization routine or not. For DDR4, this bit + * can be used to initialize the DDR4 RCD (MR7) before automatic SDRAM init + * ialization. For LPDDR4, this bit can be used to program additional mode + * registers before automatic SDRAM initialization if necessary. Note: This + * must be cleared to 0 after completing Software operation. Otherwise, SD + * RAM initialization routine will not re-start. - 0 - Software interventio + * n is not allowed - 1 - Software intervention is allowed + * PSU_DDRC_MRCTRL0_SW_INIT_INT 0x0 + + * Indicates whether the mode register operation is MRS in PDA mode or not + * - 0 - MRS - 1 - MRS in Per DRAM Addressability mode + * PSU_DDRC_MRCTRL0_PDA_EN 0x0 + + * Indicates whether the mode register operation is MRS or WR/RD for MPR (o + * nly supported for DDR4) - 0 - MRS - 1 - WR/RD for MPR + * PSU_DDRC_MRCTRL0_MPR_EN 0x0 + + * Indicates whether the mode register operation is read or write. Only use + * d for LPDDR2/LPDDR3/LPDDR4/DDR4. - 0 - Write - 1 - Read + * PSU_DDRC_MRCTRL0_MR_TYPE 0x0 + + * Mode Register Read/Write Control Register 0. Note: Do not enable more th + * an one of the following fields simultaneously: - sw_init_int - pda_en - + * mpr_en + * (OFFSET, MASK, VALUE) (0XFD070010, 0x8000F03FU ,0x00000030U) + */ + PSU_Mask_Write(DDRC_MRCTRL0_OFFSET, 0x8000F03FU, 0x00000030U); +/*##################################################################### */ + + /* + * Register : DERATEEN @ 0XFD070020 + + * Derate value of tRC for LPDDR4 - 0 - Derating uses +1. - 1 - Derating us + * es +2. - 2 - Derating uses +3. - 3 - Derating uses +4. Present only in d + * esigns configured to support LPDDR4. The required number of cycles for d + * erating can be determined by dividing 3.75ns by the core_ddrc_core_clk p + * eriod, and rounding up the next integer. + * PSU_DDRC_DERATEEN_RC_DERATE_VALUE 0x2 + + * Derate byte Present only in designs configured to support LPDDR2/LPDDR3/ + * LPDDR4 Indicates which byte of the MRR data is used for derating. The ma + * ximum valid value depends on MEMC_DRAM_TOTAL_DATA_WIDTH. + * PSU_DDRC_DERATEEN_DERATE_BYTE 0x0 + + * Derate value - 0 - Derating uses +1. - 1 - Derating uses +2. Present onl + * y in designs configured to support LPDDR2/LPDDR3/LPDDR4 Set to 0 for all + * LPDDR2 speed grades as derating value of +1.875 ns is less than a core_ + * ddrc_core_clk period. Can be 0 or 1 for LPDDR3/LPDDR4, depending if +1.8 + * 75 ns is less than a core_ddrc_core_clk period or not. + * PSU_DDRC_DERATEEN_DERATE_VALUE 0x0 + + * Enables derating - 0 - Timing parameter derating is disabled - 1 - Timin + * g parameter derating is enabled using MR4 read value. Present only in de + * signs configured to support LPDDR2/LPDDR3/LPDDR4 This field must be set + * to '0' for non-LPDDR2/LPDDR3/LPDDR4 mode. + * PSU_DDRC_DERATEEN_DERATE_ENABLE 0x0 + + * Temperature Derate Enable Register + * (OFFSET, MASK, VALUE) (0XFD070020, 0x000003F3U ,0x00000200U) + */ + PSU_Mask_Write(DDRC_DERATEEN_OFFSET, 0x000003F3U, 0x00000200U); +/*##################################################################### */ + + /* + * Register : DERATEINT @ 0XFD070024 + + * Interval between two MR4 reads, used to derate the timing parameters. Pr + * esent only in designs configured to support LPDDR2/LPDDR3/LPDDR4. This r + * egister must not be set to zero + * PSU_DDRC_DERATEINT_MR4_READ_INTERVAL 0x800000 + + * Temperature Derate Interval Register + * (OFFSET, MASK, VALUE) (0XFD070024, 0xFFFFFFFFU ,0x00800000U) + */ + PSU_Mask_Write(DDRC_DERATEINT_OFFSET, 0xFFFFFFFFU, 0x00800000U); +/*##################################################################### */ + + /* + * Register : PWRCTL @ 0XFD070030 + + * Self refresh state is an intermediate state to enter to Self refresh pow + * er down state or exit Self refresh power down state for LPDDR4. This reg + * ister controls transition from the Self refresh state. - 1 - Prohibit tr + * ansition from Self refresh state - 0 - Allow transition from Self refres + * h state + * PSU_DDRC_PWRCTL_STAY_IN_SELFREF 0x0 + + * A value of 1 to this register causes system to move to Self Refresh stat + * e immediately, as long as it is not in INIT or DPD/MPSM operating_mode. + * This is referred to as Software Entry/Exit to Self Refresh. - 1 - Softwa + * re Entry to Self Refresh - 0 - Software Exit from Self Refresh + * PSU_DDRC_PWRCTL_SELFREF_SW 0x0 + + * When this is 1, the uMCTL2 puts the SDRAM into maximum power saving mode + * when the transaction store is empty. This register must be reset to '0' + * to bring uMCTL2 out of maximum power saving mode. Present only in desig + * ns configured to support DDR4. For non-DDR4, this register should not be + * set to 1. Note that MPSM is not supported when using a DWC DDR PHY, if + * the PHY parameter DWC_AC_CS_USE is disabled, as the MPSM exit sequence r + * equires the chip-select signal to toggle. FOR PERFORMANCE ONLY. + * PSU_DDRC_PWRCTL_MPSM_EN 0x0 + + * Enable the assertion of dfi_dram_clk_disable whenever a clock is not req + * uired by the SDRAM. If set to 0, dfi_dram_clk_disable is never asserted. + * Assertion of dfi_dram_clk_disable is as follows: In DDR2/DDR3, can only + * be asserted in Self Refresh. In DDR4, can be asserted in following: - i + * n Self Refresh. - in Maximum Power Saving Mode In mDDR/LPDDR2/LPDDR3, ca + * n be asserted in following: - in Self Refresh - in Power Down - in Deep + * Power Down - during Normal operation (Clock Stop) In LPDDR4, can be asse + * rted in following: - in Self Refresh Power Down - in Power Down - during + * Normal operation (Clock Stop) + * PSU_DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE 0x0 + + * When this is 1, uMCTL2 puts the SDRAM into deep power-down mode when the + * transaction store is empty. This register must be reset to '0' to bring + * uMCTL2 out of deep power-down mode. Controller performs automatic SDRAM + * initialization on deep power-down exit. Present only in designs configu + * red to support mDDR or LPDDR2 or LPDDR3. For non-mDDR/non-LPDDR2/non-LPD + * DR3, this register should not be set to 1. FOR PERFORMANCE ONLY. + * PSU_DDRC_PWRCTL_DEEPPOWERDOWN_EN 0x0 + + * If true then the uMCTL2 goes into power-down after a programmable number + * of cycles 'maximum idle clocks before power down' (PWRTMG.powerdown_to_ + * x32). This register bit may be re-programmed during the course of normal + * operation. + * PSU_DDRC_PWRCTL_POWERDOWN_EN 0x0 + + * If true then the uMCTL2 puts the SDRAM into Self Refresh after a program + * mable number of cycles 'maximum idle clocks before Self Refresh (PWRTMG. + * selfref_to_x32)'. This register bit may be re-programmed during the cour + * se of normal operation. + * PSU_DDRC_PWRCTL_SELFREF_EN 0x0 + + * Low Power Control Register + * (OFFSET, MASK, VALUE) (0XFD070030, 0x0000007FU ,0x00000000U) + */ + PSU_Mask_Write(DDRC_PWRCTL_OFFSET, 0x0000007FU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : PWRTMG @ 0XFD070034 + + * After this many clocks of NOP or deselect the uMCTL2 automatically puts + * the SDRAM into Self Refresh. This must be enabled in the PWRCTL.selfref_ + * en. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY. + * PSU_DDRC_PWRTMG_SELFREF_TO_X32 0x40 + + * Minimum deep power-down time. For mDDR, value from the JEDEC specificati + * on is 0 as mDDR exits from deep power-down mode immediately after PWRCTL + * .deeppowerdown_en is de-asserted. For LPDDR2/LPDDR3, value from the JEDE + * C specification is 500us. Unit: Multiples of 4096 clocks. Present only i + * n designs configured to support mDDR, LPDDR2 or LPDDR3. FOR PERFORMANCE + * ONLY. + * PSU_DDRC_PWRTMG_T_DPD_X4096 0x84 + + * After this many clocks of NOP or deselect the uMCTL2 automatically puts + * the SDRAM into power-down. This must be enabled in the PWRCTL.powerdown_ + * en. Unit: Multiples of 32 clocks FOR PERFORMANCE ONLY. + * PSU_DDRC_PWRTMG_POWERDOWN_TO_X32 0x10 + + * Low Power Timing Register + * (OFFSET, MASK, VALUE) (0XFD070034, 0x00FFFF1FU ,0x00408410U) + */ + PSU_Mask_Write(DDRC_PWRTMG_OFFSET, 0x00FFFF1FU, 0x00408410U); +/*##################################################################### */ + + /* + * Register : RFSHCTL0 @ 0XFD070050 + + * Threshold value in number of clock cycles before the critical refresh or + * page timer expires. A critical refresh is to be issued before this thre + * shold is reached. It is recommended that this not be changed from the de + * fault value, currently shown as 0x2. It must always be less than interna + * lly used t_rfc_nom_x32. Note that, in LPDDR2/LPDDR3/LPDDR4, internally u + * sed t_rfc_nom_x32 may be equal to RFSHTMG.t_rfc_nom_x32>>2 if derating i + * s enabled (DERATEEN.derate_enable=1). Otherwise, internally used t_rfc_n + * om_x32 will be equal to RFSHTMG.t_rfc_nom_x32. Unit: Multiples of 32 clo + * cks. + * PSU_DDRC_RFSHCTL0_REFRESH_MARGIN 0x2 + + * If the refresh timer (tRFCnom, also known as tREFI) has expired at least + * once, but it has not expired (RFSHCTL0.refresh_burst+1) times yet, then + * a speculative refresh may be performed. A speculative refresh is a refr + * esh performed at a time when refresh would be useful, but before it is a + * bsolutely required. When the SDRAM bus is idle for a period of time dete + * rmined by this RFSHCTL0.refresh_to_x32 and the refresh timer has expired + * at least once since the last refresh, then a speculative refresh is per + * formed. Speculative refreshes continues successively until there are no + * refreshes pending or until new reads or writes are issued to the uMCTL2. + * FOR PERFORMANCE ONLY. + * PSU_DDRC_RFSHCTL0_REFRESH_TO_X32 0x10 + + * The programmed value + 1 is the number of refresh timeouts that is allow + * ed to accumulate before traffic is blocked and the refreshes are forced + * to execute. Closing pages to perform a refresh is a one-time penalty tha + * t must be paid for each group of refreshes. Therefore, performing refres + * hes in a burst reduces the per-refresh penalty of these page closings. H + * igher numbers for RFSHCTL.refresh_burst slightly increases utilization; + * lower numbers decreases the worst-case latency associated with refreshes + * . - 0 - single refresh - 1 - burst-of-2 refresh - 7 - burst-of-8 refresh + * For information on burst refresh feature refer to section 3.9 of DDR2 J + * EDEC specification - JESD79-2F.pdf. For DDR2/3, the refresh is always pe + * r-rank and not per-bank. The rank refresh can be accumulated over 8*tREF + * I cycles using the burst refresh feature. In DDR4 mode, according to Fin + * e Granularity feature, 8 refreshes can be postponed in 1X mode, 16 refre + * shes in 2X mode and 32 refreshes in 4X mode. If using PHY-initiated upda + * tes, care must be taken in the setting of RFSHCTL0.refresh_burst, to ens + * ure that tRFCmax is not violated due to a PHY-initiated update occurring + * shortly before a refresh burst was due. In this situation, the refresh + * burst will be delayed until the PHY-initiated update is complete. + * PSU_DDRC_RFSHCTL0_REFRESH_BURST 0x0 + + * - 1 - Per bank refresh; - 0 - All bank refresh. Per bank refresh allows + * traffic to flow to other banks. Per bank refresh is not supported by all + * LPDDR2 devices but should be supported by all LPDDR3/LPDDR4 devices. Pr + * esent only in designs configured to support LPDDR2/LPDDR3/LPDDR4 + * PSU_DDRC_RFSHCTL0_PER_BANK_REFRESH 0x0 + + * Refresh Control Register 0 + * (OFFSET, MASK, VALUE) (0XFD070050, 0x00F1F1F4U ,0x00210000U) + */ + PSU_Mask_Write(DDRC_RFSHCTL0_OFFSET, 0x00F1F1F4U, 0x00210000U); +/*##################################################################### */ + + /* + * Register : RFSHCTL1 @ 0XFD070054 + + * Refresh timer start for rank 1 (only present in multi-rank configuration + * s). This is useful in staggering the refreshes to multiple ranks to help + * traffic to proceed. This is explained in Refresh Controls section of ar + * chitecture chapter. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY. + * PSU_DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32 0x0 + + * Refresh timer start for rank 0 (only present in multi-rank configuration + * s). This is useful in staggering the refreshes to multiple ranks to help + * traffic to proceed. This is explained in Refresh Controls section of ar + * chitecture chapter. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY. + * PSU_DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32 0x0 + + * Refresh Control Register 1 + * (OFFSET, MASK, VALUE) (0XFD070054, 0x0FFF0FFFU ,0x00000000U) + */ + PSU_Mask_Write(DDRC_RFSHCTL1_OFFSET, 0x0FFF0FFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : RFSHCTL3 @ 0XFD070060 + + * Fine Granularity Refresh Mode - 000 - Fixed 1x (Normal mode) - 001 - Fix + * ed 2x - 010 - Fixed 4x - 101 - Enable on the fly 2x (not supported) - 11 + * 0 - Enable on the fly 4x (not supported) - Everything else - reserved No + * te: The on-the-fly modes is not supported in this version of the uMCTL2. + * Note: This must be set up while the Controller is in reset or while the + * Controller is in self-refresh mode. Changing this during normal operati + * on is not allowed. Making this a dynamic register will be supported in f + * uture version of the uMCTL2. + * PSU_DDRC_RFSHCTL3_REFRESH_MODE 0x0 + + * Toggle this signal (either from 0 to 1 or from 1 to 0) to indicate that + * the refresh register(s) have been updated. The value is automatically up + * dated when exiting reset, so it does not need to be toggled initially. + * PSU_DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL 0x0 + + * When '1', disable auto-refresh generated by the uMCTL2. When auto-refres + * h is disabled, the SoC core must generate refreshes using the registers + * reg_ddrc_rank0_refresh, reg_ddrc_rank1_refresh, reg_ddrc_rank2_refresh a + * nd reg_ddrc_rank3_refresh. When dis_auto_refresh transitions from 0 to 1 + * , any pending refreshes are immediately scheduled by the uMCTL2. If DDR4 + * CRC/parity retry is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), d + * isable auto-refresh is not supported, and this bit must be set to '0'. T + * his register field is changeable on the fly. + * PSU_DDRC_RFSHCTL3_DIS_AUTO_REFRESH 0x1 + + * Refresh Control Register 3 + * (OFFSET, MASK, VALUE) (0XFD070060, 0x00000073U ,0x00000001U) + */ + PSU_Mask_Write(DDRC_RFSHCTL3_OFFSET, 0x00000073U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : RFSHTMG @ 0XFD070064 + + * tREFI: Average time interval between refreshes per rank (Specification: + * 7.8us for DDR2, DDR3 and DDR4. See JEDEC specification for mDDR, LPDDR2, + * LPDDR3 and LPDDR4). For LPDDR2/LPDDR3/LPDDR4: - if using all-bank refre + * shes (RFSHCTL0.per_bank_refresh = 0), this register should be set to tRE + * FIab - if using per-bank refreshes (RFSHCTL0.per_bank_refresh = 1), this + * register should be set to tREFIpb For configurations with MEMC_FREQ_RAT + * IO=2, program this to (tREFI/2), no rounding up. In DDR4 mode, tREFI val + * ue is different depending on the refresh mode. The user should program t + * he appropriate value from the spec based on the value programmed in the + * refresh mode register. Note that RFSHTMG.t_rfc_nom_x32 * 32 must be grea + * ter than RFSHTMG.t_rfc_min, and RFSHTMG.t_rfc_nom_x32 must be greater th + * an 0x1. Unit: Multiples of 32 clocks. + * PSU_DDRC_RFSHTMG_T_RFC_NOM_X32 0x81 + + * Used only when LPDDR3 memory type is connected. Should only be changed w + * hen uMCTL2 is in reset. Specifies whether to use the tREFBW parameter (r + * equired by some LPDDR3 devices which comply with earlier versions of the + * LPDDR3 JEDEC specification) or not: - 0 - tREFBW parameter not used - 1 + * - tREFBW parameter used + * PSU_DDRC_RFSHTMG_LPDDR3_TREFBW_EN 0x1 + + * tRFC (min): Minimum time from refresh to refresh or activate. For MEMC_F + * REQ_RATIO=1 configurations, t_rfc_min should be set to RoundUp(tRFCmin/t + * CK). For MEMC_FREQ_RATIO=2 configurations, t_rfc_min should be set to Ro + * undUp(RoundUp(tRFCmin/tCK)/2). In LPDDR2/LPDDR3/LPDDR4 mode: - if using + * all-bank refreshes, the tRFCmin value in the above equations is equal to + * tRFCab - if using per-bank refreshes, the tRFCmin value in the above eq + * uations is equal to tRFCpb In DDR4 mode, the tRFCmin value in the above + * equations is different depending on the refresh mode (fixed 1X,2X,4X) an + * d the device density. The user should program the appropriate value from + * the spec based on the 'refresh_mode' and the device density that is use + * d. Unit: Clocks. + * PSU_DDRC_RFSHTMG_T_RFC_MIN 0x8b + + * Refresh Timing Register + * (OFFSET, MASK, VALUE) (0XFD070064, 0x0FFF83FFU ,0x0081808BU) + */ + PSU_Mask_Write(DDRC_RFSHTMG_OFFSET, 0x0FFF83FFU, 0x0081808BU); +/*##################################################################### */ + + /* + * Register : ECCCFG0 @ 0XFD070070 + + * Disable ECC scrubs. Valid only when ECCCFG0.ecc_mode = 3'b100 and MEMC_U + * SE_RMW is defined + * PSU_DDRC_ECCCFG0_DIS_SCRUB 0x1 + + * ECC mode indicator - 000 - ECC disabled - 100 - ECC enabled - SEC/DED ov + * er 1 beat - all other settings are reserved for future use + * PSU_DDRC_ECCCFG0_ECC_MODE 0x0 + + * ECC Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD070070, 0x00000017U ,0x00000010U) + */ + PSU_Mask_Write(DDRC_ECCCFG0_OFFSET, 0x00000017U, 0x00000010U); +/*##################################################################### */ + + /* + * Register : ECCCFG1 @ 0XFD070074 + + * Selects whether to poison 1 or 2 bits - if 0 -> 2-bit (uncorrectable) da + * ta poisoning, if 1 -> 1-bit (correctable) data poisoning, if ECCCFG1.dat + * a_poison_en=1 + * PSU_DDRC_ECCCFG1_DATA_POISON_BIT 0x0 + + * Enable ECC data poisoning - introduces ECC errors on writes to address s + * pecified by the ECCPOISONADDR0/1 registers + * PSU_DDRC_ECCCFG1_DATA_POISON_EN 0x0 + + * ECC Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD070074, 0x00000003U ,0x00000000U) + */ + PSU_Mask_Write(DDRC_ECCCFG1_OFFSET, 0x00000003U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : CRCPARCTL1 @ 0XFD0700C4 + + * The maximum number of DFI PHY clock cycles allowed from the assertion of + * the dfi_rddata_en signal to the assertion of each of the corresponding + * bits of the dfi_rddata_valid signal. This corresponds to the DFI timing + * parameter tphy_rdlat. Refer to PHY specification for correct value. This + * value it only used for detecting read data timeout when DDR4 retry is e + * nabled by CRCPARCTL1.crc_parity_retry_enable=1. Maximum supported value: + * - 1:1 Frequency mode : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_r + * dlat < 'd114 - 1:2 Frequency mode ANDAND DFITMG0.dfi_rddata_use_sdr == 1 + * : CRCPARCTL1.dfi_t_phy_rdlat < 64 - 1:2 Frequency mode ANDAND DFITMG0.d + * fi_rddata_use_sdr == 0 : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_ + * rdlat < 'd114 Unit: DFI Clocks + * PSU_DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT 0x10 + + * After a Parity or CRC error is flagged on dfi_alert_n signal, the softwa + * re has an option to read the mode registers in the DRAM before the hardw + * are begins the retry process - 1: Wait for software to read/write the mo + * de registers before hardware begins the retry. After software is done wi + * th its operations, it will clear the alert interrupt register bit - 0: H + * ardware can begin the retry right away after the dfi_alert_n pulse goes + * away. The value on this register is valid only when retry is enabled (PA + * RCTRL.crc_parity_retry_enable = 1) If this register is set to 1 and if t + * he software doesn't clear the interrupt register after handling the pari + * ty/CRC error, then the hardware will not begin the retry process and the + * system will hang. In the case of Parity/CRC error, there are two possib + * ilities when the software doesn't reset MR5[4] to 0. - (i) If 'Persisten + * t parity' mode register bit is NOT set: the commands sent during retry a + * nd normal operation are executed without parity checking. The value in t + * he Parity error log register MPR Page 1 is valid. - (ii) If 'Persistent + * parity' mode register bit is SET: Parity checking is done for commands s + * ent during retry and normal operation. If multiple errors occur before M + * R5[4] is cleared, the error log in MPR Page 1 should be treated as 'Don' + * t care'. + * PSU_DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW 0x1 + + * - 1: Enable command retry mechanism in case of C/A Parity or CRC error - + * 0: Disable command retry mechanism when C/A Parity or CRC features are + * enabled. Note that retry functionality is not supported if burst chop is + * enabled (MSTR.burstchop = 1) and/or disable auto-refresh is enabled (RF + * SHCTL3.dis_auto_refresh = 1) + * PSU_DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE 0x0 + + * CRC Calculation setting register - 1: CRC includes DM signal - 0: CRC no + * t includes DM signal Present only in designs configured to support DDR4. + * PSU_DDRC_CRCPARCTL1_CRC_INC_DM 0x0 + + * CRC enable Register - 1: Enable generation of CRC - 0: Disable generatio + * n of CRC The setting of this register should match the CRC mode register + * setting in the DRAM. + * PSU_DDRC_CRCPARCTL1_CRC_ENABLE 0x0 + + * C/A Parity enable register - 1: Enable generation of C/A parity and dete + * ction of C/A parity error - 0: Disable generation of C/A parity and disa + * ble detection of C/A parity error If RCD's parity error detection or SDR + * AM's parity detection is enabled, this register should be 1. + * PSU_DDRC_CRCPARCTL1_PARITY_ENABLE 0x0 + + * CRC Parity Control Register1 + * (OFFSET, MASK, VALUE) (0XFD0700C4, 0x3F000391U ,0x10000200U) + */ + PSU_Mask_Write(DDRC_CRCPARCTL1_OFFSET, 0x3F000391U, 0x10000200U); +/*##################################################################### */ + + /* + * Register : CRCPARCTL2 @ 0XFD0700C8 + + * Value from the DRAM spec indicating the maximum width of the dfi_alert_n + * pulse when a parity error occurs. Recommended values: - tPAR_ALERT_PW.M + * AX For configurations with MEMC_FREQ_RATIO=2, program this to tPAR_ALERT + * _PW.MAX/2 and round up to next integer value. Values of 0, 1 and 2 are i + * llegal. This value must be greater than CRCPARCTL2.t_crc_alert_pw_max. + * PSU_DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX 0x40 + + * Value from the DRAM spec indicating the maximum width of the dfi_alert_n + * pulse when a CRC error occurs. Recommended values: - tCRC_ALERT_PW.MAX + * For configurations with MEMC_FREQ_RATIO=2, program this to tCRC_ALERT_PW + * .MAX/2 and round up to next integer value. Values of 0, 1 and 2 are ille + * gal. This value must be less than CRCPARCTL2.t_par_alert_pw_max. + * PSU_DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX 0x5 + + * Indicates the maximum duration in number of DRAM clock cycles for which + * a command should be held in the Command Retry FIFO before it is popped o + * ut. Every location in the Command Retry FIFO has an associated down coun + * ting timer that will use this register as the start value. The down coun + * ting starts when a command is loaded into the FIFO. The timer counts dow + * n every 4 DRAM cycles. When the counter reaches zero, the entry is poppe + * d from the FIFO. All the counters are frozen, if a C/A Parity or CRC err + * or occurs before the counter reaches zero. The counter is reset to 0, af + * ter all the commands in the FIFO are retried. Recommended(minimum) value + * s: - Only C/A Parity is enabled. RoundUp((PHY Command Latency(DRAM CLK) + * + CAL + RDIMM delay + tPAR_ALERT_ON.max + tPAR_UNKNOWN + PHY Alert Laten + * cy(DRAM CLK) + board delay) / 4) + 2 - Both C/A Parity and CRC is enable + * d/ Only CRC is enabled. RoundUp((PHY Command Latency(DRAM CLK) + CAL + R + * DIMM delay + WL + 5(BL10)+ tCRC_ALERT.max + PHY Alert Latency(DRAM CLK) + * + board delay) / 4) + 2 Note 1: All value (e.g. tPAR_ALERT_ON) should be + * in terms of DRAM Clock and round up Note 2: Board delay(Command/Alert_n + * ) should be considered. Note 3: Use the worst case(longer) value for PHY + * Latencies/Board delay Note 4: The Recommended values are minimum value + * to be set. For mode detail, See 'Calculation of FIFO Depth' section. Max + * value can be set to this register is defined below: - MEMC_BURST_LENGTH + * == 16 Full bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 + * Full bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Half b + * us Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-4 Half bus Mod + * e (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-6 Quarter bus Mode (C + * RC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-8 Quarter bus Mode (CRC= + * ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-12 - MEMC_BURST_LENGTH != 16 + * Full bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-1 Full + * bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mod + * e (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mode (CRC + * =ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Quarter bus Mode (CRC=OFF + * ) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-4 Quarter bus Mode (CRC=ON) Ma + * x value = UMCTL2_RETRY_CMD_FIFO_DEPTH-6 Values of 0, 1 and 2 are illegal + * . + * PSU_DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4 0x1f + + * CRC Parity Control Register2 + * (OFFSET, MASK, VALUE) (0XFD0700C8, 0x01FF1F3FU ,0x0040051FU) + */ + PSU_Mask_Write(DDRC_CRCPARCTL2_OFFSET, 0x01FF1F3FU, 0x0040051FU); +/*##################################################################### */ + + /* + * Register : INIT0 @ 0XFD0700D0 + + * If lower bit is enabled the SDRAM initialization routine is skipped. The + * upper bit decides what state the controller starts up in when reset is + * removed - 00 - SDRAM Intialization routine is run after power-up - 01 - + * SDRAM Intialization routine is skipped after power-up. Controller starts + * up in Normal Mode - 11 - SDRAM Intialization routine is skipped after p + * ower-up. Controller starts up in Self-refresh Mode - 10 - SDRAM Intializ + * ation routine is run after power-up. Note: The only 2'b00 is supported f + * or LPDDR4 in this version of the uMCTL2. + * PSU_DDRC_INIT0_SKIP_DRAM_INIT 0x0 + + * Cycles to wait after driving CKE high to start the SDRAM initialization + * sequence. Unit: 1024 clocks. DDR2 typically requires a 400 ns delay, req + * uiring this value to be programmed to 2 at all clock speeds. LPDDR2/LPDD + * R3 typically requires this to be programmed for a delay of 200 us. LPDDR + * 4 typically requires this to be programmed for a delay of 2 us. For conf + * igurations with MEMC_FREQ_RATIO=2, program this to JEDEC spec value divi + * ded by 2, and round it up to next integer value. + * PSU_DDRC_INIT0_POST_CKE_X1024 0x2 + + * Cycles to wait after reset before driving CKE high to start the SDRAM in + * itialization sequence. Unit: 1024 clock cycles. DDR2 specifications typi + * cally require this to be programmed for a delay of >= 200 us. LPDDR2/LPD + * DR3: tINIT1 of 100 ns (min) LPDDR4: tINIT3 of 2 ms (min) For configurati + * ons with MEMC_FREQ_RATIO=2, program this to JEDEC spec value divided by + * 2, and round it up to next integer value. + * PSU_DDRC_INIT0_PRE_CKE_X1024 0x106 + + * SDRAM Initialization Register 0 + * (OFFSET, MASK, VALUE) (0XFD0700D0, 0xC3FF0FFFU ,0x00020106U) + */ + PSU_Mask_Write(DDRC_INIT0_OFFSET, 0xC3FF0FFFU, 0x00020106U); +/*##################################################################### */ + + /* + * Register : INIT1 @ 0XFD0700D4 + + * Number of cycles to assert SDRAM reset signal during init sequence. This + * is only present for designs supporting DDR3, DDR4 or LPDDR4 devices. Fo + * r use with a DDR PHY, this should be set to a minimum of 1 + * PSU_DDRC_INIT1_DRAM_RSTN_X1024 0x2 + + * Cycles to wait after completing the SDRAM initialization sequence before + * starting the dynamic scheduler. Unit: Counts of a global timer that pul + * ses every 32 clock cycles. There is no known specific requirement for th + * is; it may be set to zero. + * PSU_DDRC_INIT1_FINAL_WAIT_X32 0x0 + + * Wait period before driving the OCD complete command to SDRAM. Unit: Coun + * ts of a global timer that pulses every 32 clock cycles. There is no know + * n specific requirement for this; it may be set to zero. + * PSU_DDRC_INIT1_PRE_OCD_X32 0x0 + + * SDRAM Initialization Register 1 + * (OFFSET, MASK, VALUE) (0XFD0700D4, 0x01FF7F0FU ,0x00020000U) + */ + PSU_Mask_Write(DDRC_INIT1_OFFSET, 0x01FF7F0FU, 0x00020000U); +/*##################################################################### */ + + /* + * Register : INIT2 @ 0XFD0700D8 + + * Idle time after the reset command, tINIT4. Present only in designs confi + * gured to support LPDDR2. Unit: 32 clock cycles. + * PSU_DDRC_INIT2_IDLE_AFTER_RESET_X32 0x23 + + * Time to wait after the first CKE high, tINIT2. Present only in designs c + * onfigured to support LPDDR2/LPDDR3. Unit: 1 clock cycle. LPDDR2/LPDDR3 t + * ypically requires 5 x tCK delay. + * PSU_DDRC_INIT2_MIN_STABLE_CLOCK_X1 0x5 + + * SDRAM Initialization Register 2 + * (OFFSET, MASK, VALUE) (0XFD0700D8, 0x0000FF0FU ,0x00002305U) + */ + PSU_Mask_Write(DDRC_INIT2_OFFSET, 0x0000FF0FU, 0x00002305U); +/*##################################################################### */ + + /* + * Register : INIT3 @ 0XFD0700DC + + * DDR2: Value to write to MR register. Bit 8 is for DLL and the setting he + * re is ignored. The uMCTL2 sets this bit appropriately. DDR3/DDR4: Value + * loaded into MR0 register. mDDR: Value to write to MR register. LPDDR2/LP + * DDR3/LPDDR4 - Value to write to MR1 register + * PSU_DDRC_INIT3_MR 0x730 + + * DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setti + * ng in this register is ignored. The uMCTL2 sets those bits appropriately + * . DDR3/DDR4: Value to write to MR1 register Set bit 7 to 0. If PHY-evalu + * ation mode training is enabled, this bit is set appropriately by the uMC + * TL2 during write leveling. mDDR: Value to write to EMR register. LPDDR2/ + * LPDDR3/LPDDR4 - Value to write to MR2 register + * PSU_DDRC_INIT3_EMR 0x301 + + * SDRAM Initialization Register 3 + * (OFFSET, MASK, VALUE) (0XFD0700DC, 0xFFFFFFFFU ,0x07300301U) + */ + PSU_Mask_Write(DDRC_INIT3_OFFSET, 0xFFFFFFFFU, 0x07300301U); +/*##################################################################### */ + + /* + * Register : INIT4 @ 0XFD0700E0 + + * DDR2: Value to write to EMR2 register. DDR3/DDR4: Value to write to MR2 + * register LPDDR2/LPDDR3/LPDDR4: Value to write to MR3 register mDDR: Unus + * ed + * PSU_DDRC_INIT4_EMR2 0x20 + + * DDR2: Value to write to EMR3 register. DDR3/DDR4: Value to write to MR3 + * register mDDR/LPDDR2/LPDDR3: Unused LPDDR4: Value to write to MR13 regis + * ter + * PSU_DDRC_INIT4_EMR3 0x200 + + * SDRAM Initialization Register 4 + * (OFFSET, MASK, VALUE) (0XFD0700E0, 0xFFFFFFFFU ,0x00200200U) + */ + PSU_Mask_Write(DDRC_INIT4_OFFSET, 0xFFFFFFFFU, 0x00200200U); +/*##################################################################### */ + + /* + * Register : INIT5 @ 0XFD0700E4 + + * ZQ initial calibration, tZQINIT. Present only in designs configured to s + * upport DDR3 or DDR4 or LPDDR2/LPDDR3. Unit: 32 clock cycles. DDR3 typica + * lly requires 512 clocks. DDR4 requires 1024 clocks. LPDDR2/LPDDR3 requir + * es 1 us. + * PSU_DDRC_INIT5_DEV_ZQINIT_X32 0x21 + + * Maximum duration of the auto initialization, tINIT5. Present only in des + * igns configured to support LPDDR2/LPDDR3. LPDDR2/LPDDR3 typically requir + * es 10 us. + * PSU_DDRC_INIT5_MAX_AUTO_INIT_X1024 0x4 + + * SDRAM Initialization Register 5 + * (OFFSET, MASK, VALUE) (0XFD0700E4, 0x00FF03FFU ,0x00210004U) + */ + PSU_Mask_Write(DDRC_INIT5_OFFSET, 0x00FF03FFU, 0x00210004U); +/*##################################################################### */ + + /* + * Register : INIT6 @ 0XFD0700E8 + + * DDR4- Value to be loaded into SDRAM MR4 registers. Used in DDR4 designs + * only. + * PSU_DDRC_INIT6_MR4 0x0 + + * DDR4- Value to be loaded into SDRAM MR5 registers. Used in DDR4 designs + * only. + * PSU_DDRC_INIT6_MR5 0x6c0 + + * SDRAM Initialization Register 6 + * (OFFSET, MASK, VALUE) (0XFD0700E8, 0xFFFFFFFFU ,0x000006C0U) + */ + PSU_Mask_Write(DDRC_INIT6_OFFSET, 0xFFFFFFFFU, 0x000006C0U); +/*##################################################################### */ + + /* + * Register : INIT7 @ 0XFD0700EC + + * DDR4- Value to be loaded into SDRAM MR6 registers. Used in DDR4 designs + * only. + * PSU_DDRC_INIT7_MR6 0x819 + + * SDRAM Initialization Register 7 + * (OFFSET, MASK, VALUE) (0XFD0700EC, 0xFFFF0000U ,0x08190000U) + */ + PSU_Mask_Write(DDRC_INIT7_OFFSET, 0xFFFF0000U, 0x08190000U); +/*##################################################################### */ + + /* + * Register : DIMMCTL @ 0XFD0700F0 + + * Disabling Address Mirroring for BG bits. When this is set to 1, BG0 and + * BG1 are NOT swapped even if Address Mirroring is enabled. This will be r + * equired for DDR4 DIMMs with x16 devices. - 1 - BG0 and BG1 are NOT swapp + * ed. - 0 - BG0 and BG1 are swapped if address mirroring is enabled. + * PSU_DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING 0x0 + + * Enable for BG1 bit of MRS command. BG1 bit of the mode register address + * is specified as RFU (Reserved for Future Use) and must be programmed to + * 0 during MRS. In case where DRAMs which do not have BG1 are attached and + * both the CA parity and the Output Inversion are enabled, this must be s + * et to 0, so that the calculation of CA parity will not include BG1 bit. + * Note: This has no effect on the address of any other memory accesses, or + * of software-driven mode register accesses. If address mirroring is enab + * led, this is applied to BG1 of even ranks and BG0 of odd ranks. - 1 - En + * abled - 0 - Disabled + * PSU_DDRC_DIMMCTL_MRS_BG1_EN 0x1 + + * Enable for A17 bit of MRS command. A17 bit of the mode register address + * is specified as RFU (Reserved for Future Use) and must be programmed to + * 0 during MRS. In case where DRAMs which do not have A17 are attached and + * the Output Inversion are enabled, this must be set to 0, so that the ca + * lculation of CA parity will not include A17 bit. Note: This has no effec + * t on the address of any other memory accesses, or of software-driven mod + * e register accesses. - 1 - Enabled - 0 - Disabled + * PSU_DDRC_DIMMCTL_MRS_A17_EN 0x0 + + * Output Inversion Enable (for DDR4 RDIMM implementations only). DDR4 RDIM + * M implements the Output Inversion feature by default, which means that t + * he following address, bank address and bank group bits of B-side DRAMs a + * re inverted: A3-A9, A11, A13, A17, BA0-BA1, BG0-BG1. Setting this bit en + * sures that, for mode register accesses generated by the uMCTL2 during th + * e automatic initialization routine and enabling of a particular DDR4 fea + * ture, separate A-side and B-side mode register accesses are generated. F + * or B-side mode register accesses, these bits are inverted within the uMC + * TL2 to compensate for this RDIMM inversion. Note: This has no effect on + * the address of any other memory accesses, or of software-driven mode reg + * ister accesses. - 1 - Implement output inversion for B-side DRAMs. - 0 - + * Do not implement output inversion for B-side DRAMs. + * PSU_DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN 0x0 + + * Address Mirroring Enable (for multi-rank UDIMM implementations and multi + * -rank DDR4 RDIMM implementations). Some UDIMMs and DDR4 RDIMMs implement + * address mirroring for odd ranks, which means that the following address + * , bank address and bank group bits are swapped: (A3, A4), (A5, A6), (A7, + * A8), (BA0, BA1) and also (A11, A13), (BG0, BG1) for the DDR4. Setting t + * his bit ensures that, for mode register accesses during the automatic in + * itialization routine, these bits are swapped within the uMCTL2 to compen + * sate for this UDIMM/RDIMM swapping. In addition to the automatic initial + * ization routine, in case of DDR4 UDIMM/RDIMM, they are swapped during th + * e automatic MRS access to enable/disable of a particular DDR4 feature. N + * ote: This has no effect on the address of any other memory accesses, or + * of software-driven mode register accesses. This is not supported for mDD + * R, LPDDR2, LPDDR3 or LPDDR4 SDRAMs. Note: In case of x16 DDR4 DIMMs, BG1 + * output of MRS for the odd ranks is same as BG0 because BG1 is invalid, + * hence dimm_dis_bg_mirroring register must be set to 1. - 1 - For odd ran + * ks, implement address mirroring for MRS commands to during initializatio + * n and for any automatic DDR4 MRS commands (to be used if UDIMM/RDIMM imp + * lements address mirroring) - 0 - Do not implement address mirroring + * PSU_DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN 0x0 + + * Staggering enable for multi-rank accesses (for multi-rank UDIMM and RDIM + * M implementations only). This is not supported for mDDR, LPDDR2, LPDDR3 + * or LPDDR4 SDRAMs. Note: Even if this bit is set it does not take care of + * software driven MR commands (via MRCTRL0/MRCTRL1), where software is re + * sponsible to send them to seperate ranks as appropriate. - 1 - (DDR4) Se + * nd MRS commands to each ranks seperately - 1 - (non-DDR4) Send all comma + * nds to even and odd ranks seperately - 0 - Do not stagger accesses + * PSU_DDRC_DIMMCTL_DIMM_STAGGER_CS_EN 0x0 + + * DIMM Control Register + * (OFFSET, MASK, VALUE) (0XFD0700F0, 0x0000003FU ,0x00000010U) + */ + PSU_Mask_Write(DDRC_DIMMCTL_OFFSET, 0x0000003FU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : RANKCTL @ 0XFD0700F4 + + * Only present for multi-rank configurations. Indicates the number of cloc + * ks of gap in data responses when performing consecutive writes to differ + * ent ranks. This is used to switch the delays in the PHY to match the ran + * k requirements. This value should consider both PHY requirement and ODT + * requirement. - PHY requirement: tphy_wrcsgap + 1 (see PHY databook for v + * alue of tphy_wrcsgap) If CRC feature is enabled, should be increased by + * 1. If write preamble is set to 2tCK(DDR4/LPDDR4 only), should be increas + * ed by 1. If write postamble is set to 1.5tCK(LPDDR4 only), should be inc + * reased by 1. - ODT requirement: The value programmed in this register ta + * kes care of the ODT switch off timing requirement when switching ranks d + * uring writes. For LPDDR4, the requirement is ODTLoff - ODTLon - BL/2 + 1 + * For configurations with MEMC_FREQ_RATIO=1, program this to the larger o + * f PHY requirement or ODT requirement. For configurations with MEMC_FREQ_ + * RATIO=2, program this to the larger value divided by two and round it up + * to the next integer. + * PSU_DDRC_RANKCTL_DIFF_RANK_WR_GAP 0x6 + + * Only present for multi-rank configurations. Indicates the number of cloc + * ks of gap in data responses when performing consecutive reads to differe + * nt ranks. This is used to switch the delays in the PHY to match the rank + * requirements. This value should consider both PHY requirement and ODT r + * equirement. - PHY requirement: tphy_rdcsgap + 1 (see PHY databook for va + * lue of tphy_rdcsgap) If read preamble is set to 2tCK(DDR4/LPDDR4 only), + * should be increased by 1. If read postamble is set to 1.5tCK(LPDDR4 only + * ), should be increased by 1. - ODT requirement: The value programmed in + * this register takes care of the ODT switch off timing requirement when s + * witching ranks during reads. For configurations with MEMC_FREQ_RATIO=1, + * program this to the larger of PHY requirement or ODT requirement. For co + * nfigurations with MEMC_FREQ_RATIO=2, program this to the larger value di + * vided by two and round it up to the next integer. + * PSU_DDRC_RANKCTL_DIFF_RANK_RD_GAP 0x6 + + * Only present for multi-rank configurations. Background: Reads to the sam + * e rank can be performed back-to-back. Reads to different ranks require a + * dditional gap dictated by the register RANKCTL.diff_rank_rd_gap. This is + * to avoid possible data bus contention as well as to give PHY enough tim + * e to switch the delay when changing ranks. The uMCTL2 arbitrates for bus + * access on a cycle-by-cycle basis; therefore after a read is scheduled, + * there are few clock cycles (determined by the value on RANKCTL.diff_rank + * _rd_gap register) in which only reads from the same rank are eligible to + * be scheduled. This prevents reads from other ranks from having fair acc + * ess to the data bus. This parameter represents the maximum number of rea + * ds that can be scheduled consecutively to the same rank. After this numb + * er is reached, a delay equal to RANKCTL.diff_rank_rd_gap is inserted by + * the scheduler to allow all ranks a fair opportunity to be scheduled. Hig + * her numbers increase bandwidth utilization, lower numbers increase fairn + * ess. This feature can be DISABLED by setting this register to 0. When se + * t to 0, the Controller will stay on the same rank as long as commands ar + * e available for it. Minimum programmable value is 0 (feature disabled) a + * nd maximum programmable value is 0xF. FOR PERFORMANCE ONLY. + * PSU_DDRC_RANKCTL_MAX_RANK_RD 0xf + + * Rank Control Register + * (OFFSET, MASK, VALUE) (0XFD0700F4, 0x00000FFFU ,0x0000066FU) + */ + PSU_Mask_Write(DDRC_RANKCTL_OFFSET, 0x00000FFFU, 0x0000066FU); +/*##################################################################### */ + + /* + * Register : DRAMTMG0 @ 0XFD070100 + + * Minimum time between write and precharge to same bank. Unit: Clocks Spec + * ifications: WL + BL/2 + tWR = approximately 8 cycles + 15 ns = 14 clocks + * @400MHz and less for lower frequencies where: - WL = write latency - BL + * = burst length. This must match the value programmed in the BL bit of t + * he mode register to the SDRAM. BST (burst terminate) is not supported at + * present. - tWR = Write recovery time. This comes directly from the SDRA + * M specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 for this p + * arameter. For configurations with MEMC_FREQ_RATIO=2, 1T mode, divide the + * above value by 2. No rounding up. For configurations with MEMC_FREQ_RAT + * IO=2, 2T mode or LPDDR4 mode, divide the above value by 2 and round it u + * p to the next integer value. + * PSU_DDRC_DRAMTMG0_WR2PRE 0x11 + + * tFAW Valid only when 8 or more banks(or banks x bank groups) are present + * . In 8-bank design, at most 4 banks must be activated in a rolling windo + * w of tFAW cycles. For configurations with MEMC_FREQ_RATIO=2, program thi + * s to (tFAW/2) and round up to next integer value. In a 4-bank design, se + * t this register to 0x1 independent of the MEMC_FREQ_RATIO configuration. + * Unit: Clocks + * PSU_DDRC_DRAMTMG0_T_FAW 0x10 + + * tRAS(max): Maximum time between activate and precharge to same bank. Thi + * s is the maximum time that a page can be kept open Minimum value of this + * register is 1. Zero is invalid. For configurations with MEMC_FREQ_RATIO + * =2, program this to (tRAS(max)-1)/2. No rounding up. Unit: Multiples of + * 1024 clocks. + * PSU_DDRC_DRAMTMG0_T_RAS_MAX 0x24 + + * tRAS(min): Minimum time between activate and precharge to the same bank. + * For configurations with MEMC_FREQ_RATIO=2, 1T mode, program this to tRA + * S(min)/2. No rounding up. For configurations with MEMC_FREQ_RATIO=2, 2T + * mode or LPDDR4 mode, program this to (tRAS(min)/2) and round it up to th + * e next integer value. Unit: Clocks + * PSU_DDRC_DRAMTMG0_T_RAS_MIN 0x12 + + * SDRAM Timing Register 0 + * (OFFSET, MASK, VALUE) (0XFD070100, 0x7F3F7F3FU ,0x11102412U) + */ + PSU_Mask_Write(DDRC_DRAMTMG0_OFFSET, 0x7F3F7F3FU, 0x11102412U); +/*##################################################################### */ + + /* + * Register : DRAMTMG1 @ 0XFD070104 + + * tXP: Minimum time after power-down exit to any operation. For DDR3, this + * should be programmed to tXPDLL if slow powerdown exit is selected in MR + * 0[12]. If C/A parity for DDR4 is used, set to (tXP+PL) instead. For conf + * igurations with MEMC_FREQ_RATIO=2, program this to (tXP/2) and round it + * up to the next integer value. Units: Clocks + * PSU_DDRC_DRAMTMG1_T_XP 0x4 + + * tRTP: Minimum time from read to precharge of same bank. - DDR2: tAL + BL + * /2 + max(tRTP, 2) - 2 - DDR3: tAL + max (tRTP, 4) - DDR4: Max of followi + * ng two equations: tAL + max (tRTP, 4) or, RL + BL/2 - tRP. - mDDR: BL/2 + * - LPDDR2: Depends on if it's LPDDR2-S2 or LPDDR2-S4: LPDDR2-S2: BL/2 + t + * RTP - 1. LPDDR2-S4: BL/2 + max(tRTP,2) - 2. - LPDDR3: BL/2 + max(tRTP,4) + * - 4 - LPDDR4: BL/2 + max(tRTP,8) - 8 For configurations with MEMC_FREQ_ + * RATIO=2, 1T mode, divide the above value by 2. No rounding up. For confi + * gurations with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, divide the abo + * ve value by 2 and round it up to the next integer value. Unit: Clocks. + * PSU_DDRC_DRAMTMG1_RD2PRE 0x4 + + * tRC: Minimum time between activates to same bank. For configurations wit + * h MEMC_FREQ_RATIO=2, program this to (tRC/2) and round up to next intege + * r value. Unit: Clocks. + * PSU_DDRC_DRAMTMG1_T_RC 0x1a + + * SDRAM Timing Register 1 + * (OFFSET, MASK, VALUE) (0XFD070104, 0x001F1F7FU ,0x0004041AU) + */ + PSU_Mask_Write(DDRC_DRAMTMG1_OFFSET, 0x001F1F7FU, 0x0004041AU); +/*##################################################################### */ + + /* + * Register : DRAMTMG2 @ 0XFD070108 + + * Set to WL Time from write command to write data on SDRAM interface. This + * must be set to WL. For mDDR, it should normally be set to 1. Note that, + * depending on the PHY, if using RDIMM, it may be necessary to use a valu + * e of WL + 1 to compensate for the extra cycle of latency through the RDI + * MM For configurations with MEMC_FREQ_RATIO=2, divide the value calculate + * d using the above equation by 2, and round it up to next integer. This r + * egister field is not required for DDR2 and DDR3 (except if MEMC_TRAINING + * is set), as the DFI read and write latencies defined in DFITMG0 and DFI + * TMG1 are sufficient for those protocols Unit: clocks + * PSU_DDRC_DRAMTMG2_WRITE_LATENCY 0x7 + + * Set to RL Time from read command to read data on SDRAM interface. This m + * ust be set to RL. Note that, depending on the PHY, if using RDIMM, it ma + * t be necessary to use a value of RL + 1 to compensate for the extra cycl + * e of latency through the RDIMM For configurations with MEMC_FREQ_RATIO=2 + * , divide the value calculated using the above equation by 2, and round i + * t up to next integer. This register field is not required for DDR2 and D + * DR3 (except if MEMC_TRAINING is set), as the DFI read and write latencie + * s defined in DFITMG0 and DFITMG1 are sufficient for those protocols Unit + * : clocks + * PSU_DDRC_DRAMTMG2_READ_LATENCY 0x8 + + * DDR2/3/mDDR: RL + BL/2 + 2 - WL DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL L + * PDDR2/LPDDR3: RL + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL LPDDR4(DQ ODT is Di + * sabled): RL + BL/2 + RU(tDQSCKmax/tCK) + WR_PREAMBLE + RD_POSTAMBLE - WL + * LPDDR4(DQ ODT is Enabled) : RL + BL/2 + RU(tDQSCKmax/tCK) + RD_POSTAMBL + * E - ODTLon - RU(tODTon(min)/tCK) Minimum time from read command to write + * command. Include time for bus turnaround and all per-bank, per-rank, an + * d global constraints. Unit: Clocks. Where: - WL = write latency - BL = b + * urst length. This must match the value programmed in the BL bit of the m + * ode register to the SDRAM - RL = read latency = CAS latency - WR_PREAMBL + * E = write preamble. This is unique to DDR4 and LPDDR4. - RD_POSTAMBLE = + * read postamble. This is unique to LPDDR4. For LPDDR2/LPDDR3/LPDDR4, if d + * erating is enabled (DERATEEN.derate_enable=1), derated tDQSCKmax should + * be used. For configurations with MEMC_FREQ_RATIO=2, divide the value cal + * culated using the above equation by 2, and round it up to next integer. + * PSU_DDRC_DRAMTMG2_RD2WR 0x6 + + * DDR4: CWL + PL + BL/2 + tWTR_L Others: CWL + BL/2 + tWTR In DDR4, minimu + * m time from write command to read command for same bank group. In others + * , minimum time from write command to read command. Includes time for bus + * turnaround, recovery times, and all per-bank, per-rank, and global cons + * traints. Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity la + * tency - BL = burst length. This must match the value programmed in the B + * L bit of the mode register to the SDRAM - tWTR_L = internal write to rea + * d command delay for same bank group. This comes directly from the SDRAM + * specification. - tWTR = internal write to read command delay. This comes + * directly from the SDRAM specification. Add one extra cycle for LPDDR2/L + * PDDR3/LPDDR4 operation. For configurations with MEMC_FREQ_RATIO=2, divid + * e the value calculated using the above equation by 2, and round it up to + * next integer. + * PSU_DDRC_DRAMTMG2_WR2RD 0xd + + * SDRAM Timing Register 2 + * (OFFSET, MASK, VALUE) (0XFD070108, 0x3F3F3F3FU ,0x0708060DU) + */ + PSU_Mask_Write(DDRC_DRAMTMG2_OFFSET, 0x3F3F3F3FU, 0x0708060DU); +/*##################################################################### */ + + /* + * Register : DRAMTMG3 @ 0XFD07010C + + * Time to wait after a mode register write or read (MRW or MRR). Present o + * nly in designs configured to support LPDDR2, LPDDR3 or LPDDR4. LPDDR2 ty + * pically requires value of 5. LPDDR3 typically requires value of 10. LPDD + * R4: Set this to the larger of tMRW and tMRWCKEL. For LPDDR2, this regist + * er is used for the time from a MRW/MRR to all other commands. For LDPDR3 + * , this register is used for the time from a MRW/MRR to a MRW/MRR. + * PSU_DDRC_DRAMTMG3_T_MRW 0x5 + + * tMRD: Cycles to wait after a mode register write or read. Depending on t + * he connected SDRAM, tMRD represents: DDR2/mDDR: Time from MRS to any com + * mand DDR3/4: Time from MRS to MRS command LPDDR2: not used LPDDR3/4: Tim + * e from MRS to non-MRS command For configurations with MEMC_FREQ_RATIO=2, + * program this to (tMRD/2) and round it up to the next integer value. If + * C/A parity for DDR4 is used, set to tMRD_PAR(tMOD+PL) instead. + * PSU_DDRC_DRAMTMG3_T_MRD 0x4 + + * tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode com + * mand and following non-load mode command. If C/A parity for DDR4 is used + * , set to tMOD_PAR(tMOD+PL) instead. Set to tMOD if MEMC_FREQ_RATIO=1, or + * tMOD/2 (rounded up to next integer) if MEMC_FREQ_RATIO=2. Note that if + * using RDIMM, depending on the PHY, it may be necessary to use a value of + * tMOD + 1 or (tMOD + 1)/2 to compensate for the extra cycle of latency a + * pplied to mode register writes by the RDIMM chip. + * PSU_DDRC_DRAMTMG3_T_MOD 0xc + + * SDRAM Timing Register 3 + * (OFFSET, MASK, VALUE) (0XFD07010C, 0x3FF3F3FFU ,0x0050400CU) + */ + PSU_Mask_Write(DDRC_DRAMTMG3_OFFSET, 0x3FF3F3FFU, 0x0050400CU); +/*##################################################################### */ + + /* + * Register : DRAMTMG4 @ 0XFD070110 + + * tRCD - tAL: Minimum time from activate to read or write command to same + * bank. For configurations with MEMC_FREQ_RATIO=2, program this to ((tRCD + * - tAL)/2) and round it up to the next integer value. Minimum value allow + * ed for this register is 1, which implies minimum (tRCD - tAL) value to b + * e 2 in configurations with MEMC_FREQ_RATIO=2. Unit: Clocks. + * PSU_DDRC_DRAMTMG4_T_RCD 0x8 + + * DDR4: tCCD_L: This is the minimum time between two reads or two writes f + * or same bank group. Others: tCCD: This is the minimum time between two r + * eads or two writes. For configurations with MEMC_FREQ_RATIO=2, program t + * his to (tCCD_L/2 or tCCD/2) and round it up to the next integer value. U + * nit: clocks. + * PSU_DDRC_DRAMTMG4_T_CCD 0x3 + + * DDR4: tRRD_L: Minimum time between activates from bank 'a' to bank 'b' f + * or same bank group. Others: tRRD: Minimum time between activates from ba + * nk 'a' to bank 'b'For configurations with MEMC_FREQ_RATIO=2, program thi + * s to (tRRD_L/2 or tRRD/2) and round it up to the next integer value. Uni + * t: Clocks. + * PSU_DDRC_DRAMTMG4_T_RRD 0x3 + + * tRP: Minimum time from precharge to activate of same bank. For MEMC_FREQ + * _RATIO=1 configurations, t_rp should be set to RoundUp(tRP/tCK). For MEM + * C_FREQ_RATIO=2 configurations, t_rp should be set to RoundDown(RoundUp(t + * RP/tCK)/2) + 1. For MEMC_FREQ_RATIO=2 configurations in LPDDR4, t_rp sho + * uld be set to RoundUp(RoundUp(tRP/tCK)/2). Unit: Clocks. + * PSU_DDRC_DRAMTMG4_T_RP 0x9 + + * SDRAM Timing Register 4 + * (OFFSET, MASK, VALUE) (0XFD070110, 0x1F0F0F1FU ,0x08030309U) + */ + PSU_Mask_Write(DDRC_DRAMTMG4_OFFSET, 0x1F0F0F1FU, 0x08030309U); +/*##################################################################### */ + + /* + * Register : DRAMTMG5 @ 0XFD070114 + + * This is the time before Self Refresh Exit that CK is maintained as a val + * id clock before issuing SRX. Specifies the clock stable time before SRX. + * Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCK + * EH - DDR2: 1 - DDR3: tCKSRX - DDR4: tCKSRX For configurations with MEMC_ + * FREQ_RATIO=2, program this to recommended value divided by two and round + * it up to next integer. + * PSU_DDRC_DRAMTMG5_T_CKSRX 0x6 + + * This is the time after Self Refresh Down Entry that CK is maintained as + * a valid clock. Specifies the clock disable delay after SRE. Recommended + * settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL - DDR2: 1 + * - DDR3: max (10 ns, 5 tCK) - DDR4: max (10 ns, 5 tCK) For configurations + * with MEMC_FREQ_RATIO=2, program this to recommended value divided by tw + * o and round it up to next integer. + * PSU_DDRC_DRAMTMG5_T_CKSRE 0x6 + + * Minimum CKE low width for Self refresh or Self refresh power down entry + * to exit timing in memory clock cycles. Recommended settings: - mDDR: tRF + * C - LPDDR2: tCKESR - LPDDR3: tCKESR - LPDDR4: max(tCKELPD, tSR) - DDR2: + * tCKE - DDR3: tCKE + 1 - DDR4: tCKE + 1 For configurations with MEMC_FREQ + * _RATIO=2, program this to recommended value divided by two and round it + * up to next integer. + * PSU_DDRC_DRAMTMG5_T_CKESR 0x4 + + * Minimum number of cycles of CKE HIGH/LOW during power-down and self refr + * esh. - LPDDR2/LPDDR3 mode: Set this to the larger of tCKE or tCKESR - LP + * DDR4 mode: Set this to the larger of tCKE, tCKELPD or tSR. - Non-LPDDR2/ + * non-LPDDR3/non-LPDDR4 designs: Set this to tCKE value. For configuration + * s with MEMC_FREQ_RATIO=2, program this to (value described above)/2 and + * round it up to the next integer value. Unit: Clocks. + * PSU_DDRC_DRAMTMG5_T_CKE 0x3 + + * SDRAM Timing Register 5 + * (OFFSET, MASK, VALUE) (0XFD070114, 0x0F0F3F1FU ,0x06060403U) + */ + PSU_Mask_Write(DDRC_DRAMTMG5_OFFSET, 0x0F0F3F1FU, 0x06060403U); +/*##################################################################### */ + + /* + * Register : DRAMTMG6 @ 0XFD070118 + + * This is the time after Deep Power Down Entry that CK is maintained as a + * valid clock. Specifies the clock disable delay after DPDE. Recommended s + * ettings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 For configurations with MEMC_ + * FREQ_RATIO=2, program this to recommended value divided by two and round + * it up to next integer. This is only present for designs supporting mDDR + * or LPDDR2/LPDDR3 devices. + * PSU_DDRC_DRAMTMG6_T_CKDPDE 0x1 + + * This is the time before Deep Power Down Exit that CK is maintained as a + * valid clock before issuing DPDX. Specifies the clock stable time before + * DPDX. Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 For config + * urations with MEMC_FREQ_RATIO=2, program this to recommended value divid + * ed by two and round it up to next integer. This is only present for desi + * gns supporting mDDR or LPDDR2 devices. + * PSU_DDRC_DRAMTMG6_T_CKDPDX 0x1 + + * This is the time before Clock Stop Exit that CK is maintained as a valid + * clock before issuing Clock Stop Exit. Specifies the clock stable time b + * efore next command after Clock Stop Exit. Recommended settings: - mDDR: + * 1 - LPDDR2: tXP + 2 - LPDDR3: tXP + 2 - LPDDR4: tXP + 2 For configuratio + * ns with MEMC_FREQ_RATIO=2, program this to recommended value divided by + * two and round it up to next integer. This is only present for designs su + * pporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices. + * PSU_DDRC_DRAMTMG6_T_CKCSX 0x4 + + * SDRAM Timing Register 6 + * (OFFSET, MASK, VALUE) (0XFD070118, 0x0F0F000FU ,0x01010004U) + */ + PSU_Mask_Write(DDRC_DRAMTMG6_OFFSET, 0x0F0F000FU, 0x01010004U); +/*##################################################################### */ + + /* + * Register : DRAMTMG7 @ 0XFD07011C + + * This is the time after Power Down Entry that CK is maintained as a valid + * clock. Specifies the clock disable delay after PDE. Recommended setting + * s: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL For configuration + * s with MEMC_FREQ_RATIO=2, program this to recommended value divided by t + * wo and round it up to next integer. This is only present for designs sup + * porting mDDR or LPDDR2/LPDDR3/LPDDR4 devices. + * PSU_DDRC_DRAMTMG7_T_CKPDE 0x6 + + * This is the time before Power Down Exit that CK is maintained as a valid + * clock before issuing PDX. Specifies the clock stable time before PDX. R + * ecommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: 2 For c + * onfigurations with MEMC_FREQ_RATIO=2, program this to recommended value + * divided by two and round it up to next integer. This is only present for + * designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices. + * PSU_DDRC_DRAMTMG7_T_CKPDX 0x6 + + * SDRAM Timing Register 7 + * (OFFSET, MASK, VALUE) (0XFD07011C, 0x00000F0FU ,0x00000606U) + */ + PSU_Mask_Write(DDRC_DRAMTMG7_OFFSET, 0x00000F0FU, 0x00000606U); +/*##################################################################### */ + + /* + * Register : DRAMTMG8 @ 0XFD070120 + + * tXS_FAST: Exit Self Refresh to ZQCL, ZQCS and MRS (only CL, WR, RTP and + * Geardown mode). For configurations with MEMC_FREQ_RATIO=2, program this + * to the above value divided by 2 and round up to next integer value. Unit + * : Multiples of 32 clocks. Note: This is applicable to only ZQCL/ZQCS com + * mands. Note: Ensure this is less than or equal to t_xs_x32. + * PSU_DDRC_DRAMTMG8_T_XS_FAST_X32 0x3 + + * tXS_ABORT: Exit Self Refresh to commands not requiring a locked DLL in S + * elf Refresh Abort. For configurations with MEMC_FREQ_RATIO=2, program th + * is to the above value divided by 2 and round up to next integer value. U + * nit: Multiples of 32 clocks. Note: Ensure this is less than or equal to + * t_xs_x32. + * PSU_DDRC_DRAMTMG8_T_XS_ABORT_X32 0x3 + + * tXSDLL: Exit Self Refresh to commands requiring a locked DLL. For config + * urations with MEMC_FREQ_RATIO=2, program this to the above value divided + * by 2 and round up to next integer value. Unit: Multiples of 32 clocks. + * Note: Used only for DDR2, DDR3 and DDR4 SDRAMs. + * PSU_DDRC_DRAMTMG8_T_XS_DLL_X32 0xd + + * tXS: Exit Self Refresh to commands not requiring a locked DLL. For confi + * gurations with MEMC_FREQ_RATIO=2, program this to the above value divide + * d by 2 and round up to next integer value. Unit: Multiples of 32 clocks. + * Note: Used only for DDR2, DDR3 and DDR4 SDRAMs. + * PSU_DDRC_DRAMTMG8_T_XS_X32 0x6 + + * SDRAM Timing Register 8 + * (OFFSET, MASK, VALUE) (0XFD070120, 0x7F7F7F7FU ,0x03030D06U) + */ + PSU_Mask_Write(DDRC_DRAMTMG8_OFFSET, 0x7F7F7F7FU, 0x03030D06U); +/*##################################################################### */ + + /* + * Register : DRAMTMG9 @ 0XFD070124 + + * DDR4 Write preamble mode - 0: 1tCK preamble - 1: 2tCK preamble Present o + * nly with MEMC_FREQ_RATIO=2 + * PSU_DDRC_DRAMTMG9_DDR4_WR_PREAMBLE 0x0 + + * tCCD_S: This is the minimum time between two reads or two writes for dif + * ferent bank group. For bank switching (from bank 'a' to bank 'b'), the m + * inimum time is this value + 1. For configurations with MEMC_FREQ_RATIO=2 + * , program this to (tCCD_S/2) and round it up to the next integer value. + * Present only in designs configured to support DDR4. Unit: clocks. + * PSU_DDRC_DRAMTMG9_T_CCD_S 0x2 + + * tRRD_S: Minimum time between activates from bank 'a' to bank 'b' for dif + * ferent bank group. For configurations with MEMC_FREQ_RATIO=2, program th + * is to (tRRD_S/2) and round it up to the next integer value. Present only + * in designs configured to support DDR4. Unit: Clocks. + * PSU_DDRC_DRAMTMG9_T_RRD_S 0x2 + + * CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command + * for different bank group. Includes time for bus turnaround, recovery ti + * mes, and all per-bank, per-rank, and global constraints. Present only in + * designs configured to support DDR4. Unit: Clocks. Where: - CWL = CAS wr + * ite latency - PL = Parity latency - BL = burst length. This must match t + * he value programmed in the BL bit of the mode register to the SDRAM - tW + * TR_S = internal write to read command delay for different bank group. Th + * is comes directly from the SDRAM specification. For configurations with + * MEMC_FREQ_RATIO=2, divide the value calculated using the above equation + * by 2, and round it up to next integer. + * PSU_DDRC_DRAMTMG9_WR2RD_S 0xb + + * SDRAM Timing Register 9 + * (OFFSET, MASK, VALUE) (0XFD070124, 0x40070F3FU ,0x0002020BU) + */ + PSU_Mask_Write(DDRC_DRAMTMG9_OFFSET, 0x40070F3FU, 0x0002020BU); +/*##################################################################### */ + + /* + * Register : DRAMTMG11 @ 0XFD07012C + + * tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DL + * L. For configurations with MEMC_FREQ_RATIO=2, program this to (tXMPDLL/2 + * ) and round it up to the next integer value. Present only in designs con + * figured to support DDR4. Unit: Multiples of 32 clocks. + * PSU_DDRC_DRAMTMG11_POST_MPSM_GAP_X32 0x70 + + * tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge. For + * configurations with MEMC_FREQ_RATIO=2, program this to RoundUp(tMPX_LH/2 + * )+1. Present only in designs configured to support DDR4. Unit: clocks. + * PSU_DDRC_DRAMTMG11_T_MPX_LH 0x7 + + * tMPX_S: Minimum time CS setup time to CKE. For configurations with MEMC_ + * FREQ_RATIO=2, program this to (tMPX_S/2) and round it up to the next int + * eger value. Present only in designs configured to support DDR4. Unit: Cl + * ocks. + * PSU_DDRC_DRAMTMG11_T_MPX_S 0x1 + + * tCKMPE: Minimum valid clock requirement after MPSM entry. Present only i + * n designs configured to support DDR4. Unit: Clocks. For configurations w + * ith MEMC_FREQ_RATIO=2, divide the value calculated using the above equat + * ion by 2, and round it up to next integer. + * PSU_DDRC_DRAMTMG11_T_CKMPE 0xe + + * SDRAM Timing Register 11 + * (OFFSET, MASK, VALUE) (0XFD07012C, 0x7F1F031FU ,0x7007010EU) + */ + PSU_Mask_Write(DDRC_DRAMTMG11_OFFSET, 0x7F1F031FU, 0x7007010EU); +/*##################################################################### */ + + /* + * Register : DRAMTMG12 @ 0XFD070130 + + * tCMDCKE: Delay from valid command to CKE input LOW. Set this to the larg + * er of tESCKE or tCMDCKE For configurations with MEMC_FREQ_RATIO=2, progr + * am this to (max(tESCKE, tCMDCKE)/2) and round it up to next integer valu + * e. + * PSU_DDRC_DRAMTMG12_T_CMDCKE 0x2 + + * tCKEHCMD: Valid command requirement after CKE input HIGH. For configurat + * ions with MEMC_FREQ_RATIO=2, program this to (tCKEHCMD/2) and round it u + * p to next integer value. + * PSU_DDRC_DRAMTMG12_T_CKEHCMD 0x6 + + * tMRD_PDA: This is the Mode Register Set command cycle time in PDA mode. + * For configurations with MEMC_FREQ_RATIO=2, program this to (tMRD_PDA/2) + * and round it up to next integer value. + * PSU_DDRC_DRAMTMG12_T_MRD_PDA 0x8 + + * SDRAM Timing Register 12 + * (OFFSET, MASK, VALUE) (0XFD070130, 0x00030F1FU ,0x00020608U) + */ + PSU_Mask_Write(DDRC_DRAMTMG12_OFFSET, 0x00030F1FU, 0x00020608U); +/*##################################################################### */ + + /* + * Register : ZQCTL0 @ 0XFD070180 + + * - 1 - Disable uMCTL2 generation of ZQCS/MPC(ZQ calibration) command. Reg + * ister DBGCMD.zq_calib_short can be used instead to issue ZQ calibration + * request from APB module. - 0 - Internally generate ZQCS/MPC(ZQ calibrati + * on) commands based on ZQCTL1.t_zq_short_interval_x1024. This is only pre + * sent for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. + * PSU_DDRC_ZQCTL0_DIS_AUTO_ZQ 0x1 + + * - 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refres + * h/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 + * or LPDDR3 or LPDDR4 mode. - 0 - Enable issuing of ZQCL/MPC(ZQ calibratio + * n) command at Self-Refresh/SR-Powerdown exit. Only applicable when run i + * n DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. This is only present + * for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. + * PSU_DDRC_ZQCTL0_DIS_SRX_ZQCL 0x0 + + * - 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQC + * L/ZQCS/MPC(ZQ calibration) commands are sent to one rank at a time with + * tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that co + * mmands to different ranks do not overlap. - 0 - ZQ resistor is not share + * d. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR + * 3/LPDDR4 devices. + * PSU_DDRC_ZQCTL0_ZQ_RESISTOR_SHARED 0x0 + + * - 1 - Disable issuing of ZQCL command at Maximum Power Saving Mode exit. + * Only applicable when run in DDR4 mode. - 0 - Enable issuing of ZQCL com + * mand at Maximum Power Saving Mode exit. Only applicable when run in DDR4 + * mode. This is only present for designs supporting DDR4 devices. + * PSU_DDRC_ZQCTL0_DIS_MPSMX_ZQCL 0x0 + + * tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Numbe + * r of cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ St + * art) command is issued to SDRAM. For configurations with MEMC_FREQ_RATIO + * =2: DDR3/DDR4: program this to tZQoper/2 and round it up to the next int + * eger value. LPDDR2/LPDDR3: program this to tZQCL/2 and round it up to th + * e next integer value. LPDDR4: program this to tZQCAL/2 and round it up t + * o the next integer value. Unit: Clock cycles. This is only present for d + * esigns supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. + * PSU_DDRC_ZQCTL0_T_ZQ_LONG_NOP 0x100 + + * tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of cycles of + * NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command + * is issued to SDRAM. For configurations with MEMC_FREQ_RATIO=2, program t + * his to tZQCS/2 and round it up to the next integer value. Unit: Clock cy + * cles. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LP + * DDR3/LPDDR4 devices. + * PSU_DDRC_ZQCTL0_T_ZQ_SHORT_NOP 0x40 + + * ZQ Control Register 0 + * (OFFSET, MASK, VALUE) (0XFD070180, 0xF7FF03FFU ,0x81000040U) + */ + PSU_Mask_Write(DDRC_ZQCTL0_OFFSET, 0xF7FF03FFU, 0x81000040U); +/*##################################################################### */ + + /* + * Register : ZQCTL1 @ 0XFD070184 + + * tZQReset: Number of cycles of NOP required after a ZQReset (ZQ calibrati + * on Reset) command is issued to SDRAM. For configurations with MEMC_FREQ_ + * RATIO=2, program this to tZQReset/2 and round it up to the next integer + * value. Unit: Clock cycles. This is only present for designs supporting L + * PDDR2/LPDDR3/LPDDR4 devices. + * PSU_DDRC_ZQCTL1_T_ZQ_RESET_NOP 0x20 + + * Average interval to wait between automatically issuing ZQCS (ZQ calibrat + * ion short)/MPC(ZQ calibration) commands to DDR3/DDR4/LPDDR2/LPDDR3/LPDDR + * 4 devices. Meaningless, if ZQCTL0.dis_auto_zq=1. Unit: 1024 clock cycles + * . This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3 + * /LPDDR4 devices. + * PSU_DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024 0x196dc + + * ZQ Control Register 1 + * (OFFSET, MASK, VALUE) (0XFD070184, 0x3FFFFFFFU ,0x020196DCU) + */ + PSU_Mask_Write(DDRC_ZQCTL1_OFFSET, 0x3FFFFFFFU, 0x020196DCU); +/*##################################################################### */ + + /* + * Register : DFITMG0 @ 0XFD070190 + + * Specifies the number of DFI clock cycles after an assertion or de-assert + * ion of the DFI control signals that the control signals at the PHY-DRAM + * interface reflect the assertion or de-assertion. If the DFI clock and th + * e memory clock are not phase-aligned, this timing parameter should be ro + * unded up to the next integer value. Note that if using RDIMM, it is nece + * ssary to increment this parameter by RDIMM's extra cycle of latency in t + * erms of DFI clock. + * PSU_DDRC_DFITMG0_DFI_T_CTRL_DELAY 0x4 + + * Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated u + * sing HDR or SDR values Selects whether value in DFITMG0.dfi_t_rddata_en + * is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles + * - 1 in terms of SDR clock cycles Refer to PHY specification for correct + * value. + * PSU_DDRC_DFITMG0_DFI_RDDATA_USE_SDR 0x1 + + * Time from the assertion of a read command on the DFI interface to the as + * sertion of the dfi_rddata_en signal. Refer to PHY specification for corr + * ect value. This corresponds to the DFI parameter trddata_en. Note that, + * depending on the PHY, if using RDIMM, it may be necessary to use the val + * ue (CL + 1) in the calculation of trddata_en. This is to compensate for + * the extra cycle of latency through the RDIMM. Unit: Clocks + * PSU_DDRC_DFITMG0_DFI_T_RDDATA_EN 0xb + + * Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated us + * ing HDR or SDR values Selects whether value in DFITMG0.dfi_tphy_wrlat is + * in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.df + * i_tphy_wrdata is in terms of SDR or HDR clock cycles - 0 in terms of HDR + * clock cycles - 1 in terms of SDR clock cycles Refer to PHY specificatio + * n for correct value. + * PSU_DDRC_DFITMG0_DFI_WRDATA_USE_SDR 0x1 + + * Specifies the number of clock cycles between when dfi_wrdata_en is asser + * ted to when the associated write data is driven on the dfi_wrdata signal + * . This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY + * specification for correct value. Note, max supported value is 8. Unit: + * Clocks + * PSU_DDRC_DFITMG0_DFI_TPHY_WRDATA 0x2 + + * Write latency Number of clocks from the write command to write data enab + * le (dfi_wrdata_en). This corresponds to the DFI timing parameter tphy_wr + * lat. Refer to PHY specification for correct value.Note that, depending o + * n the PHY, if using RDIMM, it may be necessary to use the value (CL + 1) + * in the calculation of tphy_wrlat. This is to compensate for the extra c + * ycle of latency through the RDIMM. + * PSU_DDRC_DFITMG0_DFI_TPHY_WRLAT 0xb + + * DFI Timing Register 0 + * (OFFSET, MASK, VALUE) (0XFD070190, 0x1FBFBF3FU ,0x048B820BU) + */ + PSU_Mask_Write(DDRC_DFITMG0_OFFSET, 0x1FBFBF3FU, 0x048B820BU); +/*##################################################################### */ + + /* + * Register : DFITMG1 @ 0XFD070194 + + * Specifies the number of DFI PHY clocks between when the dfi_cs signal is + * asserted and when the associated command is driven. This field is used + * for CAL mode, should be set to '0' or the value which matches the CAL mo + * de register setting in the DRAM. If the PHY can add the latency for CAL + * mode, this should be set to '0'. Valid Range: 0, 3, 4, 5, 6, and 8 + * PSU_DDRC_DFITMG1_DFI_T_CMD_LAT 0x0 + + * Specifies the number of DFI PHY clocks between when the dfi_cs signal is + * asserted and when the associated dfi_parity_in signal is driven. + * PSU_DDRC_DFITMG1_DFI_T_PARIN_LAT 0x0 + + * Specifies the number of DFI clocks between when the dfi_wrdata_en signal + * is asserted and when the corresponding write data transfer is completed + * on the DRAM bus. This corresponds to the DFI timing parameter twrdata_d + * elay. Refer to PHY specification for correct value. For DFI 3.0 PHY, set + * to twrdata_delay, a new timing parameter introduced in DFI 3.0. For DFI + * 2.1 PHY, set to tphy_wrdata + (delay of DFI write data to the DRAM). Va + * lue to be programmed is in terms of DFI clocks, not PHY clocks. In FREQ_ + * RATIO=2, divide PHY's value by 2 and round up to next integer. If using + * DFITMG0.dfi_wrdata_use_sdr=1, add 1 to the value. Unit: Clocks + * PSU_DDRC_DFITMG1_DFI_T_WRDATA_DELAY 0x3 + + * Specifies the number of DFI clock cycles from the assertion of the dfi_d + * ram_clk_disable signal on the DFI until the clock to the DRAM memory dev + * ices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock + * and the memory clock are not phase aligned, this timing parameter should + * be rounded up to the next integer value. + * PSU_DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE 0x3 + + * Specifies the number of DFI clock cycles from the de-assertion of the df + * i_dram_clk_disable signal on the DFI until the first valid rising edge o + * f the clock to the DRAM memory devices, at the PHY-DRAM boundary. If the + * DFI clock and the memory clock are not phase aligned, this timing param + * eter should be rounded up to the next integer value. + * PSU_DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE 0x4 + + * DFI Timing Register 1 + * (OFFSET, MASK, VALUE) (0XFD070194, 0xF31F0F0FU ,0x00030304U) + */ + PSU_Mask_Write(DDRC_DFITMG1_OFFSET, 0xF31F0F0FU, 0x00030304U); +/*##################################################################### */ + + /* + * Register : DFILPCFG0 @ 0XFD070198 + + * Setting for DFI's tlp_resp time. Same value is used for both Power Down, + * Self Refresh, Deep Power Down and Maximum Power Saving modes. DFI 2.1 s + * pecification onwards, recommends using a fixed value of 7 always. + * PSU_DDRC_DFILPCFG0_DFI_TLP_RESP 0x7 + + * Value to drive on dfi_lp_wakeup signal when Deep Power Down mode is ente + * red. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32 + * cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 5 + * 12 cycles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycles - + * 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 6553 + * 6 cycles - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited T + * his is only present for designs supporting mDDR or LPDDR2/LPDDR3 devices + * . + * PSU_DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD 0x0 + + * Enables DFI Low Power interface handshaking during Deep Power Down Entry + * /Exit. - 0 - Disabled - 1 - Enabled This is only present for designs sup + * porting mDDR or LPDDR2/LPDDR3 devices. + * PSU_DDRC_DFILPCFG0_DFI_LP_EN_DPD 0x0 + + * Value to drive on dfi_lp_wakeup signal when Self Refresh mode is entered + * . Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32 cyc + * les - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 + * cycles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycles - 0x9 + * - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 c + * ycles - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited + * PSU_DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR 0x0 + + * Enables DFI Low Power interface handshaking during Self Refresh Entry/Ex + * it. - 0 - Disabled - 1 - Enabled + * PSU_DDRC_DFILPCFG0_DFI_LP_EN_SR 0x1 + + * Value to drive on dfi_lp_wakeup signal when Power Down mode is entered. + * Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32 cycle + * s - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cy + * cles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycles - 0x9 - + * 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cyc + * les - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited + * PSU_DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD 0x0 + + * Enables DFI Low Power interface handshaking during Power Down Entry/Exit + * . - 0 - Disabled - 1 - Enabled + * PSU_DDRC_DFILPCFG0_DFI_LP_EN_PD 0x1 + + * DFI Low Power Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD070198, 0x0FF1F1F1U ,0x07000101U) + */ + PSU_Mask_Write(DDRC_DFILPCFG0_OFFSET, 0x0FF1F1F1U, 0x07000101U); +/*##################################################################### */ + + /* + * Register : DFILPCFG1 @ 0XFD07019C + + * Value to drive on dfi_lp_wakeup signal when Maximum Power Saving Mode is + * entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 + * - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x + * 5 - 512 cycles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycl + * es - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - + * 65536 cycles - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimi + * ted This is only present for designs supporting DDR4 devices. + * PSU_DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM 0x2 + + * Enables DFI Low Power interface handshaking during Maximum Power Saving + * Mode Entry/Exit. - 0 - Disabled - 1 - Enabled This is only present for d + * esigns supporting DDR4 devices. + * PSU_DDRC_DFILPCFG1_DFI_LP_EN_MPSM 0x1 + + * DFI Low Power Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD07019C, 0x000000F1U ,0x00000021U) + */ + PSU_Mask_Write(DDRC_DFILPCFG1_OFFSET, 0x000000F1U, 0x00000021U); +/*##################################################################### */ + + /* + * Register : DFIUPD0 @ 0XFD0701A0 + + * When '1', disable the automatic dfi_ctrlupd_req generation by the uMCTL2 + * . The core must issue the dfi_ctrlupd_req signal using register reg_ddrc + * _ctrlupd. When '0', uMCTL2 issues dfi_ctrlupd_req periodically. + * PSU_DDRC_DFIUPD0_DIS_AUTO_CTRLUPD 0x0 + + * When '1', disable the automatic dfi_ctrlupd_req generation by the uMCTL2 + * following a self-refresh exit. The core must issue the dfi_ctrlupd_req + * signal using register reg_ddrc_ctrlupd. When '0', uMCTL2 issues a dfi_ct + * rlupd_req after exiting self-refresh. + * PSU_DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX 0x0 + + * Specifies the maximum number of clock cycles that the dfi_ctrlupd_req si + * gnal can assert. Lowest value to assign to this variable is 0x40. Unit: + * Clocks + * PSU_DDRC_DFIUPD0_DFI_T_CTRLUP_MAX 0x40 + + * Specifies the minimum number of clock cycles that the dfi_ctrlupd_req si + * gnal must be asserted. The uMCTL2 expects the PHY to respond within this + * time. If the PHY does not respond, the uMCTL2 will de-assert dfi_ctrlup + * d_req after dfi_t_ctrlup_min + 2 cycles. Lowest value to assign to this + * variable is 0x3. Unit: Clocks + * PSU_DDRC_DFIUPD0_DFI_T_CTRLUP_MIN 0x3 + + * DFI Update Register 0 + * (OFFSET, MASK, VALUE) (0XFD0701A0, 0xC3FF03FFU ,0x00400003U) + */ + PSU_Mask_Write(DDRC_DFIUPD0_OFFSET, 0xC3FF03FFU, 0x00400003U); +/*##################################################################### */ + + /* + * Register : DFIUPD1 @ 0XFD0701A4 + + * This is the minimum amount of time between uMCTL2 initiated DFI update r + * equests (which is executed whenever the uMCTL2 is idle). Set this number + * higher to reduce the frequency of update requests, which can have a sma + * ll impact on the latency of the first read request when the uMCTL2 is id + * le. Unit: 1024 clocks + * PSU_DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024 0x41 + + * This is the maximum amount of time between uMCTL2 initiated DFI update r + * equests. This timer resets with each update request; when the timer expi + * res dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd + * _ackx is received. PHY can use this idle time to recalibrate the delay l + * ines to the DLLs. The DFI controller update is also used to reset PHY FI + * FO pointers in case of data capture errors. Updates are required to main + * tain calibration over PVT, but frequent updates may impact performance. + * Note: Value programmed for DFIUPD1.dfi_t_ctrlupd_interval_max_x1024 must + * be greater than DFIUPD1.dfi_t_ctrlupd_interval_min_x1024. Unit: 1024 cl + * ocks + * PSU_DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024 0xe1 + + * DFI Update Register 1 + * (OFFSET, MASK, VALUE) (0XFD0701A4, 0x00FF00FFU ,0x004100E1U) + */ + PSU_Mask_Write(DDRC_DFIUPD1_OFFSET, 0x00FF00FFU, 0x004100E1U); +/*##################################################################### */ + + /* + * Register : DFIMISC @ 0XFD0701B0 + + * Defines polarity of dfi_wrdata_cs and dfi_rddata_cs signals. - 0: Signal + * s are active low - 1: Signals are active high + * PSU_DDRC_DFIMISC_DFI_DATA_CS_POLARITY 0x0 + + * DBI implemented in DDRC or PHY. - 0 - DDRC implements DBI functionality. + * - 1 - PHY implements DBI functionality. Present only in designs configu + * red to support DDR4 and LPDDR4. + * PSU_DDRC_DFIMISC_PHY_DBI_MODE 0x0 + + * PHY initialization complete enable signal. When asserted the dfi_init_co + * mplete signal can be used to trigger SDRAM initialisation + * PSU_DDRC_DFIMISC_DFI_INIT_COMPLETE_EN 0x0 + + * DFI Miscellaneous Control Register + * (OFFSET, MASK, VALUE) (0XFD0701B0, 0x00000007U ,0x00000000U) + */ + PSU_Mask_Write(DDRC_DFIMISC_OFFSET, 0x00000007U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : DFITMG2 @ 0XFD0701B4 + + * >Number of clocks between when a read command is sent on the DFI control + * interface and when the associated dfi_rddata_cs signal is asserted. Thi + * s corresponds to the DFI timing parameter tphy_rdcslat. Refer to PHY spe + * cification for correct value. + * PSU_DDRC_DFITMG2_DFI_TPHY_RDCSLAT 0x9 + + * Number of clocks between when a write command is sent on the DFI control + * interface and when the associated dfi_wrdata_cs signal is asserted. Thi + * s corresponds to the DFI timing parameter tphy_wrcslat. Refer to PHY spe + * cification for correct value. + * PSU_DDRC_DFITMG2_DFI_TPHY_WRCSLAT 0x6 + + * DFI Timing Register 2 + * (OFFSET, MASK, VALUE) (0XFD0701B4, 0x00003F3FU ,0x00000906U) + */ + PSU_Mask_Write(DDRC_DFITMG2_OFFSET, 0x00003F3FU, 0x00000906U); +/*##################################################################### */ + + /* + * Register : DBICTL @ 0XFD0701C0 + + * Read DBI enable signal in DDRC. - 0 - Read DBI is disabled. - 1 - Read D + * BI is enabled. This signal must be set the same value as DRAM's mode reg + * ister. - DDR4: MR5 bit A12. When x4 devices are used, this signal must b + * e set to 0. - LPDDR4: MR3[6] + * PSU_DDRC_DBICTL_RD_DBI_EN 0x0 + + * Write DBI enable signal in DDRC. - 0 - Write DBI is disabled. - 1 - Writ + * e DBI is enabled. This signal must be set the same value as DRAM's mode + * register. - DDR4: MR5 bit A11. When x4 devices are used, this signal mus + * t be set to 0. - LPDDR4: MR3[7] + * PSU_DDRC_DBICTL_WR_DBI_EN 0x0 + + * DM enable signal in DDRC. - 0 - DM is disabled. - 1 - DM is enabled. Thi + * s signal must be set the same logical value as DRAM's mode register. - D + * DR4: Set this to same value as MR5 bit A10. When x4 devices are used, th + * is signal must be set to 0. - LPDDR4: Set this to inverted value of MR13 + * [5] which is opposite polarity from this signal + * PSU_DDRC_DBICTL_DM_EN 0x1 + + * DM/DBI Control Register + * (OFFSET, MASK, VALUE) (0XFD0701C0, 0x00000007U ,0x00000001U) + */ + PSU_Mask_Write(DDRC_DBICTL_OFFSET, 0x00000007U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : ADDRMAP0 @ 0XFD070200 + + * Selects the HIF address bit used as rank address bit 0. Valid Range: 0 t + * o 27, and 31 Internal Base: 6 The selected HIF address bit is determined + * by adding the internal base to the value of this field. If set to 31, r + * ank address bit 0 is set to 0. + * PSU_DDRC_ADDRMAP0_ADDRMAP_CS_BIT0 0x1f + + * Address Map Register 0 + * (OFFSET, MASK, VALUE) (0XFD070200, 0x0000001FU ,0x0000001FU) + */ + PSU_Mask_Write(DDRC_ADDRMAP0_OFFSET, 0x0000001FU, 0x0000001FU); +/*##################################################################### */ + + /* + * Register : ADDRMAP1 @ 0XFD070204 + + * Selects the HIF address bit used as bank address bit 2. Valid Range: 0 t + * o 29 and 31 Internal Base: 4 The selected HIF address bit is determined + * by adding the internal base to the value of this field. If set to 31, ba + * nk address bit 2 is set to 0. + * PSU_DDRC_ADDRMAP1_ADDRMAP_BANK_B2 0x1f + + * Selects the HIF address bits used as bank address bit 1. Valid Range: 0 + * to 30 Internal Base: 3 The selected HIF address bit for each of the bank + * address bits is determined by adding the internal base to the value of + * this field. + * PSU_DDRC_ADDRMAP1_ADDRMAP_BANK_B1 0xa + + * Selects the HIF address bits used as bank address bit 0. Valid Range: 0 + * to 30 Internal Base: 2 The selected HIF address bit for each of the bank + * address bits is determined by adding the internal base to the value of + * this field. + * PSU_DDRC_ADDRMAP1_ADDRMAP_BANK_B0 0xa + + * Address Map Register 1 + * (OFFSET, MASK, VALUE) (0XFD070204, 0x001F1F1FU ,0x001F0A0AU) + */ + PSU_Mask_Write(DDRC_ADDRMAP1_OFFSET, 0x001F1F1FU, 0x001F0A0AU); +/*##################################################################### */ + + /* + * Register : ADDRMAP2 @ 0XFD070208 + + * - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 5. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 6. - Quarter bus width mode: Selects the HIF address bit + * used as column address bit 7 . Valid Range: 0 to 7, and 15 Internal Base + * : 5 The selected HIF address bit is determined by adding the internal ba + * se to the value of this field. If set to 15, this column address bit is + * set to 0. + * PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B5 0x0 + + * - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 4. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 5. - Quarter bus width mode: Selects the HIF address bit + * used as column address bit 6. Valid Range: 0 to 7, and 15 Internal Base: + * 4 The selected HIF address bit is determined by adding the internal bas + * e to the value of this field. If set to 15, this column address bit is s + * et to 0. + * PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B4 0x0 + + * - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 3. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 4. - Quarter bus width mode: Selects the HIF address bit + * used as column address bit 5. Valid Range: 0 to 7 Internal Base: 3 The s + * elected HIF address bit is determined by adding the internal base to the + * value of this field. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=1 + * 6, it is required to program this to 0, hence register does not exist in + * this case. + * PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B3 0x0 + + * - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 2. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 3. - Quarter bus width mode: Selects the HIF address bit + * used as column address bit 4. Valid Range: 0 to 7 Internal Base: 2 The s + * elected HIF address bit is determined by adding the internal base to the + * value of this field. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=8 + * or 16, it is required to program this to 0. + * PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B2 0x0 + + * Address Map Register 2 + * (OFFSET, MASK, VALUE) (0XFD070208, 0x0F0F0F0FU ,0x00000000U) + */ + PSU_Mask_Write(DDRC_ADDRMAP2_OFFSET, 0x0F0F0F0FU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ADDRMAP3 @ 0XFD07020C + + * - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 9. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 11 (10 in LPDDR2/LPDDR3 mode). - Quarter bus width mode: + * Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/ + * LPDDR3 mode). Valid Range: 0 to 7, and 15 Internal Base: 9 The selected + * HIF address bit is determined by adding the internal base to the value o + * f this field. If set to 15, this column address bit is set to 0. Note: P + * er JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved fo + * r indicating auto-precharge, and hence no source address bit can be mapp + * ed to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit + * for auto-precharge in the CA bus and hence column bit 10 is used. + * PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B9 0x0 + + * - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 8. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 9. - Quarter bus width mode: Selects the HIF address bit + * used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). Valid Range: 0 + * to 7, and 15 Internal Base: 8 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specifi + * cation, column address bit 10 is reserved for indicating auto-precharge, + * and hence no source address bit can be mapped to column address bit 10. + * In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA + * bus and hence column bit 10 is used. + * PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B8 0x0 + + * - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 7. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 8. - Quarter bus width mode: Selects the HIF address bit + * used as column address bit 9. Valid Range: 0 to 7, and 15 Internal Base: + * 7 The selected HIF address bit is determined by adding the internal bas + * e to the value of this field. If set to 15, this column address bit is s + * et to 0. + * PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B7 0x0 + + * - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 6. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 7. - Quarter bus width mode: Selects the HIF address bit + * used as column address bit 8. Valid Range: 0 to 7, and 15 Internal Base: + * 6 The selected HIF address bit is determined by adding the internal bas + * e to the value of this field. If set to 15, this column address bit is s + * et to 0. + * PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B6 0x0 + + * Address Map Register 3 + * (OFFSET, MASK, VALUE) (0XFD07020C, 0x0F0F0F0FU ,0x00000000U) + */ + PSU_Mask_Write(DDRC_ADDRMAP3_OFFSET, 0x0F0F0F0FU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ADDRMAP4 @ 0XFD070210 + + * - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 13 (11 in LPDDR2/LPDDR3 mode). - Half bus width mode: Unused. To m + * ake it unused, this should be tied to 4'hF. - Quarter bus width mode: Un + * used. To make it unused, this must be tied to 4'hF. Valid Range: 0 to 7, + * and 15 Internal Base: 11 The selected HIF address bit is determined by + * adding the internal base to the value of this field. If set to 15, this + * column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specificatio + * n, column address bit 10 is reserved for indicating auto-precharge, and + * hence no source address bit can be mapped to column address bit 10. In L + * PDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus + * and hence column bit 10 is used. + * PSU_DDRC_ADDRMAP4_ADDRMAP_COL_B11 0xf + + * - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 11 (10 in LPDDR2/LPDDR3 mode). - Half bus width mode: Selects the + * HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode) + * . - Quarter bus width mode: UNUSED. To make it unused, this must be tied + * to 4'hF. Valid Range: 0 to 7, and 15 Internal Base: 10 The selected HIF + * address bit is determined by adding the internal base to the value of t + * his field. If set to 15, this column address bit is set to 0. Note: Per + * JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for i + * ndicating auto-precharge, and hence no source address bit can be mapped + * to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for + * auto-precharge in the CA bus and hence column bit 10 is used. + * PSU_DDRC_ADDRMAP4_ADDRMAP_COL_B10 0xf + + * Address Map Register 4 + * (OFFSET, MASK, VALUE) (0XFD070210, 0x00000F0FU ,0x00000F0FU) + */ + PSU_Mask_Write(DDRC_ADDRMAP4_OFFSET, 0x00000F0FU, 0x00000F0FU); +/*##################################################################### */ + + /* + * Register : ADDRMAP5 @ 0XFD070214 + + * Selects the HIF address bit used as row address bit 11. Valid Range: 0 t + * o 11, and 15 Internal Base: 17 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * row address bit 11 is set to 0. + * PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B11 0x8 + + * Selects the HIF address bits used as row address bits 2 to 10. Valid Ran + * ge: 0 to 11, and 15 Internal Base: 8 (for row address bit 2), 9 (for row + * address bit 3), 10 (for row address bit 4) etc increasing to 16 (for ro + * w address bit 10) The selected HIF address bit for each of the row addre + * ss bits is determined by adding the internal base to the value of this f + * ield. When value 15 is used the values of row address bits 2 to 10 are d + * efined by registers ADDRMAP9, ADDRMAP10, ADDRMAP11. + * PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10 0xf + + * Selects the HIF address bits used as row address bit 1. Valid Range: 0 t + * o 11 Internal Base: 7 The selected HIF address bit for each of the row a + * ddress bits is determined by adding the internal base to the value of th + * is field. + * PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B1 0x8 + + * Selects the HIF address bits used as row address bit 0. Valid Range: 0 t + * o 11 Internal Base: 6 The selected HIF address bit for each of the row a + * ddress bits is determined by adding the internal base to the value of th + * is field. + * PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B0 0x8 + + * Address Map Register 5 + * (OFFSET, MASK, VALUE) (0XFD070214, 0x0F0F0F0FU ,0x080F0808U) + */ + PSU_Mask_Write(DDRC_ADDRMAP5_OFFSET, 0x0F0F0F0FU, 0x080F0808U); +/*##################################################################### */ + + /* + * Register : ADDRMAP6 @ 0XFD070218 + + * Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use. - 1 + * - LPDDR3 SDRAM 6Gb/12Gb device in use. Every address having row[14:13]= + * =2'b11 is considered as invalid - 0 - non-LPDDR3 6Gb/12Gb device in use. + * All addresses are valid Present only in designs configured to support L + * PDDR3. + * PSU_DDRC_ADDRMAP6_LPDDR3_6GB_12GB 0x0 + + * Selects the HIF address bit used as row address bit 15. Valid Range: 0 t + * o 11, and 15 Internal Base: 21 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * row address bit 15 is set to 0. + * PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B15 0xf + + * Selects the HIF address bit used as row address bit 14. Valid Range: 0 t + * o 11, and 15 Internal Base: 20 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * row address bit 14 is set to 0. + * PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B14 0x8 + + * Selects the HIF address bit used as row address bit 13. Valid Range: 0 t + * o 11, and 15 Internal Base: 19 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * row address bit 13 is set to 0. + * PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B13 0x8 + + * Selects the HIF address bit used as row address bit 12. Valid Range: 0 t + * o 11, and 15 Internal Base: 18 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * row address bit 12 is set to 0. + * PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B12 0x8 + + * Address Map Register 6 + * (OFFSET, MASK, VALUE) (0XFD070218, 0x8F0F0F0FU ,0x0F080808U) + */ + PSU_Mask_Write(DDRC_ADDRMAP6_OFFSET, 0x8F0F0F0FU, 0x0F080808U); +/*##################################################################### */ + + /* + * Register : ADDRMAP7 @ 0XFD07021C + + * Selects the HIF address bit used as row address bit 17. Valid Range: 0 t + * o 10, and 15 Internal Base: 23 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * row address bit 17 is set to 0. + * PSU_DDRC_ADDRMAP7_ADDRMAP_ROW_B17 0xf + + * Selects the HIF address bit used as row address bit 16. Valid Range: 0 t + * o 11, and 15 Internal Base: 22 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * row address bit 16 is set to 0. + * PSU_DDRC_ADDRMAP7_ADDRMAP_ROW_B16 0xf + + * Address Map Register 7 + * (OFFSET, MASK, VALUE) (0XFD07021C, 0x00000F0FU ,0x00000F0FU) + */ + PSU_Mask_Write(DDRC_ADDRMAP7_OFFSET, 0x00000F0FU, 0x00000F0FU); +/*##################################################################### */ + + /* + * Register : ADDRMAP8 @ 0XFD070220 + + * Selects the HIF address bits used as bank group address bit 1. Valid Ran + * ge: 0 to 30, and 31 Internal Base: 3 The selected HIF address bit for ea + * ch of the bank group address bits is determined by adding the internal b + * ase to the value of this field. If set to 31, bank group address bit 1 i + * s set to 0. + * PSU_DDRC_ADDRMAP8_ADDRMAP_BG_B1 0x8 + + * Selects the HIF address bits used as bank group address bit 0. Valid Ran + * ge: 0 to 30 Internal Base: 2 The selected HIF address bit for each of th + * e bank group address bits is determined by adding the internal base to t + * he value of this field. + * PSU_DDRC_ADDRMAP8_ADDRMAP_BG_B0 0x8 + + * Address Map Register 8 + * (OFFSET, MASK, VALUE) (0XFD070220, 0x00001F1FU ,0x00000808U) + */ + PSU_Mask_Write(DDRC_ADDRMAP8_OFFSET, 0x00001F1FU, 0x00000808U); +/*##################################################################### */ + + /* + * Register : ADDRMAP9 @ 0XFD070224 + + * Selects the HIF address bits used as row address bit 5. Valid Range: 0 t + * o 11 Internal Base: 11 The selected HIF address bit for each of the row + * address bits is determined by adding the internal base to the value of t + * his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + * _10 is set to value 15. + * PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B5 0x8 + + * Selects the HIF address bits used as row address bit 4. Valid Range: 0 t + * o 11 Internal Base: 10 The selected HIF address bit for each of the row + * address bits is determined by adding the internal base to the value of t + * his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + * _10 is set to value 15. + * PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B4 0x8 + + * Selects the HIF address bits used as row address bit 3. Valid Range: 0 t + * o 11 Internal Base: 9 The selected HIF address bit for each of the row a + * ddress bits is determined by adding the internal base to the value of th + * is field. This register field is used only when ADDRMAP5.addrmap_row_b2_ + * 10 is set to value 15. + * PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B3 0x8 + + * Selects the HIF address bits used as row address bit 2. Valid Range: 0 t + * o 11 Internal Base: 8 The selected HIF address bit for each of the row a + * ddress bits is determined by adding the internal base to the value of th + * is field. This register field is used only when ADDRMAP5.addrmap_row_b2_ + * 10 is set to value 15. + * PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B2 0x8 + + * Address Map Register 9 + * (OFFSET, MASK, VALUE) (0XFD070224, 0x0F0F0F0FU ,0x08080808U) + */ + PSU_Mask_Write(DDRC_ADDRMAP9_OFFSET, 0x0F0F0F0FU, 0x08080808U); +/*##################################################################### */ + + /* + * Register : ADDRMAP10 @ 0XFD070228 + + * Selects the HIF address bits used as row address bit 9. Valid Range: 0 t + * o 11 Internal Base: 15 The selected HIF address bit for each of the row + * address bits is determined by adding the internal base to the value of t + * his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + * _10 is set to value 15. + * PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B9 0x8 + + * Selects the HIF address bits used as row address bit 8. Valid Range: 0 t + * o 11 Internal Base: 14 The selected HIF address bit for each of the row + * address bits is determined by adding the internal base to the value of t + * his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + * _10 is set to value 15. + * PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B8 0x8 + + * Selects the HIF address bits used as row address bit 7. Valid Range: 0 t + * o 11 Internal Base: 13 The selected HIF address bit for each of the row + * address bits is determined by adding the internal base to the value of t + * his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + * _10 is set to value 15. + * PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B7 0x8 + + * Selects the HIF address bits used as row address bit 6. Valid Range: 0 t + * o 11 Internal Base: 12 The selected HIF address bit for each of the row + * address bits is determined by adding the internal base to the value of t + * his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + * _10 is set to value 15. + * PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B6 0x8 + + * Address Map Register 10 + * (OFFSET, MASK, VALUE) (0XFD070228, 0x0F0F0F0FU ,0x08080808U) + */ + PSU_Mask_Write(DDRC_ADDRMAP10_OFFSET, 0x0F0F0F0FU, 0x08080808U); +/*##################################################################### */ + + /* + * Register : ADDRMAP11 @ 0XFD07022C + + * Selects the HIF address bits used as row address bit 10. Valid Range: 0 + * to 11 Internal Base: 16 The selected HIF address bit for each of the row + * address bits is determined by adding the internal base to the value of + * this field. This register field is used only when ADDRMAP5.addrmap_row_b + * 2_10 is set to value 15. + * PSU_DDRC_ADDRMAP11_ADDRMAP_ROW_B10 0x8 + + * Address Map Register 11 + * (OFFSET, MASK, VALUE) (0XFD07022C, 0x0000000FU ,0x00000008U) + */ + PSU_Mask_Write(DDRC_ADDRMAP11_OFFSET, 0x0000000FU, 0x00000008U); +/*##################################################################### */ + + /* + * Register : ODTCFG @ 0XFD070240 + + * Cycles to hold ODT for a write command. The minimum supported value is 2 + * . Recommended values: DDR2: - BL8: 0x5 (DDR2-400/533/667), 0x6 (DDR2-800 + * ), 0x7 (DDR2-1066) - BL4: 0x3 (DDR2-400/533/667), 0x4 (DDR2-800), 0x5 (D + * DR2-1066) DDR3: - BL8: 0x6 DDR4: - BL8: 5 + WR_PREAMBLE + CRC_MODE WR_PR + * EAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) CRC_MODE = 0 ( + * not CRC mode), 1 (CRC mode) LPDDR3: - BL8: 7 + RU(tODTon(max)/tCK) + * PSU_DDRC_ODTCFG_WR_ODT_HOLD 0x6 + + * The delay, in clock cycles, from issuing a write command to setting ODT + * values associated with that command. ODT setting must remain constant fo + * r the entire time that DQS is driven by the uMCTL2. Recommended values: + * DDR2: - CWL + AL - 3 (DDR2-400/533/667), CWL + AL - 4 (DDR2-800), CWL + + * AL - 5 (DDR2-1066) If (CWL + AL - 3 < 0), uMCTL2 does not support ODT fo + * r write operation. DDR3: - 0x0 DDR4: - DFITMG1.dfi_t_cmd_lat (to adjust + * for CAL mode) LPDDR3: - WL - 1 - RU(tODTon(max)/tCK)) + * PSU_DDRC_ODTCFG_WR_ODT_DELAY 0x0 + + * Cycles to hold ODT for a read command. The minimum supported value is 2. + * Recommended values: DDR2: - BL8: 0x6 (not DDR2-1066), 0x7 (DDR2-1066) - + * BL4: 0x4 (not DDR2-1066), 0x5 (DDR2-1066) DDR3: - BL8 - 0x6 DDR4: - BL8 + * : 5 + RD_PREAMBLE RD_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write p + * reamble) LPDDR3: - BL8: 5 + RU(tDQSCK(max)/tCK) - RD(tDQSCK(min)/tCK) + + * RU(tODTon(max)/tCK) + * PSU_DDRC_ODTCFG_RD_ODT_HOLD 0x6 + + * The delay, in clock cycles, from issuing a read command to setting ODT v + * alues associated with that command. ODT setting must remain constant for + * the entire time that DQS is driven by the uMCTL2. Recommended values: D + * DR2: - CL + AL - 4 (not DDR2-1066), CL + AL - 5 (DDR2-1066) If (CL + AL + * - 4 < 0), uMCTL2 does not support ODT for read operation. DDR3: - CL - C + * WL DDR4: - CL - CWL - RD_PREAMBLE + WR_PREAMBLE + DFITMG1.dfi_t_cmd_lat + * (to adjust for CAL mode) WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK + * write preamble) RD_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write pre + * amble) If (CL - CWL - RD_PREAMBLE + WR_PREAMBLE) < 0, uMCTL2 does not su + * pport ODT for read operation. LPDDR3: - RL + RD(tDQSCK(min)/tCK) - 1 - R + * U(tODTon(max)/tCK) + * PSU_DDRC_ODTCFG_RD_ODT_DELAY 0x0 + + * ODT Configuration Register + * (OFFSET, MASK, VALUE) (0XFD070240, 0x0F1F0F7CU ,0x06000600U) + */ + PSU_Mask_Write(DDRC_ODTCFG_OFFSET, 0x0F1F0F7CU, 0x06000600U); +/*##################################################################### */ + + /* + * Register : ODTMAP @ 0XFD070244 + + * Indicates which remote ODTs must be turned on during a read from rank 1. + * Each rank has a remote ODT (in the SDRAM) which can be turned on by set + * ting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 i + * s controlled by bit next to the LSB, etc. For each rank, set its bit to + * 1 to enable its ODT. Present only in configurations that have 2 or more + * ranks + * PSU_DDRC_ODTMAP_RANK1_RD_ODT 0x0 + + * Indicates which remote ODTs must be turned on during a write to rank 1. + * Each rank has a remote ODT (in the SDRAM) which can be turned on by sett + * ing the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is + * controlled by bit next to the LSB, etc. For each rank, set its bit to 1 + * to enable its ODT. Present only in configurations that have 2 or more r + * anks + * PSU_DDRC_ODTMAP_RANK1_WR_ODT 0x0 + + * Indicates which remote ODTs must be turned on during a read from rank 0. + * Each rank has a remote ODT (in the SDRAM) which can be turned on by set + * ting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 i + * s controlled by bit next to the LSB, etc. For each rank, set its bit to + * 1 to enable its ODT. + * PSU_DDRC_ODTMAP_RANK0_RD_ODT 0x0 + + * Indicates which remote ODTs must be turned on during a write to rank 0. + * Each rank has a remote ODT (in the SDRAM) which can be turned on by sett + * ing the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is + * controlled by bit next to the LSB, etc. For each rank, set its bit to 1 + * to enable its ODT. + * PSU_DDRC_ODTMAP_RANK0_WR_ODT 0x1 + + * ODT/Rank Map Register + * (OFFSET, MASK, VALUE) (0XFD070244, 0x00003333U ,0x00000001U) + */ + PSU_Mask_Write(DDRC_ODTMAP_OFFSET, 0x00003333U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : SCHED @ 0XFD070250 + + * When the preferred transaction store is empty for these many clock cycle + * s, switch to the alternate transaction store if it is non-empty. The rea + * d transaction store (both high and low priority) is the default preferre + * d transaction store and the write transaction store is the alternative s + * tore. When prefer write over read is set this is reversed. 0x0 is a lega + * l value for this register. When set to 0x0, the transaction store switch + * ing will happen immediately when the switching conditions become true. F + * OR PERFORMANCE ONLY + * PSU_DDRC_SCHED_RDWR_IDLE_GAP 0x1 + + * UNUSED + * PSU_DDRC_SCHED_GO2CRITICAL_HYSTERESIS 0x0 + + * Number of entries in the low priority transaction store is this value + + * 1. (MEMC_NO_OF_ENTRY - (SCHED.lpr_num_entries + 1)) is the number of ent + * ries available for the high priority transaction store. Setting this to + * maximum value allocates all entries to low priority transaction store. S + * etting this to 0 allocates 1 entry to low priority transaction store and + * the rest to high priority transaction store. Note: In ECC configuration + * s, the numbers of write and low priority read credits issued is one less + * than in the non-ECC case. One entry each is reserved in the write and l + * ow-priority read CAMs for storing the RMW requests arising out of single + * bit error correction RMW operation. + * PSU_DDRC_SCHED_LPR_NUM_ENTRIES 0x20 + + * If true, bank is kept open only while there are page hit transactions av + * ailable in the CAM to that bank. The last read or write command in the C + * AM with a bank and page hit will be executed with auto-precharge if SCHE + * D1.pageclose_timer=0. Even if this register set to 1 and SCHED1.pageclos + * e_timer is set to 0, explicit precharge (and not auto-precharge) may be + * issued in some cases where there is a mode switch between Write and Read + * or between LPR and HPR. The Read and Write commands that are executed a + * s part of the ECC scrub requests are also executed without auto-precharg + * e. If false, the bank remains open until there is a need to close it (to + * open a different page, or for page timeout or refresh timeout) - also k + * nown as open page policy. The open page policy can be overridden by sett + * ing the per-command-autopre bit on the HIF interface (hif_cmd_autopre). + * The pageclose feature provids a midway between Open and Close page polic + * ies. FOR PERFORMANCE ONLY. + * PSU_DDRC_SCHED_PAGECLOSE 0x0 + + * If set then the bank selector prefers writes over reads. FOR DEBUG ONLY. + * PSU_DDRC_SCHED_PREFER_WRITE 0x0 + + * Active low signal. When asserted ('0'), all incoming transactions are fo + * rced to low priority. This implies that all High Priority Read (HPR) and + * Variable Priority Read commands (VPR) will be treated as Low Priority R + * ead (LPR) commands. On the write side, all Variable Priority Write (VPW) + * commands will be treated as Normal Priority Write (NPW) commands. Forci + * ng the incoming transactions to low priority implicitly turns off Bypass + * path for read commands. FOR PERFORMANCE ONLY. + * PSU_DDRC_SCHED_FORCE_LOW_PRI_N 0x1 + + * Scheduler Control Register + * (OFFSET, MASK, VALUE) (0XFD070250, 0x7FFF3F07U ,0x01002001U) + */ + PSU_Mask_Write(DDRC_SCHED_OFFSET, 0x7FFF3F07U, 0x01002001U); +/*##################################################################### */ + + /* + * Register : PERFLPR1 @ 0XFD070264 + + * Number of transactions that are serviced once the LPR queue goes critica + * l is the smaller of: - (a) This number - (b) Number of transactions avai + * lable. Unit: Transaction. FOR PERFORMANCE ONLY. + * PSU_DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH 0x8 + + * Number of clocks that the LPR queue can be starved before it goes critic + * al. The minimum valid functional value for this register is 0x1. Program + * ming it to 0x0 will disable the starvation functionality; during normal + * operation, this function should not be disabled as it will cause excessi + * ve latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY. + * PSU_DDRC_PERFLPR1_LPR_MAX_STARVE 0x40 + + * Low Priority Read CAM Register 1 + * (OFFSET, MASK, VALUE) (0XFD070264, 0xFF00FFFFU ,0x08000040U) + */ + PSU_Mask_Write(DDRC_PERFLPR1_OFFSET, 0xFF00FFFFU, 0x08000040U); +/*##################################################################### */ + + /* + * Register : PERFWR1 @ 0XFD07026C + + * Number of transactions that are serviced once the WR queue goes critical + * is the smaller of: - (a) This number - (b) Number of transactions avail + * able. Unit: Transaction. FOR PERFORMANCE ONLY. + * PSU_DDRC_PERFWR1_W_XACT_RUN_LENGTH 0x8 + + * Number of clocks that the WR queue can be starved before it goes critica + * l. The minimum valid functional value for this register is 0x1. Programm + * ing it to 0x0 will disable the starvation functionality; during normal o + * peration, this function should not be disabled as it will cause excessiv + * e latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY. + * PSU_DDRC_PERFWR1_W_MAX_STARVE 0x40 + + * Write CAM Register 1 + * (OFFSET, MASK, VALUE) (0XFD07026C, 0xFF00FFFFU ,0x08000040U) + */ + PSU_Mask_Write(DDRC_PERFWR1_OFFSET, 0xFF00FFFFU, 0x08000040U); +/*##################################################################### */ + + /* + * Register : DQMAP0 @ 0XFD070280 + + * DQ nibble map for DQ bits [12-15] Present only in designs configured to + * support DDR4. + * PSU_DDRC_DQMAP0_DQ_NIBBLE_MAP_12_15 0x0 + + * DQ nibble map for DQ bits [8-11] Present only in designs configured to s + * upport DDR4. + * PSU_DDRC_DQMAP0_DQ_NIBBLE_MAP_8_11 0x0 + + * DQ nibble map for DQ bits [4-7] Present only in designs configured to su + * pport DDR4. + * PSU_DDRC_DQMAP0_DQ_NIBBLE_MAP_4_7 0x0 + + * DQ nibble map for DQ bits [0-3] Present only in designs configured to su + * pport DDR4. + * PSU_DDRC_DQMAP0_DQ_NIBBLE_MAP_0_3 0x0 + + * DQ Map Register 0 + * (OFFSET, MASK, VALUE) (0XFD070280, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDRC_DQMAP0_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : DQMAP1 @ 0XFD070284 + + * DQ nibble map for DQ bits [28-31] Present only in designs configured to + * support DDR4. + * PSU_DDRC_DQMAP1_DQ_NIBBLE_MAP_28_31 0x0 + + * DQ nibble map for DQ bits [24-27] Present only in designs configured to + * support DDR4. + * PSU_DDRC_DQMAP1_DQ_NIBBLE_MAP_24_27 0x0 + + * DQ nibble map for DQ bits [20-23] Present only in designs configured to + * support DDR4. + * PSU_DDRC_DQMAP1_DQ_NIBBLE_MAP_20_23 0x0 + + * DQ nibble map for DQ bits [16-19] Present only in designs configured to + * support DDR4. + * PSU_DDRC_DQMAP1_DQ_NIBBLE_MAP_16_19 0x0 + + * DQ Map Register 1 + * (OFFSET, MASK, VALUE) (0XFD070284, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDRC_DQMAP1_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : DQMAP2 @ 0XFD070288 + + * DQ nibble map for DQ bits [44-47] Present only in designs configured to + * support DDR4. + * PSU_DDRC_DQMAP2_DQ_NIBBLE_MAP_44_47 0x0 + + * DQ nibble map for DQ bits [40-43] Present only in designs configured to + * support DDR4. + * PSU_DDRC_DQMAP2_DQ_NIBBLE_MAP_40_43 0x0 + + * DQ nibble map for DQ bits [36-39] Present only in designs configured to + * support DDR4. + * PSU_DDRC_DQMAP2_DQ_NIBBLE_MAP_36_39 0x0 + + * DQ nibble map for DQ bits [32-35] Present only in designs configured to + * support DDR4. + * PSU_DDRC_DQMAP2_DQ_NIBBLE_MAP_32_35 0x0 + + * DQ Map Register 2 + * (OFFSET, MASK, VALUE) (0XFD070288, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDRC_DQMAP2_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : DQMAP3 @ 0XFD07028C + + * DQ nibble map for DQ bits [60-63] Present only in designs configured to + * support DDR4. + * PSU_DDRC_DQMAP3_DQ_NIBBLE_MAP_60_63 0x0 + + * DQ nibble map for DQ bits [56-59] Present only in designs configured to + * support DDR4. + * PSU_DDRC_DQMAP3_DQ_NIBBLE_MAP_56_59 0x0 + + * DQ nibble map for DQ bits [52-55] Present only in designs configured to + * support DDR4. + * PSU_DDRC_DQMAP3_DQ_NIBBLE_MAP_52_55 0x0 + + * DQ nibble map for DQ bits [48-51] Present only in designs configured to + * support DDR4. + * PSU_DDRC_DQMAP3_DQ_NIBBLE_MAP_48_51 0x0 + + * DQ Map Register 3 + * (OFFSET, MASK, VALUE) (0XFD07028C, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDRC_DQMAP3_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : DQMAP4 @ 0XFD070290 + + * DQ nibble map for DIMM ECC check bits [4-7] Present only in designs conf + * igured to support DDR4. + * PSU_DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_4_7 0x0 + + * DQ nibble map for DIMM ECC check bits [0-3] Present only in designs conf + * igured to support DDR4. + * PSU_DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_0_3 0x0 + + * DQ Map Register 4 + * (OFFSET, MASK, VALUE) (0XFD070290, 0x0000FFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDRC_DQMAP4_OFFSET, 0x0000FFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : DQMAP5 @ 0XFD070294 + + * All even ranks have the same DQ mapping controled by DQMAP0-4 register a + * s rank 0. This register provides DQ swap function for all odd ranks to s + * upport CRC feature. rank based DQ swapping is: swap bit 0 with 1, swap b + * it 2 with 3, swap bit 4 with 5 and swap bit 6 with 7. 1: Disable rank ba + * sed DQ swapping 0: Enable rank based DQ swapping Present only in designs + * configured to support DDR4. + * PSU_DDRC_DQMAP5_DIS_DQ_RANK_SWAP 0x1 + + * DQ Map Register 5 + * (OFFSET, MASK, VALUE) (0XFD070294, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(DDRC_DQMAP5_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : DBG0 @ 0XFD070300 + + * When this is set to '0', auto-precharge is disabled for the flushed comm + * and in a collision case. Collision cases are write followed by read to s + * ame address, read followed by write to same address, or write followed b + * y write to same address with DBG0.dis_wc bit = 1 (where same address com + * parisons exclude the two address bits representing critical word). FOR D + * EBUG ONLY. + * PSU_DDRC_DBG0_DIS_COLLISION_PAGE_OPT 0x0 + + * When 1, disable write combine. FOR DEBUG ONLY + * PSU_DDRC_DBG0_DIS_WC 0x0 + + * Debug Register 0 + * (OFFSET, MASK, VALUE) (0XFD070300, 0x00000011U ,0x00000000U) + */ + PSU_Mask_Write(DDRC_DBG0_OFFSET, 0x00000011U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : DBGCMD @ 0XFD07030C + + * Setting this register bit to 1 allows refresh and ZQCS commands to be tr + * iggered from hardware via the IOs ext_*. If set to 1, the fields DBGCMD. + * zq_calib_short and DBGCMD.rank*_refresh have no function, and are ignore + * d by the uMCTL2 logic. Setting this register bit to 0 allows refresh and + * ZQCS to be triggered from software, via the fields DBGCMD.zq_calib_shor + * t and DBGCMD.rank*_refresh. If set to 0, the hardware pins ext_* have no + * function, and are ignored by the uMCTL2 logic. This register is static, + * and may only be changed when the DDRC reset signal, core_ddrc_rstn, is + * asserted (0). + * PSU_DDRC_DBGCMD_HW_REF_ZQ_EN 0x0 + + * Setting this register bit to 1 indicates to the uMCTL2 to issue a dfi_ct + * rlupd_req to the PHY. When this request is stored in the uMCTL2, the bit + * is automatically cleared. This operation must only be performed when DF + * IUPD0.dis_auto_ctrlupd=1. + * PSU_DDRC_DBGCMD_CTRLUPD 0x0 + + * Setting this register bit to 1 indicates to the uMCTL2 to issue a ZQCS ( + * ZQ calibration short)/MPC(ZQ calibration) command to the SDRAM. When thi + * s request is stored in the uMCTL2, the bit is automatically cleared. Thi + * s operation can be performed only when ZQCTL0.dis_auto_zq=1. It is recom + * mended NOT to set this register bit if in Init operating mode. This regi + * ster bit is ignored when in Self-Refresh(except LPDDR4) and SR-Powerdown + * (LPDDR4) and Deep power-down operating modes and Maximum Power Saving Mo + * de. + * PSU_DDRC_DBGCMD_ZQ_CALIB_SHORT 0x0 + + * Setting this register bit to 1 indicates to the uMCTL2 to issue a refres + * h to rank 1. Writing to this bit causes DBGSTAT.rank1_refresh_busy to be + * set. When DBGSTAT.rank1_refresh_busy is cleared, the command has been s + * tored in uMCTL2. This operation can be performed only when RFSHCTL3.dis_ + * auto_refresh=1. It is recommended NOT to set this register bit if in Ini + * t or Deep power-down operating modes or Maximum Power Saving Mode. + * PSU_DDRC_DBGCMD_RANK1_REFRESH 0x0 + + * Setting this register bit to 1 indicates to the uMCTL2 to issue a refres + * h to rank 0. Writing to this bit causes DBGSTAT.rank0_refresh_busy to be + * set. When DBGSTAT.rank0_refresh_busy is cleared, the command has been s + * tored in uMCTL2. This operation can be performed only when RFSHCTL3.dis_ + * auto_refresh=1. It is recommended NOT to set this register bit if in Ini + * t or Deep power-down operating modes or Maximum Power Saving Mode. + * PSU_DDRC_DBGCMD_RANK0_REFRESH 0x0 + + * Command Debug Register + * (OFFSET, MASK, VALUE) (0XFD07030C, 0x80000033U ,0x00000000U) + */ + PSU_Mask_Write(DDRC_DBGCMD_OFFSET, 0x80000033U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : SWCTL @ 0XFD070320 + + * Enable quasi-dynamic register programming outside reset. Program registe + * r to 0 to enable quasi-dynamic programming. Set back register to 1 once + * programming is done. + * PSU_DDRC_SWCTL_SW_DONE 0x0 + + * Software register programming control enable + * (OFFSET, MASK, VALUE) (0XFD070320, 0x00000001U ,0x00000000U) + */ + PSU_Mask_Write(DDRC_SWCTL_OFFSET, 0x00000001U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : PCCFG @ 0XFD070400 + + * Burst length expansion mode. By default (i.e. bl_exp_mode==0) XPI expand + * s every AXI burst into multiple HIF commands, using the memory burst len + * gth as a unit. If set to 1, then XPI will use half of the memory burst l + * ength as a unit. This applies to both reads and writes. When MSTR.data_b + * us_width==00, setting bl_exp_mode to 1 has no effect. This can be used i + * n cases where Partial Writes is enabled (UMCTL2_PARTIAL_WR=1) and DBG0.d + * is_wc=1, in order to avoid or minimize t_ccd_l penalty in DDR4 and t_ccd + * _mw penalty in LPDDR4. Note that if DBICTL.reg_ddrc_dm_en=0, functionali + * ty is not supported in the following cases: - UMCTL2_PARTIAL_WR=0 - UMCT + * L2_PARTIAL_WR=1, MSTR.reg_ddrc_data_bus_width=01, MEMC_BURST_LENGTH=8 an + * d MSTR.reg_ddrc_burst_rdwr=1000 (LPDDR4 only) - UMCTL2_PARTIAL_WR=1, MST + * R.reg_ddrc_data_bus_width=01, MEMC_BURST_LENGTH=4 and MSTR.reg_ddrc_burs + * t_rdwr=0100 (DDR4 only), with either MSTR.reg_ddrc_burstchop=0 or CRCPAR + * CTL1.reg_ddrc_crc_enable=1 Functionality is also not supported if Shared + * -AC is enabled + * PSU_DDRC_PCCFG_BL_EXP_MODE 0x0 + + * Page match four limit. If set to 1, limits the number of consecutive sam + * e page DDRC transactions that can be granted by the Port Arbiter to four + * when Page Match feature is enabled. If set to 0, there is no limit impo + * sed on number of consecutive same page DDRC transactions. + * PSU_DDRC_PCCFG_PAGEMATCH_LIMIT 0x0 + + * If set to 1 (enabled), sets co_gs_go2critical_wr and co_gs_go2critical_l + * pr/co_gs_go2critical_hpr signals going to DDRC based on urgent input (aw + * urgent, arurgent) coming from AXI master. If set to 0 (disabled), co_gs_ + * go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals a + * t DDRC are driven to 1b'0. + * PSU_DDRC_PCCFG_GO2CRITICAL_EN 0x1 + + * Port Common Configuration Register + * (OFFSET, MASK, VALUE) (0XFD070400, 0x00000111U ,0x00000001U) + */ + PSU_Mask_Write(DDRC_PCCFG_OFFSET, 0x00000111U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : PCFGR_0 @ 0XFD070404 + + * If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. + * PSU_DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN 0x0 + + * If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + * bled and arurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + * urgent signal can be asserted anytime and as long as required which is i + * ndependent of address handshaking (it is not associated with any particu + * lar command). + * PSU_DDRC_PCFGR_0_RD_PORT_URGENT_EN 0x1 + + * If set to 1, enables aging function for the read channel of the port. + * PSU_DDRC_PCFGR_0_RD_PORT_AGING_EN 0x0 + + * Determines the initial load value of read aging counters. These counters + * will be parallel loaded after reset, or after each grant to the corresp + * onding port. The aging counters down-count every clock cycle where the p + * ort is requesting but not granted. The higher significant 5-bits of the + * read aging counter sets the priority of the read channel of a given port + * . Port's priority will increase as the higher significant 5-bits of the + * counter starts to decrease. When the aging counter becomes 0, the corres + * ponding port channel will have the highest priority level (timeout condi + * tion - Priority0). For multi-port configurations, the aging counters can + * not be used to set port priorities when external dynamic priority inputs + * (arqos) are enabled (timeout is still applicable). For single port conf + * igurations, the aging counters are only used when they timeout (become 0 + * ) to force read-write direction switching. In this case, external dynami + * c priority input, arqos (for reads only) can still be used to set the DD + * RC read priority (2 priority levels: low priority read - LPR, high prior + * ity read - HPR) on a command by command basis. Note: The two LSBs of thi + * s register field are tied internally to 2'b00. + * PSU_DDRC_PCFGR_0_RD_PORT_PRIORITY 0xf + + * Port n Configuration Read Register + * (OFFSET, MASK, VALUE) (0XFD070404, 0x000073FFU ,0x0000200FU) + */ + PSU_Mask_Write(DDRC_PCFGR_0_OFFSET, 0x000073FFU, 0x0000200FU); +/*##################################################################### */ + + /* + * Register : PCFGW_0 @ 0XFD070408 + + * If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. + * PSU_DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN 0x0 + + * If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + * bled and awurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + * serted anytime and as long as required which is independent of address h + * andshaking (it is not associated with any particular command). + * PSU_DDRC_PCFGW_0_WR_PORT_URGENT_EN 0x1 + + * If set to 1, enables aging function for the write channel of the port. + * PSU_DDRC_PCFGW_0_WR_PORT_AGING_EN 0x0 + + * Determines the initial load value of write aging counters. These counter + * s will be parallel loaded after reset, or after each grant to the corres + * ponding port. The aging counters down-count every clock cycle where the + * port is requesting but not granted. The higher significant 5-bits of the + * write aging counter sets the initial priority of the write channel of a + * given port. Port's priority will increase as the higher significant 5-b + * its of the counter starts to decrease. When the aging counter becomes 0, + * the corresponding port channel will have the highest priority level. Fo + * r multi-port configurations, the aging counters cannot be used to set po + * rt priorities when external dynamic priority inputs (awqos) are enabled + * (timeout is still applicable). For single port configurations, the aging + * counters are only used when they timeout (become 0) to force read-write + * direction switching. Note: The two LSBs of this register field are tied + * internally to 2'b00. + * PSU_DDRC_PCFGW_0_WR_PORT_PRIORITY 0xf + + * Port n Configuration Write Register + * (OFFSET, MASK, VALUE) (0XFD070408, 0x000073FFU ,0x0000200FU) + */ + PSU_Mask_Write(DDRC_PCFGW_0_OFFSET, 0x000073FFU, 0x0000200FU); +/*##################################################################### */ + + /* + * Register : PCTRL_0 @ 0XFD070490 + + * Enables port n. + * PSU_DDRC_PCTRL_0_PORT_EN 0x1 + + * Port n Control Register + * (OFFSET, MASK, VALUE) (0XFD070490, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(DDRC_PCTRL_0_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : PCFGQOS0_0 @ 0XFD070494 + + * This bitfield indicates the traffic class of region 1. Valid values are: + * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + * maps to the blue address queue. In this case, valid values are 0: LPR a + * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. + * PSU_DDRC_PCFGQOS0_0_RQOS_MAP_REGION1 0x2 + + * This bitfield indicates the traffic class of region 0. Valid values are: + * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + * maps to the blue address queue. In this case, valid values are: 0: LPR + * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. + * PSU_DDRC_PCFGQOS0_0_RQOS_MAP_REGION0 0x0 + + * Separation level1 indicating the end of region0 mapping; start of region + * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + * lues are used directly as port priorities, where the higher the value co + * rresponds to higher port priority. All of the map_level* registers must + * be set to distinct values. + * PSU_DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1 0xb + + * Port n Read QoS Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD070494, 0x0033000FU ,0x0020000BU) + */ + PSU_Mask_Write(DDRC_PCFGQOS0_0_OFFSET, 0x0033000FU, 0x0020000BU); +/*##################################################################### */ + + /* + * Register : PCFGQOS1_0 @ 0XFD070498 + + * Specifies the timeout value for transactions mapped to the red address q + * ueue. + * PSU_DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR 0x0 + + * Specifies the timeout value for transactions mapped to the blue address + * queue. + * PSU_DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB 0x0 + + * Port n Read QoS Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD070498, 0x07FF07FFU ,0x00000000U) + */ + PSU_Mask_Write(DDRC_PCFGQOS1_0_OFFSET, 0x07FF07FFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : PCFGR_1 @ 0XFD0704B4 + + * If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. + * PSU_DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN 0x0 + + * If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + * bled and arurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + * urgent signal can be asserted anytime and as long as required which is i + * ndependent of address handshaking (it is not associated with any particu + * lar command). + * PSU_DDRC_PCFGR_1_RD_PORT_URGENT_EN 0x1 + + * If set to 1, enables aging function for the read channel of the port. + * PSU_DDRC_PCFGR_1_RD_PORT_AGING_EN 0x0 + + * Determines the initial load value of read aging counters. These counters + * will be parallel loaded after reset, or after each grant to the corresp + * onding port. The aging counters down-count every clock cycle where the p + * ort is requesting but not granted. The higher significant 5-bits of the + * read aging counter sets the priority of the read channel of a given port + * . Port's priority will increase as the higher significant 5-bits of the + * counter starts to decrease. When the aging counter becomes 0, the corres + * ponding port channel will have the highest priority level (timeout condi + * tion - Priority0). For multi-port configurations, the aging counters can + * not be used to set port priorities when external dynamic priority inputs + * (arqos) are enabled (timeout is still applicable). For single port conf + * igurations, the aging counters are only used when they timeout (become 0 + * ) to force read-write direction switching. In this case, external dynami + * c priority input, arqos (for reads only) can still be used to set the DD + * RC read priority (2 priority levels: low priority read - LPR, high prior + * ity read - HPR) on a command by command basis. Note: The two LSBs of thi + * s register field are tied internally to 2'b00. + * PSU_DDRC_PCFGR_1_RD_PORT_PRIORITY 0xf + + * Port n Configuration Read Register + * (OFFSET, MASK, VALUE) (0XFD0704B4, 0x000073FFU ,0x0000200FU) + */ + PSU_Mask_Write(DDRC_PCFGR_1_OFFSET, 0x000073FFU, 0x0000200FU); +/*##################################################################### */ + + /* + * Register : PCFGW_1 @ 0XFD0704B8 + + * If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. + * PSU_DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN 0x0 + + * If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + * bled and awurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + * serted anytime and as long as required which is independent of address h + * andshaking (it is not associated with any particular command). + * PSU_DDRC_PCFGW_1_WR_PORT_URGENT_EN 0x1 + + * If set to 1, enables aging function for the write channel of the port. + * PSU_DDRC_PCFGW_1_WR_PORT_AGING_EN 0x0 + + * Determines the initial load value of write aging counters. These counter + * s will be parallel loaded after reset, or after each grant to the corres + * ponding port. The aging counters down-count every clock cycle where the + * port is requesting but not granted. The higher significant 5-bits of the + * write aging counter sets the initial priority of the write channel of a + * given port. Port's priority will increase as the higher significant 5-b + * its of the counter starts to decrease. When the aging counter becomes 0, + * the corresponding port channel will have the highest priority level. Fo + * r multi-port configurations, the aging counters cannot be used to set po + * rt priorities when external dynamic priority inputs (awqos) are enabled + * (timeout is still applicable). For single port configurations, the aging + * counters are only used when they timeout (become 0) to force read-write + * direction switching. Note: The two LSBs of this register field are tied + * internally to 2'b00. + * PSU_DDRC_PCFGW_1_WR_PORT_PRIORITY 0xf + + * Port n Configuration Write Register + * (OFFSET, MASK, VALUE) (0XFD0704B8, 0x000073FFU ,0x0000200FU) + */ + PSU_Mask_Write(DDRC_PCFGW_1_OFFSET, 0x000073FFU, 0x0000200FU); +/*##################################################################### */ + + /* + * Register : PCTRL_1 @ 0XFD070540 + + * Enables port n. + * PSU_DDRC_PCTRL_1_PORT_EN 0x1 + + * Port n Control Register + * (OFFSET, MASK, VALUE) (0XFD070540, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(DDRC_PCTRL_1_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : PCFGQOS0_1 @ 0XFD070544 + + * This bitfield indicates the traffic class of region2. For dual address q + * ueue configurations, region2 maps to the red address queue. Valid values + * are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN + * = 0) and traffic class of region2 is set to 1 (VPR), VPR traffic is ali + * ased to LPR traffic. + * PSU_DDRC_PCFGQOS0_1_RQOS_MAP_REGION2 0x2 + + * This bitfield indicates the traffic class of region 1. Valid values are: + * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + * maps to the blue address queue. In this case, valid values are 0: LPR a + * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. + * PSU_DDRC_PCFGQOS0_1_RQOS_MAP_REGION1 0x0 + + * This bitfield indicates the traffic class of region 0. Valid values are: + * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + * maps to the blue address queue. In this case, valid values are: 0: LPR + * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. + * PSU_DDRC_PCFGQOS0_1_RQOS_MAP_REGION0 0x0 + + * Separation level2 indicating the end of region1 mapping; start of region + * 1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 whi + * ch corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note + * that for PA, arqos values are used directly as port priorities, where t + * he higher the value corresponds to higher port priority. All of the map_ + * level* registers must be set to distinct values. + * PSU_DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2 0xb + + * Separation level1 indicating the end of region0 mapping; start of region + * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + * lues are used directly as port priorities, where the higher the value co + * rresponds to higher port priority. All of the map_level* registers must + * be set to distinct values. + * PSU_DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1 0x3 + + * Port n Read QoS Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD070544, 0x03330F0FU ,0x02000B03U) + */ + PSU_Mask_Write(DDRC_PCFGQOS0_1_OFFSET, 0x03330F0FU, 0x02000B03U); +/*##################################################################### */ + + /* + * Register : PCFGQOS1_1 @ 0XFD070548 + + * Specifies the timeout value for transactions mapped to the red address q + * ueue. + * PSU_DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR 0x0 + + * Specifies the timeout value for transactions mapped to the blue address + * queue. + * PSU_DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB 0x0 + + * Port n Read QoS Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD070548, 0x07FF07FFU ,0x00000000U) + */ + PSU_Mask_Write(DDRC_PCFGQOS1_1_OFFSET, 0x07FF07FFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : PCFGR_2 @ 0XFD070564 + + * If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. + * PSU_DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN 0x0 + + * If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + * bled and arurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + * urgent signal can be asserted anytime and as long as required which is i + * ndependent of address handshaking (it is not associated with any particu + * lar command). + * PSU_DDRC_PCFGR_2_RD_PORT_URGENT_EN 0x1 + + * If set to 1, enables aging function for the read channel of the port. + * PSU_DDRC_PCFGR_2_RD_PORT_AGING_EN 0x0 + + * Determines the initial load value of read aging counters. These counters + * will be parallel loaded after reset, or after each grant to the corresp + * onding port. The aging counters down-count every clock cycle where the p + * ort is requesting but not granted. The higher significant 5-bits of the + * read aging counter sets the priority of the read channel of a given port + * . Port's priority will increase as the higher significant 5-bits of the + * counter starts to decrease. When the aging counter becomes 0, the corres + * ponding port channel will have the highest priority level (timeout condi + * tion - Priority0). For multi-port configurations, the aging counters can + * not be used to set port priorities when external dynamic priority inputs + * (arqos) are enabled (timeout is still applicable). For single port conf + * igurations, the aging counters are only used when they timeout (become 0 + * ) to force read-write direction switching. In this case, external dynami + * c priority input, arqos (for reads only) can still be used to set the DD + * RC read priority (2 priority levels: low priority read - LPR, high prior + * ity read - HPR) on a command by command basis. Note: The two LSBs of thi + * s register field are tied internally to 2'b00. + * PSU_DDRC_PCFGR_2_RD_PORT_PRIORITY 0xf + + * Port n Configuration Read Register + * (OFFSET, MASK, VALUE) (0XFD070564, 0x000073FFU ,0x0000200FU) + */ + PSU_Mask_Write(DDRC_PCFGR_2_OFFSET, 0x000073FFU, 0x0000200FU); +/*##################################################################### */ + + /* + * Register : PCFGW_2 @ 0XFD070568 + + * If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. + * PSU_DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN 0x0 + + * If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + * bled and awurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + * serted anytime and as long as required which is independent of address h + * andshaking (it is not associated with any particular command). + * PSU_DDRC_PCFGW_2_WR_PORT_URGENT_EN 0x1 + + * If set to 1, enables aging function for the write channel of the port. + * PSU_DDRC_PCFGW_2_WR_PORT_AGING_EN 0x0 + + * Determines the initial load value of write aging counters. These counter + * s will be parallel loaded after reset, or after each grant to the corres + * ponding port. The aging counters down-count every clock cycle where the + * port is requesting but not granted. The higher significant 5-bits of the + * write aging counter sets the initial priority of the write channel of a + * given port. Port's priority will increase as the higher significant 5-b + * its of the counter starts to decrease. When the aging counter becomes 0, + * the corresponding port channel will have the highest priority level. Fo + * r multi-port configurations, the aging counters cannot be used to set po + * rt priorities when external dynamic priority inputs (awqos) are enabled + * (timeout is still applicable). For single port configurations, the aging + * counters are only used when they timeout (become 0) to force read-write + * direction switching. Note: The two LSBs of this register field are tied + * internally to 2'b00. + * PSU_DDRC_PCFGW_2_WR_PORT_PRIORITY 0xf + + * Port n Configuration Write Register + * (OFFSET, MASK, VALUE) (0XFD070568, 0x000073FFU ,0x0000200FU) + */ + PSU_Mask_Write(DDRC_PCFGW_2_OFFSET, 0x000073FFU, 0x0000200FU); +/*##################################################################### */ + + /* + * Register : PCTRL_2 @ 0XFD0705F0 + + * Enables port n. + * PSU_DDRC_PCTRL_2_PORT_EN 0x1 + + * Port n Control Register + * (OFFSET, MASK, VALUE) (0XFD0705F0, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(DDRC_PCTRL_2_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : PCFGQOS0_2 @ 0XFD0705F4 + + * This bitfield indicates the traffic class of region2. For dual address q + * ueue configurations, region2 maps to the red address queue. Valid values + * are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN + * = 0) and traffic class of region2 is set to 1 (VPR), VPR traffic is ali + * ased to LPR traffic. + * PSU_DDRC_PCFGQOS0_2_RQOS_MAP_REGION2 0x2 + + * This bitfield indicates the traffic class of region 1. Valid values are: + * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + * maps to the blue address queue. In this case, valid values are 0: LPR a + * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. + * PSU_DDRC_PCFGQOS0_2_RQOS_MAP_REGION1 0x0 + + * This bitfield indicates the traffic class of region 0. Valid values are: + * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + * maps to the blue address queue. In this case, valid values are: 0: LPR + * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. + * PSU_DDRC_PCFGQOS0_2_RQOS_MAP_REGION0 0x0 + + * Separation level2 indicating the end of region1 mapping; start of region + * 1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 whi + * ch corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note + * that for PA, arqos values are used directly as port priorities, where t + * he higher the value corresponds to higher port priority. All of the map_ + * level* registers must be set to distinct values. + * PSU_DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2 0xb + + * Separation level1 indicating the end of region0 mapping; start of region + * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + * lues are used directly as port priorities, where the higher the value co + * rresponds to higher port priority. All of the map_level* registers must + * be set to distinct values. + * PSU_DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1 0x3 + + * Port n Read QoS Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD0705F4, 0x03330F0FU ,0x02000B03U) + */ + PSU_Mask_Write(DDRC_PCFGQOS0_2_OFFSET, 0x03330F0FU, 0x02000B03U); +/*##################################################################### */ + + /* + * Register : PCFGQOS1_2 @ 0XFD0705F8 + + * Specifies the timeout value for transactions mapped to the red address q + * ueue. + * PSU_DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR 0x0 + + * Specifies the timeout value for transactions mapped to the blue address + * queue. + * PSU_DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB 0x0 + + * Port n Read QoS Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD0705F8, 0x07FF07FFU ,0x00000000U) + */ + PSU_Mask_Write(DDRC_PCFGQOS1_2_OFFSET, 0x07FF07FFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : PCFGR_3 @ 0XFD070614 + + * If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. + * PSU_DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN 0x0 + + * If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + * bled and arurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + * urgent signal can be asserted anytime and as long as required which is i + * ndependent of address handshaking (it is not associated with any particu + * lar command). + * PSU_DDRC_PCFGR_3_RD_PORT_URGENT_EN 0x1 + + * If set to 1, enables aging function for the read channel of the port. + * PSU_DDRC_PCFGR_3_RD_PORT_AGING_EN 0x0 + + * Determines the initial load value of read aging counters. These counters + * will be parallel loaded after reset, or after each grant to the corresp + * onding port. The aging counters down-count every clock cycle where the p + * ort is requesting but not granted. The higher significant 5-bits of the + * read aging counter sets the priority of the read channel of a given port + * . Port's priority will increase as the higher significant 5-bits of the + * counter starts to decrease. When the aging counter becomes 0, the corres + * ponding port channel will have the highest priority level (timeout condi + * tion - Priority0). For multi-port configurations, the aging counters can + * not be used to set port priorities when external dynamic priority inputs + * (arqos) are enabled (timeout is still applicable). For single port conf + * igurations, the aging counters are only used when they timeout (become 0 + * ) to force read-write direction switching. In this case, external dynami + * c priority input, arqos (for reads only) can still be used to set the DD + * RC read priority (2 priority levels: low priority read - LPR, high prior + * ity read - HPR) on a command by command basis. Note: The two LSBs of thi + * s register field are tied internally to 2'b00. + * PSU_DDRC_PCFGR_3_RD_PORT_PRIORITY 0xf + + * Port n Configuration Read Register + * (OFFSET, MASK, VALUE) (0XFD070614, 0x000073FFU ,0x0000200FU) + */ + PSU_Mask_Write(DDRC_PCFGR_3_OFFSET, 0x000073FFU, 0x0000200FU); +/*##################################################################### */ + + /* + * Register : PCFGW_3 @ 0XFD070618 + + * If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. + * PSU_DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN 0x0 + + * If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + * bled and awurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + * serted anytime and as long as required which is independent of address h + * andshaking (it is not associated with any particular command). + * PSU_DDRC_PCFGW_3_WR_PORT_URGENT_EN 0x1 + + * If set to 1, enables aging function for the write channel of the port. + * PSU_DDRC_PCFGW_3_WR_PORT_AGING_EN 0x0 + + * Determines the initial load value of write aging counters. These counter + * s will be parallel loaded after reset, or after each grant to the corres + * ponding port. The aging counters down-count every clock cycle where the + * port is requesting but not granted. The higher significant 5-bits of the + * write aging counter sets the initial priority of the write channel of a + * given port. Port's priority will increase as the higher significant 5-b + * its of the counter starts to decrease. When the aging counter becomes 0, + * the corresponding port channel will have the highest priority level. Fo + * r multi-port configurations, the aging counters cannot be used to set po + * rt priorities when external dynamic priority inputs (awqos) are enabled + * (timeout is still applicable). For single port configurations, the aging + * counters are only used when they timeout (become 0) to force read-write + * direction switching. Note: The two LSBs of this register field are tied + * internally to 2'b00. + * PSU_DDRC_PCFGW_3_WR_PORT_PRIORITY 0xf + + * Port n Configuration Write Register + * (OFFSET, MASK, VALUE) (0XFD070618, 0x000073FFU ,0x0000200FU) + */ + PSU_Mask_Write(DDRC_PCFGW_3_OFFSET, 0x000073FFU, 0x0000200FU); +/*##################################################################### */ + + /* + * Register : PCTRL_3 @ 0XFD0706A0 + + * Enables port n. + * PSU_DDRC_PCTRL_3_PORT_EN 0x1 + + * Port n Control Register + * (OFFSET, MASK, VALUE) (0XFD0706A0, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(DDRC_PCTRL_3_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : PCFGQOS0_3 @ 0XFD0706A4 + + * This bitfield indicates the traffic class of region 1. Valid values are: + * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + * maps to the blue address queue. In this case, valid values are 0: LPR a + * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. + * PSU_DDRC_PCFGQOS0_3_RQOS_MAP_REGION1 0x1 + + * This bitfield indicates the traffic class of region 0. Valid values are: + * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + * maps to the blue address queue. In this case, valid values are: 0: LPR + * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. + * PSU_DDRC_PCFGQOS0_3_RQOS_MAP_REGION0 0x0 + + * Separation level1 indicating the end of region0 mapping; start of region + * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + * lues are used directly as port priorities, where the higher the value co + * rresponds to higher port priority. All of the map_level* registers must + * be set to distinct values. + * PSU_DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1 0x3 + + * Port n Read QoS Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD0706A4, 0x0033000FU ,0x00100003U) + */ + PSU_Mask_Write(DDRC_PCFGQOS0_3_OFFSET, 0x0033000FU, 0x00100003U); +/*##################################################################### */ + + /* + * Register : PCFGQOS1_3 @ 0XFD0706A8 + + * Specifies the timeout value for transactions mapped to the red address q + * ueue. + * PSU_DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR 0x0 + + * Specifies the timeout value for transactions mapped to the blue address + * queue. + * PSU_DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB 0x4f + + * Port n Read QoS Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD0706A8, 0x07FF07FFU ,0x0000004FU) + */ + PSU_Mask_Write(DDRC_PCFGQOS1_3_OFFSET, 0x07FF07FFU, 0x0000004FU); +/*##################################################################### */ + + /* + * Register : PCFGWQOS0_3 @ 0XFD0706AC + + * This bitfield indicates the traffic class of region 1. Valid values are: + * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + * affic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW + * traffic. + * PSU_DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1 0x1 + + * This bitfield indicates the traffic class of region 0. Valid values are: + * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + * affic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW + * traffic. + * PSU_DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0 0x0 + + * Separation level indicating the end of region0 mapping; start of region0 + * is 0. Possible values for level1 are 0 to 14 which corresponds to awqos + * . Note that for PA, awqos values are used directly as port priorities, w + * here the higher the value corresponds to higher port priority. + * PSU_DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL 0x3 + + * Port n Write QoS Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD0706AC, 0x0033000FU ,0x00100003U) + */ + PSU_Mask_Write(DDRC_PCFGWQOS0_3_OFFSET, 0x0033000FU, 0x00100003U); +/*##################################################################### */ + + /* + * Register : PCFGWQOS1_3 @ 0XFD0706B0 + + * Specifies the timeout value for write transactions. + * PSU_DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT 0x4f + + * Port n Write QoS Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD0706B0, 0x000007FFU ,0x0000004FU) + */ + PSU_Mask_Write(DDRC_PCFGWQOS1_3_OFFSET, 0x000007FFU, 0x0000004FU); +/*##################################################################### */ + + /* + * Register : PCFGR_4 @ 0XFD0706C4 + + * If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. + * PSU_DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN 0x0 + + * If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + * bled and arurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + * urgent signal can be asserted anytime and as long as required which is i + * ndependent of address handshaking (it is not associated with any particu + * lar command). + * PSU_DDRC_PCFGR_4_RD_PORT_URGENT_EN 0x1 + + * If set to 1, enables aging function for the read channel of the port. + * PSU_DDRC_PCFGR_4_RD_PORT_AGING_EN 0x0 + + * Determines the initial load value of read aging counters. These counters + * will be parallel loaded after reset, or after each grant to the corresp + * onding port. The aging counters down-count every clock cycle where the p + * ort is requesting but not granted. The higher significant 5-bits of the + * read aging counter sets the priority of the read channel of a given port + * . Port's priority will increase as the higher significant 5-bits of the + * counter starts to decrease. When the aging counter becomes 0, the corres + * ponding port channel will have the highest priority level (timeout condi + * tion - Priority0). For multi-port configurations, the aging counters can + * not be used to set port priorities when external dynamic priority inputs + * (arqos) are enabled (timeout is still applicable). For single port conf + * igurations, the aging counters are only used when they timeout (become 0 + * ) to force read-write direction switching. In this case, external dynami + * c priority input, arqos (for reads only) can still be used to set the DD + * RC read priority (2 priority levels: low priority read - LPR, high prior + * ity read - HPR) on a command by command basis. Note: The two LSBs of thi + * s register field are tied internally to 2'b00. + * PSU_DDRC_PCFGR_4_RD_PORT_PRIORITY 0xf + + * Port n Configuration Read Register + * (OFFSET, MASK, VALUE) (0XFD0706C4, 0x000073FFU ,0x0000200FU) + */ + PSU_Mask_Write(DDRC_PCFGR_4_OFFSET, 0x000073FFU, 0x0000200FU); +/*##################################################################### */ + + /* + * Register : PCFGW_4 @ 0XFD0706C8 + + * If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. + * PSU_DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN 0x0 + + * If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + * bled and awurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + * serted anytime and as long as required which is independent of address h + * andshaking (it is not associated with any particular command). + * PSU_DDRC_PCFGW_4_WR_PORT_URGENT_EN 0x1 + + * If set to 1, enables aging function for the write channel of the port. + * PSU_DDRC_PCFGW_4_WR_PORT_AGING_EN 0x0 + + * Determines the initial load value of write aging counters. These counter + * s will be parallel loaded after reset, or after each grant to the corres + * ponding port. The aging counters down-count every clock cycle where the + * port is requesting but not granted. The higher significant 5-bits of the + * write aging counter sets the initial priority of the write channel of a + * given port. Port's priority will increase as the higher significant 5-b + * its of the counter starts to decrease. When the aging counter becomes 0, + * the corresponding port channel will have the highest priority level. Fo + * r multi-port configurations, the aging counters cannot be used to set po + * rt priorities when external dynamic priority inputs (awqos) are enabled + * (timeout is still applicable). For single port configurations, the aging + * counters are only used when they timeout (become 0) to force read-write + * direction switching. Note: The two LSBs of this register field are tied + * internally to 2'b00. + * PSU_DDRC_PCFGW_4_WR_PORT_PRIORITY 0xf + + * Port n Configuration Write Register + * (OFFSET, MASK, VALUE) (0XFD0706C8, 0x000073FFU ,0x0000200FU) + */ + PSU_Mask_Write(DDRC_PCFGW_4_OFFSET, 0x000073FFU, 0x0000200FU); +/*##################################################################### */ + + /* + * Register : PCTRL_4 @ 0XFD070750 + + * Enables port n. + * PSU_DDRC_PCTRL_4_PORT_EN 0x1 + + * Port n Control Register + * (OFFSET, MASK, VALUE) (0XFD070750, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(DDRC_PCTRL_4_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : PCFGQOS0_4 @ 0XFD070754 + + * This bitfield indicates the traffic class of region 1. Valid values are: + * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + * maps to the blue address queue. In this case, valid values are 0: LPR a + * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. + * PSU_DDRC_PCFGQOS0_4_RQOS_MAP_REGION1 0x1 + + * This bitfield indicates the traffic class of region 0. Valid values are: + * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + * maps to the blue address queue. In this case, valid values are: 0: LPR + * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. + * PSU_DDRC_PCFGQOS0_4_RQOS_MAP_REGION0 0x0 + + * Separation level1 indicating the end of region0 mapping; start of region + * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + * lues are used directly as port priorities, where the higher the value co + * rresponds to higher port priority. All of the map_level* registers must + * be set to distinct values. + * PSU_DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1 0x3 + + * Port n Read QoS Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD070754, 0x0033000FU ,0x00100003U) + */ + PSU_Mask_Write(DDRC_PCFGQOS0_4_OFFSET, 0x0033000FU, 0x00100003U); +/*##################################################################### */ + + /* + * Register : PCFGQOS1_4 @ 0XFD070758 + + * Specifies the timeout value for transactions mapped to the red address q + * ueue. + * PSU_DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR 0x0 + + * Specifies the timeout value for transactions mapped to the blue address + * queue. + * PSU_DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB 0x4f + + * Port n Read QoS Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD070758, 0x07FF07FFU ,0x0000004FU) + */ + PSU_Mask_Write(DDRC_PCFGQOS1_4_OFFSET, 0x07FF07FFU, 0x0000004FU); +/*##################################################################### */ + + /* + * Register : PCFGWQOS0_4 @ 0XFD07075C + + * This bitfield indicates the traffic class of region 1. Valid values are: + * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + * affic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW + * traffic. + * PSU_DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1 0x1 + + * This bitfield indicates the traffic class of region 0. Valid values are: + * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + * affic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW + * traffic. + * PSU_DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0 0x0 + + * Separation level indicating the end of region0 mapping; start of region0 + * is 0. Possible values for level1 are 0 to 14 which corresponds to awqos + * . Note that for PA, awqos values are used directly as port priorities, w + * here the higher the value corresponds to higher port priority. + * PSU_DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL 0x3 + + * Port n Write QoS Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD07075C, 0x0033000FU ,0x00100003U) + */ + PSU_Mask_Write(DDRC_PCFGWQOS0_4_OFFSET, 0x0033000FU, 0x00100003U); +/*##################################################################### */ + + /* + * Register : PCFGWQOS1_4 @ 0XFD070760 + + * Specifies the timeout value for write transactions. + * PSU_DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT 0x4f + + * Port n Write QoS Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD070760, 0x000007FFU ,0x0000004FU) + */ + PSU_Mask_Write(DDRC_PCFGWQOS1_4_OFFSET, 0x000007FFU, 0x0000004FU); +/*##################################################################### */ + + /* + * Register : PCFGR_5 @ 0XFD070774 + + * If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. + * PSU_DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN 0x0 + + * If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + * bled and arurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + * urgent signal can be asserted anytime and as long as required which is i + * ndependent of address handshaking (it is not associated with any particu + * lar command). + * PSU_DDRC_PCFGR_5_RD_PORT_URGENT_EN 0x1 + + * If set to 1, enables aging function for the read channel of the port. + * PSU_DDRC_PCFGR_5_RD_PORT_AGING_EN 0x0 + + * Determines the initial load value of read aging counters. These counters + * will be parallel loaded after reset, or after each grant to the corresp + * onding port. The aging counters down-count every clock cycle where the p + * ort is requesting but not granted. The higher significant 5-bits of the + * read aging counter sets the priority of the read channel of a given port + * . Port's priority will increase as the higher significant 5-bits of the + * counter starts to decrease. When the aging counter becomes 0, the corres + * ponding port channel will have the highest priority level (timeout condi + * tion - Priority0). For multi-port configurations, the aging counters can + * not be used to set port priorities when external dynamic priority inputs + * (arqos) are enabled (timeout is still applicable). For single port conf + * igurations, the aging counters are only used when they timeout (become 0 + * ) to force read-write direction switching. In this case, external dynami + * c priority input, arqos (for reads only) can still be used to set the DD + * RC read priority (2 priority levels: low priority read - LPR, high prior + * ity read - HPR) on a command by command basis. Note: The two LSBs of thi + * s register field are tied internally to 2'b00. + * PSU_DDRC_PCFGR_5_RD_PORT_PRIORITY 0xf + + * Port n Configuration Read Register + * (OFFSET, MASK, VALUE) (0XFD070774, 0x000073FFU ,0x0000200FU) + */ + PSU_Mask_Write(DDRC_PCFGR_5_OFFSET, 0x000073FFU, 0x0000200FU); +/*##################################################################### */ + + /* + * Register : PCFGW_5 @ 0XFD070778 + + * If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. + * PSU_DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN 0x0 + + * If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + * bled and awurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + * serted anytime and as long as required which is independent of address h + * andshaking (it is not associated with any particular command). + * PSU_DDRC_PCFGW_5_WR_PORT_URGENT_EN 0x1 + + * If set to 1, enables aging function for the write channel of the port. + * PSU_DDRC_PCFGW_5_WR_PORT_AGING_EN 0x0 + + * Determines the initial load value of write aging counters. These counter + * s will be parallel loaded after reset, or after each grant to the corres + * ponding port. The aging counters down-count every clock cycle where the + * port is requesting but not granted. The higher significant 5-bits of the + * write aging counter sets the initial priority of the write channel of a + * given port. Port's priority will increase as the higher significant 5-b + * its of the counter starts to decrease. When the aging counter becomes 0, + * the corresponding port channel will have the highest priority level. Fo + * r multi-port configurations, the aging counters cannot be used to set po + * rt priorities when external dynamic priority inputs (awqos) are enabled + * (timeout is still applicable). For single port configurations, the aging + * counters are only used when they timeout (become 0) to force read-write + * direction switching. Note: The two LSBs of this register field are tied + * internally to 2'b00. + * PSU_DDRC_PCFGW_5_WR_PORT_PRIORITY 0xf + + * Port n Configuration Write Register + * (OFFSET, MASK, VALUE) (0XFD070778, 0x000073FFU ,0x0000200FU) + */ + PSU_Mask_Write(DDRC_PCFGW_5_OFFSET, 0x000073FFU, 0x0000200FU); +/*##################################################################### */ + + /* + * Register : PCTRL_5 @ 0XFD070800 + + * Enables port n. + * PSU_DDRC_PCTRL_5_PORT_EN 0x1 + + * Port n Control Register + * (OFFSET, MASK, VALUE) (0XFD070800, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(DDRC_PCTRL_5_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : PCFGQOS0_5 @ 0XFD070804 + + * This bitfield indicates the traffic class of region 1. Valid values are: + * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + * maps to the blue address queue. In this case, valid values are 0: LPR a + * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. + * PSU_DDRC_PCFGQOS0_5_RQOS_MAP_REGION1 0x1 + + * This bitfield indicates the traffic class of region 0. Valid values are: + * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + * maps to the blue address queue. In this case, valid values are: 0: LPR + * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. + * PSU_DDRC_PCFGQOS0_5_RQOS_MAP_REGION0 0x0 + + * Separation level1 indicating the end of region0 mapping; start of region + * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + * lues are used directly as port priorities, where the higher the value co + * rresponds to higher port priority. All of the map_level* registers must + * be set to distinct values. + * PSU_DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1 0x3 + + * Port n Read QoS Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD070804, 0x0033000FU ,0x00100003U) + */ + PSU_Mask_Write(DDRC_PCFGQOS0_5_OFFSET, 0x0033000FU, 0x00100003U); +/*##################################################################### */ + + /* + * Register : PCFGQOS1_5 @ 0XFD070808 + + * Specifies the timeout value for transactions mapped to the red address q + * ueue. + * PSU_DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR 0x0 + + * Specifies the timeout value for transactions mapped to the blue address + * queue. + * PSU_DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB 0x4f + + * Port n Read QoS Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD070808, 0x07FF07FFU ,0x0000004FU) + */ + PSU_Mask_Write(DDRC_PCFGQOS1_5_OFFSET, 0x07FF07FFU, 0x0000004FU); +/*##################################################################### */ + + /* + * Register : PCFGWQOS0_5 @ 0XFD07080C + + * This bitfield indicates the traffic class of region 1. Valid values are: + * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + * affic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW + * traffic. + * PSU_DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1 0x1 + + * This bitfield indicates the traffic class of region 0. Valid values are: + * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + * affic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW + * traffic. + * PSU_DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0 0x0 + + * Separation level indicating the end of region0 mapping; start of region0 + * is 0. Possible values for level1 are 0 to 14 which corresponds to awqos + * . Note that for PA, awqos values are used directly as port priorities, w + * here the higher the value corresponds to higher port priority. + * PSU_DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL 0x3 + + * Port n Write QoS Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD07080C, 0x0033000FU ,0x00100003U) + */ + PSU_Mask_Write(DDRC_PCFGWQOS0_5_OFFSET, 0x0033000FU, 0x00100003U); +/*##################################################################### */ + + /* + * Register : PCFGWQOS1_5 @ 0XFD070810 + + * Specifies the timeout value for write transactions. + * PSU_DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT 0x4f + + * Port n Write QoS Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD070810, 0x000007FFU ,0x0000004FU) + */ + PSU_Mask_Write(DDRC_PCFGWQOS1_5_OFFSET, 0x000007FFU, 0x0000004FU); +/*##################################################################### */ + + /* + * Register : SARBASE0 @ 0XFD070F04 + + * Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x + * ] and araddr[UMCTL2_A_ADDRW-1:x] where x is determined by the minimum bl + * ock size parameter UMCTL2_SARMINSIZE: (x=log2(block size)). + * PSU_DDRC_SARBASE0_BASE_ADDR 0x0 + + * SAR Base Address Register n + * (OFFSET, MASK, VALUE) (0XFD070F04, 0x000001FFU ,0x00000000U) + */ + PSU_Mask_Write(DDRC_SARBASE0_OFFSET, 0x000001FFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : SARSIZE0 @ 0XFD070F08 + + * Number of blocks for address region n. This register determines the tota + * l size of the region in multiples of minimum block size as specified by + * the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded + * as number of blocks = nblocks + 1. For example, if register is programme + * d to 0, region will have 1 block. + * PSU_DDRC_SARSIZE0_NBLOCKS 0x0 + + * SAR Size Register n + * (OFFSET, MASK, VALUE) (0XFD070F08, 0x000000FFU ,0x00000000U) + */ + PSU_Mask_Write(DDRC_SARSIZE0_OFFSET, 0x000000FFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : SARBASE1 @ 0XFD070F0C + + * Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x + * ] and araddr[UMCTL2_A_ADDRW-1:x] where x is determined by the minimum bl + * ock size parameter UMCTL2_SARMINSIZE: (x=log2(block size)). + * PSU_DDRC_SARBASE1_BASE_ADDR 0x10 + + * SAR Base Address Register n + * (OFFSET, MASK, VALUE) (0XFD070F0C, 0x000001FFU ,0x00000010U) + */ + PSU_Mask_Write(DDRC_SARBASE1_OFFSET, 0x000001FFU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : SARSIZE1 @ 0XFD070F10 + + * Number of blocks for address region n. This register determines the tota + * l size of the region in multiples of minimum block size as specified by + * the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded + * as number of blocks = nblocks + 1. For example, if register is programme + * d to 0, region will have 1 block. + * PSU_DDRC_SARSIZE1_NBLOCKS 0xf + + * SAR Size Register n + * (OFFSET, MASK, VALUE) (0XFD070F10, 0x000000FFU ,0x0000000FU) + */ + PSU_Mask_Write(DDRC_SARSIZE1_OFFSET, 0x000000FFU, 0x0000000FU); +/*##################################################################### */ + + /* + * Register : DFITMG0_SHADOW @ 0XFD072190 + + * Specifies the number of DFI clock cycles after an assertion or de-assert + * ion of the DFI control signals that the control signals at the PHY-DRAM + * interface reflect the assertion or de-assertion. If the DFI clock and th + * e memory clock are not phase-aligned, this timing parameter should be ro + * unded up to the next integer value. Note that if using RDIMM, it is nece + * ssary to increment this parameter by RDIMM's extra cycle of latency in t + * erms of DFI clock. + * PSU_DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY 0x7 + + * Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated u + * sing HDR or SDR values Selects whether value in DFITMG0.dfi_t_rddata_en + * is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles + * - 1 in terms of SDR clock cycles Refer to PHY specification for correct + * value. + * PSU_DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR 0x1 + + * Time from the assertion of a read command on the DFI interface to the as + * sertion of the dfi_rddata_en signal. Refer to PHY specification for corr + * ect value. This corresponds to the DFI parameter trddata_en. Note that, + * depending on the PHY, if using RDIMM, it may be necessary to use the val + * ue (CL + 1) in the calculation of trddata_en. This is to compensate for + * the extra cycle of latency through the RDIMM. Unit: Clocks + * PSU_DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN 0x2 + + * Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated us + * ing HDR or SDR values Selects whether value in DFITMG0.dfi_tphy_wrlat is + * in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.df + * i_tphy_wrdata is in terms of SDR or HDR clock cycles - 0 in terms of HDR + * clock cycles - 1 in terms of SDR clock cycles Refer to PHY specificatio + * n for correct value. + * PSU_DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR 0x1 + + * Specifies the number of clock cycles between when dfi_wrdata_en is asser + * ted to when the associated write data is driven on the dfi_wrdata signal + * . This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY + * specification for correct value. Note, max supported value is 8. Unit: + * Clocks + * PSU_DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA 0x0 + + * Write latency Number of clocks from the write command to write data enab + * le (dfi_wrdata_en). This corresponds to the DFI timing parameter tphy_wr + * lat. Refer to PHY specification for correct value.Note that, depending o + * n the PHY, if using RDIMM, it may be necessary to use the value (CL + 1) + * in the calculation of tphy_wrlat. This is to compensate for the extra c + * ycle of latency through the RDIMM. + * PSU_DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT 0x2 + + * DFI Timing Shadow Register 0 + * (OFFSET, MASK, VALUE) (0XFD072190, 0x1FBFBF3FU ,0x07828002U) + */ + PSU_Mask_Write(DDRC_DFITMG0_SHADOW_OFFSET, 0x1FBFBF3FU, 0x07828002U); +/*##################################################################### */ + + /* + * DDR CONTROLLER RESET + */ + /* + * Register : RST_DDR_SS @ 0XFD1A0108 + + * DDR block level reset inside of the DDR Sub System + * PSU_CRF_APB_RST_DDR_SS_DDR_RESET 0X0 + + * APM block level reset inside of the DDR Sub System + * PSU_CRF_APB_RST_DDR_SS_APM_RESET 0X0 + + * DDR sub system block level reset + * (OFFSET, MASK, VALUE) (0XFD1A0108, 0x0000000CU ,0x00000000U) + */ + PSU_Mask_Write(CRF_APB_RST_DDR_SS_OFFSET, 0x0000000CU, 0x00000000U); +/*##################################################################### */ + + /* + * DDR PHY + */ + /* + * Register : PGCR0 @ 0XFD080010 + + * Address Copy + * PSU_DDR_PHY_PGCR0_ADCP 0x0 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_PGCR0_RESERVED_30_27 0x0 + + * PHY FIFO Reset + * PSU_DDR_PHY_PGCR0_PHYFRST 0x1 + + * Oscillator Mode Address/Command Delay Line Select + * PSU_DDR_PHY_PGCR0_OSCACDL 0x3 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_PGCR0_RESERVED_23_19 0x0 + + * Digital Test Output Select + * PSU_DDR_PHY_PGCR0_DTOSEL 0x0 - RegVal = ((0x0000000FU << DDRC_SARSIZE1_NBLOCKS_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_SARSIZE1_OFFSET ,0x000000FFU ,0x0000000FU); - /*############################################################################################################################ */ + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_PGCR0_RESERVED_13 0x0 - /*Register : DFITMG0_SHADOW @ 0XFD072190

+ * Oscillator Mode Division + * PSU_DDR_PHY_PGCR0_OSCDIV 0xf - Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signa - s at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligne - , this timing parameter should be rounded up to the next integer value. Note that if using RDIMM, it is necessary to incremen - this parameter by RDIMM's extra cycle of latency in terms of DFI clock. - PSU_DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY 0x7 - - Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR or SDR values Selects whether value in DFITM - 0.dfi_t_rddata_en is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles R - fer to PHY specification for correct value. - PSU_DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR 0x1 - - Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. Refer to PHY spe - ification for correct value. This corresponds to the DFI parameter trddata_en. Note that, depending on the PHY, if using RDIM - , it may be necessary to use the value (CL + 1) in the calculation of trddata_en. This is to compensate for the extra cycle o - latency through the RDIMM. Unit: Clocks - PSU_DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN 0x2 - - Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using HDR or SDR values Selects whether value in DFITMG - .dfi_tphy_wrlat is in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.dfi_tphy_wrdata is in terms of SDR or - HDR clock cycles - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles Refer to PHY specification for correct val - e. - PSU_DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR 0x1 - - Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on th - dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. N - te, max supported value is 8. Unit: Clocks - PSU_DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA 0x0 - - Write latency Number of clocks from the write command to write data enable (dfi_wrdata_en). This corresponds to the DFI timin - parameter tphy_wrlat. Refer to PHY specification for correct value.Note that, depending on the PHY, if using RDIMM, it may b - necessary to use the value (CL + 1) in the calculation of tphy_wrlat. This is to compensate for the extra cycle of latency t - rough the RDIMM. - PSU_DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT 0x2 + * Oscillator Enable + * PSU_DDR_PHY_PGCR0_OSCEN 0x0 - DFI Timing Shadow Register 0 - (OFFSET, MASK, VALUE) (0XFD072190, 0x1FBFBF3FU ,0x07828002U) - RegMask = (DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_MASK | DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_MASK | DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_MASK | DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_MASK | DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_MASK | DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_MASK | 0 ); + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_PGCR0_RESERVED_7_0 0x0 - RegVal = ((0x00000007U << DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_SHIFT - | 0x00000001U << DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_SHIFT - | 0x00000002U << DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_SHIFT - | 0x00000001U << DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_SHIFT - | 0x00000000U << DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_SHIFT - | 0x00000002U << DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DFITMG0_SHADOW_OFFSET ,0x1FBFBF3FU ,0x07828002U); - /*############################################################################################################################ */ - - // : DDR CONTROLLER RESET - /*Register : RST_DDR_SS @ 0XFD1A0108

- - DDR block level reset inside of the DDR Sub System - PSU_CRF_APB_RST_DDR_SS_DDR_RESET 0X0 - - DDR sub system block level reset - (OFFSET, MASK, VALUE) (0XFD1A0108, 0x00000008U ,0x00000000U) - RegMask = (CRF_APB_RST_DDR_SS_DDR_RESET_MASK | 0 ); - - RegVal = ((0x00000000U << CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_RST_DDR_SS_OFFSET ,0x00000008U ,0x00000000U); - /*############################################################################################################################ */ - - // : DDR PHY - /*Register : PGCR0 @ 0XFD080010

- - Address Copy - PSU_DDR_PHY_PGCR0_ADCP 0x0 - - Reserved. Returns zeroes on reads. - PSU_DDR_PHY_PGCR0_RESERVED_30_27 0x0 - - PHY FIFO Reset - PSU_DDR_PHY_PGCR0_PHYFRST 0x1 - - Oscillator Mode Address/Command Delay Line Select - PSU_DDR_PHY_PGCR0_OSCACDL 0x3 - - Reserved. Returns zeroes on reads. - PSU_DDR_PHY_PGCR0_RESERVED_23_19 0x0 + * PHY General Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD080010, 0xFFFFFFFFU ,0x07001E00U) + */ + PSU_Mask_Write(DDR_PHY_PGCR0_OFFSET, 0xFFFFFFFFU, 0x07001E00U); +/*##################################################################### */ - Digital Test Output Select - PSU_DDR_PHY_PGCR0_DTOSEL 0x0 + /* + * Register : PGCR2 @ 0XFD080018 - Reserved. Returns zeroes on reads. - PSU_DDR_PHY_PGCR0_RESERVED_13 0x0 + * Clear Training Status Registers + * PSU_DDR_PHY_PGCR2_CLRTSTAT 0x0 - Oscillator Mode Division - PSU_DDR_PHY_PGCR0_OSCDIV 0xf + * Clear Impedance Calibration + * PSU_DDR_PHY_PGCR2_CLRZCAL 0x0 - Oscillator Enable - PSU_DDR_PHY_PGCR0_OSCEN 0x0 + * Clear Parity Error + * PSU_DDR_PHY_PGCR2_CLRPERR 0x0 - Reserved. Returns zeroes on reads. - PSU_DDR_PHY_PGCR0_RESERVED_7_0 0x0 + * Initialization Complete Pin Configuration + * PSU_DDR_PHY_PGCR2_ICPC 0x0 - PHY General Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD080010, 0xFFFFFFFFU ,0x07001E00U) - RegMask = (DDR_PHY_PGCR0_ADCP_MASK | DDR_PHY_PGCR0_RESERVED_30_27_MASK | DDR_PHY_PGCR0_PHYFRST_MASK | DDR_PHY_PGCR0_OSCACDL_MASK | DDR_PHY_PGCR0_RESERVED_23_19_MASK | DDR_PHY_PGCR0_DTOSEL_MASK | DDR_PHY_PGCR0_RESERVED_13_MASK | DDR_PHY_PGCR0_OSCDIV_MASK | DDR_PHY_PGCR0_OSCEN_MASK | DDR_PHY_PGCR0_RESERVED_7_0_MASK | 0 ); + * Data Training PUB Mode Exit Timer + * PSU_DDR_PHY_PGCR2_DTPMXTMR 0xf - RegVal = ((0x00000000U << DDR_PHY_PGCR0_ADCP_SHIFT - | 0x00000000U << DDR_PHY_PGCR0_RESERVED_30_27_SHIFT - | 0x00000001U << DDR_PHY_PGCR0_PHYFRST_SHIFT - | 0x00000003U << DDR_PHY_PGCR0_OSCACDL_SHIFT - | 0x00000000U << DDR_PHY_PGCR0_RESERVED_23_19_SHIFT - | 0x00000000U << DDR_PHY_PGCR0_DTOSEL_SHIFT - | 0x00000000U << DDR_PHY_PGCR0_RESERVED_13_SHIFT - | 0x0000000FU << DDR_PHY_PGCR0_OSCDIV_SHIFT - | 0x00000000U << DDR_PHY_PGCR0_OSCEN_SHIFT - | 0x00000000U << DDR_PHY_PGCR0_RESERVED_7_0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_PGCR0_OFFSET ,0xFFFFFFFFU ,0x07001E00U); - /*############################################################################################################################ */ - - /*Register : PGCR2 @ 0XFD080018

+ * Initialization Bypass + * PSU_DDR_PHY_PGCR2_INITFSMBYP 0x0 - Clear Training Status Registers - PSU_DDR_PHY_PGCR2_CLRTSTAT 0x0 + * PLL FSM Bypass + * PSU_DDR_PHY_PGCR2_PLLFSMBYP 0x0 - Clear Impedance Calibration - PSU_DDR_PHY_PGCR2_CLRZCAL 0x0 + * Refresh Period + * PSU_DDR_PHY_PGCR2_TREFPRD 0x10010 - Clear Parity Error - PSU_DDR_PHY_PGCR2_CLRPERR 0x0 + * PHY General Configuration Register 2 + * (OFFSET, MASK, VALUE) (0XFD080018, 0xFFFFFFFFU ,0x00F10010U) + */ + PSU_Mask_Write(DDR_PHY_PGCR2_OFFSET, 0xFFFFFFFFU, 0x00F10010U); +/*##################################################################### */ - Initialization Complete Pin Configuration - PSU_DDR_PHY_PGCR2_ICPC 0x0 + /* + * Register : PGCR3 @ 0XFD08001C - Data Training PUB Mode Exit Timer - PSU_DDR_PHY_PGCR2_DTPMXTMR 0xf + * CKN Enable + * PSU_DDR_PHY_PGCR3_CKNEN 0x55 - Initialization Bypass - PSU_DDR_PHY_PGCR2_INITFSMBYP 0x0 + * CK Enable + * PSU_DDR_PHY_PGCR3_CKEN 0xaa - PLL FSM Bypass - PSU_DDR_PHY_PGCR2_PLLFSMBYP 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_PGCR3_RESERVED_15 0x0 - Refresh Period - PSU_DDR_PHY_PGCR2_TREFPRD 0x10028 + * Enable Clock Gating for AC [0] ctl_rd_clk + * PSU_DDR_PHY_PGCR3_GATEACRDCLK 0x2 - PHY General Configuration Register 2 - (OFFSET, MASK, VALUE) (0XFD080018, 0xFFFFFFFFU ,0x00F10028U) - RegMask = (DDR_PHY_PGCR2_CLRTSTAT_MASK | DDR_PHY_PGCR2_CLRZCAL_MASK | DDR_PHY_PGCR2_CLRPERR_MASK | DDR_PHY_PGCR2_ICPC_MASK | DDR_PHY_PGCR2_DTPMXTMR_MASK | DDR_PHY_PGCR2_INITFSMBYP_MASK | DDR_PHY_PGCR2_PLLFSMBYP_MASK | DDR_PHY_PGCR2_TREFPRD_MASK | 0 ); + * Enable Clock Gating for AC [0] ddr_clk + * PSU_DDR_PHY_PGCR3_GATEACDDRCLK 0x2 - RegVal = ((0x00000000U << DDR_PHY_PGCR2_CLRTSTAT_SHIFT - | 0x00000000U << DDR_PHY_PGCR2_CLRZCAL_SHIFT - | 0x00000000U << DDR_PHY_PGCR2_CLRPERR_SHIFT - | 0x00000000U << DDR_PHY_PGCR2_ICPC_SHIFT - | 0x0000000FU << DDR_PHY_PGCR2_DTPMXTMR_SHIFT - | 0x00000000U << DDR_PHY_PGCR2_INITFSMBYP_SHIFT - | 0x00000000U << DDR_PHY_PGCR2_PLLFSMBYP_SHIFT - | 0x00010028U << DDR_PHY_PGCR2_TREFPRD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_PGCR2_OFFSET ,0xFFFFFFFFU ,0x00F10028U); - /*############################################################################################################################ */ + * Enable Clock Gating for AC [0] ctl_clk + * PSU_DDR_PHY_PGCR3_GATEACCTLCLK 0x2 - /*Register : PGCR3 @ 0XFD08001C

+ * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_PGCR3_RESERVED_8 0x0 - CKN Enable - PSU_DDR_PHY_PGCR3_CKNEN 0x55 + * Controls DDL Bypass Modes + * PSU_DDR_PHY_PGCR3_DDLBYPMODE 0x2 - CK Enable - PSU_DDR_PHY_PGCR3_CKEN 0xaa + * IO Loop-Back Select + * PSU_DDR_PHY_PGCR3_IOLB 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_PGCR3_RESERVED_15 0x0 + * AC Receive FIFO Read Mode + * PSU_DDR_PHY_PGCR3_RDMODE 0x0 - Enable Clock Gating for AC [0] ctl_rd_clk - PSU_DDR_PHY_PGCR3_GATEACRDCLK 0x2 + * Read FIFO Reset Disable + * PSU_DDR_PHY_PGCR3_DISRST 0x0 - Enable Clock Gating for AC [0] ddr_clk - PSU_DDR_PHY_PGCR3_GATEACDDRCLK 0x2 + * Clock Level when Clock Gating + * PSU_DDR_PHY_PGCR3_CLKLEVEL 0x0 - Enable Clock Gating for AC [0] ctl_clk - PSU_DDR_PHY_PGCR3_GATEACCTLCLK 0x2 + * PHY General Configuration Register 3 + * (OFFSET, MASK, VALUE) (0XFD08001C, 0xFFFFFFFFU ,0x55AA5480U) + */ + PSU_Mask_Write(DDR_PHY_PGCR3_OFFSET, 0xFFFFFFFFU, 0x55AA5480U); +/*##################################################################### */ - Reserved. Return zeroes on reads. - PSU_DDR_PHY_PGCR3_RESERVED_8 0x0 + /* + * Register : PGCR5 @ 0XFD080024 - Controls DDL Bypass Modes - PSU_DDR_PHY_PGCR3_DDLBYPMODE 0x2 + * Frequency B Ratio Term + * PSU_DDR_PHY_PGCR5_FRQBT 0x1 - IO Loop-Back Select - PSU_DDR_PHY_PGCR3_IOLB 0x0 + * Frequency A Ratio Term + * PSU_DDR_PHY_PGCR5_FRQAT 0x1 - AC Receive FIFO Read Mode - PSU_DDR_PHY_PGCR3_RDMODE 0x0 + * DFI Disconnect Time Period + * PSU_DDR_PHY_PGCR5_DISCNPERIOD 0x0 - Read FIFO Reset Disable - PSU_DDR_PHY_PGCR3_DISRST 0x0 + * Receiver bias core side control + * PSU_DDR_PHY_PGCR5_VREF_RBCTRL 0xf - Clock Level when Clock Gating - PSU_DDR_PHY_PGCR3_CLKLEVEL 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_PGCR5_RESERVED_3 0x0 - PHY General Configuration Register 3 - (OFFSET, MASK, VALUE) (0XFD08001C, 0xFFFFFFFFU ,0x55AA5480U) - RegMask = (DDR_PHY_PGCR3_CKNEN_MASK | DDR_PHY_PGCR3_CKEN_MASK | DDR_PHY_PGCR3_RESERVED_15_MASK | DDR_PHY_PGCR3_GATEACRDCLK_MASK | DDR_PHY_PGCR3_GATEACDDRCLK_MASK | DDR_PHY_PGCR3_GATEACCTLCLK_MASK | DDR_PHY_PGCR3_RESERVED_8_MASK | DDR_PHY_PGCR3_DDLBYPMODE_MASK | DDR_PHY_PGCR3_IOLB_MASK | DDR_PHY_PGCR3_RDMODE_MASK | DDR_PHY_PGCR3_DISRST_MASK | DDR_PHY_PGCR3_CLKLEVEL_MASK | 0 ); + * Internal VREF generator REFSEL ragne select + * PSU_DDR_PHY_PGCR5_DXREFISELRANGE 0x1 - RegVal = ((0x00000055U << DDR_PHY_PGCR3_CKNEN_SHIFT - | 0x000000AAU << DDR_PHY_PGCR3_CKEN_SHIFT - | 0x00000000U << DDR_PHY_PGCR3_RESERVED_15_SHIFT - | 0x00000002U << DDR_PHY_PGCR3_GATEACRDCLK_SHIFT - | 0x00000002U << DDR_PHY_PGCR3_GATEACDDRCLK_SHIFT - | 0x00000002U << DDR_PHY_PGCR3_GATEACCTLCLK_SHIFT - | 0x00000000U << DDR_PHY_PGCR3_RESERVED_8_SHIFT - | 0x00000002U << DDR_PHY_PGCR3_DDLBYPMODE_SHIFT - | 0x00000000U << DDR_PHY_PGCR3_IOLB_SHIFT - | 0x00000000U << DDR_PHY_PGCR3_RDMODE_SHIFT - | 0x00000000U << DDR_PHY_PGCR3_DISRST_SHIFT - | 0x00000000U << DDR_PHY_PGCR3_CLKLEVEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_PGCR3_OFFSET ,0xFFFFFFFFU ,0x55AA5480U); - /*############################################################################################################################ */ + * DDL Page Read Write select + * PSU_DDR_PHY_PGCR5_DDLPGACT 0x0 - /*Register : PGCR5 @ 0XFD080024

+ * DDL Page Read Write select + * PSU_DDR_PHY_PGCR5_DDLPGRW 0x0 - Frequency B Ratio Term - PSU_DDR_PHY_PGCR5_FRQBT 0x1 + * PHY General Configuration Register 5 + * (OFFSET, MASK, VALUE) (0XFD080024, 0xFFFFFFFFU ,0x010100F4U) + */ + PSU_Mask_Write(DDR_PHY_PGCR5_OFFSET, 0xFFFFFFFFU, 0x010100F4U); +/*##################################################################### */ - Frequency A Ratio Term - PSU_DDR_PHY_PGCR5_FRQAT 0x1 + /* + * Register : PTR0 @ 0XFD080040 - DFI Disconnect Time Period - PSU_DDR_PHY_PGCR5_DISCNPERIOD 0x0 + * PLL Power-Down Time + * PSU_DDR_PHY_PTR0_TPLLPD 0x56 - Receiver bias core side control - PSU_DDR_PHY_PGCR5_VREF_RBCTRL 0xf + * PLL Gear Shift Time + * PSU_DDR_PHY_PTR0_TPLLGS 0x2155 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_PGCR5_RESERVED_3 0x0 + * PHY Reset Time + * PSU_DDR_PHY_PTR0_TPHYRST 0x10 - Internal VREF generator REFSEL ragne select - PSU_DDR_PHY_PGCR5_DXREFISELRANGE 0x1 + * PHY Timing Register 0 + * (OFFSET, MASK, VALUE) (0XFD080040, 0xFFFFFFFFU ,0x0AC85550U) + */ + PSU_Mask_Write(DDR_PHY_PTR0_OFFSET, 0xFFFFFFFFU, 0x0AC85550U); +/*##################################################################### */ - DDL Page Read Write select - PSU_DDR_PHY_PGCR5_DDLPGACT 0x0 + /* + * Register : PTR1 @ 0XFD080044 - DDL Page Read Write select - PSU_DDR_PHY_PGCR5_DDLPGRW 0x0 + * PLL Lock Time + * PSU_DDR_PHY_PTR1_TPLLLOCK 0x4141 - PHY General Configuration Register 5 - (OFFSET, MASK, VALUE) (0XFD080024, 0xFFFFFFFFU ,0x010100F4U) - RegMask = (DDR_PHY_PGCR5_FRQBT_MASK | DDR_PHY_PGCR5_FRQAT_MASK | DDR_PHY_PGCR5_DISCNPERIOD_MASK | DDR_PHY_PGCR5_VREF_RBCTRL_MASK | DDR_PHY_PGCR5_RESERVED_3_MASK | DDR_PHY_PGCR5_DXREFISELRANGE_MASK | DDR_PHY_PGCR5_DDLPGACT_MASK | DDR_PHY_PGCR5_DDLPGRW_MASK | 0 ); + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_PTR1_RESERVED_15_13 0x0 - RegVal = ((0x00000001U << DDR_PHY_PGCR5_FRQBT_SHIFT - | 0x00000001U << DDR_PHY_PGCR5_FRQAT_SHIFT - | 0x00000000U << DDR_PHY_PGCR5_DISCNPERIOD_SHIFT - | 0x0000000FU << DDR_PHY_PGCR5_VREF_RBCTRL_SHIFT - | 0x00000000U << DDR_PHY_PGCR5_RESERVED_3_SHIFT - | 0x00000001U << DDR_PHY_PGCR5_DXREFISELRANGE_SHIFT - | 0x00000000U << DDR_PHY_PGCR5_DDLPGACT_SHIFT - | 0x00000000U << DDR_PHY_PGCR5_DDLPGRW_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_PGCR5_OFFSET ,0xFFFFFFFFU ,0x010100F4U); - /*############################################################################################################################ */ + * PLL Reset Time + * PSU_DDR_PHY_PTR1_TPLLRST 0xaff - /*Register : PTR0 @ 0XFD080040

+ * PHY Timing Register 1 + * (OFFSET, MASK, VALUE) (0XFD080044, 0xFFFFFFFFU ,0x41410AFFU) + */ + PSU_Mask_Write(DDR_PHY_PTR1_OFFSET, 0xFFFFFFFFU, 0x41410AFFU); +/*##################################################################### */ - PLL Power-Down Time - PSU_DDR_PHY_PTR0_TPLLPD 0x2f0 + /* + * Register : PLLCR0 @ 0XFD080068 - PLL Gear Shift Time - PSU_DDR_PHY_PTR0_TPLLGS 0x60 + * PLL Bypass + * PSU_DDR_PHY_PLLCR0_PLLBYP 0x0 - PHY Reset Time - PSU_DDR_PHY_PTR0_TPHYRST 0x10 + * PLL Reset + * PSU_DDR_PHY_PLLCR0_PLLRST 0x0 - PHY Timing Register 0 - (OFFSET, MASK, VALUE) (0XFD080040, 0xFFFFFFFFU ,0x5E001810U) - RegMask = (DDR_PHY_PTR0_TPLLPD_MASK | DDR_PHY_PTR0_TPLLGS_MASK | DDR_PHY_PTR0_TPHYRST_MASK | 0 ); + * PLL Power Down + * PSU_DDR_PHY_PLLCR0_PLLPD 0x0 - RegVal = ((0x000002F0U << DDR_PHY_PTR0_TPLLPD_SHIFT - | 0x00000060U << DDR_PHY_PTR0_TPLLGS_SHIFT - | 0x00000010U << DDR_PHY_PTR0_TPHYRST_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_PTR0_OFFSET ,0xFFFFFFFFU ,0x5E001810U); - /*############################################################################################################################ */ + * Reference Stop Mode + * PSU_DDR_PHY_PLLCR0_RSTOPM 0x0 - /*Register : PTR1 @ 0XFD080044

+ * PLL Frequency Select + * PSU_DDR_PHY_PLLCR0_FRQSEL 0x1 - PLL Lock Time - PSU_DDR_PHY_PTR1_TPLLLOCK 0x80 + * Relock Mode + * PSU_DDR_PHY_PLLCR0_RLOCKM 0x0 - Reserved. Returns zeroes on reads. - PSU_DDR_PHY_PTR1_RESERVED_15_13 0x0 + * Charge Pump Proportional Current Control + * PSU_DDR_PHY_PLLCR0_CPPC 0x8 - PLL Reset Time - PSU_DDR_PHY_PTR1_TPLLRST 0x5f0 - - PHY Timing Register 1 - (OFFSET, MASK, VALUE) (0XFD080044, 0xFFFFFFFFU ,0x008005F0U) - RegMask = (DDR_PHY_PTR1_TPLLLOCK_MASK | DDR_PHY_PTR1_RESERVED_15_13_MASK | DDR_PHY_PTR1_TPLLRST_MASK | 0 ); + * Charge Pump Integrating Current Control + * PSU_DDR_PHY_PLLCR0_CPIC 0x0 - RegVal = ((0x00000080U << DDR_PHY_PTR1_TPLLLOCK_SHIFT - | 0x00000000U << DDR_PHY_PTR1_RESERVED_15_13_SHIFT - | 0x000005F0U << DDR_PHY_PTR1_TPLLRST_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_PTR1_OFFSET ,0xFFFFFFFFU ,0x008005F0U); - /*############################################################################################################################ */ + * Gear Shift + * PSU_DDR_PHY_PLLCR0_GSHIFT 0x0 - /*Register : DSGCR @ 0XFD080090

+ * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_PLLCR0_RESERVED_11_9 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DSGCR_RESERVED_31_28 0x0 + * Analog Test Enable + * PSU_DDR_PHY_PLLCR0_ATOEN 0x0 - When RDBI enabled, this bit is used to select RDBI CL calculation, if it is 1b1, calculation will use RDBICL, otherwise use d - fault calculation. - PSU_DDR_PHY_DSGCR_RDBICLSEL 0x0 + * Analog Test Control + * PSU_DDR_PHY_PLLCR0_ATC 0x0 - When RDBI enabled, if RDBICLSEL is asserted, RDBI CL adjust using this value. - PSU_DDR_PHY_DSGCR_RDBICL 0x2 + * Digital Test Control + * PSU_DDR_PHY_PLLCR0_DTC 0x0 - PHY Impedance Update Enable - PSU_DDR_PHY_DSGCR_PHYZUEN 0x1 + * PLL Control Register 0 (Type B PLL Only) + * (OFFSET, MASK, VALUE) (0XFD080068, 0xFFFFFFFFU ,0x01100000U) + */ + PSU_Mask_Write(DDR_PHY_PLLCR0_OFFSET, 0xFFFFFFFFU, 0x01100000U); +/*##################################################################### */ - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DSGCR_RESERVED_22 0x0 + /* + * Register : DSGCR @ 0XFD080090 - SDRAM Reset Output Enable - PSU_DDR_PHY_DSGCR_RSTOE 0x1 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DSGCR_RESERVED_31_28 0x0 - Single Data Rate Mode - PSU_DDR_PHY_DSGCR_SDRMODE 0x0 + * When RDBI enabled, this bit is used to select RDBI CL calculation, if it + * is 1b1, calculation will use RDBICL, otherwise use default calculation. + * PSU_DDR_PHY_DSGCR_RDBICLSEL 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DSGCR_RESERVED_18 0x0 + * When RDBI enabled, if RDBICLSEL is asserted, RDBI CL adjust using this v + * alue. + * PSU_DDR_PHY_DSGCR_RDBICL 0x2 - ATO Analog Test Enable - PSU_DDR_PHY_DSGCR_ATOAE 0x0 + * PHY Impedance Update Enable + * PSU_DDR_PHY_DSGCR_PHYZUEN 0x1 - DTO Output Enable - PSU_DDR_PHY_DSGCR_DTOOE 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DSGCR_RESERVED_22 0x0 - DTO I/O Mode - PSU_DDR_PHY_DSGCR_DTOIOM 0x0 + * SDRAM Reset Output Enable + * PSU_DDR_PHY_DSGCR_RSTOE 0x1 - DTO Power Down Receiver - PSU_DDR_PHY_DSGCR_DTOPDR 0x1 + * Single Data Rate Mode + * PSU_DDR_PHY_DSGCR_SDRMODE 0x0 - Reserved. Return zeroes on reads - PSU_DDR_PHY_DSGCR_RESERVED_13 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DSGCR_RESERVED_18 0x0 - DTO On-Die Termination - PSU_DDR_PHY_DSGCR_DTOODT 0x0 + * ATO Analog Test Enable + * PSU_DDR_PHY_DSGCR_ATOAE 0x0 - PHY Update Acknowledge Delay - PSU_DDR_PHY_DSGCR_PUAD 0x4 + * DTO Output Enable + * PSU_DDR_PHY_DSGCR_DTOOE 0x0 - Controller Update Acknowledge Enable - PSU_DDR_PHY_DSGCR_CUAEN 0x1 + * DTO I/O Mode + * PSU_DDR_PHY_DSGCR_DTOIOM 0x0 - Reserved. Return zeroes on reads - PSU_DDR_PHY_DSGCR_RESERVED_4_3 0x0 + * DTO Power Down Receiver + * PSU_DDR_PHY_DSGCR_DTOPDR 0x1 - Controller Impedance Update Enable - PSU_DDR_PHY_DSGCR_CTLZUEN 0x0 + * Reserved. Return zeroes on reads + * PSU_DDR_PHY_DSGCR_RESERVED_13 0x0 - Reserved. Return zeroes on reads - PSU_DDR_PHY_DSGCR_RESERVED_1 0x0 + * DTO On-Die Termination + * PSU_DDR_PHY_DSGCR_DTOODT 0x0 - PHY Update Request Enable - PSU_DDR_PHY_DSGCR_PUREN 0x1 + * PHY Update Acknowledge Delay + * PSU_DDR_PHY_DSGCR_PUAD 0x5 - DDR System General Configuration Register - (OFFSET, MASK, VALUE) (0XFD080090, 0xFFFFFFFFU ,0x02A04121U) - RegMask = (DDR_PHY_DSGCR_RESERVED_31_28_MASK | DDR_PHY_DSGCR_RDBICLSEL_MASK | DDR_PHY_DSGCR_RDBICL_MASK | DDR_PHY_DSGCR_PHYZUEN_MASK | DDR_PHY_DSGCR_RESERVED_22_MASK | DDR_PHY_DSGCR_RSTOE_MASK | DDR_PHY_DSGCR_SDRMODE_MASK | DDR_PHY_DSGCR_RESERVED_18_MASK | DDR_PHY_DSGCR_ATOAE_MASK | DDR_PHY_DSGCR_DTOOE_MASK | DDR_PHY_DSGCR_DTOIOM_MASK | DDR_PHY_DSGCR_DTOPDR_MASK | DDR_PHY_DSGCR_RESERVED_13_MASK | DDR_PHY_DSGCR_DTOODT_MASK | DDR_PHY_DSGCR_PUAD_MASK | DDR_PHY_DSGCR_CUAEN_MASK | DDR_PHY_DSGCR_RESERVED_4_3_MASK | DDR_PHY_DSGCR_CTLZUEN_MASK | DDR_PHY_DSGCR_RESERVED_1_MASK | DDR_PHY_DSGCR_PUREN_MASK | 0 ); + * Controller Update Acknowledge Enable + * PSU_DDR_PHY_DSGCR_CUAEN 0x1 - RegVal = ((0x00000000U << DDR_PHY_DSGCR_RESERVED_31_28_SHIFT - | 0x00000000U << DDR_PHY_DSGCR_RDBICLSEL_SHIFT - | 0x00000002U << DDR_PHY_DSGCR_RDBICL_SHIFT - | 0x00000001U << DDR_PHY_DSGCR_PHYZUEN_SHIFT - | 0x00000000U << DDR_PHY_DSGCR_RESERVED_22_SHIFT - | 0x00000001U << DDR_PHY_DSGCR_RSTOE_SHIFT - | 0x00000000U << DDR_PHY_DSGCR_SDRMODE_SHIFT - | 0x00000000U << DDR_PHY_DSGCR_RESERVED_18_SHIFT - | 0x00000000U << DDR_PHY_DSGCR_ATOAE_SHIFT - | 0x00000000U << DDR_PHY_DSGCR_DTOOE_SHIFT - | 0x00000000U << DDR_PHY_DSGCR_DTOIOM_SHIFT - | 0x00000001U << DDR_PHY_DSGCR_DTOPDR_SHIFT - | 0x00000000U << DDR_PHY_DSGCR_RESERVED_13_SHIFT - | 0x00000000U << DDR_PHY_DSGCR_DTOODT_SHIFT - | 0x00000004U << DDR_PHY_DSGCR_PUAD_SHIFT - | 0x00000001U << DDR_PHY_DSGCR_CUAEN_SHIFT - | 0x00000000U << DDR_PHY_DSGCR_RESERVED_4_3_SHIFT - | 0x00000000U << DDR_PHY_DSGCR_CTLZUEN_SHIFT - | 0x00000000U << DDR_PHY_DSGCR_RESERVED_1_SHIFT - | 0x00000001U << DDR_PHY_DSGCR_PUREN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DSGCR_OFFSET ,0xFFFFFFFFU ,0x02A04121U); - /*############################################################################################################################ */ + * Reserved. Return zeroes on reads + * PSU_DDR_PHY_DSGCR_RESERVED_4_3 0x0 - /*Register : DCR @ 0XFD080100

+ * Controller Impedance Update Enable + * PSU_DDR_PHY_DSGCR_CTLZUEN 0x0 - DDR4 Gear Down Timing. - PSU_DDR_PHY_DCR_GEARDN 0x0 + * Reserved. Return zeroes on reads + * PSU_DDR_PHY_DSGCR_RESERVED_1 0x0 - Un-used Bank Group - PSU_DDR_PHY_DCR_UBG 0x0 + * PHY Update Request Enable + * PSU_DDR_PHY_DSGCR_PUREN 0x1 - Un-buffered DIMM Address Mirroring - PSU_DDR_PHY_DCR_UDIMM 0x0 + * DDR System General Configuration Register + * (OFFSET, MASK, VALUE) (0XFD080090, 0xFFFFFFFFU ,0x02A04161U) + */ + PSU_Mask_Write(DDR_PHY_DSGCR_OFFSET, 0xFFFFFFFFU, 0x02A04161U); +/*##################################################################### */ - DDR 2T Timing - PSU_DDR_PHY_DCR_DDR2T 0x0 + /* + * Register : GPR0 @ 0XFD0800C0 - No Simultaneous Rank Access - PSU_DDR_PHY_DCR_NOSRA 0x1 + * General Purpose Register 0 + * PSU_DDR_PHY_GPR0_GPR0 0xd3 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DCR_RESERVED_26_18 0x0 + * General Purpose Register 0 + * (OFFSET, MASK, VALUE) (0XFD0800C0, 0xFFFFFFFFU ,0x000000D3U) + */ + PSU_Mask_Write(DDR_PHY_GPR0_OFFSET, 0xFFFFFFFFU, 0x000000D3U); +/*##################################################################### */ - Byte Mask - PSU_DDR_PHY_DCR_BYTEMASK 0x1 + /* + * Register : DCR @ 0XFD080100 - DDR Type - PSU_DDR_PHY_DCR_DDRTYPE 0x0 + * DDR4 Gear Down Timing. + * PSU_DDR_PHY_DCR_GEARDN 0x0 - Multi-Purpose Register (MPR) DQ (DDR3 Only) - PSU_DDR_PHY_DCR_MPRDQ 0x0 + * Un-used Bank Group + * PSU_DDR_PHY_DCR_UBG 0x0 - Primary DQ (DDR3 Only) - PSU_DDR_PHY_DCR_PDQ 0x0 + * Un-buffered DIMM Address Mirroring + * PSU_DDR_PHY_DCR_UDIMM 0x0 - DDR 8-Bank - PSU_DDR_PHY_DCR_DDR8BNK 0x1 + * DDR 2T Timing + * PSU_DDR_PHY_DCR_DDR2T 0x0 - DDR Mode - PSU_DDR_PHY_DCR_DDRMD 0x4 + * No Simultaneous Rank Access + * PSU_DDR_PHY_DCR_NOSRA 0x1 - DRAM Configuration Register - (OFFSET, MASK, VALUE) (0XFD080100, 0xFFFFFFFFU ,0x0800040CU) - RegMask = (DDR_PHY_DCR_GEARDN_MASK | DDR_PHY_DCR_UBG_MASK | DDR_PHY_DCR_UDIMM_MASK | DDR_PHY_DCR_DDR2T_MASK | DDR_PHY_DCR_NOSRA_MASK | DDR_PHY_DCR_RESERVED_26_18_MASK | DDR_PHY_DCR_BYTEMASK_MASK | DDR_PHY_DCR_DDRTYPE_MASK | DDR_PHY_DCR_MPRDQ_MASK | DDR_PHY_DCR_PDQ_MASK | DDR_PHY_DCR_DDR8BNK_MASK | DDR_PHY_DCR_DDRMD_MASK | 0 ); + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DCR_RESERVED_26_18 0x0 - RegVal = ((0x00000000U << DDR_PHY_DCR_GEARDN_SHIFT - | 0x00000000U << DDR_PHY_DCR_UBG_SHIFT - | 0x00000000U << DDR_PHY_DCR_UDIMM_SHIFT - | 0x00000000U << DDR_PHY_DCR_DDR2T_SHIFT - | 0x00000001U << DDR_PHY_DCR_NOSRA_SHIFT - | 0x00000000U << DDR_PHY_DCR_RESERVED_26_18_SHIFT - | 0x00000001U << DDR_PHY_DCR_BYTEMASK_SHIFT - | 0x00000000U << DDR_PHY_DCR_DDRTYPE_SHIFT - | 0x00000000U << DDR_PHY_DCR_MPRDQ_SHIFT - | 0x00000000U << DDR_PHY_DCR_PDQ_SHIFT - | 0x00000001U << DDR_PHY_DCR_DDR8BNK_SHIFT - | 0x00000004U << DDR_PHY_DCR_DDRMD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DCR_OFFSET ,0xFFFFFFFFU ,0x0800040CU); - /*############################################################################################################################ */ - - /*Register : DTPR0 @ 0XFD080110

+ * Byte Mask + * PSU_DDR_PHY_DCR_BYTEMASK 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR0_RESERVED_31_29 0x0 + * DDR Type + * PSU_DDR_PHY_DCR_DDRTYPE 0x0 - Activate to activate command delay (different banks) - PSU_DDR_PHY_DTPR0_TRRD 0x6 + * Multi-Purpose Register (MPR) DQ (DDR3 Only) + * PSU_DDR_PHY_DCR_MPRDQ 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR0_RESERVED_23 0x0 + * Primary DQ (DDR3 Only) + * PSU_DDR_PHY_DCR_PDQ 0x0 - Activate to precharge command delay - PSU_DDR_PHY_DTPR0_TRAS 0x24 + * DDR 8-Bank + * PSU_DDR_PHY_DCR_DDR8BNK 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR0_RESERVED_15 0x0 - - Precharge command period - PSU_DDR_PHY_DTPR0_TRP 0xf - - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR0_RESERVED_7_5 0x0 - - Internal read to precharge command delay - PSU_DDR_PHY_DTPR0_TRTP 0x9 - - DRAM Timing Parameters Register 0 - (OFFSET, MASK, VALUE) (0XFD080110, 0xFFFFFFFFU ,0x06240F09U) - RegMask = (DDR_PHY_DTPR0_RESERVED_31_29_MASK | DDR_PHY_DTPR0_TRRD_MASK | DDR_PHY_DTPR0_RESERVED_23_MASK | DDR_PHY_DTPR0_TRAS_MASK | DDR_PHY_DTPR0_RESERVED_15_MASK | DDR_PHY_DTPR0_TRP_MASK | DDR_PHY_DTPR0_RESERVED_7_5_MASK | DDR_PHY_DTPR0_TRTP_MASK | 0 ); + * DDR Mode + * PSU_DDR_PHY_DCR_DDRMD 0x4 - RegVal = ((0x00000000U << DDR_PHY_DTPR0_RESERVED_31_29_SHIFT - | 0x00000006U << DDR_PHY_DTPR0_TRRD_SHIFT - | 0x00000000U << DDR_PHY_DTPR0_RESERVED_23_SHIFT - | 0x00000024U << DDR_PHY_DTPR0_TRAS_SHIFT - | 0x00000000U << DDR_PHY_DTPR0_RESERVED_15_SHIFT - | 0x0000000FU << DDR_PHY_DTPR0_TRP_SHIFT - | 0x00000000U << DDR_PHY_DTPR0_RESERVED_7_5_SHIFT - | 0x00000009U << DDR_PHY_DTPR0_TRTP_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DTPR0_OFFSET ,0xFFFFFFFFU ,0x06240F09U); - /*############################################################################################################################ */ + * DRAM Configuration Register + * (OFFSET, MASK, VALUE) (0XFD080100, 0xFFFFFFFFU ,0x0800040CU) + */ + PSU_Mask_Write(DDR_PHY_DCR_OFFSET, 0xFFFFFFFFU, 0x0800040CU); +/*##################################################################### */ - /*Register : DTPR1 @ 0XFD080114

+ /* + * Register : DTPR0 @ 0XFD080110 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR1_RESERVED_31 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR0_RESERVED_31_29 0x0 - Minimum delay from when write leveling mode is programmed to the first DQS/DQS# rising edge. - PSU_DDR_PHY_DTPR1_TWLMRD 0x28 + * Activate to activate command delay (different banks) + * PSU_DDR_PHY_DTPR0_TRRD 0x6 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR1_RESERVED_23 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR0_RESERVED_23 0x0 - 4-bank activate period - PSU_DDR_PHY_DTPR1_TFAW 0x18 + * Activate to precharge command delay + * PSU_DDR_PHY_DTPR0_TRAS 0x24 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR1_RESERVED_15_11 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR0_RESERVED_15 0x0 - Load mode update delay (DDR4 and DDR3 only) - PSU_DDR_PHY_DTPR1_TMOD 0x7 + * Precharge command period + * PSU_DDR_PHY_DTPR0_TRP 0xf - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR1_RESERVED_7_5 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR0_RESERVED_7_5 0x0 - Load mode cycle time - PSU_DDR_PHY_DTPR1_TMRD 0x8 + * Internal read to precharge command delay + * PSU_DDR_PHY_DTPR0_TRTP 0x8 - DRAM Timing Parameters Register 1 - (OFFSET, MASK, VALUE) (0XFD080114, 0xFFFFFFFFU ,0x28180708U) - RegMask = (DDR_PHY_DTPR1_RESERVED_31_MASK | DDR_PHY_DTPR1_TWLMRD_MASK | DDR_PHY_DTPR1_RESERVED_23_MASK | DDR_PHY_DTPR1_TFAW_MASK | DDR_PHY_DTPR1_RESERVED_15_11_MASK | DDR_PHY_DTPR1_TMOD_MASK | DDR_PHY_DTPR1_RESERVED_7_5_MASK | DDR_PHY_DTPR1_TMRD_MASK | 0 ); + * DRAM Timing Parameters Register 0 + * (OFFSET, MASK, VALUE) (0XFD080110, 0xFFFFFFFFU ,0x06240F08U) + */ + PSU_Mask_Write(DDR_PHY_DTPR0_OFFSET, 0xFFFFFFFFU, 0x06240F08U); +/*##################################################################### */ - RegVal = ((0x00000000U << DDR_PHY_DTPR1_RESERVED_31_SHIFT - | 0x00000028U << DDR_PHY_DTPR1_TWLMRD_SHIFT - | 0x00000000U << DDR_PHY_DTPR1_RESERVED_23_SHIFT - | 0x00000018U << DDR_PHY_DTPR1_TFAW_SHIFT - | 0x00000000U << DDR_PHY_DTPR1_RESERVED_15_11_SHIFT - | 0x00000007U << DDR_PHY_DTPR1_TMOD_SHIFT - | 0x00000000U << DDR_PHY_DTPR1_RESERVED_7_5_SHIFT - | 0x00000008U << DDR_PHY_DTPR1_TMRD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DTPR1_OFFSET ,0xFFFFFFFFU ,0x28180708U); - /*############################################################################################################################ */ + /* + * Register : DTPR1 @ 0XFD080114 - /*Register : DTPR2 @ 0XFD080118

+ * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR1_RESERVED_31 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR2_RESERVED_31_29 0x0 + * Minimum delay from when write leveling mode is programmed to the first D + * QS/DQS# rising edge. + * PSU_DDR_PHY_DTPR1_TWLMRD 0x28 - Read to Write command delay. Valid values are - PSU_DDR_PHY_DTPR2_TRTW 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR1_RESERVED_23 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR2_RESERVED_27_25 0x0 + * 4-bank activate period + * PSU_DDR_PHY_DTPR1_TFAW 0x20 - Read to ODT delay (DDR3 only) - PSU_DDR_PHY_DTPR2_TRTODT 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR1_RESERVED_15_11 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR2_RESERVED_23_20 0x0 + * Load mode update delay (DDR4 and DDR3 only) + * PSU_DDR_PHY_DTPR1_TMOD 0x0 - CKE minimum pulse width - PSU_DDR_PHY_DTPR2_TCKE 0x8 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR1_RESERVED_7_5 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR2_RESERVED_15_10 0x0 + * Load mode cycle time + * PSU_DDR_PHY_DTPR1_TMRD 0x8 - Self refresh exit delay - PSU_DDR_PHY_DTPR2_TXS 0x200 + * DRAM Timing Parameters Register 1 + * (OFFSET, MASK, VALUE) (0XFD080114, 0xFFFFFFFFU ,0x28200008U) + */ + PSU_Mask_Write(DDR_PHY_DTPR1_OFFSET, 0xFFFFFFFFU, 0x28200008U); +/*##################################################################### */ - DRAM Timing Parameters Register 2 - (OFFSET, MASK, VALUE) (0XFD080118, 0xFFFFFFFFU ,0x00080200U) - RegMask = (DDR_PHY_DTPR2_RESERVED_31_29_MASK | DDR_PHY_DTPR2_TRTW_MASK | DDR_PHY_DTPR2_RESERVED_27_25_MASK | DDR_PHY_DTPR2_TRTODT_MASK | DDR_PHY_DTPR2_RESERVED_23_20_MASK | DDR_PHY_DTPR2_TCKE_MASK | DDR_PHY_DTPR2_RESERVED_15_10_MASK | DDR_PHY_DTPR2_TXS_MASK | 0 ); + /* + * Register : DTPR2 @ 0XFD080118 - RegVal = ((0x00000000U << DDR_PHY_DTPR2_RESERVED_31_29_SHIFT - | 0x00000000U << DDR_PHY_DTPR2_TRTW_SHIFT - | 0x00000000U << DDR_PHY_DTPR2_RESERVED_27_25_SHIFT - | 0x00000000U << DDR_PHY_DTPR2_TRTODT_SHIFT - | 0x00000000U << DDR_PHY_DTPR2_RESERVED_23_20_SHIFT - | 0x00000008U << DDR_PHY_DTPR2_TCKE_SHIFT - | 0x00000000U << DDR_PHY_DTPR2_RESERVED_15_10_SHIFT - | 0x00000200U << DDR_PHY_DTPR2_TXS_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DTPR2_OFFSET ,0xFFFFFFFFU ,0x00080200U); - /*############################################################################################################################ */ + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR2_RESERVED_31_29 0x0 - /*Register : DTPR3 @ 0XFD08011C

+ * Read to Write command delay. Valid values are + * PSU_DDR_PHY_DTPR2_TRTW 0x0 - ODT turn-off delay extension - PSU_DDR_PHY_DTPR3_TOFDX 0x4 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR2_RESERVED_27_25 0x0 - Read to read and write to write command delay - PSU_DDR_PHY_DTPR3_TCCD 0x0 + * Read to ODT delay (DDR3 only) + * PSU_DDR_PHY_DTPR2_TRTODT 0x0 - DLL locking time - PSU_DDR_PHY_DTPR3_TDLLK 0x300 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR2_RESERVED_23_20 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR3_RESERVED_15_12 0x0 + * CKE minimum pulse width + * PSU_DDR_PHY_DTPR2_TCKE 0x7 - Maximum DQS output access time from CK/CK# (LPDDR2/3 only) - PSU_DDR_PHY_DTPR3_TDQSCKMAX 0x8 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR2_RESERVED_15_10 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR3_RESERVED_7_3 0x0 + * Self refresh exit delay + * PSU_DDR_PHY_DTPR2_TXS 0x300 - DQS output access time from CK/CK# (LPDDR2/3 only) - PSU_DDR_PHY_DTPR3_TDQSCK 0x0 + * DRAM Timing Parameters Register 2 + * (OFFSET, MASK, VALUE) (0XFD080118, 0xFFFFFFFFU ,0x00070300U) + */ + PSU_Mask_Write(DDR_PHY_DTPR2_OFFSET, 0xFFFFFFFFU, 0x00070300U); +/*##################################################################### */ - DRAM Timing Parameters Register 3 - (OFFSET, MASK, VALUE) (0XFD08011C, 0xFFFFFFFFU ,0x83000800U) - RegMask = (DDR_PHY_DTPR3_TOFDX_MASK | DDR_PHY_DTPR3_TCCD_MASK | DDR_PHY_DTPR3_TDLLK_MASK | DDR_PHY_DTPR3_RESERVED_15_12_MASK | DDR_PHY_DTPR3_TDQSCKMAX_MASK | DDR_PHY_DTPR3_RESERVED_7_3_MASK | DDR_PHY_DTPR3_TDQSCK_MASK | 0 ); + /* + * Register : DTPR3 @ 0XFD08011C - RegVal = ((0x00000004U << DDR_PHY_DTPR3_TOFDX_SHIFT - | 0x00000000U << DDR_PHY_DTPR3_TCCD_SHIFT - | 0x00000300U << DDR_PHY_DTPR3_TDLLK_SHIFT - | 0x00000000U << DDR_PHY_DTPR3_RESERVED_15_12_SHIFT - | 0x00000008U << DDR_PHY_DTPR3_TDQSCKMAX_SHIFT - | 0x00000000U << DDR_PHY_DTPR3_RESERVED_7_3_SHIFT - | 0x00000000U << DDR_PHY_DTPR3_TDQSCK_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DTPR3_OFFSET ,0xFFFFFFFFU ,0x83000800U); - /*############################################################################################################################ */ + * ODT turn-off delay extension + * PSU_DDR_PHY_DTPR3_TOFDX 0x4 - /*Register : DTPR4 @ 0XFD080120

+ * Read to read and write to write command delay + * PSU_DDR_PHY_DTPR3_TCCD 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR4_RESERVED_31_30 0x0 + * DLL locking time + * PSU_DDR_PHY_DTPR3_TDLLK 0x300 - ODT turn-on/turn-off delays (DDR2 only) - PSU_DDR_PHY_DTPR4_TAOND_TAOFD 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR3_RESERVED_15_12 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR4_RESERVED_27_26 0x0 + * Maximum DQS output access time from CK/CK# (LPDDR2/3 only) + * PSU_DDR_PHY_DTPR3_TDQSCKMAX 0x8 - Refresh-to-Refresh - PSU_DDR_PHY_DTPR4_TRFC 0x116 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR3_RESERVED_7_3 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR4_RESERVED_15_14 0x0 + * DQS output access time from CK/CK# (LPDDR2/3 only) + * PSU_DDR_PHY_DTPR3_TDQSCK 0x0 - Write leveling output delay - PSU_DDR_PHY_DTPR4_TWLO 0x2b + * DRAM Timing Parameters Register 3 + * (OFFSET, MASK, VALUE) (0XFD08011C, 0xFFFFFFFFU ,0x83000800U) + */ + PSU_Mask_Write(DDR_PHY_DTPR3_OFFSET, 0xFFFFFFFFU, 0x83000800U); +/*##################################################################### */ - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR4_RESERVED_7_5 0x0 + /* + * Register : DTPR4 @ 0XFD080120 - Power down exit delay - PSU_DDR_PHY_DTPR4_TXP 0x8 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR4_RESERVED_31_30 0x0 - DRAM Timing Parameters Register 4 - (OFFSET, MASK, VALUE) (0XFD080120, 0xFFFFFFFFU ,0x01162B08U) - RegMask = (DDR_PHY_DTPR4_RESERVED_31_30_MASK | DDR_PHY_DTPR4_TAOND_TAOFD_MASK | DDR_PHY_DTPR4_RESERVED_27_26_MASK | DDR_PHY_DTPR4_TRFC_MASK | DDR_PHY_DTPR4_RESERVED_15_14_MASK | DDR_PHY_DTPR4_TWLO_MASK | DDR_PHY_DTPR4_RESERVED_7_5_MASK | DDR_PHY_DTPR4_TXP_MASK | 0 ); + * ODT turn-on/turn-off delays (DDR2 only) + * PSU_DDR_PHY_DTPR4_TAOND_TAOFD 0x0 - RegVal = ((0x00000000U << DDR_PHY_DTPR4_RESERVED_31_30_SHIFT - | 0x00000000U << DDR_PHY_DTPR4_TAOND_TAOFD_SHIFT - | 0x00000000U << DDR_PHY_DTPR4_RESERVED_27_26_SHIFT - | 0x00000116U << DDR_PHY_DTPR4_TRFC_SHIFT - | 0x00000000U << DDR_PHY_DTPR4_RESERVED_15_14_SHIFT - | 0x0000002BU << DDR_PHY_DTPR4_TWLO_SHIFT - | 0x00000000U << DDR_PHY_DTPR4_RESERVED_7_5_SHIFT - | 0x00000008U << DDR_PHY_DTPR4_TXP_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DTPR4_OFFSET ,0xFFFFFFFFU ,0x01162B08U); - /*############################################################################################################################ */ + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR4_RESERVED_27_26 0x0 - /*Register : DTPR5 @ 0XFD080124

+ * Refresh-to-Refresh + * PSU_DDR_PHY_DTPR4_TRFC 0x116 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR5_RESERVED_31_24 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR4_RESERVED_15_14 0x0 - Activate to activate command delay (same bank) - PSU_DDR_PHY_DTPR5_TRC 0x32 + * Write leveling output delay + * PSU_DDR_PHY_DTPR4_TWLO 0x2b - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR5_RESERVED_15 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR4_RESERVED_7_5 0x0 - Activate to read or write delay - PSU_DDR_PHY_DTPR5_TRCD 0xf + * Power down exit delay + * PSU_DDR_PHY_DTPR4_TXP 0x7 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR5_RESERVED_7_5 0x0 + * DRAM Timing Parameters Register 4 + * (OFFSET, MASK, VALUE) (0XFD080120, 0xFFFFFFFFU ,0x01162B07U) + */ + PSU_Mask_Write(DDR_PHY_DTPR4_OFFSET, 0xFFFFFFFFU, 0x01162B07U); +/*##################################################################### */ - Internal write to read command delay - PSU_DDR_PHY_DTPR5_TWTR 0x9 + /* + * Register : DTPR5 @ 0XFD080124 - DRAM Timing Parameters Register 5 - (OFFSET, MASK, VALUE) (0XFD080124, 0xFFFFFFFFU ,0x00320F09U) - RegMask = (DDR_PHY_DTPR5_RESERVED_31_24_MASK | DDR_PHY_DTPR5_TRC_MASK | DDR_PHY_DTPR5_RESERVED_15_MASK | DDR_PHY_DTPR5_TRCD_MASK | DDR_PHY_DTPR5_RESERVED_7_5_MASK | DDR_PHY_DTPR5_TWTR_MASK | 0 ); + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR5_RESERVED_31_24 0x0 - RegVal = ((0x00000000U << DDR_PHY_DTPR5_RESERVED_31_24_SHIFT - | 0x00000032U << DDR_PHY_DTPR5_TRC_SHIFT - | 0x00000000U << DDR_PHY_DTPR5_RESERVED_15_SHIFT - | 0x0000000FU << DDR_PHY_DTPR5_TRCD_SHIFT - | 0x00000000U << DDR_PHY_DTPR5_RESERVED_7_5_SHIFT - | 0x00000009U << DDR_PHY_DTPR5_TWTR_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DTPR5_OFFSET ,0xFFFFFFFFU ,0x00320F09U); - /*############################################################################################################################ */ + * Activate to activate command delay (same bank) + * PSU_DDR_PHY_DTPR5_TRC 0x33 - /*Register : DTPR6 @ 0XFD080128

+ * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR5_RESERVED_15 0x0 - PUB Write Latency Enable - PSU_DDR_PHY_DTPR6_PUBWLEN 0x0 + * Activate to read or write delay + * PSU_DDR_PHY_DTPR5_TRCD 0xf - PUB Read Latency Enable - PSU_DDR_PHY_DTPR6_PUBRLEN 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR5_RESERVED_7_5 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR6_RESERVED_29_14 0x0 + * Internal write to read command delay + * PSU_DDR_PHY_DTPR5_TWTR 0x8 - Write Latency - PSU_DDR_PHY_DTPR6_PUBWL 0xe + * DRAM Timing Parameters Register 5 + * (OFFSET, MASK, VALUE) (0XFD080124, 0xFFFFFFFFU ,0x00330F08U) + */ + PSU_Mask_Write(DDR_PHY_DTPR5_OFFSET, 0xFFFFFFFFU, 0x00330F08U); +/*##################################################################### */ - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR6_RESERVED_7_6 0x0 + /* + * Register : DTPR6 @ 0XFD080128 - Read Latency - PSU_DDR_PHY_DTPR6_PUBRL 0xf + * PUB Write Latency Enable + * PSU_DDR_PHY_DTPR6_PUBWLEN 0x0 - DRAM Timing Parameters Register 6 - (OFFSET, MASK, VALUE) (0XFD080128, 0xFFFFFFFFU ,0x00000E0FU) - RegMask = (DDR_PHY_DTPR6_PUBWLEN_MASK | DDR_PHY_DTPR6_PUBRLEN_MASK | DDR_PHY_DTPR6_RESERVED_29_14_MASK | DDR_PHY_DTPR6_PUBWL_MASK | DDR_PHY_DTPR6_RESERVED_7_6_MASK | DDR_PHY_DTPR6_PUBRL_MASK | 0 ); + * PUB Read Latency Enable + * PSU_DDR_PHY_DTPR6_PUBRLEN 0x0 - RegVal = ((0x00000000U << DDR_PHY_DTPR6_PUBWLEN_SHIFT - | 0x00000000U << DDR_PHY_DTPR6_PUBRLEN_SHIFT - | 0x00000000U << DDR_PHY_DTPR6_RESERVED_29_14_SHIFT - | 0x0000000EU << DDR_PHY_DTPR6_PUBWL_SHIFT - | 0x00000000U << DDR_PHY_DTPR6_RESERVED_7_6_SHIFT - | 0x0000000FU << DDR_PHY_DTPR6_PUBRL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DTPR6_OFFSET ,0xFFFFFFFFU ,0x00000E0FU); - /*############################################################################################################################ */ + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR6_RESERVED_29_14 0x0 - /*Register : RDIMMGCR0 @ 0XFD080140

+ * Write Latency + * PSU_DDR_PHY_DTPR6_PUBWL 0xe - Reserved. Return zeroes on reads. - PSU_DDR_PHY_RDIMMGCR0_RESERVED_31 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR6_RESERVED_7_6 0x0 - RDMIMM Quad CS Enable - PSU_DDR_PHY_RDIMMGCR0_QCSEN 0x0 + * Read Latency + * PSU_DDR_PHY_DTPR6_PUBRL 0xf - Reserved. Return zeroes on reads. - PSU_DDR_PHY_RDIMMGCR0_RESERVED_29_28 0x0 + * DRAM Timing Parameters Register 6 + * (OFFSET, MASK, VALUE) (0XFD080128, 0xFFFFFFFFU ,0x00000E0FU) + */ + PSU_Mask_Write(DDR_PHY_DTPR6_OFFSET, 0xFFFFFFFFU, 0x00000E0FU); +/*##################################################################### */ - RDIMM Outputs I/O Mode - PSU_DDR_PHY_RDIMMGCR0_RDIMMIOM 0x1 + /* + * Register : RDIMMGCR0 @ 0XFD080140 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_RDIMMGCR0_RESERVED_26_24 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_RDIMMGCR0_RESERVED_31 0x0 - ERROUT# Output Enable - PSU_DDR_PHY_RDIMMGCR0_ERROUTOE 0x0 + * RDMIMM Quad CS Enable + * PSU_DDR_PHY_RDIMMGCR0_QCSEN 0x0 - ERROUT# I/O Mode - PSU_DDR_PHY_RDIMMGCR0_ERROUTIOM 0x1 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_RDIMMGCR0_RESERVED_29_28 0x0 - ERROUT# Power Down Receiver - PSU_DDR_PHY_RDIMMGCR0_ERROUTPDR 0x0 + * RDIMM Outputs I/O Mode + * PSU_DDR_PHY_RDIMMGCR0_RDIMMIOM 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_RDIMMGCR0_RESERVED_20 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_RDIMMGCR0_RESERVED_26_24 0x0 - ERROUT# On-Die Termination - PSU_DDR_PHY_RDIMMGCR0_ERROUTODT 0x0 + * ERROUT# Output Enable + * PSU_DDR_PHY_RDIMMGCR0_ERROUTOE 0x0 - Load Reduced DIMM - PSU_DDR_PHY_RDIMMGCR0_LRDIMM 0x0 + * ERROUT# I/O Mode + * PSU_DDR_PHY_RDIMMGCR0_ERROUTIOM 0x1 - PAR_IN I/O Mode - PSU_DDR_PHY_RDIMMGCR0_PARINIOM 0x0 + * ERROUT# Power Down Receiver + * PSU_DDR_PHY_RDIMMGCR0_ERROUTPDR 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_RDIMMGCR0_RESERVED_16_8 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_RDIMMGCR0_RESERVED_20 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD 0x0 + * ERROUT# On-Die Termination + * PSU_DDR_PHY_RDIMMGCR0_ERROUTODT 0x0 - Rank Mirror Enable. - PSU_DDR_PHY_RDIMMGCR0_RNKMRREN 0x2 + * Load Reduced DIMM + * PSU_DDR_PHY_RDIMMGCR0_LRDIMM 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_RDIMMGCR0_RESERVED_3 0x0 + * PAR_IN I/O Mode + * PSU_DDR_PHY_RDIMMGCR0_PARINIOM 0x0 - Stop on Parity Error - PSU_DDR_PHY_RDIMMGCR0_SOPERR 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_RDIMMGCR0_RESERVED_16_8 0x0 - Parity Error No Registering - PSU_DDR_PHY_RDIMMGCR0_ERRNOREG 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD 0x0 - Registered DIMM - PSU_DDR_PHY_RDIMMGCR0_RDIMM 0x0 + * Rank Mirror Enable. + * PSU_DDR_PHY_RDIMMGCR0_RNKMRREN 0x2 - RDIMM General Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD080140, 0xFFFFFFFFU ,0x08400020U) - RegMask = (DDR_PHY_RDIMMGCR0_RESERVED_31_MASK | DDR_PHY_RDIMMGCR0_QCSEN_MASK | DDR_PHY_RDIMMGCR0_RESERVED_29_28_MASK | DDR_PHY_RDIMMGCR0_RDIMMIOM_MASK | DDR_PHY_RDIMMGCR0_RESERVED_26_24_MASK | DDR_PHY_RDIMMGCR0_ERROUTOE_MASK | DDR_PHY_RDIMMGCR0_ERROUTIOM_MASK | DDR_PHY_RDIMMGCR0_ERROUTPDR_MASK | DDR_PHY_RDIMMGCR0_RESERVED_20_MASK | DDR_PHY_RDIMMGCR0_ERROUTODT_MASK | DDR_PHY_RDIMMGCR0_LRDIMM_MASK | DDR_PHY_RDIMMGCR0_PARINIOM_MASK | DDR_PHY_RDIMMGCR0_RESERVED_16_8_MASK | DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_MASK | DDR_PHY_RDIMMGCR0_RNKMRREN_MASK | DDR_PHY_RDIMMGCR0_RESERVED_3_MASK | DDR_PHY_RDIMMGCR0_SOPERR_MASK | DDR_PHY_RDIMMGCR0_ERRNOREG_MASK | DDR_PHY_RDIMMGCR0_RDIMM_MASK | 0 ); + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_RDIMMGCR0_RESERVED_3 0x0 - RegVal = ((0x00000000U << DDR_PHY_RDIMMGCR0_RESERVED_31_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR0_QCSEN_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR0_RESERVED_29_28_SHIFT - | 0x00000001U << DDR_PHY_RDIMMGCR0_RDIMMIOM_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR0_RESERVED_26_24_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR0_ERROUTOE_SHIFT - | 0x00000001U << DDR_PHY_RDIMMGCR0_ERROUTIOM_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR0_ERROUTPDR_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR0_RESERVED_20_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR0_ERROUTODT_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR0_LRDIMM_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR0_PARINIOM_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR0_RESERVED_16_8_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_SHIFT - | 0x00000002U << DDR_PHY_RDIMMGCR0_RNKMRREN_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR0_RESERVED_3_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR0_SOPERR_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR0_ERRNOREG_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR0_RDIMM_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_RDIMMGCR0_OFFSET ,0xFFFFFFFFU ,0x08400020U); - /*############################################################################################################################ */ + * Stop on Parity Error + * PSU_DDR_PHY_RDIMMGCR0_SOPERR 0x0 - /*Register : RDIMMGCR1 @ 0XFD080144

+ * Parity Error No Registering + * PSU_DDR_PHY_RDIMMGCR0_ERRNOREG 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_RDIMMGCR1_RESERVED_31_29 0x0 + * Registered DIMM + * PSU_DDR_PHY_RDIMMGCR0_RDIMM 0x0 - Address [17] B-side Inversion Disable - PSU_DDR_PHY_RDIMMGCR1_A17BID 0x0 + * RDIMM General Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD080140, 0xFFFFFFFFU ,0x08400020U) + */ + PSU_Mask_Write(DDR_PHY_RDIMMGCR0_OFFSET, 0xFFFFFFFFU, 0x08400020U); +/*##################################################################### */ - Reserved. Return zeroes on reads. - PSU_DDR_PHY_RDIMMGCR1_RESERVED_27 0x0 + /* + * Register : RDIMMGCR1 @ 0XFD080144 - Command word to command word programming delay - PSU_DDR_PHY_RDIMMGCR1_TBCMRD_L2 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_RDIMMGCR1_RESERVED_31_29 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_RDIMMGCR1_RESERVED_23 0x0 + * Address [17] B-side Inversion Disable + * PSU_DDR_PHY_RDIMMGCR1_A17BID 0x0 - Command word to command word programming delay - PSU_DDR_PHY_RDIMMGCR1_TBCMRD_L 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_RDIMMGCR1_RESERVED_27 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_RDIMMGCR1_RESERVED_19 0x0 + * Command word to command word programming delay + * PSU_DDR_PHY_RDIMMGCR1_TBCMRD_L2 0x0 - Command word to command word programming delay - PSU_DDR_PHY_RDIMMGCR1_TBCMRD 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_RDIMMGCR1_RESERVED_23 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_RDIMMGCR1_RESERVED_15_14 0x0 + * Command word to command word programming delay + * PSU_DDR_PHY_RDIMMGCR1_TBCMRD_L 0x0 - Stabilization time - PSU_DDR_PHY_RDIMMGCR1_TBCSTAB 0xc80 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_RDIMMGCR1_RESERVED_19 0x0 - RDIMM General Configuration Register 1 - (OFFSET, MASK, VALUE) (0XFD080144, 0xFFFFFFFFU ,0x00000C80U) - RegMask = (DDR_PHY_RDIMMGCR1_RESERVED_31_29_MASK | DDR_PHY_RDIMMGCR1_A17BID_MASK | DDR_PHY_RDIMMGCR1_RESERVED_27_MASK | DDR_PHY_RDIMMGCR1_TBCMRD_L2_MASK | DDR_PHY_RDIMMGCR1_RESERVED_23_MASK | DDR_PHY_RDIMMGCR1_TBCMRD_L_MASK | DDR_PHY_RDIMMGCR1_RESERVED_19_MASK | DDR_PHY_RDIMMGCR1_TBCMRD_MASK | DDR_PHY_RDIMMGCR1_RESERVED_15_14_MASK | DDR_PHY_RDIMMGCR1_TBCSTAB_MASK | 0 ); - - RegVal = ((0x00000000U << DDR_PHY_RDIMMGCR1_RESERVED_31_29_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR1_A17BID_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR1_RESERVED_27_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR1_TBCMRD_L2_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR1_RESERVED_23_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR1_TBCMRD_L_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR1_RESERVED_19_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR1_TBCMRD_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR1_RESERVED_15_14_SHIFT - | 0x00000C80U << DDR_PHY_RDIMMGCR1_TBCSTAB_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_RDIMMGCR1_OFFSET ,0xFFFFFFFFU ,0x00000C80U); - /*############################################################################################################################ */ - - /*Register : RDIMMCR0 @ 0XFD080150

+ * Command word to command word programming delay + * PSU_DDR_PHY_RDIMMGCR1_TBCMRD 0x0 - DDR4/DDR3 Control Word 7 - PSU_DDR_PHY_RDIMMCR0_RC7 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_RDIMMGCR1_RESERVED_15_14 0x0 - DDR4 Control Word 6 (Comman space Control Word) / DDR3 Reserved - PSU_DDR_PHY_RDIMMCR0_RC6 0x0 - - DDR4/DDR3 Control Word 5 (CK Driver Characteristics Control Word) - PSU_DDR_PHY_RDIMMCR0_RC5 0x0 - - DDR4 Control Word 4 (ODT and CKE Signals Driver Characteristics Control Word) / DDR3 Control Word 4 (Control Signals Driver C - aracteristics Control Word) - PSU_DDR_PHY_RDIMMCR0_RC4 0x0 - - DDR4 Control Word 3 (CA and CS Signals Driver Characteristics Control Word) / DDR3 Control Word 3 (Command/Address Signals Dr - ver Characteristrics Control Word) - PSU_DDR_PHY_RDIMMCR0_RC3 0x0 - - DDR4 Control Word 2 (Timing and IBT Control Word) / DDR3 Control Word 2 (Timing Control Word) - PSU_DDR_PHY_RDIMMCR0_RC2 0x0 - - DDR4/DDR3 Control Word 1 (Clock Driver Enable Control Word) - PSU_DDR_PHY_RDIMMCR0_RC1 0x0 - - DDR4/DDR3 Control Word 0 (Global Features Control Word) - PSU_DDR_PHY_RDIMMCR0_RC0 0x0 - - RDIMM Control Register 0 - (OFFSET, MASK, VALUE) (0XFD080150, 0xFFFFFFFFU ,0x00000000U) - RegMask = (DDR_PHY_RDIMMCR0_RC7_MASK | DDR_PHY_RDIMMCR0_RC6_MASK | DDR_PHY_RDIMMCR0_RC5_MASK | DDR_PHY_RDIMMCR0_RC4_MASK | DDR_PHY_RDIMMCR0_RC3_MASK | DDR_PHY_RDIMMCR0_RC2_MASK | DDR_PHY_RDIMMCR0_RC1_MASK | DDR_PHY_RDIMMCR0_RC0_MASK | 0 ); - - RegVal = ((0x00000000U << DDR_PHY_RDIMMCR0_RC7_SHIFT - | 0x00000000U << DDR_PHY_RDIMMCR0_RC6_SHIFT - | 0x00000000U << DDR_PHY_RDIMMCR0_RC5_SHIFT - | 0x00000000U << DDR_PHY_RDIMMCR0_RC4_SHIFT - | 0x00000000U << DDR_PHY_RDIMMCR0_RC3_SHIFT - | 0x00000000U << DDR_PHY_RDIMMCR0_RC2_SHIFT - | 0x00000000U << DDR_PHY_RDIMMCR0_RC1_SHIFT - | 0x00000000U << DDR_PHY_RDIMMCR0_RC0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_RDIMMCR0_OFFSET ,0xFFFFFFFFU ,0x00000000U); - /*############################################################################################################################ */ + * Stabilization time + * PSU_DDR_PHY_RDIMMGCR1_TBCSTAB 0xc80 - /*Register : RDIMMCR1 @ 0XFD080154

+ * RDIMM General Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD080144, 0xFFFFFFFFU ,0x00000C80U) + */ + PSU_Mask_Write(DDR_PHY_RDIMMGCR1_OFFSET, 0xFFFFFFFFU, 0x00000C80U); +/*##################################################################### */ - Control Word 15 - PSU_DDR_PHY_RDIMMCR1_RC15 0x0 + /* + * Register : RDIMMCR0 @ 0XFD080150 - DDR4 Control Word 14 (Parity Control Word) / DDR3 Reserved - PSU_DDR_PHY_RDIMMCR1_RC14 0x0 + * DDR4/DDR3 Control Word 7 + * PSU_DDR_PHY_RDIMMCR0_RC7 0x0 - DDR4 Control Word 13 (DIMM Configuration Control Word) / DDR3 Reserved - PSU_DDR_PHY_RDIMMCR1_RC13 0x0 + * DDR4 Control Word 6 (Comman space Control Word) / DDR3 Reserved + * PSU_DDR_PHY_RDIMMCR0_RC6 0x0 - DDR4 Control Word 12 (Training Control Word) / DDR3 Reserved - PSU_DDR_PHY_RDIMMCR1_RC12 0x0 + * DDR4/DDR3 Control Word 5 (CK Driver Characteristics Control Word) + * PSU_DDR_PHY_RDIMMCR0_RC5 0x0 - DDR4 Control Word 11 (Operating Voltage VDD and VREFCA Source Control Word) / DDR3 Control Word 11 (Operation Voltage VDD Con - rol Word) - PSU_DDR_PHY_RDIMMCR1_RC11 0x0 + * DDR4 Control Word 4 (ODT and CKE Signals Driver Characteristics Control + * Word) / DDR3 Control Word 4 (Control Signals Driver Characteristics Cont + * rol Word) + * PSU_DDR_PHY_RDIMMCR0_RC4 0x0 - DDR4/DDR3 Control Word 10 (RDIMM Operating Speed Control Word) - PSU_DDR_PHY_RDIMMCR1_RC10 0x2 + * DDR4 Control Word 3 (CA and CS Signals Driver Characteristics Control Wo + * rd) / DDR3 Control Word 3 (Command/Address Signals Driver Characteristri + * cs Control Word) + * PSU_DDR_PHY_RDIMMCR0_RC3 0x0 - DDR4/DDR3 Control Word 9 (Power Saving Settings Control Word) - PSU_DDR_PHY_RDIMMCR1_RC9 0x0 + * DDR4 Control Word 2 (Timing and IBT Control Word) / DDR3 Control Word 2 + * (Timing Control Word) + * PSU_DDR_PHY_RDIMMCR0_RC2 0x0 - DDR4 Control Word 8 (Input/Output Configuration Control Word) / DDR3 Control Word 8 (Additional Input Bus Termination Setting - Control Word) - PSU_DDR_PHY_RDIMMCR1_RC8 0x0 + * DDR4/DDR3 Control Word 1 (Clock Driver Enable Control Word) + * PSU_DDR_PHY_RDIMMCR0_RC1 0x0 - RDIMM Control Register 1 - (OFFSET, MASK, VALUE) (0XFD080154, 0xFFFFFFFFU ,0x00000200U) - RegMask = (DDR_PHY_RDIMMCR1_RC15_MASK | DDR_PHY_RDIMMCR1_RC14_MASK | DDR_PHY_RDIMMCR1_RC13_MASK | DDR_PHY_RDIMMCR1_RC12_MASK | DDR_PHY_RDIMMCR1_RC11_MASK | DDR_PHY_RDIMMCR1_RC10_MASK | DDR_PHY_RDIMMCR1_RC9_MASK | DDR_PHY_RDIMMCR1_RC8_MASK | 0 ); + * DDR4/DDR3 Control Word 0 (Global Features Control Word) + * PSU_DDR_PHY_RDIMMCR0_RC0 0x0 - RegVal = ((0x00000000U << DDR_PHY_RDIMMCR1_RC15_SHIFT - | 0x00000000U << DDR_PHY_RDIMMCR1_RC14_SHIFT - | 0x00000000U << DDR_PHY_RDIMMCR1_RC13_SHIFT - | 0x00000000U << DDR_PHY_RDIMMCR1_RC12_SHIFT - | 0x00000000U << DDR_PHY_RDIMMCR1_RC11_SHIFT - | 0x00000002U << DDR_PHY_RDIMMCR1_RC10_SHIFT - | 0x00000000U << DDR_PHY_RDIMMCR1_RC9_SHIFT - | 0x00000000U << DDR_PHY_RDIMMCR1_RC8_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_RDIMMCR1_OFFSET ,0xFFFFFFFFU ,0x00000200U); - /*############################################################################################################################ */ + * RDIMM Control Register 0 + * (OFFSET, MASK, VALUE) (0XFD080150, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDR_PHY_RDIMMCR0_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ - /*Register : MR0 @ 0XFD080180

+ /* + * Register : RDIMMCR1 @ 0XFD080154 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_MR0_RESERVED_31_8 0x8 + * Control Word 15 + * PSU_DDR_PHY_RDIMMCR1_RC15 0x0 - CA Terminating Rank - PSU_DDR_PHY_MR0_CATR 0x0 + * DDR4 Control Word 14 (Parity Control Word) / DDR3 Reserved + * PSU_DDR_PHY_RDIMMCR1_RC14 0x0 - Reserved. These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0. - PSU_DDR_PHY_MR0_RSVD_6_5 0x1 + * DDR4 Control Word 13 (DIMM Configuration Control Word) / DDR3 Reserved + * PSU_DDR_PHY_RDIMMCR1_RC13 0x0 - Built-in Self-Test for RZQ - PSU_DDR_PHY_MR0_RZQI 0x2 + * DDR4 Control Word 12 (Training Control Word) / DDR3 Reserved + * PSU_DDR_PHY_RDIMMCR1_RC12 0x0 - Reserved. These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0. - PSU_DDR_PHY_MR0_RSVD_2_0 0x0 + * DDR4 Control Word 11 (Operating Voltage VDD and VREFCA Source Control Wo + * rd) / DDR3 Control Word 11 (Operation Voltage VDD Control Word) + * PSU_DDR_PHY_RDIMMCR1_RC11 0x0 - LPDDR4 Mode Register 0 - (OFFSET, MASK, VALUE) (0XFD080180, 0xFFFFFFFFU ,0x00000830U) - RegMask = (DDR_PHY_MR0_RESERVED_31_8_MASK | DDR_PHY_MR0_CATR_MASK | DDR_PHY_MR0_RSVD_6_5_MASK | DDR_PHY_MR0_RZQI_MASK | DDR_PHY_MR0_RSVD_2_0_MASK | 0 ); + * DDR4/DDR3 Control Word 10 (RDIMM Operating Speed Control Word) + * PSU_DDR_PHY_RDIMMCR1_RC10 0x2 - RegVal = ((0x00000008U << DDR_PHY_MR0_RESERVED_31_8_SHIFT - | 0x00000000U << DDR_PHY_MR0_CATR_SHIFT - | 0x00000001U << DDR_PHY_MR0_RSVD_6_5_SHIFT - | 0x00000002U << DDR_PHY_MR0_RZQI_SHIFT - | 0x00000000U << DDR_PHY_MR0_RSVD_2_0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_MR0_OFFSET ,0xFFFFFFFFU ,0x00000830U); - /*############################################################################################################################ */ + * DDR4/DDR3 Control Word 9 (Power Saving Settings Control Word) + * PSU_DDR_PHY_RDIMMCR1_RC9 0x0 - /*Register : MR1 @ 0XFD080184

+ * DDR4 Control Word 8 (Input/Output Configuration Control Word) / DDR3 Con + * trol Word 8 (Additional Input Bus Termination Setting Control Word) + * PSU_DDR_PHY_RDIMMCR1_RC8 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_MR1_RESERVED_31_8 0x3 + * RDIMM Control Register 1 + * (OFFSET, MASK, VALUE) (0XFD080154, 0xFFFFFFFFU ,0x00000200U) + */ + PSU_Mask_Write(DDR_PHY_RDIMMCR1_OFFSET, 0xFFFFFFFFU, 0x00000200U); +/*##################################################################### */ - Read Postamble Length - PSU_DDR_PHY_MR1_RDPST 0x0 + /* + * Register : MR0 @ 0XFD080180 - Write-recovery for auto-precharge command - PSU_DDR_PHY_MR1_NWR 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_MR0_RESERVED_31_8 0x6 - Read Preamble Length - PSU_DDR_PHY_MR1_RDPRE 0x0 + * CA Terminating Rank + * PSU_DDR_PHY_MR0_CATR 0x0 - Write Preamble Length - PSU_DDR_PHY_MR1_WRPRE 0x0 + * Reserved. These are JEDEC reserved bits and are recommended by JEDEC to + * be programmed to 0x0. + * PSU_DDR_PHY_MR0_RSVD_6_5 0x1 - Burst Length - PSU_DDR_PHY_MR1_BL 0x1 + * Built-in Self-Test for RZQ + * PSU_DDR_PHY_MR0_RZQI 0x2 - LPDDR4 Mode Register 1 - (OFFSET, MASK, VALUE) (0XFD080184, 0xFFFFFFFFU ,0x00000301U) - RegMask = (DDR_PHY_MR1_RESERVED_31_8_MASK | DDR_PHY_MR1_RDPST_MASK | DDR_PHY_MR1_NWR_MASK | DDR_PHY_MR1_RDPRE_MASK | DDR_PHY_MR1_WRPRE_MASK | DDR_PHY_MR1_BL_MASK | 0 ); + * Reserved. These are JEDEC reserved bits and are recommended by JEDEC to + * be programmed to 0x0. + * PSU_DDR_PHY_MR0_RSVD_2_0 0x0 - RegVal = ((0x00000003U << DDR_PHY_MR1_RESERVED_31_8_SHIFT - | 0x00000000U << DDR_PHY_MR1_RDPST_SHIFT - | 0x00000000U << DDR_PHY_MR1_NWR_SHIFT - | 0x00000000U << DDR_PHY_MR1_RDPRE_SHIFT - | 0x00000000U << DDR_PHY_MR1_WRPRE_SHIFT - | 0x00000001U << DDR_PHY_MR1_BL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_MR1_OFFSET ,0xFFFFFFFFU ,0x00000301U); - /*############################################################################################################################ */ + * LPDDR4 Mode Register 0 + * (OFFSET, MASK, VALUE) (0XFD080180, 0xFFFFFFFFU ,0x00000630U) + */ + PSU_Mask_Write(DDR_PHY_MR0_OFFSET, 0xFFFFFFFFU, 0x00000630U); +/*##################################################################### */ - /*Register : MR2 @ 0XFD080188

+ /* + * Register : MR1 @ 0XFD080184 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_MR2_RESERVED_31_8 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_MR1_RESERVED_31_8 0x3 - Write Leveling - PSU_DDR_PHY_MR2_WRL 0x0 + * Read Postamble Length + * PSU_DDR_PHY_MR1_RDPST 0x0 - Write Latency Set - PSU_DDR_PHY_MR2_WLS 0x0 + * Write-recovery for auto-precharge command + * PSU_DDR_PHY_MR1_NWR 0x0 - Write Latency - PSU_DDR_PHY_MR2_WL 0x4 + * Read Preamble Length + * PSU_DDR_PHY_MR1_RDPRE 0x0 - Read Latency - PSU_DDR_PHY_MR2_RL 0x0 + * Write Preamble Length + * PSU_DDR_PHY_MR1_WRPRE 0x0 - LPDDR4 Mode Register 2 - (OFFSET, MASK, VALUE) (0XFD080188, 0xFFFFFFFFU ,0x00000020U) - RegMask = (DDR_PHY_MR2_RESERVED_31_8_MASK | DDR_PHY_MR2_WRL_MASK | DDR_PHY_MR2_WLS_MASK | DDR_PHY_MR2_WL_MASK | DDR_PHY_MR2_RL_MASK | 0 ); + * Burst Length + * PSU_DDR_PHY_MR1_BL 0x1 - RegVal = ((0x00000000U << DDR_PHY_MR2_RESERVED_31_8_SHIFT - | 0x00000000U << DDR_PHY_MR2_WRL_SHIFT - | 0x00000000U << DDR_PHY_MR2_WLS_SHIFT - | 0x00000004U << DDR_PHY_MR2_WL_SHIFT - | 0x00000000U << DDR_PHY_MR2_RL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_MR2_OFFSET ,0xFFFFFFFFU ,0x00000020U); - /*############################################################################################################################ */ + * LPDDR4 Mode Register 1 + * (OFFSET, MASK, VALUE) (0XFD080184, 0xFFFFFFFFU ,0x00000301U) + */ + PSU_Mask_Write(DDR_PHY_MR1_OFFSET, 0xFFFFFFFFU, 0x00000301U); +/*##################################################################### */ - /*Register : MR3 @ 0XFD08018C

+ /* + * Register : MR2 @ 0XFD080188 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_MR3_RESERVED_31_8 0x2 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_MR2_RESERVED_31_8 0x0 - DBI-Write Enable - PSU_DDR_PHY_MR3_DBIWR 0x0 + * Write Leveling + * PSU_DDR_PHY_MR2_WRL 0x0 - DBI-Read Enable - PSU_DDR_PHY_MR3_DBIRD 0x0 + * Write Latency Set + * PSU_DDR_PHY_MR2_WLS 0x0 - Pull-down Drive Strength - PSU_DDR_PHY_MR3_PDDS 0x0 + * Write Latency + * PSU_DDR_PHY_MR2_WL 0x4 - These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0. - PSU_DDR_PHY_MR3_RSVD 0x0 + * Read Latency + * PSU_DDR_PHY_MR2_RL 0x0 - Write Postamble Length - PSU_DDR_PHY_MR3_WRPST 0x0 + * LPDDR4 Mode Register 2 + * (OFFSET, MASK, VALUE) (0XFD080188, 0xFFFFFFFFU ,0x00000020U) + */ + PSU_Mask_Write(DDR_PHY_MR2_OFFSET, 0xFFFFFFFFU, 0x00000020U); +/*##################################################################### */ - Pull-up Calibration Point - PSU_DDR_PHY_MR3_PUCAL 0x0 + /* + * Register : MR3 @ 0XFD08018C - LPDDR4 Mode Register 3 - (OFFSET, MASK, VALUE) (0XFD08018C, 0xFFFFFFFFU ,0x00000200U) - RegMask = (DDR_PHY_MR3_RESERVED_31_8_MASK | DDR_PHY_MR3_DBIWR_MASK | DDR_PHY_MR3_DBIRD_MASK | DDR_PHY_MR3_PDDS_MASK | DDR_PHY_MR3_RSVD_MASK | DDR_PHY_MR3_WRPST_MASK | DDR_PHY_MR3_PUCAL_MASK | 0 ); + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_MR3_RESERVED_31_8 0x2 - RegVal = ((0x00000002U << DDR_PHY_MR3_RESERVED_31_8_SHIFT - | 0x00000000U << DDR_PHY_MR3_DBIWR_SHIFT - | 0x00000000U << DDR_PHY_MR3_DBIRD_SHIFT - | 0x00000000U << DDR_PHY_MR3_PDDS_SHIFT - | 0x00000000U << DDR_PHY_MR3_RSVD_SHIFT - | 0x00000000U << DDR_PHY_MR3_WRPST_SHIFT - | 0x00000000U << DDR_PHY_MR3_PUCAL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_MR3_OFFSET ,0xFFFFFFFFU ,0x00000200U); - /*############################################################################################################################ */ + * DBI-Write Enable + * PSU_DDR_PHY_MR3_DBIWR 0x0 - /*Register : MR4 @ 0XFD080190

+ * DBI-Read Enable + * PSU_DDR_PHY_MR3_DBIRD 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_MR4_RESERVED_31_16 0x0 + * Pull-down Drive Strength + * PSU_DDR_PHY_MR3_PDDS 0x0 - These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0. - PSU_DDR_PHY_MR4_RSVD_15_13 0x0 + * These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. + * PSU_DDR_PHY_MR3_RSVD 0x0 - Write Preamble - PSU_DDR_PHY_MR4_WRP 0x0 + * Write Postamble Length + * PSU_DDR_PHY_MR3_WRPST 0x0 - Read Preamble - PSU_DDR_PHY_MR4_RDP 0x0 + * Pull-up Calibration Point + * PSU_DDR_PHY_MR3_PUCAL 0x0 - Read Preamble Training Mode - PSU_DDR_PHY_MR4_RPTM 0x0 + * LPDDR4 Mode Register 3 + * (OFFSET, MASK, VALUE) (0XFD08018C, 0xFFFFFFFFU ,0x00000200U) + */ + PSU_Mask_Write(DDR_PHY_MR3_OFFSET, 0xFFFFFFFFU, 0x00000200U); +/*##################################################################### */ - Self Refresh Abort - PSU_DDR_PHY_MR4_SRA 0x0 + /* + * Register : MR4 @ 0XFD080190 - CS to Command Latency Mode - PSU_DDR_PHY_MR4_CS2CMDL 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_MR4_RESERVED_31_16 0x0 - These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0. - PSU_DDR_PHY_MR4_RSVD1 0x0 + * These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. + * PSU_DDR_PHY_MR4_RSVD_15_13 0x0 - Internal VREF Monitor - PSU_DDR_PHY_MR4_IVM 0x0 + * Write Preamble + * PSU_DDR_PHY_MR4_WRP 0x0 - Temperature Controlled Refresh Mode - PSU_DDR_PHY_MR4_TCRM 0x0 + * Read Preamble + * PSU_DDR_PHY_MR4_RDP 0x0 - Temperature Controlled Refresh Range - PSU_DDR_PHY_MR4_TCRR 0x0 + * Read Preamble Training Mode + * PSU_DDR_PHY_MR4_RPTM 0x0 - Maximum Power Down Mode - PSU_DDR_PHY_MR4_MPDM 0x0 + * Self Refresh Abort + * PSU_DDR_PHY_MR4_SRA 0x0 - This is a JEDEC reserved bit and is recommended by JEDEC to be programmed to 0x0. - PSU_DDR_PHY_MR4_RSVD_0 0x0 + * CS to Command Latency Mode + * PSU_DDR_PHY_MR4_CS2CMDL 0x0 - DDR4 Mode Register 4 - (OFFSET, MASK, VALUE) (0XFD080190, 0xFFFFFFFFU ,0x00000000U) - RegMask = (DDR_PHY_MR4_RESERVED_31_16_MASK | DDR_PHY_MR4_RSVD_15_13_MASK | DDR_PHY_MR4_WRP_MASK | DDR_PHY_MR4_RDP_MASK | DDR_PHY_MR4_RPTM_MASK | DDR_PHY_MR4_SRA_MASK | DDR_PHY_MR4_CS2CMDL_MASK | DDR_PHY_MR4_RSVD1_MASK | DDR_PHY_MR4_IVM_MASK | DDR_PHY_MR4_TCRM_MASK | DDR_PHY_MR4_TCRR_MASK | DDR_PHY_MR4_MPDM_MASK | DDR_PHY_MR4_RSVD_0_MASK | 0 ); + * These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. + * PSU_DDR_PHY_MR4_RSVD1 0x0 - RegVal = ((0x00000000U << DDR_PHY_MR4_RESERVED_31_16_SHIFT - | 0x00000000U << DDR_PHY_MR4_RSVD_15_13_SHIFT - | 0x00000000U << DDR_PHY_MR4_WRP_SHIFT - | 0x00000000U << DDR_PHY_MR4_RDP_SHIFT - | 0x00000000U << DDR_PHY_MR4_RPTM_SHIFT - | 0x00000000U << DDR_PHY_MR4_SRA_SHIFT - | 0x00000000U << DDR_PHY_MR4_CS2CMDL_SHIFT - | 0x00000000U << DDR_PHY_MR4_RSVD1_SHIFT - | 0x00000000U << DDR_PHY_MR4_IVM_SHIFT - | 0x00000000U << DDR_PHY_MR4_TCRM_SHIFT - | 0x00000000U << DDR_PHY_MR4_TCRR_SHIFT - | 0x00000000U << DDR_PHY_MR4_MPDM_SHIFT - | 0x00000000U << DDR_PHY_MR4_RSVD_0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_MR4_OFFSET ,0xFFFFFFFFU ,0x00000000U); - /*############################################################################################################################ */ + * Internal VREF Monitor + * PSU_DDR_PHY_MR4_IVM 0x0 - /*Register : MR5 @ 0XFD080194

+ * Temperature Controlled Refresh Mode + * PSU_DDR_PHY_MR4_TCRM 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_MR5_RESERVED_31_16 0x0 + * Temperature Controlled Refresh Range + * PSU_DDR_PHY_MR4_TCRR 0x0 - These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0. - PSU_DDR_PHY_MR5_RSVD 0x0 + * Maximum Power Down Mode + * PSU_DDR_PHY_MR4_MPDM 0x0 - Read DBI - PSU_DDR_PHY_MR5_RDBI 0x0 + * This is a JEDEC reserved bit and is recommended by JEDEC to be programme + * d to 0x0. + * PSU_DDR_PHY_MR4_RSVD_0 0x0 - Write DBI - PSU_DDR_PHY_MR5_WDBI 0x0 + * DDR4 Mode Register 4 + * (OFFSET, MASK, VALUE) (0XFD080190, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDR_PHY_MR4_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ - Data Mask - PSU_DDR_PHY_MR5_DM 0x1 + /* + * Register : MR5 @ 0XFD080194 - CA Parity Persistent Error - PSU_DDR_PHY_MR5_CAPPE 0x1 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_MR5_RESERVED_31_16 0x0 - RTT_PARK - PSU_DDR_PHY_MR5_RTTPARK 0x3 + * These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. + * PSU_DDR_PHY_MR5_RSVD 0x0 - ODT Input Buffer during Power Down mode - PSU_DDR_PHY_MR5_ODTIBPD 0x0 + * Read DBI + * PSU_DDR_PHY_MR5_RDBI 0x0 - C/A Parity Error Status - PSU_DDR_PHY_MR5_CAPES 0x0 + * Write DBI + * PSU_DDR_PHY_MR5_WDBI 0x0 - CRC Error Clear - PSU_DDR_PHY_MR5_CRCEC 0x0 + * Data Mask + * PSU_DDR_PHY_MR5_DM 0x1 - C/A Parity Latency Mode - PSU_DDR_PHY_MR5_CAPM 0x0 + * CA Parity Persistent Error + * PSU_DDR_PHY_MR5_CAPPE 0x1 - DDR4 Mode Register 5 - (OFFSET, MASK, VALUE) (0XFD080194, 0xFFFFFFFFU ,0x000006C0U) - RegMask = (DDR_PHY_MR5_RESERVED_31_16_MASK | DDR_PHY_MR5_RSVD_MASK | DDR_PHY_MR5_RDBI_MASK | DDR_PHY_MR5_WDBI_MASK | DDR_PHY_MR5_DM_MASK | DDR_PHY_MR5_CAPPE_MASK | DDR_PHY_MR5_RTTPARK_MASK | DDR_PHY_MR5_ODTIBPD_MASK | DDR_PHY_MR5_CAPES_MASK | DDR_PHY_MR5_CRCEC_MASK | DDR_PHY_MR5_CAPM_MASK | 0 ); + * RTT_PARK + * PSU_DDR_PHY_MR5_RTTPARK 0x3 - RegVal = ((0x00000000U << DDR_PHY_MR5_RESERVED_31_16_SHIFT - | 0x00000000U << DDR_PHY_MR5_RSVD_SHIFT - | 0x00000000U << DDR_PHY_MR5_RDBI_SHIFT - | 0x00000000U << DDR_PHY_MR5_WDBI_SHIFT - | 0x00000001U << DDR_PHY_MR5_DM_SHIFT - | 0x00000001U << DDR_PHY_MR5_CAPPE_SHIFT - | 0x00000003U << DDR_PHY_MR5_RTTPARK_SHIFT - | 0x00000000U << DDR_PHY_MR5_ODTIBPD_SHIFT - | 0x00000000U << DDR_PHY_MR5_CAPES_SHIFT - | 0x00000000U << DDR_PHY_MR5_CRCEC_SHIFT - | 0x00000000U << DDR_PHY_MR5_CAPM_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_MR5_OFFSET ,0xFFFFFFFFU ,0x000006C0U); - /*############################################################################################################################ */ + * ODT Input Buffer during Power Down mode + * PSU_DDR_PHY_MR5_ODTIBPD 0x0 - /*Register : MR6 @ 0XFD080198

+ * C/A Parity Error Status + * PSU_DDR_PHY_MR5_CAPES 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_MR6_RESERVED_31_16 0x0 + * CRC Error Clear + * PSU_DDR_PHY_MR5_CRCEC 0x0 - These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0. - PSU_DDR_PHY_MR6_RSVD_15_13 0x0 + * C/A Parity Latency Mode + * PSU_DDR_PHY_MR5_CAPM 0x0 - CAS_n to CAS_n command delay for same bank group (tCCD_L) - PSU_DDR_PHY_MR6_TCCDL 0x2 + * DDR4 Mode Register 5 + * (OFFSET, MASK, VALUE) (0XFD080194, 0xFFFFFFFFU ,0x000006C0U) + */ + PSU_Mask_Write(DDR_PHY_MR5_OFFSET, 0xFFFFFFFFU, 0x000006C0U); +/*##################################################################### */ - These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0. - PSU_DDR_PHY_MR6_RSVD_9_8 0x0 + /* + * Register : MR6 @ 0XFD080198 - VrefDQ Training Enable - PSU_DDR_PHY_MR6_VDDQTEN 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_MR6_RESERVED_31_16 0x0 - VrefDQ Training Range - PSU_DDR_PHY_MR6_VDQTRG 0x0 + * These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. + * PSU_DDR_PHY_MR6_RSVD_15_13 0x0 - VrefDQ Training Values - PSU_DDR_PHY_MR6_VDQTVAL 0x19 + * CAS_n to CAS_n command delay for same bank group (tCCD_L) + * PSU_DDR_PHY_MR6_TCCDL 0x2 - DDR4 Mode Register 6 - (OFFSET, MASK, VALUE) (0XFD080198, 0xFFFFFFFFU ,0x00000819U) - RegMask = (DDR_PHY_MR6_RESERVED_31_16_MASK | DDR_PHY_MR6_RSVD_15_13_MASK | DDR_PHY_MR6_TCCDL_MASK | DDR_PHY_MR6_RSVD_9_8_MASK | DDR_PHY_MR6_VDDQTEN_MASK | DDR_PHY_MR6_VDQTRG_MASK | DDR_PHY_MR6_VDQTVAL_MASK | 0 ); + * These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. + * PSU_DDR_PHY_MR6_RSVD_9_8 0x0 - RegVal = ((0x00000000U << DDR_PHY_MR6_RESERVED_31_16_SHIFT - | 0x00000000U << DDR_PHY_MR6_RSVD_15_13_SHIFT - | 0x00000002U << DDR_PHY_MR6_TCCDL_SHIFT - | 0x00000000U << DDR_PHY_MR6_RSVD_9_8_SHIFT - | 0x00000000U << DDR_PHY_MR6_VDDQTEN_SHIFT - | 0x00000000U << DDR_PHY_MR6_VDQTRG_SHIFT - | 0x00000019U << DDR_PHY_MR6_VDQTVAL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_MR6_OFFSET ,0xFFFFFFFFU ,0x00000819U); - /*############################################################################################################################ */ + * VrefDQ Training Enable + * PSU_DDR_PHY_MR6_VDDQTEN 0x0 - /*Register : MR11 @ 0XFD0801AC

+ * VrefDQ Training Range + * PSU_DDR_PHY_MR6_VDQTRG 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_MR11_RESERVED_31_8 0x0 + * VrefDQ Training Values + * PSU_DDR_PHY_MR6_VDQTVAL 0x19 - These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0. - PSU_DDR_PHY_MR11_RSVD 0x0 + * DDR4 Mode Register 6 + * (OFFSET, MASK, VALUE) (0XFD080198, 0xFFFFFFFFU ,0x00000819U) + */ + PSU_Mask_Write(DDR_PHY_MR6_OFFSET, 0xFFFFFFFFU, 0x00000819U); +/*##################################################################### */ - Power Down Control - PSU_DDR_PHY_MR11_PDCTL 0x0 + /* + * Register : MR11 @ 0XFD0801AC - DQ Bus Receiver On-Die-Termination - PSU_DDR_PHY_MR11_DQODT 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_MR11_RESERVED_31_8 0x0 - LPDDR4 Mode Register 11 - (OFFSET, MASK, VALUE) (0XFD0801AC, 0xFFFFFFFFU ,0x00000000U) - RegMask = (DDR_PHY_MR11_RESERVED_31_8_MASK | DDR_PHY_MR11_RSVD_MASK | DDR_PHY_MR11_PDCTL_MASK | DDR_PHY_MR11_DQODT_MASK | 0 ); + * These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. + * PSU_DDR_PHY_MR11_RSVD 0x0 - RegVal = ((0x00000000U << DDR_PHY_MR11_RESERVED_31_8_SHIFT - | 0x00000000U << DDR_PHY_MR11_RSVD_SHIFT - | 0x00000000U << DDR_PHY_MR11_PDCTL_SHIFT - | 0x00000000U << DDR_PHY_MR11_DQODT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_MR11_OFFSET ,0xFFFFFFFFU ,0x00000000U); - /*############################################################################################################################ */ + * Power Down Control + * PSU_DDR_PHY_MR11_PDCTL 0x0 - /*Register : MR12 @ 0XFD0801B0

+ * DQ Bus Receiver On-Die-Termination + * PSU_DDR_PHY_MR11_DQODT 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_MR12_RESERVED_31_8 0x0 + * LPDDR4 Mode Register 11 + * (OFFSET, MASK, VALUE) (0XFD0801AC, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDR_PHY_MR11_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ - These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0. - PSU_DDR_PHY_MR12_RSVD 0x0 + /* + * Register : MR12 @ 0XFD0801B0 - VREF_CA Range Select. - PSU_DDR_PHY_MR12_VR_CA 0x1 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_MR12_RESERVED_31_8 0x0 - Controls the VREF(ca) levels for Frequency-Set-Point[1:0]. - PSU_DDR_PHY_MR12_VREF_CA 0xd + * These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. + * PSU_DDR_PHY_MR12_RSVD 0x0 - LPDDR4 Mode Register 12 - (OFFSET, MASK, VALUE) (0XFD0801B0, 0xFFFFFFFFU ,0x0000004DU) - RegMask = (DDR_PHY_MR12_RESERVED_31_8_MASK | DDR_PHY_MR12_RSVD_MASK | DDR_PHY_MR12_VR_CA_MASK | DDR_PHY_MR12_VREF_CA_MASK | 0 ); + * VREF_CA Range Select. + * PSU_DDR_PHY_MR12_VR_CA 0x1 - RegVal = ((0x00000000U << DDR_PHY_MR12_RESERVED_31_8_SHIFT - | 0x00000000U << DDR_PHY_MR12_RSVD_SHIFT - | 0x00000001U << DDR_PHY_MR12_VR_CA_SHIFT - | 0x0000000DU << DDR_PHY_MR12_VREF_CA_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_MR12_OFFSET ,0xFFFFFFFFU ,0x0000004DU); - /*############################################################################################################################ */ + * Controls the VREF(ca) levels for Frequency-Set-Point[1:0]. + * PSU_DDR_PHY_MR12_VREF_CA 0xd - /*Register : MR13 @ 0XFD0801B4

+ * LPDDR4 Mode Register 12 + * (OFFSET, MASK, VALUE) (0XFD0801B0, 0xFFFFFFFFU ,0x0000004DU) + */ + PSU_Mask_Write(DDR_PHY_MR12_OFFSET, 0xFFFFFFFFU, 0x0000004DU); +/*##################################################################### */ - Reserved. Return zeroes on reads. - PSU_DDR_PHY_MR13_RESERVED_31_8 0x0 + /* + * Register : MR13 @ 0XFD0801B4 - Frequency Set Point Operation Mode - PSU_DDR_PHY_MR13_FSPOP 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_MR13_RESERVED_31_8 0x0 - Frequency Set Point Write Enable - PSU_DDR_PHY_MR13_FSPWR 0x0 + * Frequency Set Point Operation Mode + * PSU_DDR_PHY_MR13_FSPOP 0x0 - Data Mask Enable - PSU_DDR_PHY_MR13_DMD 0x0 + * Frequency Set Point Write Enable + * PSU_DDR_PHY_MR13_FSPWR 0x0 - Refresh Rate Option - PSU_DDR_PHY_MR13_RRO 0x0 + * Data Mask Enable + * PSU_DDR_PHY_MR13_DMD 0x0 - VREF Current Generator - PSU_DDR_PHY_MR13_VRCG 0x1 + * Refresh Rate Option + * PSU_DDR_PHY_MR13_RRO 0x0 - VREF Output - PSU_DDR_PHY_MR13_VRO 0x0 + * VREF Current Generator + * PSU_DDR_PHY_MR13_VRCG 0x1 - Read Preamble Training Mode - PSU_DDR_PHY_MR13_RPT 0x0 + * VREF Output + * PSU_DDR_PHY_MR13_VRO 0x0 - Command Bus Training - PSU_DDR_PHY_MR13_CBT 0x0 + * Read Preamble Training Mode + * PSU_DDR_PHY_MR13_RPT 0x0 - LPDDR4 Mode Register 13 - (OFFSET, MASK, VALUE) (0XFD0801B4, 0xFFFFFFFFU ,0x00000008U) - RegMask = (DDR_PHY_MR13_RESERVED_31_8_MASK | DDR_PHY_MR13_FSPOP_MASK | DDR_PHY_MR13_FSPWR_MASK | DDR_PHY_MR13_DMD_MASK | DDR_PHY_MR13_RRO_MASK | DDR_PHY_MR13_VRCG_MASK | DDR_PHY_MR13_VRO_MASK | DDR_PHY_MR13_RPT_MASK | DDR_PHY_MR13_CBT_MASK | 0 ); + * Command Bus Training + * PSU_DDR_PHY_MR13_CBT 0x0 - RegVal = ((0x00000000U << DDR_PHY_MR13_RESERVED_31_8_SHIFT - | 0x00000000U << DDR_PHY_MR13_FSPOP_SHIFT - | 0x00000000U << DDR_PHY_MR13_FSPWR_SHIFT - | 0x00000000U << DDR_PHY_MR13_DMD_SHIFT - | 0x00000000U << DDR_PHY_MR13_RRO_SHIFT - | 0x00000001U << DDR_PHY_MR13_VRCG_SHIFT - | 0x00000000U << DDR_PHY_MR13_VRO_SHIFT - | 0x00000000U << DDR_PHY_MR13_RPT_SHIFT - | 0x00000000U << DDR_PHY_MR13_CBT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_MR13_OFFSET ,0xFFFFFFFFU ,0x00000008U); - /*############################################################################################################################ */ + * LPDDR4 Mode Register 13 + * (OFFSET, MASK, VALUE) (0XFD0801B4, 0xFFFFFFFFU ,0x00000008U) + */ + PSU_Mask_Write(DDR_PHY_MR13_OFFSET, 0xFFFFFFFFU, 0x00000008U); +/*##################################################################### */ - /*Register : MR14 @ 0XFD0801B8

+ /* + * Register : MR14 @ 0XFD0801B8 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_MR14_RESERVED_31_8 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_MR14_RESERVED_31_8 0x0 - These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0. - PSU_DDR_PHY_MR14_RSVD 0x0 + * These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. + * PSU_DDR_PHY_MR14_RSVD 0x0 - VREFDQ Range Selects. - PSU_DDR_PHY_MR14_VR_DQ 0x1 + * VREFDQ Range Selects. + * PSU_DDR_PHY_MR14_VR_DQ 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_MR14_VREF_DQ 0xd + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_MR14_VREF_DQ 0xd - LPDDR4 Mode Register 14 - (OFFSET, MASK, VALUE) (0XFD0801B8, 0xFFFFFFFFU ,0x0000004DU) - RegMask = (DDR_PHY_MR14_RESERVED_31_8_MASK | DDR_PHY_MR14_RSVD_MASK | DDR_PHY_MR14_VR_DQ_MASK | DDR_PHY_MR14_VREF_DQ_MASK | 0 ); + * LPDDR4 Mode Register 14 + * (OFFSET, MASK, VALUE) (0XFD0801B8, 0xFFFFFFFFU ,0x0000004DU) + */ + PSU_Mask_Write(DDR_PHY_MR14_OFFSET, 0xFFFFFFFFU, 0x0000004DU); +/*##################################################################### */ - RegVal = ((0x00000000U << DDR_PHY_MR14_RESERVED_31_8_SHIFT - | 0x00000000U << DDR_PHY_MR14_RSVD_SHIFT - | 0x00000001U << DDR_PHY_MR14_VR_DQ_SHIFT - | 0x0000000DU << DDR_PHY_MR14_VREF_DQ_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_MR14_OFFSET ,0xFFFFFFFFU ,0x0000004DU); - /*############################################################################################################################ */ + /* + * Register : MR22 @ 0XFD0801D8 - /*Register : MR22 @ 0XFD0801D8

+ * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_MR22_RESERVED_31_8 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_MR22_RESERVED_31_8 0x0 + * These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. + * PSU_DDR_PHY_MR22_RSVD 0x0 - These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0. - PSU_DDR_PHY_MR22_RSVD 0x0 + * CA ODT termination disable. + * PSU_DDR_PHY_MR22_ODTD_CA 0x0 - CA ODT termination disable. - PSU_DDR_PHY_MR22_ODTD_CA 0x0 + * ODT CS override. + * PSU_DDR_PHY_MR22_ODTE_CS 0x0 - ODT CS override. - PSU_DDR_PHY_MR22_ODTE_CS 0x0 + * ODT CK override. + * PSU_DDR_PHY_MR22_ODTE_CK 0x0 - ODT CK override. - PSU_DDR_PHY_MR22_ODTE_CK 0x0 + * Controller ODT value for VOH calibration. + * PSU_DDR_PHY_MR22_CODT 0x0 - Controller ODT value for VOH calibration. - PSU_DDR_PHY_MR22_CODT 0x0 + * LPDDR4 Mode Register 22 + * (OFFSET, MASK, VALUE) (0XFD0801D8, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDR_PHY_MR22_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ - LPDDR4 Mode Register 22 - (OFFSET, MASK, VALUE) (0XFD0801D8, 0xFFFFFFFFU ,0x00000000U) - RegMask = (DDR_PHY_MR22_RESERVED_31_8_MASK | DDR_PHY_MR22_RSVD_MASK | DDR_PHY_MR22_ODTD_CA_MASK | DDR_PHY_MR22_ODTE_CS_MASK | DDR_PHY_MR22_ODTE_CK_MASK | DDR_PHY_MR22_CODT_MASK | 0 ); + /* + * Register : DTCR0 @ 0XFD080200 - RegVal = ((0x00000000U << DDR_PHY_MR22_RESERVED_31_8_SHIFT - | 0x00000000U << DDR_PHY_MR22_RSVD_SHIFT - | 0x00000000U << DDR_PHY_MR22_ODTD_CA_SHIFT - | 0x00000000U << DDR_PHY_MR22_ODTE_CS_SHIFT - | 0x00000000U << DDR_PHY_MR22_ODTE_CK_SHIFT - | 0x00000000U << DDR_PHY_MR22_CODT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_MR22_OFFSET ,0xFFFFFFFFU ,0x00000000U); - /*############################################################################################################################ */ + * Refresh During Training + * PSU_DDR_PHY_DTCR0_RFSHDT 0x8 - /*Register : DTCR0 @ 0XFD080200

+ * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTCR0_RESERVED_27_26 0x0 - Refresh During Training - PSU_DDR_PHY_DTCR0_RFSHDT 0x8 + * Data Training Debug Rank Select + * PSU_DDR_PHY_DTCR0_DTDRS 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTCR0_RESERVED_27_26 0x0 + * Data Training with Early/Extended Gate + * PSU_DDR_PHY_DTCR0_DTEXG 0x0 - Data Training Debug Rank Select - PSU_DDR_PHY_DTCR0_DTDRS 0x0 + * Data Training Extended Write DQS + * PSU_DDR_PHY_DTCR0_DTEXD 0x0 - Data Training with Early/Extended Gate - PSU_DDR_PHY_DTCR0_DTEXG 0x0 + * Data Training Debug Step + * PSU_DDR_PHY_DTCR0_DTDSTP 0x0 - Data Training Extended Write DQS - PSU_DDR_PHY_DTCR0_DTEXD 0x0 + * Data Training Debug Enable + * PSU_DDR_PHY_DTCR0_DTDEN 0x0 - Data Training Debug Step - PSU_DDR_PHY_DTCR0_DTDSTP 0x0 + * Data Training Debug Byte Select + * PSU_DDR_PHY_DTCR0_DTDBS 0x0 - Data Training Debug Enable - PSU_DDR_PHY_DTCR0_DTDEN 0x0 + * Data Training read DBI deskewing configuration + * PSU_DDR_PHY_DTCR0_DTRDBITR 0x2 - Data Training Debug Byte Select - PSU_DDR_PHY_DTCR0_DTDBS 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTCR0_RESERVED_13 0x0 - Data Training read DBI deskewing configuration - PSU_DDR_PHY_DTCR0_DTRDBITR 0x2 + * Data Training Write Bit Deskew Data Mask + * PSU_DDR_PHY_DTCR0_DTWBDDM 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTCR0_RESERVED_13 0x0 + * Refreshes Issued During Entry to Training + * PSU_DDR_PHY_DTCR0_RFSHEN 0x1 - Data Training Write Bit Deskew Data Mask - PSU_DDR_PHY_DTCR0_DTWBDDM 0x1 + * Data Training Compare Data + * PSU_DDR_PHY_DTCR0_DTCMPD 0x1 - Refreshes Issued During Entry to Training - PSU_DDR_PHY_DTCR0_RFSHEN 0x1 + * Data Training Using MPR + * PSU_DDR_PHY_DTCR0_DTMPR 0x1 - Data Training Compare Data - PSU_DDR_PHY_DTCR0_DTCMPD 0x1 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTCR0_RESERVED_5_4 0x0 - Data Training Using MPR - PSU_DDR_PHY_DTCR0_DTMPR 0x1 + * Data Training Repeat Number + * PSU_DDR_PHY_DTCR0_DTRPTN 0x7 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTCR0_RESERVED_5_4 0x0 + * Data Training Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD080200, 0xFFFFFFFFU ,0x800091C7U) + */ + PSU_Mask_Write(DDR_PHY_DTCR0_OFFSET, 0xFFFFFFFFU, 0x800091C7U); +/*##################################################################### */ - Data Training Repeat Number - PSU_DDR_PHY_DTCR0_DTRPTN 0x7 + /* + * Register : DTCR1 @ 0XFD080204 - Data Training Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD080200, 0xFFFFFFFFU ,0x800091C7U) - RegMask = (DDR_PHY_DTCR0_RFSHDT_MASK | DDR_PHY_DTCR0_RESERVED_27_26_MASK | DDR_PHY_DTCR0_DTDRS_MASK | DDR_PHY_DTCR0_DTEXG_MASK | DDR_PHY_DTCR0_DTEXD_MASK | DDR_PHY_DTCR0_DTDSTP_MASK | DDR_PHY_DTCR0_DTDEN_MASK | DDR_PHY_DTCR0_DTDBS_MASK | DDR_PHY_DTCR0_DTRDBITR_MASK | DDR_PHY_DTCR0_RESERVED_13_MASK | DDR_PHY_DTCR0_DTWBDDM_MASK | DDR_PHY_DTCR0_RFSHEN_MASK | DDR_PHY_DTCR0_DTCMPD_MASK | DDR_PHY_DTCR0_DTMPR_MASK | DDR_PHY_DTCR0_RESERVED_5_4_MASK | DDR_PHY_DTCR0_DTRPTN_MASK | 0 ); + * Rank Enable. + * PSU_DDR_PHY_DTCR1_RANKEN_RSVD 0x0 - RegVal = ((0x00000008U << DDR_PHY_DTCR0_RFSHDT_SHIFT - | 0x00000000U << DDR_PHY_DTCR0_RESERVED_27_26_SHIFT - | 0x00000000U << DDR_PHY_DTCR0_DTDRS_SHIFT - | 0x00000000U << DDR_PHY_DTCR0_DTEXG_SHIFT - | 0x00000000U << DDR_PHY_DTCR0_DTEXD_SHIFT - | 0x00000000U << DDR_PHY_DTCR0_DTDSTP_SHIFT - | 0x00000000U << DDR_PHY_DTCR0_DTDEN_SHIFT - | 0x00000000U << DDR_PHY_DTCR0_DTDBS_SHIFT - | 0x00000002U << DDR_PHY_DTCR0_DTRDBITR_SHIFT - | 0x00000000U << DDR_PHY_DTCR0_RESERVED_13_SHIFT - | 0x00000001U << DDR_PHY_DTCR0_DTWBDDM_SHIFT - | 0x00000001U << DDR_PHY_DTCR0_RFSHEN_SHIFT - | 0x00000001U << DDR_PHY_DTCR0_DTCMPD_SHIFT - | 0x00000001U << DDR_PHY_DTCR0_DTMPR_SHIFT - | 0x00000000U << DDR_PHY_DTCR0_RESERVED_5_4_SHIFT - | 0x00000007U << DDR_PHY_DTCR0_DTRPTN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DTCR0_OFFSET ,0xFFFFFFFFU ,0x800091C7U); - /*############################################################################################################################ */ + * Rank Enable. + * PSU_DDR_PHY_DTCR1_RANKEN 0x1 - /*Register : DTCR1 @ 0XFD080204

+ * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTCR1_RESERVED_15_14 0x0 - Rank Enable. - PSU_DDR_PHY_DTCR1_RANKEN_RSVD 0x0 + * Data Training Rank + * PSU_DDR_PHY_DTCR1_DTRANK 0x0 - Rank Enable. - PSU_DDR_PHY_DTCR1_RANKEN 0x1 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTCR1_RESERVED_11 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTCR1_RESERVED_15_14 0x0 + * Read Leveling Gate Sampling Difference + * PSU_DDR_PHY_DTCR1_RDLVLGDIFF 0x2 - Data Training Rank - PSU_DDR_PHY_DTCR1_DTRANK 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTCR1_RESERVED_7 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTCR1_RESERVED_11 0x0 + * Read Leveling Gate Shift + * PSU_DDR_PHY_DTCR1_RDLVLGS 0x3 - Read Leveling Gate Sampling Difference - PSU_DDR_PHY_DTCR1_RDLVLGDIFF 0x2 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTCR1_RESERVED_3 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTCR1_RESERVED_7 0x0 + * Read Preamble Training enable + * PSU_DDR_PHY_DTCR1_RDPRMVL_TRN 0x1 - Read Leveling Gate Shift - PSU_DDR_PHY_DTCR1_RDLVLGS 0x3 + * Read Leveling Enable + * PSU_DDR_PHY_DTCR1_RDLVLEN 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTCR1_RESERVED_3 0x0 + * Basic Gate Training Enable + * PSU_DDR_PHY_DTCR1_BSTEN 0x0 - Read Preamble Training enable - PSU_DDR_PHY_DTCR1_RDPRMVL_TRN 0x1 + * Data Training Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD080204, 0xFFFFFFFFU ,0x00010236U) + */ + PSU_Mask_Write(DDR_PHY_DTCR1_OFFSET, 0xFFFFFFFFU, 0x00010236U); +/*##################################################################### */ - Read Leveling Enable - PSU_DDR_PHY_DTCR1_RDLVLEN 0x1 + /* + * Register : CATR0 @ 0XFD080240 - Basic Gate Training Enable - PSU_DDR_PHY_DTCR1_BSTEN 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_CATR0_RESERVED_31_21 0x0 - Data Training Configuration Register 1 - (OFFSET, MASK, VALUE) (0XFD080204, 0xFFFFFFFFU ,0x00010236U) - RegMask = (DDR_PHY_DTCR1_RANKEN_RSVD_MASK | DDR_PHY_DTCR1_RANKEN_MASK | DDR_PHY_DTCR1_RESERVED_15_14_MASK | DDR_PHY_DTCR1_DTRANK_MASK | DDR_PHY_DTCR1_RESERVED_11_MASK | DDR_PHY_DTCR1_RDLVLGDIFF_MASK | DDR_PHY_DTCR1_RESERVED_7_MASK | DDR_PHY_DTCR1_RDLVLGS_MASK | DDR_PHY_DTCR1_RESERVED_3_MASK | DDR_PHY_DTCR1_RDPRMVL_TRN_MASK | DDR_PHY_DTCR1_RDLVLEN_MASK | DDR_PHY_DTCR1_BSTEN_MASK | 0 ); + * Minimum time (in terms of number of dram clocks) between two consectuve + * CA calibration command + * PSU_DDR_PHY_CATR0_CACD 0x14 - RegVal = ((0x00000000U << DDR_PHY_DTCR1_RANKEN_RSVD_SHIFT - | 0x00000001U << DDR_PHY_DTCR1_RANKEN_SHIFT - | 0x00000000U << DDR_PHY_DTCR1_RESERVED_15_14_SHIFT - | 0x00000000U << DDR_PHY_DTCR1_DTRANK_SHIFT - | 0x00000000U << DDR_PHY_DTCR1_RESERVED_11_SHIFT - | 0x00000002U << DDR_PHY_DTCR1_RDLVLGDIFF_SHIFT - | 0x00000000U << DDR_PHY_DTCR1_RESERVED_7_SHIFT - | 0x00000003U << DDR_PHY_DTCR1_RDLVLGS_SHIFT - | 0x00000000U << DDR_PHY_DTCR1_RESERVED_3_SHIFT - | 0x00000001U << DDR_PHY_DTCR1_RDPRMVL_TRN_SHIFT - | 0x00000001U << DDR_PHY_DTCR1_RDLVLEN_SHIFT - | 0x00000000U << DDR_PHY_DTCR1_BSTEN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DTCR1_OFFSET ,0xFFFFFFFFU ,0x00010236U); - /*############################################################################################################################ */ + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_CATR0_RESERVED_15_13 0x0 - /*Register : CATR0 @ 0XFD080240

+ * Minimum time (in terms of number of dram clocks) PUB should wait before + * sampling the CA response after Calibration command has been sent to the + * memory + * PSU_DDR_PHY_CATR0_CAADR 0x10 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_CATR0_RESERVED_31_21 0x0 + * CA_1 Response Byte Lane 1 + * PSU_DDR_PHY_CATR0_CA1BYTE1 0x5 - Minimum time (in terms of number of dram clocks) between two consectuve CA calibration command - PSU_DDR_PHY_CATR0_CACD 0x14 + * CA_1 Response Byte Lane 0 + * PSU_DDR_PHY_CATR0_CA1BYTE0 0x4 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_CATR0_RESERVED_15_13 0x0 + * CA Training Register 0 + * (OFFSET, MASK, VALUE) (0XFD080240, 0xFFFFFFFFU ,0x00141054U) + */ + PSU_Mask_Write(DDR_PHY_CATR0_OFFSET, 0xFFFFFFFFU, 0x00141054U); +/*##################################################################### */ - Minimum time (in terms of number of dram clocks) PUB should wait before sampling the CA response after Calibration command ha - been sent to the memory - PSU_DDR_PHY_CATR0_CAADR 0x10 + /* + * Register : DQSDR0 @ 0XFD080250 - CA_1 Response Byte Lane 1 - PSU_DDR_PHY_CATR0_CA1BYTE1 0x5 + * Number of delay taps by which the DQS gate LCDL will be updated when DQS + * drift is detected + * PSU_DDR_PHY_DQSDR0_DFTDLY 0x0 - CA_1 Response Byte Lane 0 - PSU_DDR_PHY_CATR0_CA1BYTE0 0x4 - - CA Training Register 0 - (OFFSET, MASK, VALUE) (0XFD080240, 0xFFFFFFFFU ,0x00141054U) - RegMask = (DDR_PHY_CATR0_RESERVED_31_21_MASK | DDR_PHY_CATR0_CACD_MASK | DDR_PHY_CATR0_RESERVED_15_13_MASK | DDR_PHY_CATR0_CAADR_MASK | DDR_PHY_CATR0_CA1BYTE1_MASK | DDR_PHY_CATR0_CA1BYTE0_MASK | 0 ); - - RegVal = ((0x00000000U << DDR_PHY_CATR0_RESERVED_31_21_SHIFT - | 0x00000014U << DDR_PHY_CATR0_CACD_SHIFT - | 0x00000000U << DDR_PHY_CATR0_RESERVED_15_13_SHIFT - | 0x00000010U << DDR_PHY_CATR0_CAADR_SHIFT - | 0x00000005U << DDR_PHY_CATR0_CA1BYTE1_SHIFT - | 0x00000004U << DDR_PHY_CATR0_CA1BYTE0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_CATR0_OFFSET ,0xFFFFFFFFU ,0x00141054U); - /*############################################################################################################################ */ + * Drift Impedance Update + * PSU_DDR_PHY_DQSDR0_DFTZQUP 0x0 - /*Register : BISTLSR @ 0XFD080414

+ * Drift DDL Update + * PSU_DDR_PHY_DQSDR0_DFTDDLUP 0x0 - LFSR seed for pseudo-random BIST patterns - PSU_DDR_PHY_BISTLSR_SEED 0x12341000 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DQSDR0_RESERVED_25_22 0x0 - BIST LFSR Seed Register - (OFFSET, MASK, VALUE) (0XFD080414, 0xFFFFFFFFU ,0x12341000U) - RegMask = (DDR_PHY_BISTLSR_SEED_MASK | 0 ); + * Drift Read Spacing + * PSU_DDR_PHY_DQSDR0_DFTRDSPC 0x0 - RegVal = ((0x12341000U << DDR_PHY_BISTLSR_SEED_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_BISTLSR_OFFSET ,0xFFFFFFFFU ,0x12341000U); - /*############################################################################################################################ */ + * Drift Back-to-Back Reads + * PSU_DDR_PHY_DQSDR0_DFTB2BRD 0x8 - /*Register : RIOCR5 @ 0XFD0804F4

+ * Drift Idle Reads + * PSU_DDR_PHY_DQSDR0_DFTIDLRD 0x8 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_RIOCR5_RESERVED_31_16 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DQSDR0_RESERVED_11_8 0x0 - Reserved. Return zeros on reads. - PSU_DDR_PHY_RIOCR5_ODTOEMODE_RSVD 0x0 + * Gate Pulse Enable + * PSU_DDR_PHY_DQSDR0_DFTGPULSE 0x0 - SDRAM On-die Termination Output Enable (OE) Mode Selection. - PSU_DDR_PHY_RIOCR5_ODTOEMODE 0x5 + * DQS Drift Update Mode + * PSU_DDR_PHY_DQSDR0_DFTUPMODE 0x0 - Rank I/O Configuration Register 5 - (OFFSET, MASK, VALUE) (0XFD0804F4, 0xFFFFFFFFU ,0x00000005U) - RegMask = (DDR_PHY_RIOCR5_RESERVED_31_16_MASK | DDR_PHY_RIOCR5_ODTOEMODE_RSVD_MASK | DDR_PHY_RIOCR5_ODTOEMODE_MASK | 0 ); + * DQS Drift Detection Mode + * PSU_DDR_PHY_DQSDR0_DFTDTMODE 0x0 - RegVal = ((0x00000000U << DDR_PHY_RIOCR5_RESERVED_31_16_SHIFT - | 0x00000000U << DDR_PHY_RIOCR5_ODTOEMODE_RSVD_SHIFT - | 0x00000005U << DDR_PHY_RIOCR5_ODTOEMODE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_RIOCR5_OFFSET ,0xFFFFFFFFU ,0x00000005U); - /*############################################################################################################################ */ + * DQS Drift Detection Enable + * PSU_DDR_PHY_DQSDR0_DFTDTEN 0x0 - /*Register : ACIOCR0 @ 0XFD080500

+ * DQS Drift Register 0 + * (OFFSET, MASK, VALUE) (0XFD080250, 0xFFFFFFFFU ,0x00088000U) + */ + PSU_Mask_Write(DDR_PHY_DQSDR0_OFFSET, 0xFFFFFFFFU, 0x00088000U); +/*##################################################################### */ - Address/Command Slew Rate (D3F I/O Only) - PSU_DDR_PHY_ACIOCR0_ACSR 0x0 + /* + * Register : BISTLSR @ 0XFD080414 - SDRAM Reset I/O Mode - PSU_DDR_PHY_ACIOCR0_RSTIOM 0x1 + * LFSR seed for pseudo-random BIST patterns + * PSU_DDR_PHY_BISTLSR_SEED 0x12341000 - SDRAM Reset Power Down Receiver - PSU_DDR_PHY_ACIOCR0_RSTPDR 0x1 + * BIST LFSR Seed Register + * (OFFSET, MASK, VALUE) (0XFD080414, 0xFFFFFFFFU ,0x12341000U) + */ + PSU_Mask_Write(DDR_PHY_BISTLSR_OFFSET, 0xFFFFFFFFU, 0x12341000U); +/*##################################################################### */ - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACIOCR0_RESERVED_27 0x0 + /* + * Register : RIOCR5 @ 0XFD0804F4 - SDRAM Reset On-Die Termination - PSU_DDR_PHY_ACIOCR0_RSTODT 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_RIOCR5_RESERVED_31_16 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACIOCR0_RESERVED_25_10 0x0 + * Reserved. Return zeros on reads. + * PSU_DDR_PHY_RIOCR5_ODTOEMODE_RSVD 0x0 - CK Duty Cycle Correction - PSU_DDR_PHY_ACIOCR0_CKDCC 0x0 + * SDRAM On-die Termination Output Enable (OE) Mode Selection. + * PSU_DDR_PHY_RIOCR5_ODTOEMODE 0x5 - AC Power Down Receiver Mode - PSU_DDR_PHY_ACIOCR0_ACPDRMODE 0x2 + * Rank I/O Configuration Register 5 + * (OFFSET, MASK, VALUE) (0XFD0804F4, 0xFFFFFFFFU ,0x00000005U) + */ + PSU_Mask_Write(DDR_PHY_RIOCR5_OFFSET, 0xFFFFFFFFU, 0x00000005U); +/*##################################################################### */ - AC On-die Termination Mode - PSU_DDR_PHY_ACIOCR0_ACODTMODE 0x2 + /* + * Register : ACIOCR0 @ 0XFD080500 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACIOCR0_RESERVED_1 0x0 + * Address/Command Slew Rate (D3F I/O Only) + * PSU_DDR_PHY_ACIOCR0_ACSR 0x0 - Control delayed or non-delayed clock to CS_N/ODT?CKE AC slices. - PSU_DDR_PHY_ACIOCR0_ACRANKCLKSEL 0x0 + * SDRAM Reset I/O Mode + * PSU_DDR_PHY_ACIOCR0_RSTIOM 0x1 - AC I/O Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD080500, 0xFFFFFFFFU ,0x30000028U) - RegMask = (DDR_PHY_ACIOCR0_ACSR_MASK | DDR_PHY_ACIOCR0_RSTIOM_MASK | DDR_PHY_ACIOCR0_RSTPDR_MASK | DDR_PHY_ACIOCR0_RESERVED_27_MASK | DDR_PHY_ACIOCR0_RSTODT_MASK | DDR_PHY_ACIOCR0_RESERVED_25_10_MASK | DDR_PHY_ACIOCR0_CKDCC_MASK | DDR_PHY_ACIOCR0_ACPDRMODE_MASK | DDR_PHY_ACIOCR0_ACODTMODE_MASK | DDR_PHY_ACIOCR0_RESERVED_1_MASK | DDR_PHY_ACIOCR0_ACRANKCLKSEL_MASK | 0 ); + * SDRAM Reset Power Down Receiver + * PSU_DDR_PHY_ACIOCR0_RSTPDR 0x1 - RegVal = ((0x00000000U << DDR_PHY_ACIOCR0_ACSR_SHIFT - | 0x00000001U << DDR_PHY_ACIOCR0_RSTIOM_SHIFT - | 0x00000001U << DDR_PHY_ACIOCR0_RSTPDR_SHIFT - | 0x00000000U << DDR_PHY_ACIOCR0_RESERVED_27_SHIFT - | 0x00000000U << DDR_PHY_ACIOCR0_RSTODT_SHIFT - | 0x00000000U << DDR_PHY_ACIOCR0_RESERVED_25_10_SHIFT - | 0x00000000U << DDR_PHY_ACIOCR0_CKDCC_SHIFT - | 0x00000002U << DDR_PHY_ACIOCR0_ACPDRMODE_SHIFT - | 0x00000002U << DDR_PHY_ACIOCR0_ACODTMODE_SHIFT - | 0x00000000U << DDR_PHY_ACIOCR0_RESERVED_1_SHIFT - | 0x00000000U << DDR_PHY_ACIOCR0_ACRANKCLKSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_ACIOCR0_OFFSET ,0xFFFFFFFFU ,0x30000028U); - /*############################################################################################################################ */ + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACIOCR0_RESERVED_27 0x0 - /*Register : ACIOCR2 @ 0XFD080508

+ * SDRAM Reset On-Die Termination + * PSU_DDR_PHY_ACIOCR0_RSTODT 0x0 - Clock gating for glue logic inside CLKGEN and glue logic inside CONTROL slice - PSU_DDR_PHY_ACIOCR2_CLKGENCLKGATE 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACIOCR0_RESERVED_25_10 0x0 - Clock gating for Output Enable D slices [0] - PSU_DDR_PHY_ACIOCR2_ACOECLKGATE0 0x0 + * CK Duty Cycle Correction + * PSU_DDR_PHY_ACIOCR0_CKDCC 0x0 - Clock gating for Power Down Receiver D slices [0] - PSU_DDR_PHY_ACIOCR2_ACPDRCLKGATE0 0x0 + * AC Power Down Receiver Mode + * PSU_DDR_PHY_ACIOCR0_ACPDRMODE 0x2 - Clock gating for Termination Enable D slices [0] - PSU_DDR_PHY_ACIOCR2_ACTECLKGATE0 0x0 + * AC On-die Termination Mode + * PSU_DDR_PHY_ACIOCR0_ACODTMODE 0x2 - Clock gating for CK# D slices [1:0] - PSU_DDR_PHY_ACIOCR2_CKNCLKGATE0 0x2 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACIOCR0_RESERVED_1 0x0 - Clock gating for CK D slices [1:0] - PSU_DDR_PHY_ACIOCR2_CKCLKGATE0 0x2 + * Control delayed or non-delayed clock to CS_N/ODT?CKE AC slices. + * PSU_DDR_PHY_ACIOCR0_ACRANKCLKSEL 0x0 - Clock gating for AC D slices [23:0] - PSU_DDR_PHY_ACIOCR2_ACCLKGATE0 0x0 + * AC I/O Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD080500, 0xFFFFFFFFU ,0x30000028U) + */ + PSU_Mask_Write(DDR_PHY_ACIOCR0_OFFSET, 0xFFFFFFFFU, 0x30000028U); +/*##################################################################### */ - AC I/O Configuration Register 2 - (OFFSET, MASK, VALUE) (0XFD080508, 0xFFFFFFFFU ,0x0A000000U) - RegMask = (DDR_PHY_ACIOCR2_CLKGENCLKGATE_MASK | DDR_PHY_ACIOCR2_ACOECLKGATE0_MASK | DDR_PHY_ACIOCR2_ACPDRCLKGATE0_MASK | DDR_PHY_ACIOCR2_ACTECLKGATE0_MASK | DDR_PHY_ACIOCR2_CKNCLKGATE0_MASK | DDR_PHY_ACIOCR2_CKCLKGATE0_MASK | DDR_PHY_ACIOCR2_ACCLKGATE0_MASK | 0 ); + /* + * Register : ACIOCR2 @ 0XFD080508 - RegVal = ((0x00000000U << DDR_PHY_ACIOCR2_CLKGENCLKGATE_SHIFT - | 0x00000000U << DDR_PHY_ACIOCR2_ACOECLKGATE0_SHIFT - | 0x00000000U << DDR_PHY_ACIOCR2_ACPDRCLKGATE0_SHIFT - | 0x00000000U << DDR_PHY_ACIOCR2_ACTECLKGATE0_SHIFT - | 0x00000002U << DDR_PHY_ACIOCR2_CKNCLKGATE0_SHIFT - | 0x00000002U << DDR_PHY_ACIOCR2_CKCLKGATE0_SHIFT - | 0x00000000U << DDR_PHY_ACIOCR2_ACCLKGATE0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_ACIOCR2_OFFSET ,0xFFFFFFFFU ,0x0A000000U); - /*############################################################################################################################ */ + * Clock gating for glue logic inside CLKGEN and glue logic inside CONTROL + * slice + * PSU_DDR_PHY_ACIOCR2_CLKGENCLKGATE 0x0 - /*Register : ACIOCR3 @ 0XFD08050C

+ * Clock gating for Output Enable D slices [0] + * PSU_DDR_PHY_ACIOCR2_ACOECLKGATE0 0x0 - SDRAM Parity Output Enable (OE) Mode Selection - PSU_DDR_PHY_ACIOCR3_PAROEMODE 0x0 + * Clock gating for Power Down Receiver D slices [0] + * PSU_DDR_PHY_ACIOCR2_ACPDRCLKGATE0 0x0 - SDRAM Bank Group Output Enable (OE) Mode Selection - PSU_DDR_PHY_ACIOCR3_BGOEMODE 0x0 + * Clock gating for Termination Enable D slices [0] + * PSU_DDR_PHY_ACIOCR2_ACTECLKGATE0 0x0 - SDRAM Bank Address Output Enable (OE) Mode Selection - PSU_DDR_PHY_ACIOCR3_BAOEMODE 0x0 + * Clock gating for CK# D slices [1:0] + * PSU_DDR_PHY_ACIOCR2_CKNCLKGATE0 0x2 - SDRAM A[17] Output Enable (OE) Mode Selection - PSU_DDR_PHY_ACIOCR3_A17OEMODE 0x0 + * Clock gating for CK D slices [1:0] + * PSU_DDR_PHY_ACIOCR2_CKCLKGATE0 0x2 - SDRAM A[16] / RAS_n Output Enable (OE) Mode Selection - PSU_DDR_PHY_ACIOCR3_A16OEMODE 0x0 + * Clock gating for AC D slices [23:0] + * PSU_DDR_PHY_ACIOCR2_ACCLKGATE0 0x0 - SDRAM ACT_n Output Enable (OE) Mode Selection (DDR4 only) - PSU_DDR_PHY_ACIOCR3_ACTOEMODE 0x0 + * AC I/O Configuration Register 2 + * (OFFSET, MASK, VALUE) (0XFD080508, 0xFFFFFFFFU ,0x0A000000U) + */ + PSU_Mask_Write(DDR_PHY_ACIOCR2_OFFSET, 0xFFFFFFFFU, 0x0A000000U); +/*##################################################################### */ - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACIOCR3_RESERVED_15_8 0x0 + /* + * Register : ACIOCR3 @ 0XFD08050C - Reserved. Return zeros on reads. - PSU_DDR_PHY_ACIOCR3_CKOEMODE_RSVD 0x0 + * SDRAM Parity Output Enable (OE) Mode Selection + * PSU_DDR_PHY_ACIOCR3_PAROEMODE 0x0 - SDRAM CK Output Enable (OE) Mode Selection. - PSU_DDR_PHY_ACIOCR3_CKOEMODE 0x9 + * SDRAM Bank Group Output Enable (OE) Mode Selection + * PSU_DDR_PHY_ACIOCR3_BGOEMODE 0x0 - AC I/O Configuration Register 3 - (OFFSET, MASK, VALUE) (0XFD08050C, 0xFFFFFFFFU ,0x00000009U) - RegMask = (DDR_PHY_ACIOCR3_PAROEMODE_MASK | DDR_PHY_ACIOCR3_BGOEMODE_MASK | DDR_PHY_ACIOCR3_BAOEMODE_MASK | DDR_PHY_ACIOCR3_A17OEMODE_MASK | DDR_PHY_ACIOCR3_A16OEMODE_MASK | DDR_PHY_ACIOCR3_ACTOEMODE_MASK | DDR_PHY_ACIOCR3_RESERVED_15_8_MASK | DDR_PHY_ACIOCR3_CKOEMODE_RSVD_MASK | DDR_PHY_ACIOCR3_CKOEMODE_MASK | 0 ); + * SDRAM Bank Address Output Enable (OE) Mode Selection + * PSU_DDR_PHY_ACIOCR3_BAOEMODE 0x0 - RegVal = ((0x00000000U << DDR_PHY_ACIOCR3_PAROEMODE_SHIFT - | 0x00000000U << DDR_PHY_ACIOCR3_BGOEMODE_SHIFT - | 0x00000000U << DDR_PHY_ACIOCR3_BAOEMODE_SHIFT - | 0x00000000U << DDR_PHY_ACIOCR3_A17OEMODE_SHIFT - | 0x00000000U << DDR_PHY_ACIOCR3_A16OEMODE_SHIFT - | 0x00000000U << DDR_PHY_ACIOCR3_ACTOEMODE_SHIFT - | 0x00000000U << DDR_PHY_ACIOCR3_RESERVED_15_8_SHIFT - | 0x00000000U << DDR_PHY_ACIOCR3_CKOEMODE_RSVD_SHIFT - | 0x00000009U << DDR_PHY_ACIOCR3_CKOEMODE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_ACIOCR3_OFFSET ,0xFFFFFFFFU ,0x00000009U); - /*############################################################################################################################ */ + * SDRAM A[17] Output Enable (OE) Mode Selection + * PSU_DDR_PHY_ACIOCR3_A17OEMODE 0x0 - /*Register : ACIOCR4 @ 0XFD080510

+ * SDRAM A[16] / RAS_n Output Enable (OE) Mode Selection + * PSU_DDR_PHY_ACIOCR3_A16OEMODE 0x0 - Clock gating for AC LB slices and loopback read valid slices - PSU_DDR_PHY_ACIOCR4_LBCLKGATE 0x0 + * SDRAM ACT_n Output Enable (OE) Mode Selection (DDR4 only) + * PSU_DDR_PHY_ACIOCR3_ACTOEMODE 0x0 - Clock gating for Output Enable D slices [1] - PSU_DDR_PHY_ACIOCR4_ACOECLKGATE1 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACIOCR3_RESERVED_15_8 0x0 - Clock gating for Power Down Receiver D slices [1] - PSU_DDR_PHY_ACIOCR4_ACPDRCLKGATE1 0x0 + * Reserved. Return zeros on reads. + * PSU_DDR_PHY_ACIOCR3_CKOEMODE_RSVD 0x0 - Clock gating for Termination Enable D slices [1] - PSU_DDR_PHY_ACIOCR4_ACTECLKGATE1 0x0 + * SDRAM CK Output Enable (OE) Mode Selection. + * PSU_DDR_PHY_ACIOCR3_CKOEMODE 0x9 - Clock gating for CK# D slices [3:2] - PSU_DDR_PHY_ACIOCR4_CKNCLKGATE1 0x2 + * AC I/O Configuration Register 3 + * (OFFSET, MASK, VALUE) (0XFD08050C, 0xFFFFFFFFU ,0x00000009U) + */ + PSU_Mask_Write(DDR_PHY_ACIOCR3_OFFSET, 0xFFFFFFFFU, 0x00000009U); +/*##################################################################### */ - Clock gating for CK D slices [3:2] - PSU_DDR_PHY_ACIOCR4_CKCLKGATE1 0x2 + /* + * Register : ACIOCR4 @ 0XFD080510 - Clock gating for AC D slices [47:24] - PSU_DDR_PHY_ACIOCR4_ACCLKGATE1 0x0 + * Clock gating for AC LB slices and loopback read valid slices + * PSU_DDR_PHY_ACIOCR4_LBCLKGATE 0x0 - AC I/O Configuration Register 4 - (OFFSET, MASK, VALUE) (0XFD080510, 0xFFFFFFFFU ,0x0A000000U) - RegMask = (DDR_PHY_ACIOCR4_LBCLKGATE_MASK | DDR_PHY_ACIOCR4_ACOECLKGATE1_MASK | DDR_PHY_ACIOCR4_ACPDRCLKGATE1_MASK | DDR_PHY_ACIOCR4_ACTECLKGATE1_MASK | DDR_PHY_ACIOCR4_CKNCLKGATE1_MASK | DDR_PHY_ACIOCR4_CKCLKGATE1_MASK | DDR_PHY_ACIOCR4_ACCLKGATE1_MASK | 0 ); + * Clock gating for Output Enable D slices [1] + * PSU_DDR_PHY_ACIOCR4_ACOECLKGATE1 0x0 - RegVal = ((0x00000000U << DDR_PHY_ACIOCR4_LBCLKGATE_SHIFT - | 0x00000000U << DDR_PHY_ACIOCR4_ACOECLKGATE1_SHIFT - | 0x00000000U << DDR_PHY_ACIOCR4_ACPDRCLKGATE1_SHIFT - | 0x00000000U << DDR_PHY_ACIOCR4_ACTECLKGATE1_SHIFT - | 0x00000002U << DDR_PHY_ACIOCR4_CKNCLKGATE1_SHIFT - | 0x00000002U << DDR_PHY_ACIOCR4_CKCLKGATE1_SHIFT - | 0x00000000U << DDR_PHY_ACIOCR4_ACCLKGATE1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_ACIOCR4_OFFSET ,0xFFFFFFFFU ,0x0A000000U); - /*############################################################################################################################ */ + * Clock gating for Power Down Receiver D slices [1] + * PSU_DDR_PHY_ACIOCR4_ACPDRCLKGATE1 0x0 - /*Register : IOVCR0 @ 0XFD080520

+ * Clock gating for Termination Enable D slices [1] + * PSU_DDR_PHY_ACIOCR4_ACTECLKGATE1 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_IOVCR0_RESERVED_31_29 0x0 + * Clock gating for CK# D slices [3:2] + * PSU_DDR_PHY_ACIOCR4_CKNCLKGATE1 0x2 - Address/command lane VREF Pad Enable - PSU_DDR_PHY_IOVCR0_ACREFPEN 0x0 + * Clock gating for CK D slices [3:2] + * PSU_DDR_PHY_ACIOCR4_CKCLKGATE1 0x2 - Address/command lane Internal VREF Enable - PSU_DDR_PHY_IOVCR0_ACREFEEN 0x0 + * Clock gating for AC D slices [47:24] + * PSU_DDR_PHY_ACIOCR4_ACCLKGATE1 0x0 - Address/command lane Single-End VREF Enable - PSU_DDR_PHY_IOVCR0_ACREFSEN 0x1 + * AC I/O Configuration Register 4 + * (OFFSET, MASK, VALUE) (0XFD080510, 0xFFFFFFFFU ,0x0A000000U) + */ + PSU_Mask_Write(DDR_PHY_ACIOCR4_OFFSET, 0xFFFFFFFFU, 0x0A000000U); +/*##################################################################### */ - Address/command lane Internal VREF Enable - PSU_DDR_PHY_IOVCR0_ACREFIEN 0x1 + /* + * Register : IOVCR0 @ 0XFD080520 - External VREF generato REFSEL range select - PSU_DDR_PHY_IOVCR0_ACREFESELRANGE 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_IOVCR0_RESERVED_31_29 0x0 - Address/command lane External VREF Select - PSU_DDR_PHY_IOVCR0_ACREFESEL 0x0 + * Address/command lane VREF Pad Enable + * PSU_DDR_PHY_IOVCR0_ACREFPEN 0x0 - Single ended VREF generator REFSEL range select - PSU_DDR_PHY_IOVCR0_ACREFSSELRANGE 0x1 + * Address/command lane Internal VREF Enable + * PSU_DDR_PHY_IOVCR0_ACREFEEN 0x0 - Address/command lane Single-End VREF Select - PSU_DDR_PHY_IOVCR0_ACREFSSEL 0x30 + * Address/command lane Single-End VREF Enable + * PSU_DDR_PHY_IOVCR0_ACREFSEN 0x1 - Internal VREF generator REFSEL ragne select - PSU_DDR_PHY_IOVCR0_ACVREFISELRANGE 0x1 + * Address/command lane Internal VREF Enable + * PSU_DDR_PHY_IOVCR0_ACREFIEN 0x1 - REFSEL Control for internal AC IOs - PSU_DDR_PHY_IOVCR0_ACVREFISEL 0x30 + * External VREF generato REFSEL range select + * PSU_DDR_PHY_IOVCR0_ACREFESELRANGE 0x0 - IO VREF Control Register 0 - (OFFSET, MASK, VALUE) (0XFD080520, 0xFFFFFFFFU ,0x0300B0B0U) - RegMask = (DDR_PHY_IOVCR0_RESERVED_31_29_MASK | DDR_PHY_IOVCR0_ACREFPEN_MASK | DDR_PHY_IOVCR0_ACREFEEN_MASK | DDR_PHY_IOVCR0_ACREFSEN_MASK | DDR_PHY_IOVCR0_ACREFIEN_MASK | DDR_PHY_IOVCR0_ACREFESELRANGE_MASK | DDR_PHY_IOVCR0_ACREFESEL_MASK | DDR_PHY_IOVCR0_ACREFSSELRANGE_MASK | DDR_PHY_IOVCR0_ACREFSSEL_MASK | DDR_PHY_IOVCR0_ACVREFISELRANGE_MASK | DDR_PHY_IOVCR0_ACVREFISEL_MASK | 0 ); + * Address/command lane External VREF Select + * PSU_DDR_PHY_IOVCR0_ACREFESEL 0x0 - RegVal = ((0x00000000U << DDR_PHY_IOVCR0_RESERVED_31_29_SHIFT - | 0x00000000U << DDR_PHY_IOVCR0_ACREFPEN_SHIFT - | 0x00000000U << DDR_PHY_IOVCR0_ACREFEEN_SHIFT - | 0x00000001U << DDR_PHY_IOVCR0_ACREFSEN_SHIFT - | 0x00000001U << DDR_PHY_IOVCR0_ACREFIEN_SHIFT - | 0x00000000U << DDR_PHY_IOVCR0_ACREFESELRANGE_SHIFT - | 0x00000000U << DDR_PHY_IOVCR0_ACREFESEL_SHIFT - | 0x00000001U << DDR_PHY_IOVCR0_ACREFSSELRANGE_SHIFT - | 0x00000030U << DDR_PHY_IOVCR0_ACREFSSEL_SHIFT - | 0x00000001U << DDR_PHY_IOVCR0_ACVREFISELRANGE_SHIFT - | 0x00000030U << DDR_PHY_IOVCR0_ACVREFISEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_IOVCR0_OFFSET ,0xFFFFFFFFU ,0x0300B0B0U); - /*############################################################################################################################ */ + * Single ended VREF generator REFSEL range select + * PSU_DDR_PHY_IOVCR0_ACREFSSELRANGE 0x1 - /*Register : VTCR0 @ 0XFD080528

+ * Address/command lane Single-End VREF Select + * PSU_DDR_PHY_IOVCR0_ACREFSSEL 0x30 - Number of ctl_clk required to meet (> 150ns) timing requirements during DRAM DQ VREF training - PSU_DDR_PHY_VTCR0_TVREF 0x7 + * Internal VREF generator REFSEL ragne select + * PSU_DDR_PHY_IOVCR0_ACVREFISELRANGE 0x1 - DRM DQ VREF training Enable - PSU_DDR_PHY_VTCR0_DVEN 0x1 + * REFSEL Control for internal AC IOs + * PSU_DDR_PHY_IOVCR0_ACVREFISEL 0x4e - Per Device Addressability Enable - PSU_DDR_PHY_VTCR0_PDAEN 0x1 + * IO VREF Control Register 0 + * (OFFSET, MASK, VALUE) (0XFD080520, 0xFFFFFFFFU ,0x0300B0CEU) + */ + PSU_Mask_Write(DDR_PHY_IOVCR0_OFFSET, 0xFFFFFFFFU, 0x0300B0CEU); +/*##################################################################### */ - Reserved. Returns zeroes on reads. - PSU_DDR_PHY_VTCR0_RESERVED_26 0x0 + /* + * Register : VTCR0 @ 0XFD080528 - VREF Word Count - PSU_DDR_PHY_VTCR0_VWCR 0x4 + * Number of ctl_clk required to meet (> 150ns) timing requirements during + * DRAM DQ VREF training + * PSU_DDR_PHY_VTCR0_TVREF 0x7 - DRAM DQ VREF step size used during DRAM VREF training - PSU_DDR_PHY_VTCR0_DVSS 0x0 + * DRM DQ VREF training Enable + * PSU_DDR_PHY_VTCR0_DVEN 0x1 - Maximum VREF limit value used during DRAM VREF training - PSU_DDR_PHY_VTCR0_DVMAX 0x32 + * Per Device Addressability Enable + * PSU_DDR_PHY_VTCR0_PDAEN 0x1 - Minimum VREF limit value used during DRAM VREF training - PSU_DDR_PHY_VTCR0_DVMIN 0x0 + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_VTCR0_RESERVED_26 0x0 - Initial DRAM DQ VREF value used during DRAM VREF training - PSU_DDR_PHY_VTCR0_DVINIT 0x19 + * VREF Word Count + * PSU_DDR_PHY_VTCR0_VWCR 0x4 - VREF Training Control Register 0 - (OFFSET, MASK, VALUE) (0XFD080528, 0xFFFFFFFFU ,0xF9032019U) - RegMask = (DDR_PHY_VTCR0_TVREF_MASK | DDR_PHY_VTCR0_DVEN_MASK | DDR_PHY_VTCR0_PDAEN_MASK | DDR_PHY_VTCR0_RESERVED_26_MASK | DDR_PHY_VTCR0_VWCR_MASK | DDR_PHY_VTCR0_DVSS_MASK | DDR_PHY_VTCR0_DVMAX_MASK | DDR_PHY_VTCR0_DVMIN_MASK | DDR_PHY_VTCR0_DVINIT_MASK | 0 ); + * DRAM DQ VREF step size used during DRAM VREF training + * PSU_DDR_PHY_VTCR0_DVSS 0x0 - RegVal = ((0x00000007U << DDR_PHY_VTCR0_TVREF_SHIFT - | 0x00000001U << DDR_PHY_VTCR0_DVEN_SHIFT - | 0x00000001U << DDR_PHY_VTCR0_PDAEN_SHIFT - | 0x00000000U << DDR_PHY_VTCR0_RESERVED_26_SHIFT - | 0x00000004U << DDR_PHY_VTCR0_VWCR_SHIFT - | 0x00000000U << DDR_PHY_VTCR0_DVSS_SHIFT - | 0x00000032U << DDR_PHY_VTCR0_DVMAX_SHIFT - | 0x00000000U << DDR_PHY_VTCR0_DVMIN_SHIFT - | 0x00000019U << DDR_PHY_VTCR0_DVINIT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_VTCR0_OFFSET ,0xFFFFFFFFU ,0xF9032019U); - /*############################################################################################################################ */ + * Maximum VREF limit value used during DRAM VREF training + * PSU_DDR_PHY_VTCR0_DVMAX 0x32 - /*Register : VTCR1 @ 0XFD08052C

+ * Minimum VREF limit value used during DRAM VREF training + * PSU_DDR_PHY_VTCR0_DVMIN 0x0 - Host VREF step size used during VREF training. The register value of N indicates step size of (N+1) - PSU_DDR_PHY_VTCR1_HVSS 0x0 + * Initial DRAM DQ VREF value used during DRAM VREF training + * PSU_DDR_PHY_VTCR0_DVINIT 0x19 - Reserved. Returns zeroes on reads. - PSU_DDR_PHY_VTCR1_RESERVED_27 0x0 + * VREF Training Control Register 0 + * (OFFSET, MASK, VALUE) (0XFD080528, 0xFFFFFFFFU ,0xF9032019U) + */ + PSU_Mask_Write(DDR_PHY_VTCR0_OFFSET, 0xFFFFFFFFU, 0xF9032019U); +/*##################################################################### */ - Maximum VREF limit value used during DRAM VREF training. - PSU_DDR_PHY_VTCR1_HVMAX 0x7f + /* + * Register : VTCR1 @ 0XFD08052C - Reserved. Returns zeroes on reads. - PSU_DDR_PHY_VTCR1_RESERVED_19 0x0 + * Host VREF step size used during VREF training. The register value of N i + * ndicates step size of (N+1) + * PSU_DDR_PHY_VTCR1_HVSS 0x0 - Minimum VREF limit value used during DRAM VREF training. - PSU_DDR_PHY_VTCR1_HVMIN 0x0 + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_VTCR1_RESERVED_27 0x0 - Reserved. Returns zeroes on reads. - PSU_DDR_PHY_VTCR1_RESERVED_11 0x0 + * Maximum VREF limit value used during DRAM VREF training. + * PSU_DDR_PHY_VTCR1_HVMAX 0x7f - Static Host Vref Rank Value - PSU_DDR_PHY_VTCR1_SHRNK 0x0 + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_VTCR1_RESERVED_19 0x0 - Static Host Vref Rank Enable - PSU_DDR_PHY_VTCR1_SHREN 0x1 + * Minimum VREF limit value used during DRAM VREF training. + * PSU_DDR_PHY_VTCR1_HVMIN 0x0 - Number of ctl_clk required to meet (> 200ns) VREF Settling timing requirements during Host IO VREF training - PSU_DDR_PHY_VTCR1_TVREFIO 0x7 + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_VTCR1_RESERVED_11 0x0 - Eye LCDL Offset value for VREF training - PSU_DDR_PHY_VTCR1_EOFF 0x0 + * Static Host Vref Rank Value + * PSU_DDR_PHY_VTCR1_SHRNK 0x0 - Number of LCDL Eye points for which VREF training is repeated - PSU_DDR_PHY_VTCR1_ENUM 0x0 + * Static Host Vref Rank Enable + * PSU_DDR_PHY_VTCR1_SHREN 0x1 - HOST (IO) internal VREF training Enable - PSU_DDR_PHY_VTCR1_HVEN 0x1 + * Number of ctl_clk required to meet (> 200ns) VREF Settling timing requir + * ements during Host IO VREF training + * PSU_DDR_PHY_VTCR1_TVREFIO 0x7 - Host IO Type Control - PSU_DDR_PHY_VTCR1_HVIO 0x1 + * Eye LCDL Offset value for VREF training + * PSU_DDR_PHY_VTCR1_EOFF 0x0 - VREF Training Control Register 1 - (OFFSET, MASK, VALUE) (0XFD08052C, 0xFFFFFFFFU ,0x07F001E3U) - RegMask = (DDR_PHY_VTCR1_HVSS_MASK | DDR_PHY_VTCR1_RESERVED_27_MASK | DDR_PHY_VTCR1_HVMAX_MASK | DDR_PHY_VTCR1_RESERVED_19_MASK | DDR_PHY_VTCR1_HVMIN_MASK | DDR_PHY_VTCR1_RESERVED_11_MASK | DDR_PHY_VTCR1_SHRNK_MASK | DDR_PHY_VTCR1_SHREN_MASK | DDR_PHY_VTCR1_TVREFIO_MASK | DDR_PHY_VTCR1_EOFF_MASK | DDR_PHY_VTCR1_ENUM_MASK | DDR_PHY_VTCR1_HVEN_MASK | DDR_PHY_VTCR1_HVIO_MASK | 0 ); + * Number of LCDL Eye points for which VREF training is repeated + * PSU_DDR_PHY_VTCR1_ENUM 0x0 - RegVal = ((0x00000000U << DDR_PHY_VTCR1_HVSS_SHIFT - | 0x00000000U << DDR_PHY_VTCR1_RESERVED_27_SHIFT - | 0x0000007FU << DDR_PHY_VTCR1_HVMAX_SHIFT - | 0x00000000U << DDR_PHY_VTCR1_RESERVED_19_SHIFT - | 0x00000000U << DDR_PHY_VTCR1_HVMIN_SHIFT - | 0x00000000U << DDR_PHY_VTCR1_RESERVED_11_SHIFT - | 0x00000000U << DDR_PHY_VTCR1_SHRNK_SHIFT - | 0x00000001U << DDR_PHY_VTCR1_SHREN_SHIFT - | 0x00000007U << DDR_PHY_VTCR1_TVREFIO_SHIFT - | 0x00000000U << DDR_PHY_VTCR1_EOFF_SHIFT - | 0x00000000U << DDR_PHY_VTCR1_ENUM_SHIFT - | 0x00000001U << DDR_PHY_VTCR1_HVEN_SHIFT - | 0x00000001U << DDR_PHY_VTCR1_HVIO_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_VTCR1_OFFSET ,0xFFFFFFFFU ,0x07F001E3U); - /*############################################################################################################################ */ + * HOST (IO) internal VREF training Enable + * PSU_DDR_PHY_VTCR1_HVEN 0x1 - /*Register : ACBDLR1 @ 0XFD080544

+ * Host IO Type Control + * PSU_DDR_PHY_VTCR1_HVIO 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR1_RESERVED_31_30 0x0 + * VREF Training Control Register 1 + * (OFFSET, MASK, VALUE) (0XFD08052C, 0xFFFFFFFFU ,0x07F001E3U) + */ + PSU_Mask_Write(DDR_PHY_VTCR1_OFFSET, 0xFFFFFFFFU, 0x07F001E3U); +/*##################################################################### */ - Delay select for the BDL on Parity. - PSU_DDR_PHY_ACBDLR1_PARBD 0x0 + /* + * Register : ACBDLR1 @ 0XFD080544 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR1_RESERVED_23_22 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR1_RESERVED_31_30 0x0 - Delay select for the BDL on Address A[16]. In DDR3 mode this pin is connected to WE. - PSU_DDR_PHY_ACBDLR1_A16BD 0x0 + * Delay select for the BDL on Parity. + * PSU_DDR_PHY_ACBDLR1_PARBD 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR1_RESERVED_15_14 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR1_RESERVED_23_22 0x0 - Delay select for the BDL on Address A[17]. When not in DDR4 modemode this pin is connected to CAS. - PSU_DDR_PHY_ACBDLR1_A17BD 0x0 + * Delay select for the BDL on Address A[16]. In DDR3 mode this pin is conn + * ected to WE. + * PSU_DDR_PHY_ACBDLR1_A16BD 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR1_RESERVED_7_6 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR1_RESERVED_15_14 0x0 - Delay select for the BDL on ACTN. - PSU_DDR_PHY_ACBDLR1_ACTBD 0x0 + * Delay select for the BDL on Address A[17]. When not in DDR4 modemode thi + * s pin is connected to CAS. + * PSU_DDR_PHY_ACBDLR1_A17BD 0x0 - AC Bit Delay Line Register 1 - (OFFSET, MASK, VALUE) (0XFD080544, 0xFFFFFFFFU ,0x00000000U) - RegMask = (DDR_PHY_ACBDLR1_RESERVED_31_30_MASK | DDR_PHY_ACBDLR1_PARBD_MASK | DDR_PHY_ACBDLR1_RESERVED_23_22_MASK | DDR_PHY_ACBDLR1_A16BD_MASK | DDR_PHY_ACBDLR1_RESERVED_15_14_MASK | DDR_PHY_ACBDLR1_A17BD_MASK | DDR_PHY_ACBDLR1_RESERVED_7_6_MASK | DDR_PHY_ACBDLR1_ACTBD_MASK | 0 ); + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR1_RESERVED_7_6 0x0 - RegVal = ((0x00000000U << DDR_PHY_ACBDLR1_RESERVED_31_30_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR1_PARBD_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR1_RESERVED_23_22_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR1_A16BD_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR1_RESERVED_15_14_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR1_A17BD_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR1_RESERVED_7_6_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR1_ACTBD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_ACBDLR1_OFFSET ,0xFFFFFFFFU ,0x00000000U); - /*############################################################################################################################ */ + * Delay select for the BDL on ACTN. + * PSU_DDR_PHY_ACBDLR1_ACTBD 0x0 - /*Register : ACBDLR2 @ 0XFD080548

+ * AC Bit Delay Line Register 1 + * (OFFSET, MASK, VALUE) (0XFD080544, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDR_PHY_ACBDLR1_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR2_RESERVED_31_30 0x0 + /* + * Register : ACBDLR2 @ 0XFD080548 - Delay select for the BDL on BG[1]. - PSU_DDR_PHY_ACBDLR2_BG1BD 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR2_RESERVED_31_30 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR2_RESERVED_23_22 0x0 + * Delay select for the BDL on BG[1]. + * PSU_DDR_PHY_ACBDLR2_BG1BD 0x0 - Delay select for the BDL on BG[0]. - PSU_DDR_PHY_ACBDLR2_BG0BD 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR2_RESERVED_23_22 0x0 - Reser.ved Return zeroes on reads. - PSU_DDR_PHY_ACBDLR2_RESERVED_15_14 0x0 + * Delay select for the BDL on BG[0]. + * PSU_DDR_PHY_ACBDLR2_BG0BD 0x0 - Delay select for the BDL on BA[1]. - PSU_DDR_PHY_ACBDLR2_BA1BD 0x0 + * Reser.ved Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR2_RESERVED_15_14 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR2_RESERVED_7_6 0x0 + * Delay select for the BDL on BA[1]. + * PSU_DDR_PHY_ACBDLR2_BA1BD 0x0 - Delay select for the BDL on BA[0]. - PSU_DDR_PHY_ACBDLR2_BA0BD 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR2_RESERVED_7_6 0x0 - AC Bit Delay Line Register 2 - (OFFSET, MASK, VALUE) (0XFD080548, 0xFFFFFFFFU ,0x00000000U) - RegMask = (DDR_PHY_ACBDLR2_RESERVED_31_30_MASK | DDR_PHY_ACBDLR2_BG1BD_MASK | DDR_PHY_ACBDLR2_RESERVED_23_22_MASK | DDR_PHY_ACBDLR2_BG0BD_MASK | DDR_PHY_ACBDLR2_RESERVED_15_14_MASK | DDR_PHY_ACBDLR2_BA1BD_MASK | DDR_PHY_ACBDLR2_RESERVED_7_6_MASK | DDR_PHY_ACBDLR2_BA0BD_MASK | 0 ); + * Delay select for the BDL on BA[0]. + * PSU_DDR_PHY_ACBDLR2_BA0BD 0x0 - RegVal = ((0x00000000U << DDR_PHY_ACBDLR2_RESERVED_31_30_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR2_BG1BD_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR2_RESERVED_23_22_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR2_BG0BD_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR2_RESERVED_15_14_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR2_BA1BD_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR2_RESERVED_7_6_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR2_BA0BD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_ACBDLR2_OFFSET ,0xFFFFFFFFU ,0x00000000U); - /*############################################################################################################################ */ + * AC Bit Delay Line Register 2 + * (OFFSET, MASK, VALUE) (0XFD080548, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDR_PHY_ACBDLR2_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ - /*Register : ACBDLR6 @ 0XFD080558

+ /* + * Register : ACBDLR6 @ 0XFD080558 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR6_RESERVED_31_30 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR6_RESERVED_31_30 0x0 - Delay select for the BDL on Address A[3]. - PSU_DDR_PHY_ACBDLR6_A03BD 0x0 + * Delay select for the BDL on Address A[3]. + * PSU_DDR_PHY_ACBDLR6_A03BD 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR6_RESERVED_23_22 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR6_RESERVED_23_22 0x0 - Delay select for the BDL on Address A[2]. - PSU_DDR_PHY_ACBDLR6_A02BD 0x0 + * Delay select for the BDL on Address A[2]. + * PSU_DDR_PHY_ACBDLR6_A02BD 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR6_RESERVED_15_14 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR6_RESERVED_15_14 0x0 - Delay select for the BDL on Address A[1]. - PSU_DDR_PHY_ACBDLR6_A01BD 0x0 + * Delay select for the BDL on Address A[1]. + * PSU_DDR_PHY_ACBDLR6_A01BD 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR6_RESERVED_7_6 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR6_RESERVED_7_6 0x0 - Delay select for the BDL on Address A[0]. - PSU_DDR_PHY_ACBDLR6_A00BD 0x0 + * Delay select for the BDL on Address A[0]. + * PSU_DDR_PHY_ACBDLR6_A00BD 0x0 - AC Bit Delay Line Register 6 - (OFFSET, MASK, VALUE) (0XFD080558, 0xFFFFFFFFU ,0x00000000U) - RegMask = (DDR_PHY_ACBDLR6_RESERVED_31_30_MASK | DDR_PHY_ACBDLR6_A03BD_MASK | DDR_PHY_ACBDLR6_RESERVED_23_22_MASK | DDR_PHY_ACBDLR6_A02BD_MASK | DDR_PHY_ACBDLR6_RESERVED_15_14_MASK | DDR_PHY_ACBDLR6_A01BD_MASK | DDR_PHY_ACBDLR6_RESERVED_7_6_MASK | DDR_PHY_ACBDLR6_A00BD_MASK | 0 ); + * AC Bit Delay Line Register 6 + * (OFFSET, MASK, VALUE) (0XFD080558, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDR_PHY_ACBDLR6_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ - RegVal = ((0x00000000U << DDR_PHY_ACBDLR6_RESERVED_31_30_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR6_A03BD_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR6_RESERVED_23_22_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR6_A02BD_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR6_RESERVED_15_14_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR6_A01BD_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR6_RESERVED_7_6_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR6_A00BD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_ACBDLR6_OFFSET ,0xFFFFFFFFU ,0x00000000U); - /*############################################################################################################################ */ + /* + * Register : ACBDLR7 @ 0XFD08055C - /*Register : ACBDLR7 @ 0XFD08055C

+ * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR7_RESERVED_31_30 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR7_RESERVED_31_30 0x0 + * Delay select for the BDL on Address A[7]. + * PSU_DDR_PHY_ACBDLR7_A07BD 0x0 - Delay select for the BDL on Address A[7]. - PSU_DDR_PHY_ACBDLR7_A07BD 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR7_RESERVED_23_22 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR7_RESERVED_23_22 0x0 + * Delay select for the BDL on Address A[6]. + * PSU_DDR_PHY_ACBDLR7_A06BD 0x0 - Delay select for the BDL on Address A[6]. - PSU_DDR_PHY_ACBDLR7_A06BD 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR7_RESERVED_15_14 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR7_RESERVED_15_14 0x0 + * Delay select for the BDL on Address A[5]. + * PSU_DDR_PHY_ACBDLR7_A05BD 0x0 - Delay select for the BDL on Address A[5]. - PSU_DDR_PHY_ACBDLR7_A05BD 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR7_RESERVED_7_6 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR7_RESERVED_7_6 0x0 + * Delay select for the BDL on Address A[4]. + * PSU_DDR_PHY_ACBDLR7_A04BD 0x0 - Delay select for the BDL on Address A[4]. - PSU_DDR_PHY_ACBDLR7_A04BD 0x0 + * AC Bit Delay Line Register 7 + * (OFFSET, MASK, VALUE) (0XFD08055C, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDR_PHY_ACBDLR7_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ - AC Bit Delay Line Register 7 - (OFFSET, MASK, VALUE) (0XFD08055C, 0xFFFFFFFFU ,0x00000000U) - RegMask = (DDR_PHY_ACBDLR7_RESERVED_31_30_MASK | DDR_PHY_ACBDLR7_A07BD_MASK | DDR_PHY_ACBDLR7_RESERVED_23_22_MASK | DDR_PHY_ACBDLR7_A06BD_MASK | DDR_PHY_ACBDLR7_RESERVED_15_14_MASK | DDR_PHY_ACBDLR7_A05BD_MASK | DDR_PHY_ACBDLR7_RESERVED_7_6_MASK | DDR_PHY_ACBDLR7_A04BD_MASK | 0 ); + /* + * Register : ACBDLR8 @ 0XFD080560 - RegVal = ((0x00000000U << DDR_PHY_ACBDLR7_RESERVED_31_30_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR7_A07BD_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR7_RESERVED_23_22_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR7_A06BD_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR7_RESERVED_15_14_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR7_A05BD_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR7_RESERVED_7_6_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR7_A04BD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_ACBDLR7_OFFSET ,0xFFFFFFFFU ,0x00000000U); - /*############################################################################################################################ */ + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR8_RESERVED_31_30 0x0 - /*Register : ACBDLR8 @ 0XFD080560

+ * Delay select for the BDL on Address A[11]. + * PSU_DDR_PHY_ACBDLR8_A11BD 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR8_RESERVED_31_30 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR8_RESERVED_23_22 0x0 - Delay select for the BDL on Address A[11]. - PSU_DDR_PHY_ACBDLR8_A11BD 0x0 + * Delay select for the BDL on Address A[10]. + * PSU_DDR_PHY_ACBDLR8_A10BD 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR8_RESERVED_23_22 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR8_RESERVED_15_14 0x0 - Delay select for the BDL on Address A[10]. - PSU_DDR_PHY_ACBDLR8_A10BD 0x0 + * Delay select for the BDL on Address A[9]. + * PSU_DDR_PHY_ACBDLR8_A09BD 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR8_RESERVED_15_14 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR8_RESERVED_7_6 0x0 - Delay select for the BDL on Address A[9]. - PSU_DDR_PHY_ACBDLR8_A09BD 0x0 + * Delay select for the BDL on Address A[8]. + * PSU_DDR_PHY_ACBDLR8_A08BD 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR8_RESERVED_7_6 0x0 + * AC Bit Delay Line Register 8 + * (OFFSET, MASK, VALUE) (0XFD080560, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDR_PHY_ACBDLR8_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ - Delay select for the BDL on Address A[8]. - PSU_DDR_PHY_ACBDLR8_A08BD 0x0 + /* + * Register : ACBDLR9 @ 0XFD080564 - AC Bit Delay Line Register 8 - (OFFSET, MASK, VALUE) (0XFD080560, 0xFFFFFFFFU ,0x00000000U) - RegMask = (DDR_PHY_ACBDLR8_RESERVED_31_30_MASK | DDR_PHY_ACBDLR8_A11BD_MASK | DDR_PHY_ACBDLR8_RESERVED_23_22_MASK | DDR_PHY_ACBDLR8_A10BD_MASK | DDR_PHY_ACBDLR8_RESERVED_15_14_MASK | DDR_PHY_ACBDLR8_A09BD_MASK | DDR_PHY_ACBDLR8_RESERVED_7_6_MASK | DDR_PHY_ACBDLR8_A08BD_MASK | 0 ); + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR9_RESERVED_31_30 0x0 - RegVal = ((0x00000000U << DDR_PHY_ACBDLR8_RESERVED_31_30_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR8_A11BD_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR8_RESERVED_23_22_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR8_A10BD_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR8_RESERVED_15_14_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR8_A09BD_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR8_RESERVED_7_6_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR8_A08BD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_ACBDLR8_OFFSET ,0xFFFFFFFFU ,0x00000000U); - /*############################################################################################################################ */ + * Delay select for the BDL on Address A[15]. + * PSU_DDR_PHY_ACBDLR9_A15BD 0x0 - /*Register : ACBDLR9 @ 0XFD080564

+ * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR9_RESERVED_23_22 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR9_RESERVED_31_30 0x0 + * Delay select for the BDL on Address A[14]. + * PSU_DDR_PHY_ACBDLR9_A14BD 0x0 - Delay select for the BDL on Address A[15]. - PSU_DDR_PHY_ACBDLR9_A15BD 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR9_RESERVED_15_14 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR9_RESERVED_23_22 0x0 + * Delay select for the BDL on Address A[13]. + * PSU_DDR_PHY_ACBDLR9_A13BD 0x0 - Delay select for the BDL on Address A[14]. - PSU_DDR_PHY_ACBDLR9_A14BD 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR9_RESERVED_7_6 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR9_RESERVED_15_14 0x0 + * Delay select for the BDL on Address A[12]. + * PSU_DDR_PHY_ACBDLR9_A12BD 0x0 - Delay select for the BDL on Address A[13]. - PSU_DDR_PHY_ACBDLR9_A13BD 0x0 + * AC Bit Delay Line Register 9 + * (OFFSET, MASK, VALUE) (0XFD080564, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDR_PHY_ACBDLR9_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR9_RESERVED_7_6 0x0 + /* + * Register : ZQCR @ 0XFD080680 - Delay select for the BDL on Address A[12]. - PSU_DDR_PHY_ACBDLR9_A12BD 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ZQCR_RESERVED_31_26 0x0 - AC Bit Delay Line Register 9 - (OFFSET, MASK, VALUE) (0XFD080564, 0xFFFFFFFFU ,0x00000000U) - RegMask = (DDR_PHY_ACBDLR9_RESERVED_31_30_MASK | DDR_PHY_ACBDLR9_A15BD_MASK | DDR_PHY_ACBDLR9_RESERVED_23_22_MASK | DDR_PHY_ACBDLR9_A14BD_MASK | DDR_PHY_ACBDLR9_RESERVED_15_14_MASK | DDR_PHY_ACBDLR9_A13BD_MASK | DDR_PHY_ACBDLR9_RESERVED_7_6_MASK | DDR_PHY_ACBDLR9_A12BD_MASK | 0 ); + * ZQ VREF Range + * PSU_DDR_PHY_ZQCR_ZQREFISELRANGE 0x0 - RegVal = ((0x00000000U << DDR_PHY_ACBDLR9_RESERVED_31_30_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR9_A15BD_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR9_RESERVED_23_22_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR9_A14BD_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR9_RESERVED_15_14_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR9_A13BD_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR9_RESERVED_7_6_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR9_A12BD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_ACBDLR9_OFFSET ,0xFFFFFFFFU ,0x00000000U); - /*############################################################################################################################ */ + * Programmable Wait for Frequency B + * PSU_DDR_PHY_ZQCR_PGWAIT_FRQB 0x11 - /*Register : ZQCR @ 0XFD080680

+ * Programmable Wait for Frequency A + * PSU_DDR_PHY_ZQCR_PGWAIT_FRQA 0x15 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ZQCR_RESERVED_31_26 0x0 + * ZQ VREF Pad Enable + * PSU_DDR_PHY_ZQCR_ZQREFPEN 0x0 - ZQ VREF Range - PSU_DDR_PHY_ZQCR_ZQREFISELRANGE 0x0 + * ZQ Internal VREF Enable + * PSU_DDR_PHY_ZQCR_ZQREFIEN 0x1 - Programmable Wait for Frequency B - PSU_DDR_PHY_ZQCR_PGWAIT_FRQB 0x11 + * Choice of termination mode + * PSU_DDR_PHY_ZQCR_ODT_MODE 0x1 - Programmable Wait for Frequency A - PSU_DDR_PHY_ZQCR_PGWAIT_FRQA 0x11 + * Force ZCAL VT update + * PSU_DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE 0x0 - ZQ VREF Pad Enable - PSU_DDR_PHY_ZQCR_ZQREFPEN 0x0 + * IO VT Drift Limit + * PSU_DDR_PHY_ZQCR_IODLMT 0x2 - ZQ Internal VREF Enable - PSU_DDR_PHY_ZQCR_ZQREFIEN 0x1 + * Averaging algorithm enable, if set, enables averaging algorithm + * PSU_DDR_PHY_ZQCR_AVGEN 0x1 - Choice of termination mode - PSU_DDR_PHY_ZQCR_ODT_MODE 0x1 + * Maximum number of averaging rounds to be used by averaging algorithm + * PSU_DDR_PHY_ZQCR_AVGMAX 0x2 - Force ZCAL VT update - PSU_DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE 0x0 + * ZQ Calibration Type + * PSU_DDR_PHY_ZQCR_ZCALT 0x0 - IO VT Drift Limit - PSU_DDR_PHY_ZQCR_IODLMT 0x2 + * ZQ Power Down + * PSU_DDR_PHY_ZQCR_ZQPD 0x0 - Averaging algorithm enable, if set, enables averaging algorithm - PSU_DDR_PHY_ZQCR_AVGEN 0x1 + * ZQ Impedance Control Register + * (OFFSET, MASK, VALUE) (0XFD080680, 0xFFFFFFFFU ,0x008AAA58U) + */ + PSU_Mask_Write(DDR_PHY_ZQCR_OFFSET, 0xFFFFFFFFU, 0x008AAA58U); +/*##################################################################### */ - Maximum number of averaging rounds to be used by averaging algorithm - PSU_DDR_PHY_ZQCR_AVGMAX 0x2 + /* + * Register : ZQ0PR0 @ 0XFD080684 - ZQ Calibration Type - PSU_DDR_PHY_ZQCR_ZCALT 0x0 + * Pull-down drive strength ZCTRL over-ride enable + * PSU_DDR_PHY_ZQ0PR0_PD_DRV_ZDEN 0x0 - ZQ Power Down - PSU_DDR_PHY_ZQCR_ZQPD 0x0 + * Pull-up drive strength ZCTRL over-ride enable + * PSU_DDR_PHY_ZQ0PR0_PU_DRV_ZDEN 0x0 - ZQ Impedance Control Register - (OFFSET, MASK, VALUE) (0XFD080680, 0xFFFFFFFFU ,0x008A2A58U) - RegMask = (DDR_PHY_ZQCR_RESERVED_31_26_MASK | DDR_PHY_ZQCR_ZQREFISELRANGE_MASK | DDR_PHY_ZQCR_PGWAIT_FRQB_MASK | DDR_PHY_ZQCR_PGWAIT_FRQA_MASK | DDR_PHY_ZQCR_ZQREFPEN_MASK | DDR_PHY_ZQCR_ZQREFIEN_MASK | DDR_PHY_ZQCR_ODT_MODE_MASK | DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_MASK | DDR_PHY_ZQCR_IODLMT_MASK | DDR_PHY_ZQCR_AVGEN_MASK | DDR_PHY_ZQCR_AVGMAX_MASK | DDR_PHY_ZQCR_ZCALT_MASK | DDR_PHY_ZQCR_ZQPD_MASK | 0 ); + * Pull-down termination ZCTRL over-ride enable + * PSU_DDR_PHY_ZQ0PR0_PD_ODT_ZDEN 0x0 - RegVal = ((0x00000000U << DDR_PHY_ZQCR_RESERVED_31_26_SHIFT - | 0x00000000U << DDR_PHY_ZQCR_ZQREFISELRANGE_SHIFT - | 0x00000011U << DDR_PHY_ZQCR_PGWAIT_FRQB_SHIFT - | 0x00000011U << DDR_PHY_ZQCR_PGWAIT_FRQA_SHIFT - | 0x00000000U << DDR_PHY_ZQCR_ZQREFPEN_SHIFT - | 0x00000001U << DDR_PHY_ZQCR_ZQREFIEN_SHIFT - | 0x00000001U << DDR_PHY_ZQCR_ODT_MODE_SHIFT - | 0x00000000U << DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_SHIFT - | 0x00000002U << DDR_PHY_ZQCR_IODLMT_SHIFT - | 0x00000001U << DDR_PHY_ZQCR_AVGEN_SHIFT - | 0x00000002U << DDR_PHY_ZQCR_AVGMAX_SHIFT - | 0x00000000U << DDR_PHY_ZQCR_ZCALT_SHIFT - | 0x00000000U << DDR_PHY_ZQCR_ZQPD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_ZQCR_OFFSET ,0xFFFFFFFFU ,0x008A2A58U); - /*############################################################################################################################ */ + * Pull-up termination ZCTRL over-ride enable + * PSU_DDR_PHY_ZQ0PR0_PU_ODT_ZDEN 0x0 - /*Register : ZQ0PR0 @ 0XFD080684

+ * Calibration segment bypass + * PSU_DDR_PHY_ZQ0PR0_ZSEGBYP 0x0 - Pull-down drive strength ZCTRL over-ride enable - PSU_DDR_PHY_ZQ0PR0_PD_DRV_ZDEN 0x0 + * VREF latch mode controls the mode in which the ZLE pin of the PVREF cell + * is driven by the PUB + * PSU_DDR_PHY_ZQ0PR0_ZLE_MODE 0x0 - Pull-up drive strength ZCTRL over-ride enable - PSU_DDR_PHY_ZQ0PR0_PU_DRV_ZDEN 0x0 + * Termination adjustment + * PSU_DDR_PHY_ZQ0PR0_ODT_ADJUST 0x0 - Pull-down termination ZCTRL over-ride enable - PSU_DDR_PHY_ZQ0PR0_PD_ODT_ZDEN 0x0 + * Pulldown drive strength adjustment + * PSU_DDR_PHY_ZQ0PR0_PD_DRV_ADJUST 0x0 - Pull-up termination ZCTRL over-ride enable - PSU_DDR_PHY_ZQ0PR0_PU_ODT_ZDEN 0x0 + * Pullup drive strength adjustment + * PSU_DDR_PHY_ZQ0PR0_PU_DRV_ADJUST 0x0 - Calibration segment bypass - PSU_DDR_PHY_ZQ0PR0_ZSEGBYP 0x0 + * DRAM Impedance Divide Ratio + * PSU_DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT 0x7 - VREF latch mode controls the mode in which the ZLE pin of the PVREF cell is driven by the PUB - PSU_DDR_PHY_ZQ0PR0_ZLE_MODE 0x0 + * HOST Impedance Divide Ratio + * PSU_DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT 0x9 - Termination adjustment - PSU_DDR_PHY_ZQ0PR0_ODT_ADJUST 0x0 + * Impedance Divide Ratio (pulldown drive calibration during asymmetric dri + * ve strength calibration) + * PSU_DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD 0xd - Pulldown drive strength adjustment - PSU_DDR_PHY_ZQ0PR0_PD_DRV_ADJUST 0x0 + * Impedance Divide Ratio (pullup drive calibration during asymmetric drive + * strength calibration) + * PSU_DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU 0xd - Pullup drive strength adjustment - PSU_DDR_PHY_ZQ0PR0_PU_DRV_ADJUST 0x0 + * ZQ n Impedance Control Program Register 0 + * (OFFSET, MASK, VALUE) (0XFD080684, 0xFFFFFFFFU ,0x000079DDU) + */ + PSU_Mask_Write(DDR_PHY_ZQ0PR0_OFFSET, 0xFFFFFFFFU, 0x000079DDU); +/*##################################################################### */ - DRAM Impedance Divide Ratio - PSU_DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT 0x7 + /* + * Register : ZQ0OR0 @ 0XFD080694 - HOST Impedance Divide Ratio - PSU_DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT 0x7 + * Reserved. Return zeros on reads. + * PSU_DDR_PHY_ZQ0OR0_RESERVED_31_26 0x0 - Impedance Divide Ratio (pulldown drive calibration during asymmetric drive strength calibration) - PSU_DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD 0xd + * Override value for the pull-up output impedance + * PSU_DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD 0x1e1 - Impedance Divide Ratio (pullup drive calibration during asymmetric drive strength calibration) - PSU_DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU 0xd + * Reserved. Return zeros on reads. + * PSU_DDR_PHY_ZQ0OR0_RESERVED_15_10 0x0 - ZQ n Impedance Control Program Register 0 - (OFFSET, MASK, VALUE) (0XFD080684, 0xFFFFFFFFU ,0x000077DDU) - RegMask = (DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_MASK | DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_MASK | DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_MASK | DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_MASK | DDR_PHY_ZQ0PR0_ZSEGBYP_MASK | DDR_PHY_ZQ0PR0_ZLE_MODE_MASK | DDR_PHY_ZQ0PR0_ODT_ADJUST_MASK | DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_MASK | DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_MASK | DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_MASK | DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_MASK | DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_MASK | DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_MASK | 0 ); + * Override value for the pull-down output impedance + * PSU_DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD 0x210 - RegVal = ((0x00000000U << DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_SHIFT - | 0x00000000U << DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_SHIFT - | 0x00000000U << DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_SHIFT - | 0x00000000U << DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_SHIFT - | 0x00000000U << DDR_PHY_ZQ0PR0_ZSEGBYP_SHIFT - | 0x00000000U << DDR_PHY_ZQ0PR0_ZLE_MODE_SHIFT - | 0x00000000U << DDR_PHY_ZQ0PR0_ODT_ADJUST_SHIFT - | 0x00000000U << DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_SHIFT - | 0x00000000U << DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_SHIFT - | 0x00000007U << DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_SHIFT - | 0x00000007U << DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_SHIFT - | 0x0000000DU << DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_SHIFT - | 0x0000000DU << DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_ZQ0PR0_OFFSET ,0xFFFFFFFFU ,0x000077DDU); - /*############################################################################################################################ */ + * ZQ n Impedance Control Override Data Register 0 + * (OFFSET, MASK, VALUE) (0XFD080694, 0xFFFFFFFFU ,0x01E10210U) + */ + PSU_Mask_Write(DDR_PHY_ZQ0OR0_OFFSET, 0xFFFFFFFFU, 0x01E10210U); +/*##################################################################### */ - /*Register : ZQ0OR0 @ 0XFD080694

+ /* + * Register : ZQ0OR1 @ 0XFD080698 - Reserved. Return zeros on reads. - PSU_DDR_PHY_ZQ0OR0_RESERVED_31_26 0x0 + * Reserved. Return zeros on reads. + * PSU_DDR_PHY_ZQ0OR1_RESERVED_31_26 0x0 - Override value for the pull-up output impedance - PSU_DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD 0x1e1 + * Override value for the pull-up termination + * PSU_DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD 0x1e1 - Reserved. Return zeros on reads. - PSU_DDR_PHY_ZQ0OR0_RESERVED_15_10 0x0 + * Reserved. Return zeros on reads. + * PSU_DDR_PHY_ZQ0OR1_RESERVED_15_10 0x0 - Override value for the pull-down output impedance - PSU_DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD 0x210 + * Override value for the pull-down termination + * PSU_DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD 0x0 - ZQ n Impedance Control Override Data Register 0 - (OFFSET, MASK, VALUE) (0XFD080694, 0xFFFFFFFFU ,0x01E10210U) - RegMask = (DDR_PHY_ZQ0OR0_RESERVED_31_26_MASK | DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_MASK | DDR_PHY_ZQ0OR0_RESERVED_15_10_MASK | DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_MASK | 0 ); - - RegVal = ((0x00000000U << DDR_PHY_ZQ0OR0_RESERVED_31_26_SHIFT - | 0x000001E1U << DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_SHIFT - | 0x00000000U << DDR_PHY_ZQ0OR0_RESERVED_15_10_SHIFT - | 0x00000210U << DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_ZQ0OR0_OFFSET ,0xFFFFFFFFU ,0x01E10210U); - /*############################################################################################################################ */ + * ZQ n Impedance Control Override Data Register 1 + * (OFFSET, MASK, VALUE) (0XFD080698, 0xFFFFFFFFU ,0x01E10000U) + */ + PSU_Mask_Write(DDR_PHY_ZQ0OR1_OFFSET, 0xFFFFFFFFU, 0x01E10000U); +/*##################################################################### */ - /*Register : ZQ0OR1 @ 0XFD080698

+ /* + * Register : ZQ1PR0 @ 0XFD0806A4 - Reserved. Return zeros on reads. - PSU_DDR_PHY_ZQ0OR1_RESERVED_31_26 0x0 + * Pull-down drive strength ZCTRL over-ride enable + * PSU_DDR_PHY_ZQ1PR0_PD_DRV_ZDEN 0x0 - Override value for the pull-up termination - PSU_DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD 0x1e1 + * Pull-up drive strength ZCTRL over-ride enable + * PSU_DDR_PHY_ZQ1PR0_PU_DRV_ZDEN 0x0 - Reserved. Return zeros on reads. - PSU_DDR_PHY_ZQ0OR1_RESERVED_15_10 0x0 + * Pull-down termination ZCTRL over-ride enable + * PSU_DDR_PHY_ZQ1PR0_PD_ODT_ZDEN 0x0 - Override value for the pull-down termination - PSU_DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD 0x0 + * Pull-up termination ZCTRL over-ride enable + * PSU_DDR_PHY_ZQ1PR0_PU_ODT_ZDEN 0x0 - ZQ n Impedance Control Override Data Register 1 - (OFFSET, MASK, VALUE) (0XFD080698, 0xFFFFFFFFU ,0x01E10000U) - RegMask = (DDR_PHY_ZQ0OR1_RESERVED_31_26_MASK | DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_MASK | DDR_PHY_ZQ0OR1_RESERVED_15_10_MASK | DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_MASK | 0 ); + * Calibration segment bypass + * PSU_DDR_PHY_ZQ1PR0_ZSEGBYP 0x0 - RegVal = ((0x00000000U << DDR_PHY_ZQ0OR1_RESERVED_31_26_SHIFT - | 0x000001E1U << DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_SHIFT - | 0x00000000U << DDR_PHY_ZQ0OR1_RESERVED_15_10_SHIFT - | 0x00000000U << DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_ZQ0OR1_OFFSET ,0xFFFFFFFFU ,0x01E10000U); - /*############################################################################################################################ */ + * VREF latch mode controls the mode in which the ZLE pin of the PVREF cell + * is driven by the PUB + * PSU_DDR_PHY_ZQ1PR0_ZLE_MODE 0x0 - /*Register : ZQ1PR0 @ 0XFD0806A4

+ * Termination adjustment + * PSU_DDR_PHY_ZQ1PR0_ODT_ADJUST 0x0 - Pull-down drive strength ZCTRL over-ride enable - PSU_DDR_PHY_ZQ1PR0_PD_DRV_ZDEN 0x0 + * Pulldown drive strength adjustment + * PSU_DDR_PHY_ZQ1PR0_PD_DRV_ADJUST 0x1 - Pull-up drive strength ZCTRL over-ride enable - PSU_DDR_PHY_ZQ1PR0_PU_DRV_ZDEN 0x0 + * Pullup drive strength adjustment + * PSU_DDR_PHY_ZQ1PR0_PU_DRV_ADJUST 0x0 - Pull-down termination ZCTRL over-ride enable - PSU_DDR_PHY_ZQ1PR0_PD_ODT_ZDEN 0x0 + * DRAM Impedance Divide Ratio + * PSU_DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT 0x7 - Pull-up termination ZCTRL over-ride enable - PSU_DDR_PHY_ZQ1PR0_PU_ODT_ZDEN 0x0 + * HOST Impedance Divide Ratio + * PSU_DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT 0xb - Calibration segment bypass - PSU_DDR_PHY_ZQ1PR0_ZSEGBYP 0x0 + * Impedance Divide Ratio (pulldown drive calibration during asymmetric dri + * ve strength calibration) + * PSU_DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD 0xd - VREF latch mode controls the mode in which the ZLE pin of the PVREF cell is driven by the PUB - PSU_DDR_PHY_ZQ1PR0_ZLE_MODE 0x0 + * Impedance Divide Ratio (pullup drive calibration during asymmetric drive + * strength calibration) + * PSU_DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU 0xb - Termination adjustment - PSU_DDR_PHY_ZQ1PR0_ODT_ADJUST 0x0 + * ZQ n Impedance Control Program Register 0 + * (OFFSET, MASK, VALUE) (0XFD0806A4, 0xFFFFFFFFU ,0x00087BDBU) + */ + PSU_Mask_Write(DDR_PHY_ZQ1PR0_OFFSET, 0xFFFFFFFFU, 0x00087BDBU); +/*##################################################################### */ - Pulldown drive strength adjustment - PSU_DDR_PHY_ZQ1PR0_PD_DRV_ADJUST 0x1 + /* + * Register : DX0GCR0 @ 0XFD080700 - Pullup drive strength adjustment - PSU_DDR_PHY_ZQ1PR0_PU_DRV_ADJUST 0x0 + * Calibration Bypass + * PSU_DDR_PHY_DX0GCR0_CALBYP 0x0 - DRAM Impedance Divide Ratio - PSU_DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT 0x7 + * Master Delay Line Enable + * PSU_DDR_PHY_DX0GCR0_MDLEN 0x1 - HOST Impedance Divide Ratio - PSU_DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT 0xb + * Configurable ODT(TE) Phase Shift + * PSU_DDR_PHY_DX0GCR0_CODTSHFT 0x0 - Impedance Divide Ratio (pulldown drive calibration during asymmetric drive strength calibration) - PSU_DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD 0xd + * DQS Duty Cycle Correction + * PSU_DDR_PHY_DX0GCR0_DQSDCC 0x0 - Impedance Divide Ratio (pullup drive calibration during asymmetric drive strength calibration) - PSU_DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU 0xb + * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY + * PSU_DDR_PHY_DX0GCR0_RDDLY 0x8 - ZQ n Impedance Control Program Register 0 - (OFFSET, MASK, VALUE) (0XFD0806A4, 0xFFFFFFFFU ,0x00087BDBU) - RegMask = (DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_MASK | DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_MASK | DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_MASK | DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_MASK | DDR_PHY_ZQ1PR0_ZSEGBYP_MASK | DDR_PHY_ZQ1PR0_ZLE_MODE_MASK | DDR_PHY_ZQ1PR0_ODT_ADJUST_MASK | DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_MASK | DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_MASK | DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_MASK | DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_MASK | DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_MASK | DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_MASK | 0 ); + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX0GCR0_RESERVED_19_14 0x0 - RegVal = ((0x00000000U << DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_SHIFT - | 0x00000000U << DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_SHIFT - | 0x00000000U << DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_SHIFT - | 0x00000000U << DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_SHIFT - | 0x00000000U << DDR_PHY_ZQ1PR0_ZSEGBYP_SHIFT - | 0x00000000U << DDR_PHY_ZQ1PR0_ZLE_MODE_SHIFT - | 0x00000000U << DDR_PHY_ZQ1PR0_ODT_ADJUST_SHIFT - | 0x00000001U << DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_SHIFT - | 0x00000000U << DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_SHIFT - | 0x00000007U << DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_SHIFT - | 0x0000000BU << DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_SHIFT - | 0x0000000DU << DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_SHIFT - | 0x0000000BU << DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_ZQ1PR0_OFFSET ,0xFFFFFFFFU ,0x00087BDBU); - /*############################################################################################################################ */ + * DQSNSE Power Down Receiver + * PSU_DDR_PHY_DX0GCR0_DQSNSEPDR 0x0 - /*Register : DX0GCR0 @ 0XFD080700

+ * DQSSE Power Down Receiver + * PSU_DDR_PHY_DX0GCR0_DQSSEPDR 0x0 - Calibration Bypass - PSU_DDR_PHY_DX0GCR0_CALBYP 0x0 + * RTT On Additive Latency + * PSU_DDR_PHY_DX0GCR0_RTTOAL 0x0 - Master Delay Line Enable - PSU_DDR_PHY_DX0GCR0_MDLEN 0x1 + * RTT Output Hold + * PSU_DDR_PHY_DX0GCR0_RTTOH 0x3 - Configurable ODT(TE) Phase Shift - PSU_DDR_PHY_DX0GCR0_CODTSHFT 0x0 + * Configurable PDR Phase Shift + * PSU_DDR_PHY_DX0GCR0_CPDRSHFT 0x0 - DQS Duty Cycle Correction - PSU_DDR_PHY_DX0GCR0_DQSDCC 0x0 + * DQSR Power Down + * PSU_DDR_PHY_DX0GCR0_DQSRPD 0x0 - Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY - PSU_DDR_PHY_DX0GCR0_RDDLY 0x8 + * DQSG Power Down Receiver + * PSU_DDR_PHY_DX0GCR0_DQSGPDR 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX0GCR0_RESERVED_19_14 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX0GCR0_RESERVED_4 0x0 - DQSNSE Power Down Receiver - PSU_DDR_PHY_DX0GCR0_DQSNSEPDR 0x0 + * DQSG On-Die Termination + * PSU_DDR_PHY_DX0GCR0_DQSGODT 0x0 - DQSSE Power Down Receiver - PSU_DDR_PHY_DX0GCR0_DQSSEPDR 0x0 + * DQSG Output Enable + * PSU_DDR_PHY_DX0GCR0_DQSGOE 0x1 - RTT On Additive Latency - PSU_DDR_PHY_DX0GCR0_RTTOAL 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX0GCR0_RESERVED_1_0 0x0 - RTT Output Hold - PSU_DDR_PHY_DX0GCR0_RTTOH 0x3 + * DATX8 n General Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD080700, 0xFFFFFFFFU ,0x40800604U) + */ + PSU_Mask_Write(DDR_PHY_DX0GCR0_OFFSET, 0xFFFFFFFFU, 0x40800604U); +/*##################################################################### */ - Configurable PDR Phase Shift - PSU_DDR_PHY_DX0GCR0_CPDRSHFT 0x0 + /* + * Register : DX0GCR4 @ 0XFD080710 - DQSR Power Down - PSU_DDR_PHY_DX0GCR0_DQSRPD 0x0 + * Byte lane VREF IOM (Used only by D4MU IOs) + * PSU_DDR_PHY_DX0GCR4_RESERVED_31_29 0x0 - DQSG Power Down Receiver - PSU_DDR_PHY_DX0GCR0_DQSGPDR 0x0 + * Byte Lane VREF Pad Enable + * PSU_DDR_PHY_DX0GCR4_DXREFPEN 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX0GCR0_RESERVED_4 0x0 + * Byte Lane Internal VREF Enable + * PSU_DDR_PHY_DX0GCR4_DXREFEEN 0x3 - DQSG On-Die Termination - PSU_DDR_PHY_DX0GCR0_DQSGODT 0x0 + * Byte Lane Single-End VREF Enable + * PSU_DDR_PHY_DX0GCR4_DXREFSEN 0x1 - DQSG Output Enable - PSU_DDR_PHY_DX0GCR0_DQSGOE 0x1 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX0GCR4_RESERVED_24 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX0GCR0_RESERVED_1_0 0x0 + * External VREF generator REFSEL range select + * PSU_DDR_PHY_DX0GCR4_DXREFESELRANGE 0x0 - DATX8 n General Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD080700, 0xFFFFFFFFU ,0x40800604U) - RegMask = (DDR_PHY_DX0GCR0_CALBYP_MASK | DDR_PHY_DX0GCR0_MDLEN_MASK | DDR_PHY_DX0GCR0_CODTSHFT_MASK | DDR_PHY_DX0GCR0_DQSDCC_MASK | DDR_PHY_DX0GCR0_RDDLY_MASK | DDR_PHY_DX0GCR0_RESERVED_19_14_MASK | DDR_PHY_DX0GCR0_DQSNSEPDR_MASK | DDR_PHY_DX0GCR0_DQSSEPDR_MASK | DDR_PHY_DX0GCR0_RTTOAL_MASK | DDR_PHY_DX0GCR0_RTTOH_MASK | DDR_PHY_DX0GCR0_CPDRSHFT_MASK | DDR_PHY_DX0GCR0_DQSRPD_MASK | DDR_PHY_DX0GCR0_DQSGPDR_MASK | DDR_PHY_DX0GCR0_RESERVED_4_MASK | DDR_PHY_DX0GCR0_DQSGODT_MASK | DDR_PHY_DX0GCR0_DQSGOE_MASK | DDR_PHY_DX0GCR0_RESERVED_1_0_MASK | 0 ); + * Byte Lane External VREF Select + * PSU_DDR_PHY_DX0GCR4_DXREFESEL 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX0GCR0_CALBYP_SHIFT - | 0x00000001U << DDR_PHY_DX0GCR0_MDLEN_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR0_CODTSHFT_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR0_DQSDCC_SHIFT - | 0x00000008U << DDR_PHY_DX0GCR0_RDDLY_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR0_RESERVED_19_14_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR0_DQSNSEPDR_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR0_DQSSEPDR_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR0_RTTOAL_SHIFT - | 0x00000003U << DDR_PHY_DX0GCR0_RTTOH_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR0_CPDRSHFT_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR0_DQSRPD_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR0_DQSGPDR_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR0_RESERVED_4_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR0_DQSGODT_SHIFT - | 0x00000001U << DDR_PHY_DX0GCR0_DQSGOE_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR0_RESERVED_1_0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX0GCR0_OFFSET ,0xFFFFFFFFU ,0x40800604U); - /*############################################################################################################################ */ - - /*Register : DX0GCR4 @ 0XFD080710

- - Byte lane VREF IOM (Used only by D4MU IOs) - PSU_DDR_PHY_DX0GCR4_RESERVED_31_29 0x0 + * Single ended VREF generator REFSEL range select + * PSU_DDR_PHY_DX0GCR4_DXREFSSELRANGE 0x1 - Byte Lane VREF Pad Enable - PSU_DDR_PHY_DX0GCR4_DXREFPEN 0x0 + * Byte Lane Single-End VREF Select + * PSU_DDR_PHY_DX0GCR4_DXREFSSEL 0x30 - Byte Lane Internal VREF Enable - PSU_DDR_PHY_DX0GCR4_DXREFEEN 0x3 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX0GCR4_RESERVED_7_6 0x0 - Byte Lane Single-End VREF Enable - PSU_DDR_PHY_DX0GCR4_DXREFSEN 0x1 + * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX0GCR4_DXREFIEN 0xf - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX0GCR4_RESERVED_24 0x0 + * VRMON control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX0GCR4_DXREFIMON 0x0 - External VREF generator REFSEL range select - PSU_DDR_PHY_DX0GCR4_DXREFESELRANGE 0x0 + * DATX8 n General Configuration Register 4 + * (OFFSET, MASK, VALUE) (0XFD080710, 0xFFFFFFFFU ,0x0E00B03CU) + */ + PSU_Mask_Write(DDR_PHY_DX0GCR4_OFFSET, 0xFFFFFFFFU, 0x0E00B03CU); +/*##################################################################### */ - Byte Lane External VREF Select - PSU_DDR_PHY_DX0GCR4_DXREFESEL 0x0 + /* + * Register : DX0GCR5 @ 0XFD080714 - Single ended VREF generator REFSEL range select - PSU_DDR_PHY_DX0GCR4_DXREFSSELRANGE 0x1 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX0GCR5_RESERVED_31 0x0 - Byte Lane Single-End VREF Select - PSU_DDR_PHY_DX0GCR4_DXREFSSEL 0x30 + * Byte Lane internal VREF Select for Rank 3 + * PSU_DDR_PHY_DX0GCR5_DXREFISELR3 0x9 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX0GCR4_RESERVED_7_6 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX0GCR5_RESERVED_23 0x0 - VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. - PSU_DDR_PHY_DX0GCR4_DXREFIEN 0xf + * Byte Lane internal VREF Select for Rank 2 + * PSU_DDR_PHY_DX0GCR5_DXREFISELR2 0x9 - VRMON control for DQ IO (Single Ended) buffers of a byte lane. - PSU_DDR_PHY_DX0GCR4_DXREFIMON 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX0GCR5_RESERVED_15 0x0 - DATX8 n General Configuration Register 4 - (OFFSET, MASK, VALUE) (0XFD080710, 0xFFFFFFFFU ,0x0E00B03CU) - RegMask = (DDR_PHY_DX0GCR4_RESERVED_31_29_MASK | DDR_PHY_DX0GCR4_DXREFPEN_MASK | DDR_PHY_DX0GCR4_DXREFEEN_MASK | DDR_PHY_DX0GCR4_DXREFSEN_MASK | DDR_PHY_DX0GCR4_RESERVED_24_MASK | DDR_PHY_DX0GCR4_DXREFESELRANGE_MASK | DDR_PHY_DX0GCR4_DXREFESEL_MASK | DDR_PHY_DX0GCR4_DXREFSSELRANGE_MASK | DDR_PHY_DX0GCR4_DXREFSSEL_MASK | DDR_PHY_DX0GCR4_RESERVED_7_6_MASK | DDR_PHY_DX0GCR4_DXREFIEN_MASK | DDR_PHY_DX0GCR4_DXREFIMON_MASK | 0 ); + * Byte Lane internal VREF Select for Rank 1 + * PSU_DDR_PHY_DX0GCR5_DXREFISELR1 0x55 - RegVal = ((0x00000000U << DDR_PHY_DX0GCR4_RESERVED_31_29_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR4_DXREFPEN_SHIFT - | 0x00000003U << DDR_PHY_DX0GCR4_DXREFEEN_SHIFT - | 0x00000001U << DDR_PHY_DX0GCR4_DXREFSEN_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR4_RESERVED_24_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR4_DXREFESELRANGE_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR4_DXREFESEL_SHIFT - | 0x00000001U << DDR_PHY_DX0GCR4_DXREFSSELRANGE_SHIFT - | 0x00000030U << DDR_PHY_DX0GCR4_DXREFSSEL_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR4_RESERVED_7_6_SHIFT - | 0x0000000FU << DDR_PHY_DX0GCR4_DXREFIEN_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR4_DXREFIMON_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX0GCR4_OFFSET ,0xFFFFFFFFU ,0x0E00B03CU); - /*############################################################################################################################ */ + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX0GCR5_RESERVED_7 0x0 - /*Register : DX0GCR5 @ 0XFD080714

+ * Byte Lane internal VREF Select for Rank 0 + * PSU_DDR_PHY_DX0GCR5_DXREFISELR0 0x55 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX0GCR5_RESERVED_31 0x0 + * DATX8 n General Configuration Register 5 + * (OFFSET, MASK, VALUE) (0XFD080714, 0xFFFFFFFFU ,0x09095555U) + */ + PSU_Mask_Write(DDR_PHY_DX0GCR5_OFFSET, 0xFFFFFFFFU, 0x09095555U); +/*##################################################################### */ - Byte Lane internal VREF Select for Rank 3 - PSU_DDR_PHY_DX0GCR5_DXREFISELR3 0x9 - - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX0GCR5_RESERVED_23 0x0 - - Byte Lane internal VREF Select for Rank 2 - PSU_DDR_PHY_DX0GCR5_DXREFISELR2 0x9 - - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX0GCR5_RESERVED_15 0x0 - - Byte Lane internal VREF Select for Rank 1 - PSU_DDR_PHY_DX0GCR5_DXREFISELR1 0x4f - - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX0GCR5_RESERVED_7 0x0 - - Byte Lane internal VREF Select for Rank 0 - PSU_DDR_PHY_DX0GCR5_DXREFISELR0 0x4f + /* + * Register : DX0GCR6 @ 0XFD080718 - DATX8 n General Configuration Register 5 - (OFFSET, MASK, VALUE) (0XFD080714, 0xFFFFFFFFU ,0x09094F4FU) - RegMask = (DDR_PHY_DX0GCR5_RESERVED_31_MASK | DDR_PHY_DX0GCR5_DXREFISELR3_MASK | DDR_PHY_DX0GCR5_RESERVED_23_MASK | DDR_PHY_DX0GCR5_DXREFISELR2_MASK | DDR_PHY_DX0GCR5_RESERVED_15_MASK | DDR_PHY_DX0GCR5_DXREFISELR1_MASK | DDR_PHY_DX0GCR5_RESERVED_7_MASK | DDR_PHY_DX0GCR5_DXREFISELR0_MASK | 0 ); + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX0GCR6_RESERVED_31_30 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX0GCR5_RESERVED_31_SHIFT - | 0x00000009U << DDR_PHY_DX0GCR5_DXREFISELR3_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR5_RESERVED_23_SHIFT - | 0x00000009U << DDR_PHY_DX0GCR5_DXREFISELR2_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR5_RESERVED_15_SHIFT - | 0x0000004FU << DDR_PHY_DX0GCR5_DXREFISELR1_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR5_RESERVED_7_SHIFT - | 0x0000004FU << DDR_PHY_DX0GCR5_DXREFISELR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX0GCR5_OFFSET ,0xFFFFFFFFU ,0x09094F4FU); - /*############################################################################################################################ */ + * DRAM DQ VREF Select for Rank3 + * PSU_DDR_PHY_DX0GCR6_DXDQVREFR3 0x9 - /*Register : DX0GCR6 @ 0XFD080718

+ * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX0GCR6_RESERVED_23_22 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX0GCR6_RESERVED_31_30 0x0 + * DRAM DQ VREF Select for Rank2 + * PSU_DDR_PHY_DX0GCR6_DXDQVREFR2 0x9 - DRAM DQ VREF Select for Rank3 - PSU_DDR_PHY_DX0GCR6_DXDQVREFR3 0x9 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX0GCR6_RESERVED_15_14 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX0GCR6_RESERVED_23_22 0x0 + * DRAM DQ VREF Select for Rank1 + * PSU_DDR_PHY_DX0GCR6_DXDQVREFR1 0x2b - DRAM DQ VREF Select for Rank2 - PSU_DDR_PHY_DX0GCR6_DXDQVREFR2 0x9 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX0GCR6_RESERVED_7_6 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX0GCR6_RESERVED_15_14 0x0 + * DRAM DQ VREF Select for Rank0 + * PSU_DDR_PHY_DX0GCR6_DXDQVREFR0 0x2b - DRAM DQ VREF Select for Rank1 - PSU_DDR_PHY_DX0GCR6_DXDQVREFR1 0x2b + * DATX8 n General Configuration Register 6 + * (OFFSET, MASK, VALUE) (0XFD080718, 0xFFFFFFFFU ,0x09092B2BU) + */ + PSU_Mask_Write(DDR_PHY_DX0GCR6_OFFSET, 0xFFFFFFFFU, 0x09092B2BU); +/*##################################################################### */ - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX0GCR6_RESERVED_7_6 0x0 + /* + * Register : DX1GCR0 @ 0XFD080800 - DRAM DQ VREF Select for Rank0 - PSU_DDR_PHY_DX0GCR6_DXDQVREFR0 0x2b + * Calibration Bypass + * PSU_DDR_PHY_DX1GCR0_CALBYP 0x0 - DATX8 n General Configuration Register 6 - (OFFSET, MASK, VALUE) (0XFD080718, 0xFFFFFFFFU ,0x09092B2BU) - RegMask = (DDR_PHY_DX0GCR6_RESERVED_31_30_MASK | DDR_PHY_DX0GCR6_DXDQVREFR3_MASK | DDR_PHY_DX0GCR6_RESERVED_23_22_MASK | DDR_PHY_DX0GCR6_DXDQVREFR2_MASK | DDR_PHY_DX0GCR6_RESERVED_15_14_MASK | DDR_PHY_DX0GCR6_DXDQVREFR1_MASK | DDR_PHY_DX0GCR6_RESERVED_7_6_MASK | DDR_PHY_DX0GCR6_DXDQVREFR0_MASK | 0 ); + * Master Delay Line Enable + * PSU_DDR_PHY_DX1GCR0_MDLEN 0x1 - RegVal = ((0x00000000U << DDR_PHY_DX0GCR6_RESERVED_31_30_SHIFT - | 0x00000009U << DDR_PHY_DX0GCR6_DXDQVREFR3_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR6_RESERVED_23_22_SHIFT - | 0x00000009U << DDR_PHY_DX0GCR6_DXDQVREFR2_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR6_RESERVED_15_14_SHIFT - | 0x0000002BU << DDR_PHY_DX0GCR6_DXDQVREFR1_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR6_RESERVED_7_6_SHIFT - | 0x0000002BU << DDR_PHY_DX0GCR6_DXDQVREFR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX0GCR6_OFFSET ,0xFFFFFFFFU ,0x09092B2BU); - /*############################################################################################################################ */ + * Configurable ODT(TE) Phase Shift + * PSU_DDR_PHY_DX1GCR0_CODTSHFT 0x0 - /*Register : DX0LCDLR2 @ 0XFD080788

+ * DQS Duty Cycle Correction + * PSU_DDR_PHY_DX1GCR0_DQSDCC 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX0LCDLR2_RESERVED_31_25 0x0 + * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY + * PSU_DDR_PHY_DX1GCR0_RDDLY 0x8 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX0LCDLR2_RESERVED_24_16 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX1GCR0_RESERVED_19_14 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX0LCDLR2_RESERVED_15_9 0x0 + * DQSNSE Power Down Receiver + * PSU_DDR_PHY_DX1GCR0_DQSNSEPDR 0x0 - Read DQS Gating Delay - PSU_DDR_PHY_DX0LCDLR2_DQSGD 0x0 + * DQSSE Power Down Receiver + * PSU_DDR_PHY_DX1GCR0_DQSSEPDR 0x0 - DATX8 n Local Calibrated Delay Line Register 2 - (OFFSET, MASK, VALUE) (0XFD080788, 0xFFFFFFFFU ,0x00000000U) - RegMask = (DDR_PHY_DX0LCDLR2_RESERVED_31_25_MASK | DDR_PHY_DX0LCDLR2_RESERVED_24_16_MASK | DDR_PHY_DX0LCDLR2_RESERVED_15_9_MASK | DDR_PHY_DX0LCDLR2_DQSGD_MASK | 0 ); + * RTT On Additive Latency + * PSU_DDR_PHY_DX1GCR0_RTTOAL 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX0LCDLR2_RESERVED_31_25_SHIFT - | 0x00000000U << DDR_PHY_DX0LCDLR2_RESERVED_24_16_SHIFT - | 0x00000000U << DDR_PHY_DX0LCDLR2_RESERVED_15_9_SHIFT - | 0x00000000U << DDR_PHY_DX0LCDLR2_DQSGD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX0LCDLR2_OFFSET ,0xFFFFFFFFU ,0x00000000U); - /*############################################################################################################################ */ + * RTT Output Hold + * PSU_DDR_PHY_DX1GCR0_RTTOH 0x3 - /*Register : DX0GTR0 @ 0XFD0807C0

+ * Configurable PDR Phase Shift + * PSU_DDR_PHY_DX1GCR0_CPDRSHFT 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX0GTR0_RESERVED_31_24 0x0 + * DQSR Power Down + * PSU_DDR_PHY_DX1GCR0_DQSRPD 0x0 - DQ Write Path Latency Pipeline - PSU_DDR_PHY_DX0GTR0_WDQSL 0x0 + * DQSG Power Down Receiver + * PSU_DDR_PHY_DX1GCR0_DQSGPDR 0x0 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX0GTR0_RESERVED_23_20 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX1GCR0_RESERVED_4 0x0 - Write Leveling System Latency - PSU_DDR_PHY_DX0GTR0_WLSL 0x2 + * DQSG On-Die Termination + * PSU_DDR_PHY_DX1GCR0_DQSGODT 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX0GTR0_RESERVED_15_13 0x0 + * DQSG Output Enable + * PSU_DDR_PHY_DX1GCR0_DQSGOE 0x1 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX0GTR0_RESERVED_12_8 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX1GCR0_RESERVED_1_0 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX0GTR0_RESERVED_7_5 0x0 + * DATX8 n General Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD080800, 0xFFFFFFFFU ,0x40800604U) + */ + PSU_Mask_Write(DDR_PHY_DX1GCR0_OFFSET, 0xFFFFFFFFU, 0x40800604U); +/*##################################################################### */ - DQS Gating System Latency - PSU_DDR_PHY_DX0GTR0_DGSL 0x0 + /* + * Register : DX1GCR4 @ 0XFD080810 - DATX8 n General Timing Register 0 - (OFFSET, MASK, VALUE) (0XFD0807C0, 0xFFFFFFFFU ,0x00020000U) - RegMask = (DDR_PHY_DX0GTR0_RESERVED_31_24_MASK | DDR_PHY_DX0GTR0_WDQSL_MASK | DDR_PHY_DX0GTR0_RESERVED_23_20_MASK | DDR_PHY_DX0GTR0_WLSL_MASK | DDR_PHY_DX0GTR0_RESERVED_15_13_MASK | DDR_PHY_DX0GTR0_RESERVED_12_8_MASK | DDR_PHY_DX0GTR0_RESERVED_7_5_MASK | DDR_PHY_DX0GTR0_DGSL_MASK | 0 ); + * Byte lane VREF IOM (Used only by D4MU IOs) + * PSU_DDR_PHY_DX1GCR4_RESERVED_31_29 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX0GTR0_RESERVED_31_24_SHIFT - | 0x00000000U << DDR_PHY_DX0GTR0_WDQSL_SHIFT - | 0x00000000U << DDR_PHY_DX0GTR0_RESERVED_23_20_SHIFT - | 0x00000002U << DDR_PHY_DX0GTR0_WLSL_SHIFT - | 0x00000000U << DDR_PHY_DX0GTR0_RESERVED_15_13_SHIFT - | 0x00000000U << DDR_PHY_DX0GTR0_RESERVED_12_8_SHIFT - | 0x00000000U << DDR_PHY_DX0GTR0_RESERVED_7_5_SHIFT - | 0x00000000U << DDR_PHY_DX0GTR0_DGSL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX0GTR0_OFFSET ,0xFFFFFFFFU ,0x00020000U); - /*############################################################################################################################ */ + * Byte Lane VREF Pad Enable + * PSU_DDR_PHY_DX1GCR4_DXREFPEN 0x0 - /*Register : DX1GCR0 @ 0XFD080800

+ * Byte Lane Internal VREF Enable + * PSU_DDR_PHY_DX1GCR4_DXREFEEN 0x3 - Calibration Bypass - PSU_DDR_PHY_DX1GCR0_CALBYP 0x0 + * Byte Lane Single-End VREF Enable + * PSU_DDR_PHY_DX1GCR4_DXREFSEN 0x1 - Master Delay Line Enable - PSU_DDR_PHY_DX1GCR0_MDLEN 0x1 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX1GCR4_RESERVED_24 0x0 - Configurable ODT(TE) Phase Shift - PSU_DDR_PHY_DX1GCR0_CODTSHFT 0x0 + * External VREF generator REFSEL range select + * PSU_DDR_PHY_DX1GCR4_DXREFESELRANGE 0x0 - DQS Duty Cycle Correction - PSU_DDR_PHY_DX1GCR0_DQSDCC 0x0 + * Byte Lane External VREF Select + * PSU_DDR_PHY_DX1GCR4_DXREFESEL 0x0 - Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY - PSU_DDR_PHY_DX1GCR0_RDDLY 0x8 + * Single ended VREF generator REFSEL range select + * PSU_DDR_PHY_DX1GCR4_DXREFSSELRANGE 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX1GCR0_RESERVED_19_14 0x0 + * Byte Lane Single-End VREF Select + * PSU_DDR_PHY_DX1GCR4_DXREFSSEL 0x30 - DQSNSE Power Down Receiver - PSU_DDR_PHY_DX1GCR0_DQSNSEPDR 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX1GCR4_RESERVED_7_6 0x0 - DQSSE Power Down Receiver - PSU_DDR_PHY_DX1GCR0_DQSSEPDR 0x0 + * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX1GCR4_DXREFIEN 0xf - RTT On Additive Latency - PSU_DDR_PHY_DX1GCR0_RTTOAL 0x0 + * VRMON control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX1GCR4_DXREFIMON 0x0 - RTT Output Hold - PSU_DDR_PHY_DX1GCR0_RTTOH 0x3 + * DATX8 n General Configuration Register 4 + * (OFFSET, MASK, VALUE) (0XFD080810, 0xFFFFFFFFU ,0x0E00B03CU) + */ + PSU_Mask_Write(DDR_PHY_DX1GCR4_OFFSET, 0xFFFFFFFFU, 0x0E00B03CU); +/*##################################################################### */ - Configurable PDR Phase Shift - PSU_DDR_PHY_DX1GCR0_CPDRSHFT 0x0 + /* + * Register : DX1GCR5 @ 0XFD080814 - DQSR Power Down - PSU_DDR_PHY_DX1GCR0_DQSRPD 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX1GCR5_RESERVED_31 0x0 - DQSG Power Down Receiver - PSU_DDR_PHY_DX1GCR0_DQSGPDR 0x0 + * Byte Lane internal VREF Select for Rank 3 + * PSU_DDR_PHY_DX1GCR5_DXREFISELR3 0x9 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX1GCR0_RESERVED_4 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX1GCR5_RESERVED_23 0x0 - DQSG On-Die Termination - PSU_DDR_PHY_DX1GCR0_DQSGODT 0x0 + * Byte Lane internal VREF Select for Rank 2 + * PSU_DDR_PHY_DX1GCR5_DXREFISELR2 0x9 - DQSG Output Enable - PSU_DDR_PHY_DX1GCR0_DQSGOE 0x1 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX1GCR5_RESERVED_15 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX1GCR0_RESERVED_1_0 0x0 + * Byte Lane internal VREF Select for Rank 1 + * PSU_DDR_PHY_DX1GCR5_DXREFISELR1 0x55 - DATX8 n General Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD080800, 0xFFFFFFFFU ,0x40800604U) - RegMask = (DDR_PHY_DX1GCR0_CALBYP_MASK | DDR_PHY_DX1GCR0_MDLEN_MASK | DDR_PHY_DX1GCR0_CODTSHFT_MASK | DDR_PHY_DX1GCR0_DQSDCC_MASK | DDR_PHY_DX1GCR0_RDDLY_MASK | DDR_PHY_DX1GCR0_RESERVED_19_14_MASK | DDR_PHY_DX1GCR0_DQSNSEPDR_MASK | DDR_PHY_DX1GCR0_DQSSEPDR_MASK | DDR_PHY_DX1GCR0_RTTOAL_MASK | DDR_PHY_DX1GCR0_RTTOH_MASK | DDR_PHY_DX1GCR0_CPDRSHFT_MASK | DDR_PHY_DX1GCR0_DQSRPD_MASK | DDR_PHY_DX1GCR0_DQSGPDR_MASK | DDR_PHY_DX1GCR0_RESERVED_4_MASK | DDR_PHY_DX1GCR0_DQSGODT_MASK | DDR_PHY_DX1GCR0_DQSGOE_MASK | DDR_PHY_DX1GCR0_RESERVED_1_0_MASK | 0 ); + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX1GCR5_RESERVED_7 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX1GCR0_CALBYP_SHIFT - | 0x00000001U << DDR_PHY_DX1GCR0_MDLEN_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR0_CODTSHFT_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR0_DQSDCC_SHIFT - | 0x00000008U << DDR_PHY_DX1GCR0_RDDLY_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR0_RESERVED_19_14_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR0_DQSNSEPDR_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR0_DQSSEPDR_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR0_RTTOAL_SHIFT - | 0x00000003U << DDR_PHY_DX1GCR0_RTTOH_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR0_CPDRSHFT_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR0_DQSRPD_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR0_DQSGPDR_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR0_RESERVED_4_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR0_DQSGODT_SHIFT - | 0x00000001U << DDR_PHY_DX1GCR0_DQSGOE_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR0_RESERVED_1_0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX1GCR0_OFFSET ,0xFFFFFFFFU ,0x40800604U); - /*############################################################################################################################ */ + * Byte Lane internal VREF Select for Rank 0 + * PSU_DDR_PHY_DX1GCR5_DXREFISELR0 0x55 - /*Register : DX1GCR4 @ 0XFD080810

+ * DATX8 n General Configuration Register 5 + * (OFFSET, MASK, VALUE) (0XFD080814, 0xFFFFFFFFU ,0x09095555U) + */ + PSU_Mask_Write(DDR_PHY_DX1GCR5_OFFSET, 0xFFFFFFFFU, 0x09095555U); +/*##################################################################### */ - Byte lane VREF IOM (Used only by D4MU IOs) - PSU_DDR_PHY_DX1GCR4_RESERVED_31_29 0x0 + /* + * Register : DX1GCR6 @ 0XFD080818 - Byte Lane VREF Pad Enable - PSU_DDR_PHY_DX1GCR4_DXREFPEN 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX1GCR6_RESERVED_31_30 0x0 - Byte Lane Internal VREF Enable - PSU_DDR_PHY_DX1GCR4_DXREFEEN 0x3 + * DRAM DQ VREF Select for Rank3 + * PSU_DDR_PHY_DX1GCR6_DXDQVREFR3 0x9 - Byte Lane Single-End VREF Enable - PSU_DDR_PHY_DX1GCR4_DXREFSEN 0x1 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX1GCR6_RESERVED_23_22 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX1GCR4_RESERVED_24 0x0 + * DRAM DQ VREF Select for Rank2 + * PSU_DDR_PHY_DX1GCR6_DXDQVREFR2 0x9 - External VREF generator REFSEL range select - PSU_DDR_PHY_DX1GCR4_DXREFESELRANGE 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX1GCR6_RESERVED_15_14 0x0 - Byte Lane External VREF Select - PSU_DDR_PHY_DX1GCR4_DXREFESEL 0x0 + * DRAM DQ VREF Select for Rank1 + * PSU_DDR_PHY_DX1GCR6_DXDQVREFR1 0x2b - Single ended VREF generator REFSEL range select - PSU_DDR_PHY_DX1GCR4_DXREFSSELRANGE 0x1 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX1GCR6_RESERVED_7_6 0x0 - Byte Lane Single-End VREF Select - PSU_DDR_PHY_DX1GCR4_DXREFSSEL 0x30 + * DRAM DQ VREF Select for Rank0 + * PSU_DDR_PHY_DX1GCR6_DXDQVREFR0 0x2b - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX1GCR4_RESERVED_7_6 0x0 + * DATX8 n General Configuration Register 6 + * (OFFSET, MASK, VALUE) (0XFD080818, 0xFFFFFFFFU ,0x09092B2BU) + */ + PSU_Mask_Write(DDR_PHY_DX1GCR6_OFFSET, 0xFFFFFFFFU, 0x09092B2BU); +/*##################################################################### */ - VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. - PSU_DDR_PHY_DX1GCR4_DXREFIEN 0xf + /* + * Register : DX2GCR0 @ 0XFD080900 - VRMON control for DQ IO (Single Ended) buffers of a byte lane. - PSU_DDR_PHY_DX1GCR4_DXREFIMON 0x0 + * Calibration Bypass + * PSU_DDR_PHY_DX2GCR0_CALBYP 0x0 - DATX8 n General Configuration Register 4 - (OFFSET, MASK, VALUE) (0XFD080810, 0xFFFFFFFFU ,0x0E00B03CU) - RegMask = (DDR_PHY_DX1GCR4_RESERVED_31_29_MASK | DDR_PHY_DX1GCR4_DXREFPEN_MASK | DDR_PHY_DX1GCR4_DXREFEEN_MASK | DDR_PHY_DX1GCR4_DXREFSEN_MASK | DDR_PHY_DX1GCR4_RESERVED_24_MASK | DDR_PHY_DX1GCR4_DXREFESELRANGE_MASK | DDR_PHY_DX1GCR4_DXREFESEL_MASK | DDR_PHY_DX1GCR4_DXREFSSELRANGE_MASK | DDR_PHY_DX1GCR4_DXREFSSEL_MASK | DDR_PHY_DX1GCR4_RESERVED_7_6_MASK | DDR_PHY_DX1GCR4_DXREFIEN_MASK | DDR_PHY_DX1GCR4_DXREFIMON_MASK | 0 ); + * Master Delay Line Enable + * PSU_DDR_PHY_DX2GCR0_MDLEN 0x1 - RegVal = ((0x00000000U << DDR_PHY_DX1GCR4_RESERVED_31_29_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR4_DXREFPEN_SHIFT - | 0x00000003U << DDR_PHY_DX1GCR4_DXREFEEN_SHIFT - | 0x00000001U << DDR_PHY_DX1GCR4_DXREFSEN_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR4_RESERVED_24_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR4_DXREFESELRANGE_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR4_DXREFESEL_SHIFT - | 0x00000001U << DDR_PHY_DX1GCR4_DXREFSSELRANGE_SHIFT - | 0x00000030U << DDR_PHY_DX1GCR4_DXREFSSEL_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR4_RESERVED_7_6_SHIFT - | 0x0000000FU << DDR_PHY_DX1GCR4_DXREFIEN_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR4_DXREFIMON_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX1GCR4_OFFSET ,0xFFFFFFFFU ,0x0E00B03CU); - /*############################################################################################################################ */ + * Configurable ODT(TE) Phase Shift + * PSU_DDR_PHY_DX2GCR0_CODTSHFT 0x0 - /*Register : DX1GCR5 @ 0XFD080814

+ * DQS Duty Cycle Correction + * PSU_DDR_PHY_DX2GCR0_DQSDCC 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX1GCR5_RESERVED_31 0x0 + * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY + * PSU_DDR_PHY_DX2GCR0_RDDLY 0x8 - Byte Lane internal VREF Select for Rank 3 - PSU_DDR_PHY_DX1GCR5_DXREFISELR3 0x9 - - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX1GCR5_RESERVED_23 0x0 - - Byte Lane internal VREF Select for Rank 2 - PSU_DDR_PHY_DX1GCR5_DXREFISELR2 0x9 - - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX1GCR5_RESERVED_15 0x0 - - Byte Lane internal VREF Select for Rank 1 - PSU_DDR_PHY_DX1GCR5_DXREFISELR1 0x4f - - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX1GCR5_RESERVED_7 0x0 - - Byte Lane internal VREF Select for Rank 0 - PSU_DDR_PHY_DX1GCR5_DXREFISELR0 0x4f + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX2GCR0_RESERVED_19_14 0x0 - DATX8 n General Configuration Register 5 - (OFFSET, MASK, VALUE) (0XFD080814, 0xFFFFFFFFU ,0x09094F4FU) - RegMask = (DDR_PHY_DX1GCR5_RESERVED_31_MASK | DDR_PHY_DX1GCR5_DXREFISELR3_MASK | DDR_PHY_DX1GCR5_RESERVED_23_MASK | DDR_PHY_DX1GCR5_DXREFISELR2_MASK | DDR_PHY_DX1GCR5_RESERVED_15_MASK | DDR_PHY_DX1GCR5_DXREFISELR1_MASK | DDR_PHY_DX1GCR5_RESERVED_7_MASK | DDR_PHY_DX1GCR5_DXREFISELR0_MASK | 0 ); + * DQSNSE Power Down Receiver + * PSU_DDR_PHY_DX2GCR0_DQSNSEPDR 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX1GCR5_RESERVED_31_SHIFT - | 0x00000009U << DDR_PHY_DX1GCR5_DXREFISELR3_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR5_RESERVED_23_SHIFT - | 0x00000009U << DDR_PHY_DX1GCR5_DXREFISELR2_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR5_RESERVED_15_SHIFT - | 0x0000004FU << DDR_PHY_DX1GCR5_DXREFISELR1_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR5_RESERVED_7_SHIFT - | 0x0000004FU << DDR_PHY_DX1GCR5_DXREFISELR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX1GCR5_OFFSET ,0xFFFFFFFFU ,0x09094F4FU); - /*############################################################################################################################ */ + * DQSSE Power Down Receiver + * PSU_DDR_PHY_DX2GCR0_DQSSEPDR 0x0 - /*Register : DX1GCR6 @ 0XFD080818

+ * RTT On Additive Latency + * PSU_DDR_PHY_DX2GCR0_RTTOAL 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX1GCR6_RESERVED_31_30 0x0 + * RTT Output Hold + * PSU_DDR_PHY_DX2GCR0_RTTOH 0x3 - DRAM DQ VREF Select for Rank3 - PSU_DDR_PHY_DX1GCR6_DXDQVREFR3 0x9 + * Configurable PDR Phase Shift + * PSU_DDR_PHY_DX2GCR0_CPDRSHFT 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX1GCR6_RESERVED_23_22 0x0 + * DQSR Power Down + * PSU_DDR_PHY_DX2GCR0_DQSRPD 0x0 - DRAM DQ VREF Select for Rank2 - PSU_DDR_PHY_DX1GCR6_DXDQVREFR2 0x9 + * DQSG Power Down Receiver + * PSU_DDR_PHY_DX2GCR0_DQSGPDR 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX1GCR6_RESERVED_15_14 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX2GCR0_RESERVED_4 0x0 - DRAM DQ VREF Select for Rank1 - PSU_DDR_PHY_DX1GCR6_DXDQVREFR1 0x2b + * DQSG On-Die Termination + * PSU_DDR_PHY_DX2GCR0_DQSGODT 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX1GCR6_RESERVED_7_6 0x0 + * DQSG Output Enable + * PSU_DDR_PHY_DX2GCR0_DQSGOE 0x1 - DRAM DQ VREF Select for Rank0 - PSU_DDR_PHY_DX1GCR6_DXDQVREFR0 0x2b + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX2GCR0_RESERVED_1_0 0x0 - DATX8 n General Configuration Register 6 - (OFFSET, MASK, VALUE) (0XFD080818, 0xFFFFFFFFU ,0x09092B2BU) - RegMask = (DDR_PHY_DX1GCR6_RESERVED_31_30_MASK | DDR_PHY_DX1GCR6_DXDQVREFR3_MASK | DDR_PHY_DX1GCR6_RESERVED_23_22_MASK | DDR_PHY_DX1GCR6_DXDQVREFR2_MASK | DDR_PHY_DX1GCR6_RESERVED_15_14_MASK | DDR_PHY_DX1GCR6_DXDQVREFR1_MASK | DDR_PHY_DX1GCR6_RESERVED_7_6_MASK | DDR_PHY_DX1GCR6_DXDQVREFR0_MASK | 0 ); + * DATX8 n General Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD080900, 0xFFFFFFFFU ,0x40800604U) + */ + PSU_Mask_Write(DDR_PHY_DX2GCR0_OFFSET, 0xFFFFFFFFU, 0x40800604U); +/*##################################################################### */ - RegVal = ((0x00000000U << DDR_PHY_DX1GCR6_RESERVED_31_30_SHIFT - | 0x00000009U << DDR_PHY_DX1GCR6_DXDQVREFR3_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR6_RESERVED_23_22_SHIFT - | 0x00000009U << DDR_PHY_DX1GCR6_DXDQVREFR2_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR6_RESERVED_15_14_SHIFT - | 0x0000002BU << DDR_PHY_DX1GCR6_DXDQVREFR1_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR6_RESERVED_7_6_SHIFT - | 0x0000002BU << DDR_PHY_DX1GCR6_DXDQVREFR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX1GCR6_OFFSET ,0xFFFFFFFFU ,0x09092B2BU); - /*############################################################################################################################ */ + /* + * Register : DX2GCR1 @ 0XFD080904 - /*Register : DX1LCDLR2 @ 0XFD080888

+ * Enables the PDR mode for DQ[7:0] + * PSU_DDR_PHY_DX2GCR1_DXPDRMODE 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX1LCDLR2_RESERVED_31_25 0x0 + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX2GCR1_RESERVED_15 0x0 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX1LCDLR2_RESERVED_24_16 0x0 + * Select the delayed or non-delayed read data strobe # + * PSU_DDR_PHY_DX2GCR1_QSNSEL 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX1LCDLR2_RESERVED_15_9 0x0 + * Select the delayed or non-delayed read data strobe + * PSU_DDR_PHY_DX2GCR1_QSSEL 0x1 - Read DQS Gating Delay - PSU_DDR_PHY_DX1LCDLR2_DQSGD 0x0 + * Enables Read Data Strobe in a byte lane + * PSU_DDR_PHY_DX2GCR1_OEEN 0x1 - DATX8 n Local Calibrated Delay Line Register 2 - (OFFSET, MASK, VALUE) (0XFD080888, 0xFFFFFFFFU ,0x00000000U) - RegMask = (DDR_PHY_DX1LCDLR2_RESERVED_31_25_MASK | DDR_PHY_DX1LCDLR2_RESERVED_24_16_MASK | DDR_PHY_DX1LCDLR2_RESERVED_15_9_MASK | DDR_PHY_DX1LCDLR2_DQSGD_MASK | 0 ); + * Enables PDR in a byte lane + * PSU_DDR_PHY_DX2GCR1_PDREN 0x1 - RegVal = ((0x00000000U << DDR_PHY_DX1LCDLR2_RESERVED_31_25_SHIFT - | 0x00000000U << DDR_PHY_DX1LCDLR2_RESERVED_24_16_SHIFT - | 0x00000000U << DDR_PHY_DX1LCDLR2_RESERVED_15_9_SHIFT - | 0x00000000U << DDR_PHY_DX1LCDLR2_DQSGD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX1LCDLR2_OFFSET ,0xFFFFFFFFU ,0x00000000U); - /*############################################################################################################################ */ + * Enables ODT/TE in a byte lane + * PSU_DDR_PHY_DX2GCR1_TEEN 0x1 - /*Register : DX1GTR0 @ 0XFD0808C0

+ * Enables Write Data strobe in a byte lane + * PSU_DDR_PHY_DX2GCR1_DSEN 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX1GTR0_RESERVED_31_24 0x0 + * Enables DM pin in a byte lane + * PSU_DDR_PHY_DX2GCR1_DMEN 0x1 - DQ Write Path Latency Pipeline - PSU_DDR_PHY_DX1GTR0_WDQSL 0x0 + * Enables DQ corresponding to each bit in a byte + * PSU_DDR_PHY_DX2GCR1_DQEN 0xff - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX1GTR0_RESERVED_23_20 0x0 + * DATX8 n General Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD080904, 0xFFFFFFFFU ,0x00007FFFU) + */ + PSU_Mask_Write(DDR_PHY_DX2GCR1_OFFSET, 0xFFFFFFFFU, 0x00007FFFU); +/*##################################################################### */ - Write Leveling System Latency - PSU_DDR_PHY_DX1GTR0_WLSL 0x2 + /* + * Register : DX2GCR4 @ 0XFD080910 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX1GTR0_RESERVED_15_13 0x0 + * Byte lane VREF IOM (Used only by D4MU IOs) + * PSU_DDR_PHY_DX2GCR4_RESERVED_31_29 0x0 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX1GTR0_RESERVED_12_8 0x0 + * Byte Lane VREF Pad Enable + * PSU_DDR_PHY_DX2GCR4_DXREFPEN 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX1GTR0_RESERVED_7_5 0x0 + * Byte Lane Internal VREF Enable + * PSU_DDR_PHY_DX2GCR4_DXREFEEN 0x3 - DQS Gating System Latency - PSU_DDR_PHY_DX1GTR0_DGSL 0x0 + * Byte Lane Single-End VREF Enable + * PSU_DDR_PHY_DX2GCR4_DXREFSEN 0x1 - DATX8 n General Timing Register 0 - (OFFSET, MASK, VALUE) (0XFD0808C0, 0xFFFFFFFFU ,0x00020000U) - RegMask = (DDR_PHY_DX1GTR0_RESERVED_31_24_MASK | DDR_PHY_DX1GTR0_WDQSL_MASK | DDR_PHY_DX1GTR0_RESERVED_23_20_MASK | DDR_PHY_DX1GTR0_WLSL_MASK | DDR_PHY_DX1GTR0_RESERVED_15_13_MASK | DDR_PHY_DX1GTR0_RESERVED_12_8_MASK | DDR_PHY_DX1GTR0_RESERVED_7_5_MASK | DDR_PHY_DX1GTR0_DGSL_MASK | 0 ); + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX2GCR4_RESERVED_24 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX1GTR0_RESERVED_31_24_SHIFT - | 0x00000000U << DDR_PHY_DX1GTR0_WDQSL_SHIFT - | 0x00000000U << DDR_PHY_DX1GTR0_RESERVED_23_20_SHIFT - | 0x00000002U << DDR_PHY_DX1GTR0_WLSL_SHIFT - | 0x00000000U << DDR_PHY_DX1GTR0_RESERVED_15_13_SHIFT - | 0x00000000U << DDR_PHY_DX1GTR0_RESERVED_12_8_SHIFT - | 0x00000000U << DDR_PHY_DX1GTR0_RESERVED_7_5_SHIFT - | 0x00000000U << DDR_PHY_DX1GTR0_DGSL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX1GTR0_OFFSET ,0xFFFFFFFFU ,0x00020000U); - /*############################################################################################################################ */ + * External VREF generator REFSEL range select + * PSU_DDR_PHY_DX2GCR4_DXREFESELRANGE 0x0 - /*Register : DX2GCR0 @ 0XFD080900

+ * Byte Lane External VREF Select + * PSU_DDR_PHY_DX2GCR4_DXREFESEL 0x0 - Calibration Bypass - PSU_DDR_PHY_DX2GCR0_CALBYP 0x0 + * Single ended VREF generator REFSEL range select + * PSU_DDR_PHY_DX2GCR4_DXREFSSELRANGE 0x1 - Master Delay Line Enable - PSU_DDR_PHY_DX2GCR0_MDLEN 0x1 + * Byte Lane Single-End VREF Select + * PSU_DDR_PHY_DX2GCR4_DXREFSSEL 0x30 - Configurable ODT(TE) Phase Shift - PSU_DDR_PHY_DX2GCR0_CODTSHFT 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX2GCR4_RESERVED_7_6 0x0 - DQS Duty Cycle Correction - PSU_DDR_PHY_DX2GCR0_DQSDCC 0x0 + * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX2GCR4_DXREFIEN 0xf - Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY - PSU_DDR_PHY_DX2GCR0_RDDLY 0x8 + * VRMON control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX2GCR4_DXREFIMON 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX2GCR0_RESERVED_19_14 0x0 + * DATX8 n General Configuration Register 4 + * (OFFSET, MASK, VALUE) (0XFD080910, 0xFFFFFFFFU ,0x0E00B03CU) + */ + PSU_Mask_Write(DDR_PHY_DX2GCR4_OFFSET, 0xFFFFFFFFU, 0x0E00B03CU); +/*##################################################################### */ - DQSNSE Power Down Receiver - PSU_DDR_PHY_DX2GCR0_DQSNSEPDR 0x0 + /* + * Register : DX2GCR5 @ 0XFD080914 - DQSSE Power Down Receiver - PSU_DDR_PHY_DX2GCR0_DQSSEPDR 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX2GCR5_RESERVED_31 0x0 - RTT On Additive Latency - PSU_DDR_PHY_DX2GCR0_RTTOAL 0x0 + * Byte Lane internal VREF Select for Rank 3 + * PSU_DDR_PHY_DX2GCR5_DXREFISELR3 0x9 - RTT Output Hold - PSU_DDR_PHY_DX2GCR0_RTTOH 0x3 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX2GCR5_RESERVED_23 0x0 - Configurable PDR Phase Shift - PSU_DDR_PHY_DX2GCR0_CPDRSHFT 0x0 + * Byte Lane internal VREF Select for Rank 2 + * PSU_DDR_PHY_DX2GCR5_DXREFISELR2 0x9 - DQSR Power Down - PSU_DDR_PHY_DX2GCR0_DQSRPD 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX2GCR5_RESERVED_15 0x0 - DQSG Power Down Receiver - PSU_DDR_PHY_DX2GCR0_DQSGPDR 0x0 + * Byte Lane internal VREF Select for Rank 1 + * PSU_DDR_PHY_DX2GCR5_DXREFISELR1 0x55 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX2GCR0_RESERVED_4 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX2GCR5_RESERVED_7 0x0 - DQSG On-Die Termination - PSU_DDR_PHY_DX2GCR0_DQSGODT 0x0 + * Byte Lane internal VREF Select for Rank 0 + * PSU_DDR_PHY_DX2GCR5_DXREFISELR0 0x55 - DQSG Output Enable - PSU_DDR_PHY_DX2GCR0_DQSGOE 0x1 + * DATX8 n General Configuration Register 5 + * (OFFSET, MASK, VALUE) (0XFD080914, 0xFFFFFFFFU ,0x09095555U) + */ + PSU_Mask_Write(DDR_PHY_DX2GCR5_OFFSET, 0xFFFFFFFFU, 0x09095555U); +/*##################################################################### */ - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX2GCR0_RESERVED_1_0 0x0 + /* + * Register : DX2GCR6 @ 0XFD080918 - DATX8 n General Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD080900, 0xFFFFFFFFU ,0x40800604U) - RegMask = (DDR_PHY_DX2GCR0_CALBYP_MASK | DDR_PHY_DX2GCR0_MDLEN_MASK | DDR_PHY_DX2GCR0_CODTSHFT_MASK | DDR_PHY_DX2GCR0_DQSDCC_MASK | DDR_PHY_DX2GCR0_RDDLY_MASK | DDR_PHY_DX2GCR0_RESERVED_19_14_MASK | DDR_PHY_DX2GCR0_DQSNSEPDR_MASK | DDR_PHY_DX2GCR0_DQSSEPDR_MASK | DDR_PHY_DX2GCR0_RTTOAL_MASK | DDR_PHY_DX2GCR0_RTTOH_MASK | DDR_PHY_DX2GCR0_CPDRSHFT_MASK | DDR_PHY_DX2GCR0_DQSRPD_MASK | DDR_PHY_DX2GCR0_DQSGPDR_MASK | DDR_PHY_DX2GCR0_RESERVED_4_MASK | DDR_PHY_DX2GCR0_DQSGODT_MASK | DDR_PHY_DX2GCR0_DQSGOE_MASK | DDR_PHY_DX2GCR0_RESERVED_1_0_MASK | 0 ); + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX2GCR6_RESERVED_31_30 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX2GCR0_CALBYP_SHIFT - | 0x00000001U << DDR_PHY_DX2GCR0_MDLEN_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR0_CODTSHFT_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR0_DQSDCC_SHIFT - | 0x00000008U << DDR_PHY_DX2GCR0_RDDLY_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR0_RESERVED_19_14_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR0_DQSNSEPDR_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR0_DQSSEPDR_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR0_RTTOAL_SHIFT - | 0x00000003U << DDR_PHY_DX2GCR0_RTTOH_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR0_CPDRSHFT_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR0_DQSRPD_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR0_DQSGPDR_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR0_RESERVED_4_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR0_DQSGODT_SHIFT - | 0x00000001U << DDR_PHY_DX2GCR0_DQSGOE_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR0_RESERVED_1_0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX2GCR0_OFFSET ,0xFFFFFFFFU ,0x40800604U); - /*############################################################################################################################ */ + * DRAM DQ VREF Select for Rank3 + * PSU_DDR_PHY_DX2GCR6_DXDQVREFR3 0x9 - /*Register : DX2GCR1 @ 0XFD080904

+ * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX2GCR6_RESERVED_23_22 0x0 - Enables the PDR mode for DQ[7:0] - PSU_DDR_PHY_DX2GCR1_DXPDRMODE 0x0 + * DRAM DQ VREF Select for Rank2 + * PSU_DDR_PHY_DX2GCR6_DXDQVREFR2 0x9 - Reserved. Returns zeroes on reads. - PSU_DDR_PHY_DX2GCR1_RESERVED_15 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX2GCR6_RESERVED_15_14 0x0 - Select the delayed or non-delayed read data strobe # - PSU_DDR_PHY_DX2GCR1_QSNSEL 0x1 + * DRAM DQ VREF Select for Rank1 + * PSU_DDR_PHY_DX2GCR6_DXDQVREFR1 0x2b - Select the delayed or non-delayed read data strobe - PSU_DDR_PHY_DX2GCR1_QSSEL 0x1 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX2GCR6_RESERVED_7_6 0x0 - Enables Read Data Strobe in a byte lane - PSU_DDR_PHY_DX2GCR1_OEEN 0x1 + * DRAM DQ VREF Select for Rank0 + * PSU_DDR_PHY_DX2GCR6_DXDQVREFR0 0x2b - Enables PDR in a byte lane - PSU_DDR_PHY_DX2GCR1_PDREN 0x1 + * DATX8 n General Configuration Register 6 + * (OFFSET, MASK, VALUE) (0XFD080918, 0xFFFFFFFFU ,0x09092B2BU) + */ + PSU_Mask_Write(DDR_PHY_DX2GCR6_OFFSET, 0xFFFFFFFFU, 0x09092B2BU); +/*##################################################################### */ - Enables ODT/TE in a byte lane - PSU_DDR_PHY_DX2GCR1_TEEN 0x1 + /* + * Register : DX3GCR0 @ 0XFD080A00 - Enables Write Data strobe in a byte lane - PSU_DDR_PHY_DX2GCR1_DSEN 0x1 + * Calibration Bypass + * PSU_DDR_PHY_DX3GCR0_CALBYP 0x0 - Enables DM pin in a byte lane - PSU_DDR_PHY_DX2GCR1_DMEN 0x1 + * Master Delay Line Enable + * PSU_DDR_PHY_DX3GCR0_MDLEN 0x1 - Enables DQ corresponding to each bit in a byte - PSU_DDR_PHY_DX2GCR1_DQEN 0xff + * Configurable ODT(TE) Phase Shift + * PSU_DDR_PHY_DX3GCR0_CODTSHFT 0x0 - DATX8 n General Configuration Register 1 - (OFFSET, MASK, VALUE) (0XFD080904, 0xFFFFFFFFU ,0x00007FFFU) - RegMask = (DDR_PHY_DX2GCR1_DXPDRMODE_MASK | DDR_PHY_DX2GCR1_RESERVED_15_MASK | DDR_PHY_DX2GCR1_QSNSEL_MASK | DDR_PHY_DX2GCR1_QSSEL_MASK | DDR_PHY_DX2GCR1_OEEN_MASK | DDR_PHY_DX2GCR1_PDREN_MASK | DDR_PHY_DX2GCR1_TEEN_MASK | DDR_PHY_DX2GCR1_DSEN_MASK | DDR_PHY_DX2GCR1_DMEN_MASK | DDR_PHY_DX2GCR1_DQEN_MASK | 0 ); + * DQS Duty Cycle Correction + * PSU_DDR_PHY_DX3GCR0_DQSDCC 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX2GCR1_DXPDRMODE_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR1_RESERVED_15_SHIFT - | 0x00000001U << DDR_PHY_DX2GCR1_QSNSEL_SHIFT - | 0x00000001U << DDR_PHY_DX2GCR1_QSSEL_SHIFT - | 0x00000001U << DDR_PHY_DX2GCR1_OEEN_SHIFT - | 0x00000001U << DDR_PHY_DX2GCR1_PDREN_SHIFT - | 0x00000001U << DDR_PHY_DX2GCR1_TEEN_SHIFT - | 0x00000001U << DDR_PHY_DX2GCR1_DSEN_SHIFT - | 0x00000001U << DDR_PHY_DX2GCR1_DMEN_SHIFT - | 0x000000FFU << DDR_PHY_DX2GCR1_DQEN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX2GCR1_OFFSET ,0xFFFFFFFFU ,0x00007FFFU); - /*############################################################################################################################ */ + * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY + * PSU_DDR_PHY_DX3GCR0_RDDLY 0x8 - /*Register : DX2GCR4 @ 0XFD080910

+ * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX3GCR0_RESERVED_19_14 0x0 - Byte lane VREF IOM (Used only by D4MU IOs) - PSU_DDR_PHY_DX2GCR4_RESERVED_31_29 0x0 + * DQSNSE Power Down Receiver + * PSU_DDR_PHY_DX3GCR0_DQSNSEPDR 0x0 - Byte Lane VREF Pad Enable - PSU_DDR_PHY_DX2GCR4_DXREFPEN 0x0 + * DQSSE Power Down Receiver + * PSU_DDR_PHY_DX3GCR0_DQSSEPDR 0x0 - Byte Lane Internal VREF Enable - PSU_DDR_PHY_DX2GCR4_DXREFEEN 0x3 + * RTT On Additive Latency + * PSU_DDR_PHY_DX3GCR0_RTTOAL 0x0 - Byte Lane Single-End VREF Enable - PSU_DDR_PHY_DX2GCR4_DXREFSEN 0x1 + * RTT Output Hold + * PSU_DDR_PHY_DX3GCR0_RTTOH 0x3 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX2GCR4_RESERVED_24 0x0 + * Configurable PDR Phase Shift + * PSU_DDR_PHY_DX3GCR0_CPDRSHFT 0x0 - External VREF generator REFSEL range select - PSU_DDR_PHY_DX2GCR4_DXREFESELRANGE 0x0 + * DQSR Power Down + * PSU_DDR_PHY_DX3GCR0_DQSRPD 0x0 - Byte Lane External VREF Select - PSU_DDR_PHY_DX2GCR4_DXREFESEL 0x0 + * DQSG Power Down Receiver + * PSU_DDR_PHY_DX3GCR0_DQSGPDR 0x0 - Single ended VREF generator REFSEL range select - PSU_DDR_PHY_DX2GCR4_DXREFSSELRANGE 0x1 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX3GCR0_RESERVED_4 0x0 - Byte Lane Single-End VREF Select - PSU_DDR_PHY_DX2GCR4_DXREFSSEL 0x30 + * DQSG On-Die Termination + * PSU_DDR_PHY_DX3GCR0_DQSGODT 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX2GCR4_RESERVED_7_6 0x0 + * DQSG Output Enable + * PSU_DDR_PHY_DX3GCR0_DQSGOE 0x1 - VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. - PSU_DDR_PHY_DX2GCR4_DXREFIEN 0xf + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX3GCR0_RESERVED_1_0 0x0 - VRMON control for DQ IO (Single Ended) buffers of a byte lane. - PSU_DDR_PHY_DX2GCR4_DXREFIMON 0x0 + * DATX8 n General Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD080A00, 0xFFFFFFFFU ,0x40800604U) + */ + PSU_Mask_Write(DDR_PHY_DX3GCR0_OFFSET, 0xFFFFFFFFU, 0x40800604U); +/*##################################################################### */ - DATX8 n General Configuration Register 4 - (OFFSET, MASK, VALUE) (0XFD080910, 0xFFFFFFFFU ,0x0E00B03CU) - RegMask = (DDR_PHY_DX2GCR4_RESERVED_31_29_MASK | DDR_PHY_DX2GCR4_DXREFPEN_MASK | DDR_PHY_DX2GCR4_DXREFEEN_MASK | DDR_PHY_DX2GCR4_DXREFSEN_MASK | DDR_PHY_DX2GCR4_RESERVED_24_MASK | DDR_PHY_DX2GCR4_DXREFESELRANGE_MASK | DDR_PHY_DX2GCR4_DXREFESEL_MASK | DDR_PHY_DX2GCR4_DXREFSSELRANGE_MASK | DDR_PHY_DX2GCR4_DXREFSSEL_MASK | DDR_PHY_DX2GCR4_RESERVED_7_6_MASK | DDR_PHY_DX2GCR4_DXREFIEN_MASK | DDR_PHY_DX2GCR4_DXREFIMON_MASK | 0 ); + /* + * Register : DX3GCR1 @ 0XFD080A04 - RegVal = ((0x00000000U << DDR_PHY_DX2GCR4_RESERVED_31_29_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR4_DXREFPEN_SHIFT - | 0x00000003U << DDR_PHY_DX2GCR4_DXREFEEN_SHIFT - | 0x00000001U << DDR_PHY_DX2GCR4_DXREFSEN_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR4_RESERVED_24_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR4_DXREFESELRANGE_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR4_DXREFESEL_SHIFT - | 0x00000001U << DDR_PHY_DX2GCR4_DXREFSSELRANGE_SHIFT - | 0x00000030U << DDR_PHY_DX2GCR4_DXREFSSEL_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR4_RESERVED_7_6_SHIFT - | 0x0000000FU << DDR_PHY_DX2GCR4_DXREFIEN_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR4_DXREFIMON_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX2GCR4_OFFSET ,0xFFFFFFFFU ,0x0E00B03CU); - /*############################################################################################################################ */ + * Enables the PDR mode for DQ[7:0] + * PSU_DDR_PHY_DX3GCR1_DXPDRMODE 0x0 - /*Register : DX2GCR5 @ 0XFD080914

+ * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX3GCR1_RESERVED_15 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX2GCR5_RESERVED_31 0x0 + * Select the delayed or non-delayed read data strobe # + * PSU_DDR_PHY_DX3GCR1_QSNSEL 0x1 - Byte Lane internal VREF Select for Rank 3 - PSU_DDR_PHY_DX2GCR5_DXREFISELR3 0x9 + * Select the delayed or non-delayed read data strobe + * PSU_DDR_PHY_DX3GCR1_QSSEL 0x1 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX2GCR5_RESERVED_23 0x0 + * Enables Read Data Strobe in a byte lane + * PSU_DDR_PHY_DX3GCR1_OEEN 0x1 - Byte Lane internal VREF Select for Rank 2 - PSU_DDR_PHY_DX2GCR5_DXREFISELR2 0x9 + * Enables PDR in a byte lane + * PSU_DDR_PHY_DX3GCR1_PDREN 0x1 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX2GCR5_RESERVED_15 0x0 + * Enables ODT/TE in a byte lane + * PSU_DDR_PHY_DX3GCR1_TEEN 0x1 - Byte Lane internal VREF Select for Rank 1 - PSU_DDR_PHY_DX2GCR5_DXREFISELR1 0x4f + * Enables Write Data strobe in a byte lane + * PSU_DDR_PHY_DX3GCR1_DSEN 0x1 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX2GCR5_RESERVED_7 0x0 + * Enables DM pin in a byte lane + * PSU_DDR_PHY_DX3GCR1_DMEN 0x1 - Byte Lane internal VREF Select for Rank 0 - PSU_DDR_PHY_DX2GCR5_DXREFISELR0 0x4f + * Enables DQ corresponding to each bit in a byte + * PSU_DDR_PHY_DX3GCR1_DQEN 0xff - DATX8 n General Configuration Register 5 - (OFFSET, MASK, VALUE) (0XFD080914, 0xFFFFFFFFU ,0x09094F4FU) - RegMask = (DDR_PHY_DX2GCR5_RESERVED_31_MASK | DDR_PHY_DX2GCR5_DXREFISELR3_MASK | DDR_PHY_DX2GCR5_RESERVED_23_MASK | DDR_PHY_DX2GCR5_DXREFISELR2_MASK | DDR_PHY_DX2GCR5_RESERVED_15_MASK | DDR_PHY_DX2GCR5_DXREFISELR1_MASK | DDR_PHY_DX2GCR5_RESERVED_7_MASK | DDR_PHY_DX2GCR5_DXREFISELR0_MASK | 0 ); + * DATX8 n General Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD080A04, 0xFFFFFFFFU ,0x00007FFFU) + */ + PSU_Mask_Write(DDR_PHY_DX3GCR1_OFFSET, 0xFFFFFFFFU, 0x00007FFFU); +/*##################################################################### */ - RegVal = ((0x00000000U << DDR_PHY_DX2GCR5_RESERVED_31_SHIFT - | 0x00000009U << DDR_PHY_DX2GCR5_DXREFISELR3_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR5_RESERVED_23_SHIFT - | 0x00000009U << DDR_PHY_DX2GCR5_DXREFISELR2_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR5_RESERVED_15_SHIFT - | 0x0000004FU << DDR_PHY_DX2GCR5_DXREFISELR1_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR5_RESERVED_7_SHIFT - | 0x0000004FU << DDR_PHY_DX2GCR5_DXREFISELR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX2GCR5_OFFSET ,0xFFFFFFFFU ,0x09094F4FU); - /*############################################################################################################################ */ + /* + * Register : DX3GCR4 @ 0XFD080A10 - /*Register : DX2GCR6 @ 0XFD080918

+ * Byte lane VREF IOM (Used only by D4MU IOs) + * PSU_DDR_PHY_DX3GCR4_RESERVED_31_29 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX2GCR6_RESERVED_31_30 0x0 + * Byte Lane VREF Pad Enable + * PSU_DDR_PHY_DX3GCR4_DXREFPEN 0x0 - DRAM DQ VREF Select for Rank3 - PSU_DDR_PHY_DX2GCR6_DXDQVREFR3 0x9 + * Byte Lane Internal VREF Enable + * PSU_DDR_PHY_DX3GCR4_DXREFEEN 0x3 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX2GCR6_RESERVED_23_22 0x0 + * Byte Lane Single-End VREF Enable + * PSU_DDR_PHY_DX3GCR4_DXREFSEN 0x1 - DRAM DQ VREF Select for Rank2 - PSU_DDR_PHY_DX2GCR6_DXDQVREFR2 0x9 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX3GCR4_RESERVED_24 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX2GCR6_RESERVED_15_14 0x0 + * External VREF generator REFSEL range select + * PSU_DDR_PHY_DX3GCR4_DXREFESELRANGE 0x0 - DRAM DQ VREF Select for Rank1 - PSU_DDR_PHY_DX2GCR6_DXDQVREFR1 0x2b + * Byte Lane External VREF Select + * PSU_DDR_PHY_DX3GCR4_DXREFESEL 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX2GCR6_RESERVED_7_6 0x0 + * Single ended VREF generator REFSEL range select + * PSU_DDR_PHY_DX3GCR4_DXREFSSELRANGE 0x1 - DRAM DQ VREF Select for Rank0 - PSU_DDR_PHY_DX2GCR6_DXDQVREFR0 0x2b + * Byte Lane Single-End VREF Select + * PSU_DDR_PHY_DX3GCR4_DXREFSSEL 0x30 - DATX8 n General Configuration Register 6 - (OFFSET, MASK, VALUE) (0XFD080918, 0xFFFFFFFFU ,0x09092B2BU) - RegMask = (DDR_PHY_DX2GCR6_RESERVED_31_30_MASK | DDR_PHY_DX2GCR6_DXDQVREFR3_MASK | DDR_PHY_DX2GCR6_RESERVED_23_22_MASK | DDR_PHY_DX2GCR6_DXDQVREFR2_MASK | DDR_PHY_DX2GCR6_RESERVED_15_14_MASK | DDR_PHY_DX2GCR6_DXDQVREFR1_MASK | DDR_PHY_DX2GCR6_RESERVED_7_6_MASK | DDR_PHY_DX2GCR6_DXDQVREFR0_MASK | 0 ); + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX3GCR4_RESERVED_7_6 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX2GCR6_RESERVED_31_30_SHIFT - | 0x00000009U << DDR_PHY_DX2GCR6_DXDQVREFR3_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR6_RESERVED_23_22_SHIFT - | 0x00000009U << DDR_PHY_DX2GCR6_DXDQVREFR2_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR6_RESERVED_15_14_SHIFT - | 0x0000002BU << DDR_PHY_DX2GCR6_DXDQVREFR1_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR6_RESERVED_7_6_SHIFT - | 0x0000002BU << DDR_PHY_DX2GCR6_DXDQVREFR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX2GCR6_OFFSET ,0xFFFFFFFFU ,0x09092B2BU); - /*############################################################################################################################ */ + * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX3GCR4_DXREFIEN 0xf - /*Register : DX2LCDLR2 @ 0XFD080988

+ * VRMON control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX3GCR4_DXREFIMON 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX2LCDLR2_RESERVED_31_25 0x0 + * DATX8 n General Configuration Register 4 + * (OFFSET, MASK, VALUE) (0XFD080A10, 0xFFFFFFFFU ,0x0E00B03CU) + */ + PSU_Mask_Write(DDR_PHY_DX3GCR4_OFFSET, 0xFFFFFFFFU, 0x0E00B03CU); +/*##################################################################### */ - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX2LCDLR2_RESERVED_24_16 0x0 + /* + * Register : DX3GCR5 @ 0XFD080A14 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX2LCDLR2_RESERVED_15_9 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX3GCR5_RESERVED_31 0x0 - Read DQS Gating Delay - PSU_DDR_PHY_DX2LCDLR2_DQSGD 0x0 + * Byte Lane internal VREF Select for Rank 3 + * PSU_DDR_PHY_DX3GCR5_DXREFISELR3 0x9 - DATX8 n Local Calibrated Delay Line Register 2 - (OFFSET, MASK, VALUE) (0XFD080988, 0xFFFFFFFFU ,0x00000000U) - RegMask = (DDR_PHY_DX2LCDLR2_RESERVED_31_25_MASK | DDR_PHY_DX2LCDLR2_RESERVED_24_16_MASK | DDR_PHY_DX2LCDLR2_RESERVED_15_9_MASK | DDR_PHY_DX2LCDLR2_DQSGD_MASK | 0 ); + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX3GCR5_RESERVED_23 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX2LCDLR2_RESERVED_31_25_SHIFT - | 0x00000000U << DDR_PHY_DX2LCDLR2_RESERVED_24_16_SHIFT - | 0x00000000U << DDR_PHY_DX2LCDLR2_RESERVED_15_9_SHIFT - | 0x00000000U << DDR_PHY_DX2LCDLR2_DQSGD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX2LCDLR2_OFFSET ,0xFFFFFFFFU ,0x00000000U); - /*############################################################################################################################ */ + * Byte Lane internal VREF Select for Rank 2 + * PSU_DDR_PHY_DX3GCR5_DXREFISELR2 0x9 - /*Register : DX2GTR0 @ 0XFD0809C0

+ * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX3GCR5_RESERVED_15 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX2GTR0_RESERVED_31_24 0x0 + * Byte Lane internal VREF Select for Rank 1 + * PSU_DDR_PHY_DX3GCR5_DXREFISELR1 0x55 - DQ Write Path Latency Pipeline - PSU_DDR_PHY_DX2GTR0_WDQSL 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX3GCR5_RESERVED_7 0x0 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX2GTR0_RESERVED_23_20 0x0 + * Byte Lane internal VREF Select for Rank 0 + * PSU_DDR_PHY_DX3GCR5_DXREFISELR0 0x55 - Write Leveling System Latency - PSU_DDR_PHY_DX2GTR0_WLSL 0x2 + * DATX8 n General Configuration Register 5 + * (OFFSET, MASK, VALUE) (0XFD080A14, 0xFFFFFFFFU ,0x09095555U) + */ + PSU_Mask_Write(DDR_PHY_DX3GCR5_OFFSET, 0xFFFFFFFFU, 0x09095555U); +/*##################################################################### */ - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX2GTR0_RESERVED_15_13 0x0 + /* + * Register : DX3GCR6 @ 0XFD080A18 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX2GTR0_RESERVED_12_8 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX3GCR6_RESERVED_31_30 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX2GTR0_RESERVED_7_5 0x0 + * DRAM DQ VREF Select for Rank3 + * PSU_DDR_PHY_DX3GCR6_DXDQVREFR3 0x9 - DQS Gating System Latency - PSU_DDR_PHY_DX2GTR0_DGSL 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX3GCR6_RESERVED_23_22 0x0 - DATX8 n General Timing Register 0 - (OFFSET, MASK, VALUE) (0XFD0809C0, 0xFFFFFFFFU ,0x00020000U) - RegMask = (DDR_PHY_DX2GTR0_RESERVED_31_24_MASK | DDR_PHY_DX2GTR0_WDQSL_MASK | DDR_PHY_DX2GTR0_RESERVED_23_20_MASK | DDR_PHY_DX2GTR0_WLSL_MASK | DDR_PHY_DX2GTR0_RESERVED_15_13_MASK | DDR_PHY_DX2GTR0_RESERVED_12_8_MASK | DDR_PHY_DX2GTR0_RESERVED_7_5_MASK | DDR_PHY_DX2GTR0_DGSL_MASK | 0 ); + * DRAM DQ VREF Select for Rank2 + * PSU_DDR_PHY_DX3GCR6_DXDQVREFR2 0x9 - RegVal = ((0x00000000U << DDR_PHY_DX2GTR0_RESERVED_31_24_SHIFT - | 0x00000000U << DDR_PHY_DX2GTR0_WDQSL_SHIFT - | 0x00000000U << DDR_PHY_DX2GTR0_RESERVED_23_20_SHIFT - | 0x00000002U << DDR_PHY_DX2GTR0_WLSL_SHIFT - | 0x00000000U << DDR_PHY_DX2GTR0_RESERVED_15_13_SHIFT - | 0x00000000U << DDR_PHY_DX2GTR0_RESERVED_12_8_SHIFT - | 0x00000000U << DDR_PHY_DX2GTR0_RESERVED_7_5_SHIFT - | 0x00000000U << DDR_PHY_DX2GTR0_DGSL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX2GTR0_OFFSET ,0xFFFFFFFFU ,0x00020000U); - /*############################################################################################################################ */ + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX3GCR6_RESERVED_15_14 0x0 - /*Register : DX3GCR0 @ 0XFD080A00

+ * DRAM DQ VREF Select for Rank1 + * PSU_DDR_PHY_DX3GCR6_DXDQVREFR1 0x2b - Calibration Bypass - PSU_DDR_PHY_DX3GCR0_CALBYP 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX3GCR6_RESERVED_7_6 0x0 - Master Delay Line Enable - PSU_DDR_PHY_DX3GCR0_MDLEN 0x1 + * DRAM DQ VREF Select for Rank0 + * PSU_DDR_PHY_DX3GCR6_DXDQVREFR0 0x2b - Configurable ODT(TE) Phase Shift - PSU_DDR_PHY_DX3GCR0_CODTSHFT 0x0 + * DATX8 n General Configuration Register 6 + * (OFFSET, MASK, VALUE) (0XFD080A18, 0xFFFFFFFFU ,0x09092B2BU) + */ + PSU_Mask_Write(DDR_PHY_DX3GCR6_OFFSET, 0xFFFFFFFFU, 0x09092B2BU); +/*##################################################################### */ - DQS Duty Cycle Correction - PSU_DDR_PHY_DX3GCR0_DQSDCC 0x0 + /* + * Register : DX4GCR0 @ 0XFD080B00 - Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY - PSU_DDR_PHY_DX3GCR0_RDDLY 0x8 + * Calibration Bypass + * PSU_DDR_PHY_DX4GCR0_CALBYP 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX3GCR0_RESERVED_19_14 0x0 + * Master Delay Line Enable + * PSU_DDR_PHY_DX4GCR0_MDLEN 0x1 - DQSNSE Power Down Receiver - PSU_DDR_PHY_DX3GCR0_DQSNSEPDR 0x0 + * Configurable ODT(TE) Phase Shift + * PSU_DDR_PHY_DX4GCR0_CODTSHFT 0x0 - DQSSE Power Down Receiver - PSU_DDR_PHY_DX3GCR0_DQSSEPDR 0x0 + * DQS Duty Cycle Correction + * PSU_DDR_PHY_DX4GCR0_DQSDCC 0x0 - RTT On Additive Latency - PSU_DDR_PHY_DX3GCR0_RTTOAL 0x0 + * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY + * PSU_DDR_PHY_DX4GCR0_RDDLY 0x8 - RTT Output Hold - PSU_DDR_PHY_DX3GCR0_RTTOH 0x3 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX4GCR0_RESERVED_19_14 0x0 - Configurable PDR Phase Shift - PSU_DDR_PHY_DX3GCR0_CPDRSHFT 0x0 + * DQSNSE Power Down Receiver + * PSU_DDR_PHY_DX4GCR0_DQSNSEPDR 0x0 - DQSR Power Down - PSU_DDR_PHY_DX3GCR0_DQSRPD 0x0 + * DQSSE Power Down Receiver + * PSU_DDR_PHY_DX4GCR0_DQSSEPDR 0x0 - DQSG Power Down Receiver - PSU_DDR_PHY_DX3GCR0_DQSGPDR 0x0 + * RTT On Additive Latency + * PSU_DDR_PHY_DX4GCR0_RTTOAL 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX3GCR0_RESERVED_4 0x0 + * RTT Output Hold + * PSU_DDR_PHY_DX4GCR0_RTTOH 0x3 - DQSG On-Die Termination - PSU_DDR_PHY_DX3GCR0_DQSGODT 0x0 + * Configurable PDR Phase Shift + * PSU_DDR_PHY_DX4GCR0_CPDRSHFT 0x0 - DQSG Output Enable - PSU_DDR_PHY_DX3GCR0_DQSGOE 0x1 + * DQSR Power Down + * PSU_DDR_PHY_DX4GCR0_DQSRPD 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX3GCR0_RESERVED_1_0 0x0 + * DQSG Power Down Receiver + * PSU_DDR_PHY_DX4GCR0_DQSGPDR 0x0 - DATX8 n General Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD080A00, 0xFFFFFFFFU ,0x40800604U) - RegMask = (DDR_PHY_DX3GCR0_CALBYP_MASK | DDR_PHY_DX3GCR0_MDLEN_MASK | DDR_PHY_DX3GCR0_CODTSHFT_MASK | DDR_PHY_DX3GCR0_DQSDCC_MASK | DDR_PHY_DX3GCR0_RDDLY_MASK | DDR_PHY_DX3GCR0_RESERVED_19_14_MASK | DDR_PHY_DX3GCR0_DQSNSEPDR_MASK | DDR_PHY_DX3GCR0_DQSSEPDR_MASK | DDR_PHY_DX3GCR0_RTTOAL_MASK | DDR_PHY_DX3GCR0_RTTOH_MASK | DDR_PHY_DX3GCR0_CPDRSHFT_MASK | DDR_PHY_DX3GCR0_DQSRPD_MASK | DDR_PHY_DX3GCR0_DQSGPDR_MASK | DDR_PHY_DX3GCR0_RESERVED_4_MASK | DDR_PHY_DX3GCR0_DQSGODT_MASK | DDR_PHY_DX3GCR0_DQSGOE_MASK | DDR_PHY_DX3GCR0_RESERVED_1_0_MASK | 0 ); + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX4GCR0_RESERVED_4 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX3GCR0_CALBYP_SHIFT - | 0x00000001U << DDR_PHY_DX3GCR0_MDLEN_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR0_CODTSHFT_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR0_DQSDCC_SHIFT - | 0x00000008U << DDR_PHY_DX3GCR0_RDDLY_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR0_RESERVED_19_14_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR0_DQSNSEPDR_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR0_DQSSEPDR_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR0_RTTOAL_SHIFT - | 0x00000003U << DDR_PHY_DX3GCR0_RTTOH_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR0_CPDRSHFT_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR0_DQSRPD_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR0_DQSGPDR_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR0_RESERVED_4_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR0_DQSGODT_SHIFT - | 0x00000001U << DDR_PHY_DX3GCR0_DQSGOE_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR0_RESERVED_1_0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX3GCR0_OFFSET ,0xFFFFFFFFU ,0x40800604U); - /*############################################################################################################################ */ + * DQSG On-Die Termination + * PSU_DDR_PHY_DX4GCR0_DQSGODT 0x0 - /*Register : DX3GCR1 @ 0XFD080A04

+ * DQSG Output Enable + * PSU_DDR_PHY_DX4GCR0_DQSGOE 0x1 - Enables the PDR mode for DQ[7:0] - PSU_DDR_PHY_DX3GCR1_DXPDRMODE 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX4GCR0_RESERVED_1_0 0x0 - Reserved. Returns zeroes on reads. - PSU_DDR_PHY_DX3GCR1_RESERVED_15 0x0 + * DATX8 n General Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD080B00, 0xFFFFFFFFU ,0x40800604U) + */ + PSU_Mask_Write(DDR_PHY_DX4GCR0_OFFSET, 0xFFFFFFFFU, 0x40800604U); +/*##################################################################### */ - Select the delayed or non-delayed read data strobe # - PSU_DDR_PHY_DX3GCR1_QSNSEL 0x1 + /* + * Register : DX4GCR1 @ 0XFD080B04 - Select the delayed or non-delayed read data strobe - PSU_DDR_PHY_DX3GCR1_QSSEL 0x1 + * Enables the PDR mode for DQ[7:0] + * PSU_DDR_PHY_DX4GCR1_DXPDRMODE 0x0 - Enables Read Data Strobe in a byte lane - PSU_DDR_PHY_DX3GCR1_OEEN 0x1 + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX4GCR1_RESERVED_15 0x0 - Enables PDR in a byte lane - PSU_DDR_PHY_DX3GCR1_PDREN 0x1 + * Select the delayed or non-delayed read data strobe # + * PSU_DDR_PHY_DX4GCR1_QSNSEL 0x1 - Enables ODT/TE in a byte lane - PSU_DDR_PHY_DX3GCR1_TEEN 0x1 + * Select the delayed or non-delayed read data strobe + * PSU_DDR_PHY_DX4GCR1_QSSEL 0x1 - Enables Write Data strobe in a byte lane - PSU_DDR_PHY_DX3GCR1_DSEN 0x1 + * Enables Read Data Strobe in a byte lane + * PSU_DDR_PHY_DX4GCR1_OEEN 0x1 - Enables DM pin in a byte lane - PSU_DDR_PHY_DX3GCR1_DMEN 0x1 + * Enables PDR in a byte lane + * PSU_DDR_PHY_DX4GCR1_PDREN 0x1 - Enables DQ corresponding to each bit in a byte - PSU_DDR_PHY_DX3GCR1_DQEN 0xff + * Enables ODT/TE in a byte lane + * PSU_DDR_PHY_DX4GCR1_TEEN 0x1 - DATX8 n General Configuration Register 1 - (OFFSET, MASK, VALUE) (0XFD080A04, 0xFFFFFFFFU ,0x00007FFFU) - RegMask = (DDR_PHY_DX3GCR1_DXPDRMODE_MASK | DDR_PHY_DX3GCR1_RESERVED_15_MASK | DDR_PHY_DX3GCR1_QSNSEL_MASK | DDR_PHY_DX3GCR1_QSSEL_MASK | DDR_PHY_DX3GCR1_OEEN_MASK | DDR_PHY_DX3GCR1_PDREN_MASK | DDR_PHY_DX3GCR1_TEEN_MASK | DDR_PHY_DX3GCR1_DSEN_MASK | DDR_PHY_DX3GCR1_DMEN_MASK | DDR_PHY_DX3GCR1_DQEN_MASK | 0 ); + * Enables Write Data strobe in a byte lane + * PSU_DDR_PHY_DX4GCR1_DSEN 0x1 - RegVal = ((0x00000000U << DDR_PHY_DX3GCR1_DXPDRMODE_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR1_RESERVED_15_SHIFT - | 0x00000001U << DDR_PHY_DX3GCR1_QSNSEL_SHIFT - | 0x00000001U << DDR_PHY_DX3GCR1_QSSEL_SHIFT - | 0x00000001U << DDR_PHY_DX3GCR1_OEEN_SHIFT - | 0x00000001U << DDR_PHY_DX3GCR1_PDREN_SHIFT - | 0x00000001U << DDR_PHY_DX3GCR1_TEEN_SHIFT - | 0x00000001U << DDR_PHY_DX3GCR1_DSEN_SHIFT - | 0x00000001U << DDR_PHY_DX3GCR1_DMEN_SHIFT - | 0x000000FFU << DDR_PHY_DX3GCR1_DQEN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX3GCR1_OFFSET ,0xFFFFFFFFU ,0x00007FFFU); - /*############################################################################################################################ */ + * Enables DM pin in a byte lane + * PSU_DDR_PHY_DX4GCR1_DMEN 0x1 - /*Register : DX3GCR4 @ 0XFD080A10

+ * Enables DQ corresponding to each bit in a byte + * PSU_DDR_PHY_DX4GCR1_DQEN 0xff - Byte lane VREF IOM (Used only by D4MU IOs) - PSU_DDR_PHY_DX3GCR4_RESERVED_31_29 0x0 + * DATX8 n General Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD080B04, 0xFFFFFFFFU ,0x00007FFFU) + */ + PSU_Mask_Write(DDR_PHY_DX4GCR1_OFFSET, 0xFFFFFFFFU, 0x00007FFFU); +/*##################################################################### */ - Byte Lane VREF Pad Enable - PSU_DDR_PHY_DX3GCR4_DXREFPEN 0x0 + /* + * Register : DX4GCR4 @ 0XFD080B10 - Byte Lane Internal VREF Enable - PSU_DDR_PHY_DX3GCR4_DXREFEEN 0x3 + * Byte lane VREF IOM (Used only by D4MU IOs) + * PSU_DDR_PHY_DX4GCR4_RESERVED_31_29 0x0 - Byte Lane Single-End VREF Enable - PSU_DDR_PHY_DX3GCR4_DXREFSEN 0x1 + * Byte Lane VREF Pad Enable + * PSU_DDR_PHY_DX4GCR4_DXREFPEN 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX3GCR4_RESERVED_24 0x0 + * Byte Lane Internal VREF Enable + * PSU_DDR_PHY_DX4GCR4_DXREFEEN 0x3 - External VREF generator REFSEL range select - PSU_DDR_PHY_DX3GCR4_DXREFESELRANGE 0x0 + * Byte Lane Single-End VREF Enable + * PSU_DDR_PHY_DX4GCR4_DXREFSEN 0x1 - Byte Lane External VREF Select - PSU_DDR_PHY_DX3GCR4_DXREFESEL 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX4GCR4_RESERVED_24 0x0 - Single ended VREF generator REFSEL range select - PSU_DDR_PHY_DX3GCR4_DXREFSSELRANGE 0x1 + * External VREF generator REFSEL range select + * PSU_DDR_PHY_DX4GCR4_DXREFESELRANGE 0x0 - Byte Lane Single-End VREF Select - PSU_DDR_PHY_DX3GCR4_DXREFSSEL 0x30 + * Byte Lane External VREF Select + * PSU_DDR_PHY_DX4GCR4_DXREFESEL 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX3GCR4_RESERVED_7_6 0x0 + * Single ended VREF generator REFSEL range select + * PSU_DDR_PHY_DX4GCR4_DXREFSSELRANGE 0x1 - VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. - PSU_DDR_PHY_DX3GCR4_DXREFIEN 0xf + * Byte Lane Single-End VREF Select + * PSU_DDR_PHY_DX4GCR4_DXREFSSEL 0x30 - VRMON control for DQ IO (Single Ended) buffers of a byte lane. - PSU_DDR_PHY_DX3GCR4_DXREFIMON 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX4GCR4_RESERVED_7_6 0x0 - DATX8 n General Configuration Register 4 - (OFFSET, MASK, VALUE) (0XFD080A10, 0xFFFFFFFFU ,0x0E00B03CU) - RegMask = (DDR_PHY_DX3GCR4_RESERVED_31_29_MASK | DDR_PHY_DX3GCR4_DXREFPEN_MASK | DDR_PHY_DX3GCR4_DXREFEEN_MASK | DDR_PHY_DX3GCR4_DXREFSEN_MASK | DDR_PHY_DX3GCR4_RESERVED_24_MASK | DDR_PHY_DX3GCR4_DXREFESELRANGE_MASK | DDR_PHY_DX3GCR4_DXREFESEL_MASK | DDR_PHY_DX3GCR4_DXREFSSELRANGE_MASK | DDR_PHY_DX3GCR4_DXREFSSEL_MASK | DDR_PHY_DX3GCR4_RESERVED_7_6_MASK | DDR_PHY_DX3GCR4_DXREFIEN_MASK | DDR_PHY_DX3GCR4_DXREFIMON_MASK | 0 ); + * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX4GCR4_DXREFIEN 0xf - RegVal = ((0x00000000U << DDR_PHY_DX3GCR4_RESERVED_31_29_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR4_DXREFPEN_SHIFT - | 0x00000003U << DDR_PHY_DX3GCR4_DXREFEEN_SHIFT - | 0x00000001U << DDR_PHY_DX3GCR4_DXREFSEN_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR4_RESERVED_24_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR4_DXREFESELRANGE_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR4_DXREFESEL_SHIFT - | 0x00000001U << DDR_PHY_DX3GCR4_DXREFSSELRANGE_SHIFT - | 0x00000030U << DDR_PHY_DX3GCR4_DXREFSSEL_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR4_RESERVED_7_6_SHIFT - | 0x0000000FU << DDR_PHY_DX3GCR4_DXREFIEN_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR4_DXREFIMON_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX3GCR4_OFFSET ,0xFFFFFFFFU ,0x0E00B03CU); - /*############################################################################################################################ */ + * VRMON control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX4GCR4_DXREFIMON 0x0 - /*Register : DX3GCR5 @ 0XFD080A14

+ * DATX8 n General Configuration Register 4 + * (OFFSET, MASK, VALUE) (0XFD080B10, 0xFFFFFFFFU ,0x0E00B03CU) + */ + PSU_Mask_Write(DDR_PHY_DX4GCR4_OFFSET, 0xFFFFFFFFU, 0x0E00B03CU); +/*##################################################################### */ - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX3GCR5_RESERVED_31 0x0 + /* + * Register : DX4GCR5 @ 0XFD080B14 - Byte Lane internal VREF Select for Rank 3 - PSU_DDR_PHY_DX3GCR5_DXREFISELR3 0x9 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX4GCR5_RESERVED_31 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX3GCR5_RESERVED_23 0x0 + * Byte Lane internal VREF Select for Rank 3 + * PSU_DDR_PHY_DX4GCR5_DXREFISELR3 0x9 - Byte Lane internal VREF Select for Rank 2 - PSU_DDR_PHY_DX3GCR5_DXREFISELR2 0x9 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX4GCR5_RESERVED_23 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX3GCR5_RESERVED_15 0x0 + * Byte Lane internal VREF Select for Rank 2 + * PSU_DDR_PHY_DX4GCR5_DXREFISELR2 0x9 - Byte Lane internal VREF Select for Rank 1 - PSU_DDR_PHY_DX3GCR5_DXREFISELR1 0x4f + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX4GCR5_RESERVED_15 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX3GCR5_RESERVED_7 0x0 + * Byte Lane internal VREF Select for Rank 1 + * PSU_DDR_PHY_DX4GCR5_DXREFISELR1 0x55 - Byte Lane internal VREF Select for Rank 0 - PSU_DDR_PHY_DX3GCR5_DXREFISELR0 0x4f + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX4GCR5_RESERVED_7 0x0 - DATX8 n General Configuration Register 5 - (OFFSET, MASK, VALUE) (0XFD080A14, 0xFFFFFFFFU ,0x09094F4FU) - RegMask = (DDR_PHY_DX3GCR5_RESERVED_31_MASK | DDR_PHY_DX3GCR5_DXREFISELR3_MASK | DDR_PHY_DX3GCR5_RESERVED_23_MASK | DDR_PHY_DX3GCR5_DXREFISELR2_MASK | DDR_PHY_DX3GCR5_RESERVED_15_MASK | DDR_PHY_DX3GCR5_DXREFISELR1_MASK | DDR_PHY_DX3GCR5_RESERVED_7_MASK | DDR_PHY_DX3GCR5_DXREFISELR0_MASK | 0 ); + * Byte Lane internal VREF Select for Rank 0 + * PSU_DDR_PHY_DX4GCR5_DXREFISELR0 0x55 - RegVal = ((0x00000000U << DDR_PHY_DX3GCR5_RESERVED_31_SHIFT - | 0x00000009U << DDR_PHY_DX3GCR5_DXREFISELR3_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR5_RESERVED_23_SHIFT - | 0x00000009U << DDR_PHY_DX3GCR5_DXREFISELR2_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR5_RESERVED_15_SHIFT - | 0x0000004FU << DDR_PHY_DX3GCR5_DXREFISELR1_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR5_RESERVED_7_SHIFT - | 0x0000004FU << DDR_PHY_DX3GCR5_DXREFISELR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX3GCR5_OFFSET ,0xFFFFFFFFU ,0x09094F4FU); - /*############################################################################################################################ */ + * DATX8 n General Configuration Register 5 + * (OFFSET, MASK, VALUE) (0XFD080B14, 0xFFFFFFFFU ,0x09095555U) + */ + PSU_Mask_Write(DDR_PHY_DX4GCR5_OFFSET, 0xFFFFFFFFU, 0x09095555U); +/*##################################################################### */ - /*Register : DX3GCR6 @ 0XFD080A18

+ /* + * Register : DX4GCR6 @ 0XFD080B18 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX3GCR6_RESERVED_31_30 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX4GCR6_RESERVED_31_30 0x0 - DRAM DQ VREF Select for Rank3 - PSU_DDR_PHY_DX3GCR6_DXDQVREFR3 0x9 + * DRAM DQ VREF Select for Rank3 + * PSU_DDR_PHY_DX4GCR6_DXDQVREFR3 0x9 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX3GCR6_RESERVED_23_22 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX4GCR6_RESERVED_23_22 0x0 - DRAM DQ VREF Select for Rank2 - PSU_DDR_PHY_DX3GCR6_DXDQVREFR2 0x9 + * DRAM DQ VREF Select for Rank2 + * PSU_DDR_PHY_DX4GCR6_DXDQVREFR2 0x9 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX3GCR6_RESERVED_15_14 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX4GCR6_RESERVED_15_14 0x0 - DRAM DQ VREF Select for Rank1 - PSU_DDR_PHY_DX3GCR6_DXDQVREFR1 0x2b + * DRAM DQ VREF Select for Rank1 + * PSU_DDR_PHY_DX4GCR6_DXDQVREFR1 0x2b - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX3GCR6_RESERVED_7_6 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX4GCR6_RESERVED_7_6 0x0 - DRAM DQ VREF Select for Rank0 - PSU_DDR_PHY_DX3GCR6_DXDQVREFR0 0x2b + * DRAM DQ VREF Select for Rank0 + * PSU_DDR_PHY_DX4GCR6_DXDQVREFR0 0x2b - DATX8 n General Configuration Register 6 - (OFFSET, MASK, VALUE) (0XFD080A18, 0xFFFFFFFFU ,0x09092B2BU) - RegMask = (DDR_PHY_DX3GCR6_RESERVED_31_30_MASK | DDR_PHY_DX3GCR6_DXDQVREFR3_MASK | DDR_PHY_DX3GCR6_RESERVED_23_22_MASK | DDR_PHY_DX3GCR6_DXDQVREFR2_MASK | DDR_PHY_DX3GCR6_RESERVED_15_14_MASK | DDR_PHY_DX3GCR6_DXDQVREFR1_MASK | DDR_PHY_DX3GCR6_RESERVED_7_6_MASK | DDR_PHY_DX3GCR6_DXDQVREFR0_MASK | 0 ); + * DATX8 n General Configuration Register 6 + * (OFFSET, MASK, VALUE) (0XFD080B18, 0xFFFFFFFFU ,0x09092B2BU) + */ + PSU_Mask_Write(DDR_PHY_DX4GCR6_OFFSET, 0xFFFFFFFFU, 0x09092B2BU); +/*##################################################################### */ - RegVal = ((0x00000000U << DDR_PHY_DX3GCR6_RESERVED_31_30_SHIFT - | 0x00000009U << DDR_PHY_DX3GCR6_DXDQVREFR3_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR6_RESERVED_23_22_SHIFT - | 0x00000009U << DDR_PHY_DX3GCR6_DXDQVREFR2_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR6_RESERVED_15_14_SHIFT - | 0x0000002BU << DDR_PHY_DX3GCR6_DXDQVREFR1_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR6_RESERVED_7_6_SHIFT - | 0x0000002BU << DDR_PHY_DX3GCR6_DXDQVREFR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX3GCR6_OFFSET ,0xFFFFFFFFU ,0x09092B2BU); - /*############################################################################################################################ */ + /* + * Register : DX5GCR0 @ 0XFD080C00 - /*Register : DX3LCDLR2 @ 0XFD080A88

+ * Calibration Bypass + * PSU_DDR_PHY_DX5GCR0_CALBYP 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX3LCDLR2_RESERVED_31_25 0x0 + * Master Delay Line Enable + * PSU_DDR_PHY_DX5GCR0_MDLEN 0x1 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX3LCDLR2_RESERVED_24_16 0x0 + * Configurable ODT(TE) Phase Shift + * PSU_DDR_PHY_DX5GCR0_CODTSHFT 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX3LCDLR2_RESERVED_15_9 0x0 + * DQS Duty Cycle Correction + * PSU_DDR_PHY_DX5GCR0_DQSDCC 0x0 - Read DQS Gating Delay - PSU_DDR_PHY_DX3LCDLR2_DQSGD 0x0 + * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY + * PSU_DDR_PHY_DX5GCR0_RDDLY 0x8 - DATX8 n Local Calibrated Delay Line Register 2 - (OFFSET, MASK, VALUE) (0XFD080A88, 0xFFFFFFFFU ,0x00000000U) - RegMask = (DDR_PHY_DX3LCDLR2_RESERVED_31_25_MASK | DDR_PHY_DX3LCDLR2_RESERVED_24_16_MASK | DDR_PHY_DX3LCDLR2_RESERVED_15_9_MASK | DDR_PHY_DX3LCDLR2_DQSGD_MASK | 0 ); + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX5GCR0_RESERVED_19_14 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX3LCDLR2_RESERVED_31_25_SHIFT - | 0x00000000U << DDR_PHY_DX3LCDLR2_RESERVED_24_16_SHIFT - | 0x00000000U << DDR_PHY_DX3LCDLR2_RESERVED_15_9_SHIFT - | 0x00000000U << DDR_PHY_DX3LCDLR2_DQSGD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX3LCDLR2_OFFSET ,0xFFFFFFFFU ,0x00000000U); - /*############################################################################################################################ */ + * DQSNSE Power Down Receiver + * PSU_DDR_PHY_DX5GCR0_DQSNSEPDR 0x0 - /*Register : DX3GTR0 @ 0XFD080AC0

+ * DQSSE Power Down Receiver + * PSU_DDR_PHY_DX5GCR0_DQSSEPDR 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX3GTR0_RESERVED_31_24 0x0 + * RTT On Additive Latency + * PSU_DDR_PHY_DX5GCR0_RTTOAL 0x0 - DQ Write Path Latency Pipeline - PSU_DDR_PHY_DX3GTR0_WDQSL 0x0 + * RTT Output Hold + * PSU_DDR_PHY_DX5GCR0_RTTOH 0x3 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX3GTR0_RESERVED_23_20 0x0 + * Configurable PDR Phase Shift + * PSU_DDR_PHY_DX5GCR0_CPDRSHFT 0x0 - Write Leveling System Latency - PSU_DDR_PHY_DX3GTR0_WLSL 0x2 + * DQSR Power Down + * PSU_DDR_PHY_DX5GCR0_DQSRPD 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX3GTR0_RESERVED_15_13 0x0 + * DQSG Power Down Receiver + * PSU_DDR_PHY_DX5GCR0_DQSGPDR 0x0 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX3GTR0_RESERVED_12_8 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX5GCR0_RESERVED_4 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX3GTR0_RESERVED_7_5 0x0 + * DQSG On-Die Termination + * PSU_DDR_PHY_DX5GCR0_DQSGODT 0x0 - DQS Gating System Latency - PSU_DDR_PHY_DX3GTR0_DGSL 0x0 + * DQSG Output Enable + * PSU_DDR_PHY_DX5GCR0_DQSGOE 0x1 - DATX8 n General Timing Register 0 - (OFFSET, MASK, VALUE) (0XFD080AC0, 0xFFFFFFFFU ,0x00020000U) - RegMask = (DDR_PHY_DX3GTR0_RESERVED_31_24_MASK | DDR_PHY_DX3GTR0_WDQSL_MASK | DDR_PHY_DX3GTR0_RESERVED_23_20_MASK | DDR_PHY_DX3GTR0_WLSL_MASK | DDR_PHY_DX3GTR0_RESERVED_15_13_MASK | DDR_PHY_DX3GTR0_RESERVED_12_8_MASK | DDR_PHY_DX3GTR0_RESERVED_7_5_MASK | DDR_PHY_DX3GTR0_DGSL_MASK | 0 ); + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX5GCR0_RESERVED_1_0 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX3GTR0_RESERVED_31_24_SHIFT - | 0x00000000U << DDR_PHY_DX3GTR0_WDQSL_SHIFT - | 0x00000000U << DDR_PHY_DX3GTR0_RESERVED_23_20_SHIFT - | 0x00000002U << DDR_PHY_DX3GTR0_WLSL_SHIFT - | 0x00000000U << DDR_PHY_DX3GTR0_RESERVED_15_13_SHIFT - | 0x00000000U << DDR_PHY_DX3GTR0_RESERVED_12_8_SHIFT - | 0x00000000U << DDR_PHY_DX3GTR0_RESERVED_7_5_SHIFT - | 0x00000000U << DDR_PHY_DX3GTR0_DGSL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX3GTR0_OFFSET ,0xFFFFFFFFU ,0x00020000U); - /*############################################################################################################################ */ + * DATX8 n General Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD080C00, 0xFFFFFFFFU ,0x40800604U) + */ + PSU_Mask_Write(DDR_PHY_DX5GCR0_OFFSET, 0xFFFFFFFFU, 0x40800604U); +/*##################################################################### */ - /*Register : DX4GCR0 @ 0XFD080B00

+ /* + * Register : DX5GCR1 @ 0XFD080C04 - Calibration Bypass - PSU_DDR_PHY_DX4GCR0_CALBYP 0x0 + * Enables the PDR mode for DQ[7:0] + * PSU_DDR_PHY_DX5GCR1_DXPDRMODE 0x0 - Master Delay Line Enable - PSU_DDR_PHY_DX4GCR0_MDLEN 0x1 + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX5GCR1_RESERVED_15 0x0 - Configurable ODT(TE) Phase Shift - PSU_DDR_PHY_DX4GCR0_CODTSHFT 0x0 + * Select the delayed or non-delayed read data strobe # + * PSU_DDR_PHY_DX5GCR1_QSNSEL 0x1 - DQS Duty Cycle Correction - PSU_DDR_PHY_DX4GCR0_DQSDCC 0x0 + * Select the delayed or non-delayed read data strobe + * PSU_DDR_PHY_DX5GCR1_QSSEL 0x1 - Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY - PSU_DDR_PHY_DX4GCR0_RDDLY 0x8 + * Enables Read Data Strobe in a byte lane + * PSU_DDR_PHY_DX5GCR1_OEEN 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX4GCR0_RESERVED_19_14 0x0 + * Enables PDR in a byte lane + * PSU_DDR_PHY_DX5GCR1_PDREN 0x1 - DQSNSE Power Down Receiver - PSU_DDR_PHY_DX4GCR0_DQSNSEPDR 0x0 + * Enables ODT/TE in a byte lane + * PSU_DDR_PHY_DX5GCR1_TEEN 0x1 - DQSSE Power Down Receiver - PSU_DDR_PHY_DX4GCR0_DQSSEPDR 0x0 + * Enables Write Data strobe in a byte lane + * PSU_DDR_PHY_DX5GCR1_DSEN 0x1 - RTT On Additive Latency - PSU_DDR_PHY_DX4GCR0_RTTOAL 0x0 + * Enables DM pin in a byte lane + * PSU_DDR_PHY_DX5GCR1_DMEN 0x1 - RTT Output Hold - PSU_DDR_PHY_DX4GCR0_RTTOH 0x3 + * Enables DQ corresponding to each bit in a byte + * PSU_DDR_PHY_DX5GCR1_DQEN 0xff - Configurable PDR Phase Shift - PSU_DDR_PHY_DX4GCR0_CPDRSHFT 0x0 + * DATX8 n General Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD080C04, 0xFFFFFFFFU ,0x00007FFFU) + */ + PSU_Mask_Write(DDR_PHY_DX5GCR1_OFFSET, 0xFFFFFFFFU, 0x00007FFFU); +/*##################################################################### */ - DQSR Power Down - PSU_DDR_PHY_DX4GCR0_DQSRPD 0x0 + /* + * Register : DX5GCR4 @ 0XFD080C10 - DQSG Power Down Receiver - PSU_DDR_PHY_DX4GCR0_DQSGPDR 0x0 + * Byte lane VREF IOM (Used only by D4MU IOs) + * PSU_DDR_PHY_DX5GCR4_RESERVED_31_29 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX4GCR0_RESERVED_4 0x0 + * Byte Lane VREF Pad Enable + * PSU_DDR_PHY_DX5GCR4_DXREFPEN 0x0 - DQSG On-Die Termination - PSU_DDR_PHY_DX4GCR0_DQSGODT 0x0 + * Byte Lane Internal VREF Enable + * PSU_DDR_PHY_DX5GCR4_DXREFEEN 0x3 - DQSG Output Enable - PSU_DDR_PHY_DX4GCR0_DQSGOE 0x1 + * Byte Lane Single-End VREF Enable + * PSU_DDR_PHY_DX5GCR4_DXREFSEN 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX4GCR0_RESERVED_1_0 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX5GCR4_RESERVED_24 0x0 - DATX8 n General Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD080B00, 0xFFFFFFFFU ,0x40800604U) - RegMask = (DDR_PHY_DX4GCR0_CALBYP_MASK | DDR_PHY_DX4GCR0_MDLEN_MASK | DDR_PHY_DX4GCR0_CODTSHFT_MASK | DDR_PHY_DX4GCR0_DQSDCC_MASK | DDR_PHY_DX4GCR0_RDDLY_MASK | DDR_PHY_DX4GCR0_RESERVED_19_14_MASK | DDR_PHY_DX4GCR0_DQSNSEPDR_MASK | DDR_PHY_DX4GCR0_DQSSEPDR_MASK | DDR_PHY_DX4GCR0_RTTOAL_MASK | DDR_PHY_DX4GCR0_RTTOH_MASK | DDR_PHY_DX4GCR0_CPDRSHFT_MASK | DDR_PHY_DX4GCR0_DQSRPD_MASK | DDR_PHY_DX4GCR0_DQSGPDR_MASK | DDR_PHY_DX4GCR0_RESERVED_4_MASK | DDR_PHY_DX4GCR0_DQSGODT_MASK | DDR_PHY_DX4GCR0_DQSGOE_MASK | DDR_PHY_DX4GCR0_RESERVED_1_0_MASK | 0 ); + * External VREF generator REFSEL range select + * PSU_DDR_PHY_DX5GCR4_DXREFESELRANGE 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX4GCR0_CALBYP_SHIFT - | 0x00000001U << DDR_PHY_DX4GCR0_MDLEN_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR0_CODTSHFT_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR0_DQSDCC_SHIFT - | 0x00000008U << DDR_PHY_DX4GCR0_RDDLY_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR0_RESERVED_19_14_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR0_DQSNSEPDR_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR0_DQSSEPDR_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR0_RTTOAL_SHIFT - | 0x00000003U << DDR_PHY_DX4GCR0_RTTOH_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR0_CPDRSHFT_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR0_DQSRPD_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR0_DQSGPDR_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR0_RESERVED_4_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR0_DQSGODT_SHIFT - | 0x00000001U << DDR_PHY_DX4GCR0_DQSGOE_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR0_RESERVED_1_0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX4GCR0_OFFSET ,0xFFFFFFFFU ,0x40800604U); - /*############################################################################################################################ */ + * Byte Lane External VREF Select + * PSU_DDR_PHY_DX5GCR4_DXREFESEL 0x0 - /*Register : DX4GCR1 @ 0XFD080B04

+ * Single ended VREF generator REFSEL range select + * PSU_DDR_PHY_DX5GCR4_DXREFSSELRANGE 0x1 - Enables the PDR mode for DQ[7:0] - PSU_DDR_PHY_DX4GCR1_DXPDRMODE 0x0 + * Byte Lane Single-End VREF Select + * PSU_DDR_PHY_DX5GCR4_DXREFSSEL 0x30 - Reserved. Returns zeroes on reads. - PSU_DDR_PHY_DX4GCR1_RESERVED_15 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX5GCR4_RESERVED_7_6 0x0 - Select the delayed or non-delayed read data strobe # - PSU_DDR_PHY_DX4GCR1_QSNSEL 0x1 + * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX5GCR4_DXREFIEN 0xf - Select the delayed or non-delayed read data strobe - PSU_DDR_PHY_DX4GCR1_QSSEL 0x1 + * VRMON control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX5GCR4_DXREFIMON 0x0 - Enables Read Data Strobe in a byte lane - PSU_DDR_PHY_DX4GCR1_OEEN 0x1 + * DATX8 n General Configuration Register 4 + * (OFFSET, MASK, VALUE) (0XFD080C10, 0xFFFFFFFFU ,0x0E00B03CU) + */ + PSU_Mask_Write(DDR_PHY_DX5GCR4_OFFSET, 0xFFFFFFFFU, 0x0E00B03CU); +/*##################################################################### */ - Enables PDR in a byte lane - PSU_DDR_PHY_DX4GCR1_PDREN 0x1 + /* + * Register : DX5GCR5 @ 0XFD080C14 - Enables ODT/TE in a byte lane - PSU_DDR_PHY_DX4GCR1_TEEN 0x1 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX5GCR5_RESERVED_31 0x0 - Enables Write Data strobe in a byte lane - PSU_DDR_PHY_DX4GCR1_DSEN 0x1 + * Byte Lane internal VREF Select for Rank 3 + * PSU_DDR_PHY_DX5GCR5_DXREFISELR3 0x9 - Enables DM pin in a byte lane - PSU_DDR_PHY_DX4GCR1_DMEN 0x1 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX5GCR5_RESERVED_23 0x0 - Enables DQ corresponding to each bit in a byte - PSU_DDR_PHY_DX4GCR1_DQEN 0xff + * Byte Lane internal VREF Select for Rank 2 + * PSU_DDR_PHY_DX5GCR5_DXREFISELR2 0x9 - DATX8 n General Configuration Register 1 - (OFFSET, MASK, VALUE) (0XFD080B04, 0xFFFFFFFFU ,0x00007FFFU) - RegMask = (DDR_PHY_DX4GCR1_DXPDRMODE_MASK | DDR_PHY_DX4GCR1_RESERVED_15_MASK | DDR_PHY_DX4GCR1_QSNSEL_MASK | DDR_PHY_DX4GCR1_QSSEL_MASK | DDR_PHY_DX4GCR1_OEEN_MASK | DDR_PHY_DX4GCR1_PDREN_MASK | DDR_PHY_DX4GCR1_TEEN_MASK | DDR_PHY_DX4GCR1_DSEN_MASK | DDR_PHY_DX4GCR1_DMEN_MASK | DDR_PHY_DX4GCR1_DQEN_MASK | 0 ); + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX5GCR5_RESERVED_15 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX4GCR1_DXPDRMODE_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR1_RESERVED_15_SHIFT - | 0x00000001U << DDR_PHY_DX4GCR1_QSNSEL_SHIFT - | 0x00000001U << DDR_PHY_DX4GCR1_QSSEL_SHIFT - | 0x00000001U << DDR_PHY_DX4GCR1_OEEN_SHIFT - | 0x00000001U << DDR_PHY_DX4GCR1_PDREN_SHIFT - | 0x00000001U << DDR_PHY_DX4GCR1_TEEN_SHIFT - | 0x00000001U << DDR_PHY_DX4GCR1_DSEN_SHIFT - | 0x00000001U << DDR_PHY_DX4GCR1_DMEN_SHIFT - | 0x000000FFU << DDR_PHY_DX4GCR1_DQEN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX4GCR1_OFFSET ,0xFFFFFFFFU ,0x00007FFFU); - /*############################################################################################################################ */ + * Byte Lane internal VREF Select for Rank 1 + * PSU_DDR_PHY_DX5GCR5_DXREFISELR1 0x55 - /*Register : DX4GCR4 @ 0XFD080B10

+ * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX5GCR5_RESERVED_7 0x0 - Byte lane VREF IOM (Used only by D4MU IOs) - PSU_DDR_PHY_DX4GCR4_RESERVED_31_29 0x0 + * Byte Lane internal VREF Select for Rank 0 + * PSU_DDR_PHY_DX5GCR5_DXREFISELR0 0x55 - Byte Lane VREF Pad Enable - PSU_DDR_PHY_DX4GCR4_DXREFPEN 0x0 + * DATX8 n General Configuration Register 5 + * (OFFSET, MASK, VALUE) (0XFD080C14, 0xFFFFFFFFU ,0x09095555U) + */ + PSU_Mask_Write(DDR_PHY_DX5GCR5_OFFSET, 0xFFFFFFFFU, 0x09095555U); +/*##################################################################### */ - Byte Lane Internal VREF Enable - PSU_DDR_PHY_DX4GCR4_DXREFEEN 0x3 + /* + * Register : DX5GCR6 @ 0XFD080C18 - Byte Lane Single-End VREF Enable - PSU_DDR_PHY_DX4GCR4_DXREFSEN 0x1 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX5GCR6_RESERVED_31_30 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX4GCR4_RESERVED_24 0x0 + * DRAM DQ VREF Select for Rank3 + * PSU_DDR_PHY_DX5GCR6_DXDQVREFR3 0x9 - External VREF generator REFSEL range select - PSU_DDR_PHY_DX4GCR4_DXREFESELRANGE 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX5GCR6_RESERVED_23_22 0x0 - Byte Lane External VREF Select - PSU_DDR_PHY_DX4GCR4_DXREFESEL 0x0 + * DRAM DQ VREF Select for Rank2 + * PSU_DDR_PHY_DX5GCR6_DXDQVREFR2 0x9 - Single ended VREF generator REFSEL range select - PSU_DDR_PHY_DX4GCR4_DXREFSSELRANGE 0x1 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX5GCR6_RESERVED_15_14 0x0 - Byte Lane Single-End VREF Select - PSU_DDR_PHY_DX4GCR4_DXREFSSEL 0x30 + * DRAM DQ VREF Select for Rank1 + * PSU_DDR_PHY_DX5GCR6_DXDQVREFR1 0x2b - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX4GCR4_RESERVED_7_6 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX5GCR6_RESERVED_7_6 0x0 - VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. - PSU_DDR_PHY_DX4GCR4_DXREFIEN 0xf + * DRAM DQ VREF Select for Rank0 + * PSU_DDR_PHY_DX5GCR6_DXDQVREFR0 0x2b - VRMON control for DQ IO (Single Ended) buffers of a byte lane. - PSU_DDR_PHY_DX4GCR4_DXREFIMON 0x0 + * DATX8 n General Configuration Register 6 + * (OFFSET, MASK, VALUE) (0XFD080C18, 0xFFFFFFFFU ,0x09092B2BU) + */ + PSU_Mask_Write(DDR_PHY_DX5GCR6_OFFSET, 0xFFFFFFFFU, 0x09092B2BU); +/*##################################################################### */ - DATX8 n General Configuration Register 4 - (OFFSET, MASK, VALUE) (0XFD080B10, 0xFFFFFFFFU ,0x0E00B03CU) - RegMask = (DDR_PHY_DX4GCR4_RESERVED_31_29_MASK | DDR_PHY_DX4GCR4_DXREFPEN_MASK | DDR_PHY_DX4GCR4_DXREFEEN_MASK | DDR_PHY_DX4GCR4_DXREFSEN_MASK | DDR_PHY_DX4GCR4_RESERVED_24_MASK | DDR_PHY_DX4GCR4_DXREFESELRANGE_MASK | DDR_PHY_DX4GCR4_DXREFESEL_MASK | DDR_PHY_DX4GCR4_DXREFSSELRANGE_MASK | DDR_PHY_DX4GCR4_DXREFSSEL_MASK | DDR_PHY_DX4GCR4_RESERVED_7_6_MASK | DDR_PHY_DX4GCR4_DXREFIEN_MASK | DDR_PHY_DX4GCR4_DXREFIMON_MASK | 0 ); + /* + * Register : DX6GCR0 @ 0XFD080D00 - RegVal = ((0x00000000U << DDR_PHY_DX4GCR4_RESERVED_31_29_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR4_DXREFPEN_SHIFT - | 0x00000003U << DDR_PHY_DX4GCR4_DXREFEEN_SHIFT - | 0x00000001U << DDR_PHY_DX4GCR4_DXREFSEN_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR4_RESERVED_24_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR4_DXREFESELRANGE_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR4_DXREFESEL_SHIFT - | 0x00000001U << DDR_PHY_DX4GCR4_DXREFSSELRANGE_SHIFT - | 0x00000030U << DDR_PHY_DX4GCR4_DXREFSSEL_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR4_RESERVED_7_6_SHIFT - | 0x0000000FU << DDR_PHY_DX4GCR4_DXREFIEN_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR4_DXREFIMON_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX4GCR4_OFFSET ,0xFFFFFFFFU ,0x0E00B03CU); - /*############################################################################################################################ */ + * Calibration Bypass + * PSU_DDR_PHY_DX6GCR0_CALBYP 0x0 - /*Register : DX4GCR5 @ 0XFD080B14

+ * Master Delay Line Enable + * PSU_DDR_PHY_DX6GCR0_MDLEN 0x1 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX4GCR5_RESERVED_31 0x0 + * Configurable ODT(TE) Phase Shift + * PSU_DDR_PHY_DX6GCR0_CODTSHFT 0x0 - Byte Lane internal VREF Select for Rank 3 - PSU_DDR_PHY_DX4GCR5_DXREFISELR3 0x9 + * DQS Duty Cycle Correction + * PSU_DDR_PHY_DX6GCR0_DQSDCC 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX4GCR5_RESERVED_23 0x0 + * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY + * PSU_DDR_PHY_DX6GCR0_RDDLY 0x8 - Byte Lane internal VREF Select for Rank 2 - PSU_DDR_PHY_DX4GCR5_DXREFISELR2 0x9 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX6GCR0_RESERVED_19_14 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX4GCR5_RESERVED_15 0x0 + * DQSNSE Power Down Receiver + * PSU_DDR_PHY_DX6GCR0_DQSNSEPDR 0x0 - Byte Lane internal VREF Select for Rank 1 - PSU_DDR_PHY_DX4GCR5_DXREFISELR1 0x4f + * DQSSE Power Down Receiver + * PSU_DDR_PHY_DX6GCR0_DQSSEPDR 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX4GCR5_RESERVED_7 0x0 + * RTT On Additive Latency + * PSU_DDR_PHY_DX6GCR0_RTTOAL 0x0 - Byte Lane internal VREF Select for Rank 0 - PSU_DDR_PHY_DX4GCR5_DXREFISELR0 0x4f + * RTT Output Hold + * PSU_DDR_PHY_DX6GCR0_RTTOH 0x3 - DATX8 n General Configuration Register 5 - (OFFSET, MASK, VALUE) (0XFD080B14, 0xFFFFFFFFU ,0x09094F4FU) - RegMask = (DDR_PHY_DX4GCR5_RESERVED_31_MASK | DDR_PHY_DX4GCR5_DXREFISELR3_MASK | DDR_PHY_DX4GCR5_RESERVED_23_MASK | DDR_PHY_DX4GCR5_DXREFISELR2_MASK | DDR_PHY_DX4GCR5_RESERVED_15_MASK | DDR_PHY_DX4GCR5_DXREFISELR1_MASK | DDR_PHY_DX4GCR5_RESERVED_7_MASK | DDR_PHY_DX4GCR5_DXREFISELR0_MASK | 0 ); + * Configurable PDR Phase Shift + * PSU_DDR_PHY_DX6GCR0_CPDRSHFT 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX4GCR5_RESERVED_31_SHIFT - | 0x00000009U << DDR_PHY_DX4GCR5_DXREFISELR3_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR5_RESERVED_23_SHIFT - | 0x00000009U << DDR_PHY_DX4GCR5_DXREFISELR2_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR5_RESERVED_15_SHIFT - | 0x0000004FU << DDR_PHY_DX4GCR5_DXREFISELR1_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR5_RESERVED_7_SHIFT - | 0x0000004FU << DDR_PHY_DX4GCR5_DXREFISELR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX4GCR5_OFFSET ,0xFFFFFFFFU ,0x09094F4FU); - /*############################################################################################################################ */ + * DQSR Power Down + * PSU_DDR_PHY_DX6GCR0_DQSRPD 0x0 - /*Register : DX4GCR6 @ 0XFD080B18

+ * DQSG Power Down Receiver + * PSU_DDR_PHY_DX6GCR0_DQSGPDR 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX4GCR6_RESERVED_31_30 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX6GCR0_RESERVED_4 0x0 - DRAM DQ VREF Select for Rank3 - PSU_DDR_PHY_DX4GCR6_DXDQVREFR3 0x9 + * DQSG On-Die Termination + * PSU_DDR_PHY_DX6GCR0_DQSGODT 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX4GCR6_RESERVED_23_22 0x0 + * DQSG Output Enable + * PSU_DDR_PHY_DX6GCR0_DQSGOE 0x1 - DRAM DQ VREF Select for Rank2 - PSU_DDR_PHY_DX4GCR6_DXDQVREFR2 0x9 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX6GCR0_RESERVED_1_0 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX4GCR6_RESERVED_15_14 0x0 + * DATX8 n General Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD080D00, 0xFFFFFFFFU ,0x40800604U) + */ + PSU_Mask_Write(DDR_PHY_DX6GCR0_OFFSET, 0xFFFFFFFFU, 0x40800604U); +/*##################################################################### */ - DRAM DQ VREF Select for Rank1 - PSU_DDR_PHY_DX4GCR6_DXDQVREFR1 0x2b + /* + * Register : DX6GCR1 @ 0XFD080D04 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX4GCR6_RESERVED_7_6 0x0 + * Enables the PDR mode for DQ[7:0] + * PSU_DDR_PHY_DX6GCR1_DXPDRMODE 0x0 - DRAM DQ VREF Select for Rank0 - PSU_DDR_PHY_DX4GCR6_DXDQVREFR0 0x2b + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX6GCR1_RESERVED_15 0x0 - DATX8 n General Configuration Register 6 - (OFFSET, MASK, VALUE) (0XFD080B18, 0xFFFFFFFFU ,0x09092B2BU) - RegMask = (DDR_PHY_DX4GCR6_RESERVED_31_30_MASK | DDR_PHY_DX4GCR6_DXDQVREFR3_MASK | DDR_PHY_DX4GCR6_RESERVED_23_22_MASK | DDR_PHY_DX4GCR6_DXDQVREFR2_MASK | DDR_PHY_DX4GCR6_RESERVED_15_14_MASK | DDR_PHY_DX4GCR6_DXDQVREFR1_MASK | DDR_PHY_DX4GCR6_RESERVED_7_6_MASK | DDR_PHY_DX4GCR6_DXDQVREFR0_MASK | 0 ); + * Select the delayed or non-delayed read data strobe # + * PSU_DDR_PHY_DX6GCR1_QSNSEL 0x1 - RegVal = ((0x00000000U << DDR_PHY_DX4GCR6_RESERVED_31_30_SHIFT - | 0x00000009U << DDR_PHY_DX4GCR6_DXDQVREFR3_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR6_RESERVED_23_22_SHIFT - | 0x00000009U << DDR_PHY_DX4GCR6_DXDQVREFR2_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR6_RESERVED_15_14_SHIFT - | 0x0000002BU << DDR_PHY_DX4GCR6_DXDQVREFR1_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR6_RESERVED_7_6_SHIFT - | 0x0000002BU << DDR_PHY_DX4GCR6_DXDQVREFR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX4GCR6_OFFSET ,0xFFFFFFFFU ,0x09092B2BU); - /*############################################################################################################################ */ + * Select the delayed or non-delayed read data strobe + * PSU_DDR_PHY_DX6GCR1_QSSEL 0x1 - /*Register : DX4LCDLR2 @ 0XFD080B88

+ * Enables Read Data Strobe in a byte lane + * PSU_DDR_PHY_DX6GCR1_OEEN 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX4LCDLR2_RESERVED_31_25 0x0 + * Enables PDR in a byte lane + * PSU_DDR_PHY_DX6GCR1_PDREN 0x1 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX4LCDLR2_RESERVED_24_16 0x0 + * Enables ODT/TE in a byte lane + * PSU_DDR_PHY_DX6GCR1_TEEN 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX4LCDLR2_RESERVED_15_9 0x0 + * Enables Write Data strobe in a byte lane + * PSU_DDR_PHY_DX6GCR1_DSEN 0x1 - Read DQS Gating Delay - PSU_DDR_PHY_DX4LCDLR2_DQSGD 0x0 + * Enables DM pin in a byte lane + * PSU_DDR_PHY_DX6GCR1_DMEN 0x1 - DATX8 n Local Calibrated Delay Line Register 2 - (OFFSET, MASK, VALUE) (0XFD080B88, 0xFFFFFFFFU ,0x00000000U) - RegMask = (DDR_PHY_DX4LCDLR2_RESERVED_31_25_MASK | DDR_PHY_DX4LCDLR2_RESERVED_24_16_MASK | DDR_PHY_DX4LCDLR2_RESERVED_15_9_MASK | DDR_PHY_DX4LCDLR2_DQSGD_MASK | 0 ); + * Enables DQ corresponding to each bit in a byte + * PSU_DDR_PHY_DX6GCR1_DQEN 0xff - RegVal = ((0x00000000U << DDR_PHY_DX4LCDLR2_RESERVED_31_25_SHIFT - | 0x00000000U << DDR_PHY_DX4LCDLR2_RESERVED_24_16_SHIFT - | 0x00000000U << DDR_PHY_DX4LCDLR2_RESERVED_15_9_SHIFT - | 0x00000000U << DDR_PHY_DX4LCDLR2_DQSGD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX4LCDLR2_OFFSET ,0xFFFFFFFFU ,0x00000000U); - /*############################################################################################################################ */ + * DATX8 n General Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD080D04, 0xFFFFFFFFU ,0x00007FFFU) + */ + PSU_Mask_Write(DDR_PHY_DX6GCR1_OFFSET, 0xFFFFFFFFU, 0x00007FFFU); +/*##################################################################### */ - /*Register : DX4GTR0 @ 0XFD080BC0

+ /* + * Register : DX6GCR4 @ 0XFD080D10 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX4GTR0_RESERVED_31_24 0x0 + * Byte lane VREF IOM (Used only by D4MU IOs) + * PSU_DDR_PHY_DX6GCR4_RESERVED_31_29 0x0 - DQ Write Path Latency Pipeline - PSU_DDR_PHY_DX4GTR0_WDQSL 0x0 + * Byte Lane VREF Pad Enable + * PSU_DDR_PHY_DX6GCR4_DXREFPEN 0x0 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX4GTR0_RESERVED_23_20 0x0 + * Byte Lane Internal VREF Enable + * PSU_DDR_PHY_DX6GCR4_DXREFEEN 0x3 - Write Leveling System Latency - PSU_DDR_PHY_DX4GTR0_WLSL 0x2 + * Byte Lane Single-End VREF Enable + * PSU_DDR_PHY_DX6GCR4_DXREFSEN 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX4GTR0_RESERVED_15_13 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX6GCR4_RESERVED_24 0x0 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX4GTR0_RESERVED_12_8 0x0 + * External VREF generator REFSEL range select + * PSU_DDR_PHY_DX6GCR4_DXREFESELRANGE 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX4GTR0_RESERVED_7_5 0x0 + * Byte Lane External VREF Select + * PSU_DDR_PHY_DX6GCR4_DXREFESEL 0x0 - DQS Gating System Latency - PSU_DDR_PHY_DX4GTR0_DGSL 0x0 + * Single ended VREF generator REFSEL range select + * PSU_DDR_PHY_DX6GCR4_DXREFSSELRANGE 0x1 - DATX8 n General Timing Register 0 - (OFFSET, MASK, VALUE) (0XFD080BC0, 0xFFFFFFFFU ,0x00020000U) - RegMask = (DDR_PHY_DX4GTR0_RESERVED_31_24_MASK | DDR_PHY_DX4GTR0_WDQSL_MASK | DDR_PHY_DX4GTR0_RESERVED_23_20_MASK | DDR_PHY_DX4GTR0_WLSL_MASK | DDR_PHY_DX4GTR0_RESERVED_15_13_MASK | DDR_PHY_DX4GTR0_RESERVED_12_8_MASK | DDR_PHY_DX4GTR0_RESERVED_7_5_MASK | DDR_PHY_DX4GTR0_DGSL_MASK | 0 ); + * Byte Lane Single-End VREF Select + * PSU_DDR_PHY_DX6GCR4_DXREFSSEL 0x30 - RegVal = ((0x00000000U << DDR_PHY_DX4GTR0_RESERVED_31_24_SHIFT - | 0x00000000U << DDR_PHY_DX4GTR0_WDQSL_SHIFT - | 0x00000000U << DDR_PHY_DX4GTR0_RESERVED_23_20_SHIFT - | 0x00000002U << DDR_PHY_DX4GTR0_WLSL_SHIFT - | 0x00000000U << DDR_PHY_DX4GTR0_RESERVED_15_13_SHIFT - | 0x00000000U << DDR_PHY_DX4GTR0_RESERVED_12_8_SHIFT - | 0x00000000U << DDR_PHY_DX4GTR0_RESERVED_7_5_SHIFT - | 0x00000000U << DDR_PHY_DX4GTR0_DGSL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX4GTR0_OFFSET ,0xFFFFFFFFU ,0x00020000U); - /*############################################################################################################################ */ + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX6GCR4_RESERVED_7_6 0x0 - /*Register : DX5GCR0 @ 0XFD080C00

+ * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX6GCR4_DXREFIEN 0xf - Calibration Bypass - PSU_DDR_PHY_DX5GCR0_CALBYP 0x0 + * VRMON control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX6GCR4_DXREFIMON 0x0 - Master Delay Line Enable - PSU_DDR_PHY_DX5GCR0_MDLEN 0x1 + * DATX8 n General Configuration Register 4 + * (OFFSET, MASK, VALUE) (0XFD080D10, 0xFFFFFFFFU ,0x0E00B03CU) + */ + PSU_Mask_Write(DDR_PHY_DX6GCR4_OFFSET, 0xFFFFFFFFU, 0x0E00B03CU); +/*##################################################################### */ - Configurable ODT(TE) Phase Shift - PSU_DDR_PHY_DX5GCR0_CODTSHFT 0x0 + /* + * Register : DX6GCR5 @ 0XFD080D14 - DQS Duty Cycle Correction - PSU_DDR_PHY_DX5GCR0_DQSDCC 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX6GCR5_RESERVED_31 0x0 - Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY - PSU_DDR_PHY_DX5GCR0_RDDLY 0x8 + * Byte Lane internal VREF Select for Rank 3 + * PSU_DDR_PHY_DX6GCR5_DXREFISELR3 0x9 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX5GCR0_RESERVED_19_14 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX6GCR5_RESERVED_23 0x0 - DQSNSE Power Down Receiver - PSU_DDR_PHY_DX5GCR0_DQSNSEPDR 0x0 + * Byte Lane internal VREF Select for Rank 2 + * PSU_DDR_PHY_DX6GCR5_DXREFISELR2 0x9 - DQSSE Power Down Receiver - PSU_DDR_PHY_DX5GCR0_DQSSEPDR 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX6GCR5_RESERVED_15 0x0 - RTT On Additive Latency - PSU_DDR_PHY_DX5GCR0_RTTOAL 0x0 + * Byte Lane internal VREF Select for Rank 1 + * PSU_DDR_PHY_DX6GCR5_DXREFISELR1 0x55 - RTT Output Hold - PSU_DDR_PHY_DX5GCR0_RTTOH 0x3 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX6GCR5_RESERVED_7 0x0 - Configurable PDR Phase Shift - PSU_DDR_PHY_DX5GCR0_CPDRSHFT 0x0 + * Byte Lane internal VREF Select for Rank 0 + * PSU_DDR_PHY_DX6GCR5_DXREFISELR0 0x55 - DQSR Power Down - PSU_DDR_PHY_DX5GCR0_DQSRPD 0x0 + * DATX8 n General Configuration Register 5 + * (OFFSET, MASK, VALUE) (0XFD080D14, 0xFFFFFFFFU ,0x09095555U) + */ + PSU_Mask_Write(DDR_PHY_DX6GCR5_OFFSET, 0xFFFFFFFFU, 0x09095555U); +/*##################################################################### */ - DQSG Power Down Receiver - PSU_DDR_PHY_DX5GCR0_DQSGPDR 0x0 + /* + * Register : DX6GCR6 @ 0XFD080D18 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX5GCR0_RESERVED_4 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX6GCR6_RESERVED_31_30 0x0 - DQSG On-Die Termination - PSU_DDR_PHY_DX5GCR0_DQSGODT 0x0 + * DRAM DQ VREF Select for Rank3 + * PSU_DDR_PHY_DX6GCR6_DXDQVREFR3 0x9 - DQSG Output Enable - PSU_DDR_PHY_DX5GCR0_DQSGOE 0x1 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX6GCR6_RESERVED_23_22 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX5GCR0_RESERVED_1_0 0x0 + * DRAM DQ VREF Select for Rank2 + * PSU_DDR_PHY_DX6GCR6_DXDQVREFR2 0x9 - DATX8 n General Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD080C00, 0xFFFFFFFFU ,0x40800604U) - RegMask = (DDR_PHY_DX5GCR0_CALBYP_MASK | DDR_PHY_DX5GCR0_MDLEN_MASK | DDR_PHY_DX5GCR0_CODTSHFT_MASK | DDR_PHY_DX5GCR0_DQSDCC_MASK | DDR_PHY_DX5GCR0_RDDLY_MASK | DDR_PHY_DX5GCR0_RESERVED_19_14_MASK | DDR_PHY_DX5GCR0_DQSNSEPDR_MASK | DDR_PHY_DX5GCR0_DQSSEPDR_MASK | DDR_PHY_DX5GCR0_RTTOAL_MASK | DDR_PHY_DX5GCR0_RTTOH_MASK | DDR_PHY_DX5GCR0_CPDRSHFT_MASK | DDR_PHY_DX5GCR0_DQSRPD_MASK | DDR_PHY_DX5GCR0_DQSGPDR_MASK | DDR_PHY_DX5GCR0_RESERVED_4_MASK | DDR_PHY_DX5GCR0_DQSGODT_MASK | DDR_PHY_DX5GCR0_DQSGOE_MASK | DDR_PHY_DX5GCR0_RESERVED_1_0_MASK | 0 ); + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX6GCR6_RESERVED_15_14 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX5GCR0_CALBYP_SHIFT - | 0x00000001U << DDR_PHY_DX5GCR0_MDLEN_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR0_CODTSHFT_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR0_DQSDCC_SHIFT - | 0x00000008U << DDR_PHY_DX5GCR0_RDDLY_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR0_RESERVED_19_14_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR0_DQSNSEPDR_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR0_DQSSEPDR_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR0_RTTOAL_SHIFT - | 0x00000003U << DDR_PHY_DX5GCR0_RTTOH_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR0_CPDRSHFT_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR0_DQSRPD_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR0_DQSGPDR_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR0_RESERVED_4_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR0_DQSGODT_SHIFT - | 0x00000001U << DDR_PHY_DX5GCR0_DQSGOE_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR0_RESERVED_1_0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX5GCR0_OFFSET ,0xFFFFFFFFU ,0x40800604U); - /*############################################################################################################################ */ + * DRAM DQ VREF Select for Rank1 + * PSU_DDR_PHY_DX6GCR6_DXDQVREFR1 0x2b - /*Register : DX5GCR1 @ 0XFD080C04

+ * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX6GCR6_RESERVED_7_6 0x0 - Enables the PDR mode for DQ[7:0] - PSU_DDR_PHY_DX5GCR1_DXPDRMODE 0x0 + * DRAM DQ VREF Select for Rank0 + * PSU_DDR_PHY_DX6GCR6_DXDQVREFR0 0x2b - Reserved. Returns zeroes on reads. - PSU_DDR_PHY_DX5GCR1_RESERVED_15 0x0 + * DATX8 n General Configuration Register 6 + * (OFFSET, MASK, VALUE) (0XFD080D18, 0xFFFFFFFFU ,0x09092B2BU) + */ + PSU_Mask_Write(DDR_PHY_DX6GCR6_OFFSET, 0xFFFFFFFFU, 0x09092B2BU); +/*##################################################################### */ - Select the delayed or non-delayed read data strobe # - PSU_DDR_PHY_DX5GCR1_QSNSEL 0x1 + /* + * Register : DX7GCR0 @ 0XFD080E00 - Select the delayed or non-delayed read data strobe - PSU_DDR_PHY_DX5GCR1_QSSEL 0x1 + * Calibration Bypass + * PSU_DDR_PHY_DX7GCR0_CALBYP 0x0 - Enables Read Data Strobe in a byte lane - PSU_DDR_PHY_DX5GCR1_OEEN 0x1 + * Master Delay Line Enable + * PSU_DDR_PHY_DX7GCR0_MDLEN 0x1 - Enables PDR in a byte lane - PSU_DDR_PHY_DX5GCR1_PDREN 0x1 + * Configurable ODT(TE) Phase Shift + * PSU_DDR_PHY_DX7GCR0_CODTSHFT 0x0 - Enables ODT/TE in a byte lane - PSU_DDR_PHY_DX5GCR1_TEEN 0x1 + * DQS Duty Cycle Correction + * PSU_DDR_PHY_DX7GCR0_DQSDCC 0x0 - Enables Write Data strobe in a byte lane - PSU_DDR_PHY_DX5GCR1_DSEN 0x1 + * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY + * PSU_DDR_PHY_DX7GCR0_RDDLY 0x8 - Enables DM pin in a byte lane - PSU_DDR_PHY_DX5GCR1_DMEN 0x1 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX7GCR0_RESERVED_19_14 0x0 - Enables DQ corresponding to each bit in a byte - PSU_DDR_PHY_DX5GCR1_DQEN 0xff + * DQSNSE Power Down Receiver + * PSU_DDR_PHY_DX7GCR0_DQSNSEPDR 0x0 - DATX8 n General Configuration Register 1 - (OFFSET, MASK, VALUE) (0XFD080C04, 0xFFFFFFFFU ,0x00007FFFU) - RegMask = (DDR_PHY_DX5GCR1_DXPDRMODE_MASK | DDR_PHY_DX5GCR1_RESERVED_15_MASK | DDR_PHY_DX5GCR1_QSNSEL_MASK | DDR_PHY_DX5GCR1_QSSEL_MASK | DDR_PHY_DX5GCR1_OEEN_MASK | DDR_PHY_DX5GCR1_PDREN_MASK | DDR_PHY_DX5GCR1_TEEN_MASK | DDR_PHY_DX5GCR1_DSEN_MASK | DDR_PHY_DX5GCR1_DMEN_MASK | DDR_PHY_DX5GCR1_DQEN_MASK | 0 ); + * DQSSE Power Down Receiver + * PSU_DDR_PHY_DX7GCR0_DQSSEPDR 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX5GCR1_DXPDRMODE_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR1_RESERVED_15_SHIFT - | 0x00000001U << DDR_PHY_DX5GCR1_QSNSEL_SHIFT - | 0x00000001U << DDR_PHY_DX5GCR1_QSSEL_SHIFT - | 0x00000001U << DDR_PHY_DX5GCR1_OEEN_SHIFT - | 0x00000001U << DDR_PHY_DX5GCR1_PDREN_SHIFT - | 0x00000001U << DDR_PHY_DX5GCR1_TEEN_SHIFT - | 0x00000001U << DDR_PHY_DX5GCR1_DSEN_SHIFT - | 0x00000001U << DDR_PHY_DX5GCR1_DMEN_SHIFT - | 0x000000FFU << DDR_PHY_DX5GCR1_DQEN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX5GCR1_OFFSET ,0xFFFFFFFFU ,0x00007FFFU); - /*############################################################################################################################ */ + * RTT On Additive Latency + * PSU_DDR_PHY_DX7GCR0_RTTOAL 0x0 - /*Register : DX5GCR4 @ 0XFD080C10

+ * RTT Output Hold + * PSU_DDR_PHY_DX7GCR0_RTTOH 0x3 - Byte lane VREF IOM (Used only by D4MU IOs) - PSU_DDR_PHY_DX5GCR4_RESERVED_31_29 0x0 + * Configurable PDR Phase Shift + * PSU_DDR_PHY_DX7GCR0_CPDRSHFT 0x0 - Byte Lane VREF Pad Enable - PSU_DDR_PHY_DX5GCR4_DXREFPEN 0x0 + * DQSR Power Down + * PSU_DDR_PHY_DX7GCR0_DQSRPD 0x0 - Byte Lane Internal VREF Enable - PSU_DDR_PHY_DX5GCR4_DXREFEEN 0x3 + * DQSG Power Down Receiver + * PSU_DDR_PHY_DX7GCR0_DQSGPDR 0x0 - Byte Lane Single-End VREF Enable - PSU_DDR_PHY_DX5GCR4_DXREFSEN 0x1 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX7GCR0_RESERVED_4 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX5GCR4_RESERVED_24 0x0 + * DQSG On-Die Termination + * PSU_DDR_PHY_DX7GCR0_DQSGODT 0x0 - External VREF generator REFSEL range select - PSU_DDR_PHY_DX5GCR4_DXREFESELRANGE 0x0 + * DQSG Output Enable + * PSU_DDR_PHY_DX7GCR0_DQSGOE 0x1 - Byte Lane External VREF Select - PSU_DDR_PHY_DX5GCR4_DXREFESEL 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX7GCR0_RESERVED_1_0 0x0 - Single ended VREF generator REFSEL range select - PSU_DDR_PHY_DX5GCR4_DXREFSSELRANGE 0x1 + * DATX8 n General Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD080E00, 0xFFFFFFFFU ,0x40800604U) + */ + PSU_Mask_Write(DDR_PHY_DX7GCR0_OFFSET, 0xFFFFFFFFU, 0x40800604U); +/*##################################################################### */ - Byte Lane Single-End VREF Select - PSU_DDR_PHY_DX5GCR4_DXREFSSEL 0x30 + /* + * Register : DX7GCR1 @ 0XFD080E04 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX5GCR4_RESERVED_7_6 0x0 + * Enables the PDR mode for DQ[7:0] + * PSU_DDR_PHY_DX7GCR1_DXPDRMODE 0x0 - VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. - PSU_DDR_PHY_DX5GCR4_DXREFIEN 0xf + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX7GCR1_RESERVED_15 0x0 - VRMON control for DQ IO (Single Ended) buffers of a byte lane. - PSU_DDR_PHY_DX5GCR4_DXREFIMON 0x0 + * Select the delayed or non-delayed read data strobe # + * PSU_DDR_PHY_DX7GCR1_QSNSEL 0x1 - DATX8 n General Configuration Register 4 - (OFFSET, MASK, VALUE) (0XFD080C10, 0xFFFFFFFFU ,0x0E00B03CU) - RegMask = (DDR_PHY_DX5GCR4_RESERVED_31_29_MASK | DDR_PHY_DX5GCR4_DXREFPEN_MASK | DDR_PHY_DX5GCR4_DXREFEEN_MASK | DDR_PHY_DX5GCR4_DXREFSEN_MASK | DDR_PHY_DX5GCR4_RESERVED_24_MASK | DDR_PHY_DX5GCR4_DXREFESELRANGE_MASK | DDR_PHY_DX5GCR4_DXREFESEL_MASK | DDR_PHY_DX5GCR4_DXREFSSELRANGE_MASK | DDR_PHY_DX5GCR4_DXREFSSEL_MASK | DDR_PHY_DX5GCR4_RESERVED_7_6_MASK | DDR_PHY_DX5GCR4_DXREFIEN_MASK | DDR_PHY_DX5GCR4_DXREFIMON_MASK | 0 ); + * Select the delayed or non-delayed read data strobe + * PSU_DDR_PHY_DX7GCR1_QSSEL 0x1 - RegVal = ((0x00000000U << DDR_PHY_DX5GCR4_RESERVED_31_29_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR4_DXREFPEN_SHIFT - | 0x00000003U << DDR_PHY_DX5GCR4_DXREFEEN_SHIFT - | 0x00000001U << DDR_PHY_DX5GCR4_DXREFSEN_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR4_RESERVED_24_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR4_DXREFESELRANGE_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR4_DXREFESEL_SHIFT - | 0x00000001U << DDR_PHY_DX5GCR4_DXREFSSELRANGE_SHIFT - | 0x00000030U << DDR_PHY_DX5GCR4_DXREFSSEL_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR4_RESERVED_7_6_SHIFT - | 0x0000000FU << DDR_PHY_DX5GCR4_DXREFIEN_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR4_DXREFIMON_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX5GCR4_OFFSET ,0xFFFFFFFFU ,0x0E00B03CU); - /*############################################################################################################################ */ + * Enables Read Data Strobe in a byte lane + * PSU_DDR_PHY_DX7GCR1_OEEN 0x1 - /*Register : DX5GCR5 @ 0XFD080C14

+ * Enables PDR in a byte lane + * PSU_DDR_PHY_DX7GCR1_PDREN 0x1 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX5GCR5_RESERVED_31 0x0 + * Enables ODT/TE in a byte lane + * PSU_DDR_PHY_DX7GCR1_TEEN 0x1 - Byte Lane internal VREF Select for Rank 3 - PSU_DDR_PHY_DX5GCR5_DXREFISELR3 0x9 + * Enables Write Data strobe in a byte lane + * PSU_DDR_PHY_DX7GCR1_DSEN 0x1 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX5GCR5_RESERVED_23 0x0 + * Enables DM pin in a byte lane + * PSU_DDR_PHY_DX7GCR1_DMEN 0x1 - Byte Lane internal VREF Select for Rank 2 - PSU_DDR_PHY_DX5GCR5_DXREFISELR2 0x9 + * Enables DQ corresponding to each bit in a byte + * PSU_DDR_PHY_DX7GCR1_DQEN 0xff - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX5GCR5_RESERVED_15 0x0 + * DATX8 n General Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD080E04, 0xFFFFFFFFU ,0x00007FFFU) + */ + PSU_Mask_Write(DDR_PHY_DX7GCR1_OFFSET, 0xFFFFFFFFU, 0x00007FFFU); +/*##################################################################### */ - Byte Lane internal VREF Select for Rank 1 - PSU_DDR_PHY_DX5GCR5_DXREFISELR1 0x4f + /* + * Register : DX7GCR4 @ 0XFD080E10 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX5GCR5_RESERVED_7 0x0 + * Byte lane VREF IOM (Used only by D4MU IOs) + * PSU_DDR_PHY_DX7GCR4_RESERVED_31_29 0x0 - Byte Lane internal VREF Select for Rank 0 - PSU_DDR_PHY_DX5GCR5_DXREFISELR0 0x4f + * Byte Lane VREF Pad Enable + * PSU_DDR_PHY_DX7GCR4_DXREFPEN 0x0 - DATX8 n General Configuration Register 5 - (OFFSET, MASK, VALUE) (0XFD080C14, 0xFFFFFFFFU ,0x09094F4FU) - RegMask = (DDR_PHY_DX5GCR5_RESERVED_31_MASK | DDR_PHY_DX5GCR5_DXREFISELR3_MASK | DDR_PHY_DX5GCR5_RESERVED_23_MASK | DDR_PHY_DX5GCR5_DXREFISELR2_MASK | DDR_PHY_DX5GCR5_RESERVED_15_MASK | DDR_PHY_DX5GCR5_DXREFISELR1_MASK | DDR_PHY_DX5GCR5_RESERVED_7_MASK | DDR_PHY_DX5GCR5_DXREFISELR0_MASK | 0 ); + * Byte Lane Internal VREF Enable + * PSU_DDR_PHY_DX7GCR4_DXREFEEN 0x3 - RegVal = ((0x00000000U << DDR_PHY_DX5GCR5_RESERVED_31_SHIFT - | 0x00000009U << DDR_PHY_DX5GCR5_DXREFISELR3_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR5_RESERVED_23_SHIFT - | 0x00000009U << DDR_PHY_DX5GCR5_DXREFISELR2_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR5_RESERVED_15_SHIFT - | 0x0000004FU << DDR_PHY_DX5GCR5_DXREFISELR1_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR5_RESERVED_7_SHIFT - | 0x0000004FU << DDR_PHY_DX5GCR5_DXREFISELR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX5GCR5_OFFSET ,0xFFFFFFFFU ,0x09094F4FU); - /*############################################################################################################################ */ + * Byte Lane Single-End VREF Enable + * PSU_DDR_PHY_DX7GCR4_DXREFSEN 0x1 - /*Register : DX5GCR6 @ 0XFD080C18

+ * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX7GCR4_RESERVED_24 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX5GCR6_RESERVED_31_30 0x0 + * External VREF generator REFSEL range select + * PSU_DDR_PHY_DX7GCR4_DXREFESELRANGE 0x0 - DRAM DQ VREF Select for Rank3 - PSU_DDR_PHY_DX5GCR6_DXDQVREFR3 0x9 + * Byte Lane External VREF Select + * PSU_DDR_PHY_DX7GCR4_DXREFESEL 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX5GCR6_RESERVED_23_22 0x0 + * Single ended VREF generator REFSEL range select + * PSU_DDR_PHY_DX7GCR4_DXREFSSELRANGE 0x1 - DRAM DQ VREF Select for Rank2 - PSU_DDR_PHY_DX5GCR6_DXDQVREFR2 0x9 + * Byte Lane Single-End VREF Select + * PSU_DDR_PHY_DX7GCR4_DXREFSSEL 0x30 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX5GCR6_RESERVED_15_14 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX7GCR4_RESERVED_7_6 0x0 - DRAM DQ VREF Select for Rank1 - PSU_DDR_PHY_DX5GCR6_DXDQVREFR1 0x2b + * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX7GCR4_DXREFIEN 0xf - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX5GCR6_RESERVED_7_6 0x0 + * VRMON control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX7GCR4_DXREFIMON 0x0 - DRAM DQ VREF Select for Rank0 - PSU_DDR_PHY_DX5GCR6_DXDQVREFR0 0x2b + * DATX8 n General Configuration Register 4 + * (OFFSET, MASK, VALUE) (0XFD080E10, 0xFFFFFFFFU ,0x0E00B03CU) + */ + PSU_Mask_Write(DDR_PHY_DX7GCR4_OFFSET, 0xFFFFFFFFU, 0x0E00B03CU); +/*##################################################################### */ - DATX8 n General Configuration Register 6 - (OFFSET, MASK, VALUE) (0XFD080C18, 0xFFFFFFFFU ,0x09092B2BU) - RegMask = (DDR_PHY_DX5GCR6_RESERVED_31_30_MASK | DDR_PHY_DX5GCR6_DXDQVREFR3_MASK | DDR_PHY_DX5GCR6_RESERVED_23_22_MASK | DDR_PHY_DX5GCR6_DXDQVREFR2_MASK | DDR_PHY_DX5GCR6_RESERVED_15_14_MASK | DDR_PHY_DX5GCR6_DXDQVREFR1_MASK | DDR_PHY_DX5GCR6_RESERVED_7_6_MASK | DDR_PHY_DX5GCR6_DXDQVREFR0_MASK | 0 ); + /* + * Register : DX7GCR5 @ 0XFD080E14 - RegVal = ((0x00000000U << DDR_PHY_DX5GCR6_RESERVED_31_30_SHIFT - | 0x00000009U << DDR_PHY_DX5GCR6_DXDQVREFR3_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR6_RESERVED_23_22_SHIFT - | 0x00000009U << DDR_PHY_DX5GCR6_DXDQVREFR2_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR6_RESERVED_15_14_SHIFT - | 0x0000002BU << DDR_PHY_DX5GCR6_DXDQVREFR1_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR6_RESERVED_7_6_SHIFT - | 0x0000002BU << DDR_PHY_DX5GCR6_DXDQVREFR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX5GCR6_OFFSET ,0xFFFFFFFFU ,0x09092B2BU); - /*############################################################################################################################ */ + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX7GCR5_RESERVED_31 0x0 - /*Register : DX5LCDLR2 @ 0XFD080C88

+ * Byte Lane internal VREF Select for Rank 3 + * PSU_DDR_PHY_DX7GCR5_DXREFISELR3 0x9 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX5LCDLR2_RESERVED_31_25 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX7GCR5_RESERVED_23 0x0 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX5LCDLR2_RESERVED_24_16 0x0 + * Byte Lane internal VREF Select for Rank 2 + * PSU_DDR_PHY_DX7GCR5_DXREFISELR2 0x9 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX5LCDLR2_RESERVED_15_9 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX7GCR5_RESERVED_15 0x0 - Read DQS Gating Delay - PSU_DDR_PHY_DX5LCDLR2_DQSGD 0x0 + * Byte Lane internal VREF Select for Rank 1 + * PSU_DDR_PHY_DX7GCR5_DXREFISELR1 0x55 - DATX8 n Local Calibrated Delay Line Register 2 - (OFFSET, MASK, VALUE) (0XFD080C88, 0xFFFFFFFFU ,0x00000000U) - RegMask = (DDR_PHY_DX5LCDLR2_RESERVED_31_25_MASK | DDR_PHY_DX5LCDLR2_RESERVED_24_16_MASK | DDR_PHY_DX5LCDLR2_RESERVED_15_9_MASK | DDR_PHY_DX5LCDLR2_DQSGD_MASK | 0 ); + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX7GCR5_RESERVED_7 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX5LCDLR2_RESERVED_31_25_SHIFT - | 0x00000000U << DDR_PHY_DX5LCDLR2_RESERVED_24_16_SHIFT - | 0x00000000U << DDR_PHY_DX5LCDLR2_RESERVED_15_9_SHIFT - | 0x00000000U << DDR_PHY_DX5LCDLR2_DQSGD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX5LCDLR2_OFFSET ,0xFFFFFFFFU ,0x00000000U); - /*############################################################################################################################ */ + * Byte Lane internal VREF Select for Rank 0 + * PSU_DDR_PHY_DX7GCR5_DXREFISELR0 0x55 - /*Register : DX5GTR0 @ 0XFD080CC0

+ * DATX8 n General Configuration Register 5 + * (OFFSET, MASK, VALUE) (0XFD080E14, 0xFFFFFFFFU ,0x09095555U) + */ + PSU_Mask_Write(DDR_PHY_DX7GCR5_OFFSET, 0xFFFFFFFFU, 0x09095555U); +/*##################################################################### */ - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX5GTR0_RESERVED_31_24 0x0 + /* + * Register : DX7GCR6 @ 0XFD080E18 - DQ Write Path Latency Pipeline - PSU_DDR_PHY_DX5GTR0_WDQSL 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX7GCR6_RESERVED_31_30 0x0 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX5GTR0_RESERVED_23_20 0x0 + * DRAM DQ VREF Select for Rank3 + * PSU_DDR_PHY_DX7GCR6_DXDQVREFR3 0x9 - Write Leveling System Latency - PSU_DDR_PHY_DX5GTR0_WLSL 0x2 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX7GCR6_RESERVED_23_22 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX5GTR0_RESERVED_15_13 0x0 + * DRAM DQ VREF Select for Rank2 + * PSU_DDR_PHY_DX7GCR6_DXDQVREFR2 0x9 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX5GTR0_RESERVED_12_8 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX7GCR6_RESERVED_15_14 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX5GTR0_RESERVED_7_5 0x0 + * DRAM DQ VREF Select for Rank1 + * PSU_DDR_PHY_DX7GCR6_DXDQVREFR1 0x2b - DQS Gating System Latency - PSU_DDR_PHY_DX5GTR0_DGSL 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX7GCR6_RESERVED_7_6 0x0 - DATX8 n General Timing Register 0 - (OFFSET, MASK, VALUE) (0XFD080CC0, 0xFFFFFFFFU ,0x00020000U) - RegMask = (DDR_PHY_DX5GTR0_RESERVED_31_24_MASK | DDR_PHY_DX5GTR0_WDQSL_MASK | DDR_PHY_DX5GTR0_RESERVED_23_20_MASK | DDR_PHY_DX5GTR0_WLSL_MASK | DDR_PHY_DX5GTR0_RESERVED_15_13_MASK | DDR_PHY_DX5GTR0_RESERVED_12_8_MASK | DDR_PHY_DX5GTR0_RESERVED_7_5_MASK | DDR_PHY_DX5GTR0_DGSL_MASK | 0 ); + * DRAM DQ VREF Select for Rank0 + * PSU_DDR_PHY_DX7GCR6_DXDQVREFR0 0x2b - RegVal = ((0x00000000U << DDR_PHY_DX5GTR0_RESERVED_31_24_SHIFT - | 0x00000000U << DDR_PHY_DX5GTR0_WDQSL_SHIFT - | 0x00000000U << DDR_PHY_DX5GTR0_RESERVED_23_20_SHIFT - | 0x00000002U << DDR_PHY_DX5GTR0_WLSL_SHIFT - | 0x00000000U << DDR_PHY_DX5GTR0_RESERVED_15_13_SHIFT - | 0x00000000U << DDR_PHY_DX5GTR0_RESERVED_12_8_SHIFT - | 0x00000000U << DDR_PHY_DX5GTR0_RESERVED_7_5_SHIFT - | 0x00000000U << DDR_PHY_DX5GTR0_DGSL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX5GTR0_OFFSET ,0xFFFFFFFFU ,0x00020000U); - /*############################################################################################################################ */ + * DATX8 n General Configuration Register 6 + * (OFFSET, MASK, VALUE) (0XFD080E18, 0xFFFFFFFFU ,0x09092B2BU) + */ + PSU_Mask_Write(DDR_PHY_DX7GCR6_OFFSET, 0xFFFFFFFFU, 0x09092B2BU); +/*##################################################################### */ - /*Register : DX6GCR0 @ 0XFD080D00

+ /* + * Register : DX8GCR0 @ 0XFD080F00 - Calibration Bypass - PSU_DDR_PHY_DX6GCR0_CALBYP 0x0 + * Calibration Bypass + * PSU_DDR_PHY_DX8GCR0_CALBYP 0x0 - Master Delay Line Enable - PSU_DDR_PHY_DX6GCR0_MDLEN 0x1 + * Master Delay Line Enable + * PSU_DDR_PHY_DX8GCR0_MDLEN 0x1 - Configurable ODT(TE) Phase Shift - PSU_DDR_PHY_DX6GCR0_CODTSHFT 0x0 + * Configurable ODT(TE) Phase Shift + * PSU_DDR_PHY_DX8GCR0_CODTSHFT 0x0 - DQS Duty Cycle Correction - PSU_DDR_PHY_DX6GCR0_DQSDCC 0x0 + * DQS Duty Cycle Correction + * PSU_DDR_PHY_DX8GCR0_DQSDCC 0x0 - Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY - PSU_DDR_PHY_DX6GCR0_RDDLY 0x8 + * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY + * PSU_DDR_PHY_DX8GCR0_RDDLY 0x8 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX6GCR0_RESERVED_19_14 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8GCR0_RESERVED_19_14 0x0 - DQSNSE Power Down Receiver - PSU_DDR_PHY_DX6GCR0_DQSNSEPDR 0x0 + * DQSNSE Power Down Receiver + * PSU_DDR_PHY_DX8GCR0_DQSNSEPDR 0x0 - DQSSE Power Down Receiver - PSU_DDR_PHY_DX6GCR0_DQSSEPDR 0x0 + * DQSSE Power Down Receiver + * PSU_DDR_PHY_DX8GCR0_DQSSEPDR 0x0 - RTT On Additive Latency - PSU_DDR_PHY_DX6GCR0_RTTOAL 0x0 + * RTT On Additive Latency + * PSU_DDR_PHY_DX8GCR0_RTTOAL 0x0 - RTT Output Hold - PSU_DDR_PHY_DX6GCR0_RTTOH 0x3 + * RTT Output Hold + * PSU_DDR_PHY_DX8GCR0_RTTOH 0x3 - Configurable PDR Phase Shift - PSU_DDR_PHY_DX6GCR0_CPDRSHFT 0x0 + * Configurable PDR Phase Shift + * PSU_DDR_PHY_DX8GCR0_CPDRSHFT 0x0 - DQSR Power Down - PSU_DDR_PHY_DX6GCR0_DQSRPD 0x0 + * DQSR Power Down + * PSU_DDR_PHY_DX8GCR0_DQSRPD 0x0 - DQSG Power Down Receiver - PSU_DDR_PHY_DX6GCR0_DQSGPDR 0x0 + * DQSG Power Down Receiver + * PSU_DDR_PHY_DX8GCR0_DQSGPDR 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX6GCR0_RESERVED_4 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8GCR0_RESERVED_4 0x0 - DQSG On-Die Termination - PSU_DDR_PHY_DX6GCR0_DQSGODT 0x0 + * DQSG On-Die Termination + * PSU_DDR_PHY_DX8GCR0_DQSGODT 0x0 - DQSG Output Enable - PSU_DDR_PHY_DX6GCR0_DQSGOE 0x1 + * DQSG Output Enable + * PSU_DDR_PHY_DX8GCR0_DQSGOE 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX6GCR0_RESERVED_1_0 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8GCR0_RESERVED_1_0 0x0 - DATX8 n General Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD080D00, 0xFFFFFFFFU ,0x40800604U) - RegMask = (DDR_PHY_DX6GCR0_CALBYP_MASK | DDR_PHY_DX6GCR0_MDLEN_MASK | DDR_PHY_DX6GCR0_CODTSHFT_MASK | DDR_PHY_DX6GCR0_DQSDCC_MASK | DDR_PHY_DX6GCR0_RDDLY_MASK | DDR_PHY_DX6GCR0_RESERVED_19_14_MASK | DDR_PHY_DX6GCR0_DQSNSEPDR_MASK | DDR_PHY_DX6GCR0_DQSSEPDR_MASK | DDR_PHY_DX6GCR0_RTTOAL_MASK | DDR_PHY_DX6GCR0_RTTOH_MASK | DDR_PHY_DX6GCR0_CPDRSHFT_MASK | DDR_PHY_DX6GCR0_DQSRPD_MASK | DDR_PHY_DX6GCR0_DQSGPDR_MASK | DDR_PHY_DX6GCR0_RESERVED_4_MASK | DDR_PHY_DX6GCR0_DQSGODT_MASK | DDR_PHY_DX6GCR0_DQSGOE_MASK | DDR_PHY_DX6GCR0_RESERVED_1_0_MASK | 0 ); + * DATX8 n General Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD080F00, 0xFFFFFFFFU ,0x40800624U) + */ + PSU_Mask_Write(DDR_PHY_DX8GCR0_OFFSET, 0xFFFFFFFFU, 0x40800624U); +/*##################################################################### */ - RegVal = ((0x00000000U << DDR_PHY_DX6GCR0_CALBYP_SHIFT - | 0x00000001U << DDR_PHY_DX6GCR0_MDLEN_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR0_CODTSHFT_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR0_DQSDCC_SHIFT - | 0x00000008U << DDR_PHY_DX6GCR0_RDDLY_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR0_RESERVED_19_14_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR0_DQSNSEPDR_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR0_DQSSEPDR_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR0_RTTOAL_SHIFT - | 0x00000003U << DDR_PHY_DX6GCR0_RTTOH_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR0_CPDRSHFT_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR0_DQSRPD_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR0_DQSGPDR_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR0_RESERVED_4_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR0_DQSGODT_SHIFT - | 0x00000001U << DDR_PHY_DX6GCR0_DQSGOE_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR0_RESERVED_1_0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX6GCR0_OFFSET ,0xFFFFFFFFU ,0x40800604U); - /*############################################################################################################################ */ + /* + * Register : DX8GCR1 @ 0XFD080F04 - /*Register : DX6GCR1 @ 0XFD080D04

+ * Enables the PDR mode for DQ[7:0] + * PSU_DDR_PHY_DX8GCR1_DXPDRMODE 0x0 - Enables the PDR mode for DQ[7:0] - PSU_DDR_PHY_DX6GCR1_DXPDRMODE 0x0 + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX8GCR1_RESERVED_15 0x0 - Reserved. Returns zeroes on reads. - PSU_DDR_PHY_DX6GCR1_RESERVED_15 0x0 + * Select the delayed or non-delayed read data strobe # + * PSU_DDR_PHY_DX8GCR1_QSNSEL 0x1 - Select the delayed or non-delayed read data strobe # - PSU_DDR_PHY_DX6GCR1_QSNSEL 0x1 + * Select the delayed or non-delayed read data strobe + * PSU_DDR_PHY_DX8GCR1_QSSEL 0x1 - Select the delayed or non-delayed read data strobe - PSU_DDR_PHY_DX6GCR1_QSSEL 0x1 + * Enables Read Data Strobe in a byte lane + * PSU_DDR_PHY_DX8GCR1_OEEN 0x1 - Enables Read Data Strobe in a byte lane - PSU_DDR_PHY_DX6GCR1_OEEN 0x1 + * Enables PDR in a byte lane + * PSU_DDR_PHY_DX8GCR1_PDREN 0x1 - Enables PDR in a byte lane - PSU_DDR_PHY_DX6GCR1_PDREN 0x1 + * Enables ODT/TE in a byte lane + * PSU_DDR_PHY_DX8GCR1_TEEN 0x1 - Enables ODT/TE in a byte lane - PSU_DDR_PHY_DX6GCR1_TEEN 0x1 + * Enables Write Data strobe in a byte lane + * PSU_DDR_PHY_DX8GCR1_DSEN 0x1 - Enables Write Data strobe in a byte lane - PSU_DDR_PHY_DX6GCR1_DSEN 0x1 + * Enables DM pin in a byte lane + * PSU_DDR_PHY_DX8GCR1_DMEN 0x1 - Enables DM pin in a byte lane - PSU_DDR_PHY_DX6GCR1_DMEN 0x1 + * Enables DQ corresponding to each bit in a byte + * PSU_DDR_PHY_DX8GCR1_DQEN 0x0 - Enables DQ corresponding to each bit in a byte - PSU_DDR_PHY_DX6GCR1_DQEN 0xff + * DATX8 n General Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD080F04, 0xFFFFFFFFU ,0x00007F00U) + */ + PSU_Mask_Write(DDR_PHY_DX8GCR1_OFFSET, 0xFFFFFFFFU, 0x00007F00U); +/*##################################################################### */ - DATX8 n General Configuration Register 1 - (OFFSET, MASK, VALUE) (0XFD080D04, 0xFFFFFFFFU ,0x00007FFFU) - RegMask = (DDR_PHY_DX6GCR1_DXPDRMODE_MASK | DDR_PHY_DX6GCR1_RESERVED_15_MASK | DDR_PHY_DX6GCR1_QSNSEL_MASK | DDR_PHY_DX6GCR1_QSSEL_MASK | DDR_PHY_DX6GCR1_OEEN_MASK | DDR_PHY_DX6GCR1_PDREN_MASK | DDR_PHY_DX6GCR1_TEEN_MASK | DDR_PHY_DX6GCR1_DSEN_MASK | DDR_PHY_DX6GCR1_DMEN_MASK | DDR_PHY_DX6GCR1_DQEN_MASK | 0 ); + /* + * Register : DX8GCR4 @ 0XFD080F10 - RegVal = ((0x00000000U << DDR_PHY_DX6GCR1_DXPDRMODE_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR1_RESERVED_15_SHIFT - | 0x00000001U << DDR_PHY_DX6GCR1_QSNSEL_SHIFT - | 0x00000001U << DDR_PHY_DX6GCR1_QSSEL_SHIFT - | 0x00000001U << DDR_PHY_DX6GCR1_OEEN_SHIFT - | 0x00000001U << DDR_PHY_DX6GCR1_PDREN_SHIFT - | 0x00000001U << DDR_PHY_DX6GCR1_TEEN_SHIFT - | 0x00000001U << DDR_PHY_DX6GCR1_DSEN_SHIFT - | 0x00000001U << DDR_PHY_DX6GCR1_DMEN_SHIFT - | 0x000000FFU << DDR_PHY_DX6GCR1_DQEN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX6GCR1_OFFSET ,0xFFFFFFFFU ,0x00007FFFU); - /*############################################################################################################################ */ + * Byte lane VREF IOM (Used only by D4MU IOs) + * PSU_DDR_PHY_DX8GCR4_RESERVED_31_29 0x0 - /*Register : DX6GCR4 @ 0XFD080D10

+ * Byte Lane VREF Pad Enable + * PSU_DDR_PHY_DX8GCR4_DXREFPEN 0x0 - Byte lane VREF IOM (Used only by D4MU IOs) - PSU_DDR_PHY_DX6GCR4_RESERVED_31_29 0x0 + * Byte Lane Internal VREF Enable + * PSU_DDR_PHY_DX8GCR4_DXREFEEN 0x3 - Byte Lane VREF Pad Enable - PSU_DDR_PHY_DX6GCR4_DXREFPEN 0x0 + * Byte Lane Single-End VREF Enable + * PSU_DDR_PHY_DX8GCR4_DXREFSEN 0x1 - Byte Lane Internal VREF Enable - PSU_DDR_PHY_DX6GCR4_DXREFEEN 0x3 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX8GCR4_RESERVED_24 0x0 - Byte Lane Single-End VREF Enable - PSU_DDR_PHY_DX6GCR4_DXREFSEN 0x1 + * External VREF generator REFSEL range select + * PSU_DDR_PHY_DX8GCR4_DXREFESELRANGE 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX6GCR4_RESERVED_24 0x0 + * Byte Lane External VREF Select + * PSU_DDR_PHY_DX8GCR4_DXREFESEL 0x0 - External VREF generator REFSEL range select - PSU_DDR_PHY_DX6GCR4_DXREFESELRANGE 0x0 + * Single ended VREF generator REFSEL range select + * PSU_DDR_PHY_DX8GCR4_DXREFSSELRANGE 0x1 - Byte Lane External VREF Select - PSU_DDR_PHY_DX6GCR4_DXREFESEL 0x0 + * Byte Lane Single-End VREF Select + * PSU_DDR_PHY_DX8GCR4_DXREFSSEL 0x30 - Single ended VREF generator REFSEL range select - PSU_DDR_PHY_DX6GCR4_DXREFSSELRANGE 0x1 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX8GCR4_RESERVED_7_6 0x0 - Byte Lane Single-End VREF Select - PSU_DDR_PHY_DX6GCR4_DXREFSSEL 0x30 + * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX8GCR4_DXREFIEN 0xf - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX6GCR4_RESERVED_7_6 0x0 + * VRMON control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX8GCR4_DXREFIMON 0x0 - VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. - PSU_DDR_PHY_DX6GCR4_DXREFIEN 0xf + * DATX8 n General Configuration Register 4 + * (OFFSET, MASK, VALUE) (0XFD080F10, 0xFFFFFFFFU ,0x0E00B03CU) + */ + PSU_Mask_Write(DDR_PHY_DX8GCR4_OFFSET, 0xFFFFFFFFU, 0x0E00B03CU); +/*##################################################################### */ - VRMON control for DQ IO (Single Ended) buffers of a byte lane. - PSU_DDR_PHY_DX6GCR4_DXREFIMON 0x0 + /* + * Register : DX8GCR5 @ 0XFD080F14 - DATX8 n General Configuration Register 4 - (OFFSET, MASK, VALUE) (0XFD080D10, 0xFFFFFFFFU ,0x0E00B03CU) - RegMask = (DDR_PHY_DX6GCR4_RESERVED_31_29_MASK | DDR_PHY_DX6GCR4_DXREFPEN_MASK | DDR_PHY_DX6GCR4_DXREFEEN_MASK | DDR_PHY_DX6GCR4_DXREFSEN_MASK | DDR_PHY_DX6GCR4_RESERVED_24_MASK | DDR_PHY_DX6GCR4_DXREFESELRANGE_MASK | DDR_PHY_DX6GCR4_DXREFESEL_MASK | DDR_PHY_DX6GCR4_DXREFSSELRANGE_MASK | DDR_PHY_DX6GCR4_DXREFSSEL_MASK | DDR_PHY_DX6GCR4_RESERVED_7_6_MASK | DDR_PHY_DX6GCR4_DXREFIEN_MASK | DDR_PHY_DX6GCR4_DXREFIMON_MASK | 0 ); + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX8GCR5_RESERVED_31 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX6GCR4_RESERVED_31_29_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR4_DXREFPEN_SHIFT - | 0x00000003U << DDR_PHY_DX6GCR4_DXREFEEN_SHIFT - | 0x00000001U << DDR_PHY_DX6GCR4_DXREFSEN_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR4_RESERVED_24_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR4_DXREFESELRANGE_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR4_DXREFESEL_SHIFT - | 0x00000001U << DDR_PHY_DX6GCR4_DXREFSSELRANGE_SHIFT - | 0x00000030U << DDR_PHY_DX6GCR4_DXREFSSEL_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR4_RESERVED_7_6_SHIFT - | 0x0000000FU << DDR_PHY_DX6GCR4_DXREFIEN_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR4_DXREFIMON_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX6GCR4_OFFSET ,0xFFFFFFFFU ,0x0E00B03CU); - /*############################################################################################################################ */ + * Byte Lane internal VREF Select for Rank 3 + * PSU_DDR_PHY_DX8GCR5_DXREFISELR3 0x9 - /*Register : DX6GCR5 @ 0XFD080D14

+ * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX8GCR5_RESERVED_23 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX6GCR5_RESERVED_31 0x0 + * Byte Lane internal VREF Select for Rank 2 + * PSU_DDR_PHY_DX8GCR5_DXREFISELR2 0x9 - Byte Lane internal VREF Select for Rank 3 - PSU_DDR_PHY_DX6GCR5_DXREFISELR3 0x9 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX8GCR5_RESERVED_15 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX6GCR5_RESERVED_23 0x0 + * Byte Lane internal VREF Select for Rank 1 + * PSU_DDR_PHY_DX8GCR5_DXREFISELR1 0x55 - Byte Lane internal VREF Select for Rank 2 - PSU_DDR_PHY_DX6GCR5_DXREFISELR2 0x9 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX8GCR5_RESERVED_7 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX6GCR5_RESERVED_15 0x0 + * Byte Lane internal VREF Select for Rank 0 + * PSU_DDR_PHY_DX8GCR5_DXREFISELR0 0x55 - Byte Lane internal VREF Select for Rank 1 - PSU_DDR_PHY_DX6GCR5_DXREFISELR1 0x4f + * DATX8 n General Configuration Register 5 + * (OFFSET, MASK, VALUE) (0XFD080F14, 0xFFFFFFFFU ,0x09095555U) + */ + PSU_Mask_Write(DDR_PHY_DX8GCR5_OFFSET, 0xFFFFFFFFU, 0x09095555U); +/*##################################################################### */ - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX6GCR5_RESERVED_7 0x0 + /* + * Register : DX8GCR6 @ 0XFD080F18 - Byte Lane internal VREF Select for Rank 0 - PSU_DDR_PHY_DX6GCR5_DXREFISELR0 0x4f + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX8GCR6_RESERVED_31_30 0x0 - DATX8 n General Configuration Register 5 - (OFFSET, MASK, VALUE) (0XFD080D14, 0xFFFFFFFFU ,0x09094F4FU) - RegMask = (DDR_PHY_DX6GCR5_RESERVED_31_MASK | DDR_PHY_DX6GCR5_DXREFISELR3_MASK | DDR_PHY_DX6GCR5_RESERVED_23_MASK | DDR_PHY_DX6GCR5_DXREFISELR2_MASK | DDR_PHY_DX6GCR5_RESERVED_15_MASK | DDR_PHY_DX6GCR5_DXREFISELR1_MASK | DDR_PHY_DX6GCR5_RESERVED_7_MASK | DDR_PHY_DX6GCR5_DXREFISELR0_MASK | 0 ); + * DRAM DQ VREF Select for Rank3 + * PSU_DDR_PHY_DX8GCR6_DXDQVREFR3 0x9 - RegVal = ((0x00000000U << DDR_PHY_DX6GCR5_RESERVED_31_SHIFT - | 0x00000009U << DDR_PHY_DX6GCR5_DXREFISELR3_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR5_RESERVED_23_SHIFT - | 0x00000009U << DDR_PHY_DX6GCR5_DXREFISELR2_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR5_RESERVED_15_SHIFT - | 0x0000004FU << DDR_PHY_DX6GCR5_DXREFISELR1_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR5_RESERVED_7_SHIFT - | 0x0000004FU << DDR_PHY_DX6GCR5_DXREFISELR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX6GCR5_OFFSET ,0xFFFFFFFFU ,0x09094F4FU); - /*############################################################################################################################ */ + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX8GCR6_RESERVED_23_22 0x0 - /*Register : DX6GCR6 @ 0XFD080D18

+ * DRAM DQ VREF Select for Rank2 + * PSU_DDR_PHY_DX8GCR6_DXDQVREFR2 0x9 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX6GCR6_RESERVED_31_30 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX8GCR6_RESERVED_15_14 0x0 - DRAM DQ VREF Select for Rank3 - PSU_DDR_PHY_DX6GCR6_DXDQVREFR3 0x9 + * DRAM DQ VREF Select for Rank1 + * PSU_DDR_PHY_DX8GCR6_DXDQVREFR1 0x2b - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX6GCR6_RESERVED_23_22 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX8GCR6_RESERVED_7_6 0x0 - DRAM DQ VREF Select for Rank2 - PSU_DDR_PHY_DX6GCR6_DXDQVREFR2 0x9 + * DRAM DQ VREF Select for Rank0 + * PSU_DDR_PHY_DX8GCR6_DXDQVREFR0 0x2b - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX6GCR6_RESERVED_15_14 0x0 + * DATX8 n General Configuration Register 6 + * (OFFSET, MASK, VALUE) (0XFD080F18, 0xFFFFFFFFU ,0x09092B2BU) + */ + PSU_Mask_Write(DDR_PHY_DX8GCR6_OFFSET, 0xFFFFFFFFU, 0x09092B2BU); +/*##################################################################### */ - DRAM DQ VREF Select for Rank1 - PSU_DDR_PHY_DX6GCR6_DXDQVREFR1 0x2b + /* + * Register : DX8SL0OSC @ 0XFD081400 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX6GCR6_RESERVED_7_6 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL0OSC_RESERVED_31_30 0x0 - DRAM DQ VREF Select for Rank0 - PSU_DDR_PHY_DX6GCR6_DXDQVREFR0 0x2b + * Enable Clock Gating for DX ddr_clk + * PSU_DDR_PHY_DX8SL0OSC_GATEDXRDCLK 0x2 - DATX8 n General Configuration Register 6 - (OFFSET, MASK, VALUE) (0XFD080D18, 0xFFFFFFFFU ,0x09092B2BU) - RegMask = (DDR_PHY_DX6GCR6_RESERVED_31_30_MASK | DDR_PHY_DX6GCR6_DXDQVREFR3_MASK | DDR_PHY_DX6GCR6_RESERVED_23_22_MASK | DDR_PHY_DX6GCR6_DXDQVREFR2_MASK | DDR_PHY_DX6GCR6_RESERVED_15_14_MASK | DDR_PHY_DX6GCR6_DXDQVREFR1_MASK | DDR_PHY_DX6GCR6_RESERVED_7_6_MASK | DDR_PHY_DX6GCR6_DXDQVREFR0_MASK | 0 ); + * Enable Clock Gating for DX ctl_rd_clk + * PSU_DDR_PHY_DX8SL0OSC_GATEDXDDRCLK 0x2 - RegVal = ((0x00000000U << DDR_PHY_DX6GCR6_RESERVED_31_30_SHIFT - | 0x00000009U << DDR_PHY_DX6GCR6_DXDQVREFR3_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR6_RESERVED_23_22_SHIFT - | 0x00000009U << DDR_PHY_DX6GCR6_DXDQVREFR2_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR6_RESERVED_15_14_SHIFT - | 0x0000002BU << DDR_PHY_DX6GCR6_DXDQVREFR1_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR6_RESERVED_7_6_SHIFT - | 0x0000002BU << DDR_PHY_DX6GCR6_DXDQVREFR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX6GCR6_OFFSET ,0xFFFFFFFFU ,0x09092B2BU); - /*############################################################################################################################ */ + * Enable Clock Gating for DX ctl_clk + * PSU_DDR_PHY_DX8SL0OSC_GATEDXCTLCLK 0x2 - /*Register : DX6LCDLR2 @ 0XFD080D88

+ * Selects the level to which clocks will be stalled when clock gating is e + * nabled. + * PSU_DDR_PHY_DX8SL0OSC_CLKLEVEL 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX6LCDLR2_RESERVED_31_25 0x0 + * Loopback Mode + * PSU_DDR_PHY_DX8SL0OSC_LBMODE 0x0 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX6LCDLR2_RESERVED_24_16 0x0 + * Load GSDQS LCDL with 2x the calibrated GSDQSPRD value + * PSU_DDR_PHY_DX8SL0OSC_LBGSDQS 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX6LCDLR2_RESERVED_15_9 0x0 + * Loopback DQS Gating + * PSU_DDR_PHY_DX8SL0OSC_LBGDQS 0x0 - Read DQS Gating Delay - PSU_DDR_PHY_DX6LCDLR2_DQSGD 0x0 + * Loopback DQS Shift + * PSU_DDR_PHY_DX8SL0OSC_LBDQSS 0x0 - DATX8 n Local Calibrated Delay Line Register 2 - (OFFSET, MASK, VALUE) (0XFD080D88, 0xFFFFFFFFU ,0x00000000U) - RegMask = (DDR_PHY_DX6LCDLR2_RESERVED_31_25_MASK | DDR_PHY_DX6LCDLR2_RESERVED_24_16_MASK | DDR_PHY_DX6LCDLR2_RESERVED_15_9_MASK | DDR_PHY_DX6LCDLR2_DQSGD_MASK | 0 ); + * PHY High-Speed Reset + * PSU_DDR_PHY_DX8SL0OSC_PHYHRST 0x1 - RegVal = ((0x00000000U << DDR_PHY_DX6LCDLR2_RESERVED_31_25_SHIFT - | 0x00000000U << DDR_PHY_DX6LCDLR2_RESERVED_24_16_SHIFT - | 0x00000000U << DDR_PHY_DX6LCDLR2_RESERVED_15_9_SHIFT - | 0x00000000U << DDR_PHY_DX6LCDLR2_DQSGD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX6LCDLR2_OFFSET ,0xFFFFFFFFU ,0x00000000U); - /*############################################################################################################################ */ + * PHY FIFO Reset + * PSU_DDR_PHY_DX8SL0OSC_PHYFRST 0x1 - /*Register : DX6GTR0 @ 0XFD080DC0

+ * Delay Line Test Start + * PSU_DDR_PHY_DX8SL0OSC_DLTST 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX6GTR0_RESERVED_31_24 0x0 + * Delay Line Test Mode + * PSU_DDR_PHY_DX8SL0OSC_DLTMODE 0x0 - DQ Write Path Latency Pipeline - PSU_DDR_PHY_DX6GTR0_WDQSL 0x0 + * Reserved. Caution, do not write to this register field. + * PSU_DDR_PHY_DX8SL0OSC_RESERVED_12_11 0x3 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX6GTR0_RESERVED_23_20 0x0 + * Oscillator Mode Write-Data Delay Line Select + * PSU_DDR_PHY_DX8SL0OSC_OSCWDDL 0x3 - Write Leveling System Latency - PSU_DDR_PHY_DX6GTR0_WLSL 0x2 + * Reserved. Caution, do not write to this register field. + * PSU_DDR_PHY_DX8SL0OSC_RESERVED_8_7 0x3 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX6GTR0_RESERVED_15_13 0x0 + * Oscillator Mode Write-Leveling Delay Line Select + * PSU_DDR_PHY_DX8SL0OSC_OSCWDL 0x3 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX6GTR0_RESERVED_12_8 0x0 + * Oscillator Mode Division + * PSU_DDR_PHY_DX8SL0OSC_OSCDIV 0xf - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX6GTR0_RESERVED_7_5 0x0 + * Oscillator Enable + * PSU_DDR_PHY_DX8SL0OSC_OSCEN 0x0 - DQS Gating System Latency - PSU_DDR_PHY_DX6GTR0_DGSL 0x0 + * DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Lo + * opback, and Gated Clock Control Register + * (OFFSET, MASK, VALUE) (0XFD081400, 0xFFFFFFFFU ,0x2A019FFEU) + */ + PSU_Mask_Write(DDR_PHY_DX8SL0OSC_OFFSET, 0xFFFFFFFFU, 0x2A019FFEU); +/*##################################################################### */ - DATX8 n General Timing Register 0 - (OFFSET, MASK, VALUE) (0XFD080DC0, 0xFFFFFFFFU ,0x00020000U) - RegMask = (DDR_PHY_DX6GTR0_RESERVED_31_24_MASK | DDR_PHY_DX6GTR0_WDQSL_MASK | DDR_PHY_DX6GTR0_RESERVED_23_20_MASK | DDR_PHY_DX6GTR0_WLSL_MASK | DDR_PHY_DX6GTR0_RESERVED_15_13_MASK | DDR_PHY_DX6GTR0_RESERVED_12_8_MASK | DDR_PHY_DX6GTR0_RESERVED_7_5_MASK | DDR_PHY_DX6GTR0_DGSL_MASK | 0 ); + /* + * Register : DX8SL0PLLCR0 @ 0XFD081404 - RegVal = ((0x00000000U << DDR_PHY_DX6GTR0_RESERVED_31_24_SHIFT - | 0x00000000U << DDR_PHY_DX6GTR0_WDQSL_SHIFT - | 0x00000000U << DDR_PHY_DX6GTR0_RESERVED_23_20_SHIFT - | 0x00000002U << DDR_PHY_DX6GTR0_WLSL_SHIFT - | 0x00000000U << DDR_PHY_DX6GTR0_RESERVED_15_13_SHIFT - | 0x00000000U << DDR_PHY_DX6GTR0_RESERVED_12_8_SHIFT - | 0x00000000U << DDR_PHY_DX6GTR0_RESERVED_7_5_SHIFT - | 0x00000000U << DDR_PHY_DX6GTR0_DGSL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX6GTR0_OFFSET ,0xFFFFFFFFU ,0x00020000U); - /*############################################################################################################################ */ + * PLL Bypass + * PSU_DDR_PHY_DX8SL0PLLCR0_PLLBYP 0x0 - /*Register : DX7GCR0 @ 0XFD080E00

+ * PLL Reset + * PSU_DDR_PHY_DX8SL0PLLCR0_PLLRST 0x0 - Calibration Bypass - PSU_DDR_PHY_DX7GCR0_CALBYP 0x0 + * PLL Power Down + * PSU_DDR_PHY_DX8SL0PLLCR0_PLLPD 0x0 - Master Delay Line Enable - PSU_DDR_PHY_DX7GCR0_MDLEN 0x1 + * Reference Stop Mode + * PSU_DDR_PHY_DX8SL0PLLCR0_RSTOPM 0x0 - Configurable ODT(TE) Phase Shift - PSU_DDR_PHY_DX7GCR0_CODTSHFT 0x0 + * PLL Frequency Select + * PSU_DDR_PHY_DX8SL0PLLCR0_FRQSEL 0x1 - DQS Duty Cycle Correction - PSU_DDR_PHY_DX7GCR0_DQSDCC 0x0 + * Relock Mode + * PSU_DDR_PHY_DX8SL0PLLCR0_RLOCKM 0x0 - Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY - PSU_DDR_PHY_DX7GCR0_RDDLY 0x8 + * Charge Pump Proportional Current Control + * PSU_DDR_PHY_DX8SL0PLLCR0_CPPC 0x8 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX7GCR0_RESERVED_19_14 0x0 + * Charge Pump Integrating Current Control + * PSU_DDR_PHY_DX8SL0PLLCR0_CPIC 0x0 - DQSNSE Power Down Receiver - PSU_DDR_PHY_DX7GCR0_DQSNSEPDR 0x0 + * Gear Shift + * PSU_DDR_PHY_DX8SL0PLLCR0_GSHIFT 0x0 - DQSSE Power Down Receiver - PSU_DDR_PHY_DX7GCR0_DQSSEPDR 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL0PLLCR0_RESERVED_11_9 0x0 - RTT On Additive Latency - PSU_DDR_PHY_DX7GCR0_RTTOAL 0x0 + * Analog Test Enable (ATOEN) + * PSU_DDR_PHY_DX8SL0PLLCR0_ATOEN 0x0 - RTT Output Hold - PSU_DDR_PHY_DX7GCR0_RTTOH 0x3 + * Analog Test Control + * PSU_DDR_PHY_DX8SL0PLLCR0_ATC 0x0 - Configurable PDR Phase Shift - PSU_DDR_PHY_DX7GCR0_CPDRSHFT 0x0 + * Digital Test Control + * PSU_DDR_PHY_DX8SL0PLLCR0_DTC 0x0 - DQSR Power Down - PSU_DDR_PHY_DX7GCR0_DQSRPD 0x0 + * DAXT8 0-1 PLL Control Register 0 + * (OFFSET, MASK, VALUE) (0XFD081404, 0xFFFFFFFFU ,0x01100000U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL0PLLCR0_OFFSET, + 0xFFFFFFFFU, 0x01100000U); +/*##################################################################### */ - DQSG Power Down Receiver - PSU_DDR_PHY_DX7GCR0_DQSGPDR 0x0 + /* + * Register : DX8SL0DQSCTL @ 0XFD08141C - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX7GCR0_RESERVED_4 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25 0x0 - DQSG On-Die Termination - PSU_DDR_PHY_DX7GCR0_DQSGODT 0x0 + * Read Path Rise-to-Rise Mode + * PSU_DDR_PHY_DX8SL0DQSCTL_RRRMODE 0x1 - DQSG Output Enable - PSU_DDR_PHY_DX7GCR0_DQSGOE 0x1 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX7GCR0_RESERVED_1_0 0x0 + * Write Path Rise-to-Rise Mode + * PSU_DDR_PHY_DX8SL0DQSCTL_WRRMODE 0x1 - DATX8 n General Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD080E00, 0xFFFFFFFFU ,0x40800604U) - RegMask = (DDR_PHY_DX7GCR0_CALBYP_MASK | DDR_PHY_DX7GCR0_MDLEN_MASK | DDR_PHY_DX7GCR0_CODTSHFT_MASK | DDR_PHY_DX7GCR0_DQSDCC_MASK | DDR_PHY_DX7GCR0_RDDLY_MASK | DDR_PHY_DX7GCR0_RESERVED_19_14_MASK | DDR_PHY_DX7GCR0_DQSNSEPDR_MASK | DDR_PHY_DX7GCR0_DQSSEPDR_MASK | DDR_PHY_DX7GCR0_RTTOAL_MASK | DDR_PHY_DX7GCR0_RTTOH_MASK | DDR_PHY_DX7GCR0_CPDRSHFT_MASK | DDR_PHY_DX7GCR0_DQSRPD_MASK | DDR_PHY_DX7GCR0_DQSGPDR_MASK | DDR_PHY_DX7GCR0_RESERVED_4_MASK | DDR_PHY_DX7GCR0_DQSGODT_MASK | DDR_PHY_DX7GCR0_DQSGOE_MASK | DDR_PHY_DX7GCR0_RESERVED_1_0_MASK | 0 ); + * DQS Gate Extension + * PSU_DDR_PHY_DX8SL0DQSCTL_DQSGX 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX7GCR0_CALBYP_SHIFT - | 0x00000001U << DDR_PHY_DX7GCR0_MDLEN_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR0_CODTSHFT_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR0_DQSDCC_SHIFT - | 0x00000008U << DDR_PHY_DX7GCR0_RDDLY_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR0_RESERVED_19_14_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR0_DQSNSEPDR_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR0_DQSSEPDR_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR0_RTTOAL_SHIFT - | 0x00000003U << DDR_PHY_DX7GCR0_RTTOH_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR0_CPDRSHFT_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR0_DQSRPD_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR0_DQSGPDR_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR0_RESERVED_4_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR0_DQSGODT_SHIFT - | 0x00000001U << DDR_PHY_DX7GCR0_DQSGOE_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR0_RESERVED_1_0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX7GCR0_OFFSET ,0xFFFFFFFFU ,0x40800604U); - /*############################################################################################################################ */ + * Low Power PLL Power Down + * PSU_DDR_PHY_DX8SL0DQSCTL_LPPLLPD 0x1 - /*Register : DX7GCR1 @ 0XFD080E04

+ * Low Power I/O Power Down + * PSU_DDR_PHY_DX8SL0DQSCTL_LPIOPD 0x1 - Enables the PDR mode for DQ[7:0] - PSU_DDR_PHY_DX7GCR1_DXPDRMODE 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15 0x0 - Reserved. Returns zeroes on reads. - PSU_DDR_PHY_DX7GCR1_RESERVED_15 0x0 + * QS Counter Enable + * PSU_DDR_PHY_DX8SL0DQSCTL_QSCNTEN 0x1 - Select the delayed or non-delayed read data strobe # - PSU_DDR_PHY_DX7GCR1_QSNSEL 0x1 + * Unused DQ I/O Mode + * PSU_DDR_PHY_DX8SL0DQSCTL_UDQIOM 0x0 - Select the delayed or non-delayed read data strobe - PSU_DDR_PHY_DX7GCR1_QSSEL 0x1 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10 0x0 - Enables Read Data Strobe in a byte lane - PSU_DDR_PHY_DX7GCR1_OEEN 0x1 + * Data Slew Rate + * PSU_DDR_PHY_DX8SL0DQSCTL_DXSR 0x3 - Enables PDR in a byte lane - PSU_DDR_PHY_DX7GCR1_PDREN 0x1 + * DQS_N Resistor + * PSU_DDR_PHY_DX8SL0DQSCTL_DQSNRES 0x0 - Enables ODT/TE in a byte lane - PSU_DDR_PHY_DX7GCR1_TEEN 0x1 + * DQS Resistor + * PSU_DDR_PHY_DX8SL0DQSCTL_DQSRES 0x0 - Enables Write Data strobe in a byte lane - PSU_DDR_PHY_DX7GCR1_DSEN 0x1 + * DATX8 0-1 DQS Control Register + * (OFFSET, MASK, VALUE) (0XFD08141C, 0xFFFFFFFFU ,0x01264300U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL0DQSCTL_OFFSET, + 0xFFFFFFFFU, 0x01264300U); +/*##################################################################### */ - Enables DM pin in a byte lane - PSU_DDR_PHY_DX7GCR1_DMEN 0x1 + /* + * Register : DX8SL0DXCTL2 @ 0XFD08142C - Enables DQ corresponding to each bit in a byte - PSU_DDR_PHY_DX7GCR1_DQEN 0xff + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24 0x0 - DATX8 n General Configuration Register 1 - (OFFSET, MASK, VALUE) (0XFD080E04, 0xFFFFFFFFU ,0x00007FFFU) - RegMask = (DDR_PHY_DX7GCR1_DXPDRMODE_MASK | DDR_PHY_DX7GCR1_RESERVED_15_MASK | DDR_PHY_DX7GCR1_QSNSEL_MASK | DDR_PHY_DX7GCR1_QSSEL_MASK | DDR_PHY_DX7GCR1_OEEN_MASK | DDR_PHY_DX7GCR1_PDREN_MASK | DDR_PHY_DX7GCR1_TEEN_MASK | DDR_PHY_DX7GCR1_DSEN_MASK | DDR_PHY_DX7GCR1_DMEN_MASK | DDR_PHY_DX7GCR1_DQEN_MASK | 0 ); + * Configurable Read Data Enable + * PSU_DDR_PHY_DX8SL0DXCTL2_CRDEN 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX7GCR1_DXPDRMODE_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR1_RESERVED_15_SHIFT - | 0x00000001U << DDR_PHY_DX7GCR1_QSNSEL_SHIFT - | 0x00000001U << DDR_PHY_DX7GCR1_QSSEL_SHIFT - | 0x00000001U << DDR_PHY_DX7GCR1_OEEN_SHIFT - | 0x00000001U << DDR_PHY_DX7GCR1_PDREN_SHIFT - | 0x00000001U << DDR_PHY_DX7GCR1_TEEN_SHIFT - | 0x00000001U << DDR_PHY_DX7GCR1_DSEN_SHIFT - | 0x00000001U << DDR_PHY_DX7GCR1_DMEN_SHIFT - | 0x000000FFU << DDR_PHY_DX7GCR1_DQEN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX7GCR1_OFFSET ,0xFFFFFFFFU ,0x00007FFFU); - /*############################################################################################################################ */ + * OX Extension during Post-amble + * PSU_DDR_PHY_DX8SL0DXCTL2_POSOEX 0x0 - /*Register : DX7GCR4 @ 0XFD080E10

+ * OE Extension during Pre-amble + * PSU_DDR_PHY_DX8SL0DXCTL2_PREOEX 0x1 - Byte lane VREF IOM (Used only by D4MU IOs) - PSU_DDR_PHY_DX7GCR4_RESERVED_31_29 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_17 0x0 - Byte Lane VREF Pad Enable - PSU_DDR_PHY_DX7GCR4_DXREFPEN 0x0 + * I/O Assisted Gate Select + * PSU_DDR_PHY_DX8SL0DXCTL2_IOAG 0x0 - Byte Lane Internal VREF Enable - PSU_DDR_PHY_DX7GCR4_DXREFEEN 0x3 + * I/O Loopback Select + * PSU_DDR_PHY_DX8SL0DXCTL2_IOLB 0x0 - Byte Lane Single-End VREF Enable - PSU_DDR_PHY_DX7GCR4_DXREFSEN 0x1 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX7GCR4_RESERVED_24 0x0 + * Low Power Wakeup Threshold + * PSU_DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH 0xc - External VREF generator REFSEL range select - PSU_DDR_PHY_DX7GCR4_DXREFESELRANGE 0x0 + * Read Data Bus Inversion Enable + * PSU_DDR_PHY_DX8SL0DXCTL2_RDBI 0x0 - Byte Lane External VREF Select - PSU_DDR_PHY_DX7GCR4_DXREFESEL 0x0 + * Write Data Bus Inversion Enable + * PSU_DDR_PHY_DX8SL0DXCTL2_WDBI 0x0 - Single ended VREF generator REFSEL range select - PSU_DDR_PHY_DX7GCR4_DXREFSSELRANGE 0x1 + * PUB Read FIFO Bypass + * PSU_DDR_PHY_DX8SL0DXCTL2_PRFBYP 0x0 - Byte Lane Single-End VREF Select - PSU_DDR_PHY_DX7GCR4_DXREFSSEL 0x30 + * DATX8 Receive FIFO Read Mode + * PSU_DDR_PHY_DX8SL0DXCTL2_RDMODE 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX7GCR4_RESERVED_7_6 0x0 + * Disables the Read FIFO Reset + * PSU_DDR_PHY_DX8SL0DXCTL2_DISRST 0x0 - VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. - PSU_DDR_PHY_DX7GCR4_DXREFIEN 0xf + * Read DQS Gate I/O Loopback + * PSU_DDR_PHY_DX8SL0DXCTL2_DQSGLB 0x0 - VRMON control for DQ IO (Single Ended) buffers of a byte lane. - PSU_DDR_PHY_DX7GCR4_DXREFIMON 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_0 0x0 - DATX8 n General Configuration Register 4 - (OFFSET, MASK, VALUE) (0XFD080E10, 0xFFFFFFFFU ,0x0E00B03CU) - RegMask = (DDR_PHY_DX7GCR4_RESERVED_31_29_MASK | DDR_PHY_DX7GCR4_DXREFPEN_MASK | DDR_PHY_DX7GCR4_DXREFEEN_MASK | DDR_PHY_DX7GCR4_DXREFSEN_MASK | DDR_PHY_DX7GCR4_RESERVED_24_MASK | DDR_PHY_DX7GCR4_DXREFESELRANGE_MASK | DDR_PHY_DX7GCR4_DXREFESEL_MASK | DDR_PHY_DX7GCR4_DXREFSSELRANGE_MASK | DDR_PHY_DX7GCR4_DXREFSSEL_MASK | DDR_PHY_DX7GCR4_RESERVED_7_6_MASK | DDR_PHY_DX7GCR4_DXREFIEN_MASK | DDR_PHY_DX7GCR4_DXREFIMON_MASK | 0 ); + * DATX8 0-1 DX Control Register 2 + * (OFFSET, MASK, VALUE) (0XFD08142C, 0xFFFFFFFFU ,0x00041800U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL0DXCTL2_OFFSET, + 0xFFFFFFFFU, 0x00041800U); +/*##################################################################### */ - RegVal = ((0x00000000U << DDR_PHY_DX7GCR4_RESERVED_31_29_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR4_DXREFPEN_SHIFT - | 0x00000003U << DDR_PHY_DX7GCR4_DXREFEEN_SHIFT - | 0x00000001U << DDR_PHY_DX7GCR4_DXREFSEN_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR4_RESERVED_24_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR4_DXREFESELRANGE_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR4_DXREFESEL_SHIFT - | 0x00000001U << DDR_PHY_DX7GCR4_DXREFSSELRANGE_SHIFT - | 0x00000030U << DDR_PHY_DX7GCR4_DXREFSSEL_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR4_RESERVED_7_6_SHIFT - | 0x0000000FU << DDR_PHY_DX7GCR4_DXREFIEN_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR4_DXREFIMON_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX7GCR4_OFFSET ,0xFFFFFFFFU ,0x0E00B03CU); - /*############################################################################################################################ */ + /* + * Register : DX8SL0IOCR @ 0XFD081430 - /*Register : DX7GCR5 @ 0XFD080E14

+ * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL0IOCR_RESERVED_31 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX7GCR5_RESERVED_31 0x0 + * PVREF_DAC REFSEL range select + * PSU_DDR_PHY_DX8SL0IOCR_DXDACRANGE 0x7 - Byte Lane internal VREF Select for Rank 3 - PSU_DDR_PHY_DX7GCR5_DXREFISELR3 0x9 + * IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring + * PSU_DDR_PHY_DX8SL0IOCR_DXVREFIOM 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX7GCR5_RESERVED_23 0x0 + * DX IO Mode + * PSU_DDR_PHY_DX8SL0IOCR_DXIOM 0x2 - Byte Lane internal VREF Select for Rank 2 - PSU_DDR_PHY_DX7GCR5_DXREFISELR2 0x9 + * DX IO Transmitter Mode + * PSU_DDR_PHY_DX8SL0IOCR_DXTXM 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX7GCR5_RESERVED_15 0x0 + * DX IO Receiver Mode + * PSU_DDR_PHY_DX8SL0IOCR_DXRXM 0x0 - Byte Lane internal VREF Select for Rank 1 - PSU_DDR_PHY_DX7GCR5_DXREFISELR1 0x4f + * DATX8 0-1 I/O Configuration Register + * (OFFSET, MASK, VALUE) (0XFD081430, 0xFFFFFFFFU ,0x70800000U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL0IOCR_OFFSET, 0xFFFFFFFFU, 0x70800000U); +/*##################################################################### */ - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX7GCR5_RESERVED_7 0x0 + /* + * Register : DX8SL1OSC @ 0XFD081440 - Byte Lane internal VREF Select for Rank 0 - PSU_DDR_PHY_DX7GCR5_DXREFISELR0 0x4f + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL1OSC_RESERVED_31_30 0x0 - DATX8 n General Configuration Register 5 - (OFFSET, MASK, VALUE) (0XFD080E14, 0xFFFFFFFFU ,0x09094F4FU) - RegMask = (DDR_PHY_DX7GCR5_RESERVED_31_MASK | DDR_PHY_DX7GCR5_DXREFISELR3_MASK | DDR_PHY_DX7GCR5_RESERVED_23_MASK | DDR_PHY_DX7GCR5_DXREFISELR2_MASK | DDR_PHY_DX7GCR5_RESERVED_15_MASK | DDR_PHY_DX7GCR5_DXREFISELR1_MASK | DDR_PHY_DX7GCR5_RESERVED_7_MASK | DDR_PHY_DX7GCR5_DXREFISELR0_MASK | 0 ); + * Enable Clock Gating for DX ddr_clk + * PSU_DDR_PHY_DX8SL1OSC_GATEDXRDCLK 0x2 - RegVal = ((0x00000000U << DDR_PHY_DX7GCR5_RESERVED_31_SHIFT - | 0x00000009U << DDR_PHY_DX7GCR5_DXREFISELR3_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR5_RESERVED_23_SHIFT - | 0x00000009U << DDR_PHY_DX7GCR5_DXREFISELR2_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR5_RESERVED_15_SHIFT - | 0x0000004FU << DDR_PHY_DX7GCR5_DXREFISELR1_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR5_RESERVED_7_SHIFT - | 0x0000004FU << DDR_PHY_DX7GCR5_DXREFISELR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX7GCR5_OFFSET ,0xFFFFFFFFU ,0x09094F4FU); - /*############################################################################################################################ */ + * Enable Clock Gating for DX ctl_rd_clk + * PSU_DDR_PHY_DX8SL1OSC_GATEDXDDRCLK 0x2 - /*Register : DX7GCR6 @ 0XFD080E18

+ * Enable Clock Gating for DX ctl_clk + * PSU_DDR_PHY_DX8SL1OSC_GATEDXCTLCLK 0x2 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX7GCR6_RESERVED_31_30 0x0 + * Selects the level to which clocks will be stalled when clock gating is e + * nabled. + * PSU_DDR_PHY_DX8SL1OSC_CLKLEVEL 0x0 - DRAM DQ VREF Select for Rank3 - PSU_DDR_PHY_DX7GCR6_DXDQVREFR3 0x9 + * Loopback Mode + * PSU_DDR_PHY_DX8SL1OSC_LBMODE 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX7GCR6_RESERVED_23_22 0x0 + * Load GSDQS LCDL with 2x the calibrated GSDQSPRD value + * PSU_DDR_PHY_DX8SL1OSC_LBGSDQS 0x0 - DRAM DQ VREF Select for Rank2 - PSU_DDR_PHY_DX7GCR6_DXDQVREFR2 0x9 + * Loopback DQS Gating + * PSU_DDR_PHY_DX8SL1OSC_LBGDQS 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX7GCR6_RESERVED_15_14 0x0 + * Loopback DQS Shift + * PSU_DDR_PHY_DX8SL1OSC_LBDQSS 0x0 - DRAM DQ VREF Select for Rank1 - PSU_DDR_PHY_DX7GCR6_DXDQVREFR1 0x2b + * PHY High-Speed Reset + * PSU_DDR_PHY_DX8SL1OSC_PHYHRST 0x1 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX7GCR6_RESERVED_7_6 0x0 + * PHY FIFO Reset + * PSU_DDR_PHY_DX8SL1OSC_PHYFRST 0x1 - DRAM DQ VREF Select for Rank0 - PSU_DDR_PHY_DX7GCR6_DXDQVREFR0 0x2b + * Delay Line Test Start + * PSU_DDR_PHY_DX8SL1OSC_DLTST 0x0 - DATX8 n General Configuration Register 6 - (OFFSET, MASK, VALUE) (0XFD080E18, 0xFFFFFFFFU ,0x09092B2BU) - RegMask = (DDR_PHY_DX7GCR6_RESERVED_31_30_MASK | DDR_PHY_DX7GCR6_DXDQVREFR3_MASK | DDR_PHY_DX7GCR6_RESERVED_23_22_MASK | DDR_PHY_DX7GCR6_DXDQVREFR2_MASK | DDR_PHY_DX7GCR6_RESERVED_15_14_MASK | DDR_PHY_DX7GCR6_DXDQVREFR1_MASK | DDR_PHY_DX7GCR6_RESERVED_7_6_MASK | DDR_PHY_DX7GCR6_DXDQVREFR0_MASK | 0 ); + * Delay Line Test Mode + * PSU_DDR_PHY_DX8SL1OSC_DLTMODE 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX7GCR6_RESERVED_31_30_SHIFT - | 0x00000009U << DDR_PHY_DX7GCR6_DXDQVREFR3_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR6_RESERVED_23_22_SHIFT - | 0x00000009U << DDR_PHY_DX7GCR6_DXDQVREFR2_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR6_RESERVED_15_14_SHIFT - | 0x0000002BU << DDR_PHY_DX7GCR6_DXDQVREFR1_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR6_RESERVED_7_6_SHIFT - | 0x0000002BU << DDR_PHY_DX7GCR6_DXDQVREFR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX7GCR6_OFFSET ,0xFFFFFFFFU ,0x09092B2BU); - /*############################################################################################################################ */ + * Reserved. Caution, do not write to this register field. + * PSU_DDR_PHY_DX8SL1OSC_RESERVED_12_11 0x3 - /*Register : DX7LCDLR2 @ 0XFD080E88

+ * Oscillator Mode Write-Data Delay Line Select + * PSU_DDR_PHY_DX8SL1OSC_OSCWDDL 0x3 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX7LCDLR2_RESERVED_31_25 0x0 + * Reserved. Caution, do not write to this register field. + * PSU_DDR_PHY_DX8SL1OSC_RESERVED_8_7 0x3 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX7LCDLR2_RESERVED_24_16 0x0 + * Oscillator Mode Write-Leveling Delay Line Select + * PSU_DDR_PHY_DX8SL1OSC_OSCWDL 0x3 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX7LCDLR2_RESERVED_15_9 0x0 + * Oscillator Mode Division + * PSU_DDR_PHY_DX8SL1OSC_OSCDIV 0xf - Read DQS Gating Delay - PSU_DDR_PHY_DX7LCDLR2_DQSGD 0xa + * Oscillator Enable + * PSU_DDR_PHY_DX8SL1OSC_OSCEN 0x0 - DATX8 n Local Calibrated Delay Line Register 2 - (OFFSET, MASK, VALUE) (0XFD080E88, 0xFFFFFFFFU ,0x0000000AU) - RegMask = (DDR_PHY_DX7LCDLR2_RESERVED_31_25_MASK | DDR_PHY_DX7LCDLR2_RESERVED_24_16_MASK | DDR_PHY_DX7LCDLR2_RESERVED_15_9_MASK | DDR_PHY_DX7LCDLR2_DQSGD_MASK | 0 ); + * DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Lo + * opback, and Gated Clock Control Register + * (OFFSET, MASK, VALUE) (0XFD081440, 0xFFFFFFFFU ,0x2A019FFEU) + */ + PSU_Mask_Write(DDR_PHY_DX8SL1OSC_OFFSET, 0xFFFFFFFFU, 0x2A019FFEU); +/*##################################################################### */ - RegVal = ((0x00000000U << DDR_PHY_DX7LCDLR2_RESERVED_31_25_SHIFT - | 0x00000000U << DDR_PHY_DX7LCDLR2_RESERVED_24_16_SHIFT - | 0x00000000U << DDR_PHY_DX7LCDLR2_RESERVED_15_9_SHIFT - | 0x0000000AU << DDR_PHY_DX7LCDLR2_DQSGD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX7LCDLR2_OFFSET ,0xFFFFFFFFU ,0x0000000AU); - /*############################################################################################################################ */ + /* + * Register : DX8SL1PLLCR0 @ 0XFD081444 - /*Register : DX7GTR0 @ 0XFD080EC0

+ * PLL Bypass + * PSU_DDR_PHY_DX8SL1PLLCR0_PLLBYP 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX7GTR0_RESERVED_31_24 0x0 + * PLL Reset + * PSU_DDR_PHY_DX8SL1PLLCR0_PLLRST 0x0 - DQ Write Path Latency Pipeline - PSU_DDR_PHY_DX7GTR0_WDQSL 0x0 + * PLL Power Down + * PSU_DDR_PHY_DX8SL1PLLCR0_PLLPD 0x0 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX7GTR0_RESERVED_23_20 0x0 + * Reference Stop Mode + * PSU_DDR_PHY_DX8SL1PLLCR0_RSTOPM 0x0 - Write Leveling System Latency - PSU_DDR_PHY_DX7GTR0_WLSL 0x2 + * PLL Frequency Select + * PSU_DDR_PHY_DX8SL1PLLCR0_FRQSEL 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX7GTR0_RESERVED_15_13 0x0 + * Relock Mode + * PSU_DDR_PHY_DX8SL1PLLCR0_RLOCKM 0x0 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX7GTR0_RESERVED_12_8 0x0 + * Charge Pump Proportional Current Control + * PSU_DDR_PHY_DX8SL1PLLCR0_CPPC 0x8 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX7GTR0_RESERVED_7_5 0x0 + * Charge Pump Integrating Current Control + * PSU_DDR_PHY_DX8SL1PLLCR0_CPIC 0x0 - DQS Gating System Latency - PSU_DDR_PHY_DX7GTR0_DGSL 0x0 + * Gear Shift + * PSU_DDR_PHY_DX8SL1PLLCR0_GSHIFT 0x0 - DATX8 n General Timing Register 0 - (OFFSET, MASK, VALUE) (0XFD080EC0, 0xFFFFFFFFU ,0x00020000U) - RegMask = (DDR_PHY_DX7GTR0_RESERVED_31_24_MASK | DDR_PHY_DX7GTR0_WDQSL_MASK | DDR_PHY_DX7GTR0_RESERVED_23_20_MASK | DDR_PHY_DX7GTR0_WLSL_MASK | DDR_PHY_DX7GTR0_RESERVED_15_13_MASK | DDR_PHY_DX7GTR0_RESERVED_12_8_MASK | DDR_PHY_DX7GTR0_RESERVED_7_5_MASK | DDR_PHY_DX7GTR0_DGSL_MASK | 0 ); + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL1PLLCR0_RESERVED_11_9 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX7GTR0_RESERVED_31_24_SHIFT - | 0x00000000U << DDR_PHY_DX7GTR0_WDQSL_SHIFT - | 0x00000000U << DDR_PHY_DX7GTR0_RESERVED_23_20_SHIFT - | 0x00000002U << DDR_PHY_DX7GTR0_WLSL_SHIFT - | 0x00000000U << DDR_PHY_DX7GTR0_RESERVED_15_13_SHIFT - | 0x00000000U << DDR_PHY_DX7GTR0_RESERVED_12_8_SHIFT - | 0x00000000U << DDR_PHY_DX7GTR0_RESERVED_7_5_SHIFT - | 0x00000000U << DDR_PHY_DX7GTR0_DGSL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX7GTR0_OFFSET ,0xFFFFFFFFU ,0x00020000U); - /*############################################################################################################################ */ + * Analog Test Enable (ATOEN) + * PSU_DDR_PHY_DX8SL1PLLCR0_ATOEN 0x0 - /*Register : DX8GCR0 @ 0XFD080F00

+ * Analog Test Control + * PSU_DDR_PHY_DX8SL1PLLCR0_ATC 0x0 - Calibration Bypass - PSU_DDR_PHY_DX8GCR0_CALBYP 0x0 + * Digital Test Control + * PSU_DDR_PHY_DX8SL1PLLCR0_DTC 0x0 - Master Delay Line Enable - PSU_DDR_PHY_DX8GCR0_MDLEN 0x1 + * DAXT8 0-1 PLL Control Register 0 + * (OFFSET, MASK, VALUE) (0XFD081444, 0xFFFFFFFFU ,0x01100000U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL1PLLCR0_OFFSET, + 0xFFFFFFFFU, 0x01100000U); +/*##################################################################### */ - Configurable ODT(TE) Phase Shift - PSU_DDR_PHY_DX8GCR0_CODTSHFT 0x0 + /* + * Register : DX8SL1DQSCTL @ 0XFD08145C - DQS Duty Cycle Correction - PSU_DDR_PHY_DX8GCR0_DQSDCC 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25 0x0 - Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY - PSU_DDR_PHY_DX8GCR0_RDDLY 0x8 + * Read Path Rise-to-Rise Mode + * PSU_DDR_PHY_DX8SL1DQSCTL_RRRMODE 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8GCR0_RESERVED_19_14 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22 0x0 - DQSNSE Power Down Receiver - PSU_DDR_PHY_DX8GCR0_DQSNSEPDR 0x0 + * Write Path Rise-to-Rise Mode + * PSU_DDR_PHY_DX8SL1DQSCTL_WRRMODE 0x1 - DQSSE Power Down Receiver - PSU_DDR_PHY_DX8GCR0_DQSSEPDR 0x0 + * DQS Gate Extension + * PSU_DDR_PHY_DX8SL1DQSCTL_DQSGX 0x0 - RTT On Additive Latency - PSU_DDR_PHY_DX8GCR0_RTTOAL 0x0 + * Low Power PLL Power Down + * PSU_DDR_PHY_DX8SL1DQSCTL_LPPLLPD 0x1 - RTT Output Hold - PSU_DDR_PHY_DX8GCR0_RTTOH 0x3 + * Low Power I/O Power Down + * PSU_DDR_PHY_DX8SL1DQSCTL_LPIOPD 0x1 - Configurable PDR Phase Shift - PSU_DDR_PHY_DX8GCR0_CPDRSHFT 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15 0x0 - DQSR Power Down - PSU_DDR_PHY_DX8GCR0_DQSRPD 0x0 + * QS Counter Enable + * PSU_DDR_PHY_DX8SL1DQSCTL_QSCNTEN 0x1 - DQSG Power Down Receiver - PSU_DDR_PHY_DX8GCR0_DQSGPDR 0x1 + * Unused DQ I/O Mode + * PSU_DDR_PHY_DX8SL1DQSCTL_UDQIOM 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8GCR0_RESERVED_4 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10 0x0 - DQSG On-Die Termination - PSU_DDR_PHY_DX8GCR0_DQSGODT 0x0 + * Data Slew Rate + * PSU_DDR_PHY_DX8SL1DQSCTL_DXSR 0x3 - DQSG Output Enable - PSU_DDR_PHY_DX8GCR0_DQSGOE 0x1 + * DQS_N Resistor + * PSU_DDR_PHY_DX8SL1DQSCTL_DQSNRES 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8GCR0_RESERVED_1_0 0x0 + * DQS Resistor + * PSU_DDR_PHY_DX8SL1DQSCTL_DQSRES 0x0 - DATX8 n General Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD080F00, 0xFFFFFFFFU ,0x40800624U) - RegMask = (DDR_PHY_DX8GCR0_CALBYP_MASK | DDR_PHY_DX8GCR0_MDLEN_MASK | DDR_PHY_DX8GCR0_CODTSHFT_MASK | DDR_PHY_DX8GCR0_DQSDCC_MASK | DDR_PHY_DX8GCR0_RDDLY_MASK | DDR_PHY_DX8GCR0_RESERVED_19_14_MASK | DDR_PHY_DX8GCR0_DQSNSEPDR_MASK | DDR_PHY_DX8GCR0_DQSSEPDR_MASK | DDR_PHY_DX8GCR0_RTTOAL_MASK | DDR_PHY_DX8GCR0_RTTOH_MASK | DDR_PHY_DX8GCR0_CPDRSHFT_MASK | DDR_PHY_DX8GCR0_DQSRPD_MASK | DDR_PHY_DX8GCR0_DQSGPDR_MASK | DDR_PHY_DX8GCR0_RESERVED_4_MASK | DDR_PHY_DX8GCR0_DQSGODT_MASK | DDR_PHY_DX8GCR0_DQSGOE_MASK | DDR_PHY_DX8GCR0_RESERVED_1_0_MASK | 0 ); + * DATX8 0-1 DQS Control Register + * (OFFSET, MASK, VALUE) (0XFD08145C, 0xFFFFFFFFU ,0x01264300U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL1DQSCTL_OFFSET, + 0xFFFFFFFFU, 0x01264300U); +/*##################################################################### */ - RegVal = ((0x00000000U << DDR_PHY_DX8GCR0_CALBYP_SHIFT - | 0x00000001U << DDR_PHY_DX8GCR0_MDLEN_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR0_CODTSHFT_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR0_DQSDCC_SHIFT - | 0x00000008U << DDR_PHY_DX8GCR0_RDDLY_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR0_RESERVED_19_14_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR0_DQSNSEPDR_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR0_DQSSEPDR_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR0_RTTOAL_SHIFT - | 0x00000003U << DDR_PHY_DX8GCR0_RTTOH_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR0_CPDRSHFT_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR0_DQSRPD_SHIFT - | 0x00000001U << DDR_PHY_DX8GCR0_DQSGPDR_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR0_RESERVED_4_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR0_DQSGODT_SHIFT - | 0x00000001U << DDR_PHY_DX8GCR0_DQSGOE_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR0_RESERVED_1_0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8GCR0_OFFSET ,0xFFFFFFFFU ,0x40800624U); - /*############################################################################################################################ */ + /* + * Register : DX8SL1DXCTL2 @ 0XFD08146C - /*Register : DX8GCR1 @ 0XFD080F04

+ * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24 0x0 - Enables the PDR mode for DQ[7:0] - PSU_DDR_PHY_DX8GCR1_DXPDRMODE 0x0 + * Configurable Read Data Enable + * PSU_DDR_PHY_DX8SL1DXCTL2_CRDEN 0x0 - Reserved. Returns zeroes on reads. - PSU_DDR_PHY_DX8GCR1_RESERVED_15 0x0 + * OX Extension during Post-amble + * PSU_DDR_PHY_DX8SL1DXCTL2_POSOEX 0x0 - Select the delayed or non-delayed read data strobe # - PSU_DDR_PHY_DX8GCR1_QSNSEL 0x1 + * OE Extension during Pre-amble + * PSU_DDR_PHY_DX8SL1DXCTL2_PREOEX 0x1 - Select the delayed or non-delayed read data strobe - PSU_DDR_PHY_DX8GCR1_QSSEL 0x1 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_17 0x0 - Enables Read Data Strobe in a byte lane - PSU_DDR_PHY_DX8GCR1_OEEN 0x1 + * I/O Assisted Gate Select + * PSU_DDR_PHY_DX8SL1DXCTL2_IOAG 0x0 - Enables PDR in a byte lane - PSU_DDR_PHY_DX8GCR1_PDREN 0x1 + * I/O Loopback Select + * PSU_DDR_PHY_DX8SL1DXCTL2_IOLB 0x0 - Enables ODT/TE in a byte lane - PSU_DDR_PHY_DX8GCR1_TEEN 0x1 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13 0x0 - Enables Write Data strobe in a byte lane - PSU_DDR_PHY_DX8GCR1_DSEN 0x1 + * Low Power Wakeup Threshold + * PSU_DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH 0xc - Enables DM pin in a byte lane - PSU_DDR_PHY_DX8GCR1_DMEN 0x1 + * Read Data Bus Inversion Enable + * PSU_DDR_PHY_DX8SL1DXCTL2_RDBI 0x0 - Enables DQ corresponding to each bit in a byte - PSU_DDR_PHY_DX8GCR1_DQEN 0x0 + * Write Data Bus Inversion Enable + * PSU_DDR_PHY_DX8SL1DXCTL2_WDBI 0x0 - DATX8 n General Configuration Register 1 - (OFFSET, MASK, VALUE) (0XFD080F04, 0xFFFFFFFFU ,0x00007F00U) - RegMask = (DDR_PHY_DX8GCR1_DXPDRMODE_MASK | DDR_PHY_DX8GCR1_RESERVED_15_MASK | DDR_PHY_DX8GCR1_QSNSEL_MASK | DDR_PHY_DX8GCR1_QSSEL_MASK | DDR_PHY_DX8GCR1_OEEN_MASK | DDR_PHY_DX8GCR1_PDREN_MASK | DDR_PHY_DX8GCR1_TEEN_MASK | DDR_PHY_DX8GCR1_DSEN_MASK | DDR_PHY_DX8GCR1_DMEN_MASK | DDR_PHY_DX8GCR1_DQEN_MASK | 0 ); + * PUB Read FIFO Bypass + * PSU_DDR_PHY_DX8SL1DXCTL2_PRFBYP 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX8GCR1_DXPDRMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR1_RESERVED_15_SHIFT - | 0x00000001U << DDR_PHY_DX8GCR1_QSNSEL_SHIFT - | 0x00000001U << DDR_PHY_DX8GCR1_QSSEL_SHIFT - | 0x00000001U << DDR_PHY_DX8GCR1_OEEN_SHIFT - | 0x00000001U << DDR_PHY_DX8GCR1_PDREN_SHIFT - | 0x00000001U << DDR_PHY_DX8GCR1_TEEN_SHIFT - | 0x00000001U << DDR_PHY_DX8GCR1_DSEN_SHIFT - | 0x00000001U << DDR_PHY_DX8GCR1_DMEN_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR1_DQEN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8GCR1_OFFSET ,0xFFFFFFFFU ,0x00007F00U); - /*############################################################################################################################ */ + * DATX8 Receive FIFO Read Mode + * PSU_DDR_PHY_DX8SL1DXCTL2_RDMODE 0x0 - /*Register : DX8GCR4 @ 0XFD080F10

+ * Disables the Read FIFO Reset + * PSU_DDR_PHY_DX8SL1DXCTL2_DISRST 0x0 - Byte lane VREF IOM (Used only by D4MU IOs) - PSU_DDR_PHY_DX8GCR4_RESERVED_31_29 0x0 + * Read DQS Gate I/O Loopback + * PSU_DDR_PHY_DX8SL1DXCTL2_DQSGLB 0x0 - Byte Lane VREF Pad Enable - PSU_DDR_PHY_DX8GCR4_DXREFPEN 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_0 0x0 - Byte Lane Internal VREF Enable - PSU_DDR_PHY_DX8GCR4_DXREFEEN 0x3 + * DATX8 0-1 DX Control Register 2 + * (OFFSET, MASK, VALUE) (0XFD08146C, 0xFFFFFFFFU ,0x00041800U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL1DXCTL2_OFFSET, + 0xFFFFFFFFU, 0x00041800U); +/*##################################################################### */ - Byte Lane Single-End VREF Enable - PSU_DDR_PHY_DX8GCR4_DXREFSEN 0x1 + /* + * Register : DX8SL1IOCR @ 0XFD081470 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX8GCR4_RESERVED_24 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL1IOCR_RESERVED_31 0x0 - External VREF generator REFSEL range select - PSU_DDR_PHY_DX8GCR4_DXREFESELRANGE 0x0 + * PVREF_DAC REFSEL range select + * PSU_DDR_PHY_DX8SL1IOCR_DXDACRANGE 0x7 - Byte Lane External VREF Select - PSU_DDR_PHY_DX8GCR4_DXREFESEL 0x0 + * IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring + * PSU_DDR_PHY_DX8SL1IOCR_DXVREFIOM 0x0 - Single ended VREF generator REFSEL range select - PSU_DDR_PHY_DX8GCR4_DXREFSSELRANGE 0x1 + * DX IO Mode + * PSU_DDR_PHY_DX8SL1IOCR_DXIOM 0x2 - Byte Lane Single-End VREF Select - PSU_DDR_PHY_DX8GCR4_DXREFSSEL 0x30 + * DX IO Transmitter Mode + * PSU_DDR_PHY_DX8SL1IOCR_DXTXM 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX8GCR4_RESERVED_7_6 0x0 + * DX IO Receiver Mode + * PSU_DDR_PHY_DX8SL1IOCR_DXRXM 0x0 - VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. - PSU_DDR_PHY_DX8GCR4_DXREFIEN 0xf + * DATX8 0-1 I/O Configuration Register + * (OFFSET, MASK, VALUE) (0XFD081470, 0xFFFFFFFFU ,0x70800000U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL1IOCR_OFFSET, 0xFFFFFFFFU, 0x70800000U); +/*##################################################################### */ - VRMON control for DQ IO (Single Ended) buffers of a byte lane. - PSU_DDR_PHY_DX8GCR4_DXREFIMON 0x0 + /* + * Register : DX8SL2OSC @ 0XFD081480 - DATX8 n General Configuration Register 4 - (OFFSET, MASK, VALUE) (0XFD080F10, 0xFFFFFFFFU ,0x0E00B03CU) - RegMask = (DDR_PHY_DX8GCR4_RESERVED_31_29_MASK | DDR_PHY_DX8GCR4_DXREFPEN_MASK | DDR_PHY_DX8GCR4_DXREFEEN_MASK | DDR_PHY_DX8GCR4_DXREFSEN_MASK | DDR_PHY_DX8GCR4_RESERVED_24_MASK | DDR_PHY_DX8GCR4_DXREFESELRANGE_MASK | DDR_PHY_DX8GCR4_DXREFESEL_MASK | DDR_PHY_DX8GCR4_DXREFSSELRANGE_MASK | DDR_PHY_DX8GCR4_DXREFSSEL_MASK | DDR_PHY_DX8GCR4_RESERVED_7_6_MASK | DDR_PHY_DX8GCR4_DXREFIEN_MASK | DDR_PHY_DX8GCR4_DXREFIMON_MASK | 0 ); + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL2OSC_RESERVED_31_30 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX8GCR4_RESERVED_31_29_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR4_DXREFPEN_SHIFT - | 0x00000003U << DDR_PHY_DX8GCR4_DXREFEEN_SHIFT - | 0x00000001U << DDR_PHY_DX8GCR4_DXREFSEN_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR4_RESERVED_24_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR4_DXREFESELRANGE_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR4_DXREFESEL_SHIFT - | 0x00000001U << DDR_PHY_DX8GCR4_DXREFSSELRANGE_SHIFT - | 0x00000030U << DDR_PHY_DX8GCR4_DXREFSSEL_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR4_RESERVED_7_6_SHIFT - | 0x0000000FU << DDR_PHY_DX8GCR4_DXREFIEN_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR4_DXREFIMON_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8GCR4_OFFSET ,0xFFFFFFFFU ,0x0E00B03CU); - /*############################################################################################################################ */ + * Enable Clock Gating for DX ddr_clk + * PSU_DDR_PHY_DX8SL2OSC_GATEDXRDCLK 0x2 - /*Register : DX8GCR5 @ 0XFD080F14

+ * Enable Clock Gating for DX ctl_rd_clk + * PSU_DDR_PHY_DX8SL2OSC_GATEDXDDRCLK 0x2 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX8GCR5_RESERVED_31 0x0 + * Enable Clock Gating for DX ctl_clk + * PSU_DDR_PHY_DX8SL2OSC_GATEDXCTLCLK 0x2 - Byte Lane internal VREF Select for Rank 3 - PSU_DDR_PHY_DX8GCR5_DXREFISELR3 0x9 + * Selects the level to which clocks will be stalled when clock gating is e + * nabled. + * PSU_DDR_PHY_DX8SL2OSC_CLKLEVEL 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX8GCR5_RESERVED_23 0x0 + * Loopback Mode + * PSU_DDR_PHY_DX8SL2OSC_LBMODE 0x0 - Byte Lane internal VREF Select for Rank 2 - PSU_DDR_PHY_DX8GCR5_DXREFISELR2 0x9 + * Load GSDQS LCDL with 2x the calibrated GSDQSPRD value + * PSU_DDR_PHY_DX8SL2OSC_LBGSDQS 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX8GCR5_RESERVED_15 0x0 + * Loopback DQS Gating + * PSU_DDR_PHY_DX8SL2OSC_LBGDQS 0x0 - Byte Lane internal VREF Select for Rank 1 - PSU_DDR_PHY_DX8GCR5_DXREFISELR1 0x4f + * Loopback DQS Shift + * PSU_DDR_PHY_DX8SL2OSC_LBDQSS 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX8GCR5_RESERVED_7 0x0 + * PHY High-Speed Reset + * PSU_DDR_PHY_DX8SL2OSC_PHYHRST 0x1 - Byte Lane internal VREF Select for Rank 0 - PSU_DDR_PHY_DX8GCR5_DXREFISELR0 0x4f + * PHY FIFO Reset + * PSU_DDR_PHY_DX8SL2OSC_PHYFRST 0x1 - DATX8 n General Configuration Register 5 - (OFFSET, MASK, VALUE) (0XFD080F14, 0xFFFFFFFFU ,0x09094F4FU) - RegMask = (DDR_PHY_DX8GCR5_RESERVED_31_MASK | DDR_PHY_DX8GCR5_DXREFISELR3_MASK | DDR_PHY_DX8GCR5_RESERVED_23_MASK | DDR_PHY_DX8GCR5_DXREFISELR2_MASK | DDR_PHY_DX8GCR5_RESERVED_15_MASK | DDR_PHY_DX8GCR5_DXREFISELR1_MASK | DDR_PHY_DX8GCR5_RESERVED_7_MASK | DDR_PHY_DX8GCR5_DXREFISELR0_MASK | 0 ); + * Delay Line Test Start + * PSU_DDR_PHY_DX8SL2OSC_DLTST 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX8GCR5_RESERVED_31_SHIFT - | 0x00000009U << DDR_PHY_DX8GCR5_DXREFISELR3_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR5_RESERVED_23_SHIFT - | 0x00000009U << DDR_PHY_DX8GCR5_DXREFISELR2_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR5_RESERVED_15_SHIFT - | 0x0000004FU << DDR_PHY_DX8GCR5_DXREFISELR1_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR5_RESERVED_7_SHIFT - | 0x0000004FU << DDR_PHY_DX8GCR5_DXREFISELR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8GCR5_OFFSET ,0xFFFFFFFFU ,0x09094F4FU); - /*############################################################################################################################ */ + * Delay Line Test Mode + * PSU_DDR_PHY_DX8SL2OSC_DLTMODE 0x0 - /*Register : DX8GCR6 @ 0XFD080F18

+ * Reserved. Caution, do not write to this register field. + * PSU_DDR_PHY_DX8SL2OSC_RESERVED_12_11 0x3 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX8GCR6_RESERVED_31_30 0x0 + * Oscillator Mode Write-Data Delay Line Select + * PSU_DDR_PHY_DX8SL2OSC_OSCWDDL 0x3 - DRAM DQ VREF Select for Rank3 - PSU_DDR_PHY_DX8GCR6_DXDQVREFR3 0x9 + * Reserved. Caution, do not write to this register field. + * PSU_DDR_PHY_DX8SL2OSC_RESERVED_8_7 0x3 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX8GCR6_RESERVED_23_22 0x0 + * Oscillator Mode Write-Leveling Delay Line Select + * PSU_DDR_PHY_DX8SL2OSC_OSCWDL 0x3 - DRAM DQ VREF Select for Rank2 - PSU_DDR_PHY_DX8GCR6_DXDQVREFR2 0x9 + * Oscillator Mode Division + * PSU_DDR_PHY_DX8SL2OSC_OSCDIV 0xf - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX8GCR6_RESERVED_15_14 0x0 + * Oscillator Enable + * PSU_DDR_PHY_DX8SL2OSC_OSCEN 0x0 - DRAM DQ VREF Select for Rank1 - PSU_DDR_PHY_DX8GCR6_DXDQVREFR1 0x2b + * DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Lo + * opback, and Gated Clock Control Register + * (OFFSET, MASK, VALUE) (0XFD081480, 0xFFFFFFFFU ,0x2A019FFEU) + */ + PSU_Mask_Write(DDR_PHY_DX8SL2OSC_OFFSET, 0xFFFFFFFFU, 0x2A019FFEU); +/*##################################################################### */ - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX8GCR6_RESERVED_7_6 0x0 + /* + * Register : DX8SL2PLLCR0 @ 0XFD081484 - DRAM DQ VREF Select for Rank0 - PSU_DDR_PHY_DX8GCR6_DXDQVREFR0 0x2b + * PLL Bypass + * PSU_DDR_PHY_DX8SL2PLLCR0_PLLBYP 0x0 - DATX8 n General Configuration Register 6 - (OFFSET, MASK, VALUE) (0XFD080F18, 0xFFFFFFFFU ,0x09092B2BU) - RegMask = (DDR_PHY_DX8GCR6_RESERVED_31_30_MASK | DDR_PHY_DX8GCR6_DXDQVREFR3_MASK | DDR_PHY_DX8GCR6_RESERVED_23_22_MASK | DDR_PHY_DX8GCR6_DXDQVREFR2_MASK | DDR_PHY_DX8GCR6_RESERVED_15_14_MASK | DDR_PHY_DX8GCR6_DXDQVREFR1_MASK | DDR_PHY_DX8GCR6_RESERVED_7_6_MASK | DDR_PHY_DX8GCR6_DXDQVREFR0_MASK | 0 ); + * PLL Reset + * PSU_DDR_PHY_DX8SL2PLLCR0_PLLRST 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX8GCR6_RESERVED_31_30_SHIFT - | 0x00000009U << DDR_PHY_DX8GCR6_DXDQVREFR3_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR6_RESERVED_23_22_SHIFT - | 0x00000009U << DDR_PHY_DX8GCR6_DXDQVREFR2_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR6_RESERVED_15_14_SHIFT - | 0x0000002BU << DDR_PHY_DX8GCR6_DXDQVREFR1_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR6_RESERVED_7_6_SHIFT - | 0x0000002BU << DDR_PHY_DX8GCR6_DXDQVREFR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8GCR6_OFFSET ,0xFFFFFFFFU ,0x09092B2BU); - /*############################################################################################################################ */ + * PLL Power Down + * PSU_DDR_PHY_DX8SL2PLLCR0_PLLPD 0x0 - /*Register : DX8LCDLR2 @ 0XFD080F88

+ * Reference Stop Mode + * PSU_DDR_PHY_DX8SL2PLLCR0_RSTOPM 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8LCDLR2_RESERVED_31_25 0x0 + * PLL Frequency Select + * PSU_DDR_PHY_DX8SL2PLLCR0_FRQSEL 0x1 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX8LCDLR2_RESERVED_24_16 0x0 + * Relock Mode + * PSU_DDR_PHY_DX8SL2PLLCR0_RLOCKM 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8LCDLR2_RESERVED_15_9 0x0 + * Charge Pump Proportional Current Control + * PSU_DDR_PHY_DX8SL2PLLCR0_CPPC 0x8 - Read DQS Gating Delay - PSU_DDR_PHY_DX8LCDLR2_DQSGD 0x0 + * Charge Pump Integrating Current Control + * PSU_DDR_PHY_DX8SL2PLLCR0_CPIC 0x0 - DATX8 n Local Calibrated Delay Line Register 2 - (OFFSET, MASK, VALUE) (0XFD080F88, 0xFFFFFFFFU ,0x00000000U) - RegMask = (DDR_PHY_DX8LCDLR2_RESERVED_31_25_MASK | DDR_PHY_DX8LCDLR2_RESERVED_24_16_MASK | DDR_PHY_DX8LCDLR2_RESERVED_15_9_MASK | DDR_PHY_DX8LCDLR2_DQSGD_MASK | 0 ); + * Gear Shift + * PSU_DDR_PHY_DX8SL2PLLCR0_GSHIFT 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX8LCDLR2_RESERVED_31_25_SHIFT - | 0x00000000U << DDR_PHY_DX8LCDLR2_RESERVED_24_16_SHIFT - | 0x00000000U << DDR_PHY_DX8LCDLR2_RESERVED_15_9_SHIFT - | 0x00000000U << DDR_PHY_DX8LCDLR2_DQSGD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8LCDLR2_OFFSET ,0xFFFFFFFFU ,0x00000000U); - /*############################################################################################################################ */ + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL2PLLCR0_RESERVED_11_9 0x0 - /*Register : DX8GTR0 @ 0XFD080FC0

+ * Analog Test Enable (ATOEN) + * PSU_DDR_PHY_DX8SL2PLLCR0_ATOEN 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8GTR0_RESERVED_31_24 0x0 + * Analog Test Control + * PSU_DDR_PHY_DX8SL2PLLCR0_ATC 0x0 - DQ Write Path Latency Pipeline - PSU_DDR_PHY_DX8GTR0_WDQSL 0x0 + * Digital Test Control + * PSU_DDR_PHY_DX8SL2PLLCR0_DTC 0x0 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX8GTR0_RESERVED_23_20 0x0 + * DAXT8 0-1 PLL Control Register 0 + * (OFFSET, MASK, VALUE) (0XFD081484, 0xFFFFFFFFU ,0x01100000U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL2PLLCR0_OFFSET, + 0xFFFFFFFFU, 0x01100000U); +/*##################################################################### */ - Write Leveling System Latency - PSU_DDR_PHY_DX8GTR0_WLSL 0x2 + /* + * Register : DX8SL2DQSCTL @ 0XFD08149C - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8GTR0_RESERVED_15_13 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25 0x0 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX8GTR0_RESERVED_12_8 0x0 + * Read Path Rise-to-Rise Mode + * PSU_DDR_PHY_DX8SL2DQSCTL_RRRMODE 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8GTR0_RESERVED_7_5 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22 0x0 - DQS Gating System Latency - PSU_DDR_PHY_DX8GTR0_DGSL 0x0 + * Write Path Rise-to-Rise Mode + * PSU_DDR_PHY_DX8SL2DQSCTL_WRRMODE 0x1 - DATX8 n General Timing Register 0 - (OFFSET, MASK, VALUE) (0XFD080FC0, 0xFFFFFFFFU ,0x00020000U) - RegMask = (DDR_PHY_DX8GTR0_RESERVED_31_24_MASK | DDR_PHY_DX8GTR0_WDQSL_MASK | DDR_PHY_DX8GTR0_RESERVED_23_20_MASK | DDR_PHY_DX8GTR0_WLSL_MASK | DDR_PHY_DX8GTR0_RESERVED_15_13_MASK | DDR_PHY_DX8GTR0_RESERVED_12_8_MASK | DDR_PHY_DX8GTR0_RESERVED_7_5_MASK | DDR_PHY_DX8GTR0_DGSL_MASK | 0 ); + * DQS Gate Extension + * PSU_DDR_PHY_DX8SL2DQSCTL_DQSGX 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX8GTR0_RESERVED_31_24_SHIFT - | 0x00000000U << DDR_PHY_DX8GTR0_WDQSL_SHIFT - | 0x00000000U << DDR_PHY_DX8GTR0_RESERVED_23_20_SHIFT - | 0x00000002U << DDR_PHY_DX8GTR0_WLSL_SHIFT - | 0x00000000U << DDR_PHY_DX8GTR0_RESERVED_15_13_SHIFT - | 0x00000000U << DDR_PHY_DX8GTR0_RESERVED_12_8_SHIFT - | 0x00000000U << DDR_PHY_DX8GTR0_RESERVED_7_5_SHIFT - | 0x00000000U << DDR_PHY_DX8GTR0_DGSL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8GTR0_OFFSET ,0xFFFFFFFFU ,0x00020000U); - /*############################################################################################################################ */ + * Low Power PLL Power Down + * PSU_DDR_PHY_DX8SL2DQSCTL_LPPLLPD 0x1 - /*Register : DX8SL0OSC @ 0XFD081400

+ * Low Power I/O Power Down + * PSU_DDR_PHY_DX8SL2DQSCTL_LPIOPD 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL0OSC_RESERVED_31_30 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15 0x0 - Enable Clock Gating for DX ddr_clk - PSU_DDR_PHY_DX8SL0OSC_GATEDXRDCLK 0x2 + * QS Counter Enable + * PSU_DDR_PHY_DX8SL2DQSCTL_QSCNTEN 0x1 - Enable Clock Gating for DX ctl_rd_clk - PSU_DDR_PHY_DX8SL0OSC_GATEDXDDRCLK 0x2 + * Unused DQ I/O Mode + * PSU_DDR_PHY_DX8SL2DQSCTL_UDQIOM 0x0 - Enable Clock Gating for DX ctl_clk - PSU_DDR_PHY_DX8SL0OSC_GATEDXCTLCLK 0x2 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10 0x0 - Selects the level to which clocks will be stalled when clock gating is enabled. - PSU_DDR_PHY_DX8SL0OSC_CLKLEVEL 0x0 + * Data Slew Rate + * PSU_DDR_PHY_DX8SL2DQSCTL_DXSR 0x3 - Loopback Mode - PSU_DDR_PHY_DX8SL0OSC_LBMODE 0x0 + * DQS_N Resistor + * PSU_DDR_PHY_DX8SL2DQSCTL_DQSNRES 0x0 - Load GSDQS LCDL with 2x the calibrated GSDQSPRD value - PSU_DDR_PHY_DX8SL0OSC_LBGSDQS 0x0 + * DQS Resistor + * PSU_DDR_PHY_DX8SL2DQSCTL_DQSRES 0x0 - Loopback DQS Gating - PSU_DDR_PHY_DX8SL0OSC_LBGDQS 0x0 + * DATX8 0-1 DQS Control Register + * (OFFSET, MASK, VALUE) (0XFD08149C, 0xFFFFFFFFU ,0x01264300U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL2DQSCTL_OFFSET, + 0xFFFFFFFFU, 0x01264300U); +/*##################################################################### */ - Loopback DQS Shift - PSU_DDR_PHY_DX8SL0OSC_LBDQSS 0x0 + /* + * Register : DX8SL2DXCTL2 @ 0XFD0814AC - PHY High-Speed Reset - PSU_DDR_PHY_DX8SL0OSC_PHYHRST 0x1 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24 0x0 - PHY FIFO Reset - PSU_DDR_PHY_DX8SL0OSC_PHYFRST 0x1 + * Configurable Read Data Enable + * PSU_DDR_PHY_DX8SL2DXCTL2_CRDEN 0x0 - Delay Line Test Start - PSU_DDR_PHY_DX8SL0OSC_DLTST 0x0 + * OX Extension during Post-amble + * PSU_DDR_PHY_DX8SL2DXCTL2_POSOEX 0x0 - Delay Line Test Mode - PSU_DDR_PHY_DX8SL0OSC_DLTMODE 0x0 + * OE Extension during Pre-amble + * PSU_DDR_PHY_DX8SL2DXCTL2_PREOEX 0x1 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX8SL0OSC_RESERVED_12_11 0x3 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_17 0x0 - Oscillator Mode Write-Data Delay Line Select - PSU_DDR_PHY_DX8SL0OSC_OSCWDDL 0x3 + * I/O Assisted Gate Select + * PSU_DDR_PHY_DX8SL2DXCTL2_IOAG 0x0 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX8SL0OSC_RESERVED_8_7 0x3 + * I/O Loopback Select + * PSU_DDR_PHY_DX8SL2DXCTL2_IOLB 0x0 - Oscillator Mode Write-Leveling Delay Line Select - PSU_DDR_PHY_DX8SL0OSC_OSCWDL 0x3 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13 0x0 - Oscillator Mode Division - PSU_DDR_PHY_DX8SL0OSC_OSCDIV 0xf + * Low Power Wakeup Threshold + * PSU_DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH 0xc - Oscillator Enable - PSU_DDR_PHY_DX8SL0OSC_OSCEN 0x0 + * Read Data Bus Inversion Enable + * PSU_DDR_PHY_DX8SL2DXCTL2_RDBI 0x0 - DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register - (OFFSET, MASK, VALUE) (0XFD081400, 0xFFFFFFFFU ,0x2A019FFEU) - RegMask = (DDR_PHY_DX8SL0OSC_RESERVED_31_30_MASK | DDR_PHY_DX8SL0OSC_GATEDXRDCLK_MASK | DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_MASK | DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_MASK | DDR_PHY_DX8SL0OSC_CLKLEVEL_MASK | DDR_PHY_DX8SL0OSC_LBMODE_MASK | DDR_PHY_DX8SL0OSC_LBGSDQS_MASK | DDR_PHY_DX8SL0OSC_LBGDQS_MASK | DDR_PHY_DX8SL0OSC_LBDQSS_MASK | DDR_PHY_DX8SL0OSC_PHYHRST_MASK | DDR_PHY_DX8SL0OSC_PHYFRST_MASK | DDR_PHY_DX8SL0OSC_DLTST_MASK | DDR_PHY_DX8SL0OSC_DLTMODE_MASK | DDR_PHY_DX8SL0OSC_RESERVED_12_11_MASK | DDR_PHY_DX8SL0OSC_OSCWDDL_MASK | DDR_PHY_DX8SL0OSC_RESERVED_8_7_MASK | DDR_PHY_DX8SL0OSC_OSCWDL_MASK | DDR_PHY_DX8SL0OSC_OSCDIV_MASK | DDR_PHY_DX8SL0OSC_OSCEN_MASK | 0 ); + * Write Data Bus Inversion Enable + * PSU_DDR_PHY_DX8SL2DXCTL2_WDBI 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX8SL0OSC_RESERVED_31_30_SHIFT - | 0x00000002U << DDR_PHY_DX8SL0OSC_GATEDXRDCLK_SHIFT - | 0x00000002U << DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_SHIFT - | 0x00000002U << DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0OSC_CLKLEVEL_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0OSC_LBMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0OSC_LBGSDQS_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0OSC_LBGDQS_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0OSC_LBDQSS_SHIFT - | 0x00000001U << DDR_PHY_DX8SL0OSC_PHYHRST_SHIFT - | 0x00000001U << DDR_PHY_DX8SL0OSC_PHYFRST_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0OSC_DLTST_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0OSC_DLTMODE_SHIFT - | 0x00000003U << DDR_PHY_DX8SL0OSC_RESERVED_12_11_SHIFT - | 0x00000003U << DDR_PHY_DX8SL0OSC_OSCWDDL_SHIFT - | 0x00000003U << DDR_PHY_DX8SL0OSC_RESERVED_8_7_SHIFT - | 0x00000003U << DDR_PHY_DX8SL0OSC_OSCWDL_SHIFT - | 0x0000000FU << DDR_PHY_DX8SL0OSC_OSCDIV_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0OSC_OSCEN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8SL0OSC_OFFSET ,0xFFFFFFFFU ,0x2A019FFEU); - /*############################################################################################################################ */ + * PUB Read FIFO Bypass + * PSU_DDR_PHY_DX8SL2DXCTL2_PRFBYP 0x0 - /*Register : DX8SL0DQSCTL @ 0XFD08141C

+ * DATX8 Receive FIFO Read Mode + * PSU_DDR_PHY_DX8SL2DXCTL2_RDMODE 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25 0x0 + * Disables the Read FIFO Reset + * PSU_DDR_PHY_DX8SL2DXCTL2_DISRST 0x0 - Read Path Rise-to-Rise Mode - PSU_DDR_PHY_DX8SL0DQSCTL_RRRMODE 0x1 + * Read DQS Gate I/O Loopback + * PSU_DDR_PHY_DX8SL2DXCTL2_DQSGLB 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_0 0x0 - Write Path Rise-to-Rise Mode - PSU_DDR_PHY_DX8SL0DQSCTL_WRRMODE 0x1 + * DATX8 0-1 DX Control Register 2 + * (OFFSET, MASK, VALUE) (0XFD0814AC, 0xFFFFFFFFU ,0x00041800U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL2DXCTL2_OFFSET, + 0xFFFFFFFFU, 0x00041800U); +/*##################################################################### */ - DQS Gate Extension - PSU_DDR_PHY_DX8SL0DQSCTL_DQSGX 0x0 + /* + * Register : DX8SL2IOCR @ 0XFD0814B0 - Low Power PLL Power Down - PSU_DDR_PHY_DX8SL0DQSCTL_LPPLLPD 0x1 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL2IOCR_RESERVED_31 0x0 - Low Power I/O Power Down - PSU_DDR_PHY_DX8SL0DQSCTL_LPIOPD 0x1 + * PVREF_DAC REFSEL range select + * PSU_DDR_PHY_DX8SL2IOCR_DXDACRANGE 0x7 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15 0x0 + * IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring + * PSU_DDR_PHY_DX8SL2IOCR_DXVREFIOM 0x0 - QS Counter Enable - PSU_DDR_PHY_DX8SL0DQSCTL_QSCNTEN 0x1 + * DX IO Mode + * PSU_DDR_PHY_DX8SL2IOCR_DXIOM 0x2 - Unused DQ I/O Mode - PSU_DDR_PHY_DX8SL0DQSCTL_UDQIOM 0x0 + * DX IO Transmitter Mode + * PSU_DDR_PHY_DX8SL2IOCR_DXTXM 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10 0x0 + * DX IO Receiver Mode + * PSU_DDR_PHY_DX8SL2IOCR_DXRXM 0x0 - Data Slew Rate - PSU_DDR_PHY_DX8SL0DQSCTL_DXSR 0x3 - - DQS_N Resistor - PSU_DDR_PHY_DX8SL0DQSCTL_DQSNRES 0x0 - - DQS Resistor - PSU_DDR_PHY_DX8SL0DQSCTL_DQSRES 0x0 - - DATX8 0-1 DQS Control Register - (OFFSET, MASK, VALUE) (0XFD08141C, 0xFFFFFFFFU ,0x01264300U) - RegMask = (DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_MASK | DDR_PHY_DX8SL0DQSCTL_RRRMODE_MASK | DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_MASK | DDR_PHY_DX8SL0DQSCTL_WRRMODE_MASK | DDR_PHY_DX8SL0DQSCTL_DQSGX_MASK | DDR_PHY_DX8SL0DQSCTL_LPPLLPD_MASK | DDR_PHY_DX8SL0DQSCTL_LPIOPD_MASK | DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_MASK | DDR_PHY_DX8SL0DQSCTL_QSCNTEN_MASK | DDR_PHY_DX8SL0DQSCTL_UDQIOM_MASK | DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_MASK | DDR_PHY_DX8SL0DQSCTL_DXSR_MASK | DDR_PHY_DX8SL0DQSCTL_DQSNRES_MASK | DDR_PHY_DX8SL0DQSCTL_DQSRES_MASK | 0 ); + * DATX8 0-1 I/O Configuration Register + * (OFFSET, MASK, VALUE) (0XFD0814B0, 0xFFFFFFFFU ,0x70800000U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL2IOCR_OFFSET, 0xFFFFFFFFU, 0x70800000U); +/*##################################################################### */ - RegVal = ((0x00000000U << DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_SHIFT - | 0x00000001U << DDR_PHY_DX8SL0DQSCTL_RRRMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_SHIFT - | 0x00000001U << DDR_PHY_DX8SL0DQSCTL_WRRMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0DQSCTL_DQSGX_SHIFT - | 0x00000001U << DDR_PHY_DX8SL0DQSCTL_LPPLLPD_SHIFT - | 0x00000001U << DDR_PHY_DX8SL0DQSCTL_LPIOPD_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_SHIFT - | 0x00000001U << DDR_PHY_DX8SL0DQSCTL_QSCNTEN_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0DQSCTL_UDQIOM_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_SHIFT - | 0x00000003U << DDR_PHY_DX8SL0DQSCTL_DXSR_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0DQSCTL_DQSNRES_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0DQSCTL_DQSRES_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8SL0DQSCTL_OFFSET ,0xFFFFFFFFU ,0x01264300U); - /*############################################################################################################################ */ - - /*Register : DX8SL0DXCTL2 @ 0XFD08142C

- - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24 0x0 - - Configurable Read Data Enable - PSU_DDR_PHY_DX8SL0DXCTL2_CRDEN 0x0 - - OX Extension during Post-amble - PSU_DDR_PHY_DX8SL0DXCTL2_POSOEX 0x0 - - OE Extension during Pre-amble - PSU_DDR_PHY_DX8SL0DXCTL2_PREOEX 0x1 - - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_17 0x0 - - I/O Assisted Gate Select - PSU_DDR_PHY_DX8SL0DXCTL2_IOAG 0x0 + /* + * Register : DX8SL3OSC @ 0XFD0814C0 - I/O Loopback Select - PSU_DDR_PHY_DX8SL0DXCTL2_IOLB 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL3OSC_RESERVED_31_30 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13 0x0 + * Enable Clock Gating for DX ddr_clk + * PSU_DDR_PHY_DX8SL3OSC_GATEDXRDCLK 0x2 - Low Power Wakeup Threshold - PSU_DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH 0xc + * Enable Clock Gating for DX ctl_rd_clk + * PSU_DDR_PHY_DX8SL3OSC_GATEDXDDRCLK 0x2 - Read Data Bus Inversion Enable - PSU_DDR_PHY_DX8SL0DXCTL2_RDBI 0x0 + * Enable Clock Gating for DX ctl_clk + * PSU_DDR_PHY_DX8SL3OSC_GATEDXCTLCLK 0x2 - Write Data Bus Inversion Enable - PSU_DDR_PHY_DX8SL0DXCTL2_WDBI 0x0 + * Selects the level to which clocks will be stalled when clock gating is e + * nabled. + * PSU_DDR_PHY_DX8SL3OSC_CLKLEVEL 0x0 - PUB Read FIFO Bypass - PSU_DDR_PHY_DX8SL0DXCTL2_PRFBYP 0x0 + * Loopback Mode + * PSU_DDR_PHY_DX8SL3OSC_LBMODE 0x0 - DATX8 Receive FIFO Read Mode - PSU_DDR_PHY_DX8SL0DXCTL2_RDMODE 0x0 + * Load GSDQS LCDL with 2x the calibrated GSDQSPRD value + * PSU_DDR_PHY_DX8SL3OSC_LBGSDQS 0x0 - Disables the Read FIFO Reset - PSU_DDR_PHY_DX8SL0DXCTL2_DISRST 0x0 + * Loopback DQS Gating + * PSU_DDR_PHY_DX8SL3OSC_LBGDQS 0x0 - Read DQS Gate I/O Loopback - PSU_DDR_PHY_DX8SL0DXCTL2_DQSGLB 0x0 + * Loopback DQS Shift + * PSU_DDR_PHY_DX8SL3OSC_LBDQSS 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_0 0x0 + * PHY High-Speed Reset + * PSU_DDR_PHY_DX8SL3OSC_PHYHRST 0x1 - DATX8 0-1 DX Control Register 2 - (OFFSET, MASK, VALUE) (0XFD08142C, 0xFFFFFFFFU ,0x00041800U) - RegMask = (DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_MASK | DDR_PHY_DX8SL0DXCTL2_CRDEN_MASK | DDR_PHY_DX8SL0DXCTL2_POSOEX_MASK | DDR_PHY_DX8SL0DXCTL2_PREOEX_MASK | DDR_PHY_DX8SL0DXCTL2_RESERVED_17_MASK | DDR_PHY_DX8SL0DXCTL2_IOAG_MASK | DDR_PHY_DX8SL0DXCTL2_IOLB_MASK | DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_MASK | DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_MASK | DDR_PHY_DX8SL0DXCTL2_RDBI_MASK | DDR_PHY_DX8SL0DXCTL2_WDBI_MASK | DDR_PHY_DX8SL0DXCTL2_PRFBYP_MASK | DDR_PHY_DX8SL0DXCTL2_RDMODE_MASK | DDR_PHY_DX8SL0DXCTL2_DISRST_MASK | DDR_PHY_DX8SL0DXCTL2_DQSGLB_MASK | DDR_PHY_DX8SL0DXCTL2_RESERVED_0_MASK | 0 ); + * PHY FIFO Reset + * PSU_DDR_PHY_DX8SL3OSC_PHYFRST 0x1 - RegVal = ((0x00000000U << DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_CRDEN_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_POSOEX_SHIFT - | 0x00000001U << DDR_PHY_DX8SL0DXCTL2_PREOEX_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_RESERVED_17_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_IOAG_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_IOLB_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_SHIFT - | 0x0000000CU << DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_RDBI_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_WDBI_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_PRFBYP_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_RDMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_DISRST_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_DQSGLB_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_RESERVED_0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8SL0DXCTL2_OFFSET ,0xFFFFFFFFU ,0x00041800U); - /*############################################################################################################################ */ + * Delay Line Test Start + * PSU_DDR_PHY_DX8SL3OSC_DLTST 0x0 - /*Register : DX8SL0IOCR @ 0XFD081430

+ * Delay Line Test Mode + * PSU_DDR_PHY_DX8SL3OSC_DLTMODE 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL0IOCR_RESERVED_31 0x0 + * Reserved. Caution, do not write to this register field. + * PSU_DDR_PHY_DX8SL3OSC_RESERVED_12_11 0x3 - PVREF_DAC REFSEL range select - PSU_DDR_PHY_DX8SL0IOCR_DXDACRANGE 0x7 + * Oscillator Mode Write-Data Delay Line Select + * PSU_DDR_PHY_DX8SL3OSC_OSCWDDL 0x3 - IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring - PSU_DDR_PHY_DX8SL0IOCR_DXVREFIOM 0x0 + * Reserved. Caution, do not write to this register field. + * PSU_DDR_PHY_DX8SL3OSC_RESERVED_8_7 0x3 - DX IO Mode - PSU_DDR_PHY_DX8SL0IOCR_DXIOM 0x2 + * Oscillator Mode Write-Leveling Delay Line Select + * PSU_DDR_PHY_DX8SL3OSC_OSCWDL 0x3 - DX IO Transmitter Mode - PSU_DDR_PHY_DX8SL0IOCR_DXTXM 0x0 + * Oscillator Mode Division + * PSU_DDR_PHY_DX8SL3OSC_OSCDIV 0xf - DX IO Receiver Mode - PSU_DDR_PHY_DX8SL0IOCR_DXRXM 0x0 + * Oscillator Enable + * PSU_DDR_PHY_DX8SL3OSC_OSCEN 0x0 - DATX8 0-1 I/O Configuration Register - (OFFSET, MASK, VALUE) (0XFD081430, 0xFFFFFFFFU ,0x70800000U) - RegMask = (DDR_PHY_DX8SL0IOCR_RESERVED_31_MASK | DDR_PHY_DX8SL0IOCR_DXDACRANGE_MASK | DDR_PHY_DX8SL0IOCR_DXVREFIOM_MASK | DDR_PHY_DX8SL0IOCR_DXIOM_MASK | DDR_PHY_DX8SL0IOCR_DXTXM_MASK | DDR_PHY_DX8SL0IOCR_DXRXM_MASK | 0 ); + * DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Lo + * opback, and Gated Clock Control Register + * (OFFSET, MASK, VALUE) (0XFD0814C0, 0xFFFFFFFFU ,0x2A019FFEU) + */ + PSU_Mask_Write(DDR_PHY_DX8SL3OSC_OFFSET, 0xFFFFFFFFU, 0x2A019FFEU); +/*##################################################################### */ - RegVal = ((0x00000000U << DDR_PHY_DX8SL0IOCR_RESERVED_31_SHIFT - | 0x00000007U << DDR_PHY_DX8SL0IOCR_DXDACRANGE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0IOCR_DXVREFIOM_SHIFT - | 0x00000002U << DDR_PHY_DX8SL0IOCR_DXIOM_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0IOCR_DXTXM_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0IOCR_DXRXM_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8SL0IOCR_OFFSET ,0xFFFFFFFFU ,0x70800000U); - /*############################################################################################################################ */ + /* + * Register : DX8SL3PLLCR0 @ 0XFD0814C4 - /*Register : DX8SL1OSC @ 0XFD081440

+ * PLL Bypass + * PSU_DDR_PHY_DX8SL3PLLCR0_PLLBYP 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL1OSC_RESERVED_31_30 0x0 + * PLL Reset + * PSU_DDR_PHY_DX8SL3PLLCR0_PLLRST 0x0 - Enable Clock Gating for DX ddr_clk - PSU_DDR_PHY_DX8SL1OSC_GATEDXRDCLK 0x2 + * PLL Power Down + * PSU_DDR_PHY_DX8SL3PLLCR0_PLLPD 0x0 - Enable Clock Gating for DX ctl_rd_clk - PSU_DDR_PHY_DX8SL1OSC_GATEDXDDRCLK 0x2 + * Reference Stop Mode + * PSU_DDR_PHY_DX8SL3PLLCR0_RSTOPM 0x0 - Enable Clock Gating for DX ctl_clk - PSU_DDR_PHY_DX8SL1OSC_GATEDXCTLCLK 0x2 + * PLL Frequency Select + * PSU_DDR_PHY_DX8SL3PLLCR0_FRQSEL 0x1 - Selects the level to which clocks will be stalled when clock gating is enabled. - PSU_DDR_PHY_DX8SL1OSC_CLKLEVEL 0x0 + * Relock Mode + * PSU_DDR_PHY_DX8SL3PLLCR0_RLOCKM 0x0 - Loopback Mode - PSU_DDR_PHY_DX8SL1OSC_LBMODE 0x0 + * Charge Pump Proportional Current Control + * PSU_DDR_PHY_DX8SL3PLLCR0_CPPC 0x8 - Load GSDQS LCDL with 2x the calibrated GSDQSPRD value - PSU_DDR_PHY_DX8SL1OSC_LBGSDQS 0x0 + * Charge Pump Integrating Current Control + * PSU_DDR_PHY_DX8SL3PLLCR0_CPIC 0x0 - Loopback DQS Gating - PSU_DDR_PHY_DX8SL1OSC_LBGDQS 0x0 + * Gear Shift + * PSU_DDR_PHY_DX8SL3PLLCR0_GSHIFT 0x0 - Loopback DQS Shift - PSU_DDR_PHY_DX8SL1OSC_LBDQSS 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL3PLLCR0_RESERVED_11_9 0x0 - PHY High-Speed Reset - PSU_DDR_PHY_DX8SL1OSC_PHYHRST 0x1 + * Analog Test Enable (ATOEN) + * PSU_DDR_PHY_DX8SL3PLLCR0_ATOEN 0x0 - PHY FIFO Reset - PSU_DDR_PHY_DX8SL1OSC_PHYFRST 0x1 + * Analog Test Control + * PSU_DDR_PHY_DX8SL3PLLCR0_ATC 0x0 - Delay Line Test Start - PSU_DDR_PHY_DX8SL1OSC_DLTST 0x0 + * Digital Test Control + * PSU_DDR_PHY_DX8SL3PLLCR0_DTC 0x0 - Delay Line Test Mode - PSU_DDR_PHY_DX8SL1OSC_DLTMODE 0x0 + * DAXT8 0-1 PLL Control Register 0 + * (OFFSET, MASK, VALUE) (0XFD0814C4, 0xFFFFFFFFU ,0x01100000U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL3PLLCR0_OFFSET, + 0xFFFFFFFFU, 0x01100000U); +/*##################################################################### */ - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX8SL1OSC_RESERVED_12_11 0x3 - - Oscillator Mode Write-Data Delay Line Select - PSU_DDR_PHY_DX8SL1OSC_OSCWDDL 0x3 - - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX8SL1OSC_RESERVED_8_7 0x3 - - Oscillator Mode Write-Leveling Delay Line Select - PSU_DDR_PHY_DX8SL1OSC_OSCWDL 0x3 - - Oscillator Mode Division - PSU_DDR_PHY_DX8SL1OSC_OSCDIV 0xf + /* + * Register : DX8SL3DQSCTL @ 0XFD0814DC - Oscillator Enable - PSU_DDR_PHY_DX8SL1OSC_OSCEN 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25 0x0 - DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register - (OFFSET, MASK, VALUE) (0XFD081440, 0xFFFFFFFFU ,0x2A019FFEU) - RegMask = (DDR_PHY_DX8SL1OSC_RESERVED_31_30_MASK | DDR_PHY_DX8SL1OSC_GATEDXRDCLK_MASK | DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_MASK | DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_MASK | DDR_PHY_DX8SL1OSC_CLKLEVEL_MASK | DDR_PHY_DX8SL1OSC_LBMODE_MASK | DDR_PHY_DX8SL1OSC_LBGSDQS_MASK | DDR_PHY_DX8SL1OSC_LBGDQS_MASK | DDR_PHY_DX8SL1OSC_LBDQSS_MASK | DDR_PHY_DX8SL1OSC_PHYHRST_MASK | DDR_PHY_DX8SL1OSC_PHYFRST_MASK | DDR_PHY_DX8SL1OSC_DLTST_MASK | DDR_PHY_DX8SL1OSC_DLTMODE_MASK | DDR_PHY_DX8SL1OSC_RESERVED_12_11_MASK | DDR_PHY_DX8SL1OSC_OSCWDDL_MASK | DDR_PHY_DX8SL1OSC_RESERVED_8_7_MASK | DDR_PHY_DX8SL1OSC_OSCWDL_MASK | DDR_PHY_DX8SL1OSC_OSCDIV_MASK | DDR_PHY_DX8SL1OSC_OSCEN_MASK | 0 ); + * Read Path Rise-to-Rise Mode + * PSU_DDR_PHY_DX8SL3DQSCTL_RRRMODE 0x1 - RegVal = ((0x00000000U << DDR_PHY_DX8SL1OSC_RESERVED_31_30_SHIFT - | 0x00000002U << DDR_PHY_DX8SL1OSC_GATEDXRDCLK_SHIFT - | 0x00000002U << DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_SHIFT - | 0x00000002U << DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1OSC_CLKLEVEL_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1OSC_LBMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1OSC_LBGSDQS_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1OSC_LBGDQS_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1OSC_LBDQSS_SHIFT - | 0x00000001U << DDR_PHY_DX8SL1OSC_PHYHRST_SHIFT - | 0x00000001U << DDR_PHY_DX8SL1OSC_PHYFRST_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1OSC_DLTST_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1OSC_DLTMODE_SHIFT - | 0x00000003U << DDR_PHY_DX8SL1OSC_RESERVED_12_11_SHIFT - | 0x00000003U << DDR_PHY_DX8SL1OSC_OSCWDDL_SHIFT - | 0x00000003U << DDR_PHY_DX8SL1OSC_RESERVED_8_7_SHIFT - | 0x00000003U << DDR_PHY_DX8SL1OSC_OSCWDL_SHIFT - | 0x0000000FU << DDR_PHY_DX8SL1OSC_OSCDIV_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1OSC_OSCEN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8SL1OSC_OFFSET ,0xFFFFFFFFU ,0x2A019FFEU); - /*############################################################################################################################ */ + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22 0x0 - /*Register : DX8SL1DQSCTL @ 0XFD08145C

+ * Write Path Rise-to-Rise Mode + * PSU_DDR_PHY_DX8SL3DQSCTL_WRRMODE 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25 0x0 + * DQS Gate Extension + * PSU_DDR_PHY_DX8SL3DQSCTL_DQSGX 0x0 - Read Path Rise-to-Rise Mode - PSU_DDR_PHY_DX8SL1DQSCTL_RRRMODE 0x1 + * Low Power PLL Power Down + * PSU_DDR_PHY_DX8SL3DQSCTL_LPPLLPD 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22 0x0 + * Low Power I/O Power Down + * PSU_DDR_PHY_DX8SL3DQSCTL_LPIOPD 0x1 - Write Path Rise-to-Rise Mode - PSU_DDR_PHY_DX8SL1DQSCTL_WRRMODE 0x1 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15 0x0 - DQS Gate Extension - PSU_DDR_PHY_DX8SL1DQSCTL_DQSGX 0x0 + * QS Counter Enable + * PSU_DDR_PHY_DX8SL3DQSCTL_QSCNTEN 0x1 - Low Power PLL Power Down - PSU_DDR_PHY_DX8SL1DQSCTL_LPPLLPD 0x1 + * Unused DQ I/O Mode + * PSU_DDR_PHY_DX8SL3DQSCTL_UDQIOM 0x0 - Low Power I/O Power Down - PSU_DDR_PHY_DX8SL1DQSCTL_LPIOPD 0x1 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15 0x0 + * Data Slew Rate + * PSU_DDR_PHY_DX8SL3DQSCTL_DXSR 0x3 - QS Counter Enable - PSU_DDR_PHY_DX8SL1DQSCTL_QSCNTEN 0x1 + * DQS_N Resistor + * PSU_DDR_PHY_DX8SL3DQSCTL_DQSNRES 0x0 - Unused DQ I/O Mode - PSU_DDR_PHY_DX8SL1DQSCTL_UDQIOM 0x0 + * DQS Resistor + * PSU_DDR_PHY_DX8SL3DQSCTL_DQSRES 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10 0x0 + * DATX8 0-1 DQS Control Register + * (OFFSET, MASK, VALUE) (0XFD0814DC, 0xFFFFFFFFU ,0x01264300U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL3DQSCTL_OFFSET, + 0xFFFFFFFFU, 0x01264300U); +/*##################################################################### */ - Data Slew Rate - PSU_DDR_PHY_DX8SL1DQSCTL_DXSR 0x3 - - DQS_N Resistor - PSU_DDR_PHY_DX8SL1DQSCTL_DQSNRES 0x0 - - DQS Resistor - PSU_DDR_PHY_DX8SL1DQSCTL_DQSRES 0x0 - - DATX8 0-1 DQS Control Register - (OFFSET, MASK, VALUE) (0XFD08145C, 0xFFFFFFFFU ,0x01264300U) - RegMask = (DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_MASK | DDR_PHY_DX8SL1DQSCTL_RRRMODE_MASK | DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_MASK | DDR_PHY_DX8SL1DQSCTL_WRRMODE_MASK | DDR_PHY_DX8SL1DQSCTL_DQSGX_MASK | DDR_PHY_DX8SL1DQSCTL_LPPLLPD_MASK | DDR_PHY_DX8SL1DQSCTL_LPIOPD_MASK | DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_MASK | DDR_PHY_DX8SL1DQSCTL_QSCNTEN_MASK | DDR_PHY_DX8SL1DQSCTL_UDQIOM_MASK | DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_MASK | DDR_PHY_DX8SL1DQSCTL_DXSR_MASK | DDR_PHY_DX8SL1DQSCTL_DQSNRES_MASK | DDR_PHY_DX8SL1DQSCTL_DQSRES_MASK | 0 ); + /* + * Register : DX8SL3DXCTL2 @ 0XFD0814EC - RegVal = ((0x00000000U << DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_SHIFT - | 0x00000001U << DDR_PHY_DX8SL1DQSCTL_RRRMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_SHIFT - | 0x00000001U << DDR_PHY_DX8SL1DQSCTL_WRRMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1DQSCTL_DQSGX_SHIFT - | 0x00000001U << DDR_PHY_DX8SL1DQSCTL_LPPLLPD_SHIFT - | 0x00000001U << DDR_PHY_DX8SL1DQSCTL_LPIOPD_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_SHIFT - | 0x00000001U << DDR_PHY_DX8SL1DQSCTL_QSCNTEN_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1DQSCTL_UDQIOM_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_SHIFT - | 0x00000003U << DDR_PHY_DX8SL1DQSCTL_DXSR_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1DQSCTL_DQSNRES_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1DQSCTL_DQSRES_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8SL1DQSCTL_OFFSET ,0xFFFFFFFFU ,0x01264300U); - /*############################################################################################################################ */ - - /*Register : DX8SL1DXCTL2 @ 0XFD08146C

- - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24 0x0 - - Configurable Read Data Enable - PSU_DDR_PHY_DX8SL1DXCTL2_CRDEN 0x0 - - OX Extension during Post-amble - PSU_DDR_PHY_DX8SL1DXCTL2_POSOEX 0x0 - - OE Extension during Pre-amble - PSU_DDR_PHY_DX8SL1DXCTL2_PREOEX 0x1 - - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_17 0x0 - - I/O Assisted Gate Select - PSU_DDR_PHY_DX8SL1DXCTL2_IOAG 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24 0x0 - I/O Loopback Select - PSU_DDR_PHY_DX8SL1DXCTL2_IOLB 0x0 + * Configurable Read Data Enable + * PSU_DDR_PHY_DX8SL3DXCTL2_CRDEN 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13 0x0 + * OX Extension during Post-amble + * PSU_DDR_PHY_DX8SL3DXCTL2_POSOEX 0x0 - Low Power Wakeup Threshold - PSU_DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH 0xc + * OE Extension during Pre-amble + * PSU_DDR_PHY_DX8SL3DXCTL2_PREOEX 0x1 - Read Data Bus Inversion Enable - PSU_DDR_PHY_DX8SL1DXCTL2_RDBI 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_17 0x0 - Write Data Bus Inversion Enable - PSU_DDR_PHY_DX8SL1DXCTL2_WDBI 0x0 + * I/O Assisted Gate Select + * PSU_DDR_PHY_DX8SL3DXCTL2_IOAG 0x0 - PUB Read FIFO Bypass - PSU_DDR_PHY_DX8SL1DXCTL2_PRFBYP 0x0 + * I/O Loopback Select + * PSU_DDR_PHY_DX8SL3DXCTL2_IOLB 0x0 - DATX8 Receive FIFO Read Mode - PSU_DDR_PHY_DX8SL1DXCTL2_RDMODE 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13 0x0 - Disables the Read FIFO Reset - PSU_DDR_PHY_DX8SL1DXCTL2_DISRST 0x0 + * Low Power Wakeup Threshold + * PSU_DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH 0xc - Read DQS Gate I/O Loopback - PSU_DDR_PHY_DX8SL1DXCTL2_DQSGLB 0x0 + * Read Data Bus Inversion Enable + * PSU_DDR_PHY_DX8SL3DXCTL2_RDBI 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_0 0x0 + * Write Data Bus Inversion Enable + * PSU_DDR_PHY_DX8SL3DXCTL2_WDBI 0x0 - DATX8 0-1 DX Control Register 2 - (OFFSET, MASK, VALUE) (0XFD08146C, 0xFFFFFFFFU ,0x00041800U) - RegMask = (DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_MASK | DDR_PHY_DX8SL1DXCTL2_CRDEN_MASK | DDR_PHY_DX8SL1DXCTL2_POSOEX_MASK | DDR_PHY_DX8SL1DXCTL2_PREOEX_MASK | DDR_PHY_DX8SL1DXCTL2_RESERVED_17_MASK | DDR_PHY_DX8SL1DXCTL2_IOAG_MASK | DDR_PHY_DX8SL1DXCTL2_IOLB_MASK | DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_MASK | DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_MASK | DDR_PHY_DX8SL1DXCTL2_RDBI_MASK | DDR_PHY_DX8SL1DXCTL2_WDBI_MASK | DDR_PHY_DX8SL1DXCTL2_PRFBYP_MASK | DDR_PHY_DX8SL1DXCTL2_RDMODE_MASK | DDR_PHY_DX8SL1DXCTL2_DISRST_MASK | DDR_PHY_DX8SL1DXCTL2_DQSGLB_MASK | DDR_PHY_DX8SL1DXCTL2_RESERVED_0_MASK | 0 ); + * PUB Read FIFO Bypass + * PSU_DDR_PHY_DX8SL3DXCTL2_PRFBYP 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_CRDEN_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_POSOEX_SHIFT - | 0x00000001U << DDR_PHY_DX8SL1DXCTL2_PREOEX_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_RESERVED_17_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_IOAG_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_IOLB_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_SHIFT - | 0x0000000CU << DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_RDBI_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_WDBI_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_PRFBYP_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_RDMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_DISRST_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_DQSGLB_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_RESERVED_0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8SL1DXCTL2_OFFSET ,0xFFFFFFFFU ,0x00041800U); - /*############################################################################################################################ */ + * DATX8 Receive FIFO Read Mode + * PSU_DDR_PHY_DX8SL3DXCTL2_RDMODE 0x0 - /*Register : DX8SL1IOCR @ 0XFD081470

+ * Disables the Read FIFO Reset + * PSU_DDR_PHY_DX8SL3DXCTL2_DISRST 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL1IOCR_RESERVED_31 0x0 + * Read DQS Gate I/O Loopback + * PSU_DDR_PHY_DX8SL3DXCTL2_DQSGLB 0x0 - PVREF_DAC REFSEL range select - PSU_DDR_PHY_DX8SL1IOCR_DXDACRANGE 0x7 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_0 0x0 - IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring - PSU_DDR_PHY_DX8SL1IOCR_DXVREFIOM 0x0 + * DATX8 0-1 DX Control Register 2 + * (OFFSET, MASK, VALUE) (0XFD0814EC, 0xFFFFFFFFU ,0x00041800U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL3DXCTL2_OFFSET, + 0xFFFFFFFFU, 0x00041800U); +/*##################################################################### */ - DX IO Mode - PSU_DDR_PHY_DX8SL1IOCR_DXIOM 0x2 + /* + * Register : DX8SL3IOCR @ 0XFD0814F0 - DX IO Transmitter Mode - PSU_DDR_PHY_DX8SL1IOCR_DXTXM 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL3IOCR_RESERVED_31 0x0 - DX IO Receiver Mode - PSU_DDR_PHY_DX8SL1IOCR_DXRXM 0x0 + * PVREF_DAC REFSEL range select + * PSU_DDR_PHY_DX8SL3IOCR_DXDACRANGE 0x7 - DATX8 0-1 I/O Configuration Register - (OFFSET, MASK, VALUE) (0XFD081470, 0xFFFFFFFFU ,0x70800000U) - RegMask = (DDR_PHY_DX8SL1IOCR_RESERVED_31_MASK | DDR_PHY_DX8SL1IOCR_DXDACRANGE_MASK | DDR_PHY_DX8SL1IOCR_DXVREFIOM_MASK | DDR_PHY_DX8SL1IOCR_DXIOM_MASK | DDR_PHY_DX8SL1IOCR_DXTXM_MASK | DDR_PHY_DX8SL1IOCR_DXRXM_MASK | 0 ); + * IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring + * PSU_DDR_PHY_DX8SL3IOCR_DXVREFIOM 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX8SL1IOCR_RESERVED_31_SHIFT - | 0x00000007U << DDR_PHY_DX8SL1IOCR_DXDACRANGE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1IOCR_DXVREFIOM_SHIFT - | 0x00000002U << DDR_PHY_DX8SL1IOCR_DXIOM_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1IOCR_DXTXM_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1IOCR_DXRXM_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8SL1IOCR_OFFSET ,0xFFFFFFFFU ,0x70800000U); - /*############################################################################################################################ */ + * DX IO Mode + * PSU_DDR_PHY_DX8SL3IOCR_DXIOM 0x2 - /*Register : DX8SL2OSC @ 0XFD081480

+ * DX IO Transmitter Mode + * PSU_DDR_PHY_DX8SL3IOCR_DXTXM 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL2OSC_RESERVED_31_30 0x0 + * DX IO Receiver Mode + * PSU_DDR_PHY_DX8SL3IOCR_DXRXM 0x0 - Enable Clock Gating for DX ddr_clk - PSU_DDR_PHY_DX8SL2OSC_GATEDXRDCLK 0x2 + * DATX8 0-1 I/O Configuration Register + * (OFFSET, MASK, VALUE) (0XFD0814F0, 0xFFFFFFFFU ,0x70800000U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL3IOCR_OFFSET, 0xFFFFFFFFU, 0x70800000U); +/*##################################################################### */ - Enable Clock Gating for DX ctl_rd_clk - PSU_DDR_PHY_DX8SL2OSC_GATEDXDDRCLK 0x2 + /* + * Register : DX8SL4OSC @ 0XFD081500 - Enable Clock Gating for DX ctl_clk - PSU_DDR_PHY_DX8SL2OSC_GATEDXCTLCLK 0x2 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL4OSC_RESERVED_31_30 0x0 - Selects the level to which clocks will be stalled when clock gating is enabled. - PSU_DDR_PHY_DX8SL2OSC_CLKLEVEL 0x0 + * Enable Clock Gating for DX ddr_clk + * PSU_DDR_PHY_DX8SL4OSC_GATEDXRDCLK 0x2 - Loopback Mode - PSU_DDR_PHY_DX8SL2OSC_LBMODE 0x0 + * Enable Clock Gating for DX ctl_rd_clk + * PSU_DDR_PHY_DX8SL4OSC_GATEDXDDRCLK 0x2 - Load GSDQS LCDL with 2x the calibrated GSDQSPRD value - PSU_DDR_PHY_DX8SL2OSC_LBGSDQS 0x0 + * Enable Clock Gating for DX ctl_clk + * PSU_DDR_PHY_DX8SL4OSC_GATEDXCTLCLK 0x2 - Loopback DQS Gating - PSU_DDR_PHY_DX8SL2OSC_LBGDQS 0x0 + * Selects the level to which clocks will be stalled when clock gating is e + * nabled. + * PSU_DDR_PHY_DX8SL4OSC_CLKLEVEL 0x0 - Loopback DQS Shift - PSU_DDR_PHY_DX8SL2OSC_LBDQSS 0x0 + * Loopback Mode + * PSU_DDR_PHY_DX8SL4OSC_LBMODE 0x0 - PHY High-Speed Reset - PSU_DDR_PHY_DX8SL2OSC_PHYHRST 0x1 + * Load GSDQS LCDL with 2x the calibrated GSDQSPRD value + * PSU_DDR_PHY_DX8SL4OSC_LBGSDQS 0x0 - PHY FIFO Reset - PSU_DDR_PHY_DX8SL2OSC_PHYFRST 0x1 + * Loopback DQS Gating + * PSU_DDR_PHY_DX8SL4OSC_LBGDQS 0x0 - Delay Line Test Start - PSU_DDR_PHY_DX8SL2OSC_DLTST 0x0 + * Loopback DQS Shift + * PSU_DDR_PHY_DX8SL4OSC_LBDQSS 0x0 - Delay Line Test Mode - PSU_DDR_PHY_DX8SL2OSC_DLTMODE 0x0 + * PHY High-Speed Reset + * PSU_DDR_PHY_DX8SL4OSC_PHYHRST 0x1 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX8SL2OSC_RESERVED_12_11 0x3 - - Oscillator Mode Write-Data Delay Line Select - PSU_DDR_PHY_DX8SL2OSC_OSCWDDL 0x3 - - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX8SL2OSC_RESERVED_8_7 0x3 - - Oscillator Mode Write-Leveling Delay Line Select - PSU_DDR_PHY_DX8SL2OSC_OSCWDL 0x3 - - Oscillator Mode Division - PSU_DDR_PHY_DX8SL2OSC_OSCDIV 0xf + * PHY FIFO Reset + * PSU_DDR_PHY_DX8SL4OSC_PHYFRST 0x1 - Oscillator Enable - PSU_DDR_PHY_DX8SL2OSC_OSCEN 0x0 + * Delay Line Test Start + * PSU_DDR_PHY_DX8SL4OSC_DLTST 0x0 - DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register - (OFFSET, MASK, VALUE) (0XFD081480, 0xFFFFFFFFU ,0x2A019FFEU) - RegMask = (DDR_PHY_DX8SL2OSC_RESERVED_31_30_MASK | DDR_PHY_DX8SL2OSC_GATEDXRDCLK_MASK | DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_MASK | DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_MASK | DDR_PHY_DX8SL2OSC_CLKLEVEL_MASK | DDR_PHY_DX8SL2OSC_LBMODE_MASK | DDR_PHY_DX8SL2OSC_LBGSDQS_MASK | DDR_PHY_DX8SL2OSC_LBGDQS_MASK | DDR_PHY_DX8SL2OSC_LBDQSS_MASK | DDR_PHY_DX8SL2OSC_PHYHRST_MASK | DDR_PHY_DX8SL2OSC_PHYFRST_MASK | DDR_PHY_DX8SL2OSC_DLTST_MASK | DDR_PHY_DX8SL2OSC_DLTMODE_MASK | DDR_PHY_DX8SL2OSC_RESERVED_12_11_MASK | DDR_PHY_DX8SL2OSC_OSCWDDL_MASK | DDR_PHY_DX8SL2OSC_RESERVED_8_7_MASK | DDR_PHY_DX8SL2OSC_OSCWDL_MASK | DDR_PHY_DX8SL2OSC_OSCDIV_MASK | DDR_PHY_DX8SL2OSC_OSCEN_MASK | 0 ); + * Delay Line Test Mode + * PSU_DDR_PHY_DX8SL4OSC_DLTMODE 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX8SL2OSC_RESERVED_31_30_SHIFT - | 0x00000002U << DDR_PHY_DX8SL2OSC_GATEDXRDCLK_SHIFT - | 0x00000002U << DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_SHIFT - | 0x00000002U << DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2OSC_CLKLEVEL_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2OSC_LBMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2OSC_LBGSDQS_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2OSC_LBGDQS_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2OSC_LBDQSS_SHIFT - | 0x00000001U << DDR_PHY_DX8SL2OSC_PHYHRST_SHIFT - | 0x00000001U << DDR_PHY_DX8SL2OSC_PHYFRST_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2OSC_DLTST_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2OSC_DLTMODE_SHIFT - | 0x00000003U << DDR_PHY_DX8SL2OSC_RESERVED_12_11_SHIFT - | 0x00000003U << DDR_PHY_DX8SL2OSC_OSCWDDL_SHIFT - | 0x00000003U << DDR_PHY_DX8SL2OSC_RESERVED_8_7_SHIFT - | 0x00000003U << DDR_PHY_DX8SL2OSC_OSCWDL_SHIFT - | 0x0000000FU << DDR_PHY_DX8SL2OSC_OSCDIV_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2OSC_OSCEN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8SL2OSC_OFFSET ,0xFFFFFFFFU ,0x2A019FFEU); - /*############################################################################################################################ */ + * Reserved. Caution, do not write to this register field. + * PSU_DDR_PHY_DX8SL4OSC_RESERVED_12_11 0x3 - /*Register : DX8SL2DQSCTL @ 0XFD08149C

+ * Oscillator Mode Write-Data Delay Line Select + * PSU_DDR_PHY_DX8SL4OSC_OSCWDDL 0x3 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25 0x0 + * Reserved. Caution, do not write to this register field. + * PSU_DDR_PHY_DX8SL4OSC_RESERVED_8_7 0x3 - Read Path Rise-to-Rise Mode - PSU_DDR_PHY_DX8SL2DQSCTL_RRRMODE 0x1 + * Oscillator Mode Write-Leveling Delay Line Select + * PSU_DDR_PHY_DX8SL4OSC_OSCWDL 0x3 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22 0x0 + * Oscillator Mode Division + * PSU_DDR_PHY_DX8SL4OSC_OSCDIV 0xf - Write Path Rise-to-Rise Mode - PSU_DDR_PHY_DX8SL2DQSCTL_WRRMODE 0x1 + * Oscillator Enable + * PSU_DDR_PHY_DX8SL4OSC_OSCEN 0x0 - DQS Gate Extension - PSU_DDR_PHY_DX8SL2DQSCTL_DQSGX 0x0 + * DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Lo + * opback, and Gated Clock Control Register + * (OFFSET, MASK, VALUE) (0XFD081500, 0xFFFFFFFFU ,0x2A019FFEU) + */ + PSU_Mask_Write(DDR_PHY_DX8SL4OSC_OFFSET, 0xFFFFFFFFU, 0x2A019FFEU); +/*##################################################################### */ - Low Power PLL Power Down - PSU_DDR_PHY_DX8SL2DQSCTL_LPPLLPD 0x1 + /* + * Register : DX8SL4PLLCR0 @ 0XFD081504 - Low Power I/O Power Down - PSU_DDR_PHY_DX8SL2DQSCTL_LPIOPD 0x1 + * PLL Bypass + * PSU_DDR_PHY_DX8SL4PLLCR0_PLLBYP 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15 0x0 + * PLL Reset + * PSU_DDR_PHY_DX8SL4PLLCR0_PLLRST 0x0 - QS Counter Enable - PSU_DDR_PHY_DX8SL2DQSCTL_QSCNTEN 0x1 + * PLL Power Down + * PSU_DDR_PHY_DX8SL4PLLCR0_PLLPD 0x0 - Unused DQ I/O Mode - PSU_DDR_PHY_DX8SL2DQSCTL_UDQIOM 0x0 + * Reference Stop Mode + * PSU_DDR_PHY_DX8SL4PLLCR0_RSTOPM 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10 0x0 + * PLL Frequency Select + * PSU_DDR_PHY_DX8SL4PLLCR0_FRQSEL 0x1 - Data Slew Rate - PSU_DDR_PHY_DX8SL2DQSCTL_DXSR 0x3 - - DQS_N Resistor - PSU_DDR_PHY_DX8SL2DQSCTL_DQSNRES 0x0 - - DQS Resistor - PSU_DDR_PHY_DX8SL2DQSCTL_DQSRES 0x0 - - DATX8 0-1 DQS Control Register - (OFFSET, MASK, VALUE) (0XFD08149C, 0xFFFFFFFFU ,0x01264300U) - RegMask = (DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_MASK | DDR_PHY_DX8SL2DQSCTL_RRRMODE_MASK | DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_MASK | DDR_PHY_DX8SL2DQSCTL_WRRMODE_MASK | DDR_PHY_DX8SL2DQSCTL_DQSGX_MASK | DDR_PHY_DX8SL2DQSCTL_LPPLLPD_MASK | DDR_PHY_DX8SL2DQSCTL_LPIOPD_MASK | DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_MASK | DDR_PHY_DX8SL2DQSCTL_QSCNTEN_MASK | DDR_PHY_DX8SL2DQSCTL_UDQIOM_MASK | DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_MASK | DDR_PHY_DX8SL2DQSCTL_DXSR_MASK | DDR_PHY_DX8SL2DQSCTL_DQSNRES_MASK | DDR_PHY_DX8SL2DQSCTL_DQSRES_MASK | 0 ); + * Relock Mode + * PSU_DDR_PHY_DX8SL4PLLCR0_RLOCKM 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_SHIFT - | 0x00000001U << DDR_PHY_DX8SL2DQSCTL_RRRMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_SHIFT - | 0x00000001U << DDR_PHY_DX8SL2DQSCTL_WRRMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2DQSCTL_DQSGX_SHIFT - | 0x00000001U << DDR_PHY_DX8SL2DQSCTL_LPPLLPD_SHIFT - | 0x00000001U << DDR_PHY_DX8SL2DQSCTL_LPIOPD_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_SHIFT - | 0x00000001U << DDR_PHY_DX8SL2DQSCTL_QSCNTEN_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2DQSCTL_UDQIOM_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_SHIFT - | 0x00000003U << DDR_PHY_DX8SL2DQSCTL_DXSR_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2DQSCTL_DQSNRES_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2DQSCTL_DQSRES_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8SL2DQSCTL_OFFSET ,0xFFFFFFFFU ,0x01264300U); - /*############################################################################################################################ */ - - /*Register : DX8SL2DXCTL2 @ 0XFD0814AC

- - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24 0x0 - - Configurable Read Data Enable - PSU_DDR_PHY_DX8SL2DXCTL2_CRDEN 0x0 - - OX Extension during Post-amble - PSU_DDR_PHY_DX8SL2DXCTL2_POSOEX 0x0 - - OE Extension during Pre-amble - PSU_DDR_PHY_DX8SL2DXCTL2_PREOEX 0x1 - - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_17 0x0 - - I/O Assisted Gate Select - PSU_DDR_PHY_DX8SL2DXCTL2_IOAG 0x0 + * Charge Pump Proportional Current Control + * PSU_DDR_PHY_DX8SL4PLLCR0_CPPC 0x8 - I/O Loopback Select - PSU_DDR_PHY_DX8SL2DXCTL2_IOLB 0x0 + * Charge Pump Integrating Current Control + * PSU_DDR_PHY_DX8SL4PLLCR0_CPIC 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13 0x0 + * Gear Shift + * PSU_DDR_PHY_DX8SL4PLLCR0_GSHIFT 0x0 - Low Power Wakeup Threshold - PSU_DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH 0xc + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL4PLLCR0_RESERVED_11_9 0x0 - Read Data Bus Inversion Enable - PSU_DDR_PHY_DX8SL2DXCTL2_RDBI 0x0 + * Analog Test Enable (ATOEN) + * PSU_DDR_PHY_DX8SL4PLLCR0_ATOEN 0x0 - Write Data Bus Inversion Enable - PSU_DDR_PHY_DX8SL2DXCTL2_WDBI 0x0 + * Analog Test Control + * PSU_DDR_PHY_DX8SL4PLLCR0_ATC 0x0 - PUB Read FIFO Bypass - PSU_DDR_PHY_DX8SL2DXCTL2_PRFBYP 0x0 + * Digital Test Control + * PSU_DDR_PHY_DX8SL4PLLCR0_DTC 0x0 - DATX8 Receive FIFO Read Mode - PSU_DDR_PHY_DX8SL2DXCTL2_RDMODE 0x0 + * DAXT8 0-1 PLL Control Register 0 + * (OFFSET, MASK, VALUE) (0XFD081504, 0xFFFFFFFFU ,0x01100000U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL4PLLCR0_OFFSET, + 0xFFFFFFFFU, 0x01100000U); +/*##################################################################### */ - Disables the Read FIFO Reset - PSU_DDR_PHY_DX8SL2DXCTL2_DISRST 0x0 + /* + * Register : DX8SL4DQSCTL @ 0XFD08151C - Read DQS Gate I/O Loopback - PSU_DDR_PHY_DX8SL2DXCTL2_DQSGLB 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_0 0x0 + * Read Path Rise-to-Rise Mode + * PSU_DDR_PHY_DX8SL4DQSCTL_RRRMODE 0x1 - DATX8 0-1 DX Control Register 2 - (OFFSET, MASK, VALUE) (0XFD0814AC, 0xFFFFFFFFU ,0x00041800U) - RegMask = (DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_MASK | DDR_PHY_DX8SL2DXCTL2_CRDEN_MASK | DDR_PHY_DX8SL2DXCTL2_POSOEX_MASK | DDR_PHY_DX8SL2DXCTL2_PREOEX_MASK | DDR_PHY_DX8SL2DXCTL2_RESERVED_17_MASK | DDR_PHY_DX8SL2DXCTL2_IOAG_MASK | DDR_PHY_DX8SL2DXCTL2_IOLB_MASK | DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_MASK | DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_MASK | DDR_PHY_DX8SL2DXCTL2_RDBI_MASK | DDR_PHY_DX8SL2DXCTL2_WDBI_MASK | DDR_PHY_DX8SL2DXCTL2_PRFBYP_MASK | DDR_PHY_DX8SL2DXCTL2_RDMODE_MASK | DDR_PHY_DX8SL2DXCTL2_DISRST_MASK | DDR_PHY_DX8SL2DXCTL2_DQSGLB_MASK | DDR_PHY_DX8SL2DXCTL2_RESERVED_0_MASK | 0 ); + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_CRDEN_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_POSOEX_SHIFT - | 0x00000001U << DDR_PHY_DX8SL2DXCTL2_PREOEX_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_RESERVED_17_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_IOAG_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_IOLB_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_SHIFT - | 0x0000000CU << DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_RDBI_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_WDBI_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_PRFBYP_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_RDMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_DISRST_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_DQSGLB_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_RESERVED_0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8SL2DXCTL2_OFFSET ,0xFFFFFFFFU ,0x00041800U); - /*############################################################################################################################ */ + * Write Path Rise-to-Rise Mode + * PSU_DDR_PHY_DX8SL4DQSCTL_WRRMODE 0x1 - /*Register : DX8SL2IOCR @ 0XFD0814B0

+ * DQS Gate Extension + * PSU_DDR_PHY_DX8SL4DQSCTL_DQSGX 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL2IOCR_RESERVED_31 0x0 + * Low Power PLL Power Down + * PSU_DDR_PHY_DX8SL4DQSCTL_LPPLLPD 0x1 - PVREF_DAC REFSEL range select - PSU_DDR_PHY_DX8SL2IOCR_DXDACRANGE 0x7 + * Low Power I/O Power Down + * PSU_DDR_PHY_DX8SL4DQSCTL_LPIOPD 0x1 - IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring - PSU_DDR_PHY_DX8SL2IOCR_DXVREFIOM 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15 0x0 - DX IO Mode - PSU_DDR_PHY_DX8SL2IOCR_DXIOM 0x2 + * QS Counter Enable + * PSU_DDR_PHY_DX8SL4DQSCTL_QSCNTEN 0x1 - DX IO Transmitter Mode - PSU_DDR_PHY_DX8SL2IOCR_DXTXM 0x0 + * Unused DQ I/O Mode + * PSU_DDR_PHY_DX8SL4DQSCTL_UDQIOM 0x0 - DX IO Receiver Mode - PSU_DDR_PHY_DX8SL2IOCR_DXRXM 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10 0x0 - DATX8 0-1 I/O Configuration Register - (OFFSET, MASK, VALUE) (0XFD0814B0, 0xFFFFFFFFU ,0x70800000U) - RegMask = (DDR_PHY_DX8SL2IOCR_RESERVED_31_MASK | DDR_PHY_DX8SL2IOCR_DXDACRANGE_MASK | DDR_PHY_DX8SL2IOCR_DXVREFIOM_MASK | DDR_PHY_DX8SL2IOCR_DXIOM_MASK | DDR_PHY_DX8SL2IOCR_DXTXM_MASK | DDR_PHY_DX8SL2IOCR_DXRXM_MASK | 0 ); + * Data Slew Rate + * PSU_DDR_PHY_DX8SL4DQSCTL_DXSR 0x3 - RegVal = ((0x00000000U << DDR_PHY_DX8SL2IOCR_RESERVED_31_SHIFT - | 0x00000007U << DDR_PHY_DX8SL2IOCR_DXDACRANGE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2IOCR_DXVREFIOM_SHIFT - | 0x00000002U << DDR_PHY_DX8SL2IOCR_DXIOM_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2IOCR_DXTXM_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2IOCR_DXRXM_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8SL2IOCR_OFFSET ,0xFFFFFFFFU ,0x70800000U); - /*############################################################################################################################ */ + * DQS_N Resistor + * PSU_DDR_PHY_DX8SL4DQSCTL_DQSNRES 0x0 - /*Register : DX8SL3OSC @ 0XFD0814C0

+ * DQS Resistor + * PSU_DDR_PHY_DX8SL4DQSCTL_DQSRES 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL3OSC_RESERVED_31_30 0x0 + * DATX8 0-1 DQS Control Register + * (OFFSET, MASK, VALUE) (0XFD08151C, 0xFFFFFFFFU ,0x01264300U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL4DQSCTL_OFFSET, + 0xFFFFFFFFU, 0x01264300U); +/*##################################################################### */ - Enable Clock Gating for DX ddr_clk - PSU_DDR_PHY_DX8SL3OSC_GATEDXRDCLK 0x2 + /* + * Register : DX8SL4DXCTL2 @ 0XFD08152C - Enable Clock Gating for DX ctl_rd_clk - PSU_DDR_PHY_DX8SL3OSC_GATEDXDDRCLK 0x2 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24 0x0 - Enable Clock Gating for DX ctl_clk - PSU_DDR_PHY_DX8SL3OSC_GATEDXCTLCLK 0x2 + * Configurable Read Data Enable + * PSU_DDR_PHY_DX8SL4DXCTL2_CRDEN 0x0 - Selects the level to which clocks will be stalled when clock gating is enabled. - PSU_DDR_PHY_DX8SL3OSC_CLKLEVEL 0x0 + * OX Extension during Post-amble + * PSU_DDR_PHY_DX8SL4DXCTL2_POSOEX 0x0 - Loopback Mode - PSU_DDR_PHY_DX8SL3OSC_LBMODE 0x0 + * OE Extension during Pre-amble + * PSU_DDR_PHY_DX8SL4DXCTL2_PREOEX 0x1 - Load GSDQS LCDL with 2x the calibrated GSDQSPRD value - PSU_DDR_PHY_DX8SL3OSC_LBGSDQS 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_17 0x0 - Loopback DQS Gating - PSU_DDR_PHY_DX8SL3OSC_LBGDQS 0x0 + * I/O Assisted Gate Select + * PSU_DDR_PHY_DX8SL4DXCTL2_IOAG 0x0 - Loopback DQS Shift - PSU_DDR_PHY_DX8SL3OSC_LBDQSS 0x0 + * I/O Loopback Select + * PSU_DDR_PHY_DX8SL4DXCTL2_IOLB 0x0 - PHY High-Speed Reset - PSU_DDR_PHY_DX8SL3OSC_PHYHRST 0x1 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13 0x0 - PHY FIFO Reset - PSU_DDR_PHY_DX8SL3OSC_PHYFRST 0x1 + * Low Power Wakeup Threshold + * PSU_DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH 0xc - Delay Line Test Start - PSU_DDR_PHY_DX8SL3OSC_DLTST 0x0 + * Read Data Bus Inversion Enable + * PSU_DDR_PHY_DX8SL4DXCTL2_RDBI 0x0 - Delay Line Test Mode - PSU_DDR_PHY_DX8SL3OSC_DLTMODE 0x0 + * Write Data Bus Inversion Enable + * PSU_DDR_PHY_DX8SL4DXCTL2_WDBI 0x0 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX8SL3OSC_RESERVED_12_11 0x3 - - Oscillator Mode Write-Data Delay Line Select - PSU_DDR_PHY_DX8SL3OSC_OSCWDDL 0x3 - - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX8SL3OSC_RESERVED_8_7 0x3 - - Oscillator Mode Write-Leveling Delay Line Select - PSU_DDR_PHY_DX8SL3OSC_OSCWDL 0x3 - - Oscillator Mode Division - PSU_DDR_PHY_DX8SL3OSC_OSCDIV 0xf + * PUB Read FIFO Bypass + * PSU_DDR_PHY_DX8SL4DXCTL2_PRFBYP 0x0 - Oscillator Enable - PSU_DDR_PHY_DX8SL3OSC_OSCEN 0x0 + * DATX8 Receive FIFO Read Mode + * PSU_DDR_PHY_DX8SL4DXCTL2_RDMODE 0x0 - DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register - (OFFSET, MASK, VALUE) (0XFD0814C0, 0xFFFFFFFFU ,0x2A019FFEU) - RegMask = (DDR_PHY_DX8SL3OSC_RESERVED_31_30_MASK | DDR_PHY_DX8SL3OSC_GATEDXRDCLK_MASK | DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_MASK | DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_MASK | DDR_PHY_DX8SL3OSC_CLKLEVEL_MASK | DDR_PHY_DX8SL3OSC_LBMODE_MASK | DDR_PHY_DX8SL3OSC_LBGSDQS_MASK | DDR_PHY_DX8SL3OSC_LBGDQS_MASK | DDR_PHY_DX8SL3OSC_LBDQSS_MASK | DDR_PHY_DX8SL3OSC_PHYHRST_MASK | DDR_PHY_DX8SL3OSC_PHYFRST_MASK | DDR_PHY_DX8SL3OSC_DLTST_MASK | DDR_PHY_DX8SL3OSC_DLTMODE_MASK | DDR_PHY_DX8SL3OSC_RESERVED_12_11_MASK | DDR_PHY_DX8SL3OSC_OSCWDDL_MASK | DDR_PHY_DX8SL3OSC_RESERVED_8_7_MASK | DDR_PHY_DX8SL3OSC_OSCWDL_MASK | DDR_PHY_DX8SL3OSC_OSCDIV_MASK | DDR_PHY_DX8SL3OSC_OSCEN_MASK | 0 ); + * Disables the Read FIFO Reset + * PSU_DDR_PHY_DX8SL4DXCTL2_DISRST 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX8SL3OSC_RESERVED_31_30_SHIFT - | 0x00000002U << DDR_PHY_DX8SL3OSC_GATEDXRDCLK_SHIFT - | 0x00000002U << DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_SHIFT - | 0x00000002U << DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3OSC_CLKLEVEL_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3OSC_LBMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3OSC_LBGSDQS_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3OSC_LBGDQS_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3OSC_LBDQSS_SHIFT - | 0x00000001U << DDR_PHY_DX8SL3OSC_PHYHRST_SHIFT - | 0x00000001U << DDR_PHY_DX8SL3OSC_PHYFRST_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3OSC_DLTST_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3OSC_DLTMODE_SHIFT - | 0x00000003U << DDR_PHY_DX8SL3OSC_RESERVED_12_11_SHIFT - | 0x00000003U << DDR_PHY_DX8SL3OSC_OSCWDDL_SHIFT - | 0x00000003U << DDR_PHY_DX8SL3OSC_RESERVED_8_7_SHIFT - | 0x00000003U << DDR_PHY_DX8SL3OSC_OSCWDL_SHIFT - | 0x0000000FU << DDR_PHY_DX8SL3OSC_OSCDIV_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3OSC_OSCEN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8SL3OSC_OFFSET ,0xFFFFFFFFU ,0x2A019FFEU); - /*############################################################################################################################ */ + * Read DQS Gate I/O Loopback + * PSU_DDR_PHY_DX8SL4DXCTL2_DQSGLB 0x0 - /*Register : DX8SL3DQSCTL @ 0XFD0814DC

+ * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_0 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25 0x0 + * DATX8 0-1 DX Control Register 2 + * (OFFSET, MASK, VALUE) (0XFD08152C, 0xFFFFFFFFU ,0x00041800U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL4DXCTL2_OFFSET, + 0xFFFFFFFFU, 0x00041800U); +/*##################################################################### */ - Read Path Rise-to-Rise Mode - PSU_DDR_PHY_DX8SL3DQSCTL_RRRMODE 0x1 + /* + * Register : DX8SL4IOCR @ 0XFD081530 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL4IOCR_RESERVED_31 0x0 - Write Path Rise-to-Rise Mode - PSU_DDR_PHY_DX8SL3DQSCTL_WRRMODE 0x1 + * PVREF_DAC REFSEL range select + * PSU_DDR_PHY_DX8SL4IOCR_DXDACRANGE 0x7 - DQS Gate Extension - PSU_DDR_PHY_DX8SL3DQSCTL_DQSGX 0x0 + * IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring + * PSU_DDR_PHY_DX8SL4IOCR_DXVREFIOM 0x0 - Low Power PLL Power Down - PSU_DDR_PHY_DX8SL3DQSCTL_LPPLLPD 0x1 + * DX IO Mode + * PSU_DDR_PHY_DX8SL4IOCR_DXIOM 0x2 - Low Power I/O Power Down - PSU_DDR_PHY_DX8SL3DQSCTL_LPIOPD 0x1 + * DX IO Transmitter Mode + * PSU_DDR_PHY_DX8SL4IOCR_DXTXM 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15 0x0 + * DX IO Receiver Mode + * PSU_DDR_PHY_DX8SL4IOCR_DXRXM 0x0 - QS Counter Enable - PSU_DDR_PHY_DX8SL3DQSCTL_QSCNTEN 0x1 + * DATX8 0-1 I/O Configuration Register + * (OFFSET, MASK, VALUE) (0XFD081530, 0xFFFFFFFFU ,0x70800000U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL4IOCR_OFFSET, 0xFFFFFFFFU, 0x70800000U); +/*##################################################################### */ - Unused DQ I/O Mode - PSU_DDR_PHY_DX8SL3DQSCTL_UDQIOM 0x0 + /* + * Register : DX8SLbPLLCR0 @ 0XFD0817C4 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10 0x0 + * PLL Bypass + * PSU_DDR_PHY_DX8SLBPLLCR0_PLLBYP 0x0 - Data Slew Rate - PSU_DDR_PHY_DX8SL3DQSCTL_DXSR 0x3 - - DQS_N Resistor - PSU_DDR_PHY_DX8SL3DQSCTL_DQSNRES 0x0 - - DQS Resistor - PSU_DDR_PHY_DX8SL3DQSCTL_DQSRES 0x0 - - DATX8 0-1 DQS Control Register - (OFFSET, MASK, VALUE) (0XFD0814DC, 0xFFFFFFFFU ,0x01264300U) - RegMask = (DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_MASK | DDR_PHY_DX8SL3DQSCTL_RRRMODE_MASK | DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_MASK | DDR_PHY_DX8SL3DQSCTL_WRRMODE_MASK | DDR_PHY_DX8SL3DQSCTL_DQSGX_MASK | DDR_PHY_DX8SL3DQSCTL_LPPLLPD_MASK | DDR_PHY_DX8SL3DQSCTL_LPIOPD_MASK | DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_MASK | DDR_PHY_DX8SL3DQSCTL_QSCNTEN_MASK | DDR_PHY_DX8SL3DQSCTL_UDQIOM_MASK | DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_MASK | DDR_PHY_DX8SL3DQSCTL_DXSR_MASK | DDR_PHY_DX8SL3DQSCTL_DQSNRES_MASK | DDR_PHY_DX8SL3DQSCTL_DQSRES_MASK | 0 ); + * PLL Reset + * PSU_DDR_PHY_DX8SLBPLLCR0_PLLRST 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_SHIFT - | 0x00000001U << DDR_PHY_DX8SL3DQSCTL_RRRMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_SHIFT - | 0x00000001U << DDR_PHY_DX8SL3DQSCTL_WRRMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3DQSCTL_DQSGX_SHIFT - | 0x00000001U << DDR_PHY_DX8SL3DQSCTL_LPPLLPD_SHIFT - | 0x00000001U << DDR_PHY_DX8SL3DQSCTL_LPIOPD_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_SHIFT - | 0x00000001U << DDR_PHY_DX8SL3DQSCTL_QSCNTEN_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3DQSCTL_UDQIOM_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_SHIFT - | 0x00000003U << DDR_PHY_DX8SL3DQSCTL_DXSR_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3DQSCTL_DQSNRES_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3DQSCTL_DQSRES_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8SL3DQSCTL_OFFSET ,0xFFFFFFFFU ,0x01264300U); - /*############################################################################################################################ */ - - /*Register : DX8SL3DXCTL2 @ 0XFD0814EC

- - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24 0x0 - - Configurable Read Data Enable - PSU_DDR_PHY_DX8SL3DXCTL2_CRDEN 0x0 - - OX Extension during Post-amble - PSU_DDR_PHY_DX8SL3DXCTL2_POSOEX 0x0 - - OE Extension during Pre-amble - PSU_DDR_PHY_DX8SL3DXCTL2_PREOEX 0x1 - - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_17 0x0 - - I/O Assisted Gate Select - PSU_DDR_PHY_DX8SL3DXCTL2_IOAG 0x0 + * PLL Power Down + * PSU_DDR_PHY_DX8SLBPLLCR0_PLLPD 0x0 - I/O Loopback Select - PSU_DDR_PHY_DX8SL3DXCTL2_IOLB 0x0 + * Reference Stop Mode + * PSU_DDR_PHY_DX8SLBPLLCR0_RSTOPM 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13 0x0 + * PLL Frequency Select + * PSU_DDR_PHY_DX8SLBPLLCR0_FRQSEL 0x1 - Low Power Wakeup Threshold - PSU_DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH 0xc + * Relock Mode + * PSU_DDR_PHY_DX8SLBPLLCR0_RLOCKM 0x0 - Read Data Bus Inversion Enable - PSU_DDR_PHY_DX8SL3DXCTL2_RDBI 0x0 + * Charge Pump Proportional Current Control + * PSU_DDR_PHY_DX8SLBPLLCR0_CPPC 0x8 - Write Data Bus Inversion Enable - PSU_DDR_PHY_DX8SL3DXCTL2_WDBI 0x0 + * Charge Pump Integrating Current Control + * PSU_DDR_PHY_DX8SLBPLLCR0_CPIC 0x0 - PUB Read FIFO Bypass - PSU_DDR_PHY_DX8SL3DXCTL2_PRFBYP 0x0 + * Gear Shift + * PSU_DDR_PHY_DX8SLBPLLCR0_GSHIFT 0x0 - DATX8 Receive FIFO Read Mode - PSU_DDR_PHY_DX8SL3DXCTL2_RDMODE 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SLBPLLCR0_RESERVED_11_9 0x0 - Disables the Read FIFO Reset - PSU_DDR_PHY_DX8SL3DXCTL2_DISRST 0x0 + * Analog Test Enable (ATOEN) + * PSU_DDR_PHY_DX8SLBPLLCR0_ATOEN 0x0 - Read DQS Gate I/O Loopback - PSU_DDR_PHY_DX8SL3DXCTL2_DQSGLB 0x0 + * Analog Test Control + * PSU_DDR_PHY_DX8SLBPLLCR0_ATC 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_0 0x0 + * Digital Test Control + * PSU_DDR_PHY_DX8SLBPLLCR0_DTC 0x0 - DATX8 0-1 DX Control Register 2 - (OFFSET, MASK, VALUE) (0XFD0814EC, 0xFFFFFFFFU ,0x00041800U) - RegMask = (DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_MASK | DDR_PHY_DX8SL3DXCTL2_CRDEN_MASK | DDR_PHY_DX8SL3DXCTL2_POSOEX_MASK | DDR_PHY_DX8SL3DXCTL2_PREOEX_MASK | DDR_PHY_DX8SL3DXCTL2_RESERVED_17_MASK | DDR_PHY_DX8SL3DXCTL2_IOAG_MASK | DDR_PHY_DX8SL3DXCTL2_IOLB_MASK | DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_MASK | DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_MASK | DDR_PHY_DX8SL3DXCTL2_RDBI_MASK | DDR_PHY_DX8SL3DXCTL2_WDBI_MASK | DDR_PHY_DX8SL3DXCTL2_PRFBYP_MASK | DDR_PHY_DX8SL3DXCTL2_RDMODE_MASK | DDR_PHY_DX8SL3DXCTL2_DISRST_MASK | DDR_PHY_DX8SL3DXCTL2_DQSGLB_MASK | DDR_PHY_DX8SL3DXCTL2_RESERVED_0_MASK | 0 ); + * DAXT8 0-8 PLL Control Register 0 + * (OFFSET, MASK, VALUE) (0XFD0817C4, 0xFFFFFFFFU ,0x01100000U) + */ + PSU_Mask_Write(DDR_PHY_DX8SLBPLLCR0_OFFSET, + 0xFFFFFFFFU, 0x01100000U); +/*##################################################################### */ - RegVal = ((0x00000000U << DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_CRDEN_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_POSOEX_SHIFT - | 0x00000001U << DDR_PHY_DX8SL3DXCTL2_PREOEX_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_RESERVED_17_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_IOAG_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_IOLB_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_SHIFT - | 0x0000000CU << DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_RDBI_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_WDBI_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_PRFBYP_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_RDMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_DISRST_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_DQSGLB_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_RESERVED_0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8SL3DXCTL2_OFFSET ,0xFFFFFFFFU ,0x00041800U); - /*############################################################################################################################ */ + /* + * Register : DX8SLbDQSCTL @ 0XFD0817DC - /*Register : DX8SL3IOCR @ 0XFD0814F0

+ * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL3IOCR_RESERVED_31 0x0 + * Read Path Rise-to-Rise Mode + * PSU_DDR_PHY_DX8SLBDQSCTL_RRRMODE 0x1 - PVREF_DAC REFSEL range select - PSU_DDR_PHY_DX8SL3IOCR_DXDACRANGE 0x7 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22 0x0 - IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring - PSU_DDR_PHY_DX8SL3IOCR_DXVREFIOM 0x0 + * Write Path Rise-to-Rise Mode + * PSU_DDR_PHY_DX8SLBDQSCTL_WRRMODE 0x1 - DX IO Mode - PSU_DDR_PHY_DX8SL3IOCR_DXIOM 0x2 + * DQS Gate Extension + * PSU_DDR_PHY_DX8SLBDQSCTL_DQSGX 0x0 - DX IO Transmitter Mode - PSU_DDR_PHY_DX8SL3IOCR_DXTXM 0x0 + * Low Power PLL Power Down + * PSU_DDR_PHY_DX8SLBDQSCTL_LPPLLPD 0x1 - DX IO Receiver Mode - PSU_DDR_PHY_DX8SL3IOCR_DXRXM 0x0 + * Low Power I/O Power Down + * PSU_DDR_PHY_DX8SLBDQSCTL_LPIOPD 0x1 - DATX8 0-1 I/O Configuration Register - (OFFSET, MASK, VALUE) (0XFD0814F0, 0xFFFFFFFFU ,0x70800000U) - RegMask = (DDR_PHY_DX8SL3IOCR_RESERVED_31_MASK | DDR_PHY_DX8SL3IOCR_DXDACRANGE_MASK | DDR_PHY_DX8SL3IOCR_DXVREFIOM_MASK | DDR_PHY_DX8SL3IOCR_DXIOM_MASK | DDR_PHY_DX8SL3IOCR_DXTXM_MASK | DDR_PHY_DX8SL3IOCR_DXRXM_MASK | 0 ); + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX8SL3IOCR_RESERVED_31_SHIFT - | 0x00000007U << DDR_PHY_DX8SL3IOCR_DXDACRANGE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3IOCR_DXVREFIOM_SHIFT - | 0x00000002U << DDR_PHY_DX8SL3IOCR_DXIOM_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3IOCR_DXTXM_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3IOCR_DXRXM_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8SL3IOCR_OFFSET ,0xFFFFFFFFU ,0x70800000U); - /*############################################################################################################################ */ + * QS Counter Enable + * PSU_DDR_PHY_DX8SLBDQSCTL_QSCNTEN 0x1 - /*Register : DX8SL4OSC @ 0XFD081500

+ * Unused DQ I/O Mode + * PSU_DDR_PHY_DX8SLBDQSCTL_UDQIOM 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL4OSC_RESERVED_31_30 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10 0x0 - Enable Clock Gating for DX ddr_clk - PSU_DDR_PHY_DX8SL4OSC_GATEDXRDCLK 0x2 + * Data Slew Rate + * PSU_DDR_PHY_DX8SLBDQSCTL_DXSR 0x3 - Enable Clock Gating for DX ctl_rd_clk - PSU_DDR_PHY_DX8SL4OSC_GATEDXDDRCLK 0x2 + * DQS# Resistor + * PSU_DDR_PHY_DX8SLBDQSCTL_DQSNRES 0xc - Enable Clock Gating for DX ctl_clk - PSU_DDR_PHY_DX8SL4OSC_GATEDXCTLCLK 0x2 + * DQS Resistor + * PSU_DDR_PHY_DX8SLBDQSCTL_DQSRES 0x4 - Selects the level to which clocks will be stalled when clock gating is enabled. - PSU_DDR_PHY_DX8SL4OSC_CLKLEVEL 0x0 + * DATX8 0-8 DQS Control Register + * (OFFSET, MASK, VALUE) (0XFD0817DC, 0xFFFFFFFFU ,0x012643C4U) + */ + PSU_Mask_Write(DDR_PHY_DX8SLBDQSCTL_OFFSET, + 0xFFFFFFFFU, 0x012643C4U); +/*##################################################################### */ - Loopback Mode - PSU_DDR_PHY_DX8SL4OSC_LBMODE 0x0 - Load GSDQS LCDL with 2x the calibrated GSDQSPRD value - PSU_DDR_PHY_DX8SL4OSC_LBGSDQS 0x0 - - Loopback DQS Gating - PSU_DDR_PHY_DX8SL4OSC_LBGDQS 0x0 - - Loopback DQS Shift - PSU_DDR_PHY_DX8SL4OSC_LBDQSS 0x0 - - PHY High-Speed Reset - PSU_DDR_PHY_DX8SL4OSC_PHYHRST 0x1 - - PHY FIFO Reset - PSU_DDR_PHY_DX8SL4OSC_PHYFRST 0x1 - - Delay Line Test Start - PSU_DDR_PHY_DX8SL4OSC_DLTST 0x0 - - Delay Line Test Mode - PSU_DDR_PHY_DX8SL4OSC_DLTMODE 0x0 - - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX8SL4OSC_RESERVED_12_11 0x3 - - Oscillator Mode Write-Data Delay Line Select - PSU_DDR_PHY_DX8SL4OSC_OSCWDDL 0x3 - - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX8SL4OSC_RESERVED_8_7 0x3 - - Oscillator Mode Write-Leveling Delay Line Select - PSU_DDR_PHY_DX8SL4OSC_OSCWDL 0x3 - - Oscillator Mode Division - PSU_DDR_PHY_DX8SL4OSC_OSCDIV 0xf - - Oscillator Enable - PSU_DDR_PHY_DX8SL4OSC_OSCEN 0x0 - - DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register - (OFFSET, MASK, VALUE) (0XFD081500, 0xFFFFFFFFU ,0x2A019FFEU) - RegMask = (DDR_PHY_DX8SL4OSC_RESERVED_31_30_MASK | DDR_PHY_DX8SL4OSC_GATEDXRDCLK_MASK | DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_MASK | DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_MASK | DDR_PHY_DX8SL4OSC_CLKLEVEL_MASK | DDR_PHY_DX8SL4OSC_LBMODE_MASK | DDR_PHY_DX8SL4OSC_LBGSDQS_MASK | DDR_PHY_DX8SL4OSC_LBGDQS_MASK | DDR_PHY_DX8SL4OSC_LBDQSS_MASK | DDR_PHY_DX8SL4OSC_PHYHRST_MASK | DDR_PHY_DX8SL4OSC_PHYFRST_MASK | DDR_PHY_DX8SL4OSC_DLTST_MASK | DDR_PHY_DX8SL4OSC_DLTMODE_MASK | DDR_PHY_DX8SL4OSC_RESERVED_12_11_MASK | DDR_PHY_DX8SL4OSC_OSCWDDL_MASK | DDR_PHY_DX8SL4OSC_RESERVED_8_7_MASK | DDR_PHY_DX8SL4OSC_OSCWDL_MASK | DDR_PHY_DX8SL4OSC_OSCDIV_MASK | DDR_PHY_DX8SL4OSC_OSCEN_MASK | 0 ); - - RegVal = ((0x00000000U << DDR_PHY_DX8SL4OSC_RESERVED_31_30_SHIFT - | 0x00000002U << DDR_PHY_DX8SL4OSC_GATEDXRDCLK_SHIFT - | 0x00000002U << DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_SHIFT - | 0x00000002U << DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4OSC_CLKLEVEL_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4OSC_LBMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4OSC_LBGSDQS_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4OSC_LBGDQS_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4OSC_LBDQSS_SHIFT - | 0x00000001U << DDR_PHY_DX8SL4OSC_PHYHRST_SHIFT - | 0x00000001U << DDR_PHY_DX8SL4OSC_PHYFRST_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4OSC_DLTST_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4OSC_DLTMODE_SHIFT - | 0x00000003U << DDR_PHY_DX8SL4OSC_RESERVED_12_11_SHIFT - | 0x00000003U << DDR_PHY_DX8SL4OSC_OSCWDDL_SHIFT - | 0x00000003U << DDR_PHY_DX8SL4OSC_RESERVED_8_7_SHIFT - | 0x00000003U << DDR_PHY_DX8SL4OSC_OSCWDL_SHIFT - | 0x0000000FU << DDR_PHY_DX8SL4OSC_OSCDIV_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4OSC_OSCEN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8SL4OSC_OFFSET ,0xFFFFFFFFU ,0x2A019FFEU); - /*############################################################################################################################ */ - - /*Register : DX8SL4DQSCTL @ 0XFD08151C

- - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25 0x0 - - Read Path Rise-to-Rise Mode - PSU_DDR_PHY_DX8SL4DQSCTL_RRRMODE 0x1 - - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22 0x0 - - Write Path Rise-to-Rise Mode - PSU_DDR_PHY_DX8SL4DQSCTL_WRRMODE 0x1 - - DQS Gate Extension - PSU_DDR_PHY_DX8SL4DQSCTL_DQSGX 0x0 - - Low Power PLL Power Down - PSU_DDR_PHY_DX8SL4DQSCTL_LPPLLPD 0x1 - - Low Power I/O Power Down - PSU_DDR_PHY_DX8SL4DQSCTL_LPIOPD 0x1 - - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15 0x0 - - QS Counter Enable - PSU_DDR_PHY_DX8SL4DQSCTL_QSCNTEN 0x1 - - Unused DQ I/O Mode - PSU_DDR_PHY_DX8SL4DQSCTL_UDQIOM 0x0 - - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10 0x0 - - Data Slew Rate - PSU_DDR_PHY_DX8SL4DQSCTL_DXSR 0x3 - - DQS_N Resistor - PSU_DDR_PHY_DX8SL4DQSCTL_DQSNRES 0x0 - - DQS Resistor - PSU_DDR_PHY_DX8SL4DQSCTL_DQSRES 0x0 - - DATX8 0-1 DQS Control Register - (OFFSET, MASK, VALUE) (0XFD08151C, 0xFFFFFFFFU ,0x01264300U) - RegMask = (DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_MASK | DDR_PHY_DX8SL4DQSCTL_RRRMODE_MASK | DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_MASK | DDR_PHY_DX8SL4DQSCTL_WRRMODE_MASK | DDR_PHY_DX8SL4DQSCTL_DQSGX_MASK | DDR_PHY_DX8SL4DQSCTL_LPPLLPD_MASK | DDR_PHY_DX8SL4DQSCTL_LPIOPD_MASK | DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_MASK | DDR_PHY_DX8SL4DQSCTL_QSCNTEN_MASK | DDR_PHY_DX8SL4DQSCTL_UDQIOM_MASK | DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_MASK | DDR_PHY_DX8SL4DQSCTL_DXSR_MASK | DDR_PHY_DX8SL4DQSCTL_DQSNRES_MASK | DDR_PHY_DX8SL4DQSCTL_DQSRES_MASK | 0 ); - - RegVal = ((0x00000000U << DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_SHIFT - | 0x00000001U << DDR_PHY_DX8SL4DQSCTL_RRRMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_SHIFT - | 0x00000001U << DDR_PHY_DX8SL4DQSCTL_WRRMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4DQSCTL_DQSGX_SHIFT - | 0x00000001U << DDR_PHY_DX8SL4DQSCTL_LPPLLPD_SHIFT - | 0x00000001U << DDR_PHY_DX8SL4DQSCTL_LPIOPD_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_SHIFT - | 0x00000001U << DDR_PHY_DX8SL4DQSCTL_QSCNTEN_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4DQSCTL_UDQIOM_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_SHIFT - | 0x00000003U << DDR_PHY_DX8SL4DQSCTL_DXSR_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4DQSCTL_DQSNRES_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4DQSCTL_DQSRES_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8SL4DQSCTL_OFFSET ,0xFFFFFFFFU ,0x01264300U); - /*############################################################################################################################ */ - - /*Register : DX8SL4DXCTL2 @ 0XFD08152C

- - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24 0x0 - - Configurable Read Data Enable - PSU_DDR_PHY_DX8SL4DXCTL2_CRDEN 0x0 - - OX Extension during Post-amble - PSU_DDR_PHY_DX8SL4DXCTL2_POSOEX 0x0 - - OE Extension during Pre-amble - PSU_DDR_PHY_DX8SL4DXCTL2_PREOEX 0x1 - - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_17 0x0 - - I/O Assisted Gate Select - PSU_DDR_PHY_DX8SL4DXCTL2_IOAG 0x0 - - I/O Loopback Select - PSU_DDR_PHY_DX8SL4DXCTL2_IOLB 0x0 - - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13 0x0 - - Low Power Wakeup Threshold - PSU_DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH 0xc - - Read Data Bus Inversion Enable - PSU_DDR_PHY_DX8SL4DXCTL2_RDBI 0x0 - - Write Data Bus Inversion Enable - PSU_DDR_PHY_DX8SL4DXCTL2_WDBI 0x0 - - PUB Read FIFO Bypass - PSU_DDR_PHY_DX8SL4DXCTL2_PRFBYP 0x0 - - DATX8 Receive FIFO Read Mode - PSU_DDR_PHY_DX8SL4DXCTL2_RDMODE 0x0 - - Disables the Read FIFO Reset - PSU_DDR_PHY_DX8SL4DXCTL2_DISRST 0x0 - - Read DQS Gate I/O Loopback - PSU_DDR_PHY_DX8SL4DXCTL2_DQSGLB 0x0 - - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_0 0x0 - - DATX8 0-1 DX Control Register 2 - (OFFSET, MASK, VALUE) (0XFD08152C, 0xFFFFFFFFU ,0x00041800U) - RegMask = (DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_MASK | DDR_PHY_DX8SL4DXCTL2_CRDEN_MASK | DDR_PHY_DX8SL4DXCTL2_POSOEX_MASK | DDR_PHY_DX8SL4DXCTL2_PREOEX_MASK | DDR_PHY_DX8SL4DXCTL2_RESERVED_17_MASK | DDR_PHY_DX8SL4DXCTL2_IOAG_MASK | DDR_PHY_DX8SL4DXCTL2_IOLB_MASK | DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_MASK | DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_MASK | DDR_PHY_DX8SL4DXCTL2_RDBI_MASK | DDR_PHY_DX8SL4DXCTL2_WDBI_MASK | DDR_PHY_DX8SL4DXCTL2_PRFBYP_MASK | DDR_PHY_DX8SL4DXCTL2_RDMODE_MASK | DDR_PHY_DX8SL4DXCTL2_DISRST_MASK | DDR_PHY_DX8SL4DXCTL2_DQSGLB_MASK | DDR_PHY_DX8SL4DXCTL2_RESERVED_0_MASK | 0 ); - - RegVal = ((0x00000000U << DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_CRDEN_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_POSOEX_SHIFT - | 0x00000001U << DDR_PHY_DX8SL4DXCTL2_PREOEX_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_RESERVED_17_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_IOAG_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_IOLB_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_SHIFT - | 0x0000000CU << DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_RDBI_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_WDBI_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_PRFBYP_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_RDMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_DISRST_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_DQSGLB_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_RESERVED_0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8SL4DXCTL2_OFFSET ,0xFFFFFFFFU ,0x00041800U); - /*############################################################################################################################ */ - - /*Register : DX8SL4IOCR @ 0XFD081530

- - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL4IOCR_RESERVED_31 0x0 - - PVREF_DAC REFSEL range select - PSU_DDR_PHY_DX8SL4IOCR_DXDACRANGE 0x7 - - IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring - PSU_DDR_PHY_DX8SL4IOCR_DXVREFIOM 0x0 - - DX IO Mode - PSU_DDR_PHY_DX8SL4IOCR_DXIOM 0x2 - - DX IO Transmitter Mode - PSU_DDR_PHY_DX8SL4IOCR_DXTXM 0x0 - - DX IO Receiver Mode - PSU_DDR_PHY_DX8SL4IOCR_DXRXM 0x0 - - DATX8 0-1 I/O Configuration Register - (OFFSET, MASK, VALUE) (0XFD081530, 0xFFFFFFFFU ,0x70800000U) - RegMask = (DDR_PHY_DX8SL4IOCR_RESERVED_31_MASK | DDR_PHY_DX8SL4IOCR_DXDACRANGE_MASK | DDR_PHY_DX8SL4IOCR_DXVREFIOM_MASK | DDR_PHY_DX8SL4IOCR_DXIOM_MASK | DDR_PHY_DX8SL4IOCR_DXTXM_MASK | DDR_PHY_DX8SL4IOCR_DXRXM_MASK | 0 ); - - RegVal = ((0x00000000U << DDR_PHY_DX8SL4IOCR_RESERVED_31_SHIFT - | 0x00000007U << DDR_PHY_DX8SL4IOCR_DXDACRANGE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4IOCR_DXVREFIOM_SHIFT - | 0x00000002U << DDR_PHY_DX8SL4IOCR_DXIOM_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4IOCR_DXTXM_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4IOCR_DXRXM_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8SL4IOCR_OFFSET ,0xFFFFFFFFU ,0x70800000U); - /*############################################################################################################################ */ - - /*Register : DX8SLbDQSCTL @ 0XFD0817DC

- - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25 0x0 - - Read Path Rise-to-Rise Mode - PSU_DDR_PHY_DX8SLBDQSCTL_RRRMODE 0x1 - - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22 0x0 - - Write Path Rise-to-Rise Mode - PSU_DDR_PHY_DX8SLBDQSCTL_WRRMODE 0x1 - - DQS Gate Extension - PSU_DDR_PHY_DX8SLBDQSCTL_DQSGX 0x0 - - Low Power PLL Power Down - PSU_DDR_PHY_DX8SLBDQSCTL_LPPLLPD 0x1 - - Low Power I/O Power Down - PSU_DDR_PHY_DX8SLBDQSCTL_LPIOPD 0x1 - - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15 0x0 - - QS Counter Enable - PSU_DDR_PHY_DX8SLBDQSCTL_QSCNTEN 0x1 - - Unused DQ I/O Mode - PSU_DDR_PHY_DX8SLBDQSCTL_UDQIOM 0x0 - - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10 0x0 - - Data Slew Rate - PSU_DDR_PHY_DX8SLBDQSCTL_DXSR 0x3 - - DQS# Resistor - PSU_DDR_PHY_DX8SLBDQSCTL_DQSNRES 0xc - - DQS Resistor - PSU_DDR_PHY_DX8SLBDQSCTL_DQSRES 0x4 - - DATX8 0-8 DQS Control Register - (OFFSET, MASK, VALUE) (0XFD0817DC, 0xFFFFFFFFU ,0x012643C4U) - RegMask = (DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_MASK | DDR_PHY_DX8SLBDQSCTL_RRRMODE_MASK | DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_MASK | DDR_PHY_DX8SLBDQSCTL_WRRMODE_MASK | DDR_PHY_DX8SLBDQSCTL_DQSGX_MASK | DDR_PHY_DX8SLBDQSCTL_LPPLLPD_MASK | DDR_PHY_DX8SLBDQSCTL_LPIOPD_MASK | DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_MASK | DDR_PHY_DX8SLBDQSCTL_QSCNTEN_MASK | DDR_PHY_DX8SLBDQSCTL_UDQIOM_MASK | DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_MASK | DDR_PHY_DX8SLBDQSCTL_DXSR_MASK | DDR_PHY_DX8SLBDQSCTL_DQSNRES_MASK | DDR_PHY_DX8SLBDQSCTL_DQSRES_MASK | 0 ); - - RegVal = ((0x00000000U << DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_SHIFT - | 0x00000001U << DDR_PHY_DX8SLBDQSCTL_RRRMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_SHIFT - | 0x00000001U << DDR_PHY_DX8SLBDQSCTL_WRRMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8SLBDQSCTL_DQSGX_SHIFT - | 0x00000001U << DDR_PHY_DX8SLBDQSCTL_LPPLLPD_SHIFT - | 0x00000001U << DDR_PHY_DX8SLBDQSCTL_LPIOPD_SHIFT - | 0x00000000U << DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_SHIFT - | 0x00000001U << DDR_PHY_DX8SLBDQSCTL_QSCNTEN_SHIFT - | 0x00000000U << DDR_PHY_DX8SLBDQSCTL_UDQIOM_SHIFT - | 0x00000000U << DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_SHIFT - | 0x00000003U << DDR_PHY_DX8SLBDQSCTL_DXSR_SHIFT - | 0x0000000CU << DDR_PHY_DX8SLBDQSCTL_DQSNRES_SHIFT - | 0x00000004U << DDR_PHY_DX8SLBDQSCTL_DQSRES_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8SLBDQSCTL_OFFSET ,0xFFFFFFFFU ,0x012643C4U); - /*############################################################################################################################ */ - - /*Register : PIR @ 0XFD080004

- - Reserved. Return zeroes on reads. - PSU_DDR_PHY_PIR_RESERVED_31 0x0 - - Impedance Calibration Bypass - PSU_DDR_PHY_PIR_ZCALBYP 0x0 - - Digital Delay Line (DDL) Calibration Pause - PSU_DDR_PHY_PIR_DCALPSE 0x0 - - Reserved. Return zeroes on reads. - PSU_DDR_PHY_PIR_RESERVED_28_21 0x0 - - Write DQS2DQ Training - PSU_DDR_PHY_PIR_DQS2DQ 0x0 - - RDIMM Initialization - PSU_DDR_PHY_PIR_RDIMMINIT 0x0 - - Controller DRAM Initialization - PSU_DDR_PHY_PIR_CTLDINIT 0x1 - - VREF Training - PSU_DDR_PHY_PIR_VREF 0x0 - - Static Read Training - PSU_DDR_PHY_PIR_SRD 0x0 - - Write Data Eye Training - PSU_DDR_PHY_PIR_WREYE 0x0 - - Read Data Eye Training - PSU_DDR_PHY_PIR_RDEYE 0x0 - - Write Data Bit Deskew - PSU_DDR_PHY_PIR_WRDSKW 0x0 - - Read Data Bit Deskew - PSU_DDR_PHY_PIR_RDDSKW 0x0 - - Write Leveling Adjust - PSU_DDR_PHY_PIR_WLADJ 0x0 - - Read DQS Gate Training - PSU_DDR_PHY_PIR_QSGATE 0x0 - - Write Leveling - PSU_DDR_PHY_PIR_WL 0x0 - - DRAM Initialization - PSU_DDR_PHY_PIR_DRAMINIT 0x0 - - DRAM Reset (DDR3/DDR4/LPDDR4 Only) - PSU_DDR_PHY_PIR_DRAMRST 0x0 - - PHY Reset - PSU_DDR_PHY_PIR_PHYRST 0x1 - - Digital Delay Line (DDL) Calibration - PSU_DDR_PHY_PIR_DCAL 0x1 - - PLL Initialiazation - PSU_DDR_PHY_PIR_PLLINIT 0x1 - - Reserved. Return zeroes on reads. - PSU_DDR_PHY_PIR_RESERVED_3 0x0 - - CA Training - PSU_DDR_PHY_PIR_CA 0x0 - - Impedance Calibration - PSU_DDR_PHY_PIR_ZCAL 0x1 - - Initialization Trigger - PSU_DDR_PHY_PIR_INIT 0x1 - - PHY Initialization Register - (OFFSET, MASK, VALUE) (0XFD080004, 0xFFFFFFFFU ,0x00040073U) - RegMask = (DDR_PHY_PIR_RESERVED_31_MASK | DDR_PHY_PIR_ZCALBYP_MASK | DDR_PHY_PIR_DCALPSE_MASK | DDR_PHY_PIR_RESERVED_28_21_MASK | DDR_PHY_PIR_DQS2DQ_MASK | DDR_PHY_PIR_RDIMMINIT_MASK | DDR_PHY_PIR_CTLDINIT_MASK | DDR_PHY_PIR_VREF_MASK | DDR_PHY_PIR_SRD_MASK | DDR_PHY_PIR_WREYE_MASK | DDR_PHY_PIR_RDEYE_MASK | DDR_PHY_PIR_WRDSKW_MASK | DDR_PHY_PIR_RDDSKW_MASK | DDR_PHY_PIR_WLADJ_MASK | DDR_PHY_PIR_QSGATE_MASK | DDR_PHY_PIR_WL_MASK | DDR_PHY_PIR_DRAMINIT_MASK | DDR_PHY_PIR_DRAMRST_MASK | DDR_PHY_PIR_PHYRST_MASK | DDR_PHY_PIR_DCAL_MASK | DDR_PHY_PIR_PLLINIT_MASK | DDR_PHY_PIR_RESERVED_3_MASK | DDR_PHY_PIR_CA_MASK | DDR_PHY_PIR_ZCAL_MASK | DDR_PHY_PIR_INIT_MASK | 0 ); - - RegVal = ((0x00000000U << DDR_PHY_PIR_RESERVED_31_SHIFT - | 0x00000000U << DDR_PHY_PIR_ZCALBYP_SHIFT - | 0x00000000U << DDR_PHY_PIR_DCALPSE_SHIFT - | 0x00000000U << DDR_PHY_PIR_RESERVED_28_21_SHIFT - | 0x00000000U << DDR_PHY_PIR_DQS2DQ_SHIFT - | 0x00000000U << DDR_PHY_PIR_RDIMMINIT_SHIFT - | 0x00000001U << DDR_PHY_PIR_CTLDINIT_SHIFT - | 0x00000000U << DDR_PHY_PIR_VREF_SHIFT - | 0x00000000U << DDR_PHY_PIR_SRD_SHIFT - | 0x00000000U << DDR_PHY_PIR_WREYE_SHIFT - | 0x00000000U << DDR_PHY_PIR_RDEYE_SHIFT - | 0x00000000U << DDR_PHY_PIR_WRDSKW_SHIFT - | 0x00000000U << DDR_PHY_PIR_RDDSKW_SHIFT - | 0x00000000U << DDR_PHY_PIR_WLADJ_SHIFT - | 0x00000000U << DDR_PHY_PIR_QSGATE_SHIFT - | 0x00000000U << DDR_PHY_PIR_WL_SHIFT - | 0x00000000U << DDR_PHY_PIR_DRAMINIT_SHIFT - | 0x00000000U << DDR_PHY_PIR_DRAMRST_SHIFT - | 0x00000001U << DDR_PHY_PIR_PHYRST_SHIFT - | 0x00000001U << DDR_PHY_PIR_DCAL_SHIFT - | 0x00000001U << DDR_PHY_PIR_PLLINIT_SHIFT - | 0x00000000U << DDR_PHY_PIR_RESERVED_3_SHIFT - | 0x00000000U << DDR_PHY_PIR_CA_SHIFT - | 0x00000001U << DDR_PHY_PIR_ZCAL_SHIFT - | 0x00000001U << DDR_PHY_PIR_INIT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_PIR_OFFSET ,0xFFFFFFFFU ,0x00040073U); - /*############################################################################################################################ */ - - - return 1; + return 1; } -unsigned long psu_mio_init_data() { - // : MIO PROGRAMMING - /*Register : MIO_PIN_0 @ 0XFF180000

+unsigned long psu_ddr_qos_init_data(void) +{ - Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out- (QSPI Clock) - PSU_IOU_SLCR_MIO_PIN_0_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_0_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[0]- (Test Scan Port) = test_scan, Outp - t, test_scan_out[0]- (Test Scan Port) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_0_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[0]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[0]- (GPIO bank 0) 1= can - , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa - ) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Cloc - ) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_ - lk- (Trace Port Clock) - PSU_IOU_SLCR_MIO_PIN_0_L3_SEL 0 - - Configures MIO Pin 0 peripheral interface mapping. S - (OFFSET, MASK, VALUE) (0XFF180000, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_0_L0_SEL_MASK | IOU_SLCR_MIO_PIN_0_L1_SEL_MASK | IOU_SLCR_MIO_PIN_0_L2_SEL_MASK | IOU_SLCR_MIO_PIN_0_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_0_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_0_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_0_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_0_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_0_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_1 @ 0XFF180004

- - Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (QSPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Data - us) - PSU_IOU_SLCR_MIO_PIN_1_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_1_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[1]- (Test Scan Port) = test_scan, Outp - t, test_scan_out[1]- (Test Scan Port) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_1_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[1]- (GPIO bank 0) 1= can - , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal - 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_o - t- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control - Signal) - PSU_IOU_SLCR_MIO_PIN_1_L3_SEL 0 - - Configures MIO Pin 1 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180004, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_1_L0_SEL_MASK | IOU_SLCR_MIO_PIN_1_L1_SEL_MASK | IOU_SLCR_MIO_PIN_1_L2_SEL_MASK | IOU_SLCR_MIO_PIN_1_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_1_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_1_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_1_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_1_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_1_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_2 @ 0XFF180008

- - Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus) - PSU_IOU_SLCR_MIO_PIN_2_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_2_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[2]- (Test Scan Port) = test_scan, Outp - t, test_scan_out[2]- (Test Scan Port) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_2_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[2]- (GPIO bank 0) 1= can - , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal - 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc2, Input, ttc2_clk_in - (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[0]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_2_L3_SEL 0 - - Configures MIO Pin 2 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180008, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_2_L0_SEL_MASK | IOU_SLCR_MIO_PIN_2_L1_SEL_MASK | IOU_SLCR_MIO_PIN_2_L2_SEL_MASK | IOU_SLCR_MIO_PIN_2_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_2_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_2_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_2_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_2_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_2_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_3 @ 0XFF18000C

- - Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus) - PSU_IOU_SLCR_MIO_PIN_3_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_3_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[3]- (Test Scan Port) = test_scan, Outp - t, test_scan_out[3]- (Test Scan Port) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_3_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[3]- (GPIO bank 0) 1= can - , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa - ) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0 - - (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial - output) 7= trace, Output, tracedq[1]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_3_L3_SEL 0 - - Configures MIO Pin 3 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF18000C, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_3_L0_SEL_MASK | IOU_SLCR_MIO_PIN_3_L1_SEL_MASK | IOU_SLCR_MIO_PIN_3_L2_SEL_MASK | IOU_SLCR_MIO_PIN_3_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_3_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_3_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_3_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_3_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_3_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_4 @ 0XFF180010

- - Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- (QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Data - us) - PSU_IOU_SLCR_MIO_PIN_4_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_4_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[4]- (Test Scan Port) = test_scan, Outp - t, test_scan_out[4]- (Test Scan Port) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_4_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[4]- (GPIO bank 0) 1= can - , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa - ) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_s - - (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, - utput, tracedq[2]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_4_L3_SEL 0 - - Configures MIO Pin 4 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180010, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_4_L0_SEL_MASK | IOU_SLCR_MIO_PIN_4_L1_SEL_MASK | IOU_SLCR_MIO_PIN_4_L2_SEL_MASK | IOU_SLCR_MIO_PIN_4_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_4_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_4_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_4_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_4_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_4_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_5 @ 0XFF180014

- - Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out- (QSPI Slave Select) - PSU_IOU_SLCR_MIO_PIN_5_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_5_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[5]- (Test Scan Port) = test_scan, Outp - t, test_scan_out[5]- (Test Scan Port) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_5_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[5]- (GPIO bank 0) 1= can - , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal - 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi0 - si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7 - trace, Output, tracedq[3]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_5_L3_SEL 0 - - Configures MIO Pin 5 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180014, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_5_L0_SEL_MASK | IOU_SLCR_MIO_PIN_5_L1_SEL_MASK | IOU_SLCR_MIO_PIN_5_L2_SEL_MASK | IOU_SLCR_MIO_PIN_5_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_5_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_5_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_5_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_5_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_5_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_6 @ 0XFF180018

- - Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_clk_for_lpbk- (QSPI Clock to be fed-back) - PSU_IOU_SLCR_MIO_PIN_6_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_6_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[6]- (Test Scan Port) = test_scan, Outp - t, test_scan_out[6]- (Test Scan Port) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_6_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[6]- (GPIO bank 0) 1= can - , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal - 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1 - sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, - Output, tracedq[4]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_6_L3_SEL 0 - - Configures MIO Pin 6 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180018, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_6_L0_SEL_MASK | IOU_SLCR_MIO_PIN_6_L1_SEL_MASK | IOU_SLCR_MIO_PIN_6_L2_SEL_MASK | IOU_SLCR_MIO_PIN_6_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_6_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_6_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_6_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_6_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_6_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_7 @ 0XFF18001C

- - Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out_upper- (QSPI Slave Select upper) - PSU_IOU_SLCR_MIO_PIN_7_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_7_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[7]- (Test Scan Port) = test_scan, Outp - t, test_scan_out[7]- (Test Scan Port) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_7_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[7]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[7]- (GPIO bank 0) 1= can - , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa - ) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= - tc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, - racedq[5]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_7_L3_SEL 0 - - Configures MIO Pin 7 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF18001C, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_7_L0_SEL_MASK | IOU_SLCR_MIO_PIN_7_L1_SEL_MASK | IOU_SLCR_MIO_PIN_7_L2_SEL_MASK | IOU_SLCR_MIO_PIN_7_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_7_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_7_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_7_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_7_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_7_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_8 @ 0XFF180020

- - Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[0]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe - [0]- (QSPI Upper Databus) - PSU_IOU_SLCR_MIO_PIN_8_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_8_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[8]- (Test Scan Port) = test_scan, Outp - t, test_scan_out[8]- (Test Scan Port) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_8_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[8]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[8]- (GPIO bank 0) 1= can - , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa - ) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc - , Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Tr - ce Port Databus) - PSU_IOU_SLCR_MIO_PIN_8_L3_SEL 0 - - Configures MIO Pin 8 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180020, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_8_L0_SEL_MASK | IOU_SLCR_MIO_PIN_8_L1_SEL_MASK | IOU_SLCR_MIO_PIN_8_L2_SEL_MASK | IOU_SLCR_MIO_PIN_8_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_8_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_8_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_8_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_8_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_8_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_9 @ 0XFF180024

- - Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[1]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe - [1]- (QSPI Upper Databus) - PSU_IOU_SLCR_MIO_PIN_9_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NAND chip enable) - PSU_IOU_SLCR_MIO_PIN_9_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[9]- (Test Scan Port) = test_scan, Outp - t, test_scan_out[9]- (Test Scan Port) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_9_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[9]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[9]- (GPIO bank 0) 1= can - , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal - 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, - utput, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (U - RT receiver serial input) 7= trace, Output, tracedq[7]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_9_L3_SEL 0 - - Configures MIO Pin 9 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180024, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_9_L0_SEL_MASK | IOU_SLCR_MIO_PIN_9_L1_SEL_MASK | IOU_SLCR_MIO_PIN_9_L2_SEL_MASK | IOU_SLCR_MIO_PIN_9_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_9_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_9_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_9_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_9_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_9_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_10 @ 0XFF180028

- - Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[2]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe - [2]- (QSPI Upper Databus) - PSU_IOU_SLCR_MIO_PIN_10_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (NAND Ready/Busy) - PSU_IOU_SLCR_MIO_PIN_10_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[10]- (Test Scan Port) = test_scan, Out - ut, test_scan_out[10]- (Test Scan Port) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_10_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[10]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[10]- (GPIO bank 0) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_ - o- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outp - t, tracedq[8]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_10_L3_SEL 0 - - Configures MIO Pin 10 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180028, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_10_L0_SEL_MASK | IOU_SLCR_MIO_PIN_10_L1_SEL_MASK | IOU_SLCR_MIO_PIN_10_L2_SEL_MASK | IOU_SLCR_MIO_PIN_10_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_10_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_10_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_10_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_10_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_10_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_11 @ 0XFF18002C

- - Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[3]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe - [3]- (QSPI Upper Databus) - PSU_IOU_SLCR_MIO_PIN_11_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (NAND Ready/Busy) - PSU_IOU_SLCR_MIO_PIN_11_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[11]- (Test Scan Port) = test_scan, Out - ut, test_scan_out[11]- (Test Scan Port) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_11_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s - i1_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o - tput) 7= trace, Output, tracedq[9]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_11_L3_SEL 0 - - Configures MIO Pin 11 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF18002C, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_11_L0_SEL_MASK | IOU_SLCR_MIO_PIN_11_L1_SEL_MASK | IOU_SLCR_MIO_PIN_11_L2_SEL_MASK | IOU_SLCR_MIO_PIN_11_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_11_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_11_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_11_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_11_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_11_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_12 @ 0XFF180030

- - Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out_upper- (QSPI Upper Clock) - PSU_IOU_SLCR_MIO_PIN_12_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NAND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe - - PSU_IOU_SLCR_MIO_PIN_12_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[12]- (Test Scan Port) = test_scan, Out - ut, test_scan_out[12]- (Test Scan Port) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_12_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[12]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[12]- (GPIO bank 0) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Cl - ck) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trac - dq[10]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_12_L3_SEL 0 - - Configures MIO Pin 12 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180030, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_12_L0_SEL_MASK | IOU_SLCR_MIO_PIN_12_L1_SEL_MASK | IOU_SLCR_MIO_PIN_12_L2_SEL_MASK | IOU_SLCR_MIO_PIN_12_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_12_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_12_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_12_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_12_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_12_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_13 @ 0XFF180034

- - Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_13_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[0]- (NAND chip enable) - PSU_IOU_SLCR_MIO_PIN_13_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8 - bit Data bus) 2= test_scan, Input, test_scan_in[13]- (Test Scan Port) = test_scan, Output, test_scan_out[13]- (Test Scan Port - 3= Not Used - PSU_IOU_SLCR_MIO_PIN_13_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[13]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[13]- (GPIO bank 0) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave - out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq[11]- (Trace Port Dat - bus) - PSU_IOU_SLCR_MIO_PIN_13_L3_SEL 0 - - Configures MIO Pin 13 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180034, 0x000000FEU ,0x00000000U) - RegMask = (IOU_SLCR_MIO_PIN_13_L0_SEL_MASK | IOU_SLCR_MIO_PIN_13_L1_SEL_MASK | IOU_SLCR_MIO_PIN_13_L2_SEL_MASK | IOU_SLCR_MIO_PIN_13_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_13_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_13_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_13_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_13_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_13_OFFSET ,0x000000FEU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_14 @ 0XFF180038

- - Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_14_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_cle- (NAND Command Latch Enable) - PSU_IOU_SLCR_MIO_PIN_14_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8 - bit Data bus) 2= test_scan, Input, test_scan_in[14]- (Test Scan Port) = test_scan, Output, test_scan_out[14]- (Test Scan Port - 3= Not Used - PSU_IOU_SLCR_MIO_PIN_14_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, Input, ttc0_clk_ - n- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_14_L3_SEL 2 - - Configures MIO Pin 14 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180038, 0x000000FEU ,0x00000040U) - RegMask = (IOU_SLCR_MIO_PIN_14_L0_SEL_MASK | IOU_SLCR_MIO_PIN_14_L1_SEL_MASK | IOU_SLCR_MIO_PIN_14_L2_SEL_MASK | IOU_SLCR_MIO_PIN_14_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_14_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_14_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_14_L2_SEL_SHIFT - | 0x00000002U << IOU_SLCR_MIO_PIN_14_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_14_OFFSET ,0x000000FEU ,0x00000040U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_15 @ 0XFF18003C

- - Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_15_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ale- (NAND Address Latch Enable) - PSU_IOU_SLCR_MIO_PIN_15_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8 - bit Data bus) 2= test_scan, Input, test_scan_in[15]- (Test Scan Port) = test_scan, Output, test_scan_out[15]- (Test Scan Port - 3= Not Used - PSU_IOU_SLCR_MIO_PIN_15_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[15]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[15]- (GPIO bank 0) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out - 0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter seri - l output) 7= trace, Output, tracedq[13]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_15_L3_SEL 2 - - Configures MIO Pin 15 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF18003C, 0x000000FEU ,0x00000040U) - RegMask = (IOU_SLCR_MIO_PIN_15_L0_SEL_MASK | IOU_SLCR_MIO_PIN_15_L1_SEL_MASK | IOU_SLCR_MIO_PIN_15_L2_SEL_MASK | IOU_SLCR_MIO_PIN_15_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_15_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_15_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_15_L2_SEL_SHIFT - | 0x00000002U << IOU_SLCR_MIO_PIN_15_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_15_OFFSET ,0x000000FEU ,0x00000040U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_16 @ 0XFF180040

- - Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_16_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[0]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[0]- (NAND - ata Bus) - PSU_IOU_SLCR_MIO_PIN_16_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8 - bit Data bus) 2= test_scan, Input, test_scan_in[16]- (Test Scan Port) = test_scan, Output, test_scan_out[16]- (Test Scan Port - 3= Not Used - PSU_IOU_SLCR_MIO_PIN_16_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[16]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[16]- (GPIO bank 0) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0 - so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace - Output, tracedq[14]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_16_L3_SEL 2 - - Configures MIO Pin 16 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180040, 0x000000FEU ,0x00000040U) - RegMask = (IOU_SLCR_MIO_PIN_16_L0_SEL_MASK | IOU_SLCR_MIO_PIN_16_L1_SEL_MASK | IOU_SLCR_MIO_PIN_16_L2_SEL_MASK | IOU_SLCR_MIO_PIN_16_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_16_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_16_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_16_L2_SEL_SHIFT - | 0x00000002U << IOU_SLCR_MIO_PIN_16_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_16_OFFSET ,0x000000FEU ,0x00000040U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_17 @ 0XFF180044

- - Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_17_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[1]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[1]- (NAND - ata Bus) - PSU_IOU_SLCR_MIO_PIN_17_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8 - bit Data bus) 2= test_scan, Input, test_scan_in[17]- (Test Scan Port) = test_scan, Output, test_scan_out[17]- (Test Scan Port - 3= Not Used - PSU_IOU_SLCR_MIO_PIN_17_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[17]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[17]- (GPIO bank 0) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, sp - 0_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) - 7= trace, Output, tracedq[15]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_17_L3_SEL 2 - - Configures MIO Pin 17 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180044, 0x000000FEU ,0x00000040U) - RegMask = (IOU_SLCR_MIO_PIN_17_L0_SEL_MASK | IOU_SLCR_MIO_PIN_17_L1_SEL_MASK | IOU_SLCR_MIO_PIN_17_L2_SEL_MASK | IOU_SLCR_MIO_PIN_17_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_17_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_17_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_17_L2_SEL_SHIFT - | 0x00000002U << IOU_SLCR_MIO_PIN_17_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_17_OFFSET ,0x000000FEU ,0x00000040U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_18 @ 0XFF180048

- - Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_18_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[2]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[2]- (NAND - ata Bus) - PSU_IOU_SLCR_MIO_PIN_18_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8 - bit Data bus) 2= test_scan, Input, test_scan_in[18]- (Test Scan Port) = test_scan, Output, test_scan_out[18]- (Test Scan Port - 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper) - PSU_IOU_SLCR_MIO_PIN_18_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[18]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[18]- (GPIO bank 0) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_ - o- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used - PSU_IOU_SLCR_MIO_PIN_18_L3_SEL 6 - - Configures MIO Pin 18 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180048, 0x000000FEU ,0x000000C0U) - RegMask = (IOU_SLCR_MIO_PIN_18_L0_SEL_MASK | IOU_SLCR_MIO_PIN_18_L1_SEL_MASK | IOU_SLCR_MIO_PIN_18_L2_SEL_MASK | IOU_SLCR_MIO_PIN_18_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_18_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_18_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_18_L2_SEL_SHIFT - | 0x00000006U << IOU_SLCR_MIO_PIN_18_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_18_OFFSET ,0x000000FEU ,0x000000C0U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_19 @ 0XFF18004C

- - Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_19_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[3]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[3]- (NAND - ata Bus) - PSU_IOU_SLCR_MIO_PIN_19_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8 - bit Data bus) 2= test_scan, Input, test_scan_in[19]- (Test Scan Port) = test_scan, Output, test_scan_out[19]- (Test Scan Port - 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper) - PSU_IOU_SLCR_MIO_PIN_19_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[19]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[19]- (GPIO bank 0) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5 - ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used - PSU_IOU_SLCR_MIO_PIN_19_L3_SEL 6 - - Configures MIO Pin 19 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF18004C, 0x000000FEU ,0x000000C0U) - RegMask = (IOU_SLCR_MIO_PIN_19_L0_SEL_MASK | IOU_SLCR_MIO_PIN_19_L1_SEL_MASK | IOU_SLCR_MIO_PIN_19_L2_SEL_MASK | IOU_SLCR_MIO_PIN_19_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_19_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_19_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_19_L2_SEL_SHIFT - | 0x00000006U << IOU_SLCR_MIO_PIN_19_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_19_OFFSET ,0x000000FEU ,0x000000C0U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_20 @ 0XFF180050

- - Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_20_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[4]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[4]- (NAND - ata Bus) - PSU_IOU_SLCR_MIO_PIN_20_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8 - bit Data bus) 2= test_scan, Input, test_scan_in[20]- (Test Scan Port) = test_scan, Output, test_scan_out[20]- (Test Scan Port - 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper) - PSU_IOU_SLCR_MIO_PIN_20_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[20]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[20]- (GPIO bank 0) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= t - c1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Used - PSU_IOU_SLCR_MIO_PIN_20_L3_SEL 6 - - Configures MIO Pin 20 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180050, 0x000000FEU ,0x000000C0U) - RegMask = (IOU_SLCR_MIO_PIN_20_L0_SEL_MASK | IOU_SLCR_MIO_PIN_20_L1_SEL_MASK | IOU_SLCR_MIO_PIN_20_L2_SEL_MASK | IOU_SLCR_MIO_PIN_20_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_20_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_20_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_20_L2_SEL_SHIFT - | 0x00000006U << IOU_SLCR_MIO_PIN_20_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_20_OFFSET ,0x000000FEU ,0x000000C0U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_21 @ 0XFF180054

- - Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_21_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[5]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[5]- (NAND - ata Bus) - PSU_IOU_SLCR_MIO_PIN_21_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Comman - Indicator) 2= test_scan, Input, test_scan_in[21]- (Test Scan Port) = test_scan, Output, test_scan_out[21]- (Test Scan Port) - = csu, Input, csu_ext_tamper- (CSU Ext Tamper) - PSU_IOU_SLCR_MIO_PIN_21_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[21]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[21]- (GPIO bank 0) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1 - Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- - UART receiver serial input) 7= Not Used - PSU_IOU_SLCR_MIO_PIN_21_L3_SEL 6 - - Configures MIO Pin 21 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180054, 0x000000FEU ,0x000000C0U) - RegMask = (IOU_SLCR_MIO_PIN_21_L0_SEL_MASK | IOU_SLCR_MIO_PIN_21_L1_SEL_MASK | IOU_SLCR_MIO_PIN_21_L2_SEL_MASK | IOU_SLCR_MIO_PIN_21_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_21_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_21_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_21_L2_SEL_SHIFT - | 0x00000006U << IOU_SLCR_MIO_PIN_21_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_21_OFFSET ,0x000000FEU ,0x000000C0U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_22 @ 0XFF180058

- - Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_22_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_we_b- (NAND Write Enable) - PSU_IOU_SLCR_MIO_PIN_22_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= test_scan, Input, test_scan_in[22]- - (Test Scan Port) = test_scan, Output, test_scan_out[22]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper) - PSU_IOU_SLCR_MIO_PIN_22_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[22]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[22]- (GPIO bank 0) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, sp - 1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not - sed - PSU_IOU_SLCR_MIO_PIN_22_L3_SEL 0 - - Configures MIO Pin 22 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180058, 0x000000FEU ,0x00000000U) - RegMask = (IOU_SLCR_MIO_PIN_22_L0_SEL_MASK | IOU_SLCR_MIO_PIN_22_L1_SEL_MASK | IOU_SLCR_MIO_PIN_22_L2_SEL_MASK | IOU_SLCR_MIO_PIN_22_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_22_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_22_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_22_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_22_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_22_OFFSET ,0x000000FEU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_23 @ 0XFF18005C

- - Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_23_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[6]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[6]- (NAND - ata Bus) - PSU_IOU_SLCR_MIO_PIN_23_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= test_scan, Input, test_scan_in - 23]- (Test Scan Port) = test_scan, Output, test_scan_out[23]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper - - PSU_IOU_SLCR_MIO_PIN_23_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[23]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[23]- (GPIO bank 0) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s - i1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o - tput) 7= Not Used - PSU_IOU_SLCR_MIO_PIN_23_L3_SEL 0 - - Configures MIO Pin 23 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF18005C, 0x000000FEU ,0x00000000U) - RegMask = (IOU_SLCR_MIO_PIN_23_L0_SEL_MASK | IOU_SLCR_MIO_PIN_23_L1_SEL_MASK | IOU_SLCR_MIO_PIN_23_L2_SEL_MASK | IOU_SLCR_MIO_PIN_23_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_23_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_23_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_23_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_23_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_23_OFFSET ,0x000000FEU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_24 @ 0XFF180060

- - Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_24_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[7]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[7]- (NAND - ata Bus) - PSU_IOU_SLCR_MIO_PIN_24_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= test_scan, Input, test - scan_in[24]- (Test Scan Port) = test_scan, Output, test_scan_out[24]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ex - Tamper) - PSU_IOU_SLCR_MIO_PIN_24_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[24]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[24]- (GPIO bank 0) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= Not Used 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, - Output, ua1_txd- (UART transmitter serial output) 7= Not Used - PSU_IOU_SLCR_MIO_PIN_24_L3_SEL 1 - - Configures MIO Pin 24 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180060, 0x000000FEU ,0x00000020U) - RegMask = (IOU_SLCR_MIO_PIN_24_L0_SEL_MASK | IOU_SLCR_MIO_PIN_24_L1_SEL_MASK | IOU_SLCR_MIO_PIN_24_L2_SEL_MASK | IOU_SLCR_MIO_PIN_24_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_24_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_24_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_24_L2_SEL_SHIFT - | 0x00000001U << IOU_SLCR_MIO_PIN_24_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_24_OFFSET ,0x000000FEU ,0x00000020U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_25 @ 0XFF180064

- - Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_25_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_re_n- (NAND Read Enable) - PSU_IOU_SLCR_MIO_PIN_25_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= test_scan, Input, - test_scan_in[25]- (Test Scan Port) = test_scan, Output, test_scan_out[25]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (C - U Ext Tamper) - PSU_IOU_SLCR_MIO_PIN_25_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[25]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[25]- (GPIO bank 0) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= Not Used 5= ttc3, Output, ttc3_wave_out- (TTC Waveform - lock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used - PSU_IOU_SLCR_MIO_PIN_25_L3_SEL 1 - - Configures MIO Pin 25 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180064, 0x000000FEU ,0x00000020U) - RegMask = (IOU_SLCR_MIO_PIN_25_L0_SEL_MASK | IOU_SLCR_MIO_PIN_25_L1_SEL_MASK | IOU_SLCR_MIO_PIN_25_L2_SEL_MASK | IOU_SLCR_MIO_PIN_25_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_25_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_25_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_25_L2_SEL_SHIFT - | 0x00000001U << IOU_SLCR_MIO_PIN_25_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_25_OFFSET ,0x000000FEU ,0x00000020U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_26 @ 0XFF180068

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_clk- (TX RGMII clock) - PSU_IOU_SLCR_MIO_PIN_26_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NAND chip enable) - PSU_IOU_SLCR_MIO_PIN_26_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[0]- (PMU GPI) 2= test_scan, Input, test_scan_in[26]- (Test Sc - n Port) = test_scan, Output, test_scan_out[26]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper) - PSU_IOU_SLCR_MIO_PIN_26_L2_SEL 0 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[0]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[0]- (GPIO bank 1) 1= can - , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal - 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Clock - 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- - Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_26_L3_SEL 0 - - Configures MIO Pin 26 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180068, 0x000000FEU ,0x00000000U) - RegMask = (IOU_SLCR_MIO_PIN_26_L0_SEL_MASK | IOU_SLCR_MIO_PIN_26_L1_SEL_MASK | IOU_SLCR_MIO_PIN_26_L2_SEL_MASK | IOU_SLCR_MIO_PIN_26_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_26_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_26_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_26_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_26_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_26_OFFSET ,0x000000FEU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_27 @ 0XFF18006C

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[0]- (TX RGMII data) - PSU_IOU_SLCR_MIO_PIN_27_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (NAND Ready/Busy) - PSU_IOU_SLCR_MIO_PIN_27_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[1]- (PMU GPI) 2= test_scan, Input, test_scan_in[27]- (Test Sc - n Port) = test_scan, Output, test_scan_out[27]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Outp - t, dp_aux_data_out- (Dp Aux Data) - PSU_IOU_SLCR_MIO_PIN_27_L2_SEL 3 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[1]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[1]- (GPIO bank 1) 1= can - , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa - ) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_ - ut- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port - atabus) - PSU_IOU_SLCR_MIO_PIN_27_L3_SEL 0 - - Configures MIO Pin 27 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF18006C, 0x000000FEU ,0x00000018U) - RegMask = (IOU_SLCR_MIO_PIN_27_L0_SEL_MASK | IOU_SLCR_MIO_PIN_27_L1_SEL_MASK | IOU_SLCR_MIO_PIN_27_L2_SEL_MASK | IOU_SLCR_MIO_PIN_27_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_27_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_27_L1_SEL_SHIFT - | 0x00000003U << IOU_SLCR_MIO_PIN_27_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_27_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_27_OFFSET ,0x000000FEU ,0x00000018U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_28 @ 0XFF180070

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[1]- (TX RGMII data) - PSU_IOU_SLCR_MIO_PIN_28_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (NAND Ready/Busy) - PSU_IOU_SLCR_MIO_PIN_28_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[2]- (PMU GPI) 2= test_scan, Input, test_scan_in[28]- (Test Sc - n Port) = test_scan, Output, test_scan_out[28]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug) - PSU_IOU_SLCR_MIO_PIN_28_L2_SEL 3 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[2]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[2]- (GPIO bank 1) 1= can - , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa - ) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc1, Input, ttc1_clk_i - - (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_28_L3_SEL 0 - - Configures MIO Pin 28 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180070, 0x000000FEU ,0x00000018U) - RegMask = (IOU_SLCR_MIO_PIN_28_L0_SEL_MASK | IOU_SLCR_MIO_PIN_28_L1_SEL_MASK | IOU_SLCR_MIO_PIN_28_L2_SEL_MASK | IOU_SLCR_MIO_PIN_28_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_28_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_28_L1_SEL_SHIFT - | 0x00000003U << IOU_SLCR_MIO_PIN_28_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_28_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_28_OFFSET ,0x000000FEU ,0x00000018U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_29 @ 0XFF180074

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[2]- (TX RGMII data) - PSU_IOU_SLCR_MIO_PIN_29_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal) - PSU_IOU_SLCR_MIO_PIN_29_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[3]- (PMU GPI) 2= test_scan, Input, test_scan_in[29]- (Test Sc - n Port) = test_scan, Output, test_scan_out[29]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Outp - t, dp_aux_data_out- (Dp Aux Data) - PSU_IOU_SLCR_MIO_PIN_29_L2_SEL 3 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[3]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[3]- (GPIO bank 1) 1= can - , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal - 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0] - (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial inpu - ) 7= trace, Output, tracedq[7]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_29_L3_SEL 0 - - Configures MIO Pin 29 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180074, 0x000000FEU ,0x00000018U) - RegMask = (IOU_SLCR_MIO_PIN_29_L0_SEL_MASK | IOU_SLCR_MIO_PIN_29_L1_SEL_MASK | IOU_SLCR_MIO_PIN_29_L2_SEL_MASK | IOU_SLCR_MIO_PIN_29_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_29_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_29_L1_SEL_SHIFT - | 0x00000003U << IOU_SLCR_MIO_PIN_29_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_29_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_29_OFFSET ,0x000000FEU ,0x00000018U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_30 @ 0XFF180078

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[3]- (TX RGMII data) - PSU_IOU_SLCR_MIO_PIN_30_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal) - PSU_IOU_SLCR_MIO_PIN_30_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[4]- (PMU GPI) 2= test_scan, Input, test_scan_in[30]- (Test Sc - n Port) = test_scan, Output, test_scan_out[30]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug) - PSU_IOU_SLCR_MIO_PIN_30_L2_SEL 3 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[4]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[4]- (GPIO bank 1) 1= can - , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal - 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_so - (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output - tracedq[8]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_30_L3_SEL 0 - - Configures MIO Pin 30 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180078, 0x000000FEU ,0x00000018U) - RegMask = (IOU_SLCR_MIO_PIN_30_L0_SEL_MASK | IOU_SLCR_MIO_PIN_30_L1_SEL_MASK | IOU_SLCR_MIO_PIN_30_L2_SEL_MASK | IOU_SLCR_MIO_PIN_30_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_30_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_30_L1_SEL_SHIFT - | 0x00000003U << IOU_SLCR_MIO_PIN_30_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_30_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_30_OFFSET ,0x000000FEU ,0x00000018U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_31 @ 0XFF18007C

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ctl- (TX RGMII control) - PSU_IOU_SLCR_MIO_PIN_31_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal) - PSU_IOU_SLCR_MIO_PIN_31_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[5]- (PMU GPI) 2= test_scan, Input, test_scan_in[31]- (Test Sc - n Port) = test_scan, Output, test_scan_out[31]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper) - PSU_IOU_SLCR_MIO_PIN_31_L2_SEL 0 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[5]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[5]- (GPIO bank 1) 1= can - , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa - ) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi - _si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial out - ut) 7= trace, Output, tracedq[9]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_31_L3_SEL 0 - - Configures MIO Pin 31 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF18007C, 0x000000FEU ,0x00000000U) - RegMask = (IOU_SLCR_MIO_PIN_31_L0_SEL_MASK | IOU_SLCR_MIO_PIN_31_L1_SEL_MASK | IOU_SLCR_MIO_PIN_31_L2_SEL_MASK | IOU_SLCR_MIO_PIN_31_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_31_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_31_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_31_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_31_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_31_OFFSET ,0x000000FEU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_32 @ 0XFF180080

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_clk- (RX RGMII clock) - PSU_IOU_SLCR_MIO_PIN_32_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NAND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe - - PSU_IOU_SLCR_MIO_PIN_32_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[0]- (PMU GPI) 2= test_scan, Input, test_scan_in[32]- (Test S - an Port) = test_scan, Output, test_scan_out[32]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper) - PSU_IOU_SLCR_MIO_PIN_32_L2_SEL 1 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[6]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[6]- (GPIO bank 1) 1= can - , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa - ) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi - _sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= - race, Output, tracedq[10]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_32_L3_SEL 0 - - Configures MIO Pin 32 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180080, 0x000000FEU ,0x00000008U) - RegMask = (IOU_SLCR_MIO_PIN_32_L0_SEL_MASK | IOU_SLCR_MIO_PIN_32_L1_SEL_MASK | IOU_SLCR_MIO_PIN_32_L2_SEL_MASK | IOU_SLCR_MIO_PIN_32_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_32_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_32_L1_SEL_SHIFT - | 0x00000001U << IOU_SLCR_MIO_PIN_32_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_32_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_32_OFFSET ,0x000000FEU ,0x00000008U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_33 @ 0XFF180084

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[0]- (RX RGMII data) - PSU_IOU_SLCR_MIO_PIN_33_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal) - PSU_IOU_SLCR_MIO_PIN_33_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[1]- (PMU GPI) 2= test_scan, Input, test_scan_in[33]- (Test S - an Port) = test_scan, Output, test_scan_out[33]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper) - PSU_IOU_SLCR_MIO_PIN_33_L2_SEL 1 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[7]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[7]- (GPIO bank 1) 1= can - , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal - 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= t - c3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, traced - [11]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_33_L3_SEL 0 - - Configures MIO Pin 33 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180084, 0x000000FEU ,0x00000008U) - RegMask = (IOU_SLCR_MIO_PIN_33_L0_SEL_MASK | IOU_SLCR_MIO_PIN_33_L1_SEL_MASK | IOU_SLCR_MIO_PIN_33_L2_SEL_MASK | IOU_SLCR_MIO_PIN_33_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_33_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_33_L1_SEL_SHIFT - | 0x00000001U << IOU_SLCR_MIO_PIN_33_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_33_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_33_OFFSET ,0x000000FEU ,0x00000008U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_34 @ 0XFF180088

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[1]- (RX RGMII data) - PSU_IOU_SLCR_MIO_PIN_34_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal) - PSU_IOU_SLCR_MIO_PIN_34_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[2]- (PMU GPI) 2= test_scan, Input, test_scan_in[34]- (Test S - an Port) = test_scan, Output, test_scan_out[34]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Out - ut, dp_aux_data_out- (Dp Aux Data) - PSU_IOU_SLCR_MIO_PIN_34_L2_SEL 1 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[8]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[8]- (GPIO bank 1) 1= can - , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal - 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc2 - Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace P - rt Databus) - PSU_IOU_SLCR_MIO_PIN_34_L3_SEL 0 - - Configures MIO Pin 34 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180088, 0x000000FEU ,0x00000008U) - RegMask = (IOU_SLCR_MIO_PIN_34_L0_SEL_MASK | IOU_SLCR_MIO_PIN_34_L1_SEL_MASK | IOU_SLCR_MIO_PIN_34_L2_SEL_MASK | IOU_SLCR_MIO_PIN_34_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_34_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_34_L1_SEL_SHIFT - | 0x00000001U << IOU_SLCR_MIO_PIN_34_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_34_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_34_OFFSET ,0x000000FEU ,0x00000008U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_35 @ 0XFF18008C

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[2]- (RX RGMII data) - PSU_IOU_SLCR_MIO_PIN_35_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal) - PSU_IOU_SLCR_MIO_PIN_35_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[3]- (PMU GPI) 2= test_scan, Input, test_scan_in[35]- (Test S - an Port) = test_scan, Output, test_scan_out[35]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug) - PSU_IOU_SLCR_MIO_PIN_35_L2_SEL 1 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[9]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[9]- (GPIO bank 1) 1= can - , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa - ) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, - Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- - UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_35_L3_SEL 0 - - Configures MIO Pin 35 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF18008C, 0x000000FEU ,0x00000008U) - RegMask = (IOU_SLCR_MIO_PIN_35_L0_SEL_MASK | IOU_SLCR_MIO_PIN_35_L1_SEL_MASK | IOU_SLCR_MIO_PIN_35_L2_SEL_MASK | IOU_SLCR_MIO_PIN_35_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_35_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_35_L1_SEL_SHIFT - | 0x00000001U << IOU_SLCR_MIO_PIN_35_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_35_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_35_OFFSET ,0x000000FEU ,0x00000008U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_36 @ 0XFF180090

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[3]- (RX RGMII data) - PSU_IOU_SLCR_MIO_PIN_36_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal) - PSU_IOU_SLCR_MIO_PIN_36_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[4]- (PMU GPI) 2= test_scan, Input, test_scan_in[36]- (Test S - an Port) = test_scan, Output, test_scan_out[36]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Out - ut, dp_aux_data_out- (Dp Aux Data) - PSU_IOU_SLCR_MIO_PIN_36_L2_SEL 1 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[10]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[10]- (GPIO bank 1) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1 - so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace - Output, tracedq[14]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_36_L3_SEL 0 - - Configures MIO Pin 36 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180090, 0x000000FEU ,0x00000008U) - RegMask = (IOU_SLCR_MIO_PIN_36_L0_SEL_MASK | IOU_SLCR_MIO_PIN_36_L1_SEL_MASK | IOU_SLCR_MIO_PIN_36_L2_SEL_MASK | IOU_SLCR_MIO_PIN_36_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_36_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_36_L1_SEL_SHIFT - | 0x00000001U << IOU_SLCR_MIO_PIN_36_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_36_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_36_OFFSET ,0x000000FEU ,0x00000008U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_37 @ 0XFF180094

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_ctl- (RX RGMII control ) - PSU_IOU_SLCR_MIO_PIN_37_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal) - PSU_IOU_SLCR_MIO_PIN_37_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[5]- (PMU GPI) 2= test_scan, Input, test_scan_in[37]- (Test S - an Port) = test_scan, Output, test_scan_out[37]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug) - PSU_IOU_SLCR_MIO_PIN_37_L2_SEL 1 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[11]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[11]- (GPIO bank 1) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, sp - 1_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) - 7= trace, Output, tracedq[15]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_37_L3_SEL 0 - - Configures MIO Pin 37 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180094, 0x000000FEU ,0x00000008U) - RegMask = (IOU_SLCR_MIO_PIN_37_L0_SEL_MASK | IOU_SLCR_MIO_PIN_37_L1_SEL_MASK | IOU_SLCR_MIO_PIN_37_L2_SEL_MASK | IOU_SLCR_MIO_PIN_37_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_37_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_37_L1_SEL_SHIFT - | 0x00000001U << IOU_SLCR_MIO_PIN_37_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_37_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_37_OFFSET ,0x000000FEU ,0x00000008U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_38 @ 0XFF180098

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_clk- (TX RGMII clock) - PSU_IOU_SLCR_MIO_PIN_38_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_38_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= Not Used 3= Not Used - PSU_IOU_SLCR_MIO_PIN_38_L2_SEL 0 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[12]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[12]- (GPIO bank 1) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Clo - k) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, trace_clk- - (Trace Port Clock) - PSU_IOU_SLCR_MIO_PIN_38_L3_SEL 0 - - Configures MIO Pin 38 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180098, 0x000000FEU ,0x00000000U) - RegMask = (IOU_SLCR_MIO_PIN_38_L0_SEL_MASK | IOU_SLCR_MIO_PIN_38_L1_SEL_MASK | IOU_SLCR_MIO_PIN_38_L2_SEL_MASK | IOU_SLCR_MIO_PIN_38_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_38_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_38_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_38_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_38_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_38_OFFSET ,0x000000FEU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_39 @ 0XFF18009C

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[0]- (TX RGMII data) - PSU_IOU_SLCR_MIO_PIN_39_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_39_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= sd1, Input, sd1_data_i - [4]- (8-bit Data bus) = sd1, Output, sdio1_data_out[4]- (8-bit Data bus) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_39_L2_SEL 0 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[13]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[13]- (GPIO bank 1) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc0, Output, ttc0_wav - _out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, trace_ctl- (Trace Port - Control Signal) - PSU_IOU_SLCR_MIO_PIN_39_L3_SEL 0 - - Configures MIO Pin 39 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF18009C, 0x000000FEU ,0x00000000U) - RegMask = (IOU_SLCR_MIO_PIN_39_L0_SEL_MASK | IOU_SLCR_MIO_PIN_39_L1_SEL_MASK | IOU_SLCR_MIO_PIN_39_L2_SEL_MASK | IOU_SLCR_MIO_PIN_39_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_39_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_39_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_39_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_39_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_39_OFFSET ,0x000000FEU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_40 @ 0XFF1800A0

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[1]- (TX RGMII data) - PSU_IOU_SLCR_MIO_PIN_40_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_40_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Comman - Indicator) 2= sd1, Input, sd1_data_in[5]- (8-bit Data bus) = sd1, Output, sdio1_data_out[5]- (8-bit Data bus) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_40_L2_SEL 0 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[14]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[14]- (GPIO bank 1) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc3, Input, ttc3_clk - in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[0]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_40_L3_SEL 0 - - Configures MIO Pin 40 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800A0, 0x000000FEU ,0x00000000U) - RegMask = (IOU_SLCR_MIO_PIN_40_L0_SEL_MASK | IOU_SLCR_MIO_PIN_40_L1_SEL_MASK | IOU_SLCR_MIO_PIN_40_L2_SEL_MASK | IOU_SLCR_MIO_PIN_40_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_40_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_40_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_40_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_40_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_40_OFFSET ,0x000000FEU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_41 @ 0XFF1800A4

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[2]- (TX RGMII data) - PSU_IOU_SLCR_MIO_PIN_41_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_41_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8 - bit Data bus) 2= sd1, Input, sd1_data_in[6]- (8-bit Data bus) = sd1, Output, sdio1_data_out[6]- (8-bit Data bus) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_41_L2_SEL 0 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[15]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[15]- (GPIO bank 1) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[ - ]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial in - ut) 7= trace, Output, tracedq[1]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_41_L3_SEL 0 - - Configures MIO Pin 41 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800A4, 0x000000FEU ,0x00000000U) - RegMask = (IOU_SLCR_MIO_PIN_41_L0_SEL_MASK | IOU_SLCR_MIO_PIN_41_L1_SEL_MASK | IOU_SLCR_MIO_PIN_41_L2_SEL_MASK | IOU_SLCR_MIO_PIN_41_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_41_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_41_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_41_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_41_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_41_OFFSET ,0x000000FEU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_42 @ 0XFF1800A8

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[3]- (TX RGMII data) - PSU_IOU_SLCR_MIO_PIN_42_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_42_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8 - bit Data bus) 2= sd1, Input, sd1_data_in[7]- (8-bit Data bus) = sd1, Output, sdio1_data_out[7]- (8-bit Data bus) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_42_L2_SEL 0 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_ - o- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outp - t, tracedq[2]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_42_L3_SEL 0 - - Configures MIO Pin 42 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800A8, 0x000000FEU ,0x00000000U) - RegMask = (IOU_SLCR_MIO_PIN_42_L0_SEL_MASK | IOU_SLCR_MIO_PIN_42_L1_SEL_MASK | IOU_SLCR_MIO_PIN_42_L2_SEL_MASK | IOU_SLCR_MIO_PIN_42_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_42_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_42_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_42_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_42_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_42_OFFSET ,0x000000FEU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_43 @ 0XFF1800AC

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ctl- (TX RGMII control) - PSU_IOU_SLCR_MIO_PIN_43_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_43_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8 - bit Data bus) 2= sd1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_43_L2_SEL 2 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, s - i0_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o - tput) 7= trace, Output, tracedq[3]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_43_L3_SEL 0 - - Configures MIO Pin 43 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800AC, 0x000000FEU ,0x00000010U) - RegMask = (IOU_SLCR_MIO_PIN_43_L0_SEL_MASK | IOU_SLCR_MIO_PIN_43_L1_SEL_MASK | IOU_SLCR_MIO_PIN_43_L2_SEL_MASK | IOU_SLCR_MIO_PIN_43_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_43_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_43_L1_SEL_SHIFT - | 0x00000002U << IOU_SLCR_MIO_PIN_43_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_43_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_43_OFFSET ,0x000000FEU ,0x00000010U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_44 @ 0XFF1800B0

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_clk- (RX RGMII clock) - PSU_IOU_SLCR_MIO_PIN_44_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_44_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8 - bit Data bus) 2= sd1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_44_L2_SEL 2 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[18]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[18]- (GPIO bank 1) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, s - i1_sclk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7 - Not Used - PSU_IOU_SLCR_MIO_PIN_44_L3_SEL 0 - - Configures MIO Pin 44 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800B0, 0x000000FEU ,0x00000010U) - RegMask = (IOU_SLCR_MIO_PIN_44_L0_SEL_MASK | IOU_SLCR_MIO_PIN_44_L1_SEL_MASK | IOU_SLCR_MIO_PIN_44_L2_SEL_MASK | IOU_SLCR_MIO_PIN_44_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_44_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_44_L1_SEL_SHIFT - | 0x00000002U << IOU_SLCR_MIO_PIN_44_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_44_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_44_OFFSET ,0x000000FEU ,0x00000010U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_45 @ 0XFF1800B4

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[0]- (RX RGMII data) - PSU_IOU_SLCR_MIO_PIN_45_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_45_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8 - bit Data bus) 2= sd1, Input, sdio1_cd_n- (SD card detect from connector) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_45_L2_SEL 2 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[19]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[19]- (GPIO bank 1) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= - ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used - PSU_IOU_SLCR_MIO_PIN_45_L3_SEL 0 - - Configures MIO Pin 45 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800B4, 0x000000FEU ,0x00000010U) - RegMask = (IOU_SLCR_MIO_PIN_45_L0_SEL_MASK | IOU_SLCR_MIO_PIN_45_L1_SEL_MASK | IOU_SLCR_MIO_PIN_45_L2_SEL_MASK | IOU_SLCR_MIO_PIN_45_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_45_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_45_L1_SEL_SHIFT - | 0x00000002U << IOU_SLCR_MIO_PIN_45_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_45_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_45_OFFSET ,0x000000FEU ,0x00000010U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_46 @ 0XFF1800B8

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[1]- (RX RGMII data) - PSU_IOU_SLCR_MIO_PIN_46_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_46_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8 - bit Data bus) 2= sd1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_out[0]- (8-bit Data bus) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_46_L2_SEL 2 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= tt - 0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used - PSU_IOU_SLCR_MIO_PIN_46_L3_SEL 0 - - Configures MIO Pin 46 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800B8, 0x000000FEU ,0x00000010U) - RegMask = (IOU_SLCR_MIO_PIN_46_L0_SEL_MASK | IOU_SLCR_MIO_PIN_46_L1_SEL_MASK | IOU_SLCR_MIO_PIN_46_L2_SEL_MASK | IOU_SLCR_MIO_PIN_46_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_46_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_46_L1_SEL_SHIFT - | 0x00000002U << IOU_SLCR_MIO_PIN_46_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_46_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_46_OFFSET ,0x000000FEU ,0x00000010U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_47 @ 0XFF1800BC

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[2]- (RX RGMII data) - PSU_IOU_SLCR_MIO_PIN_47_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_47_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8 - bit Data bus) 2= sd1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_out[1]- (8-bit Data bus) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_47_L2_SEL 2 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi - , Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd - (UART transmitter serial output) 7= Not Used - PSU_IOU_SLCR_MIO_PIN_47_L3_SEL 0 - - Configures MIO Pin 47 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800BC, 0x000000FEU ,0x00000010U) - RegMask = (IOU_SLCR_MIO_PIN_47_L0_SEL_MASK | IOU_SLCR_MIO_PIN_47_L1_SEL_MASK | IOU_SLCR_MIO_PIN_47_L2_SEL_MASK | IOU_SLCR_MIO_PIN_47_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_47_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_47_L1_SEL_SHIFT - | 0x00000002U << IOU_SLCR_MIO_PIN_47_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_47_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_47_OFFSET ,0x000000FEU ,0x00000010U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_48 @ 0XFF1800C0

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[3]- (RX RGMII data) - PSU_IOU_SLCR_MIO_PIN_48_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_48_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8 - bit Data bus) 2= sd1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_out[2]- (8-bit Data bus) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_48_L2_SEL 2 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[22]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[22]- (GPIO bank 1) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1 - so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not U - ed - PSU_IOU_SLCR_MIO_PIN_48_L3_SEL 0 - - Configures MIO Pin 48 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800C0, 0x000000FEU ,0x00000010U) - RegMask = (IOU_SLCR_MIO_PIN_48_L0_SEL_MASK | IOU_SLCR_MIO_PIN_48_L1_SEL_MASK | IOU_SLCR_MIO_PIN_48_L2_SEL_MASK | IOU_SLCR_MIO_PIN_48_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_48_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_48_L1_SEL_SHIFT - | 0x00000002U << IOU_SLCR_MIO_PIN_48_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_48_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_48_OFFSET ,0x000000FEU ,0x00000010U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_49 @ 0XFF1800C4

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_ctl- (RX RGMII control ) - PSU_IOU_SLCR_MIO_PIN_49_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_49_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= sd1, Input, sd1_data_in[3]- (8 - bit Data bus) = sd1, Output, sdio1_data_out[3]- (8-bit Data bus) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_49_L2_SEL 2 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[23]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[23]- (GPIO bank 1) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, sp - 1_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) - 7= Not Used - PSU_IOU_SLCR_MIO_PIN_49_L3_SEL 0 - - Configures MIO Pin 49 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800C4, 0x000000FEU ,0x00000010U) - RegMask = (IOU_SLCR_MIO_PIN_49_L0_SEL_MASK | IOU_SLCR_MIO_PIN_49_L1_SEL_MASK | IOU_SLCR_MIO_PIN_49_L2_SEL_MASK | IOU_SLCR_MIO_PIN_49_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_49_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_49_L1_SEL_SHIFT - | 0x00000002U << IOU_SLCR_MIO_PIN_49_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_49_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_49_OFFSET ,0x000000FEU ,0x00000010U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_50 @ 0XFF1800C8

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- (TSU clock) - PSU_IOU_SLCR_MIO_PIN_50_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_50_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= sd1, Input, sd1_c - d_in- (Command Indicator) = sd1, Output, sdio1_cmd_out- (Command Indicator) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_50_L2_SEL 2 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[24]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[24]- (GPIO bank 1) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= ttc2, Input, ttc2 - clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used - PSU_IOU_SLCR_MIO_PIN_50_L3_SEL 0 - - Configures MIO Pin 50 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800C8, 0x000000FEU ,0x00000010U) - RegMask = (IOU_SLCR_MIO_PIN_50_L0_SEL_MASK | IOU_SLCR_MIO_PIN_50_L1_SEL_MASK | IOU_SLCR_MIO_PIN_50_L2_SEL_MASK | IOU_SLCR_MIO_PIN_50_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_50_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_50_L1_SEL_SHIFT - | 0x00000002U << IOU_SLCR_MIO_PIN_50_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_50_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_50_OFFSET ,0x000000FEU ,0x00000010U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_51 @ 0XFF1800CC

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- (TSU clock) - PSU_IOU_SLCR_MIO_PIN_51_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_51_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Output, sdio1_clk_out- (SDSDIO clock) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_51_L2_SEL 2 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[25]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[25]- (GPIO bank 1) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= mdio1, Input, gem1_mdio_in- (MDIO Data) 4= mdio1, Outp - t, gem1_mdio_out- (MDIO Data) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter - serial output) 7= Not Used - PSU_IOU_SLCR_MIO_PIN_51_L3_SEL 0 - - Configures MIO Pin 51 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800CC, 0x000000FEU ,0x00000010U) - RegMask = (IOU_SLCR_MIO_PIN_51_L0_SEL_MASK | IOU_SLCR_MIO_PIN_51_L1_SEL_MASK | IOU_SLCR_MIO_PIN_51_L2_SEL_MASK | IOU_SLCR_MIO_PIN_51_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_51_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_51_L1_SEL_SHIFT - | 0x00000002U << IOU_SLCR_MIO_PIN_51_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_51_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_51_OFFSET ,0x000000FEU ,0x00000010U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_52 @ 0XFF1800D0

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_clk- (TX RGMII clock) - PSU_IOU_SLCR_MIO_PIN_52_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_clk_in- (ULPI Clock) - PSU_IOU_SLCR_MIO_PIN_52_L1_SEL 1 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used - PSU_IOU_SLCR_MIO_PIN_52_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[0]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[0]- (GPIO bank 2) 1= can - , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa - ) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Cloc - ) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_ - lk- (Trace Port Clock) - PSU_IOU_SLCR_MIO_PIN_52_L3_SEL 0 - - Configures MIO Pin 52 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800D0, 0x000000FEU ,0x00000004U) - RegMask = (IOU_SLCR_MIO_PIN_52_L0_SEL_MASK | IOU_SLCR_MIO_PIN_52_L1_SEL_MASK | IOU_SLCR_MIO_PIN_52_L2_SEL_MASK | IOU_SLCR_MIO_PIN_52_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_52_L0_SEL_SHIFT - | 0x00000001U << IOU_SLCR_MIO_PIN_52_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_52_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_52_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_52_OFFSET ,0x000000FEU ,0x00000004U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_53 @ 0XFF1800D4

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[0]- (TX RGMII data) - PSU_IOU_SLCR_MIO_PIN_53_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_dir- (Data bus direction control) - PSU_IOU_SLCR_MIO_PIN_53_L1_SEL 1 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used - PSU_IOU_SLCR_MIO_PIN_53_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[1]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[1]- (GPIO bank 2) 1= can - , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal - 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_o - t- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control - Signal) - PSU_IOU_SLCR_MIO_PIN_53_L3_SEL 0 - - Configures MIO Pin 53 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800D4, 0x000000FEU ,0x00000004U) - RegMask = (IOU_SLCR_MIO_PIN_53_L0_SEL_MASK | IOU_SLCR_MIO_PIN_53_L1_SEL_MASK | IOU_SLCR_MIO_PIN_53_L2_SEL_MASK | IOU_SLCR_MIO_PIN_53_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_53_L0_SEL_SHIFT - | 0x00000001U << IOU_SLCR_MIO_PIN_53_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_53_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_53_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_53_OFFSET ,0x000000FEU ,0x00000004U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_54 @ 0XFF1800D8

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[1]- (TX RGMII data) - PSU_IOU_SLCR_MIO_PIN_54_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[2]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_ - ata[2]- (ULPI data bus) - PSU_IOU_SLCR_MIO_PIN_54_L1_SEL 1 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used - PSU_IOU_SLCR_MIO_PIN_54_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[2]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[2]- (GPIO bank 2) 1= can - , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal - 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, Input, ttc0_clk_in - (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[0]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_54_L3_SEL 0 - - Configures MIO Pin 54 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800D8, 0x000000FEU ,0x00000004U) - RegMask = (IOU_SLCR_MIO_PIN_54_L0_SEL_MASK | IOU_SLCR_MIO_PIN_54_L1_SEL_MASK | IOU_SLCR_MIO_PIN_54_L2_SEL_MASK | IOU_SLCR_MIO_PIN_54_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_54_L0_SEL_SHIFT - | 0x00000001U << IOU_SLCR_MIO_PIN_54_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_54_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_54_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_54_OFFSET ,0x000000FEU ,0x00000004U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_55 @ 0XFF1800DC

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[2]- (TX RGMII data) - PSU_IOU_SLCR_MIO_PIN_55_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_nxt- (Data flow control signal from the PHY) - PSU_IOU_SLCR_MIO_PIN_55_L1_SEL 1 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used - PSU_IOU_SLCR_MIO_PIN_55_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[3]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[3]- (GPIO bank 2) 1= can - , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa - ) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0 - - (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial - output) 7= trace, Output, tracedq[1]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_55_L3_SEL 0 - - Configures MIO Pin 55 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800DC, 0x000000FEU ,0x00000004U) - RegMask = (IOU_SLCR_MIO_PIN_55_L0_SEL_MASK | IOU_SLCR_MIO_PIN_55_L1_SEL_MASK | IOU_SLCR_MIO_PIN_55_L2_SEL_MASK | IOU_SLCR_MIO_PIN_55_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_55_L0_SEL_SHIFT - | 0x00000001U << IOU_SLCR_MIO_PIN_55_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_55_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_55_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_55_OFFSET ,0x000000FEU ,0x00000004U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_56 @ 0XFF1800E0

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[3]- (TX RGMII data) - PSU_IOU_SLCR_MIO_PIN_56_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[0]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_ - ata[0]- (ULPI data bus) - PSU_IOU_SLCR_MIO_PIN_56_L1_SEL 1 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used - PSU_IOU_SLCR_MIO_PIN_56_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[4]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[4]- (GPIO bank 2) 1= can - , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa - ) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_s - - (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, - utput, tracedq[2]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_56_L3_SEL 0 - - Configures MIO Pin 56 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800E0, 0x000000FEU ,0x00000004U) - RegMask = (IOU_SLCR_MIO_PIN_56_L0_SEL_MASK | IOU_SLCR_MIO_PIN_56_L1_SEL_MASK | IOU_SLCR_MIO_PIN_56_L2_SEL_MASK | IOU_SLCR_MIO_PIN_56_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_56_L0_SEL_SHIFT - | 0x00000001U << IOU_SLCR_MIO_PIN_56_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_56_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_56_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_56_OFFSET ,0x000000FEU ,0x00000004U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_57 @ 0XFF1800E4

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_ctl- (TX RGMII control) - PSU_IOU_SLCR_MIO_PIN_57_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[1]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_ - ata[1]- (ULPI data bus) - PSU_IOU_SLCR_MIO_PIN_57_L1_SEL 1 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used - PSU_IOU_SLCR_MIO_PIN_57_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[5]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[5]- (GPIO bank 2) 1= can - , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal - 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi0 - si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7 - trace, Output, tracedq[3]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_57_L3_SEL 0 - - Configures MIO Pin 57 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800E4, 0x000000FEU ,0x00000004U) - RegMask = (IOU_SLCR_MIO_PIN_57_L0_SEL_MASK | IOU_SLCR_MIO_PIN_57_L1_SEL_MASK | IOU_SLCR_MIO_PIN_57_L2_SEL_MASK | IOU_SLCR_MIO_PIN_57_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_57_L0_SEL_SHIFT - | 0x00000001U << IOU_SLCR_MIO_PIN_57_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_57_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_57_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_57_OFFSET ,0x000000FEU ,0x00000004U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_58 @ 0XFF1800E8

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_clk- (RX RGMII clock) - PSU_IOU_SLCR_MIO_PIN_58_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Output, usb0_ulpi_stp- (Asserted to end or interrupt transfers) - PSU_IOU_SLCR_MIO_PIN_58_L1_SEL 1 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used - PSU_IOU_SLCR_MIO_PIN_58_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[6]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[6]- (GPIO bank 2) 1= can - , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal - 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1_sclk_out- (SPI Clock - 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- - Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_58_L3_SEL 0 - - Configures MIO Pin 58 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800E8, 0x000000FEU ,0x00000004U) - RegMask = (IOU_SLCR_MIO_PIN_58_L0_SEL_MASK | IOU_SLCR_MIO_PIN_58_L1_SEL_MASK | IOU_SLCR_MIO_PIN_58_L2_SEL_MASK | IOU_SLCR_MIO_PIN_58_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_58_L0_SEL_SHIFT - | 0x00000001U << IOU_SLCR_MIO_PIN_58_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_58_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_58_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_58_OFFSET ,0x000000FEU ,0x00000004U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_59 @ 0XFF1800EC

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[0]- (RX RGMII data) - PSU_IOU_SLCR_MIO_PIN_59_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[3]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_ - ata[3]- (ULPI data bus) - PSU_IOU_SLCR_MIO_PIN_59_L1_SEL 1 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used - PSU_IOU_SLCR_MIO_PIN_59_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[7]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[7]- (GPIO bank 2) 1= can - , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa - ) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_ - ut- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port - atabus) - PSU_IOU_SLCR_MIO_PIN_59_L3_SEL 0 - - Configures MIO Pin 59 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800EC, 0x000000FEU ,0x00000004U) - RegMask = (IOU_SLCR_MIO_PIN_59_L0_SEL_MASK | IOU_SLCR_MIO_PIN_59_L1_SEL_MASK | IOU_SLCR_MIO_PIN_59_L2_SEL_MASK | IOU_SLCR_MIO_PIN_59_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_59_L0_SEL_SHIFT - | 0x00000001U << IOU_SLCR_MIO_PIN_59_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_59_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_59_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_59_OFFSET ,0x000000FEU ,0x00000004U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_60 @ 0XFF1800F0

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[1]- (RX RGMII data) - PSU_IOU_SLCR_MIO_PIN_60_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[4]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_ - ata[4]- (ULPI data bus) - PSU_IOU_SLCR_MIO_PIN_60_L1_SEL 1 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used - PSU_IOU_SLCR_MIO_PIN_60_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[8]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[8]- (GPIO bank 2) 1= can - , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa - ) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc1, Input, ttc1_clk_i - - (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_60_L3_SEL 0 - - Configures MIO Pin 60 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800F0, 0x000000FEU ,0x00000004U) - RegMask = (IOU_SLCR_MIO_PIN_60_L0_SEL_MASK | IOU_SLCR_MIO_PIN_60_L1_SEL_MASK | IOU_SLCR_MIO_PIN_60_L2_SEL_MASK | IOU_SLCR_MIO_PIN_60_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_60_L0_SEL_SHIFT - | 0x00000001U << IOU_SLCR_MIO_PIN_60_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_60_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_60_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_60_OFFSET ,0x000000FEU ,0x00000004U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_61 @ 0XFF1800F4

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[2]- (RX RGMII data) - PSU_IOU_SLCR_MIO_PIN_61_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[5]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_ - ata[5]- (ULPI data bus) - PSU_IOU_SLCR_MIO_PIN_61_L1_SEL 1 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used - PSU_IOU_SLCR_MIO_PIN_61_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[9]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[9]- (GPIO bank 2) 1= can - , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal - 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, Output, spi1_n_ss_out[0] - (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial inpu - ) 7= trace, Output, tracedq[7]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_61_L3_SEL 0 - - Configures MIO Pin 61 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800F4, 0x000000FEU ,0x00000004U) - RegMask = (IOU_SLCR_MIO_PIN_61_L0_SEL_MASK | IOU_SLCR_MIO_PIN_61_L1_SEL_MASK | IOU_SLCR_MIO_PIN_61_L2_SEL_MASK | IOU_SLCR_MIO_PIN_61_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_61_L0_SEL_SHIFT - | 0x00000001U << IOU_SLCR_MIO_PIN_61_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_61_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_61_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_61_OFFSET ,0x000000FEU ,0x00000004U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_62 @ 0XFF1800F8

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[3]- (RX RGMII data) - PSU_IOU_SLCR_MIO_PIN_62_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[6]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_ - ata[6]- (ULPI data bus) - PSU_IOU_SLCR_MIO_PIN_62_L1_SEL 1 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used - PSU_IOU_SLCR_MIO_PIN_62_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[10]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[10]- (GPIO bank 2) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_ - o- (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outp - t, tracedq[8]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_62_L3_SEL 0 - - Configures MIO Pin 62 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800F8, 0x000000FEU ,0x00000004U) - RegMask = (IOU_SLCR_MIO_PIN_62_L0_SEL_MASK | IOU_SLCR_MIO_PIN_62_L1_SEL_MASK | IOU_SLCR_MIO_PIN_62_L2_SEL_MASK | IOU_SLCR_MIO_PIN_62_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_62_L0_SEL_SHIFT - | 0x00000001U << IOU_SLCR_MIO_PIN_62_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_62_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_62_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_62_OFFSET ,0x000000FEU ,0x00000004U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_63 @ 0XFF1800FC

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_ctl- (RX RGMII control ) - PSU_IOU_SLCR_MIO_PIN_63_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[7]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_ - ata[7]- (ULPI data bus) - PSU_IOU_SLCR_MIO_PIN_63_L1_SEL 1 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used - PSU_IOU_SLCR_MIO_PIN_63_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[11]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[11]- (GPIO bank 2) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s - i1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o - tput) 7= trace, Output, tracedq[9]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_63_L3_SEL 0 - - Configures MIO Pin 63 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800FC, 0x000000FEU ,0x00000004U) - RegMask = (IOU_SLCR_MIO_PIN_63_L0_SEL_MASK | IOU_SLCR_MIO_PIN_63_L1_SEL_MASK | IOU_SLCR_MIO_PIN_63_L2_SEL_MASK | IOU_SLCR_MIO_PIN_63_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_63_L0_SEL_SHIFT - | 0x00000001U << IOU_SLCR_MIO_PIN_63_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_63_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_63_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_63_OFFSET ,0x000000FEU ,0x00000004U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_64 @ 0XFF180100

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_clk- (TX RGMII clock) - PSU_IOU_SLCR_MIO_PIN_64_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_clk_in- (ULPI Clock) - PSU_IOU_SLCR_MIO_PIN_64_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= Not Used 3= Not Used - PSU_IOU_SLCR_MIO_PIN_64_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[12]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[12]- (GPIO bank 2) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, s - i0_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7 - trace, Output, tracedq[10]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_64_L3_SEL 0 - - Configures MIO Pin 64 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180100, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_64_L0_SEL_MASK | IOU_SLCR_MIO_PIN_64_L1_SEL_MASK | IOU_SLCR_MIO_PIN_64_L2_SEL_MASK | IOU_SLCR_MIO_PIN_64_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_64_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_64_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_64_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_64_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_64_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_65 @ 0XFF180104

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[0]- (TX RGMII data) - PSU_IOU_SLCR_MIO_PIN_65_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_dir- (Data bus direction control) - PSU_IOU_SLCR_MIO_PIN_65_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= Not Used 3= Not Used - PSU_IOU_SLCR_MIO_PIN_65_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[13]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[13]- (GPIO bank 2) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= - ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trac - dq[11]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_65_L3_SEL 0 - - Configures MIO Pin 65 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180104, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_65_L0_SEL_MASK | IOU_SLCR_MIO_PIN_65_L1_SEL_MASK | IOU_SLCR_MIO_PIN_65_L2_SEL_MASK | IOU_SLCR_MIO_PIN_65_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_65_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_65_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_65_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_65_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_65_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_66 @ 0XFF180108

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[1]- (TX RGMII data) - PSU_IOU_SLCR_MIO_PIN_66_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[2]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_ - ata[2]- (ULPI data bus) - PSU_IOU_SLCR_MIO_PIN_66_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Comman - Indicator) 2= Not Used 3= Not Used - PSU_IOU_SLCR_MIO_PIN_66_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[14]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[14]- (GPIO bank 2) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= tt - 2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace - Port Databus) - PSU_IOU_SLCR_MIO_PIN_66_L3_SEL 0 - - Configures MIO Pin 66 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180108, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_66_L0_SEL_MASK | IOU_SLCR_MIO_PIN_66_L1_SEL_MASK | IOU_SLCR_MIO_PIN_66_L2_SEL_MASK | IOU_SLCR_MIO_PIN_66_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_66_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_66_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_66_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_66_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_66_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_67 @ 0XFF18010C

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[2]- (TX RGMII data) - PSU_IOU_SLCR_MIO_PIN_67_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_nxt- (Data flow control signal from the PHY) - PSU_IOU_SLCR_MIO_PIN_67_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8 - bit Data bus) 2= Not Used 3= Not Used - PSU_IOU_SLCR_MIO_PIN_67_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[15]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[15]- (GPIO bank 2) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi - , Output, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd - (UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_67_L3_SEL 0 - - Configures MIO Pin 67 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF18010C, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_67_L0_SEL_MASK | IOU_SLCR_MIO_PIN_67_L1_SEL_MASK | IOU_SLCR_MIO_PIN_67_L2_SEL_MASK | IOU_SLCR_MIO_PIN_67_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_67_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_67_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_67_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_67_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_67_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_68 @ 0XFF180110

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[3]- (TX RGMII data) - PSU_IOU_SLCR_MIO_PIN_68_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[0]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_ - ata[0]- (ULPI data bus) - PSU_IOU_SLCR_MIO_PIN_68_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8 - bit Data bus) 2= Not Used 3= Not Used - PSU_IOU_SLCR_MIO_PIN_68_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[16]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[16]- (GPIO bank 2) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0 - so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace - Output, tracedq[14]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_68_L3_SEL 0 - - Configures MIO Pin 68 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180110, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_68_L0_SEL_MASK | IOU_SLCR_MIO_PIN_68_L1_SEL_MASK | IOU_SLCR_MIO_PIN_68_L2_SEL_MASK | IOU_SLCR_MIO_PIN_68_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_68_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_68_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_68_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_68_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_68_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_69 @ 0XFF180114

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_ctl- (TX RGMII control) - PSU_IOU_SLCR_MIO_PIN_69_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[1]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_ - ata[1]- (ULPI data bus) - PSU_IOU_SLCR_MIO_PIN_69_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8 - bit Data bus) 2= sd1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_69_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[17]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[17]- (GPIO bank 2) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, sp - 0_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) - 7= trace, Output, tracedq[15]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_69_L3_SEL 0 - - Configures MIO Pin 69 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180114, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_69_L0_SEL_MASK | IOU_SLCR_MIO_PIN_69_L1_SEL_MASK | IOU_SLCR_MIO_PIN_69_L2_SEL_MASK | IOU_SLCR_MIO_PIN_69_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_69_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_69_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_69_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_69_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_69_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_70 @ 0XFF180118

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_clk- (RX RGMII clock) - PSU_IOU_SLCR_MIO_PIN_70_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Output, usb1_ulpi_stp- (Asserted to end or interrupt transfers) - PSU_IOU_SLCR_MIO_PIN_70_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8 - bit Data bus) 2= sd1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_70_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[18]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[18]- (GPIO bank 2) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, sp - 1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not - sed - PSU_IOU_SLCR_MIO_PIN_70_L3_SEL 0 - - Configures MIO Pin 70 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180118, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_70_L0_SEL_MASK | IOU_SLCR_MIO_PIN_70_L1_SEL_MASK | IOU_SLCR_MIO_PIN_70_L2_SEL_MASK | IOU_SLCR_MIO_PIN_70_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_70_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_70_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_70_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_70_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_70_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_71 @ 0XFF18011C

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[0]- (RX RGMII data) - PSU_IOU_SLCR_MIO_PIN_71_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[3]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_ - ata[3]- (ULPI data bus) - PSU_IOU_SLCR_MIO_PIN_71_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8 - bit Data bus) 2= sd1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_out[0]- (8-bit Data bus) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_71_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[19]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[19]- (GPIO bank 2) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5 - ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used - PSU_IOU_SLCR_MIO_PIN_71_L3_SEL 0 - - Configures MIO Pin 71 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF18011C, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_71_L0_SEL_MASK | IOU_SLCR_MIO_PIN_71_L1_SEL_MASK | IOU_SLCR_MIO_PIN_71_L2_SEL_MASK | IOU_SLCR_MIO_PIN_71_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_71_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_71_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_71_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_71_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_71_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_72 @ 0XFF180120

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[1]- (RX RGMII data) - PSU_IOU_SLCR_MIO_PIN_72_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[4]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_ - ata[4]- (ULPI data bus) - PSU_IOU_SLCR_MIO_PIN_72_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8 - bit Data bus) 2= sd1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_out[1]- (8-bit Data bus) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_72_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[20]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[20]- (GPIO bank 2) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= N - t Used 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Used - PSU_IOU_SLCR_MIO_PIN_72_L3_SEL 0 - - Configures MIO Pin 72 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180120, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_72_L0_SEL_MASK | IOU_SLCR_MIO_PIN_72_L1_SEL_MASK | IOU_SLCR_MIO_PIN_72_L2_SEL_MASK | IOU_SLCR_MIO_PIN_72_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_72_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_72_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_72_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_72_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_72_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_73 @ 0XFF180124

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[2]- (RX RGMII data) - PSU_IOU_SLCR_MIO_PIN_73_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_ - ata[5]- (ULPI data bus) - PSU_IOU_SLCR_MIO_PIN_73_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8 - bit Data bus) 2= sd1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_out[2]- (8-bit Data bus) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_73_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[21]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[21]- (GPIO bank 2) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1 - Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= Not Used 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used - PSU_IOU_SLCR_MIO_PIN_73_L3_SEL 0 - - Configures MIO Pin 73 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180124, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_73_L0_SEL_MASK | IOU_SLCR_MIO_PIN_73_L1_SEL_MASK | IOU_SLCR_MIO_PIN_73_L2_SEL_MASK | IOU_SLCR_MIO_PIN_73_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_73_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_73_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_73_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_73_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_73_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_74 @ 0XFF180128

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[3]- (RX RGMII data) - PSU_IOU_SLCR_MIO_PIN_74_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[6]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_ - ata[6]- (ULPI data bus) - PSU_IOU_SLCR_MIO_PIN_74_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8 - bit Data bus) 2= sd1, Input, sd1_data_in[3]- (8-bit Data bus) = sd1, Output, sdio1_data_out[3]- (8-bit Data bus) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_74_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[22]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[22]- (GPIO bank 2) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_ - o- (MISO signal) 5= Not Used 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used - PSU_IOU_SLCR_MIO_PIN_74_L3_SEL 0 - - Configures MIO Pin 74 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180128, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_74_L0_SEL_MASK | IOU_SLCR_MIO_PIN_74_L1_SEL_MASK | IOU_SLCR_MIO_PIN_74_L2_SEL_MASK | IOU_SLCR_MIO_PIN_74_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_74_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_74_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_74_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_74_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_74_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_75 @ 0XFF18012C

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_ctl- (RX RGMII control ) - PSU_IOU_SLCR_MIO_PIN_75_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[7]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_ - ata[7]- (ULPI data bus) - PSU_IOU_SLCR_MIO_PIN_75_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= sd1, Input, sd1_cmd_in- (Comma - d Indicator) = sd1, Output, sdio1_cmd_out- (Command Indicator) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_75_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[23]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[23]- (GPIO bank 2) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s - i1_si- (MOSI signal) 5= Not Used 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used - PSU_IOU_SLCR_MIO_PIN_75_L3_SEL 0 - - Configures MIO Pin 75 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF18012C, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_75_L0_SEL_MASK | IOU_SLCR_MIO_PIN_75_L1_SEL_MASK | IOU_SLCR_MIO_PIN_75_L2_SEL_MASK | IOU_SLCR_MIO_PIN_75_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_75_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_75_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_75_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_75_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_75_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_76 @ 0XFF180130

- - Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_76_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_76_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= sd1, Output, sdio - _clk_out- (SDSDIO clock) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_76_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[24]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[24]- (GPIO bank 2) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= mdio0, Output, gem0_mdc- (MDIO Clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= mdio2, Output, gem2_mdc- (MDIO Clock - 6= mdio3, Output, gem3_mdc- (MDIO Clock) 7= Not Used - PSU_IOU_SLCR_MIO_PIN_76_L3_SEL 6 - - Configures MIO Pin 76 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180130, 0x000000FEU ,0x000000C0U) - RegMask = (IOU_SLCR_MIO_PIN_76_L0_SEL_MASK | IOU_SLCR_MIO_PIN_76_L1_SEL_MASK | IOU_SLCR_MIO_PIN_76_L2_SEL_MASK | IOU_SLCR_MIO_PIN_76_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_76_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_76_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_76_L2_SEL_SHIFT - | 0x00000006U << IOU_SLCR_MIO_PIN_76_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_76_OFFSET ,0x000000FEU ,0x000000C0U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_77 @ 0XFF180134

- - Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_77_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_77_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Input, sdio1_cd_n- (SD card detect from connector) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_77_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[25]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[25]- (GPIO bank 2) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= mdio0, Input, gem0_mdio_in- (MDIO Data) 3= mdio0, Output, gem0_mdio_out- (MDIO Data) 4= mdio1, Input, gem1_mdio_in- (MD - O Data) 4= mdio1, Output, gem1_mdio_out- (MDIO Data) 5= mdio2, Input, gem2_mdio_in- (MDIO Data) 5= mdio2, Output, gem2_mdio_o - t- (MDIO Data) 6= mdio3, Input, gem3_mdio_in- (MDIO Data) 6= mdio3, Output, gem3_mdio_out- (MDIO Data) 7= Not Used - PSU_IOU_SLCR_MIO_PIN_77_L3_SEL 6 - - Configures MIO Pin 77 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180134, 0x000000FEU ,0x000000C0U) - RegMask = (IOU_SLCR_MIO_PIN_77_L0_SEL_MASK | IOU_SLCR_MIO_PIN_77_L1_SEL_MASK | IOU_SLCR_MIO_PIN_77_L2_SEL_MASK | IOU_SLCR_MIO_PIN_77_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_77_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_77_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_77_L2_SEL_SHIFT - | 0x00000006U << IOU_SLCR_MIO_PIN_77_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_77_OFFSET ,0x000000FEU ,0x000000C0U); - /*############################################################################################################################ */ - - /*Register : MIO_MST_TRI0 @ 0XFF180204

- - Master Tri-state Enable for pin 0, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI 0 - - Master Tri-state Enable for pin 1, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI 0 - - Master Tri-state Enable for pin 2, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI 0 - - Master Tri-state Enable for pin 3, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI 0 - - Master Tri-state Enable for pin 4, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI 0 - - Master Tri-state Enable for pin 5, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI 0 - - Master Tri-state Enable for pin 6, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI 0 - - Master Tri-state Enable for pin 7, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI 0 - - Master Tri-state Enable for pin 8, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI 0 - - Master Tri-state Enable for pin 9, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI 0 - - Master Tri-state Enable for pin 10, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI 0 - - Master Tri-state Enable for pin 11, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI 0 - - Master Tri-state Enable for pin 12, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI 0 - - Master Tri-state Enable for pin 13, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI 0 - - Master Tri-state Enable for pin 14, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI 0 - - Master Tri-state Enable for pin 15, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI 0 - - Master Tri-state Enable for pin 16, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI 0 - - Master Tri-state Enable for pin 17, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI 0 - - Master Tri-state Enable for pin 18, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI 1 - - Master Tri-state Enable for pin 19, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI 0 - - Master Tri-state Enable for pin 20, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI 0 - - Master Tri-state Enable for pin 21, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI 1 - - Master Tri-state Enable for pin 22, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI 0 - - Master Tri-state Enable for pin 23, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI 0 - - Master Tri-state Enable for pin 24, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI 0 - - Master Tri-state Enable for pin 25, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI 1 - - Master Tri-state Enable for pin 26, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI 0 - - Master Tri-state Enable for pin 27, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI 0 - - Master Tri-state Enable for pin 28, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI 1 - - Master Tri-state Enable for pin 29, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI 0 - - Master Tri-state Enable for pin 30, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI 1 - - Master Tri-state Enable for pin 31, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI 0 - - MIO pin Tri-state Enables, 31:0 - (OFFSET, MASK, VALUE) (0XFF180204, 0xFFFFFFFFU ,0x52240000U) - RegMask = (IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_SHIFT - | 0x00000001U << IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_SHIFT - | 0x00000001U << IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_SHIFT - | 0x00000001U << IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_SHIFT - | 0x00000001U << IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_SHIFT - | 0x00000001U << IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_MST_TRI0_OFFSET ,0xFFFFFFFFU ,0x52240000U); - /*############################################################################################################################ */ - - /*Register : MIO_MST_TRI1 @ 0XFF180208

- - Master Tri-state Enable for pin 32, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI 0 - - Master Tri-state Enable for pin 33, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI 0 - - Master Tri-state Enable for pin 34, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI 0 - - Master Tri-state Enable for pin 35, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI 0 - - Master Tri-state Enable for pin 36, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI 0 - - Master Tri-state Enable for pin 37, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI 0 - - Master Tri-state Enable for pin 38, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI 0 - - Master Tri-state Enable for pin 39, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI 0 - - Master Tri-state Enable for pin 40, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI 0 - - Master Tri-state Enable for pin 41, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI 0 - - Master Tri-state Enable for pin 42, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI 0 - - Master Tri-state Enable for pin 43, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI 0 - - Master Tri-state Enable for pin 44, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI 1 - - Master Tri-state Enable for pin 45, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI 1 - - Master Tri-state Enable for pin 46, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI 0 - - Master Tri-state Enable for pin 47, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI 0 - - Master Tri-state Enable for pin 48, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI 0 - - Master Tri-state Enable for pin 49, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI 0 - - Master Tri-state Enable for pin 50, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI 0 - - Master Tri-state Enable for pin 51, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI 0 - - Master Tri-state Enable for pin 52, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI 1 - - Master Tri-state Enable for pin 53, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI 1 - - Master Tri-state Enable for pin 54, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI 0 - - Master Tri-state Enable for pin 55, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI 1 - - Master Tri-state Enable for pin 56, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI 0 - - Master Tri-state Enable for pin 57, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI 0 - - Master Tri-state Enable for pin 58, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI 0 - - Master Tri-state Enable for pin 59, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI 0 - - Master Tri-state Enable for pin 60, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI 0 - - Master Tri-state Enable for pin 61, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI 0 - - Master Tri-state Enable for pin 62, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI 0 - - Master Tri-state Enable for pin 63, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI 0 - - MIO pin Tri-state Enables, 63:32 - (OFFSET, MASK, VALUE) (0XFF180208, 0xFFFFFFFFU ,0x00B03000U) - RegMask = (IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_SHIFT - | 0x00000001U << IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_SHIFT - | 0x00000001U << IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_SHIFT - | 0x00000001U << IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_SHIFT - | 0x00000001U << IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_SHIFT - | 0x00000001U << IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_MST_TRI1_OFFSET ,0xFFFFFFFFU ,0x00B03000U); - /*############################################################################################################################ */ - - /*Register : MIO_MST_TRI2 @ 0XFF18020C

- - Master Tri-state Enable for pin 64, active high - PSU_IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI 0 - - Master Tri-state Enable for pin 65, active high - PSU_IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI 0 - - Master Tri-state Enable for pin 66, active high - PSU_IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI 0 - - Master Tri-state Enable for pin 67, active high - PSU_IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI 0 - - Master Tri-state Enable for pin 68, active high - PSU_IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI 0 - - Master Tri-state Enable for pin 69, active high - PSU_IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI 0 - - Master Tri-state Enable for pin 70, active high - PSU_IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI 1 - - Master Tri-state Enable for pin 71, active high - PSU_IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI 1 - - Master Tri-state Enable for pin 72, active high - PSU_IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI 1 - - Master Tri-state Enable for pin 73, active high - PSU_IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI 1 - - Master Tri-state Enable for pin 74, active high - PSU_IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI 1 - - Master Tri-state Enable for pin 75, active high - PSU_IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI 1 - - Master Tri-state Enable for pin 76, active high - PSU_IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI 0 - - Master Tri-state Enable for pin 77, active high - PSU_IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI 0 - - MIO pin Tri-state Enables, 77:64 - (OFFSET, MASK, VALUE) (0XFF18020C, 0x00003FFFU ,0x00000FC0U) - RegMask = (IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_SHIFT - | 0x00000001U << IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_SHIFT - | 0x00000001U << IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_SHIFT - | 0x00000001U << IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_SHIFT - | 0x00000001U << IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_SHIFT - | 0x00000001U << IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_SHIFT - | 0x00000001U << IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_MST_TRI2_OFFSET ,0x00003FFFU ,0x00000FC0U); - /*############################################################################################################################ */ - - /*Register : bank0_ctrl0 @ 0XFF180138

- - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25 1 - - Drive0 control to MIO Bank 0 - control MIO[25:0] - (OFFSET, MASK, VALUE) (0XFF180138, 0x03FFFFFFU ,0x03FFFFFFU) - RegMask = (IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_BANK0_CTRL0_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU); - /*############################################################################################################################ */ - - /*Register : bank0_ctrl1 @ 0XFF18013C

- - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25 1 - - Drive1 control to MIO Bank 0 - control MIO[25:0] - (OFFSET, MASK, VALUE) (0XFF18013C, 0x03FFFFFFU ,0x03FFFFFFU) - RegMask = (IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_BANK0_CTRL1_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU); - /*############################################################################################################################ */ - - /*Register : bank0_ctrl3 @ 0XFF180140

- - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25 0 - - Selects either Schmitt or CMOS input for MIO Bank 0 - control MIO[25:0] - (OFFSET, MASK, VALUE) (0XFF180140, 0x03FFFFFFU ,0x00000000U) - RegMask = (IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_BANK0_CTRL3_OFFSET ,0x03FFFFFFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : bank0_ctrl4 @ 0XFF180144

- - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25 1 - - When mio_bank0_pull_enable is set, this selects pull up or pull down for MIO Bank 0 - control MIO[25:0] - (OFFSET, MASK, VALUE) (0XFF180144, 0x03FFFFFFU ,0x03FFFFFFU) - RegMask = (IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_BANK0_CTRL4_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU); - /*############################################################################################################################ */ - - /*Register : bank0_ctrl5 @ 0XFF180148

- - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25 1 - - When set, this enables mio_bank0_pullupdown to selects pull up or pull down for MIO Bank 0 - control MIO[25:0] - (OFFSET, MASK, VALUE) (0XFF180148, 0x03FFFFFFU ,0x03FFFFFFU) - RegMask = (IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_BANK0_CTRL5_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU); - /*############################################################################################################################ */ - - /*Register : bank0_ctrl6 @ 0XFF18014C

- - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25 0 - - Slew rate control to MIO Bank 0 - control MIO[25:0] - (OFFSET, MASK, VALUE) (0XFF18014C, 0x03FFFFFFU ,0x00000000U) - RegMask = (IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_BANK0_CTRL6_OFFSET ,0x03FFFFFFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : bank1_ctrl0 @ 0XFF180154

- - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25 1 - - Drive0 control to MIO Bank 1 - control MIO[51:26] - (OFFSET, MASK, VALUE) (0XFF180154, 0x03FFFFFFU ,0x03FFFFFFU) - RegMask = (IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_BANK1_CTRL0_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU); - /*############################################################################################################################ */ - - /*Register : bank1_ctrl1 @ 0XFF180158

- - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25 1 - - Drive1 control to MIO Bank 1 - control MIO[51:26] - (OFFSET, MASK, VALUE) (0XFF180158, 0x03FFFFFFU ,0x03FFFFFFU) - RegMask = (IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_BANK1_CTRL1_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU); - /*############################################################################################################################ */ - - /*Register : bank1_ctrl3 @ 0XFF18015C

- - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25 0 - - Selects either Schmitt or CMOS input for MIO Bank 1 - control MIO[51:26] - (OFFSET, MASK, VALUE) (0XFF18015C, 0x03FFFFFFU ,0x00000000U) - RegMask = (IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_BANK1_CTRL3_OFFSET ,0x03FFFFFFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : bank1_ctrl4 @ 0XFF180160

- - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25 1 - - When mio_bank1_pull_enable is set, this selects pull up or pull down for MIO Bank 1 - control MIO[51:26] - (OFFSET, MASK, VALUE) (0XFF180160, 0x03FFFFFFU ,0x03FFFFFFU) - RegMask = (IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_BANK1_CTRL4_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU); - /*############################################################################################################################ */ - - /*Register : bank1_ctrl5 @ 0XFF180164

- - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25 1 - - When set, this enables mio_bank1_pullupdown to selects pull up or pull down for MIO Bank 1 - control MIO[51:26] - (OFFSET, MASK, VALUE) (0XFF180164, 0x03FFFFFFU ,0x03FFFFFFU) - RegMask = (IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_BANK1_CTRL5_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU); - /*############################################################################################################################ */ - - /*Register : bank1_ctrl6 @ 0XFF180168

- - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25 0 - - Slew rate control to MIO Bank 1 - control MIO[51:26] - (OFFSET, MASK, VALUE) (0XFF180168, 0x03FFFFFFU ,0x00000000U) - RegMask = (IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_BANK1_CTRL6_OFFSET ,0x03FFFFFFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : bank2_ctrl0 @ 0XFF180170

- - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25 1 - - Drive0 control to MIO Bank 2 - control MIO[77:52] - (OFFSET, MASK, VALUE) (0XFF180170, 0x03FFFFFFU ,0x03FFFFFFU) - RegMask = (IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_BANK2_CTRL0_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU); - /*############################################################################################################################ */ - - /*Register : bank2_ctrl1 @ 0XFF180174

- - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25 1 - - Drive1 control to MIO Bank 2 - control MIO[77:52] - (OFFSET, MASK, VALUE) (0XFF180174, 0x03FFFFFFU ,0x03FFFFFFU) - RegMask = (IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_BANK2_CTRL1_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU); - /*############################################################################################################################ */ - - /*Register : bank2_ctrl3 @ 0XFF180178

- - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25 0 - - Selects either Schmitt or CMOS input for MIO Bank 2 - control MIO[77:52] - (OFFSET, MASK, VALUE) (0XFF180178, 0x03FFFFFFU ,0x00000000U) - RegMask = (IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_BANK2_CTRL3_OFFSET ,0x03FFFFFFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : bank2_ctrl4 @ 0XFF18017C

- - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25 1 - - When mio_bank2_pull_enable is set, this selects pull up or pull down for MIO Bank 2 - control MIO[77:52] - (OFFSET, MASK, VALUE) (0XFF18017C, 0x03FFFFFFU ,0x03FFFFFFU) - RegMask = (IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_BANK2_CTRL4_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU); - /*############################################################################################################################ */ - - /*Register : bank2_ctrl5 @ 0XFF180180

- - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25 1 - - When set, this enables mio_bank2_pullupdown to selects pull up or pull down for MIO Bank 2 - control MIO[77:52] - (OFFSET, MASK, VALUE) (0XFF180180, 0x03FFFFFFU ,0x03FFFFFFU) - RegMask = (IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_BANK2_CTRL5_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU); - /*############################################################################################################################ */ - - /*Register : bank2_ctrl6 @ 0XFF180184

- - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25 0 - - Slew rate control to MIO Bank 2 - control MIO[77:52] - (OFFSET, MASK, VALUE) (0XFF180184, 0x03FFFFFFU ,0x00000000U) - RegMask = (IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_BANK2_CTRL6_OFFSET ,0x03FFFFFFU ,0x00000000U); - /*############################################################################################################################ */ - - // : LOOPBACK - /*Register : MIO_LOOPBACK @ 0XFF180200

- - I2C Loopback Control. 0 = Connect I2C inputs according to MIO mapping. 1 = Loop I2C 0 outputs to I2C 1 inputs, and I2C 1 outp - ts to I2C 0 inputs. - PSU_IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1 0 - - CAN Loopback Control. 0 = Connect CAN inputs according to MIO mapping. 1 = Loop CAN 0 Tx to CAN 1 Rx, and CAN 1 Tx to CAN 0 R - . - PSU_IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1 0 - - UART Loopback Control. 0 = Connect UART inputs according to MIO mapping. 1 = Loop UART 0 outputs to UART 1 inputs, and UART 1 - outputs to UART 0 inputs. RXD/TXD cross-connected. RTS/CTS cross-connected. DSR, DTR, DCD and RI not used. - PSU_IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1 0 - - SPI Loopback Control. 0 = Connect SPI inputs according to MIO mapping. 1 = Loop SPI 0 outputs to SPI 1 inputs, and SPI 1 outp - ts to SPI 0 inputs. The other SPI core will appear on the LS Slave Select. - PSU_IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1 0 - - Loopback function within MIO - (OFFSET, MASK, VALUE) (0XFF180200, 0x0000000FU ,0x00000000U) - RegMask = (IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_MASK | IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_MASK | IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_MASK | IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_SHIFT - | 0x00000000U << IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_SHIFT - | 0x00000000U << IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_SHIFT - | 0x00000000U << IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_LOOPBACK_OFFSET ,0x0000000FU ,0x00000000U); - /*############################################################################################################################ */ - - - return 1; + return 1; } -unsigned long psu_peripherals_init_data() { - // : RESET BLOCKS - // : TIMESTAMP - /*Register : RST_LPD_IOU2 @ 0XFF5E0238

+unsigned long psu_mio_init_data(void) +{ + /* + * MIO PROGRAMMING + */ + /* + * Register : MIO_PIN_0 @ 0XFF180000 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out- + * (QSPI Clock) + * PSU_IOU_SLCR_MIO_PIN_0_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_0_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[0]- (Test Scan Port) = test_scan, Output, test_scan_out[0 + * ]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_0_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[0]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[0]- (GPIO bank 0) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG + * TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sc + * lk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Out + * put, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_c + * lk- (Trace Port Clock) + * PSU_IOU_SLCR_MIO_PIN_0_L3_SEL 0 + + * Configures MIO Pin 0 peripheral interface mapping. S + * (OFFSET, MASK, VALUE) (0XFF180000, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_0_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_1 @ 0XFF180004 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (Q + * SPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Databus) + * PSU_IOU_SLCR_MIO_PIN_1_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_1_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[1]- (Test Scan Port) = test_scan, Output, test_scan_out[1 + * ]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_1_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[1]- (GPIO bank 0) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG + * TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc3, Ou + * tput, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART + * receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control + * Signal) + * PSU_IOU_SLCR_MIO_PIN_1_L3_SEL 0 + + * Configures MIO Pin 1 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180004, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_1_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_2 @ 0XFF180008 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI + * Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus) + * PSU_IOU_SLCR_MIO_PIN_2_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_2_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[2]- (Test Scan Port) = test_scan, Output, test_scan_out[2 + * ]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_2_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[2]- (GPIO bank 0) 1= can0, Input, can0_phy_ + * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + * , Output, i2c0_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTAG + * TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc2, I + * nput, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver se + * rial input) 7= trace, Output, tracedq[0]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_2_L3_SEL 0 + + * Configures MIO Pin 2 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180008, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_2_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_3 @ 0XFF18000C + + * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI + * Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus) + * PSU_IOU_SLCR_MIO_PIN_3_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_3_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[3]- (Test Scan Port) = test_scan, Output, test_scan_out[3 + * ]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_3_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[3]- (GPIO bank 0) 1= can0, Output, can0_phy + * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + * 0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG + * TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output + * , spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- + * (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial + * output) 7= trace, Output, tracedq[1]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_3_L3_SEL 0 + + * Configures MIO Pin 3 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF18000C, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_3_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_4 @ 0XFF180010 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- ( + * QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Databus) + * PSU_IOU_SLCR_MIO_PIN_4_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_4_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[4]- (Test Scan Port) = test_scan, Output, test_scan_out[4 + * ]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_4_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[4]- (GPIO bank 0) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Wa + * tch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi + * 0, Output, spi0_so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Cloc + * k) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, O + * utput, tracedq[2]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_4_L3_SEL 0 + + * Configures MIO Pin 4 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180010, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_4_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_5 @ 0XFF180014 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out- + * (QSPI Slave Select) + * PSU_IOU_SLCR_MIO_PIN_5_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_5_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[5]- (Test Scan Port) = test_scan, Output, test_scan_out[5 + * ]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_5_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[5]- (GPIO bank 0) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (W + * atch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= + * spi0, Input, spi0_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC + * Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= + * trace, Output, tracedq[3]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_5_L3_SEL 0 + + * Configures MIO Pin 5 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180014, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_5_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_6 @ 0XFF180018 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_clk_for_l + * pbk- (QSPI Clock to be fed-back) + * PSU_IOU_SLCR_MIO_PIN_6_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_6_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[6]- (Test Scan Port) = test_scan, Output, test_scan_out[6 + * ]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_6_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[6]- (GPIO bank 0) 1= can0, Input, can0_phy_ + * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + * , Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Wat + * ch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= s + * pi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TT + * C Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, + * Output, tracedq[4]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_6_L3_SEL 0 + + * Configures MIO Pin 6 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180018, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_6_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_7 @ 0XFF18001C + + * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out_ + * upper- (QSPI Slave Select upper) + * PSU_IOU_SLCR_MIO_PIN_7_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_7_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[7]- (Test Scan Port) = test_scan, Output, test_scan_out[7 + * ]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_7_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[7]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[7]- (GPIO bank 0) 1= can0, Output, can0_phy + * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + * 0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- ( + * Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Ma + * ster Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua + * 0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, t + * racedq[5]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_7_L3_SEL 0 + + * Configures MIO Pin 7 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF18001C, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_7_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_8 @ 0XFF180020 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[0 + * ]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[0]- (QSPI Upper D + * atabus) + * PSU_IOU_SLCR_MIO_PIN_8_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_8_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[8]- (Test Scan Port) = test_scan, Output, test_scan_out[8 + * ]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_8_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[8]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[8]- (GPIO bank 0) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Wa + * tch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Maste + * r Selects) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_ + * txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Tra + * ce Port Databus) + * PSU_IOU_SLCR_MIO_PIN_8_L3_SEL 0 + + * Configures MIO Pin 8 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180020, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_8_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_9 @ 0XFF180024 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[1 + * ]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[1]- (QSPI Upper D + * atabus) + * PSU_IOU_SLCR_MIO_PIN_9_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NA + * ND chip enable) + * PSU_IOU_SLCR_MIO_PIN_9_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[9]- (Test Scan Port) = test_scan, Output, test_scan_out[9 + * ]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_9_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[9]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[9]- (GPIO bank 0) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (W + * atch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master S + * elects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc3, + * Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UA + * RT receiver serial input) 7= trace, Output, tracedq[7]- (Trace Port Data + * bus) + * PSU_IOU_SLCR_MIO_PIN_9_L3_SEL 0 + + * Configures MIO Pin 9 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180024, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_9_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_10 @ 0XFF180028 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[2 + * ]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[2]- (QSPI Upper D + * atabus) + * PSU_IOU_SLCR_MIO_PIN_10_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (N + * AND Ready/Busy) + * PSU_IOU_SLCR_MIO_PIN_10_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[10]- (Test Scan Port) = test_scan, Output, test_scan_out[ + * 10]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_10_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[10]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[10]- (GPIO bank 0) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= sp + * i1, Output, spi1_so- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clo + * ck) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outpu + * t, tracedq[8]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_10_L3_SEL 0 + + * Configures MIO Pin 10 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180028, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_10_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_11 @ 0XFF18002C + + * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[3 + * ]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[3]- (QSPI Upper D + * atabus) + * PSU_IOU_SLCR_MIO_PIN_11_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (N + * AND Ready/Busy) + * PSU_IOU_SLCR_MIO_PIN_11_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[11]- (Test Scan Port) = test_scan, Output, test_scan_out[ + * 11]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_11_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) + * 4= spi1, Input, spi1_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- ( + * TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial ou + * tput) 7= trace, Output, tracedq[9]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_11_L3_SEL 0 + + * Configures MIO Pin 11 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF18002C, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_11_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_12 @ 0XFF180030 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out_ + * upper- (QSPI Upper Clock) + * PSU_IOU_SLCR_MIO_PIN_12_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NA + * ND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe) + * PSU_IOU_SLCR_MIO_PIN_12_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[12]- (Test Scan Port) = test_scan, Output, test_scan_out[ + * 12]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_12_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[12]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[12]- (GPIO bank 0) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJT + * AG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_ + * sclk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, O + * utput, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace + * dq[10]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_12_L3_SEL 0 + + * Configures MIO Pin 12 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180030, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_12_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_13 @ 0XFF180034 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_13_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[0]- (NA + * ND chip enable) + * PSU_IOU_SLCR_MIO_PIN_13_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[13]- (Test Scan Port) = test_scan, Output, + * test_scan_out[13]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_13_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[13]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[13]- (GPIO bank 0) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTA + * G TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, + * Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UAR + * T receiver serial input) 7= trace, Output, tracedq[11]- (Trace Port Data + * bus) + * PSU_IOU_SLCR_MIO_PIN_13_L3_SEL 0 + + * Configures MIO Pin 13 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180034, 0x000000FEU ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_13_OFFSET, 0x000000FEU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_14 @ 0XFF180038 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_14_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_cle- (NAND + * Command Latch Enable) + * PSU_IOU_SLCR_MIO_PIN_14_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[14]- (Test Scan Port) = test_scan, Output, + * test_scan_out[14]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_14_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJT + * AG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, + * Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver + * serial input) 7= trace, Output, tracedq[12]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_14_L3_SEL 2 + + * Configures MIO Pin 14 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180038, 0x000000FEU ,0x00000040U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_14_OFFSET, 0x000000FEU, 0x00000040U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_15 @ 0XFF18003C + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_15_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ale- (NAND + * Address Latch Enable) + * PSU_IOU_SLCR_MIO_PIN_15_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[15]- (Test Scan Port) = test_scan, Output, + * test_scan_out[15]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_15_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[15]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[15]- (GPIO bank 0) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJT + * AG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Outp + * ut, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_ou + * t- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter seria + * l output) 7= trace, Output, tracedq[13]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_15_L3_SEL 2 + + * Configures MIO Pin 15 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF18003C, 0x000000FEU ,0x00000040U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_15_OFFSET, 0x000000FEU, 0x00000040U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_16 @ 0XFF180040 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_16_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[0]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[0]- (NAND Data Bus) + * PSU_IOU_SLCR_MIO_PIN_16_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[16]- (Test Scan Port) = test_scan, Output, + * test_scan_out[16]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_16_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[16]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[16]- (GPIO bank 0) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= s + * pi0, Output, spi0_so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Cl + * ock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, + * Output, tracedq[14]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_16_L3_SEL 2 + + * Configures MIO Pin 16 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180040, 0x000000FEU ,0x00000040U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_16_OFFSET, 0x000000FEU, 0x00000040U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_17 @ 0XFF180044 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_17_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[1]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[1]- (NAND Data Bus) + * PSU_IOU_SLCR_MIO_PIN_17_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[17]- (Test Scan Port) = test_scan, Output, + * test_scan_out[17]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_17_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[17]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[17]- (GPIO bank 0) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4 + * = spi0, Input, spi0_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (T + * TC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) + * 7= trace, Output, tracedq[15]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_17_L3_SEL 2 + + * Configures MIO Pin 17 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180044, 0x000000FEU ,0x00000040U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_17_OFFSET, 0x000000FEU, 0x00000040U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_18 @ 0XFF180048 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_18_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[2]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[2]- (NAND Data Bus) + * PSU_IOU_SLCR_MIO_PIN_18_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[18]- (Test Scan Port) = test_scan, Output, + * test_scan_out[18]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU + * Ext Tamper) + * PSU_IOU_SLCR_MIO_PIN_18_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[18]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[18]- (GPIO bank 0) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= sp + * i1, Output, spi1_so- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clo + * ck) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_18_L3_SEL 6 + + * Configures MIO Pin 18 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180048, 0x000000FEU ,0x000000C0U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_18_OFFSET, 0x000000FEU, 0x000000C0U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_19 @ 0XFF18004C + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_19_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[3]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[3]- (NAND Data Bus) + * PSU_IOU_SLCR_MIO_PIN_19_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[19]- (Test Scan Port) = test_scan, Output, + * test_scan_out[19]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU + * Ext Tamper) + * PSU_IOU_SLCR_MIO_PIN_19_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[19]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[19]- (GPIO bank 0) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI + * Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= + * ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_19_L3_SEL 6 + + * Configures MIO Pin 19 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF18004C, 0x000000FEU ,0x000000C0U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_19_OFFSET, 0x000000FEU, 0x000000C0U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_20 @ 0XFF180050 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_20_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[4]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[4]- (NAND Data Bus) + * PSU_IOU_SLCR_MIO_PIN_20_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[20]- (Test Scan Port) = test_scan, Output, + * test_scan_out[20]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU + * Ext Tamper) + * PSU_IOU_SLCR_MIO_PIN_20_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[20]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[20]- (GPIO bank 0) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Mas + * ter Selects) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua + * 1_txd- (UART transmitter serial output) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_20_L3_SEL 6 + + * Configures MIO Pin 20 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180050, 0x000000FEU ,0x000000C0U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_20_OFFSET, 0x000000FEU, 0x000000C0U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_21 @ 0XFF180054 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_21_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[5]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[5]- (NAND Data Bus) + * PSU_IOU_SLCR_MIO_PIN_21_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Com + * mand Indicator) = sd0, Output, sdio0_cmd_out- (Command Indicator) 2= tes + * t_scan, Input, test_scan_in[21]- (Test Scan Port) = test_scan, Output, t + * est_scan_out[21]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU E + * xt Tamper) + * PSU_IOU_SLCR_MIO_PIN_21_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[21]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[21]- (GPIO bank 0) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master + * Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc + * 1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- ( + * UART receiver serial input) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_21_L3_SEL 6 + + * Configures MIO Pin 21 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180054, 0x000000FEU ,0x000000C0U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_21_OFFSET, 0x000000FEU, 0x000000C0U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_22 @ 0XFF180058 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_22_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_we_b- (NAN + * D Write Enable) + * PSU_IOU_SLCR_MIO_PIN_22_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- + * (SDSDIO clock) 2= test_scan, Input, test_scan_in[22]- (Test Scan Port) = + * test_scan, Output, test_scan_out[22]- (Test Scan Port) 3= csu, Input, c + * su_ext_tamper- (CSU Ext Tamper) + * PSU_IOU_SLCR_MIO_PIN_22_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[22]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[22]- (GPIO bank 0) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= + * spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- ( + * TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not U + * sed + * PSU_IOU_SLCR_MIO_PIN_22_L3_SEL 0 + + * Configures MIO Pin 22 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180058, 0x000000FEU ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_22_OFFSET, 0x000000FEU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_23 @ 0XFF18005C + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_23_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[6]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[6]- (NAND Data Bus) + * PSU_IOU_SLCR_MIO_PIN_23_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- + * (SD card bus power) 2= test_scan, Input, test_scan_in[23]- (Test Scan Po + * rt) = test_scan, Output, test_scan_out[23]- (Test Scan Port) 3= csu, Inp + * ut, csu_ext_tamper- (CSU Ext Tamper) + * PSU_IOU_SLCR_MIO_PIN_23_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[23]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[23]- (GPIO bank 0) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) + * 4= spi1, Input, spi1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- ( + * TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial ou + * tput) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_23_L3_SEL 0 + + * Configures MIO Pin 23 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF18005C, 0x000000FEU ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_23_OFFSET, 0x000000FEU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_24 @ 0XFF180060 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_24_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[7]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[7]- (NAND Data Bus) + * PSU_IOU_SLCR_MIO_PIN_24_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD + * card detect from connector) 2= test_scan, Input, test_scan_in[24]- (Test + * Scan Port) = test_scan, Output, test_scan_out[24]- (Test Scan Port) 3= + * csu, Input, csu_ext_tamper- (CSU Ext Tamper) + * PSU_IOU_SLCR_MIO_PIN_24_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[24]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[24]- (GPIO bank 0) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= Not Used 5= ttc3, Input, ttc3_clk_in- (T + * TC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= N + * ot Used + * PSU_IOU_SLCR_MIO_PIN_24_L3_SEL 1 + + * Configures MIO Pin 24 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180060, 0x000000FEU ,0x00000020U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_24_OFFSET, 0x000000FEU, 0x00000020U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_25 @ 0XFF180064 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_25_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_re_n- (NAN + * D Read Enable) + * PSU_IOU_SLCR_MIO_PIN_25_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD ca + * rd write protect from connector) 2= test_scan, Input, test_scan_in[25]- + * (Test Scan Port) = test_scan, Output, test_scan_out[25]- (Test Scan Port + * ) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper) + * PSU_IOU_SLCR_MIO_PIN_25_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[25]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[25]- (GPIO bank 0) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= Not Used 5= ttc3, Output, ttc3_wave_ou + * t- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial in + * put) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_25_L3_SEL 1 + + * Configures MIO Pin 25 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180064, 0x000000FEU ,0x00000020U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_25_OFFSET, 0x000000FEU, 0x00000020U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_26 @ 0XFF180068 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ + * clk- (TX RGMII clock) + * PSU_IOU_SLCR_MIO_PIN_26_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NA + * ND chip enable) + * PSU_IOU_SLCR_MIO_PIN_26_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[0]- (PMU + * GPI) 2= test_scan, Input, test_scan_in[26]- (Test Scan Port) = test_sca + * n, Output, test_scan_out[26]- (Test Scan Port) 3= csu, Input, csu_ext_ta + * mper- (CSU Ext Tamper) + * PSU_IOU_SLCR_MIO_PIN_26_L2_SEL 0 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[0]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[0]- (GPIO bank 1) 1= can0, Input, can0_phy_ + * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + * , Output, i2c0_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG + * TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_scl + * k_out- (SPI Clock) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Inpu + * t, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- ( + * Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_26_L3_SEL 0 + + * Configures MIO Pin 26 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180068, 0x000000FEU ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_26_OFFSET, 0x000000FEU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_27 @ 0XFF18006C + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd + * [0]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_27_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (N + * AND Ready/Busy) + * PSU_IOU_SLCR_MIO_PIN_27_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[1]- (PMU + * GPI) 2= test_scan, Input, test_scan_in[27]- (Test Scan Port) = test_sca + * n, Output, test_scan_out[27]- (Test Scan Port) 3= dpaux, Input, dp_aux_d + * ata_in- (Dp Aux Data) = dpaux, Output, dp_aux_data_out- (Dp Aux Data) + * PSU_IOU_SLCR_MIO_PIN_27_L2_SEL 3 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[1]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[1]- (GPIO bank 1) 1= can0, Output, can0_phy + * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + * 0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG + * TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc2, O + * utput, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UAR + * T transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port D + * atabus) + * PSU_IOU_SLCR_MIO_PIN_27_L3_SEL 0 + + * Configures MIO Pin 27 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF18006C, 0x000000FEU ,0x00000018U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_27_OFFSET, 0x000000FEU, 0x00000018U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_28 @ 0XFF180070 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd + * [1]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_28_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (N + * AND Ready/Busy) + * PSU_IOU_SLCR_MIO_PIN_28_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[2]- (PMU + * GPI) 2= test_scan, Input, test_scan_in[28]- (Test Scan Port) = test_sca + * n, Output, test_scan_out[28]- (Test Scan Port) 3= dpaux, Input, dp_hot_p + * lug_detect- (Dp Aux Hot Plug) + * PSU_IOU_SLCR_MIO_PIN_28_L2_SEL 3 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[2]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[2]- (GPIO bank 1) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTA + * G TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc1, + * Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitt + * er serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_28_L3_SEL 0 + + * Configures MIO Pin 28 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180070, 0x000000FEU ,0x00000018U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_28_OFFSET, 0x000000FEU, 0x00000018U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_29 @ 0XFF180074 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd + * [2]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_29_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + * PCIE Reset signal) + * PSU_IOU_SLCR_MIO_PIN_29_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[3]- (PMU + * GPI) 2= test_scan, Input, test_scan_in[29]- (Test Scan Port) = test_sca + * n, Output, test_scan_out[29]- (Test Scan Port) 3= dpaux, Input, dp_aux_d + * ata_in- (Dp Aux Data) = dpaux, Output, dp_aux_data_out- (Dp Aux Data) + * PSU_IOU_SLCR_MIO_PIN_29_L2_SEL 3 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[3]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[3]- (GPIO bank 1) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG + * TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, + * spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- + * (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input + * ) 7= trace, Output, tracedq[7]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_29_L3_SEL 0 + + * Configures MIO Pin 29 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180074, 0x000000FEU ,0x00000018U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_29_OFFSET, 0x000000FEU, 0x00000018U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_30 @ 0XFF180078 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd + * [3]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_30_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + * PCIE Reset signal) + * PSU_IOU_SLCR_MIO_PIN_30_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[4]- (PMU + * GPI) 2= test_scan, Input, test_scan_in[30]- (Test Scan Port) = test_sca + * n, Output, test_scan_out[30]- (Test Scan Port) 3= dpaux, Input, dp_hot_p + * lug_detect- (Dp Aux Hot Plug) + * PSU_IOU_SLCR_MIO_PIN_30_L2_SEL 3 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[4]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[4]- (GPIO bank 1) 1= can0, Input, can0_phy_ + * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + * , Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Wat + * ch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0 + * , Output, spi0_so- (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clock + * ) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, + * tracedq[8]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_30_L3_SEL 0 + + * Configures MIO Pin 30 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180078, 0x000000FEU ,0x00000018U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_30_OFFSET, 0x000000FEU, 0x00000018U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_31 @ 0XFF18007C + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ + * ctl- (TX RGMII control) + * PSU_IOU_SLCR_MIO_PIN_31_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + * PCIE Reset signal) + * PSU_IOU_SLCR_MIO_PIN_31_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[5]- (PMU + * GPI) 2= test_scan, Input, test_scan_in[31]- (Test Scan Port) = test_sca + * n, Output, test_scan_out[31]- (Test Scan Port) 3= csu, Input, csu_ext_ta + * mper- (CSU Ext Tamper) + * PSU_IOU_SLCR_MIO_PIN_31_L2_SEL 0 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[5]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[5]- (GPIO bank 1) 1= can0, Output, can0_phy + * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + * 0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- ( + * Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= + * spi0, Input, spi0_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TT + * C Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial outp + * ut) 7= trace, Output, tracedq[9]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_31_L3_SEL 0 + + * Configures MIO Pin 31 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF18007C, 0x000000FEU ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_31_OFFSET, 0x000000FEU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_32 @ 0XFF180080 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_c + * lk- (RX RGMII clock) + * PSU_IOU_SLCR_MIO_PIN_32_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NA + * ND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe) + * PSU_IOU_SLCR_MIO_PIN_32_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[0]- (PM + * U GPI) 2= test_scan, Input, test_scan_in[32]- (Test Scan Port) = test_sc + * an, Output, test_scan_out[32]- (Test Scan Port) 3= csu, Input, csu_ext_t + * amper- (CSU Ext Tamper) + * PSU_IOU_SLCR_MIO_PIN_32_L2_SEL 1 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[6]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[6]- (GPIO bank 1) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Wa + * tch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= + * spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (T + * TC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= t + * race, Output, tracedq[10]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_32_L3_SEL 0 + + * Configures MIO Pin 32 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180080, 0x000000FEU ,0x00000008U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_32_OFFSET, 0x000000FEU, 0x00000008U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_33 @ 0XFF180084 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[ + * 0]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_33_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + * PCIE Reset signal) + * PSU_IOU_SLCR_MIO_PIN_33_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[1]- (PM + * U GPI) 2= test_scan, Input, test_scan_in[33]- (Test Scan Port) = test_sc + * an, Output, test_scan_out[33]- (Test Scan Port) 3= csu, Input, csu_ext_t + * amper- (CSU Ext Tamper) + * PSU_IOU_SLCR_MIO_PIN_33_L2_SEL 1 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[7]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[7]- (GPIO bank 1) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (W + * atch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Mas + * ter Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1 + * , Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq + * [11]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_33_L3_SEL 0 + + * Configures MIO Pin 33 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180084, 0x000000FEU ,0x00000008U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_33_OFFSET, 0x000000FEU, 0x00000008U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_34 @ 0XFF180088 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[ + * 1]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_34_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + * PCIE Reset signal) + * PSU_IOU_SLCR_MIO_PIN_34_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[2]- (PM + * U GPI) 2= test_scan, Input, test_scan_in[34]- (Test Scan Port) = test_sc + * an, Output, test_scan_out[34]- (Test Scan Port) 3= dpaux, Input, dp_aux_ + * data_in- (Dp Aux Data) = dpaux, Output, dp_aux_data_out- (Dp Aux Data) + * PSU_IOU_SLCR_MIO_PIN_34_L2_SEL 1 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[8]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[8]- (GPIO bank 1) 1= can0, Input, can0_phy_ + * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + * , Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Wat + * ch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master + * Selects) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rx + * d- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace Po + * rt Databus) + * PSU_IOU_SLCR_MIO_PIN_34_L3_SEL 0 + + * Configures MIO Pin 34 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180088, 0x000000FEU ,0x00000008U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_34_OFFSET, 0x000000FEU, 0x00000008U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_35 @ 0XFF18008C + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[ + * 2]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_35_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + * PCIE Reset signal) + * PSU_IOU_SLCR_MIO_PIN_35_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[3]- (PM + * U GPI) 2= test_scan, Input, test_scan_in[35]- (Test Scan Port) = test_sc + * an, Output, test_scan_out[35]- (Test Scan Port) 3= dpaux, Input, dp_hot_ + * plug_detect- (Dp Aux Hot Plug) + * PSU_IOU_SLCR_MIO_PIN_35_L2_SEL 1 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[9]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[9]- (GPIO bank 1) 1= can0, Output, can0_phy + * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + * 0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- ( + * Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master + * Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc2 + * , Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- ( + * UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace Po + * rt Databus) + * PSU_IOU_SLCR_MIO_PIN_35_L3_SEL 0 + + * Configures MIO Pin 35 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF18008C, 0x000000FEU ,0x00000008U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_35_OFFSET, 0x000000FEU, 0x00000008U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_36 @ 0XFF180090 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[ + * 3]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_36_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + * PCIE Reset signal) + * PSU_IOU_SLCR_MIO_PIN_36_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[4]- (PM + * U GPI) 2= test_scan, Input, test_scan_in[36]- (Test Scan Port) = test_sc + * an, Output, test_scan_out[36]- (Test Scan Port) 3= dpaux, Input, dp_aux_ + * data_in- (Dp Aux Data) = dpaux, Output, dp_aux_data_out- (Dp Aux Data) + * PSU_IOU_SLCR_MIO_PIN_36_L2_SEL 1 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[10]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[10]- (GPIO bank 1) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= s + * pi1, Output, spi1_so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Cl + * ock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, + * Output, tracedq[14]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_36_L3_SEL 0 + + * Configures MIO Pin 36 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180090, 0x000000FEU ,0x00000008U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_36_OFFSET, 0x000000FEU, 0x00000008U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_37 @ 0XFF180094 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_c + * tl- (RX RGMII control ) + * PSU_IOU_SLCR_MIO_PIN_37_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + * PCIE Reset signal) + * PSU_IOU_SLCR_MIO_PIN_37_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[5]- (PM + * U GPI) 2= test_scan, Input, test_scan_in[37]- (Test Scan Port) = test_sc + * an, Output, test_scan_out[37]- (Test Scan Port) 3= dpaux, Input, dp_hot_ + * plug_detect- (Dp Aux Hot Plug) + * PSU_IOU_SLCR_MIO_PIN_37_L2_SEL 1 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[11]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[11]- (GPIO bank 1) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4 + * = spi1, Input, spi1_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (T + * TC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) + * 7= trace, Output, tracedq[15]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_37_L3_SEL 0 + + * Configures MIO Pin 37 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180094, 0x000000FEU ,0x00000008U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_37_OFFSET, 0x000000FEU, 0x00000008U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_38 @ 0XFF180098 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ + * clk- (TX RGMII clock) + * PSU_IOU_SLCR_MIO_PIN_38_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_38_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- + * (SDSDIO clock) 2= Not Used 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_38_L2_SEL 0 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[12]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[12]- (GPIO bank 1) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTA + * G TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_s + * clk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, In + * put, ua0_rxd- (UART receiver serial input) 7= trace, Output, trace_clk- + * (Trace Port Clock) + * PSU_IOU_SLCR_MIO_PIN_38_L3_SEL 0 + + * Configures MIO Pin 38 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180098, 0x000000FEU ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_38_OFFSET, 0x000000FEU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_39 @ 0XFF18009C + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd + * [0]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_39_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_39_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD + * card detect from connector) 2= sd1, Input, sd1_data_in[4]- (8-bit Data b + * us) = sd1, Output, sdio1_data_out[4]- (8-bit Data bus) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_39_L2_SEL 2 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[13]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[13]- (GPIO bank 1) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJT + * AG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc0, + * Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (U + * ART transmitter serial output) 7= trace, Output, trace_ctl- (Trace Port + * Control Signal) + * PSU_IOU_SLCR_MIO_PIN_39_L3_SEL 0 + + * Configures MIO Pin 39 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF18009C, 0x000000FEU ,0x00000010U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_39_OFFSET, 0x000000FEU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_40 @ 0XFF1800A0 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd + * [1]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_40_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_40_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Com + * mand Indicator) = sd0, Output, sdio0_cmd_out- (Command Indicator) 2= sd1 + * , Input, sd1_data_in[5]- (8-bit Data bus) = sd1, Output, sdio1_data_out[ + * 5]- (8-bit Data bus) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_40_L2_SEL 2 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[14]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[14]- (GPIO bank 1) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJ + * TAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc3 + * , Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmi + * tter serial output) 7= trace, Output, tracedq[0]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_40_L3_SEL 0 + + * Configures MIO Pin 40 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800A0, 0x000000FEU ,0x00000010U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_40_OFFSET, 0x000000FEU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_41 @ 0XFF1800A4 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd + * [2]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_41_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_41_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[6]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[6]- (8-bit Data bus) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_41_L2_SEL 2 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[15]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[15]- (GPIO bank 1) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTA + * G TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Outpu + * t, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out + * - (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial inp + * ut) 7= trace, Output, tracedq[1]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_41_L3_SEL 0 + + * Configures MIO Pin 41 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800A4, 0x000000FEU ,0x00000010U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_41_OFFSET, 0x000000FEU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_42 @ 0XFF1800A8 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd + * [3]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_42_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_42_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[7]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[7]- (8-bit Data bus) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_42_L2_SEL 2 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= sp + * i0, Output, spi0_so- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clo + * ck) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outpu + * t, tracedq[2]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_42_L3_SEL 0 + + * Configures MIO Pin 42 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800A8, 0x000000FEU ,0x00000010U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_42_OFFSET, 0x000000FEU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_43 @ 0XFF1800AC + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ + * ctl- (TX RGMII control) + * PSU_IOU_SLCR_MIO_PIN_43_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_43_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8-bit Data bus) 2= s + * d1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_43_L2_SEL 0 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) + * 4= spi0, Input, spi0_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- ( + * TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial ou + * tput) 7= trace, Output, tracedq[3]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_43_L3_SEL 0 + + * Configures MIO Pin 43 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800AC, 0x000000FEU ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_43_OFFSET, 0x000000FEU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_44 @ 0XFF1800B0 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_c + * lk- (RX RGMII clock) + * PSU_IOU_SLCR_MIO_PIN_44_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_44_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8-bit Data bus) 2= s + * d1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_44_L2_SEL 2 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[18]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[18]- (GPIO bank 1) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4 + * = spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- + * (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= + * Not Used + * PSU_IOU_SLCR_MIO_PIN_44_L3_SEL 0 + + * Configures MIO Pin 44 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800B0, 0x000000FEU ,0x00000010U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_44_OFFSET, 0x000000FEU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_45 @ 0XFF1800B4 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[ + * 0]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_45_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_45_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8-bit Data bus) 2= s + * d1, Input, sdio1_cd_n- (SD card detect from connector) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_45_L2_SEL 2 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[19]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[19]- (GPIO bank 1) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI M + * aster Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= u + * a1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_45_L3_SEL 0 + + * Configures MIO Pin 45 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800B4, 0x000000FEU ,0x00000010U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_45_OFFSET, 0x000000FEU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_46 @ 0XFF1800B8 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[ + * 1]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_46_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_46_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[0]- (8-bit Data bus) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_46_L2_SEL 2 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Mast + * er Selects) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_ + * rxd- (UART receiver serial input) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_46_L3_SEL 0 + + * Configures MIO Pin 46 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800B8, 0x000000FEU ,0x00000010U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_46_OFFSET, 0x000000FEU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_47 @ 0XFF1800BC + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[ + * 2]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_47_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_47_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[1]- (8-bit Data bus) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_47_L2_SEL 2 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Maste + * r Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= tt + * c0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- + * (UART transmitter serial output) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_47_L3_SEL 0 + + * Configures MIO Pin 47 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800BC, 0x000000FEU ,0x00000010U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_47_OFFSET, 0x000000FEU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_48 @ 0XFF1800C0 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[ + * 3]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_48_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_48_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[2]- (8-bit Data bus) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_48_L2_SEL 2 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[22]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[22]- (GPIO bank 1) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= s + * pi1, Output, spi1_so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Cl + * ock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Us + * ed + * PSU_IOU_SLCR_MIO_PIN_48_L3_SEL 0 + + * Configures MIO Pin 48 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800C0, 0x000000FEU ,0x00000010U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_48_OFFSET, 0x000000FEU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_49 @ 0XFF1800C4 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_c + * tl- (RX RGMII control ) + * PSU_IOU_SLCR_MIO_PIN_49_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_49_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- + * (SD card bus power) 2= sd1, Input, sd1_data_in[3]- (8-bit Data bus) = sd + * 1, Output, sdio1_data_out[3]- (8-bit Data bus) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_49_L2_SEL 2 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[23]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[23]- (GPIO bank 1) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4 + * = spi1, Input, spi1_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (T + * TC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) + * 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_49_L3_SEL 0 + + * Configures MIO Pin 49 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800C4, 0x000000FEU ,0x00000010U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_49_OFFSET, 0x000000FEU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_50 @ 0XFF1800C8 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- + * (TSU clock) + * PSU_IOU_SLCR_MIO_PIN_50_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_50_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD ca + * rd write protect from connector) 2= sd1, Input, sd1_cmd_in- (Command Ind + * icator) = sd1, Output, sdio1_cmd_out- (Command Indicator) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_50_L2_SEL 2 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[24]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[24]- (GPIO bank 1) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= + * ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART rece + * iver serial input) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_50_L3_SEL 0 + + * Configures MIO Pin 50 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800C8, 0x000000FEU ,0x00000010U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_50_OFFSET, 0x000000FEU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_51 @ 0XFF1800CC + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- + * (TSU clock) + * PSU_IOU_SLCR_MIO_PIN_51_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_51_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Output, sdi + * o1_clk_out- (SDSDIO clock) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_51_L2_SEL 2 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[25]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[25]- (GPIO bank 1) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= mdio1, Input, gem1_mdio_in- (MDIO Dat + * a) 4= mdio1, Output, gem1_mdio_out- (MDIO Data) 5= ttc2, Output, ttc2_wa + * ve_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter + * serial output) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_51_L3_SEL 0 + + * Configures MIO Pin 51 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800CC, 0x000000FEU ,0x00000010U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_51_OFFSET, 0x000000FEU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_52 @ 0XFF1800D0 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_ + * clk- (TX RGMII clock) + * PSU_IOU_SLCR_MIO_PIN_52_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_clk_i + * n- (ULPI Clock) + * PSU_IOU_SLCR_MIO_PIN_52_L1_SEL 1 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used + * PSU_IOU_SLCR_MIO_PIN_52_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[0]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[0]- (GPIO bank 2) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG + * TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sc + * lk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Out + * put, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_c + * lk- (Trace Port Clock) + * PSU_IOU_SLCR_MIO_PIN_52_L3_SEL 0 + + * Configures MIO Pin 52 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800D0, 0x000000FEU ,0x00000004U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_52_OFFSET, 0x000000FEU, 0x00000004U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_53 @ 0XFF1800D4 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd + * [0]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_53_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_dir- + * (Data bus direction control) + * PSU_IOU_SLCR_MIO_PIN_53_L1_SEL 1 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used + * PSU_IOU_SLCR_MIO_PIN_53_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[1]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[1]- (GPIO bank 2) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG + * TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Ou + * tput, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART + * receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control + * Signal) + * PSU_IOU_SLCR_MIO_PIN_53_L3_SEL 0 + + * Configures MIO Pin 53 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800D4, 0x000000FEU ,0x00000004U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_53_OFFSET, 0x000000FEU, 0x00000004U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_54 @ 0XFF1800D8 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd + * [1]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_54_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[2]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[2]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_54_L1_SEL 1 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used + * PSU_IOU_SLCR_MIO_PIN_54_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[2]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[2]- (GPIO bank 2) 1= can0, Input, can0_phy_ + * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + * , Output, i2c0_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTAG + * TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, I + * nput, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver se + * rial input) 7= trace, Output, tracedq[0]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_54_L3_SEL 0 + + * Configures MIO Pin 54 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800D8, 0x000000FEU ,0x00000004U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_54_OFFSET, 0x000000FEU, 0x00000004U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_55 @ 0XFF1800DC + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd + * [2]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_55_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_nxt- + * (Data flow control signal from the PHY) + * PSU_IOU_SLCR_MIO_PIN_55_L1_SEL 1 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used + * PSU_IOU_SLCR_MIO_PIN_55_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[3]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[3]- (GPIO bank 2) 1= can0, Output, can0_phy + * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + * 0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG + * TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output + * , spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- + * (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial + * output) 7= trace, Output, tracedq[1]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_55_L3_SEL 0 + + * Configures MIO Pin 55 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800DC, 0x000000FEU ,0x00000004U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_55_OFFSET, 0x000000FEU, 0x00000004U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_56 @ 0XFF1800E0 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd + * [3]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_56_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[0]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[0]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_56_L1_SEL 1 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used + * PSU_IOU_SLCR_MIO_PIN_56_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[4]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[4]- (GPIO bank 2) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Wa + * tch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi + * 0, Output, spi0_so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Cloc + * k) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, O + * utput, tracedq[2]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_56_L3_SEL 0 + + * Configures MIO Pin 56 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800E0, 0x000000FEU ,0x00000004U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_56_OFFSET, 0x000000FEU, 0x00000004U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_57 @ 0XFF1800E4 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_ + * ctl- (TX RGMII control) + * PSU_IOU_SLCR_MIO_PIN_57_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[1]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[1]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_57_L1_SEL 1 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used + * PSU_IOU_SLCR_MIO_PIN_57_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[5]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[5]- (GPIO bank 2) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (W + * atch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= + * spi0, Input, spi0_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC + * Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= + * trace, Output, tracedq[3]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_57_L3_SEL 0 + + * Configures MIO Pin 57 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800E4, 0x000000FEU ,0x00000004U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_57_OFFSET, 0x000000FEU, 0x00000004U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_58 @ 0XFF1800E8 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_c + * lk- (RX RGMII clock) + * PSU_IOU_SLCR_MIO_PIN_58_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Output, usb0_ulpi_stp- + * (Asserted to end or interrupt transfers) + * PSU_IOU_SLCR_MIO_PIN_58_L1_SEL 1 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used + * PSU_IOU_SLCR_MIO_PIN_58_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[6]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[6]- (GPIO bank 2) 1= can0, Input, can0_phy_ + * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + * , Output, i2c0_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG + * TCK) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1_scl + * k_out- (SPI Clock) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Inpu + * t, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- ( + * Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_58_L3_SEL 0 + + * Configures MIO Pin 58 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800E8, 0x000000FEU ,0x00000004U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_58_OFFSET, 0x000000FEU, 0x00000004U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_59 @ 0XFF1800EC + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[ + * 0]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_59_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[3]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[3]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_59_L1_SEL 1 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used + * PSU_IOU_SLCR_MIO_PIN_59_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[7]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[7]- (GPIO bank 2) 1= can0, Output, can0_phy + * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + * 0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG + * TDI) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= ttc2, O + * utput, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UAR + * T transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port D + * atabus) + * PSU_IOU_SLCR_MIO_PIN_59_L3_SEL 0 + + * Configures MIO Pin 59 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800EC, 0x000000FEU ,0x00000004U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_59_OFFSET, 0x000000FEU, 0x00000004U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_60 @ 0XFF1800F0 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[ + * 1]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_60_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[4]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[4]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_60_L1_SEL 1 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used + * PSU_IOU_SLCR_MIO_PIN_60_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[8]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[8]- (GPIO bank 2) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTA + * G TDO) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc1, + * Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitt + * er serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_60_L3_SEL 0 + + * Configures MIO Pin 60 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800F0, 0x000000FEU ,0x00000004U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_60_OFFSET, 0x000000FEU, 0x00000004U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_61 @ 0XFF1800F4 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[ + * 2]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_61_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[5]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[5]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_61_L1_SEL 1 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used + * PSU_IOU_SLCR_MIO_PIN_61_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[9]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[9]- (GPIO bank 2) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG + * TMS) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, Output, + * spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- + * (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input + * ) 7= trace, Output, tracedq[7]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_61_L3_SEL 0 + + * Configures MIO Pin 61 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800F4, 0x000000FEU ,0x00000004U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_61_OFFSET, 0x000000FEU, 0x00000004U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_62 @ 0XFF1800F8 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[ + * 3]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_62_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[6]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[6]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_62_L1_SEL 1 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used + * PSU_IOU_SLCR_MIO_PIN_62_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[10]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[10]- (GPIO bank 2) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= sp + * i1, Output, spi1_so- (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clo + * ck) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outpu + * t, tracedq[8]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_62_L3_SEL 0 + + * Configures MIO Pin 62 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800F8, 0x000000FEU ,0x00000004U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_62_OFFSET, 0x000000FEU, 0x00000004U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_63 @ 0XFF1800FC + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_c + * tl- (RX RGMII control ) + * PSU_IOU_SLCR_MIO_PIN_63_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[7]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[7]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_63_L1_SEL 1 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used + * PSU_IOU_SLCR_MIO_PIN_63_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[11]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[11]- (GPIO bank 2) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) + * 4= spi1, Input, spi1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- ( + * TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial ou + * tput) 7= trace, Output, tracedq[9]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_63_L3_SEL 0 + + * Configures MIO Pin 63 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800FC, 0x000000FEU ,0x00000004U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_63_OFFSET, 0x000000FEU, 0x00000004U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_64 @ 0XFF180100 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_ + * clk- (TX RGMII clock) + * PSU_IOU_SLCR_MIO_PIN_64_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_clk_i + * n- (ULPI Clock) + * PSU_IOU_SLCR_MIO_PIN_64_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- + * (SDSDIO clock) 2= Not Used 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_64_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[12]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[12]- (GPIO bank 2) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4 + * = spi0, Output, spi0_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- + * (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= + * trace, Output, tracedq[10]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_64_L3_SEL 0 + + * Configures MIO Pin 64 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180100, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_64_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_65 @ 0XFF180104 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd + * [0]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_65_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_dir- + * (Data bus direction control) + * PSU_IOU_SLCR_MIO_PIN_65_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD + * card detect from connector) 2= Not Used 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_65_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[13]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[13]- (GPIO bank 2) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi0, Output, spi0_n_ss_out[2]- (SPI M + * aster Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= u + * a1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trace + * dq[11]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_65_L3_SEL 0 + + * Configures MIO Pin 65 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180104, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_65_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_66 @ 0XFF180108 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd + * [1]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_66_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[2]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[2]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_66_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Com + * mand Indicator) = sd0, Output, sdio0_cmd_out- (Command Indicator) 2= Not + * Used 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_66_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[14]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[14]- (GPIO bank 2) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Mast + * er Selects) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_ + * rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace + * Port Databus) + * PSU_IOU_SLCR_MIO_PIN_66_L3_SEL 0 + + * Configures MIO Pin 66 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180108, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_66_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_67 @ 0XFF18010C + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd + * [2]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_67_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_nxt- + * (Data flow control signal from the PHY) + * PSU_IOU_SLCR_MIO_PIN_67_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8-bit Data bus) 2= N + * ot Used 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_67_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[15]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[15]- (GPIO bank 2) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi0, Input, spi0_n_ss_in- (SPI Maste + * r Selects) 4= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 5= tt + * c2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- + * (UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace + * Port Databus) + * PSU_IOU_SLCR_MIO_PIN_67_L3_SEL 0 + + * Configures MIO Pin 67 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF18010C, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_67_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_68 @ 0XFF180110 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd + * [3]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_68_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[0]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[0]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_68_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8-bit Data bus) 2= N + * ot Used 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_68_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[16]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[16]- (GPIO bank 2) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= s + * pi0, Output, spi0_so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Cl + * ock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, + * Output, tracedq[14]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_68_L3_SEL 0 + + * Configures MIO Pin 68 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180110, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_68_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_69 @ 0XFF180114 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_ + * ctl- (TX RGMII control) + * PSU_IOU_SLCR_MIO_PIN_69_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[1]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[1]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_69_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8-bit Data bus) 2= s + * d1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_69_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[17]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[17]- (GPIO bank 2) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4 + * = spi0, Input, spi0_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (T + * TC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) + * 7= trace, Output, tracedq[15]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_69_L3_SEL 0 + + * Configures MIO Pin 69 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180114, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_69_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_70 @ 0XFF180118 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_c + * lk- (RX RGMII clock) + * PSU_IOU_SLCR_MIO_PIN_70_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Output, usb1_ulpi_stp- + * (Asserted to end or interrupt transfers) + * PSU_IOU_SLCR_MIO_PIN_70_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8-bit Data bus) 2= s + * d1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_70_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[18]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[18]- (GPIO bank 2) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= + * spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- ( + * TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not U + * sed + * PSU_IOU_SLCR_MIO_PIN_70_L3_SEL 0 + + * Configures MIO Pin 70 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180118, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_70_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_71 @ 0XFF18011C + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[ + * 0]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_71_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[3]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[3]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_71_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[0]- (8-bit Data bus) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_71_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[19]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[19]- (GPIO bank 2) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI + * Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= + * ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_71_L3_SEL 0 + + * Configures MIO Pin 71 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF18011C, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_71_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_72 @ 0XFF180120 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[ + * 1]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_72_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[4]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[4]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_72_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[1]- (8-bit Data bus) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_72_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[20]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[20]- (GPIO bank 2) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Mas + * ter Selects) 5= Not Used 6= ua1, Output, ua1_txd- (UART transmitter seri + * al output) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_72_L3_SEL 0 + + * Configures MIO Pin 72 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180120, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_72_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_73 @ 0XFF180124 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[ + * 2]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_73_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[5]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_73_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[2]- (8-bit Data bus) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_73_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[21]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[21]- (GPIO bank 2) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master + * Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= Not + * Used 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_73_L3_SEL 0 + + * Configures MIO Pin 73 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180124, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_73_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_74 @ 0XFF180128 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[ + * 3]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_74_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[6]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[6]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_74_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[3]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[3]- (8-bit Data bus) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_74_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[22]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[22]- (GPIO bank 2) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= sp + * i1, Output, spi1_so- (MISO signal) 5= Not Used 6= ua0, Input, ua0_rxd- ( + * UART receiver serial input) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_74_L3_SEL 0 + + * Configures MIO Pin 74 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180128, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_74_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_75 @ 0XFF18012C + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_c + * tl- (RX RGMII control ) + * PSU_IOU_SLCR_MIO_PIN_75_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[7]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[7]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_75_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- + * (SD card bus power) 2= sd1, Input, sd1_cmd_in- (Command Indicator) = sd1 + * , Output, sdio1_cmd_out- (Command Indicator) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_75_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[23]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[23]- (GPIO bank 2) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) + * 4= spi1, Input, spi1_si- (MOSI signal) 5= Not Used 6= ua0, Output, ua0_t + * xd- (UART transmitter serial output) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_75_L3_SEL 0 + + * Configures MIO Pin 75 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF18012C, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_75_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_76 @ 0XFF180130 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_76_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_76_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD ca + * rd write protect from connector) 2= sd1, Output, sdio1_clk_out- (SDSDIO + * clock) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_76_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[24]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[24]- (GPIO bank 2) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= mdio0, Output, gem0_mdc- (MDI + * O Clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= mdio2, Output, gem2 + * _mdc- (MDIO Clock) 6= mdio3, Output, gem3_mdc- (MDIO Clock) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_76_L3_SEL 6 + + * Configures MIO Pin 76 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180130, 0x000000FEU ,0x000000C0U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_76_OFFSET, 0x000000FEU, 0x000000C0U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_77 @ 0XFF180134 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_77_L0_SEL 0 - Block level reset - PSU_CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET 0 + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_77_L1_SEL 0 - Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset. - (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00100000U ,0x00000000U) - RegMask = (CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_MASK | 0 ); + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Input, sdio + * 1_cd_n- (SD card detect from connector) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_77_L2_SEL 0 - RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RST_LPD_IOU2_OFFSET ,0x00100000U ,0x00000000U); - /*############################################################################################################################ */ + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[25]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[25]- (GPIO bank 2) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= mdio0, Input, gem0_mdio_in- (M + * DIO Data) 3= mdio0, Output, gem0_mdio_out- (MDIO Data) 4= mdio1, Input, + * gem1_mdio_in- (MDIO Data) 4= mdio1, Output, gem1_mdio_out- (MDIO Data) 5 + * = mdio2, Input, gem2_mdio_in- (MDIO Data) 5= mdio2, Output, gem2_mdio_ou + * t- (MDIO Data) 6= mdio3, Input, gem3_mdio_in- (MDIO Data) 6= mdio3, Outp + * ut, gem3_mdio_out- (MDIO Data) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_77_L3_SEL 6 - // : ENET - /*Register : RST_LPD_IOU0 @ 0XFF5E0230

+ * Configures MIO Pin 77 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180134, 0x000000FEU ,0x000000C0U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_77_OFFSET, 0x000000FEU, 0x000000C0U); +/*##################################################################### */ - GEM 3 reset - PSU_CRL_APB_RST_LPD_IOU0_GEM3_RESET 0 + /* + * Register : MIO_MST_TRI0 @ 0XFF180204 - Software controlled reset for the GEMs - (OFFSET, MASK, VALUE) (0XFF5E0230, 0x00000008U ,0x00000000U) - RegMask = (CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK | 0 ); + * Master Tri-state Enable for pin 0, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI 0 - RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RST_LPD_IOU0_OFFSET ,0x00000008U ,0x00000000U); - /*############################################################################################################################ */ + * Master Tri-state Enable for pin 1, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI 0 - // : QSPI - /*Register : RST_LPD_IOU2 @ 0XFF5E0238

+ * Master Tri-state Enable for pin 2, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI 0 - Block level reset - PSU_CRL_APB_RST_LPD_IOU2_QSPI_RESET 0 + * Master Tri-state Enable for pin 3, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI 0 - Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset. - (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000001U ,0x00000000U) - RegMask = (CRL_APB_RST_LPD_IOU2_QSPI_RESET_MASK | 0 ); + * Master Tri-state Enable for pin 4, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI 0 - RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU2_QSPI_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RST_LPD_IOU2_OFFSET ,0x00000001U ,0x00000000U); - /*############################################################################################################################ */ + * Master Tri-state Enable for pin 5, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI 0 - // : QSPI TAP DELAY - /*Register : IOU_TAPDLY_BYPASS @ 0XFF180390

+ * Master Tri-state Enable for pin 6, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI 0 - 0: Do not by pass the tap delays on the Rx clock signal of LQSPI 1: Bypass the Tap delay on the Rx clock signal of LQSPI - PSU_IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX 1 + * Master Tri-state Enable for pin 7, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI 0 - IOU tap delay bypass for the LQSPI and NAND controllers - (OFFSET, MASK, VALUE) (0XFF180390, 0x00000004U ,0x00000004U) - RegMask = (IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_MASK | 0 ); + * Master Tri-state Enable for pin 8, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI 0 - RegVal = ((0x00000001U << IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_IOU_TAPDLY_BYPASS_OFFSET ,0x00000004U ,0x00000004U); - /*############################################################################################################################ */ + * Master Tri-state Enable for pin 9, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI 0 - // : NAND - // : USB - /*Register : RST_LPD_TOP @ 0XFF5E023C

+ * Master Tri-state Enable for pin 10, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI 0 - USB 0 reset for control registers - PSU_CRL_APB_RST_LPD_TOP_USB0_APB_RESET 0 + * Master Tri-state Enable for pin 11, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI 0 - USB 0 sleep circuit reset - PSU_CRL_APB_RST_LPD_TOP_USB0_HIBERRESET 0 + * Master Tri-state Enable for pin 12, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI 0 - USB 0 reset - PSU_CRL_APB_RST_LPD_TOP_USB0_CORERESET 0 + * Master Tri-state Enable for pin 13, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI 0 - Software control register for the LPD block. - (OFFSET, MASK, VALUE) (0XFF5E023C, 0x00000540U ,0x00000000U) - RegMask = (CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK | CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK | CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK | 0 ); + * Master Tri-state Enable for pin 14, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI 0 - RegVal = ((0x00000000U << CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT - | 0x00000000U << CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT - | 0x00000000U << CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RST_LPD_TOP_OFFSET ,0x00000540U ,0x00000000U); - /*############################################################################################################################ */ + * Master Tri-state Enable for pin 15, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI 0 - // : FPD RESET - /*Register : RST_FPD_TOP @ 0XFD1A0100

+ * Master Tri-state Enable for pin 16, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI 0 - PCIE config reset - PSU_CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET 0 + * Master Tri-state Enable for pin 17, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI 0 - PCIE control block level reset - PSU_CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET 0 + * Master Tri-state Enable for pin 18, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI 1 - PCIE bridge block level reset (AXI interface) - PSU_CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET 0 + * Master Tri-state Enable for pin 19, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI 0 - Display Port block level reset (includes DPDMA) - PSU_CRF_APB_RST_FPD_TOP_DP_RESET 0 + * Master Tri-state Enable for pin 20, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI 0 - FPD WDT reset - PSU_CRF_APB_RST_FPD_TOP_SWDT_RESET 0 + * Master Tri-state Enable for pin 21, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI 1 - GDMA block level reset - PSU_CRF_APB_RST_FPD_TOP_GDMA_RESET 0 + * Master Tri-state Enable for pin 22, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI 0 - Pixel Processor (submodule of GPU) block level reset - PSU_CRF_APB_RST_FPD_TOP_GPU_PP0_RESET 0 + * Master Tri-state Enable for pin 23, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI 0 - Pixel Processor (submodule of GPU) block level reset - PSU_CRF_APB_RST_FPD_TOP_GPU_PP1_RESET 0 + * Master Tri-state Enable for pin 24, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI 0 - GPU block level reset - PSU_CRF_APB_RST_FPD_TOP_GPU_RESET 0 + * Master Tri-state Enable for pin 25, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI 1 - GT block level reset - PSU_CRF_APB_RST_FPD_TOP_GT_RESET 0 + * Master Tri-state Enable for pin 26, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI 0 - Sata block level reset - PSU_CRF_APB_RST_FPD_TOP_SATA_RESET 0 + * Master Tri-state Enable for pin 27, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI 0 - FPD Block level software controlled reset - (OFFSET, MASK, VALUE) (0XFD1A0100, 0x000F807EU ,0x00000000U) - RegMask = (CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK | CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK | CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK | CRF_APB_RST_FPD_TOP_DP_RESET_MASK | CRF_APB_RST_FPD_TOP_SWDT_RESET_MASK | CRF_APB_RST_FPD_TOP_GDMA_RESET_MASK | CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_MASK | CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_MASK | CRF_APB_RST_FPD_TOP_GPU_RESET_MASK | CRF_APB_RST_FPD_TOP_GT_RESET_MASK | CRF_APB_RST_FPD_TOP_SATA_RESET_MASK | 0 ); + * Master Tri-state Enable for pin 28, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI 1 - RegVal = ((0x00000000U << CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT - | 0x00000000U << CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT - | 0x00000000U << CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT - | 0x00000000U << CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT - | 0x00000000U << CRF_APB_RST_FPD_TOP_SWDT_RESET_SHIFT - | 0x00000000U << CRF_APB_RST_FPD_TOP_GDMA_RESET_SHIFT - | 0x00000000U << CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_SHIFT - | 0x00000000U << CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_SHIFT - | 0x00000000U << CRF_APB_RST_FPD_TOP_GPU_RESET_SHIFT - | 0x00000000U << CRF_APB_RST_FPD_TOP_GT_RESET_SHIFT - | 0x00000000U << CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_RST_FPD_TOP_OFFSET ,0x000F807EU ,0x00000000U); - /*############################################################################################################################ */ + * Master Tri-state Enable for pin 29, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI 0 - // : SD - /*Register : RST_LPD_IOU2 @ 0XFF5E0238

+ * Master Tri-state Enable for pin 30, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI 1 - Block level reset - PSU_CRL_APB_RST_LPD_IOU2_SDIO1_RESET 0 + * Master Tri-state Enable for pin 31, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI 0 - Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset. - (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000040U ,0x00000000U) - RegMask = (CRL_APB_RST_LPD_IOU2_SDIO1_RESET_MASK | 0 ); + * MIO pin Tri-state Enables, 31:0 + * (OFFSET, MASK, VALUE) (0XFF180204, 0xFFFFFFFFU ,0x52240000U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_MST_TRI0_OFFSET, + 0xFFFFFFFFU, 0x52240000U); +/*##################################################################### */ - RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU2_SDIO1_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RST_LPD_IOU2_OFFSET ,0x00000040U ,0x00000000U); - /*############################################################################################################################ */ + /* + * Register : MIO_MST_TRI1 @ 0XFF180208 - /*Register : CTRL_REG_SD @ 0XFF180310

+ * Master Tri-state Enable for pin 32, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI 0 - SD or eMMC selection on SDIO1 0: SD enabled 1: eMMC enabled - PSU_IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL 0 + * Master Tri-state Enable for pin 33, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI 0 - SD eMMC selection - (OFFSET, MASK, VALUE) (0XFF180310, 0x00008000U ,0x00000000U) - RegMask = (IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_MASK | 0 ); + * Master Tri-state Enable for pin 34, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI 0 - RegVal = ((0x00000000U << IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_CTRL_REG_SD_OFFSET ,0x00008000U ,0x00000000U); - /*############################################################################################################################ */ + * Master Tri-state Enable for pin 35, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI 0 - /*Register : SD_CONFIG_REG2 @ 0XFF180320

+ * Master Tri-state Enable for pin 36, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI 0 - Should be set based on the final product usage 00 - Removable SCard Slot 01 - Embedded Slot for One Device 10 - Shared Bus Sl - t 11 - Reserved - PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE 0 + * Master Tri-state Enable for pin 37, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI 0 - 1.8V Support 1: 1.8V supported 0: 1.8V not supported support - PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V 0 + * Master Tri-state Enable for pin 38, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI 0 - 3.0V Support 1: 3.0V supported 0: 3.0V not supported support - PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V 0 + * Master Tri-state Enable for pin 39, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI 0 - 3.3V Support 1: 3.3V supported 0: 3.3V not supported support - PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V 1 + * Master Tri-state Enable for pin 40, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI 0 - SD Config Register 2 - (OFFSET, MASK, VALUE) (0XFF180320, 0x33800000U ,0x00800000U) - RegMask = (IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_MASK | IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_MASK | IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_MASK | IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_MASK | 0 ); + * Master Tri-state Enable for pin 41, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI 0 - RegVal = ((0x00000000U << IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_SHIFT - | 0x00000000U << IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_SHIFT - | 0x00000000U << IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_SHIFT - | 0x00000001U << IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_SD_CONFIG_REG2_OFFSET ,0x33800000U ,0x00800000U); - /*############################################################################################################################ */ + * Master Tri-state Enable for pin 42, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI 0 - // : SD1 BASE CLOCK - /*Register : SD_CONFIG_REG1 @ 0XFF18031C

+ * Master Tri-state Enable for pin 43, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI 0 - Base Clock Frequency for SD Clock. This is the frequency of the xin_clk. - PSU_IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK 0xc7 + * Master Tri-state Enable for pin 44, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI 1 - SD Config Register 1 - (OFFSET, MASK, VALUE) (0XFF18031C, 0x7F800000U ,0x63800000U) - RegMask = (IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_MASK | 0 ); + * Master Tri-state Enable for pin 45, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI 1 - RegVal = ((0x000000C7U << IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_SD_CONFIG_REG1_OFFSET ,0x7F800000U ,0x63800000U); - /*############################################################################################################################ */ + * Master Tri-state Enable for pin 46, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI 0 - // : SD1 RETUNER - /*Register : SD_CONFIG_REG3 @ 0XFF180324

+ * Master Tri-state Enable for pin 47, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI 0 - This is the Timer Count for Re-Tuning Timer for Re-Tuning Mode 1 to 3. Setting to 4'b0 disables Re-Tuning Timer. 0h - Get inf - rmation via other source 1h = 1 seconds 2h = 2 seconds 3h = 4 seconds 4h = 8 seconds -- n = 2(n-1) seconds -- Bh = 1024 secon - s Fh - Ch = Reserved - PSU_IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR 0X0 + * Master Tri-state Enable for pin 48, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI 0 - SD Config Register 3 - (OFFSET, MASK, VALUE) (0XFF180324, 0x03C00000U ,0x00000000U) - RegMask = (IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_SD_CONFIG_REG3_OFFSET ,0x03C00000U ,0x00000000U); - /*############################################################################################################################ */ + * Master Tri-state Enable for pin 49, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI 0 - // : CAN - /*Register : RST_LPD_IOU2 @ 0XFF5E0238

+ * Master Tri-state Enable for pin 50, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI 0 - Block level reset - PSU_CRL_APB_RST_LPD_IOU2_CAN1_RESET 0 + * Master Tri-state Enable for pin 51, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI 0 - Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset. - (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000100U ,0x00000000U) - RegMask = (CRL_APB_RST_LPD_IOU2_CAN1_RESET_MASK | 0 ); + * Master Tri-state Enable for pin 52, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI 1 - RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU2_CAN1_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RST_LPD_IOU2_OFFSET ,0x00000100U ,0x00000000U); - /*############################################################################################################################ */ + * Master Tri-state Enable for pin 53, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI 1 - // : I2C - /*Register : RST_LPD_IOU2 @ 0XFF5E0238

+ * Master Tri-state Enable for pin 54, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI 0 - Block level reset - PSU_CRL_APB_RST_LPD_IOU2_I2C0_RESET 0 + * Master Tri-state Enable for pin 55, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI 1 - Block level reset - PSU_CRL_APB_RST_LPD_IOU2_I2C1_RESET 0 + * Master Tri-state Enable for pin 56, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI 0 - Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset. - (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000600U ,0x00000000U) - RegMask = (CRL_APB_RST_LPD_IOU2_I2C0_RESET_MASK | CRL_APB_RST_LPD_IOU2_I2C1_RESET_MASK | 0 ); + * Master Tri-state Enable for pin 57, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI 0 - RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU2_I2C0_RESET_SHIFT - | 0x00000000U << CRL_APB_RST_LPD_IOU2_I2C1_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RST_LPD_IOU2_OFFSET ,0x00000600U ,0x00000000U); - /*############################################################################################################################ */ + * Master Tri-state Enable for pin 58, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI 0 - // : SWDT - /*Register : RST_LPD_IOU2 @ 0XFF5E0238

+ * Master Tri-state Enable for pin 59, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI 0 - Block level reset - PSU_CRL_APB_RST_LPD_IOU2_SWDT_RESET 0 + * Master Tri-state Enable for pin 60, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI 0 - Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset. - (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00008000U ,0x00000000U) - RegMask = (CRL_APB_RST_LPD_IOU2_SWDT_RESET_MASK | 0 ); + * Master Tri-state Enable for pin 61, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI 0 - RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU2_SWDT_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RST_LPD_IOU2_OFFSET ,0x00008000U ,0x00000000U); - /*############################################################################################################################ */ + * Master Tri-state Enable for pin 62, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI 0 - // : SPI - // : TTC - /*Register : RST_LPD_IOU2 @ 0XFF5E0238

+ * Master Tri-state Enable for pin 63, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI 0 - Block level reset - PSU_CRL_APB_RST_LPD_IOU2_TTC0_RESET 0 + * MIO pin Tri-state Enables, 63:32 + * (OFFSET, MASK, VALUE) (0XFF180208, 0xFFFFFFFFU ,0x00B03000U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_MST_TRI1_OFFSET, + 0xFFFFFFFFU, 0x00B03000U); +/*##################################################################### */ - Block level reset - PSU_CRL_APB_RST_LPD_IOU2_TTC1_RESET 0 + /* + * Register : MIO_MST_TRI2 @ 0XFF18020C - Block level reset - PSU_CRL_APB_RST_LPD_IOU2_TTC2_RESET 0 + * Master Tri-state Enable for pin 64, active high + * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI 0 - Block level reset - PSU_CRL_APB_RST_LPD_IOU2_TTC3_RESET 0 + * Master Tri-state Enable for pin 65, active high + * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI 0 - Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset. - (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00007800U ,0x00000000U) - RegMask = (CRL_APB_RST_LPD_IOU2_TTC0_RESET_MASK | CRL_APB_RST_LPD_IOU2_TTC1_RESET_MASK | CRL_APB_RST_LPD_IOU2_TTC2_RESET_MASK | CRL_APB_RST_LPD_IOU2_TTC3_RESET_MASK | 0 ); + * Master Tri-state Enable for pin 66, active high + * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI 0 - RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU2_TTC0_RESET_SHIFT - | 0x00000000U << CRL_APB_RST_LPD_IOU2_TTC1_RESET_SHIFT - | 0x00000000U << CRL_APB_RST_LPD_IOU2_TTC2_RESET_SHIFT - | 0x00000000U << CRL_APB_RST_LPD_IOU2_TTC3_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RST_LPD_IOU2_OFFSET ,0x00007800U ,0x00000000U); - /*############################################################################################################################ */ + * Master Tri-state Enable for pin 67, active high + * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI 0 - // : UART - /*Register : RST_LPD_IOU2 @ 0XFF5E0238

+ * Master Tri-state Enable for pin 68, active high + * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI 0 - Block level reset - PSU_CRL_APB_RST_LPD_IOU2_UART0_RESET 0 + * Master Tri-state Enable for pin 69, active high + * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI 0 - Block level reset - PSU_CRL_APB_RST_LPD_IOU2_UART1_RESET 0 + * Master Tri-state Enable for pin 70, active high + * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI 1 - Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset. - (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000006U ,0x00000000U) - RegMask = (CRL_APB_RST_LPD_IOU2_UART0_RESET_MASK | CRL_APB_RST_LPD_IOU2_UART1_RESET_MASK | 0 ); + * Master Tri-state Enable for pin 71, active high + * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI 1 - RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU2_UART0_RESET_SHIFT - | 0x00000000U << CRL_APB_RST_LPD_IOU2_UART1_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RST_LPD_IOU2_OFFSET ,0x00000006U ,0x00000000U); - /*############################################################################################################################ */ + * Master Tri-state Enable for pin 72, active high + * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI 1 - // : UART BAUD RATE - /*Register : Baud_rate_divider_reg0 @ 0XFF000034

+ * Master Tri-state Enable for pin 73, active high + * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI 1 - Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate - PSU_UART0_BAUD_RATE_DIVIDER_REG0_BDIV 0x5 + * Master Tri-state Enable for pin 74, active high + * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI 1 - Baud Rate Divider Register - (OFFSET, MASK, VALUE) (0XFF000034, 0x000000FFU ,0x00000005U) - RegMask = (UART0_BAUD_RATE_DIVIDER_REG0_BDIV_MASK | 0 ); + * Master Tri-state Enable for pin 75, active high + * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI 1 - RegVal = ((0x00000005U << UART0_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (UART0_BAUD_RATE_DIVIDER_REG0_OFFSET ,0x000000FFU ,0x00000005U); - /*############################################################################################################################ */ + * Master Tri-state Enable for pin 76, active high + * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI 0 - /*Register : Baud_rate_gen_reg0 @ 0XFF000018

+ * Master Tri-state Enable for pin 77, active high + * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI 0 - Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample - PSU_UART0_BAUD_RATE_GEN_REG0_CD 0x8f + * MIO pin Tri-state Enables, 77:64 + * (OFFSET, MASK, VALUE) (0XFF18020C, 0x00003FFFU ,0x00000FC0U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_MST_TRI2_OFFSET, + 0x00003FFFU, 0x00000FC0U); +/*##################################################################### */ - Baud Rate Generator Register. - (OFFSET, MASK, VALUE) (0XFF000018, 0x0000FFFFU ,0x0000008FU) - RegMask = (UART0_BAUD_RATE_GEN_REG0_CD_MASK | 0 ); + /* + * Register : bank0_ctrl0 @ 0XFF180138 - RegVal = ((0x0000008FU << UART0_BAUD_RATE_GEN_REG0_CD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (UART0_BAUD_RATE_GEN_REG0_OFFSET ,0x0000FFFFU ,0x0000008FU); - /*############################################################################################################################ */ + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0 1 - /*Register : Control_reg0 @ 0XFF000000

+ * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1 1 - Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a - high level during 12 bit periods. It can be set regardless of the value of STTBRK. - PSU_UART0_CONTROL_REG0_STPBRK 0x0 + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2 1 - Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the - transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high. - PSU_UART0_CONTROL_REG0_STTBRK 0x0 + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3 1 - Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has co - pleted. - PSU_UART0_CONTROL_REG0_RSTTO 0x0 + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4 1 - Transmit disable: 0: enable transmitter 1: disable transmitter - PSU_UART0_CONTROL_REG0_TXDIS 0x0 + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5 1 - Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0. - PSU_UART0_CONTROL_REG0_TXEN 0x1 + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6 1 - Receive disable: 0: enable 1: disable, regardless of the value of RXEN - PSU_UART0_CONTROL_REG0_RXDIS 0x0 + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7 1 - Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero. - PSU_UART0_CONTROL_REG0_RXEN 0x1 + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8 1 - Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded Thi - bit is self clearing once the reset has completed. - PSU_UART0_CONTROL_REG0_TXRES 0x1 + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9 1 - Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit - is self clearing once the reset has completed. - PSU_UART0_CONTROL_REG0_RXRES 0x1 + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10 1 - UART Control Register - (OFFSET, MASK, VALUE) (0XFF000000, 0x000001FFU ,0x00000017U) - RegMask = (UART0_CONTROL_REG0_STPBRK_MASK | UART0_CONTROL_REG0_STTBRK_MASK | UART0_CONTROL_REG0_RSTTO_MASK | UART0_CONTROL_REG0_TXDIS_MASK | UART0_CONTROL_REG0_TXEN_MASK | UART0_CONTROL_REG0_RXDIS_MASK | UART0_CONTROL_REG0_RXEN_MASK | UART0_CONTROL_REG0_TXRES_MASK | UART0_CONTROL_REG0_RXRES_MASK | 0 ); + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11 1 - RegVal = ((0x00000000U << UART0_CONTROL_REG0_STPBRK_SHIFT - | 0x00000000U << UART0_CONTROL_REG0_STTBRK_SHIFT - | 0x00000000U << UART0_CONTROL_REG0_RSTTO_SHIFT - | 0x00000000U << UART0_CONTROL_REG0_TXDIS_SHIFT - | 0x00000001U << UART0_CONTROL_REG0_TXEN_SHIFT - | 0x00000000U << UART0_CONTROL_REG0_RXDIS_SHIFT - | 0x00000001U << UART0_CONTROL_REG0_RXEN_SHIFT - | 0x00000001U << UART0_CONTROL_REG0_TXRES_SHIFT - | 0x00000001U << UART0_CONTROL_REG0_RXRES_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (UART0_CONTROL_REG0_OFFSET ,0x000001FFU ,0x00000017U); - /*############################################################################################################################ */ + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12 1 - /*Register : mode_reg0 @ 0XFF000004

+ * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13 1 - Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback - PSU_UART0_MODE_REG0_CHMODE 0x0 + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14 1 - Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5 - stop bits 10: 2 stop bits 11: reserved - PSU_UART0_MODE_REG0_NBSTOP 0x0 + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15 1 - Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity - 01: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity - PSU_UART0_MODE_REG0_PAR 0x4 + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16 1 - Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits - PSU_UART0_MODE_REG0_CHRL 0x0 + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17 1 - Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock - source is uart_ref_clk 1: clock source is uart_ref_clk/8 - PSU_UART0_MODE_REG0_CLKS 0x0 + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18 1 - UART Mode Register - (OFFSET, MASK, VALUE) (0XFF000004, 0x000003FFU ,0x00000020U) - RegMask = (UART0_MODE_REG0_CHMODE_MASK | UART0_MODE_REG0_NBSTOP_MASK | UART0_MODE_REG0_PAR_MASK | UART0_MODE_REG0_CHRL_MASK | UART0_MODE_REG0_CLKS_MASK | 0 ); + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19 1 - RegVal = ((0x00000000U << UART0_MODE_REG0_CHMODE_SHIFT - | 0x00000000U << UART0_MODE_REG0_NBSTOP_SHIFT - | 0x00000004U << UART0_MODE_REG0_PAR_SHIFT - | 0x00000000U << UART0_MODE_REG0_CHRL_SHIFT - | 0x00000000U << UART0_MODE_REG0_CLKS_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (UART0_MODE_REG0_OFFSET ,0x000003FFU ,0x00000020U); - /*############################################################################################################################ */ + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20 1 - /*Register : Baud_rate_divider_reg0 @ 0XFF010034

+ * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21 1 - Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate - PSU_UART1_BAUD_RATE_DIVIDER_REG0_BDIV 0x5 + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22 1 - Baud Rate Divider Register - (OFFSET, MASK, VALUE) (0XFF010034, 0x000000FFU ,0x00000005U) - RegMask = (UART1_BAUD_RATE_DIVIDER_REG0_BDIV_MASK | 0 ); - - RegVal = ((0x00000005U << UART1_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (UART1_BAUD_RATE_DIVIDER_REG0_OFFSET ,0x000000FFU ,0x00000005U); - /*############################################################################################################################ */ - - /*Register : Baud_rate_gen_reg0 @ 0XFF010018

+ * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23 1 - Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample - PSU_UART1_BAUD_RATE_GEN_REG0_CD 0x8f - - Baud Rate Generator Register. - (OFFSET, MASK, VALUE) (0XFF010018, 0x0000FFFFU ,0x0000008FU) - RegMask = (UART1_BAUD_RATE_GEN_REG0_CD_MASK | 0 ); - - RegVal = ((0x0000008FU << UART1_BAUD_RATE_GEN_REG0_CD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (UART1_BAUD_RATE_GEN_REG0_OFFSET ,0x0000FFFFU ,0x0000008FU); - /*############################################################################################################################ */ - - /*Register : Control_reg0 @ 0XFF010000

- - Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a - high level during 12 bit periods. It can be set regardless of the value of STTBRK. - PSU_UART1_CONTROL_REG0_STPBRK 0x0 - - Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the - transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high. - PSU_UART1_CONTROL_REG0_STTBRK 0x0 - - Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has co - pleted. - PSU_UART1_CONTROL_REG0_RSTTO 0x0 - - Transmit disable: 0: enable transmitter 1: disable transmitter - PSU_UART1_CONTROL_REG0_TXDIS 0x0 - - Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0. - PSU_UART1_CONTROL_REG0_TXEN 0x1 - - Receive disable: 0: enable 1: disable, regardless of the value of RXEN - PSU_UART1_CONTROL_REG0_RXDIS 0x0 - - Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero. - PSU_UART1_CONTROL_REG0_RXEN 0x1 + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24 1 - Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded Thi - bit is self clearing once the reset has completed. - PSU_UART1_CONTROL_REG0_TXRES 0x1 + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25 1 - Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit - is self clearing once the reset has completed. - PSU_UART1_CONTROL_REG0_RXRES 0x1 + * Drive0 control to MIO Bank 0 - control MIO[25:0] + * (OFFSET, MASK, VALUE) (0XFF180138, 0x03FFFFFFU ,0x03FFFFFFU) + */ + PSU_Mask_Write(IOU_SLCR_BANK0_CTRL0_OFFSET, + 0x03FFFFFFU, 0x03FFFFFFU); +/*##################################################################### */ - UART Control Register - (OFFSET, MASK, VALUE) (0XFF010000, 0x000001FFU ,0x00000017U) - RegMask = (UART1_CONTROL_REG0_STPBRK_MASK | UART1_CONTROL_REG0_STTBRK_MASK | UART1_CONTROL_REG0_RSTTO_MASK | UART1_CONTROL_REG0_TXDIS_MASK | UART1_CONTROL_REG0_TXEN_MASK | UART1_CONTROL_REG0_RXDIS_MASK | UART1_CONTROL_REG0_RXEN_MASK | UART1_CONTROL_REG0_TXRES_MASK | UART1_CONTROL_REG0_RXRES_MASK | 0 ); + /* + * Register : bank0_ctrl1 @ 0XFF18013C - RegVal = ((0x00000000U << UART1_CONTROL_REG0_STPBRK_SHIFT - | 0x00000000U << UART1_CONTROL_REG0_STTBRK_SHIFT - | 0x00000000U << UART1_CONTROL_REG0_RSTTO_SHIFT - | 0x00000000U << UART1_CONTROL_REG0_TXDIS_SHIFT - | 0x00000001U << UART1_CONTROL_REG0_TXEN_SHIFT - | 0x00000000U << UART1_CONTROL_REG0_RXDIS_SHIFT - | 0x00000001U << UART1_CONTROL_REG0_RXEN_SHIFT - | 0x00000001U << UART1_CONTROL_REG0_TXRES_SHIFT - | 0x00000001U << UART1_CONTROL_REG0_RXRES_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (UART1_CONTROL_REG0_OFFSET ,0x000001FFU ,0x00000017U); - /*############################################################################################################################ */ + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0 1 - /*Register : mode_reg0 @ 0XFF010004

+ * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1 1 - Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback - PSU_UART1_MODE_REG0_CHMODE 0x0 + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2 1 - Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5 - stop bits 10: 2 stop bits 11: reserved - PSU_UART1_MODE_REG0_NBSTOP 0x0 - - Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity - 01: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity - PSU_UART1_MODE_REG0_PAR 0x4 - - Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits - PSU_UART1_MODE_REG0_CHRL 0x0 - - Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock - source is uart_ref_clk 1: clock source is uart_ref_clk/8 - PSU_UART1_MODE_REG0_CLKS 0x0 + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3 1 - UART Mode Register - (OFFSET, MASK, VALUE) (0XFF010004, 0x000003FFU ,0x00000020U) - RegMask = (UART1_MODE_REG0_CHMODE_MASK | UART1_MODE_REG0_NBSTOP_MASK | UART1_MODE_REG0_PAR_MASK | UART1_MODE_REG0_CHRL_MASK | UART1_MODE_REG0_CLKS_MASK | 0 ); + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4 1 - RegVal = ((0x00000000U << UART1_MODE_REG0_CHMODE_SHIFT - | 0x00000000U << UART1_MODE_REG0_NBSTOP_SHIFT - | 0x00000004U << UART1_MODE_REG0_PAR_SHIFT - | 0x00000000U << UART1_MODE_REG0_CHRL_SHIFT - | 0x00000000U << UART1_MODE_REG0_CLKS_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (UART1_MODE_REG0_OFFSET ,0x000003FFU ,0x00000020U); - /*############################################################################################################################ */ - - // : GPIO - // : ADMA TZ - /*Register : slcr_adma @ 0XFF4B0024

+ * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5 1 - TrustZone Classification for ADMA - PSU_LPD_SLCR_SECURE_SLCR_ADMA_TZ 0XFF - - RPU TrustZone settings - (OFFSET, MASK, VALUE) (0XFF4B0024, 0x000000FFU ,0x000000FFU) - RegMask = (LPD_SLCR_SECURE_SLCR_ADMA_TZ_MASK | 0 ); - - RegVal = ((0x000000FFU << LPD_SLCR_SECURE_SLCR_ADMA_TZ_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (LPD_SLCR_SECURE_SLCR_ADMA_OFFSET ,0x000000FFU ,0x000000FFU); - /*############################################################################################################################ */ - - // : CSU TAMPERING - // : CSU TAMPER STATUS - /*Register : tamper_status @ 0XFFCA5000

- - CSU regsiter - PSU_CSU_TAMPER_STATUS_TAMPER_0 0 - - External MIO - PSU_CSU_TAMPER_STATUS_TAMPER_1 0 - - JTAG toggle detect - PSU_CSU_TAMPER_STATUS_TAMPER_2 0 - - PL SEU error - PSU_CSU_TAMPER_STATUS_TAMPER_3 0 - - AMS over temperature alarm for LPD - PSU_CSU_TAMPER_STATUS_TAMPER_4 0 - - AMS over temperature alarm for APU - PSU_CSU_TAMPER_STATUS_TAMPER_5 0 - - AMS voltage alarm for VCCPINT_FPD - PSU_CSU_TAMPER_STATUS_TAMPER_6 0 - - AMS voltage alarm for VCCPINT_LPD - PSU_CSU_TAMPER_STATUS_TAMPER_7 0 - - AMS voltage alarm for VCCPAUX - PSU_CSU_TAMPER_STATUS_TAMPER_8 0 - - AMS voltage alarm for DDRPHY - PSU_CSU_TAMPER_STATUS_TAMPER_9 0 - - AMS voltage alarm for PSIO bank 0/1/2 - PSU_CSU_TAMPER_STATUS_TAMPER_10 0 - - AMS voltage alarm for PSIO bank 3 (dedicated pins) - PSU_CSU_TAMPER_STATUS_TAMPER_11 0 - - AMS voltaage alarm for GT - PSU_CSU_TAMPER_STATUS_TAMPER_12 0 - - Tamper Response Status - (OFFSET, MASK, VALUE) (0XFFCA5000, 0x00001FFFU ,0x00000000U) - RegMask = (CSU_TAMPER_STATUS_TAMPER_0_MASK | CSU_TAMPER_STATUS_TAMPER_1_MASK | CSU_TAMPER_STATUS_TAMPER_2_MASK | CSU_TAMPER_STATUS_TAMPER_3_MASK | CSU_TAMPER_STATUS_TAMPER_4_MASK | CSU_TAMPER_STATUS_TAMPER_5_MASK | CSU_TAMPER_STATUS_TAMPER_6_MASK | CSU_TAMPER_STATUS_TAMPER_7_MASK | CSU_TAMPER_STATUS_TAMPER_8_MASK | CSU_TAMPER_STATUS_TAMPER_9_MASK | CSU_TAMPER_STATUS_TAMPER_10_MASK | CSU_TAMPER_STATUS_TAMPER_11_MASK | CSU_TAMPER_STATUS_TAMPER_12_MASK | 0 ); + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6 1 - RegVal = ((0x00000000U << CSU_TAMPER_STATUS_TAMPER_0_SHIFT - | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_1_SHIFT - | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_2_SHIFT - | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_3_SHIFT - | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_4_SHIFT - | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_5_SHIFT - | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_6_SHIFT - | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_7_SHIFT - | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_8_SHIFT - | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_9_SHIFT - | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_10_SHIFT - | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_11_SHIFT - | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_12_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CSU_TAMPER_STATUS_OFFSET ,0x00001FFFU ,0x00000000U); - /*############################################################################################################################ */ + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7 1 - // : CSU TAMPER RESPONSE - // : AFIFM INTERFACE WIDTH - // : CPU QOS DEFAULT - /*Register : ACE_CTRL @ 0XFD5C0060

- - Set ACE outgoing AWQOS value - PSU_APU_ACE_CTRL_AWQOS 0X0 - - Set ACE outgoing ARQOS value - PSU_APU_ACE_CTRL_ARQOS 0X0 + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8 1 - ACE Control Register - (OFFSET, MASK, VALUE) (0XFD5C0060, 0x000F000FU ,0x00000000U) - RegMask = (APU_ACE_CTRL_AWQOS_MASK | APU_ACE_CTRL_ARQOS_MASK | 0 ); + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9 1 - RegVal = ((0x00000000U << APU_ACE_CTRL_AWQOS_SHIFT - | 0x00000000U << APU_ACE_CTRL_ARQOS_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (APU_ACE_CTRL_OFFSET ,0x000F000FU ,0x00000000U); - /*############################################################################################################################ */ + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10 1 - // : ENABLES RTC SWITCH TO BATTERY WHEN VCC_PSAUX IS NOT AVAILABLE - /*Register : CONTROL @ 0XFFA60040

+ * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11 1 - Enables the RTC. By writing a 0 to this bit, RTC will be powered off and the only module that potentially draws current from - he battery will be BBRAM. The value read through this bit does not necessarily reflect whether RTC is enabled or not. It is e - pected that RTC is enabled every time it is being configured. If RTC is not used in the design, FSBL will disable it by writi - g a 0 to this bit. - PSU_RTC_CONTROL_BATTERY_DISABLE 0X1 + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12 1 - This register controls various functionalities within the RTC - (OFFSET, MASK, VALUE) (0XFFA60040, 0x80000000U ,0x80000000U) - RegMask = (RTC_CONTROL_BATTERY_DISABLE_MASK | 0 ); + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13 1 - RegVal = ((0x00000001U << RTC_CONTROL_BATTERY_DISABLE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (RTC_CONTROL_OFFSET ,0x80000000U ,0x80000000U); - /*############################################################################################################################ */ + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14 1 - // : TIMESTAMP COUNTER - /*Register : base_frequency_ID_register @ 0XFF260020

+ * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15 1 - Frequency in number of ticks per second. Valid range from 10 MHz to 100 MHz. - PSU_IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ 0x5f5e100 + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16 1 - Program this register to match the clock frequency of the timestamp generator, in ticks per second. For example, for a 50 MHz - clock, program 0x02FAF080. This register is not accessible to the read-only programming interface. - (OFFSET, MASK, VALUE) (0XFF260020, 0xFFFFFFFFU ,0x05F5E100U) - RegMask = (IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_MASK | 0 ); + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17 1 - RegVal = ((0x05F5E100U << IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_OFFSET ,0xFFFFFFFFU ,0x05F5E100U); - /*############################################################################################################################ */ + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18 1 - /*Register : counter_control_register @ 0XFF260000

- - Enable 0: The counter is disabled and not incrementing. 1: The counter is enabled and is incrementing. - PSU_IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN 0x1 - - Controls the counter increments. This register is not accessible to the read-only programming interface. - (OFFSET, MASK, VALUE) (0XFF260000, 0x00000001U ,0x00000001U) - RegMask = (IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SCNTRS_COUNTER_CONTROL_REGISTER_OFFSET ,0x00000001U ,0x00000001U); - /*############################################################################################################################ */ - - // : TTC SRC SELECT - - return 1; + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25 1 + + * Drive1 control to MIO Bank 0 - control MIO[25:0] + * (OFFSET, MASK, VALUE) (0XFF18013C, 0x03FFFFFFU ,0x03FFFFFFU) + */ + PSU_Mask_Write(IOU_SLCR_BANK0_CTRL1_OFFSET, + 0x03FFFFFFU, 0x03FFFFFFU); +/*##################################################################### */ + + /* + * Register : bank0_ctrl3 @ 0XFF180140 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25 0 + + * Selects either Schmitt or CMOS input for MIO Bank 0 - control MIO[25:0] + * (OFFSET, MASK, VALUE) (0XFF180140, 0x03FFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_BANK0_CTRL3_OFFSET, + 0x03FFFFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : bank0_ctrl4 @ 0XFF180144 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25 1 + + * When mio_bank0_pull_enable is set, this selects pull up or pull down for + * MIO Bank 0 - control MIO[25:0] + * (OFFSET, MASK, VALUE) (0XFF180144, 0x03FFFFFFU ,0x03FFFFFFU) + */ + PSU_Mask_Write(IOU_SLCR_BANK0_CTRL4_OFFSET, + 0x03FFFFFFU, 0x03FFFFFFU); +/*##################################################################### */ + + /* + * Register : bank0_ctrl5 @ 0XFF180148 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25 1 + + * When set, this enables mio_bank0_pullupdown to selects pull up or pull d + * own for MIO Bank 0 - control MIO[25:0] + * (OFFSET, MASK, VALUE) (0XFF180148, 0x03FFFFFFU ,0x03FFFFFFU) + */ + PSU_Mask_Write(IOU_SLCR_BANK0_CTRL5_OFFSET, + 0x03FFFFFFU, 0x03FFFFFFU); +/*##################################################################### */ + + /* + * Register : bank0_ctrl6 @ 0XFF18014C + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25 0 + + * Slew rate control to MIO Bank 0 - control MIO[25:0] + * (OFFSET, MASK, VALUE) (0XFF18014C, 0x03FFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_BANK0_CTRL6_OFFSET, + 0x03FFFFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : bank1_ctrl0 @ 0XFF180154 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25 1 + + * Drive0 control to MIO Bank 1 - control MIO[51:26] + * (OFFSET, MASK, VALUE) (0XFF180154, 0x03FFFFFFU ,0x03FFFFFFU) + */ + PSU_Mask_Write(IOU_SLCR_BANK1_CTRL0_OFFSET, + 0x03FFFFFFU, 0x03FFFFFFU); +/*##################################################################### */ + + /* + * Register : bank1_ctrl1 @ 0XFF180158 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25 1 + + * Drive1 control to MIO Bank 1 - control MIO[51:26] + * (OFFSET, MASK, VALUE) (0XFF180158, 0x03FFFFFFU ,0x03FFFFFFU) + */ + PSU_Mask_Write(IOU_SLCR_BANK1_CTRL1_OFFSET, + 0x03FFFFFFU, 0x03FFFFFFU); +/*##################################################################### */ + + /* + * Register : bank1_ctrl3 @ 0XFF18015C + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25 0 + + * Selects either Schmitt or CMOS input for MIO Bank 1 - control MIO[51:26] + * (OFFSET, MASK, VALUE) (0XFF18015C, 0x03FFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_BANK1_CTRL3_OFFSET, + 0x03FFFFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : bank1_ctrl4 @ 0XFF180160 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25 1 + + * When mio_bank1_pull_enable is set, this selects pull up or pull down for + * MIO Bank 1 - control MIO[51:26] + * (OFFSET, MASK, VALUE) (0XFF180160, 0x03FFFFFFU ,0x03FFFFFFU) + */ + PSU_Mask_Write(IOU_SLCR_BANK1_CTRL4_OFFSET, + 0x03FFFFFFU, 0x03FFFFFFU); +/*##################################################################### */ + + /* + * Register : bank1_ctrl5 @ 0XFF180164 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25 1 + + * When set, this enables mio_bank1_pullupdown to selects pull up or pull d + * own for MIO Bank 1 - control MIO[51:26] + * (OFFSET, MASK, VALUE) (0XFF180164, 0x03FFFFFFU ,0x03FFFFFFU) + */ + PSU_Mask_Write(IOU_SLCR_BANK1_CTRL5_OFFSET, + 0x03FFFFFFU, 0x03FFFFFFU); +/*##################################################################### */ + + /* + * Register : bank1_ctrl6 @ 0XFF180168 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25 0 + + * Slew rate control to MIO Bank 1 - control MIO[51:26] + * (OFFSET, MASK, VALUE) (0XFF180168, 0x03FFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_BANK1_CTRL6_OFFSET, + 0x03FFFFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : bank2_ctrl0 @ 0XFF180170 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25 1 + + * Drive0 control to MIO Bank 2 - control MIO[77:52] + * (OFFSET, MASK, VALUE) (0XFF180170, 0x03FFFFFFU ,0x03FFFFFFU) + */ + PSU_Mask_Write(IOU_SLCR_BANK2_CTRL0_OFFSET, + 0x03FFFFFFU, 0x03FFFFFFU); +/*##################################################################### */ + + /* + * Register : bank2_ctrl1 @ 0XFF180174 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25 1 + + * Drive1 control to MIO Bank 2 - control MIO[77:52] + * (OFFSET, MASK, VALUE) (0XFF180174, 0x03FFFFFFU ,0x03FFFFFFU) + */ + PSU_Mask_Write(IOU_SLCR_BANK2_CTRL1_OFFSET, + 0x03FFFFFFU, 0x03FFFFFFU); +/*##################################################################### */ + + /* + * Register : bank2_ctrl3 @ 0XFF180178 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25 0 + + * Selects either Schmitt or CMOS input for MIO Bank 2 - control MIO[77:52] + * (OFFSET, MASK, VALUE) (0XFF180178, 0x03FFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_BANK2_CTRL3_OFFSET, + 0x03FFFFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : bank2_ctrl4 @ 0XFF18017C + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25 1 + + * When mio_bank2_pull_enable is set, this selects pull up or pull down for + * MIO Bank 2 - control MIO[77:52] + * (OFFSET, MASK, VALUE) (0XFF18017C, 0x03FFFFFFU ,0x03FFFFFFU) + */ + PSU_Mask_Write(IOU_SLCR_BANK2_CTRL4_OFFSET, + 0x03FFFFFFU, 0x03FFFFFFU); +/*##################################################################### */ + + /* + * Register : bank2_ctrl5 @ 0XFF180180 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25 1 + + * When set, this enables mio_bank2_pullupdown to selects pull up or pull d + * own for MIO Bank 2 - control MIO[77:52] + * (OFFSET, MASK, VALUE) (0XFF180180, 0x03FFFFFFU ,0x03FFFFFFU) + */ + PSU_Mask_Write(IOU_SLCR_BANK2_CTRL5_OFFSET, + 0x03FFFFFFU, 0x03FFFFFFU); +/*##################################################################### */ + + /* + * Register : bank2_ctrl6 @ 0XFF180184 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25 0 + + * Slew rate control to MIO Bank 2 - control MIO[77:52] + * (OFFSET, MASK, VALUE) (0XFF180184, 0x03FFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_BANK2_CTRL6_OFFSET, + 0x03FFFFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * LOOPBACK + */ + /* + * Register : MIO_LOOPBACK @ 0XFF180200 + + * I2C Loopback Control. 0 = Connect I2C inputs according to MIO mapping. 1 + * = Loop I2C 0 outputs to I2C 1 inputs, and I2C 1 outputs to I2C 0 inputs + * . + * PSU_IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1 0 + + * CAN Loopback Control. 0 = Connect CAN inputs according to MIO mapping. 1 + * = Loop CAN 0 Tx to CAN 1 Rx, and CAN 1 Tx to CAN 0 Rx. + * PSU_IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1 0 + + * UART Loopback Control. 0 = Connect UART inputs according to MIO mapping. + * 1 = Loop UART 0 outputs to UART 1 inputs, and UART 1 outputs to UART 0 + * inputs. RXD/TXD cross-connected. RTS/CTS cross-connected. DSR, DTR, DCD + * and RI not used. + * PSU_IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1 0 + + * SPI Loopback Control. 0 = Connect SPI inputs according to MIO mapping. 1 + * = Loop SPI 0 outputs to SPI 1 inputs, and SPI 1 outputs to SPI 0 inputs + * . The other SPI core will appear on the LS Slave Select. + * PSU_IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1 0 + + * Loopback function within MIO + * (OFFSET, MASK, VALUE) (0XFF180200, 0x0000000FU ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_LOOPBACK_OFFSET, + 0x0000000FU, 0x00000000U); +/*##################################################################### */ + + + return 1; } -unsigned long psu_post_config_data() { - // : POST_CONFIG +unsigned long psu_peripherals_init_data(void) +{ + /* + * COHERENCY + */ + /* + * FPD RESET + */ + /* + * Register : RST_FPD_TOP @ 0XFD1A0100 - return 1; + * PCIE config reset + * PSU_CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET 0 + + * PCIE control block level reset + * PSU_CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET 0 + + * PCIE bridge block level reset (AXI interface) + * PSU_CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET 0 + + * Display Port block level reset (includes DPDMA) + * PSU_CRF_APB_RST_FPD_TOP_DP_RESET 0 + + * FPD WDT reset + * PSU_CRF_APB_RST_FPD_TOP_SWDT_RESET 0 + + * GDMA block level reset + * PSU_CRF_APB_RST_FPD_TOP_GDMA_RESET 0 + + * Pixel Processor (submodule of GPU) block level reset + * PSU_CRF_APB_RST_FPD_TOP_GPU_PP0_RESET 0 + + * Pixel Processor (submodule of GPU) block level reset + * PSU_CRF_APB_RST_FPD_TOP_GPU_PP1_RESET 0 + + * GPU block level reset + * PSU_CRF_APB_RST_FPD_TOP_GPU_RESET 0 + + * GT block level reset + * PSU_CRF_APB_RST_FPD_TOP_GT_RESET 0 + + * Sata block level reset + * PSU_CRF_APB_RST_FPD_TOP_SATA_RESET 0 + + * FPD Block level software controlled reset + * (OFFSET, MASK, VALUE) (0XFD1A0100, 0x000F807EU ,0x00000000U) + */ + PSU_Mask_Write(CRF_APB_RST_FPD_TOP_OFFSET, 0x000F807EU, 0x00000000U); +/*##################################################################### */ + + /* + * RESET BLOCKS + */ + /* + * TIMESTAMP + */ + /* + * Register : RST_LPD_IOU2 @ 0XFF5E0238 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET 0 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_IOU_CC_RESET 0 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_ADMA_RESET 0 + + * Software control register for the IOU block. Each bit will cause a singl + * erperipheral or part of the peripheral to be reset. + * (OFFSET, MASK, VALUE) (0XFF5E0238, 0x001A0000U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_IOU2_OFFSET, + 0x001A0000U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : RST_LPD_TOP @ 0XFF5E023C + + * Reset entire full power domain. + * PSU_CRL_APB_RST_LPD_TOP_FPD_RESET 0 + + * LPD SWDT + * PSU_CRL_APB_RST_LPD_TOP_LPD_SWDT_RESET 0 + + * Sysmonitor reset + * PSU_CRL_APB_RST_LPD_TOP_SYSMON_RESET 0 + + * Real Time Clock reset + * PSU_CRL_APB_RST_LPD_TOP_RTC_RESET 0 + + * APM reset + * PSU_CRL_APB_RST_LPD_TOP_APM_RESET 0 + + * IPI reset + * PSU_CRL_APB_RST_LPD_TOP_IPI_RESET 0 + + * reset entire RPU power island + * PSU_CRL_APB_RST_LPD_TOP_RPU_PGE_RESET 0 + + * reset ocm + * PSU_CRL_APB_RST_LPD_TOP_OCM_RESET 0 + + * Software control register for the LPD block. + * (OFFSET, MASK, VALUE) (0XFF5E023C, 0x0093C018U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_TOP_OFFSET, 0x0093C018U, 0x00000000U); +/*##################################################################### */ + + /* + * ENET + */ + /* + * Register : RST_LPD_IOU0 @ 0XFF5E0230 + + * GEM 3 reset + * PSU_CRL_APB_RST_LPD_IOU0_GEM3_RESET 0 + + * Software controlled reset for the GEMs + * (OFFSET, MASK, VALUE) (0XFF5E0230, 0x00000008U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_IOU0_OFFSET, + 0x00000008U, 0x00000000U); +/*##################################################################### */ + + /* + * QSPI + */ + /* + * Register : RST_LPD_IOU2 @ 0XFF5E0238 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_QSPI_RESET 0 + + * Software control register for the IOU block. Each bit will cause a singl + * erperipheral or part of the peripheral to be reset. + * (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000001U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_IOU2_OFFSET, + 0x00000001U, 0x00000000U); +/*##################################################################### */ + + /* + * QSPI TAP DELAY + */ + /* + * Register : IOU_TAPDLY_BYPASS @ 0XFF180390 + + * 0: Do not by pass the tap delays on the Rx clock signal of LQSPI 1: Bypa + * ss the Tap delay on the Rx clock signal of LQSPI + * PSU_IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX 1 + + * IOU tap delay bypass for the LQSPI and NAND controllers + * (OFFSET, MASK, VALUE) (0XFF180390, 0x00000004U ,0x00000004U) + */ + PSU_Mask_Write(IOU_SLCR_IOU_TAPDLY_BYPASS_OFFSET, + 0x00000004U, 0x00000004U); +/*##################################################################### */ + + /* + * NAND + */ + /* + * USB + */ + /* + * Register : RST_LPD_TOP @ 0XFF5E023C + + * USB 0 reset for control registers + * PSU_CRL_APB_RST_LPD_TOP_USB0_APB_RESET 0 + + * USB 0 sleep circuit reset + * PSU_CRL_APB_RST_LPD_TOP_USB0_HIBERRESET 0 + + * USB 0 reset + * PSU_CRL_APB_RST_LPD_TOP_USB0_CORERESET 0 + + * Software control register for the LPD block. + * (OFFSET, MASK, VALUE) (0XFF5E023C, 0x00000540U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_TOP_OFFSET, 0x00000540U, 0x00000000U); +/*##################################################################### */ + + /* + * USB0 PIPE POWER PRESENT + */ + /* + * Register : fpd_power_prsnt @ 0XFF9D0080 + + * This bit is used to choose between PIPE power present and 1'b1 + * PSU_USB3_0_FPD_POWER_PRSNT_OPTION 0X1 + + * fpd_power_prsnt + * (OFFSET, MASK, VALUE) (0XFF9D0080, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(USB3_0_FPD_POWER_PRSNT_OFFSET, + 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : fpd_pipe_clk @ 0XFF9D007C + + * This bit is used to choose between PIPE clock coming from SerDes and the + * suspend clk + * PSU_USB3_0_FPD_PIPE_CLK_OPTION 0x0 + + * fpd_pipe_clk + * (OFFSET, MASK, VALUE) (0XFF9D007C, 0x00000001U ,0x00000000U) + */ + PSU_Mask_Write(USB3_0_FPD_PIPE_CLK_OFFSET, 0x00000001U, 0x00000000U); +/*##################################################################### */ + + /* + * SD + */ + /* + * Register : RST_LPD_IOU2 @ 0XFF5E0238 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_SDIO1_RESET 0 + + * Software control register for the IOU block. Each bit will cause a singl + * erperipheral or part of the peripheral to be reset. + * (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000040U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_IOU2_OFFSET, + 0x00000040U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : CTRL_REG_SD @ 0XFF180310 + + * SD or eMMC selection on SDIO1 0: SD enabled 1: eMMC enabled + * PSU_IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL 0 + + * SD eMMC selection + * (OFFSET, MASK, VALUE) (0XFF180310, 0x00008000U ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_CTRL_REG_SD_OFFSET, + 0x00008000U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : SD_CONFIG_REG2 @ 0XFF180320 + + * Should be set based on the final product usage 00 - Removable SCard Slot + * 01 - Embedded Slot for One Device 10 - Shared Bus Slot 11 - Reserved + * PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE 0 + + * 1.8V Support 1: 1.8V supported 0: 1.8V not supported support + * PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V 1 + + * 3.0V Support 1: 3.0V supported 0: 3.0V not supported support + * PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V 0 + + * 3.3V Support 1: 3.3V supported 0: 3.3V not supported support + * PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V 1 + + * SD Config Register 2 + * (OFFSET, MASK, VALUE) (0XFF180320, 0x33800000U ,0x02800000U) + */ + PSU_Mask_Write(IOU_SLCR_SD_CONFIG_REG2_OFFSET, + 0x33800000U, 0x02800000U); +/*##################################################################### */ + + /* + * SD1 BASE CLOCK + */ + /* + * Register : SD_CONFIG_REG1 @ 0XFF18031C + + * Base Clock Frequency for SD Clock. This is the frequency of the xin_clk. + * PSU_IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK 0xc8 + + * Configures the Number of Taps (Phases) of the rxclk_in that is supported + * . + * PSU_IOU_SLCR_SD_CONFIG_REG1_SD1_TUNIGCOUNT 0x28 + + * SD Config Register 1 + * (OFFSET, MASK, VALUE) (0XFF18031C, 0x7FFE0000U ,0x64500000U) + */ + PSU_Mask_Write(IOU_SLCR_SD_CONFIG_REG1_OFFSET, + 0x7FFE0000U, 0x64500000U); +/*##################################################################### */ + + /* + * Register : SD_DLL_CTRL @ 0XFF180358 + + * Reserved. + * PSU_IOU_SLCR_SD_DLL_CTRL_RESERVED 1 + + * SDIO status register + * (OFFSET, MASK, VALUE) (0XFF180358, 0x00000008U ,0x00000008U) + */ + PSU_Mask_Write(IOU_SLCR_SD_DLL_CTRL_OFFSET, + 0x00000008U, 0x00000008U); +/*##################################################################### */ + + /* + * SD1 RETUNER + */ + /* + * Register : SD_CONFIG_REG3 @ 0XFF180324 + + * This is the Timer Count for Re-Tuning Timer for Re-Tuning Mode 1 to 3. S + * etting to 4'b0 disables Re-Tuning Timer. 0h - Get information via other + * source 1h = 1 seconds 2h = 2 seconds 3h = 4 seconds 4h = 8 seconds -- n + * = 2(n-1) seconds -- Bh = 1024 seconds Fh - Ch = Reserved + * PSU_IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR 0X0 + + * SD Config Register 3 + * (OFFSET, MASK, VALUE) (0XFF180324, 0x03C00000U ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_SD_CONFIG_REG3_OFFSET, + 0x03C00000U, 0x00000000U); +/*##################################################################### */ + + /* + * CAN + */ + /* + * Register : RST_LPD_IOU2 @ 0XFF5E0238 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_CAN1_RESET 0 + + * Software control register for the IOU block. Each bit will cause a singl + * erperipheral or part of the peripheral to be reset. + * (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000100U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_IOU2_OFFSET, + 0x00000100U, 0x00000000U); +/*##################################################################### */ + + /* + * I2C + */ + /* + * Register : RST_LPD_IOU2 @ 0XFF5E0238 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_I2C0_RESET 0 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_I2C1_RESET 0 + + * Software control register for the IOU block. Each bit will cause a singl + * erperipheral or part of the peripheral to be reset. + * (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000600U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_IOU2_OFFSET, + 0x00000600U, 0x00000000U); +/*##################################################################### */ + + /* + * SWDT + */ + /* + * Register : RST_LPD_IOU2 @ 0XFF5E0238 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_SWDT_RESET 0 + + * Software control register for the IOU block. Each bit will cause a singl + * erperipheral or part of the peripheral to be reset. + * (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00008000U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_IOU2_OFFSET, + 0x00008000U, 0x00000000U); +/*##################################################################### */ + + /* + * SPI + */ + /* + * TTC + */ + /* + * Register : RST_LPD_IOU2 @ 0XFF5E0238 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_TTC0_RESET 0 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_TTC1_RESET 0 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_TTC2_RESET 0 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_TTC3_RESET 0 + + * Software control register for the IOU block. Each bit will cause a singl + * erperipheral or part of the peripheral to be reset. + * (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00007800U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_IOU2_OFFSET, + 0x00007800U, 0x00000000U); +/*##################################################################### */ + + /* + * UART + */ + /* + * Register : RST_LPD_IOU2 @ 0XFF5E0238 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_UART0_RESET 0 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_UART1_RESET 0 + + * Software control register for the IOU block. Each bit will cause a singl + * erperipheral or part of the peripheral to be reset. + * (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000006U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_IOU2_OFFSET, + 0x00000006U, 0x00000000U); +/*##################################################################### */ + + /* + * UART BAUD RATE + */ + /* + * Register : Baud_rate_divider_reg0 @ 0XFF000034 + + * Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate + * PSU_UART0_BAUD_RATE_DIVIDER_REG0_BDIV 0x5 + + * Baud Rate Divider Register + * (OFFSET, MASK, VALUE) (0XFF000034, 0x000000FFU ,0x00000005U) + */ + PSU_Mask_Write(UART0_BAUD_RATE_DIVIDER_REG0_OFFSET, + 0x000000FFU, 0x00000005U); +/*##################################################################### */ + + /* + * Register : Baud_rate_gen_reg0 @ 0XFF000018 + + * Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor + * bypass (baud_sample = sel_clk) 2 - 65535: baud_sample + * PSU_UART0_BAUD_RATE_GEN_REG0_CD 0x8f + + * Baud Rate Generator Register. + * (OFFSET, MASK, VALUE) (0XFF000018, 0x0000FFFFU ,0x0000008FU) + */ + PSU_Mask_Write(UART0_BAUD_RATE_GEN_REG0_OFFSET, + 0x0000FFFFU, 0x0000008FU); +/*##################################################################### */ + + /* + * Register : Control_reg0 @ 0XFF000000 + + * Stop transmitter break: 0: no affect 1: stop transmission of the break a + * fter a minimum of one character length and transmit a high level during + * 12 bit periods. It can be set regardless of the value of STTBRK. + * PSU_UART0_CONTROL_REG0_STPBRK 0x0 + + * Start transmitter break: 0: no affect 1: start to transmit a break after + * the characters currently present in the FIFO and the transmit shift reg + * ister have been transmitted. It can only be set if STPBRK (Stop transmit + * ter break) is not high. + * PSU_UART0_CONTROL_REG0_STTBRK 0x0 + + * Restart receiver timeout counter: 1: receiver timeout counter is restart + * ed. This bit is self clearing once the restart has completed. + * PSU_UART0_CONTROL_REG0_RSTTO 0x0 + + * Transmit disable: 0: enable transmitter 1: disable transmitter + * PSU_UART0_CONTROL_REG0_TXDIS 0x0 + + * Transmit enable: 0: disable transmitter 1: enable transmitter, provided + * the TXDIS field is set to 0. + * PSU_UART0_CONTROL_REG0_TXEN 0x1 + + * Receive disable: 0: enable 1: disable, regardless of the value of RXEN + * PSU_UART0_CONTROL_REG0_RXDIS 0x0 + + * Receive enable: 0: disable 1: enable When set to one, the receiver logic + * is enabled, provided the RXDIS field is set to zero. + * PSU_UART0_CONTROL_REG0_RXEN 0x1 + + * Software reset for Tx data path: 0: no affect 1: transmitter logic is re + * set and all pending transmitter data is discarded This bit is self clear + * ing once the reset has completed. + * PSU_UART0_CONTROL_REG0_TXRES 0x1 + + * Software reset for Rx data path: 0: no affect 1: receiver logic is reset + * and all pending receiver data is discarded. This bit is self clearing o + * nce the reset has completed. + * PSU_UART0_CONTROL_REG0_RXRES 0x1 + + * UART Control Register + * (OFFSET, MASK, VALUE) (0XFF000000, 0x000001FFU ,0x00000017U) + */ + PSU_Mask_Write(UART0_CONTROL_REG0_OFFSET, 0x000001FFU, 0x00000017U); +/*##################################################################### */ + + /* + * Register : mode_reg0 @ 0XFF000004 + + * Channel mode: Defines the mode of operation of the UART. 00: normal 01: + * automatic echo 10: local loopback 11: remote loopback + * PSU_UART0_MODE_REG0_CHMODE 0x0 + + * Number of stop bits: Defines the number of stop bits to detect on receiv + * e and to generate on transmit. 00: 1 stop bit 01: 1.5 stop bits 10: 2 st + * op bits 11: reserved + * PSU_UART0_MODE_REG0_NBSTOP 0x0 + + * Parity type select: Defines the expected parity to check on receive and + * the parity to generate on transmit. 000: even parity 001: odd parity 010 + * : forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no pari + * ty + * PSU_UART0_MODE_REG0_PAR 0x4 + + * Character length select: Defines the number of bits in each character. 1 + * 1: 6 bits 10: 7 bits 0x: 8 bits + * PSU_UART0_MODE_REG0_CHRL 0x0 + + * Clock source select: This field defines whether a pre-scalar of 8 is app + * lied to the baud rate generator input clock. 0: clock source is uart_ref + * _clk 1: clock source is uart_ref_clk/8 + * PSU_UART0_MODE_REG0_CLKS 0x0 + + * UART Mode Register + * (OFFSET, MASK, VALUE) (0XFF000004, 0x000003FFU ,0x00000020U) + */ + PSU_Mask_Write(UART0_MODE_REG0_OFFSET, 0x000003FFU, 0x00000020U); +/*##################################################################### */ + + /* + * Register : Baud_rate_divider_reg0 @ 0XFF010034 + + * Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate + * PSU_UART1_BAUD_RATE_DIVIDER_REG0_BDIV 0x5 + + * Baud Rate Divider Register + * (OFFSET, MASK, VALUE) (0XFF010034, 0x000000FFU ,0x00000005U) + */ + PSU_Mask_Write(UART1_BAUD_RATE_DIVIDER_REG0_OFFSET, + 0x000000FFU, 0x00000005U); +/*##################################################################### */ + + /* + * Register : Baud_rate_gen_reg0 @ 0XFF010018 + + * Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor + * bypass (baud_sample = sel_clk) 2 - 65535: baud_sample + * PSU_UART1_BAUD_RATE_GEN_REG0_CD 0x8f + + * Baud Rate Generator Register. + * (OFFSET, MASK, VALUE) (0XFF010018, 0x0000FFFFU ,0x0000008FU) + */ + PSU_Mask_Write(UART1_BAUD_RATE_GEN_REG0_OFFSET, + 0x0000FFFFU, 0x0000008FU); +/*##################################################################### */ + + /* + * Register : Control_reg0 @ 0XFF010000 + + * Stop transmitter break: 0: no affect 1: stop transmission of the break a + * fter a minimum of one character length and transmit a high level during + * 12 bit periods. It can be set regardless of the value of STTBRK. + * PSU_UART1_CONTROL_REG0_STPBRK 0x0 + + * Start transmitter break: 0: no affect 1: start to transmit a break after + * the characters currently present in the FIFO and the transmit shift reg + * ister have been transmitted. It can only be set if STPBRK (Stop transmit + * ter break) is not high. + * PSU_UART1_CONTROL_REG0_STTBRK 0x0 + + * Restart receiver timeout counter: 1: receiver timeout counter is restart + * ed. This bit is self clearing once the restart has completed. + * PSU_UART1_CONTROL_REG0_RSTTO 0x0 + + * Transmit disable: 0: enable transmitter 1: disable transmitter + * PSU_UART1_CONTROL_REG0_TXDIS 0x0 + + * Transmit enable: 0: disable transmitter 1: enable transmitter, provided + * the TXDIS field is set to 0. + * PSU_UART1_CONTROL_REG0_TXEN 0x1 + + * Receive disable: 0: enable 1: disable, regardless of the value of RXEN + * PSU_UART1_CONTROL_REG0_RXDIS 0x0 + + * Receive enable: 0: disable 1: enable When set to one, the receiver logic + * is enabled, provided the RXDIS field is set to zero. + * PSU_UART1_CONTROL_REG0_RXEN 0x1 + + * Software reset for Tx data path: 0: no affect 1: transmitter logic is re + * set and all pending transmitter data is discarded This bit is self clear + * ing once the reset has completed. + * PSU_UART1_CONTROL_REG0_TXRES 0x1 + + * Software reset for Rx data path: 0: no affect 1: receiver logic is reset + * and all pending receiver data is discarded. This bit is self clearing o + * nce the reset has completed. + * PSU_UART1_CONTROL_REG0_RXRES 0x1 + + * UART Control Register + * (OFFSET, MASK, VALUE) (0XFF010000, 0x000001FFU ,0x00000017U) + */ + PSU_Mask_Write(UART1_CONTROL_REG0_OFFSET, 0x000001FFU, 0x00000017U); +/*##################################################################### */ + + /* + * Register : mode_reg0 @ 0XFF010004 + + * Channel mode: Defines the mode of operation of the UART. 00: normal 01: + * automatic echo 10: local loopback 11: remote loopback + * PSU_UART1_MODE_REG0_CHMODE 0x0 + + * Number of stop bits: Defines the number of stop bits to detect on receiv + * e and to generate on transmit. 00: 1 stop bit 01: 1.5 stop bits 10: 2 st + * op bits 11: reserved + * PSU_UART1_MODE_REG0_NBSTOP 0x0 + + * Parity type select: Defines the expected parity to check on receive and + * the parity to generate on transmit. 000: even parity 001: odd parity 010 + * : forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no pari + * ty + * PSU_UART1_MODE_REG0_PAR 0x4 + + * Character length select: Defines the number of bits in each character. 1 + * 1: 6 bits 10: 7 bits 0x: 8 bits + * PSU_UART1_MODE_REG0_CHRL 0x0 + + * Clock source select: This field defines whether a pre-scalar of 8 is app + * lied to the baud rate generator input clock. 0: clock source is uart_ref + * _clk 1: clock source is uart_ref_clk/8 + * PSU_UART1_MODE_REG0_CLKS 0x0 + + * UART Mode Register + * (OFFSET, MASK, VALUE) (0XFF010004, 0x000003FFU ,0x00000020U) + */ + PSU_Mask_Write(UART1_MODE_REG0_OFFSET, 0x000003FFU, 0x00000020U); +/*##################################################################### */ + + /* + * GPIO + */ + /* + * Register : RST_LPD_IOU2 @ 0XFF5E0238 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_GPIO_RESET 0 + + * Software control register for the IOU block. Each bit will cause a singl + * erperipheral or part of the peripheral to be reset. + * (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00040000U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_IOU2_OFFSET, + 0x00040000U, 0x00000000U); +/*##################################################################### */ + + /* + * ADMA TZ + */ + /* + * Register : slcr_adma @ 0XFF4B0024 + + * TrustZone Classification for ADMA + * PSU_LPD_SLCR_SECURE_SLCR_ADMA_TZ 0XFF + + * RPU TrustZone settings + * (OFFSET, MASK, VALUE) (0XFF4B0024, 0x000000FFU ,0x000000FFU) + */ + PSU_Mask_Write(LPD_SLCR_SECURE_SLCR_ADMA_OFFSET, + 0x000000FFU, 0x000000FFU); +/*##################################################################### */ + + /* + * CSU TAMPERING + */ + /* + * CSU TAMPER STATUS + */ + /* + * Register : tamper_status @ 0XFFCA5000 + + * CSU regsiter + * PSU_CSU_TAMPER_STATUS_TAMPER_0 0 + + * External MIO + * PSU_CSU_TAMPER_STATUS_TAMPER_1 0 + + * JTAG toggle detect + * PSU_CSU_TAMPER_STATUS_TAMPER_2 0 + + * PL SEU error + * PSU_CSU_TAMPER_STATUS_TAMPER_3 0 + + * AMS over temperature alarm for LPD + * PSU_CSU_TAMPER_STATUS_TAMPER_4 0 + + * AMS over temperature alarm for APU + * PSU_CSU_TAMPER_STATUS_TAMPER_5 0 + + * AMS voltage alarm for VCCPINT_FPD + * PSU_CSU_TAMPER_STATUS_TAMPER_6 0 + + * AMS voltage alarm for VCCPINT_LPD + * PSU_CSU_TAMPER_STATUS_TAMPER_7 0 + + * AMS voltage alarm for VCCPAUX + * PSU_CSU_TAMPER_STATUS_TAMPER_8 0 + + * AMS voltage alarm for DDRPHY + * PSU_CSU_TAMPER_STATUS_TAMPER_9 0 + + * AMS voltage alarm for PSIO bank 0/1/2 + * PSU_CSU_TAMPER_STATUS_TAMPER_10 0 + + * AMS voltage alarm for PSIO bank 3 (dedicated pins) + * PSU_CSU_TAMPER_STATUS_TAMPER_11 0 + + * AMS voltaage alarm for GT + * PSU_CSU_TAMPER_STATUS_TAMPER_12 0 + + * Tamper Response Status + * (OFFSET, MASK, VALUE) (0XFFCA5000, 0x00001FFFU ,0x00000000U) + */ + PSU_Mask_Write(CSU_TAMPER_STATUS_OFFSET, 0x00001FFFU, 0x00000000U); +/*##################################################################### */ + + /* + * CSU TAMPER RESPONSE + */ + /* + * CPU QOS DEFAULT + */ + /* + * Register : ACE_CTRL @ 0XFD5C0060 + + * Set ACE outgoing AWQOS value + * PSU_APU_ACE_CTRL_AWQOS 0X0 + + * Set ACE outgoing ARQOS value + * PSU_APU_ACE_CTRL_ARQOS 0X0 + + * ACE Control Register + * (OFFSET, MASK, VALUE) (0XFD5C0060, 0x000F000FU ,0x00000000U) + */ + PSU_Mask_Write(APU_ACE_CTRL_OFFSET, 0x000F000FU, 0x00000000U); +/*##################################################################### */ + + /* + * ENABLES RTC SWITCH TO BATTERY WHEN VCC_PSAUX IS NOT AVAILABLE + */ + /* + * Register : CONTROL @ 0XFFA60040 + + * Enables the RTC. By writing a 0 to this bit, RTC will be powered off and + * the only module that potentially draws current from the battery will be + * BBRAM. The value read through this bit does not necessarily reflect whe + * ther RTC is enabled or not. It is expected that RTC is enabled every tim + * e it is being configured. If RTC is not used in the design, FSBL will di + * sable it by writing a 0 to this bit. + * PSU_RTC_CONTROL_BATTERY_DISABLE 0X1 + + * This register controls various functionalities within the RTC + * (OFFSET, MASK, VALUE) (0XFFA60040, 0x80000000U ,0x80000000U) + */ + PSU_Mask_Write(RTC_CONTROL_OFFSET, 0x80000000U, 0x80000000U); +/*##################################################################### */ + + /* + * TIMESTAMP COUNTER + */ + /* + * Register : base_frequency_ID_register @ 0XFF260020 + + * Frequency in number of ticks per second. Valid range from 10 MHz to 100 + * MHz. + * PSU_IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ 0x5f5b9f0 + + * Program this register to match the clock frequency of the timestamp gene + * rator, in ticks per second. For example, for a 50 MHz clock, program 0x0 + * 2FAF080. This register is not accessible to the read-only programming in + * terface. + * (OFFSET, MASK, VALUE) (0XFF260020, 0xFFFFFFFFU ,0x05F5B9F0U) + */ + PSU_Mask_Write(IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_OFFSET, + 0xFFFFFFFFU, 0x05F5B9F0U); +/*##################################################################### */ + + /* + * Register : counter_control_register @ 0XFF260000 + + * Enable 0: The counter is disabled and not incrementing. 1: The counter i + * s enabled and is incrementing. + * PSU_IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN 0x1 + + * Controls the counter increments. This register is not accessible to the + * read-only programming interface. + * (OFFSET, MASK, VALUE) (0XFF260000, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(IOU_SCNTRS_COUNTER_CONTROL_REGISTER_OFFSET, + 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * TTC SRC SELECT + */ + /* + * PCIE GPIO RESET + */ + /* + * PCIE RESET + */ + /* + * DIR MODE BANK 0 + */ + /* + * DIR MODE BANK 1 + */ + /* + * Register : DIRM_1 @ 0XFF0A0244 + + * Operation is the same as DIRM_0[DIRECTION_0] + * PSU_GPIO_DIRM_1_DIRECTION_1 0x20 + + * Direction mode (GPIO Bank1, MIO) + * (OFFSET, MASK, VALUE) (0XFF0A0244, 0x03FFFFFFU ,0x00000020U) + */ + PSU_Mask_Write(GPIO_DIRM_1_OFFSET, 0x03FFFFFFU, 0x00000020U); +/*##################################################################### */ + + /* + * DIR MODE BANK 2 + */ + /* + * OUTPUT ENABLE BANK 0 + */ + /* + * OUTPUT ENABLE BANK 1 + */ + /* + * Register : OEN_1 @ 0XFF0A0248 + + * Operation is the same as OEN_0[OP_ENABLE_0] + * PSU_GPIO_OEN_1_OP_ENABLE_1 0x20 + + * Output enable (GPIO Bank1, MIO) + * (OFFSET, MASK, VALUE) (0XFF0A0248, 0x03FFFFFFU ,0x00000020U) + */ + PSU_Mask_Write(GPIO_OEN_1_OFFSET, 0x03FFFFFFU, 0x00000020U); +/*##################################################################### */ + + /* + * OUTPUT ENABLE BANK 2 + */ + /* + * MASK_DATA_0_LSW LOW BANK [15:0] + */ + /* + * MASK_DATA_0_MSW LOW BANK [25:16] + */ + /* + * MASK_DATA_1_LSW LOW BANK [41:26] + */ + /* + * Register : MASK_DATA_1_LSW @ 0XFF0A0008 + + * Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW] + * PSU_GPIO_MASK_DATA_1_LSW_MASK_1_LSW 0xffdf + + * Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW] + * PSU_GPIO_MASK_DATA_1_LSW_DATA_1_LSW 0x20 + + * Maskable Output Data (GPIO Bank1, MIO, Lower 16bits) + * (OFFSET, MASK, VALUE) (0XFF0A0008, 0xFFFFFFFFU ,0xFFDF0020U) + */ + PSU_Mask_Write(GPIO_MASK_DATA_1_LSW_OFFSET, + 0xFFFFFFFFU, 0xFFDF0020U); +/*##################################################################### */ + + /* + * MASK_DATA_1_MSW HIGH BANK [51:42] + */ + /* + * MASK_DATA_1_LSW HIGH BANK [67:52] + */ + /* + * MASK_DATA_1_LSW HIGH BANK [77:68] + */ + /* + * ADD 1 MS DELAY + */ + mask_delay(1); + +/*##################################################################### */ + + /* + * MASK_DATA_0_LSW LOW BANK [15:0] + */ + /* + * MASK_DATA_0_MSW LOW BANK [25:16] + */ + /* + * MASK_DATA_1_LSW LOW BANK [41:26] + */ + /* + * Register : MASK_DATA_1_LSW @ 0XFF0A0008 + + * Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW] + * PSU_GPIO_MASK_DATA_1_LSW_MASK_1_LSW 0xffdf + + * Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW] + * PSU_GPIO_MASK_DATA_1_LSW_DATA_1_LSW 0x0 + + * Maskable Output Data (GPIO Bank1, MIO, Lower 16bits) + * (OFFSET, MASK, VALUE) (0XFF0A0008, 0xFFFFFFFFU ,0xFFDF0000U) + */ + PSU_Mask_Write(GPIO_MASK_DATA_1_LSW_OFFSET, + 0xFFFFFFFFU, 0xFFDF0000U); +/*##################################################################### */ + + /* + * MASK_DATA_1_MSW HIGH BANK [51:42] + */ + /* + * MASK_DATA_1_LSW HIGH BANK [67:52] + */ + /* + * MASK_DATA_1_LSW HIGH BANK [77:68] + */ + /* + * ADD 5 MS DELAY + */ + mask_delay(5); + +/*##################################################################### */ + + + return 1; } -unsigned long psu_peripherals_powerdwn_data() { - // : POWER DOWN REQUEST INTERRUPT ENABLE - // : POWER DOWN TRIGGER +unsigned long psu_post_config_data(void) +{ + /* + * POST_CONFIG + */ - return 1; + return 1; } -unsigned long psu_lpd_xppu_data() { - // : XPPU INTERRUPT ENABLE - /*Register : IEN @ 0XFF980018

+unsigned long psu_peripherals_powerdwn_data(void) +{ + /* + * POWER DOWN REQUEST INTERRUPT ENABLE + */ + /* + * POWER DOWN TRIGGER + */ - See Interuppt Status Register for details - PSU_LPD_XPPU_CFG_IEN_APER_PARITY 0X1 - - See Interuppt Status Register for details - PSU_LPD_XPPU_CFG_IEN_APER_TZ 0X1 - - See Interuppt Status Register for details - PSU_LPD_XPPU_CFG_IEN_APER_PERM 0X1 - - See Interuppt Status Register for details - PSU_LPD_XPPU_CFG_IEN_MID_PARITY 0X1 - - See Interuppt Status Register for details - PSU_LPD_XPPU_CFG_IEN_MID_RO 0X1 - - See Interuppt Status Register for details - PSU_LPD_XPPU_CFG_IEN_MID_MISS 0X1 - - See Interuppt Status Register for details - PSU_LPD_XPPU_CFG_IEN_INV_APB 0X1 - - Interrupt Enable Register - (OFFSET, MASK, VALUE) (0XFF980018, 0x000000EFU ,0x000000EFU) - RegMask = (LPD_XPPU_CFG_IEN_APER_PARITY_MASK | LPD_XPPU_CFG_IEN_APER_TZ_MASK | LPD_XPPU_CFG_IEN_APER_PERM_MASK | LPD_XPPU_CFG_IEN_MID_PARITY_MASK | LPD_XPPU_CFG_IEN_MID_RO_MASK | LPD_XPPU_CFG_IEN_MID_MISS_MASK | LPD_XPPU_CFG_IEN_INV_APB_MASK | 0 ); - - RegVal = ((0x00000001U << LPD_XPPU_CFG_IEN_APER_PARITY_SHIFT - | 0x00000001U << LPD_XPPU_CFG_IEN_APER_TZ_SHIFT - | 0x00000001U << LPD_XPPU_CFG_IEN_APER_PERM_SHIFT - | 0x00000001U << LPD_XPPU_CFG_IEN_MID_PARITY_SHIFT - | 0x00000001U << LPD_XPPU_CFG_IEN_MID_RO_SHIFT - | 0x00000001U << LPD_XPPU_CFG_IEN_MID_MISS_SHIFT - | 0x00000001U << LPD_XPPU_CFG_IEN_INV_APB_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (LPD_XPPU_CFG_IEN_OFFSET ,0x000000EFU ,0x000000EFU); - /*############################################################################################################################ */ - - - return 1; + return 1; } -unsigned long psu_ddr_xmpu0_data() { +unsigned long psu_lpd_xppu_data(void) +{ + /* + * MASTER ID LIST + */ + /* + * APERTURE PERMISIION LIST + */ + /* + * APERTURE NAME: UART0, START ADDRESS: FF000000, END ADDRESS: FF00FFFF + */ + /* + * APERTURE NAME: UART1, START ADDRESS: FF010000, END ADDRESS: FF01FFFF + */ + /* + * APERTURE NAME: I2C0, START ADDRESS: FF020000, END ADDRESS: FF02FFFF + */ + /* + * APERTURE NAME: I2C1, START ADDRESS: FF030000, END ADDRESS: FF03FFFF + */ + /* + * APERTURE NAME: SPI0, START ADDRESS: FF040000, END ADDRESS: FF04FFFF + */ + /* + * APERTURE NAME: SPI1, START ADDRESS: FF050000, END ADDRESS: FF05FFFF + */ + /* + * APERTURE NAME: CAN0, START ADDRESS: FF060000, END ADDRESS: FF06FFFF + */ + /* + * APERTURE NAME: CAN1, START ADDRESS: FF070000, END ADDRESS: FF07FFFF + */ + /* + * APERTURE NAME: RPU_UNUSED_12, START ADDRESS: FF080000, END ADDRESS: FF09 + * FFFF + */ + /* + * APERTURE NAME: RPU_UNUSED_12, START ADDRESS: FF080000, END ADDRESS: FF09 + * FFFF + */ + /* + * APERTURE NAME: GPIO, START ADDRESS: FF0A0000, END ADDRESS: FF0AFFFF + */ + /* + * APERTURE NAME: GEM0, START ADDRESS: FF0B0000, END ADDRESS: FF0BFFFF + */ + /* + * APERTURE NAME: GEM1, START ADDRESS: FF0C0000, END ADDRESS: FF0CFFFF + */ + /* + * APERTURE NAME: GEM2, START ADDRESS: FF0D0000, END ADDRESS: FF0DFFFF + */ + /* + * APERTURE NAME: GEM3, START ADDRESS: FF0E0000, END ADDRESS: FF0EFFFF + */ + /* + * APERTURE NAME: QSPI, START ADDRESS: FF0F0000, END ADDRESS: FF0FFFFF + */ + /* + * APERTURE NAME: NAND, START ADDRESS: FF100000, END ADDRESS: FF10FFFF + */ + /* + * APERTURE NAME: TTC0, START ADDRESS: FF110000, END ADDRESS: FF11FFFF + */ + /* + * APERTURE NAME: TTC1, START ADDRESS: FF120000, END ADDRESS: FF12FFFF + */ + /* + * APERTURE NAME: TTC2, START ADDRESS: FF130000, END ADDRESS: FF13FFFF + */ + /* + * APERTURE NAME: TTC3, START ADDRESS: FF140000, END ADDRESS: FF14FFFF + */ + /* + * APERTURE NAME: SWDT, START ADDRESS: FF150000, END ADDRESS: FF15FFFF + */ + /* + * APERTURE NAME: SD0, START ADDRESS: FF160000, END ADDRESS: FF16FFFF + */ + /* + * APERTURE NAME: SD1, START ADDRESS: FF170000, END ADDRESS: FF17FFFF + */ + /* + * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + */ + /* + * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + */ + /* + * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + */ + /* + * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + */ + /* + * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + */ + /* + * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + */ + /* + * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + */ + /* + * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + */ + /* + * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + */ + /* + * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + */ + /* + * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + */ + /* + * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + */ + /* + * APERTURE NAME: IOU_SECURE_SLCR, START ADDRESS: FF240000, END ADDRESS: FF + * 24FFFF + */ + /* + * APERTURE NAME: IOU_SCNTR, START ADDRESS: FF250000, END ADDRESS: FF25FFFF + */ + /* + * APERTURE NAME: IOU_SCNTRS, START ADDRESS: FF260000, END ADDRESS: FF26FFF + * F + */ + /* + * APERTURE NAME: RPU_UNUSED_11, START ADDRESS: FF270000, END ADDRESS: FF2A + * FFFF + */ + /* + * APERTURE NAME: RPU_UNUSED_11, START ADDRESS: FF270000, END ADDRESS: FF2A + * FFFF + */ + /* + * APERTURE NAME: RPU_UNUSED_11, START ADDRESS: FF270000, END ADDRESS: FF2A + * FFFF + */ + /* + * APERTURE NAME: RPU_UNUSED_11, START ADDRESS: FF270000, END ADDRESS: FF2A + * FFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_14, START ADDRESS: FF2B0000, END ADDRESS: FF2F + * FFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_14, START ADDRESS: FF2B0000, END ADDRESS: FF2F + * FFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_14, START ADDRESS: FF2B0000, END ADDRESS: FF2F + * FFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_14, START ADDRESS: FF2B0000, END ADDRESS: FF2F + * FFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_14, START ADDRESS: FF2B0000, END ADDRESS: FF2F + * FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF + */ + /* + * APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF + */ + /* + * APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF + */ + /* + * APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF + */ + /* + * APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF + */ + /* + * APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF + */ + /* + * APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF + */ + /* + * APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_1, START ADDRESS: FF400000, END ADDRESS: FF40F + * FFF + */ + /* + * APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + */ + /* + * APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + */ + /* + * APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + */ + /* + * APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + */ + /* + * APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + */ + /* + * APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + */ + /* + * APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + */ + /* + * APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + */ + /* + * APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + */ + /* + * APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + */ + /* + * APERTURE NAME: LPD_SLCR_SECURE, START ADDRESS: FF4B0000, END ADDRESS: FF + * 4DFFFF + */ + /* + * APERTURE NAME: LPD_SLCR_SECURE, START ADDRESS: FF4B0000, END ADDRESS: FF + * 4DFFFF + */ + /* + * APERTURE NAME: LPD_SLCR_SECURE, START ADDRESS: FF4B0000, END ADDRESS: FF + * 4DFFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: OCM_SLCR, START ADDRESS: FF960000, END ADDRESS: FF96FFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_4, START ADDRESS: FF970000, END ADDRESS: FF97F + * FFF + */ + /* + * APERTURE NAME: LPD_XPPU, START ADDRESS: FF980000, END ADDRESS: FF99FFFF + */ + /* + * APERTURE NAME: RPU, START ADDRESS: FF9A0000, END ADDRESS: FF9AFFFF + */ + /* + * APERTURE NAME: AFIFM6, START ADDRESS: FF9B0000, END ADDRESS: FF9BFFFF + */ + /* + * APERTURE NAME: LPD_XPPU_SINK, START ADDRESS: FF9C0000, END ADDRESS: FF9C + * FFFF + */ + /* + * APERTURE NAME: USB3_0, START ADDRESS: FF9D0000, END ADDRESS: FF9DFFFF + */ + /* + * APERTURE NAME: USB3_1, START ADDRESS: FF9E0000, END ADDRESS: FF9EFFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_5, START ADDRESS: FF9F0000, END ADDRESS: FF9FF + * FFF + */ + /* + * APERTURE NAME: APM0, START ADDRESS: FFA00000, END ADDRESS: FFA0FFFF + */ + /* + * APERTURE NAME: APM1, START ADDRESS: FFA10000, END ADDRESS: FFA1FFFF + */ + /* + * APERTURE NAME: APM_INTC_IOU, START ADDRESS: FFA20000, END ADDRESS: FFA2F + * FFF + */ + /* + * APERTURE NAME: APM_FPD_LPD, START ADDRESS: FFA30000, END ADDRESS: FFA3FF + * FF + */ + /* + * APERTURE NAME: LPD_UNUSED_6, START ADDRESS: FFA40000, END ADDRESS: FFA4F + * FFF + */ + /* + * APERTURE NAME: AMS, START ADDRESS: FFA50000, END ADDRESS: FFA5FFFF + */ + /* + * APERTURE NAME: RTC, START ADDRESS: FFA60000, END ADDRESS: FFA6FFFF + */ + /* + * APERTURE NAME: OCM_XMPU_CFG, START ADDRESS: FFA70000, END ADDRESS: FFA7F + * FFF + */ + /* + * APERTURE NAME: ADMA_0, START ADDRESS: FFA80000, END ADDRESS: FFA8FFFF + */ + /* + * APERTURE NAME: ADMA_1, START ADDRESS: FFA90000, END ADDRESS: FFA9FFFF + */ + /* + * APERTURE NAME: ADMA_2, START ADDRESS: FFAA0000, END ADDRESS: FFAAFFFF + */ + /* + * APERTURE NAME: ADMA_3, START ADDRESS: FFAB0000, END ADDRESS: FFABFFFF + */ + /* + * APERTURE NAME: ADMA_4, START ADDRESS: FFAC0000, END ADDRESS: FFACFFFF + */ + /* + * APERTURE NAME: ADMA_5, START ADDRESS: FFAD0000, END ADDRESS: FFADFFFF + */ + /* + * APERTURE NAME: ADMA_6, START ADDRESS: FFAE0000, END ADDRESS: FFAEFFFF + */ + /* + * APERTURE NAME: ADMA_7, START ADDRESS: FFAF0000, END ADDRESS: FFAFFFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: CSU_ROM, START ADDRESS: FFC00000, END ADDRESS: FFC1FFFF + */ + /* + * APERTURE NAME: CSU_ROM, START ADDRESS: FFC00000, END ADDRESS: FFC1FFFF + */ + /* + * APERTURE NAME: CSU_LOCAL, START ADDRESS: FFC20000, END ADDRESS: FFC2FFFF + */ + /* + * APERTURE NAME: PUF, START ADDRESS: FFC30000, END ADDRESS: FFC3FFFF + */ + /* + * APERTURE NAME: CSU_RAM, START ADDRESS: FFC40000, END ADDRESS: FFC5FFFF + */ + /* + * APERTURE NAME: CSU_RAM, START ADDRESS: FFC40000, END ADDRESS: FFC5FFFF + */ + /* + * APERTURE NAME: CSU_IOMODULE, START ADDRESS: FFC60000, END ADDRESS: FFC7F + * FFF + */ + /* + * APERTURE NAME: CSU_IOMODULE, START ADDRESS: FFC60000, END ADDRESS: FFC7F + * FFF + */ + /* + * APERTURE NAME: CSUDMA, START ADDRESS: FFC80000, END ADDRESS: FFC9FFFF + */ + /* + * APERTURE NAME: CSUDMA, START ADDRESS: FFC80000, END ADDRESS: FFC9FFFF + */ + /* + * APERTURE NAME: CSU, START ADDRESS: FFCA0000, END ADDRESS: FFCAFFFF + */ + /* + * APERTURE NAME: CSU_WDT, START ADDRESS: FFCB0000, END ADDRESS: FFCBFFFF + */ + /* + * APERTURE NAME: EFUSE, START ADDRESS: FFCC0000, END ADDRESS: FFCCFFFF + */ + /* + * APERTURE NAME: BBRAM, START ADDRESS: FFCD0000, END ADDRESS: FFCDFFFF + */ + /* + * APERTURE NAME: RSA_CORE, START ADDRESS: FFCE0000, END ADDRESS: FFCEFFFF + */ + /* + * APERTURE NAME: MBISTJTAG, START ADDRESS: FFCF0000, END ADDRESS: FFCFFFFF + */ + /* + * APERTURE NAME: PMU_ROM, START ADDRESS: FFD00000, END ADDRESS: FFD3FFFF + */ + /* + * APERTURE NAME: PMU_ROM, START ADDRESS: FFD00000, END ADDRESS: FFD3FFFF + */ + /* + * APERTURE NAME: PMU_ROM, START ADDRESS: FFD00000, END ADDRESS: FFD3FFFF + */ + /* + * APERTURE NAME: PMU_ROM, START ADDRESS: FFD00000, END ADDRESS: FFD3FFFF + */ + /* + * APERTURE NAME: PMU_IOMODULE, START ADDRESS: FFD40000, END ADDRESS: FFD5F + * FFF + */ + /* + * APERTURE NAME: PMU_IOMODULE, START ADDRESS: FFD40000, END ADDRESS: FFD5F + * FFF + */ + /* + * APERTURE NAME: PMU_LOCAL, START ADDRESS: FFD60000, END ADDRESS: FFD7FFFF + */ + /* + * APERTURE NAME: PMU_LOCAL, START ADDRESS: FFD60000, END ADDRESS: FFD7FFFF + */ + /* + * APERTURE NAME: PMU_GLOBAL, START ADDRESS: FFD80000, END ADDRESS: FFDBFFF + * F + */ + /* + * APERTURE NAME: PMU_GLOBAL, START ADDRESS: FFD80000, END ADDRESS: FFDBFFF + * F + */ + /* + * APERTURE NAME: PMU_GLOBAL, START ADDRESS: FFD80000, END ADDRESS: FFDBFFF + * F + */ + /* + * APERTURE NAME: PMU_GLOBAL, START ADDRESS: FFD80000, END ADDRESS: FFDBFFF + * F + */ + /* + * APERTURE NAME: PMU_RAM, START ADDRESS: FFDC0000, END ADDRESS: FFDFFFFF + */ + /* + * APERTURE NAME: PMU_RAM, START ADDRESS: FFDC0000, END ADDRESS: FFDFFFFF + */ + /* + * APERTURE NAME: PMU_RAM, START ADDRESS: FFDC0000, END ADDRESS: FFDFFFFF + */ + /* + * APERTURE NAME: PMU_RAM, START ADDRESS: FFDC0000, END ADDRESS: FFDFFFFF + */ + /* + * APERTURE NAME: R5_0_ATCM, START ADDRESS: FFE00000, END ADDRESS: FFE0FFFF + */ + /* + * APERTURE NAME: R5_0_ATCM_LOCKSTEP, START ADDRESS: FFE10000, END ADDRESS: + * FFE1FFFF + */ + /* + * APERTURE NAME: R5_0_BTCM, START ADDRESS: FFE20000, END ADDRESS: FFE2FFFF + */ + /* + * APERTURE NAME: R5_0_BTCM_LOCKSTEP, START ADDRESS: FFE30000, END ADDRESS: + * FFE3FFFF + */ + /* + * APERTURE NAME: R5_0_INSTRUCTION_CACHE, START ADDRESS: FFE40000, END ADDR + * ESS: FFE4FFFF + */ + /* + * APERTURE NAME: R5_0_DATA_CACHE, START ADDRESS: FFE50000, END ADDRESS: FF + * E5FFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_8, START ADDRESS: FFE60000, END ADDRESS: FFE8F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_8, START ADDRESS: FFE60000, END ADDRESS: FFE8F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_8, START ADDRESS: FFE60000, END ADDRESS: FFE8F + * FFF + */ + /* + * APERTURE NAME: R5_1_ATCM_, START ADDRESS: FFE90000, END ADDRESS: FFE9FFF + * F + */ + /* + * APERTURE NAME: RPU_UNUSED_10, START ADDRESS: FFEA0000, END ADDRESS: FFEA + * FFFF + */ + /* + * APERTURE NAME: R5_1_BTCM_, START ADDRESS: FFEB0000, END ADDRESS: FFEBFFF + * F + */ + /* + * APERTURE NAME: R5_1_INSTRUCTION_CACHE, START ADDRESS: FFEC0000, END ADDR + * ESS: FFECFFFF + */ + /* + * APERTURE NAME: R5_1_DATA_CACHE, START ADDRESS: FFED0000, END ADDRESS: FF + * EDFFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_15, START ADDRESS: FFFD0000, END ADDRESS: FFFF + * FFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_15, START ADDRESS: FFFD0000, END ADDRESS: FFFF + * FFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_15, START ADDRESS: FFFD0000, END ADDRESS: FFFF + * FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IOU_GPV, START ADDRESS: FE000000, END ADDRESS: FE0FFFFF + */ + /* + * APERTURE NAME: LPD_GPV, START ADDRESS: FE100000, END ADDRESS: FE1FFFFF + */ + /* + * APERTURE NAME: USB3_0_XHCI, START ADDRESS: FE200000, END ADDRESS: FE2FFF + * FF + */ + /* + * APERTURE NAME: USB3_1_XHCI, START ADDRESS: FE300000, END ADDRESS: FE3FFF + * FF + */ + /* + * APERTURE NAME: LPD_UNUSED_13, START ADDRESS: FE400000, END ADDRESS: FE7F + * FFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_13, START ADDRESS: FE400000, END ADDRESS: FE7F + * FFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_13, START ADDRESS: FE400000, END ADDRESS: FE7F + * FFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_13, START ADDRESS: FE400000, END ADDRESS: FE7F + * FFFF + */ + /* + * APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF + */ + /* + * APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF + */ + /* + * APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF + */ + /* + * APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF + */ + /* + * APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF + */ + /* + * APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF + */ + /* + * APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF + */ + /* + * APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF + */ + /* + * APERTURE NAME: QSPI_LINEAR_ADDRESS, START ADDRESS: C0000000, END ADDRESS + * : DFFFFFFF + */ + /* + * XPPU CONTROL + */ - return 1; + return 1; } -unsigned long psu_ddr_xmpu1_data() { +unsigned long psu_ddr_xmpu0_data(void) +{ + /* + * DDR XMPU0 + */ - return 1; + return 1; } -unsigned long psu_ddr_xmpu2_data() { +unsigned long psu_ddr_xmpu1_data(void) +{ + /* + * DDR XMPU1 + */ - return 1; + return 1; } -unsigned long psu_ddr_xmpu3_data() { +unsigned long psu_ddr_xmpu2_data(void) +{ + /* + * DDR XMPU2 + */ - return 1; + return 1; } -unsigned long psu_ddr_xmpu4_data() { +unsigned long psu_ddr_xmpu3_data(void) +{ + /* + * DDR XMPU3 + */ - return 1; + return 1; } -unsigned long psu_ddr_xmpu5_data() { +unsigned long psu_ddr_xmpu4_data(void) +{ + /* + * DDR XMPU4 + */ - return 1; + return 1; } -unsigned long psu_ocm_xmpu_data() { +unsigned long psu_ddr_xmpu5_data(void) +{ + /* + * DDR XMPU5 + */ - return 1; + return 1; } -unsigned long psu_fpd_xmpu_data() { +unsigned long psu_ocm_xmpu_data(void) +{ + /* + * OCM XMPU + */ - return 1; + return 1; } -unsigned long psu_protection_lock_data() { +unsigned long psu_fpd_xmpu_data(void) +{ + /* + * FPD XMPU + */ - return 1; + return 1; } -unsigned long psu_apply_master_tz() { - // : RPU - // : DP TZ - // : SATA TZ - // : PCIE TZ - // : USB TZ - // : SD TZ - // : GEM TZ - // : QSPI TZ - // : NAND TZ +unsigned long psu_protection_lock_data(void) +{ + /* + * LOCKING PROTECTION MODULE + */ + /* + * XPPU LOCK + */ + /* + * APERTURE NAME: LPD_XPPU, START ADDRESS: FF980000, END ADDRESS: FF99FFFF + */ + /* + * XMPU LOCK + */ + /* + * LOCK OCM XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER + */ + /* + * LOCK FPD XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER + */ + /* + * LOCK DDR XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER + */ + /* + * LOCK DDR XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER + */ + /* + * LOCK DDR XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER + */ + /* + * LOCK DDR XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER + */ + /* + * LOCK DDR XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER + */ + /* + * LOCK DDR XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER + */ - return 1; + return 1; } -unsigned long psu_serdes_init_data() { - // : SERDES INITIALIZATION - // : GT REFERENCE CLOCK SOURCE SELECTION - /*Register : PLL_REF_SEL0 @ 0XFD410000

+unsigned long psu_apply_master_tz(void) +{ + /* + * RPU + */ + /* + * DP TZ + */ + /* + * Register : slcr_dpdma @ 0XFD690040 - PLL0 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - - 4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135 - Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved - PSU_SERDES_PLL_REF_SEL0_PLLREFSEL0 0xD + * TrustZone classification for DisplayPort DMA + * PSU_FPD_SLCR_SECURE_SLCR_DPDMA_TZ 1 - PLL0 Reference Selection Register - (OFFSET, MASK, VALUE) (0XFD410000, 0x0000001FU ,0x0000000DU) - RegMask = (SERDES_PLL_REF_SEL0_PLLREFSEL0_MASK | 0 ); + * DPDMA TrustZone Settings + * (OFFSET, MASK, VALUE) (0XFD690040, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(FPD_SLCR_SECURE_SLCR_DPDMA_OFFSET, + 0x00000001U, 0x00000001U); +/*##################################################################### */ - RegVal = ((0x0000000DU << SERDES_PLL_REF_SEL0_PLLREFSEL0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_PLL_REF_SEL0_OFFSET ,0x0000001FU ,0x0000000DU); - /*############################################################################################################################ */ + /* + * SATA TZ + */ + /* + * PCIE TZ + */ + /* + * Register : slcr_pcie @ 0XFD690030 - /*Register : PLL_REF_SEL1 @ 0XFD410004

+ * TrustZone classification for DMA Channel 0 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_0 1 - PLL1 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - - 4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135 - Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved - PSU_SERDES_PLL_REF_SEL1_PLLREFSEL1 0x9 + * TrustZone classification for DMA Channel 1 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_1 1 - PLL1 Reference Selection Register - (OFFSET, MASK, VALUE) (0XFD410004, 0x0000001FU ,0x00000009U) - RegMask = (SERDES_PLL_REF_SEL1_PLLREFSEL1_MASK | 0 ); + * TrustZone classification for DMA Channel 2 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_2 1 - RegVal = ((0x00000009U << SERDES_PLL_REF_SEL1_PLLREFSEL1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_PLL_REF_SEL1_OFFSET ,0x0000001FU ,0x00000009U); - /*############################################################################################################################ */ + * TrustZone classification for DMA Channel 3 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_3 1 - /*Register : PLL_REF_SEL2 @ 0XFD410008

+ * TrustZone classification for Ingress Address Translation 0 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_0 1 - PLL2 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - - 4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135 - Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved - PSU_SERDES_PLL_REF_SEL2_PLLREFSEL2 0x8 + * TrustZone classification for Ingress Address Translation 1 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_1 1 - PLL2 Reference Selection Register - (OFFSET, MASK, VALUE) (0XFD410008, 0x0000001FU ,0x00000008U) - RegMask = (SERDES_PLL_REF_SEL2_PLLREFSEL2_MASK | 0 ); + * TrustZone classification for Ingress Address Translation 2 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_2 1 - RegVal = ((0x00000008U << SERDES_PLL_REF_SEL2_PLLREFSEL2_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_PLL_REF_SEL2_OFFSET ,0x0000001FU ,0x00000008U); - /*############################################################################################################################ */ + * TrustZone classification for Ingress Address Translation 3 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_3 1 + + * TrustZone classification for Ingress Address Translation 4 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_4 1 + + * TrustZone classification for Ingress Address Translation 5 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_5 1 + + * TrustZone classification for Ingress Address Translation 6 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_6 1 - /*Register : PLL_REF_SEL3 @ 0XFD41000C

- - PLL3 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - - 4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135 - Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved - PSU_SERDES_PLL_REF_SEL3_PLLREFSEL3 0xF - - PLL3 Reference Selection Register - (OFFSET, MASK, VALUE) (0XFD41000C, 0x0000001FU ,0x0000000FU) - RegMask = (SERDES_PLL_REF_SEL3_PLLREFSEL3_MASK | 0 ); - - RegVal = ((0x0000000FU << SERDES_PLL_REF_SEL3_PLLREFSEL3_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_PLL_REF_SEL3_OFFSET ,0x0000001FU ,0x0000000FU); - /*############################################################################################################################ */ - - // : GT REFERENCE CLOCK FREQUENCY SELECTION - /*Register : L0_L0_REF_CLK_SEL @ 0XFD402860

- - Sel of lane 0 ref clock local mux. Set to 1 to select lane 0 slicer output. Set to 0 to select lane0 ref clock mux output. - PSU_SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL 0x1 - - Lane0 Ref Clock Selection Register - (OFFSET, MASK, VALUE) (0XFD402860, 0x00000080U ,0x00000080U) - RegMask = (SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_L0_REF_CLK_SEL_OFFSET ,0x00000080U ,0x00000080U); - /*############################################################################################################################ */ - - /*Register : L0_L1_REF_CLK_SEL @ 0XFD402864

- - Sel of lane 1 ref clock local mux. Set to 1 to select lane 1 slicer output. Set to 0 to select lane1 ref clock mux output. - PSU_SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL 0x0 - - Bit 3 of lane 1 ref clock mux one hot sel. Set to 1 to select lane 3 slicer output from ref clock network - PSU_SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3 0x1 - - Lane1 Ref Clock Selection Register - (OFFSET, MASK, VALUE) (0XFD402864, 0x00000088U ,0x00000008U) - RegMask = (SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_MASK | SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_MASK | 0 ); - - RegVal = ((0x00000000U << SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_SHIFT - | 0x00000001U << SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_L1_REF_CLK_SEL_OFFSET ,0x00000088U ,0x00000008U); - /*############################################################################################################################ */ - - /*Register : L0_L2_REF_CLK_SEL @ 0XFD402868

- - Sel of lane 2 ref clock local mux. Set to 1 to select lane 1 slicer output. Set to 0 to select lane2 ref clock mux output. - PSU_SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL 0x1 - - Lane2 Ref Clock Selection Register - (OFFSET, MASK, VALUE) (0XFD402868, 0x00000080U ,0x00000080U) - RegMask = (SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_L2_REF_CLK_SEL_OFFSET ,0x00000080U ,0x00000080U); - /*############################################################################################################################ */ - - /*Register : L0_L3_REF_CLK_SEL @ 0XFD40286C

- - Sel of lane 3 ref clock local mux. Set to 1 to select lane 3 slicer output. Set to 0 to select lane3 ref clock mux output. - PSU_SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL 0x0 - - Bit 1 of lane 3 ref clock mux one hot sel. Set to 1 to select lane 1 slicer output from ref clock network - PSU_SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1 0x1 - - Lane3 Ref Clock Selection Register - (OFFSET, MASK, VALUE) (0XFD40286C, 0x00000082U ,0x00000002U) - RegMask = (SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_MASK | SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_MASK | 0 ); - - RegVal = ((0x00000000U << SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_SHIFT - | 0x00000001U << SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_L3_REF_CLK_SEL_OFFSET ,0x00000082U ,0x00000002U); - /*############################################################################################################################ */ - - // : ENABLE SPREAD SPECTRUM - /*Register : L2_TM_PLL_DIG_37 @ 0XFD40A094

- - Enable/Disable coarse code satureation limiting logic - PSU_SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION 0x1 - - Test mode register 37 - (OFFSET, MASK, VALUE) (0XFD40A094, 0x00000010U ,0x00000010U) - RegMask = (SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_TM_PLL_DIG_37_OFFSET ,0x00000010U ,0x00000010U); - /*############################################################################################################################ */ - - /*Register : L2_PLL_SS_STEPS_0_LSB @ 0XFD40A368

- - Spread Spectrum No of Steps [7:0] - PSU_SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB 0x38 - - Spread Spectrum No of Steps bits 7:0 - (OFFSET, MASK, VALUE) (0XFD40A368, 0x000000FFU ,0x00000038U) - RegMask = (SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK | 0 ); - - RegVal = ((0x00000038U << SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_PLL_SS_STEPS_0_LSB_OFFSET ,0x000000FFU ,0x00000038U); - /*############################################################################################################################ */ - - /*Register : L2_PLL_SS_STEPS_1_MSB @ 0XFD40A36C

- - Spread Spectrum No of Steps [10:8] - PSU_SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB 0x03 - - Spread Spectrum No of Steps bits 10:8 - (OFFSET, MASK, VALUE) (0XFD40A36C, 0x00000007U ,0x00000003U) - RegMask = (SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK | 0 ); - - RegVal = ((0x00000003U << SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_PLL_SS_STEPS_1_MSB_OFFSET ,0x00000007U ,0x00000003U); - /*############################################################################################################################ */ - - /*Register : L3_PLL_SS_STEPS_0_LSB @ 0XFD40E368

- - Spread Spectrum No of Steps [7:0] - PSU_SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB 0xE0 - - Spread Spectrum No of Steps bits 7:0 - (OFFSET, MASK, VALUE) (0XFD40E368, 0x000000FFU ,0x000000E0U) - RegMask = (SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK | 0 ); - - RegVal = ((0x000000E0U << SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_PLL_SS_STEPS_0_LSB_OFFSET ,0x000000FFU ,0x000000E0U); - /*############################################################################################################################ */ - - /*Register : L3_PLL_SS_STEPS_1_MSB @ 0XFD40E36C

- - Spread Spectrum No of Steps [10:8] - PSU_SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB 0x3 - - Spread Spectrum No of Steps bits 10:8 - (OFFSET, MASK, VALUE) (0XFD40E36C, 0x00000007U ,0x00000003U) - RegMask = (SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK | 0 ); - - RegVal = ((0x00000003U << SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_PLL_SS_STEPS_1_MSB_OFFSET ,0x00000007U ,0x00000003U); - /*############################################################################################################################ */ - - /*Register : L1_PLL_SS_STEPS_0_LSB @ 0XFD406368

- - Spread Spectrum No of Steps [7:0] - PSU_SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB 0x58 - - Spread Spectrum No of Steps bits 7:0 - (OFFSET, MASK, VALUE) (0XFD406368, 0x000000FFU ,0x00000058U) - RegMask = (SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK | 0 ); - - RegVal = ((0x00000058U << SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L1_PLL_SS_STEPS_0_LSB_OFFSET ,0x000000FFU ,0x00000058U); - /*############################################################################################################################ */ - - /*Register : L1_PLL_SS_STEPS_1_MSB @ 0XFD40636C

- - Spread Spectrum No of Steps [10:8] - PSU_SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB 0x3 - - Spread Spectrum No of Steps bits 10:8 - (OFFSET, MASK, VALUE) (0XFD40636C, 0x00000007U ,0x00000003U) - RegMask = (SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK | 0 ); - - RegVal = ((0x00000003U << SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L1_PLL_SS_STEPS_1_MSB_OFFSET ,0x00000007U ,0x00000003U); - /*############################################################################################################################ */ - - /*Register : L1_PLL_SS_STEP_SIZE_0_LSB @ 0XFD406370

- - Step Size for Spread Spectrum [7:0] - PSU_SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB 0x7C - - Step Size for Spread Spectrum LSB - (OFFSET, MASK, VALUE) (0XFD406370, 0x000000FFU ,0x0000007CU) - RegMask = (SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK | 0 ); - - RegVal = ((0x0000007CU << SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_OFFSET ,0x000000FFU ,0x0000007CU); - /*############################################################################################################################ */ - - /*Register : L1_PLL_SS_STEP_SIZE_1 @ 0XFD406374

- - Step Size for Spread Spectrum [15:8] - PSU_SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1 0x33 - - Step Size for Spread Spectrum 1 - (OFFSET, MASK, VALUE) (0XFD406374, 0x000000FFU ,0x00000033U) - RegMask = (SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK | 0 ); - - RegVal = ((0x00000033U << SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L1_PLL_SS_STEP_SIZE_1_OFFSET ,0x000000FFU ,0x00000033U); - /*############################################################################################################################ */ - - /*Register : L1_PLL_SS_STEP_SIZE_2 @ 0XFD406378

- - Step Size for Spread Spectrum [23:16] - PSU_SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2 0x2 - - Step Size for Spread Spectrum 2 - (OFFSET, MASK, VALUE) (0XFD406378, 0x000000FFU ,0x00000002U) - RegMask = (SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK | 0 ); - - RegVal = ((0x00000002U << SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L1_PLL_SS_STEP_SIZE_2_OFFSET ,0x000000FFU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : L1_PLL_SS_STEP_SIZE_3_MSB @ 0XFD40637C

- - Step Size for Spread Spectrum [25:24] - PSU_SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB 0x0 - - Enable/Disable test mode force on SS step size - PSU_SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE 0x1 - - Enable/Disable test mode force on SS no of steps - PSU_SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS 0x1 - - Enable force on enable Spread Spectrum - (OFFSET, MASK, VALUE) (0XFD40637C, 0x00000033U ,0x00000030U) - RegMask = (SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK | SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK | SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK | 0 ); - - RegVal = ((0x00000000U << SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT - | 0x00000001U << SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT - | 0x00000001U << SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_OFFSET ,0x00000033U ,0x00000030U); - /*############################################################################################################################ */ - - /*Register : L2_PLL_SS_STEP_SIZE_0_LSB @ 0XFD40A370

- - Step Size for Spread Spectrum [7:0] - PSU_SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB 0xF4 - - Step Size for Spread Spectrum LSB - (OFFSET, MASK, VALUE) (0XFD40A370, 0x000000FFU ,0x000000F4U) - RegMask = (SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK | 0 ); - - RegVal = ((0x000000F4U << SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_OFFSET ,0x000000FFU ,0x000000F4U); - /*############################################################################################################################ */ - - /*Register : L2_PLL_SS_STEP_SIZE_1 @ 0XFD40A374

- - Step Size for Spread Spectrum [15:8] - PSU_SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1 0x31 - - Step Size for Spread Spectrum 1 - (OFFSET, MASK, VALUE) (0XFD40A374, 0x000000FFU ,0x00000031U) - RegMask = (SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK | 0 ); - - RegVal = ((0x00000031U << SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_PLL_SS_STEP_SIZE_1_OFFSET ,0x000000FFU ,0x00000031U); - /*############################################################################################################################ */ - - /*Register : L2_PLL_SS_STEP_SIZE_2 @ 0XFD40A378

- - Step Size for Spread Spectrum [23:16] - PSU_SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2 0x2 - - Step Size for Spread Spectrum 2 - (OFFSET, MASK, VALUE) (0XFD40A378, 0x000000FFU ,0x00000002U) - RegMask = (SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK | 0 ); - - RegVal = ((0x00000002U << SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_PLL_SS_STEP_SIZE_2_OFFSET ,0x000000FFU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : L2_PLL_SS_STEP_SIZE_3_MSB @ 0XFD40A37C

- - Step Size for Spread Spectrum [25:24] - PSU_SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB 0x0 - - Enable/Disable test mode force on SS step size - PSU_SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE 0x1 - - Enable/Disable test mode force on SS no of steps - PSU_SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS 0x1 - - Enable force on enable Spread Spectrum - (OFFSET, MASK, VALUE) (0XFD40A37C, 0x00000033U ,0x00000030U) - RegMask = (SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK | SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK | SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK | 0 ); - - RegVal = ((0x00000000U << SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT - | 0x00000001U << SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT - | 0x00000001U << SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_OFFSET ,0x00000033U ,0x00000030U); - /*############################################################################################################################ */ - - /*Register : L3_PLL_SS_STEP_SIZE_0_LSB @ 0XFD40E370

- - Step Size for Spread Spectrum [7:0] - PSU_SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB 0xC9 - - Step Size for Spread Spectrum LSB - (OFFSET, MASK, VALUE) (0XFD40E370, 0x000000FFU ,0x000000C9U) - RegMask = (SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK | 0 ); - - RegVal = ((0x000000C9U << SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_OFFSET ,0x000000FFU ,0x000000C9U); - /*############################################################################################################################ */ - - /*Register : L3_PLL_SS_STEP_SIZE_1 @ 0XFD40E374

- - Step Size for Spread Spectrum [15:8] - PSU_SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1 0xD2 - - Step Size for Spread Spectrum 1 - (OFFSET, MASK, VALUE) (0XFD40E374, 0x000000FFU ,0x000000D2U) - RegMask = (SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK | 0 ); - - RegVal = ((0x000000D2U << SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_PLL_SS_STEP_SIZE_1_OFFSET ,0x000000FFU ,0x000000D2U); - /*############################################################################################################################ */ - - /*Register : L3_PLL_SS_STEP_SIZE_2 @ 0XFD40E378

- - Step Size for Spread Spectrum [23:16] - PSU_SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2 0x1 - - Step Size for Spread Spectrum 2 - (OFFSET, MASK, VALUE) (0XFD40E378, 0x000000FFU ,0x00000001U) - RegMask = (SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_PLL_SS_STEP_SIZE_2_OFFSET ,0x000000FFU ,0x00000001U); - /*############################################################################################################################ */ - - /*Register : L3_PLL_SS_STEP_SIZE_3_MSB @ 0XFD40E37C

- - Step Size for Spread Spectrum [25:24] - PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB 0x0 - - Enable/Disable test mode force on SS step size - PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE 0x1 - - Enable/Disable test mode force on SS no of steps - PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS 0x1 - - Enable test mode forcing on enable Spread Spectrum - PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS 0x1 - - Enable force on enable Spread Spectrum - (OFFSET, MASK, VALUE) (0XFD40E37C, 0x000000B3U ,0x000000B0U) - RegMask = (SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK | SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK | SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK | SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_MASK | 0 ); - - RegVal = ((0x00000000U << SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT - | 0x00000001U << SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT - | 0x00000001U << SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT - | 0x00000001U << SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_OFFSET ,0x000000B3U ,0x000000B0U); - /*############################################################################################################################ */ - - /*Register : L2_TM_DIG_6 @ 0XFD40906C

- - Bypass Descrambler - PSU_SERDES_L2_TM_DIG_6_BYPASS_DESCRAM 0x1 - - Enable Bypass for <1> TM_DIG_CTRL_6 - PSU_SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM 0x1 - - Data path test modes in decoder and descram - (OFFSET, MASK, VALUE) (0XFD40906C, 0x00000003U ,0x00000003U) - RegMask = (SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_MASK | SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_SHIFT - | 0x00000001U << SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_TM_DIG_6_OFFSET ,0x00000003U ,0x00000003U); - /*############################################################################################################################ */ - - /*Register : L2_TX_DIG_TM_61 @ 0XFD4080F4

- - Bypass scrambler signal - PSU_SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM 0x1 - - Enable/disable scrambler bypass signal - PSU_SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM 0x1 - - MPHY PLL Gear and bypass scrambler - (OFFSET, MASK, VALUE) (0XFD4080F4, 0x00000003U ,0x00000003U) - RegMask = (SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_MASK | SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_SHIFT - | 0x00000001U << SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_TX_DIG_TM_61_OFFSET ,0x00000003U ,0x00000003U); - /*############################################################################################################################ */ - - /*Register : L3_PLL_FBDIV_FRAC_3_MSB @ 0XFD40E360

- - Enable test mode force on fractional mode enable - PSU_SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC 0x1 - - Fractional feedback division control and fractional value for feedback division bits 26:24 - (OFFSET, MASK, VALUE) (0XFD40E360, 0x00000040U ,0x00000040U) - RegMask = (SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_PLL_FBDIV_FRAC_3_MSB_OFFSET ,0x00000040U ,0x00000040U); - /*############################################################################################################################ */ - - /*Register : L3_TM_DIG_6 @ 0XFD40D06C

- - Bypass 8b10b decoder - PSU_SERDES_L3_TM_DIG_6_BYPASS_DECODER 0x1 - - Enable Bypass for <3> TM_DIG_CTRL_6 - PSU_SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC 0x1 - - Bypass Descrambler - PSU_SERDES_L3_TM_DIG_6_BYPASS_DESCRAM 0x1 - - Enable Bypass for <1> TM_DIG_CTRL_6 - PSU_SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM 0x1 - - Data path test modes in decoder and descram - (OFFSET, MASK, VALUE) (0XFD40D06C, 0x0000000FU ,0x0000000FU) - RegMask = (SERDES_L3_TM_DIG_6_BYPASS_DECODER_MASK | SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_MASK | SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_MASK | SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L3_TM_DIG_6_BYPASS_DECODER_SHIFT - | 0x00000001U << SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_SHIFT - | 0x00000001U << SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_SHIFT - | 0x00000001U << SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_DIG_6_OFFSET ,0x0000000FU ,0x0000000FU); - /*############################################################################################################################ */ - - /*Register : L3_TX_DIG_TM_61 @ 0XFD40C0F4

- - Enable/disable encoder bypass signal - PSU_SERDES_L3_TX_DIG_TM_61_BYPASS_ENC 0x1 - - Bypass scrambler signal - PSU_SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM 0x1 - - Enable/disable scrambler bypass signal - PSU_SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM 0x1 - - MPHY PLL Gear and bypass scrambler - (OFFSET, MASK, VALUE) (0XFD40C0F4, 0x0000000BU ,0x0000000BU) - RegMask = (SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_MASK | SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_MASK | SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_SHIFT - | 0x00000001U << SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_SHIFT - | 0x00000001U << SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TX_DIG_TM_61_OFFSET ,0x0000000BU ,0x0000000BU); - /*############################################################################################################################ */ - - /*Register : L3_TXPMA_ST_0 @ 0XFD40CB00

- - PHY Mode: 4'b000 - PCIe, 4'b001 - USB3, 4'b0010 - SATA, 4'b0100 - SGMII, 4'b0101 - DP, 4'b1000 - MPHY - PSU_SERDES_L3_TXPMA_ST_0_TX_PHY_MODE 0x21 - - Opmode Info - (OFFSET, MASK, VALUE) (0XFD40CB00, 0x000000F0U ,0x000000F0U) - RegMask = (SERDES_L3_TXPMA_ST_0_TX_PHY_MODE_MASK | 0 ); - - RegVal = ((0x00000021U << SERDES_L3_TXPMA_ST_0_TX_PHY_MODE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TXPMA_ST_0_OFFSET ,0x000000F0U ,0x000000F0U); - /*############################################################################################################################ */ - - // : ENABLE CHICKEN BIT FOR PCIE AND USB - /*Register : L0_TM_AUX_0 @ 0XFD4010CC

- - Spare- not used - PSU_SERDES_L0_TM_AUX_0_BIT_2 1 - - Spare registers - (OFFSET, MASK, VALUE) (0XFD4010CC, 0x00000020U ,0x00000020U) - RegMask = (SERDES_L0_TM_AUX_0_BIT_2_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L0_TM_AUX_0_BIT_2_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_TM_AUX_0_OFFSET ,0x00000020U ,0x00000020U); - /*############################################################################################################################ */ - - /*Register : L2_TM_AUX_0 @ 0XFD4090CC

- - Spare- not used - PSU_SERDES_L2_TM_AUX_0_BIT_2 1 - - Spare registers - (OFFSET, MASK, VALUE) (0XFD4090CC, 0x00000020U ,0x00000020U) - RegMask = (SERDES_L2_TM_AUX_0_BIT_2_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L2_TM_AUX_0_BIT_2_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_TM_AUX_0_OFFSET ,0x00000020U ,0x00000020U); - /*############################################################################################################################ */ - - // : ENABLING EYE SURF - /*Register : L0_TM_DIG_8 @ 0XFD401074

- - Enable Eye Surf - PSU_SERDES_L0_TM_DIG_8_EYESURF_ENABLE 0x1 - - Test modes for Elastic buffer and enabling Eye Surf - (OFFSET, MASK, VALUE) (0XFD401074, 0x00000010U ,0x00000010U) - RegMask = (SERDES_L0_TM_DIG_8_EYESURF_ENABLE_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L0_TM_DIG_8_EYESURF_ENABLE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_TM_DIG_8_OFFSET ,0x00000010U ,0x00000010U); - /*############################################################################################################################ */ - - /*Register : L1_TM_DIG_8 @ 0XFD405074

- - Enable Eye Surf - PSU_SERDES_L1_TM_DIG_8_EYESURF_ENABLE 0x1 - - Test modes for Elastic buffer and enabling Eye Surf - (OFFSET, MASK, VALUE) (0XFD405074, 0x00000010U ,0x00000010U) - RegMask = (SERDES_L1_TM_DIG_8_EYESURF_ENABLE_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L1_TM_DIG_8_EYESURF_ENABLE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L1_TM_DIG_8_OFFSET ,0x00000010U ,0x00000010U); - /*############################################################################################################################ */ - - /*Register : L2_TM_DIG_8 @ 0XFD409074

- - Enable Eye Surf - PSU_SERDES_L2_TM_DIG_8_EYESURF_ENABLE 0x1 - - Test modes for Elastic buffer and enabling Eye Surf - (OFFSET, MASK, VALUE) (0XFD409074, 0x00000010U ,0x00000010U) - RegMask = (SERDES_L2_TM_DIG_8_EYESURF_ENABLE_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L2_TM_DIG_8_EYESURF_ENABLE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_TM_DIG_8_OFFSET ,0x00000010U ,0x00000010U); - /*############################################################################################################################ */ - - /*Register : L3_TM_DIG_8 @ 0XFD40D074

- - Enable Eye Surf - PSU_SERDES_L3_TM_DIG_8_EYESURF_ENABLE 0x1 - - Test modes for Elastic buffer and enabling Eye Surf - (OFFSET, MASK, VALUE) (0XFD40D074, 0x00000010U ,0x00000010U) - RegMask = (SERDES_L3_TM_DIG_8_EYESURF_ENABLE_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L3_TM_DIG_8_EYESURF_ENABLE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_DIG_8_OFFSET ,0x00000010U ,0x00000010U); - /*############################################################################################################################ */ - - // : ILL SETTINGS FOR GAIN AND LOCK SETTINGS - /*Register : L0_TM_MISC2 @ 0XFD40189C

- - ILL calib counts BYPASSED with calcode bits - PSU_SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS 0x1 - - sampler cal - (OFFSET, MASK, VALUE) (0XFD40189C, 0x00000080U ,0x00000080U) - RegMask = (SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_TM_MISC2_OFFSET ,0x00000080U ,0x00000080U); - /*############################################################################################################################ */ - - /*Register : L0_TM_IQ_ILL1 @ 0XFD4018F8

- - IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS - PSU_SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0 0x64 - - iqpi cal code - (OFFSET, MASK, VALUE) (0XFD4018F8, 0x000000FFU ,0x00000064U) - RegMask = (SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK | 0 ); - - RegVal = ((0x00000064U << SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_TM_IQ_ILL1_OFFSET ,0x000000FFU ,0x00000064U); - /*############################################################################################################################ */ - - /*Register : L0_TM_IQ_ILL2 @ 0XFD4018FC

- - IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 - PSU_SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1 0x64 - - iqpi cal code - (OFFSET, MASK, VALUE) (0XFD4018FC, 0x000000FFU ,0x00000064U) - RegMask = (SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK | 0 ); - - RegVal = ((0x00000064U << SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_TM_IQ_ILL2_OFFSET ,0x000000FFU ,0x00000064U); - /*############################################################################################################################ */ - - /*Register : L0_TM_ILL12 @ 0XFD401990

- - G1A pll ctr bypass value - PSU_SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL 0x11 - - ill pll counter values - (OFFSET, MASK, VALUE) (0XFD401990, 0x000000FFU ,0x00000011U) - RegMask = (SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK | 0 ); - - RegVal = ((0x00000011U << SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_TM_ILL12_OFFSET ,0x000000FFU ,0x00000011U); - /*############################################################################################################################ */ - - /*Register : L0_TM_E_ILL1 @ 0XFD401924

- - E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS - PSU_SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0 0x4 - - epi cal code - (OFFSET, MASK, VALUE) (0XFD401924, 0x000000FFU ,0x00000004U) - RegMask = (SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK | 0 ); - - RegVal = ((0x00000004U << SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_TM_E_ILL1_OFFSET ,0x000000FFU ,0x00000004U); - /*############################################################################################################################ */ - - /*Register : L0_TM_E_ILL2 @ 0XFD401928

- - E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 - PSU_SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1 0xFE - - epi cal code - (OFFSET, MASK, VALUE) (0XFD401928, 0x000000FFU ,0x000000FEU) - RegMask = (SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK | 0 ); - - RegVal = ((0x000000FEU << SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_TM_E_ILL2_OFFSET ,0x000000FFU ,0x000000FEU); - /*############################################################################################################################ */ - - /*Register : L0_TM_IQ_ILL3 @ 0XFD401900

- - IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 - PSU_SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2 0x64 - - iqpi cal code - (OFFSET, MASK, VALUE) (0XFD401900, 0x000000FFU ,0x00000064U) - RegMask = (SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK | 0 ); - - RegVal = ((0x00000064U << SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_TM_IQ_ILL3_OFFSET ,0x000000FFU ,0x00000064U); - /*############################################################################################################################ */ - - /*Register : L0_TM_E_ILL3 @ 0XFD40192C

- - E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 - PSU_SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2 0x0 - - epi cal code - (OFFSET, MASK, VALUE) (0XFD40192C, 0x000000FFU ,0x00000000U) - RegMask = (SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK | 0 ); - - RegVal = ((0x00000000U << SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_TM_E_ILL3_OFFSET ,0x000000FFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : L0_TM_ILL8 @ 0XFD401980

- - ILL calibration code change wait time - PSU_SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT 0xFF - - ILL cal routine control - (OFFSET, MASK, VALUE) (0XFD401980, 0x000000FFU ,0x000000FFU) - RegMask = (SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_MASK | 0 ); - - RegVal = ((0x000000FFU << SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_TM_ILL8_OFFSET ,0x000000FFU ,0x000000FFU); - /*############################################################################################################################ */ - - /*Register : L0_TM_IQ_ILL8 @ 0XFD401914

- - IQ ILL polytrim bypass value - PSU_SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL 0xF7 - - iqpi polytrim - (OFFSET, MASK, VALUE) (0XFD401914, 0x000000FFU ,0x000000F7U) - RegMask = (SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK | 0 ); - - RegVal = ((0x000000F7U << SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_TM_IQ_ILL8_OFFSET ,0x000000FFU ,0x000000F7U); - /*############################################################################################################################ */ - - /*Register : L0_TM_IQ_ILL9 @ 0XFD401918

- - bypass IQ polytrim - PSU_SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM 0x1 - - enables for lf,constant gm trim and polytirm - (OFFSET, MASK, VALUE) (0XFD401918, 0x00000001U ,0x00000001U) - RegMask = (SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_TM_IQ_ILL9_OFFSET ,0x00000001U ,0x00000001U); - /*############################################################################################################################ */ - - /*Register : L0_TM_E_ILL8 @ 0XFD401940

- - E ILL polytrim bypass value - PSU_SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL 0xF7 - - epi polytrim - (OFFSET, MASK, VALUE) (0XFD401940, 0x000000FFU ,0x000000F7U) - RegMask = (SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK | 0 ); - - RegVal = ((0x000000F7U << SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_TM_E_ILL8_OFFSET ,0x000000FFU ,0x000000F7U); - /*############################################################################################################################ */ - - /*Register : L0_TM_E_ILL9 @ 0XFD401944

- - bypass E polytrim - PSU_SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM 0x1 - - enables for lf,constant gm trim and polytirm - (OFFSET, MASK, VALUE) (0XFD401944, 0x00000001U ,0x00000001U) - RegMask = (SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_TM_E_ILL9_OFFSET ,0x00000001U ,0x00000001U); - /*############################################################################################################################ */ - - /*Register : L2_TM_MISC2 @ 0XFD40989C

- - ILL calib counts BYPASSED with calcode bits - PSU_SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS 0x1 - - sampler cal - (OFFSET, MASK, VALUE) (0XFD40989C, 0x00000080U ,0x00000080U) - RegMask = (SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_TM_MISC2_OFFSET ,0x00000080U ,0x00000080U); - /*############################################################################################################################ */ - - /*Register : L2_TM_IQ_ILL1 @ 0XFD4098F8

- - IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS - PSU_SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0 0x1A - - iqpi cal code - (OFFSET, MASK, VALUE) (0XFD4098F8, 0x000000FFU ,0x0000001AU) - RegMask = (SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK | 0 ); - - RegVal = ((0x0000001AU << SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_TM_IQ_ILL1_OFFSET ,0x000000FFU ,0x0000001AU); - /*############################################################################################################################ */ - - /*Register : L2_TM_IQ_ILL2 @ 0XFD4098FC

- - IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 - PSU_SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1 0x1A - - iqpi cal code - (OFFSET, MASK, VALUE) (0XFD4098FC, 0x000000FFU ,0x0000001AU) - RegMask = (SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK | 0 ); - - RegVal = ((0x0000001AU << SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_TM_IQ_ILL2_OFFSET ,0x000000FFU ,0x0000001AU); - /*############################################################################################################################ */ - - /*Register : L2_TM_ILL12 @ 0XFD409990

- - G1A pll ctr bypass value - PSU_SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL 0x10 - - ill pll counter values - (OFFSET, MASK, VALUE) (0XFD409990, 0x000000FFU ,0x00000010U) - RegMask = (SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK | 0 ); - - RegVal = ((0x00000010U << SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_TM_ILL12_OFFSET ,0x000000FFU ,0x00000010U); - /*############################################################################################################################ */ - - /*Register : L2_TM_E_ILL1 @ 0XFD409924

- - E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS - PSU_SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0 0xFE - - epi cal code - (OFFSET, MASK, VALUE) (0XFD409924, 0x000000FFU ,0x000000FEU) - RegMask = (SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK | 0 ); - - RegVal = ((0x000000FEU << SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_TM_E_ILL1_OFFSET ,0x000000FFU ,0x000000FEU); - /*############################################################################################################################ */ - - /*Register : L2_TM_E_ILL2 @ 0XFD409928

- - E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 - PSU_SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1 0x0 - - epi cal code - (OFFSET, MASK, VALUE) (0XFD409928, 0x000000FFU ,0x00000000U) - RegMask = (SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK | 0 ); - - RegVal = ((0x00000000U << SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_TM_E_ILL2_OFFSET ,0x000000FFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : L2_TM_IQ_ILL3 @ 0XFD409900

- - IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 - PSU_SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2 0x1A - - iqpi cal code - (OFFSET, MASK, VALUE) (0XFD409900, 0x000000FFU ,0x0000001AU) - RegMask = (SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK | 0 ); - - RegVal = ((0x0000001AU << SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_TM_IQ_ILL3_OFFSET ,0x000000FFU ,0x0000001AU); - /*############################################################################################################################ */ - - /*Register : L2_TM_E_ILL3 @ 0XFD40992C

- - E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 - PSU_SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2 0x0 - - epi cal code - (OFFSET, MASK, VALUE) (0XFD40992C, 0x000000FFU ,0x00000000U) - RegMask = (SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK | 0 ); - - RegVal = ((0x00000000U << SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_TM_E_ILL3_OFFSET ,0x000000FFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : L2_TM_ILL8 @ 0XFD409980

- - ILL calibration code change wait time - PSU_SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT 0xFF - - ILL cal routine control - (OFFSET, MASK, VALUE) (0XFD409980, 0x000000FFU ,0x000000FFU) - RegMask = (SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_MASK | 0 ); - - RegVal = ((0x000000FFU << SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_TM_ILL8_OFFSET ,0x000000FFU ,0x000000FFU); - /*############################################################################################################################ */ - - /*Register : L2_TM_IQ_ILL8 @ 0XFD409914

- - IQ ILL polytrim bypass value - PSU_SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL 0xF7 - - iqpi polytrim - (OFFSET, MASK, VALUE) (0XFD409914, 0x000000FFU ,0x000000F7U) - RegMask = (SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK | 0 ); - - RegVal = ((0x000000F7U << SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_TM_IQ_ILL8_OFFSET ,0x000000FFU ,0x000000F7U); - /*############################################################################################################################ */ - - /*Register : L2_TM_IQ_ILL9 @ 0XFD409918

- - bypass IQ polytrim - PSU_SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM 0x1 - - enables for lf,constant gm trim and polytirm - (OFFSET, MASK, VALUE) (0XFD409918, 0x00000001U ,0x00000001U) - RegMask = (SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_TM_IQ_ILL9_OFFSET ,0x00000001U ,0x00000001U); - /*############################################################################################################################ */ - - /*Register : L2_TM_E_ILL8 @ 0XFD409940

- - E ILL polytrim bypass value - PSU_SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL 0xF7 - - epi polytrim - (OFFSET, MASK, VALUE) (0XFD409940, 0x000000FFU ,0x000000F7U) - RegMask = (SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK | 0 ); - - RegVal = ((0x000000F7U << SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_TM_E_ILL8_OFFSET ,0x000000FFU ,0x000000F7U); - /*############################################################################################################################ */ - - /*Register : L2_TM_E_ILL9 @ 0XFD409944

- - bypass E polytrim - PSU_SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM 0x1 - - enables for lf,constant gm trim and polytirm - (OFFSET, MASK, VALUE) (0XFD409944, 0x00000001U ,0x00000001U) - RegMask = (SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_TM_E_ILL9_OFFSET ,0x00000001U ,0x00000001U); - /*############################################################################################################################ */ - - /*Register : L3_TM_MISC2 @ 0XFD40D89C

- - ILL calib counts BYPASSED with calcode bits - PSU_SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS 0x1 - - sampler cal - (OFFSET, MASK, VALUE) (0XFD40D89C, 0x00000080U ,0x00000080U) - RegMask = (SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_MISC2_OFFSET ,0x00000080U ,0x00000080U); - /*############################################################################################################################ */ - - /*Register : L3_TM_IQ_ILL1 @ 0XFD40D8F8

- - IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS - PSU_SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0 0x7D - - iqpi cal code - (OFFSET, MASK, VALUE) (0XFD40D8F8, 0x000000FFU ,0x0000007DU) - RegMask = (SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK | 0 ); - - RegVal = ((0x0000007DU << SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_IQ_ILL1_OFFSET ,0x000000FFU ,0x0000007DU); - /*############################################################################################################################ */ - - /*Register : L3_TM_IQ_ILL2 @ 0XFD40D8FC

- - IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 - PSU_SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1 0x7D - - iqpi cal code - (OFFSET, MASK, VALUE) (0XFD40D8FC, 0x000000FFU ,0x0000007DU) - RegMask = (SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK | 0 ); - - RegVal = ((0x0000007DU << SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_IQ_ILL2_OFFSET ,0x000000FFU ,0x0000007DU); - /*############################################################################################################################ */ - - /*Register : L3_TM_ILL12 @ 0XFD40D990

- - G1A pll ctr bypass value - PSU_SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL 0x1 - - ill pll counter values - (OFFSET, MASK, VALUE) (0XFD40D990, 0x000000FFU ,0x00000001U) - RegMask = (SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_ILL12_OFFSET ,0x000000FFU ,0x00000001U); - /*############################################################################################################################ */ - - /*Register : L3_TM_E_ILL1 @ 0XFD40D924

- - E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS - PSU_SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0 0x9C - - epi cal code - (OFFSET, MASK, VALUE) (0XFD40D924, 0x000000FFU ,0x0000009CU) - RegMask = (SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK | 0 ); - - RegVal = ((0x0000009CU << SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_E_ILL1_OFFSET ,0x000000FFU ,0x0000009CU); - /*############################################################################################################################ */ - - /*Register : L3_TM_E_ILL2 @ 0XFD40D928

- - E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 - PSU_SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1 0x39 - - epi cal code - (OFFSET, MASK, VALUE) (0XFD40D928, 0x000000FFU ,0x00000039U) - RegMask = (SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK | 0 ); - - RegVal = ((0x00000039U << SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_E_ILL2_OFFSET ,0x000000FFU ,0x00000039U); - /*############################################################################################################################ */ - - /*Register : L3_TM_ILL11 @ 0XFD40D98C

- - G2A_PCIe1 PLL ctr bypass value - PSU_SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL 0x2 - - ill pll counter values - (OFFSET, MASK, VALUE) (0XFD40D98C, 0x000000F0U ,0x00000020U) - RegMask = (SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_MASK | 0 ); - - RegVal = ((0x00000002U << SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_ILL11_OFFSET ,0x000000F0U ,0x00000020U); - /*############################################################################################################################ */ - - /*Register : L3_TM_IQ_ILL3 @ 0XFD40D900

- - IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 - PSU_SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2 0x7D - - iqpi cal code - (OFFSET, MASK, VALUE) (0XFD40D900, 0x000000FFU ,0x0000007DU) - RegMask = (SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK | 0 ); - - RegVal = ((0x0000007DU << SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_IQ_ILL3_OFFSET ,0x000000FFU ,0x0000007DU); - /*############################################################################################################################ */ - - /*Register : L3_TM_E_ILL3 @ 0XFD40D92C

- - E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 - PSU_SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2 0x64 - - epi cal code - (OFFSET, MASK, VALUE) (0XFD40D92C, 0x000000FFU ,0x00000064U) - RegMask = (SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK | 0 ); - - RegVal = ((0x00000064U << SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_E_ILL3_OFFSET ,0x000000FFU ,0x00000064U); - /*############################################################################################################################ */ - - /*Register : L3_TM_ILL8 @ 0XFD40D980

- - ILL calibration code change wait time - PSU_SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT 0xFF - - ILL cal routine control - (OFFSET, MASK, VALUE) (0XFD40D980, 0x000000FFU ,0x000000FFU) - RegMask = (SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_MASK | 0 ); - - RegVal = ((0x000000FFU << SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_ILL8_OFFSET ,0x000000FFU ,0x000000FFU); - /*############################################################################################################################ */ - - /*Register : L3_TM_IQ_ILL8 @ 0XFD40D914

- - IQ ILL polytrim bypass value - PSU_SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL 0xF7 - - iqpi polytrim - (OFFSET, MASK, VALUE) (0XFD40D914, 0x000000FFU ,0x000000F7U) - RegMask = (SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK | 0 ); - - RegVal = ((0x000000F7U << SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_IQ_ILL8_OFFSET ,0x000000FFU ,0x000000F7U); - /*############################################################################################################################ */ - - /*Register : L3_TM_IQ_ILL9 @ 0XFD40D918

- - bypass IQ polytrim - PSU_SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM 0x1 - - enables for lf,constant gm trim and polytirm - (OFFSET, MASK, VALUE) (0XFD40D918, 0x00000001U ,0x00000001U) - RegMask = (SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_IQ_ILL9_OFFSET ,0x00000001U ,0x00000001U); - /*############################################################################################################################ */ - - /*Register : L3_TM_E_ILL8 @ 0XFD40D940

- - E ILL polytrim bypass value - PSU_SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL 0xF7 - - epi polytrim - (OFFSET, MASK, VALUE) (0XFD40D940, 0x000000FFU ,0x000000F7U) - RegMask = (SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK | 0 ); - - RegVal = ((0x000000F7U << SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_E_ILL8_OFFSET ,0x000000FFU ,0x000000F7U); - /*############################################################################################################################ */ - - /*Register : L3_TM_E_ILL9 @ 0XFD40D944

- - bypass E polytrim - PSU_SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM 0x1 - - enables for lf,constant gm trim and polytirm - (OFFSET, MASK, VALUE) (0XFD40D944, 0x00000001U ,0x00000001U) - RegMask = (SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_E_ILL9_OFFSET ,0x00000001U ,0x00000001U); - /*############################################################################################################################ */ - - // : SYMBOL LOCK AND WAIT - /*Register : L0_TM_DIG_21 @ 0XFD4010A8

- - pre lock comma count threshold. 2'b 00 : 3, 2'b 01 : 5, 2'b 10 : 10, 2'b 11 : 20 - PSU_SERDES_L0_TM_DIG_21_COMMA_PRE_LOCK_THRESH 0x11 - - Control symbol alignment locking - wait counts - (OFFSET, MASK, VALUE) (0XFD4010A8, 0x00000003U ,0x00000003U) - RegMask = (SERDES_L0_TM_DIG_21_COMMA_PRE_LOCK_THRESH_MASK | 0 ); - - RegVal = ((0x00000011U << SERDES_L0_TM_DIG_21_COMMA_PRE_LOCK_THRESH_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_TM_DIG_21_OFFSET ,0x00000003U ,0x00000003U); - /*############################################################################################################################ */ - - /*Register : L0_TM_DIG_10 @ 0XFD40107C

- - CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001 - PSU_SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME 0xF - - test control for changing cdr lock wait time - (OFFSET, MASK, VALUE) (0XFD40107C, 0x0000000FU ,0x0000000FU) - RegMask = (SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK | 0 ); - - RegVal = ((0x0000000FU << SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_TM_DIG_10_OFFSET ,0x0000000FU ,0x0000000FU); - /*############################################################################################################################ */ - - // : SIOU SETTINGS FOR BYPASS CONTROL,HSRX-DIG - /*Register : L0_TM_RST_DLY @ 0XFD4019A4

- - Delay apb reset by specified amount - PSU_SERDES_L0_TM_RST_DLY_APB_RST_DLY 0xFF - - reset delay for apb reset w.r.t pso of hsrx - (OFFSET, MASK, VALUE) (0XFD4019A4, 0x000000FFU ,0x000000FFU) - RegMask = (SERDES_L0_TM_RST_DLY_APB_RST_DLY_MASK | 0 ); - - RegVal = ((0x000000FFU << SERDES_L0_TM_RST_DLY_APB_RST_DLY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_TM_RST_DLY_OFFSET ,0x000000FFU ,0x000000FFU); - /*############################################################################################################################ */ - - /*Register : L0_TM_ANA_BYP_15 @ 0XFD401038

- - Enable Bypass for <7> of TM_ANA_BYPS_15 - PSU_SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE 0x1 - - Bypass control for pcs-pma interface. EQ supplies, main master supply and ps for samp c2c - (OFFSET, MASK, VALUE) (0XFD401038, 0x00000040U ,0x00000040U) - RegMask = (SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_TM_ANA_BYP_15_OFFSET ,0x00000040U ,0x00000040U); - /*############################################################################################################################ */ - - /*Register : L0_TM_ANA_BYP_12 @ 0XFD40102C

- - Enable Bypass for <7> of TM_ANA_BYPS_12 - PSU_SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG 0x1 - - Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr enable controls - (OFFSET, MASK, VALUE) (0XFD40102C, 0x00000040U ,0x00000040U) - RegMask = (SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_TM_ANA_BYP_12_OFFSET ,0x00000040U ,0x00000040U); - /*############################################################################################################################ */ - - /*Register : L1_TM_RST_DLY @ 0XFD4059A4

- - Delay apb reset by specified amount - PSU_SERDES_L1_TM_RST_DLY_APB_RST_DLY 0xFF - - reset delay for apb reset w.r.t pso of hsrx - (OFFSET, MASK, VALUE) (0XFD4059A4, 0x000000FFU ,0x000000FFU) - RegMask = (SERDES_L1_TM_RST_DLY_APB_RST_DLY_MASK | 0 ); - - RegVal = ((0x000000FFU << SERDES_L1_TM_RST_DLY_APB_RST_DLY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L1_TM_RST_DLY_OFFSET ,0x000000FFU ,0x000000FFU); - /*############################################################################################################################ */ - - /*Register : L1_TM_ANA_BYP_15 @ 0XFD405038

- - Enable Bypass for <7> of TM_ANA_BYPS_15 - PSU_SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE 0x1 - - Bypass control for pcs-pma interface. EQ supplies, main master supply and ps for samp c2c - (OFFSET, MASK, VALUE) (0XFD405038, 0x00000040U ,0x00000040U) - RegMask = (SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L1_TM_ANA_BYP_15_OFFSET ,0x00000040U ,0x00000040U); - /*############################################################################################################################ */ - - /*Register : L1_TM_ANA_BYP_12 @ 0XFD40502C

- - Enable Bypass for <7> of TM_ANA_BYPS_12 - PSU_SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG 0x1 - - Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr enable controls - (OFFSET, MASK, VALUE) (0XFD40502C, 0x00000040U ,0x00000040U) - RegMask = (SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L1_TM_ANA_BYP_12_OFFSET ,0x00000040U ,0x00000040U); - /*############################################################################################################################ */ - - /*Register : L2_TM_RST_DLY @ 0XFD4099A4

- - Delay apb reset by specified amount - PSU_SERDES_L2_TM_RST_DLY_APB_RST_DLY 0xFF - - reset delay for apb reset w.r.t pso of hsrx - (OFFSET, MASK, VALUE) (0XFD4099A4, 0x000000FFU ,0x000000FFU) - RegMask = (SERDES_L2_TM_RST_DLY_APB_RST_DLY_MASK | 0 ); - - RegVal = ((0x000000FFU << SERDES_L2_TM_RST_DLY_APB_RST_DLY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_TM_RST_DLY_OFFSET ,0x000000FFU ,0x000000FFU); - /*############################################################################################################################ */ - - /*Register : L2_TM_ANA_BYP_15 @ 0XFD409038

- - Enable Bypass for <7> of TM_ANA_BYPS_15 - PSU_SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE 0x1 - - Bypass control for pcs-pma interface. EQ supplies, main master supply and ps for samp c2c - (OFFSET, MASK, VALUE) (0XFD409038, 0x00000040U ,0x00000040U) - RegMask = (SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_TM_ANA_BYP_15_OFFSET ,0x00000040U ,0x00000040U); - /*############################################################################################################################ */ - - /*Register : L2_TM_ANA_BYP_12 @ 0XFD40902C

- - Enable Bypass for <7> of TM_ANA_BYPS_12 - PSU_SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG 0x1 - - Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr enable controls - (OFFSET, MASK, VALUE) (0XFD40902C, 0x00000040U ,0x00000040U) - RegMask = (SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_TM_ANA_BYP_12_OFFSET ,0x00000040U ,0x00000040U); - /*############################################################################################################################ */ - - /*Register : L3_TM_RST_DLY @ 0XFD40D9A4

- - Delay apb reset by specified amount - PSU_SERDES_L3_TM_RST_DLY_APB_RST_DLY 0xFF - - reset delay for apb reset w.r.t pso of hsrx - (OFFSET, MASK, VALUE) (0XFD40D9A4, 0x000000FFU ,0x000000FFU) - RegMask = (SERDES_L3_TM_RST_DLY_APB_RST_DLY_MASK | 0 ); - - RegVal = ((0x000000FFU << SERDES_L3_TM_RST_DLY_APB_RST_DLY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_RST_DLY_OFFSET ,0x000000FFU ,0x000000FFU); - /*############################################################################################################################ */ - - /*Register : L3_TM_ANA_BYP_15 @ 0XFD40D038

- - Enable Bypass for <7> of TM_ANA_BYPS_15 - PSU_SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE 0x1 - - Bypass control for pcs-pma interface. EQ supplies, main master supply and ps for samp c2c - (OFFSET, MASK, VALUE) (0XFD40D038, 0x00000040U ,0x00000040U) - RegMask = (SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_ANA_BYP_15_OFFSET ,0x00000040U ,0x00000040U); - /*############################################################################################################################ */ - - /*Register : L3_TM_ANA_BYP_12 @ 0XFD40D02C

- - Enable Bypass for <7> of TM_ANA_BYPS_12 - PSU_SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG 0x1 - - Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr enable controls - (OFFSET, MASK, VALUE) (0XFD40D02C, 0x00000040U ,0x00000040U) - RegMask = (SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_ANA_BYP_12_OFFSET ,0x00000040U ,0x00000040U); - /*############################################################################################################################ */ - - // : GT LANE SETTINGS - /*Register : ICM_CFG0 @ 0XFD410010

- - Controls UPHY Lane 0 protocol configuration. 0 - PowerDown, 1 - PCIe .0, 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII0, 6 - Unuse - , 7 - Unused - PSU_SERDES_ICM_CFG0_L0_ICM_CFG 1 - - Controls UPHY Lane 1 protocol configuration. 0 - PowerDown, 1 - PCIe.1, 2 - Sata1, 3 - USB0, 4 - DP.0, 5 - SGMII1, 6 - Unused - 7 - Unused - PSU_SERDES_ICM_CFG0_L1_ICM_CFG 4 - - ICM Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD410010, 0x00000077U ,0x00000041U) - RegMask = (SERDES_ICM_CFG0_L0_ICM_CFG_MASK | SERDES_ICM_CFG0_L1_ICM_CFG_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_ICM_CFG0_L0_ICM_CFG_SHIFT - | 0x00000004U << SERDES_ICM_CFG0_L1_ICM_CFG_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_ICM_CFG0_OFFSET ,0x00000077U ,0x00000041U); - /*############################################################################################################################ */ - - /*Register : ICM_CFG1 @ 0XFD410014

- - Controls UPHY Lane 2 protocol configuration. 0 - PowerDown, 1 - PCIe.1, 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII2, 6 - Unused - 7 - Unused - PSU_SERDES_ICM_CFG1_L2_ICM_CFG 3 - - Controls UPHY Lane 3 protocol configuration. 0 - PowerDown, 1 - PCIe.3, 2 - Sata1, 3 - USB1, 4 - DP.0, 5 - SGMII3, 6 - Unused - 7 - Unused - PSU_SERDES_ICM_CFG1_L3_ICM_CFG 2 - - ICM Configuration Register 1 - (OFFSET, MASK, VALUE) (0XFD410014, 0x00000077U ,0x00000023U) - RegMask = (SERDES_ICM_CFG1_L2_ICM_CFG_MASK | SERDES_ICM_CFG1_L3_ICM_CFG_MASK | 0 ); - - RegVal = ((0x00000003U << SERDES_ICM_CFG1_L2_ICM_CFG_SHIFT - | 0x00000002U << SERDES_ICM_CFG1_L3_ICM_CFG_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_ICM_CFG1_OFFSET ,0x00000077U ,0x00000023U); - /*############################################################################################################################ */ - - // : CHECKING PLL LOCK - // : ENABLE SERIAL DATA MUX DEEMPH - /*Register : L1_TXPMD_TM_45 @ 0XFD404CB4

- - Enable/disable DP post2 path - PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH 0x1 - - Override enable/disable of DP post2 path - PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH 0x1 - - Override enable/disable of DP post1 path - PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH 0x1 - - Enable/disable DP main path - PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH 0x1 - - Override enable/disable of DP main path - PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH 0x1 - - Post or pre or main DP path selection - (OFFSET, MASK, VALUE) (0XFD404CB4, 0x00000037U ,0x00000037U) - RegMask = (SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_MASK | SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_MASK | SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_MASK | SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_MASK | SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_SHIFT - | 0x00000001U << SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_SHIFT - | 0x00000001U << SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_SHIFT - | 0x00000001U << SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_SHIFT - | 0x00000001U << SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L1_TXPMD_TM_45_OFFSET ,0x00000037U ,0x00000037U); - /*############################################################################################################################ */ - - /*Register : L1_TX_ANA_TM_118 @ 0XFD4041D8

- - Test register force for enabling/disablign TX deemphasis bits <17:0> - PSU_SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0 0x1 - - Enable Override of TX deemphasis - (OFFSET, MASK, VALUE) (0XFD4041D8, 0x00000001U ,0x00000001U) - RegMask = (SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L1_TX_ANA_TM_118_OFFSET ,0x00000001U ,0x00000001U); - /*############################################################################################################################ */ - - /*Register : L3_TX_ANA_TM_118 @ 0XFD40C1D8

- - Test register force for enabling/disablign TX deemphasis bits <17:0> - PSU_SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0 0x1 - - Enable Override of TX deemphasis - (OFFSET, MASK, VALUE) (0XFD40C1D8, 0x00000001U ,0x00000001U) - RegMask = (SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TX_ANA_TM_118_OFFSET ,0x00000001U ,0x00000001U); - /*############################################################################################################################ */ - - // : CDR AND RX EQUALIZATION SETTINGS - /*Register : L3_TM_CDR5 @ 0XFD40DC14

- - FPHL FSM accumulate cycles - PSU_SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES 0x7 - - FFL Phase0 int gain aka 2ol SD update rate - PSU_SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN 0x6 - - Fast phase lock controls -- FSM accumulator cycle control and phase 0 int gain control. - (OFFSET, MASK, VALUE) (0XFD40DC14, 0x000000FFU ,0x000000E6U) - RegMask = (SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_MASK | SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_MASK | 0 ); - - RegVal = ((0x00000007U << SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_SHIFT - | 0x00000006U << SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_CDR5_OFFSET ,0x000000FFU ,0x000000E6U); - /*############################################################################################################################ */ - - /*Register : L3_TM_CDR16 @ 0XFD40DC40

- - FFL Phase0 prop gain aka 1ol SD update rate - PSU_SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN 0xC - - Fast phase lock controls -- phase 0 prop gain - (OFFSET, MASK, VALUE) (0XFD40DC40, 0x0000001FU ,0x0000000CU) - RegMask = (SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_MASK | 0 ); - - RegVal = ((0x0000000CU << SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_CDR16_OFFSET ,0x0000001FU ,0x0000000CU); - /*############################################################################################################################ */ - - /*Register : L3_TM_EQ0 @ 0XFD40D94C

- - EQ stg 2 controls BYPASSED - PSU_SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP 1 - - eq stg1 and stg2 controls - (OFFSET, MASK, VALUE) (0XFD40D94C, 0x00000020U ,0x00000020U) - RegMask = (SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_EQ0_OFFSET ,0x00000020U ,0x00000020U); - /*############################################################################################################################ */ - - /*Register : L3_TM_EQ1 @ 0XFD40D950

- - EQ STG2 RL PROG - PSU_SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG 0x2 - - EQ stg 2 preamp mode val - PSU_SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL 0x1 - - eq stg1 and stg2 controls - (OFFSET, MASK, VALUE) (0XFD40D950, 0x00000007U ,0x00000006U) - RegMask = (SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_MASK | SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_MASK | 0 ); - - RegVal = ((0x00000002U << SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_SHIFT - | 0x00000001U << SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_EQ1_OFFSET ,0x00000007U ,0x00000006U); - /*############################################################################################################################ */ - - // : GEM SERDES SETTINGS - // : ENABLE PRE EMPHAIS AND VOLTAGE SWING - /*Register : L1_TXPMD_TM_48 @ 0XFD404CC0

- - Margining factor value - PSU_SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR 0 - - Margining factor - (OFFSET, MASK, VALUE) (0XFD404CC0, 0x0000001FU ,0x00000000U) - RegMask = (SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_MASK | 0 ); - - RegVal = ((0x00000000U << SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L1_TXPMD_TM_48_OFFSET ,0x0000001FU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : L1_TX_ANA_TM_18 @ 0XFD404048

- - pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-emphasis, Others: reserved - PSU_SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0 0 - - Override for PIPE TX de-emphasis - (OFFSET, MASK, VALUE) (0XFD404048, 0x000000FFU ,0x00000000U) - RegMask = (SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK | 0 ); - - RegVal = ((0x00000000U << SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L1_TX_ANA_TM_18_OFFSET ,0x000000FFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : L3_TX_ANA_TM_18 @ 0XFD40C048

- - pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-emphasis, Others: reserved - PSU_SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0 0x1 - - Override for PIPE TX de-emphasis - (OFFSET, MASK, VALUE) (0XFD40C048, 0x000000FFU ,0x00000001U) - RegMask = (SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TX_ANA_TM_18_OFFSET ,0x000000FFU ,0x00000001U); - /*############################################################################################################################ */ - - - return 1; + * TrustZone classification for Ingress Address Translation 7 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_7 1 + + * TrustZone classification for Egress Address Translation 0 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_0 1 + + * TrustZone classification for Egress Address Translation 1 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_1 1 + + * TrustZone classification for Egress Address Translation 2 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_2 1 + + * TrustZone classification for Egress Address Translation 3 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_3 1 + + * TrustZone classification for Egress Address Translation 4 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_4 1 + + * TrustZone classification for Egress Address Translation 5 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_5 1 + + * TrustZone classification for Egress Address Translation 6 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_6 1 + + * TrustZone classification for Egress Address Translation 7 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_7 1 + + * TrustZone classification for DMA Registers + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_REGS 1 + + * TrustZone classification for MSIx Table + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_TABLE 1 + + * TrustZone classification for MSIx PBA + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_PBA 1 + + * TrustZone classification for ECAM + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_ECAM 1 + + * TrustZone classification for Bridge Common Registers + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_BRIDGE_REGS 1 + + * PCIe TrustZone settings. This register may only be modified during bootu + * p (while PCIe block is disabled) + * (OFFSET, MASK, VALUE) (0XFD690030, 0x01FFFFFFU ,0x01FFFFFFU) + */ + PSU_Mask_Write(FPD_SLCR_SECURE_SLCR_PCIE_OFFSET, + 0x01FFFFFFU, 0x01FFFFFFU); +/*##################################################################### */ + + /* + * USB TZ + */ + /* + * Register : slcr_usb @ 0XFF4B0034 + + * TrustZone Classification for USB3_0 + * PSU_LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_0 1 + + * TrustZone Classification for USB3_1 + * PSU_LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_1 1 + + * USB3 TrustZone settings + * (OFFSET, MASK, VALUE) (0XFF4B0034, 0x00000003U ,0x00000003U) + */ + PSU_Mask_Write(LPD_SLCR_SECURE_SLCR_USB_OFFSET, + 0x00000003U, 0x00000003U); +/*##################################################################### */ + + /* + * SD TZ + */ + /* + * Register : IOU_AXI_RPRTCN @ 0XFF240004 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD0_AXI_ARPROT 2 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD1_AXI_ARPROT 2 + + * AXI read protection type selection + * (OFFSET, MASK, VALUE) (0XFF240004, 0x003F0000U ,0x00120000U) + */ + PSU_Mask_Write(IOU_SECURE_SLCR_IOU_AXI_RPRTCN_OFFSET, + 0x003F0000U, 0x00120000U); +/*##################################################################### */ + + /* + * Register : IOU_AXI_WPRTCN @ 0XFF240000 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD0_AXI_AWPROT 2 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD1_AXI_AWPROT 2 + + * AXI write protection type selection + * (OFFSET, MASK, VALUE) (0XFF240000, 0x003F0000U ,0x00120000U) + */ + PSU_Mask_Write(IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET, + 0x003F0000U, 0x00120000U); +/*##################################################################### */ + + /* + * GEM TZ + */ + /* + * Register : IOU_AXI_RPRTCN @ 0XFF240004 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM0_AXI_ARPROT 2 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM1_AXI_ARPROT 2 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM2_AXI_ARPROT 2 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM3_AXI_ARPROT 2 + + * AXI read protection type selection + * (OFFSET, MASK, VALUE) (0XFF240004, 0x00000FFFU ,0x00000492U) + */ + PSU_Mask_Write(IOU_SECURE_SLCR_IOU_AXI_RPRTCN_OFFSET, + 0x00000FFFU, 0x00000492U); +/*##################################################################### */ + + /* + * Register : IOU_AXI_WPRTCN @ 0XFF240000 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM0_AXI_AWPROT 2 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM1_AXI_AWPROT 2 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM2_AXI_AWPROT 2 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM3_AXI_AWPROT 2 + + * AXI write protection type selection + * (OFFSET, MASK, VALUE) (0XFF240000, 0x00000FFFU ,0x00000492U) + */ + PSU_Mask_Write(IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET, + 0x00000FFFU, 0x00000492U); +/*##################################################################### */ + + /* + * QSPI TZ + */ + /* + * Register : IOU_AXI_WPRTCN @ 0XFF240000 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_QSPI_AXI_AWPROT 2 + + * AXI write protection type selection + * (OFFSET, MASK, VALUE) (0XFF240000, 0x0E000000U ,0x04000000U) + */ + PSU_Mask_Write(IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET, + 0x0E000000U, 0x04000000U); +/*##################################################################### */ + + /* + * NAND TZ + */ + /* + * Register : IOU_AXI_RPRTCN @ 0XFF240004 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_RPRTCN_NAND_AXI_ARPROT 2 + + * AXI read protection type selection + * (OFFSET, MASK, VALUE) (0XFF240004, 0x01C00000U ,0x00800000U) + */ + PSU_Mask_Write(IOU_SECURE_SLCR_IOU_AXI_RPRTCN_OFFSET, + 0x01C00000U, 0x00800000U); +/*##################################################################### */ + + /* + * Register : IOU_AXI_WPRTCN @ 0XFF240000 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_NAND_AXI_AWPROT 2 + + * AXI write protection type selection + * (OFFSET, MASK, VALUE) (0XFF240000, 0x01C00000U ,0x00800000U) + */ + PSU_Mask_Write(IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET, + 0x01C00000U, 0x00800000U); +/*##################################################################### */ + + /* + * DMA TZ + */ + /* + * Register : slcr_adma @ 0XFF4B0024 + + * TrustZone Classification for ADMA + * PSU_LPD_SLCR_SECURE_SLCR_ADMA_TZ 0xFF + + * RPU TrustZone settings + * (OFFSET, MASK, VALUE) (0XFF4B0024, 0x000000FFU ,0x000000FFU) + */ + PSU_Mask_Write(LPD_SLCR_SECURE_SLCR_ADMA_OFFSET, + 0x000000FFU, 0x000000FFU); +/*##################################################################### */ + + /* + * Register : slcr_gdma @ 0XFD690050 + + * TrustZone Classification for GDMA + * PSU_FPD_SLCR_SECURE_SLCR_GDMA_TZ 0xFF + + * GDMA Trustzone Settings + * (OFFSET, MASK, VALUE) (0XFD690050, 0x000000FFU ,0x000000FFU) + */ + PSU_Mask_Write(FPD_SLCR_SECURE_SLCR_GDMA_OFFSET, + 0x000000FFU, 0x000000FFU); +/*##################################################################### */ + + + return 1; } -unsigned long psu_resetout_init_data() { - // : TAKING SERDES PERIPHERAL OUT OF RESET RESET - // : PUTTING USB0 IN RESET - /*Register : RST_LPD_TOP @ 0XFF5E023C

+unsigned long psu_serdes_init_data(void) +{ + /* + * SERDES INITIALIZATION + */ + /* + * GT REFERENCE CLOCK SOURCE SELECTION + */ + /* + * Register : PLL_REF_SEL0 @ 0XFD410000 + + * PLL0 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 1 + * 2MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 24MHz, 0x8 - 26MHz, + * 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE + * - 108MHz, 0xF - 125MHz, 0x10 - 135MHz, 0x11 - 150 MHz. 0x12 to 0x1F - R + * eserved + * PSU_SERDES_PLL_REF_SEL0_PLLREFSEL0 0xD + + * PLL0 Reference Selection Register + * (OFFSET, MASK, VALUE) (0XFD410000, 0x0000001FU ,0x0000000DU) + */ + PSU_Mask_Write(SERDES_PLL_REF_SEL0_OFFSET, 0x0000001FU, 0x0000000DU); +/*##################################################################### */ + + /* + * Register : PLL_REF_SEL1 @ 0XFD410004 + + * PLL1 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 1 + * 2MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 24MHz, 0x8 - 26MHz, + * 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE + * - 108MHz, 0xF - 125MHz, 0x10 - 135MHz, 0x11 - 150 MHz. 0x12 to 0x1F - R + * eserved + * PSU_SERDES_PLL_REF_SEL1_PLLREFSEL1 0x9 + + * PLL1 Reference Selection Register + * (OFFSET, MASK, VALUE) (0XFD410004, 0x0000001FU ,0x00000009U) + */ + PSU_Mask_Write(SERDES_PLL_REF_SEL1_OFFSET, 0x0000001FU, 0x00000009U); +/*##################################################################### */ + + /* + * Register : PLL_REF_SEL2 @ 0XFD410008 + + * PLL2 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 1 + * 2MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 24MHz, 0x8 - 26MHz, + * 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE + * - 108MHz, 0xF - 125MHz, 0x10 - 135MHz, 0x11 - 150 MHz. 0x12 to 0x1F - R + * eserved + * PSU_SERDES_PLL_REF_SEL2_PLLREFSEL2 0x8 + + * PLL2 Reference Selection Register + * (OFFSET, MASK, VALUE) (0XFD410008, 0x0000001FU ,0x00000008U) + */ + PSU_Mask_Write(SERDES_PLL_REF_SEL2_OFFSET, 0x0000001FU, 0x00000008U); +/*##################################################################### */ + + /* + * Register : PLL_REF_SEL3 @ 0XFD41000C + + * PLL3 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 1 + * 2MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 24MHz, 0x8 - 26MHz, + * 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE + * - 108MHz, 0xF - 125MHz, 0x10 - 135MHz, 0x11 - 150 MHz. 0x12 to 0x1F - R + * eserved + * PSU_SERDES_PLL_REF_SEL3_PLLREFSEL3 0xF + + * PLL3 Reference Selection Register + * (OFFSET, MASK, VALUE) (0XFD41000C, 0x0000001FU ,0x0000000FU) + */ + PSU_Mask_Write(SERDES_PLL_REF_SEL3_OFFSET, 0x0000001FU, 0x0000000FU); +/*##################################################################### */ + + /* + * GT REFERENCE CLOCK FREQUENCY SELECTION + */ + /* + * Register : L0_L0_REF_CLK_SEL @ 0XFD402860 + + * Sel of lane 0 ref clock local mux. Set to 1 to select lane 0 slicer outp + * ut. Set to 0 to select lane0 ref clock mux output. + * PSU_SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL 0x1 + + * Lane0 Ref Clock Selection Register + * (OFFSET, MASK, VALUE) (0XFD402860, 0x00000080U ,0x00000080U) + */ + PSU_Mask_Write(SERDES_L0_L0_REF_CLK_SEL_OFFSET, + 0x00000080U, 0x00000080U); +/*##################################################################### */ + + /* + * Register : L0_L1_REF_CLK_SEL @ 0XFD402864 + + * Sel of lane 1 ref clock local mux. Set to 1 to select lane 1 slicer outp + * ut. Set to 0 to select lane1 ref clock mux output. + * PSU_SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL 0x0 + + * Bit 3 of lane 1 ref clock mux one hot sel. Set to 1 to select lane 3 sli + * cer output from ref clock network + * PSU_SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3 0x1 + + * Lane1 Ref Clock Selection Register + * (OFFSET, MASK, VALUE) (0XFD402864, 0x00000088U ,0x00000008U) + */ + PSU_Mask_Write(SERDES_L0_L1_REF_CLK_SEL_OFFSET, + 0x00000088U, 0x00000008U); +/*##################################################################### */ + + /* + * Register : L0_L2_REF_CLK_SEL @ 0XFD402868 + + * Sel of lane 2 ref clock local mux. Set to 1 to select lane 1 slicer outp + * ut. Set to 0 to select lane2 ref clock mux output. + * PSU_SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL 0x1 + + * Lane2 Ref Clock Selection Register + * (OFFSET, MASK, VALUE) (0XFD402868, 0x00000080U ,0x00000080U) + */ + PSU_Mask_Write(SERDES_L0_L2_REF_CLK_SEL_OFFSET, + 0x00000080U, 0x00000080U); +/*##################################################################### */ + + /* + * Register : L0_L3_REF_CLK_SEL @ 0XFD40286C + + * Sel of lane 3 ref clock local mux. Set to 1 to select lane 3 slicer outp + * ut. Set to 0 to select lane3 ref clock mux output. + * PSU_SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL 0x0 + + * Bit 1 of lane 3 ref clock mux one hot sel. Set to 1 to select lane 1 sli + * cer output from ref clock network + * PSU_SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1 0x1 + + * Lane3 Ref Clock Selection Register + * (OFFSET, MASK, VALUE) (0XFD40286C, 0x00000082U ,0x00000002U) + */ + PSU_Mask_Write(SERDES_L0_L3_REF_CLK_SEL_OFFSET, + 0x00000082U, 0x00000002U); +/*##################################################################### */ + + /* + * ENABLE SPREAD SPECTRUM + */ + /* + * Register : L2_TM_PLL_DIG_37 @ 0XFD40A094 + + * Enable/Disable coarse code satureation limiting logic + * PSU_SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION 0x1 + + * Test mode register 37 + * (OFFSET, MASK, VALUE) (0XFD40A094, 0x00000010U ,0x00000010U) + */ + PSU_Mask_Write(SERDES_L2_TM_PLL_DIG_37_OFFSET, + 0x00000010U, 0x00000010U); +/*##################################################################### */ + + /* + * Register : L2_PLL_SS_STEPS_0_LSB @ 0XFD40A368 + + * Spread Spectrum No of Steps [7:0] + * PSU_SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB 0x38 + + * Spread Spectrum No of Steps bits 7:0 + * (OFFSET, MASK, VALUE) (0XFD40A368, 0x000000FFU ,0x00000038U) + */ + PSU_Mask_Write(SERDES_L2_PLL_SS_STEPS_0_LSB_OFFSET, + 0x000000FFU, 0x00000038U); +/*##################################################################### */ + + /* + * Register : L2_PLL_SS_STEPS_1_MSB @ 0XFD40A36C + + * Spread Spectrum No of Steps [10:8] + * PSU_SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB 0x03 + + * Spread Spectrum No of Steps bits 10:8 + * (OFFSET, MASK, VALUE) (0XFD40A36C, 0x00000007U ,0x00000003U) + */ + PSU_Mask_Write(SERDES_L2_PLL_SS_STEPS_1_MSB_OFFSET, + 0x00000007U, 0x00000003U); +/*##################################################################### */ + + /* + * Register : L3_PLL_SS_STEPS_0_LSB @ 0XFD40E368 + + * Spread Spectrum No of Steps [7:0] + * PSU_SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB 0xE0 + + * Spread Spectrum No of Steps bits 7:0 + * (OFFSET, MASK, VALUE) (0XFD40E368, 0x000000FFU ,0x000000E0U) + */ + PSU_Mask_Write(SERDES_L3_PLL_SS_STEPS_0_LSB_OFFSET, + 0x000000FFU, 0x000000E0U); +/*##################################################################### */ + + /* + * Register : L3_PLL_SS_STEPS_1_MSB @ 0XFD40E36C + + * Spread Spectrum No of Steps [10:8] + * PSU_SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB 0x3 + + * Spread Spectrum No of Steps bits 10:8 + * (OFFSET, MASK, VALUE) (0XFD40E36C, 0x00000007U ,0x00000003U) + */ + PSU_Mask_Write(SERDES_L3_PLL_SS_STEPS_1_MSB_OFFSET, + 0x00000007U, 0x00000003U); +/*##################################################################### */ + + /* + * Register : L1_PLL_SS_STEPS_0_LSB @ 0XFD406368 + + * Spread Spectrum No of Steps [7:0] + * PSU_SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB 0x58 + + * Spread Spectrum No of Steps bits 7:0 + * (OFFSET, MASK, VALUE) (0XFD406368, 0x000000FFU ,0x00000058U) + */ + PSU_Mask_Write(SERDES_L1_PLL_SS_STEPS_0_LSB_OFFSET, + 0x000000FFU, 0x00000058U); +/*##################################################################### */ + + /* + * Register : L1_PLL_SS_STEPS_1_MSB @ 0XFD40636C + + * Spread Spectrum No of Steps [10:8] + * PSU_SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB 0x3 + + * Spread Spectrum No of Steps bits 10:8 + * (OFFSET, MASK, VALUE) (0XFD40636C, 0x00000007U ,0x00000003U) + */ + PSU_Mask_Write(SERDES_L1_PLL_SS_STEPS_1_MSB_OFFSET, + 0x00000007U, 0x00000003U); +/*##################################################################### */ + + /* + * Register : L1_PLL_SS_STEP_SIZE_0_LSB @ 0XFD406370 + + * Step Size for Spread Spectrum [7:0] + * PSU_SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB 0x7C + + * Step Size for Spread Spectrum LSB + * (OFFSET, MASK, VALUE) (0XFD406370, 0x000000FFU ,0x0000007CU) + */ + PSU_Mask_Write(SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_OFFSET, + 0x000000FFU, 0x0000007CU); +/*##################################################################### */ + + /* + * Register : L1_PLL_SS_STEP_SIZE_1 @ 0XFD406374 + + * Step Size for Spread Spectrum [15:8] + * PSU_SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1 0x33 + + * Step Size for Spread Spectrum 1 + * (OFFSET, MASK, VALUE) (0XFD406374, 0x000000FFU ,0x00000033U) + */ + PSU_Mask_Write(SERDES_L1_PLL_SS_STEP_SIZE_1_OFFSET, + 0x000000FFU, 0x00000033U); +/*##################################################################### */ + + /* + * Register : L1_PLL_SS_STEP_SIZE_2 @ 0XFD406378 + + * Step Size for Spread Spectrum [23:16] + * PSU_SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2 0x2 + + * Step Size for Spread Spectrum 2 + * (OFFSET, MASK, VALUE) (0XFD406378, 0x000000FFU ,0x00000002U) + */ + PSU_Mask_Write(SERDES_L1_PLL_SS_STEP_SIZE_2_OFFSET, + 0x000000FFU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : L1_PLL_SS_STEP_SIZE_3_MSB @ 0XFD40637C + + * Step Size for Spread Spectrum [25:24] + * PSU_SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB 0x0 + + * Enable/Disable test mode force on SS step size + * PSU_SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE 0x1 + + * Enable/Disable test mode force on SS no of steps + * PSU_SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS 0x1 + + * Enable force on enable Spread Spectrum + * (OFFSET, MASK, VALUE) (0XFD40637C, 0x00000033U ,0x00000030U) + */ + PSU_Mask_Write(SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_OFFSET, + 0x00000033U, 0x00000030U); +/*##################################################################### */ + + /* + * Register : L2_PLL_SS_STEP_SIZE_0_LSB @ 0XFD40A370 + + * Step Size for Spread Spectrum [7:0] + * PSU_SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB 0xF4 + + * Step Size for Spread Spectrum LSB + * (OFFSET, MASK, VALUE) (0XFD40A370, 0x000000FFU ,0x000000F4U) + */ + PSU_Mask_Write(SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_OFFSET, + 0x000000FFU, 0x000000F4U); +/*##################################################################### */ + + /* + * Register : L2_PLL_SS_STEP_SIZE_1 @ 0XFD40A374 + + * Step Size for Spread Spectrum [15:8] + * PSU_SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1 0x31 + + * Step Size for Spread Spectrum 1 + * (OFFSET, MASK, VALUE) (0XFD40A374, 0x000000FFU ,0x00000031U) + */ + PSU_Mask_Write(SERDES_L2_PLL_SS_STEP_SIZE_1_OFFSET, + 0x000000FFU, 0x00000031U); +/*##################################################################### */ + + /* + * Register : L2_PLL_SS_STEP_SIZE_2 @ 0XFD40A378 - USB 0 reset for control registers - PSU_CRL_APB_RST_LPD_TOP_USB0_APB_RESET 0X0 + * Step Size for Spread Spectrum [23:16] + * PSU_SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2 0x2 + + * Step Size for Spread Spectrum 2 + * (OFFSET, MASK, VALUE) (0XFD40A378, 0x000000FFU ,0x00000002U) + */ + PSU_Mask_Write(SERDES_L2_PLL_SS_STEP_SIZE_2_OFFSET, + 0x000000FFU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : L2_PLL_SS_STEP_SIZE_3_MSB @ 0XFD40A37C - Software control register for the LPD block. - (OFFSET, MASK, VALUE) (0XFF5E023C, 0x00000400U ,0x00000000U) - RegMask = (CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK | 0 ); + * Step Size for Spread Spectrum [25:24] + * PSU_SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB 0x0 - RegVal = ((0x00000000U << CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RST_LPD_TOP_OFFSET ,0x00000400U ,0x00000000U); - /*############################################################################################################################ */ + * Enable/Disable test mode force on SS step size + * PSU_SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE 0x1 + + * Enable/Disable test mode force on SS no of steps + * PSU_SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS 0x1 + + * Enable force on enable Spread Spectrum + * (OFFSET, MASK, VALUE) (0XFD40A37C, 0x00000033U ,0x00000030U) + */ + PSU_Mask_Write(SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_OFFSET, + 0x00000033U, 0x00000030U); +/*##################################################################### */ - // : USB0 PIPE POWER PRESENT - /*Register : fpd_power_prsnt @ 0XFF9D0080

+ /* + * Register : L3_PLL_SS_STEP_SIZE_0_LSB @ 0XFD40E370 + + * Step Size for Spread Spectrum [7:0] + * PSU_SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB 0xC9 + + * Step Size for Spread Spectrum LSB + * (OFFSET, MASK, VALUE) (0XFD40E370, 0x000000FFU ,0x000000C9U) + */ + PSU_Mask_Write(SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_OFFSET, + 0x000000FFU, 0x000000C9U); +/*##################################################################### */ - This bit is used to choose between PIPE power present and 1'b1 - PSU_USB3_0_FPD_POWER_PRSNT_OPTION 0X1 + /* + * Register : L3_PLL_SS_STEP_SIZE_1 @ 0XFD40E374 - fpd_power_prsnt - (OFFSET, MASK, VALUE) (0XFF9D0080, 0x00000001U ,0x00000001U) - RegMask = (USB3_0_FPD_POWER_PRSNT_OPTION_MASK | 0 ); + * Step Size for Spread Spectrum [15:8] + * PSU_SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1 0xD2 - RegVal = ((0x00000001U << USB3_0_FPD_POWER_PRSNT_OPTION_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (USB3_0_FPD_POWER_PRSNT_OFFSET ,0x00000001U ,0x00000001U); - /*############################################################################################################################ */ + * Step Size for Spread Spectrum 1 + * (OFFSET, MASK, VALUE) (0XFD40E374, 0x000000FFU ,0x000000D2U) + */ + PSU_Mask_Write(SERDES_L3_PLL_SS_STEP_SIZE_1_OFFSET, + 0x000000FFU, 0x000000D2U); +/*##################################################################### */ - /*Register : fpd_pipe_clk @ 0XFF9D007C

+ /* + * Register : L3_PLL_SS_STEP_SIZE_2 @ 0XFD40E378 - This bit is used to choose between PIPE clock coming from SerDes and the suspend clk - PSU_USB3_0_FPD_PIPE_CLK_OPTION 0x0 + * Step Size for Spread Spectrum [23:16] + * PSU_SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2 0x1 - fpd_pipe_clk - (OFFSET, MASK, VALUE) (0XFF9D007C, 0x00000001U ,0x00000000U) - RegMask = (USB3_0_FPD_PIPE_CLK_OPTION_MASK | 0 ); + * Step Size for Spread Spectrum 2 + * (OFFSET, MASK, VALUE) (0XFD40E378, 0x000000FFU ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L3_PLL_SS_STEP_SIZE_2_OFFSET, + 0x000000FFU, 0x00000001U); +/*##################################################################### */ - RegVal = ((0x00000000U << USB3_0_FPD_PIPE_CLK_OPTION_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (USB3_0_FPD_PIPE_CLK_OFFSET ,0x00000001U ,0x00000000U); - /*############################################################################################################################ */ + /* + * Register : L3_PLL_SS_STEP_SIZE_3_MSB @ 0XFD40E37C - // : - /*Register : RST_LPD_TOP @ 0XFF5E023C

+ * Step Size for Spread Spectrum [25:24] + * PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB 0x0 - USB 0 sleep circuit reset - PSU_CRL_APB_RST_LPD_TOP_USB0_HIBERRESET 0X0 + * Enable/Disable test mode force on SS step size + * PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE 0x1 - USB 0 reset - PSU_CRL_APB_RST_LPD_TOP_USB0_CORERESET 0X0 + * Enable/Disable test mode force on SS no of steps + * PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS 0x1 + + * Enable test mode forcing on enable Spread Spectrum + * PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS 0x1 - Software control register for the LPD block. - (OFFSET, MASK, VALUE) (0XFF5E023C, 0x00000140U ,0x00000000U) - RegMask = (CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK | CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK | 0 ); + * Enable force on enable Spread Spectrum + * (OFFSET, MASK, VALUE) (0XFD40E37C, 0x000000B3U ,0x000000B0U) + */ + PSU_Mask_Write(SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_OFFSET, + 0x000000B3U, 0x000000B0U); +/*##################################################################### */ - RegVal = ((0x00000000U << CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT - | 0x00000000U << CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RST_LPD_TOP_OFFSET ,0x00000140U ,0x00000000U); - /*############################################################################################################################ */ + /* + * Register : L2_TM_DIG_6 @ 0XFD40906C - // : PUTTING GEM0 IN RESET - /*Register : RST_LPD_IOU0 @ 0XFF5E0230

+ * Bypass Descrambler + * PSU_SERDES_L2_TM_DIG_6_BYPASS_DESCRAM 0x1 - GEM 3 reset - PSU_CRL_APB_RST_LPD_IOU0_GEM3_RESET 0X0 + * Enable Bypass for <1> TM_DIG_CTRL_6 + * PSU_SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM 0x1 - Software controlled reset for the GEMs - (OFFSET, MASK, VALUE) (0XFF5E0230, 0x00000008U ,0x00000000U) - RegMask = (CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK | 0 ); + * Data path test modes in decoder and descram + * (OFFSET, MASK, VALUE) (0XFD40906C, 0x00000003U ,0x00000003U) + */ + PSU_Mask_Write(SERDES_L2_TM_DIG_6_OFFSET, 0x00000003U, 0x00000003U); +/*##################################################################### */ + + /* + * Register : L2_TX_DIG_TM_61 @ 0XFD4080F4 - RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RST_LPD_IOU0_OFFSET ,0x00000008U ,0x00000000U); - /*############################################################################################################################ */ + * Bypass scrambler signal + * PSU_SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM 0x1 - // : PUTTING SATA IN RESET - /*Register : sata_misc_ctrl @ 0XFD3D0100

+ * Enable/disable scrambler bypass signal + * PSU_SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM 0x1 + + * MPHY PLL Gear and bypass scrambler + * (OFFSET, MASK, VALUE) (0XFD4080F4, 0x00000003U ,0x00000003U) + */ + PSU_Mask_Write(SERDES_L2_TX_DIG_TM_61_OFFSET, + 0x00000003U, 0x00000003U); +/*##################################################################### */ + + /* + * Register : L3_PLL_FBDIV_FRAC_3_MSB @ 0XFD40E360 + + * Enable test mode force on fractional mode enable + * PSU_SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC 0x1 + + * Fractional feedback division control and fractional value for feedback d + * ivision bits 26:24 + * (OFFSET, MASK, VALUE) (0XFD40E360, 0x00000040U ,0x00000040U) + */ + PSU_Mask_Write(SERDES_L3_PLL_FBDIV_FRAC_3_MSB_OFFSET, + 0x00000040U, 0x00000040U); +/*##################################################################### */ - Sata PM clock control select - PSU_SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL 0x3 + /* + * Register : L3_TM_DIG_6 @ 0XFD40D06C + + * Bypass 8b10b decoder + * PSU_SERDES_L3_TM_DIG_6_BYPASS_DECODER 0x1 - Misc Contorls for SATA.This register may only be modified during bootup (while SATA block is disabled) - (OFFSET, MASK, VALUE) (0XFD3D0100, 0x00000003U ,0x00000003U) - RegMask = (SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_MASK | 0 ); + * Enable Bypass for <3> TM_DIG_CTRL_6 + * PSU_SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC 0x1 - RegVal = ((0x00000003U << SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SIOU_SATA_MISC_CTRL_OFFSET ,0x00000003U ,0x00000003U); - /*############################################################################################################################ */ + * Bypass Descrambler + * PSU_SERDES_L3_TM_DIG_6_BYPASS_DESCRAM 0x1 - /*Register : RST_FPD_TOP @ 0XFD1A0100

+ * Enable Bypass for <1> TM_DIG_CTRL_6 + * PSU_SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM 0x1 + + * Data path test modes in decoder and descram + * (OFFSET, MASK, VALUE) (0XFD40D06C, 0x0000000FU ,0x0000000FU) + */ + PSU_Mask_Write(SERDES_L3_TM_DIG_6_OFFSET, 0x0000000FU, 0x0000000FU); +/*##################################################################### */ + + /* + * Register : L3_TX_DIG_TM_61 @ 0XFD40C0F4 + + * Enable/disable encoder bypass signal + * PSU_SERDES_L3_TX_DIG_TM_61_BYPASS_ENC 0x1 + + * Bypass scrambler signal + * PSU_SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM 0x1 + + * Enable/disable scrambler bypass signal + * PSU_SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM 0x1 - Sata block level reset - PSU_CRF_APB_RST_FPD_TOP_SATA_RESET 0X0 - - FPD Block level software controlled reset - (OFFSET, MASK, VALUE) (0XFD1A0100, 0x00000002U ,0x00000000U) - RegMask = (CRF_APB_RST_FPD_TOP_SATA_RESET_MASK | 0 ); - - RegVal = ((0x00000000U << CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_RST_FPD_TOP_OFFSET ,0x00000002U ,0x00000000U); - /*############################################################################################################################ */ - - // : PUTTING PCIE CFG AND BRIDGE IN RESET - /*Register : RST_FPD_TOP @ 0XFD1A0100

- - PCIE config reset - PSU_CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET 0X0 - - PCIE bridge block level reset (AXI interface) - PSU_CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET 0X0 - - FPD Block level software controlled reset - (OFFSET, MASK, VALUE) (0XFD1A0100, 0x000C0000U ,0x00000000U) - RegMask = (CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK | CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK | 0 ); - - RegVal = ((0x00000000U << CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT - | 0x00000000U << CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_RST_FPD_TOP_OFFSET ,0x000C0000U ,0x00000000U); - /*############################################################################################################################ */ - - // : PUTTING DP IN RESET - /*Register : RST_FPD_TOP @ 0XFD1A0100

- - Display Port block level reset (includes DPDMA) - PSU_CRF_APB_RST_FPD_TOP_DP_RESET 0X0 - - FPD Block level software controlled reset - (OFFSET, MASK, VALUE) (0XFD1A0100, 0x00010000U ,0x00000000U) - RegMask = (CRF_APB_RST_FPD_TOP_DP_RESET_MASK | 0 ); - - RegVal = ((0x00000000U << CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_RST_FPD_TOP_OFFSET ,0x00010000U ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : DP_PHY_RESET @ 0XFD4A0200

- - Set to '1' to hold the GT in reset. Clear to release. - PSU_DP_DP_PHY_RESET_GT_RESET 0X0 - - Reset the transmitter PHY. - (OFFSET, MASK, VALUE) (0XFD4A0200, 0x00000002U ,0x00000000U) - RegMask = (DP_DP_PHY_RESET_GT_RESET_MASK | 0 ); - - RegVal = ((0x00000000U << DP_DP_PHY_RESET_GT_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DP_DP_PHY_RESET_OFFSET ,0x00000002U ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : DP_TX_PHY_POWER_DOWN @ 0XFD4A0238

- - Two bits per lane. When set to 11, moves the GT to power down mode. When set to 00, GT will be in active state. bits [1:0] - - ane0 Bits [3:2] - lane 1 - PSU_DP_DP_TX_PHY_POWER_DOWN_POWER_DWN 0X0 - - Control PHY Power down - (OFFSET, MASK, VALUE) (0XFD4A0238, 0x0000000FU ,0x00000000U) - RegMask = (DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK | 0 ); - - RegVal = ((0x00000000U << DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DP_DP_TX_PHY_POWER_DOWN_OFFSET ,0x0000000FU ,0x00000000U); - /*############################################################################################################################ */ - - // : USB0 GFLADJ - /*Register : GUSB2PHYCFG @ 0XFE20C200

- - USB 2.0 Turnaround Time (USBTrdTim) Sets the turnaround time in PHY clocks. Specifies the response time for a MAC request to - he Packet FIFO Controller (PFC) to fetch data from the DFIFO (SPRAM). The following are the required values for the minimum S - C bus frequency of 60 MHz. USB turnaround time is a critical certification criteria when using long cables and five hub level - . The required values for this field: - 4'h5: When the MAC interface is 16-bit UTMI+. - 4'h9: When the MAC interface is 8-bit - UTMI+/ULPI. If SoC bus clock is less than 60 MHz, and USB turnaround time is not critical, this field can be set to a larger - alue. Note: This field is valid only in device mode. - PSU_USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM 0x9 - - Transceiver Delay: Enables a delay between the assertion of the UTMI/ULPI Transceiver Select signal (for HS) and the assertio - of the TxValid signal during a HS Chirp. When this bit is set to 1, a delay (of approximately 2.5 us) is introduced from the - time when the Transceiver Select is set to 2'b00 (HS) to the time the TxValid is driven to 0 for sending the chirp-K. This de - ay is required for some UTMI/ULPI PHYs. Note: - If you enable the hibernation feature when the device core comes out of power - off, you must re-initialize this bit with the appropriate value because the core does not save and restore this bit value dur - ng hibernation. - This bit is valid only in device mode. - PSU_USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY 0x0 - - Enable utmi_sleep_n and utmi_l1_suspend_n (EnblSlpM) The application uses this bit to control utmi_sleep_n and utmi_l1_suspen - _n assertion to the PHY in the L1 state. - 1'b0: utmi_sleep_n and utmi_l1_suspend_n assertion from the core is not transferre - to the external PHY. - 1'b1: utmi_sleep_n and utmi_l1_suspend_n assertion from the core is transferred to the external PHY. - ote: This bit must be set high for Port0 if PHY is used. Note: In Device mode - Before issuing any device endpoint command wh - n operating in 2.0 speeds, disable this bit and enable it after the command completes. Without disabling this bit, if a comma - d is issued when the device is in L1 state and if mac2_clk (utmi_clk/ulpi_clk) is gated off, the command will not get complet - d. - PSU_USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM 0x0 - - USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial Transceiver Select The application uses this bit to select a high-speed P - Y or a full-speed transceiver. - 1'b0: USB 2.0 high-speed UTMI+ or ULPI PHY. This bit is always 0, with Write Only access. - - 'b1: USB 1.1 full-speed serial transceiver. This bit is always 1, with Write Only access. If both interface types are selecte - in coreConsultant (that is, parameters' values are not zero), the application uses this bit to select the active interface i - active, with Read-Write bit access. Note: USB 1.1 full-serial transceiver is not supported. This bit always reads as 1'b0. - PSU_USB3_0_XHCI_GUSB2PHYCFG_PHYSEL 0x0 - - Full-Speed Serial Interface Select (FSIntf) The application uses this bit to select a unidirectional or bidirectional USB 1.1 - full-speed serial transceiver interface. - 1'b0: 6-pin unidirectional full-speed serial interface. This bit is set to 0 with - ead Only access. - 1'b1: 3-pin bidirectional full-speed serial interface. This bit is set to 0 with Read Only access. Note: U - B 1.1 full-speed serial interface is not supported. This bit always reads as 1'b0. - PSU_USB3_0_XHCI_GUSB2PHYCFG_FSINTF 0x0 - - ULPI or UTMI+ Select (ULPI_UTMI_Sel) The application uses this bit to select a UTMI+ or ULPI Interface. - 1'b0: UTMI+ Interfa - e - 1'b1: ULPI Interface This bit is writable only if UTMI+ and ULPI is specified for High-Speed PHY Interface(s) in coreCons - ltant configuration (DWC_USB3_HSPHY_INTERFACE = 3). Otherwise, this bit is read-only and the value depends on the interface s - lected through DWC_USB3_HSPHY_INTERFACE. - PSU_USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL 0x1 - - PHY Interface (PHYIf) If UTMI+ is selected, the application uses this bit to configure the core to support a UTMI+ PHY with a - 8- or 16-bit interface. - 1'b0: 8 bits - 1'b1: 16 bits ULPI Mode: 1'b0 Note: - All the enabled 2.0 ports must have the same - lock frequency as Port0 clock frequency (utmi_clk[0]). - The UTMI 8-bit and 16-bit modes cannot be used together for differen - ports at the same time (that is, all the ports must be in 8-bit mode, or all of them must be in 16-bit mode, at a time). - I - any of the USB 2.0 ports is selected as ULPI port for operation, then all the USB 2.0 ports must be operating at 60 MHz. - PSU_USB3_0_XHCI_GUSB2PHYCFG_PHYIF 0x0 - - HS/FS Timeout Calibration (TOutCal) The number of PHY clocks, as indicated by the application in this field, is multiplied by - a bit-time factor; this factor is added to the high-speed/full-speed interpacket timeout duration in the core to account for - dditional delays introduced by the PHY. This may be required, since the delay introduced by the PHY in generating the linesta - e condition may vary among PHYs. The USB standard timeout value for high-speed operation is 736 to 816 (inclusive) bit times. - The USB standard timeout value for full-speed operation is 16 to 18 (inclusive) bit times. The application must program this - ield based on the speed of connection. The number of bit times added per PHY clock are: High-speed operation: - One 30-MHz PH - clock = 16 bit times - One 60-MHz PHY clock = 8 bit times Full-speed operation: - One 30-MHz PHY clock = 0.4 bit times - One - 60-MHz PHY clock = 0.2 bit times - One 48-MHz PHY clock = 0.25 bit times - PSU_USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL 0x7 - - Global USB2 PHY Configuration Register The application must program this register before starting any transactions on either - he SoC bus or the USB. In Device-only configurations, only one register is needed. In Host mode, per-port registers are imple - ented. - (OFFSET, MASK, VALUE) (0XFE20C200, 0x00003FBFU ,0x00002417U) - RegMask = (USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_MASK | USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_MASK | USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_MASK | USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_MASK | USB3_0_XHCI_GUSB2PHYCFG_FSINTF_MASK | USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_MASK | USB3_0_XHCI_GUSB2PHYCFG_PHYIF_MASK | USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_MASK | 0 ); - - RegVal = ((0x00000009U << USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_SHIFT - | 0x00000000U << USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_SHIFT - | 0x00000000U << USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_SHIFT - | 0x00000000U << USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_SHIFT - | 0x00000000U << USB3_0_XHCI_GUSB2PHYCFG_FSINTF_SHIFT - | 0x00000001U << USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_SHIFT - | 0x00000000U << USB3_0_XHCI_GUSB2PHYCFG_PHYIF_SHIFT - | 0x00000007U << USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (USB3_0_XHCI_GUSB2PHYCFG_OFFSET ,0x00003FBFU ,0x00002417U); - /*############################################################################################################################ */ - - /*Register : GFLADJ @ 0XFE20C630

- - This field indicates the frame length adjustment to be applied when SOF/ITP counter is running on the ref_clk. This register - alue is used to adjust the ITP interval when GCTL[SOFITPSYNC] is set to '1'; SOF and ITP interval when GLADJ.GFLADJ_REFCLK_LP - _SEL is set to '1'. This field must be programmed to a non-zero value only if GFLADJ_REFCLK_LPM_SEL is set to '1' or GCTL.SOF - TPSYNC is set to '1'. The value is derived as follows: FLADJ_REF_CLK_FLADJ=((125000/ref_clk_period_integer)-(125000/ref_clk_p - riod)) * ref_clk_period where - the ref_clk_period_integer is the integer value of the ref_clk period got by truncating the d - cimal (fractional) value that is programmed in the GUCTL.REF_CLK_PERIOD field. - the ref_clk_period is the ref_clk period inc - uding the fractional value. Examples: If the ref_clk is 24 MHz then - GUCTL.REF_CLK_PERIOD = 41 - GFLADJ.GLADJ_REFCLK_FLADJ = - ((125000/41)-(125000/41.6666))*41.6666 = 2032 (ignoring the fractional value) If the ref_clk is 48 MHz then - GUCTL.REF_CLK_P - RIOD = 20 - GFLADJ.GLADJ_REFCLK_FLADJ = ((125000/20)-(125000/20.8333))*20.8333 = 5208 (ignoring the fractional value) - PSU_USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ 0x0 - - Global Frame Length Adjustment Register This register provides options for the software to control the core behavior with res - ect to SOF (Start of Frame) and ITP (Isochronous Timestamp Packet) timers and frame timer functionality. It provides an optio - to override the fladj_30mhz_reg sideband signal. In addition, it enables running SOF or ITP frame timer counters completely - rom the ref_clk. This facilitates hardware LPM in host mode with the SOF or ITP counters being run from the ref_clk signal. - (OFFSET, MASK, VALUE) (0XFE20C630, 0x003FFF00U ,0x00000000U) - RegMask = (USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_MASK | 0 ); - - RegVal = ((0x00000000U << USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (USB3_0_XHCI_GFLADJ_OFFSET ,0x003FFF00U ,0x00000000U); - /*############################################################################################################################ */ - - // : UPDATING TWO PCIE REGISTERS DEFAULT VALUES, AS THESE REGISTERS HAVE INCORRECT RESET VALUES IN SILICON. - /*Register : ATTR_25 @ 0XFD480064

- - If TRUE Completion Timeout Disable is supported. This is required to be TRUE for Endpoint and either setting allowed for Root - ports. Drives Device Capability 2 [4]; EP=0x0001; RP=0x0001 - PSU_PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED 0X1 - - ATTR_25 - (OFFSET, MASK, VALUE) (0XFD480064, 0x00000200U ,0x00000200U) - RegMask = (PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_MASK | 0 ); - - RegVal = ((0x00000001U << PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_25_OFFSET ,0x00000200U ,0x00000200U); - /*############################################################################################################################ */ - - // : PCIE SETTINGS - /*Register : ATTR_7 @ 0XFD48001C

- - Specifies mask/settings for Base Address Register (BAR) 0. If BAR is not to be implemented, set to 32'h00000000. Bits are def - ned as follows: Memory Space BAR [0] = Mem Space Indicator (set to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = - Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory a - erture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR1,BAR0\'7d to 1. IO Space BAR 0] = IO Space Indicator - set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o apert - re size in bytes.; EP=0x0004; RP=0x0000 - PSU_PCIE_ATTRIB_ATTR_7_ATTR_BAR0 0x0 - - ATTR_7 - (OFFSET, MASK, VALUE) (0XFD48001C, 0x0000FFFFU ,0x00000000U) - RegMask = (PCIE_ATTRIB_ATTR_7_ATTR_BAR0_MASK | 0 ); - - RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_7_ATTR_BAR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_7_OFFSET ,0x0000FFFFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : ATTR_8 @ 0XFD480020

- - Specifies mask/settings for Base Address Register (BAR) 0. If BAR is not to be implemented, set to 32'h00000000. Bits are def - ned as follows: Memory Space BAR [0] = Mem Space Indicator (set to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = - Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory a - erture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR1,BAR0\'7d to 1. IO Space BAR 0] = IO Space Indicator - set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o apert - re size in bytes.; EP=0xFFF0; RP=0x0000 - PSU_PCIE_ATTRIB_ATTR_8_ATTR_BAR0 0x0 - - ATTR_8 - (OFFSET, MASK, VALUE) (0XFD480020, 0x0000FFFFU ,0x00000000U) - RegMask = (PCIE_ATTRIB_ATTR_8_ATTR_BAR0_MASK | 0 ); - - RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_8_ATTR_BAR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_8_OFFSET ,0x0000FFFFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : ATTR_9 @ 0XFD480024

- - Specifies mask/settings for Base Address Register (BAR) 1 if BAR0 is a 32-bit BAR, or the upper bits of \'7bBAR1,BAR0\'7d if - AR0 is a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR0 description if this functions as the uppe - bits of a 64-bit BAR. Bits are defined as follows: Memory Space BAR (not upper bits of BAR0) [0] = Mem Space Indicator (set - o 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if - 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of - '7bBAR2,BAR1\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable b - ts of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000 - PSU_PCIE_ATTRIB_ATTR_9_ATTR_BAR1 0x0 - - ATTR_9 - (OFFSET, MASK, VALUE) (0XFD480024, 0x0000FFFFU ,0x00000000U) - RegMask = (PCIE_ATTRIB_ATTR_9_ATTR_BAR1_MASK | 0 ); - - RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_9_ATTR_BAR1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_9_OFFSET ,0x0000FFFFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : ATTR_10 @ 0XFD480028

- - Specifies mask/settings for Base Address Register (BAR) 1 if BAR0 is a 32-bit BAR, or the upper bits of \'7bBAR1,BAR0\'7d if - AR0 is a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR0 description if this functions as the uppe - bits of a 64-bit BAR. Bits are defined as follows: Memory Space BAR (not upper bits of BAR0) [0] = Mem Space Indicator (set - o 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if - 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of - '7bBAR2,BAR1\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable b - ts of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000 - PSU_PCIE_ATTRIB_ATTR_10_ATTR_BAR1 0x0 - - ATTR_10 - (OFFSET, MASK, VALUE) (0XFD480028, 0x0000FFFFU ,0x00000000U) - RegMask = (PCIE_ATTRIB_ATTR_10_ATTR_BAR1_MASK | 0 ); - - RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_10_ATTR_BAR1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_10_OFFSET ,0x0000FFFFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : ATTR_11 @ 0XFD48002C

- - For an endpoint, specifies mask/settings for Base Address Register (BAR) 2 if BAR1 is a 32-bit BAR, or the upper bits of \'7b - AR2,BAR1\'7d if BAR1 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR1 descri - tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to 00FF_FFFF. For an endpoin - , bits are defined as follows: Memory Space BAR (not upper bits of BAR1) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi - ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe - most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR3,BAR2\'7d to - . IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper - ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0x0004; RP=0xFFFF - PSU_PCIE_ATTRIB_ATTR_11_ATTR_BAR2 0xFFFF - - ATTR_11 - (OFFSET, MASK, VALUE) (0XFD48002C, 0x0000FFFFU ,0x0000FFFFU) - RegMask = (PCIE_ATTRIB_ATTR_11_ATTR_BAR2_MASK | 0 ); - - RegVal = ((0x0000FFFFU << PCIE_ATTRIB_ATTR_11_ATTR_BAR2_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_11_OFFSET ,0x0000FFFFU ,0x0000FFFFU); - /*############################################################################################################################ */ - - /*Register : ATTR_12 @ 0XFD480030

- - For an endpoint, specifies mask/settings for Base Address Register (BAR) 2 if BAR1 is a 32-bit BAR, or the upper bits of \'7b - AR2,BAR1\'7d if BAR1 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR1 descri - tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to 00FF_FFFF. For an endpoin - , bits are defined as follows: Memory Space BAR (not upper bits of BAR1) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi - ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe - most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR3,BAR2\'7d to - . IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper - ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFF0; RP=0x00FF - PSU_PCIE_ATTRIB_ATTR_12_ATTR_BAR2 0xFF - - ATTR_12 - (OFFSET, MASK, VALUE) (0XFD480030, 0x0000FFFFU ,0x000000FFU) - RegMask = (PCIE_ATTRIB_ATTR_12_ATTR_BAR2_MASK | 0 ); - - RegVal = ((0x000000FFU << PCIE_ATTRIB_ATTR_12_ATTR_BAR2_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_12_OFFSET ,0x0000FFFFU ,0x000000FFU); - /*############################################################################################################################ */ - - /*Register : ATTR_13 @ 0XFD480034

- - For an endpoint, specifies mask/settings for Base Address Register (BAR) 3 if BAR2 is a 32-bit BAR, or the upper bits of \'7b - AR3,BAR2\'7d if BAR2 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR2 descri - tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: FFFF_0000 = IO Limit/Bas - Registers not implemented FFFF_F0F0 = IO Limit/Base Registers use 16-bit decode FFFF_F1F1 = IO Limit/Base Registers use 32-b - t decode For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of BAR2) [0] = Mem Space Indicator (s - t to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; - if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits - f \'7bBAR4,BAR3\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writabl - bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000 - PSU_PCIE_ATTRIB_ATTR_13_ATTR_BAR3 0x0 - - ATTR_13 - (OFFSET, MASK, VALUE) (0XFD480034, 0x0000FFFFU ,0x00000000U) - RegMask = (PCIE_ATTRIB_ATTR_13_ATTR_BAR3_MASK | 0 ); - - RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_13_ATTR_BAR3_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_13_OFFSET ,0x0000FFFFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : ATTR_14 @ 0XFD480038

- - For an endpoint, specifies mask/settings for Base Address Register (BAR) 3 if BAR2 is a 32-bit BAR, or the upper bits of \'7b - AR3,BAR2\'7d if BAR2 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR2 descri - tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: FFFF_0000 = IO Limit/Bas - Registers not implemented FFFF_F0F0 = IO Limit/Base Registers use 16-bit decode FFFF_F1F1 = IO Limit/Base Registers use 32-b - t decode For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of BAR2) [0] = Mem Space Indicator (s - t to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; - if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits - f \'7bBAR4,BAR3\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writabl - bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0xFFFF - PSU_PCIE_ATTRIB_ATTR_14_ATTR_BAR3 0xFFFF - - ATTR_14 - (OFFSET, MASK, VALUE) (0XFD480038, 0x0000FFFFU ,0x0000FFFFU) - RegMask = (PCIE_ATTRIB_ATTR_14_ATTR_BAR3_MASK | 0 ); - - RegVal = ((0x0000FFFFU << PCIE_ATTRIB_ATTR_14_ATTR_BAR3_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_14_OFFSET ,0x0000FFFFU ,0x0000FFFFU); - /*############################################################################################################################ */ - - /*Register : ATTR_15 @ 0XFD48003C

- - For an endpoint, specifies mask/settings for Base Address Register (BAR) 4 if BAR3 is a 32-bit BAR, or the upper bits of \'7b - AR4,BAR3\'7d if BAR3 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR3 descri - tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to FFF0_FFF0. For an endpoin - , bits are defined as follows: Memory Space BAR (not upper bits of BAR3) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi - ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe - most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR5,BAR4\'7d to - . IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper - ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0x0004; RP=0xFFF0 - PSU_PCIE_ATTRIB_ATTR_15_ATTR_BAR4 0xFFF0 - - ATTR_15 - (OFFSET, MASK, VALUE) (0XFD48003C, 0x0000FFFFU ,0x0000FFF0U) - RegMask = (PCIE_ATTRIB_ATTR_15_ATTR_BAR4_MASK | 0 ); - - RegVal = ((0x0000FFF0U << PCIE_ATTRIB_ATTR_15_ATTR_BAR4_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_15_OFFSET ,0x0000FFFFU ,0x0000FFF0U); - /*############################################################################################################################ */ - - /*Register : ATTR_16 @ 0XFD480040

- - For an endpoint, specifies mask/settings for Base Address Register (BAR) 4 if BAR3 is a 32-bit BAR, or the upper bits of \'7b - AR4,BAR3\'7d if BAR3 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR3 descri - tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to FFF0_FFF0. For an endpoin - , bits are defined as follows: Memory Space BAR (not upper bits of BAR3) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi - ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe - most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR5,BAR4\'7d to - . IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper - ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFF0; RP=0xFFF0 - PSU_PCIE_ATTRIB_ATTR_16_ATTR_BAR4 0xFFF0 - - ATTR_16 - (OFFSET, MASK, VALUE) (0XFD480040, 0x0000FFFFU ,0x0000FFF0U) - RegMask = (PCIE_ATTRIB_ATTR_16_ATTR_BAR4_MASK | 0 ); - - RegVal = ((0x0000FFF0U << PCIE_ATTRIB_ATTR_16_ATTR_BAR4_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_16_OFFSET ,0x0000FFFFU ,0x0000FFF0U); - /*############################################################################################################################ */ - - /*Register : ATTR_17 @ 0XFD480044

- - For an endpoint, specifies mask/settings for Base Address Register (BAR) 5 if BAR4 is a 32-bit BAR, or the upper bits of \'7b - AR5,BAR4\'7d if BAR4 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR4 descri - tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: 0000_0000 = Prefetchable - Memory Limit/Base Registers not implemented FFF0_FFF0 = 32-bit Prefetchable Memory Limit/Base implemented FFF1_FFF1 = 64-bit - refetchable Memory Limit/Base implemented For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of B - R4) [0] = Mem Space Indicator (set to 0) [2:1] = Type field (00 for 32-bit; BAR5 cannot be lower part of a 64-bit BAR) [3] = - refetchable (0 or 1) [31:4] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=memory aperture size in - ytes. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set u - permost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0xFFF1 - PSU_PCIE_ATTRIB_ATTR_17_ATTR_BAR5 0xFFF1 - - ATTR_17 - (OFFSET, MASK, VALUE) (0XFD480044, 0x0000FFFFU ,0x0000FFF1U) - RegMask = (PCIE_ATTRIB_ATTR_17_ATTR_BAR5_MASK | 0 ); - - RegVal = ((0x0000FFF1U << PCIE_ATTRIB_ATTR_17_ATTR_BAR5_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_17_OFFSET ,0x0000FFFFU ,0x0000FFF1U); - /*############################################################################################################################ */ - - /*Register : ATTR_18 @ 0XFD480048

- - For an endpoint, specifies mask/settings for Base Address Register (BAR) 5 if BAR4 is a 32-bit BAR, or the upper bits of \'7b - AR5,BAR4\'7d if BAR4 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR4 descri - tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: 0000_0000 = Prefetchable - Memory Limit/Base Registers not implemented FFF0_FFF0 = 32-bit Prefetchable Memory Limit/Base implemented FFF1_FFF1 = 64-bit - refetchable Memory Limit/Base implemented For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of B - R4) [0] = Mem Space Indicator (set to 0) [2:1] = Type field (00 for 32-bit; BAR5 cannot be lower part of a 64-bit BAR) [3] = - refetchable (0 or 1) [31:4] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=memory aperture size in - ytes. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set u - permost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0xFFF1 - PSU_PCIE_ATTRIB_ATTR_18_ATTR_BAR5 0xFFF1 - - ATTR_18 - (OFFSET, MASK, VALUE) (0XFD480048, 0x0000FFFFU ,0x0000FFF1U) - RegMask = (PCIE_ATTRIB_ATTR_18_ATTR_BAR5_MASK | 0 ); - - RegVal = ((0x0000FFF1U << PCIE_ATTRIB_ATTR_18_ATTR_BAR5_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_18_OFFSET ,0x0000FFFFU ,0x0000FFF1U); - /*############################################################################################################################ */ - - /*Register : ATTR_27 @ 0XFD48006C

- - Specifies maximum payload supported. Valid settings are: 0- 128 bytes, 1- 256 bytes, 2- 512 bytes, 3- 1024 bytes. Transferred - to the Device Capabilities register. The values: 4-2048 bytes, 5- 4096 bytes are not supported; EP=0x0001; RP=0x0001 - PSU_PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED 1 - - Endpoint L1 Acceptable Latency. Records the latency that the endpoint can withstand on transitions from L1 state to L0 (if L1 - state supported). Valid settings are: 0h less than 1us, 1h 1 to 2us, 2h 2 to 4us, 3h 4 to 8us, 4h 8 to 16us, 5h 16 to 32us, 6 - 32 to 64us, 7h more than 64us. For Endpoints only. Must be 0h for other devices.; EP=0x0007; RP=0x0000 - PSU_PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY 0x0 - - ATTR_27 - (OFFSET, MASK, VALUE) (0XFD48006C, 0x00000738U ,0x00000100U) - RegMask = (PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_MASK | PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_MASK | 0 ); - - RegVal = ((0x00000001U << PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_SHIFT - | 0x00000000U << PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_27_OFFSET ,0x00000738U ,0x00000100U); - /*############################################################################################################################ */ - - /*Register : ATTR_50 @ 0XFD4800C8

- - Identifies the type of device/port as follows: 0000b PCI Express Endpoint device, 0001b Legacy PCI Express Endpoint device, 0 - 00b Root Port of PCI Express Root Complex, 0101b Upstream Port of PCI Express Switch, 0110b Downstream Port of PCI Express Sw - tch, 0111b PCIE Express to PCI/PCI-X Bridge, 1000b PCI/PCI-X to PCI Express Bridge. Transferred to PCI Express Capabilities r - gister. Must be consistent with IS_SWITCH and UPSTREAM_FACING settings.; EP=0x0000; RP=0x0004 - PSU_PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE 4 - - PCIe Capability's Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capab - lity.; EP=0x009C; RP=0x0000 - PSU_PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR 0 - - ATTR_50 - (OFFSET, MASK, VALUE) (0XFD4800C8, 0x0000FFF0U ,0x00000040U) - RegMask = (PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_MASK | PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_MASK | 0 ); - - RegVal = ((0x00000004U << PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_SHIFT - | 0x00000000U << PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_50_OFFSET ,0x0000FFF0U ,0x00000040U); - /*############################################################################################################################ */ - - /*Register : ATTR_105 @ 0XFD4801A4

- - Number of credits that should be advertised for Completion data received on Virtual Channel 0. The bytes advertised must be l - ss than or equal to the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0172; RP=0x00CD - PSU_PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD 0xCD - - ATTR_105 - (OFFSET, MASK, VALUE) (0XFD4801A4, 0x000007FFU ,0x000000CDU) - RegMask = (PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_MASK | 0 ); - - RegVal = ((0x000000CDU << PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_105_OFFSET ,0x000007FFU ,0x000000CDU); - /*############################################################################################################################ */ - - /*Register : ATTR_106 @ 0XFD4801A8

- - Number of credits that should be advertised for Completion headers received on Virtual Channel 0. The sum of the posted, non - osted, and completion header credits must be <= 80; EP=0x0048; RP=0x0024 - PSU_PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH 0x24 - - Number of credits that should be advertised for Non-Posted headers received on Virtual Channel 0. The number of non posted da - a credits advertised by the block is equal to the number of non posted header credits. The sum of the posted, non posted, and - completion header credits must be <= 80; EP=0x0004; RP=0x000C - PSU_PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH 0xC - - ATTR_106 - (OFFSET, MASK, VALUE) (0XFD4801A8, 0x00003FFFU ,0x00000624U) - RegMask = (PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_MASK | PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_MASK | 0 ); - - RegVal = ((0x00000024U << PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_SHIFT - | 0x0000000CU << PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_106_OFFSET ,0x00003FFFU ,0x00000624U); - /*############################################################################################################################ */ - - /*Register : ATTR_107 @ 0XFD4801AC

- - Number of credits that should be advertised for Non-Posted data received on Virtual Channel 0. The number of non posted data - redits advertised by the block is equal to two times the number of non posted header credits if atomic operations are support - d or is equal to the number of non posted header credits if atomic operations are not supported. The bytes advertised must be - less than or equal to the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0008; RP=0x0018 - PSU_PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD 0x18 - - ATTR_107 - (OFFSET, MASK, VALUE) (0XFD4801AC, 0x000007FFU ,0x00000018U) - RegMask = (PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_MASK | 0 ); - - RegVal = ((0x00000018U << PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_107_OFFSET ,0x000007FFU ,0x00000018U); - /*############################################################################################################################ */ - - /*Register : ATTR_108 @ 0XFD4801B0

- - Number of credits that should be advertised for Posted data received on Virtual Channel 0. The bytes advertised must be less - han or equal to the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0020; RP=0x00B5 - PSU_PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD 0xB5 - - ATTR_108 - (OFFSET, MASK, VALUE) (0XFD4801B0, 0x000007FFU ,0x000000B5U) - RegMask = (PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_MASK | 0 ); - - RegVal = ((0x000000B5U << PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_108_OFFSET ,0x000007FFU ,0x000000B5U); - /*############################################################################################################################ */ - - /*Register : ATTR_109 @ 0XFD4801B4

- - Not currently in use. Invert ECRC generated by block when trn_tecrc_gen_n and trn_terrfwd_n are asserted.; EP=0x0000; RP=0x00 - 0 - PSU_PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV 0x0 - - Enables td bit clear and ECRC trim on received TLP's FALSE == don't trim TRUE == trim.; EP=0x0001; RP=0x0001 - PSU_PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM 0x1 - - Enables ECRC check on received TLP's 0 == don't check 1 == always check 3 == check if enabled by ECRC check enable bit of AER - cap structure; EP=0x0003; RP=0x0003 - PSU_PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK 0x3 - - Index of last packet buffer used by TX TLM (i.e. number of buffers - 1). Calculated from max payload size supported and the n - mber of brams configured for transmit; EP=0x001C; RP=0x001C - PSU_PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET 0x1c - - Number of credits that should be advertised for Posted headers received on Virtual Channel 0. The sum of the posted, non post - d, and completion header credits must be <= 80; EP=0x0004; RP=0x0020 - PSU_PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH 0x20 - - ATTR_109 - (OFFSET, MASK, VALUE) (0XFD4801B4, 0x0000FFFFU ,0x00007E20U) - RegMask = (PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_MASK | PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_MASK | PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_MASK | PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_MASK | PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_MASK | 0 ); - - RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_SHIFT - | 0x00000001U << PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_SHIFT - | 0x00000003U << PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_SHIFT - | 0x0000001CU << PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_SHIFT - | 0x00000020U << PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_109_OFFSET ,0x0000FFFFU ,0x00007E20U); - /*############################################################################################################################ */ - - /*Register : ATTR_34 @ 0XFD480088

- - Specifies values to be transferred to Header Type register. Bit 7 should be set to '0' indicating single-function device. Bit - 0 identifies header as Type 0 or Type 1, with '0' indicating a Type 0 header.; EP=0x0000; RP=0x0001 - PSU_PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE 0x1 - - ATTR_34 - (OFFSET, MASK, VALUE) (0XFD480088, 0x000000FFU ,0x00000001U) - RegMask = (PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_MASK | 0 ); - - RegVal = ((0x00000001U << PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_34_OFFSET ,0x000000FFU ,0x00000001U); - /*############################################################################################################################ */ - - /*Register : ATTR_53 @ 0XFD4800D4

- - PM Capability's Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capabil - ty.; EP=0x0048; RP=0x0060 - PSU_PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR 0x60 - - ATTR_53 - (OFFSET, MASK, VALUE) (0XFD4800D4, 0x000000FFU ,0x00000060U) - RegMask = (PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_MASK | 0 ); - - RegVal = ((0x00000060U << PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_53_OFFSET ,0x000000FFU ,0x00000060U); - /*############################################################################################################################ */ - - /*Register : ATTR_41 @ 0XFD4800A4

- - MSI Per-Vector Masking Capable. The value is transferred to the MSI Control Register[8]. When set, adds Mask and Pending Dwor - to Cap structure; EP=0x0000; RP=0x0000 - PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE 0x0 - - Indicates that the MSI structures exists. If this is FALSE, then the MSI structure cannot be accessed via either the link or - he management port.; EP=0x0001; RP=0x0000 - PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON 0 - - MSI Capability's Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capabi - ity.; EP=0x0060; RP=0x0000 - PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR 0x0 - - Indicates that the MSI structures exists. If this is FALSE, then the MSI structure cannot be accessed via either the link or - he management port.; EP=0x0001; RP=0x0000 - PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON 0 - - ATTR_41 - (OFFSET, MASK, VALUE) (0XFD4800A4, 0x000003FFU ,0x00000000U) - RegMask = (PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_MASK | PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_MASK | PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_MASK | PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_MASK | 0 ); - - RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_SHIFT - | 0x00000000U << PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_SHIFT - | 0x00000000U << PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_SHIFT - | 0x00000000U << PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_41_OFFSET ,0x000003FFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : ATTR_97 @ 0XFD480184

- - Maximum Link Width. Valid settings are: 000001b x1, 000010b x2, 000100b x4, 001000b x8.; EP=0x0004; RP=0x0004 - PSU_PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH 0x1 - - Used by LTSSM to set Maximum Link Width. Valid settings are: 000001b [x1], 000010b [x2], 000100b [x4], 001000b [x8].; EP=0x00 - 4; RP=0x0004 - PSU_PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH 0x1 - - ATTR_97 - (OFFSET, MASK, VALUE) (0XFD480184, 0x00000FFFU ,0x00000041U) - RegMask = (PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_MASK | PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_MASK | 0 ); - - RegVal = ((0x00000001U << PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_SHIFT - | 0x00000001U << PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_97_OFFSET ,0x00000FFFU ,0x00000041U); - /*############################################################################################################################ */ - - /*Register : ATTR_100 @ 0XFD480190

- - TRUE specifies upstream-facing port. FALSE specifies downstream-facing port.; EP=0x0001; RP=0x0000 - PSU_PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING 0x0 - - ATTR_100 - (OFFSET, MASK, VALUE) (0XFD480190, 0x00000040U ,0x00000000U) - RegMask = (PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_MASK | 0 ); - - RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_100_OFFSET ,0x00000040U ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : ATTR_101 @ 0XFD480194

- - Enable the routing of message TLPs to the user through the TRN RX interface. A bit value of 1 enables routing of the message - LP to the user. Messages are always decoded by the message decoder. Bit 0 - ERR COR, Bit 1 - ERR NONFATAL, Bit 2 - ERR FATAL, - Bit 3 - INTA Bit 4 - INTB, Bit 5 - INTC, Bit 6 - INTD, Bit 7 PM_PME, Bit 8 - PME_TO_ACK, Bit 9 - unlock, Bit 10 PME_Turn_Off; - EP=0x0000; RP=0x07FF - PSU_PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE 0x7FF - - Disable BAR filtering. Does not change the behavior of the bar hit outputs; EP=0x0000; RP=0x0001 - PSU_PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING 0x1 - - ATTR_101 - (OFFSET, MASK, VALUE) (0XFD480194, 0x0000FFE2U ,0x0000FFE2U) - RegMask = (PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_MASK | PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_MASK | 0 ); - - RegVal = ((0x000007FFU << PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_SHIFT - | 0x00000001U << PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_101_OFFSET ,0x0000FFE2U ,0x0000FFE2U); - /*############################################################################################################################ */ - - /*Register : ATTR_37 @ 0XFD480094

- - Link Bandwidth notification capability. Indicates support for the link bandwidth notification status and interrupt mechanism. - Required for Root.; EP=0x0000; RP=0x0001 - PSU_PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP 0x1 - - Sets the ASPM Optionality Compliance bit, to comply with the 2.1 ASPM Optionality ECN. Transferred to the Link Capabilities r - gister.; EP=0x0001; RP=0x0001 - PSU_PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY 0x1 - - ATTR_37 - (OFFSET, MASK, VALUE) (0XFD480094, 0x00004200U ,0x00004200U) - RegMask = (PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_MASK | PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_MASK | 0 ); - - RegVal = ((0x00000001U << PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_SHIFT - | 0x00000001U << PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_37_OFFSET ,0x00004200U ,0x00004200U); - /*############################################################################################################################ */ - - /*Register : ATTR_93 @ 0XFD480174

- - Enables the Replay Timer to use the user-defined LL_REPLAY_TIMEOUT value (or combined with the built-in value, depending on L - _REPLAY_TIMEOUT_FUNC). If FALSE, the built-in value is used.; EP=0x0000; RP=0x0000 - PSU_PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN 0x1 - - Sets a user-defined timeout for the Replay Timer to force cause the retransmission of unacknowledged TLPs; refer to LL_REPLAY - TIMEOUT_EN and LL_REPLAY_TIMEOUT_FUNC to see how this value is used. The unit for this attribute is in symbol times, which is - 4ns at GEN1 speeds and 2ns at GEN2.; EP=0x0000; RP=0x0000 - PSU_PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT 0x1000 - - ATTR_93 - (OFFSET, MASK, VALUE) (0XFD480174, 0x0000FFFFU ,0x00009000U) - RegMask = (PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_MASK | PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_MASK | 0 ); - - RegVal = ((0x00000001U << PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_SHIFT - | 0x00001000U << PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_93_OFFSET ,0x0000FFFFU ,0x00009000U); - /*############################################################################################################################ */ - - /*Register : ID @ 0XFD480200

- - Device ID for the the PCIe Cap Structure Device ID field - PSU_PCIE_ATTRIB_ID_CFG_DEV_ID 0xd021 - - Vendor ID for the PCIe Cap Structure Vendor ID field - PSU_PCIE_ATTRIB_ID_CFG_VEND_ID 0x10ee - - ID - (OFFSET, MASK, VALUE) (0XFD480200, 0xFFFFFFFFU ,0x10EED021U) - RegMask = (PCIE_ATTRIB_ID_CFG_DEV_ID_MASK | PCIE_ATTRIB_ID_CFG_VEND_ID_MASK | 0 ); - - RegVal = ((0x0000D021U << PCIE_ATTRIB_ID_CFG_DEV_ID_SHIFT - | 0x000010EEU << PCIE_ATTRIB_ID_CFG_VEND_ID_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ID_OFFSET ,0xFFFFFFFFU ,0x10EED021U); - /*############################################################################################################################ */ - - /*Register : SUBSYS_ID @ 0XFD480204

- - Subsystem ID for the the PCIe Cap Structure Subsystem ID field - PSU_PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID 0x7 - - Subsystem Vendor ID for the PCIe Cap Structure Subsystem Vendor ID field - PSU_PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID 0x10ee - - SUBSYS_ID - (OFFSET, MASK, VALUE) (0XFD480204, 0xFFFFFFFFU ,0x10EE0007U) - RegMask = (PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_MASK | PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_MASK | 0 ); - - RegVal = ((0x00000007U << PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_SHIFT - | 0x000010EEU << PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_SUBSYS_ID_OFFSET ,0xFFFFFFFFU ,0x10EE0007U); - /*############################################################################################################################ */ - - /*Register : REV_ID @ 0XFD480208

- - Revision ID for the the PCIe Cap Structure - PSU_PCIE_ATTRIB_REV_ID_CFG_REV_ID 0x0 - - REV_ID - (OFFSET, MASK, VALUE) (0XFD480208, 0x000000FFU ,0x00000000U) - RegMask = (PCIE_ATTRIB_REV_ID_CFG_REV_ID_MASK | 0 ); - - RegVal = ((0x00000000U << PCIE_ATTRIB_REV_ID_CFG_REV_ID_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_REV_ID_OFFSET ,0x000000FFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : ATTR_24 @ 0XFD480060

- - Code identifying basic function, subclass and applicable programming interface. Transferred to the Class Code register.; EP=0 - 8000; RP=0x8000 - PSU_PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE 0x400 - - ATTR_24 - (OFFSET, MASK, VALUE) (0XFD480060, 0x0000FFFFU ,0x00000400U) - RegMask = (PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_MASK | 0 ); - - RegVal = ((0x00000400U << PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_24_OFFSET ,0x0000FFFFU ,0x00000400U); - /*############################################################################################################################ */ - - /*Register : ATTR_25 @ 0XFD480064

- - Code identifying basic function, subclass and applicable programming interface. Transferred to the Class Code register.; EP=0 - 0005; RP=0x0006 - PSU_PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE 0x6 - - INTX Interrupt Generation Capable. If FALSE, this will cause Command[10] to be hardwired to 0.; EP=0x0001; RP=0x0001 - PSU_PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED 0 - - ATTR_25 - (OFFSET, MASK, VALUE) (0XFD480064, 0x000001FFU ,0x00000006U) - RegMask = (PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_MASK | PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_MASK | 0 ); - - RegVal = ((0x00000006U << PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_SHIFT - | 0x00000000U << PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_25_OFFSET ,0x000001FFU ,0x00000006U); - /*############################################################################################################################ */ - - /*Register : ATTR_4 @ 0XFD480010

- - Indicates that the AER structures exists. If this is FALSE, then the AER structure cannot be accessed via either the link or - he management port, and AER will be considered to not be present for error management tasks (such as what types of error mess - ges are sent if an error is detected).; EP=0x0001; RP=0x0001 - PSU_PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON 0 - - Indicates that the AER structures exists. If this is FALSE, then the AER structure cannot be accessed via either the link or - he management port, and AER will be considered to not be present for error management tasks (such as what types of error mess - ges are sent if an error is detected).; EP=0x0001; RP=0x0001 - PSU_PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON 0 - - ATTR_4 - (OFFSET, MASK, VALUE) (0XFD480010, 0x00001000U ,0x00000000U) - RegMask = (PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_MASK | PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_MASK | 0 ); - - RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_SHIFT - | 0x00000000U << PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_4_OFFSET ,0x00001000U ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : ATTR_89 @ 0XFD480164

- - VSEC's Next Capability Offset pointer to the next item in the capabilities list, or 000h if this is the final capability.; EP - 0x0140; RP=0x0140 - PSU_PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR 0 - - ATTR_89 - (OFFSET, MASK, VALUE) (0XFD480164, 0x00001FFEU ,0x00000000U) - RegMask = (PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_MASK | 0 ); - - RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_89_OFFSET ,0x00001FFEU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : ATTR_79 @ 0XFD48013C

- - CRS SW Visibility. Indicates RC can return CRS to SW. Transferred to the Root Capabilities register.; EP=0x0000; RP=0x0000 - PSU_PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY 1 - - ATTR_79 - (OFFSET, MASK, VALUE) (0XFD48013C, 0x00000020U ,0x00000020U) - RegMask = (PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_MASK | 0 ); - - RegVal = ((0x00000001U << PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_79_OFFSET ,0x00000020U ,0x00000020U); - /*############################################################################################################################ */ - - /*Register : ATTR_43 @ 0XFD4800AC

- - Indicates that the MSIX structures exists. If this is FALSE, then the MSIX structure cannot be accessed via either the link o - the management port.; EP=0x0001; RP=0x0000 - PSU_PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON 0 - - ATTR_43 - (OFFSET, MASK, VALUE) (0XFD4800AC, 0x00000100U ,0x00000000U) - RegMask = (PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_MASK | 0 ); - - RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_43_OFFSET ,0x00000100U ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : ATTR_48 @ 0XFD4800C0

- - MSI-X Table Size. This value is transferred to the MSI-X Message Control[10:0] field. Set to 0 if MSI-X is not enabled. Note - hat the core does not implement the table; that must be implemented in user logic.; EP=0x0003; RP=0x0000 - PSU_PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE 0 - - ATTR_48 - (OFFSET, MASK, VALUE) (0XFD4800C0, 0x000007FFU ,0x00000000U) - RegMask = (PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_MASK | 0 ); - - RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_48_OFFSET ,0x000007FFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : ATTR_46 @ 0XFD4800B8

- - MSI-X Table Offset. This value is transferred to the MSI-X Table Offset field. Set to 0 if MSI-X is not enabled.; EP=0x0001; - P=0x0000 - PSU_PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET 0 - - ATTR_46 - (OFFSET, MASK, VALUE) (0XFD4800B8, 0x0000FFFFU ,0x00000000U) - RegMask = (PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_MASK | 0 ); - - RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_46_OFFSET ,0x0000FFFFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : ATTR_47 @ 0XFD4800BC

- - MSI-X Table Offset. This value is transferred to the MSI-X Table Offset field. Set to 0 if MSI-X is not enabled.; EP=0x0000; - P=0x0000 - PSU_PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET 0 - - ATTR_47 - (OFFSET, MASK, VALUE) (0XFD4800BC, 0x00001FFFU ,0x00000000U) - RegMask = (PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_MASK | 0 ); - - RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_47_OFFSET ,0x00001FFFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : ATTR_44 @ 0XFD4800B0

- - MSI-X Pending Bit Array Offset This value is transferred to the MSI-X PBA Offset field. Set to 0 if MSI-X is not enabled.; EP - 0x0001; RP=0x0000 - PSU_PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET 0 - - ATTR_44 - (OFFSET, MASK, VALUE) (0XFD4800B0, 0x0000FFFFU ,0x00000000U) - RegMask = (PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_MASK | 0 ); - - RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_44_OFFSET ,0x0000FFFFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : ATTR_45 @ 0XFD4800B4

- - MSI-X Pending Bit Array Offset This value is transferred to the MSI-X PBA Offset field. Set to 0 if MSI-X is not enabled.; EP - 0x1000; RP=0x0000 - PSU_PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET 0 - - ATTR_45 - (OFFSET, MASK, VALUE) (0XFD4800B4, 0x0000FFF8U ,0x00000000U) - RegMask = (PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_MASK | 0 ); - - RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_45_OFFSET ,0x0000FFF8U ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : CB @ 0XFD48031C

- - DT837748 Enable - PSU_PCIE_ATTRIB_CB_CB1 0x0 - - ECO Register 1 - (OFFSET, MASK, VALUE) (0XFD48031C, 0x00000002U ,0x00000000U) - RegMask = (PCIE_ATTRIB_CB_CB1_MASK | 0 ); - - RegVal = ((0x00000000U << PCIE_ATTRIB_CB_CB1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_CB_OFFSET ,0x00000002U ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : ATTR_35 @ 0XFD48008C

- - Active State PM Support. Indicates the level of active state power management supported by the selected PCI Express Link, enc - ded as follows: 0 Reserved, 1 L0s entry supported, 2 Reserved, 3 L0s and L1 entry supported.; EP=0x0001; RP=0x0001 - PSU_PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT 0x0 - - ATTR_35 - (OFFSET, MASK, VALUE) (0XFD48008C, 0x00003000U ,0x00000000U) - RegMask = (PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_MASK | 0 ); - - RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_35_OFFSET ,0x00003000U ,0x00000000U); - /*############################################################################################################################ */ - - // : PUTTING PCIE CONTROL IN RESET - /*Register : RST_FPD_TOP @ 0XFD1A0100

- - PCIE control block level reset - PSU_CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET 0X0 - - FPD Block level software controlled reset - (OFFSET, MASK, VALUE) (0XFD1A0100, 0x00020000U ,0x00000000U) - RegMask = (CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK | 0 ); - - RegVal = ((0x00000000U << CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_RST_FPD_TOP_OFFSET ,0x00020000U ,0x00000000U); - /*############################################################################################################################ */ - - // : CHECK PLL LOCK FOR LANE0 - /*Register : L0_PLL_STATUS_READ_1 @ 0XFD4023E4

- - Status Read value of PLL Lock - PSU_SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1 - (OFFSET, MASK, VALUE) (0XFD4023E4, 0x00000010U ,0x00000010U) */ - mask_poll(SERDES_L0_PLL_STATUS_READ_1_OFFSET,0x00000010U); - - /*############################################################################################################################ */ - - // : CHECK PLL LOCK FOR LANE1 - /*Register : L1_PLL_STATUS_READ_1 @ 0XFD4063E4

- - Status Read value of PLL Lock - PSU_SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1 - (OFFSET, MASK, VALUE) (0XFD4063E4, 0x00000010U ,0x00000010U) */ - mask_poll(SERDES_L1_PLL_STATUS_READ_1_OFFSET,0x00000010U); - - /*############################################################################################################################ */ - - // : CHECK PLL LOCK FOR LANE2 - /*Register : L2_PLL_STATUS_READ_1 @ 0XFD40A3E4

- - Status Read value of PLL Lock - PSU_SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1 - (OFFSET, MASK, VALUE) (0XFD40A3E4, 0x00000010U ,0x00000010U) */ - mask_poll(SERDES_L2_PLL_STATUS_READ_1_OFFSET,0x00000010U); - - /*############################################################################################################################ */ - - // : CHECK PLL LOCK FOR LANE3 - /*Register : L3_PLL_STATUS_READ_1 @ 0XFD40E3E4

- - Status Read value of PLL Lock - PSU_SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1 - (OFFSET, MASK, VALUE) (0XFD40E3E4, 0x00000010U ,0x00000010U) */ - mask_poll(SERDES_L3_PLL_STATUS_READ_1_OFFSET,0x00000010U); - - /*############################################################################################################################ */ - - // : SATA AHCI VENDOR SETTING - /*Register : PP2C @ 0XFD0C00AC

- - CIBGMN: COMINIT Burst Gap Minimum. - PSU_SATA_AHCI_VENDOR_PP2C_CIBGMN 0x18 - - CIBGMX: COMINIT Burst Gap Maximum. - PSU_SATA_AHCI_VENDOR_PP2C_CIBGMX 0x40 - - CIBGN: COMINIT Burst Gap Nominal. - PSU_SATA_AHCI_VENDOR_PP2C_CIBGN 0x18 - - CINMP: COMINIT Negate Minimum Period. - PSU_SATA_AHCI_VENDOR_PP2C_CINMP 0x28 - - PP2C - Port Phy2Cfg Register. This register controls the configuration of the Phy Control OOB timing for the COMINIT paramete - s for either Port 0 or Port 1. The Port configured is controlled by the value programmed into the Port Config Register. - (OFFSET, MASK, VALUE) (0XFD0C00AC, 0xFFFFFFFFU ,0x28184018U) - RegMask = (SATA_AHCI_VENDOR_PP2C_CIBGMN_MASK | SATA_AHCI_VENDOR_PP2C_CIBGMX_MASK | SATA_AHCI_VENDOR_PP2C_CIBGN_MASK | SATA_AHCI_VENDOR_PP2C_CINMP_MASK | 0 ); - - RegVal = ((0x00000018U << SATA_AHCI_VENDOR_PP2C_CIBGMN_SHIFT - | 0x00000040U << SATA_AHCI_VENDOR_PP2C_CIBGMX_SHIFT - | 0x00000018U << SATA_AHCI_VENDOR_PP2C_CIBGN_SHIFT - | 0x00000028U << SATA_AHCI_VENDOR_PP2C_CINMP_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SATA_AHCI_VENDOR_PP2C_OFFSET ,0xFFFFFFFFU ,0x28184018U); - /*############################################################################################################################ */ - - /*Register : PP3C @ 0XFD0C00B0

- - CWBGMN: COMWAKE Burst Gap Minimum. - PSU_SATA_AHCI_VENDOR_PP3C_CWBGMN 0x06 - - CWBGMX: COMWAKE Burst Gap Maximum. - PSU_SATA_AHCI_VENDOR_PP3C_CWBGMX 0x14 - - CWBGN: COMWAKE Burst Gap Nominal. - PSU_SATA_AHCI_VENDOR_PP3C_CWBGN 0x08 - - CWNMP: COMWAKE Negate Minimum Period. - PSU_SATA_AHCI_VENDOR_PP3C_CWNMP 0x0E - - PP3C - Port Phy3CfgRegister. This register controls the configuration of the Phy Control OOB timing for the COMWAKE parameter - for either Port 0 or Port 1. The Port configured is controlled by the value programmed into the Port Config Register. - (OFFSET, MASK, VALUE) (0XFD0C00B0, 0xFFFFFFFFU ,0x0E081406U) - RegMask = (SATA_AHCI_VENDOR_PP3C_CWBGMN_MASK | SATA_AHCI_VENDOR_PP3C_CWBGMX_MASK | SATA_AHCI_VENDOR_PP3C_CWBGN_MASK | SATA_AHCI_VENDOR_PP3C_CWNMP_MASK | 0 ); - - RegVal = ((0x00000006U << SATA_AHCI_VENDOR_PP3C_CWBGMN_SHIFT - | 0x00000014U << SATA_AHCI_VENDOR_PP3C_CWBGMX_SHIFT - | 0x00000008U << SATA_AHCI_VENDOR_PP3C_CWBGN_SHIFT - | 0x0000000EU << SATA_AHCI_VENDOR_PP3C_CWNMP_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SATA_AHCI_VENDOR_PP3C_OFFSET ,0xFFFFFFFFU ,0x0E081406U); - /*############################################################################################################################ */ - - /*Register : PP4C @ 0XFD0C00B4

- - BMX: COM Burst Maximum. - PSU_SATA_AHCI_VENDOR_PP4C_BMX 0x13 - - BNM: COM Burst Nominal. - PSU_SATA_AHCI_VENDOR_PP4C_BNM 0x08 - - SFD: Signal Failure Detection, if the signal detection de-asserts for a time greater than this then the OOB detector will det - rmine this is a line idle and cause the PhyInit state machine to exit the Phy Ready State. A value of zero disables the Signa - Failure Detector. The value is based on the OOB Detector Clock typically (PMCLK Clock Period) * SFD giving a nominal time of - 500ns based on a 150MHz PMCLK. - PSU_SATA_AHCI_VENDOR_PP4C_SFD 0x4A - - PTST: Partial to Slumber timer value, specific delay the controller should apply while in partial before entering slumber. Th - value is bases on the system clock divided by 128, total delay = (Sys Clock Period) * PTST * 128 - PSU_SATA_AHCI_VENDOR_PP4C_PTST 0x06 - - PP4C - Port Phy4Cfg Register. This register controls the configuration of the Phy Control Burst timing for the COM parameters - for either Port 0 or Port 1. The Port configured is controlled by the value programmed into the Port Config Register. - (OFFSET, MASK, VALUE) (0XFD0C00B4, 0xFFFFFFFFU ,0x064A0813U) - RegMask = (SATA_AHCI_VENDOR_PP4C_BMX_MASK | SATA_AHCI_VENDOR_PP4C_BNM_MASK | SATA_AHCI_VENDOR_PP4C_SFD_MASK | SATA_AHCI_VENDOR_PP4C_PTST_MASK | 0 ); - - RegVal = ((0x00000013U << SATA_AHCI_VENDOR_PP4C_BMX_SHIFT - | 0x00000008U << SATA_AHCI_VENDOR_PP4C_BNM_SHIFT - | 0x0000004AU << SATA_AHCI_VENDOR_PP4C_SFD_SHIFT - | 0x00000006U << SATA_AHCI_VENDOR_PP4C_PTST_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SATA_AHCI_VENDOR_PP4C_OFFSET ,0xFFFFFFFFU ,0x064A0813U); - /*############################################################################################################################ */ - - /*Register : PP5C @ 0XFD0C00B8

- - RIT: Retry Interval Timer. The calculated value divided by two, the lower digit of precision is not needed. - PSU_SATA_AHCI_VENDOR_PP5C_RIT 0xC96A4 - - RCT: Rate Change Timer, a value based on the 54.2us for which a SATA device will transmit at a fixed rate ALIGNp after OOB ha - completed, for a fast SERDES it is suggested that this value be 54.2us / 4 - PSU_SATA_AHCI_VENDOR_PP5C_RCT 0x3FF - - PP5C - Port Phy5Cfg Register. This register controls the configuration of the Phy Control Retry Interval timing for either Po - t 0 or Port 1. The Port configured is controlled by the value programmed into the Port Config Register. - (OFFSET, MASK, VALUE) (0XFD0C00B8, 0xFFFFFFFFU ,0x3FFC96A4U) - RegMask = (SATA_AHCI_VENDOR_PP5C_RIT_MASK | SATA_AHCI_VENDOR_PP5C_RCT_MASK | 0 ); - - RegVal = ((0x000C96A4U << SATA_AHCI_VENDOR_PP5C_RIT_SHIFT - | 0x000003FFU << SATA_AHCI_VENDOR_PP5C_RCT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SATA_AHCI_VENDOR_PP5C_OFFSET ,0xFFFFFFFFU ,0x3FFC96A4U); - /*############################################################################################################################ */ - - - return 1; + * MPHY PLL Gear and bypass scrambler + * (OFFSET, MASK, VALUE) (0XFD40C0F4, 0x0000000BU ,0x0000000BU) + */ + PSU_Mask_Write(SERDES_L3_TX_DIG_TM_61_OFFSET, + 0x0000000BU, 0x0000000BU); +/*##################################################################### */ + + /* + * ENABLE CHICKEN BIT FOR PCIE AND USB + */ + /* + * Register : L0_TM_AUX_0 @ 0XFD4010CC + + * Spare- not used + * PSU_SERDES_L0_TM_AUX_0_BIT_2 1 + + * Spare registers + * (OFFSET, MASK, VALUE) (0XFD4010CC, 0x00000020U ,0x00000020U) + */ + PSU_Mask_Write(SERDES_L0_TM_AUX_0_OFFSET, 0x00000020U, 0x00000020U); +/*##################################################################### */ + + /* + * Register : L2_TM_AUX_0 @ 0XFD4090CC + + * Spare- not used + * PSU_SERDES_L2_TM_AUX_0_BIT_2 1 + + * Spare registers + * (OFFSET, MASK, VALUE) (0XFD4090CC, 0x00000020U ,0x00000020U) + */ + PSU_Mask_Write(SERDES_L2_TM_AUX_0_OFFSET, 0x00000020U, 0x00000020U); +/*##################################################################### */ + + /* + * ENABLING EYE SURF + */ + /* + * Register : L0_TM_DIG_8 @ 0XFD401074 + + * Enable Eye Surf + * PSU_SERDES_L0_TM_DIG_8_EYESURF_ENABLE 0x1 + + * Test modes for Elastic buffer and enabling Eye Surf + * (OFFSET, MASK, VALUE) (0XFD401074, 0x00000010U ,0x00000010U) + */ + PSU_Mask_Write(SERDES_L0_TM_DIG_8_OFFSET, 0x00000010U, 0x00000010U); +/*##################################################################### */ + + /* + * Register : L1_TM_DIG_8 @ 0XFD405074 + + * Enable Eye Surf + * PSU_SERDES_L1_TM_DIG_8_EYESURF_ENABLE 0x1 + + * Test modes for Elastic buffer and enabling Eye Surf + * (OFFSET, MASK, VALUE) (0XFD405074, 0x00000010U ,0x00000010U) + */ + PSU_Mask_Write(SERDES_L1_TM_DIG_8_OFFSET, 0x00000010U, 0x00000010U); +/*##################################################################### */ + + /* + * Register : L2_TM_DIG_8 @ 0XFD409074 + + * Enable Eye Surf + * PSU_SERDES_L2_TM_DIG_8_EYESURF_ENABLE 0x1 + + * Test modes for Elastic buffer and enabling Eye Surf + * (OFFSET, MASK, VALUE) (0XFD409074, 0x00000010U ,0x00000010U) + */ + PSU_Mask_Write(SERDES_L2_TM_DIG_8_OFFSET, 0x00000010U, 0x00000010U); +/*##################################################################### */ + + /* + * Register : L3_TM_DIG_8 @ 0XFD40D074 + + * Enable Eye Surf + * PSU_SERDES_L3_TM_DIG_8_EYESURF_ENABLE 0x1 + + * Test modes for Elastic buffer and enabling Eye Surf + * (OFFSET, MASK, VALUE) (0XFD40D074, 0x00000010U ,0x00000010U) + */ + PSU_Mask_Write(SERDES_L3_TM_DIG_8_OFFSET, 0x00000010U, 0x00000010U); +/*##################################################################### */ + + /* + * ILL SETTINGS FOR GAIN AND LOCK SETTINGS + */ + /* + * Register : L0_TM_MISC2 @ 0XFD40189C + + * ILL calib counts BYPASSED with calcode bits + * PSU_SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS 0x1 + + * sampler cal + * (OFFSET, MASK, VALUE) (0XFD40189C, 0x00000080U ,0x00000080U) + */ + PSU_Mask_Write(SERDES_L0_TM_MISC2_OFFSET, 0x00000080U, 0x00000080U); +/*##################################################################### */ + + /* + * Register : L0_TM_IQ_ILL1 @ 0XFD4018F8 + + * IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , + * USB3 : SS + * PSU_SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0 0x64 + + * iqpi cal code + * (OFFSET, MASK, VALUE) (0XFD4018F8, 0x000000FFU ,0x00000064U) + */ + PSU_Mask_Write(SERDES_L0_TM_IQ_ILL1_OFFSET, + 0x000000FFU, 0x00000064U); +/*##################################################################### */ + + /* + * Register : L0_TM_IQ_ILL2 @ 0XFD4018FC + + * IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 + * PSU_SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1 0x64 + + * iqpi cal code + * (OFFSET, MASK, VALUE) (0XFD4018FC, 0x000000FFU ,0x00000064U) + */ + PSU_Mask_Write(SERDES_L0_TM_IQ_ILL2_OFFSET, + 0x000000FFU, 0x00000064U); +/*##################################################################### */ + + /* + * Register : L0_TM_ILL12 @ 0XFD401990 + + * G1A pll ctr bypass value + * PSU_SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL 0x11 + + * ill pll counter values + * (OFFSET, MASK, VALUE) (0XFD401990, 0x000000FFU ,0x00000011U) + */ + PSU_Mask_Write(SERDES_L0_TM_ILL12_OFFSET, 0x000000FFU, 0x00000011U); +/*##################################################################### */ + + /* + * Register : L0_TM_E_ILL1 @ 0XFD401924 + + * E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , U + * SB3 : SS + * PSU_SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0 0x4 + + * epi cal code + * (OFFSET, MASK, VALUE) (0XFD401924, 0x000000FFU ,0x00000004U) + */ + PSU_Mask_Write(SERDES_L0_TM_E_ILL1_OFFSET, 0x000000FFU, 0x00000004U); +/*##################################################################### */ + + /* + * Register : L0_TM_E_ILL2 @ 0XFD401928 + + * E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 + * PSU_SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1 0xFE + + * epi cal code + * (OFFSET, MASK, VALUE) (0XFD401928, 0x000000FFU ,0x000000FEU) + */ + PSU_Mask_Write(SERDES_L0_TM_E_ILL2_OFFSET, 0x000000FFU, 0x000000FEU); +/*##################################################################### */ + + /* + * Register : L0_TM_IQ_ILL3 @ 0XFD401900 + + * IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 + * PSU_SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2 0x64 + + * iqpi cal code + * (OFFSET, MASK, VALUE) (0XFD401900, 0x000000FFU ,0x00000064U) + */ + PSU_Mask_Write(SERDES_L0_TM_IQ_ILL3_OFFSET, + 0x000000FFU, 0x00000064U); +/*##################################################################### */ + + /* + * Register : L0_TM_E_ILL3 @ 0XFD40192C + + * E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 + * PSU_SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2 0x0 + + * epi cal code + * (OFFSET, MASK, VALUE) (0XFD40192C, 0x000000FFU ,0x00000000U) + */ + PSU_Mask_Write(SERDES_L0_TM_E_ILL3_OFFSET, 0x000000FFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : L0_TM_ILL8 @ 0XFD401980 + + * ILL calibration code change wait time + * PSU_SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT 0xFF + + * ILL cal routine control + * (OFFSET, MASK, VALUE) (0XFD401980, 0x000000FFU ,0x000000FFU) + */ + PSU_Mask_Write(SERDES_L0_TM_ILL8_OFFSET, 0x000000FFU, 0x000000FFU); +/*##################################################################### */ + + /* + * Register : L0_TM_IQ_ILL8 @ 0XFD401914 + + * IQ ILL polytrim bypass value + * PSU_SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL 0xF7 + + * iqpi polytrim + * (OFFSET, MASK, VALUE) (0XFD401914, 0x000000FFU ,0x000000F7U) + */ + PSU_Mask_Write(SERDES_L0_TM_IQ_ILL8_OFFSET, + 0x000000FFU, 0x000000F7U); +/*##################################################################### */ + + /* + * Register : L0_TM_IQ_ILL9 @ 0XFD401918 + + * bypass IQ polytrim + * PSU_SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM 0x1 + + * enables for lf,constant gm trim and polytirm + * (OFFSET, MASK, VALUE) (0XFD401918, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L0_TM_IQ_ILL9_OFFSET, + 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : L0_TM_E_ILL8 @ 0XFD401940 + + * E ILL polytrim bypass value + * PSU_SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL 0xF7 + + * epi polytrim + * (OFFSET, MASK, VALUE) (0XFD401940, 0x000000FFU ,0x000000F7U) + */ + PSU_Mask_Write(SERDES_L0_TM_E_ILL8_OFFSET, 0x000000FFU, 0x000000F7U); +/*##################################################################### */ + + /* + * Register : L0_TM_E_ILL9 @ 0XFD401944 + + * bypass E polytrim + * PSU_SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM 0x1 + + * enables for lf,constant gm trim and polytirm + * (OFFSET, MASK, VALUE) (0XFD401944, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L0_TM_E_ILL9_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : L0_TM_ILL13 @ 0XFD401994 + + * ILL cal idle val refcnt + * PSU_SERDES_L0_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT 0x7 + + * ill cal idle value count + * (OFFSET, MASK, VALUE) (0XFD401994, 0x00000007U ,0x00000007U) + */ + PSU_Mask_Write(SERDES_L0_TM_ILL13_OFFSET, 0x00000007U, 0x00000007U); +/*##################################################################### */ + + /* + * Register : L1_TM_ILL13 @ 0XFD405994 + + * ILL cal idle val refcnt + * PSU_SERDES_L1_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT 0x7 + + * ill cal idle value count + * (OFFSET, MASK, VALUE) (0XFD405994, 0x00000007U ,0x00000007U) + */ + PSU_Mask_Write(SERDES_L1_TM_ILL13_OFFSET, 0x00000007U, 0x00000007U); +/*##################################################################### */ + + /* + * Register : L2_TM_MISC2 @ 0XFD40989C + + * ILL calib counts BYPASSED with calcode bits + * PSU_SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS 0x1 + + * sampler cal + * (OFFSET, MASK, VALUE) (0XFD40989C, 0x00000080U ,0x00000080U) + */ + PSU_Mask_Write(SERDES_L2_TM_MISC2_OFFSET, 0x00000080U, 0x00000080U); +/*##################################################################### */ + + /* + * Register : L2_TM_IQ_ILL1 @ 0XFD4098F8 + + * IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , + * USB3 : SS + * PSU_SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0 0x1A + + * iqpi cal code + * (OFFSET, MASK, VALUE) (0XFD4098F8, 0x000000FFU ,0x0000001AU) + */ + PSU_Mask_Write(SERDES_L2_TM_IQ_ILL1_OFFSET, + 0x000000FFU, 0x0000001AU); +/*##################################################################### */ + + /* + * Register : L2_TM_IQ_ILL2 @ 0XFD4098FC + + * IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 + * PSU_SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1 0x1A + + * iqpi cal code + * (OFFSET, MASK, VALUE) (0XFD4098FC, 0x000000FFU ,0x0000001AU) + */ + PSU_Mask_Write(SERDES_L2_TM_IQ_ILL2_OFFSET, + 0x000000FFU, 0x0000001AU); +/*##################################################################### */ + + /* + * Register : L2_TM_ILL12 @ 0XFD409990 + + * G1A pll ctr bypass value + * PSU_SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL 0x10 + + * ill pll counter values + * (OFFSET, MASK, VALUE) (0XFD409990, 0x000000FFU ,0x00000010U) + */ + PSU_Mask_Write(SERDES_L2_TM_ILL12_OFFSET, 0x000000FFU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : L2_TM_E_ILL1 @ 0XFD409924 + + * E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , U + * SB3 : SS + * PSU_SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0 0xFE + + * epi cal code + * (OFFSET, MASK, VALUE) (0XFD409924, 0x000000FFU ,0x000000FEU) + */ + PSU_Mask_Write(SERDES_L2_TM_E_ILL1_OFFSET, 0x000000FFU, 0x000000FEU); +/*##################################################################### */ + + /* + * Register : L2_TM_E_ILL2 @ 0XFD409928 + + * E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 + * PSU_SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1 0x0 + + * epi cal code + * (OFFSET, MASK, VALUE) (0XFD409928, 0x000000FFU ,0x00000000U) + */ + PSU_Mask_Write(SERDES_L2_TM_E_ILL2_OFFSET, 0x000000FFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : L2_TM_IQ_ILL3 @ 0XFD409900 + + * IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 + * PSU_SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2 0x1A + + * iqpi cal code + * (OFFSET, MASK, VALUE) (0XFD409900, 0x000000FFU ,0x0000001AU) + */ + PSU_Mask_Write(SERDES_L2_TM_IQ_ILL3_OFFSET, + 0x000000FFU, 0x0000001AU); +/*##################################################################### */ + + /* + * Register : L2_TM_E_ILL3 @ 0XFD40992C + + * E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 + * PSU_SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2 0x0 + + * epi cal code + * (OFFSET, MASK, VALUE) (0XFD40992C, 0x000000FFU ,0x00000000U) + */ + PSU_Mask_Write(SERDES_L2_TM_E_ILL3_OFFSET, 0x000000FFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : L2_TM_ILL8 @ 0XFD409980 + + * ILL calibration code change wait time + * PSU_SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT 0xFF + + * ILL cal routine control + * (OFFSET, MASK, VALUE) (0XFD409980, 0x000000FFU ,0x000000FFU) + */ + PSU_Mask_Write(SERDES_L2_TM_ILL8_OFFSET, 0x000000FFU, 0x000000FFU); +/*##################################################################### */ + + /* + * Register : L2_TM_IQ_ILL8 @ 0XFD409914 + + * IQ ILL polytrim bypass value + * PSU_SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL 0xF7 + + * iqpi polytrim + * (OFFSET, MASK, VALUE) (0XFD409914, 0x000000FFU ,0x000000F7U) + */ + PSU_Mask_Write(SERDES_L2_TM_IQ_ILL8_OFFSET, + 0x000000FFU, 0x000000F7U); +/*##################################################################### */ + + /* + * Register : L2_TM_IQ_ILL9 @ 0XFD409918 + + * bypass IQ polytrim + * PSU_SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM 0x1 + + * enables for lf,constant gm trim and polytirm + * (OFFSET, MASK, VALUE) (0XFD409918, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L2_TM_IQ_ILL9_OFFSET, + 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : L2_TM_E_ILL8 @ 0XFD409940 + + * E ILL polytrim bypass value + * PSU_SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL 0xF7 + + * epi polytrim + * (OFFSET, MASK, VALUE) (0XFD409940, 0x000000FFU ,0x000000F7U) + */ + PSU_Mask_Write(SERDES_L2_TM_E_ILL8_OFFSET, 0x000000FFU, 0x000000F7U); +/*##################################################################### */ + + /* + * Register : L2_TM_E_ILL9 @ 0XFD409944 + + * bypass E polytrim + * PSU_SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM 0x1 + + * enables for lf,constant gm trim and polytirm + * (OFFSET, MASK, VALUE) (0XFD409944, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L2_TM_E_ILL9_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : L2_TM_ILL13 @ 0XFD409994 + + * ILL cal idle val refcnt + * PSU_SERDES_L2_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT 0x7 + + * ill cal idle value count + * (OFFSET, MASK, VALUE) (0XFD409994, 0x00000007U ,0x00000007U) + */ + PSU_Mask_Write(SERDES_L2_TM_ILL13_OFFSET, 0x00000007U, 0x00000007U); +/*##################################################################### */ + + /* + * Register : L3_TM_MISC2 @ 0XFD40D89C + + * ILL calib counts BYPASSED with calcode bits + * PSU_SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS 0x1 + + * sampler cal + * (OFFSET, MASK, VALUE) (0XFD40D89C, 0x00000080U ,0x00000080U) + */ + PSU_Mask_Write(SERDES_L3_TM_MISC2_OFFSET, 0x00000080U, 0x00000080U); +/*##################################################################### */ + + /* + * Register : L3_TM_IQ_ILL1 @ 0XFD40D8F8 + + * IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , + * USB3 : SS + * PSU_SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0 0x7D + + * iqpi cal code + * (OFFSET, MASK, VALUE) (0XFD40D8F8, 0x000000FFU ,0x0000007DU) + */ + PSU_Mask_Write(SERDES_L3_TM_IQ_ILL1_OFFSET, + 0x000000FFU, 0x0000007DU); +/*##################################################################### */ + + /* + * Register : L3_TM_IQ_ILL2 @ 0XFD40D8FC + + * IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 + * PSU_SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1 0x7D + + * iqpi cal code + * (OFFSET, MASK, VALUE) (0XFD40D8FC, 0x000000FFU ,0x0000007DU) + */ + PSU_Mask_Write(SERDES_L3_TM_IQ_ILL2_OFFSET, + 0x000000FFU, 0x0000007DU); +/*##################################################################### */ + + /* + * Register : L3_TM_ILL12 @ 0XFD40D990 + + * G1A pll ctr bypass value + * PSU_SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL 0x1 + + * ill pll counter values + * (OFFSET, MASK, VALUE) (0XFD40D990, 0x000000FFU ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L3_TM_ILL12_OFFSET, 0x000000FFU, 0x00000001U); +/*##################################################################### */ + + /* + * Register : L3_TM_E_ILL1 @ 0XFD40D924 + + * E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , U + * SB3 : SS + * PSU_SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0 0x9C + + * epi cal code + * (OFFSET, MASK, VALUE) (0XFD40D924, 0x000000FFU ,0x0000009CU) + */ + PSU_Mask_Write(SERDES_L3_TM_E_ILL1_OFFSET, 0x000000FFU, 0x0000009CU); +/*##################################################################### */ + + /* + * Register : L3_TM_E_ILL2 @ 0XFD40D928 + + * E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 + * PSU_SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1 0x39 + + * epi cal code + * (OFFSET, MASK, VALUE) (0XFD40D928, 0x000000FFU ,0x00000039U) + */ + PSU_Mask_Write(SERDES_L3_TM_E_ILL2_OFFSET, 0x000000FFU, 0x00000039U); +/*##################################################################### */ + + /* + * Register : L3_TM_ILL11 @ 0XFD40D98C + + * G2A_PCIe1 PLL ctr bypass value + * PSU_SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL 0x2 + + * ill pll counter values + * (OFFSET, MASK, VALUE) (0XFD40D98C, 0x000000F0U ,0x00000020U) + */ + PSU_Mask_Write(SERDES_L3_TM_ILL11_OFFSET, 0x000000F0U, 0x00000020U); +/*##################################################################### */ + + /* + * Register : L3_TM_IQ_ILL3 @ 0XFD40D900 + + * IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 + * PSU_SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2 0x7D + + * iqpi cal code + * (OFFSET, MASK, VALUE) (0XFD40D900, 0x000000FFU ,0x0000007DU) + */ + PSU_Mask_Write(SERDES_L3_TM_IQ_ILL3_OFFSET, + 0x000000FFU, 0x0000007DU); +/*##################################################################### */ + + /* + * Register : L3_TM_E_ILL3 @ 0XFD40D92C + + * E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 + * PSU_SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2 0x64 + + * epi cal code + * (OFFSET, MASK, VALUE) (0XFD40D92C, 0x000000FFU ,0x00000064U) + */ + PSU_Mask_Write(SERDES_L3_TM_E_ILL3_OFFSET, 0x000000FFU, 0x00000064U); +/*##################################################################### */ + + /* + * Register : L3_TM_ILL8 @ 0XFD40D980 + + * ILL calibration code change wait time + * PSU_SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT 0xFF + + * ILL cal routine control + * (OFFSET, MASK, VALUE) (0XFD40D980, 0x000000FFU ,0x000000FFU) + */ + PSU_Mask_Write(SERDES_L3_TM_ILL8_OFFSET, 0x000000FFU, 0x000000FFU); +/*##################################################################### */ + + /* + * Register : L3_TM_IQ_ILL8 @ 0XFD40D914 + + * IQ ILL polytrim bypass value + * PSU_SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL 0xF7 + + * iqpi polytrim + * (OFFSET, MASK, VALUE) (0XFD40D914, 0x000000FFU ,0x000000F7U) + */ + PSU_Mask_Write(SERDES_L3_TM_IQ_ILL8_OFFSET, + 0x000000FFU, 0x000000F7U); +/*##################################################################### */ + + /* + * Register : L3_TM_IQ_ILL9 @ 0XFD40D918 + + * bypass IQ polytrim + * PSU_SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM 0x1 + + * enables for lf,constant gm trim and polytirm + * (OFFSET, MASK, VALUE) (0XFD40D918, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L3_TM_IQ_ILL9_OFFSET, + 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : L3_TM_E_ILL8 @ 0XFD40D940 + + * E ILL polytrim bypass value + * PSU_SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL 0xF7 + + * epi polytrim + * (OFFSET, MASK, VALUE) (0XFD40D940, 0x000000FFU ,0x000000F7U) + */ + PSU_Mask_Write(SERDES_L3_TM_E_ILL8_OFFSET, 0x000000FFU, 0x000000F7U); +/*##################################################################### */ + + /* + * Register : L3_TM_E_ILL9 @ 0XFD40D944 + + * bypass E polytrim + * PSU_SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM 0x1 + + * enables for lf,constant gm trim and polytirm + * (OFFSET, MASK, VALUE) (0XFD40D944, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L3_TM_E_ILL9_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : L3_TM_ILL13 @ 0XFD40D994 + + * ILL cal idle val refcnt + * PSU_SERDES_L3_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT 0x7 + + * ill cal idle value count + * (OFFSET, MASK, VALUE) (0XFD40D994, 0x00000007U ,0x00000007U) + */ + PSU_Mask_Write(SERDES_L3_TM_ILL13_OFFSET, 0x00000007U, 0x00000007U); +/*##################################################################### */ + + /* + * SYMBOL LOCK AND WAIT + */ + /* + * Register : L0_TM_DIG_10 @ 0XFD40107C + + * CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001 + * PSU_SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME 0x1 + + * test control for changing cdr lock wait time + * (OFFSET, MASK, VALUE) (0XFD40107C, 0x0000000FU ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L0_TM_DIG_10_OFFSET, 0x0000000FU, 0x00000001U); +/*##################################################################### */ + + /* + * Register : L1_TM_DIG_10 @ 0XFD40507C + + * CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001 + * PSU_SERDES_L1_TM_DIG_10_CDR_BIT_LOCK_TIME 0x1 + + * test control for changing cdr lock wait time + * (OFFSET, MASK, VALUE) (0XFD40507C, 0x0000000FU ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L1_TM_DIG_10_OFFSET, 0x0000000FU, 0x00000001U); +/*##################################################################### */ + + /* + * Register : L2_TM_DIG_10 @ 0XFD40907C + + * CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001 + * PSU_SERDES_L2_TM_DIG_10_CDR_BIT_LOCK_TIME 0x1 + + * test control for changing cdr lock wait time + * (OFFSET, MASK, VALUE) (0XFD40907C, 0x0000000FU ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L2_TM_DIG_10_OFFSET, 0x0000000FU, 0x00000001U); +/*##################################################################### */ + + /* + * Register : L3_TM_DIG_10 @ 0XFD40D07C + + * CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001 + * PSU_SERDES_L3_TM_DIG_10_CDR_BIT_LOCK_TIME 0x1 + + * test control for changing cdr lock wait time + * (OFFSET, MASK, VALUE) (0XFD40D07C, 0x0000000FU ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L3_TM_DIG_10_OFFSET, 0x0000000FU, 0x00000001U); +/*##################################################################### */ + + /* + * SIOU SETTINGS FOR BYPASS CONTROL,HSRX-DIG + */ + /* + * Register : L0_TM_RST_DLY @ 0XFD4019A4 + + * Delay apb reset by specified amount + * PSU_SERDES_L0_TM_RST_DLY_APB_RST_DLY 0xFF + + * reset delay for apb reset w.r.t pso of hsrx + * (OFFSET, MASK, VALUE) (0XFD4019A4, 0x000000FFU ,0x000000FFU) + */ + PSU_Mask_Write(SERDES_L0_TM_RST_DLY_OFFSET, + 0x000000FFU, 0x000000FFU); +/*##################################################################### */ + + /* + * Register : L0_TM_ANA_BYP_15 @ 0XFD401038 + + * Enable Bypass for <7> of TM_ANA_BYPS_15 + * PSU_SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE 0x1 + + * Bypass control for pcs-pma interface. EQ supplies, main master supply an + * d ps for samp c2c + * (OFFSET, MASK, VALUE) (0XFD401038, 0x00000040U ,0x00000040U) + */ + PSU_Mask_Write(SERDES_L0_TM_ANA_BYP_15_OFFSET, + 0x00000040U, 0x00000040U); +/*##################################################################### */ + + /* + * Register : L0_TM_ANA_BYP_12 @ 0XFD40102C + + * Enable Bypass for <7> of TM_ANA_BYPS_12 + * PSU_SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG 0x1 + + * Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr ena + * ble controls + * (OFFSET, MASK, VALUE) (0XFD40102C, 0x00000040U ,0x00000040U) + */ + PSU_Mask_Write(SERDES_L0_TM_ANA_BYP_12_OFFSET, + 0x00000040U, 0x00000040U); +/*##################################################################### */ + + /* + * Register : L1_TM_RST_DLY @ 0XFD4059A4 + + * Delay apb reset by specified amount + * PSU_SERDES_L1_TM_RST_DLY_APB_RST_DLY 0xFF + + * reset delay for apb reset w.r.t pso of hsrx + * (OFFSET, MASK, VALUE) (0XFD4059A4, 0x000000FFU ,0x000000FFU) + */ + PSU_Mask_Write(SERDES_L1_TM_RST_DLY_OFFSET, + 0x000000FFU, 0x000000FFU); +/*##################################################################### */ + + /* + * Register : L1_TM_ANA_BYP_15 @ 0XFD405038 + + * Enable Bypass for <7> of TM_ANA_BYPS_15 + * PSU_SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE 0x1 + + * Bypass control for pcs-pma interface. EQ supplies, main master supply an + * d ps for samp c2c + * (OFFSET, MASK, VALUE) (0XFD405038, 0x00000040U ,0x00000040U) + */ + PSU_Mask_Write(SERDES_L1_TM_ANA_BYP_15_OFFSET, + 0x00000040U, 0x00000040U); +/*##################################################################### */ + + /* + * Register : L1_TM_ANA_BYP_12 @ 0XFD40502C + + * Enable Bypass for <7> of TM_ANA_BYPS_12 + * PSU_SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG 0x1 + + * Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr ena + * ble controls + * (OFFSET, MASK, VALUE) (0XFD40502C, 0x00000040U ,0x00000040U) + */ + PSU_Mask_Write(SERDES_L1_TM_ANA_BYP_12_OFFSET, + 0x00000040U, 0x00000040U); +/*##################################################################### */ + + /* + * Register : L2_TM_RST_DLY @ 0XFD4099A4 + + * Delay apb reset by specified amount + * PSU_SERDES_L2_TM_RST_DLY_APB_RST_DLY 0xFF + + * reset delay for apb reset w.r.t pso of hsrx + * (OFFSET, MASK, VALUE) (0XFD4099A4, 0x000000FFU ,0x000000FFU) + */ + PSU_Mask_Write(SERDES_L2_TM_RST_DLY_OFFSET, + 0x000000FFU, 0x000000FFU); +/*##################################################################### */ + + /* + * Register : L2_TM_ANA_BYP_15 @ 0XFD409038 + + * Enable Bypass for <7> of TM_ANA_BYPS_15 + * PSU_SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE 0x1 + + * Bypass control for pcs-pma interface. EQ supplies, main master supply an + * d ps for samp c2c + * (OFFSET, MASK, VALUE) (0XFD409038, 0x00000040U ,0x00000040U) + */ + PSU_Mask_Write(SERDES_L2_TM_ANA_BYP_15_OFFSET, + 0x00000040U, 0x00000040U); +/*##################################################################### */ + + /* + * Register : L2_TM_ANA_BYP_12 @ 0XFD40902C + + * Enable Bypass for <7> of TM_ANA_BYPS_12 + * PSU_SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG 0x1 + + * Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr ena + * ble controls + * (OFFSET, MASK, VALUE) (0XFD40902C, 0x00000040U ,0x00000040U) + */ + PSU_Mask_Write(SERDES_L2_TM_ANA_BYP_12_OFFSET, + 0x00000040U, 0x00000040U); +/*##################################################################### */ + + /* + * Register : L3_TM_RST_DLY @ 0XFD40D9A4 + + * Delay apb reset by specified amount + * PSU_SERDES_L3_TM_RST_DLY_APB_RST_DLY 0xFF + + * reset delay for apb reset w.r.t pso of hsrx + * (OFFSET, MASK, VALUE) (0XFD40D9A4, 0x000000FFU ,0x000000FFU) + */ + PSU_Mask_Write(SERDES_L3_TM_RST_DLY_OFFSET, + 0x000000FFU, 0x000000FFU); +/*##################################################################### */ + + /* + * Register : L3_TM_ANA_BYP_15 @ 0XFD40D038 + + * Enable Bypass for <7> of TM_ANA_BYPS_15 + * PSU_SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE 0x1 + + * Bypass control for pcs-pma interface. EQ supplies, main master supply an + * d ps for samp c2c + * (OFFSET, MASK, VALUE) (0XFD40D038, 0x00000040U ,0x00000040U) + */ + PSU_Mask_Write(SERDES_L3_TM_ANA_BYP_15_OFFSET, + 0x00000040U, 0x00000040U); +/*##################################################################### */ + + /* + * Register : L3_TM_ANA_BYP_12 @ 0XFD40D02C + + * Enable Bypass for <7> of TM_ANA_BYPS_12 + * PSU_SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG 0x1 + + * Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr ena + * ble controls + * (OFFSET, MASK, VALUE) (0XFD40D02C, 0x00000040U ,0x00000040U) + */ + PSU_Mask_Write(SERDES_L3_TM_ANA_BYP_12_OFFSET, + 0x00000040U, 0x00000040U); +/*##################################################################### */ + + /* + * DISABLE FPL/FFL + */ + /* + * Register : L0_TM_MISC3 @ 0XFD4019AC + + * CDR fast phase lock control + * PSU_SERDES_L0_TM_MISC3_CDR_EN_FPL 0x0 + + * CDR fast frequency lock control + * PSU_SERDES_L0_TM_MISC3_CDR_EN_FFL 0x0 + + * debug bus selection bit, cdr fast phase and freq controls + * (OFFSET, MASK, VALUE) (0XFD4019AC, 0x00000003U ,0x00000000U) + */ + PSU_Mask_Write(SERDES_L0_TM_MISC3_OFFSET, 0x00000003U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : L1_TM_MISC3 @ 0XFD4059AC + + * CDR fast phase lock control + * PSU_SERDES_L1_TM_MISC3_CDR_EN_FPL 0x0 + + * CDR fast frequency lock control + * PSU_SERDES_L1_TM_MISC3_CDR_EN_FFL 0x0 + + * debug bus selection bit, cdr fast phase and freq controls + * (OFFSET, MASK, VALUE) (0XFD4059AC, 0x00000003U ,0x00000000U) + */ + PSU_Mask_Write(SERDES_L1_TM_MISC3_OFFSET, 0x00000003U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : L2_TM_MISC3 @ 0XFD4099AC + + * CDR fast phase lock control + * PSU_SERDES_L2_TM_MISC3_CDR_EN_FPL 0x0 + + * CDR fast frequency lock control + * PSU_SERDES_L2_TM_MISC3_CDR_EN_FFL 0x0 + + * debug bus selection bit, cdr fast phase and freq controls + * (OFFSET, MASK, VALUE) (0XFD4099AC, 0x00000003U ,0x00000000U) + */ + PSU_Mask_Write(SERDES_L2_TM_MISC3_OFFSET, 0x00000003U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : L3_TM_MISC3 @ 0XFD40D9AC + + * CDR fast phase lock control + * PSU_SERDES_L3_TM_MISC3_CDR_EN_FPL 0x0 + + * CDR fast frequency lock control + * PSU_SERDES_L3_TM_MISC3_CDR_EN_FFL 0x0 + + * debug bus selection bit, cdr fast phase and freq controls + * (OFFSET, MASK, VALUE) (0XFD40D9AC, 0x00000003U ,0x00000000U) + */ + PSU_Mask_Write(SERDES_L3_TM_MISC3_OFFSET, 0x00000003U, 0x00000000U); +/*##################################################################### */ + + /* + * DISABLE DYNAMIC OFFSET CALIBRATION + */ + /* + * Register : L0_TM_EQ11 @ 0XFD401978 + + * Force EQ offset correction algo off if not forced on + * PSU_SERDES_L0_TM_EQ11_FORCE_EQ_OFFS_OFF 0x1 + + * eq dynamic offset correction + * (OFFSET, MASK, VALUE) (0XFD401978, 0x00000010U ,0x00000010U) + */ + PSU_Mask_Write(SERDES_L0_TM_EQ11_OFFSET, 0x00000010U, 0x00000010U); +/*##################################################################### */ + + /* + * Register : L1_TM_EQ11 @ 0XFD405978 + + * Force EQ offset correction algo off if not forced on + * PSU_SERDES_L1_TM_EQ11_FORCE_EQ_OFFS_OFF 0x1 + + * eq dynamic offset correction + * (OFFSET, MASK, VALUE) (0XFD405978, 0x00000010U ,0x00000010U) + */ + PSU_Mask_Write(SERDES_L1_TM_EQ11_OFFSET, 0x00000010U, 0x00000010U); +/*##################################################################### */ + + /* + * Register : L2_TM_EQ11 @ 0XFD409978 + + * Force EQ offset correction algo off if not forced on + * PSU_SERDES_L2_TM_EQ11_FORCE_EQ_OFFS_OFF 0x1 + + * eq dynamic offset correction + * (OFFSET, MASK, VALUE) (0XFD409978, 0x00000010U ,0x00000010U) + */ + PSU_Mask_Write(SERDES_L2_TM_EQ11_OFFSET, 0x00000010U, 0x00000010U); +/*##################################################################### */ + + /* + * Register : L3_TM_EQ11 @ 0XFD40D978 + + * Force EQ offset correction algo off if not forced on + * PSU_SERDES_L3_TM_EQ11_FORCE_EQ_OFFS_OFF 0x1 + + * eq dynamic offset correction + * (OFFSET, MASK, VALUE) (0XFD40D978, 0x00000010U ,0x00000010U) + */ + PSU_Mask_Write(SERDES_L3_TM_EQ11_OFFSET, 0x00000010U, 0x00000010U); +/*##################################################################### */ + + /* + * DISABLE ECO FOR PCIE + */ + /* + * Register : eco_0 @ 0XFD3D001C + + * For future use + * PSU_SIOU_ECO_0_FIELD 0x1 + + * ECO Register for future use + * (OFFSET, MASK, VALUE) (0XFD3D001C, 0xFFFFFFFFU ,0x00000001U) + */ + PSU_Mask_Write(SIOU_ECO_0_OFFSET, 0xFFFFFFFFU, 0x00000001U); +/*##################################################################### */ + + /* + * GT LANE SETTINGS + */ + /* + * Register : ICM_CFG0 @ 0XFD410010 + + * Controls UPHY Lane 0 protocol configuration. 0 - PowerDown, 1 - PCIe .0, + * 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII0, 6 - Unused, 7 - Unused + * PSU_SERDES_ICM_CFG0_L0_ICM_CFG 1 + + * Controls UPHY Lane 1 protocol configuration. 0 - PowerDown, 1 - PCIe.1, + * 2 - Sata1, 3 - USB0, 4 - DP.0, 5 - SGMII1, 6 - Unused, 7 - Unused + * PSU_SERDES_ICM_CFG0_L1_ICM_CFG 4 + + * ICM Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD410010, 0x00000077U ,0x00000041U) + */ + PSU_Mask_Write(SERDES_ICM_CFG0_OFFSET, 0x00000077U, 0x00000041U); +/*##################################################################### */ + + /* + * Register : ICM_CFG1 @ 0XFD410014 + + * Controls UPHY Lane 2 protocol configuration. 0 - PowerDown, 1 - PCIe.1, + * 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII2, 6 - Unused, 7 - Unused + * PSU_SERDES_ICM_CFG1_L2_ICM_CFG 3 + + * Controls UPHY Lane 3 protocol configuration. 0 - PowerDown, 1 - PCIe.3, + * 2 - Sata1, 3 - USB1, 4 - DP.0, 5 - SGMII3, 6 - Unused, 7 - Unused + * PSU_SERDES_ICM_CFG1_L3_ICM_CFG 2 + + * ICM Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD410014, 0x00000077U ,0x00000023U) + */ + PSU_Mask_Write(SERDES_ICM_CFG1_OFFSET, 0x00000077U, 0x00000023U); +/*##################################################################### */ + + /* + * CHECKING PLL LOCK + */ + /* + * ENABLE SERIAL DATA MUX DEEMPH + */ + /* + * Register : L1_TXPMD_TM_45 @ 0XFD404CB4 + + * Enable/disable DP post2 path + * PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH 0x1 + + * Override enable/disable of DP post2 path + * PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH 0x1 + + * Override enable/disable of DP post1 path + * PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH 0x1 + + * Enable/disable DP main path + * PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH 0x1 + + * Override enable/disable of DP main path + * PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH 0x1 + + * Post or pre or main DP path selection + * (OFFSET, MASK, VALUE) (0XFD404CB4, 0x00000037U ,0x00000037U) + */ + PSU_Mask_Write(SERDES_L1_TXPMD_TM_45_OFFSET, + 0x00000037U, 0x00000037U); +/*##################################################################### */ + + /* + * Register : L1_TX_ANA_TM_118 @ 0XFD4041D8 + + * Test register force for enabling/disablign TX deemphasis bits <17:0> + * PSU_SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0 0x1 + + * Enable Override of TX deemphasis + * (OFFSET, MASK, VALUE) (0XFD4041D8, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L1_TX_ANA_TM_118_OFFSET, + 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : L3_TX_ANA_TM_118 @ 0XFD40C1D8 + + * Test register force for enabling/disablign TX deemphasis bits <17:0> + * PSU_SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0 0x1 + + * Enable Override of TX deemphasis + * (OFFSET, MASK, VALUE) (0XFD40C1D8, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L3_TX_ANA_TM_118_OFFSET, + 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * CDR AND RX EQUALIZATION SETTINGS + */ + /* + * Register : L3_TM_CDR5 @ 0XFD40DC14 + + * FPHL FSM accumulate cycles + * PSU_SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES 0x7 + + * FFL Phase0 int gain aka 2ol SD update rate + * PSU_SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN 0x6 + + * Fast phase lock controls -- FSM accumulator cycle control and phase 0 in + * t gain control. + * (OFFSET, MASK, VALUE) (0XFD40DC14, 0x000000FFU ,0x000000E6U) + */ + PSU_Mask_Write(SERDES_L3_TM_CDR5_OFFSET, 0x000000FFU, 0x000000E6U); +/*##################################################################### */ + + /* + * Register : L3_TM_CDR16 @ 0XFD40DC40 + + * FFL Phase0 prop gain aka 1ol SD update rate + * PSU_SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN 0xC + + * Fast phase lock controls -- phase 0 prop gain + * (OFFSET, MASK, VALUE) (0XFD40DC40, 0x0000001FU ,0x0000000CU) + */ + PSU_Mask_Write(SERDES_L3_TM_CDR16_OFFSET, 0x0000001FU, 0x0000000CU); +/*##################################################################### */ + + /* + * Register : L3_TM_EQ0 @ 0XFD40D94C + + * EQ stg 2 controls BYPASSED + * PSU_SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP 1 + + * eq stg1 and stg2 controls + * (OFFSET, MASK, VALUE) (0XFD40D94C, 0x00000020U ,0x00000020U) + */ + PSU_Mask_Write(SERDES_L3_TM_EQ0_OFFSET, 0x00000020U, 0x00000020U); +/*##################################################################### */ + + /* + * Register : L3_TM_EQ1 @ 0XFD40D950 + + * EQ STG2 RL PROG + * PSU_SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG 0x2 + + * EQ stg 2 preamp mode val + * PSU_SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL 0x1 + + * eq stg1 and stg2 controls + * (OFFSET, MASK, VALUE) (0XFD40D950, 0x00000007U ,0x00000006U) + */ + PSU_Mask_Write(SERDES_L3_TM_EQ1_OFFSET, 0x00000007U, 0x00000006U); +/*##################################################################### */ + + /* + * GEM SERDES SETTINGS + */ + /* + * ENABLE PRE EMPHAIS AND VOLTAGE SWING + */ + /* + * Register : L1_TXPMD_TM_48 @ 0XFD404CC0 + + * Margining factor value + * PSU_SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR 0 + + * Margining factor + * (OFFSET, MASK, VALUE) (0XFD404CC0, 0x0000001FU ,0x00000000U) + */ + PSU_Mask_Write(SERDES_L1_TXPMD_TM_48_OFFSET, + 0x0000001FU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : L1_TX_ANA_TM_18 @ 0XFD404048 + + * pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-em + * phasis, Others: reserved + * PSU_SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0 0 + + * Override for PIPE TX de-emphasis + * (OFFSET, MASK, VALUE) (0XFD404048, 0x000000FFU ,0x00000000U) + */ + PSU_Mask_Write(SERDES_L1_TX_ANA_TM_18_OFFSET, + 0x000000FFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : L3_TX_ANA_TM_18 @ 0XFD40C048 + + * pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-em + * phasis, Others: reserved + * PSU_SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0 0x1 + + * Override for PIPE TX de-emphasis + * (OFFSET, MASK, VALUE) (0XFD40C048, 0x000000FFU ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L3_TX_ANA_TM_18_OFFSET, + 0x000000FFU, 0x00000001U); +/*##################################################################### */ + + + return 1; } -unsigned long psu_resetin_init_data() { - // : PUTTING SERDES PERIPHERAL IN RESET - // : PUTTING USB0 IN RESET - /*Register : RST_LPD_TOP @ 0XFF5E023C

+unsigned long psu_resetout_init_data(void) +{ + /* + * TAKING SERDES PERIPHERAL OUT OF RESET RESET + */ + /* + * PUTTING USB0 IN RESET + */ + /* + * Register : RST_LPD_TOP @ 0XFF5E023C - USB 0 reset for control registers - PSU_CRL_APB_RST_LPD_TOP_USB0_APB_RESET 0X1 + * USB 0 reset for control registers + * PSU_CRL_APB_RST_LPD_TOP_USB0_APB_RESET 0X0 - USB 0 sleep circuit reset - PSU_CRL_APB_RST_LPD_TOP_USB0_HIBERRESET 0X1 + * Software control register for the LPD block. + * (OFFSET, MASK, VALUE) (0XFF5E023C, 0x00000400U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_TOP_OFFSET, 0x00000400U, 0x00000000U); +/*##################################################################### */ - USB 0 reset - PSU_CRL_APB_RST_LPD_TOP_USB0_CORERESET 0X1 + /* + * HIBERREST + */ + /* + * Register : RST_LPD_TOP @ 0XFF5E023C - Software control register for the LPD block. - (OFFSET, MASK, VALUE) (0XFF5E023C, 0x00000540U ,0x00000540U) - RegMask = (CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK | CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK | CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK | 0 ); + * USB 0 sleep circuit reset + * PSU_CRL_APB_RST_LPD_TOP_USB0_HIBERRESET 0X0 - RegVal = ((0x00000001U << CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT - | 0x00000001U << CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT - | 0x00000001U << CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RST_LPD_TOP_OFFSET ,0x00000540U ,0x00000540U); - /*############################################################################################################################ */ + * USB 0 reset + * PSU_CRL_APB_RST_LPD_TOP_USB0_CORERESET 0X0 - // : PUTTING GEM0 IN RESET - /*Register : RST_LPD_IOU0 @ 0XFF5E0230

+ * Software control register for the LPD block. + * (OFFSET, MASK, VALUE) (0XFF5E023C, 0x00000140U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_TOP_OFFSET, 0x00000140U, 0x00000000U); +/*##################################################################### */ - GEM 3 reset - PSU_CRL_APB_RST_LPD_IOU0_GEM3_RESET 0X1 + /* + * PUTTING GEM0 IN RESET + */ + /* + * Register : RST_LPD_IOU0 @ 0XFF5E0230 - Software controlled reset for the GEMs - (OFFSET, MASK, VALUE) (0XFF5E0230, 0x00000008U ,0x00000008U) - RegMask = (CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK | 0 ); + * GEM 3 reset + * PSU_CRL_APB_RST_LPD_IOU0_GEM3_RESET 0X0 - RegVal = ((0x00000001U << CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RST_LPD_IOU0_OFFSET ,0x00000008U ,0x00000008U); - /*############################################################################################################################ */ + * Software controlled reset for the GEMs + * (OFFSET, MASK, VALUE) (0XFF5E0230, 0x00000008U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_IOU0_OFFSET, + 0x00000008U, 0x00000000U); +/*##################################################################### */ - // : PUTTING SATA IN RESET - /*Register : RST_FPD_TOP @ 0XFD1A0100

+ /* + * PUTTING SATA IN RESET + */ + /* + * Register : sata_misc_ctrl @ 0XFD3D0100 - Sata block level reset - PSU_CRF_APB_RST_FPD_TOP_SATA_RESET 0X1 + * Sata PM clock control select + * PSU_SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL 0x3 - FPD Block level software controlled reset - (OFFSET, MASK, VALUE) (0XFD1A0100, 0x00000002U ,0x00000002U) - RegMask = (CRF_APB_RST_FPD_TOP_SATA_RESET_MASK | 0 ); + * Misc Contorls for SATA.This register may only be modified during bootup + * (while SATA block is disabled) + * (OFFSET, MASK, VALUE) (0XFD3D0100, 0x00000003U ,0x00000003U) + */ + PSU_Mask_Write(SIOU_SATA_MISC_CTRL_OFFSET, 0x00000003U, 0x00000003U); +/*##################################################################### */ - RegVal = ((0x00000001U << CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_RST_FPD_TOP_OFFSET ,0x00000002U ,0x00000002U); - /*############################################################################################################################ */ + /* + * Register : RST_FPD_TOP @ 0XFD1A0100 - // : PUTTING PCIE IN RESET - /*Register : RST_FPD_TOP @ 0XFD1A0100

+ * Sata block level reset + * PSU_CRF_APB_RST_FPD_TOP_SATA_RESET 0X0 - PCIE config reset - PSU_CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET 0X1 + * FPD Block level software controlled reset + * (OFFSET, MASK, VALUE) (0XFD1A0100, 0x00000002U ,0x00000000U) + */ + PSU_Mask_Write(CRF_APB_RST_FPD_TOP_OFFSET, 0x00000002U, 0x00000000U); +/*##################################################################### */ - PCIE control block level reset - PSU_CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET 0X1 + /* + * PUTTING PCIE CFG AND BRIDGE IN RESET + */ + /* + * Register : RST_FPD_TOP @ 0XFD1A0100 - PCIE bridge block level reset (AXI interface) - PSU_CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET 0X1 + * PCIE config reset + * PSU_CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET 0X0 - FPD Block level software controlled reset - (OFFSET, MASK, VALUE) (0XFD1A0100, 0x000E0000U ,0x000E0000U) - RegMask = (CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK | CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK | CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK | 0 ); + * PCIE bridge block level reset (AXI interface) + * PSU_CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET 0X0 - RegVal = ((0x00000001U << CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT - | 0x00000001U << CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT - | 0x00000001U << CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_RST_FPD_TOP_OFFSET ,0x000E0000U ,0x000E0000U); - /*############################################################################################################################ */ + * FPD Block level software controlled reset + * (OFFSET, MASK, VALUE) (0XFD1A0100, 0x000C0000U ,0x00000000U) + */ + PSU_Mask_Write(CRF_APB_RST_FPD_TOP_OFFSET, 0x000C0000U, 0x00000000U); +/*##################################################################### */ - // : PUTTING DP IN RESET - /*Register : DP_TX_PHY_POWER_DOWN @ 0XFD4A0238

+ /* + * PUTTING DP IN RESET + */ + /* + * Register : RST_FPD_TOP @ 0XFD1A0100 - Two bits per lane. When set to 11, moves the GT to power down mode. When set to 00, GT will be in active state. bits [1:0] - - ane0 Bits [3:2] - lane 1 - PSU_DP_DP_TX_PHY_POWER_DOWN_POWER_DWN 0XA + * Display Port block level reset (includes DPDMA) + * PSU_CRF_APB_RST_FPD_TOP_DP_RESET 0X0 - Control PHY Power down - (OFFSET, MASK, VALUE) (0XFD4A0238, 0x0000000FU ,0x0000000AU) - RegMask = (DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK | 0 ); + * FPD Block level software controlled reset + * (OFFSET, MASK, VALUE) (0XFD1A0100, 0x00010000U ,0x00000000U) + */ + PSU_Mask_Write(CRF_APB_RST_FPD_TOP_OFFSET, 0x00010000U, 0x00000000U); +/*##################################################################### */ - RegVal = ((0x0000000AU << DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DP_DP_TX_PHY_POWER_DOWN_OFFSET ,0x0000000FU ,0x0000000AU); - /*############################################################################################################################ */ + /* + * Register : DP_PHY_RESET @ 0XFD4A0200 - /*Register : DP_PHY_RESET @ 0XFD4A0200

+ * Set to '1' to hold the GT in reset. Clear to release. + * PSU_DP_DP_PHY_RESET_GT_RESET 0X0 - Set to '1' to hold the GT in reset. Clear to release. - PSU_DP_DP_PHY_RESET_GT_RESET 0X1 + * Reset the transmitter PHY. + * (OFFSET, MASK, VALUE) (0XFD4A0200, 0x00000002U ,0x00000000U) + */ + PSU_Mask_Write(DP_DP_PHY_RESET_OFFSET, 0x00000002U, 0x00000000U); +/*##################################################################### */ - Reset the transmitter PHY. - (OFFSET, MASK, VALUE) (0XFD4A0200, 0x00000002U ,0x00000002U) - RegMask = (DP_DP_PHY_RESET_GT_RESET_MASK | 0 ); + /* + * Register : DP_TX_PHY_POWER_DOWN @ 0XFD4A0238 - RegVal = ((0x00000001U << DP_DP_PHY_RESET_GT_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DP_DP_PHY_RESET_OFFSET ,0x00000002U ,0x00000002U); - /*############################################################################################################################ */ + * Two bits per lane. When set to 11, moves the GT to power down mode. When + * set to 00, GT will be in active state. bits [1:0] - lane0 Bits [3:2] - + * lane 1 + * PSU_DP_DP_TX_PHY_POWER_DOWN_POWER_DWN 0X0 - /*Register : RST_FPD_TOP @ 0XFD1A0100

+ * Control PHY Power down + * (OFFSET, MASK, VALUE) (0XFD4A0238, 0x0000000FU ,0x00000000U) + */ + PSU_Mask_Write(DP_DP_TX_PHY_POWER_DOWN_OFFSET, + 0x0000000FU, 0x00000000U); +/*##################################################################### */ - Display Port block level reset (includes DPDMA) - PSU_CRF_APB_RST_FPD_TOP_DP_RESET 0X1 + /* + * USB0 GFLADJ + */ + /* + * Register : GUSB2PHYCFG @ 0XFE20C200 - FPD Block level software controlled reset - (OFFSET, MASK, VALUE) (0XFD1A0100, 0x00010000U ,0x00010000U) - RegMask = (CRF_APB_RST_FPD_TOP_DP_RESET_MASK | 0 ); + * USB 2.0 Turnaround Time (USBTrdTim) Sets the turnaround time in PHY cloc + * ks. Specifies the response time for a MAC request to the Packet FIFO Con + * troller (PFC) to fetch data from the DFIFO (SPRAM). The following are th + * e required values for the minimum SoC bus frequency of 60 MHz. USB turna + * round time is a critical certification criteria when using long cables a + * nd five hub levels. The required values for this field: - 4'h5: When the + * MAC interface is 16-bit UTMI+. - 4'h9: When the MAC interface is 8-bit + * UTMI+/ULPI. If SoC bus clock is less than 60 MHz, and USB turnaround tim + * e is not critical, this field can be set to a larger value. Note: This f + * ield is valid only in device mode. + * PSU_USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM 0x9 - RegVal = ((0x00000001U << CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_RST_FPD_TOP_OFFSET ,0x00010000U ,0x00010000U); - /*############################################################################################################################ */ + * Transceiver Delay: Enables a delay between the assertion of the UTMI/ULP + * I Transceiver Select signal (for HS) and the assertion of the TxValid si + * gnal during a HS Chirp. When this bit is set to 1, a delay (of approxima + * tely 2.5 us) is introduced from the time when the Transceiver Select is + * set to 2'b00 (HS) to the time the TxValid is driven to 0 for sending the + * chirp-K. This delay is required for some UTMI/ULPI PHYs. Note: - If you + * enable the hibernation feature when the device core comes out of power- + * off, you must re-initialize this bit with the appropriate value because + * the core does not save and restore this bit value during hibernation. - + * This bit is valid only in device mode. + * PSU_USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY 0x0 + + * Enable utmi_sleep_n and utmi_l1_suspend_n (EnblSlpM) The application use + * s this bit to control utmi_sleep_n and utmi_l1_suspend_n assertion to th + * e PHY in the L1 state. - 1'b0: utmi_sleep_n and utmi_l1_suspend_n assert + * ion from the core is not transferred to the external PHY. - 1'b1: utmi_s + * leep_n and utmi_l1_suspend_n assertion from the core is transferred to t + * he external PHY. Note: This bit must be set high for Port0 if PHY is use + * d. Note: In Device mode - Before issuing any device endpoint command whe + * n operating in 2.0 speeds, disable this bit and enable it after the comm + * and completes. Without disabling this bit, if a command is issued when t + * he device is in L1 state and if mac2_clk (utmi_clk/ulpi_clk) is gated of + * f, the command will not get completed. + * PSU_USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM 0x0 + + * USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial Transceiver Select T + * he application uses this bit to select a high-speed PHY or a full-speed + * transceiver. - 1'b0: USB 2.0 high-speed UTMI+ or ULPI PHY. This bit is a + * lways 0, with Write Only access. - 1'b1: USB 1.1 full-speed serial trans + * ceiver. This bit is always 1, with Write Only access. If both interface + * types are selected in coreConsultant (that is, parameters' values are no + * t zero), the application uses this bit to select the active interface is + * active, with Read-Write bit access. Note: USB 1.1 full-serial transceiv + * er is not supported. This bit always reads as 1'b0. + * PSU_USB3_0_XHCI_GUSB2PHYCFG_PHYSEL 0x0 + + * Suspend USB2.0 HS/FS/LS PHY (SusPHY) When set, USB2.0 PHY enters Suspend + * mode if Suspend conditions are valid. For DRD/OTG configurations, it is + * recommended that this bit is set to 0 during coreConsultant configurati + * on. If it is set to 1, then the application must clear this bit after po + * wer-on reset. Application needs to set it to 1 after the core initializa + * tion completes. For all other configurations, this bit can be set to 1 d + * uring core configuration. Note: - In host mode, on reset, this bit is se + * t to 1. Software can override this bit after reset. - In device mode, be + * fore issuing any device endpoint command when operating in 2.0 speeds, d + * isable this bit and enable it after the command completes. If you issue + * a command without disabling this bit when the device is in L2 state and + * if mac2_clk (utmi_clk/ulpi_clk) is gated off, the command will not get c + * ompleted. + * PSU_USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20 0x1 + + * Full-Speed Serial Interface Select (FSIntf) The application uses this bi + * t to select a unidirectional or bidirectional USB 1.1 full-speed serial + * transceiver interface. - 1'b0: 6-pin unidirectional full-speed serial in + * terface. This bit is set to 0 with Read Only access. - 1'b1: 3-pin bidir + * ectional full-speed serial interface. This bit is set to 0 with Read Onl + * y access. Note: USB 1.1 full-speed serial interface is not supported. Th + * is bit always reads as 1'b0. + * PSU_USB3_0_XHCI_GUSB2PHYCFG_FSINTF 0x0 + + * ULPI or UTMI+ Select (ULPI_UTMI_Sel) The application uses this bit to se + * lect a UTMI+ or ULPI Interface. - 1'b0: UTMI+ Interface - 1'b1: ULPI Int + * erface This bit is writable only if UTMI+ and ULPI is specified for High + * -Speed PHY Interface(s) in coreConsultant configuration (DWC_USB3_HSPHY_ + * INTERFACE = 3). Otherwise, this bit is read-only and the value depends o + * n the interface selected through DWC_USB3_HSPHY_INTERFACE. + * PSU_USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL 0x1 + + * PHY Interface (PHYIf) If UTMI+ is selected, the application uses this bi + * t to configure the core to support a UTMI+ PHY with an 8- or 16-bit inte + * rface. - 1'b0: 8 bits - 1'b1: 16 bits ULPI Mode: 1'b0 Note: - All the en + * abled 2.0 ports must have the same clock frequency as Port0 clock freque + * ncy (utmi_clk[0]). - The UTMI 8-bit and 16-bit modes cannot be used toge + * ther for different ports at the same time (that is, all the ports must b + * e in 8-bit mode, or all of them must be in 16-bit mode, at a time). - If + * any of the USB 2.0 ports is selected as ULPI port for operation, then a + * ll the USB 2.0 ports must be operating at 60 MHz. + * PSU_USB3_0_XHCI_GUSB2PHYCFG_PHYIF 0x0 + + * HS/FS Timeout Calibration (TOutCal) The number of PHY clocks, as indicat + * ed by the application in this field, is multiplied by a bit-time factor; + * this factor is added to the high-speed/full-speed interpacket timeout d + * uration in the core to account for additional delays introduced by the P + * HY. This may be required, since the delay introduced by the PHY in gener + * ating the linestate condition may vary among PHYs. The USB standard time + * out value for high-speed operation is 736 to 816 (inclusive) bit times. + * The USB standard timeout value for full-speed operation is 16 to 18 (inc + * lusive) bit times. The application must program this field based on the + * speed of connection. The number of bit times added per PHY clock are: Hi + * gh-speed operation: - One 30-MHz PHY clock = 16 bit times - One 60-MHz P + * HY clock = 8 bit times Full-speed operation: - One 30-MHz PHY clock = 0. + * 4 bit times - One 60-MHz PHY clock = 0.2 bit times - One 48-MHz PHY cloc + * k = 0.25 bit times + * PSU_USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL 0x7 + + * ULPI External VBUS Drive (ULPIExtVbusDrv) Selects supply source to drive + * 5V on VBUS, in the ULPI PHY. - 1'b0: PHY drives VBUS with internal char + * ge pump (default). - 1'b1: PHY drives VBUS with an external supply. (Onl + * y when RTL parameter DWC_USB3_HSPHY_INTERFACE = 2 or 3) + * PSU_USB3_0_XHCI_GUSB2PHYCFG_ULPIEXTVBUSDRV 0x1 + + * Global USB2 PHY Configuration Register The application must program this + * register before starting any transactions on either the SoC bus or the + * USB. In Device-only configurations, only one register is needed. In Host + * mode, per-port registers are implemented. + * (OFFSET, MASK, VALUE) (0XFE20C200, 0x00023FFFU ,0x00022457U) + */ + PSU_Mask_Write(USB3_0_XHCI_GUSB2PHYCFG_OFFSET, + 0x00023FFFU, 0x00022457U); +/*##################################################################### */ + + /* + * Register : GFLADJ @ 0XFE20C630 + + * This field indicates the frame length adjustment to be applied when SOF/ + * ITP counter is running on the ref_clk. This register value is used to ad + * just the ITP interval when GCTL[SOFITPSYNC] is set to '1'; SOF and ITP i + * nterval when GLADJ.GFLADJ_REFCLK_LPM_SEL is set to '1'. This field must + * be programmed to a non-zero value only if GFLADJ_REFCLK_LPM_SEL is set t + * o '1' or GCTL.SOFITPSYNC is set to '1'. The value is derived as follows: + * FLADJ_REF_CLK_FLADJ=((125000/ref_clk_period_integer)-(125000/ref_clk_pe + * riod)) * ref_clk_period where - the ref_clk_period_integer is the intege + * r value of the ref_clk period got by truncating the decimal (fractional) + * value that is programmed in the GUCTL.REF_CLK_PERIOD field. - the ref_c + * lk_period is the ref_clk period including the fractional value. Examples + * : If the ref_clk is 24 MHz then - GUCTL.REF_CLK_PERIOD = 41 - GFLADJ.GLA + * DJ_REFCLK_FLADJ = ((125000/41)-(125000/41.6666))*41.6666 = 2032 (ignorin + * g the fractional value) If the ref_clk is 48 MHz then - GUCTL.REF_CLK_PE + * RIOD = 20 - GFLADJ.GLADJ_REFCLK_FLADJ = ((125000/20)-(125000/20.8333))*2 + * 0.8333 = 5208 (ignoring the fractional value) + * PSU_USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ 0x0 + + * Global Frame Length Adjustment Register This register provides options f + * or the software to control the core behavior with respect to SOF (Start + * of Frame) and ITP (Isochronous Timestamp Packet) timers and frame timer + * functionality. It provides an option to override the fladj_30mhz_reg sid + * eband signal. In addition, it enables running SOF or ITP frame timer cou + * nters completely from the ref_clk. This facilitates hardware LPM in host + * mode with the SOF or ITP counters being run from the ref_clk signal. + * (OFFSET, MASK, VALUE) (0XFE20C630, 0x003FFF00U ,0x00000000U) + */ + PSU_Mask_Write(USB3_0_XHCI_GFLADJ_OFFSET, 0x003FFF00U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : GUCTL1 @ 0XFE20C11C + + * When this bit is set to '0', termsel, xcvrsel will become 0 during end o + * f resume while the opmode will become 0 once controller completes end of + * resume and enters U0 state (2 separate commandswill be issued). When th + * is bit is set to '1', all the termsel, xcvrsel, opmode becomes 0 during + * end of resume itself (only 1 command will be issued) + * PSU_USB3_0_XHCI_GUCTL1_RESUME_TERMSEL_XCVRSEL_UNIFY 0x1 + + * Reserved + * PSU_USB3_0_XHCI_GUCTL1_RESERVED_9 0x1 + + * Global User Control Register 1 + * (OFFSET, MASK, VALUE) (0XFE20C11C, 0x00000600U ,0x00000600U) + */ + PSU_Mask_Write(USB3_0_XHCI_GUCTL1_OFFSET, 0x00000600U, 0x00000600U); +/*##################################################################### */ + + /* + * Register : GUCTL @ 0XFE20C12C + + * Host IN Auto Retry (USBHstInAutoRetryEn) When set, this field enables th + * e Auto Retry feature. For IN transfers (non-isochronous) that encounter + * data packets with CRC errors or internal overrun scenarios, the auto ret + * ry feature causes the Host core to reply to the device with a non-termin + * ating retry ACK (that is, an ACK transaction packet with Retry = 1 and N + * umP != 0). If the Auto Retry feature is disabled (default), the core wil + * l respond with a terminating retry ACK (that is, an ACK transaction pack + * et with Retry = 1 and NumP = 0). - 1'b0: Auto Retry Disabled - 1'b1: Aut + * o Retry Enabled Note: This bit is also applicable to the device mode. + * PSU_USB3_0_XHCI_GUCTL_USBHSTINAUTORETRYEN 0x1 + + * Global User Control Register: This register provides a few options for t + * he software to control the core behavior in the Host mode. Most of the o + * ptions are used to improve host inter-operability with different devices + * . + * (OFFSET, MASK, VALUE) (0XFE20C12C, 0x00004000U ,0x00004000U) + */ + PSU_Mask_Write(USB3_0_XHCI_GUCTL_OFFSET, 0x00004000U, 0x00004000U); +/*##################################################################### */ + + /* + * UPDATING TWO PCIE REGISTERS DEFAULT VALUES, AS THESE REGISTERS HAVE INCO + * RRECT RESET VALUES IN SILICON. + */ + /* + * Register : ATTR_25 @ 0XFD480064 + + * If TRUE Completion Timeout Disable is supported. This is required to be + * TRUE for Endpoint and either setting allowed for Root ports. Drives Devi + * ce Capability 2 [4]; EP=0x0001; RP=0x0001 + * PSU_PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED 0X1 + + * ATTR_25 + * (OFFSET, MASK, VALUE) (0XFD480064, 0x00000200U ,0x00000200U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_25_OFFSET, 0x00000200U, 0x00000200U); +/*##################################################################### */ + + /* + * PCIE SETTINGS + */ + /* + * Register : ATTR_7 @ 0XFD48001C + + * Specifies mask/settings for Base Address Register (BAR) 0. If BAR is not + * to be implemented, set to 32'h00000000. Bits are defined as follows: Me + * mory Space BAR [0] = Mem Space Indicator (set to 0) [2:1] = Type field ( + * 10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask + * for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to 1, w + * here 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63: + * n bits of \'7bBAR1,BAR0\'7d to 1. IO Space BAR 0] = IO Space Indicator ( + * set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of B + * AR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; + * EP=0x0004; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_7_ATTR_BAR0 0x0 + + * ATTR_7 + * (OFFSET, MASK, VALUE) (0XFD48001C, 0x0000FFFFU ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_7_OFFSET, 0x0000FFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_8 @ 0XFD480020 + + * Specifies mask/settings for Base Address Register (BAR) 0. If BAR is not + * to be implemented, set to 32'h00000000. Bits are defined as follows: Me + * mory Space BAR [0] = Mem Space Indicator (set to 0) [2:1] = Type field ( + * 10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask + * for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to 1, w + * here 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63: + * n bits of \'7bBAR1,BAR0\'7d to 1. IO Space BAR 0] = IO Space Indicator ( + * set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of B + * AR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; + * EP=0xFFF0; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_8_ATTR_BAR0 0x0 + + * ATTR_8 + * (OFFSET, MASK, VALUE) (0XFD480020, 0x0000FFFFU ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_8_OFFSET, 0x0000FFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_9 @ 0XFD480024 + + * Specifies mask/settings for Base Address Register (BAR) 1 if BAR0 is a 3 + * 2-bit BAR, or the upper bits of \'7bBAR1,BAR0\'7d if BAR0 is a 64-bit BA + * R. If BAR is not to be implemented, set to 32'h00000000. See BAR0 descri + * ption if this functions as the upper bits of a 64-bit BAR. Bits are defi + * ned as follows: Memory Space BAR (not upper bits of BAR0) [0] = Mem Spac + * e Indicator (set to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) + * [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if + * 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size + * in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR2,BAR1\'7d t + * o 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set + * to 0) [31:2] = Mask for writable bits of BAR; set uppermost 31:n bits t + * o 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_9_ATTR_BAR1 0x0 + + * ATTR_9 + * (OFFSET, MASK, VALUE) (0XFD480024, 0x0000FFFFU ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_9_OFFSET, 0x0000FFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_10 @ 0XFD480028 + + * Specifies mask/settings for Base Address Register (BAR) 1 if BAR0 is a 3 + * 2-bit BAR, or the upper bits of \'7bBAR1,BAR0\'7d if BAR0 is a 64-bit BA + * R. If BAR is not to be implemented, set to 32'h00000000. See BAR0 descri + * ption if this functions as the upper bits of a 64-bit BAR. Bits are defi + * ned as follows: Memory Space BAR (not upper bits of BAR0) [0] = Mem Spac + * e Indicator (set to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) + * [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if + * 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size + * in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR2,BAR1\'7d t + * o 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set + * to 0) [31:2] = Mask for writable bits of BAR; set uppermost 31:n bits t + * o 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_10_ATTR_BAR1 0x0 + + * ATTR_10 + * (OFFSET, MASK, VALUE) (0XFD480028, 0x0000FFFFU ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_10_OFFSET, 0x0000FFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_11 @ 0XFD48002C + + * For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 2 if BAR1 is a 32-bit BAR, or the upper bits of \'7bBAR2,BAR1\'7d if BA + * R1 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR1 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root: This must be set to 00FF_FFF + * F. For an endpoint, bits are defined as follows: Memory Space BAR (not u + * pper bits of BAR1) [0] = Mem Space Indicator (set to 0) [2:1] = Type fie + * ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = M + * ask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to + * 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost + * 63:n bits of \'7bBAR3,BAR2\'7d to 1. IO Space BAR 0] = IO Space Indicat + * or (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits + * of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in byt + * es.; EP=0x0004; RP=0xFFFF + * PSU_PCIE_ATTRIB_ATTR_11_ATTR_BAR2 0xFFFF + + * ATTR_11 + * (OFFSET, MASK, VALUE) (0XFD48002C, 0x0000FFFFU ,0x0000FFFFU) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_11_OFFSET, 0x0000FFFFU, 0x0000FFFFU); +/*##################################################################### */ + + /* + * Register : ATTR_12 @ 0XFD480030 + + * For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 2 if BAR1 is a 32-bit BAR, or the upper bits of \'7bBAR2,BAR1\'7d if BA + * R1 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR1 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root: This must be set to 00FF_FFF + * F. For an endpoint, bits are defined as follows: Memory Space BAR (not u + * pper bits of BAR1) [0] = Mem Space Indicator (set to 0) [2:1] = Type fie + * ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = M + * ask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to + * 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost + * 63:n bits of \'7bBAR3,BAR2\'7d to 1. IO Space BAR 0] = IO Space Indicat + * or (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits + * of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in byt + * es.; EP=0xFFF0; RP=0x00FF + * PSU_PCIE_ATTRIB_ATTR_12_ATTR_BAR2 0xFF + + * ATTR_12 + * (OFFSET, MASK, VALUE) (0XFD480030, 0x0000FFFFU ,0x000000FFU) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_12_OFFSET, 0x0000FFFFU, 0x000000FFU); +/*##################################################################### */ + + /* + * Register : ATTR_13 @ 0XFD480034 + + * For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 3 if BAR2 is a 32-bit BAR, or the upper bits of \'7bBAR3,BAR2\'7d if BA + * R2 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR2 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root, this must be set to: FFFF_00 + * 00 = IO Limit/Base Registers not implemented FFFF_F0F0 = IO Limit/Base R + * egisters use 16-bit decode FFFF_F1F1 = IO Limit/Base Registers use 32-bi + * t decode For an endpoint, bits are defined as follows: Memory Space BAR + * (not upper bits of BAR2) [0] = Mem Space Indicator (set to 0) [2:1] = Ty + * pe field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31: + * 4] = Mask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bi + * ts to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set upp + * ermost 63:n bits of \'7bBAR4,BAR3\'7d to 1. IO Space BAR 0] = IO Space I + * ndicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable + * bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size + * in bytes.; EP=0xFFFF; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_13_ATTR_BAR3 0x0 + + * ATTR_13 + * (OFFSET, MASK, VALUE) (0XFD480034, 0x0000FFFFU ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_13_OFFSET, 0x0000FFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_14 @ 0XFD480038 + + * For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 3 if BAR2 is a 32-bit BAR, or the upper bits of \'7bBAR3,BAR2\'7d if BA + * R2 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR2 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root, this must be set to: FFFF_00 + * 00 = IO Limit/Base Registers not implemented FFFF_F0F0 = IO Limit/Base R + * egisters use 16-bit decode FFFF_F1F1 = IO Limit/Base Registers use 32-bi + * t decode For an endpoint, bits are defined as follows: Memory Space BAR + * (not upper bits of BAR2) [0] = Mem Space Indicator (set to 0) [2:1] = Ty + * pe field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31: + * 4] = Mask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bi + * ts to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set upp + * ermost 63:n bits of \'7bBAR4,BAR3\'7d to 1. IO Space BAR 0] = IO Space I + * ndicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable + * bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size + * in bytes.; EP=0xFFFF; RP=0xFFFF + * PSU_PCIE_ATTRIB_ATTR_14_ATTR_BAR3 0xFFFF + + * ATTR_14 + * (OFFSET, MASK, VALUE) (0XFD480038, 0x0000FFFFU ,0x0000FFFFU) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_14_OFFSET, 0x0000FFFFU, 0x0000FFFFU); +/*##################################################################### */ + + /* + * Register : ATTR_15 @ 0XFD48003C + + * For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 4 if BAR3 is a 32-bit BAR, or the upper bits of \'7bBAR4,BAR3\'7d if BA + * R3 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR3 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root: This must be set to FFF0_FFF + * 0. For an endpoint, bits are defined as follows: Memory Space BAR (not u + * pper bits of BAR3) [0] = Mem Space Indicator (set to 0) [2:1] = Type fie + * ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = M + * ask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to + * 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost + * 63:n bits of \'7bBAR5,BAR4\'7d to 1. IO Space BAR 0] = IO Space Indicat + * or (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits + * of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in byt + * es.; EP=0x0004; RP=0xFFF0 + * PSU_PCIE_ATTRIB_ATTR_15_ATTR_BAR4 0xFFF0 + + * ATTR_15 + * (OFFSET, MASK, VALUE) (0XFD48003C, 0x0000FFFFU ,0x0000FFF0U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_15_OFFSET, 0x0000FFFFU, 0x0000FFF0U); +/*##################################################################### */ + + /* + * Register : ATTR_16 @ 0XFD480040 + + * For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 4 if BAR3 is a 32-bit BAR, or the upper bits of \'7bBAR4,BAR3\'7d if BA + * R3 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR3 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root: This must be set to FFF0_FFF + * 0. For an endpoint, bits are defined as follows: Memory Space BAR (not u + * pper bits of BAR3) [0] = Mem Space Indicator (set to 0) [2:1] = Type fie + * ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = M + * ask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to + * 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost + * 63:n bits of \'7bBAR5,BAR4\'7d to 1. IO Space BAR 0] = IO Space Indicat + * or (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits + * of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in byt + * es.; EP=0xFFF0; RP=0xFFF0 + * PSU_PCIE_ATTRIB_ATTR_16_ATTR_BAR4 0xFFF0 + + * ATTR_16 + * (OFFSET, MASK, VALUE) (0XFD480040, 0x0000FFFFU ,0x0000FFF0U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_16_OFFSET, 0x0000FFFFU, 0x0000FFF0U); +/*##################################################################### */ + + /* + * Register : ATTR_17 @ 0XFD480044 + + * For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 5 if BAR4 is a 32-bit BAR, or the upper bits of \'7bBAR5,BAR4\'7d if BA + * R4 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR4 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root, this must be set to: 0000_00 + * 00 = Prefetchable Memory Limit/Base Registers not implemented FFF0_FFF0 + * = 32-bit Prefetchable Memory Limit/Base implemented FFF1_FFF1 = 64-bit P + * refetchable Memory Limit/Base implemented For an endpoint, bits are defi + * ned as follows: Memory Space BAR (not upper bits of BAR4) [0] = Mem Spac + * e Indicator (set to 0) [2:1] = Type field (00 for 32-bit; BAR5 cannot be + * lower part of a 64-bit BAR) [3] = Prefetchable (0 or 1) [31:4] = Mask f + * or writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=memory + * aperture size in bytes. IO Space BAR 0] = IO Space Indicator (set to 1) + * [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set up + * permost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF + * ; RP=0xFFF1 + * PSU_PCIE_ATTRIB_ATTR_17_ATTR_BAR5 0xFFF1 + + * ATTR_17 + * (OFFSET, MASK, VALUE) (0XFD480044, 0x0000FFFFU ,0x0000FFF1U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_17_OFFSET, 0x0000FFFFU, 0x0000FFF1U); +/*##################################################################### */ + + /* + * Register : ATTR_18 @ 0XFD480048 + + * For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 5 if BAR4 is a 32-bit BAR, or the upper bits of \'7bBAR5,BAR4\'7d if BA + * R4 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR4 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root, this must be set to: 0000_00 + * 00 = Prefetchable Memory Limit/Base Registers not implemented FFF0_FFF0 + * = 32-bit Prefetchable Memory Limit/Base implemented FFF1_FFF1 = 64-bit P + * refetchable Memory Limit/Base implemented For an endpoint, bits are defi + * ned as follows: Memory Space BAR (not upper bits of BAR4) [0] = Mem Spac + * e Indicator (set to 0) [2:1] = Type field (00 for 32-bit; BAR5 cannot be + * lower part of a 64-bit BAR) [3] = Prefetchable (0 or 1) [31:4] = Mask f + * or writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=memory + * aperture size in bytes. IO Space BAR 0] = IO Space Indicator (set to 1) + * [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set up + * permost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF + * ; RP=0xFFF1 + * PSU_PCIE_ATTRIB_ATTR_18_ATTR_BAR5 0xFFF1 + + * ATTR_18 + * (OFFSET, MASK, VALUE) (0XFD480048, 0x0000FFFFU ,0x0000FFF1U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_18_OFFSET, 0x0000FFFFU, 0x0000FFF1U); +/*##################################################################### */ + + /* + * Register : ATTR_27 @ 0XFD48006C + + * Specifies maximum payload supported. Valid settings are: 0- 128 bytes, 1 + * - 256 bytes, 2- 512 bytes, 3- 1024 bytes. Transferred to the Device Capa + * bilities register. The values: 4-2048 bytes, 5- 4096 bytes are not suppo + * rted; EP=0x0001; RP=0x0001 + * PSU_PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED 1 + + * Endpoint L1 Acceptable Latency. Records the latency that the endpoint ca + * n withstand on transitions from L1 state to L0 (if L1 state supported). + * Valid settings are: 0h less than 1us, 1h 1 to 2us, 2h 2 to 4us, 3h 4 to + * 8us, 4h 8 to 16us, 5h 16 to 32us, 6h 32 to 64us, 7h more than 64us. For + * Endpoints only. Must be 0h for other devices.; EP=0x0007; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY 0x0 + + * ATTR_27 + * (OFFSET, MASK, VALUE) (0XFD48006C, 0x00000738U ,0x00000100U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_27_OFFSET, 0x00000738U, 0x00000100U); +/*##################################################################### */ + + /* + * Register : ATTR_50 @ 0XFD4800C8 + + * Identifies the type of device/port as follows: 0000b PCI Express Endpoin + * t device, 0001b Legacy PCI Express Endpoint device, 0100b Root Port of P + * CI Express Root Complex, 0101b Upstream Port of PCI Express Switch, 0110 + * b Downstream Port of PCI Express Switch, 0111b PCIE Express to PCI/PCI-X + * Bridge, 1000b PCI/PCI-X to PCI Express Bridge. Transferred to PCI Expre + * ss Capabilities register. Must be consistent with IS_SWITCH and UPSTREAM + * _FACING settings.; EP=0x0000; RP=0x0004 + * PSU_PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE 4 + + * PCIe Capability's Next Capability Offset pointer to the next item in the + * capabilities list, or 00h if this is the final capability.; EP=0x009C; + * RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR 0 + + * ATTR_50 + * (OFFSET, MASK, VALUE) (0XFD4800C8, 0x0000FFF0U ,0x00000040U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_50_OFFSET, 0x0000FFF0U, 0x00000040U); +/*##################################################################### */ + + /* + * Register : ATTR_105 @ 0XFD4801A4 + + * Number of credits that should be advertised for Completion data received + * on Virtual Channel 0. The bytes advertised must be less than or equal t + * o the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0172; RP=0x00CD + * PSU_PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD 0xCD + + * ATTR_105 + * (OFFSET, MASK, VALUE) (0XFD4801A4, 0x000007FFU ,0x000000CDU) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_105_OFFSET, + 0x000007FFU, 0x000000CDU); +/*##################################################################### */ + + /* + * Register : ATTR_106 @ 0XFD4801A8 + + * Number of credits that should be advertised for Completion headers recei + * ved on Virtual Channel 0. The sum of the posted, non posted, and complet + * ion header credits must be <= 80; EP=0x0048; RP=0x0024 + * PSU_PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH 0x24 + + * Number of credits that should be advertised for Non-Posted headers recei + * ved on Virtual Channel 0. The number of non posted data credits advertis + * ed by the block is equal to the number of non posted header credits. The + * sum of the posted, non posted, and completion header credits must be <= + * 80; EP=0x0004; RP=0x000C + * PSU_PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH 0xC + + * ATTR_106 + * (OFFSET, MASK, VALUE) (0XFD4801A8, 0x00003FFFU ,0x00000624U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_106_OFFSET, + 0x00003FFFU, 0x00000624U); +/*##################################################################### */ + + /* + * Register : ATTR_107 @ 0XFD4801AC + + * Number of credits that should be advertised for Non-Posted data received + * on Virtual Channel 0. The number of non posted data credits advertised + * by the block is equal to two times the number of non posted header credi + * ts if atomic operations are supported or is equal to the number of non p + * osted header credits if atomic operations are not supported. The bytes a + * dvertised must be less than or equal to the bram bytes available. See VC + * 0_RX_RAM_LIMIT; EP=0x0008; RP=0x0018 + * PSU_PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD 0x18 + + * ATTR_107 + * (OFFSET, MASK, VALUE) (0XFD4801AC, 0x000007FFU ,0x00000018U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_107_OFFSET, + 0x000007FFU, 0x00000018U); +/*##################################################################### */ + + /* + * Register : ATTR_108 @ 0XFD4801B0 + + * Number of credits that should be advertised for Posted data received on + * Virtual Channel 0. The bytes advertised must be less than or equal to th + * e bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0020; RP=0x00B5 + * PSU_PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD 0xB5 + + * ATTR_108 + * (OFFSET, MASK, VALUE) (0XFD4801B0, 0x000007FFU ,0x000000B5U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_108_OFFSET, + 0x000007FFU, 0x000000B5U); +/*##################################################################### */ + + /* + * Register : ATTR_109 @ 0XFD4801B4 + + * Not currently in use. Invert ECRC generated by block when trn_tecrc_gen_ + * n and trn_terrfwd_n are asserted.; EP=0x0000; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV 0x0 + + * Enables td bit clear and ECRC trim on received TLP's FALSE == don't trim + * TRUE == trim.; EP=0x0001; RP=0x0001 + * PSU_PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM 0x1 + + * Enables ECRC check on received TLP's 0 == don't check 1 == always check + * 3 == check if enabled by ECRC check enable bit of AER cap structure; EP= + * 0x0003; RP=0x0003 + * PSU_PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK 0x3 + + * Index of last packet buffer used by TX TLM (i.e. number of buffers - 1). + * Calculated from max payload size supported and the number of brams conf + * igured for transmit; EP=0x001C; RP=0x001C + * PSU_PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET 0x1c + + * Number of credits that should be advertised for Posted headers received + * on Virtual Channel 0. The sum of the posted, non posted, and completion + * header credits must be <= 80; EP=0x0004; RP=0x0020 + * PSU_PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH 0x20 + + * ATTR_109 + * (OFFSET, MASK, VALUE) (0XFD4801B4, 0x0000FFFFU ,0x00007E20U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_109_OFFSET, + 0x0000FFFFU, 0x00007E20U); +/*##################################################################### */ + + /* + * Register : ATTR_34 @ 0XFD480088 + + * Specifies values to be transferred to Header Type register. Bit 7 should + * be set to '0' indicating single-function device. Bit 0 identifies heade + * r as Type 0 or Type 1, with '0' indicating a Type 0 header.; EP=0x0000; + * RP=0x0001 + * PSU_PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE 0x1 + + * ATTR_34 + * (OFFSET, MASK, VALUE) (0XFD480088, 0x000000FFU ,0x00000001U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_34_OFFSET, 0x000000FFU, 0x00000001U); +/*##################################################################### */ + + /* + * Register : ATTR_53 @ 0XFD4800D4 + + * PM Capability's Next Capability Offset pointer to the next item in the c + * apabilities list, or 00h if this is the final capability.; EP=0x0048; RP + * =0x0060 + * PSU_PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR 0x60 + + * ATTR_53 + * (OFFSET, MASK, VALUE) (0XFD4800D4, 0x000000FFU ,0x00000060U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_53_OFFSET, 0x000000FFU, 0x00000060U); +/*##################################################################### */ + + /* + * Register : ATTR_41 @ 0XFD4800A4 + + * MSI Per-Vector Masking Capable. The value is transferred to the MSI Cont + * rol Register[8]. When set, adds Mask and Pending Dword to Cap structure; + * EP=0x0000; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE 0x0 + + * Indicates that the MSI structures exists. If this is FALSE, then the MSI + * structure cannot be accessed via either the link or the management port + * .; EP=0x0001; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON 0 + + * MSI Capability's Next Capability Offset pointer to the next item in the + * capabilities list, or 00h if this is the final capability.; EP=0x0060; R + * P=0x0000 + * PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR 0x0 + + * Indicates that the MSI structures exists. If this is FALSE, then the MSI + * structure cannot be accessed via either the link or the management port + * .; EP=0x0001; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON 0 + + * ATTR_41 + * (OFFSET, MASK, VALUE) (0XFD4800A4, 0x000003FFU ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_41_OFFSET, 0x000003FFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_97 @ 0XFD480184 + + * Maximum Link Width. Valid settings are: 000001b x1, 000010b x2, 000100b + * x4, 001000b x8.; EP=0x0004; RP=0x0004 + * PSU_PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH 0x1 + + * Used by LTSSM to set Maximum Link Width. Valid settings are: 000001b [x1 + * ], 000010b [x2], 000100b [x4], 001000b [x8].; EP=0x0004; RP=0x0004 + * PSU_PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH 0x1 + + * ATTR_97 + * (OFFSET, MASK, VALUE) (0XFD480184, 0x00000FFFU ,0x00000041U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_97_OFFSET, 0x00000FFFU, 0x00000041U); +/*##################################################################### */ + + /* + * Register : ATTR_100 @ 0XFD480190 + + * TRUE specifies upstream-facing port. FALSE specifies downstream-facing p + * ort.; EP=0x0001; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING 0x0 + + * ATTR_100 + * (OFFSET, MASK, VALUE) (0XFD480190, 0x00000040U ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_100_OFFSET, + 0x00000040U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_101 @ 0XFD480194 + + * Enable the routing of message TLPs to the user through the TRN RX interf + * ace. A bit value of 1 enables routing of the message TLP to the user. Me + * ssages are always decoded by the message decoder. Bit 0 - ERR COR, Bit 1 + * - ERR NONFATAL, Bit 2 - ERR FATAL, Bit 3 - INTA Bit 4 - INTB, Bit 5 - I + * NTC, Bit 6 - INTD, Bit 7 PM_PME, Bit 8 - PME_TO_ACK, Bit 9 - unlock, Bit + * 10 PME_Turn_Off; EP=0x0000; RP=0x07FF + * PSU_PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE 0x7FF + + * Disable BAR filtering. Does not change the behavior of the bar hit outpu + * ts; EP=0x0000; RP=0x0001 + * PSU_PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING 0x1 + + * ATTR_101 + * (OFFSET, MASK, VALUE) (0XFD480194, 0x0000FFE2U ,0x0000FFE2U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_101_OFFSET, + 0x0000FFE2U, 0x0000FFE2U); +/*##################################################################### */ + + /* + * Register : ATTR_37 @ 0XFD480094 + + * Link Bandwidth notification capability. Indicates support for the link b + * andwidth notification status and interrupt mechanism. Required for Root. + * ; EP=0x0000; RP=0x0001 + * PSU_PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP 0x1 + + * Sets the ASPM Optionality Compliance bit, to comply with the 2.1 ASPM Op + * tionality ECN. Transferred to the Link Capabilities register.; EP=0x0001 + * ; RP=0x0001 + * PSU_PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY 0x1 + + * ATTR_37 + * (OFFSET, MASK, VALUE) (0XFD480094, 0x00004200U ,0x00004200U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_37_OFFSET, 0x00004200U, 0x00004200U); +/*##################################################################### */ + + /* + * Register : ATTR_93 @ 0XFD480174 + + * Enables the Replay Timer to use the user-defined LL_REPLAY_TIMEOUT value + * (or combined with the built-in value, depending on LL_REPLAY_TIMEOUT_FU + * NC). If FALSE, the built-in value is used.; EP=0x0000; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN 0x1 + + * Sets a user-defined timeout for the Replay Timer to force cause the retr + * ansmission of unacknowledged TLPs; refer to LL_REPLAY_TIMEOUT_EN and LL_ + * REPLAY_TIMEOUT_FUNC to see how this value is used. The unit for this att + * ribute is in symbol times, which is 4ns at GEN1 speeds and 2ns at GEN2.; + * EP=0x0000; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT 0x1000 + + * ATTR_93 + * (OFFSET, MASK, VALUE) (0XFD480174, 0x0000FFFFU ,0x00009000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_93_OFFSET, 0x0000FFFFU, 0x00009000U); +/*##################################################################### */ + + /* + * Register : ID @ 0XFD480200 + + * Device ID for the the PCIe Cap Structure Device ID field + * PSU_PCIE_ATTRIB_ID_CFG_DEV_ID 0xd021 + + * Vendor ID for the PCIe Cap Structure Vendor ID field + * PSU_PCIE_ATTRIB_ID_CFG_VEND_ID 0x10ee + + * ID + * (OFFSET, MASK, VALUE) (0XFD480200, 0xFFFFFFFFU ,0x10EED021U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ID_OFFSET, 0xFFFFFFFFU, 0x10EED021U); +/*##################################################################### */ + + /* + * Register : SUBSYS_ID @ 0XFD480204 + + * Subsystem ID for the the PCIe Cap Structure Subsystem ID field + * PSU_PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID 0x7 + + * Subsystem Vendor ID for the PCIe Cap Structure Subsystem Vendor ID field + * PSU_PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID 0x10ee + + * SUBSYS_ID + * (OFFSET, MASK, VALUE) (0XFD480204, 0xFFFFFFFFU ,0x10EE0007U) + */ + PSU_Mask_Write(PCIE_ATTRIB_SUBSYS_ID_OFFSET, + 0xFFFFFFFFU, 0x10EE0007U); +/*##################################################################### */ + + /* + * Register : REV_ID @ 0XFD480208 + + * Revision ID for the the PCIe Cap Structure + * PSU_PCIE_ATTRIB_REV_ID_CFG_REV_ID 0x0 + + * REV_ID + * (OFFSET, MASK, VALUE) (0XFD480208, 0x000000FFU ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_REV_ID_OFFSET, 0x000000FFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_24 @ 0XFD480060 + + * Code identifying basic function, subclass and applicable programming int + * erface. Transferred to the Class Code register.; EP=0x8000; RP=0x8000 + * PSU_PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE 0x400 + + * ATTR_24 + * (OFFSET, MASK, VALUE) (0XFD480060, 0x0000FFFFU ,0x00000400U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_24_OFFSET, 0x0000FFFFU, 0x00000400U); +/*##################################################################### */ + + /* + * Register : ATTR_25 @ 0XFD480064 + + * Code identifying basic function, subclass and applicable programming int + * erface. Transferred to the Class Code register.; EP=0x0005; RP=0x0006 + * PSU_PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE 0x6 + + * INTX Interrupt Generation Capable. If FALSE, this will cause Command[10] + * to be hardwired to 0.; EP=0x0001; RP=0x0001 + * PSU_PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED 0 + + * ATTR_25 + * (OFFSET, MASK, VALUE) (0XFD480064, 0x000001FFU ,0x00000006U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_25_OFFSET, 0x000001FFU, 0x00000006U); +/*##################################################################### */ + + /* + * Register : ATTR_4 @ 0XFD480010 + + * Indicates that the AER structures exists. If this is FALSE, then the AER + * structure cannot be accessed via either the link or the management port + * , and AER will be considered to not be present for error management task + * s (such as what types of error messages are sent if an error is detected + * ).; EP=0x0001; RP=0x0001 + * PSU_PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON 0 + + * Indicates that the AER structures exists. If this is FALSE, then the AER + * structure cannot be accessed via either the link or the management port + * , and AER will be considered to not be present for error management task + * s (such as what types of error messages are sent if an error is detected + * ).; EP=0x0001; RP=0x0001 + * PSU_PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON 0 + + * ATTR_4 + * (OFFSET, MASK, VALUE) (0XFD480010, 0x00001000U ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_4_OFFSET, 0x00001000U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_89 @ 0XFD480164 + + * VSEC's Next Capability Offset pointer to the next item in the capabiliti + * es list, or 000h if this is the final capability.; EP=0x0140; RP=0x0140 + * PSU_PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR 0 + + * ATTR_89 + * (OFFSET, MASK, VALUE) (0XFD480164, 0x00001FFEU ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_89_OFFSET, 0x00001FFEU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_79 @ 0XFD48013C + + * CRS SW Visibility. Indicates RC can return CRS to SW. Transferred to the + * Root Capabilities register.; EP=0x0000; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY 1 + + * ATTR_79 + * (OFFSET, MASK, VALUE) (0XFD48013C, 0x00000020U ,0x00000020U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_79_OFFSET, 0x00000020U, 0x00000020U); +/*##################################################################### */ + + /* + * Register : ATTR_43 @ 0XFD4800AC + + * Indicates that the MSIX structures exists. If this is FALSE, then the MS + * IX structure cannot be accessed via either the link or the management po + * rt.; EP=0x0001; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON 0 + + * ATTR_43 + * (OFFSET, MASK, VALUE) (0XFD4800AC, 0x00000100U ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_43_OFFSET, 0x00000100U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_48 @ 0XFD4800C0 + + * MSI-X Table Size. This value is transferred to the MSI-X Message Control + * [10:0] field. Set to 0 if MSI-X is not enabled. Note that the core does + * not implement the table; that must be implemented in user logic.; EP=0x0 + * 003; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE 0 + + * ATTR_48 + * (OFFSET, MASK, VALUE) (0XFD4800C0, 0x000007FFU ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_48_OFFSET, 0x000007FFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_46 @ 0XFD4800B8 + + * MSI-X Table Offset. This value is transferred to the MSI-X Table Offset + * field. Set to 0 if MSI-X is not enabled.; EP=0x0001; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET 0 + + * ATTR_46 + * (OFFSET, MASK, VALUE) (0XFD4800B8, 0x0000FFFFU ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_46_OFFSET, 0x0000FFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_47 @ 0XFD4800BC + + * MSI-X Table Offset. This value is transferred to the MSI-X Table Offset + * field. Set to 0 if MSI-X is not enabled.; EP=0x0000; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET 0 + + * ATTR_47 + * (OFFSET, MASK, VALUE) (0XFD4800BC, 0x00001FFFU ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_47_OFFSET, 0x00001FFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_44 @ 0XFD4800B0 + + * MSI-X Pending Bit Array Offset This value is transferred to the MSI-X PB + * A Offset field. Set to 0 if MSI-X is not enabled.; EP=0x0001; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET 0 + + * ATTR_44 + * (OFFSET, MASK, VALUE) (0XFD4800B0, 0x0000FFFFU ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_44_OFFSET, 0x0000FFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_45 @ 0XFD4800B4 + + * MSI-X Pending Bit Array Offset This value is transferred to the MSI-X PB + * A Offset field. Set to 0 if MSI-X is not enabled.; EP=0x1000; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET 0 + + * ATTR_45 + * (OFFSET, MASK, VALUE) (0XFD4800B4, 0x0000FFF8U ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_45_OFFSET, 0x0000FFF8U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : CB @ 0XFD48031C + + * DT837748 Enable + * PSU_PCIE_ATTRIB_CB_CB1 0x0 + + * ECO Register 1 + * (OFFSET, MASK, VALUE) (0XFD48031C, 0x00000002U ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_CB_OFFSET, 0x00000002U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_35 @ 0XFD48008C + + * Active State PM Support. Indicates the level of active state power manag + * ement supported by the selected PCI Express Link, encoded as follows: 0 + * Reserved, 1 L0s entry supported, 2 Reserved, 3 L0s and L1 entry supporte + * d.; EP=0x0001; RP=0x0001 + * PSU_PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT 0x0 + + * ATTR_35 + * (OFFSET, MASK, VALUE) (0XFD48008C, 0x00003000U ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_35_OFFSET, 0x00003000U, 0x00000000U); +/*##################################################################### */ + + /* + * PUTTING PCIE CONTROL IN RESET + */ + /* + * Register : RST_FPD_TOP @ 0XFD1A0100 + + * PCIE control block level reset + * PSU_CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET 0X0 + + * FPD Block level software controlled reset + * (OFFSET, MASK, VALUE) (0XFD1A0100, 0x00020000U ,0x00000000U) + */ + PSU_Mask_Write(CRF_APB_RST_FPD_TOP_OFFSET, 0x00020000U, 0x00000000U); +/*##################################################################### */ + + /* + * PCIE GPIO RESET + */ + /* + * MASK_DATA_0_LSW LOW BANK [15:0] + */ + /* + * MASK_DATA_0_MSW LOW BANK [25:16] + */ + /* + * MASK_DATA_1_LSW LOW BANK [41:26] + */ + /* + * Register : MASK_DATA_1_LSW @ 0XFF0A0008 + + * Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW] + * PSU_GPIO_MASK_DATA_1_LSW_MASK_1_LSW 0xffdf + + * Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW] + * PSU_GPIO_MASK_DATA_1_LSW_DATA_1_LSW 0x20 + + * Maskable Output Data (GPIO Bank1, MIO, Lower 16bits) + * (OFFSET, MASK, VALUE) (0XFF0A0008, 0xFFFFFFFFU ,0xFFDF0020U) + */ + PSU_Mask_Write(GPIO_MASK_DATA_1_LSW_OFFSET, + 0xFFFFFFFFU, 0xFFDF0020U); +/*##################################################################### */ + + /* + * MASK_DATA_1_MSW HIGH BANK [51:42] + */ + /* + * MASK_DATA_1_LSW HIGH BANK [67:52] + */ + /* + * MASK_DATA_1_LSW HIGH BANK [77:68] + */ + /* + * CHECK PLL LOCK FOR LANE0 + */ + /* + * Register : L0_PLL_STATUS_READ_1 @ 0XFD4023E4 + + * Status Read value of PLL Lock + * PSU_SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1 + * (OFFSET, MASK, VALUE) (0XFD4023E4, 0x00000010U ,0x00000010U) + */ + mask_poll(SERDES_L0_PLL_STATUS_READ_1_OFFSET, 0x00000010U); + +/*##################################################################### */ + + /* + * CHECK PLL LOCK FOR LANE1 + */ + /* + * Register : L1_PLL_STATUS_READ_1 @ 0XFD4063E4 + + * Status Read value of PLL Lock + * PSU_SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1 + * (OFFSET, MASK, VALUE) (0XFD4063E4, 0x00000010U ,0x00000010U) + */ + mask_poll(SERDES_L1_PLL_STATUS_READ_1_OFFSET, 0x00000010U); + +/*##################################################################### */ + + /* + * CHECK PLL LOCK FOR LANE2 + */ + /* + * Register : L2_PLL_STATUS_READ_1 @ 0XFD40A3E4 + + * Status Read value of PLL Lock + * PSU_SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1 + * (OFFSET, MASK, VALUE) (0XFD40A3E4, 0x00000010U ,0x00000010U) + */ + mask_poll(SERDES_L2_PLL_STATUS_READ_1_OFFSET, 0x00000010U); + +/*##################################################################### */ + + /* + * CHECK PLL LOCK FOR LANE3 + */ + /* + * Register : L3_PLL_STATUS_READ_1 @ 0XFD40E3E4 + + * Status Read value of PLL Lock + * PSU_SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1 + * (OFFSET, MASK, VALUE) (0XFD40E3E4, 0x00000010U ,0x00000010U) + */ + mask_poll(SERDES_L3_PLL_STATUS_READ_1_OFFSET, 0x00000010U); + +/*##################################################################### */ + + /* + * SATA AHCI VENDOR SETTING + */ + /* + * Register : PP2C @ 0XFD0C00AC + + * CIBGMN: COMINIT Burst Gap Minimum. + * PSU_SATA_AHCI_VENDOR_PP2C_CIBGMN 0x18 + + * CIBGMX: COMINIT Burst Gap Maximum. + * PSU_SATA_AHCI_VENDOR_PP2C_CIBGMX 0x40 + + * CIBGN: COMINIT Burst Gap Nominal. + * PSU_SATA_AHCI_VENDOR_PP2C_CIBGN 0x18 + + * CINMP: COMINIT Negate Minimum Period. + * PSU_SATA_AHCI_VENDOR_PP2C_CINMP 0x28 + + * PP2C - Port Phy2Cfg Register. This register controls the configuration o + * f the Phy Control OOB timing for the COMINIT parameters for either Port + * 0 or Port 1. The Port configured is controlled by the value programmed i + * nto the Port Config Register. + * (OFFSET, MASK, VALUE) (0XFD0C00AC, 0xFFFFFFFFU ,0x28184018U) + */ + PSU_Mask_Write(SATA_AHCI_VENDOR_PP2C_OFFSET, + 0xFFFFFFFFU, 0x28184018U); +/*##################################################################### */ + + /* + * Register : PP3C @ 0XFD0C00B0 + + * CWBGMN: COMWAKE Burst Gap Minimum. + * PSU_SATA_AHCI_VENDOR_PP3C_CWBGMN 0x06 + + * CWBGMX: COMWAKE Burst Gap Maximum. + * PSU_SATA_AHCI_VENDOR_PP3C_CWBGMX 0x14 + + * CWBGN: COMWAKE Burst Gap Nominal. + * PSU_SATA_AHCI_VENDOR_PP3C_CWBGN 0x08 + + * CWNMP: COMWAKE Negate Minimum Period. + * PSU_SATA_AHCI_VENDOR_PP3C_CWNMP 0x0E + + * PP3C - Port Phy3CfgRegister. This register controls the configuration of + * the Phy Control OOB timing for the COMWAKE parameters for either Port 0 + * or Port 1. The Port configured is controlled by the value programmed in + * to the Port Config Register. + * (OFFSET, MASK, VALUE) (0XFD0C00B0, 0xFFFFFFFFU ,0x0E081406U) + */ + PSU_Mask_Write(SATA_AHCI_VENDOR_PP3C_OFFSET, + 0xFFFFFFFFU, 0x0E081406U); +/*##################################################################### */ + + /* + * Register : PP4C @ 0XFD0C00B4 + + * BMX: COM Burst Maximum. + * PSU_SATA_AHCI_VENDOR_PP4C_BMX 0x13 + + * BNM: COM Burst Nominal. + * PSU_SATA_AHCI_VENDOR_PP4C_BNM 0x08 + + * SFD: Signal Failure Detection, if the signal detection de-asserts for a + * time greater than this then the OOB detector will determine this is a li + * ne idle and cause the PhyInit state machine to exit the Phy Ready State. + * A value of zero disables the Signal Failure Detector. The value is base + * d on the OOB Detector Clock typically (PMCLK Clock Period) * SFD giving + * a nominal time of 500ns based on a 150MHz PMCLK. + * PSU_SATA_AHCI_VENDOR_PP4C_SFD 0x4A + + * PTST: Partial to Slumber timer value, specific delay the controller shou + * ld apply while in partial before entering slumber. The value is bases on + * the system clock divided by 128, total delay = (Sys Clock Period) * PTS + * T * 128 + * PSU_SATA_AHCI_VENDOR_PP4C_PTST 0x06 + + * PP4C - Port Phy4Cfg Register. This register controls the configuration o + * f the Phy Control Burst timing for the COM parameters for either Port 0 + * or Port 1. The Port configured is controlled by the value programmed int + * o the Port Config Register. + * (OFFSET, MASK, VALUE) (0XFD0C00B4, 0xFFFFFFFFU ,0x064A0813U) + */ + PSU_Mask_Write(SATA_AHCI_VENDOR_PP4C_OFFSET, + 0xFFFFFFFFU, 0x064A0813U); +/*##################################################################### */ + + /* + * Register : PP5C @ 0XFD0C00B8 + + * RIT: Retry Interval Timer. The calculated value divided by two, the lowe + * r digit of precision is not needed. + * PSU_SATA_AHCI_VENDOR_PP5C_RIT 0xC96A4 + + * RCT: Rate Change Timer, a value based on the 54.2us for which a SATA dev + * ice will transmit at a fixed rate ALIGNp after OOB has completed, for a + * fast SERDES it is suggested that this value be 54.2us / 4 + * PSU_SATA_AHCI_VENDOR_PP5C_RCT 0x3FF + + * PP5C - Port Phy5Cfg Register. This register controls the configuration o + * f the Phy Control Retry Interval timing for either Port 0 or Port 1. The + * Port configured is controlled by the value programmed into the Port Con + * fig Register. + * (OFFSET, MASK, VALUE) (0XFD0C00B8, 0xFFFFFFFFU ,0x3FFC96A4U) + */ + PSU_Mask_Write(SATA_AHCI_VENDOR_PP5C_OFFSET, + 0xFFFFFFFFU, 0x3FFC96A4U); +/*##################################################################### */ - return 1; + return 1; } -unsigned long psu_ps_pl_isolation_removal_data() { - // : PS-PL POWER UP REQUEST - /*Register : REQ_PWRUP_INT_EN @ 0XFFD80118

+unsigned long psu_resetin_init_data(void) +{ + /* + * PUTTING SERDES PERIPHERAL IN RESET + */ + /* + * PUTTING USB0 IN RESET + */ + /* + * Register : RST_LPD_TOP @ 0XFF5E023C - Power-up Request Interrupt Enable for PL - PSU_PMU_GLOBAL_REQ_PWRUP_INT_EN_PL 1 + * USB 0 reset for control registers + * PSU_CRL_APB_RST_LPD_TOP_USB0_APB_RESET 0X1 - Power-up Request Interrupt Enable Register. Writing a 1 to this location will unmask the interrupt. - (OFFSET, MASK, VALUE) (0XFFD80118, 0x00800000U ,0x00800000U) - RegMask = (PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_MASK | 0 ); + * USB 0 sleep circuit reset + * PSU_CRL_APB_RST_LPD_TOP_USB0_HIBERRESET 0X1 - RegVal = ((0x00000001U << PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PMU_GLOBAL_REQ_PWRUP_INT_EN_OFFSET ,0x00800000U ,0x00800000U); - /*############################################################################################################################ */ + * USB 0 reset + * PSU_CRL_APB_RST_LPD_TOP_USB0_CORERESET 0X1 - /*Register : REQ_PWRUP_TRIG @ 0XFFD80120

+ * Software control register for the LPD block. + * (OFFSET, MASK, VALUE) (0XFF5E023C, 0x00000540U ,0x00000540U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_TOP_OFFSET, 0x00000540U, 0x00000540U); +/*##################################################################### */ - Power-up Request Trigger for PL - PSU_PMU_GLOBAL_REQ_PWRUP_TRIG_PL 1 + /* + * PUTTING GEM0 IN RESET + */ + /* + * Register : RST_LPD_IOU0 @ 0XFF5E0230 - Power-up Request Trigger Register. A write of one to this location will generate a power-up request to the PMU. - (OFFSET, MASK, VALUE) (0XFFD80120, 0x00800000U ,0x00800000U) - RegMask = (PMU_GLOBAL_REQ_PWRUP_TRIG_PL_MASK | 0 ); + * GEM 3 reset + * PSU_CRL_APB_RST_LPD_IOU0_GEM3_RESET 0X1 - RegVal = ((0x00000001U << PMU_GLOBAL_REQ_PWRUP_TRIG_PL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PMU_GLOBAL_REQ_PWRUP_TRIG_OFFSET ,0x00800000U ,0x00800000U); - /*############################################################################################################################ */ + * Software controlled reset for the GEMs + * (OFFSET, MASK, VALUE) (0XFF5E0230, 0x00000008U ,0x00000008U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_IOU0_OFFSET, + 0x00000008U, 0x00000008U); +/*##################################################################### */ - // : POLL ON PL POWER STATUS - /*Register : REQ_PWRUP_STATUS @ 0XFFD80110

+ /* + * PUTTING SATA IN RESET + */ + /* + * Register : RST_FPD_TOP @ 0XFD1A0100 - Power-up Request Status for PL - PSU_PMU_GLOBAL_REQ_PWRUP_STATUS_PL 1 - (OFFSET, MASK, VALUE) (0XFFD80110, 0x00800000U ,0x00000000U) */ - mask_pollOnValue(PMU_GLOBAL_REQ_PWRUP_STATUS_OFFSET,0x00800000U,0x00000000U); + * Sata block level reset + * PSU_CRF_APB_RST_FPD_TOP_SATA_RESET 0X1 - /*############################################################################################################################ */ + * FPD Block level software controlled reset + * (OFFSET, MASK, VALUE) (0XFD1A0100, 0x00000002U ,0x00000002U) + */ + PSU_Mask_Write(CRF_APB_RST_FPD_TOP_OFFSET, 0x00000002U, 0x00000002U); +/*##################################################################### */ + + /* + * PUTTING PCIE IN RESET + */ + /* + * Register : RST_FPD_TOP @ 0XFD1A0100 + + * PCIE config reset + * PSU_CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET 0X1 + + * PCIE control block level reset + * PSU_CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET 0X1 + + * PCIE bridge block level reset (AXI interface) + * PSU_CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET 0X1 + + * FPD Block level software controlled reset + * (OFFSET, MASK, VALUE) (0XFD1A0100, 0x000E0000U ,0x000E0000U) + */ + PSU_Mask_Write(CRF_APB_RST_FPD_TOP_OFFSET, 0x000E0000U, 0x000E0000U); +/*##################################################################### */ + + /* + * PUTTING DP IN RESET + */ + /* + * Register : DP_TX_PHY_POWER_DOWN @ 0XFD4A0238 + + * Two bits per lane. When set to 11, moves the GT to power down mode. When + * set to 00, GT will be in active state. bits [1:0] - lane0 Bits [3:2] - + * lane 1 + * PSU_DP_DP_TX_PHY_POWER_DOWN_POWER_DWN 0XA + + * Control PHY Power down + * (OFFSET, MASK, VALUE) (0XFD4A0238, 0x0000000FU ,0x0000000AU) + */ + PSU_Mask_Write(DP_DP_TX_PHY_POWER_DOWN_OFFSET, + 0x0000000FU, 0x0000000AU); +/*##################################################################### */ + + /* + * Register : DP_PHY_RESET @ 0XFD4A0200 + + * Set to '1' to hold the GT in reset. Clear to release. + * PSU_DP_DP_PHY_RESET_GT_RESET 0X1 + + * Reset the transmitter PHY. + * (OFFSET, MASK, VALUE) (0XFD4A0200, 0x00000002U ,0x00000002U) + */ + PSU_Mask_Write(DP_DP_PHY_RESET_OFFSET, 0x00000002U, 0x00000002U); +/*##################################################################### */ + + /* + * Register : RST_FPD_TOP @ 0XFD1A0100 + + * Display Port block level reset (includes DPDMA) + * PSU_CRF_APB_RST_FPD_TOP_DP_RESET 0X1 + + * FPD Block level software controlled reset + * (OFFSET, MASK, VALUE) (0XFD1A0100, 0x00010000U ,0x00010000U) + */ + PSU_Mask_Write(CRF_APB_RST_FPD_TOP_OFFSET, 0x00010000U, 0x00010000U); +/*##################################################################### */ - return 1; + return 1; } -unsigned long psu_ps_pl_reset_config_data() { - // : PS PL RESET SEQUENCE - // : FABRIC RESET USING EMIO - /*Register : MASK_DATA_5_MSW @ 0XFF0A002C

+unsigned long psu_ps_pl_isolation_removal_data(void) +{ + /* + * PS-PL POWER UP REQUEST + */ + /* + * Register : REQ_PWRUP_INT_EN @ 0XFFD80118 - Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW] - PSU_GPIO_MASK_DATA_5_MSW_MASK_5_MSW 0x8000 + * Power-up Request Interrupt Enable for PL + * PSU_PMU_GLOBAL_REQ_PWRUP_INT_EN_PL 1 - Maskable Output Data (GPIO Bank5, EMIO, Upper 16bits) - (OFFSET, MASK, VALUE) (0XFF0A002C, 0xFFFF0000U ,0x80000000U) - RegMask = (GPIO_MASK_DATA_5_MSW_MASK_5_MSW_MASK | 0 ); + * Power-up Request Interrupt Enable Register. Writing a 1 to this location + * will unmask the interrupt. + * (OFFSET, MASK, VALUE) (0XFFD80118, 0x00800000U ,0x00800000U) + */ + PSU_Mask_Write(PMU_GLOBAL_REQ_PWRUP_INT_EN_OFFSET, + 0x00800000U, 0x00800000U); +/*##################################################################### */ - RegVal = ((0x00008000U << GPIO_MASK_DATA_5_MSW_MASK_5_MSW_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (GPIO_MASK_DATA_5_MSW_OFFSET ,0xFFFF0000U ,0x80000000U); - /*############################################################################################################################ */ + /* + * Register : REQ_PWRUP_TRIG @ 0XFFD80120 - /*Register : DIRM_5 @ 0XFF0A0344

+ * Power-up Request Trigger for PL + * PSU_PMU_GLOBAL_REQ_PWRUP_TRIG_PL 1 - Operation is the same as DIRM_0[DIRECTION_0] - PSU_GPIO_DIRM_5_DIRECTION_5 0x80000000 + * Power-up Request Trigger Register. A write of one to this location will + * generate a power-up request to the PMU. + * (OFFSET, MASK, VALUE) (0XFFD80120, 0x00800000U ,0x00800000U) + */ + PSU_Mask_Write(PMU_GLOBAL_REQ_PWRUP_TRIG_OFFSET, + 0x00800000U, 0x00800000U); +/*##################################################################### */ - Direction mode (GPIO Bank5, EMIO) - (OFFSET, MASK, VALUE) (0XFF0A0344, 0xFFFFFFFFU ,0x80000000U) - RegMask = (GPIO_DIRM_5_DIRECTION_5_MASK | 0 ); + /* + * POLL ON PL POWER STATUS + */ + /* + * Register : REQ_PWRUP_STATUS @ 0XFFD80110 - RegVal = ((0x80000000U << GPIO_DIRM_5_DIRECTION_5_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (GPIO_DIRM_5_OFFSET ,0xFFFFFFFFU ,0x80000000U); - /*############################################################################################################################ */ + * Power-up Request Status for PL + * PSU_PMU_GLOBAL_REQ_PWRUP_STATUS_PL 1 + * (OFFSET, MASK, VALUE) (0XFFD80110, 0x00800000U ,0x00000000U) + */ + mask_pollOnValue(PMU_GLOBAL_REQ_PWRUP_STATUS_OFFSET, + 0x00800000U, 0x00000000U); - /*Register : OEN_5 @ 0XFF0A0348

+/*##################################################################### */ - Operation is the same as OEN_0[OP_ENABLE_0] - PSU_GPIO_OEN_5_OP_ENABLE_5 0x80000000 - Output enable (GPIO Bank5, EMIO) - (OFFSET, MASK, VALUE) (0XFF0A0348, 0xFFFFFFFFU ,0x80000000U) - RegMask = (GPIO_OEN_5_OP_ENABLE_5_MASK | 0 ); + return 1; +} +unsigned long psu_afi_config(void) +{ + /* + * AFI RESET + */ + /* + * Register : RST_FPD_TOP @ 0XFD1A0100 - RegVal = ((0x80000000U << GPIO_OEN_5_OP_ENABLE_5_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (GPIO_OEN_5_OFFSET ,0xFFFFFFFFU ,0x80000000U); - /*############################################################################################################################ */ + * AF_FM0 block level reset + * PSU_CRF_APB_RST_FPD_TOP_AFI_FM0_RESET 0 - /*Register : DATA_5 @ 0XFF0A0054

+ * AF_FM1 block level reset + * PSU_CRF_APB_RST_FPD_TOP_AFI_FM1_RESET 0 - Output Data - PSU_GPIO_DATA_5_DATA_5 0x80000000 + * AF_FM2 block level reset + * PSU_CRF_APB_RST_FPD_TOP_AFI_FM2_RESET 0 - Output Data (GPIO Bank5, EMIO) - (OFFSET, MASK, VALUE) (0XFF0A0054, 0xFFFFFFFFU ,0x80000000U) - RegMask = (GPIO_DATA_5_DATA_5_MASK | 0 ); + * AF_FM3 block level reset + * PSU_CRF_APB_RST_FPD_TOP_AFI_FM3_RESET 0 - RegVal = ((0x80000000U << GPIO_DATA_5_DATA_5_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (GPIO_DATA_5_OFFSET ,0xFFFFFFFFU ,0x80000000U); - /*############################################################################################################################ */ + * AF_FM4 block level reset + * PSU_CRF_APB_RST_FPD_TOP_AFI_FM4_RESET 0 + + * AF_FM5 block level reset + * PSU_CRF_APB_RST_FPD_TOP_AFI_FM5_RESET 0 + + * FPD Block level software controlled reset + * (OFFSET, MASK, VALUE) (0XFD1A0100, 0x00001F80U ,0x00000000U) + */ + PSU_Mask_Write(CRF_APB_RST_FPD_TOP_OFFSET, 0x00001F80U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : RST_LPD_TOP @ 0XFF5E023C + + * AFI FM 6 + * PSU_CRL_APB_RST_LPD_TOP_AFI_FM6_RESET 0 + + * Software control register for the LPD block. + * (OFFSET, MASK, VALUE) (0XFF5E023C, 0x00080000U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_TOP_OFFSET, 0x00080000U, 0x00000000U); +/*##################################################################### */ + + /* + * AFIFM INTERFACE WIDTH + */ + /* + * Register : afi_fs @ 0XFD615000 + + * Select the 32/64/128-bit data width selection for the Slave 0 00: 32-bit + * AXI data width (default) 01: 64-bit AXI data width 10: 128-bit AXI data + * width 11: reserved + * PSU_FPD_SLCR_AFI_FS_DW_SS0_SEL 0x2 + + * Select the 32/64/128-bit data width selection for the Slave 1 00: 32-bit + * AXI data width (default) 01: 64-bit AXI data width 10: 128-bit AXI data + * width 11: reserved + * PSU_FPD_SLCR_AFI_FS_DW_SS1_SEL 0x2 + + * afi fs SLCR control register. This register is static and should not be + * modified during operation. + * (OFFSET, MASK, VALUE) (0XFD615000, 0x00000F00U ,0x00000A00U) + */ + PSU_Mask_Write(FPD_SLCR_AFI_FS_OFFSET, 0x00000F00U, 0x00000A00U); +/*##################################################################### */ + + + return 1; +} +unsigned long psu_ps_pl_reset_config_data(void) +{ + /* + * PS PL RESET SEQUENCE + */ + /* + * FABRIC RESET USING EMIO + */ + /* + * Register : MASK_DATA_5_MSW @ 0XFF0A002C + + * Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW] + * PSU_GPIO_MASK_DATA_5_MSW_MASK_5_MSW 0x8000 + + * Maskable Output Data (GPIO Bank5, EMIO, Upper 16bits) + * (OFFSET, MASK, VALUE) (0XFF0A002C, 0xFFFF0000U ,0x80000000U) + */ + PSU_Mask_Write(GPIO_MASK_DATA_5_MSW_OFFSET, + 0xFFFF0000U, 0x80000000U); +/*##################################################################### */ + + /* + * Register : DIRM_5 @ 0XFF0A0344 + + * Operation is the same as DIRM_0[DIRECTION_0] + * PSU_GPIO_DIRM_5_DIRECTION_5 0x80000000 + + * Direction mode (GPIO Bank5, EMIO) + * (OFFSET, MASK, VALUE) (0XFF0A0344, 0xFFFFFFFFU ,0x80000000U) + */ + PSU_Mask_Write(GPIO_DIRM_5_OFFSET, 0xFFFFFFFFU, 0x80000000U); +/*##################################################################### */ + + /* + * Register : OEN_5 @ 0XFF0A0348 + + * Operation is the same as OEN_0[OP_ENABLE_0] + * PSU_GPIO_OEN_5_OP_ENABLE_5 0x80000000 + + * Output enable (GPIO Bank5, EMIO) + * (OFFSET, MASK, VALUE) (0XFF0A0348, 0xFFFFFFFFU ,0x80000000U) + */ + PSU_Mask_Write(GPIO_OEN_5_OFFSET, 0xFFFFFFFFU, 0x80000000U); +/*##################################################################### */ + + /* + * Register : DATA_5 @ 0XFF0A0054 + + * Output Data + * PSU_GPIO_DATA_5_DATA_5 0x80000000 + + * Output Data (GPIO Bank5, EMIO) + * (OFFSET, MASK, VALUE) (0XFF0A0054, 0xFFFFFFFFU ,0x80000000U) + */ + PSU_Mask_Write(GPIO_DATA_5_OFFSET, 0xFFFFFFFFU, 0x80000000U); +/*##################################################################### */ mask_delay(1); - /*############################################################################################################################ */ +/*##################################################################### */ - // : FABRIC RESET USING DATA_5 TOGGLE - /*Register : DATA_5 @ 0XFF0A0054

+ /* + * FABRIC RESET USING DATA_5 TOGGLE + */ + /* + * Register : DATA_5 @ 0XFF0A0054 - Output Data - PSU_GPIO_DATA_5_DATA_5 0X00000000 + * Output Data + * PSU_GPIO_DATA_5_DATA_5 0X00000000 - Output Data (GPIO Bank5, EMIO) - (OFFSET, MASK, VALUE) (0XFF0A0054, 0xFFFFFFFFU ,0x00000000U) - RegMask = (GPIO_DATA_5_DATA_5_MASK | 0 ); - - RegVal = ((0x00000000U << GPIO_DATA_5_DATA_5_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (GPIO_DATA_5_OFFSET ,0xFFFFFFFFU ,0x00000000U); - /*############################################################################################################################ */ + * Output Data (GPIO Bank5, EMIO) + * (OFFSET, MASK, VALUE) (0XFF0A0054, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(GPIO_DATA_5_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ mask_delay(1); - /*############################################################################################################################ */ +/*##################################################################### */ - // : FABRIC RESET USING DATA_5 TOGGLE - /*Register : DATA_5 @ 0XFF0A0054

+ /* + * FABRIC RESET USING DATA_5 TOGGLE + */ + /* + * Register : DATA_5 @ 0XFF0A0054 - Output Data - PSU_GPIO_DATA_5_DATA_5 0x80000000 + * Output Data + * PSU_GPIO_DATA_5_DATA_5 0x80000000 - Output Data (GPIO Bank5, EMIO) - (OFFSET, MASK, VALUE) (0XFF0A0054, 0xFFFFFFFFU ,0x80000000U) - RegMask = (GPIO_DATA_5_DATA_5_MASK | 0 ); - - RegVal = ((0x80000000U << GPIO_DATA_5_DATA_5_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (GPIO_DATA_5_OFFSET ,0xFFFFFFFFU ,0x80000000U); - /*############################################################################################################################ */ + * Output Data (GPIO Bank5, EMIO) + * (OFFSET, MASK, VALUE) (0XFF0A0054, 0xFFFFFFFFU ,0x80000000U) + */ + PSU_Mask_Write(GPIO_DATA_5_OFFSET, 0xFFFFFFFFU, 0x80000000U); +/*##################################################################### */ - return 1; + return 1; } -unsigned long psu_ddr_phybringup_data() { +unsigned long psu_ddr_phybringup_data(void) +{ + + + unsigned int regval = 0; + + unsigned int pll_retry = 10; + + unsigned int pll_locked = 0; + + + while ((pll_retry > 0) && (!pll_locked)) { + + Xil_Out32(0xFD080004, 0x00040010);/*PIR*/ + Xil_Out32(0xFD080004, 0x00040011);/*PIR*/ + + while ((Xil_In32(0xFD080030) & 0x1) != 1) { + /*****TODO*****/ + + /*TIMEOUT poll mechanism need to be inserted in this block*/ + + } + + + pll_locked = (Xil_In32(0xFD080030) & 0x80000000) + >> 31;/*PGSR0*/ + pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000) + >> 16;/*DX0GSR0*/ + pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000) + >> 16;/*DX2GSR0*/ + pll_locked &= (Xil_In32(0xFD080BE0) & 0x10000) + >> 16;/*DX4GSR0*/ + pll_locked &= (Xil_In32(0xFD080DE0) & 0x10000) + >> 16;/*DX6GSR0*/ + pll_retry--; + } + Xil_Out32(0xFD0800C0, Xil_In32(0xFD0800C0) | + (pll_retry << 16));/*GPR0*/ + Xil_Out32(0xFD080004U, 0x00040063U); + /* PHY BRINGUP SEQ */ + while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU) { + /*****TODO*****/ + + /*TIMEOUT poll mechanism need to be inserted in this block*/ + + } + + prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U); + /* poll for PHY initialization to complete */ + while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU) { + /*****TODO*****/ + + /*TIMEOUT poll mechanism need to be inserted in this block*/ + + } - unsigned int regval = 0; - int dpll_divisor; - dpll_divisor = (Xil_In32(0xFD1A0080U) & 0x00003F00U) >> 0x00000008U; - prog_reg (0xFD1A0080U, 0x00003F00U, 0x00000008U, 0x00000005U); - prog_reg (0xFD080028U, 0x00000001U, 0x00000000U, 0x00000001U); - Xil_Out32(0xFD080004U, 0x00040003U); - while ((Xil_In32(0xFD080030U) & 0x00000001U) != 0x00000001U); - prog_reg (0xFD080684U, 0x06000000U, 0x00000019U, 0x00000001U); - prog_reg (0xFD0806A4U, 0x06000000U, 0x00000019U, 0x00000001U); - prog_reg (0xFD0806C4U, 0x06000000U, 0x00000019U, 0x00000001U); - prog_reg (0xFD0806E4U, 0x06000000U, 0x00000019U, 0x00000001U); - prog_reg (0xFD1A0080, 0x3F00, 0x8, dpll_divisor); - Xil_Out32(0xFD080004U, 0x40040071U); - while ((Xil_In32(0xFD080030U) & 0x00000001U) != 0x00000001U); - Xil_Out32(0xFD080004U, 0x40040001U); - while ((Xil_In32(0xFD080030U) & 0x00000001U) != 0x00000001U); - // PHY BRINGUP SEQ - while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU); - prog_reg (0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U); - //poll for PHY initialization to complete - while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU); - Xil_Out32(0xFD0701B0U, 0x00000001U); Xil_Out32(0xFD070320U, 0x00000001U); - while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U); - prog_reg (0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U); - Xil_Out32(0xFD080004, 0x0004FE01); //PUB_PIR - regval = Xil_In32(0xFD080030); //PUB_PGSR0 - while(regval != 0x80000FFF){ - regval = Xil_In32(0xFD080030); //PUB_PGSR0 - } + while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U) { + /*****TODO*****/ - - // Run Vref training in static read mode + /*TIMEOUT poll mechanism need to be inserted in this block*/ + + } + + prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U); + Xil_Out32(0xFD080004, 0x0004FE01); /*PUB_PIR*/ + regval = Xil_In32(0xFD080030); /*PUB_PGSR0*/ + while (regval != 0x80000FFF) + regval = Xil_In32(0xFD080030); /*PUB_PGSR0*/ + +/* Run Vref training in static read mode*/ Xil_Out32(0xFD080200U, 0x100091C7U); - Xil_Out32(0xFD080018U, 0x00F01EF2U); - Xil_Out32(0xFD08001CU, 0x55AA5498U); - Xil_Out32(0xFD08142CU, 0x00041830U); - Xil_Out32(0xFD08146CU, 0x00041830U); - Xil_Out32(0xFD0814ACU, 0x00041830U); - Xil_Out32(0xFD0814ECU, 0x00041830U); - Xil_Out32(0xFD08152CU, 0x00041830U); - + Xil_Out32(0xFD080018U, 0x00F01EEFU); + prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U); + prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U); - Xil_Out32(0xFD080004, 0x00060001); //PUB_PIR - regval = Xil_In32(0xFD080030); //PUB_PGSR0 - while((regval & 0x80004001) != 0x80004001){ - regval = Xil_In32(0xFD080030); //PUB_PGSR0 - } - // Vref training is complete, disabling static read mode + Xil_Out32(0xFD080004, 0x00060001); /*PUB_PIR*/ + regval = Xil_In32(0xFD080030); /*PUB_PGSR0*/ + while ((regval & 0x80004001) != 0x80004001) { + /*PUB_PGSR0*/ + regval = Xil_In32(0xFD080030); + } + + prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U); + prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U); +/*Vref training is complete, disabling static read mode*/ Xil_Out32(0xFD080200U, 0x800091C7U); - Xil_Out32(0xFD080018U, 0x00F12302U); - Xil_Out32(0xFD08001CU, 0x55AA5480U); - Xil_Out32(0xFD08142CU, 0x00041800U); - Xil_Out32(0xFD08146CU, 0x00041800U); - Xil_Out32(0xFD0814ACU, 0x00041800U); - Xil_Out32(0xFD0814ECU, 0x00041800U); - Xil_Out32(0xFD08152CU, 0x00041800U); - + Xil_Out32(0xFD080018U, 0x00F122E7U); - Xil_Out32(0xFD080004, 0x0000C001); //PUB_PIR - regval = Xil_In32(0xFD080030); //PUB_PGSR0 - while((regval & 0x80000C01) != 0x80000C01){ - regval = Xil_In32(0xFD080030); //PUB_PGSR0 - } + + Xil_Out32(0xFD080004, 0x0000C001); /*PUB_PIR*/ + regval = Xil_In32(0xFD080030); /*PUB_PGSR0*/ + while ((regval & 0x80000C01) != 0x80000C01) { + /*PUB_PGSR0*/ + regval = Xil_In32(0xFD080030); + } Xil_Out32(0xFD070180U, 0x01000040U); Xil_Out32(0xFD070060U, 0x00000000U); - prog_reg (0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U); + prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U); -return 1; +return 1; } /** * CRL_APB Base Address */ #define CRL_APB_BASEADDR 0XFF5E0000U -#define CRL_APB_RST_LPD_IOU0 ( ( CRL_APB_BASEADDR ) + 0X00000230U ) -#define CRL_APB_RST_LPD_IOU1 ( ( CRL_APB_BASEADDR ) + 0X00000234U ) -#define CRL_APB_RST_LPD_IOU2 ( ( CRL_APB_BASEADDR ) + 0X00000238U ) -#define CRL_APB_RST_LPD_TOP ( ( CRL_APB_BASEADDR ) + 0X0000023CU ) -#define CRL_APB_IOU_SWITCH_CTRL ( ( CRL_APB_BASEADDR ) + 0X0000009CU ) +#define CRL_APB_RST_LPD_IOU0 ((CRL_APB_BASEADDR) + 0X00000230U) +#define CRL_APB_RST_LPD_IOU1 ((CRL_APB_BASEADDR) + 0X00000234U) +#define CRL_APB_RST_LPD_IOU2 ((CRL_APB_BASEADDR) + 0X00000238U) +#define CRL_APB_RST_LPD_TOP ((CRL_APB_BASEADDR) + 0X0000023CU) +#define CRL_APB_IOU_SWITCH_CTRL ((CRL_APB_BASEADDR) + 0X0000009CU) /** * CRF_APB Base Address */ #define CRF_APB_BASEADDR 0XFD1A0000U -#define CRF_APB_RST_FPD_TOP ( ( CRF_APB_BASEADDR ) + 0X00000100U ) -#define CRF_APB_GPU_REF_CTRL ( ( CRF_APB_BASEADDR ) + 0X00000084U ) -#define CRF_APB_RST_DDR_SS ( ( CRF_APB_BASEADDR ) + 0X00000108U ) +#define CRF_APB_RST_FPD_TOP ((CRF_APB_BASEADDR) + 0X00000100U) +#define CRF_APB_GPU_REF_CTRL ((CRF_APB_BASEADDR) + 0X00000084U) +#define CRF_APB_RST_DDR_SS ((CRF_APB_BASEADDR) + 0X00000108U) #define PSU_MASK_POLL_TIME 1100000 +/** + * * Register: CRF_APB_DPLL_CTRL + */ +#define CRF_APB_DPLL_CTRL ((CRF_APB_BASEADDR) + 0X0000002C) -int mask_pollOnValue(u32 add , u32 mask, u32 value ) { - volatile u32 *addr = (volatile u32*)(unsigned long) add; + +#define CRF_APB_DPLL_CTRL_DIV2_SHIFT 16 +#define CRF_APB_DPLL_CTRL_DIV2_WIDTH 1 + +#define CRF_APB_DPLL_CTRL_FBDIV_SHIFT 8 +#define CRF_APB_DPLL_CTRL_FBDIV_WIDTH 7 + +#define CRF_APB_DPLL_CTRL_BYPASS_SHIFT 3 +#define CRF_APB_DPLL_CTRL_BYPASS_WIDTH 1 + +#define CRF_APB_DPLL_CTRL_RESET_SHIFT 0 +#define CRF_APB_DPLL_CTRL_RESET_WIDTH 1 + +/** + * * Register: CRF_APB_DPLL_CFG + */ +#define CRF_APB_DPLL_CFG ((CRF_APB_BASEADDR) + 0X00000030) + +#define CRF_APB_DPLL_CFG_LOCK_DLY_SHIFT 25 +#define CRF_APB_DPLL_CFG_LOCK_DLY_WIDTH 7 + +#define CRF_APB_DPLL_CFG_LOCK_CNT_SHIFT 13 +#define CRF_APB_DPLL_CFG_LOCK_CNT_WIDTH 10 + +#define CRF_APB_DPLL_CFG_LFHF_SHIFT 10 +#define CRF_APB_DPLL_CFG_LFHF_WIDTH 2 + +#define CRF_APB_DPLL_CFG_CP_SHIFT 5 +#define CRF_APB_DPLL_CFG_CP_WIDTH 4 + +#define CRF_APB_DPLL_CFG_RES_SHIFT 0 +#define CRF_APB_DPLL_CFG_RES_WIDTH 4 + +/** + * Register: CRF_APB_PLL_STATUS + */ +#define CRF_APB_PLL_STATUS ((CRF_APB_BASEADDR) + 0X00000044) + + +static int mask_pollOnValue(u32 add, u32 mask, u32 value) +{ + volatile u32 *addr = (volatile u32 *)(unsigned long) add; int i = 0; - while ((*addr & mask)!= value) { - if (i == PSU_MASK_POLL_TIME) { + + while ((*addr & mask) != value) { + if (i == PSU_MASK_POLL_TIME) return 0; - } i++; } - return 1; - //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr); + return 1; } -int mask_poll(u32 add , u32 mask) { - volatile u32 *addr = (volatile u32*)(unsigned long) add; +static int mask_poll(u32 add, u32 mask) +{ + volatile u32 *addr = (volatile u32 *)(unsigned long) add; int i = 0; + while (!(*addr & mask)) { - if (i == PSU_MASK_POLL_TIME) { + if (i == PSU_MASK_POLL_TIME) return 0; - } i++; } - return 1; - //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr); + return 1; } -void mask_delay(u32 delay) { - usleep (delay); +static void mask_delay(u32 delay) +{ + usleep(delay); } -u32 mask_read(u32 add , u32 mask ) { - volatile u32 *addr = (volatile u32*)(unsigned long) add; - u32 val = (*addr & mask); - //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val); - return val; +static u32 mask_read(u32 add, u32 mask) +{ + volatile u32 *addr = (volatile u32 *)(unsigned long) add; + u32 val = (*addr & mask); + return val; } +static void dpll_prog(int ddr_pll_fbdiv, int d_lock_dly, int d_lock_cnt, + int d_lfhf, int d_cp, int d_res) { -//Following SERDES programming sequences that a user need to follow to work around the known limitation with SERDES. -//These sequences should done before STEP 1 and STEP 2 as described in previous section. These programming steps are -//required for current silicon version and are likely to undergo further changes with subsequent silicon versions. + unsigned int pll_ctrl_regval; + unsigned int pll_status_regval; + + pll_ctrl_regval = Xil_In32(CRF_APB_DPLL_CTRL); + pll_ctrl_regval = pll_ctrl_regval & (~CRF_APB_DPLL_CTRL_DIV2_MASK); + pll_ctrl_regval = pll_ctrl_regval | (1 << CRF_APB_DPLL_CTRL_DIV2_SHIFT); + Xil_Out32(CRF_APB_DPLL_CTRL, pll_ctrl_regval); + + pll_ctrl_regval = Xil_In32(CRF_APB_DPLL_CFG); + pll_ctrl_regval = pll_ctrl_regval & (~CRF_APB_DPLL_CFG_LOCK_DLY_MASK); + pll_ctrl_regval = pll_ctrl_regval | + (d_lock_dly << CRF_APB_DPLL_CFG_LOCK_DLY_SHIFT); + Xil_Out32(CRF_APB_DPLL_CFG, pll_ctrl_regval); + + pll_ctrl_regval = Xil_In32(CRF_APB_DPLL_CFG); + pll_ctrl_regval = pll_ctrl_regval & (~CRF_APB_DPLL_CFG_LOCK_CNT_MASK); + pll_ctrl_regval = pll_ctrl_regval | + (d_lock_cnt << CRF_APB_DPLL_CFG_LOCK_CNT_SHIFT); + Xil_Out32(CRF_APB_DPLL_CFG, pll_ctrl_regval); + + pll_ctrl_regval = Xil_In32(CRF_APB_DPLL_CFG); + pll_ctrl_regval = pll_ctrl_regval & (~CRF_APB_DPLL_CFG_LFHF_MASK); + pll_ctrl_regval = pll_ctrl_regval | + (d_lfhf << CRF_APB_DPLL_CFG_LFHF_SHIFT); + Xil_Out32(CRF_APB_DPLL_CFG, pll_ctrl_regval); + + pll_ctrl_regval = Xil_In32(CRF_APB_DPLL_CFG); + pll_ctrl_regval = pll_ctrl_regval & (~CRF_APB_DPLL_CFG_CP_MASK); + pll_ctrl_regval = pll_ctrl_regval | + (d_cp << CRF_APB_DPLL_CFG_CP_SHIFT); + Xil_Out32(CRF_APB_DPLL_CFG, pll_ctrl_regval); + + pll_ctrl_regval = Xil_In32(CRF_APB_DPLL_CFG); + pll_ctrl_regval = pll_ctrl_regval & (~CRF_APB_DPLL_CFG_RES_MASK); + pll_ctrl_regval = pll_ctrl_regval | + (d_res << CRF_APB_DPLL_CFG_RES_SHIFT); + Xil_Out32(CRF_APB_DPLL_CFG, pll_ctrl_regval); + + pll_ctrl_regval = Xil_In32(CRF_APB_DPLL_CTRL); + pll_ctrl_regval = pll_ctrl_regval & (~CRF_APB_DPLL_CTRL_FBDIV_MASK); + pll_ctrl_regval = pll_ctrl_regval | + (ddr_pll_fbdiv << CRF_APB_DPLL_CTRL_FBDIV_SHIFT); + Xil_Out32(CRF_APB_DPLL_CTRL, pll_ctrl_regval); + + /*Setting PLL BYPASS*/ + pll_ctrl_regval = Xil_In32(CRF_APB_DPLL_CTRL); + pll_ctrl_regval = pll_ctrl_regval & (~CRF_APB_DPLL_CTRL_BYPASS_MASK); + pll_ctrl_regval = pll_ctrl_regval | + (1 << CRF_APB_DPLL_CTRL_BYPASS_SHIFT); + Xil_Out32(CRF_APB_DPLL_CTRL, pll_ctrl_regval); + + /*Setting PLL RESET*/ + pll_ctrl_regval = Xil_In32(CRF_APB_DPLL_CTRL); + pll_ctrl_regval = pll_ctrl_regval & (~CRF_APB_DPLL_CTRL_RESET_MASK); + pll_ctrl_regval = pll_ctrl_regval | + (1 << CRF_APB_DPLL_CTRL_RESET_SHIFT); + Xil_Out32(CRF_APB_DPLL_CTRL, pll_ctrl_regval); + + /*Clearing PLL RESET*/ + pll_ctrl_regval = Xil_In32(CRF_APB_DPLL_CTRL); + pll_ctrl_regval = pll_ctrl_regval & (~CRF_APB_DPLL_CTRL_RESET_MASK); + pll_ctrl_regval = pll_ctrl_regval | + (0 << CRF_APB_DPLL_CTRL_RESET_SHIFT); + Xil_Out32(CRF_APB_DPLL_CTRL, pll_ctrl_regval); + + /*Checking PLL lock*/ + pll_status_regval = 0x00000000; + while ((pll_status_regval & CRF_APB_PLL_STATUS_DPLL_LOCK_MASK) != + CRF_APB_PLL_STATUS_DPLL_LOCK_MASK) + pll_status_regval = Xil_In32(CRF_APB_PLL_STATUS); -int serdes_fixcal_code() { + + /*Clearing PLL BYPASS*/ + pll_ctrl_regval = Xil_In32(CRF_APB_DPLL_CTRL); + pll_ctrl_regval = pll_ctrl_regval & (~CRF_APB_DPLL_CTRL_BYPASS_MASK); + pll_ctrl_regval = pll_ctrl_regval | + (0 << CRF_APB_DPLL_CTRL_BYPASS_SHIFT); + Xil_Out32(CRF_APB_DPLL_CTRL, pll_ctrl_regval); + +} + +/*Following SERDES programming sequences that a user need to follow to work + * around the known limitation with SERDES. These sequences should done + * before STEP 1 and STEP 2 as described in previous section. These + * programming steps are *required for current silicon version and are + * likely to undergo further changes with subsequent silicon versions. + */ + + +static int serdes_enb_coarse_saturation(void) +{ + /*Enable PLL Coarse Code saturation Logic*/ + Xil_Out32(0xFD402094, 0x00000010); + Xil_Out32(0xFD406094, 0x00000010); + Xil_Out32(0xFD40A094, 0x00000010); + Xil_Out32(0xFD40E094, 0x00000010); + return 1; +} + +int serdes_fixcal_code(void) +{ int MaskStatus = 1; - // L3_TM_CALIB_DIG19 - Xil_Out32(0xFD40EC4C,0x00000020); - //ICM_CFG0 - Xil_Out32(0xFD410010,0x00000001); + unsigned int rdata = 0; + + /*The valid codes are from 0x26 to 0x3C. + *There are 23 valid codes in total. + */ + /*Each element of array stands for count of occurence of valid code.*/ + unsigned int match_pmos_code[23]; + /*Each element of array stands for count of occurence of valid code.*/ + /*The valid codes are from 0xC to 0x12. + *There are 7 valid codes in total. + */ + unsigned int match_nmos_code[23]; + /*Each element of array stands for count of occurence of valid code.*/ + /*The valid codes are from 0x6 to 0xC. + * There are 7 valid codes in total. + */ + unsigned int match_ical_code[7]; + /*Each element of array stands for count of occurence of valid code.*/ + unsigned int match_rcal_code[7]; - //is calibration done, polling on L3_CALIB_DONE_STATUS - MaskStatus = mask_poll(0xFD40EF14, 0x2); - - if (MaskStatus == 0) - { - xil_printf("SERDES initialization timed out\n\r"); - } - - unsigned int tmp_0_1; - tmp_0_1 = mask_read(0xFD400B0C, 0x3F); - - unsigned int tmp_0_2 = tmp_0_1 & (0x7); - unsigned int tmp_0_3 = tmp_0_1 & (0x38); - //Configure ICM for de-asserting CMN_Resetn - Xil_Out32(0xFD410010,0x00000000); - Xil_Out32(0xFD410014,0x00000000); - - unsigned int tmp_0_2_mod = (tmp_0_2 <<1) | (0x1); - tmp_0_2_mod = (tmp_0_2_mod <<4); - - tmp_0_3 = tmp_0_3 >>3; - Xil_Out32(0xFD40EC4C,tmp_0_3); + unsigned int p_code = 0; + unsigned int n_code = 0; + unsigned int i_code = 0; + unsigned int r_code = 0; + unsigned int repeat_count = 0; + unsigned int L3_TM_CALIB_DIG20 = 0; + unsigned int L3_TM_CALIB_DIG19 = 0; + unsigned int L3_TM_CALIB_DIG18 = 0; + unsigned int L3_TM_CALIB_DIG16 = 0; + unsigned int L3_TM_CALIB_DIG15 = 0; + unsigned int L3_TM_CALIB_DIG14 = 0; - //L3_TM_CALIB_DIG18 - Xil_Out32(0xFD40EC48,tmp_0_2_mod); - return MaskStatus; + int i = 0; + rdata = Xil_In32(0XFD40289C); + rdata = rdata & ~0x03; + rdata = rdata | 0x1; + Xil_Out32(0XFD40289C, rdata); + // check supply good status before starting AFE sequencing + int count = 0; + do + { + if (count == PSU_MASK_POLL_TIME) + break; + rdata = Xil_In32(0xFD402B1C); + count++; + }while((rdata&0x0000000E) !=0x0000000E); + + for (i = 0; i < 23; i++) { + match_pmos_code[i] = 0; + match_nmos_code[i] = 0; + } + for (i = 0; i < 7; i++) { + match_ical_code[i] = 0; + match_rcal_code[i] = 0; + } + + + do { + /*Clear ICM_CFG value*/ + Xil_Out32(0xFD410010, 0x00000000); + Xil_Out32(0xFD410014, 0x00000000); + + /*Set ICM_CFG value*/ + /*This will trigger recalibration of all stages*/ + Xil_Out32(0xFD410010, 0x00000001); + Xil_Out32(0xFD410014, 0x00000000); + + /*is calibration done? polling on L3_CALIB_DONE_STATUS*/ + MaskStatus = mask_poll(0xFD40EF14, 0x2); + if (MaskStatus == 0) { + /*failure here is because of calibration done timeout*/ + xil_printf("#SERDES initialization timed out\n\r"); + return MaskStatus; + } + + p_code = mask_read(0xFD40EF18, 0xFFFFFFFF);/*PMOS code*/ + n_code = mask_read(0xFD40EF1C, 0xFFFFFFFF);/*NMOS code*/ + /*m_code = mask_read(0xFD40EF20, 0xFFFFFFFF)*/;/*MPHY code*/ + i_code = mask_read(0xFD40EF24, 0xFFFFFFFF);/*ICAL code*/ + r_code = mask_read(0xFD40EF28, 0xFFFFFFFF);/*RX code*/ + /*u_code = mask_read(0xFD40EF2C, 0xFFFFFFFF)*/;/*USB2 code*/ + + /*PMOS code in acceptable range*/ + if ((p_code >= 0x26) && (p_code <= 0x3C)) + match_pmos_code[p_code - 0x26] += 1; + + /*NMOS code in acceptable range*/ + if ((n_code >= 0x26) && (n_code <= 0x3C)) + match_nmos_code[n_code - 0x26] += 1; + + /*PMOS code in acceptable range*/ + if ((i_code >= 0xC) && (i_code <= 0x12)) + match_ical_code[i_code - 0xC] += 1; + + /*NMOS code in acceptable range*/ + if ((r_code >= 0x6) && (r_code <= 0xC)) + match_rcal_code[r_code - 0x6] += 1; + + + } while (repeat_count++ < 10); + + /*find the valid code which resulted in maximum times in 10 iterations*/ + for (i = 0; i < 23; i++) { + if (match_pmos_code[i] >= match_pmos_code[0]) { + match_pmos_code[0] = match_pmos_code[i]; + p_code = 0x26 + i; + } + if (match_nmos_code[i] >= match_nmos_code[0]) { + match_nmos_code[0] = match_nmos_code[i]; + n_code = 0x26 + i; + } + } + + for (i = 0; i < 7; i++) { + if (match_ical_code[i] >= match_ical_code[0]) { + match_ical_code[0] = match_ical_code[i]; + i_code = 0xC + i; + } + if (match_rcal_code[i] >= match_rcal_code[0]) { + match_rcal_code[0] = match_rcal_code[i]; + r_code = 0x6 + i; + } + } + /*L3_TM_CALIB_DIG20[3] PSW MSB Override*/ + /*L3_TM_CALIB_DIG20[2:0] PSW Code [4:2]*/ + L3_TM_CALIB_DIG20 = mask_read(0xFD40EC50, 0xFFFFFFF0);/*read DIG20*/ + L3_TM_CALIB_DIG20 = L3_TM_CALIB_DIG20 | 0x8 | ((p_code >> 2) & 0x7); + + + /*L3_TM_CALIB_DIG19[7:6] PSW Code [1:0]*/ + /*L3_TM_CALIB_DIG19[5] PSW Override*/ + /*L3_TM_CALIB_DIG19[2] NSW MSB Override*/ + /*L3_TM_CALIB_DIG19[1:0] NSW Code [4:3]*/ + L3_TM_CALIB_DIG19 = mask_read(0xFD40EC4C, 0xFFFFFF18);/*read DIG19*/ + L3_TM_CALIB_DIG19 = L3_TM_CALIB_DIG19 | ((p_code & 0x3) << 6) + | 0x20 | 0x4 | ((n_code >> 3) & 0x3); + + /*L3_TM_CALIB_DIG18[7:5] NSW Code [2:0]*/ + /*L3_TM_CALIB_DIG18[4] NSW Override*/ + L3_TM_CALIB_DIG18 = mask_read(0xFD40EC48, 0xFFFFFF0F);/*read DIG18*/ + L3_TM_CALIB_DIG18 = L3_TM_CALIB_DIG18 | ((n_code & 0x7) << 5) | 0x10; + + + /*L3_TM_CALIB_DIG16[2:0] RX Code [3:1]*/ + L3_TM_CALIB_DIG16 = mask_read(0xFD40EC40, 0xFFFFFFF8);/*read DIG16*/ + L3_TM_CALIB_DIG16 = L3_TM_CALIB_DIG16 | ((r_code >> 1) & 0x7); + + /*L3_TM_CALIB_DIG15[7] RX Code [0]*/ + /*L3_TM_CALIB_DIG15[6] RX CODE Override*/ + /*L3_TM_CALIB_DIG15[3] ICAL MSB Override*/ + /*L3_TM_CALIB_DIG15[2:0] ICAL Code [3:1]*/ + L3_TM_CALIB_DIG15 = mask_read(0xFD40EC3C, 0xFFFFFF30);/*read DIG15*/ + L3_TM_CALIB_DIG15 = L3_TM_CALIB_DIG15 | ((r_code & 0x1) << 7) + | 0x40 | 0x8 | ((i_code >> 1) & 0x7); + + /*L3_TM_CALIB_DIG14[7] ICAL Code [0]*/ + /*L3_TM_CALIB_DIG14[6] ICAL Override*/ + L3_TM_CALIB_DIG14 = mask_read(0xFD40EC38, 0xFFFFFF3F);/*read DIG14*/ + L3_TM_CALIB_DIG14 = L3_TM_CALIB_DIG14 | ((i_code & 0x1) << 7) | 0x40; + + /*Forces the calibration values*/ + Xil_Out32(0xFD40EC50, L3_TM_CALIB_DIG20); + Xil_Out32(0xFD40EC4C, L3_TM_CALIB_DIG19); + Xil_Out32(0xFD40EC48, L3_TM_CALIB_DIG18); + Xil_Out32(0xFD40EC40, L3_TM_CALIB_DIG16); + Xil_Out32(0xFD40EC3C, L3_TM_CALIB_DIG15); + Xil_Out32(0xFD40EC38, L3_TM_CALIB_DIG14); + return MaskStatus; } - -int serdes_enb_coarse_saturation() { - //Enable PLL Coarse Code saturation Logic - Xil_Out32(0xFD402094,0x00000010); - Xil_Out32(0xFD406094,0x00000010); - Xil_Out32(0xFD40A094,0x00000010); - Xil_Out32(0xFD40E094,0x00000010); - return 1; -} - -int init_serdes() { +static int init_serdes(void) +{ int status = 1; + status &= psu_resetin_init_data(); status &= serdes_fixcal_code(); status &= serdes_enb_coarse_saturation(); - status &= psu_serdes_init_data(); + status &= psu_serdes_init_data(); status &= psu_resetout_init_data(); return status; } - - - - -void init_peripheral() +static void init_peripheral(void) { - unsigned int RegValue; - - /* Turn on IOU Clock */ - //Xil_Out32( CRL_APB_IOU_SWITCH_CTRL, 0x01001500); - - /* Release all resets in the IOU */ - Xil_Out32( CRL_APB_RST_LPD_IOU0, 0x00000000); - Xil_Out32( CRL_APB_RST_LPD_IOU1, 0x00000000); - Xil_Out32( CRL_APB_RST_LPD_IOU2, 0x00000000); - - /* Activate GPU clocks */ - //Xil_Out32(CRF_APB_GPU_REF_CTRL, 0x07001500); - - /* Take LPD out of reset except R5 */ - RegValue = Xil_In32(CRL_APB_RST_LPD_TOP); - RegValue &= 0x7; - Xil_Out32( CRL_APB_RST_LPD_TOP, RegValue); - - /* Take most of FPD out of reset */ - Xil_Out32( CRF_APB_RST_FPD_TOP, 0x00000000); - - /* Making DPDMA as secure */ - unsigned int tmp_regval; - tmp_regval = Xil_In32(0xFD690040); - tmp_regval &= ~0x00000001; - Xil_Out32(0xFD690040, tmp_regval); - - /* Making PCIe as secure */ - tmp_regval = Xil_In32(0xFD690030); - tmp_regval &= ~0x00000001; - Xil_Out32(0xFD690030, tmp_regval); +/*SMMU_REG Interrrupt Enable: Followig register need to be written all the time to properly catch SMMU messages.*/ + PSU_Mask_Write(0xFD5F0018, 0x8000001FU, 0x8000001FU); } -int psu_init_xppu_aper_ram() { - unsigned long APER_OFFSET = 0xFF981000; - int i = 0; - for (; i <= 400; i++) { - PSU_Mask_Write (APER_OFFSET ,0xF80FFFFFU ,0x08080000U); - APER_OFFSET = APER_OFFSET + 0x4; - } +static int psu_init_xppu_aper_ram(void) +{ return 0; } -int psu_lpd_protection() { - psu_init_xppu_aper_ram(); - psu_lpd_xppu_data(); - return 0; +int psu_lpd_protection(void) +{ + psu_init_xppu_aper_ram(); + return 0; } -int psu_ddr_protection() { - psu_ddr_xmpu0_data(); - psu_ddr_xmpu1_data(); - psu_ddr_xmpu2_data(); - psu_ddr_xmpu3_data(); - psu_ddr_xmpu4_data(); - psu_ddr_xmpu5_data(); - return 0; +int psu_ddr_protection(void) +{ + psu_ddr_xmpu0_data(); + psu_ddr_xmpu1_data(); + psu_ddr_xmpu2_data(); + psu_ddr_xmpu3_data(); + psu_ddr_xmpu4_data(); + psu_ddr_xmpu5_data(); + return 0; } -int psu_ocm_protection() { - psu_ocm_xmpu_data(); - return 0; +int psu_ocm_protection(void) +{ + psu_ocm_xmpu_data(); + return 0; } -int psu_fpd_protection() { - psu_fpd_xmpu_data(); - return 0; +int psu_fpd_protection(void) +{ + psu_fpd_xmpu_data(); + return 0; } -int psu_protection_lock() { - psu_protection_lock_data(); - return 0; +int psu_protection_lock(void) +{ + psu_protection_lock_data(); + return 0; } -int psu_protection() { - psu_ddr_protection(); - psu_ocm_protection(); - psu_fpd_protection(); - psu_lpd_protection(); - return 0; +int psu_protection(void) +{ + psu_apply_master_tz(); + psu_ddr_protection(); + psu_ocm_protection(); + psu_fpd_protection(); + psu_lpd_protection(); + return 0; } - - int -psu_init() +psu_init(void) { - int status = 1; - status &= psu_mio_init_data (); - status &= psu_pll_init_data (); - status &= psu_clock_init_data (); - - status &= psu_ddr_init_data (); - status &= psu_ddr_phybringup_data (); - status &= psu_peripherals_init_data (); + int status = 1; + status &= psu_mio_init_data(); + status &= psu_pll_init_data(); + status &= psu_clock_init_data(); + status &= psu_ddr_init_data(); + status &= psu_ddr_phybringup_data(); + status &= psu_peripherals_init_data(); status &= init_serdes(); - init_peripheral (); + init_peripheral(); - status &= psu_peripherals_powerdwn_data (); - - if (status == 0) { + status &= psu_peripherals_powerdwn_data(); + status &= psu_afi_config(); + psu_ddr_qos_init_data(); + + if (status == 0) return 1; - } return 0; } diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init.h index e9741eb2f..591552936 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init.h +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init.h @@ -34,7 +34,7 @@ * * @file psu_init.h * -* This file is automatically generated +* This file is automatically generated * *****************************************************************************/ @@ -53,8 +53,6 @@ #define CRL_APB_RPLL_CTRL_OFFSET 0XFF5E0030 #undef CRL_APB_RPLL_TO_FPD_CTRL_OFFSET #define CRL_APB_RPLL_TO_FPD_CTRL_OFFSET 0XFF5E0048 -#undef CRL_APB_RPLL_FRAC_CFG_OFFSET -#define CRL_APB_RPLL_FRAC_CFG_OFFSET 0XFF5E0038 #undef CRL_APB_IOPLL_CFG_OFFSET #define CRL_APB_IOPLL_CFG_OFFSET 0XFF5E0024 #undef CRL_APB_IOPLL_CTRL_OFFSET @@ -69,8 +67,6 @@ #define CRL_APB_IOPLL_CTRL_OFFSET 0XFF5E0020 #undef CRL_APB_IOPLL_TO_FPD_CTRL_OFFSET #define CRL_APB_IOPLL_TO_FPD_CTRL_OFFSET 0XFF5E0044 -#undef CRL_APB_IOPLL_FRAC_CFG_OFFSET -#define CRL_APB_IOPLL_FRAC_CFG_OFFSET 0XFF5E0028 #undef CRF_APB_APLL_CFG_OFFSET #define CRF_APB_APLL_CFG_OFFSET 0XFD1A0024 #undef CRF_APB_APLL_CTRL_OFFSET @@ -85,8 +81,6 @@ #define CRF_APB_APLL_CTRL_OFFSET 0XFD1A0020 #undef CRF_APB_APLL_TO_LPD_CTRL_OFFSET #define CRF_APB_APLL_TO_LPD_CTRL_OFFSET 0XFD1A0048 -#undef CRF_APB_APLL_FRAC_CFG_OFFSET -#define CRF_APB_APLL_FRAC_CFG_OFFSET 0XFD1A0028 #undef CRF_APB_DPLL_CFG_OFFSET #define CRF_APB_DPLL_CFG_OFFSET 0XFD1A0030 #undef CRF_APB_DPLL_CTRL_OFFSET @@ -101,8 +95,6 @@ #define CRF_APB_DPLL_CTRL_OFFSET 0XFD1A002C #undef CRF_APB_DPLL_TO_LPD_CTRL_OFFSET #define CRF_APB_DPLL_TO_LPD_CTRL_OFFSET 0XFD1A004C -#undef CRF_APB_DPLL_FRAC_CFG_OFFSET -#define CRF_APB_DPLL_FRAC_CFG_OFFSET 0XFD1A0034 #undef CRF_APB_VPLL_CFG_OFFSET #define CRF_APB_VPLL_CFG_OFFSET 0XFD1A003C #undef CRF_APB_VPLL_CTRL_OFFSET @@ -117,675 +109,770 @@ #define CRF_APB_VPLL_CTRL_OFFSET 0XFD1A0038 #undef CRF_APB_VPLL_TO_LPD_CTRL_OFFSET #define CRF_APB_VPLL_TO_LPD_CTRL_OFFSET 0XFD1A0050 -#undef CRF_APB_VPLL_FRAC_CFG_OFFSET -#define CRF_APB_VPLL_FRAC_CFG_OFFSET 0XFD1A0040 -/*PLL loop filter resistor control*/ +/* +* PLL loop filter resistor control +*/ #undef CRL_APB_RPLL_CFG_RES_DEFVAL #undef CRL_APB_RPLL_CFG_RES_SHIFT #undef CRL_APB_RPLL_CFG_RES_MASK -#define CRL_APB_RPLL_CFG_RES_DEFVAL 0x00000000 -#define CRL_APB_RPLL_CFG_RES_SHIFT 0 -#define CRL_APB_RPLL_CFG_RES_MASK 0x0000000FU +#define CRL_APB_RPLL_CFG_RES_DEFVAL 0x00000000 +#define CRL_APB_RPLL_CFG_RES_SHIFT 0 +#define CRL_APB_RPLL_CFG_RES_MASK 0x0000000FU -/*PLL charge pump control*/ +/* +* PLL charge pump control +*/ #undef CRL_APB_RPLL_CFG_CP_DEFVAL #undef CRL_APB_RPLL_CFG_CP_SHIFT #undef CRL_APB_RPLL_CFG_CP_MASK -#define CRL_APB_RPLL_CFG_CP_DEFVAL 0x00000000 -#define CRL_APB_RPLL_CFG_CP_SHIFT 5 -#define CRL_APB_RPLL_CFG_CP_MASK 0x000001E0U +#define CRL_APB_RPLL_CFG_CP_DEFVAL 0x00000000 +#define CRL_APB_RPLL_CFG_CP_SHIFT 5 +#define CRL_APB_RPLL_CFG_CP_MASK 0x000001E0U -/*PLL loop filter high frequency capacitor control*/ +/* +* PLL loop filter high frequency capacitor control +*/ #undef CRL_APB_RPLL_CFG_LFHF_DEFVAL #undef CRL_APB_RPLL_CFG_LFHF_SHIFT #undef CRL_APB_RPLL_CFG_LFHF_MASK -#define CRL_APB_RPLL_CFG_LFHF_DEFVAL 0x00000000 -#define CRL_APB_RPLL_CFG_LFHF_SHIFT 10 -#define CRL_APB_RPLL_CFG_LFHF_MASK 0x00000C00U +#define CRL_APB_RPLL_CFG_LFHF_DEFVAL 0x00000000 +#define CRL_APB_RPLL_CFG_LFHF_SHIFT 10 +#define CRL_APB_RPLL_CFG_LFHF_MASK 0x00000C00U -/*Lock circuit counter setting*/ +/* +* Lock circuit counter setting +*/ #undef CRL_APB_RPLL_CFG_LOCK_CNT_DEFVAL #undef CRL_APB_RPLL_CFG_LOCK_CNT_SHIFT #undef CRL_APB_RPLL_CFG_LOCK_CNT_MASK -#define CRL_APB_RPLL_CFG_LOCK_CNT_DEFVAL 0x00000000 -#define CRL_APB_RPLL_CFG_LOCK_CNT_SHIFT 13 -#define CRL_APB_RPLL_CFG_LOCK_CNT_MASK 0x007FE000U +#define CRL_APB_RPLL_CFG_LOCK_CNT_DEFVAL 0x00000000 +#define CRL_APB_RPLL_CFG_LOCK_CNT_SHIFT 13 +#define CRL_APB_RPLL_CFG_LOCK_CNT_MASK 0x007FE000U -/*Lock circuit configuration settings for lock windowsize*/ +/* +* Lock circuit configuration settings for lock windowsize +*/ #undef CRL_APB_RPLL_CFG_LOCK_DLY_DEFVAL #undef CRL_APB_RPLL_CFG_LOCK_DLY_SHIFT #undef CRL_APB_RPLL_CFG_LOCK_DLY_MASK -#define CRL_APB_RPLL_CFG_LOCK_DLY_DEFVAL 0x00000000 -#define CRL_APB_RPLL_CFG_LOCK_DLY_SHIFT 25 -#define CRL_APB_RPLL_CFG_LOCK_DLY_MASK 0xFE000000U +#define CRL_APB_RPLL_CFG_LOCK_DLY_DEFVAL 0x00000000 +#define CRL_APB_RPLL_CFG_LOCK_DLY_SHIFT 25 +#define CRL_APB_RPLL_CFG_LOCK_DLY_MASK 0xFE000000U -/*Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_ - ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source*/ +/* +* Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i + * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour + * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source +*/ #undef CRL_APB_RPLL_CTRL_PRE_SRC_DEFVAL #undef CRL_APB_RPLL_CTRL_PRE_SRC_SHIFT #undef CRL_APB_RPLL_CTRL_PRE_SRC_MASK -#define CRL_APB_RPLL_CTRL_PRE_SRC_DEFVAL 0x00012C09 -#define CRL_APB_RPLL_CTRL_PRE_SRC_SHIFT 20 -#define CRL_APB_RPLL_CTRL_PRE_SRC_MASK 0x00700000U +#define CRL_APB_RPLL_CTRL_PRE_SRC_DEFVAL 0x00012C09 +#define CRL_APB_RPLL_CTRL_PRE_SRC_SHIFT 20 +#define CRL_APB_RPLL_CTRL_PRE_SRC_MASK 0x00700000U -/*The integer portion of the feedback divider to the PLL*/ +/* +* The integer portion of the feedback divider to the PLL +*/ #undef CRL_APB_RPLL_CTRL_FBDIV_DEFVAL #undef CRL_APB_RPLL_CTRL_FBDIV_SHIFT #undef CRL_APB_RPLL_CTRL_FBDIV_MASK -#define CRL_APB_RPLL_CTRL_FBDIV_DEFVAL 0x00012C09 -#define CRL_APB_RPLL_CTRL_FBDIV_SHIFT 8 -#define CRL_APB_RPLL_CTRL_FBDIV_MASK 0x00007F00U +#define CRL_APB_RPLL_CTRL_FBDIV_DEFVAL 0x00012C09 +#define CRL_APB_RPLL_CTRL_FBDIV_SHIFT 8 +#define CRL_APB_RPLL_CTRL_FBDIV_MASK 0x00007F00U -/*This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency*/ +/* +* This turns on the divide by 2 that is inside of the PLL. This does not c + * hange the VCO frequency, just the output frequency +*/ #undef CRL_APB_RPLL_CTRL_DIV2_DEFVAL #undef CRL_APB_RPLL_CTRL_DIV2_SHIFT #undef CRL_APB_RPLL_CTRL_DIV2_MASK -#define CRL_APB_RPLL_CTRL_DIV2_DEFVAL 0x00012C09 -#define CRL_APB_RPLL_CTRL_DIV2_SHIFT 16 -#define CRL_APB_RPLL_CTRL_DIV2_MASK 0x00010000U +#define CRL_APB_RPLL_CTRL_DIV2_DEFVAL 0x00012C09 +#define CRL_APB_RPLL_CTRL_DIV2_SHIFT 16 +#define CRL_APB_RPLL_CTRL_DIV2_MASK 0x00010000U -/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/ +/* +* Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) +*/ #undef CRL_APB_RPLL_CTRL_BYPASS_DEFVAL #undef CRL_APB_RPLL_CTRL_BYPASS_SHIFT #undef CRL_APB_RPLL_CTRL_BYPASS_MASK -#define CRL_APB_RPLL_CTRL_BYPASS_DEFVAL 0x00012C09 -#define CRL_APB_RPLL_CTRL_BYPASS_SHIFT 3 -#define CRL_APB_RPLL_CTRL_BYPASS_MASK 0x00000008U +#define CRL_APB_RPLL_CTRL_BYPASS_DEFVAL 0x00012C09 +#define CRL_APB_RPLL_CTRL_BYPASS_SHIFT 3 +#define CRL_APB_RPLL_CTRL_BYPASS_MASK 0x00000008U -/*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/ +/* +* Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. +*/ #undef CRL_APB_RPLL_CTRL_RESET_DEFVAL #undef CRL_APB_RPLL_CTRL_RESET_SHIFT #undef CRL_APB_RPLL_CTRL_RESET_MASK -#define CRL_APB_RPLL_CTRL_RESET_DEFVAL 0x00012C09 -#define CRL_APB_RPLL_CTRL_RESET_SHIFT 0 -#define CRL_APB_RPLL_CTRL_RESET_MASK 0x00000001U +#define CRL_APB_RPLL_CTRL_RESET_DEFVAL 0x00012C09 +#define CRL_APB_RPLL_CTRL_RESET_SHIFT 0 +#define CRL_APB_RPLL_CTRL_RESET_MASK 0x00000001U -/*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/ +/* +* Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. +*/ #undef CRL_APB_RPLL_CTRL_RESET_DEFVAL #undef CRL_APB_RPLL_CTRL_RESET_SHIFT #undef CRL_APB_RPLL_CTRL_RESET_MASK -#define CRL_APB_RPLL_CTRL_RESET_DEFVAL 0x00012C09 -#define CRL_APB_RPLL_CTRL_RESET_SHIFT 0 -#define CRL_APB_RPLL_CTRL_RESET_MASK 0x00000001U +#define CRL_APB_RPLL_CTRL_RESET_DEFVAL 0x00012C09 +#define CRL_APB_RPLL_CTRL_RESET_SHIFT 0 +#define CRL_APB_RPLL_CTRL_RESET_MASK 0x00000001U -/*RPLL is locked*/ +/* +* RPLL is locked +*/ #undef CRL_APB_PLL_STATUS_RPLL_LOCK_DEFVAL #undef CRL_APB_PLL_STATUS_RPLL_LOCK_SHIFT #undef CRL_APB_PLL_STATUS_RPLL_LOCK_MASK -#define CRL_APB_PLL_STATUS_RPLL_LOCK_DEFVAL 0x00000018 -#define CRL_APB_PLL_STATUS_RPLL_LOCK_SHIFT 1 -#define CRL_APB_PLL_STATUS_RPLL_LOCK_MASK 0x00000002U +#define CRL_APB_PLL_STATUS_RPLL_LOCK_DEFVAL 0x00000018 +#define CRL_APB_PLL_STATUS_RPLL_LOCK_SHIFT 1 +#define CRL_APB_PLL_STATUS_RPLL_LOCK_MASK 0x00000002U #define CRL_APB_PLL_STATUS_OFFSET 0XFF5E0040 -/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/ +/* +* Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) +*/ #undef CRL_APB_RPLL_CTRL_BYPASS_DEFVAL #undef CRL_APB_RPLL_CTRL_BYPASS_SHIFT #undef CRL_APB_RPLL_CTRL_BYPASS_MASK -#define CRL_APB_RPLL_CTRL_BYPASS_DEFVAL 0x00012C09 -#define CRL_APB_RPLL_CTRL_BYPASS_SHIFT 3 -#define CRL_APB_RPLL_CTRL_BYPASS_MASK 0x00000008U +#define CRL_APB_RPLL_CTRL_BYPASS_DEFVAL 0x00012C09 +#define CRL_APB_RPLL_CTRL_BYPASS_SHIFT 3 +#define CRL_APB_RPLL_CTRL_BYPASS_MASK 0x00000008U -/*Divisor value for this clock.*/ +/* +* Divisor value for this clock. +*/ #undef CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL #undef CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_SHIFT #undef CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_MASK -#define CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL 0x00000400 -#define CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL 0x00000400 +#define CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_MASK 0x00003F00U -/*Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona - mode and uses DATA of this register for the fractional portion of the feedback divider.*/ -#undef CRL_APB_RPLL_FRAC_CFG_ENABLED_DEFVAL -#undef CRL_APB_RPLL_FRAC_CFG_ENABLED_SHIFT -#undef CRL_APB_RPLL_FRAC_CFG_ENABLED_MASK -#define CRL_APB_RPLL_FRAC_CFG_ENABLED_DEFVAL 0x00000000 -#define CRL_APB_RPLL_FRAC_CFG_ENABLED_SHIFT 31 -#define CRL_APB_RPLL_FRAC_CFG_ENABLED_MASK 0x80000000U - -/*Fractional value for the Feedback value.*/ -#undef CRL_APB_RPLL_FRAC_CFG_DATA_DEFVAL -#undef CRL_APB_RPLL_FRAC_CFG_DATA_SHIFT -#undef CRL_APB_RPLL_FRAC_CFG_DATA_MASK -#define CRL_APB_RPLL_FRAC_CFG_DATA_DEFVAL 0x00000000 -#define CRL_APB_RPLL_FRAC_CFG_DATA_SHIFT 0 -#define CRL_APB_RPLL_FRAC_CFG_DATA_MASK 0x0000FFFFU - -/*PLL loop filter resistor control*/ +/* +* PLL loop filter resistor control +*/ #undef CRL_APB_IOPLL_CFG_RES_DEFVAL #undef CRL_APB_IOPLL_CFG_RES_SHIFT #undef CRL_APB_IOPLL_CFG_RES_MASK -#define CRL_APB_IOPLL_CFG_RES_DEFVAL 0x00000000 -#define CRL_APB_IOPLL_CFG_RES_SHIFT 0 -#define CRL_APB_IOPLL_CFG_RES_MASK 0x0000000FU +#define CRL_APB_IOPLL_CFG_RES_DEFVAL 0x00000000 +#define CRL_APB_IOPLL_CFG_RES_SHIFT 0 +#define CRL_APB_IOPLL_CFG_RES_MASK 0x0000000FU -/*PLL charge pump control*/ +/* +* PLL charge pump control +*/ #undef CRL_APB_IOPLL_CFG_CP_DEFVAL #undef CRL_APB_IOPLL_CFG_CP_SHIFT #undef CRL_APB_IOPLL_CFG_CP_MASK -#define CRL_APB_IOPLL_CFG_CP_DEFVAL 0x00000000 -#define CRL_APB_IOPLL_CFG_CP_SHIFT 5 -#define CRL_APB_IOPLL_CFG_CP_MASK 0x000001E0U +#define CRL_APB_IOPLL_CFG_CP_DEFVAL 0x00000000 +#define CRL_APB_IOPLL_CFG_CP_SHIFT 5 +#define CRL_APB_IOPLL_CFG_CP_MASK 0x000001E0U -/*PLL loop filter high frequency capacitor control*/ +/* +* PLL loop filter high frequency capacitor control +*/ #undef CRL_APB_IOPLL_CFG_LFHF_DEFVAL #undef CRL_APB_IOPLL_CFG_LFHF_SHIFT #undef CRL_APB_IOPLL_CFG_LFHF_MASK -#define CRL_APB_IOPLL_CFG_LFHF_DEFVAL 0x00000000 -#define CRL_APB_IOPLL_CFG_LFHF_SHIFT 10 -#define CRL_APB_IOPLL_CFG_LFHF_MASK 0x00000C00U +#define CRL_APB_IOPLL_CFG_LFHF_DEFVAL 0x00000000 +#define CRL_APB_IOPLL_CFG_LFHF_SHIFT 10 +#define CRL_APB_IOPLL_CFG_LFHF_MASK 0x00000C00U -/*Lock circuit counter setting*/ +/* +* Lock circuit counter setting +*/ #undef CRL_APB_IOPLL_CFG_LOCK_CNT_DEFVAL #undef CRL_APB_IOPLL_CFG_LOCK_CNT_SHIFT #undef CRL_APB_IOPLL_CFG_LOCK_CNT_MASK -#define CRL_APB_IOPLL_CFG_LOCK_CNT_DEFVAL 0x00000000 -#define CRL_APB_IOPLL_CFG_LOCK_CNT_SHIFT 13 -#define CRL_APB_IOPLL_CFG_LOCK_CNT_MASK 0x007FE000U +#define CRL_APB_IOPLL_CFG_LOCK_CNT_DEFVAL 0x00000000 +#define CRL_APB_IOPLL_CFG_LOCK_CNT_SHIFT 13 +#define CRL_APB_IOPLL_CFG_LOCK_CNT_MASK 0x007FE000U -/*Lock circuit configuration settings for lock windowsize*/ +/* +* Lock circuit configuration settings for lock windowsize +*/ #undef CRL_APB_IOPLL_CFG_LOCK_DLY_DEFVAL #undef CRL_APB_IOPLL_CFG_LOCK_DLY_SHIFT #undef CRL_APB_IOPLL_CFG_LOCK_DLY_MASK -#define CRL_APB_IOPLL_CFG_LOCK_DLY_DEFVAL 0x00000000 -#define CRL_APB_IOPLL_CFG_LOCK_DLY_SHIFT 25 -#define CRL_APB_IOPLL_CFG_LOCK_DLY_MASK 0xFE000000U +#define CRL_APB_IOPLL_CFG_LOCK_DLY_DEFVAL 0x00000000 +#define CRL_APB_IOPLL_CFG_LOCK_DLY_SHIFT 25 +#define CRL_APB_IOPLL_CFG_LOCK_DLY_MASK 0xFE000000U -/*Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_ - ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source*/ +/* +* Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i + * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour + * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source +*/ #undef CRL_APB_IOPLL_CTRL_PRE_SRC_DEFVAL #undef CRL_APB_IOPLL_CTRL_PRE_SRC_SHIFT #undef CRL_APB_IOPLL_CTRL_PRE_SRC_MASK -#define CRL_APB_IOPLL_CTRL_PRE_SRC_DEFVAL 0x00012C09 -#define CRL_APB_IOPLL_CTRL_PRE_SRC_SHIFT 20 -#define CRL_APB_IOPLL_CTRL_PRE_SRC_MASK 0x00700000U +#define CRL_APB_IOPLL_CTRL_PRE_SRC_DEFVAL 0x00012C09 +#define CRL_APB_IOPLL_CTRL_PRE_SRC_SHIFT 20 +#define CRL_APB_IOPLL_CTRL_PRE_SRC_MASK 0x00700000U -/*The integer portion of the feedback divider to the PLL*/ +/* +* The integer portion of the feedback divider to the PLL +*/ #undef CRL_APB_IOPLL_CTRL_FBDIV_DEFVAL #undef CRL_APB_IOPLL_CTRL_FBDIV_SHIFT #undef CRL_APB_IOPLL_CTRL_FBDIV_MASK -#define CRL_APB_IOPLL_CTRL_FBDIV_DEFVAL 0x00012C09 -#define CRL_APB_IOPLL_CTRL_FBDIV_SHIFT 8 -#define CRL_APB_IOPLL_CTRL_FBDIV_MASK 0x00007F00U +#define CRL_APB_IOPLL_CTRL_FBDIV_DEFVAL 0x00012C09 +#define CRL_APB_IOPLL_CTRL_FBDIV_SHIFT 8 +#define CRL_APB_IOPLL_CTRL_FBDIV_MASK 0x00007F00U -/*This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency*/ +/* +* This turns on the divide by 2 that is inside of the PLL. This does not c + * hange the VCO frequency, just the output frequency +*/ #undef CRL_APB_IOPLL_CTRL_DIV2_DEFVAL #undef CRL_APB_IOPLL_CTRL_DIV2_SHIFT #undef CRL_APB_IOPLL_CTRL_DIV2_MASK -#define CRL_APB_IOPLL_CTRL_DIV2_DEFVAL 0x00012C09 -#define CRL_APB_IOPLL_CTRL_DIV2_SHIFT 16 -#define CRL_APB_IOPLL_CTRL_DIV2_MASK 0x00010000U +#define CRL_APB_IOPLL_CTRL_DIV2_DEFVAL 0x00012C09 +#define CRL_APB_IOPLL_CTRL_DIV2_SHIFT 16 +#define CRL_APB_IOPLL_CTRL_DIV2_MASK 0x00010000U -/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/ +/* +* Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) +*/ #undef CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL #undef CRL_APB_IOPLL_CTRL_BYPASS_SHIFT #undef CRL_APB_IOPLL_CTRL_BYPASS_MASK -#define CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL 0x00012C09 -#define CRL_APB_IOPLL_CTRL_BYPASS_SHIFT 3 -#define CRL_APB_IOPLL_CTRL_BYPASS_MASK 0x00000008U +#define CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL 0x00012C09 +#define CRL_APB_IOPLL_CTRL_BYPASS_SHIFT 3 +#define CRL_APB_IOPLL_CTRL_BYPASS_MASK 0x00000008U -/*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/ +/* +* Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. +*/ #undef CRL_APB_IOPLL_CTRL_RESET_DEFVAL #undef CRL_APB_IOPLL_CTRL_RESET_SHIFT #undef CRL_APB_IOPLL_CTRL_RESET_MASK -#define CRL_APB_IOPLL_CTRL_RESET_DEFVAL 0x00012C09 -#define CRL_APB_IOPLL_CTRL_RESET_SHIFT 0 -#define CRL_APB_IOPLL_CTRL_RESET_MASK 0x00000001U +#define CRL_APB_IOPLL_CTRL_RESET_DEFVAL 0x00012C09 +#define CRL_APB_IOPLL_CTRL_RESET_SHIFT 0 +#define CRL_APB_IOPLL_CTRL_RESET_MASK 0x00000001U -/*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/ +/* +* Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. +*/ #undef CRL_APB_IOPLL_CTRL_RESET_DEFVAL #undef CRL_APB_IOPLL_CTRL_RESET_SHIFT #undef CRL_APB_IOPLL_CTRL_RESET_MASK -#define CRL_APB_IOPLL_CTRL_RESET_DEFVAL 0x00012C09 -#define CRL_APB_IOPLL_CTRL_RESET_SHIFT 0 -#define CRL_APB_IOPLL_CTRL_RESET_MASK 0x00000001U +#define CRL_APB_IOPLL_CTRL_RESET_DEFVAL 0x00012C09 +#define CRL_APB_IOPLL_CTRL_RESET_SHIFT 0 +#define CRL_APB_IOPLL_CTRL_RESET_MASK 0x00000001U -/*IOPLL is locked*/ +/* +* IOPLL is locked +*/ #undef CRL_APB_PLL_STATUS_IOPLL_LOCK_DEFVAL #undef CRL_APB_PLL_STATUS_IOPLL_LOCK_SHIFT #undef CRL_APB_PLL_STATUS_IOPLL_LOCK_MASK -#define CRL_APB_PLL_STATUS_IOPLL_LOCK_DEFVAL 0x00000018 -#define CRL_APB_PLL_STATUS_IOPLL_LOCK_SHIFT 0 -#define CRL_APB_PLL_STATUS_IOPLL_LOCK_MASK 0x00000001U +#define CRL_APB_PLL_STATUS_IOPLL_LOCK_DEFVAL 0x00000018 +#define CRL_APB_PLL_STATUS_IOPLL_LOCK_SHIFT 0 +#define CRL_APB_PLL_STATUS_IOPLL_LOCK_MASK 0x00000001U #define CRL_APB_PLL_STATUS_OFFSET 0XFF5E0040 -/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/ +/* +* Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) +*/ #undef CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL #undef CRL_APB_IOPLL_CTRL_BYPASS_SHIFT #undef CRL_APB_IOPLL_CTRL_BYPASS_MASK -#define CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL 0x00012C09 -#define CRL_APB_IOPLL_CTRL_BYPASS_SHIFT 3 -#define CRL_APB_IOPLL_CTRL_BYPASS_MASK 0x00000008U +#define CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL 0x00012C09 +#define CRL_APB_IOPLL_CTRL_BYPASS_SHIFT 3 +#define CRL_APB_IOPLL_CTRL_BYPASS_MASK 0x00000008U -/*Divisor value for this clock.*/ +/* +* Divisor value for this clock. +*/ #undef CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL #undef CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_SHIFT #undef CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_MASK -#define CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL 0x00000400 -#define CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL 0x00000400 +#define CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_MASK 0x00003F00U -/*Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona - mode and uses DATA of this register for the fractional portion of the feedback divider.*/ -#undef CRL_APB_IOPLL_FRAC_CFG_ENABLED_DEFVAL -#undef CRL_APB_IOPLL_FRAC_CFG_ENABLED_SHIFT -#undef CRL_APB_IOPLL_FRAC_CFG_ENABLED_MASK -#define CRL_APB_IOPLL_FRAC_CFG_ENABLED_DEFVAL 0x00000000 -#define CRL_APB_IOPLL_FRAC_CFG_ENABLED_SHIFT 31 -#define CRL_APB_IOPLL_FRAC_CFG_ENABLED_MASK 0x80000000U - -/*Fractional value for the Feedback value.*/ -#undef CRL_APB_IOPLL_FRAC_CFG_DATA_DEFVAL -#undef CRL_APB_IOPLL_FRAC_CFG_DATA_SHIFT -#undef CRL_APB_IOPLL_FRAC_CFG_DATA_MASK -#define CRL_APB_IOPLL_FRAC_CFG_DATA_DEFVAL 0x00000000 -#define CRL_APB_IOPLL_FRAC_CFG_DATA_SHIFT 0 -#define CRL_APB_IOPLL_FRAC_CFG_DATA_MASK 0x0000FFFFU - -/*PLL loop filter resistor control*/ +/* +* PLL loop filter resistor control +*/ #undef CRF_APB_APLL_CFG_RES_DEFVAL #undef CRF_APB_APLL_CFG_RES_SHIFT #undef CRF_APB_APLL_CFG_RES_MASK -#define CRF_APB_APLL_CFG_RES_DEFVAL 0x00000000 -#define CRF_APB_APLL_CFG_RES_SHIFT 0 -#define CRF_APB_APLL_CFG_RES_MASK 0x0000000FU +#define CRF_APB_APLL_CFG_RES_DEFVAL 0x00000000 +#define CRF_APB_APLL_CFG_RES_SHIFT 0 +#define CRF_APB_APLL_CFG_RES_MASK 0x0000000FU -/*PLL charge pump control*/ +/* +* PLL charge pump control +*/ #undef CRF_APB_APLL_CFG_CP_DEFVAL #undef CRF_APB_APLL_CFG_CP_SHIFT #undef CRF_APB_APLL_CFG_CP_MASK -#define CRF_APB_APLL_CFG_CP_DEFVAL 0x00000000 -#define CRF_APB_APLL_CFG_CP_SHIFT 5 -#define CRF_APB_APLL_CFG_CP_MASK 0x000001E0U +#define CRF_APB_APLL_CFG_CP_DEFVAL 0x00000000 +#define CRF_APB_APLL_CFG_CP_SHIFT 5 +#define CRF_APB_APLL_CFG_CP_MASK 0x000001E0U -/*PLL loop filter high frequency capacitor control*/ +/* +* PLL loop filter high frequency capacitor control +*/ #undef CRF_APB_APLL_CFG_LFHF_DEFVAL #undef CRF_APB_APLL_CFG_LFHF_SHIFT #undef CRF_APB_APLL_CFG_LFHF_MASK -#define CRF_APB_APLL_CFG_LFHF_DEFVAL 0x00000000 -#define CRF_APB_APLL_CFG_LFHF_SHIFT 10 -#define CRF_APB_APLL_CFG_LFHF_MASK 0x00000C00U +#define CRF_APB_APLL_CFG_LFHF_DEFVAL 0x00000000 +#define CRF_APB_APLL_CFG_LFHF_SHIFT 10 +#define CRF_APB_APLL_CFG_LFHF_MASK 0x00000C00U -/*Lock circuit counter setting*/ +/* +* Lock circuit counter setting +*/ #undef CRF_APB_APLL_CFG_LOCK_CNT_DEFVAL #undef CRF_APB_APLL_CFG_LOCK_CNT_SHIFT #undef CRF_APB_APLL_CFG_LOCK_CNT_MASK -#define CRF_APB_APLL_CFG_LOCK_CNT_DEFVAL 0x00000000 -#define CRF_APB_APLL_CFG_LOCK_CNT_SHIFT 13 -#define CRF_APB_APLL_CFG_LOCK_CNT_MASK 0x007FE000U +#define CRF_APB_APLL_CFG_LOCK_CNT_DEFVAL 0x00000000 +#define CRF_APB_APLL_CFG_LOCK_CNT_SHIFT 13 +#define CRF_APB_APLL_CFG_LOCK_CNT_MASK 0x007FE000U -/*Lock circuit configuration settings for lock windowsize*/ +/* +* Lock circuit configuration settings for lock windowsize +*/ #undef CRF_APB_APLL_CFG_LOCK_DLY_DEFVAL #undef CRF_APB_APLL_CFG_LOCK_DLY_SHIFT #undef CRF_APB_APLL_CFG_LOCK_DLY_MASK -#define CRF_APB_APLL_CFG_LOCK_DLY_DEFVAL 0x00000000 -#define CRF_APB_APLL_CFG_LOCK_DLY_SHIFT 25 -#define CRF_APB_APLL_CFG_LOCK_DLY_MASK 0xFE000000U +#define CRF_APB_APLL_CFG_LOCK_DLY_DEFVAL 0x00000000 +#define CRF_APB_APLL_CFG_LOCK_DLY_SHIFT 25 +#define CRF_APB_APLL_CFG_LOCK_DLY_MASK 0xFE000000U -/*Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_ - ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source*/ +/* +* Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i + * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour + * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source +*/ #undef CRF_APB_APLL_CTRL_PRE_SRC_DEFVAL #undef CRF_APB_APLL_CTRL_PRE_SRC_SHIFT #undef CRF_APB_APLL_CTRL_PRE_SRC_MASK -#define CRF_APB_APLL_CTRL_PRE_SRC_DEFVAL 0x00012C09 -#define CRF_APB_APLL_CTRL_PRE_SRC_SHIFT 20 -#define CRF_APB_APLL_CTRL_PRE_SRC_MASK 0x00700000U +#define CRF_APB_APLL_CTRL_PRE_SRC_DEFVAL 0x00012C09 +#define CRF_APB_APLL_CTRL_PRE_SRC_SHIFT 20 +#define CRF_APB_APLL_CTRL_PRE_SRC_MASK 0x00700000U -/*The integer portion of the feedback divider to the PLL*/ +/* +* The integer portion of the feedback divider to the PLL +*/ #undef CRF_APB_APLL_CTRL_FBDIV_DEFVAL #undef CRF_APB_APLL_CTRL_FBDIV_SHIFT #undef CRF_APB_APLL_CTRL_FBDIV_MASK -#define CRF_APB_APLL_CTRL_FBDIV_DEFVAL 0x00012C09 -#define CRF_APB_APLL_CTRL_FBDIV_SHIFT 8 -#define CRF_APB_APLL_CTRL_FBDIV_MASK 0x00007F00U +#define CRF_APB_APLL_CTRL_FBDIV_DEFVAL 0x00012C09 +#define CRF_APB_APLL_CTRL_FBDIV_SHIFT 8 +#define CRF_APB_APLL_CTRL_FBDIV_MASK 0x00007F00U -/*This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency*/ +/* +* This turns on the divide by 2 that is inside of the PLL. This does not c + * hange the VCO frequency, just the output frequency +*/ #undef CRF_APB_APLL_CTRL_DIV2_DEFVAL #undef CRF_APB_APLL_CTRL_DIV2_SHIFT #undef CRF_APB_APLL_CTRL_DIV2_MASK -#define CRF_APB_APLL_CTRL_DIV2_DEFVAL 0x00012C09 -#define CRF_APB_APLL_CTRL_DIV2_SHIFT 16 -#define CRF_APB_APLL_CTRL_DIV2_MASK 0x00010000U +#define CRF_APB_APLL_CTRL_DIV2_DEFVAL 0x00012C09 +#define CRF_APB_APLL_CTRL_DIV2_SHIFT 16 +#define CRF_APB_APLL_CTRL_DIV2_MASK 0x00010000U -/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/ +/* +* Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) +*/ #undef CRF_APB_APLL_CTRL_BYPASS_DEFVAL #undef CRF_APB_APLL_CTRL_BYPASS_SHIFT #undef CRF_APB_APLL_CTRL_BYPASS_MASK -#define CRF_APB_APLL_CTRL_BYPASS_DEFVAL 0x00012C09 -#define CRF_APB_APLL_CTRL_BYPASS_SHIFT 3 -#define CRF_APB_APLL_CTRL_BYPASS_MASK 0x00000008U +#define CRF_APB_APLL_CTRL_BYPASS_DEFVAL 0x00012C09 +#define CRF_APB_APLL_CTRL_BYPASS_SHIFT 3 +#define CRF_APB_APLL_CTRL_BYPASS_MASK 0x00000008U -/*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/ +/* +* Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. +*/ #undef CRF_APB_APLL_CTRL_RESET_DEFVAL #undef CRF_APB_APLL_CTRL_RESET_SHIFT #undef CRF_APB_APLL_CTRL_RESET_MASK -#define CRF_APB_APLL_CTRL_RESET_DEFVAL 0x00012C09 -#define CRF_APB_APLL_CTRL_RESET_SHIFT 0 -#define CRF_APB_APLL_CTRL_RESET_MASK 0x00000001U +#define CRF_APB_APLL_CTRL_RESET_DEFVAL 0x00012C09 +#define CRF_APB_APLL_CTRL_RESET_SHIFT 0 +#define CRF_APB_APLL_CTRL_RESET_MASK 0x00000001U -/*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/ +/* +* Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. +*/ #undef CRF_APB_APLL_CTRL_RESET_DEFVAL #undef CRF_APB_APLL_CTRL_RESET_SHIFT #undef CRF_APB_APLL_CTRL_RESET_MASK -#define CRF_APB_APLL_CTRL_RESET_DEFVAL 0x00012C09 -#define CRF_APB_APLL_CTRL_RESET_SHIFT 0 -#define CRF_APB_APLL_CTRL_RESET_MASK 0x00000001U +#define CRF_APB_APLL_CTRL_RESET_DEFVAL 0x00012C09 +#define CRF_APB_APLL_CTRL_RESET_SHIFT 0 +#define CRF_APB_APLL_CTRL_RESET_MASK 0x00000001U -/*APLL is locked*/ +/* +* APLL is locked +*/ #undef CRF_APB_PLL_STATUS_APLL_LOCK_DEFVAL #undef CRF_APB_PLL_STATUS_APLL_LOCK_SHIFT #undef CRF_APB_PLL_STATUS_APLL_LOCK_MASK -#define CRF_APB_PLL_STATUS_APLL_LOCK_DEFVAL 0x00000038 -#define CRF_APB_PLL_STATUS_APLL_LOCK_SHIFT 0 -#define CRF_APB_PLL_STATUS_APLL_LOCK_MASK 0x00000001U +#define CRF_APB_PLL_STATUS_APLL_LOCK_DEFVAL 0x00000038 +#define CRF_APB_PLL_STATUS_APLL_LOCK_SHIFT 0 +#define CRF_APB_PLL_STATUS_APLL_LOCK_MASK 0x00000001U #define CRF_APB_PLL_STATUS_OFFSET 0XFD1A0044 -/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/ +/* +* Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) +*/ #undef CRF_APB_APLL_CTRL_BYPASS_DEFVAL #undef CRF_APB_APLL_CTRL_BYPASS_SHIFT #undef CRF_APB_APLL_CTRL_BYPASS_MASK -#define CRF_APB_APLL_CTRL_BYPASS_DEFVAL 0x00012C09 -#define CRF_APB_APLL_CTRL_BYPASS_SHIFT 3 -#define CRF_APB_APLL_CTRL_BYPASS_MASK 0x00000008U +#define CRF_APB_APLL_CTRL_BYPASS_DEFVAL 0x00012C09 +#define CRF_APB_APLL_CTRL_BYPASS_SHIFT 3 +#define CRF_APB_APLL_CTRL_BYPASS_MASK 0x00000008U -/*Divisor value for this clock.*/ +/* +* Divisor value for this clock. +*/ #undef CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_DEFVAL #undef CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_SHIFT #undef CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_MASK -#define CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_DEFVAL 0x00000400 -#define CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_SHIFT 8 -#define CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_DEFVAL 0x00000400 +#define CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_MASK 0x00003F00U -/*Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona - mode and uses DATA of this register for the fractional portion of the feedback divider.*/ -#undef CRF_APB_APLL_FRAC_CFG_ENABLED_DEFVAL -#undef CRF_APB_APLL_FRAC_CFG_ENABLED_SHIFT -#undef CRF_APB_APLL_FRAC_CFG_ENABLED_MASK -#define CRF_APB_APLL_FRAC_CFG_ENABLED_DEFVAL 0x00000000 -#define CRF_APB_APLL_FRAC_CFG_ENABLED_SHIFT 31 -#define CRF_APB_APLL_FRAC_CFG_ENABLED_MASK 0x80000000U - -/*Fractional value for the Feedback value.*/ -#undef CRF_APB_APLL_FRAC_CFG_DATA_DEFVAL -#undef CRF_APB_APLL_FRAC_CFG_DATA_SHIFT -#undef CRF_APB_APLL_FRAC_CFG_DATA_MASK -#define CRF_APB_APLL_FRAC_CFG_DATA_DEFVAL 0x00000000 -#define CRF_APB_APLL_FRAC_CFG_DATA_SHIFT 0 -#define CRF_APB_APLL_FRAC_CFG_DATA_MASK 0x0000FFFFU - -/*PLL loop filter resistor control*/ +/* +* PLL loop filter resistor control +*/ #undef CRF_APB_DPLL_CFG_RES_DEFVAL #undef CRF_APB_DPLL_CFG_RES_SHIFT #undef CRF_APB_DPLL_CFG_RES_MASK -#define CRF_APB_DPLL_CFG_RES_DEFVAL 0x00000000 -#define CRF_APB_DPLL_CFG_RES_SHIFT 0 -#define CRF_APB_DPLL_CFG_RES_MASK 0x0000000FU +#define CRF_APB_DPLL_CFG_RES_DEFVAL 0x00000000 +#define CRF_APB_DPLL_CFG_RES_SHIFT 0 +#define CRF_APB_DPLL_CFG_RES_MASK 0x0000000FU -/*PLL charge pump control*/ +/* +* PLL charge pump control +*/ #undef CRF_APB_DPLL_CFG_CP_DEFVAL #undef CRF_APB_DPLL_CFG_CP_SHIFT #undef CRF_APB_DPLL_CFG_CP_MASK -#define CRF_APB_DPLL_CFG_CP_DEFVAL 0x00000000 -#define CRF_APB_DPLL_CFG_CP_SHIFT 5 -#define CRF_APB_DPLL_CFG_CP_MASK 0x000001E0U +#define CRF_APB_DPLL_CFG_CP_DEFVAL 0x00000000 +#define CRF_APB_DPLL_CFG_CP_SHIFT 5 +#define CRF_APB_DPLL_CFG_CP_MASK 0x000001E0U -/*PLL loop filter high frequency capacitor control*/ +/* +* PLL loop filter high frequency capacitor control +*/ #undef CRF_APB_DPLL_CFG_LFHF_DEFVAL #undef CRF_APB_DPLL_CFG_LFHF_SHIFT #undef CRF_APB_DPLL_CFG_LFHF_MASK -#define CRF_APB_DPLL_CFG_LFHF_DEFVAL 0x00000000 -#define CRF_APB_DPLL_CFG_LFHF_SHIFT 10 -#define CRF_APB_DPLL_CFG_LFHF_MASK 0x00000C00U +#define CRF_APB_DPLL_CFG_LFHF_DEFVAL 0x00000000 +#define CRF_APB_DPLL_CFG_LFHF_SHIFT 10 +#define CRF_APB_DPLL_CFG_LFHF_MASK 0x00000C00U -/*Lock circuit counter setting*/ +/* +* Lock circuit counter setting +*/ #undef CRF_APB_DPLL_CFG_LOCK_CNT_DEFVAL #undef CRF_APB_DPLL_CFG_LOCK_CNT_SHIFT #undef CRF_APB_DPLL_CFG_LOCK_CNT_MASK -#define CRF_APB_DPLL_CFG_LOCK_CNT_DEFVAL 0x00000000 -#define CRF_APB_DPLL_CFG_LOCK_CNT_SHIFT 13 -#define CRF_APB_DPLL_CFG_LOCK_CNT_MASK 0x007FE000U +#define CRF_APB_DPLL_CFG_LOCK_CNT_DEFVAL 0x00000000 +#define CRF_APB_DPLL_CFG_LOCK_CNT_SHIFT 13 +#define CRF_APB_DPLL_CFG_LOCK_CNT_MASK 0x007FE000U -/*Lock circuit configuration settings for lock windowsize*/ +/* +* Lock circuit configuration settings for lock windowsize +*/ #undef CRF_APB_DPLL_CFG_LOCK_DLY_DEFVAL #undef CRF_APB_DPLL_CFG_LOCK_DLY_SHIFT #undef CRF_APB_DPLL_CFG_LOCK_DLY_MASK -#define CRF_APB_DPLL_CFG_LOCK_DLY_DEFVAL 0x00000000 -#define CRF_APB_DPLL_CFG_LOCK_DLY_SHIFT 25 -#define CRF_APB_DPLL_CFG_LOCK_DLY_MASK 0xFE000000U +#define CRF_APB_DPLL_CFG_LOCK_DLY_DEFVAL 0x00000000 +#define CRF_APB_DPLL_CFG_LOCK_DLY_SHIFT 25 +#define CRF_APB_DPLL_CFG_LOCK_DLY_MASK 0xFE000000U -/*Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_ - ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source*/ +/* +* Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i + * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour + * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source +*/ #undef CRF_APB_DPLL_CTRL_PRE_SRC_DEFVAL #undef CRF_APB_DPLL_CTRL_PRE_SRC_SHIFT #undef CRF_APB_DPLL_CTRL_PRE_SRC_MASK -#define CRF_APB_DPLL_CTRL_PRE_SRC_DEFVAL 0x00002C09 -#define CRF_APB_DPLL_CTRL_PRE_SRC_SHIFT 20 -#define CRF_APB_DPLL_CTRL_PRE_SRC_MASK 0x00700000U +#define CRF_APB_DPLL_CTRL_PRE_SRC_DEFVAL 0x00002C09 +#define CRF_APB_DPLL_CTRL_PRE_SRC_SHIFT 20 +#define CRF_APB_DPLL_CTRL_PRE_SRC_MASK 0x00700000U -/*The integer portion of the feedback divider to the PLL*/ +/* +* The integer portion of the feedback divider to the PLL +*/ #undef CRF_APB_DPLL_CTRL_FBDIV_DEFVAL #undef CRF_APB_DPLL_CTRL_FBDIV_SHIFT #undef CRF_APB_DPLL_CTRL_FBDIV_MASK -#define CRF_APB_DPLL_CTRL_FBDIV_DEFVAL 0x00002C09 -#define CRF_APB_DPLL_CTRL_FBDIV_SHIFT 8 -#define CRF_APB_DPLL_CTRL_FBDIV_MASK 0x00007F00U +#define CRF_APB_DPLL_CTRL_FBDIV_DEFVAL 0x00002C09 +#define CRF_APB_DPLL_CTRL_FBDIV_SHIFT 8 +#define CRF_APB_DPLL_CTRL_FBDIV_MASK 0x00007F00U -/*This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency*/ +/* +* This turns on the divide by 2 that is inside of the PLL. This does not c + * hange the VCO frequency, just the output frequency +*/ #undef CRF_APB_DPLL_CTRL_DIV2_DEFVAL #undef CRF_APB_DPLL_CTRL_DIV2_SHIFT #undef CRF_APB_DPLL_CTRL_DIV2_MASK -#define CRF_APB_DPLL_CTRL_DIV2_DEFVAL 0x00002C09 -#define CRF_APB_DPLL_CTRL_DIV2_SHIFT 16 -#define CRF_APB_DPLL_CTRL_DIV2_MASK 0x00010000U +#define CRF_APB_DPLL_CTRL_DIV2_DEFVAL 0x00002C09 +#define CRF_APB_DPLL_CTRL_DIV2_SHIFT 16 +#define CRF_APB_DPLL_CTRL_DIV2_MASK 0x00010000U -/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/ +/* +* Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) +*/ #undef CRF_APB_DPLL_CTRL_BYPASS_DEFVAL #undef CRF_APB_DPLL_CTRL_BYPASS_SHIFT #undef CRF_APB_DPLL_CTRL_BYPASS_MASK -#define CRF_APB_DPLL_CTRL_BYPASS_DEFVAL 0x00002C09 -#define CRF_APB_DPLL_CTRL_BYPASS_SHIFT 3 -#define CRF_APB_DPLL_CTRL_BYPASS_MASK 0x00000008U +#define CRF_APB_DPLL_CTRL_BYPASS_DEFVAL 0x00002C09 +#define CRF_APB_DPLL_CTRL_BYPASS_SHIFT 3 +#define CRF_APB_DPLL_CTRL_BYPASS_MASK 0x00000008U -/*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/ +/* +* Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. +*/ #undef CRF_APB_DPLL_CTRL_RESET_DEFVAL #undef CRF_APB_DPLL_CTRL_RESET_SHIFT #undef CRF_APB_DPLL_CTRL_RESET_MASK -#define CRF_APB_DPLL_CTRL_RESET_DEFVAL 0x00002C09 -#define CRF_APB_DPLL_CTRL_RESET_SHIFT 0 -#define CRF_APB_DPLL_CTRL_RESET_MASK 0x00000001U +#define CRF_APB_DPLL_CTRL_RESET_DEFVAL 0x00002C09 +#define CRF_APB_DPLL_CTRL_RESET_SHIFT 0 +#define CRF_APB_DPLL_CTRL_RESET_MASK 0x00000001U -/*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/ +/* +* Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. +*/ #undef CRF_APB_DPLL_CTRL_RESET_DEFVAL #undef CRF_APB_DPLL_CTRL_RESET_SHIFT #undef CRF_APB_DPLL_CTRL_RESET_MASK -#define CRF_APB_DPLL_CTRL_RESET_DEFVAL 0x00002C09 -#define CRF_APB_DPLL_CTRL_RESET_SHIFT 0 -#define CRF_APB_DPLL_CTRL_RESET_MASK 0x00000001U +#define CRF_APB_DPLL_CTRL_RESET_DEFVAL 0x00002C09 +#define CRF_APB_DPLL_CTRL_RESET_SHIFT 0 +#define CRF_APB_DPLL_CTRL_RESET_MASK 0x00000001U -/*DPLL is locked*/ +/* +* DPLL is locked +*/ #undef CRF_APB_PLL_STATUS_DPLL_LOCK_DEFVAL #undef CRF_APB_PLL_STATUS_DPLL_LOCK_SHIFT #undef CRF_APB_PLL_STATUS_DPLL_LOCK_MASK -#define CRF_APB_PLL_STATUS_DPLL_LOCK_DEFVAL 0x00000038 -#define CRF_APB_PLL_STATUS_DPLL_LOCK_SHIFT 1 -#define CRF_APB_PLL_STATUS_DPLL_LOCK_MASK 0x00000002U +#define CRF_APB_PLL_STATUS_DPLL_LOCK_DEFVAL 0x00000038 +#define CRF_APB_PLL_STATUS_DPLL_LOCK_SHIFT 1 +#define CRF_APB_PLL_STATUS_DPLL_LOCK_MASK 0x00000002U #define CRF_APB_PLL_STATUS_OFFSET 0XFD1A0044 -/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/ +/* +* Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) +*/ #undef CRF_APB_DPLL_CTRL_BYPASS_DEFVAL #undef CRF_APB_DPLL_CTRL_BYPASS_SHIFT #undef CRF_APB_DPLL_CTRL_BYPASS_MASK -#define CRF_APB_DPLL_CTRL_BYPASS_DEFVAL 0x00002C09 -#define CRF_APB_DPLL_CTRL_BYPASS_SHIFT 3 -#define CRF_APB_DPLL_CTRL_BYPASS_MASK 0x00000008U +#define CRF_APB_DPLL_CTRL_BYPASS_DEFVAL 0x00002C09 +#define CRF_APB_DPLL_CTRL_BYPASS_SHIFT 3 +#define CRF_APB_DPLL_CTRL_BYPASS_MASK 0x00000008U -/*Divisor value for this clock.*/ +/* +* Divisor value for this clock. +*/ #undef CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL #undef CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_SHIFT #undef CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_MASK -#define CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL 0x00000400 -#define CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_SHIFT 8 -#define CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL 0x00000400 +#define CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_MASK 0x00003F00U -/*Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona - mode and uses DATA of this register for the fractional portion of the feedback divider.*/ -#undef CRF_APB_DPLL_FRAC_CFG_ENABLED_DEFVAL -#undef CRF_APB_DPLL_FRAC_CFG_ENABLED_SHIFT -#undef CRF_APB_DPLL_FRAC_CFG_ENABLED_MASK -#define CRF_APB_DPLL_FRAC_CFG_ENABLED_DEFVAL 0x00000000 -#define CRF_APB_DPLL_FRAC_CFG_ENABLED_SHIFT 31 -#define CRF_APB_DPLL_FRAC_CFG_ENABLED_MASK 0x80000000U - -/*Fractional value for the Feedback value.*/ -#undef CRF_APB_DPLL_FRAC_CFG_DATA_DEFVAL -#undef CRF_APB_DPLL_FRAC_CFG_DATA_SHIFT -#undef CRF_APB_DPLL_FRAC_CFG_DATA_MASK -#define CRF_APB_DPLL_FRAC_CFG_DATA_DEFVAL 0x00000000 -#define CRF_APB_DPLL_FRAC_CFG_DATA_SHIFT 0 -#define CRF_APB_DPLL_FRAC_CFG_DATA_MASK 0x0000FFFFU - -/*PLL loop filter resistor control*/ +/* +* PLL loop filter resistor control +*/ #undef CRF_APB_VPLL_CFG_RES_DEFVAL #undef CRF_APB_VPLL_CFG_RES_SHIFT #undef CRF_APB_VPLL_CFG_RES_MASK -#define CRF_APB_VPLL_CFG_RES_DEFVAL 0x00000000 -#define CRF_APB_VPLL_CFG_RES_SHIFT 0 -#define CRF_APB_VPLL_CFG_RES_MASK 0x0000000FU +#define CRF_APB_VPLL_CFG_RES_DEFVAL 0x00000000 +#define CRF_APB_VPLL_CFG_RES_SHIFT 0 +#define CRF_APB_VPLL_CFG_RES_MASK 0x0000000FU -/*PLL charge pump control*/ +/* +* PLL charge pump control +*/ #undef CRF_APB_VPLL_CFG_CP_DEFVAL #undef CRF_APB_VPLL_CFG_CP_SHIFT #undef CRF_APB_VPLL_CFG_CP_MASK -#define CRF_APB_VPLL_CFG_CP_DEFVAL 0x00000000 -#define CRF_APB_VPLL_CFG_CP_SHIFT 5 -#define CRF_APB_VPLL_CFG_CP_MASK 0x000001E0U +#define CRF_APB_VPLL_CFG_CP_DEFVAL 0x00000000 +#define CRF_APB_VPLL_CFG_CP_SHIFT 5 +#define CRF_APB_VPLL_CFG_CP_MASK 0x000001E0U -/*PLL loop filter high frequency capacitor control*/ +/* +* PLL loop filter high frequency capacitor control +*/ #undef CRF_APB_VPLL_CFG_LFHF_DEFVAL #undef CRF_APB_VPLL_CFG_LFHF_SHIFT #undef CRF_APB_VPLL_CFG_LFHF_MASK -#define CRF_APB_VPLL_CFG_LFHF_DEFVAL 0x00000000 -#define CRF_APB_VPLL_CFG_LFHF_SHIFT 10 -#define CRF_APB_VPLL_CFG_LFHF_MASK 0x00000C00U +#define CRF_APB_VPLL_CFG_LFHF_DEFVAL 0x00000000 +#define CRF_APB_VPLL_CFG_LFHF_SHIFT 10 +#define CRF_APB_VPLL_CFG_LFHF_MASK 0x00000C00U -/*Lock circuit counter setting*/ +/* +* Lock circuit counter setting +*/ #undef CRF_APB_VPLL_CFG_LOCK_CNT_DEFVAL #undef CRF_APB_VPLL_CFG_LOCK_CNT_SHIFT #undef CRF_APB_VPLL_CFG_LOCK_CNT_MASK -#define CRF_APB_VPLL_CFG_LOCK_CNT_DEFVAL 0x00000000 -#define CRF_APB_VPLL_CFG_LOCK_CNT_SHIFT 13 -#define CRF_APB_VPLL_CFG_LOCK_CNT_MASK 0x007FE000U +#define CRF_APB_VPLL_CFG_LOCK_CNT_DEFVAL 0x00000000 +#define CRF_APB_VPLL_CFG_LOCK_CNT_SHIFT 13 +#define CRF_APB_VPLL_CFG_LOCK_CNT_MASK 0x007FE000U -/*Lock circuit configuration settings for lock windowsize*/ +/* +* Lock circuit configuration settings for lock windowsize +*/ #undef CRF_APB_VPLL_CFG_LOCK_DLY_DEFVAL #undef CRF_APB_VPLL_CFG_LOCK_DLY_SHIFT #undef CRF_APB_VPLL_CFG_LOCK_DLY_MASK -#define CRF_APB_VPLL_CFG_LOCK_DLY_DEFVAL 0x00000000 -#define CRF_APB_VPLL_CFG_LOCK_DLY_SHIFT 25 -#define CRF_APB_VPLL_CFG_LOCK_DLY_MASK 0xFE000000U +#define CRF_APB_VPLL_CFG_LOCK_DLY_DEFVAL 0x00000000 +#define CRF_APB_VPLL_CFG_LOCK_DLY_SHIFT 25 +#define CRF_APB_VPLL_CFG_LOCK_DLY_MASK 0xFE000000U -/*Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_ - ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source*/ +/* +* Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i + * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour + * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source +*/ #undef CRF_APB_VPLL_CTRL_PRE_SRC_DEFVAL #undef CRF_APB_VPLL_CTRL_PRE_SRC_SHIFT #undef CRF_APB_VPLL_CTRL_PRE_SRC_MASK -#define CRF_APB_VPLL_CTRL_PRE_SRC_DEFVAL 0x00012809 -#define CRF_APB_VPLL_CTRL_PRE_SRC_SHIFT 20 -#define CRF_APB_VPLL_CTRL_PRE_SRC_MASK 0x00700000U +#define CRF_APB_VPLL_CTRL_PRE_SRC_DEFVAL 0x00012809 +#define CRF_APB_VPLL_CTRL_PRE_SRC_SHIFT 20 +#define CRF_APB_VPLL_CTRL_PRE_SRC_MASK 0x00700000U -/*The integer portion of the feedback divider to the PLL*/ +/* +* The integer portion of the feedback divider to the PLL +*/ #undef CRF_APB_VPLL_CTRL_FBDIV_DEFVAL #undef CRF_APB_VPLL_CTRL_FBDIV_SHIFT #undef CRF_APB_VPLL_CTRL_FBDIV_MASK -#define CRF_APB_VPLL_CTRL_FBDIV_DEFVAL 0x00012809 -#define CRF_APB_VPLL_CTRL_FBDIV_SHIFT 8 -#define CRF_APB_VPLL_CTRL_FBDIV_MASK 0x00007F00U +#define CRF_APB_VPLL_CTRL_FBDIV_DEFVAL 0x00012809 +#define CRF_APB_VPLL_CTRL_FBDIV_SHIFT 8 +#define CRF_APB_VPLL_CTRL_FBDIV_MASK 0x00007F00U -/*This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency*/ +/* +* This turns on the divide by 2 that is inside of the PLL. This does not c + * hange the VCO frequency, just the output frequency +*/ #undef CRF_APB_VPLL_CTRL_DIV2_DEFVAL #undef CRF_APB_VPLL_CTRL_DIV2_SHIFT #undef CRF_APB_VPLL_CTRL_DIV2_MASK -#define CRF_APB_VPLL_CTRL_DIV2_DEFVAL 0x00012809 -#define CRF_APB_VPLL_CTRL_DIV2_SHIFT 16 -#define CRF_APB_VPLL_CTRL_DIV2_MASK 0x00010000U +#define CRF_APB_VPLL_CTRL_DIV2_DEFVAL 0x00012809 +#define CRF_APB_VPLL_CTRL_DIV2_SHIFT 16 +#define CRF_APB_VPLL_CTRL_DIV2_MASK 0x00010000U -/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/ +/* +* Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) +*/ #undef CRF_APB_VPLL_CTRL_BYPASS_DEFVAL #undef CRF_APB_VPLL_CTRL_BYPASS_SHIFT #undef CRF_APB_VPLL_CTRL_BYPASS_MASK -#define CRF_APB_VPLL_CTRL_BYPASS_DEFVAL 0x00012809 -#define CRF_APB_VPLL_CTRL_BYPASS_SHIFT 3 -#define CRF_APB_VPLL_CTRL_BYPASS_MASK 0x00000008U +#define CRF_APB_VPLL_CTRL_BYPASS_DEFVAL 0x00012809 +#define CRF_APB_VPLL_CTRL_BYPASS_SHIFT 3 +#define CRF_APB_VPLL_CTRL_BYPASS_MASK 0x00000008U -/*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/ +/* +* Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. +*/ #undef CRF_APB_VPLL_CTRL_RESET_DEFVAL #undef CRF_APB_VPLL_CTRL_RESET_SHIFT #undef CRF_APB_VPLL_CTRL_RESET_MASK -#define CRF_APB_VPLL_CTRL_RESET_DEFVAL 0x00012809 -#define CRF_APB_VPLL_CTRL_RESET_SHIFT 0 -#define CRF_APB_VPLL_CTRL_RESET_MASK 0x00000001U +#define CRF_APB_VPLL_CTRL_RESET_DEFVAL 0x00012809 +#define CRF_APB_VPLL_CTRL_RESET_SHIFT 0 +#define CRF_APB_VPLL_CTRL_RESET_MASK 0x00000001U -/*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/ +/* +* Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. +*/ #undef CRF_APB_VPLL_CTRL_RESET_DEFVAL #undef CRF_APB_VPLL_CTRL_RESET_SHIFT #undef CRF_APB_VPLL_CTRL_RESET_MASK -#define CRF_APB_VPLL_CTRL_RESET_DEFVAL 0x00012809 -#define CRF_APB_VPLL_CTRL_RESET_SHIFT 0 -#define CRF_APB_VPLL_CTRL_RESET_MASK 0x00000001U +#define CRF_APB_VPLL_CTRL_RESET_DEFVAL 0x00012809 +#define CRF_APB_VPLL_CTRL_RESET_SHIFT 0 +#define CRF_APB_VPLL_CTRL_RESET_MASK 0x00000001U -/*VPLL is locked*/ +/* +* VPLL is locked +*/ #undef CRF_APB_PLL_STATUS_VPLL_LOCK_DEFVAL #undef CRF_APB_PLL_STATUS_VPLL_LOCK_SHIFT #undef CRF_APB_PLL_STATUS_VPLL_LOCK_MASK -#define CRF_APB_PLL_STATUS_VPLL_LOCK_DEFVAL 0x00000038 -#define CRF_APB_PLL_STATUS_VPLL_LOCK_SHIFT 2 -#define CRF_APB_PLL_STATUS_VPLL_LOCK_MASK 0x00000004U +#define CRF_APB_PLL_STATUS_VPLL_LOCK_DEFVAL 0x00000038 +#define CRF_APB_PLL_STATUS_VPLL_LOCK_SHIFT 2 +#define CRF_APB_PLL_STATUS_VPLL_LOCK_MASK 0x00000004U #define CRF_APB_PLL_STATUS_OFFSET 0XFD1A0044 -/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/ +/* +* Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) +*/ #undef CRF_APB_VPLL_CTRL_BYPASS_DEFVAL #undef CRF_APB_VPLL_CTRL_BYPASS_SHIFT #undef CRF_APB_VPLL_CTRL_BYPASS_MASK -#define CRF_APB_VPLL_CTRL_BYPASS_DEFVAL 0x00012809 -#define CRF_APB_VPLL_CTRL_BYPASS_SHIFT 3 -#define CRF_APB_VPLL_CTRL_BYPASS_MASK 0x00000008U +#define CRF_APB_VPLL_CTRL_BYPASS_DEFVAL 0x00012809 +#define CRF_APB_VPLL_CTRL_BYPASS_SHIFT 3 +#define CRF_APB_VPLL_CTRL_BYPASS_MASK 0x00000008U -/*Divisor value for this clock.*/ +/* +* Divisor value for this clock. +*/ #undef CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL #undef CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_SHIFT #undef CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_MASK -#define CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL 0x00000400 -#define CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_SHIFT 8 -#define CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_MASK 0x00003F00U - -/*Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona - mode and uses DATA of this register for the fractional portion of the feedback divider.*/ -#undef CRF_APB_VPLL_FRAC_CFG_ENABLED_DEFVAL -#undef CRF_APB_VPLL_FRAC_CFG_ENABLED_SHIFT -#undef CRF_APB_VPLL_FRAC_CFG_ENABLED_MASK -#define CRF_APB_VPLL_FRAC_CFG_ENABLED_DEFVAL 0x00000000 -#define CRF_APB_VPLL_FRAC_CFG_ENABLED_SHIFT 31 -#define CRF_APB_VPLL_FRAC_CFG_ENABLED_MASK 0x80000000U - -/*Fractional value for the Feedback value.*/ -#undef CRF_APB_VPLL_FRAC_CFG_DATA_DEFVAL -#undef CRF_APB_VPLL_FRAC_CFG_DATA_SHIFT -#undef CRF_APB_VPLL_FRAC_CFG_DATA_MASK -#define CRF_APB_VPLL_FRAC_CFG_DATA_DEFVAL 0x00000000 -#define CRF_APB_VPLL_FRAC_CFG_DATA_SHIFT 0 -#define CRF_APB_VPLL_FRAC_CFG_DATA_MASK 0x0000FFFFU +#define CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL 0x00000400 +#define CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_MASK 0x00003F00U #undef CRL_APB_GEM3_REF_CTRL_OFFSET #define CRL_APB_GEM3_REF_CTRL_OFFSET 0XFF5E005C +#undef CRL_APB_GEM_TSU_REF_CTRL_OFFSET +#define CRL_APB_GEM_TSU_REF_CTRL_OFFSET 0XFF5E0100 #undef CRL_APB_USB0_BUS_REF_CTRL_OFFSET #define CRL_APB_USB0_BUS_REF_CTRL_OFFSET 0XFF5E0060 #undef CRL_APB_USB3_DUAL_REF_CTRL_OFFSET @@ -822,12 +909,6 @@ #define CRL_APB_ADMA_REF_CTRL_OFFSET 0XFF5E00B8 #undef CRL_APB_PL0_REF_CTRL_OFFSET #define CRL_APB_PL0_REF_CTRL_OFFSET 0XFF5E00C0 -#undef CRL_APB_PL1_REF_CTRL_OFFSET -#define CRL_APB_PL1_REF_CTRL_OFFSET 0XFF5E00C4 -#undef CRL_APB_PL2_REF_CTRL_OFFSET -#define CRL_APB_PL2_REF_CTRL_OFFSET 0XFF5E00C8 -#undef CRL_APB_PL3_REF_CTRL_OFFSET -#define CRL_APB_PL3_REF_CTRL_OFFSET 0XFF5E00CC #undef CRL_APB_AMS_REF_CTRL_OFFSET #define CRL_APB_AMS_REF_CTRL_OFFSET 0XFF5E0108 #undef CRL_APB_DLL_REF_CTRL_OFFSET @@ -846,8 +927,6 @@ #define CRF_APB_DP_STC_REF_CTRL_OFFSET 0XFD1A007C #undef CRF_APB_ACPU_CTRL_OFFSET #define CRF_APB_ACPU_CTRL_OFFSET 0XFD1A0060 -#undef CRF_APB_DBG_TRACE_CTRL_OFFSET -#define CRF_APB_DBG_TRACE_CTRL_OFFSET 0XFD1A0064 #undef CRF_APB_DBG_FPD_CTRL_OFFSET #define CRF_APB_DBG_FPD_CTRL_OFFSET 0XFD1A0068 #undef CRF_APB_DDR_CTRL_OFFSET @@ -873,1195 +952,1418 @@ #undef LPD_SLCR_CSUPMU_WDT_CLK_SEL_OFFSET #define LPD_SLCR_CSUPMU_WDT_CLK_SEL_OFFSET 0XFF410050 -/*Clock active for the RX channel*/ +/* +* Clock active for the RX channel +*/ #undef CRL_APB_GEM3_REF_CTRL_RX_CLKACT_DEFVAL #undef CRL_APB_GEM3_REF_CTRL_RX_CLKACT_SHIFT #undef CRL_APB_GEM3_REF_CTRL_RX_CLKACT_MASK -#define CRL_APB_GEM3_REF_CTRL_RX_CLKACT_DEFVAL 0x00002500 -#define CRL_APB_GEM3_REF_CTRL_RX_CLKACT_SHIFT 26 -#define CRL_APB_GEM3_REF_CTRL_RX_CLKACT_MASK 0x04000000U +#define CRL_APB_GEM3_REF_CTRL_RX_CLKACT_DEFVAL 0x00002500 +#define CRL_APB_GEM3_REF_CTRL_RX_CLKACT_SHIFT 26 +#define CRL_APB_GEM3_REF_CTRL_RX_CLKACT_MASK 0x04000000U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRL_APB_GEM3_REF_CTRL_CLKACT_DEFVAL #undef CRL_APB_GEM3_REF_CTRL_CLKACT_SHIFT #undef CRL_APB_GEM3_REF_CTRL_CLKACT_MASK -#define CRL_APB_GEM3_REF_CTRL_CLKACT_DEFVAL 0x00002500 -#define CRL_APB_GEM3_REF_CTRL_CLKACT_SHIFT 25 -#define CRL_APB_GEM3_REF_CTRL_CLKACT_MASK 0x02000000U +#define CRL_APB_GEM3_REF_CTRL_CLKACT_DEFVAL 0x00002500 +#define CRL_APB_GEM3_REF_CTRL_CLKACT_SHIFT 25 +#define CRL_APB_GEM3_REF_CTRL_CLKACT_MASK 0x02000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_GEM3_REF_CTRL_DIVISOR1_DEFVAL #undef CRL_APB_GEM3_REF_CTRL_DIVISOR1_SHIFT #undef CRL_APB_GEM3_REF_CTRL_DIVISOR1_MASK -#define CRL_APB_GEM3_REF_CTRL_DIVISOR1_DEFVAL 0x00002500 -#define CRL_APB_GEM3_REF_CTRL_DIVISOR1_SHIFT 16 -#define CRL_APB_GEM3_REF_CTRL_DIVISOR1_MASK 0x003F0000U +#define CRL_APB_GEM3_REF_CTRL_DIVISOR1_DEFVAL 0x00002500 +#define CRL_APB_GEM3_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_GEM3_REF_CTRL_DIVISOR1_MASK 0x003F0000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_GEM3_REF_CTRL_DIVISOR0_DEFVAL #undef CRL_APB_GEM3_REF_CTRL_DIVISOR0_SHIFT #undef CRL_APB_GEM3_REF_CTRL_DIVISOR0_MASK -#define CRL_APB_GEM3_REF_CTRL_DIVISOR0_DEFVAL 0x00002500 -#define CRL_APB_GEM3_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_GEM3_REF_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRL_APB_GEM3_REF_CTRL_DIVISOR0_DEFVAL 0x00002500 +#define CRL_APB_GEM3_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_GEM3_REF_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRL_APB_GEM3_REF_CTRL_SRCSEL_DEFVAL #undef CRL_APB_GEM3_REF_CTRL_SRCSEL_SHIFT #undef CRL_APB_GEM3_REF_CTRL_SRCSEL_MASK -#define CRL_APB_GEM3_REF_CTRL_SRCSEL_DEFVAL 0x00002500 -#define CRL_APB_GEM3_REF_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_GEM3_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRL_APB_GEM3_REF_CTRL_SRCSEL_DEFVAL 0x00002500 +#define CRL_APB_GEM3_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_GEM3_REF_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* 6 bit divider +*/ +#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_DEFVAL +#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_SHIFT +#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_MASK +#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_DEFVAL 0x00051000 +#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_MASK 0x00003F00U + +/* +* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ +#undef CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_DEFVAL +#undef CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_SHIFT +#undef CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_MASK +#define CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_DEFVAL 0x00051000 +#define CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_MASK 0x00000007U + +/* +* 6 bit divider +*/ +#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_DEFVAL +#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_SHIFT +#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_MASK +#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_DEFVAL 0x00051000 +#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_MASK 0x003F0000U + +/* +* Clock active signal. Switch to 0 to disable the clock +*/ +#undef CRL_APB_GEM_TSU_REF_CTRL_CLKACT_DEFVAL +#undef CRL_APB_GEM_TSU_REF_CTRL_CLKACT_SHIFT +#undef CRL_APB_GEM_TSU_REF_CTRL_CLKACT_MASK +#define CRL_APB_GEM_TSU_REF_CTRL_CLKACT_DEFVAL 0x00051000 +#define CRL_APB_GEM_TSU_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_GEM_TSU_REF_CTRL_CLKACT_MASK 0x01000000U + +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRL_APB_USB0_BUS_REF_CTRL_CLKACT_DEFVAL #undef CRL_APB_USB0_BUS_REF_CTRL_CLKACT_SHIFT #undef CRL_APB_USB0_BUS_REF_CTRL_CLKACT_MASK -#define CRL_APB_USB0_BUS_REF_CTRL_CLKACT_DEFVAL 0x00052000 -#define CRL_APB_USB0_BUS_REF_CTRL_CLKACT_SHIFT 25 -#define CRL_APB_USB0_BUS_REF_CTRL_CLKACT_MASK 0x02000000U +#define CRL_APB_USB0_BUS_REF_CTRL_CLKACT_DEFVAL 0x00052000 +#define CRL_APB_USB0_BUS_REF_CTRL_CLKACT_SHIFT 25 +#define CRL_APB_USB0_BUS_REF_CTRL_CLKACT_MASK 0x02000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_DEFVAL #undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_SHIFT #undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_MASK -#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_DEFVAL 0x00052000 -#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_SHIFT 16 -#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_MASK 0x003F0000U +#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_DEFVAL 0x00052000 +#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_MASK 0x003F0000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_DEFVAL #undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_SHIFT #undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_MASK -#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_DEFVAL 0x00052000 -#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_DEFVAL 0x00052000 +#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_DEFVAL #undef CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_SHIFT #undef CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_MASK -#define CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_DEFVAL 0x00052000 -#define CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_DEFVAL 0x00052000 +#define CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_DEFVAL #undef CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_SHIFT #undef CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_MASK -#define CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_DEFVAL 0x00052000 -#define CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_SHIFT 25 -#define CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_MASK 0x02000000U +#define CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_DEFVAL 0x00052000 +#define CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_SHIFT 25 +#define CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_MASK 0x02000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_DEFVAL #undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_SHIFT #undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_MASK -#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_DEFVAL 0x00052000 -#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_SHIFT 16 -#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_MASK 0x003F0000U +#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_DEFVAL 0x00052000 +#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_MASK 0x003F0000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_DEFVAL #undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_SHIFT #undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_MASK -#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_DEFVAL 0x00052000 -#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_DEFVAL 0x00052000 +#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = IOPLL; 010 = RPLL; 011 = DPLL. (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = IOPLL; 010 = RPLL; 011 = DPLL. (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_DEFVAL #undef CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_SHIFT #undef CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_MASK -#define CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_DEFVAL 0x00052000 -#define CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_DEFVAL 0x00052000 +#define CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRL_APB_QSPI_REF_CTRL_CLKACT_DEFVAL #undef CRL_APB_QSPI_REF_CTRL_CLKACT_SHIFT #undef CRL_APB_QSPI_REF_CTRL_CLKACT_MASK -#define CRL_APB_QSPI_REF_CTRL_CLKACT_DEFVAL 0x01000800 -#define CRL_APB_QSPI_REF_CTRL_CLKACT_SHIFT 24 -#define CRL_APB_QSPI_REF_CTRL_CLKACT_MASK 0x01000000U +#define CRL_APB_QSPI_REF_CTRL_CLKACT_DEFVAL 0x01000800 +#define CRL_APB_QSPI_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_QSPI_REF_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_QSPI_REF_CTRL_DIVISOR1_DEFVAL #undef CRL_APB_QSPI_REF_CTRL_DIVISOR1_SHIFT #undef CRL_APB_QSPI_REF_CTRL_DIVISOR1_MASK -#define CRL_APB_QSPI_REF_CTRL_DIVISOR1_DEFVAL 0x01000800 -#define CRL_APB_QSPI_REF_CTRL_DIVISOR1_SHIFT 16 -#define CRL_APB_QSPI_REF_CTRL_DIVISOR1_MASK 0x003F0000U +#define CRL_APB_QSPI_REF_CTRL_DIVISOR1_DEFVAL 0x01000800 +#define CRL_APB_QSPI_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_QSPI_REF_CTRL_DIVISOR1_MASK 0x003F0000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_QSPI_REF_CTRL_DIVISOR0_DEFVAL #undef CRL_APB_QSPI_REF_CTRL_DIVISOR0_SHIFT #undef CRL_APB_QSPI_REF_CTRL_DIVISOR0_MASK -#define CRL_APB_QSPI_REF_CTRL_DIVISOR0_DEFVAL 0x01000800 -#define CRL_APB_QSPI_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_QSPI_REF_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRL_APB_QSPI_REF_CTRL_DIVISOR0_DEFVAL 0x01000800 +#define CRL_APB_QSPI_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_QSPI_REF_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRL_APB_QSPI_REF_CTRL_SRCSEL_DEFVAL #undef CRL_APB_QSPI_REF_CTRL_SRCSEL_SHIFT #undef CRL_APB_QSPI_REF_CTRL_SRCSEL_MASK -#define CRL_APB_QSPI_REF_CTRL_SRCSEL_DEFVAL 0x01000800 -#define CRL_APB_QSPI_REF_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_QSPI_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRL_APB_QSPI_REF_CTRL_SRCSEL_DEFVAL 0x01000800 +#define CRL_APB_QSPI_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_QSPI_REF_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRL_APB_SDIO1_REF_CTRL_CLKACT_DEFVAL #undef CRL_APB_SDIO1_REF_CTRL_CLKACT_SHIFT #undef CRL_APB_SDIO1_REF_CTRL_CLKACT_MASK -#define CRL_APB_SDIO1_REF_CTRL_CLKACT_DEFVAL 0x01000F00 -#define CRL_APB_SDIO1_REF_CTRL_CLKACT_SHIFT 24 -#define CRL_APB_SDIO1_REF_CTRL_CLKACT_MASK 0x01000000U +#define CRL_APB_SDIO1_REF_CTRL_CLKACT_DEFVAL 0x01000F00 +#define CRL_APB_SDIO1_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_SDIO1_REF_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_SDIO1_REF_CTRL_DIVISOR1_DEFVAL #undef CRL_APB_SDIO1_REF_CTRL_DIVISOR1_SHIFT #undef CRL_APB_SDIO1_REF_CTRL_DIVISOR1_MASK -#define CRL_APB_SDIO1_REF_CTRL_DIVISOR1_DEFVAL 0x01000F00 -#define CRL_APB_SDIO1_REF_CTRL_DIVISOR1_SHIFT 16 -#define CRL_APB_SDIO1_REF_CTRL_DIVISOR1_MASK 0x003F0000U +#define CRL_APB_SDIO1_REF_CTRL_DIVISOR1_DEFVAL 0x01000F00 +#define CRL_APB_SDIO1_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_SDIO1_REF_CTRL_DIVISOR1_MASK 0x003F0000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_SDIO1_REF_CTRL_DIVISOR0_DEFVAL #undef CRL_APB_SDIO1_REF_CTRL_DIVISOR0_SHIFT #undef CRL_APB_SDIO1_REF_CTRL_DIVISOR0_MASK -#define CRL_APB_SDIO1_REF_CTRL_DIVISOR0_DEFVAL 0x01000F00 -#define CRL_APB_SDIO1_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_SDIO1_REF_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRL_APB_SDIO1_REF_CTRL_DIVISOR0_DEFVAL 0x01000F00 +#define CRL_APB_SDIO1_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_SDIO1_REF_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = IOPLL; 010 = RPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = IOPLL; 010 = RPLL; 011 = VPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRL_APB_SDIO1_REF_CTRL_SRCSEL_DEFVAL #undef CRL_APB_SDIO1_REF_CTRL_SRCSEL_SHIFT #undef CRL_APB_SDIO1_REF_CTRL_SRCSEL_MASK -#define CRL_APB_SDIO1_REF_CTRL_SRCSEL_DEFVAL 0x01000F00 -#define CRL_APB_SDIO1_REF_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_SDIO1_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRL_APB_SDIO1_REF_CTRL_SRCSEL_DEFVAL 0x01000F00 +#define CRL_APB_SDIO1_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_SDIO1_REF_CTRL_SRCSEL_MASK 0x00000007U -/*MIO pad selection for sdio1_rx_clk (feedback clock from the PAD) 0: MIO [51] 1: MIO [76]*/ +/* +* MIO pad selection for sdio1_rx_clk (feedback clock from the PAD) 0: MIO + * [51] 1: MIO [76] +*/ #undef IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_DEFVAL #undef IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_SHIFT #undef IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_MASK -#define IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_SHIFT 17 -#define IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_MASK 0x00020000U +#define IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_SHIFT 17 +#define IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_MASK 0x00020000U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRL_APB_UART0_REF_CTRL_CLKACT_DEFVAL #undef CRL_APB_UART0_REF_CTRL_CLKACT_SHIFT #undef CRL_APB_UART0_REF_CTRL_CLKACT_MASK -#define CRL_APB_UART0_REF_CTRL_CLKACT_DEFVAL 0x01001800 -#define CRL_APB_UART0_REF_CTRL_CLKACT_SHIFT 24 -#define CRL_APB_UART0_REF_CTRL_CLKACT_MASK 0x01000000U +#define CRL_APB_UART0_REF_CTRL_CLKACT_DEFVAL 0x01001800 +#define CRL_APB_UART0_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_UART0_REF_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_UART0_REF_CTRL_DIVISOR1_DEFVAL #undef CRL_APB_UART0_REF_CTRL_DIVISOR1_SHIFT #undef CRL_APB_UART0_REF_CTRL_DIVISOR1_MASK -#define CRL_APB_UART0_REF_CTRL_DIVISOR1_DEFVAL 0x01001800 -#define CRL_APB_UART0_REF_CTRL_DIVISOR1_SHIFT 16 -#define CRL_APB_UART0_REF_CTRL_DIVISOR1_MASK 0x003F0000U +#define CRL_APB_UART0_REF_CTRL_DIVISOR1_DEFVAL 0x01001800 +#define CRL_APB_UART0_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_UART0_REF_CTRL_DIVISOR1_MASK 0x003F0000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_UART0_REF_CTRL_DIVISOR0_DEFVAL #undef CRL_APB_UART0_REF_CTRL_DIVISOR0_SHIFT #undef CRL_APB_UART0_REF_CTRL_DIVISOR0_MASK -#define CRL_APB_UART0_REF_CTRL_DIVISOR0_DEFVAL 0x01001800 -#define CRL_APB_UART0_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_UART0_REF_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRL_APB_UART0_REF_CTRL_DIVISOR0_DEFVAL 0x01001800 +#define CRL_APB_UART0_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_UART0_REF_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRL_APB_UART0_REF_CTRL_SRCSEL_DEFVAL #undef CRL_APB_UART0_REF_CTRL_SRCSEL_SHIFT #undef CRL_APB_UART0_REF_CTRL_SRCSEL_MASK -#define CRL_APB_UART0_REF_CTRL_SRCSEL_DEFVAL 0x01001800 -#define CRL_APB_UART0_REF_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_UART0_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRL_APB_UART0_REF_CTRL_SRCSEL_DEFVAL 0x01001800 +#define CRL_APB_UART0_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_UART0_REF_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRL_APB_UART1_REF_CTRL_CLKACT_DEFVAL #undef CRL_APB_UART1_REF_CTRL_CLKACT_SHIFT #undef CRL_APB_UART1_REF_CTRL_CLKACT_MASK -#define CRL_APB_UART1_REF_CTRL_CLKACT_DEFVAL 0x01001800 -#define CRL_APB_UART1_REF_CTRL_CLKACT_SHIFT 24 -#define CRL_APB_UART1_REF_CTRL_CLKACT_MASK 0x01000000U +#define CRL_APB_UART1_REF_CTRL_CLKACT_DEFVAL 0x01001800 +#define CRL_APB_UART1_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_UART1_REF_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_UART1_REF_CTRL_DIVISOR1_DEFVAL #undef CRL_APB_UART1_REF_CTRL_DIVISOR1_SHIFT #undef CRL_APB_UART1_REF_CTRL_DIVISOR1_MASK -#define CRL_APB_UART1_REF_CTRL_DIVISOR1_DEFVAL 0x01001800 -#define CRL_APB_UART1_REF_CTRL_DIVISOR1_SHIFT 16 -#define CRL_APB_UART1_REF_CTRL_DIVISOR1_MASK 0x003F0000U +#define CRL_APB_UART1_REF_CTRL_DIVISOR1_DEFVAL 0x01001800 +#define CRL_APB_UART1_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_UART1_REF_CTRL_DIVISOR1_MASK 0x003F0000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_UART1_REF_CTRL_DIVISOR0_DEFVAL #undef CRL_APB_UART1_REF_CTRL_DIVISOR0_SHIFT #undef CRL_APB_UART1_REF_CTRL_DIVISOR0_MASK -#define CRL_APB_UART1_REF_CTRL_DIVISOR0_DEFVAL 0x01001800 -#define CRL_APB_UART1_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_UART1_REF_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRL_APB_UART1_REF_CTRL_DIVISOR0_DEFVAL 0x01001800 +#define CRL_APB_UART1_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_UART1_REF_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRL_APB_UART1_REF_CTRL_SRCSEL_DEFVAL #undef CRL_APB_UART1_REF_CTRL_SRCSEL_SHIFT #undef CRL_APB_UART1_REF_CTRL_SRCSEL_MASK -#define CRL_APB_UART1_REF_CTRL_SRCSEL_DEFVAL 0x01001800 -#define CRL_APB_UART1_REF_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_UART1_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRL_APB_UART1_REF_CTRL_SRCSEL_DEFVAL 0x01001800 +#define CRL_APB_UART1_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_UART1_REF_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRL_APB_I2C0_REF_CTRL_CLKACT_DEFVAL #undef CRL_APB_I2C0_REF_CTRL_CLKACT_SHIFT #undef CRL_APB_I2C0_REF_CTRL_CLKACT_MASK -#define CRL_APB_I2C0_REF_CTRL_CLKACT_DEFVAL 0x01000500 -#define CRL_APB_I2C0_REF_CTRL_CLKACT_SHIFT 24 -#define CRL_APB_I2C0_REF_CTRL_CLKACT_MASK 0x01000000U +#define CRL_APB_I2C0_REF_CTRL_CLKACT_DEFVAL 0x01000500 +#define CRL_APB_I2C0_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_I2C0_REF_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_I2C0_REF_CTRL_DIVISOR1_DEFVAL #undef CRL_APB_I2C0_REF_CTRL_DIVISOR1_SHIFT #undef CRL_APB_I2C0_REF_CTRL_DIVISOR1_MASK -#define CRL_APB_I2C0_REF_CTRL_DIVISOR1_DEFVAL 0x01000500 -#define CRL_APB_I2C0_REF_CTRL_DIVISOR1_SHIFT 16 -#define CRL_APB_I2C0_REF_CTRL_DIVISOR1_MASK 0x003F0000U +#define CRL_APB_I2C0_REF_CTRL_DIVISOR1_DEFVAL 0x01000500 +#define CRL_APB_I2C0_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_I2C0_REF_CTRL_DIVISOR1_MASK 0x003F0000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_I2C0_REF_CTRL_DIVISOR0_DEFVAL #undef CRL_APB_I2C0_REF_CTRL_DIVISOR0_SHIFT #undef CRL_APB_I2C0_REF_CTRL_DIVISOR0_MASK -#define CRL_APB_I2C0_REF_CTRL_DIVISOR0_DEFVAL 0x01000500 -#define CRL_APB_I2C0_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_I2C0_REF_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRL_APB_I2C0_REF_CTRL_DIVISOR0_DEFVAL 0x01000500 +#define CRL_APB_I2C0_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_I2C0_REF_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRL_APB_I2C0_REF_CTRL_SRCSEL_DEFVAL #undef CRL_APB_I2C0_REF_CTRL_SRCSEL_SHIFT #undef CRL_APB_I2C0_REF_CTRL_SRCSEL_MASK -#define CRL_APB_I2C0_REF_CTRL_SRCSEL_DEFVAL 0x01000500 -#define CRL_APB_I2C0_REF_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_I2C0_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRL_APB_I2C0_REF_CTRL_SRCSEL_DEFVAL 0x01000500 +#define CRL_APB_I2C0_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_I2C0_REF_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRL_APB_I2C1_REF_CTRL_CLKACT_DEFVAL #undef CRL_APB_I2C1_REF_CTRL_CLKACT_SHIFT #undef CRL_APB_I2C1_REF_CTRL_CLKACT_MASK -#define CRL_APB_I2C1_REF_CTRL_CLKACT_DEFVAL 0x01000500 -#define CRL_APB_I2C1_REF_CTRL_CLKACT_SHIFT 24 -#define CRL_APB_I2C1_REF_CTRL_CLKACT_MASK 0x01000000U +#define CRL_APB_I2C1_REF_CTRL_CLKACT_DEFVAL 0x01000500 +#define CRL_APB_I2C1_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_I2C1_REF_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_I2C1_REF_CTRL_DIVISOR1_DEFVAL #undef CRL_APB_I2C1_REF_CTRL_DIVISOR1_SHIFT #undef CRL_APB_I2C1_REF_CTRL_DIVISOR1_MASK -#define CRL_APB_I2C1_REF_CTRL_DIVISOR1_DEFVAL 0x01000500 -#define CRL_APB_I2C1_REF_CTRL_DIVISOR1_SHIFT 16 -#define CRL_APB_I2C1_REF_CTRL_DIVISOR1_MASK 0x003F0000U +#define CRL_APB_I2C1_REF_CTRL_DIVISOR1_DEFVAL 0x01000500 +#define CRL_APB_I2C1_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_I2C1_REF_CTRL_DIVISOR1_MASK 0x003F0000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_I2C1_REF_CTRL_DIVISOR0_DEFVAL #undef CRL_APB_I2C1_REF_CTRL_DIVISOR0_SHIFT #undef CRL_APB_I2C1_REF_CTRL_DIVISOR0_MASK -#define CRL_APB_I2C1_REF_CTRL_DIVISOR0_DEFVAL 0x01000500 -#define CRL_APB_I2C1_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_I2C1_REF_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRL_APB_I2C1_REF_CTRL_DIVISOR0_DEFVAL 0x01000500 +#define CRL_APB_I2C1_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_I2C1_REF_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRL_APB_I2C1_REF_CTRL_SRCSEL_DEFVAL #undef CRL_APB_I2C1_REF_CTRL_SRCSEL_SHIFT #undef CRL_APB_I2C1_REF_CTRL_SRCSEL_MASK -#define CRL_APB_I2C1_REF_CTRL_SRCSEL_DEFVAL 0x01000500 -#define CRL_APB_I2C1_REF_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_I2C1_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRL_APB_I2C1_REF_CTRL_SRCSEL_DEFVAL 0x01000500 +#define CRL_APB_I2C1_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_I2C1_REF_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRL_APB_CAN1_REF_CTRL_CLKACT_DEFVAL #undef CRL_APB_CAN1_REF_CTRL_CLKACT_SHIFT #undef CRL_APB_CAN1_REF_CTRL_CLKACT_MASK -#define CRL_APB_CAN1_REF_CTRL_CLKACT_DEFVAL 0x01001800 -#define CRL_APB_CAN1_REF_CTRL_CLKACT_SHIFT 24 -#define CRL_APB_CAN1_REF_CTRL_CLKACT_MASK 0x01000000U +#define CRL_APB_CAN1_REF_CTRL_CLKACT_DEFVAL 0x01001800 +#define CRL_APB_CAN1_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_CAN1_REF_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_CAN1_REF_CTRL_DIVISOR1_DEFVAL #undef CRL_APB_CAN1_REF_CTRL_DIVISOR1_SHIFT #undef CRL_APB_CAN1_REF_CTRL_DIVISOR1_MASK -#define CRL_APB_CAN1_REF_CTRL_DIVISOR1_DEFVAL 0x01001800 -#define CRL_APB_CAN1_REF_CTRL_DIVISOR1_SHIFT 16 -#define CRL_APB_CAN1_REF_CTRL_DIVISOR1_MASK 0x003F0000U +#define CRL_APB_CAN1_REF_CTRL_DIVISOR1_DEFVAL 0x01001800 +#define CRL_APB_CAN1_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_CAN1_REF_CTRL_DIVISOR1_MASK 0x003F0000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_CAN1_REF_CTRL_DIVISOR0_DEFVAL #undef CRL_APB_CAN1_REF_CTRL_DIVISOR0_SHIFT #undef CRL_APB_CAN1_REF_CTRL_DIVISOR0_MASK -#define CRL_APB_CAN1_REF_CTRL_DIVISOR0_DEFVAL 0x01001800 -#define CRL_APB_CAN1_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_CAN1_REF_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRL_APB_CAN1_REF_CTRL_DIVISOR0_DEFVAL 0x01001800 +#define CRL_APB_CAN1_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_CAN1_REF_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRL_APB_CAN1_REF_CTRL_SRCSEL_DEFVAL #undef CRL_APB_CAN1_REF_CTRL_SRCSEL_SHIFT #undef CRL_APB_CAN1_REF_CTRL_SRCSEL_MASK -#define CRL_APB_CAN1_REF_CTRL_SRCSEL_DEFVAL 0x01001800 -#define CRL_APB_CAN1_REF_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_CAN1_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRL_APB_CAN1_REF_CTRL_SRCSEL_DEFVAL 0x01001800 +#define CRL_APB_CAN1_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_CAN1_REF_CTRL_SRCSEL_MASK 0x00000007U -/*Turing this off will shut down the OCM, some parts of the APM, and prevent transactions going from the FPD to the LPD and cou - d lead to system hang*/ +/* +* Turing this off will shut down the OCM, some parts of the APM, and preve + * nt transactions going from the FPD to the LPD and could lead to system h + * ang +*/ #undef CRL_APB_CPU_R5_CTRL_CLKACT_DEFVAL #undef CRL_APB_CPU_R5_CTRL_CLKACT_SHIFT #undef CRL_APB_CPU_R5_CTRL_CLKACT_MASK -#define CRL_APB_CPU_R5_CTRL_CLKACT_DEFVAL 0x03000600 -#define CRL_APB_CPU_R5_CTRL_CLKACT_SHIFT 24 -#define CRL_APB_CPU_R5_CTRL_CLKACT_MASK 0x01000000U +#define CRL_APB_CPU_R5_CTRL_CLKACT_DEFVAL 0x03000600 +#define CRL_APB_CPU_R5_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_CPU_R5_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_CPU_R5_CTRL_DIVISOR0_DEFVAL #undef CRL_APB_CPU_R5_CTRL_DIVISOR0_SHIFT #undef CRL_APB_CPU_R5_CTRL_DIVISOR0_MASK -#define CRL_APB_CPU_R5_CTRL_DIVISOR0_DEFVAL 0x03000600 -#define CRL_APB_CPU_R5_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_CPU_R5_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRL_APB_CPU_R5_CTRL_DIVISOR0_DEFVAL 0x03000600 +#define CRL_APB_CPU_R5_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_CPU_R5_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRL_APB_CPU_R5_CTRL_SRCSEL_DEFVAL #undef CRL_APB_CPU_R5_CTRL_SRCSEL_SHIFT #undef CRL_APB_CPU_R5_CTRL_SRCSEL_MASK -#define CRL_APB_CPU_R5_CTRL_SRCSEL_DEFVAL 0x03000600 -#define CRL_APB_CPU_R5_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_CPU_R5_CTRL_SRCSEL_MASK 0x00000007U +#define CRL_APB_CPU_R5_CTRL_SRCSEL_DEFVAL 0x03000600 +#define CRL_APB_CPU_R5_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_CPU_R5_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRL_APB_IOU_SWITCH_CTRL_CLKACT_DEFVAL #undef CRL_APB_IOU_SWITCH_CTRL_CLKACT_SHIFT #undef CRL_APB_IOU_SWITCH_CTRL_CLKACT_MASK -#define CRL_APB_IOU_SWITCH_CTRL_CLKACT_DEFVAL 0x00001500 -#define CRL_APB_IOU_SWITCH_CTRL_CLKACT_SHIFT 24 -#define CRL_APB_IOU_SWITCH_CTRL_CLKACT_MASK 0x01000000U +#define CRL_APB_IOU_SWITCH_CTRL_CLKACT_DEFVAL 0x00001500 +#define CRL_APB_IOU_SWITCH_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_IOU_SWITCH_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_DEFVAL #undef CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_SHIFT #undef CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_MASK -#define CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_DEFVAL 0x00001500 -#define CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_DEFVAL 0x00001500 +#define CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRL_APB_IOU_SWITCH_CTRL_SRCSEL_DEFVAL #undef CRL_APB_IOU_SWITCH_CTRL_SRCSEL_SHIFT #undef CRL_APB_IOU_SWITCH_CTRL_SRCSEL_MASK -#define CRL_APB_IOU_SWITCH_CTRL_SRCSEL_DEFVAL 0x00001500 -#define CRL_APB_IOU_SWITCH_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_IOU_SWITCH_CTRL_SRCSEL_MASK 0x00000007U +#define CRL_APB_IOU_SWITCH_CTRL_SRCSEL_DEFVAL 0x00001500 +#define CRL_APB_IOU_SWITCH_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_IOU_SWITCH_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRL_APB_PCAP_CTRL_CLKACT_DEFVAL #undef CRL_APB_PCAP_CTRL_CLKACT_SHIFT #undef CRL_APB_PCAP_CTRL_CLKACT_MASK -#define CRL_APB_PCAP_CTRL_CLKACT_DEFVAL 0x00001500 -#define CRL_APB_PCAP_CTRL_CLKACT_SHIFT 24 -#define CRL_APB_PCAP_CTRL_CLKACT_MASK 0x01000000U +#define CRL_APB_PCAP_CTRL_CLKACT_DEFVAL 0x00001500 +#define CRL_APB_PCAP_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_PCAP_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_PCAP_CTRL_DIVISOR0_DEFVAL #undef CRL_APB_PCAP_CTRL_DIVISOR0_SHIFT #undef CRL_APB_PCAP_CTRL_DIVISOR0_MASK -#define CRL_APB_PCAP_CTRL_DIVISOR0_DEFVAL 0x00001500 -#define CRL_APB_PCAP_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_PCAP_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRL_APB_PCAP_CTRL_DIVISOR0_DEFVAL 0x00001500 +#define CRL_APB_PCAP_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_PCAP_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRL_APB_PCAP_CTRL_SRCSEL_DEFVAL #undef CRL_APB_PCAP_CTRL_SRCSEL_SHIFT #undef CRL_APB_PCAP_CTRL_SRCSEL_MASK -#define CRL_APB_PCAP_CTRL_SRCSEL_DEFVAL 0x00001500 -#define CRL_APB_PCAP_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_PCAP_CTRL_SRCSEL_MASK 0x00000007U +#define CRL_APB_PCAP_CTRL_SRCSEL_DEFVAL 0x00001500 +#define CRL_APB_PCAP_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_PCAP_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRL_APB_LPD_SWITCH_CTRL_CLKACT_DEFVAL #undef CRL_APB_LPD_SWITCH_CTRL_CLKACT_SHIFT #undef CRL_APB_LPD_SWITCH_CTRL_CLKACT_MASK -#define CRL_APB_LPD_SWITCH_CTRL_CLKACT_DEFVAL 0x01000500 -#define CRL_APB_LPD_SWITCH_CTRL_CLKACT_SHIFT 24 -#define CRL_APB_LPD_SWITCH_CTRL_CLKACT_MASK 0x01000000U +#define CRL_APB_LPD_SWITCH_CTRL_CLKACT_DEFVAL 0x01000500 +#define CRL_APB_LPD_SWITCH_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_LPD_SWITCH_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_DEFVAL #undef CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_SHIFT #undef CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_MASK -#define CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_DEFVAL 0x01000500 -#define CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_DEFVAL 0x01000500 +#define CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRL_APB_LPD_SWITCH_CTRL_SRCSEL_DEFVAL #undef CRL_APB_LPD_SWITCH_CTRL_SRCSEL_SHIFT #undef CRL_APB_LPD_SWITCH_CTRL_SRCSEL_MASK -#define CRL_APB_LPD_SWITCH_CTRL_SRCSEL_DEFVAL 0x01000500 -#define CRL_APB_LPD_SWITCH_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_LPD_SWITCH_CTRL_SRCSEL_MASK 0x00000007U +#define CRL_APB_LPD_SWITCH_CTRL_SRCSEL_DEFVAL 0x01000500 +#define CRL_APB_LPD_SWITCH_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_LPD_SWITCH_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRL_APB_LPD_LSBUS_CTRL_CLKACT_DEFVAL #undef CRL_APB_LPD_LSBUS_CTRL_CLKACT_SHIFT #undef CRL_APB_LPD_LSBUS_CTRL_CLKACT_MASK -#define CRL_APB_LPD_LSBUS_CTRL_CLKACT_DEFVAL 0x01001800 -#define CRL_APB_LPD_LSBUS_CTRL_CLKACT_SHIFT 24 -#define CRL_APB_LPD_LSBUS_CTRL_CLKACT_MASK 0x01000000U +#define CRL_APB_LPD_LSBUS_CTRL_CLKACT_DEFVAL 0x01001800 +#define CRL_APB_LPD_LSBUS_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_LPD_LSBUS_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_DEFVAL #undef CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_SHIFT #undef CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_MASK -#define CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_DEFVAL 0x01001800 -#define CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_DEFVAL 0x01001800 +#define CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRL_APB_LPD_LSBUS_CTRL_SRCSEL_DEFVAL #undef CRL_APB_LPD_LSBUS_CTRL_SRCSEL_SHIFT #undef CRL_APB_LPD_LSBUS_CTRL_SRCSEL_MASK -#define CRL_APB_LPD_LSBUS_CTRL_SRCSEL_DEFVAL 0x01001800 -#define CRL_APB_LPD_LSBUS_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_LPD_LSBUS_CTRL_SRCSEL_MASK 0x00000007U +#define CRL_APB_LPD_LSBUS_CTRL_SRCSEL_DEFVAL 0x01001800 +#define CRL_APB_LPD_LSBUS_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_LPD_LSBUS_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRL_APB_DBG_LPD_CTRL_CLKACT_DEFVAL #undef CRL_APB_DBG_LPD_CTRL_CLKACT_SHIFT #undef CRL_APB_DBG_LPD_CTRL_CLKACT_MASK -#define CRL_APB_DBG_LPD_CTRL_CLKACT_DEFVAL 0x01002000 -#define CRL_APB_DBG_LPD_CTRL_CLKACT_SHIFT 24 -#define CRL_APB_DBG_LPD_CTRL_CLKACT_MASK 0x01000000U +#define CRL_APB_DBG_LPD_CTRL_CLKACT_DEFVAL 0x01002000 +#define CRL_APB_DBG_LPD_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_DBG_LPD_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_DBG_LPD_CTRL_DIVISOR0_DEFVAL #undef CRL_APB_DBG_LPD_CTRL_DIVISOR0_SHIFT #undef CRL_APB_DBG_LPD_CTRL_DIVISOR0_MASK -#define CRL_APB_DBG_LPD_CTRL_DIVISOR0_DEFVAL 0x01002000 -#define CRL_APB_DBG_LPD_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_DBG_LPD_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRL_APB_DBG_LPD_CTRL_DIVISOR0_DEFVAL 0x01002000 +#define CRL_APB_DBG_LPD_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_DBG_LPD_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRL_APB_DBG_LPD_CTRL_SRCSEL_DEFVAL #undef CRL_APB_DBG_LPD_CTRL_SRCSEL_SHIFT #undef CRL_APB_DBG_LPD_CTRL_SRCSEL_MASK -#define CRL_APB_DBG_LPD_CTRL_SRCSEL_DEFVAL 0x01002000 -#define CRL_APB_DBG_LPD_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_DBG_LPD_CTRL_SRCSEL_MASK 0x00000007U +#define CRL_APB_DBG_LPD_CTRL_SRCSEL_DEFVAL 0x01002000 +#define CRL_APB_DBG_LPD_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_DBG_LPD_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRL_APB_ADMA_REF_CTRL_CLKACT_DEFVAL #undef CRL_APB_ADMA_REF_CTRL_CLKACT_SHIFT #undef CRL_APB_ADMA_REF_CTRL_CLKACT_MASK -#define CRL_APB_ADMA_REF_CTRL_CLKACT_DEFVAL 0x00002000 -#define CRL_APB_ADMA_REF_CTRL_CLKACT_SHIFT 24 -#define CRL_APB_ADMA_REF_CTRL_CLKACT_MASK 0x01000000U +#define CRL_APB_ADMA_REF_CTRL_CLKACT_DEFVAL 0x00002000 +#define CRL_APB_ADMA_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_ADMA_REF_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_ADMA_REF_CTRL_DIVISOR0_DEFVAL #undef CRL_APB_ADMA_REF_CTRL_DIVISOR0_SHIFT #undef CRL_APB_ADMA_REF_CTRL_DIVISOR0_MASK -#define CRL_APB_ADMA_REF_CTRL_DIVISOR0_DEFVAL 0x00002000 -#define CRL_APB_ADMA_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_ADMA_REF_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRL_APB_ADMA_REF_CTRL_DIVISOR0_DEFVAL 0x00002000 +#define CRL_APB_ADMA_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_ADMA_REF_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRL_APB_ADMA_REF_CTRL_SRCSEL_DEFVAL #undef CRL_APB_ADMA_REF_CTRL_SRCSEL_SHIFT #undef CRL_APB_ADMA_REF_CTRL_SRCSEL_MASK -#define CRL_APB_ADMA_REF_CTRL_SRCSEL_DEFVAL 0x00002000 -#define CRL_APB_ADMA_REF_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_ADMA_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRL_APB_ADMA_REF_CTRL_SRCSEL_DEFVAL 0x00002000 +#define CRL_APB_ADMA_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_ADMA_REF_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRL_APB_PL0_REF_CTRL_CLKACT_DEFVAL #undef CRL_APB_PL0_REF_CTRL_CLKACT_SHIFT #undef CRL_APB_PL0_REF_CTRL_CLKACT_MASK -#define CRL_APB_PL0_REF_CTRL_CLKACT_DEFVAL 0x00052000 -#define CRL_APB_PL0_REF_CTRL_CLKACT_SHIFT 24 -#define CRL_APB_PL0_REF_CTRL_CLKACT_MASK 0x01000000U +#define CRL_APB_PL0_REF_CTRL_CLKACT_DEFVAL 0x00052000 +#define CRL_APB_PL0_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_PL0_REF_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_PL0_REF_CTRL_DIVISOR1_DEFVAL #undef CRL_APB_PL0_REF_CTRL_DIVISOR1_SHIFT #undef CRL_APB_PL0_REF_CTRL_DIVISOR1_MASK -#define CRL_APB_PL0_REF_CTRL_DIVISOR1_DEFVAL 0x00052000 -#define CRL_APB_PL0_REF_CTRL_DIVISOR1_SHIFT 16 -#define CRL_APB_PL0_REF_CTRL_DIVISOR1_MASK 0x003F0000U +#define CRL_APB_PL0_REF_CTRL_DIVISOR1_DEFVAL 0x00052000 +#define CRL_APB_PL0_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_PL0_REF_CTRL_DIVISOR1_MASK 0x003F0000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_PL0_REF_CTRL_DIVISOR0_DEFVAL #undef CRL_APB_PL0_REF_CTRL_DIVISOR0_SHIFT #undef CRL_APB_PL0_REF_CTRL_DIVISOR0_MASK -#define CRL_APB_PL0_REF_CTRL_DIVISOR0_DEFVAL 0x00052000 -#define CRL_APB_PL0_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_PL0_REF_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRL_APB_PL0_REF_CTRL_DIVISOR0_DEFVAL 0x00052000 +#define CRL_APB_PL0_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_PL0_REF_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRL_APB_PL0_REF_CTRL_SRCSEL_DEFVAL #undef CRL_APB_PL0_REF_CTRL_SRCSEL_SHIFT #undef CRL_APB_PL0_REF_CTRL_SRCSEL_MASK -#define CRL_APB_PL0_REF_CTRL_SRCSEL_DEFVAL 0x00052000 -#define CRL_APB_PL0_REF_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_PL0_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRL_APB_PL0_REF_CTRL_SRCSEL_DEFVAL 0x00052000 +#define CRL_APB_PL0_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_PL0_REF_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ -#undef CRL_APB_PL1_REF_CTRL_CLKACT_DEFVAL -#undef CRL_APB_PL1_REF_CTRL_CLKACT_SHIFT -#undef CRL_APB_PL1_REF_CTRL_CLKACT_MASK -#define CRL_APB_PL1_REF_CTRL_CLKACT_DEFVAL 0x00052000 -#define CRL_APB_PL1_REF_CTRL_CLKACT_SHIFT 24 -#define CRL_APB_PL1_REF_CTRL_CLKACT_MASK 0x01000000U - -/*6 bit divider*/ -#undef CRL_APB_PL1_REF_CTRL_DIVISOR1_DEFVAL -#undef CRL_APB_PL1_REF_CTRL_DIVISOR1_SHIFT -#undef CRL_APB_PL1_REF_CTRL_DIVISOR1_MASK -#define CRL_APB_PL1_REF_CTRL_DIVISOR1_DEFVAL 0x00052000 -#define CRL_APB_PL1_REF_CTRL_DIVISOR1_SHIFT 16 -#define CRL_APB_PL1_REF_CTRL_DIVISOR1_MASK 0x003F0000U - -/*6 bit divider*/ -#undef CRL_APB_PL1_REF_CTRL_DIVISOR0_DEFVAL -#undef CRL_APB_PL1_REF_CTRL_DIVISOR0_SHIFT -#undef CRL_APB_PL1_REF_CTRL_DIVISOR0_MASK -#define CRL_APB_PL1_REF_CTRL_DIVISOR0_DEFVAL 0x00052000 -#define CRL_APB_PL1_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_PL1_REF_CTRL_DIVISOR0_MASK 0x00003F00U - -/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.)*/ -#undef CRL_APB_PL1_REF_CTRL_SRCSEL_DEFVAL -#undef CRL_APB_PL1_REF_CTRL_SRCSEL_SHIFT -#undef CRL_APB_PL1_REF_CTRL_SRCSEL_MASK -#define CRL_APB_PL1_REF_CTRL_SRCSEL_DEFVAL 0x00052000 -#define CRL_APB_PL1_REF_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_PL1_REF_CTRL_SRCSEL_MASK 0x00000007U - -/*Clock active signal. Switch to 0 to disable the clock*/ -#undef CRL_APB_PL2_REF_CTRL_CLKACT_DEFVAL -#undef CRL_APB_PL2_REF_CTRL_CLKACT_SHIFT -#undef CRL_APB_PL2_REF_CTRL_CLKACT_MASK -#define CRL_APB_PL2_REF_CTRL_CLKACT_DEFVAL 0x00052000 -#define CRL_APB_PL2_REF_CTRL_CLKACT_SHIFT 24 -#define CRL_APB_PL2_REF_CTRL_CLKACT_MASK 0x01000000U - -/*6 bit divider*/ -#undef CRL_APB_PL2_REF_CTRL_DIVISOR1_DEFVAL -#undef CRL_APB_PL2_REF_CTRL_DIVISOR1_SHIFT -#undef CRL_APB_PL2_REF_CTRL_DIVISOR1_MASK -#define CRL_APB_PL2_REF_CTRL_DIVISOR1_DEFVAL 0x00052000 -#define CRL_APB_PL2_REF_CTRL_DIVISOR1_SHIFT 16 -#define CRL_APB_PL2_REF_CTRL_DIVISOR1_MASK 0x003F0000U - -/*6 bit divider*/ -#undef CRL_APB_PL2_REF_CTRL_DIVISOR0_DEFVAL -#undef CRL_APB_PL2_REF_CTRL_DIVISOR0_SHIFT -#undef CRL_APB_PL2_REF_CTRL_DIVISOR0_MASK -#define CRL_APB_PL2_REF_CTRL_DIVISOR0_DEFVAL 0x00052000 -#define CRL_APB_PL2_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_PL2_REF_CTRL_DIVISOR0_MASK 0x00003F00U - -/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.)*/ -#undef CRL_APB_PL2_REF_CTRL_SRCSEL_DEFVAL -#undef CRL_APB_PL2_REF_CTRL_SRCSEL_SHIFT -#undef CRL_APB_PL2_REF_CTRL_SRCSEL_MASK -#define CRL_APB_PL2_REF_CTRL_SRCSEL_DEFVAL 0x00052000 -#define CRL_APB_PL2_REF_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_PL2_REF_CTRL_SRCSEL_MASK 0x00000007U - -/*Clock active signal. Switch to 0 to disable the clock*/ -#undef CRL_APB_PL3_REF_CTRL_CLKACT_DEFVAL -#undef CRL_APB_PL3_REF_CTRL_CLKACT_SHIFT -#undef CRL_APB_PL3_REF_CTRL_CLKACT_MASK -#define CRL_APB_PL3_REF_CTRL_CLKACT_DEFVAL 0x00052000 -#define CRL_APB_PL3_REF_CTRL_CLKACT_SHIFT 24 -#define CRL_APB_PL3_REF_CTRL_CLKACT_MASK 0x01000000U - -/*6 bit divider*/ -#undef CRL_APB_PL3_REF_CTRL_DIVISOR1_DEFVAL -#undef CRL_APB_PL3_REF_CTRL_DIVISOR1_SHIFT -#undef CRL_APB_PL3_REF_CTRL_DIVISOR1_MASK -#define CRL_APB_PL3_REF_CTRL_DIVISOR1_DEFVAL 0x00052000 -#define CRL_APB_PL3_REF_CTRL_DIVISOR1_SHIFT 16 -#define CRL_APB_PL3_REF_CTRL_DIVISOR1_MASK 0x003F0000U - -/*6 bit divider*/ -#undef CRL_APB_PL3_REF_CTRL_DIVISOR0_DEFVAL -#undef CRL_APB_PL3_REF_CTRL_DIVISOR0_SHIFT -#undef CRL_APB_PL3_REF_CTRL_DIVISOR0_MASK -#define CRL_APB_PL3_REF_CTRL_DIVISOR0_DEFVAL 0x00052000 -#define CRL_APB_PL3_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_PL3_REF_CTRL_DIVISOR0_MASK 0x00003F00U - -/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.)*/ -#undef CRL_APB_PL3_REF_CTRL_SRCSEL_DEFVAL -#undef CRL_APB_PL3_REF_CTRL_SRCSEL_SHIFT -#undef CRL_APB_PL3_REF_CTRL_SRCSEL_MASK -#define CRL_APB_PL3_REF_CTRL_SRCSEL_DEFVAL 0x00052000 -#define CRL_APB_PL3_REF_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_PL3_REF_CTRL_SRCSEL_MASK 0x00000007U - -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_AMS_REF_CTRL_DIVISOR1_DEFVAL #undef CRL_APB_AMS_REF_CTRL_DIVISOR1_SHIFT #undef CRL_APB_AMS_REF_CTRL_DIVISOR1_MASK -#define CRL_APB_AMS_REF_CTRL_DIVISOR1_DEFVAL 0x01001800 -#define CRL_APB_AMS_REF_CTRL_DIVISOR1_SHIFT 16 -#define CRL_APB_AMS_REF_CTRL_DIVISOR1_MASK 0x003F0000U +#define CRL_APB_AMS_REF_CTRL_DIVISOR1_DEFVAL 0x01001800 +#define CRL_APB_AMS_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_AMS_REF_CTRL_DIVISOR1_MASK 0x003F0000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_AMS_REF_CTRL_DIVISOR0_DEFVAL #undef CRL_APB_AMS_REF_CTRL_DIVISOR0_SHIFT #undef CRL_APB_AMS_REF_CTRL_DIVISOR0_MASK -#define CRL_APB_AMS_REF_CTRL_DIVISOR0_DEFVAL 0x01001800 -#define CRL_APB_AMS_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_AMS_REF_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRL_APB_AMS_REF_CTRL_DIVISOR0_DEFVAL 0x01001800 +#define CRL_APB_AMS_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_AMS_REF_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRL_APB_AMS_REF_CTRL_SRCSEL_DEFVAL #undef CRL_APB_AMS_REF_CTRL_SRCSEL_SHIFT #undef CRL_APB_AMS_REF_CTRL_SRCSEL_MASK -#define CRL_APB_AMS_REF_CTRL_SRCSEL_DEFVAL 0x01001800 -#define CRL_APB_AMS_REF_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_AMS_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRL_APB_AMS_REF_CTRL_SRCSEL_DEFVAL 0x01001800 +#define CRL_APB_AMS_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_AMS_REF_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRL_APB_AMS_REF_CTRL_CLKACT_DEFVAL #undef CRL_APB_AMS_REF_CTRL_CLKACT_SHIFT #undef CRL_APB_AMS_REF_CTRL_CLKACT_MASK -#define CRL_APB_AMS_REF_CTRL_CLKACT_DEFVAL 0x01001800 -#define CRL_APB_AMS_REF_CTRL_CLKACT_SHIFT 24 -#define CRL_APB_AMS_REF_CTRL_CLKACT_MASK 0x01000000U +#define CRL_APB_AMS_REF_CTRL_CLKACT_DEFVAL 0x01001800 +#define CRL_APB_AMS_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_AMS_REF_CTRL_CLKACT_MASK 0x01000000U -/*000 = IOPLL; 001 = RPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This - is not usually an issue, but designers must be aware.)*/ +/* +* 000 = IOPLL; 001 = RPLL; (This signal may only be toggled after 4 cycles + * of the old clock and 4 cycles of the new clock. This is not usually an + * issue, but designers must be aware.) +*/ #undef CRL_APB_DLL_REF_CTRL_SRCSEL_DEFVAL #undef CRL_APB_DLL_REF_CTRL_SRCSEL_SHIFT #undef CRL_APB_DLL_REF_CTRL_SRCSEL_MASK -#define CRL_APB_DLL_REF_CTRL_SRCSEL_DEFVAL 0x00000000 -#define CRL_APB_DLL_REF_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_DLL_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRL_APB_DLL_REF_CTRL_SRCSEL_DEFVAL 0x00000000 +#define CRL_APB_DLL_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_DLL_REF_CTRL_SRCSEL_MASK 0x00000007U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_DEFVAL #undef CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_SHIFT #undef CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_MASK -#define CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_DEFVAL 0x00001800 -#define CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_DEFVAL 0x00001800 +#define CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_MASK 0x00003F00U -/*1XX = pss_ref_clk; 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and - cycles of the new clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 1XX = pss_ref_clk; 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may + * only be toggled after 4 cycles of the old clock and 4 cycles of the new + * clock. This is not usually an issue, but designers must be aware.) +*/ #undef CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_DEFVAL #undef CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_SHIFT #undef CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_MASK -#define CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_DEFVAL 0x00001800 -#define CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_DEFVAL 0x00001800 +#define CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_DEFVAL #undef CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_SHIFT #undef CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_MASK -#define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_DEFVAL 0x00001800 -#define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_SHIFT 24 -#define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_MASK 0x01000000U +#define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_DEFVAL 0x00001800 +#define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_MASK 0x01000000U -/*000 = IOPLL_TO_FPD; 010 = APLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of - he new clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = IOPLL_TO_FPD; 010 = APLL; 011 = DPLL; (This signal may only be tog + * gled after 4 cycles of the old clock and 4 cycles of the new clock. This + * is not usually an issue, but designers must be aware.) +*/ #undef CRF_APB_SATA_REF_CTRL_SRCSEL_DEFVAL #undef CRF_APB_SATA_REF_CTRL_SRCSEL_SHIFT #undef CRF_APB_SATA_REF_CTRL_SRCSEL_MASK -#define CRF_APB_SATA_REF_CTRL_SRCSEL_DEFVAL 0x01001600 -#define CRF_APB_SATA_REF_CTRL_SRCSEL_SHIFT 0 -#define CRF_APB_SATA_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRF_APB_SATA_REF_CTRL_SRCSEL_DEFVAL 0x01001600 +#define CRF_APB_SATA_REF_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_SATA_REF_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRF_APB_SATA_REF_CTRL_CLKACT_DEFVAL #undef CRF_APB_SATA_REF_CTRL_CLKACT_SHIFT #undef CRF_APB_SATA_REF_CTRL_CLKACT_MASK -#define CRF_APB_SATA_REF_CTRL_CLKACT_DEFVAL 0x01001600 -#define CRF_APB_SATA_REF_CTRL_CLKACT_SHIFT 24 -#define CRF_APB_SATA_REF_CTRL_CLKACT_MASK 0x01000000U +#define CRF_APB_SATA_REF_CTRL_CLKACT_DEFVAL 0x01001600 +#define CRF_APB_SATA_REF_CTRL_CLKACT_SHIFT 24 +#define CRF_APB_SATA_REF_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRF_APB_SATA_REF_CTRL_DIVISOR0_DEFVAL #undef CRF_APB_SATA_REF_CTRL_DIVISOR0_SHIFT #undef CRF_APB_SATA_REF_CTRL_DIVISOR0_MASK -#define CRF_APB_SATA_REF_CTRL_DIVISOR0_DEFVAL 0x01001600 -#define CRF_APB_SATA_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRF_APB_SATA_REF_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRF_APB_SATA_REF_CTRL_DIVISOR0_DEFVAL 0x01001600 +#define CRF_APB_SATA_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_SATA_REF_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = IOPLL_TO_FPD; 010 = RPLL_TO_FPD; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cyc - es of the new clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = IOPLL_TO_FPD; 010 = RPLL_TO_FPD; 011 = DPLL; (This signal may only + * be toggled after 4 cycles of the old clock and 4 cycles of the new cloc + * k. This is not usually an issue, but designers must be aware.) +*/ #undef CRF_APB_PCIE_REF_CTRL_SRCSEL_DEFVAL #undef CRF_APB_PCIE_REF_CTRL_SRCSEL_SHIFT #undef CRF_APB_PCIE_REF_CTRL_SRCSEL_MASK -#define CRF_APB_PCIE_REF_CTRL_SRCSEL_DEFVAL 0x00001500 -#define CRF_APB_PCIE_REF_CTRL_SRCSEL_SHIFT 0 -#define CRF_APB_PCIE_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRF_APB_PCIE_REF_CTRL_SRCSEL_DEFVAL 0x00001500 +#define CRF_APB_PCIE_REF_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_PCIE_REF_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRF_APB_PCIE_REF_CTRL_CLKACT_DEFVAL #undef CRF_APB_PCIE_REF_CTRL_CLKACT_SHIFT #undef CRF_APB_PCIE_REF_CTRL_CLKACT_MASK -#define CRF_APB_PCIE_REF_CTRL_CLKACT_DEFVAL 0x00001500 -#define CRF_APB_PCIE_REF_CTRL_CLKACT_SHIFT 24 -#define CRF_APB_PCIE_REF_CTRL_CLKACT_MASK 0x01000000U +#define CRF_APB_PCIE_REF_CTRL_CLKACT_DEFVAL 0x00001500 +#define CRF_APB_PCIE_REF_CTRL_CLKACT_SHIFT 24 +#define CRF_APB_PCIE_REF_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRF_APB_PCIE_REF_CTRL_DIVISOR0_DEFVAL #undef CRF_APB_PCIE_REF_CTRL_DIVISOR0_SHIFT #undef CRF_APB_PCIE_REF_CTRL_DIVISOR0_MASK -#define CRF_APB_PCIE_REF_CTRL_DIVISOR0_DEFVAL 0x00001500 -#define CRF_APB_PCIE_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRF_APB_PCIE_REF_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRF_APB_PCIE_REF_CTRL_DIVISOR0_DEFVAL 0x00001500 +#define CRF_APB_PCIE_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_PCIE_REF_CTRL_DIVISOR0_MASK 0x00003F00U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_DEFVAL #undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_SHIFT #undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_MASK -#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_DEFVAL 0x01002300 -#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_SHIFT 16 -#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_MASK 0x003F0000U +#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_DEFVAL 0x01002300 +#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_MASK 0x003F0000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_DEFVAL #undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_SHIFT #undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_MASK -#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_DEFVAL 0x01002300 -#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_DEFVAL 0x01002300 +#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (This signal may only be toggled after 4 cycles of the - ld clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (T + * his signal may only be toggled after 4 cycles of the old clock and 4 cyc + * les of the new clock. This is not usually an issue, but designers must b + * e aware.) +*/ #undef CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_DEFVAL #undef CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_SHIFT #undef CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_MASK -#define CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_DEFVAL 0x01002300 -#define CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_SHIFT 0 -#define CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_DEFVAL 0x01002300 +#define CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_DEFVAL #undef CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_SHIFT #undef CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_MASK -#define CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_DEFVAL 0x01002300 -#define CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_SHIFT 24 -#define CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_MASK 0x01000000U +#define CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_DEFVAL 0x01002300 +#define CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_SHIFT 24 +#define CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_DEFVAL #undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_SHIFT #undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_MASK -#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_DEFVAL 0x01032300 -#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_SHIFT 16 -#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_MASK 0x003F0000U +#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_DEFVAL 0x01032300 +#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_MASK 0x003F0000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_DEFVAL #undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_SHIFT #undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_MASK -#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_DEFVAL 0x01032300 -#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_DEFVAL 0x01032300 +#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (This signal may only be toggled after 4 cycles of the - ld clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (T + * his signal may only be toggled after 4 cycles of the old clock and 4 cyc + * les of the new clock. This is not usually an issue, but designers must b + * e aware.) +*/ #undef CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_DEFVAL #undef CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_SHIFT #undef CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_MASK -#define CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_DEFVAL 0x01032300 -#define CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_SHIFT 0 -#define CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_DEFVAL 0x01032300 +#define CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_DEFVAL #undef CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_SHIFT #undef CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_MASK -#define CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_DEFVAL 0x01032300 -#define CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_SHIFT 24 -#define CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_MASK 0x01000000U +#define CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_DEFVAL 0x01032300 +#define CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_SHIFT 24 +#define CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRF_APB_DP_STC_REF_CTRL_DIVISOR1_DEFVAL #undef CRF_APB_DP_STC_REF_CTRL_DIVISOR1_SHIFT #undef CRF_APB_DP_STC_REF_CTRL_DIVISOR1_MASK -#define CRF_APB_DP_STC_REF_CTRL_DIVISOR1_DEFVAL 0x01203200 -#define CRF_APB_DP_STC_REF_CTRL_DIVISOR1_SHIFT 16 -#define CRF_APB_DP_STC_REF_CTRL_DIVISOR1_MASK 0x003F0000U +#define CRF_APB_DP_STC_REF_CTRL_DIVISOR1_DEFVAL 0x01203200 +#define CRF_APB_DP_STC_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRF_APB_DP_STC_REF_CTRL_DIVISOR1_MASK 0x003F0000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRF_APB_DP_STC_REF_CTRL_DIVISOR0_DEFVAL #undef CRF_APB_DP_STC_REF_CTRL_DIVISOR0_SHIFT #undef CRF_APB_DP_STC_REF_CTRL_DIVISOR0_MASK -#define CRF_APB_DP_STC_REF_CTRL_DIVISOR0_DEFVAL 0x01203200 -#define CRF_APB_DP_STC_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRF_APB_DP_STC_REF_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRF_APB_DP_STC_REF_CTRL_DIVISOR0_DEFVAL 0x01203200 +#define CRF_APB_DP_STC_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_DP_STC_REF_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of t - e new clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD; (This signal may only be togg + * led after 4 cycles of the old clock and 4 cycles of the new clock. This + * is not usually an issue, but designers must be aware.) +*/ #undef CRF_APB_DP_STC_REF_CTRL_SRCSEL_DEFVAL #undef CRF_APB_DP_STC_REF_CTRL_SRCSEL_SHIFT #undef CRF_APB_DP_STC_REF_CTRL_SRCSEL_MASK -#define CRF_APB_DP_STC_REF_CTRL_SRCSEL_DEFVAL 0x01203200 -#define CRF_APB_DP_STC_REF_CTRL_SRCSEL_SHIFT 0 -#define CRF_APB_DP_STC_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRF_APB_DP_STC_REF_CTRL_SRCSEL_DEFVAL 0x01203200 +#define CRF_APB_DP_STC_REF_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_DP_STC_REF_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRF_APB_DP_STC_REF_CTRL_CLKACT_DEFVAL #undef CRF_APB_DP_STC_REF_CTRL_CLKACT_SHIFT #undef CRF_APB_DP_STC_REF_CTRL_CLKACT_MASK -#define CRF_APB_DP_STC_REF_CTRL_CLKACT_DEFVAL 0x01203200 -#define CRF_APB_DP_STC_REF_CTRL_CLKACT_SHIFT 24 -#define CRF_APB_DP_STC_REF_CTRL_CLKACT_MASK 0x01000000U +#define CRF_APB_DP_STC_REF_CTRL_CLKACT_DEFVAL 0x01203200 +#define CRF_APB_DP_STC_REF_CTRL_CLKACT_SHIFT 24 +#define CRF_APB_DP_STC_REF_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRF_APB_ACPU_CTRL_DIVISOR0_DEFVAL #undef CRF_APB_ACPU_CTRL_DIVISOR0_SHIFT #undef CRF_APB_ACPU_CTRL_DIVISOR0_MASK -#define CRF_APB_ACPU_CTRL_DIVISOR0_DEFVAL 0x03000400 -#define CRF_APB_ACPU_CTRL_DIVISOR0_SHIFT 8 -#define CRF_APB_ACPU_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRF_APB_ACPU_CTRL_DIVISOR0_DEFVAL 0x03000400 +#define CRF_APB_ACPU_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_ACPU_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = APLL; 010 = DPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - lock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = APLL; 010 = DPLL; 011 = VPLL; (This signal may only be toggled aft + * er 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRF_APB_ACPU_CTRL_SRCSEL_DEFVAL #undef CRF_APB_ACPU_CTRL_SRCSEL_SHIFT #undef CRF_APB_ACPU_CTRL_SRCSEL_MASK -#define CRF_APB_ACPU_CTRL_SRCSEL_DEFVAL 0x03000400 -#define CRF_APB_ACPU_CTRL_SRCSEL_SHIFT 0 -#define CRF_APB_ACPU_CTRL_SRCSEL_MASK 0x00000007U +#define CRF_APB_ACPU_CTRL_SRCSEL_DEFVAL 0x03000400 +#define CRF_APB_ACPU_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_ACPU_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock. For the half speed APU Clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock. For the half spee + * d APU Clock +*/ #undef CRF_APB_ACPU_CTRL_CLKACT_HALF_DEFVAL #undef CRF_APB_ACPU_CTRL_CLKACT_HALF_SHIFT #undef CRF_APB_ACPU_CTRL_CLKACT_HALF_MASK -#define CRF_APB_ACPU_CTRL_CLKACT_HALF_DEFVAL 0x03000400 -#define CRF_APB_ACPU_CTRL_CLKACT_HALF_SHIFT 25 -#define CRF_APB_ACPU_CTRL_CLKACT_HALF_MASK 0x02000000U +#define CRF_APB_ACPU_CTRL_CLKACT_HALF_DEFVAL 0x03000400 +#define CRF_APB_ACPU_CTRL_CLKACT_HALF_SHIFT 25 +#define CRF_APB_ACPU_CTRL_CLKACT_HALF_MASK 0x02000000U -/*Clock active signal. Switch to 0 to disable the clock. For the full speed ACPUX Clock. This will shut off the high speed cloc - to the entire APU*/ +/* +* Clock active signal. Switch to 0 to disable the clock. For the full spee + * d ACPUX Clock. This will shut off the high speed clock to the entire APU +*/ #undef CRF_APB_ACPU_CTRL_CLKACT_FULL_DEFVAL #undef CRF_APB_ACPU_CTRL_CLKACT_FULL_SHIFT #undef CRF_APB_ACPU_CTRL_CLKACT_FULL_MASK -#define CRF_APB_ACPU_CTRL_CLKACT_FULL_DEFVAL 0x03000400 -#define CRF_APB_ACPU_CTRL_CLKACT_FULL_SHIFT 24 -#define CRF_APB_ACPU_CTRL_CLKACT_FULL_MASK 0x01000000U +#define CRF_APB_ACPU_CTRL_CLKACT_FULL_DEFVAL 0x03000400 +#define CRF_APB_ACPU_CTRL_CLKACT_FULL_SHIFT 24 +#define CRF_APB_ACPU_CTRL_CLKACT_FULL_MASK 0x01000000U -/*6 bit divider*/ -#undef CRF_APB_DBG_TRACE_CTRL_DIVISOR0_DEFVAL -#undef CRF_APB_DBG_TRACE_CTRL_DIVISOR0_SHIFT -#undef CRF_APB_DBG_TRACE_CTRL_DIVISOR0_MASK -#define CRF_APB_DBG_TRACE_CTRL_DIVISOR0_DEFVAL 0x00002500 -#define CRF_APB_DBG_TRACE_CTRL_DIVISOR0_SHIFT 8 -#define CRF_APB_DBG_TRACE_CTRL_DIVISOR0_MASK 0x00003F00U - -/*000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of - he new clock. This is not usually an issue, but designers must be aware.)*/ -#undef CRF_APB_DBG_TRACE_CTRL_SRCSEL_DEFVAL -#undef CRF_APB_DBG_TRACE_CTRL_SRCSEL_SHIFT -#undef CRF_APB_DBG_TRACE_CTRL_SRCSEL_MASK -#define CRF_APB_DBG_TRACE_CTRL_SRCSEL_DEFVAL 0x00002500 -#define CRF_APB_DBG_TRACE_CTRL_SRCSEL_SHIFT 0 -#define CRF_APB_DBG_TRACE_CTRL_SRCSEL_MASK 0x00000007U - -/*Clock active signal. Switch to 0 to disable the clock*/ -#undef CRF_APB_DBG_TRACE_CTRL_CLKACT_DEFVAL -#undef CRF_APB_DBG_TRACE_CTRL_CLKACT_SHIFT -#undef CRF_APB_DBG_TRACE_CTRL_CLKACT_MASK -#define CRF_APB_DBG_TRACE_CTRL_CLKACT_DEFVAL 0x00002500 -#define CRF_APB_DBG_TRACE_CTRL_CLKACT_SHIFT 24 -#define CRF_APB_DBG_TRACE_CTRL_CLKACT_MASK 0x01000000U - -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRF_APB_DBG_FPD_CTRL_DIVISOR0_DEFVAL #undef CRF_APB_DBG_FPD_CTRL_DIVISOR0_SHIFT #undef CRF_APB_DBG_FPD_CTRL_DIVISOR0_MASK -#define CRF_APB_DBG_FPD_CTRL_DIVISOR0_DEFVAL 0x01002500 -#define CRF_APB_DBG_FPD_CTRL_DIVISOR0_SHIFT 8 -#define CRF_APB_DBG_FPD_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRF_APB_DBG_FPD_CTRL_DIVISOR0_DEFVAL 0x01002500 +#define CRF_APB_DBG_FPD_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_DBG_FPD_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of - he new clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be tog + * gled after 4 cycles of the old clock and 4 cycles of the new clock. This + * is not usually an issue, but designers must be aware.) +*/ #undef CRF_APB_DBG_FPD_CTRL_SRCSEL_DEFVAL #undef CRF_APB_DBG_FPD_CTRL_SRCSEL_SHIFT #undef CRF_APB_DBG_FPD_CTRL_SRCSEL_MASK -#define CRF_APB_DBG_FPD_CTRL_SRCSEL_DEFVAL 0x01002500 -#define CRF_APB_DBG_FPD_CTRL_SRCSEL_SHIFT 0 -#define CRF_APB_DBG_FPD_CTRL_SRCSEL_MASK 0x00000007U +#define CRF_APB_DBG_FPD_CTRL_SRCSEL_DEFVAL 0x01002500 +#define CRF_APB_DBG_FPD_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_DBG_FPD_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRF_APB_DBG_FPD_CTRL_CLKACT_DEFVAL #undef CRF_APB_DBG_FPD_CTRL_CLKACT_SHIFT #undef CRF_APB_DBG_FPD_CTRL_CLKACT_MASK -#define CRF_APB_DBG_FPD_CTRL_CLKACT_DEFVAL 0x01002500 -#define CRF_APB_DBG_FPD_CTRL_CLKACT_SHIFT 24 -#define CRF_APB_DBG_FPD_CTRL_CLKACT_MASK 0x01000000U +#define CRF_APB_DBG_FPD_CTRL_CLKACT_DEFVAL 0x01002500 +#define CRF_APB_DBG_FPD_CTRL_CLKACT_SHIFT 24 +#define CRF_APB_DBG_FPD_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRF_APB_DDR_CTRL_DIVISOR0_DEFVAL #undef CRF_APB_DDR_CTRL_DIVISOR0_SHIFT #undef CRF_APB_DDR_CTRL_DIVISOR0_MASK -#define CRF_APB_DDR_CTRL_DIVISOR0_DEFVAL 0x01000500 -#define CRF_APB_DDR_CTRL_DIVISOR0_SHIFT 8 -#define CRF_APB_DDR_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRF_APB_DDR_CTRL_DIVISOR0_DEFVAL 0x01000500 +#define CRF_APB_DDR_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_DDR_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = DPLL; 001 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This - s not usually an issue, but designers must be aware.)*/ +/* +* 000 = DPLL; 001 = VPLL; (This signal may only be toggled after 4 cycles + * of the old clock and 4 cycles of the new clock. This is not usually an i + * ssue, but designers must be aware.) +*/ #undef CRF_APB_DDR_CTRL_SRCSEL_DEFVAL #undef CRF_APB_DDR_CTRL_SRCSEL_SHIFT #undef CRF_APB_DDR_CTRL_SRCSEL_MASK -#define CRF_APB_DDR_CTRL_SRCSEL_DEFVAL 0x01000500 -#define CRF_APB_DDR_CTRL_SRCSEL_SHIFT 0 -#define CRF_APB_DDR_CTRL_SRCSEL_MASK 0x00000007U +#define CRF_APB_DDR_CTRL_SRCSEL_DEFVAL 0x01000500 +#define CRF_APB_DDR_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_DDR_CTRL_SRCSEL_MASK 0x00000007U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRF_APB_GPU_REF_CTRL_DIVISOR0_DEFVAL #undef CRF_APB_GPU_REF_CTRL_DIVISOR0_SHIFT #undef CRF_APB_GPU_REF_CTRL_DIVISOR0_MASK -#define CRF_APB_GPU_REF_CTRL_DIVISOR0_DEFVAL 0x00001500 -#define CRF_APB_GPU_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRF_APB_GPU_REF_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRF_APB_GPU_REF_CTRL_DIVISOR0_DEFVAL 0x00001500 +#define CRF_APB_GPU_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_GPU_REF_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = IOPLL_TO_FPD; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of - he new clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = IOPLL_TO_FPD; 010 = VPLL; 011 = DPLL; (This signal may only be tog + * gled after 4 cycles of the old clock and 4 cycles of the new clock. This + * is not usually an issue, but designers must be aware.) +*/ #undef CRF_APB_GPU_REF_CTRL_SRCSEL_DEFVAL #undef CRF_APB_GPU_REF_CTRL_SRCSEL_SHIFT #undef CRF_APB_GPU_REF_CTRL_SRCSEL_MASK -#define CRF_APB_GPU_REF_CTRL_SRCSEL_DEFVAL 0x00001500 -#define CRF_APB_GPU_REF_CTRL_SRCSEL_SHIFT 0 -#define CRF_APB_GPU_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRF_APB_GPU_REF_CTRL_SRCSEL_DEFVAL 0x00001500 +#define CRF_APB_GPU_REF_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_GPU_REF_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock, which will stop clock for GPU (and both Pixel Processors).*/ +/* +* Clock active signal. Switch to 0 to disable the clock, which will stop c + * lock for GPU (and both Pixel Processors). +*/ #undef CRF_APB_GPU_REF_CTRL_CLKACT_DEFVAL #undef CRF_APB_GPU_REF_CTRL_CLKACT_SHIFT #undef CRF_APB_GPU_REF_CTRL_CLKACT_MASK -#define CRF_APB_GPU_REF_CTRL_CLKACT_DEFVAL 0x00001500 -#define CRF_APB_GPU_REF_CTRL_CLKACT_SHIFT 24 -#define CRF_APB_GPU_REF_CTRL_CLKACT_MASK 0x01000000U +#define CRF_APB_GPU_REF_CTRL_CLKACT_DEFVAL 0x00001500 +#define CRF_APB_GPU_REF_CTRL_CLKACT_SHIFT 24 +#define CRF_APB_GPU_REF_CTRL_CLKACT_MASK 0x01000000U -/*Clock active signal for Pixel Processor. Switch to 0 to disable the clock only to this Pixel Processor*/ +/* +* Clock active signal for Pixel Processor. Switch to 0 to disable the cloc + * k only to this Pixel Processor +*/ #undef CRF_APB_GPU_REF_CTRL_PP0_CLKACT_DEFVAL #undef CRF_APB_GPU_REF_CTRL_PP0_CLKACT_SHIFT #undef CRF_APB_GPU_REF_CTRL_PP0_CLKACT_MASK -#define CRF_APB_GPU_REF_CTRL_PP0_CLKACT_DEFVAL 0x00001500 -#define CRF_APB_GPU_REF_CTRL_PP0_CLKACT_SHIFT 25 -#define CRF_APB_GPU_REF_CTRL_PP0_CLKACT_MASK 0x02000000U +#define CRF_APB_GPU_REF_CTRL_PP0_CLKACT_DEFVAL 0x00001500 +#define CRF_APB_GPU_REF_CTRL_PP0_CLKACT_SHIFT 25 +#define CRF_APB_GPU_REF_CTRL_PP0_CLKACT_MASK 0x02000000U -/*Clock active signal for Pixel Processor. Switch to 0 to disable the clock only to this Pixel Processor*/ +/* +* Clock active signal for Pixel Processor. Switch to 0 to disable the cloc + * k only to this Pixel Processor +*/ #undef CRF_APB_GPU_REF_CTRL_PP1_CLKACT_DEFVAL #undef CRF_APB_GPU_REF_CTRL_PP1_CLKACT_SHIFT #undef CRF_APB_GPU_REF_CTRL_PP1_CLKACT_MASK -#define CRF_APB_GPU_REF_CTRL_PP1_CLKACT_DEFVAL 0x00001500 -#define CRF_APB_GPU_REF_CTRL_PP1_CLKACT_SHIFT 26 -#define CRF_APB_GPU_REF_CTRL_PP1_CLKACT_MASK 0x04000000U +#define CRF_APB_GPU_REF_CTRL_PP1_CLKACT_DEFVAL 0x00001500 +#define CRF_APB_GPU_REF_CTRL_PP1_CLKACT_SHIFT 26 +#define CRF_APB_GPU_REF_CTRL_PP1_CLKACT_MASK 0x04000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRF_APB_GDMA_REF_CTRL_DIVISOR0_DEFVAL #undef CRF_APB_GDMA_REF_CTRL_DIVISOR0_SHIFT #undef CRF_APB_GDMA_REF_CTRL_DIVISOR0_MASK -#define CRF_APB_GDMA_REF_CTRL_DIVISOR0_DEFVAL 0x01000500 -#define CRF_APB_GDMA_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRF_APB_GDMA_REF_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRF_APB_GDMA_REF_CTRL_DIVISOR0_DEFVAL 0x01000500 +#define CRF_APB_GDMA_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_GDMA_REF_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - lock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled aft + * er 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRF_APB_GDMA_REF_CTRL_SRCSEL_DEFVAL #undef CRF_APB_GDMA_REF_CTRL_SRCSEL_SHIFT #undef CRF_APB_GDMA_REF_CTRL_SRCSEL_MASK -#define CRF_APB_GDMA_REF_CTRL_SRCSEL_DEFVAL 0x01000500 -#define CRF_APB_GDMA_REF_CTRL_SRCSEL_SHIFT 0 -#define CRF_APB_GDMA_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRF_APB_GDMA_REF_CTRL_SRCSEL_DEFVAL 0x01000500 +#define CRF_APB_GDMA_REF_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_GDMA_REF_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRF_APB_GDMA_REF_CTRL_CLKACT_DEFVAL #undef CRF_APB_GDMA_REF_CTRL_CLKACT_SHIFT #undef CRF_APB_GDMA_REF_CTRL_CLKACT_MASK -#define CRF_APB_GDMA_REF_CTRL_CLKACT_DEFVAL 0x01000500 -#define CRF_APB_GDMA_REF_CTRL_CLKACT_SHIFT 24 -#define CRF_APB_GDMA_REF_CTRL_CLKACT_MASK 0x01000000U +#define CRF_APB_GDMA_REF_CTRL_CLKACT_DEFVAL 0x01000500 +#define CRF_APB_GDMA_REF_CTRL_CLKACT_SHIFT 24 +#define CRF_APB_GDMA_REF_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRF_APB_DPDMA_REF_CTRL_DIVISOR0_DEFVAL #undef CRF_APB_DPDMA_REF_CTRL_DIVISOR0_SHIFT #undef CRF_APB_DPDMA_REF_CTRL_DIVISOR0_MASK -#define CRF_APB_DPDMA_REF_CTRL_DIVISOR0_DEFVAL 0x01000500 -#define CRF_APB_DPDMA_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRF_APB_DPDMA_REF_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRF_APB_DPDMA_REF_CTRL_DIVISOR0_DEFVAL 0x01000500 +#define CRF_APB_DPDMA_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_DPDMA_REF_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - lock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled aft + * er 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRF_APB_DPDMA_REF_CTRL_SRCSEL_DEFVAL #undef CRF_APB_DPDMA_REF_CTRL_SRCSEL_SHIFT #undef CRF_APB_DPDMA_REF_CTRL_SRCSEL_MASK -#define CRF_APB_DPDMA_REF_CTRL_SRCSEL_DEFVAL 0x01000500 -#define CRF_APB_DPDMA_REF_CTRL_SRCSEL_SHIFT 0 -#define CRF_APB_DPDMA_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRF_APB_DPDMA_REF_CTRL_SRCSEL_DEFVAL 0x01000500 +#define CRF_APB_DPDMA_REF_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_DPDMA_REF_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRF_APB_DPDMA_REF_CTRL_CLKACT_DEFVAL #undef CRF_APB_DPDMA_REF_CTRL_CLKACT_SHIFT #undef CRF_APB_DPDMA_REF_CTRL_CLKACT_MASK -#define CRF_APB_DPDMA_REF_CTRL_CLKACT_DEFVAL 0x01000500 -#define CRF_APB_DPDMA_REF_CTRL_CLKACT_SHIFT 24 -#define CRF_APB_DPDMA_REF_CTRL_CLKACT_MASK 0x01000000U +#define CRF_APB_DPDMA_REF_CTRL_CLKACT_DEFVAL 0x01000500 +#define CRF_APB_DPDMA_REF_CTRL_CLKACT_SHIFT 24 +#define CRF_APB_DPDMA_REF_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_DEFVAL #undef CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_SHIFT #undef CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_MASK -#define CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_DEFVAL 0x01000400 -#define CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_SHIFT 8 -#define CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_DEFVAL 0x01000400 +#define CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - lock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled aft + * er 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_DEFVAL #undef CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_SHIFT #undef CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_MASK -#define CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_DEFVAL 0x01000400 -#define CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_SHIFT 0 -#define CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_MASK 0x00000007U +#define CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_DEFVAL 0x01000400 +#define CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRF_APB_TOPSW_MAIN_CTRL_CLKACT_DEFVAL #undef CRF_APB_TOPSW_MAIN_CTRL_CLKACT_SHIFT #undef CRF_APB_TOPSW_MAIN_CTRL_CLKACT_MASK -#define CRF_APB_TOPSW_MAIN_CTRL_CLKACT_DEFVAL 0x01000400 -#define CRF_APB_TOPSW_MAIN_CTRL_CLKACT_SHIFT 24 -#define CRF_APB_TOPSW_MAIN_CTRL_CLKACT_MASK 0x01000000U +#define CRF_APB_TOPSW_MAIN_CTRL_CLKACT_DEFVAL 0x01000400 +#define CRF_APB_TOPSW_MAIN_CTRL_CLKACT_SHIFT 24 +#define CRF_APB_TOPSW_MAIN_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_DEFVAL #undef CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_SHIFT #undef CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_MASK -#define CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_DEFVAL 0x01000800 -#define CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_SHIFT 8 -#define CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_DEFVAL 0x01000800 +#define CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = APLL; 010 = IOPLL_TO_FPD; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of - he new clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = APLL; 010 = IOPLL_TO_FPD; 011 = DPLL; (This signal may only be tog + * gled after 4 cycles of the old clock and 4 cycles of the new clock. This + * is not usually an issue, but designers must be aware.) +*/ #undef CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_DEFVAL #undef CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_SHIFT #undef CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_MASK -#define CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_DEFVAL 0x01000800 -#define CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_SHIFT 0 -#define CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_MASK 0x00000007U +#define CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_DEFVAL 0x01000800 +#define CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_DEFVAL #undef CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_SHIFT #undef CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_MASK -#define CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_DEFVAL 0x01000800 -#define CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_SHIFT 24 -#define CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_MASK 0x01000000U +#define CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_DEFVAL 0x01000800 +#define CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_SHIFT 24 +#define CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_DEFVAL #undef CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_SHIFT #undef CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_MASK -#define CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_DEFVAL 0x00000A00 -#define CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_SHIFT 8 -#define CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_DEFVAL 0x00000A00 +#define CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of - he new clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be tog + * gled after 4 cycles of the old clock and 4 cycles of the new clock. This + * is not usually an issue, but designers must be aware.) +*/ #undef CRF_APB_DBG_TSTMP_CTRL_SRCSEL_DEFVAL #undef CRF_APB_DBG_TSTMP_CTRL_SRCSEL_SHIFT #undef CRF_APB_DBG_TSTMP_CTRL_SRCSEL_MASK -#define CRF_APB_DBG_TSTMP_CTRL_SRCSEL_DEFVAL 0x00000A00 -#define CRF_APB_DBG_TSTMP_CTRL_SRCSEL_SHIFT 0 -#define CRF_APB_DBG_TSTMP_CTRL_SRCSEL_MASK 0x00000007U +#define CRF_APB_DBG_TSTMP_CTRL_SRCSEL_DEFVAL 0x00000A00 +#define CRF_APB_DBG_TSTMP_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_DBG_TSTMP_CTRL_SRCSEL_MASK 0x00000007U -/*00" = Select the APB switch clock for the APB interface of TTC0'01" = Select the PLL ref clock for the APB interface of TTC0' - 0" = Select the R5 clock for the APB interface of TTC0*/ +/* +* 00" = Select the APB switch clock for the APB interface of TTC0'01" = Se + * lect the PLL ref clock for the APB interface of TTC0'10" = Select the R5 + * clock for the APB interface of TTC0 +*/ #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_DEFVAL #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_SHIFT #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_MASK -#define IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_SHIFT 0 -#define IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_MASK 0x00000003U +#define IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_SHIFT 0 +#define IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_MASK 0x00000003U -/*00" = Select the APB switch clock for the APB interface of TTC1'01" = Select the PLL ref clock for the APB interface of TTC1' - 0" = Select the R5 clock for the APB interface of TTC1*/ +/* +* 00" = Select the APB switch clock for the APB interface of TTC1'01" = Se + * lect the PLL ref clock for the APB interface of TTC1'10" = Select the R5 + * clock for the APB interface of TTC1 +*/ #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_DEFVAL #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_SHIFT #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_MASK -#define IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_SHIFT 2 -#define IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_MASK 0x0000000CU +#define IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_SHIFT 2 +#define IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_MASK 0x0000000CU -/*00" = Select the APB switch clock for the APB interface of TTC2'01" = Select the PLL ref clock for the APB interface of TTC2' - 0" = Select the R5 clock for the APB interface of TTC2*/ +/* +* 00" = Select the APB switch clock for the APB interface of TTC2'01" = Se + * lect the PLL ref clock for the APB interface of TTC2'10" = Select the R5 + * clock for the APB interface of TTC2 +*/ #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_DEFVAL #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_SHIFT #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_MASK -#define IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_SHIFT 4 -#define IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_MASK 0x00000030U +#define IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_SHIFT 4 +#define IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_MASK 0x00000030U -/*00" = Select the APB switch clock for the APB interface of TTC3'01" = Select the PLL ref clock for the APB interface of TTC3' - 0" = Select the R5 clock for the APB interface of TTC3*/ +/* +* 00" = Select the APB switch clock for the APB interface of TTC3'01" = Se + * lect the PLL ref clock for the APB interface of TTC3'10" = Select the R5 + * clock for the APB interface of TTC3 +*/ #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_DEFVAL #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_SHIFT #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_MASK -#define IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_SHIFT 6 -#define IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_MASK 0x000000C0U +#define IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_SHIFT 6 +#define IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_MASK 0x000000C0U -/*System watchdog timer clock source selection: 0: Internal APB clock 1: External (PL clock via EMIO or Pinout clock via MIO)*/ +/* +* System watchdog timer clock source selection: 0: Internal APB clock 1: E + * xternal (PL clock via EMIO or Pinout clock via MIO) +*/ #undef FPD_SLCR_WDT_CLK_SEL_SELECT_DEFVAL #undef FPD_SLCR_WDT_CLK_SEL_SELECT_SHIFT #undef FPD_SLCR_WDT_CLK_SEL_SELECT_MASK -#define FPD_SLCR_WDT_CLK_SEL_SELECT_DEFVAL 0x00000000 -#define FPD_SLCR_WDT_CLK_SEL_SELECT_SHIFT 0 -#define FPD_SLCR_WDT_CLK_SEL_SELECT_MASK 0x00000001U +#define FPD_SLCR_WDT_CLK_SEL_SELECT_DEFVAL 0x00000000 +#define FPD_SLCR_WDT_CLK_SEL_SELECT_SHIFT 0 +#define FPD_SLCR_WDT_CLK_SEL_SELECT_MASK 0x00000001U -/*System watchdog timer clock source selection: 0: internal clock APB clock 1: external clock from PL via EMIO, or from pinout - ia MIO*/ +/* +* System watchdog timer clock source selection: 0: internal clock APB cloc + * k 1: external clock from PL via EMIO, or from pinout via MIO +*/ #undef IOU_SLCR_WDT_CLK_SEL_SELECT_DEFVAL #undef IOU_SLCR_WDT_CLK_SEL_SELECT_SHIFT #undef IOU_SLCR_WDT_CLK_SEL_SELECT_MASK -#define IOU_SLCR_WDT_CLK_SEL_SELECT_DEFVAL 0x00000000 -#define IOU_SLCR_WDT_CLK_SEL_SELECT_SHIFT 0 -#define IOU_SLCR_WDT_CLK_SEL_SELECT_MASK 0x00000001U +#define IOU_SLCR_WDT_CLK_SEL_SELECT_DEFVAL 0x00000000 +#define IOU_SLCR_WDT_CLK_SEL_SELECT_SHIFT 0 +#define IOU_SLCR_WDT_CLK_SEL_SELECT_MASK 0x00000001U -/*System watchdog timer clock source selection: 0: internal clock APB clock 1: external clock pss_ref_clk*/ +/* +* System watchdog timer clock source selection: 0: internal clock APB cloc + * k 1: external clock pss_ref_clk +*/ #undef LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_DEFVAL #undef LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_SHIFT #undef LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_MASK -#define LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_DEFVAL 0x00000000 -#define LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_SHIFT 0 -#define LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_MASK 0x00000001U +#define LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_DEFVAL 0x00000000 +#define LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_SHIFT 0 +#define LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_MASK 0x00000001U #undef CRF_APB_RST_DDR_SS_OFFSET #define CRF_APB_RST_DDR_SS_OFFSET 0XFD1A0108 #undef DDRC_MSTR_OFFSET @@ -2078,6 +2380,8 @@ #define DDRC_PWRTMG_OFFSET 0XFD070034 #undef DDRC_RFSHCTL0_OFFSET #define DDRC_RFSHCTL0_OFFSET 0XFD070050 +#undef DDRC_RFSHCTL1_OFFSET +#define DDRC_RFSHCTL1_OFFSET 0XFD070054 #undef DDRC_RFSHCTL3_OFFSET #define DDRC_RFSHCTL3_OFFSET 0XFD070060 #undef DDRC_RFSHTMG_OFFSET @@ -2146,6 +2450,8 @@ #define DDRC_DFILPCFG0_OFFSET 0XFD070198 #undef DDRC_DFILPCFG1_OFFSET #define DDRC_DFILPCFG1_OFFSET 0XFD07019C +#undef DDRC_DFIUPD0_OFFSET +#define DDRC_DFIUPD0_OFFSET 0XFD0701A0 #undef DDRC_DFIUPD1_OFFSET #define DDRC_DFIUPD1_OFFSET 0XFD0701A4 #undef DDRC_DFIMISC_OFFSET @@ -2188,6 +2494,16 @@ #define DDRC_PERFLPR1_OFFSET 0XFD070264 #undef DDRC_PERFWR1_OFFSET #define DDRC_PERFWR1_OFFSET 0XFD07026C +#undef DDRC_DQMAP0_OFFSET +#define DDRC_DQMAP0_OFFSET 0XFD070280 +#undef DDRC_DQMAP1_OFFSET +#define DDRC_DQMAP1_OFFSET 0XFD070284 +#undef DDRC_DQMAP2_OFFSET +#define DDRC_DQMAP2_OFFSET 0XFD070288 +#undef DDRC_DQMAP3_OFFSET +#define DDRC_DQMAP3_OFFSET 0XFD07028C +#undef DDRC_DQMAP4_OFFSET +#define DDRC_DQMAP4_OFFSET 0XFD070290 #undef DDRC_DQMAP5_OFFSET #define DDRC_DQMAP5_OFFSET 0XFD070294 #undef DDRC_DBG0_OFFSET @@ -2294,8 +2610,12 @@ #define DDR_PHY_PTR0_OFFSET 0XFD080040 #undef DDR_PHY_PTR1_OFFSET #define DDR_PHY_PTR1_OFFSET 0XFD080044 +#undef DDR_PHY_PLLCR0_OFFSET +#define DDR_PHY_PLLCR0_OFFSET 0XFD080068 #undef DDR_PHY_DSGCR_OFFSET #define DDR_PHY_DSGCR_OFFSET 0XFD080090 +#undef DDR_PHY_GPR0_OFFSET +#define DDR_PHY_GPR0_OFFSET 0XFD0800C0 #undef DDR_PHY_DCR_OFFSET #define DDR_PHY_DCR_OFFSET 0XFD080100 #undef DDR_PHY_DTPR0_OFFSET @@ -2350,6 +2670,8 @@ #define DDR_PHY_DTCR1_OFFSET 0XFD080204 #undef DDR_PHY_CATR0_OFFSET #define DDR_PHY_CATR0_OFFSET 0XFD080240 +#undef DDR_PHY_DQSDR0_OFFSET +#define DDR_PHY_DQSDR0_OFFSET 0XFD080250 #undef DDR_PHY_BISTLSR_OFFSET #define DDR_PHY_BISTLSR_OFFSET 0XFD080414 #undef DDR_PHY_RIOCR5_OFFSET @@ -2398,10 +2720,6 @@ #define DDR_PHY_DX0GCR5_OFFSET 0XFD080714 #undef DDR_PHY_DX0GCR6_OFFSET #define DDR_PHY_DX0GCR6_OFFSET 0XFD080718 -#undef DDR_PHY_DX0LCDLR2_OFFSET -#define DDR_PHY_DX0LCDLR2_OFFSET 0XFD080788 -#undef DDR_PHY_DX0GTR0_OFFSET -#define DDR_PHY_DX0GTR0_OFFSET 0XFD0807C0 #undef DDR_PHY_DX1GCR0_OFFSET #define DDR_PHY_DX1GCR0_OFFSET 0XFD080800 #undef DDR_PHY_DX1GCR4_OFFSET @@ -2410,10 +2728,6 @@ #define DDR_PHY_DX1GCR5_OFFSET 0XFD080814 #undef DDR_PHY_DX1GCR6_OFFSET #define DDR_PHY_DX1GCR6_OFFSET 0XFD080818 -#undef DDR_PHY_DX1LCDLR2_OFFSET -#define DDR_PHY_DX1LCDLR2_OFFSET 0XFD080888 -#undef DDR_PHY_DX1GTR0_OFFSET -#define DDR_PHY_DX1GTR0_OFFSET 0XFD0808C0 #undef DDR_PHY_DX2GCR0_OFFSET #define DDR_PHY_DX2GCR0_OFFSET 0XFD080900 #undef DDR_PHY_DX2GCR1_OFFSET @@ -2424,10 +2738,6 @@ #define DDR_PHY_DX2GCR5_OFFSET 0XFD080914 #undef DDR_PHY_DX2GCR6_OFFSET #define DDR_PHY_DX2GCR6_OFFSET 0XFD080918 -#undef DDR_PHY_DX2LCDLR2_OFFSET -#define DDR_PHY_DX2LCDLR2_OFFSET 0XFD080988 -#undef DDR_PHY_DX2GTR0_OFFSET -#define DDR_PHY_DX2GTR0_OFFSET 0XFD0809C0 #undef DDR_PHY_DX3GCR0_OFFSET #define DDR_PHY_DX3GCR0_OFFSET 0XFD080A00 #undef DDR_PHY_DX3GCR1_OFFSET @@ -2438,10 +2748,6 @@ #define DDR_PHY_DX3GCR5_OFFSET 0XFD080A14 #undef DDR_PHY_DX3GCR6_OFFSET #define DDR_PHY_DX3GCR6_OFFSET 0XFD080A18 -#undef DDR_PHY_DX3LCDLR2_OFFSET -#define DDR_PHY_DX3LCDLR2_OFFSET 0XFD080A88 -#undef DDR_PHY_DX3GTR0_OFFSET -#define DDR_PHY_DX3GTR0_OFFSET 0XFD080AC0 #undef DDR_PHY_DX4GCR0_OFFSET #define DDR_PHY_DX4GCR0_OFFSET 0XFD080B00 #undef DDR_PHY_DX4GCR1_OFFSET @@ -2452,10 +2758,6 @@ #define DDR_PHY_DX4GCR5_OFFSET 0XFD080B14 #undef DDR_PHY_DX4GCR6_OFFSET #define DDR_PHY_DX4GCR6_OFFSET 0XFD080B18 -#undef DDR_PHY_DX4LCDLR2_OFFSET -#define DDR_PHY_DX4LCDLR2_OFFSET 0XFD080B88 -#undef DDR_PHY_DX4GTR0_OFFSET -#define DDR_PHY_DX4GTR0_OFFSET 0XFD080BC0 #undef DDR_PHY_DX5GCR0_OFFSET #define DDR_PHY_DX5GCR0_OFFSET 0XFD080C00 #undef DDR_PHY_DX5GCR1_OFFSET @@ -2466,10 +2768,6 @@ #define DDR_PHY_DX5GCR5_OFFSET 0XFD080C14 #undef DDR_PHY_DX5GCR6_OFFSET #define DDR_PHY_DX5GCR6_OFFSET 0XFD080C18 -#undef DDR_PHY_DX5LCDLR2_OFFSET -#define DDR_PHY_DX5LCDLR2_OFFSET 0XFD080C88 -#undef DDR_PHY_DX5GTR0_OFFSET -#define DDR_PHY_DX5GTR0_OFFSET 0XFD080CC0 #undef DDR_PHY_DX6GCR0_OFFSET #define DDR_PHY_DX6GCR0_OFFSET 0XFD080D00 #undef DDR_PHY_DX6GCR1_OFFSET @@ -2480,10 +2778,6 @@ #define DDR_PHY_DX6GCR5_OFFSET 0XFD080D14 #undef DDR_PHY_DX6GCR6_OFFSET #define DDR_PHY_DX6GCR6_OFFSET 0XFD080D18 -#undef DDR_PHY_DX6LCDLR2_OFFSET -#define DDR_PHY_DX6LCDLR2_OFFSET 0XFD080D88 -#undef DDR_PHY_DX6GTR0_OFFSET -#define DDR_PHY_DX6GTR0_OFFSET 0XFD080DC0 #undef DDR_PHY_DX7GCR0_OFFSET #define DDR_PHY_DX7GCR0_OFFSET 0XFD080E00 #undef DDR_PHY_DX7GCR1_OFFSET @@ -2494,10 +2788,6 @@ #define DDR_PHY_DX7GCR5_OFFSET 0XFD080E14 #undef DDR_PHY_DX7GCR6_OFFSET #define DDR_PHY_DX7GCR6_OFFSET 0XFD080E18 -#undef DDR_PHY_DX7LCDLR2_OFFSET -#define DDR_PHY_DX7LCDLR2_OFFSET 0XFD080E88 -#undef DDR_PHY_DX7GTR0_OFFSET -#define DDR_PHY_DX7GTR0_OFFSET 0XFD080EC0 #undef DDR_PHY_DX8GCR0_OFFSET #define DDR_PHY_DX8GCR0_OFFSET 0XFD080F00 #undef DDR_PHY_DX8GCR1_OFFSET @@ -2508,12 +2798,10 @@ #define DDR_PHY_DX8GCR5_OFFSET 0XFD080F14 #undef DDR_PHY_DX8GCR6_OFFSET #define DDR_PHY_DX8GCR6_OFFSET 0XFD080F18 -#undef DDR_PHY_DX8LCDLR2_OFFSET -#define DDR_PHY_DX8LCDLR2_OFFSET 0XFD080F88 -#undef DDR_PHY_DX8GTR0_OFFSET -#define DDR_PHY_DX8GTR0_OFFSET 0XFD080FC0 #undef DDR_PHY_DX8SL0OSC_OFFSET #define DDR_PHY_DX8SL0OSC_OFFSET 0XFD081400 +#undef DDR_PHY_DX8SL0PLLCR0_OFFSET +#define DDR_PHY_DX8SL0PLLCR0_OFFSET 0XFD081404 #undef DDR_PHY_DX8SL0DQSCTL_OFFSET #define DDR_PHY_DX8SL0DQSCTL_OFFSET 0XFD08141C #undef DDR_PHY_DX8SL0DXCTL2_OFFSET @@ -2522,6 +2810,8 @@ #define DDR_PHY_DX8SL0IOCR_OFFSET 0XFD081430 #undef DDR_PHY_DX8SL1OSC_OFFSET #define DDR_PHY_DX8SL1OSC_OFFSET 0XFD081440 +#undef DDR_PHY_DX8SL1PLLCR0_OFFSET +#define DDR_PHY_DX8SL1PLLCR0_OFFSET 0XFD081444 #undef DDR_PHY_DX8SL1DQSCTL_OFFSET #define DDR_PHY_DX8SL1DQSCTL_OFFSET 0XFD08145C #undef DDR_PHY_DX8SL1DXCTL2_OFFSET @@ -2530,6 +2820,8 @@ #define DDR_PHY_DX8SL1IOCR_OFFSET 0XFD081470 #undef DDR_PHY_DX8SL2OSC_OFFSET #define DDR_PHY_DX8SL2OSC_OFFSET 0XFD081480 +#undef DDR_PHY_DX8SL2PLLCR0_OFFSET +#define DDR_PHY_DX8SL2PLLCR0_OFFSET 0XFD081484 #undef DDR_PHY_DX8SL2DQSCTL_OFFSET #define DDR_PHY_DX8SL2DQSCTL_OFFSET 0XFD08149C #undef DDR_PHY_DX8SL2DXCTL2_OFFSET @@ -2538,6 +2830,8 @@ #define DDR_PHY_DX8SL2IOCR_OFFSET 0XFD0814B0 #undef DDR_PHY_DX8SL3OSC_OFFSET #define DDR_PHY_DX8SL3OSC_OFFSET 0XFD0814C0 +#undef DDR_PHY_DX8SL3PLLCR0_OFFSET +#define DDR_PHY_DX8SL3PLLCR0_OFFSET 0XFD0814C4 #undef DDR_PHY_DX8SL3DQSCTL_OFFSET #define DDR_PHY_DX8SL3DQSCTL_OFFSET 0XFD0814DC #undef DDR_PHY_DX8SL3DXCTL2_OFFSET @@ -2546,14391 +2840,18570 @@ #define DDR_PHY_DX8SL3IOCR_OFFSET 0XFD0814F0 #undef DDR_PHY_DX8SL4OSC_OFFSET #define DDR_PHY_DX8SL4OSC_OFFSET 0XFD081500 +#undef DDR_PHY_DX8SL4PLLCR0_OFFSET +#define DDR_PHY_DX8SL4PLLCR0_OFFSET 0XFD081504 #undef DDR_PHY_DX8SL4DQSCTL_OFFSET #define DDR_PHY_DX8SL4DQSCTL_OFFSET 0XFD08151C #undef DDR_PHY_DX8SL4DXCTL2_OFFSET #define DDR_PHY_DX8SL4DXCTL2_OFFSET 0XFD08152C #undef DDR_PHY_DX8SL4IOCR_OFFSET #define DDR_PHY_DX8SL4IOCR_OFFSET 0XFD081530 +#undef DDR_PHY_DX8SLBPLLCR0_OFFSET +#define DDR_PHY_DX8SLBPLLCR0_OFFSET 0XFD0817C4 #undef DDR_PHY_DX8SLBDQSCTL_OFFSET #define DDR_PHY_DX8SLBDQSCTL_OFFSET 0XFD0817DC -#undef DDR_PHY_PIR_OFFSET -#define DDR_PHY_PIR_OFFSET 0XFD080004 -/*DDR block level reset inside of the DDR Sub System*/ +/* +* DDR block level reset inside of the DDR Sub System +*/ #undef CRF_APB_RST_DDR_SS_DDR_RESET_DEFVAL #undef CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT #undef CRF_APB_RST_DDR_SS_DDR_RESET_MASK -#define CRF_APB_RST_DDR_SS_DDR_RESET_DEFVAL 0x0000000F -#define CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT 3 -#define CRF_APB_RST_DDR_SS_DDR_RESET_MASK 0x00000008U +#define CRF_APB_RST_DDR_SS_DDR_RESET_DEFVAL 0x0000000F +#define CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT 3 +#define CRF_APB_RST_DDR_SS_DDR_RESET_MASK 0x00000008U -/*Indicates the configuration of the device used in the system. - 00 - x4 device - 01 - x8 device - 10 - x16 device - 11 - x32 - evice*/ +/* +* Indicates the configuration of the device used in the system. - 00 - x4 + * device - 01 - x8 device - 10 - x16 device - 11 - x32 device +*/ #undef DDRC_MSTR_DEVICE_CONFIG_DEFVAL #undef DDRC_MSTR_DEVICE_CONFIG_SHIFT #undef DDRC_MSTR_DEVICE_CONFIG_MASK -#define DDRC_MSTR_DEVICE_CONFIG_DEFVAL 0x03040001 -#define DDRC_MSTR_DEVICE_CONFIG_SHIFT 30 -#define DDRC_MSTR_DEVICE_CONFIG_MASK 0xC0000000U +#define DDRC_MSTR_DEVICE_CONFIG_DEFVAL 0x03040001 +#define DDRC_MSTR_DEVICE_CONFIG_SHIFT 30 +#define DDRC_MSTR_DEVICE_CONFIG_MASK 0xC0000000U -/*Choose which registers are used. - 0 - Original registers - 1 - Shadow registers*/ +/* +* Choose which registers are used. - 0 - Original registers - 1 - Shadow r + * egisters +*/ #undef DDRC_MSTR_FREQUENCY_MODE_DEFVAL #undef DDRC_MSTR_FREQUENCY_MODE_SHIFT #undef DDRC_MSTR_FREQUENCY_MODE_MASK -#define DDRC_MSTR_FREQUENCY_MODE_DEFVAL 0x03040001 -#define DDRC_MSTR_FREQUENCY_MODE_SHIFT 29 -#define DDRC_MSTR_FREQUENCY_MODE_MASK 0x20000000U +#define DDRC_MSTR_FREQUENCY_MODE_DEFVAL 0x03040001 +#define DDRC_MSTR_FREQUENCY_MODE_SHIFT 29 +#define DDRC_MSTR_FREQUENCY_MODE_MASK 0x20000000U -/*Only present for multi-rank configurations. Each bit represents one rank. For two-rank configurations, only bits[25:24] are p - esent. - 1 - populated - 0 - unpopulated LSB is the lowest rank number. For 2 ranks following combinations are legal: - 01 - - ne rank - 11 - Two ranks - Others - Reserved. For 4 ranks following combinations are legal: - 0001 - One rank - 0011 - Two ra - ks - 1111 - Four ranks*/ +/* +* Only present for multi-rank configurations. Each bit represents one rank + * . For two-rank configurations, only bits[25:24] are present. - 1 - popul + * ated - 0 - unpopulated LSB is the lowest rank number. For 2 ranks follow + * ing combinations are legal: - 01 - One rank - 11 - Two ranks - Others - + * Reserved. For 4 ranks following combinations are legal: - 0001 - One ran + * k - 0011 - Two ranks - 1111 - Four ranks +*/ #undef DDRC_MSTR_ACTIVE_RANKS_DEFVAL #undef DDRC_MSTR_ACTIVE_RANKS_SHIFT #undef DDRC_MSTR_ACTIVE_RANKS_MASK -#define DDRC_MSTR_ACTIVE_RANKS_DEFVAL 0x03040001 -#define DDRC_MSTR_ACTIVE_RANKS_SHIFT 24 -#define DDRC_MSTR_ACTIVE_RANKS_MASK 0x03000000U +#define DDRC_MSTR_ACTIVE_RANKS_DEFVAL 0x03040001 +#define DDRC_MSTR_ACTIVE_RANKS_SHIFT 24 +#define DDRC_MSTR_ACTIVE_RANKS_MASK 0x03000000U -/*SDRAM burst length used: - 0001 - Burst length of 2 (only supported for mDDR) - 0010 - Burst length of 4 - 0100 - Burst lengt - of 8 - 1000 - Burst length of 16 (only supported for mDDR, LPDDR2, and LPDDR4) All other values are reserved. This controls - he burst size used to access the SDRAM. This must match the burst length mode register setting in the SDRAM. (For BC4/8 on-th - -fly mode of DDR3 and DDR4, set this field to 0x0100) Burst length of 2 is not supported with AXI ports when MEMC_BURST_LENGT - is 8. Burst length of 2 is only supported with MEMC_FREQ_RATIO = 1*/ +/* +* SDRAM burst length used: - 0001 - Burst length of 2 (only supported for + * mDDR) - 0010 - Burst length of 4 - 0100 - Burst length of 8 - 1000 - Bur + * st length of 16 (only supported for mDDR, LPDDR2, and LPDDR4) All other + * values are reserved. This controls the burst size used to access the SDR + * AM. This must match the burst length mode register setting in the SDRAM. + * (For BC4/8 on-the-fly mode of DDR3 and DDR4, set this field to 0x0100) + * Burst length of 2 is not supported with AXI ports when MEMC_BURST_LENGTH + * is 8. Burst length of 2 is only supported with MEMC_FREQ_RATIO = 1 +*/ #undef DDRC_MSTR_BURST_RDWR_DEFVAL #undef DDRC_MSTR_BURST_RDWR_SHIFT #undef DDRC_MSTR_BURST_RDWR_MASK -#define DDRC_MSTR_BURST_RDWR_DEFVAL 0x03040001 -#define DDRC_MSTR_BURST_RDWR_SHIFT 16 -#define DDRC_MSTR_BURST_RDWR_MASK 0x000F0000U +#define DDRC_MSTR_BURST_RDWR_DEFVAL 0x03040001 +#define DDRC_MSTR_BURST_RDWR_SHIFT 16 +#define DDRC_MSTR_BURST_RDWR_MASK 0x000F0000U -/*Set to 1 when the uMCTL2 and DRAM has to be put in DLL-off mode for low frequency operation. Set to 0 to put uMCTL2 and DRAM - n DLL-on mode for normal frequency operation. If DDR4 CRC/parity retry is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), d - l_off_mode is not supported, and this bit must be set to '0'.*/ +/* +* Set to 1 when the uMCTL2 and DRAM has to be put in DLL-off mode for low + * frequency operation. Set to 0 to put uMCTL2 and DRAM in DLL-on mode for + * normal frequency operation. If DDR4 CRC/parity retry is enabled (CRCPARC + * TL1.crc_parity_retry_enable = 1), dll_off_mode is not supported, and thi + * s bit must be set to '0'. +*/ #undef DDRC_MSTR_DLL_OFF_MODE_DEFVAL #undef DDRC_MSTR_DLL_OFF_MODE_SHIFT #undef DDRC_MSTR_DLL_OFF_MODE_MASK -#define DDRC_MSTR_DLL_OFF_MODE_DEFVAL 0x03040001 -#define DDRC_MSTR_DLL_OFF_MODE_SHIFT 15 -#define DDRC_MSTR_DLL_OFF_MODE_MASK 0x00008000U +#define DDRC_MSTR_DLL_OFF_MODE_DEFVAL 0x03040001 +#define DDRC_MSTR_DLL_OFF_MODE_SHIFT 15 +#define DDRC_MSTR_DLL_OFF_MODE_MASK 0x00008000U -/*Selects proportion of DQ bus width that is used by the SDRAM - 00 - Full DQ bus width to SDRAM - 01 - Half DQ bus width to SD - AM - 10 - Quarter DQ bus width to SDRAM - 11 - Reserved. Note that half bus width mode is only supported when the SDRAM bus w - dth is a multiple of 16, and quarter bus width mode is only supported when the SDRAM bus width is a multiple of 32 and the co - figuration parameter MEMC_QBUS_SUPPORT is set. Bus width refers to DQ bus width (excluding any ECC width).*/ +/* +* Selects proportion of DQ bus width that is used by the SDRAM - 00 - Full + * DQ bus width to SDRAM - 01 - Half DQ bus width to SDRAM - 10 - Quarter + * DQ bus width to SDRAM - 11 - Reserved. Note that half bus width mode is + * only supported when the SDRAM bus width is a multiple of 16, and quarter + * bus width mode is only supported when the SDRAM bus width is a multiple + * of 32 and the configuration parameter MEMC_QBUS_SUPPORT is set. Bus wid + * th refers to DQ bus width (excluding any ECC width). +*/ #undef DDRC_MSTR_DATA_BUS_WIDTH_DEFVAL #undef DDRC_MSTR_DATA_BUS_WIDTH_SHIFT #undef DDRC_MSTR_DATA_BUS_WIDTH_MASK -#define DDRC_MSTR_DATA_BUS_WIDTH_DEFVAL 0x03040001 -#define DDRC_MSTR_DATA_BUS_WIDTH_SHIFT 12 -#define DDRC_MSTR_DATA_BUS_WIDTH_MASK 0x00003000U +#define DDRC_MSTR_DATA_BUS_WIDTH_DEFVAL 0x03040001 +#define DDRC_MSTR_DATA_BUS_WIDTH_SHIFT 12 +#define DDRC_MSTR_DATA_BUS_WIDTH_MASK 0x00003000U -/*1 indicates put the DRAM in geardown mode (2N) and 0 indicates put the DRAM in normal mode (1N). This register can be changed - only when the Controller is in self-refresh mode. This signal must be set the same value as MR3 bit A3. Note: Geardown mode - s not supported if the configuration parameter MEMC_CMD_RTN2IDLE is set*/ +/* +* 1 indicates put the DRAM in geardown mode (2N) and 0 indicates put the D + * RAM in normal mode (1N). This register can be changed, only when the Con + * troller is in self-refresh mode. This signal must be set the same value + * as MR3 bit A3. Note: Geardown mode is not supported if the configuration + * parameter MEMC_CMD_RTN2IDLE is set +*/ #undef DDRC_MSTR_GEARDOWN_MODE_DEFVAL #undef DDRC_MSTR_GEARDOWN_MODE_SHIFT #undef DDRC_MSTR_GEARDOWN_MODE_MASK -#define DDRC_MSTR_GEARDOWN_MODE_DEFVAL 0x03040001 -#define DDRC_MSTR_GEARDOWN_MODE_SHIFT 11 -#define DDRC_MSTR_GEARDOWN_MODE_MASK 0x00000800U +#define DDRC_MSTR_GEARDOWN_MODE_DEFVAL 0x03040001 +#define DDRC_MSTR_GEARDOWN_MODE_SHIFT 11 +#define DDRC_MSTR_GEARDOWN_MODE_MASK 0x00000800U -/*If 1, then uMCTL2 uses 2T timing. Otherwise, uses 1T timing. In 2T timing, all command signals (except chip select) are held - or 2 clocks on the SDRAM bus. Chip select is asserted on the second cycle of the command Note: 2T timing is not supported in - PDDR2/LPDDR3/LPDDR4 mode Note: 2T timing is not supported if the configuration parameter MEMC_CMD_RTN2IDLE is set Note: 2T ti - ing is not supported in DDR4 geardown mode.*/ +/* +* If 1, then uMCTL2 uses 2T timing. Otherwise, uses 1T timing. In 2T timin + * g, all command signals (except chip select) are held for 2 clocks on the + * SDRAM bus. Chip select is asserted on the second cycle of the command N + * ote: 2T timing is not supported in LPDDR2/LPDDR3/LPDDR4 mode Note: 2T ti + * ming is not supported if the configuration parameter MEMC_CMD_RTN2IDLE i + * s set Note: 2T timing is not supported in DDR4 geardown mode. +*/ #undef DDRC_MSTR_EN_2T_TIMING_MODE_DEFVAL #undef DDRC_MSTR_EN_2T_TIMING_MODE_SHIFT #undef DDRC_MSTR_EN_2T_TIMING_MODE_MASK -#define DDRC_MSTR_EN_2T_TIMING_MODE_DEFVAL 0x03040001 -#define DDRC_MSTR_EN_2T_TIMING_MODE_SHIFT 10 -#define DDRC_MSTR_EN_2T_TIMING_MODE_MASK 0x00000400U +#define DDRC_MSTR_EN_2T_TIMING_MODE_DEFVAL 0x03040001 +#define DDRC_MSTR_EN_2T_TIMING_MODE_SHIFT 10 +#define DDRC_MSTR_EN_2T_TIMING_MODE_MASK 0x00000400U -/*When set, enable burst-chop in DDR3/DDR4. Burst Chop for Reads is exercised only in HIF configurations (UMCTL2_INCL_ARB not s - t) and if in full bus width mode (MSTR.data_bus_width = 00). Burst Chop for Writes is exercised only if Partial Writes enable - (UMCTL2_PARTIAL_WR=1) and if CRC is disabled (CRCPARCTL1.crc_enable = 0). If DDR4 CRC/parity retry is enabled (CRCPARCTL1.cr - _parity_retry_enable = 1), burst chop is not supported, and this bit must be set to '0'*/ +/* +* When set, enable burst-chop in DDR3/DDR4. Burst Chop for Reads is exerci + * sed only in HIF configurations (UMCTL2_INCL_ARB not set) and if in full + * bus width mode (MSTR.data_bus_width = 00). Burst Chop for Writes is exer + * cised only if Partial Writes enabled (UMCTL2_PARTIAL_WR=1) and if CRC is + * disabled (CRCPARCTL1.crc_enable = 0). If DDR4 CRC/parity retry is enabl + * ed (CRCPARCTL1.crc_parity_retry_enable = 1), burst chop is not supported + * , and this bit must be set to '0' +*/ #undef DDRC_MSTR_BURSTCHOP_DEFVAL #undef DDRC_MSTR_BURSTCHOP_SHIFT #undef DDRC_MSTR_BURSTCHOP_MASK -#define DDRC_MSTR_BURSTCHOP_DEFVAL 0x03040001 -#define DDRC_MSTR_BURSTCHOP_SHIFT 9 -#define DDRC_MSTR_BURSTCHOP_MASK 0x00000200U +#define DDRC_MSTR_BURSTCHOP_DEFVAL 0x03040001 +#define DDRC_MSTR_BURSTCHOP_SHIFT 9 +#define DDRC_MSTR_BURSTCHOP_MASK 0x00000200U -/*Select LPDDR4 SDRAM - 1 - LPDDR4 SDRAM device in use. - 0 - non-LPDDR4 device in use Present only in designs configured to su - port LPDDR4.*/ +/* +* Select LPDDR4 SDRAM - 1 - LPDDR4 SDRAM device in use. - 0 - non-LPDDR4 d + * evice in use Present only in designs configured to support LPDDR4. +*/ #undef DDRC_MSTR_LPDDR4_DEFVAL #undef DDRC_MSTR_LPDDR4_SHIFT #undef DDRC_MSTR_LPDDR4_MASK -#define DDRC_MSTR_LPDDR4_DEFVAL 0x03040001 -#define DDRC_MSTR_LPDDR4_SHIFT 5 -#define DDRC_MSTR_LPDDR4_MASK 0x00000020U +#define DDRC_MSTR_LPDDR4_DEFVAL 0x03040001 +#define DDRC_MSTR_LPDDR4_SHIFT 5 +#define DDRC_MSTR_LPDDR4_MASK 0x00000020U -/*Select DDR4 SDRAM - 1 - DDR4 SDRAM device in use. - 0 - non-DDR4 device in use Present only in designs configured to support - DR4.*/ +/* +* Select DDR4 SDRAM - 1 - DDR4 SDRAM device in use. - 0 - non-DDR4 device + * in use Present only in designs configured to support DDR4. +*/ #undef DDRC_MSTR_DDR4_DEFVAL #undef DDRC_MSTR_DDR4_SHIFT #undef DDRC_MSTR_DDR4_MASK -#define DDRC_MSTR_DDR4_DEFVAL 0x03040001 -#define DDRC_MSTR_DDR4_SHIFT 4 -#define DDRC_MSTR_DDR4_MASK 0x00000010U +#define DDRC_MSTR_DDR4_DEFVAL 0x03040001 +#define DDRC_MSTR_DDR4_SHIFT 4 +#define DDRC_MSTR_DDR4_MASK 0x00000010U -/*Select LPDDR3 SDRAM - 1 - LPDDR3 SDRAM device in use. - 0 - non-LPDDR3 device in use Present only in designs configured to su - port LPDDR3.*/ +/* +* Select LPDDR3 SDRAM - 1 - LPDDR3 SDRAM device in use. - 0 - non-LPDDR3 d + * evice in use Present only in designs configured to support LPDDR3. +*/ #undef DDRC_MSTR_LPDDR3_DEFVAL #undef DDRC_MSTR_LPDDR3_SHIFT #undef DDRC_MSTR_LPDDR3_MASK -#define DDRC_MSTR_LPDDR3_DEFVAL 0x03040001 -#define DDRC_MSTR_LPDDR3_SHIFT 3 -#define DDRC_MSTR_LPDDR3_MASK 0x00000008U +#define DDRC_MSTR_LPDDR3_DEFVAL 0x03040001 +#define DDRC_MSTR_LPDDR3_SHIFT 3 +#define DDRC_MSTR_LPDDR3_MASK 0x00000008U -/*Select LPDDR2 SDRAM - 1 - LPDDR2 SDRAM device in use. - 0 - non-LPDDR2 device in use Present only in designs configured to su - port LPDDR2.*/ +/* +* Select LPDDR2 SDRAM - 1 - LPDDR2 SDRAM device in use. - 0 - non-LPDDR2 d + * evice in use Present only in designs configured to support LPDDR2. +*/ #undef DDRC_MSTR_LPDDR2_DEFVAL #undef DDRC_MSTR_LPDDR2_SHIFT #undef DDRC_MSTR_LPDDR2_MASK -#define DDRC_MSTR_LPDDR2_DEFVAL 0x03040001 -#define DDRC_MSTR_LPDDR2_SHIFT 2 -#define DDRC_MSTR_LPDDR2_MASK 0x00000004U +#define DDRC_MSTR_LPDDR2_DEFVAL 0x03040001 +#define DDRC_MSTR_LPDDR2_SHIFT 2 +#define DDRC_MSTR_LPDDR2_MASK 0x00000004U -/*Select DDR3 SDRAM - 1 - DDR3 SDRAM device in use - 0 - non-DDR3 SDRAM device in use Only present in designs that support DDR3 - */ +/* +* Select DDR3 SDRAM - 1 - DDR3 SDRAM device in use - 0 - non-DDR3 SDRAM de + * vice in use Only present in designs that support DDR3. +*/ #undef DDRC_MSTR_DDR3_DEFVAL #undef DDRC_MSTR_DDR3_SHIFT #undef DDRC_MSTR_DDR3_MASK -#define DDRC_MSTR_DDR3_DEFVAL 0x03040001 -#define DDRC_MSTR_DDR3_SHIFT 0 -#define DDRC_MSTR_DDR3_MASK 0x00000001U +#define DDRC_MSTR_DDR3_DEFVAL 0x03040001 +#define DDRC_MSTR_DDR3_SHIFT 0 +#define DDRC_MSTR_DDR3_MASK 0x00000001U -/*Setting this register bit to 1 triggers a mode register read or write operation. When the MR operation is complete, the uMCTL - automatically clears this bit. The other register fields of this register must be written in a separate APB transaction, bef - re setting this mr_wr bit. It is recommended NOT to set this signal if in Init, Deep power-down or MPSM operating modes.*/ +/* +* Setting this register bit to 1 triggers a mode register read or write op + * eration. When the MR operation is complete, the uMCTL2 automatically cle + * ars this bit. The other register fields of this register must be written + * in a separate APB transaction, before setting this mr_wr bit. It is rec + * ommended NOT to set this signal if in Init, Deep power-down or MPSM oper + * ating modes. +*/ #undef DDRC_MRCTRL0_MR_WR_DEFVAL #undef DDRC_MRCTRL0_MR_WR_SHIFT #undef DDRC_MRCTRL0_MR_WR_MASK -#define DDRC_MRCTRL0_MR_WR_DEFVAL 0x00000030 -#define DDRC_MRCTRL0_MR_WR_SHIFT 31 -#define DDRC_MRCTRL0_MR_WR_MASK 0x80000000U +#define DDRC_MRCTRL0_MR_WR_DEFVAL 0x00000030 +#define DDRC_MRCTRL0_MR_WR_SHIFT 31 +#define DDRC_MRCTRL0_MR_WR_MASK 0x80000000U -/*Address of the mode register that is to be written to. - 0000 - MR0 - 0001 - MR1 - 0010 - MR2 - 0011 - MR3 - 0100 - MR4 - 010 - - MR5 - 0110 - MR6 - 0111 - MR7 Don't Care for LPDDR2/LPDDR3/LPDDR4 (see MRCTRL1.mr_data for mode register addressing in LPD - R2/LPDDR3/LPDDR4) This signal is also used for writing to control words of RDIMMs. In that case, it corresponds to the bank a - dress bits sent to the RDIMM In case of DDR4, the bit[3:2] corresponds to the bank group bits. Therefore, the bit[3] as well - s the bit[2:0] must be set to an appropriate value which is considered both the Address Mirroring of UDIMMs/RDIMMs and the Ou - put Inversion of RDIMMs.*/ +/* +* Address of the mode register that is to be written to. - 0000 - MR0 - 00 + * 01 - MR1 - 0010 - MR2 - 0011 - MR3 - 0100 - MR4 - 0101 - MR5 - 0110 - MR + * 6 - 0111 - MR7 Don't Care for LPDDR2/LPDDR3/LPDDR4 (see MRCTRL1.mr_data + * for mode register addressing in LPDDR2/LPDDR3/LPDDR4) This signal is als + * o used for writing to control words of RDIMMs. In that case, it correspo + * nds to the bank address bits sent to the RDIMM In case of DDR4, the bit[ + * 3:2] corresponds to the bank group bits. Therefore, the bit[3] as well a + * s the bit[2:0] must be set to an appropriate value which is considered b + * oth the Address Mirroring of UDIMMs/RDIMMs and the Output Inversion of R + * DIMMs. +*/ #undef DDRC_MRCTRL0_MR_ADDR_DEFVAL #undef DDRC_MRCTRL0_MR_ADDR_SHIFT #undef DDRC_MRCTRL0_MR_ADDR_MASK -#define DDRC_MRCTRL0_MR_ADDR_DEFVAL 0x00000030 -#define DDRC_MRCTRL0_MR_ADDR_SHIFT 12 -#define DDRC_MRCTRL0_MR_ADDR_MASK 0x0000F000U +#define DDRC_MRCTRL0_MR_ADDR_DEFVAL 0x00000030 +#define DDRC_MRCTRL0_MR_ADDR_SHIFT 12 +#define DDRC_MRCTRL0_MR_ADDR_MASK 0x0000F000U -/*Controls which rank is accessed by MRCTRL0.mr_wr. Normally, it is desired to access all ranks, so all bits should be set to 1 - However, for multi-rank UDIMMs/RDIMMs which implement address mirroring, it may be necessary to access ranks individually. E - amples (assume uMCTL2 is configured for 4 ranks): - 0x1 - select rank 0 only - 0x2 - select rank 1 only - 0x5 - select ranks - and 2 - 0xA - select ranks 1 and 3 - 0xF - select ranks 0, 1, 2 and 3*/ +/* +* Controls which rank is accessed by MRCTRL0.mr_wr. Normally, it is desire + * d to access all ranks, so all bits should be set to 1. However, for mult + * i-rank UDIMMs/RDIMMs which implement address mirroring, it may be necess + * ary to access ranks individually. Examples (assume uMCTL2 is configured + * for 4 ranks): - 0x1 - select rank 0 only - 0x2 - select rank 1 only - 0x + * 5 - select ranks 0 and 2 - 0xA - select ranks 1 and 3 - 0xF - select ran + * ks 0, 1, 2 and 3 +*/ #undef DDRC_MRCTRL0_MR_RANK_DEFVAL #undef DDRC_MRCTRL0_MR_RANK_SHIFT #undef DDRC_MRCTRL0_MR_RANK_MASK -#define DDRC_MRCTRL0_MR_RANK_DEFVAL 0x00000030 -#define DDRC_MRCTRL0_MR_RANK_SHIFT 4 -#define DDRC_MRCTRL0_MR_RANK_MASK 0x00000030U +#define DDRC_MRCTRL0_MR_RANK_DEFVAL 0x00000030 +#define DDRC_MRCTRL0_MR_RANK_SHIFT 4 +#define DDRC_MRCTRL0_MR_RANK_MASK 0x00000030U -/*Indicates whether Software intervention is allowed via MRCTRL0/MRCTRL1 before automatic SDRAM initialization routine or not. - or DDR4, this bit can be used to initialize the DDR4 RCD (MR7) before automatic SDRAM initialization. For LPDDR4, this bit ca - be used to program additional mode registers before automatic SDRAM initialization if necessary. Note: This must be cleared - o 0 after completing Software operation. Otherwise, SDRAM initialization routine will not re-start. - 0 - Software interventi - n is not allowed - 1 - Software intervention is allowed*/ +/* +* Indicates whether Software intervention is allowed via MRCTRL0/MRCTRL1 b + * efore automatic SDRAM initialization routine or not. For DDR4, this bit + * can be used to initialize the DDR4 RCD (MR7) before automatic SDRAM init + * ialization. For LPDDR4, this bit can be used to program additional mode + * registers before automatic SDRAM initialization if necessary. Note: This + * must be cleared to 0 after completing Software operation. Otherwise, SD + * RAM initialization routine will not re-start. - 0 - Software interventio + * n is not allowed - 1 - Software intervention is allowed +*/ #undef DDRC_MRCTRL0_SW_INIT_INT_DEFVAL #undef DDRC_MRCTRL0_SW_INIT_INT_SHIFT #undef DDRC_MRCTRL0_SW_INIT_INT_MASK -#define DDRC_MRCTRL0_SW_INIT_INT_DEFVAL 0x00000030 -#define DDRC_MRCTRL0_SW_INIT_INT_SHIFT 3 -#define DDRC_MRCTRL0_SW_INIT_INT_MASK 0x00000008U +#define DDRC_MRCTRL0_SW_INIT_INT_DEFVAL 0x00000030 +#define DDRC_MRCTRL0_SW_INIT_INT_SHIFT 3 +#define DDRC_MRCTRL0_SW_INIT_INT_MASK 0x00000008U -/*Indicates whether the mode register operation is MRS in PDA mode or not - 0 - MRS - 1 - MRS in Per DRAM Addressability mode*/ +/* +* Indicates whether the mode register operation is MRS in PDA mode or not + * - 0 - MRS - 1 - MRS in Per DRAM Addressability mode +*/ #undef DDRC_MRCTRL0_PDA_EN_DEFVAL #undef DDRC_MRCTRL0_PDA_EN_SHIFT #undef DDRC_MRCTRL0_PDA_EN_MASK -#define DDRC_MRCTRL0_PDA_EN_DEFVAL 0x00000030 -#define DDRC_MRCTRL0_PDA_EN_SHIFT 2 -#define DDRC_MRCTRL0_PDA_EN_MASK 0x00000004U +#define DDRC_MRCTRL0_PDA_EN_DEFVAL 0x00000030 +#define DDRC_MRCTRL0_PDA_EN_SHIFT 2 +#define DDRC_MRCTRL0_PDA_EN_MASK 0x00000004U -/*Indicates whether the mode register operation is MRS or WR/RD for MPR (only supported for DDR4) - 0 - MRS - 1 - WR/RD for MPR*/ +/* +* Indicates whether the mode register operation is MRS or WR/RD for MPR (o + * nly supported for DDR4) - 0 - MRS - 1 - WR/RD for MPR +*/ #undef DDRC_MRCTRL0_MPR_EN_DEFVAL #undef DDRC_MRCTRL0_MPR_EN_SHIFT #undef DDRC_MRCTRL0_MPR_EN_MASK -#define DDRC_MRCTRL0_MPR_EN_DEFVAL 0x00000030 -#define DDRC_MRCTRL0_MPR_EN_SHIFT 1 -#define DDRC_MRCTRL0_MPR_EN_MASK 0x00000002U +#define DDRC_MRCTRL0_MPR_EN_DEFVAL 0x00000030 +#define DDRC_MRCTRL0_MPR_EN_SHIFT 1 +#define DDRC_MRCTRL0_MPR_EN_MASK 0x00000002U -/*Indicates whether the mode register operation is read or write. Only used for LPDDR2/LPDDR3/LPDDR4/DDR4. - 0 - Write - 1 - Re - d*/ +/* +* Indicates whether the mode register operation is read or write. Only use + * d for LPDDR2/LPDDR3/LPDDR4/DDR4. - 0 - Write - 1 - Read +*/ #undef DDRC_MRCTRL0_MR_TYPE_DEFVAL #undef DDRC_MRCTRL0_MR_TYPE_SHIFT #undef DDRC_MRCTRL0_MR_TYPE_MASK -#define DDRC_MRCTRL0_MR_TYPE_DEFVAL 0x00000030 -#define DDRC_MRCTRL0_MR_TYPE_SHIFT 0 -#define DDRC_MRCTRL0_MR_TYPE_MASK 0x00000001U +#define DDRC_MRCTRL0_MR_TYPE_DEFVAL 0x00000030 +#define DDRC_MRCTRL0_MR_TYPE_SHIFT 0 +#define DDRC_MRCTRL0_MR_TYPE_MASK 0x00000001U -/*Derate value of tRC for LPDDR4 - 0 - Derating uses +1. - 1 - Derating uses +2. - 2 - Derating uses +3. - 3 - Derating uses +4 - Present only in designs configured to support LPDDR4. The required number of cycles for derating can be determined by dividi - g 3.75ns by the core_ddrc_core_clk period, and rounding up the next integer.*/ +/* +* Derate value of tRC for LPDDR4 - 0 - Derating uses +1. - 1 - Derating us + * es +2. - 2 - Derating uses +3. - 3 - Derating uses +4. Present only in d + * esigns configured to support LPDDR4. The required number of cycles for d + * erating can be determined by dividing 3.75ns by the core_ddrc_core_clk p + * eriod, and rounding up the next integer. +*/ #undef DDRC_DERATEEN_RC_DERATE_VALUE_DEFVAL #undef DDRC_DERATEEN_RC_DERATE_VALUE_SHIFT #undef DDRC_DERATEEN_RC_DERATE_VALUE_MASK -#define DDRC_DERATEEN_RC_DERATE_VALUE_DEFVAL 0x00000000 -#define DDRC_DERATEEN_RC_DERATE_VALUE_SHIFT 8 -#define DDRC_DERATEEN_RC_DERATE_VALUE_MASK 0x00000300U +#define DDRC_DERATEEN_RC_DERATE_VALUE_DEFVAL 0x00000000 +#define DDRC_DERATEEN_RC_DERATE_VALUE_SHIFT 8 +#define DDRC_DERATEEN_RC_DERATE_VALUE_MASK 0x00000300U -/*Derate byte Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4 Indicates which byte of the MRR data is used f - r derating. The maximum valid value depends on MEMC_DRAM_TOTAL_DATA_WIDTH.*/ +/* +* Derate byte Present only in designs configured to support LPDDR2/LPDDR3/ + * LPDDR4 Indicates which byte of the MRR data is used for derating. The ma + * ximum valid value depends on MEMC_DRAM_TOTAL_DATA_WIDTH. +*/ #undef DDRC_DERATEEN_DERATE_BYTE_DEFVAL #undef DDRC_DERATEEN_DERATE_BYTE_SHIFT #undef DDRC_DERATEEN_DERATE_BYTE_MASK -#define DDRC_DERATEEN_DERATE_BYTE_DEFVAL 0x00000000 -#define DDRC_DERATEEN_DERATE_BYTE_SHIFT 4 -#define DDRC_DERATEEN_DERATE_BYTE_MASK 0x000000F0U +#define DDRC_DERATEEN_DERATE_BYTE_DEFVAL 0x00000000 +#define DDRC_DERATEEN_DERATE_BYTE_SHIFT 4 +#define DDRC_DERATEEN_DERATE_BYTE_MASK 0x000000F0U -/*Derate value - 0 - Derating uses +1. - 1 - Derating uses +2. Present only in designs configured to support LPDDR2/LPDDR3/LPDD - 4 Set to 0 for all LPDDR2 speed grades as derating value of +1.875 ns is less than a core_ddrc_core_clk period. Can be 0 or 1 - for LPDDR3/LPDDR4, depending if +1.875 ns is less than a core_ddrc_core_clk period or not.*/ +/* +* Derate value - 0 - Derating uses +1. - 1 - Derating uses +2. Present onl + * y in designs configured to support LPDDR2/LPDDR3/LPDDR4 Set to 0 for all + * LPDDR2 speed grades as derating value of +1.875 ns is less than a core_ + * ddrc_core_clk period. Can be 0 or 1 for LPDDR3/LPDDR4, depending if +1.8 + * 75 ns is less than a core_ddrc_core_clk period or not. +*/ #undef DDRC_DERATEEN_DERATE_VALUE_DEFVAL #undef DDRC_DERATEEN_DERATE_VALUE_SHIFT #undef DDRC_DERATEEN_DERATE_VALUE_MASK -#define DDRC_DERATEEN_DERATE_VALUE_DEFVAL 0x00000000 -#define DDRC_DERATEEN_DERATE_VALUE_SHIFT 1 -#define DDRC_DERATEEN_DERATE_VALUE_MASK 0x00000002U +#define DDRC_DERATEEN_DERATE_VALUE_DEFVAL 0x00000000 +#define DDRC_DERATEEN_DERATE_VALUE_SHIFT 1 +#define DDRC_DERATEEN_DERATE_VALUE_MASK 0x00000002U -/*Enables derating - 0 - Timing parameter derating is disabled - 1 - Timing parameter derating is enabled using MR4 read value. - Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4 This field must be set to '0' for non-LPDDR2/LPDDR3/LPDDR4 - mode.*/ +/* +* Enables derating - 0 - Timing parameter derating is disabled - 1 - Timin + * g parameter derating is enabled using MR4 read value. Present only in de + * signs configured to support LPDDR2/LPDDR3/LPDDR4 This field must be set + * to '0' for non-LPDDR2/LPDDR3/LPDDR4 mode. +*/ #undef DDRC_DERATEEN_DERATE_ENABLE_DEFVAL #undef DDRC_DERATEEN_DERATE_ENABLE_SHIFT #undef DDRC_DERATEEN_DERATE_ENABLE_MASK -#define DDRC_DERATEEN_DERATE_ENABLE_DEFVAL 0x00000000 -#define DDRC_DERATEEN_DERATE_ENABLE_SHIFT 0 -#define DDRC_DERATEEN_DERATE_ENABLE_MASK 0x00000001U +#define DDRC_DERATEEN_DERATE_ENABLE_DEFVAL 0x00000000 +#define DDRC_DERATEEN_DERATE_ENABLE_SHIFT 0 +#define DDRC_DERATEEN_DERATE_ENABLE_MASK 0x00000001U -/*Interval between two MR4 reads, used to derate the timing parameters. Present only in designs configured to support LPDDR2/LP - DR3/LPDDR4. This register must not be set to zero*/ +/* +* Interval between two MR4 reads, used to derate the timing parameters. Pr + * esent only in designs configured to support LPDDR2/LPDDR3/LPDDR4. This r + * egister must not be set to zero +*/ #undef DDRC_DERATEINT_MR4_READ_INTERVAL_DEFVAL #undef DDRC_DERATEINT_MR4_READ_INTERVAL_SHIFT #undef DDRC_DERATEINT_MR4_READ_INTERVAL_MASK -#define DDRC_DERATEINT_MR4_READ_INTERVAL_DEFVAL -#define DDRC_DERATEINT_MR4_READ_INTERVAL_SHIFT 0 -#define DDRC_DERATEINT_MR4_READ_INTERVAL_MASK 0xFFFFFFFFU +#define DDRC_DERATEINT_MR4_READ_INTERVAL_DEFVAL +#define DDRC_DERATEINT_MR4_READ_INTERVAL_SHIFT 0 +#define DDRC_DERATEINT_MR4_READ_INTERVAL_MASK 0xFFFFFFFFU -/*Self refresh state is an intermediate state to enter to Self refresh power down state or exit Self refresh power down state f - r LPDDR4. This register controls transition from the Self refresh state. - 1 - Prohibit transition from Self refresh state - - - Allow transition from Self refresh state*/ +/* +* Self refresh state is an intermediate state to enter to Self refresh pow + * er down state or exit Self refresh power down state for LPDDR4. This reg + * ister controls transition from the Self refresh state. - 1 - Prohibit tr + * ansition from Self refresh state - 0 - Allow transition from Self refres + * h state +*/ #undef DDRC_PWRCTL_STAY_IN_SELFREF_DEFVAL #undef DDRC_PWRCTL_STAY_IN_SELFREF_SHIFT #undef DDRC_PWRCTL_STAY_IN_SELFREF_MASK -#define DDRC_PWRCTL_STAY_IN_SELFREF_DEFVAL 0x00000000 -#define DDRC_PWRCTL_STAY_IN_SELFREF_SHIFT 6 -#define DDRC_PWRCTL_STAY_IN_SELFREF_MASK 0x00000040U +#define DDRC_PWRCTL_STAY_IN_SELFREF_DEFVAL 0x00000000 +#define DDRC_PWRCTL_STAY_IN_SELFREF_SHIFT 6 +#define DDRC_PWRCTL_STAY_IN_SELFREF_MASK 0x00000040U -/*A value of 1 to this register causes system to move to Self Refresh state immediately, as long as it is not in INIT or DPD/MP - M operating_mode. This is referred to as Software Entry/Exit to Self Refresh. - 1 - Software Entry to Self Refresh - 0 - Soft - are Exit from Self Refresh*/ +/* +* A value of 1 to this register causes system to move to Self Refresh stat + * e immediately, as long as it is not in INIT or DPD/MPSM operating_mode. + * This is referred to as Software Entry/Exit to Self Refresh. - 1 - Softwa + * re Entry to Self Refresh - 0 - Software Exit from Self Refresh +*/ #undef DDRC_PWRCTL_SELFREF_SW_DEFVAL #undef DDRC_PWRCTL_SELFREF_SW_SHIFT #undef DDRC_PWRCTL_SELFREF_SW_MASK -#define DDRC_PWRCTL_SELFREF_SW_DEFVAL 0x00000000 -#define DDRC_PWRCTL_SELFREF_SW_SHIFT 5 -#define DDRC_PWRCTL_SELFREF_SW_MASK 0x00000020U +#define DDRC_PWRCTL_SELFREF_SW_DEFVAL 0x00000000 +#define DDRC_PWRCTL_SELFREF_SW_SHIFT 5 +#define DDRC_PWRCTL_SELFREF_SW_MASK 0x00000020U -/*When this is 1, the uMCTL2 puts the SDRAM into maximum power saving mode when the transaction store is empty. This register m - st be reset to '0' to bring uMCTL2 out of maximum power saving mode. Present only in designs configured to support DDR4. For - on-DDR4, this register should not be set to 1. Note that MPSM is not supported when using a DWC DDR PHY, if the PHY parameter - DWC_AC_CS_USE is disabled, as the MPSM exit sequence requires the chip-select signal to toggle. FOR PERFORMANCE ONLY.*/ +/* +* When this is 1, the uMCTL2 puts the SDRAM into maximum power saving mode + * when the transaction store is empty. This register must be reset to '0' + * to bring uMCTL2 out of maximum power saving mode. Present only in desig + * ns configured to support DDR4. For non-DDR4, this register should not be + * set to 1. Note that MPSM is not supported when using a DWC DDR PHY, if + * the PHY parameter DWC_AC_CS_USE is disabled, as the MPSM exit sequence r + * equires the chip-select signal to toggle. FOR PERFORMANCE ONLY. +*/ #undef DDRC_PWRCTL_MPSM_EN_DEFVAL #undef DDRC_PWRCTL_MPSM_EN_SHIFT #undef DDRC_PWRCTL_MPSM_EN_MASK -#define DDRC_PWRCTL_MPSM_EN_DEFVAL 0x00000000 -#define DDRC_PWRCTL_MPSM_EN_SHIFT 4 -#define DDRC_PWRCTL_MPSM_EN_MASK 0x00000010U +#define DDRC_PWRCTL_MPSM_EN_DEFVAL 0x00000000 +#define DDRC_PWRCTL_MPSM_EN_SHIFT 4 +#define DDRC_PWRCTL_MPSM_EN_MASK 0x00000010U -/*Enable the assertion of dfi_dram_clk_disable whenever a clock is not required by the SDRAM. If set to 0, dfi_dram_clk_disable - is never asserted. Assertion of dfi_dram_clk_disable is as follows: In DDR2/DDR3, can only be asserted in Self Refresh. In DD - 4, can be asserted in following: - in Self Refresh. - in Maximum Power Saving Mode In mDDR/LPDDR2/LPDDR3, can be asserted in - ollowing: - in Self Refresh - in Power Down - in Deep Power Down - during Normal operation (Clock Stop) In LPDDR4, can be ass - rted in following: - in Self Refresh Power Down - in Power Down - during Normal operation (Clock Stop)*/ +/* +* Enable the assertion of dfi_dram_clk_disable whenever a clock is not req + * uired by the SDRAM. If set to 0, dfi_dram_clk_disable is never asserted. + * Assertion of dfi_dram_clk_disable is as follows: In DDR2/DDR3, can only + * be asserted in Self Refresh. In DDR4, can be asserted in following: - i + * n Self Refresh. - in Maximum Power Saving Mode In mDDR/LPDDR2/LPDDR3, ca + * n be asserted in following: - in Self Refresh - in Power Down - in Deep + * Power Down - during Normal operation (Clock Stop) In LPDDR4, can be asse + * rted in following: - in Self Refresh Power Down - in Power Down - during + * Normal operation (Clock Stop) +*/ #undef DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_DEFVAL #undef DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_SHIFT #undef DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_MASK -#define DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_DEFVAL 0x00000000 -#define DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_SHIFT 3 -#define DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_MASK 0x00000008U +#define DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_DEFVAL 0x00000000 +#define DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_SHIFT 3 +#define DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_MASK 0x00000008U -/*When this is 1, uMCTL2 puts the SDRAM into deep power-down mode when the transaction store is empty. This register must be re - et to '0' to bring uMCTL2 out of deep power-down mode. Controller performs automatic SDRAM initialization on deep power-down - xit. Present only in designs configured to support mDDR or LPDDR2 or LPDDR3. For non-mDDR/non-LPDDR2/non-LPDDR3, this registe - should not be set to 1. FOR PERFORMANCE ONLY.*/ +/* +* When this is 1, uMCTL2 puts the SDRAM into deep power-down mode when the + * transaction store is empty. This register must be reset to '0' to bring + * uMCTL2 out of deep power-down mode. Controller performs automatic SDRAM + * initialization on deep power-down exit. Present only in designs configu + * red to support mDDR or LPDDR2 or LPDDR3. For non-mDDR/non-LPDDR2/non-LPD + * DR3, this register should not be set to 1. FOR PERFORMANCE ONLY. +*/ #undef DDRC_PWRCTL_DEEPPOWERDOWN_EN_DEFVAL #undef DDRC_PWRCTL_DEEPPOWERDOWN_EN_SHIFT #undef DDRC_PWRCTL_DEEPPOWERDOWN_EN_MASK -#define DDRC_PWRCTL_DEEPPOWERDOWN_EN_DEFVAL 0x00000000 -#define DDRC_PWRCTL_DEEPPOWERDOWN_EN_SHIFT 2 -#define DDRC_PWRCTL_DEEPPOWERDOWN_EN_MASK 0x00000004U +#define DDRC_PWRCTL_DEEPPOWERDOWN_EN_DEFVAL 0x00000000 +#define DDRC_PWRCTL_DEEPPOWERDOWN_EN_SHIFT 2 +#define DDRC_PWRCTL_DEEPPOWERDOWN_EN_MASK 0x00000004U -/*If true then the uMCTL2 goes into power-down after a programmable number of cycles 'maximum idle clocks before power down' (P - RTMG.powerdown_to_x32). This register bit may be re-programmed during the course of normal operation.*/ +/* +* If true then the uMCTL2 goes into power-down after a programmable number + * of cycles 'maximum idle clocks before power down' (PWRTMG.powerdown_to_ + * x32). This register bit may be re-programmed during the course of normal + * operation. +*/ #undef DDRC_PWRCTL_POWERDOWN_EN_DEFVAL #undef DDRC_PWRCTL_POWERDOWN_EN_SHIFT #undef DDRC_PWRCTL_POWERDOWN_EN_MASK -#define DDRC_PWRCTL_POWERDOWN_EN_DEFVAL 0x00000000 -#define DDRC_PWRCTL_POWERDOWN_EN_SHIFT 1 -#define DDRC_PWRCTL_POWERDOWN_EN_MASK 0x00000002U +#define DDRC_PWRCTL_POWERDOWN_EN_DEFVAL 0x00000000 +#define DDRC_PWRCTL_POWERDOWN_EN_SHIFT 1 +#define DDRC_PWRCTL_POWERDOWN_EN_MASK 0x00000002U -/*If true then the uMCTL2 puts the SDRAM into Self Refresh after a programmable number of cycles 'maximum idle clocks before Se - f Refresh (PWRTMG.selfref_to_x32)'. This register bit may be re-programmed during the course of normal operation.*/ +/* +* If true then the uMCTL2 puts the SDRAM into Self Refresh after a program + * mable number of cycles 'maximum idle clocks before Self Refresh (PWRTMG. + * selfref_to_x32)'. This register bit may be re-programmed during the cour + * se of normal operation. +*/ #undef DDRC_PWRCTL_SELFREF_EN_DEFVAL #undef DDRC_PWRCTL_SELFREF_EN_SHIFT #undef DDRC_PWRCTL_SELFREF_EN_MASK -#define DDRC_PWRCTL_SELFREF_EN_DEFVAL 0x00000000 -#define DDRC_PWRCTL_SELFREF_EN_SHIFT 0 -#define DDRC_PWRCTL_SELFREF_EN_MASK 0x00000001U +#define DDRC_PWRCTL_SELFREF_EN_DEFVAL 0x00000000 +#define DDRC_PWRCTL_SELFREF_EN_SHIFT 0 +#define DDRC_PWRCTL_SELFREF_EN_MASK 0x00000001U -/*After this many clocks of NOP or deselect the uMCTL2 automatically puts the SDRAM into Self Refresh. This must be enabled in - he PWRCTL.selfref_en. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY.*/ +/* +* After this many clocks of NOP or deselect the uMCTL2 automatically puts + * the SDRAM into Self Refresh. This must be enabled in the PWRCTL.selfref_ + * en. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY. +*/ #undef DDRC_PWRTMG_SELFREF_TO_X32_DEFVAL #undef DDRC_PWRTMG_SELFREF_TO_X32_SHIFT #undef DDRC_PWRTMG_SELFREF_TO_X32_MASK -#define DDRC_PWRTMG_SELFREF_TO_X32_DEFVAL 0x00402010 -#define DDRC_PWRTMG_SELFREF_TO_X32_SHIFT 16 -#define DDRC_PWRTMG_SELFREF_TO_X32_MASK 0x00FF0000U +#define DDRC_PWRTMG_SELFREF_TO_X32_DEFVAL 0x00402010 +#define DDRC_PWRTMG_SELFREF_TO_X32_SHIFT 16 +#define DDRC_PWRTMG_SELFREF_TO_X32_MASK 0x00FF0000U -/*Minimum deep power-down time. For mDDR, value from the JEDEC specification is 0 as mDDR exits from deep power-down mode immed - ately after PWRCTL.deeppowerdown_en is de-asserted. For LPDDR2/LPDDR3, value from the JEDEC specification is 500us. Unit: Mul - iples of 4096 clocks. Present only in designs configured to support mDDR, LPDDR2 or LPDDR3. FOR PERFORMANCE ONLY.*/ +/* +* Minimum deep power-down time. For mDDR, value from the JEDEC specificati + * on is 0 as mDDR exits from deep power-down mode immediately after PWRCTL + * .deeppowerdown_en is de-asserted. For LPDDR2/LPDDR3, value from the JEDE + * C specification is 500us. Unit: Multiples of 4096 clocks. Present only i + * n designs configured to support mDDR, LPDDR2 or LPDDR3. FOR PERFORMANCE + * ONLY. +*/ #undef DDRC_PWRTMG_T_DPD_X4096_DEFVAL #undef DDRC_PWRTMG_T_DPD_X4096_SHIFT #undef DDRC_PWRTMG_T_DPD_X4096_MASK -#define DDRC_PWRTMG_T_DPD_X4096_DEFVAL 0x00402010 -#define DDRC_PWRTMG_T_DPD_X4096_SHIFT 8 -#define DDRC_PWRTMG_T_DPD_X4096_MASK 0x0000FF00U +#define DDRC_PWRTMG_T_DPD_X4096_DEFVAL 0x00402010 +#define DDRC_PWRTMG_T_DPD_X4096_SHIFT 8 +#define DDRC_PWRTMG_T_DPD_X4096_MASK 0x0000FF00U -/*After this many clocks of NOP or deselect the uMCTL2 automatically puts the SDRAM into power-down. This must be enabled in th - PWRCTL.powerdown_en. Unit: Multiples of 32 clocks FOR PERFORMANCE ONLY.*/ +/* +* After this many clocks of NOP or deselect the uMCTL2 automatically puts + * the SDRAM into power-down. This must be enabled in the PWRCTL.powerdown_ + * en. Unit: Multiples of 32 clocks FOR PERFORMANCE ONLY. +*/ #undef DDRC_PWRTMG_POWERDOWN_TO_X32_DEFVAL #undef DDRC_PWRTMG_POWERDOWN_TO_X32_SHIFT #undef DDRC_PWRTMG_POWERDOWN_TO_X32_MASK -#define DDRC_PWRTMG_POWERDOWN_TO_X32_DEFVAL 0x00402010 -#define DDRC_PWRTMG_POWERDOWN_TO_X32_SHIFT 0 -#define DDRC_PWRTMG_POWERDOWN_TO_X32_MASK 0x0000001FU +#define DDRC_PWRTMG_POWERDOWN_TO_X32_DEFVAL 0x00402010 +#define DDRC_PWRTMG_POWERDOWN_TO_X32_SHIFT 0 +#define DDRC_PWRTMG_POWERDOWN_TO_X32_MASK 0x0000001FU -/*Threshold value in number of clock cycles before the critical refresh or page timer expires. A critical refresh is to be issu - d before this threshold is reached. It is recommended that this not be changed from the default value, currently shown as 0x2 - It must always be less than internally used t_rfc_nom_x32. Note that, in LPDDR2/LPDDR3/LPDDR4, internally used t_rfc_nom_x32 - may be equal to RFSHTMG.t_rfc_nom_x32>>2 if derating is enabled (DERATEEN.derate_enable=1). Otherwise, internally used t_rfc_ - om_x32 will be equal to RFSHTMG.t_rfc_nom_x32. Unit: Multiples of 32 clocks.*/ +/* +* Threshold value in number of clock cycles before the critical refresh or + * page timer expires. A critical refresh is to be issued before this thre + * shold is reached. It is recommended that this not be changed from the de + * fault value, currently shown as 0x2. It must always be less than interna + * lly used t_rfc_nom_x32. Note that, in LPDDR2/LPDDR3/LPDDR4, internally u + * sed t_rfc_nom_x32 may be equal to RFSHTMG.t_rfc_nom_x32>>2 if derating i + * s enabled (DERATEEN.derate_enable=1). Otherwise, internally used t_rfc_n + * om_x32 will be equal to RFSHTMG.t_rfc_nom_x32. Unit: Multiples of 32 clo + * cks. +*/ #undef DDRC_RFSHCTL0_REFRESH_MARGIN_DEFVAL #undef DDRC_RFSHCTL0_REFRESH_MARGIN_SHIFT #undef DDRC_RFSHCTL0_REFRESH_MARGIN_MASK -#define DDRC_RFSHCTL0_REFRESH_MARGIN_DEFVAL 0x00210000 -#define DDRC_RFSHCTL0_REFRESH_MARGIN_SHIFT 20 -#define DDRC_RFSHCTL0_REFRESH_MARGIN_MASK 0x00F00000U +#define DDRC_RFSHCTL0_REFRESH_MARGIN_DEFVAL 0x00210000 +#define DDRC_RFSHCTL0_REFRESH_MARGIN_SHIFT 20 +#define DDRC_RFSHCTL0_REFRESH_MARGIN_MASK 0x00F00000U -/*If the refresh timer (tRFCnom, also known as tREFI) has expired at least once, but it has not expired (RFSHCTL0.refresh_burst - 1) times yet, then a speculative refresh may be performed. A speculative refresh is a refresh performed at a time when refres - would be useful, but before it is absolutely required. When the SDRAM bus is idle for a period of time determined by this RF - HCTL0.refresh_to_x32 and the refresh timer has expired at least once since the last refresh, then a speculative refresh is pe - formed. Speculative refreshes continues successively until there are no refreshes pending or until new reads or writes are is - ued to the uMCTL2. FOR PERFORMANCE ONLY.*/ +/* +* If the refresh timer (tRFCnom, also known as tREFI) has expired at least + * once, but it has not expired (RFSHCTL0.refresh_burst+1) times yet, then + * a speculative refresh may be performed. A speculative refresh is a refr + * esh performed at a time when refresh would be useful, but before it is a + * bsolutely required. When the SDRAM bus is idle for a period of time dete + * rmined by this RFSHCTL0.refresh_to_x32 and the refresh timer has expired + * at least once since the last refresh, then a speculative refresh is per + * formed. Speculative refreshes continues successively until there are no + * refreshes pending or until new reads or writes are issued to the uMCTL2. + * FOR PERFORMANCE ONLY. +*/ #undef DDRC_RFSHCTL0_REFRESH_TO_X32_DEFVAL #undef DDRC_RFSHCTL0_REFRESH_TO_X32_SHIFT #undef DDRC_RFSHCTL0_REFRESH_TO_X32_MASK -#define DDRC_RFSHCTL0_REFRESH_TO_X32_DEFVAL 0x00210000 -#define DDRC_RFSHCTL0_REFRESH_TO_X32_SHIFT 12 -#define DDRC_RFSHCTL0_REFRESH_TO_X32_MASK 0x0001F000U +#define DDRC_RFSHCTL0_REFRESH_TO_X32_DEFVAL 0x00210000 +#define DDRC_RFSHCTL0_REFRESH_TO_X32_SHIFT 12 +#define DDRC_RFSHCTL0_REFRESH_TO_X32_MASK 0x0001F000U -/*The programmed value + 1 is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the re - reshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of re - reshes. Therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for - RFSHCTL.refresh_burst slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshe - . - 0 - single refresh - 1 - burst-of-2 refresh - 7 - burst-of-8 refresh For information on burst refresh feature refer to se - tion 3.9 of DDR2 JEDEC specification - JESD79-2F.pdf. For DDR2/3, the refresh is always per-rank and not per-bank. The rank r - fresh can be accumulated over 8*tREFI cycles using the burst refresh feature. In DDR4 mode, according to Fine Granularity fea - ure, 8 refreshes can be postponed in 1X mode, 16 refreshes in 2X mode and 32 refreshes in 4X mode. If using PHY-initiated upd - tes, care must be taken in the setting of RFSHCTL0.refresh_burst, to ensure that tRFCmax is not violated due to a PHY-initiat - d update occurring shortly before a refresh burst was due. In this situation, the refresh burst will be delayed until the PHY - initiated update is complete.*/ +/* +* The programmed value + 1 is the number of refresh timeouts that is allow + * ed to accumulate before traffic is blocked and the refreshes are forced + * to execute. Closing pages to perform a refresh is a one-time penalty tha + * t must be paid for each group of refreshes. Therefore, performing refres + * hes in a burst reduces the per-refresh penalty of these page closings. H + * igher numbers for RFSHCTL.refresh_burst slightly increases utilization; + * lower numbers decreases the worst-case latency associated with refreshes + * . - 0 - single refresh - 1 - burst-of-2 refresh - 7 - burst-of-8 refresh + * For information on burst refresh feature refer to section 3.9 of DDR2 J + * EDEC specification - JESD79-2F.pdf. For DDR2/3, the refresh is always pe + * r-rank and not per-bank. The rank refresh can be accumulated over 8*tREF + * I cycles using the burst refresh feature. In DDR4 mode, according to Fin + * e Granularity feature, 8 refreshes can be postponed in 1X mode, 16 refre + * shes in 2X mode and 32 refreshes in 4X mode. If using PHY-initiated upda + * tes, care must be taken in the setting of RFSHCTL0.refresh_burst, to ens + * ure that tRFCmax is not violated due to a PHY-initiated update occurring + * shortly before a refresh burst was due. In this situation, the refresh + * burst will be delayed until the PHY-initiated update is complete. +*/ #undef DDRC_RFSHCTL0_REFRESH_BURST_DEFVAL #undef DDRC_RFSHCTL0_REFRESH_BURST_SHIFT #undef DDRC_RFSHCTL0_REFRESH_BURST_MASK -#define DDRC_RFSHCTL0_REFRESH_BURST_DEFVAL 0x00210000 -#define DDRC_RFSHCTL0_REFRESH_BURST_SHIFT 4 -#define DDRC_RFSHCTL0_REFRESH_BURST_MASK 0x000001F0U +#define DDRC_RFSHCTL0_REFRESH_BURST_DEFVAL 0x00210000 +#define DDRC_RFSHCTL0_REFRESH_BURST_SHIFT 4 +#define DDRC_RFSHCTL0_REFRESH_BURST_MASK 0x000001F0U -/*- 1 - Per bank refresh; - 0 - All bank refresh. Per bank refresh allows traffic to flow to other banks. Per bank refresh is n - t supported by all LPDDR2 devices but should be supported by all LPDDR3/LPDDR4 devices. Present only in designs configured to - support LPDDR2/LPDDR3/LPDDR4*/ +/* +* - 1 - Per bank refresh; - 0 - All bank refresh. Per bank refresh allows + * traffic to flow to other banks. Per bank refresh is not supported by all + * LPDDR2 devices but should be supported by all LPDDR3/LPDDR4 devices. Pr + * esent only in designs configured to support LPDDR2/LPDDR3/LPDDR4 +*/ #undef DDRC_RFSHCTL0_PER_BANK_REFRESH_DEFVAL #undef DDRC_RFSHCTL0_PER_BANK_REFRESH_SHIFT #undef DDRC_RFSHCTL0_PER_BANK_REFRESH_MASK -#define DDRC_RFSHCTL0_PER_BANK_REFRESH_DEFVAL 0x00210000 -#define DDRC_RFSHCTL0_PER_BANK_REFRESH_SHIFT 2 -#define DDRC_RFSHCTL0_PER_BANK_REFRESH_MASK 0x00000004U +#define DDRC_RFSHCTL0_PER_BANK_REFRESH_DEFVAL 0x00210000 +#define DDRC_RFSHCTL0_PER_BANK_REFRESH_SHIFT 2 +#define DDRC_RFSHCTL0_PER_BANK_REFRESH_MASK 0x00000004U -/*Fine Granularity Refresh Mode - 000 - Fixed 1x (Normal mode) - 001 - Fixed 2x - 010 - Fixed 4x - 101 - Enable on the fly 2x ( - ot supported) - 110 - Enable on the fly 4x (not supported) - Everything else - reserved Note: The on-the-fly modes is not sup - orted in this version of the uMCTL2. Note: This must be set up while the Controller is in reset or while the Controller is in - self-refresh mode. Changing this during normal operation is not allowed. Making this a dynamic register will be supported in - uture version of the uMCTL2.*/ +/* +* Refresh timer start for rank 1 (only present in multi-rank configuration + * s). This is useful in staggering the refreshes to multiple ranks to help + * traffic to proceed. This is explained in Refresh Controls section of ar + * chitecture chapter. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY. +*/ +#undef DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_DEFVAL +#undef DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_SHIFT +#undef DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_MASK +#define DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_DEFVAL 0x00000000 +#define DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_SHIFT 16 +#define DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_MASK 0x0FFF0000U + +/* +* Refresh timer start for rank 0 (only present in multi-rank configuration + * s). This is useful in staggering the refreshes to multiple ranks to help + * traffic to proceed. This is explained in Refresh Controls section of ar + * chitecture chapter. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY. +*/ +#undef DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_DEFVAL +#undef DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_SHIFT +#undef DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_MASK +#define DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_DEFVAL 0x00000000 +#define DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_SHIFT 0 +#define DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_MASK 0x00000FFFU + +/* +* Fine Granularity Refresh Mode - 000 - Fixed 1x (Normal mode) - 001 - Fix + * ed 2x - 010 - Fixed 4x - 101 - Enable on the fly 2x (not supported) - 11 + * 0 - Enable on the fly 4x (not supported) - Everything else - reserved No + * te: The on-the-fly modes is not supported in this version of the uMCTL2. + * Note: This must be set up while the Controller is in reset or while the + * Controller is in self-refresh mode. Changing this during normal operati + * on is not allowed. Making this a dynamic register will be supported in f + * uture version of the uMCTL2. +*/ #undef DDRC_RFSHCTL3_REFRESH_MODE_DEFVAL #undef DDRC_RFSHCTL3_REFRESH_MODE_SHIFT #undef DDRC_RFSHCTL3_REFRESH_MODE_MASK -#define DDRC_RFSHCTL3_REFRESH_MODE_DEFVAL 0x00000000 -#define DDRC_RFSHCTL3_REFRESH_MODE_SHIFT 4 -#define DDRC_RFSHCTL3_REFRESH_MODE_MASK 0x00000070U +#define DDRC_RFSHCTL3_REFRESH_MODE_DEFVAL 0x00000000 +#define DDRC_RFSHCTL3_REFRESH_MODE_SHIFT 4 +#define DDRC_RFSHCTL3_REFRESH_MODE_MASK 0x00000070U -/*Toggle this signal (either from 0 to 1 or from 1 to 0) to indicate that the refresh register(s) have been updated. The value - s automatically updated when exiting reset, so it does not need to be toggled initially.*/ +/* +* Toggle this signal (either from 0 to 1 or from 1 to 0) to indicate that + * the refresh register(s) have been updated. The value is automatically up + * dated when exiting reset, so it does not need to be toggled initially. +*/ #undef DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_DEFVAL #undef DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_SHIFT #undef DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_MASK -#define DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_DEFVAL 0x00000000 -#define DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_SHIFT 1 -#define DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_MASK 0x00000002U +#define DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_DEFVAL 0x00000000 +#define DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_SHIFT 1 +#define DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_MASK 0x00000002U -/*When '1', disable auto-refresh generated by the uMCTL2. When auto-refresh is disabled, the SoC core must generate refreshes u - ing the registers reg_ddrc_rank0_refresh, reg_ddrc_rank1_refresh, reg_ddrc_rank2_refresh and reg_ddrc_rank3_refresh. When dis - auto_refresh transitions from 0 to 1, any pending refreshes are immediately scheduled by the uMCTL2. If DDR4 CRC/parity retry - is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), disable auto-refresh is not supported, and this bit must be set to '0'. - his register field is changeable on the fly.*/ +/* +* When '1', disable auto-refresh generated by the uMCTL2. When auto-refres + * h is disabled, the SoC core must generate refreshes using the registers + * reg_ddrc_rank0_refresh, reg_ddrc_rank1_refresh, reg_ddrc_rank2_refresh a + * nd reg_ddrc_rank3_refresh. When dis_auto_refresh transitions from 0 to 1 + * , any pending refreshes are immediately scheduled by the uMCTL2. If DDR4 + * CRC/parity retry is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), d + * isable auto-refresh is not supported, and this bit must be set to '0'. T + * his register field is changeable on the fly. +*/ #undef DDRC_RFSHCTL3_DIS_AUTO_REFRESH_DEFVAL #undef DDRC_RFSHCTL3_DIS_AUTO_REFRESH_SHIFT #undef DDRC_RFSHCTL3_DIS_AUTO_REFRESH_MASK -#define DDRC_RFSHCTL3_DIS_AUTO_REFRESH_DEFVAL 0x00000000 -#define DDRC_RFSHCTL3_DIS_AUTO_REFRESH_SHIFT 0 -#define DDRC_RFSHCTL3_DIS_AUTO_REFRESH_MASK 0x00000001U +#define DDRC_RFSHCTL3_DIS_AUTO_REFRESH_DEFVAL 0x00000000 +#define DDRC_RFSHCTL3_DIS_AUTO_REFRESH_SHIFT 0 +#define DDRC_RFSHCTL3_DIS_AUTO_REFRESH_MASK 0x00000001U -/*tREFI: Average time interval between refreshes per rank (Specification: 7.8us for DDR2, DDR3 and DDR4. See JEDEC specificatio - for mDDR, LPDDR2, LPDDR3 and LPDDR4). For LPDDR2/LPDDR3/LPDDR4: - if using all-bank refreshes (RFSHCTL0.per_bank_refresh = 0 - , this register should be set to tREFIab - if using per-bank refreshes (RFSHCTL0.per_bank_refresh = 1), this register should - e set to tREFIpb For configurations with MEMC_FREQ_RATIO=2, program this to (tREFI/2), no rounding up. In DDR4 mode, tREFI va - ue is different depending on the refresh mode. The user should program the appropriate value from the spec based on the value - programmed in the refresh mode register. Note that RFSHTMG.t_rfc_nom_x32 * 32 must be greater than RFSHTMG.t_rfc_min, and RFS - TMG.t_rfc_nom_x32 must be greater than 0x1. Unit: Multiples of 32 clocks.*/ +/* +* tREFI: Average time interval between refreshes per rank (Specification: + * 7.8us for DDR2, DDR3 and DDR4. See JEDEC specification for mDDR, LPDDR2, + * LPDDR3 and LPDDR4). For LPDDR2/LPDDR3/LPDDR4: - if using all-bank refre + * shes (RFSHCTL0.per_bank_refresh = 0), this register should be set to tRE + * FIab - if using per-bank refreshes (RFSHCTL0.per_bank_refresh = 1), this + * register should be set to tREFIpb For configurations with MEMC_FREQ_RAT + * IO=2, program this to (tREFI/2), no rounding up. In DDR4 mode, tREFI val + * ue is different depending on the refresh mode. The user should program t + * he appropriate value from the spec based on the value programmed in the + * refresh mode register. Note that RFSHTMG.t_rfc_nom_x32 * 32 must be grea + * ter than RFSHTMG.t_rfc_min, and RFSHTMG.t_rfc_nom_x32 must be greater th + * an 0x1. Unit: Multiples of 32 clocks. +*/ #undef DDRC_RFSHTMG_T_RFC_NOM_X32_DEFVAL #undef DDRC_RFSHTMG_T_RFC_NOM_X32_SHIFT #undef DDRC_RFSHTMG_T_RFC_NOM_X32_MASK -#define DDRC_RFSHTMG_T_RFC_NOM_X32_DEFVAL 0x0062008C -#define DDRC_RFSHTMG_T_RFC_NOM_X32_SHIFT 16 -#define DDRC_RFSHTMG_T_RFC_NOM_X32_MASK 0x0FFF0000U +#define DDRC_RFSHTMG_T_RFC_NOM_X32_DEFVAL 0x0062008C +#define DDRC_RFSHTMG_T_RFC_NOM_X32_SHIFT 16 +#define DDRC_RFSHTMG_T_RFC_NOM_X32_MASK 0x0FFF0000U -/*Used only when LPDDR3 memory type is connected. Should only be changed when uMCTL2 is in reset. Specifies whether to use the - REFBW parameter (required by some LPDDR3 devices which comply with earlier versions of the LPDDR3 JEDEC specification) or not - - 0 - tREFBW parameter not used - 1 - tREFBW parameter used*/ +/* +* Used only when LPDDR3 memory type is connected. Should only be changed w + * hen uMCTL2 is in reset. Specifies whether to use the tREFBW parameter (r + * equired by some LPDDR3 devices which comply with earlier versions of the + * LPDDR3 JEDEC specification) or not: - 0 - tREFBW parameter not used - 1 + * - tREFBW parameter used +*/ #undef DDRC_RFSHTMG_LPDDR3_TREFBW_EN_DEFVAL #undef DDRC_RFSHTMG_LPDDR3_TREFBW_EN_SHIFT #undef DDRC_RFSHTMG_LPDDR3_TREFBW_EN_MASK -#define DDRC_RFSHTMG_LPDDR3_TREFBW_EN_DEFVAL 0x0062008C -#define DDRC_RFSHTMG_LPDDR3_TREFBW_EN_SHIFT 15 -#define DDRC_RFSHTMG_LPDDR3_TREFBW_EN_MASK 0x00008000U +#define DDRC_RFSHTMG_LPDDR3_TREFBW_EN_DEFVAL 0x0062008C +#define DDRC_RFSHTMG_LPDDR3_TREFBW_EN_SHIFT 15 +#define DDRC_RFSHTMG_LPDDR3_TREFBW_EN_MASK 0x00008000U -/*tRFC (min): Minimum time from refresh to refresh or activate. For MEMC_FREQ_RATIO=1 configurations, t_rfc_min should be set t - RoundUp(tRFCmin/tCK). For MEMC_FREQ_RATIO=2 configurations, t_rfc_min should be set to RoundUp(RoundUp(tRFCmin/tCK)/2). In L - DDR2/LPDDR3/LPDDR4 mode: - if using all-bank refreshes, the tRFCmin value in the above equations is equal to tRFCab - if usin - per-bank refreshes, the tRFCmin value in the above equations is equal to tRFCpb In DDR4 mode, the tRFCmin value in the above - equations is different depending on the refresh mode (fixed 1X,2X,4X) and the device density. The user should program the app - opriate value from the spec based on the 'refresh_mode' and the device density that is used. Unit: Clocks.*/ +/* +* tRFC (min): Minimum time from refresh to refresh or activate. For MEMC_F + * REQ_RATIO=1 configurations, t_rfc_min should be set to RoundUp(tRFCmin/t + * CK). For MEMC_FREQ_RATIO=2 configurations, t_rfc_min should be set to Ro + * undUp(RoundUp(tRFCmin/tCK)/2). In LPDDR2/LPDDR3/LPDDR4 mode: - if using + * all-bank refreshes, the tRFCmin value in the above equations is equal to + * tRFCab - if using per-bank refreshes, the tRFCmin value in the above eq + * uations is equal to tRFCpb In DDR4 mode, the tRFCmin value in the above + * equations is different depending on the refresh mode (fixed 1X,2X,4X) an + * d the device density. The user should program the appropriate value from + * the spec based on the 'refresh_mode' and the device density that is use + * d. Unit: Clocks. +*/ #undef DDRC_RFSHTMG_T_RFC_MIN_DEFVAL #undef DDRC_RFSHTMG_T_RFC_MIN_SHIFT #undef DDRC_RFSHTMG_T_RFC_MIN_MASK -#define DDRC_RFSHTMG_T_RFC_MIN_DEFVAL 0x0062008C -#define DDRC_RFSHTMG_T_RFC_MIN_SHIFT 0 -#define DDRC_RFSHTMG_T_RFC_MIN_MASK 0x000003FFU +#define DDRC_RFSHTMG_T_RFC_MIN_DEFVAL 0x0062008C +#define DDRC_RFSHTMG_T_RFC_MIN_SHIFT 0 +#define DDRC_RFSHTMG_T_RFC_MIN_MASK 0x000003FFU -/*Disable ECC scrubs. Valid only when ECCCFG0.ecc_mode = 3'b100 and MEMC_USE_RMW is defined*/ +/* +* Disable ECC scrubs. Valid only when ECCCFG0.ecc_mode = 3'b100 and MEMC_U + * SE_RMW is defined +*/ #undef DDRC_ECCCFG0_DIS_SCRUB_DEFVAL #undef DDRC_ECCCFG0_DIS_SCRUB_SHIFT #undef DDRC_ECCCFG0_DIS_SCRUB_MASK -#define DDRC_ECCCFG0_DIS_SCRUB_DEFVAL 0x00000000 -#define DDRC_ECCCFG0_DIS_SCRUB_SHIFT 4 -#define DDRC_ECCCFG0_DIS_SCRUB_MASK 0x00000010U +#define DDRC_ECCCFG0_DIS_SCRUB_DEFVAL 0x00000000 +#define DDRC_ECCCFG0_DIS_SCRUB_SHIFT 4 +#define DDRC_ECCCFG0_DIS_SCRUB_MASK 0x00000010U -/*ECC mode indicator - 000 - ECC disabled - 100 - ECC enabled - SEC/DED over 1 beat - all other settings are reserved for futur - use*/ +/* +* ECC mode indicator - 000 - ECC disabled - 100 - ECC enabled - SEC/DED ov + * er 1 beat - all other settings are reserved for future use +*/ #undef DDRC_ECCCFG0_ECC_MODE_DEFVAL #undef DDRC_ECCCFG0_ECC_MODE_SHIFT #undef DDRC_ECCCFG0_ECC_MODE_MASK -#define DDRC_ECCCFG0_ECC_MODE_DEFVAL 0x00000000 -#define DDRC_ECCCFG0_ECC_MODE_SHIFT 0 -#define DDRC_ECCCFG0_ECC_MODE_MASK 0x00000007U +#define DDRC_ECCCFG0_ECC_MODE_DEFVAL 0x00000000 +#define DDRC_ECCCFG0_ECC_MODE_SHIFT 0 +#define DDRC_ECCCFG0_ECC_MODE_MASK 0x00000007U -/*Selects whether to poison 1 or 2 bits - if 0 -> 2-bit (uncorrectable) data poisoning, if 1 -> 1-bit (correctable) data poison - ng, if ECCCFG1.data_poison_en=1*/ +/* +* Selects whether to poison 1 or 2 bits - if 0 -> 2-bit (uncorrectable) da + * ta poisoning, if 1 -> 1-bit (correctable) data poisoning, if ECCCFG1.dat + * a_poison_en=1 +*/ #undef DDRC_ECCCFG1_DATA_POISON_BIT_DEFVAL #undef DDRC_ECCCFG1_DATA_POISON_BIT_SHIFT #undef DDRC_ECCCFG1_DATA_POISON_BIT_MASK -#define DDRC_ECCCFG1_DATA_POISON_BIT_DEFVAL 0x00000000 -#define DDRC_ECCCFG1_DATA_POISON_BIT_SHIFT 1 -#define DDRC_ECCCFG1_DATA_POISON_BIT_MASK 0x00000002U +#define DDRC_ECCCFG1_DATA_POISON_BIT_DEFVAL 0x00000000 +#define DDRC_ECCCFG1_DATA_POISON_BIT_SHIFT 1 +#define DDRC_ECCCFG1_DATA_POISON_BIT_MASK 0x00000002U -/*Enable ECC data poisoning - introduces ECC errors on writes to address specified by the ECCPOISONADDR0/1 registers*/ +/* +* Enable ECC data poisoning - introduces ECC errors on writes to address s + * pecified by the ECCPOISONADDR0/1 registers +*/ #undef DDRC_ECCCFG1_DATA_POISON_EN_DEFVAL #undef DDRC_ECCCFG1_DATA_POISON_EN_SHIFT #undef DDRC_ECCCFG1_DATA_POISON_EN_MASK -#define DDRC_ECCCFG1_DATA_POISON_EN_DEFVAL 0x00000000 -#define DDRC_ECCCFG1_DATA_POISON_EN_SHIFT 0 -#define DDRC_ECCCFG1_DATA_POISON_EN_MASK 0x00000001U +#define DDRC_ECCCFG1_DATA_POISON_EN_DEFVAL 0x00000000 +#define DDRC_ECCCFG1_DATA_POISON_EN_SHIFT 0 +#define DDRC_ECCCFG1_DATA_POISON_EN_MASK 0x00000001U -/*The maximum number of DFI PHY clock cycles allowed from the assertion of the dfi_rddata_en signal to the assertion of each of - the corresponding bits of the dfi_rddata_valid signal. This corresponds to the DFI timing parameter tphy_rdlat. Refer to PHY - pecification for correct value. This value it only used for detecting read data timeout when DDR4 retry is enabled by CRCPARC - L1.crc_parity_retry_enable=1. Maximum supported value: - 1:1 Frequency mode : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_ - dlat < 'd114 - 1:2 Frequency mode ANDAND DFITMG0.dfi_rddata_use_sdr == 1 : CRCPARCTL1.dfi_t_phy_rdlat < 64 - 1:2 Frequency mo - e ANDAND DFITMG0.dfi_rddata_use_sdr == 0 : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_rdlat < 'd114 Unit: DFI Clocks*/ +/* +* The maximum number of DFI PHY clock cycles allowed from the assertion of + * the dfi_rddata_en signal to the assertion of each of the corresponding + * bits of the dfi_rddata_valid signal. This corresponds to the DFI timing + * parameter tphy_rdlat. Refer to PHY specification for correct value. This + * value it only used for detecting read data timeout when DDR4 retry is e + * nabled by CRCPARCTL1.crc_parity_retry_enable=1. Maximum supported value: + * - 1:1 Frequency mode : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_r + * dlat < 'd114 - 1:2 Frequency mode ANDAND DFITMG0.dfi_rddata_use_sdr == 1 + * : CRCPARCTL1.dfi_t_phy_rdlat < 64 - 1:2 Frequency mode ANDAND DFITMG0.d + * fi_rddata_use_sdr == 0 : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_ + * rdlat < 'd114 Unit: DFI Clocks +*/ #undef DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_DEFVAL #undef DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_SHIFT #undef DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_MASK -#define DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_DEFVAL 0x10000200 -#define DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_SHIFT 24 -#define DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_MASK 0x3F000000U +#define DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_DEFVAL 0x10000200 +#define DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_SHIFT 24 +#define DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_MASK 0x3F000000U -/*After a Parity or CRC error is flagged on dfi_alert_n signal, the software has an option to read the mode registers in the DR - M before the hardware begins the retry process - 1: Wait for software to read/write the mode registers before hardware begins - the retry. After software is done with its operations, it will clear the alert interrupt register bit - 0: Hardware can begin - the retry right away after the dfi_alert_n pulse goes away. The value on this register is valid only when retry is enabled (P - RCTRL.crc_parity_retry_enable = 1) If this register is set to 1 and if the software doesn't clear the interrupt register afte - handling the parity/CRC error, then the hardware will not begin the retry process and the system will hang. In the case of P - rity/CRC error, there are two possibilities when the software doesn't reset MR5[4] to 0. - (i) If 'Persistent parity' mode re - ister bit is NOT set: the commands sent during retry and normal operation are executed without parity checking. The value in - he Parity error log register MPR Page 1 is valid. - (ii) If 'Persistent parity' mode register bit is SET: Parity checking is - one for commands sent during retry and normal operation. If multiple errors occur before MR5[4] is cleared, the error log in - PR Page 1 should be treated as 'Don't care'.*/ +/* +* After a Parity or CRC error is flagged on dfi_alert_n signal, the softwa + * re has an option to read the mode registers in the DRAM before the hardw + * are begins the retry process - 1: Wait for software to read/write the mo + * de registers before hardware begins the retry. After software is done wi + * th its operations, it will clear the alert interrupt register bit - 0: H + * ardware can begin the retry right away after the dfi_alert_n pulse goes + * away. The value on this register is valid only when retry is enabled (PA + * RCTRL.crc_parity_retry_enable = 1) If this register is set to 1 and if t + * he software doesn't clear the interrupt register after handling the pari + * ty/CRC error, then the hardware will not begin the retry process and the + * system will hang. In the case of Parity/CRC error, there are two possib + * ilities when the software doesn't reset MR5[4] to 0. - (i) If 'Persisten + * t parity' mode register bit is NOT set: the commands sent during retry a + * nd normal operation are executed without parity checking. The value in t + * he Parity error log register MPR Page 1 is valid. - (ii) If 'Persistent + * parity' mode register bit is SET: Parity checking is done for commands s + * ent during retry and normal operation. If multiple errors occur before M + * R5[4] is cleared, the error log in MPR Page 1 should be treated as 'Don' + * t care'. +*/ #undef DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_DEFVAL #undef DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_SHIFT #undef DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_MASK -#define DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_DEFVAL 0x10000200 -#define DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_SHIFT 9 -#define DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_MASK 0x00000200U +#define DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_DEFVAL 0x10000200 +#define DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_SHIFT 9 +#define DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_MASK 0x00000200U -/*- 1: Enable command retry mechanism in case of C/A Parity or CRC error - 0: Disable command retry mechanism when C/A Parity o - CRC features are enabled. Note that retry functionality is not supported if burst chop is enabled (MSTR.burstchop = 1) and/o - disable auto-refresh is enabled (RFSHCTL3.dis_auto_refresh = 1)*/ +/* +* - 1: Enable command retry mechanism in case of C/A Parity or CRC error - + * 0: Disable command retry mechanism when C/A Parity or CRC features are + * enabled. Note that retry functionality is not supported if burst chop is + * enabled (MSTR.burstchop = 1) and/or disable auto-refresh is enabled (RF + * SHCTL3.dis_auto_refresh = 1) +*/ #undef DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_DEFVAL #undef DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_SHIFT #undef DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_MASK -#define DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_DEFVAL 0x10000200 -#define DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_SHIFT 8 -#define DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_MASK 0x00000100U +#define DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_DEFVAL 0x10000200 +#define DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_SHIFT 8 +#define DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_MASK 0x00000100U -/*CRC Calculation setting register - 1: CRC includes DM signal - 0: CRC not includes DM signal Present only in designs configur - d to support DDR4.*/ +/* +* CRC Calculation setting register - 1: CRC includes DM signal - 0: CRC no + * t includes DM signal Present only in designs configured to support DDR4. +*/ #undef DDRC_CRCPARCTL1_CRC_INC_DM_DEFVAL #undef DDRC_CRCPARCTL1_CRC_INC_DM_SHIFT #undef DDRC_CRCPARCTL1_CRC_INC_DM_MASK -#define DDRC_CRCPARCTL1_CRC_INC_DM_DEFVAL 0x10000200 -#define DDRC_CRCPARCTL1_CRC_INC_DM_SHIFT 7 -#define DDRC_CRCPARCTL1_CRC_INC_DM_MASK 0x00000080U +#define DDRC_CRCPARCTL1_CRC_INC_DM_DEFVAL 0x10000200 +#define DDRC_CRCPARCTL1_CRC_INC_DM_SHIFT 7 +#define DDRC_CRCPARCTL1_CRC_INC_DM_MASK 0x00000080U -/*CRC enable Register - 1: Enable generation of CRC - 0: Disable generation of CRC The setting of this register should match th - CRC mode register setting in the DRAM.*/ +/* +* CRC enable Register - 1: Enable generation of CRC - 0: Disable generatio + * n of CRC The setting of this register should match the CRC mode register + * setting in the DRAM. +*/ #undef DDRC_CRCPARCTL1_CRC_ENABLE_DEFVAL #undef DDRC_CRCPARCTL1_CRC_ENABLE_SHIFT #undef DDRC_CRCPARCTL1_CRC_ENABLE_MASK -#define DDRC_CRCPARCTL1_CRC_ENABLE_DEFVAL 0x10000200 -#define DDRC_CRCPARCTL1_CRC_ENABLE_SHIFT 4 -#define DDRC_CRCPARCTL1_CRC_ENABLE_MASK 0x00000010U +#define DDRC_CRCPARCTL1_CRC_ENABLE_DEFVAL 0x10000200 +#define DDRC_CRCPARCTL1_CRC_ENABLE_SHIFT 4 +#define DDRC_CRCPARCTL1_CRC_ENABLE_MASK 0x00000010U -/*C/A Parity enable register - 1: Enable generation of C/A parity and detection of C/A parity error - 0: Disable generation of - /A parity and disable detection of C/A parity error If RCD's parity error detection or SDRAM's parity detection is enabled, t - is register should be 1.*/ +/* +* C/A Parity enable register - 1: Enable generation of C/A parity and dete + * ction of C/A parity error - 0: Disable generation of C/A parity and disa + * ble detection of C/A parity error If RCD's parity error detection or SDR + * AM's parity detection is enabled, this register should be 1. +*/ #undef DDRC_CRCPARCTL1_PARITY_ENABLE_DEFVAL #undef DDRC_CRCPARCTL1_PARITY_ENABLE_SHIFT #undef DDRC_CRCPARCTL1_PARITY_ENABLE_MASK -#define DDRC_CRCPARCTL1_PARITY_ENABLE_DEFVAL 0x10000200 -#define DDRC_CRCPARCTL1_PARITY_ENABLE_SHIFT 0 -#define DDRC_CRCPARCTL1_PARITY_ENABLE_MASK 0x00000001U +#define DDRC_CRCPARCTL1_PARITY_ENABLE_DEFVAL 0x10000200 +#define DDRC_CRCPARCTL1_PARITY_ENABLE_SHIFT 0 +#define DDRC_CRCPARCTL1_PARITY_ENABLE_MASK 0x00000001U -/*Value from the DRAM spec indicating the maximum width of the dfi_alert_n pulse when a parity error occurs. Recommended values - - tPAR_ALERT_PW.MAX For configurations with MEMC_FREQ_RATIO=2, program this to tPAR_ALERT_PW.MAX/2 and round up to next inte - er value. Values of 0, 1 and 2 are illegal. This value must be greater than CRCPARCTL2.t_crc_alert_pw_max.*/ +/* +* Value from the DRAM spec indicating the maximum width of the dfi_alert_n + * pulse when a parity error occurs. Recommended values: - tPAR_ALERT_PW.M + * AX For configurations with MEMC_FREQ_RATIO=2, program this to tPAR_ALERT + * _PW.MAX/2 and round up to next integer value. Values of 0, 1 and 2 are i + * llegal. This value must be greater than CRCPARCTL2.t_crc_alert_pw_max. +*/ #undef DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_DEFVAL #undef DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_SHIFT #undef DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_MASK -#define DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_DEFVAL 0x0030050C -#define DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_SHIFT 16 -#define DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_MASK 0x01FF0000U +#define DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_DEFVAL 0x0030050C +#define DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_SHIFT 16 +#define DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_MASK 0x01FF0000U -/*Value from the DRAM spec indicating the maximum width of the dfi_alert_n pulse when a CRC error occurs. Recommended values: - - tCRC_ALERT_PW.MAX For configurations with MEMC_FREQ_RATIO=2, program this to tCRC_ALERT_PW.MAX/2 and round up to next integer - value. Values of 0, 1 and 2 are illegal. This value must be less than CRCPARCTL2.t_par_alert_pw_max.*/ +/* +* Value from the DRAM spec indicating the maximum width of the dfi_alert_n + * pulse when a CRC error occurs. Recommended values: - tCRC_ALERT_PW.MAX + * For configurations with MEMC_FREQ_RATIO=2, program this to tCRC_ALERT_PW + * .MAX/2 and round up to next integer value. Values of 0, 1 and 2 are ille + * gal. This value must be less than CRCPARCTL2.t_par_alert_pw_max. +*/ #undef DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_DEFVAL #undef DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_SHIFT #undef DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_MASK -#define DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_DEFVAL 0x0030050C -#define DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_SHIFT 8 -#define DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_MASK 0x00001F00U +#define DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_DEFVAL 0x0030050C +#define DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_SHIFT 8 +#define DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_MASK 0x00001F00U -/*Indicates the maximum duration in number of DRAM clock cycles for which a command should be held in the Command Retry FIFO be - ore it is popped out. Every location in the Command Retry FIFO has an associated down counting timer that will use this regis - er as the start value. The down counting starts when a command is loaded into the FIFO. The timer counts down every 4 DRAM cy - les. When the counter reaches zero, the entry is popped from the FIFO. All the counters are frozen, if a C/A Parity or CRC er - or occurs before the counter reaches zero. The counter is reset to 0, after all the commands in the FIFO are retried. Recomme - ded(minimum) values: - Only C/A Parity is enabled. RoundUp((PHY Command Latency(DRAM CLK) + CAL + RDIMM delay + tPAR_ALERT_ON - max + tPAR_UNKNOWN + PHY Alert Latency(DRAM CLK) + board delay) / 4) + 2 - Both C/A Parity and CRC is enabled/ Only CRC is en - bled. RoundUp((PHY Command Latency(DRAM CLK) + CAL + RDIMM delay + WL + 5(BL10)+ tCRC_ALERT.max + PHY Alert Latency(DRAM CLK) - + board delay) / 4) + 2 Note 1: All value (e.g. tPAR_ALERT_ON) should be in terms of DRAM Clock and round up Note 2: Board de - ay(Command/Alert_n) should be considered. Note 3: Use the worst case(longer) value for PHY Latencies/Board delay Note 4: The - ecommended values are minimum value to be set. For mode detail, See 'Calculation of FIFO Depth' section. Max value can be set - to this register is defined below: - MEMC_BURST_LENGTH == 16 Full bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH- - Full bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Half bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_D - PTH-4 Half bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-6 Quarter bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CM - _FIFO_DEPTH-8 Quarter bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-12 - MEMC_BURST_LENGTH != 16 Full bus Mode (C - C=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-1 Full bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mo - e (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Quarte - bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-4 Quarter bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEP - H-6 Values of 0, 1 and 2 are illegal.*/ +/* +* Indicates the maximum duration in number of DRAM clock cycles for which + * a command should be held in the Command Retry FIFO before it is popped o + * ut. Every location in the Command Retry FIFO has an associated down coun + * ting timer that will use this register as the start value. The down coun + * ting starts when a command is loaded into the FIFO. The timer counts dow + * n every 4 DRAM cycles. When the counter reaches zero, the entry is poppe + * d from the FIFO. All the counters are frozen, if a C/A Parity or CRC err + * or occurs before the counter reaches zero. The counter is reset to 0, af + * ter all the commands in the FIFO are retried. Recommended(minimum) value + * s: - Only C/A Parity is enabled. RoundUp((PHY Command Latency(DRAM CLK) + * + CAL + RDIMM delay + tPAR_ALERT_ON.max + tPAR_UNKNOWN + PHY Alert Laten + * cy(DRAM CLK) + board delay) / 4) + 2 - Both C/A Parity and CRC is enable + * d/ Only CRC is enabled. RoundUp((PHY Command Latency(DRAM CLK) + CAL + R + * DIMM delay + WL + 5(BL10)+ tCRC_ALERT.max + PHY Alert Latency(DRAM CLK) + * + board delay) / 4) + 2 Note 1: All value (e.g. tPAR_ALERT_ON) should be + * in terms of DRAM Clock and round up Note 2: Board delay(Command/Alert_n + * ) should be considered. Note 3: Use the worst case(longer) value for PHY + * Latencies/Board delay Note 4: The Recommended values are minimum value + * to be set. For mode detail, See 'Calculation of FIFO Depth' section. Max + * value can be set to this register is defined below: - MEMC_BURST_LENGTH + * == 16 Full bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 + * Full bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Half b + * us Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-4 Half bus Mod + * e (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-6 Quarter bus Mode (C + * RC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-8 Quarter bus Mode (CRC= + * ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-12 - MEMC_BURST_LENGTH != 16 + * Full bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-1 Full + * bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mod + * e (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mode (CRC + * =ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Quarter bus Mode (CRC=OFF + * ) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-4 Quarter bus Mode (CRC=ON) Ma + * x value = UMCTL2_RETRY_CMD_FIFO_DEPTH-6 Values of 0, 1 and 2 are illegal + * . +*/ #undef DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_DEFVAL #undef DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_SHIFT #undef DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_MASK -#define DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_DEFVAL 0x0030050C -#define DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_SHIFT 0 -#define DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_MASK 0x0000003FU +#define DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_DEFVAL 0x0030050C +#define DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_SHIFT 0 +#define DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_MASK 0x0000003FU -/*If lower bit is enabled the SDRAM initialization routine is skipped. The upper bit decides what state the controller starts u - in when reset is removed - 00 - SDRAM Intialization routine is run after power-up - 01 - SDRAM Intialization routine is skip - ed after power-up. Controller starts up in Normal Mode - 11 - SDRAM Intialization routine is skipped after power-up. Controll - r starts up in Self-refresh Mode - 10 - SDRAM Intialization routine is run after power-up. Note: The only 2'b00 is supported - or LPDDR4 in this version of the uMCTL2.*/ +/* +* If lower bit is enabled the SDRAM initialization routine is skipped. The + * upper bit decides what state the controller starts up in when reset is + * removed - 00 - SDRAM Intialization routine is run after power-up - 01 - + * SDRAM Intialization routine is skipped after power-up. Controller starts + * up in Normal Mode - 11 - SDRAM Intialization routine is skipped after p + * ower-up. Controller starts up in Self-refresh Mode - 10 - SDRAM Intializ + * ation routine is run after power-up. Note: The only 2'b00 is supported f + * or LPDDR4 in this version of the uMCTL2. +*/ #undef DDRC_INIT0_SKIP_DRAM_INIT_DEFVAL #undef DDRC_INIT0_SKIP_DRAM_INIT_SHIFT #undef DDRC_INIT0_SKIP_DRAM_INIT_MASK -#define DDRC_INIT0_SKIP_DRAM_INIT_DEFVAL 0x0002004E -#define DDRC_INIT0_SKIP_DRAM_INIT_SHIFT 30 -#define DDRC_INIT0_SKIP_DRAM_INIT_MASK 0xC0000000U +#define DDRC_INIT0_SKIP_DRAM_INIT_DEFVAL 0x0002004E +#define DDRC_INIT0_SKIP_DRAM_INIT_SHIFT 30 +#define DDRC_INIT0_SKIP_DRAM_INIT_MASK 0xC0000000U -/*Cycles to wait after driving CKE high to start the SDRAM initialization sequence. Unit: 1024 clocks. DDR2 typically requires - 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2/LPDDR3 typically requires this to be pr - grammed for a delay of 200 us. LPDDR4 typically requires this to be programmed for a delay of 2 us. For configurations with M - MC_FREQ_RATIO=2, program this to JEDEC spec value divided by 2, and round it up to next integer value.*/ +/* +* Cycles to wait after driving CKE high to start the SDRAM initialization + * sequence. Unit: 1024 clocks. DDR2 typically requires a 400 ns delay, req + * uiring this value to be programmed to 2 at all clock speeds. LPDDR2/LPDD + * R3 typically requires this to be programmed for a delay of 200 us. LPDDR + * 4 typically requires this to be programmed for a delay of 2 us. For conf + * igurations with MEMC_FREQ_RATIO=2, program this to JEDEC spec value divi + * ded by 2, and round it up to next integer value. +*/ #undef DDRC_INIT0_POST_CKE_X1024_DEFVAL #undef DDRC_INIT0_POST_CKE_X1024_SHIFT #undef DDRC_INIT0_POST_CKE_X1024_MASK -#define DDRC_INIT0_POST_CKE_X1024_DEFVAL 0x0002004E -#define DDRC_INIT0_POST_CKE_X1024_SHIFT 16 -#define DDRC_INIT0_POST_CKE_X1024_MASK 0x03FF0000U +#define DDRC_INIT0_POST_CKE_X1024_DEFVAL 0x0002004E +#define DDRC_INIT0_POST_CKE_X1024_SHIFT 16 +#define DDRC_INIT0_POST_CKE_X1024_MASK 0x03FF0000U -/*Cycles to wait after reset before driving CKE high to start the SDRAM initialization sequence. Unit: 1024 clock cycles. DDR2 - pecifications typically require this to be programmed for a delay of >= 200 us. LPDDR2/LPDDR3: tINIT1 of 100 ns (min) LPDDR4: - tINIT3 of 2 ms (min) For configurations with MEMC_FREQ_RATIO=2, program this to JEDEC spec value divided by 2, and round it u - to next integer value.*/ +/* +* Cycles to wait after reset before driving CKE high to start the SDRAM in + * itialization sequence. Unit: 1024 clock cycles. DDR2 specifications typi + * cally require this to be programmed for a delay of >= 200 us. LPDDR2/LPD + * DR3: tINIT1 of 100 ns (min) LPDDR4: tINIT3 of 2 ms (min) For configurati + * ons with MEMC_FREQ_RATIO=2, program this to JEDEC spec value divided by + * 2, and round it up to next integer value. +*/ #undef DDRC_INIT0_PRE_CKE_X1024_DEFVAL #undef DDRC_INIT0_PRE_CKE_X1024_SHIFT #undef DDRC_INIT0_PRE_CKE_X1024_MASK -#define DDRC_INIT0_PRE_CKE_X1024_DEFVAL 0x0002004E -#define DDRC_INIT0_PRE_CKE_X1024_SHIFT 0 -#define DDRC_INIT0_PRE_CKE_X1024_MASK 0x00000FFFU +#define DDRC_INIT0_PRE_CKE_X1024_DEFVAL 0x0002004E +#define DDRC_INIT0_PRE_CKE_X1024_SHIFT 0 +#define DDRC_INIT0_PRE_CKE_X1024_MASK 0x00000FFFU -/*Number of cycles to assert SDRAM reset signal during init sequence. This is only present for designs supporting DDR3, DDR4 or - LPDDR4 devices. For use with a DDR PHY, this should be set to a minimum of 1*/ +/* +* Number of cycles to assert SDRAM reset signal during init sequence. This + * is only present for designs supporting DDR3, DDR4 or LPDDR4 devices. Fo + * r use with a DDR PHY, this should be set to a minimum of 1 +*/ #undef DDRC_INIT1_DRAM_RSTN_X1024_DEFVAL #undef DDRC_INIT1_DRAM_RSTN_X1024_SHIFT #undef DDRC_INIT1_DRAM_RSTN_X1024_MASK -#define DDRC_INIT1_DRAM_RSTN_X1024_DEFVAL 0x00000000 -#define DDRC_INIT1_DRAM_RSTN_X1024_SHIFT 16 -#define DDRC_INIT1_DRAM_RSTN_X1024_MASK 0x01FF0000U +#define DDRC_INIT1_DRAM_RSTN_X1024_DEFVAL 0x00000000 +#define DDRC_INIT1_DRAM_RSTN_X1024_SHIFT 16 +#define DDRC_INIT1_DRAM_RSTN_X1024_MASK 0x01FF0000U -/*Cycles to wait after completing the SDRAM initialization sequence before starting the dynamic scheduler. Unit: Counts of a gl - bal timer that pulses every 32 clock cycles. There is no known specific requirement for this; it may be set to zero.*/ +/* +* Cycles to wait after completing the SDRAM initialization sequence before + * starting the dynamic scheduler. Unit: Counts of a global timer that pul + * ses every 32 clock cycles. There is no known specific requirement for th + * is; it may be set to zero. +*/ #undef DDRC_INIT1_FINAL_WAIT_X32_DEFVAL #undef DDRC_INIT1_FINAL_WAIT_X32_SHIFT #undef DDRC_INIT1_FINAL_WAIT_X32_MASK -#define DDRC_INIT1_FINAL_WAIT_X32_DEFVAL 0x00000000 -#define DDRC_INIT1_FINAL_WAIT_X32_SHIFT 8 -#define DDRC_INIT1_FINAL_WAIT_X32_MASK 0x00007F00U +#define DDRC_INIT1_FINAL_WAIT_X32_DEFVAL 0x00000000 +#define DDRC_INIT1_FINAL_WAIT_X32_SHIFT 8 +#define DDRC_INIT1_FINAL_WAIT_X32_MASK 0x00007F00U -/*Wait period before driving the OCD complete command to SDRAM. Unit: Counts of a global timer that pulses every 32 clock cycle - . There is no known specific requirement for this; it may be set to zero.*/ +/* +* Wait period before driving the OCD complete command to SDRAM. Unit: Coun + * ts of a global timer that pulses every 32 clock cycles. There is no know + * n specific requirement for this; it may be set to zero. +*/ #undef DDRC_INIT1_PRE_OCD_X32_DEFVAL #undef DDRC_INIT1_PRE_OCD_X32_SHIFT #undef DDRC_INIT1_PRE_OCD_X32_MASK -#define DDRC_INIT1_PRE_OCD_X32_DEFVAL 0x00000000 -#define DDRC_INIT1_PRE_OCD_X32_SHIFT 0 -#define DDRC_INIT1_PRE_OCD_X32_MASK 0x0000000FU +#define DDRC_INIT1_PRE_OCD_X32_DEFVAL 0x00000000 +#define DDRC_INIT1_PRE_OCD_X32_SHIFT 0 +#define DDRC_INIT1_PRE_OCD_X32_MASK 0x0000000FU -/*Idle time after the reset command, tINIT4. Present only in designs configured to support LPDDR2. Unit: 32 clock cycles.*/ +/* +* Idle time after the reset command, tINIT4. Present only in designs confi + * gured to support LPDDR2. Unit: 32 clock cycles. +*/ #undef DDRC_INIT2_IDLE_AFTER_RESET_X32_DEFVAL #undef DDRC_INIT2_IDLE_AFTER_RESET_X32_SHIFT #undef DDRC_INIT2_IDLE_AFTER_RESET_X32_MASK -#define DDRC_INIT2_IDLE_AFTER_RESET_X32_DEFVAL 0x00000D05 -#define DDRC_INIT2_IDLE_AFTER_RESET_X32_SHIFT 8 -#define DDRC_INIT2_IDLE_AFTER_RESET_X32_MASK 0x0000FF00U +#define DDRC_INIT2_IDLE_AFTER_RESET_X32_DEFVAL 0x00000D05 +#define DDRC_INIT2_IDLE_AFTER_RESET_X32_SHIFT 8 +#define DDRC_INIT2_IDLE_AFTER_RESET_X32_MASK 0x0000FF00U -/*Time to wait after the first CKE high, tINIT2. Present only in designs configured to support LPDDR2/LPDDR3. Unit: 1 clock cyc - e. LPDDR2/LPDDR3 typically requires 5 x tCK delay.*/ +/* +* Time to wait after the first CKE high, tINIT2. Present only in designs c + * onfigured to support LPDDR2/LPDDR3. Unit: 1 clock cycle. LPDDR2/LPDDR3 t + * ypically requires 5 x tCK delay. +*/ #undef DDRC_INIT2_MIN_STABLE_CLOCK_X1_DEFVAL #undef DDRC_INIT2_MIN_STABLE_CLOCK_X1_SHIFT #undef DDRC_INIT2_MIN_STABLE_CLOCK_X1_MASK -#define DDRC_INIT2_MIN_STABLE_CLOCK_X1_DEFVAL 0x00000D05 -#define DDRC_INIT2_MIN_STABLE_CLOCK_X1_SHIFT 0 -#define DDRC_INIT2_MIN_STABLE_CLOCK_X1_MASK 0x0000000FU +#define DDRC_INIT2_MIN_STABLE_CLOCK_X1_DEFVAL 0x00000D05 +#define DDRC_INIT2_MIN_STABLE_CLOCK_X1_SHIFT 0 +#define DDRC_INIT2_MIN_STABLE_CLOCK_X1_MASK 0x0000000FU -/*DDR2: Value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The uMCTL2 sets this bit appropriately - DDR3/DDR4: Value loaded into MR0 register. mDDR: Value to write to MR register. LPDDR2/LPDDR3/LPDDR4 - Value to write to MR1 - register*/ +/* +* DDR2: Value to write to MR register. Bit 8 is for DLL and the setting he + * re is ignored. The uMCTL2 sets this bit appropriately. DDR3/DDR4: Value + * loaded into MR0 register. mDDR: Value to write to MR register. LPDDR2/LP + * DDR3/LPDDR4 - Value to write to MR1 register +*/ #undef DDRC_INIT3_MR_DEFVAL #undef DDRC_INIT3_MR_SHIFT #undef DDRC_INIT3_MR_MASK -#define DDRC_INIT3_MR_DEFVAL 0x00000510 -#define DDRC_INIT3_MR_SHIFT 16 -#define DDRC_INIT3_MR_MASK 0xFFFF0000U +#define DDRC_INIT3_MR_DEFVAL 0x00000510 +#define DDRC_INIT3_MR_SHIFT 16 +#define DDRC_INIT3_MR_MASK 0xFFFF0000U -/*DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setting in this register is ignored. The uMCTL2 sets those - bits appropriately. DDR3/DDR4: Value to write to MR1 register Set bit 7 to 0. If PHY-evaluation mode training is enabled, thi - bit is set appropriately by the uMCTL2 during write leveling. mDDR: Value to write to EMR register. LPDDR2/LPDDR3/LPDDR4 - V - lue to write to MR2 register*/ +/* +* DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setti + * ng in this register is ignored. The uMCTL2 sets those bits appropriately + * . DDR3/DDR4: Value to write to MR1 register Set bit 7 to 0. If PHY-evalu + * ation mode training is enabled, this bit is set appropriately by the uMC + * TL2 during write leveling. mDDR: Value to write to EMR register. LPDDR2/ + * LPDDR3/LPDDR4 - Value to write to MR2 register +*/ #undef DDRC_INIT3_EMR_DEFVAL #undef DDRC_INIT3_EMR_SHIFT #undef DDRC_INIT3_EMR_MASK -#define DDRC_INIT3_EMR_DEFVAL 0x00000510 -#define DDRC_INIT3_EMR_SHIFT 0 -#define DDRC_INIT3_EMR_MASK 0x0000FFFFU +#define DDRC_INIT3_EMR_DEFVAL 0x00000510 +#define DDRC_INIT3_EMR_SHIFT 0 +#define DDRC_INIT3_EMR_MASK 0x0000FFFFU -/*DDR2: Value to write to EMR2 register. DDR3/DDR4: Value to write to MR2 register LPDDR2/LPDDR3/LPDDR4: Value to write to MR3 - egister mDDR: Unused*/ +/* +* DDR2: Value to write to EMR2 register. DDR3/DDR4: Value to write to MR2 + * register LPDDR2/LPDDR3/LPDDR4: Value to write to MR3 register mDDR: Unus + * ed +*/ #undef DDRC_INIT4_EMR2_DEFVAL #undef DDRC_INIT4_EMR2_SHIFT #undef DDRC_INIT4_EMR2_MASK -#define DDRC_INIT4_EMR2_DEFVAL 0x00000000 -#define DDRC_INIT4_EMR2_SHIFT 16 -#define DDRC_INIT4_EMR2_MASK 0xFFFF0000U +#define DDRC_INIT4_EMR2_DEFVAL 0x00000000 +#define DDRC_INIT4_EMR2_SHIFT 16 +#define DDRC_INIT4_EMR2_MASK 0xFFFF0000U -/*DDR2: Value to write to EMR3 register. DDR3/DDR4: Value to write to MR3 register mDDR/LPDDR2/LPDDR3: Unused LPDDR4: Value to - rite to MR13 register*/ +/* +* DDR2: Value to write to EMR3 register. DDR3/DDR4: Value to write to MR3 + * register mDDR/LPDDR2/LPDDR3: Unused LPDDR4: Value to write to MR13 regis + * ter +*/ #undef DDRC_INIT4_EMR3_DEFVAL #undef DDRC_INIT4_EMR3_SHIFT #undef DDRC_INIT4_EMR3_MASK -#define DDRC_INIT4_EMR3_DEFVAL 0x00000000 -#define DDRC_INIT4_EMR3_SHIFT 0 -#define DDRC_INIT4_EMR3_MASK 0x0000FFFFU +#define DDRC_INIT4_EMR3_DEFVAL 0x00000000 +#define DDRC_INIT4_EMR3_SHIFT 0 +#define DDRC_INIT4_EMR3_MASK 0x0000FFFFU -/*ZQ initial calibration, tZQINIT. Present only in designs configured to support DDR3 or DDR4 or LPDDR2/LPDDR3. Unit: 32 clock - ycles. DDR3 typically requires 512 clocks. DDR4 requires 1024 clocks. LPDDR2/LPDDR3 requires 1 us.*/ +/* +* ZQ initial calibration, tZQINIT. Present only in designs configured to s + * upport DDR3 or DDR4 or LPDDR2/LPDDR3. Unit: 32 clock cycles. DDR3 typica + * lly requires 512 clocks. DDR4 requires 1024 clocks. LPDDR2/LPDDR3 requir + * es 1 us. +*/ #undef DDRC_INIT5_DEV_ZQINIT_X32_DEFVAL #undef DDRC_INIT5_DEV_ZQINIT_X32_SHIFT #undef DDRC_INIT5_DEV_ZQINIT_X32_MASK -#define DDRC_INIT5_DEV_ZQINIT_X32_DEFVAL 0x00100004 -#define DDRC_INIT5_DEV_ZQINIT_X32_SHIFT 16 -#define DDRC_INIT5_DEV_ZQINIT_X32_MASK 0x00FF0000U +#define DDRC_INIT5_DEV_ZQINIT_X32_DEFVAL 0x00100004 +#define DDRC_INIT5_DEV_ZQINIT_X32_SHIFT 16 +#define DDRC_INIT5_DEV_ZQINIT_X32_MASK 0x00FF0000U -/*Maximum duration of the auto initialization, tINIT5. Present only in designs configured to support LPDDR2/LPDDR3. LPDDR2/LPDD - 3 typically requires 10 us.*/ +/* +* Maximum duration of the auto initialization, tINIT5. Present only in des + * igns configured to support LPDDR2/LPDDR3. LPDDR2/LPDDR3 typically requir + * es 10 us. +*/ #undef DDRC_INIT5_MAX_AUTO_INIT_X1024_DEFVAL #undef DDRC_INIT5_MAX_AUTO_INIT_X1024_SHIFT #undef DDRC_INIT5_MAX_AUTO_INIT_X1024_MASK -#define DDRC_INIT5_MAX_AUTO_INIT_X1024_DEFVAL 0x00100004 -#define DDRC_INIT5_MAX_AUTO_INIT_X1024_SHIFT 0 -#define DDRC_INIT5_MAX_AUTO_INIT_X1024_MASK 0x000003FFU +#define DDRC_INIT5_MAX_AUTO_INIT_X1024_DEFVAL 0x00100004 +#define DDRC_INIT5_MAX_AUTO_INIT_X1024_SHIFT 0 +#define DDRC_INIT5_MAX_AUTO_INIT_X1024_MASK 0x000003FFU -/*DDR4- Value to be loaded into SDRAM MR4 registers. Used in DDR4 designs only.*/ +/* +* DDR4- Value to be loaded into SDRAM MR4 registers. Used in DDR4 designs + * only. +*/ #undef DDRC_INIT6_MR4_DEFVAL #undef DDRC_INIT6_MR4_SHIFT #undef DDRC_INIT6_MR4_MASK -#define DDRC_INIT6_MR4_DEFVAL 0x00000000 -#define DDRC_INIT6_MR4_SHIFT 16 -#define DDRC_INIT6_MR4_MASK 0xFFFF0000U +#define DDRC_INIT6_MR4_DEFVAL 0x00000000 +#define DDRC_INIT6_MR4_SHIFT 16 +#define DDRC_INIT6_MR4_MASK 0xFFFF0000U -/*DDR4- Value to be loaded into SDRAM MR5 registers. Used in DDR4 designs only.*/ +/* +* DDR4- Value to be loaded into SDRAM MR5 registers. Used in DDR4 designs + * only. +*/ #undef DDRC_INIT6_MR5_DEFVAL #undef DDRC_INIT6_MR5_SHIFT #undef DDRC_INIT6_MR5_MASK -#define DDRC_INIT6_MR5_DEFVAL 0x00000000 -#define DDRC_INIT6_MR5_SHIFT 0 -#define DDRC_INIT6_MR5_MASK 0x0000FFFFU +#define DDRC_INIT6_MR5_DEFVAL 0x00000000 +#define DDRC_INIT6_MR5_SHIFT 0 +#define DDRC_INIT6_MR5_MASK 0x0000FFFFU -/*DDR4- Value to be loaded into SDRAM MR6 registers. Used in DDR4 designs only.*/ +/* +* DDR4- Value to be loaded into SDRAM MR6 registers. Used in DDR4 designs + * only. +*/ #undef DDRC_INIT7_MR6_DEFVAL #undef DDRC_INIT7_MR6_SHIFT #undef DDRC_INIT7_MR6_MASK -#define DDRC_INIT7_MR6_DEFVAL -#define DDRC_INIT7_MR6_SHIFT 16 -#define DDRC_INIT7_MR6_MASK 0xFFFF0000U +#define DDRC_INIT7_MR6_DEFVAL +#define DDRC_INIT7_MR6_SHIFT 16 +#define DDRC_INIT7_MR6_MASK 0xFFFF0000U -/*Disabling Address Mirroring for BG bits. When this is set to 1, BG0 and BG1 are NOT swapped even if Address Mirroring is enab - ed. This will be required for DDR4 DIMMs with x16 devices. - 1 - BG0 and BG1 are NOT swapped. - 0 - BG0 and BG1 are swapped i - address mirroring is enabled.*/ +/* +* Disabling Address Mirroring for BG bits. When this is set to 1, BG0 and + * BG1 are NOT swapped even if Address Mirroring is enabled. This will be r + * equired for DDR4 DIMMs with x16 devices. - 1 - BG0 and BG1 are NOT swapp + * ed. - 0 - BG0 and BG1 are swapped if address mirroring is enabled. +*/ #undef DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_DEFVAL #undef DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_SHIFT #undef DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_MASK -#define DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_DEFVAL 0x00000000 -#define DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_SHIFT 5 -#define DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_MASK 0x00000020U +#define DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_DEFVAL 0x00000000 +#define DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_SHIFT 5 +#define DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_MASK 0x00000020U -/*Enable for BG1 bit of MRS command. BG1 bit of the mode register address is specified as RFU (Reserved for Future Use) and mus - be programmed to 0 during MRS. In case where DRAMs which do not have BG1 are attached and both the CA parity and the Output - nversion are enabled, this must be set to 0, so that the calculation of CA parity will not include BG1 bit. Note: This has no - effect on the address of any other memory accesses, or of software-driven mode register accesses. If address mirroring is ena - led, this is applied to BG1 of even ranks and BG0 of odd ranks. - 1 - Enabled - 0 - Disabled*/ +/* +* Enable for BG1 bit of MRS command. BG1 bit of the mode register address + * is specified as RFU (Reserved for Future Use) and must be programmed to + * 0 during MRS. In case where DRAMs which do not have BG1 are attached and + * both the CA parity and the Output Inversion are enabled, this must be s + * et to 0, so that the calculation of CA parity will not include BG1 bit. + * Note: This has no effect on the address of any other memory accesses, or + * of software-driven mode register accesses. If address mirroring is enab + * led, this is applied to BG1 of even ranks and BG0 of odd ranks. - 1 - En + * abled - 0 - Disabled +*/ #undef DDRC_DIMMCTL_MRS_BG1_EN_DEFVAL #undef DDRC_DIMMCTL_MRS_BG1_EN_SHIFT #undef DDRC_DIMMCTL_MRS_BG1_EN_MASK -#define DDRC_DIMMCTL_MRS_BG1_EN_DEFVAL 0x00000000 -#define DDRC_DIMMCTL_MRS_BG1_EN_SHIFT 4 -#define DDRC_DIMMCTL_MRS_BG1_EN_MASK 0x00000010U +#define DDRC_DIMMCTL_MRS_BG1_EN_DEFVAL 0x00000000 +#define DDRC_DIMMCTL_MRS_BG1_EN_SHIFT 4 +#define DDRC_DIMMCTL_MRS_BG1_EN_MASK 0x00000010U -/*Enable for A17 bit of MRS command. A17 bit of the mode register address is specified as RFU (Reserved for Future Use) and mus - be programmed to 0 during MRS. In case where DRAMs which do not have A17 are attached and the Output Inversion are enabled, - his must be set to 0, so that the calculation of CA parity will not include A17 bit. Note: This has no effect on the address - f any other memory accesses, or of software-driven mode register accesses. - 1 - Enabled - 0 - Disabled*/ +/* +* Enable for A17 bit of MRS command. A17 bit of the mode register address + * is specified as RFU (Reserved for Future Use) and must be programmed to + * 0 during MRS. In case where DRAMs which do not have A17 are attached and + * the Output Inversion are enabled, this must be set to 0, so that the ca + * lculation of CA parity will not include A17 bit. Note: This has no effec + * t on the address of any other memory accesses, or of software-driven mod + * e register accesses. - 1 - Enabled - 0 - Disabled +*/ #undef DDRC_DIMMCTL_MRS_A17_EN_DEFVAL #undef DDRC_DIMMCTL_MRS_A17_EN_SHIFT #undef DDRC_DIMMCTL_MRS_A17_EN_MASK -#define DDRC_DIMMCTL_MRS_A17_EN_DEFVAL 0x00000000 -#define DDRC_DIMMCTL_MRS_A17_EN_SHIFT 3 -#define DDRC_DIMMCTL_MRS_A17_EN_MASK 0x00000008U +#define DDRC_DIMMCTL_MRS_A17_EN_DEFVAL 0x00000000 +#define DDRC_DIMMCTL_MRS_A17_EN_SHIFT 3 +#define DDRC_DIMMCTL_MRS_A17_EN_MASK 0x00000008U -/*Output Inversion Enable (for DDR4 RDIMM implementations only). DDR4 RDIMM implements the Output Inversion feature by default, - which means that the following address, bank address and bank group bits of B-side DRAMs are inverted: A3-A9, A11, A13, A17, - A0-BA1, BG0-BG1. Setting this bit ensures that, for mode register accesses generated by the uMCTL2 during the automatic initi - lization routine and enabling of a particular DDR4 feature, separate A-side and B-side mode register accesses are generated. - or B-side mode register accesses, these bits are inverted within the uMCTL2 to compensate for this RDIMM inversion. Note: Thi - has no effect on the address of any other memory accesses, or of software-driven mode register accesses. - 1 - Implement out - ut inversion for B-side DRAMs. - 0 - Do not implement output inversion for B-side DRAMs.*/ +/* +* Output Inversion Enable (for DDR4 RDIMM implementations only). DDR4 RDIM + * M implements the Output Inversion feature by default, which means that t + * he following address, bank address and bank group bits of B-side DRAMs a + * re inverted: A3-A9, A11, A13, A17, BA0-BA1, BG0-BG1. Setting this bit en + * sures that, for mode register accesses generated by the uMCTL2 during th + * e automatic initialization routine and enabling of a particular DDR4 fea + * ture, separate A-side and B-side mode register accesses are generated. F + * or B-side mode register accesses, these bits are inverted within the uMC + * TL2 to compensate for this RDIMM inversion. Note: This has no effect on + * the address of any other memory accesses, or of software-driven mode reg + * ister accesses. - 1 - Implement output inversion for B-side DRAMs. - 0 - + * Do not implement output inversion for B-side DRAMs. +*/ #undef DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_DEFVAL #undef DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_SHIFT #undef DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_MASK -#define DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_DEFVAL 0x00000000 -#define DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_SHIFT 2 -#define DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_MASK 0x00000004U +#define DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_DEFVAL 0x00000000 +#define DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_SHIFT 2 +#define DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_MASK 0x00000004U -/*Address Mirroring Enable (for multi-rank UDIMM implementations and multi-rank DDR4 RDIMM implementations). Some UDIMMs and DD - 4 RDIMMs implement address mirroring for odd ranks, which means that the following address, bank address and bank group bits - re swapped: (A3, A4), (A5, A6), (A7, A8), (BA0, BA1) and also (A11, A13), (BG0, BG1) for the DDR4. Setting this bit ensures t - at, for mode register accesses during the automatic initialization routine, these bits are swapped within the uMCTL2 to compe - sate for this UDIMM/RDIMM swapping. In addition to the automatic initialization routine, in case of DDR4 UDIMM/RDIMM, they ar - swapped during the automatic MRS access to enable/disable of a particular DDR4 feature. Note: This has no effect on the addr - ss of any other memory accesses, or of software-driven mode register accesses. This is not supported for mDDR, LPDDR2, LPDDR3 - or LPDDR4 SDRAMs. Note: In case of x16 DDR4 DIMMs, BG1 output of MRS for the odd ranks is same as BG0 because BG1 is invalid, - hence dimm_dis_bg_mirroring register must be set to 1. - 1 - For odd ranks, implement address mirroring for MRS commands to d - ring initialization and for any automatic DDR4 MRS commands (to be used if UDIMM/RDIMM implements address mirroring) - 0 - Do - not implement address mirroring*/ +/* +* Address Mirroring Enable (for multi-rank UDIMM implementations and multi + * -rank DDR4 RDIMM implementations). Some UDIMMs and DDR4 RDIMMs implement + * address mirroring for odd ranks, which means that the following address + * , bank address and bank group bits are swapped: (A3, A4), (A5, A6), (A7, + * A8), (BA0, BA1) and also (A11, A13), (BG0, BG1) for the DDR4. Setting t + * his bit ensures that, for mode register accesses during the automatic in + * itialization routine, these bits are swapped within the uMCTL2 to compen + * sate for this UDIMM/RDIMM swapping. In addition to the automatic initial + * ization routine, in case of DDR4 UDIMM/RDIMM, they are swapped during th + * e automatic MRS access to enable/disable of a particular DDR4 feature. N + * ote: This has no effect on the address of any other memory accesses, or + * of software-driven mode register accesses. This is not supported for mDD + * R, LPDDR2, LPDDR3 or LPDDR4 SDRAMs. Note: In case of x16 DDR4 DIMMs, BG1 + * output of MRS for the odd ranks is same as BG0 because BG1 is invalid, + * hence dimm_dis_bg_mirroring register must be set to 1. - 1 - For odd ran + * ks, implement address mirroring for MRS commands to during initializatio + * n and for any automatic DDR4 MRS commands (to be used if UDIMM/RDIMM imp + * lements address mirroring) - 0 - Do not implement address mirroring +*/ #undef DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_DEFVAL #undef DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_SHIFT #undef DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_MASK -#define DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_DEFVAL 0x00000000 -#define DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_SHIFT 1 -#define DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_MASK 0x00000002U +#define DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_DEFVAL 0x00000000 +#define DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_SHIFT 1 +#define DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_MASK 0x00000002U -/*Staggering enable for multi-rank accesses (for multi-rank UDIMM and RDIMM implementations only). This is not supported for mD - R, LPDDR2, LPDDR3 or LPDDR4 SDRAMs. Note: Even if this bit is set it does not take care of software driven MR commands (via M - CTRL0/MRCTRL1), where software is responsible to send them to seperate ranks as appropriate. - 1 - (DDR4) Send MRS commands t - each ranks seperately - 1 - (non-DDR4) Send all commands to even and odd ranks seperately - 0 - Do not stagger accesses*/ +/* +* Staggering enable for multi-rank accesses (for multi-rank UDIMM and RDIM + * M implementations only). This is not supported for mDDR, LPDDR2, LPDDR3 + * or LPDDR4 SDRAMs. Note: Even if this bit is set it does not take care of + * software driven MR commands (via MRCTRL0/MRCTRL1), where software is re + * sponsible to send them to seperate ranks as appropriate. - 1 - (DDR4) Se + * nd MRS commands to each ranks seperately - 1 - (non-DDR4) Send all comma + * nds to even and odd ranks seperately - 0 - Do not stagger accesses +*/ #undef DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_DEFVAL #undef DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_SHIFT #undef DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_MASK -#define DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_DEFVAL 0x00000000 -#define DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_SHIFT 0 -#define DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_MASK 0x00000001U +#define DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_DEFVAL 0x00000000 +#define DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_SHIFT 0 +#define DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_MASK 0x00000001U -/*Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecuti - e writes to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This value should c - nsider both PHY requirement and ODT requirement. - PHY requirement: tphy_wrcsgap + 1 (see PHY databook for value of tphy_wrcs - ap) If CRC feature is enabled, should be increased by 1. If write preamble is set to 2tCK(DDR4/LPDDR4 only), should be increa - ed by 1. If write postamble is set to 1.5tCK(LPDDR4 only), should be increased by 1. - ODT requirement: The value programmed - n this register takes care of the ODT switch off timing requirement when switching ranks during writes. For LPDDR4, the requi - ement is ODTLoff - ODTLon - BL/2 + 1 For configurations with MEMC_FREQ_RATIO=1, program this to the larger of PHY requirement - or ODT requirement. For configurations with MEMC_FREQ_RATIO=2, program this to the larger value divided by two and round it u - to the next integer.*/ +/* +* Only present for multi-rank configurations. Indicates the number of cloc + * ks of gap in data responses when performing consecutive writes to differ + * ent ranks. This is used to switch the delays in the PHY to match the ran + * k requirements. This value should consider both PHY requirement and ODT + * requirement. - PHY requirement: tphy_wrcsgap + 1 (see PHY databook for v + * alue of tphy_wrcsgap) If CRC feature is enabled, should be increased by + * 1. If write preamble is set to 2tCK(DDR4/LPDDR4 only), should be increas + * ed by 1. If write postamble is set to 1.5tCK(LPDDR4 only), should be inc + * reased by 1. - ODT requirement: The value programmed in this register ta + * kes care of the ODT switch off timing requirement when switching ranks d + * uring writes. For LPDDR4, the requirement is ODTLoff - ODTLon - BL/2 + 1 + * For configurations with MEMC_FREQ_RATIO=1, program this to the larger o + * f PHY requirement or ODT requirement. For configurations with MEMC_FREQ_ + * RATIO=2, program this to the larger value divided by two and round it up + * to the next integer. +*/ #undef DDRC_RANKCTL_DIFF_RANK_WR_GAP_DEFVAL #undef DDRC_RANKCTL_DIFF_RANK_WR_GAP_SHIFT #undef DDRC_RANKCTL_DIFF_RANK_WR_GAP_MASK -#define DDRC_RANKCTL_DIFF_RANK_WR_GAP_DEFVAL 0x0000066F -#define DDRC_RANKCTL_DIFF_RANK_WR_GAP_SHIFT 8 -#define DDRC_RANKCTL_DIFF_RANK_WR_GAP_MASK 0x00000F00U +#define DDRC_RANKCTL_DIFF_RANK_WR_GAP_DEFVAL 0x0000066F +#define DDRC_RANKCTL_DIFF_RANK_WR_GAP_SHIFT 8 +#define DDRC_RANKCTL_DIFF_RANK_WR_GAP_MASK 0x00000F00U -/*Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecuti - e reads to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This value should co - sider both PHY requirement and ODT requirement. - PHY requirement: tphy_rdcsgap + 1 (see PHY databook for value of tphy_rdcsg - p) If read preamble is set to 2tCK(DDR4/LPDDR4 only), should be increased by 1. If read postamble is set to 1.5tCK(LPDDR4 onl - ), should be increased by 1. - ODT requirement: The value programmed in this register takes care of the ODT switch off timing - requirement when switching ranks during reads. For configurations with MEMC_FREQ_RATIO=1, program this to the larger of PHY r - quirement or ODT requirement. For configurations with MEMC_FREQ_RATIO=2, program this to the larger value divided by two and - ound it up to the next integer.*/ +/* +* Only present for multi-rank configurations. Indicates the number of cloc + * ks of gap in data responses when performing consecutive reads to differe + * nt ranks. This is used to switch the delays in the PHY to match the rank + * requirements. This value should consider both PHY requirement and ODT r + * equirement. - PHY requirement: tphy_rdcsgap + 1 (see PHY databook for va + * lue of tphy_rdcsgap) If read preamble is set to 2tCK(DDR4/LPDDR4 only), + * should be increased by 1. If read postamble is set to 1.5tCK(LPDDR4 only + * ), should be increased by 1. - ODT requirement: The value programmed in + * this register takes care of the ODT switch off timing requirement when s + * witching ranks during reads. For configurations with MEMC_FREQ_RATIO=1, + * program this to the larger of PHY requirement or ODT requirement. For co + * nfigurations with MEMC_FREQ_RATIO=2, program this to the larger value di + * vided by two and round it up to the next integer. +*/ #undef DDRC_RANKCTL_DIFF_RANK_RD_GAP_DEFVAL #undef DDRC_RANKCTL_DIFF_RANK_RD_GAP_SHIFT #undef DDRC_RANKCTL_DIFF_RANK_RD_GAP_MASK -#define DDRC_RANKCTL_DIFF_RANK_RD_GAP_DEFVAL 0x0000066F -#define DDRC_RANKCTL_DIFF_RANK_RD_GAP_SHIFT 4 -#define DDRC_RANKCTL_DIFF_RANK_RD_GAP_MASK 0x000000F0U +#define DDRC_RANKCTL_DIFF_RANK_RD_GAP_DEFVAL 0x0000066F +#define DDRC_RANKCTL_DIFF_RANK_RD_GAP_SHIFT 4 +#define DDRC_RANKCTL_DIFF_RANK_RD_GAP_MASK 0x000000F0U -/*Only present for multi-rank configurations. Background: Reads to the same rank can be performed back-to-back. Reads to differ - nt ranks require additional gap dictated by the register RANKCTL.diff_rank_rd_gap. This is to avoid possible data bus content - on as well as to give PHY enough time to switch the delay when changing ranks. The uMCTL2 arbitrates for bus access on a cycl - -by-cycle basis; therefore after a read is scheduled, there are few clock cycles (determined by the value on RANKCTL.diff_ran - _rd_gap register) in which only reads from the same rank are eligible to be scheduled. This prevents reads from other ranks f - om having fair access to the data bus. This parameter represents the maximum number of reads that can be scheduled consecutiv - ly to the same rank. After this number is reached, a delay equal to RANKCTL.diff_rank_rd_gap is inserted by the scheduler to - llow all ranks a fair opportunity to be scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fair - ess. This feature can be DISABLED by setting this register to 0. When set to 0, the Controller will stay on the same rank as - ong as commands are available for it. Minimum programmable value is 0 (feature disabled) and maximum programmable value is 0x - . FOR PERFORMANCE ONLY.*/ +/* +* Only present for multi-rank configurations. Background: Reads to the sam + * e rank can be performed back-to-back. Reads to different ranks require a + * dditional gap dictated by the register RANKCTL.diff_rank_rd_gap. This is + * to avoid possible data bus contention as well as to give PHY enough tim + * e to switch the delay when changing ranks. The uMCTL2 arbitrates for bus + * access on a cycle-by-cycle basis; therefore after a read is scheduled, + * there are few clock cycles (determined by the value on RANKCTL.diff_rank + * _rd_gap register) in which only reads from the same rank are eligible to + * be scheduled. This prevents reads from other ranks from having fair acc + * ess to the data bus. This parameter represents the maximum number of rea + * ds that can be scheduled consecutively to the same rank. After this numb + * er is reached, a delay equal to RANKCTL.diff_rank_rd_gap is inserted by + * the scheduler to allow all ranks a fair opportunity to be scheduled. Hig + * her numbers increase bandwidth utilization, lower numbers increase fairn + * ess. This feature can be DISABLED by setting this register to 0. When se + * t to 0, the Controller will stay on the same rank as long as commands ar + * e available for it. Minimum programmable value is 0 (feature disabled) a + * nd maximum programmable value is 0xF. FOR PERFORMANCE ONLY. +*/ #undef DDRC_RANKCTL_MAX_RANK_RD_DEFVAL #undef DDRC_RANKCTL_MAX_RANK_RD_SHIFT #undef DDRC_RANKCTL_MAX_RANK_RD_MASK -#define DDRC_RANKCTL_MAX_RANK_RD_DEFVAL 0x0000066F -#define DDRC_RANKCTL_MAX_RANK_RD_SHIFT 0 -#define DDRC_RANKCTL_MAX_RANK_RD_MASK 0x0000000FU +#define DDRC_RANKCTL_MAX_RANK_RD_DEFVAL 0x0000066F +#define DDRC_RANKCTL_MAX_RANK_RD_SHIFT 0 +#define DDRC_RANKCTL_MAX_RANK_RD_MASK 0x0000000FU -/*Minimum time between write and precharge to same bank. Unit: Clocks Specifications: WL + BL/2 + tWR = approximately 8 cycles - 15 ns = 14 clocks @400MHz and less for lower frequencies where: - WL = write latency - BL = burst length. This must match th - value programmed in the BL bit of the mode register to the SDRAM. BST (burst terminate) is not supported at present. - tWR = - Write recovery time. This comes directly from the SDRAM specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 for this - arameter. For configurations with MEMC_FREQ_RATIO=2, 1T mode, divide the above value by 2. No rounding up. For configurations - with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, divide the above value by 2 and round it up to the next integer value.*/ +/* +* Minimum time between write and precharge to same bank. Unit: Clocks Spec + * ifications: WL + BL/2 + tWR = approximately 8 cycles + 15 ns = 14 clocks + * @400MHz and less for lower frequencies where: - WL = write latency - BL + * = burst length. This must match the value programmed in the BL bit of t + * he mode register to the SDRAM. BST (burst terminate) is not supported at + * present. - tWR = Write recovery time. This comes directly from the SDRA + * M specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 for this p + * arameter. For configurations with MEMC_FREQ_RATIO=2, 1T mode, divide the + * above value by 2. No rounding up. For configurations with MEMC_FREQ_RAT + * IO=2, 2T mode or LPDDR4 mode, divide the above value by 2 and round it u + * p to the next integer value. +*/ #undef DDRC_DRAMTMG0_WR2PRE_DEFVAL #undef DDRC_DRAMTMG0_WR2PRE_SHIFT #undef DDRC_DRAMTMG0_WR2PRE_MASK -#define DDRC_DRAMTMG0_WR2PRE_DEFVAL 0x0F101B0F -#define DDRC_DRAMTMG0_WR2PRE_SHIFT 24 -#define DDRC_DRAMTMG0_WR2PRE_MASK 0x7F000000U +#define DDRC_DRAMTMG0_WR2PRE_DEFVAL 0x0F101B0F +#define DDRC_DRAMTMG0_WR2PRE_SHIFT 24 +#define DDRC_DRAMTMG0_WR2PRE_MASK 0x7F000000U -/*tFAW Valid only when 8 or more banks(or banks x bank groups) are present. In 8-bank design, at most 4 banks must be activated - in a rolling window of tFAW cycles. For configurations with MEMC_FREQ_RATIO=2, program this to (tFAW/2) and round up to next - nteger value. In a 4-bank design, set this register to 0x1 independent of the MEMC_FREQ_RATIO configuration. Unit: Clocks*/ +/* +* tFAW Valid only when 8 or more banks(or banks x bank groups) are present + * . In 8-bank design, at most 4 banks must be activated in a rolling windo + * w of tFAW cycles. For configurations with MEMC_FREQ_RATIO=2, program thi + * s to (tFAW/2) and round up to next integer value. In a 4-bank design, se + * t this register to 0x1 independent of the MEMC_FREQ_RATIO configuration. + * Unit: Clocks +*/ #undef DDRC_DRAMTMG0_T_FAW_DEFVAL #undef DDRC_DRAMTMG0_T_FAW_SHIFT #undef DDRC_DRAMTMG0_T_FAW_MASK -#define DDRC_DRAMTMG0_T_FAW_DEFVAL 0x0F101B0F -#define DDRC_DRAMTMG0_T_FAW_SHIFT 16 -#define DDRC_DRAMTMG0_T_FAW_MASK 0x003F0000U +#define DDRC_DRAMTMG0_T_FAW_DEFVAL 0x0F101B0F +#define DDRC_DRAMTMG0_T_FAW_SHIFT 16 +#define DDRC_DRAMTMG0_T_FAW_MASK 0x003F0000U -/*tRAS(max): Maximum time between activate and precharge to same bank. This is the maximum time that a page can be kept open Mi - imum value of this register is 1. Zero is invalid. For configurations with MEMC_FREQ_RATIO=2, program this to (tRAS(max)-1)/2 - No rounding up. Unit: Multiples of 1024 clocks.*/ +/* +* tRAS(max): Maximum time between activate and precharge to same bank. Thi + * s is the maximum time that a page can be kept open Minimum value of this + * register is 1. Zero is invalid. For configurations with MEMC_FREQ_RATIO + * =2, program this to (tRAS(max)-1)/2. No rounding up. Unit: Multiples of + * 1024 clocks. +*/ #undef DDRC_DRAMTMG0_T_RAS_MAX_DEFVAL #undef DDRC_DRAMTMG0_T_RAS_MAX_SHIFT #undef DDRC_DRAMTMG0_T_RAS_MAX_MASK -#define DDRC_DRAMTMG0_T_RAS_MAX_DEFVAL 0x0F101B0F -#define DDRC_DRAMTMG0_T_RAS_MAX_SHIFT 8 -#define DDRC_DRAMTMG0_T_RAS_MAX_MASK 0x00007F00U +#define DDRC_DRAMTMG0_T_RAS_MAX_DEFVAL 0x0F101B0F +#define DDRC_DRAMTMG0_T_RAS_MAX_SHIFT 8 +#define DDRC_DRAMTMG0_T_RAS_MAX_MASK 0x00007F00U -/*tRAS(min): Minimum time between activate and precharge to the same bank. For configurations with MEMC_FREQ_RATIO=2, 1T mode, - rogram this to tRAS(min)/2. No rounding up. For configurations with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, program this t - (tRAS(min)/2) and round it up to the next integer value. Unit: Clocks*/ +/* +* tRAS(min): Minimum time between activate and precharge to the same bank. + * For configurations with MEMC_FREQ_RATIO=2, 1T mode, program this to tRA + * S(min)/2. No rounding up. For configurations with MEMC_FREQ_RATIO=2, 2T + * mode or LPDDR4 mode, program this to (tRAS(min)/2) and round it up to th + * e next integer value. Unit: Clocks +*/ #undef DDRC_DRAMTMG0_T_RAS_MIN_DEFVAL #undef DDRC_DRAMTMG0_T_RAS_MIN_SHIFT #undef DDRC_DRAMTMG0_T_RAS_MIN_MASK -#define DDRC_DRAMTMG0_T_RAS_MIN_DEFVAL 0x0F101B0F -#define DDRC_DRAMTMG0_T_RAS_MIN_SHIFT 0 -#define DDRC_DRAMTMG0_T_RAS_MIN_MASK 0x0000003FU +#define DDRC_DRAMTMG0_T_RAS_MIN_DEFVAL 0x0F101B0F +#define DDRC_DRAMTMG0_T_RAS_MIN_SHIFT 0 +#define DDRC_DRAMTMG0_T_RAS_MIN_MASK 0x0000003FU -/*tXP: Minimum time after power-down exit to any operation. For DDR3, this should be programmed to tXPDLL if slow powerdown exi - is selected in MR0[12]. If C/A parity for DDR4 is used, set to (tXP+PL) instead. For configurations with MEMC_FREQ_RATIO=2, - rogram this to (tXP/2) and round it up to the next integer value. Units: Clocks*/ +/* +* tXP: Minimum time after power-down exit to any operation. For DDR3, this + * should be programmed to tXPDLL if slow powerdown exit is selected in MR + * 0[12]. If C/A parity for DDR4 is used, set to (tXP+PL) instead. For conf + * igurations with MEMC_FREQ_RATIO=2, program this to (tXP/2) and round it + * up to the next integer value. Units: Clocks +*/ #undef DDRC_DRAMTMG1_T_XP_DEFVAL #undef DDRC_DRAMTMG1_T_XP_SHIFT #undef DDRC_DRAMTMG1_T_XP_MASK -#define DDRC_DRAMTMG1_T_XP_DEFVAL 0x00080414 -#define DDRC_DRAMTMG1_T_XP_SHIFT 16 -#define DDRC_DRAMTMG1_T_XP_MASK 0x001F0000U +#define DDRC_DRAMTMG1_T_XP_DEFVAL 0x00080414 +#define DDRC_DRAMTMG1_T_XP_SHIFT 16 +#define DDRC_DRAMTMG1_T_XP_MASK 0x001F0000U -/*tRTP: Minimum time from read to precharge of same bank. - DDR2: tAL + BL/2 + max(tRTP, 2) - 2 - DDR3: tAL + max (tRTP, 4) - D - R4: Max of following two equations: tAL + max (tRTP, 4) or, RL + BL/2 - tRP. - mDDR: BL/2 - LPDDR2: Depends on if it's LPDDR2 - S2 or LPDDR2-S4: LPDDR2-S2: BL/2 + tRTP - 1. LPDDR2-S4: BL/2 + max(tRTP,2) - 2. - LPDDR3: BL/2 + max(tRTP,4) - 4 - LPDDR4: BL - 2 + max(tRTP,8) - 8 For configurations with MEMC_FREQ_RATIO=2, 1T mode, divide the above value by 2. No rounding up. For conf - gurations with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, divide the above value by 2 and round it up to the next integer val - e. Unit: Clocks.*/ +/* +* tRTP: Minimum time from read to precharge of same bank. - DDR2: tAL + BL + * /2 + max(tRTP, 2) - 2 - DDR3: tAL + max (tRTP, 4) - DDR4: Max of followi + * ng two equations: tAL + max (tRTP, 4) or, RL + BL/2 - tRP. - mDDR: BL/2 + * - LPDDR2: Depends on if it's LPDDR2-S2 or LPDDR2-S4: LPDDR2-S2: BL/2 + t + * RTP - 1. LPDDR2-S4: BL/2 + max(tRTP,2) - 2. - LPDDR3: BL/2 + max(tRTP,4) + * - 4 - LPDDR4: BL/2 + max(tRTP,8) - 8 For configurations with MEMC_FREQ_ + * RATIO=2, 1T mode, divide the above value by 2. No rounding up. For confi + * gurations with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, divide the abo + * ve value by 2 and round it up to the next integer value. Unit: Clocks. +*/ #undef DDRC_DRAMTMG1_RD2PRE_DEFVAL #undef DDRC_DRAMTMG1_RD2PRE_SHIFT #undef DDRC_DRAMTMG1_RD2PRE_MASK -#define DDRC_DRAMTMG1_RD2PRE_DEFVAL 0x00080414 -#define DDRC_DRAMTMG1_RD2PRE_SHIFT 8 -#define DDRC_DRAMTMG1_RD2PRE_MASK 0x00001F00U +#define DDRC_DRAMTMG1_RD2PRE_DEFVAL 0x00080414 +#define DDRC_DRAMTMG1_RD2PRE_SHIFT 8 +#define DDRC_DRAMTMG1_RD2PRE_MASK 0x00001F00U -/*tRC: Minimum time between activates to same bank. For configurations with MEMC_FREQ_RATIO=2, program this to (tRC/2) and roun - up to next integer value. Unit: Clocks.*/ +/* +* tRC: Minimum time between activates to same bank. For configurations wit + * h MEMC_FREQ_RATIO=2, program this to (tRC/2) and round up to next intege + * r value. Unit: Clocks. +*/ #undef DDRC_DRAMTMG1_T_RC_DEFVAL #undef DDRC_DRAMTMG1_T_RC_SHIFT #undef DDRC_DRAMTMG1_T_RC_MASK -#define DDRC_DRAMTMG1_T_RC_DEFVAL 0x00080414 -#define DDRC_DRAMTMG1_T_RC_SHIFT 0 -#define DDRC_DRAMTMG1_T_RC_MASK 0x0000007FU +#define DDRC_DRAMTMG1_T_RC_DEFVAL 0x00080414 +#define DDRC_DRAMTMG1_T_RC_SHIFT 0 +#define DDRC_DRAMTMG1_T_RC_MASK 0x0000007FU -/*Set to WL Time from write command to write data on SDRAM interface. This must be set to WL. For mDDR, it should normally be s - t to 1. Note that, depending on the PHY, if using RDIMM, it may be necessary to use a value of WL + 1 to compensate for the e - tra cycle of latency through the RDIMM For configurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above - equation by 2, and round it up to next integer. This register field is not required for DDR2 and DDR3 (except if MEMC_TRAININ - is set), as the DFI read and write latencies defined in DFITMG0 and DFITMG1 are sufficient for those protocols Unit: clocks*/ +/* +* Set to WL Time from write command to write data on SDRAM interface. This + * must be set to WL. For mDDR, it should normally be set to 1. Note that, + * depending on the PHY, if using RDIMM, it may be necessary to use a valu + * e of WL + 1 to compensate for the extra cycle of latency through the RDI + * MM For configurations with MEMC_FREQ_RATIO=2, divide the value calculate + * d using the above equation by 2, and round it up to next integer. This r + * egister field is not required for DDR2 and DDR3 (except if MEMC_TRAINING + * is set), as the DFI read and write latencies defined in DFITMG0 and DFI + * TMG1 are sufficient for those protocols Unit: clocks +*/ #undef DDRC_DRAMTMG2_WRITE_LATENCY_DEFVAL #undef DDRC_DRAMTMG2_WRITE_LATENCY_SHIFT #undef DDRC_DRAMTMG2_WRITE_LATENCY_MASK -#define DDRC_DRAMTMG2_WRITE_LATENCY_DEFVAL 0x0305060D -#define DDRC_DRAMTMG2_WRITE_LATENCY_SHIFT 24 -#define DDRC_DRAMTMG2_WRITE_LATENCY_MASK 0x3F000000U +#define DDRC_DRAMTMG2_WRITE_LATENCY_DEFVAL 0x0305060D +#define DDRC_DRAMTMG2_WRITE_LATENCY_SHIFT 24 +#define DDRC_DRAMTMG2_WRITE_LATENCY_MASK 0x3F000000U -/*Set to RL Time from read command to read data on SDRAM interface. This must be set to RL. Note that, depending on the PHY, if - using RDIMM, it mat be necessary to use a value of RL + 1 to compensate for the extra cycle of latency through the RDIMM For - onfigurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next inte - er. This register field is not required for DDR2 and DDR3 (except if MEMC_TRAINING is set), as the DFI read and write latenci - s defined in DFITMG0 and DFITMG1 are sufficient for those protocols Unit: clocks*/ +/* +* Set to RL Time from read command to read data on SDRAM interface. This m + * ust be set to RL. Note that, depending on the PHY, if using RDIMM, it ma + * t be necessary to use a value of RL + 1 to compensate for the extra cycl + * e of latency through the RDIMM For configurations with MEMC_FREQ_RATIO=2 + * , divide the value calculated using the above equation by 2, and round i + * t up to next integer. This register field is not required for DDR2 and D + * DR3 (except if MEMC_TRAINING is set), as the DFI read and write latencie + * s defined in DFITMG0 and DFITMG1 are sufficient for those protocols Unit + * : clocks +*/ #undef DDRC_DRAMTMG2_READ_LATENCY_DEFVAL #undef DDRC_DRAMTMG2_READ_LATENCY_SHIFT #undef DDRC_DRAMTMG2_READ_LATENCY_MASK -#define DDRC_DRAMTMG2_READ_LATENCY_DEFVAL 0x0305060D -#define DDRC_DRAMTMG2_READ_LATENCY_SHIFT 16 -#define DDRC_DRAMTMG2_READ_LATENCY_MASK 0x003F0000U +#define DDRC_DRAMTMG2_READ_LATENCY_DEFVAL 0x0305060D +#define DDRC_DRAMTMG2_READ_LATENCY_SHIFT 16 +#define DDRC_DRAMTMG2_READ_LATENCY_MASK 0x003F0000U -/*DDR2/3/mDDR: RL + BL/2 + 2 - WL DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL LPDDR2/LPDDR3: RL + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL - PDDR4(DQ ODT is Disabled): RL + BL/2 + RU(tDQSCKmax/tCK) + WR_PREAMBLE + RD_POSTAMBLE - WL LPDDR4(DQ ODT is Enabled) : RL + B - /2 + RU(tDQSCKmax/tCK) + RD_POSTAMBLE - ODTLon - RU(tODTon(min)/tCK) Minimum time from read command to write command. Include - time for bus turnaround and all per-bank, per-rank, and global constraints. Unit: Clocks. Where: - WL = write latency - BL = - urst length. This must match the value programmed in the BL bit of the mode register to the SDRAM - RL = read latency = CAS l - tency - WR_PREAMBLE = write preamble. This is unique to DDR4 and LPDDR4. - RD_POSTAMBLE = read postamble. This is unique to L - DDR4. For LPDDR2/LPDDR3/LPDDR4, if derating is enabled (DERATEEN.derate_enable=1), derated tDQSCKmax should be used. For conf - gurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next integer.*/ +/* +* DDR2/3/mDDR: RL + BL/2 + 2 - WL DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL L + * PDDR2/LPDDR3: RL + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL LPDDR4(DQ ODT is Di + * sabled): RL + BL/2 + RU(tDQSCKmax/tCK) + WR_PREAMBLE + RD_POSTAMBLE - WL + * LPDDR4(DQ ODT is Enabled) : RL + BL/2 + RU(tDQSCKmax/tCK) + RD_POSTAMBL + * E - ODTLon - RU(tODTon(min)/tCK) Minimum time from read command to write + * command. Include time for bus turnaround and all per-bank, per-rank, an + * d global constraints. Unit: Clocks. Where: - WL = write latency - BL = b + * urst length. This must match the value programmed in the BL bit of the m + * ode register to the SDRAM - RL = read latency = CAS latency - WR_PREAMBL + * E = write preamble. This is unique to DDR4 and LPDDR4. - RD_POSTAMBLE = + * read postamble. This is unique to LPDDR4. For LPDDR2/LPDDR3/LPDDR4, if d + * erating is enabled (DERATEEN.derate_enable=1), derated tDQSCKmax should + * be used. For configurations with MEMC_FREQ_RATIO=2, divide the value cal + * culated using the above equation by 2, and round it up to next integer. +*/ #undef DDRC_DRAMTMG2_RD2WR_DEFVAL #undef DDRC_DRAMTMG2_RD2WR_SHIFT #undef DDRC_DRAMTMG2_RD2WR_MASK -#define DDRC_DRAMTMG2_RD2WR_DEFVAL 0x0305060D -#define DDRC_DRAMTMG2_RD2WR_SHIFT 8 -#define DDRC_DRAMTMG2_RD2WR_MASK 0x00003F00U +#define DDRC_DRAMTMG2_RD2WR_DEFVAL 0x0305060D +#define DDRC_DRAMTMG2_RD2WR_SHIFT 8 +#define DDRC_DRAMTMG2_RD2WR_MASK 0x00003F00U -/*DDR4: CWL + PL + BL/2 + tWTR_L Others: CWL + BL/2 + tWTR In DDR4, minimum time from write command to read command for same ba - k group. In others, minimum time from write command to read command. Includes time for bus turnaround, recovery times, and al - per-bank, per-rank, and global constraints. Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity latency - BL = burs - length. This must match the value programmed in the BL bit of the mode register to the SDRAM - tWTR_L = internal write to re - d command delay for same bank group. This comes directly from the SDRAM specification. - tWTR = internal write to read comman - delay. This comes directly from the SDRAM specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 operation. For configu - ations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next integer.*/ +/* +* DDR4: CWL + PL + BL/2 + tWTR_L Others: CWL + BL/2 + tWTR In DDR4, minimu + * m time from write command to read command for same bank group. In others + * , minimum time from write command to read command. Includes time for bus + * turnaround, recovery times, and all per-bank, per-rank, and global cons + * traints. Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity la + * tency - BL = burst length. This must match the value programmed in the B + * L bit of the mode register to the SDRAM - tWTR_L = internal write to rea + * d command delay for same bank group. This comes directly from the SDRAM + * specification. - tWTR = internal write to read command delay. This comes + * directly from the SDRAM specification. Add one extra cycle for LPDDR2/L + * PDDR3/LPDDR4 operation. For configurations with MEMC_FREQ_RATIO=2, divid + * e the value calculated using the above equation by 2, and round it up to + * next integer. +*/ #undef DDRC_DRAMTMG2_WR2RD_DEFVAL #undef DDRC_DRAMTMG2_WR2RD_SHIFT #undef DDRC_DRAMTMG2_WR2RD_MASK -#define DDRC_DRAMTMG2_WR2RD_DEFVAL 0x0305060D -#define DDRC_DRAMTMG2_WR2RD_SHIFT 0 -#define DDRC_DRAMTMG2_WR2RD_MASK 0x0000003FU +#define DDRC_DRAMTMG2_WR2RD_DEFVAL 0x0305060D +#define DDRC_DRAMTMG2_WR2RD_SHIFT 0 +#define DDRC_DRAMTMG2_WR2RD_MASK 0x0000003FU -/*Time to wait after a mode register write or read (MRW or MRR). Present only in designs configured to support LPDDR2, LPDDR3 o - LPDDR4. LPDDR2 typically requires value of 5. LPDDR3 typically requires value of 10. LPDDR4: Set this to the larger of tMRW - nd tMRWCKEL. For LPDDR2, this register is used for the time from a MRW/MRR to all other commands. For LDPDR3, this register i - used for the time from a MRW/MRR to a MRW/MRR.*/ +/* +* Time to wait after a mode register write or read (MRW or MRR). Present o + * nly in designs configured to support LPDDR2, LPDDR3 or LPDDR4. LPDDR2 ty + * pically requires value of 5. LPDDR3 typically requires value of 10. LPDD + * R4: Set this to the larger of tMRW and tMRWCKEL. For LPDDR2, this regist + * er is used for the time from a MRW/MRR to all other commands. For LDPDR3 + * , this register is used for the time from a MRW/MRR to a MRW/MRR. +*/ #undef DDRC_DRAMTMG3_T_MRW_DEFVAL #undef DDRC_DRAMTMG3_T_MRW_SHIFT #undef DDRC_DRAMTMG3_T_MRW_MASK -#define DDRC_DRAMTMG3_T_MRW_DEFVAL 0x0050400C -#define DDRC_DRAMTMG3_T_MRW_SHIFT 20 -#define DDRC_DRAMTMG3_T_MRW_MASK 0x3FF00000U +#define DDRC_DRAMTMG3_T_MRW_DEFVAL 0x0050400C +#define DDRC_DRAMTMG3_T_MRW_SHIFT 20 +#define DDRC_DRAMTMG3_T_MRW_MASK 0x3FF00000U -/*tMRD: Cycles to wait after a mode register write or read. Depending on the connected SDRAM, tMRD represents: DDR2/mDDR: Time - rom MRS to any command DDR3/4: Time from MRS to MRS command LPDDR2: not used LPDDR3/4: Time from MRS to non-MRS command For c - nfigurations with MEMC_FREQ_RATIO=2, program this to (tMRD/2) and round it up to the next integer value. If C/A parity for DD - 4 is used, set to tMRD_PAR(tMOD+PL) instead.*/ +/* +* tMRD: Cycles to wait after a mode register write or read. Depending on t + * he connected SDRAM, tMRD represents: DDR2/mDDR: Time from MRS to any com + * mand DDR3/4: Time from MRS to MRS command LPDDR2: not used LPDDR3/4: Tim + * e from MRS to non-MRS command For configurations with MEMC_FREQ_RATIO=2, + * program this to (tMRD/2) and round it up to the next integer value. If + * C/A parity for DDR4 is used, set to tMRD_PAR(tMOD+PL) instead. +*/ #undef DDRC_DRAMTMG3_T_MRD_DEFVAL #undef DDRC_DRAMTMG3_T_MRD_SHIFT #undef DDRC_DRAMTMG3_T_MRD_MASK -#define DDRC_DRAMTMG3_T_MRD_DEFVAL 0x0050400C -#define DDRC_DRAMTMG3_T_MRD_SHIFT 12 -#define DDRC_DRAMTMG3_T_MRD_MASK 0x0003F000U +#define DDRC_DRAMTMG3_T_MRD_DEFVAL 0x0050400C +#define DDRC_DRAMTMG3_T_MRD_SHIFT 12 +#define DDRC_DRAMTMG3_T_MRD_MASK 0x0003F000U -/*tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode command and following non-load mode command. If C/A pari - y for DDR4 is used, set to tMOD_PAR(tMOD+PL) instead. Set to tMOD if MEMC_FREQ_RATIO=1, or tMOD/2 (rounded up to next integer - if MEMC_FREQ_RATIO=2. Note that if using RDIMM, depending on the PHY, it may be necessary to use a value of tMOD + 1 or (tMO - + 1)/2 to compensate for the extra cycle of latency applied to mode register writes by the RDIMM chip.*/ +/* +* tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode com + * mand and following non-load mode command. If C/A parity for DDR4 is used + * , set to tMOD_PAR(tMOD+PL) instead. Set to tMOD if MEMC_FREQ_RATIO=1, or + * tMOD/2 (rounded up to next integer) if MEMC_FREQ_RATIO=2. Note that if + * using RDIMM, depending on the PHY, it may be necessary to use a value of + * tMOD + 1 or (tMOD + 1)/2 to compensate for the extra cycle of latency a + * pplied to mode register writes by the RDIMM chip. +*/ #undef DDRC_DRAMTMG3_T_MOD_DEFVAL #undef DDRC_DRAMTMG3_T_MOD_SHIFT #undef DDRC_DRAMTMG3_T_MOD_MASK -#define DDRC_DRAMTMG3_T_MOD_DEFVAL 0x0050400C -#define DDRC_DRAMTMG3_T_MOD_SHIFT 0 -#define DDRC_DRAMTMG3_T_MOD_MASK 0x000003FFU +#define DDRC_DRAMTMG3_T_MOD_DEFVAL 0x0050400C +#define DDRC_DRAMTMG3_T_MOD_SHIFT 0 +#define DDRC_DRAMTMG3_T_MOD_MASK 0x000003FFU -/*tRCD - tAL: Minimum time from activate to read or write command to same bank. For configurations with MEMC_FREQ_RATIO=2, prog - am this to ((tRCD - tAL)/2) and round it up to the next integer value. Minimum value allowed for this register is 1, which im - lies minimum (tRCD - tAL) value to be 2 in configurations with MEMC_FREQ_RATIO=2. Unit: Clocks.*/ +/* +* tRCD - tAL: Minimum time from activate to read or write command to same + * bank. For configurations with MEMC_FREQ_RATIO=2, program this to ((tRCD + * - tAL)/2) and round it up to the next integer value. Minimum value allow + * ed for this register is 1, which implies minimum (tRCD - tAL) value to b + * e 2 in configurations with MEMC_FREQ_RATIO=2. Unit: Clocks. +*/ #undef DDRC_DRAMTMG4_T_RCD_DEFVAL #undef DDRC_DRAMTMG4_T_RCD_SHIFT #undef DDRC_DRAMTMG4_T_RCD_MASK -#define DDRC_DRAMTMG4_T_RCD_DEFVAL 0x05040405 -#define DDRC_DRAMTMG4_T_RCD_SHIFT 24 -#define DDRC_DRAMTMG4_T_RCD_MASK 0x1F000000U +#define DDRC_DRAMTMG4_T_RCD_DEFVAL 0x05040405 +#define DDRC_DRAMTMG4_T_RCD_SHIFT 24 +#define DDRC_DRAMTMG4_T_RCD_MASK 0x1F000000U -/*DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank group. Others: tCCD: This is the minimum - time between two reads or two writes. For configurations with MEMC_FREQ_RATIO=2, program this to (tCCD_L/2 or tCCD/2) and rou - d it up to the next integer value. Unit: clocks.*/ +/* +* DDR4: tCCD_L: This is the minimum time between two reads or two writes f + * or same bank group. Others: tCCD: This is the minimum time between two r + * eads or two writes. For configurations with MEMC_FREQ_RATIO=2, program t + * his to (tCCD_L/2 or tCCD/2) and round it up to the next integer value. U + * nit: clocks. +*/ #undef DDRC_DRAMTMG4_T_CCD_DEFVAL #undef DDRC_DRAMTMG4_T_CCD_SHIFT #undef DDRC_DRAMTMG4_T_CCD_MASK -#define DDRC_DRAMTMG4_T_CCD_DEFVAL 0x05040405 -#define DDRC_DRAMTMG4_T_CCD_SHIFT 16 -#define DDRC_DRAMTMG4_T_CCD_MASK 0x000F0000U +#define DDRC_DRAMTMG4_T_CCD_DEFVAL 0x05040405 +#define DDRC_DRAMTMG4_T_CCD_SHIFT 16 +#define DDRC_DRAMTMG4_T_CCD_MASK 0x000F0000U -/*DDR4: tRRD_L: Minimum time between activates from bank 'a' to bank 'b' for same bank group. Others: tRRD: Minimum time betwee - activates from bank 'a' to bank 'b'For configurations with MEMC_FREQ_RATIO=2, program this to (tRRD_L/2 or tRRD/2) and round - it up to the next integer value. Unit: Clocks.*/ +/* +* DDR4: tRRD_L: Minimum time between activates from bank 'a' to bank 'b' f + * or same bank group. Others: tRRD: Minimum time between activates from ba + * nk 'a' to bank 'b'For configurations with MEMC_FREQ_RATIO=2, program thi + * s to (tRRD_L/2 or tRRD/2) and round it up to the next integer value. Uni + * t: Clocks. +*/ #undef DDRC_DRAMTMG4_T_RRD_DEFVAL #undef DDRC_DRAMTMG4_T_RRD_SHIFT #undef DDRC_DRAMTMG4_T_RRD_MASK -#define DDRC_DRAMTMG4_T_RRD_DEFVAL 0x05040405 -#define DDRC_DRAMTMG4_T_RRD_SHIFT 8 -#define DDRC_DRAMTMG4_T_RRD_MASK 0x00000F00U +#define DDRC_DRAMTMG4_T_RRD_DEFVAL 0x05040405 +#define DDRC_DRAMTMG4_T_RRD_SHIFT 8 +#define DDRC_DRAMTMG4_T_RRD_MASK 0x00000F00U -/*tRP: Minimum time from precharge to activate of same bank. For MEMC_FREQ_RATIO=1 configurations, t_rp should be set to RoundU - (tRP/tCK). For MEMC_FREQ_RATIO=2 configurations, t_rp should be set to RoundDown(RoundUp(tRP/tCK)/2) + 1. For MEMC_FREQ_RATIO - 2 configurations in LPDDR4, t_rp should be set to RoundUp(RoundUp(tRP/tCK)/2). Unit: Clocks.*/ +/* +* tRP: Minimum time from precharge to activate of same bank. For MEMC_FREQ + * _RATIO=1 configurations, t_rp should be set to RoundUp(tRP/tCK). For MEM + * C_FREQ_RATIO=2 configurations, t_rp should be set to RoundDown(RoundUp(t + * RP/tCK)/2) + 1. For MEMC_FREQ_RATIO=2 configurations in LPDDR4, t_rp sho + * uld be set to RoundUp(RoundUp(tRP/tCK)/2). Unit: Clocks. +*/ #undef DDRC_DRAMTMG4_T_RP_DEFVAL #undef DDRC_DRAMTMG4_T_RP_SHIFT #undef DDRC_DRAMTMG4_T_RP_MASK -#define DDRC_DRAMTMG4_T_RP_DEFVAL 0x05040405 -#define DDRC_DRAMTMG4_T_RP_SHIFT 0 -#define DDRC_DRAMTMG4_T_RP_MASK 0x0000001FU +#define DDRC_DRAMTMG4_T_RP_DEFVAL 0x05040405 +#define DDRC_DRAMTMG4_T_RP_SHIFT 0 +#define DDRC_DRAMTMG4_T_RP_MASK 0x0000001FU -/*This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stab - e time before SRX. Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEH - DDR2: 1 - DDR3: tCKSRX - DDR4: - tCKSRX For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it up to next in - eger.*/ +/* +* This is the time before Self Refresh Exit that CK is maintained as a val + * id clock before issuing SRX. Specifies the clock stable time before SRX. + * Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCK + * EH - DDR2: 1 - DDR3: tCKSRX - DDR4: tCKSRX For configurations with MEMC_ + * FREQ_RATIO=2, program this to recommended value divided by two and round + * it up to next integer. +*/ #undef DDRC_DRAMTMG5_T_CKSRX_DEFVAL #undef DDRC_DRAMTMG5_T_CKSRX_SHIFT #undef DDRC_DRAMTMG5_T_CKSRX_MASK -#define DDRC_DRAMTMG5_T_CKSRX_DEFVAL 0x05050403 -#define DDRC_DRAMTMG5_T_CKSRX_SHIFT 24 -#define DDRC_DRAMTMG5_T_CKSRX_MASK 0x0F000000U +#define DDRC_DRAMTMG5_T_CKSRX_DEFVAL 0x05050403 +#define DDRC_DRAMTMG5_T_CKSRX_SHIFT 24 +#define DDRC_DRAMTMG5_T_CKSRX_MASK 0x0F000000U -/*This is the time after Self Refresh Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay afte - SRE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL - DDR2: 1 - DDR3: max (10 ns, 5 tCK) - DDR4: - ax (10 ns, 5 tCK) For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it up - to next integer.*/ +/* +* This is the time after Self Refresh Down Entry that CK is maintained as + * a valid clock. Specifies the clock disable delay after SRE. Recommended + * settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL - DDR2: 1 + * - DDR3: max (10 ns, 5 tCK) - DDR4: max (10 ns, 5 tCK) For configurations + * with MEMC_FREQ_RATIO=2, program this to recommended value divided by tw + * o and round it up to next integer. +*/ #undef DDRC_DRAMTMG5_T_CKSRE_DEFVAL #undef DDRC_DRAMTMG5_T_CKSRE_SHIFT #undef DDRC_DRAMTMG5_T_CKSRE_MASK -#define DDRC_DRAMTMG5_T_CKSRE_DEFVAL 0x05050403 -#define DDRC_DRAMTMG5_T_CKSRE_SHIFT 16 -#define DDRC_DRAMTMG5_T_CKSRE_MASK 0x000F0000U +#define DDRC_DRAMTMG5_T_CKSRE_DEFVAL 0x05050403 +#define DDRC_DRAMTMG5_T_CKSRE_SHIFT 16 +#define DDRC_DRAMTMG5_T_CKSRE_MASK 0x000F0000U -/*Minimum CKE low width for Self refresh or Self refresh power down entry to exit timing in memory clock cycles. Recommended se - tings: - mDDR: tRFC - LPDDR2: tCKESR - LPDDR3: tCKESR - LPDDR4: max(tCKELPD, tSR) - DDR2: tCKE - DDR3: tCKE + 1 - DDR4: tCKE - 1 For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it up to next intege - .*/ +/* +* Minimum CKE low width for Self refresh or Self refresh power down entry + * to exit timing in memory clock cycles. Recommended settings: - mDDR: tRF + * C - LPDDR2: tCKESR - LPDDR3: tCKESR - LPDDR4: max(tCKELPD, tSR) - DDR2: + * tCKE - DDR3: tCKE + 1 - DDR4: tCKE + 1 For configurations with MEMC_FREQ + * _RATIO=2, program this to recommended value divided by two and round it + * up to next integer. +*/ #undef DDRC_DRAMTMG5_T_CKESR_DEFVAL #undef DDRC_DRAMTMG5_T_CKESR_SHIFT #undef DDRC_DRAMTMG5_T_CKESR_MASK -#define DDRC_DRAMTMG5_T_CKESR_DEFVAL 0x05050403 -#define DDRC_DRAMTMG5_T_CKESR_SHIFT 8 -#define DDRC_DRAMTMG5_T_CKESR_MASK 0x00003F00U +#define DDRC_DRAMTMG5_T_CKESR_DEFVAL 0x05050403 +#define DDRC_DRAMTMG5_T_CKESR_SHIFT 8 +#define DDRC_DRAMTMG5_T_CKESR_MASK 0x00003F00U -/*Minimum number of cycles of CKE HIGH/LOW during power-down and self refresh. - LPDDR2/LPDDR3 mode: Set this to the larger of - CKE or tCKESR - LPDDR4 mode: Set this to the larger of tCKE, tCKELPD or tSR. - Non-LPDDR2/non-LPDDR3/non-LPDDR4 designs: Set - his to tCKE value. For configurations with MEMC_FREQ_RATIO=2, program this to (value described above)/2 and round it up to th - next integer value. Unit: Clocks.*/ +/* +* Minimum number of cycles of CKE HIGH/LOW during power-down and self refr + * esh. - LPDDR2/LPDDR3 mode: Set this to the larger of tCKE or tCKESR - LP + * DDR4 mode: Set this to the larger of tCKE, tCKELPD or tSR. - Non-LPDDR2/ + * non-LPDDR3/non-LPDDR4 designs: Set this to tCKE value. For configuration + * s with MEMC_FREQ_RATIO=2, program this to (value described above)/2 and + * round it up to the next integer value. Unit: Clocks. +*/ #undef DDRC_DRAMTMG5_T_CKE_DEFVAL #undef DDRC_DRAMTMG5_T_CKE_SHIFT #undef DDRC_DRAMTMG5_T_CKE_MASK -#define DDRC_DRAMTMG5_T_CKE_DEFVAL 0x05050403 -#define DDRC_DRAMTMG5_T_CKE_SHIFT 0 -#define DDRC_DRAMTMG5_T_CKE_MASK 0x0000001FU +#define DDRC_DRAMTMG5_T_CKE_DEFVAL 0x05050403 +#define DDRC_DRAMTMG5_T_CKE_SHIFT 0 +#define DDRC_DRAMTMG5_T_CKE_MASK 0x0000001FU -/*This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after - PDE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 For configurations with MEMC_FREQ_RATIO=2, program this to recom - ended value divided by two and round it up to next integer. This is only present for designs supporting mDDR or LPDDR2/LPDDR3 - devices.*/ +/* +* This is the time after Deep Power Down Entry that CK is maintained as a + * valid clock. Specifies the clock disable delay after DPDE. Recommended s + * ettings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 For configurations with MEMC_ + * FREQ_RATIO=2, program this to recommended value divided by two and round + * it up to next integer. This is only present for designs supporting mDDR + * or LPDDR2/LPDDR3 devices. +*/ #undef DDRC_DRAMTMG6_T_CKDPDE_DEFVAL #undef DDRC_DRAMTMG6_T_CKDPDE_SHIFT #undef DDRC_DRAMTMG6_T_CKDPDE_MASK -#define DDRC_DRAMTMG6_T_CKDPDE_DEFVAL 0x02020005 -#define DDRC_DRAMTMG6_T_CKDPDE_SHIFT 24 -#define DDRC_DRAMTMG6_T_CKDPDE_MASK 0x0F000000U +#define DDRC_DRAMTMG6_T_CKDPDE_DEFVAL 0x02020005 +#define DDRC_DRAMTMG6_T_CKDPDE_SHIFT 24 +#define DDRC_DRAMTMG6_T_CKDPDE_MASK 0x0F000000U -/*This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock - table time before DPDX. Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 For configurations with MEMC_FREQ_RATIO=2, pr - gram this to recommended value divided by two and round it up to next integer. This is only present for designs supporting mD - R or LPDDR2 devices.*/ +/* +* This is the time before Deep Power Down Exit that CK is maintained as a + * valid clock before issuing DPDX. Specifies the clock stable time before + * DPDX. Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 For config + * urations with MEMC_FREQ_RATIO=2, program this to recommended value divid + * ed by two and round it up to next integer. This is only present for desi + * gns supporting mDDR or LPDDR2 devices. +*/ #undef DDRC_DRAMTMG6_T_CKDPDX_DEFVAL #undef DDRC_DRAMTMG6_T_CKDPDX_SHIFT #undef DDRC_DRAMTMG6_T_CKDPDX_MASK -#define DDRC_DRAMTMG6_T_CKDPDX_DEFVAL 0x02020005 -#define DDRC_DRAMTMG6_T_CKDPDX_SHIFT 16 -#define DDRC_DRAMTMG6_T_CKDPDX_MASK 0x000F0000U +#define DDRC_DRAMTMG6_T_CKDPDX_DEFVAL 0x02020005 +#define DDRC_DRAMTMG6_T_CKDPDX_SHIFT 16 +#define DDRC_DRAMTMG6_T_CKDPDX_MASK 0x000F0000U -/*This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing Clock Stop Exit. Specifies the - lock stable time before next command after Clock Stop Exit. Recommended settings: - mDDR: 1 - LPDDR2: tXP + 2 - LPDDR3: tXP + - 2 - LPDDR4: tXP + 2 For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it - p to next integer. This is only present for designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices.*/ +/* +* This is the time before Clock Stop Exit that CK is maintained as a valid + * clock before issuing Clock Stop Exit. Specifies the clock stable time b + * efore next command after Clock Stop Exit. Recommended settings: - mDDR: + * 1 - LPDDR2: tXP + 2 - LPDDR3: tXP + 2 - LPDDR4: tXP + 2 For configuratio + * ns with MEMC_FREQ_RATIO=2, program this to recommended value divided by + * two and round it up to next integer. This is only present for designs su + * pporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices. +*/ #undef DDRC_DRAMTMG6_T_CKCSX_DEFVAL #undef DDRC_DRAMTMG6_T_CKCSX_SHIFT #undef DDRC_DRAMTMG6_T_CKCSX_MASK -#define DDRC_DRAMTMG6_T_CKCSX_DEFVAL 0x02020005 -#define DDRC_DRAMTMG6_T_CKCSX_SHIFT 0 -#define DDRC_DRAMTMG6_T_CKCSX_MASK 0x0000000FU +#define DDRC_DRAMTMG6_T_CKCSX_DEFVAL 0x02020005 +#define DDRC_DRAMTMG6_T_CKCSX_SHIFT 0 +#define DDRC_DRAMTMG6_T_CKCSX_MASK 0x0000000FU -/*This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. - ecommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL For configurations with MEMC_FREQ_RATIO=2, program t - is to recommended value divided by two and round it up to next integer. This is only present for designs supporting mDDR or L - DDR2/LPDDR3/LPDDR4 devices.*/ +/* +* This is the time after Power Down Entry that CK is maintained as a valid + * clock. Specifies the clock disable delay after PDE. Recommended setting + * s: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL For configuration + * s with MEMC_FREQ_RATIO=2, program this to recommended value divided by t + * wo and round it up to next integer. This is only present for designs sup + * porting mDDR or LPDDR2/LPDDR3/LPDDR4 devices. +*/ #undef DDRC_DRAMTMG7_T_CKPDE_DEFVAL #undef DDRC_DRAMTMG7_T_CKPDE_SHIFT #undef DDRC_DRAMTMG7_T_CKPDE_MASK -#define DDRC_DRAMTMG7_T_CKPDE_DEFVAL 0x00000202 -#define DDRC_DRAMTMG7_T_CKPDE_SHIFT 8 -#define DDRC_DRAMTMG7_T_CKPDE_MASK 0x00000F00U +#define DDRC_DRAMTMG7_T_CKPDE_DEFVAL 0x00000202 +#define DDRC_DRAMTMG7_T_CKPDE_SHIFT 8 +#define DDRC_DRAMTMG7_T_CKPDE_MASK 0x00000F00U -/*This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable - time before PDX. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: 2 For configurations with MEMC_FREQ_RATIO= - , program this to recommended value divided by two and round it up to next integer. This is only present for designs supporti - g mDDR or LPDDR2/LPDDR3/LPDDR4 devices.*/ +/* +* This is the time before Power Down Exit that CK is maintained as a valid + * clock before issuing PDX. Specifies the clock stable time before PDX. R + * ecommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: 2 For c + * onfigurations with MEMC_FREQ_RATIO=2, program this to recommended value + * divided by two and round it up to next integer. This is only present for + * designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices. +*/ #undef DDRC_DRAMTMG7_T_CKPDX_DEFVAL #undef DDRC_DRAMTMG7_T_CKPDX_SHIFT #undef DDRC_DRAMTMG7_T_CKPDX_MASK -#define DDRC_DRAMTMG7_T_CKPDX_DEFVAL 0x00000202 -#define DDRC_DRAMTMG7_T_CKPDX_SHIFT 0 -#define DDRC_DRAMTMG7_T_CKPDX_MASK 0x0000000FU +#define DDRC_DRAMTMG7_T_CKPDX_DEFVAL 0x00000202 +#define DDRC_DRAMTMG7_T_CKPDX_SHIFT 0 +#define DDRC_DRAMTMG7_T_CKPDX_MASK 0x0000000FU -/*tXS_FAST: Exit Self Refresh to ZQCL, ZQCS and MRS (only CL, WR, RTP and Geardown mode). For configurations with MEMC_FREQ_RAT - O=2, program this to the above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: Thi - is applicable to only ZQCL/ZQCS commands. Note: Ensure this is less than or equal to t_xs_x32.*/ +/* +* tXS_FAST: Exit Self Refresh to ZQCL, ZQCS and MRS (only CL, WR, RTP and + * Geardown mode). For configurations with MEMC_FREQ_RATIO=2, program this + * to the above value divided by 2 and round up to next integer value. Unit + * : Multiples of 32 clocks. Note: This is applicable to only ZQCL/ZQCS com + * mands. Note: Ensure this is less than or equal to t_xs_x32. +*/ #undef DDRC_DRAMTMG8_T_XS_FAST_X32_DEFVAL #undef DDRC_DRAMTMG8_T_XS_FAST_X32_SHIFT #undef DDRC_DRAMTMG8_T_XS_FAST_X32_MASK -#define DDRC_DRAMTMG8_T_XS_FAST_X32_DEFVAL 0x03034405 -#define DDRC_DRAMTMG8_T_XS_FAST_X32_SHIFT 24 -#define DDRC_DRAMTMG8_T_XS_FAST_X32_MASK 0x7F000000U +#define DDRC_DRAMTMG8_T_XS_FAST_X32_DEFVAL 0x03034405 +#define DDRC_DRAMTMG8_T_XS_FAST_X32_SHIFT 24 +#define DDRC_DRAMTMG8_T_XS_FAST_X32_MASK 0x7F000000U -/*tXS_ABORT: Exit Self Refresh to commands not requiring a locked DLL in Self Refresh Abort. For configurations with MEMC_FREQ_ - ATIO=2, program this to the above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: - nsure this is less than or equal to t_xs_x32.*/ +/* +* tXS_ABORT: Exit Self Refresh to commands not requiring a locked DLL in S + * elf Refresh Abort. For configurations with MEMC_FREQ_RATIO=2, program th + * is to the above value divided by 2 and round up to next integer value. U + * nit: Multiples of 32 clocks. Note: Ensure this is less than or equal to + * t_xs_x32. +*/ #undef DDRC_DRAMTMG8_T_XS_ABORT_X32_DEFVAL #undef DDRC_DRAMTMG8_T_XS_ABORT_X32_SHIFT #undef DDRC_DRAMTMG8_T_XS_ABORT_X32_MASK -#define DDRC_DRAMTMG8_T_XS_ABORT_X32_DEFVAL 0x03034405 -#define DDRC_DRAMTMG8_T_XS_ABORT_X32_SHIFT 16 -#define DDRC_DRAMTMG8_T_XS_ABORT_X32_MASK 0x007F0000U +#define DDRC_DRAMTMG8_T_XS_ABORT_X32_DEFVAL 0x03034405 +#define DDRC_DRAMTMG8_T_XS_ABORT_X32_SHIFT 16 +#define DDRC_DRAMTMG8_T_XS_ABORT_X32_MASK 0x007F0000U -/*tXSDLL: Exit Self Refresh to commands requiring a locked DLL. For configurations with MEMC_FREQ_RATIO=2, program this to the - bove value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: Used only for DDR2, DDR3 and - DR4 SDRAMs.*/ +/* +* tXSDLL: Exit Self Refresh to commands requiring a locked DLL. For config + * urations with MEMC_FREQ_RATIO=2, program this to the above value divided + * by 2 and round up to next integer value. Unit: Multiples of 32 clocks. + * Note: Used only for DDR2, DDR3 and DDR4 SDRAMs. +*/ #undef DDRC_DRAMTMG8_T_XS_DLL_X32_DEFVAL #undef DDRC_DRAMTMG8_T_XS_DLL_X32_SHIFT #undef DDRC_DRAMTMG8_T_XS_DLL_X32_MASK -#define DDRC_DRAMTMG8_T_XS_DLL_X32_DEFVAL 0x03034405 -#define DDRC_DRAMTMG8_T_XS_DLL_X32_SHIFT 8 -#define DDRC_DRAMTMG8_T_XS_DLL_X32_MASK 0x00007F00U +#define DDRC_DRAMTMG8_T_XS_DLL_X32_DEFVAL 0x03034405 +#define DDRC_DRAMTMG8_T_XS_DLL_X32_SHIFT 8 +#define DDRC_DRAMTMG8_T_XS_DLL_X32_MASK 0x00007F00U -/*tXS: Exit Self Refresh to commands not requiring a locked DLL. For configurations with MEMC_FREQ_RATIO=2, program this to the - above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: Used only for DDR2, DDR3 and - DDR4 SDRAMs.*/ +/* +* tXS: Exit Self Refresh to commands not requiring a locked DLL. For confi + * gurations with MEMC_FREQ_RATIO=2, program this to the above value divide + * d by 2 and round up to next integer value. Unit: Multiples of 32 clocks. + * Note: Used only for DDR2, DDR3 and DDR4 SDRAMs. +*/ #undef DDRC_DRAMTMG8_T_XS_X32_DEFVAL #undef DDRC_DRAMTMG8_T_XS_X32_SHIFT #undef DDRC_DRAMTMG8_T_XS_X32_MASK -#define DDRC_DRAMTMG8_T_XS_X32_DEFVAL 0x03034405 -#define DDRC_DRAMTMG8_T_XS_X32_SHIFT 0 -#define DDRC_DRAMTMG8_T_XS_X32_MASK 0x0000007FU +#define DDRC_DRAMTMG8_T_XS_X32_DEFVAL 0x03034405 +#define DDRC_DRAMTMG8_T_XS_X32_SHIFT 0 +#define DDRC_DRAMTMG8_T_XS_X32_MASK 0x0000007FU -/*DDR4 Write preamble mode - 0: 1tCK preamble - 1: 2tCK preamble Present only with MEMC_FREQ_RATIO=2*/ +/* +* DDR4 Write preamble mode - 0: 1tCK preamble - 1: 2tCK preamble Present o + * nly with MEMC_FREQ_RATIO=2 +*/ #undef DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_DEFVAL #undef DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_SHIFT #undef DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_MASK -#define DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_DEFVAL 0x0004040D -#define DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_SHIFT 30 -#define DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_MASK 0x40000000U +#define DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_DEFVAL 0x0004040D +#define DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_SHIFT 30 +#define DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_MASK 0x40000000U -/*tCCD_S: This is the minimum time between two reads or two writes for different bank group. For bank switching (from bank 'a' - o bank 'b'), the minimum time is this value + 1. For configurations with MEMC_FREQ_RATIO=2, program this to (tCCD_S/2) and ro - nd it up to the next integer value. Present only in designs configured to support DDR4. Unit: clocks.*/ +/* +* tCCD_S: This is the minimum time between two reads or two writes for dif + * ferent bank group. For bank switching (from bank 'a' to bank 'b'), the m + * inimum time is this value + 1. For configurations with MEMC_FREQ_RATIO=2 + * , program this to (tCCD_S/2) and round it up to the next integer value. + * Present only in designs configured to support DDR4. Unit: clocks. +*/ #undef DDRC_DRAMTMG9_T_CCD_S_DEFVAL #undef DDRC_DRAMTMG9_T_CCD_S_SHIFT #undef DDRC_DRAMTMG9_T_CCD_S_MASK -#define DDRC_DRAMTMG9_T_CCD_S_DEFVAL 0x0004040D -#define DDRC_DRAMTMG9_T_CCD_S_SHIFT 16 -#define DDRC_DRAMTMG9_T_CCD_S_MASK 0x00070000U +#define DDRC_DRAMTMG9_T_CCD_S_DEFVAL 0x0004040D +#define DDRC_DRAMTMG9_T_CCD_S_SHIFT 16 +#define DDRC_DRAMTMG9_T_CCD_S_MASK 0x00070000U -/*tRRD_S: Minimum time between activates from bank 'a' to bank 'b' for different bank group. For configurations with MEMC_FREQ_ - ATIO=2, program this to (tRRD_S/2) and round it up to the next integer value. Present only in designs configured to support D - R4. Unit: Clocks.*/ +/* +* tRRD_S: Minimum time between activates from bank 'a' to bank 'b' for dif + * ferent bank group. For configurations with MEMC_FREQ_RATIO=2, program th + * is to (tRRD_S/2) and round it up to the next integer value. Present only + * in designs configured to support DDR4. Unit: Clocks. +*/ #undef DDRC_DRAMTMG9_T_RRD_S_DEFVAL #undef DDRC_DRAMTMG9_T_RRD_S_SHIFT #undef DDRC_DRAMTMG9_T_RRD_S_MASK -#define DDRC_DRAMTMG9_T_RRD_S_DEFVAL 0x0004040D -#define DDRC_DRAMTMG9_T_RRD_S_SHIFT 8 -#define DDRC_DRAMTMG9_T_RRD_S_MASK 0x00000F00U +#define DDRC_DRAMTMG9_T_RRD_S_DEFVAL 0x0004040D +#define DDRC_DRAMTMG9_T_RRD_S_SHIFT 8 +#define DDRC_DRAMTMG9_T_RRD_S_MASK 0x00000F00U -/*CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command for different bank group. Includes time for bus turn - round, recovery times, and all per-bank, per-rank, and global constraints. Present only in designs configured to support DDR4 - Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity latency - BL = burst length. This must match the value programm - d in the BL bit of the mode register to the SDRAM - tWTR_S = internal write to read command delay for different bank group. T - is comes directly from the SDRAM specification. For configurations with MEMC_FREQ_RATIO=2, divide the value calculated using - he above equation by 2, and round it up to next integer.*/ +/* +* CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command + * for different bank group. Includes time for bus turnaround, recovery ti + * mes, and all per-bank, per-rank, and global constraints. Present only in + * designs configured to support DDR4. Unit: Clocks. Where: - CWL = CAS wr + * ite latency - PL = Parity latency - BL = burst length. This must match t + * he value programmed in the BL bit of the mode register to the SDRAM - tW + * TR_S = internal write to read command delay for different bank group. Th + * is comes directly from the SDRAM specification. For configurations with + * MEMC_FREQ_RATIO=2, divide the value calculated using the above equation + * by 2, and round it up to next integer. +*/ #undef DDRC_DRAMTMG9_WR2RD_S_DEFVAL #undef DDRC_DRAMTMG9_WR2RD_S_SHIFT #undef DDRC_DRAMTMG9_WR2RD_S_MASK -#define DDRC_DRAMTMG9_WR2RD_S_DEFVAL 0x0004040D -#define DDRC_DRAMTMG9_WR2RD_S_SHIFT 0 -#define DDRC_DRAMTMG9_WR2RD_S_MASK 0x0000003FU +#define DDRC_DRAMTMG9_WR2RD_S_DEFVAL 0x0004040D +#define DDRC_DRAMTMG9_WR2RD_S_SHIFT 0 +#define DDRC_DRAMTMG9_WR2RD_S_MASK 0x0000003FU -/*tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DLL. For configurations with MEMC_FREQ_RATIO=2, program - this to (tXMPDLL/2) and round it up to the next integer value. Present only in designs configured to support DDR4. Unit: Mult - ples of 32 clocks.*/ +/* +* tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DL + * L. For configurations with MEMC_FREQ_RATIO=2, program this to (tXMPDLL/2 + * ) and round it up to the next integer value. Present only in designs con + * figured to support DDR4. Unit: Multiples of 32 clocks. +*/ #undef DDRC_DRAMTMG11_POST_MPSM_GAP_X32_DEFVAL #undef DDRC_DRAMTMG11_POST_MPSM_GAP_X32_SHIFT #undef DDRC_DRAMTMG11_POST_MPSM_GAP_X32_MASK -#define DDRC_DRAMTMG11_POST_MPSM_GAP_X32_DEFVAL 0x440C021C -#define DDRC_DRAMTMG11_POST_MPSM_GAP_X32_SHIFT 24 -#define DDRC_DRAMTMG11_POST_MPSM_GAP_X32_MASK 0x7F000000U +#define DDRC_DRAMTMG11_POST_MPSM_GAP_X32_DEFVAL 0x440C021C +#define DDRC_DRAMTMG11_POST_MPSM_GAP_X32_SHIFT 24 +#define DDRC_DRAMTMG11_POST_MPSM_GAP_X32_MASK 0x7F000000U -/*tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge. For configurations with MEMC_FREQ_RATIO=2, program this t - RoundUp(tMPX_LH/2)+1. Present only in designs configured to support DDR4. Unit: clocks.*/ +/* +* tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge. For + * configurations with MEMC_FREQ_RATIO=2, program this to RoundUp(tMPX_LH/2 + * )+1. Present only in designs configured to support DDR4. Unit: clocks. +*/ #undef DDRC_DRAMTMG11_T_MPX_LH_DEFVAL #undef DDRC_DRAMTMG11_T_MPX_LH_SHIFT #undef DDRC_DRAMTMG11_T_MPX_LH_MASK -#define DDRC_DRAMTMG11_T_MPX_LH_DEFVAL 0x440C021C -#define DDRC_DRAMTMG11_T_MPX_LH_SHIFT 16 -#define DDRC_DRAMTMG11_T_MPX_LH_MASK 0x001F0000U +#define DDRC_DRAMTMG11_T_MPX_LH_DEFVAL 0x440C021C +#define DDRC_DRAMTMG11_T_MPX_LH_SHIFT 16 +#define DDRC_DRAMTMG11_T_MPX_LH_MASK 0x001F0000U -/*tMPX_S: Minimum time CS setup time to CKE. For configurations with MEMC_FREQ_RATIO=2, program this to (tMPX_S/2) and round it - up to the next integer value. Present only in designs configured to support DDR4. Unit: Clocks.*/ +/* +* tMPX_S: Minimum time CS setup time to CKE. For configurations with MEMC_ + * FREQ_RATIO=2, program this to (tMPX_S/2) and round it up to the next int + * eger value. Present only in designs configured to support DDR4. Unit: Cl + * ocks. +*/ #undef DDRC_DRAMTMG11_T_MPX_S_DEFVAL #undef DDRC_DRAMTMG11_T_MPX_S_SHIFT #undef DDRC_DRAMTMG11_T_MPX_S_MASK -#define DDRC_DRAMTMG11_T_MPX_S_DEFVAL 0x440C021C -#define DDRC_DRAMTMG11_T_MPX_S_SHIFT 8 -#define DDRC_DRAMTMG11_T_MPX_S_MASK 0x00000300U +#define DDRC_DRAMTMG11_T_MPX_S_DEFVAL 0x440C021C +#define DDRC_DRAMTMG11_T_MPX_S_SHIFT 8 +#define DDRC_DRAMTMG11_T_MPX_S_MASK 0x00000300U -/*tCKMPE: Minimum valid clock requirement after MPSM entry. Present only in designs configured to support DDR4. Unit: Clocks. F - r configurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next i - teger.*/ +/* +* tCKMPE: Minimum valid clock requirement after MPSM entry. Present only i + * n designs configured to support DDR4. Unit: Clocks. For configurations w + * ith MEMC_FREQ_RATIO=2, divide the value calculated using the above equat + * ion by 2, and round it up to next integer. +*/ #undef DDRC_DRAMTMG11_T_CKMPE_DEFVAL #undef DDRC_DRAMTMG11_T_CKMPE_SHIFT #undef DDRC_DRAMTMG11_T_CKMPE_MASK -#define DDRC_DRAMTMG11_T_CKMPE_DEFVAL 0x440C021C -#define DDRC_DRAMTMG11_T_CKMPE_SHIFT 0 -#define DDRC_DRAMTMG11_T_CKMPE_MASK 0x0000001FU +#define DDRC_DRAMTMG11_T_CKMPE_DEFVAL 0x440C021C +#define DDRC_DRAMTMG11_T_CKMPE_SHIFT 0 +#define DDRC_DRAMTMG11_T_CKMPE_MASK 0x0000001FU -/*tCMDCKE: Delay from valid command to CKE input LOW. Set this to the larger of tESCKE or tCMDCKE For configurations with MEMC_ - REQ_RATIO=2, program this to (max(tESCKE, tCMDCKE)/2) and round it up to next integer value.*/ +/* +* tCMDCKE: Delay from valid command to CKE input LOW. Set this to the larg + * er of tESCKE or tCMDCKE For configurations with MEMC_FREQ_RATIO=2, progr + * am this to (max(tESCKE, tCMDCKE)/2) and round it up to next integer valu + * e. +*/ #undef DDRC_DRAMTMG12_T_CMDCKE_DEFVAL #undef DDRC_DRAMTMG12_T_CMDCKE_SHIFT #undef DDRC_DRAMTMG12_T_CMDCKE_MASK -#define DDRC_DRAMTMG12_T_CMDCKE_DEFVAL 0x00020610 -#define DDRC_DRAMTMG12_T_CMDCKE_SHIFT 16 -#define DDRC_DRAMTMG12_T_CMDCKE_MASK 0x00030000U +#define DDRC_DRAMTMG12_T_CMDCKE_DEFVAL 0x00020610 +#define DDRC_DRAMTMG12_T_CMDCKE_SHIFT 16 +#define DDRC_DRAMTMG12_T_CMDCKE_MASK 0x00030000U -/*tCKEHCMD: Valid command requirement after CKE input HIGH. For configurations with MEMC_FREQ_RATIO=2, program this to (tCKEHCM - /2) and round it up to next integer value.*/ +/* +* tCKEHCMD: Valid command requirement after CKE input HIGH. For configurat + * ions with MEMC_FREQ_RATIO=2, program this to (tCKEHCMD/2) and round it u + * p to next integer value. +*/ #undef DDRC_DRAMTMG12_T_CKEHCMD_DEFVAL #undef DDRC_DRAMTMG12_T_CKEHCMD_SHIFT #undef DDRC_DRAMTMG12_T_CKEHCMD_MASK -#define DDRC_DRAMTMG12_T_CKEHCMD_DEFVAL 0x00020610 -#define DDRC_DRAMTMG12_T_CKEHCMD_SHIFT 8 -#define DDRC_DRAMTMG12_T_CKEHCMD_MASK 0x00000F00U +#define DDRC_DRAMTMG12_T_CKEHCMD_DEFVAL 0x00020610 +#define DDRC_DRAMTMG12_T_CKEHCMD_SHIFT 8 +#define DDRC_DRAMTMG12_T_CKEHCMD_MASK 0x00000F00U -/*tMRD_PDA: This is the Mode Register Set command cycle time in PDA mode. For configurations with MEMC_FREQ_RATIO=2, program th - s to (tMRD_PDA/2) and round it up to next integer value.*/ +/* +* tMRD_PDA: This is the Mode Register Set command cycle time in PDA mode. + * For configurations with MEMC_FREQ_RATIO=2, program this to (tMRD_PDA/2) + * and round it up to next integer value. +*/ #undef DDRC_DRAMTMG12_T_MRD_PDA_DEFVAL #undef DDRC_DRAMTMG12_T_MRD_PDA_SHIFT #undef DDRC_DRAMTMG12_T_MRD_PDA_MASK -#define DDRC_DRAMTMG12_T_MRD_PDA_DEFVAL 0x00020610 -#define DDRC_DRAMTMG12_T_MRD_PDA_SHIFT 0 -#define DDRC_DRAMTMG12_T_MRD_PDA_MASK 0x0000001FU +#define DDRC_DRAMTMG12_T_MRD_PDA_DEFVAL 0x00020610 +#define DDRC_DRAMTMG12_T_MRD_PDA_SHIFT 0 +#define DDRC_DRAMTMG12_T_MRD_PDA_MASK 0x0000001FU -/*- 1 - Disable uMCTL2 generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used instead to is - ue ZQ calibration request from APB module. - 0 - Internally generate ZQCS/MPC(ZQ calibration) commands based on ZQCTL1.t_zq_s - ort_interval_x1024. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.*/ +/* +* - 1 - Disable uMCTL2 generation of ZQCS/MPC(ZQ calibration) command. Reg + * ister DBGCMD.zq_calib_short can be used instead to issue ZQ calibration + * request from APB module. - 0 - Internally generate ZQCS/MPC(ZQ calibrati + * on) commands based on ZQCTL1.t_zq_short_interval_x1024. This is only pre + * sent for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. +*/ #undef DDRC_ZQCTL0_DIS_AUTO_ZQ_DEFVAL #undef DDRC_ZQCTL0_DIS_AUTO_ZQ_SHIFT #undef DDRC_ZQCTL0_DIS_AUTO_ZQ_MASK -#define DDRC_ZQCTL0_DIS_AUTO_ZQ_DEFVAL 0x02000040 -#define DDRC_ZQCTL0_DIS_AUTO_ZQ_SHIFT 31 -#define DDRC_ZQCTL0_DIS_AUTO_ZQ_MASK 0x80000000U +#define DDRC_ZQCTL0_DIS_AUTO_ZQ_DEFVAL 0x02000040 +#define DDRC_ZQCTL0_DIS_AUTO_ZQ_SHIFT 31 +#define DDRC_ZQCTL0_DIS_AUTO_ZQ_MASK 0x80000000U -/*- 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable when run in DDR3 - or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. - 0 - Enable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Power - own exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. This is only present for designs suppo - ting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.*/ +/* +* - 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refres + * h/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 + * or LPDDR3 or LPDDR4 mode. - 0 - Enable issuing of ZQCL/MPC(ZQ calibratio + * n) command at Self-Refresh/SR-Powerdown exit. Only applicable when run i + * n DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. This is only present + * for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. +*/ #undef DDRC_ZQCTL0_DIS_SRX_ZQCL_DEFVAL #undef DDRC_ZQCTL0_DIS_SRX_ZQCL_SHIFT #undef DDRC_ZQCTL0_DIS_SRX_ZQCL_MASK -#define DDRC_ZQCTL0_DIS_SRX_ZQCL_DEFVAL 0x02000040 -#define DDRC_ZQCTL0_DIS_SRX_ZQCL_SHIFT 30 -#define DDRC_ZQCTL0_DIS_SRX_ZQCL_MASK 0x40000000U +#define DDRC_ZQCTL0_DIS_SRX_ZQCL_DEFVAL 0x02000040 +#define DDRC_ZQCTL0_DIS_SRX_ZQCL_SHIFT 30 +#define DDRC_ZQCTL0_DIS_SRX_ZQCL_MASK 0x40000000U -/*- 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are sent to one r - nk at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to different ranks do not ov - rlap. - 0 - ZQ resistor is not shared. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.*/ +/* +* - 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQC + * L/ZQCS/MPC(ZQ calibration) commands are sent to one rank at a time with + * tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that co + * mmands to different ranks do not overlap. - 0 - ZQ resistor is not share + * d. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR + * 3/LPDDR4 devices. +*/ #undef DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_DEFVAL #undef DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_SHIFT #undef DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_MASK -#define DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_DEFVAL 0x02000040 -#define DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_SHIFT 29 -#define DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_MASK 0x20000000U +#define DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_DEFVAL 0x02000040 +#define DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_SHIFT 29 +#define DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_MASK 0x20000000U -/*- 1 - Disable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode. - 0 - Enable - ssuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode. This is only present for des - gns supporting DDR4 devices.*/ +/* +* - 1 - Disable issuing of ZQCL command at Maximum Power Saving Mode exit. + * Only applicable when run in DDR4 mode. - 0 - Enable issuing of ZQCL com + * mand at Maximum Power Saving Mode exit. Only applicable when run in DDR4 + * mode. This is only present for designs supporting DDR4 devices. +*/ #undef DDRC_ZQCTL0_DIS_MPSMX_ZQCL_DEFVAL #undef DDRC_ZQCTL0_DIS_MPSMX_ZQCL_SHIFT #undef DDRC_ZQCTL0_DIS_MPSMX_ZQCL_MASK -#define DDRC_ZQCTL0_DIS_MPSMX_ZQCL_DEFVAL 0x02000040 -#define DDRC_ZQCTL0_DIS_MPSMX_ZQCL_SHIFT 28 -#define DDRC_ZQCTL0_DIS_MPSMX_ZQCL_MASK 0x10000000U +#define DDRC_ZQCTL0_DIS_MPSMX_ZQCL_DEFVAL 0x02000040 +#define DDRC_ZQCTL0_DIS_MPSMX_ZQCL_SHIFT 28 +#define DDRC_ZQCTL0_DIS_MPSMX_ZQCL_MASK 0x10000000U -/*tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Number of cycles of NOP required after a ZQCL (ZQ calibrat - on long)/MPC(ZQ Start) command is issued to SDRAM. For configurations with MEMC_FREQ_RATIO=2: DDR3/DDR4: program this to tZQo - er/2 and round it up to the next integer value. LPDDR2/LPDDR3: program this to tZQCL/2 and round it up to the next integer va - ue. LPDDR4: program this to tZQCAL/2 and round it up to the next integer value. Unit: Clock cycles. This is only present for - esigns supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.*/ +/* +* tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Numbe + * r of cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ St + * art) command is issued to SDRAM. For configurations with MEMC_FREQ_RATIO + * =2: DDR3/DDR4: program this to tZQoper/2 and round it up to the next int + * eger value. LPDDR2/LPDDR3: program this to tZQCL/2 and round it up to th + * e next integer value. LPDDR4: program this to tZQCAL/2 and round it up t + * o the next integer value. Unit: Clock cycles. This is only present for d + * esigns supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. +*/ #undef DDRC_ZQCTL0_T_ZQ_LONG_NOP_DEFVAL #undef DDRC_ZQCTL0_T_ZQ_LONG_NOP_SHIFT #undef DDRC_ZQCTL0_T_ZQ_LONG_NOP_MASK -#define DDRC_ZQCTL0_T_ZQ_LONG_NOP_DEFVAL 0x02000040 -#define DDRC_ZQCTL0_T_ZQ_LONG_NOP_SHIFT 16 -#define DDRC_ZQCTL0_T_ZQ_LONG_NOP_MASK 0x07FF0000U +#define DDRC_ZQCTL0_T_ZQ_LONG_NOP_DEFVAL 0x02000040 +#define DDRC_ZQCTL0_T_ZQ_LONG_NOP_SHIFT 16 +#define DDRC_ZQCTL0_T_ZQ_LONG_NOP_MASK 0x07FF0000U -/*tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of cycles of NOP required after a ZQCS (ZQ calibration short)/MPC - ZQ Latch) command is issued to SDRAM. For configurations with MEMC_FREQ_RATIO=2, program this to tZQCS/2 and round it up to t - e next integer value. Unit: Clock cycles. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devic - s.*/ +/* +* tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of cycles of + * NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command + * is issued to SDRAM. For configurations with MEMC_FREQ_RATIO=2, program t + * his to tZQCS/2 and round it up to the next integer value. Unit: Clock cy + * cles. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LP + * DDR3/LPDDR4 devices. +*/ #undef DDRC_ZQCTL0_T_ZQ_SHORT_NOP_DEFVAL #undef DDRC_ZQCTL0_T_ZQ_SHORT_NOP_SHIFT #undef DDRC_ZQCTL0_T_ZQ_SHORT_NOP_MASK -#define DDRC_ZQCTL0_T_ZQ_SHORT_NOP_DEFVAL 0x02000040 -#define DDRC_ZQCTL0_T_ZQ_SHORT_NOP_SHIFT 0 -#define DDRC_ZQCTL0_T_ZQ_SHORT_NOP_MASK 0x000003FFU +#define DDRC_ZQCTL0_T_ZQ_SHORT_NOP_DEFVAL 0x02000040 +#define DDRC_ZQCTL0_T_ZQ_SHORT_NOP_SHIFT 0 +#define DDRC_ZQCTL0_T_ZQ_SHORT_NOP_MASK 0x000003FFU -/*tZQReset: Number of cycles of NOP required after a ZQReset (ZQ calibration Reset) command is issued to SDRAM. For configurati - ns with MEMC_FREQ_RATIO=2, program this to tZQReset/2 and round it up to the next integer value. Unit: Clock cycles. This is - nly present for designs supporting LPDDR2/LPDDR3/LPDDR4 devices.*/ +/* +* tZQReset: Number of cycles of NOP required after a ZQReset (ZQ calibrati + * on Reset) command is issued to SDRAM. For configurations with MEMC_FREQ_ + * RATIO=2, program this to tZQReset/2 and round it up to the next integer + * value. Unit: Clock cycles. This is only present for designs supporting L + * PDDR2/LPDDR3/LPDDR4 devices. +*/ #undef DDRC_ZQCTL1_T_ZQ_RESET_NOP_DEFVAL #undef DDRC_ZQCTL1_T_ZQ_RESET_NOP_SHIFT #undef DDRC_ZQCTL1_T_ZQ_RESET_NOP_MASK -#define DDRC_ZQCTL1_T_ZQ_RESET_NOP_DEFVAL 0x02000100 -#define DDRC_ZQCTL1_T_ZQ_RESET_NOP_SHIFT 20 -#define DDRC_ZQCTL1_T_ZQ_RESET_NOP_MASK 0x3FF00000U +#define DDRC_ZQCTL1_T_ZQ_RESET_NOP_DEFVAL 0x02000100 +#define DDRC_ZQCTL1_T_ZQ_RESET_NOP_SHIFT 20 +#define DDRC_ZQCTL1_T_ZQ_RESET_NOP_MASK 0x3FF00000U -/*Average interval to wait between automatically issuing ZQCS (ZQ calibration short)/MPC(ZQ calibration) commands to DDR3/DDR4/ - PDDR2/LPDDR3/LPDDR4 devices. Meaningless, if ZQCTL0.dis_auto_zq=1. Unit: 1024 clock cycles. This is only present for designs - upporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.*/ +/* +* Average interval to wait between automatically issuing ZQCS (ZQ calibrat + * ion short)/MPC(ZQ calibration) commands to DDR3/DDR4/LPDDR2/LPDDR3/LPDDR + * 4 devices. Meaningless, if ZQCTL0.dis_auto_zq=1. Unit: 1024 clock cycles + * . This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3 + * /LPDDR4 devices. +*/ #undef DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_DEFVAL #undef DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_SHIFT #undef DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_MASK -#define DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_DEFVAL 0x02000100 -#define DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_SHIFT 0 -#define DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_MASK 0x000FFFFFU +#define DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_DEFVAL 0x02000100 +#define DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_SHIFT 0 +#define DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_MASK 0x000FFFFFU -/*Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signa - s at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligne - , this timing parameter should be rounded up to the next integer value. Note that if using RDIMM, it is necessary to incremen - this parameter by RDIMM's extra cycle of latency in terms of DFI clock.*/ +/* +* Specifies the number of DFI clock cycles after an assertion or de-assert + * ion of the DFI control signals that the control signals at the PHY-DRAM + * interface reflect the assertion or de-assertion. If the DFI clock and th + * e memory clock are not phase-aligned, this timing parameter should be ro + * unded up to the next integer value. Note that if using RDIMM, it is nece + * ssary to increment this parameter by RDIMM's extra cycle of latency in t + * erms of DFI clock. +*/ #undef DDRC_DFITMG0_DFI_T_CTRL_DELAY_DEFVAL #undef DDRC_DFITMG0_DFI_T_CTRL_DELAY_SHIFT #undef DDRC_DFITMG0_DFI_T_CTRL_DELAY_MASK -#define DDRC_DFITMG0_DFI_T_CTRL_DELAY_DEFVAL 0x07020002 -#define DDRC_DFITMG0_DFI_T_CTRL_DELAY_SHIFT 24 -#define DDRC_DFITMG0_DFI_T_CTRL_DELAY_MASK 0x1F000000U +#define DDRC_DFITMG0_DFI_T_CTRL_DELAY_DEFVAL 0x07020002 +#define DDRC_DFITMG0_DFI_T_CTRL_DELAY_SHIFT 24 +#define DDRC_DFITMG0_DFI_T_CTRL_DELAY_MASK 0x1F000000U -/*Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR or SDR values Selects whether value in DFITM - 0.dfi_t_rddata_en is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles R - fer to PHY specification for correct value.*/ +/* +* Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated u + * sing HDR or SDR values Selects whether value in DFITMG0.dfi_t_rddata_en + * is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles + * - 1 in terms of SDR clock cycles Refer to PHY specification for correct + * value. +*/ #undef DDRC_DFITMG0_DFI_RDDATA_USE_SDR_DEFVAL #undef DDRC_DFITMG0_DFI_RDDATA_USE_SDR_SHIFT #undef DDRC_DFITMG0_DFI_RDDATA_USE_SDR_MASK -#define DDRC_DFITMG0_DFI_RDDATA_USE_SDR_DEFVAL 0x07020002 -#define DDRC_DFITMG0_DFI_RDDATA_USE_SDR_SHIFT 23 -#define DDRC_DFITMG0_DFI_RDDATA_USE_SDR_MASK 0x00800000U +#define DDRC_DFITMG0_DFI_RDDATA_USE_SDR_DEFVAL 0x07020002 +#define DDRC_DFITMG0_DFI_RDDATA_USE_SDR_SHIFT 23 +#define DDRC_DFITMG0_DFI_RDDATA_USE_SDR_MASK 0x00800000U -/*Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. Refer to PHY spe - ification for correct value. This corresponds to the DFI parameter trddata_en. Note that, depending on the PHY, if using RDIM - , it may be necessary to use the value (CL + 1) in the calculation of trddata_en. This is to compensate for the extra cycle o - latency through the RDIMM. Unit: Clocks*/ +/* +* Time from the assertion of a read command on the DFI interface to the as + * sertion of the dfi_rddata_en signal. Refer to PHY specification for corr + * ect value. This corresponds to the DFI parameter trddata_en. Note that, + * depending on the PHY, if using RDIMM, it may be necessary to use the val + * ue (CL + 1) in the calculation of trddata_en. This is to compensate for + * the extra cycle of latency through the RDIMM. Unit: Clocks +*/ #undef DDRC_DFITMG0_DFI_T_RDDATA_EN_DEFVAL #undef DDRC_DFITMG0_DFI_T_RDDATA_EN_SHIFT #undef DDRC_DFITMG0_DFI_T_RDDATA_EN_MASK -#define DDRC_DFITMG0_DFI_T_RDDATA_EN_DEFVAL 0x07020002 -#define DDRC_DFITMG0_DFI_T_RDDATA_EN_SHIFT 16 -#define DDRC_DFITMG0_DFI_T_RDDATA_EN_MASK 0x003F0000U +#define DDRC_DFITMG0_DFI_T_RDDATA_EN_DEFVAL 0x07020002 +#define DDRC_DFITMG0_DFI_T_RDDATA_EN_SHIFT 16 +#define DDRC_DFITMG0_DFI_T_RDDATA_EN_MASK 0x003F0000U -/*Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using HDR or SDR values Selects whether value in DFITMG - .dfi_tphy_wrlat is in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.dfi_tphy_wrdata is in terms of SDR or - HDR clock cycles - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles Refer to PHY specification for correct val - e.*/ +/* +* Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated us + * ing HDR or SDR values Selects whether value in DFITMG0.dfi_tphy_wrlat is + * in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.df + * i_tphy_wrdata is in terms of SDR or HDR clock cycles - 0 in terms of HDR + * clock cycles - 1 in terms of SDR clock cycles Refer to PHY specificatio + * n for correct value. +*/ #undef DDRC_DFITMG0_DFI_WRDATA_USE_SDR_DEFVAL #undef DDRC_DFITMG0_DFI_WRDATA_USE_SDR_SHIFT #undef DDRC_DFITMG0_DFI_WRDATA_USE_SDR_MASK -#define DDRC_DFITMG0_DFI_WRDATA_USE_SDR_DEFVAL 0x07020002 -#define DDRC_DFITMG0_DFI_WRDATA_USE_SDR_SHIFT 15 -#define DDRC_DFITMG0_DFI_WRDATA_USE_SDR_MASK 0x00008000U +#define DDRC_DFITMG0_DFI_WRDATA_USE_SDR_DEFVAL 0x07020002 +#define DDRC_DFITMG0_DFI_WRDATA_USE_SDR_SHIFT 15 +#define DDRC_DFITMG0_DFI_WRDATA_USE_SDR_MASK 0x00008000U -/*Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on th - dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. N - te, max supported value is 8. Unit: Clocks*/ +/* +* Specifies the number of clock cycles between when dfi_wrdata_en is asser + * ted to when the associated write data is driven on the dfi_wrdata signal + * . This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY + * specification for correct value. Note, max supported value is 8. Unit: + * Clocks +*/ #undef DDRC_DFITMG0_DFI_TPHY_WRDATA_DEFVAL #undef DDRC_DFITMG0_DFI_TPHY_WRDATA_SHIFT #undef DDRC_DFITMG0_DFI_TPHY_WRDATA_MASK -#define DDRC_DFITMG0_DFI_TPHY_WRDATA_DEFVAL 0x07020002 -#define DDRC_DFITMG0_DFI_TPHY_WRDATA_SHIFT 8 -#define DDRC_DFITMG0_DFI_TPHY_WRDATA_MASK 0x00003F00U +#define DDRC_DFITMG0_DFI_TPHY_WRDATA_DEFVAL 0x07020002 +#define DDRC_DFITMG0_DFI_TPHY_WRDATA_SHIFT 8 +#define DDRC_DFITMG0_DFI_TPHY_WRDATA_MASK 0x00003F00U -/*Write latency Number of clocks from the write command to write data enable (dfi_wrdata_en). This corresponds to the DFI timin - parameter tphy_wrlat. Refer to PHY specification for correct value.Note that, depending on the PHY, if using RDIMM, it may b - necessary to use the value (CL + 1) in the calculation of tphy_wrlat. This is to compensate for the extra cycle of latency t - rough the RDIMM.*/ +/* +* Write latency Number of clocks from the write command to write data enab + * le (dfi_wrdata_en). This corresponds to the DFI timing parameter tphy_wr + * lat. Refer to PHY specification for correct value.Note that, depending o + * n the PHY, if using RDIMM, it may be necessary to use the value (CL + 1) + * in the calculation of tphy_wrlat. This is to compensate for the extra c + * ycle of latency through the RDIMM. +*/ #undef DDRC_DFITMG0_DFI_TPHY_WRLAT_DEFVAL #undef DDRC_DFITMG0_DFI_TPHY_WRLAT_SHIFT #undef DDRC_DFITMG0_DFI_TPHY_WRLAT_MASK -#define DDRC_DFITMG0_DFI_TPHY_WRLAT_DEFVAL 0x07020002 -#define DDRC_DFITMG0_DFI_TPHY_WRLAT_SHIFT 0 -#define DDRC_DFITMG0_DFI_TPHY_WRLAT_MASK 0x0000003FU +#define DDRC_DFITMG0_DFI_TPHY_WRLAT_DEFVAL 0x07020002 +#define DDRC_DFITMG0_DFI_TPHY_WRLAT_SHIFT 0 +#define DDRC_DFITMG0_DFI_TPHY_WRLAT_MASK 0x0000003FU -/*Specifies the number of DFI PHY clocks between when the dfi_cs signal is asserted and when the associated command is driven. - his field is used for CAL mode, should be set to '0' or the value which matches the CAL mode register setting in the DRAM. If - the PHY can add the latency for CAL mode, this should be set to '0'. Valid Range: 0, 3, 4, 5, 6, and 8*/ +/* +* Specifies the number of DFI PHY clocks between when the dfi_cs signal is + * asserted and when the associated command is driven. This field is used + * for CAL mode, should be set to '0' or the value which matches the CAL mo + * de register setting in the DRAM. If the PHY can add the latency for CAL + * mode, this should be set to '0'. Valid Range: 0, 3, 4, 5, 6, and 8 +*/ #undef DDRC_DFITMG1_DFI_T_CMD_LAT_DEFVAL #undef DDRC_DFITMG1_DFI_T_CMD_LAT_SHIFT #undef DDRC_DFITMG1_DFI_T_CMD_LAT_MASK -#define DDRC_DFITMG1_DFI_T_CMD_LAT_DEFVAL 0x00000404 -#define DDRC_DFITMG1_DFI_T_CMD_LAT_SHIFT 28 -#define DDRC_DFITMG1_DFI_T_CMD_LAT_MASK 0xF0000000U +#define DDRC_DFITMG1_DFI_T_CMD_LAT_DEFVAL 0x00000404 +#define DDRC_DFITMG1_DFI_T_CMD_LAT_SHIFT 28 +#define DDRC_DFITMG1_DFI_T_CMD_LAT_MASK 0xF0000000U -/*Specifies the number of DFI PHY clocks between when the dfi_cs signal is asserted and when the associated dfi_parity_in signa - is driven.*/ +/* +* Specifies the number of DFI PHY clocks between when the dfi_cs signal is + * asserted and when the associated dfi_parity_in signal is driven. +*/ #undef DDRC_DFITMG1_DFI_T_PARIN_LAT_DEFVAL #undef DDRC_DFITMG1_DFI_T_PARIN_LAT_SHIFT #undef DDRC_DFITMG1_DFI_T_PARIN_LAT_MASK -#define DDRC_DFITMG1_DFI_T_PARIN_LAT_DEFVAL 0x00000404 -#define DDRC_DFITMG1_DFI_T_PARIN_LAT_SHIFT 24 -#define DDRC_DFITMG1_DFI_T_PARIN_LAT_MASK 0x03000000U +#define DDRC_DFITMG1_DFI_T_PARIN_LAT_DEFVAL 0x00000404 +#define DDRC_DFITMG1_DFI_T_PARIN_LAT_SHIFT 24 +#define DDRC_DFITMG1_DFI_T_PARIN_LAT_MASK 0x03000000U -/*Specifies the number of DFI clocks between when the dfi_wrdata_en signal is asserted and when the corresponding write data tr - nsfer is completed on the DRAM bus. This corresponds to the DFI timing parameter twrdata_delay. Refer to PHY specification fo - correct value. For DFI 3.0 PHY, set to twrdata_delay, a new timing parameter introduced in DFI 3.0. For DFI 2.1 PHY, set to - phy_wrdata + (delay of DFI write data to the DRAM). Value to be programmed is in terms of DFI clocks, not PHY clocks. In FREQ - RATIO=2, divide PHY's value by 2 and round up to next integer. If using DFITMG0.dfi_wrdata_use_sdr=1, add 1 to the value. Uni - : Clocks*/ +/* +* Specifies the number of DFI clocks between when the dfi_wrdata_en signal + * is asserted and when the corresponding write data transfer is completed + * on the DRAM bus. This corresponds to the DFI timing parameter twrdata_d + * elay. Refer to PHY specification for correct value. For DFI 3.0 PHY, set + * to twrdata_delay, a new timing parameter introduced in DFI 3.0. For DFI + * 2.1 PHY, set to tphy_wrdata + (delay of DFI write data to the DRAM). Va + * lue to be programmed is in terms of DFI clocks, not PHY clocks. In FREQ_ + * RATIO=2, divide PHY's value by 2 and round up to next integer. If using + * DFITMG0.dfi_wrdata_use_sdr=1, add 1 to the value. Unit: Clocks +*/ #undef DDRC_DFITMG1_DFI_T_WRDATA_DELAY_DEFVAL #undef DDRC_DFITMG1_DFI_T_WRDATA_DELAY_SHIFT #undef DDRC_DFITMG1_DFI_T_WRDATA_DELAY_MASK -#define DDRC_DFITMG1_DFI_T_WRDATA_DELAY_DEFVAL 0x00000404 -#define DDRC_DFITMG1_DFI_T_WRDATA_DELAY_SHIFT 16 -#define DDRC_DFITMG1_DFI_T_WRDATA_DELAY_MASK 0x001F0000U +#define DDRC_DFITMG1_DFI_T_WRDATA_DELAY_DEFVAL 0x00000404 +#define DDRC_DFITMG1_DFI_T_WRDATA_DELAY_SHIFT 16 +#define DDRC_DFITMG1_DFI_T_WRDATA_DELAY_MASK 0x001F0000U -/*Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to - he DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase - ligned, this timing parameter should be rounded up to the next integer value.*/ +/* +* Specifies the number of DFI clock cycles from the assertion of the dfi_d + * ram_clk_disable signal on the DFI until the clock to the DRAM memory dev + * ices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock + * and the memory clock are not phase aligned, this timing parameter should + * be rounded up to the next integer value. +*/ #undef DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_DEFVAL #undef DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_SHIFT #undef DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_MASK -#define DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_DEFVAL 0x00000404 -#define DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_SHIFT 8 -#define DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_MASK 0x00000F00U +#define DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_DEFVAL 0x00000404 +#define DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_SHIFT 8 +#define DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_MASK 0x00000F00U -/*Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first - alid rising edge of the clock to the DRAM memory devices, at the PHY-DRAM boundary. If the DFI clock and the memory clock are - not phase aligned, this timing parameter should be rounded up to the next integer value.*/ +/* +* Specifies the number of DFI clock cycles from the de-assertion of the df + * i_dram_clk_disable signal on the DFI until the first valid rising edge o + * f the clock to the DRAM memory devices, at the PHY-DRAM boundary. If the + * DFI clock and the memory clock are not phase aligned, this timing param + * eter should be rounded up to the next integer value. +*/ #undef DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_DEFVAL #undef DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_SHIFT #undef DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_MASK -#define DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_DEFVAL 0x00000404 -#define DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_SHIFT 0 -#define DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_MASK 0x0000000FU +#define DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_DEFVAL 0x00000404 +#define DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_SHIFT 0 +#define DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_MASK 0x0000000FU -/*Setting for DFI's tlp_resp time. Same value is used for both Power Down, Self Refresh, Deep Power Down and Maximum Power Savi - g modes. DFI 2.1 specification onwards, recommends using a fixed value of 7 always.*/ +/* +* Setting for DFI's tlp_resp time. Same value is used for both Power Down, + * Self Refresh, Deep Power Down and Maximum Power Saving modes. DFI 2.1 s + * pecification onwards, recommends using a fixed value of 7 always. +*/ #undef DDRC_DFILPCFG0_DFI_TLP_RESP_DEFVAL #undef DDRC_DFILPCFG0_DFI_TLP_RESP_SHIFT #undef DDRC_DFILPCFG0_DFI_TLP_RESP_MASK -#define DDRC_DFILPCFG0_DFI_TLP_RESP_DEFVAL 0x07000000 -#define DDRC_DFILPCFG0_DFI_TLP_RESP_SHIFT 24 -#define DDRC_DFILPCFG0_DFI_TLP_RESP_MASK 0x0F000000U +#define DDRC_DFILPCFG0_DFI_TLP_RESP_DEFVAL 0x07000000 +#define DDRC_DFILPCFG0_DFI_TLP_RESP_SHIFT 24 +#define DDRC_DFILPCFG0_DFI_TLP_RESP_MASK 0x0F000000U -/*Value to drive on dfi_lp_wakeup signal when Deep Power Down mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 - cycles - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles - 0x7 - - 2048 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0xD - - 31072 cycles - 0xE - 262144 cycles - 0xF - Unlimited This is only present for designs supporting mDDR or LPDDR2/LPDDR3 device - .*/ +/* +* Value to drive on dfi_lp_wakeup signal when Deep Power Down mode is ente + * red. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32 + * cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 5 + * 12 cycles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycles - + * 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 6553 + * 6 cycles - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited T + * his is only present for designs supporting mDDR or LPDDR2/LPDDR3 devices + * . +*/ #undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_DEFVAL #undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_SHIFT #undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_MASK -#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_DEFVAL 0x07000000 -#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_SHIFT 20 -#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_MASK 0x00F00000U +#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_DEFVAL 0x07000000 +#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_SHIFT 20 +#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_MASK 0x00F00000U -/*Enables DFI Low Power interface handshaking during Deep Power Down Entry/Exit. - 0 - Disabled - 1 - Enabled This is only pres - nt for designs supporting mDDR or LPDDR2/LPDDR3 devices.*/ +/* +* Enables DFI Low Power interface handshaking during Deep Power Down Entry + * /Exit. - 0 - Disabled - 1 - Enabled This is only present for designs sup + * porting mDDR or LPDDR2/LPDDR3 devices. +*/ #undef DDRC_DFILPCFG0_DFI_LP_EN_DPD_DEFVAL #undef DDRC_DFILPCFG0_DFI_LP_EN_DPD_SHIFT #undef DDRC_DFILPCFG0_DFI_LP_EN_DPD_MASK -#define DDRC_DFILPCFG0_DFI_LP_EN_DPD_DEFVAL 0x07000000 -#define DDRC_DFILPCFG0_DFI_LP_EN_DPD_SHIFT 16 -#define DDRC_DFILPCFG0_DFI_LP_EN_DPD_MASK 0x00010000U +#define DDRC_DFILPCFG0_DFI_LP_EN_DPD_DEFVAL 0x07000000 +#define DDRC_DFILPCFG0_DFI_LP_EN_DPD_SHIFT 16 +#define DDRC_DFILPCFG0_DFI_LP_EN_DPD_MASK 0x00010000U -/*Value to drive on dfi_lp_wakeup signal when Self Refresh mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cy - les - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles - 0x7 - - 048 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0xD - 131 - 72 cycles - 0xE - 262144 cycles - 0xF - Unlimited*/ +/* +* Value to drive on dfi_lp_wakeup signal when Self Refresh mode is entered + * . Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32 cyc + * les - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 + * cycles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycles - 0x9 + * - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 c + * ycles - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited +*/ #undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_DEFVAL #undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_SHIFT #undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_MASK -#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_DEFVAL 0x07000000 -#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_SHIFT 12 -#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_MASK 0x0000F000U +#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_DEFVAL 0x07000000 +#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_SHIFT 12 +#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_MASK 0x0000F000U -/*Enables DFI Low Power interface handshaking during Self Refresh Entry/Exit. - 0 - Disabled - 1 - Enabled*/ +/* +* Enables DFI Low Power interface handshaking during Self Refresh Entry/Ex + * it. - 0 - Disabled - 1 - Enabled +*/ #undef DDRC_DFILPCFG0_DFI_LP_EN_SR_DEFVAL #undef DDRC_DFILPCFG0_DFI_LP_EN_SR_SHIFT #undef DDRC_DFILPCFG0_DFI_LP_EN_SR_MASK -#define DDRC_DFILPCFG0_DFI_LP_EN_SR_DEFVAL 0x07000000 -#define DDRC_DFILPCFG0_DFI_LP_EN_SR_SHIFT 8 -#define DDRC_DFILPCFG0_DFI_LP_EN_SR_MASK 0x00000100U +#define DDRC_DFILPCFG0_DFI_LP_EN_SR_DEFVAL 0x07000000 +#define DDRC_DFILPCFG0_DFI_LP_EN_SR_SHIFT 8 +#define DDRC_DFILPCFG0_DFI_LP_EN_SR_MASK 0x00000100U -/*Value to drive on dfi_lp_wakeup signal when Power Down mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycl - s - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles - 0x7 - 20 - 8 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0xD - 13107 - cycles - 0xE - 262144 cycles - 0xF - Unlimited*/ +/* +* Value to drive on dfi_lp_wakeup signal when Power Down mode is entered. + * Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32 cycle + * s - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cy + * cles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycles - 0x9 - + * 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cyc + * les - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited +*/ #undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_DEFVAL #undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_SHIFT #undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_MASK -#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_DEFVAL 0x07000000 -#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_SHIFT 4 -#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_MASK 0x000000F0U +#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_DEFVAL 0x07000000 +#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_SHIFT 4 +#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_MASK 0x000000F0U -/*Enables DFI Low Power interface handshaking during Power Down Entry/Exit. - 0 - Disabled - 1 - Enabled*/ +/* +* Enables DFI Low Power interface handshaking during Power Down Entry/Exit + * . - 0 - Disabled - 1 - Enabled +*/ #undef DDRC_DFILPCFG0_DFI_LP_EN_PD_DEFVAL #undef DDRC_DFILPCFG0_DFI_LP_EN_PD_SHIFT #undef DDRC_DFILPCFG0_DFI_LP_EN_PD_MASK -#define DDRC_DFILPCFG0_DFI_LP_EN_PD_DEFVAL 0x07000000 -#define DDRC_DFILPCFG0_DFI_LP_EN_PD_SHIFT 0 -#define DDRC_DFILPCFG0_DFI_LP_EN_PD_MASK 0x00000001U +#define DDRC_DFILPCFG0_DFI_LP_EN_PD_DEFVAL 0x07000000 +#define DDRC_DFILPCFG0_DFI_LP_EN_PD_SHIFT 0 +#define DDRC_DFILPCFG0_DFI_LP_EN_PD_MASK 0x00000001U -/*Value to drive on dfi_lp_wakeup signal when Maximum Power Saving Mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - - 16 cycles - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0 - D - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited This is only present for designs supporting DDR4 devices.*/ +/* +* Value to drive on dfi_lp_wakeup signal when Maximum Power Saving Mode is + * entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 + * - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x + * 5 - 512 cycles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycl + * es - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - + * 65536 cycles - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimi + * ted This is only present for designs supporting DDR4 devices. +*/ #undef DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_DEFVAL #undef DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_SHIFT #undef DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_MASK -#define DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_DEFVAL 0x00000000 -#define DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_SHIFT 4 -#define DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_MASK 0x000000F0U +#define DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_DEFVAL 0x00000000 +#define DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_SHIFT 4 +#define DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_MASK 0x000000F0U -/*Enables DFI Low Power interface handshaking during Maximum Power Saving Mode Entry/Exit. - 0 - Disabled - 1 - Enabled This is - only present for designs supporting DDR4 devices.*/ +/* +* Enables DFI Low Power interface handshaking during Maximum Power Saving + * Mode Entry/Exit. - 0 - Disabled - 1 - Enabled This is only present for d + * esigns supporting DDR4 devices. +*/ #undef DDRC_DFILPCFG1_DFI_LP_EN_MPSM_DEFVAL #undef DDRC_DFILPCFG1_DFI_LP_EN_MPSM_SHIFT #undef DDRC_DFILPCFG1_DFI_LP_EN_MPSM_MASK -#define DDRC_DFILPCFG1_DFI_LP_EN_MPSM_DEFVAL 0x00000000 -#define DDRC_DFILPCFG1_DFI_LP_EN_MPSM_SHIFT 0 -#define DDRC_DFILPCFG1_DFI_LP_EN_MPSM_MASK 0x00000001U +#define DDRC_DFILPCFG1_DFI_LP_EN_MPSM_DEFVAL 0x00000000 +#define DDRC_DFILPCFG1_DFI_LP_EN_MPSM_SHIFT 0 +#define DDRC_DFILPCFG1_DFI_LP_EN_MPSM_MASK 0x00000001U -/*This is the minimum amount of time between uMCTL2 initiated DFI update requests (which is executed whenever the uMCTL2 is idl - ). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the fir - t read request when the uMCTL2 is idle. Unit: 1024 clocks*/ +/* +* When '1', disable the automatic dfi_ctrlupd_req generation by the uMCTL2 + * . The core must issue the dfi_ctrlupd_req signal using register reg_ddrc + * _ctrlupd. When '0', uMCTL2 issues dfi_ctrlupd_req periodically. +*/ +#undef DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_DEFVAL +#undef DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SHIFT +#undef DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_MASK +#define DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_DEFVAL 0x00400003 +#define DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SHIFT 31 +#define DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_MASK 0x80000000U + +/* +* When '1', disable the automatic dfi_ctrlupd_req generation by the uMCTL2 + * following a self-refresh exit. The core must issue the dfi_ctrlupd_req + * signal using register reg_ddrc_ctrlupd. When '0', uMCTL2 issues a dfi_ct + * rlupd_req after exiting self-refresh. +*/ +#undef DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_DEFVAL +#undef DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_SHIFT +#undef DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_MASK +#define DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_DEFVAL 0x00400003 +#define DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_SHIFT 30 +#define DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_MASK 0x40000000U + +/* +* Specifies the maximum number of clock cycles that the dfi_ctrlupd_req si + * gnal can assert. Lowest value to assign to this variable is 0x40. Unit: + * Clocks +*/ +#undef DDRC_DFIUPD0_DFI_T_CTRLUP_MAX_DEFVAL +#undef DDRC_DFIUPD0_DFI_T_CTRLUP_MAX_SHIFT +#undef DDRC_DFIUPD0_DFI_T_CTRLUP_MAX_MASK +#define DDRC_DFIUPD0_DFI_T_CTRLUP_MAX_DEFVAL 0x00400003 +#define DDRC_DFIUPD0_DFI_T_CTRLUP_MAX_SHIFT 16 +#define DDRC_DFIUPD0_DFI_T_CTRLUP_MAX_MASK 0x03FF0000U + +/* +* Specifies the minimum number of clock cycles that the dfi_ctrlupd_req si + * gnal must be asserted. The uMCTL2 expects the PHY to respond within this + * time. If the PHY does not respond, the uMCTL2 will de-assert dfi_ctrlup + * d_req after dfi_t_ctrlup_min + 2 cycles. Lowest value to assign to this + * variable is 0x3. Unit: Clocks +*/ +#undef DDRC_DFIUPD0_DFI_T_CTRLUP_MIN_DEFVAL +#undef DDRC_DFIUPD0_DFI_T_CTRLUP_MIN_SHIFT +#undef DDRC_DFIUPD0_DFI_T_CTRLUP_MIN_MASK +#define DDRC_DFIUPD0_DFI_T_CTRLUP_MIN_DEFVAL 0x00400003 +#define DDRC_DFIUPD0_DFI_T_CTRLUP_MIN_SHIFT 0 +#define DDRC_DFIUPD0_DFI_T_CTRLUP_MIN_MASK 0x000003FFU + +/* +* This is the minimum amount of time between uMCTL2 initiated DFI update r + * equests (which is executed whenever the uMCTL2 is idle). Set this number + * higher to reduce the frequency of update requests, which can have a sma + * ll impact on the latency of the first read request when the uMCTL2 is id + * le. Unit: 1024 clocks +*/ #undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_DEFVAL #undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_SHIFT #undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_MASK -#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_DEFVAL 0x00000000 -#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_SHIFT 16 -#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_MASK 0x00FF0000U +#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_DEFVAL 0x00000000 +#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_SHIFT 16 +#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_MASK 0x00FF0000U -/*This is the maximum amount of time between uMCTL2 initiated DFI update requests. This timer resets with each update request; - hen the timer expires dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd_ackx is received. PHY can use this - idle time to recalibrate the delay lines to the DLLs. The DFI controller update is also used to reset PHY FIFO pointers in ca - e of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. - Note: Value programmed for DFIUPD1.dfi_t_ctrlupd_interval_max_x1024 must be greater than DFIUPD1.dfi_t_ctrlupd_interval_min_x - 024. Unit: 1024 clocks*/ +/* +* This is the maximum amount of time between uMCTL2 initiated DFI update r + * equests. This timer resets with each update request; when the timer expi + * res dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd + * _ackx is received. PHY can use this idle time to recalibrate the delay l + * ines to the DLLs. The DFI controller update is also used to reset PHY FI + * FO pointers in case of data capture errors. Updates are required to main + * tain calibration over PVT, but frequent updates may impact performance. + * Note: Value programmed for DFIUPD1.dfi_t_ctrlupd_interval_max_x1024 must + * be greater than DFIUPD1.dfi_t_ctrlupd_interval_min_x1024. Unit: 1024 cl + * ocks +*/ #undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_DEFVAL #undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_SHIFT #undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_MASK -#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_DEFVAL 0x00000000 -#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_SHIFT 0 -#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_MASK 0x000000FFU +#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_DEFVAL 0x00000000 +#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_SHIFT 0 +#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_MASK 0x000000FFU -/*Defines polarity of dfi_wrdata_cs and dfi_rddata_cs signals. - 0: Signals are active low - 1: Signals are active high*/ +/* +* Defines polarity of dfi_wrdata_cs and dfi_rddata_cs signals. - 0: Signal + * s are active low - 1: Signals are active high +*/ #undef DDRC_DFIMISC_DFI_DATA_CS_POLARITY_DEFVAL #undef DDRC_DFIMISC_DFI_DATA_CS_POLARITY_SHIFT #undef DDRC_DFIMISC_DFI_DATA_CS_POLARITY_MASK -#define DDRC_DFIMISC_DFI_DATA_CS_POLARITY_DEFVAL 0x00000001 -#define DDRC_DFIMISC_DFI_DATA_CS_POLARITY_SHIFT 2 -#define DDRC_DFIMISC_DFI_DATA_CS_POLARITY_MASK 0x00000004U +#define DDRC_DFIMISC_DFI_DATA_CS_POLARITY_DEFVAL 0x00000001 +#define DDRC_DFIMISC_DFI_DATA_CS_POLARITY_SHIFT 2 +#define DDRC_DFIMISC_DFI_DATA_CS_POLARITY_MASK 0x00000004U -/*DBI implemented in DDRC or PHY. - 0 - DDRC implements DBI functionality. - 1 - PHY implements DBI functionality. Present only - in designs configured to support DDR4 and LPDDR4.*/ +/* +* DBI implemented in DDRC or PHY. - 0 - DDRC implements DBI functionality. + * - 1 - PHY implements DBI functionality. Present only in designs configu + * red to support DDR4 and LPDDR4. +*/ #undef DDRC_DFIMISC_PHY_DBI_MODE_DEFVAL #undef DDRC_DFIMISC_PHY_DBI_MODE_SHIFT #undef DDRC_DFIMISC_PHY_DBI_MODE_MASK -#define DDRC_DFIMISC_PHY_DBI_MODE_DEFVAL 0x00000001 -#define DDRC_DFIMISC_PHY_DBI_MODE_SHIFT 1 -#define DDRC_DFIMISC_PHY_DBI_MODE_MASK 0x00000002U +#define DDRC_DFIMISC_PHY_DBI_MODE_DEFVAL 0x00000001 +#define DDRC_DFIMISC_PHY_DBI_MODE_SHIFT 1 +#define DDRC_DFIMISC_PHY_DBI_MODE_MASK 0x00000002U -/*PHY initialization complete enable signal. When asserted the dfi_init_complete signal can be used to trigger SDRAM initialisa - ion*/ +/* +* PHY initialization complete enable signal. When asserted the dfi_init_co + * mplete signal can be used to trigger SDRAM initialisation +*/ #undef DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_DEFVAL #undef DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_SHIFT #undef DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_MASK -#define DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_DEFVAL 0x00000001 -#define DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_SHIFT 0 -#define DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_MASK 0x00000001U +#define DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_DEFVAL 0x00000001 +#define DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_SHIFT 0 +#define DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_MASK 0x00000001U -/*>Number of clocks between when a read command is sent on the DFI control interface and when the associated dfi_rddata_cs sign - l is asserted. This corresponds to the DFI timing parameter tphy_rdcslat. Refer to PHY specification for correct value.*/ +/* +* >Number of clocks between when a read command is sent on the DFI control + * interface and when the associated dfi_rddata_cs signal is asserted. Thi + * s corresponds to the DFI timing parameter tphy_rdcslat. Refer to PHY spe + * cification for correct value. +*/ #undef DDRC_DFITMG2_DFI_TPHY_RDCSLAT_DEFVAL #undef DDRC_DFITMG2_DFI_TPHY_RDCSLAT_SHIFT #undef DDRC_DFITMG2_DFI_TPHY_RDCSLAT_MASK -#define DDRC_DFITMG2_DFI_TPHY_RDCSLAT_DEFVAL 0x00000202 -#define DDRC_DFITMG2_DFI_TPHY_RDCSLAT_SHIFT 8 -#define DDRC_DFITMG2_DFI_TPHY_RDCSLAT_MASK 0x00003F00U +#define DDRC_DFITMG2_DFI_TPHY_RDCSLAT_DEFVAL 0x00000202 +#define DDRC_DFITMG2_DFI_TPHY_RDCSLAT_SHIFT 8 +#define DDRC_DFITMG2_DFI_TPHY_RDCSLAT_MASK 0x00003F00U -/*Number of clocks between when a write command is sent on the DFI control interface and when the associated dfi_wrdata_cs sign - l is asserted. This corresponds to the DFI timing parameter tphy_wrcslat. Refer to PHY specification for correct value.*/ +/* +* Number of clocks between when a write command is sent on the DFI control + * interface and when the associated dfi_wrdata_cs signal is asserted. Thi + * s corresponds to the DFI timing parameter tphy_wrcslat. Refer to PHY spe + * cification for correct value. +*/ #undef DDRC_DFITMG2_DFI_TPHY_WRCSLAT_DEFVAL #undef DDRC_DFITMG2_DFI_TPHY_WRCSLAT_SHIFT #undef DDRC_DFITMG2_DFI_TPHY_WRCSLAT_MASK -#define DDRC_DFITMG2_DFI_TPHY_WRCSLAT_DEFVAL 0x00000202 -#define DDRC_DFITMG2_DFI_TPHY_WRCSLAT_SHIFT 0 -#define DDRC_DFITMG2_DFI_TPHY_WRCSLAT_MASK 0x0000003FU +#define DDRC_DFITMG2_DFI_TPHY_WRCSLAT_DEFVAL 0x00000202 +#define DDRC_DFITMG2_DFI_TPHY_WRCSLAT_SHIFT 0 +#define DDRC_DFITMG2_DFI_TPHY_WRCSLAT_MASK 0x0000003FU -/*Read DBI enable signal in DDRC. - 0 - Read DBI is disabled. - 1 - Read DBI is enabled. This signal must be set the same value - as DRAM's mode register. - DDR4: MR5 bit A12. When x4 devices are used, this signal must be set to 0. - LPDDR4: MR3[6]*/ +/* +* Read DBI enable signal in DDRC. - 0 - Read DBI is disabled. - 1 - Read D + * BI is enabled. This signal must be set the same value as DRAM's mode reg + * ister. - DDR4: MR5 bit A12. When x4 devices are used, this signal must b + * e set to 0. - LPDDR4: MR3[6] +*/ #undef DDRC_DBICTL_RD_DBI_EN_DEFVAL #undef DDRC_DBICTL_RD_DBI_EN_SHIFT #undef DDRC_DBICTL_RD_DBI_EN_MASK -#define DDRC_DBICTL_RD_DBI_EN_DEFVAL 0x00000001 -#define DDRC_DBICTL_RD_DBI_EN_SHIFT 2 -#define DDRC_DBICTL_RD_DBI_EN_MASK 0x00000004U +#define DDRC_DBICTL_RD_DBI_EN_DEFVAL 0x00000001 +#define DDRC_DBICTL_RD_DBI_EN_SHIFT 2 +#define DDRC_DBICTL_RD_DBI_EN_MASK 0x00000004U -/*Write DBI enable signal in DDRC. - 0 - Write DBI is disabled. - 1 - Write DBI is enabled. This signal must be set the same va - ue as DRAM's mode register. - DDR4: MR5 bit A11. When x4 devices are used, this signal must be set to 0. - LPDDR4: MR3[7]*/ +/* +* Write DBI enable signal in DDRC. - 0 - Write DBI is disabled. - 1 - Writ + * e DBI is enabled. This signal must be set the same value as DRAM's mode + * register. - DDR4: MR5 bit A11. When x4 devices are used, this signal mus + * t be set to 0. - LPDDR4: MR3[7] +*/ #undef DDRC_DBICTL_WR_DBI_EN_DEFVAL #undef DDRC_DBICTL_WR_DBI_EN_SHIFT #undef DDRC_DBICTL_WR_DBI_EN_MASK -#define DDRC_DBICTL_WR_DBI_EN_DEFVAL 0x00000001 -#define DDRC_DBICTL_WR_DBI_EN_SHIFT 1 -#define DDRC_DBICTL_WR_DBI_EN_MASK 0x00000002U +#define DDRC_DBICTL_WR_DBI_EN_DEFVAL 0x00000001 +#define DDRC_DBICTL_WR_DBI_EN_SHIFT 1 +#define DDRC_DBICTL_WR_DBI_EN_MASK 0x00000002U -/*DM enable signal in DDRC. - 0 - DM is disabled. - 1 - DM is enabled. This signal must be set the same logical value as DRAM's - mode register. - DDR4: Set this to same value as MR5 bit A10. When x4 devices are used, this signal must be set to 0. - LPDDR - : Set this to inverted value of MR13[5] which is opposite polarity from this signal*/ +/* +* DM enable signal in DDRC. - 0 - DM is disabled. - 1 - DM is enabled. Thi + * s signal must be set the same logical value as DRAM's mode register. - D + * DR4: Set this to same value as MR5 bit A10. When x4 devices are used, th + * is signal must be set to 0. - LPDDR4: Set this to inverted value of MR13 + * [5] which is opposite polarity from this signal +*/ #undef DDRC_DBICTL_DM_EN_DEFVAL #undef DDRC_DBICTL_DM_EN_SHIFT #undef DDRC_DBICTL_DM_EN_MASK -#define DDRC_DBICTL_DM_EN_DEFVAL 0x00000001 -#define DDRC_DBICTL_DM_EN_SHIFT 0 -#define DDRC_DBICTL_DM_EN_MASK 0x00000001U +#define DDRC_DBICTL_DM_EN_DEFVAL 0x00000001 +#define DDRC_DBICTL_DM_EN_SHIFT 0 +#define DDRC_DBICTL_DM_EN_MASK 0x00000001U -/*Selects the HIF address bit used as rank address bit 0. Valid Range: 0 to 27, and 31 Internal Base: 6 The selected HIF addres - bit is determined by adding the internal base to the value of this field. If set to 31, rank address bit 0 is set to 0.*/ +/* +* Selects the HIF address bit used as rank address bit 0. Valid Range: 0 t + * o 27, and 31 Internal Base: 6 The selected HIF address bit is determined + * by adding the internal base to the value of this field. If set to 31, r + * ank address bit 0 is set to 0. +*/ #undef DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_DEFVAL #undef DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_SHIFT #undef DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_MASK -#define DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_DEFVAL -#define DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_SHIFT 0 -#define DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_MASK 0x0000001FU +#define DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_DEFVAL +#define DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_SHIFT 0 +#define DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_MASK 0x0000001FU -/*Selects the HIF address bit used as bank address bit 2. Valid Range: 0 to 29 and 31 Internal Base: 4 The selected HIF address - bit is determined by adding the internal base to the value of this field. If set to 31, bank address bit 2 is set to 0.*/ +/* +* Selects the HIF address bit used as bank address bit 2. Valid Range: 0 t + * o 29 and 31 Internal Base: 4 The selected HIF address bit is determined + * by adding the internal base to the value of this field. If set to 31, ba + * nk address bit 2 is set to 0. +*/ #undef DDRC_ADDRMAP1_ADDRMAP_BANK_B2_DEFVAL #undef DDRC_ADDRMAP1_ADDRMAP_BANK_B2_SHIFT #undef DDRC_ADDRMAP1_ADDRMAP_BANK_B2_MASK -#define DDRC_ADDRMAP1_ADDRMAP_BANK_B2_DEFVAL 0x00000000 -#define DDRC_ADDRMAP1_ADDRMAP_BANK_B2_SHIFT 16 -#define DDRC_ADDRMAP1_ADDRMAP_BANK_B2_MASK 0x001F0000U +#define DDRC_ADDRMAP1_ADDRMAP_BANK_B2_DEFVAL 0x00000000 +#define DDRC_ADDRMAP1_ADDRMAP_BANK_B2_SHIFT 16 +#define DDRC_ADDRMAP1_ADDRMAP_BANK_B2_MASK 0x001F0000U -/*Selects the HIF address bits used as bank address bit 1. Valid Range: 0 to 30 Internal Base: 3 The selected HIF address bit f - r each of the bank address bits is determined by adding the internal base to the value of this field.*/ +/* +* Selects the HIF address bits used as bank address bit 1. Valid Range: 0 + * to 30 Internal Base: 3 The selected HIF address bit for each of the bank + * address bits is determined by adding the internal base to the value of + * this field. +*/ #undef DDRC_ADDRMAP1_ADDRMAP_BANK_B1_DEFVAL #undef DDRC_ADDRMAP1_ADDRMAP_BANK_B1_SHIFT #undef DDRC_ADDRMAP1_ADDRMAP_BANK_B1_MASK -#define DDRC_ADDRMAP1_ADDRMAP_BANK_B1_DEFVAL 0x00000000 -#define DDRC_ADDRMAP1_ADDRMAP_BANK_B1_SHIFT 8 -#define DDRC_ADDRMAP1_ADDRMAP_BANK_B1_MASK 0x00001F00U +#define DDRC_ADDRMAP1_ADDRMAP_BANK_B1_DEFVAL 0x00000000 +#define DDRC_ADDRMAP1_ADDRMAP_BANK_B1_SHIFT 8 +#define DDRC_ADDRMAP1_ADDRMAP_BANK_B1_MASK 0x00001F00U -/*Selects the HIF address bits used as bank address bit 0. Valid Range: 0 to 30 Internal Base: 2 The selected HIF address bit f - r each of the bank address bits is determined by adding the internal base to the value of this field.*/ +/* +* Selects the HIF address bits used as bank address bit 0. Valid Range: 0 + * to 30 Internal Base: 2 The selected HIF address bit for each of the bank + * address bits is determined by adding the internal base to the value of + * this field. +*/ #undef DDRC_ADDRMAP1_ADDRMAP_BANK_B0_DEFVAL #undef DDRC_ADDRMAP1_ADDRMAP_BANK_B0_SHIFT #undef DDRC_ADDRMAP1_ADDRMAP_BANK_B0_MASK -#define DDRC_ADDRMAP1_ADDRMAP_BANK_B0_DEFVAL 0x00000000 -#define DDRC_ADDRMAP1_ADDRMAP_BANK_B0_SHIFT 0 -#define DDRC_ADDRMAP1_ADDRMAP_BANK_B0_MASK 0x0000001FU +#define DDRC_ADDRMAP1_ADDRMAP_BANK_B0_DEFVAL 0x00000000 +#define DDRC_ADDRMAP1_ADDRMAP_BANK_B0_SHIFT 0 +#define DDRC_ADDRMAP1_ADDRMAP_BANK_B0_MASK 0x0000001FU -/*- Full bus width mode: Selects the HIF address bit used as column address bit 5. - Half bus width mode: Selects the HIF addre - s bit used as column address bit 6. - Quarter bus width mode: Selects the HIF address bit used as column address bit 7 . Vali - Range: 0 to 7, and 15 Internal Base: 5 The selected HIF address bit is determined by adding the internal base to the value o - this field. If set to 15, this column address bit is set to 0.*/ +/* +* - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 5. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 6. - Quarter bus width mode: Selects the HIF address bit + * used as column address bit 7 . Valid Range: 0 to 7, and 15 Internal Base + * : 5 The selected HIF address bit is determined by adding the internal ba + * se to the value of this field. If set to 15, this column address bit is + * set to 0. +*/ #undef DDRC_ADDRMAP2_ADDRMAP_COL_B5_DEFVAL #undef DDRC_ADDRMAP2_ADDRMAP_COL_B5_SHIFT #undef DDRC_ADDRMAP2_ADDRMAP_COL_B5_MASK -#define DDRC_ADDRMAP2_ADDRMAP_COL_B5_DEFVAL 0x00000000 -#define DDRC_ADDRMAP2_ADDRMAP_COL_B5_SHIFT 24 -#define DDRC_ADDRMAP2_ADDRMAP_COL_B5_MASK 0x0F000000U +#define DDRC_ADDRMAP2_ADDRMAP_COL_B5_DEFVAL 0x00000000 +#define DDRC_ADDRMAP2_ADDRMAP_COL_B5_SHIFT 24 +#define DDRC_ADDRMAP2_ADDRMAP_COL_B5_MASK 0x0F000000U -/*- Full bus width mode: Selects the HIF address bit used as column address bit 4. - Half bus width mode: Selects the HIF addre - s bit used as column address bit 5. - Quarter bus width mode: Selects the HIF address bit used as column address bit 6. Valid - Range: 0 to 7, and 15 Internal Base: 4 The selected HIF address bit is determined by adding the internal base to the value of - this field. If set to 15, this column address bit is set to 0.*/ +/* +* - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 4. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 5. - Quarter bus width mode: Selects the HIF address bit + * used as column address bit 6. Valid Range: 0 to 7, and 15 Internal Base: + * 4 The selected HIF address bit is determined by adding the internal bas + * e to the value of this field. If set to 15, this column address bit is s + * et to 0. +*/ #undef DDRC_ADDRMAP2_ADDRMAP_COL_B4_DEFVAL #undef DDRC_ADDRMAP2_ADDRMAP_COL_B4_SHIFT #undef DDRC_ADDRMAP2_ADDRMAP_COL_B4_MASK -#define DDRC_ADDRMAP2_ADDRMAP_COL_B4_DEFVAL 0x00000000 -#define DDRC_ADDRMAP2_ADDRMAP_COL_B4_SHIFT 16 -#define DDRC_ADDRMAP2_ADDRMAP_COL_B4_MASK 0x000F0000U +#define DDRC_ADDRMAP2_ADDRMAP_COL_B4_DEFVAL 0x00000000 +#define DDRC_ADDRMAP2_ADDRMAP_COL_B4_SHIFT 16 +#define DDRC_ADDRMAP2_ADDRMAP_COL_B4_MASK 0x000F0000U -/*- Full bus width mode: Selects the HIF address bit used as column address bit 3. - Half bus width mode: Selects the HIF addre - s bit used as column address bit 4. - Quarter bus width mode: Selects the HIF address bit used as column address bit 5. Valid - Range: 0 to 7 Internal Base: 3 The selected HIF address bit is determined by adding the internal base to the value of this fi - ld. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=16, it is required to program this to 0, hence register does not exist i - this case.*/ +/* +* - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 3. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 4. - Quarter bus width mode: Selects the HIF address bit + * used as column address bit 5. Valid Range: 0 to 7 Internal Base: 3 The s + * elected HIF address bit is determined by adding the internal base to the + * value of this field. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=1 + * 6, it is required to program this to 0, hence register does not exist in + * this case. +*/ #undef DDRC_ADDRMAP2_ADDRMAP_COL_B3_DEFVAL #undef DDRC_ADDRMAP2_ADDRMAP_COL_B3_SHIFT #undef DDRC_ADDRMAP2_ADDRMAP_COL_B3_MASK -#define DDRC_ADDRMAP2_ADDRMAP_COL_B3_DEFVAL 0x00000000 -#define DDRC_ADDRMAP2_ADDRMAP_COL_B3_SHIFT 8 -#define DDRC_ADDRMAP2_ADDRMAP_COL_B3_MASK 0x00000F00U +#define DDRC_ADDRMAP2_ADDRMAP_COL_B3_DEFVAL 0x00000000 +#define DDRC_ADDRMAP2_ADDRMAP_COL_B3_SHIFT 8 +#define DDRC_ADDRMAP2_ADDRMAP_COL_B3_MASK 0x00000F00U -/*- Full bus width mode: Selects the HIF address bit used as column address bit 2. - Half bus width mode: Selects the HIF addre - s bit used as column address bit 3. - Quarter bus width mode: Selects the HIF address bit used as column address bit 4. Valid - Range: 0 to 7 Internal Base: 2 The selected HIF address bit is determined by adding the internal base to the value of this fi - ld. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=8 or 16, it is required to program this to 0.*/ +/* +* - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 2. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 3. - Quarter bus width mode: Selects the HIF address bit + * used as column address bit 4. Valid Range: 0 to 7 Internal Base: 2 The s + * elected HIF address bit is determined by adding the internal base to the + * value of this field. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=8 + * or 16, it is required to program this to 0. +*/ #undef DDRC_ADDRMAP2_ADDRMAP_COL_B2_DEFVAL #undef DDRC_ADDRMAP2_ADDRMAP_COL_B2_SHIFT #undef DDRC_ADDRMAP2_ADDRMAP_COL_B2_MASK -#define DDRC_ADDRMAP2_ADDRMAP_COL_B2_DEFVAL 0x00000000 -#define DDRC_ADDRMAP2_ADDRMAP_COL_B2_SHIFT 0 -#define DDRC_ADDRMAP2_ADDRMAP_COL_B2_MASK 0x0000000FU +#define DDRC_ADDRMAP2_ADDRMAP_COL_B2_DEFVAL 0x00000000 +#define DDRC_ADDRMAP2_ADDRMAP_COL_B2_SHIFT 0 +#define DDRC_ADDRMAP2_ADDRMAP_COL_B2_MASK 0x0000000FU -/*- Full bus width mode: Selects the HIF address bit used as column address bit 9. - Half bus width mode: Selects the HIF addre - s bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). - Quarter bus width mode: Selects the HIF address bit used as - column address bit 13 (11 in LPDDR2/LPDDR3 mode). Valid Range: 0 to 7, and 15 Internal Base: 9 The selected HIF address bit i - determined by adding the internal base to the value of this field. If set to 15, this column address bit is set to 0. Note: - er JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source addr - ss bit can be mapped to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus an - hence column bit 10 is used.*/ +/* +* - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 9. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 11 (10 in LPDDR2/LPDDR3 mode). - Quarter bus width mode: + * Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/ + * LPDDR3 mode). Valid Range: 0 to 7, and 15 Internal Base: 9 The selected + * HIF address bit is determined by adding the internal base to the value o + * f this field. If set to 15, this column address bit is set to 0. Note: P + * er JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved fo + * r indicating auto-precharge, and hence no source address bit can be mapp + * ed to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit + * for auto-precharge in the CA bus and hence column bit 10 is used. +*/ #undef DDRC_ADDRMAP3_ADDRMAP_COL_B9_DEFVAL #undef DDRC_ADDRMAP3_ADDRMAP_COL_B9_SHIFT #undef DDRC_ADDRMAP3_ADDRMAP_COL_B9_MASK -#define DDRC_ADDRMAP3_ADDRMAP_COL_B9_DEFVAL 0x00000000 -#define DDRC_ADDRMAP3_ADDRMAP_COL_B9_SHIFT 24 -#define DDRC_ADDRMAP3_ADDRMAP_COL_B9_MASK 0x0F000000U +#define DDRC_ADDRMAP3_ADDRMAP_COL_B9_DEFVAL 0x00000000 +#define DDRC_ADDRMAP3_ADDRMAP_COL_B9_SHIFT 24 +#define DDRC_ADDRMAP3_ADDRMAP_COL_B9_MASK 0x0F000000U -/*- Full bus width mode: Selects the HIF address bit used as column address bit 8. - Half bus width mode: Selects the HIF addre - s bit used as column address bit 9. - Quarter bus width mode: Selects the HIF address bit used as column address bit 11 (10 i - LPDDR2/LPDDR3 mode). Valid Range: 0 to 7, and 15 Internal Base: 8 The selected HIF address bit is determined by adding the i - ternal base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specif - cation, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to col - mn address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and hence column bit 10 is use - .*/ +/* +* - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 8. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 9. - Quarter bus width mode: Selects the HIF address bit + * used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). Valid Range: 0 + * to 7, and 15 Internal Base: 8 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specifi + * cation, column address bit 10 is reserved for indicating auto-precharge, + * and hence no source address bit can be mapped to column address bit 10. + * In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA + * bus and hence column bit 10 is used. +*/ #undef DDRC_ADDRMAP3_ADDRMAP_COL_B8_DEFVAL #undef DDRC_ADDRMAP3_ADDRMAP_COL_B8_SHIFT #undef DDRC_ADDRMAP3_ADDRMAP_COL_B8_MASK -#define DDRC_ADDRMAP3_ADDRMAP_COL_B8_DEFVAL 0x00000000 -#define DDRC_ADDRMAP3_ADDRMAP_COL_B8_SHIFT 16 -#define DDRC_ADDRMAP3_ADDRMAP_COL_B8_MASK 0x000F0000U +#define DDRC_ADDRMAP3_ADDRMAP_COL_B8_DEFVAL 0x00000000 +#define DDRC_ADDRMAP3_ADDRMAP_COL_B8_SHIFT 16 +#define DDRC_ADDRMAP3_ADDRMAP_COL_B8_MASK 0x000F0000U -/*- Full bus width mode: Selects the HIF address bit used as column address bit 7. - Half bus width mode: Selects the HIF addre - s bit used as column address bit 8. - Quarter bus width mode: Selects the HIF address bit used as column address bit 9. Valid - Range: 0 to 7, and 15 Internal Base: 7 The selected HIF address bit is determined by adding the internal base to the value of - this field. If set to 15, this column address bit is set to 0.*/ +/* +* - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 7. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 8. - Quarter bus width mode: Selects the HIF address bit + * used as column address bit 9. Valid Range: 0 to 7, and 15 Internal Base: + * 7 The selected HIF address bit is determined by adding the internal bas + * e to the value of this field. If set to 15, this column address bit is s + * et to 0. +*/ #undef DDRC_ADDRMAP3_ADDRMAP_COL_B7_DEFVAL #undef DDRC_ADDRMAP3_ADDRMAP_COL_B7_SHIFT #undef DDRC_ADDRMAP3_ADDRMAP_COL_B7_MASK -#define DDRC_ADDRMAP3_ADDRMAP_COL_B7_DEFVAL 0x00000000 -#define DDRC_ADDRMAP3_ADDRMAP_COL_B7_SHIFT 8 -#define DDRC_ADDRMAP3_ADDRMAP_COL_B7_MASK 0x00000F00U +#define DDRC_ADDRMAP3_ADDRMAP_COL_B7_DEFVAL 0x00000000 +#define DDRC_ADDRMAP3_ADDRMAP_COL_B7_SHIFT 8 +#define DDRC_ADDRMAP3_ADDRMAP_COL_B7_MASK 0x00000F00U -/*- Full bus width mode: Selects the HIF address bit used as column address bit 6. - Half bus width mode: Selects the HIF addre - s bit used as column address bit 7. - Quarter bus width mode: Selects the HIF address bit used as column address bit 8. Valid - Range: 0 to 7, and 15 Internal Base: 6 The selected HIF address bit is determined by adding the internal base to the value of - this field. If set to 15, this column address bit is set to 0.*/ +/* +* - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 6. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 7. - Quarter bus width mode: Selects the HIF address bit + * used as column address bit 8. Valid Range: 0 to 7, and 15 Internal Base: + * 6 The selected HIF address bit is determined by adding the internal bas + * e to the value of this field. If set to 15, this column address bit is s + * et to 0. +*/ #undef DDRC_ADDRMAP3_ADDRMAP_COL_B6_DEFVAL #undef DDRC_ADDRMAP3_ADDRMAP_COL_B6_SHIFT #undef DDRC_ADDRMAP3_ADDRMAP_COL_B6_MASK -#define DDRC_ADDRMAP3_ADDRMAP_COL_B6_DEFVAL 0x00000000 -#define DDRC_ADDRMAP3_ADDRMAP_COL_B6_SHIFT 0 -#define DDRC_ADDRMAP3_ADDRMAP_COL_B6_MASK 0x0000000FU +#define DDRC_ADDRMAP3_ADDRMAP_COL_B6_DEFVAL 0x00000000 +#define DDRC_ADDRMAP3_ADDRMAP_COL_B6_SHIFT 0 +#define DDRC_ADDRMAP3_ADDRMAP_COL_B6_MASK 0x0000000FU -/*- Full bus width mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode). - Half bus width - mode: Unused. To make it unused, this should be tied to 4'hF. - Quarter bus width mode: Unused. To make it unused, this must - e tied to 4'hF. Valid Range: 0 to 7, and 15 Internal Base: 11 The selected HIF address bit is determined by adding the intern - l base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specificati - n, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column a - dress bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and hence column bit 10 is used.*/ +/* +* - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 13 (11 in LPDDR2/LPDDR3 mode). - Half bus width mode: Unused. To m + * ake it unused, this should be tied to 4'hF. - Quarter bus width mode: Un + * used. To make it unused, this must be tied to 4'hF. Valid Range: 0 to 7, + * and 15 Internal Base: 11 The selected HIF address bit is determined by + * adding the internal base to the value of this field. If set to 15, this + * column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specificatio + * n, column address bit 10 is reserved for indicating auto-precharge, and + * hence no source address bit can be mapped to column address bit 10. In L + * PDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus + * and hence column bit 10 is used. +*/ #undef DDRC_ADDRMAP4_ADDRMAP_COL_B11_DEFVAL #undef DDRC_ADDRMAP4_ADDRMAP_COL_B11_SHIFT #undef DDRC_ADDRMAP4_ADDRMAP_COL_B11_MASK -#define DDRC_ADDRMAP4_ADDRMAP_COL_B11_DEFVAL 0x00000000 -#define DDRC_ADDRMAP4_ADDRMAP_COL_B11_SHIFT 8 -#define DDRC_ADDRMAP4_ADDRMAP_COL_B11_MASK 0x00000F00U +#define DDRC_ADDRMAP4_ADDRMAP_COL_B11_DEFVAL 0x00000000 +#define DDRC_ADDRMAP4_ADDRMAP_COL_B11_SHIFT 8 +#define DDRC_ADDRMAP4_ADDRMAP_COL_B11_MASK 0x00000F00U -/*- Full bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). - Half bus width - mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode). - Quarter bus width mode: UNUSED. - To make it unused, this must be tied to 4'hF. Valid Range: 0 to 7, and 15 Internal Base: 10 The selected HIF address bit is d - termined by adding the internal base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per - JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source address - bit can be mapped to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and h - nce column bit 10 is used.*/ +/* +* - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 11 (10 in LPDDR2/LPDDR3 mode). - Half bus width mode: Selects the + * HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode) + * . - Quarter bus width mode: UNUSED. To make it unused, this must be tied + * to 4'hF. Valid Range: 0 to 7, and 15 Internal Base: 10 The selected HIF + * address bit is determined by adding the internal base to the value of t + * his field. If set to 15, this column address bit is set to 0. Note: Per + * JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for i + * ndicating auto-precharge, and hence no source address bit can be mapped + * to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for + * auto-precharge in the CA bus and hence column bit 10 is used. +*/ #undef DDRC_ADDRMAP4_ADDRMAP_COL_B10_DEFVAL #undef DDRC_ADDRMAP4_ADDRMAP_COL_B10_SHIFT #undef DDRC_ADDRMAP4_ADDRMAP_COL_B10_MASK -#define DDRC_ADDRMAP4_ADDRMAP_COL_B10_DEFVAL 0x00000000 -#define DDRC_ADDRMAP4_ADDRMAP_COL_B10_SHIFT 0 -#define DDRC_ADDRMAP4_ADDRMAP_COL_B10_MASK 0x0000000FU +#define DDRC_ADDRMAP4_ADDRMAP_COL_B10_DEFVAL 0x00000000 +#define DDRC_ADDRMAP4_ADDRMAP_COL_B10_SHIFT 0 +#define DDRC_ADDRMAP4_ADDRMAP_COL_B10_MASK 0x0000000FU -/*Selects the HIF address bit used as row address bit 11. Valid Range: 0 to 11, and 15 Internal Base: 17 The selected HIF addre - s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 11 is set to 0.*/ +/* +* Selects the HIF address bit used as row address bit 11. Valid Range: 0 t + * o 11, and 15 Internal Base: 17 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * row address bit 11 is set to 0. +*/ #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B11_DEFVAL #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B11_SHIFT #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B11_MASK -#define DDRC_ADDRMAP5_ADDRMAP_ROW_B11_DEFVAL 0x00000000 -#define DDRC_ADDRMAP5_ADDRMAP_ROW_B11_SHIFT 24 -#define DDRC_ADDRMAP5_ADDRMAP_ROW_B11_MASK 0x0F000000U +#define DDRC_ADDRMAP5_ADDRMAP_ROW_B11_DEFVAL 0x00000000 +#define DDRC_ADDRMAP5_ADDRMAP_ROW_B11_SHIFT 24 +#define DDRC_ADDRMAP5_ADDRMAP_ROW_B11_MASK 0x0F000000U -/*Selects the HIF address bits used as row address bits 2 to 10. Valid Range: 0 to 11, and 15 Internal Base: 8 (for row address - bit 2), 9 (for row address bit 3), 10 (for row address bit 4) etc increasing to 16 (for row address bit 10) The selected HIF - ddress bit for each of the row address bits is determined by adding the internal base to the value of this field. When value - 5 is used the values of row address bits 2 to 10 are defined by registers ADDRMAP9, ADDRMAP10, ADDRMAP11.*/ +/* +* Selects the HIF address bits used as row address bits 2 to 10. Valid Ran + * ge: 0 to 11, and 15 Internal Base: 8 (for row address bit 2), 9 (for row + * address bit 3), 10 (for row address bit 4) etc increasing to 16 (for ro + * w address bit 10) The selected HIF address bit for each of the row addre + * ss bits is determined by adding the internal base to the value of this f + * ield. When value 15 is used the values of row address bits 2 to 10 are d + * efined by registers ADDRMAP9, ADDRMAP10, ADDRMAP11. +*/ #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_DEFVAL #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_SHIFT #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_MASK -#define DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_DEFVAL 0x00000000 -#define DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_SHIFT 16 -#define DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_MASK 0x000F0000U +#define DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_DEFVAL 0x00000000 +#define DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_SHIFT 16 +#define DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_MASK 0x000F0000U -/*Selects the HIF address bits used as row address bit 1. Valid Range: 0 to 11 Internal Base: 7 The selected HIF address bit fo - each of the row address bits is determined by adding the internal base to the value of this field.*/ +/* +* Selects the HIF address bits used as row address bit 1. Valid Range: 0 t + * o 11 Internal Base: 7 The selected HIF address bit for each of the row a + * ddress bits is determined by adding the internal base to the value of th + * is field. +*/ #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B1_DEFVAL #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B1_SHIFT #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B1_MASK -#define DDRC_ADDRMAP5_ADDRMAP_ROW_B1_DEFVAL 0x00000000 -#define DDRC_ADDRMAP5_ADDRMAP_ROW_B1_SHIFT 8 -#define DDRC_ADDRMAP5_ADDRMAP_ROW_B1_MASK 0x00000F00U +#define DDRC_ADDRMAP5_ADDRMAP_ROW_B1_DEFVAL 0x00000000 +#define DDRC_ADDRMAP5_ADDRMAP_ROW_B1_SHIFT 8 +#define DDRC_ADDRMAP5_ADDRMAP_ROW_B1_MASK 0x00000F00U -/*Selects the HIF address bits used as row address bit 0. Valid Range: 0 to 11 Internal Base: 6 The selected HIF address bit fo - each of the row address bits is determined by adding the internal base to the value of this field.*/ +/* +* Selects the HIF address bits used as row address bit 0. Valid Range: 0 t + * o 11 Internal Base: 6 The selected HIF address bit for each of the row a + * ddress bits is determined by adding the internal base to the value of th + * is field. +*/ #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B0_DEFVAL #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B0_SHIFT #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B0_MASK -#define DDRC_ADDRMAP5_ADDRMAP_ROW_B0_DEFVAL 0x00000000 -#define DDRC_ADDRMAP5_ADDRMAP_ROW_B0_SHIFT 0 -#define DDRC_ADDRMAP5_ADDRMAP_ROW_B0_MASK 0x0000000FU +#define DDRC_ADDRMAP5_ADDRMAP_ROW_B0_DEFVAL 0x00000000 +#define DDRC_ADDRMAP5_ADDRMAP_ROW_B0_SHIFT 0 +#define DDRC_ADDRMAP5_ADDRMAP_ROW_B0_MASK 0x0000000FU -/*Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use. - 1 - LPDDR3 SDRAM 6Gb/12Gb device in use. Every address - having row[14:13]==2'b11 is considered as invalid - 0 - non-LPDDR3 6Gb/12Gb device in use. All addresses are valid Present on - y in designs configured to support LPDDR3.*/ +/* +* Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use. - 1 + * - LPDDR3 SDRAM 6Gb/12Gb device in use. Every address having row[14:13]= + * =2'b11 is considered as invalid - 0 - non-LPDDR3 6Gb/12Gb device in use. + * All addresses are valid Present only in designs configured to support L + * PDDR3. +*/ #undef DDRC_ADDRMAP6_LPDDR3_6GB_12GB_DEFVAL #undef DDRC_ADDRMAP6_LPDDR3_6GB_12GB_SHIFT #undef DDRC_ADDRMAP6_LPDDR3_6GB_12GB_MASK -#define DDRC_ADDRMAP6_LPDDR3_6GB_12GB_DEFVAL 0x00000000 -#define DDRC_ADDRMAP6_LPDDR3_6GB_12GB_SHIFT 31 -#define DDRC_ADDRMAP6_LPDDR3_6GB_12GB_MASK 0x80000000U +#define DDRC_ADDRMAP6_LPDDR3_6GB_12GB_DEFVAL 0x00000000 +#define DDRC_ADDRMAP6_LPDDR3_6GB_12GB_SHIFT 31 +#define DDRC_ADDRMAP6_LPDDR3_6GB_12GB_MASK 0x80000000U -/*Selects the HIF address bit used as row address bit 15. Valid Range: 0 to 11, and 15 Internal Base: 21 The selected HIF addre - s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 15 is set to 0.*/ +/* +* Selects the HIF address bit used as row address bit 15. Valid Range: 0 t + * o 11, and 15 Internal Base: 21 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * row address bit 15 is set to 0. +*/ #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B15_DEFVAL #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B15_SHIFT #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B15_MASK -#define DDRC_ADDRMAP6_ADDRMAP_ROW_B15_DEFVAL 0x00000000 -#define DDRC_ADDRMAP6_ADDRMAP_ROW_B15_SHIFT 24 -#define DDRC_ADDRMAP6_ADDRMAP_ROW_B15_MASK 0x0F000000U +#define DDRC_ADDRMAP6_ADDRMAP_ROW_B15_DEFVAL 0x00000000 +#define DDRC_ADDRMAP6_ADDRMAP_ROW_B15_SHIFT 24 +#define DDRC_ADDRMAP6_ADDRMAP_ROW_B15_MASK 0x0F000000U -/*Selects the HIF address bit used as row address bit 14. Valid Range: 0 to 11, and 15 Internal Base: 20 The selected HIF addre - s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 14 is set to 0.*/ +/* +* Selects the HIF address bit used as row address bit 14. Valid Range: 0 t + * o 11, and 15 Internal Base: 20 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * row address bit 14 is set to 0. +*/ #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B14_DEFVAL #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B14_SHIFT #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B14_MASK -#define DDRC_ADDRMAP6_ADDRMAP_ROW_B14_DEFVAL 0x00000000 -#define DDRC_ADDRMAP6_ADDRMAP_ROW_B14_SHIFT 16 -#define DDRC_ADDRMAP6_ADDRMAP_ROW_B14_MASK 0x000F0000U +#define DDRC_ADDRMAP6_ADDRMAP_ROW_B14_DEFVAL 0x00000000 +#define DDRC_ADDRMAP6_ADDRMAP_ROW_B14_SHIFT 16 +#define DDRC_ADDRMAP6_ADDRMAP_ROW_B14_MASK 0x000F0000U -/*Selects the HIF address bit used as row address bit 13. Valid Range: 0 to 11, and 15 Internal Base: 19 The selected HIF addre - s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 13 is set to 0.*/ +/* +* Selects the HIF address bit used as row address bit 13. Valid Range: 0 t + * o 11, and 15 Internal Base: 19 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * row address bit 13 is set to 0. +*/ #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B13_DEFVAL #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B13_SHIFT #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B13_MASK -#define DDRC_ADDRMAP6_ADDRMAP_ROW_B13_DEFVAL 0x00000000 -#define DDRC_ADDRMAP6_ADDRMAP_ROW_B13_SHIFT 8 -#define DDRC_ADDRMAP6_ADDRMAP_ROW_B13_MASK 0x00000F00U +#define DDRC_ADDRMAP6_ADDRMAP_ROW_B13_DEFVAL 0x00000000 +#define DDRC_ADDRMAP6_ADDRMAP_ROW_B13_SHIFT 8 +#define DDRC_ADDRMAP6_ADDRMAP_ROW_B13_MASK 0x00000F00U -/*Selects the HIF address bit used as row address bit 12. Valid Range: 0 to 11, and 15 Internal Base: 18 The selected HIF addre - s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 12 is set to 0.*/ +/* +* Selects the HIF address bit used as row address bit 12. Valid Range: 0 t + * o 11, and 15 Internal Base: 18 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * row address bit 12 is set to 0. +*/ #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B12_DEFVAL #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B12_SHIFT #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B12_MASK -#define DDRC_ADDRMAP6_ADDRMAP_ROW_B12_DEFVAL 0x00000000 -#define DDRC_ADDRMAP6_ADDRMAP_ROW_B12_SHIFT 0 -#define DDRC_ADDRMAP6_ADDRMAP_ROW_B12_MASK 0x0000000FU +#define DDRC_ADDRMAP6_ADDRMAP_ROW_B12_DEFVAL 0x00000000 +#define DDRC_ADDRMAP6_ADDRMAP_ROW_B12_SHIFT 0 +#define DDRC_ADDRMAP6_ADDRMAP_ROW_B12_MASK 0x0000000FU -/*Selects the HIF address bit used as row address bit 17. Valid Range: 0 to 10, and 15 Internal Base: 23 The selected HIF addre - s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 17 is set to 0.*/ +/* +* Selects the HIF address bit used as row address bit 17. Valid Range: 0 t + * o 10, and 15 Internal Base: 23 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * row address bit 17 is set to 0. +*/ #undef DDRC_ADDRMAP7_ADDRMAP_ROW_B17_DEFVAL #undef DDRC_ADDRMAP7_ADDRMAP_ROW_B17_SHIFT #undef DDRC_ADDRMAP7_ADDRMAP_ROW_B17_MASK -#define DDRC_ADDRMAP7_ADDRMAP_ROW_B17_DEFVAL 0x00000000 -#define DDRC_ADDRMAP7_ADDRMAP_ROW_B17_SHIFT 8 -#define DDRC_ADDRMAP7_ADDRMAP_ROW_B17_MASK 0x00000F00U +#define DDRC_ADDRMAP7_ADDRMAP_ROW_B17_DEFVAL 0x00000000 +#define DDRC_ADDRMAP7_ADDRMAP_ROW_B17_SHIFT 8 +#define DDRC_ADDRMAP7_ADDRMAP_ROW_B17_MASK 0x00000F00U -/*Selects the HIF address bit used as row address bit 16. Valid Range: 0 to 11, and 15 Internal Base: 22 The selected HIF addre - s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 16 is set to 0.*/ +/* +* Selects the HIF address bit used as row address bit 16. Valid Range: 0 t + * o 11, and 15 Internal Base: 22 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * row address bit 16 is set to 0. +*/ #undef DDRC_ADDRMAP7_ADDRMAP_ROW_B16_DEFVAL #undef DDRC_ADDRMAP7_ADDRMAP_ROW_B16_SHIFT #undef DDRC_ADDRMAP7_ADDRMAP_ROW_B16_MASK -#define DDRC_ADDRMAP7_ADDRMAP_ROW_B16_DEFVAL 0x00000000 -#define DDRC_ADDRMAP7_ADDRMAP_ROW_B16_SHIFT 0 -#define DDRC_ADDRMAP7_ADDRMAP_ROW_B16_MASK 0x0000000FU +#define DDRC_ADDRMAP7_ADDRMAP_ROW_B16_DEFVAL 0x00000000 +#define DDRC_ADDRMAP7_ADDRMAP_ROW_B16_SHIFT 0 +#define DDRC_ADDRMAP7_ADDRMAP_ROW_B16_MASK 0x0000000FU -/*Selects the HIF address bits used as bank group address bit 1. Valid Range: 0 to 30, and 31 Internal Base: 3 The selected HIF - address bit for each of the bank group address bits is determined by adding the internal base to the value of this field. If - et to 31, bank group address bit 1 is set to 0.*/ +/* +* Selects the HIF address bits used as bank group address bit 1. Valid Ran + * ge: 0 to 30, and 31 Internal Base: 3 The selected HIF address bit for ea + * ch of the bank group address bits is determined by adding the internal b + * ase to the value of this field. If set to 31, bank group address bit 1 i + * s set to 0. +*/ #undef DDRC_ADDRMAP8_ADDRMAP_BG_B1_DEFVAL #undef DDRC_ADDRMAP8_ADDRMAP_BG_B1_SHIFT #undef DDRC_ADDRMAP8_ADDRMAP_BG_B1_MASK -#define DDRC_ADDRMAP8_ADDRMAP_BG_B1_DEFVAL 0x00000000 -#define DDRC_ADDRMAP8_ADDRMAP_BG_B1_SHIFT 8 -#define DDRC_ADDRMAP8_ADDRMAP_BG_B1_MASK 0x00001F00U +#define DDRC_ADDRMAP8_ADDRMAP_BG_B1_DEFVAL 0x00000000 +#define DDRC_ADDRMAP8_ADDRMAP_BG_B1_SHIFT 8 +#define DDRC_ADDRMAP8_ADDRMAP_BG_B1_MASK 0x00001F00U -/*Selects the HIF address bits used as bank group address bit 0. Valid Range: 0 to 30 Internal Base: 2 The selected HIF address - bit for each of the bank group address bits is determined by adding the internal base to the value of this field.*/ +/* +* Selects the HIF address bits used as bank group address bit 0. Valid Ran + * ge: 0 to 30 Internal Base: 2 The selected HIF address bit for each of th + * e bank group address bits is determined by adding the internal base to t + * he value of this field. +*/ #undef DDRC_ADDRMAP8_ADDRMAP_BG_B0_DEFVAL #undef DDRC_ADDRMAP8_ADDRMAP_BG_B0_SHIFT #undef DDRC_ADDRMAP8_ADDRMAP_BG_B0_MASK -#define DDRC_ADDRMAP8_ADDRMAP_BG_B0_DEFVAL 0x00000000 -#define DDRC_ADDRMAP8_ADDRMAP_BG_B0_SHIFT 0 -#define DDRC_ADDRMAP8_ADDRMAP_BG_B0_MASK 0x0000001FU +#define DDRC_ADDRMAP8_ADDRMAP_BG_B0_DEFVAL 0x00000000 +#define DDRC_ADDRMAP8_ADDRMAP_BG_B0_SHIFT 0 +#define DDRC_ADDRMAP8_ADDRMAP_BG_B0_MASK 0x0000001FU -/*Selects the HIF address bits used as row address bit 5. Valid Range: 0 to 11 Internal Base: 11 The selected HIF address bit f - r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u - ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/ +/* +* Selects the HIF address bits used as row address bit 5. Valid Range: 0 t + * o 11 Internal Base: 11 The selected HIF address bit for each of the row + * address bits is determined by adding the internal base to the value of t + * his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + * _10 is set to value 15. +*/ #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B5_DEFVAL #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B5_SHIFT #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B5_MASK -#define DDRC_ADDRMAP9_ADDRMAP_ROW_B5_DEFVAL 0x00000000 -#define DDRC_ADDRMAP9_ADDRMAP_ROW_B5_SHIFT 24 -#define DDRC_ADDRMAP9_ADDRMAP_ROW_B5_MASK 0x0F000000U +#define DDRC_ADDRMAP9_ADDRMAP_ROW_B5_DEFVAL 0x00000000 +#define DDRC_ADDRMAP9_ADDRMAP_ROW_B5_SHIFT 24 +#define DDRC_ADDRMAP9_ADDRMAP_ROW_B5_MASK 0x0F000000U -/*Selects the HIF address bits used as row address bit 4. Valid Range: 0 to 11 Internal Base: 10 The selected HIF address bit f - r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u - ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/ +/* +* Selects the HIF address bits used as row address bit 4. Valid Range: 0 t + * o 11 Internal Base: 10 The selected HIF address bit for each of the row + * address bits is determined by adding the internal base to the value of t + * his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + * _10 is set to value 15. +*/ #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B4_DEFVAL #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B4_SHIFT #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B4_MASK -#define DDRC_ADDRMAP9_ADDRMAP_ROW_B4_DEFVAL 0x00000000 -#define DDRC_ADDRMAP9_ADDRMAP_ROW_B4_SHIFT 16 -#define DDRC_ADDRMAP9_ADDRMAP_ROW_B4_MASK 0x000F0000U +#define DDRC_ADDRMAP9_ADDRMAP_ROW_B4_DEFVAL 0x00000000 +#define DDRC_ADDRMAP9_ADDRMAP_ROW_B4_SHIFT 16 +#define DDRC_ADDRMAP9_ADDRMAP_ROW_B4_MASK 0x000F0000U -/*Selects the HIF address bits used as row address bit 3. Valid Range: 0 to 11 Internal Base: 9 The selected HIF address bit fo - each of the row address bits is determined by adding the internal base to the value of this field. This register field is us - d only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/ +/* +* Selects the HIF address bits used as row address bit 3. Valid Range: 0 t + * o 11 Internal Base: 9 The selected HIF address bit for each of the row a + * ddress bits is determined by adding the internal base to the value of th + * is field. This register field is used only when ADDRMAP5.addrmap_row_b2_ + * 10 is set to value 15. +*/ #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B3_DEFVAL #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B3_SHIFT #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B3_MASK -#define DDRC_ADDRMAP9_ADDRMAP_ROW_B3_DEFVAL 0x00000000 -#define DDRC_ADDRMAP9_ADDRMAP_ROW_B3_SHIFT 8 -#define DDRC_ADDRMAP9_ADDRMAP_ROW_B3_MASK 0x00000F00U +#define DDRC_ADDRMAP9_ADDRMAP_ROW_B3_DEFVAL 0x00000000 +#define DDRC_ADDRMAP9_ADDRMAP_ROW_B3_SHIFT 8 +#define DDRC_ADDRMAP9_ADDRMAP_ROW_B3_MASK 0x00000F00U -/*Selects the HIF address bits used as row address bit 2. Valid Range: 0 to 11 Internal Base: 8 The selected HIF address bit fo - each of the row address bits is determined by adding the internal base to the value of this field. This register field is us - d only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/ +/* +* Selects the HIF address bits used as row address bit 2. Valid Range: 0 t + * o 11 Internal Base: 8 The selected HIF address bit for each of the row a + * ddress bits is determined by adding the internal base to the value of th + * is field. This register field is used only when ADDRMAP5.addrmap_row_b2_ + * 10 is set to value 15. +*/ #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B2_DEFVAL #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B2_SHIFT #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B2_MASK -#define DDRC_ADDRMAP9_ADDRMAP_ROW_B2_DEFVAL 0x00000000 -#define DDRC_ADDRMAP9_ADDRMAP_ROW_B2_SHIFT 0 -#define DDRC_ADDRMAP9_ADDRMAP_ROW_B2_MASK 0x0000000FU +#define DDRC_ADDRMAP9_ADDRMAP_ROW_B2_DEFVAL 0x00000000 +#define DDRC_ADDRMAP9_ADDRMAP_ROW_B2_SHIFT 0 +#define DDRC_ADDRMAP9_ADDRMAP_ROW_B2_MASK 0x0000000FU -/*Selects the HIF address bits used as row address bit 9. Valid Range: 0 to 11 Internal Base: 15 The selected HIF address bit f - r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u - ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/ +/* +* Selects the HIF address bits used as row address bit 9. Valid Range: 0 t + * o 11 Internal Base: 15 The selected HIF address bit for each of the row + * address bits is determined by adding the internal base to the value of t + * his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + * _10 is set to value 15. +*/ #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B9_DEFVAL #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B9_SHIFT #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B9_MASK -#define DDRC_ADDRMAP10_ADDRMAP_ROW_B9_DEFVAL 0x00000000 -#define DDRC_ADDRMAP10_ADDRMAP_ROW_B9_SHIFT 24 -#define DDRC_ADDRMAP10_ADDRMAP_ROW_B9_MASK 0x0F000000U +#define DDRC_ADDRMAP10_ADDRMAP_ROW_B9_DEFVAL 0x00000000 +#define DDRC_ADDRMAP10_ADDRMAP_ROW_B9_SHIFT 24 +#define DDRC_ADDRMAP10_ADDRMAP_ROW_B9_MASK 0x0F000000U -/*Selects the HIF address bits used as row address bit 8. Valid Range: 0 to 11 Internal Base: 14 The selected HIF address bit f - r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u - ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/ +/* +* Selects the HIF address bits used as row address bit 8. Valid Range: 0 t + * o 11 Internal Base: 14 The selected HIF address bit for each of the row + * address bits is determined by adding the internal base to the value of t + * his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + * _10 is set to value 15. +*/ #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B8_DEFVAL #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B8_SHIFT #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B8_MASK -#define DDRC_ADDRMAP10_ADDRMAP_ROW_B8_DEFVAL 0x00000000 -#define DDRC_ADDRMAP10_ADDRMAP_ROW_B8_SHIFT 16 -#define DDRC_ADDRMAP10_ADDRMAP_ROW_B8_MASK 0x000F0000U +#define DDRC_ADDRMAP10_ADDRMAP_ROW_B8_DEFVAL 0x00000000 +#define DDRC_ADDRMAP10_ADDRMAP_ROW_B8_SHIFT 16 +#define DDRC_ADDRMAP10_ADDRMAP_ROW_B8_MASK 0x000F0000U -/*Selects the HIF address bits used as row address bit 7. Valid Range: 0 to 11 Internal Base: 13 The selected HIF address bit f - r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u - ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/ +/* +* Selects the HIF address bits used as row address bit 7. Valid Range: 0 t + * o 11 Internal Base: 13 The selected HIF address bit for each of the row + * address bits is determined by adding the internal base to the value of t + * his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + * _10 is set to value 15. +*/ #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B7_DEFVAL #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B7_SHIFT #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B7_MASK -#define DDRC_ADDRMAP10_ADDRMAP_ROW_B7_DEFVAL 0x00000000 -#define DDRC_ADDRMAP10_ADDRMAP_ROW_B7_SHIFT 8 -#define DDRC_ADDRMAP10_ADDRMAP_ROW_B7_MASK 0x00000F00U +#define DDRC_ADDRMAP10_ADDRMAP_ROW_B7_DEFVAL 0x00000000 +#define DDRC_ADDRMAP10_ADDRMAP_ROW_B7_SHIFT 8 +#define DDRC_ADDRMAP10_ADDRMAP_ROW_B7_MASK 0x00000F00U -/*Selects the HIF address bits used as row address bit 6. Valid Range: 0 to 11 Internal Base: 12 The selected HIF address bit f - r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u - ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/ +/* +* Selects the HIF address bits used as row address bit 6. Valid Range: 0 t + * o 11 Internal Base: 12 The selected HIF address bit for each of the row + * address bits is determined by adding the internal base to the value of t + * his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + * _10 is set to value 15. +*/ #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B6_DEFVAL #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B6_SHIFT #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B6_MASK -#define DDRC_ADDRMAP10_ADDRMAP_ROW_B6_DEFVAL 0x00000000 -#define DDRC_ADDRMAP10_ADDRMAP_ROW_B6_SHIFT 0 -#define DDRC_ADDRMAP10_ADDRMAP_ROW_B6_MASK 0x0000000FU +#define DDRC_ADDRMAP10_ADDRMAP_ROW_B6_DEFVAL 0x00000000 +#define DDRC_ADDRMAP10_ADDRMAP_ROW_B6_SHIFT 0 +#define DDRC_ADDRMAP10_ADDRMAP_ROW_B6_MASK 0x0000000FU -/*Selects the HIF address bits used as row address bit 10. Valid Range: 0 to 11 Internal Base: 16 The selected HIF address bit - or each of the row address bits is determined by adding the internal base to the value of this field. This register field is - sed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/ +/* +* Selects the HIF address bits used as row address bit 10. Valid Range: 0 + * to 11 Internal Base: 16 The selected HIF address bit for each of the row + * address bits is determined by adding the internal base to the value of + * this field. This register field is used only when ADDRMAP5.addrmap_row_b + * 2_10 is set to value 15. +*/ #undef DDRC_ADDRMAP11_ADDRMAP_ROW_B10_DEFVAL #undef DDRC_ADDRMAP11_ADDRMAP_ROW_B10_SHIFT #undef DDRC_ADDRMAP11_ADDRMAP_ROW_B10_MASK -#define DDRC_ADDRMAP11_ADDRMAP_ROW_B10_DEFVAL -#define DDRC_ADDRMAP11_ADDRMAP_ROW_B10_SHIFT 0 -#define DDRC_ADDRMAP11_ADDRMAP_ROW_B10_MASK 0x0000000FU +#define DDRC_ADDRMAP11_ADDRMAP_ROW_B10_DEFVAL +#define DDRC_ADDRMAP11_ADDRMAP_ROW_B10_SHIFT 0 +#define DDRC_ADDRMAP11_ADDRMAP_ROW_B10_MASK 0x0000000FU -/*Cycles to hold ODT for a write command. The minimum supported value is 2. Recommended values: DDR2: - BL8: 0x5 (DDR2-400/533/ - 67), 0x6 (DDR2-800), 0x7 (DDR2-1066) - BL4: 0x3 (DDR2-400/533/667), 0x4 (DDR2-800), 0x5 (DDR2-1066) DDR3: - BL8: 0x6 DDR4: - - L8: 5 + WR_PREAMBLE + CRC_MODE WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) CRC_MODE = 0 (not CRC mode), 1 - CRC mode) LPDDR3: - BL8: 7 + RU(tODTon(max)/tCK)*/ +/* +* Cycles to hold ODT for a write command. The minimum supported value is 2 + * . Recommended values: DDR2: - BL8: 0x5 (DDR2-400/533/667), 0x6 (DDR2-800 + * ), 0x7 (DDR2-1066) - BL4: 0x3 (DDR2-400/533/667), 0x4 (DDR2-800), 0x5 (D + * DR2-1066) DDR3: - BL8: 0x6 DDR4: - BL8: 5 + WR_PREAMBLE + CRC_MODE WR_PR + * EAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) CRC_MODE = 0 ( + * not CRC mode), 1 (CRC mode) LPDDR3: - BL8: 7 + RU(tODTon(max)/tCK) +*/ #undef DDRC_ODTCFG_WR_ODT_HOLD_DEFVAL #undef DDRC_ODTCFG_WR_ODT_HOLD_SHIFT #undef DDRC_ODTCFG_WR_ODT_HOLD_MASK -#define DDRC_ODTCFG_WR_ODT_HOLD_DEFVAL 0x04000400 -#define DDRC_ODTCFG_WR_ODT_HOLD_SHIFT 24 -#define DDRC_ODTCFG_WR_ODT_HOLD_MASK 0x0F000000U +#define DDRC_ODTCFG_WR_ODT_HOLD_DEFVAL 0x04000400 +#define DDRC_ODTCFG_WR_ODT_HOLD_SHIFT 24 +#define DDRC_ODTCFG_WR_ODT_HOLD_MASK 0x0F000000U -/*The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting must - remain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: - CWL + AL - 3 (DDR2-400/533/ - 67), CWL + AL - 4 (DDR2-800), CWL + AL - 5 (DDR2-1066) If (CWL + AL - 3 < 0), uMCTL2 does not support ODT for write operation - DDR3: - 0x0 DDR4: - DFITMG1.dfi_t_cmd_lat (to adjust for CAL mode) LPDDR3: - WL - 1 - RU(tODTon(max)/tCK))*/ +/* +* The delay, in clock cycles, from issuing a write command to setting ODT + * values associated with that command. ODT setting must remain constant fo + * r the entire time that DQS is driven by the uMCTL2. Recommended values: + * DDR2: - CWL + AL - 3 (DDR2-400/533/667), CWL + AL - 4 (DDR2-800), CWL + + * AL - 5 (DDR2-1066) If (CWL + AL - 3 < 0), uMCTL2 does not support ODT fo + * r write operation. DDR3: - 0x0 DDR4: - DFITMG1.dfi_t_cmd_lat (to adjust + * for CAL mode) LPDDR3: - WL - 1 - RU(tODTon(max)/tCK)) +*/ #undef DDRC_ODTCFG_WR_ODT_DELAY_DEFVAL #undef DDRC_ODTCFG_WR_ODT_DELAY_SHIFT #undef DDRC_ODTCFG_WR_ODT_DELAY_MASK -#define DDRC_ODTCFG_WR_ODT_DELAY_DEFVAL 0x04000400 -#define DDRC_ODTCFG_WR_ODT_DELAY_SHIFT 16 -#define DDRC_ODTCFG_WR_ODT_DELAY_MASK 0x001F0000U +#define DDRC_ODTCFG_WR_ODT_DELAY_DEFVAL 0x04000400 +#define DDRC_ODTCFG_WR_ODT_DELAY_SHIFT 16 +#define DDRC_ODTCFG_WR_ODT_DELAY_MASK 0x001F0000U -/*Cycles to hold ODT for a read command. The minimum supported value is 2. Recommended values: DDR2: - BL8: 0x6 (not DDR2-1066) - 0x7 (DDR2-1066) - BL4: 0x4 (not DDR2-1066), 0x5 (DDR2-1066) DDR3: - BL8 - 0x6 DDR4: - BL8: 5 + RD_PREAMBLE RD_PREAMBLE = 1 ( - tCK write preamble), 2 (2tCK write preamble) LPDDR3: - BL8: 5 + RU(tDQSCK(max)/tCK) - RD(tDQSCK(min)/tCK) + RU(tODTon(max)/tC - )*/ +/* +* Cycles to hold ODT for a read command. The minimum supported value is 2. + * Recommended values: DDR2: - BL8: 0x6 (not DDR2-1066), 0x7 (DDR2-1066) - + * BL4: 0x4 (not DDR2-1066), 0x5 (DDR2-1066) DDR3: - BL8 - 0x6 DDR4: - BL8 + * : 5 + RD_PREAMBLE RD_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write p + * reamble) LPDDR3: - BL8: 5 + RU(tDQSCK(max)/tCK) - RD(tDQSCK(min)/tCK) + + * RU(tODTon(max)/tCK) +*/ #undef DDRC_ODTCFG_RD_ODT_HOLD_DEFVAL #undef DDRC_ODTCFG_RD_ODT_HOLD_SHIFT #undef DDRC_ODTCFG_RD_ODT_HOLD_MASK -#define DDRC_ODTCFG_RD_ODT_HOLD_DEFVAL 0x04000400 -#define DDRC_ODTCFG_RD_ODT_HOLD_SHIFT 8 -#define DDRC_ODTCFG_RD_ODT_HOLD_MASK 0x00000F00U +#define DDRC_ODTCFG_RD_ODT_HOLD_DEFVAL 0x04000400 +#define DDRC_ODTCFG_RD_ODT_HOLD_SHIFT 8 +#define DDRC_ODTCFG_RD_ODT_HOLD_MASK 0x00000F00U -/*The delay, in clock cycles, from issuing a read command to setting ODT values associated with that command. ODT setting must - emain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: - CL + AL - 4 (not DDR2-1066), - CL + AL - 5 (DDR2-1066) If (CL + AL - 4 < 0), uMCTL2 does not support ODT for read operation. DDR3: - CL - CWL DDR4: - CL - C - L - RD_PREAMBLE + WR_PREAMBLE + DFITMG1.dfi_t_cmd_lat (to adjust for CAL mode) WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK - write preamble) RD_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) If (CL - CWL - RD_PREAMBLE + WR_PREAMBLE) < 0, - uMCTL2 does not support ODT for read operation. LPDDR3: - RL + RD(tDQSCK(min)/tCK) - 1 - RU(tODTon(max)/tCK)*/ +/* +* The delay, in clock cycles, from issuing a read command to setting ODT v + * alues associated with that command. ODT setting must remain constant for + * the entire time that DQS is driven by the uMCTL2. Recommended values: D + * DR2: - CL + AL - 4 (not DDR2-1066), CL + AL - 5 (DDR2-1066) If (CL + AL + * - 4 < 0), uMCTL2 does not support ODT for read operation. DDR3: - CL - C + * WL DDR4: - CL - CWL - RD_PREAMBLE + WR_PREAMBLE + DFITMG1.dfi_t_cmd_lat + * (to adjust for CAL mode) WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK + * write preamble) RD_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write pre + * amble) If (CL - CWL - RD_PREAMBLE + WR_PREAMBLE) < 0, uMCTL2 does not su + * pport ODT for read operation. LPDDR3: - RL + RD(tDQSCK(min)/tCK) - 1 - R + * U(tODTon(max)/tCK) +*/ #undef DDRC_ODTCFG_RD_ODT_DELAY_DEFVAL #undef DDRC_ODTCFG_RD_ODT_DELAY_SHIFT #undef DDRC_ODTCFG_RD_ODT_DELAY_MASK -#define DDRC_ODTCFG_RD_ODT_DELAY_DEFVAL 0x04000400 -#define DDRC_ODTCFG_RD_ODT_DELAY_SHIFT 2 -#define DDRC_ODTCFG_RD_ODT_DELAY_MASK 0x0000007CU +#define DDRC_ODTCFG_RD_ODT_DELAY_DEFVAL 0x04000400 +#define DDRC_ODTCFG_RD_ODT_DELAY_SHIFT 2 +#define DDRC_ODTCFG_RD_ODT_DELAY_MASK 0x0000007CU -/*Indicates which remote ODTs must be turned on during a read from rank 1. Each rank has a remote ODT (in the SDRAM) which can - e turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB - etc. For each rank, set its bit to 1 to enable its ODT. Present only in configurations that have 2 or more ranks*/ +/* +* Indicates which remote ODTs must be turned on during a read from rank 1. + * Each rank has a remote ODT (in the SDRAM) which can be turned on by set + * ting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 i + * s controlled by bit next to the LSB, etc. For each rank, set its bit to + * 1 to enable its ODT. Present only in configurations that have 2 or more + * ranks +*/ #undef DDRC_ODTMAP_RANK1_RD_ODT_DEFVAL #undef DDRC_ODTMAP_RANK1_RD_ODT_SHIFT #undef DDRC_ODTMAP_RANK1_RD_ODT_MASK -#define DDRC_ODTMAP_RANK1_RD_ODT_DEFVAL 0x00002211 -#define DDRC_ODTMAP_RANK1_RD_ODT_SHIFT 12 -#define DDRC_ODTMAP_RANK1_RD_ODT_MASK 0x00003000U +#define DDRC_ODTMAP_RANK1_RD_ODT_DEFVAL 0x00002211 +#define DDRC_ODTMAP_RANK1_RD_ODT_SHIFT 12 +#define DDRC_ODTMAP_RANK1_RD_ODT_MASK 0x00003000U -/*Indicates which remote ODTs must be turned on during a write to rank 1. Each rank has a remote ODT (in the SDRAM) which can b - turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB, - etc. For each rank, set its bit to 1 to enable its ODT. Present only in configurations that have 2 or more ranks*/ +/* +* Indicates which remote ODTs must be turned on during a write to rank 1. + * Each rank has a remote ODT (in the SDRAM) which can be turned on by sett + * ing the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is + * controlled by bit next to the LSB, etc. For each rank, set its bit to 1 + * to enable its ODT. Present only in configurations that have 2 or more r + * anks +*/ #undef DDRC_ODTMAP_RANK1_WR_ODT_DEFVAL #undef DDRC_ODTMAP_RANK1_WR_ODT_SHIFT #undef DDRC_ODTMAP_RANK1_WR_ODT_MASK -#define DDRC_ODTMAP_RANK1_WR_ODT_DEFVAL 0x00002211 -#define DDRC_ODTMAP_RANK1_WR_ODT_SHIFT 8 -#define DDRC_ODTMAP_RANK1_WR_ODT_MASK 0x00000300U +#define DDRC_ODTMAP_RANK1_WR_ODT_DEFVAL 0x00002211 +#define DDRC_ODTMAP_RANK1_WR_ODT_SHIFT 8 +#define DDRC_ODTMAP_RANK1_WR_ODT_MASK 0x00000300U -/*Indicates which remote ODTs must be turned on during a read from rank 0. Each rank has a remote ODT (in the SDRAM) which can - e turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB - etc. For each rank, set its bit to 1 to enable its ODT.*/ +/* +* Indicates which remote ODTs must be turned on during a read from rank 0. + * Each rank has a remote ODT (in the SDRAM) which can be turned on by set + * ting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 i + * s controlled by bit next to the LSB, etc. For each rank, set its bit to + * 1 to enable its ODT. +*/ #undef DDRC_ODTMAP_RANK0_RD_ODT_DEFVAL #undef DDRC_ODTMAP_RANK0_RD_ODT_SHIFT #undef DDRC_ODTMAP_RANK0_RD_ODT_MASK -#define DDRC_ODTMAP_RANK0_RD_ODT_DEFVAL 0x00002211 -#define DDRC_ODTMAP_RANK0_RD_ODT_SHIFT 4 -#define DDRC_ODTMAP_RANK0_RD_ODT_MASK 0x00000030U +#define DDRC_ODTMAP_RANK0_RD_ODT_DEFVAL 0x00002211 +#define DDRC_ODTMAP_RANK0_RD_ODT_SHIFT 4 +#define DDRC_ODTMAP_RANK0_RD_ODT_MASK 0x00000030U -/*Indicates which remote ODTs must be turned on during a write to rank 0. Each rank has a remote ODT (in the SDRAM) which can b - turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB, - etc. For each rank, set its bit to 1 to enable its ODT.*/ +/* +* Indicates which remote ODTs must be turned on during a write to rank 0. + * Each rank has a remote ODT (in the SDRAM) which can be turned on by sett + * ing the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is + * controlled by bit next to the LSB, etc. For each rank, set its bit to 1 + * to enable its ODT. +*/ #undef DDRC_ODTMAP_RANK0_WR_ODT_DEFVAL #undef DDRC_ODTMAP_RANK0_WR_ODT_SHIFT #undef DDRC_ODTMAP_RANK0_WR_ODT_MASK -#define DDRC_ODTMAP_RANK0_WR_ODT_DEFVAL 0x00002211 -#define DDRC_ODTMAP_RANK0_WR_ODT_SHIFT 0 -#define DDRC_ODTMAP_RANK0_WR_ODT_MASK 0x00000003U +#define DDRC_ODTMAP_RANK0_WR_ODT_DEFVAL 0x00002211 +#define DDRC_ODTMAP_RANK0_WR_ODT_SHIFT 0 +#define DDRC_ODTMAP_RANK0_WR_ODT_MASK 0x00000003U -/*When the preferred transaction store is empty for these many clock cycles, switch to the alternate transaction store if it is - non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write t - ansaction store is the alternative store. When prefer write over read is set this is reversed. 0x0 is a legal value for this - egister. When set to 0x0, the transaction store switching will happen immediately when the switching conditions become true. - OR PERFORMANCE ONLY*/ +/* +* When the preferred transaction store is empty for these many clock cycle + * s, switch to the alternate transaction store if it is non-empty. The rea + * d transaction store (both high and low priority) is the default preferre + * d transaction store and the write transaction store is the alternative s + * tore. When prefer write over read is set this is reversed. 0x0 is a lega + * l value for this register. When set to 0x0, the transaction store switch + * ing will happen immediately when the switching conditions become true. F + * OR PERFORMANCE ONLY +*/ #undef DDRC_SCHED_RDWR_IDLE_GAP_DEFVAL #undef DDRC_SCHED_RDWR_IDLE_GAP_SHIFT #undef DDRC_SCHED_RDWR_IDLE_GAP_MASK -#define DDRC_SCHED_RDWR_IDLE_GAP_DEFVAL 0x00002005 -#define DDRC_SCHED_RDWR_IDLE_GAP_SHIFT 24 -#define DDRC_SCHED_RDWR_IDLE_GAP_MASK 0x7F000000U +#define DDRC_SCHED_RDWR_IDLE_GAP_DEFVAL 0x00002005 +#define DDRC_SCHED_RDWR_IDLE_GAP_SHIFT 24 +#define DDRC_SCHED_RDWR_IDLE_GAP_MASK 0x7F000000U -/*UNUSED*/ +/* +* UNUSED +*/ #undef DDRC_SCHED_GO2CRITICAL_HYSTERESIS_DEFVAL #undef DDRC_SCHED_GO2CRITICAL_HYSTERESIS_SHIFT #undef DDRC_SCHED_GO2CRITICAL_HYSTERESIS_MASK -#define DDRC_SCHED_GO2CRITICAL_HYSTERESIS_DEFVAL 0x00002005 -#define DDRC_SCHED_GO2CRITICAL_HYSTERESIS_SHIFT 16 -#define DDRC_SCHED_GO2CRITICAL_HYSTERESIS_MASK 0x00FF0000U +#define DDRC_SCHED_GO2CRITICAL_HYSTERESIS_DEFVAL 0x00002005 +#define DDRC_SCHED_GO2CRITICAL_HYSTERESIS_SHIFT 16 +#define DDRC_SCHED_GO2CRITICAL_HYSTERESIS_MASK 0x00FF0000U -/*Number of entries in the low priority transaction store is this value + 1. (MEMC_NO_OF_ENTRY - (SCHED.lpr_num_entries + 1)) i - the number of entries available for the high priority transaction store. Setting this to maximum value allocates all entries - to low priority transaction store. Setting this to 0 allocates 1 entry to low priority transaction store and the rest to high - priority transaction store. Note: In ECC configurations, the numbers of write and low priority read credits issued is one les - than in the non-ECC case. One entry each is reserved in the write and low-priority read CAMs for storing the RMW requests ar - sing out of single bit error correction RMW operation.*/ +/* +* Number of entries in the low priority transaction store is this value + + * 1. (MEMC_NO_OF_ENTRY - (SCHED.lpr_num_entries + 1)) is the number of ent + * ries available for the high priority transaction store. Setting this to + * maximum value allocates all entries to low priority transaction store. S + * etting this to 0 allocates 1 entry to low priority transaction store and + * the rest to high priority transaction store. Note: In ECC configuration + * s, the numbers of write and low priority read credits issued is one less + * than in the non-ECC case. One entry each is reserved in the write and l + * ow-priority read CAMs for storing the RMW requests arising out of single + * bit error correction RMW operation. +*/ #undef DDRC_SCHED_LPR_NUM_ENTRIES_DEFVAL #undef DDRC_SCHED_LPR_NUM_ENTRIES_SHIFT #undef DDRC_SCHED_LPR_NUM_ENTRIES_MASK -#define DDRC_SCHED_LPR_NUM_ENTRIES_DEFVAL 0x00002005 -#define DDRC_SCHED_LPR_NUM_ENTRIES_SHIFT 8 -#define DDRC_SCHED_LPR_NUM_ENTRIES_MASK 0x00003F00U +#define DDRC_SCHED_LPR_NUM_ENTRIES_DEFVAL 0x00002005 +#define DDRC_SCHED_LPR_NUM_ENTRIES_SHIFT 8 +#define DDRC_SCHED_LPR_NUM_ENTRIES_MASK 0x00003F00U -/*If true, bank is kept open only while there are page hit transactions available in the CAM to that bank. The last read or wri - e command in the CAM with a bank and page hit will be executed with auto-precharge if SCHED1.pageclose_timer=0. Even if this - egister set to 1 and SCHED1.pageclose_timer is set to 0, explicit precharge (and not auto-precharge) may be issued in some ca - es where there is a mode switch between Write and Read or between LPR and HPR. The Read and Write commands that are executed - s part of the ECC scrub requests are also executed without auto-precharge. If false, the bank remains open until there is a n - ed to close it (to open a different page, or for page timeout or refresh timeout) - also known as open page policy. The open - age policy can be overridden by setting the per-command-autopre bit on the HIF interface (hif_cmd_autopre). The pageclose fea - ure provids a midway between Open and Close page policies. FOR PERFORMANCE ONLY.*/ +/* +* If true, bank is kept open only while there are page hit transactions av + * ailable in the CAM to that bank. The last read or write command in the C + * AM with a bank and page hit will be executed with auto-precharge if SCHE + * D1.pageclose_timer=0. Even if this register set to 1 and SCHED1.pageclos + * e_timer is set to 0, explicit precharge (and not auto-precharge) may be + * issued in some cases where there is a mode switch between Write and Read + * or between LPR and HPR. The Read and Write commands that are executed a + * s part of the ECC scrub requests are also executed without auto-precharg + * e. If false, the bank remains open until there is a need to close it (to + * open a different page, or for page timeout or refresh timeout) - also k + * nown as open page policy. The open page policy can be overridden by sett + * ing the per-command-autopre bit on the HIF interface (hif_cmd_autopre). + * The pageclose feature provids a midway between Open and Close page polic + * ies. FOR PERFORMANCE ONLY. +*/ #undef DDRC_SCHED_PAGECLOSE_DEFVAL #undef DDRC_SCHED_PAGECLOSE_SHIFT #undef DDRC_SCHED_PAGECLOSE_MASK -#define DDRC_SCHED_PAGECLOSE_DEFVAL 0x00002005 -#define DDRC_SCHED_PAGECLOSE_SHIFT 2 -#define DDRC_SCHED_PAGECLOSE_MASK 0x00000004U +#define DDRC_SCHED_PAGECLOSE_DEFVAL 0x00002005 +#define DDRC_SCHED_PAGECLOSE_SHIFT 2 +#define DDRC_SCHED_PAGECLOSE_MASK 0x00000004U -/*If set then the bank selector prefers writes over reads. FOR DEBUG ONLY.*/ +/* +* If set then the bank selector prefers writes over reads. FOR DEBUG ONLY. +*/ #undef DDRC_SCHED_PREFER_WRITE_DEFVAL #undef DDRC_SCHED_PREFER_WRITE_SHIFT #undef DDRC_SCHED_PREFER_WRITE_MASK -#define DDRC_SCHED_PREFER_WRITE_DEFVAL 0x00002005 -#define DDRC_SCHED_PREFER_WRITE_SHIFT 1 -#define DDRC_SCHED_PREFER_WRITE_MASK 0x00000002U +#define DDRC_SCHED_PREFER_WRITE_DEFVAL 0x00002005 +#define DDRC_SCHED_PREFER_WRITE_SHIFT 1 +#define DDRC_SCHED_PREFER_WRITE_MASK 0x00000002U -/*Active low signal. When asserted ('0'), all incoming transactions are forced to low priority. This implies that all High Prio - ity Read (HPR) and Variable Priority Read commands (VPR) will be treated as Low Priority Read (LPR) commands. On the write si - e, all Variable Priority Write (VPW) commands will be treated as Normal Priority Write (NPW) commands. Forcing the incoming t - ansactions to low priority implicitly turns off Bypass path for read commands. FOR PERFORMANCE ONLY.*/ +/* +* Active low signal. When asserted ('0'), all incoming transactions are fo + * rced to low priority. This implies that all High Priority Read (HPR) and + * Variable Priority Read commands (VPR) will be treated as Low Priority R + * ead (LPR) commands. On the write side, all Variable Priority Write (VPW) + * commands will be treated as Normal Priority Write (NPW) commands. Forci + * ng the incoming transactions to low priority implicitly turns off Bypass + * path for read commands. FOR PERFORMANCE ONLY. +*/ #undef DDRC_SCHED_FORCE_LOW_PRI_N_DEFVAL #undef DDRC_SCHED_FORCE_LOW_PRI_N_SHIFT #undef DDRC_SCHED_FORCE_LOW_PRI_N_MASK -#define DDRC_SCHED_FORCE_LOW_PRI_N_DEFVAL 0x00002005 -#define DDRC_SCHED_FORCE_LOW_PRI_N_SHIFT 0 -#define DDRC_SCHED_FORCE_LOW_PRI_N_MASK 0x00000001U +#define DDRC_SCHED_FORCE_LOW_PRI_N_DEFVAL 0x00002005 +#define DDRC_SCHED_FORCE_LOW_PRI_N_SHIFT 0 +#define DDRC_SCHED_FORCE_LOW_PRI_N_MASK 0x00000001U -/*Number of transactions that are serviced once the LPR queue goes critical is the smaller of: - (a) This number - (b) Number o - transactions available. Unit: Transaction. FOR PERFORMANCE ONLY.*/ +/* +* Number of transactions that are serviced once the LPR queue goes critica + * l is the smaller of: - (a) This number - (b) Number of transactions avai + * lable. Unit: Transaction. FOR PERFORMANCE ONLY. +*/ #undef DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_DEFVAL #undef DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_SHIFT #undef DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_MASK -#define DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_DEFVAL 0x0F00007F -#define DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_SHIFT 24 -#define DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_MASK 0xFF000000U +#define DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_DEFVAL 0x0F00007F +#define DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_SHIFT 24 +#define DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_MASK 0xFF000000U -/*Number of clocks that the LPR queue can be starved before it goes critical. The minimum valid functional value for this regis - er is 0x1. Programming it to 0x0 will disable the starvation functionality; during normal operation, this function should not - be disabled as it will cause excessive latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY.*/ +/* +* Number of clocks that the LPR queue can be starved before it goes critic + * al. The minimum valid functional value for this register is 0x1. Program + * ming it to 0x0 will disable the starvation functionality; during normal + * operation, this function should not be disabled as it will cause excessi + * ve latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY. +*/ #undef DDRC_PERFLPR1_LPR_MAX_STARVE_DEFVAL #undef DDRC_PERFLPR1_LPR_MAX_STARVE_SHIFT #undef DDRC_PERFLPR1_LPR_MAX_STARVE_MASK -#define DDRC_PERFLPR1_LPR_MAX_STARVE_DEFVAL 0x0F00007F -#define DDRC_PERFLPR1_LPR_MAX_STARVE_SHIFT 0 -#define DDRC_PERFLPR1_LPR_MAX_STARVE_MASK 0x0000FFFFU +#define DDRC_PERFLPR1_LPR_MAX_STARVE_DEFVAL 0x0F00007F +#define DDRC_PERFLPR1_LPR_MAX_STARVE_SHIFT 0 +#define DDRC_PERFLPR1_LPR_MAX_STARVE_MASK 0x0000FFFFU -/*Number of transactions that are serviced once the WR queue goes critical is the smaller of: - (a) This number - (b) Number of - transactions available. Unit: Transaction. FOR PERFORMANCE ONLY.*/ +/* +* Number of transactions that are serviced once the WR queue goes critical + * is the smaller of: - (a) This number - (b) Number of transactions avail + * able. Unit: Transaction. FOR PERFORMANCE ONLY. +*/ #undef DDRC_PERFWR1_W_XACT_RUN_LENGTH_DEFVAL #undef DDRC_PERFWR1_W_XACT_RUN_LENGTH_SHIFT #undef DDRC_PERFWR1_W_XACT_RUN_LENGTH_MASK -#define DDRC_PERFWR1_W_XACT_RUN_LENGTH_DEFVAL 0x0F00007F -#define DDRC_PERFWR1_W_XACT_RUN_LENGTH_SHIFT 24 -#define DDRC_PERFWR1_W_XACT_RUN_LENGTH_MASK 0xFF000000U +#define DDRC_PERFWR1_W_XACT_RUN_LENGTH_DEFVAL 0x0F00007F +#define DDRC_PERFWR1_W_XACT_RUN_LENGTH_SHIFT 24 +#define DDRC_PERFWR1_W_XACT_RUN_LENGTH_MASK 0xFF000000U -/*Number of clocks that the WR queue can be starved before it goes critical. The minimum valid functional value for this regist - r is 0x1. Programming it to 0x0 will disable the starvation functionality; during normal operation, this function should not - e disabled as it will cause excessive latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY.*/ +/* +* Number of clocks that the WR queue can be starved before it goes critica + * l. The minimum valid functional value for this register is 0x1. Programm + * ing it to 0x0 will disable the starvation functionality; during normal o + * peration, this function should not be disabled as it will cause excessiv + * e latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY. +*/ #undef DDRC_PERFWR1_W_MAX_STARVE_DEFVAL #undef DDRC_PERFWR1_W_MAX_STARVE_SHIFT #undef DDRC_PERFWR1_W_MAX_STARVE_MASK -#define DDRC_PERFWR1_W_MAX_STARVE_DEFVAL 0x0F00007F -#define DDRC_PERFWR1_W_MAX_STARVE_SHIFT 0 -#define DDRC_PERFWR1_W_MAX_STARVE_MASK 0x0000FFFFU +#define DDRC_PERFWR1_W_MAX_STARVE_DEFVAL 0x0F00007F +#define DDRC_PERFWR1_W_MAX_STARVE_SHIFT 0 +#define DDRC_PERFWR1_W_MAX_STARVE_MASK 0x0000FFFFU -/*All even ranks have the same DQ mapping controled by DQMAP0-4 register as rank 0. This register provides DQ swap function for - all odd ranks to support CRC feature. rank based DQ swapping is: swap bit 0 with 1, swap bit 2 with 3, swap bit 4 with 5 and - wap bit 6 with 7. 1: Disable rank based DQ swapping 0: Enable rank based DQ swapping Present only in designs configured to su - port DDR4.*/ +/* +* DQ nibble map for DQ bits [12-15] Present only in designs configured to + * support DDR4. +*/ +#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_12_15_DEFVAL +#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_12_15_SHIFT +#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_12_15_MASK +#define DDRC_DQMAP0_DQ_NIBBLE_MAP_12_15_DEFVAL 0x00000000 +#define DDRC_DQMAP0_DQ_NIBBLE_MAP_12_15_SHIFT 24 +#define DDRC_DQMAP0_DQ_NIBBLE_MAP_12_15_MASK 0xFF000000U + +/* +* DQ nibble map for DQ bits [8-11] Present only in designs configured to s + * upport DDR4. +*/ +#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_8_11_DEFVAL +#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_8_11_SHIFT +#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_8_11_MASK +#define DDRC_DQMAP0_DQ_NIBBLE_MAP_8_11_DEFVAL 0x00000000 +#define DDRC_DQMAP0_DQ_NIBBLE_MAP_8_11_SHIFT 16 +#define DDRC_DQMAP0_DQ_NIBBLE_MAP_8_11_MASK 0x00FF0000U + +/* +* DQ nibble map for DQ bits [4-7] Present only in designs configured to su + * pport DDR4. +*/ +#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_4_7_DEFVAL +#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_4_7_SHIFT +#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_4_7_MASK +#define DDRC_DQMAP0_DQ_NIBBLE_MAP_4_7_DEFVAL 0x00000000 +#define DDRC_DQMAP0_DQ_NIBBLE_MAP_4_7_SHIFT 8 +#define DDRC_DQMAP0_DQ_NIBBLE_MAP_4_7_MASK 0x0000FF00U + +/* +* DQ nibble map for DQ bits [0-3] Present only in designs configured to su + * pport DDR4. +*/ +#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_0_3_DEFVAL +#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_0_3_SHIFT +#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_0_3_MASK +#define DDRC_DQMAP0_DQ_NIBBLE_MAP_0_3_DEFVAL 0x00000000 +#define DDRC_DQMAP0_DQ_NIBBLE_MAP_0_3_SHIFT 0 +#define DDRC_DQMAP0_DQ_NIBBLE_MAP_0_3_MASK 0x000000FFU + +/* +* DQ nibble map for DQ bits [28-31] Present only in designs configured to + * support DDR4. +*/ +#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_28_31_DEFVAL +#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_28_31_SHIFT +#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_28_31_MASK +#define DDRC_DQMAP1_DQ_NIBBLE_MAP_28_31_DEFVAL 0x00000000 +#define DDRC_DQMAP1_DQ_NIBBLE_MAP_28_31_SHIFT 24 +#define DDRC_DQMAP1_DQ_NIBBLE_MAP_28_31_MASK 0xFF000000U + +/* +* DQ nibble map for DQ bits [24-27] Present only in designs configured to + * support DDR4. +*/ +#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_24_27_DEFVAL +#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_24_27_SHIFT +#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_24_27_MASK +#define DDRC_DQMAP1_DQ_NIBBLE_MAP_24_27_DEFVAL 0x00000000 +#define DDRC_DQMAP1_DQ_NIBBLE_MAP_24_27_SHIFT 16 +#define DDRC_DQMAP1_DQ_NIBBLE_MAP_24_27_MASK 0x00FF0000U + +/* +* DQ nibble map for DQ bits [20-23] Present only in designs configured to + * support DDR4. +*/ +#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_20_23_DEFVAL +#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_20_23_SHIFT +#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_20_23_MASK +#define DDRC_DQMAP1_DQ_NIBBLE_MAP_20_23_DEFVAL 0x00000000 +#define DDRC_DQMAP1_DQ_NIBBLE_MAP_20_23_SHIFT 8 +#define DDRC_DQMAP1_DQ_NIBBLE_MAP_20_23_MASK 0x0000FF00U + +/* +* DQ nibble map for DQ bits [16-19] Present only in designs configured to + * support DDR4. +*/ +#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_16_19_DEFVAL +#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_16_19_SHIFT +#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_16_19_MASK +#define DDRC_DQMAP1_DQ_NIBBLE_MAP_16_19_DEFVAL 0x00000000 +#define DDRC_DQMAP1_DQ_NIBBLE_MAP_16_19_SHIFT 0 +#define DDRC_DQMAP1_DQ_NIBBLE_MAP_16_19_MASK 0x000000FFU + +/* +* DQ nibble map for DQ bits [44-47] Present only in designs configured to + * support DDR4. +*/ +#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_44_47_DEFVAL +#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_44_47_SHIFT +#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_44_47_MASK +#define DDRC_DQMAP2_DQ_NIBBLE_MAP_44_47_DEFVAL 0x00000000 +#define DDRC_DQMAP2_DQ_NIBBLE_MAP_44_47_SHIFT 24 +#define DDRC_DQMAP2_DQ_NIBBLE_MAP_44_47_MASK 0xFF000000U + +/* +* DQ nibble map for DQ bits [40-43] Present only in designs configured to + * support DDR4. +*/ +#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_40_43_DEFVAL +#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_40_43_SHIFT +#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_40_43_MASK +#define DDRC_DQMAP2_DQ_NIBBLE_MAP_40_43_DEFVAL 0x00000000 +#define DDRC_DQMAP2_DQ_NIBBLE_MAP_40_43_SHIFT 16 +#define DDRC_DQMAP2_DQ_NIBBLE_MAP_40_43_MASK 0x00FF0000U + +/* +* DQ nibble map for DQ bits [36-39] Present only in designs configured to + * support DDR4. +*/ +#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_36_39_DEFVAL +#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_36_39_SHIFT +#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_36_39_MASK +#define DDRC_DQMAP2_DQ_NIBBLE_MAP_36_39_DEFVAL 0x00000000 +#define DDRC_DQMAP2_DQ_NIBBLE_MAP_36_39_SHIFT 8 +#define DDRC_DQMAP2_DQ_NIBBLE_MAP_36_39_MASK 0x0000FF00U + +/* +* DQ nibble map for DQ bits [32-35] Present only in designs configured to + * support DDR4. +*/ +#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_32_35_DEFVAL +#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_32_35_SHIFT +#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_32_35_MASK +#define DDRC_DQMAP2_DQ_NIBBLE_MAP_32_35_DEFVAL 0x00000000 +#define DDRC_DQMAP2_DQ_NIBBLE_MAP_32_35_SHIFT 0 +#define DDRC_DQMAP2_DQ_NIBBLE_MAP_32_35_MASK 0x000000FFU + +/* +* DQ nibble map for DQ bits [60-63] Present only in designs configured to + * support DDR4. +*/ +#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_60_63_DEFVAL +#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_60_63_SHIFT +#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_60_63_MASK +#define DDRC_DQMAP3_DQ_NIBBLE_MAP_60_63_DEFVAL 0x00000000 +#define DDRC_DQMAP3_DQ_NIBBLE_MAP_60_63_SHIFT 24 +#define DDRC_DQMAP3_DQ_NIBBLE_MAP_60_63_MASK 0xFF000000U + +/* +* DQ nibble map for DQ bits [56-59] Present only in designs configured to + * support DDR4. +*/ +#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_56_59_DEFVAL +#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_56_59_SHIFT +#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_56_59_MASK +#define DDRC_DQMAP3_DQ_NIBBLE_MAP_56_59_DEFVAL 0x00000000 +#define DDRC_DQMAP3_DQ_NIBBLE_MAP_56_59_SHIFT 16 +#define DDRC_DQMAP3_DQ_NIBBLE_MAP_56_59_MASK 0x00FF0000U + +/* +* DQ nibble map for DQ bits [52-55] Present only in designs configured to + * support DDR4. +*/ +#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_52_55_DEFVAL +#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_52_55_SHIFT +#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_52_55_MASK +#define DDRC_DQMAP3_DQ_NIBBLE_MAP_52_55_DEFVAL 0x00000000 +#define DDRC_DQMAP3_DQ_NIBBLE_MAP_52_55_SHIFT 8 +#define DDRC_DQMAP3_DQ_NIBBLE_MAP_52_55_MASK 0x0000FF00U + +/* +* DQ nibble map for DQ bits [48-51] Present only in designs configured to + * support DDR4. +*/ +#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_48_51_DEFVAL +#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_48_51_SHIFT +#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_48_51_MASK +#define DDRC_DQMAP3_DQ_NIBBLE_MAP_48_51_DEFVAL 0x00000000 +#define DDRC_DQMAP3_DQ_NIBBLE_MAP_48_51_SHIFT 0 +#define DDRC_DQMAP3_DQ_NIBBLE_MAP_48_51_MASK 0x000000FFU + +/* +* DQ nibble map for DIMM ECC check bits [4-7] Present only in designs conf + * igured to support DDR4. +*/ +#undef DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_4_7_DEFVAL +#undef DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_4_7_SHIFT +#undef DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_4_7_MASK +#define DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_4_7_DEFVAL 0x00000000 +#define DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_4_7_SHIFT 8 +#define DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_4_7_MASK 0x0000FF00U + +/* +* DQ nibble map for DIMM ECC check bits [0-3] Present only in designs conf + * igured to support DDR4. +*/ +#undef DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_0_3_DEFVAL +#undef DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_0_3_SHIFT +#undef DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_0_3_MASK +#define DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_0_3_DEFVAL 0x00000000 +#define DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_0_3_SHIFT 0 +#define DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_0_3_MASK 0x000000FFU + +/* +* All even ranks have the same DQ mapping controled by DQMAP0-4 register a + * s rank 0. This register provides DQ swap function for all odd ranks to s + * upport CRC feature. rank based DQ swapping is: swap bit 0 with 1, swap b + * it 2 with 3, swap bit 4 with 5 and swap bit 6 with 7. 1: Disable rank ba + * sed DQ swapping 0: Enable rank based DQ swapping Present only in designs + * configured to support DDR4. +*/ #undef DDRC_DQMAP5_DIS_DQ_RANK_SWAP_DEFVAL #undef DDRC_DQMAP5_DIS_DQ_RANK_SWAP_SHIFT #undef DDRC_DQMAP5_DIS_DQ_RANK_SWAP_MASK -#define DDRC_DQMAP5_DIS_DQ_RANK_SWAP_DEFVAL -#define DDRC_DQMAP5_DIS_DQ_RANK_SWAP_SHIFT 0 -#define DDRC_DQMAP5_DIS_DQ_RANK_SWAP_MASK 0x00000001U +#define DDRC_DQMAP5_DIS_DQ_RANK_SWAP_DEFVAL +#define DDRC_DQMAP5_DIS_DQ_RANK_SWAP_SHIFT 0 +#define DDRC_DQMAP5_DIS_DQ_RANK_SWAP_MASK 0x00000001U -/*When this is set to '0', auto-precharge is disabled for the flushed command in a collision case. Collision cases are write fo - lowed by read to same address, read followed by write to same address, or write followed by write to same address with DBG0.d - s_wc bit = 1 (where same address comparisons exclude the two address bits representing critical word). FOR DEBUG ONLY.*/ +/* +* When this is set to '0', auto-precharge is disabled for the flushed comm + * and in a collision case. Collision cases are write followed by read to s + * ame address, read followed by write to same address, or write followed b + * y write to same address with DBG0.dis_wc bit = 1 (where same address com + * parisons exclude the two address bits representing critical word). FOR D + * EBUG ONLY. +*/ #undef DDRC_DBG0_DIS_COLLISION_PAGE_OPT_DEFVAL #undef DDRC_DBG0_DIS_COLLISION_PAGE_OPT_SHIFT #undef DDRC_DBG0_DIS_COLLISION_PAGE_OPT_MASK -#define DDRC_DBG0_DIS_COLLISION_PAGE_OPT_DEFVAL 0x00000000 -#define DDRC_DBG0_DIS_COLLISION_PAGE_OPT_SHIFT 4 -#define DDRC_DBG0_DIS_COLLISION_PAGE_OPT_MASK 0x00000010U +#define DDRC_DBG0_DIS_COLLISION_PAGE_OPT_DEFVAL 0x00000000 +#define DDRC_DBG0_DIS_COLLISION_PAGE_OPT_SHIFT 4 +#define DDRC_DBG0_DIS_COLLISION_PAGE_OPT_MASK 0x00000010U -/*When 1, disable write combine. FOR DEBUG ONLY*/ +/* +* When 1, disable write combine. FOR DEBUG ONLY +*/ #undef DDRC_DBG0_DIS_WC_DEFVAL #undef DDRC_DBG0_DIS_WC_SHIFT #undef DDRC_DBG0_DIS_WC_MASK -#define DDRC_DBG0_DIS_WC_DEFVAL 0x00000000 -#define DDRC_DBG0_DIS_WC_SHIFT 0 -#define DDRC_DBG0_DIS_WC_MASK 0x00000001U +#define DDRC_DBG0_DIS_WC_DEFVAL 0x00000000 +#define DDRC_DBG0_DIS_WC_SHIFT 0 +#define DDRC_DBG0_DIS_WC_MASK 0x00000001U -/*Setting this register bit to 1 allows refresh and ZQCS commands to be triggered from hardware via the IOs ext_*. If set to 1, - the fields DBGCMD.zq_calib_short and DBGCMD.rank*_refresh have no function, and are ignored by the uMCTL2 logic. Setting this - register bit to 0 allows refresh and ZQCS to be triggered from software, via the fields DBGCMD.zq_calib_short and DBGCMD.rank - _refresh. If set to 0, the hardware pins ext_* have no function, and are ignored by the uMCTL2 logic. This register is static - and may only be changed when the DDRC reset signal, core_ddrc_rstn, is asserted (0).*/ +/* +* Setting this register bit to 1 allows refresh and ZQCS commands to be tr + * iggered from hardware via the IOs ext_*. If set to 1, the fields DBGCMD. + * zq_calib_short and DBGCMD.rank*_refresh have no function, and are ignore + * d by the uMCTL2 logic. Setting this register bit to 0 allows refresh and + * ZQCS to be triggered from software, via the fields DBGCMD.zq_calib_shor + * t and DBGCMD.rank*_refresh. If set to 0, the hardware pins ext_* have no + * function, and are ignored by the uMCTL2 logic. This register is static, + * and may only be changed when the DDRC reset signal, core_ddrc_rstn, is + * asserted (0). +*/ #undef DDRC_DBGCMD_HW_REF_ZQ_EN_DEFVAL #undef DDRC_DBGCMD_HW_REF_ZQ_EN_SHIFT #undef DDRC_DBGCMD_HW_REF_ZQ_EN_MASK -#define DDRC_DBGCMD_HW_REF_ZQ_EN_DEFVAL 0x00000000 -#define DDRC_DBGCMD_HW_REF_ZQ_EN_SHIFT 31 -#define DDRC_DBGCMD_HW_REF_ZQ_EN_MASK 0x80000000U +#define DDRC_DBGCMD_HW_REF_ZQ_EN_DEFVAL 0x00000000 +#define DDRC_DBGCMD_HW_REF_ZQ_EN_SHIFT 31 +#define DDRC_DBGCMD_HW_REF_ZQ_EN_MASK 0x80000000U -/*Setting this register bit to 1 indicates to the uMCTL2 to issue a dfi_ctrlupd_req to the PHY. When this request is stored in - he uMCTL2, the bit is automatically cleared. This operation must only be performed when DFIUPD0.dis_auto_ctrlupd=1.*/ +/* +* Setting this register bit to 1 indicates to the uMCTL2 to issue a dfi_ct + * rlupd_req to the PHY. When this request is stored in the uMCTL2, the bit + * is automatically cleared. This operation must only be performed when DF + * IUPD0.dis_auto_ctrlupd=1. +*/ #undef DDRC_DBGCMD_CTRLUPD_DEFVAL #undef DDRC_DBGCMD_CTRLUPD_SHIFT #undef DDRC_DBGCMD_CTRLUPD_MASK -#define DDRC_DBGCMD_CTRLUPD_DEFVAL 0x00000000 -#define DDRC_DBGCMD_CTRLUPD_SHIFT 5 -#define DDRC_DBGCMD_CTRLUPD_MASK 0x00000020U +#define DDRC_DBGCMD_CTRLUPD_DEFVAL 0x00000000 +#define DDRC_DBGCMD_CTRLUPD_SHIFT 5 +#define DDRC_DBGCMD_CTRLUPD_MASK 0x00000020U -/*Setting this register bit to 1 indicates to the uMCTL2 to issue a ZQCS (ZQ calibration short)/MPC(ZQ calibration) command to - he SDRAM. When this request is stored in the uMCTL2, the bit is automatically cleared. This operation can be performed only w - en ZQCTL0.dis_auto_zq=1. It is recommended NOT to set this register bit if in Init operating mode. This register bit is ignor - d when in Self-Refresh(except LPDDR4) and SR-Powerdown(LPDDR4) and Deep power-down operating modes and Maximum Power Saving M - de.*/ +/* +* Setting this register bit to 1 indicates to the uMCTL2 to issue a ZQCS ( + * ZQ calibration short)/MPC(ZQ calibration) command to the SDRAM. When thi + * s request is stored in the uMCTL2, the bit is automatically cleared. Thi + * s operation can be performed only when ZQCTL0.dis_auto_zq=1. It is recom + * mended NOT to set this register bit if in Init operating mode. This regi + * ster bit is ignored when in Self-Refresh(except LPDDR4) and SR-Powerdown + * (LPDDR4) and Deep power-down operating modes and Maximum Power Saving Mo + * de. +*/ #undef DDRC_DBGCMD_ZQ_CALIB_SHORT_DEFVAL #undef DDRC_DBGCMD_ZQ_CALIB_SHORT_SHIFT #undef DDRC_DBGCMD_ZQ_CALIB_SHORT_MASK -#define DDRC_DBGCMD_ZQ_CALIB_SHORT_DEFVAL 0x00000000 -#define DDRC_DBGCMD_ZQ_CALIB_SHORT_SHIFT 4 -#define DDRC_DBGCMD_ZQ_CALIB_SHORT_MASK 0x00000010U +#define DDRC_DBGCMD_ZQ_CALIB_SHORT_DEFVAL 0x00000000 +#define DDRC_DBGCMD_ZQ_CALIB_SHORT_SHIFT 4 +#define DDRC_DBGCMD_ZQ_CALIB_SHORT_MASK 0x00000010U -/*Setting this register bit to 1 indicates to the uMCTL2 to issue a refresh to rank 1. Writing to this bit causes DBGSTAT.rank1 - refresh_busy to be set. When DBGSTAT.rank1_refresh_busy is cleared, the command has been stored in uMCTL2. This operation can - be performed only when RFSHCTL3.dis_auto_refresh=1. It is recommended NOT to set this register bit if in Init or Deep power-d - wn operating modes or Maximum Power Saving Mode.*/ +/* +* Setting this register bit to 1 indicates to the uMCTL2 to issue a refres + * h to rank 1. Writing to this bit causes DBGSTAT.rank1_refresh_busy to be + * set. When DBGSTAT.rank1_refresh_busy is cleared, the command has been s + * tored in uMCTL2. This operation can be performed only when RFSHCTL3.dis_ + * auto_refresh=1. It is recommended NOT to set this register bit if in Ini + * t or Deep power-down operating modes or Maximum Power Saving Mode. +*/ #undef DDRC_DBGCMD_RANK1_REFRESH_DEFVAL #undef DDRC_DBGCMD_RANK1_REFRESH_SHIFT #undef DDRC_DBGCMD_RANK1_REFRESH_MASK -#define DDRC_DBGCMD_RANK1_REFRESH_DEFVAL 0x00000000 -#define DDRC_DBGCMD_RANK1_REFRESH_SHIFT 1 -#define DDRC_DBGCMD_RANK1_REFRESH_MASK 0x00000002U +#define DDRC_DBGCMD_RANK1_REFRESH_DEFVAL 0x00000000 +#define DDRC_DBGCMD_RANK1_REFRESH_SHIFT 1 +#define DDRC_DBGCMD_RANK1_REFRESH_MASK 0x00000002U -/*Setting this register bit to 1 indicates to the uMCTL2 to issue a refresh to rank 0. Writing to this bit causes DBGSTAT.rank0 - refresh_busy to be set. When DBGSTAT.rank0_refresh_busy is cleared, the command has been stored in uMCTL2. This operation can - be performed only when RFSHCTL3.dis_auto_refresh=1. It is recommended NOT to set this register bit if in Init or Deep power-d - wn operating modes or Maximum Power Saving Mode.*/ +/* +* Setting this register bit to 1 indicates to the uMCTL2 to issue a refres + * h to rank 0. Writing to this bit causes DBGSTAT.rank0_refresh_busy to be + * set. When DBGSTAT.rank0_refresh_busy is cleared, the command has been s + * tored in uMCTL2. This operation can be performed only when RFSHCTL3.dis_ + * auto_refresh=1. It is recommended NOT to set this register bit if in Ini + * t or Deep power-down operating modes or Maximum Power Saving Mode. +*/ #undef DDRC_DBGCMD_RANK0_REFRESH_DEFVAL #undef DDRC_DBGCMD_RANK0_REFRESH_SHIFT #undef DDRC_DBGCMD_RANK0_REFRESH_MASK -#define DDRC_DBGCMD_RANK0_REFRESH_DEFVAL 0x00000000 -#define DDRC_DBGCMD_RANK0_REFRESH_SHIFT 0 -#define DDRC_DBGCMD_RANK0_REFRESH_MASK 0x00000001U +#define DDRC_DBGCMD_RANK0_REFRESH_DEFVAL 0x00000000 +#define DDRC_DBGCMD_RANK0_REFRESH_SHIFT 0 +#define DDRC_DBGCMD_RANK0_REFRESH_MASK 0x00000001U -/*Enable quasi-dynamic register programming outside reset. Program register to 0 to enable quasi-dynamic programming. Set back - egister to 1 once programming is done.*/ +/* +* Enable quasi-dynamic register programming outside reset. Program registe + * r to 0 to enable quasi-dynamic programming. Set back register to 1 once + * programming is done. +*/ #undef DDRC_SWCTL_SW_DONE_DEFVAL #undef DDRC_SWCTL_SW_DONE_SHIFT #undef DDRC_SWCTL_SW_DONE_MASK -#define DDRC_SWCTL_SW_DONE_DEFVAL -#define DDRC_SWCTL_SW_DONE_SHIFT 0 -#define DDRC_SWCTL_SW_DONE_MASK 0x00000001U +#define DDRC_SWCTL_SW_DONE_DEFVAL +#define DDRC_SWCTL_SW_DONE_SHIFT 0 +#define DDRC_SWCTL_SW_DONE_MASK 0x00000001U -/*Burst length expansion mode. By default (i.e. bl_exp_mode==0) XPI expands every AXI burst into multiple HIF commands, using t - e memory burst length as a unit. If set to 1, then XPI will use half of the memory burst length as a unit. This applies to bo - h reads and writes. When MSTR.data_bus_width==00, setting bl_exp_mode to 1 has no effect. This can be used in cases where Par - ial Writes is enabled (UMCTL2_PARTIAL_WR=1) and DBG0.dis_wc=1, in order to avoid or minimize t_ccd_l penalty in DDR4 and t_cc - _mw penalty in LPDDR4. Note that if DBICTL.reg_ddrc_dm_en=0, functionality is not supported in the following cases: - UMCTL2_ - ARTIAL_WR=0 - UMCTL2_PARTIAL_WR=1, MSTR.reg_ddrc_data_bus_width=01, MEMC_BURST_LENGTH=8 and MSTR.reg_ddrc_burst_rdwr=1000 (LP - DR4 only) - UMCTL2_PARTIAL_WR=1, MSTR.reg_ddrc_data_bus_width=01, MEMC_BURST_LENGTH=4 and MSTR.reg_ddrc_burst_rdwr=0100 (DDR4 - only), with either MSTR.reg_ddrc_burstchop=0 or CRCPARCTL1.reg_ddrc_crc_enable=1 Functionality is also not supported if Share - -AC is enabled*/ +/* +* Burst length expansion mode. By default (i.e. bl_exp_mode==0) XPI expand + * s every AXI burst into multiple HIF commands, using the memory burst len + * gth as a unit. If set to 1, then XPI will use half of the memory burst l + * ength as a unit. This applies to both reads and writes. When MSTR.data_b + * us_width==00, setting bl_exp_mode to 1 has no effect. This can be used i + * n cases where Partial Writes is enabled (UMCTL2_PARTIAL_WR=1) and DBG0.d + * is_wc=1, in order to avoid or minimize t_ccd_l penalty in DDR4 and t_ccd + * _mw penalty in LPDDR4. Note that if DBICTL.reg_ddrc_dm_en=0, functionali + * ty is not supported in the following cases: - UMCTL2_PARTIAL_WR=0 - UMCT + * L2_PARTIAL_WR=1, MSTR.reg_ddrc_data_bus_width=01, MEMC_BURST_LENGTH=8 an + * d MSTR.reg_ddrc_burst_rdwr=1000 (LPDDR4 only) - UMCTL2_PARTIAL_WR=1, MST + * R.reg_ddrc_data_bus_width=01, MEMC_BURST_LENGTH=4 and MSTR.reg_ddrc_burs + * t_rdwr=0100 (DDR4 only), with either MSTR.reg_ddrc_burstchop=0 or CRCPAR + * CTL1.reg_ddrc_crc_enable=1 Functionality is also not supported if Shared + * -AC is enabled +*/ #undef DDRC_PCCFG_BL_EXP_MODE_DEFVAL #undef DDRC_PCCFG_BL_EXP_MODE_SHIFT #undef DDRC_PCCFG_BL_EXP_MODE_MASK -#define DDRC_PCCFG_BL_EXP_MODE_DEFVAL 0x00000000 -#define DDRC_PCCFG_BL_EXP_MODE_SHIFT 8 -#define DDRC_PCCFG_BL_EXP_MODE_MASK 0x00000100U +#define DDRC_PCCFG_BL_EXP_MODE_DEFVAL 0x00000000 +#define DDRC_PCCFG_BL_EXP_MODE_SHIFT 8 +#define DDRC_PCCFG_BL_EXP_MODE_MASK 0x00000100U -/*Page match four limit. If set to 1, limits the number of consecutive same page DDRC transactions that can be granted by the P - rt Arbiter to four when Page Match feature is enabled. If set to 0, there is no limit imposed on number of consecutive same p - ge DDRC transactions.*/ +/* +* Page match four limit. If set to 1, limits the number of consecutive sam + * e page DDRC transactions that can be granted by the Port Arbiter to four + * when Page Match feature is enabled. If set to 0, there is no limit impo + * sed on number of consecutive same page DDRC transactions. +*/ #undef DDRC_PCCFG_PAGEMATCH_LIMIT_DEFVAL #undef DDRC_PCCFG_PAGEMATCH_LIMIT_SHIFT #undef DDRC_PCCFG_PAGEMATCH_LIMIT_MASK -#define DDRC_PCCFG_PAGEMATCH_LIMIT_DEFVAL 0x00000000 -#define DDRC_PCCFG_PAGEMATCH_LIMIT_SHIFT 4 -#define DDRC_PCCFG_PAGEMATCH_LIMIT_MASK 0x00000010U +#define DDRC_PCCFG_PAGEMATCH_LIMIT_DEFVAL 0x00000000 +#define DDRC_PCCFG_PAGEMATCH_LIMIT_SHIFT 4 +#define DDRC_PCCFG_PAGEMATCH_LIMIT_MASK 0x00000010U -/*If set to 1 (enabled), sets co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals going to DDRC based - n urgent input (awurgent, arurgent) coming from AXI master. If set to 0 (disabled), co_gs_go2critical_wr and co_gs_go2critica - _lpr/co_gs_go2critical_hpr signals at DDRC are driven to 1b'0.*/ +/* +* If set to 1 (enabled), sets co_gs_go2critical_wr and co_gs_go2critical_l + * pr/co_gs_go2critical_hpr signals going to DDRC based on urgent input (aw + * urgent, arurgent) coming from AXI master. If set to 0 (disabled), co_gs_ + * go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals a + * t DDRC are driven to 1b'0. +*/ #undef DDRC_PCCFG_GO2CRITICAL_EN_DEFVAL #undef DDRC_PCCFG_GO2CRITICAL_EN_SHIFT #undef DDRC_PCCFG_GO2CRITICAL_EN_MASK -#define DDRC_PCCFG_GO2CRITICAL_EN_DEFVAL 0x00000000 -#define DDRC_PCCFG_GO2CRITICAL_EN_SHIFT 0 -#define DDRC_PCCFG_GO2CRITICAL_EN_MASK 0x00000001U +#define DDRC_PCCFG_GO2CRITICAL_EN_DEFVAL 0x00000000 +#define DDRC_PCCFG_GO2CRITICAL_EN_SHIFT 0 +#define DDRC_PCCFG_GO2CRITICAL_EN_MASK 0x00000001U -/*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register.*/ +/* +* If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. +*/ #undef DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_DEFVAL #undef DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_SHIFT #undef DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_MASK -#define DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_DEFVAL 0x00000000 -#define DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_SHIFT 14 -#define DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_MASK 0x00004000U +#define DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_SHIFT 14 +#define DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_MASK 0x00004000U -/*If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG. - o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add - ess handshaking (it is not associated with any particular command).*/ +/* +* If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + * bled and arurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + * urgent signal can be asserted anytime and as long as required which is i + * ndependent of address handshaking (it is not associated with any particu + * lar command). +*/ #undef DDRC_PCFGR_0_RD_PORT_URGENT_EN_DEFVAL #undef DDRC_PCFGR_0_RD_PORT_URGENT_EN_SHIFT #undef DDRC_PCFGR_0_RD_PORT_URGENT_EN_MASK -#define DDRC_PCFGR_0_RD_PORT_URGENT_EN_DEFVAL 0x00000000 -#define DDRC_PCFGR_0_RD_PORT_URGENT_EN_SHIFT 13 -#define DDRC_PCFGR_0_RD_PORT_URGENT_EN_MASK 0x00002000U +#define DDRC_PCFGR_0_RD_PORT_URGENT_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_0_RD_PORT_URGENT_EN_SHIFT 13 +#define DDRC_PCFGR_0_RD_PORT_URGENT_EN_MASK 0x00002000U -/*If set to 1, enables aging function for the read channel of the port.*/ +/* +* If set to 1, enables aging function for the read channel of the port. +*/ #undef DDRC_PCFGR_0_RD_PORT_AGING_EN_DEFVAL #undef DDRC_PCFGR_0_RD_PORT_AGING_EN_SHIFT #undef DDRC_PCFGR_0_RD_PORT_AGING_EN_MASK -#define DDRC_PCFGR_0_RD_PORT_AGING_EN_DEFVAL 0x00000000 -#define DDRC_PCFGR_0_RD_PORT_AGING_EN_SHIFT 12 -#define DDRC_PCFGR_0_RD_PORT_AGING_EN_MASK 0x00001000U +#define DDRC_PCFGR_0_RD_PORT_AGING_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_0_RD_PORT_AGING_EN_SHIFT 12 +#define DDRC_PCFGR_0_RD_PORT_AGING_EN_MASK 0x00001000U -/*Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g - ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority - will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre - ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the - aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st - ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w - ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D - RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: - he two LSBs of this register field are tied internally to 2'b00.*/ +/* +* Determines the initial load value of read aging counters. These counters + * will be parallel loaded after reset, or after each grant to the corresp + * onding port. The aging counters down-count every clock cycle where the p + * ort is requesting but not granted. The higher significant 5-bits of the + * read aging counter sets the priority of the read channel of a given port + * . Port's priority will increase as the higher significant 5-bits of the + * counter starts to decrease. When the aging counter becomes 0, the corres + * ponding port channel will have the highest priority level (timeout condi + * tion - Priority0). For multi-port configurations, the aging counters can + * not be used to set port priorities when external dynamic priority inputs + * (arqos) are enabled (timeout is still applicable). For single port conf + * igurations, the aging counters are only used when they timeout (become 0 + * ) to force read-write direction switching. In this case, external dynami + * c priority input, arqos (for reads only) can still be used to set the DD + * RC read priority (2 priority levels: low priority read - LPR, high prior + * ity read - HPR) on a command by command basis. Note: The two LSBs of thi + * s register field are tied internally to 2'b00. +*/ #undef DDRC_PCFGR_0_RD_PORT_PRIORITY_DEFVAL #undef DDRC_PCFGR_0_RD_PORT_PRIORITY_SHIFT #undef DDRC_PCFGR_0_RD_PORT_PRIORITY_MASK -#define DDRC_PCFGR_0_RD_PORT_PRIORITY_DEFVAL 0x00000000 -#define DDRC_PCFGR_0_RD_PORT_PRIORITY_SHIFT 0 -#define DDRC_PCFGR_0_RD_PORT_PRIORITY_MASK 0x000003FFU +#define DDRC_PCFGR_0_RD_PORT_PRIORITY_DEFVAL 0x00000000 +#define DDRC_PCFGR_0_RD_PORT_PRIORITY_SHIFT 0 +#define DDRC_PCFGR_0_RD_PORT_PRIORITY_MASK 0x000003FFU -/*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register.*/ +/* +* If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. +*/ #undef DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_DEFVAL #undef DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_SHIFT #undef DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_MASK -#define DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_DEFVAL 0x00004000 -#define DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_SHIFT 14 -#define DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_MASK 0x00004000U +#define DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_SHIFT 14 +#define DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_MASK 0x00004000U -/*If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register - Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is - not associated with any particular command).*/ +/* +* If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + * bled and awurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + * serted anytime and as long as required which is independent of address h + * andshaking (it is not associated with any particular command). +*/ #undef DDRC_PCFGW_0_WR_PORT_URGENT_EN_DEFVAL #undef DDRC_PCFGW_0_WR_PORT_URGENT_EN_SHIFT #undef DDRC_PCFGW_0_WR_PORT_URGENT_EN_MASK -#define DDRC_PCFGW_0_WR_PORT_URGENT_EN_DEFVAL 0x00004000 -#define DDRC_PCFGW_0_WR_PORT_URGENT_EN_SHIFT 13 -#define DDRC_PCFGW_0_WR_PORT_URGENT_EN_MASK 0x00002000U +#define DDRC_PCFGW_0_WR_PORT_URGENT_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_0_WR_PORT_URGENT_EN_SHIFT 13 +#define DDRC_PCFGW_0_WR_PORT_URGENT_EN_MASK 0x00002000U -/*If set to 1, enables aging function for the write channel of the port.*/ +/* +* If set to 1, enables aging function for the write channel of the port. +*/ #undef DDRC_PCFGW_0_WR_PORT_AGING_EN_DEFVAL #undef DDRC_PCFGW_0_WR_PORT_AGING_EN_SHIFT #undef DDRC_PCFGW_0_WR_PORT_AGING_EN_MASK -#define DDRC_PCFGW_0_WR_PORT_AGING_EN_DEFVAL 0x00004000 -#define DDRC_PCFGW_0_WR_PORT_AGING_EN_SHIFT 12 -#define DDRC_PCFGW_0_WR_PORT_AGING_EN_MASK 0x00001000U +#define DDRC_PCFGW_0_WR_PORT_AGING_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_0_WR_PORT_AGING_EN_SHIFT 12 +#define DDRC_PCFGW_0_WR_PORT_AGING_EN_MASK 0x00001000U -/*Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each - rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port - s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0 - the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno - be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For - ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch - ng. Note: The two LSBs of this register field are tied internally to 2'b00.*/ +/* +* Determines the initial load value of write aging counters. These counter + * s will be parallel loaded after reset, or after each grant to the corres + * ponding port. The aging counters down-count every clock cycle where the + * port is requesting but not granted. The higher significant 5-bits of the + * write aging counter sets the initial priority of the write channel of a + * given port. Port's priority will increase as the higher significant 5-b + * its of the counter starts to decrease. When the aging counter becomes 0, + * the corresponding port channel will have the highest priority level. Fo + * r multi-port configurations, the aging counters cannot be used to set po + * rt priorities when external dynamic priority inputs (awqos) are enabled + * (timeout is still applicable). For single port configurations, the aging + * counters are only used when they timeout (become 0) to force read-write + * direction switching. Note: The two LSBs of this register field are tied + * internally to 2'b00. +*/ #undef DDRC_PCFGW_0_WR_PORT_PRIORITY_DEFVAL #undef DDRC_PCFGW_0_WR_PORT_PRIORITY_SHIFT #undef DDRC_PCFGW_0_WR_PORT_PRIORITY_MASK -#define DDRC_PCFGW_0_WR_PORT_PRIORITY_DEFVAL 0x00004000 -#define DDRC_PCFGW_0_WR_PORT_PRIORITY_SHIFT 0 -#define DDRC_PCFGW_0_WR_PORT_PRIORITY_MASK 0x000003FFU +#define DDRC_PCFGW_0_WR_PORT_PRIORITY_DEFVAL 0x00004000 +#define DDRC_PCFGW_0_WR_PORT_PRIORITY_SHIFT 0 +#define DDRC_PCFGW_0_WR_PORT_PRIORITY_MASK 0x000003FFU -/*Enables port n.*/ +/* +* Enables port n. +*/ #undef DDRC_PCTRL_0_PORT_EN_DEFVAL #undef DDRC_PCTRL_0_PORT_EN_SHIFT #undef DDRC_PCTRL_0_PORT_EN_MASK -#define DDRC_PCTRL_0_PORT_EN_DEFVAL -#define DDRC_PCTRL_0_PORT_EN_SHIFT 0 -#define DDRC_PCTRL_0_PORT_EN_MASK 0x00000001U +#define DDRC_PCTRL_0_PORT_EN_DEFVAL +#define DDRC_PCTRL_0_PORT_EN_SHIFT 0 +#define DDRC_PCTRL_0_PORT_EN_MASK 0x00000001U -/*This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf - gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is - disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/ +/* +* This bitfield indicates the traffic class of region 1. Valid values are: + * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + * maps to the blue address queue. In this case, valid values are 0: LPR a + * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. +*/ #undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_DEFVAL #undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_SHIFT #undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_MASK -#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_DEFVAL 0x00000000 -#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_SHIFT 20 -#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_MASK 0x00300000U +#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_DEFVAL 0x00000000 +#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_SHIFT 20 +#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_MASK 0x00300000U -/*This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi - urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i - disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/ +/* +* This bitfield indicates the traffic class of region 0. Valid values are: + * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + * maps to the blue address queue. In this case, valid values are: 0: LPR + * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. +*/ #undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_DEFVAL #undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_SHIFT #undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_MASK -#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_DEFVAL 0x00000000 -#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_SHIFT 16 -#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_MASK 0x00030000U +#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_DEFVAL 0x00000000 +#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_SHIFT 16 +#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_MASK 0x00030000U -/*Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d - al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio - ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc - values.*/ +/* +* Separation level1 indicating the end of region0 mapping; start of region + * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + * lues are used directly as port priorities, where the higher the value co + * rresponds to higher port priority. All of the map_level* registers must + * be set to distinct values. +*/ #undef DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_DEFVAL #undef DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_SHIFT #undef DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_MASK -#define DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_DEFVAL 0x00000000 -#define DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_SHIFT 0 -#define DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_MASK 0x0000000FU +#define DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_DEFVAL 0x00000000 +#define DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_SHIFT 0 +#define DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_MASK 0x0000000FU -/*Specifies the timeout value for transactions mapped to the red address queue.*/ +/* +* Specifies the timeout value for transactions mapped to the red address q + * ueue. +*/ #undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_DEFVAL #undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_SHIFT #undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_MASK -#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_DEFVAL 0x00000000 -#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_SHIFT 16 -#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_MASK 0x07FF0000U +#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_DEFVAL 0x00000000 +#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_SHIFT 16 +#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_MASK 0x07FF0000U -/*Specifies the timeout value for transactions mapped to the blue address queue.*/ +/* +* Specifies the timeout value for transactions mapped to the blue address + * queue. +*/ #undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_DEFVAL #undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_SHIFT #undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_MASK -#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_DEFVAL 0x00000000 -#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_SHIFT 0 -#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_MASK 0x000007FFU +#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_DEFVAL 0x00000000 +#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_SHIFT 0 +#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_MASK 0x000007FFU -/*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register.*/ +/* +* If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. +*/ #undef DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_DEFVAL #undef DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_SHIFT #undef DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_MASK -#define DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_DEFVAL 0x00000000 -#define DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_SHIFT 14 -#define DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_MASK 0x00004000U +#define DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_SHIFT 14 +#define DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_MASK 0x00004000U -/*If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG. - o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add - ess handshaking (it is not associated with any particular command).*/ +/* +* If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + * bled and arurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + * urgent signal can be asserted anytime and as long as required which is i + * ndependent of address handshaking (it is not associated with any particu + * lar command). +*/ #undef DDRC_PCFGR_1_RD_PORT_URGENT_EN_DEFVAL #undef DDRC_PCFGR_1_RD_PORT_URGENT_EN_SHIFT #undef DDRC_PCFGR_1_RD_PORT_URGENT_EN_MASK -#define DDRC_PCFGR_1_RD_PORT_URGENT_EN_DEFVAL 0x00000000 -#define DDRC_PCFGR_1_RD_PORT_URGENT_EN_SHIFT 13 -#define DDRC_PCFGR_1_RD_PORT_URGENT_EN_MASK 0x00002000U +#define DDRC_PCFGR_1_RD_PORT_URGENT_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_1_RD_PORT_URGENT_EN_SHIFT 13 +#define DDRC_PCFGR_1_RD_PORT_URGENT_EN_MASK 0x00002000U -/*If set to 1, enables aging function for the read channel of the port.*/ +/* +* If set to 1, enables aging function for the read channel of the port. +*/ #undef DDRC_PCFGR_1_RD_PORT_AGING_EN_DEFVAL #undef DDRC_PCFGR_1_RD_PORT_AGING_EN_SHIFT #undef DDRC_PCFGR_1_RD_PORT_AGING_EN_MASK -#define DDRC_PCFGR_1_RD_PORT_AGING_EN_DEFVAL 0x00000000 -#define DDRC_PCFGR_1_RD_PORT_AGING_EN_SHIFT 12 -#define DDRC_PCFGR_1_RD_PORT_AGING_EN_MASK 0x00001000U +#define DDRC_PCFGR_1_RD_PORT_AGING_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_1_RD_PORT_AGING_EN_SHIFT 12 +#define DDRC_PCFGR_1_RD_PORT_AGING_EN_MASK 0x00001000U -/*Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g - ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority - will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre - ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the - aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st - ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w - ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D - RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: - he two LSBs of this register field are tied internally to 2'b00.*/ +/* +* Determines the initial load value of read aging counters. These counters + * will be parallel loaded after reset, or after each grant to the corresp + * onding port. The aging counters down-count every clock cycle where the p + * ort is requesting but not granted. The higher significant 5-bits of the + * read aging counter sets the priority of the read channel of a given port + * . Port's priority will increase as the higher significant 5-bits of the + * counter starts to decrease. When the aging counter becomes 0, the corres + * ponding port channel will have the highest priority level (timeout condi + * tion - Priority0). For multi-port configurations, the aging counters can + * not be used to set port priorities when external dynamic priority inputs + * (arqos) are enabled (timeout is still applicable). For single port conf + * igurations, the aging counters are only used when they timeout (become 0 + * ) to force read-write direction switching. In this case, external dynami + * c priority input, arqos (for reads only) can still be used to set the DD + * RC read priority (2 priority levels: low priority read - LPR, high prior + * ity read - HPR) on a command by command basis. Note: The two LSBs of thi + * s register field are tied internally to 2'b00. +*/ #undef DDRC_PCFGR_1_RD_PORT_PRIORITY_DEFVAL #undef DDRC_PCFGR_1_RD_PORT_PRIORITY_SHIFT #undef DDRC_PCFGR_1_RD_PORT_PRIORITY_MASK -#define DDRC_PCFGR_1_RD_PORT_PRIORITY_DEFVAL 0x00000000 -#define DDRC_PCFGR_1_RD_PORT_PRIORITY_SHIFT 0 -#define DDRC_PCFGR_1_RD_PORT_PRIORITY_MASK 0x000003FFU +#define DDRC_PCFGR_1_RD_PORT_PRIORITY_DEFVAL 0x00000000 +#define DDRC_PCFGR_1_RD_PORT_PRIORITY_SHIFT 0 +#define DDRC_PCFGR_1_RD_PORT_PRIORITY_MASK 0x000003FFU -/*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register.*/ +/* +* If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. +*/ #undef DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_DEFVAL #undef DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_SHIFT #undef DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_MASK -#define DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_DEFVAL 0x00004000 -#define DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_SHIFT 14 -#define DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_MASK 0x00004000U +#define DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_SHIFT 14 +#define DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_MASK 0x00004000U -/*If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register - Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is - not associated with any particular command).*/ +/* +* If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + * bled and awurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + * serted anytime and as long as required which is independent of address h + * andshaking (it is not associated with any particular command). +*/ #undef DDRC_PCFGW_1_WR_PORT_URGENT_EN_DEFVAL #undef DDRC_PCFGW_1_WR_PORT_URGENT_EN_SHIFT #undef DDRC_PCFGW_1_WR_PORT_URGENT_EN_MASK -#define DDRC_PCFGW_1_WR_PORT_URGENT_EN_DEFVAL 0x00004000 -#define DDRC_PCFGW_1_WR_PORT_URGENT_EN_SHIFT 13 -#define DDRC_PCFGW_1_WR_PORT_URGENT_EN_MASK 0x00002000U +#define DDRC_PCFGW_1_WR_PORT_URGENT_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_1_WR_PORT_URGENT_EN_SHIFT 13 +#define DDRC_PCFGW_1_WR_PORT_URGENT_EN_MASK 0x00002000U -/*If set to 1, enables aging function for the write channel of the port.*/ +/* +* If set to 1, enables aging function for the write channel of the port. +*/ #undef DDRC_PCFGW_1_WR_PORT_AGING_EN_DEFVAL #undef DDRC_PCFGW_1_WR_PORT_AGING_EN_SHIFT #undef DDRC_PCFGW_1_WR_PORT_AGING_EN_MASK -#define DDRC_PCFGW_1_WR_PORT_AGING_EN_DEFVAL 0x00004000 -#define DDRC_PCFGW_1_WR_PORT_AGING_EN_SHIFT 12 -#define DDRC_PCFGW_1_WR_PORT_AGING_EN_MASK 0x00001000U +#define DDRC_PCFGW_1_WR_PORT_AGING_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_1_WR_PORT_AGING_EN_SHIFT 12 +#define DDRC_PCFGW_1_WR_PORT_AGING_EN_MASK 0x00001000U -/*Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each - rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port - s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0 - the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno - be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For - ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch - ng. Note: The two LSBs of this register field are tied internally to 2'b00.*/ +/* +* Determines the initial load value of write aging counters. These counter + * s will be parallel loaded after reset, or after each grant to the corres + * ponding port. The aging counters down-count every clock cycle where the + * port is requesting but not granted. The higher significant 5-bits of the + * write aging counter sets the initial priority of the write channel of a + * given port. Port's priority will increase as the higher significant 5-b + * its of the counter starts to decrease. When the aging counter becomes 0, + * the corresponding port channel will have the highest priority level. Fo + * r multi-port configurations, the aging counters cannot be used to set po + * rt priorities when external dynamic priority inputs (awqos) are enabled + * (timeout is still applicable). For single port configurations, the aging + * counters are only used when they timeout (become 0) to force read-write + * direction switching. Note: The two LSBs of this register field are tied + * internally to 2'b00. +*/ #undef DDRC_PCFGW_1_WR_PORT_PRIORITY_DEFVAL #undef DDRC_PCFGW_1_WR_PORT_PRIORITY_SHIFT #undef DDRC_PCFGW_1_WR_PORT_PRIORITY_MASK -#define DDRC_PCFGW_1_WR_PORT_PRIORITY_DEFVAL 0x00004000 -#define DDRC_PCFGW_1_WR_PORT_PRIORITY_SHIFT 0 -#define DDRC_PCFGW_1_WR_PORT_PRIORITY_MASK 0x000003FFU +#define DDRC_PCFGW_1_WR_PORT_PRIORITY_DEFVAL 0x00004000 +#define DDRC_PCFGW_1_WR_PORT_PRIORITY_SHIFT 0 +#define DDRC_PCFGW_1_WR_PORT_PRIORITY_MASK 0x000003FFU -/*Enables port n.*/ +/* +* Enables port n. +*/ #undef DDRC_PCTRL_1_PORT_EN_DEFVAL #undef DDRC_PCTRL_1_PORT_EN_SHIFT #undef DDRC_PCTRL_1_PORT_EN_MASK -#define DDRC_PCTRL_1_PORT_EN_DEFVAL -#define DDRC_PCTRL_1_PORT_EN_SHIFT 0 -#define DDRC_PCTRL_1_PORT_EN_MASK 0x00000001U +#define DDRC_PCTRL_1_PORT_EN_DEFVAL +#define DDRC_PCTRL_1_PORT_EN_SHIFT 0 +#define DDRC_PCTRL_1_PORT_EN_MASK 0x00000001U -/*This bitfield indicates the traffic class of region2. For dual address queue configurations, region2 maps to the red address - ueue. Valid values are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and traffic class of region2 - s set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/ +/* +* This bitfield indicates the traffic class of region2. For dual address q + * ueue configurations, region2 maps to the red address queue. Valid values + * are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN + * = 0) and traffic class of region2 is set to 1 (VPR), VPR traffic is ali + * ased to LPR traffic. +*/ #undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_DEFVAL #undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_SHIFT #undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_MASK -#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_DEFVAL 0x02000E00 -#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_SHIFT 24 -#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_MASK 0x03000000U +#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_DEFVAL 0x02000E00 +#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_SHIFT 24 +#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_MASK 0x03000000U -/*This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf - gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is - disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/ +/* +* This bitfield indicates the traffic class of region 1. Valid values are: + * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + * maps to the blue address queue. In this case, valid values are 0: LPR a + * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. +*/ #undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_DEFVAL #undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_SHIFT #undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_MASK -#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_DEFVAL 0x02000E00 -#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_SHIFT 20 -#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_MASK 0x00300000U +#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_DEFVAL 0x02000E00 +#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_SHIFT 20 +#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_MASK 0x00300000U -/*This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi - urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i - disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/ +/* +* This bitfield indicates the traffic class of region 0. Valid values are: + * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + * maps to the blue address queue. In this case, valid values are: 0: LPR + * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. +*/ #undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_DEFVAL #undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_SHIFT #undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_MASK -#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_DEFVAL 0x02000E00 -#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_SHIFT 16 -#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_MASK 0x00030000U +#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_DEFVAL 0x02000E00 +#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_SHIFT 16 +#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_MASK 0x00030000U -/*Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (le - el1 + 1) to 14 which corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note that for PA, arqos values are used - directly as port priorities, where the higher the value corresponds to higher port priority. All of the map_level* registers - ust be set to distinct values.*/ +/* +* Separation level2 indicating the end of region1 mapping; start of region + * 1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 whi + * ch corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note + * that for PA, arqos values are used directly as port priorities, where t + * he higher the value corresponds to higher port priority. All of the map_ + * level* registers must be set to distinct values. +*/ #undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_DEFVAL #undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_SHIFT #undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_MASK -#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_DEFVAL 0x02000E00 -#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_SHIFT 8 -#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_MASK 0x00000F00U +#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_DEFVAL 0x02000E00 +#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_SHIFT 8 +#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_MASK 0x00000F00U -/*Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d - al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio - ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc - values.*/ +/* +* Separation level1 indicating the end of region0 mapping; start of region + * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + * lues are used directly as port priorities, where the higher the value co + * rresponds to higher port priority. All of the map_level* registers must + * be set to distinct values. +*/ #undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_DEFVAL #undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_SHIFT #undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_MASK -#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_DEFVAL 0x02000E00 -#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_SHIFT 0 -#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_MASK 0x0000000FU +#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_DEFVAL 0x02000E00 +#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_SHIFT 0 +#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_MASK 0x0000000FU -/*Specifies the timeout value for transactions mapped to the red address queue.*/ +/* +* Specifies the timeout value for transactions mapped to the red address q + * ueue. +*/ #undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_DEFVAL #undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_SHIFT #undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_MASK -#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_DEFVAL 0x00000000 -#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_SHIFT 16 -#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_MASK 0x07FF0000U +#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_DEFVAL 0x00000000 +#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_SHIFT 16 +#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_MASK 0x07FF0000U -/*Specifies the timeout value for transactions mapped to the blue address queue.*/ +/* +* Specifies the timeout value for transactions mapped to the blue address + * queue. +*/ #undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_DEFVAL #undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_SHIFT #undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_MASK -#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_DEFVAL 0x00000000 -#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_SHIFT 0 -#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_MASK 0x000007FFU +#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_DEFVAL 0x00000000 +#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_SHIFT 0 +#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_MASK 0x000007FFU -/*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register.*/ +/* +* If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. +*/ #undef DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_DEFVAL #undef DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_SHIFT #undef DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_MASK -#define DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_DEFVAL 0x00000000 -#define DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_SHIFT 14 -#define DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_MASK 0x00004000U +#define DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_SHIFT 14 +#define DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_MASK 0x00004000U -/*If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG. - o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add - ess handshaking (it is not associated with any particular command).*/ +/* +* If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + * bled and arurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + * urgent signal can be asserted anytime and as long as required which is i + * ndependent of address handshaking (it is not associated with any particu + * lar command). +*/ #undef DDRC_PCFGR_2_RD_PORT_URGENT_EN_DEFVAL #undef DDRC_PCFGR_2_RD_PORT_URGENT_EN_SHIFT #undef DDRC_PCFGR_2_RD_PORT_URGENT_EN_MASK -#define DDRC_PCFGR_2_RD_PORT_URGENT_EN_DEFVAL 0x00000000 -#define DDRC_PCFGR_2_RD_PORT_URGENT_EN_SHIFT 13 -#define DDRC_PCFGR_2_RD_PORT_URGENT_EN_MASK 0x00002000U +#define DDRC_PCFGR_2_RD_PORT_URGENT_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_2_RD_PORT_URGENT_EN_SHIFT 13 +#define DDRC_PCFGR_2_RD_PORT_URGENT_EN_MASK 0x00002000U -/*If set to 1, enables aging function for the read channel of the port.*/ +/* +* If set to 1, enables aging function for the read channel of the port. +*/ #undef DDRC_PCFGR_2_RD_PORT_AGING_EN_DEFVAL #undef DDRC_PCFGR_2_RD_PORT_AGING_EN_SHIFT #undef DDRC_PCFGR_2_RD_PORT_AGING_EN_MASK -#define DDRC_PCFGR_2_RD_PORT_AGING_EN_DEFVAL 0x00000000 -#define DDRC_PCFGR_2_RD_PORT_AGING_EN_SHIFT 12 -#define DDRC_PCFGR_2_RD_PORT_AGING_EN_MASK 0x00001000U +#define DDRC_PCFGR_2_RD_PORT_AGING_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_2_RD_PORT_AGING_EN_SHIFT 12 +#define DDRC_PCFGR_2_RD_PORT_AGING_EN_MASK 0x00001000U -/*Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g - ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority - will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre - ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the - aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st - ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w - ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D - RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: - he two LSBs of this register field are tied internally to 2'b00.*/ +/* +* Determines the initial load value of read aging counters. These counters + * will be parallel loaded after reset, or after each grant to the corresp + * onding port. The aging counters down-count every clock cycle where the p + * ort is requesting but not granted. The higher significant 5-bits of the + * read aging counter sets the priority of the read channel of a given port + * . Port's priority will increase as the higher significant 5-bits of the + * counter starts to decrease. When the aging counter becomes 0, the corres + * ponding port channel will have the highest priority level (timeout condi + * tion - Priority0). For multi-port configurations, the aging counters can + * not be used to set port priorities when external dynamic priority inputs + * (arqos) are enabled (timeout is still applicable). For single port conf + * igurations, the aging counters are only used when they timeout (become 0 + * ) to force read-write direction switching. In this case, external dynami + * c priority input, arqos (for reads only) can still be used to set the DD + * RC read priority (2 priority levels: low priority read - LPR, high prior + * ity read - HPR) on a command by command basis. Note: The two LSBs of thi + * s register field are tied internally to 2'b00. +*/ #undef DDRC_PCFGR_2_RD_PORT_PRIORITY_DEFVAL #undef DDRC_PCFGR_2_RD_PORT_PRIORITY_SHIFT #undef DDRC_PCFGR_2_RD_PORT_PRIORITY_MASK -#define DDRC_PCFGR_2_RD_PORT_PRIORITY_DEFVAL 0x00000000 -#define DDRC_PCFGR_2_RD_PORT_PRIORITY_SHIFT 0 -#define DDRC_PCFGR_2_RD_PORT_PRIORITY_MASK 0x000003FFU +#define DDRC_PCFGR_2_RD_PORT_PRIORITY_DEFVAL 0x00000000 +#define DDRC_PCFGR_2_RD_PORT_PRIORITY_SHIFT 0 +#define DDRC_PCFGR_2_RD_PORT_PRIORITY_MASK 0x000003FFU -/*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register.*/ +/* +* If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. +*/ #undef DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_DEFVAL #undef DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_SHIFT #undef DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_MASK -#define DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_DEFVAL 0x00004000 -#define DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_SHIFT 14 -#define DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_MASK 0x00004000U +#define DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_SHIFT 14 +#define DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_MASK 0x00004000U -/*If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register - Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is - not associated with any particular command).*/ +/* +* If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + * bled and awurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + * serted anytime and as long as required which is independent of address h + * andshaking (it is not associated with any particular command). +*/ #undef DDRC_PCFGW_2_WR_PORT_URGENT_EN_DEFVAL #undef DDRC_PCFGW_2_WR_PORT_URGENT_EN_SHIFT #undef DDRC_PCFGW_2_WR_PORT_URGENT_EN_MASK -#define DDRC_PCFGW_2_WR_PORT_URGENT_EN_DEFVAL 0x00004000 -#define DDRC_PCFGW_2_WR_PORT_URGENT_EN_SHIFT 13 -#define DDRC_PCFGW_2_WR_PORT_URGENT_EN_MASK 0x00002000U +#define DDRC_PCFGW_2_WR_PORT_URGENT_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_2_WR_PORT_URGENT_EN_SHIFT 13 +#define DDRC_PCFGW_2_WR_PORT_URGENT_EN_MASK 0x00002000U -/*If set to 1, enables aging function for the write channel of the port.*/ +/* +* If set to 1, enables aging function for the write channel of the port. +*/ #undef DDRC_PCFGW_2_WR_PORT_AGING_EN_DEFVAL #undef DDRC_PCFGW_2_WR_PORT_AGING_EN_SHIFT #undef DDRC_PCFGW_2_WR_PORT_AGING_EN_MASK -#define DDRC_PCFGW_2_WR_PORT_AGING_EN_DEFVAL 0x00004000 -#define DDRC_PCFGW_2_WR_PORT_AGING_EN_SHIFT 12 -#define DDRC_PCFGW_2_WR_PORT_AGING_EN_MASK 0x00001000U +#define DDRC_PCFGW_2_WR_PORT_AGING_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_2_WR_PORT_AGING_EN_SHIFT 12 +#define DDRC_PCFGW_2_WR_PORT_AGING_EN_MASK 0x00001000U -/*Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each - rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port - s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0 - the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno - be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For - ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch - ng. Note: The two LSBs of this register field are tied internally to 2'b00.*/ +/* +* Determines the initial load value of write aging counters. These counter + * s will be parallel loaded after reset, or after each grant to the corres + * ponding port. The aging counters down-count every clock cycle where the + * port is requesting but not granted. The higher significant 5-bits of the + * write aging counter sets the initial priority of the write channel of a + * given port. Port's priority will increase as the higher significant 5-b + * its of the counter starts to decrease. When the aging counter becomes 0, + * the corresponding port channel will have the highest priority level. Fo + * r multi-port configurations, the aging counters cannot be used to set po + * rt priorities when external dynamic priority inputs (awqos) are enabled + * (timeout is still applicable). For single port configurations, the aging + * counters are only used when they timeout (become 0) to force read-write + * direction switching. Note: The two LSBs of this register field are tied + * internally to 2'b00. +*/ #undef DDRC_PCFGW_2_WR_PORT_PRIORITY_DEFVAL #undef DDRC_PCFGW_2_WR_PORT_PRIORITY_SHIFT #undef DDRC_PCFGW_2_WR_PORT_PRIORITY_MASK -#define DDRC_PCFGW_2_WR_PORT_PRIORITY_DEFVAL 0x00004000 -#define DDRC_PCFGW_2_WR_PORT_PRIORITY_SHIFT 0 -#define DDRC_PCFGW_2_WR_PORT_PRIORITY_MASK 0x000003FFU +#define DDRC_PCFGW_2_WR_PORT_PRIORITY_DEFVAL 0x00004000 +#define DDRC_PCFGW_2_WR_PORT_PRIORITY_SHIFT 0 +#define DDRC_PCFGW_2_WR_PORT_PRIORITY_MASK 0x000003FFU -/*Enables port n.*/ +/* +* Enables port n. +*/ #undef DDRC_PCTRL_2_PORT_EN_DEFVAL #undef DDRC_PCTRL_2_PORT_EN_SHIFT #undef DDRC_PCTRL_2_PORT_EN_MASK -#define DDRC_PCTRL_2_PORT_EN_DEFVAL -#define DDRC_PCTRL_2_PORT_EN_SHIFT 0 -#define DDRC_PCTRL_2_PORT_EN_MASK 0x00000001U +#define DDRC_PCTRL_2_PORT_EN_DEFVAL +#define DDRC_PCTRL_2_PORT_EN_SHIFT 0 +#define DDRC_PCTRL_2_PORT_EN_MASK 0x00000001U -/*This bitfield indicates the traffic class of region2. For dual address queue configurations, region2 maps to the red address - ueue. Valid values are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and traffic class of region2 - s set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/ +/* +* This bitfield indicates the traffic class of region2. For dual address q + * ueue configurations, region2 maps to the red address queue. Valid values + * are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN + * = 0) and traffic class of region2 is set to 1 (VPR), VPR traffic is ali + * ased to LPR traffic. +*/ #undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_DEFVAL #undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_SHIFT #undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_MASK -#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_DEFVAL 0x02000E00 -#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_SHIFT 24 -#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_MASK 0x03000000U +#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_DEFVAL 0x02000E00 +#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_SHIFT 24 +#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_MASK 0x03000000U -/*This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf - gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is - disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/ +/* +* This bitfield indicates the traffic class of region 1. Valid values are: + * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + * maps to the blue address queue. In this case, valid values are 0: LPR a + * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. +*/ #undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_DEFVAL #undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_SHIFT #undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_MASK -#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_DEFVAL 0x02000E00 -#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_SHIFT 20 -#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_MASK 0x00300000U +#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_DEFVAL 0x02000E00 +#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_SHIFT 20 +#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_MASK 0x00300000U -/*This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi - urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i - disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/ +/* +* This bitfield indicates the traffic class of region 0. Valid values are: + * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + * maps to the blue address queue. In this case, valid values are: 0: LPR + * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. +*/ #undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_DEFVAL #undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_SHIFT #undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_MASK -#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_DEFVAL 0x02000E00 -#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_SHIFT 16 -#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_MASK 0x00030000U +#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_DEFVAL 0x02000E00 +#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_SHIFT 16 +#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_MASK 0x00030000U -/*Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (le - el1 + 1) to 14 which corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note that for PA, arqos values are used - directly as port priorities, where the higher the value corresponds to higher port priority. All of the map_level* registers - ust be set to distinct values.*/ +/* +* Separation level2 indicating the end of region1 mapping; start of region + * 1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 whi + * ch corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note + * that for PA, arqos values are used directly as port priorities, where t + * he higher the value corresponds to higher port priority. All of the map_ + * level* registers must be set to distinct values. +*/ #undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_DEFVAL #undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_SHIFT #undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_MASK -#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_DEFVAL 0x02000E00 -#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_SHIFT 8 -#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_MASK 0x00000F00U +#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_DEFVAL 0x02000E00 +#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_SHIFT 8 +#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_MASK 0x00000F00U -/*Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d - al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio - ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc - values.*/ +/* +* Separation level1 indicating the end of region0 mapping; start of region + * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + * lues are used directly as port priorities, where the higher the value co + * rresponds to higher port priority. All of the map_level* registers must + * be set to distinct values. +*/ #undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_DEFVAL #undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_SHIFT #undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_MASK -#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_DEFVAL 0x02000E00 -#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_SHIFT 0 -#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_MASK 0x0000000FU +#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_DEFVAL 0x02000E00 +#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_SHIFT 0 +#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_MASK 0x0000000FU -/*Specifies the timeout value for transactions mapped to the red address queue.*/ +/* +* Specifies the timeout value for transactions mapped to the red address q + * ueue. +*/ #undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_DEFVAL #undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_SHIFT #undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_MASK -#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_DEFVAL 0x00000000 -#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_SHIFT 16 -#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_MASK 0x07FF0000U +#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_DEFVAL 0x00000000 +#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_SHIFT 16 +#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_MASK 0x07FF0000U -/*Specifies the timeout value for transactions mapped to the blue address queue.*/ +/* +* Specifies the timeout value for transactions mapped to the blue address + * queue. +*/ #undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_DEFVAL #undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_SHIFT #undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_MASK -#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_DEFVAL 0x00000000 -#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_SHIFT 0 -#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_MASK 0x000007FFU +#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_DEFVAL 0x00000000 +#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_SHIFT 0 +#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_MASK 0x000007FFU -/*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register.*/ +/* +* If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. +*/ #undef DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_DEFVAL #undef DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_SHIFT #undef DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_MASK -#define DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_DEFVAL 0x00000000 -#define DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_SHIFT 14 -#define DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_MASK 0x00004000U +#define DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_SHIFT 14 +#define DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_MASK 0x00004000U -/*If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG. - o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add - ess handshaking (it is not associated with any particular command).*/ +/* +* If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + * bled and arurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + * urgent signal can be asserted anytime and as long as required which is i + * ndependent of address handshaking (it is not associated with any particu + * lar command). +*/ #undef DDRC_PCFGR_3_RD_PORT_URGENT_EN_DEFVAL #undef DDRC_PCFGR_3_RD_PORT_URGENT_EN_SHIFT #undef DDRC_PCFGR_3_RD_PORT_URGENT_EN_MASK -#define DDRC_PCFGR_3_RD_PORT_URGENT_EN_DEFVAL 0x00000000 -#define DDRC_PCFGR_3_RD_PORT_URGENT_EN_SHIFT 13 -#define DDRC_PCFGR_3_RD_PORT_URGENT_EN_MASK 0x00002000U +#define DDRC_PCFGR_3_RD_PORT_URGENT_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_3_RD_PORT_URGENT_EN_SHIFT 13 +#define DDRC_PCFGR_3_RD_PORT_URGENT_EN_MASK 0x00002000U -/*If set to 1, enables aging function for the read channel of the port.*/ +/* +* If set to 1, enables aging function for the read channel of the port. +*/ #undef DDRC_PCFGR_3_RD_PORT_AGING_EN_DEFVAL #undef DDRC_PCFGR_3_RD_PORT_AGING_EN_SHIFT #undef DDRC_PCFGR_3_RD_PORT_AGING_EN_MASK -#define DDRC_PCFGR_3_RD_PORT_AGING_EN_DEFVAL 0x00000000 -#define DDRC_PCFGR_3_RD_PORT_AGING_EN_SHIFT 12 -#define DDRC_PCFGR_3_RD_PORT_AGING_EN_MASK 0x00001000U +#define DDRC_PCFGR_3_RD_PORT_AGING_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_3_RD_PORT_AGING_EN_SHIFT 12 +#define DDRC_PCFGR_3_RD_PORT_AGING_EN_MASK 0x00001000U -/*Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g - ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority - will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre - ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the - aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st - ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w - ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D - RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: - he two LSBs of this register field are tied internally to 2'b00.*/ +/* +* Determines the initial load value of read aging counters. These counters + * will be parallel loaded after reset, or after each grant to the corresp + * onding port. The aging counters down-count every clock cycle where the p + * ort is requesting but not granted. The higher significant 5-bits of the + * read aging counter sets the priority of the read channel of a given port + * . Port's priority will increase as the higher significant 5-bits of the + * counter starts to decrease. When the aging counter becomes 0, the corres + * ponding port channel will have the highest priority level (timeout condi + * tion - Priority0). For multi-port configurations, the aging counters can + * not be used to set port priorities when external dynamic priority inputs + * (arqos) are enabled (timeout is still applicable). For single port conf + * igurations, the aging counters are only used when they timeout (become 0 + * ) to force read-write direction switching. In this case, external dynami + * c priority input, arqos (for reads only) can still be used to set the DD + * RC read priority (2 priority levels: low priority read - LPR, high prior + * ity read - HPR) on a command by command basis. Note: The two LSBs of thi + * s register field are tied internally to 2'b00. +*/ #undef DDRC_PCFGR_3_RD_PORT_PRIORITY_DEFVAL #undef DDRC_PCFGR_3_RD_PORT_PRIORITY_SHIFT #undef DDRC_PCFGR_3_RD_PORT_PRIORITY_MASK -#define DDRC_PCFGR_3_RD_PORT_PRIORITY_DEFVAL 0x00000000 -#define DDRC_PCFGR_3_RD_PORT_PRIORITY_SHIFT 0 -#define DDRC_PCFGR_3_RD_PORT_PRIORITY_MASK 0x000003FFU +#define DDRC_PCFGR_3_RD_PORT_PRIORITY_DEFVAL 0x00000000 +#define DDRC_PCFGR_3_RD_PORT_PRIORITY_SHIFT 0 +#define DDRC_PCFGR_3_RD_PORT_PRIORITY_MASK 0x000003FFU -/*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register.*/ +/* +* If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. +*/ #undef DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_DEFVAL #undef DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_SHIFT #undef DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_MASK -#define DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_DEFVAL 0x00004000 -#define DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_SHIFT 14 -#define DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_MASK 0x00004000U +#define DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_SHIFT 14 +#define DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_MASK 0x00004000U -/*If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register - Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is - not associated with any particular command).*/ +/* +* If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + * bled and awurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + * serted anytime and as long as required which is independent of address h + * andshaking (it is not associated with any particular command). +*/ #undef DDRC_PCFGW_3_WR_PORT_URGENT_EN_DEFVAL #undef DDRC_PCFGW_3_WR_PORT_URGENT_EN_SHIFT #undef DDRC_PCFGW_3_WR_PORT_URGENT_EN_MASK -#define DDRC_PCFGW_3_WR_PORT_URGENT_EN_DEFVAL 0x00004000 -#define DDRC_PCFGW_3_WR_PORT_URGENT_EN_SHIFT 13 -#define DDRC_PCFGW_3_WR_PORT_URGENT_EN_MASK 0x00002000U +#define DDRC_PCFGW_3_WR_PORT_URGENT_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_3_WR_PORT_URGENT_EN_SHIFT 13 +#define DDRC_PCFGW_3_WR_PORT_URGENT_EN_MASK 0x00002000U -/*If set to 1, enables aging function for the write channel of the port.*/ +/* +* If set to 1, enables aging function for the write channel of the port. +*/ #undef DDRC_PCFGW_3_WR_PORT_AGING_EN_DEFVAL #undef DDRC_PCFGW_3_WR_PORT_AGING_EN_SHIFT #undef DDRC_PCFGW_3_WR_PORT_AGING_EN_MASK -#define DDRC_PCFGW_3_WR_PORT_AGING_EN_DEFVAL 0x00004000 -#define DDRC_PCFGW_3_WR_PORT_AGING_EN_SHIFT 12 -#define DDRC_PCFGW_3_WR_PORT_AGING_EN_MASK 0x00001000U +#define DDRC_PCFGW_3_WR_PORT_AGING_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_3_WR_PORT_AGING_EN_SHIFT 12 +#define DDRC_PCFGW_3_WR_PORT_AGING_EN_MASK 0x00001000U -/*Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each - rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port - s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0 - the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno - be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For - ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch - ng. Note: The two LSBs of this register field are tied internally to 2'b00.*/ +/* +* Determines the initial load value of write aging counters. These counter + * s will be parallel loaded after reset, or after each grant to the corres + * ponding port. The aging counters down-count every clock cycle where the + * port is requesting but not granted. The higher significant 5-bits of the + * write aging counter sets the initial priority of the write channel of a + * given port. Port's priority will increase as the higher significant 5-b + * its of the counter starts to decrease. When the aging counter becomes 0, + * the corresponding port channel will have the highest priority level. Fo + * r multi-port configurations, the aging counters cannot be used to set po + * rt priorities when external dynamic priority inputs (awqos) are enabled + * (timeout is still applicable). For single port configurations, the aging + * counters are only used when they timeout (become 0) to force read-write + * direction switching. Note: The two LSBs of this register field are tied + * internally to 2'b00. +*/ #undef DDRC_PCFGW_3_WR_PORT_PRIORITY_DEFVAL #undef DDRC_PCFGW_3_WR_PORT_PRIORITY_SHIFT #undef DDRC_PCFGW_3_WR_PORT_PRIORITY_MASK -#define DDRC_PCFGW_3_WR_PORT_PRIORITY_DEFVAL 0x00004000 -#define DDRC_PCFGW_3_WR_PORT_PRIORITY_SHIFT 0 -#define DDRC_PCFGW_3_WR_PORT_PRIORITY_MASK 0x000003FFU +#define DDRC_PCFGW_3_WR_PORT_PRIORITY_DEFVAL 0x00004000 +#define DDRC_PCFGW_3_WR_PORT_PRIORITY_SHIFT 0 +#define DDRC_PCFGW_3_WR_PORT_PRIORITY_MASK 0x000003FFU -/*Enables port n.*/ +/* +* Enables port n. +*/ #undef DDRC_PCTRL_3_PORT_EN_DEFVAL #undef DDRC_PCTRL_3_PORT_EN_SHIFT #undef DDRC_PCTRL_3_PORT_EN_MASK -#define DDRC_PCTRL_3_PORT_EN_DEFVAL -#define DDRC_PCTRL_3_PORT_EN_SHIFT 0 -#define DDRC_PCTRL_3_PORT_EN_MASK 0x00000001U +#define DDRC_PCTRL_3_PORT_EN_DEFVAL +#define DDRC_PCTRL_3_PORT_EN_SHIFT 0 +#define DDRC_PCTRL_3_PORT_EN_MASK 0x00000001U -/*This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf - gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is - disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/ +/* +* This bitfield indicates the traffic class of region 1. Valid values are: + * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + * maps to the blue address queue. In this case, valid values are 0: LPR a + * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. +*/ #undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_DEFVAL #undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_SHIFT #undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_MASK -#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_DEFVAL 0x00000000 -#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_SHIFT 20 -#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_MASK 0x00300000U +#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_DEFVAL 0x00000000 +#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_SHIFT 20 +#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_MASK 0x00300000U -/*This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi - urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i - disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/ +/* +* This bitfield indicates the traffic class of region 0. Valid values are: + * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + * maps to the blue address queue. In this case, valid values are: 0: LPR + * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. +*/ #undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_DEFVAL #undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_SHIFT #undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_MASK -#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_DEFVAL 0x00000000 -#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_SHIFT 16 -#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_MASK 0x00030000U +#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_DEFVAL 0x00000000 +#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_SHIFT 16 +#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_MASK 0x00030000U -/*Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d - al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio - ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc - values.*/ +/* +* Separation level1 indicating the end of region0 mapping; start of region + * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + * lues are used directly as port priorities, where the higher the value co + * rresponds to higher port priority. All of the map_level* registers must + * be set to distinct values. +*/ #undef DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_DEFVAL #undef DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_SHIFT #undef DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_MASK -#define DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_DEFVAL 0x00000000 -#define DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_SHIFT 0 -#define DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_MASK 0x0000000FU +#define DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_DEFVAL 0x00000000 +#define DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_SHIFT 0 +#define DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_MASK 0x0000000FU -/*Specifies the timeout value for transactions mapped to the red address queue.*/ +/* +* Specifies the timeout value for transactions mapped to the red address q + * ueue. +*/ #undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_DEFVAL #undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_SHIFT #undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_MASK -#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_DEFVAL 0x00000000 -#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_SHIFT 16 -#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_MASK 0x07FF0000U +#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_DEFVAL 0x00000000 +#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_SHIFT 16 +#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_MASK 0x07FF0000U -/*Specifies the timeout value for transactions mapped to the blue address queue.*/ +/* +* Specifies the timeout value for transactions mapped to the blue address + * queue. +*/ #undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_DEFVAL #undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_SHIFT #undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_MASK -#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_DEFVAL 0x00000000 -#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_SHIFT 0 -#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_MASK 0x000007FFU +#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_DEFVAL 0x00000000 +#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_SHIFT 0 +#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_MASK 0x000007FFU -/*This bitfield indicates the traffic class of region 1. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2 - VPW_EN = 0) and traffic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW traffic.*/ +/* +* This bitfield indicates the traffic class of region 1. Valid values are: + * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + * affic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW + * traffic. +*/ #undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_DEFVAL #undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_SHIFT #undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_MASK -#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_DEFVAL 0x00000000 -#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_SHIFT 20 -#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_MASK 0x00300000U +#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_DEFVAL 0x00000000 +#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_SHIFT 20 +#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_MASK 0x00300000U -/*This bitfield indicates the traffic class of region 0. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2 - VPW_EN = 0) and traffic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW traffic.*/ +/* +* This bitfield indicates the traffic class of region 0. Valid values are: + * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + * affic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW + * traffic. +*/ #undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_DEFVAL #undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_SHIFT #undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_MASK -#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_DEFVAL 0x00000000 -#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_SHIFT 16 -#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_MASK 0x00030000U +#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_DEFVAL 0x00000000 +#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_SHIFT 16 +#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_MASK 0x00030000U -/*Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 14 which c - rresponds to awqos. Note that for PA, awqos values are used directly as port priorities, where the higher the value correspon - s to higher port priority.*/ +/* +* Separation level indicating the end of region0 mapping; start of region0 + * is 0. Possible values for level1 are 0 to 14 which corresponds to awqos + * . Note that for PA, awqos values are used directly as port priorities, w + * here the higher the value corresponds to higher port priority. +*/ #undef DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_DEFVAL #undef DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_SHIFT #undef DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_MASK -#define DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_DEFVAL 0x00000000 -#define DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_SHIFT 0 -#define DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_MASK 0x0000000FU +#define DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_DEFVAL 0x00000000 +#define DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_SHIFT 0 +#define DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_MASK 0x0000000FU -/*Specifies the timeout value for write transactions.*/ +/* +* Specifies the timeout value for write transactions. +*/ #undef DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_DEFVAL #undef DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_SHIFT #undef DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_MASK -#define DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_DEFVAL -#define DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_SHIFT 0 -#define DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_MASK 0x000007FFU +#define DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_DEFVAL +#define DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_SHIFT 0 +#define DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_MASK 0x000007FFU -/*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register.*/ +/* +* If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. +*/ #undef DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_DEFVAL #undef DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_SHIFT #undef DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_MASK -#define DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_DEFVAL 0x00000000 -#define DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_SHIFT 14 -#define DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_MASK 0x00004000U +#define DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_SHIFT 14 +#define DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_MASK 0x00004000U -/*If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG. - o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add - ess handshaking (it is not associated with any particular command).*/ +/* +* If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + * bled and arurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + * urgent signal can be asserted anytime and as long as required which is i + * ndependent of address handshaking (it is not associated with any particu + * lar command). +*/ #undef DDRC_PCFGR_4_RD_PORT_URGENT_EN_DEFVAL #undef DDRC_PCFGR_4_RD_PORT_URGENT_EN_SHIFT #undef DDRC_PCFGR_4_RD_PORT_URGENT_EN_MASK -#define DDRC_PCFGR_4_RD_PORT_URGENT_EN_DEFVAL 0x00000000 -#define DDRC_PCFGR_4_RD_PORT_URGENT_EN_SHIFT 13 -#define DDRC_PCFGR_4_RD_PORT_URGENT_EN_MASK 0x00002000U +#define DDRC_PCFGR_4_RD_PORT_URGENT_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_4_RD_PORT_URGENT_EN_SHIFT 13 +#define DDRC_PCFGR_4_RD_PORT_URGENT_EN_MASK 0x00002000U -/*If set to 1, enables aging function for the read channel of the port.*/ +/* +* If set to 1, enables aging function for the read channel of the port. +*/ #undef DDRC_PCFGR_4_RD_PORT_AGING_EN_DEFVAL #undef DDRC_PCFGR_4_RD_PORT_AGING_EN_SHIFT #undef DDRC_PCFGR_4_RD_PORT_AGING_EN_MASK -#define DDRC_PCFGR_4_RD_PORT_AGING_EN_DEFVAL 0x00000000 -#define DDRC_PCFGR_4_RD_PORT_AGING_EN_SHIFT 12 -#define DDRC_PCFGR_4_RD_PORT_AGING_EN_MASK 0x00001000U +#define DDRC_PCFGR_4_RD_PORT_AGING_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_4_RD_PORT_AGING_EN_SHIFT 12 +#define DDRC_PCFGR_4_RD_PORT_AGING_EN_MASK 0x00001000U -/*Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g - ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority - will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre - ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the - aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st - ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w - ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D - RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: - he two LSBs of this register field are tied internally to 2'b00.*/ +/* +* Determines the initial load value of read aging counters. These counters + * will be parallel loaded after reset, or after each grant to the corresp + * onding port. The aging counters down-count every clock cycle where the p + * ort is requesting but not granted. The higher significant 5-bits of the + * read aging counter sets the priority of the read channel of a given port + * . Port's priority will increase as the higher significant 5-bits of the + * counter starts to decrease. When the aging counter becomes 0, the corres + * ponding port channel will have the highest priority level (timeout condi + * tion - Priority0). For multi-port configurations, the aging counters can + * not be used to set port priorities when external dynamic priority inputs + * (arqos) are enabled (timeout is still applicable). For single port conf + * igurations, the aging counters are only used when they timeout (become 0 + * ) to force read-write direction switching. In this case, external dynami + * c priority input, arqos (for reads only) can still be used to set the DD + * RC read priority (2 priority levels: low priority read - LPR, high prior + * ity read - HPR) on a command by command basis. Note: The two LSBs of thi + * s register field are tied internally to 2'b00. +*/ #undef DDRC_PCFGR_4_RD_PORT_PRIORITY_DEFVAL #undef DDRC_PCFGR_4_RD_PORT_PRIORITY_SHIFT #undef DDRC_PCFGR_4_RD_PORT_PRIORITY_MASK -#define DDRC_PCFGR_4_RD_PORT_PRIORITY_DEFVAL 0x00000000 -#define DDRC_PCFGR_4_RD_PORT_PRIORITY_SHIFT 0 -#define DDRC_PCFGR_4_RD_PORT_PRIORITY_MASK 0x000003FFU +#define DDRC_PCFGR_4_RD_PORT_PRIORITY_DEFVAL 0x00000000 +#define DDRC_PCFGR_4_RD_PORT_PRIORITY_SHIFT 0 +#define DDRC_PCFGR_4_RD_PORT_PRIORITY_MASK 0x000003FFU -/*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register.*/ +/* +* If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. +*/ #undef DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_DEFVAL #undef DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_SHIFT #undef DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_MASK -#define DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_DEFVAL 0x00004000 -#define DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_SHIFT 14 -#define DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_MASK 0x00004000U +#define DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_SHIFT 14 +#define DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_MASK 0x00004000U -/*If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register - Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is - not associated with any particular command).*/ +/* +* If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + * bled and awurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + * serted anytime and as long as required which is independent of address h + * andshaking (it is not associated with any particular command). +*/ #undef DDRC_PCFGW_4_WR_PORT_URGENT_EN_DEFVAL #undef DDRC_PCFGW_4_WR_PORT_URGENT_EN_SHIFT #undef DDRC_PCFGW_4_WR_PORT_URGENT_EN_MASK -#define DDRC_PCFGW_4_WR_PORT_URGENT_EN_DEFVAL 0x00004000 -#define DDRC_PCFGW_4_WR_PORT_URGENT_EN_SHIFT 13 -#define DDRC_PCFGW_4_WR_PORT_URGENT_EN_MASK 0x00002000U +#define DDRC_PCFGW_4_WR_PORT_URGENT_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_4_WR_PORT_URGENT_EN_SHIFT 13 +#define DDRC_PCFGW_4_WR_PORT_URGENT_EN_MASK 0x00002000U -/*If set to 1, enables aging function for the write channel of the port.*/ +/* +* If set to 1, enables aging function for the write channel of the port. +*/ #undef DDRC_PCFGW_4_WR_PORT_AGING_EN_DEFVAL #undef DDRC_PCFGW_4_WR_PORT_AGING_EN_SHIFT #undef DDRC_PCFGW_4_WR_PORT_AGING_EN_MASK -#define DDRC_PCFGW_4_WR_PORT_AGING_EN_DEFVAL 0x00004000 -#define DDRC_PCFGW_4_WR_PORT_AGING_EN_SHIFT 12 -#define DDRC_PCFGW_4_WR_PORT_AGING_EN_MASK 0x00001000U +#define DDRC_PCFGW_4_WR_PORT_AGING_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_4_WR_PORT_AGING_EN_SHIFT 12 +#define DDRC_PCFGW_4_WR_PORT_AGING_EN_MASK 0x00001000U -/*Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each - rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port - s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0 - the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno - be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For - ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch - ng. Note: The two LSBs of this register field are tied internally to 2'b00.*/ +/* +* Determines the initial load value of write aging counters. These counter + * s will be parallel loaded after reset, or after each grant to the corres + * ponding port. The aging counters down-count every clock cycle where the + * port is requesting but not granted. The higher significant 5-bits of the + * write aging counter sets the initial priority of the write channel of a + * given port. Port's priority will increase as the higher significant 5-b + * its of the counter starts to decrease. When the aging counter becomes 0, + * the corresponding port channel will have the highest priority level. Fo + * r multi-port configurations, the aging counters cannot be used to set po + * rt priorities when external dynamic priority inputs (awqos) are enabled + * (timeout is still applicable). For single port configurations, the aging + * counters are only used when they timeout (become 0) to force read-write + * direction switching. Note: The two LSBs of this register field are tied + * internally to 2'b00. +*/ #undef DDRC_PCFGW_4_WR_PORT_PRIORITY_DEFVAL #undef DDRC_PCFGW_4_WR_PORT_PRIORITY_SHIFT #undef DDRC_PCFGW_4_WR_PORT_PRIORITY_MASK -#define DDRC_PCFGW_4_WR_PORT_PRIORITY_DEFVAL 0x00004000 -#define DDRC_PCFGW_4_WR_PORT_PRIORITY_SHIFT 0 -#define DDRC_PCFGW_4_WR_PORT_PRIORITY_MASK 0x000003FFU +#define DDRC_PCFGW_4_WR_PORT_PRIORITY_DEFVAL 0x00004000 +#define DDRC_PCFGW_4_WR_PORT_PRIORITY_SHIFT 0 +#define DDRC_PCFGW_4_WR_PORT_PRIORITY_MASK 0x000003FFU -/*Enables port n.*/ +/* +* Enables port n. +*/ #undef DDRC_PCTRL_4_PORT_EN_DEFVAL #undef DDRC_PCTRL_4_PORT_EN_SHIFT #undef DDRC_PCTRL_4_PORT_EN_MASK -#define DDRC_PCTRL_4_PORT_EN_DEFVAL -#define DDRC_PCTRL_4_PORT_EN_SHIFT 0 -#define DDRC_PCTRL_4_PORT_EN_MASK 0x00000001U +#define DDRC_PCTRL_4_PORT_EN_DEFVAL +#define DDRC_PCTRL_4_PORT_EN_SHIFT 0 +#define DDRC_PCTRL_4_PORT_EN_MASK 0x00000001U -/*This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf - gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is - disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/ +/* +* This bitfield indicates the traffic class of region 1. Valid values are: + * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + * maps to the blue address queue. In this case, valid values are 0: LPR a + * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. +*/ #undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_DEFVAL #undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_SHIFT #undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_MASK -#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_DEFVAL 0x00000000 -#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_SHIFT 20 -#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_MASK 0x00300000U +#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_DEFVAL 0x00000000 +#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_SHIFT 20 +#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_MASK 0x00300000U -/*This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi - urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i - disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/ +/* +* This bitfield indicates the traffic class of region 0. Valid values are: + * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + * maps to the blue address queue. In this case, valid values are: 0: LPR + * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. +*/ #undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_DEFVAL #undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_SHIFT #undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_MASK -#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_DEFVAL 0x00000000 -#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_SHIFT 16 -#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_MASK 0x00030000U +#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_DEFVAL 0x00000000 +#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_SHIFT 16 +#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_MASK 0x00030000U -/*Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d - al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio - ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc - values.*/ +/* +* Separation level1 indicating the end of region0 mapping; start of region + * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + * lues are used directly as port priorities, where the higher the value co + * rresponds to higher port priority. All of the map_level* registers must + * be set to distinct values. +*/ #undef DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_DEFVAL #undef DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_SHIFT #undef DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_MASK -#define DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_DEFVAL 0x00000000 -#define DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_SHIFT 0 -#define DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_MASK 0x0000000FU +#define DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_DEFVAL 0x00000000 +#define DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_SHIFT 0 +#define DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_MASK 0x0000000FU -/*Specifies the timeout value for transactions mapped to the red address queue.*/ +/* +* Specifies the timeout value for transactions mapped to the red address q + * ueue. +*/ #undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_DEFVAL #undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_SHIFT #undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_MASK -#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_DEFVAL 0x00000000 -#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_SHIFT 16 -#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_MASK 0x07FF0000U +#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_DEFVAL 0x00000000 +#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_SHIFT 16 +#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_MASK 0x07FF0000U -/*Specifies the timeout value for transactions mapped to the blue address queue.*/ +/* +* Specifies the timeout value for transactions mapped to the blue address + * queue. +*/ #undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_DEFVAL #undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_SHIFT #undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_MASK -#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_DEFVAL 0x00000000 -#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_SHIFT 0 -#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_MASK 0x000007FFU +#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_DEFVAL 0x00000000 +#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_SHIFT 0 +#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_MASK 0x000007FFU -/*This bitfield indicates the traffic class of region 1. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2 - VPW_EN = 0) and traffic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW traffic.*/ +/* +* This bitfield indicates the traffic class of region 1. Valid values are: + * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + * affic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW + * traffic. +*/ #undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_DEFVAL #undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_SHIFT #undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_MASK -#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_DEFVAL 0x00000000 -#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_SHIFT 20 -#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_MASK 0x00300000U +#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_DEFVAL 0x00000000 +#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_SHIFT 20 +#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_MASK 0x00300000U -/*This bitfield indicates the traffic class of region 0. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2 - VPW_EN = 0) and traffic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW traffic.*/ +/* +* This bitfield indicates the traffic class of region 0. Valid values are: + * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + * affic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW + * traffic. +*/ #undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_DEFVAL #undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_SHIFT #undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_MASK -#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_DEFVAL 0x00000000 -#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_SHIFT 16 -#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_MASK 0x00030000U +#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_DEFVAL 0x00000000 +#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_SHIFT 16 +#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_MASK 0x00030000U -/*Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 14 which c - rresponds to awqos. Note that for PA, awqos values are used directly as port priorities, where the higher the value correspon - s to higher port priority.*/ +/* +* Separation level indicating the end of region0 mapping; start of region0 + * is 0. Possible values for level1 are 0 to 14 which corresponds to awqos + * . Note that for PA, awqos values are used directly as port priorities, w + * here the higher the value corresponds to higher port priority. +*/ #undef DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_DEFVAL #undef DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_SHIFT #undef DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_MASK -#define DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_DEFVAL 0x00000000 -#define DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_SHIFT 0 -#define DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_MASK 0x0000000FU +#define DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_DEFVAL 0x00000000 +#define DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_SHIFT 0 +#define DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_MASK 0x0000000FU -/*Specifies the timeout value for write transactions.*/ +/* +* Specifies the timeout value for write transactions. +*/ #undef DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_DEFVAL #undef DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_SHIFT #undef DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_MASK -#define DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_DEFVAL -#define DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_SHIFT 0 -#define DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_MASK 0x000007FFU +#define DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_DEFVAL +#define DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_SHIFT 0 +#define DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_MASK 0x000007FFU -/*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register.*/ +/* +* If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. +*/ #undef DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_DEFVAL #undef DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_SHIFT #undef DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_MASK -#define DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_DEFVAL 0x00000000 -#define DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_SHIFT 14 -#define DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_MASK 0x00004000U +#define DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_SHIFT 14 +#define DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_MASK 0x00004000U -/*If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG. - o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add - ess handshaking (it is not associated with any particular command).*/ +/* +* If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + * bled and arurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + * urgent signal can be asserted anytime and as long as required which is i + * ndependent of address handshaking (it is not associated with any particu + * lar command). +*/ #undef DDRC_PCFGR_5_RD_PORT_URGENT_EN_DEFVAL #undef DDRC_PCFGR_5_RD_PORT_URGENT_EN_SHIFT #undef DDRC_PCFGR_5_RD_PORT_URGENT_EN_MASK -#define DDRC_PCFGR_5_RD_PORT_URGENT_EN_DEFVAL 0x00000000 -#define DDRC_PCFGR_5_RD_PORT_URGENT_EN_SHIFT 13 -#define DDRC_PCFGR_5_RD_PORT_URGENT_EN_MASK 0x00002000U +#define DDRC_PCFGR_5_RD_PORT_URGENT_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_5_RD_PORT_URGENT_EN_SHIFT 13 +#define DDRC_PCFGR_5_RD_PORT_URGENT_EN_MASK 0x00002000U -/*If set to 1, enables aging function for the read channel of the port.*/ +/* +* If set to 1, enables aging function for the read channel of the port. +*/ #undef DDRC_PCFGR_5_RD_PORT_AGING_EN_DEFVAL #undef DDRC_PCFGR_5_RD_PORT_AGING_EN_SHIFT #undef DDRC_PCFGR_5_RD_PORT_AGING_EN_MASK -#define DDRC_PCFGR_5_RD_PORT_AGING_EN_DEFVAL 0x00000000 -#define DDRC_PCFGR_5_RD_PORT_AGING_EN_SHIFT 12 -#define DDRC_PCFGR_5_RD_PORT_AGING_EN_MASK 0x00001000U +#define DDRC_PCFGR_5_RD_PORT_AGING_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_5_RD_PORT_AGING_EN_SHIFT 12 +#define DDRC_PCFGR_5_RD_PORT_AGING_EN_MASK 0x00001000U -/*Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g - ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority - will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre - ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the - aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st - ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w - ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D - RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: - he two LSBs of this register field are tied internally to 2'b00.*/ +/* +* Determines the initial load value of read aging counters. These counters + * will be parallel loaded after reset, or after each grant to the corresp + * onding port. The aging counters down-count every clock cycle where the p + * ort is requesting but not granted. The higher significant 5-bits of the + * read aging counter sets the priority of the read channel of a given port + * . Port's priority will increase as the higher significant 5-bits of the + * counter starts to decrease. When the aging counter becomes 0, the corres + * ponding port channel will have the highest priority level (timeout condi + * tion - Priority0). For multi-port configurations, the aging counters can + * not be used to set port priorities when external dynamic priority inputs + * (arqos) are enabled (timeout is still applicable). For single port conf + * igurations, the aging counters are only used when they timeout (become 0 + * ) to force read-write direction switching. In this case, external dynami + * c priority input, arqos (for reads only) can still be used to set the DD + * RC read priority (2 priority levels: low priority read - LPR, high prior + * ity read - HPR) on a command by command basis. Note: The two LSBs of thi + * s register field are tied internally to 2'b00. +*/ #undef DDRC_PCFGR_5_RD_PORT_PRIORITY_DEFVAL #undef DDRC_PCFGR_5_RD_PORT_PRIORITY_SHIFT #undef DDRC_PCFGR_5_RD_PORT_PRIORITY_MASK -#define DDRC_PCFGR_5_RD_PORT_PRIORITY_DEFVAL 0x00000000 -#define DDRC_PCFGR_5_RD_PORT_PRIORITY_SHIFT 0 -#define DDRC_PCFGR_5_RD_PORT_PRIORITY_MASK 0x000003FFU +#define DDRC_PCFGR_5_RD_PORT_PRIORITY_DEFVAL 0x00000000 +#define DDRC_PCFGR_5_RD_PORT_PRIORITY_SHIFT 0 +#define DDRC_PCFGR_5_RD_PORT_PRIORITY_MASK 0x000003FFU -/*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register.*/ +/* +* If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. +*/ #undef DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_DEFVAL #undef DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_SHIFT #undef DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_MASK -#define DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_DEFVAL 0x00004000 -#define DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_SHIFT 14 -#define DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_MASK 0x00004000U +#define DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_SHIFT 14 +#define DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_MASK 0x00004000U -/*If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register - Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is - not associated with any particular command).*/ +/* +* If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + * bled and awurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + * serted anytime and as long as required which is independent of address h + * andshaking (it is not associated with any particular command). +*/ #undef DDRC_PCFGW_5_WR_PORT_URGENT_EN_DEFVAL #undef DDRC_PCFGW_5_WR_PORT_URGENT_EN_SHIFT #undef DDRC_PCFGW_5_WR_PORT_URGENT_EN_MASK -#define DDRC_PCFGW_5_WR_PORT_URGENT_EN_DEFVAL 0x00004000 -#define DDRC_PCFGW_5_WR_PORT_URGENT_EN_SHIFT 13 -#define DDRC_PCFGW_5_WR_PORT_URGENT_EN_MASK 0x00002000U +#define DDRC_PCFGW_5_WR_PORT_URGENT_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_5_WR_PORT_URGENT_EN_SHIFT 13 +#define DDRC_PCFGW_5_WR_PORT_URGENT_EN_MASK 0x00002000U -/*If set to 1, enables aging function for the write channel of the port.*/ +/* +* If set to 1, enables aging function for the write channel of the port. +*/ #undef DDRC_PCFGW_5_WR_PORT_AGING_EN_DEFVAL #undef DDRC_PCFGW_5_WR_PORT_AGING_EN_SHIFT #undef DDRC_PCFGW_5_WR_PORT_AGING_EN_MASK -#define DDRC_PCFGW_5_WR_PORT_AGING_EN_DEFVAL 0x00004000 -#define DDRC_PCFGW_5_WR_PORT_AGING_EN_SHIFT 12 -#define DDRC_PCFGW_5_WR_PORT_AGING_EN_MASK 0x00001000U +#define DDRC_PCFGW_5_WR_PORT_AGING_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_5_WR_PORT_AGING_EN_SHIFT 12 +#define DDRC_PCFGW_5_WR_PORT_AGING_EN_MASK 0x00001000U -/*Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each - rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port - s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0 - the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno - be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For - ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch - ng. Note: The two LSBs of this register field are tied internally to 2'b00.*/ +/* +* Determines the initial load value of write aging counters. These counter + * s will be parallel loaded after reset, or after each grant to the corres + * ponding port. The aging counters down-count every clock cycle where the + * port is requesting but not granted. The higher significant 5-bits of the + * write aging counter sets the initial priority of the write channel of a + * given port. Port's priority will increase as the higher significant 5-b + * its of the counter starts to decrease. When the aging counter becomes 0, + * the corresponding port channel will have the highest priority level. Fo + * r multi-port configurations, the aging counters cannot be used to set po + * rt priorities when external dynamic priority inputs (awqos) are enabled + * (timeout is still applicable). For single port configurations, the aging + * counters are only used when they timeout (become 0) to force read-write + * direction switching. Note: The two LSBs of this register field are tied + * internally to 2'b00. +*/ #undef DDRC_PCFGW_5_WR_PORT_PRIORITY_DEFVAL #undef DDRC_PCFGW_5_WR_PORT_PRIORITY_SHIFT #undef DDRC_PCFGW_5_WR_PORT_PRIORITY_MASK -#define DDRC_PCFGW_5_WR_PORT_PRIORITY_DEFVAL 0x00004000 -#define DDRC_PCFGW_5_WR_PORT_PRIORITY_SHIFT 0 -#define DDRC_PCFGW_5_WR_PORT_PRIORITY_MASK 0x000003FFU +#define DDRC_PCFGW_5_WR_PORT_PRIORITY_DEFVAL 0x00004000 +#define DDRC_PCFGW_5_WR_PORT_PRIORITY_SHIFT 0 +#define DDRC_PCFGW_5_WR_PORT_PRIORITY_MASK 0x000003FFU -/*Enables port n.*/ +/* +* Enables port n. +*/ #undef DDRC_PCTRL_5_PORT_EN_DEFVAL #undef DDRC_PCTRL_5_PORT_EN_SHIFT #undef DDRC_PCTRL_5_PORT_EN_MASK -#define DDRC_PCTRL_5_PORT_EN_DEFVAL -#define DDRC_PCTRL_5_PORT_EN_SHIFT 0 -#define DDRC_PCTRL_5_PORT_EN_MASK 0x00000001U +#define DDRC_PCTRL_5_PORT_EN_DEFVAL +#define DDRC_PCTRL_5_PORT_EN_SHIFT 0 +#define DDRC_PCTRL_5_PORT_EN_MASK 0x00000001U -/*This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf - gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is - disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/ +/* +* This bitfield indicates the traffic class of region 1. Valid values are: + * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + * maps to the blue address queue. In this case, valid values are 0: LPR a + * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. +*/ #undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_DEFVAL #undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_SHIFT #undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_MASK -#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_DEFVAL 0x00000000 -#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_SHIFT 20 -#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_MASK 0x00300000U +#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_DEFVAL 0x00000000 +#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_SHIFT 20 +#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_MASK 0x00300000U -/*This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi - urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i - disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/ +/* +* This bitfield indicates the traffic class of region 0. Valid values are: + * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + * maps to the blue address queue. In this case, valid values are: 0: LPR + * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. +*/ #undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_DEFVAL #undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_SHIFT #undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_MASK -#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_DEFVAL 0x00000000 -#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_SHIFT 16 -#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_MASK 0x00030000U +#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_DEFVAL 0x00000000 +#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_SHIFT 16 +#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_MASK 0x00030000U -/*Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d - al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio - ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc - values.*/ +/* +* Separation level1 indicating the end of region0 mapping; start of region + * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + * lues are used directly as port priorities, where the higher the value co + * rresponds to higher port priority. All of the map_level* registers must + * be set to distinct values. +*/ #undef DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_DEFVAL #undef DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_SHIFT #undef DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_MASK -#define DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_DEFVAL 0x00000000 -#define DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_SHIFT 0 -#define DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_MASK 0x0000000FU +#define DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_DEFVAL 0x00000000 +#define DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_SHIFT 0 +#define DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_MASK 0x0000000FU -/*Specifies the timeout value for transactions mapped to the red address queue.*/ +/* +* Specifies the timeout value for transactions mapped to the red address q + * ueue. +*/ #undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_DEFVAL #undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_SHIFT #undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_MASK -#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_DEFVAL 0x00000000 -#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_SHIFT 16 -#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_MASK 0x07FF0000U +#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_DEFVAL 0x00000000 +#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_SHIFT 16 +#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_MASK 0x07FF0000U -/*Specifies the timeout value for transactions mapped to the blue address queue.*/ +/* +* Specifies the timeout value for transactions mapped to the blue address + * queue. +*/ #undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_DEFVAL #undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_SHIFT #undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_MASK -#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_DEFVAL 0x00000000 -#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_SHIFT 0 -#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_MASK 0x000007FFU +#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_DEFVAL 0x00000000 +#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_SHIFT 0 +#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_MASK 0x000007FFU -/*This bitfield indicates the traffic class of region 1. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2 - VPW_EN = 0) and traffic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW traffic.*/ +/* +* This bitfield indicates the traffic class of region 1. Valid values are: + * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + * affic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW + * traffic. +*/ #undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_DEFVAL #undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_SHIFT #undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_MASK -#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_DEFVAL 0x00000000 -#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_SHIFT 20 -#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_MASK 0x00300000U +#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_DEFVAL 0x00000000 +#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_SHIFT 20 +#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_MASK 0x00300000U -/*This bitfield indicates the traffic class of region 0. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2 - VPW_EN = 0) and traffic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW traffic.*/ +/* +* This bitfield indicates the traffic class of region 0. Valid values are: + * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + * affic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW + * traffic. +*/ #undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_DEFVAL #undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_SHIFT #undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_MASK -#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_DEFVAL 0x00000000 -#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_SHIFT 16 -#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_MASK 0x00030000U +#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_DEFVAL 0x00000000 +#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_SHIFT 16 +#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_MASK 0x00030000U -/*Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 14 which c - rresponds to awqos. Note that for PA, awqos values are used directly as port priorities, where the higher the value correspon - s to higher port priority.*/ +/* +* Separation level indicating the end of region0 mapping; start of region0 + * is 0. Possible values for level1 are 0 to 14 which corresponds to awqos + * . Note that for PA, awqos values are used directly as port priorities, w + * here the higher the value corresponds to higher port priority. +*/ #undef DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_DEFVAL #undef DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_SHIFT #undef DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_MASK -#define DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_DEFVAL 0x00000000 -#define DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_SHIFT 0 -#define DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_MASK 0x0000000FU +#define DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_DEFVAL 0x00000000 +#define DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_SHIFT 0 +#define DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_MASK 0x0000000FU -/*Specifies the timeout value for write transactions.*/ +/* +* Specifies the timeout value for write transactions. +*/ #undef DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_DEFVAL #undef DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_SHIFT #undef DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_MASK -#define DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_DEFVAL -#define DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_SHIFT 0 -#define DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_MASK 0x000007FFU +#define DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_DEFVAL +#define DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_SHIFT 0 +#define DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_MASK 0x000007FFU -/*Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x] and araddr[UMCTL2_A_ADDRW-1:x] where x is determine - by the minimum block size parameter UMCTL2_SARMINSIZE: (x=log2(block size)).*/ +/* +* Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x + * ] and araddr[UMCTL2_A_ADDRW-1:x] where x is determined by the minimum bl + * ock size parameter UMCTL2_SARMINSIZE: (x=log2(block size)). +*/ #undef DDRC_SARBASE0_BASE_ADDR_DEFVAL #undef DDRC_SARBASE0_BASE_ADDR_SHIFT #undef DDRC_SARBASE0_BASE_ADDR_MASK -#define DDRC_SARBASE0_BASE_ADDR_DEFVAL -#define DDRC_SARBASE0_BASE_ADDR_SHIFT 0 -#define DDRC_SARBASE0_BASE_ADDR_MASK 0x000001FFU +#define DDRC_SARBASE0_BASE_ADDR_DEFVAL +#define DDRC_SARBASE0_BASE_ADDR_SHIFT 0 +#define DDRC_SARBASE0_BASE_ADDR_MASK 0x000001FFU -/*Number of blocks for address region n. This register determines the total size of the region in multiples of minimum block si - e as specified by the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded as number of blocks = nblocks + 1. - or example, if register is programmed to 0, region will have 1 block.*/ +/* +* Number of blocks for address region n. This register determines the tota + * l size of the region in multiples of minimum block size as specified by + * the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded + * as number of blocks = nblocks + 1. For example, if register is programme + * d to 0, region will have 1 block. +*/ #undef DDRC_SARSIZE0_NBLOCKS_DEFVAL #undef DDRC_SARSIZE0_NBLOCKS_SHIFT #undef DDRC_SARSIZE0_NBLOCKS_MASK -#define DDRC_SARSIZE0_NBLOCKS_DEFVAL -#define DDRC_SARSIZE0_NBLOCKS_SHIFT 0 -#define DDRC_SARSIZE0_NBLOCKS_MASK 0x000000FFU +#define DDRC_SARSIZE0_NBLOCKS_DEFVAL +#define DDRC_SARSIZE0_NBLOCKS_SHIFT 0 +#define DDRC_SARSIZE0_NBLOCKS_MASK 0x000000FFU -/*Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x] and araddr[UMCTL2_A_ADDRW-1:x] where x is determine - by the minimum block size parameter UMCTL2_SARMINSIZE: (x=log2(block size)).*/ +/* +* Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x + * ] and araddr[UMCTL2_A_ADDRW-1:x] where x is determined by the minimum bl + * ock size parameter UMCTL2_SARMINSIZE: (x=log2(block size)). +*/ #undef DDRC_SARBASE1_BASE_ADDR_DEFVAL #undef DDRC_SARBASE1_BASE_ADDR_SHIFT #undef DDRC_SARBASE1_BASE_ADDR_MASK -#define DDRC_SARBASE1_BASE_ADDR_DEFVAL -#define DDRC_SARBASE1_BASE_ADDR_SHIFT 0 -#define DDRC_SARBASE1_BASE_ADDR_MASK 0x000001FFU +#define DDRC_SARBASE1_BASE_ADDR_DEFVAL +#define DDRC_SARBASE1_BASE_ADDR_SHIFT 0 +#define DDRC_SARBASE1_BASE_ADDR_MASK 0x000001FFU -/*Number of blocks for address region n. This register determines the total size of the region in multiples of minimum block si - e as specified by the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded as number of blocks = nblocks + 1. - or example, if register is programmed to 0, region will have 1 block.*/ +/* +* Number of blocks for address region n. This register determines the tota + * l size of the region in multiples of minimum block size as specified by + * the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded + * as number of blocks = nblocks + 1. For example, if register is programme + * d to 0, region will have 1 block. +*/ #undef DDRC_SARSIZE1_NBLOCKS_DEFVAL #undef DDRC_SARSIZE1_NBLOCKS_SHIFT #undef DDRC_SARSIZE1_NBLOCKS_MASK -#define DDRC_SARSIZE1_NBLOCKS_DEFVAL -#define DDRC_SARSIZE1_NBLOCKS_SHIFT 0 -#define DDRC_SARSIZE1_NBLOCKS_MASK 0x000000FFU +#define DDRC_SARSIZE1_NBLOCKS_DEFVAL +#define DDRC_SARSIZE1_NBLOCKS_SHIFT 0 +#define DDRC_SARSIZE1_NBLOCKS_MASK 0x000000FFU -/*Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signa - s at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligne - , this timing parameter should be rounded up to the next integer value. Note that if using RDIMM, it is necessary to incremen - this parameter by RDIMM's extra cycle of latency in terms of DFI clock.*/ +/* +* Specifies the number of DFI clock cycles after an assertion or de-assert + * ion of the DFI control signals that the control signals at the PHY-DRAM + * interface reflect the assertion or de-assertion. If the DFI clock and th + * e memory clock are not phase-aligned, this timing parameter should be ro + * unded up to the next integer value. Note that if using RDIMM, it is nece + * ssary to increment this parameter by RDIMM's extra cycle of latency in t + * erms of DFI clock. +*/ #undef DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_DEFVAL #undef DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_SHIFT #undef DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_MASK -#define DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_DEFVAL 0x07020002 -#define DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_SHIFT 24 -#define DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_MASK 0x1F000000U +#define DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_DEFVAL 0x07020002 +#define DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_SHIFT 24 +#define DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_MASK 0x1F000000U -/*Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR or SDR values Selects whether value in DFITM - 0.dfi_t_rddata_en is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles R - fer to PHY specification for correct value.*/ +/* +* Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated u + * sing HDR or SDR values Selects whether value in DFITMG0.dfi_t_rddata_en + * is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles + * - 1 in terms of SDR clock cycles Refer to PHY specification for correct + * value. +*/ #undef DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_DEFVAL #undef DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_SHIFT #undef DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_MASK -#define DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_DEFVAL 0x07020002 -#define DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_SHIFT 23 -#define DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_MASK 0x00800000U +#define DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_DEFVAL 0x07020002 +#define DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_SHIFT 23 +#define DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_MASK 0x00800000U -/*Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. Refer to PHY spe - ification for correct value. This corresponds to the DFI parameter trddata_en. Note that, depending on the PHY, if using RDIM - , it may be necessary to use the value (CL + 1) in the calculation of trddata_en. This is to compensate for the extra cycle o - latency through the RDIMM. Unit: Clocks*/ +/* +* Time from the assertion of a read command on the DFI interface to the as + * sertion of the dfi_rddata_en signal. Refer to PHY specification for corr + * ect value. This corresponds to the DFI parameter trddata_en. Note that, + * depending on the PHY, if using RDIMM, it may be necessary to use the val + * ue (CL + 1) in the calculation of trddata_en. This is to compensate for + * the extra cycle of latency through the RDIMM. Unit: Clocks +*/ #undef DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_DEFVAL #undef DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_SHIFT #undef DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_MASK -#define DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_DEFVAL 0x07020002 -#define DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_SHIFT 16 -#define DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_MASK 0x003F0000U +#define DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_DEFVAL 0x07020002 +#define DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_SHIFT 16 +#define DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_MASK 0x003F0000U -/*Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using HDR or SDR values Selects whether value in DFITMG - .dfi_tphy_wrlat is in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.dfi_tphy_wrdata is in terms of SDR or - HDR clock cycles - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles Refer to PHY specification for correct val - e.*/ +/* +* Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated us + * ing HDR or SDR values Selects whether value in DFITMG0.dfi_tphy_wrlat is + * in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.df + * i_tphy_wrdata is in terms of SDR or HDR clock cycles - 0 in terms of HDR + * clock cycles - 1 in terms of SDR clock cycles Refer to PHY specificatio + * n for correct value. +*/ #undef DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_DEFVAL #undef DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_SHIFT #undef DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_MASK -#define DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_DEFVAL 0x07020002 -#define DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_SHIFT 15 -#define DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_MASK 0x00008000U +#define DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_DEFVAL 0x07020002 +#define DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_SHIFT 15 +#define DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_MASK 0x00008000U -/*Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on th - dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. N - te, max supported value is 8. Unit: Clocks*/ +/* +* Specifies the number of clock cycles between when dfi_wrdata_en is asser + * ted to when the associated write data is driven on the dfi_wrdata signal + * . This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY + * specification for correct value. Note, max supported value is 8. Unit: + * Clocks +*/ #undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_DEFVAL #undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_SHIFT #undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_MASK -#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_DEFVAL 0x07020002 -#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_SHIFT 8 -#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_MASK 0x00003F00U +#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_DEFVAL 0x07020002 +#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_SHIFT 8 +#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_MASK 0x00003F00U -/*Write latency Number of clocks from the write command to write data enable (dfi_wrdata_en). This corresponds to the DFI timin - parameter tphy_wrlat. Refer to PHY specification for correct value.Note that, depending on the PHY, if using RDIMM, it may b - necessary to use the value (CL + 1) in the calculation of tphy_wrlat. This is to compensate for the extra cycle of latency t - rough the RDIMM.*/ +/* +* Write latency Number of clocks from the write command to write data enab + * le (dfi_wrdata_en). This corresponds to the DFI timing parameter tphy_wr + * lat. Refer to PHY specification for correct value.Note that, depending o + * n the PHY, if using RDIMM, it may be necessary to use the value (CL + 1) + * in the calculation of tphy_wrlat. This is to compensate for the extra c + * ycle of latency through the RDIMM. +*/ #undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_DEFVAL #undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_SHIFT #undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_MASK -#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_DEFVAL 0x07020002 -#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_SHIFT 0 -#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_MASK 0x0000003FU +#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_DEFVAL 0x07020002 +#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_SHIFT 0 +#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_MASK 0x0000003FU -/*DDR block level reset inside of the DDR Sub System*/ +/* +* DDR block level reset inside of the DDR Sub System +*/ #undef CRF_APB_RST_DDR_SS_DDR_RESET_DEFVAL #undef CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT #undef CRF_APB_RST_DDR_SS_DDR_RESET_MASK -#define CRF_APB_RST_DDR_SS_DDR_RESET_DEFVAL 0x0000000F -#define CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT 3 -#define CRF_APB_RST_DDR_SS_DDR_RESET_MASK 0x00000008U +#define CRF_APB_RST_DDR_SS_DDR_RESET_DEFVAL 0x0000000F +#define CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT 3 +#define CRF_APB_RST_DDR_SS_DDR_RESET_MASK 0x00000008U -/*Address Copy*/ +/* +* APM block level reset inside of the DDR Sub System +*/ +#undef CRF_APB_RST_DDR_SS_APM_RESET_DEFVAL +#undef CRF_APB_RST_DDR_SS_APM_RESET_SHIFT +#undef CRF_APB_RST_DDR_SS_APM_RESET_MASK +#define CRF_APB_RST_DDR_SS_APM_RESET_DEFVAL 0x0000000F +#define CRF_APB_RST_DDR_SS_APM_RESET_SHIFT 2 +#define CRF_APB_RST_DDR_SS_APM_RESET_MASK 0x00000004U + +/* +* Address Copy +*/ #undef DDR_PHY_PGCR0_ADCP_DEFVAL #undef DDR_PHY_PGCR0_ADCP_SHIFT #undef DDR_PHY_PGCR0_ADCP_MASK -#define DDR_PHY_PGCR0_ADCP_DEFVAL 0x07001E00 -#define DDR_PHY_PGCR0_ADCP_SHIFT 31 -#define DDR_PHY_PGCR0_ADCP_MASK 0x80000000U +#define DDR_PHY_PGCR0_ADCP_DEFVAL 0x07001E00 +#define DDR_PHY_PGCR0_ADCP_SHIFT 31 +#define DDR_PHY_PGCR0_ADCP_MASK 0x80000000U -/*Reserved. Returns zeroes on reads.*/ +/* +* Reserved. Returns zeroes on reads. +*/ #undef DDR_PHY_PGCR0_RESERVED_30_27_DEFVAL #undef DDR_PHY_PGCR0_RESERVED_30_27_SHIFT #undef DDR_PHY_PGCR0_RESERVED_30_27_MASK -#define DDR_PHY_PGCR0_RESERVED_30_27_DEFVAL 0x07001E00 -#define DDR_PHY_PGCR0_RESERVED_30_27_SHIFT 27 -#define DDR_PHY_PGCR0_RESERVED_30_27_MASK 0x78000000U +#define DDR_PHY_PGCR0_RESERVED_30_27_DEFVAL 0x07001E00 +#define DDR_PHY_PGCR0_RESERVED_30_27_SHIFT 27 +#define DDR_PHY_PGCR0_RESERVED_30_27_MASK 0x78000000U -/*PHY FIFO Reset*/ +/* +* PHY FIFO Reset +*/ #undef DDR_PHY_PGCR0_PHYFRST_DEFVAL #undef DDR_PHY_PGCR0_PHYFRST_SHIFT #undef DDR_PHY_PGCR0_PHYFRST_MASK -#define DDR_PHY_PGCR0_PHYFRST_DEFVAL 0x07001E00 -#define DDR_PHY_PGCR0_PHYFRST_SHIFT 26 -#define DDR_PHY_PGCR0_PHYFRST_MASK 0x04000000U +#define DDR_PHY_PGCR0_PHYFRST_DEFVAL 0x07001E00 +#define DDR_PHY_PGCR0_PHYFRST_SHIFT 26 +#define DDR_PHY_PGCR0_PHYFRST_MASK 0x04000000U -/*Oscillator Mode Address/Command Delay Line Select*/ +/* +* Oscillator Mode Address/Command Delay Line Select +*/ #undef DDR_PHY_PGCR0_OSCACDL_DEFVAL #undef DDR_PHY_PGCR0_OSCACDL_SHIFT #undef DDR_PHY_PGCR0_OSCACDL_MASK -#define DDR_PHY_PGCR0_OSCACDL_DEFVAL 0x07001E00 -#define DDR_PHY_PGCR0_OSCACDL_SHIFT 24 -#define DDR_PHY_PGCR0_OSCACDL_MASK 0x03000000U +#define DDR_PHY_PGCR0_OSCACDL_DEFVAL 0x07001E00 +#define DDR_PHY_PGCR0_OSCACDL_SHIFT 24 +#define DDR_PHY_PGCR0_OSCACDL_MASK 0x03000000U -/*Reserved. Returns zeroes on reads.*/ +/* +* Reserved. Returns zeroes on reads. +*/ #undef DDR_PHY_PGCR0_RESERVED_23_19_DEFVAL #undef DDR_PHY_PGCR0_RESERVED_23_19_SHIFT #undef DDR_PHY_PGCR0_RESERVED_23_19_MASK -#define DDR_PHY_PGCR0_RESERVED_23_19_DEFVAL 0x07001E00 -#define DDR_PHY_PGCR0_RESERVED_23_19_SHIFT 19 -#define DDR_PHY_PGCR0_RESERVED_23_19_MASK 0x00F80000U +#define DDR_PHY_PGCR0_RESERVED_23_19_DEFVAL 0x07001E00 +#define DDR_PHY_PGCR0_RESERVED_23_19_SHIFT 19 +#define DDR_PHY_PGCR0_RESERVED_23_19_MASK 0x00F80000U -/*Digital Test Output Select*/ +/* +* Digital Test Output Select +*/ #undef DDR_PHY_PGCR0_DTOSEL_DEFVAL #undef DDR_PHY_PGCR0_DTOSEL_SHIFT #undef DDR_PHY_PGCR0_DTOSEL_MASK -#define DDR_PHY_PGCR0_DTOSEL_DEFVAL 0x07001E00 -#define DDR_PHY_PGCR0_DTOSEL_SHIFT 14 -#define DDR_PHY_PGCR0_DTOSEL_MASK 0x0007C000U +#define DDR_PHY_PGCR0_DTOSEL_DEFVAL 0x07001E00 +#define DDR_PHY_PGCR0_DTOSEL_SHIFT 14 +#define DDR_PHY_PGCR0_DTOSEL_MASK 0x0007C000U -/*Reserved. Returns zeroes on reads.*/ +/* +* Reserved. Returns zeroes on reads. +*/ #undef DDR_PHY_PGCR0_RESERVED_13_DEFVAL #undef DDR_PHY_PGCR0_RESERVED_13_SHIFT #undef DDR_PHY_PGCR0_RESERVED_13_MASK -#define DDR_PHY_PGCR0_RESERVED_13_DEFVAL 0x07001E00 -#define DDR_PHY_PGCR0_RESERVED_13_SHIFT 13 -#define DDR_PHY_PGCR0_RESERVED_13_MASK 0x00002000U +#define DDR_PHY_PGCR0_RESERVED_13_DEFVAL 0x07001E00 +#define DDR_PHY_PGCR0_RESERVED_13_SHIFT 13 +#define DDR_PHY_PGCR0_RESERVED_13_MASK 0x00002000U -/*Oscillator Mode Division*/ +/* +* Oscillator Mode Division +*/ #undef DDR_PHY_PGCR0_OSCDIV_DEFVAL #undef DDR_PHY_PGCR0_OSCDIV_SHIFT #undef DDR_PHY_PGCR0_OSCDIV_MASK -#define DDR_PHY_PGCR0_OSCDIV_DEFVAL 0x07001E00 -#define DDR_PHY_PGCR0_OSCDIV_SHIFT 9 -#define DDR_PHY_PGCR0_OSCDIV_MASK 0x00001E00U +#define DDR_PHY_PGCR0_OSCDIV_DEFVAL 0x07001E00 +#define DDR_PHY_PGCR0_OSCDIV_SHIFT 9 +#define DDR_PHY_PGCR0_OSCDIV_MASK 0x00001E00U -/*Oscillator Enable*/ +/* +* Oscillator Enable +*/ #undef DDR_PHY_PGCR0_OSCEN_DEFVAL #undef DDR_PHY_PGCR0_OSCEN_SHIFT #undef DDR_PHY_PGCR0_OSCEN_MASK -#define DDR_PHY_PGCR0_OSCEN_DEFVAL 0x07001E00 -#define DDR_PHY_PGCR0_OSCEN_SHIFT 8 -#define DDR_PHY_PGCR0_OSCEN_MASK 0x00000100U +#define DDR_PHY_PGCR0_OSCEN_DEFVAL 0x07001E00 +#define DDR_PHY_PGCR0_OSCEN_SHIFT 8 +#define DDR_PHY_PGCR0_OSCEN_MASK 0x00000100U -/*Reserved. Returns zeroes on reads.*/ +/* +* Reserved. Returns zeroes on reads. +*/ #undef DDR_PHY_PGCR0_RESERVED_7_0_DEFVAL #undef DDR_PHY_PGCR0_RESERVED_7_0_SHIFT #undef DDR_PHY_PGCR0_RESERVED_7_0_MASK -#define DDR_PHY_PGCR0_RESERVED_7_0_DEFVAL 0x07001E00 -#define DDR_PHY_PGCR0_RESERVED_7_0_SHIFT 0 -#define DDR_PHY_PGCR0_RESERVED_7_0_MASK 0x000000FFU +#define DDR_PHY_PGCR0_RESERVED_7_0_DEFVAL 0x07001E00 +#define DDR_PHY_PGCR0_RESERVED_7_0_SHIFT 0 +#define DDR_PHY_PGCR0_RESERVED_7_0_MASK 0x000000FFU -/*Clear Training Status Registers*/ +/* +* Clear Training Status Registers +*/ #undef DDR_PHY_PGCR2_CLRTSTAT_DEFVAL #undef DDR_PHY_PGCR2_CLRTSTAT_SHIFT #undef DDR_PHY_PGCR2_CLRTSTAT_MASK -#define DDR_PHY_PGCR2_CLRTSTAT_DEFVAL 0x00F12480 -#define DDR_PHY_PGCR2_CLRTSTAT_SHIFT 31 -#define DDR_PHY_PGCR2_CLRTSTAT_MASK 0x80000000U +#define DDR_PHY_PGCR2_CLRTSTAT_DEFVAL 0x00F12480 +#define DDR_PHY_PGCR2_CLRTSTAT_SHIFT 31 +#define DDR_PHY_PGCR2_CLRTSTAT_MASK 0x80000000U -/*Clear Impedance Calibration*/ +/* +* Clear Impedance Calibration +*/ #undef DDR_PHY_PGCR2_CLRZCAL_DEFVAL #undef DDR_PHY_PGCR2_CLRZCAL_SHIFT #undef DDR_PHY_PGCR2_CLRZCAL_MASK -#define DDR_PHY_PGCR2_CLRZCAL_DEFVAL 0x00F12480 -#define DDR_PHY_PGCR2_CLRZCAL_SHIFT 30 -#define DDR_PHY_PGCR2_CLRZCAL_MASK 0x40000000U +#define DDR_PHY_PGCR2_CLRZCAL_DEFVAL 0x00F12480 +#define DDR_PHY_PGCR2_CLRZCAL_SHIFT 30 +#define DDR_PHY_PGCR2_CLRZCAL_MASK 0x40000000U -/*Clear Parity Error*/ +/* +* Clear Parity Error +*/ #undef DDR_PHY_PGCR2_CLRPERR_DEFVAL #undef DDR_PHY_PGCR2_CLRPERR_SHIFT #undef DDR_PHY_PGCR2_CLRPERR_MASK -#define DDR_PHY_PGCR2_CLRPERR_DEFVAL 0x00F12480 -#define DDR_PHY_PGCR2_CLRPERR_SHIFT 29 -#define DDR_PHY_PGCR2_CLRPERR_MASK 0x20000000U +#define DDR_PHY_PGCR2_CLRPERR_DEFVAL 0x00F12480 +#define DDR_PHY_PGCR2_CLRPERR_SHIFT 29 +#define DDR_PHY_PGCR2_CLRPERR_MASK 0x20000000U -/*Initialization Complete Pin Configuration*/ +/* +* Initialization Complete Pin Configuration +*/ #undef DDR_PHY_PGCR2_ICPC_DEFVAL #undef DDR_PHY_PGCR2_ICPC_SHIFT #undef DDR_PHY_PGCR2_ICPC_MASK -#define DDR_PHY_PGCR2_ICPC_DEFVAL 0x00F12480 -#define DDR_PHY_PGCR2_ICPC_SHIFT 28 -#define DDR_PHY_PGCR2_ICPC_MASK 0x10000000U +#define DDR_PHY_PGCR2_ICPC_DEFVAL 0x00F12480 +#define DDR_PHY_PGCR2_ICPC_SHIFT 28 +#define DDR_PHY_PGCR2_ICPC_MASK 0x10000000U -/*Data Training PUB Mode Exit Timer*/ +/* +* Data Training PUB Mode Exit Timer +*/ #undef DDR_PHY_PGCR2_DTPMXTMR_DEFVAL #undef DDR_PHY_PGCR2_DTPMXTMR_SHIFT #undef DDR_PHY_PGCR2_DTPMXTMR_MASK -#define DDR_PHY_PGCR2_DTPMXTMR_DEFVAL 0x00F12480 -#define DDR_PHY_PGCR2_DTPMXTMR_SHIFT 20 -#define DDR_PHY_PGCR2_DTPMXTMR_MASK 0x0FF00000U +#define DDR_PHY_PGCR2_DTPMXTMR_DEFVAL 0x00F12480 +#define DDR_PHY_PGCR2_DTPMXTMR_SHIFT 20 +#define DDR_PHY_PGCR2_DTPMXTMR_MASK 0x0FF00000U -/*Initialization Bypass*/ +/* +* Initialization Bypass +*/ #undef DDR_PHY_PGCR2_INITFSMBYP_DEFVAL #undef DDR_PHY_PGCR2_INITFSMBYP_SHIFT #undef DDR_PHY_PGCR2_INITFSMBYP_MASK -#define DDR_PHY_PGCR2_INITFSMBYP_DEFVAL 0x00F12480 -#define DDR_PHY_PGCR2_INITFSMBYP_SHIFT 19 -#define DDR_PHY_PGCR2_INITFSMBYP_MASK 0x00080000U +#define DDR_PHY_PGCR2_INITFSMBYP_DEFVAL 0x00F12480 +#define DDR_PHY_PGCR2_INITFSMBYP_SHIFT 19 +#define DDR_PHY_PGCR2_INITFSMBYP_MASK 0x00080000U -/*PLL FSM Bypass*/ +/* +* PLL FSM Bypass +*/ #undef DDR_PHY_PGCR2_PLLFSMBYP_DEFVAL #undef DDR_PHY_PGCR2_PLLFSMBYP_SHIFT #undef DDR_PHY_PGCR2_PLLFSMBYP_MASK -#define DDR_PHY_PGCR2_PLLFSMBYP_DEFVAL 0x00F12480 -#define DDR_PHY_PGCR2_PLLFSMBYP_SHIFT 18 -#define DDR_PHY_PGCR2_PLLFSMBYP_MASK 0x00040000U +#define DDR_PHY_PGCR2_PLLFSMBYP_DEFVAL 0x00F12480 +#define DDR_PHY_PGCR2_PLLFSMBYP_SHIFT 18 +#define DDR_PHY_PGCR2_PLLFSMBYP_MASK 0x00040000U -/*Refresh Period*/ +/* +* Refresh Period +*/ #undef DDR_PHY_PGCR2_TREFPRD_DEFVAL #undef DDR_PHY_PGCR2_TREFPRD_SHIFT #undef DDR_PHY_PGCR2_TREFPRD_MASK -#define DDR_PHY_PGCR2_TREFPRD_DEFVAL 0x00F12480 -#define DDR_PHY_PGCR2_TREFPRD_SHIFT 0 -#define DDR_PHY_PGCR2_TREFPRD_MASK 0x0003FFFFU +#define DDR_PHY_PGCR2_TREFPRD_DEFVAL 0x00F12480 +#define DDR_PHY_PGCR2_TREFPRD_SHIFT 0 +#define DDR_PHY_PGCR2_TREFPRD_MASK 0x0003FFFFU -/*CKN Enable*/ +/* +* CKN Enable +*/ #undef DDR_PHY_PGCR3_CKNEN_DEFVAL #undef DDR_PHY_PGCR3_CKNEN_SHIFT #undef DDR_PHY_PGCR3_CKNEN_MASK -#define DDR_PHY_PGCR3_CKNEN_DEFVAL 0x55AA0080 -#define DDR_PHY_PGCR3_CKNEN_SHIFT 24 -#define DDR_PHY_PGCR3_CKNEN_MASK 0xFF000000U +#define DDR_PHY_PGCR3_CKNEN_DEFVAL 0x55AA0080 +#define DDR_PHY_PGCR3_CKNEN_SHIFT 24 +#define DDR_PHY_PGCR3_CKNEN_MASK 0xFF000000U -/*CK Enable*/ +/* +* CK Enable +*/ #undef DDR_PHY_PGCR3_CKEN_DEFVAL #undef DDR_PHY_PGCR3_CKEN_SHIFT #undef DDR_PHY_PGCR3_CKEN_MASK -#define DDR_PHY_PGCR3_CKEN_DEFVAL 0x55AA0080 -#define DDR_PHY_PGCR3_CKEN_SHIFT 16 -#define DDR_PHY_PGCR3_CKEN_MASK 0x00FF0000U +#define DDR_PHY_PGCR3_CKEN_DEFVAL 0x55AA0080 +#define DDR_PHY_PGCR3_CKEN_SHIFT 16 +#define DDR_PHY_PGCR3_CKEN_MASK 0x00FF0000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_PGCR3_RESERVED_15_DEFVAL #undef DDR_PHY_PGCR3_RESERVED_15_SHIFT #undef DDR_PHY_PGCR3_RESERVED_15_MASK -#define DDR_PHY_PGCR3_RESERVED_15_DEFVAL 0x55AA0080 -#define DDR_PHY_PGCR3_RESERVED_15_SHIFT 15 -#define DDR_PHY_PGCR3_RESERVED_15_MASK 0x00008000U +#define DDR_PHY_PGCR3_RESERVED_15_DEFVAL 0x55AA0080 +#define DDR_PHY_PGCR3_RESERVED_15_SHIFT 15 +#define DDR_PHY_PGCR3_RESERVED_15_MASK 0x00008000U -/*Enable Clock Gating for AC [0] ctl_rd_clk*/ +/* +* Enable Clock Gating for AC [0] ctl_rd_clk +*/ #undef DDR_PHY_PGCR3_GATEACRDCLK_DEFVAL #undef DDR_PHY_PGCR3_GATEACRDCLK_SHIFT #undef DDR_PHY_PGCR3_GATEACRDCLK_MASK -#define DDR_PHY_PGCR3_GATEACRDCLK_DEFVAL 0x55AA0080 -#define DDR_PHY_PGCR3_GATEACRDCLK_SHIFT 13 -#define DDR_PHY_PGCR3_GATEACRDCLK_MASK 0x00006000U +#define DDR_PHY_PGCR3_GATEACRDCLK_DEFVAL 0x55AA0080 +#define DDR_PHY_PGCR3_GATEACRDCLK_SHIFT 13 +#define DDR_PHY_PGCR3_GATEACRDCLK_MASK 0x00006000U -/*Enable Clock Gating for AC [0] ddr_clk*/ +/* +* Enable Clock Gating for AC [0] ddr_clk +*/ #undef DDR_PHY_PGCR3_GATEACDDRCLK_DEFVAL #undef DDR_PHY_PGCR3_GATEACDDRCLK_SHIFT #undef DDR_PHY_PGCR3_GATEACDDRCLK_MASK -#define DDR_PHY_PGCR3_GATEACDDRCLK_DEFVAL 0x55AA0080 -#define DDR_PHY_PGCR3_GATEACDDRCLK_SHIFT 11 -#define DDR_PHY_PGCR3_GATEACDDRCLK_MASK 0x00001800U +#define DDR_PHY_PGCR3_GATEACDDRCLK_DEFVAL 0x55AA0080 +#define DDR_PHY_PGCR3_GATEACDDRCLK_SHIFT 11 +#define DDR_PHY_PGCR3_GATEACDDRCLK_MASK 0x00001800U -/*Enable Clock Gating for AC [0] ctl_clk*/ +/* +* Enable Clock Gating for AC [0] ctl_clk +*/ #undef DDR_PHY_PGCR3_GATEACCTLCLK_DEFVAL #undef DDR_PHY_PGCR3_GATEACCTLCLK_SHIFT #undef DDR_PHY_PGCR3_GATEACCTLCLK_MASK -#define DDR_PHY_PGCR3_GATEACCTLCLK_DEFVAL 0x55AA0080 -#define DDR_PHY_PGCR3_GATEACCTLCLK_SHIFT 9 -#define DDR_PHY_PGCR3_GATEACCTLCLK_MASK 0x00000600U +#define DDR_PHY_PGCR3_GATEACCTLCLK_DEFVAL 0x55AA0080 +#define DDR_PHY_PGCR3_GATEACCTLCLK_SHIFT 9 +#define DDR_PHY_PGCR3_GATEACCTLCLK_MASK 0x00000600U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_PGCR3_RESERVED_8_DEFVAL #undef DDR_PHY_PGCR3_RESERVED_8_SHIFT #undef DDR_PHY_PGCR3_RESERVED_8_MASK -#define DDR_PHY_PGCR3_RESERVED_8_DEFVAL 0x55AA0080 -#define DDR_PHY_PGCR3_RESERVED_8_SHIFT 8 -#define DDR_PHY_PGCR3_RESERVED_8_MASK 0x00000100U +#define DDR_PHY_PGCR3_RESERVED_8_DEFVAL 0x55AA0080 +#define DDR_PHY_PGCR3_RESERVED_8_SHIFT 8 +#define DDR_PHY_PGCR3_RESERVED_8_MASK 0x00000100U -/*Controls DDL Bypass Modes*/ +/* +* Controls DDL Bypass Modes +*/ #undef DDR_PHY_PGCR3_DDLBYPMODE_DEFVAL #undef DDR_PHY_PGCR3_DDLBYPMODE_SHIFT #undef DDR_PHY_PGCR3_DDLBYPMODE_MASK -#define DDR_PHY_PGCR3_DDLBYPMODE_DEFVAL 0x55AA0080 -#define DDR_PHY_PGCR3_DDLBYPMODE_SHIFT 6 -#define DDR_PHY_PGCR3_DDLBYPMODE_MASK 0x000000C0U +#define DDR_PHY_PGCR3_DDLBYPMODE_DEFVAL 0x55AA0080 +#define DDR_PHY_PGCR3_DDLBYPMODE_SHIFT 6 +#define DDR_PHY_PGCR3_DDLBYPMODE_MASK 0x000000C0U -/*IO Loop-Back Select*/ +/* +* IO Loop-Back Select +*/ #undef DDR_PHY_PGCR3_IOLB_DEFVAL #undef DDR_PHY_PGCR3_IOLB_SHIFT #undef DDR_PHY_PGCR3_IOLB_MASK -#define DDR_PHY_PGCR3_IOLB_DEFVAL 0x55AA0080 -#define DDR_PHY_PGCR3_IOLB_SHIFT 5 -#define DDR_PHY_PGCR3_IOLB_MASK 0x00000020U +#define DDR_PHY_PGCR3_IOLB_DEFVAL 0x55AA0080 +#define DDR_PHY_PGCR3_IOLB_SHIFT 5 +#define DDR_PHY_PGCR3_IOLB_MASK 0x00000020U -/*AC Receive FIFO Read Mode*/ +/* +* AC Receive FIFO Read Mode +*/ #undef DDR_PHY_PGCR3_RDMODE_DEFVAL #undef DDR_PHY_PGCR3_RDMODE_SHIFT #undef DDR_PHY_PGCR3_RDMODE_MASK -#define DDR_PHY_PGCR3_RDMODE_DEFVAL 0x55AA0080 -#define DDR_PHY_PGCR3_RDMODE_SHIFT 3 -#define DDR_PHY_PGCR3_RDMODE_MASK 0x00000018U +#define DDR_PHY_PGCR3_RDMODE_DEFVAL 0x55AA0080 +#define DDR_PHY_PGCR3_RDMODE_SHIFT 3 +#define DDR_PHY_PGCR3_RDMODE_MASK 0x00000018U -/*Read FIFO Reset Disable*/ +/* +* Read FIFO Reset Disable +*/ #undef DDR_PHY_PGCR3_DISRST_DEFVAL #undef DDR_PHY_PGCR3_DISRST_SHIFT #undef DDR_PHY_PGCR3_DISRST_MASK -#define DDR_PHY_PGCR3_DISRST_DEFVAL 0x55AA0080 -#define DDR_PHY_PGCR3_DISRST_SHIFT 2 -#define DDR_PHY_PGCR3_DISRST_MASK 0x00000004U +#define DDR_PHY_PGCR3_DISRST_DEFVAL 0x55AA0080 +#define DDR_PHY_PGCR3_DISRST_SHIFT 2 +#define DDR_PHY_PGCR3_DISRST_MASK 0x00000004U -/*Clock Level when Clock Gating*/ +/* +* Clock Level when Clock Gating +*/ #undef DDR_PHY_PGCR3_CLKLEVEL_DEFVAL #undef DDR_PHY_PGCR3_CLKLEVEL_SHIFT #undef DDR_PHY_PGCR3_CLKLEVEL_MASK -#define DDR_PHY_PGCR3_CLKLEVEL_DEFVAL 0x55AA0080 -#define DDR_PHY_PGCR3_CLKLEVEL_SHIFT 0 -#define DDR_PHY_PGCR3_CLKLEVEL_MASK 0x00000003U +#define DDR_PHY_PGCR3_CLKLEVEL_DEFVAL 0x55AA0080 +#define DDR_PHY_PGCR3_CLKLEVEL_SHIFT 0 +#define DDR_PHY_PGCR3_CLKLEVEL_MASK 0x00000003U -/*Frequency B Ratio Term*/ +/* +* Frequency B Ratio Term +*/ #undef DDR_PHY_PGCR5_FRQBT_DEFVAL #undef DDR_PHY_PGCR5_FRQBT_SHIFT #undef DDR_PHY_PGCR5_FRQBT_MASK -#define DDR_PHY_PGCR5_FRQBT_DEFVAL 0x01010000 -#define DDR_PHY_PGCR5_FRQBT_SHIFT 24 -#define DDR_PHY_PGCR5_FRQBT_MASK 0xFF000000U +#define DDR_PHY_PGCR5_FRQBT_DEFVAL 0x01010000 +#define DDR_PHY_PGCR5_FRQBT_SHIFT 24 +#define DDR_PHY_PGCR5_FRQBT_MASK 0xFF000000U -/*Frequency A Ratio Term*/ +/* +* Frequency A Ratio Term +*/ #undef DDR_PHY_PGCR5_FRQAT_DEFVAL #undef DDR_PHY_PGCR5_FRQAT_SHIFT #undef DDR_PHY_PGCR5_FRQAT_MASK -#define DDR_PHY_PGCR5_FRQAT_DEFVAL 0x01010000 -#define DDR_PHY_PGCR5_FRQAT_SHIFT 16 -#define DDR_PHY_PGCR5_FRQAT_MASK 0x00FF0000U +#define DDR_PHY_PGCR5_FRQAT_DEFVAL 0x01010000 +#define DDR_PHY_PGCR5_FRQAT_SHIFT 16 +#define DDR_PHY_PGCR5_FRQAT_MASK 0x00FF0000U -/*DFI Disconnect Time Period*/ +/* +* DFI Disconnect Time Period +*/ #undef DDR_PHY_PGCR5_DISCNPERIOD_DEFVAL #undef DDR_PHY_PGCR5_DISCNPERIOD_SHIFT #undef DDR_PHY_PGCR5_DISCNPERIOD_MASK -#define DDR_PHY_PGCR5_DISCNPERIOD_DEFVAL 0x01010000 -#define DDR_PHY_PGCR5_DISCNPERIOD_SHIFT 8 -#define DDR_PHY_PGCR5_DISCNPERIOD_MASK 0x0000FF00U +#define DDR_PHY_PGCR5_DISCNPERIOD_DEFVAL 0x01010000 +#define DDR_PHY_PGCR5_DISCNPERIOD_SHIFT 8 +#define DDR_PHY_PGCR5_DISCNPERIOD_MASK 0x0000FF00U -/*Receiver bias core side control*/ +/* +* Receiver bias core side control +*/ #undef DDR_PHY_PGCR5_VREF_RBCTRL_DEFVAL #undef DDR_PHY_PGCR5_VREF_RBCTRL_SHIFT #undef DDR_PHY_PGCR5_VREF_RBCTRL_MASK -#define DDR_PHY_PGCR5_VREF_RBCTRL_DEFVAL 0x01010000 -#define DDR_PHY_PGCR5_VREF_RBCTRL_SHIFT 4 -#define DDR_PHY_PGCR5_VREF_RBCTRL_MASK 0x000000F0U +#define DDR_PHY_PGCR5_VREF_RBCTRL_DEFVAL 0x01010000 +#define DDR_PHY_PGCR5_VREF_RBCTRL_SHIFT 4 +#define DDR_PHY_PGCR5_VREF_RBCTRL_MASK 0x000000F0U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_PGCR5_RESERVED_3_DEFVAL #undef DDR_PHY_PGCR5_RESERVED_3_SHIFT #undef DDR_PHY_PGCR5_RESERVED_3_MASK -#define DDR_PHY_PGCR5_RESERVED_3_DEFVAL 0x01010000 -#define DDR_PHY_PGCR5_RESERVED_3_SHIFT 3 -#define DDR_PHY_PGCR5_RESERVED_3_MASK 0x00000008U +#define DDR_PHY_PGCR5_RESERVED_3_DEFVAL 0x01010000 +#define DDR_PHY_PGCR5_RESERVED_3_SHIFT 3 +#define DDR_PHY_PGCR5_RESERVED_3_MASK 0x00000008U -/*Internal VREF generator REFSEL ragne select*/ +/* +* Internal VREF generator REFSEL ragne select +*/ #undef DDR_PHY_PGCR5_DXREFISELRANGE_DEFVAL #undef DDR_PHY_PGCR5_DXREFISELRANGE_SHIFT #undef DDR_PHY_PGCR5_DXREFISELRANGE_MASK -#define DDR_PHY_PGCR5_DXREFISELRANGE_DEFVAL 0x01010000 -#define DDR_PHY_PGCR5_DXREFISELRANGE_SHIFT 2 -#define DDR_PHY_PGCR5_DXREFISELRANGE_MASK 0x00000004U +#define DDR_PHY_PGCR5_DXREFISELRANGE_DEFVAL 0x01010000 +#define DDR_PHY_PGCR5_DXREFISELRANGE_SHIFT 2 +#define DDR_PHY_PGCR5_DXREFISELRANGE_MASK 0x00000004U -/*DDL Page Read Write select*/ +/* +* DDL Page Read Write select +*/ #undef DDR_PHY_PGCR5_DDLPGACT_DEFVAL #undef DDR_PHY_PGCR5_DDLPGACT_SHIFT #undef DDR_PHY_PGCR5_DDLPGACT_MASK -#define DDR_PHY_PGCR5_DDLPGACT_DEFVAL 0x01010000 -#define DDR_PHY_PGCR5_DDLPGACT_SHIFT 1 -#define DDR_PHY_PGCR5_DDLPGACT_MASK 0x00000002U +#define DDR_PHY_PGCR5_DDLPGACT_DEFVAL 0x01010000 +#define DDR_PHY_PGCR5_DDLPGACT_SHIFT 1 +#define DDR_PHY_PGCR5_DDLPGACT_MASK 0x00000002U -/*DDL Page Read Write select*/ +/* +* DDL Page Read Write select +*/ #undef DDR_PHY_PGCR5_DDLPGRW_DEFVAL #undef DDR_PHY_PGCR5_DDLPGRW_SHIFT #undef DDR_PHY_PGCR5_DDLPGRW_MASK -#define DDR_PHY_PGCR5_DDLPGRW_DEFVAL 0x01010000 -#define DDR_PHY_PGCR5_DDLPGRW_SHIFT 0 -#define DDR_PHY_PGCR5_DDLPGRW_MASK 0x00000001U +#define DDR_PHY_PGCR5_DDLPGRW_DEFVAL 0x01010000 +#define DDR_PHY_PGCR5_DDLPGRW_SHIFT 0 +#define DDR_PHY_PGCR5_DDLPGRW_MASK 0x00000001U -/*PLL Power-Down Time*/ +/* +* PLL Power-Down Time +*/ #undef DDR_PHY_PTR0_TPLLPD_DEFVAL #undef DDR_PHY_PTR0_TPLLPD_SHIFT #undef DDR_PHY_PTR0_TPLLPD_MASK -#define DDR_PHY_PTR0_TPLLPD_DEFVAL 0x42C21590 -#define DDR_PHY_PTR0_TPLLPD_SHIFT 21 -#define DDR_PHY_PTR0_TPLLPD_MASK 0xFFE00000U +#define DDR_PHY_PTR0_TPLLPD_DEFVAL 0x42C21590 +#define DDR_PHY_PTR0_TPLLPD_SHIFT 21 +#define DDR_PHY_PTR0_TPLLPD_MASK 0xFFE00000U -/*PLL Gear Shift Time*/ +/* +* PLL Gear Shift Time +*/ #undef DDR_PHY_PTR0_TPLLGS_DEFVAL #undef DDR_PHY_PTR0_TPLLGS_SHIFT #undef DDR_PHY_PTR0_TPLLGS_MASK -#define DDR_PHY_PTR0_TPLLGS_DEFVAL 0x42C21590 -#define DDR_PHY_PTR0_TPLLGS_SHIFT 6 -#define DDR_PHY_PTR0_TPLLGS_MASK 0x001FFFC0U +#define DDR_PHY_PTR0_TPLLGS_DEFVAL 0x42C21590 +#define DDR_PHY_PTR0_TPLLGS_SHIFT 6 +#define DDR_PHY_PTR0_TPLLGS_MASK 0x001FFFC0U -/*PHY Reset Time*/ +/* +* PHY Reset Time +*/ #undef DDR_PHY_PTR0_TPHYRST_DEFVAL #undef DDR_PHY_PTR0_TPHYRST_SHIFT #undef DDR_PHY_PTR0_TPHYRST_MASK -#define DDR_PHY_PTR0_TPHYRST_DEFVAL 0x42C21590 -#define DDR_PHY_PTR0_TPHYRST_SHIFT 0 -#define DDR_PHY_PTR0_TPHYRST_MASK 0x0000003FU +#define DDR_PHY_PTR0_TPHYRST_DEFVAL 0x42C21590 +#define DDR_PHY_PTR0_TPHYRST_SHIFT 0 +#define DDR_PHY_PTR0_TPHYRST_MASK 0x0000003FU -/*PLL Lock Time*/ +/* +* PLL Lock Time +*/ #undef DDR_PHY_PTR1_TPLLLOCK_DEFVAL #undef DDR_PHY_PTR1_TPLLLOCK_SHIFT #undef DDR_PHY_PTR1_TPLLLOCK_MASK -#define DDR_PHY_PTR1_TPLLLOCK_DEFVAL 0xD05612C0 -#define DDR_PHY_PTR1_TPLLLOCK_SHIFT 16 -#define DDR_PHY_PTR1_TPLLLOCK_MASK 0xFFFF0000U +#define DDR_PHY_PTR1_TPLLLOCK_DEFVAL 0xD05612C0 +#define DDR_PHY_PTR1_TPLLLOCK_SHIFT 16 +#define DDR_PHY_PTR1_TPLLLOCK_MASK 0xFFFF0000U -/*Reserved. Returns zeroes on reads.*/ +/* +* Reserved. Returns zeroes on reads. +*/ #undef DDR_PHY_PTR1_RESERVED_15_13_DEFVAL #undef DDR_PHY_PTR1_RESERVED_15_13_SHIFT #undef DDR_PHY_PTR1_RESERVED_15_13_MASK -#define DDR_PHY_PTR1_RESERVED_15_13_DEFVAL 0xD05612C0 -#define DDR_PHY_PTR1_RESERVED_15_13_SHIFT 13 -#define DDR_PHY_PTR1_RESERVED_15_13_MASK 0x0000E000U +#define DDR_PHY_PTR1_RESERVED_15_13_DEFVAL 0xD05612C0 +#define DDR_PHY_PTR1_RESERVED_15_13_SHIFT 13 +#define DDR_PHY_PTR1_RESERVED_15_13_MASK 0x0000E000U -/*PLL Reset Time*/ +/* +* PLL Reset Time +*/ #undef DDR_PHY_PTR1_TPLLRST_DEFVAL #undef DDR_PHY_PTR1_TPLLRST_SHIFT #undef DDR_PHY_PTR1_TPLLRST_MASK -#define DDR_PHY_PTR1_TPLLRST_DEFVAL 0xD05612C0 -#define DDR_PHY_PTR1_TPLLRST_SHIFT 0 -#define DDR_PHY_PTR1_TPLLRST_MASK 0x00001FFFU +#define DDR_PHY_PTR1_TPLLRST_DEFVAL 0xD05612C0 +#define DDR_PHY_PTR1_TPLLRST_SHIFT 0 +#define DDR_PHY_PTR1_TPLLRST_MASK 0x00001FFFU -/*Reserved. Return zeroes on reads.*/ +/* +* PLL Bypass +*/ +#undef DDR_PHY_PLLCR0_PLLBYP_DEFVAL +#undef DDR_PHY_PLLCR0_PLLBYP_SHIFT +#undef DDR_PHY_PLLCR0_PLLBYP_MASK +#define DDR_PHY_PLLCR0_PLLBYP_DEFVAL 0x001C0000 +#define DDR_PHY_PLLCR0_PLLBYP_SHIFT 31 +#define DDR_PHY_PLLCR0_PLLBYP_MASK 0x80000000U + +/* +* PLL Reset +*/ +#undef DDR_PHY_PLLCR0_PLLRST_DEFVAL +#undef DDR_PHY_PLLCR0_PLLRST_SHIFT +#undef DDR_PHY_PLLCR0_PLLRST_MASK +#define DDR_PHY_PLLCR0_PLLRST_DEFVAL 0x001C0000 +#define DDR_PHY_PLLCR0_PLLRST_SHIFT 30 +#define DDR_PHY_PLLCR0_PLLRST_MASK 0x40000000U + +/* +* PLL Power Down +*/ +#undef DDR_PHY_PLLCR0_PLLPD_DEFVAL +#undef DDR_PHY_PLLCR0_PLLPD_SHIFT +#undef DDR_PHY_PLLCR0_PLLPD_MASK +#define DDR_PHY_PLLCR0_PLLPD_DEFVAL 0x001C0000 +#define DDR_PHY_PLLCR0_PLLPD_SHIFT 29 +#define DDR_PHY_PLLCR0_PLLPD_MASK 0x20000000U + +/* +* Reference Stop Mode +*/ +#undef DDR_PHY_PLLCR0_RSTOPM_DEFVAL +#undef DDR_PHY_PLLCR0_RSTOPM_SHIFT +#undef DDR_PHY_PLLCR0_RSTOPM_MASK +#define DDR_PHY_PLLCR0_RSTOPM_DEFVAL 0x001C0000 +#define DDR_PHY_PLLCR0_RSTOPM_SHIFT 28 +#define DDR_PHY_PLLCR0_RSTOPM_MASK 0x10000000U + +/* +* PLL Frequency Select +*/ +#undef DDR_PHY_PLLCR0_FRQSEL_DEFVAL +#undef DDR_PHY_PLLCR0_FRQSEL_SHIFT +#undef DDR_PHY_PLLCR0_FRQSEL_MASK +#define DDR_PHY_PLLCR0_FRQSEL_DEFVAL 0x001C0000 +#define DDR_PHY_PLLCR0_FRQSEL_SHIFT 24 +#define DDR_PHY_PLLCR0_FRQSEL_MASK 0x0F000000U + +/* +* Relock Mode +*/ +#undef DDR_PHY_PLLCR0_RLOCKM_DEFVAL +#undef DDR_PHY_PLLCR0_RLOCKM_SHIFT +#undef DDR_PHY_PLLCR0_RLOCKM_MASK +#define DDR_PHY_PLLCR0_RLOCKM_DEFVAL 0x001C0000 +#define DDR_PHY_PLLCR0_RLOCKM_SHIFT 23 +#define DDR_PHY_PLLCR0_RLOCKM_MASK 0x00800000U + +/* +* Charge Pump Proportional Current Control +*/ +#undef DDR_PHY_PLLCR0_CPPC_DEFVAL +#undef DDR_PHY_PLLCR0_CPPC_SHIFT +#undef DDR_PHY_PLLCR0_CPPC_MASK +#define DDR_PHY_PLLCR0_CPPC_DEFVAL 0x001C0000 +#define DDR_PHY_PLLCR0_CPPC_SHIFT 17 +#define DDR_PHY_PLLCR0_CPPC_MASK 0x007E0000U + +/* +* Charge Pump Integrating Current Control +*/ +#undef DDR_PHY_PLLCR0_CPIC_DEFVAL +#undef DDR_PHY_PLLCR0_CPIC_SHIFT +#undef DDR_PHY_PLLCR0_CPIC_MASK +#define DDR_PHY_PLLCR0_CPIC_DEFVAL 0x001C0000 +#define DDR_PHY_PLLCR0_CPIC_SHIFT 13 +#define DDR_PHY_PLLCR0_CPIC_MASK 0x0001E000U + +/* +* Gear Shift +*/ +#undef DDR_PHY_PLLCR0_GSHIFT_DEFVAL +#undef DDR_PHY_PLLCR0_GSHIFT_SHIFT +#undef DDR_PHY_PLLCR0_GSHIFT_MASK +#define DDR_PHY_PLLCR0_GSHIFT_DEFVAL 0x001C0000 +#define DDR_PHY_PLLCR0_GSHIFT_SHIFT 12 +#define DDR_PHY_PLLCR0_GSHIFT_MASK 0x00001000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_PLLCR0_RESERVED_11_9_DEFVAL +#undef DDR_PHY_PLLCR0_RESERVED_11_9_SHIFT +#undef DDR_PHY_PLLCR0_RESERVED_11_9_MASK +#define DDR_PHY_PLLCR0_RESERVED_11_9_DEFVAL 0x001C0000 +#define DDR_PHY_PLLCR0_RESERVED_11_9_SHIFT 9 +#define DDR_PHY_PLLCR0_RESERVED_11_9_MASK 0x00000E00U + +/* +* Analog Test Enable +*/ +#undef DDR_PHY_PLLCR0_ATOEN_DEFVAL +#undef DDR_PHY_PLLCR0_ATOEN_SHIFT +#undef DDR_PHY_PLLCR0_ATOEN_MASK +#define DDR_PHY_PLLCR0_ATOEN_DEFVAL 0x001C0000 +#define DDR_PHY_PLLCR0_ATOEN_SHIFT 8 +#define DDR_PHY_PLLCR0_ATOEN_MASK 0x00000100U + +/* +* Analog Test Control +*/ +#undef DDR_PHY_PLLCR0_ATC_DEFVAL +#undef DDR_PHY_PLLCR0_ATC_SHIFT +#undef DDR_PHY_PLLCR0_ATC_MASK +#define DDR_PHY_PLLCR0_ATC_DEFVAL 0x001C0000 +#define DDR_PHY_PLLCR0_ATC_SHIFT 4 +#define DDR_PHY_PLLCR0_ATC_MASK 0x000000F0U + +/* +* Digital Test Control +*/ +#undef DDR_PHY_PLLCR0_DTC_DEFVAL +#undef DDR_PHY_PLLCR0_DTC_SHIFT +#undef DDR_PHY_PLLCR0_DTC_MASK +#define DDR_PHY_PLLCR0_DTC_DEFVAL 0x001C0000 +#define DDR_PHY_PLLCR0_DTC_SHIFT 0 +#define DDR_PHY_PLLCR0_DTC_MASK 0x0000000FU + +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DSGCR_RESERVED_31_28_DEFVAL #undef DDR_PHY_DSGCR_RESERVED_31_28_SHIFT #undef DDR_PHY_DSGCR_RESERVED_31_28_MASK -#define DDR_PHY_DSGCR_RESERVED_31_28_DEFVAL 0x02A04101 -#define DDR_PHY_DSGCR_RESERVED_31_28_SHIFT 28 -#define DDR_PHY_DSGCR_RESERVED_31_28_MASK 0xF0000000U +#define DDR_PHY_DSGCR_RESERVED_31_28_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_RESERVED_31_28_SHIFT 28 +#define DDR_PHY_DSGCR_RESERVED_31_28_MASK 0xF0000000U -/*When RDBI enabled, this bit is used to select RDBI CL calculation, if it is 1b1, calculation will use RDBICL, otherwise use d - fault calculation.*/ +/* +* When RDBI enabled, this bit is used to select RDBI CL calculation, if it + * is 1b1, calculation will use RDBICL, otherwise use default calculation. +*/ #undef DDR_PHY_DSGCR_RDBICLSEL_DEFVAL #undef DDR_PHY_DSGCR_RDBICLSEL_SHIFT #undef DDR_PHY_DSGCR_RDBICLSEL_MASK -#define DDR_PHY_DSGCR_RDBICLSEL_DEFVAL 0x02A04101 -#define DDR_PHY_DSGCR_RDBICLSEL_SHIFT 27 -#define DDR_PHY_DSGCR_RDBICLSEL_MASK 0x08000000U +#define DDR_PHY_DSGCR_RDBICLSEL_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_RDBICLSEL_SHIFT 27 +#define DDR_PHY_DSGCR_RDBICLSEL_MASK 0x08000000U -/*When RDBI enabled, if RDBICLSEL is asserted, RDBI CL adjust using this value.*/ +/* +* When RDBI enabled, if RDBICLSEL is asserted, RDBI CL adjust using this v + * alue. +*/ #undef DDR_PHY_DSGCR_RDBICL_DEFVAL #undef DDR_PHY_DSGCR_RDBICL_SHIFT #undef DDR_PHY_DSGCR_RDBICL_MASK -#define DDR_PHY_DSGCR_RDBICL_DEFVAL 0x02A04101 -#define DDR_PHY_DSGCR_RDBICL_SHIFT 24 -#define DDR_PHY_DSGCR_RDBICL_MASK 0x07000000U +#define DDR_PHY_DSGCR_RDBICL_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_RDBICL_SHIFT 24 +#define DDR_PHY_DSGCR_RDBICL_MASK 0x07000000U -/*PHY Impedance Update Enable*/ +/* +* PHY Impedance Update Enable +*/ #undef DDR_PHY_DSGCR_PHYZUEN_DEFVAL #undef DDR_PHY_DSGCR_PHYZUEN_SHIFT #undef DDR_PHY_DSGCR_PHYZUEN_MASK -#define DDR_PHY_DSGCR_PHYZUEN_DEFVAL 0x02A04101 -#define DDR_PHY_DSGCR_PHYZUEN_SHIFT 23 -#define DDR_PHY_DSGCR_PHYZUEN_MASK 0x00800000U +#define DDR_PHY_DSGCR_PHYZUEN_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_PHYZUEN_SHIFT 23 +#define DDR_PHY_DSGCR_PHYZUEN_MASK 0x00800000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DSGCR_RESERVED_22_DEFVAL #undef DDR_PHY_DSGCR_RESERVED_22_SHIFT #undef DDR_PHY_DSGCR_RESERVED_22_MASK -#define DDR_PHY_DSGCR_RESERVED_22_DEFVAL 0x02A04101 -#define DDR_PHY_DSGCR_RESERVED_22_SHIFT 22 -#define DDR_PHY_DSGCR_RESERVED_22_MASK 0x00400000U +#define DDR_PHY_DSGCR_RESERVED_22_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_RESERVED_22_SHIFT 22 +#define DDR_PHY_DSGCR_RESERVED_22_MASK 0x00400000U -/*SDRAM Reset Output Enable*/ +/* +* SDRAM Reset Output Enable +*/ #undef DDR_PHY_DSGCR_RSTOE_DEFVAL #undef DDR_PHY_DSGCR_RSTOE_SHIFT #undef DDR_PHY_DSGCR_RSTOE_MASK -#define DDR_PHY_DSGCR_RSTOE_DEFVAL 0x02A04101 -#define DDR_PHY_DSGCR_RSTOE_SHIFT 21 -#define DDR_PHY_DSGCR_RSTOE_MASK 0x00200000U +#define DDR_PHY_DSGCR_RSTOE_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_RSTOE_SHIFT 21 +#define DDR_PHY_DSGCR_RSTOE_MASK 0x00200000U -/*Single Data Rate Mode*/ +/* +* Single Data Rate Mode +*/ #undef DDR_PHY_DSGCR_SDRMODE_DEFVAL #undef DDR_PHY_DSGCR_SDRMODE_SHIFT #undef DDR_PHY_DSGCR_SDRMODE_MASK -#define DDR_PHY_DSGCR_SDRMODE_DEFVAL 0x02A04101 -#define DDR_PHY_DSGCR_SDRMODE_SHIFT 19 -#define DDR_PHY_DSGCR_SDRMODE_MASK 0x00180000U +#define DDR_PHY_DSGCR_SDRMODE_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_SDRMODE_SHIFT 19 +#define DDR_PHY_DSGCR_SDRMODE_MASK 0x00180000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DSGCR_RESERVED_18_DEFVAL #undef DDR_PHY_DSGCR_RESERVED_18_SHIFT #undef DDR_PHY_DSGCR_RESERVED_18_MASK -#define DDR_PHY_DSGCR_RESERVED_18_DEFVAL 0x02A04101 -#define DDR_PHY_DSGCR_RESERVED_18_SHIFT 18 -#define DDR_PHY_DSGCR_RESERVED_18_MASK 0x00040000U +#define DDR_PHY_DSGCR_RESERVED_18_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_RESERVED_18_SHIFT 18 +#define DDR_PHY_DSGCR_RESERVED_18_MASK 0x00040000U -/*ATO Analog Test Enable*/ +/* +* ATO Analog Test Enable +*/ #undef DDR_PHY_DSGCR_ATOAE_DEFVAL #undef DDR_PHY_DSGCR_ATOAE_SHIFT #undef DDR_PHY_DSGCR_ATOAE_MASK -#define DDR_PHY_DSGCR_ATOAE_DEFVAL 0x02A04101 -#define DDR_PHY_DSGCR_ATOAE_SHIFT 17 -#define DDR_PHY_DSGCR_ATOAE_MASK 0x00020000U +#define DDR_PHY_DSGCR_ATOAE_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_ATOAE_SHIFT 17 +#define DDR_PHY_DSGCR_ATOAE_MASK 0x00020000U -/*DTO Output Enable*/ +/* +* DTO Output Enable +*/ #undef DDR_PHY_DSGCR_DTOOE_DEFVAL #undef DDR_PHY_DSGCR_DTOOE_SHIFT #undef DDR_PHY_DSGCR_DTOOE_MASK -#define DDR_PHY_DSGCR_DTOOE_DEFVAL 0x02A04101 -#define DDR_PHY_DSGCR_DTOOE_SHIFT 16 -#define DDR_PHY_DSGCR_DTOOE_MASK 0x00010000U +#define DDR_PHY_DSGCR_DTOOE_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_DTOOE_SHIFT 16 +#define DDR_PHY_DSGCR_DTOOE_MASK 0x00010000U -/*DTO I/O Mode*/ +/* +* DTO I/O Mode +*/ #undef DDR_PHY_DSGCR_DTOIOM_DEFVAL #undef DDR_PHY_DSGCR_DTOIOM_SHIFT #undef DDR_PHY_DSGCR_DTOIOM_MASK -#define DDR_PHY_DSGCR_DTOIOM_DEFVAL 0x02A04101 -#define DDR_PHY_DSGCR_DTOIOM_SHIFT 15 -#define DDR_PHY_DSGCR_DTOIOM_MASK 0x00008000U +#define DDR_PHY_DSGCR_DTOIOM_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_DTOIOM_SHIFT 15 +#define DDR_PHY_DSGCR_DTOIOM_MASK 0x00008000U -/*DTO Power Down Receiver*/ +/* +* DTO Power Down Receiver +*/ #undef DDR_PHY_DSGCR_DTOPDR_DEFVAL #undef DDR_PHY_DSGCR_DTOPDR_SHIFT #undef DDR_PHY_DSGCR_DTOPDR_MASK -#define DDR_PHY_DSGCR_DTOPDR_DEFVAL 0x02A04101 -#define DDR_PHY_DSGCR_DTOPDR_SHIFT 14 -#define DDR_PHY_DSGCR_DTOPDR_MASK 0x00004000U +#define DDR_PHY_DSGCR_DTOPDR_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_DTOPDR_SHIFT 14 +#define DDR_PHY_DSGCR_DTOPDR_MASK 0x00004000U -/*Reserved. Return zeroes on reads*/ +/* +* Reserved. Return zeroes on reads +*/ #undef DDR_PHY_DSGCR_RESERVED_13_DEFVAL #undef DDR_PHY_DSGCR_RESERVED_13_SHIFT #undef DDR_PHY_DSGCR_RESERVED_13_MASK -#define DDR_PHY_DSGCR_RESERVED_13_DEFVAL 0x02A04101 -#define DDR_PHY_DSGCR_RESERVED_13_SHIFT 13 -#define DDR_PHY_DSGCR_RESERVED_13_MASK 0x00002000U +#define DDR_PHY_DSGCR_RESERVED_13_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_RESERVED_13_SHIFT 13 +#define DDR_PHY_DSGCR_RESERVED_13_MASK 0x00002000U -/*DTO On-Die Termination*/ +/* +* DTO On-Die Termination +*/ #undef DDR_PHY_DSGCR_DTOODT_DEFVAL #undef DDR_PHY_DSGCR_DTOODT_SHIFT #undef DDR_PHY_DSGCR_DTOODT_MASK -#define DDR_PHY_DSGCR_DTOODT_DEFVAL 0x02A04101 -#define DDR_PHY_DSGCR_DTOODT_SHIFT 12 -#define DDR_PHY_DSGCR_DTOODT_MASK 0x00001000U +#define DDR_PHY_DSGCR_DTOODT_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_DTOODT_SHIFT 12 +#define DDR_PHY_DSGCR_DTOODT_MASK 0x00001000U -/*PHY Update Acknowledge Delay*/ +/* +* PHY Update Acknowledge Delay +*/ #undef DDR_PHY_DSGCR_PUAD_DEFVAL #undef DDR_PHY_DSGCR_PUAD_SHIFT #undef DDR_PHY_DSGCR_PUAD_MASK -#define DDR_PHY_DSGCR_PUAD_DEFVAL 0x02A04101 -#define DDR_PHY_DSGCR_PUAD_SHIFT 6 -#define DDR_PHY_DSGCR_PUAD_MASK 0x00000FC0U +#define DDR_PHY_DSGCR_PUAD_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_PUAD_SHIFT 6 +#define DDR_PHY_DSGCR_PUAD_MASK 0x00000FC0U -/*Controller Update Acknowledge Enable*/ +/* +* Controller Update Acknowledge Enable +*/ #undef DDR_PHY_DSGCR_CUAEN_DEFVAL #undef DDR_PHY_DSGCR_CUAEN_SHIFT #undef DDR_PHY_DSGCR_CUAEN_MASK -#define DDR_PHY_DSGCR_CUAEN_DEFVAL 0x02A04101 -#define DDR_PHY_DSGCR_CUAEN_SHIFT 5 -#define DDR_PHY_DSGCR_CUAEN_MASK 0x00000020U +#define DDR_PHY_DSGCR_CUAEN_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_CUAEN_SHIFT 5 +#define DDR_PHY_DSGCR_CUAEN_MASK 0x00000020U -/*Reserved. Return zeroes on reads*/ +/* +* Reserved. Return zeroes on reads +*/ #undef DDR_PHY_DSGCR_RESERVED_4_3_DEFVAL #undef DDR_PHY_DSGCR_RESERVED_4_3_SHIFT #undef DDR_PHY_DSGCR_RESERVED_4_3_MASK -#define DDR_PHY_DSGCR_RESERVED_4_3_DEFVAL 0x02A04101 -#define DDR_PHY_DSGCR_RESERVED_4_3_SHIFT 3 -#define DDR_PHY_DSGCR_RESERVED_4_3_MASK 0x00000018U +#define DDR_PHY_DSGCR_RESERVED_4_3_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_RESERVED_4_3_SHIFT 3 +#define DDR_PHY_DSGCR_RESERVED_4_3_MASK 0x00000018U -/*Controller Impedance Update Enable*/ +/* +* Controller Impedance Update Enable +*/ #undef DDR_PHY_DSGCR_CTLZUEN_DEFVAL #undef DDR_PHY_DSGCR_CTLZUEN_SHIFT #undef DDR_PHY_DSGCR_CTLZUEN_MASK -#define DDR_PHY_DSGCR_CTLZUEN_DEFVAL 0x02A04101 -#define DDR_PHY_DSGCR_CTLZUEN_SHIFT 2 -#define DDR_PHY_DSGCR_CTLZUEN_MASK 0x00000004U +#define DDR_PHY_DSGCR_CTLZUEN_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_CTLZUEN_SHIFT 2 +#define DDR_PHY_DSGCR_CTLZUEN_MASK 0x00000004U -/*Reserved. Return zeroes on reads*/ +/* +* Reserved. Return zeroes on reads +*/ #undef DDR_PHY_DSGCR_RESERVED_1_DEFVAL #undef DDR_PHY_DSGCR_RESERVED_1_SHIFT #undef DDR_PHY_DSGCR_RESERVED_1_MASK -#define DDR_PHY_DSGCR_RESERVED_1_DEFVAL 0x02A04101 -#define DDR_PHY_DSGCR_RESERVED_1_SHIFT 1 -#define DDR_PHY_DSGCR_RESERVED_1_MASK 0x00000002U +#define DDR_PHY_DSGCR_RESERVED_1_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_RESERVED_1_SHIFT 1 +#define DDR_PHY_DSGCR_RESERVED_1_MASK 0x00000002U -/*PHY Update Request Enable*/ +/* +* PHY Update Request Enable +*/ #undef DDR_PHY_DSGCR_PUREN_DEFVAL #undef DDR_PHY_DSGCR_PUREN_SHIFT #undef DDR_PHY_DSGCR_PUREN_MASK -#define DDR_PHY_DSGCR_PUREN_DEFVAL 0x02A04101 -#define DDR_PHY_DSGCR_PUREN_SHIFT 0 -#define DDR_PHY_DSGCR_PUREN_MASK 0x00000001U +#define DDR_PHY_DSGCR_PUREN_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_PUREN_SHIFT 0 +#define DDR_PHY_DSGCR_PUREN_MASK 0x00000001U -/*DDR4 Gear Down Timing.*/ +/* +* General Purpose Register 0 +*/ +#undef DDR_PHY_GPR0_GPR0_DEFVAL +#undef DDR_PHY_GPR0_GPR0_SHIFT +#undef DDR_PHY_GPR0_GPR0_MASK +#define DDR_PHY_GPR0_GPR0_DEFVAL +#define DDR_PHY_GPR0_GPR0_SHIFT 0 +#define DDR_PHY_GPR0_GPR0_MASK 0xFFFFFFFFU + +/* +* DDR4 Gear Down Timing. +*/ #undef DDR_PHY_DCR_GEARDN_DEFVAL #undef DDR_PHY_DCR_GEARDN_SHIFT #undef DDR_PHY_DCR_GEARDN_MASK -#define DDR_PHY_DCR_GEARDN_DEFVAL 0x0000040D -#define DDR_PHY_DCR_GEARDN_SHIFT 31 -#define DDR_PHY_DCR_GEARDN_MASK 0x80000000U +#define DDR_PHY_DCR_GEARDN_DEFVAL 0x0000040D +#define DDR_PHY_DCR_GEARDN_SHIFT 31 +#define DDR_PHY_DCR_GEARDN_MASK 0x80000000U -/*Un-used Bank Group*/ +/* +* Un-used Bank Group +*/ #undef DDR_PHY_DCR_UBG_DEFVAL #undef DDR_PHY_DCR_UBG_SHIFT #undef DDR_PHY_DCR_UBG_MASK -#define DDR_PHY_DCR_UBG_DEFVAL 0x0000040D -#define DDR_PHY_DCR_UBG_SHIFT 30 -#define DDR_PHY_DCR_UBG_MASK 0x40000000U +#define DDR_PHY_DCR_UBG_DEFVAL 0x0000040D +#define DDR_PHY_DCR_UBG_SHIFT 30 +#define DDR_PHY_DCR_UBG_MASK 0x40000000U -/*Un-buffered DIMM Address Mirroring*/ +/* +* Un-buffered DIMM Address Mirroring +*/ #undef DDR_PHY_DCR_UDIMM_DEFVAL #undef DDR_PHY_DCR_UDIMM_SHIFT #undef DDR_PHY_DCR_UDIMM_MASK -#define DDR_PHY_DCR_UDIMM_DEFVAL 0x0000040D -#define DDR_PHY_DCR_UDIMM_SHIFT 29 -#define DDR_PHY_DCR_UDIMM_MASK 0x20000000U +#define DDR_PHY_DCR_UDIMM_DEFVAL 0x0000040D +#define DDR_PHY_DCR_UDIMM_SHIFT 29 +#define DDR_PHY_DCR_UDIMM_MASK 0x20000000U -/*DDR 2T Timing*/ +/* +* DDR 2T Timing +*/ #undef DDR_PHY_DCR_DDR2T_DEFVAL #undef DDR_PHY_DCR_DDR2T_SHIFT #undef DDR_PHY_DCR_DDR2T_MASK -#define DDR_PHY_DCR_DDR2T_DEFVAL 0x0000040D -#define DDR_PHY_DCR_DDR2T_SHIFT 28 -#define DDR_PHY_DCR_DDR2T_MASK 0x10000000U +#define DDR_PHY_DCR_DDR2T_DEFVAL 0x0000040D +#define DDR_PHY_DCR_DDR2T_SHIFT 28 +#define DDR_PHY_DCR_DDR2T_MASK 0x10000000U -/*No Simultaneous Rank Access*/ +/* +* No Simultaneous Rank Access +*/ #undef DDR_PHY_DCR_NOSRA_DEFVAL #undef DDR_PHY_DCR_NOSRA_SHIFT #undef DDR_PHY_DCR_NOSRA_MASK -#define DDR_PHY_DCR_NOSRA_DEFVAL 0x0000040D -#define DDR_PHY_DCR_NOSRA_SHIFT 27 -#define DDR_PHY_DCR_NOSRA_MASK 0x08000000U +#define DDR_PHY_DCR_NOSRA_DEFVAL 0x0000040D +#define DDR_PHY_DCR_NOSRA_SHIFT 27 +#define DDR_PHY_DCR_NOSRA_MASK 0x08000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DCR_RESERVED_26_18_DEFVAL #undef DDR_PHY_DCR_RESERVED_26_18_SHIFT #undef DDR_PHY_DCR_RESERVED_26_18_MASK -#define DDR_PHY_DCR_RESERVED_26_18_DEFVAL 0x0000040D -#define DDR_PHY_DCR_RESERVED_26_18_SHIFT 18 -#define DDR_PHY_DCR_RESERVED_26_18_MASK 0x07FC0000U +#define DDR_PHY_DCR_RESERVED_26_18_DEFVAL 0x0000040D +#define DDR_PHY_DCR_RESERVED_26_18_SHIFT 18 +#define DDR_PHY_DCR_RESERVED_26_18_MASK 0x07FC0000U -/*Byte Mask*/ +/* +* Byte Mask +*/ #undef DDR_PHY_DCR_BYTEMASK_DEFVAL #undef DDR_PHY_DCR_BYTEMASK_SHIFT #undef DDR_PHY_DCR_BYTEMASK_MASK -#define DDR_PHY_DCR_BYTEMASK_DEFVAL 0x0000040D -#define DDR_PHY_DCR_BYTEMASK_SHIFT 10 -#define DDR_PHY_DCR_BYTEMASK_MASK 0x0003FC00U +#define DDR_PHY_DCR_BYTEMASK_DEFVAL 0x0000040D +#define DDR_PHY_DCR_BYTEMASK_SHIFT 10 +#define DDR_PHY_DCR_BYTEMASK_MASK 0x0003FC00U -/*DDR Type*/ +/* +* DDR Type +*/ #undef DDR_PHY_DCR_DDRTYPE_DEFVAL #undef DDR_PHY_DCR_DDRTYPE_SHIFT #undef DDR_PHY_DCR_DDRTYPE_MASK -#define DDR_PHY_DCR_DDRTYPE_DEFVAL 0x0000040D -#define DDR_PHY_DCR_DDRTYPE_SHIFT 8 -#define DDR_PHY_DCR_DDRTYPE_MASK 0x00000300U +#define DDR_PHY_DCR_DDRTYPE_DEFVAL 0x0000040D +#define DDR_PHY_DCR_DDRTYPE_SHIFT 8 +#define DDR_PHY_DCR_DDRTYPE_MASK 0x00000300U -/*Multi-Purpose Register (MPR) DQ (DDR3 Only)*/ +/* +* Multi-Purpose Register (MPR) DQ (DDR3 Only) +*/ #undef DDR_PHY_DCR_MPRDQ_DEFVAL #undef DDR_PHY_DCR_MPRDQ_SHIFT #undef DDR_PHY_DCR_MPRDQ_MASK -#define DDR_PHY_DCR_MPRDQ_DEFVAL 0x0000040D -#define DDR_PHY_DCR_MPRDQ_SHIFT 7 -#define DDR_PHY_DCR_MPRDQ_MASK 0x00000080U +#define DDR_PHY_DCR_MPRDQ_DEFVAL 0x0000040D +#define DDR_PHY_DCR_MPRDQ_SHIFT 7 +#define DDR_PHY_DCR_MPRDQ_MASK 0x00000080U -/*Primary DQ (DDR3 Only)*/ +/* +* Primary DQ (DDR3 Only) +*/ #undef DDR_PHY_DCR_PDQ_DEFVAL #undef DDR_PHY_DCR_PDQ_SHIFT #undef DDR_PHY_DCR_PDQ_MASK -#define DDR_PHY_DCR_PDQ_DEFVAL 0x0000040D -#define DDR_PHY_DCR_PDQ_SHIFT 4 -#define DDR_PHY_DCR_PDQ_MASK 0x00000070U +#define DDR_PHY_DCR_PDQ_DEFVAL 0x0000040D +#define DDR_PHY_DCR_PDQ_SHIFT 4 +#define DDR_PHY_DCR_PDQ_MASK 0x00000070U -/*DDR 8-Bank*/ +/* +* DDR 8-Bank +*/ #undef DDR_PHY_DCR_DDR8BNK_DEFVAL #undef DDR_PHY_DCR_DDR8BNK_SHIFT #undef DDR_PHY_DCR_DDR8BNK_MASK -#define DDR_PHY_DCR_DDR8BNK_DEFVAL 0x0000040D -#define DDR_PHY_DCR_DDR8BNK_SHIFT 3 -#define DDR_PHY_DCR_DDR8BNK_MASK 0x00000008U +#define DDR_PHY_DCR_DDR8BNK_DEFVAL 0x0000040D +#define DDR_PHY_DCR_DDR8BNK_SHIFT 3 +#define DDR_PHY_DCR_DDR8BNK_MASK 0x00000008U -/*DDR Mode*/ +/* +* DDR Mode +*/ #undef DDR_PHY_DCR_DDRMD_DEFVAL #undef DDR_PHY_DCR_DDRMD_SHIFT #undef DDR_PHY_DCR_DDRMD_MASK -#define DDR_PHY_DCR_DDRMD_DEFVAL 0x0000040D -#define DDR_PHY_DCR_DDRMD_SHIFT 0 -#define DDR_PHY_DCR_DDRMD_MASK 0x00000007U +#define DDR_PHY_DCR_DDRMD_DEFVAL 0x0000040D +#define DDR_PHY_DCR_DDRMD_SHIFT 0 +#define DDR_PHY_DCR_DDRMD_MASK 0x00000007U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR0_RESERVED_31_29_DEFVAL #undef DDR_PHY_DTPR0_RESERVED_31_29_SHIFT #undef DDR_PHY_DTPR0_RESERVED_31_29_MASK -#define DDR_PHY_DTPR0_RESERVED_31_29_DEFVAL 0x105A2D08 -#define DDR_PHY_DTPR0_RESERVED_31_29_SHIFT 29 -#define DDR_PHY_DTPR0_RESERVED_31_29_MASK 0xE0000000U +#define DDR_PHY_DTPR0_RESERVED_31_29_DEFVAL 0x105A2D08 +#define DDR_PHY_DTPR0_RESERVED_31_29_SHIFT 29 +#define DDR_PHY_DTPR0_RESERVED_31_29_MASK 0xE0000000U -/*Activate to activate command delay (different banks)*/ +/* +* Activate to activate command delay (different banks) +*/ #undef DDR_PHY_DTPR0_TRRD_DEFVAL #undef DDR_PHY_DTPR0_TRRD_SHIFT #undef DDR_PHY_DTPR0_TRRD_MASK -#define DDR_PHY_DTPR0_TRRD_DEFVAL 0x105A2D08 -#define DDR_PHY_DTPR0_TRRD_SHIFT 24 -#define DDR_PHY_DTPR0_TRRD_MASK 0x1F000000U +#define DDR_PHY_DTPR0_TRRD_DEFVAL 0x105A2D08 +#define DDR_PHY_DTPR0_TRRD_SHIFT 24 +#define DDR_PHY_DTPR0_TRRD_MASK 0x1F000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR0_RESERVED_23_DEFVAL #undef DDR_PHY_DTPR0_RESERVED_23_SHIFT #undef DDR_PHY_DTPR0_RESERVED_23_MASK -#define DDR_PHY_DTPR0_RESERVED_23_DEFVAL 0x105A2D08 -#define DDR_PHY_DTPR0_RESERVED_23_SHIFT 23 -#define DDR_PHY_DTPR0_RESERVED_23_MASK 0x00800000U +#define DDR_PHY_DTPR0_RESERVED_23_DEFVAL 0x105A2D08 +#define DDR_PHY_DTPR0_RESERVED_23_SHIFT 23 +#define DDR_PHY_DTPR0_RESERVED_23_MASK 0x00800000U -/*Activate to precharge command delay*/ +/* +* Activate to precharge command delay +*/ #undef DDR_PHY_DTPR0_TRAS_DEFVAL #undef DDR_PHY_DTPR0_TRAS_SHIFT #undef DDR_PHY_DTPR0_TRAS_MASK -#define DDR_PHY_DTPR0_TRAS_DEFVAL 0x105A2D08 -#define DDR_PHY_DTPR0_TRAS_SHIFT 16 -#define DDR_PHY_DTPR0_TRAS_MASK 0x007F0000U +#define DDR_PHY_DTPR0_TRAS_DEFVAL 0x105A2D08 +#define DDR_PHY_DTPR0_TRAS_SHIFT 16 +#define DDR_PHY_DTPR0_TRAS_MASK 0x007F0000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR0_RESERVED_15_DEFVAL #undef DDR_PHY_DTPR0_RESERVED_15_SHIFT #undef DDR_PHY_DTPR0_RESERVED_15_MASK -#define DDR_PHY_DTPR0_RESERVED_15_DEFVAL 0x105A2D08 -#define DDR_PHY_DTPR0_RESERVED_15_SHIFT 15 -#define DDR_PHY_DTPR0_RESERVED_15_MASK 0x00008000U +#define DDR_PHY_DTPR0_RESERVED_15_DEFVAL 0x105A2D08 +#define DDR_PHY_DTPR0_RESERVED_15_SHIFT 15 +#define DDR_PHY_DTPR0_RESERVED_15_MASK 0x00008000U -/*Precharge command period*/ +/* +* Precharge command period +*/ #undef DDR_PHY_DTPR0_TRP_DEFVAL #undef DDR_PHY_DTPR0_TRP_SHIFT #undef DDR_PHY_DTPR0_TRP_MASK -#define DDR_PHY_DTPR0_TRP_DEFVAL 0x105A2D08 -#define DDR_PHY_DTPR0_TRP_SHIFT 8 -#define DDR_PHY_DTPR0_TRP_MASK 0x00007F00U +#define DDR_PHY_DTPR0_TRP_DEFVAL 0x105A2D08 +#define DDR_PHY_DTPR0_TRP_SHIFT 8 +#define DDR_PHY_DTPR0_TRP_MASK 0x00007F00U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR0_RESERVED_7_5_DEFVAL #undef DDR_PHY_DTPR0_RESERVED_7_5_SHIFT #undef DDR_PHY_DTPR0_RESERVED_7_5_MASK -#define DDR_PHY_DTPR0_RESERVED_7_5_DEFVAL 0x105A2D08 -#define DDR_PHY_DTPR0_RESERVED_7_5_SHIFT 5 -#define DDR_PHY_DTPR0_RESERVED_7_5_MASK 0x000000E0U +#define DDR_PHY_DTPR0_RESERVED_7_5_DEFVAL 0x105A2D08 +#define DDR_PHY_DTPR0_RESERVED_7_5_SHIFT 5 +#define DDR_PHY_DTPR0_RESERVED_7_5_MASK 0x000000E0U -/*Internal read to precharge command delay*/ +/* +* Internal read to precharge command delay +*/ #undef DDR_PHY_DTPR0_TRTP_DEFVAL #undef DDR_PHY_DTPR0_TRTP_SHIFT #undef DDR_PHY_DTPR0_TRTP_MASK -#define DDR_PHY_DTPR0_TRTP_DEFVAL 0x105A2D08 -#define DDR_PHY_DTPR0_TRTP_SHIFT 0 -#define DDR_PHY_DTPR0_TRTP_MASK 0x0000001FU +#define DDR_PHY_DTPR0_TRTP_DEFVAL 0x105A2D08 +#define DDR_PHY_DTPR0_TRTP_SHIFT 0 +#define DDR_PHY_DTPR0_TRTP_MASK 0x0000001FU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR1_RESERVED_31_DEFVAL #undef DDR_PHY_DTPR1_RESERVED_31_SHIFT #undef DDR_PHY_DTPR1_RESERVED_31_MASK -#define DDR_PHY_DTPR1_RESERVED_31_DEFVAL 0x5656041E -#define DDR_PHY_DTPR1_RESERVED_31_SHIFT 31 -#define DDR_PHY_DTPR1_RESERVED_31_MASK 0x80000000U +#define DDR_PHY_DTPR1_RESERVED_31_DEFVAL 0x5656041E +#define DDR_PHY_DTPR1_RESERVED_31_SHIFT 31 +#define DDR_PHY_DTPR1_RESERVED_31_MASK 0x80000000U -/*Minimum delay from when write leveling mode is programmed to the first DQS/DQS# rising edge.*/ +/* +* Minimum delay from when write leveling mode is programmed to the first D + * QS/DQS# rising edge. +*/ #undef DDR_PHY_DTPR1_TWLMRD_DEFVAL #undef DDR_PHY_DTPR1_TWLMRD_SHIFT #undef DDR_PHY_DTPR1_TWLMRD_MASK -#define DDR_PHY_DTPR1_TWLMRD_DEFVAL 0x5656041E -#define DDR_PHY_DTPR1_TWLMRD_SHIFT 24 -#define DDR_PHY_DTPR1_TWLMRD_MASK 0x7F000000U +#define DDR_PHY_DTPR1_TWLMRD_DEFVAL 0x5656041E +#define DDR_PHY_DTPR1_TWLMRD_SHIFT 24 +#define DDR_PHY_DTPR1_TWLMRD_MASK 0x7F000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR1_RESERVED_23_DEFVAL #undef DDR_PHY_DTPR1_RESERVED_23_SHIFT #undef DDR_PHY_DTPR1_RESERVED_23_MASK -#define DDR_PHY_DTPR1_RESERVED_23_DEFVAL 0x5656041E -#define DDR_PHY_DTPR1_RESERVED_23_SHIFT 23 -#define DDR_PHY_DTPR1_RESERVED_23_MASK 0x00800000U +#define DDR_PHY_DTPR1_RESERVED_23_DEFVAL 0x5656041E +#define DDR_PHY_DTPR1_RESERVED_23_SHIFT 23 +#define DDR_PHY_DTPR1_RESERVED_23_MASK 0x00800000U -/*4-bank activate period*/ +/* +* 4-bank activate period +*/ #undef DDR_PHY_DTPR1_TFAW_DEFVAL #undef DDR_PHY_DTPR1_TFAW_SHIFT #undef DDR_PHY_DTPR1_TFAW_MASK -#define DDR_PHY_DTPR1_TFAW_DEFVAL 0x5656041E -#define DDR_PHY_DTPR1_TFAW_SHIFT 16 -#define DDR_PHY_DTPR1_TFAW_MASK 0x007F0000U +#define DDR_PHY_DTPR1_TFAW_DEFVAL 0x5656041E +#define DDR_PHY_DTPR1_TFAW_SHIFT 16 +#define DDR_PHY_DTPR1_TFAW_MASK 0x007F0000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR1_RESERVED_15_11_DEFVAL #undef DDR_PHY_DTPR1_RESERVED_15_11_SHIFT #undef DDR_PHY_DTPR1_RESERVED_15_11_MASK -#define DDR_PHY_DTPR1_RESERVED_15_11_DEFVAL 0x5656041E -#define DDR_PHY_DTPR1_RESERVED_15_11_SHIFT 11 -#define DDR_PHY_DTPR1_RESERVED_15_11_MASK 0x0000F800U +#define DDR_PHY_DTPR1_RESERVED_15_11_DEFVAL 0x5656041E +#define DDR_PHY_DTPR1_RESERVED_15_11_SHIFT 11 +#define DDR_PHY_DTPR1_RESERVED_15_11_MASK 0x0000F800U -/*Load mode update delay (DDR4 and DDR3 only)*/ +/* +* Load mode update delay (DDR4 and DDR3 only) +*/ #undef DDR_PHY_DTPR1_TMOD_DEFVAL #undef DDR_PHY_DTPR1_TMOD_SHIFT #undef DDR_PHY_DTPR1_TMOD_MASK -#define DDR_PHY_DTPR1_TMOD_DEFVAL 0x5656041E -#define DDR_PHY_DTPR1_TMOD_SHIFT 8 -#define DDR_PHY_DTPR1_TMOD_MASK 0x00000700U +#define DDR_PHY_DTPR1_TMOD_DEFVAL 0x5656041E +#define DDR_PHY_DTPR1_TMOD_SHIFT 8 +#define DDR_PHY_DTPR1_TMOD_MASK 0x00000700U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR1_RESERVED_7_5_DEFVAL #undef DDR_PHY_DTPR1_RESERVED_7_5_SHIFT #undef DDR_PHY_DTPR1_RESERVED_7_5_MASK -#define DDR_PHY_DTPR1_RESERVED_7_5_DEFVAL 0x5656041E -#define DDR_PHY_DTPR1_RESERVED_7_5_SHIFT 5 -#define DDR_PHY_DTPR1_RESERVED_7_5_MASK 0x000000E0U +#define DDR_PHY_DTPR1_RESERVED_7_5_DEFVAL 0x5656041E +#define DDR_PHY_DTPR1_RESERVED_7_5_SHIFT 5 +#define DDR_PHY_DTPR1_RESERVED_7_5_MASK 0x000000E0U -/*Load mode cycle time*/ +/* +* Load mode cycle time +*/ #undef DDR_PHY_DTPR1_TMRD_DEFVAL #undef DDR_PHY_DTPR1_TMRD_SHIFT #undef DDR_PHY_DTPR1_TMRD_MASK -#define DDR_PHY_DTPR1_TMRD_DEFVAL 0x5656041E -#define DDR_PHY_DTPR1_TMRD_SHIFT 0 -#define DDR_PHY_DTPR1_TMRD_MASK 0x0000001FU +#define DDR_PHY_DTPR1_TMRD_DEFVAL 0x5656041E +#define DDR_PHY_DTPR1_TMRD_SHIFT 0 +#define DDR_PHY_DTPR1_TMRD_MASK 0x0000001FU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR2_RESERVED_31_29_DEFVAL #undef DDR_PHY_DTPR2_RESERVED_31_29_SHIFT #undef DDR_PHY_DTPR2_RESERVED_31_29_MASK -#define DDR_PHY_DTPR2_RESERVED_31_29_DEFVAL 0x000B01D0 -#define DDR_PHY_DTPR2_RESERVED_31_29_SHIFT 29 -#define DDR_PHY_DTPR2_RESERVED_31_29_MASK 0xE0000000U +#define DDR_PHY_DTPR2_RESERVED_31_29_DEFVAL 0x000B01D0 +#define DDR_PHY_DTPR2_RESERVED_31_29_SHIFT 29 +#define DDR_PHY_DTPR2_RESERVED_31_29_MASK 0xE0000000U -/*Read to Write command delay. Valid values are*/ +/* +* Read to Write command delay. Valid values are +*/ #undef DDR_PHY_DTPR2_TRTW_DEFVAL #undef DDR_PHY_DTPR2_TRTW_SHIFT #undef DDR_PHY_DTPR2_TRTW_MASK -#define DDR_PHY_DTPR2_TRTW_DEFVAL 0x000B01D0 -#define DDR_PHY_DTPR2_TRTW_SHIFT 28 -#define DDR_PHY_DTPR2_TRTW_MASK 0x10000000U +#define DDR_PHY_DTPR2_TRTW_DEFVAL 0x000B01D0 +#define DDR_PHY_DTPR2_TRTW_SHIFT 28 +#define DDR_PHY_DTPR2_TRTW_MASK 0x10000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR2_RESERVED_27_25_DEFVAL #undef DDR_PHY_DTPR2_RESERVED_27_25_SHIFT #undef DDR_PHY_DTPR2_RESERVED_27_25_MASK -#define DDR_PHY_DTPR2_RESERVED_27_25_DEFVAL 0x000B01D0 -#define DDR_PHY_DTPR2_RESERVED_27_25_SHIFT 25 -#define DDR_PHY_DTPR2_RESERVED_27_25_MASK 0x0E000000U +#define DDR_PHY_DTPR2_RESERVED_27_25_DEFVAL 0x000B01D0 +#define DDR_PHY_DTPR2_RESERVED_27_25_SHIFT 25 +#define DDR_PHY_DTPR2_RESERVED_27_25_MASK 0x0E000000U -/*Read to ODT delay (DDR3 only)*/ +/* +* Read to ODT delay (DDR3 only) +*/ #undef DDR_PHY_DTPR2_TRTODT_DEFVAL #undef DDR_PHY_DTPR2_TRTODT_SHIFT #undef DDR_PHY_DTPR2_TRTODT_MASK -#define DDR_PHY_DTPR2_TRTODT_DEFVAL 0x000B01D0 -#define DDR_PHY_DTPR2_TRTODT_SHIFT 24 -#define DDR_PHY_DTPR2_TRTODT_MASK 0x01000000U +#define DDR_PHY_DTPR2_TRTODT_DEFVAL 0x000B01D0 +#define DDR_PHY_DTPR2_TRTODT_SHIFT 24 +#define DDR_PHY_DTPR2_TRTODT_MASK 0x01000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR2_RESERVED_23_20_DEFVAL #undef DDR_PHY_DTPR2_RESERVED_23_20_SHIFT #undef DDR_PHY_DTPR2_RESERVED_23_20_MASK -#define DDR_PHY_DTPR2_RESERVED_23_20_DEFVAL 0x000B01D0 -#define DDR_PHY_DTPR2_RESERVED_23_20_SHIFT 20 -#define DDR_PHY_DTPR2_RESERVED_23_20_MASK 0x00F00000U +#define DDR_PHY_DTPR2_RESERVED_23_20_DEFVAL 0x000B01D0 +#define DDR_PHY_DTPR2_RESERVED_23_20_SHIFT 20 +#define DDR_PHY_DTPR2_RESERVED_23_20_MASK 0x00F00000U -/*CKE minimum pulse width*/ +/* +* CKE minimum pulse width +*/ #undef DDR_PHY_DTPR2_TCKE_DEFVAL #undef DDR_PHY_DTPR2_TCKE_SHIFT #undef DDR_PHY_DTPR2_TCKE_MASK -#define DDR_PHY_DTPR2_TCKE_DEFVAL 0x000B01D0 -#define DDR_PHY_DTPR2_TCKE_SHIFT 16 -#define DDR_PHY_DTPR2_TCKE_MASK 0x000F0000U +#define DDR_PHY_DTPR2_TCKE_DEFVAL 0x000B01D0 +#define DDR_PHY_DTPR2_TCKE_SHIFT 16 +#define DDR_PHY_DTPR2_TCKE_MASK 0x000F0000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR2_RESERVED_15_10_DEFVAL #undef DDR_PHY_DTPR2_RESERVED_15_10_SHIFT #undef DDR_PHY_DTPR2_RESERVED_15_10_MASK -#define DDR_PHY_DTPR2_RESERVED_15_10_DEFVAL 0x000B01D0 -#define DDR_PHY_DTPR2_RESERVED_15_10_SHIFT 10 -#define DDR_PHY_DTPR2_RESERVED_15_10_MASK 0x0000FC00U +#define DDR_PHY_DTPR2_RESERVED_15_10_DEFVAL 0x000B01D0 +#define DDR_PHY_DTPR2_RESERVED_15_10_SHIFT 10 +#define DDR_PHY_DTPR2_RESERVED_15_10_MASK 0x0000FC00U -/*Self refresh exit delay*/ +/* +* Self refresh exit delay +*/ #undef DDR_PHY_DTPR2_TXS_DEFVAL #undef DDR_PHY_DTPR2_TXS_SHIFT #undef DDR_PHY_DTPR2_TXS_MASK -#define DDR_PHY_DTPR2_TXS_DEFVAL 0x000B01D0 -#define DDR_PHY_DTPR2_TXS_SHIFT 0 -#define DDR_PHY_DTPR2_TXS_MASK 0x000003FFU +#define DDR_PHY_DTPR2_TXS_DEFVAL 0x000B01D0 +#define DDR_PHY_DTPR2_TXS_SHIFT 0 +#define DDR_PHY_DTPR2_TXS_MASK 0x000003FFU -/*ODT turn-off delay extension*/ +/* +* ODT turn-off delay extension +*/ #undef DDR_PHY_DTPR3_TOFDX_DEFVAL #undef DDR_PHY_DTPR3_TOFDX_SHIFT #undef DDR_PHY_DTPR3_TOFDX_MASK -#define DDR_PHY_DTPR3_TOFDX_DEFVAL 0x02000804 -#define DDR_PHY_DTPR3_TOFDX_SHIFT 29 -#define DDR_PHY_DTPR3_TOFDX_MASK 0xE0000000U +#define DDR_PHY_DTPR3_TOFDX_DEFVAL 0x02000804 +#define DDR_PHY_DTPR3_TOFDX_SHIFT 29 +#define DDR_PHY_DTPR3_TOFDX_MASK 0xE0000000U -/*Read to read and write to write command delay*/ +/* +* Read to read and write to write command delay +*/ #undef DDR_PHY_DTPR3_TCCD_DEFVAL #undef DDR_PHY_DTPR3_TCCD_SHIFT #undef DDR_PHY_DTPR3_TCCD_MASK -#define DDR_PHY_DTPR3_TCCD_DEFVAL 0x02000804 -#define DDR_PHY_DTPR3_TCCD_SHIFT 26 -#define DDR_PHY_DTPR3_TCCD_MASK 0x1C000000U +#define DDR_PHY_DTPR3_TCCD_DEFVAL 0x02000804 +#define DDR_PHY_DTPR3_TCCD_SHIFT 26 +#define DDR_PHY_DTPR3_TCCD_MASK 0x1C000000U -/*DLL locking time*/ +/* +* DLL locking time +*/ #undef DDR_PHY_DTPR3_TDLLK_DEFVAL #undef DDR_PHY_DTPR3_TDLLK_SHIFT #undef DDR_PHY_DTPR3_TDLLK_MASK -#define DDR_PHY_DTPR3_TDLLK_DEFVAL 0x02000804 -#define DDR_PHY_DTPR3_TDLLK_SHIFT 16 -#define DDR_PHY_DTPR3_TDLLK_MASK 0x03FF0000U +#define DDR_PHY_DTPR3_TDLLK_DEFVAL 0x02000804 +#define DDR_PHY_DTPR3_TDLLK_SHIFT 16 +#define DDR_PHY_DTPR3_TDLLK_MASK 0x03FF0000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR3_RESERVED_15_12_DEFVAL #undef DDR_PHY_DTPR3_RESERVED_15_12_SHIFT #undef DDR_PHY_DTPR3_RESERVED_15_12_MASK -#define DDR_PHY_DTPR3_RESERVED_15_12_DEFVAL 0x02000804 -#define DDR_PHY_DTPR3_RESERVED_15_12_SHIFT 12 -#define DDR_PHY_DTPR3_RESERVED_15_12_MASK 0x0000F000U +#define DDR_PHY_DTPR3_RESERVED_15_12_DEFVAL 0x02000804 +#define DDR_PHY_DTPR3_RESERVED_15_12_SHIFT 12 +#define DDR_PHY_DTPR3_RESERVED_15_12_MASK 0x0000F000U -/*Maximum DQS output access time from CK/CK# (LPDDR2/3 only)*/ +/* +* Maximum DQS output access time from CK/CK# (LPDDR2/3 only) +*/ #undef DDR_PHY_DTPR3_TDQSCKMAX_DEFVAL #undef DDR_PHY_DTPR3_TDQSCKMAX_SHIFT #undef DDR_PHY_DTPR3_TDQSCKMAX_MASK -#define DDR_PHY_DTPR3_TDQSCKMAX_DEFVAL 0x02000804 -#define DDR_PHY_DTPR3_TDQSCKMAX_SHIFT 8 -#define DDR_PHY_DTPR3_TDQSCKMAX_MASK 0x00000F00U +#define DDR_PHY_DTPR3_TDQSCKMAX_DEFVAL 0x02000804 +#define DDR_PHY_DTPR3_TDQSCKMAX_SHIFT 8 +#define DDR_PHY_DTPR3_TDQSCKMAX_MASK 0x00000F00U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR3_RESERVED_7_3_DEFVAL #undef DDR_PHY_DTPR3_RESERVED_7_3_SHIFT #undef DDR_PHY_DTPR3_RESERVED_7_3_MASK -#define DDR_PHY_DTPR3_RESERVED_7_3_DEFVAL 0x02000804 -#define DDR_PHY_DTPR3_RESERVED_7_3_SHIFT 3 -#define DDR_PHY_DTPR3_RESERVED_7_3_MASK 0x000000F8U +#define DDR_PHY_DTPR3_RESERVED_7_3_DEFVAL 0x02000804 +#define DDR_PHY_DTPR3_RESERVED_7_3_SHIFT 3 +#define DDR_PHY_DTPR3_RESERVED_7_3_MASK 0x000000F8U -/*DQS output access time from CK/CK# (LPDDR2/3 only)*/ +/* +* DQS output access time from CK/CK# (LPDDR2/3 only) +*/ #undef DDR_PHY_DTPR3_TDQSCK_DEFVAL #undef DDR_PHY_DTPR3_TDQSCK_SHIFT #undef DDR_PHY_DTPR3_TDQSCK_MASK -#define DDR_PHY_DTPR3_TDQSCK_DEFVAL 0x02000804 -#define DDR_PHY_DTPR3_TDQSCK_SHIFT 0 -#define DDR_PHY_DTPR3_TDQSCK_MASK 0x00000007U +#define DDR_PHY_DTPR3_TDQSCK_DEFVAL 0x02000804 +#define DDR_PHY_DTPR3_TDQSCK_SHIFT 0 +#define DDR_PHY_DTPR3_TDQSCK_MASK 0x00000007U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR4_RESERVED_31_30_DEFVAL #undef DDR_PHY_DTPR4_RESERVED_31_30_SHIFT #undef DDR_PHY_DTPR4_RESERVED_31_30_MASK -#define DDR_PHY_DTPR4_RESERVED_31_30_DEFVAL 0x01C02B10 -#define DDR_PHY_DTPR4_RESERVED_31_30_SHIFT 30 -#define DDR_PHY_DTPR4_RESERVED_31_30_MASK 0xC0000000U +#define DDR_PHY_DTPR4_RESERVED_31_30_DEFVAL 0x01C02B10 +#define DDR_PHY_DTPR4_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DTPR4_RESERVED_31_30_MASK 0xC0000000U -/*ODT turn-on/turn-off delays (DDR2 only)*/ +/* +* ODT turn-on/turn-off delays (DDR2 only) +*/ #undef DDR_PHY_DTPR4_TAOND_TAOFD_DEFVAL #undef DDR_PHY_DTPR4_TAOND_TAOFD_SHIFT #undef DDR_PHY_DTPR4_TAOND_TAOFD_MASK -#define DDR_PHY_DTPR4_TAOND_TAOFD_DEFVAL 0x01C02B10 -#define DDR_PHY_DTPR4_TAOND_TAOFD_SHIFT 28 -#define DDR_PHY_DTPR4_TAOND_TAOFD_MASK 0x30000000U +#define DDR_PHY_DTPR4_TAOND_TAOFD_DEFVAL 0x01C02B10 +#define DDR_PHY_DTPR4_TAOND_TAOFD_SHIFT 28 +#define DDR_PHY_DTPR4_TAOND_TAOFD_MASK 0x30000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR4_RESERVED_27_26_DEFVAL #undef DDR_PHY_DTPR4_RESERVED_27_26_SHIFT #undef DDR_PHY_DTPR4_RESERVED_27_26_MASK -#define DDR_PHY_DTPR4_RESERVED_27_26_DEFVAL 0x01C02B10 -#define DDR_PHY_DTPR4_RESERVED_27_26_SHIFT 26 -#define DDR_PHY_DTPR4_RESERVED_27_26_MASK 0x0C000000U +#define DDR_PHY_DTPR4_RESERVED_27_26_DEFVAL 0x01C02B10 +#define DDR_PHY_DTPR4_RESERVED_27_26_SHIFT 26 +#define DDR_PHY_DTPR4_RESERVED_27_26_MASK 0x0C000000U -/*Refresh-to-Refresh*/ +/* +* Refresh-to-Refresh +*/ #undef DDR_PHY_DTPR4_TRFC_DEFVAL #undef DDR_PHY_DTPR4_TRFC_SHIFT #undef DDR_PHY_DTPR4_TRFC_MASK -#define DDR_PHY_DTPR4_TRFC_DEFVAL 0x01C02B10 -#define DDR_PHY_DTPR4_TRFC_SHIFT 16 -#define DDR_PHY_DTPR4_TRFC_MASK 0x03FF0000U +#define DDR_PHY_DTPR4_TRFC_DEFVAL 0x01C02B10 +#define DDR_PHY_DTPR4_TRFC_SHIFT 16 +#define DDR_PHY_DTPR4_TRFC_MASK 0x03FF0000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR4_RESERVED_15_14_DEFVAL #undef DDR_PHY_DTPR4_RESERVED_15_14_SHIFT #undef DDR_PHY_DTPR4_RESERVED_15_14_MASK -#define DDR_PHY_DTPR4_RESERVED_15_14_DEFVAL 0x01C02B10 -#define DDR_PHY_DTPR4_RESERVED_15_14_SHIFT 14 -#define DDR_PHY_DTPR4_RESERVED_15_14_MASK 0x0000C000U +#define DDR_PHY_DTPR4_RESERVED_15_14_DEFVAL 0x01C02B10 +#define DDR_PHY_DTPR4_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_DTPR4_RESERVED_15_14_MASK 0x0000C000U -/*Write leveling output delay*/ +/* +* Write leveling output delay +*/ #undef DDR_PHY_DTPR4_TWLO_DEFVAL #undef DDR_PHY_DTPR4_TWLO_SHIFT #undef DDR_PHY_DTPR4_TWLO_MASK -#define DDR_PHY_DTPR4_TWLO_DEFVAL 0x01C02B10 -#define DDR_PHY_DTPR4_TWLO_SHIFT 8 -#define DDR_PHY_DTPR4_TWLO_MASK 0x00003F00U +#define DDR_PHY_DTPR4_TWLO_DEFVAL 0x01C02B10 +#define DDR_PHY_DTPR4_TWLO_SHIFT 8 +#define DDR_PHY_DTPR4_TWLO_MASK 0x00003F00U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR4_RESERVED_7_5_DEFVAL #undef DDR_PHY_DTPR4_RESERVED_7_5_SHIFT #undef DDR_PHY_DTPR4_RESERVED_7_5_MASK -#define DDR_PHY_DTPR4_RESERVED_7_5_DEFVAL 0x01C02B10 -#define DDR_PHY_DTPR4_RESERVED_7_5_SHIFT 5 -#define DDR_PHY_DTPR4_RESERVED_7_5_MASK 0x000000E0U +#define DDR_PHY_DTPR4_RESERVED_7_5_DEFVAL 0x01C02B10 +#define DDR_PHY_DTPR4_RESERVED_7_5_SHIFT 5 +#define DDR_PHY_DTPR4_RESERVED_7_5_MASK 0x000000E0U -/*Power down exit delay*/ +/* +* Power down exit delay +*/ #undef DDR_PHY_DTPR4_TXP_DEFVAL #undef DDR_PHY_DTPR4_TXP_SHIFT #undef DDR_PHY_DTPR4_TXP_MASK -#define DDR_PHY_DTPR4_TXP_DEFVAL 0x01C02B10 -#define DDR_PHY_DTPR4_TXP_SHIFT 0 -#define DDR_PHY_DTPR4_TXP_MASK 0x0000001FU +#define DDR_PHY_DTPR4_TXP_DEFVAL 0x01C02B10 +#define DDR_PHY_DTPR4_TXP_SHIFT 0 +#define DDR_PHY_DTPR4_TXP_MASK 0x0000001FU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR5_RESERVED_31_24_DEFVAL #undef DDR_PHY_DTPR5_RESERVED_31_24_SHIFT #undef DDR_PHY_DTPR5_RESERVED_31_24_MASK -#define DDR_PHY_DTPR5_RESERVED_31_24_DEFVAL 0x00872716 -#define DDR_PHY_DTPR5_RESERVED_31_24_SHIFT 24 -#define DDR_PHY_DTPR5_RESERVED_31_24_MASK 0xFF000000U +#define DDR_PHY_DTPR5_RESERVED_31_24_DEFVAL 0x00872716 +#define DDR_PHY_DTPR5_RESERVED_31_24_SHIFT 24 +#define DDR_PHY_DTPR5_RESERVED_31_24_MASK 0xFF000000U -/*Activate to activate command delay (same bank)*/ +/* +* Activate to activate command delay (same bank) +*/ #undef DDR_PHY_DTPR5_TRC_DEFVAL #undef DDR_PHY_DTPR5_TRC_SHIFT #undef DDR_PHY_DTPR5_TRC_MASK -#define DDR_PHY_DTPR5_TRC_DEFVAL 0x00872716 -#define DDR_PHY_DTPR5_TRC_SHIFT 16 -#define DDR_PHY_DTPR5_TRC_MASK 0x00FF0000U +#define DDR_PHY_DTPR5_TRC_DEFVAL 0x00872716 +#define DDR_PHY_DTPR5_TRC_SHIFT 16 +#define DDR_PHY_DTPR5_TRC_MASK 0x00FF0000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR5_RESERVED_15_DEFVAL #undef DDR_PHY_DTPR5_RESERVED_15_SHIFT #undef DDR_PHY_DTPR5_RESERVED_15_MASK -#define DDR_PHY_DTPR5_RESERVED_15_DEFVAL 0x00872716 -#define DDR_PHY_DTPR5_RESERVED_15_SHIFT 15 -#define DDR_PHY_DTPR5_RESERVED_15_MASK 0x00008000U +#define DDR_PHY_DTPR5_RESERVED_15_DEFVAL 0x00872716 +#define DDR_PHY_DTPR5_RESERVED_15_SHIFT 15 +#define DDR_PHY_DTPR5_RESERVED_15_MASK 0x00008000U -/*Activate to read or write delay*/ +/* +* Activate to read or write delay +*/ #undef DDR_PHY_DTPR5_TRCD_DEFVAL #undef DDR_PHY_DTPR5_TRCD_SHIFT #undef DDR_PHY_DTPR5_TRCD_MASK -#define DDR_PHY_DTPR5_TRCD_DEFVAL 0x00872716 -#define DDR_PHY_DTPR5_TRCD_SHIFT 8 -#define DDR_PHY_DTPR5_TRCD_MASK 0x00007F00U +#define DDR_PHY_DTPR5_TRCD_DEFVAL 0x00872716 +#define DDR_PHY_DTPR5_TRCD_SHIFT 8 +#define DDR_PHY_DTPR5_TRCD_MASK 0x00007F00U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR5_RESERVED_7_5_DEFVAL #undef DDR_PHY_DTPR5_RESERVED_7_5_SHIFT #undef DDR_PHY_DTPR5_RESERVED_7_5_MASK -#define DDR_PHY_DTPR5_RESERVED_7_5_DEFVAL 0x00872716 -#define DDR_PHY_DTPR5_RESERVED_7_5_SHIFT 5 -#define DDR_PHY_DTPR5_RESERVED_7_5_MASK 0x000000E0U +#define DDR_PHY_DTPR5_RESERVED_7_5_DEFVAL 0x00872716 +#define DDR_PHY_DTPR5_RESERVED_7_5_SHIFT 5 +#define DDR_PHY_DTPR5_RESERVED_7_5_MASK 0x000000E0U -/*Internal write to read command delay*/ +/* +* Internal write to read command delay +*/ #undef DDR_PHY_DTPR5_TWTR_DEFVAL #undef DDR_PHY_DTPR5_TWTR_SHIFT #undef DDR_PHY_DTPR5_TWTR_MASK -#define DDR_PHY_DTPR5_TWTR_DEFVAL 0x00872716 -#define DDR_PHY_DTPR5_TWTR_SHIFT 0 -#define DDR_PHY_DTPR5_TWTR_MASK 0x0000001FU +#define DDR_PHY_DTPR5_TWTR_DEFVAL 0x00872716 +#define DDR_PHY_DTPR5_TWTR_SHIFT 0 +#define DDR_PHY_DTPR5_TWTR_MASK 0x0000001FU -/*PUB Write Latency Enable*/ +/* +* PUB Write Latency Enable +*/ #undef DDR_PHY_DTPR6_PUBWLEN_DEFVAL #undef DDR_PHY_DTPR6_PUBWLEN_SHIFT #undef DDR_PHY_DTPR6_PUBWLEN_MASK -#define DDR_PHY_DTPR6_PUBWLEN_DEFVAL 0x00000505 -#define DDR_PHY_DTPR6_PUBWLEN_SHIFT 31 -#define DDR_PHY_DTPR6_PUBWLEN_MASK 0x80000000U +#define DDR_PHY_DTPR6_PUBWLEN_DEFVAL 0x00000505 +#define DDR_PHY_DTPR6_PUBWLEN_SHIFT 31 +#define DDR_PHY_DTPR6_PUBWLEN_MASK 0x80000000U -/*PUB Read Latency Enable*/ +/* +* PUB Read Latency Enable +*/ #undef DDR_PHY_DTPR6_PUBRLEN_DEFVAL #undef DDR_PHY_DTPR6_PUBRLEN_SHIFT #undef DDR_PHY_DTPR6_PUBRLEN_MASK -#define DDR_PHY_DTPR6_PUBRLEN_DEFVAL 0x00000505 -#define DDR_PHY_DTPR6_PUBRLEN_SHIFT 30 -#define DDR_PHY_DTPR6_PUBRLEN_MASK 0x40000000U +#define DDR_PHY_DTPR6_PUBRLEN_DEFVAL 0x00000505 +#define DDR_PHY_DTPR6_PUBRLEN_SHIFT 30 +#define DDR_PHY_DTPR6_PUBRLEN_MASK 0x40000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR6_RESERVED_29_14_DEFVAL #undef DDR_PHY_DTPR6_RESERVED_29_14_SHIFT #undef DDR_PHY_DTPR6_RESERVED_29_14_MASK -#define DDR_PHY_DTPR6_RESERVED_29_14_DEFVAL 0x00000505 -#define DDR_PHY_DTPR6_RESERVED_29_14_SHIFT 14 -#define DDR_PHY_DTPR6_RESERVED_29_14_MASK 0x3FFFC000U +#define DDR_PHY_DTPR6_RESERVED_29_14_DEFVAL 0x00000505 +#define DDR_PHY_DTPR6_RESERVED_29_14_SHIFT 14 +#define DDR_PHY_DTPR6_RESERVED_29_14_MASK 0x3FFFC000U -/*Write Latency*/ +/* +* Write Latency +*/ #undef DDR_PHY_DTPR6_PUBWL_DEFVAL #undef DDR_PHY_DTPR6_PUBWL_SHIFT #undef DDR_PHY_DTPR6_PUBWL_MASK -#define DDR_PHY_DTPR6_PUBWL_DEFVAL 0x00000505 -#define DDR_PHY_DTPR6_PUBWL_SHIFT 8 -#define DDR_PHY_DTPR6_PUBWL_MASK 0x00003F00U +#define DDR_PHY_DTPR6_PUBWL_DEFVAL 0x00000505 +#define DDR_PHY_DTPR6_PUBWL_SHIFT 8 +#define DDR_PHY_DTPR6_PUBWL_MASK 0x00003F00U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR6_RESERVED_7_6_DEFVAL #undef DDR_PHY_DTPR6_RESERVED_7_6_SHIFT #undef DDR_PHY_DTPR6_RESERVED_7_6_MASK -#define DDR_PHY_DTPR6_RESERVED_7_6_DEFVAL 0x00000505 -#define DDR_PHY_DTPR6_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_DTPR6_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_DTPR6_RESERVED_7_6_DEFVAL 0x00000505 +#define DDR_PHY_DTPR6_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DTPR6_RESERVED_7_6_MASK 0x000000C0U -/*Read Latency*/ +/* +* Read Latency +*/ #undef DDR_PHY_DTPR6_PUBRL_DEFVAL #undef DDR_PHY_DTPR6_PUBRL_SHIFT #undef DDR_PHY_DTPR6_PUBRL_MASK -#define DDR_PHY_DTPR6_PUBRL_DEFVAL 0x00000505 -#define DDR_PHY_DTPR6_PUBRL_SHIFT 0 -#define DDR_PHY_DTPR6_PUBRL_MASK 0x0000003FU +#define DDR_PHY_DTPR6_PUBRL_DEFVAL 0x00000505 +#define DDR_PHY_DTPR6_PUBRL_SHIFT 0 +#define DDR_PHY_DTPR6_PUBRL_MASK 0x0000003FU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_RDIMMGCR0_RESERVED_31_DEFVAL #undef DDR_PHY_RDIMMGCR0_RESERVED_31_SHIFT #undef DDR_PHY_RDIMMGCR0_RESERVED_31_MASK -#define DDR_PHY_RDIMMGCR0_RESERVED_31_DEFVAL 0x08400020 -#define DDR_PHY_RDIMMGCR0_RESERVED_31_SHIFT 31 -#define DDR_PHY_RDIMMGCR0_RESERVED_31_MASK 0x80000000U +#define DDR_PHY_RDIMMGCR0_RESERVED_31_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_RESERVED_31_SHIFT 31 +#define DDR_PHY_RDIMMGCR0_RESERVED_31_MASK 0x80000000U -/*RDMIMM Quad CS Enable*/ +/* +* RDMIMM Quad CS Enable +*/ #undef DDR_PHY_RDIMMGCR0_QCSEN_DEFVAL #undef DDR_PHY_RDIMMGCR0_QCSEN_SHIFT #undef DDR_PHY_RDIMMGCR0_QCSEN_MASK -#define DDR_PHY_RDIMMGCR0_QCSEN_DEFVAL 0x08400020 -#define DDR_PHY_RDIMMGCR0_QCSEN_SHIFT 30 -#define DDR_PHY_RDIMMGCR0_QCSEN_MASK 0x40000000U +#define DDR_PHY_RDIMMGCR0_QCSEN_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_QCSEN_SHIFT 30 +#define DDR_PHY_RDIMMGCR0_QCSEN_MASK 0x40000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_RDIMMGCR0_RESERVED_29_28_DEFVAL #undef DDR_PHY_RDIMMGCR0_RESERVED_29_28_SHIFT #undef DDR_PHY_RDIMMGCR0_RESERVED_29_28_MASK -#define DDR_PHY_RDIMMGCR0_RESERVED_29_28_DEFVAL 0x08400020 -#define DDR_PHY_RDIMMGCR0_RESERVED_29_28_SHIFT 28 -#define DDR_PHY_RDIMMGCR0_RESERVED_29_28_MASK 0x30000000U +#define DDR_PHY_RDIMMGCR0_RESERVED_29_28_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_RESERVED_29_28_SHIFT 28 +#define DDR_PHY_RDIMMGCR0_RESERVED_29_28_MASK 0x30000000U -/*RDIMM Outputs I/O Mode*/ +/* +* RDIMM Outputs I/O Mode +*/ #undef DDR_PHY_RDIMMGCR0_RDIMMIOM_DEFVAL #undef DDR_PHY_RDIMMGCR0_RDIMMIOM_SHIFT #undef DDR_PHY_RDIMMGCR0_RDIMMIOM_MASK -#define DDR_PHY_RDIMMGCR0_RDIMMIOM_DEFVAL 0x08400020 -#define DDR_PHY_RDIMMGCR0_RDIMMIOM_SHIFT 27 -#define DDR_PHY_RDIMMGCR0_RDIMMIOM_MASK 0x08000000U +#define DDR_PHY_RDIMMGCR0_RDIMMIOM_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_RDIMMIOM_SHIFT 27 +#define DDR_PHY_RDIMMGCR0_RDIMMIOM_MASK 0x08000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_RDIMMGCR0_RESERVED_26_24_DEFVAL #undef DDR_PHY_RDIMMGCR0_RESERVED_26_24_SHIFT #undef DDR_PHY_RDIMMGCR0_RESERVED_26_24_MASK -#define DDR_PHY_RDIMMGCR0_RESERVED_26_24_DEFVAL 0x08400020 -#define DDR_PHY_RDIMMGCR0_RESERVED_26_24_SHIFT 24 -#define DDR_PHY_RDIMMGCR0_RESERVED_26_24_MASK 0x07000000U +#define DDR_PHY_RDIMMGCR0_RESERVED_26_24_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_RESERVED_26_24_SHIFT 24 +#define DDR_PHY_RDIMMGCR0_RESERVED_26_24_MASK 0x07000000U -/*ERROUT# Output Enable*/ +/* +* ERROUT# Output Enable +*/ #undef DDR_PHY_RDIMMGCR0_ERROUTOE_DEFVAL #undef DDR_PHY_RDIMMGCR0_ERROUTOE_SHIFT #undef DDR_PHY_RDIMMGCR0_ERROUTOE_MASK -#define DDR_PHY_RDIMMGCR0_ERROUTOE_DEFVAL 0x08400020 -#define DDR_PHY_RDIMMGCR0_ERROUTOE_SHIFT 23 -#define DDR_PHY_RDIMMGCR0_ERROUTOE_MASK 0x00800000U +#define DDR_PHY_RDIMMGCR0_ERROUTOE_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_ERROUTOE_SHIFT 23 +#define DDR_PHY_RDIMMGCR0_ERROUTOE_MASK 0x00800000U -/*ERROUT# I/O Mode*/ +/* +* ERROUT# I/O Mode +*/ #undef DDR_PHY_RDIMMGCR0_ERROUTIOM_DEFVAL #undef DDR_PHY_RDIMMGCR0_ERROUTIOM_SHIFT #undef DDR_PHY_RDIMMGCR0_ERROUTIOM_MASK -#define DDR_PHY_RDIMMGCR0_ERROUTIOM_DEFVAL 0x08400020 -#define DDR_PHY_RDIMMGCR0_ERROUTIOM_SHIFT 22 -#define DDR_PHY_RDIMMGCR0_ERROUTIOM_MASK 0x00400000U +#define DDR_PHY_RDIMMGCR0_ERROUTIOM_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_ERROUTIOM_SHIFT 22 +#define DDR_PHY_RDIMMGCR0_ERROUTIOM_MASK 0x00400000U -/*ERROUT# Power Down Receiver*/ +/* +* ERROUT# Power Down Receiver +*/ #undef DDR_PHY_RDIMMGCR0_ERROUTPDR_DEFVAL #undef DDR_PHY_RDIMMGCR0_ERROUTPDR_SHIFT #undef DDR_PHY_RDIMMGCR0_ERROUTPDR_MASK -#define DDR_PHY_RDIMMGCR0_ERROUTPDR_DEFVAL 0x08400020 -#define DDR_PHY_RDIMMGCR0_ERROUTPDR_SHIFT 21 -#define DDR_PHY_RDIMMGCR0_ERROUTPDR_MASK 0x00200000U +#define DDR_PHY_RDIMMGCR0_ERROUTPDR_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_ERROUTPDR_SHIFT 21 +#define DDR_PHY_RDIMMGCR0_ERROUTPDR_MASK 0x00200000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_RDIMMGCR0_RESERVED_20_DEFVAL #undef DDR_PHY_RDIMMGCR0_RESERVED_20_SHIFT #undef DDR_PHY_RDIMMGCR0_RESERVED_20_MASK -#define DDR_PHY_RDIMMGCR0_RESERVED_20_DEFVAL 0x08400020 -#define DDR_PHY_RDIMMGCR0_RESERVED_20_SHIFT 20 -#define DDR_PHY_RDIMMGCR0_RESERVED_20_MASK 0x00100000U +#define DDR_PHY_RDIMMGCR0_RESERVED_20_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_RESERVED_20_SHIFT 20 +#define DDR_PHY_RDIMMGCR0_RESERVED_20_MASK 0x00100000U -/*ERROUT# On-Die Termination*/ +/* +* ERROUT# On-Die Termination +*/ #undef DDR_PHY_RDIMMGCR0_ERROUTODT_DEFVAL #undef DDR_PHY_RDIMMGCR0_ERROUTODT_SHIFT #undef DDR_PHY_RDIMMGCR0_ERROUTODT_MASK -#define DDR_PHY_RDIMMGCR0_ERROUTODT_DEFVAL 0x08400020 -#define DDR_PHY_RDIMMGCR0_ERROUTODT_SHIFT 19 -#define DDR_PHY_RDIMMGCR0_ERROUTODT_MASK 0x00080000U +#define DDR_PHY_RDIMMGCR0_ERROUTODT_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_ERROUTODT_SHIFT 19 +#define DDR_PHY_RDIMMGCR0_ERROUTODT_MASK 0x00080000U -/*Load Reduced DIMM*/ +/* +* Load Reduced DIMM +*/ #undef DDR_PHY_RDIMMGCR0_LRDIMM_DEFVAL #undef DDR_PHY_RDIMMGCR0_LRDIMM_SHIFT #undef DDR_PHY_RDIMMGCR0_LRDIMM_MASK -#define DDR_PHY_RDIMMGCR0_LRDIMM_DEFVAL 0x08400020 -#define DDR_PHY_RDIMMGCR0_LRDIMM_SHIFT 18 -#define DDR_PHY_RDIMMGCR0_LRDIMM_MASK 0x00040000U +#define DDR_PHY_RDIMMGCR0_LRDIMM_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_LRDIMM_SHIFT 18 +#define DDR_PHY_RDIMMGCR0_LRDIMM_MASK 0x00040000U -/*PAR_IN I/O Mode*/ +/* +* PAR_IN I/O Mode +*/ #undef DDR_PHY_RDIMMGCR0_PARINIOM_DEFVAL #undef DDR_PHY_RDIMMGCR0_PARINIOM_SHIFT #undef DDR_PHY_RDIMMGCR0_PARINIOM_MASK -#define DDR_PHY_RDIMMGCR0_PARINIOM_DEFVAL 0x08400020 -#define DDR_PHY_RDIMMGCR0_PARINIOM_SHIFT 17 -#define DDR_PHY_RDIMMGCR0_PARINIOM_MASK 0x00020000U +#define DDR_PHY_RDIMMGCR0_PARINIOM_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_PARINIOM_SHIFT 17 +#define DDR_PHY_RDIMMGCR0_PARINIOM_MASK 0x00020000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_RDIMMGCR0_RESERVED_16_8_DEFVAL #undef DDR_PHY_RDIMMGCR0_RESERVED_16_8_SHIFT #undef DDR_PHY_RDIMMGCR0_RESERVED_16_8_MASK -#define DDR_PHY_RDIMMGCR0_RESERVED_16_8_DEFVAL 0x08400020 -#define DDR_PHY_RDIMMGCR0_RESERVED_16_8_SHIFT 8 -#define DDR_PHY_RDIMMGCR0_RESERVED_16_8_MASK 0x0001FF00U +#define DDR_PHY_RDIMMGCR0_RESERVED_16_8_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_RESERVED_16_8_SHIFT 8 +#define DDR_PHY_RDIMMGCR0_RESERVED_16_8_MASK 0x0001FF00U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_DEFVAL #undef DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_SHIFT #undef DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_MASK -#define DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_DEFVAL 0x08400020 -#define DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_SHIFT 6 -#define DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_MASK 0x000000C0U +#define DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_SHIFT 6 +#define DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_MASK 0x000000C0U -/*Rank Mirror Enable.*/ +/* +* Rank Mirror Enable. +*/ #undef DDR_PHY_RDIMMGCR0_RNKMRREN_DEFVAL #undef DDR_PHY_RDIMMGCR0_RNKMRREN_SHIFT #undef DDR_PHY_RDIMMGCR0_RNKMRREN_MASK -#define DDR_PHY_RDIMMGCR0_RNKMRREN_DEFVAL 0x08400020 -#define DDR_PHY_RDIMMGCR0_RNKMRREN_SHIFT 4 -#define DDR_PHY_RDIMMGCR0_RNKMRREN_MASK 0x00000030U +#define DDR_PHY_RDIMMGCR0_RNKMRREN_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_RNKMRREN_SHIFT 4 +#define DDR_PHY_RDIMMGCR0_RNKMRREN_MASK 0x00000030U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_RDIMMGCR0_RESERVED_3_DEFVAL #undef DDR_PHY_RDIMMGCR0_RESERVED_3_SHIFT #undef DDR_PHY_RDIMMGCR0_RESERVED_3_MASK -#define DDR_PHY_RDIMMGCR0_RESERVED_3_DEFVAL 0x08400020 -#define DDR_PHY_RDIMMGCR0_RESERVED_3_SHIFT 3 -#define DDR_PHY_RDIMMGCR0_RESERVED_3_MASK 0x00000008U +#define DDR_PHY_RDIMMGCR0_RESERVED_3_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_RESERVED_3_SHIFT 3 +#define DDR_PHY_RDIMMGCR0_RESERVED_3_MASK 0x00000008U -/*Stop on Parity Error*/ +/* +* Stop on Parity Error +*/ #undef DDR_PHY_RDIMMGCR0_SOPERR_DEFVAL #undef DDR_PHY_RDIMMGCR0_SOPERR_SHIFT #undef DDR_PHY_RDIMMGCR0_SOPERR_MASK -#define DDR_PHY_RDIMMGCR0_SOPERR_DEFVAL 0x08400020 -#define DDR_PHY_RDIMMGCR0_SOPERR_SHIFT 2 -#define DDR_PHY_RDIMMGCR0_SOPERR_MASK 0x00000004U +#define DDR_PHY_RDIMMGCR0_SOPERR_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_SOPERR_SHIFT 2 +#define DDR_PHY_RDIMMGCR0_SOPERR_MASK 0x00000004U -/*Parity Error No Registering*/ +/* +* Parity Error No Registering +*/ #undef DDR_PHY_RDIMMGCR0_ERRNOREG_DEFVAL #undef DDR_PHY_RDIMMGCR0_ERRNOREG_SHIFT #undef DDR_PHY_RDIMMGCR0_ERRNOREG_MASK -#define DDR_PHY_RDIMMGCR0_ERRNOREG_DEFVAL 0x08400020 -#define DDR_PHY_RDIMMGCR0_ERRNOREG_SHIFT 1 -#define DDR_PHY_RDIMMGCR0_ERRNOREG_MASK 0x00000002U +#define DDR_PHY_RDIMMGCR0_ERRNOREG_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_ERRNOREG_SHIFT 1 +#define DDR_PHY_RDIMMGCR0_ERRNOREG_MASK 0x00000002U -/*Registered DIMM*/ +/* +* Registered DIMM +*/ #undef DDR_PHY_RDIMMGCR0_RDIMM_DEFVAL #undef DDR_PHY_RDIMMGCR0_RDIMM_SHIFT #undef DDR_PHY_RDIMMGCR0_RDIMM_MASK -#define DDR_PHY_RDIMMGCR0_RDIMM_DEFVAL 0x08400020 -#define DDR_PHY_RDIMMGCR0_RDIMM_SHIFT 0 -#define DDR_PHY_RDIMMGCR0_RDIMM_MASK 0x00000001U +#define DDR_PHY_RDIMMGCR0_RDIMM_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_RDIMM_SHIFT 0 +#define DDR_PHY_RDIMMGCR0_RDIMM_MASK 0x00000001U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_RDIMMGCR1_RESERVED_31_29_DEFVAL #undef DDR_PHY_RDIMMGCR1_RESERVED_31_29_SHIFT #undef DDR_PHY_RDIMMGCR1_RESERVED_31_29_MASK -#define DDR_PHY_RDIMMGCR1_RESERVED_31_29_DEFVAL 0x00000C80 -#define DDR_PHY_RDIMMGCR1_RESERVED_31_29_SHIFT 29 -#define DDR_PHY_RDIMMGCR1_RESERVED_31_29_MASK 0xE0000000U +#define DDR_PHY_RDIMMGCR1_RESERVED_31_29_DEFVAL 0x00000C80 +#define DDR_PHY_RDIMMGCR1_RESERVED_31_29_SHIFT 29 +#define DDR_PHY_RDIMMGCR1_RESERVED_31_29_MASK 0xE0000000U -/*Address [17] B-side Inversion Disable*/ +/* +* Address [17] B-side Inversion Disable +*/ #undef DDR_PHY_RDIMMGCR1_A17BID_DEFVAL #undef DDR_PHY_RDIMMGCR1_A17BID_SHIFT #undef DDR_PHY_RDIMMGCR1_A17BID_MASK -#define DDR_PHY_RDIMMGCR1_A17BID_DEFVAL 0x00000C80 -#define DDR_PHY_RDIMMGCR1_A17BID_SHIFT 28 -#define DDR_PHY_RDIMMGCR1_A17BID_MASK 0x10000000U +#define DDR_PHY_RDIMMGCR1_A17BID_DEFVAL 0x00000C80 +#define DDR_PHY_RDIMMGCR1_A17BID_SHIFT 28 +#define DDR_PHY_RDIMMGCR1_A17BID_MASK 0x10000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_RDIMMGCR1_RESERVED_27_DEFVAL #undef DDR_PHY_RDIMMGCR1_RESERVED_27_SHIFT #undef DDR_PHY_RDIMMGCR1_RESERVED_27_MASK -#define DDR_PHY_RDIMMGCR1_RESERVED_27_DEFVAL 0x00000C80 -#define DDR_PHY_RDIMMGCR1_RESERVED_27_SHIFT 27 -#define DDR_PHY_RDIMMGCR1_RESERVED_27_MASK 0x08000000U +#define DDR_PHY_RDIMMGCR1_RESERVED_27_DEFVAL 0x00000C80 +#define DDR_PHY_RDIMMGCR1_RESERVED_27_SHIFT 27 +#define DDR_PHY_RDIMMGCR1_RESERVED_27_MASK 0x08000000U -/*Command word to command word programming delay*/ +/* +* Command word to command word programming delay +*/ #undef DDR_PHY_RDIMMGCR1_TBCMRD_L2_DEFVAL #undef DDR_PHY_RDIMMGCR1_TBCMRD_L2_SHIFT #undef DDR_PHY_RDIMMGCR1_TBCMRD_L2_MASK -#define DDR_PHY_RDIMMGCR1_TBCMRD_L2_DEFVAL 0x00000C80 -#define DDR_PHY_RDIMMGCR1_TBCMRD_L2_SHIFT 24 -#define DDR_PHY_RDIMMGCR1_TBCMRD_L2_MASK 0x07000000U +#define DDR_PHY_RDIMMGCR1_TBCMRD_L2_DEFVAL 0x00000C80 +#define DDR_PHY_RDIMMGCR1_TBCMRD_L2_SHIFT 24 +#define DDR_PHY_RDIMMGCR1_TBCMRD_L2_MASK 0x07000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_RDIMMGCR1_RESERVED_23_DEFVAL #undef DDR_PHY_RDIMMGCR1_RESERVED_23_SHIFT #undef DDR_PHY_RDIMMGCR1_RESERVED_23_MASK -#define DDR_PHY_RDIMMGCR1_RESERVED_23_DEFVAL 0x00000C80 -#define DDR_PHY_RDIMMGCR1_RESERVED_23_SHIFT 23 -#define DDR_PHY_RDIMMGCR1_RESERVED_23_MASK 0x00800000U +#define DDR_PHY_RDIMMGCR1_RESERVED_23_DEFVAL 0x00000C80 +#define DDR_PHY_RDIMMGCR1_RESERVED_23_SHIFT 23 +#define DDR_PHY_RDIMMGCR1_RESERVED_23_MASK 0x00800000U -/*Command word to command word programming delay*/ +/* +* Command word to command word programming delay +*/ #undef DDR_PHY_RDIMMGCR1_TBCMRD_L_DEFVAL #undef DDR_PHY_RDIMMGCR1_TBCMRD_L_SHIFT #undef DDR_PHY_RDIMMGCR1_TBCMRD_L_MASK -#define DDR_PHY_RDIMMGCR1_TBCMRD_L_DEFVAL 0x00000C80 -#define DDR_PHY_RDIMMGCR1_TBCMRD_L_SHIFT 20 -#define DDR_PHY_RDIMMGCR1_TBCMRD_L_MASK 0x00700000U +#define DDR_PHY_RDIMMGCR1_TBCMRD_L_DEFVAL 0x00000C80 +#define DDR_PHY_RDIMMGCR1_TBCMRD_L_SHIFT 20 +#define DDR_PHY_RDIMMGCR1_TBCMRD_L_MASK 0x00700000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_RDIMMGCR1_RESERVED_19_DEFVAL #undef DDR_PHY_RDIMMGCR1_RESERVED_19_SHIFT #undef DDR_PHY_RDIMMGCR1_RESERVED_19_MASK -#define DDR_PHY_RDIMMGCR1_RESERVED_19_DEFVAL 0x00000C80 -#define DDR_PHY_RDIMMGCR1_RESERVED_19_SHIFT 19 -#define DDR_PHY_RDIMMGCR1_RESERVED_19_MASK 0x00080000U +#define DDR_PHY_RDIMMGCR1_RESERVED_19_DEFVAL 0x00000C80 +#define DDR_PHY_RDIMMGCR1_RESERVED_19_SHIFT 19 +#define DDR_PHY_RDIMMGCR1_RESERVED_19_MASK 0x00080000U -/*Command word to command word programming delay*/ +/* +* Command word to command word programming delay +*/ #undef DDR_PHY_RDIMMGCR1_TBCMRD_DEFVAL #undef DDR_PHY_RDIMMGCR1_TBCMRD_SHIFT #undef DDR_PHY_RDIMMGCR1_TBCMRD_MASK -#define DDR_PHY_RDIMMGCR1_TBCMRD_DEFVAL 0x00000C80 -#define DDR_PHY_RDIMMGCR1_TBCMRD_SHIFT 16 -#define DDR_PHY_RDIMMGCR1_TBCMRD_MASK 0x00070000U +#define DDR_PHY_RDIMMGCR1_TBCMRD_DEFVAL 0x00000C80 +#define DDR_PHY_RDIMMGCR1_TBCMRD_SHIFT 16 +#define DDR_PHY_RDIMMGCR1_TBCMRD_MASK 0x00070000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_RDIMMGCR1_RESERVED_15_14_DEFVAL #undef DDR_PHY_RDIMMGCR1_RESERVED_15_14_SHIFT #undef DDR_PHY_RDIMMGCR1_RESERVED_15_14_MASK -#define DDR_PHY_RDIMMGCR1_RESERVED_15_14_DEFVAL 0x00000C80 -#define DDR_PHY_RDIMMGCR1_RESERVED_15_14_SHIFT 14 -#define DDR_PHY_RDIMMGCR1_RESERVED_15_14_MASK 0x0000C000U +#define DDR_PHY_RDIMMGCR1_RESERVED_15_14_DEFVAL 0x00000C80 +#define DDR_PHY_RDIMMGCR1_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_RDIMMGCR1_RESERVED_15_14_MASK 0x0000C000U -/*Stabilization time*/ +/* +* Stabilization time +*/ #undef DDR_PHY_RDIMMGCR1_TBCSTAB_DEFVAL #undef DDR_PHY_RDIMMGCR1_TBCSTAB_SHIFT #undef DDR_PHY_RDIMMGCR1_TBCSTAB_MASK -#define DDR_PHY_RDIMMGCR1_TBCSTAB_DEFVAL 0x00000C80 -#define DDR_PHY_RDIMMGCR1_TBCSTAB_SHIFT 0 -#define DDR_PHY_RDIMMGCR1_TBCSTAB_MASK 0x00003FFFU +#define DDR_PHY_RDIMMGCR1_TBCSTAB_DEFVAL 0x00000C80 +#define DDR_PHY_RDIMMGCR1_TBCSTAB_SHIFT 0 +#define DDR_PHY_RDIMMGCR1_TBCSTAB_MASK 0x00003FFFU -/*DDR4/DDR3 Control Word 7*/ +/* +* DDR4/DDR3 Control Word 7 +*/ #undef DDR_PHY_RDIMMCR0_RC7_DEFVAL #undef DDR_PHY_RDIMMCR0_RC7_SHIFT #undef DDR_PHY_RDIMMCR0_RC7_MASK -#define DDR_PHY_RDIMMCR0_RC7_DEFVAL 0x00000000 -#define DDR_PHY_RDIMMCR0_RC7_SHIFT 28 -#define DDR_PHY_RDIMMCR0_RC7_MASK 0xF0000000U +#define DDR_PHY_RDIMMCR0_RC7_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR0_RC7_SHIFT 28 +#define DDR_PHY_RDIMMCR0_RC7_MASK 0xF0000000U -/*DDR4 Control Word 6 (Comman space Control Word) / DDR3 Reserved*/ +/* +* DDR4 Control Word 6 (Comman space Control Word) / DDR3 Reserved +*/ #undef DDR_PHY_RDIMMCR0_RC6_DEFVAL #undef DDR_PHY_RDIMMCR0_RC6_SHIFT #undef DDR_PHY_RDIMMCR0_RC6_MASK -#define DDR_PHY_RDIMMCR0_RC6_DEFVAL 0x00000000 -#define DDR_PHY_RDIMMCR0_RC6_SHIFT 24 -#define DDR_PHY_RDIMMCR0_RC6_MASK 0x0F000000U +#define DDR_PHY_RDIMMCR0_RC6_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR0_RC6_SHIFT 24 +#define DDR_PHY_RDIMMCR0_RC6_MASK 0x0F000000U -/*DDR4/DDR3 Control Word 5 (CK Driver Characteristics Control Word)*/ +/* +* DDR4/DDR3 Control Word 5 (CK Driver Characteristics Control Word) +*/ #undef DDR_PHY_RDIMMCR0_RC5_DEFVAL #undef DDR_PHY_RDIMMCR0_RC5_SHIFT #undef DDR_PHY_RDIMMCR0_RC5_MASK -#define DDR_PHY_RDIMMCR0_RC5_DEFVAL 0x00000000 -#define DDR_PHY_RDIMMCR0_RC5_SHIFT 20 -#define DDR_PHY_RDIMMCR0_RC5_MASK 0x00F00000U +#define DDR_PHY_RDIMMCR0_RC5_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR0_RC5_SHIFT 20 +#define DDR_PHY_RDIMMCR0_RC5_MASK 0x00F00000U -/*DDR4 Control Word 4 (ODT and CKE Signals Driver Characteristics Control Word) / DDR3 Control Word 4 (Control Signals Driver C - aracteristics Control Word)*/ +/* +* DDR4 Control Word 4 (ODT and CKE Signals Driver Characteristics Control + * Word) / DDR3 Control Word 4 (Control Signals Driver Characteristics Cont + * rol Word) +*/ #undef DDR_PHY_RDIMMCR0_RC4_DEFVAL #undef DDR_PHY_RDIMMCR0_RC4_SHIFT #undef DDR_PHY_RDIMMCR0_RC4_MASK -#define DDR_PHY_RDIMMCR0_RC4_DEFVAL 0x00000000 -#define DDR_PHY_RDIMMCR0_RC4_SHIFT 16 -#define DDR_PHY_RDIMMCR0_RC4_MASK 0x000F0000U +#define DDR_PHY_RDIMMCR0_RC4_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR0_RC4_SHIFT 16 +#define DDR_PHY_RDIMMCR0_RC4_MASK 0x000F0000U -/*DDR4 Control Word 3 (CA and CS Signals Driver Characteristics Control Word) / DDR3 Control Word 3 (Command/Address Signals Dr - ver Characteristrics Control Word)*/ +/* +* DDR4 Control Word 3 (CA and CS Signals Driver Characteristics Control Wo + * rd) / DDR3 Control Word 3 (Command/Address Signals Driver Characteristri + * cs Control Word) +*/ #undef DDR_PHY_RDIMMCR0_RC3_DEFVAL #undef DDR_PHY_RDIMMCR0_RC3_SHIFT #undef DDR_PHY_RDIMMCR0_RC3_MASK -#define DDR_PHY_RDIMMCR0_RC3_DEFVAL 0x00000000 -#define DDR_PHY_RDIMMCR0_RC3_SHIFT 12 -#define DDR_PHY_RDIMMCR0_RC3_MASK 0x0000F000U +#define DDR_PHY_RDIMMCR0_RC3_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR0_RC3_SHIFT 12 +#define DDR_PHY_RDIMMCR0_RC3_MASK 0x0000F000U -/*DDR4 Control Word 2 (Timing and IBT Control Word) / DDR3 Control Word 2 (Timing Control Word)*/ +/* +* DDR4 Control Word 2 (Timing and IBT Control Word) / DDR3 Control Word 2 + * (Timing Control Word) +*/ #undef DDR_PHY_RDIMMCR0_RC2_DEFVAL #undef DDR_PHY_RDIMMCR0_RC2_SHIFT #undef DDR_PHY_RDIMMCR0_RC2_MASK -#define DDR_PHY_RDIMMCR0_RC2_DEFVAL 0x00000000 -#define DDR_PHY_RDIMMCR0_RC2_SHIFT 8 -#define DDR_PHY_RDIMMCR0_RC2_MASK 0x00000F00U +#define DDR_PHY_RDIMMCR0_RC2_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR0_RC2_SHIFT 8 +#define DDR_PHY_RDIMMCR0_RC2_MASK 0x00000F00U -/*DDR4/DDR3 Control Word 1 (Clock Driver Enable Control Word)*/ +/* +* DDR4/DDR3 Control Word 1 (Clock Driver Enable Control Word) +*/ #undef DDR_PHY_RDIMMCR0_RC1_DEFVAL #undef DDR_PHY_RDIMMCR0_RC1_SHIFT #undef DDR_PHY_RDIMMCR0_RC1_MASK -#define DDR_PHY_RDIMMCR0_RC1_DEFVAL 0x00000000 -#define DDR_PHY_RDIMMCR0_RC1_SHIFT 4 -#define DDR_PHY_RDIMMCR0_RC1_MASK 0x000000F0U +#define DDR_PHY_RDIMMCR0_RC1_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR0_RC1_SHIFT 4 +#define DDR_PHY_RDIMMCR0_RC1_MASK 0x000000F0U -/*DDR4/DDR3 Control Word 0 (Global Features Control Word)*/ +/* +* DDR4/DDR3 Control Word 0 (Global Features Control Word) +*/ #undef DDR_PHY_RDIMMCR0_RC0_DEFVAL #undef DDR_PHY_RDIMMCR0_RC0_SHIFT #undef DDR_PHY_RDIMMCR0_RC0_MASK -#define DDR_PHY_RDIMMCR0_RC0_DEFVAL 0x00000000 -#define DDR_PHY_RDIMMCR0_RC0_SHIFT 0 -#define DDR_PHY_RDIMMCR0_RC0_MASK 0x0000000FU +#define DDR_PHY_RDIMMCR0_RC0_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR0_RC0_SHIFT 0 +#define DDR_PHY_RDIMMCR0_RC0_MASK 0x0000000FU -/*Control Word 15*/ +/* +* Control Word 15 +*/ #undef DDR_PHY_RDIMMCR1_RC15_DEFVAL #undef DDR_PHY_RDIMMCR1_RC15_SHIFT #undef DDR_PHY_RDIMMCR1_RC15_MASK -#define DDR_PHY_RDIMMCR1_RC15_DEFVAL 0x00000000 -#define DDR_PHY_RDIMMCR1_RC15_SHIFT 28 -#define DDR_PHY_RDIMMCR1_RC15_MASK 0xF0000000U +#define DDR_PHY_RDIMMCR1_RC15_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR1_RC15_SHIFT 28 +#define DDR_PHY_RDIMMCR1_RC15_MASK 0xF0000000U -/*DDR4 Control Word 14 (Parity Control Word) / DDR3 Reserved*/ +/* +* DDR4 Control Word 14 (Parity Control Word) / DDR3 Reserved +*/ #undef DDR_PHY_RDIMMCR1_RC14_DEFVAL #undef DDR_PHY_RDIMMCR1_RC14_SHIFT #undef DDR_PHY_RDIMMCR1_RC14_MASK -#define DDR_PHY_RDIMMCR1_RC14_DEFVAL 0x00000000 -#define DDR_PHY_RDIMMCR1_RC14_SHIFT 24 -#define DDR_PHY_RDIMMCR1_RC14_MASK 0x0F000000U +#define DDR_PHY_RDIMMCR1_RC14_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR1_RC14_SHIFT 24 +#define DDR_PHY_RDIMMCR1_RC14_MASK 0x0F000000U -/*DDR4 Control Word 13 (DIMM Configuration Control Word) / DDR3 Reserved*/ +/* +* DDR4 Control Word 13 (DIMM Configuration Control Word) / DDR3 Reserved +*/ #undef DDR_PHY_RDIMMCR1_RC13_DEFVAL #undef DDR_PHY_RDIMMCR1_RC13_SHIFT #undef DDR_PHY_RDIMMCR1_RC13_MASK -#define DDR_PHY_RDIMMCR1_RC13_DEFVAL 0x00000000 -#define DDR_PHY_RDIMMCR1_RC13_SHIFT 20 -#define DDR_PHY_RDIMMCR1_RC13_MASK 0x00F00000U +#define DDR_PHY_RDIMMCR1_RC13_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR1_RC13_SHIFT 20 +#define DDR_PHY_RDIMMCR1_RC13_MASK 0x00F00000U -/*DDR4 Control Word 12 (Training Control Word) / DDR3 Reserved*/ +/* +* DDR4 Control Word 12 (Training Control Word) / DDR3 Reserved +*/ #undef DDR_PHY_RDIMMCR1_RC12_DEFVAL #undef DDR_PHY_RDIMMCR1_RC12_SHIFT #undef DDR_PHY_RDIMMCR1_RC12_MASK -#define DDR_PHY_RDIMMCR1_RC12_DEFVAL 0x00000000 -#define DDR_PHY_RDIMMCR1_RC12_SHIFT 16 -#define DDR_PHY_RDIMMCR1_RC12_MASK 0x000F0000U +#define DDR_PHY_RDIMMCR1_RC12_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR1_RC12_SHIFT 16 +#define DDR_PHY_RDIMMCR1_RC12_MASK 0x000F0000U -/*DDR4 Control Word 11 (Operating Voltage VDD and VREFCA Source Control Word) / DDR3 Control Word 11 (Operation Voltage VDD Con - rol Word)*/ +/* +* DDR4 Control Word 11 (Operating Voltage VDD and VREFCA Source Control Wo + * rd) / DDR3 Control Word 11 (Operation Voltage VDD Control Word) +*/ #undef DDR_PHY_RDIMMCR1_RC11_DEFVAL #undef DDR_PHY_RDIMMCR1_RC11_SHIFT #undef DDR_PHY_RDIMMCR1_RC11_MASK -#define DDR_PHY_RDIMMCR1_RC11_DEFVAL 0x00000000 -#define DDR_PHY_RDIMMCR1_RC11_SHIFT 12 -#define DDR_PHY_RDIMMCR1_RC11_MASK 0x0000F000U +#define DDR_PHY_RDIMMCR1_RC11_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR1_RC11_SHIFT 12 +#define DDR_PHY_RDIMMCR1_RC11_MASK 0x0000F000U -/*DDR4/DDR3 Control Word 10 (RDIMM Operating Speed Control Word)*/ +/* +* DDR4/DDR3 Control Word 10 (RDIMM Operating Speed Control Word) +*/ #undef DDR_PHY_RDIMMCR1_RC10_DEFVAL #undef DDR_PHY_RDIMMCR1_RC10_SHIFT #undef DDR_PHY_RDIMMCR1_RC10_MASK -#define DDR_PHY_RDIMMCR1_RC10_DEFVAL 0x00000000 -#define DDR_PHY_RDIMMCR1_RC10_SHIFT 8 -#define DDR_PHY_RDIMMCR1_RC10_MASK 0x00000F00U +#define DDR_PHY_RDIMMCR1_RC10_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR1_RC10_SHIFT 8 +#define DDR_PHY_RDIMMCR1_RC10_MASK 0x00000F00U -/*DDR4/DDR3 Control Word 9 (Power Saving Settings Control Word)*/ +/* +* DDR4/DDR3 Control Word 9 (Power Saving Settings Control Word) +*/ #undef DDR_PHY_RDIMMCR1_RC9_DEFVAL #undef DDR_PHY_RDIMMCR1_RC9_SHIFT #undef DDR_PHY_RDIMMCR1_RC9_MASK -#define DDR_PHY_RDIMMCR1_RC9_DEFVAL 0x00000000 -#define DDR_PHY_RDIMMCR1_RC9_SHIFT 4 -#define DDR_PHY_RDIMMCR1_RC9_MASK 0x000000F0U +#define DDR_PHY_RDIMMCR1_RC9_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR1_RC9_SHIFT 4 +#define DDR_PHY_RDIMMCR1_RC9_MASK 0x000000F0U -/*DDR4 Control Word 8 (Input/Output Configuration Control Word) / DDR3 Control Word 8 (Additional Input Bus Termination Setting - Control Word)*/ +/* +* DDR4 Control Word 8 (Input/Output Configuration Control Word) / DDR3 Con + * trol Word 8 (Additional Input Bus Termination Setting Control Word) +*/ #undef DDR_PHY_RDIMMCR1_RC8_DEFVAL #undef DDR_PHY_RDIMMCR1_RC8_SHIFT #undef DDR_PHY_RDIMMCR1_RC8_MASK -#define DDR_PHY_RDIMMCR1_RC8_DEFVAL 0x00000000 -#define DDR_PHY_RDIMMCR1_RC8_SHIFT 0 -#define DDR_PHY_RDIMMCR1_RC8_MASK 0x0000000FU +#define DDR_PHY_RDIMMCR1_RC8_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR1_RC8_SHIFT 0 +#define DDR_PHY_RDIMMCR1_RC8_MASK 0x0000000FU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_MR0_RESERVED_31_8_DEFVAL #undef DDR_PHY_MR0_RESERVED_31_8_SHIFT #undef DDR_PHY_MR0_RESERVED_31_8_MASK -#define DDR_PHY_MR0_RESERVED_31_8_DEFVAL 0x00000052 -#define DDR_PHY_MR0_RESERVED_31_8_SHIFT 8 -#define DDR_PHY_MR0_RESERVED_31_8_MASK 0xFFFFFF00U +#define DDR_PHY_MR0_RESERVED_31_8_DEFVAL 0x00000052 +#define DDR_PHY_MR0_RESERVED_31_8_SHIFT 8 +#define DDR_PHY_MR0_RESERVED_31_8_MASK 0xFFFFFF00U -/*CA Terminating Rank*/ +/* +* CA Terminating Rank +*/ #undef DDR_PHY_MR0_CATR_DEFVAL #undef DDR_PHY_MR0_CATR_SHIFT #undef DDR_PHY_MR0_CATR_MASK -#define DDR_PHY_MR0_CATR_DEFVAL 0x00000052 -#define DDR_PHY_MR0_CATR_SHIFT 7 -#define DDR_PHY_MR0_CATR_MASK 0x00000080U +#define DDR_PHY_MR0_CATR_DEFVAL 0x00000052 +#define DDR_PHY_MR0_CATR_SHIFT 7 +#define DDR_PHY_MR0_CATR_MASK 0x00000080U -/*Reserved. These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/ +/* +* Reserved. These are JEDEC reserved bits and are recommended by JEDEC to + * be programmed to 0x0. +*/ #undef DDR_PHY_MR0_RSVD_6_5_DEFVAL #undef DDR_PHY_MR0_RSVD_6_5_SHIFT #undef DDR_PHY_MR0_RSVD_6_5_MASK -#define DDR_PHY_MR0_RSVD_6_5_DEFVAL 0x00000052 -#define DDR_PHY_MR0_RSVD_6_5_SHIFT 5 -#define DDR_PHY_MR0_RSVD_6_5_MASK 0x00000060U +#define DDR_PHY_MR0_RSVD_6_5_DEFVAL 0x00000052 +#define DDR_PHY_MR0_RSVD_6_5_SHIFT 5 +#define DDR_PHY_MR0_RSVD_6_5_MASK 0x00000060U -/*Built-in Self-Test for RZQ*/ +/* +* Built-in Self-Test for RZQ +*/ #undef DDR_PHY_MR0_RZQI_DEFVAL #undef DDR_PHY_MR0_RZQI_SHIFT #undef DDR_PHY_MR0_RZQI_MASK -#define DDR_PHY_MR0_RZQI_DEFVAL 0x00000052 -#define DDR_PHY_MR0_RZQI_SHIFT 3 -#define DDR_PHY_MR0_RZQI_MASK 0x00000018U +#define DDR_PHY_MR0_RZQI_DEFVAL 0x00000052 +#define DDR_PHY_MR0_RZQI_SHIFT 3 +#define DDR_PHY_MR0_RZQI_MASK 0x00000018U -/*Reserved. These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/ +/* +* Reserved. These are JEDEC reserved bits and are recommended by JEDEC to + * be programmed to 0x0. +*/ #undef DDR_PHY_MR0_RSVD_2_0_DEFVAL #undef DDR_PHY_MR0_RSVD_2_0_SHIFT #undef DDR_PHY_MR0_RSVD_2_0_MASK -#define DDR_PHY_MR0_RSVD_2_0_DEFVAL 0x00000052 -#define DDR_PHY_MR0_RSVD_2_0_SHIFT 0 -#define DDR_PHY_MR0_RSVD_2_0_MASK 0x00000007U +#define DDR_PHY_MR0_RSVD_2_0_DEFVAL 0x00000052 +#define DDR_PHY_MR0_RSVD_2_0_SHIFT 0 +#define DDR_PHY_MR0_RSVD_2_0_MASK 0x00000007U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_MR1_RESERVED_31_8_DEFVAL #undef DDR_PHY_MR1_RESERVED_31_8_SHIFT #undef DDR_PHY_MR1_RESERVED_31_8_MASK -#define DDR_PHY_MR1_RESERVED_31_8_DEFVAL 0x00000004 -#define DDR_PHY_MR1_RESERVED_31_8_SHIFT 8 -#define DDR_PHY_MR1_RESERVED_31_8_MASK 0xFFFFFF00U +#define DDR_PHY_MR1_RESERVED_31_8_DEFVAL 0x00000004 +#define DDR_PHY_MR1_RESERVED_31_8_SHIFT 8 +#define DDR_PHY_MR1_RESERVED_31_8_MASK 0xFFFFFF00U -/*Read Postamble Length*/ +/* +* Read Postamble Length +*/ #undef DDR_PHY_MR1_RDPST_DEFVAL #undef DDR_PHY_MR1_RDPST_SHIFT #undef DDR_PHY_MR1_RDPST_MASK -#define DDR_PHY_MR1_RDPST_DEFVAL 0x00000004 -#define DDR_PHY_MR1_RDPST_SHIFT 7 -#define DDR_PHY_MR1_RDPST_MASK 0x00000080U +#define DDR_PHY_MR1_RDPST_DEFVAL 0x00000004 +#define DDR_PHY_MR1_RDPST_SHIFT 7 +#define DDR_PHY_MR1_RDPST_MASK 0x00000080U -/*Write-recovery for auto-precharge command*/ +/* +* Write-recovery for auto-precharge command +*/ #undef DDR_PHY_MR1_NWR_DEFVAL #undef DDR_PHY_MR1_NWR_SHIFT #undef DDR_PHY_MR1_NWR_MASK -#define DDR_PHY_MR1_NWR_DEFVAL 0x00000004 -#define DDR_PHY_MR1_NWR_SHIFT 4 -#define DDR_PHY_MR1_NWR_MASK 0x00000070U +#define DDR_PHY_MR1_NWR_DEFVAL 0x00000004 +#define DDR_PHY_MR1_NWR_SHIFT 4 +#define DDR_PHY_MR1_NWR_MASK 0x00000070U -/*Read Preamble Length*/ +/* +* Read Preamble Length +*/ #undef DDR_PHY_MR1_RDPRE_DEFVAL #undef DDR_PHY_MR1_RDPRE_SHIFT #undef DDR_PHY_MR1_RDPRE_MASK -#define DDR_PHY_MR1_RDPRE_DEFVAL 0x00000004 -#define DDR_PHY_MR1_RDPRE_SHIFT 3 -#define DDR_PHY_MR1_RDPRE_MASK 0x00000008U +#define DDR_PHY_MR1_RDPRE_DEFVAL 0x00000004 +#define DDR_PHY_MR1_RDPRE_SHIFT 3 +#define DDR_PHY_MR1_RDPRE_MASK 0x00000008U -/*Write Preamble Length*/ +/* +* Write Preamble Length +*/ #undef DDR_PHY_MR1_WRPRE_DEFVAL #undef DDR_PHY_MR1_WRPRE_SHIFT #undef DDR_PHY_MR1_WRPRE_MASK -#define DDR_PHY_MR1_WRPRE_DEFVAL 0x00000004 -#define DDR_PHY_MR1_WRPRE_SHIFT 2 -#define DDR_PHY_MR1_WRPRE_MASK 0x00000004U +#define DDR_PHY_MR1_WRPRE_DEFVAL 0x00000004 +#define DDR_PHY_MR1_WRPRE_SHIFT 2 +#define DDR_PHY_MR1_WRPRE_MASK 0x00000004U -/*Burst Length*/ +/* +* Burst Length +*/ #undef DDR_PHY_MR1_BL_DEFVAL #undef DDR_PHY_MR1_BL_SHIFT #undef DDR_PHY_MR1_BL_MASK -#define DDR_PHY_MR1_BL_DEFVAL 0x00000004 -#define DDR_PHY_MR1_BL_SHIFT 0 -#define DDR_PHY_MR1_BL_MASK 0x00000003U +#define DDR_PHY_MR1_BL_DEFVAL 0x00000004 +#define DDR_PHY_MR1_BL_SHIFT 0 +#define DDR_PHY_MR1_BL_MASK 0x00000003U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_MR2_RESERVED_31_8_DEFVAL #undef DDR_PHY_MR2_RESERVED_31_8_SHIFT #undef DDR_PHY_MR2_RESERVED_31_8_MASK -#define DDR_PHY_MR2_RESERVED_31_8_DEFVAL 0x00000000 -#define DDR_PHY_MR2_RESERVED_31_8_SHIFT 8 -#define DDR_PHY_MR2_RESERVED_31_8_MASK 0xFFFFFF00U +#define DDR_PHY_MR2_RESERVED_31_8_DEFVAL 0x00000000 +#define DDR_PHY_MR2_RESERVED_31_8_SHIFT 8 +#define DDR_PHY_MR2_RESERVED_31_8_MASK 0xFFFFFF00U -/*Write Leveling*/ +/* +* Write Leveling +*/ #undef DDR_PHY_MR2_WRL_DEFVAL #undef DDR_PHY_MR2_WRL_SHIFT #undef DDR_PHY_MR2_WRL_MASK -#define DDR_PHY_MR2_WRL_DEFVAL 0x00000000 -#define DDR_PHY_MR2_WRL_SHIFT 7 -#define DDR_PHY_MR2_WRL_MASK 0x00000080U +#define DDR_PHY_MR2_WRL_DEFVAL 0x00000000 +#define DDR_PHY_MR2_WRL_SHIFT 7 +#define DDR_PHY_MR2_WRL_MASK 0x00000080U -/*Write Latency Set*/ +/* +* Write Latency Set +*/ #undef DDR_PHY_MR2_WLS_DEFVAL #undef DDR_PHY_MR2_WLS_SHIFT #undef DDR_PHY_MR2_WLS_MASK -#define DDR_PHY_MR2_WLS_DEFVAL 0x00000000 -#define DDR_PHY_MR2_WLS_SHIFT 6 -#define DDR_PHY_MR2_WLS_MASK 0x00000040U +#define DDR_PHY_MR2_WLS_DEFVAL 0x00000000 +#define DDR_PHY_MR2_WLS_SHIFT 6 +#define DDR_PHY_MR2_WLS_MASK 0x00000040U -/*Write Latency*/ +/* +* Write Latency +*/ #undef DDR_PHY_MR2_WL_DEFVAL #undef DDR_PHY_MR2_WL_SHIFT #undef DDR_PHY_MR2_WL_MASK -#define DDR_PHY_MR2_WL_DEFVAL 0x00000000 -#define DDR_PHY_MR2_WL_SHIFT 3 -#define DDR_PHY_MR2_WL_MASK 0x00000038U +#define DDR_PHY_MR2_WL_DEFVAL 0x00000000 +#define DDR_PHY_MR2_WL_SHIFT 3 +#define DDR_PHY_MR2_WL_MASK 0x00000038U -/*Read Latency*/ +/* +* Read Latency +*/ #undef DDR_PHY_MR2_RL_DEFVAL #undef DDR_PHY_MR2_RL_SHIFT #undef DDR_PHY_MR2_RL_MASK -#define DDR_PHY_MR2_RL_DEFVAL 0x00000000 -#define DDR_PHY_MR2_RL_SHIFT 0 -#define DDR_PHY_MR2_RL_MASK 0x00000007U +#define DDR_PHY_MR2_RL_DEFVAL 0x00000000 +#define DDR_PHY_MR2_RL_SHIFT 0 +#define DDR_PHY_MR2_RL_MASK 0x00000007U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_MR3_RESERVED_31_8_DEFVAL #undef DDR_PHY_MR3_RESERVED_31_8_SHIFT #undef DDR_PHY_MR3_RESERVED_31_8_MASK -#define DDR_PHY_MR3_RESERVED_31_8_DEFVAL 0x00000031 -#define DDR_PHY_MR3_RESERVED_31_8_SHIFT 8 -#define DDR_PHY_MR3_RESERVED_31_8_MASK 0xFFFFFF00U +#define DDR_PHY_MR3_RESERVED_31_8_DEFVAL 0x00000031 +#define DDR_PHY_MR3_RESERVED_31_8_SHIFT 8 +#define DDR_PHY_MR3_RESERVED_31_8_MASK 0xFFFFFF00U -/*DBI-Write Enable*/ +/* +* DBI-Write Enable +*/ #undef DDR_PHY_MR3_DBIWR_DEFVAL #undef DDR_PHY_MR3_DBIWR_SHIFT #undef DDR_PHY_MR3_DBIWR_MASK -#define DDR_PHY_MR3_DBIWR_DEFVAL 0x00000031 -#define DDR_PHY_MR3_DBIWR_SHIFT 7 -#define DDR_PHY_MR3_DBIWR_MASK 0x00000080U +#define DDR_PHY_MR3_DBIWR_DEFVAL 0x00000031 +#define DDR_PHY_MR3_DBIWR_SHIFT 7 +#define DDR_PHY_MR3_DBIWR_MASK 0x00000080U -/*DBI-Read Enable*/ +/* +* DBI-Read Enable +*/ #undef DDR_PHY_MR3_DBIRD_DEFVAL #undef DDR_PHY_MR3_DBIRD_SHIFT #undef DDR_PHY_MR3_DBIRD_MASK -#define DDR_PHY_MR3_DBIRD_DEFVAL 0x00000031 -#define DDR_PHY_MR3_DBIRD_SHIFT 6 -#define DDR_PHY_MR3_DBIRD_MASK 0x00000040U +#define DDR_PHY_MR3_DBIRD_DEFVAL 0x00000031 +#define DDR_PHY_MR3_DBIRD_SHIFT 6 +#define DDR_PHY_MR3_DBIRD_MASK 0x00000040U -/*Pull-down Drive Strength*/ +/* +* Pull-down Drive Strength +*/ #undef DDR_PHY_MR3_PDDS_DEFVAL #undef DDR_PHY_MR3_PDDS_SHIFT #undef DDR_PHY_MR3_PDDS_MASK -#define DDR_PHY_MR3_PDDS_DEFVAL 0x00000031 -#define DDR_PHY_MR3_PDDS_SHIFT 3 -#define DDR_PHY_MR3_PDDS_MASK 0x00000038U +#define DDR_PHY_MR3_PDDS_DEFVAL 0x00000031 +#define DDR_PHY_MR3_PDDS_SHIFT 3 +#define DDR_PHY_MR3_PDDS_MASK 0x00000038U -/*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/ +/* +* These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. +*/ #undef DDR_PHY_MR3_RSVD_DEFVAL #undef DDR_PHY_MR3_RSVD_SHIFT #undef DDR_PHY_MR3_RSVD_MASK -#define DDR_PHY_MR3_RSVD_DEFVAL 0x00000031 -#define DDR_PHY_MR3_RSVD_SHIFT 2 -#define DDR_PHY_MR3_RSVD_MASK 0x00000004U +#define DDR_PHY_MR3_RSVD_DEFVAL 0x00000031 +#define DDR_PHY_MR3_RSVD_SHIFT 2 +#define DDR_PHY_MR3_RSVD_MASK 0x00000004U -/*Write Postamble Length*/ +/* +* Write Postamble Length +*/ #undef DDR_PHY_MR3_WRPST_DEFVAL #undef DDR_PHY_MR3_WRPST_SHIFT #undef DDR_PHY_MR3_WRPST_MASK -#define DDR_PHY_MR3_WRPST_DEFVAL 0x00000031 -#define DDR_PHY_MR3_WRPST_SHIFT 1 -#define DDR_PHY_MR3_WRPST_MASK 0x00000002U +#define DDR_PHY_MR3_WRPST_DEFVAL 0x00000031 +#define DDR_PHY_MR3_WRPST_SHIFT 1 +#define DDR_PHY_MR3_WRPST_MASK 0x00000002U -/*Pull-up Calibration Point*/ +/* +* Pull-up Calibration Point +*/ #undef DDR_PHY_MR3_PUCAL_DEFVAL #undef DDR_PHY_MR3_PUCAL_SHIFT #undef DDR_PHY_MR3_PUCAL_MASK -#define DDR_PHY_MR3_PUCAL_DEFVAL 0x00000031 -#define DDR_PHY_MR3_PUCAL_SHIFT 0 -#define DDR_PHY_MR3_PUCAL_MASK 0x00000001U +#define DDR_PHY_MR3_PUCAL_DEFVAL 0x00000031 +#define DDR_PHY_MR3_PUCAL_SHIFT 0 +#define DDR_PHY_MR3_PUCAL_MASK 0x00000001U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_MR4_RESERVED_31_16_DEFVAL #undef DDR_PHY_MR4_RESERVED_31_16_SHIFT #undef DDR_PHY_MR4_RESERVED_31_16_MASK -#define DDR_PHY_MR4_RESERVED_31_16_DEFVAL 0x00000000 -#define DDR_PHY_MR4_RESERVED_31_16_SHIFT 16 -#define DDR_PHY_MR4_RESERVED_31_16_MASK 0xFFFF0000U +#define DDR_PHY_MR4_RESERVED_31_16_DEFVAL 0x00000000 +#define DDR_PHY_MR4_RESERVED_31_16_SHIFT 16 +#define DDR_PHY_MR4_RESERVED_31_16_MASK 0xFFFF0000U -/*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/ +/* +* These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. +*/ #undef DDR_PHY_MR4_RSVD_15_13_DEFVAL #undef DDR_PHY_MR4_RSVD_15_13_SHIFT #undef DDR_PHY_MR4_RSVD_15_13_MASK -#define DDR_PHY_MR4_RSVD_15_13_DEFVAL 0x00000000 -#define DDR_PHY_MR4_RSVD_15_13_SHIFT 13 -#define DDR_PHY_MR4_RSVD_15_13_MASK 0x0000E000U +#define DDR_PHY_MR4_RSVD_15_13_DEFVAL 0x00000000 +#define DDR_PHY_MR4_RSVD_15_13_SHIFT 13 +#define DDR_PHY_MR4_RSVD_15_13_MASK 0x0000E000U -/*Write Preamble*/ +/* +* Write Preamble +*/ #undef DDR_PHY_MR4_WRP_DEFVAL #undef DDR_PHY_MR4_WRP_SHIFT #undef DDR_PHY_MR4_WRP_MASK -#define DDR_PHY_MR4_WRP_DEFVAL 0x00000000 -#define DDR_PHY_MR4_WRP_SHIFT 12 -#define DDR_PHY_MR4_WRP_MASK 0x00001000U +#define DDR_PHY_MR4_WRP_DEFVAL 0x00000000 +#define DDR_PHY_MR4_WRP_SHIFT 12 +#define DDR_PHY_MR4_WRP_MASK 0x00001000U -/*Read Preamble*/ +/* +* Read Preamble +*/ #undef DDR_PHY_MR4_RDP_DEFVAL #undef DDR_PHY_MR4_RDP_SHIFT #undef DDR_PHY_MR4_RDP_MASK -#define DDR_PHY_MR4_RDP_DEFVAL 0x00000000 -#define DDR_PHY_MR4_RDP_SHIFT 11 -#define DDR_PHY_MR4_RDP_MASK 0x00000800U +#define DDR_PHY_MR4_RDP_DEFVAL 0x00000000 +#define DDR_PHY_MR4_RDP_SHIFT 11 +#define DDR_PHY_MR4_RDP_MASK 0x00000800U -/*Read Preamble Training Mode*/ +/* +* Read Preamble Training Mode +*/ #undef DDR_PHY_MR4_RPTM_DEFVAL #undef DDR_PHY_MR4_RPTM_SHIFT #undef DDR_PHY_MR4_RPTM_MASK -#define DDR_PHY_MR4_RPTM_DEFVAL 0x00000000 -#define DDR_PHY_MR4_RPTM_SHIFT 10 -#define DDR_PHY_MR4_RPTM_MASK 0x00000400U +#define DDR_PHY_MR4_RPTM_DEFVAL 0x00000000 +#define DDR_PHY_MR4_RPTM_SHIFT 10 +#define DDR_PHY_MR4_RPTM_MASK 0x00000400U -/*Self Refresh Abort*/ +/* +* Self Refresh Abort +*/ #undef DDR_PHY_MR4_SRA_DEFVAL #undef DDR_PHY_MR4_SRA_SHIFT #undef DDR_PHY_MR4_SRA_MASK -#define DDR_PHY_MR4_SRA_DEFVAL 0x00000000 -#define DDR_PHY_MR4_SRA_SHIFT 9 -#define DDR_PHY_MR4_SRA_MASK 0x00000200U +#define DDR_PHY_MR4_SRA_DEFVAL 0x00000000 +#define DDR_PHY_MR4_SRA_SHIFT 9 +#define DDR_PHY_MR4_SRA_MASK 0x00000200U -/*CS to Command Latency Mode*/ +/* +* CS to Command Latency Mode +*/ #undef DDR_PHY_MR4_CS2CMDL_DEFVAL #undef DDR_PHY_MR4_CS2CMDL_SHIFT #undef DDR_PHY_MR4_CS2CMDL_MASK -#define DDR_PHY_MR4_CS2CMDL_DEFVAL 0x00000000 -#define DDR_PHY_MR4_CS2CMDL_SHIFT 6 -#define DDR_PHY_MR4_CS2CMDL_MASK 0x000001C0U +#define DDR_PHY_MR4_CS2CMDL_DEFVAL 0x00000000 +#define DDR_PHY_MR4_CS2CMDL_SHIFT 6 +#define DDR_PHY_MR4_CS2CMDL_MASK 0x000001C0U -/*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/ +/* +* These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. +*/ #undef DDR_PHY_MR4_RSVD1_DEFVAL #undef DDR_PHY_MR4_RSVD1_SHIFT #undef DDR_PHY_MR4_RSVD1_MASK -#define DDR_PHY_MR4_RSVD1_DEFVAL 0x00000000 -#define DDR_PHY_MR4_RSVD1_SHIFT 5 -#define DDR_PHY_MR4_RSVD1_MASK 0x00000020U +#define DDR_PHY_MR4_RSVD1_DEFVAL 0x00000000 +#define DDR_PHY_MR4_RSVD1_SHIFT 5 +#define DDR_PHY_MR4_RSVD1_MASK 0x00000020U -/*Internal VREF Monitor*/ +/* +* Internal VREF Monitor +*/ #undef DDR_PHY_MR4_IVM_DEFVAL #undef DDR_PHY_MR4_IVM_SHIFT #undef DDR_PHY_MR4_IVM_MASK -#define DDR_PHY_MR4_IVM_DEFVAL 0x00000000 -#define DDR_PHY_MR4_IVM_SHIFT 4 -#define DDR_PHY_MR4_IVM_MASK 0x00000010U +#define DDR_PHY_MR4_IVM_DEFVAL 0x00000000 +#define DDR_PHY_MR4_IVM_SHIFT 4 +#define DDR_PHY_MR4_IVM_MASK 0x00000010U -/*Temperature Controlled Refresh Mode*/ +/* +* Temperature Controlled Refresh Mode +*/ #undef DDR_PHY_MR4_TCRM_DEFVAL #undef DDR_PHY_MR4_TCRM_SHIFT #undef DDR_PHY_MR4_TCRM_MASK -#define DDR_PHY_MR4_TCRM_DEFVAL 0x00000000 -#define DDR_PHY_MR4_TCRM_SHIFT 3 -#define DDR_PHY_MR4_TCRM_MASK 0x00000008U +#define DDR_PHY_MR4_TCRM_DEFVAL 0x00000000 +#define DDR_PHY_MR4_TCRM_SHIFT 3 +#define DDR_PHY_MR4_TCRM_MASK 0x00000008U -/*Temperature Controlled Refresh Range*/ +/* +* Temperature Controlled Refresh Range +*/ #undef DDR_PHY_MR4_TCRR_DEFVAL #undef DDR_PHY_MR4_TCRR_SHIFT #undef DDR_PHY_MR4_TCRR_MASK -#define DDR_PHY_MR4_TCRR_DEFVAL 0x00000000 -#define DDR_PHY_MR4_TCRR_SHIFT 2 -#define DDR_PHY_MR4_TCRR_MASK 0x00000004U +#define DDR_PHY_MR4_TCRR_DEFVAL 0x00000000 +#define DDR_PHY_MR4_TCRR_SHIFT 2 +#define DDR_PHY_MR4_TCRR_MASK 0x00000004U -/*Maximum Power Down Mode*/ +/* +* Maximum Power Down Mode +*/ #undef DDR_PHY_MR4_MPDM_DEFVAL #undef DDR_PHY_MR4_MPDM_SHIFT #undef DDR_PHY_MR4_MPDM_MASK -#define DDR_PHY_MR4_MPDM_DEFVAL 0x00000000 -#define DDR_PHY_MR4_MPDM_SHIFT 1 -#define DDR_PHY_MR4_MPDM_MASK 0x00000002U +#define DDR_PHY_MR4_MPDM_DEFVAL 0x00000000 +#define DDR_PHY_MR4_MPDM_SHIFT 1 +#define DDR_PHY_MR4_MPDM_MASK 0x00000002U -/*This is a JEDEC reserved bit and is recommended by JEDEC to be programmed to 0x0.*/ +/* +* This is a JEDEC reserved bit and is recommended by JEDEC to be programme + * d to 0x0. +*/ #undef DDR_PHY_MR4_RSVD_0_DEFVAL #undef DDR_PHY_MR4_RSVD_0_SHIFT #undef DDR_PHY_MR4_RSVD_0_MASK -#define DDR_PHY_MR4_RSVD_0_DEFVAL 0x00000000 -#define DDR_PHY_MR4_RSVD_0_SHIFT 0 -#define DDR_PHY_MR4_RSVD_0_MASK 0x00000001U +#define DDR_PHY_MR4_RSVD_0_DEFVAL 0x00000000 +#define DDR_PHY_MR4_RSVD_0_SHIFT 0 +#define DDR_PHY_MR4_RSVD_0_MASK 0x00000001U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_MR5_RESERVED_31_16_DEFVAL #undef DDR_PHY_MR5_RESERVED_31_16_SHIFT #undef DDR_PHY_MR5_RESERVED_31_16_MASK -#define DDR_PHY_MR5_RESERVED_31_16_DEFVAL 0x00000000 -#define DDR_PHY_MR5_RESERVED_31_16_SHIFT 16 -#define DDR_PHY_MR5_RESERVED_31_16_MASK 0xFFFF0000U +#define DDR_PHY_MR5_RESERVED_31_16_DEFVAL 0x00000000 +#define DDR_PHY_MR5_RESERVED_31_16_SHIFT 16 +#define DDR_PHY_MR5_RESERVED_31_16_MASK 0xFFFF0000U -/*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/ +/* +* These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. +*/ #undef DDR_PHY_MR5_RSVD_DEFVAL #undef DDR_PHY_MR5_RSVD_SHIFT #undef DDR_PHY_MR5_RSVD_MASK -#define DDR_PHY_MR5_RSVD_DEFVAL 0x00000000 -#define DDR_PHY_MR5_RSVD_SHIFT 13 -#define DDR_PHY_MR5_RSVD_MASK 0x0000E000U +#define DDR_PHY_MR5_RSVD_DEFVAL 0x00000000 +#define DDR_PHY_MR5_RSVD_SHIFT 13 +#define DDR_PHY_MR5_RSVD_MASK 0x0000E000U -/*Read DBI*/ +/* +* Read DBI +*/ #undef DDR_PHY_MR5_RDBI_DEFVAL #undef DDR_PHY_MR5_RDBI_SHIFT #undef DDR_PHY_MR5_RDBI_MASK -#define DDR_PHY_MR5_RDBI_DEFVAL 0x00000000 -#define DDR_PHY_MR5_RDBI_SHIFT 12 -#define DDR_PHY_MR5_RDBI_MASK 0x00001000U +#define DDR_PHY_MR5_RDBI_DEFVAL 0x00000000 +#define DDR_PHY_MR5_RDBI_SHIFT 12 +#define DDR_PHY_MR5_RDBI_MASK 0x00001000U -/*Write DBI*/ +/* +* Write DBI +*/ #undef DDR_PHY_MR5_WDBI_DEFVAL #undef DDR_PHY_MR5_WDBI_SHIFT #undef DDR_PHY_MR5_WDBI_MASK -#define DDR_PHY_MR5_WDBI_DEFVAL 0x00000000 -#define DDR_PHY_MR5_WDBI_SHIFT 11 -#define DDR_PHY_MR5_WDBI_MASK 0x00000800U +#define DDR_PHY_MR5_WDBI_DEFVAL 0x00000000 +#define DDR_PHY_MR5_WDBI_SHIFT 11 +#define DDR_PHY_MR5_WDBI_MASK 0x00000800U -/*Data Mask*/ +/* +* Data Mask +*/ #undef DDR_PHY_MR5_DM_DEFVAL #undef DDR_PHY_MR5_DM_SHIFT #undef DDR_PHY_MR5_DM_MASK -#define DDR_PHY_MR5_DM_DEFVAL 0x00000000 -#define DDR_PHY_MR5_DM_SHIFT 10 -#define DDR_PHY_MR5_DM_MASK 0x00000400U +#define DDR_PHY_MR5_DM_DEFVAL 0x00000000 +#define DDR_PHY_MR5_DM_SHIFT 10 +#define DDR_PHY_MR5_DM_MASK 0x00000400U -/*CA Parity Persistent Error*/ +/* +* CA Parity Persistent Error +*/ #undef DDR_PHY_MR5_CAPPE_DEFVAL #undef DDR_PHY_MR5_CAPPE_SHIFT #undef DDR_PHY_MR5_CAPPE_MASK -#define DDR_PHY_MR5_CAPPE_DEFVAL 0x00000000 -#define DDR_PHY_MR5_CAPPE_SHIFT 9 -#define DDR_PHY_MR5_CAPPE_MASK 0x00000200U +#define DDR_PHY_MR5_CAPPE_DEFVAL 0x00000000 +#define DDR_PHY_MR5_CAPPE_SHIFT 9 +#define DDR_PHY_MR5_CAPPE_MASK 0x00000200U -/*RTT_PARK*/ +/* +* RTT_PARK +*/ #undef DDR_PHY_MR5_RTTPARK_DEFVAL #undef DDR_PHY_MR5_RTTPARK_SHIFT #undef DDR_PHY_MR5_RTTPARK_MASK -#define DDR_PHY_MR5_RTTPARK_DEFVAL 0x00000000 -#define DDR_PHY_MR5_RTTPARK_SHIFT 6 -#define DDR_PHY_MR5_RTTPARK_MASK 0x000001C0U +#define DDR_PHY_MR5_RTTPARK_DEFVAL 0x00000000 +#define DDR_PHY_MR5_RTTPARK_SHIFT 6 +#define DDR_PHY_MR5_RTTPARK_MASK 0x000001C0U -/*ODT Input Buffer during Power Down mode*/ +/* +* ODT Input Buffer during Power Down mode +*/ #undef DDR_PHY_MR5_ODTIBPD_DEFVAL #undef DDR_PHY_MR5_ODTIBPD_SHIFT #undef DDR_PHY_MR5_ODTIBPD_MASK -#define DDR_PHY_MR5_ODTIBPD_DEFVAL 0x00000000 -#define DDR_PHY_MR5_ODTIBPD_SHIFT 5 -#define DDR_PHY_MR5_ODTIBPD_MASK 0x00000020U +#define DDR_PHY_MR5_ODTIBPD_DEFVAL 0x00000000 +#define DDR_PHY_MR5_ODTIBPD_SHIFT 5 +#define DDR_PHY_MR5_ODTIBPD_MASK 0x00000020U -/*C/A Parity Error Status*/ +/* +* C/A Parity Error Status +*/ #undef DDR_PHY_MR5_CAPES_DEFVAL #undef DDR_PHY_MR5_CAPES_SHIFT #undef DDR_PHY_MR5_CAPES_MASK -#define DDR_PHY_MR5_CAPES_DEFVAL 0x00000000 -#define DDR_PHY_MR5_CAPES_SHIFT 4 -#define DDR_PHY_MR5_CAPES_MASK 0x00000010U +#define DDR_PHY_MR5_CAPES_DEFVAL 0x00000000 +#define DDR_PHY_MR5_CAPES_SHIFT 4 +#define DDR_PHY_MR5_CAPES_MASK 0x00000010U -/*CRC Error Clear*/ +/* +* CRC Error Clear +*/ #undef DDR_PHY_MR5_CRCEC_DEFVAL #undef DDR_PHY_MR5_CRCEC_SHIFT #undef DDR_PHY_MR5_CRCEC_MASK -#define DDR_PHY_MR5_CRCEC_DEFVAL 0x00000000 -#define DDR_PHY_MR5_CRCEC_SHIFT 3 -#define DDR_PHY_MR5_CRCEC_MASK 0x00000008U +#define DDR_PHY_MR5_CRCEC_DEFVAL 0x00000000 +#define DDR_PHY_MR5_CRCEC_SHIFT 3 +#define DDR_PHY_MR5_CRCEC_MASK 0x00000008U -/*C/A Parity Latency Mode*/ +/* +* C/A Parity Latency Mode +*/ #undef DDR_PHY_MR5_CAPM_DEFVAL #undef DDR_PHY_MR5_CAPM_SHIFT #undef DDR_PHY_MR5_CAPM_MASK -#define DDR_PHY_MR5_CAPM_DEFVAL 0x00000000 -#define DDR_PHY_MR5_CAPM_SHIFT 0 -#define DDR_PHY_MR5_CAPM_MASK 0x00000007U +#define DDR_PHY_MR5_CAPM_DEFVAL 0x00000000 +#define DDR_PHY_MR5_CAPM_SHIFT 0 +#define DDR_PHY_MR5_CAPM_MASK 0x00000007U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_MR6_RESERVED_31_16_DEFVAL #undef DDR_PHY_MR6_RESERVED_31_16_SHIFT #undef DDR_PHY_MR6_RESERVED_31_16_MASK -#define DDR_PHY_MR6_RESERVED_31_16_DEFVAL 0x00000000 -#define DDR_PHY_MR6_RESERVED_31_16_SHIFT 16 -#define DDR_PHY_MR6_RESERVED_31_16_MASK 0xFFFF0000U +#define DDR_PHY_MR6_RESERVED_31_16_DEFVAL 0x00000000 +#define DDR_PHY_MR6_RESERVED_31_16_SHIFT 16 +#define DDR_PHY_MR6_RESERVED_31_16_MASK 0xFFFF0000U -/*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/ +/* +* These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. +*/ #undef DDR_PHY_MR6_RSVD_15_13_DEFVAL #undef DDR_PHY_MR6_RSVD_15_13_SHIFT #undef DDR_PHY_MR6_RSVD_15_13_MASK -#define DDR_PHY_MR6_RSVD_15_13_DEFVAL 0x00000000 -#define DDR_PHY_MR6_RSVD_15_13_SHIFT 13 -#define DDR_PHY_MR6_RSVD_15_13_MASK 0x0000E000U +#define DDR_PHY_MR6_RSVD_15_13_DEFVAL 0x00000000 +#define DDR_PHY_MR6_RSVD_15_13_SHIFT 13 +#define DDR_PHY_MR6_RSVD_15_13_MASK 0x0000E000U -/*CAS_n to CAS_n command delay for same bank group (tCCD_L)*/ +/* +* CAS_n to CAS_n command delay for same bank group (tCCD_L) +*/ #undef DDR_PHY_MR6_TCCDL_DEFVAL #undef DDR_PHY_MR6_TCCDL_SHIFT #undef DDR_PHY_MR6_TCCDL_MASK -#define DDR_PHY_MR6_TCCDL_DEFVAL 0x00000000 -#define DDR_PHY_MR6_TCCDL_SHIFT 10 -#define DDR_PHY_MR6_TCCDL_MASK 0x00001C00U +#define DDR_PHY_MR6_TCCDL_DEFVAL 0x00000000 +#define DDR_PHY_MR6_TCCDL_SHIFT 10 +#define DDR_PHY_MR6_TCCDL_MASK 0x00001C00U -/*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/ +/* +* These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. +*/ #undef DDR_PHY_MR6_RSVD_9_8_DEFVAL #undef DDR_PHY_MR6_RSVD_9_8_SHIFT #undef DDR_PHY_MR6_RSVD_9_8_MASK -#define DDR_PHY_MR6_RSVD_9_8_DEFVAL 0x00000000 -#define DDR_PHY_MR6_RSVD_9_8_SHIFT 8 -#define DDR_PHY_MR6_RSVD_9_8_MASK 0x00000300U +#define DDR_PHY_MR6_RSVD_9_8_DEFVAL 0x00000000 +#define DDR_PHY_MR6_RSVD_9_8_SHIFT 8 +#define DDR_PHY_MR6_RSVD_9_8_MASK 0x00000300U -/*VrefDQ Training Enable*/ +/* +* VrefDQ Training Enable +*/ #undef DDR_PHY_MR6_VDDQTEN_DEFVAL #undef DDR_PHY_MR6_VDDQTEN_SHIFT #undef DDR_PHY_MR6_VDDQTEN_MASK -#define DDR_PHY_MR6_VDDQTEN_DEFVAL 0x00000000 -#define DDR_PHY_MR6_VDDQTEN_SHIFT 7 -#define DDR_PHY_MR6_VDDQTEN_MASK 0x00000080U +#define DDR_PHY_MR6_VDDQTEN_DEFVAL 0x00000000 +#define DDR_PHY_MR6_VDDQTEN_SHIFT 7 +#define DDR_PHY_MR6_VDDQTEN_MASK 0x00000080U -/*VrefDQ Training Range*/ +/* +* VrefDQ Training Range +*/ #undef DDR_PHY_MR6_VDQTRG_DEFVAL #undef DDR_PHY_MR6_VDQTRG_SHIFT #undef DDR_PHY_MR6_VDQTRG_MASK -#define DDR_PHY_MR6_VDQTRG_DEFVAL 0x00000000 -#define DDR_PHY_MR6_VDQTRG_SHIFT 6 -#define DDR_PHY_MR6_VDQTRG_MASK 0x00000040U +#define DDR_PHY_MR6_VDQTRG_DEFVAL 0x00000000 +#define DDR_PHY_MR6_VDQTRG_SHIFT 6 +#define DDR_PHY_MR6_VDQTRG_MASK 0x00000040U -/*VrefDQ Training Values*/ +/* +* VrefDQ Training Values +*/ #undef DDR_PHY_MR6_VDQTVAL_DEFVAL #undef DDR_PHY_MR6_VDQTVAL_SHIFT #undef DDR_PHY_MR6_VDQTVAL_MASK -#define DDR_PHY_MR6_VDQTVAL_DEFVAL 0x00000000 -#define DDR_PHY_MR6_VDQTVAL_SHIFT 0 -#define DDR_PHY_MR6_VDQTVAL_MASK 0x0000003FU +#define DDR_PHY_MR6_VDQTVAL_DEFVAL 0x00000000 +#define DDR_PHY_MR6_VDQTVAL_SHIFT 0 +#define DDR_PHY_MR6_VDQTVAL_MASK 0x0000003FU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_MR11_RESERVED_31_8_DEFVAL #undef DDR_PHY_MR11_RESERVED_31_8_SHIFT #undef DDR_PHY_MR11_RESERVED_31_8_MASK -#define DDR_PHY_MR11_RESERVED_31_8_DEFVAL 0x00000000 -#define DDR_PHY_MR11_RESERVED_31_8_SHIFT 8 -#define DDR_PHY_MR11_RESERVED_31_8_MASK 0xFFFFFF00U +#define DDR_PHY_MR11_RESERVED_31_8_DEFVAL 0x00000000 +#define DDR_PHY_MR11_RESERVED_31_8_SHIFT 8 +#define DDR_PHY_MR11_RESERVED_31_8_MASK 0xFFFFFF00U -/*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/ +/* +* These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. +*/ #undef DDR_PHY_MR11_RSVD_DEFVAL #undef DDR_PHY_MR11_RSVD_SHIFT #undef DDR_PHY_MR11_RSVD_MASK -#define DDR_PHY_MR11_RSVD_DEFVAL 0x00000000 -#define DDR_PHY_MR11_RSVD_SHIFT 3 -#define DDR_PHY_MR11_RSVD_MASK 0x000000F8U +#define DDR_PHY_MR11_RSVD_DEFVAL 0x00000000 +#define DDR_PHY_MR11_RSVD_SHIFT 3 +#define DDR_PHY_MR11_RSVD_MASK 0x000000F8U -/*Power Down Control*/ +/* +* Power Down Control +*/ #undef DDR_PHY_MR11_PDCTL_DEFVAL #undef DDR_PHY_MR11_PDCTL_SHIFT #undef DDR_PHY_MR11_PDCTL_MASK -#define DDR_PHY_MR11_PDCTL_DEFVAL 0x00000000 -#define DDR_PHY_MR11_PDCTL_SHIFT 2 -#define DDR_PHY_MR11_PDCTL_MASK 0x00000004U +#define DDR_PHY_MR11_PDCTL_DEFVAL 0x00000000 +#define DDR_PHY_MR11_PDCTL_SHIFT 2 +#define DDR_PHY_MR11_PDCTL_MASK 0x00000004U -/*DQ Bus Receiver On-Die-Termination*/ +/* +* DQ Bus Receiver On-Die-Termination +*/ #undef DDR_PHY_MR11_DQODT_DEFVAL #undef DDR_PHY_MR11_DQODT_SHIFT #undef DDR_PHY_MR11_DQODT_MASK -#define DDR_PHY_MR11_DQODT_DEFVAL 0x00000000 -#define DDR_PHY_MR11_DQODT_SHIFT 0 -#define DDR_PHY_MR11_DQODT_MASK 0x00000003U +#define DDR_PHY_MR11_DQODT_DEFVAL 0x00000000 +#define DDR_PHY_MR11_DQODT_SHIFT 0 +#define DDR_PHY_MR11_DQODT_MASK 0x00000003U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_MR12_RESERVED_31_8_DEFVAL #undef DDR_PHY_MR12_RESERVED_31_8_SHIFT #undef DDR_PHY_MR12_RESERVED_31_8_MASK -#define DDR_PHY_MR12_RESERVED_31_8_DEFVAL 0x0000004D -#define DDR_PHY_MR12_RESERVED_31_8_SHIFT 8 -#define DDR_PHY_MR12_RESERVED_31_8_MASK 0xFFFFFF00U +#define DDR_PHY_MR12_RESERVED_31_8_DEFVAL 0x0000004D +#define DDR_PHY_MR12_RESERVED_31_8_SHIFT 8 +#define DDR_PHY_MR12_RESERVED_31_8_MASK 0xFFFFFF00U -/*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/ +/* +* These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. +*/ #undef DDR_PHY_MR12_RSVD_DEFVAL #undef DDR_PHY_MR12_RSVD_SHIFT #undef DDR_PHY_MR12_RSVD_MASK -#define DDR_PHY_MR12_RSVD_DEFVAL 0x0000004D -#define DDR_PHY_MR12_RSVD_SHIFT 7 -#define DDR_PHY_MR12_RSVD_MASK 0x00000080U +#define DDR_PHY_MR12_RSVD_DEFVAL 0x0000004D +#define DDR_PHY_MR12_RSVD_SHIFT 7 +#define DDR_PHY_MR12_RSVD_MASK 0x00000080U -/*VREF_CA Range Select.*/ +/* +* VREF_CA Range Select. +*/ #undef DDR_PHY_MR12_VR_CA_DEFVAL #undef DDR_PHY_MR12_VR_CA_SHIFT #undef DDR_PHY_MR12_VR_CA_MASK -#define DDR_PHY_MR12_VR_CA_DEFVAL 0x0000004D -#define DDR_PHY_MR12_VR_CA_SHIFT 6 -#define DDR_PHY_MR12_VR_CA_MASK 0x00000040U +#define DDR_PHY_MR12_VR_CA_DEFVAL 0x0000004D +#define DDR_PHY_MR12_VR_CA_SHIFT 6 +#define DDR_PHY_MR12_VR_CA_MASK 0x00000040U -/*Controls the VREF(ca) levels for Frequency-Set-Point[1:0].*/ +/* +* Controls the VREF(ca) levels for Frequency-Set-Point[1:0]. +*/ #undef DDR_PHY_MR12_VREF_CA_DEFVAL #undef DDR_PHY_MR12_VREF_CA_SHIFT #undef DDR_PHY_MR12_VREF_CA_MASK -#define DDR_PHY_MR12_VREF_CA_DEFVAL 0x0000004D -#define DDR_PHY_MR12_VREF_CA_SHIFT 0 -#define DDR_PHY_MR12_VREF_CA_MASK 0x0000003FU +#define DDR_PHY_MR12_VREF_CA_DEFVAL 0x0000004D +#define DDR_PHY_MR12_VREF_CA_SHIFT 0 +#define DDR_PHY_MR12_VREF_CA_MASK 0x0000003FU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_MR13_RESERVED_31_8_DEFVAL #undef DDR_PHY_MR13_RESERVED_31_8_SHIFT #undef DDR_PHY_MR13_RESERVED_31_8_MASK -#define DDR_PHY_MR13_RESERVED_31_8_DEFVAL 0x00000000 -#define DDR_PHY_MR13_RESERVED_31_8_SHIFT 8 -#define DDR_PHY_MR13_RESERVED_31_8_MASK 0xFFFFFF00U +#define DDR_PHY_MR13_RESERVED_31_8_DEFVAL 0x00000000 +#define DDR_PHY_MR13_RESERVED_31_8_SHIFT 8 +#define DDR_PHY_MR13_RESERVED_31_8_MASK 0xFFFFFF00U -/*Frequency Set Point Operation Mode*/ +/* +* Frequency Set Point Operation Mode +*/ #undef DDR_PHY_MR13_FSPOP_DEFVAL #undef DDR_PHY_MR13_FSPOP_SHIFT #undef DDR_PHY_MR13_FSPOP_MASK -#define DDR_PHY_MR13_FSPOP_DEFVAL 0x00000000 -#define DDR_PHY_MR13_FSPOP_SHIFT 7 -#define DDR_PHY_MR13_FSPOP_MASK 0x00000080U +#define DDR_PHY_MR13_FSPOP_DEFVAL 0x00000000 +#define DDR_PHY_MR13_FSPOP_SHIFT 7 +#define DDR_PHY_MR13_FSPOP_MASK 0x00000080U -/*Frequency Set Point Write Enable*/ +/* +* Frequency Set Point Write Enable +*/ #undef DDR_PHY_MR13_FSPWR_DEFVAL #undef DDR_PHY_MR13_FSPWR_SHIFT #undef DDR_PHY_MR13_FSPWR_MASK -#define DDR_PHY_MR13_FSPWR_DEFVAL 0x00000000 -#define DDR_PHY_MR13_FSPWR_SHIFT 6 -#define DDR_PHY_MR13_FSPWR_MASK 0x00000040U +#define DDR_PHY_MR13_FSPWR_DEFVAL 0x00000000 +#define DDR_PHY_MR13_FSPWR_SHIFT 6 +#define DDR_PHY_MR13_FSPWR_MASK 0x00000040U -/*Data Mask Enable*/ +/* +* Data Mask Enable +*/ #undef DDR_PHY_MR13_DMD_DEFVAL #undef DDR_PHY_MR13_DMD_SHIFT #undef DDR_PHY_MR13_DMD_MASK -#define DDR_PHY_MR13_DMD_DEFVAL 0x00000000 -#define DDR_PHY_MR13_DMD_SHIFT 5 -#define DDR_PHY_MR13_DMD_MASK 0x00000020U +#define DDR_PHY_MR13_DMD_DEFVAL 0x00000000 +#define DDR_PHY_MR13_DMD_SHIFT 5 +#define DDR_PHY_MR13_DMD_MASK 0x00000020U -/*Refresh Rate Option*/ +/* +* Refresh Rate Option +*/ #undef DDR_PHY_MR13_RRO_DEFVAL #undef DDR_PHY_MR13_RRO_SHIFT #undef DDR_PHY_MR13_RRO_MASK -#define DDR_PHY_MR13_RRO_DEFVAL 0x00000000 -#define DDR_PHY_MR13_RRO_SHIFT 4 -#define DDR_PHY_MR13_RRO_MASK 0x00000010U +#define DDR_PHY_MR13_RRO_DEFVAL 0x00000000 +#define DDR_PHY_MR13_RRO_SHIFT 4 +#define DDR_PHY_MR13_RRO_MASK 0x00000010U -/*VREF Current Generator*/ +/* +* VREF Current Generator +*/ #undef DDR_PHY_MR13_VRCG_DEFVAL #undef DDR_PHY_MR13_VRCG_SHIFT #undef DDR_PHY_MR13_VRCG_MASK -#define DDR_PHY_MR13_VRCG_DEFVAL 0x00000000 -#define DDR_PHY_MR13_VRCG_SHIFT 3 -#define DDR_PHY_MR13_VRCG_MASK 0x00000008U +#define DDR_PHY_MR13_VRCG_DEFVAL 0x00000000 +#define DDR_PHY_MR13_VRCG_SHIFT 3 +#define DDR_PHY_MR13_VRCG_MASK 0x00000008U -/*VREF Output*/ +/* +* VREF Output +*/ #undef DDR_PHY_MR13_VRO_DEFVAL #undef DDR_PHY_MR13_VRO_SHIFT #undef DDR_PHY_MR13_VRO_MASK -#define DDR_PHY_MR13_VRO_DEFVAL 0x00000000 -#define DDR_PHY_MR13_VRO_SHIFT 2 -#define DDR_PHY_MR13_VRO_MASK 0x00000004U +#define DDR_PHY_MR13_VRO_DEFVAL 0x00000000 +#define DDR_PHY_MR13_VRO_SHIFT 2 +#define DDR_PHY_MR13_VRO_MASK 0x00000004U -/*Read Preamble Training Mode*/ +/* +* Read Preamble Training Mode +*/ #undef DDR_PHY_MR13_RPT_DEFVAL #undef DDR_PHY_MR13_RPT_SHIFT #undef DDR_PHY_MR13_RPT_MASK -#define DDR_PHY_MR13_RPT_DEFVAL 0x00000000 -#define DDR_PHY_MR13_RPT_SHIFT 1 -#define DDR_PHY_MR13_RPT_MASK 0x00000002U +#define DDR_PHY_MR13_RPT_DEFVAL 0x00000000 +#define DDR_PHY_MR13_RPT_SHIFT 1 +#define DDR_PHY_MR13_RPT_MASK 0x00000002U -/*Command Bus Training*/ +/* +* Command Bus Training +*/ #undef DDR_PHY_MR13_CBT_DEFVAL #undef DDR_PHY_MR13_CBT_SHIFT #undef DDR_PHY_MR13_CBT_MASK -#define DDR_PHY_MR13_CBT_DEFVAL 0x00000000 -#define DDR_PHY_MR13_CBT_SHIFT 0 -#define DDR_PHY_MR13_CBT_MASK 0x00000001U +#define DDR_PHY_MR13_CBT_DEFVAL 0x00000000 +#define DDR_PHY_MR13_CBT_SHIFT 0 +#define DDR_PHY_MR13_CBT_MASK 0x00000001U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_MR14_RESERVED_31_8_DEFVAL #undef DDR_PHY_MR14_RESERVED_31_8_SHIFT #undef DDR_PHY_MR14_RESERVED_31_8_MASK -#define DDR_PHY_MR14_RESERVED_31_8_DEFVAL 0x0000004D -#define DDR_PHY_MR14_RESERVED_31_8_SHIFT 8 -#define DDR_PHY_MR14_RESERVED_31_8_MASK 0xFFFFFF00U +#define DDR_PHY_MR14_RESERVED_31_8_DEFVAL 0x0000004D +#define DDR_PHY_MR14_RESERVED_31_8_SHIFT 8 +#define DDR_PHY_MR14_RESERVED_31_8_MASK 0xFFFFFF00U -/*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/ +/* +* These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. +*/ #undef DDR_PHY_MR14_RSVD_DEFVAL #undef DDR_PHY_MR14_RSVD_SHIFT #undef DDR_PHY_MR14_RSVD_MASK -#define DDR_PHY_MR14_RSVD_DEFVAL 0x0000004D -#define DDR_PHY_MR14_RSVD_SHIFT 7 -#define DDR_PHY_MR14_RSVD_MASK 0x00000080U +#define DDR_PHY_MR14_RSVD_DEFVAL 0x0000004D +#define DDR_PHY_MR14_RSVD_SHIFT 7 +#define DDR_PHY_MR14_RSVD_MASK 0x00000080U -/*VREFDQ Range Selects.*/ +/* +* VREFDQ Range Selects. +*/ #undef DDR_PHY_MR14_VR_DQ_DEFVAL #undef DDR_PHY_MR14_VR_DQ_SHIFT #undef DDR_PHY_MR14_VR_DQ_MASK -#define DDR_PHY_MR14_VR_DQ_DEFVAL 0x0000004D -#define DDR_PHY_MR14_VR_DQ_SHIFT 6 -#define DDR_PHY_MR14_VR_DQ_MASK 0x00000040U +#define DDR_PHY_MR14_VR_DQ_DEFVAL 0x0000004D +#define DDR_PHY_MR14_VR_DQ_SHIFT 6 +#define DDR_PHY_MR14_VR_DQ_MASK 0x00000040U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_MR14_VREF_DQ_DEFVAL #undef DDR_PHY_MR14_VREF_DQ_SHIFT #undef DDR_PHY_MR14_VREF_DQ_MASK -#define DDR_PHY_MR14_VREF_DQ_DEFVAL 0x0000004D -#define DDR_PHY_MR14_VREF_DQ_SHIFT 0 -#define DDR_PHY_MR14_VREF_DQ_MASK 0x0000003FU +#define DDR_PHY_MR14_VREF_DQ_DEFVAL 0x0000004D +#define DDR_PHY_MR14_VREF_DQ_SHIFT 0 +#define DDR_PHY_MR14_VREF_DQ_MASK 0x0000003FU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_MR22_RESERVED_31_8_DEFVAL #undef DDR_PHY_MR22_RESERVED_31_8_SHIFT #undef DDR_PHY_MR22_RESERVED_31_8_MASK -#define DDR_PHY_MR22_RESERVED_31_8_DEFVAL 0x00000000 -#define DDR_PHY_MR22_RESERVED_31_8_SHIFT 8 -#define DDR_PHY_MR22_RESERVED_31_8_MASK 0xFFFFFF00U +#define DDR_PHY_MR22_RESERVED_31_8_DEFVAL 0x00000000 +#define DDR_PHY_MR22_RESERVED_31_8_SHIFT 8 +#define DDR_PHY_MR22_RESERVED_31_8_MASK 0xFFFFFF00U -/*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/ +/* +* These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. +*/ #undef DDR_PHY_MR22_RSVD_DEFVAL #undef DDR_PHY_MR22_RSVD_SHIFT #undef DDR_PHY_MR22_RSVD_MASK -#define DDR_PHY_MR22_RSVD_DEFVAL 0x00000000 -#define DDR_PHY_MR22_RSVD_SHIFT 6 -#define DDR_PHY_MR22_RSVD_MASK 0x000000C0U +#define DDR_PHY_MR22_RSVD_DEFVAL 0x00000000 +#define DDR_PHY_MR22_RSVD_SHIFT 6 +#define DDR_PHY_MR22_RSVD_MASK 0x000000C0U -/*CA ODT termination disable.*/ +/* +* CA ODT termination disable. +*/ #undef DDR_PHY_MR22_ODTD_CA_DEFVAL #undef DDR_PHY_MR22_ODTD_CA_SHIFT #undef DDR_PHY_MR22_ODTD_CA_MASK -#define DDR_PHY_MR22_ODTD_CA_DEFVAL 0x00000000 -#define DDR_PHY_MR22_ODTD_CA_SHIFT 5 -#define DDR_PHY_MR22_ODTD_CA_MASK 0x00000020U +#define DDR_PHY_MR22_ODTD_CA_DEFVAL 0x00000000 +#define DDR_PHY_MR22_ODTD_CA_SHIFT 5 +#define DDR_PHY_MR22_ODTD_CA_MASK 0x00000020U -/*ODT CS override.*/ +/* +* ODT CS override. +*/ #undef DDR_PHY_MR22_ODTE_CS_DEFVAL #undef DDR_PHY_MR22_ODTE_CS_SHIFT #undef DDR_PHY_MR22_ODTE_CS_MASK -#define DDR_PHY_MR22_ODTE_CS_DEFVAL 0x00000000 -#define DDR_PHY_MR22_ODTE_CS_SHIFT 4 -#define DDR_PHY_MR22_ODTE_CS_MASK 0x00000010U +#define DDR_PHY_MR22_ODTE_CS_DEFVAL 0x00000000 +#define DDR_PHY_MR22_ODTE_CS_SHIFT 4 +#define DDR_PHY_MR22_ODTE_CS_MASK 0x00000010U -/*ODT CK override.*/ +/* +* ODT CK override. +*/ #undef DDR_PHY_MR22_ODTE_CK_DEFVAL #undef DDR_PHY_MR22_ODTE_CK_SHIFT #undef DDR_PHY_MR22_ODTE_CK_MASK -#define DDR_PHY_MR22_ODTE_CK_DEFVAL 0x00000000 -#define DDR_PHY_MR22_ODTE_CK_SHIFT 3 -#define DDR_PHY_MR22_ODTE_CK_MASK 0x00000008U +#define DDR_PHY_MR22_ODTE_CK_DEFVAL 0x00000000 +#define DDR_PHY_MR22_ODTE_CK_SHIFT 3 +#define DDR_PHY_MR22_ODTE_CK_MASK 0x00000008U -/*Controller ODT value for VOH calibration.*/ +/* +* Controller ODT value for VOH calibration. +*/ #undef DDR_PHY_MR22_CODT_DEFVAL #undef DDR_PHY_MR22_CODT_SHIFT #undef DDR_PHY_MR22_CODT_MASK -#define DDR_PHY_MR22_CODT_DEFVAL 0x00000000 -#define DDR_PHY_MR22_CODT_SHIFT 0 -#define DDR_PHY_MR22_CODT_MASK 0x00000007U +#define DDR_PHY_MR22_CODT_DEFVAL 0x00000000 +#define DDR_PHY_MR22_CODT_SHIFT 0 +#define DDR_PHY_MR22_CODT_MASK 0x00000007U -/*Refresh During Training*/ +/* +* Refresh During Training +*/ #undef DDR_PHY_DTCR0_RFSHDT_DEFVAL #undef DDR_PHY_DTCR0_RFSHDT_SHIFT #undef DDR_PHY_DTCR0_RFSHDT_MASK -#define DDR_PHY_DTCR0_RFSHDT_DEFVAL 0x800091C7 -#define DDR_PHY_DTCR0_RFSHDT_SHIFT 28 -#define DDR_PHY_DTCR0_RFSHDT_MASK 0xF0000000U +#define DDR_PHY_DTCR0_RFSHDT_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_RFSHDT_SHIFT 28 +#define DDR_PHY_DTCR0_RFSHDT_MASK 0xF0000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTCR0_RESERVED_27_26_DEFVAL #undef DDR_PHY_DTCR0_RESERVED_27_26_SHIFT #undef DDR_PHY_DTCR0_RESERVED_27_26_MASK -#define DDR_PHY_DTCR0_RESERVED_27_26_DEFVAL 0x800091C7 -#define DDR_PHY_DTCR0_RESERVED_27_26_SHIFT 26 -#define DDR_PHY_DTCR0_RESERVED_27_26_MASK 0x0C000000U +#define DDR_PHY_DTCR0_RESERVED_27_26_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_RESERVED_27_26_SHIFT 26 +#define DDR_PHY_DTCR0_RESERVED_27_26_MASK 0x0C000000U -/*Data Training Debug Rank Select*/ +/* +* Data Training Debug Rank Select +*/ #undef DDR_PHY_DTCR0_DTDRS_DEFVAL #undef DDR_PHY_DTCR0_DTDRS_SHIFT #undef DDR_PHY_DTCR0_DTDRS_MASK -#define DDR_PHY_DTCR0_DTDRS_DEFVAL 0x800091C7 -#define DDR_PHY_DTCR0_DTDRS_SHIFT 24 -#define DDR_PHY_DTCR0_DTDRS_MASK 0x03000000U +#define DDR_PHY_DTCR0_DTDRS_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_DTDRS_SHIFT 24 +#define DDR_PHY_DTCR0_DTDRS_MASK 0x03000000U -/*Data Training with Early/Extended Gate*/ +/* +* Data Training with Early/Extended Gate +*/ #undef DDR_PHY_DTCR0_DTEXG_DEFVAL #undef DDR_PHY_DTCR0_DTEXG_SHIFT #undef DDR_PHY_DTCR0_DTEXG_MASK -#define DDR_PHY_DTCR0_DTEXG_DEFVAL 0x800091C7 -#define DDR_PHY_DTCR0_DTEXG_SHIFT 23 -#define DDR_PHY_DTCR0_DTEXG_MASK 0x00800000U +#define DDR_PHY_DTCR0_DTEXG_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_DTEXG_SHIFT 23 +#define DDR_PHY_DTCR0_DTEXG_MASK 0x00800000U -/*Data Training Extended Write DQS*/ +/* +* Data Training Extended Write DQS +*/ #undef DDR_PHY_DTCR0_DTEXD_DEFVAL #undef DDR_PHY_DTCR0_DTEXD_SHIFT #undef DDR_PHY_DTCR0_DTEXD_MASK -#define DDR_PHY_DTCR0_DTEXD_DEFVAL 0x800091C7 -#define DDR_PHY_DTCR0_DTEXD_SHIFT 22 -#define DDR_PHY_DTCR0_DTEXD_MASK 0x00400000U +#define DDR_PHY_DTCR0_DTEXD_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_DTEXD_SHIFT 22 +#define DDR_PHY_DTCR0_DTEXD_MASK 0x00400000U -/*Data Training Debug Step*/ +/* +* Data Training Debug Step +*/ #undef DDR_PHY_DTCR0_DTDSTP_DEFVAL #undef DDR_PHY_DTCR0_DTDSTP_SHIFT #undef DDR_PHY_DTCR0_DTDSTP_MASK -#define DDR_PHY_DTCR0_DTDSTP_DEFVAL 0x800091C7 -#define DDR_PHY_DTCR0_DTDSTP_SHIFT 21 -#define DDR_PHY_DTCR0_DTDSTP_MASK 0x00200000U +#define DDR_PHY_DTCR0_DTDSTP_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_DTDSTP_SHIFT 21 +#define DDR_PHY_DTCR0_DTDSTP_MASK 0x00200000U -/*Data Training Debug Enable*/ +/* +* Data Training Debug Enable +*/ #undef DDR_PHY_DTCR0_DTDEN_DEFVAL #undef DDR_PHY_DTCR0_DTDEN_SHIFT #undef DDR_PHY_DTCR0_DTDEN_MASK -#define DDR_PHY_DTCR0_DTDEN_DEFVAL 0x800091C7 -#define DDR_PHY_DTCR0_DTDEN_SHIFT 20 -#define DDR_PHY_DTCR0_DTDEN_MASK 0x00100000U +#define DDR_PHY_DTCR0_DTDEN_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_DTDEN_SHIFT 20 +#define DDR_PHY_DTCR0_DTDEN_MASK 0x00100000U -/*Data Training Debug Byte Select*/ +/* +* Data Training Debug Byte Select +*/ #undef DDR_PHY_DTCR0_DTDBS_DEFVAL #undef DDR_PHY_DTCR0_DTDBS_SHIFT #undef DDR_PHY_DTCR0_DTDBS_MASK -#define DDR_PHY_DTCR0_DTDBS_DEFVAL 0x800091C7 -#define DDR_PHY_DTCR0_DTDBS_SHIFT 16 -#define DDR_PHY_DTCR0_DTDBS_MASK 0x000F0000U +#define DDR_PHY_DTCR0_DTDBS_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_DTDBS_SHIFT 16 +#define DDR_PHY_DTCR0_DTDBS_MASK 0x000F0000U -/*Data Training read DBI deskewing configuration*/ +/* +* Data Training read DBI deskewing configuration +*/ #undef DDR_PHY_DTCR0_DTRDBITR_DEFVAL #undef DDR_PHY_DTCR0_DTRDBITR_SHIFT #undef DDR_PHY_DTCR0_DTRDBITR_MASK -#define DDR_PHY_DTCR0_DTRDBITR_DEFVAL 0x800091C7 -#define DDR_PHY_DTCR0_DTRDBITR_SHIFT 14 -#define DDR_PHY_DTCR0_DTRDBITR_MASK 0x0000C000U +#define DDR_PHY_DTCR0_DTRDBITR_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_DTRDBITR_SHIFT 14 +#define DDR_PHY_DTCR0_DTRDBITR_MASK 0x0000C000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTCR0_RESERVED_13_DEFVAL #undef DDR_PHY_DTCR0_RESERVED_13_SHIFT #undef DDR_PHY_DTCR0_RESERVED_13_MASK -#define DDR_PHY_DTCR0_RESERVED_13_DEFVAL 0x800091C7 -#define DDR_PHY_DTCR0_RESERVED_13_SHIFT 13 -#define DDR_PHY_DTCR0_RESERVED_13_MASK 0x00002000U +#define DDR_PHY_DTCR0_RESERVED_13_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_RESERVED_13_SHIFT 13 +#define DDR_PHY_DTCR0_RESERVED_13_MASK 0x00002000U -/*Data Training Write Bit Deskew Data Mask*/ +/* +* Data Training Write Bit Deskew Data Mask +*/ #undef DDR_PHY_DTCR0_DTWBDDM_DEFVAL #undef DDR_PHY_DTCR0_DTWBDDM_SHIFT #undef DDR_PHY_DTCR0_DTWBDDM_MASK -#define DDR_PHY_DTCR0_DTWBDDM_DEFVAL 0x800091C7 -#define DDR_PHY_DTCR0_DTWBDDM_SHIFT 12 -#define DDR_PHY_DTCR0_DTWBDDM_MASK 0x00001000U +#define DDR_PHY_DTCR0_DTWBDDM_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_DTWBDDM_SHIFT 12 +#define DDR_PHY_DTCR0_DTWBDDM_MASK 0x00001000U -/*Refreshes Issued During Entry to Training*/ +/* +* Refreshes Issued During Entry to Training +*/ #undef DDR_PHY_DTCR0_RFSHEN_DEFVAL #undef DDR_PHY_DTCR0_RFSHEN_SHIFT #undef DDR_PHY_DTCR0_RFSHEN_MASK -#define DDR_PHY_DTCR0_RFSHEN_DEFVAL 0x800091C7 -#define DDR_PHY_DTCR0_RFSHEN_SHIFT 8 -#define DDR_PHY_DTCR0_RFSHEN_MASK 0x00000F00U +#define DDR_PHY_DTCR0_RFSHEN_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_RFSHEN_SHIFT 8 +#define DDR_PHY_DTCR0_RFSHEN_MASK 0x00000F00U -/*Data Training Compare Data*/ +/* +* Data Training Compare Data +*/ #undef DDR_PHY_DTCR0_DTCMPD_DEFVAL #undef DDR_PHY_DTCR0_DTCMPD_SHIFT #undef DDR_PHY_DTCR0_DTCMPD_MASK -#define DDR_PHY_DTCR0_DTCMPD_DEFVAL 0x800091C7 -#define DDR_PHY_DTCR0_DTCMPD_SHIFT 7 -#define DDR_PHY_DTCR0_DTCMPD_MASK 0x00000080U +#define DDR_PHY_DTCR0_DTCMPD_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_DTCMPD_SHIFT 7 +#define DDR_PHY_DTCR0_DTCMPD_MASK 0x00000080U -/*Data Training Using MPR*/ +/* +* Data Training Using MPR +*/ #undef DDR_PHY_DTCR0_DTMPR_DEFVAL #undef DDR_PHY_DTCR0_DTMPR_SHIFT #undef DDR_PHY_DTCR0_DTMPR_MASK -#define DDR_PHY_DTCR0_DTMPR_DEFVAL 0x800091C7 -#define DDR_PHY_DTCR0_DTMPR_SHIFT 6 -#define DDR_PHY_DTCR0_DTMPR_MASK 0x00000040U +#define DDR_PHY_DTCR0_DTMPR_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_DTMPR_SHIFT 6 +#define DDR_PHY_DTCR0_DTMPR_MASK 0x00000040U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTCR0_RESERVED_5_4_DEFVAL #undef DDR_PHY_DTCR0_RESERVED_5_4_SHIFT #undef DDR_PHY_DTCR0_RESERVED_5_4_MASK -#define DDR_PHY_DTCR0_RESERVED_5_4_DEFVAL 0x800091C7 -#define DDR_PHY_DTCR0_RESERVED_5_4_SHIFT 4 -#define DDR_PHY_DTCR0_RESERVED_5_4_MASK 0x00000030U +#define DDR_PHY_DTCR0_RESERVED_5_4_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_RESERVED_5_4_SHIFT 4 +#define DDR_PHY_DTCR0_RESERVED_5_4_MASK 0x00000030U -/*Data Training Repeat Number*/ +/* +* Data Training Repeat Number +*/ #undef DDR_PHY_DTCR0_DTRPTN_DEFVAL #undef DDR_PHY_DTCR0_DTRPTN_SHIFT #undef DDR_PHY_DTCR0_DTRPTN_MASK -#define DDR_PHY_DTCR0_DTRPTN_DEFVAL 0x800091C7 -#define DDR_PHY_DTCR0_DTRPTN_SHIFT 0 -#define DDR_PHY_DTCR0_DTRPTN_MASK 0x0000000FU +#define DDR_PHY_DTCR0_DTRPTN_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_DTRPTN_SHIFT 0 +#define DDR_PHY_DTCR0_DTRPTN_MASK 0x0000000FU -/*Rank Enable.*/ +/* +* Rank Enable. +*/ #undef DDR_PHY_DTCR1_RANKEN_RSVD_DEFVAL #undef DDR_PHY_DTCR1_RANKEN_RSVD_SHIFT #undef DDR_PHY_DTCR1_RANKEN_RSVD_MASK -#define DDR_PHY_DTCR1_RANKEN_RSVD_DEFVAL 0x00030237 -#define DDR_PHY_DTCR1_RANKEN_RSVD_SHIFT 18 -#define DDR_PHY_DTCR1_RANKEN_RSVD_MASK 0xFFFC0000U +#define DDR_PHY_DTCR1_RANKEN_RSVD_DEFVAL 0x00030237 +#define DDR_PHY_DTCR1_RANKEN_RSVD_SHIFT 18 +#define DDR_PHY_DTCR1_RANKEN_RSVD_MASK 0xFFFC0000U -/*Rank Enable.*/ +/* +* Rank Enable. +*/ #undef DDR_PHY_DTCR1_RANKEN_DEFVAL #undef DDR_PHY_DTCR1_RANKEN_SHIFT #undef DDR_PHY_DTCR1_RANKEN_MASK -#define DDR_PHY_DTCR1_RANKEN_DEFVAL 0x00030237 -#define DDR_PHY_DTCR1_RANKEN_SHIFT 16 -#define DDR_PHY_DTCR1_RANKEN_MASK 0x00030000U +#define DDR_PHY_DTCR1_RANKEN_DEFVAL 0x00030237 +#define DDR_PHY_DTCR1_RANKEN_SHIFT 16 +#define DDR_PHY_DTCR1_RANKEN_MASK 0x00030000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTCR1_RESERVED_15_14_DEFVAL #undef DDR_PHY_DTCR1_RESERVED_15_14_SHIFT #undef DDR_PHY_DTCR1_RESERVED_15_14_MASK -#define DDR_PHY_DTCR1_RESERVED_15_14_DEFVAL 0x00030237 -#define DDR_PHY_DTCR1_RESERVED_15_14_SHIFT 14 -#define DDR_PHY_DTCR1_RESERVED_15_14_MASK 0x0000C000U +#define DDR_PHY_DTCR1_RESERVED_15_14_DEFVAL 0x00030237 +#define DDR_PHY_DTCR1_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_DTCR1_RESERVED_15_14_MASK 0x0000C000U -/*Data Training Rank*/ +/* +* Data Training Rank +*/ #undef DDR_PHY_DTCR1_DTRANK_DEFVAL #undef DDR_PHY_DTCR1_DTRANK_SHIFT #undef DDR_PHY_DTCR1_DTRANK_MASK -#define DDR_PHY_DTCR1_DTRANK_DEFVAL 0x00030237 -#define DDR_PHY_DTCR1_DTRANK_SHIFT 12 -#define DDR_PHY_DTCR1_DTRANK_MASK 0x00003000U +#define DDR_PHY_DTCR1_DTRANK_DEFVAL 0x00030237 +#define DDR_PHY_DTCR1_DTRANK_SHIFT 12 +#define DDR_PHY_DTCR1_DTRANK_MASK 0x00003000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTCR1_RESERVED_11_DEFVAL #undef DDR_PHY_DTCR1_RESERVED_11_SHIFT #undef DDR_PHY_DTCR1_RESERVED_11_MASK -#define DDR_PHY_DTCR1_RESERVED_11_DEFVAL 0x00030237 -#define DDR_PHY_DTCR1_RESERVED_11_SHIFT 11 -#define DDR_PHY_DTCR1_RESERVED_11_MASK 0x00000800U +#define DDR_PHY_DTCR1_RESERVED_11_DEFVAL 0x00030237 +#define DDR_PHY_DTCR1_RESERVED_11_SHIFT 11 +#define DDR_PHY_DTCR1_RESERVED_11_MASK 0x00000800U -/*Read Leveling Gate Sampling Difference*/ +/* +* Read Leveling Gate Sampling Difference +*/ #undef DDR_PHY_DTCR1_RDLVLGDIFF_DEFVAL #undef DDR_PHY_DTCR1_RDLVLGDIFF_SHIFT #undef DDR_PHY_DTCR1_RDLVLGDIFF_MASK -#define DDR_PHY_DTCR1_RDLVLGDIFF_DEFVAL 0x00030237 -#define DDR_PHY_DTCR1_RDLVLGDIFF_SHIFT 8 -#define DDR_PHY_DTCR1_RDLVLGDIFF_MASK 0x00000700U +#define DDR_PHY_DTCR1_RDLVLGDIFF_DEFVAL 0x00030237 +#define DDR_PHY_DTCR1_RDLVLGDIFF_SHIFT 8 +#define DDR_PHY_DTCR1_RDLVLGDIFF_MASK 0x00000700U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTCR1_RESERVED_7_DEFVAL #undef DDR_PHY_DTCR1_RESERVED_7_SHIFT #undef DDR_PHY_DTCR1_RESERVED_7_MASK -#define DDR_PHY_DTCR1_RESERVED_7_DEFVAL 0x00030237 -#define DDR_PHY_DTCR1_RESERVED_7_SHIFT 7 -#define DDR_PHY_DTCR1_RESERVED_7_MASK 0x00000080U +#define DDR_PHY_DTCR1_RESERVED_7_DEFVAL 0x00030237 +#define DDR_PHY_DTCR1_RESERVED_7_SHIFT 7 +#define DDR_PHY_DTCR1_RESERVED_7_MASK 0x00000080U -/*Read Leveling Gate Shift*/ +/* +* Read Leveling Gate Shift +*/ #undef DDR_PHY_DTCR1_RDLVLGS_DEFVAL #undef DDR_PHY_DTCR1_RDLVLGS_SHIFT #undef DDR_PHY_DTCR1_RDLVLGS_MASK -#define DDR_PHY_DTCR1_RDLVLGS_DEFVAL 0x00030237 -#define DDR_PHY_DTCR1_RDLVLGS_SHIFT 4 -#define DDR_PHY_DTCR1_RDLVLGS_MASK 0x00000070U +#define DDR_PHY_DTCR1_RDLVLGS_DEFVAL 0x00030237 +#define DDR_PHY_DTCR1_RDLVLGS_SHIFT 4 +#define DDR_PHY_DTCR1_RDLVLGS_MASK 0x00000070U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTCR1_RESERVED_3_DEFVAL #undef DDR_PHY_DTCR1_RESERVED_3_SHIFT #undef DDR_PHY_DTCR1_RESERVED_3_MASK -#define DDR_PHY_DTCR1_RESERVED_3_DEFVAL 0x00030237 -#define DDR_PHY_DTCR1_RESERVED_3_SHIFT 3 -#define DDR_PHY_DTCR1_RESERVED_3_MASK 0x00000008U +#define DDR_PHY_DTCR1_RESERVED_3_DEFVAL 0x00030237 +#define DDR_PHY_DTCR1_RESERVED_3_SHIFT 3 +#define DDR_PHY_DTCR1_RESERVED_3_MASK 0x00000008U -/*Read Preamble Training enable*/ +/* +* Read Preamble Training enable +*/ #undef DDR_PHY_DTCR1_RDPRMVL_TRN_DEFVAL #undef DDR_PHY_DTCR1_RDPRMVL_TRN_SHIFT #undef DDR_PHY_DTCR1_RDPRMVL_TRN_MASK -#define DDR_PHY_DTCR1_RDPRMVL_TRN_DEFVAL 0x00030237 -#define DDR_PHY_DTCR1_RDPRMVL_TRN_SHIFT 2 -#define DDR_PHY_DTCR1_RDPRMVL_TRN_MASK 0x00000004U +#define DDR_PHY_DTCR1_RDPRMVL_TRN_DEFVAL 0x00030237 +#define DDR_PHY_DTCR1_RDPRMVL_TRN_SHIFT 2 +#define DDR_PHY_DTCR1_RDPRMVL_TRN_MASK 0x00000004U -/*Read Leveling Enable*/ +/* +* Read Leveling Enable +*/ #undef DDR_PHY_DTCR1_RDLVLEN_DEFVAL #undef DDR_PHY_DTCR1_RDLVLEN_SHIFT #undef DDR_PHY_DTCR1_RDLVLEN_MASK -#define DDR_PHY_DTCR1_RDLVLEN_DEFVAL 0x00030237 -#define DDR_PHY_DTCR1_RDLVLEN_SHIFT 1 -#define DDR_PHY_DTCR1_RDLVLEN_MASK 0x00000002U +#define DDR_PHY_DTCR1_RDLVLEN_DEFVAL 0x00030237 +#define DDR_PHY_DTCR1_RDLVLEN_SHIFT 1 +#define DDR_PHY_DTCR1_RDLVLEN_MASK 0x00000002U -/*Basic Gate Training Enable*/ +/* +* Basic Gate Training Enable +*/ #undef DDR_PHY_DTCR1_BSTEN_DEFVAL #undef DDR_PHY_DTCR1_BSTEN_SHIFT #undef DDR_PHY_DTCR1_BSTEN_MASK -#define DDR_PHY_DTCR1_BSTEN_DEFVAL 0x00030237 -#define DDR_PHY_DTCR1_BSTEN_SHIFT 0 -#define DDR_PHY_DTCR1_BSTEN_MASK 0x00000001U +#define DDR_PHY_DTCR1_BSTEN_DEFVAL 0x00030237 +#define DDR_PHY_DTCR1_BSTEN_SHIFT 0 +#define DDR_PHY_DTCR1_BSTEN_MASK 0x00000001U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_CATR0_RESERVED_31_21_DEFVAL #undef DDR_PHY_CATR0_RESERVED_31_21_SHIFT #undef DDR_PHY_CATR0_RESERVED_31_21_MASK -#define DDR_PHY_CATR0_RESERVED_31_21_DEFVAL 0x00141054 -#define DDR_PHY_CATR0_RESERVED_31_21_SHIFT 21 -#define DDR_PHY_CATR0_RESERVED_31_21_MASK 0xFFE00000U +#define DDR_PHY_CATR0_RESERVED_31_21_DEFVAL 0x00141054 +#define DDR_PHY_CATR0_RESERVED_31_21_SHIFT 21 +#define DDR_PHY_CATR0_RESERVED_31_21_MASK 0xFFE00000U -/*Minimum time (in terms of number of dram clocks) between two consectuve CA calibration command*/ +/* +* Minimum time (in terms of number of dram clocks) between two consectuve + * CA calibration command +*/ #undef DDR_PHY_CATR0_CACD_DEFVAL #undef DDR_PHY_CATR0_CACD_SHIFT #undef DDR_PHY_CATR0_CACD_MASK -#define DDR_PHY_CATR0_CACD_DEFVAL 0x00141054 -#define DDR_PHY_CATR0_CACD_SHIFT 16 -#define DDR_PHY_CATR0_CACD_MASK 0x001F0000U +#define DDR_PHY_CATR0_CACD_DEFVAL 0x00141054 +#define DDR_PHY_CATR0_CACD_SHIFT 16 +#define DDR_PHY_CATR0_CACD_MASK 0x001F0000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_CATR0_RESERVED_15_13_DEFVAL #undef DDR_PHY_CATR0_RESERVED_15_13_SHIFT #undef DDR_PHY_CATR0_RESERVED_15_13_MASK -#define DDR_PHY_CATR0_RESERVED_15_13_DEFVAL 0x00141054 -#define DDR_PHY_CATR0_RESERVED_15_13_SHIFT 13 -#define DDR_PHY_CATR0_RESERVED_15_13_MASK 0x0000E000U +#define DDR_PHY_CATR0_RESERVED_15_13_DEFVAL 0x00141054 +#define DDR_PHY_CATR0_RESERVED_15_13_SHIFT 13 +#define DDR_PHY_CATR0_RESERVED_15_13_MASK 0x0000E000U -/*Minimum time (in terms of number of dram clocks) PUB should wait before sampling the CA response after Calibration command ha - been sent to the memory*/ +/* +* Minimum time (in terms of number of dram clocks) PUB should wait before + * sampling the CA response after Calibration command has been sent to the + * memory +*/ #undef DDR_PHY_CATR0_CAADR_DEFVAL #undef DDR_PHY_CATR0_CAADR_SHIFT #undef DDR_PHY_CATR0_CAADR_MASK -#define DDR_PHY_CATR0_CAADR_DEFVAL 0x00141054 -#define DDR_PHY_CATR0_CAADR_SHIFT 8 -#define DDR_PHY_CATR0_CAADR_MASK 0x00001F00U +#define DDR_PHY_CATR0_CAADR_DEFVAL 0x00141054 +#define DDR_PHY_CATR0_CAADR_SHIFT 8 +#define DDR_PHY_CATR0_CAADR_MASK 0x00001F00U -/*CA_1 Response Byte Lane 1*/ +/* +* CA_1 Response Byte Lane 1 +*/ #undef DDR_PHY_CATR0_CA1BYTE1_DEFVAL #undef DDR_PHY_CATR0_CA1BYTE1_SHIFT #undef DDR_PHY_CATR0_CA1BYTE1_MASK -#define DDR_PHY_CATR0_CA1BYTE1_DEFVAL 0x00141054 -#define DDR_PHY_CATR0_CA1BYTE1_SHIFT 4 -#define DDR_PHY_CATR0_CA1BYTE1_MASK 0x000000F0U +#define DDR_PHY_CATR0_CA1BYTE1_DEFVAL 0x00141054 +#define DDR_PHY_CATR0_CA1BYTE1_SHIFT 4 +#define DDR_PHY_CATR0_CA1BYTE1_MASK 0x000000F0U -/*CA_1 Response Byte Lane 0*/ +/* +* CA_1 Response Byte Lane 0 +*/ #undef DDR_PHY_CATR0_CA1BYTE0_DEFVAL #undef DDR_PHY_CATR0_CA1BYTE0_SHIFT #undef DDR_PHY_CATR0_CA1BYTE0_MASK -#define DDR_PHY_CATR0_CA1BYTE0_DEFVAL 0x00141054 -#define DDR_PHY_CATR0_CA1BYTE0_SHIFT 0 -#define DDR_PHY_CATR0_CA1BYTE0_MASK 0x0000000FU +#define DDR_PHY_CATR0_CA1BYTE0_DEFVAL 0x00141054 +#define DDR_PHY_CATR0_CA1BYTE0_SHIFT 0 +#define DDR_PHY_CATR0_CA1BYTE0_MASK 0x0000000FU -/*LFSR seed for pseudo-random BIST patterns*/ +/* +* Number of delay taps by which the DQS gate LCDL will be updated when DQS + * drift is detected +*/ +#undef DDR_PHY_DQSDR0_DFTDLY_DEFVAL +#undef DDR_PHY_DQSDR0_DFTDLY_SHIFT +#undef DDR_PHY_DQSDR0_DFTDLY_MASK +#define DDR_PHY_DQSDR0_DFTDLY_DEFVAL 0x00088000 +#define DDR_PHY_DQSDR0_DFTDLY_SHIFT 28 +#define DDR_PHY_DQSDR0_DFTDLY_MASK 0xF0000000U + +/* +* Drift Impedance Update +*/ +#undef DDR_PHY_DQSDR0_DFTZQUP_DEFVAL +#undef DDR_PHY_DQSDR0_DFTZQUP_SHIFT +#undef DDR_PHY_DQSDR0_DFTZQUP_MASK +#define DDR_PHY_DQSDR0_DFTZQUP_DEFVAL 0x00088000 +#define DDR_PHY_DQSDR0_DFTZQUP_SHIFT 27 +#define DDR_PHY_DQSDR0_DFTZQUP_MASK 0x08000000U + +/* +* Drift DDL Update +*/ +#undef DDR_PHY_DQSDR0_DFTDDLUP_DEFVAL +#undef DDR_PHY_DQSDR0_DFTDDLUP_SHIFT +#undef DDR_PHY_DQSDR0_DFTDDLUP_MASK +#define DDR_PHY_DQSDR0_DFTDDLUP_DEFVAL 0x00088000 +#define DDR_PHY_DQSDR0_DFTDDLUP_SHIFT 26 +#define DDR_PHY_DQSDR0_DFTDDLUP_MASK 0x04000000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DQSDR0_RESERVED_25_22_DEFVAL +#undef DDR_PHY_DQSDR0_RESERVED_25_22_SHIFT +#undef DDR_PHY_DQSDR0_RESERVED_25_22_MASK +#define DDR_PHY_DQSDR0_RESERVED_25_22_DEFVAL 0x00088000 +#define DDR_PHY_DQSDR0_RESERVED_25_22_SHIFT 22 +#define DDR_PHY_DQSDR0_RESERVED_25_22_MASK 0x03C00000U + +/* +* Drift Read Spacing +*/ +#undef DDR_PHY_DQSDR0_DFTRDSPC_DEFVAL +#undef DDR_PHY_DQSDR0_DFTRDSPC_SHIFT +#undef DDR_PHY_DQSDR0_DFTRDSPC_MASK +#define DDR_PHY_DQSDR0_DFTRDSPC_DEFVAL 0x00088000 +#define DDR_PHY_DQSDR0_DFTRDSPC_SHIFT 20 +#define DDR_PHY_DQSDR0_DFTRDSPC_MASK 0x00300000U + +/* +* Drift Back-to-Back Reads +*/ +#undef DDR_PHY_DQSDR0_DFTB2BRD_DEFVAL +#undef DDR_PHY_DQSDR0_DFTB2BRD_SHIFT +#undef DDR_PHY_DQSDR0_DFTB2BRD_MASK +#define DDR_PHY_DQSDR0_DFTB2BRD_DEFVAL 0x00088000 +#define DDR_PHY_DQSDR0_DFTB2BRD_SHIFT 16 +#define DDR_PHY_DQSDR0_DFTB2BRD_MASK 0x000F0000U + +/* +* Drift Idle Reads +*/ +#undef DDR_PHY_DQSDR0_DFTIDLRD_DEFVAL +#undef DDR_PHY_DQSDR0_DFTIDLRD_SHIFT +#undef DDR_PHY_DQSDR0_DFTIDLRD_MASK +#define DDR_PHY_DQSDR0_DFTIDLRD_DEFVAL 0x00088000 +#define DDR_PHY_DQSDR0_DFTIDLRD_SHIFT 12 +#define DDR_PHY_DQSDR0_DFTIDLRD_MASK 0x0000F000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DQSDR0_RESERVED_11_8_DEFVAL +#undef DDR_PHY_DQSDR0_RESERVED_11_8_SHIFT +#undef DDR_PHY_DQSDR0_RESERVED_11_8_MASK +#define DDR_PHY_DQSDR0_RESERVED_11_8_DEFVAL 0x00088000 +#define DDR_PHY_DQSDR0_RESERVED_11_8_SHIFT 8 +#define DDR_PHY_DQSDR0_RESERVED_11_8_MASK 0x00000F00U + +/* +* Gate Pulse Enable +*/ +#undef DDR_PHY_DQSDR0_DFTGPULSE_DEFVAL +#undef DDR_PHY_DQSDR0_DFTGPULSE_SHIFT +#undef DDR_PHY_DQSDR0_DFTGPULSE_MASK +#define DDR_PHY_DQSDR0_DFTGPULSE_DEFVAL 0x00088000 +#define DDR_PHY_DQSDR0_DFTGPULSE_SHIFT 4 +#define DDR_PHY_DQSDR0_DFTGPULSE_MASK 0x000000F0U + +/* +* DQS Drift Update Mode +*/ +#undef DDR_PHY_DQSDR0_DFTUPMODE_DEFVAL +#undef DDR_PHY_DQSDR0_DFTUPMODE_SHIFT +#undef DDR_PHY_DQSDR0_DFTUPMODE_MASK +#define DDR_PHY_DQSDR0_DFTUPMODE_DEFVAL 0x00088000 +#define DDR_PHY_DQSDR0_DFTUPMODE_SHIFT 2 +#define DDR_PHY_DQSDR0_DFTUPMODE_MASK 0x0000000CU + +/* +* DQS Drift Detection Mode +*/ +#undef DDR_PHY_DQSDR0_DFTDTMODE_DEFVAL +#undef DDR_PHY_DQSDR0_DFTDTMODE_SHIFT +#undef DDR_PHY_DQSDR0_DFTDTMODE_MASK +#define DDR_PHY_DQSDR0_DFTDTMODE_DEFVAL 0x00088000 +#define DDR_PHY_DQSDR0_DFTDTMODE_SHIFT 1 +#define DDR_PHY_DQSDR0_DFTDTMODE_MASK 0x00000002U + +/* +* DQS Drift Detection Enable +*/ +#undef DDR_PHY_DQSDR0_DFTDTEN_DEFVAL +#undef DDR_PHY_DQSDR0_DFTDTEN_SHIFT +#undef DDR_PHY_DQSDR0_DFTDTEN_MASK +#define DDR_PHY_DQSDR0_DFTDTEN_DEFVAL 0x00088000 +#define DDR_PHY_DQSDR0_DFTDTEN_SHIFT 0 +#define DDR_PHY_DQSDR0_DFTDTEN_MASK 0x00000001U + +/* +* LFSR seed for pseudo-random BIST patterns +*/ #undef DDR_PHY_BISTLSR_SEED_DEFVAL #undef DDR_PHY_BISTLSR_SEED_SHIFT #undef DDR_PHY_BISTLSR_SEED_MASK -#define DDR_PHY_BISTLSR_SEED_DEFVAL -#define DDR_PHY_BISTLSR_SEED_SHIFT 0 -#define DDR_PHY_BISTLSR_SEED_MASK 0xFFFFFFFFU +#define DDR_PHY_BISTLSR_SEED_DEFVAL +#define DDR_PHY_BISTLSR_SEED_SHIFT 0 +#define DDR_PHY_BISTLSR_SEED_MASK 0xFFFFFFFFU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_RIOCR5_RESERVED_31_16_DEFVAL #undef DDR_PHY_RIOCR5_RESERVED_31_16_SHIFT #undef DDR_PHY_RIOCR5_RESERVED_31_16_MASK -#define DDR_PHY_RIOCR5_RESERVED_31_16_DEFVAL 0x00000005 -#define DDR_PHY_RIOCR5_RESERVED_31_16_SHIFT 16 -#define DDR_PHY_RIOCR5_RESERVED_31_16_MASK 0xFFFF0000U +#define DDR_PHY_RIOCR5_RESERVED_31_16_DEFVAL 0x00000005 +#define DDR_PHY_RIOCR5_RESERVED_31_16_SHIFT 16 +#define DDR_PHY_RIOCR5_RESERVED_31_16_MASK 0xFFFF0000U -/*Reserved. Return zeros on reads.*/ +/* +* Reserved. Return zeros on reads. +*/ #undef DDR_PHY_RIOCR5_ODTOEMODE_RSVD_DEFVAL #undef DDR_PHY_RIOCR5_ODTOEMODE_RSVD_SHIFT #undef DDR_PHY_RIOCR5_ODTOEMODE_RSVD_MASK -#define DDR_PHY_RIOCR5_ODTOEMODE_RSVD_DEFVAL 0x00000005 -#define DDR_PHY_RIOCR5_ODTOEMODE_RSVD_SHIFT 4 -#define DDR_PHY_RIOCR5_ODTOEMODE_RSVD_MASK 0x0000FFF0U +#define DDR_PHY_RIOCR5_ODTOEMODE_RSVD_DEFVAL 0x00000005 +#define DDR_PHY_RIOCR5_ODTOEMODE_RSVD_SHIFT 4 +#define DDR_PHY_RIOCR5_ODTOEMODE_RSVD_MASK 0x0000FFF0U -/*SDRAM On-die Termination Output Enable (OE) Mode Selection.*/ +/* +* SDRAM On-die Termination Output Enable (OE) Mode Selection. +*/ #undef DDR_PHY_RIOCR5_ODTOEMODE_DEFVAL #undef DDR_PHY_RIOCR5_ODTOEMODE_SHIFT #undef DDR_PHY_RIOCR5_ODTOEMODE_MASK -#define DDR_PHY_RIOCR5_ODTOEMODE_DEFVAL 0x00000005 -#define DDR_PHY_RIOCR5_ODTOEMODE_SHIFT 0 -#define DDR_PHY_RIOCR5_ODTOEMODE_MASK 0x0000000FU +#define DDR_PHY_RIOCR5_ODTOEMODE_DEFVAL 0x00000005 +#define DDR_PHY_RIOCR5_ODTOEMODE_SHIFT 0 +#define DDR_PHY_RIOCR5_ODTOEMODE_MASK 0x0000000FU -/*Address/Command Slew Rate (D3F I/O Only)*/ +/* +* Address/Command Slew Rate (D3F I/O Only) +*/ #undef DDR_PHY_ACIOCR0_ACSR_DEFVAL #undef DDR_PHY_ACIOCR0_ACSR_SHIFT #undef DDR_PHY_ACIOCR0_ACSR_MASK -#define DDR_PHY_ACIOCR0_ACSR_DEFVAL 0x30000000 -#define DDR_PHY_ACIOCR0_ACSR_SHIFT 30 -#define DDR_PHY_ACIOCR0_ACSR_MASK 0xC0000000U +#define DDR_PHY_ACIOCR0_ACSR_DEFVAL 0x30000000 +#define DDR_PHY_ACIOCR0_ACSR_SHIFT 30 +#define DDR_PHY_ACIOCR0_ACSR_MASK 0xC0000000U -/*SDRAM Reset I/O Mode*/ +/* +* SDRAM Reset I/O Mode +*/ #undef DDR_PHY_ACIOCR0_RSTIOM_DEFVAL #undef DDR_PHY_ACIOCR0_RSTIOM_SHIFT #undef DDR_PHY_ACIOCR0_RSTIOM_MASK -#define DDR_PHY_ACIOCR0_RSTIOM_DEFVAL 0x30000000 -#define DDR_PHY_ACIOCR0_RSTIOM_SHIFT 29 -#define DDR_PHY_ACIOCR0_RSTIOM_MASK 0x20000000U +#define DDR_PHY_ACIOCR0_RSTIOM_DEFVAL 0x30000000 +#define DDR_PHY_ACIOCR0_RSTIOM_SHIFT 29 +#define DDR_PHY_ACIOCR0_RSTIOM_MASK 0x20000000U -/*SDRAM Reset Power Down Receiver*/ +/* +* SDRAM Reset Power Down Receiver +*/ #undef DDR_PHY_ACIOCR0_RSTPDR_DEFVAL #undef DDR_PHY_ACIOCR0_RSTPDR_SHIFT #undef DDR_PHY_ACIOCR0_RSTPDR_MASK -#define DDR_PHY_ACIOCR0_RSTPDR_DEFVAL 0x30000000 -#define DDR_PHY_ACIOCR0_RSTPDR_SHIFT 28 -#define DDR_PHY_ACIOCR0_RSTPDR_MASK 0x10000000U +#define DDR_PHY_ACIOCR0_RSTPDR_DEFVAL 0x30000000 +#define DDR_PHY_ACIOCR0_RSTPDR_SHIFT 28 +#define DDR_PHY_ACIOCR0_RSTPDR_MASK 0x10000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACIOCR0_RESERVED_27_DEFVAL #undef DDR_PHY_ACIOCR0_RESERVED_27_SHIFT #undef DDR_PHY_ACIOCR0_RESERVED_27_MASK -#define DDR_PHY_ACIOCR0_RESERVED_27_DEFVAL 0x30000000 -#define DDR_PHY_ACIOCR0_RESERVED_27_SHIFT 27 -#define DDR_PHY_ACIOCR0_RESERVED_27_MASK 0x08000000U +#define DDR_PHY_ACIOCR0_RESERVED_27_DEFVAL 0x30000000 +#define DDR_PHY_ACIOCR0_RESERVED_27_SHIFT 27 +#define DDR_PHY_ACIOCR0_RESERVED_27_MASK 0x08000000U -/*SDRAM Reset On-Die Termination*/ +/* +* SDRAM Reset On-Die Termination +*/ #undef DDR_PHY_ACIOCR0_RSTODT_DEFVAL #undef DDR_PHY_ACIOCR0_RSTODT_SHIFT #undef DDR_PHY_ACIOCR0_RSTODT_MASK -#define DDR_PHY_ACIOCR0_RSTODT_DEFVAL 0x30000000 -#define DDR_PHY_ACIOCR0_RSTODT_SHIFT 26 -#define DDR_PHY_ACIOCR0_RSTODT_MASK 0x04000000U +#define DDR_PHY_ACIOCR0_RSTODT_DEFVAL 0x30000000 +#define DDR_PHY_ACIOCR0_RSTODT_SHIFT 26 +#define DDR_PHY_ACIOCR0_RSTODT_MASK 0x04000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACIOCR0_RESERVED_25_10_DEFVAL #undef DDR_PHY_ACIOCR0_RESERVED_25_10_SHIFT #undef DDR_PHY_ACIOCR0_RESERVED_25_10_MASK -#define DDR_PHY_ACIOCR0_RESERVED_25_10_DEFVAL 0x30000000 -#define DDR_PHY_ACIOCR0_RESERVED_25_10_SHIFT 10 -#define DDR_PHY_ACIOCR0_RESERVED_25_10_MASK 0x03FFFC00U +#define DDR_PHY_ACIOCR0_RESERVED_25_10_DEFVAL 0x30000000 +#define DDR_PHY_ACIOCR0_RESERVED_25_10_SHIFT 10 +#define DDR_PHY_ACIOCR0_RESERVED_25_10_MASK 0x03FFFC00U -/*CK Duty Cycle Correction*/ +/* +* CK Duty Cycle Correction +*/ #undef DDR_PHY_ACIOCR0_CKDCC_DEFVAL #undef DDR_PHY_ACIOCR0_CKDCC_SHIFT #undef DDR_PHY_ACIOCR0_CKDCC_MASK -#define DDR_PHY_ACIOCR0_CKDCC_DEFVAL 0x30000000 -#define DDR_PHY_ACIOCR0_CKDCC_SHIFT 6 -#define DDR_PHY_ACIOCR0_CKDCC_MASK 0x000003C0U +#define DDR_PHY_ACIOCR0_CKDCC_DEFVAL 0x30000000 +#define DDR_PHY_ACIOCR0_CKDCC_SHIFT 6 +#define DDR_PHY_ACIOCR0_CKDCC_MASK 0x000003C0U -/*AC Power Down Receiver Mode*/ +/* +* AC Power Down Receiver Mode +*/ #undef DDR_PHY_ACIOCR0_ACPDRMODE_DEFVAL #undef DDR_PHY_ACIOCR0_ACPDRMODE_SHIFT #undef DDR_PHY_ACIOCR0_ACPDRMODE_MASK -#define DDR_PHY_ACIOCR0_ACPDRMODE_DEFVAL 0x30000000 -#define DDR_PHY_ACIOCR0_ACPDRMODE_SHIFT 4 -#define DDR_PHY_ACIOCR0_ACPDRMODE_MASK 0x00000030U +#define DDR_PHY_ACIOCR0_ACPDRMODE_DEFVAL 0x30000000 +#define DDR_PHY_ACIOCR0_ACPDRMODE_SHIFT 4 +#define DDR_PHY_ACIOCR0_ACPDRMODE_MASK 0x00000030U -/*AC On-die Termination Mode*/ +/* +* AC On-die Termination Mode +*/ #undef DDR_PHY_ACIOCR0_ACODTMODE_DEFVAL #undef DDR_PHY_ACIOCR0_ACODTMODE_SHIFT #undef DDR_PHY_ACIOCR0_ACODTMODE_MASK -#define DDR_PHY_ACIOCR0_ACODTMODE_DEFVAL 0x30000000 -#define DDR_PHY_ACIOCR0_ACODTMODE_SHIFT 2 -#define DDR_PHY_ACIOCR0_ACODTMODE_MASK 0x0000000CU +#define DDR_PHY_ACIOCR0_ACODTMODE_DEFVAL 0x30000000 +#define DDR_PHY_ACIOCR0_ACODTMODE_SHIFT 2 +#define DDR_PHY_ACIOCR0_ACODTMODE_MASK 0x0000000CU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACIOCR0_RESERVED_1_DEFVAL #undef DDR_PHY_ACIOCR0_RESERVED_1_SHIFT #undef DDR_PHY_ACIOCR0_RESERVED_1_MASK -#define DDR_PHY_ACIOCR0_RESERVED_1_DEFVAL 0x30000000 -#define DDR_PHY_ACIOCR0_RESERVED_1_SHIFT 1 -#define DDR_PHY_ACIOCR0_RESERVED_1_MASK 0x00000002U +#define DDR_PHY_ACIOCR0_RESERVED_1_DEFVAL 0x30000000 +#define DDR_PHY_ACIOCR0_RESERVED_1_SHIFT 1 +#define DDR_PHY_ACIOCR0_RESERVED_1_MASK 0x00000002U -/*Control delayed or non-delayed clock to CS_N/ODT?CKE AC slices.*/ +/* +* Control delayed or non-delayed clock to CS_N/ODT?CKE AC slices. +*/ #undef DDR_PHY_ACIOCR0_ACRANKCLKSEL_DEFVAL #undef DDR_PHY_ACIOCR0_ACRANKCLKSEL_SHIFT #undef DDR_PHY_ACIOCR0_ACRANKCLKSEL_MASK -#define DDR_PHY_ACIOCR0_ACRANKCLKSEL_DEFVAL 0x30000000 -#define DDR_PHY_ACIOCR0_ACRANKCLKSEL_SHIFT 0 -#define DDR_PHY_ACIOCR0_ACRANKCLKSEL_MASK 0x00000001U +#define DDR_PHY_ACIOCR0_ACRANKCLKSEL_DEFVAL 0x30000000 +#define DDR_PHY_ACIOCR0_ACRANKCLKSEL_SHIFT 0 +#define DDR_PHY_ACIOCR0_ACRANKCLKSEL_MASK 0x00000001U -/*Clock gating for glue logic inside CLKGEN and glue logic inside CONTROL slice*/ +/* +* Clock gating for glue logic inside CLKGEN and glue logic inside CONTROL + * slice +*/ #undef DDR_PHY_ACIOCR2_CLKGENCLKGATE_DEFVAL #undef DDR_PHY_ACIOCR2_CLKGENCLKGATE_SHIFT #undef DDR_PHY_ACIOCR2_CLKGENCLKGATE_MASK -#define DDR_PHY_ACIOCR2_CLKGENCLKGATE_DEFVAL 0x00000000 -#define DDR_PHY_ACIOCR2_CLKGENCLKGATE_SHIFT 31 -#define DDR_PHY_ACIOCR2_CLKGENCLKGATE_MASK 0x80000000U +#define DDR_PHY_ACIOCR2_CLKGENCLKGATE_DEFVAL 0x00000000 +#define DDR_PHY_ACIOCR2_CLKGENCLKGATE_SHIFT 31 +#define DDR_PHY_ACIOCR2_CLKGENCLKGATE_MASK 0x80000000U -/*Clock gating for Output Enable D slices [0]*/ +/* +* Clock gating for Output Enable D slices [0] +*/ #undef DDR_PHY_ACIOCR2_ACOECLKGATE0_DEFVAL #undef DDR_PHY_ACIOCR2_ACOECLKGATE0_SHIFT #undef DDR_PHY_ACIOCR2_ACOECLKGATE0_MASK -#define DDR_PHY_ACIOCR2_ACOECLKGATE0_DEFVAL 0x00000000 -#define DDR_PHY_ACIOCR2_ACOECLKGATE0_SHIFT 30 -#define DDR_PHY_ACIOCR2_ACOECLKGATE0_MASK 0x40000000U +#define DDR_PHY_ACIOCR2_ACOECLKGATE0_DEFVAL 0x00000000 +#define DDR_PHY_ACIOCR2_ACOECLKGATE0_SHIFT 30 +#define DDR_PHY_ACIOCR2_ACOECLKGATE0_MASK 0x40000000U -/*Clock gating for Power Down Receiver D slices [0]*/ +/* +* Clock gating for Power Down Receiver D slices [0] +*/ #undef DDR_PHY_ACIOCR2_ACPDRCLKGATE0_DEFVAL #undef DDR_PHY_ACIOCR2_ACPDRCLKGATE0_SHIFT #undef DDR_PHY_ACIOCR2_ACPDRCLKGATE0_MASK -#define DDR_PHY_ACIOCR2_ACPDRCLKGATE0_DEFVAL 0x00000000 -#define DDR_PHY_ACIOCR2_ACPDRCLKGATE0_SHIFT 29 -#define DDR_PHY_ACIOCR2_ACPDRCLKGATE0_MASK 0x20000000U +#define DDR_PHY_ACIOCR2_ACPDRCLKGATE0_DEFVAL 0x00000000 +#define DDR_PHY_ACIOCR2_ACPDRCLKGATE0_SHIFT 29 +#define DDR_PHY_ACIOCR2_ACPDRCLKGATE0_MASK 0x20000000U -/*Clock gating for Termination Enable D slices [0]*/ +/* +* Clock gating for Termination Enable D slices [0] +*/ #undef DDR_PHY_ACIOCR2_ACTECLKGATE0_DEFVAL #undef DDR_PHY_ACIOCR2_ACTECLKGATE0_SHIFT #undef DDR_PHY_ACIOCR2_ACTECLKGATE0_MASK -#define DDR_PHY_ACIOCR2_ACTECLKGATE0_DEFVAL 0x00000000 -#define DDR_PHY_ACIOCR2_ACTECLKGATE0_SHIFT 28 -#define DDR_PHY_ACIOCR2_ACTECLKGATE0_MASK 0x10000000U +#define DDR_PHY_ACIOCR2_ACTECLKGATE0_DEFVAL 0x00000000 +#define DDR_PHY_ACIOCR2_ACTECLKGATE0_SHIFT 28 +#define DDR_PHY_ACIOCR2_ACTECLKGATE0_MASK 0x10000000U -/*Clock gating for CK# D slices [1:0]*/ +/* +* Clock gating for CK# D slices [1:0] +*/ #undef DDR_PHY_ACIOCR2_CKNCLKGATE0_DEFVAL #undef DDR_PHY_ACIOCR2_CKNCLKGATE0_SHIFT #undef DDR_PHY_ACIOCR2_CKNCLKGATE0_MASK -#define DDR_PHY_ACIOCR2_CKNCLKGATE0_DEFVAL 0x00000000 -#define DDR_PHY_ACIOCR2_CKNCLKGATE0_SHIFT 26 -#define DDR_PHY_ACIOCR2_CKNCLKGATE0_MASK 0x0C000000U +#define DDR_PHY_ACIOCR2_CKNCLKGATE0_DEFVAL 0x00000000 +#define DDR_PHY_ACIOCR2_CKNCLKGATE0_SHIFT 26 +#define DDR_PHY_ACIOCR2_CKNCLKGATE0_MASK 0x0C000000U -/*Clock gating for CK D slices [1:0]*/ +/* +* Clock gating for CK D slices [1:0] +*/ #undef DDR_PHY_ACIOCR2_CKCLKGATE0_DEFVAL #undef DDR_PHY_ACIOCR2_CKCLKGATE0_SHIFT #undef DDR_PHY_ACIOCR2_CKCLKGATE0_MASK -#define DDR_PHY_ACIOCR2_CKCLKGATE0_DEFVAL 0x00000000 -#define DDR_PHY_ACIOCR2_CKCLKGATE0_SHIFT 24 -#define DDR_PHY_ACIOCR2_CKCLKGATE0_MASK 0x03000000U +#define DDR_PHY_ACIOCR2_CKCLKGATE0_DEFVAL 0x00000000 +#define DDR_PHY_ACIOCR2_CKCLKGATE0_SHIFT 24 +#define DDR_PHY_ACIOCR2_CKCLKGATE0_MASK 0x03000000U -/*Clock gating for AC D slices [23:0]*/ +/* +* Clock gating for AC D slices [23:0] +*/ #undef DDR_PHY_ACIOCR2_ACCLKGATE0_DEFVAL #undef DDR_PHY_ACIOCR2_ACCLKGATE0_SHIFT #undef DDR_PHY_ACIOCR2_ACCLKGATE0_MASK -#define DDR_PHY_ACIOCR2_ACCLKGATE0_DEFVAL 0x00000000 -#define DDR_PHY_ACIOCR2_ACCLKGATE0_SHIFT 0 -#define DDR_PHY_ACIOCR2_ACCLKGATE0_MASK 0x00FFFFFFU +#define DDR_PHY_ACIOCR2_ACCLKGATE0_DEFVAL 0x00000000 +#define DDR_PHY_ACIOCR2_ACCLKGATE0_SHIFT 0 +#define DDR_PHY_ACIOCR2_ACCLKGATE0_MASK 0x00FFFFFFU -/*SDRAM Parity Output Enable (OE) Mode Selection*/ +/* +* SDRAM Parity Output Enable (OE) Mode Selection +*/ #undef DDR_PHY_ACIOCR3_PAROEMODE_DEFVAL #undef DDR_PHY_ACIOCR3_PAROEMODE_SHIFT #undef DDR_PHY_ACIOCR3_PAROEMODE_MASK -#define DDR_PHY_ACIOCR3_PAROEMODE_DEFVAL 0x00000005 -#define DDR_PHY_ACIOCR3_PAROEMODE_SHIFT 30 -#define DDR_PHY_ACIOCR3_PAROEMODE_MASK 0xC0000000U +#define DDR_PHY_ACIOCR3_PAROEMODE_DEFVAL 0x00000005 +#define DDR_PHY_ACIOCR3_PAROEMODE_SHIFT 30 +#define DDR_PHY_ACIOCR3_PAROEMODE_MASK 0xC0000000U -/*SDRAM Bank Group Output Enable (OE) Mode Selection*/ +/* +* SDRAM Bank Group Output Enable (OE) Mode Selection +*/ #undef DDR_PHY_ACIOCR3_BGOEMODE_DEFVAL #undef DDR_PHY_ACIOCR3_BGOEMODE_SHIFT #undef DDR_PHY_ACIOCR3_BGOEMODE_MASK -#define DDR_PHY_ACIOCR3_BGOEMODE_DEFVAL 0x00000005 -#define DDR_PHY_ACIOCR3_BGOEMODE_SHIFT 26 -#define DDR_PHY_ACIOCR3_BGOEMODE_MASK 0x3C000000U +#define DDR_PHY_ACIOCR3_BGOEMODE_DEFVAL 0x00000005 +#define DDR_PHY_ACIOCR3_BGOEMODE_SHIFT 26 +#define DDR_PHY_ACIOCR3_BGOEMODE_MASK 0x3C000000U -/*SDRAM Bank Address Output Enable (OE) Mode Selection*/ +/* +* SDRAM Bank Address Output Enable (OE) Mode Selection +*/ #undef DDR_PHY_ACIOCR3_BAOEMODE_DEFVAL #undef DDR_PHY_ACIOCR3_BAOEMODE_SHIFT #undef DDR_PHY_ACIOCR3_BAOEMODE_MASK -#define DDR_PHY_ACIOCR3_BAOEMODE_DEFVAL 0x00000005 -#define DDR_PHY_ACIOCR3_BAOEMODE_SHIFT 22 -#define DDR_PHY_ACIOCR3_BAOEMODE_MASK 0x03C00000U +#define DDR_PHY_ACIOCR3_BAOEMODE_DEFVAL 0x00000005 +#define DDR_PHY_ACIOCR3_BAOEMODE_SHIFT 22 +#define DDR_PHY_ACIOCR3_BAOEMODE_MASK 0x03C00000U -/*SDRAM A[17] Output Enable (OE) Mode Selection*/ +/* +* SDRAM A[17] Output Enable (OE) Mode Selection +*/ #undef DDR_PHY_ACIOCR3_A17OEMODE_DEFVAL #undef DDR_PHY_ACIOCR3_A17OEMODE_SHIFT #undef DDR_PHY_ACIOCR3_A17OEMODE_MASK -#define DDR_PHY_ACIOCR3_A17OEMODE_DEFVAL 0x00000005 -#define DDR_PHY_ACIOCR3_A17OEMODE_SHIFT 20 -#define DDR_PHY_ACIOCR3_A17OEMODE_MASK 0x00300000U +#define DDR_PHY_ACIOCR3_A17OEMODE_DEFVAL 0x00000005 +#define DDR_PHY_ACIOCR3_A17OEMODE_SHIFT 20 +#define DDR_PHY_ACIOCR3_A17OEMODE_MASK 0x00300000U -/*SDRAM A[16] / RAS_n Output Enable (OE) Mode Selection*/ +/* +* SDRAM A[16] / RAS_n Output Enable (OE) Mode Selection +*/ #undef DDR_PHY_ACIOCR3_A16OEMODE_DEFVAL #undef DDR_PHY_ACIOCR3_A16OEMODE_SHIFT #undef DDR_PHY_ACIOCR3_A16OEMODE_MASK -#define DDR_PHY_ACIOCR3_A16OEMODE_DEFVAL 0x00000005 -#define DDR_PHY_ACIOCR3_A16OEMODE_SHIFT 18 -#define DDR_PHY_ACIOCR3_A16OEMODE_MASK 0x000C0000U +#define DDR_PHY_ACIOCR3_A16OEMODE_DEFVAL 0x00000005 +#define DDR_PHY_ACIOCR3_A16OEMODE_SHIFT 18 +#define DDR_PHY_ACIOCR3_A16OEMODE_MASK 0x000C0000U -/*SDRAM ACT_n Output Enable (OE) Mode Selection (DDR4 only)*/ +/* +* SDRAM ACT_n Output Enable (OE) Mode Selection (DDR4 only) +*/ #undef DDR_PHY_ACIOCR3_ACTOEMODE_DEFVAL #undef DDR_PHY_ACIOCR3_ACTOEMODE_SHIFT #undef DDR_PHY_ACIOCR3_ACTOEMODE_MASK -#define DDR_PHY_ACIOCR3_ACTOEMODE_DEFVAL 0x00000005 -#define DDR_PHY_ACIOCR3_ACTOEMODE_SHIFT 16 -#define DDR_PHY_ACIOCR3_ACTOEMODE_MASK 0x00030000U +#define DDR_PHY_ACIOCR3_ACTOEMODE_DEFVAL 0x00000005 +#define DDR_PHY_ACIOCR3_ACTOEMODE_SHIFT 16 +#define DDR_PHY_ACIOCR3_ACTOEMODE_MASK 0x00030000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACIOCR3_RESERVED_15_8_DEFVAL #undef DDR_PHY_ACIOCR3_RESERVED_15_8_SHIFT #undef DDR_PHY_ACIOCR3_RESERVED_15_8_MASK -#define DDR_PHY_ACIOCR3_RESERVED_15_8_DEFVAL 0x00000005 -#define DDR_PHY_ACIOCR3_RESERVED_15_8_SHIFT 8 -#define DDR_PHY_ACIOCR3_RESERVED_15_8_MASK 0x0000FF00U +#define DDR_PHY_ACIOCR3_RESERVED_15_8_DEFVAL 0x00000005 +#define DDR_PHY_ACIOCR3_RESERVED_15_8_SHIFT 8 +#define DDR_PHY_ACIOCR3_RESERVED_15_8_MASK 0x0000FF00U -/*Reserved. Return zeros on reads.*/ +/* +* Reserved. Return zeros on reads. +*/ #undef DDR_PHY_ACIOCR3_CKOEMODE_RSVD_DEFVAL #undef DDR_PHY_ACIOCR3_CKOEMODE_RSVD_SHIFT #undef DDR_PHY_ACIOCR3_CKOEMODE_RSVD_MASK -#define DDR_PHY_ACIOCR3_CKOEMODE_RSVD_DEFVAL 0x00000005 -#define DDR_PHY_ACIOCR3_CKOEMODE_RSVD_SHIFT 4 -#define DDR_PHY_ACIOCR3_CKOEMODE_RSVD_MASK 0x000000F0U +#define DDR_PHY_ACIOCR3_CKOEMODE_RSVD_DEFVAL 0x00000005 +#define DDR_PHY_ACIOCR3_CKOEMODE_RSVD_SHIFT 4 +#define DDR_PHY_ACIOCR3_CKOEMODE_RSVD_MASK 0x000000F0U -/*SDRAM CK Output Enable (OE) Mode Selection.*/ +/* +* SDRAM CK Output Enable (OE) Mode Selection. +*/ #undef DDR_PHY_ACIOCR3_CKOEMODE_DEFVAL #undef DDR_PHY_ACIOCR3_CKOEMODE_SHIFT #undef DDR_PHY_ACIOCR3_CKOEMODE_MASK -#define DDR_PHY_ACIOCR3_CKOEMODE_DEFVAL 0x00000005 -#define DDR_PHY_ACIOCR3_CKOEMODE_SHIFT 0 -#define DDR_PHY_ACIOCR3_CKOEMODE_MASK 0x0000000FU +#define DDR_PHY_ACIOCR3_CKOEMODE_DEFVAL 0x00000005 +#define DDR_PHY_ACIOCR3_CKOEMODE_SHIFT 0 +#define DDR_PHY_ACIOCR3_CKOEMODE_MASK 0x0000000FU -/*Clock gating for AC LB slices and loopback read valid slices*/ +/* +* Clock gating for AC LB slices and loopback read valid slices +*/ #undef DDR_PHY_ACIOCR4_LBCLKGATE_DEFVAL #undef DDR_PHY_ACIOCR4_LBCLKGATE_SHIFT #undef DDR_PHY_ACIOCR4_LBCLKGATE_MASK -#define DDR_PHY_ACIOCR4_LBCLKGATE_DEFVAL 0x00000000 -#define DDR_PHY_ACIOCR4_LBCLKGATE_SHIFT 31 -#define DDR_PHY_ACIOCR4_LBCLKGATE_MASK 0x80000000U +#define DDR_PHY_ACIOCR4_LBCLKGATE_DEFVAL 0x00000000 +#define DDR_PHY_ACIOCR4_LBCLKGATE_SHIFT 31 +#define DDR_PHY_ACIOCR4_LBCLKGATE_MASK 0x80000000U -/*Clock gating for Output Enable D slices [1]*/ +/* +* Clock gating for Output Enable D slices [1] +*/ #undef DDR_PHY_ACIOCR4_ACOECLKGATE1_DEFVAL #undef DDR_PHY_ACIOCR4_ACOECLKGATE1_SHIFT #undef DDR_PHY_ACIOCR4_ACOECLKGATE1_MASK -#define DDR_PHY_ACIOCR4_ACOECLKGATE1_DEFVAL 0x00000000 -#define DDR_PHY_ACIOCR4_ACOECLKGATE1_SHIFT 30 -#define DDR_PHY_ACIOCR4_ACOECLKGATE1_MASK 0x40000000U +#define DDR_PHY_ACIOCR4_ACOECLKGATE1_DEFVAL 0x00000000 +#define DDR_PHY_ACIOCR4_ACOECLKGATE1_SHIFT 30 +#define DDR_PHY_ACIOCR4_ACOECLKGATE1_MASK 0x40000000U -/*Clock gating for Power Down Receiver D slices [1]*/ +/* +* Clock gating for Power Down Receiver D slices [1] +*/ #undef DDR_PHY_ACIOCR4_ACPDRCLKGATE1_DEFVAL #undef DDR_PHY_ACIOCR4_ACPDRCLKGATE1_SHIFT #undef DDR_PHY_ACIOCR4_ACPDRCLKGATE1_MASK -#define DDR_PHY_ACIOCR4_ACPDRCLKGATE1_DEFVAL 0x00000000 -#define DDR_PHY_ACIOCR4_ACPDRCLKGATE1_SHIFT 29 -#define DDR_PHY_ACIOCR4_ACPDRCLKGATE1_MASK 0x20000000U +#define DDR_PHY_ACIOCR4_ACPDRCLKGATE1_DEFVAL 0x00000000 +#define DDR_PHY_ACIOCR4_ACPDRCLKGATE1_SHIFT 29 +#define DDR_PHY_ACIOCR4_ACPDRCLKGATE1_MASK 0x20000000U -/*Clock gating for Termination Enable D slices [1]*/ +/* +* Clock gating for Termination Enable D slices [1] +*/ #undef DDR_PHY_ACIOCR4_ACTECLKGATE1_DEFVAL #undef DDR_PHY_ACIOCR4_ACTECLKGATE1_SHIFT #undef DDR_PHY_ACIOCR4_ACTECLKGATE1_MASK -#define DDR_PHY_ACIOCR4_ACTECLKGATE1_DEFVAL 0x00000000 -#define DDR_PHY_ACIOCR4_ACTECLKGATE1_SHIFT 28 -#define DDR_PHY_ACIOCR4_ACTECLKGATE1_MASK 0x10000000U +#define DDR_PHY_ACIOCR4_ACTECLKGATE1_DEFVAL 0x00000000 +#define DDR_PHY_ACIOCR4_ACTECLKGATE1_SHIFT 28 +#define DDR_PHY_ACIOCR4_ACTECLKGATE1_MASK 0x10000000U -/*Clock gating for CK# D slices [3:2]*/ +/* +* Clock gating for CK# D slices [3:2] +*/ #undef DDR_PHY_ACIOCR4_CKNCLKGATE1_DEFVAL #undef DDR_PHY_ACIOCR4_CKNCLKGATE1_SHIFT #undef DDR_PHY_ACIOCR4_CKNCLKGATE1_MASK -#define DDR_PHY_ACIOCR4_CKNCLKGATE1_DEFVAL 0x00000000 -#define DDR_PHY_ACIOCR4_CKNCLKGATE1_SHIFT 26 -#define DDR_PHY_ACIOCR4_CKNCLKGATE1_MASK 0x0C000000U +#define DDR_PHY_ACIOCR4_CKNCLKGATE1_DEFVAL 0x00000000 +#define DDR_PHY_ACIOCR4_CKNCLKGATE1_SHIFT 26 +#define DDR_PHY_ACIOCR4_CKNCLKGATE1_MASK 0x0C000000U -/*Clock gating for CK D slices [3:2]*/ +/* +* Clock gating for CK D slices [3:2] +*/ #undef DDR_PHY_ACIOCR4_CKCLKGATE1_DEFVAL #undef DDR_PHY_ACIOCR4_CKCLKGATE1_SHIFT #undef DDR_PHY_ACIOCR4_CKCLKGATE1_MASK -#define DDR_PHY_ACIOCR4_CKCLKGATE1_DEFVAL 0x00000000 -#define DDR_PHY_ACIOCR4_CKCLKGATE1_SHIFT 24 -#define DDR_PHY_ACIOCR4_CKCLKGATE1_MASK 0x03000000U +#define DDR_PHY_ACIOCR4_CKCLKGATE1_DEFVAL 0x00000000 +#define DDR_PHY_ACIOCR4_CKCLKGATE1_SHIFT 24 +#define DDR_PHY_ACIOCR4_CKCLKGATE1_MASK 0x03000000U -/*Clock gating for AC D slices [47:24]*/ +/* +* Clock gating for AC D slices [47:24] +*/ #undef DDR_PHY_ACIOCR4_ACCLKGATE1_DEFVAL #undef DDR_PHY_ACIOCR4_ACCLKGATE1_SHIFT #undef DDR_PHY_ACIOCR4_ACCLKGATE1_MASK -#define DDR_PHY_ACIOCR4_ACCLKGATE1_DEFVAL 0x00000000 -#define DDR_PHY_ACIOCR4_ACCLKGATE1_SHIFT 0 -#define DDR_PHY_ACIOCR4_ACCLKGATE1_MASK 0x00FFFFFFU +#define DDR_PHY_ACIOCR4_ACCLKGATE1_DEFVAL 0x00000000 +#define DDR_PHY_ACIOCR4_ACCLKGATE1_SHIFT 0 +#define DDR_PHY_ACIOCR4_ACCLKGATE1_MASK 0x00FFFFFFU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_IOVCR0_RESERVED_31_29_DEFVAL #undef DDR_PHY_IOVCR0_RESERVED_31_29_SHIFT #undef DDR_PHY_IOVCR0_RESERVED_31_29_MASK -#define DDR_PHY_IOVCR0_RESERVED_31_29_DEFVAL 0x0F000000 -#define DDR_PHY_IOVCR0_RESERVED_31_29_SHIFT 29 -#define DDR_PHY_IOVCR0_RESERVED_31_29_MASK 0xE0000000U +#define DDR_PHY_IOVCR0_RESERVED_31_29_DEFVAL 0x0F000000 +#define DDR_PHY_IOVCR0_RESERVED_31_29_SHIFT 29 +#define DDR_PHY_IOVCR0_RESERVED_31_29_MASK 0xE0000000U -/*Address/command lane VREF Pad Enable*/ +/* +* Address/command lane VREF Pad Enable +*/ #undef DDR_PHY_IOVCR0_ACREFPEN_DEFVAL #undef DDR_PHY_IOVCR0_ACREFPEN_SHIFT #undef DDR_PHY_IOVCR0_ACREFPEN_MASK -#define DDR_PHY_IOVCR0_ACREFPEN_DEFVAL 0x0F000000 -#define DDR_PHY_IOVCR0_ACREFPEN_SHIFT 28 -#define DDR_PHY_IOVCR0_ACREFPEN_MASK 0x10000000U +#define DDR_PHY_IOVCR0_ACREFPEN_DEFVAL 0x0F000000 +#define DDR_PHY_IOVCR0_ACREFPEN_SHIFT 28 +#define DDR_PHY_IOVCR0_ACREFPEN_MASK 0x10000000U -/*Address/command lane Internal VREF Enable*/ +/* +* Address/command lane Internal VREF Enable +*/ #undef DDR_PHY_IOVCR0_ACREFEEN_DEFVAL #undef DDR_PHY_IOVCR0_ACREFEEN_SHIFT #undef DDR_PHY_IOVCR0_ACREFEEN_MASK -#define DDR_PHY_IOVCR0_ACREFEEN_DEFVAL 0x0F000000 -#define DDR_PHY_IOVCR0_ACREFEEN_SHIFT 26 -#define DDR_PHY_IOVCR0_ACREFEEN_MASK 0x0C000000U +#define DDR_PHY_IOVCR0_ACREFEEN_DEFVAL 0x0F000000 +#define DDR_PHY_IOVCR0_ACREFEEN_SHIFT 26 +#define DDR_PHY_IOVCR0_ACREFEEN_MASK 0x0C000000U -/*Address/command lane Single-End VREF Enable*/ +/* +* Address/command lane Single-End VREF Enable +*/ #undef DDR_PHY_IOVCR0_ACREFSEN_DEFVAL #undef DDR_PHY_IOVCR0_ACREFSEN_SHIFT #undef DDR_PHY_IOVCR0_ACREFSEN_MASK -#define DDR_PHY_IOVCR0_ACREFSEN_DEFVAL 0x0F000000 -#define DDR_PHY_IOVCR0_ACREFSEN_SHIFT 25 -#define DDR_PHY_IOVCR0_ACREFSEN_MASK 0x02000000U +#define DDR_PHY_IOVCR0_ACREFSEN_DEFVAL 0x0F000000 +#define DDR_PHY_IOVCR0_ACREFSEN_SHIFT 25 +#define DDR_PHY_IOVCR0_ACREFSEN_MASK 0x02000000U -/*Address/command lane Internal VREF Enable*/ +/* +* Address/command lane Internal VREF Enable +*/ #undef DDR_PHY_IOVCR0_ACREFIEN_DEFVAL #undef DDR_PHY_IOVCR0_ACREFIEN_SHIFT #undef DDR_PHY_IOVCR0_ACREFIEN_MASK -#define DDR_PHY_IOVCR0_ACREFIEN_DEFVAL 0x0F000000 -#define DDR_PHY_IOVCR0_ACREFIEN_SHIFT 24 -#define DDR_PHY_IOVCR0_ACREFIEN_MASK 0x01000000U +#define DDR_PHY_IOVCR0_ACREFIEN_DEFVAL 0x0F000000 +#define DDR_PHY_IOVCR0_ACREFIEN_SHIFT 24 +#define DDR_PHY_IOVCR0_ACREFIEN_MASK 0x01000000U -/*External VREF generato REFSEL range select*/ +/* +* External VREF generato REFSEL range select +*/ #undef DDR_PHY_IOVCR0_ACREFESELRANGE_DEFVAL #undef DDR_PHY_IOVCR0_ACREFESELRANGE_SHIFT #undef DDR_PHY_IOVCR0_ACREFESELRANGE_MASK -#define DDR_PHY_IOVCR0_ACREFESELRANGE_DEFVAL 0x0F000000 -#define DDR_PHY_IOVCR0_ACREFESELRANGE_SHIFT 23 -#define DDR_PHY_IOVCR0_ACREFESELRANGE_MASK 0x00800000U +#define DDR_PHY_IOVCR0_ACREFESELRANGE_DEFVAL 0x0F000000 +#define DDR_PHY_IOVCR0_ACREFESELRANGE_SHIFT 23 +#define DDR_PHY_IOVCR0_ACREFESELRANGE_MASK 0x00800000U -/*Address/command lane External VREF Select*/ +/* +* Address/command lane External VREF Select +*/ #undef DDR_PHY_IOVCR0_ACREFESEL_DEFVAL #undef DDR_PHY_IOVCR0_ACREFESEL_SHIFT #undef DDR_PHY_IOVCR0_ACREFESEL_MASK -#define DDR_PHY_IOVCR0_ACREFESEL_DEFVAL 0x0F000000 -#define DDR_PHY_IOVCR0_ACREFESEL_SHIFT 16 -#define DDR_PHY_IOVCR0_ACREFESEL_MASK 0x007F0000U +#define DDR_PHY_IOVCR0_ACREFESEL_DEFVAL 0x0F000000 +#define DDR_PHY_IOVCR0_ACREFESEL_SHIFT 16 +#define DDR_PHY_IOVCR0_ACREFESEL_MASK 0x007F0000U -/*Single ended VREF generator REFSEL range select*/ +/* +* Single ended VREF generator REFSEL range select +*/ #undef DDR_PHY_IOVCR0_ACREFSSELRANGE_DEFVAL #undef DDR_PHY_IOVCR0_ACREFSSELRANGE_SHIFT #undef DDR_PHY_IOVCR0_ACREFSSELRANGE_MASK -#define DDR_PHY_IOVCR0_ACREFSSELRANGE_DEFVAL 0x0F000000 -#define DDR_PHY_IOVCR0_ACREFSSELRANGE_SHIFT 15 -#define DDR_PHY_IOVCR0_ACREFSSELRANGE_MASK 0x00008000U +#define DDR_PHY_IOVCR0_ACREFSSELRANGE_DEFVAL 0x0F000000 +#define DDR_PHY_IOVCR0_ACREFSSELRANGE_SHIFT 15 +#define DDR_PHY_IOVCR0_ACREFSSELRANGE_MASK 0x00008000U -/*Address/command lane Single-End VREF Select*/ +/* +* Address/command lane Single-End VREF Select +*/ #undef DDR_PHY_IOVCR0_ACREFSSEL_DEFVAL #undef DDR_PHY_IOVCR0_ACREFSSEL_SHIFT #undef DDR_PHY_IOVCR0_ACREFSSEL_MASK -#define DDR_PHY_IOVCR0_ACREFSSEL_DEFVAL 0x0F000000 -#define DDR_PHY_IOVCR0_ACREFSSEL_SHIFT 8 -#define DDR_PHY_IOVCR0_ACREFSSEL_MASK 0x00007F00U +#define DDR_PHY_IOVCR0_ACREFSSEL_DEFVAL 0x0F000000 +#define DDR_PHY_IOVCR0_ACREFSSEL_SHIFT 8 +#define DDR_PHY_IOVCR0_ACREFSSEL_MASK 0x00007F00U -/*Internal VREF generator REFSEL ragne select*/ +/* +* Internal VREF generator REFSEL ragne select +*/ #undef DDR_PHY_IOVCR0_ACVREFISELRANGE_DEFVAL #undef DDR_PHY_IOVCR0_ACVREFISELRANGE_SHIFT #undef DDR_PHY_IOVCR0_ACVREFISELRANGE_MASK -#define DDR_PHY_IOVCR0_ACVREFISELRANGE_DEFVAL 0x0F000000 -#define DDR_PHY_IOVCR0_ACVREFISELRANGE_SHIFT 7 -#define DDR_PHY_IOVCR0_ACVREFISELRANGE_MASK 0x00000080U +#define DDR_PHY_IOVCR0_ACVREFISELRANGE_DEFVAL 0x0F000000 +#define DDR_PHY_IOVCR0_ACVREFISELRANGE_SHIFT 7 +#define DDR_PHY_IOVCR0_ACVREFISELRANGE_MASK 0x00000080U -/*REFSEL Control for internal AC IOs*/ +/* +* REFSEL Control for internal AC IOs +*/ #undef DDR_PHY_IOVCR0_ACVREFISEL_DEFVAL #undef DDR_PHY_IOVCR0_ACVREFISEL_SHIFT #undef DDR_PHY_IOVCR0_ACVREFISEL_MASK -#define DDR_PHY_IOVCR0_ACVREFISEL_DEFVAL 0x0F000000 -#define DDR_PHY_IOVCR0_ACVREFISEL_SHIFT 0 -#define DDR_PHY_IOVCR0_ACVREFISEL_MASK 0x0000007FU +#define DDR_PHY_IOVCR0_ACVREFISEL_DEFVAL 0x0F000000 +#define DDR_PHY_IOVCR0_ACVREFISEL_SHIFT 0 +#define DDR_PHY_IOVCR0_ACVREFISEL_MASK 0x0000007FU -/*Number of ctl_clk required to meet (> 150ns) timing requirements during DRAM DQ VREF training*/ +/* +* Number of ctl_clk required to meet (> 150ns) timing requirements during + * DRAM DQ VREF training +*/ #undef DDR_PHY_VTCR0_TVREF_DEFVAL #undef DDR_PHY_VTCR0_TVREF_SHIFT #undef DDR_PHY_VTCR0_TVREF_MASK -#define DDR_PHY_VTCR0_TVREF_DEFVAL 0x70032019 -#define DDR_PHY_VTCR0_TVREF_SHIFT 29 -#define DDR_PHY_VTCR0_TVREF_MASK 0xE0000000U +#define DDR_PHY_VTCR0_TVREF_DEFVAL 0x70032019 +#define DDR_PHY_VTCR0_TVREF_SHIFT 29 +#define DDR_PHY_VTCR0_TVREF_MASK 0xE0000000U -/*DRM DQ VREF training Enable*/ +/* +* DRM DQ VREF training Enable +*/ #undef DDR_PHY_VTCR0_DVEN_DEFVAL #undef DDR_PHY_VTCR0_DVEN_SHIFT #undef DDR_PHY_VTCR0_DVEN_MASK -#define DDR_PHY_VTCR0_DVEN_DEFVAL 0x70032019 -#define DDR_PHY_VTCR0_DVEN_SHIFT 28 -#define DDR_PHY_VTCR0_DVEN_MASK 0x10000000U +#define DDR_PHY_VTCR0_DVEN_DEFVAL 0x70032019 +#define DDR_PHY_VTCR0_DVEN_SHIFT 28 +#define DDR_PHY_VTCR0_DVEN_MASK 0x10000000U -/*Per Device Addressability Enable*/ +/* +* Per Device Addressability Enable +*/ #undef DDR_PHY_VTCR0_PDAEN_DEFVAL #undef DDR_PHY_VTCR0_PDAEN_SHIFT #undef DDR_PHY_VTCR0_PDAEN_MASK -#define DDR_PHY_VTCR0_PDAEN_DEFVAL 0x70032019 -#define DDR_PHY_VTCR0_PDAEN_SHIFT 27 -#define DDR_PHY_VTCR0_PDAEN_MASK 0x08000000U +#define DDR_PHY_VTCR0_PDAEN_DEFVAL 0x70032019 +#define DDR_PHY_VTCR0_PDAEN_SHIFT 27 +#define DDR_PHY_VTCR0_PDAEN_MASK 0x08000000U -/*Reserved. Returns zeroes on reads.*/ +/* +* Reserved. Returns zeroes on reads. +*/ #undef DDR_PHY_VTCR0_RESERVED_26_DEFVAL #undef DDR_PHY_VTCR0_RESERVED_26_SHIFT #undef DDR_PHY_VTCR0_RESERVED_26_MASK -#define DDR_PHY_VTCR0_RESERVED_26_DEFVAL 0x70032019 -#define DDR_PHY_VTCR0_RESERVED_26_SHIFT 26 -#define DDR_PHY_VTCR0_RESERVED_26_MASK 0x04000000U +#define DDR_PHY_VTCR0_RESERVED_26_DEFVAL 0x70032019 +#define DDR_PHY_VTCR0_RESERVED_26_SHIFT 26 +#define DDR_PHY_VTCR0_RESERVED_26_MASK 0x04000000U -/*VREF Word Count*/ +/* +* VREF Word Count +*/ #undef DDR_PHY_VTCR0_VWCR_DEFVAL #undef DDR_PHY_VTCR0_VWCR_SHIFT #undef DDR_PHY_VTCR0_VWCR_MASK -#define DDR_PHY_VTCR0_VWCR_DEFVAL 0x70032019 -#define DDR_PHY_VTCR0_VWCR_SHIFT 22 -#define DDR_PHY_VTCR0_VWCR_MASK 0x03C00000U +#define DDR_PHY_VTCR0_VWCR_DEFVAL 0x70032019 +#define DDR_PHY_VTCR0_VWCR_SHIFT 22 +#define DDR_PHY_VTCR0_VWCR_MASK 0x03C00000U -/*DRAM DQ VREF step size used during DRAM VREF training*/ +/* +* DRAM DQ VREF step size used during DRAM VREF training +*/ #undef DDR_PHY_VTCR0_DVSS_DEFVAL #undef DDR_PHY_VTCR0_DVSS_SHIFT #undef DDR_PHY_VTCR0_DVSS_MASK -#define DDR_PHY_VTCR0_DVSS_DEFVAL 0x70032019 -#define DDR_PHY_VTCR0_DVSS_SHIFT 18 -#define DDR_PHY_VTCR0_DVSS_MASK 0x003C0000U +#define DDR_PHY_VTCR0_DVSS_DEFVAL 0x70032019 +#define DDR_PHY_VTCR0_DVSS_SHIFT 18 +#define DDR_PHY_VTCR0_DVSS_MASK 0x003C0000U -/*Maximum VREF limit value used during DRAM VREF training*/ +/* +* Maximum VREF limit value used during DRAM VREF training +*/ #undef DDR_PHY_VTCR0_DVMAX_DEFVAL #undef DDR_PHY_VTCR0_DVMAX_SHIFT #undef DDR_PHY_VTCR0_DVMAX_MASK -#define DDR_PHY_VTCR0_DVMAX_DEFVAL 0x70032019 -#define DDR_PHY_VTCR0_DVMAX_SHIFT 12 -#define DDR_PHY_VTCR0_DVMAX_MASK 0x0003F000U +#define DDR_PHY_VTCR0_DVMAX_DEFVAL 0x70032019 +#define DDR_PHY_VTCR0_DVMAX_SHIFT 12 +#define DDR_PHY_VTCR0_DVMAX_MASK 0x0003F000U -/*Minimum VREF limit value used during DRAM VREF training*/ +/* +* Minimum VREF limit value used during DRAM VREF training +*/ #undef DDR_PHY_VTCR0_DVMIN_DEFVAL #undef DDR_PHY_VTCR0_DVMIN_SHIFT #undef DDR_PHY_VTCR0_DVMIN_MASK -#define DDR_PHY_VTCR0_DVMIN_DEFVAL 0x70032019 -#define DDR_PHY_VTCR0_DVMIN_SHIFT 6 -#define DDR_PHY_VTCR0_DVMIN_MASK 0x00000FC0U +#define DDR_PHY_VTCR0_DVMIN_DEFVAL 0x70032019 +#define DDR_PHY_VTCR0_DVMIN_SHIFT 6 +#define DDR_PHY_VTCR0_DVMIN_MASK 0x00000FC0U -/*Initial DRAM DQ VREF value used during DRAM VREF training*/ +/* +* Initial DRAM DQ VREF value used during DRAM VREF training +*/ #undef DDR_PHY_VTCR0_DVINIT_DEFVAL #undef DDR_PHY_VTCR0_DVINIT_SHIFT #undef DDR_PHY_VTCR0_DVINIT_MASK -#define DDR_PHY_VTCR0_DVINIT_DEFVAL 0x70032019 -#define DDR_PHY_VTCR0_DVINIT_SHIFT 0 -#define DDR_PHY_VTCR0_DVINIT_MASK 0x0000003FU +#define DDR_PHY_VTCR0_DVINIT_DEFVAL 0x70032019 +#define DDR_PHY_VTCR0_DVINIT_SHIFT 0 +#define DDR_PHY_VTCR0_DVINIT_MASK 0x0000003FU -/*Host VREF step size used during VREF training. The register value of N indicates step size of (N+1)*/ +/* +* Host VREF step size used during VREF training. The register value of N i + * ndicates step size of (N+1) +*/ #undef DDR_PHY_VTCR1_HVSS_DEFVAL #undef DDR_PHY_VTCR1_HVSS_SHIFT #undef DDR_PHY_VTCR1_HVSS_MASK -#define DDR_PHY_VTCR1_HVSS_DEFVAL 0x07F00072 -#define DDR_PHY_VTCR1_HVSS_SHIFT 28 -#define DDR_PHY_VTCR1_HVSS_MASK 0xF0000000U +#define DDR_PHY_VTCR1_HVSS_DEFVAL 0x07F00072 +#define DDR_PHY_VTCR1_HVSS_SHIFT 28 +#define DDR_PHY_VTCR1_HVSS_MASK 0xF0000000U -/*Reserved. Returns zeroes on reads.*/ +/* +* Reserved. Returns zeroes on reads. +*/ #undef DDR_PHY_VTCR1_RESERVED_27_DEFVAL #undef DDR_PHY_VTCR1_RESERVED_27_SHIFT #undef DDR_PHY_VTCR1_RESERVED_27_MASK -#define DDR_PHY_VTCR1_RESERVED_27_DEFVAL 0x07F00072 -#define DDR_PHY_VTCR1_RESERVED_27_SHIFT 27 -#define DDR_PHY_VTCR1_RESERVED_27_MASK 0x08000000U +#define DDR_PHY_VTCR1_RESERVED_27_DEFVAL 0x07F00072 +#define DDR_PHY_VTCR1_RESERVED_27_SHIFT 27 +#define DDR_PHY_VTCR1_RESERVED_27_MASK 0x08000000U -/*Maximum VREF limit value used during DRAM VREF training.*/ +/* +* Maximum VREF limit value used during DRAM VREF training. +*/ #undef DDR_PHY_VTCR1_HVMAX_DEFVAL #undef DDR_PHY_VTCR1_HVMAX_SHIFT #undef DDR_PHY_VTCR1_HVMAX_MASK -#define DDR_PHY_VTCR1_HVMAX_DEFVAL 0x07F00072 -#define DDR_PHY_VTCR1_HVMAX_SHIFT 20 -#define DDR_PHY_VTCR1_HVMAX_MASK 0x07F00000U +#define DDR_PHY_VTCR1_HVMAX_DEFVAL 0x07F00072 +#define DDR_PHY_VTCR1_HVMAX_SHIFT 20 +#define DDR_PHY_VTCR1_HVMAX_MASK 0x07F00000U -/*Reserved. Returns zeroes on reads.*/ +/* +* Reserved. Returns zeroes on reads. +*/ #undef DDR_PHY_VTCR1_RESERVED_19_DEFVAL #undef DDR_PHY_VTCR1_RESERVED_19_SHIFT #undef DDR_PHY_VTCR1_RESERVED_19_MASK -#define DDR_PHY_VTCR1_RESERVED_19_DEFVAL 0x07F00072 -#define DDR_PHY_VTCR1_RESERVED_19_SHIFT 19 -#define DDR_PHY_VTCR1_RESERVED_19_MASK 0x00080000U +#define DDR_PHY_VTCR1_RESERVED_19_DEFVAL 0x07F00072 +#define DDR_PHY_VTCR1_RESERVED_19_SHIFT 19 +#define DDR_PHY_VTCR1_RESERVED_19_MASK 0x00080000U -/*Minimum VREF limit value used during DRAM VREF training.*/ +/* +* Minimum VREF limit value used during DRAM VREF training. +*/ #undef DDR_PHY_VTCR1_HVMIN_DEFVAL #undef DDR_PHY_VTCR1_HVMIN_SHIFT #undef DDR_PHY_VTCR1_HVMIN_MASK -#define DDR_PHY_VTCR1_HVMIN_DEFVAL 0x07F00072 -#define DDR_PHY_VTCR1_HVMIN_SHIFT 12 -#define DDR_PHY_VTCR1_HVMIN_MASK 0x0007F000U +#define DDR_PHY_VTCR1_HVMIN_DEFVAL 0x07F00072 +#define DDR_PHY_VTCR1_HVMIN_SHIFT 12 +#define DDR_PHY_VTCR1_HVMIN_MASK 0x0007F000U -/*Reserved. Returns zeroes on reads.*/ +/* +* Reserved. Returns zeroes on reads. +*/ #undef DDR_PHY_VTCR1_RESERVED_11_DEFVAL #undef DDR_PHY_VTCR1_RESERVED_11_SHIFT #undef DDR_PHY_VTCR1_RESERVED_11_MASK -#define DDR_PHY_VTCR1_RESERVED_11_DEFVAL 0x07F00072 -#define DDR_PHY_VTCR1_RESERVED_11_SHIFT 11 -#define DDR_PHY_VTCR1_RESERVED_11_MASK 0x00000800U +#define DDR_PHY_VTCR1_RESERVED_11_DEFVAL 0x07F00072 +#define DDR_PHY_VTCR1_RESERVED_11_SHIFT 11 +#define DDR_PHY_VTCR1_RESERVED_11_MASK 0x00000800U -/*Static Host Vref Rank Value*/ +/* +* Static Host Vref Rank Value +*/ #undef DDR_PHY_VTCR1_SHRNK_DEFVAL #undef DDR_PHY_VTCR1_SHRNK_SHIFT #undef DDR_PHY_VTCR1_SHRNK_MASK -#define DDR_PHY_VTCR1_SHRNK_DEFVAL 0x07F00072 -#define DDR_PHY_VTCR1_SHRNK_SHIFT 9 -#define DDR_PHY_VTCR1_SHRNK_MASK 0x00000600U +#define DDR_PHY_VTCR1_SHRNK_DEFVAL 0x07F00072 +#define DDR_PHY_VTCR1_SHRNK_SHIFT 9 +#define DDR_PHY_VTCR1_SHRNK_MASK 0x00000600U -/*Static Host Vref Rank Enable*/ +/* +* Static Host Vref Rank Enable +*/ #undef DDR_PHY_VTCR1_SHREN_DEFVAL #undef DDR_PHY_VTCR1_SHREN_SHIFT #undef DDR_PHY_VTCR1_SHREN_MASK -#define DDR_PHY_VTCR1_SHREN_DEFVAL 0x07F00072 -#define DDR_PHY_VTCR1_SHREN_SHIFT 8 -#define DDR_PHY_VTCR1_SHREN_MASK 0x00000100U +#define DDR_PHY_VTCR1_SHREN_DEFVAL 0x07F00072 +#define DDR_PHY_VTCR1_SHREN_SHIFT 8 +#define DDR_PHY_VTCR1_SHREN_MASK 0x00000100U -/*Number of ctl_clk required to meet (> 200ns) VREF Settling timing requirements during Host IO VREF training*/ +/* +* Number of ctl_clk required to meet (> 200ns) VREF Settling timing requir + * ements during Host IO VREF training +*/ #undef DDR_PHY_VTCR1_TVREFIO_DEFVAL #undef DDR_PHY_VTCR1_TVREFIO_SHIFT #undef DDR_PHY_VTCR1_TVREFIO_MASK -#define DDR_PHY_VTCR1_TVREFIO_DEFVAL 0x07F00072 -#define DDR_PHY_VTCR1_TVREFIO_SHIFT 5 -#define DDR_PHY_VTCR1_TVREFIO_MASK 0x000000E0U +#define DDR_PHY_VTCR1_TVREFIO_DEFVAL 0x07F00072 +#define DDR_PHY_VTCR1_TVREFIO_SHIFT 5 +#define DDR_PHY_VTCR1_TVREFIO_MASK 0x000000E0U -/*Eye LCDL Offset value for VREF training*/ +/* +* Eye LCDL Offset value for VREF training +*/ #undef DDR_PHY_VTCR1_EOFF_DEFVAL #undef DDR_PHY_VTCR1_EOFF_SHIFT #undef DDR_PHY_VTCR1_EOFF_MASK -#define DDR_PHY_VTCR1_EOFF_DEFVAL 0x07F00072 -#define DDR_PHY_VTCR1_EOFF_SHIFT 3 -#define DDR_PHY_VTCR1_EOFF_MASK 0x00000018U +#define DDR_PHY_VTCR1_EOFF_DEFVAL 0x07F00072 +#define DDR_PHY_VTCR1_EOFF_SHIFT 3 +#define DDR_PHY_VTCR1_EOFF_MASK 0x00000018U -/*Number of LCDL Eye points for which VREF training is repeated*/ +/* +* Number of LCDL Eye points for which VREF training is repeated +*/ #undef DDR_PHY_VTCR1_ENUM_DEFVAL #undef DDR_PHY_VTCR1_ENUM_SHIFT #undef DDR_PHY_VTCR1_ENUM_MASK -#define DDR_PHY_VTCR1_ENUM_DEFVAL 0x07F00072 -#define DDR_PHY_VTCR1_ENUM_SHIFT 2 -#define DDR_PHY_VTCR1_ENUM_MASK 0x00000004U +#define DDR_PHY_VTCR1_ENUM_DEFVAL 0x07F00072 +#define DDR_PHY_VTCR1_ENUM_SHIFT 2 +#define DDR_PHY_VTCR1_ENUM_MASK 0x00000004U -/*HOST (IO) internal VREF training Enable*/ +/* +* HOST (IO) internal VREF training Enable +*/ #undef DDR_PHY_VTCR1_HVEN_DEFVAL #undef DDR_PHY_VTCR1_HVEN_SHIFT #undef DDR_PHY_VTCR1_HVEN_MASK -#define DDR_PHY_VTCR1_HVEN_DEFVAL 0x07F00072 -#define DDR_PHY_VTCR1_HVEN_SHIFT 1 -#define DDR_PHY_VTCR1_HVEN_MASK 0x00000002U +#define DDR_PHY_VTCR1_HVEN_DEFVAL 0x07F00072 +#define DDR_PHY_VTCR1_HVEN_SHIFT 1 +#define DDR_PHY_VTCR1_HVEN_MASK 0x00000002U -/*Host IO Type Control*/ +/* +* Host IO Type Control +*/ #undef DDR_PHY_VTCR1_HVIO_DEFVAL #undef DDR_PHY_VTCR1_HVIO_SHIFT #undef DDR_PHY_VTCR1_HVIO_MASK -#define DDR_PHY_VTCR1_HVIO_DEFVAL 0x07F00072 -#define DDR_PHY_VTCR1_HVIO_SHIFT 0 -#define DDR_PHY_VTCR1_HVIO_MASK 0x00000001U +#define DDR_PHY_VTCR1_HVIO_DEFVAL 0x07F00072 +#define DDR_PHY_VTCR1_HVIO_SHIFT 0 +#define DDR_PHY_VTCR1_HVIO_MASK 0x00000001U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR1_RESERVED_31_30_DEFVAL #undef DDR_PHY_ACBDLR1_RESERVED_31_30_SHIFT #undef DDR_PHY_ACBDLR1_RESERVED_31_30_MASK -#define DDR_PHY_ACBDLR1_RESERVED_31_30_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR1_RESERVED_31_30_SHIFT 30 -#define DDR_PHY_ACBDLR1_RESERVED_31_30_MASK 0xC0000000U +#define DDR_PHY_ACBDLR1_RESERVED_31_30_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR1_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_ACBDLR1_RESERVED_31_30_MASK 0xC0000000U -/*Delay select for the BDL on Parity.*/ +/* +* Delay select for the BDL on Parity. +*/ #undef DDR_PHY_ACBDLR1_PARBD_DEFVAL #undef DDR_PHY_ACBDLR1_PARBD_SHIFT #undef DDR_PHY_ACBDLR1_PARBD_MASK -#define DDR_PHY_ACBDLR1_PARBD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR1_PARBD_SHIFT 24 -#define DDR_PHY_ACBDLR1_PARBD_MASK 0x3F000000U +#define DDR_PHY_ACBDLR1_PARBD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR1_PARBD_SHIFT 24 +#define DDR_PHY_ACBDLR1_PARBD_MASK 0x3F000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR1_RESERVED_23_22_DEFVAL #undef DDR_PHY_ACBDLR1_RESERVED_23_22_SHIFT #undef DDR_PHY_ACBDLR1_RESERVED_23_22_MASK -#define DDR_PHY_ACBDLR1_RESERVED_23_22_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR1_RESERVED_23_22_SHIFT 22 -#define DDR_PHY_ACBDLR1_RESERVED_23_22_MASK 0x00C00000U +#define DDR_PHY_ACBDLR1_RESERVED_23_22_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR1_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_ACBDLR1_RESERVED_23_22_MASK 0x00C00000U -/*Delay select for the BDL on Address A[16]. In DDR3 mode this pin is connected to WE.*/ +/* +* Delay select for the BDL on Address A[16]. In DDR3 mode this pin is conn + * ected to WE. +*/ #undef DDR_PHY_ACBDLR1_A16BD_DEFVAL #undef DDR_PHY_ACBDLR1_A16BD_SHIFT #undef DDR_PHY_ACBDLR1_A16BD_MASK -#define DDR_PHY_ACBDLR1_A16BD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR1_A16BD_SHIFT 16 -#define DDR_PHY_ACBDLR1_A16BD_MASK 0x003F0000U +#define DDR_PHY_ACBDLR1_A16BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR1_A16BD_SHIFT 16 +#define DDR_PHY_ACBDLR1_A16BD_MASK 0x003F0000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR1_RESERVED_15_14_DEFVAL #undef DDR_PHY_ACBDLR1_RESERVED_15_14_SHIFT #undef DDR_PHY_ACBDLR1_RESERVED_15_14_MASK -#define DDR_PHY_ACBDLR1_RESERVED_15_14_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR1_RESERVED_15_14_SHIFT 14 -#define DDR_PHY_ACBDLR1_RESERVED_15_14_MASK 0x0000C000U +#define DDR_PHY_ACBDLR1_RESERVED_15_14_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR1_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_ACBDLR1_RESERVED_15_14_MASK 0x0000C000U -/*Delay select for the BDL on Address A[17]. When not in DDR4 modemode this pin is connected to CAS.*/ +/* +* Delay select for the BDL on Address A[17]. When not in DDR4 modemode thi + * s pin is connected to CAS. +*/ #undef DDR_PHY_ACBDLR1_A17BD_DEFVAL #undef DDR_PHY_ACBDLR1_A17BD_SHIFT #undef DDR_PHY_ACBDLR1_A17BD_MASK -#define DDR_PHY_ACBDLR1_A17BD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR1_A17BD_SHIFT 8 -#define DDR_PHY_ACBDLR1_A17BD_MASK 0x00003F00U +#define DDR_PHY_ACBDLR1_A17BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR1_A17BD_SHIFT 8 +#define DDR_PHY_ACBDLR1_A17BD_MASK 0x00003F00U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR1_RESERVED_7_6_DEFVAL #undef DDR_PHY_ACBDLR1_RESERVED_7_6_SHIFT #undef DDR_PHY_ACBDLR1_RESERVED_7_6_MASK -#define DDR_PHY_ACBDLR1_RESERVED_7_6_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR1_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_ACBDLR1_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_ACBDLR1_RESERVED_7_6_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR1_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_ACBDLR1_RESERVED_7_6_MASK 0x000000C0U -/*Delay select for the BDL on ACTN.*/ +/* +* Delay select for the BDL on ACTN. +*/ #undef DDR_PHY_ACBDLR1_ACTBD_DEFVAL #undef DDR_PHY_ACBDLR1_ACTBD_SHIFT #undef DDR_PHY_ACBDLR1_ACTBD_MASK -#define DDR_PHY_ACBDLR1_ACTBD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR1_ACTBD_SHIFT 0 -#define DDR_PHY_ACBDLR1_ACTBD_MASK 0x0000003FU +#define DDR_PHY_ACBDLR1_ACTBD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR1_ACTBD_SHIFT 0 +#define DDR_PHY_ACBDLR1_ACTBD_MASK 0x0000003FU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR2_RESERVED_31_30_DEFVAL #undef DDR_PHY_ACBDLR2_RESERVED_31_30_SHIFT #undef DDR_PHY_ACBDLR2_RESERVED_31_30_MASK -#define DDR_PHY_ACBDLR2_RESERVED_31_30_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR2_RESERVED_31_30_SHIFT 30 -#define DDR_PHY_ACBDLR2_RESERVED_31_30_MASK 0xC0000000U +#define DDR_PHY_ACBDLR2_RESERVED_31_30_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR2_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_ACBDLR2_RESERVED_31_30_MASK 0xC0000000U -/*Delay select for the BDL on BG[1].*/ +/* +* Delay select for the BDL on BG[1]. +*/ #undef DDR_PHY_ACBDLR2_BG1BD_DEFVAL #undef DDR_PHY_ACBDLR2_BG1BD_SHIFT #undef DDR_PHY_ACBDLR2_BG1BD_MASK -#define DDR_PHY_ACBDLR2_BG1BD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR2_BG1BD_SHIFT 24 -#define DDR_PHY_ACBDLR2_BG1BD_MASK 0x3F000000U +#define DDR_PHY_ACBDLR2_BG1BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR2_BG1BD_SHIFT 24 +#define DDR_PHY_ACBDLR2_BG1BD_MASK 0x3F000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR2_RESERVED_23_22_DEFVAL #undef DDR_PHY_ACBDLR2_RESERVED_23_22_SHIFT #undef DDR_PHY_ACBDLR2_RESERVED_23_22_MASK -#define DDR_PHY_ACBDLR2_RESERVED_23_22_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR2_RESERVED_23_22_SHIFT 22 -#define DDR_PHY_ACBDLR2_RESERVED_23_22_MASK 0x00C00000U +#define DDR_PHY_ACBDLR2_RESERVED_23_22_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR2_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_ACBDLR2_RESERVED_23_22_MASK 0x00C00000U -/*Delay select for the BDL on BG[0].*/ +/* +* Delay select for the BDL on BG[0]. +*/ #undef DDR_PHY_ACBDLR2_BG0BD_DEFVAL #undef DDR_PHY_ACBDLR2_BG0BD_SHIFT #undef DDR_PHY_ACBDLR2_BG0BD_MASK -#define DDR_PHY_ACBDLR2_BG0BD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR2_BG0BD_SHIFT 16 -#define DDR_PHY_ACBDLR2_BG0BD_MASK 0x003F0000U +#define DDR_PHY_ACBDLR2_BG0BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR2_BG0BD_SHIFT 16 +#define DDR_PHY_ACBDLR2_BG0BD_MASK 0x003F0000U -/*Reser.ved Return zeroes on reads.*/ +/* +* Reser.ved Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR2_RESERVED_15_14_DEFVAL #undef DDR_PHY_ACBDLR2_RESERVED_15_14_SHIFT #undef DDR_PHY_ACBDLR2_RESERVED_15_14_MASK -#define DDR_PHY_ACBDLR2_RESERVED_15_14_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR2_RESERVED_15_14_SHIFT 14 -#define DDR_PHY_ACBDLR2_RESERVED_15_14_MASK 0x0000C000U +#define DDR_PHY_ACBDLR2_RESERVED_15_14_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR2_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_ACBDLR2_RESERVED_15_14_MASK 0x0000C000U -/*Delay select for the BDL on BA[1].*/ +/* +* Delay select for the BDL on BA[1]. +*/ #undef DDR_PHY_ACBDLR2_BA1BD_DEFVAL #undef DDR_PHY_ACBDLR2_BA1BD_SHIFT #undef DDR_PHY_ACBDLR2_BA1BD_MASK -#define DDR_PHY_ACBDLR2_BA1BD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR2_BA1BD_SHIFT 8 -#define DDR_PHY_ACBDLR2_BA1BD_MASK 0x00003F00U +#define DDR_PHY_ACBDLR2_BA1BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR2_BA1BD_SHIFT 8 +#define DDR_PHY_ACBDLR2_BA1BD_MASK 0x00003F00U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR2_RESERVED_7_6_DEFVAL #undef DDR_PHY_ACBDLR2_RESERVED_7_6_SHIFT #undef DDR_PHY_ACBDLR2_RESERVED_7_6_MASK -#define DDR_PHY_ACBDLR2_RESERVED_7_6_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR2_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_ACBDLR2_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_ACBDLR2_RESERVED_7_6_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR2_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_ACBDLR2_RESERVED_7_6_MASK 0x000000C0U -/*Delay select for the BDL on BA[0].*/ +/* +* Delay select for the BDL on BA[0]. +*/ #undef DDR_PHY_ACBDLR2_BA0BD_DEFVAL #undef DDR_PHY_ACBDLR2_BA0BD_SHIFT #undef DDR_PHY_ACBDLR2_BA0BD_MASK -#define DDR_PHY_ACBDLR2_BA0BD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR2_BA0BD_SHIFT 0 -#define DDR_PHY_ACBDLR2_BA0BD_MASK 0x0000003FU +#define DDR_PHY_ACBDLR2_BA0BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR2_BA0BD_SHIFT 0 +#define DDR_PHY_ACBDLR2_BA0BD_MASK 0x0000003FU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR6_RESERVED_31_30_DEFVAL #undef DDR_PHY_ACBDLR6_RESERVED_31_30_SHIFT #undef DDR_PHY_ACBDLR6_RESERVED_31_30_MASK -#define DDR_PHY_ACBDLR6_RESERVED_31_30_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR6_RESERVED_31_30_SHIFT 30 -#define DDR_PHY_ACBDLR6_RESERVED_31_30_MASK 0xC0000000U +#define DDR_PHY_ACBDLR6_RESERVED_31_30_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR6_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_ACBDLR6_RESERVED_31_30_MASK 0xC0000000U -/*Delay select for the BDL on Address A[3].*/ +/* +* Delay select for the BDL on Address A[3]. +*/ #undef DDR_PHY_ACBDLR6_A03BD_DEFVAL #undef DDR_PHY_ACBDLR6_A03BD_SHIFT #undef DDR_PHY_ACBDLR6_A03BD_MASK -#define DDR_PHY_ACBDLR6_A03BD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR6_A03BD_SHIFT 24 -#define DDR_PHY_ACBDLR6_A03BD_MASK 0x3F000000U +#define DDR_PHY_ACBDLR6_A03BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR6_A03BD_SHIFT 24 +#define DDR_PHY_ACBDLR6_A03BD_MASK 0x3F000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR6_RESERVED_23_22_DEFVAL #undef DDR_PHY_ACBDLR6_RESERVED_23_22_SHIFT #undef DDR_PHY_ACBDLR6_RESERVED_23_22_MASK -#define DDR_PHY_ACBDLR6_RESERVED_23_22_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR6_RESERVED_23_22_SHIFT 22 -#define DDR_PHY_ACBDLR6_RESERVED_23_22_MASK 0x00C00000U +#define DDR_PHY_ACBDLR6_RESERVED_23_22_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR6_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_ACBDLR6_RESERVED_23_22_MASK 0x00C00000U -/*Delay select for the BDL on Address A[2].*/ +/* +* Delay select for the BDL on Address A[2]. +*/ #undef DDR_PHY_ACBDLR6_A02BD_DEFVAL #undef DDR_PHY_ACBDLR6_A02BD_SHIFT #undef DDR_PHY_ACBDLR6_A02BD_MASK -#define DDR_PHY_ACBDLR6_A02BD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR6_A02BD_SHIFT 16 -#define DDR_PHY_ACBDLR6_A02BD_MASK 0x003F0000U +#define DDR_PHY_ACBDLR6_A02BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR6_A02BD_SHIFT 16 +#define DDR_PHY_ACBDLR6_A02BD_MASK 0x003F0000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR6_RESERVED_15_14_DEFVAL #undef DDR_PHY_ACBDLR6_RESERVED_15_14_SHIFT #undef DDR_PHY_ACBDLR6_RESERVED_15_14_MASK -#define DDR_PHY_ACBDLR6_RESERVED_15_14_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR6_RESERVED_15_14_SHIFT 14 -#define DDR_PHY_ACBDLR6_RESERVED_15_14_MASK 0x0000C000U +#define DDR_PHY_ACBDLR6_RESERVED_15_14_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR6_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_ACBDLR6_RESERVED_15_14_MASK 0x0000C000U -/*Delay select for the BDL on Address A[1].*/ +/* +* Delay select for the BDL on Address A[1]. +*/ #undef DDR_PHY_ACBDLR6_A01BD_DEFVAL #undef DDR_PHY_ACBDLR6_A01BD_SHIFT #undef DDR_PHY_ACBDLR6_A01BD_MASK -#define DDR_PHY_ACBDLR6_A01BD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR6_A01BD_SHIFT 8 -#define DDR_PHY_ACBDLR6_A01BD_MASK 0x00003F00U +#define DDR_PHY_ACBDLR6_A01BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR6_A01BD_SHIFT 8 +#define DDR_PHY_ACBDLR6_A01BD_MASK 0x00003F00U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR6_RESERVED_7_6_DEFVAL #undef DDR_PHY_ACBDLR6_RESERVED_7_6_SHIFT #undef DDR_PHY_ACBDLR6_RESERVED_7_6_MASK -#define DDR_PHY_ACBDLR6_RESERVED_7_6_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR6_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_ACBDLR6_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_ACBDLR6_RESERVED_7_6_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR6_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_ACBDLR6_RESERVED_7_6_MASK 0x000000C0U -/*Delay select for the BDL on Address A[0].*/ +/* +* Delay select for the BDL on Address A[0]. +*/ #undef DDR_PHY_ACBDLR6_A00BD_DEFVAL #undef DDR_PHY_ACBDLR6_A00BD_SHIFT #undef DDR_PHY_ACBDLR6_A00BD_MASK -#define DDR_PHY_ACBDLR6_A00BD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR6_A00BD_SHIFT 0 -#define DDR_PHY_ACBDLR6_A00BD_MASK 0x0000003FU +#define DDR_PHY_ACBDLR6_A00BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR6_A00BD_SHIFT 0 +#define DDR_PHY_ACBDLR6_A00BD_MASK 0x0000003FU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR7_RESERVED_31_30_DEFVAL #undef DDR_PHY_ACBDLR7_RESERVED_31_30_SHIFT #undef DDR_PHY_ACBDLR7_RESERVED_31_30_MASK -#define DDR_PHY_ACBDLR7_RESERVED_31_30_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR7_RESERVED_31_30_SHIFT 30 -#define DDR_PHY_ACBDLR7_RESERVED_31_30_MASK 0xC0000000U +#define DDR_PHY_ACBDLR7_RESERVED_31_30_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR7_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_ACBDLR7_RESERVED_31_30_MASK 0xC0000000U -/*Delay select for the BDL on Address A[7].*/ +/* +* Delay select for the BDL on Address A[7]. +*/ #undef DDR_PHY_ACBDLR7_A07BD_DEFVAL #undef DDR_PHY_ACBDLR7_A07BD_SHIFT #undef DDR_PHY_ACBDLR7_A07BD_MASK -#define DDR_PHY_ACBDLR7_A07BD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR7_A07BD_SHIFT 24 -#define DDR_PHY_ACBDLR7_A07BD_MASK 0x3F000000U +#define DDR_PHY_ACBDLR7_A07BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR7_A07BD_SHIFT 24 +#define DDR_PHY_ACBDLR7_A07BD_MASK 0x3F000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR7_RESERVED_23_22_DEFVAL #undef DDR_PHY_ACBDLR7_RESERVED_23_22_SHIFT #undef DDR_PHY_ACBDLR7_RESERVED_23_22_MASK -#define DDR_PHY_ACBDLR7_RESERVED_23_22_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR7_RESERVED_23_22_SHIFT 22 -#define DDR_PHY_ACBDLR7_RESERVED_23_22_MASK 0x00C00000U +#define DDR_PHY_ACBDLR7_RESERVED_23_22_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR7_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_ACBDLR7_RESERVED_23_22_MASK 0x00C00000U -/*Delay select for the BDL on Address A[6].*/ +/* +* Delay select for the BDL on Address A[6]. +*/ #undef DDR_PHY_ACBDLR7_A06BD_DEFVAL #undef DDR_PHY_ACBDLR7_A06BD_SHIFT #undef DDR_PHY_ACBDLR7_A06BD_MASK -#define DDR_PHY_ACBDLR7_A06BD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR7_A06BD_SHIFT 16 -#define DDR_PHY_ACBDLR7_A06BD_MASK 0x003F0000U +#define DDR_PHY_ACBDLR7_A06BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR7_A06BD_SHIFT 16 +#define DDR_PHY_ACBDLR7_A06BD_MASK 0x003F0000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR7_RESERVED_15_14_DEFVAL #undef DDR_PHY_ACBDLR7_RESERVED_15_14_SHIFT #undef DDR_PHY_ACBDLR7_RESERVED_15_14_MASK -#define DDR_PHY_ACBDLR7_RESERVED_15_14_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR7_RESERVED_15_14_SHIFT 14 -#define DDR_PHY_ACBDLR7_RESERVED_15_14_MASK 0x0000C000U +#define DDR_PHY_ACBDLR7_RESERVED_15_14_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR7_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_ACBDLR7_RESERVED_15_14_MASK 0x0000C000U -/*Delay select for the BDL on Address A[5].*/ +/* +* Delay select for the BDL on Address A[5]. +*/ #undef DDR_PHY_ACBDLR7_A05BD_DEFVAL #undef DDR_PHY_ACBDLR7_A05BD_SHIFT #undef DDR_PHY_ACBDLR7_A05BD_MASK -#define DDR_PHY_ACBDLR7_A05BD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR7_A05BD_SHIFT 8 -#define DDR_PHY_ACBDLR7_A05BD_MASK 0x00003F00U +#define DDR_PHY_ACBDLR7_A05BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR7_A05BD_SHIFT 8 +#define DDR_PHY_ACBDLR7_A05BD_MASK 0x00003F00U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR7_RESERVED_7_6_DEFVAL #undef DDR_PHY_ACBDLR7_RESERVED_7_6_SHIFT #undef DDR_PHY_ACBDLR7_RESERVED_7_6_MASK -#define DDR_PHY_ACBDLR7_RESERVED_7_6_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR7_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_ACBDLR7_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_ACBDLR7_RESERVED_7_6_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR7_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_ACBDLR7_RESERVED_7_6_MASK 0x000000C0U -/*Delay select for the BDL on Address A[4].*/ +/* +* Delay select for the BDL on Address A[4]. +*/ #undef DDR_PHY_ACBDLR7_A04BD_DEFVAL #undef DDR_PHY_ACBDLR7_A04BD_SHIFT #undef DDR_PHY_ACBDLR7_A04BD_MASK -#define DDR_PHY_ACBDLR7_A04BD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR7_A04BD_SHIFT 0 -#define DDR_PHY_ACBDLR7_A04BD_MASK 0x0000003FU +#define DDR_PHY_ACBDLR7_A04BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR7_A04BD_SHIFT 0 +#define DDR_PHY_ACBDLR7_A04BD_MASK 0x0000003FU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR8_RESERVED_31_30_DEFVAL #undef DDR_PHY_ACBDLR8_RESERVED_31_30_SHIFT #undef DDR_PHY_ACBDLR8_RESERVED_31_30_MASK -#define DDR_PHY_ACBDLR8_RESERVED_31_30_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR8_RESERVED_31_30_SHIFT 30 -#define DDR_PHY_ACBDLR8_RESERVED_31_30_MASK 0xC0000000U +#define DDR_PHY_ACBDLR8_RESERVED_31_30_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR8_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_ACBDLR8_RESERVED_31_30_MASK 0xC0000000U -/*Delay select for the BDL on Address A[11].*/ +/* +* Delay select for the BDL on Address A[11]. +*/ #undef DDR_PHY_ACBDLR8_A11BD_DEFVAL #undef DDR_PHY_ACBDLR8_A11BD_SHIFT #undef DDR_PHY_ACBDLR8_A11BD_MASK -#define DDR_PHY_ACBDLR8_A11BD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR8_A11BD_SHIFT 24 -#define DDR_PHY_ACBDLR8_A11BD_MASK 0x3F000000U +#define DDR_PHY_ACBDLR8_A11BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR8_A11BD_SHIFT 24 +#define DDR_PHY_ACBDLR8_A11BD_MASK 0x3F000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR8_RESERVED_23_22_DEFVAL #undef DDR_PHY_ACBDLR8_RESERVED_23_22_SHIFT #undef DDR_PHY_ACBDLR8_RESERVED_23_22_MASK -#define DDR_PHY_ACBDLR8_RESERVED_23_22_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR8_RESERVED_23_22_SHIFT 22 -#define DDR_PHY_ACBDLR8_RESERVED_23_22_MASK 0x00C00000U +#define DDR_PHY_ACBDLR8_RESERVED_23_22_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR8_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_ACBDLR8_RESERVED_23_22_MASK 0x00C00000U -/*Delay select for the BDL on Address A[10].*/ +/* +* Delay select for the BDL on Address A[10]. +*/ #undef DDR_PHY_ACBDLR8_A10BD_DEFVAL #undef DDR_PHY_ACBDLR8_A10BD_SHIFT #undef DDR_PHY_ACBDLR8_A10BD_MASK -#define DDR_PHY_ACBDLR8_A10BD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR8_A10BD_SHIFT 16 -#define DDR_PHY_ACBDLR8_A10BD_MASK 0x003F0000U +#define DDR_PHY_ACBDLR8_A10BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR8_A10BD_SHIFT 16 +#define DDR_PHY_ACBDLR8_A10BD_MASK 0x003F0000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR8_RESERVED_15_14_DEFVAL #undef DDR_PHY_ACBDLR8_RESERVED_15_14_SHIFT #undef DDR_PHY_ACBDLR8_RESERVED_15_14_MASK -#define DDR_PHY_ACBDLR8_RESERVED_15_14_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR8_RESERVED_15_14_SHIFT 14 -#define DDR_PHY_ACBDLR8_RESERVED_15_14_MASK 0x0000C000U +#define DDR_PHY_ACBDLR8_RESERVED_15_14_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR8_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_ACBDLR8_RESERVED_15_14_MASK 0x0000C000U -/*Delay select for the BDL on Address A[9].*/ +/* +* Delay select for the BDL on Address A[9]. +*/ #undef DDR_PHY_ACBDLR8_A09BD_DEFVAL #undef DDR_PHY_ACBDLR8_A09BD_SHIFT #undef DDR_PHY_ACBDLR8_A09BD_MASK -#define DDR_PHY_ACBDLR8_A09BD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR8_A09BD_SHIFT 8 -#define DDR_PHY_ACBDLR8_A09BD_MASK 0x00003F00U +#define DDR_PHY_ACBDLR8_A09BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR8_A09BD_SHIFT 8 +#define DDR_PHY_ACBDLR8_A09BD_MASK 0x00003F00U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR8_RESERVED_7_6_DEFVAL #undef DDR_PHY_ACBDLR8_RESERVED_7_6_SHIFT #undef DDR_PHY_ACBDLR8_RESERVED_7_6_MASK -#define DDR_PHY_ACBDLR8_RESERVED_7_6_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR8_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_ACBDLR8_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_ACBDLR8_RESERVED_7_6_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR8_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_ACBDLR8_RESERVED_7_6_MASK 0x000000C0U -/*Delay select for the BDL on Address A[8].*/ +/* +* Delay select for the BDL on Address A[8]. +*/ #undef DDR_PHY_ACBDLR8_A08BD_DEFVAL #undef DDR_PHY_ACBDLR8_A08BD_SHIFT #undef DDR_PHY_ACBDLR8_A08BD_MASK -#define DDR_PHY_ACBDLR8_A08BD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR8_A08BD_SHIFT 0 -#define DDR_PHY_ACBDLR8_A08BD_MASK 0x0000003FU +#define DDR_PHY_ACBDLR8_A08BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR8_A08BD_SHIFT 0 +#define DDR_PHY_ACBDLR8_A08BD_MASK 0x0000003FU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR9_RESERVED_31_30_DEFVAL #undef DDR_PHY_ACBDLR9_RESERVED_31_30_SHIFT #undef DDR_PHY_ACBDLR9_RESERVED_31_30_MASK -#define DDR_PHY_ACBDLR9_RESERVED_31_30_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR9_RESERVED_31_30_SHIFT 30 -#define DDR_PHY_ACBDLR9_RESERVED_31_30_MASK 0xC0000000U +#define DDR_PHY_ACBDLR9_RESERVED_31_30_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR9_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_ACBDLR9_RESERVED_31_30_MASK 0xC0000000U -/*Delay select for the BDL on Address A[15].*/ +/* +* Delay select for the BDL on Address A[15]. +*/ #undef DDR_PHY_ACBDLR9_A15BD_DEFVAL #undef DDR_PHY_ACBDLR9_A15BD_SHIFT #undef DDR_PHY_ACBDLR9_A15BD_MASK -#define DDR_PHY_ACBDLR9_A15BD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR9_A15BD_SHIFT 24 -#define DDR_PHY_ACBDLR9_A15BD_MASK 0x3F000000U +#define DDR_PHY_ACBDLR9_A15BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR9_A15BD_SHIFT 24 +#define DDR_PHY_ACBDLR9_A15BD_MASK 0x3F000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR9_RESERVED_23_22_DEFVAL #undef DDR_PHY_ACBDLR9_RESERVED_23_22_SHIFT #undef DDR_PHY_ACBDLR9_RESERVED_23_22_MASK -#define DDR_PHY_ACBDLR9_RESERVED_23_22_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR9_RESERVED_23_22_SHIFT 22 -#define DDR_PHY_ACBDLR9_RESERVED_23_22_MASK 0x00C00000U +#define DDR_PHY_ACBDLR9_RESERVED_23_22_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR9_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_ACBDLR9_RESERVED_23_22_MASK 0x00C00000U -/*Delay select for the BDL on Address A[14].*/ +/* +* Delay select for the BDL on Address A[14]. +*/ #undef DDR_PHY_ACBDLR9_A14BD_DEFVAL #undef DDR_PHY_ACBDLR9_A14BD_SHIFT #undef DDR_PHY_ACBDLR9_A14BD_MASK -#define DDR_PHY_ACBDLR9_A14BD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR9_A14BD_SHIFT 16 -#define DDR_PHY_ACBDLR9_A14BD_MASK 0x003F0000U +#define DDR_PHY_ACBDLR9_A14BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR9_A14BD_SHIFT 16 +#define DDR_PHY_ACBDLR9_A14BD_MASK 0x003F0000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR9_RESERVED_15_14_DEFVAL #undef DDR_PHY_ACBDLR9_RESERVED_15_14_SHIFT #undef DDR_PHY_ACBDLR9_RESERVED_15_14_MASK -#define DDR_PHY_ACBDLR9_RESERVED_15_14_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR9_RESERVED_15_14_SHIFT 14 -#define DDR_PHY_ACBDLR9_RESERVED_15_14_MASK 0x0000C000U +#define DDR_PHY_ACBDLR9_RESERVED_15_14_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR9_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_ACBDLR9_RESERVED_15_14_MASK 0x0000C000U -/*Delay select for the BDL on Address A[13].*/ +/* +* Delay select for the BDL on Address A[13]. +*/ #undef DDR_PHY_ACBDLR9_A13BD_DEFVAL #undef DDR_PHY_ACBDLR9_A13BD_SHIFT #undef DDR_PHY_ACBDLR9_A13BD_MASK -#define DDR_PHY_ACBDLR9_A13BD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR9_A13BD_SHIFT 8 -#define DDR_PHY_ACBDLR9_A13BD_MASK 0x00003F00U +#define DDR_PHY_ACBDLR9_A13BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR9_A13BD_SHIFT 8 +#define DDR_PHY_ACBDLR9_A13BD_MASK 0x00003F00U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR9_RESERVED_7_6_DEFVAL #undef DDR_PHY_ACBDLR9_RESERVED_7_6_SHIFT #undef DDR_PHY_ACBDLR9_RESERVED_7_6_MASK -#define DDR_PHY_ACBDLR9_RESERVED_7_6_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR9_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_ACBDLR9_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_ACBDLR9_RESERVED_7_6_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR9_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_ACBDLR9_RESERVED_7_6_MASK 0x000000C0U -/*Delay select for the BDL on Address A[12].*/ +/* +* Delay select for the BDL on Address A[12]. +*/ #undef DDR_PHY_ACBDLR9_A12BD_DEFVAL #undef DDR_PHY_ACBDLR9_A12BD_SHIFT #undef DDR_PHY_ACBDLR9_A12BD_MASK -#define DDR_PHY_ACBDLR9_A12BD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR9_A12BD_SHIFT 0 -#define DDR_PHY_ACBDLR9_A12BD_MASK 0x0000003FU +#define DDR_PHY_ACBDLR9_A12BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR9_A12BD_SHIFT 0 +#define DDR_PHY_ACBDLR9_A12BD_MASK 0x0000003FU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ZQCR_RESERVED_31_26_DEFVAL #undef DDR_PHY_ZQCR_RESERVED_31_26_SHIFT #undef DDR_PHY_ZQCR_RESERVED_31_26_MASK -#define DDR_PHY_ZQCR_RESERVED_31_26_DEFVAL 0x008A2858 -#define DDR_PHY_ZQCR_RESERVED_31_26_SHIFT 26 -#define DDR_PHY_ZQCR_RESERVED_31_26_MASK 0xFC000000U +#define DDR_PHY_ZQCR_RESERVED_31_26_DEFVAL 0x008A2858 +#define DDR_PHY_ZQCR_RESERVED_31_26_SHIFT 26 +#define DDR_PHY_ZQCR_RESERVED_31_26_MASK 0xFC000000U -/*ZQ VREF Range*/ +/* +* ZQ VREF Range +*/ #undef DDR_PHY_ZQCR_ZQREFISELRANGE_DEFVAL #undef DDR_PHY_ZQCR_ZQREFISELRANGE_SHIFT #undef DDR_PHY_ZQCR_ZQREFISELRANGE_MASK -#define DDR_PHY_ZQCR_ZQREFISELRANGE_DEFVAL 0x008A2858 -#define DDR_PHY_ZQCR_ZQREFISELRANGE_SHIFT 25 -#define DDR_PHY_ZQCR_ZQREFISELRANGE_MASK 0x02000000U +#define DDR_PHY_ZQCR_ZQREFISELRANGE_DEFVAL 0x008A2858 +#define DDR_PHY_ZQCR_ZQREFISELRANGE_SHIFT 25 +#define DDR_PHY_ZQCR_ZQREFISELRANGE_MASK 0x02000000U -/*Programmable Wait for Frequency B*/ +/* +* Programmable Wait for Frequency B +*/ #undef DDR_PHY_ZQCR_PGWAIT_FRQB_DEFVAL #undef DDR_PHY_ZQCR_PGWAIT_FRQB_SHIFT #undef DDR_PHY_ZQCR_PGWAIT_FRQB_MASK -#define DDR_PHY_ZQCR_PGWAIT_FRQB_DEFVAL 0x008A2858 -#define DDR_PHY_ZQCR_PGWAIT_FRQB_SHIFT 19 -#define DDR_PHY_ZQCR_PGWAIT_FRQB_MASK 0x01F80000U +#define DDR_PHY_ZQCR_PGWAIT_FRQB_DEFVAL 0x008A2858 +#define DDR_PHY_ZQCR_PGWAIT_FRQB_SHIFT 19 +#define DDR_PHY_ZQCR_PGWAIT_FRQB_MASK 0x01F80000U -/*Programmable Wait for Frequency A*/ +/* +* Programmable Wait for Frequency A +*/ #undef DDR_PHY_ZQCR_PGWAIT_FRQA_DEFVAL #undef DDR_PHY_ZQCR_PGWAIT_FRQA_SHIFT #undef DDR_PHY_ZQCR_PGWAIT_FRQA_MASK -#define DDR_PHY_ZQCR_PGWAIT_FRQA_DEFVAL 0x008A2858 -#define DDR_PHY_ZQCR_PGWAIT_FRQA_SHIFT 13 -#define DDR_PHY_ZQCR_PGWAIT_FRQA_MASK 0x0007E000U +#define DDR_PHY_ZQCR_PGWAIT_FRQA_DEFVAL 0x008A2858 +#define DDR_PHY_ZQCR_PGWAIT_FRQA_SHIFT 13 +#define DDR_PHY_ZQCR_PGWAIT_FRQA_MASK 0x0007E000U -/*ZQ VREF Pad Enable*/ +/* +* ZQ VREF Pad Enable +*/ #undef DDR_PHY_ZQCR_ZQREFPEN_DEFVAL #undef DDR_PHY_ZQCR_ZQREFPEN_SHIFT #undef DDR_PHY_ZQCR_ZQREFPEN_MASK -#define DDR_PHY_ZQCR_ZQREFPEN_DEFVAL 0x008A2858 -#define DDR_PHY_ZQCR_ZQREFPEN_SHIFT 12 -#define DDR_PHY_ZQCR_ZQREFPEN_MASK 0x00001000U +#define DDR_PHY_ZQCR_ZQREFPEN_DEFVAL 0x008A2858 +#define DDR_PHY_ZQCR_ZQREFPEN_SHIFT 12 +#define DDR_PHY_ZQCR_ZQREFPEN_MASK 0x00001000U -/*ZQ Internal VREF Enable*/ +/* +* ZQ Internal VREF Enable +*/ #undef DDR_PHY_ZQCR_ZQREFIEN_DEFVAL #undef DDR_PHY_ZQCR_ZQREFIEN_SHIFT #undef DDR_PHY_ZQCR_ZQREFIEN_MASK -#define DDR_PHY_ZQCR_ZQREFIEN_DEFVAL 0x008A2858 -#define DDR_PHY_ZQCR_ZQREFIEN_SHIFT 11 -#define DDR_PHY_ZQCR_ZQREFIEN_MASK 0x00000800U +#define DDR_PHY_ZQCR_ZQREFIEN_DEFVAL 0x008A2858 +#define DDR_PHY_ZQCR_ZQREFIEN_SHIFT 11 +#define DDR_PHY_ZQCR_ZQREFIEN_MASK 0x00000800U -/*Choice of termination mode*/ +/* +* Choice of termination mode +*/ #undef DDR_PHY_ZQCR_ODT_MODE_DEFVAL #undef DDR_PHY_ZQCR_ODT_MODE_SHIFT #undef DDR_PHY_ZQCR_ODT_MODE_MASK -#define DDR_PHY_ZQCR_ODT_MODE_DEFVAL 0x008A2858 -#define DDR_PHY_ZQCR_ODT_MODE_SHIFT 9 -#define DDR_PHY_ZQCR_ODT_MODE_MASK 0x00000600U +#define DDR_PHY_ZQCR_ODT_MODE_DEFVAL 0x008A2858 +#define DDR_PHY_ZQCR_ODT_MODE_SHIFT 9 +#define DDR_PHY_ZQCR_ODT_MODE_MASK 0x00000600U -/*Force ZCAL VT update*/ +/* +* Force ZCAL VT update +*/ #undef DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_DEFVAL #undef DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_SHIFT #undef DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_MASK -#define DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_DEFVAL 0x008A2858 -#define DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_SHIFT 8 -#define DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_MASK 0x00000100U +#define DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_DEFVAL 0x008A2858 +#define DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_SHIFT 8 +#define DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_MASK 0x00000100U -/*IO VT Drift Limit*/ +/* +* IO VT Drift Limit +*/ #undef DDR_PHY_ZQCR_IODLMT_DEFVAL #undef DDR_PHY_ZQCR_IODLMT_SHIFT #undef DDR_PHY_ZQCR_IODLMT_MASK -#define DDR_PHY_ZQCR_IODLMT_DEFVAL 0x008A2858 -#define DDR_PHY_ZQCR_IODLMT_SHIFT 5 -#define DDR_PHY_ZQCR_IODLMT_MASK 0x000000E0U +#define DDR_PHY_ZQCR_IODLMT_DEFVAL 0x008A2858 +#define DDR_PHY_ZQCR_IODLMT_SHIFT 5 +#define DDR_PHY_ZQCR_IODLMT_MASK 0x000000E0U -/*Averaging algorithm enable, if set, enables averaging algorithm*/ +/* +* Averaging algorithm enable, if set, enables averaging algorithm +*/ #undef DDR_PHY_ZQCR_AVGEN_DEFVAL #undef DDR_PHY_ZQCR_AVGEN_SHIFT #undef DDR_PHY_ZQCR_AVGEN_MASK -#define DDR_PHY_ZQCR_AVGEN_DEFVAL 0x008A2858 -#define DDR_PHY_ZQCR_AVGEN_SHIFT 4 -#define DDR_PHY_ZQCR_AVGEN_MASK 0x00000010U +#define DDR_PHY_ZQCR_AVGEN_DEFVAL 0x008A2858 +#define DDR_PHY_ZQCR_AVGEN_SHIFT 4 +#define DDR_PHY_ZQCR_AVGEN_MASK 0x00000010U -/*Maximum number of averaging rounds to be used by averaging algorithm*/ +/* +* Maximum number of averaging rounds to be used by averaging algorithm +*/ #undef DDR_PHY_ZQCR_AVGMAX_DEFVAL #undef DDR_PHY_ZQCR_AVGMAX_SHIFT #undef DDR_PHY_ZQCR_AVGMAX_MASK -#define DDR_PHY_ZQCR_AVGMAX_DEFVAL 0x008A2858 -#define DDR_PHY_ZQCR_AVGMAX_SHIFT 2 -#define DDR_PHY_ZQCR_AVGMAX_MASK 0x0000000CU +#define DDR_PHY_ZQCR_AVGMAX_DEFVAL 0x008A2858 +#define DDR_PHY_ZQCR_AVGMAX_SHIFT 2 +#define DDR_PHY_ZQCR_AVGMAX_MASK 0x0000000CU -/*ZQ Calibration Type*/ +/* +* ZQ Calibration Type +*/ #undef DDR_PHY_ZQCR_ZCALT_DEFVAL #undef DDR_PHY_ZQCR_ZCALT_SHIFT #undef DDR_PHY_ZQCR_ZCALT_MASK -#define DDR_PHY_ZQCR_ZCALT_DEFVAL 0x008A2858 -#define DDR_PHY_ZQCR_ZCALT_SHIFT 1 -#define DDR_PHY_ZQCR_ZCALT_MASK 0x00000002U +#define DDR_PHY_ZQCR_ZCALT_DEFVAL 0x008A2858 +#define DDR_PHY_ZQCR_ZCALT_SHIFT 1 +#define DDR_PHY_ZQCR_ZCALT_MASK 0x00000002U -/*ZQ Power Down*/ +/* +* ZQ Power Down +*/ #undef DDR_PHY_ZQCR_ZQPD_DEFVAL #undef DDR_PHY_ZQCR_ZQPD_SHIFT #undef DDR_PHY_ZQCR_ZQPD_MASK -#define DDR_PHY_ZQCR_ZQPD_DEFVAL 0x008A2858 -#define DDR_PHY_ZQCR_ZQPD_SHIFT 0 -#define DDR_PHY_ZQCR_ZQPD_MASK 0x00000001U +#define DDR_PHY_ZQCR_ZQPD_DEFVAL 0x008A2858 +#define DDR_PHY_ZQCR_ZQPD_SHIFT 0 +#define DDR_PHY_ZQCR_ZQPD_MASK 0x00000001U -/*Pull-down drive strength ZCTRL over-ride enable*/ +/* +* Pull-down drive strength ZCTRL over-ride enable +*/ #undef DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_DEFVAL #undef DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_SHIFT #undef DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_MASK -#define DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_DEFVAL 0x000077BB -#define DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_SHIFT 31 -#define DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_MASK 0x80000000U +#define DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_DEFVAL 0x000077BB +#define DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_SHIFT 31 +#define DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_MASK 0x80000000U -/*Pull-up drive strength ZCTRL over-ride enable*/ +/* +* Pull-up drive strength ZCTRL over-ride enable +*/ #undef DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_DEFVAL #undef DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_SHIFT #undef DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_MASK -#define DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_DEFVAL 0x000077BB -#define DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_SHIFT 30 -#define DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_MASK 0x40000000U +#define DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_DEFVAL 0x000077BB +#define DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_SHIFT 30 +#define DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_MASK 0x40000000U -/*Pull-down termination ZCTRL over-ride enable*/ +/* +* Pull-down termination ZCTRL over-ride enable +*/ #undef DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_DEFVAL #undef DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_SHIFT #undef DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_MASK -#define DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_DEFVAL 0x000077BB -#define DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_SHIFT 29 -#define DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_MASK 0x20000000U +#define DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_DEFVAL 0x000077BB +#define DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_SHIFT 29 +#define DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_MASK 0x20000000U -/*Pull-up termination ZCTRL over-ride enable*/ +/* +* Pull-up termination ZCTRL over-ride enable +*/ #undef DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_DEFVAL #undef DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_SHIFT #undef DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_MASK -#define DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_DEFVAL 0x000077BB -#define DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_SHIFT 28 -#define DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_MASK 0x10000000U +#define DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_DEFVAL 0x000077BB +#define DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_SHIFT 28 +#define DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_MASK 0x10000000U -/*Calibration segment bypass*/ +/* +* Calibration segment bypass +*/ #undef DDR_PHY_ZQ0PR0_ZSEGBYP_DEFVAL #undef DDR_PHY_ZQ0PR0_ZSEGBYP_SHIFT #undef DDR_PHY_ZQ0PR0_ZSEGBYP_MASK -#define DDR_PHY_ZQ0PR0_ZSEGBYP_DEFVAL 0x000077BB -#define DDR_PHY_ZQ0PR0_ZSEGBYP_SHIFT 27 -#define DDR_PHY_ZQ0PR0_ZSEGBYP_MASK 0x08000000U +#define DDR_PHY_ZQ0PR0_ZSEGBYP_DEFVAL 0x000077BB +#define DDR_PHY_ZQ0PR0_ZSEGBYP_SHIFT 27 +#define DDR_PHY_ZQ0PR0_ZSEGBYP_MASK 0x08000000U -/*VREF latch mode controls the mode in which the ZLE pin of the PVREF cell is driven by the PUB*/ +/* +* VREF latch mode controls the mode in which the ZLE pin of the PVREF cell + * is driven by the PUB +*/ #undef DDR_PHY_ZQ0PR0_ZLE_MODE_DEFVAL #undef DDR_PHY_ZQ0PR0_ZLE_MODE_SHIFT #undef DDR_PHY_ZQ0PR0_ZLE_MODE_MASK -#define DDR_PHY_ZQ0PR0_ZLE_MODE_DEFVAL 0x000077BB -#define DDR_PHY_ZQ0PR0_ZLE_MODE_SHIFT 25 -#define DDR_PHY_ZQ0PR0_ZLE_MODE_MASK 0x06000000U +#define DDR_PHY_ZQ0PR0_ZLE_MODE_DEFVAL 0x000077BB +#define DDR_PHY_ZQ0PR0_ZLE_MODE_SHIFT 25 +#define DDR_PHY_ZQ0PR0_ZLE_MODE_MASK 0x06000000U -/*Termination adjustment*/ +/* +* Termination adjustment +*/ #undef DDR_PHY_ZQ0PR0_ODT_ADJUST_DEFVAL #undef DDR_PHY_ZQ0PR0_ODT_ADJUST_SHIFT #undef DDR_PHY_ZQ0PR0_ODT_ADJUST_MASK -#define DDR_PHY_ZQ0PR0_ODT_ADJUST_DEFVAL 0x000077BB -#define DDR_PHY_ZQ0PR0_ODT_ADJUST_SHIFT 22 -#define DDR_PHY_ZQ0PR0_ODT_ADJUST_MASK 0x01C00000U +#define DDR_PHY_ZQ0PR0_ODT_ADJUST_DEFVAL 0x000077BB +#define DDR_PHY_ZQ0PR0_ODT_ADJUST_SHIFT 22 +#define DDR_PHY_ZQ0PR0_ODT_ADJUST_MASK 0x01C00000U -/*Pulldown drive strength adjustment*/ +/* +* Pulldown drive strength adjustment +*/ #undef DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_DEFVAL #undef DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_SHIFT #undef DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_MASK -#define DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_DEFVAL 0x000077BB -#define DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_SHIFT 19 -#define DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_MASK 0x00380000U +#define DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_DEFVAL 0x000077BB +#define DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_SHIFT 19 +#define DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_MASK 0x00380000U -/*Pullup drive strength adjustment*/ +/* +* Pullup drive strength adjustment +*/ #undef DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_DEFVAL #undef DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_SHIFT #undef DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_MASK -#define DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_DEFVAL 0x000077BB -#define DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_SHIFT 16 -#define DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_MASK 0x00070000U +#define DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_DEFVAL 0x000077BB +#define DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_SHIFT 16 +#define DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_MASK 0x00070000U -/*DRAM Impedance Divide Ratio*/ +/* +* DRAM Impedance Divide Ratio +*/ #undef DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_DEFVAL #undef DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_SHIFT #undef DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_MASK -#define DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_DEFVAL 0x000077BB -#define DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_SHIFT 12 -#define DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_MASK 0x0000F000U +#define DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_DEFVAL 0x000077BB +#define DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_SHIFT 12 +#define DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_MASK 0x0000F000U -/*HOST Impedance Divide Ratio*/ +/* +* HOST Impedance Divide Ratio +*/ #undef DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_DEFVAL #undef DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_SHIFT #undef DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_MASK -#define DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_DEFVAL 0x000077BB -#define DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_SHIFT 8 -#define DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_MASK 0x00000F00U +#define DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_DEFVAL 0x000077BB +#define DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_SHIFT 8 +#define DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_MASK 0x00000F00U -/*Impedance Divide Ratio (pulldown drive calibration during asymmetric drive strength calibration)*/ +/* +* Impedance Divide Ratio (pulldown drive calibration during asymmetric dri + * ve strength calibration) +*/ #undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_DEFVAL #undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_SHIFT #undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_MASK -#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_DEFVAL 0x000077BB -#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_SHIFT 4 -#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_MASK 0x000000F0U +#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_DEFVAL 0x000077BB +#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_SHIFT 4 +#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_MASK 0x000000F0U -/*Impedance Divide Ratio (pullup drive calibration during asymmetric drive strength calibration)*/ +/* +* Impedance Divide Ratio (pullup drive calibration during asymmetric drive + * strength calibration) +*/ #undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_DEFVAL #undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_SHIFT #undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_MASK -#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_DEFVAL 0x000077BB -#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_SHIFT 0 -#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_MASK 0x0000000FU +#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_DEFVAL 0x000077BB +#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_SHIFT 0 +#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_MASK 0x0000000FU -/*Reserved. Return zeros on reads.*/ +/* +* Reserved. Return zeros on reads. +*/ #undef DDR_PHY_ZQ0OR0_RESERVED_31_26_DEFVAL #undef DDR_PHY_ZQ0OR0_RESERVED_31_26_SHIFT #undef DDR_PHY_ZQ0OR0_RESERVED_31_26_MASK -#define DDR_PHY_ZQ0OR0_RESERVED_31_26_DEFVAL 0x00000000 -#define DDR_PHY_ZQ0OR0_RESERVED_31_26_SHIFT 26 -#define DDR_PHY_ZQ0OR0_RESERVED_31_26_MASK 0xFC000000U +#define DDR_PHY_ZQ0OR0_RESERVED_31_26_DEFVAL 0x00000000 +#define DDR_PHY_ZQ0OR0_RESERVED_31_26_SHIFT 26 +#define DDR_PHY_ZQ0OR0_RESERVED_31_26_MASK 0xFC000000U -/*Override value for the pull-up output impedance*/ +/* +* Override value for the pull-up output impedance +*/ #undef DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_DEFVAL #undef DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_SHIFT #undef DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_MASK -#define DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_DEFVAL 0x00000000 -#define DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_SHIFT 16 -#define DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_MASK 0x03FF0000U +#define DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_DEFVAL 0x00000000 +#define DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_SHIFT 16 +#define DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_MASK 0x03FF0000U -/*Reserved. Return zeros on reads.*/ +/* +* Reserved. Return zeros on reads. +*/ #undef DDR_PHY_ZQ0OR0_RESERVED_15_10_DEFVAL #undef DDR_PHY_ZQ0OR0_RESERVED_15_10_SHIFT #undef DDR_PHY_ZQ0OR0_RESERVED_15_10_MASK -#define DDR_PHY_ZQ0OR0_RESERVED_15_10_DEFVAL 0x00000000 -#define DDR_PHY_ZQ0OR0_RESERVED_15_10_SHIFT 10 -#define DDR_PHY_ZQ0OR0_RESERVED_15_10_MASK 0x0000FC00U +#define DDR_PHY_ZQ0OR0_RESERVED_15_10_DEFVAL 0x00000000 +#define DDR_PHY_ZQ0OR0_RESERVED_15_10_SHIFT 10 +#define DDR_PHY_ZQ0OR0_RESERVED_15_10_MASK 0x0000FC00U -/*Override value for the pull-down output impedance*/ +/* +* Override value for the pull-down output impedance +*/ #undef DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_DEFVAL #undef DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_SHIFT #undef DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_MASK -#define DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_DEFVAL 0x00000000 -#define DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_SHIFT 0 -#define DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_MASK 0x000003FFU +#define DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_DEFVAL 0x00000000 +#define DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_SHIFT 0 +#define DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_MASK 0x000003FFU -/*Reserved. Return zeros on reads.*/ +/* +* Reserved. Return zeros on reads. +*/ #undef DDR_PHY_ZQ0OR1_RESERVED_31_26_DEFVAL #undef DDR_PHY_ZQ0OR1_RESERVED_31_26_SHIFT #undef DDR_PHY_ZQ0OR1_RESERVED_31_26_MASK -#define DDR_PHY_ZQ0OR1_RESERVED_31_26_DEFVAL 0x00000000 -#define DDR_PHY_ZQ0OR1_RESERVED_31_26_SHIFT 26 -#define DDR_PHY_ZQ0OR1_RESERVED_31_26_MASK 0xFC000000U +#define DDR_PHY_ZQ0OR1_RESERVED_31_26_DEFVAL 0x00000000 +#define DDR_PHY_ZQ0OR1_RESERVED_31_26_SHIFT 26 +#define DDR_PHY_ZQ0OR1_RESERVED_31_26_MASK 0xFC000000U -/*Override value for the pull-up termination*/ +/* +* Override value for the pull-up termination +*/ #undef DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_DEFVAL #undef DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_SHIFT #undef DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_MASK -#define DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_DEFVAL 0x00000000 -#define DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_SHIFT 16 -#define DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_MASK 0x03FF0000U +#define DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_DEFVAL 0x00000000 +#define DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_SHIFT 16 +#define DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_MASK 0x03FF0000U -/*Reserved. Return zeros on reads.*/ +/* +* Reserved. Return zeros on reads. +*/ #undef DDR_PHY_ZQ0OR1_RESERVED_15_10_DEFVAL #undef DDR_PHY_ZQ0OR1_RESERVED_15_10_SHIFT #undef DDR_PHY_ZQ0OR1_RESERVED_15_10_MASK -#define DDR_PHY_ZQ0OR1_RESERVED_15_10_DEFVAL 0x00000000 -#define DDR_PHY_ZQ0OR1_RESERVED_15_10_SHIFT 10 -#define DDR_PHY_ZQ0OR1_RESERVED_15_10_MASK 0x0000FC00U +#define DDR_PHY_ZQ0OR1_RESERVED_15_10_DEFVAL 0x00000000 +#define DDR_PHY_ZQ0OR1_RESERVED_15_10_SHIFT 10 +#define DDR_PHY_ZQ0OR1_RESERVED_15_10_MASK 0x0000FC00U -/*Override value for the pull-down termination*/ +/* +* Override value for the pull-down termination +*/ #undef DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_DEFVAL #undef DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_SHIFT #undef DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_MASK -#define DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_DEFVAL 0x00000000 -#define DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_SHIFT 0 -#define DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_MASK 0x000003FFU +#define DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_DEFVAL 0x00000000 +#define DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_SHIFT 0 +#define DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_MASK 0x000003FFU -/*Pull-down drive strength ZCTRL over-ride enable*/ +/* +* Pull-down drive strength ZCTRL over-ride enable +*/ #undef DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_DEFVAL #undef DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_SHIFT #undef DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_MASK -#define DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_DEFVAL 0x000077BB -#define DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_SHIFT 31 -#define DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_MASK 0x80000000U +#define DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_DEFVAL 0x000077BB +#define DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_SHIFT 31 +#define DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_MASK 0x80000000U -/*Pull-up drive strength ZCTRL over-ride enable*/ +/* +* Pull-up drive strength ZCTRL over-ride enable +*/ #undef DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_DEFVAL #undef DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_SHIFT #undef DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_MASK -#define DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_DEFVAL 0x000077BB -#define DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_SHIFT 30 -#define DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_MASK 0x40000000U +#define DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_DEFVAL 0x000077BB +#define DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_SHIFT 30 +#define DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_MASK 0x40000000U -/*Pull-down termination ZCTRL over-ride enable*/ +/* +* Pull-down termination ZCTRL over-ride enable +*/ #undef DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_DEFVAL #undef DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_SHIFT #undef DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_MASK -#define DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_DEFVAL 0x000077BB -#define DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_SHIFT 29 -#define DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_MASK 0x20000000U +#define DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_DEFVAL 0x000077BB +#define DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_SHIFT 29 +#define DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_MASK 0x20000000U -/*Pull-up termination ZCTRL over-ride enable*/ +/* +* Pull-up termination ZCTRL over-ride enable +*/ #undef DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_DEFVAL #undef DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_SHIFT #undef DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_MASK -#define DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_DEFVAL 0x000077BB -#define DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_SHIFT 28 -#define DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_MASK 0x10000000U +#define DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_DEFVAL 0x000077BB +#define DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_SHIFT 28 +#define DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_MASK 0x10000000U -/*Calibration segment bypass*/ +/* +* Calibration segment bypass +*/ #undef DDR_PHY_ZQ1PR0_ZSEGBYP_DEFVAL #undef DDR_PHY_ZQ1PR0_ZSEGBYP_SHIFT #undef DDR_PHY_ZQ1PR0_ZSEGBYP_MASK -#define DDR_PHY_ZQ1PR0_ZSEGBYP_DEFVAL 0x000077BB -#define DDR_PHY_ZQ1PR0_ZSEGBYP_SHIFT 27 -#define DDR_PHY_ZQ1PR0_ZSEGBYP_MASK 0x08000000U +#define DDR_PHY_ZQ1PR0_ZSEGBYP_DEFVAL 0x000077BB +#define DDR_PHY_ZQ1PR0_ZSEGBYP_SHIFT 27 +#define DDR_PHY_ZQ1PR0_ZSEGBYP_MASK 0x08000000U -/*VREF latch mode controls the mode in which the ZLE pin of the PVREF cell is driven by the PUB*/ +/* +* VREF latch mode controls the mode in which the ZLE pin of the PVREF cell + * is driven by the PUB +*/ #undef DDR_PHY_ZQ1PR0_ZLE_MODE_DEFVAL #undef DDR_PHY_ZQ1PR0_ZLE_MODE_SHIFT #undef DDR_PHY_ZQ1PR0_ZLE_MODE_MASK -#define DDR_PHY_ZQ1PR0_ZLE_MODE_DEFVAL 0x000077BB -#define DDR_PHY_ZQ1PR0_ZLE_MODE_SHIFT 25 -#define DDR_PHY_ZQ1PR0_ZLE_MODE_MASK 0x06000000U +#define DDR_PHY_ZQ1PR0_ZLE_MODE_DEFVAL 0x000077BB +#define DDR_PHY_ZQ1PR0_ZLE_MODE_SHIFT 25 +#define DDR_PHY_ZQ1PR0_ZLE_MODE_MASK 0x06000000U -/*Termination adjustment*/ +/* +* Termination adjustment +*/ #undef DDR_PHY_ZQ1PR0_ODT_ADJUST_DEFVAL #undef DDR_PHY_ZQ1PR0_ODT_ADJUST_SHIFT #undef DDR_PHY_ZQ1PR0_ODT_ADJUST_MASK -#define DDR_PHY_ZQ1PR0_ODT_ADJUST_DEFVAL 0x000077BB -#define DDR_PHY_ZQ1PR0_ODT_ADJUST_SHIFT 22 -#define DDR_PHY_ZQ1PR0_ODT_ADJUST_MASK 0x01C00000U +#define DDR_PHY_ZQ1PR0_ODT_ADJUST_DEFVAL 0x000077BB +#define DDR_PHY_ZQ1PR0_ODT_ADJUST_SHIFT 22 +#define DDR_PHY_ZQ1PR0_ODT_ADJUST_MASK 0x01C00000U -/*Pulldown drive strength adjustment*/ +/* +* Pulldown drive strength adjustment +*/ #undef DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_DEFVAL #undef DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_SHIFT #undef DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_MASK -#define DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_DEFVAL 0x000077BB -#define DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_SHIFT 19 -#define DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_MASK 0x00380000U +#define DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_DEFVAL 0x000077BB +#define DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_SHIFT 19 +#define DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_MASK 0x00380000U -/*Pullup drive strength adjustment*/ +/* +* Pullup drive strength adjustment +*/ #undef DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_DEFVAL #undef DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_SHIFT #undef DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_MASK -#define DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_DEFVAL 0x000077BB -#define DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_SHIFT 16 -#define DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_MASK 0x00070000U +#define DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_DEFVAL 0x000077BB +#define DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_SHIFT 16 +#define DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_MASK 0x00070000U -/*DRAM Impedance Divide Ratio*/ +/* +* DRAM Impedance Divide Ratio +*/ #undef DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_DEFVAL #undef DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_SHIFT #undef DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_MASK -#define DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_DEFVAL 0x000077BB -#define DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_SHIFT 12 -#define DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_MASK 0x0000F000U +#define DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_DEFVAL 0x000077BB +#define DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_SHIFT 12 +#define DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_MASK 0x0000F000U -/*HOST Impedance Divide Ratio*/ +/* +* HOST Impedance Divide Ratio +*/ #undef DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_DEFVAL #undef DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_SHIFT #undef DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_MASK -#define DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_DEFVAL 0x000077BB -#define DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_SHIFT 8 -#define DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_MASK 0x00000F00U +#define DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_DEFVAL 0x000077BB +#define DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_SHIFT 8 +#define DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_MASK 0x00000F00U -/*Impedance Divide Ratio (pulldown drive calibration during asymmetric drive strength calibration)*/ +/* +* Impedance Divide Ratio (pulldown drive calibration during asymmetric dri + * ve strength calibration) +*/ #undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_DEFVAL #undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_SHIFT #undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_MASK -#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_DEFVAL 0x000077BB -#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_SHIFT 4 -#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_MASK 0x000000F0U +#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_DEFVAL 0x000077BB +#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_SHIFT 4 +#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_MASK 0x000000F0U -/*Impedance Divide Ratio (pullup drive calibration during asymmetric drive strength calibration)*/ +/* +* Impedance Divide Ratio (pullup drive calibration during asymmetric drive + * strength calibration) +*/ #undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_DEFVAL #undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_SHIFT #undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_MASK -#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_DEFVAL 0x000077BB -#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_SHIFT 0 -#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_MASK 0x0000000FU +#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_DEFVAL 0x000077BB +#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_SHIFT 0 +#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_MASK 0x0000000FU -/*Calibration Bypass*/ +/* +* Calibration Bypass +*/ #undef DDR_PHY_DX0GCR0_CALBYP_DEFVAL #undef DDR_PHY_DX0GCR0_CALBYP_SHIFT #undef DDR_PHY_DX0GCR0_CALBYP_MASK -#define DDR_PHY_DX0GCR0_CALBYP_DEFVAL 0x40200204 -#define DDR_PHY_DX0GCR0_CALBYP_SHIFT 31 -#define DDR_PHY_DX0GCR0_CALBYP_MASK 0x80000000U +#define DDR_PHY_DX0GCR0_CALBYP_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_CALBYP_SHIFT 31 +#define DDR_PHY_DX0GCR0_CALBYP_MASK 0x80000000U -/*Master Delay Line Enable*/ +/* +* Master Delay Line Enable +*/ #undef DDR_PHY_DX0GCR0_MDLEN_DEFVAL #undef DDR_PHY_DX0GCR0_MDLEN_SHIFT #undef DDR_PHY_DX0GCR0_MDLEN_MASK -#define DDR_PHY_DX0GCR0_MDLEN_DEFVAL 0x40200204 -#define DDR_PHY_DX0GCR0_MDLEN_SHIFT 30 -#define DDR_PHY_DX0GCR0_MDLEN_MASK 0x40000000U +#define DDR_PHY_DX0GCR0_MDLEN_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_MDLEN_SHIFT 30 +#define DDR_PHY_DX0GCR0_MDLEN_MASK 0x40000000U -/*Configurable ODT(TE) Phase Shift*/ +/* +* Configurable ODT(TE) Phase Shift +*/ #undef DDR_PHY_DX0GCR0_CODTSHFT_DEFVAL #undef DDR_PHY_DX0GCR0_CODTSHFT_SHIFT #undef DDR_PHY_DX0GCR0_CODTSHFT_MASK -#define DDR_PHY_DX0GCR0_CODTSHFT_DEFVAL 0x40200204 -#define DDR_PHY_DX0GCR0_CODTSHFT_SHIFT 28 -#define DDR_PHY_DX0GCR0_CODTSHFT_MASK 0x30000000U +#define DDR_PHY_DX0GCR0_CODTSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_CODTSHFT_SHIFT 28 +#define DDR_PHY_DX0GCR0_CODTSHFT_MASK 0x30000000U -/*DQS Duty Cycle Correction*/ +/* +* DQS Duty Cycle Correction +*/ #undef DDR_PHY_DX0GCR0_DQSDCC_DEFVAL #undef DDR_PHY_DX0GCR0_DQSDCC_SHIFT #undef DDR_PHY_DX0GCR0_DQSDCC_MASK -#define DDR_PHY_DX0GCR0_DQSDCC_DEFVAL 0x40200204 -#define DDR_PHY_DX0GCR0_DQSDCC_SHIFT 24 -#define DDR_PHY_DX0GCR0_DQSDCC_MASK 0x0F000000U +#define DDR_PHY_DX0GCR0_DQSDCC_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_DQSDCC_SHIFT 24 +#define DDR_PHY_DX0GCR0_DQSDCC_MASK 0x0F000000U -/*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/ +/* +* Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY +*/ #undef DDR_PHY_DX0GCR0_RDDLY_DEFVAL #undef DDR_PHY_DX0GCR0_RDDLY_SHIFT #undef DDR_PHY_DX0GCR0_RDDLY_MASK -#define DDR_PHY_DX0GCR0_RDDLY_DEFVAL 0x40200204 -#define DDR_PHY_DX0GCR0_RDDLY_SHIFT 20 -#define DDR_PHY_DX0GCR0_RDDLY_MASK 0x00F00000U +#define DDR_PHY_DX0GCR0_RDDLY_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_RDDLY_SHIFT 20 +#define DDR_PHY_DX0GCR0_RDDLY_MASK 0x00F00000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX0GCR0_RESERVED_19_14_DEFVAL #undef DDR_PHY_DX0GCR0_RESERVED_19_14_SHIFT #undef DDR_PHY_DX0GCR0_RESERVED_19_14_MASK -#define DDR_PHY_DX0GCR0_RESERVED_19_14_DEFVAL 0x40200204 -#define DDR_PHY_DX0GCR0_RESERVED_19_14_SHIFT 14 -#define DDR_PHY_DX0GCR0_RESERVED_19_14_MASK 0x000FC000U +#define DDR_PHY_DX0GCR0_RESERVED_19_14_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_RESERVED_19_14_SHIFT 14 +#define DDR_PHY_DX0GCR0_RESERVED_19_14_MASK 0x000FC000U -/*DQSNSE Power Down Receiver*/ +/* +* DQSNSE Power Down Receiver +*/ #undef DDR_PHY_DX0GCR0_DQSNSEPDR_DEFVAL #undef DDR_PHY_DX0GCR0_DQSNSEPDR_SHIFT #undef DDR_PHY_DX0GCR0_DQSNSEPDR_MASK -#define DDR_PHY_DX0GCR0_DQSNSEPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX0GCR0_DQSNSEPDR_SHIFT 13 -#define DDR_PHY_DX0GCR0_DQSNSEPDR_MASK 0x00002000U +#define DDR_PHY_DX0GCR0_DQSNSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_DQSNSEPDR_SHIFT 13 +#define DDR_PHY_DX0GCR0_DQSNSEPDR_MASK 0x00002000U -/*DQSSE Power Down Receiver*/ +/* +* DQSSE Power Down Receiver +*/ #undef DDR_PHY_DX0GCR0_DQSSEPDR_DEFVAL #undef DDR_PHY_DX0GCR0_DQSSEPDR_SHIFT #undef DDR_PHY_DX0GCR0_DQSSEPDR_MASK -#define DDR_PHY_DX0GCR0_DQSSEPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX0GCR0_DQSSEPDR_SHIFT 12 -#define DDR_PHY_DX0GCR0_DQSSEPDR_MASK 0x00001000U +#define DDR_PHY_DX0GCR0_DQSSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_DQSSEPDR_SHIFT 12 +#define DDR_PHY_DX0GCR0_DQSSEPDR_MASK 0x00001000U -/*RTT On Additive Latency*/ +/* +* RTT On Additive Latency +*/ #undef DDR_PHY_DX0GCR0_RTTOAL_DEFVAL #undef DDR_PHY_DX0GCR0_RTTOAL_SHIFT #undef DDR_PHY_DX0GCR0_RTTOAL_MASK -#define DDR_PHY_DX0GCR0_RTTOAL_DEFVAL 0x40200204 -#define DDR_PHY_DX0GCR0_RTTOAL_SHIFT 11 -#define DDR_PHY_DX0GCR0_RTTOAL_MASK 0x00000800U +#define DDR_PHY_DX0GCR0_RTTOAL_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_RTTOAL_SHIFT 11 +#define DDR_PHY_DX0GCR0_RTTOAL_MASK 0x00000800U -/*RTT Output Hold*/ +/* +* RTT Output Hold +*/ #undef DDR_PHY_DX0GCR0_RTTOH_DEFVAL #undef DDR_PHY_DX0GCR0_RTTOH_SHIFT #undef DDR_PHY_DX0GCR0_RTTOH_MASK -#define DDR_PHY_DX0GCR0_RTTOH_DEFVAL 0x40200204 -#define DDR_PHY_DX0GCR0_RTTOH_SHIFT 9 -#define DDR_PHY_DX0GCR0_RTTOH_MASK 0x00000600U +#define DDR_PHY_DX0GCR0_RTTOH_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_RTTOH_SHIFT 9 +#define DDR_PHY_DX0GCR0_RTTOH_MASK 0x00000600U -/*Configurable PDR Phase Shift*/ +/* +* Configurable PDR Phase Shift +*/ #undef DDR_PHY_DX0GCR0_CPDRSHFT_DEFVAL #undef DDR_PHY_DX0GCR0_CPDRSHFT_SHIFT #undef DDR_PHY_DX0GCR0_CPDRSHFT_MASK -#define DDR_PHY_DX0GCR0_CPDRSHFT_DEFVAL 0x40200204 -#define DDR_PHY_DX0GCR0_CPDRSHFT_SHIFT 7 -#define DDR_PHY_DX0GCR0_CPDRSHFT_MASK 0x00000180U +#define DDR_PHY_DX0GCR0_CPDRSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_CPDRSHFT_SHIFT 7 +#define DDR_PHY_DX0GCR0_CPDRSHFT_MASK 0x00000180U -/*DQSR Power Down*/ +/* +* DQSR Power Down +*/ #undef DDR_PHY_DX0GCR0_DQSRPD_DEFVAL #undef DDR_PHY_DX0GCR0_DQSRPD_SHIFT #undef DDR_PHY_DX0GCR0_DQSRPD_MASK -#define DDR_PHY_DX0GCR0_DQSRPD_DEFVAL 0x40200204 -#define DDR_PHY_DX0GCR0_DQSRPD_SHIFT 6 -#define DDR_PHY_DX0GCR0_DQSRPD_MASK 0x00000040U +#define DDR_PHY_DX0GCR0_DQSRPD_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_DQSRPD_SHIFT 6 +#define DDR_PHY_DX0GCR0_DQSRPD_MASK 0x00000040U -/*DQSG Power Down Receiver*/ +/* +* DQSG Power Down Receiver +*/ #undef DDR_PHY_DX0GCR0_DQSGPDR_DEFVAL #undef DDR_PHY_DX0GCR0_DQSGPDR_SHIFT #undef DDR_PHY_DX0GCR0_DQSGPDR_MASK -#define DDR_PHY_DX0GCR0_DQSGPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX0GCR0_DQSGPDR_SHIFT 5 -#define DDR_PHY_DX0GCR0_DQSGPDR_MASK 0x00000020U +#define DDR_PHY_DX0GCR0_DQSGPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_DQSGPDR_SHIFT 5 +#define DDR_PHY_DX0GCR0_DQSGPDR_MASK 0x00000020U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX0GCR0_RESERVED_4_DEFVAL #undef DDR_PHY_DX0GCR0_RESERVED_4_SHIFT #undef DDR_PHY_DX0GCR0_RESERVED_4_MASK -#define DDR_PHY_DX0GCR0_RESERVED_4_DEFVAL 0x40200204 -#define DDR_PHY_DX0GCR0_RESERVED_4_SHIFT 4 -#define DDR_PHY_DX0GCR0_RESERVED_4_MASK 0x00000010U +#define DDR_PHY_DX0GCR0_RESERVED_4_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_RESERVED_4_SHIFT 4 +#define DDR_PHY_DX0GCR0_RESERVED_4_MASK 0x00000010U -/*DQSG On-Die Termination*/ +/* +* DQSG On-Die Termination +*/ #undef DDR_PHY_DX0GCR0_DQSGODT_DEFVAL #undef DDR_PHY_DX0GCR0_DQSGODT_SHIFT #undef DDR_PHY_DX0GCR0_DQSGODT_MASK -#define DDR_PHY_DX0GCR0_DQSGODT_DEFVAL 0x40200204 -#define DDR_PHY_DX0GCR0_DQSGODT_SHIFT 3 -#define DDR_PHY_DX0GCR0_DQSGODT_MASK 0x00000008U +#define DDR_PHY_DX0GCR0_DQSGODT_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_DQSGODT_SHIFT 3 +#define DDR_PHY_DX0GCR0_DQSGODT_MASK 0x00000008U -/*DQSG Output Enable*/ +/* +* DQSG Output Enable +*/ #undef DDR_PHY_DX0GCR0_DQSGOE_DEFVAL #undef DDR_PHY_DX0GCR0_DQSGOE_SHIFT #undef DDR_PHY_DX0GCR0_DQSGOE_MASK -#define DDR_PHY_DX0GCR0_DQSGOE_DEFVAL 0x40200204 -#define DDR_PHY_DX0GCR0_DQSGOE_SHIFT 2 -#define DDR_PHY_DX0GCR0_DQSGOE_MASK 0x00000004U +#define DDR_PHY_DX0GCR0_DQSGOE_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_DQSGOE_SHIFT 2 +#define DDR_PHY_DX0GCR0_DQSGOE_MASK 0x00000004U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX0GCR0_RESERVED_1_0_DEFVAL #undef DDR_PHY_DX0GCR0_RESERVED_1_0_SHIFT #undef DDR_PHY_DX0GCR0_RESERVED_1_0_MASK -#define DDR_PHY_DX0GCR0_RESERVED_1_0_DEFVAL 0x40200204 -#define DDR_PHY_DX0GCR0_RESERVED_1_0_SHIFT 0 -#define DDR_PHY_DX0GCR0_RESERVED_1_0_MASK 0x00000003U +#define DDR_PHY_DX0GCR0_RESERVED_1_0_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_RESERVED_1_0_SHIFT 0 +#define DDR_PHY_DX0GCR0_RESERVED_1_0_MASK 0x00000003U -/*Byte lane VREF IOM (Used only by D4MU IOs)*/ +/* +* Byte lane VREF IOM (Used only by D4MU IOs) +*/ #undef DDR_PHY_DX0GCR4_RESERVED_31_29_DEFVAL #undef DDR_PHY_DX0GCR4_RESERVED_31_29_SHIFT #undef DDR_PHY_DX0GCR4_RESERVED_31_29_MASK -#define DDR_PHY_DX0GCR4_RESERVED_31_29_DEFVAL 0x0E00003C -#define DDR_PHY_DX0GCR4_RESERVED_31_29_SHIFT 29 -#define DDR_PHY_DX0GCR4_RESERVED_31_29_MASK 0xE0000000U +#define DDR_PHY_DX0GCR4_RESERVED_31_29_DEFVAL 0x0E00003C +#define DDR_PHY_DX0GCR4_RESERVED_31_29_SHIFT 29 +#define DDR_PHY_DX0GCR4_RESERVED_31_29_MASK 0xE0000000U -/*Byte Lane VREF Pad Enable*/ +/* +* Byte Lane VREF Pad Enable +*/ #undef DDR_PHY_DX0GCR4_DXREFPEN_DEFVAL #undef DDR_PHY_DX0GCR4_DXREFPEN_SHIFT #undef DDR_PHY_DX0GCR4_DXREFPEN_MASK -#define DDR_PHY_DX0GCR4_DXREFPEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX0GCR4_DXREFPEN_SHIFT 28 -#define DDR_PHY_DX0GCR4_DXREFPEN_MASK 0x10000000U +#define DDR_PHY_DX0GCR4_DXREFPEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX0GCR4_DXREFPEN_SHIFT 28 +#define DDR_PHY_DX0GCR4_DXREFPEN_MASK 0x10000000U -/*Byte Lane Internal VREF Enable*/ +/* +* Byte Lane Internal VREF Enable +*/ #undef DDR_PHY_DX0GCR4_DXREFEEN_DEFVAL #undef DDR_PHY_DX0GCR4_DXREFEEN_SHIFT #undef DDR_PHY_DX0GCR4_DXREFEEN_MASK -#define DDR_PHY_DX0GCR4_DXREFEEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX0GCR4_DXREFEEN_SHIFT 26 -#define DDR_PHY_DX0GCR4_DXREFEEN_MASK 0x0C000000U +#define DDR_PHY_DX0GCR4_DXREFEEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX0GCR4_DXREFEEN_SHIFT 26 +#define DDR_PHY_DX0GCR4_DXREFEEN_MASK 0x0C000000U -/*Byte Lane Single-End VREF Enable*/ +/* +* Byte Lane Single-End VREF Enable +*/ #undef DDR_PHY_DX0GCR4_DXREFSEN_DEFVAL #undef DDR_PHY_DX0GCR4_DXREFSEN_SHIFT #undef DDR_PHY_DX0GCR4_DXREFSEN_MASK -#define DDR_PHY_DX0GCR4_DXREFSEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX0GCR4_DXREFSEN_SHIFT 25 -#define DDR_PHY_DX0GCR4_DXREFSEN_MASK 0x02000000U +#define DDR_PHY_DX0GCR4_DXREFSEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX0GCR4_DXREFSEN_SHIFT 25 +#define DDR_PHY_DX0GCR4_DXREFSEN_MASK 0x02000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX0GCR4_RESERVED_24_DEFVAL #undef DDR_PHY_DX0GCR4_RESERVED_24_SHIFT #undef DDR_PHY_DX0GCR4_RESERVED_24_MASK -#define DDR_PHY_DX0GCR4_RESERVED_24_DEFVAL 0x0E00003C -#define DDR_PHY_DX0GCR4_RESERVED_24_SHIFT 24 -#define DDR_PHY_DX0GCR4_RESERVED_24_MASK 0x01000000U +#define DDR_PHY_DX0GCR4_RESERVED_24_DEFVAL 0x0E00003C +#define DDR_PHY_DX0GCR4_RESERVED_24_SHIFT 24 +#define DDR_PHY_DX0GCR4_RESERVED_24_MASK 0x01000000U -/*External VREF generator REFSEL range select*/ +/* +* External VREF generator REFSEL range select +*/ #undef DDR_PHY_DX0GCR4_DXREFESELRANGE_DEFVAL #undef DDR_PHY_DX0GCR4_DXREFESELRANGE_SHIFT #undef DDR_PHY_DX0GCR4_DXREFESELRANGE_MASK -#define DDR_PHY_DX0GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C -#define DDR_PHY_DX0GCR4_DXREFESELRANGE_SHIFT 23 -#define DDR_PHY_DX0GCR4_DXREFESELRANGE_MASK 0x00800000U +#define DDR_PHY_DX0GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX0GCR4_DXREFESELRANGE_SHIFT 23 +#define DDR_PHY_DX0GCR4_DXREFESELRANGE_MASK 0x00800000U -/*Byte Lane External VREF Select*/ +/* +* Byte Lane External VREF Select +*/ #undef DDR_PHY_DX0GCR4_DXREFESEL_DEFVAL #undef DDR_PHY_DX0GCR4_DXREFESEL_SHIFT #undef DDR_PHY_DX0GCR4_DXREFESEL_MASK -#define DDR_PHY_DX0GCR4_DXREFESEL_DEFVAL 0x0E00003C -#define DDR_PHY_DX0GCR4_DXREFESEL_SHIFT 16 -#define DDR_PHY_DX0GCR4_DXREFESEL_MASK 0x007F0000U +#define DDR_PHY_DX0GCR4_DXREFESEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX0GCR4_DXREFESEL_SHIFT 16 +#define DDR_PHY_DX0GCR4_DXREFESEL_MASK 0x007F0000U -/*Single ended VREF generator REFSEL range select*/ +/* +* Single ended VREF generator REFSEL range select +*/ #undef DDR_PHY_DX0GCR4_DXREFSSELRANGE_DEFVAL #undef DDR_PHY_DX0GCR4_DXREFSSELRANGE_SHIFT #undef DDR_PHY_DX0GCR4_DXREFSSELRANGE_MASK -#define DDR_PHY_DX0GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C -#define DDR_PHY_DX0GCR4_DXREFSSELRANGE_SHIFT 15 -#define DDR_PHY_DX0GCR4_DXREFSSELRANGE_MASK 0x00008000U +#define DDR_PHY_DX0GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX0GCR4_DXREFSSELRANGE_SHIFT 15 +#define DDR_PHY_DX0GCR4_DXREFSSELRANGE_MASK 0x00008000U -/*Byte Lane Single-End VREF Select*/ +/* +* Byte Lane Single-End VREF Select +*/ #undef DDR_PHY_DX0GCR4_DXREFSSEL_DEFVAL #undef DDR_PHY_DX0GCR4_DXREFSSEL_SHIFT #undef DDR_PHY_DX0GCR4_DXREFSSEL_MASK -#define DDR_PHY_DX0GCR4_DXREFSSEL_DEFVAL 0x0E00003C -#define DDR_PHY_DX0GCR4_DXREFSSEL_SHIFT 8 -#define DDR_PHY_DX0GCR4_DXREFSSEL_MASK 0x00007F00U +#define DDR_PHY_DX0GCR4_DXREFSSEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX0GCR4_DXREFSSEL_SHIFT 8 +#define DDR_PHY_DX0GCR4_DXREFSSEL_MASK 0x00007F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX0GCR4_RESERVED_7_6_DEFVAL #undef DDR_PHY_DX0GCR4_RESERVED_7_6_SHIFT #undef DDR_PHY_DX0GCR4_RESERVED_7_6_MASK -#define DDR_PHY_DX0GCR4_RESERVED_7_6_DEFVAL 0x0E00003C -#define DDR_PHY_DX0GCR4_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_DX0GCR4_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_DX0GCR4_RESERVED_7_6_DEFVAL 0x0E00003C +#define DDR_PHY_DX0GCR4_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX0GCR4_RESERVED_7_6_MASK 0x000000C0U -/*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/ +/* +* VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. +*/ #undef DDR_PHY_DX0GCR4_DXREFIEN_DEFVAL #undef DDR_PHY_DX0GCR4_DXREFIEN_SHIFT #undef DDR_PHY_DX0GCR4_DXREFIEN_MASK -#define DDR_PHY_DX0GCR4_DXREFIEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX0GCR4_DXREFIEN_SHIFT 2 -#define DDR_PHY_DX0GCR4_DXREFIEN_MASK 0x0000003CU +#define DDR_PHY_DX0GCR4_DXREFIEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX0GCR4_DXREFIEN_SHIFT 2 +#define DDR_PHY_DX0GCR4_DXREFIEN_MASK 0x0000003CU -/*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/ +/* +* VRMON control for DQ IO (Single Ended) buffers of a byte lane. +*/ #undef DDR_PHY_DX0GCR4_DXREFIMON_DEFVAL #undef DDR_PHY_DX0GCR4_DXREFIMON_SHIFT #undef DDR_PHY_DX0GCR4_DXREFIMON_MASK -#define DDR_PHY_DX0GCR4_DXREFIMON_DEFVAL 0x0E00003C -#define DDR_PHY_DX0GCR4_DXREFIMON_SHIFT 0 -#define DDR_PHY_DX0GCR4_DXREFIMON_MASK 0x00000003U +#define DDR_PHY_DX0GCR4_DXREFIMON_DEFVAL 0x0E00003C +#define DDR_PHY_DX0GCR4_DXREFIMON_SHIFT 0 +#define DDR_PHY_DX0GCR4_DXREFIMON_MASK 0x00000003U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX0GCR5_RESERVED_31_DEFVAL #undef DDR_PHY_DX0GCR5_RESERVED_31_SHIFT #undef DDR_PHY_DX0GCR5_RESERVED_31_MASK -#define DDR_PHY_DX0GCR5_RESERVED_31_DEFVAL 0x09090909 -#define DDR_PHY_DX0GCR5_RESERVED_31_SHIFT 31 -#define DDR_PHY_DX0GCR5_RESERVED_31_MASK 0x80000000U +#define DDR_PHY_DX0GCR5_RESERVED_31_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR5_RESERVED_31_SHIFT 31 +#define DDR_PHY_DX0GCR5_RESERVED_31_MASK 0x80000000U -/*Byte Lane internal VREF Select for Rank 3*/ +/* +* Byte Lane internal VREF Select for Rank 3 +*/ #undef DDR_PHY_DX0GCR5_DXREFISELR3_DEFVAL #undef DDR_PHY_DX0GCR5_DXREFISELR3_SHIFT #undef DDR_PHY_DX0GCR5_DXREFISELR3_MASK -#define DDR_PHY_DX0GCR5_DXREFISELR3_DEFVAL 0x09090909 -#define DDR_PHY_DX0GCR5_DXREFISELR3_SHIFT 24 -#define DDR_PHY_DX0GCR5_DXREFISELR3_MASK 0x7F000000U +#define DDR_PHY_DX0GCR5_DXREFISELR3_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR5_DXREFISELR3_SHIFT 24 +#define DDR_PHY_DX0GCR5_DXREFISELR3_MASK 0x7F000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX0GCR5_RESERVED_23_DEFVAL #undef DDR_PHY_DX0GCR5_RESERVED_23_SHIFT #undef DDR_PHY_DX0GCR5_RESERVED_23_MASK -#define DDR_PHY_DX0GCR5_RESERVED_23_DEFVAL 0x09090909 -#define DDR_PHY_DX0GCR5_RESERVED_23_SHIFT 23 -#define DDR_PHY_DX0GCR5_RESERVED_23_MASK 0x00800000U +#define DDR_PHY_DX0GCR5_RESERVED_23_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR5_RESERVED_23_SHIFT 23 +#define DDR_PHY_DX0GCR5_RESERVED_23_MASK 0x00800000U -/*Byte Lane internal VREF Select for Rank 2*/ +/* +* Byte Lane internal VREF Select for Rank 2 +*/ #undef DDR_PHY_DX0GCR5_DXREFISELR2_DEFVAL #undef DDR_PHY_DX0GCR5_DXREFISELR2_SHIFT #undef DDR_PHY_DX0GCR5_DXREFISELR2_MASK -#define DDR_PHY_DX0GCR5_DXREFISELR2_DEFVAL 0x09090909 -#define DDR_PHY_DX0GCR5_DXREFISELR2_SHIFT 16 -#define DDR_PHY_DX0GCR5_DXREFISELR2_MASK 0x007F0000U +#define DDR_PHY_DX0GCR5_DXREFISELR2_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR5_DXREFISELR2_SHIFT 16 +#define DDR_PHY_DX0GCR5_DXREFISELR2_MASK 0x007F0000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX0GCR5_RESERVED_15_DEFVAL #undef DDR_PHY_DX0GCR5_RESERVED_15_SHIFT #undef DDR_PHY_DX0GCR5_RESERVED_15_MASK -#define DDR_PHY_DX0GCR5_RESERVED_15_DEFVAL 0x09090909 -#define DDR_PHY_DX0GCR5_RESERVED_15_SHIFT 15 -#define DDR_PHY_DX0GCR5_RESERVED_15_MASK 0x00008000U +#define DDR_PHY_DX0GCR5_RESERVED_15_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR5_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX0GCR5_RESERVED_15_MASK 0x00008000U -/*Byte Lane internal VREF Select for Rank 1*/ +/* +* Byte Lane internal VREF Select for Rank 1 +*/ #undef DDR_PHY_DX0GCR5_DXREFISELR1_DEFVAL #undef DDR_PHY_DX0GCR5_DXREFISELR1_SHIFT #undef DDR_PHY_DX0GCR5_DXREFISELR1_MASK -#define DDR_PHY_DX0GCR5_DXREFISELR1_DEFVAL 0x09090909 -#define DDR_PHY_DX0GCR5_DXREFISELR1_SHIFT 8 -#define DDR_PHY_DX0GCR5_DXREFISELR1_MASK 0x00007F00U +#define DDR_PHY_DX0GCR5_DXREFISELR1_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR5_DXREFISELR1_SHIFT 8 +#define DDR_PHY_DX0GCR5_DXREFISELR1_MASK 0x00007F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX0GCR5_RESERVED_7_DEFVAL #undef DDR_PHY_DX0GCR5_RESERVED_7_SHIFT #undef DDR_PHY_DX0GCR5_RESERVED_7_MASK -#define DDR_PHY_DX0GCR5_RESERVED_7_DEFVAL 0x09090909 -#define DDR_PHY_DX0GCR5_RESERVED_7_SHIFT 7 -#define DDR_PHY_DX0GCR5_RESERVED_7_MASK 0x00000080U +#define DDR_PHY_DX0GCR5_RESERVED_7_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR5_RESERVED_7_SHIFT 7 +#define DDR_PHY_DX0GCR5_RESERVED_7_MASK 0x00000080U -/*Byte Lane internal VREF Select for Rank 0*/ +/* +* Byte Lane internal VREF Select for Rank 0 +*/ #undef DDR_PHY_DX0GCR5_DXREFISELR0_DEFVAL #undef DDR_PHY_DX0GCR5_DXREFISELR0_SHIFT #undef DDR_PHY_DX0GCR5_DXREFISELR0_MASK -#define DDR_PHY_DX0GCR5_DXREFISELR0_DEFVAL 0x09090909 -#define DDR_PHY_DX0GCR5_DXREFISELR0_SHIFT 0 -#define DDR_PHY_DX0GCR5_DXREFISELR0_MASK 0x0000007FU +#define DDR_PHY_DX0GCR5_DXREFISELR0_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR5_DXREFISELR0_SHIFT 0 +#define DDR_PHY_DX0GCR5_DXREFISELR0_MASK 0x0000007FU -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX0GCR6_RESERVED_31_30_DEFVAL #undef DDR_PHY_DX0GCR6_RESERVED_31_30_SHIFT #undef DDR_PHY_DX0GCR6_RESERVED_31_30_MASK -#define DDR_PHY_DX0GCR6_RESERVED_31_30_DEFVAL 0x09090909 -#define DDR_PHY_DX0GCR6_RESERVED_31_30_SHIFT 30 -#define DDR_PHY_DX0GCR6_RESERVED_31_30_MASK 0xC0000000U +#define DDR_PHY_DX0GCR6_RESERVED_31_30_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR6_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX0GCR6_RESERVED_31_30_MASK 0xC0000000U -/*DRAM DQ VREF Select for Rank3*/ +/* +* DRAM DQ VREF Select for Rank3 +*/ #undef DDR_PHY_DX0GCR6_DXDQVREFR3_DEFVAL #undef DDR_PHY_DX0GCR6_DXDQVREFR3_SHIFT #undef DDR_PHY_DX0GCR6_DXDQVREFR3_MASK -#define DDR_PHY_DX0GCR6_DXDQVREFR3_DEFVAL 0x09090909 -#define DDR_PHY_DX0GCR6_DXDQVREFR3_SHIFT 24 -#define DDR_PHY_DX0GCR6_DXDQVREFR3_MASK 0x3F000000U +#define DDR_PHY_DX0GCR6_DXDQVREFR3_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR6_DXDQVREFR3_SHIFT 24 +#define DDR_PHY_DX0GCR6_DXDQVREFR3_MASK 0x3F000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX0GCR6_RESERVED_23_22_DEFVAL #undef DDR_PHY_DX0GCR6_RESERVED_23_22_SHIFT #undef DDR_PHY_DX0GCR6_RESERVED_23_22_MASK -#define DDR_PHY_DX0GCR6_RESERVED_23_22_DEFVAL 0x09090909 -#define DDR_PHY_DX0GCR6_RESERVED_23_22_SHIFT 22 -#define DDR_PHY_DX0GCR6_RESERVED_23_22_MASK 0x00C00000U +#define DDR_PHY_DX0GCR6_RESERVED_23_22_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR6_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX0GCR6_RESERVED_23_22_MASK 0x00C00000U -/*DRAM DQ VREF Select for Rank2*/ +/* +* DRAM DQ VREF Select for Rank2 +*/ #undef DDR_PHY_DX0GCR6_DXDQVREFR2_DEFVAL #undef DDR_PHY_DX0GCR6_DXDQVREFR2_SHIFT #undef DDR_PHY_DX0GCR6_DXDQVREFR2_MASK -#define DDR_PHY_DX0GCR6_DXDQVREFR2_DEFVAL 0x09090909 -#define DDR_PHY_DX0GCR6_DXDQVREFR2_SHIFT 16 -#define DDR_PHY_DX0GCR6_DXDQVREFR2_MASK 0x003F0000U +#define DDR_PHY_DX0GCR6_DXDQVREFR2_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR6_DXDQVREFR2_SHIFT 16 +#define DDR_PHY_DX0GCR6_DXDQVREFR2_MASK 0x003F0000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX0GCR6_RESERVED_15_14_DEFVAL #undef DDR_PHY_DX0GCR6_RESERVED_15_14_SHIFT #undef DDR_PHY_DX0GCR6_RESERVED_15_14_MASK -#define DDR_PHY_DX0GCR6_RESERVED_15_14_DEFVAL 0x09090909 -#define DDR_PHY_DX0GCR6_RESERVED_15_14_SHIFT 14 -#define DDR_PHY_DX0GCR6_RESERVED_15_14_MASK 0x0000C000U +#define DDR_PHY_DX0GCR6_RESERVED_15_14_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR6_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_DX0GCR6_RESERVED_15_14_MASK 0x0000C000U -/*DRAM DQ VREF Select for Rank1*/ +/* +* DRAM DQ VREF Select for Rank1 +*/ #undef DDR_PHY_DX0GCR6_DXDQVREFR1_DEFVAL #undef DDR_PHY_DX0GCR6_DXDQVREFR1_SHIFT #undef DDR_PHY_DX0GCR6_DXDQVREFR1_MASK -#define DDR_PHY_DX0GCR6_DXDQVREFR1_DEFVAL 0x09090909 -#define DDR_PHY_DX0GCR6_DXDQVREFR1_SHIFT 8 -#define DDR_PHY_DX0GCR6_DXDQVREFR1_MASK 0x00003F00U +#define DDR_PHY_DX0GCR6_DXDQVREFR1_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR6_DXDQVREFR1_SHIFT 8 +#define DDR_PHY_DX0GCR6_DXDQVREFR1_MASK 0x00003F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX0GCR6_RESERVED_7_6_DEFVAL #undef DDR_PHY_DX0GCR6_RESERVED_7_6_SHIFT #undef DDR_PHY_DX0GCR6_RESERVED_7_6_MASK -#define DDR_PHY_DX0GCR6_RESERVED_7_6_DEFVAL 0x09090909 -#define DDR_PHY_DX0GCR6_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_DX0GCR6_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_DX0GCR6_RESERVED_7_6_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR6_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX0GCR6_RESERVED_7_6_MASK 0x000000C0U -/*DRAM DQ VREF Select for Rank0*/ +/* +* DRAM DQ VREF Select for Rank0 +*/ #undef DDR_PHY_DX0GCR6_DXDQVREFR0_DEFVAL #undef DDR_PHY_DX0GCR6_DXDQVREFR0_SHIFT #undef DDR_PHY_DX0GCR6_DXDQVREFR0_MASK -#define DDR_PHY_DX0GCR6_DXDQVREFR0_DEFVAL 0x09090909 -#define DDR_PHY_DX0GCR6_DXDQVREFR0_SHIFT 0 -#define DDR_PHY_DX0GCR6_DXDQVREFR0_MASK 0x0000003FU +#define DDR_PHY_DX0GCR6_DXDQVREFR0_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR6_DXDQVREFR0_SHIFT 0 +#define DDR_PHY_DX0GCR6_DXDQVREFR0_MASK 0x0000003FU -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX0LCDLR2_RESERVED_31_25_DEFVAL -#undef DDR_PHY_DX0LCDLR2_RESERVED_31_25_SHIFT -#undef DDR_PHY_DX0LCDLR2_RESERVED_31_25_MASK -#define DDR_PHY_DX0LCDLR2_RESERVED_31_25_DEFVAL 0x00000000 -#define DDR_PHY_DX0LCDLR2_RESERVED_31_25_SHIFT 25 -#define DDR_PHY_DX0LCDLR2_RESERVED_31_25_MASK 0xFE000000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX0LCDLR2_RESERVED_24_16_DEFVAL -#undef DDR_PHY_DX0LCDLR2_RESERVED_24_16_SHIFT -#undef DDR_PHY_DX0LCDLR2_RESERVED_24_16_MASK -#define DDR_PHY_DX0LCDLR2_RESERVED_24_16_DEFVAL 0x00000000 -#define DDR_PHY_DX0LCDLR2_RESERVED_24_16_SHIFT 16 -#define DDR_PHY_DX0LCDLR2_RESERVED_24_16_MASK 0x01FF0000U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX0LCDLR2_RESERVED_15_9_DEFVAL -#undef DDR_PHY_DX0LCDLR2_RESERVED_15_9_SHIFT -#undef DDR_PHY_DX0LCDLR2_RESERVED_15_9_MASK -#define DDR_PHY_DX0LCDLR2_RESERVED_15_9_DEFVAL 0x00000000 -#define DDR_PHY_DX0LCDLR2_RESERVED_15_9_SHIFT 9 -#define DDR_PHY_DX0LCDLR2_RESERVED_15_9_MASK 0x0000FE00U - -/*Read DQS Gating Delay*/ -#undef DDR_PHY_DX0LCDLR2_DQSGD_DEFVAL -#undef DDR_PHY_DX0LCDLR2_DQSGD_SHIFT -#undef DDR_PHY_DX0LCDLR2_DQSGD_MASK -#define DDR_PHY_DX0LCDLR2_DQSGD_DEFVAL 0x00000000 -#define DDR_PHY_DX0LCDLR2_DQSGD_SHIFT 0 -#define DDR_PHY_DX0LCDLR2_DQSGD_MASK 0x000001FFU - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX0GTR0_RESERVED_31_24_DEFVAL -#undef DDR_PHY_DX0GTR0_RESERVED_31_24_SHIFT -#undef DDR_PHY_DX0GTR0_RESERVED_31_24_MASK -#define DDR_PHY_DX0GTR0_RESERVED_31_24_DEFVAL 0x00020000 -#define DDR_PHY_DX0GTR0_RESERVED_31_24_SHIFT 27 -#define DDR_PHY_DX0GTR0_RESERVED_31_24_MASK 0xF8000000U - -/*DQ Write Path Latency Pipeline*/ -#undef DDR_PHY_DX0GTR0_WDQSL_DEFVAL -#undef DDR_PHY_DX0GTR0_WDQSL_SHIFT -#undef DDR_PHY_DX0GTR0_WDQSL_MASK -#define DDR_PHY_DX0GTR0_WDQSL_DEFVAL 0x00020000 -#define DDR_PHY_DX0GTR0_WDQSL_SHIFT 24 -#define DDR_PHY_DX0GTR0_WDQSL_MASK 0x07000000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX0GTR0_RESERVED_23_20_DEFVAL -#undef DDR_PHY_DX0GTR0_RESERVED_23_20_SHIFT -#undef DDR_PHY_DX0GTR0_RESERVED_23_20_MASK -#define DDR_PHY_DX0GTR0_RESERVED_23_20_DEFVAL 0x00020000 -#define DDR_PHY_DX0GTR0_RESERVED_23_20_SHIFT 20 -#define DDR_PHY_DX0GTR0_RESERVED_23_20_MASK 0x00F00000U - -/*Write Leveling System Latency*/ -#undef DDR_PHY_DX0GTR0_WLSL_DEFVAL -#undef DDR_PHY_DX0GTR0_WLSL_SHIFT -#undef DDR_PHY_DX0GTR0_WLSL_MASK -#define DDR_PHY_DX0GTR0_WLSL_DEFVAL 0x00020000 -#define DDR_PHY_DX0GTR0_WLSL_SHIFT 16 -#define DDR_PHY_DX0GTR0_WLSL_MASK 0x000F0000U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX0GTR0_RESERVED_15_13_DEFVAL -#undef DDR_PHY_DX0GTR0_RESERVED_15_13_SHIFT -#undef DDR_PHY_DX0GTR0_RESERVED_15_13_MASK -#define DDR_PHY_DX0GTR0_RESERVED_15_13_DEFVAL 0x00020000 -#define DDR_PHY_DX0GTR0_RESERVED_15_13_SHIFT 13 -#define DDR_PHY_DX0GTR0_RESERVED_15_13_MASK 0x0000E000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX0GTR0_RESERVED_12_8_DEFVAL -#undef DDR_PHY_DX0GTR0_RESERVED_12_8_SHIFT -#undef DDR_PHY_DX0GTR0_RESERVED_12_8_MASK -#define DDR_PHY_DX0GTR0_RESERVED_12_8_DEFVAL 0x00020000 -#define DDR_PHY_DX0GTR0_RESERVED_12_8_SHIFT 8 -#define DDR_PHY_DX0GTR0_RESERVED_12_8_MASK 0x00001F00U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX0GTR0_RESERVED_7_5_DEFVAL -#undef DDR_PHY_DX0GTR0_RESERVED_7_5_SHIFT -#undef DDR_PHY_DX0GTR0_RESERVED_7_5_MASK -#define DDR_PHY_DX0GTR0_RESERVED_7_5_DEFVAL 0x00020000 -#define DDR_PHY_DX0GTR0_RESERVED_7_5_SHIFT 5 -#define DDR_PHY_DX0GTR0_RESERVED_7_5_MASK 0x000000E0U - -/*DQS Gating System Latency*/ -#undef DDR_PHY_DX0GTR0_DGSL_DEFVAL -#undef DDR_PHY_DX0GTR0_DGSL_SHIFT -#undef DDR_PHY_DX0GTR0_DGSL_MASK -#define DDR_PHY_DX0GTR0_DGSL_DEFVAL 0x00020000 -#define DDR_PHY_DX0GTR0_DGSL_SHIFT 0 -#define DDR_PHY_DX0GTR0_DGSL_MASK 0x0000001FU - -/*Calibration Bypass*/ +/* +* Calibration Bypass +*/ #undef DDR_PHY_DX1GCR0_CALBYP_DEFVAL #undef DDR_PHY_DX1GCR0_CALBYP_SHIFT #undef DDR_PHY_DX1GCR0_CALBYP_MASK -#define DDR_PHY_DX1GCR0_CALBYP_DEFVAL 0x40200204 -#define DDR_PHY_DX1GCR0_CALBYP_SHIFT 31 -#define DDR_PHY_DX1GCR0_CALBYP_MASK 0x80000000U +#define DDR_PHY_DX1GCR0_CALBYP_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_CALBYP_SHIFT 31 +#define DDR_PHY_DX1GCR0_CALBYP_MASK 0x80000000U -/*Master Delay Line Enable*/ +/* +* Master Delay Line Enable +*/ #undef DDR_PHY_DX1GCR0_MDLEN_DEFVAL #undef DDR_PHY_DX1GCR0_MDLEN_SHIFT #undef DDR_PHY_DX1GCR0_MDLEN_MASK -#define DDR_PHY_DX1GCR0_MDLEN_DEFVAL 0x40200204 -#define DDR_PHY_DX1GCR0_MDLEN_SHIFT 30 -#define DDR_PHY_DX1GCR0_MDLEN_MASK 0x40000000U +#define DDR_PHY_DX1GCR0_MDLEN_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_MDLEN_SHIFT 30 +#define DDR_PHY_DX1GCR0_MDLEN_MASK 0x40000000U -/*Configurable ODT(TE) Phase Shift*/ +/* +* Configurable ODT(TE) Phase Shift +*/ #undef DDR_PHY_DX1GCR0_CODTSHFT_DEFVAL #undef DDR_PHY_DX1GCR0_CODTSHFT_SHIFT #undef DDR_PHY_DX1GCR0_CODTSHFT_MASK -#define DDR_PHY_DX1GCR0_CODTSHFT_DEFVAL 0x40200204 -#define DDR_PHY_DX1GCR0_CODTSHFT_SHIFT 28 -#define DDR_PHY_DX1GCR0_CODTSHFT_MASK 0x30000000U +#define DDR_PHY_DX1GCR0_CODTSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_CODTSHFT_SHIFT 28 +#define DDR_PHY_DX1GCR0_CODTSHFT_MASK 0x30000000U -/*DQS Duty Cycle Correction*/ +/* +* DQS Duty Cycle Correction +*/ #undef DDR_PHY_DX1GCR0_DQSDCC_DEFVAL #undef DDR_PHY_DX1GCR0_DQSDCC_SHIFT #undef DDR_PHY_DX1GCR0_DQSDCC_MASK -#define DDR_PHY_DX1GCR0_DQSDCC_DEFVAL 0x40200204 -#define DDR_PHY_DX1GCR0_DQSDCC_SHIFT 24 -#define DDR_PHY_DX1GCR0_DQSDCC_MASK 0x0F000000U +#define DDR_PHY_DX1GCR0_DQSDCC_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_DQSDCC_SHIFT 24 +#define DDR_PHY_DX1GCR0_DQSDCC_MASK 0x0F000000U -/*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/ +/* +* Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY +*/ #undef DDR_PHY_DX1GCR0_RDDLY_DEFVAL #undef DDR_PHY_DX1GCR0_RDDLY_SHIFT #undef DDR_PHY_DX1GCR0_RDDLY_MASK -#define DDR_PHY_DX1GCR0_RDDLY_DEFVAL 0x40200204 -#define DDR_PHY_DX1GCR0_RDDLY_SHIFT 20 -#define DDR_PHY_DX1GCR0_RDDLY_MASK 0x00F00000U +#define DDR_PHY_DX1GCR0_RDDLY_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_RDDLY_SHIFT 20 +#define DDR_PHY_DX1GCR0_RDDLY_MASK 0x00F00000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX1GCR0_RESERVED_19_14_DEFVAL #undef DDR_PHY_DX1GCR0_RESERVED_19_14_SHIFT #undef DDR_PHY_DX1GCR0_RESERVED_19_14_MASK -#define DDR_PHY_DX1GCR0_RESERVED_19_14_DEFVAL 0x40200204 -#define DDR_PHY_DX1GCR0_RESERVED_19_14_SHIFT 14 -#define DDR_PHY_DX1GCR0_RESERVED_19_14_MASK 0x000FC000U +#define DDR_PHY_DX1GCR0_RESERVED_19_14_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_RESERVED_19_14_SHIFT 14 +#define DDR_PHY_DX1GCR0_RESERVED_19_14_MASK 0x000FC000U -/*DQSNSE Power Down Receiver*/ +/* +* DQSNSE Power Down Receiver +*/ #undef DDR_PHY_DX1GCR0_DQSNSEPDR_DEFVAL #undef DDR_PHY_DX1GCR0_DQSNSEPDR_SHIFT #undef DDR_PHY_DX1GCR0_DQSNSEPDR_MASK -#define DDR_PHY_DX1GCR0_DQSNSEPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX1GCR0_DQSNSEPDR_SHIFT 13 -#define DDR_PHY_DX1GCR0_DQSNSEPDR_MASK 0x00002000U +#define DDR_PHY_DX1GCR0_DQSNSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_DQSNSEPDR_SHIFT 13 +#define DDR_PHY_DX1GCR0_DQSNSEPDR_MASK 0x00002000U -/*DQSSE Power Down Receiver*/ +/* +* DQSSE Power Down Receiver +*/ #undef DDR_PHY_DX1GCR0_DQSSEPDR_DEFVAL #undef DDR_PHY_DX1GCR0_DQSSEPDR_SHIFT #undef DDR_PHY_DX1GCR0_DQSSEPDR_MASK -#define DDR_PHY_DX1GCR0_DQSSEPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX1GCR0_DQSSEPDR_SHIFT 12 -#define DDR_PHY_DX1GCR0_DQSSEPDR_MASK 0x00001000U +#define DDR_PHY_DX1GCR0_DQSSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_DQSSEPDR_SHIFT 12 +#define DDR_PHY_DX1GCR0_DQSSEPDR_MASK 0x00001000U -/*RTT On Additive Latency*/ +/* +* RTT On Additive Latency +*/ #undef DDR_PHY_DX1GCR0_RTTOAL_DEFVAL #undef DDR_PHY_DX1GCR0_RTTOAL_SHIFT #undef DDR_PHY_DX1GCR0_RTTOAL_MASK -#define DDR_PHY_DX1GCR0_RTTOAL_DEFVAL 0x40200204 -#define DDR_PHY_DX1GCR0_RTTOAL_SHIFT 11 -#define DDR_PHY_DX1GCR0_RTTOAL_MASK 0x00000800U +#define DDR_PHY_DX1GCR0_RTTOAL_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_RTTOAL_SHIFT 11 +#define DDR_PHY_DX1GCR0_RTTOAL_MASK 0x00000800U -/*RTT Output Hold*/ +/* +* RTT Output Hold +*/ #undef DDR_PHY_DX1GCR0_RTTOH_DEFVAL #undef DDR_PHY_DX1GCR0_RTTOH_SHIFT #undef DDR_PHY_DX1GCR0_RTTOH_MASK -#define DDR_PHY_DX1GCR0_RTTOH_DEFVAL 0x40200204 -#define DDR_PHY_DX1GCR0_RTTOH_SHIFT 9 -#define DDR_PHY_DX1GCR0_RTTOH_MASK 0x00000600U +#define DDR_PHY_DX1GCR0_RTTOH_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_RTTOH_SHIFT 9 +#define DDR_PHY_DX1GCR0_RTTOH_MASK 0x00000600U -/*Configurable PDR Phase Shift*/ +/* +* Configurable PDR Phase Shift +*/ #undef DDR_PHY_DX1GCR0_CPDRSHFT_DEFVAL #undef DDR_PHY_DX1GCR0_CPDRSHFT_SHIFT #undef DDR_PHY_DX1GCR0_CPDRSHFT_MASK -#define DDR_PHY_DX1GCR0_CPDRSHFT_DEFVAL 0x40200204 -#define DDR_PHY_DX1GCR0_CPDRSHFT_SHIFT 7 -#define DDR_PHY_DX1GCR0_CPDRSHFT_MASK 0x00000180U +#define DDR_PHY_DX1GCR0_CPDRSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_CPDRSHFT_SHIFT 7 +#define DDR_PHY_DX1GCR0_CPDRSHFT_MASK 0x00000180U -/*DQSR Power Down*/ +/* +* DQSR Power Down +*/ #undef DDR_PHY_DX1GCR0_DQSRPD_DEFVAL #undef DDR_PHY_DX1GCR0_DQSRPD_SHIFT #undef DDR_PHY_DX1GCR0_DQSRPD_MASK -#define DDR_PHY_DX1GCR0_DQSRPD_DEFVAL 0x40200204 -#define DDR_PHY_DX1GCR0_DQSRPD_SHIFT 6 -#define DDR_PHY_DX1GCR0_DQSRPD_MASK 0x00000040U +#define DDR_PHY_DX1GCR0_DQSRPD_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_DQSRPD_SHIFT 6 +#define DDR_PHY_DX1GCR0_DQSRPD_MASK 0x00000040U -/*DQSG Power Down Receiver*/ +/* +* DQSG Power Down Receiver +*/ #undef DDR_PHY_DX1GCR0_DQSGPDR_DEFVAL #undef DDR_PHY_DX1GCR0_DQSGPDR_SHIFT #undef DDR_PHY_DX1GCR0_DQSGPDR_MASK -#define DDR_PHY_DX1GCR0_DQSGPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX1GCR0_DQSGPDR_SHIFT 5 -#define DDR_PHY_DX1GCR0_DQSGPDR_MASK 0x00000020U +#define DDR_PHY_DX1GCR0_DQSGPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_DQSGPDR_SHIFT 5 +#define DDR_PHY_DX1GCR0_DQSGPDR_MASK 0x00000020U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX1GCR0_RESERVED_4_DEFVAL #undef DDR_PHY_DX1GCR0_RESERVED_4_SHIFT #undef DDR_PHY_DX1GCR0_RESERVED_4_MASK -#define DDR_PHY_DX1GCR0_RESERVED_4_DEFVAL 0x40200204 -#define DDR_PHY_DX1GCR0_RESERVED_4_SHIFT 4 -#define DDR_PHY_DX1GCR0_RESERVED_4_MASK 0x00000010U +#define DDR_PHY_DX1GCR0_RESERVED_4_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_RESERVED_4_SHIFT 4 +#define DDR_PHY_DX1GCR0_RESERVED_4_MASK 0x00000010U -/*DQSG On-Die Termination*/ +/* +* DQSG On-Die Termination +*/ #undef DDR_PHY_DX1GCR0_DQSGODT_DEFVAL #undef DDR_PHY_DX1GCR0_DQSGODT_SHIFT #undef DDR_PHY_DX1GCR0_DQSGODT_MASK -#define DDR_PHY_DX1GCR0_DQSGODT_DEFVAL 0x40200204 -#define DDR_PHY_DX1GCR0_DQSGODT_SHIFT 3 -#define DDR_PHY_DX1GCR0_DQSGODT_MASK 0x00000008U +#define DDR_PHY_DX1GCR0_DQSGODT_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_DQSGODT_SHIFT 3 +#define DDR_PHY_DX1GCR0_DQSGODT_MASK 0x00000008U -/*DQSG Output Enable*/ +/* +* DQSG Output Enable +*/ #undef DDR_PHY_DX1GCR0_DQSGOE_DEFVAL #undef DDR_PHY_DX1GCR0_DQSGOE_SHIFT #undef DDR_PHY_DX1GCR0_DQSGOE_MASK -#define DDR_PHY_DX1GCR0_DQSGOE_DEFVAL 0x40200204 -#define DDR_PHY_DX1GCR0_DQSGOE_SHIFT 2 -#define DDR_PHY_DX1GCR0_DQSGOE_MASK 0x00000004U +#define DDR_PHY_DX1GCR0_DQSGOE_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_DQSGOE_SHIFT 2 +#define DDR_PHY_DX1GCR0_DQSGOE_MASK 0x00000004U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX1GCR0_RESERVED_1_0_DEFVAL #undef DDR_PHY_DX1GCR0_RESERVED_1_0_SHIFT #undef DDR_PHY_DX1GCR0_RESERVED_1_0_MASK -#define DDR_PHY_DX1GCR0_RESERVED_1_0_DEFVAL 0x40200204 -#define DDR_PHY_DX1GCR0_RESERVED_1_0_SHIFT 0 -#define DDR_PHY_DX1GCR0_RESERVED_1_0_MASK 0x00000003U +#define DDR_PHY_DX1GCR0_RESERVED_1_0_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_RESERVED_1_0_SHIFT 0 +#define DDR_PHY_DX1GCR0_RESERVED_1_0_MASK 0x00000003U -/*Byte lane VREF IOM (Used only by D4MU IOs)*/ +/* +* Byte lane VREF IOM (Used only by D4MU IOs) +*/ #undef DDR_PHY_DX1GCR4_RESERVED_31_29_DEFVAL #undef DDR_PHY_DX1GCR4_RESERVED_31_29_SHIFT #undef DDR_PHY_DX1GCR4_RESERVED_31_29_MASK -#define DDR_PHY_DX1GCR4_RESERVED_31_29_DEFVAL 0x0E00003C -#define DDR_PHY_DX1GCR4_RESERVED_31_29_SHIFT 29 -#define DDR_PHY_DX1GCR4_RESERVED_31_29_MASK 0xE0000000U +#define DDR_PHY_DX1GCR4_RESERVED_31_29_DEFVAL 0x0E00003C +#define DDR_PHY_DX1GCR4_RESERVED_31_29_SHIFT 29 +#define DDR_PHY_DX1GCR4_RESERVED_31_29_MASK 0xE0000000U -/*Byte Lane VREF Pad Enable*/ +/* +* Byte Lane VREF Pad Enable +*/ #undef DDR_PHY_DX1GCR4_DXREFPEN_DEFVAL #undef DDR_PHY_DX1GCR4_DXREFPEN_SHIFT #undef DDR_PHY_DX1GCR4_DXREFPEN_MASK -#define DDR_PHY_DX1GCR4_DXREFPEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX1GCR4_DXREFPEN_SHIFT 28 -#define DDR_PHY_DX1GCR4_DXREFPEN_MASK 0x10000000U +#define DDR_PHY_DX1GCR4_DXREFPEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX1GCR4_DXREFPEN_SHIFT 28 +#define DDR_PHY_DX1GCR4_DXREFPEN_MASK 0x10000000U -/*Byte Lane Internal VREF Enable*/ +/* +* Byte Lane Internal VREF Enable +*/ #undef DDR_PHY_DX1GCR4_DXREFEEN_DEFVAL #undef DDR_PHY_DX1GCR4_DXREFEEN_SHIFT #undef DDR_PHY_DX1GCR4_DXREFEEN_MASK -#define DDR_PHY_DX1GCR4_DXREFEEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX1GCR4_DXREFEEN_SHIFT 26 -#define DDR_PHY_DX1GCR4_DXREFEEN_MASK 0x0C000000U +#define DDR_PHY_DX1GCR4_DXREFEEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX1GCR4_DXREFEEN_SHIFT 26 +#define DDR_PHY_DX1GCR4_DXREFEEN_MASK 0x0C000000U -/*Byte Lane Single-End VREF Enable*/ +/* +* Byte Lane Single-End VREF Enable +*/ #undef DDR_PHY_DX1GCR4_DXREFSEN_DEFVAL #undef DDR_PHY_DX1GCR4_DXREFSEN_SHIFT #undef DDR_PHY_DX1GCR4_DXREFSEN_MASK -#define DDR_PHY_DX1GCR4_DXREFSEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX1GCR4_DXREFSEN_SHIFT 25 -#define DDR_PHY_DX1GCR4_DXREFSEN_MASK 0x02000000U +#define DDR_PHY_DX1GCR4_DXREFSEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX1GCR4_DXREFSEN_SHIFT 25 +#define DDR_PHY_DX1GCR4_DXREFSEN_MASK 0x02000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX1GCR4_RESERVED_24_DEFVAL #undef DDR_PHY_DX1GCR4_RESERVED_24_SHIFT #undef DDR_PHY_DX1GCR4_RESERVED_24_MASK -#define DDR_PHY_DX1GCR4_RESERVED_24_DEFVAL 0x0E00003C -#define DDR_PHY_DX1GCR4_RESERVED_24_SHIFT 24 -#define DDR_PHY_DX1GCR4_RESERVED_24_MASK 0x01000000U +#define DDR_PHY_DX1GCR4_RESERVED_24_DEFVAL 0x0E00003C +#define DDR_PHY_DX1GCR4_RESERVED_24_SHIFT 24 +#define DDR_PHY_DX1GCR4_RESERVED_24_MASK 0x01000000U -/*External VREF generator REFSEL range select*/ +/* +* External VREF generator REFSEL range select +*/ #undef DDR_PHY_DX1GCR4_DXREFESELRANGE_DEFVAL #undef DDR_PHY_DX1GCR4_DXREFESELRANGE_SHIFT #undef DDR_PHY_DX1GCR4_DXREFESELRANGE_MASK -#define DDR_PHY_DX1GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C -#define DDR_PHY_DX1GCR4_DXREFESELRANGE_SHIFT 23 -#define DDR_PHY_DX1GCR4_DXREFESELRANGE_MASK 0x00800000U +#define DDR_PHY_DX1GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX1GCR4_DXREFESELRANGE_SHIFT 23 +#define DDR_PHY_DX1GCR4_DXREFESELRANGE_MASK 0x00800000U -/*Byte Lane External VREF Select*/ +/* +* Byte Lane External VREF Select +*/ #undef DDR_PHY_DX1GCR4_DXREFESEL_DEFVAL #undef DDR_PHY_DX1GCR4_DXREFESEL_SHIFT #undef DDR_PHY_DX1GCR4_DXREFESEL_MASK -#define DDR_PHY_DX1GCR4_DXREFESEL_DEFVAL 0x0E00003C -#define DDR_PHY_DX1GCR4_DXREFESEL_SHIFT 16 -#define DDR_PHY_DX1GCR4_DXREFESEL_MASK 0x007F0000U +#define DDR_PHY_DX1GCR4_DXREFESEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX1GCR4_DXREFESEL_SHIFT 16 +#define DDR_PHY_DX1GCR4_DXREFESEL_MASK 0x007F0000U -/*Single ended VREF generator REFSEL range select*/ +/* +* Single ended VREF generator REFSEL range select +*/ #undef DDR_PHY_DX1GCR4_DXREFSSELRANGE_DEFVAL #undef DDR_PHY_DX1GCR4_DXREFSSELRANGE_SHIFT #undef DDR_PHY_DX1GCR4_DXREFSSELRANGE_MASK -#define DDR_PHY_DX1GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C -#define DDR_PHY_DX1GCR4_DXREFSSELRANGE_SHIFT 15 -#define DDR_PHY_DX1GCR4_DXREFSSELRANGE_MASK 0x00008000U +#define DDR_PHY_DX1GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX1GCR4_DXREFSSELRANGE_SHIFT 15 +#define DDR_PHY_DX1GCR4_DXREFSSELRANGE_MASK 0x00008000U -/*Byte Lane Single-End VREF Select*/ +/* +* Byte Lane Single-End VREF Select +*/ #undef DDR_PHY_DX1GCR4_DXREFSSEL_DEFVAL #undef DDR_PHY_DX1GCR4_DXREFSSEL_SHIFT #undef DDR_PHY_DX1GCR4_DXREFSSEL_MASK -#define DDR_PHY_DX1GCR4_DXREFSSEL_DEFVAL 0x0E00003C -#define DDR_PHY_DX1GCR4_DXREFSSEL_SHIFT 8 -#define DDR_PHY_DX1GCR4_DXREFSSEL_MASK 0x00007F00U +#define DDR_PHY_DX1GCR4_DXREFSSEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX1GCR4_DXREFSSEL_SHIFT 8 +#define DDR_PHY_DX1GCR4_DXREFSSEL_MASK 0x00007F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX1GCR4_RESERVED_7_6_DEFVAL #undef DDR_PHY_DX1GCR4_RESERVED_7_6_SHIFT #undef DDR_PHY_DX1GCR4_RESERVED_7_6_MASK -#define DDR_PHY_DX1GCR4_RESERVED_7_6_DEFVAL 0x0E00003C -#define DDR_PHY_DX1GCR4_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_DX1GCR4_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_DX1GCR4_RESERVED_7_6_DEFVAL 0x0E00003C +#define DDR_PHY_DX1GCR4_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX1GCR4_RESERVED_7_6_MASK 0x000000C0U -/*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/ +/* +* VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. +*/ #undef DDR_PHY_DX1GCR4_DXREFIEN_DEFVAL #undef DDR_PHY_DX1GCR4_DXREFIEN_SHIFT #undef DDR_PHY_DX1GCR4_DXREFIEN_MASK -#define DDR_PHY_DX1GCR4_DXREFIEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX1GCR4_DXREFIEN_SHIFT 2 -#define DDR_PHY_DX1GCR4_DXREFIEN_MASK 0x0000003CU +#define DDR_PHY_DX1GCR4_DXREFIEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX1GCR4_DXREFIEN_SHIFT 2 +#define DDR_PHY_DX1GCR4_DXREFIEN_MASK 0x0000003CU -/*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/ +/* +* VRMON control for DQ IO (Single Ended) buffers of a byte lane. +*/ #undef DDR_PHY_DX1GCR4_DXREFIMON_DEFVAL #undef DDR_PHY_DX1GCR4_DXREFIMON_SHIFT #undef DDR_PHY_DX1GCR4_DXREFIMON_MASK -#define DDR_PHY_DX1GCR4_DXREFIMON_DEFVAL 0x0E00003C -#define DDR_PHY_DX1GCR4_DXREFIMON_SHIFT 0 -#define DDR_PHY_DX1GCR4_DXREFIMON_MASK 0x00000003U +#define DDR_PHY_DX1GCR4_DXREFIMON_DEFVAL 0x0E00003C +#define DDR_PHY_DX1GCR4_DXREFIMON_SHIFT 0 +#define DDR_PHY_DX1GCR4_DXREFIMON_MASK 0x00000003U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX1GCR5_RESERVED_31_DEFVAL #undef DDR_PHY_DX1GCR5_RESERVED_31_SHIFT #undef DDR_PHY_DX1GCR5_RESERVED_31_MASK -#define DDR_PHY_DX1GCR5_RESERVED_31_DEFVAL 0x09090909 -#define DDR_PHY_DX1GCR5_RESERVED_31_SHIFT 31 -#define DDR_PHY_DX1GCR5_RESERVED_31_MASK 0x80000000U +#define DDR_PHY_DX1GCR5_RESERVED_31_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR5_RESERVED_31_SHIFT 31 +#define DDR_PHY_DX1GCR5_RESERVED_31_MASK 0x80000000U -/*Byte Lane internal VREF Select for Rank 3*/ +/* +* Byte Lane internal VREF Select for Rank 3 +*/ #undef DDR_PHY_DX1GCR5_DXREFISELR3_DEFVAL #undef DDR_PHY_DX1GCR5_DXREFISELR3_SHIFT #undef DDR_PHY_DX1GCR5_DXREFISELR3_MASK -#define DDR_PHY_DX1GCR5_DXREFISELR3_DEFVAL 0x09090909 -#define DDR_PHY_DX1GCR5_DXREFISELR3_SHIFT 24 -#define DDR_PHY_DX1GCR5_DXREFISELR3_MASK 0x7F000000U +#define DDR_PHY_DX1GCR5_DXREFISELR3_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR5_DXREFISELR3_SHIFT 24 +#define DDR_PHY_DX1GCR5_DXREFISELR3_MASK 0x7F000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX1GCR5_RESERVED_23_DEFVAL #undef DDR_PHY_DX1GCR5_RESERVED_23_SHIFT #undef DDR_PHY_DX1GCR5_RESERVED_23_MASK -#define DDR_PHY_DX1GCR5_RESERVED_23_DEFVAL 0x09090909 -#define DDR_PHY_DX1GCR5_RESERVED_23_SHIFT 23 -#define DDR_PHY_DX1GCR5_RESERVED_23_MASK 0x00800000U +#define DDR_PHY_DX1GCR5_RESERVED_23_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR5_RESERVED_23_SHIFT 23 +#define DDR_PHY_DX1GCR5_RESERVED_23_MASK 0x00800000U -/*Byte Lane internal VREF Select for Rank 2*/ +/* +* Byte Lane internal VREF Select for Rank 2 +*/ #undef DDR_PHY_DX1GCR5_DXREFISELR2_DEFVAL #undef DDR_PHY_DX1GCR5_DXREFISELR2_SHIFT #undef DDR_PHY_DX1GCR5_DXREFISELR2_MASK -#define DDR_PHY_DX1GCR5_DXREFISELR2_DEFVAL 0x09090909 -#define DDR_PHY_DX1GCR5_DXREFISELR2_SHIFT 16 -#define DDR_PHY_DX1GCR5_DXREFISELR2_MASK 0x007F0000U +#define DDR_PHY_DX1GCR5_DXREFISELR2_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR5_DXREFISELR2_SHIFT 16 +#define DDR_PHY_DX1GCR5_DXREFISELR2_MASK 0x007F0000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX1GCR5_RESERVED_15_DEFVAL #undef DDR_PHY_DX1GCR5_RESERVED_15_SHIFT #undef DDR_PHY_DX1GCR5_RESERVED_15_MASK -#define DDR_PHY_DX1GCR5_RESERVED_15_DEFVAL 0x09090909 -#define DDR_PHY_DX1GCR5_RESERVED_15_SHIFT 15 -#define DDR_PHY_DX1GCR5_RESERVED_15_MASK 0x00008000U +#define DDR_PHY_DX1GCR5_RESERVED_15_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR5_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX1GCR5_RESERVED_15_MASK 0x00008000U -/*Byte Lane internal VREF Select for Rank 1*/ +/* +* Byte Lane internal VREF Select for Rank 1 +*/ #undef DDR_PHY_DX1GCR5_DXREFISELR1_DEFVAL #undef DDR_PHY_DX1GCR5_DXREFISELR1_SHIFT #undef DDR_PHY_DX1GCR5_DXREFISELR1_MASK -#define DDR_PHY_DX1GCR5_DXREFISELR1_DEFVAL 0x09090909 -#define DDR_PHY_DX1GCR5_DXREFISELR1_SHIFT 8 -#define DDR_PHY_DX1GCR5_DXREFISELR1_MASK 0x00007F00U +#define DDR_PHY_DX1GCR5_DXREFISELR1_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR5_DXREFISELR1_SHIFT 8 +#define DDR_PHY_DX1GCR5_DXREFISELR1_MASK 0x00007F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX1GCR5_RESERVED_7_DEFVAL #undef DDR_PHY_DX1GCR5_RESERVED_7_SHIFT #undef DDR_PHY_DX1GCR5_RESERVED_7_MASK -#define DDR_PHY_DX1GCR5_RESERVED_7_DEFVAL 0x09090909 -#define DDR_PHY_DX1GCR5_RESERVED_7_SHIFT 7 -#define DDR_PHY_DX1GCR5_RESERVED_7_MASK 0x00000080U +#define DDR_PHY_DX1GCR5_RESERVED_7_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR5_RESERVED_7_SHIFT 7 +#define DDR_PHY_DX1GCR5_RESERVED_7_MASK 0x00000080U -/*Byte Lane internal VREF Select for Rank 0*/ +/* +* Byte Lane internal VREF Select for Rank 0 +*/ #undef DDR_PHY_DX1GCR5_DXREFISELR0_DEFVAL #undef DDR_PHY_DX1GCR5_DXREFISELR0_SHIFT #undef DDR_PHY_DX1GCR5_DXREFISELR0_MASK -#define DDR_PHY_DX1GCR5_DXREFISELR0_DEFVAL 0x09090909 -#define DDR_PHY_DX1GCR5_DXREFISELR0_SHIFT 0 -#define DDR_PHY_DX1GCR5_DXREFISELR0_MASK 0x0000007FU +#define DDR_PHY_DX1GCR5_DXREFISELR0_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR5_DXREFISELR0_SHIFT 0 +#define DDR_PHY_DX1GCR5_DXREFISELR0_MASK 0x0000007FU -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX1GCR6_RESERVED_31_30_DEFVAL #undef DDR_PHY_DX1GCR6_RESERVED_31_30_SHIFT #undef DDR_PHY_DX1GCR6_RESERVED_31_30_MASK -#define DDR_PHY_DX1GCR6_RESERVED_31_30_DEFVAL 0x09090909 -#define DDR_PHY_DX1GCR6_RESERVED_31_30_SHIFT 30 -#define DDR_PHY_DX1GCR6_RESERVED_31_30_MASK 0xC0000000U +#define DDR_PHY_DX1GCR6_RESERVED_31_30_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR6_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX1GCR6_RESERVED_31_30_MASK 0xC0000000U -/*DRAM DQ VREF Select for Rank3*/ +/* +* DRAM DQ VREF Select for Rank3 +*/ #undef DDR_PHY_DX1GCR6_DXDQVREFR3_DEFVAL #undef DDR_PHY_DX1GCR6_DXDQVREFR3_SHIFT #undef DDR_PHY_DX1GCR6_DXDQVREFR3_MASK -#define DDR_PHY_DX1GCR6_DXDQVREFR3_DEFVAL 0x09090909 -#define DDR_PHY_DX1GCR6_DXDQVREFR3_SHIFT 24 -#define DDR_PHY_DX1GCR6_DXDQVREFR3_MASK 0x3F000000U +#define DDR_PHY_DX1GCR6_DXDQVREFR3_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR6_DXDQVREFR3_SHIFT 24 +#define DDR_PHY_DX1GCR6_DXDQVREFR3_MASK 0x3F000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX1GCR6_RESERVED_23_22_DEFVAL #undef DDR_PHY_DX1GCR6_RESERVED_23_22_SHIFT #undef DDR_PHY_DX1GCR6_RESERVED_23_22_MASK -#define DDR_PHY_DX1GCR6_RESERVED_23_22_DEFVAL 0x09090909 -#define DDR_PHY_DX1GCR6_RESERVED_23_22_SHIFT 22 -#define DDR_PHY_DX1GCR6_RESERVED_23_22_MASK 0x00C00000U +#define DDR_PHY_DX1GCR6_RESERVED_23_22_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR6_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX1GCR6_RESERVED_23_22_MASK 0x00C00000U -/*DRAM DQ VREF Select for Rank2*/ +/* +* DRAM DQ VREF Select for Rank2 +*/ #undef DDR_PHY_DX1GCR6_DXDQVREFR2_DEFVAL #undef DDR_PHY_DX1GCR6_DXDQVREFR2_SHIFT #undef DDR_PHY_DX1GCR6_DXDQVREFR2_MASK -#define DDR_PHY_DX1GCR6_DXDQVREFR2_DEFVAL 0x09090909 -#define DDR_PHY_DX1GCR6_DXDQVREFR2_SHIFT 16 -#define DDR_PHY_DX1GCR6_DXDQVREFR2_MASK 0x003F0000U +#define DDR_PHY_DX1GCR6_DXDQVREFR2_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR6_DXDQVREFR2_SHIFT 16 +#define DDR_PHY_DX1GCR6_DXDQVREFR2_MASK 0x003F0000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX1GCR6_RESERVED_15_14_DEFVAL #undef DDR_PHY_DX1GCR6_RESERVED_15_14_SHIFT #undef DDR_PHY_DX1GCR6_RESERVED_15_14_MASK -#define DDR_PHY_DX1GCR6_RESERVED_15_14_DEFVAL 0x09090909 -#define DDR_PHY_DX1GCR6_RESERVED_15_14_SHIFT 14 -#define DDR_PHY_DX1GCR6_RESERVED_15_14_MASK 0x0000C000U +#define DDR_PHY_DX1GCR6_RESERVED_15_14_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR6_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_DX1GCR6_RESERVED_15_14_MASK 0x0000C000U -/*DRAM DQ VREF Select for Rank1*/ +/* +* DRAM DQ VREF Select for Rank1 +*/ #undef DDR_PHY_DX1GCR6_DXDQVREFR1_DEFVAL #undef DDR_PHY_DX1GCR6_DXDQVREFR1_SHIFT #undef DDR_PHY_DX1GCR6_DXDQVREFR1_MASK -#define DDR_PHY_DX1GCR6_DXDQVREFR1_DEFVAL 0x09090909 -#define DDR_PHY_DX1GCR6_DXDQVREFR1_SHIFT 8 -#define DDR_PHY_DX1GCR6_DXDQVREFR1_MASK 0x00003F00U +#define DDR_PHY_DX1GCR6_DXDQVREFR1_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR6_DXDQVREFR1_SHIFT 8 +#define DDR_PHY_DX1GCR6_DXDQVREFR1_MASK 0x00003F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX1GCR6_RESERVED_7_6_DEFVAL #undef DDR_PHY_DX1GCR6_RESERVED_7_6_SHIFT #undef DDR_PHY_DX1GCR6_RESERVED_7_6_MASK -#define DDR_PHY_DX1GCR6_RESERVED_7_6_DEFVAL 0x09090909 -#define DDR_PHY_DX1GCR6_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_DX1GCR6_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_DX1GCR6_RESERVED_7_6_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR6_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX1GCR6_RESERVED_7_6_MASK 0x000000C0U -/*DRAM DQ VREF Select for Rank0*/ +/* +* DRAM DQ VREF Select for Rank0 +*/ #undef DDR_PHY_DX1GCR6_DXDQVREFR0_DEFVAL #undef DDR_PHY_DX1GCR6_DXDQVREFR0_SHIFT #undef DDR_PHY_DX1GCR6_DXDQVREFR0_MASK -#define DDR_PHY_DX1GCR6_DXDQVREFR0_DEFVAL 0x09090909 -#define DDR_PHY_DX1GCR6_DXDQVREFR0_SHIFT 0 -#define DDR_PHY_DX1GCR6_DXDQVREFR0_MASK 0x0000003FU +#define DDR_PHY_DX1GCR6_DXDQVREFR0_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR6_DXDQVREFR0_SHIFT 0 +#define DDR_PHY_DX1GCR6_DXDQVREFR0_MASK 0x0000003FU -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX1LCDLR2_RESERVED_31_25_DEFVAL -#undef DDR_PHY_DX1LCDLR2_RESERVED_31_25_SHIFT -#undef DDR_PHY_DX1LCDLR2_RESERVED_31_25_MASK -#define DDR_PHY_DX1LCDLR2_RESERVED_31_25_DEFVAL 0x00000000 -#define DDR_PHY_DX1LCDLR2_RESERVED_31_25_SHIFT 25 -#define DDR_PHY_DX1LCDLR2_RESERVED_31_25_MASK 0xFE000000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX1LCDLR2_RESERVED_24_16_DEFVAL -#undef DDR_PHY_DX1LCDLR2_RESERVED_24_16_SHIFT -#undef DDR_PHY_DX1LCDLR2_RESERVED_24_16_MASK -#define DDR_PHY_DX1LCDLR2_RESERVED_24_16_DEFVAL 0x00000000 -#define DDR_PHY_DX1LCDLR2_RESERVED_24_16_SHIFT 16 -#define DDR_PHY_DX1LCDLR2_RESERVED_24_16_MASK 0x01FF0000U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX1LCDLR2_RESERVED_15_9_DEFVAL -#undef DDR_PHY_DX1LCDLR2_RESERVED_15_9_SHIFT -#undef DDR_PHY_DX1LCDLR2_RESERVED_15_9_MASK -#define DDR_PHY_DX1LCDLR2_RESERVED_15_9_DEFVAL 0x00000000 -#define DDR_PHY_DX1LCDLR2_RESERVED_15_9_SHIFT 9 -#define DDR_PHY_DX1LCDLR2_RESERVED_15_9_MASK 0x0000FE00U - -/*Read DQS Gating Delay*/ -#undef DDR_PHY_DX1LCDLR2_DQSGD_DEFVAL -#undef DDR_PHY_DX1LCDLR2_DQSGD_SHIFT -#undef DDR_PHY_DX1LCDLR2_DQSGD_MASK -#define DDR_PHY_DX1LCDLR2_DQSGD_DEFVAL 0x00000000 -#define DDR_PHY_DX1LCDLR2_DQSGD_SHIFT 0 -#define DDR_PHY_DX1LCDLR2_DQSGD_MASK 0x000001FFU - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX1GTR0_RESERVED_31_24_DEFVAL -#undef DDR_PHY_DX1GTR0_RESERVED_31_24_SHIFT -#undef DDR_PHY_DX1GTR0_RESERVED_31_24_MASK -#define DDR_PHY_DX1GTR0_RESERVED_31_24_DEFVAL 0x00020000 -#define DDR_PHY_DX1GTR0_RESERVED_31_24_SHIFT 27 -#define DDR_PHY_DX1GTR0_RESERVED_31_24_MASK 0xF8000000U - -/*DQ Write Path Latency Pipeline*/ -#undef DDR_PHY_DX1GTR0_WDQSL_DEFVAL -#undef DDR_PHY_DX1GTR0_WDQSL_SHIFT -#undef DDR_PHY_DX1GTR0_WDQSL_MASK -#define DDR_PHY_DX1GTR0_WDQSL_DEFVAL 0x00020000 -#define DDR_PHY_DX1GTR0_WDQSL_SHIFT 24 -#define DDR_PHY_DX1GTR0_WDQSL_MASK 0x07000000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX1GTR0_RESERVED_23_20_DEFVAL -#undef DDR_PHY_DX1GTR0_RESERVED_23_20_SHIFT -#undef DDR_PHY_DX1GTR0_RESERVED_23_20_MASK -#define DDR_PHY_DX1GTR0_RESERVED_23_20_DEFVAL 0x00020000 -#define DDR_PHY_DX1GTR0_RESERVED_23_20_SHIFT 20 -#define DDR_PHY_DX1GTR0_RESERVED_23_20_MASK 0x00F00000U - -/*Write Leveling System Latency*/ -#undef DDR_PHY_DX1GTR0_WLSL_DEFVAL -#undef DDR_PHY_DX1GTR0_WLSL_SHIFT -#undef DDR_PHY_DX1GTR0_WLSL_MASK -#define DDR_PHY_DX1GTR0_WLSL_DEFVAL 0x00020000 -#define DDR_PHY_DX1GTR0_WLSL_SHIFT 16 -#define DDR_PHY_DX1GTR0_WLSL_MASK 0x000F0000U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX1GTR0_RESERVED_15_13_DEFVAL -#undef DDR_PHY_DX1GTR0_RESERVED_15_13_SHIFT -#undef DDR_PHY_DX1GTR0_RESERVED_15_13_MASK -#define DDR_PHY_DX1GTR0_RESERVED_15_13_DEFVAL 0x00020000 -#define DDR_PHY_DX1GTR0_RESERVED_15_13_SHIFT 13 -#define DDR_PHY_DX1GTR0_RESERVED_15_13_MASK 0x0000E000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX1GTR0_RESERVED_12_8_DEFVAL -#undef DDR_PHY_DX1GTR0_RESERVED_12_8_SHIFT -#undef DDR_PHY_DX1GTR0_RESERVED_12_8_MASK -#define DDR_PHY_DX1GTR0_RESERVED_12_8_DEFVAL 0x00020000 -#define DDR_PHY_DX1GTR0_RESERVED_12_8_SHIFT 8 -#define DDR_PHY_DX1GTR0_RESERVED_12_8_MASK 0x00001F00U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX1GTR0_RESERVED_7_5_DEFVAL -#undef DDR_PHY_DX1GTR0_RESERVED_7_5_SHIFT -#undef DDR_PHY_DX1GTR0_RESERVED_7_5_MASK -#define DDR_PHY_DX1GTR0_RESERVED_7_5_DEFVAL 0x00020000 -#define DDR_PHY_DX1GTR0_RESERVED_7_5_SHIFT 5 -#define DDR_PHY_DX1GTR0_RESERVED_7_5_MASK 0x000000E0U - -/*DQS Gating System Latency*/ -#undef DDR_PHY_DX1GTR0_DGSL_DEFVAL -#undef DDR_PHY_DX1GTR0_DGSL_SHIFT -#undef DDR_PHY_DX1GTR0_DGSL_MASK -#define DDR_PHY_DX1GTR0_DGSL_DEFVAL 0x00020000 -#define DDR_PHY_DX1GTR0_DGSL_SHIFT 0 -#define DDR_PHY_DX1GTR0_DGSL_MASK 0x0000001FU - -/*Calibration Bypass*/ +/* +* Calibration Bypass +*/ #undef DDR_PHY_DX2GCR0_CALBYP_DEFVAL #undef DDR_PHY_DX2GCR0_CALBYP_SHIFT #undef DDR_PHY_DX2GCR0_CALBYP_MASK -#define DDR_PHY_DX2GCR0_CALBYP_DEFVAL 0x40200204 -#define DDR_PHY_DX2GCR0_CALBYP_SHIFT 31 -#define DDR_PHY_DX2GCR0_CALBYP_MASK 0x80000000U +#define DDR_PHY_DX2GCR0_CALBYP_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_CALBYP_SHIFT 31 +#define DDR_PHY_DX2GCR0_CALBYP_MASK 0x80000000U -/*Master Delay Line Enable*/ +/* +* Master Delay Line Enable +*/ #undef DDR_PHY_DX2GCR0_MDLEN_DEFVAL #undef DDR_PHY_DX2GCR0_MDLEN_SHIFT #undef DDR_PHY_DX2GCR0_MDLEN_MASK -#define DDR_PHY_DX2GCR0_MDLEN_DEFVAL 0x40200204 -#define DDR_PHY_DX2GCR0_MDLEN_SHIFT 30 -#define DDR_PHY_DX2GCR0_MDLEN_MASK 0x40000000U +#define DDR_PHY_DX2GCR0_MDLEN_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_MDLEN_SHIFT 30 +#define DDR_PHY_DX2GCR0_MDLEN_MASK 0x40000000U -/*Configurable ODT(TE) Phase Shift*/ +/* +* Configurable ODT(TE) Phase Shift +*/ #undef DDR_PHY_DX2GCR0_CODTSHFT_DEFVAL #undef DDR_PHY_DX2GCR0_CODTSHFT_SHIFT #undef DDR_PHY_DX2GCR0_CODTSHFT_MASK -#define DDR_PHY_DX2GCR0_CODTSHFT_DEFVAL 0x40200204 -#define DDR_PHY_DX2GCR0_CODTSHFT_SHIFT 28 -#define DDR_PHY_DX2GCR0_CODTSHFT_MASK 0x30000000U +#define DDR_PHY_DX2GCR0_CODTSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_CODTSHFT_SHIFT 28 +#define DDR_PHY_DX2GCR0_CODTSHFT_MASK 0x30000000U -/*DQS Duty Cycle Correction*/ +/* +* DQS Duty Cycle Correction +*/ #undef DDR_PHY_DX2GCR0_DQSDCC_DEFVAL #undef DDR_PHY_DX2GCR0_DQSDCC_SHIFT #undef DDR_PHY_DX2GCR0_DQSDCC_MASK -#define DDR_PHY_DX2GCR0_DQSDCC_DEFVAL 0x40200204 -#define DDR_PHY_DX2GCR0_DQSDCC_SHIFT 24 -#define DDR_PHY_DX2GCR0_DQSDCC_MASK 0x0F000000U +#define DDR_PHY_DX2GCR0_DQSDCC_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_DQSDCC_SHIFT 24 +#define DDR_PHY_DX2GCR0_DQSDCC_MASK 0x0F000000U -/*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/ +/* +* Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY +*/ #undef DDR_PHY_DX2GCR0_RDDLY_DEFVAL #undef DDR_PHY_DX2GCR0_RDDLY_SHIFT #undef DDR_PHY_DX2GCR0_RDDLY_MASK -#define DDR_PHY_DX2GCR0_RDDLY_DEFVAL 0x40200204 -#define DDR_PHY_DX2GCR0_RDDLY_SHIFT 20 -#define DDR_PHY_DX2GCR0_RDDLY_MASK 0x00F00000U +#define DDR_PHY_DX2GCR0_RDDLY_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_RDDLY_SHIFT 20 +#define DDR_PHY_DX2GCR0_RDDLY_MASK 0x00F00000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX2GCR0_RESERVED_19_14_DEFVAL #undef DDR_PHY_DX2GCR0_RESERVED_19_14_SHIFT #undef DDR_PHY_DX2GCR0_RESERVED_19_14_MASK -#define DDR_PHY_DX2GCR0_RESERVED_19_14_DEFVAL 0x40200204 -#define DDR_PHY_DX2GCR0_RESERVED_19_14_SHIFT 14 -#define DDR_PHY_DX2GCR0_RESERVED_19_14_MASK 0x000FC000U +#define DDR_PHY_DX2GCR0_RESERVED_19_14_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_RESERVED_19_14_SHIFT 14 +#define DDR_PHY_DX2GCR0_RESERVED_19_14_MASK 0x000FC000U -/*DQSNSE Power Down Receiver*/ +/* +* DQSNSE Power Down Receiver +*/ #undef DDR_PHY_DX2GCR0_DQSNSEPDR_DEFVAL #undef DDR_PHY_DX2GCR0_DQSNSEPDR_SHIFT #undef DDR_PHY_DX2GCR0_DQSNSEPDR_MASK -#define DDR_PHY_DX2GCR0_DQSNSEPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX2GCR0_DQSNSEPDR_SHIFT 13 -#define DDR_PHY_DX2GCR0_DQSNSEPDR_MASK 0x00002000U +#define DDR_PHY_DX2GCR0_DQSNSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_DQSNSEPDR_SHIFT 13 +#define DDR_PHY_DX2GCR0_DQSNSEPDR_MASK 0x00002000U -/*DQSSE Power Down Receiver*/ +/* +* DQSSE Power Down Receiver +*/ #undef DDR_PHY_DX2GCR0_DQSSEPDR_DEFVAL #undef DDR_PHY_DX2GCR0_DQSSEPDR_SHIFT #undef DDR_PHY_DX2GCR0_DQSSEPDR_MASK -#define DDR_PHY_DX2GCR0_DQSSEPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX2GCR0_DQSSEPDR_SHIFT 12 -#define DDR_PHY_DX2GCR0_DQSSEPDR_MASK 0x00001000U +#define DDR_PHY_DX2GCR0_DQSSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_DQSSEPDR_SHIFT 12 +#define DDR_PHY_DX2GCR0_DQSSEPDR_MASK 0x00001000U -/*RTT On Additive Latency*/ +/* +* RTT On Additive Latency +*/ #undef DDR_PHY_DX2GCR0_RTTOAL_DEFVAL #undef DDR_PHY_DX2GCR0_RTTOAL_SHIFT #undef DDR_PHY_DX2GCR0_RTTOAL_MASK -#define DDR_PHY_DX2GCR0_RTTOAL_DEFVAL 0x40200204 -#define DDR_PHY_DX2GCR0_RTTOAL_SHIFT 11 -#define DDR_PHY_DX2GCR0_RTTOAL_MASK 0x00000800U +#define DDR_PHY_DX2GCR0_RTTOAL_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_RTTOAL_SHIFT 11 +#define DDR_PHY_DX2GCR0_RTTOAL_MASK 0x00000800U -/*RTT Output Hold*/ +/* +* RTT Output Hold +*/ #undef DDR_PHY_DX2GCR0_RTTOH_DEFVAL #undef DDR_PHY_DX2GCR0_RTTOH_SHIFT #undef DDR_PHY_DX2GCR0_RTTOH_MASK -#define DDR_PHY_DX2GCR0_RTTOH_DEFVAL 0x40200204 -#define DDR_PHY_DX2GCR0_RTTOH_SHIFT 9 -#define DDR_PHY_DX2GCR0_RTTOH_MASK 0x00000600U +#define DDR_PHY_DX2GCR0_RTTOH_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_RTTOH_SHIFT 9 +#define DDR_PHY_DX2GCR0_RTTOH_MASK 0x00000600U -/*Configurable PDR Phase Shift*/ +/* +* Configurable PDR Phase Shift +*/ #undef DDR_PHY_DX2GCR0_CPDRSHFT_DEFVAL #undef DDR_PHY_DX2GCR0_CPDRSHFT_SHIFT #undef DDR_PHY_DX2GCR0_CPDRSHFT_MASK -#define DDR_PHY_DX2GCR0_CPDRSHFT_DEFVAL 0x40200204 -#define DDR_PHY_DX2GCR0_CPDRSHFT_SHIFT 7 -#define DDR_PHY_DX2GCR0_CPDRSHFT_MASK 0x00000180U +#define DDR_PHY_DX2GCR0_CPDRSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_CPDRSHFT_SHIFT 7 +#define DDR_PHY_DX2GCR0_CPDRSHFT_MASK 0x00000180U -/*DQSR Power Down*/ +/* +* DQSR Power Down +*/ #undef DDR_PHY_DX2GCR0_DQSRPD_DEFVAL #undef DDR_PHY_DX2GCR0_DQSRPD_SHIFT #undef DDR_PHY_DX2GCR0_DQSRPD_MASK -#define DDR_PHY_DX2GCR0_DQSRPD_DEFVAL 0x40200204 -#define DDR_PHY_DX2GCR0_DQSRPD_SHIFT 6 -#define DDR_PHY_DX2GCR0_DQSRPD_MASK 0x00000040U +#define DDR_PHY_DX2GCR0_DQSRPD_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_DQSRPD_SHIFT 6 +#define DDR_PHY_DX2GCR0_DQSRPD_MASK 0x00000040U -/*DQSG Power Down Receiver*/ +/* +* DQSG Power Down Receiver +*/ #undef DDR_PHY_DX2GCR0_DQSGPDR_DEFVAL #undef DDR_PHY_DX2GCR0_DQSGPDR_SHIFT #undef DDR_PHY_DX2GCR0_DQSGPDR_MASK -#define DDR_PHY_DX2GCR0_DQSGPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX2GCR0_DQSGPDR_SHIFT 5 -#define DDR_PHY_DX2GCR0_DQSGPDR_MASK 0x00000020U +#define DDR_PHY_DX2GCR0_DQSGPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_DQSGPDR_SHIFT 5 +#define DDR_PHY_DX2GCR0_DQSGPDR_MASK 0x00000020U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX2GCR0_RESERVED_4_DEFVAL #undef DDR_PHY_DX2GCR0_RESERVED_4_SHIFT #undef DDR_PHY_DX2GCR0_RESERVED_4_MASK -#define DDR_PHY_DX2GCR0_RESERVED_4_DEFVAL 0x40200204 -#define DDR_PHY_DX2GCR0_RESERVED_4_SHIFT 4 -#define DDR_PHY_DX2GCR0_RESERVED_4_MASK 0x00000010U +#define DDR_PHY_DX2GCR0_RESERVED_4_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_RESERVED_4_SHIFT 4 +#define DDR_PHY_DX2GCR0_RESERVED_4_MASK 0x00000010U -/*DQSG On-Die Termination*/ +/* +* DQSG On-Die Termination +*/ #undef DDR_PHY_DX2GCR0_DQSGODT_DEFVAL #undef DDR_PHY_DX2GCR0_DQSGODT_SHIFT #undef DDR_PHY_DX2GCR0_DQSGODT_MASK -#define DDR_PHY_DX2GCR0_DQSGODT_DEFVAL 0x40200204 -#define DDR_PHY_DX2GCR0_DQSGODT_SHIFT 3 -#define DDR_PHY_DX2GCR0_DQSGODT_MASK 0x00000008U +#define DDR_PHY_DX2GCR0_DQSGODT_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_DQSGODT_SHIFT 3 +#define DDR_PHY_DX2GCR0_DQSGODT_MASK 0x00000008U -/*DQSG Output Enable*/ +/* +* DQSG Output Enable +*/ #undef DDR_PHY_DX2GCR0_DQSGOE_DEFVAL #undef DDR_PHY_DX2GCR0_DQSGOE_SHIFT #undef DDR_PHY_DX2GCR0_DQSGOE_MASK -#define DDR_PHY_DX2GCR0_DQSGOE_DEFVAL 0x40200204 -#define DDR_PHY_DX2GCR0_DQSGOE_SHIFT 2 -#define DDR_PHY_DX2GCR0_DQSGOE_MASK 0x00000004U +#define DDR_PHY_DX2GCR0_DQSGOE_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_DQSGOE_SHIFT 2 +#define DDR_PHY_DX2GCR0_DQSGOE_MASK 0x00000004U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX2GCR0_RESERVED_1_0_DEFVAL #undef DDR_PHY_DX2GCR0_RESERVED_1_0_SHIFT #undef DDR_PHY_DX2GCR0_RESERVED_1_0_MASK -#define DDR_PHY_DX2GCR0_RESERVED_1_0_DEFVAL 0x40200204 -#define DDR_PHY_DX2GCR0_RESERVED_1_0_SHIFT 0 -#define DDR_PHY_DX2GCR0_RESERVED_1_0_MASK 0x00000003U +#define DDR_PHY_DX2GCR0_RESERVED_1_0_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_RESERVED_1_0_SHIFT 0 +#define DDR_PHY_DX2GCR0_RESERVED_1_0_MASK 0x00000003U -/*Enables the PDR mode for DQ[7:0]*/ +/* +* Enables the PDR mode for DQ[7:0] +*/ #undef DDR_PHY_DX2GCR1_DXPDRMODE_DEFVAL #undef DDR_PHY_DX2GCR1_DXPDRMODE_SHIFT #undef DDR_PHY_DX2GCR1_DXPDRMODE_MASK -#define DDR_PHY_DX2GCR1_DXPDRMODE_DEFVAL 0x00007FFF -#define DDR_PHY_DX2GCR1_DXPDRMODE_SHIFT 16 -#define DDR_PHY_DX2GCR1_DXPDRMODE_MASK 0xFFFF0000U +#define DDR_PHY_DX2GCR1_DXPDRMODE_DEFVAL 0x00007FFF +#define DDR_PHY_DX2GCR1_DXPDRMODE_SHIFT 16 +#define DDR_PHY_DX2GCR1_DXPDRMODE_MASK 0xFFFF0000U -/*Reserved. Returns zeroes on reads.*/ +/* +* Reserved. Returns zeroes on reads. +*/ #undef DDR_PHY_DX2GCR1_RESERVED_15_DEFVAL #undef DDR_PHY_DX2GCR1_RESERVED_15_SHIFT #undef DDR_PHY_DX2GCR1_RESERVED_15_MASK -#define DDR_PHY_DX2GCR1_RESERVED_15_DEFVAL 0x00007FFF -#define DDR_PHY_DX2GCR1_RESERVED_15_SHIFT 15 -#define DDR_PHY_DX2GCR1_RESERVED_15_MASK 0x00008000U +#define DDR_PHY_DX2GCR1_RESERVED_15_DEFVAL 0x00007FFF +#define DDR_PHY_DX2GCR1_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX2GCR1_RESERVED_15_MASK 0x00008000U -/*Select the delayed or non-delayed read data strobe #*/ +/* +* Select the delayed or non-delayed read data strobe # +*/ #undef DDR_PHY_DX2GCR1_QSNSEL_DEFVAL #undef DDR_PHY_DX2GCR1_QSNSEL_SHIFT #undef DDR_PHY_DX2GCR1_QSNSEL_MASK -#define DDR_PHY_DX2GCR1_QSNSEL_DEFVAL 0x00007FFF -#define DDR_PHY_DX2GCR1_QSNSEL_SHIFT 14 -#define DDR_PHY_DX2GCR1_QSNSEL_MASK 0x00004000U +#define DDR_PHY_DX2GCR1_QSNSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX2GCR1_QSNSEL_SHIFT 14 +#define DDR_PHY_DX2GCR1_QSNSEL_MASK 0x00004000U -/*Select the delayed or non-delayed read data strobe*/ +/* +* Select the delayed or non-delayed read data strobe +*/ #undef DDR_PHY_DX2GCR1_QSSEL_DEFVAL #undef DDR_PHY_DX2GCR1_QSSEL_SHIFT #undef DDR_PHY_DX2GCR1_QSSEL_MASK -#define DDR_PHY_DX2GCR1_QSSEL_DEFVAL 0x00007FFF -#define DDR_PHY_DX2GCR1_QSSEL_SHIFT 13 -#define DDR_PHY_DX2GCR1_QSSEL_MASK 0x00002000U +#define DDR_PHY_DX2GCR1_QSSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX2GCR1_QSSEL_SHIFT 13 +#define DDR_PHY_DX2GCR1_QSSEL_MASK 0x00002000U -/*Enables Read Data Strobe in a byte lane*/ +/* +* Enables Read Data Strobe in a byte lane +*/ #undef DDR_PHY_DX2GCR1_OEEN_DEFVAL #undef DDR_PHY_DX2GCR1_OEEN_SHIFT #undef DDR_PHY_DX2GCR1_OEEN_MASK -#define DDR_PHY_DX2GCR1_OEEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX2GCR1_OEEN_SHIFT 12 -#define DDR_PHY_DX2GCR1_OEEN_MASK 0x00001000U +#define DDR_PHY_DX2GCR1_OEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX2GCR1_OEEN_SHIFT 12 +#define DDR_PHY_DX2GCR1_OEEN_MASK 0x00001000U -/*Enables PDR in a byte lane*/ +/* +* Enables PDR in a byte lane +*/ #undef DDR_PHY_DX2GCR1_PDREN_DEFVAL #undef DDR_PHY_DX2GCR1_PDREN_SHIFT #undef DDR_PHY_DX2GCR1_PDREN_MASK -#define DDR_PHY_DX2GCR1_PDREN_DEFVAL 0x00007FFF -#define DDR_PHY_DX2GCR1_PDREN_SHIFT 11 -#define DDR_PHY_DX2GCR1_PDREN_MASK 0x00000800U +#define DDR_PHY_DX2GCR1_PDREN_DEFVAL 0x00007FFF +#define DDR_PHY_DX2GCR1_PDREN_SHIFT 11 +#define DDR_PHY_DX2GCR1_PDREN_MASK 0x00000800U -/*Enables ODT/TE in a byte lane*/ +/* +* Enables ODT/TE in a byte lane +*/ #undef DDR_PHY_DX2GCR1_TEEN_DEFVAL #undef DDR_PHY_DX2GCR1_TEEN_SHIFT #undef DDR_PHY_DX2GCR1_TEEN_MASK -#define DDR_PHY_DX2GCR1_TEEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX2GCR1_TEEN_SHIFT 10 -#define DDR_PHY_DX2GCR1_TEEN_MASK 0x00000400U +#define DDR_PHY_DX2GCR1_TEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX2GCR1_TEEN_SHIFT 10 +#define DDR_PHY_DX2GCR1_TEEN_MASK 0x00000400U -/*Enables Write Data strobe in a byte lane*/ +/* +* Enables Write Data strobe in a byte lane +*/ #undef DDR_PHY_DX2GCR1_DSEN_DEFVAL #undef DDR_PHY_DX2GCR1_DSEN_SHIFT #undef DDR_PHY_DX2GCR1_DSEN_MASK -#define DDR_PHY_DX2GCR1_DSEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX2GCR1_DSEN_SHIFT 9 -#define DDR_PHY_DX2GCR1_DSEN_MASK 0x00000200U +#define DDR_PHY_DX2GCR1_DSEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX2GCR1_DSEN_SHIFT 9 +#define DDR_PHY_DX2GCR1_DSEN_MASK 0x00000200U -/*Enables DM pin in a byte lane*/ +/* +* Enables DM pin in a byte lane +*/ #undef DDR_PHY_DX2GCR1_DMEN_DEFVAL #undef DDR_PHY_DX2GCR1_DMEN_SHIFT #undef DDR_PHY_DX2GCR1_DMEN_MASK -#define DDR_PHY_DX2GCR1_DMEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX2GCR1_DMEN_SHIFT 8 -#define DDR_PHY_DX2GCR1_DMEN_MASK 0x00000100U +#define DDR_PHY_DX2GCR1_DMEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX2GCR1_DMEN_SHIFT 8 +#define DDR_PHY_DX2GCR1_DMEN_MASK 0x00000100U -/*Enables DQ corresponding to each bit in a byte*/ +/* +* Enables DQ corresponding to each bit in a byte +*/ #undef DDR_PHY_DX2GCR1_DQEN_DEFVAL #undef DDR_PHY_DX2GCR1_DQEN_SHIFT #undef DDR_PHY_DX2GCR1_DQEN_MASK -#define DDR_PHY_DX2GCR1_DQEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX2GCR1_DQEN_SHIFT 0 -#define DDR_PHY_DX2GCR1_DQEN_MASK 0x000000FFU +#define DDR_PHY_DX2GCR1_DQEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX2GCR1_DQEN_SHIFT 0 +#define DDR_PHY_DX2GCR1_DQEN_MASK 0x000000FFU -/*Byte lane VREF IOM (Used only by D4MU IOs)*/ +/* +* Byte lane VREF IOM (Used only by D4MU IOs) +*/ #undef DDR_PHY_DX2GCR4_RESERVED_31_29_DEFVAL #undef DDR_PHY_DX2GCR4_RESERVED_31_29_SHIFT #undef DDR_PHY_DX2GCR4_RESERVED_31_29_MASK -#define DDR_PHY_DX2GCR4_RESERVED_31_29_DEFVAL 0x0E00003C -#define DDR_PHY_DX2GCR4_RESERVED_31_29_SHIFT 29 -#define DDR_PHY_DX2GCR4_RESERVED_31_29_MASK 0xE0000000U +#define DDR_PHY_DX2GCR4_RESERVED_31_29_DEFVAL 0x0E00003C +#define DDR_PHY_DX2GCR4_RESERVED_31_29_SHIFT 29 +#define DDR_PHY_DX2GCR4_RESERVED_31_29_MASK 0xE0000000U -/*Byte Lane VREF Pad Enable*/ +/* +* Byte Lane VREF Pad Enable +*/ #undef DDR_PHY_DX2GCR4_DXREFPEN_DEFVAL #undef DDR_PHY_DX2GCR4_DXREFPEN_SHIFT #undef DDR_PHY_DX2GCR4_DXREFPEN_MASK -#define DDR_PHY_DX2GCR4_DXREFPEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX2GCR4_DXREFPEN_SHIFT 28 -#define DDR_PHY_DX2GCR4_DXREFPEN_MASK 0x10000000U +#define DDR_PHY_DX2GCR4_DXREFPEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX2GCR4_DXREFPEN_SHIFT 28 +#define DDR_PHY_DX2GCR4_DXREFPEN_MASK 0x10000000U -/*Byte Lane Internal VREF Enable*/ +/* +* Byte Lane Internal VREF Enable +*/ #undef DDR_PHY_DX2GCR4_DXREFEEN_DEFVAL #undef DDR_PHY_DX2GCR4_DXREFEEN_SHIFT #undef DDR_PHY_DX2GCR4_DXREFEEN_MASK -#define DDR_PHY_DX2GCR4_DXREFEEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX2GCR4_DXREFEEN_SHIFT 26 -#define DDR_PHY_DX2GCR4_DXREFEEN_MASK 0x0C000000U +#define DDR_PHY_DX2GCR4_DXREFEEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX2GCR4_DXREFEEN_SHIFT 26 +#define DDR_PHY_DX2GCR4_DXREFEEN_MASK 0x0C000000U -/*Byte Lane Single-End VREF Enable*/ +/* +* Byte Lane Single-End VREF Enable +*/ #undef DDR_PHY_DX2GCR4_DXREFSEN_DEFVAL #undef DDR_PHY_DX2GCR4_DXREFSEN_SHIFT #undef DDR_PHY_DX2GCR4_DXREFSEN_MASK -#define DDR_PHY_DX2GCR4_DXREFSEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX2GCR4_DXREFSEN_SHIFT 25 -#define DDR_PHY_DX2GCR4_DXREFSEN_MASK 0x02000000U +#define DDR_PHY_DX2GCR4_DXREFSEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX2GCR4_DXREFSEN_SHIFT 25 +#define DDR_PHY_DX2GCR4_DXREFSEN_MASK 0x02000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX2GCR4_RESERVED_24_DEFVAL #undef DDR_PHY_DX2GCR4_RESERVED_24_SHIFT #undef DDR_PHY_DX2GCR4_RESERVED_24_MASK -#define DDR_PHY_DX2GCR4_RESERVED_24_DEFVAL 0x0E00003C -#define DDR_PHY_DX2GCR4_RESERVED_24_SHIFT 24 -#define DDR_PHY_DX2GCR4_RESERVED_24_MASK 0x01000000U +#define DDR_PHY_DX2GCR4_RESERVED_24_DEFVAL 0x0E00003C +#define DDR_PHY_DX2GCR4_RESERVED_24_SHIFT 24 +#define DDR_PHY_DX2GCR4_RESERVED_24_MASK 0x01000000U -/*External VREF generator REFSEL range select*/ +/* +* External VREF generator REFSEL range select +*/ #undef DDR_PHY_DX2GCR4_DXREFESELRANGE_DEFVAL #undef DDR_PHY_DX2GCR4_DXREFESELRANGE_SHIFT #undef DDR_PHY_DX2GCR4_DXREFESELRANGE_MASK -#define DDR_PHY_DX2GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C -#define DDR_PHY_DX2GCR4_DXREFESELRANGE_SHIFT 23 -#define DDR_PHY_DX2GCR4_DXREFESELRANGE_MASK 0x00800000U +#define DDR_PHY_DX2GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX2GCR4_DXREFESELRANGE_SHIFT 23 +#define DDR_PHY_DX2GCR4_DXREFESELRANGE_MASK 0x00800000U -/*Byte Lane External VREF Select*/ +/* +* Byte Lane External VREF Select +*/ #undef DDR_PHY_DX2GCR4_DXREFESEL_DEFVAL #undef DDR_PHY_DX2GCR4_DXREFESEL_SHIFT #undef DDR_PHY_DX2GCR4_DXREFESEL_MASK -#define DDR_PHY_DX2GCR4_DXREFESEL_DEFVAL 0x0E00003C -#define DDR_PHY_DX2GCR4_DXREFESEL_SHIFT 16 -#define DDR_PHY_DX2GCR4_DXREFESEL_MASK 0x007F0000U +#define DDR_PHY_DX2GCR4_DXREFESEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX2GCR4_DXREFESEL_SHIFT 16 +#define DDR_PHY_DX2GCR4_DXREFESEL_MASK 0x007F0000U -/*Single ended VREF generator REFSEL range select*/ +/* +* Single ended VREF generator REFSEL range select +*/ #undef DDR_PHY_DX2GCR4_DXREFSSELRANGE_DEFVAL #undef DDR_PHY_DX2GCR4_DXREFSSELRANGE_SHIFT #undef DDR_PHY_DX2GCR4_DXREFSSELRANGE_MASK -#define DDR_PHY_DX2GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C -#define DDR_PHY_DX2GCR4_DXREFSSELRANGE_SHIFT 15 -#define DDR_PHY_DX2GCR4_DXREFSSELRANGE_MASK 0x00008000U +#define DDR_PHY_DX2GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX2GCR4_DXREFSSELRANGE_SHIFT 15 +#define DDR_PHY_DX2GCR4_DXREFSSELRANGE_MASK 0x00008000U -/*Byte Lane Single-End VREF Select*/ +/* +* Byte Lane Single-End VREF Select +*/ #undef DDR_PHY_DX2GCR4_DXREFSSEL_DEFVAL #undef DDR_PHY_DX2GCR4_DXREFSSEL_SHIFT #undef DDR_PHY_DX2GCR4_DXREFSSEL_MASK -#define DDR_PHY_DX2GCR4_DXREFSSEL_DEFVAL 0x0E00003C -#define DDR_PHY_DX2GCR4_DXREFSSEL_SHIFT 8 -#define DDR_PHY_DX2GCR4_DXREFSSEL_MASK 0x00007F00U +#define DDR_PHY_DX2GCR4_DXREFSSEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX2GCR4_DXREFSSEL_SHIFT 8 +#define DDR_PHY_DX2GCR4_DXREFSSEL_MASK 0x00007F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX2GCR4_RESERVED_7_6_DEFVAL #undef DDR_PHY_DX2GCR4_RESERVED_7_6_SHIFT #undef DDR_PHY_DX2GCR4_RESERVED_7_6_MASK -#define DDR_PHY_DX2GCR4_RESERVED_7_6_DEFVAL 0x0E00003C -#define DDR_PHY_DX2GCR4_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_DX2GCR4_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_DX2GCR4_RESERVED_7_6_DEFVAL 0x0E00003C +#define DDR_PHY_DX2GCR4_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX2GCR4_RESERVED_7_6_MASK 0x000000C0U -/*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/ +/* +* VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. +*/ #undef DDR_PHY_DX2GCR4_DXREFIEN_DEFVAL #undef DDR_PHY_DX2GCR4_DXREFIEN_SHIFT #undef DDR_PHY_DX2GCR4_DXREFIEN_MASK -#define DDR_PHY_DX2GCR4_DXREFIEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX2GCR4_DXREFIEN_SHIFT 2 -#define DDR_PHY_DX2GCR4_DXREFIEN_MASK 0x0000003CU +#define DDR_PHY_DX2GCR4_DXREFIEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX2GCR4_DXREFIEN_SHIFT 2 +#define DDR_PHY_DX2GCR4_DXREFIEN_MASK 0x0000003CU -/*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/ +/* +* VRMON control for DQ IO (Single Ended) buffers of a byte lane. +*/ #undef DDR_PHY_DX2GCR4_DXREFIMON_DEFVAL #undef DDR_PHY_DX2GCR4_DXREFIMON_SHIFT #undef DDR_PHY_DX2GCR4_DXREFIMON_MASK -#define DDR_PHY_DX2GCR4_DXREFIMON_DEFVAL 0x0E00003C -#define DDR_PHY_DX2GCR4_DXREFIMON_SHIFT 0 -#define DDR_PHY_DX2GCR4_DXREFIMON_MASK 0x00000003U +#define DDR_PHY_DX2GCR4_DXREFIMON_DEFVAL 0x0E00003C +#define DDR_PHY_DX2GCR4_DXREFIMON_SHIFT 0 +#define DDR_PHY_DX2GCR4_DXREFIMON_MASK 0x00000003U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX2GCR5_RESERVED_31_DEFVAL #undef DDR_PHY_DX2GCR5_RESERVED_31_SHIFT #undef DDR_PHY_DX2GCR5_RESERVED_31_MASK -#define DDR_PHY_DX2GCR5_RESERVED_31_DEFVAL 0x09090909 -#define DDR_PHY_DX2GCR5_RESERVED_31_SHIFT 31 -#define DDR_PHY_DX2GCR5_RESERVED_31_MASK 0x80000000U +#define DDR_PHY_DX2GCR5_RESERVED_31_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR5_RESERVED_31_SHIFT 31 +#define DDR_PHY_DX2GCR5_RESERVED_31_MASK 0x80000000U -/*Byte Lane internal VREF Select for Rank 3*/ +/* +* Byte Lane internal VREF Select for Rank 3 +*/ #undef DDR_PHY_DX2GCR5_DXREFISELR3_DEFVAL #undef DDR_PHY_DX2GCR5_DXREFISELR3_SHIFT #undef DDR_PHY_DX2GCR5_DXREFISELR3_MASK -#define DDR_PHY_DX2GCR5_DXREFISELR3_DEFVAL 0x09090909 -#define DDR_PHY_DX2GCR5_DXREFISELR3_SHIFT 24 -#define DDR_PHY_DX2GCR5_DXREFISELR3_MASK 0x7F000000U +#define DDR_PHY_DX2GCR5_DXREFISELR3_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR5_DXREFISELR3_SHIFT 24 +#define DDR_PHY_DX2GCR5_DXREFISELR3_MASK 0x7F000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX2GCR5_RESERVED_23_DEFVAL #undef DDR_PHY_DX2GCR5_RESERVED_23_SHIFT #undef DDR_PHY_DX2GCR5_RESERVED_23_MASK -#define DDR_PHY_DX2GCR5_RESERVED_23_DEFVAL 0x09090909 -#define DDR_PHY_DX2GCR5_RESERVED_23_SHIFT 23 -#define DDR_PHY_DX2GCR5_RESERVED_23_MASK 0x00800000U +#define DDR_PHY_DX2GCR5_RESERVED_23_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR5_RESERVED_23_SHIFT 23 +#define DDR_PHY_DX2GCR5_RESERVED_23_MASK 0x00800000U -/*Byte Lane internal VREF Select for Rank 2*/ +/* +* Byte Lane internal VREF Select for Rank 2 +*/ #undef DDR_PHY_DX2GCR5_DXREFISELR2_DEFVAL #undef DDR_PHY_DX2GCR5_DXREFISELR2_SHIFT #undef DDR_PHY_DX2GCR5_DXREFISELR2_MASK -#define DDR_PHY_DX2GCR5_DXREFISELR2_DEFVAL 0x09090909 -#define DDR_PHY_DX2GCR5_DXREFISELR2_SHIFT 16 -#define DDR_PHY_DX2GCR5_DXREFISELR2_MASK 0x007F0000U +#define DDR_PHY_DX2GCR5_DXREFISELR2_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR5_DXREFISELR2_SHIFT 16 +#define DDR_PHY_DX2GCR5_DXREFISELR2_MASK 0x007F0000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX2GCR5_RESERVED_15_DEFVAL #undef DDR_PHY_DX2GCR5_RESERVED_15_SHIFT #undef DDR_PHY_DX2GCR5_RESERVED_15_MASK -#define DDR_PHY_DX2GCR5_RESERVED_15_DEFVAL 0x09090909 -#define DDR_PHY_DX2GCR5_RESERVED_15_SHIFT 15 -#define DDR_PHY_DX2GCR5_RESERVED_15_MASK 0x00008000U +#define DDR_PHY_DX2GCR5_RESERVED_15_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR5_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX2GCR5_RESERVED_15_MASK 0x00008000U -/*Byte Lane internal VREF Select for Rank 1*/ +/* +* Byte Lane internal VREF Select for Rank 1 +*/ #undef DDR_PHY_DX2GCR5_DXREFISELR1_DEFVAL #undef DDR_PHY_DX2GCR5_DXREFISELR1_SHIFT #undef DDR_PHY_DX2GCR5_DXREFISELR1_MASK -#define DDR_PHY_DX2GCR5_DXREFISELR1_DEFVAL 0x09090909 -#define DDR_PHY_DX2GCR5_DXREFISELR1_SHIFT 8 -#define DDR_PHY_DX2GCR5_DXREFISELR1_MASK 0x00007F00U +#define DDR_PHY_DX2GCR5_DXREFISELR1_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR5_DXREFISELR1_SHIFT 8 +#define DDR_PHY_DX2GCR5_DXREFISELR1_MASK 0x00007F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX2GCR5_RESERVED_7_DEFVAL #undef DDR_PHY_DX2GCR5_RESERVED_7_SHIFT #undef DDR_PHY_DX2GCR5_RESERVED_7_MASK -#define DDR_PHY_DX2GCR5_RESERVED_7_DEFVAL 0x09090909 -#define DDR_PHY_DX2GCR5_RESERVED_7_SHIFT 7 -#define DDR_PHY_DX2GCR5_RESERVED_7_MASK 0x00000080U +#define DDR_PHY_DX2GCR5_RESERVED_7_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR5_RESERVED_7_SHIFT 7 +#define DDR_PHY_DX2GCR5_RESERVED_7_MASK 0x00000080U -/*Byte Lane internal VREF Select for Rank 0*/ +/* +* Byte Lane internal VREF Select for Rank 0 +*/ #undef DDR_PHY_DX2GCR5_DXREFISELR0_DEFVAL #undef DDR_PHY_DX2GCR5_DXREFISELR0_SHIFT #undef DDR_PHY_DX2GCR5_DXREFISELR0_MASK -#define DDR_PHY_DX2GCR5_DXREFISELR0_DEFVAL 0x09090909 -#define DDR_PHY_DX2GCR5_DXREFISELR0_SHIFT 0 -#define DDR_PHY_DX2GCR5_DXREFISELR0_MASK 0x0000007FU +#define DDR_PHY_DX2GCR5_DXREFISELR0_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR5_DXREFISELR0_SHIFT 0 +#define DDR_PHY_DX2GCR5_DXREFISELR0_MASK 0x0000007FU -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX2GCR6_RESERVED_31_30_DEFVAL #undef DDR_PHY_DX2GCR6_RESERVED_31_30_SHIFT #undef DDR_PHY_DX2GCR6_RESERVED_31_30_MASK -#define DDR_PHY_DX2GCR6_RESERVED_31_30_DEFVAL 0x09090909 -#define DDR_PHY_DX2GCR6_RESERVED_31_30_SHIFT 30 -#define DDR_PHY_DX2GCR6_RESERVED_31_30_MASK 0xC0000000U +#define DDR_PHY_DX2GCR6_RESERVED_31_30_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR6_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX2GCR6_RESERVED_31_30_MASK 0xC0000000U -/*DRAM DQ VREF Select for Rank3*/ +/* +* DRAM DQ VREF Select for Rank3 +*/ #undef DDR_PHY_DX2GCR6_DXDQVREFR3_DEFVAL #undef DDR_PHY_DX2GCR6_DXDQVREFR3_SHIFT #undef DDR_PHY_DX2GCR6_DXDQVREFR3_MASK -#define DDR_PHY_DX2GCR6_DXDQVREFR3_DEFVAL 0x09090909 -#define DDR_PHY_DX2GCR6_DXDQVREFR3_SHIFT 24 -#define DDR_PHY_DX2GCR6_DXDQVREFR3_MASK 0x3F000000U +#define DDR_PHY_DX2GCR6_DXDQVREFR3_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR6_DXDQVREFR3_SHIFT 24 +#define DDR_PHY_DX2GCR6_DXDQVREFR3_MASK 0x3F000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX2GCR6_RESERVED_23_22_DEFVAL #undef DDR_PHY_DX2GCR6_RESERVED_23_22_SHIFT #undef DDR_PHY_DX2GCR6_RESERVED_23_22_MASK -#define DDR_PHY_DX2GCR6_RESERVED_23_22_DEFVAL 0x09090909 -#define DDR_PHY_DX2GCR6_RESERVED_23_22_SHIFT 22 -#define DDR_PHY_DX2GCR6_RESERVED_23_22_MASK 0x00C00000U +#define DDR_PHY_DX2GCR6_RESERVED_23_22_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR6_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX2GCR6_RESERVED_23_22_MASK 0x00C00000U -/*DRAM DQ VREF Select for Rank2*/ +/* +* DRAM DQ VREF Select for Rank2 +*/ #undef DDR_PHY_DX2GCR6_DXDQVREFR2_DEFVAL #undef DDR_PHY_DX2GCR6_DXDQVREFR2_SHIFT #undef DDR_PHY_DX2GCR6_DXDQVREFR2_MASK -#define DDR_PHY_DX2GCR6_DXDQVREFR2_DEFVAL 0x09090909 -#define DDR_PHY_DX2GCR6_DXDQVREFR2_SHIFT 16 -#define DDR_PHY_DX2GCR6_DXDQVREFR2_MASK 0x003F0000U +#define DDR_PHY_DX2GCR6_DXDQVREFR2_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR6_DXDQVREFR2_SHIFT 16 +#define DDR_PHY_DX2GCR6_DXDQVREFR2_MASK 0x003F0000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX2GCR6_RESERVED_15_14_DEFVAL #undef DDR_PHY_DX2GCR6_RESERVED_15_14_SHIFT #undef DDR_PHY_DX2GCR6_RESERVED_15_14_MASK -#define DDR_PHY_DX2GCR6_RESERVED_15_14_DEFVAL 0x09090909 -#define DDR_PHY_DX2GCR6_RESERVED_15_14_SHIFT 14 -#define DDR_PHY_DX2GCR6_RESERVED_15_14_MASK 0x0000C000U +#define DDR_PHY_DX2GCR6_RESERVED_15_14_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR6_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_DX2GCR6_RESERVED_15_14_MASK 0x0000C000U -/*DRAM DQ VREF Select for Rank1*/ +/* +* DRAM DQ VREF Select for Rank1 +*/ #undef DDR_PHY_DX2GCR6_DXDQVREFR1_DEFVAL #undef DDR_PHY_DX2GCR6_DXDQVREFR1_SHIFT #undef DDR_PHY_DX2GCR6_DXDQVREFR1_MASK -#define DDR_PHY_DX2GCR6_DXDQVREFR1_DEFVAL 0x09090909 -#define DDR_PHY_DX2GCR6_DXDQVREFR1_SHIFT 8 -#define DDR_PHY_DX2GCR6_DXDQVREFR1_MASK 0x00003F00U +#define DDR_PHY_DX2GCR6_DXDQVREFR1_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR6_DXDQVREFR1_SHIFT 8 +#define DDR_PHY_DX2GCR6_DXDQVREFR1_MASK 0x00003F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX2GCR6_RESERVED_7_6_DEFVAL #undef DDR_PHY_DX2GCR6_RESERVED_7_6_SHIFT #undef DDR_PHY_DX2GCR6_RESERVED_7_6_MASK -#define DDR_PHY_DX2GCR6_RESERVED_7_6_DEFVAL 0x09090909 -#define DDR_PHY_DX2GCR6_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_DX2GCR6_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_DX2GCR6_RESERVED_7_6_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR6_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX2GCR6_RESERVED_7_6_MASK 0x000000C0U -/*DRAM DQ VREF Select for Rank0*/ +/* +* DRAM DQ VREF Select for Rank0 +*/ #undef DDR_PHY_DX2GCR6_DXDQVREFR0_DEFVAL #undef DDR_PHY_DX2GCR6_DXDQVREFR0_SHIFT #undef DDR_PHY_DX2GCR6_DXDQVREFR0_MASK -#define DDR_PHY_DX2GCR6_DXDQVREFR0_DEFVAL 0x09090909 -#define DDR_PHY_DX2GCR6_DXDQVREFR0_SHIFT 0 -#define DDR_PHY_DX2GCR6_DXDQVREFR0_MASK 0x0000003FU +#define DDR_PHY_DX2GCR6_DXDQVREFR0_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR6_DXDQVREFR0_SHIFT 0 +#define DDR_PHY_DX2GCR6_DXDQVREFR0_MASK 0x0000003FU -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX2LCDLR2_RESERVED_31_25_DEFVAL -#undef DDR_PHY_DX2LCDLR2_RESERVED_31_25_SHIFT -#undef DDR_PHY_DX2LCDLR2_RESERVED_31_25_MASK -#define DDR_PHY_DX2LCDLR2_RESERVED_31_25_DEFVAL 0x00000000 -#define DDR_PHY_DX2LCDLR2_RESERVED_31_25_SHIFT 25 -#define DDR_PHY_DX2LCDLR2_RESERVED_31_25_MASK 0xFE000000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX2LCDLR2_RESERVED_24_16_DEFVAL -#undef DDR_PHY_DX2LCDLR2_RESERVED_24_16_SHIFT -#undef DDR_PHY_DX2LCDLR2_RESERVED_24_16_MASK -#define DDR_PHY_DX2LCDLR2_RESERVED_24_16_DEFVAL 0x00000000 -#define DDR_PHY_DX2LCDLR2_RESERVED_24_16_SHIFT 16 -#define DDR_PHY_DX2LCDLR2_RESERVED_24_16_MASK 0x01FF0000U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX2LCDLR2_RESERVED_15_9_DEFVAL -#undef DDR_PHY_DX2LCDLR2_RESERVED_15_9_SHIFT -#undef DDR_PHY_DX2LCDLR2_RESERVED_15_9_MASK -#define DDR_PHY_DX2LCDLR2_RESERVED_15_9_DEFVAL 0x00000000 -#define DDR_PHY_DX2LCDLR2_RESERVED_15_9_SHIFT 9 -#define DDR_PHY_DX2LCDLR2_RESERVED_15_9_MASK 0x0000FE00U - -/*Read DQS Gating Delay*/ -#undef DDR_PHY_DX2LCDLR2_DQSGD_DEFVAL -#undef DDR_PHY_DX2LCDLR2_DQSGD_SHIFT -#undef DDR_PHY_DX2LCDLR2_DQSGD_MASK -#define DDR_PHY_DX2LCDLR2_DQSGD_DEFVAL 0x00000000 -#define DDR_PHY_DX2LCDLR2_DQSGD_SHIFT 0 -#define DDR_PHY_DX2LCDLR2_DQSGD_MASK 0x000001FFU - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX2GTR0_RESERVED_31_24_DEFVAL -#undef DDR_PHY_DX2GTR0_RESERVED_31_24_SHIFT -#undef DDR_PHY_DX2GTR0_RESERVED_31_24_MASK -#define DDR_PHY_DX2GTR0_RESERVED_31_24_DEFVAL 0x00020000 -#define DDR_PHY_DX2GTR0_RESERVED_31_24_SHIFT 27 -#define DDR_PHY_DX2GTR0_RESERVED_31_24_MASK 0xF8000000U - -/*DQ Write Path Latency Pipeline*/ -#undef DDR_PHY_DX2GTR0_WDQSL_DEFVAL -#undef DDR_PHY_DX2GTR0_WDQSL_SHIFT -#undef DDR_PHY_DX2GTR0_WDQSL_MASK -#define DDR_PHY_DX2GTR0_WDQSL_DEFVAL 0x00020000 -#define DDR_PHY_DX2GTR0_WDQSL_SHIFT 24 -#define DDR_PHY_DX2GTR0_WDQSL_MASK 0x07000000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX2GTR0_RESERVED_23_20_DEFVAL -#undef DDR_PHY_DX2GTR0_RESERVED_23_20_SHIFT -#undef DDR_PHY_DX2GTR0_RESERVED_23_20_MASK -#define DDR_PHY_DX2GTR0_RESERVED_23_20_DEFVAL 0x00020000 -#define DDR_PHY_DX2GTR0_RESERVED_23_20_SHIFT 20 -#define DDR_PHY_DX2GTR0_RESERVED_23_20_MASK 0x00F00000U - -/*Write Leveling System Latency*/ -#undef DDR_PHY_DX2GTR0_WLSL_DEFVAL -#undef DDR_PHY_DX2GTR0_WLSL_SHIFT -#undef DDR_PHY_DX2GTR0_WLSL_MASK -#define DDR_PHY_DX2GTR0_WLSL_DEFVAL 0x00020000 -#define DDR_PHY_DX2GTR0_WLSL_SHIFT 16 -#define DDR_PHY_DX2GTR0_WLSL_MASK 0x000F0000U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX2GTR0_RESERVED_15_13_DEFVAL -#undef DDR_PHY_DX2GTR0_RESERVED_15_13_SHIFT -#undef DDR_PHY_DX2GTR0_RESERVED_15_13_MASK -#define DDR_PHY_DX2GTR0_RESERVED_15_13_DEFVAL 0x00020000 -#define DDR_PHY_DX2GTR0_RESERVED_15_13_SHIFT 13 -#define DDR_PHY_DX2GTR0_RESERVED_15_13_MASK 0x0000E000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX2GTR0_RESERVED_12_8_DEFVAL -#undef DDR_PHY_DX2GTR0_RESERVED_12_8_SHIFT -#undef DDR_PHY_DX2GTR0_RESERVED_12_8_MASK -#define DDR_PHY_DX2GTR0_RESERVED_12_8_DEFVAL 0x00020000 -#define DDR_PHY_DX2GTR0_RESERVED_12_8_SHIFT 8 -#define DDR_PHY_DX2GTR0_RESERVED_12_8_MASK 0x00001F00U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX2GTR0_RESERVED_7_5_DEFVAL -#undef DDR_PHY_DX2GTR0_RESERVED_7_5_SHIFT -#undef DDR_PHY_DX2GTR0_RESERVED_7_5_MASK -#define DDR_PHY_DX2GTR0_RESERVED_7_5_DEFVAL 0x00020000 -#define DDR_PHY_DX2GTR0_RESERVED_7_5_SHIFT 5 -#define DDR_PHY_DX2GTR0_RESERVED_7_5_MASK 0x000000E0U - -/*DQS Gating System Latency*/ -#undef DDR_PHY_DX2GTR0_DGSL_DEFVAL -#undef DDR_PHY_DX2GTR0_DGSL_SHIFT -#undef DDR_PHY_DX2GTR0_DGSL_MASK -#define DDR_PHY_DX2GTR0_DGSL_DEFVAL 0x00020000 -#define DDR_PHY_DX2GTR0_DGSL_SHIFT 0 -#define DDR_PHY_DX2GTR0_DGSL_MASK 0x0000001FU - -/*Calibration Bypass*/ +/* +* Calibration Bypass +*/ #undef DDR_PHY_DX3GCR0_CALBYP_DEFVAL #undef DDR_PHY_DX3GCR0_CALBYP_SHIFT #undef DDR_PHY_DX3GCR0_CALBYP_MASK -#define DDR_PHY_DX3GCR0_CALBYP_DEFVAL 0x40200204 -#define DDR_PHY_DX3GCR0_CALBYP_SHIFT 31 -#define DDR_PHY_DX3GCR0_CALBYP_MASK 0x80000000U +#define DDR_PHY_DX3GCR0_CALBYP_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_CALBYP_SHIFT 31 +#define DDR_PHY_DX3GCR0_CALBYP_MASK 0x80000000U -/*Master Delay Line Enable*/ +/* +* Master Delay Line Enable +*/ #undef DDR_PHY_DX3GCR0_MDLEN_DEFVAL #undef DDR_PHY_DX3GCR0_MDLEN_SHIFT #undef DDR_PHY_DX3GCR0_MDLEN_MASK -#define DDR_PHY_DX3GCR0_MDLEN_DEFVAL 0x40200204 -#define DDR_PHY_DX3GCR0_MDLEN_SHIFT 30 -#define DDR_PHY_DX3GCR0_MDLEN_MASK 0x40000000U +#define DDR_PHY_DX3GCR0_MDLEN_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_MDLEN_SHIFT 30 +#define DDR_PHY_DX3GCR0_MDLEN_MASK 0x40000000U -/*Configurable ODT(TE) Phase Shift*/ +/* +* Configurable ODT(TE) Phase Shift +*/ #undef DDR_PHY_DX3GCR0_CODTSHFT_DEFVAL #undef DDR_PHY_DX3GCR0_CODTSHFT_SHIFT #undef DDR_PHY_DX3GCR0_CODTSHFT_MASK -#define DDR_PHY_DX3GCR0_CODTSHFT_DEFVAL 0x40200204 -#define DDR_PHY_DX3GCR0_CODTSHFT_SHIFT 28 -#define DDR_PHY_DX3GCR0_CODTSHFT_MASK 0x30000000U +#define DDR_PHY_DX3GCR0_CODTSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_CODTSHFT_SHIFT 28 +#define DDR_PHY_DX3GCR0_CODTSHFT_MASK 0x30000000U -/*DQS Duty Cycle Correction*/ +/* +* DQS Duty Cycle Correction +*/ #undef DDR_PHY_DX3GCR0_DQSDCC_DEFVAL #undef DDR_PHY_DX3GCR0_DQSDCC_SHIFT #undef DDR_PHY_DX3GCR0_DQSDCC_MASK -#define DDR_PHY_DX3GCR0_DQSDCC_DEFVAL 0x40200204 -#define DDR_PHY_DX3GCR0_DQSDCC_SHIFT 24 -#define DDR_PHY_DX3GCR0_DQSDCC_MASK 0x0F000000U +#define DDR_PHY_DX3GCR0_DQSDCC_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_DQSDCC_SHIFT 24 +#define DDR_PHY_DX3GCR0_DQSDCC_MASK 0x0F000000U -/*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/ +/* +* Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY +*/ #undef DDR_PHY_DX3GCR0_RDDLY_DEFVAL #undef DDR_PHY_DX3GCR0_RDDLY_SHIFT #undef DDR_PHY_DX3GCR0_RDDLY_MASK -#define DDR_PHY_DX3GCR0_RDDLY_DEFVAL 0x40200204 -#define DDR_PHY_DX3GCR0_RDDLY_SHIFT 20 -#define DDR_PHY_DX3GCR0_RDDLY_MASK 0x00F00000U +#define DDR_PHY_DX3GCR0_RDDLY_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_RDDLY_SHIFT 20 +#define DDR_PHY_DX3GCR0_RDDLY_MASK 0x00F00000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX3GCR0_RESERVED_19_14_DEFVAL #undef DDR_PHY_DX3GCR0_RESERVED_19_14_SHIFT #undef DDR_PHY_DX3GCR0_RESERVED_19_14_MASK -#define DDR_PHY_DX3GCR0_RESERVED_19_14_DEFVAL 0x40200204 -#define DDR_PHY_DX3GCR0_RESERVED_19_14_SHIFT 14 -#define DDR_PHY_DX3GCR0_RESERVED_19_14_MASK 0x000FC000U +#define DDR_PHY_DX3GCR0_RESERVED_19_14_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_RESERVED_19_14_SHIFT 14 +#define DDR_PHY_DX3GCR0_RESERVED_19_14_MASK 0x000FC000U -/*DQSNSE Power Down Receiver*/ +/* +* DQSNSE Power Down Receiver +*/ #undef DDR_PHY_DX3GCR0_DQSNSEPDR_DEFVAL #undef DDR_PHY_DX3GCR0_DQSNSEPDR_SHIFT #undef DDR_PHY_DX3GCR0_DQSNSEPDR_MASK -#define DDR_PHY_DX3GCR0_DQSNSEPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX3GCR0_DQSNSEPDR_SHIFT 13 -#define DDR_PHY_DX3GCR0_DQSNSEPDR_MASK 0x00002000U +#define DDR_PHY_DX3GCR0_DQSNSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_DQSNSEPDR_SHIFT 13 +#define DDR_PHY_DX3GCR0_DQSNSEPDR_MASK 0x00002000U -/*DQSSE Power Down Receiver*/ +/* +* DQSSE Power Down Receiver +*/ #undef DDR_PHY_DX3GCR0_DQSSEPDR_DEFVAL #undef DDR_PHY_DX3GCR0_DQSSEPDR_SHIFT #undef DDR_PHY_DX3GCR0_DQSSEPDR_MASK -#define DDR_PHY_DX3GCR0_DQSSEPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX3GCR0_DQSSEPDR_SHIFT 12 -#define DDR_PHY_DX3GCR0_DQSSEPDR_MASK 0x00001000U +#define DDR_PHY_DX3GCR0_DQSSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_DQSSEPDR_SHIFT 12 +#define DDR_PHY_DX3GCR0_DQSSEPDR_MASK 0x00001000U -/*RTT On Additive Latency*/ +/* +* RTT On Additive Latency +*/ #undef DDR_PHY_DX3GCR0_RTTOAL_DEFVAL #undef DDR_PHY_DX3GCR0_RTTOAL_SHIFT #undef DDR_PHY_DX3GCR0_RTTOAL_MASK -#define DDR_PHY_DX3GCR0_RTTOAL_DEFVAL 0x40200204 -#define DDR_PHY_DX3GCR0_RTTOAL_SHIFT 11 -#define DDR_PHY_DX3GCR0_RTTOAL_MASK 0x00000800U +#define DDR_PHY_DX3GCR0_RTTOAL_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_RTTOAL_SHIFT 11 +#define DDR_PHY_DX3GCR0_RTTOAL_MASK 0x00000800U -/*RTT Output Hold*/ +/* +* RTT Output Hold +*/ #undef DDR_PHY_DX3GCR0_RTTOH_DEFVAL #undef DDR_PHY_DX3GCR0_RTTOH_SHIFT #undef DDR_PHY_DX3GCR0_RTTOH_MASK -#define DDR_PHY_DX3GCR0_RTTOH_DEFVAL 0x40200204 -#define DDR_PHY_DX3GCR0_RTTOH_SHIFT 9 -#define DDR_PHY_DX3GCR0_RTTOH_MASK 0x00000600U +#define DDR_PHY_DX3GCR0_RTTOH_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_RTTOH_SHIFT 9 +#define DDR_PHY_DX3GCR0_RTTOH_MASK 0x00000600U -/*Configurable PDR Phase Shift*/ +/* +* Configurable PDR Phase Shift +*/ #undef DDR_PHY_DX3GCR0_CPDRSHFT_DEFVAL #undef DDR_PHY_DX3GCR0_CPDRSHFT_SHIFT #undef DDR_PHY_DX3GCR0_CPDRSHFT_MASK -#define DDR_PHY_DX3GCR0_CPDRSHFT_DEFVAL 0x40200204 -#define DDR_PHY_DX3GCR0_CPDRSHFT_SHIFT 7 -#define DDR_PHY_DX3GCR0_CPDRSHFT_MASK 0x00000180U +#define DDR_PHY_DX3GCR0_CPDRSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_CPDRSHFT_SHIFT 7 +#define DDR_PHY_DX3GCR0_CPDRSHFT_MASK 0x00000180U -/*DQSR Power Down*/ +/* +* DQSR Power Down +*/ #undef DDR_PHY_DX3GCR0_DQSRPD_DEFVAL #undef DDR_PHY_DX3GCR0_DQSRPD_SHIFT #undef DDR_PHY_DX3GCR0_DQSRPD_MASK -#define DDR_PHY_DX3GCR0_DQSRPD_DEFVAL 0x40200204 -#define DDR_PHY_DX3GCR0_DQSRPD_SHIFT 6 -#define DDR_PHY_DX3GCR0_DQSRPD_MASK 0x00000040U +#define DDR_PHY_DX3GCR0_DQSRPD_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_DQSRPD_SHIFT 6 +#define DDR_PHY_DX3GCR0_DQSRPD_MASK 0x00000040U -/*DQSG Power Down Receiver*/ +/* +* DQSG Power Down Receiver +*/ #undef DDR_PHY_DX3GCR0_DQSGPDR_DEFVAL #undef DDR_PHY_DX3GCR0_DQSGPDR_SHIFT #undef DDR_PHY_DX3GCR0_DQSGPDR_MASK -#define DDR_PHY_DX3GCR0_DQSGPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX3GCR0_DQSGPDR_SHIFT 5 -#define DDR_PHY_DX3GCR0_DQSGPDR_MASK 0x00000020U +#define DDR_PHY_DX3GCR0_DQSGPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_DQSGPDR_SHIFT 5 +#define DDR_PHY_DX3GCR0_DQSGPDR_MASK 0x00000020U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX3GCR0_RESERVED_4_DEFVAL #undef DDR_PHY_DX3GCR0_RESERVED_4_SHIFT #undef DDR_PHY_DX3GCR0_RESERVED_4_MASK -#define DDR_PHY_DX3GCR0_RESERVED_4_DEFVAL 0x40200204 -#define DDR_PHY_DX3GCR0_RESERVED_4_SHIFT 4 -#define DDR_PHY_DX3GCR0_RESERVED_4_MASK 0x00000010U +#define DDR_PHY_DX3GCR0_RESERVED_4_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_RESERVED_4_SHIFT 4 +#define DDR_PHY_DX3GCR0_RESERVED_4_MASK 0x00000010U -/*DQSG On-Die Termination*/ +/* +* DQSG On-Die Termination +*/ #undef DDR_PHY_DX3GCR0_DQSGODT_DEFVAL #undef DDR_PHY_DX3GCR0_DQSGODT_SHIFT #undef DDR_PHY_DX3GCR0_DQSGODT_MASK -#define DDR_PHY_DX3GCR0_DQSGODT_DEFVAL 0x40200204 -#define DDR_PHY_DX3GCR0_DQSGODT_SHIFT 3 -#define DDR_PHY_DX3GCR0_DQSGODT_MASK 0x00000008U +#define DDR_PHY_DX3GCR0_DQSGODT_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_DQSGODT_SHIFT 3 +#define DDR_PHY_DX3GCR0_DQSGODT_MASK 0x00000008U -/*DQSG Output Enable*/ +/* +* DQSG Output Enable +*/ #undef DDR_PHY_DX3GCR0_DQSGOE_DEFVAL #undef DDR_PHY_DX3GCR0_DQSGOE_SHIFT #undef DDR_PHY_DX3GCR0_DQSGOE_MASK -#define DDR_PHY_DX3GCR0_DQSGOE_DEFVAL 0x40200204 -#define DDR_PHY_DX3GCR0_DQSGOE_SHIFT 2 -#define DDR_PHY_DX3GCR0_DQSGOE_MASK 0x00000004U +#define DDR_PHY_DX3GCR0_DQSGOE_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_DQSGOE_SHIFT 2 +#define DDR_PHY_DX3GCR0_DQSGOE_MASK 0x00000004U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX3GCR0_RESERVED_1_0_DEFVAL #undef DDR_PHY_DX3GCR0_RESERVED_1_0_SHIFT #undef DDR_PHY_DX3GCR0_RESERVED_1_0_MASK -#define DDR_PHY_DX3GCR0_RESERVED_1_0_DEFVAL 0x40200204 -#define DDR_PHY_DX3GCR0_RESERVED_1_0_SHIFT 0 -#define DDR_PHY_DX3GCR0_RESERVED_1_0_MASK 0x00000003U +#define DDR_PHY_DX3GCR0_RESERVED_1_0_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_RESERVED_1_0_SHIFT 0 +#define DDR_PHY_DX3GCR0_RESERVED_1_0_MASK 0x00000003U -/*Enables the PDR mode for DQ[7:0]*/ +/* +* Enables the PDR mode for DQ[7:0] +*/ #undef DDR_PHY_DX3GCR1_DXPDRMODE_DEFVAL #undef DDR_PHY_DX3GCR1_DXPDRMODE_SHIFT #undef DDR_PHY_DX3GCR1_DXPDRMODE_MASK -#define DDR_PHY_DX3GCR1_DXPDRMODE_DEFVAL 0x00007FFF -#define DDR_PHY_DX3GCR1_DXPDRMODE_SHIFT 16 -#define DDR_PHY_DX3GCR1_DXPDRMODE_MASK 0xFFFF0000U +#define DDR_PHY_DX3GCR1_DXPDRMODE_DEFVAL 0x00007FFF +#define DDR_PHY_DX3GCR1_DXPDRMODE_SHIFT 16 +#define DDR_PHY_DX3GCR1_DXPDRMODE_MASK 0xFFFF0000U -/*Reserved. Returns zeroes on reads.*/ +/* +* Reserved. Returns zeroes on reads. +*/ #undef DDR_PHY_DX3GCR1_RESERVED_15_DEFVAL #undef DDR_PHY_DX3GCR1_RESERVED_15_SHIFT #undef DDR_PHY_DX3GCR1_RESERVED_15_MASK -#define DDR_PHY_DX3GCR1_RESERVED_15_DEFVAL 0x00007FFF -#define DDR_PHY_DX3GCR1_RESERVED_15_SHIFT 15 -#define DDR_PHY_DX3GCR1_RESERVED_15_MASK 0x00008000U +#define DDR_PHY_DX3GCR1_RESERVED_15_DEFVAL 0x00007FFF +#define DDR_PHY_DX3GCR1_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX3GCR1_RESERVED_15_MASK 0x00008000U -/*Select the delayed or non-delayed read data strobe #*/ +/* +* Select the delayed or non-delayed read data strobe # +*/ #undef DDR_PHY_DX3GCR1_QSNSEL_DEFVAL #undef DDR_PHY_DX3GCR1_QSNSEL_SHIFT #undef DDR_PHY_DX3GCR1_QSNSEL_MASK -#define DDR_PHY_DX3GCR1_QSNSEL_DEFVAL 0x00007FFF -#define DDR_PHY_DX3GCR1_QSNSEL_SHIFT 14 -#define DDR_PHY_DX3GCR1_QSNSEL_MASK 0x00004000U +#define DDR_PHY_DX3GCR1_QSNSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX3GCR1_QSNSEL_SHIFT 14 +#define DDR_PHY_DX3GCR1_QSNSEL_MASK 0x00004000U -/*Select the delayed or non-delayed read data strobe*/ +/* +* Select the delayed or non-delayed read data strobe +*/ #undef DDR_PHY_DX3GCR1_QSSEL_DEFVAL #undef DDR_PHY_DX3GCR1_QSSEL_SHIFT #undef DDR_PHY_DX3GCR1_QSSEL_MASK -#define DDR_PHY_DX3GCR1_QSSEL_DEFVAL 0x00007FFF -#define DDR_PHY_DX3GCR1_QSSEL_SHIFT 13 -#define DDR_PHY_DX3GCR1_QSSEL_MASK 0x00002000U +#define DDR_PHY_DX3GCR1_QSSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX3GCR1_QSSEL_SHIFT 13 +#define DDR_PHY_DX3GCR1_QSSEL_MASK 0x00002000U -/*Enables Read Data Strobe in a byte lane*/ +/* +* Enables Read Data Strobe in a byte lane +*/ #undef DDR_PHY_DX3GCR1_OEEN_DEFVAL #undef DDR_PHY_DX3GCR1_OEEN_SHIFT #undef DDR_PHY_DX3GCR1_OEEN_MASK -#define DDR_PHY_DX3GCR1_OEEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX3GCR1_OEEN_SHIFT 12 -#define DDR_PHY_DX3GCR1_OEEN_MASK 0x00001000U +#define DDR_PHY_DX3GCR1_OEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX3GCR1_OEEN_SHIFT 12 +#define DDR_PHY_DX3GCR1_OEEN_MASK 0x00001000U -/*Enables PDR in a byte lane*/ +/* +* Enables PDR in a byte lane +*/ #undef DDR_PHY_DX3GCR1_PDREN_DEFVAL #undef DDR_PHY_DX3GCR1_PDREN_SHIFT #undef DDR_PHY_DX3GCR1_PDREN_MASK -#define DDR_PHY_DX3GCR1_PDREN_DEFVAL 0x00007FFF -#define DDR_PHY_DX3GCR1_PDREN_SHIFT 11 -#define DDR_PHY_DX3GCR1_PDREN_MASK 0x00000800U +#define DDR_PHY_DX3GCR1_PDREN_DEFVAL 0x00007FFF +#define DDR_PHY_DX3GCR1_PDREN_SHIFT 11 +#define DDR_PHY_DX3GCR1_PDREN_MASK 0x00000800U -/*Enables ODT/TE in a byte lane*/ +/* +* Enables ODT/TE in a byte lane +*/ #undef DDR_PHY_DX3GCR1_TEEN_DEFVAL #undef DDR_PHY_DX3GCR1_TEEN_SHIFT #undef DDR_PHY_DX3GCR1_TEEN_MASK -#define DDR_PHY_DX3GCR1_TEEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX3GCR1_TEEN_SHIFT 10 -#define DDR_PHY_DX3GCR1_TEEN_MASK 0x00000400U +#define DDR_PHY_DX3GCR1_TEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX3GCR1_TEEN_SHIFT 10 +#define DDR_PHY_DX3GCR1_TEEN_MASK 0x00000400U -/*Enables Write Data strobe in a byte lane*/ +/* +* Enables Write Data strobe in a byte lane +*/ #undef DDR_PHY_DX3GCR1_DSEN_DEFVAL #undef DDR_PHY_DX3GCR1_DSEN_SHIFT #undef DDR_PHY_DX3GCR1_DSEN_MASK -#define DDR_PHY_DX3GCR1_DSEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX3GCR1_DSEN_SHIFT 9 -#define DDR_PHY_DX3GCR1_DSEN_MASK 0x00000200U +#define DDR_PHY_DX3GCR1_DSEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX3GCR1_DSEN_SHIFT 9 +#define DDR_PHY_DX3GCR1_DSEN_MASK 0x00000200U -/*Enables DM pin in a byte lane*/ +/* +* Enables DM pin in a byte lane +*/ #undef DDR_PHY_DX3GCR1_DMEN_DEFVAL #undef DDR_PHY_DX3GCR1_DMEN_SHIFT #undef DDR_PHY_DX3GCR1_DMEN_MASK -#define DDR_PHY_DX3GCR1_DMEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX3GCR1_DMEN_SHIFT 8 -#define DDR_PHY_DX3GCR1_DMEN_MASK 0x00000100U +#define DDR_PHY_DX3GCR1_DMEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX3GCR1_DMEN_SHIFT 8 +#define DDR_PHY_DX3GCR1_DMEN_MASK 0x00000100U -/*Enables DQ corresponding to each bit in a byte*/ +/* +* Enables DQ corresponding to each bit in a byte +*/ #undef DDR_PHY_DX3GCR1_DQEN_DEFVAL #undef DDR_PHY_DX3GCR1_DQEN_SHIFT #undef DDR_PHY_DX3GCR1_DQEN_MASK -#define DDR_PHY_DX3GCR1_DQEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX3GCR1_DQEN_SHIFT 0 -#define DDR_PHY_DX3GCR1_DQEN_MASK 0x000000FFU +#define DDR_PHY_DX3GCR1_DQEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX3GCR1_DQEN_SHIFT 0 +#define DDR_PHY_DX3GCR1_DQEN_MASK 0x000000FFU -/*Byte lane VREF IOM (Used only by D4MU IOs)*/ +/* +* Byte lane VREF IOM (Used only by D4MU IOs) +*/ #undef DDR_PHY_DX3GCR4_RESERVED_31_29_DEFVAL #undef DDR_PHY_DX3GCR4_RESERVED_31_29_SHIFT #undef DDR_PHY_DX3GCR4_RESERVED_31_29_MASK -#define DDR_PHY_DX3GCR4_RESERVED_31_29_DEFVAL 0x0E00003C -#define DDR_PHY_DX3GCR4_RESERVED_31_29_SHIFT 29 -#define DDR_PHY_DX3GCR4_RESERVED_31_29_MASK 0xE0000000U +#define DDR_PHY_DX3GCR4_RESERVED_31_29_DEFVAL 0x0E00003C +#define DDR_PHY_DX3GCR4_RESERVED_31_29_SHIFT 29 +#define DDR_PHY_DX3GCR4_RESERVED_31_29_MASK 0xE0000000U -/*Byte Lane VREF Pad Enable*/ +/* +* Byte Lane VREF Pad Enable +*/ #undef DDR_PHY_DX3GCR4_DXREFPEN_DEFVAL #undef DDR_PHY_DX3GCR4_DXREFPEN_SHIFT #undef DDR_PHY_DX3GCR4_DXREFPEN_MASK -#define DDR_PHY_DX3GCR4_DXREFPEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX3GCR4_DXREFPEN_SHIFT 28 -#define DDR_PHY_DX3GCR4_DXREFPEN_MASK 0x10000000U +#define DDR_PHY_DX3GCR4_DXREFPEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX3GCR4_DXREFPEN_SHIFT 28 +#define DDR_PHY_DX3GCR4_DXREFPEN_MASK 0x10000000U -/*Byte Lane Internal VREF Enable*/ +/* +* Byte Lane Internal VREF Enable +*/ #undef DDR_PHY_DX3GCR4_DXREFEEN_DEFVAL #undef DDR_PHY_DX3GCR4_DXREFEEN_SHIFT #undef DDR_PHY_DX3GCR4_DXREFEEN_MASK -#define DDR_PHY_DX3GCR4_DXREFEEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX3GCR4_DXREFEEN_SHIFT 26 -#define DDR_PHY_DX3GCR4_DXREFEEN_MASK 0x0C000000U +#define DDR_PHY_DX3GCR4_DXREFEEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX3GCR4_DXREFEEN_SHIFT 26 +#define DDR_PHY_DX3GCR4_DXREFEEN_MASK 0x0C000000U -/*Byte Lane Single-End VREF Enable*/ +/* +* Byte Lane Single-End VREF Enable +*/ #undef DDR_PHY_DX3GCR4_DXREFSEN_DEFVAL #undef DDR_PHY_DX3GCR4_DXREFSEN_SHIFT #undef DDR_PHY_DX3GCR4_DXREFSEN_MASK -#define DDR_PHY_DX3GCR4_DXREFSEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX3GCR4_DXREFSEN_SHIFT 25 -#define DDR_PHY_DX3GCR4_DXREFSEN_MASK 0x02000000U +#define DDR_PHY_DX3GCR4_DXREFSEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX3GCR4_DXREFSEN_SHIFT 25 +#define DDR_PHY_DX3GCR4_DXREFSEN_MASK 0x02000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX3GCR4_RESERVED_24_DEFVAL #undef DDR_PHY_DX3GCR4_RESERVED_24_SHIFT #undef DDR_PHY_DX3GCR4_RESERVED_24_MASK -#define DDR_PHY_DX3GCR4_RESERVED_24_DEFVAL 0x0E00003C -#define DDR_PHY_DX3GCR4_RESERVED_24_SHIFT 24 -#define DDR_PHY_DX3GCR4_RESERVED_24_MASK 0x01000000U +#define DDR_PHY_DX3GCR4_RESERVED_24_DEFVAL 0x0E00003C +#define DDR_PHY_DX3GCR4_RESERVED_24_SHIFT 24 +#define DDR_PHY_DX3GCR4_RESERVED_24_MASK 0x01000000U -/*External VREF generator REFSEL range select*/ +/* +* External VREF generator REFSEL range select +*/ #undef DDR_PHY_DX3GCR4_DXREFESELRANGE_DEFVAL #undef DDR_PHY_DX3GCR4_DXREFESELRANGE_SHIFT #undef DDR_PHY_DX3GCR4_DXREFESELRANGE_MASK -#define DDR_PHY_DX3GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C -#define DDR_PHY_DX3GCR4_DXREFESELRANGE_SHIFT 23 -#define DDR_PHY_DX3GCR4_DXREFESELRANGE_MASK 0x00800000U +#define DDR_PHY_DX3GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX3GCR4_DXREFESELRANGE_SHIFT 23 +#define DDR_PHY_DX3GCR4_DXREFESELRANGE_MASK 0x00800000U -/*Byte Lane External VREF Select*/ +/* +* Byte Lane External VREF Select +*/ #undef DDR_PHY_DX3GCR4_DXREFESEL_DEFVAL #undef DDR_PHY_DX3GCR4_DXREFESEL_SHIFT #undef DDR_PHY_DX3GCR4_DXREFESEL_MASK -#define DDR_PHY_DX3GCR4_DXREFESEL_DEFVAL 0x0E00003C -#define DDR_PHY_DX3GCR4_DXREFESEL_SHIFT 16 -#define DDR_PHY_DX3GCR4_DXREFESEL_MASK 0x007F0000U +#define DDR_PHY_DX3GCR4_DXREFESEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX3GCR4_DXREFESEL_SHIFT 16 +#define DDR_PHY_DX3GCR4_DXREFESEL_MASK 0x007F0000U -/*Single ended VREF generator REFSEL range select*/ +/* +* Single ended VREF generator REFSEL range select +*/ #undef DDR_PHY_DX3GCR4_DXREFSSELRANGE_DEFVAL #undef DDR_PHY_DX3GCR4_DXREFSSELRANGE_SHIFT #undef DDR_PHY_DX3GCR4_DXREFSSELRANGE_MASK -#define DDR_PHY_DX3GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C -#define DDR_PHY_DX3GCR4_DXREFSSELRANGE_SHIFT 15 -#define DDR_PHY_DX3GCR4_DXREFSSELRANGE_MASK 0x00008000U +#define DDR_PHY_DX3GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX3GCR4_DXREFSSELRANGE_SHIFT 15 +#define DDR_PHY_DX3GCR4_DXREFSSELRANGE_MASK 0x00008000U -/*Byte Lane Single-End VREF Select*/ +/* +* Byte Lane Single-End VREF Select +*/ #undef DDR_PHY_DX3GCR4_DXREFSSEL_DEFVAL #undef DDR_PHY_DX3GCR4_DXREFSSEL_SHIFT #undef DDR_PHY_DX3GCR4_DXREFSSEL_MASK -#define DDR_PHY_DX3GCR4_DXREFSSEL_DEFVAL 0x0E00003C -#define DDR_PHY_DX3GCR4_DXREFSSEL_SHIFT 8 -#define DDR_PHY_DX3GCR4_DXREFSSEL_MASK 0x00007F00U +#define DDR_PHY_DX3GCR4_DXREFSSEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX3GCR4_DXREFSSEL_SHIFT 8 +#define DDR_PHY_DX3GCR4_DXREFSSEL_MASK 0x00007F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX3GCR4_RESERVED_7_6_DEFVAL #undef DDR_PHY_DX3GCR4_RESERVED_7_6_SHIFT #undef DDR_PHY_DX3GCR4_RESERVED_7_6_MASK -#define DDR_PHY_DX3GCR4_RESERVED_7_6_DEFVAL 0x0E00003C -#define DDR_PHY_DX3GCR4_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_DX3GCR4_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_DX3GCR4_RESERVED_7_6_DEFVAL 0x0E00003C +#define DDR_PHY_DX3GCR4_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX3GCR4_RESERVED_7_6_MASK 0x000000C0U -/*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/ +/* +* VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. +*/ #undef DDR_PHY_DX3GCR4_DXREFIEN_DEFVAL #undef DDR_PHY_DX3GCR4_DXREFIEN_SHIFT #undef DDR_PHY_DX3GCR4_DXREFIEN_MASK -#define DDR_PHY_DX3GCR4_DXREFIEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX3GCR4_DXREFIEN_SHIFT 2 -#define DDR_PHY_DX3GCR4_DXREFIEN_MASK 0x0000003CU +#define DDR_PHY_DX3GCR4_DXREFIEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX3GCR4_DXREFIEN_SHIFT 2 +#define DDR_PHY_DX3GCR4_DXREFIEN_MASK 0x0000003CU -/*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/ +/* +* VRMON control for DQ IO (Single Ended) buffers of a byte lane. +*/ #undef DDR_PHY_DX3GCR4_DXREFIMON_DEFVAL #undef DDR_PHY_DX3GCR4_DXREFIMON_SHIFT #undef DDR_PHY_DX3GCR4_DXREFIMON_MASK -#define DDR_PHY_DX3GCR4_DXREFIMON_DEFVAL 0x0E00003C -#define DDR_PHY_DX3GCR4_DXREFIMON_SHIFT 0 -#define DDR_PHY_DX3GCR4_DXREFIMON_MASK 0x00000003U +#define DDR_PHY_DX3GCR4_DXREFIMON_DEFVAL 0x0E00003C +#define DDR_PHY_DX3GCR4_DXREFIMON_SHIFT 0 +#define DDR_PHY_DX3GCR4_DXREFIMON_MASK 0x00000003U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX3GCR5_RESERVED_31_DEFVAL #undef DDR_PHY_DX3GCR5_RESERVED_31_SHIFT #undef DDR_PHY_DX3GCR5_RESERVED_31_MASK -#define DDR_PHY_DX3GCR5_RESERVED_31_DEFVAL 0x09090909 -#define DDR_PHY_DX3GCR5_RESERVED_31_SHIFT 31 -#define DDR_PHY_DX3GCR5_RESERVED_31_MASK 0x80000000U +#define DDR_PHY_DX3GCR5_RESERVED_31_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR5_RESERVED_31_SHIFT 31 +#define DDR_PHY_DX3GCR5_RESERVED_31_MASK 0x80000000U -/*Byte Lane internal VREF Select for Rank 3*/ +/* +* Byte Lane internal VREF Select for Rank 3 +*/ #undef DDR_PHY_DX3GCR5_DXREFISELR3_DEFVAL #undef DDR_PHY_DX3GCR5_DXREFISELR3_SHIFT #undef DDR_PHY_DX3GCR5_DXREFISELR3_MASK -#define DDR_PHY_DX3GCR5_DXREFISELR3_DEFVAL 0x09090909 -#define DDR_PHY_DX3GCR5_DXREFISELR3_SHIFT 24 -#define DDR_PHY_DX3GCR5_DXREFISELR3_MASK 0x7F000000U +#define DDR_PHY_DX3GCR5_DXREFISELR3_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR5_DXREFISELR3_SHIFT 24 +#define DDR_PHY_DX3GCR5_DXREFISELR3_MASK 0x7F000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX3GCR5_RESERVED_23_DEFVAL #undef DDR_PHY_DX3GCR5_RESERVED_23_SHIFT #undef DDR_PHY_DX3GCR5_RESERVED_23_MASK -#define DDR_PHY_DX3GCR5_RESERVED_23_DEFVAL 0x09090909 -#define DDR_PHY_DX3GCR5_RESERVED_23_SHIFT 23 -#define DDR_PHY_DX3GCR5_RESERVED_23_MASK 0x00800000U +#define DDR_PHY_DX3GCR5_RESERVED_23_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR5_RESERVED_23_SHIFT 23 +#define DDR_PHY_DX3GCR5_RESERVED_23_MASK 0x00800000U -/*Byte Lane internal VREF Select for Rank 2*/ +/* +* Byte Lane internal VREF Select for Rank 2 +*/ #undef DDR_PHY_DX3GCR5_DXREFISELR2_DEFVAL #undef DDR_PHY_DX3GCR5_DXREFISELR2_SHIFT #undef DDR_PHY_DX3GCR5_DXREFISELR2_MASK -#define DDR_PHY_DX3GCR5_DXREFISELR2_DEFVAL 0x09090909 -#define DDR_PHY_DX3GCR5_DXREFISELR2_SHIFT 16 -#define DDR_PHY_DX3GCR5_DXREFISELR2_MASK 0x007F0000U +#define DDR_PHY_DX3GCR5_DXREFISELR2_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR5_DXREFISELR2_SHIFT 16 +#define DDR_PHY_DX3GCR5_DXREFISELR2_MASK 0x007F0000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX3GCR5_RESERVED_15_DEFVAL #undef DDR_PHY_DX3GCR5_RESERVED_15_SHIFT #undef DDR_PHY_DX3GCR5_RESERVED_15_MASK -#define DDR_PHY_DX3GCR5_RESERVED_15_DEFVAL 0x09090909 -#define DDR_PHY_DX3GCR5_RESERVED_15_SHIFT 15 -#define DDR_PHY_DX3GCR5_RESERVED_15_MASK 0x00008000U +#define DDR_PHY_DX3GCR5_RESERVED_15_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR5_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX3GCR5_RESERVED_15_MASK 0x00008000U -/*Byte Lane internal VREF Select for Rank 1*/ +/* +* Byte Lane internal VREF Select for Rank 1 +*/ #undef DDR_PHY_DX3GCR5_DXREFISELR1_DEFVAL #undef DDR_PHY_DX3GCR5_DXREFISELR1_SHIFT #undef DDR_PHY_DX3GCR5_DXREFISELR1_MASK -#define DDR_PHY_DX3GCR5_DXREFISELR1_DEFVAL 0x09090909 -#define DDR_PHY_DX3GCR5_DXREFISELR1_SHIFT 8 -#define DDR_PHY_DX3GCR5_DXREFISELR1_MASK 0x00007F00U +#define DDR_PHY_DX3GCR5_DXREFISELR1_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR5_DXREFISELR1_SHIFT 8 +#define DDR_PHY_DX3GCR5_DXREFISELR1_MASK 0x00007F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX3GCR5_RESERVED_7_DEFVAL #undef DDR_PHY_DX3GCR5_RESERVED_7_SHIFT #undef DDR_PHY_DX3GCR5_RESERVED_7_MASK -#define DDR_PHY_DX3GCR5_RESERVED_7_DEFVAL 0x09090909 -#define DDR_PHY_DX3GCR5_RESERVED_7_SHIFT 7 -#define DDR_PHY_DX3GCR5_RESERVED_7_MASK 0x00000080U +#define DDR_PHY_DX3GCR5_RESERVED_7_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR5_RESERVED_7_SHIFT 7 +#define DDR_PHY_DX3GCR5_RESERVED_7_MASK 0x00000080U -/*Byte Lane internal VREF Select for Rank 0*/ +/* +* Byte Lane internal VREF Select for Rank 0 +*/ #undef DDR_PHY_DX3GCR5_DXREFISELR0_DEFVAL #undef DDR_PHY_DX3GCR5_DXREFISELR0_SHIFT #undef DDR_PHY_DX3GCR5_DXREFISELR0_MASK -#define DDR_PHY_DX3GCR5_DXREFISELR0_DEFVAL 0x09090909 -#define DDR_PHY_DX3GCR5_DXREFISELR0_SHIFT 0 -#define DDR_PHY_DX3GCR5_DXREFISELR0_MASK 0x0000007FU +#define DDR_PHY_DX3GCR5_DXREFISELR0_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR5_DXREFISELR0_SHIFT 0 +#define DDR_PHY_DX3GCR5_DXREFISELR0_MASK 0x0000007FU -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX3GCR6_RESERVED_31_30_DEFVAL #undef DDR_PHY_DX3GCR6_RESERVED_31_30_SHIFT #undef DDR_PHY_DX3GCR6_RESERVED_31_30_MASK -#define DDR_PHY_DX3GCR6_RESERVED_31_30_DEFVAL 0x09090909 -#define DDR_PHY_DX3GCR6_RESERVED_31_30_SHIFT 30 -#define DDR_PHY_DX3GCR6_RESERVED_31_30_MASK 0xC0000000U +#define DDR_PHY_DX3GCR6_RESERVED_31_30_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR6_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX3GCR6_RESERVED_31_30_MASK 0xC0000000U -/*DRAM DQ VREF Select for Rank3*/ +/* +* DRAM DQ VREF Select for Rank3 +*/ #undef DDR_PHY_DX3GCR6_DXDQVREFR3_DEFVAL #undef DDR_PHY_DX3GCR6_DXDQVREFR3_SHIFT #undef DDR_PHY_DX3GCR6_DXDQVREFR3_MASK -#define DDR_PHY_DX3GCR6_DXDQVREFR3_DEFVAL 0x09090909 -#define DDR_PHY_DX3GCR6_DXDQVREFR3_SHIFT 24 -#define DDR_PHY_DX3GCR6_DXDQVREFR3_MASK 0x3F000000U +#define DDR_PHY_DX3GCR6_DXDQVREFR3_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR6_DXDQVREFR3_SHIFT 24 +#define DDR_PHY_DX3GCR6_DXDQVREFR3_MASK 0x3F000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX3GCR6_RESERVED_23_22_DEFVAL #undef DDR_PHY_DX3GCR6_RESERVED_23_22_SHIFT #undef DDR_PHY_DX3GCR6_RESERVED_23_22_MASK -#define DDR_PHY_DX3GCR6_RESERVED_23_22_DEFVAL 0x09090909 -#define DDR_PHY_DX3GCR6_RESERVED_23_22_SHIFT 22 -#define DDR_PHY_DX3GCR6_RESERVED_23_22_MASK 0x00C00000U +#define DDR_PHY_DX3GCR6_RESERVED_23_22_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR6_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX3GCR6_RESERVED_23_22_MASK 0x00C00000U -/*DRAM DQ VREF Select for Rank2*/ +/* +* DRAM DQ VREF Select for Rank2 +*/ #undef DDR_PHY_DX3GCR6_DXDQVREFR2_DEFVAL #undef DDR_PHY_DX3GCR6_DXDQVREFR2_SHIFT #undef DDR_PHY_DX3GCR6_DXDQVREFR2_MASK -#define DDR_PHY_DX3GCR6_DXDQVREFR2_DEFVAL 0x09090909 -#define DDR_PHY_DX3GCR6_DXDQVREFR2_SHIFT 16 -#define DDR_PHY_DX3GCR6_DXDQVREFR2_MASK 0x003F0000U +#define DDR_PHY_DX3GCR6_DXDQVREFR2_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR6_DXDQVREFR2_SHIFT 16 +#define DDR_PHY_DX3GCR6_DXDQVREFR2_MASK 0x003F0000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX3GCR6_RESERVED_15_14_DEFVAL #undef DDR_PHY_DX3GCR6_RESERVED_15_14_SHIFT #undef DDR_PHY_DX3GCR6_RESERVED_15_14_MASK -#define DDR_PHY_DX3GCR6_RESERVED_15_14_DEFVAL 0x09090909 -#define DDR_PHY_DX3GCR6_RESERVED_15_14_SHIFT 14 -#define DDR_PHY_DX3GCR6_RESERVED_15_14_MASK 0x0000C000U +#define DDR_PHY_DX3GCR6_RESERVED_15_14_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR6_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_DX3GCR6_RESERVED_15_14_MASK 0x0000C000U -/*DRAM DQ VREF Select for Rank1*/ +/* +* DRAM DQ VREF Select for Rank1 +*/ #undef DDR_PHY_DX3GCR6_DXDQVREFR1_DEFVAL #undef DDR_PHY_DX3GCR6_DXDQVREFR1_SHIFT #undef DDR_PHY_DX3GCR6_DXDQVREFR1_MASK -#define DDR_PHY_DX3GCR6_DXDQVREFR1_DEFVAL 0x09090909 -#define DDR_PHY_DX3GCR6_DXDQVREFR1_SHIFT 8 -#define DDR_PHY_DX3GCR6_DXDQVREFR1_MASK 0x00003F00U +#define DDR_PHY_DX3GCR6_DXDQVREFR1_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR6_DXDQVREFR1_SHIFT 8 +#define DDR_PHY_DX3GCR6_DXDQVREFR1_MASK 0x00003F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX3GCR6_RESERVED_7_6_DEFVAL #undef DDR_PHY_DX3GCR6_RESERVED_7_6_SHIFT #undef DDR_PHY_DX3GCR6_RESERVED_7_6_MASK -#define DDR_PHY_DX3GCR6_RESERVED_7_6_DEFVAL 0x09090909 -#define DDR_PHY_DX3GCR6_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_DX3GCR6_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_DX3GCR6_RESERVED_7_6_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR6_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX3GCR6_RESERVED_7_6_MASK 0x000000C0U -/*DRAM DQ VREF Select for Rank0*/ +/* +* DRAM DQ VREF Select for Rank0 +*/ #undef DDR_PHY_DX3GCR6_DXDQVREFR0_DEFVAL #undef DDR_PHY_DX3GCR6_DXDQVREFR0_SHIFT #undef DDR_PHY_DX3GCR6_DXDQVREFR0_MASK -#define DDR_PHY_DX3GCR6_DXDQVREFR0_DEFVAL 0x09090909 -#define DDR_PHY_DX3GCR6_DXDQVREFR0_SHIFT 0 -#define DDR_PHY_DX3GCR6_DXDQVREFR0_MASK 0x0000003FU +#define DDR_PHY_DX3GCR6_DXDQVREFR0_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR6_DXDQVREFR0_SHIFT 0 +#define DDR_PHY_DX3GCR6_DXDQVREFR0_MASK 0x0000003FU -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX3LCDLR2_RESERVED_31_25_DEFVAL -#undef DDR_PHY_DX3LCDLR2_RESERVED_31_25_SHIFT -#undef DDR_PHY_DX3LCDLR2_RESERVED_31_25_MASK -#define DDR_PHY_DX3LCDLR2_RESERVED_31_25_DEFVAL 0x00000000 -#define DDR_PHY_DX3LCDLR2_RESERVED_31_25_SHIFT 25 -#define DDR_PHY_DX3LCDLR2_RESERVED_31_25_MASK 0xFE000000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX3LCDLR2_RESERVED_24_16_DEFVAL -#undef DDR_PHY_DX3LCDLR2_RESERVED_24_16_SHIFT -#undef DDR_PHY_DX3LCDLR2_RESERVED_24_16_MASK -#define DDR_PHY_DX3LCDLR2_RESERVED_24_16_DEFVAL 0x00000000 -#define DDR_PHY_DX3LCDLR2_RESERVED_24_16_SHIFT 16 -#define DDR_PHY_DX3LCDLR2_RESERVED_24_16_MASK 0x01FF0000U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX3LCDLR2_RESERVED_15_9_DEFVAL -#undef DDR_PHY_DX3LCDLR2_RESERVED_15_9_SHIFT -#undef DDR_PHY_DX3LCDLR2_RESERVED_15_9_MASK -#define DDR_PHY_DX3LCDLR2_RESERVED_15_9_DEFVAL 0x00000000 -#define DDR_PHY_DX3LCDLR2_RESERVED_15_9_SHIFT 9 -#define DDR_PHY_DX3LCDLR2_RESERVED_15_9_MASK 0x0000FE00U - -/*Read DQS Gating Delay*/ -#undef DDR_PHY_DX3LCDLR2_DQSGD_DEFVAL -#undef DDR_PHY_DX3LCDLR2_DQSGD_SHIFT -#undef DDR_PHY_DX3LCDLR2_DQSGD_MASK -#define DDR_PHY_DX3LCDLR2_DQSGD_DEFVAL 0x00000000 -#define DDR_PHY_DX3LCDLR2_DQSGD_SHIFT 0 -#define DDR_PHY_DX3LCDLR2_DQSGD_MASK 0x000001FFU - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX3GTR0_RESERVED_31_24_DEFVAL -#undef DDR_PHY_DX3GTR0_RESERVED_31_24_SHIFT -#undef DDR_PHY_DX3GTR0_RESERVED_31_24_MASK -#define DDR_PHY_DX3GTR0_RESERVED_31_24_DEFVAL 0x00020000 -#define DDR_PHY_DX3GTR0_RESERVED_31_24_SHIFT 27 -#define DDR_PHY_DX3GTR0_RESERVED_31_24_MASK 0xF8000000U - -/*DQ Write Path Latency Pipeline*/ -#undef DDR_PHY_DX3GTR0_WDQSL_DEFVAL -#undef DDR_PHY_DX3GTR0_WDQSL_SHIFT -#undef DDR_PHY_DX3GTR0_WDQSL_MASK -#define DDR_PHY_DX3GTR0_WDQSL_DEFVAL 0x00020000 -#define DDR_PHY_DX3GTR0_WDQSL_SHIFT 24 -#define DDR_PHY_DX3GTR0_WDQSL_MASK 0x07000000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX3GTR0_RESERVED_23_20_DEFVAL -#undef DDR_PHY_DX3GTR0_RESERVED_23_20_SHIFT -#undef DDR_PHY_DX3GTR0_RESERVED_23_20_MASK -#define DDR_PHY_DX3GTR0_RESERVED_23_20_DEFVAL 0x00020000 -#define DDR_PHY_DX3GTR0_RESERVED_23_20_SHIFT 20 -#define DDR_PHY_DX3GTR0_RESERVED_23_20_MASK 0x00F00000U - -/*Write Leveling System Latency*/ -#undef DDR_PHY_DX3GTR0_WLSL_DEFVAL -#undef DDR_PHY_DX3GTR0_WLSL_SHIFT -#undef DDR_PHY_DX3GTR0_WLSL_MASK -#define DDR_PHY_DX3GTR0_WLSL_DEFVAL 0x00020000 -#define DDR_PHY_DX3GTR0_WLSL_SHIFT 16 -#define DDR_PHY_DX3GTR0_WLSL_MASK 0x000F0000U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX3GTR0_RESERVED_15_13_DEFVAL -#undef DDR_PHY_DX3GTR0_RESERVED_15_13_SHIFT -#undef DDR_PHY_DX3GTR0_RESERVED_15_13_MASK -#define DDR_PHY_DX3GTR0_RESERVED_15_13_DEFVAL 0x00020000 -#define DDR_PHY_DX3GTR0_RESERVED_15_13_SHIFT 13 -#define DDR_PHY_DX3GTR0_RESERVED_15_13_MASK 0x0000E000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX3GTR0_RESERVED_12_8_DEFVAL -#undef DDR_PHY_DX3GTR0_RESERVED_12_8_SHIFT -#undef DDR_PHY_DX3GTR0_RESERVED_12_8_MASK -#define DDR_PHY_DX3GTR0_RESERVED_12_8_DEFVAL 0x00020000 -#define DDR_PHY_DX3GTR0_RESERVED_12_8_SHIFT 8 -#define DDR_PHY_DX3GTR0_RESERVED_12_8_MASK 0x00001F00U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX3GTR0_RESERVED_7_5_DEFVAL -#undef DDR_PHY_DX3GTR0_RESERVED_7_5_SHIFT -#undef DDR_PHY_DX3GTR0_RESERVED_7_5_MASK -#define DDR_PHY_DX3GTR0_RESERVED_7_5_DEFVAL 0x00020000 -#define DDR_PHY_DX3GTR0_RESERVED_7_5_SHIFT 5 -#define DDR_PHY_DX3GTR0_RESERVED_7_5_MASK 0x000000E0U - -/*DQS Gating System Latency*/ -#undef DDR_PHY_DX3GTR0_DGSL_DEFVAL -#undef DDR_PHY_DX3GTR0_DGSL_SHIFT -#undef DDR_PHY_DX3GTR0_DGSL_MASK -#define DDR_PHY_DX3GTR0_DGSL_DEFVAL 0x00020000 -#define DDR_PHY_DX3GTR0_DGSL_SHIFT 0 -#define DDR_PHY_DX3GTR0_DGSL_MASK 0x0000001FU - -/*Calibration Bypass*/ +/* +* Calibration Bypass +*/ #undef DDR_PHY_DX4GCR0_CALBYP_DEFVAL #undef DDR_PHY_DX4GCR0_CALBYP_SHIFT #undef DDR_PHY_DX4GCR0_CALBYP_MASK -#define DDR_PHY_DX4GCR0_CALBYP_DEFVAL 0x40200204 -#define DDR_PHY_DX4GCR0_CALBYP_SHIFT 31 -#define DDR_PHY_DX4GCR0_CALBYP_MASK 0x80000000U +#define DDR_PHY_DX4GCR0_CALBYP_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_CALBYP_SHIFT 31 +#define DDR_PHY_DX4GCR0_CALBYP_MASK 0x80000000U -/*Master Delay Line Enable*/ +/* +* Master Delay Line Enable +*/ #undef DDR_PHY_DX4GCR0_MDLEN_DEFVAL #undef DDR_PHY_DX4GCR0_MDLEN_SHIFT #undef DDR_PHY_DX4GCR0_MDLEN_MASK -#define DDR_PHY_DX4GCR0_MDLEN_DEFVAL 0x40200204 -#define DDR_PHY_DX4GCR0_MDLEN_SHIFT 30 -#define DDR_PHY_DX4GCR0_MDLEN_MASK 0x40000000U +#define DDR_PHY_DX4GCR0_MDLEN_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_MDLEN_SHIFT 30 +#define DDR_PHY_DX4GCR0_MDLEN_MASK 0x40000000U -/*Configurable ODT(TE) Phase Shift*/ +/* +* Configurable ODT(TE) Phase Shift +*/ #undef DDR_PHY_DX4GCR0_CODTSHFT_DEFVAL #undef DDR_PHY_DX4GCR0_CODTSHFT_SHIFT #undef DDR_PHY_DX4GCR0_CODTSHFT_MASK -#define DDR_PHY_DX4GCR0_CODTSHFT_DEFVAL 0x40200204 -#define DDR_PHY_DX4GCR0_CODTSHFT_SHIFT 28 -#define DDR_PHY_DX4GCR0_CODTSHFT_MASK 0x30000000U +#define DDR_PHY_DX4GCR0_CODTSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_CODTSHFT_SHIFT 28 +#define DDR_PHY_DX4GCR0_CODTSHFT_MASK 0x30000000U -/*DQS Duty Cycle Correction*/ +/* +* DQS Duty Cycle Correction +*/ #undef DDR_PHY_DX4GCR0_DQSDCC_DEFVAL #undef DDR_PHY_DX4GCR0_DQSDCC_SHIFT #undef DDR_PHY_DX4GCR0_DQSDCC_MASK -#define DDR_PHY_DX4GCR0_DQSDCC_DEFVAL 0x40200204 -#define DDR_PHY_DX4GCR0_DQSDCC_SHIFT 24 -#define DDR_PHY_DX4GCR0_DQSDCC_MASK 0x0F000000U +#define DDR_PHY_DX4GCR0_DQSDCC_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_DQSDCC_SHIFT 24 +#define DDR_PHY_DX4GCR0_DQSDCC_MASK 0x0F000000U -/*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/ +/* +* Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY +*/ #undef DDR_PHY_DX4GCR0_RDDLY_DEFVAL #undef DDR_PHY_DX4GCR0_RDDLY_SHIFT #undef DDR_PHY_DX4GCR0_RDDLY_MASK -#define DDR_PHY_DX4GCR0_RDDLY_DEFVAL 0x40200204 -#define DDR_PHY_DX4GCR0_RDDLY_SHIFT 20 -#define DDR_PHY_DX4GCR0_RDDLY_MASK 0x00F00000U +#define DDR_PHY_DX4GCR0_RDDLY_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_RDDLY_SHIFT 20 +#define DDR_PHY_DX4GCR0_RDDLY_MASK 0x00F00000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX4GCR0_RESERVED_19_14_DEFVAL #undef DDR_PHY_DX4GCR0_RESERVED_19_14_SHIFT #undef DDR_PHY_DX4GCR0_RESERVED_19_14_MASK -#define DDR_PHY_DX4GCR0_RESERVED_19_14_DEFVAL 0x40200204 -#define DDR_PHY_DX4GCR0_RESERVED_19_14_SHIFT 14 -#define DDR_PHY_DX4GCR0_RESERVED_19_14_MASK 0x000FC000U +#define DDR_PHY_DX4GCR0_RESERVED_19_14_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_RESERVED_19_14_SHIFT 14 +#define DDR_PHY_DX4GCR0_RESERVED_19_14_MASK 0x000FC000U -/*DQSNSE Power Down Receiver*/ +/* +* DQSNSE Power Down Receiver +*/ #undef DDR_PHY_DX4GCR0_DQSNSEPDR_DEFVAL #undef DDR_PHY_DX4GCR0_DQSNSEPDR_SHIFT #undef DDR_PHY_DX4GCR0_DQSNSEPDR_MASK -#define DDR_PHY_DX4GCR0_DQSNSEPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX4GCR0_DQSNSEPDR_SHIFT 13 -#define DDR_PHY_DX4GCR0_DQSNSEPDR_MASK 0x00002000U +#define DDR_PHY_DX4GCR0_DQSNSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_DQSNSEPDR_SHIFT 13 +#define DDR_PHY_DX4GCR0_DQSNSEPDR_MASK 0x00002000U -/*DQSSE Power Down Receiver*/ +/* +* DQSSE Power Down Receiver +*/ #undef DDR_PHY_DX4GCR0_DQSSEPDR_DEFVAL #undef DDR_PHY_DX4GCR0_DQSSEPDR_SHIFT #undef DDR_PHY_DX4GCR0_DQSSEPDR_MASK -#define DDR_PHY_DX4GCR0_DQSSEPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX4GCR0_DQSSEPDR_SHIFT 12 -#define DDR_PHY_DX4GCR0_DQSSEPDR_MASK 0x00001000U +#define DDR_PHY_DX4GCR0_DQSSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_DQSSEPDR_SHIFT 12 +#define DDR_PHY_DX4GCR0_DQSSEPDR_MASK 0x00001000U -/*RTT On Additive Latency*/ +/* +* RTT On Additive Latency +*/ #undef DDR_PHY_DX4GCR0_RTTOAL_DEFVAL #undef DDR_PHY_DX4GCR0_RTTOAL_SHIFT #undef DDR_PHY_DX4GCR0_RTTOAL_MASK -#define DDR_PHY_DX4GCR0_RTTOAL_DEFVAL 0x40200204 -#define DDR_PHY_DX4GCR0_RTTOAL_SHIFT 11 -#define DDR_PHY_DX4GCR0_RTTOAL_MASK 0x00000800U +#define DDR_PHY_DX4GCR0_RTTOAL_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_RTTOAL_SHIFT 11 +#define DDR_PHY_DX4GCR0_RTTOAL_MASK 0x00000800U -/*RTT Output Hold*/ +/* +* RTT Output Hold +*/ #undef DDR_PHY_DX4GCR0_RTTOH_DEFVAL #undef DDR_PHY_DX4GCR0_RTTOH_SHIFT #undef DDR_PHY_DX4GCR0_RTTOH_MASK -#define DDR_PHY_DX4GCR0_RTTOH_DEFVAL 0x40200204 -#define DDR_PHY_DX4GCR0_RTTOH_SHIFT 9 -#define DDR_PHY_DX4GCR0_RTTOH_MASK 0x00000600U +#define DDR_PHY_DX4GCR0_RTTOH_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_RTTOH_SHIFT 9 +#define DDR_PHY_DX4GCR0_RTTOH_MASK 0x00000600U -/*Configurable PDR Phase Shift*/ +/* +* Configurable PDR Phase Shift +*/ #undef DDR_PHY_DX4GCR0_CPDRSHFT_DEFVAL #undef DDR_PHY_DX4GCR0_CPDRSHFT_SHIFT #undef DDR_PHY_DX4GCR0_CPDRSHFT_MASK -#define DDR_PHY_DX4GCR0_CPDRSHFT_DEFVAL 0x40200204 -#define DDR_PHY_DX4GCR0_CPDRSHFT_SHIFT 7 -#define DDR_PHY_DX4GCR0_CPDRSHFT_MASK 0x00000180U +#define DDR_PHY_DX4GCR0_CPDRSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_CPDRSHFT_SHIFT 7 +#define DDR_PHY_DX4GCR0_CPDRSHFT_MASK 0x00000180U -/*DQSR Power Down*/ +/* +* DQSR Power Down +*/ #undef DDR_PHY_DX4GCR0_DQSRPD_DEFVAL #undef DDR_PHY_DX4GCR0_DQSRPD_SHIFT #undef DDR_PHY_DX4GCR0_DQSRPD_MASK -#define DDR_PHY_DX4GCR0_DQSRPD_DEFVAL 0x40200204 -#define DDR_PHY_DX4GCR0_DQSRPD_SHIFT 6 -#define DDR_PHY_DX4GCR0_DQSRPD_MASK 0x00000040U +#define DDR_PHY_DX4GCR0_DQSRPD_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_DQSRPD_SHIFT 6 +#define DDR_PHY_DX4GCR0_DQSRPD_MASK 0x00000040U -/*DQSG Power Down Receiver*/ +/* +* DQSG Power Down Receiver +*/ #undef DDR_PHY_DX4GCR0_DQSGPDR_DEFVAL #undef DDR_PHY_DX4GCR0_DQSGPDR_SHIFT #undef DDR_PHY_DX4GCR0_DQSGPDR_MASK -#define DDR_PHY_DX4GCR0_DQSGPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX4GCR0_DQSGPDR_SHIFT 5 -#define DDR_PHY_DX4GCR0_DQSGPDR_MASK 0x00000020U +#define DDR_PHY_DX4GCR0_DQSGPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_DQSGPDR_SHIFT 5 +#define DDR_PHY_DX4GCR0_DQSGPDR_MASK 0x00000020U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX4GCR0_RESERVED_4_DEFVAL #undef DDR_PHY_DX4GCR0_RESERVED_4_SHIFT #undef DDR_PHY_DX4GCR0_RESERVED_4_MASK -#define DDR_PHY_DX4GCR0_RESERVED_4_DEFVAL 0x40200204 -#define DDR_PHY_DX4GCR0_RESERVED_4_SHIFT 4 -#define DDR_PHY_DX4GCR0_RESERVED_4_MASK 0x00000010U +#define DDR_PHY_DX4GCR0_RESERVED_4_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_RESERVED_4_SHIFT 4 +#define DDR_PHY_DX4GCR0_RESERVED_4_MASK 0x00000010U -/*DQSG On-Die Termination*/ +/* +* DQSG On-Die Termination +*/ #undef DDR_PHY_DX4GCR0_DQSGODT_DEFVAL #undef DDR_PHY_DX4GCR0_DQSGODT_SHIFT #undef DDR_PHY_DX4GCR0_DQSGODT_MASK -#define DDR_PHY_DX4GCR0_DQSGODT_DEFVAL 0x40200204 -#define DDR_PHY_DX4GCR0_DQSGODT_SHIFT 3 -#define DDR_PHY_DX4GCR0_DQSGODT_MASK 0x00000008U +#define DDR_PHY_DX4GCR0_DQSGODT_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_DQSGODT_SHIFT 3 +#define DDR_PHY_DX4GCR0_DQSGODT_MASK 0x00000008U -/*DQSG Output Enable*/ +/* +* DQSG Output Enable +*/ #undef DDR_PHY_DX4GCR0_DQSGOE_DEFVAL #undef DDR_PHY_DX4GCR0_DQSGOE_SHIFT #undef DDR_PHY_DX4GCR0_DQSGOE_MASK -#define DDR_PHY_DX4GCR0_DQSGOE_DEFVAL 0x40200204 -#define DDR_PHY_DX4GCR0_DQSGOE_SHIFT 2 -#define DDR_PHY_DX4GCR0_DQSGOE_MASK 0x00000004U +#define DDR_PHY_DX4GCR0_DQSGOE_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_DQSGOE_SHIFT 2 +#define DDR_PHY_DX4GCR0_DQSGOE_MASK 0x00000004U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX4GCR0_RESERVED_1_0_DEFVAL #undef DDR_PHY_DX4GCR0_RESERVED_1_0_SHIFT #undef DDR_PHY_DX4GCR0_RESERVED_1_0_MASK -#define DDR_PHY_DX4GCR0_RESERVED_1_0_DEFVAL 0x40200204 -#define DDR_PHY_DX4GCR0_RESERVED_1_0_SHIFT 0 -#define DDR_PHY_DX4GCR0_RESERVED_1_0_MASK 0x00000003U +#define DDR_PHY_DX4GCR0_RESERVED_1_0_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_RESERVED_1_0_SHIFT 0 +#define DDR_PHY_DX4GCR0_RESERVED_1_0_MASK 0x00000003U -/*Enables the PDR mode for DQ[7:0]*/ +/* +* Enables the PDR mode for DQ[7:0] +*/ #undef DDR_PHY_DX4GCR1_DXPDRMODE_DEFVAL #undef DDR_PHY_DX4GCR1_DXPDRMODE_SHIFT #undef DDR_PHY_DX4GCR1_DXPDRMODE_MASK -#define DDR_PHY_DX4GCR1_DXPDRMODE_DEFVAL 0x00007FFF -#define DDR_PHY_DX4GCR1_DXPDRMODE_SHIFT 16 -#define DDR_PHY_DX4GCR1_DXPDRMODE_MASK 0xFFFF0000U +#define DDR_PHY_DX4GCR1_DXPDRMODE_DEFVAL 0x00007FFF +#define DDR_PHY_DX4GCR1_DXPDRMODE_SHIFT 16 +#define DDR_PHY_DX4GCR1_DXPDRMODE_MASK 0xFFFF0000U -/*Reserved. Returns zeroes on reads.*/ +/* +* Reserved. Returns zeroes on reads. +*/ #undef DDR_PHY_DX4GCR1_RESERVED_15_DEFVAL #undef DDR_PHY_DX4GCR1_RESERVED_15_SHIFT #undef DDR_PHY_DX4GCR1_RESERVED_15_MASK -#define DDR_PHY_DX4GCR1_RESERVED_15_DEFVAL 0x00007FFF -#define DDR_PHY_DX4GCR1_RESERVED_15_SHIFT 15 -#define DDR_PHY_DX4GCR1_RESERVED_15_MASK 0x00008000U +#define DDR_PHY_DX4GCR1_RESERVED_15_DEFVAL 0x00007FFF +#define DDR_PHY_DX4GCR1_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX4GCR1_RESERVED_15_MASK 0x00008000U -/*Select the delayed or non-delayed read data strobe #*/ +/* +* Select the delayed or non-delayed read data strobe # +*/ #undef DDR_PHY_DX4GCR1_QSNSEL_DEFVAL #undef DDR_PHY_DX4GCR1_QSNSEL_SHIFT #undef DDR_PHY_DX4GCR1_QSNSEL_MASK -#define DDR_PHY_DX4GCR1_QSNSEL_DEFVAL 0x00007FFF -#define DDR_PHY_DX4GCR1_QSNSEL_SHIFT 14 -#define DDR_PHY_DX4GCR1_QSNSEL_MASK 0x00004000U +#define DDR_PHY_DX4GCR1_QSNSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX4GCR1_QSNSEL_SHIFT 14 +#define DDR_PHY_DX4GCR1_QSNSEL_MASK 0x00004000U -/*Select the delayed or non-delayed read data strobe*/ +/* +* Select the delayed or non-delayed read data strobe +*/ #undef DDR_PHY_DX4GCR1_QSSEL_DEFVAL #undef DDR_PHY_DX4GCR1_QSSEL_SHIFT #undef DDR_PHY_DX4GCR1_QSSEL_MASK -#define DDR_PHY_DX4GCR1_QSSEL_DEFVAL 0x00007FFF -#define DDR_PHY_DX4GCR1_QSSEL_SHIFT 13 -#define DDR_PHY_DX4GCR1_QSSEL_MASK 0x00002000U +#define DDR_PHY_DX4GCR1_QSSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX4GCR1_QSSEL_SHIFT 13 +#define DDR_PHY_DX4GCR1_QSSEL_MASK 0x00002000U -/*Enables Read Data Strobe in a byte lane*/ +/* +* Enables Read Data Strobe in a byte lane +*/ #undef DDR_PHY_DX4GCR1_OEEN_DEFVAL #undef DDR_PHY_DX4GCR1_OEEN_SHIFT #undef DDR_PHY_DX4GCR1_OEEN_MASK -#define DDR_PHY_DX4GCR1_OEEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX4GCR1_OEEN_SHIFT 12 -#define DDR_PHY_DX4GCR1_OEEN_MASK 0x00001000U +#define DDR_PHY_DX4GCR1_OEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX4GCR1_OEEN_SHIFT 12 +#define DDR_PHY_DX4GCR1_OEEN_MASK 0x00001000U -/*Enables PDR in a byte lane*/ +/* +* Enables PDR in a byte lane +*/ #undef DDR_PHY_DX4GCR1_PDREN_DEFVAL #undef DDR_PHY_DX4GCR1_PDREN_SHIFT #undef DDR_PHY_DX4GCR1_PDREN_MASK -#define DDR_PHY_DX4GCR1_PDREN_DEFVAL 0x00007FFF -#define DDR_PHY_DX4GCR1_PDREN_SHIFT 11 -#define DDR_PHY_DX4GCR1_PDREN_MASK 0x00000800U +#define DDR_PHY_DX4GCR1_PDREN_DEFVAL 0x00007FFF +#define DDR_PHY_DX4GCR1_PDREN_SHIFT 11 +#define DDR_PHY_DX4GCR1_PDREN_MASK 0x00000800U -/*Enables ODT/TE in a byte lane*/ +/* +* Enables ODT/TE in a byte lane +*/ #undef DDR_PHY_DX4GCR1_TEEN_DEFVAL #undef DDR_PHY_DX4GCR1_TEEN_SHIFT #undef DDR_PHY_DX4GCR1_TEEN_MASK -#define DDR_PHY_DX4GCR1_TEEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX4GCR1_TEEN_SHIFT 10 -#define DDR_PHY_DX4GCR1_TEEN_MASK 0x00000400U +#define DDR_PHY_DX4GCR1_TEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX4GCR1_TEEN_SHIFT 10 +#define DDR_PHY_DX4GCR1_TEEN_MASK 0x00000400U -/*Enables Write Data strobe in a byte lane*/ +/* +* Enables Write Data strobe in a byte lane +*/ #undef DDR_PHY_DX4GCR1_DSEN_DEFVAL #undef DDR_PHY_DX4GCR1_DSEN_SHIFT #undef DDR_PHY_DX4GCR1_DSEN_MASK -#define DDR_PHY_DX4GCR1_DSEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX4GCR1_DSEN_SHIFT 9 -#define DDR_PHY_DX4GCR1_DSEN_MASK 0x00000200U +#define DDR_PHY_DX4GCR1_DSEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX4GCR1_DSEN_SHIFT 9 +#define DDR_PHY_DX4GCR1_DSEN_MASK 0x00000200U -/*Enables DM pin in a byte lane*/ +/* +* Enables DM pin in a byte lane +*/ #undef DDR_PHY_DX4GCR1_DMEN_DEFVAL #undef DDR_PHY_DX4GCR1_DMEN_SHIFT #undef DDR_PHY_DX4GCR1_DMEN_MASK -#define DDR_PHY_DX4GCR1_DMEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX4GCR1_DMEN_SHIFT 8 -#define DDR_PHY_DX4GCR1_DMEN_MASK 0x00000100U +#define DDR_PHY_DX4GCR1_DMEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX4GCR1_DMEN_SHIFT 8 +#define DDR_PHY_DX4GCR1_DMEN_MASK 0x00000100U -/*Enables DQ corresponding to each bit in a byte*/ +/* +* Enables DQ corresponding to each bit in a byte +*/ #undef DDR_PHY_DX4GCR1_DQEN_DEFVAL #undef DDR_PHY_DX4GCR1_DQEN_SHIFT #undef DDR_PHY_DX4GCR1_DQEN_MASK -#define DDR_PHY_DX4GCR1_DQEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX4GCR1_DQEN_SHIFT 0 -#define DDR_PHY_DX4GCR1_DQEN_MASK 0x000000FFU +#define DDR_PHY_DX4GCR1_DQEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX4GCR1_DQEN_SHIFT 0 +#define DDR_PHY_DX4GCR1_DQEN_MASK 0x000000FFU -/*Byte lane VREF IOM (Used only by D4MU IOs)*/ +/* +* Byte lane VREF IOM (Used only by D4MU IOs) +*/ #undef DDR_PHY_DX4GCR4_RESERVED_31_29_DEFVAL #undef DDR_PHY_DX4GCR4_RESERVED_31_29_SHIFT #undef DDR_PHY_DX4GCR4_RESERVED_31_29_MASK -#define DDR_PHY_DX4GCR4_RESERVED_31_29_DEFVAL 0x0E00003C -#define DDR_PHY_DX4GCR4_RESERVED_31_29_SHIFT 29 -#define DDR_PHY_DX4GCR4_RESERVED_31_29_MASK 0xE0000000U +#define DDR_PHY_DX4GCR4_RESERVED_31_29_DEFVAL 0x0E00003C +#define DDR_PHY_DX4GCR4_RESERVED_31_29_SHIFT 29 +#define DDR_PHY_DX4GCR4_RESERVED_31_29_MASK 0xE0000000U -/*Byte Lane VREF Pad Enable*/ +/* +* Byte Lane VREF Pad Enable +*/ #undef DDR_PHY_DX4GCR4_DXREFPEN_DEFVAL #undef DDR_PHY_DX4GCR4_DXREFPEN_SHIFT #undef DDR_PHY_DX4GCR4_DXREFPEN_MASK -#define DDR_PHY_DX4GCR4_DXREFPEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX4GCR4_DXREFPEN_SHIFT 28 -#define DDR_PHY_DX4GCR4_DXREFPEN_MASK 0x10000000U +#define DDR_PHY_DX4GCR4_DXREFPEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX4GCR4_DXREFPEN_SHIFT 28 +#define DDR_PHY_DX4GCR4_DXREFPEN_MASK 0x10000000U -/*Byte Lane Internal VREF Enable*/ +/* +* Byte Lane Internal VREF Enable +*/ #undef DDR_PHY_DX4GCR4_DXREFEEN_DEFVAL #undef DDR_PHY_DX4GCR4_DXREFEEN_SHIFT #undef DDR_PHY_DX4GCR4_DXREFEEN_MASK -#define DDR_PHY_DX4GCR4_DXREFEEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX4GCR4_DXREFEEN_SHIFT 26 -#define DDR_PHY_DX4GCR4_DXREFEEN_MASK 0x0C000000U +#define DDR_PHY_DX4GCR4_DXREFEEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX4GCR4_DXREFEEN_SHIFT 26 +#define DDR_PHY_DX4GCR4_DXREFEEN_MASK 0x0C000000U -/*Byte Lane Single-End VREF Enable*/ +/* +* Byte Lane Single-End VREF Enable +*/ #undef DDR_PHY_DX4GCR4_DXREFSEN_DEFVAL #undef DDR_PHY_DX4GCR4_DXREFSEN_SHIFT #undef DDR_PHY_DX4GCR4_DXREFSEN_MASK -#define DDR_PHY_DX4GCR4_DXREFSEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX4GCR4_DXREFSEN_SHIFT 25 -#define DDR_PHY_DX4GCR4_DXREFSEN_MASK 0x02000000U +#define DDR_PHY_DX4GCR4_DXREFSEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX4GCR4_DXREFSEN_SHIFT 25 +#define DDR_PHY_DX4GCR4_DXREFSEN_MASK 0x02000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX4GCR4_RESERVED_24_DEFVAL #undef DDR_PHY_DX4GCR4_RESERVED_24_SHIFT #undef DDR_PHY_DX4GCR4_RESERVED_24_MASK -#define DDR_PHY_DX4GCR4_RESERVED_24_DEFVAL 0x0E00003C -#define DDR_PHY_DX4GCR4_RESERVED_24_SHIFT 24 -#define DDR_PHY_DX4GCR4_RESERVED_24_MASK 0x01000000U +#define DDR_PHY_DX4GCR4_RESERVED_24_DEFVAL 0x0E00003C +#define DDR_PHY_DX4GCR4_RESERVED_24_SHIFT 24 +#define DDR_PHY_DX4GCR4_RESERVED_24_MASK 0x01000000U -/*External VREF generator REFSEL range select*/ +/* +* External VREF generator REFSEL range select +*/ #undef DDR_PHY_DX4GCR4_DXREFESELRANGE_DEFVAL #undef DDR_PHY_DX4GCR4_DXREFESELRANGE_SHIFT #undef DDR_PHY_DX4GCR4_DXREFESELRANGE_MASK -#define DDR_PHY_DX4GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C -#define DDR_PHY_DX4GCR4_DXREFESELRANGE_SHIFT 23 -#define DDR_PHY_DX4GCR4_DXREFESELRANGE_MASK 0x00800000U +#define DDR_PHY_DX4GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX4GCR4_DXREFESELRANGE_SHIFT 23 +#define DDR_PHY_DX4GCR4_DXREFESELRANGE_MASK 0x00800000U -/*Byte Lane External VREF Select*/ +/* +* Byte Lane External VREF Select +*/ #undef DDR_PHY_DX4GCR4_DXREFESEL_DEFVAL #undef DDR_PHY_DX4GCR4_DXREFESEL_SHIFT #undef DDR_PHY_DX4GCR4_DXREFESEL_MASK -#define DDR_PHY_DX4GCR4_DXREFESEL_DEFVAL 0x0E00003C -#define DDR_PHY_DX4GCR4_DXREFESEL_SHIFT 16 -#define DDR_PHY_DX4GCR4_DXREFESEL_MASK 0x007F0000U +#define DDR_PHY_DX4GCR4_DXREFESEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX4GCR4_DXREFESEL_SHIFT 16 +#define DDR_PHY_DX4GCR4_DXREFESEL_MASK 0x007F0000U -/*Single ended VREF generator REFSEL range select*/ +/* +* Single ended VREF generator REFSEL range select +*/ #undef DDR_PHY_DX4GCR4_DXREFSSELRANGE_DEFVAL #undef DDR_PHY_DX4GCR4_DXREFSSELRANGE_SHIFT #undef DDR_PHY_DX4GCR4_DXREFSSELRANGE_MASK -#define DDR_PHY_DX4GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C -#define DDR_PHY_DX4GCR4_DXREFSSELRANGE_SHIFT 15 -#define DDR_PHY_DX4GCR4_DXREFSSELRANGE_MASK 0x00008000U +#define DDR_PHY_DX4GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX4GCR4_DXREFSSELRANGE_SHIFT 15 +#define DDR_PHY_DX4GCR4_DXREFSSELRANGE_MASK 0x00008000U -/*Byte Lane Single-End VREF Select*/ +/* +* Byte Lane Single-End VREF Select +*/ #undef DDR_PHY_DX4GCR4_DXREFSSEL_DEFVAL #undef DDR_PHY_DX4GCR4_DXREFSSEL_SHIFT #undef DDR_PHY_DX4GCR4_DXREFSSEL_MASK -#define DDR_PHY_DX4GCR4_DXREFSSEL_DEFVAL 0x0E00003C -#define DDR_PHY_DX4GCR4_DXREFSSEL_SHIFT 8 -#define DDR_PHY_DX4GCR4_DXREFSSEL_MASK 0x00007F00U +#define DDR_PHY_DX4GCR4_DXREFSSEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX4GCR4_DXREFSSEL_SHIFT 8 +#define DDR_PHY_DX4GCR4_DXREFSSEL_MASK 0x00007F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX4GCR4_RESERVED_7_6_DEFVAL #undef DDR_PHY_DX4GCR4_RESERVED_7_6_SHIFT #undef DDR_PHY_DX4GCR4_RESERVED_7_6_MASK -#define DDR_PHY_DX4GCR4_RESERVED_7_6_DEFVAL 0x0E00003C -#define DDR_PHY_DX4GCR4_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_DX4GCR4_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_DX4GCR4_RESERVED_7_6_DEFVAL 0x0E00003C +#define DDR_PHY_DX4GCR4_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX4GCR4_RESERVED_7_6_MASK 0x000000C0U -/*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/ +/* +* VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. +*/ #undef DDR_PHY_DX4GCR4_DXREFIEN_DEFVAL #undef DDR_PHY_DX4GCR4_DXREFIEN_SHIFT #undef DDR_PHY_DX4GCR4_DXREFIEN_MASK -#define DDR_PHY_DX4GCR4_DXREFIEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX4GCR4_DXREFIEN_SHIFT 2 -#define DDR_PHY_DX4GCR4_DXREFIEN_MASK 0x0000003CU +#define DDR_PHY_DX4GCR4_DXREFIEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX4GCR4_DXREFIEN_SHIFT 2 +#define DDR_PHY_DX4GCR4_DXREFIEN_MASK 0x0000003CU -/*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/ +/* +* VRMON control for DQ IO (Single Ended) buffers of a byte lane. +*/ #undef DDR_PHY_DX4GCR4_DXREFIMON_DEFVAL #undef DDR_PHY_DX4GCR4_DXREFIMON_SHIFT #undef DDR_PHY_DX4GCR4_DXREFIMON_MASK -#define DDR_PHY_DX4GCR4_DXREFIMON_DEFVAL 0x0E00003C -#define DDR_PHY_DX4GCR4_DXREFIMON_SHIFT 0 -#define DDR_PHY_DX4GCR4_DXREFIMON_MASK 0x00000003U +#define DDR_PHY_DX4GCR4_DXREFIMON_DEFVAL 0x0E00003C +#define DDR_PHY_DX4GCR4_DXREFIMON_SHIFT 0 +#define DDR_PHY_DX4GCR4_DXREFIMON_MASK 0x00000003U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX4GCR5_RESERVED_31_DEFVAL #undef DDR_PHY_DX4GCR5_RESERVED_31_SHIFT #undef DDR_PHY_DX4GCR5_RESERVED_31_MASK -#define DDR_PHY_DX4GCR5_RESERVED_31_DEFVAL 0x09090909 -#define DDR_PHY_DX4GCR5_RESERVED_31_SHIFT 31 -#define DDR_PHY_DX4GCR5_RESERVED_31_MASK 0x80000000U +#define DDR_PHY_DX4GCR5_RESERVED_31_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR5_RESERVED_31_SHIFT 31 +#define DDR_PHY_DX4GCR5_RESERVED_31_MASK 0x80000000U -/*Byte Lane internal VREF Select for Rank 3*/ +/* +* Byte Lane internal VREF Select for Rank 3 +*/ #undef DDR_PHY_DX4GCR5_DXREFISELR3_DEFVAL #undef DDR_PHY_DX4GCR5_DXREFISELR3_SHIFT #undef DDR_PHY_DX4GCR5_DXREFISELR3_MASK -#define DDR_PHY_DX4GCR5_DXREFISELR3_DEFVAL 0x09090909 -#define DDR_PHY_DX4GCR5_DXREFISELR3_SHIFT 24 -#define DDR_PHY_DX4GCR5_DXREFISELR3_MASK 0x7F000000U +#define DDR_PHY_DX4GCR5_DXREFISELR3_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR5_DXREFISELR3_SHIFT 24 +#define DDR_PHY_DX4GCR5_DXREFISELR3_MASK 0x7F000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX4GCR5_RESERVED_23_DEFVAL #undef DDR_PHY_DX4GCR5_RESERVED_23_SHIFT #undef DDR_PHY_DX4GCR5_RESERVED_23_MASK -#define DDR_PHY_DX4GCR5_RESERVED_23_DEFVAL 0x09090909 -#define DDR_PHY_DX4GCR5_RESERVED_23_SHIFT 23 -#define DDR_PHY_DX4GCR5_RESERVED_23_MASK 0x00800000U +#define DDR_PHY_DX4GCR5_RESERVED_23_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR5_RESERVED_23_SHIFT 23 +#define DDR_PHY_DX4GCR5_RESERVED_23_MASK 0x00800000U -/*Byte Lane internal VREF Select for Rank 2*/ +/* +* Byte Lane internal VREF Select for Rank 2 +*/ #undef DDR_PHY_DX4GCR5_DXREFISELR2_DEFVAL #undef DDR_PHY_DX4GCR5_DXREFISELR2_SHIFT #undef DDR_PHY_DX4GCR5_DXREFISELR2_MASK -#define DDR_PHY_DX4GCR5_DXREFISELR2_DEFVAL 0x09090909 -#define DDR_PHY_DX4GCR5_DXREFISELR2_SHIFT 16 -#define DDR_PHY_DX4GCR5_DXREFISELR2_MASK 0x007F0000U +#define DDR_PHY_DX4GCR5_DXREFISELR2_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR5_DXREFISELR2_SHIFT 16 +#define DDR_PHY_DX4GCR5_DXREFISELR2_MASK 0x007F0000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX4GCR5_RESERVED_15_DEFVAL #undef DDR_PHY_DX4GCR5_RESERVED_15_SHIFT #undef DDR_PHY_DX4GCR5_RESERVED_15_MASK -#define DDR_PHY_DX4GCR5_RESERVED_15_DEFVAL 0x09090909 -#define DDR_PHY_DX4GCR5_RESERVED_15_SHIFT 15 -#define DDR_PHY_DX4GCR5_RESERVED_15_MASK 0x00008000U +#define DDR_PHY_DX4GCR5_RESERVED_15_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR5_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX4GCR5_RESERVED_15_MASK 0x00008000U -/*Byte Lane internal VREF Select for Rank 1*/ +/* +* Byte Lane internal VREF Select for Rank 1 +*/ #undef DDR_PHY_DX4GCR5_DXREFISELR1_DEFVAL #undef DDR_PHY_DX4GCR5_DXREFISELR1_SHIFT #undef DDR_PHY_DX4GCR5_DXREFISELR1_MASK -#define DDR_PHY_DX4GCR5_DXREFISELR1_DEFVAL 0x09090909 -#define DDR_PHY_DX4GCR5_DXREFISELR1_SHIFT 8 -#define DDR_PHY_DX4GCR5_DXREFISELR1_MASK 0x00007F00U +#define DDR_PHY_DX4GCR5_DXREFISELR1_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR5_DXREFISELR1_SHIFT 8 +#define DDR_PHY_DX4GCR5_DXREFISELR1_MASK 0x00007F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX4GCR5_RESERVED_7_DEFVAL #undef DDR_PHY_DX4GCR5_RESERVED_7_SHIFT #undef DDR_PHY_DX4GCR5_RESERVED_7_MASK -#define DDR_PHY_DX4GCR5_RESERVED_7_DEFVAL 0x09090909 -#define DDR_PHY_DX4GCR5_RESERVED_7_SHIFT 7 -#define DDR_PHY_DX4GCR5_RESERVED_7_MASK 0x00000080U +#define DDR_PHY_DX4GCR5_RESERVED_7_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR5_RESERVED_7_SHIFT 7 +#define DDR_PHY_DX4GCR5_RESERVED_7_MASK 0x00000080U -/*Byte Lane internal VREF Select for Rank 0*/ +/* +* Byte Lane internal VREF Select for Rank 0 +*/ #undef DDR_PHY_DX4GCR5_DXREFISELR0_DEFVAL #undef DDR_PHY_DX4GCR5_DXREFISELR0_SHIFT #undef DDR_PHY_DX4GCR5_DXREFISELR0_MASK -#define DDR_PHY_DX4GCR5_DXREFISELR0_DEFVAL 0x09090909 -#define DDR_PHY_DX4GCR5_DXREFISELR0_SHIFT 0 -#define DDR_PHY_DX4GCR5_DXREFISELR0_MASK 0x0000007FU +#define DDR_PHY_DX4GCR5_DXREFISELR0_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR5_DXREFISELR0_SHIFT 0 +#define DDR_PHY_DX4GCR5_DXREFISELR0_MASK 0x0000007FU -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX4GCR6_RESERVED_31_30_DEFVAL #undef DDR_PHY_DX4GCR6_RESERVED_31_30_SHIFT #undef DDR_PHY_DX4GCR6_RESERVED_31_30_MASK -#define DDR_PHY_DX4GCR6_RESERVED_31_30_DEFVAL 0x09090909 -#define DDR_PHY_DX4GCR6_RESERVED_31_30_SHIFT 30 -#define DDR_PHY_DX4GCR6_RESERVED_31_30_MASK 0xC0000000U +#define DDR_PHY_DX4GCR6_RESERVED_31_30_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR6_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX4GCR6_RESERVED_31_30_MASK 0xC0000000U -/*DRAM DQ VREF Select for Rank3*/ +/* +* DRAM DQ VREF Select for Rank3 +*/ #undef DDR_PHY_DX4GCR6_DXDQVREFR3_DEFVAL #undef DDR_PHY_DX4GCR6_DXDQVREFR3_SHIFT #undef DDR_PHY_DX4GCR6_DXDQVREFR3_MASK -#define DDR_PHY_DX4GCR6_DXDQVREFR3_DEFVAL 0x09090909 -#define DDR_PHY_DX4GCR6_DXDQVREFR3_SHIFT 24 -#define DDR_PHY_DX4GCR6_DXDQVREFR3_MASK 0x3F000000U +#define DDR_PHY_DX4GCR6_DXDQVREFR3_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR6_DXDQVREFR3_SHIFT 24 +#define DDR_PHY_DX4GCR6_DXDQVREFR3_MASK 0x3F000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX4GCR6_RESERVED_23_22_DEFVAL #undef DDR_PHY_DX4GCR6_RESERVED_23_22_SHIFT #undef DDR_PHY_DX4GCR6_RESERVED_23_22_MASK -#define DDR_PHY_DX4GCR6_RESERVED_23_22_DEFVAL 0x09090909 -#define DDR_PHY_DX4GCR6_RESERVED_23_22_SHIFT 22 -#define DDR_PHY_DX4GCR6_RESERVED_23_22_MASK 0x00C00000U +#define DDR_PHY_DX4GCR6_RESERVED_23_22_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR6_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX4GCR6_RESERVED_23_22_MASK 0x00C00000U -/*DRAM DQ VREF Select for Rank2*/ +/* +* DRAM DQ VREF Select for Rank2 +*/ #undef DDR_PHY_DX4GCR6_DXDQVREFR2_DEFVAL #undef DDR_PHY_DX4GCR6_DXDQVREFR2_SHIFT #undef DDR_PHY_DX4GCR6_DXDQVREFR2_MASK -#define DDR_PHY_DX4GCR6_DXDQVREFR2_DEFVAL 0x09090909 -#define DDR_PHY_DX4GCR6_DXDQVREFR2_SHIFT 16 -#define DDR_PHY_DX4GCR6_DXDQVREFR2_MASK 0x003F0000U +#define DDR_PHY_DX4GCR6_DXDQVREFR2_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR6_DXDQVREFR2_SHIFT 16 +#define DDR_PHY_DX4GCR6_DXDQVREFR2_MASK 0x003F0000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX4GCR6_RESERVED_15_14_DEFVAL #undef DDR_PHY_DX4GCR6_RESERVED_15_14_SHIFT #undef DDR_PHY_DX4GCR6_RESERVED_15_14_MASK -#define DDR_PHY_DX4GCR6_RESERVED_15_14_DEFVAL 0x09090909 -#define DDR_PHY_DX4GCR6_RESERVED_15_14_SHIFT 14 -#define DDR_PHY_DX4GCR6_RESERVED_15_14_MASK 0x0000C000U +#define DDR_PHY_DX4GCR6_RESERVED_15_14_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR6_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_DX4GCR6_RESERVED_15_14_MASK 0x0000C000U -/*DRAM DQ VREF Select for Rank1*/ +/* +* DRAM DQ VREF Select for Rank1 +*/ #undef DDR_PHY_DX4GCR6_DXDQVREFR1_DEFVAL #undef DDR_PHY_DX4GCR6_DXDQVREFR1_SHIFT #undef DDR_PHY_DX4GCR6_DXDQVREFR1_MASK -#define DDR_PHY_DX4GCR6_DXDQVREFR1_DEFVAL 0x09090909 -#define DDR_PHY_DX4GCR6_DXDQVREFR1_SHIFT 8 -#define DDR_PHY_DX4GCR6_DXDQVREFR1_MASK 0x00003F00U +#define DDR_PHY_DX4GCR6_DXDQVREFR1_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR6_DXDQVREFR1_SHIFT 8 +#define DDR_PHY_DX4GCR6_DXDQVREFR1_MASK 0x00003F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX4GCR6_RESERVED_7_6_DEFVAL #undef DDR_PHY_DX4GCR6_RESERVED_7_6_SHIFT #undef DDR_PHY_DX4GCR6_RESERVED_7_6_MASK -#define DDR_PHY_DX4GCR6_RESERVED_7_6_DEFVAL 0x09090909 -#define DDR_PHY_DX4GCR6_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_DX4GCR6_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_DX4GCR6_RESERVED_7_6_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR6_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX4GCR6_RESERVED_7_6_MASK 0x000000C0U -/*DRAM DQ VREF Select for Rank0*/ +/* +* DRAM DQ VREF Select for Rank0 +*/ #undef DDR_PHY_DX4GCR6_DXDQVREFR0_DEFVAL #undef DDR_PHY_DX4GCR6_DXDQVREFR0_SHIFT #undef DDR_PHY_DX4GCR6_DXDQVREFR0_MASK -#define DDR_PHY_DX4GCR6_DXDQVREFR0_DEFVAL 0x09090909 -#define DDR_PHY_DX4GCR6_DXDQVREFR0_SHIFT 0 -#define DDR_PHY_DX4GCR6_DXDQVREFR0_MASK 0x0000003FU +#define DDR_PHY_DX4GCR6_DXDQVREFR0_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR6_DXDQVREFR0_SHIFT 0 +#define DDR_PHY_DX4GCR6_DXDQVREFR0_MASK 0x0000003FU -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX4LCDLR2_RESERVED_31_25_DEFVAL -#undef DDR_PHY_DX4LCDLR2_RESERVED_31_25_SHIFT -#undef DDR_PHY_DX4LCDLR2_RESERVED_31_25_MASK -#define DDR_PHY_DX4LCDLR2_RESERVED_31_25_DEFVAL 0x00000000 -#define DDR_PHY_DX4LCDLR2_RESERVED_31_25_SHIFT 25 -#define DDR_PHY_DX4LCDLR2_RESERVED_31_25_MASK 0xFE000000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX4LCDLR2_RESERVED_24_16_DEFVAL -#undef DDR_PHY_DX4LCDLR2_RESERVED_24_16_SHIFT -#undef DDR_PHY_DX4LCDLR2_RESERVED_24_16_MASK -#define DDR_PHY_DX4LCDLR2_RESERVED_24_16_DEFVAL 0x00000000 -#define DDR_PHY_DX4LCDLR2_RESERVED_24_16_SHIFT 16 -#define DDR_PHY_DX4LCDLR2_RESERVED_24_16_MASK 0x01FF0000U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX4LCDLR2_RESERVED_15_9_DEFVAL -#undef DDR_PHY_DX4LCDLR2_RESERVED_15_9_SHIFT -#undef DDR_PHY_DX4LCDLR2_RESERVED_15_9_MASK -#define DDR_PHY_DX4LCDLR2_RESERVED_15_9_DEFVAL 0x00000000 -#define DDR_PHY_DX4LCDLR2_RESERVED_15_9_SHIFT 9 -#define DDR_PHY_DX4LCDLR2_RESERVED_15_9_MASK 0x0000FE00U - -/*Read DQS Gating Delay*/ -#undef DDR_PHY_DX4LCDLR2_DQSGD_DEFVAL -#undef DDR_PHY_DX4LCDLR2_DQSGD_SHIFT -#undef DDR_PHY_DX4LCDLR2_DQSGD_MASK -#define DDR_PHY_DX4LCDLR2_DQSGD_DEFVAL 0x00000000 -#define DDR_PHY_DX4LCDLR2_DQSGD_SHIFT 0 -#define DDR_PHY_DX4LCDLR2_DQSGD_MASK 0x000001FFU - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX4GTR0_RESERVED_31_24_DEFVAL -#undef DDR_PHY_DX4GTR0_RESERVED_31_24_SHIFT -#undef DDR_PHY_DX4GTR0_RESERVED_31_24_MASK -#define DDR_PHY_DX4GTR0_RESERVED_31_24_DEFVAL 0x00020000 -#define DDR_PHY_DX4GTR0_RESERVED_31_24_SHIFT 27 -#define DDR_PHY_DX4GTR0_RESERVED_31_24_MASK 0xF8000000U - -/*DQ Write Path Latency Pipeline*/ -#undef DDR_PHY_DX4GTR0_WDQSL_DEFVAL -#undef DDR_PHY_DX4GTR0_WDQSL_SHIFT -#undef DDR_PHY_DX4GTR0_WDQSL_MASK -#define DDR_PHY_DX4GTR0_WDQSL_DEFVAL 0x00020000 -#define DDR_PHY_DX4GTR0_WDQSL_SHIFT 24 -#define DDR_PHY_DX4GTR0_WDQSL_MASK 0x07000000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX4GTR0_RESERVED_23_20_DEFVAL -#undef DDR_PHY_DX4GTR0_RESERVED_23_20_SHIFT -#undef DDR_PHY_DX4GTR0_RESERVED_23_20_MASK -#define DDR_PHY_DX4GTR0_RESERVED_23_20_DEFVAL 0x00020000 -#define DDR_PHY_DX4GTR0_RESERVED_23_20_SHIFT 20 -#define DDR_PHY_DX4GTR0_RESERVED_23_20_MASK 0x00F00000U - -/*Write Leveling System Latency*/ -#undef DDR_PHY_DX4GTR0_WLSL_DEFVAL -#undef DDR_PHY_DX4GTR0_WLSL_SHIFT -#undef DDR_PHY_DX4GTR0_WLSL_MASK -#define DDR_PHY_DX4GTR0_WLSL_DEFVAL 0x00020000 -#define DDR_PHY_DX4GTR0_WLSL_SHIFT 16 -#define DDR_PHY_DX4GTR0_WLSL_MASK 0x000F0000U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX4GTR0_RESERVED_15_13_DEFVAL -#undef DDR_PHY_DX4GTR0_RESERVED_15_13_SHIFT -#undef DDR_PHY_DX4GTR0_RESERVED_15_13_MASK -#define DDR_PHY_DX4GTR0_RESERVED_15_13_DEFVAL 0x00020000 -#define DDR_PHY_DX4GTR0_RESERVED_15_13_SHIFT 13 -#define DDR_PHY_DX4GTR0_RESERVED_15_13_MASK 0x0000E000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX4GTR0_RESERVED_12_8_DEFVAL -#undef DDR_PHY_DX4GTR0_RESERVED_12_8_SHIFT -#undef DDR_PHY_DX4GTR0_RESERVED_12_8_MASK -#define DDR_PHY_DX4GTR0_RESERVED_12_8_DEFVAL 0x00020000 -#define DDR_PHY_DX4GTR0_RESERVED_12_8_SHIFT 8 -#define DDR_PHY_DX4GTR0_RESERVED_12_8_MASK 0x00001F00U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX4GTR0_RESERVED_7_5_DEFVAL -#undef DDR_PHY_DX4GTR0_RESERVED_7_5_SHIFT -#undef DDR_PHY_DX4GTR0_RESERVED_7_5_MASK -#define DDR_PHY_DX4GTR0_RESERVED_7_5_DEFVAL 0x00020000 -#define DDR_PHY_DX4GTR0_RESERVED_7_5_SHIFT 5 -#define DDR_PHY_DX4GTR0_RESERVED_7_5_MASK 0x000000E0U - -/*DQS Gating System Latency*/ -#undef DDR_PHY_DX4GTR0_DGSL_DEFVAL -#undef DDR_PHY_DX4GTR0_DGSL_SHIFT -#undef DDR_PHY_DX4GTR0_DGSL_MASK -#define DDR_PHY_DX4GTR0_DGSL_DEFVAL 0x00020000 -#define DDR_PHY_DX4GTR0_DGSL_SHIFT 0 -#define DDR_PHY_DX4GTR0_DGSL_MASK 0x0000001FU - -/*Calibration Bypass*/ +/* +* Calibration Bypass +*/ #undef DDR_PHY_DX5GCR0_CALBYP_DEFVAL #undef DDR_PHY_DX5GCR0_CALBYP_SHIFT #undef DDR_PHY_DX5GCR0_CALBYP_MASK -#define DDR_PHY_DX5GCR0_CALBYP_DEFVAL 0x40200204 -#define DDR_PHY_DX5GCR0_CALBYP_SHIFT 31 -#define DDR_PHY_DX5GCR0_CALBYP_MASK 0x80000000U +#define DDR_PHY_DX5GCR0_CALBYP_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_CALBYP_SHIFT 31 +#define DDR_PHY_DX5GCR0_CALBYP_MASK 0x80000000U -/*Master Delay Line Enable*/ +/* +* Master Delay Line Enable +*/ #undef DDR_PHY_DX5GCR0_MDLEN_DEFVAL #undef DDR_PHY_DX5GCR0_MDLEN_SHIFT #undef DDR_PHY_DX5GCR0_MDLEN_MASK -#define DDR_PHY_DX5GCR0_MDLEN_DEFVAL 0x40200204 -#define DDR_PHY_DX5GCR0_MDLEN_SHIFT 30 -#define DDR_PHY_DX5GCR0_MDLEN_MASK 0x40000000U +#define DDR_PHY_DX5GCR0_MDLEN_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_MDLEN_SHIFT 30 +#define DDR_PHY_DX5GCR0_MDLEN_MASK 0x40000000U -/*Configurable ODT(TE) Phase Shift*/ +/* +* Configurable ODT(TE) Phase Shift +*/ #undef DDR_PHY_DX5GCR0_CODTSHFT_DEFVAL #undef DDR_PHY_DX5GCR0_CODTSHFT_SHIFT #undef DDR_PHY_DX5GCR0_CODTSHFT_MASK -#define DDR_PHY_DX5GCR0_CODTSHFT_DEFVAL 0x40200204 -#define DDR_PHY_DX5GCR0_CODTSHFT_SHIFT 28 -#define DDR_PHY_DX5GCR0_CODTSHFT_MASK 0x30000000U +#define DDR_PHY_DX5GCR0_CODTSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_CODTSHFT_SHIFT 28 +#define DDR_PHY_DX5GCR0_CODTSHFT_MASK 0x30000000U -/*DQS Duty Cycle Correction*/ +/* +* DQS Duty Cycle Correction +*/ #undef DDR_PHY_DX5GCR0_DQSDCC_DEFVAL #undef DDR_PHY_DX5GCR0_DQSDCC_SHIFT #undef DDR_PHY_DX5GCR0_DQSDCC_MASK -#define DDR_PHY_DX5GCR0_DQSDCC_DEFVAL 0x40200204 -#define DDR_PHY_DX5GCR0_DQSDCC_SHIFT 24 -#define DDR_PHY_DX5GCR0_DQSDCC_MASK 0x0F000000U +#define DDR_PHY_DX5GCR0_DQSDCC_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_DQSDCC_SHIFT 24 +#define DDR_PHY_DX5GCR0_DQSDCC_MASK 0x0F000000U -/*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/ +/* +* Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY +*/ #undef DDR_PHY_DX5GCR0_RDDLY_DEFVAL #undef DDR_PHY_DX5GCR0_RDDLY_SHIFT #undef DDR_PHY_DX5GCR0_RDDLY_MASK -#define DDR_PHY_DX5GCR0_RDDLY_DEFVAL 0x40200204 -#define DDR_PHY_DX5GCR0_RDDLY_SHIFT 20 -#define DDR_PHY_DX5GCR0_RDDLY_MASK 0x00F00000U +#define DDR_PHY_DX5GCR0_RDDLY_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_RDDLY_SHIFT 20 +#define DDR_PHY_DX5GCR0_RDDLY_MASK 0x00F00000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX5GCR0_RESERVED_19_14_DEFVAL #undef DDR_PHY_DX5GCR0_RESERVED_19_14_SHIFT #undef DDR_PHY_DX5GCR0_RESERVED_19_14_MASK -#define DDR_PHY_DX5GCR0_RESERVED_19_14_DEFVAL 0x40200204 -#define DDR_PHY_DX5GCR0_RESERVED_19_14_SHIFT 14 -#define DDR_PHY_DX5GCR0_RESERVED_19_14_MASK 0x000FC000U +#define DDR_PHY_DX5GCR0_RESERVED_19_14_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_RESERVED_19_14_SHIFT 14 +#define DDR_PHY_DX5GCR0_RESERVED_19_14_MASK 0x000FC000U -/*DQSNSE Power Down Receiver*/ +/* +* DQSNSE Power Down Receiver +*/ #undef DDR_PHY_DX5GCR0_DQSNSEPDR_DEFVAL #undef DDR_PHY_DX5GCR0_DQSNSEPDR_SHIFT #undef DDR_PHY_DX5GCR0_DQSNSEPDR_MASK -#define DDR_PHY_DX5GCR0_DQSNSEPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX5GCR0_DQSNSEPDR_SHIFT 13 -#define DDR_PHY_DX5GCR0_DQSNSEPDR_MASK 0x00002000U +#define DDR_PHY_DX5GCR0_DQSNSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_DQSNSEPDR_SHIFT 13 +#define DDR_PHY_DX5GCR0_DQSNSEPDR_MASK 0x00002000U -/*DQSSE Power Down Receiver*/ +/* +* DQSSE Power Down Receiver +*/ #undef DDR_PHY_DX5GCR0_DQSSEPDR_DEFVAL #undef DDR_PHY_DX5GCR0_DQSSEPDR_SHIFT #undef DDR_PHY_DX5GCR0_DQSSEPDR_MASK -#define DDR_PHY_DX5GCR0_DQSSEPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX5GCR0_DQSSEPDR_SHIFT 12 -#define DDR_PHY_DX5GCR0_DQSSEPDR_MASK 0x00001000U +#define DDR_PHY_DX5GCR0_DQSSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_DQSSEPDR_SHIFT 12 +#define DDR_PHY_DX5GCR0_DQSSEPDR_MASK 0x00001000U -/*RTT On Additive Latency*/ +/* +* RTT On Additive Latency +*/ #undef DDR_PHY_DX5GCR0_RTTOAL_DEFVAL #undef DDR_PHY_DX5GCR0_RTTOAL_SHIFT #undef DDR_PHY_DX5GCR0_RTTOAL_MASK -#define DDR_PHY_DX5GCR0_RTTOAL_DEFVAL 0x40200204 -#define DDR_PHY_DX5GCR0_RTTOAL_SHIFT 11 -#define DDR_PHY_DX5GCR0_RTTOAL_MASK 0x00000800U +#define DDR_PHY_DX5GCR0_RTTOAL_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_RTTOAL_SHIFT 11 +#define DDR_PHY_DX5GCR0_RTTOAL_MASK 0x00000800U -/*RTT Output Hold*/ +/* +* RTT Output Hold +*/ #undef DDR_PHY_DX5GCR0_RTTOH_DEFVAL #undef DDR_PHY_DX5GCR0_RTTOH_SHIFT #undef DDR_PHY_DX5GCR0_RTTOH_MASK -#define DDR_PHY_DX5GCR0_RTTOH_DEFVAL 0x40200204 -#define DDR_PHY_DX5GCR0_RTTOH_SHIFT 9 -#define DDR_PHY_DX5GCR0_RTTOH_MASK 0x00000600U +#define DDR_PHY_DX5GCR0_RTTOH_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_RTTOH_SHIFT 9 +#define DDR_PHY_DX5GCR0_RTTOH_MASK 0x00000600U -/*Configurable PDR Phase Shift*/ +/* +* Configurable PDR Phase Shift +*/ #undef DDR_PHY_DX5GCR0_CPDRSHFT_DEFVAL #undef DDR_PHY_DX5GCR0_CPDRSHFT_SHIFT #undef DDR_PHY_DX5GCR0_CPDRSHFT_MASK -#define DDR_PHY_DX5GCR0_CPDRSHFT_DEFVAL 0x40200204 -#define DDR_PHY_DX5GCR0_CPDRSHFT_SHIFT 7 -#define DDR_PHY_DX5GCR0_CPDRSHFT_MASK 0x00000180U +#define DDR_PHY_DX5GCR0_CPDRSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_CPDRSHFT_SHIFT 7 +#define DDR_PHY_DX5GCR0_CPDRSHFT_MASK 0x00000180U -/*DQSR Power Down*/ +/* +* DQSR Power Down +*/ #undef DDR_PHY_DX5GCR0_DQSRPD_DEFVAL #undef DDR_PHY_DX5GCR0_DQSRPD_SHIFT #undef DDR_PHY_DX5GCR0_DQSRPD_MASK -#define DDR_PHY_DX5GCR0_DQSRPD_DEFVAL 0x40200204 -#define DDR_PHY_DX5GCR0_DQSRPD_SHIFT 6 -#define DDR_PHY_DX5GCR0_DQSRPD_MASK 0x00000040U +#define DDR_PHY_DX5GCR0_DQSRPD_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_DQSRPD_SHIFT 6 +#define DDR_PHY_DX5GCR0_DQSRPD_MASK 0x00000040U -/*DQSG Power Down Receiver*/ +/* +* DQSG Power Down Receiver +*/ #undef DDR_PHY_DX5GCR0_DQSGPDR_DEFVAL #undef DDR_PHY_DX5GCR0_DQSGPDR_SHIFT #undef DDR_PHY_DX5GCR0_DQSGPDR_MASK -#define DDR_PHY_DX5GCR0_DQSGPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX5GCR0_DQSGPDR_SHIFT 5 -#define DDR_PHY_DX5GCR0_DQSGPDR_MASK 0x00000020U +#define DDR_PHY_DX5GCR0_DQSGPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_DQSGPDR_SHIFT 5 +#define DDR_PHY_DX5GCR0_DQSGPDR_MASK 0x00000020U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX5GCR0_RESERVED_4_DEFVAL #undef DDR_PHY_DX5GCR0_RESERVED_4_SHIFT #undef DDR_PHY_DX5GCR0_RESERVED_4_MASK -#define DDR_PHY_DX5GCR0_RESERVED_4_DEFVAL 0x40200204 -#define DDR_PHY_DX5GCR0_RESERVED_4_SHIFT 4 -#define DDR_PHY_DX5GCR0_RESERVED_4_MASK 0x00000010U +#define DDR_PHY_DX5GCR0_RESERVED_4_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_RESERVED_4_SHIFT 4 +#define DDR_PHY_DX5GCR0_RESERVED_4_MASK 0x00000010U -/*DQSG On-Die Termination*/ +/* +* DQSG On-Die Termination +*/ #undef DDR_PHY_DX5GCR0_DQSGODT_DEFVAL #undef DDR_PHY_DX5GCR0_DQSGODT_SHIFT #undef DDR_PHY_DX5GCR0_DQSGODT_MASK -#define DDR_PHY_DX5GCR0_DQSGODT_DEFVAL 0x40200204 -#define DDR_PHY_DX5GCR0_DQSGODT_SHIFT 3 -#define DDR_PHY_DX5GCR0_DQSGODT_MASK 0x00000008U +#define DDR_PHY_DX5GCR0_DQSGODT_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_DQSGODT_SHIFT 3 +#define DDR_PHY_DX5GCR0_DQSGODT_MASK 0x00000008U -/*DQSG Output Enable*/ +/* +* DQSG Output Enable +*/ #undef DDR_PHY_DX5GCR0_DQSGOE_DEFVAL #undef DDR_PHY_DX5GCR0_DQSGOE_SHIFT #undef DDR_PHY_DX5GCR0_DQSGOE_MASK -#define DDR_PHY_DX5GCR0_DQSGOE_DEFVAL 0x40200204 -#define DDR_PHY_DX5GCR0_DQSGOE_SHIFT 2 -#define DDR_PHY_DX5GCR0_DQSGOE_MASK 0x00000004U +#define DDR_PHY_DX5GCR0_DQSGOE_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_DQSGOE_SHIFT 2 +#define DDR_PHY_DX5GCR0_DQSGOE_MASK 0x00000004U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX5GCR0_RESERVED_1_0_DEFVAL #undef DDR_PHY_DX5GCR0_RESERVED_1_0_SHIFT #undef DDR_PHY_DX5GCR0_RESERVED_1_0_MASK -#define DDR_PHY_DX5GCR0_RESERVED_1_0_DEFVAL 0x40200204 -#define DDR_PHY_DX5GCR0_RESERVED_1_0_SHIFT 0 -#define DDR_PHY_DX5GCR0_RESERVED_1_0_MASK 0x00000003U +#define DDR_PHY_DX5GCR0_RESERVED_1_0_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_RESERVED_1_0_SHIFT 0 +#define DDR_PHY_DX5GCR0_RESERVED_1_0_MASK 0x00000003U -/*Enables the PDR mode for DQ[7:0]*/ +/* +* Enables the PDR mode for DQ[7:0] +*/ #undef DDR_PHY_DX5GCR1_DXPDRMODE_DEFVAL #undef DDR_PHY_DX5GCR1_DXPDRMODE_SHIFT #undef DDR_PHY_DX5GCR1_DXPDRMODE_MASK -#define DDR_PHY_DX5GCR1_DXPDRMODE_DEFVAL 0x00007FFF -#define DDR_PHY_DX5GCR1_DXPDRMODE_SHIFT 16 -#define DDR_PHY_DX5GCR1_DXPDRMODE_MASK 0xFFFF0000U +#define DDR_PHY_DX5GCR1_DXPDRMODE_DEFVAL 0x00007FFF +#define DDR_PHY_DX5GCR1_DXPDRMODE_SHIFT 16 +#define DDR_PHY_DX5GCR1_DXPDRMODE_MASK 0xFFFF0000U -/*Reserved. Returns zeroes on reads.*/ +/* +* Reserved. Returns zeroes on reads. +*/ #undef DDR_PHY_DX5GCR1_RESERVED_15_DEFVAL #undef DDR_PHY_DX5GCR1_RESERVED_15_SHIFT #undef DDR_PHY_DX5GCR1_RESERVED_15_MASK -#define DDR_PHY_DX5GCR1_RESERVED_15_DEFVAL 0x00007FFF -#define DDR_PHY_DX5GCR1_RESERVED_15_SHIFT 15 -#define DDR_PHY_DX5GCR1_RESERVED_15_MASK 0x00008000U +#define DDR_PHY_DX5GCR1_RESERVED_15_DEFVAL 0x00007FFF +#define DDR_PHY_DX5GCR1_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX5GCR1_RESERVED_15_MASK 0x00008000U -/*Select the delayed or non-delayed read data strobe #*/ +/* +* Select the delayed or non-delayed read data strobe # +*/ #undef DDR_PHY_DX5GCR1_QSNSEL_DEFVAL #undef DDR_PHY_DX5GCR1_QSNSEL_SHIFT #undef DDR_PHY_DX5GCR1_QSNSEL_MASK -#define DDR_PHY_DX5GCR1_QSNSEL_DEFVAL 0x00007FFF -#define DDR_PHY_DX5GCR1_QSNSEL_SHIFT 14 -#define DDR_PHY_DX5GCR1_QSNSEL_MASK 0x00004000U +#define DDR_PHY_DX5GCR1_QSNSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX5GCR1_QSNSEL_SHIFT 14 +#define DDR_PHY_DX5GCR1_QSNSEL_MASK 0x00004000U -/*Select the delayed or non-delayed read data strobe*/ +/* +* Select the delayed or non-delayed read data strobe +*/ #undef DDR_PHY_DX5GCR1_QSSEL_DEFVAL #undef DDR_PHY_DX5GCR1_QSSEL_SHIFT #undef DDR_PHY_DX5GCR1_QSSEL_MASK -#define DDR_PHY_DX5GCR1_QSSEL_DEFVAL 0x00007FFF -#define DDR_PHY_DX5GCR1_QSSEL_SHIFT 13 -#define DDR_PHY_DX5GCR1_QSSEL_MASK 0x00002000U +#define DDR_PHY_DX5GCR1_QSSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX5GCR1_QSSEL_SHIFT 13 +#define DDR_PHY_DX5GCR1_QSSEL_MASK 0x00002000U -/*Enables Read Data Strobe in a byte lane*/ +/* +* Enables Read Data Strobe in a byte lane +*/ #undef DDR_PHY_DX5GCR1_OEEN_DEFVAL #undef DDR_PHY_DX5GCR1_OEEN_SHIFT #undef DDR_PHY_DX5GCR1_OEEN_MASK -#define DDR_PHY_DX5GCR1_OEEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX5GCR1_OEEN_SHIFT 12 -#define DDR_PHY_DX5GCR1_OEEN_MASK 0x00001000U +#define DDR_PHY_DX5GCR1_OEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX5GCR1_OEEN_SHIFT 12 +#define DDR_PHY_DX5GCR1_OEEN_MASK 0x00001000U -/*Enables PDR in a byte lane*/ +/* +* Enables PDR in a byte lane +*/ #undef DDR_PHY_DX5GCR1_PDREN_DEFVAL #undef DDR_PHY_DX5GCR1_PDREN_SHIFT #undef DDR_PHY_DX5GCR1_PDREN_MASK -#define DDR_PHY_DX5GCR1_PDREN_DEFVAL 0x00007FFF -#define DDR_PHY_DX5GCR1_PDREN_SHIFT 11 -#define DDR_PHY_DX5GCR1_PDREN_MASK 0x00000800U +#define DDR_PHY_DX5GCR1_PDREN_DEFVAL 0x00007FFF +#define DDR_PHY_DX5GCR1_PDREN_SHIFT 11 +#define DDR_PHY_DX5GCR1_PDREN_MASK 0x00000800U -/*Enables ODT/TE in a byte lane*/ +/* +* Enables ODT/TE in a byte lane +*/ #undef DDR_PHY_DX5GCR1_TEEN_DEFVAL #undef DDR_PHY_DX5GCR1_TEEN_SHIFT #undef DDR_PHY_DX5GCR1_TEEN_MASK -#define DDR_PHY_DX5GCR1_TEEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX5GCR1_TEEN_SHIFT 10 -#define DDR_PHY_DX5GCR1_TEEN_MASK 0x00000400U +#define DDR_PHY_DX5GCR1_TEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX5GCR1_TEEN_SHIFT 10 +#define DDR_PHY_DX5GCR1_TEEN_MASK 0x00000400U -/*Enables Write Data strobe in a byte lane*/ +/* +* Enables Write Data strobe in a byte lane +*/ #undef DDR_PHY_DX5GCR1_DSEN_DEFVAL #undef DDR_PHY_DX5GCR1_DSEN_SHIFT #undef DDR_PHY_DX5GCR1_DSEN_MASK -#define DDR_PHY_DX5GCR1_DSEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX5GCR1_DSEN_SHIFT 9 -#define DDR_PHY_DX5GCR1_DSEN_MASK 0x00000200U +#define DDR_PHY_DX5GCR1_DSEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX5GCR1_DSEN_SHIFT 9 +#define DDR_PHY_DX5GCR1_DSEN_MASK 0x00000200U -/*Enables DM pin in a byte lane*/ +/* +* Enables DM pin in a byte lane +*/ #undef DDR_PHY_DX5GCR1_DMEN_DEFVAL #undef DDR_PHY_DX5GCR1_DMEN_SHIFT #undef DDR_PHY_DX5GCR1_DMEN_MASK -#define DDR_PHY_DX5GCR1_DMEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX5GCR1_DMEN_SHIFT 8 -#define DDR_PHY_DX5GCR1_DMEN_MASK 0x00000100U +#define DDR_PHY_DX5GCR1_DMEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX5GCR1_DMEN_SHIFT 8 +#define DDR_PHY_DX5GCR1_DMEN_MASK 0x00000100U -/*Enables DQ corresponding to each bit in a byte*/ +/* +* Enables DQ corresponding to each bit in a byte +*/ #undef DDR_PHY_DX5GCR1_DQEN_DEFVAL #undef DDR_PHY_DX5GCR1_DQEN_SHIFT #undef DDR_PHY_DX5GCR1_DQEN_MASK -#define DDR_PHY_DX5GCR1_DQEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX5GCR1_DQEN_SHIFT 0 -#define DDR_PHY_DX5GCR1_DQEN_MASK 0x000000FFU +#define DDR_PHY_DX5GCR1_DQEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX5GCR1_DQEN_SHIFT 0 +#define DDR_PHY_DX5GCR1_DQEN_MASK 0x000000FFU -/*Byte lane VREF IOM (Used only by D4MU IOs)*/ +/* +* Byte lane VREF IOM (Used only by D4MU IOs) +*/ #undef DDR_PHY_DX5GCR4_RESERVED_31_29_DEFVAL #undef DDR_PHY_DX5GCR4_RESERVED_31_29_SHIFT #undef DDR_PHY_DX5GCR4_RESERVED_31_29_MASK -#define DDR_PHY_DX5GCR4_RESERVED_31_29_DEFVAL 0x0E00003C -#define DDR_PHY_DX5GCR4_RESERVED_31_29_SHIFT 29 -#define DDR_PHY_DX5GCR4_RESERVED_31_29_MASK 0xE0000000U +#define DDR_PHY_DX5GCR4_RESERVED_31_29_DEFVAL 0x0E00003C +#define DDR_PHY_DX5GCR4_RESERVED_31_29_SHIFT 29 +#define DDR_PHY_DX5GCR4_RESERVED_31_29_MASK 0xE0000000U -/*Byte Lane VREF Pad Enable*/ +/* +* Byte Lane VREF Pad Enable +*/ #undef DDR_PHY_DX5GCR4_DXREFPEN_DEFVAL #undef DDR_PHY_DX5GCR4_DXREFPEN_SHIFT #undef DDR_PHY_DX5GCR4_DXREFPEN_MASK -#define DDR_PHY_DX5GCR4_DXREFPEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX5GCR4_DXREFPEN_SHIFT 28 -#define DDR_PHY_DX5GCR4_DXREFPEN_MASK 0x10000000U +#define DDR_PHY_DX5GCR4_DXREFPEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX5GCR4_DXREFPEN_SHIFT 28 +#define DDR_PHY_DX5GCR4_DXREFPEN_MASK 0x10000000U -/*Byte Lane Internal VREF Enable*/ +/* +* Byte Lane Internal VREF Enable +*/ #undef DDR_PHY_DX5GCR4_DXREFEEN_DEFVAL #undef DDR_PHY_DX5GCR4_DXREFEEN_SHIFT #undef DDR_PHY_DX5GCR4_DXREFEEN_MASK -#define DDR_PHY_DX5GCR4_DXREFEEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX5GCR4_DXREFEEN_SHIFT 26 -#define DDR_PHY_DX5GCR4_DXREFEEN_MASK 0x0C000000U +#define DDR_PHY_DX5GCR4_DXREFEEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX5GCR4_DXREFEEN_SHIFT 26 +#define DDR_PHY_DX5GCR4_DXREFEEN_MASK 0x0C000000U -/*Byte Lane Single-End VREF Enable*/ +/* +* Byte Lane Single-End VREF Enable +*/ #undef DDR_PHY_DX5GCR4_DXREFSEN_DEFVAL #undef DDR_PHY_DX5GCR4_DXREFSEN_SHIFT #undef DDR_PHY_DX5GCR4_DXREFSEN_MASK -#define DDR_PHY_DX5GCR4_DXREFSEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX5GCR4_DXREFSEN_SHIFT 25 -#define DDR_PHY_DX5GCR4_DXREFSEN_MASK 0x02000000U +#define DDR_PHY_DX5GCR4_DXREFSEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX5GCR4_DXREFSEN_SHIFT 25 +#define DDR_PHY_DX5GCR4_DXREFSEN_MASK 0x02000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX5GCR4_RESERVED_24_DEFVAL #undef DDR_PHY_DX5GCR4_RESERVED_24_SHIFT #undef DDR_PHY_DX5GCR4_RESERVED_24_MASK -#define DDR_PHY_DX5GCR4_RESERVED_24_DEFVAL 0x0E00003C -#define DDR_PHY_DX5GCR4_RESERVED_24_SHIFT 24 -#define DDR_PHY_DX5GCR4_RESERVED_24_MASK 0x01000000U +#define DDR_PHY_DX5GCR4_RESERVED_24_DEFVAL 0x0E00003C +#define DDR_PHY_DX5GCR4_RESERVED_24_SHIFT 24 +#define DDR_PHY_DX5GCR4_RESERVED_24_MASK 0x01000000U -/*External VREF generator REFSEL range select*/ +/* +* External VREF generator REFSEL range select +*/ #undef DDR_PHY_DX5GCR4_DXREFESELRANGE_DEFVAL #undef DDR_PHY_DX5GCR4_DXREFESELRANGE_SHIFT #undef DDR_PHY_DX5GCR4_DXREFESELRANGE_MASK -#define DDR_PHY_DX5GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C -#define DDR_PHY_DX5GCR4_DXREFESELRANGE_SHIFT 23 -#define DDR_PHY_DX5GCR4_DXREFESELRANGE_MASK 0x00800000U +#define DDR_PHY_DX5GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX5GCR4_DXREFESELRANGE_SHIFT 23 +#define DDR_PHY_DX5GCR4_DXREFESELRANGE_MASK 0x00800000U -/*Byte Lane External VREF Select*/ +/* +* Byte Lane External VREF Select +*/ #undef DDR_PHY_DX5GCR4_DXREFESEL_DEFVAL #undef DDR_PHY_DX5GCR4_DXREFESEL_SHIFT #undef DDR_PHY_DX5GCR4_DXREFESEL_MASK -#define DDR_PHY_DX5GCR4_DXREFESEL_DEFVAL 0x0E00003C -#define DDR_PHY_DX5GCR4_DXREFESEL_SHIFT 16 -#define DDR_PHY_DX5GCR4_DXREFESEL_MASK 0x007F0000U +#define DDR_PHY_DX5GCR4_DXREFESEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX5GCR4_DXREFESEL_SHIFT 16 +#define DDR_PHY_DX5GCR4_DXREFESEL_MASK 0x007F0000U -/*Single ended VREF generator REFSEL range select*/ +/* +* Single ended VREF generator REFSEL range select +*/ #undef DDR_PHY_DX5GCR4_DXREFSSELRANGE_DEFVAL #undef DDR_PHY_DX5GCR4_DXREFSSELRANGE_SHIFT #undef DDR_PHY_DX5GCR4_DXREFSSELRANGE_MASK -#define DDR_PHY_DX5GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C -#define DDR_PHY_DX5GCR4_DXREFSSELRANGE_SHIFT 15 -#define DDR_PHY_DX5GCR4_DXREFSSELRANGE_MASK 0x00008000U +#define DDR_PHY_DX5GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX5GCR4_DXREFSSELRANGE_SHIFT 15 +#define DDR_PHY_DX5GCR4_DXREFSSELRANGE_MASK 0x00008000U -/*Byte Lane Single-End VREF Select*/ +/* +* Byte Lane Single-End VREF Select +*/ #undef DDR_PHY_DX5GCR4_DXREFSSEL_DEFVAL #undef DDR_PHY_DX5GCR4_DXREFSSEL_SHIFT #undef DDR_PHY_DX5GCR4_DXREFSSEL_MASK -#define DDR_PHY_DX5GCR4_DXREFSSEL_DEFVAL 0x0E00003C -#define DDR_PHY_DX5GCR4_DXREFSSEL_SHIFT 8 -#define DDR_PHY_DX5GCR4_DXREFSSEL_MASK 0x00007F00U +#define DDR_PHY_DX5GCR4_DXREFSSEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX5GCR4_DXREFSSEL_SHIFT 8 +#define DDR_PHY_DX5GCR4_DXREFSSEL_MASK 0x00007F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX5GCR4_RESERVED_7_6_DEFVAL #undef DDR_PHY_DX5GCR4_RESERVED_7_6_SHIFT #undef DDR_PHY_DX5GCR4_RESERVED_7_6_MASK -#define DDR_PHY_DX5GCR4_RESERVED_7_6_DEFVAL 0x0E00003C -#define DDR_PHY_DX5GCR4_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_DX5GCR4_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_DX5GCR4_RESERVED_7_6_DEFVAL 0x0E00003C +#define DDR_PHY_DX5GCR4_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX5GCR4_RESERVED_7_6_MASK 0x000000C0U -/*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/ +/* +* VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. +*/ #undef DDR_PHY_DX5GCR4_DXREFIEN_DEFVAL #undef DDR_PHY_DX5GCR4_DXREFIEN_SHIFT #undef DDR_PHY_DX5GCR4_DXREFIEN_MASK -#define DDR_PHY_DX5GCR4_DXREFIEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX5GCR4_DXREFIEN_SHIFT 2 -#define DDR_PHY_DX5GCR4_DXREFIEN_MASK 0x0000003CU +#define DDR_PHY_DX5GCR4_DXREFIEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX5GCR4_DXREFIEN_SHIFT 2 +#define DDR_PHY_DX5GCR4_DXREFIEN_MASK 0x0000003CU -/*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/ +/* +* VRMON control for DQ IO (Single Ended) buffers of a byte lane. +*/ #undef DDR_PHY_DX5GCR4_DXREFIMON_DEFVAL #undef DDR_PHY_DX5GCR4_DXREFIMON_SHIFT #undef DDR_PHY_DX5GCR4_DXREFIMON_MASK -#define DDR_PHY_DX5GCR4_DXREFIMON_DEFVAL 0x0E00003C -#define DDR_PHY_DX5GCR4_DXREFIMON_SHIFT 0 -#define DDR_PHY_DX5GCR4_DXREFIMON_MASK 0x00000003U +#define DDR_PHY_DX5GCR4_DXREFIMON_DEFVAL 0x0E00003C +#define DDR_PHY_DX5GCR4_DXREFIMON_SHIFT 0 +#define DDR_PHY_DX5GCR4_DXREFIMON_MASK 0x00000003U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX5GCR5_RESERVED_31_DEFVAL #undef DDR_PHY_DX5GCR5_RESERVED_31_SHIFT #undef DDR_PHY_DX5GCR5_RESERVED_31_MASK -#define DDR_PHY_DX5GCR5_RESERVED_31_DEFVAL 0x09090909 -#define DDR_PHY_DX5GCR5_RESERVED_31_SHIFT 31 -#define DDR_PHY_DX5GCR5_RESERVED_31_MASK 0x80000000U +#define DDR_PHY_DX5GCR5_RESERVED_31_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR5_RESERVED_31_SHIFT 31 +#define DDR_PHY_DX5GCR5_RESERVED_31_MASK 0x80000000U -/*Byte Lane internal VREF Select for Rank 3*/ +/* +* Byte Lane internal VREF Select for Rank 3 +*/ #undef DDR_PHY_DX5GCR5_DXREFISELR3_DEFVAL #undef DDR_PHY_DX5GCR5_DXREFISELR3_SHIFT #undef DDR_PHY_DX5GCR5_DXREFISELR3_MASK -#define DDR_PHY_DX5GCR5_DXREFISELR3_DEFVAL 0x09090909 -#define DDR_PHY_DX5GCR5_DXREFISELR3_SHIFT 24 -#define DDR_PHY_DX5GCR5_DXREFISELR3_MASK 0x7F000000U +#define DDR_PHY_DX5GCR5_DXREFISELR3_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR5_DXREFISELR3_SHIFT 24 +#define DDR_PHY_DX5GCR5_DXREFISELR3_MASK 0x7F000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX5GCR5_RESERVED_23_DEFVAL #undef DDR_PHY_DX5GCR5_RESERVED_23_SHIFT #undef DDR_PHY_DX5GCR5_RESERVED_23_MASK -#define DDR_PHY_DX5GCR5_RESERVED_23_DEFVAL 0x09090909 -#define DDR_PHY_DX5GCR5_RESERVED_23_SHIFT 23 -#define DDR_PHY_DX5GCR5_RESERVED_23_MASK 0x00800000U +#define DDR_PHY_DX5GCR5_RESERVED_23_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR5_RESERVED_23_SHIFT 23 +#define DDR_PHY_DX5GCR5_RESERVED_23_MASK 0x00800000U -/*Byte Lane internal VREF Select for Rank 2*/ +/* +* Byte Lane internal VREF Select for Rank 2 +*/ #undef DDR_PHY_DX5GCR5_DXREFISELR2_DEFVAL #undef DDR_PHY_DX5GCR5_DXREFISELR2_SHIFT #undef DDR_PHY_DX5GCR5_DXREFISELR2_MASK -#define DDR_PHY_DX5GCR5_DXREFISELR2_DEFVAL 0x09090909 -#define DDR_PHY_DX5GCR5_DXREFISELR2_SHIFT 16 -#define DDR_PHY_DX5GCR5_DXREFISELR2_MASK 0x007F0000U +#define DDR_PHY_DX5GCR5_DXREFISELR2_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR5_DXREFISELR2_SHIFT 16 +#define DDR_PHY_DX5GCR5_DXREFISELR2_MASK 0x007F0000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX5GCR5_RESERVED_15_DEFVAL #undef DDR_PHY_DX5GCR5_RESERVED_15_SHIFT #undef DDR_PHY_DX5GCR5_RESERVED_15_MASK -#define DDR_PHY_DX5GCR5_RESERVED_15_DEFVAL 0x09090909 -#define DDR_PHY_DX5GCR5_RESERVED_15_SHIFT 15 -#define DDR_PHY_DX5GCR5_RESERVED_15_MASK 0x00008000U +#define DDR_PHY_DX5GCR5_RESERVED_15_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR5_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX5GCR5_RESERVED_15_MASK 0x00008000U -/*Byte Lane internal VREF Select for Rank 1*/ +/* +* Byte Lane internal VREF Select for Rank 1 +*/ #undef DDR_PHY_DX5GCR5_DXREFISELR1_DEFVAL #undef DDR_PHY_DX5GCR5_DXREFISELR1_SHIFT #undef DDR_PHY_DX5GCR5_DXREFISELR1_MASK -#define DDR_PHY_DX5GCR5_DXREFISELR1_DEFVAL 0x09090909 -#define DDR_PHY_DX5GCR5_DXREFISELR1_SHIFT 8 -#define DDR_PHY_DX5GCR5_DXREFISELR1_MASK 0x00007F00U +#define DDR_PHY_DX5GCR5_DXREFISELR1_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR5_DXREFISELR1_SHIFT 8 +#define DDR_PHY_DX5GCR5_DXREFISELR1_MASK 0x00007F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX5GCR5_RESERVED_7_DEFVAL #undef DDR_PHY_DX5GCR5_RESERVED_7_SHIFT #undef DDR_PHY_DX5GCR5_RESERVED_7_MASK -#define DDR_PHY_DX5GCR5_RESERVED_7_DEFVAL 0x09090909 -#define DDR_PHY_DX5GCR5_RESERVED_7_SHIFT 7 -#define DDR_PHY_DX5GCR5_RESERVED_7_MASK 0x00000080U +#define DDR_PHY_DX5GCR5_RESERVED_7_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR5_RESERVED_7_SHIFT 7 +#define DDR_PHY_DX5GCR5_RESERVED_7_MASK 0x00000080U -/*Byte Lane internal VREF Select for Rank 0*/ +/* +* Byte Lane internal VREF Select for Rank 0 +*/ #undef DDR_PHY_DX5GCR5_DXREFISELR0_DEFVAL #undef DDR_PHY_DX5GCR5_DXREFISELR0_SHIFT #undef DDR_PHY_DX5GCR5_DXREFISELR0_MASK -#define DDR_PHY_DX5GCR5_DXREFISELR0_DEFVAL 0x09090909 -#define DDR_PHY_DX5GCR5_DXREFISELR0_SHIFT 0 -#define DDR_PHY_DX5GCR5_DXREFISELR0_MASK 0x0000007FU +#define DDR_PHY_DX5GCR5_DXREFISELR0_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR5_DXREFISELR0_SHIFT 0 +#define DDR_PHY_DX5GCR5_DXREFISELR0_MASK 0x0000007FU -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX5GCR6_RESERVED_31_30_DEFVAL #undef DDR_PHY_DX5GCR6_RESERVED_31_30_SHIFT #undef DDR_PHY_DX5GCR6_RESERVED_31_30_MASK -#define DDR_PHY_DX5GCR6_RESERVED_31_30_DEFVAL 0x09090909 -#define DDR_PHY_DX5GCR6_RESERVED_31_30_SHIFT 30 -#define DDR_PHY_DX5GCR6_RESERVED_31_30_MASK 0xC0000000U +#define DDR_PHY_DX5GCR6_RESERVED_31_30_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR6_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX5GCR6_RESERVED_31_30_MASK 0xC0000000U -/*DRAM DQ VREF Select for Rank3*/ +/* +* DRAM DQ VREF Select for Rank3 +*/ #undef DDR_PHY_DX5GCR6_DXDQVREFR3_DEFVAL #undef DDR_PHY_DX5GCR6_DXDQVREFR3_SHIFT #undef DDR_PHY_DX5GCR6_DXDQVREFR3_MASK -#define DDR_PHY_DX5GCR6_DXDQVREFR3_DEFVAL 0x09090909 -#define DDR_PHY_DX5GCR6_DXDQVREFR3_SHIFT 24 -#define DDR_PHY_DX5GCR6_DXDQVREFR3_MASK 0x3F000000U +#define DDR_PHY_DX5GCR6_DXDQVREFR3_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR6_DXDQVREFR3_SHIFT 24 +#define DDR_PHY_DX5GCR6_DXDQVREFR3_MASK 0x3F000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX5GCR6_RESERVED_23_22_DEFVAL #undef DDR_PHY_DX5GCR6_RESERVED_23_22_SHIFT #undef DDR_PHY_DX5GCR6_RESERVED_23_22_MASK -#define DDR_PHY_DX5GCR6_RESERVED_23_22_DEFVAL 0x09090909 -#define DDR_PHY_DX5GCR6_RESERVED_23_22_SHIFT 22 -#define DDR_PHY_DX5GCR6_RESERVED_23_22_MASK 0x00C00000U +#define DDR_PHY_DX5GCR6_RESERVED_23_22_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR6_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX5GCR6_RESERVED_23_22_MASK 0x00C00000U -/*DRAM DQ VREF Select for Rank2*/ +/* +* DRAM DQ VREF Select for Rank2 +*/ #undef DDR_PHY_DX5GCR6_DXDQVREFR2_DEFVAL #undef DDR_PHY_DX5GCR6_DXDQVREFR2_SHIFT #undef DDR_PHY_DX5GCR6_DXDQVREFR2_MASK -#define DDR_PHY_DX5GCR6_DXDQVREFR2_DEFVAL 0x09090909 -#define DDR_PHY_DX5GCR6_DXDQVREFR2_SHIFT 16 -#define DDR_PHY_DX5GCR6_DXDQVREFR2_MASK 0x003F0000U +#define DDR_PHY_DX5GCR6_DXDQVREFR2_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR6_DXDQVREFR2_SHIFT 16 +#define DDR_PHY_DX5GCR6_DXDQVREFR2_MASK 0x003F0000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX5GCR6_RESERVED_15_14_DEFVAL #undef DDR_PHY_DX5GCR6_RESERVED_15_14_SHIFT #undef DDR_PHY_DX5GCR6_RESERVED_15_14_MASK -#define DDR_PHY_DX5GCR6_RESERVED_15_14_DEFVAL 0x09090909 -#define DDR_PHY_DX5GCR6_RESERVED_15_14_SHIFT 14 -#define DDR_PHY_DX5GCR6_RESERVED_15_14_MASK 0x0000C000U +#define DDR_PHY_DX5GCR6_RESERVED_15_14_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR6_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_DX5GCR6_RESERVED_15_14_MASK 0x0000C000U -/*DRAM DQ VREF Select for Rank1*/ +/* +* DRAM DQ VREF Select for Rank1 +*/ #undef DDR_PHY_DX5GCR6_DXDQVREFR1_DEFVAL #undef DDR_PHY_DX5GCR6_DXDQVREFR1_SHIFT #undef DDR_PHY_DX5GCR6_DXDQVREFR1_MASK -#define DDR_PHY_DX5GCR6_DXDQVREFR1_DEFVAL 0x09090909 -#define DDR_PHY_DX5GCR6_DXDQVREFR1_SHIFT 8 -#define DDR_PHY_DX5GCR6_DXDQVREFR1_MASK 0x00003F00U +#define DDR_PHY_DX5GCR6_DXDQVREFR1_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR6_DXDQVREFR1_SHIFT 8 +#define DDR_PHY_DX5GCR6_DXDQVREFR1_MASK 0x00003F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX5GCR6_RESERVED_7_6_DEFVAL #undef DDR_PHY_DX5GCR6_RESERVED_7_6_SHIFT #undef DDR_PHY_DX5GCR6_RESERVED_7_6_MASK -#define DDR_PHY_DX5GCR6_RESERVED_7_6_DEFVAL 0x09090909 -#define DDR_PHY_DX5GCR6_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_DX5GCR6_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_DX5GCR6_RESERVED_7_6_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR6_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX5GCR6_RESERVED_7_6_MASK 0x000000C0U -/*DRAM DQ VREF Select for Rank0*/ +/* +* DRAM DQ VREF Select for Rank0 +*/ #undef DDR_PHY_DX5GCR6_DXDQVREFR0_DEFVAL #undef DDR_PHY_DX5GCR6_DXDQVREFR0_SHIFT #undef DDR_PHY_DX5GCR6_DXDQVREFR0_MASK -#define DDR_PHY_DX5GCR6_DXDQVREFR0_DEFVAL 0x09090909 -#define DDR_PHY_DX5GCR6_DXDQVREFR0_SHIFT 0 -#define DDR_PHY_DX5GCR6_DXDQVREFR0_MASK 0x0000003FU +#define DDR_PHY_DX5GCR6_DXDQVREFR0_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR6_DXDQVREFR0_SHIFT 0 +#define DDR_PHY_DX5GCR6_DXDQVREFR0_MASK 0x0000003FU -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX5LCDLR2_RESERVED_31_25_DEFVAL -#undef DDR_PHY_DX5LCDLR2_RESERVED_31_25_SHIFT -#undef DDR_PHY_DX5LCDLR2_RESERVED_31_25_MASK -#define DDR_PHY_DX5LCDLR2_RESERVED_31_25_DEFVAL 0x00000000 -#define DDR_PHY_DX5LCDLR2_RESERVED_31_25_SHIFT 25 -#define DDR_PHY_DX5LCDLR2_RESERVED_31_25_MASK 0xFE000000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX5LCDLR2_RESERVED_24_16_DEFVAL -#undef DDR_PHY_DX5LCDLR2_RESERVED_24_16_SHIFT -#undef DDR_PHY_DX5LCDLR2_RESERVED_24_16_MASK -#define DDR_PHY_DX5LCDLR2_RESERVED_24_16_DEFVAL 0x00000000 -#define DDR_PHY_DX5LCDLR2_RESERVED_24_16_SHIFT 16 -#define DDR_PHY_DX5LCDLR2_RESERVED_24_16_MASK 0x01FF0000U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX5LCDLR2_RESERVED_15_9_DEFVAL -#undef DDR_PHY_DX5LCDLR2_RESERVED_15_9_SHIFT -#undef DDR_PHY_DX5LCDLR2_RESERVED_15_9_MASK -#define DDR_PHY_DX5LCDLR2_RESERVED_15_9_DEFVAL 0x00000000 -#define DDR_PHY_DX5LCDLR2_RESERVED_15_9_SHIFT 9 -#define DDR_PHY_DX5LCDLR2_RESERVED_15_9_MASK 0x0000FE00U - -/*Read DQS Gating Delay*/ -#undef DDR_PHY_DX5LCDLR2_DQSGD_DEFVAL -#undef DDR_PHY_DX5LCDLR2_DQSGD_SHIFT -#undef DDR_PHY_DX5LCDLR2_DQSGD_MASK -#define DDR_PHY_DX5LCDLR2_DQSGD_DEFVAL 0x00000000 -#define DDR_PHY_DX5LCDLR2_DQSGD_SHIFT 0 -#define DDR_PHY_DX5LCDLR2_DQSGD_MASK 0x000001FFU - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX5GTR0_RESERVED_31_24_DEFVAL -#undef DDR_PHY_DX5GTR0_RESERVED_31_24_SHIFT -#undef DDR_PHY_DX5GTR0_RESERVED_31_24_MASK -#define DDR_PHY_DX5GTR0_RESERVED_31_24_DEFVAL 0x00020000 -#define DDR_PHY_DX5GTR0_RESERVED_31_24_SHIFT 27 -#define DDR_PHY_DX5GTR0_RESERVED_31_24_MASK 0xF8000000U - -/*DQ Write Path Latency Pipeline*/ -#undef DDR_PHY_DX5GTR0_WDQSL_DEFVAL -#undef DDR_PHY_DX5GTR0_WDQSL_SHIFT -#undef DDR_PHY_DX5GTR0_WDQSL_MASK -#define DDR_PHY_DX5GTR0_WDQSL_DEFVAL 0x00020000 -#define DDR_PHY_DX5GTR0_WDQSL_SHIFT 24 -#define DDR_PHY_DX5GTR0_WDQSL_MASK 0x07000000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX5GTR0_RESERVED_23_20_DEFVAL -#undef DDR_PHY_DX5GTR0_RESERVED_23_20_SHIFT -#undef DDR_PHY_DX5GTR0_RESERVED_23_20_MASK -#define DDR_PHY_DX5GTR0_RESERVED_23_20_DEFVAL 0x00020000 -#define DDR_PHY_DX5GTR0_RESERVED_23_20_SHIFT 20 -#define DDR_PHY_DX5GTR0_RESERVED_23_20_MASK 0x00F00000U - -/*Write Leveling System Latency*/ -#undef DDR_PHY_DX5GTR0_WLSL_DEFVAL -#undef DDR_PHY_DX5GTR0_WLSL_SHIFT -#undef DDR_PHY_DX5GTR0_WLSL_MASK -#define DDR_PHY_DX5GTR0_WLSL_DEFVAL 0x00020000 -#define DDR_PHY_DX5GTR0_WLSL_SHIFT 16 -#define DDR_PHY_DX5GTR0_WLSL_MASK 0x000F0000U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX5GTR0_RESERVED_15_13_DEFVAL -#undef DDR_PHY_DX5GTR0_RESERVED_15_13_SHIFT -#undef DDR_PHY_DX5GTR0_RESERVED_15_13_MASK -#define DDR_PHY_DX5GTR0_RESERVED_15_13_DEFVAL 0x00020000 -#define DDR_PHY_DX5GTR0_RESERVED_15_13_SHIFT 13 -#define DDR_PHY_DX5GTR0_RESERVED_15_13_MASK 0x0000E000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX5GTR0_RESERVED_12_8_DEFVAL -#undef DDR_PHY_DX5GTR0_RESERVED_12_8_SHIFT -#undef DDR_PHY_DX5GTR0_RESERVED_12_8_MASK -#define DDR_PHY_DX5GTR0_RESERVED_12_8_DEFVAL 0x00020000 -#define DDR_PHY_DX5GTR0_RESERVED_12_8_SHIFT 8 -#define DDR_PHY_DX5GTR0_RESERVED_12_8_MASK 0x00001F00U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX5GTR0_RESERVED_7_5_DEFVAL -#undef DDR_PHY_DX5GTR0_RESERVED_7_5_SHIFT -#undef DDR_PHY_DX5GTR0_RESERVED_7_5_MASK -#define DDR_PHY_DX5GTR0_RESERVED_7_5_DEFVAL 0x00020000 -#define DDR_PHY_DX5GTR0_RESERVED_7_5_SHIFT 5 -#define DDR_PHY_DX5GTR0_RESERVED_7_5_MASK 0x000000E0U - -/*DQS Gating System Latency*/ -#undef DDR_PHY_DX5GTR0_DGSL_DEFVAL -#undef DDR_PHY_DX5GTR0_DGSL_SHIFT -#undef DDR_PHY_DX5GTR0_DGSL_MASK -#define DDR_PHY_DX5GTR0_DGSL_DEFVAL 0x00020000 -#define DDR_PHY_DX5GTR0_DGSL_SHIFT 0 -#define DDR_PHY_DX5GTR0_DGSL_MASK 0x0000001FU - -/*Calibration Bypass*/ +/* +* Calibration Bypass +*/ #undef DDR_PHY_DX6GCR0_CALBYP_DEFVAL #undef DDR_PHY_DX6GCR0_CALBYP_SHIFT #undef DDR_PHY_DX6GCR0_CALBYP_MASK -#define DDR_PHY_DX6GCR0_CALBYP_DEFVAL 0x40200204 -#define DDR_PHY_DX6GCR0_CALBYP_SHIFT 31 -#define DDR_PHY_DX6GCR0_CALBYP_MASK 0x80000000U +#define DDR_PHY_DX6GCR0_CALBYP_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_CALBYP_SHIFT 31 +#define DDR_PHY_DX6GCR0_CALBYP_MASK 0x80000000U -/*Master Delay Line Enable*/ +/* +* Master Delay Line Enable +*/ #undef DDR_PHY_DX6GCR0_MDLEN_DEFVAL #undef DDR_PHY_DX6GCR0_MDLEN_SHIFT #undef DDR_PHY_DX6GCR0_MDLEN_MASK -#define DDR_PHY_DX6GCR0_MDLEN_DEFVAL 0x40200204 -#define DDR_PHY_DX6GCR0_MDLEN_SHIFT 30 -#define DDR_PHY_DX6GCR0_MDLEN_MASK 0x40000000U +#define DDR_PHY_DX6GCR0_MDLEN_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_MDLEN_SHIFT 30 +#define DDR_PHY_DX6GCR0_MDLEN_MASK 0x40000000U -/*Configurable ODT(TE) Phase Shift*/ +/* +* Configurable ODT(TE) Phase Shift +*/ #undef DDR_PHY_DX6GCR0_CODTSHFT_DEFVAL #undef DDR_PHY_DX6GCR0_CODTSHFT_SHIFT #undef DDR_PHY_DX6GCR0_CODTSHFT_MASK -#define DDR_PHY_DX6GCR0_CODTSHFT_DEFVAL 0x40200204 -#define DDR_PHY_DX6GCR0_CODTSHFT_SHIFT 28 -#define DDR_PHY_DX6GCR0_CODTSHFT_MASK 0x30000000U +#define DDR_PHY_DX6GCR0_CODTSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_CODTSHFT_SHIFT 28 +#define DDR_PHY_DX6GCR0_CODTSHFT_MASK 0x30000000U -/*DQS Duty Cycle Correction*/ +/* +* DQS Duty Cycle Correction +*/ #undef DDR_PHY_DX6GCR0_DQSDCC_DEFVAL #undef DDR_PHY_DX6GCR0_DQSDCC_SHIFT #undef DDR_PHY_DX6GCR0_DQSDCC_MASK -#define DDR_PHY_DX6GCR0_DQSDCC_DEFVAL 0x40200204 -#define DDR_PHY_DX6GCR0_DQSDCC_SHIFT 24 -#define DDR_PHY_DX6GCR0_DQSDCC_MASK 0x0F000000U +#define DDR_PHY_DX6GCR0_DQSDCC_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_DQSDCC_SHIFT 24 +#define DDR_PHY_DX6GCR0_DQSDCC_MASK 0x0F000000U -/*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/ +/* +* Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY +*/ #undef DDR_PHY_DX6GCR0_RDDLY_DEFVAL #undef DDR_PHY_DX6GCR0_RDDLY_SHIFT #undef DDR_PHY_DX6GCR0_RDDLY_MASK -#define DDR_PHY_DX6GCR0_RDDLY_DEFVAL 0x40200204 -#define DDR_PHY_DX6GCR0_RDDLY_SHIFT 20 -#define DDR_PHY_DX6GCR0_RDDLY_MASK 0x00F00000U +#define DDR_PHY_DX6GCR0_RDDLY_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_RDDLY_SHIFT 20 +#define DDR_PHY_DX6GCR0_RDDLY_MASK 0x00F00000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX6GCR0_RESERVED_19_14_DEFVAL #undef DDR_PHY_DX6GCR0_RESERVED_19_14_SHIFT #undef DDR_PHY_DX6GCR0_RESERVED_19_14_MASK -#define DDR_PHY_DX6GCR0_RESERVED_19_14_DEFVAL 0x40200204 -#define DDR_PHY_DX6GCR0_RESERVED_19_14_SHIFT 14 -#define DDR_PHY_DX6GCR0_RESERVED_19_14_MASK 0x000FC000U +#define DDR_PHY_DX6GCR0_RESERVED_19_14_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_RESERVED_19_14_SHIFT 14 +#define DDR_PHY_DX6GCR0_RESERVED_19_14_MASK 0x000FC000U -/*DQSNSE Power Down Receiver*/ +/* +* DQSNSE Power Down Receiver +*/ #undef DDR_PHY_DX6GCR0_DQSNSEPDR_DEFVAL #undef DDR_PHY_DX6GCR0_DQSNSEPDR_SHIFT #undef DDR_PHY_DX6GCR0_DQSNSEPDR_MASK -#define DDR_PHY_DX6GCR0_DQSNSEPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX6GCR0_DQSNSEPDR_SHIFT 13 -#define DDR_PHY_DX6GCR0_DQSNSEPDR_MASK 0x00002000U +#define DDR_PHY_DX6GCR0_DQSNSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_DQSNSEPDR_SHIFT 13 +#define DDR_PHY_DX6GCR0_DQSNSEPDR_MASK 0x00002000U -/*DQSSE Power Down Receiver*/ +/* +* DQSSE Power Down Receiver +*/ #undef DDR_PHY_DX6GCR0_DQSSEPDR_DEFVAL #undef DDR_PHY_DX6GCR0_DQSSEPDR_SHIFT #undef DDR_PHY_DX6GCR0_DQSSEPDR_MASK -#define DDR_PHY_DX6GCR0_DQSSEPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX6GCR0_DQSSEPDR_SHIFT 12 -#define DDR_PHY_DX6GCR0_DQSSEPDR_MASK 0x00001000U +#define DDR_PHY_DX6GCR0_DQSSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_DQSSEPDR_SHIFT 12 +#define DDR_PHY_DX6GCR0_DQSSEPDR_MASK 0x00001000U -/*RTT On Additive Latency*/ +/* +* RTT On Additive Latency +*/ #undef DDR_PHY_DX6GCR0_RTTOAL_DEFVAL #undef DDR_PHY_DX6GCR0_RTTOAL_SHIFT #undef DDR_PHY_DX6GCR0_RTTOAL_MASK -#define DDR_PHY_DX6GCR0_RTTOAL_DEFVAL 0x40200204 -#define DDR_PHY_DX6GCR0_RTTOAL_SHIFT 11 -#define DDR_PHY_DX6GCR0_RTTOAL_MASK 0x00000800U +#define DDR_PHY_DX6GCR0_RTTOAL_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_RTTOAL_SHIFT 11 +#define DDR_PHY_DX6GCR0_RTTOAL_MASK 0x00000800U -/*RTT Output Hold*/ +/* +* RTT Output Hold +*/ #undef DDR_PHY_DX6GCR0_RTTOH_DEFVAL #undef DDR_PHY_DX6GCR0_RTTOH_SHIFT #undef DDR_PHY_DX6GCR0_RTTOH_MASK -#define DDR_PHY_DX6GCR0_RTTOH_DEFVAL 0x40200204 -#define DDR_PHY_DX6GCR0_RTTOH_SHIFT 9 -#define DDR_PHY_DX6GCR0_RTTOH_MASK 0x00000600U +#define DDR_PHY_DX6GCR0_RTTOH_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_RTTOH_SHIFT 9 +#define DDR_PHY_DX6GCR0_RTTOH_MASK 0x00000600U -/*Configurable PDR Phase Shift*/ +/* +* Configurable PDR Phase Shift +*/ #undef DDR_PHY_DX6GCR0_CPDRSHFT_DEFVAL #undef DDR_PHY_DX6GCR0_CPDRSHFT_SHIFT #undef DDR_PHY_DX6GCR0_CPDRSHFT_MASK -#define DDR_PHY_DX6GCR0_CPDRSHFT_DEFVAL 0x40200204 -#define DDR_PHY_DX6GCR0_CPDRSHFT_SHIFT 7 -#define DDR_PHY_DX6GCR0_CPDRSHFT_MASK 0x00000180U +#define DDR_PHY_DX6GCR0_CPDRSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_CPDRSHFT_SHIFT 7 +#define DDR_PHY_DX6GCR0_CPDRSHFT_MASK 0x00000180U -/*DQSR Power Down*/ +/* +* DQSR Power Down +*/ #undef DDR_PHY_DX6GCR0_DQSRPD_DEFVAL #undef DDR_PHY_DX6GCR0_DQSRPD_SHIFT #undef DDR_PHY_DX6GCR0_DQSRPD_MASK -#define DDR_PHY_DX6GCR0_DQSRPD_DEFVAL 0x40200204 -#define DDR_PHY_DX6GCR0_DQSRPD_SHIFT 6 -#define DDR_PHY_DX6GCR0_DQSRPD_MASK 0x00000040U +#define DDR_PHY_DX6GCR0_DQSRPD_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_DQSRPD_SHIFT 6 +#define DDR_PHY_DX6GCR0_DQSRPD_MASK 0x00000040U -/*DQSG Power Down Receiver*/ +/* +* DQSG Power Down Receiver +*/ #undef DDR_PHY_DX6GCR0_DQSGPDR_DEFVAL #undef DDR_PHY_DX6GCR0_DQSGPDR_SHIFT #undef DDR_PHY_DX6GCR0_DQSGPDR_MASK -#define DDR_PHY_DX6GCR0_DQSGPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX6GCR0_DQSGPDR_SHIFT 5 -#define DDR_PHY_DX6GCR0_DQSGPDR_MASK 0x00000020U +#define DDR_PHY_DX6GCR0_DQSGPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_DQSGPDR_SHIFT 5 +#define DDR_PHY_DX6GCR0_DQSGPDR_MASK 0x00000020U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX6GCR0_RESERVED_4_DEFVAL #undef DDR_PHY_DX6GCR0_RESERVED_4_SHIFT #undef DDR_PHY_DX6GCR0_RESERVED_4_MASK -#define DDR_PHY_DX6GCR0_RESERVED_4_DEFVAL 0x40200204 -#define DDR_PHY_DX6GCR0_RESERVED_4_SHIFT 4 -#define DDR_PHY_DX6GCR0_RESERVED_4_MASK 0x00000010U +#define DDR_PHY_DX6GCR0_RESERVED_4_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_RESERVED_4_SHIFT 4 +#define DDR_PHY_DX6GCR0_RESERVED_4_MASK 0x00000010U -/*DQSG On-Die Termination*/ +/* +* DQSG On-Die Termination +*/ #undef DDR_PHY_DX6GCR0_DQSGODT_DEFVAL #undef DDR_PHY_DX6GCR0_DQSGODT_SHIFT #undef DDR_PHY_DX6GCR0_DQSGODT_MASK -#define DDR_PHY_DX6GCR0_DQSGODT_DEFVAL 0x40200204 -#define DDR_PHY_DX6GCR0_DQSGODT_SHIFT 3 -#define DDR_PHY_DX6GCR0_DQSGODT_MASK 0x00000008U +#define DDR_PHY_DX6GCR0_DQSGODT_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_DQSGODT_SHIFT 3 +#define DDR_PHY_DX6GCR0_DQSGODT_MASK 0x00000008U -/*DQSG Output Enable*/ +/* +* DQSG Output Enable +*/ #undef DDR_PHY_DX6GCR0_DQSGOE_DEFVAL #undef DDR_PHY_DX6GCR0_DQSGOE_SHIFT #undef DDR_PHY_DX6GCR0_DQSGOE_MASK -#define DDR_PHY_DX6GCR0_DQSGOE_DEFVAL 0x40200204 -#define DDR_PHY_DX6GCR0_DQSGOE_SHIFT 2 -#define DDR_PHY_DX6GCR0_DQSGOE_MASK 0x00000004U +#define DDR_PHY_DX6GCR0_DQSGOE_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_DQSGOE_SHIFT 2 +#define DDR_PHY_DX6GCR0_DQSGOE_MASK 0x00000004U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX6GCR0_RESERVED_1_0_DEFVAL #undef DDR_PHY_DX6GCR0_RESERVED_1_0_SHIFT #undef DDR_PHY_DX6GCR0_RESERVED_1_0_MASK -#define DDR_PHY_DX6GCR0_RESERVED_1_0_DEFVAL 0x40200204 -#define DDR_PHY_DX6GCR0_RESERVED_1_0_SHIFT 0 -#define DDR_PHY_DX6GCR0_RESERVED_1_0_MASK 0x00000003U +#define DDR_PHY_DX6GCR0_RESERVED_1_0_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_RESERVED_1_0_SHIFT 0 +#define DDR_PHY_DX6GCR0_RESERVED_1_0_MASK 0x00000003U -/*Enables the PDR mode for DQ[7:0]*/ +/* +* Enables the PDR mode for DQ[7:0] +*/ #undef DDR_PHY_DX6GCR1_DXPDRMODE_DEFVAL #undef DDR_PHY_DX6GCR1_DXPDRMODE_SHIFT #undef DDR_PHY_DX6GCR1_DXPDRMODE_MASK -#define DDR_PHY_DX6GCR1_DXPDRMODE_DEFVAL 0x00007FFF -#define DDR_PHY_DX6GCR1_DXPDRMODE_SHIFT 16 -#define DDR_PHY_DX6GCR1_DXPDRMODE_MASK 0xFFFF0000U +#define DDR_PHY_DX6GCR1_DXPDRMODE_DEFVAL 0x00007FFF +#define DDR_PHY_DX6GCR1_DXPDRMODE_SHIFT 16 +#define DDR_PHY_DX6GCR1_DXPDRMODE_MASK 0xFFFF0000U -/*Reserved. Returns zeroes on reads.*/ +/* +* Reserved. Returns zeroes on reads. +*/ #undef DDR_PHY_DX6GCR1_RESERVED_15_DEFVAL #undef DDR_PHY_DX6GCR1_RESERVED_15_SHIFT #undef DDR_PHY_DX6GCR1_RESERVED_15_MASK -#define DDR_PHY_DX6GCR1_RESERVED_15_DEFVAL 0x00007FFF -#define DDR_PHY_DX6GCR1_RESERVED_15_SHIFT 15 -#define DDR_PHY_DX6GCR1_RESERVED_15_MASK 0x00008000U +#define DDR_PHY_DX6GCR1_RESERVED_15_DEFVAL 0x00007FFF +#define DDR_PHY_DX6GCR1_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX6GCR1_RESERVED_15_MASK 0x00008000U -/*Select the delayed or non-delayed read data strobe #*/ +/* +* Select the delayed or non-delayed read data strobe # +*/ #undef DDR_PHY_DX6GCR1_QSNSEL_DEFVAL #undef DDR_PHY_DX6GCR1_QSNSEL_SHIFT #undef DDR_PHY_DX6GCR1_QSNSEL_MASK -#define DDR_PHY_DX6GCR1_QSNSEL_DEFVAL 0x00007FFF -#define DDR_PHY_DX6GCR1_QSNSEL_SHIFT 14 -#define DDR_PHY_DX6GCR1_QSNSEL_MASK 0x00004000U +#define DDR_PHY_DX6GCR1_QSNSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX6GCR1_QSNSEL_SHIFT 14 +#define DDR_PHY_DX6GCR1_QSNSEL_MASK 0x00004000U -/*Select the delayed or non-delayed read data strobe*/ +/* +* Select the delayed or non-delayed read data strobe +*/ #undef DDR_PHY_DX6GCR1_QSSEL_DEFVAL #undef DDR_PHY_DX6GCR1_QSSEL_SHIFT #undef DDR_PHY_DX6GCR1_QSSEL_MASK -#define DDR_PHY_DX6GCR1_QSSEL_DEFVAL 0x00007FFF -#define DDR_PHY_DX6GCR1_QSSEL_SHIFT 13 -#define DDR_PHY_DX6GCR1_QSSEL_MASK 0x00002000U +#define DDR_PHY_DX6GCR1_QSSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX6GCR1_QSSEL_SHIFT 13 +#define DDR_PHY_DX6GCR1_QSSEL_MASK 0x00002000U -/*Enables Read Data Strobe in a byte lane*/ +/* +* Enables Read Data Strobe in a byte lane +*/ #undef DDR_PHY_DX6GCR1_OEEN_DEFVAL #undef DDR_PHY_DX6GCR1_OEEN_SHIFT #undef DDR_PHY_DX6GCR1_OEEN_MASK -#define DDR_PHY_DX6GCR1_OEEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX6GCR1_OEEN_SHIFT 12 -#define DDR_PHY_DX6GCR1_OEEN_MASK 0x00001000U +#define DDR_PHY_DX6GCR1_OEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX6GCR1_OEEN_SHIFT 12 +#define DDR_PHY_DX6GCR1_OEEN_MASK 0x00001000U -/*Enables PDR in a byte lane*/ +/* +* Enables PDR in a byte lane +*/ #undef DDR_PHY_DX6GCR1_PDREN_DEFVAL #undef DDR_PHY_DX6GCR1_PDREN_SHIFT #undef DDR_PHY_DX6GCR1_PDREN_MASK -#define DDR_PHY_DX6GCR1_PDREN_DEFVAL 0x00007FFF -#define DDR_PHY_DX6GCR1_PDREN_SHIFT 11 -#define DDR_PHY_DX6GCR1_PDREN_MASK 0x00000800U +#define DDR_PHY_DX6GCR1_PDREN_DEFVAL 0x00007FFF +#define DDR_PHY_DX6GCR1_PDREN_SHIFT 11 +#define DDR_PHY_DX6GCR1_PDREN_MASK 0x00000800U -/*Enables ODT/TE in a byte lane*/ +/* +* Enables ODT/TE in a byte lane +*/ #undef DDR_PHY_DX6GCR1_TEEN_DEFVAL #undef DDR_PHY_DX6GCR1_TEEN_SHIFT #undef DDR_PHY_DX6GCR1_TEEN_MASK -#define DDR_PHY_DX6GCR1_TEEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX6GCR1_TEEN_SHIFT 10 -#define DDR_PHY_DX6GCR1_TEEN_MASK 0x00000400U +#define DDR_PHY_DX6GCR1_TEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX6GCR1_TEEN_SHIFT 10 +#define DDR_PHY_DX6GCR1_TEEN_MASK 0x00000400U -/*Enables Write Data strobe in a byte lane*/ +/* +* Enables Write Data strobe in a byte lane +*/ #undef DDR_PHY_DX6GCR1_DSEN_DEFVAL #undef DDR_PHY_DX6GCR1_DSEN_SHIFT #undef DDR_PHY_DX6GCR1_DSEN_MASK -#define DDR_PHY_DX6GCR1_DSEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX6GCR1_DSEN_SHIFT 9 -#define DDR_PHY_DX6GCR1_DSEN_MASK 0x00000200U +#define DDR_PHY_DX6GCR1_DSEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX6GCR1_DSEN_SHIFT 9 +#define DDR_PHY_DX6GCR1_DSEN_MASK 0x00000200U -/*Enables DM pin in a byte lane*/ +/* +* Enables DM pin in a byte lane +*/ #undef DDR_PHY_DX6GCR1_DMEN_DEFVAL #undef DDR_PHY_DX6GCR1_DMEN_SHIFT #undef DDR_PHY_DX6GCR1_DMEN_MASK -#define DDR_PHY_DX6GCR1_DMEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX6GCR1_DMEN_SHIFT 8 -#define DDR_PHY_DX6GCR1_DMEN_MASK 0x00000100U +#define DDR_PHY_DX6GCR1_DMEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX6GCR1_DMEN_SHIFT 8 +#define DDR_PHY_DX6GCR1_DMEN_MASK 0x00000100U -/*Enables DQ corresponding to each bit in a byte*/ +/* +* Enables DQ corresponding to each bit in a byte +*/ #undef DDR_PHY_DX6GCR1_DQEN_DEFVAL #undef DDR_PHY_DX6GCR1_DQEN_SHIFT #undef DDR_PHY_DX6GCR1_DQEN_MASK -#define DDR_PHY_DX6GCR1_DQEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX6GCR1_DQEN_SHIFT 0 -#define DDR_PHY_DX6GCR1_DQEN_MASK 0x000000FFU +#define DDR_PHY_DX6GCR1_DQEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX6GCR1_DQEN_SHIFT 0 +#define DDR_PHY_DX6GCR1_DQEN_MASK 0x000000FFU -/*Byte lane VREF IOM (Used only by D4MU IOs)*/ +/* +* Byte lane VREF IOM (Used only by D4MU IOs) +*/ #undef DDR_PHY_DX6GCR4_RESERVED_31_29_DEFVAL #undef DDR_PHY_DX6GCR4_RESERVED_31_29_SHIFT #undef DDR_PHY_DX6GCR4_RESERVED_31_29_MASK -#define DDR_PHY_DX6GCR4_RESERVED_31_29_DEFVAL 0x0E00003C -#define DDR_PHY_DX6GCR4_RESERVED_31_29_SHIFT 29 -#define DDR_PHY_DX6GCR4_RESERVED_31_29_MASK 0xE0000000U +#define DDR_PHY_DX6GCR4_RESERVED_31_29_DEFVAL 0x0E00003C +#define DDR_PHY_DX6GCR4_RESERVED_31_29_SHIFT 29 +#define DDR_PHY_DX6GCR4_RESERVED_31_29_MASK 0xE0000000U -/*Byte Lane VREF Pad Enable*/ +/* +* Byte Lane VREF Pad Enable +*/ #undef DDR_PHY_DX6GCR4_DXREFPEN_DEFVAL #undef DDR_PHY_DX6GCR4_DXREFPEN_SHIFT #undef DDR_PHY_DX6GCR4_DXREFPEN_MASK -#define DDR_PHY_DX6GCR4_DXREFPEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX6GCR4_DXREFPEN_SHIFT 28 -#define DDR_PHY_DX6GCR4_DXREFPEN_MASK 0x10000000U +#define DDR_PHY_DX6GCR4_DXREFPEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX6GCR4_DXREFPEN_SHIFT 28 +#define DDR_PHY_DX6GCR4_DXREFPEN_MASK 0x10000000U -/*Byte Lane Internal VREF Enable*/ +/* +* Byte Lane Internal VREF Enable +*/ #undef DDR_PHY_DX6GCR4_DXREFEEN_DEFVAL #undef DDR_PHY_DX6GCR4_DXREFEEN_SHIFT #undef DDR_PHY_DX6GCR4_DXREFEEN_MASK -#define DDR_PHY_DX6GCR4_DXREFEEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX6GCR4_DXREFEEN_SHIFT 26 -#define DDR_PHY_DX6GCR4_DXREFEEN_MASK 0x0C000000U +#define DDR_PHY_DX6GCR4_DXREFEEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX6GCR4_DXREFEEN_SHIFT 26 +#define DDR_PHY_DX6GCR4_DXREFEEN_MASK 0x0C000000U -/*Byte Lane Single-End VREF Enable*/ +/* +* Byte Lane Single-End VREF Enable +*/ #undef DDR_PHY_DX6GCR4_DXREFSEN_DEFVAL #undef DDR_PHY_DX6GCR4_DXREFSEN_SHIFT #undef DDR_PHY_DX6GCR4_DXREFSEN_MASK -#define DDR_PHY_DX6GCR4_DXREFSEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX6GCR4_DXREFSEN_SHIFT 25 -#define DDR_PHY_DX6GCR4_DXREFSEN_MASK 0x02000000U +#define DDR_PHY_DX6GCR4_DXREFSEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX6GCR4_DXREFSEN_SHIFT 25 +#define DDR_PHY_DX6GCR4_DXREFSEN_MASK 0x02000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX6GCR4_RESERVED_24_DEFVAL #undef DDR_PHY_DX6GCR4_RESERVED_24_SHIFT #undef DDR_PHY_DX6GCR4_RESERVED_24_MASK -#define DDR_PHY_DX6GCR4_RESERVED_24_DEFVAL 0x0E00003C -#define DDR_PHY_DX6GCR4_RESERVED_24_SHIFT 24 -#define DDR_PHY_DX6GCR4_RESERVED_24_MASK 0x01000000U +#define DDR_PHY_DX6GCR4_RESERVED_24_DEFVAL 0x0E00003C +#define DDR_PHY_DX6GCR4_RESERVED_24_SHIFT 24 +#define DDR_PHY_DX6GCR4_RESERVED_24_MASK 0x01000000U -/*External VREF generator REFSEL range select*/ +/* +* External VREF generator REFSEL range select +*/ #undef DDR_PHY_DX6GCR4_DXREFESELRANGE_DEFVAL #undef DDR_PHY_DX6GCR4_DXREFESELRANGE_SHIFT #undef DDR_PHY_DX6GCR4_DXREFESELRANGE_MASK -#define DDR_PHY_DX6GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C -#define DDR_PHY_DX6GCR4_DXREFESELRANGE_SHIFT 23 -#define DDR_PHY_DX6GCR4_DXREFESELRANGE_MASK 0x00800000U +#define DDR_PHY_DX6GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX6GCR4_DXREFESELRANGE_SHIFT 23 +#define DDR_PHY_DX6GCR4_DXREFESELRANGE_MASK 0x00800000U -/*Byte Lane External VREF Select*/ +/* +* Byte Lane External VREF Select +*/ #undef DDR_PHY_DX6GCR4_DXREFESEL_DEFVAL #undef DDR_PHY_DX6GCR4_DXREFESEL_SHIFT #undef DDR_PHY_DX6GCR4_DXREFESEL_MASK -#define DDR_PHY_DX6GCR4_DXREFESEL_DEFVAL 0x0E00003C -#define DDR_PHY_DX6GCR4_DXREFESEL_SHIFT 16 -#define DDR_PHY_DX6GCR4_DXREFESEL_MASK 0x007F0000U +#define DDR_PHY_DX6GCR4_DXREFESEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX6GCR4_DXREFESEL_SHIFT 16 +#define DDR_PHY_DX6GCR4_DXREFESEL_MASK 0x007F0000U -/*Single ended VREF generator REFSEL range select*/ +/* +* Single ended VREF generator REFSEL range select +*/ #undef DDR_PHY_DX6GCR4_DXREFSSELRANGE_DEFVAL #undef DDR_PHY_DX6GCR4_DXREFSSELRANGE_SHIFT #undef DDR_PHY_DX6GCR4_DXREFSSELRANGE_MASK -#define DDR_PHY_DX6GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C -#define DDR_PHY_DX6GCR4_DXREFSSELRANGE_SHIFT 15 -#define DDR_PHY_DX6GCR4_DXREFSSELRANGE_MASK 0x00008000U +#define DDR_PHY_DX6GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX6GCR4_DXREFSSELRANGE_SHIFT 15 +#define DDR_PHY_DX6GCR4_DXREFSSELRANGE_MASK 0x00008000U -/*Byte Lane Single-End VREF Select*/ +/* +* Byte Lane Single-End VREF Select +*/ #undef DDR_PHY_DX6GCR4_DXREFSSEL_DEFVAL #undef DDR_PHY_DX6GCR4_DXREFSSEL_SHIFT #undef DDR_PHY_DX6GCR4_DXREFSSEL_MASK -#define DDR_PHY_DX6GCR4_DXREFSSEL_DEFVAL 0x0E00003C -#define DDR_PHY_DX6GCR4_DXREFSSEL_SHIFT 8 -#define DDR_PHY_DX6GCR4_DXREFSSEL_MASK 0x00007F00U +#define DDR_PHY_DX6GCR4_DXREFSSEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX6GCR4_DXREFSSEL_SHIFT 8 +#define DDR_PHY_DX6GCR4_DXREFSSEL_MASK 0x00007F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX6GCR4_RESERVED_7_6_DEFVAL #undef DDR_PHY_DX6GCR4_RESERVED_7_6_SHIFT #undef DDR_PHY_DX6GCR4_RESERVED_7_6_MASK -#define DDR_PHY_DX6GCR4_RESERVED_7_6_DEFVAL 0x0E00003C -#define DDR_PHY_DX6GCR4_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_DX6GCR4_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_DX6GCR4_RESERVED_7_6_DEFVAL 0x0E00003C +#define DDR_PHY_DX6GCR4_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX6GCR4_RESERVED_7_6_MASK 0x000000C0U -/*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/ +/* +* VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. +*/ #undef DDR_PHY_DX6GCR4_DXREFIEN_DEFVAL #undef DDR_PHY_DX6GCR4_DXREFIEN_SHIFT #undef DDR_PHY_DX6GCR4_DXREFIEN_MASK -#define DDR_PHY_DX6GCR4_DXREFIEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX6GCR4_DXREFIEN_SHIFT 2 -#define DDR_PHY_DX6GCR4_DXREFIEN_MASK 0x0000003CU +#define DDR_PHY_DX6GCR4_DXREFIEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX6GCR4_DXREFIEN_SHIFT 2 +#define DDR_PHY_DX6GCR4_DXREFIEN_MASK 0x0000003CU -/*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/ +/* +* VRMON control for DQ IO (Single Ended) buffers of a byte lane. +*/ #undef DDR_PHY_DX6GCR4_DXREFIMON_DEFVAL #undef DDR_PHY_DX6GCR4_DXREFIMON_SHIFT #undef DDR_PHY_DX6GCR4_DXREFIMON_MASK -#define DDR_PHY_DX6GCR4_DXREFIMON_DEFVAL 0x0E00003C -#define DDR_PHY_DX6GCR4_DXREFIMON_SHIFT 0 -#define DDR_PHY_DX6GCR4_DXREFIMON_MASK 0x00000003U +#define DDR_PHY_DX6GCR4_DXREFIMON_DEFVAL 0x0E00003C +#define DDR_PHY_DX6GCR4_DXREFIMON_SHIFT 0 +#define DDR_PHY_DX6GCR4_DXREFIMON_MASK 0x00000003U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX6GCR5_RESERVED_31_DEFVAL #undef DDR_PHY_DX6GCR5_RESERVED_31_SHIFT #undef DDR_PHY_DX6GCR5_RESERVED_31_MASK -#define DDR_PHY_DX6GCR5_RESERVED_31_DEFVAL 0x09090909 -#define DDR_PHY_DX6GCR5_RESERVED_31_SHIFT 31 -#define DDR_PHY_DX6GCR5_RESERVED_31_MASK 0x80000000U +#define DDR_PHY_DX6GCR5_RESERVED_31_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR5_RESERVED_31_SHIFT 31 +#define DDR_PHY_DX6GCR5_RESERVED_31_MASK 0x80000000U -/*Byte Lane internal VREF Select for Rank 3*/ +/* +* Byte Lane internal VREF Select for Rank 3 +*/ #undef DDR_PHY_DX6GCR5_DXREFISELR3_DEFVAL #undef DDR_PHY_DX6GCR5_DXREFISELR3_SHIFT #undef DDR_PHY_DX6GCR5_DXREFISELR3_MASK -#define DDR_PHY_DX6GCR5_DXREFISELR3_DEFVAL 0x09090909 -#define DDR_PHY_DX6GCR5_DXREFISELR3_SHIFT 24 -#define DDR_PHY_DX6GCR5_DXREFISELR3_MASK 0x7F000000U +#define DDR_PHY_DX6GCR5_DXREFISELR3_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR5_DXREFISELR3_SHIFT 24 +#define DDR_PHY_DX6GCR5_DXREFISELR3_MASK 0x7F000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX6GCR5_RESERVED_23_DEFVAL #undef DDR_PHY_DX6GCR5_RESERVED_23_SHIFT #undef DDR_PHY_DX6GCR5_RESERVED_23_MASK -#define DDR_PHY_DX6GCR5_RESERVED_23_DEFVAL 0x09090909 -#define DDR_PHY_DX6GCR5_RESERVED_23_SHIFT 23 -#define DDR_PHY_DX6GCR5_RESERVED_23_MASK 0x00800000U +#define DDR_PHY_DX6GCR5_RESERVED_23_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR5_RESERVED_23_SHIFT 23 +#define DDR_PHY_DX6GCR5_RESERVED_23_MASK 0x00800000U -/*Byte Lane internal VREF Select for Rank 2*/ +/* +* Byte Lane internal VREF Select for Rank 2 +*/ #undef DDR_PHY_DX6GCR5_DXREFISELR2_DEFVAL #undef DDR_PHY_DX6GCR5_DXREFISELR2_SHIFT #undef DDR_PHY_DX6GCR5_DXREFISELR2_MASK -#define DDR_PHY_DX6GCR5_DXREFISELR2_DEFVAL 0x09090909 -#define DDR_PHY_DX6GCR5_DXREFISELR2_SHIFT 16 -#define DDR_PHY_DX6GCR5_DXREFISELR2_MASK 0x007F0000U +#define DDR_PHY_DX6GCR5_DXREFISELR2_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR5_DXREFISELR2_SHIFT 16 +#define DDR_PHY_DX6GCR5_DXREFISELR2_MASK 0x007F0000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX6GCR5_RESERVED_15_DEFVAL #undef DDR_PHY_DX6GCR5_RESERVED_15_SHIFT #undef DDR_PHY_DX6GCR5_RESERVED_15_MASK -#define DDR_PHY_DX6GCR5_RESERVED_15_DEFVAL 0x09090909 -#define DDR_PHY_DX6GCR5_RESERVED_15_SHIFT 15 -#define DDR_PHY_DX6GCR5_RESERVED_15_MASK 0x00008000U +#define DDR_PHY_DX6GCR5_RESERVED_15_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR5_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX6GCR5_RESERVED_15_MASK 0x00008000U -/*Byte Lane internal VREF Select for Rank 1*/ +/* +* Byte Lane internal VREF Select for Rank 1 +*/ #undef DDR_PHY_DX6GCR5_DXREFISELR1_DEFVAL #undef DDR_PHY_DX6GCR5_DXREFISELR1_SHIFT #undef DDR_PHY_DX6GCR5_DXREFISELR1_MASK -#define DDR_PHY_DX6GCR5_DXREFISELR1_DEFVAL 0x09090909 -#define DDR_PHY_DX6GCR5_DXREFISELR1_SHIFT 8 -#define DDR_PHY_DX6GCR5_DXREFISELR1_MASK 0x00007F00U +#define DDR_PHY_DX6GCR5_DXREFISELR1_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR5_DXREFISELR1_SHIFT 8 +#define DDR_PHY_DX6GCR5_DXREFISELR1_MASK 0x00007F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX6GCR5_RESERVED_7_DEFVAL #undef DDR_PHY_DX6GCR5_RESERVED_7_SHIFT #undef DDR_PHY_DX6GCR5_RESERVED_7_MASK -#define DDR_PHY_DX6GCR5_RESERVED_7_DEFVAL 0x09090909 -#define DDR_PHY_DX6GCR5_RESERVED_7_SHIFT 7 -#define DDR_PHY_DX6GCR5_RESERVED_7_MASK 0x00000080U +#define DDR_PHY_DX6GCR5_RESERVED_7_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR5_RESERVED_7_SHIFT 7 +#define DDR_PHY_DX6GCR5_RESERVED_7_MASK 0x00000080U -/*Byte Lane internal VREF Select for Rank 0*/ +/* +* Byte Lane internal VREF Select for Rank 0 +*/ #undef DDR_PHY_DX6GCR5_DXREFISELR0_DEFVAL #undef DDR_PHY_DX6GCR5_DXREFISELR0_SHIFT #undef DDR_PHY_DX6GCR5_DXREFISELR0_MASK -#define DDR_PHY_DX6GCR5_DXREFISELR0_DEFVAL 0x09090909 -#define DDR_PHY_DX6GCR5_DXREFISELR0_SHIFT 0 -#define DDR_PHY_DX6GCR5_DXREFISELR0_MASK 0x0000007FU +#define DDR_PHY_DX6GCR5_DXREFISELR0_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR5_DXREFISELR0_SHIFT 0 +#define DDR_PHY_DX6GCR5_DXREFISELR0_MASK 0x0000007FU -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX6GCR6_RESERVED_31_30_DEFVAL #undef DDR_PHY_DX6GCR6_RESERVED_31_30_SHIFT #undef DDR_PHY_DX6GCR6_RESERVED_31_30_MASK -#define DDR_PHY_DX6GCR6_RESERVED_31_30_DEFVAL 0x09090909 -#define DDR_PHY_DX6GCR6_RESERVED_31_30_SHIFT 30 -#define DDR_PHY_DX6GCR6_RESERVED_31_30_MASK 0xC0000000U +#define DDR_PHY_DX6GCR6_RESERVED_31_30_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR6_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX6GCR6_RESERVED_31_30_MASK 0xC0000000U -/*DRAM DQ VREF Select for Rank3*/ +/* +* DRAM DQ VREF Select for Rank3 +*/ #undef DDR_PHY_DX6GCR6_DXDQVREFR3_DEFVAL #undef DDR_PHY_DX6GCR6_DXDQVREFR3_SHIFT #undef DDR_PHY_DX6GCR6_DXDQVREFR3_MASK -#define DDR_PHY_DX6GCR6_DXDQVREFR3_DEFVAL 0x09090909 -#define DDR_PHY_DX6GCR6_DXDQVREFR3_SHIFT 24 -#define DDR_PHY_DX6GCR6_DXDQVREFR3_MASK 0x3F000000U +#define DDR_PHY_DX6GCR6_DXDQVREFR3_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR6_DXDQVREFR3_SHIFT 24 +#define DDR_PHY_DX6GCR6_DXDQVREFR3_MASK 0x3F000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX6GCR6_RESERVED_23_22_DEFVAL #undef DDR_PHY_DX6GCR6_RESERVED_23_22_SHIFT #undef DDR_PHY_DX6GCR6_RESERVED_23_22_MASK -#define DDR_PHY_DX6GCR6_RESERVED_23_22_DEFVAL 0x09090909 -#define DDR_PHY_DX6GCR6_RESERVED_23_22_SHIFT 22 -#define DDR_PHY_DX6GCR6_RESERVED_23_22_MASK 0x00C00000U +#define DDR_PHY_DX6GCR6_RESERVED_23_22_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR6_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX6GCR6_RESERVED_23_22_MASK 0x00C00000U -/*DRAM DQ VREF Select for Rank2*/ +/* +* DRAM DQ VREF Select for Rank2 +*/ #undef DDR_PHY_DX6GCR6_DXDQVREFR2_DEFVAL #undef DDR_PHY_DX6GCR6_DXDQVREFR2_SHIFT #undef DDR_PHY_DX6GCR6_DXDQVREFR2_MASK -#define DDR_PHY_DX6GCR6_DXDQVREFR2_DEFVAL 0x09090909 -#define DDR_PHY_DX6GCR6_DXDQVREFR2_SHIFT 16 -#define DDR_PHY_DX6GCR6_DXDQVREFR2_MASK 0x003F0000U +#define DDR_PHY_DX6GCR6_DXDQVREFR2_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR6_DXDQVREFR2_SHIFT 16 +#define DDR_PHY_DX6GCR6_DXDQVREFR2_MASK 0x003F0000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX6GCR6_RESERVED_15_14_DEFVAL #undef DDR_PHY_DX6GCR6_RESERVED_15_14_SHIFT #undef DDR_PHY_DX6GCR6_RESERVED_15_14_MASK -#define DDR_PHY_DX6GCR6_RESERVED_15_14_DEFVAL 0x09090909 -#define DDR_PHY_DX6GCR6_RESERVED_15_14_SHIFT 14 -#define DDR_PHY_DX6GCR6_RESERVED_15_14_MASK 0x0000C000U +#define DDR_PHY_DX6GCR6_RESERVED_15_14_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR6_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_DX6GCR6_RESERVED_15_14_MASK 0x0000C000U -/*DRAM DQ VREF Select for Rank1*/ +/* +* DRAM DQ VREF Select for Rank1 +*/ #undef DDR_PHY_DX6GCR6_DXDQVREFR1_DEFVAL #undef DDR_PHY_DX6GCR6_DXDQVREFR1_SHIFT #undef DDR_PHY_DX6GCR6_DXDQVREFR1_MASK -#define DDR_PHY_DX6GCR6_DXDQVREFR1_DEFVAL 0x09090909 -#define DDR_PHY_DX6GCR6_DXDQVREFR1_SHIFT 8 -#define DDR_PHY_DX6GCR6_DXDQVREFR1_MASK 0x00003F00U +#define DDR_PHY_DX6GCR6_DXDQVREFR1_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR6_DXDQVREFR1_SHIFT 8 +#define DDR_PHY_DX6GCR6_DXDQVREFR1_MASK 0x00003F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX6GCR6_RESERVED_7_6_DEFVAL #undef DDR_PHY_DX6GCR6_RESERVED_7_6_SHIFT #undef DDR_PHY_DX6GCR6_RESERVED_7_6_MASK -#define DDR_PHY_DX6GCR6_RESERVED_7_6_DEFVAL 0x09090909 -#define DDR_PHY_DX6GCR6_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_DX6GCR6_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_DX6GCR6_RESERVED_7_6_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR6_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX6GCR6_RESERVED_7_6_MASK 0x000000C0U -/*DRAM DQ VREF Select for Rank0*/ +/* +* DRAM DQ VREF Select for Rank0 +*/ #undef DDR_PHY_DX6GCR6_DXDQVREFR0_DEFVAL #undef DDR_PHY_DX6GCR6_DXDQVREFR0_SHIFT #undef DDR_PHY_DX6GCR6_DXDQVREFR0_MASK -#define DDR_PHY_DX6GCR6_DXDQVREFR0_DEFVAL 0x09090909 -#define DDR_PHY_DX6GCR6_DXDQVREFR0_SHIFT 0 -#define DDR_PHY_DX6GCR6_DXDQVREFR0_MASK 0x0000003FU +#define DDR_PHY_DX6GCR6_DXDQVREFR0_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR6_DXDQVREFR0_SHIFT 0 +#define DDR_PHY_DX6GCR6_DXDQVREFR0_MASK 0x0000003FU -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX6LCDLR2_RESERVED_31_25_DEFVAL -#undef DDR_PHY_DX6LCDLR2_RESERVED_31_25_SHIFT -#undef DDR_PHY_DX6LCDLR2_RESERVED_31_25_MASK -#define DDR_PHY_DX6LCDLR2_RESERVED_31_25_DEFVAL 0x00000000 -#define DDR_PHY_DX6LCDLR2_RESERVED_31_25_SHIFT 25 -#define DDR_PHY_DX6LCDLR2_RESERVED_31_25_MASK 0xFE000000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX6LCDLR2_RESERVED_24_16_DEFVAL -#undef DDR_PHY_DX6LCDLR2_RESERVED_24_16_SHIFT -#undef DDR_PHY_DX6LCDLR2_RESERVED_24_16_MASK -#define DDR_PHY_DX6LCDLR2_RESERVED_24_16_DEFVAL 0x00000000 -#define DDR_PHY_DX6LCDLR2_RESERVED_24_16_SHIFT 16 -#define DDR_PHY_DX6LCDLR2_RESERVED_24_16_MASK 0x01FF0000U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX6LCDLR2_RESERVED_15_9_DEFVAL -#undef DDR_PHY_DX6LCDLR2_RESERVED_15_9_SHIFT -#undef DDR_PHY_DX6LCDLR2_RESERVED_15_9_MASK -#define DDR_PHY_DX6LCDLR2_RESERVED_15_9_DEFVAL 0x00000000 -#define DDR_PHY_DX6LCDLR2_RESERVED_15_9_SHIFT 9 -#define DDR_PHY_DX6LCDLR2_RESERVED_15_9_MASK 0x0000FE00U - -/*Read DQS Gating Delay*/ -#undef DDR_PHY_DX6LCDLR2_DQSGD_DEFVAL -#undef DDR_PHY_DX6LCDLR2_DQSGD_SHIFT -#undef DDR_PHY_DX6LCDLR2_DQSGD_MASK -#define DDR_PHY_DX6LCDLR2_DQSGD_DEFVAL 0x00000000 -#define DDR_PHY_DX6LCDLR2_DQSGD_SHIFT 0 -#define DDR_PHY_DX6LCDLR2_DQSGD_MASK 0x000001FFU - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX6GTR0_RESERVED_31_24_DEFVAL -#undef DDR_PHY_DX6GTR0_RESERVED_31_24_SHIFT -#undef DDR_PHY_DX6GTR0_RESERVED_31_24_MASK -#define DDR_PHY_DX6GTR0_RESERVED_31_24_DEFVAL 0x00020000 -#define DDR_PHY_DX6GTR0_RESERVED_31_24_SHIFT 27 -#define DDR_PHY_DX6GTR0_RESERVED_31_24_MASK 0xF8000000U - -/*DQ Write Path Latency Pipeline*/ -#undef DDR_PHY_DX6GTR0_WDQSL_DEFVAL -#undef DDR_PHY_DX6GTR0_WDQSL_SHIFT -#undef DDR_PHY_DX6GTR0_WDQSL_MASK -#define DDR_PHY_DX6GTR0_WDQSL_DEFVAL 0x00020000 -#define DDR_PHY_DX6GTR0_WDQSL_SHIFT 24 -#define DDR_PHY_DX6GTR0_WDQSL_MASK 0x07000000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX6GTR0_RESERVED_23_20_DEFVAL -#undef DDR_PHY_DX6GTR0_RESERVED_23_20_SHIFT -#undef DDR_PHY_DX6GTR0_RESERVED_23_20_MASK -#define DDR_PHY_DX6GTR0_RESERVED_23_20_DEFVAL 0x00020000 -#define DDR_PHY_DX6GTR0_RESERVED_23_20_SHIFT 20 -#define DDR_PHY_DX6GTR0_RESERVED_23_20_MASK 0x00F00000U - -/*Write Leveling System Latency*/ -#undef DDR_PHY_DX6GTR0_WLSL_DEFVAL -#undef DDR_PHY_DX6GTR0_WLSL_SHIFT -#undef DDR_PHY_DX6GTR0_WLSL_MASK -#define DDR_PHY_DX6GTR0_WLSL_DEFVAL 0x00020000 -#define DDR_PHY_DX6GTR0_WLSL_SHIFT 16 -#define DDR_PHY_DX6GTR0_WLSL_MASK 0x000F0000U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX6GTR0_RESERVED_15_13_DEFVAL -#undef DDR_PHY_DX6GTR0_RESERVED_15_13_SHIFT -#undef DDR_PHY_DX6GTR0_RESERVED_15_13_MASK -#define DDR_PHY_DX6GTR0_RESERVED_15_13_DEFVAL 0x00020000 -#define DDR_PHY_DX6GTR0_RESERVED_15_13_SHIFT 13 -#define DDR_PHY_DX6GTR0_RESERVED_15_13_MASK 0x0000E000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX6GTR0_RESERVED_12_8_DEFVAL -#undef DDR_PHY_DX6GTR0_RESERVED_12_8_SHIFT -#undef DDR_PHY_DX6GTR0_RESERVED_12_8_MASK -#define DDR_PHY_DX6GTR0_RESERVED_12_8_DEFVAL 0x00020000 -#define DDR_PHY_DX6GTR0_RESERVED_12_8_SHIFT 8 -#define DDR_PHY_DX6GTR0_RESERVED_12_8_MASK 0x00001F00U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX6GTR0_RESERVED_7_5_DEFVAL -#undef DDR_PHY_DX6GTR0_RESERVED_7_5_SHIFT -#undef DDR_PHY_DX6GTR0_RESERVED_7_5_MASK -#define DDR_PHY_DX6GTR0_RESERVED_7_5_DEFVAL 0x00020000 -#define DDR_PHY_DX6GTR0_RESERVED_7_5_SHIFT 5 -#define DDR_PHY_DX6GTR0_RESERVED_7_5_MASK 0x000000E0U - -/*DQS Gating System Latency*/ -#undef DDR_PHY_DX6GTR0_DGSL_DEFVAL -#undef DDR_PHY_DX6GTR0_DGSL_SHIFT -#undef DDR_PHY_DX6GTR0_DGSL_MASK -#define DDR_PHY_DX6GTR0_DGSL_DEFVAL 0x00020000 -#define DDR_PHY_DX6GTR0_DGSL_SHIFT 0 -#define DDR_PHY_DX6GTR0_DGSL_MASK 0x0000001FU - -/*Calibration Bypass*/ +/* +* Calibration Bypass +*/ #undef DDR_PHY_DX7GCR0_CALBYP_DEFVAL #undef DDR_PHY_DX7GCR0_CALBYP_SHIFT #undef DDR_PHY_DX7GCR0_CALBYP_MASK -#define DDR_PHY_DX7GCR0_CALBYP_DEFVAL 0x40200204 -#define DDR_PHY_DX7GCR0_CALBYP_SHIFT 31 -#define DDR_PHY_DX7GCR0_CALBYP_MASK 0x80000000U +#define DDR_PHY_DX7GCR0_CALBYP_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_CALBYP_SHIFT 31 +#define DDR_PHY_DX7GCR0_CALBYP_MASK 0x80000000U -/*Master Delay Line Enable*/ +/* +* Master Delay Line Enable +*/ #undef DDR_PHY_DX7GCR0_MDLEN_DEFVAL #undef DDR_PHY_DX7GCR0_MDLEN_SHIFT #undef DDR_PHY_DX7GCR0_MDLEN_MASK -#define DDR_PHY_DX7GCR0_MDLEN_DEFVAL 0x40200204 -#define DDR_PHY_DX7GCR0_MDLEN_SHIFT 30 -#define DDR_PHY_DX7GCR0_MDLEN_MASK 0x40000000U +#define DDR_PHY_DX7GCR0_MDLEN_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_MDLEN_SHIFT 30 +#define DDR_PHY_DX7GCR0_MDLEN_MASK 0x40000000U -/*Configurable ODT(TE) Phase Shift*/ +/* +* Configurable ODT(TE) Phase Shift +*/ #undef DDR_PHY_DX7GCR0_CODTSHFT_DEFVAL #undef DDR_PHY_DX7GCR0_CODTSHFT_SHIFT #undef DDR_PHY_DX7GCR0_CODTSHFT_MASK -#define DDR_PHY_DX7GCR0_CODTSHFT_DEFVAL 0x40200204 -#define DDR_PHY_DX7GCR0_CODTSHFT_SHIFT 28 -#define DDR_PHY_DX7GCR0_CODTSHFT_MASK 0x30000000U +#define DDR_PHY_DX7GCR0_CODTSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_CODTSHFT_SHIFT 28 +#define DDR_PHY_DX7GCR0_CODTSHFT_MASK 0x30000000U -/*DQS Duty Cycle Correction*/ +/* +* DQS Duty Cycle Correction +*/ #undef DDR_PHY_DX7GCR0_DQSDCC_DEFVAL #undef DDR_PHY_DX7GCR0_DQSDCC_SHIFT #undef DDR_PHY_DX7GCR0_DQSDCC_MASK -#define DDR_PHY_DX7GCR0_DQSDCC_DEFVAL 0x40200204 -#define DDR_PHY_DX7GCR0_DQSDCC_SHIFT 24 -#define DDR_PHY_DX7GCR0_DQSDCC_MASK 0x0F000000U +#define DDR_PHY_DX7GCR0_DQSDCC_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_DQSDCC_SHIFT 24 +#define DDR_PHY_DX7GCR0_DQSDCC_MASK 0x0F000000U -/*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/ +/* +* Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY +*/ #undef DDR_PHY_DX7GCR0_RDDLY_DEFVAL #undef DDR_PHY_DX7GCR0_RDDLY_SHIFT #undef DDR_PHY_DX7GCR0_RDDLY_MASK -#define DDR_PHY_DX7GCR0_RDDLY_DEFVAL 0x40200204 -#define DDR_PHY_DX7GCR0_RDDLY_SHIFT 20 -#define DDR_PHY_DX7GCR0_RDDLY_MASK 0x00F00000U +#define DDR_PHY_DX7GCR0_RDDLY_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_RDDLY_SHIFT 20 +#define DDR_PHY_DX7GCR0_RDDLY_MASK 0x00F00000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX7GCR0_RESERVED_19_14_DEFVAL #undef DDR_PHY_DX7GCR0_RESERVED_19_14_SHIFT #undef DDR_PHY_DX7GCR0_RESERVED_19_14_MASK -#define DDR_PHY_DX7GCR0_RESERVED_19_14_DEFVAL 0x40200204 -#define DDR_PHY_DX7GCR0_RESERVED_19_14_SHIFT 14 -#define DDR_PHY_DX7GCR0_RESERVED_19_14_MASK 0x000FC000U +#define DDR_PHY_DX7GCR0_RESERVED_19_14_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_RESERVED_19_14_SHIFT 14 +#define DDR_PHY_DX7GCR0_RESERVED_19_14_MASK 0x000FC000U -/*DQSNSE Power Down Receiver*/ +/* +* DQSNSE Power Down Receiver +*/ #undef DDR_PHY_DX7GCR0_DQSNSEPDR_DEFVAL #undef DDR_PHY_DX7GCR0_DQSNSEPDR_SHIFT #undef DDR_PHY_DX7GCR0_DQSNSEPDR_MASK -#define DDR_PHY_DX7GCR0_DQSNSEPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX7GCR0_DQSNSEPDR_SHIFT 13 -#define DDR_PHY_DX7GCR0_DQSNSEPDR_MASK 0x00002000U +#define DDR_PHY_DX7GCR0_DQSNSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_DQSNSEPDR_SHIFT 13 +#define DDR_PHY_DX7GCR0_DQSNSEPDR_MASK 0x00002000U -/*DQSSE Power Down Receiver*/ +/* +* DQSSE Power Down Receiver +*/ #undef DDR_PHY_DX7GCR0_DQSSEPDR_DEFVAL #undef DDR_PHY_DX7GCR0_DQSSEPDR_SHIFT #undef DDR_PHY_DX7GCR0_DQSSEPDR_MASK -#define DDR_PHY_DX7GCR0_DQSSEPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX7GCR0_DQSSEPDR_SHIFT 12 -#define DDR_PHY_DX7GCR0_DQSSEPDR_MASK 0x00001000U +#define DDR_PHY_DX7GCR0_DQSSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_DQSSEPDR_SHIFT 12 +#define DDR_PHY_DX7GCR0_DQSSEPDR_MASK 0x00001000U -/*RTT On Additive Latency*/ +/* +* RTT On Additive Latency +*/ #undef DDR_PHY_DX7GCR0_RTTOAL_DEFVAL #undef DDR_PHY_DX7GCR0_RTTOAL_SHIFT #undef DDR_PHY_DX7GCR0_RTTOAL_MASK -#define DDR_PHY_DX7GCR0_RTTOAL_DEFVAL 0x40200204 -#define DDR_PHY_DX7GCR0_RTTOAL_SHIFT 11 -#define DDR_PHY_DX7GCR0_RTTOAL_MASK 0x00000800U +#define DDR_PHY_DX7GCR0_RTTOAL_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_RTTOAL_SHIFT 11 +#define DDR_PHY_DX7GCR0_RTTOAL_MASK 0x00000800U -/*RTT Output Hold*/ +/* +* RTT Output Hold +*/ #undef DDR_PHY_DX7GCR0_RTTOH_DEFVAL #undef DDR_PHY_DX7GCR0_RTTOH_SHIFT #undef DDR_PHY_DX7GCR0_RTTOH_MASK -#define DDR_PHY_DX7GCR0_RTTOH_DEFVAL 0x40200204 -#define DDR_PHY_DX7GCR0_RTTOH_SHIFT 9 -#define DDR_PHY_DX7GCR0_RTTOH_MASK 0x00000600U +#define DDR_PHY_DX7GCR0_RTTOH_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_RTTOH_SHIFT 9 +#define DDR_PHY_DX7GCR0_RTTOH_MASK 0x00000600U -/*Configurable PDR Phase Shift*/ +/* +* Configurable PDR Phase Shift +*/ #undef DDR_PHY_DX7GCR0_CPDRSHFT_DEFVAL #undef DDR_PHY_DX7GCR0_CPDRSHFT_SHIFT #undef DDR_PHY_DX7GCR0_CPDRSHFT_MASK -#define DDR_PHY_DX7GCR0_CPDRSHFT_DEFVAL 0x40200204 -#define DDR_PHY_DX7GCR0_CPDRSHFT_SHIFT 7 -#define DDR_PHY_DX7GCR0_CPDRSHFT_MASK 0x00000180U +#define DDR_PHY_DX7GCR0_CPDRSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_CPDRSHFT_SHIFT 7 +#define DDR_PHY_DX7GCR0_CPDRSHFT_MASK 0x00000180U -/*DQSR Power Down*/ +/* +* DQSR Power Down +*/ #undef DDR_PHY_DX7GCR0_DQSRPD_DEFVAL #undef DDR_PHY_DX7GCR0_DQSRPD_SHIFT #undef DDR_PHY_DX7GCR0_DQSRPD_MASK -#define DDR_PHY_DX7GCR0_DQSRPD_DEFVAL 0x40200204 -#define DDR_PHY_DX7GCR0_DQSRPD_SHIFT 6 -#define DDR_PHY_DX7GCR0_DQSRPD_MASK 0x00000040U +#define DDR_PHY_DX7GCR0_DQSRPD_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_DQSRPD_SHIFT 6 +#define DDR_PHY_DX7GCR0_DQSRPD_MASK 0x00000040U -/*DQSG Power Down Receiver*/ +/* +* DQSG Power Down Receiver +*/ #undef DDR_PHY_DX7GCR0_DQSGPDR_DEFVAL #undef DDR_PHY_DX7GCR0_DQSGPDR_SHIFT #undef DDR_PHY_DX7GCR0_DQSGPDR_MASK -#define DDR_PHY_DX7GCR0_DQSGPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX7GCR0_DQSGPDR_SHIFT 5 -#define DDR_PHY_DX7GCR0_DQSGPDR_MASK 0x00000020U +#define DDR_PHY_DX7GCR0_DQSGPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_DQSGPDR_SHIFT 5 +#define DDR_PHY_DX7GCR0_DQSGPDR_MASK 0x00000020U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX7GCR0_RESERVED_4_DEFVAL #undef DDR_PHY_DX7GCR0_RESERVED_4_SHIFT #undef DDR_PHY_DX7GCR0_RESERVED_4_MASK -#define DDR_PHY_DX7GCR0_RESERVED_4_DEFVAL 0x40200204 -#define DDR_PHY_DX7GCR0_RESERVED_4_SHIFT 4 -#define DDR_PHY_DX7GCR0_RESERVED_4_MASK 0x00000010U +#define DDR_PHY_DX7GCR0_RESERVED_4_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_RESERVED_4_SHIFT 4 +#define DDR_PHY_DX7GCR0_RESERVED_4_MASK 0x00000010U -/*DQSG On-Die Termination*/ +/* +* DQSG On-Die Termination +*/ #undef DDR_PHY_DX7GCR0_DQSGODT_DEFVAL #undef DDR_PHY_DX7GCR0_DQSGODT_SHIFT #undef DDR_PHY_DX7GCR0_DQSGODT_MASK -#define DDR_PHY_DX7GCR0_DQSGODT_DEFVAL 0x40200204 -#define DDR_PHY_DX7GCR0_DQSGODT_SHIFT 3 -#define DDR_PHY_DX7GCR0_DQSGODT_MASK 0x00000008U +#define DDR_PHY_DX7GCR0_DQSGODT_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_DQSGODT_SHIFT 3 +#define DDR_PHY_DX7GCR0_DQSGODT_MASK 0x00000008U -/*DQSG Output Enable*/ +/* +* DQSG Output Enable +*/ #undef DDR_PHY_DX7GCR0_DQSGOE_DEFVAL #undef DDR_PHY_DX7GCR0_DQSGOE_SHIFT #undef DDR_PHY_DX7GCR0_DQSGOE_MASK -#define DDR_PHY_DX7GCR0_DQSGOE_DEFVAL 0x40200204 -#define DDR_PHY_DX7GCR0_DQSGOE_SHIFT 2 -#define DDR_PHY_DX7GCR0_DQSGOE_MASK 0x00000004U +#define DDR_PHY_DX7GCR0_DQSGOE_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_DQSGOE_SHIFT 2 +#define DDR_PHY_DX7GCR0_DQSGOE_MASK 0x00000004U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX7GCR0_RESERVED_1_0_DEFVAL #undef DDR_PHY_DX7GCR0_RESERVED_1_0_SHIFT #undef DDR_PHY_DX7GCR0_RESERVED_1_0_MASK -#define DDR_PHY_DX7GCR0_RESERVED_1_0_DEFVAL 0x40200204 -#define DDR_PHY_DX7GCR0_RESERVED_1_0_SHIFT 0 -#define DDR_PHY_DX7GCR0_RESERVED_1_0_MASK 0x00000003U +#define DDR_PHY_DX7GCR0_RESERVED_1_0_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_RESERVED_1_0_SHIFT 0 +#define DDR_PHY_DX7GCR0_RESERVED_1_0_MASK 0x00000003U -/*Enables the PDR mode for DQ[7:0]*/ +/* +* Enables the PDR mode for DQ[7:0] +*/ #undef DDR_PHY_DX7GCR1_DXPDRMODE_DEFVAL #undef DDR_PHY_DX7GCR1_DXPDRMODE_SHIFT #undef DDR_PHY_DX7GCR1_DXPDRMODE_MASK -#define DDR_PHY_DX7GCR1_DXPDRMODE_DEFVAL 0x00007FFF -#define DDR_PHY_DX7GCR1_DXPDRMODE_SHIFT 16 -#define DDR_PHY_DX7GCR1_DXPDRMODE_MASK 0xFFFF0000U +#define DDR_PHY_DX7GCR1_DXPDRMODE_DEFVAL 0x00007FFF +#define DDR_PHY_DX7GCR1_DXPDRMODE_SHIFT 16 +#define DDR_PHY_DX7GCR1_DXPDRMODE_MASK 0xFFFF0000U -/*Reserved. Returns zeroes on reads.*/ +/* +* Reserved. Returns zeroes on reads. +*/ #undef DDR_PHY_DX7GCR1_RESERVED_15_DEFVAL #undef DDR_PHY_DX7GCR1_RESERVED_15_SHIFT #undef DDR_PHY_DX7GCR1_RESERVED_15_MASK -#define DDR_PHY_DX7GCR1_RESERVED_15_DEFVAL 0x00007FFF -#define DDR_PHY_DX7GCR1_RESERVED_15_SHIFT 15 -#define DDR_PHY_DX7GCR1_RESERVED_15_MASK 0x00008000U +#define DDR_PHY_DX7GCR1_RESERVED_15_DEFVAL 0x00007FFF +#define DDR_PHY_DX7GCR1_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX7GCR1_RESERVED_15_MASK 0x00008000U -/*Select the delayed or non-delayed read data strobe #*/ +/* +* Select the delayed or non-delayed read data strobe # +*/ #undef DDR_PHY_DX7GCR1_QSNSEL_DEFVAL #undef DDR_PHY_DX7GCR1_QSNSEL_SHIFT #undef DDR_PHY_DX7GCR1_QSNSEL_MASK -#define DDR_PHY_DX7GCR1_QSNSEL_DEFVAL 0x00007FFF -#define DDR_PHY_DX7GCR1_QSNSEL_SHIFT 14 -#define DDR_PHY_DX7GCR1_QSNSEL_MASK 0x00004000U +#define DDR_PHY_DX7GCR1_QSNSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX7GCR1_QSNSEL_SHIFT 14 +#define DDR_PHY_DX7GCR1_QSNSEL_MASK 0x00004000U -/*Select the delayed or non-delayed read data strobe*/ +/* +* Select the delayed or non-delayed read data strobe +*/ #undef DDR_PHY_DX7GCR1_QSSEL_DEFVAL #undef DDR_PHY_DX7GCR1_QSSEL_SHIFT #undef DDR_PHY_DX7GCR1_QSSEL_MASK -#define DDR_PHY_DX7GCR1_QSSEL_DEFVAL 0x00007FFF -#define DDR_PHY_DX7GCR1_QSSEL_SHIFT 13 -#define DDR_PHY_DX7GCR1_QSSEL_MASK 0x00002000U +#define DDR_PHY_DX7GCR1_QSSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX7GCR1_QSSEL_SHIFT 13 +#define DDR_PHY_DX7GCR1_QSSEL_MASK 0x00002000U -/*Enables Read Data Strobe in a byte lane*/ +/* +* Enables Read Data Strobe in a byte lane +*/ #undef DDR_PHY_DX7GCR1_OEEN_DEFVAL #undef DDR_PHY_DX7GCR1_OEEN_SHIFT #undef DDR_PHY_DX7GCR1_OEEN_MASK -#define DDR_PHY_DX7GCR1_OEEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX7GCR1_OEEN_SHIFT 12 -#define DDR_PHY_DX7GCR1_OEEN_MASK 0x00001000U +#define DDR_PHY_DX7GCR1_OEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX7GCR1_OEEN_SHIFT 12 +#define DDR_PHY_DX7GCR1_OEEN_MASK 0x00001000U -/*Enables PDR in a byte lane*/ +/* +* Enables PDR in a byte lane +*/ #undef DDR_PHY_DX7GCR1_PDREN_DEFVAL #undef DDR_PHY_DX7GCR1_PDREN_SHIFT #undef DDR_PHY_DX7GCR1_PDREN_MASK -#define DDR_PHY_DX7GCR1_PDREN_DEFVAL 0x00007FFF -#define DDR_PHY_DX7GCR1_PDREN_SHIFT 11 -#define DDR_PHY_DX7GCR1_PDREN_MASK 0x00000800U +#define DDR_PHY_DX7GCR1_PDREN_DEFVAL 0x00007FFF +#define DDR_PHY_DX7GCR1_PDREN_SHIFT 11 +#define DDR_PHY_DX7GCR1_PDREN_MASK 0x00000800U -/*Enables ODT/TE in a byte lane*/ +/* +* Enables ODT/TE in a byte lane +*/ #undef DDR_PHY_DX7GCR1_TEEN_DEFVAL #undef DDR_PHY_DX7GCR1_TEEN_SHIFT #undef DDR_PHY_DX7GCR1_TEEN_MASK -#define DDR_PHY_DX7GCR1_TEEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX7GCR1_TEEN_SHIFT 10 -#define DDR_PHY_DX7GCR1_TEEN_MASK 0x00000400U +#define DDR_PHY_DX7GCR1_TEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX7GCR1_TEEN_SHIFT 10 +#define DDR_PHY_DX7GCR1_TEEN_MASK 0x00000400U -/*Enables Write Data strobe in a byte lane*/ +/* +* Enables Write Data strobe in a byte lane +*/ #undef DDR_PHY_DX7GCR1_DSEN_DEFVAL #undef DDR_PHY_DX7GCR1_DSEN_SHIFT #undef DDR_PHY_DX7GCR1_DSEN_MASK -#define DDR_PHY_DX7GCR1_DSEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX7GCR1_DSEN_SHIFT 9 -#define DDR_PHY_DX7GCR1_DSEN_MASK 0x00000200U +#define DDR_PHY_DX7GCR1_DSEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX7GCR1_DSEN_SHIFT 9 +#define DDR_PHY_DX7GCR1_DSEN_MASK 0x00000200U -/*Enables DM pin in a byte lane*/ +/* +* Enables DM pin in a byte lane +*/ #undef DDR_PHY_DX7GCR1_DMEN_DEFVAL #undef DDR_PHY_DX7GCR1_DMEN_SHIFT #undef DDR_PHY_DX7GCR1_DMEN_MASK -#define DDR_PHY_DX7GCR1_DMEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX7GCR1_DMEN_SHIFT 8 -#define DDR_PHY_DX7GCR1_DMEN_MASK 0x00000100U +#define DDR_PHY_DX7GCR1_DMEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX7GCR1_DMEN_SHIFT 8 +#define DDR_PHY_DX7GCR1_DMEN_MASK 0x00000100U -/*Enables DQ corresponding to each bit in a byte*/ +/* +* Enables DQ corresponding to each bit in a byte +*/ #undef DDR_PHY_DX7GCR1_DQEN_DEFVAL #undef DDR_PHY_DX7GCR1_DQEN_SHIFT #undef DDR_PHY_DX7GCR1_DQEN_MASK -#define DDR_PHY_DX7GCR1_DQEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX7GCR1_DQEN_SHIFT 0 -#define DDR_PHY_DX7GCR1_DQEN_MASK 0x000000FFU +#define DDR_PHY_DX7GCR1_DQEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX7GCR1_DQEN_SHIFT 0 +#define DDR_PHY_DX7GCR1_DQEN_MASK 0x000000FFU -/*Byte lane VREF IOM (Used only by D4MU IOs)*/ +/* +* Byte lane VREF IOM (Used only by D4MU IOs) +*/ #undef DDR_PHY_DX7GCR4_RESERVED_31_29_DEFVAL #undef DDR_PHY_DX7GCR4_RESERVED_31_29_SHIFT #undef DDR_PHY_DX7GCR4_RESERVED_31_29_MASK -#define DDR_PHY_DX7GCR4_RESERVED_31_29_DEFVAL 0x0E00003C -#define DDR_PHY_DX7GCR4_RESERVED_31_29_SHIFT 29 -#define DDR_PHY_DX7GCR4_RESERVED_31_29_MASK 0xE0000000U +#define DDR_PHY_DX7GCR4_RESERVED_31_29_DEFVAL 0x0E00003C +#define DDR_PHY_DX7GCR4_RESERVED_31_29_SHIFT 29 +#define DDR_PHY_DX7GCR4_RESERVED_31_29_MASK 0xE0000000U -/*Byte Lane VREF Pad Enable*/ +/* +* Byte Lane VREF Pad Enable +*/ #undef DDR_PHY_DX7GCR4_DXREFPEN_DEFVAL #undef DDR_PHY_DX7GCR4_DXREFPEN_SHIFT #undef DDR_PHY_DX7GCR4_DXREFPEN_MASK -#define DDR_PHY_DX7GCR4_DXREFPEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX7GCR4_DXREFPEN_SHIFT 28 -#define DDR_PHY_DX7GCR4_DXREFPEN_MASK 0x10000000U +#define DDR_PHY_DX7GCR4_DXREFPEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX7GCR4_DXREFPEN_SHIFT 28 +#define DDR_PHY_DX7GCR4_DXREFPEN_MASK 0x10000000U -/*Byte Lane Internal VREF Enable*/ +/* +* Byte Lane Internal VREF Enable +*/ #undef DDR_PHY_DX7GCR4_DXREFEEN_DEFVAL #undef DDR_PHY_DX7GCR4_DXREFEEN_SHIFT #undef DDR_PHY_DX7GCR4_DXREFEEN_MASK -#define DDR_PHY_DX7GCR4_DXREFEEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX7GCR4_DXREFEEN_SHIFT 26 -#define DDR_PHY_DX7GCR4_DXREFEEN_MASK 0x0C000000U +#define DDR_PHY_DX7GCR4_DXREFEEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX7GCR4_DXREFEEN_SHIFT 26 +#define DDR_PHY_DX7GCR4_DXREFEEN_MASK 0x0C000000U -/*Byte Lane Single-End VREF Enable*/ +/* +* Byte Lane Single-End VREF Enable +*/ #undef DDR_PHY_DX7GCR4_DXREFSEN_DEFVAL #undef DDR_PHY_DX7GCR4_DXREFSEN_SHIFT #undef DDR_PHY_DX7GCR4_DXREFSEN_MASK -#define DDR_PHY_DX7GCR4_DXREFSEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX7GCR4_DXREFSEN_SHIFT 25 -#define DDR_PHY_DX7GCR4_DXREFSEN_MASK 0x02000000U +#define DDR_PHY_DX7GCR4_DXREFSEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX7GCR4_DXREFSEN_SHIFT 25 +#define DDR_PHY_DX7GCR4_DXREFSEN_MASK 0x02000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX7GCR4_RESERVED_24_DEFVAL #undef DDR_PHY_DX7GCR4_RESERVED_24_SHIFT #undef DDR_PHY_DX7GCR4_RESERVED_24_MASK -#define DDR_PHY_DX7GCR4_RESERVED_24_DEFVAL 0x0E00003C -#define DDR_PHY_DX7GCR4_RESERVED_24_SHIFT 24 -#define DDR_PHY_DX7GCR4_RESERVED_24_MASK 0x01000000U +#define DDR_PHY_DX7GCR4_RESERVED_24_DEFVAL 0x0E00003C +#define DDR_PHY_DX7GCR4_RESERVED_24_SHIFT 24 +#define DDR_PHY_DX7GCR4_RESERVED_24_MASK 0x01000000U -/*External VREF generator REFSEL range select*/ +/* +* External VREF generator REFSEL range select +*/ #undef DDR_PHY_DX7GCR4_DXREFESELRANGE_DEFVAL #undef DDR_PHY_DX7GCR4_DXREFESELRANGE_SHIFT #undef DDR_PHY_DX7GCR4_DXREFESELRANGE_MASK -#define DDR_PHY_DX7GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C -#define DDR_PHY_DX7GCR4_DXREFESELRANGE_SHIFT 23 -#define DDR_PHY_DX7GCR4_DXREFESELRANGE_MASK 0x00800000U +#define DDR_PHY_DX7GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX7GCR4_DXREFESELRANGE_SHIFT 23 +#define DDR_PHY_DX7GCR4_DXREFESELRANGE_MASK 0x00800000U -/*Byte Lane External VREF Select*/ +/* +* Byte Lane External VREF Select +*/ #undef DDR_PHY_DX7GCR4_DXREFESEL_DEFVAL #undef DDR_PHY_DX7GCR4_DXREFESEL_SHIFT #undef DDR_PHY_DX7GCR4_DXREFESEL_MASK -#define DDR_PHY_DX7GCR4_DXREFESEL_DEFVAL 0x0E00003C -#define DDR_PHY_DX7GCR4_DXREFESEL_SHIFT 16 -#define DDR_PHY_DX7GCR4_DXREFESEL_MASK 0x007F0000U +#define DDR_PHY_DX7GCR4_DXREFESEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX7GCR4_DXREFESEL_SHIFT 16 +#define DDR_PHY_DX7GCR4_DXREFESEL_MASK 0x007F0000U -/*Single ended VREF generator REFSEL range select*/ +/* +* Single ended VREF generator REFSEL range select +*/ #undef DDR_PHY_DX7GCR4_DXREFSSELRANGE_DEFVAL #undef DDR_PHY_DX7GCR4_DXREFSSELRANGE_SHIFT #undef DDR_PHY_DX7GCR4_DXREFSSELRANGE_MASK -#define DDR_PHY_DX7GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C -#define DDR_PHY_DX7GCR4_DXREFSSELRANGE_SHIFT 15 -#define DDR_PHY_DX7GCR4_DXREFSSELRANGE_MASK 0x00008000U +#define DDR_PHY_DX7GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX7GCR4_DXREFSSELRANGE_SHIFT 15 +#define DDR_PHY_DX7GCR4_DXREFSSELRANGE_MASK 0x00008000U -/*Byte Lane Single-End VREF Select*/ +/* +* Byte Lane Single-End VREF Select +*/ #undef DDR_PHY_DX7GCR4_DXREFSSEL_DEFVAL #undef DDR_PHY_DX7GCR4_DXREFSSEL_SHIFT #undef DDR_PHY_DX7GCR4_DXREFSSEL_MASK -#define DDR_PHY_DX7GCR4_DXREFSSEL_DEFVAL 0x0E00003C -#define DDR_PHY_DX7GCR4_DXREFSSEL_SHIFT 8 -#define DDR_PHY_DX7GCR4_DXREFSSEL_MASK 0x00007F00U +#define DDR_PHY_DX7GCR4_DXREFSSEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX7GCR4_DXREFSSEL_SHIFT 8 +#define DDR_PHY_DX7GCR4_DXREFSSEL_MASK 0x00007F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX7GCR4_RESERVED_7_6_DEFVAL #undef DDR_PHY_DX7GCR4_RESERVED_7_6_SHIFT #undef DDR_PHY_DX7GCR4_RESERVED_7_6_MASK -#define DDR_PHY_DX7GCR4_RESERVED_7_6_DEFVAL 0x0E00003C -#define DDR_PHY_DX7GCR4_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_DX7GCR4_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_DX7GCR4_RESERVED_7_6_DEFVAL 0x0E00003C +#define DDR_PHY_DX7GCR4_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX7GCR4_RESERVED_7_6_MASK 0x000000C0U -/*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/ +/* +* VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. +*/ #undef DDR_PHY_DX7GCR4_DXREFIEN_DEFVAL #undef DDR_PHY_DX7GCR4_DXREFIEN_SHIFT #undef DDR_PHY_DX7GCR4_DXREFIEN_MASK -#define DDR_PHY_DX7GCR4_DXREFIEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX7GCR4_DXREFIEN_SHIFT 2 -#define DDR_PHY_DX7GCR4_DXREFIEN_MASK 0x0000003CU +#define DDR_PHY_DX7GCR4_DXREFIEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX7GCR4_DXREFIEN_SHIFT 2 +#define DDR_PHY_DX7GCR4_DXREFIEN_MASK 0x0000003CU -/*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/ +/* +* VRMON control for DQ IO (Single Ended) buffers of a byte lane. +*/ #undef DDR_PHY_DX7GCR4_DXREFIMON_DEFVAL #undef DDR_PHY_DX7GCR4_DXREFIMON_SHIFT #undef DDR_PHY_DX7GCR4_DXREFIMON_MASK -#define DDR_PHY_DX7GCR4_DXREFIMON_DEFVAL 0x0E00003C -#define DDR_PHY_DX7GCR4_DXREFIMON_SHIFT 0 -#define DDR_PHY_DX7GCR4_DXREFIMON_MASK 0x00000003U +#define DDR_PHY_DX7GCR4_DXREFIMON_DEFVAL 0x0E00003C +#define DDR_PHY_DX7GCR4_DXREFIMON_SHIFT 0 +#define DDR_PHY_DX7GCR4_DXREFIMON_MASK 0x00000003U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX7GCR5_RESERVED_31_DEFVAL #undef DDR_PHY_DX7GCR5_RESERVED_31_SHIFT #undef DDR_PHY_DX7GCR5_RESERVED_31_MASK -#define DDR_PHY_DX7GCR5_RESERVED_31_DEFVAL 0x09090909 -#define DDR_PHY_DX7GCR5_RESERVED_31_SHIFT 31 -#define DDR_PHY_DX7GCR5_RESERVED_31_MASK 0x80000000U +#define DDR_PHY_DX7GCR5_RESERVED_31_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR5_RESERVED_31_SHIFT 31 +#define DDR_PHY_DX7GCR5_RESERVED_31_MASK 0x80000000U -/*Byte Lane internal VREF Select for Rank 3*/ +/* +* Byte Lane internal VREF Select for Rank 3 +*/ #undef DDR_PHY_DX7GCR5_DXREFISELR3_DEFVAL #undef DDR_PHY_DX7GCR5_DXREFISELR3_SHIFT #undef DDR_PHY_DX7GCR5_DXREFISELR3_MASK -#define DDR_PHY_DX7GCR5_DXREFISELR3_DEFVAL 0x09090909 -#define DDR_PHY_DX7GCR5_DXREFISELR3_SHIFT 24 -#define DDR_PHY_DX7GCR5_DXREFISELR3_MASK 0x7F000000U +#define DDR_PHY_DX7GCR5_DXREFISELR3_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR5_DXREFISELR3_SHIFT 24 +#define DDR_PHY_DX7GCR5_DXREFISELR3_MASK 0x7F000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX7GCR5_RESERVED_23_DEFVAL #undef DDR_PHY_DX7GCR5_RESERVED_23_SHIFT #undef DDR_PHY_DX7GCR5_RESERVED_23_MASK -#define DDR_PHY_DX7GCR5_RESERVED_23_DEFVAL 0x09090909 -#define DDR_PHY_DX7GCR5_RESERVED_23_SHIFT 23 -#define DDR_PHY_DX7GCR5_RESERVED_23_MASK 0x00800000U +#define DDR_PHY_DX7GCR5_RESERVED_23_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR5_RESERVED_23_SHIFT 23 +#define DDR_PHY_DX7GCR5_RESERVED_23_MASK 0x00800000U -/*Byte Lane internal VREF Select for Rank 2*/ +/* +* Byte Lane internal VREF Select for Rank 2 +*/ #undef DDR_PHY_DX7GCR5_DXREFISELR2_DEFVAL #undef DDR_PHY_DX7GCR5_DXREFISELR2_SHIFT #undef DDR_PHY_DX7GCR5_DXREFISELR2_MASK -#define DDR_PHY_DX7GCR5_DXREFISELR2_DEFVAL 0x09090909 -#define DDR_PHY_DX7GCR5_DXREFISELR2_SHIFT 16 -#define DDR_PHY_DX7GCR5_DXREFISELR2_MASK 0x007F0000U +#define DDR_PHY_DX7GCR5_DXREFISELR2_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR5_DXREFISELR2_SHIFT 16 +#define DDR_PHY_DX7GCR5_DXREFISELR2_MASK 0x007F0000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX7GCR5_RESERVED_15_DEFVAL #undef DDR_PHY_DX7GCR5_RESERVED_15_SHIFT #undef DDR_PHY_DX7GCR5_RESERVED_15_MASK -#define DDR_PHY_DX7GCR5_RESERVED_15_DEFVAL 0x09090909 -#define DDR_PHY_DX7GCR5_RESERVED_15_SHIFT 15 -#define DDR_PHY_DX7GCR5_RESERVED_15_MASK 0x00008000U +#define DDR_PHY_DX7GCR5_RESERVED_15_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR5_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX7GCR5_RESERVED_15_MASK 0x00008000U -/*Byte Lane internal VREF Select for Rank 1*/ +/* +* Byte Lane internal VREF Select for Rank 1 +*/ #undef DDR_PHY_DX7GCR5_DXREFISELR1_DEFVAL #undef DDR_PHY_DX7GCR5_DXREFISELR1_SHIFT #undef DDR_PHY_DX7GCR5_DXREFISELR1_MASK -#define DDR_PHY_DX7GCR5_DXREFISELR1_DEFVAL 0x09090909 -#define DDR_PHY_DX7GCR5_DXREFISELR1_SHIFT 8 -#define DDR_PHY_DX7GCR5_DXREFISELR1_MASK 0x00007F00U +#define DDR_PHY_DX7GCR5_DXREFISELR1_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR5_DXREFISELR1_SHIFT 8 +#define DDR_PHY_DX7GCR5_DXREFISELR1_MASK 0x00007F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX7GCR5_RESERVED_7_DEFVAL #undef DDR_PHY_DX7GCR5_RESERVED_7_SHIFT #undef DDR_PHY_DX7GCR5_RESERVED_7_MASK -#define DDR_PHY_DX7GCR5_RESERVED_7_DEFVAL 0x09090909 -#define DDR_PHY_DX7GCR5_RESERVED_7_SHIFT 7 -#define DDR_PHY_DX7GCR5_RESERVED_7_MASK 0x00000080U +#define DDR_PHY_DX7GCR5_RESERVED_7_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR5_RESERVED_7_SHIFT 7 +#define DDR_PHY_DX7GCR5_RESERVED_7_MASK 0x00000080U -/*Byte Lane internal VREF Select for Rank 0*/ +/* +* Byte Lane internal VREF Select for Rank 0 +*/ #undef DDR_PHY_DX7GCR5_DXREFISELR0_DEFVAL #undef DDR_PHY_DX7GCR5_DXREFISELR0_SHIFT #undef DDR_PHY_DX7GCR5_DXREFISELR0_MASK -#define DDR_PHY_DX7GCR5_DXREFISELR0_DEFVAL 0x09090909 -#define DDR_PHY_DX7GCR5_DXREFISELR0_SHIFT 0 -#define DDR_PHY_DX7GCR5_DXREFISELR0_MASK 0x0000007FU +#define DDR_PHY_DX7GCR5_DXREFISELR0_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR5_DXREFISELR0_SHIFT 0 +#define DDR_PHY_DX7GCR5_DXREFISELR0_MASK 0x0000007FU -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX7GCR6_RESERVED_31_30_DEFVAL #undef DDR_PHY_DX7GCR6_RESERVED_31_30_SHIFT #undef DDR_PHY_DX7GCR6_RESERVED_31_30_MASK -#define DDR_PHY_DX7GCR6_RESERVED_31_30_DEFVAL 0x09090909 -#define DDR_PHY_DX7GCR6_RESERVED_31_30_SHIFT 30 -#define DDR_PHY_DX7GCR6_RESERVED_31_30_MASK 0xC0000000U +#define DDR_PHY_DX7GCR6_RESERVED_31_30_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR6_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX7GCR6_RESERVED_31_30_MASK 0xC0000000U -/*DRAM DQ VREF Select for Rank3*/ +/* +* DRAM DQ VREF Select for Rank3 +*/ #undef DDR_PHY_DX7GCR6_DXDQVREFR3_DEFVAL #undef DDR_PHY_DX7GCR6_DXDQVREFR3_SHIFT #undef DDR_PHY_DX7GCR6_DXDQVREFR3_MASK -#define DDR_PHY_DX7GCR6_DXDQVREFR3_DEFVAL 0x09090909 -#define DDR_PHY_DX7GCR6_DXDQVREFR3_SHIFT 24 -#define DDR_PHY_DX7GCR6_DXDQVREFR3_MASK 0x3F000000U +#define DDR_PHY_DX7GCR6_DXDQVREFR3_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR6_DXDQVREFR3_SHIFT 24 +#define DDR_PHY_DX7GCR6_DXDQVREFR3_MASK 0x3F000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX7GCR6_RESERVED_23_22_DEFVAL #undef DDR_PHY_DX7GCR6_RESERVED_23_22_SHIFT #undef DDR_PHY_DX7GCR6_RESERVED_23_22_MASK -#define DDR_PHY_DX7GCR6_RESERVED_23_22_DEFVAL 0x09090909 -#define DDR_PHY_DX7GCR6_RESERVED_23_22_SHIFT 22 -#define DDR_PHY_DX7GCR6_RESERVED_23_22_MASK 0x00C00000U +#define DDR_PHY_DX7GCR6_RESERVED_23_22_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR6_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX7GCR6_RESERVED_23_22_MASK 0x00C00000U -/*DRAM DQ VREF Select for Rank2*/ +/* +* DRAM DQ VREF Select for Rank2 +*/ #undef DDR_PHY_DX7GCR6_DXDQVREFR2_DEFVAL #undef DDR_PHY_DX7GCR6_DXDQVREFR2_SHIFT #undef DDR_PHY_DX7GCR6_DXDQVREFR2_MASK -#define DDR_PHY_DX7GCR6_DXDQVREFR2_DEFVAL 0x09090909 -#define DDR_PHY_DX7GCR6_DXDQVREFR2_SHIFT 16 -#define DDR_PHY_DX7GCR6_DXDQVREFR2_MASK 0x003F0000U +#define DDR_PHY_DX7GCR6_DXDQVREFR2_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR6_DXDQVREFR2_SHIFT 16 +#define DDR_PHY_DX7GCR6_DXDQVREFR2_MASK 0x003F0000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX7GCR6_RESERVED_15_14_DEFVAL #undef DDR_PHY_DX7GCR6_RESERVED_15_14_SHIFT #undef DDR_PHY_DX7GCR6_RESERVED_15_14_MASK -#define DDR_PHY_DX7GCR6_RESERVED_15_14_DEFVAL 0x09090909 -#define DDR_PHY_DX7GCR6_RESERVED_15_14_SHIFT 14 -#define DDR_PHY_DX7GCR6_RESERVED_15_14_MASK 0x0000C000U +#define DDR_PHY_DX7GCR6_RESERVED_15_14_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR6_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_DX7GCR6_RESERVED_15_14_MASK 0x0000C000U -/*DRAM DQ VREF Select for Rank1*/ +/* +* DRAM DQ VREF Select for Rank1 +*/ #undef DDR_PHY_DX7GCR6_DXDQVREFR1_DEFVAL #undef DDR_PHY_DX7GCR6_DXDQVREFR1_SHIFT #undef DDR_PHY_DX7GCR6_DXDQVREFR1_MASK -#define DDR_PHY_DX7GCR6_DXDQVREFR1_DEFVAL 0x09090909 -#define DDR_PHY_DX7GCR6_DXDQVREFR1_SHIFT 8 -#define DDR_PHY_DX7GCR6_DXDQVREFR1_MASK 0x00003F00U +#define DDR_PHY_DX7GCR6_DXDQVREFR1_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR6_DXDQVREFR1_SHIFT 8 +#define DDR_PHY_DX7GCR6_DXDQVREFR1_MASK 0x00003F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX7GCR6_RESERVED_7_6_DEFVAL #undef DDR_PHY_DX7GCR6_RESERVED_7_6_SHIFT #undef DDR_PHY_DX7GCR6_RESERVED_7_6_MASK -#define DDR_PHY_DX7GCR6_RESERVED_7_6_DEFVAL 0x09090909 -#define DDR_PHY_DX7GCR6_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_DX7GCR6_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_DX7GCR6_RESERVED_7_6_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR6_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX7GCR6_RESERVED_7_6_MASK 0x000000C0U -/*DRAM DQ VREF Select for Rank0*/ +/* +* DRAM DQ VREF Select for Rank0 +*/ #undef DDR_PHY_DX7GCR6_DXDQVREFR0_DEFVAL #undef DDR_PHY_DX7GCR6_DXDQVREFR0_SHIFT #undef DDR_PHY_DX7GCR6_DXDQVREFR0_MASK -#define DDR_PHY_DX7GCR6_DXDQVREFR0_DEFVAL 0x09090909 -#define DDR_PHY_DX7GCR6_DXDQVREFR0_SHIFT 0 -#define DDR_PHY_DX7GCR6_DXDQVREFR0_MASK 0x0000003FU +#define DDR_PHY_DX7GCR6_DXDQVREFR0_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR6_DXDQVREFR0_SHIFT 0 +#define DDR_PHY_DX7GCR6_DXDQVREFR0_MASK 0x0000003FU -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX7LCDLR2_RESERVED_31_25_DEFVAL -#undef DDR_PHY_DX7LCDLR2_RESERVED_31_25_SHIFT -#undef DDR_PHY_DX7LCDLR2_RESERVED_31_25_MASK -#define DDR_PHY_DX7LCDLR2_RESERVED_31_25_DEFVAL 0x00000000 -#define DDR_PHY_DX7LCDLR2_RESERVED_31_25_SHIFT 25 -#define DDR_PHY_DX7LCDLR2_RESERVED_31_25_MASK 0xFE000000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX7LCDLR2_RESERVED_24_16_DEFVAL -#undef DDR_PHY_DX7LCDLR2_RESERVED_24_16_SHIFT -#undef DDR_PHY_DX7LCDLR2_RESERVED_24_16_MASK -#define DDR_PHY_DX7LCDLR2_RESERVED_24_16_DEFVAL 0x00000000 -#define DDR_PHY_DX7LCDLR2_RESERVED_24_16_SHIFT 16 -#define DDR_PHY_DX7LCDLR2_RESERVED_24_16_MASK 0x01FF0000U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX7LCDLR2_RESERVED_15_9_DEFVAL -#undef DDR_PHY_DX7LCDLR2_RESERVED_15_9_SHIFT -#undef DDR_PHY_DX7LCDLR2_RESERVED_15_9_MASK -#define DDR_PHY_DX7LCDLR2_RESERVED_15_9_DEFVAL 0x00000000 -#define DDR_PHY_DX7LCDLR2_RESERVED_15_9_SHIFT 9 -#define DDR_PHY_DX7LCDLR2_RESERVED_15_9_MASK 0x0000FE00U - -/*Read DQS Gating Delay*/ -#undef DDR_PHY_DX7LCDLR2_DQSGD_DEFVAL -#undef DDR_PHY_DX7LCDLR2_DQSGD_SHIFT -#undef DDR_PHY_DX7LCDLR2_DQSGD_MASK -#define DDR_PHY_DX7LCDLR2_DQSGD_DEFVAL 0x00000000 -#define DDR_PHY_DX7LCDLR2_DQSGD_SHIFT 0 -#define DDR_PHY_DX7LCDLR2_DQSGD_MASK 0x000001FFU - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX7GTR0_RESERVED_31_24_DEFVAL -#undef DDR_PHY_DX7GTR0_RESERVED_31_24_SHIFT -#undef DDR_PHY_DX7GTR0_RESERVED_31_24_MASK -#define DDR_PHY_DX7GTR0_RESERVED_31_24_DEFVAL 0x00020000 -#define DDR_PHY_DX7GTR0_RESERVED_31_24_SHIFT 27 -#define DDR_PHY_DX7GTR0_RESERVED_31_24_MASK 0xF8000000U - -/*DQ Write Path Latency Pipeline*/ -#undef DDR_PHY_DX7GTR0_WDQSL_DEFVAL -#undef DDR_PHY_DX7GTR0_WDQSL_SHIFT -#undef DDR_PHY_DX7GTR0_WDQSL_MASK -#define DDR_PHY_DX7GTR0_WDQSL_DEFVAL 0x00020000 -#define DDR_PHY_DX7GTR0_WDQSL_SHIFT 24 -#define DDR_PHY_DX7GTR0_WDQSL_MASK 0x07000000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX7GTR0_RESERVED_23_20_DEFVAL -#undef DDR_PHY_DX7GTR0_RESERVED_23_20_SHIFT -#undef DDR_PHY_DX7GTR0_RESERVED_23_20_MASK -#define DDR_PHY_DX7GTR0_RESERVED_23_20_DEFVAL 0x00020000 -#define DDR_PHY_DX7GTR0_RESERVED_23_20_SHIFT 20 -#define DDR_PHY_DX7GTR0_RESERVED_23_20_MASK 0x00F00000U - -/*Write Leveling System Latency*/ -#undef DDR_PHY_DX7GTR0_WLSL_DEFVAL -#undef DDR_PHY_DX7GTR0_WLSL_SHIFT -#undef DDR_PHY_DX7GTR0_WLSL_MASK -#define DDR_PHY_DX7GTR0_WLSL_DEFVAL 0x00020000 -#define DDR_PHY_DX7GTR0_WLSL_SHIFT 16 -#define DDR_PHY_DX7GTR0_WLSL_MASK 0x000F0000U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX7GTR0_RESERVED_15_13_DEFVAL -#undef DDR_PHY_DX7GTR0_RESERVED_15_13_SHIFT -#undef DDR_PHY_DX7GTR0_RESERVED_15_13_MASK -#define DDR_PHY_DX7GTR0_RESERVED_15_13_DEFVAL 0x00020000 -#define DDR_PHY_DX7GTR0_RESERVED_15_13_SHIFT 13 -#define DDR_PHY_DX7GTR0_RESERVED_15_13_MASK 0x0000E000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX7GTR0_RESERVED_12_8_DEFVAL -#undef DDR_PHY_DX7GTR0_RESERVED_12_8_SHIFT -#undef DDR_PHY_DX7GTR0_RESERVED_12_8_MASK -#define DDR_PHY_DX7GTR0_RESERVED_12_8_DEFVAL 0x00020000 -#define DDR_PHY_DX7GTR0_RESERVED_12_8_SHIFT 8 -#define DDR_PHY_DX7GTR0_RESERVED_12_8_MASK 0x00001F00U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX7GTR0_RESERVED_7_5_DEFVAL -#undef DDR_PHY_DX7GTR0_RESERVED_7_5_SHIFT -#undef DDR_PHY_DX7GTR0_RESERVED_7_5_MASK -#define DDR_PHY_DX7GTR0_RESERVED_7_5_DEFVAL 0x00020000 -#define DDR_PHY_DX7GTR0_RESERVED_7_5_SHIFT 5 -#define DDR_PHY_DX7GTR0_RESERVED_7_5_MASK 0x000000E0U - -/*DQS Gating System Latency*/ -#undef DDR_PHY_DX7GTR0_DGSL_DEFVAL -#undef DDR_PHY_DX7GTR0_DGSL_SHIFT -#undef DDR_PHY_DX7GTR0_DGSL_MASK -#define DDR_PHY_DX7GTR0_DGSL_DEFVAL 0x00020000 -#define DDR_PHY_DX7GTR0_DGSL_SHIFT 0 -#define DDR_PHY_DX7GTR0_DGSL_MASK 0x0000001FU - -/*Calibration Bypass*/ +/* +* Calibration Bypass +*/ #undef DDR_PHY_DX8GCR0_CALBYP_DEFVAL #undef DDR_PHY_DX8GCR0_CALBYP_SHIFT #undef DDR_PHY_DX8GCR0_CALBYP_MASK -#define DDR_PHY_DX8GCR0_CALBYP_DEFVAL 0x40200204 -#define DDR_PHY_DX8GCR0_CALBYP_SHIFT 31 -#define DDR_PHY_DX8GCR0_CALBYP_MASK 0x80000000U +#define DDR_PHY_DX8GCR0_CALBYP_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_CALBYP_SHIFT 31 +#define DDR_PHY_DX8GCR0_CALBYP_MASK 0x80000000U -/*Master Delay Line Enable*/ +/* +* Master Delay Line Enable +*/ #undef DDR_PHY_DX8GCR0_MDLEN_DEFVAL #undef DDR_PHY_DX8GCR0_MDLEN_SHIFT #undef DDR_PHY_DX8GCR0_MDLEN_MASK -#define DDR_PHY_DX8GCR0_MDLEN_DEFVAL 0x40200204 -#define DDR_PHY_DX8GCR0_MDLEN_SHIFT 30 -#define DDR_PHY_DX8GCR0_MDLEN_MASK 0x40000000U +#define DDR_PHY_DX8GCR0_MDLEN_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_MDLEN_SHIFT 30 +#define DDR_PHY_DX8GCR0_MDLEN_MASK 0x40000000U -/*Configurable ODT(TE) Phase Shift*/ +/* +* Configurable ODT(TE) Phase Shift +*/ #undef DDR_PHY_DX8GCR0_CODTSHFT_DEFVAL #undef DDR_PHY_DX8GCR0_CODTSHFT_SHIFT #undef DDR_PHY_DX8GCR0_CODTSHFT_MASK -#define DDR_PHY_DX8GCR0_CODTSHFT_DEFVAL 0x40200204 -#define DDR_PHY_DX8GCR0_CODTSHFT_SHIFT 28 -#define DDR_PHY_DX8GCR0_CODTSHFT_MASK 0x30000000U +#define DDR_PHY_DX8GCR0_CODTSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_CODTSHFT_SHIFT 28 +#define DDR_PHY_DX8GCR0_CODTSHFT_MASK 0x30000000U -/*DQS Duty Cycle Correction*/ +/* +* DQS Duty Cycle Correction +*/ #undef DDR_PHY_DX8GCR0_DQSDCC_DEFVAL #undef DDR_PHY_DX8GCR0_DQSDCC_SHIFT #undef DDR_PHY_DX8GCR0_DQSDCC_MASK -#define DDR_PHY_DX8GCR0_DQSDCC_DEFVAL 0x40200204 -#define DDR_PHY_DX8GCR0_DQSDCC_SHIFT 24 -#define DDR_PHY_DX8GCR0_DQSDCC_MASK 0x0F000000U +#define DDR_PHY_DX8GCR0_DQSDCC_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_DQSDCC_SHIFT 24 +#define DDR_PHY_DX8GCR0_DQSDCC_MASK 0x0F000000U -/*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/ +/* +* Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY +*/ #undef DDR_PHY_DX8GCR0_RDDLY_DEFVAL #undef DDR_PHY_DX8GCR0_RDDLY_SHIFT #undef DDR_PHY_DX8GCR0_RDDLY_MASK -#define DDR_PHY_DX8GCR0_RDDLY_DEFVAL 0x40200204 -#define DDR_PHY_DX8GCR0_RDDLY_SHIFT 20 -#define DDR_PHY_DX8GCR0_RDDLY_MASK 0x00F00000U +#define DDR_PHY_DX8GCR0_RDDLY_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_RDDLY_SHIFT 20 +#define DDR_PHY_DX8GCR0_RDDLY_MASK 0x00F00000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8GCR0_RESERVED_19_14_DEFVAL #undef DDR_PHY_DX8GCR0_RESERVED_19_14_SHIFT #undef DDR_PHY_DX8GCR0_RESERVED_19_14_MASK -#define DDR_PHY_DX8GCR0_RESERVED_19_14_DEFVAL 0x40200204 -#define DDR_PHY_DX8GCR0_RESERVED_19_14_SHIFT 14 -#define DDR_PHY_DX8GCR0_RESERVED_19_14_MASK 0x000FC000U +#define DDR_PHY_DX8GCR0_RESERVED_19_14_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_RESERVED_19_14_SHIFT 14 +#define DDR_PHY_DX8GCR0_RESERVED_19_14_MASK 0x000FC000U -/*DQSNSE Power Down Receiver*/ +/* +* DQSNSE Power Down Receiver +*/ #undef DDR_PHY_DX8GCR0_DQSNSEPDR_DEFVAL #undef DDR_PHY_DX8GCR0_DQSNSEPDR_SHIFT #undef DDR_PHY_DX8GCR0_DQSNSEPDR_MASK -#define DDR_PHY_DX8GCR0_DQSNSEPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX8GCR0_DQSNSEPDR_SHIFT 13 -#define DDR_PHY_DX8GCR0_DQSNSEPDR_MASK 0x00002000U +#define DDR_PHY_DX8GCR0_DQSNSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_DQSNSEPDR_SHIFT 13 +#define DDR_PHY_DX8GCR0_DQSNSEPDR_MASK 0x00002000U -/*DQSSE Power Down Receiver*/ +/* +* DQSSE Power Down Receiver +*/ #undef DDR_PHY_DX8GCR0_DQSSEPDR_DEFVAL #undef DDR_PHY_DX8GCR0_DQSSEPDR_SHIFT #undef DDR_PHY_DX8GCR0_DQSSEPDR_MASK -#define DDR_PHY_DX8GCR0_DQSSEPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX8GCR0_DQSSEPDR_SHIFT 12 -#define DDR_PHY_DX8GCR0_DQSSEPDR_MASK 0x00001000U +#define DDR_PHY_DX8GCR0_DQSSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_DQSSEPDR_SHIFT 12 +#define DDR_PHY_DX8GCR0_DQSSEPDR_MASK 0x00001000U -/*RTT On Additive Latency*/ +/* +* RTT On Additive Latency +*/ #undef DDR_PHY_DX8GCR0_RTTOAL_DEFVAL #undef DDR_PHY_DX8GCR0_RTTOAL_SHIFT #undef DDR_PHY_DX8GCR0_RTTOAL_MASK -#define DDR_PHY_DX8GCR0_RTTOAL_DEFVAL 0x40200204 -#define DDR_PHY_DX8GCR0_RTTOAL_SHIFT 11 -#define DDR_PHY_DX8GCR0_RTTOAL_MASK 0x00000800U +#define DDR_PHY_DX8GCR0_RTTOAL_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_RTTOAL_SHIFT 11 +#define DDR_PHY_DX8GCR0_RTTOAL_MASK 0x00000800U -/*RTT Output Hold*/ +/* +* RTT Output Hold +*/ #undef DDR_PHY_DX8GCR0_RTTOH_DEFVAL #undef DDR_PHY_DX8GCR0_RTTOH_SHIFT #undef DDR_PHY_DX8GCR0_RTTOH_MASK -#define DDR_PHY_DX8GCR0_RTTOH_DEFVAL 0x40200204 -#define DDR_PHY_DX8GCR0_RTTOH_SHIFT 9 -#define DDR_PHY_DX8GCR0_RTTOH_MASK 0x00000600U +#define DDR_PHY_DX8GCR0_RTTOH_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_RTTOH_SHIFT 9 +#define DDR_PHY_DX8GCR0_RTTOH_MASK 0x00000600U -/*Configurable PDR Phase Shift*/ +/* +* Configurable PDR Phase Shift +*/ #undef DDR_PHY_DX8GCR0_CPDRSHFT_DEFVAL #undef DDR_PHY_DX8GCR0_CPDRSHFT_SHIFT #undef DDR_PHY_DX8GCR0_CPDRSHFT_MASK -#define DDR_PHY_DX8GCR0_CPDRSHFT_DEFVAL 0x40200204 -#define DDR_PHY_DX8GCR0_CPDRSHFT_SHIFT 7 -#define DDR_PHY_DX8GCR0_CPDRSHFT_MASK 0x00000180U +#define DDR_PHY_DX8GCR0_CPDRSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_CPDRSHFT_SHIFT 7 +#define DDR_PHY_DX8GCR0_CPDRSHFT_MASK 0x00000180U -/*DQSR Power Down*/ +/* +* DQSR Power Down +*/ #undef DDR_PHY_DX8GCR0_DQSRPD_DEFVAL #undef DDR_PHY_DX8GCR0_DQSRPD_SHIFT #undef DDR_PHY_DX8GCR0_DQSRPD_MASK -#define DDR_PHY_DX8GCR0_DQSRPD_DEFVAL 0x40200204 -#define DDR_PHY_DX8GCR0_DQSRPD_SHIFT 6 -#define DDR_PHY_DX8GCR0_DQSRPD_MASK 0x00000040U +#define DDR_PHY_DX8GCR0_DQSRPD_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_DQSRPD_SHIFT 6 +#define DDR_PHY_DX8GCR0_DQSRPD_MASK 0x00000040U -/*DQSG Power Down Receiver*/ +/* +* DQSG Power Down Receiver +*/ #undef DDR_PHY_DX8GCR0_DQSGPDR_DEFVAL #undef DDR_PHY_DX8GCR0_DQSGPDR_SHIFT #undef DDR_PHY_DX8GCR0_DQSGPDR_MASK -#define DDR_PHY_DX8GCR0_DQSGPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX8GCR0_DQSGPDR_SHIFT 5 -#define DDR_PHY_DX8GCR0_DQSGPDR_MASK 0x00000020U +#define DDR_PHY_DX8GCR0_DQSGPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_DQSGPDR_SHIFT 5 +#define DDR_PHY_DX8GCR0_DQSGPDR_MASK 0x00000020U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8GCR0_RESERVED_4_DEFVAL #undef DDR_PHY_DX8GCR0_RESERVED_4_SHIFT #undef DDR_PHY_DX8GCR0_RESERVED_4_MASK -#define DDR_PHY_DX8GCR0_RESERVED_4_DEFVAL 0x40200204 -#define DDR_PHY_DX8GCR0_RESERVED_4_SHIFT 4 -#define DDR_PHY_DX8GCR0_RESERVED_4_MASK 0x00000010U +#define DDR_PHY_DX8GCR0_RESERVED_4_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_RESERVED_4_SHIFT 4 +#define DDR_PHY_DX8GCR0_RESERVED_4_MASK 0x00000010U -/*DQSG On-Die Termination*/ +/* +* DQSG On-Die Termination +*/ #undef DDR_PHY_DX8GCR0_DQSGODT_DEFVAL #undef DDR_PHY_DX8GCR0_DQSGODT_SHIFT #undef DDR_PHY_DX8GCR0_DQSGODT_MASK -#define DDR_PHY_DX8GCR0_DQSGODT_DEFVAL 0x40200204 -#define DDR_PHY_DX8GCR0_DQSGODT_SHIFT 3 -#define DDR_PHY_DX8GCR0_DQSGODT_MASK 0x00000008U +#define DDR_PHY_DX8GCR0_DQSGODT_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_DQSGODT_SHIFT 3 +#define DDR_PHY_DX8GCR0_DQSGODT_MASK 0x00000008U -/*DQSG Output Enable*/ +/* +* DQSG Output Enable +*/ #undef DDR_PHY_DX8GCR0_DQSGOE_DEFVAL #undef DDR_PHY_DX8GCR0_DQSGOE_SHIFT #undef DDR_PHY_DX8GCR0_DQSGOE_MASK -#define DDR_PHY_DX8GCR0_DQSGOE_DEFVAL 0x40200204 -#define DDR_PHY_DX8GCR0_DQSGOE_SHIFT 2 -#define DDR_PHY_DX8GCR0_DQSGOE_MASK 0x00000004U +#define DDR_PHY_DX8GCR0_DQSGOE_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_DQSGOE_SHIFT 2 +#define DDR_PHY_DX8GCR0_DQSGOE_MASK 0x00000004U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8GCR0_RESERVED_1_0_DEFVAL #undef DDR_PHY_DX8GCR0_RESERVED_1_0_SHIFT #undef DDR_PHY_DX8GCR0_RESERVED_1_0_MASK -#define DDR_PHY_DX8GCR0_RESERVED_1_0_DEFVAL 0x40200204 -#define DDR_PHY_DX8GCR0_RESERVED_1_0_SHIFT 0 -#define DDR_PHY_DX8GCR0_RESERVED_1_0_MASK 0x00000003U +#define DDR_PHY_DX8GCR0_RESERVED_1_0_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_RESERVED_1_0_SHIFT 0 +#define DDR_PHY_DX8GCR0_RESERVED_1_0_MASK 0x00000003U -/*Enables the PDR mode for DQ[7:0]*/ +/* +* Enables the PDR mode for DQ[7:0] +*/ #undef DDR_PHY_DX8GCR1_DXPDRMODE_DEFVAL #undef DDR_PHY_DX8GCR1_DXPDRMODE_SHIFT #undef DDR_PHY_DX8GCR1_DXPDRMODE_MASK -#define DDR_PHY_DX8GCR1_DXPDRMODE_DEFVAL 0x00007FFF -#define DDR_PHY_DX8GCR1_DXPDRMODE_SHIFT 16 -#define DDR_PHY_DX8GCR1_DXPDRMODE_MASK 0xFFFF0000U +#define DDR_PHY_DX8GCR1_DXPDRMODE_DEFVAL 0x00007FFF +#define DDR_PHY_DX8GCR1_DXPDRMODE_SHIFT 16 +#define DDR_PHY_DX8GCR1_DXPDRMODE_MASK 0xFFFF0000U -/*Reserved. Returns zeroes on reads.*/ +/* +* Reserved. Returns zeroes on reads. +*/ #undef DDR_PHY_DX8GCR1_RESERVED_15_DEFVAL #undef DDR_PHY_DX8GCR1_RESERVED_15_SHIFT #undef DDR_PHY_DX8GCR1_RESERVED_15_MASK -#define DDR_PHY_DX8GCR1_RESERVED_15_DEFVAL 0x00007FFF -#define DDR_PHY_DX8GCR1_RESERVED_15_SHIFT 15 -#define DDR_PHY_DX8GCR1_RESERVED_15_MASK 0x00008000U +#define DDR_PHY_DX8GCR1_RESERVED_15_DEFVAL 0x00007FFF +#define DDR_PHY_DX8GCR1_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX8GCR1_RESERVED_15_MASK 0x00008000U -/*Select the delayed or non-delayed read data strobe #*/ +/* +* Select the delayed or non-delayed read data strobe # +*/ #undef DDR_PHY_DX8GCR1_QSNSEL_DEFVAL #undef DDR_PHY_DX8GCR1_QSNSEL_SHIFT #undef DDR_PHY_DX8GCR1_QSNSEL_MASK -#define DDR_PHY_DX8GCR1_QSNSEL_DEFVAL 0x00007FFF -#define DDR_PHY_DX8GCR1_QSNSEL_SHIFT 14 -#define DDR_PHY_DX8GCR1_QSNSEL_MASK 0x00004000U +#define DDR_PHY_DX8GCR1_QSNSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX8GCR1_QSNSEL_SHIFT 14 +#define DDR_PHY_DX8GCR1_QSNSEL_MASK 0x00004000U -/*Select the delayed or non-delayed read data strobe*/ +/* +* Select the delayed or non-delayed read data strobe +*/ #undef DDR_PHY_DX8GCR1_QSSEL_DEFVAL #undef DDR_PHY_DX8GCR1_QSSEL_SHIFT #undef DDR_PHY_DX8GCR1_QSSEL_MASK -#define DDR_PHY_DX8GCR1_QSSEL_DEFVAL 0x00007FFF -#define DDR_PHY_DX8GCR1_QSSEL_SHIFT 13 -#define DDR_PHY_DX8GCR1_QSSEL_MASK 0x00002000U +#define DDR_PHY_DX8GCR1_QSSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX8GCR1_QSSEL_SHIFT 13 +#define DDR_PHY_DX8GCR1_QSSEL_MASK 0x00002000U -/*Enables Read Data Strobe in a byte lane*/ +/* +* Enables Read Data Strobe in a byte lane +*/ #undef DDR_PHY_DX8GCR1_OEEN_DEFVAL #undef DDR_PHY_DX8GCR1_OEEN_SHIFT #undef DDR_PHY_DX8GCR1_OEEN_MASK -#define DDR_PHY_DX8GCR1_OEEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX8GCR1_OEEN_SHIFT 12 -#define DDR_PHY_DX8GCR1_OEEN_MASK 0x00001000U +#define DDR_PHY_DX8GCR1_OEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX8GCR1_OEEN_SHIFT 12 +#define DDR_PHY_DX8GCR1_OEEN_MASK 0x00001000U -/*Enables PDR in a byte lane*/ +/* +* Enables PDR in a byte lane +*/ #undef DDR_PHY_DX8GCR1_PDREN_DEFVAL #undef DDR_PHY_DX8GCR1_PDREN_SHIFT #undef DDR_PHY_DX8GCR1_PDREN_MASK -#define DDR_PHY_DX8GCR1_PDREN_DEFVAL 0x00007FFF -#define DDR_PHY_DX8GCR1_PDREN_SHIFT 11 -#define DDR_PHY_DX8GCR1_PDREN_MASK 0x00000800U +#define DDR_PHY_DX8GCR1_PDREN_DEFVAL 0x00007FFF +#define DDR_PHY_DX8GCR1_PDREN_SHIFT 11 +#define DDR_PHY_DX8GCR1_PDREN_MASK 0x00000800U -/*Enables ODT/TE in a byte lane*/ +/* +* Enables ODT/TE in a byte lane +*/ #undef DDR_PHY_DX8GCR1_TEEN_DEFVAL #undef DDR_PHY_DX8GCR1_TEEN_SHIFT #undef DDR_PHY_DX8GCR1_TEEN_MASK -#define DDR_PHY_DX8GCR1_TEEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX8GCR1_TEEN_SHIFT 10 -#define DDR_PHY_DX8GCR1_TEEN_MASK 0x00000400U +#define DDR_PHY_DX8GCR1_TEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX8GCR1_TEEN_SHIFT 10 +#define DDR_PHY_DX8GCR1_TEEN_MASK 0x00000400U -/*Enables Write Data strobe in a byte lane*/ +/* +* Enables Write Data strobe in a byte lane +*/ #undef DDR_PHY_DX8GCR1_DSEN_DEFVAL #undef DDR_PHY_DX8GCR1_DSEN_SHIFT #undef DDR_PHY_DX8GCR1_DSEN_MASK -#define DDR_PHY_DX8GCR1_DSEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX8GCR1_DSEN_SHIFT 9 -#define DDR_PHY_DX8GCR1_DSEN_MASK 0x00000200U +#define DDR_PHY_DX8GCR1_DSEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX8GCR1_DSEN_SHIFT 9 +#define DDR_PHY_DX8GCR1_DSEN_MASK 0x00000200U -/*Enables DM pin in a byte lane*/ +/* +* Enables DM pin in a byte lane +*/ #undef DDR_PHY_DX8GCR1_DMEN_DEFVAL #undef DDR_PHY_DX8GCR1_DMEN_SHIFT #undef DDR_PHY_DX8GCR1_DMEN_MASK -#define DDR_PHY_DX8GCR1_DMEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX8GCR1_DMEN_SHIFT 8 -#define DDR_PHY_DX8GCR1_DMEN_MASK 0x00000100U +#define DDR_PHY_DX8GCR1_DMEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX8GCR1_DMEN_SHIFT 8 +#define DDR_PHY_DX8GCR1_DMEN_MASK 0x00000100U -/*Enables DQ corresponding to each bit in a byte*/ +/* +* Enables DQ corresponding to each bit in a byte +*/ #undef DDR_PHY_DX8GCR1_DQEN_DEFVAL #undef DDR_PHY_DX8GCR1_DQEN_SHIFT #undef DDR_PHY_DX8GCR1_DQEN_MASK -#define DDR_PHY_DX8GCR1_DQEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX8GCR1_DQEN_SHIFT 0 -#define DDR_PHY_DX8GCR1_DQEN_MASK 0x000000FFU +#define DDR_PHY_DX8GCR1_DQEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX8GCR1_DQEN_SHIFT 0 +#define DDR_PHY_DX8GCR1_DQEN_MASK 0x000000FFU -/*Byte lane VREF IOM (Used only by D4MU IOs)*/ +/* +* Byte lane VREF IOM (Used only by D4MU IOs) +*/ #undef DDR_PHY_DX8GCR4_RESERVED_31_29_DEFVAL #undef DDR_PHY_DX8GCR4_RESERVED_31_29_SHIFT #undef DDR_PHY_DX8GCR4_RESERVED_31_29_MASK -#define DDR_PHY_DX8GCR4_RESERVED_31_29_DEFVAL 0x0E00003C -#define DDR_PHY_DX8GCR4_RESERVED_31_29_SHIFT 29 -#define DDR_PHY_DX8GCR4_RESERVED_31_29_MASK 0xE0000000U +#define DDR_PHY_DX8GCR4_RESERVED_31_29_DEFVAL 0x0E00003C +#define DDR_PHY_DX8GCR4_RESERVED_31_29_SHIFT 29 +#define DDR_PHY_DX8GCR4_RESERVED_31_29_MASK 0xE0000000U -/*Byte Lane VREF Pad Enable*/ +/* +* Byte Lane VREF Pad Enable +*/ #undef DDR_PHY_DX8GCR4_DXREFPEN_DEFVAL #undef DDR_PHY_DX8GCR4_DXREFPEN_SHIFT #undef DDR_PHY_DX8GCR4_DXREFPEN_MASK -#define DDR_PHY_DX8GCR4_DXREFPEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX8GCR4_DXREFPEN_SHIFT 28 -#define DDR_PHY_DX8GCR4_DXREFPEN_MASK 0x10000000U +#define DDR_PHY_DX8GCR4_DXREFPEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX8GCR4_DXREFPEN_SHIFT 28 +#define DDR_PHY_DX8GCR4_DXREFPEN_MASK 0x10000000U -/*Byte Lane Internal VREF Enable*/ +/* +* Byte Lane Internal VREF Enable +*/ #undef DDR_PHY_DX8GCR4_DXREFEEN_DEFVAL #undef DDR_PHY_DX8GCR4_DXREFEEN_SHIFT #undef DDR_PHY_DX8GCR4_DXREFEEN_MASK -#define DDR_PHY_DX8GCR4_DXREFEEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX8GCR4_DXREFEEN_SHIFT 26 -#define DDR_PHY_DX8GCR4_DXREFEEN_MASK 0x0C000000U +#define DDR_PHY_DX8GCR4_DXREFEEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX8GCR4_DXREFEEN_SHIFT 26 +#define DDR_PHY_DX8GCR4_DXREFEEN_MASK 0x0C000000U -/*Byte Lane Single-End VREF Enable*/ +/* +* Byte Lane Single-End VREF Enable +*/ #undef DDR_PHY_DX8GCR4_DXREFSEN_DEFVAL #undef DDR_PHY_DX8GCR4_DXREFSEN_SHIFT #undef DDR_PHY_DX8GCR4_DXREFSEN_MASK -#define DDR_PHY_DX8GCR4_DXREFSEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX8GCR4_DXREFSEN_SHIFT 25 -#define DDR_PHY_DX8GCR4_DXREFSEN_MASK 0x02000000U +#define DDR_PHY_DX8GCR4_DXREFSEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX8GCR4_DXREFSEN_SHIFT 25 +#define DDR_PHY_DX8GCR4_DXREFSEN_MASK 0x02000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX8GCR4_RESERVED_24_DEFVAL #undef DDR_PHY_DX8GCR4_RESERVED_24_SHIFT #undef DDR_PHY_DX8GCR4_RESERVED_24_MASK -#define DDR_PHY_DX8GCR4_RESERVED_24_DEFVAL 0x0E00003C -#define DDR_PHY_DX8GCR4_RESERVED_24_SHIFT 24 -#define DDR_PHY_DX8GCR4_RESERVED_24_MASK 0x01000000U +#define DDR_PHY_DX8GCR4_RESERVED_24_DEFVAL 0x0E00003C +#define DDR_PHY_DX8GCR4_RESERVED_24_SHIFT 24 +#define DDR_PHY_DX8GCR4_RESERVED_24_MASK 0x01000000U -/*External VREF generator REFSEL range select*/ +/* +* External VREF generator REFSEL range select +*/ #undef DDR_PHY_DX8GCR4_DXREFESELRANGE_DEFVAL #undef DDR_PHY_DX8GCR4_DXREFESELRANGE_SHIFT #undef DDR_PHY_DX8GCR4_DXREFESELRANGE_MASK -#define DDR_PHY_DX8GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C -#define DDR_PHY_DX8GCR4_DXREFESELRANGE_SHIFT 23 -#define DDR_PHY_DX8GCR4_DXREFESELRANGE_MASK 0x00800000U +#define DDR_PHY_DX8GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX8GCR4_DXREFESELRANGE_SHIFT 23 +#define DDR_PHY_DX8GCR4_DXREFESELRANGE_MASK 0x00800000U -/*Byte Lane External VREF Select*/ +/* +* Byte Lane External VREF Select +*/ #undef DDR_PHY_DX8GCR4_DXREFESEL_DEFVAL #undef DDR_PHY_DX8GCR4_DXREFESEL_SHIFT #undef DDR_PHY_DX8GCR4_DXREFESEL_MASK -#define DDR_PHY_DX8GCR4_DXREFESEL_DEFVAL 0x0E00003C -#define DDR_PHY_DX8GCR4_DXREFESEL_SHIFT 16 -#define DDR_PHY_DX8GCR4_DXREFESEL_MASK 0x007F0000U +#define DDR_PHY_DX8GCR4_DXREFESEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX8GCR4_DXREFESEL_SHIFT 16 +#define DDR_PHY_DX8GCR4_DXREFESEL_MASK 0x007F0000U -/*Single ended VREF generator REFSEL range select*/ +/* +* Single ended VREF generator REFSEL range select +*/ #undef DDR_PHY_DX8GCR4_DXREFSSELRANGE_DEFVAL #undef DDR_PHY_DX8GCR4_DXREFSSELRANGE_SHIFT #undef DDR_PHY_DX8GCR4_DXREFSSELRANGE_MASK -#define DDR_PHY_DX8GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C -#define DDR_PHY_DX8GCR4_DXREFSSELRANGE_SHIFT 15 -#define DDR_PHY_DX8GCR4_DXREFSSELRANGE_MASK 0x00008000U +#define DDR_PHY_DX8GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX8GCR4_DXREFSSELRANGE_SHIFT 15 +#define DDR_PHY_DX8GCR4_DXREFSSELRANGE_MASK 0x00008000U -/*Byte Lane Single-End VREF Select*/ +/* +* Byte Lane Single-End VREF Select +*/ #undef DDR_PHY_DX8GCR4_DXREFSSEL_DEFVAL #undef DDR_PHY_DX8GCR4_DXREFSSEL_SHIFT #undef DDR_PHY_DX8GCR4_DXREFSSEL_MASK -#define DDR_PHY_DX8GCR4_DXREFSSEL_DEFVAL 0x0E00003C -#define DDR_PHY_DX8GCR4_DXREFSSEL_SHIFT 8 -#define DDR_PHY_DX8GCR4_DXREFSSEL_MASK 0x00007F00U +#define DDR_PHY_DX8GCR4_DXREFSSEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX8GCR4_DXREFSSEL_SHIFT 8 +#define DDR_PHY_DX8GCR4_DXREFSSEL_MASK 0x00007F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX8GCR4_RESERVED_7_6_DEFVAL #undef DDR_PHY_DX8GCR4_RESERVED_7_6_SHIFT #undef DDR_PHY_DX8GCR4_RESERVED_7_6_MASK -#define DDR_PHY_DX8GCR4_RESERVED_7_6_DEFVAL 0x0E00003C -#define DDR_PHY_DX8GCR4_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_DX8GCR4_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_DX8GCR4_RESERVED_7_6_DEFVAL 0x0E00003C +#define DDR_PHY_DX8GCR4_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX8GCR4_RESERVED_7_6_MASK 0x000000C0U -/*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/ +/* +* VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. +*/ #undef DDR_PHY_DX8GCR4_DXREFIEN_DEFVAL #undef DDR_PHY_DX8GCR4_DXREFIEN_SHIFT #undef DDR_PHY_DX8GCR4_DXREFIEN_MASK -#define DDR_PHY_DX8GCR4_DXREFIEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX8GCR4_DXREFIEN_SHIFT 2 -#define DDR_PHY_DX8GCR4_DXREFIEN_MASK 0x0000003CU +#define DDR_PHY_DX8GCR4_DXREFIEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX8GCR4_DXREFIEN_SHIFT 2 +#define DDR_PHY_DX8GCR4_DXREFIEN_MASK 0x0000003CU -/*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/ +/* +* VRMON control for DQ IO (Single Ended) buffers of a byte lane. +*/ #undef DDR_PHY_DX8GCR4_DXREFIMON_DEFVAL #undef DDR_PHY_DX8GCR4_DXREFIMON_SHIFT #undef DDR_PHY_DX8GCR4_DXREFIMON_MASK -#define DDR_PHY_DX8GCR4_DXREFIMON_DEFVAL 0x0E00003C -#define DDR_PHY_DX8GCR4_DXREFIMON_SHIFT 0 -#define DDR_PHY_DX8GCR4_DXREFIMON_MASK 0x00000003U +#define DDR_PHY_DX8GCR4_DXREFIMON_DEFVAL 0x0E00003C +#define DDR_PHY_DX8GCR4_DXREFIMON_SHIFT 0 +#define DDR_PHY_DX8GCR4_DXREFIMON_MASK 0x00000003U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX8GCR5_RESERVED_31_DEFVAL #undef DDR_PHY_DX8GCR5_RESERVED_31_SHIFT #undef DDR_PHY_DX8GCR5_RESERVED_31_MASK -#define DDR_PHY_DX8GCR5_RESERVED_31_DEFVAL 0x09090909 -#define DDR_PHY_DX8GCR5_RESERVED_31_SHIFT 31 -#define DDR_PHY_DX8GCR5_RESERVED_31_MASK 0x80000000U +#define DDR_PHY_DX8GCR5_RESERVED_31_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR5_RESERVED_31_SHIFT 31 +#define DDR_PHY_DX8GCR5_RESERVED_31_MASK 0x80000000U -/*Byte Lane internal VREF Select for Rank 3*/ +/* +* Byte Lane internal VREF Select for Rank 3 +*/ #undef DDR_PHY_DX8GCR5_DXREFISELR3_DEFVAL #undef DDR_PHY_DX8GCR5_DXREFISELR3_SHIFT #undef DDR_PHY_DX8GCR5_DXREFISELR3_MASK -#define DDR_PHY_DX8GCR5_DXREFISELR3_DEFVAL 0x09090909 -#define DDR_PHY_DX8GCR5_DXREFISELR3_SHIFT 24 -#define DDR_PHY_DX8GCR5_DXREFISELR3_MASK 0x7F000000U +#define DDR_PHY_DX8GCR5_DXREFISELR3_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR5_DXREFISELR3_SHIFT 24 +#define DDR_PHY_DX8GCR5_DXREFISELR3_MASK 0x7F000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX8GCR5_RESERVED_23_DEFVAL #undef DDR_PHY_DX8GCR5_RESERVED_23_SHIFT #undef DDR_PHY_DX8GCR5_RESERVED_23_MASK -#define DDR_PHY_DX8GCR5_RESERVED_23_DEFVAL 0x09090909 -#define DDR_PHY_DX8GCR5_RESERVED_23_SHIFT 23 -#define DDR_PHY_DX8GCR5_RESERVED_23_MASK 0x00800000U +#define DDR_PHY_DX8GCR5_RESERVED_23_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR5_RESERVED_23_SHIFT 23 +#define DDR_PHY_DX8GCR5_RESERVED_23_MASK 0x00800000U -/*Byte Lane internal VREF Select for Rank 2*/ +/* +* Byte Lane internal VREF Select for Rank 2 +*/ #undef DDR_PHY_DX8GCR5_DXREFISELR2_DEFVAL #undef DDR_PHY_DX8GCR5_DXREFISELR2_SHIFT #undef DDR_PHY_DX8GCR5_DXREFISELR2_MASK -#define DDR_PHY_DX8GCR5_DXREFISELR2_DEFVAL 0x09090909 -#define DDR_PHY_DX8GCR5_DXREFISELR2_SHIFT 16 -#define DDR_PHY_DX8GCR5_DXREFISELR2_MASK 0x007F0000U +#define DDR_PHY_DX8GCR5_DXREFISELR2_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR5_DXREFISELR2_SHIFT 16 +#define DDR_PHY_DX8GCR5_DXREFISELR2_MASK 0x007F0000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX8GCR5_RESERVED_15_DEFVAL #undef DDR_PHY_DX8GCR5_RESERVED_15_SHIFT #undef DDR_PHY_DX8GCR5_RESERVED_15_MASK -#define DDR_PHY_DX8GCR5_RESERVED_15_DEFVAL 0x09090909 -#define DDR_PHY_DX8GCR5_RESERVED_15_SHIFT 15 -#define DDR_PHY_DX8GCR5_RESERVED_15_MASK 0x00008000U +#define DDR_PHY_DX8GCR5_RESERVED_15_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR5_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX8GCR5_RESERVED_15_MASK 0x00008000U -/*Byte Lane internal VREF Select for Rank 1*/ +/* +* Byte Lane internal VREF Select for Rank 1 +*/ #undef DDR_PHY_DX8GCR5_DXREFISELR1_DEFVAL #undef DDR_PHY_DX8GCR5_DXREFISELR1_SHIFT #undef DDR_PHY_DX8GCR5_DXREFISELR1_MASK -#define DDR_PHY_DX8GCR5_DXREFISELR1_DEFVAL 0x09090909 -#define DDR_PHY_DX8GCR5_DXREFISELR1_SHIFT 8 -#define DDR_PHY_DX8GCR5_DXREFISELR1_MASK 0x00007F00U +#define DDR_PHY_DX8GCR5_DXREFISELR1_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR5_DXREFISELR1_SHIFT 8 +#define DDR_PHY_DX8GCR5_DXREFISELR1_MASK 0x00007F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX8GCR5_RESERVED_7_DEFVAL #undef DDR_PHY_DX8GCR5_RESERVED_7_SHIFT #undef DDR_PHY_DX8GCR5_RESERVED_7_MASK -#define DDR_PHY_DX8GCR5_RESERVED_7_DEFVAL 0x09090909 -#define DDR_PHY_DX8GCR5_RESERVED_7_SHIFT 7 -#define DDR_PHY_DX8GCR5_RESERVED_7_MASK 0x00000080U +#define DDR_PHY_DX8GCR5_RESERVED_7_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR5_RESERVED_7_SHIFT 7 +#define DDR_PHY_DX8GCR5_RESERVED_7_MASK 0x00000080U -/*Byte Lane internal VREF Select for Rank 0*/ +/* +* Byte Lane internal VREF Select for Rank 0 +*/ #undef DDR_PHY_DX8GCR5_DXREFISELR0_DEFVAL #undef DDR_PHY_DX8GCR5_DXREFISELR0_SHIFT #undef DDR_PHY_DX8GCR5_DXREFISELR0_MASK -#define DDR_PHY_DX8GCR5_DXREFISELR0_DEFVAL 0x09090909 -#define DDR_PHY_DX8GCR5_DXREFISELR0_SHIFT 0 -#define DDR_PHY_DX8GCR5_DXREFISELR0_MASK 0x0000007FU +#define DDR_PHY_DX8GCR5_DXREFISELR0_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR5_DXREFISELR0_SHIFT 0 +#define DDR_PHY_DX8GCR5_DXREFISELR0_MASK 0x0000007FU -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX8GCR6_RESERVED_31_30_DEFVAL #undef DDR_PHY_DX8GCR6_RESERVED_31_30_SHIFT #undef DDR_PHY_DX8GCR6_RESERVED_31_30_MASK -#define DDR_PHY_DX8GCR6_RESERVED_31_30_DEFVAL 0x09090909 -#define DDR_PHY_DX8GCR6_RESERVED_31_30_SHIFT 30 -#define DDR_PHY_DX8GCR6_RESERVED_31_30_MASK 0xC0000000U +#define DDR_PHY_DX8GCR6_RESERVED_31_30_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR6_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX8GCR6_RESERVED_31_30_MASK 0xC0000000U -/*DRAM DQ VREF Select for Rank3*/ +/* +* DRAM DQ VREF Select for Rank3 +*/ #undef DDR_PHY_DX8GCR6_DXDQVREFR3_DEFVAL #undef DDR_PHY_DX8GCR6_DXDQVREFR3_SHIFT #undef DDR_PHY_DX8GCR6_DXDQVREFR3_MASK -#define DDR_PHY_DX8GCR6_DXDQVREFR3_DEFVAL 0x09090909 -#define DDR_PHY_DX8GCR6_DXDQVREFR3_SHIFT 24 -#define DDR_PHY_DX8GCR6_DXDQVREFR3_MASK 0x3F000000U +#define DDR_PHY_DX8GCR6_DXDQVREFR3_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR6_DXDQVREFR3_SHIFT 24 +#define DDR_PHY_DX8GCR6_DXDQVREFR3_MASK 0x3F000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX8GCR6_RESERVED_23_22_DEFVAL #undef DDR_PHY_DX8GCR6_RESERVED_23_22_SHIFT #undef DDR_PHY_DX8GCR6_RESERVED_23_22_MASK -#define DDR_PHY_DX8GCR6_RESERVED_23_22_DEFVAL 0x09090909 -#define DDR_PHY_DX8GCR6_RESERVED_23_22_SHIFT 22 -#define DDR_PHY_DX8GCR6_RESERVED_23_22_MASK 0x00C00000U +#define DDR_PHY_DX8GCR6_RESERVED_23_22_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR6_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX8GCR6_RESERVED_23_22_MASK 0x00C00000U -/*DRAM DQ VREF Select for Rank2*/ +/* +* DRAM DQ VREF Select for Rank2 +*/ #undef DDR_PHY_DX8GCR6_DXDQVREFR2_DEFVAL #undef DDR_PHY_DX8GCR6_DXDQVREFR2_SHIFT #undef DDR_PHY_DX8GCR6_DXDQVREFR2_MASK -#define DDR_PHY_DX8GCR6_DXDQVREFR2_DEFVAL 0x09090909 -#define DDR_PHY_DX8GCR6_DXDQVREFR2_SHIFT 16 -#define DDR_PHY_DX8GCR6_DXDQVREFR2_MASK 0x003F0000U +#define DDR_PHY_DX8GCR6_DXDQVREFR2_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR6_DXDQVREFR2_SHIFT 16 +#define DDR_PHY_DX8GCR6_DXDQVREFR2_MASK 0x003F0000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX8GCR6_RESERVED_15_14_DEFVAL #undef DDR_PHY_DX8GCR6_RESERVED_15_14_SHIFT #undef DDR_PHY_DX8GCR6_RESERVED_15_14_MASK -#define DDR_PHY_DX8GCR6_RESERVED_15_14_DEFVAL 0x09090909 -#define DDR_PHY_DX8GCR6_RESERVED_15_14_SHIFT 14 -#define DDR_PHY_DX8GCR6_RESERVED_15_14_MASK 0x0000C000U +#define DDR_PHY_DX8GCR6_RESERVED_15_14_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR6_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_DX8GCR6_RESERVED_15_14_MASK 0x0000C000U -/*DRAM DQ VREF Select for Rank1*/ +/* +* DRAM DQ VREF Select for Rank1 +*/ #undef DDR_PHY_DX8GCR6_DXDQVREFR1_DEFVAL #undef DDR_PHY_DX8GCR6_DXDQVREFR1_SHIFT #undef DDR_PHY_DX8GCR6_DXDQVREFR1_MASK -#define DDR_PHY_DX8GCR6_DXDQVREFR1_DEFVAL 0x09090909 -#define DDR_PHY_DX8GCR6_DXDQVREFR1_SHIFT 8 -#define DDR_PHY_DX8GCR6_DXDQVREFR1_MASK 0x00003F00U +#define DDR_PHY_DX8GCR6_DXDQVREFR1_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR6_DXDQVREFR1_SHIFT 8 +#define DDR_PHY_DX8GCR6_DXDQVREFR1_MASK 0x00003F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX8GCR6_RESERVED_7_6_DEFVAL #undef DDR_PHY_DX8GCR6_RESERVED_7_6_SHIFT #undef DDR_PHY_DX8GCR6_RESERVED_7_6_MASK -#define DDR_PHY_DX8GCR6_RESERVED_7_6_DEFVAL 0x09090909 -#define DDR_PHY_DX8GCR6_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_DX8GCR6_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_DX8GCR6_RESERVED_7_6_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR6_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX8GCR6_RESERVED_7_6_MASK 0x000000C0U -/*DRAM DQ VREF Select for Rank0*/ +/* +* DRAM DQ VREF Select for Rank0 +*/ #undef DDR_PHY_DX8GCR6_DXDQVREFR0_DEFVAL #undef DDR_PHY_DX8GCR6_DXDQVREFR0_SHIFT #undef DDR_PHY_DX8GCR6_DXDQVREFR0_MASK -#define DDR_PHY_DX8GCR6_DXDQVREFR0_DEFVAL 0x09090909 -#define DDR_PHY_DX8GCR6_DXDQVREFR0_SHIFT 0 -#define DDR_PHY_DX8GCR6_DXDQVREFR0_MASK 0x0000003FU +#define DDR_PHY_DX8GCR6_DXDQVREFR0_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR6_DXDQVREFR0_SHIFT 0 +#define DDR_PHY_DX8GCR6_DXDQVREFR0_MASK 0x0000003FU -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX8LCDLR2_RESERVED_31_25_DEFVAL -#undef DDR_PHY_DX8LCDLR2_RESERVED_31_25_SHIFT -#undef DDR_PHY_DX8LCDLR2_RESERVED_31_25_MASK -#define DDR_PHY_DX8LCDLR2_RESERVED_31_25_DEFVAL 0x00000000 -#define DDR_PHY_DX8LCDLR2_RESERVED_31_25_SHIFT 25 -#define DDR_PHY_DX8LCDLR2_RESERVED_31_25_MASK 0xFE000000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX8LCDLR2_RESERVED_24_16_DEFVAL -#undef DDR_PHY_DX8LCDLR2_RESERVED_24_16_SHIFT -#undef DDR_PHY_DX8LCDLR2_RESERVED_24_16_MASK -#define DDR_PHY_DX8LCDLR2_RESERVED_24_16_DEFVAL 0x00000000 -#define DDR_PHY_DX8LCDLR2_RESERVED_24_16_SHIFT 16 -#define DDR_PHY_DX8LCDLR2_RESERVED_24_16_MASK 0x01FF0000U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX8LCDLR2_RESERVED_15_9_DEFVAL -#undef DDR_PHY_DX8LCDLR2_RESERVED_15_9_SHIFT -#undef DDR_PHY_DX8LCDLR2_RESERVED_15_9_MASK -#define DDR_PHY_DX8LCDLR2_RESERVED_15_9_DEFVAL 0x00000000 -#define DDR_PHY_DX8LCDLR2_RESERVED_15_9_SHIFT 9 -#define DDR_PHY_DX8LCDLR2_RESERVED_15_9_MASK 0x0000FE00U - -/*Read DQS Gating Delay*/ -#undef DDR_PHY_DX8LCDLR2_DQSGD_DEFVAL -#undef DDR_PHY_DX8LCDLR2_DQSGD_SHIFT -#undef DDR_PHY_DX8LCDLR2_DQSGD_MASK -#define DDR_PHY_DX8LCDLR2_DQSGD_DEFVAL 0x00000000 -#define DDR_PHY_DX8LCDLR2_DQSGD_SHIFT 0 -#define DDR_PHY_DX8LCDLR2_DQSGD_MASK 0x000001FFU - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX8GTR0_RESERVED_31_24_DEFVAL -#undef DDR_PHY_DX8GTR0_RESERVED_31_24_SHIFT -#undef DDR_PHY_DX8GTR0_RESERVED_31_24_MASK -#define DDR_PHY_DX8GTR0_RESERVED_31_24_DEFVAL 0x00020000 -#define DDR_PHY_DX8GTR0_RESERVED_31_24_SHIFT 27 -#define DDR_PHY_DX8GTR0_RESERVED_31_24_MASK 0xF8000000U - -/*DQ Write Path Latency Pipeline*/ -#undef DDR_PHY_DX8GTR0_WDQSL_DEFVAL -#undef DDR_PHY_DX8GTR0_WDQSL_SHIFT -#undef DDR_PHY_DX8GTR0_WDQSL_MASK -#define DDR_PHY_DX8GTR0_WDQSL_DEFVAL 0x00020000 -#define DDR_PHY_DX8GTR0_WDQSL_SHIFT 24 -#define DDR_PHY_DX8GTR0_WDQSL_MASK 0x07000000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX8GTR0_RESERVED_23_20_DEFVAL -#undef DDR_PHY_DX8GTR0_RESERVED_23_20_SHIFT -#undef DDR_PHY_DX8GTR0_RESERVED_23_20_MASK -#define DDR_PHY_DX8GTR0_RESERVED_23_20_DEFVAL 0x00020000 -#define DDR_PHY_DX8GTR0_RESERVED_23_20_SHIFT 20 -#define DDR_PHY_DX8GTR0_RESERVED_23_20_MASK 0x00F00000U - -/*Write Leveling System Latency*/ -#undef DDR_PHY_DX8GTR0_WLSL_DEFVAL -#undef DDR_PHY_DX8GTR0_WLSL_SHIFT -#undef DDR_PHY_DX8GTR0_WLSL_MASK -#define DDR_PHY_DX8GTR0_WLSL_DEFVAL 0x00020000 -#define DDR_PHY_DX8GTR0_WLSL_SHIFT 16 -#define DDR_PHY_DX8GTR0_WLSL_MASK 0x000F0000U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX8GTR0_RESERVED_15_13_DEFVAL -#undef DDR_PHY_DX8GTR0_RESERVED_15_13_SHIFT -#undef DDR_PHY_DX8GTR0_RESERVED_15_13_MASK -#define DDR_PHY_DX8GTR0_RESERVED_15_13_DEFVAL 0x00020000 -#define DDR_PHY_DX8GTR0_RESERVED_15_13_SHIFT 13 -#define DDR_PHY_DX8GTR0_RESERVED_15_13_MASK 0x0000E000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX8GTR0_RESERVED_12_8_DEFVAL -#undef DDR_PHY_DX8GTR0_RESERVED_12_8_SHIFT -#undef DDR_PHY_DX8GTR0_RESERVED_12_8_MASK -#define DDR_PHY_DX8GTR0_RESERVED_12_8_DEFVAL 0x00020000 -#define DDR_PHY_DX8GTR0_RESERVED_12_8_SHIFT 8 -#define DDR_PHY_DX8GTR0_RESERVED_12_8_MASK 0x00001F00U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX8GTR0_RESERVED_7_5_DEFVAL -#undef DDR_PHY_DX8GTR0_RESERVED_7_5_SHIFT -#undef DDR_PHY_DX8GTR0_RESERVED_7_5_MASK -#define DDR_PHY_DX8GTR0_RESERVED_7_5_DEFVAL 0x00020000 -#define DDR_PHY_DX8GTR0_RESERVED_7_5_SHIFT 5 -#define DDR_PHY_DX8GTR0_RESERVED_7_5_MASK 0x000000E0U - -/*DQS Gating System Latency*/ -#undef DDR_PHY_DX8GTR0_DGSL_DEFVAL -#undef DDR_PHY_DX8GTR0_DGSL_SHIFT -#undef DDR_PHY_DX8GTR0_DGSL_MASK -#define DDR_PHY_DX8GTR0_DGSL_DEFVAL 0x00020000 -#define DDR_PHY_DX8GTR0_DGSL_SHIFT 0 -#define DDR_PHY_DX8GTR0_DGSL_MASK 0x0000001FU - -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL0OSC_RESERVED_31_30_DEFVAL #undef DDR_PHY_DX8SL0OSC_RESERVED_31_30_SHIFT #undef DDR_PHY_DX8SL0OSC_RESERVED_31_30_MASK -#define DDR_PHY_DX8SL0OSC_RESERVED_31_30_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL0OSC_RESERVED_31_30_SHIFT 30 -#define DDR_PHY_DX8SL0OSC_RESERVED_31_30_MASK 0xC0000000U +#define DDR_PHY_DX8SL0OSC_RESERVED_31_30_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX8SL0OSC_RESERVED_31_30_MASK 0xC0000000U -/*Enable Clock Gating for DX ddr_clk*/ +/* +* Enable Clock Gating for DX ddr_clk +*/ #undef DDR_PHY_DX8SL0OSC_GATEDXRDCLK_DEFVAL #undef DDR_PHY_DX8SL0OSC_GATEDXRDCLK_SHIFT #undef DDR_PHY_DX8SL0OSC_GATEDXRDCLK_MASK -#define DDR_PHY_DX8SL0OSC_GATEDXRDCLK_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL0OSC_GATEDXRDCLK_SHIFT 28 -#define DDR_PHY_DX8SL0OSC_GATEDXRDCLK_MASK 0x30000000U +#define DDR_PHY_DX8SL0OSC_GATEDXRDCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_GATEDXRDCLK_SHIFT 28 +#define DDR_PHY_DX8SL0OSC_GATEDXRDCLK_MASK 0x30000000U -/*Enable Clock Gating for DX ctl_rd_clk*/ +/* +* Enable Clock Gating for DX ctl_rd_clk +*/ #undef DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_DEFVAL #undef DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_SHIFT #undef DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_MASK -#define DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_SHIFT 26 -#define DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_MASK 0x0C000000U +#define DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_SHIFT 26 +#define DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_MASK 0x0C000000U -/*Enable Clock Gating for DX ctl_clk*/ +/* +* Enable Clock Gating for DX ctl_clk +*/ #undef DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_DEFVAL #undef DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_SHIFT #undef DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_MASK -#define DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_SHIFT 24 -#define DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_MASK 0x03000000U +#define DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_SHIFT 24 +#define DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_MASK 0x03000000U -/*Selects the level to which clocks will be stalled when clock gating is enabled.*/ +/* +* Selects the level to which clocks will be stalled when clock gating is e + * nabled. +*/ #undef DDR_PHY_DX8SL0OSC_CLKLEVEL_DEFVAL #undef DDR_PHY_DX8SL0OSC_CLKLEVEL_SHIFT #undef DDR_PHY_DX8SL0OSC_CLKLEVEL_MASK -#define DDR_PHY_DX8SL0OSC_CLKLEVEL_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL0OSC_CLKLEVEL_SHIFT 22 -#define DDR_PHY_DX8SL0OSC_CLKLEVEL_MASK 0x00C00000U +#define DDR_PHY_DX8SL0OSC_CLKLEVEL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_CLKLEVEL_SHIFT 22 +#define DDR_PHY_DX8SL0OSC_CLKLEVEL_MASK 0x00C00000U -/*Loopback Mode*/ +/* +* Loopback Mode +*/ #undef DDR_PHY_DX8SL0OSC_LBMODE_DEFVAL #undef DDR_PHY_DX8SL0OSC_LBMODE_SHIFT #undef DDR_PHY_DX8SL0OSC_LBMODE_MASK -#define DDR_PHY_DX8SL0OSC_LBMODE_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL0OSC_LBMODE_SHIFT 21 -#define DDR_PHY_DX8SL0OSC_LBMODE_MASK 0x00200000U +#define DDR_PHY_DX8SL0OSC_LBMODE_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_LBMODE_SHIFT 21 +#define DDR_PHY_DX8SL0OSC_LBMODE_MASK 0x00200000U -/*Load GSDQS LCDL with 2x the calibrated GSDQSPRD value*/ +/* +* Load GSDQS LCDL with 2x the calibrated GSDQSPRD value +*/ #undef DDR_PHY_DX8SL0OSC_LBGSDQS_DEFVAL #undef DDR_PHY_DX8SL0OSC_LBGSDQS_SHIFT #undef DDR_PHY_DX8SL0OSC_LBGSDQS_MASK -#define DDR_PHY_DX8SL0OSC_LBGSDQS_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL0OSC_LBGSDQS_SHIFT 20 -#define DDR_PHY_DX8SL0OSC_LBGSDQS_MASK 0x00100000U +#define DDR_PHY_DX8SL0OSC_LBGSDQS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_LBGSDQS_SHIFT 20 +#define DDR_PHY_DX8SL0OSC_LBGSDQS_MASK 0x00100000U -/*Loopback DQS Gating*/ +/* +* Loopback DQS Gating +*/ #undef DDR_PHY_DX8SL0OSC_LBGDQS_DEFVAL #undef DDR_PHY_DX8SL0OSC_LBGDQS_SHIFT #undef DDR_PHY_DX8SL0OSC_LBGDQS_MASK -#define DDR_PHY_DX8SL0OSC_LBGDQS_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL0OSC_LBGDQS_SHIFT 18 -#define DDR_PHY_DX8SL0OSC_LBGDQS_MASK 0x000C0000U +#define DDR_PHY_DX8SL0OSC_LBGDQS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_LBGDQS_SHIFT 18 +#define DDR_PHY_DX8SL0OSC_LBGDQS_MASK 0x000C0000U -/*Loopback DQS Shift*/ +/* +* Loopback DQS Shift +*/ #undef DDR_PHY_DX8SL0OSC_LBDQSS_DEFVAL #undef DDR_PHY_DX8SL0OSC_LBDQSS_SHIFT #undef DDR_PHY_DX8SL0OSC_LBDQSS_MASK -#define DDR_PHY_DX8SL0OSC_LBDQSS_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL0OSC_LBDQSS_SHIFT 17 -#define DDR_PHY_DX8SL0OSC_LBDQSS_MASK 0x00020000U +#define DDR_PHY_DX8SL0OSC_LBDQSS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_LBDQSS_SHIFT 17 +#define DDR_PHY_DX8SL0OSC_LBDQSS_MASK 0x00020000U -/*PHY High-Speed Reset*/ +/* +* PHY High-Speed Reset +*/ #undef DDR_PHY_DX8SL0OSC_PHYHRST_DEFVAL #undef DDR_PHY_DX8SL0OSC_PHYHRST_SHIFT #undef DDR_PHY_DX8SL0OSC_PHYHRST_MASK -#define DDR_PHY_DX8SL0OSC_PHYHRST_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL0OSC_PHYHRST_SHIFT 16 -#define DDR_PHY_DX8SL0OSC_PHYHRST_MASK 0x00010000U +#define DDR_PHY_DX8SL0OSC_PHYHRST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_PHYHRST_SHIFT 16 +#define DDR_PHY_DX8SL0OSC_PHYHRST_MASK 0x00010000U -/*PHY FIFO Reset*/ +/* +* PHY FIFO Reset +*/ #undef DDR_PHY_DX8SL0OSC_PHYFRST_DEFVAL #undef DDR_PHY_DX8SL0OSC_PHYFRST_SHIFT #undef DDR_PHY_DX8SL0OSC_PHYFRST_MASK -#define DDR_PHY_DX8SL0OSC_PHYFRST_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL0OSC_PHYFRST_SHIFT 15 -#define DDR_PHY_DX8SL0OSC_PHYFRST_MASK 0x00008000U +#define DDR_PHY_DX8SL0OSC_PHYFRST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_PHYFRST_SHIFT 15 +#define DDR_PHY_DX8SL0OSC_PHYFRST_MASK 0x00008000U -/*Delay Line Test Start*/ +/* +* Delay Line Test Start +*/ #undef DDR_PHY_DX8SL0OSC_DLTST_DEFVAL #undef DDR_PHY_DX8SL0OSC_DLTST_SHIFT #undef DDR_PHY_DX8SL0OSC_DLTST_MASK -#define DDR_PHY_DX8SL0OSC_DLTST_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL0OSC_DLTST_SHIFT 14 -#define DDR_PHY_DX8SL0OSC_DLTST_MASK 0x00004000U +#define DDR_PHY_DX8SL0OSC_DLTST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_DLTST_SHIFT 14 +#define DDR_PHY_DX8SL0OSC_DLTST_MASK 0x00004000U -/*Delay Line Test Mode*/ +/* +* Delay Line Test Mode +*/ #undef DDR_PHY_DX8SL0OSC_DLTMODE_DEFVAL #undef DDR_PHY_DX8SL0OSC_DLTMODE_SHIFT #undef DDR_PHY_DX8SL0OSC_DLTMODE_MASK -#define DDR_PHY_DX8SL0OSC_DLTMODE_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL0OSC_DLTMODE_SHIFT 13 -#define DDR_PHY_DX8SL0OSC_DLTMODE_MASK 0x00002000U +#define DDR_PHY_DX8SL0OSC_DLTMODE_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_DLTMODE_SHIFT 13 +#define DDR_PHY_DX8SL0OSC_DLTMODE_MASK 0x00002000U -/*Reserved. Caution, do not write to this register field.*/ +/* +* Reserved. Caution, do not write to this register field. +*/ #undef DDR_PHY_DX8SL0OSC_RESERVED_12_11_DEFVAL #undef DDR_PHY_DX8SL0OSC_RESERVED_12_11_SHIFT #undef DDR_PHY_DX8SL0OSC_RESERVED_12_11_MASK -#define DDR_PHY_DX8SL0OSC_RESERVED_12_11_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL0OSC_RESERVED_12_11_SHIFT 11 -#define DDR_PHY_DX8SL0OSC_RESERVED_12_11_MASK 0x00001800U +#define DDR_PHY_DX8SL0OSC_RESERVED_12_11_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_RESERVED_12_11_SHIFT 11 +#define DDR_PHY_DX8SL0OSC_RESERVED_12_11_MASK 0x00001800U -/*Oscillator Mode Write-Data Delay Line Select*/ +/* +* Oscillator Mode Write-Data Delay Line Select +*/ #undef DDR_PHY_DX8SL0OSC_OSCWDDL_DEFVAL #undef DDR_PHY_DX8SL0OSC_OSCWDDL_SHIFT #undef DDR_PHY_DX8SL0OSC_OSCWDDL_MASK -#define DDR_PHY_DX8SL0OSC_OSCWDDL_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL0OSC_OSCWDDL_SHIFT 9 -#define DDR_PHY_DX8SL0OSC_OSCWDDL_MASK 0x00000600U +#define DDR_PHY_DX8SL0OSC_OSCWDDL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_OSCWDDL_SHIFT 9 +#define DDR_PHY_DX8SL0OSC_OSCWDDL_MASK 0x00000600U -/*Reserved. Caution, do not write to this register field.*/ +/* +* Reserved. Caution, do not write to this register field. +*/ #undef DDR_PHY_DX8SL0OSC_RESERVED_8_7_DEFVAL #undef DDR_PHY_DX8SL0OSC_RESERVED_8_7_SHIFT #undef DDR_PHY_DX8SL0OSC_RESERVED_8_7_MASK -#define DDR_PHY_DX8SL0OSC_RESERVED_8_7_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL0OSC_RESERVED_8_7_SHIFT 7 -#define DDR_PHY_DX8SL0OSC_RESERVED_8_7_MASK 0x00000180U +#define DDR_PHY_DX8SL0OSC_RESERVED_8_7_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_RESERVED_8_7_SHIFT 7 +#define DDR_PHY_DX8SL0OSC_RESERVED_8_7_MASK 0x00000180U -/*Oscillator Mode Write-Leveling Delay Line Select*/ +/* +* Oscillator Mode Write-Leveling Delay Line Select +*/ #undef DDR_PHY_DX8SL0OSC_OSCWDL_DEFVAL #undef DDR_PHY_DX8SL0OSC_OSCWDL_SHIFT #undef DDR_PHY_DX8SL0OSC_OSCWDL_MASK -#define DDR_PHY_DX8SL0OSC_OSCWDL_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL0OSC_OSCWDL_SHIFT 5 -#define DDR_PHY_DX8SL0OSC_OSCWDL_MASK 0x00000060U +#define DDR_PHY_DX8SL0OSC_OSCWDL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_OSCWDL_SHIFT 5 +#define DDR_PHY_DX8SL0OSC_OSCWDL_MASK 0x00000060U -/*Oscillator Mode Division*/ +/* +* Oscillator Mode Division +*/ #undef DDR_PHY_DX8SL0OSC_OSCDIV_DEFVAL #undef DDR_PHY_DX8SL0OSC_OSCDIV_SHIFT #undef DDR_PHY_DX8SL0OSC_OSCDIV_MASK -#define DDR_PHY_DX8SL0OSC_OSCDIV_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL0OSC_OSCDIV_SHIFT 1 -#define DDR_PHY_DX8SL0OSC_OSCDIV_MASK 0x0000001EU +#define DDR_PHY_DX8SL0OSC_OSCDIV_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_OSCDIV_SHIFT 1 +#define DDR_PHY_DX8SL0OSC_OSCDIV_MASK 0x0000001EU -/*Oscillator Enable*/ +/* +* Oscillator Enable +*/ #undef DDR_PHY_DX8SL0OSC_OSCEN_DEFVAL #undef DDR_PHY_DX8SL0OSC_OSCEN_SHIFT #undef DDR_PHY_DX8SL0OSC_OSCEN_MASK -#define DDR_PHY_DX8SL0OSC_OSCEN_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL0OSC_OSCEN_SHIFT 0 -#define DDR_PHY_DX8SL0OSC_OSCEN_MASK 0x00000001U +#define DDR_PHY_DX8SL0OSC_OSCEN_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_OSCEN_SHIFT 0 +#define DDR_PHY_DX8SL0OSC_OSCEN_MASK 0x00000001U -/*Reserved. Return zeroes on reads.*/ +/* +* PLL Bypass +*/ +#undef DDR_PHY_DX8SL0PLLCR0_PLLBYP_DEFVAL +#undef DDR_PHY_DX8SL0PLLCR0_PLLBYP_SHIFT +#undef DDR_PHY_DX8SL0PLLCR0_PLLBYP_MASK +#define DDR_PHY_DX8SL0PLLCR0_PLLBYP_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL0PLLCR0_PLLBYP_SHIFT 31 +#define DDR_PHY_DX8SL0PLLCR0_PLLBYP_MASK 0x80000000U + +/* +* PLL Reset +*/ +#undef DDR_PHY_DX8SL0PLLCR0_PLLRST_DEFVAL +#undef DDR_PHY_DX8SL0PLLCR0_PLLRST_SHIFT +#undef DDR_PHY_DX8SL0PLLCR0_PLLRST_MASK +#define DDR_PHY_DX8SL0PLLCR0_PLLRST_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL0PLLCR0_PLLRST_SHIFT 30 +#define DDR_PHY_DX8SL0PLLCR0_PLLRST_MASK 0x40000000U + +/* +* PLL Power Down +*/ +#undef DDR_PHY_DX8SL0PLLCR0_PLLPD_DEFVAL +#undef DDR_PHY_DX8SL0PLLCR0_PLLPD_SHIFT +#undef DDR_PHY_DX8SL0PLLCR0_PLLPD_MASK +#define DDR_PHY_DX8SL0PLLCR0_PLLPD_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL0PLLCR0_PLLPD_SHIFT 29 +#define DDR_PHY_DX8SL0PLLCR0_PLLPD_MASK 0x20000000U + +/* +* Reference Stop Mode +*/ +#undef DDR_PHY_DX8SL0PLLCR0_RSTOPM_DEFVAL +#undef DDR_PHY_DX8SL0PLLCR0_RSTOPM_SHIFT +#undef DDR_PHY_DX8SL0PLLCR0_RSTOPM_MASK +#define DDR_PHY_DX8SL0PLLCR0_RSTOPM_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL0PLLCR0_RSTOPM_SHIFT 28 +#define DDR_PHY_DX8SL0PLLCR0_RSTOPM_MASK 0x10000000U + +/* +* PLL Frequency Select +*/ +#undef DDR_PHY_DX8SL0PLLCR0_FRQSEL_DEFVAL +#undef DDR_PHY_DX8SL0PLLCR0_FRQSEL_SHIFT +#undef DDR_PHY_DX8SL0PLLCR0_FRQSEL_MASK +#define DDR_PHY_DX8SL0PLLCR0_FRQSEL_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL0PLLCR0_FRQSEL_SHIFT 24 +#define DDR_PHY_DX8SL0PLLCR0_FRQSEL_MASK 0x0F000000U + +/* +* Relock Mode +*/ +#undef DDR_PHY_DX8SL0PLLCR0_RLOCKM_DEFVAL +#undef DDR_PHY_DX8SL0PLLCR0_RLOCKM_SHIFT +#undef DDR_PHY_DX8SL0PLLCR0_RLOCKM_MASK +#define DDR_PHY_DX8SL0PLLCR0_RLOCKM_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL0PLLCR0_RLOCKM_SHIFT 23 +#define DDR_PHY_DX8SL0PLLCR0_RLOCKM_MASK 0x00800000U + +/* +* Charge Pump Proportional Current Control +*/ +#undef DDR_PHY_DX8SL0PLLCR0_CPPC_DEFVAL +#undef DDR_PHY_DX8SL0PLLCR0_CPPC_SHIFT +#undef DDR_PHY_DX8SL0PLLCR0_CPPC_MASK +#define DDR_PHY_DX8SL0PLLCR0_CPPC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL0PLLCR0_CPPC_SHIFT 17 +#define DDR_PHY_DX8SL0PLLCR0_CPPC_MASK 0x007E0000U + +/* +* Charge Pump Integrating Current Control +*/ +#undef DDR_PHY_DX8SL0PLLCR0_CPIC_DEFVAL +#undef DDR_PHY_DX8SL0PLLCR0_CPIC_SHIFT +#undef DDR_PHY_DX8SL0PLLCR0_CPIC_MASK +#define DDR_PHY_DX8SL0PLLCR0_CPIC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL0PLLCR0_CPIC_SHIFT 13 +#define DDR_PHY_DX8SL0PLLCR0_CPIC_MASK 0x0001E000U + +/* +* Gear Shift +*/ +#undef DDR_PHY_DX8SL0PLLCR0_GSHIFT_DEFVAL +#undef DDR_PHY_DX8SL0PLLCR0_GSHIFT_SHIFT +#undef DDR_PHY_DX8SL0PLLCR0_GSHIFT_MASK +#define DDR_PHY_DX8SL0PLLCR0_GSHIFT_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL0PLLCR0_GSHIFT_SHIFT 12 +#define DDR_PHY_DX8SL0PLLCR0_GSHIFT_MASK 0x00001000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL0PLLCR0_RESERVED_11_9_DEFVAL +#undef DDR_PHY_DX8SL0PLLCR0_RESERVED_11_9_SHIFT +#undef DDR_PHY_DX8SL0PLLCR0_RESERVED_11_9_MASK +#define DDR_PHY_DX8SL0PLLCR0_RESERVED_11_9_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL0PLLCR0_RESERVED_11_9_SHIFT 9 +#define DDR_PHY_DX8SL0PLLCR0_RESERVED_11_9_MASK 0x00000E00U + +/* +* Analog Test Enable (ATOEN) +*/ +#undef DDR_PHY_DX8SL0PLLCR0_ATOEN_DEFVAL +#undef DDR_PHY_DX8SL0PLLCR0_ATOEN_SHIFT +#undef DDR_PHY_DX8SL0PLLCR0_ATOEN_MASK +#define DDR_PHY_DX8SL0PLLCR0_ATOEN_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL0PLLCR0_ATOEN_SHIFT 8 +#define DDR_PHY_DX8SL0PLLCR0_ATOEN_MASK 0x00000100U + +/* +* Analog Test Control +*/ +#undef DDR_PHY_DX8SL0PLLCR0_ATC_DEFVAL +#undef DDR_PHY_DX8SL0PLLCR0_ATC_SHIFT +#undef DDR_PHY_DX8SL0PLLCR0_ATC_MASK +#define DDR_PHY_DX8SL0PLLCR0_ATC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL0PLLCR0_ATC_SHIFT 4 +#define DDR_PHY_DX8SL0PLLCR0_ATC_MASK 0x000000F0U + +/* +* Digital Test Control +*/ +#undef DDR_PHY_DX8SL0PLLCR0_DTC_DEFVAL +#undef DDR_PHY_DX8SL0PLLCR0_DTC_SHIFT +#undef DDR_PHY_DX8SL0PLLCR0_DTC_MASK +#define DDR_PHY_DX8SL0PLLCR0_DTC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL0PLLCR0_DTC_SHIFT 0 +#define DDR_PHY_DX8SL0PLLCR0_DTC_MASK 0x0000000FU + +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_DEFVAL #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_SHIFT #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_MASK -#define DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_SHIFT 25 -#define DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_MASK 0xFE000000U +#define DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_SHIFT 25 +#define DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_MASK 0xFE000000U -/*Read Path Rise-to-Rise Mode*/ +/* +* Read Path Rise-to-Rise Mode +*/ #undef DDR_PHY_DX8SL0DQSCTL_RRRMODE_DEFVAL #undef DDR_PHY_DX8SL0DQSCTL_RRRMODE_SHIFT #undef DDR_PHY_DX8SL0DQSCTL_RRRMODE_MASK -#define DDR_PHY_DX8SL0DQSCTL_RRRMODE_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL0DQSCTL_RRRMODE_SHIFT 24 -#define DDR_PHY_DX8SL0DQSCTL_RRRMODE_MASK 0x01000000U +#define DDR_PHY_DX8SL0DQSCTL_RRRMODE_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL0DQSCTL_RRRMODE_SHIFT 24 +#define DDR_PHY_DX8SL0DQSCTL_RRRMODE_MASK 0x01000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_DEFVAL #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_SHIFT #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_MASK -#define DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_SHIFT 22 -#define DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_MASK 0x00C00000U +#define DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_MASK 0x00C00000U -/*Write Path Rise-to-Rise Mode*/ +/* +* Write Path Rise-to-Rise Mode +*/ #undef DDR_PHY_DX8SL0DQSCTL_WRRMODE_DEFVAL #undef DDR_PHY_DX8SL0DQSCTL_WRRMODE_SHIFT #undef DDR_PHY_DX8SL0DQSCTL_WRRMODE_MASK -#define DDR_PHY_DX8SL0DQSCTL_WRRMODE_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL0DQSCTL_WRRMODE_SHIFT 21 -#define DDR_PHY_DX8SL0DQSCTL_WRRMODE_MASK 0x00200000U +#define DDR_PHY_DX8SL0DQSCTL_WRRMODE_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL0DQSCTL_WRRMODE_SHIFT 21 +#define DDR_PHY_DX8SL0DQSCTL_WRRMODE_MASK 0x00200000U -/*DQS Gate Extension*/ +/* +* DQS Gate Extension +*/ #undef DDR_PHY_DX8SL0DQSCTL_DQSGX_DEFVAL #undef DDR_PHY_DX8SL0DQSCTL_DQSGX_SHIFT #undef DDR_PHY_DX8SL0DQSCTL_DQSGX_MASK -#define DDR_PHY_DX8SL0DQSCTL_DQSGX_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL0DQSCTL_DQSGX_SHIFT 19 -#define DDR_PHY_DX8SL0DQSCTL_DQSGX_MASK 0x00180000U +#define DDR_PHY_DX8SL0DQSCTL_DQSGX_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL0DQSCTL_DQSGX_SHIFT 19 +#define DDR_PHY_DX8SL0DQSCTL_DQSGX_MASK 0x00180000U -/*Low Power PLL Power Down*/ +/* +* Low Power PLL Power Down +*/ #undef DDR_PHY_DX8SL0DQSCTL_LPPLLPD_DEFVAL #undef DDR_PHY_DX8SL0DQSCTL_LPPLLPD_SHIFT #undef DDR_PHY_DX8SL0DQSCTL_LPPLLPD_MASK -#define DDR_PHY_DX8SL0DQSCTL_LPPLLPD_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL0DQSCTL_LPPLLPD_SHIFT 18 -#define DDR_PHY_DX8SL0DQSCTL_LPPLLPD_MASK 0x00040000U +#define DDR_PHY_DX8SL0DQSCTL_LPPLLPD_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL0DQSCTL_LPPLLPD_SHIFT 18 +#define DDR_PHY_DX8SL0DQSCTL_LPPLLPD_MASK 0x00040000U -/*Low Power I/O Power Down*/ +/* +* Low Power I/O Power Down +*/ #undef DDR_PHY_DX8SL0DQSCTL_LPIOPD_DEFVAL #undef DDR_PHY_DX8SL0DQSCTL_LPIOPD_SHIFT #undef DDR_PHY_DX8SL0DQSCTL_LPIOPD_MASK -#define DDR_PHY_DX8SL0DQSCTL_LPIOPD_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL0DQSCTL_LPIOPD_SHIFT 17 -#define DDR_PHY_DX8SL0DQSCTL_LPIOPD_MASK 0x00020000U +#define DDR_PHY_DX8SL0DQSCTL_LPIOPD_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL0DQSCTL_LPIOPD_SHIFT 17 +#define DDR_PHY_DX8SL0DQSCTL_LPIOPD_MASK 0x00020000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_DEFVAL #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_SHIFT #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_MASK -#define DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_SHIFT 15 -#define DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_MASK 0x00018000U +#define DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_SHIFT 15 +#define DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_MASK 0x00018000U -/*QS Counter Enable*/ +/* +* QS Counter Enable +*/ #undef DDR_PHY_DX8SL0DQSCTL_QSCNTEN_DEFVAL #undef DDR_PHY_DX8SL0DQSCTL_QSCNTEN_SHIFT #undef DDR_PHY_DX8SL0DQSCTL_QSCNTEN_MASK -#define DDR_PHY_DX8SL0DQSCTL_QSCNTEN_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL0DQSCTL_QSCNTEN_SHIFT 14 -#define DDR_PHY_DX8SL0DQSCTL_QSCNTEN_MASK 0x00004000U +#define DDR_PHY_DX8SL0DQSCTL_QSCNTEN_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL0DQSCTL_QSCNTEN_SHIFT 14 +#define DDR_PHY_DX8SL0DQSCTL_QSCNTEN_MASK 0x00004000U -/*Unused DQ I/O Mode*/ +/* +* Unused DQ I/O Mode +*/ #undef DDR_PHY_DX8SL0DQSCTL_UDQIOM_DEFVAL #undef DDR_PHY_DX8SL0DQSCTL_UDQIOM_SHIFT #undef DDR_PHY_DX8SL0DQSCTL_UDQIOM_MASK -#define DDR_PHY_DX8SL0DQSCTL_UDQIOM_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL0DQSCTL_UDQIOM_SHIFT 13 -#define DDR_PHY_DX8SL0DQSCTL_UDQIOM_MASK 0x00002000U +#define DDR_PHY_DX8SL0DQSCTL_UDQIOM_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL0DQSCTL_UDQIOM_SHIFT 13 +#define DDR_PHY_DX8SL0DQSCTL_UDQIOM_MASK 0x00002000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_DEFVAL #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_SHIFT #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_MASK -#define DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_SHIFT 10 -#define DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_MASK 0x00001C00U +#define DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_SHIFT 10 +#define DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_MASK 0x00001C00U -/*Data Slew Rate*/ +/* +* Data Slew Rate +*/ #undef DDR_PHY_DX8SL0DQSCTL_DXSR_DEFVAL #undef DDR_PHY_DX8SL0DQSCTL_DXSR_SHIFT #undef DDR_PHY_DX8SL0DQSCTL_DXSR_MASK -#define DDR_PHY_DX8SL0DQSCTL_DXSR_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL0DQSCTL_DXSR_SHIFT 8 -#define DDR_PHY_DX8SL0DQSCTL_DXSR_MASK 0x00000300U +#define DDR_PHY_DX8SL0DQSCTL_DXSR_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL0DQSCTL_DXSR_SHIFT 8 +#define DDR_PHY_DX8SL0DQSCTL_DXSR_MASK 0x00000300U -/*DQS_N Resistor*/ +/* +* DQS_N Resistor +*/ #undef DDR_PHY_DX8SL0DQSCTL_DQSNRES_DEFVAL #undef DDR_PHY_DX8SL0DQSCTL_DQSNRES_SHIFT #undef DDR_PHY_DX8SL0DQSCTL_DQSNRES_MASK -#define DDR_PHY_DX8SL0DQSCTL_DQSNRES_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL0DQSCTL_DQSNRES_SHIFT 4 -#define DDR_PHY_DX8SL0DQSCTL_DQSNRES_MASK 0x000000F0U +#define DDR_PHY_DX8SL0DQSCTL_DQSNRES_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL0DQSCTL_DQSNRES_SHIFT 4 +#define DDR_PHY_DX8SL0DQSCTL_DQSNRES_MASK 0x000000F0U -/*DQS Resistor*/ +/* +* DQS Resistor +*/ #undef DDR_PHY_DX8SL0DQSCTL_DQSRES_DEFVAL #undef DDR_PHY_DX8SL0DQSCTL_DQSRES_SHIFT #undef DDR_PHY_DX8SL0DQSCTL_DQSRES_MASK -#define DDR_PHY_DX8SL0DQSCTL_DQSRES_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL0DQSCTL_DQSRES_SHIFT 0 -#define DDR_PHY_DX8SL0DQSCTL_DQSRES_MASK 0x0000000FU +#define DDR_PHY_DX8SL0DQSCTL_DQSRES_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL0DQSCTL_DQSRES_SHIFT 0 +#define DDR_PHY_DX8SL0DQSCTL_DQSRES_MASK 0x0000000FU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_DEFVAL #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_SHIFT #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_MASK -#define DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_SHIFT 24 -#define DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_MASK 0xFF000000U +#define DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_SHIFT 24 +#define DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_MASK 0xFF000000U -/*Configurable Read Data Enable*/ +/* +* Configurable Read Data Enable +*/ #undef DDR_PHY_DX8SL0DXCTL2_CRDEN_DEFVAL #undef DDR_PHY_DX8SL0DXCTL2_CRDEN_SHIFT #undef DDR_PHY_DX8SL0DXCTL2_CRDEN_MASK -#define DDR_PHY_DX8SL0DXCTL2_CRDEN_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL0DXCTL2_CRDEN_SHIFT 23 -#define DDR_PHY_DX8SL0DXCTL2_CRDEN_MASK 0x00800000U +#define DDR_PHY_DX8SL0DXCTL2_CRDEN_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_CRDEN_SHIFT 23 +#define DDR_PHY_DX8SL0DXCTL2_CRDEN_MASK 0x00800000U -/*OX Extension during Post-amble*/ +/* +* OX Extension during Post-amble +*/ #undef DDR_PHY_DX8SL0DXCTL2_POSOEX_DEFVAL #undef DDR_PHY_DX8SL0DXCTL2_POSOEX_SHIFT #undef DDR_PHY_DX8SL0DXCTL2_POSOEX_MASK -#define DDR_PHY_DX8SL0DXCTL2_POSOEX_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL0DXCTL2_POSOEX_SHIFT 20 -#define DDR_PHY_DX8SL0DXCTL2_POSOEX_MASK 0x00700000U +#define DDR_PHY_DX8SL0DXCTL2_POSOEX_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_POSOEX_SHIFT 20 +#define DDR_PHY_DX8SL0DXCTL2_POSOEX_MASK 0x00700000U -/*OE Extension during Pre-amble*/ +/* +* OE Extension during Pre-amble +*/ #undef DDR_PHY_DX8SL0DXCTL2_PREOEX_DEFVAL #undef DDR_PHY_DX8SL0DXCTL2_PREOEX_SHIFT #undef DDR_PHY_DX8SL0DXCTL2_PREOEX_MASK -#define DDR_PHY_DX8SL0DXCTL2_PREOEX_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL0DXCTL2_PREOEX_SHIFT 18 -#define DDR_PHY_DX8SL0DXCTL2_PREOEX_MASK 0x000C0000U +#define DDR_PHY_DX8SL0DXCTL2_PREOEX_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_PREOEX_SHIFT 18 +#define DDR_PHY_DX8SL0DXCTL2_PREOEX_MASK 0x000C0000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_17_DEFVAL #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_17_SHIFT #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_17_MASK -#define DDR_PHY_DX8SL0DXCTL2_RESERVED_17_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL0DXCTL2_RESERVED_17_SHIFT 17 -#define DDR_PHY_DX8SL0DXCTL2_RESERVED_17_MASK 0x00020000U +#define DDR_PHY_DX8SL0DXCTL2_RESERVED_17_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_RESERVED_17_SHIFT 17 +#define DDR_PHY_DX8SL0DXCTL2_RESERVED_17_MASK 0x00020000U -/*I/O Assisted Gate Select*/ +/* +* I/O Assisted Gate Select +*/ #undef DDR_PHY_DX8SL0DXCTL2_IOAG_DEFVAL #undef DDR_PHY_DX8SL0DXCTL2_IOAG_SHIFT #undef DDR_PHY_DX8SL0DXCTL2_IOAG_MASK -#define DDR_PHY_DX8SL0DXCTL2_IOAG_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL0DXCTL2_IOAG_SHIFT 16 -#define DDR_PHY_DX8SL0DXCTL2_IOAG_MASK 0x00010000U +#define DDR_PHY_DX8SL0DXCTL2_IOAG_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_IOAG_SHIFT 16 +#define DDR_PHY_DX8SL0DXCTL2_IOAG_MASK 0x00010000U -/*I/O Loopback Select*/ +/* +* I/O Loopback Select +*/ #undef DDR_PHY_DX8SL0DXCTL2_IOLB_DEFVAL #undef DDR_PHY_DX8SL0DXCTL2_IOLB_SHIFT #undef DDR_PHY_DX8SL0DXCTL2_IOLB_MASK -#define DDR_PHY_DX8SL0DXCTL2_IOLB_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL0DXCTL2_IOLB_SHIFT 15 -#define DDR_PHY_DX8SL0DXCTL2_IOLB_MASK 0x00008000U +#define DDR_PHY_DX8SL0DXCTL2_IOLB_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_IOLB_SHIFT 15 +#define DDR_PHY_DX8SL0DXCTL2_IOLB_MASK 0x00008000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_DEFVAL #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_SHIFT #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_MASK -#define DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_SHIFT 13 -#define DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_MASK 0x00006000U +#define DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_SHIFT 13 +#define DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_MASK 0x00006000U -/*Low Power Wakeup Threshold*/ +/* +* Low Power Wakeup Threshold +*/ #undef DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_DEFVAL #undef DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_SHIFT #undef DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_MASK -#define DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_SHIFT 9 -#define DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_MASK 0x00001E00U +#define DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_SHIFT 9 +#define DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_MASK 0x00001E00U -/*Read Data Bus Inversion Enable*/ +/* +* Read Data Bus Inversion Enable +*/ #undef DDR_PHY_DX8SL0DXCTL2_RDBI_DEFVAL #undef DDR_PHY_DX8SL0DXCTL2_RDBI_SHIFT #undef DDR_PHY_DX8SL0DXCTL2_RDBI_MASK -#define DDR_PHY_DX8SL0DXCTL2_RDBI_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL0DXCTL2_RDBI_SHIFT 8 -#define DDR_PHY_DX8SL0DXCTL2_RDBI_MASK 0x00000100U +#define DDR_PHY_DX8SL0DXCTL2_RDBI_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_RDBI_SHIFT 8 +#define DDR_PHY_DX8SL0DXCTL2_RDBI_MASK 0x00000100U -/*Write Data Bus Inversion Enable*/ +/* +* Write Data Bus Inversion Enable +*/ #undef DDR_PHY_DX8SL0DXCTL2_WDBI_DEFVAL #undef DDR_PHY_DX8SL0DXCTL2_WDBI_SHIFT #undef DDR_PHY_DX8SL0DXCTL2_WDBI_MASK -#define DDR_PHY_DX8SL0DXCTL2_WDBI_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL0DXCTL2_WDBI_SHIFT 7 -#define DDR_PHY_DX8SL0DXCTL2_WDBI_MASK 0x00000080U +#define DDR_PHY_DX8SL0DXCTL2_WDBI_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_WDBI_SHIFT 7 +#define DDR_PHY_DX8SL0DXCTL2_WDBI_MASK 0x00000080U -/*PUB Read FIFO Bypass*/ +/* +* PUB Read FIFO Bypass +*/ #undef DDR_PHY_DX8SL0DXCTL2_PRFBYP_DEFVAL #undef DDR_PHY_DX8SL0DXCTL2_PRFBYP_SHIFT #undef DDR_PHY_DX8SL0DXCTL2_PRFBYP_MASK -#define DDR_PHY_DX8SL0DXCTL2_PRFBYP_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL0DXCTL2_PRFBYP_SHIFT 6 -#define DDR_PHY_DX8SL0DXCTL2_PRFBYP_MASK 0x00000040U +#define DDR_PHY_DX8SL0DXCTL2_PRFBYP_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_PRFBYP_SHIFT 6 +#define DDR_PHY_DX8SL0DXCTL2_PRFBYP_MASK 0x00000040U -/*DATX8 Receive FIFO Read Mode*/ +/* +* DATX8 Receive FIFO Read Mode +*/ #undef DDR_PHY_DX8SL0DXCTL2_RDMODE_DEFVAL #undef DDR_PHY_DX8SL0DXCTL2_RDMODE_SHIFT #undef DDR_PHY_DX8SL0DXCTL2_RDMODE_MASK -#define DDR_PHY_DX8SL0DXCTL2_RDMODE_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL0DXCTL2_RDMODE_SHIFT 4 -#define DDR_PHY_DX8SL0DXCTL2_RDMODE_MASK 0x00000030U +#define DDR_PHY_DX8SL0DXCTL2_RDMODE_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_RDMODE_SHIFT 4 +#define DDR_PHY_DX8SL0DXCTL2_RDMODE_MASK 0x00000030U -/*Disables the Read FIFO Reset*/ +/* +* Disables the Read FIFO Reset +*/ #undef DDR_PHY_DX8SL0DXCTL2_DISRST_DEFVAL #undef DDR_PHY_DX8SL0DXCTL2_DISRST_SHIFT #undef DDR_PHY_DX8SL0DXCTL2_DISRST_MASK -#define DDR_PHY_DX8SL0DXCTL2_DISRST_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL0DXCTL2_DISRST_SHIFT 3 -#define DDR_PHY_DX8SL0DXCTL2_DISRST_MASK 0x00000008U +#define DDR_PHY_DX8SL0DXCTL2_DISRST_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_DISRST_SHIFT 3 +#define DDR_PHY_DX8SL0DXCTL2_DISRST_MASK 0x00000008U -/*Read DQS Gate I/O Loopback*/ +/* +* Read DQS Gate I/O Loopback +*/ #undef DDR_PHY_DX8SL0DXCTL2_DQSGLB_DEFVAL #undef DDR_PHY_DX8SL0DXCTL2_DQSGLB_SHIFT #undef DDR_PHY_DX8SL0DXCTL2_DQSGLB_MASK -#define DDR_PHY_DX8SL0DXCTL2_DQSGLB_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL0DXCTL2_DQSGLB_SHIFT 1 -#define DDR_PHY_DX8SL0DXCTL2_DQSGLB_MASK 0x00000006U +#define DDR_PHY_DX8SL0DXCTL2_DQSGLB_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_DQSGLB_SHIFT 1 +#define DDR_PHY_DX8SL0DXCTL2_DQSGLB_MASK 0x00000006U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_0_DEFVAL #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_0_SHIFT #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_0_MASK -#define DDR_PHY_DX8SL0DXCTL2_RESERVED_0_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL0DXCTL2_RESERVED_0_SHIFT 0 -#define DDR_PHY_DX8SL0DXCTL2_RESERVED_0_MASK 0x00000001U +#define DDR_PHY_DX8SL0DXCTL2_RESERVED_0_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_RESERVED_0_SHIFT 0 +#define DDR_PHY_DX8SL0DXCTL2_RESERVED_0_MASK 0x00000001U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL0IOCR_RESERVED_31_DEFVAL #undef DDR_PHY_DX8SL0IOCR_RESERVED_31_SHIFT #undef DDR_PHY_DX8SL0IOCR_RESERVED_31_MASK -#define DDR_PHY_DX8SL0IOCR_RESERVED_31_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL0IOCR_RESERVED_31_SHIFT 31 -#define DDR_PHY_DX8SL0IOCR_RESERVED_31_MASK 0x80000000U +#define DDR_PHY_DX8SL0IOCR_RESERVED_31_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL0IOCR_RESERVED_31_SHIFT 31 +#define DDR_PHY_DX8SL0IOCR_RESERVED_31_MASK 0x80000000U -/*PVREF_DAC REFSEL range select*/ +/* +* PVREF_DAC REFSEL range select +*/ #undef DDR_PHY_DX8SL0IOCR_DXDACRANGE_DEFVAL #undef DDR_PHY_DX8SL0IOCR_DXDACRANGE_SHIFT #undef DDR_PHY_DX8SL0IOCR_DXDACRANGE_MASK -#define DDR_PHY_DX8SL0IOCR_DXDACRANGE_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL0IOCR_DXDACRANGE_SHIFT 28 -#define DDR_PHY_DX8SL0IOCR_DXDACRANGE_MASK 0x70000000U +#define DDR_PHY_DX8SL0IOCR_DXDACRANGE_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL0IOCR_DXDACRANGE_SHIFT 28 +#define DDR_PHY_DX8SL0IOCR_DXDACRANGE_MASK 0x70000000U -/*IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring*/ +/* +* IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring +*/ #undef DDR_PHY_DX8SL0IOCR_DXVREFIOM_DEFVAL #undef DDR_PHY_DX8SL0IOCR_DXVREFIOM_SHIFT #undef DDR_PHY_DX8SL0IOCR_DXVREFIOM_MASK -#define DDR_PHY_DX8SL0IOCR_DXVREFIOM_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL0IOCR_DXVREFIOM_SHIFT 25 -#define DDR_PHY_DX8SL0IOCR_DXVREFIOM_MASK 0x0E000000U +#define DDR_PHY_DX8SL0IOCR_DXVREFIOM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL0IOCR_DXVREFIOM_SHIFT 25 +#define DDR_PHY_DX8SL0IOCR_DXVREFIOM_MASK 0x0E000000U -/*DX IO Mode*/ +/* +* DX IO Mode +*/ #undef DDR_PHY_DX8SL0IOCR_DXIOM_DEFVAL #undef DDR_PHY_DX8SL0IOCR_DXIOM_SHIFT #undef DDR_PHY_DX8SL0IOCR_DXIOM_MASK -#define DDR_PHY_DX8SL0IOCR_DXIOM_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL0IOCR_DXIOM_SHIFT 22 -#define DDR_PHY_DX8SL0IOCR_DXIOM_MASK 0x01C00000U +#define DDR_PHY_DX8SL0IOCR_DXIOM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL0IOCR_DXIOM_SHIFT 22 +#define DDR_PHY_DX8SL0IOCR_DXIOM_MASK 0x01C00000U -/*DX IO Transmitter Mode*/ +/* +* DX IO Transmitter Mode +*/ #undef DDR_PHY_DX8SL0IOCR_DXTXM_DEFVAL #undef DDR_PHY_DX8SL0IOCR_DXTXM_SHIFT #undef DDR_PHY_DX8SL0IOCR_DXTXM_MASK -#define DDR_PHY_DX8SL0IOCR_DXTXM_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL0IOCR_DXTXM_SHIFT 11 -#define DDR_PHY_DX8SL0IOCR_DXTXM_MASK 0x003FF800U +#define DDR_PHY_DX8SL0IOCR_DXTXM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL0IOCR_DXTXM_SHIFT 11 +#define DDR_PHY_DX8SL0IOCR_DXTXM_MASK 0x003FF800U -/*DX IO Receiver Mode*/ +/* +* DX IO Receiver Mode +*/ #undef DDR_PHY_DX8SL0IOCR_DXRXM_DEFVAL #undef DDR_PHY_DX8SL0IOCR_DXRXM_SHIFT #undef DDR_PHY_DX8SL0IOCR_DXRXM_MASK -#define DDR_PHY_DX8SL0IOCR_DXRXM_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL0IOCR_DXRXM_SHIFT 0 -#define DDR_PHY_DX8SL0IOCR_DXRXM_MASK 0x000007FFU +#define DDR_PHY_DX8SL0IOCR_DXRXM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL0IOCR_DXRXM_SHIFT 0 +#define DDR_PHY_DX8SL0IOCR_DXRXM_MASK 0x000007FFU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL1OSC_RESERVED_31_30_DEFVAL #undef DDR_PHY_DX8SL1OSC_RESERVED_31_30_SHIFT #undef DDR_PHY_DX8SL1OSC_RESERVED_31_30_MASK -#define DDR_PHY_DX8SL1OSC_RESERVED_31_30_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL1OSC_RESERVED_31_30_SHIFT 30 -#define DDR_PHY_DX8SL1OSC_RESERVED_31_30_MASK 0xC0000000U +#define DDR_PHY_DX8SL1OSC_RESERVED_31_30_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX8SL1OSC_RESERVED_31_30_MASK 0xC0000000U -/*Enable Clock Gating for DX ddr_clk*/ +/* +* Enable Clock Gating for DX ddr_clk +*/ #undef DDR_PHY_DX8SL1OSC_GATEDXRDCLK_DEFVAL #undef DDR_PHY_DX8SL1OSC_GATEDXRDCLK_SHIFT #undef DDR_PHY_DX8SL1OSC_GATEDXRDCLK_MASK -#define DDR_PHY_DX8SL1OSC_GATEDXRDCLK_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL1OSC_GATEDXRDCLK_SHIFT 28 -#define DDR_PHY_DX8SL1OSC_GATEDXRDCLK_MASK 0x30000000U +#define DDR_PHY_DX8SL1OSC_GATEDXRDCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_GATEDXRDCLK_SHIFT 28 +#define DDR_PHY_DX8SL1OSC_GATEDXRDCLK_MASK 0x30000000U -/*Enable Clock Gating for DX ctl_rd_clk*/ +/* +* Enable Clock Gating for DX ctl_rd_clk +*/ #undef DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_DEFVAL #undef DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_SHIFT #undef DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_MASK -#define DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_SHIFT 26 -#define DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_MASK 0x0C000000U +#define DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_SHIFT 26 +#define DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_MASK 0x0C000000U -/*Enable Clock Gating for DX ctl_clk*/ +/* +* Enable Clock Gating for DX ctl_clk +*/ #undef DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_DEFVAL #undef DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_SHIFT #undef DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_MASK -#define DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_SHIFT 24 -#define DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_MASK 0x03000000U +#define DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_SHIFT 24 +#define DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_MASK 0x03000000U -/*Selects the level to which clocks will be stalled when clock gating is enabled.*/ +/* +* Selects the level to which clocks will be stalled when clock gating is e + * nabled. +*/ #undef DDR_PHY_DX8SL1OSC_CLKLEVEL_DEFVAL #undef DDR_PHY_DX8SL1OSC_CLKLEVEL_SHIFT #undef DDR_PHY_DX8SL1OSC_CLKLEVEL_MASK -#define DDR_PHY_DX8SL1OSC_CLKLEVEL_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL1OSC_CLKLEVEL_SHIFT 22 -#define DDR_PHY_DX8SL1OSC_CLKLEVEL_MASK 0x00C00000U +#define DDR_PHY_DX8SL1OSC_CLKLEVEL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_CLKLEVEL_SHIFT 22 +#define DDR_PHY_DX8SL1OSC_CLKLEVEL_MASK 0x00C00000U -/*Loopback Mode*/ +/* +* Loopback Mode +*/ #undef DDR_PHY_DX8SL1OSC_LBMODE_DEFVAL #undef DDR_PHY_DX8SL1OSC_LBMODE_SHIFT #undef DDR_PHY_DX8SL1OSC_LBMODE_MASK -#define DDR_PHY_DX8SL1OSC_LBMODE_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL1OSC_LBMODE_SHIFT 21 -#define DDR_PHY_DX8SL1OSC_LBMODE_MASK 0x00200000U +#define DDR_PHY_DX8SL1OSC_LBMODE_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_LBMODE_SHIFT 21 +#define DDR_PHY_DX8SL1OSC_LBMODE_MASK 0x00200000U -/*Load GSDQS LCDL with 2x the calibrated GSDQSPRD value*/ +/* +* Load GSDQS LCDL with 2x the calibrated GSDQSPRD value +*/ #undef DDR_PHY_DX8SL1OSC_LBGSDQS_DEFVAL #undef DDR_PHY_DX8SL1OSC_LBGSDQS_SHIFT #undef DDR_PHY_DX8SL1OSC_LBGSDQS_MASK -#define DDR_PHY_DX8SL1OSC_LBGSDQS_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL1OSC_LBGSDQS_SHIFT 20 -#define DDR_PHY_DX8SL1OSC_LBGSDQS_MASK 0x00100000U +#define DDR_PHY_DX8SL1OSC_LBGSDQS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_LBGSDQS_SHIFT 20 +#define DDR_PHY_DX8SL1OSC_LBGSDQS_MASK 0x00100000U -/*Loopback DQS Gating*/ +/* +* Loopback DQS Gating +*/ #undef DDR_PHY_DX8SL1OSC_LBGDQS_DEFVAL #undef DDR_PHY_DX8SL1OSC_LBGDQS_SHIFT #undef DDR_PHY_DX8SL1OSC_LBGDQS_MASK -#define DDR_PHY_DX8SL1OSC_LBGDQS_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL1OSC_LBGDQS_SHIFT 18 -#define DDR_PHY_DX8SL1OSC_LBGDQS_MASK 0x000C0000U +#define DDR_PHY_DX8SL1OSC_LBGDQS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_LBGDQS_SHIFT 18 +#define DDR_PHY_DX8SL1OSC_LBGDQS_MASK 0x000C0000U -/*Loopback DQS Shift*/ +/* +* Loopback DQS Shift +*/ #undef DDR_PHY_DX8SL1OSC_LBDQSS_DEFVAL #undef DDR_PHY_DX8SL1OSC_LBDQSS_SHIFT #undef DDR_PHY_DX8SL1OSC_LBDQSS_MASK -#define DDR_PHY_DX8SL1OSC_LBDQSS_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL1OSC_LBDQSS_SHIFT 17 -#define DDR_PHY_DX8SL1OSC_LBDQSS_MASK 0x00020000U +#define DDR_PHY_DX8SL1OSC_LBDQSS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_LBDQSS_SHIFT 17 +#define DDR_PHY_DX8SL1OSC_LBDQSS_MASK 0x00020000U -/*PHY High-Speed Reset*/ +/* +* PHY High-Speed Reset +*/ #undef DDR_PHY_DX8SL1OSC_PHYHRST_DEFVAL #undef DDR_PHY_DX8SL1OSC_PHYHRST_SHIFT #undef DDR_PHY_DX8SL1OSC_PHYHRST_MASK -#define DDR_PHY_DX8SL1OSC_PHYHRST_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL1OSC_PHYHRST_SHIFT 16 -#define DDR_PHY_DX8SL1OSC_PHYHRST_MASK 0x00010000U +#define DDR_PHY_DX8SL1OSC_PHYHRST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_PHYHRST_SHIFT 16 +#define DDR_PHY_DX8SL1OSC_PHYHRST_MASK 0x00010000U -/*PHY FIFO Reset*/ +/* +* PHY FIFO Reset +*/ #undef DDR_PHY_DX8SL1OSC_PHYFRST_DEFVAL #undef DDR_PHY_DX8SL1OSC_PHYFRST_SHIFT #undef DDR_PHY_DX8SL1OSC_PHYFRST_MASK -#define DDR_PHY_DX8SL1OSC_PHYFRST_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL1OSC_PHYFRST_SHIFT 15 -#define DDR_PHY_DX8SL1OSC_PHYFRST_MASK 0x00008000U +#define DDR_PHY_DX8SL1OSC_PHYFRST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_PHYFRST_SHIFT 15 +#define DDR_PHY_DX8SL1OSC_PHYFRST_MASK 0x00008000U -/*Delay Line Test Start*/ +/* +* Delay Line Test Start +*/ #undef DDR_PHY_DX8SL1OSC_DLTST_DEFVAL #undef DDR_PHY_DX8SL1OSC_DLTST_SHIFT #undef DDR_PHY_DX8SL1OSC_DLTST_MASK -#define DDR_PHY_DX8SL1OSC_DLTST_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL1OSC_DLTST_SHIFT 14 -#define DDR_PHY_DX8SL1OSC_DLTST_MASK 0x00004000U +#define DDR_PHY_DX8SL1OSC_DLTST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_DLTST_SHIFT 14 +#define DDR_PHY_DX8SL1OSC_DLTST_MASK 0x00004000U -/*Delay Line Test Mode*/ +/* +* Delay Line Test Mode +*/ #undef DDR_PHY_DX8SL1OSC_DLTMODE_DEFVAL #undef DDR_PHY_DX8SL1OSC_DLTMODE_SHIFT #undef DDR_PHY_DX8SL1OSC_DLTMODE_MASK -#define DDR_PHY_DX8SL1OSC_DLTMODE_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL1OSC_DLTMODE_SHIFT 13 -#define DDR_PHY_DX8SL1OSC_DLTMODE_MASK 0x00002000U +#define DDR_PHY_DX8SL1OSC_DLTMODE_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_DLTMODE_SHIFT 13 +#define DDR_PHY_DX8SL1OSC_DLTMODE_MASK 0x00002000U -/*Reserved. Caution, do not write to this register field.*/ +/* +* Reserved. Caution, do not write to this register field. +*/ #undef DDR_PHY_DX8SL1OSC_RESERVED_12_11_DEFVAL #undef DDR_PHY_DX8SL1OSC_RESERVED_12_11_SHIFT #undef DDR_PHY_DX8SL1OSC_RESERVED_12_11_MASK -#define DDR_PHY_DX8SL1OSC_RESERVED_12_11_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL1OSC_RESERVED_12_11_SHIFT 11 -#define DDR_PHY_DX8SL1OSC_RESERVED_12_11_MASK 0x00001800U +#define DDR_PHY_DX8SL1OSC_RESERVED_12_11_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_RESERVED_12_11_SHIFT 11 +#define DDR_PHY_DX8SL1OSC_RESERVED_12_11_MASK 0x00001800U -/*Oscillator Mode Write-Data Delay Line Select*/ +/* +* Oscillator Mode Write-Data Delay Line Select +*/ #undef DDR_PHY_DX8SL1OSC_OSCWDDL_DEFVAL #undef DDR_PHY_DX8SL1OSC_OSCWDDL_SHIFT #undef DDR_PHY_DX8SL1OSC_OSCWDDL_MASK -#define DDR_PHY_DX8SL1OSC_OSCWDDL_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL1OSC_OSCWDDL_SHIFT 9 -#define DDR_PHY_DX8SL1OSC_OSCWDDL_MASK 0x00000600U +#define DDR_PHY_DX8SL1OSC_OSCWDDL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_OSCWDDL_SHIFT 9 +#define DDR_PHY_DX8SL1OSC_OSCWDDL_MASK 0x00000600U -/*Reserved. Caution, do not write to this register field.*/ +/* +* Reserved. Caution, do not write to this register field. +*/ #undef DDR_PHY_DX8SL1OSC_RESERVED_8_7_DEFVAL #undef DDR_PHY_DX8SL1OSC_RESERVED_8_7_SHIFT #undef DDR_PHY_DX8SL1OSC_RESERVED_8_7_MASK -#define DDR_PHY_DX8SL1OSC_RESERVED_8_7_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL1OSC_RESERVED_8_7_SHIFT 7 -#define DDR_PHY_DX8SL1OSC_RESERVED_8_7_MASK 0x00000180U +#define DDR_PHY_DX8SL1OSC_RESERVED_8_7_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_RESERVED_8_7_SHIFT 7 +#define DDR_PHY_DX8SL1OSC_RESERVED_8_7_MASK 0x00000180U -/*Oscillator Mode Write-Leveling Delay Line Select*/ +/* +* Oscillator Mode Write-Leveling Delay Line Select +*/ #undef DDR_PHY_DX8SL1OSC_OSCWDL_DEFVAL #undef DDR_PHY_DX8SL1OSC_OSCWDL_SHIFT #undef DDR_PHY_DX8SL1OSC_OSCWDL_MASK -#define DDR_PHY_DX8SL1OSC_OSCWDL_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL1OSC_OSCWDL_SHIFT 5 -#define DDR_PHY_DX8SL1OSC_OSCWDL_MASK 0x00000060U +#define DDR_PHY_DX8SL1OSC_OSCWDL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_OSCWDL_SHIFT 5 +#define DDR_PHY_DX8SL1OSC_OSCWDL_MASK 0x00000060U -/*Oscillator Mode Division*/ +/* +* Oscillator Mode Division +*/ #undef DDR_PHY_DX8SL1OSC_OSCDIV_DEFVAL #undef DDR_PHY_DX8SL1OSC_OSCDIV_SHIFT #undef DDR_PHY_DX8SL1OSC_OSCDIV_MASK -#define DDR_PHY_DX8SL1OSC_OSCDIV_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL1OSC_OSCDIV_SHIFT 1 -#define DDR_PHY_DX8SL1OSC_OSCDIV_MASK 0x0000001EU +#define DDR_PHY_DX8SL1OSC_OSCDIV_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_OSCDIV_SHIFT 1 +#define DDR_PHY_DX8SL1OSC_OSCDIV_MASK 0x0000001EU -/*Oscillator Enable*/ +/* +* Oscillator Enable +*/ #undef DDR_PHY_DX8SL1OSC_OSCEN_DEFVAL #undef DDR_PHY_DX8SL1OSC_OSCEN_SHIFT #undef DDR_PHY_DX8SL1OSC_OSCEN_MASK -#define DDR_PHY_DX8SL1OSC_OSCEN_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL1OSC_OSCEN_SHIFT 0 -#define DDR_PHY_DX8SL1OSC_OSCEN_MASK 0x00000001U +#define DDR_PHY_DX8SL1OSC_OSCEN_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_OSCEN_SHIFT 0 +#define DDR_PHY_DX8SL1OSC_OSCEN_MASK 0x00000001U -/*Reserved. Return zeroes on reads.*/ +/* +* PLL Bypass +*/ +#undef DDR_PHY_DX8SL1PLLCR0_PLLBYP_DEFVAL +#undef DDR_PHY_DX8SL1PLLCR0_PLLBYP_SHIFT +#undef DDR_PHY_DX8SL1PLLCR0_PLLBYP_MASK +#define DDR_PHY_DX8SL1PLLCR0_PLLBYP_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL1PLLCR0_PLLBYP_SHIFT 31 +#define DDR_PHY_DX8SL1PLLCR0_PLLBYP_MASK 0x80000000U + +/* +* PLL Reset +*/ +#undef DDR_PHY_DX8SL1PLLCR0_PLLRST_DEFVAL +#undef DDR_PHY_DX8SL1PLLCR0_PLLRST_SHIFT +#undef DDR_PHY_DX8SL1PLLCR0_PLLRST_MASK +#define DDR_PHY_DX8SL1PLLCR0_PLLRST_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL1PLLCR0_PLLRST_SHIFT 30 +#define DDR_PHY_DX8SL1PLLCR0_PLLRST_MASK 0x40000000U + +/* +* PLL Power Down +*/ +#undef DDR_PHY_DX8SL1PLLCR0_PLLPD_DEFVAL +#undef DDR_PHY_DX8SL1PLLCR0_PLLPD_SHIFT +#undef DDR_PHY_DX8SL1PLLCR0_PLLPD_MASK +#define DDR_PHY_DX8SL1PLLCR0_PLLPD_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL1PLLCR0_PLLPD_SHIFT 29 +#define DDR_PHY_DX8SL1PLLCR0_PLLPD_MASK 0x20000000U + +/* +* Reference Stop Mode +*/ +#undef DDR_PHY_DX8SL1PLLCR0_RSTOPM_DEFVAL +#undef DDR_PHY_DX8SL1PLLCR0_RSTOPM_SHIFT +#undef DDR_PHY_DX8SL1PLLCR0_RSTOPM_MASK +#define DDR_PHY_DX8SL1PLLCR0_RSTOPM_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL1PLLCR0_RSTOPM_SHIFT 28 +#define DDR_PHY_DX8SL1PLLCR0_RSTOPM_MASK 0x10000000U + +/* +* PLL Frequency Select +*/ +#undef DDR_PHY_DX8SL1PLLCR0_FRQSEL_DEFVAL +#undef DDR_PHY_DX8SL1PLLCR0_FRQSEL_SHIFT +#undef DDR_PHY_DX8SL1PLLCR0_FRQSEL_MASK +#define DDR_PHY_DX8SL1PLLCR0_FRQSEL_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL1PLLCR0_FRQSEL_SHIFT 24 +#define DDR_PHY_DX8SL1PLLCR0_FRQSEL_MASK 0x0F000000U + +/* +* Relock Mode +*/ +#undef DDR_PHY_DX8SL1PLLCR0_RLOCKM_DEFVAL +#undef DDR_PHY_DX8SL1PLLCR0_RLOCKM_SHIFT +#undef DDR_PHY_DX8SL1PLLCR0_RLOCKM_MASK +#define DDR_PHY_DX8SL1PLLCR0_RLOCKM_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL1PLLCR0_RLOCKM_SHIFT 23 +#define DDR_PHY_DX8SL1PLLCR0_RLOCKM_MASK 0x00800000U + +/* +* Charge Pump Proportional Current Control +*/ +#undef DDR_PHY_DX8SL1PLLCR0_CPPC_DEFVAL +#undef DDR_PHY_DX8SL1PLLCR0_CPPC_SHIFT +#undef DDR_PHY_DX8SL1PLLCR0_CPPC_MASK +#define DDR_PHY_DX8SL1PLLCR0_CPPC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL1PLLCR0_CPPC_SHIFT 17 +#define DDR_PHY_DX8SL1PLLCR0_CPPC_MASK 0x007E0000U + +/* +* Charge Pump Integrating Current Control +*/ +#undef DDR_PHY_DX8SL1PLLCR0_CPIC_DEFVAL +#undef DDR_PHY_DX8SL1PLLCR0_CPIC_SHIFT +#undef DDR_PHY_DX8SL1PLLCR0_CPIC_MASK +#define DDR_PHY_DX8SL1PLLCR0_CPIC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL1PLLCR0_CPIC_SHIFT 13 +#define DDR_PHY_DX8SL1PLLCR0_CPIC_MASK 0x0001E000U + +/* +* Gear Shift +*/ +#undef DDR_PHY_DX8SL1PLLCR0_GSHIFT_DEFVAL +#undef DDR_PHY_DX8SL1PLLCR0_GSHIFT_SHIFT +#undef DDR_PHY_DX8SL1PLLCR0_GSHIFT_MASK +#define DDR_PHY_DX8SL1PLLCR0_GSHIFT_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL1PLLCR0_GSHIFT_SHIFT 12 +#define DDR_PHY_DX8SL1PLLCR0_GSHIFT_MASK 0x00001000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL1PLLCR0_RESERVED_11_9_DEFVAL +#undef DDR_PHY_DX8SL1PLLCR0_RESERVED_11_9_SHIFT +#undef DDR_PHY_DX8SL1PLLCR0_RESERVED_11_9_MASK +#define DDR_PHY_DX8SL1PLLCR0_RESERVED_11_9_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL1PLLCR0_RESERVED_11_9_SHIFT 9 +#define DDR_PHY_DX8SL1PLLCR0_RESERVED_11_9_MASK 0x00000E00U + +/* +* Analog Test Enable (ATOEN) +*/ +#undef DDR_PHY_DX8SL1PLLCR0_ATOEN_DEFVAL +#undef DDR_PHY_DX8SL1PLLCR0_ATOEN_SHIFT +#undef DDR_PHY_DX8SL1PLLCR0_ATOEN_MASK +#define DDR_PHY_DX8SL1PLLCR0_ATOEN_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL1PLLCR0_ATOEN_SHIFT 8 +#define DDR_PHY_DX8SL1PLLCR0_ATOEN_MASK 0x00000100U + +/* +* Analog Test Control +*/ +#undef DDR_PHY_DX8SL1PLLCR0_ATC_DEFVAL +#undef DDR_PHY_DX8SL1PLLCR0_ATC_SHIFT +#undef DDR_PHY_DX8SL1PLLCR0_ATC_MASK +#define DDR_PHY_DX8SL1PLLCR0_ATC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL1PLLCR0_ATC_SHIFT 4 +#define DDR_PHY_DX8SL1PLLCR0_ATC_MASK 0x000000F0U + +/* +* Digital Test Control +*/ +#undef DDR_PHY_DX8SL1PLLCR0_DTC_DEFVAL +#undef DDR_PHY_DX8SL1PLLCR0_DTC_SHIFT +#undef DDR_PHY_DX8SL1PLLCR0_DTC_MASK +#define DDR_PHY_DX8SL1PLLCR0_DTC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL1PLLCR0_DTC_SHIFT 0 +#define DDR_PHY_DX8SL1PLLCR0_DTC_MASK 0x0000000FU + +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_DEFVAL #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_SHIFT #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_MASK -#define DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_SHIFT 25 -#define DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_MASK 0xFE000000U +#define DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_SHIFT 25 +#define DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_MASK 0xFE000000U -/*Read Path Rise-to-Rise Mode*/ +/* +* Read Path Rise-to-Rise Mode +*/ #undef DDR_PHY_DX8SL1DQSCTL_RRRMODE_DEFVAL #undef DDR_PHY_DX8SL1DQSCTL_RRRMODE_SHIFT #undef DDR_PHY_DX8SL1DQSCTL_RRRMODE_MASK -#define DDR_PHY_DX8SL1DQSCTL_RRRMODE_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL1DQSCTL_RRRMODE_SHIFT 24 -#define DDR_PHY_DX8SL1DQSCTL_RRRMODE_MASK 0x01000000U +#define DDR_PHY_DX8SL1DQSCTL_RRRMODE_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL1DQSCTL_RRRMODE_SHIFT 24 +#define DDR_PHY_DX8SL1DQSCTL_RRRMODE_MASK 0x01000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_DEFVAL #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_SHIFT #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_MASK -#define DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_SHIFT 22 -#define DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_MASK 0x00C00000U +#define DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_MASK 0x00C00000U -/*Write Path Rise-to-Rise Mode*/ +/* +* Write Path Rise-to-Rise Mode +*/ #undef DDR_PHY_DX8SL1DQSCTL_WRRMODE_DEFVAL #undef DDR_PHY_DX8SL1DQSCTL_WRRMODE_SHIFT #undef DDR_PHY_DX8SL1DQSCTL_WRRMODE_MASK -#define DDR_PHY_DX8SL1DQSCTL_WRRMODE_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL1DQSCTL_WRRMODE_SHIFT 21 -#define DDR_PHY_DX8SL1DQSCTL_WRRMODE_MASK 0x00200000U +#define DDR_PHY_DX8SL1DQSCTL_WRRMODE_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL1DQSCTL_WRRMODE_SHIFT 21 +#define DDR_PHY_DX8SL1DQSCTL_WRRMODE_MASK 0x00200000U -/*DQS Gate Extension*/ +/* +* DQS Gate Extension +*/ #undef DDR_PHY_DX8SL1DQSCTL_DQSGX_DEFVAL #undef DDR_PHY_DX8SL1DQSCTL_DQSGX_SHIFT #undef DDR_PHY_DX8SL1DQSCTL_DQSGX_MASK -#define DDR_PHY_DX8SL1DQSCTL_DQSGX_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL1DQSCTL_DQSGX_SHIFT 19 -#define DDR_PHY_DX8SL1DQSCTL_DQSGX_MASK 0x00180000U +#define DDR_PHY_DX8SL1DQSCTL_DQSGX_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL1DQSCTL_DQSGX_SHIFT 19 +#define DDR_PHY_DX8SL1DQSCTL_DQSGX_MASK 0x00180000U -/*Low Power PLL Power Down*/ +/* +* Low Power PLL Power Down +*/ #undef DDR_PHY_DX8SL1DQSCTL_LPPLLPD_DEFVAL #undef DDR_PHY_DX8SL1DQSCTL_LPPLLPD_SHIFT #undef DDR_PHY_DX8SL1DQSCTL_LPPLLPD_MASK -#define DDR_PHY_DX8SL1DQSCTL_LPPLLPD_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL1DQSCTL_LPPLLPD_SHIFT 18 -#define DDR_PHY_DX8SL1DQSCTL_LPPLLPD_MASK 0x00040000U +#define DDR_PHY_DX8SL1DQSCTL_LPPLLPD_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL1DQSCTL_LPPLLPD_SHIFT 18 +#define DDR_PHY_DX8SL1DQSCTL_LPPLLPD_MASK 0x00040000U -/*Low Power I/O Power Down*/ +/* +* Low Power I/O Power Down +*/ #undef DDR_PHY_DX8SL1DQSCTL_LPIOPD_DEFVAL #undef DDR_PHY_DX8SL1DQSCTL_LPIOPD_SHIFT #undef DDR_PHY_DX8SL1DQSCTL_LPIOPD_MASK -#define DDR_PHY_DX8SL1DQSCTL_LPIOPD_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL1DQSCTL_LPIOPD_SHIFT 17 -#define DDR_PHY_DX8SL1DQSCTL_LPIOPD_MASK 0x00020000U +#define DDR_PHY_DX8SL1DQSCTL_LPIOPD_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL1DQSCTL_LPIOPD_SHIFT 17 +#define DDR_PHY_DX8SL1DQSCTL_LPIOPD_MASK 0x00020000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_DEFVAL #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_SHIFT #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_MASK -#define DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_SHIFT 15 -#define DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_MASK 0x00018000U +#define DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_SHIFT 15 +#define DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_MASK 0x00018000U -/*QS Counter Enable*/ +/* +* QS Counter Enable +*/ #undef DDR_PHY_DX8SL1DQSCTL_QSCNTEN_DEFVAL #undef DDR_PHY_DX8SL1DQSCTL_QSCNTEN_SHIFT #undef DDR_PHY_DX8SL1DQSCTL_QSCNTEN_MASK -#define DDR_PHY_DX8SL1DQSCTL_QSCNTEN_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL1DQSCTL_QSCNTEN_SHIFT 14 -#define DDR_PHY_DX8SL1DQSCTL_QSCNTEN_MASK 0x00004000U +#define DDR_PHY_DX8SL1DQSCTL_QSCNTEN_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL1DQSCTL_QSCNTEN_SHIFT 14 +#define DDR_PHY_DX8SL1DQSCTL_QSCNTEN_MASK 0x00004000U -/*Unused DQ I/O Mode*/ +/* +* Unused DQ I/O Mode +*/ #undef DDR_PHY_DX8SL1DQSCTL_UDQIOM_DEFVAL #undef DDR_PHY_DX8SL1DQSCTL_UDQIOM_SHIFT #undef DDR_PHY_DX8SL1DQSCTL_UDQIOM_MASK -#define DDR_PHY_DX8SL1DQSCTL_UDQIOM_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL1DQSCTL_UDQIOM_SHIFT 13 -#define DDR_PHY_DX8SL1DQSCTL_UDQIOM_MASK 0x00002000U +#define DDR_PHY_DX8SL1DQSCTL_UDQIOM_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL1DQSCTL_UDQIOM_SHIFT 13 +#define DDR_PHY_DX8SL1DQSCTL_UDQIOM_MASK 0x00002000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_DEFVAL #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_SHIFT #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_MASK -#define DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_SHIFT 10 -#define DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_MASK 0x00001C00U +#define DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_SHIFT 10 +#define DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_MASK 0x00001C00U -/*Data Slew Rate*/ +/* +* Data Slew Rate +*/ #undef DDR_PHY_DX8SL1DQSCTL_DXSR_DEFVAL #undef DDR_PHY_DX8SL1DQSCTL_DXSR_SHIFT #undef DDR_PHY_DX8SL1DQSCTL_DXSR_MASK -#define DDR_PHY_DX8SL1DQSCTL_DXSR_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL1DQSCTL_DXSR_SHIFT 8 -#define DDR_PHY_DX8SL1DQSCTL_DXSR_MASK 0x00000300U +#define DDR_PHY_DX8SL1DQSCTL_DXSR_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL1DQSCTL_DXSR_SHIFT 8 +#define DDR_PHY_DX8SL1DQSCTL_DXSR_MASK 0x00000300U -/*DQS_N Resistor*/ +/* +* DQS_N Resistor +*/ #undef DDR_PHY_DX8SL1DQSCTL_DQSNRES_DEFVAL #undef DDR_PHY_DX8SL1DQSCTL_DQSNRES_SHIFT #undef DDR_PHY_DX8SL1DQSCTL_DQSNRES_MASK -#define DDR_PHY_DX8SL1DQSCTL_DQSNRES_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL1DQSCTL_DQSNRES_SHIFT 4 -#define DDR_PHY_DX8SL1DQSCTL_DQSNRES_MASK 0x000000F0U +#define DDR_PHY_DX8SL1DQSCTL_DQSNRES_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL1DQSCTL_DQSNRES_SHIFT 4 +#define DDR_PHY_DX8SL1DQSCTL_DQSNRES_MASK 0x000000F0U -/*DQS Resistor*/ +/* +* DQS Resistor +*/ #undef DDR_PHY_DX8SL1DQSCTL_DQSRES_DEFVAL #undef DDR_PHY_DX8SL1DQSCTL_DQSRES_SHIFT #undef DDR_PHY_DX8SL1DQSCTL_DQSRES_MASK -#define DDR_PHY_DX8SL1DQSCTL_DQSRES_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL1DQSCTL_DQSRES_SHIFT 0 -#define DDR_PHY_DX8SL1DQSCTL_DQSRES_MASK 0x0000000FU +#define DDR_PHY_DX8SL1DQSCTL_DQSRES_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL1DQSCTL_DQSRES_SHIFT 0 +#define DDR_PHY_DX8SL1DQSCTL_DQSRES_MASK 0x0000000FU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_DEFVAL #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_SHIFT #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_MASK -#define DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_SHIFT 24 -#define DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_MASK 0xFF000000U +#define DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_SHIFT 24 +#define DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_MASK 0xFF000000U -/*Configurable Read Data Enable*/ +/* +* Configurable Read Data Enable +*/ #undef DDR_PHY_DX8SL1DXCTL2_CRDEN_DEFVAL #undef DDR_PHY_DX8SL1DXCTL2_CRDEN_SHIFT #undef DDR_PHY_DX8SL1DXCTL2_CRDEN_MASK -#define DDR_PHY_DX8SL1DXCTL2_CRDEN_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL1DXCTL2_CRDEN_SHIFT 23 -#define DDR_PHY_DX8SL1DXCTL2_CRDEN_MASK 0x00800000U +#define DDR_PHY_DX8SL1DXCTL2_CRDEN_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_CRDEN_SHIFT 23 +#define DDR_PHY_DX8SL1DXCTL2_CRDEN_MASK 0x00800000U -/*OX Extension during Post-amble*/ +/* +* OX Extension during Post-amble +*/ #undef DDR_PHY_DX8SL1DXCTL2_POSOEX_DEFVAL #undef DDR_PHY_DX8SL1DXCTL2_POSOEX_SHIFT #undef DDR_PHY_DX8SL1DXCTL2_POSOEX_MASK -#define DDR_PHY_DX8SL1DXCTL2_POSOEX_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL1DXCTL2_POSOEX_SHIFT 20 -#define DDR_PHY_DX8SL1DXCTL2_POSOEX_MASK 0x00700000U +#define DDR_PHY_DX8SL1DXCTL2_POSOEX_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_POSOEX_SHIFT 20 +#define DDR_PHY_DX8SL1DXCTL2_POSOEX_MASK 0x00700000U -/*OE Extension during Pre-amble*/ +/* +* OE Extension during Pre-amble +*/ #undef DDR_PHY_DX8SL1DXCTL2_PREOEX_DEFVAL #undef DDR_PHY_DX8SL1DXCTL2_PREOEX_SHIFT #undef DDR_PHY_DX8SL1DXCTL2_PREOEX_MASK -#define DDR_PHY_DX8SL1DXCTL2_PREOEX_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL1DXCTL2_PREOEX_SHIFT 18 -#define DDR_PHY_DX8SL1DXCTL2_PREOEX_MASK 0x000C0000U +#define DDR_PHY_DX8SL1DXCTL2_PREOEX_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_PREOEX_SHIFT 18 +#define DDR_PHY_DX8SL1DXCTL2_PREOEX_MASK 0x000C0000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_17_DEFVAL #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_17_SHIFT #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_17_MASK -#define DDR_PHY_DX8SL1DXCTL2_RESERVED_17_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL1DXCTL2_RESERVED_17_SHIFT 17 -#define DDR_PHY_DX8SL1DXCTL2_RESERVED_17_MASK 0x00020000U +#define DDR_PHY_DX8SL1DXCTL2_RESERVED_17_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_RESERVED_17_SHIFT 17 +#define DDR_PHY_DX8SL1DXCTL2_RESERVED_17_MASK 0x00020000U -/*I/O Assisted Gate Select*/ +/* +* I/O Assisted Gate Select +*/ #undef DDR_PHY_DX8SL1DXCTL2_IOAG_DEFVAL #undef DDR_PHY_DX8SL1DXCTL2_IOAG_SHIFT #undef DDR_PHY_DX8SL1DXCTL2_IOAG_MASK -#define DDR_PHY_DX8SL1DXCTL2_IOAG_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL1DXCTL2_IOAG_SHIFT 16 -#define DDR_PHY_DX8SL1DXCTL2_IOAG_MASK 0x00010000U +#define DDR_PHY_DX8SL1DXCTL2_IOAG_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_IOAG_SHIFT 16 +#define DDR_PHY_DX8SL1DXCTL2_IOAG_MASK 0x00010000U -/*I/O Loopback Select*/ +/* +* I/O Loopback Select +*/ #undef DDR_PHY_DX8SL1DXCTL2_IOLB_DEFVAL #undef DDR_PHY_DX8SL1DXCTL2_IOLB_SHIFT #undef DDR_PHY_DX8SL1DXCTL2_IOLB_MASK -#define DDR_PHY_DX8SL1DXCTL2_IOLB_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL1DXCTL2_IOLB_SHIFT 15 -#define DDR_PHY_DX8SL1DXCTL2_IOLB_MASK 0x00008000U +#define DDR_PHY_DX8SL1DXCTL2_IOLB_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_IOLB_SHIFT 15 +#define DDR_PHY_DX8SL1DXCTL2_IOLB_MASK 0x00008000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_DEFVAL #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_SHIFT #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_MASK -#define DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_SHIFT 13 -#define DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_MASK 0x00006000U +#define DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_SHIFT 13 +#define DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_MASK 0x00006000U -/*Low Power Wakeup Threshold*/ +/* +* Low Power Wakeup Threshold +*/ #undef DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_DEFVAL #undef DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_SHIFT #undef DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_MASK -#define DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_SHIFT 9 -#define DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_MASK 0x00001E00U +#define DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_SHIFT 9 +#define DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_MASK 0x00001E00U -/*Read Data Bus Inversion Enable*/ +/* +* Read Data Bus Inversion Enable +*/ #undef DDR_PHY_DX8SL1DXCTL2_RDBI_DEFVAL #undef DDR_PHY_DX8SL1DXCTL2_RDBI_SHIFT #undef DDR_PHY_DX8SL1DXCTL2_RDBI_MASK -#define DDR_PHY_DX8SL1DXCTL2_RDBI_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL1DXCTL2_RDBI_SHIFT 8 -#define DDR_PHY_DX8SL1DXCTL2_RDBI_MASK 0x00000100U +#define DDR_PHY_DX8SL1DXCTL2_RDBI_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_RDBI_SHIFT 8 +#define DDR_PHY_DX8SL1DXCTL2_RDBI_MASK 0x00000100U -/*Write Data Bus Inversion Enable*/ +/* +* Write Data Bus Inversion Enable +*/ #undef DDR_PHY_DX8SL1DXCTL2_WDBI_DEFVAL #undef DDR_PHY_DX8SL1DXCTL2_WDBI_SHIFT #undef DDR_PHY_DX8SL1DXCTL2_WDBI_MASK -#define DDR_PHY_DX8SL1DXCTL2_WDBI_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL1DXCTL2_WDBI_SHIFT 7 -#define DDR_PHY_DX8SL1DXCTL2_WDBI_MASK 0x00000080U +#define DDR_PHY_DX8SL1DXCTL2_WDBI_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_WDBI_SHIFT 7 +#define DDR_PHY_DX8SL1DXCTL2_WDBI_MASK 0x00000080U -/*PUB Read FIFO Bypass*/ +/* +* PUB Read FIFO Bypass +*/ #undef DDR_PHY_DX8SL1DXCTL2_PRFBYP_DEFVAL #undef DDR_PHY_DX8SL1DXCTL2_PRFBYP_SHIFT #undef DDR_PHY_DX8SL1DXCTL2_PRFBYP_MASK -#define DDR_PHY_DX8SL1DXCTL2_PRFBYP_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL1DXCTL2_PRFBYP_SHIFT 6 -#define DDR_PHY_DX8SL1DXCTL2_PRFBYP_MASK 0x00000040U +#define DDR_PHY_DX8SL1DXCTL2_PRFBYP_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_PRFBYP_SHIFT 6 +#define DDR_PHY_DX8SL1DXCTL2_PRFBYP_MASK 0x00000040U -/*DATX8 Receive FIFO Read Mode*/ +/* +* DATX8 Receive FIFO Read Mode +*/ #undef DDR_PHY_DX8SL1DXCTL2_RDMODE_DEFVAL #undef DDR_PHY_DX8SL1DXCTL2_RDMODE_SHIFT #undef DDR_PHY_DX8SL1DXCTL2_RDMODE_MASK -#define DDR_PHY_DX8SL1DXCTL2_RDMODE_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL1DXCTL2_RDMODE_SHIFT 4 -#define DDR_PHY_DX8SL1DXCTL2_RDMODE_MASK 0x00000030U +#define DDR_PHY_DX8SL1DXCTL2_RDMODE_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_RDMODE_SHIFT 4 +#define DDR_PHY_DX8SL1DXCTL2_RDMODE_MASK 0x00000030U -/*Disables the Read FIFO Reset*/ +/* +* Disables the Read FIFO Reset +*/ #undef DDR_PHY_DX8SL1DXCTL2_DISRST_DEFVAL #undef DDR_PHY_DX8SL1DXCTL2_DISRST_SHIFT #undef DDR_PHY_DX8SL1DXCTL2_DISRST_MASK -#define DDR_PHY_DX8SL1DXCTL2_DISRST_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL1DXCTL2_DISRST_SHIFT 3 -#define DDR_PHY_DX8SL1DXCTL2_DISRST_MASK 0x00000008U +#define DDR_PHY_DX8SL1DXCTL2_DISRST_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_DISRST_SHIFT 3 +#define DDR_PHY_DX8SL1DXCTL2_DISRST_MASK 0x00000008U -/*Read DQS Gate I/O Loopback*/ +/* +* Read DQS Gate I/O Loopback +*/ #undef DDR_PHY_DX8SL1DXCTL2_DQSGLB_DEFVAL #undef DDR_PHY_DX8SL1DXCTL2_DQSGLB_SHIFT #undef DDR_PHY_DX8SL1DXCTL2_DQSGLB_MASK -#define DDR_PHY_DX8SL1DXCTL2_DQSGLB_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL1DXCTL2_DQSGLB_SHIFT 1 -#define DDR_PHY_DX8SL1DXCTL2_DQSGLB_MASK 0x00000006U +#define DDR_PHY_DX8SL1DXCTL2_DQSGLB_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_DQSGLB_SHIFT 1 +#define DDR_PHY_DX8SL1DXCTL2_DQSGLB_MASK 0x00000006U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_0_DEFVAL #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_0_SHIFT #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_0_MASK -#define DDR_PHY_DX8SL1DXCTL2_RESERVED_0_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL1DXCTL2_RESERVED_0_SHIFT 0 -#define DDR_PHY_DX8SL1DXCTL2_RESERVED_0_MASK 0x00000001U +#define DDR_PHY_DX8SL1DXCTL2_RESERVED_0_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_RESERVED_0_SHIFT 0 +#define DDR_PHY_DX8SL1DXCTL2_RESERVED_0_MASK 0x00000001U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL1IOCR_RESERVED_31_DEFVAL #undef DDR_PHY_DX8SL1IOCR_RESERVED_31_SHIFT #undef DDR_PHY_DX8SL1IOCR_RESERVED_31_MASK -#define DDR_PHY_DX8SL1IOCR_RESERVED_31_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL1IOCR_RESERVED_31_SHIFT 31 -#define DDR_PHY_DX8SL1IOCR_RESERVED_31_MASK 0x80000000U +#define DDR_PHY_DX8SL1IOCR_RESERVED_31_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL1IOCR_RESERVED_31_SHIFT 31 +#define DDR_PHY_DX8SL1IOCR_RESERVED_31_MASK 0x80000000U -/*PVREF_DAC REFSEL range select*/ +/* +* PVREF_DAC REFSEL range select +*/ #undef DDR_PHY_DX8SL1IOCR_DXDACRANGE_DEFVAL #undef DDR_PHY_DX8SL1IOCR_DXDACRANGE_SHIFT #undef DDR_PHY_DX8SL1IOCR_DXDACRANGE_MASK -#define DDR_PHY_DX8SL1IOCR_DXDACRANGE_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL1IOCR_DXDACRANGE_SHIFT 28 -#define DDR_PHY_DX8SL1IOCR_DXDACRANGE_MASK 0x70000000U +#define DDR_PHY_DX8SL1IOCR_DXDACRANGE_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL1IOCR_DXDACRANGE_SHIFT 28 +#define DDR_PHY_DX8SL1IOCR_DXDACRANGE_MASK 0x70000000U -/*IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring*/ +/* +* IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring +*/ #undef DDR_PHY_DX8SL1IOCR_DXVREFIOM_DEFVAL #undef DDR_PHY_DX8SL1IOCR_DXVREFIOM_SHIFT #undef DDR_PHY_DX8SL1IOCR_DXVREFIOM_MASK -#define DDR_PHY_DX8SL1IOCR_DXVREFIOM_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL1IOCR_DXVREFIOM_SHIFT 25 -#define DDR_PHY_DX8SL1IOCR_DXVREFIOM_MASK 0x0E000000U +#define DDR_PHY_DX8SL1IOCR_DXVREFIOM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL1IOCR_DXVREFIOM_SHIFT 25 +#define DDR_PHY_DX8SL1IOCR_DXVREFIOM_MASK 0x0E000000U -/*DX IO Mode*/ +/* +* DX IO Mode +*/ #undef DDR_PHY_DX8SL1IOCR_DXIOM_DEFVAL #undef DDR_PHY_DX8SL1IOCR_DXIOM_SHIFT #undef DDR_PHY_DX8SL1IOCR_DXIOM_MASK -#define DDR_PHY_DX8SL1IOCR_DXIOM_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL1IOCR_DXIOM_SHIFT 22 -#define DDR_PHY_DX8SL1IOCR_DXIOM_MASK 0x01C00000U +#define DDR_PHY_DX8SL1IOCR_DXIOM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL1IOCR_DXIOM_SHIFT 22 +#define DDR_PHY_DX8SL1IOCR_DXIOM_MASK 0x01C00000U -/*DX IO Transmitter Mode*/ +/* +* DX IO Transmitter Mode +*/ #undef DDR_PHY_DX8SL1IOCR_DXTXM_DEFVAL #undef DDR_PHY_DX8SL1IOCR_DXTXM_SHIFT #undef DDR_PHY_DX8SL1IOCR_DXTXM_MASK -#define DDR_PHY_DX8SL1IOCR_DXTXM_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL1IOCR_DXTXM_SHIFT 11 -#define DDR_PHY_DX8SL1IOCR_DXTXM_MASK 0x003FF800U +#define DDR_PHY_DX8SL1IOCR_DXTXM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL1IOCR_DXTXM_SHIFT 11 +#define DDR_PHY_DX8SL1IOCR_DXTXM_MASK 0x003FF800U -/*DX IO Receiver Mode*/ +/* +* DX IO Receiver Mode +*/ #undef DDR_PHY_DX8SL1IOCR_DXRXM_DEFVAL #undef DDR_PHY_DX8SL1IOCR_DXRXM_SHIFT #undef DDR_PHY_DX8SL1IOCR_DXRXM_MASK -#define DDR_PHY_DX8SL1IOCR_DXRXM_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL1IOCR_DXRXM_SHIFT 0 -#define DDR_PHY_DX8SL1IOCR_DXRXM_MASK 0x000007FFU +#define DDR_PHY_DX8SL1IOCR_DXRXM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL1IOCR_DXRXM_SHIFT 0 +#define DDR_PHY_DX8SL1IOCR_DXRXM_MASK 0x000007FFU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL2OSC_RESERVED_31_30_DEFVAL #undef DDR_PHY_DX8SL2OSC_RESERVED_31_30_SHIFT #undef DDR_PHY_DX8SL2OSC_RESERVED_31_30_MASK -#define DDR_PHY_DX8SL2OSC_RESERVED_31_30_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL2OSC_RESERVED_31_30_SHIFT 30 -#define DDR_PHY_DX8SL2OSC_RESERVED_31_30_MASK 0xC0000000U +#define DDR_PHY_DX8SL2OSC_RESERVED_31_30_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX8SL2OSC_RESERVED_31_30_MASK 0xC0000000U -/*Enable Clock Gating for DX ddr_clk*/ +/* +* Enable Clock Gating for DX ddr_clk +*/ #undef DDR_PHY_DX8SL2OSC_GATEDXRDCLK_DEFVAL #undef DDR_PHY_DX8SL2OSC_GATEDXRDCLK_SHIFT #undef DDR_PHY_DX8SL2OSC_GATEDXRDCLK_MASK -#define DDR_PHY_DX8SL2OSC_GATEDXRDCLK_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL2OSC_GATEDXRDCLK_SHIFT 28 -#define DDR_PHY_DX8SL2OSC_GATEDXRDCLK_MASK 0x30000000U +#define DDR_PHY_DX8SL2OSC_GATEDXRDCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_GATEDXRDCLK_SHIFT 28 +#define DDR_PHY_DX8SL2OSC_GATEDXRDCLK_MASK 0x30000000U -/*Enable Clock Gating for DX ctl_rd_clk*/ +/* +* Enable Clock Gating for DX ctl_rd_clk +*/ #undef DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_DEFVAL #undef DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_SHIFT #undef DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_MASK -#define DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_SHIFT 26 -#define DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_MASK 0x0C000000U +#define DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_SHIFT 26 +#define DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_MASK 0x0C000000U -/*Enable Clock Gating for DX ctl_clk*/ +/* +* Enable Clock Gating for DX ctl_clk +*/ #undef DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_DEFVAL #undef DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_SHIFT #undef DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_MASK -#define DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_SHIFT 24 -#define DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_MASK 0x03000000U +#define DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_SHIFT 24 +#define DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_MASK 0x03000000U -/*Selects the level to which clocks will be stalled when clock gating is enabled.*/ +/* +* Selects the level to which clocks will be stalled when clock gating is e + * nabled. +*/ #undef DDR_PHY_DX8SL2OSC_CLKLEVEL_DEFVAL #undef DDR_PHY_DX8SL2OSC_CLKLEVEL_SHIFT #undef DDR_PHY_DX8SL2OSC_CLKLEVEL_MASK -#define DDR_PHY_DX8SL2OSC_CLKLEVEL_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL2OSC_CLKLEVEL_SHIFT 22 -#define DDR_PHY_DX8SL2OSC_CLKLEVEL_MASK 0x00C00000U +#define DDR_PHY_DX8SL2OSC_CLKLEVEL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_CLKLEVEL_SHIFT 22 +#define DDR_PHY_DX8SL2OSC_CLKLEVEL_MASK 0x00C00000U -/*Loopback Mode*/ +/* +* Loopback Mode +*/ #undef DDR_PHY_DX8SL2OSC_LBMODE_DEFVAL #undef DDR_PHY_DX8SL2OSC_LBMODE_SHIFT #undef DDR_PHY_DX8SL2OSC_LBMODE_MASK -#define DDR_PHY_DX8SL2OSC_LBMODE_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL2OSC_LBMODE_SHIFT 21 -#define DDR_PHY_DX8SL2OSC_LBMODE_MASK 0x00200000U +#define DDR_PHY_DX8SL2OSC_LBMODE_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_LBMODE_SHIFT 21 +#define DDR_PHY_DX8SL2OSC_LBMODE_MASK 0x00200000U -/*Load GSDQS LCDL with 2x the calibrated GSDQSPRD value*/ +/* +* Load GSDQS LCDL with 2x the calibrated GSDQSPRD value +*/ #undef DDR_PHY_DX8SL2OSC_LBGSDQS_DEFVAL #undef DDR_PHY_DX8SL2OSC_LBGSDQS_SHIFT #undef DDR_PHY_DX8SL2OSC_LBGSDQS_MASK -#define DDR_PHY_DX8SL2OSC_LBGSDQS_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL2OSC_LBGSDQS_SHIFT 20 -#define DDR_PHY_DX8SL2OSC_LBGSDQS_MASK 0x00100000U +#define DDR_PHY_DX8SL2OSC_LBGSDQS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_LBGSDQS_SHIFT 20 +#define DDR_PHY_DX8SL2OSC_LBGSDQS_MASK 0x00100000U -/*Loopback DQS Gating*/ +/* +* Loopback DQS Gating +*/ #undef DDR_PHY_DX8SL2OSC_LBGDQS_DEFVAL #undef DDR_PHY_DX8SL2OSC_LBGDQS_SHIFT #undef DDR_PHY_DX8SL2OSC_LBGDQS_MASK -#define DDR_PHY_DX8SL2OSC_LBGDQS_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL2OSC_LBGDQS_SHIFT 18 -#define DDR_PHY_DX8SL2OSC_LBGDQS_MASK 0x000C0000U +#define DDR_PHY_DX8SL2OSC_LBGDQS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_LBGDQS_SHIFT 18 +#define DDR_PHY_DX8SL2OSC_LBGDQS_MASK 0x000C0000U -/*Loopback DQS Shift*/ +/* +* Loopback DQS Shift +*/ #undef DDR_PHY_DX8SL2OSC_LBDQSS_DEFVAL #undef DDR_PHY_DX8SL2OSC_LBDQSS_SHIFT #undef DDR_PHY_DX8SL2OSC_LBDQSS_MASK -#define DDR_PHY_DX8SL2OSC_LBDQSS_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL2OSC_LBDQSS_SHIFT 17 -#define DDR_PHY_DX8SL2OSC_LBDQSS_MASK 0x00020000U +#define DDR_PHY_DX8SL2OSC_LBDQSS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_LBDQSS_SHIFT 17 +#define DDR_PHY_DX8SL2OSC_LBDQSS_MASK 0x00020000U -/*PHY High-Speed Reset*/ +/* +* PHY High-Speed Reset +*/ #undef DDR_PHY_DX8SL2OSC_PHYHRST_DEFVAL #undef DDR_PHY_DX8SL2OSC_PHYHRST_SHIFT #undef DDR_PHY_DX8SL2OSC_PHYHRST_MASK -#define DDR_PHY_DX8SL2OSC_PHYHRST_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL2OSC_PHYHRST_SHIFT 16 -#define DDR_PHY_DX8SL2OSC_PHYHRST_MASK 0x00010000U +#define DDR_PHY_DX8SL2OSC_PHYHRST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_PHYHRST_SHIFT 16 +#define DDR_PHY_DX8SL2OSC_PHYHRST_MASK 0x00010000U -/*PHY FIFO Reset*/ +/* +* PHY FIFO Reset +*/ #undef DDR_PHY_DX8SL2OSC_PHYFRST_DEFVAL #undef DDR_PHY_DX8SL2OSC_PHYFRST_SHIFT #undef DDR_PHY_DX8SL2OSC_PHYFRST_MASK -#define DDR_PHY_DX8SL2OSC_PHYFRST_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL2OSC_PHYFRST_SHIFT 15 -#define DDR_PHY_DX8SL2OSC_PHYFRST_MASK 0x00008000U +#define DDR_PHY_DX8SL2OSC_PHYFRST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_PHYFRST_SHIFT 15 +#define DDR_PHY_DX8SL2OSC_PHYFRST_MASK 0x00008000U -/*Delay Line Test Start*/ +/* +* Delay Line Test Start +*/ #undef DDR_PHY_DX8SL2OSC_DLTST_DEFVAL #undef DDR_PHY_DX8SL2OSC_DLTST_SHIFT #undef DDR_PHY_DX8SL2OSC_DLTST_MASK -#define DDR_PHY_DX8SL2OSC_DLTST_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL2OSC_DLTST_SHIFT 14 -#define DDR_PHY_DX8SL2OSC_DLTST_MASK 0x00004000U +#define DDR_PHY_DX8SL2OSC_DLTST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_DLTST_SHIFT 14 +#define DDR_PHY_DX8SL2OSC_DLTST_MASK 0x00004000U -/*Delay Line Test Mode*/ +/* +* Delay Line Test Mode +*/ #undef DDR_PHY_DX8SL2OSC_DLTMODE_DEFVAL #undef DDR_PHY_DX8SL2OSC_DLTMODE_SHIFT #undef DDR_PHY_DX8SL2OSC_DLTMODE_MASK -#define DDR_PHY_DX8SL2OSC_DLTMODE_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL2OSC_DLTMODE_SHIFT 13 -#define DDR_PHY_DX8SL2OSC_DLTMODE_MASK 0x00002000U +#define DDR_PHY_DX8SL2OSC_DLTMODE_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_DLTMODE_SHIFT 13 +#define DDR_PHY_DX8SL2OSC_DLTMODE_MASK 0x00002000U -/*Reserved. Caution, do not write to this register field.*/ +/* +* Reserved. Caution, do not write to this register field. +*/ #undef DDR_PHY_DX8SL2OSC_RESERVED_12_11_DEFVAL #undef DDR_PHY_DX8SL2OSC_RESERVED_12_11_SHIFT #undef DDR_PHY_DX8SL2OSC_RESERVED_12_11_MASK -#define DDR_PHY_DX8SL2OSC_RESERVED_12_11_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL2OSC_RESERVED_12_11_SHIFT 11 -#define DDR_PHY_DX8SL2OSC_RESERVED_12_11_MASK 0x00001800U +#define DDR_PHY_DX8SL2OSC_RESERVED_12_11_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_RESERVED_12_11_SHIFT 11 +#define DDR_PHY_DX8SL2OSC_RESERVED_12_11_MASK 0x00001800U -/*Oscillator Mode Write-Data Delay Line Select*/ +/* +* Oscillator Mode Write-Data Delay Line Select +*/ #undef DDR_PHY_DX8SL2OSC_OSCWDDL_DEFVAL #undef DDR_PHY_DX8SL2OSC_OSCWDDL_SHIFT #undef DDR_PHY_DX8SL2OSC_OSCWDDL_MASK -#define DDR_PHY_DX8SL2OSC_OSCWDDL_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL2OSC_OSCWDDL_SHIFT 9 -#define DDR_PHY_DX8SL2OSC_OSCWDDL_MASK 0x00000600U +#define DDR_PHY_DX8SL2OSC_OSCWDDL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_OSCWDDL_SHIFT 9 +#define DDR_PHY_DX8SL2OSC_OSCWDDL_MASK 0x00000600U -/*Reserved. Caution, do not write to this register field.*/ +/* +* Reserved. Caution, do not write to this register field. +*/ #undef DDR_PHY_DX8SL2OSC_RESERVED_8_7_DEFVAL #undef DDR_PHY_DX8SL2OSC_RESERVED_8_7_SHIFT #undef DDR_PHY_DX8SL2OSC_RESERVED_8_7_MASK -#define DDR_PHY_DX8SL2OSC_RESERVED_8_7_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL2OSC_RESERVED_8_7_SHIFT 7 -#define DDR_PHY_DX8SL2OSC_RESERVED_8_7_MASK 0x00000180U +#define DDR_PHY_DX8SL2OSC_RESERVED_8_7_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_RESERVED_8_7_SHIFT 7 +#define DDR_PHY_DX8SL2OSC_RESERVED_8_7_MASK 0x00000180U -/*Oscillator Mode Write-Leveling Delay Line Select*/ +/* +* Oscillator Mode Write-Leveling Delay Line Select +*/ #undef DDR_PHY_DX8SL2OSC_OSCWDL_DEFVAL #undef DDR_PHY_DX8SL2OSC_OSCWDL_SHIFT #undef DDR_PHY_DX8SL2OSC_OSCWDL_MASK -#define DDR_PHY_DX8SL2OSC_OSCWDL_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL2OSC_OSCWDL_SHIFT 5 -#define DDR_PHY_DX8SL2OSC_OSCWDL_MASK 0x00000060U +#define DDR_PHY_DX8SL2OSC_OSCWDL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_OSCWDL_SHIFT 5 +#define DDR_PHY_DX8SL2OSC_OSCWDL_MASK 0x00000060U -/*Oscillator Mode Division*/ +/* +* Oscillator Mode Division +*/ #undef DDR_PHY_DX8SL2OSC_OSCDIV_DEFVAL #undef DDR_PHY_DX8SL2OSC_OSCDIV_SHIFT #undef DDR_PHY_DX8SL2OSC_OSCDIV_MASK -#define DDR_PHY_DX8SL2OSC_OSCDIV_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL2OSC_OSCDIV_SHIFT 1 -#define DDR_PHY_DX8SL2OSC_OSCDIV_MASK 0x0000001EU +#define DDR_PHY_DX8SL2OSC_OSCDIV_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_OSCDIV_SHIFT 1 +#define DDR_PHY_DX8SL2OSC_OSCDIV_MASK 0x0000001EU -/*Oscillator Enable*/ +/* +* Oscillator Enable +*/ #undef DDR_PHY_DX8SL2OSC_OSCEN_DEFVAL #undef DDR_PHY_DX8SL2OSC_OSCEN_SHIFT #undef DDR_PHY_DX8SL2OSC_OSCEN_MASK -#define DDR_PHY_DX8SL2OSC_OSCEN_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL2OSC_OSCEN_SHIFT 0 -#define DDR_PHY_DX8SL2OSC_OSCEN_MASK 0x00000001U +#define DDR_PHY_DX8SL2OSC_OSCEN_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_OSCEN_SHIFT 0 +#define DDR_PHY_DX8SL2OSC_OSCEN_MASK 0x00000001U -/*Reserved. Return zeroes on reads.*/ +/* +* PLL Bypass +*/ +#undef DDR_PHY_DX8SL2PLLCR0_PLLBYP_DEFVAL +#undef DDR_PHY_DX8SL2PLLCR0_PLLBYP_SHIFT +#undef DDR_PHY_DX8SL2PLLCR0_PLLBYP_MASK +#define DDR_PHY_DX8SL2PLLCR0_PLLBYP_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL2PLLCR0_PLLBYP_SHIFT 31 +#define DDR_PHY_DX8SL2PLLCR0_PLLBYP_MASK 0x80000000U + +/* +* PLL Reset +*/ +#undef DDR_PHY_DX8SL2PLLCR0_PLLRST_DEFVAL +#undef DDR_PHY_DX8SL2PLLCR0_PLLRST_SHIFT +#undef DDR_PHY_DX8SL2PLLCR0_PLLRST_MASK +#define DDR_PHY_DX8SL2PLLCR0_PLLRST_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL2PLLCR0_PLLRST_SHIFT 30 +#define DDR_PHY_DX8SL2PLLCR0_PLLRST_MASK 0x40000000U + +/* +* PLL Power Down +*/ +#undef DDR_PHY_DX8SL2PLLCR0_PLLPD_DEFVAL +#undef DDR_PHY_DX8SL2PLLCR0_PLLPD_SHIFT +#undef DDR_PHY_DX8SL2PLLCR0_PLLPD_MASK +#define DDR_PHY_DX8SL2PLLCR0_PLLPD_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL2PLLCR0_PLLPD_SHIFT 29 +#define DDR_PHY_DX8SL2PLLCR0_PLLPD_MASK 0x20000000U + +/* +* Reference Stop Mode +*/ +#undef DDR_PHY_DX8SL2PLLCR0_RSTOPM_DEFVAL +#undef DDR_PHY_DX8SL2PLLCR0_RSTOPM_SHIFT +#undef DDR_PHY_DX8SL2PLLCR0_RSTOPM_MASK +#define DDR_PHY_DX8SL2PLLCR0_RSTOPM_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL2PLLCR0_RSTOPM_SHIFT 28 +#define DDR_PHY_DX8SL2PLLCR0_RSTOPM_MASK 0x10000000U + +/* +* PLL Frequency Select +*/ +#undef DDR_PHY_DX8SL2PLLCR0_FRQSEL_DEFVAL +#undef DDR_PHY_DX8SL2PLLCR0_FRQSEL_SHIFT +#undef DDR_PHY_DX8SL2PLLCR0_FRQSEL_MASK +#define DDR_PHY_DX8SL2PLLCR0_FRQSEL_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL2PLLCR0_FRQSEL_SHIFT 24 +#define DDR_PHY_DX8SL2PLLCR0_FRQSEL_MASK 0x0F000000U + +/* +* Relock Mode +*/ +#undef DDR_PHY_DX8SL2PLLCR0_RLOCKM_DEFVAL +#undef DDR_PHY_DX8SL2PLLCR0_RLOCKM_SHIFT +#undef DDR_PHY_DX8SL2PLLCR0_RLOCKM_MASK +#define DDR_PHY_DX8SL2PLLCR0_RLOCKM_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL2PLLCR0_RLOCKM_SHIFT 23 +#define DDR_PHY_DX8SL2PLLCR0_RLOCKM_MASK 0x00800000U + +/* +* Charge Pump Proportional Current Control +*/ +#undef DDR_PHY_DX8SL2PLLCR0_CPPC_DEFVAL +#undef DDR_PHY_DX8SL2PLLCR0_CPPC_SHIFT +#undef DDR_PHY_DX8SL2PLLCR0_CPPC_MASK +#define DDR_PHY_DX8SL2PLLCR0_CPPC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL2PLLCR0_CPPC_SHIFT 17 +#define DDR_PHY_DX8SL2PLLCR0_CPPC_MASK 0x007E0000U + +/* +* Charge Pump Integrating Current Control +*/ +#undef DDR_PHY_DX8SL2PLLCR0_CPIC_DEFVAL +#undef DDR_PHY_DX8SL2PLLCR0_CPIC_SHIFT +#undef DDR_PHY_DX8SL2PLLCR0_CPIC_MASK +#define DDR_PHY_DX8SL2PLLCR0_CPIC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL2PLLCR0_CPIC_SHIFT 13 +#define DDR_PHY_DX8SL2PLLCR0_CPIC_MASK 0x0001E000U + +/* +* Gear Shift +*/ +#undef DDR_PHY_DX8SL2PLLCR0_GSHIFT_DEFVAL +#undef DDR_PHY_DX8SL2PLLCR0_GSHIFT_SHIFT +#undef DDR_PHY_DX8SL2PLLCR0_GSHIFT_MASK +#define DDR_PHY_DX8SL2PLLCR0_GSHIFT_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL2PLLCR0_GSHIFT_SHIFT 12 +#define DDR_PHY_DX8SL2PLLCR0_GSHIFT_MASK 0x00001000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL2PLLCR0_RESERVED_11_9_DEFVAL +#undef DDR_PHY_DX8SL2PLLCR0_RESERVED_11_9_SHIFT +#undef DDR_PHY_DX8SL2PLLCR0_RESERVED_11_9_MASK +#define DDR_PHY_DX8SL2PLLCR0_RESERVED_11_9_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL2PLLCR0_RESERVED_11_9_SHIFT 9 +#define DDR_PHY_DX8SL2PLLCR0_RESERVED_11_9_MASK 0x00000E00U + +/* +* Analog Test Enable (ATOEN) +*/ +#undef DDR_PHY_DX8SL2PLLCR0_ATOEN_DEFVAL +#undef DDR_PHY_DX8SL2PLLCR0_ATOEN_SHIFT +#undef DDR_PHY_DX8SL2PLLCR0_ATOEN_MASK +#define DDR_PHY_DX8SL2PLLCR0_ATOEN_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL2PLLCR0_ATOEN_SHIFT 8 +#define DDR_PHY_DX8SL2PLLCR0_ATOEN_MASK 0x00000100U + +/* +* Analog Test Control +*/ +#undef DDR_PHY_DX8SL2PLLCR0_ATC_DEFVAL +#undef DDR_PHY_DX8SL2PLLCR0_ATC_SHIFT +#undef DDR_PHY_DX8SL2PLLCR0_ATC_MASK +#define DDR_PHY_DX8SL2PLLCR0_ATC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL2PLLCR0_ATC_SHIFT 4 +#define DDR_PHY_DX8SL2PLLCR0_ATC_MASK 0x000000F0U + +/* +* Digital Test Control +*/ +#undef DDR_PHY_DX8SL2PLLCR0_DTC_DEFVAL +#undef DDR_PHY_DX8SL2PLLCR0_DTC_SHIFT +#undef DDR_PHY_DX8SL2PLLCR0_DTC_MASK +#define DDR_PHY_DX8SL2PLLCR0_DTC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL2PLLCR0_DTC_SHIFT 0 +#define DDR_PHY_DX8SL2PLLCR0_DTC_MASK 0x0000000FU + +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_DEFVAL #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_SHIFT #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_MASK -#define DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_SHIFT 25 -#define DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_MASK 0xFE000000U +#define DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_SHIFT 25 +#define DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_MASK 0xFE000000U -/*Read Path Rise-to-Rise Mode*/ +/* +* Read Path Rise-to-Rise Mode +*/ #undef DDR_PHY_DX8SL2DQSCTL_RRRMODE_DEFVAL #undef DDR_PHY_DX8SL2DQSCTL_RRRMODE_SHIFT #undef DDR_PHY_DX8SL2DQSCTL_RRRMODE_MASK -#define DDR_PHY_DX8SL2DQSCTL_RRRMODE_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL2DQSCTL_RRRMODE_SHIFT 24 -#define DDR_PHY_DX8SL2DQSCTL_RRRMODE_MASK 0x01000000U +#define DDR_PHY_DX8SL2DQSCTL_RRRMODE_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL2DQSCTL_RRRMODE_SHIFT 24 +#define DDR_PHY_DX8SL2DQSCTL_RRRMODE_MASK 0x01000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_DEFVAL #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_SHIFT #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_MASK -#define DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_SHIFT 22 -#define DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_MASK 0x00C00000U +#define DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_MASK 0x00C00000U -/*Write Path Rise-to-Rise Mode*/ +/* +* Write Path Rise-to-Rise Mode +*/ #undef DDR_PHY_DX8SL2DQSCTL_WRRMODE_DEFVAL #undef DDR_PHY_DX8SL2DQSCTL_WRRMODE_SHIFT #undef DDR_PHY_DX8SL2DQSCTL_WRRMODE_MASK -#define DDR_PHY_DX8SL2DQSCTL_WRRMODE_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL2DQSCTL_WRRMODE_SHIFT 21 -#define DDR_PHY_DX8SL2DQSCTL_WRRMODE_MASK 0x00200000U +#define DDR_PHY_DX8SL2DQSCTL_WRRMODE_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL2DQSCTL_WRRMODE_SHIFT 21 +#define DDR_PHY_DX8SL2DQSCTL_WRRMODE_MASK 0x00200000U -/*DQS Gate Extension*/ +/* +* DQS Gate Extension +*/ #undef DDR_PHY_DX8SL2DQSCTL_DQSGX_DEFVAL #undef DDR_PHY_DX8SL2DQSCTL_DQSGX_SHIFT #undef DDR_PHY_DX8SL2DQSCTL_DQSGX_MASK -#define DDR_PHY_DX8SL2DQSCTL_DQSGX_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL2DQSCTL_DQSGX_SHIFT 19 -#define DDR_PHY_DX8SL2DQSCTL_DQSGX_MASK 0x00180000U +#define DDR_PHY_DX8SL2DQSCTL_DQSGX_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL2DQSCTL_DQSGX_SHIFT 19 +#define DDR_PHY_DX8SL2DQSCTL_DQSGX_MASK 0x00180000U -/*Low Power PLL Power Down*/ +/* +* Low Power PLL Power Down +*/ #undef DDR_PHY_DX8SL2DQSCTL_LPPLLPD_DEFVAL #undef DDR_PHY_DX8SL2DQSCTL_LPPLLPD_SHIFT #undef DDR_PHY_DX8SL2DQSCTL_LPPLLPD_MASK -#define DDR_PHY_DX8SL2DQSCTL_LPPLLPD_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL2DQSCTL_LPPLLPD_SHIFT 18 -#define DDR_PHY_DX8SL2DQSCTL_LPPLLPD_MASK 0x00040000U +#define DDR_PHY_DX8SL2DQSCTL_LPPLLPD_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL2DQSCTL_LPPLLPD_SHIFT 18 +#define DDR_PHY_DX8SL2DQSCTL_LPPLLPD_MASK 0x00040000U -/*Low Power I/O Power Down*/ +/* +* Low Power I/O Power Down +*/ #undef DDR_PHY_DX8SL2DQSCTL_LPIOPD_DEFVAL #undef DDR_PHY_DX8SL2DQSCTL_LPIOPD_SHIFT #undef DDR_PHY_DX8SL2DQSCTL_LPIOPD_MASK -#define DDR_PHY_DX8SL2DQSCTL_LPIOPD_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL2DQSCTL_LPIOPD_SHIFT 17 -#define DDR_PHY_DX8SL2DQSCTL_LPIOPD_MASK 0x00020000U +#define DDR_PHY_DX8SL2DQSCTL_LPIOPD_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL2DQSCTL_LPIOPD_SHIFT 17 +#define DDR_PHY_DX8SL2DQSCTL_LPIOPD_MASK 0x00020000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_DEFVAL #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_SHIFT #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_MASK -#define DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_SHIFT 15 -#define DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_MASK 0x00018000U +#define DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_SHIFT 15 +#define DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_MASK 0x00018000U -/*QS Counter Enable*/ +/* +* QS Counter Enable +*/ #undef DDR_PHY_DX8SL2DQSCTL_QSCNTEN_DEFVAL #undef DDR_PHY_DX8SL2DQSCTL_QSCNTEN_SHIFT #undef DDR_PHY_DX8SL2DQSCTL_QSCNTEN_MASK -#define DDR_PHY_DX8SL2DQSCTL_QSCNTEN_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL2DQSCTL_QSCNTEN_SHIFT 14 -#define DDR_PHY_DX8SL2DQSCTL_QSCNTEN_MASK 0x00004000U +#define DDR_PHY_DX8SL2DQSCTL_QSCNTEN_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL2DQSCTL_QSCNTEN_SHIFT 14 +#define DDR_PHY_DX8SL2DQSCTL_QSCNTEN_MASK 0x00004000U -/*Unused DQ I/O Mode*/ +/* +* Unused DQ I/O Mode +*/ #undef DDR_PHY_DX8SL2DQSCTL_UDQIOM_DEFVAL #undef DDR_PHY_DX8SL2DQSCTL_UDQIOM_SHIFT #undef DDR_PHY_DX8SL2DQSCTL_UDQIOM_MASK -#define DDR_PHY_DX8SL2DQSCTL_UDQIOM_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL2DQSCTL_UDQIOM_SHIFT 13 -#define DDR_PHY_DX8SL2DQSCTL_UDQIOM_MASK 0x00002000U +#define DDR_PHY_DX8SL2DQSCTL_UDQIOM_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL2DQSCTL_UDQIOM_SHIFT 13 +#define DDR_PHY_DX8SL2DQSCTL_UDQIOM_MASK 0x00002000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_DEFVAL #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_SHIFT #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_MASK -#define DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_SHIFT 10 -#define DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_MASK 0x00001C00U +#define DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_SHIFT 10 +#define DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_MASK 0x00001C00U -/*Data Slew Rate*/ +/* +* Data Slew Rate +*/ #undef DDR_PHY_DX8SL2DQSCTL_DXSR_DEFVAL #undef DDR_PHY_DX8SL2DQSCTL_DXSR_SHIFT #undef DDR_PHY_DX8SL2DQSCTL_DXSR_MASK -#define DDR_PHY_DX8SL2DQSCTL_DXSR_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL2DQSCTL_DXSR_SHIFT 8 -#define DDR_PHY_DX8SL2DQSCTL_DXSR_MASK 0x00000300U +#define DDR_PHY_DX8SL2DQSCTL_DXSR_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL2DQSCTL_DXSR_SHIFT 8 +#define DDR_PHY_DX8SL2DQSCTL_DXSR_MASK 0x00000300U -/*DQS_N Resistor*/ +/* +* DQS_N Resistor +*/ #undef DDR_PHY_DX8SL2DQSCTL_DQSNRES_DEFVAL #undef DDR_PHY_DX8SL2DQSCTL_DQSNRES_SHIFT #undef DDR_PHY_DX8SL2DQSCTL_DQSNRES_MASK -#define DDR_PHY_DX8SL2DQSCTL_DQSNRES_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL2DQSCTL_DQSNRES_SHIFT 4 -#define DDR_PHY_DX8SL2DQSCTL_DQSNRES_MASK 0x000000F0U +#define DDR_PHY_DX8SL2DQSCTL_DQSNRES_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL2DQSCTL_DQSNRES_SHIFT 4 +#define DDR_PHY_DX8SL2DQSCTL_DQSNRES_MASK 0x000000F0U -/*DQS Resistor*/ +/* +* DQS Resistor +*/ #undef DDR_PHY_DX8SL2DQSCTL_DQSRES_DEFVAL #undef DDR_PHY_DX8SL2DQSCTL_DQSRES_SHIFT #undef DDR_PHY_DX8SL2DQSCTL_DQSRES_MASK -#define DDR_PHY_DX8SL2DQSCTL_DQSRES_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL2DQSCTL_DQSRES_SHIFT 0 -#define DDR_PHY_DX8SL2DQSCTL_DQSRES_MASK 0x0000000FU +#define DDR_PHY_DX8SL2DQSCTL_DQSRES_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL2DQSCTL_DQSRES_SHIFT 0 +#define DDR_PHY_DX8SL2DQSCTL_DQSRES_MASK 0x0000000FU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_DEFVAL #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_SHIFT #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_MASK -#define DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_SHIFT 24 -#define DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_MASK 0xFF000000U +#define DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_SHIFT 24 +#define DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_MASK 0xFF000000U -/*Configurable Read Data Enable*/ +/* +* Configurable Read Data Enable +*/ #undef DDR_PHY_DX8SL2DXCTL2_CRDEN_DEFVAL #undef DDR_PHY_DX8SL2DXCTL2_CRDEN_SHIFT #undef DDR_PHY_DX8SL2DXCTL2_CRDEN_MASK -#define DDR_PHY_DX8SL2DXCTL2_CRDEN_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL2DXCTL2_CRDEN_SHIFT 23 -#define DDR_PHY_DX8SL2DXCTL2_CRDEN_MASK 0x00800000U +#define DDR_PHY_DX8SL2DXCTL2_CRDEN_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_CRDEN_SHIFT 23 +#define DDR_PHY_DX8SL2DXCTL2_CRDEN_MASK 0x00800000U -/*OX Extension during Post-amble*/ +/* +* OX Extension during Post-amble +*/ #undef DDR_PHY_DX8SL2DXCTL2_POSOEX_DEFVAL #undef DDR_PHY_DX8SL2DXCTL2_POSOEX_SHIFT #undef DDR_PHY_DX8SL2DXCTL2_POSOEX_MASK -#define DDR_PHY_DX8SL2DXCTL2_POSOEX_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL2DXCTL2_POSOEX_SHIFT 20 -#define DDR_PHY_DX8SL2DXCTL2_POSOEX_MASK 0x00700000U +#define DDR_PHY_DX8SL2DXCTL2_POSOEX_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_POSOEX_SHIFT 20 +#define DDR_PHY_DX8SL2DXCTL2_POSOEX_MASK 0x00700000U -/*OE Extension during Pre-amble*/ +/* +* OE Extension during Pre-amble +*/ #undef DDR_PHY_DX8SL2DXCTL2_PREOEX_DEFVAL #undef DDR_PHY_DX8SL2DXCTL2_PREOEX_SHIFT #undef DDR_PHY_DX8SL2DXCTL2_PREOEX_MASK -#define DDR_PHY_DX8SL2DXCTL2_PREOEX_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL2DXCTL2_PREOEX_SHIFT 18 -#define DDR_PHY_DX8SL2DXCTL2_PREOEX_MASK 0x000C0000U +#define DDR_PHY_DX8SL2DXCTL2_PREOEX_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_PREOEX_SHIFT 18 +#define DDR_PHY_DX8SL2DXCTL2_PREOEX_MASK 0x000C0000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_17_DEFVAL #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_17_SHIFT #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_17_MASK -#define DDR_PHY_DX8SL2DXCTL2_RESERVED_17_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL2DXCTL2_RESERVED_17_SHIFT 17 -#define DDR_PHY_DX8SL2DXCTL2_RESERVED_17_MASK 0x00020000U +#define DDR_PHY_DX8SL2DXCTL2_RESERVED_17_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_RESERVED_17_SHIFT 17 +#define DDR_PHY_DX8SL2DXCTL2_RESERVED_17_MASK 0x00020000U -/*I/O Assisted Gate Select*/ +/* +* I/O Assisted Gate Select +*/ #undef DDR_PHY_DX8SL2DXCTL2_IOAG_DEFVAL #undef DDR_PHY_DX8SL2DXCTL2_IOAG_SHIFT #undef DDR_PHY_DX8SL2DXCTL2_IOAG_MASK -#define DDR_PHY_DX8SL2DXCTL2_IOAG_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL2DXCTL2_IOAG_SHIFT 16 -#define DDR_PHY_DX8SL2DXCTL2_IOAG_MASK 0x00010000U +#define DDR_PHY_DX8SL2DXCTL2_IOAG_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_IOAG_SHIFT 16 +#define DDR_PHY_DX8SL2DXCTL2_IOAG_MASK 0x00010000U -/*I/O Loopback Select*/ +/* +* I/O Loopback Select +*/ #undef DDR_PHY_DX8SL2DXCTL2_IOLB_DEFVAL #undef DDR_PHY_DX8SL2DXCTL2_IOLB_SHIFT #undef DDR_PHY_DX8SL2DXCTL2_IOLB_MASK -#define DDR_PHY_DX8SL2DXCTL2_IOLB_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL2DXCTL2_IOLB_SHIFT 15 -#define DDR_PHY_DX8SL2DXCTL2_IOLB_MASK 0x00008000U +#define DDR_PHY_DX8SL2DXCTL2_IOLB_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_IOLB_SHIFT 15 +#define DDR_PHY_DX8SL2DXCTL2_IOLB_MASK 0x00008000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_DEFVAL #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_SHIFT #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_MASK -#define DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_SHIFT 13 -#define DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_MASK 0x00006000U +#define DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_SHIFT 13 +#define DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_MASK 0x00006000U -/*Low Power Wakeup Threshold*/ +/* +* Low Power Wakeup Threshold +*/ #undef DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_DEFVAL #undef DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_SHIFT #undef DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_MASK -#define DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_SHIFT 9 -#define DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_MASK 0x00001E00U +#define DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_SHIFT 9 +#define DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_MASK 0x00001E00U -/*Read Data Bus Inversion Enable*/ +/* +* Read Data Bus Inversion Enable +*/ #undef DDR_PHY_DX8SL2DXCTL2_RDBI_DEFVAL #undef DDR_PHY_DX8SL2DXCTL2_RDBI_SHIFT #undef DDR_PHY_DX8SL2DXCTL2_RDBI_MASK -#define DDR_PHY_DX8SL2DXCTL2_RDBI_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL2DXCTL2_RDBI_SHIFT 8 -#define DDR_PHY_DX8SL2DXCTL2_RDBI_MASK 0x00000100U +#define DDR_PHY_DX8SL2DXCTL2_RDBI_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_RDBI_SHIFT 8 +#define DDR_PHY_DX8SL2DXCTL2_RDBI_MASK 0x00000100U -/*Write Data Bus Inversion Enable*/ +/* +* Write Data Bus Inversion Enable +*/ #undef DDR_PHY_DX8SL2DXCTL2_WDBI_DEFVAL #undef DDR_PHY_DX8SL2DXCTL2_WDBI_SHIFT #undef DDR_PHY_DX8SL2DXCTL2_WDBI_MASK -#define DDR_PHY_DX8SL2DXCTL2_WDBI_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL2DXCTL2_WDBI_SHIFT 7 -#define DDR_PHY_DX8SL2DXCTL2_WDBI_MASK 0x00000080U +#define DDR_PHY_DX8SL2DXCTL2_WDBI_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_WDBI_SHIFT 7 +#define DDR_PHY_DX8SL2DXCTL2_WDBI_MASK 0x00000080U -/*PUB Read FIFO Bypass*/ +/* +* PUB Read FIFO Bypass +*/ #undef DDR_PHY_DX8SL2DXCTL2_PRFBYP_DEFVAL #undef DDR_PHY_DX8SL2DXCTL2_PRFBYP_SHIFT #undef DDR_PHY_DX8SL2DXCTL2_PRFBYP_MASK -#define DDR_PHY_DX8SL2DXCTL2_PRFBYP_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL2DXCTL2_PRFBYP_SHIFT 6 -#define DDR_PHY_DX8SL2DXCTL2_PRFBYP_MASK 0x00000040U +#define DDR_PHY_DX8SL2DXCTL2_PRFBYP_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_PRFBYP_SHIFT 6 +#define DDR_PHY_DX8SL2DXCTL2_PRFBYP_MASK 0x00000040U -/*DATX8 Receive FIFO Read Mode*/ +/* +* DATX8 Receive FIFO Read Mode +*/ #undef DDR_PHY_DX8SL2DXCTL2_RDMODE_DEFVAL #undef DDR_PHY_DX8SL2DXCTL2_RDMODE_SHIFT #undef DDR_PHY_DX8SL2DXCTL2_RDMODE_MASK -#define DDR_PHY_DX8SL2DXCTL2_RDMODE_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL2DXCTL2_RDMODE_SHIFT 4 -#define DDR_PHY_DX8SL2DXCTL2_RDMODE_MASK 0x00000030U +#define DDR_PHY_DX8SL2DXCTL2_RDMODE_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_RDMODE_SHIFT 4 +#define DDR_PHY_DX8SL2DXCTL2_RDMODE_MASK 0x00000030U -/*Disables the Read FIFO Reset*/ +/* +* Disables the Read FIFO Reset +*/ #undef DDR_PHY_DX8SL2DXCTL2_DISRST_DEFVAL #undef DDR_PHY_DX8SL2DXCTL2_DISRST_SHIFT #undef DDR_PHY_DX8SL2DXCTL2_DISRST_MASK -#define DDR_PHY_DX8SL2DXCTL2_DISRST_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL2DXCTL2_DISRST_SHIFT 3 -#define DDR_PHY_DX8SL2DXCTL2_DISRST_MASK 0x00000008U +#define DDR_PHY_DX8SL2DXCTL2_DISRST_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_DISRST_SHIFT 3 +#define DDR_PHY_DX8SL2DXCTL2_DISRST_MASK 0x00000008U -/*Read DQS Gate I/O Loopback*/ +/* +* Read DQS Gate I/O Loopback +*/ #undef DDR_PHY_DX8SL2DXCTL2_DQSGLB_DEFVAL #undef DDR_PHY_DX8SL2DXCTL2_DQSGLB_SHIFT #undef DDR_PHY_DX8SL2DXCTL2_DQSGLB_MASK -#define DDR_PHY_DX8SL2DXCTL2_DQSGLB_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL2DXCTL2_DQSGLB_SHIFT 1 -#define DDR_PHY_DX8SL2DXCTL2_DQSGLB_MASK 0x00000006U +#define DDR_PHY_DX8SL2DXCTL2_DQSGLB_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_DQSGLB_SHIFT 1 +#define DDR_PHY_DX8SL2DXCTL2_DQSGLB_MASK 0x00000006U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_0_DEFVAL #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_0_SHIFT #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_0_MASK -#define DDR_PHY_DX8SL2DXCTL2_RESERVED_0_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL2DXCTL2_RESERVED_0_SHIFT 0 -#define DDR_PHY_DX8SL2DXCTL2_RESERVED_0_MASK 0x00000001U +#define DDR_PHY_DX8SL2DXCTL2_RESERVED_0_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_RESERVED_0_SHIFT 0 +#define DDR_PHY_DX8SL2DXCTL2_RESERVED_0_MASK 0x00000001U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL2IOCR_RESERVED_31_DEFVAL #undef DDR_PHY_DX8SL2IOCR_RESERVED_31_SHIFT #undef DDR_PHY_DX8SL2IOCR_RESERVED_31_MASK -#define DDR_PHY_DX8SL2IOCR_RESERVED_31_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL2IOCR_RESERVED_31_SHIFT 31 -#define DDR_PHY_DX8SL2IOCR_RESERVED_31_MASK 0x80000000U +#define DDR_PHY_DX8SL2IOCR_RESERVED_31_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL2IOCR_RESERVED_31_SHIFT 31 +#define DDR_PHY_DX8SL2IOCR_RESERVED_31_MASK 0x80000000U -/*PVREF_DAC REFSEL range select*/ +/* +* PVREF_DAC REFSEL range select +*/ #undef DDR_PHY_DX8SL2IOCR_DXDACRANGE_DEFVAL #undef DDR_PHY_DX8SL2IOCR_DXDACRANGE_SHIFT #undef DDR_PHY_DX8SL2IOCR_DXDACRANGE_MASK -#define DDR_PHY_DX8SL2IOCR_DXDACRANGE_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL2IOCR_DXDACRANGE_SHIFT 28 -#define DDR_PHY_DX8SL2IOCR_DXDACRANGE_MASK 0x70000000U +#define DDR_PHY_DX8SL2IOCR_DXDACRANGE_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL2IOCR_DXDACRANGE_SHIFT 28 +#define DDR_PHY_DX8SL2IOCR_DXDACRANGE_MASK 0x70000000U -/*IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring*/ +/* +* IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring +*/ #undef DDR_PHY_DX8SL2IOCR_DXVREFIOM_DEFVAL #undef DDR_PHY_DX8SL2IOCR_DXVREFIOM_SHIFT #undef DDR_PHY_DX8SL2IOCR_DXVREFIOM_MASK -#define DDR_PHY_DX8SL2IOCR_DXVREFIOM_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL2IOCR_DXVREFIOM_SHIFT 25 -#define DDR_PHY_DX8SL2IOCR_DXVREFIOM_MASK 0x0E000000U +#define DDR_PHY_DX8SL2IOCR_DXVREFIOM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL2IOCR_DXVREFIOM_SHIFT 25 +#define DDR_PHY_DX8SL2IOCR_DXVREFIOM_MASK 0x0E000000U -/*DX IO Mode*/ +/* +* DX IO Mode +*/ #undef DDR_PHY_DX8SL2IOCR_DXIOM_DEFVAL #undef DDR_PHY_DX8SL2IOCR_DXIOM_SHIFT #undef DDR_PHY_DX8SL2IOCR_DXIOM_MASK -#define DDR_PHY_DX8SL2IOCR_DXIOM_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL2IOCR_DXIOM_SHIFT 22 -#define DDR_PHY_DX8SL2IOCR_DXIOM_MASK 0x01C00000U +#define DDR_PHY_DX8SL2IOCR_DXIOM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL2IOCR_DXIOM_SHIFT 22 +#define DDR_PHY_DX8SL2IOCR_DXIOM_MASK 0x01C00000U -/*DX IO Transmitter Mode*/ +/* +* DX IO Transmitter Mode +*/ #undef DDR_PHY_DX8SL2IOCR_DXTXM_DEFVAL #undef DDR_PHY_DX8SL2IOCR_DXTXM_SHIFT #undef DDR_PHY_DX8SL2IOCR_DXTXM_MASK -#define DDR_PHY_DX8SL2IOCR_DXTXM_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL2IOCR_DXTXM_SHIFT 11 -#define DDR_PHY_DX8SL2IOCR_DXTXM_MASK 0x003FF800U +#define DDR_PHY_DX8SL2IOCR_DXTXM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL2IOCR_DXTXM_SHIFT 11 +#define DDR_PHY_DX8SL2IOCR_DXTXM_MASK 0x003FF800U -/*DX IO Receiver Mode*/ +/* +* DX IO Receiver Mode +*/ #undef DDR_PHY_DX8SL2IOCR_DXRXM_DEFVAL #undef DDR_PHY_DX8SL2IOCR_DXRXM_SHIFT #undef DDR_PHY_DX8SL2IOCR_DXRXM_MASK -#define DDR_PHY_DX8SL2IOCR_DXRXM_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL2IOCR_DXRXM_SHIFT 0 -#define DDR_PHY_DX8SL2IOCR_DXRXM_MASK 0x000007FFU +#define DDR_PHY_DX8SL2IOCR_DXRXM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL2IOCR_DXRXM_SHIFT 0 +#define DDR_PHY_DX8SL2IOCR_DXRXM_MASK 0x000007FFU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL3OSC_RESERVED_31_30_DEFVAL #undef DDR_PHY_DX8SL3OSC_RESERVED_31_30_SHIFT #undef DDR_PHY_DX8SL3OSC_RESERVED_31_30_MASK -#define DDR_PHY_DX8SL3OSC_RESERVED_31_30_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL3OSC_RESERVED_31_30_SHIFT 30 -#define DDR_PHY_DX8SL3OSC_RESERVED_31_30_MASK 0xC0000000U +#define DDR_PHY_DX8SL3OSC_RESERVED_31_30_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX8SL3OSC_RESERVED_31_30_MASK 0xC0000000U -/*Enable Clock Gating for DX ddr_clk*/ +/* +* Enable Clock Gating for DX ddr_clk +*/ #undef DDR_PHY_DX8SL3OSC_GATEDXRDCLK_DEFVAL #undef DDR_PHY_DX8SL3OSC_GATEDXRDCLK_SHIFT #undef DDR_PHY_DX8SL3OSC_GATEDXRDCLK_MASK -#define DDR_PHY_DX8SL3OSC_GATEDXRDCLK_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL3OSC_GATEDXRDCLK_SHIFT 28 -#define DDR_PHY_DX8SL3OSC_GATEDXRDCLK_MASK 0x30000000U +#define DDR_PHY_DX8SL3OSC_GATEDXRDCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_GATEDXRDCLK_SHIFT 28 +#define DDR_PHY_DX8SL3OSC_GATEDXRDCLK_MASK 0x30000000U -/*Enable Clock Gating for DX ctl_rd_clk*/ +/* +* Enable Clock Gating for DX ctl_rd_clk +*/ #undef DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_DEFVAL #undef DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_SHIFT #undef DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_MASK -#define DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_SHIFT 26 -#define DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_MASK 0x0C000000U +#define DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_SHIFT 26 +#define DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_MASK 0x0C000000U -/*Enable Clock Gating for DX ctl_clk*/ +/* +* Enable Clock Gating for DX ctl_clk +*/ #undef DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_DEFVAL #undef DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_SHIFT #undef DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_MASK -#define DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_SHIFT 24 -#define DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_MASK 0x03000000U +#define DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_SHIFT 24 +#define DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_MASK 0x03000000U -/*Selects the level to which clocks will be stalled when clock gating is enabled.*/ +/* +* Selects the level to which clocks will be stalled when clock gating is e + * nabled. +*/ #undef DDR_PHY_DX8SL3OSC_CLKLEVEL_DEFVAL #undef DDR_PHY_DX8SL3OSC_CLKLEVEL_SHIFT #undef DDR_PHY_DX8SL3OSC_CLKLEVEL_MASK -#define DDR_PHY_DX8SL3OSC_CLKLEVEL_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL3OSC_CLKLEVEL_SHIFT 22 -#define DDR_PHY_DX8SL3OSC_CLKLEVEL_MASK 0x00C00000U +#define DDR_PHY_DX8SL3OSC_CLKLEVEL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_CLKLEVEL_SHIFT 22 +#define DDR_PHY_DX8SL3OSC_CLKLEVEL_MASK 0x00C00000U -/*Loopback Mode*/ +/* +* Loopback Mode +*/ #undef DDR_PHY_DX8SL3OSC_LBMODE_DEFVAL #undef DDR_PHY_DX8SL3OSC_LBMODE_SHIFT #undef DDR_PHY_DX8SL3OSC_LBMODE_MASK -#define DDR_PHY_DX8SL3OSC_LBMODE_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL3OSC_LBMODE_SHIFT 21 -#define DDR_PHY_DX8SL3OSC_LBMODE_MASK 0x00200000U +#define DDR_PHY_DX8SL3OSC_LBMODE_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_LBMODE_SHIFT 21 +#define DDR_PHY_DX8SL3OSC_LBMODE_MASK 0x00200000U -/*Load GSDQS LCDL with 2x the calibrated GSDQSPRD value*/ +/* +* Load GSDQS LCDL with 2x the calibrated GSDQSPRD value +*/ #undef DDR_PHY_DX8SL3OSC_LBGSDQS_DEFVAL #undef DDR_PHY_DX8SL3OSC_LBGSDQS_SHIFT #undef DDR_PHY_DX8SL3OSC_LBGSDQS_MASK -#define DDR_PHY_DX8SL3OSC_LBGSDQS_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL3OSC_LBGSDQS_SHIFT 20 -#define DDR_PHY_DX8SL3OSC_LBGSDQS_MASK 0x00100000U +#define DDR_PHY_DX8SL3OSC_LBGSDQS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_LBGSDQS_SHIFT 20 +#define DDR_PHY_DX8SL3OSC_LBGSDQS_MASK 0x00100000U -/*Loopback DQS Gating*/ +/* +* Loopback DQS Gating +*/ #undef DDR_PHY_DX8SL3OSC_LBGDQS_DEFVAL #undef DDR_PHY_DX8SL3OSC_LBGDQS_SHIFT #undef DDR_PHY_DX8SL3OSC_LBGDQS_MASK -#define DDR_PHY_DX8SL3OSC_LBGDQS_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL3OSC_LBGDQS_SHIFT 18 -#define DDR_PHY_DX8SL3OSC_LBGDQS_MASK 0x000C0000U +#define DDR_PHY_DX8SL3OSC_LBGDQS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_LBGDQS_SHIFT 18 +#define DDR_PHY_DX8SL3OSC_LBGDQS_MASK 0x000C0000U -/*Loopback DQS Shift*/ +/* +* Loopback DQS Shift +*/ #undef DDR_PHY_DX8SL3OSC_LBDQSS_DEFVAL #undef DDR_PHY_DX8SL3OSC_LBDQSS_SHIFT #undef DDR_PHY_DX8SL3OSC_LBDQSS_MASK -#define DDR_PHY_DX8SL3OSC_LBDQSS_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL3OSC_LBDQSS_SHIFT 17 -#define DDR_PHY_DX8SL3OSC_LBDQSS_MASK 0x00020000U +#define DDR_PHY_DX8SL3OSC_LBDQSS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_LBDQSS_SHIFT 17 +#define DDR_PHY_DX8SL3OSC_LBDQSS_MASK 0x00020000U -/*PHY High-Speed Reset*/ +/* +* PHY High-Speed Reset +*/ #undef DDR_PHY_DX8SL3OSC_PHYHRST_DEFVAL #undef DDR_PHY_DX8SL3OSC_PHYHRST_SHIFT #undef DDR_PHY_DX8SL3OSC_PHYHRST_MASK -#define DDR_PHY_DX8SL3OSC_PHYHRST_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL3OSC_PHYHRST_SHIFT 16 -#define DDR_PHY_DX8SL3OSC_PHYHRST_MASK 0x00010000U +#define DDR_PHY_DX8SL3OSC_PHYHRST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_PHYHRST_SHIFT 16 +#define DDR_PHY_DX8SL3OSC_PHYHRST_MASK 0x00010000U -/*PHY FIFO Reset*/ +/* +* PHY FIFO Reset +*/ #undef DDR_PHY_DX8SL3OSC_PHYFRST_DEFVAL #undef DDR_PHY_DX8SL3OSC_PHYFRST_SHIFT #undef DDR_PHY_DX8SL3OSC_PHYFRST_MASK -#define DDR_PHY_DX8SL3OSC_PHYFRST_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL3OSC_PHYFRST_SHIFT 15 -#define DDR_PHY_DX8SL3OSC_PHYFRST_MASK 0x00008000U +#define DDR_PHY_DX8SL3OSC_PHYFRST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_PHYFRST_SHIFT 15 +#define DDR_PHY_DX8SL3OSC_PHYFRST_MASK 0x00008000U -/*Delay Line Test Start*/ +/* +* Delay Line Test Start +*/ #undef DDR_PHY_DX8SL3OSC_DLTST_DEFVAL #undef DDR_PHY_DX8SL3OSC_DLTST_SHIFT #undef DDR_PHY_DX8SL3OSC_DLTST_MASK -#define DDR_PHY_DX8SL3OSC_DLTST_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL3OSC_DLTST_SHIFT 14 -#define DDR_PHY_DX8SL3OSC_DLTST_MASK 0x00004000U +#define DDR_PHY_DX8SL3OSC_DLTST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_DLTST_SHIFT 14 +#define DDR_PHY_DX8SL3OSC_DLTST_MASK 0x00004000U -/*Delay Line Test Mode*/ +/* +* Delay Line Test Mode +*/ #undef DDR_PHY_DX8SL3OSC_DLTMODE_DEFVAL #undef DDR_PHY_DX8SL3OSC_DLTMODE_SHIFT #undef DDR_PHY_DX8SL3OSC_DLTMODE_MASK -#define DDR_PHY_DX8SL3OSC_DLTMODE_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL3OSC_DLTMODE_SHIFT 13 -#define DDR_PHY_DX8SL3OSC_DLTMODE_MASK 0x00002000U +#define DDR_PHY_DX8SL3OSC_DLTMODE_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_DLTMODE_SHIFT 13 +#define DDR_PHY_DX8SL3OSC_DLTMODE_MASK 0x00002000U -/*Reserved. Caution, do not write to this register field.*/ +/* +* Reserved. Caution, do not write to this register field. +*/ #undef DDR_PHY_DX8SL3OSC_RESERVED_12_11_DEFVAL #undef DDR_PHY_DX8SL3OSC_RESERVED_12_11_SHIFT #undef DDR_PHY_DX8SL3OSC_RESERVED_12_11_MASK -#define DDR_PHY_DX8SL3OSC_RESERVED_12_11_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL3OSC_RESERVED_12_11_SHIFT 11 -#define DDR_PHY_DX8SL3OSC_RESERVED_12_11_MASK 0x00001800U +#define DDR_PHY_DX8SL3OSC_RESERVED_12_11_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_RESERVED_12_11_SHIFT 11 +#define DDR_PHY_DX8SL3OSC_RESERVED_12_11_MASK 0x00001800U -/*Oscillator Mode Write-Data Delay Line Select*/ +/* +* Oscillator Mode Write-Data Delay Line Select +*/ #undef DDR_PHY_DX8SL3OSC_OSCWDDL_DEFVAL #undef DDR_PHY_DX8SL3OSC_OSCWDDL_SHIFT #undef DDR_PHY_DX8SL3OSC_OSCWDDL_MASK -#define DDR_PHY_DX8SL3OSC_OSCWDDL_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL3OSC_OSCWDDL_SHIFT 9 -#define DDR_PHY_DX8SL3OSC_OSCWDDL_MASK 0x00000600U +#define DDR_PHY_DX8SL3OSC_OSCWDDL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_OSCWDDL_SHIFT 9 +#define DDR_PHY_DX8SL3OSC_OSCWDDL_MASK 0x00000600U -/*Reserved. Caution, do not write to this register field.*/ +/* +* Reserved. Caution, do not write to this register field. +*/ #undef DDR_PHY_DX8SL3OSC_RESERVED_8_7_DEFVAL #undef DDR_PHY_DX8SL3OSC_RESERVED_8_7_SHIFT #undef DDR_PHY_DX8SL3OSC_RESERVED_8_7_MASK -#define DDR_PHY_DX8SL3OSC_RESERVED_8_7_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL3OSC_RESERVED_8_7_SHIFT 7 -#define DDR_PHY_DX8SL3OSC_RESERVED_8_7_MASK 0x00000180U +#define DDR_PHY_DX8SL3OSC_RESERVED_8_7_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_RESERVED_8_7_SHIFT 7 +#define DDR_PHY_DX8SL3OSC_RESERVED_8_7_MASK 0x00000180U -/*Oscillator Mode Write-Leveling Delay Line Select*/ +/* +* Oscillator Mode Write-Leveling Delay Line Select +*/ #undef DDR_PHY_DX8SL3OSC_OSCWDL_DEFVAL #undef DDR_PHY_DX8SL3OSC_OSCWDL_SHIFT #undef DDR_PHY_DX8SL3OSC_OSCWDL_MASK -#define DDR_PHY_DX8SL3OSC_OSCWDL_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL3OSC_OSCWDL_SHIFT 5 -#define DDR_PHY_DX8SL3OSC_OSCWDL_MASK 0x00000060U +#define DDR_PHY_DX8SL3OSC_OSCWDL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_OSCWDL_SHIFT 5 +#define DDR_PHY_DX8SL3OSC_OSCWDL_MASK 0x00000060U -/*Oscillator Mode Division*/ +/* +* Oscillator Mode Division +*/ #undef DDR_PHY_DX8SL3OSC_OSCDIV_DEFVAL #undef DDR_PHY_DX8SL3OSC_OSCDIV_SHIFT #undef DDR_PHY_DX8SL3OSC_OSCDIV_MASK -#define DDR_PHY_DX8SL3OSC_OSCDIV_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL3OSC_OSCDIV_SHIFT 1 -#define DDR_PHY_DX8SL3OSC_OSCDIV_MASK 0x0000001EU +#define DDR_PHY_DX8SL3OSC_OSCDIV_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_OSCDIV_SHIFT 1 +#define DDR_PHY_DX8SL3OSC_OSCDIV_MASK 0x0000001EU -/*Oscillator Enable*/ +/* +* Oscillator Enable +*/ #undef DDR_PHY_DX8SL3OSC_OSCEN_DEFVAL #undef DDR_PHY_DX8SL3OSC_OSCEN_SHIFT #undef DDR_PHY_DX8SL3OSC_OSCEN_MASK -#define DDR_PHY_DX8SL3OSC_OSCEN_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL3OSC_OSCEN_SHIFT 0 -#define DDR_PHY_DX8SL3OSC_OSCEN_MASK 0x00000001U +#define DDR_PHY_DX8SL3OSC_OSCEN_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_OSCEN_SHIFT 0 +#define DDR_PHY_DX8SL3OSC_OSCEN_MASK 0x00000001U -/*Reserved. Return zeroes on reads.*/ +/* +* PLL Bypass +*/ +#undef DDR_PHY_DX8SL3PLLCR0_PLLBYP_DEFVAL +#undef DDR_PHY_DX8SL3PLLCR0_PLLBYP_SHIFT +#undef DDR_PHY_DX8SL3PLLCR0_PLLBYP_MASK +#define DDR_PHY_DX8SL3PLLCR0_PLLBYP_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL3PLLCR0_PLLBYP_SHIFT 31 +#define DDR_PHY_DX8SL3PLLCR0_PLLBYP_MASK 0x80000000U + +/* +* PLL Reset +*/ +#undef DDR_PHY_DX8SL3PLLCR0_PLLRST_DEFVAL +#undef DDR_PHY_DX8SL3PLLCR0_PLLRST_SHIFT +#undef DDR_PHY_DX8SL3PLLCR0_PLLRST_MASK +#define DDR_PHY_DX8SL3PLLCR0_PLLRST_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL3PLLCR0_PLLRST_SHIFT 30 +#define DDR_PHY_DX8SL3PLLCR0_PLLRST_MASK 0x40000000U + +/* +* PLL Power Down +*/ +#undef DDR_PHY_DX8SL3PLLCR0_PLLPD_DEFVAL +#undef DDR_PHY_DX8SL3PLLCR0_PLLPD_SHIFT +#undef DDR_PHY_DX8SL3PLLCR0_PLLPD_MASK +#define DDR_PHY_DX8SL3PLLCR0_PLLPD_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL3PLLCR0_PLLPD_SHIFT 29 +#define DDR_PHY_DX8SL3PLLCR0_PLLPD_MASK 0x20000000U + +/* +* Reference Stop Mode +*/ +#undef DDR_PHY_DX8SL3PLLCR0_RSTOPM_DEFVAL +#undef DDR_PHY_DX8SL3PLLCR0_RSTOPM_SHIFT +#undef DDR_PHY_DX8SL3PLLCR0_RSTOPM_MASK +#define DDR_PHY_DX8SL3PLLCR0_RSTOPM_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL3PLLCR0_RSTOPM_SHIFT 28 +#define DDR_PHY_DX8SL3PLLCR0_RSTOPM_MASK 0x10000000U + +/* +* PLL Frequency Select +*/ +#undef DDR_PHY_DX8SL3PLLCR0_FRQSEL_DEFVAL +#undef DDR_PHY_DX8SL3PLLCR0_FRQSEL_SHIFT +#undef DDR_PHY_DX8SL3PLLCR0_FRQSEL_MASK +#define DDR_PHY_DX8SL3PLLCR0_FRQSEL_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL3PLLCR0_FRQSEL_SHIFT 24 +#define DDR_PHY_DX8SL3PLLCR0_FRQSEL_MASK 0x0F000000U + +/* +* Relock Mode +*/ +#undef DDR_PHY_DX8SL3PLLCR0_RLOCKM_DEFVAL +#undef DDR_PHY_DX8SL3PLLCR0_RLOCKM_SHIFT +#undef DDR_PHY_DX8SL3PLLCR0_RLOCKM_MASK +#define DDR_PHY_DX8SL3PLLCR0_RLOCKM_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL3PLLCR0_RLOCKM_SHIFT 23 +#define DDR_PHY_DX8SL3PLLCR0_RLOCKM_MASK 0x00800000U + +/* +* Charge Pump Proportional Current Control +*/ +#undef DDR_PHY_DX8SL3PLLCR0_CPPC_DEFVAL +#undef DDR_PHY_DX8SL3PLLCR0_CPPC_SHIFT +#undef DDR_PHY_DX8SL3PLLCR0_CPPC_MASK +#define DDR_PHY_DX8SL3PLLCR0_CPPC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL3PLLCR0_CPPC_SHIFT 17 +#define DDR_PHY_DX8SL3PLLCR0_CPPC_MASK 0x007E0000U + +/* +* Charge Pump Integrating Current Control +*/ +#undef DDR_PHY_DX8SL3PLLCR0_CPIC_DEFVAL +#undef DDR_PHY_DX8SL3PLLCR0_CPIC_SHIFT +#undef DDR_PHY_DX8SL3PLLCR0_CPIC_MASK +#define DDR_PHY_DX8SL3PLLCR0_CPIC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL3PLLCR0_CPIC_SHIFT 13 +#define DDR_PHY_DX8SL3PLLCR0_CPIC_MASK 0x0001E000U + +/* +* Gear Shift +*/ +#undef DDR_PHY_DX8SL3PLLCR0_GSHIFT_DEFVAL +#undef DDR_PHY_DX8SL3PLLCR0_GSHIFT_SHIFT +#undef DDR_PHY_DX8SL3PLLCR0_GSHIFT_MASK +#define DDR_PHY_DX8SL3PLLCR0_GSHIFT_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL3PLLCR0_GSHIFT_SHIFT 12 +#define DDR_PHY_DX8SL3PLLCR0_GSHIFT_MASK 0x00001000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL3PLLCR0_RESERVED_11_9_DEFVAL +#undef DDR_PHY_DX8SL3PLLCR0_RESERVED_11_9_SHIFT +#undef DDR_PHY_DX8SL3PLLCR0_RESERVED_11_9_MASK +#define DDR_PHY_DX8SL3PLLCR0_RESERVED_11_9_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL3PLLCR0_RESERVED_11_9_SHIFT 9 +#define DDR_PHY_DX8SL3PLLCR0_RESERVED_11_9_MASK 0x00000E00U + +/* +* Analog Test Enable (ATOEN) +*/ +#undef DDR_PHY_DX8SL3PLLCR0_ATOEN_DEFVAL +#undef DDR_PHY_DX8SL3PLLCR0_ATOEN_SHIFT +#undef DDR_PHY_DX8SL3PLLCR0_ATOEN_MASK +#define DDR_PHY_DX8SL3PLLCR0_ATOEN_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL3PLLCR0_ATOEN_SHIFT 8 +#define DDR_PHY_DX8SL3PLLCR0_ATOEN_MASK 0x00000100U + +/* +* Analog Test Control +*/ +#undef DDR_PHY_DX8SL3PLLCR0_ATC_DEFVAL +#undef DDR_PHY_DX8SL3PLLCR0_ATC_SHIFT +#undef DDR_PHY_DX8SL3PLLCR0_ATC_MASK +#define DDR_PHY_DX8SL3PLLCR0_ATC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL3PLLCR0_ATC_SHIFT 4 +#define DDR_PHY_DX8SL3PLLCR0_ATC_MASK 0x000000F0U + +/* +* Digital Test Control +*/ +#undef DDR_PHY_DX8SL3PLLCR0_DTC_DEFVAL +#undef DDR_PHY_DX8SL3PLLCR0_DTC_SHIFT +#undef DDR_PHY_DX8SL3PLLCR0_DTC_MASK +#define DDR_PHY_DX8SL3PLLCR0_DTC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL3PLLCR0_DTC_SHIFT 0 +#define DDR_PHY_DX8SL3PLLCR0_DTC_MASK 0x0000000FU + +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_DEFVAL #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_SHIFT #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_MASK -#define DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_SHIFT 25 -#define DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_MASK 0xFE000000U +#define DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_SHIFT 25 +#define DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_MASK 0xFE000000U -/*Read Path Rise-to-Rise Mode*/ +/* +* Read Path Rise-to-Rise Mode +*/ #undef DDR_PHY_DX8SL3DQSCTL_RRRMODE_DEFVAL #undef DDR_PHY_DX8SL3DQSCTL_RRRMODE_SHIFT #undef DDR_PHY_DX8SL3DQSCTL_RRRMODE_MASK -#define DDR_PHY_DX8SL3DQSCTL_RRRMODE_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL3DQSCTL_RRRMODE_SHIFT 24 -#define DDR_PHY_DX8SL3DQSCTL_RRRMODE_MASK 0x01000000U +#define DDR_PHY_DX8SL3DQSCTL_RRRMODE_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL3DQSCTL_RRRMODE_SHIFT 24 +#define DDR_PHY_DX8SL3DQSCTL_RRRMODE_MASK 0x01000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_DEFVAL #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_SHIFT #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_MASK -#define DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_SHIFT 22 -#define DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_MASK 0x00C00000U +#define DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_MASK 0x00C00000U -/*Write Path Rise-to-Rise Mode*/ +/* +* Write Path Rise-to-Rise Mode +*/ #undef DDR_PHY_DX8SL3DQSCTL_WRRMODE_DEFVAL #undef DDR_PHY_DX8SL3DQSCTL_WRRMODE_SHIFT #undef DDR_PHY_DX8SL3DQSCTL_WRRMODE_MASK -#define DDR_PHY_DX8SL3DQSCTL_WRRMODE_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL3DQSCTL_WRRMODE_SHIFT 21 -#define DDR_PHY_DX8SL3DQSCTL_WRRMODE_MASK 0x00200000U +#define DDR_PHY_DX8SL3DQSCTL_WRRMODE_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL3DQSCTL_WRRMODE_SHIFT 21 +#define DDR_PHY_DX8SL3DQSCTL_WRRMODE_MASK 0x00200000U -/*DQS Gate Extension*/ +/* +* DQS Gate Extension +*/ #undef DDR_PHY_DX8SL3DQSCTL_DQSGX_DEFVAL #undef DDR_PHY_DX8SL3DQSCTL_DQSGX_SHIFT #undef DDR_PHY_DX8SL3DQSCTL_DQSGX_MASK -#define DDR_PHY_DX8SL3DQSCTL_DQSGX_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL3DQSCTL_DQSGX_SHIFT 19 -#define DDR_PHY_DX8SL3DQSCTL_DQSGX_MASK 0x00180000U +#define DDR_PHY_DX8SL3DQSCTL_DQSGX_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL3DQSCTL_DQSGX_SHIFT 19 +#define DDR_PHY_DX8SL3DQSCTL_DQSGX_MASK 0x00180000U -/*Low Power PLL Power Down*/ +/* +* Low Power PLL Power Down +*/ #undef DDR_PHY_DX8SL3DQSCTL_LPPLLPD_DEFVAL #undef DDR_PHY_DX8SL3DQSCTL_LPPLLPD_SHIFT #undef DDR_PHY_DX8SL3DQSCTL_LPPLLPD_MASK -#define DDR_PHY_DX8SL3DQSCTL_LPPLLPD_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL3DQSCTL_LPPLLPD_SHIFT 18 -#define DDR_PHY_DX8SL3DQSCTL_LPPLLPD_MASK 0x00040000U +#define DDR_PHY_DX8SL3DQSCTL_LPPLLPD_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL3DQSCTL_LPPLLPD_SHIFT 18 +#define DDR_PHY_DX8SL3DQSCTL_LPPLLPD_MASK 0x00040000U -/*Low Power I/O Power Down*/ +/* +* Low Power I/O Power Down +*/ #undef DDR_PHY_DX8SL3DQSCTL_LPIOPD_DEFVAL #undef DDR_PHY_DX8SL3DQSCTL_LPIOPD_SHIFT #undef DDR_PHY_DX8SL3DQSCTL_LPIOPD_MASK -#define DDR_PHY_DX8SL3DQSCTL_LPIOPD_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL3DQSCTL_LPIOPD_SHIFT 17 -#define DDR_PHY_DX8SL3DQSCTL_LPIOPD_MASK 0x00020000U +#define DDR_PHY_DX8SL3DQSCTL_LPIOPD_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL3DQSCTL_LPIOPD_SHIFT 17 +#define DDR_PHY_DX8SL3DQSCTL_LPIOPD_MASK 0x00020000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_DEFVAL #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_SHIFT #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_MASK -#define DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_SHIFT 15 -#define DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_MASK 0x00018000U +#define DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_SHIFT 15 +#define DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_MASK 0x00018000U -/*QS Counter Enable*/ +/* +* QS Counter Enable +*/ #undef DDR_PHY_DX8SL3DQSCTL_QSCNTEN_DEFVAL #undef DDR_PHY_DX8SL3DQSCTL_QSCNTEN_SHIFT #undef DDR_PHY_DX8SL3DQSCTL_QSCNTEN_MASK -#define DDR_PHY_DX8SL3DQSCTL_QSCNTEN_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL3DQSCTL_QSCNTEN_SHIFT 14 -#define DDR_PHY_DX8SL3DQSCTL_QSCNTEN_MASK 0x00004000U +#define DDR_PHY_DX8SL3DQSCTL_QSCNTEN_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL3DQSCTL_QSCNTEN_SHIFT 14 +#define DDR_PHY_DX8SL3DQSCTL_QSCNTEN_MASK 0x00004000U -/*Unused DQ I/O Mode*/ +/* +* Unused DQ I/O Mode +*/ #undef DDR_PHY_DX8SL3DQSCTL_UDQIOM_DEFVAL #undef DDR_PHY_DX8SL3DQSCTL_UDQIOM_SHIFT #undef DDR_PHY_DX8SL3DQSCTL_UDQIOM_MASK -#define DDR_PHY_DX8SL3DQSCTL_UDQIOM_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL3DQSCTL_UDQIOM_SHIFT 13 -#define DDR_PHY_DX8SL3DQSCTL_UDQIOM_MASK 0x00002000U +#define DDR_PHY_DX8SL3DQSCTL_UDQIOM_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL3DQSCTL_UDQIOM_SHIFT 13 +#define DDR_PHY_DX8SL3DQSCTL_UDQIOM_MASK 0x00002000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_DEFVAL #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_SHIFT #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_MASK -#define DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_SHIFT 10 -#define DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_MASK 0x00001C00U +#define DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_SHIFT 10 +#define DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_MASK 0x00001C00U -/*Data Slew Rate*/ +/* +* Data Slew Rate +*/ #undef DDR_PHY_DX8SL3DQSCTL_DXSR_DEFVAL #undef DDR_PHY_DX8SL3DQSCTL_DXSR_SHIFT #undef DDR_PHY_DX8SL3DQSCTL_DXSR_MASK -#define DDR_PHY_DX8SL3DQSCTL_DXSR_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL3DQSCTL_DXSR_SHIFT 8 -#define DDR_PHY_DX8SL3DQSCTL_DXSR_MASK 0x00000300U +#define DDR_PHY_DX8SL3DQSCTL_DXSR_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL3DQSCTL_DXSR_SHIFT 8 +#define DDR_PHY_DX8SL3DQSCTL_DXSR_MASK 0x00000300U -/*DQS_N Resistor*/ +/* +* DQS_N Resistor +*/ #undef DDR_PHY_DX8SL3DQSCTL_DQSNRES_DEFVAL #undef DDR_PHY_DX8SL3DQSCTL_DQSNRES_SHIFT #undef DDR_PHY_DX8SL3DQSCTL_DQSNRES_MASK -#define DDR_PHY_DX8SL3DQSCTL_DQSNRES_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL3DQSCTL_DQSNRES_SHIFT 4 -#define DDR_PHY_DX8SL3DQSCTL_DQSNRES_MASK 0x000000F0U +#define DDR_PHY_DX8SL3DQSCTL_DQSNRES_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL3DQSCTL_DQSNRES_SHIFT 4 +#define DDR_PHY_DX8SL3DQSCTL_DQSNRES_MASK 0x000000F0U -/*DQS Resistor*/ +/* +* DQS Resistor +*/ #undef DDR_PHY_DX8SL3DQSCTL_DQSRES_DEFVAL #undef DDR_PHY_DX8SL3DQSCTL_DQSRES_SHIFT #undef DDR_PHY_DX8SL3DQSCTL_DQSRES_MASK -#define DDR_PHY_DX8SL3DQSCTL_DQSRES_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL3DQSCTL_DQSRES_SHIFT 0 -#define DDR_PHY_DX8SL3DQSCTL_DQSRES_MASK 0x0000000FU +#define DDR_PHY_DX8SL3DQSCTL_DQSRES_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL3DQSCTL_DQSRES_SHIFT 0 +#define DDR_PHY_DX8SL3DQSCTL_DQSRES_MASK 0x0000000FU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_DEFVAL #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_SHIFT #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_MASK -#define DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_SHIFT 24 -#define DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_MASK 0xFF000000U +#define DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_SHIFT 24 +#define DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_MASK 0xFF000000U -/*Configurable Read Data Enable*/ +/* +* Configurable Read Data Enable +*/ #undef DDR_PHY_DX8SL3DXCTL2_CRDEN_DEFVAL #undef DDR_PHY_DX8SL3DXCTL2_CRDEN_SHIFT #undef DDR_PHY_DX8SL3DXCTL2_CRDEN_MASK -#define DDR_PHY_DX8SL3DXCTL2_CRDEN_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL3DXCTL2_CRDEN_SHIFT 23 -#define DDR_PHY_DX8SL3DXCTL2_CRDEN_MASK 0x00800000U +#define DDR_PHY_DX8SL3DXCTL2_CRDEN_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_CRDEN_SHIFT 23 +#define DDR_PHY_DX8SL3DXCTL2_CRDEN_MASK 0x00800000U -/*OX Extension during Post-amble*/ +/* +* OX Extension during Post-amble +*/ #undef DDR_PHY_DX8SL3DXCTL2_POSOEX_DEFVAL #undef DDR_PHY_DX8SL3DXCTL2_POSOEX_SHIFT #undef DDR_PHY_DX8SL3DXCTL2_POSOEX_MASK -#define DDR_PHY_DX8SL3DXCTL2_POSOEX_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL3DXCTL2_POSOEX_SHIFT 20 -#define DDR_PHY_DX8SL3DXCTL2_POSOEX_MASK 0x00700000U +#define DDR_PHY_DX8SL3DXCTL2_POSOEX_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_POSOEX_SHIFT 20 +#define DDR_PHY_DX8SL3DXCTL2_POSOEX_MASK 0x00700000U -/*OE Extension during Pre-amble*/ +/* +* OE Extension during Pre-amble +*/ #undef DDR_PHY_DX8SL3DXCTL2_PREOEX_DEFVAL #undef DDR_PHY_DX8SL3DXCTL2_PREOEX_SHIFT #undef DDR_PHY_DX8SL3DXCTL2_PREOEX_MASK -#define DDR_PHY_DX8SL3DXCTL2_PREOEX_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL3DXCTL2_PREOEX_SHIFT 18 -#define DDR_PHY_DX8SL3DXCTL2_PREOEX_MASK 0x000C0000U +#define DDR_PHY_DX8SL3DXCTL2_PREOEX_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_PREOEX_SHIFT 18 +#define DDR_PHY_DX8SL3DXCTL2_PREOEX_MASK 0x000C0000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_17_DEFVAL #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_17_SHIFT #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_17_MASK -#define DDR_PHY_DX8SL3DXCTL2_RESERVED_17_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL3DXCTL2_RESERVED_17_SHIFT 17 -#define DDR_PHY_DX8SL3DXCTL2_RESERVED_17_MASK 0x00020000U +#define DDR_PHY_DX8SL3DXCTL2_RESERVED_17_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_RESERVED_17_SHIFT 17 +#define DDR_PHY_DX8SL3DXCTL2_RESERVED_17_MASK 0x00020000U -/*I/O Assisted Gate Select*/ +/* +* I/O Assisted Gate Select +*/ #undef DDR_PHY_DX8SL3DXCTL2_IOAG_DEFVAL #undef DDR_PHY_DX8SL3DXCTL2_IOAG_SHIFT #undef DDR_PHY_DX8SL3DXCTL2_IOAG_MASK -#define DDR_PHY_DX8SL3DXCTL2_IOAG_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL3DXCTL2_IOAG_SHIFT 16 -#define DDR_PHY_DX8SL3DXCTL2_IOAG_MASK 0x00010000U +#define DDR_PHY_DX8SL3DXCTL2_IOAG_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_IOAG_SHIFT 16 +#define DDR_PHY_DX8SL3DXCTL2_IOAG_MASK 0x00010000U -/*I/O Loopback Select*/ +/* +* I/O Loopback Select +*/ #undef DDR_PHY_DX8SL3DXCTL2_IOLB_DEFVAL #undef DDR_PHY_DX8SL3DXCTL2_IOLB_SHIFT #undef DDR_PHY_DX8SL3DXCTL2_IOLB_MASK -#define DDR_PHY_DX8SL3DXCTL2_IOLB_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL3DXCTL2_IOLB_SHIFT 15 -#define DDR_PHY_DX8SL3DXCTL2_IOLB_MASK 0x00008000U +#define DDR_PHY_DX8SL3DXCTL2_IOLB_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_IOLB_SHIFT 15 +#define DDR_PHY_DX8SL3DXCTL2_IOLB_MASK 0x00008000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_DEFVAL #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_SHIFT #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_MASK -#define DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_SHIFT 13 -#define DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_MASK 0x00006000U +#define DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_SHIFT 13 +#define DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_MASK 0x00006000U -/*Low Power Wakeup Threshold*/ +/* +* Low Power Wakeup Threshold +*/ #undef DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_DEFVAL #undef DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_SHIFT #undef DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_MASK -#define DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_SHIFT 9 -#define DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_MASK 0x00001E00U +#define DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_SHIFT 9 +#define DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_MASK 0x00001E00U -/*Read Data Bus Inversion Enable*/ +/* +* Read Data Bus Inversion Enable +*/ #undef DDR_PHY_DX8SL3DXCTL2_RDBI_DEFVAL #undef DDR_PHY_DX8SL3DXCTL2_RDBI_SHIFT #undef DDR_PHY_DX8SL3DXCTL2_RDBI_MASK -#define DDR_PHY_DX8SL3DXCTL2_RDBI_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL3DXCTL2_RDBI_SHIFT 8 -#define DDR_PHY_DX8SL3DXCTL2_RDBI_MASK 0x00000100U +#define DDR_PHY_DX8SL3DXCTL2_RDBI_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_RDBI_SHIFT 8 +#define DDR_PHY_DX8SL3DXCTL2_RDBI_MASK 0x00000100U -/*Write Data Bus Inversion Enable*/ +/* +* Write Data Bus Inversion Enable +*/ #undef DDR_PHY_DX8SL3DXCTL2_WDBI_DEFVAL #undef DDR_PHY_DX8SL3DXCTL2_WDBI_SHIFT #undef DDR_PHY_DX8SL3DXCTL2_WDBI_MASK -#define DDR_PHY_DX8SL3DXCTL2_WDBI_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL3DXCTL2_WDBI_SHIFT 7 -#define DDR_PHY_DX8SL3DXCTL2_WDBI_MASK 0x00000080U +#define DDR_PHY_DX8SL3DXCTL2_WDBI_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_WDBI_SHIFT 7 +#define DDR_PHY_DX8SL3DXCTL2_WDBI_MASK 0x00000080U -/*PUB Read FIFO Bypass*/ +/* +* PUB Read FIFO Bypass +*/ #undef DDR_PHY_DX8SL3DXCTL2_PRFBYP_DEFVAL #undef DDR_PHY_DX8SL3DXCTL2_PRFBYP_SHIFT #undef DDR_PHY_DX8SL3DXCTL2_PRFBYP_MASK -#define DDR_PHY_DX8SL3DXCTL2_PRFBYP_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL3DXCTL2_PRFBYP_SHIFT 6 -#define DDR_PHY_DX8SL3DXCTL2_PRFBYP_MASK 0x00000040U +#define DDR_PHY_DX8SL3DXCTL2_PRFBYP_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_PRFBYP_SHIFT 6 +#define DDR_PHY_DX8SL3DXCTL2_PRFBYP_MASK 0x00000040U -/*DATX8 Receive FIFO Read Mode*/ +/* +* DATX8 Receive FIFO Read Mode +*/ #undef DDR_PHY_DX8SL3DXCTL2_RDMODE_DEFVAL #undef DDR_PHY_DX8SL3DXCTL2_RDMODE_SHIFT #undef DDR_PHY_DX8SL3DXCTL2_RDMODE_MASK -#define DDR_PHY_DX8SL3DXCTL2_RDMODE_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL3DXCTL2_RDMODE_SHIFT 4 -#define DDR_PHY_DX8SL3DXCTL2_RDMODE_MASK 0x00000030U +#define DDR_PHY_DX8SL3DXCTL2_RDMODE_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_RDMODE_SHIFT 4 +#define DDR_PHY_DX8SL3DXCTL2_RDMODE_MASK 0x00000030U -/*Disables the Read FIFO Reset*/ +/* +* Disables the Read FIFO Reset +*/ #undef DDR_PHY_DX8SL3DXCTL2_DISRST_DEFVAL #undef DDR_PHY_DX8SL3DXCTL2_DISRST_SHIFT #undef DDR_PHY_DX8SL3DXCTL2_DISRST_MASK -#define DDR_PHY_DX8SL3DXCTL2_DISRST_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL3DXCTL2_DISRST_SHIFT 3 -#define DDR_PHY_DX8SL3DXCTL2_DISRST_MASK 0x00000008U +#define DDR_PHY_DX8SL3DXCTL2_DISRST_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_DISRST_SHIFT 3 +#define DDR_PHY_DX8SL3DXCTL2_DISRST_MASK 0x00000008U -/*Read DQS Gate I/O Loopback*/ +/* +* Read DQS Gate I/O Loopback +*/ #undef DDR_PHY_DX8SL3DXCTL2_DQSGLB_DEFVAL #undef DDR_PHY_DX8SL3DXCTL2_DQSGLB_SHIFT #undef DDR_PHY_DX8SL3DXCTL2_DQSGLB_MASK -#define DDR_PHY_DX8SL3DXCTL2_DQSGLB_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL3DXCTL2_DQSGLB_SHIFT 1 -#define DDR_PHY_DX8SL3DXCTL2_DQSGLB_MASK 0x00000006U +#define DDR_PHY_DX8SL3DXCTL2_DQSGLB_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_DQSGLB_SHIFT 1 +#define DDR_PHY_DX8SL3DXCTL2_DQSGLB_MASK 0x00000006U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_0_DEFVAL #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_0_SHIFT #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_0_MASK -#define DDR_PHY_DX8SL3DXCTL2_RESERVED_0_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL3DXCTL2_RESERVED_0_SHIFT 0 -#define DDR_PHY_DX8SL3DXCTL2_RESERVED_0_MASK 0x00000001U +#define DDR_PHY_DX8SL3DXCTL2_RESERVED_0_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_RESERVED_0_SHIFT 0 +#define DDR_PHY_DX8SL3DXCTL2_RESERVED_0_MASK 0x00000001U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL3IOCR_RESERVED_31_DEFVAL #undef DDR_PHY_DX8SL3IOCR_RESERVED_31_SHIFT #undef DDR_PHY_DX8SL3IOCR_RESERVED_31_MASK -#define DDR_PHY_DX8SL3IOCR_RESERVED_31_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL3IOCR_RESERVED_31_SHIFT 31 -#define DDR_PHY_DX8SL3IOCR_RESERVED_31_MASK 0x80000000U +#define DDR_PHY_DX8SL3IOCR_RESERVED_31_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL3IOCR_RESERVED_31_SHIFT 31 +#define DDR_PHY_DX8SL3IOCR_RESERVED_31_MASK 0x80000000U -/*PVREF_DAC REFSEL range select*/ +/* +* PVREF_DAC REFSEL range select +*/ #undef DDR_PHY_DX8SL3IOCR_DXDACRANGE_DEFVAL #undef DDR_PHY_DX8SL3IOCR_DXDACRANGE_SHIFT #undef DDR_PHY_DX8SL3IOCR_DXDACRANGE_MASK -#define DDR_PHY_DX8SL3IOCR_DXDACRANGE_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL3IOCR_DXDACRANGE_SHIFT 28 -#define DDR_PHY_DX8SL3IOCR_DXDACRANGE_MASK 0x70000000U +#define DDR_PHY_DX8SL3IOCR_DXDACRANGE_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL3IOCR_DXDACRANGE_SHIFT 28 +#define DDR_PHY_DX8SL3IOCR_DXDACRANGE_MASK 0x70000000U -/*IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring*/ +/* +* IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring +*/ #undef DDR_PHY_DX8SL3IOCR_DXVREFIOM_DEFVAL #undef DDR_PHY_DX8SL3IOCR_DXVREFIOM_SHIFT #undef DDR_PHY_DX8SL3IOCR_DXVREFIOM_MASK -#define DDR_PHY_DX8SL3IOCR_DXVREFIOM_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL3IOCR_DXVREFIOM_SHIFT 25 -#define DDR_PHY_DX8SL3IOCR_DXVREFIOM_MASK 0x0E000000U +#define DDR_PHY_DX8SL3IOCR_DXVREFIOM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL3IOCR_DXVREFIOM_SHIFT 25 +#define DDR_PHY_DX8SL3IOCR_DXVREFIOM_MASK 0x0E000000U -/*DX IO Mode*/ +/* +* DX IO Mode +*/ #undef DDR_PHY_DX8SL3IOCR_DXIOM_DEFVAL #undef DDR_PHY_DX8SL3IOCR_DXIOM_SHIFT #undef DDR_PHY_DX8SL3IOCR_DXIOM_MASK -#define DDR_PHY_DX8SL3IOCR_DXIOM_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL3IOCR_DXIOM_SHIFT 22 -#define DDR_PHY_DX8SL3IOCR_DXIOM_MASK 0x01C00000U +#define DDR_PHY_DX8SL3IOCR_DXIOM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL3IOCR_DXIOM_SHIFT 22 +#define DDR_PHY_DX8SL3IOCR_DXIOM_MASK 0x01C00000U -/*DX IO Transmitter Mode*/ +/* +* DX IO Transmitter Mode +*/ #undef DDR_PHY_DX8SL3IOCR_DXTXM_DEFVAL #undef DDR_PHY_DX8SL3IOCR_DXTXM_SHIFT #undef DDR_PHY_DX8SL3IOCR_DXTXM_MASK -#define DDR_PHY_DX8SL3IOCR_DXTXM_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL3IOCR_DXTXM_SHIFT 11 -#define DDR_PHY_DX8SL3IOCR_DXTXM_MASK 0x003FF800U +#define DDR_PHY_DX8SL3IOCR_DXTXM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL3IOCR_DXTXM_SHIFT 11 +#define DDR_PHY_DX8SL3IOCR_DXTXM_MASK 0x003FF800U -/*DX IO Receiver Mode*/ +/* +* DX IO Receiver Mode +*/ #undef DDR_PHY_DX8SL3IOCR_DXRXM_DEFVAL #undef DDR_PHY_DX8SL3IOCR_DXRXM_SHIFT #undef DDR_PHY_DX8SL3IOCR_DXRXM_MASK -#define DDR_PHY_DX8SL3IOCR_DXRXM_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL3IOCR_DXRXM_SHIFT 0 -#define DDR_PHY_DX8SL3IOCR_DXRXM_MASK 0x000007FFU +#define DDR_PHY_DX8SL3IOCR_DXRXM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL3IOCR_DXRXM_SHIFT 0 +#define DDR_PHY_DX8SL3IOCR_DXRXM_MASK 0x000007FFU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL4OSC_RESERVED_31_30_DEFVAL #undef DDR_PHY_DX8SL4OSC_RESERVED_31_30_SHIFT #undef DDR_PHY_DX8SL4OSC_RESERVED_31_30_MASK -#define DDR_PHY_DX8SL4OSC_RESERVED_31_30_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL4OSC_RESERVED_31_30_SHIFT 30 -#define DDR_PHY_DX8SL4OSC_RESERVED_31_30_MASK 0xC0000000U +#define DDR_PHY_DX8SL4OSC_RESERVED_31_30_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX8SL4OSC_RESERVED_31_30_MASK 0xC0000000U -/*Enable Clock Gating for DX ddr_clk*/ +/* +* Enable Clock Gating for DX ddr_clk +*/ #undef DDR_PHY_DX8SL4OSC_GATEDXRDCLK_DEFVAL #undef DDR_PHY_DX8SL4OSC_GATEDXRDCLK_SHIFT #undef DDR_PHY_DX8SL4OSC_GATEDXRDCLK_MASK -#define DDR_PHY_DX8SL4OSC_GATEDXRDCLK_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL4OSC_GATEDXRDCLK_SHIFT 28 -#define DDR_PHY_DX8SL4OSC_GATEDXRDCLK_MASK 0x30000000U +#define DDR_PHY_DX8SL4OSC_GATEDXRDCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_GATEDXRDCLK_SHIFT 28 +#define DDR_PHY_DX8SL4OSC_GATEDXRDCLK_MASK 0x30000000U -/*Enable Clock Gating for DX ctl_rd_clk*/ +/* +* Enable Clock Gating for DX ctl_rd_clk +*/ #undef DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_DEFVAL #undef DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_SHIFT #undef DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_MASK -#define DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_SHIFT 26 -#define DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_MASK 0x0C000000U +#define DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_SHIFT 26 +#define DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_MASK 0x0C000000U -/*Enable Clock Gating for DX ctl_clk*/ +/* +* Enable Clock Gating for DX ctl_clk +*/ #undef DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_DEFVAL #undef DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_SHIFT #undef DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_MASK -#define DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_SHIFT 24 -#define DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_MASK 0x03000000U +#define DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_SHIFT 24 +#define DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_MASK 0x03000000U -/*Selects the level to which clocks will be stalled when clock gating is enabled.*/ +/* +* Selects the level to which clocks will be stalled when clock gating is e + * nabled. +*/ #undef DDR_PHY_DX8SL4OSC_CLKLEVEL_DEFVAL #undef DDR_PHY_DX8SL4OSC_CLKLEVEL_SHIFT #undef DDR_PHY_DX8SL4OSC_CLKLEVEL_MASK -#define DDR_PHY_DX8SL4OSC_CLKLEVEL_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL4OSC_CLKLEVEL_SHIFT 22 -#define DDR_PHY_DX8SL4OSC_CLKLEVEL_MASK 0x00C00000U +#define DDR_PHY_DX8SL4OSC_CLKLEVEL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_CLKLEVEL_SHIFT 22 +#define DDR_PHY_DX8SL4OSC_CLKLEVEL_MASK 0x00C00000U -/*Loopback Mode*/ +/* +* Loopback Mode +*/ #undef DDR_PHY_DX8SL4OSC_LBMODE_DEFVAL #undef DDR_PHY_DX8SL4OSC_LBMODE_SHIFT #undef DDR_PHY_DX8SL4OSC_LBMODE_MASK -#define DDR_PHY_DX8SL4OSC_LBMODE_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL4OSC_LBMODE_SHIFT 21 -#define DDR_PHY_DX8SL4OSC_LBMODE_MASK 0x00200000U +#define DDR_PHY_DX8SL4OSC_LBMODE_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_LBMODE_SHIFT 21 +#define DDR_PHY_DX8SL4OSC_LBMODE_MASK 0x00200000U -/*Load GSDQS LCDL with 2x the calibrated GSDQSPRD value*/ +/* +* Load GSDQS LCDL with 2x the calibrated GSDQSPRD value +*/ #undef DDR_PHY_DX8SL4OSC_LBGSDQS_DEFVAL #undef DDR_PHY_DX8SL4OSC_LBGSDQS_SHIFT #undef DDR_PHY_DX8SL4OSC_LBGSDQS_MASK -#define DDR_PHY_DX8SL4OSC_LBGSDQS_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL4OSC_LBGSDQS_SHIFT 20 -#define DDR_PHY_DX8SL4OSC_LBGSDQS_MASK 0x00100000U +#define DDR_PHY_DX8SL4OSC_LBGSDQS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_LBGSDQS_SHIFT 20 +#define DDR_PHY_DX8SL4OSC_LBGSDQS_MASK 0x00100000U -/*Loopback DQS Gating*/ +/* +* Loopback DQS Gating +*/ #undef DDR_PHY_DX8SL4OSC_LBGDQS_DEFVAL #undef DDR_PHY_DX8SL4OSC_LBGDQS_SHIFT #undef DDR_PHY_DX8SL4OSC_LBGDQS_MASK -#define DDR_PHY_DX8SL4OSC_LBGDQS_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL4OSC_LBGDQS_SHIFT 18 -#define DDR_PHY_DX8SL4OSC_LBGDQS_MASK 0x000C0000U +#define DDR_PHY_DX8SL4OSC_LBGDQS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_LBGDQS_SHIFT 18 +#define DDR_PHY_DX8SL4OSC_LBGDQS_MASK 0x000C0000U -/*Loopback DQS Shift*/ +/* +* Loopback DQS Shift +*/ #undef DDR_PHY_DX8SL4OSC_LBDQSS_DEFVAL #undef DDR_PHY_DX8SL4OSC_LBDQSS_SHIFT #undef DDR_PHY_DX8SL4OSC_LBDQSS_MASK -#define DDR_PHY_DX8SL4OSC_LBDQSS_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL4OSC_LBDQSS_SHIFT 17 -#define DDR_PHY_DX8SL4OSC_LBDQSS_MASK 0x00020000U +#define DDR_PHY_DX8SL4OSC_LBDQSS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_LBDQSS_SHIFT 17 +#define DDR_PHY_DX8SL4OSC_LBDQSS_MASK 0x00020000U -/*PHY High-Speed Reset*/ +/* +* PHY High-Speed Reset +*/ #undef DDR_PHY_DX8SL4OSC_PHYHRST_DEFVAL #undef DDR_PHY_DX8SL4OSC_PHYHRST_SHIFT #undef DDR_PHY_DX8SL4OSC_PHYHRST_MASK -#define DDR_PHY_DX8SL4OSC_PHYHRST_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL4OSC_PHYHRST_SHIFT 16 -#define DDR_PHY_DX8SL4OSC_PHYHRST_MASK 0x00010000U +#define DDR_PHY_DX8SL4OSC_PHYHRST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_PHYHRST_SHIFT 16 +#define DDR_PHY_DX8SL4OSC_PHYHRST_MASK 0x00010000U -/*PHY FIFO Reset*/ +/* +* PHY FIFO Reset +*/ #undef DDR_PHY_DX8SL4OSC_PHYFRST_DEFVAL #undef DDR_PHY_DX8SL4OSC_PHYFRST_SHIFT #undef DDR_PHY_DX8SL4OSC_PHYFRST_MASK -#define DDR_PHY_DX8SL4OSC_PHYFRST_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL4OSC_PHYFRST_SHIFT 15 -#define DDR_PHY_DX8SL4OSC_PHYFRST_MASK 0x00008000U +#define DDR_PHY_DX8SL4OSC_PHYFRST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_PHYFRST_SHIFT 15 +#define DDR_PHY_DX8SL4OSC_PHYFRST_MASK 0x00008000U -/*Delay Line Test Start*/ +/* +* Delay Line Test Start +*/ #undef DDR_PHY_DX8SL4OSC_DLTST_DEFVAL #undef DDR_PHY_DX8SL4OSC_DLTST_SHIFT #undef DDR_PHY_DX8SL4OSC_DLTST_MASK -#define DDR_PHY_DX8SL4OSC_DLTST_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL4OSC_DLTST_SHIFT 14 -#define DDR_PHY_DX8SL4OSC_DLTST_MASK 0x00004000U +#define DDR_PHY_DX8SL4OSC_DLTST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_DLTST_SHIFT 14 +#define DDR_PHY_DX8SL4OSC_DLTST_MASK 0x00004000U -/*Delay Line Test Mode*/ +/* +* Delay Line Test Mode +*/ #undef DDR_PHY_DX8SL4OSC_DLTMODE_DEFVAL #undef DDR_PHY_DX8SL4OSC_DLTMODE_SHIFT #undef DDR_PHY_DX8SL4OSC_DLTMODE_MASK -#define DDR_PHY_DX8SL4OSC_DLTMODE_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL4OSC_DLTMODE_SHIFT 13 -#define DDR_PHY_DX8SL4OSC_DLTMODE_MASK 0x00002000U +#define DDR_PHY_DX8SL4OSC_DLTMODE_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_DLTMODE_SHIFT 13 +#define DDR_PHY_DX8SL4OSC_DLTMODE_MASK 0x00002000U -/*Reserved. Caution, do not write to this register field.*/ +/* +* Reserved. Caution, do not write to this register field. +*/ #undef DDR_PHY_DX8SL4OSC_RESERVED_12_11_DEFVAL #undef DDR_PHY_DX8SL4OSC_RESERVED_12_11_SHIFT #undef DDR_PHY_DX8SL4OSC_RESERVED_12_11_MASK -#define DDR_PHY_DX8SL4OSC_RESERVED_12_11_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL4OSC_RESERVED_12_11_SHIFT 11 -#define DDR_PHY_DX8SL4OSC_RESERVED_12_11_MASK 0x00001800U +#define DDR_PHY_DX8SL4OSC_RESERVED_12_11_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_RESERVED_12_11_SHIFT 11 +#define DDR_PHY_DX8SL4OSC_RESERVED_12_11_MASK 0x00001800U -/*Oscillator Mode Write-Data Delay Line Select*/ +/* +* Oscillator Mode Write-Data Delay Line Select +*/ #undef DDR_PHY_DX8SL4OSC_OSCWDDL_DEFVAL #undef DDR_PHY_DX8SL4OSC_OSCWDDL_SHIFT #undef DDR_PHY_DX8SL4OSC_OSCWDDL_MASK -#define DDR_PHY_DX8SL4OSC_OSCWDDL_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL4OSC_OSCWDDL_SHIFT 9 -#define DDR_PHY_DX8SL4OSC_OSCWDDL_MASK 0x00000600U +#define DDR_PHY_DX8SL4OSC_OSCWDDL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_OSCWDDL_SHIFT 9 +#define DDR_PHY_DX8SL4OSC_OSCWDDL_MASK 0x00000600U -/*Reserved. Caution, do not write to this register field.*/ +/* +* Reserved. Caution, do not write to this register field. +*/ #undef DDR_PHY_DX8SL4OSC_RESERVED_8_7_DEFVAL #undef DDR_PHY_DX8SL4OSC_RESERVED_8_7_SHIFT #undef DDR_PHY_DX8SL4OSC_RESERVED_8_7_MASK -#define DDR_PHY_DX8SL4OSC_RESERVED_8_7_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL4OSC_RESERVED_8_7_SHIFT 7 -#define DDR_PHY_DX8SL4OSC_RESERVED_8_7_MASK 0x00000180U +#define DDR_PHY_DX8SL4OSC_RESERVED_8_7_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_RESERVED_8_7_SHIFT 7 +#define DDR_PHY_DX8SL4OSC_RESERVED_8_7_MASK 0x00000180U -/*Oscillator Mode Write-Leveling Delay Line Select*/ +/* +* Oscillator Mode Write-Leveling Delay Line Select +*/ #undef DDR_PHY_DX8SL4OSC_OSCWDL_DEFVAL #undef DDR_PHY_DX8SL4OSC_OSCWDL_SHIFT #undef DDR_PHY_DX8SL4OSC_OSCWDL_MASK -#define DDR_PHY_DX8SL4OSC_OSCWDL_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL4OSC_OSCWDL_SHIFT 5 -#define DDR_PHY_DX8SL4OSC_OSCWDL_MASK 0x00000060U +#define DDR_PHY_DX8SL4OSC_OSCWDL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_OSCWDL_SHIFT 5 +#define DDR_PHY_DX8SL4OSC_OSCWDL_MASK 0x00000060U -/*Oscillator Mode Division*/ +/* +* Oscillator Mode Division +*/ #undef DDR_PHY_DX8SL4OSC_OSCDIV_DEFVAL #undef DDR_PHY_DX8SL4OSC_OSCDIV_SHIFT #undef DDR_PHY_DX8SL4OSC_OSCDIV_MASK -#define DDR_PHY_DX8SL4OSC_OSCDIV_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL4OSC_OSCDIV_SHIFT 1 -#define DDR_PHY_DX8SL4OSC_OSCDIV_MASK 0x0000001EU +#define DDR_PHY_DX8SL4OSC_OSCDIV_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_OSCDIV_SHIFT 1 +#define DDR_PHY_DX8SL4OSC_OSCDIV_MASK 0x0000001EU -/*Oscillator Enable*/ +/* +* Oscillator Enable +*/ #undef DDR_PHY_DX8SL4OSC_OSCEN_DEFVAL #undef DDR_PHY_DX8SL4OSC_OSCEN_SHIFT #undef DDR_PHY_DX8SL4OSC_OSCEN_MASK -#define DDR_PHY_DX8SL4OSC_OSCEN_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL4OSC_OSCEN_SHIFT 0 -#define DDR_PHY_DX8SL4OSC_OSCEN_MASK 0x00000001U +#define DDR_PHY_DX8SL4OSC_OSCEN_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_OSCEN_SHIFT 0 +#define DDR_PHY_DX8SL4OSC_OSCEN_MASK 0x00000001U -/*Reserved. Return zeroes on reads.*/ +/* +* PLL Bypass +*/ +#undef DDR_PHY_DX8SL4PLLCR0_PLLBYP_DEFVAL +#undef DDR_PHY_DX8SL4PLLCR0_PLLBYP_SHIFT +#undef DDR_PHY_DX8SL4PLLCR0_PLLBYP_MASK +#define DDR_PHY_DX8SL4PLLCR0_PLLBYP_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL4PLLCR0_PLLBYP_SHIFT 31 +#define DDR_PHY_DX8SL4PLLCR0_PLLBYP_MASK 0x80000000U + +/* +* PLL Reset +*/ +#undef DDR_PHY_DX8SL4PLLCR0_PLLRST_DEFVAL +#undef DDR_PHY_DX8SL4PLLCR0_PLLRST_SHIFT +#undef DDR_PHY_DX8SL4PLLCR0_PLLRST_MASK +#define DDR_PHY_DX8SL4PLLCR0_PLLRST_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL4PLLCR0_PLLRST_SHIFT 30 +#define DDR_PHY_DX8SL4PLLCR0_PLLRST_MASK 0x40000000U + +/* +* PLL Power Down +*/ +#undef DDR_PHY_DX8SL4PLLCR0_PLLPD_DEFVAL +#undef DDR_PHY_DX8SL4PLLCR0_PLLPD_SHIFT +#undef DDR_PHY_DX8SL4PLLCR0_PLLPD_MASK +#define DDR_PHY_DX8SL4PLLCR0_PLLPD_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL4PLLCR0_PLLPD_SHIFT 29 +#define DDR_PHY_DX8SL4PLLCR0_PLLPD_MASK 0x20000000U + +/* +* Reference Stop Mode +*/ +#undef DDR_PHY_DX8SL4PLLCR0_RSTOPM_DEFVAL +#undef DDR_PHY_DX8SL4PLLCR0_RSTOPM_SHIFT +#undef DDR_PHY_DX8SL4PLLCR0_RSTOPM_MASK +#define DDR_PHY_DX8SL4PLLCR0_RSTOPM_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL4PLLCR0_RSTOPM_SHIFT 28 +#define DDR_PHY_DX8SL4PLLCR0_RSTOPM_MASK 0x10000000U + +/* +* PLL Frequency Select +*/ +#undef DDR_PHY_DX8SL4PLLCR0_FRQSEL_DEFVAL +#undef DDR_PHY_DX8SL4PLLCR0_FRQSEL_SHIFT +#undef DDR_PHY_DX8SL4PLLCR0_FRQSEL_MASK +#define DDR_PHY_DX8SL4PLLCR0_FRQSEL_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL4PLLCR0_FRQSEL_SHIFT 24 +#define DDR_PHY_DX8SL4PLLCR0_FRQSEL_MASK 0x0F000000U + +/* +* Relock Mode +*/ +#undef DDR_PHY_DX8SL4PLLCR0_RLOCKM_DEFVAL +#undef DDR_PHY_DX8SL4PLLCR0_RLOCKM_SHIFT +#undef DDR_PHY_DX8SL4PLLCR0_RLOCKM_MASK +#define DDR_PHY_DX8SL4PLLCR0_RLOCKM_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL4PLLCR0_RLOCKM_SHIFT 23 +#define DDR_PHY_DX8SL4PLLCR0_RLOCKM_MASK 0x00800000U + +/* +* Charge Pump Proportional Current Control +*/ +#undef DDR_PHY_DX8SL4PLLCR0_CPPC_DEFVAL +#undef DDR_PHY_DX8SL4PLLCR0_CPPC_SHIFT +#undef DDR_PHY_DX8SL4PLLCR0_CPPC_MASK +#define DDR_PHY_DX8SL4PLLCR0_CPPC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL4PLLCR0_CPPC_SHIFT 17 +#define DDR_PHY_DX8SL4PLLCR0_CPPC_MASK 0x007E0000U + +/* +* Charge Pump Integrating Current Control +*/ +#undef DDR_PHY_DX8SL4PLLCR0_CPIC_DEFVAL +#undef DDR_PHY_DX8SL4PLLCR0_CPIC_SHIFT +#undef DDR_PHY_DX8SL4PLLCR0_CPIC_MASK +#define DDR_PHY_DX8SL4PLLCR0_CPIC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL4PLLCR0_CPIC_SHIFT 13 +#define DDR_PHY_DX8SL4PLLCR0_CPIC_MASK 0x0001E000U + +/* +* Gear Shift +*/ +#undef DDR_PHY_DX8SL4PLLCR0_GSHIFT_DEFVAL +#undef DDR_PHY_DX8SL4PLLCR0_GSHIFT_SHIFT +#undef DDR_PHY_DX8SL4PLLCR0_GSHIFT_MASK +#define DDR_PHY_DX8SL4PLLCR0_GSHIFT_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL4PLLCR0_GSHIFT_SHIFT 12 +#define DDR_PHY_DX8SL4PLLCR0_GSHIFT_MASK 0x00001000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL4PLLCR0_RESERVED_11_9_DEFVAL +#undef DDR_PHY_DX8SL4PLLCR0_RESERVED_11_9_SHIFT +#undef DDR_PHY_DX8SL4PLLCR0_RESERVED_11_9_MASK +#define DDR_PHY_DX8SL4PLLCR0_RESERVED_11_9_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL4PLLCR0_RESERVED_11_9_SHIFT 9 +#define DDR_PHY_DX8SL4PLLCR0_RESERVED_11_9_MASK 0x00000E00U + +/* +* Analog Test Enable (ATOEN) +*/ +#undef DDR_PHY_DX8SL4PLLCR0_ATOEN_DEFVAL +#undef DDR_PHY_DX8SL4PLLCR0_ATOEN_SHIFT +#undef DDR_PHY_DX8SL4PLLCR0_ATOEN_MASK +#define DDR_PHY_DX8SL4PLLCR0_ATOEN_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL4PLLCR0_ATOEN_SHIFT 8 +#define DDR_PHY_DX8SL4PLLCR0_ATOEN_MASK 0x00000100U + +/* +* Analog Test Control +*/ +#undef DDR_PHY_DX8SL4PLLCR0_ATC_DEFVAL +#undef DDR_PHY_DX8SL4PLLCR0_ATC_SHIFT +#undef DDR_PHY_DX8SL4PLLCR0_ATC_MASK +#define DDR_PHY_DX8SL4PLLCR0_ATC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL4PLLCR0_ATC_SHIFT 4 +#define DDR_PHY_DX8SL4PLLCR0_ATC_MASK 0x000000F0U + +/* +* Digital Test Control +*/ +#undef DDR_PHY_DX8SL4PLLCR0_DTC_DEFVAL +#undef DDR_PHY_DX8SL4PLLCR0_DTC_SHIFT +#undef DDR_PHY_DX8SL4PLLCR0_DTC_MASK +#define DDR_PHY_DX8SL4PLLCR0_DTC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL4PLLCR0_DTC_SHIFT 0 +#define DDR_PHY_DX8SL4PLLCR0_DTC_MASK 0x0000000FU + +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_DEFVAL #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_SHIFT #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_MASK -#define DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_SHIFT 25 -#define DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_MASK 0xFE000000U +#define DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_SHIFT 25 +#define DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_MASK 0xFE000000U -/*Read Path Rise-to-Rise Mode*/ +/* +* Read Path Rise-to-Rise Mode +*/ #undef DDR_PHY_DX8SL4DQSCTL_RRRMODE_DEFVAL #undef DDR_PHY_DX8SL4DQSCTL_RRRMODE_SHIFT #undef DDR_PHY_DX8SL4DQSCTL_RRRMODE_MASK -#define DDR_PHY_DX8SL4DQSCTL_RRRMODE_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL4DQSCTL_RRRMODE_SHIFT 24 -#define DDR_PHY_DX8SL4DQSCTL_RRRMODE_MASK 0x01000000U +#define DDR_PHY_DX8SL4DQSCTL_RRRMODE_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL4DQSCTL_RRRMODE_SHIFT 24 +#define DDR_PHY_DX8SL4DQSCTL_RRRMODE_MASK 0x01000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_DEFVAL #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_SHIFT #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_MASK -#define DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_SHIFT 22 -#define DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_MASK 0x00C00000U +#define DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_MASK 0x00C00000U -/*Write Path Rise-to-Rise Mode*/ +/* +* Write Path Rise-to-Rise Mode +*/ #undef DDR_PHY_DX8SL4DQSCTL_WRRMODE_DEFVAL #undef DDR_PHY_DX8SL4DQSCTL_WRRMODE_SHIFT #undef DDR_PHY_DX8SL4DQSCTL_WRRMODE_MASK -#define DDR_PHY_DX8SL4DQSCTL_WRRMODE_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL4DQSCTL_WRRMODE_SHIFT 21 -#define DDR_PHY_DX8SL4DQSCTL_WRRMODE_MASK 0x00200000U +#define DDR_PHY_DX8SL4DQSCTL_WRRMODE_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL4DQSCTL_WRRMODE_SHIFT 21 +#define DDR_PHY_DX8SL4DQSCTL_WRRMODE_MASK 0x00200000U -/*DQS Gate Extension*/ +/* +* DQS Gate Extension +*/ #undef DDR_PHY_DX8SL4DQSCTL_DQSGX_DEFVAL #undef DDR_PHY_DX8SL4DQSCTL_DQSGX_SHIFT #undef DDR_PHY_DX8SL4DQSCTL_DQSGX_MASK -#define DDR_PHY_DX8SL4DQSCTL_DQSGX_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL4DQSCTL_DQSGX_SHIFT 19 -#define DDR_PHY_DX8SL4DQSCTL_DQSGX_MASK 0x00180000U +#define DDR_PHY_DX8SL4DQSCTL_DQSGX_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL4DQSCTL_DQSGX_SHIFT 19 +#define DDR_PHY_DX8SL4DQSCTL_DQSGX_MASK 0x00180000U -/*Low Power PLL Power Down*/ +/* +* Low Power PLL Power Down +*/ #undef DDR_PHY_DX8SL4DQSCTL_LPPLLPD_DEFVAL #undef DDR_PHY_DX8SL4DQSCTL_LPPLLPD_SHIFT #undef DDR_PHY_DX8SL4DQSCTL_LPPLLPD_MASK -#define DDR_PHY_DX8SL4DQSCTL_LPPLLPD_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL4DQSCTL_LPPLLPD_SHIFT 18 -#define DDR_PHY_DX8SL4DQSCTL_LPPLLPD_MASK 0x00040000U +#define DDR_PHY_DX8SL4DQSCTL_LPPLLPD_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL4DQSCTL_LPPLLPD_SHIFT 18 +#define DDR_PHY_DX8SL4DQSCTL_LPPLLPD_MASK 0x00040000U -/*Low Power I/O Power Down*/ +/* +* Low Power I/O Power Down +*/ #undef DDR_PHY_DX8SL4DQSCTL_LPIOPD_DEFVAL #undef DDR_PHY_DX8SL4DQSCTL_LPIOPD_SHIFT #undef DDR_PHY_DX8SL4DQSCTL_LPIOPD_MASK -#define DDR_PHY_DX8SL4DQSCTL_LPIOPD_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL4DQSCTL_LPIOPD_SHIFT 17 -#define DDR_PHY_DX8SL4DQSCTL_LPIOPD_MASK 0x00020000U +#define DDR_PHY_DX8SL4DQSCTL_LPIOPD_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL4DQSCTL_LPIOPD_SHIFT 17 +#define DDR_PHY_DX8SL4DQSCTL_LPIOPD_MASK 0x00020000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_DEFVAL #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_SHIFT #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_MASK -#define DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_SHIFT 15 -#define DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_MASK 0x00018000U +#define DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_SHIFT 15 +#define DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_MASK 0x00018000U -/*QS Counter Enable*/ +/* +* QS Counter Enable +*/ #undef DDR_PHY_DX8SL4DQSCTL_QSCNTEN_DEFVAL #undef DDR_PHY_DX8SL4DQSCTL_QSCNTEN_SHIFT #undef DDR_PHY_DX8SL4DQSCTL_QSCNTEN_MASK -#define DDR_PHY_DX8SL4DQSCTL_QSCNTEN_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL4DQSCTL_QSCNTEN_SHIFT 14 -#define DDR_PHY_DX8SL4DQSCTL_QSCNTEN_MASK 0x00004000U +#define DDR_PHY_DX8SL4DQSCTL_QSCNTEN_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL4DQSCTL_QSCNTEN_SHIFT 14 +#define DDR_PHY_DX8SL4DQSCTL_QSCNTEN_MASK 0x00004000U -/*Unused DQ I/O Mode*/ +/* +* Unused DQ I/O Mode +*/ #undef DDR_PHY_DX8SL4DQSCTL_UDQIOM_DEFVAL #undef DDR_PHY_DX8SL4DQSCTL_UDQIOM_SHIFT #undef DDR_PHY_DX8SL4DQSCTL_UDQIOM_MASK -#define DDR_PHY_DX8SL4DQSCTL_UDQIOM_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL4DQSCTL_UDQIOM_SHIFT 13 -#define DDR_PHY_DX8SL4DQSCTL_UDQIOM_MASK 0x00002000U +#define DDR_PHY_DX8SL4DQSCTL_UDQIOM_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL4DQSCTL_UDQIOM_SHIFT 13 +#define DDR_PHY_DX8SL4DQSCTL_UDQIOM_MASK 0x00002000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_DEFVAL #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_SHIFT #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_MASK -#define DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_SHIFT 10 -#define DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_MASK 0x00001C00U +#define DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_SHIFT 10 +#define DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_MASK 0x00001C00U -/*Data Slew Rate*/ +/* +* Data Slew Rate +*/ #undef DDR_PHY_DX8SL4DQSCTL_DXSR_DEFVAL #undef DDR_PHY_DX8SL4DQSCTL_DXSR_SHIFT #undef DDR_PHY_DX8SL4DQSCTL_DXSR_MASK -#define DDR_PHY_DX8SL4DQSCTL_DXSR_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL4DQSCTL_DXSR_SHIFT 8 -#define DDR_PHY_DX8SL4DQSCTL_DXSR_MASK 0x00000300U +#define DDR_PHY_DX8SL4DQSCTL_DXSR_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL4DQSCTL_DXSR_SHIFT 8 +#define DDR_PHY_DX8SL4DQSCTL_DXSR_MASK 0x00000300U -/*DQS_N Resistor*/ +/* +* DQS_N Resistor +*/ #undef DDR_PHY_DX8SL4DQSCTL_DQSNRES_DEFVAL #undef DDR_PHY_DX8SL4DQSCTL_DQSNRES_SHIFT #undef DDR_PHY_DX8SL4DQSCTL_DQSNRES_MASK -#define DDR_PHY_DX8SL4DQSCTL_DQSNRES_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL4DQSCTL_DQSNRES_SHIFT 4 -#define DDR_PHY_DX8SL4DQSCTL_DQSNRES_MASK 0x000000F0U +#define DDR_PHY_DX8SL4DQSCTL_DQSNRES_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL4DQSCTL_DQSNRES_SHIFT 4 +#define DDR_PHY_DX8SL4DQSCTL_DQSNRES_MASK 0x000000F0U -/*DQS Resistor*/ +/* +* DQS Resistor +*/ #undef DDR_PHY_DX8SL4DQSCTL_DQSRES_DEFVAL #undef DDR_PHY_DX8SL4DQSCTL_DQSRES_SHIFT #undef DDR_PHY_DX8SL4DQSCTL_DQSRES_MASK -#define DDR_PHY_DX8SL4DQSCTL_DQSRES_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL4DQSCTL_DQSRES_SHIFT 0 -#define DDR_PHY_DX8SL4DQSCTL_DQSRES_MASK 0x0000000FU +#define DDR_PHY_DX8SL4DQSCTL_DQSRES_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL4DQSCTL_DQSRES_SHIFT 0 +#define DDR_PHY_DX8SL4DQSCTL_DQSRES_MASK 0x0000000FU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_DEFVAL #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_SHIFT #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_MASK -#define DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_SHIFT 24 -#define DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_MASK 0xFF000000U +#define DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_SHIFT 24 +#define DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_MASK 0xFF000000U -/*Configurable Read Data Enable*/ +/* +* Configurable Read Data Enable +*/ #undef DDR_PHY_DX8SL4DXCTL2_CRDEN_DEFVAL #undef DDR_PHY_DX8SL4DXCTL2_CRDEN_SHIFT #undef DDR_PHY_DX8SL4DXCTL2_CRDEN_MASK -#define DDR_PHY_DX8SL4DXCTL2_CRDEN_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL4DXCTL2_CRDEN_SHIFT 23 -#define DDR_PHY_DX8SL4DXCTL2_CRDEN_MASK 0x00800000U +#define DDR_PHY_DX8SL4DXCTL2_CRDEN_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_CRDEN_SHIFT 23 +#define DDR_PHY_DX8SL4DXCTL2_CRDEN_MASK 0x00800000U -/*OX Extension during Post-amble*/ +/* +* OX Extension during Post-amble +*/ #undef DDR_PHY_DX8SL4DXCTL2_POSOEX_DEFVAL #undef DDR_PHY_DX8SL4DXCTL2_POSOEX_SHIFT #undef DDR_PHY_DX8SL4DXCTL2_POSOEX_MASK -#define DDR_PHY_DX8SL4DXCTL2_POSOEX_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL4DXCTL2_POSOEX_SHIFT 20 -#define DDR_PHY_DX8SL4DXCTL2_POSOEX_MASK 0x00700000U +#define DDR_PHY_DX8SL4DXCTL2_POSOEX_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_POSOEX_SHIFT 20 +#define DDR_PHY_DX8SL4DXCTL2_POSOEX_MASK 0x00700000U -/*OE Extension during Pre-amble*/ +/* +* OE Extension during Pre-amble +*/ #undef DDR_PHY_DX8SL4DXCTL2_PREOEX_DEFVAL #undef DDR_PHY_DX8SL4DXCTL2_PREOEX_SHIFT #undef DDR_PHY_DX8SL4DXCTL2_PREOEX_MASK -#define DDR_PHY_DX8SL4DXCTL2_PREOEX_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL4DXCTL2_PREOEX_SHIFT 18 -#define DDR_PHY_DX8SL4DXCTL2_PREOEX_MASK 0x000C0000U +#define DDR_PHY_DX8SL4DXCTL2_PREOEX_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_PREOEX_SHIFT 18 +#define DDR_PHY_DX8SL4DXCTL2_PREOEX_MASK 0x000C0000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_17_DEFVAL #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_17_SHIFT #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_17_MASK -#define DDR_PHY_DX8SL4DXCTL2_RESERVED_17_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL4DXCTL2_RESERVED_17_SHIFT 17 -#define DDR_PHY_DX8SL4DXCTL2_RESERVED_17_MASK 0x00020000U +#define DDR_PHY_DX8SL4DXCTL2_RESERVED_17_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_RESERVED_17_SHIFT 17 +#define DDR_PHY_DX8SL4DXCTL2_RESERVED_17_MASK 0x00020000U -/*I/O Assisted Gate Select*/ +/* +* I/O Assisted Gate Select +*/ #undef DDR_PHY_DX8SL4DXCTL2_IOAG_DEFVAL #undef DDR_PHY_DX8SL4DXCTL2_IOAG_SHIFT #undef DDR_PHY_DX8SL4DXCTL2_IOAG_MASK -#define DDR_PHY_DX8SL4DXCTL2_IOAG_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL4DXCTL2_IOAG_SHIFT 16 -#define DDR_PHY_DX8SL4DXCTL2_IOAG_MASK 0x00010000U +#define DDR_PHY_DX8SL4DXCTL2_IOAG_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_IOAG_SHIFT 16 +#define DDR_PHY_DX8SL4DXCTL2_IOAG_MASK 0x00010000U -/*I/O Loopback Select*/ +/* +* I/O Loopback Select +*/ #undef DDR_PHY_DX8SL4DXCTL2_IOLB_DEFVAL #undef DDR_PHY_DX8SL4DXCTL2_IOLB_SHIFT #undef DDR_PHY_DX8SL4DXCTL2_IOLB_MASK -#define DDR_PHY_DX8SL4DXCTL2_IOLB_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL4DXCTL2_IOLB_SHIFT 15 -#define DDR_PHY_DX8SL4DXCTL2_IOLB_MASK 0x00008000U +#define DDR_PHY_DX8SL4DXCTL2_IOLB_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_IOLB_SHIFT 15 +#define DDR_PHY_DX8SL4DXCTL2_IOLB_MASK 0x00008000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_DEFVAL #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_SHIFT #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_MASK -#define DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_SHIFT 13 -#define DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_MASK 0x00006000U +#define DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_SHIFT 13 +#define DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_MASK 0x00006000U -/*Low Power Wakeup Threshold*/ +/* +* Low Power Wakeup Threshold +*/ #undef DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_DEFVAL #undef DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_SHIFT #undef DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_MASK -#define DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_SHIFT 9 -#define DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_MASK 0x00001E00U +#define DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_SHIFT 9 +#define DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_MASK 0x00001E00U -/*Read Data Bus Inversion Enable*/ +/* +* Read Data Bus Inversion Enable +*/ #undef DDR_PHY_DX8SL4DXCTL2_RDBI_DEFVAL #undef DDR_PHY_DX8SL4DXCTL2_RDBI_SHIFT #undef DDR_PHY_DX8SL4DXCTL2_RDBI_MASK -#define DDR_PHY_DX8SL4DXCTL2_RDBI_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL4DXCTL2_RDBI_SHIFT 8 -#define DDR_PHY_DX8SL4DXCTL2_RDBI_MASK 0x00000100U +#define DDR_PHY_DX8SL4DXCTL2_RDBI_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_RDBI_SHIFT 8 +#define DDR_PHY_DX8SL4DXCTL2_RDBI_MASK 0x00000100U -/*Write Data Bus Inversion Enable*/ +/* +* Write Data Bus Inversion Enable +*/ #undef DDR_PHY_DX8SL4DXCTL2_WDBI_DEFVAL #undef DDR_PHY_DX8SL4DXCTL2_WDBI_SHIFT #undef DDR_PHY_DX8SL4DXCTL2_WDBI_MASK -#define DDR_PHY_DX8SL4DXCTL2_WDBI_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL4DXCTL2_WDBI_SHIFT 7 -#define DDR_PHY_DX8SL4DXCTL2_WDBI_MASK 0x00000080U +#define DDR_PHY_DX8SL4DXCTL2_WDBI_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_WDBI_SHIFT 7 +#define DDR_PHY_DX8SL4DXCTL2_WDBI_MASK 0x00000080U -/*PUB Read FIFO Bypass*/ +/* +* PUB Read FIFO Bypass +*/ #undef DDR_PHY_DX8SL4DXCTL2_PRFBYP_DEFVAL #undef DDR_PHY_DX8SL4DXCTL2_PRFBYP_SHIFT #undef DDR_PHY_DX8SL4DXCTL2_PRFBYP_MASK -#define DDR_PHY_DX8SL4DXCTL2_PRFBYP_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL4DXCTL2_PRFBYP_SHIFT 6 -#define DDR_PHY_DX8SL4DXCTL2_PRFBYP_MASK 0x00000040U +#define DDR_PHY_DX8SL4DXCTL2_PRFBYP_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_PRFBYP_SHIFT 6 +#define DDR_PHY_DX8SL4DXCTL2_PRFBYP_MASK 0x00000040U -/*DATX8 Receive FIFO Read Mode*/ +/* +* DATX8 Receive FIFO Read Mode +*/ #undef DDR_PHY_DX8SL4DXCTL2_RDMODE_DEFVAL #undef DDR_PHY_DX8SL4DXCTL2_RDMODE_SHIFT #undef DDR_PHY_DX8SL4DXCTL2_RDMODE_MASK -#define DDR_PHY_DX8SL4DXCTL2_RDMODE_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL4DXCTL2_RDMODE_SHIFT 4 -#define DDR_PHY_DX8SL4DXCTL2_RDMODE_MASK 0x00000030U +#define DDR_PHY_DX8SL4DXCTL2_RDMODE_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_RDMODE_SHIFT 4 +#define DDR_PHY_DX8SL4DXCTL2_RDMODE_MASK 0x00000030U -/*Disables the Read FIFO Reset*/ +/* +* Disables the Read FIFO Reset +*/ #undef DDR_PHY_DX8SL4DXCTL2_DISRST_DEFVAL #undef DDR_PHY_DX8SL4DXCTL2_DISRST_SHIFT #undef DDR_PHY_DX8SL4DXCTL2_DISRST_MASK -#define DDR_PHY_DX8SL4DXCTL2_DISRST_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL4DXCTL2_DISRST_SHIFT 3 -#define DDR_PHY_DX8SL4DXCTL2_DISRST_MASK 0x00000008U +#define DDR_PHY_DX8SL4DXCTL2_DISRST_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_DISRST_SHIFT 3 +#define DDR_PHY_DX8SL4DXCTL2_DISRST_MASK 0x00000008U -/*Read DQS Gate I/O Loopback*/ +/* +* Read DQS Gate I/O Loopback +*/ #undef DDR_PHY_DX8SL4DXCTL2_DQSGLB_DEFVAL #undef DDR_PHY_DX8SL4DXCTL2_DQSGLB_SHIFT #undef DDR_PHY_DX8SL4DXCTL2_DQSGLB_MASK -#define DDR_PHY_DX8SL4DXCTL2_DQSGLB_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL4DXCTL2_DQSGLB_SHIFT 1 -#define DDR_PHY_DX8SL4DXCTL2_DQSGLB_MASK 0x00000006U +#define DDR_PHY_DX8SL4DXCTL2_DQSGLB_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_DQSGLB_SHIFT 1 +#define DDR_PHY_DX8SL4DXCTL2_DQSGLB_MASK 0x00000006U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_0_DEFVAL #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_0_SHIFT #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_0_MASK -#define DDR_PHY_DX8SL4DXCTL2_RESERVED_0_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL4DXCTL2_RESERVED_0_SHIFT 0 -#define DDR_PHY_DX8SL4DXCTL2_RESERVED_0_MASK 0x00000001U +#define DDR_PHY_DX8SL4DXCTL2_RESERVED_0_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_RESERVED_0_SHIFT 0 +#define DDR_PHY_DX8SL4DXCTL2_RESERVED_0_MASK 0x00000001U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL4IOCR_RESERVED_31_DEFVAL #undef DDR_PHY_DX8SL4IOCR_RESERVED_31_SHIFT #undef DDR_PHY_DX8SL4IOCR_RESERVED_31_MASK -#define DDR_PHY_DX8SL4IOCR_RESERVED_31_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL4IOCR_RESERVED_31_SHIFT 31 -#define DDR_PHY_DX8SL4IOCR_RESERVED_31_MASK 0x80000000U +#define DDR_PHY_DX8SL4IOCR_RESERVED_31_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL4IOCR_RESERVED_31_SHIFT 31 +#define DDR_PHY_DX8SL4IOCR_RESERVED_31_MASK 0x80000000U -/*PVREF_DAC REFSEL range select*/ +/* +* PVREF_DAC REFSEL range select +*/ #undef DDR_PHY_DX8SL4IOCR_DXDACRANGE_DEFVAL #undef DDR_PHY_DX8SL4IOCR_DXDACRANGE_SHIFT #undef DDR_PHY_DX8SL4IOCR_DXDACRANGE_MASK -#define DDR_PHY_DX8SL4IOCR_DXDACRANGE_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL4IOCR_DXDACRANGE_SHIFT 28 -#define DDR_PHY_DX8SL4IOCR_DXDACRANGE_MASK 0x70000000U +#define DDR_PHY_DX8SL4IOCR_DXDACRANGE_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL4IOCR_DXDACRANGE_SHIFT 28 +#define DDR_PHY_DX8SL4IOCR_DXDACRANGE_MASK 0x70000000U -/*IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring*/ +/* +* IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring +*/ #undef DDR_PHY_DX8SL4IOCR_DXVREFIOM_DEFVAL #undef DDR_PHY_DX8SL4IOCR_DXVREFIOM_SHIFT #undef DDR_PHY_DX8SL4IOCR_DXVREFIOM_MASK -#define DDR_PHY_DX8SL4IOCR_DXVREFIOM_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL4IOCR_DXVREFIOM_SHIFT 25 -#define DDR_PHY_DX8SL4IOCR_DXVREFIOM_MASK 0x0E000000U +#define DDR_PHY_DX8SL4IOCR_DXVREFIOM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL4IOCR_DXVREFIOM_SHIFT 25 +#define DDR_PHY_DX8SL4IOCR_DXVREFIOM_MASK 0x0E000000U -/*DX IO Mode*/ +/* +* DX IO Mode +*/ #undef DDR_PHY_DX8SL4IOCR_DXIOM_DEFVAL #undef DDR_PHY_DX8SL4IOCR_DXIOM_SHIFT #undef DDR_PHY_DX8SL4IOCR_DXIOM_MASK -#define DDR_PHY_DX8SL4IOCR_DXIOM_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL4IOCR_DXIOM_SHIFT 22 -#define DDR_PHY_DX8SL4IOCR_DXIOM_MASK 0x01C00000U +#define DDR_PHY_DX8SL4IOCR_DXIOM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL4IOCR_DXIOM_SHIFT 22 +#define DDR_PHY_DX8SL4IOCR_DXIOM_MASK 0x01C00000U -/*DX IO Transmitter Mode*/ +/* +* DX IO Transmitter Mode +*/ #undef DDR_PHY_DX8SL4IOCR_DXTXM_DEFVAL #undef DDR_PHY_DX8SL4IOCR_DXTXM_SHIFT #undef DDR_PHY_DX8SL4IOCR_DXTXM_MASK -#define DDR_PHY_DX8SL4IOCR_DXTXM_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL4IOCR_DXTXM_SHIFT 11 -#define DDR_PHY_DX8SL4IOCR_DXTXM_MASK 0x003FF800U +#define DDR_PHY_DX8SL4IOCR_DXTXM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL4IOCR_DXTXM_SHIFT 11 +#define DDR_PHY_DX8SL4IOCR_DXTXM_MASK 0x003FF800U -/*DX IO Receiver Mode*/ +/* +* DX IO Receiver Mode +*/ #undef DDR_PHY_DX8SL4IOCR_DXRXM_DEFVAL #undef DDR_PHY_DX8SL4IOCR_DXRXM_SHIFT #undef DDR_PHY_DX8SL4IOCR_DXRXM_MASK -#define DDR_PHY_DX8SL4IOCR_DXRXM_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL4IOCR_DXRXM_SHIFT 0 -#define DDR_PHY_DX8SL4IOCR_DXRXM_MASK 0x000007FFU +#define DDR_PHY_DX8SL4IOCR_DXRXM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL4IOCR_DXRXM_SHIFT 0 +#define DDR_PHY_DX8SL4IOCR_DXRXM_MASK 0x000007FFU -/*Reserved. Return zeroes on reads.*/ +/* +* PLL Bypass +*/ +#undef DDR_PHY_DX8SLBPLLCR0_PLLBYP_DEFVAL +#undef DDR_PHY_DX8SLBPLLCR0_PLLBYP_SHIFT +#undef DDR_PHY_DX8SLBPLLCR0_PLLBYP_MASK +#define DDR_PHY_DX8SLBPLLCR0_PLLBYP_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBPLLCR0_PLLBYP_SHIFT 31 +#define DDR_PHY_DX8SLBPLLCR0_PLLBYP_MASK 0x80000000U + +/* +* PLL Reset +*/ +#undef DDR_PHY_DX8SLBPLLCR0_PLLRST_DEFVAL +#undef DDR_PHY_DX8SLBPLLCR0_PLLRST_SHIFT +#undef DDR_PHY_DX8SLBPLLCR0_PLLRST_MASK +#define DDR_PHY_DX8SLBPLLCR0_PLLRST_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBPLLCR0_PLLRST_SHIFT 30 +#define DDR_PHY_DX8SLBPLLCR0_PLLRST_MASK 0x40000000U + +/* +* PLL Power Down +*/ +#undef DDR_PHY_DX8SLBPLLCR0_PLLPD_DEFVAL +#undef DDR_PHY_DX8SLBPLLCR0_PLLPD_SHIFT +#undef DDR_PHY_DX8SLBPLLCR0_PLLPD_MASK +#define DDR_PHY_DX8SLBPLLCR0_PLLPD_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBPLLCR0_PLLPD_SHIFT 29 +#define DDR_PHY_DX8SLBPLLCR0_PLLPD_MASK 0x20000000U + +/* +* Reference Stop Mode +*/ +#undef DDR_PHY_DX8SLBPLLCR0_RSTOPM_DEFVAL +#undef DDR_PHY_DX8SLBPLLCR0_RSTOPM_SHIFT +#undef DDR_PHY_DX8SLBPLLCR0_RSTOPM_MASK +#define DDR_PHY_DX8SLBPLLCR0_RSTOPM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBPLLCR0_RSTOPM_SHIFT 28 +#define DDR_PHY_DX8SLBPLLCR0_RSTOPM_MASK 0x10000000U + +/* +* PLL Frequency Select +*/ +#undef DDR_PHY_DX8SLBPLLCR0_FRQSEL_DEFVAL +#undef DDR_PHY_DX8SLBPLLCR0_FRQSEL_SHIFT +#undef DDR_PHY_DX8SLBPLLCR0_FRQSEL_MASK +#define DDR_PHY_DX8SLBPLLCR0_FRQSEL_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBPLLCR0_FRQSEL_SHIFT 24 +#define DDR_PHY_DX8SLBPLLCR0_FRQSEL_MASK 0x0F000000U + +/* +* Relock Mode +*/ +#undef DDR_PHY_DX8SLBPLLCR0_RLOCKM_DEFVAL +#undef DDR_PHY_DX8SLBPLLCR0_RLOCKM_SHIFT +#undef DDR_PHY_DX8SLBPLLCR0_RLOCKM_MASK +#define DDR_PHY_DX8SLBPLLCR0_RLOCKM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBPLLCR0_RLOCKM_SHIFT 23 +#define DDR_PHY_DX8SLBPLLCR0_RLOCKM_MASK 0x00800000U + +/* +* Charge Pump Proportional Current Control +*/ +#undef DDR_PHY_DX8SLBPLLCR0_CPPC_DEFVAL +#undef DDR_PHY_DX8SLBPLLCR0_CPPC_SHIFT +#undef DDR_PHY_DX8SLBPLLCR0_CPPC_MASK +#define DDR_PHY_DX8SLBPLLCR0_CPPC_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBPLLCR0_CPPC_SHIFT 17 +#define DDR_PHY_DX8SLBPLLCR0_CPPC_MASK 0x007E0000U + +/* +* Charge Pump Integrating Current Control +*/ +#undef DDR_PHY_DX8SLBPLLCR0_CPIC_DEFVAL +#undef DDR_PHY_DX8SLBPLLCR0_CPIC_SHIFT +#undef DDR_PHY_DX8SLBPLLCR0_CPIC_MASK +#define DDR_PHY_DX8SLBPLLCR0_CPIC_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBPLLCR0_CPIC_SHIFT 13 +#define DDR_PHY_DX8SLBPLLCR0_CPIC_MASK 0x0001E000U + +/* +* Gear Shift +*/ +#undef DDR_PHY_DX8SLBPLLCR0_GSHIFT_DEFVAL +#undef DDR_PHY_DX8SLBPLLCR0_GSHIFT_SHIFT +#undef DDR_PHY_DX8SLBPLLCR0_GSHIFT_MASK +#define DDR_PHY_DX8SLBPLLCR0_GSHIFT_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBPLLCR0_GSHIFT_SHIFT 12 +#define DDR_PHY_DX8SLBPLLCR0_GSHIFT_MASK 0x00001000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SLBPLLCR0_RESERVED_11_9_DEFVAL +#undef DDR_PHY_DX8SLBPLLCR0_RESERVED_11_9_SHIFT +#undef DDR_PHY_DX8SLBPLLCR0_RESERVED_11_9_MASK +#define DDR_PHY_DX8SLBPLLCR0_RESERVED_11_9_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBPLLCR0_RESERVED_11_9_SHIFT 9 +#define DDR_PHY_DX8SLBPLLCR0_RESERVED_11_9_MASK 0x00000E00U + +/* +* Analog Test Enable (ATOEN) +*/ +#undef DDR_PHY_DX8SLBPLLCR0_ATOEN_DEFVAL +#undef DDR_PHY_DX8SLBPLLCR0_ATOEN_SHIFT +#undef DDR_PHY_DX8SLBPLLCR0_ATOEN_MASK +#define DDR_PHY_DX8SLBPLLCR0_ATOEN_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBPLLCR0_ATOEN_SHIFT 8 +#define DDR_PHY_DX8SLBPLLCR0_ATOEN_MASK 0x00000100U + +/* +* Analog Test Control +*/ +#undef DDR_PHY_DX8SLBPLLCR0_ATC_DEFVAL +#undef DDR_PHY_DX8SLBPLLCR0_ATC_SHIFT +#undef DDR_PHY_DX8SLBPLLCR0_ATC_MASK +#define DDR_PHY_DX8SLBPLLCR0_ATC_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBPLLCR0_ATC_SHIFT 4 +#define DDR_PHY_DX8SLBPLLCR0_ATC_MASK 0x000000F0U + +/* +* Digital Test Control +*/ +#undef DDR_PHY_DX8SLBPLLCR0_DTC_DEFVAL +#undef DDR_PHY_DX8SLBPLLCR0_DTC_SHIFT +#undef DDR_PHY_DX8SLBPLLCR0_DTC_MASK +#define DDR_PHY_DX8SLBPLLCR0_DTC_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBPLLCR0_DTC_SHIFT 0 +#define DDR_PHY_DX8SLBPLLCR0_DTC_MASK 0x0000000FU + +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_DEFVAL #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_SHIFT #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_MASK -#define DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_DEFVAL 0x00000000 -#define DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_SHIFT 25 -#define DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_MASK 0xFE000000U +#define DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_SHIFT 25 +#define DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_MASK 0xFE000000U -/*Read Path Rise-to-Rise Mode*/ +/* +* Read Path Rise-to-Rise Mode +*/ #undef DDR_PHY_DX8SLBDQSCTL_RRRMODE_DEFVAL #undef DDR_PHY_DX8SLBDQSCTL_RRRMODE_SHIFT #undef DDR_PHY_DX8SLBDQSCTL_RRRMODE_MASK -#define DDR_PHY_DX8SLBDQSCTL_RRRMODE_DEFVAL 0x00000000 -#define DDR_PHY_DX8SLBDQSCTL_RRRMODE_SHIFT 24 -#define DDR_PHY_DX8SLBDQSCTL_RRRMODE_MASK 0x01000000U +#define DDR_PHY_DX8SLBDQSCTL_RRRMODE_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBDQSCTL_RRRMODE_SHIFT 24 +#define DDR_PHY_DX8SLBDQSCTL_RRRMODE_MASK 0x01000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_DEFVAL #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_SHIFT #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_MASK -#define DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_DEFVAL 0x00000000 -#define DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_SHIFT 22 -#define DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_MASK 0x00C00000U +#define DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_MASK 0x00C00000U -/*Write Path Rise-to-Rise Mode*/ +/* +* Write Path Rise-to-Rise Mode +*/ #undef DDR_PHY_DX8SLBDQSCTL_WRRMODE_DEFVAL #undef DDR_PHY_DX8SLBDQSCTL_WRRMODE_SHIFT #undef DDR_PHY_DX8SLBDQSCTL_WRRMODE_MASK -#define DDR_PHY_DX8SLBDQSCTL_WRRMODE_DEFVAL 0x00000000 -#define DDR_PHY_DX8SLBDQSCTL_WRRMODE_SHIFT 21 -#define DDR_PHY_DX8SLBDQSCTL_WRRMODE_MASK 0x00200000U +#define DDR_PHY_DX8SLBDQSCTL_WRRMODE_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBDQSCTL_WRRMODE_SHIFT 21 +#define DDR_PHY_DX8SLBDQSCTL_WRRMODE_MASK 0x00200000U -/*DQS Gate Extension*/ +/* +* DQS Gate Extension +*/ #undef DDR_PHY_DX8SLBDQSCTL_DQSGX_DEFVAL #undef DDR_PHY_DX8SLBDQSCTL_DQSGX_SHIFT #undef DDR_PHY_DX8SLBDQSCTL_DQSGX_MASK -#define DDR_PHY_DX8SLBDQSCTL_DQSGX_DEFVAL 0x00000000 -#define DDR_PHY_DX8SLBDQSCTL_DQSGX_SHIFT 19 -#define DDR_PHY_DX8SLBDQSCTL_DQSGX_MASK 0x00180000U +#define DDR_PHY_DX8SLBDQSCTL_DQSGX_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBDQSCTL_DQSGX_SHIFT 19 +#define DDR_PHY_DX8SLBDQSCTL_DQSGX_MASK 0x00180000U -/*Low Power PLL Power Down*/ +/* +* Low Power PLL Power Down +*/ #undef DDR_PHY_DX8SLBDQSCTL_LPPLLPD_DEFVAL #undef DDR_PHY_DX8SLBDQSCTL_LPPLLPD_SHIFT #undef DDR_PHY_DX8SLBDQSCTL_LPPLLPD_MASK -#define DDR_PHY_DX8SLBDQSCTL_LPPLLPD_DEFVAL 0x00000000 -#define DDR_PHY_DX8SLBDQSCTL_LPPLLPD_SHIFT 18 -#define DDR_PHY_DX8SLBDQSCTL_LPPLLPD_MASK 0x00040000U +#define DDR_PHY_DX8SLBDQSCTL_LPPLLPD_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBDQSCTL_LPPLLPD_SHIFT 18 +#define DDR_PHY_DX8SLBDQSCTL_LPPLLPD_MASK 0x00040000U -/*Low Power I/O Power Down*/ +/* +* Low Power I/O Power Down +*/ #undef DDR_PHY_DX8SLBDQSCTL_LPIOPD_DEFVAL #undef DDR_PHY_DX8SLBDQSCTL_LPIOPD_SHIFT #undef DDR_PHY_DX8SLBDQSCTL_LPIOPD_MASK -#define DDR_PHY_DX8SLBDQSCTL_LPIOPD_DEFVAL 0x00000000 -#define DDR_PHY_DX8SLBDQSCTL_LPIOPD_SHIFT 17 -#define DDR_PHY_DX8SLBDQSCTL_LPIOPD_MASK 0x00020000U +#define DDR_PHY_DX8SLBDQSCTL_LPIOPD_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBDQSCTL_LPIOPD_SHIFT 17 +#define DDR_PHY_DX8SLBDQSCTL_LPIOPD_MASK 0x00020000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_DEFVAL #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_SHIFT #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_MASK -#define DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_DEFVAL 0x00000000 -#define DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_SHIFT 15 -#define DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_MASK 0x00018000U +#define DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_SHIFT 15 +#define DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_MASK 0x00018000U -/*QS Counter Enable*/ +/* +* QS Counter Enable +*/ #undef DDR_PHY_DX8SLBDQSCTL_QSCNTEN_DEFVAL #undef DDR_PHY_DX8SLBDQSCTL_QSCNTEN_SHIFT #undef DDR_PHY_DX8SLBDQSCTL_QSCNTEN_MASK -#define DDR_PHY_DX8SLBDQSCTL_QSCNTEN_DEFVAL 0x00000000 -#define DDR_PHY_DX8SLBDQSCTL_QSCNTEN_SHIFT 14 -#define DDR_PHY_DX8SLBDQSCTL_QSCNTEN_MASK 0x00004000U +#define DDR_PHY_DX8SLBDQSCTL_QSCNTEN_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBDQSCTL_QSCNTEN_SHIFT 14 +#define DDR_PHY_DX8SLBDQSCTL_QSCNTEN_MASK 0x00004000U -/*Unused DQ I/O Mode*/ +/* +* Unused DQ I/O Mode +*/ #undef DDR_PHY_DX8SLBDQSCTL_UDQIOM_DEFVAL #undef DDR_PHY_DX8SLBDQSCTL_UDQIOM_SHIFT #undef DDR_PHY_DX8SLBDQSCTL_UDQIOM_MASK -#define DDR_PHY_DX8SLBDQSCTL_UDQIOM_DEFVAL 0x00000000 -#define DDR_PHY_DX8SLBDQSCTL_UDQIOM_SHIFT 13 -#define DDR_PHY_DX8SLBDQSCTL_UDQIOM_MASK 0x00002000U +#define DDR_PHY_DX8SLBDQSCTL_UDQIOM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBDQSCTL_UDQIOM_SHIFT 13 +#define DDR_PHY_DX8SLBDQSCTL_UDQIOM_MASK 0x00002000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_DEFVAL #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_SHIFT #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_MASK -#define DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_DEFVAL 0x00000000 -#define DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_SHIFT 10 -#define DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_MASK 0x00001C00U +#define DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_SHIFT 10 +#define DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_MASK 0x00001C00U -/*Data Slew Rate*/ +/* +* Data Slew Rate +*/ #undef DDR_PHY_DX8SLBDQSCTL_DXSR_DEFVAL #undef DDR_PHY_DX8SLBDQSCTL_DXSR_SHIFT #undef DDR_PHY_DX8SLBDQSCTL_DXSR_MASK -#define DDR_PHY_DX8SLBDQSCTL_DXSR_DEFVAL 0x00000000 -#define DDR_PHY_DX8SLBDQSCTL_DXSR_SHIFT 8 -#define DDR_PHY_DX8SLBDQSCTL_DXSR_MASK 0x00000300U +#define DDR_PHY_DX8SLBDQSCTL_DXSR_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBDQSCTL_DXSR_SHIFT 8 +#define DDR_PHY_DX8SLBDQSCTL_DXSR_MASK 0x00000300U -/*DQS# Resistor*/ +/* +* DQS# Resistor +*/ #undef DDR_PHY_DX8SLBDQSCTL_DQSNRES_DEFVAL #undef DDR_PHY_DX8SLBDQSCTL_DQSNRES_SHIFT #undef DDR_PHY_DX8SLBDQSCTL_DQSNRES_MASK -#define DDR_PHY_DX8SLBDQSCTL_DQSNRES_DEFVAL 0x00000000 -#define DDR_PHY_DX8SLBDQSCTL_DQSNRES_SHIFT 4 -#define DDR_PHY_DX8SLBDQSCTL_DQSNRES_MASK 0x000000F0U +#define DDR_PHY_DX8SLBDQSCTL_DQSNRES_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBDQSCTL_DQSNRES_SHIFT 4 +#define DDR_PHY_DX8SLBDQSCTL_DQSNRES_MASK 0x000000F0U -/*DQS Resistor*/ +/* +* DQS Resistor +*/ #undef DDR_PHY_DX8SLBDQSCTL_DQSRES_DEFVAL #undef DDR_PHY_DX8SLBDQSCTL_DQSRES_SHIFT #undef DDR_PHY_DX8SLBDQSCTL_DQSRES_MASK -#define DDR_PHY_DX8SLBDQSCTL_DQSRES_DEFVAL 0x00000000 -#define DDR_PHY_DX8SLBDQSCTL_DQSRES_SHIFT 0 -#define DDR_PHY_DX8SLBDQSCTL_DQSRES_MASK 0x0000000FU - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_PIR_RESERVED_31_DEFVAL -#undef DDR_PHY_PIR_RESERVED_31_SHIFT -#undef DDR_PHY_PIR_RESERVED_31_MASK -#define DDR_PHY_PIR_RESERVED_31_DEFVAL 0x00000000 -#define DDR_PHY_PIR_RESERVED_31_SHIFT 31 -#define DDR_PHY_PIR_RESERVED_31_MASK 0x80000000U - -/*Impedance Calibration Bypass*/ -#undef DDR_PHY_PIR_ZCALBYP_DEFVAL -#undef DDR_PHY_PIR_ZCALBYP_SHIFT -#undef DDR_PHY_PIR_ZCALBYP_MASK -#define DDR_PHY_PIR_ZCALBYP_DEFVAL 0x00000000 -#define DDR_PHY_PIR_ZCALBYP_SHIFT 30 -#define DDR_PHY_PIR_ZCALBYP_MASK 0x40000000U - -/*Digital Delay Line (DDL) Calibration Pause*/ -#undef DDR_PHY_PIR_DCALPSE_DEFVAL -#undef DDR_PHY_PIR_DCALPSE_SHIFT -#undef DDR_PHY_PIR_DCALPSE_MASK -#define DDR_PHY_PIR_DCALPSE_DEFVAL 0x00000000 -#define DDR_PHY_PIR_DCALPSE_SHIFT 29 -#define DDR_PHY_PIR_DCALPSE_MASK 0x20000000U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_PIR_RESERVED_28_21_DEFVAL -#undef DDR_PHY_PIR_RESERVED_28_21_SHIFT -#undef DDR_PHY_PIR_RESERVED_28_21_MASK -#define DDR_PHY_PIR_RESERVED_28_21_DEFVAL 0x00000000 -#define DDR_PHY_PIR_RESERVED_28_21_SHIFT 21 -#define DDR_PHY_PIR_RESERVED_28_21_MASK 0x1FE00000U - -/*Write DQS2DQ Training*/ -#undef DDR_PHY_PIR_DQS2DQ_DEFVAL -#undef DDR_PHY_PIR_DQS2DQ_SHIFT -#undef DDR_PHY_PIR_DQS2DQ_MASK -#define DDR_PHY_PIR_DQS2DQ_DEFVAL 0x00000000 -#define DDR_PHY_PIR_DQS2DQ_SHIFT 20 -#define DDR_PHY_PIR_DQS2DQ_MASK 0x00100000U - -/*RDIMM Initialization*/ -#undef DDR_PHY_PIR_RDIMMINIT_DEFVAL -#undef DDR_PHY_PIR_RDIMMINIT_SHIFT -#undef DDR_PHY_PIR_RDIMMINIT_MASK -#define DDR_PHY_PIR_RDIMMINIT_DEFVAL 0x00000000 -#define DDR_PHY_PIR_RDIMMINIT_SHIFT 19 -#define DDR_PHY_PIR_RDIMMINIT_MASK 0x00080000U - -/*Controller DRAM Initialization*/ -#undef DDR_PHY_PIR_CTLDINIT_DEFVAL -#undef DDR_PHY_PIR_CTLDINIT_SHIFT -#undef DDR_PHY_PIR_CTLDINIT_MASK -#define DDR_PHY_PIR_CTLDINIT_DEFVAL 0x00000000 -#define DDR_PHY_PIR_CTLDINIT_SHIFT 18 -#define DDR_PHY_PIR_CTLDINIT_MASK 0x00040000U - -/*VREF Training*/ -#undef DDR_PHY_PIR_VREF_DEFVAL -#undef DDR_PHY_PIR_VREF_SHIFT -#undef DDR_PHY_PIR_VREF_MASK -#define DDR_PHY_PIR_VREF_DEFVAL 0x00000000 -#define DDR_PHY_PIR_VREF_SHIFT 17 -#define DDR_PHY_PIR_VREF_MASK 0x00020000U - -/*Static Read Training*/ -#undef DDR_PHY_PIR_SRD_DEFVAL -#undef DDR_PHY_PIR_SRD_SHIFT -#undef DDR_PHY_PIR_SRD_MASK -#define DDR_PHY_PIR_SRD_DEFVAL 0x00000000 -#define DDR_PHY_PIR_SRD_SHIFT 16 -#define DDR_PHY_PIR_SRD_MASK 0x00010000U - -/*Write Data Eye Training*/ -#undef DDR_PHY_PIR_WREYE_DEFVAL -#undef DDR_PHY_PIR_WREYE_SHIFT -#undef DDR_PHY_PIR_WREYE_MASK -#define DDR_PHY_PIR_WREYE_DEFVAL 0x00000000 -#define DDR_PHY_PIR_WREYE_SHIFT 15 -#define DDR_PHY_PIR_WREYE_MASK 0x00008000U - -/*Read Data Eye Training*/ -#undef DDR_PHY_PIR_RDEYE_DEFVAL -#undef DDR_PHY_PIR_RDEYE_SHIFT -#undef DDR_PHY_PIR_RDEYE_MASK -#define DDR_PHY_PIR_RDEYE_DEFVAL 0x00000000 -#define DDR_PHY_PIR_RDEYE_SHIFT 14 -#define DDR_PHY_PIR_RDEYE_MASK 0x00004000U - -/*Write Data Bit Deskew*/ -#undef DDR_PHY_PIR_WRDSKW_DEFVAL -#undef DDR_PHY_PIR_WRDSKW_SHIFT -#undef DDR_PHY_PIR_WRDSKW_MASK -#define DDR_PHY_PIR_WRDSKW_DEFVAL 0x00000000 -#define DDR_PHY_PIR_WRDSKW_SHIFT 13 -#define DDR_PHY_PIR_WRDSKW_MASK 0x00002000U - -/*Read Data Bit Deskew*/ -#undef DDR_PHY_PIR_RDDSKW_DEFVAL -#undef DDR_PHY_PIR_RDDSKW_SHIFT -#undef DDR_PHY_PIR_RDDSKW_MASK -#define DDR_PHY_PIR_RDDSKW_DEFVAL 0x00000000 -#define DDR_PHY_PIR_RDDSKW_SHIFT 12 -#define DDR_PHY_PIR_RDDSKW_MASK 0x00001000U - -/*Write Leveling Adjust*/ -#undef DDR_PHY_PIR_WLADJ_DEFVAL -#undef DDR_PHY_PIR_WLADJ_SHIFT -#undef DDR_PHY_PIR_WLADJ_MASK -#define DDR_PHY_PIR_WLADJ_DEFVAL 0x00000000 -#define DDR_PHY_PIR_WLADJ_SHIFT 11 -#define DDR_PHY_PIR_WLADJ_MASK 0x00000800U - -/*Read DQS Gate Training*/ -#undef DDR_PHY_PIR_QSGATE_DEFVAL -#undef DDR_PHY_PIR_QSGATE_SHIFT -#undef DDR_PHY_PIR_QSGATE_MASK -#define DDR_PHY_PIR_QSGATE_DEFVAL 0x00000000 -#define DDR_PHY_PIR_QSGATE_SHIFT 10 -#define DDR_PHY_PIR_QSGATE_MASK 0x00000400U - -/*Write Leveling*/ -#undef DDR_PHY_PIR_WL_DEFVAL -#undef DDR_PHY_PIR_WL_SHIFT -#undef DDR_PHY_PIR_WL_MASK -#define DDR_PHY_PIR_WL_DEFVAL 0x00000000 -#define DDR_PHY_PIR_WL_SHIFT 9 -#define DDR_PHY_PIR_WL_MASK 0x00000200U - -/*DRAM Initialization*/ -#undef DDR_PHY_PIR_DRAMINIT_DEFVAL -#undef DDR_PHY_PIR_DRAMINIT_SHIFT -#undef DDR_PHY_PIR_DRAMINIT_MASK -#define DDR_PHY_PIR_DRAMINIT_DEFVAL 0x00000000 -#define DDR_PHY_PIR_DRAMINIT_SHIFT 8 -#define DDR_PHY_PIR_DRAMINIT_MASK 0x00000100U - -/*DRAM Reset (DDR3/DDR4/LPDDR4 Only)*/ -#undef DDR_PHY_PIR_DRAMRST_DEFVAL -#undef DDR_PHY_PIR_DRAMRST_SHIFT -#undef DDR_PHY_PIR_DRAMRST_MASK -#define DDR_PHY_PIR_DRAMRST_DEFVAL 0x00000000 -#define DDR_PHY_PIR_DRAMRST_SHIFT 7 -#define DDR_PHY_PIR_DRAMRST_MASK 0x00000080U - -/*PHY Reset*/ -#undef DDR_PHY_PIR_PHYRST_DEFVAL -#undef DDR_PHY_PIR_PHYRST_SHIFT -#undef DDR_PHY_PIR_PHYRST_MASK -#define DDR_PHY_PIR_PHYRST_DEFVAL 0x00000000 -#define DDR_PHY_PIR_PHYRST_SHIFT 6 -#define DDR_PHY_PIR_PHYRST_MASK 0x00000040U - -/*Digital Delay Line (DDL) Calibration*/ -#undef DDR_PHY_PIR_DCAL_DEFVAL -#undef DDR_PHY_PIR_DCAL_SHIFT -#undef DDR_PHY_PIR_DCAL_MASK -#define DDR_PHY_PIR_DCAL_DEFVAL 0x00000000 -#define DDR_PHY_PIR_DCAL_SHIFT 5 -#define DDR_PHY_PIR_DCAL_MASK 0x00000020U - -/*PLL Initialiazation*/ -#undef DDR_PHY_PIR_PLLINIT_DEFVAL -#undef DDR_PHY_PIR_PLLINIT_SHIFT -#undef DDR_PHY_PIR_PLLINIT_MASK -#define DDR_PHY_PIR_PLLINIT_DEFVAL 0x00000000 -#define DDR_PHY_PIR_PLLINIT_SHIFT 4 -#define DDR_PHY_PIR_PLLINIT_MASK 0x00000010U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_PIR_RESERVED_3_DEFVAL -#undef DDR_PHY_PIR_RESERVED_3_SHIFT -#undef DDR_PHY_PIR_RESERVED_3_MASK -#define DDR_PHY_PIR_RESERVED_3_DEFVAL 0x00000000 -#define DDR_PHY_PIR_RESERVED_3_SHIFT 3 -#define DDR_PHY_PIR_RESERVED_3_MASK 0x00000008U - -/*CA Training*/ -#undef DDR_PHY_PIR_CA_DEFVAL -#undef DDR_PHY_PIR_CA_SHIFT -#undef DDR_PHY_PIR_CA_MASK -#define DDR_PHY_PIR_CA_DEFVAL 0x00000000 -#define DDR_PHY_PIR_CA_SHIFT 2 -#define DDR_PHY_PIR_CA_MASK 0x00000004U - -/*Impedance Calibration*/ -#undef DDR_PHY_PIR_ZCAL_DEFVAL -#undef DDR_PHY_PIR_ZCAL_SHIFT -#undef DDR_PHY_PIR_ZCAL_MASK -#define DDR_PHY_PIR_ZCAL_DEFVAL 0x00000000 -#define DDR_PHY_PIR_ZCAL_SHIFT 1 -#define DDR_PHY_PIR_ZCAL_MASK 0x00000002U - -/*Initialization Trigger*/ -#undef DDR_PHY_PIR_INIT_DEFVAL -#undef DDR_PHY_PIR_INIT_SHIFT -#undef DDR_PHY_PIR_INIT_MASK -#define DDR_PHY_PIR_INIT_DEFVAL 0x00000000 -#define DDR_PHY_PIR_INIT_SHIFT 0 -#define DDR_PHY_PIR_INIT_MASK 0x00000001U +#define DDR_PHY_DX8SLBDQSCTL_DQSRES_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBDQSCTL_DQSRES_SHIFT 0 +#define DDR_PHY_DX8SLBDQSCTL_DQSRES_MASK 0x0000000FU #undef IOU_SLCR_MIO_PIN_0_OFFSET #define IOU_SLCR_MIO_PIN_0_OFFSET 0XFF180000 #undef IOU_SLCR_MIO_PIN_1_OFFSET @@ -17132,7308 +21605,9482 @@ #undef IOU_SLCR_MIO_LOOPBACK_OFFSET #define IOU_SLCR_MIO_LOOPBACK_OFFSET 0XFF180200 -/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out- (QSPI Clock)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out- + * (QSPI Clock) +*/ #undef IOU_SLCR_MIO_PIN_0_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_0_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_0_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_0_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_0_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_0_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_0_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_0_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_0_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_0_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_0_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_0_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_0_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_0_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_0_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_0_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_0_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_0_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[0]- (Test Scan Port) = test_scan, Outp - t, test_scan_out[0]- (Test Scan Port) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[0]- (Test Scan Port) = test_scan, Output, test_scan_out[0 + * ]- (Test Scan Port) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_0_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_0_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_0_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_0_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_0_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_0_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_0_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_0_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_0_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[0]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[0]- (GPIO bank 0) 1= can - , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa - ) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Cloc - ) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_ - lk- (Trace Port Clock)*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[0]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[0]- (GPIO bank 0) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG + * TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sc + * lk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Out + * put, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_c + * lk- (Trace Port Clock) +*/ #undef IOU_SLCR_MIO_PIN_0_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_0_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_0_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_0_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_0_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_0_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_0_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_0_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_0_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (QSPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Data - us)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (Q + * SPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Databus) +*/ #undef IOU_SLCR_MIO_PIN_1_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_1_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_1_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_1_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_1_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_1_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_1_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_1_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_1_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_1_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_1_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_1_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_1_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_1_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_1_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_1_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_1_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_1_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[1]- (Test Scan Port) = test_scan, Outp - t, test_scan_out[1]- (Test Scan Port) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[1]- (Test Scan Port) = test_scan, Output, test_scan_out[1 + * ]- (Test Scan Port) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_1_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_1_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_1_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_1_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_1_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_1_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_1_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_1_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_1_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[1]- (GPIO bank 0) 1= can - , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal - 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_o - t- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control - Signal)*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[1]- (GPIO bank 0) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG + * TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc3, Ou + * tput, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART + * receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control + * Signal) +*/ #undef IOU_SLCR_MIO_PIN_1_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_1_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_1_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_1_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_1_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_1_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_1_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_1_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_1_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI + * Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus) +*/ #undef IOU_SLCR_MIO_PIN_2_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_2_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_2_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_2_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_2_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_2_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_2_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_2_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_2_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_2_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_2_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_2_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_2_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_2_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_2_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_2_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_2_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_2_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[2]- (Test Scan Port) = test_scan, Outp - t, test_scan_out[2]- (Test Scan Port) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[2]- (Test Scan Port) = test_scan, Output, test_scan_out[2 + * ]- (Test Scan Port) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_2_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_2_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_2_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_2_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_2_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_2_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_2_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_2_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_2_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[2]- (GPIO bank 0) 1= can - , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal - 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc2, Input, ttc2_clk_in - (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[0]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[2]- (GPIO bank 0) 1= can0, Input, can0_phy_ + * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + * , Output, i2c0_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTAG + * TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc2, I + * nput, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver se + * rial input) 7= trace, Output, tracedq[0]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_2_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_2_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_2_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_2_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_2_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_2_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_2_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_2_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_2_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI + * Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus) +*/ #undef IOU_SLCR_MIO_PIN_3_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_3_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_3_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_3_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_3_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_3_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_3_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_3_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_3_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_3_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_3_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_3_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_3_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_3_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_3_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_3_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_3_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_3_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[3]- (Test Scan Port) = test_scan, Outp - t, test_scan_out[3]- (Test Scan Port) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[3]- (Test Scan Port) = test_scan, Output, test_scan_out[3 + * ]- (Test Scan Port) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_3_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_3_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_3_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_3_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_3_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_3_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_3_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_3_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_3_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[3]- (GPIO bank 0) 1= can - , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa - ) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0 - - (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial - output) 7= trace, Output, tracedq[1]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[3]- (GPIO bank 0) 1= can0, Output, can0_phy + * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + * 0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG + * TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output + * , spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- + * (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial + * output) 7= trace, Output, tracedq[1]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_3_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_3_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_3_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_3_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_3_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_3_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_3_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_3_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_3_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- (QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Data - us)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- ( + * QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Databus) +*/ #undef IOU_SLCR_MIO_PIN_4_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_4_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_4_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_4_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_4_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_4_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_4_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_4_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_4_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_4_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_4_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_4_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_4_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_4_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_4_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_4_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_4_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_4_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[4]- (Test Scan Port) = test_scan, Outp - t, test_scan_out[4]- (Test Scan Port) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[4]- (Test Scan Port) = test_scan, Output, test_scan_out[4 + * ]- (Test Scan Port) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_4_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_4_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_4_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_4_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_4_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_4_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_4_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_4_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_4_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[4]- (GPIO bank 0) 1= can - , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa - ) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_s - - (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, - utput, tracedq[2]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[4]- (GPIO bank 0) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Wa + * tch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi + * 0, Output, spi0_so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Cloc + * k) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, O + * utput, tracedq[2]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_4_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_4_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_4_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_4_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_4_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_4_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_4_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_4_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_4_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out- (QSPI Slave Select)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out- + * (QSPI Slave Select) +*/ #undef IOU_SLCR_MIO_PIN_5_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_5_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_5_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_5_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_5_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_5_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_5_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_5_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_5_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_5_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_5_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_5_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_5_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_5_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_5_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_5_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_5_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_5_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[5]- (Test Scan Port) = test_scan, Outp - t, test_scan_out[5]- (Test Scan Port) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[5]- (Test Scan Port) = test_scan, Output, test_scan_out[5 + * ]- (Test Scan Port) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_5_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_5_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_5_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_5_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_5_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_5_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_5_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_5_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_5_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[5]- (GPIO bank 0) 1= can - , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal - 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi0 - si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7 - trace, Output, tracedq[3]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[5]- (GPIO bank 0) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (W + * atch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= + * spi0, Input, spi0_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC + * Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= + * trace, Output, tracedq[3]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_5_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_5_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_5_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_5_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_5_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_5_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_5_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_5_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_5_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_clk_for_lpbk- (QSPI Clock to be fed-back)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_clk_for_l + * pbk- (QSPI Clock to be fed-back) +*/ #undef IOU_SLCR_MIO_PIN_6_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_6_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_6_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_6_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_6_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_6_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_6_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_6_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_6_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_6_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_6_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_6_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_6_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_6_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_6_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_6_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_6_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_6_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[6]- (Test Scan Port) = test_scan, Outp - t, test_scan_out[6]- (Test Scan Port) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[6]- (Test Scan Port) = test_scan, Output, test_scan_out[6 + * ]- (Test Scan Port) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_6_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_6_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_6_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_6_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_6_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_6_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_6_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_6_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_6_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[6]- (GPIO bank 0) 1= can - , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal - 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1 - sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, - Output, tracedq[4]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[6]- (GPIO bank 0) 1= can0, Input, can0_phy_ + * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + * , Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Wat + * ch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= s + * pi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TT + * C Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, + * Output, tracedq[4]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_6_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_6_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_6_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_6_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_6_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_6_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_6_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_6_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_6_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out_upper- (QSPI Slave Select upper)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out_ + * upper- (QSPI Slave Select upper) +*/ #undef IOU_SLCR_MIO_PIN_7_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_7_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_7_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_7_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_7_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_7_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_7_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_7_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_7_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_7_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_7_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_7_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_7_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_7_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_7_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_7_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_7_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_7_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[7]- (Test Scan Port) = test_scan, Outp - t, test_scan_out[7]- (Test Scan Port) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[7]- (Test Scan Port) = test_scan, Output, test_scan_out[7 + * ]- (Test Scan Port) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_7_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_7_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_7_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_7_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_7_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_7_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_7_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_7_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_7_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[7]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[7]- (GPIO bank 0) 1= can - , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa - ) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= - tc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, - racedq[5]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[7]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[7]- (GPIO bank 0) 1= can0, Output, can0_phy + * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + * 0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- ( + * Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Ma + * ster Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua + * 0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, t + * racedq[5]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_7_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_7_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_7_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_7_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_7_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_7_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_7_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_7_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_7_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[0]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe - [0]- (QSPI Upper Databus)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[0 + * ]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[0]- (QSPI Upper D + * atabus) +*/ #undef IOU_SLCR_MIO_PIN_8_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_8_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_8_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_8_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_8_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_8_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_8_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_8_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_8_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_8_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_8_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_8_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_8_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_8_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_8_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_8_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_8_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_8_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[8]- (Test Scan Port) = test_scan, Outp - t, test_scan_out[8]- (Test Scan Port) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[8]- (Test Scan Port) = test_scan, Output, test_scan_out[8 + * ]- (Test Scan Port) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_8_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_8_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_8_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_8_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_8_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_8_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_8_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_8_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_8_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[8]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[8]- (GPIO bank 0) 1= can - , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa - ) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc - , Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Tr - ce Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[8]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[8]- (GPIO bank 0) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Wa + * tch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Maste + * r Selects) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_ + * txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Tra + * ce Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_8_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_8_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_8_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_8_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_8_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_8_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_8_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_8_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_8_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[1]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe - [1]- (QSPI Upper Databus)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[1 + * ]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[1]- (QSPI Upper D + * atabus) +*/ #undef IOU_SLCR_MIO_PIN_9_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_9_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_9_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_9_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_9_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_9_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_9_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_9_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_9_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NAND chip enable)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NA + * ND chip enable) +*/ #undef IOU_SLCR_MIO_PIN_9_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_9_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_9_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_9_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_9_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_9_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_9_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_9_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_9_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[9]- (Test Scan Port) = test_scan, Outp - t, test_scan_out[9]- (Test Scan Port) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[9]- (Test Scan Port) = test_scan, Output, test_scan_out[9 + * ]- (Test Scan Port) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_9_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_9_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_9_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_9_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_9_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_9_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_9_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_9_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_9_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[9]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[9]- (GPIO bank 0) 1= can - , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal - 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, - utput, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (U - RT receiver serial input) 7= trace, Output, tracedq[7]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[9]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[9]- (GPIO bank 0) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (W + * atch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master S + * elects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc3, + * Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UA + * RT receiver serial input) 7= trace, Output, tracedq[7]- (Trace Port Data + * bus) +*/ #undef IOU_SLCR_MIO_PIN_9_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_9_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_9_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_9_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_9_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_9_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_9_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_9_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_9_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[2]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe - [2]- (QSPI Upper Databus)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[2 + * ]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[2]- (QSPI Upper D + * atabus) +*/ #undef IOU_SLCR_MIO_PIN_10_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_10_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_10_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_10_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_10_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_10_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_10_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_10_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_10_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (NAND Ready/Busy)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (N + * AND Ready/Busy) +*/ #undef IOU_SLCR_MIO_PIN_10_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_10_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_10_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_10_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_10_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_10_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_10_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_10_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_10_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[10]- (Test Scan Port) = test_scan, Out - ut, test_scan_out[10]- (Test Scan Port) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[10]- (Test Scan Port) = test_scan, Output, test_scan_out[ + * 10]- (Test Scan Port) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_10_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_10_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_10_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_10_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_10_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_10_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_10_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_10_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_10_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[10]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[10]- (GPIO bank 0) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_ - o- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outp - t, tracedq[8]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[10]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[10]- (GPIO bank 0) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= sp + * i1, Output, spi1_so- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clo + * ck) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outpu + * t, tracedq[8]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_10_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_10_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_10_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_10_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_10_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_10_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_10_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_10_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_10_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[3]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe - [3]- (QSPI Upper Databus)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[3 + * ]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[3]- (QSPI Upper D + * atabus) +*/ #undef IOU_SLCR_MIO_PIN_11_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_11_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_11_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_11_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_11_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_11_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_11_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_11_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_11_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (NAND Ready/Busy)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (N + * AND Ready/Busy) +*/ #undef IOU_SLCR_MIO_PIN_11_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_11_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_11_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_11_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_11_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_11_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_11_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_11_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_11_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[11]- (Test Scan Port) = test_scan, Out - ut, test_scan_out[11]- (Test Scan Port) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[11]- (Test Scan Port) = test_scan, Output, test_scan_out[ + * 11]- (Test Scan Port) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_11_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_11_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_11_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_11_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_11_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_11_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_11_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_11_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_11_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s - i1_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o - tput) 7= trace, Output, tracedq[9]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) + * 4= spi1, Input, spi1_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- ( + * TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial ou + * tput) 7= trace, Output, tracedq[9]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_11_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_11_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_11_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_11_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_11_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_11_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_11_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_11_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_11_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out_upper- (QSPI Upper Clock)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out_ + * upper- (QSPI Upper Clock) +*/ #undef IOU_SLCR_MIO_PIN_12_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_12_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_12_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_12_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_12_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_12_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_12_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_12_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_12_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NAND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe - */ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NA + * ND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe) +*/ #undef IOU_SLCR_MIO_PIN_12_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_12_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_12_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_12_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_12_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_12_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_12_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_12_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_12_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[12]- (Test Scan Port) = test_scan, Out - ut, test_scan_out[12]- (Test Scan Port) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[12]- (Test Scan Port) = test_scan, Output, test_scan_out[ + * 12]- (Test Scan Port) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_12_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_12_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_12_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_12_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_12_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_12_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_12_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_12_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_12_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[12]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[12]- (GPIO bank 0) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Cl - ck) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trac - dq[10]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[12]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[12]- (GPIO bank 0) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJT + * AG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_ + * sclk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, O + * utput, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace + * dq[10]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_12_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_12_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_12_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_12_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_12_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_12_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_12_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_12_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_12_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_13_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_13_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_13_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_13_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_13_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_13_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_13_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_13_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_13_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[0]- (NAND chip enable)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[0]- (NA + * ND chip enable) +*/ #undef IOU_SLCR_MIO_PIN_13_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_13_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_13_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_13_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_13_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_13_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_13_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_13_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_13_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8 - bit Data bus) 2= test_scan, Input, test_scan_in[13]- (Test Scan Port) = test_scan, Output, test_scan_out[13]- (Test Scan Port - 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[13]- (Test Scan Port) = test_scan, Output, + * test_scan_out[13]- (Test Scan Port) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_13_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_13_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_13_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_13_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_13_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_13_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_13_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_13_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_13_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[13]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[13]- (GPIO bank 0) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave - out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq[11]- (Trace Port Dat - bus)*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[13]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[13]- (GPIO bank 0) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTA + * G TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, + * Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UAR + * T receiver serial input) 7= trace, Output, tracedq[11]- (Trace Port Data + * bus) +*/ #undef IOU_SLCR_MIO_PIN_13_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_13_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_13_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_13_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_13_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_13_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_13_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_13_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_13_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_14_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_14_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_14_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_14_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_14_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_14_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_14_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_14_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_14_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_cle- (NAND Command Latch Enable)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_cle- (NAND + * Command Latch Enable) +*/ #undef IOU_SLCR_MIO_PIN_14_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_14_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_14_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_14_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_14_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_14_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_14_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_14_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_14_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8 - bit Data bus) 2= test_scan, Input, test_scan_in[14]- (Test Scan Port) = test_scan, Output, test_scan_out[14]- (Test Scan Port - 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[14]- (Test Scan Port) = test_scan, Output, + * test_scan_out[14]- (Test Scan Port) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_14_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_14_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_14_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_14_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_14_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_14_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_14_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_14_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_14_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, Input, ttc0_clk_ - n- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJT + * AG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, + * Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver + * serial input) 7= trace, Output, tracedq[12]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_14_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_14_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_14_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_14_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_14_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_14_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_14_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_14_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_14_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_15_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_15_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_15_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_15_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_15_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_15_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_15_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_15_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_15_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ale- (NAND Address Latch Enable)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ale- (NAND + * Address Latch Enable) +*/ #undef IOU_SLCR_MIO_PIN_15_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_15_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_15_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_15_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_15_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_15_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_15_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_15_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_15_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8 - bit Data bus) 2= test_scan, Input, test_scan_in[15]- (Test Scan Port) = test_scan, Output, test_scan_out[15]- (Test Scan Port - 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[15]- (Test Scan Port) = test_scan, Output, + * test_scan_out[15]- (Test Scan Port) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_15_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_15_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_15_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_15_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_15_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_15_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_15_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_15_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_15_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[15]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[15]- (GPIO bank 0) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out - 0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter seri - l output) 7= trace, Output, tracedq[13]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[15]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[15]- (GPIO bank 0) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJT + * AG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Outp + * ut, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_ou + * t- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter seria + * l output) 7= trace, Output, tracedq[13]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_15_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_15_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_15_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_15_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_15_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_15_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_15_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_15_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_15_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_16_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_16_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_16_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_16_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_16_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_16_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_16_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_16_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_16_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[0]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[0]- (NAND - ata Bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[0]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[0]- (NAND Data Bus) +*/ #undef IOU_SLCR_MIO_PIN_16_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_16_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_16_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_16_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_16_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_16_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_16_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_16_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_16_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8 - bit Data bus) 2= test_scan, Input, test_scan_in[16]- (Test Scan Port) = test_scan, Output, test_scan_out[16]- (Test Scan Port - 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[16]- (Test Scan Port) = test_scan, Output, + * test_scan_out[16]- (Test Scan Port) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_16_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_16_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_16_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_16_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_16_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_16_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_16_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_16_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_16_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[16]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[16]- (GPIO bank 0) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0 - so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace - Output, tracedq[14]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[16]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[16]- (GPIO bank 0) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= s + * pi0, Output, spi0_so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Cl + * ock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, + * Output, tracedq[14]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_16_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_16_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_16_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_16_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_16_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_16_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_16_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_16_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_16_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_17_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_17_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_17_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_17_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_17_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_17_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_17_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_17_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_17_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[1]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[1]- (NAND - ata Bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[1]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[1]- (NAND Data Bus) +*/ #undef IOU_SLCR_MIO_PIN_17_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_17_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_17_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_17_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_17_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_17_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_17_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_17_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_17_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8 - bit Data bus) 2= test_scan, Input, test_scan_in[17]- (Test Scan Port) = test_scan, Output, test_scan_out[17]- (Test Scan Port - 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[17]- (Test Scan Port) = test_scan, Output, + * test_scan_out[17]- (Test Scan Port) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_17_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_17_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_17_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_17_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_17_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_17_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_17_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_17_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_17_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[17]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[17]- (GPIO bank 0) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, sp - 0_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) - 7= trace, Output, tracedq[15]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[17]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[17]- (GPIO bank 0) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4 + * = spi0, Input, spi0_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (T + * TC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) + * 7= trace, Output, tracedq[15]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_17_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_17_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_17_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_17_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_17_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_17_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_17_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_17_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_17_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_18_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_18_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_18_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_18_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_18_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_18_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_18_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_18_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_18_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[2]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[2]- (NAND - ata Bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[2]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[2]- (NAND Data Bus) +*/ #undef IOU_SLCR_MIO_PIN_18_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_18_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_18_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_18_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_18_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_18_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_18_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_18_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_18_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8 - bit Data bus) 2= test_scan, Input, test_scan_in[18]- (Test Scan Port) = test_scan, Output, test_scan_out[18]- (Test Scan Port - 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[18]- (Test Scan Port) = test_scan, Output, + * test_scan_out[18]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU + * Ext Tamper) +*/ #undef IOU_SLCR_MIO_PIN_18_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_18_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_18_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_18_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_18_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_18_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_18_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_18_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_18_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[18]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[18]- (GPIO bank 0) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_ - o- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[18]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[18]- (GPIO bank 0) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= sp + * i1, Output, spi1_so- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clo + * ck) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used +*/ #undef IOU_SLCR_MIO_PIN_18_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_18_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_18_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_18_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_18_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_18_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_18_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_18_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_18_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_19_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_19_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_19_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_19_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_19_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_19_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_19_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_19_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_19_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[3]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[3]- (NAND - ata Bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[3]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[3]- (NAND Data Bus) +*/ #undef IOU_SLCR_MIO_PIN_19_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_19_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_19_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_19_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_19_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_19_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_19_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_19_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_19_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8 - bit Data bus) 2= test_scan, Input, test_scan_in[19]- (Test Scan Port) = test_scan, Output, test_scan_out[19]- (Test Scan Port - 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[19]- (Test Scan Port) = test_scan, Output, + * test_scan_out[19]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU + * Ext Tamper) +*/ #undef IOU_SLCR_MIO_PIN_19_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_19_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_19_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_19_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_19_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_19_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_19_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_19_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_19_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[19]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[19]- (GPIO bank 0) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5 - ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[19]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[19]- (GPIO bank 0) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI + * Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= + * ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used +*/ #undef IOU_SLCR_MIO_PIN_19_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_19_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_19_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_19_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_19_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_19_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_19_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_19_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_19_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_20_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_20_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_20_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_20_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_20_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_20_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_20_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_20_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_20_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[4]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[4]- (NAND - ata Bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[4]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[4]- (NAND Data Bus) +*/ #undef IOU_SLCR_MIO_PIN_20_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_20_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_20_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_20_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_20_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_20_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_20_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_20_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_20_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8 - bit Data bus) 2= test_scan, Input, test_scan_in[20]- (Test Scan Port) = test_scan, Output, test_scan_out[20]- (Test Scan Port - 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[20]- (Test Scan Port) = test_scan, Output, + * test_scan_out[20]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU + * Ext Tamper) +*/ #undef IOU_SLCR_MIO_PIN_20_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_20_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_20_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_20_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_20_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_20_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_20_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_20_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_20_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[20]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[20]- (GPIO bank 0) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= t - c1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Used*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[20]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[20]- (GPIO bank 0) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Mas + * ter Selects) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua + * 1_txd- (UART transmitter serial output) 7= Not Used +*/ #undef IOU_SLCR_MIO_PIN_20_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_20_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_20_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_20_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_20_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_20_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_20_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_20_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_20_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_21_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_21_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_21_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_21_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_21_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_21_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_21_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_21_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_21_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[5]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[5]- (NAND - ata Bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[5]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[5]- (NAND Data Bus) +*/ #undef IOU_SLCR_MIO_PIN_21_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_21_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_21_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_21_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_21_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_21_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_21_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_21_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_21_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Comman - Indicator) 2= test_scan, Input, test_scan_in[21]- (Test Scan Port) = test_scan, Output, test_scan_out[21]- (Test Scan Port) - = csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Com + * mand Indicator) = sd0, Output, sdio0_cmd_out- (Command Indicator) 2= tes + * t_scan, Input, test_scan_in[21]- (Test Scan Port) = test_scan, Output, t + * est_scan_out[21]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU E + * xt Tamper) +*/ #undef IOU_SLCR_MIO_PIN_21_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_21_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_21_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_21_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_21_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_21_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_21_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_21_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_21_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[21]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[21]- (GPIO bank 0) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1 - Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- - UART receiver serial input) 7= Not Used*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[21]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[21]- (GPIO bank 0) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master + * Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc + * 1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- ( + * UART receiver serial input) 7= Not Used +*/ #undef IOU_SLCR_MIO_PIN_21_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_21_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_21_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_21_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_21_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_21_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_21_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_21_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_21_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_22_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_22_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_22_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_22_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_22_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_22_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_22_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_22_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_22_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_we_b- (NAND Write Enable)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_we_b- (NAN + * D Write Enable) +*/ #undef IOU_SLCR_MIO_PIN_22_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_22_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_22_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_22_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_22_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_22_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_22_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_22_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_22_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= test_scan, Input, test_scan_in[22]- - (Test Scan Port) = test_scan, Output, test_scan_out[22]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- + * (SDSDIO clock) 2= test_scan, Input, test_scan_in[22]- (Test Scan Port) = + * test_scan, Output, test_scan_out[22]- (Test Scan Port) 3= csu, Input, c + * su_ext_tamper- (CSU Ext Tamper) +*/ #undef IOU_SLCR_MIO_PIN_22_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_22_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_22_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_22_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_22_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_22_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_22_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_22_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_22_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[22]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[22]- (GPIO bank 0) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, sp - 1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not - sed*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[22]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[22]- (GPIO bank 0) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= + * spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- ( + * TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not U + * sed +*/ #undef IOU_SLCR_MIO_PIN_22_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_22_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_22_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_22_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_22_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_22_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_22_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_22_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_22_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_23_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_23_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_23_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_23_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_23_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_23_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_23_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_23_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_23_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[6]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[6]- (NAND - ata Bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[6]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[6]- (NAND Data Bus) +*/ #undef IOU_SLCR_MIO_PIN_23_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_23_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_23_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_23_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_23_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_23_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_23_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_23_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_23_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= test_scan, Input, test_scan_in - 23]- (Test Scan Port) = test_scan, Output, test_scan_out[23]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper - */ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- + * (SD card bus power) 2= test_scan, Input, test_scan_in[23]- (Test Scan Po + * rt) = test_scan, Output, test_scan_out[23]- (Test Scan Port) 3= csu, Inp + * ut, csu_ext_tamper- (CSU Ext Tamper) +*/ #undef IOU_SLCR_MIO_PIN_23_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_23_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_23_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_23_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_23_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_23_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_23_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_23_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_23_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[23]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[23]- (GPIO bank 0) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s - i1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o - tput) 7= Not Used*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[23]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[23]- (GPIO bank 0) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) + * 4= spi1, Input, spi1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- ( + * TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial ou + * tput) 7= Not Used +*/ #undef IOU_SLCR_MIO_PIN_23_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_23_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_23_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_23_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_23_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_23_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_23_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_23_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_23_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_24_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_24_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_24_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_24_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_24_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_24_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_24_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_24_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_24_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[7]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[7]- (NAND - ata Bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[7]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[7]- (NAND Data Bus) +*/ #undef IOU_SLCR_MIO_PIN_24_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_24_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_24_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_24_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_24_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_24_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_24_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_24_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_24_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= test_scan, Input, test - scan_in[24]- (Test Scan Port) = test_scan, Output, test_scan_out[24]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ex - Tamper)*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD + * card detect from connector) 2= test_scan, Input, test_scan_in[24]- (Test + * Scan Port) = test_scan, Output, test_scan_out[24]- (Test Scan Port) 3= + * csu, Input, csu_ext_tamper- (CSU Ext Tamper) +*/ #undef IOU_SLCR_MIO_PIN_24_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_24_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_24_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_24_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_24_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_24_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_24_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_24_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_24_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[24]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[24]- (GPIO bank 0) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= Not Used 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, - Output, ua1_txd- (UART transmitter serial output) 7= Not Used*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[24]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[24]- (GPIO bank 0) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= Not Used 5= ttc3, Input, ttc3_clk_in- (T + * TC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= N + * ot Used +*/ #undef IOU_SLCR_MIO_PIN_24_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_24_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_24_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_24_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_24_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_24_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_24_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_24_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_24_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_25_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_25_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_25_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_25_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_25_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_25_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_25_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_25_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_25_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_re_n- (NAND Read Enable)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_re_n- (NAN + * D Read Enable) +*/ #undef IOU_SLCR_MIO_PIN_25_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_25_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_25_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_25_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_25_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_25_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_25_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_25_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_25_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= test_scan, Input, - test_scan_in[25]- (Test Scan Port) = test_scan, Output, test_scan_out[25]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (C - U Ext Tamper)*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD ca + * rd write protect from connector) 2= test_scan, Input, test_scan_in[25]- + * (Test Scan Port) = test_scan, Output, test_scan_out[25]- (Test Scan Port + * ) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper) +*/ #undef IOU_SLCR_MIO_PIN_25_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_25_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_25_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_25_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_25_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_25_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_25_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_25_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_25_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[25]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[25]- (GPIO bank 0) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= Not Used 5= ttc3, Output, ttc3_wave_out- (TTC Waveform - lock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[25]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[25]- (GPIO bank 0) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= Not Used 5= ttc3, Output, ttc3_wave_ou + * t- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial in + * put) 7= Not Used +*/ #undef IOU_SLCR_MIO_PIN_25_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_25_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_25_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_25_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_25_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_25_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_25_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_25_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_25_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_clk- (TX RGMII clock)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ + * clk- (TX RGMII clock) +*/ #undef IOU_SLCR_MIO_PIN_26_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_26_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_26_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_26_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_26_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_26_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_26_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_26_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_26_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NAND chip enable)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NA + * ND chip enable) +*/ #undef IOU_SLCR_MIO_PIN_26_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_26_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_26_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_26_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_26_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_26_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_26_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_26_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_26_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[0]- (PMU GPI) 2= test_scan, Input, test_scan_in[26]- (Test Sc - n Port) = test_scan, Output, test_scan_out[26]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[0]- (PMU + * GPI) 2= test_scan, Input, test_scan_in[26]- (Test Scan Port) = test_sca + * n, Output, test_scan_out[26]- (Test Scan Port) 3= csu, Input, csu_ext_ta + * mper- (CSU Ext Tamper) +*/ #undef IOU_SLCR_MIO_PIN_26_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_26_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_26_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_26_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_26_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_26_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_26_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_26_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_26_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[0]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[0]- (GPIO bank 1) 1= can - , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal - 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Clock - 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- - Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[0]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[0]- (GPIO bank 1) 1= can0, Input, can0_phy_ + * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + * , Output, i2c0_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG + * TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_scl + * k_out- (SPI Clock) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Inpu + * t, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- ( + * Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_26_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_26_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_26_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_26_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_26_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_26_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_26_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_26_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_26_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[0]- (TX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd + * [0]- (TX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_27_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_27_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_27_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_27_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_27_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_27_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_27_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_27_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_27_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (NAND Ready/Busy)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (N + * AND Ready/Busy) +*/ #undef IOU_SLCR_MIO_PIN_27_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_27_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_27_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_27_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_27_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_27_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_27_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_27_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_27_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[1]- (PMU GPI) 2= test_scan, Input, test_scan_in[27]- (Test Sc - n Port) = test_scan, Output, test_scan_out[27]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Outp - t, dp_aux_data_out- (Dp Aux Data)*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[1]- (PMU + * GPI) 2= test_scan, Input, test_scan_in[27]- (Test Scan Port) = test_sca + * n, Output, test_scan_out[27]- (Test Scan Port) 3= dpaux, Input, dp_aux_d + * ata_in- (Dp Aux Data) = dpaux, Output, dp_aux_data_out- (Dp Aux Data) +*/ #undef IOU_SLCR_MIO_PIN_27_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_27_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_27_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_27_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_27_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_27_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_27_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_27_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_27_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[1]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[1]- (GPIO bank 1) 1= can - , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa - ) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_ - ut- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port - atabus)*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[1]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[1]- (GPIO bank 1) 1= can0, Output, can0_phy + * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + * 0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG + * TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc2, O + * utput, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UAR + * T transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port D + * atabus) +*/ #undef IOU_SLCR_MIO_PIN_27_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_27_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_27_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_27_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_27_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_27_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_27_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_27_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_27_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[1]- (TX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd + * [1]- (TX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_28_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_28_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_28_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_28_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_28_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_28_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_28_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_28_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_28_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (NAND Ready/Busy)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (N + * AND Ready/Busy) +*/ #undef IOU_SLCR_MIO_PIN_28_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_28_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_28_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_28_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_28_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_28_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_28_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_28_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_28_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[2]- (PMU GPI) 2= test_scan, Input, test_scan_in[28]- (Test Sc - n Port) = test_scan, Output, test_scan_out[28]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[2]- (PMU + * GPI) 2= test_scan, Input, test_scan_in[28]- (Test Scan Port) = test_sca + * n, Output, test_scan_out[28]- (Test Scan Port) 3= dpaux, Input, dp_hot_p + * lug_detect- (Dp Aux Hot Plug) +*/ #undef IOU_SLCR_MIO_PIN_28_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_28_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_28_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_28_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_28_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_28_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_28_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_28_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_28_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[2]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[2]- (GPIO bank 1) 1= can - , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa - ) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc1, Input, ttc1_clk_i - - (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[2]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[2]- (GPIO bank 1) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTA + * G TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc1, + * Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitt + * er serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_28_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_28_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_28_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_28_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_28_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_28_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_28_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_28_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_28_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[2]- (TX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd + * [2]- (TX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_29_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_29_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_29_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_29_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_29_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_29_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_29_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_29_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_29_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + * PCIE Reset signal) +*/ #undef IOU_SLCR_MIO_PIN_29_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_29_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_29_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_29_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_29_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_29_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_29_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_29_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_29_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[3]- (PMU GPI) 2= test_scan, Input, test_scan_in[29]- (Test Sc - n Port) = test_scan, Output, test_scan_out[29]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Outp - t, dp_aux_data_out- (Dp Aux Data)*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[3]- (PMU + * GPI) 2= test_scan, Input, test_scan_in[29]- (Test Scan Port) = test_sca + * n, Output, test_scan_out[29]- (Test Scan Port) 3= dpaux, Input, dp_aux_d + * ata_in- (Dp Aux Data) = dpaux, Output, dp_aux_data_out- (Dp Aux Data) +*/ #undef IOU_SLCR_MIO_PIN_29_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_29_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_29_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_29_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_29_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_29_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_29_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_29_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_29_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[3]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[3]- (GPIO bank 1) 1= can - , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal - 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0] - (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial inpu - ) 7= trace, Output, tracedq[7]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[3]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[3]- (GPIO bank 1) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG + * TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, + * spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- + * (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input + * ) 7= trace, Output, tracedq[7]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_29_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_29_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_29_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_29_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_29_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_29_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_29_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_29_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_29_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[3]- (TX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd + * [3]- (TX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_30_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_30_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_30_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_30_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_30_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_30_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_30_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_30_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_30_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + * PCIE Reset signal) +*/ #undef IOU_SLCR_MIO_PIN_30_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_30_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_30_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_30_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_30_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_30_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_30_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_30_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_30_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[4]- (PMU GPI) 2= test_scan, Input, test_scan_in[30]- (Test Sc - n Port) = test_scan, Output, test_scan_out[30]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[4]- (PMU + * GPI) 2= test_scan, Input, test_scan_in[30]- (Test Scan Port) = test_sca + * n, Output, test_scan_out[30]- (Test Scan Port) 3= dpaux, Input, dp_hot_p + * lug_detect- (Dp Aux Hot Plug) +*/ #undef IOU_SLCR_MIO_PIN_30_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_30_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_30_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_30_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_30_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_30_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_30_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_30_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_30_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[4]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[4]- (GPIO bank 1) 1= can - , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal - 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_so - (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output - tracedq[8]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[4]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[4]- (GPIO bank 1) 1= can0, Input, can0_phy_ + * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + * , Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Wat + * ch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0 + * , Output, spi0_so- (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clock + * ) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, + * tracedq[8]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_30_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_30_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_30_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_30_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_30_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_30_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_30_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_30_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_30_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ctl- (TX RGMII control)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ + * ctl- (TX RGMII control) +*/ #undef IOU_SLCR_MIO_PIN_31_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_31_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_31_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_31_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_31_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_31_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_31_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_31_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_31_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + * PCIE Reset signal) +*/ #undef IOU_SLCR_MIO_PIN_31_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_31_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_31_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_31_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_31_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_31_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_31_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_31_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_31_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[5]- (PMU GPI) 2= test_scan, Input, test_scan_in[31]- (Test Sc - n Port) = test_scan, Output, test_scan_out[31]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[5]- (PMU + * GPI) 2= test_scan, Input, test_scan_in[31]- (Test Scan Port) = test_sca + * n, Output, test_scan_out[31]- (Test Scan Port) 3= csu, Input, csu_ext_ta + * mper- (CSU Ext Tamper) +*/ #undef IOU_SLCR_MIO_PIN_31_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_31_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_31_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_31_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_31_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_31_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_31_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_31_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_31_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[5]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[5]- (GPIO bank 1) 1= can - , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa - ) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi - _si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial out - ut) 7= trace, Output, tracedq[9]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[5]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[5]- (GPIO bank 1) 1= can0, Output, can0_phy + * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + * 0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- ( + * Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= + * spi0, Input, spi0_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TT + * C Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial outp + * ut) 7= trace, Output, tracedq[9]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_31_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_31_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_31_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_31_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_31_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_31_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_31_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_31_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_31_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_clk- (RX RGMII clock)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_c + * lk- (RX RGMII clock) +*/ #undef IOU_SLCR_MIO_PIN_32_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_32_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_32_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_32_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_32_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_32_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_32_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_32_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_32_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NAND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe - */ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NA + * ND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe) +*/ #undef IOU_SLCR_MIO_PIN_32_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_32_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_32_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_32_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_32_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_32_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_32_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_32_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_32_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[0]- (PMU GPI) 2= test_scan, Input, test_scan_in[32]- (Test S - an Port) = test_scan, Output, test_scan_out[32]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[0]- (PM + * U GPI) 2= test_scan, Input, test_scan_in[32]- (Test Scan Port) = test_sc + * an, Output, test_scan_out[32]- (Test Scan Port) 3= csu, Input, csu_ext_t + * amper- (CSU Ext Tamper) +*/ #undef IOU_SLCR_MIO_PIN_32_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_32_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_32_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_32_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_32_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_32_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_32_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_32_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_32_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[6]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[6]- (GPIO bank 1) 1= can - , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa - ) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi - _sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= - race, Output, tracedq[10]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[6]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[6]- (GPIO bank 1) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Wa + * tch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= + * spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (T + * TC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= t + * race, Output, tracedq[10]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_32_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_32_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_32_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_32_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_32_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_32_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_32_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_32_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_32_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[0]- (RX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[ + * 0]- (RX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_33_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_33_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_33_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_33_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_33_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_33_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_33_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_33_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_33_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + * PCIE Reset signal) +*/ #undef IOU_SLCR_MIO_PIN_33_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_33_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_33_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_33_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_33_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_33_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_33_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_33_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_33_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[1]- (PMU GPI) 2= test_scan, Input, test_scan_in[33]- (Test S - an Port) = test_scan, Output, test_scan_out[33]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[1]- (PM + * U GPI) 2= test_scan, Input, test_scan_in[33]- (Test Scan Port) = test_sc + * an, Output, test_scan_out[33]- (Test Scan Port) 3= csu, Input, csu_ext_t + * amper- (CSU Ext Tamper) +*/ #undef IOU_SLCR_MIO_PIN_33_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_33_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_33_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_33_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_33_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_33_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_33_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_33_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_33_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[7]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[7]- (GPIO bank 1) 1= can - , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal - 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= t - c3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, traced - [11]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[7]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[7]- (GPIO bank 1) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (W + * atch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Mas + * ter Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1 + * , Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq + * [11]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_33_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_33_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_33_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_33_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_33_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_33_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_33_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_33_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_33_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[1]- (RX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[ + * 1]- (RX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_34_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_34_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_34_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_34_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_34_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_34_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_34_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_34_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_34_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + * PCIE Reset signal) +*/ #undef IOU_SLCR_MIO_PIN_34_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_34_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_34_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_34_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_34_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_34_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_34_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_34_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_34_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[2]- (PMU GPI) 2= test_scan, Input, test_scan_in[34]- (Test S - an Port) = test_scan, Output, test_scan_out[34]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Out - ut, dp_aux_data_out- (Dp Aux Data)*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[2]- (PM + * U GPI) 2= test_scan, Input, test_scan_in[34]- (Test Scan Port) = test_sc + * an, Output, test_scan_out[34]- (Test Scan Port) 3= dpaux, Input, dp_aux_ + * data_in- (Dp Aux Data) = dpaux, Output, dp_aux_data_out- (Dp Aux Data) +*/ #undef IOU_SLCR_MIO_PIN_34_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_34_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_34_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_34_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_34_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_34_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_34_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_34_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_34_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[8]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[8]- (GPIO bank 1) 1= can - , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal - 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc2 - Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace P - rt Databus)*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[8]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[8]- (GPIO bank 1) 1= can0, Input, can0_phy_ + * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + * , Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Wat + * ch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master + * Selects) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rx + * d- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace Po + * rt Databus) +*/ #undef IOU_SLCR_MIO_PIN_34_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_34_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_34_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_34_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_34_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_34_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_34_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_34_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_34_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[2]- (RX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[ + * 2]- (RX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_35_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_35_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_35_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_35_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_35_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_35_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_35_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_35_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_35_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + * PCIE Reset signal) +*/ #undef IOU_SLCR_MIO_PIN_35_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_35_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_35_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_35_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_35_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_35_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_35_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_35_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_35_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[3]- (PMU GPI) 2= test_scan, Input, test_scan_in[35]- (Test S - an Port) = test_scan, Output, test_scan_out[35]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[3]- (PM + * U GPI) 2= test_scan, Input, test_scan_in[35]- (Test Scan Port) = test_sc + * an, Output, test_scan_out[35]- (Test Scan Port) 3= dpaux, Input, dp_hot_ + * plug_detect- (Dp Aux Hot Plug) +*/ #undef IOU_SLCR_MIO_PIN_35_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_35_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_35_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_35_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_35_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_35_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_35_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_35_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_35_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[9]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[9]- (GPIO bank 1) 1= can - , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa - ) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, - Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- - UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[9]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[9]- (GPIO bank 1) 1= can0, Output, can0_phy + * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + * 0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- ( + * Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master + * Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc2 + * , Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- ( + * UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace Po + * rt Databus) +*/ #undef IOU_SLCR_MIO_PIN_35_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_35_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_35_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_35_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_35_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_35_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_35_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_35_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_35_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[3]- (RX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[ + * 3]- (RX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_36_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_36_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_36_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_36_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_36_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_36_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_36_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_36_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_36_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + * PCIE Reset signal) +*/ #undef IOU_SLCR_MIO_PIN_36_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_36_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_36_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_36_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_36_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_36_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_36_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_36_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_36_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[4]- (PMU GPI) 2= test_scan, Input, test_scan_in[36]- (Test S - an Port) = test_scan, Output, test_scan_out[36]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Out - ut, dp_aux_data_out- (Dp Aux Data)*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[4]- (PM + * U GPI) 2= test_scan, Input, test_scan_in[36]- (Test Scan Port) = test_sc + * an, Output, test_scan_out[36]- (Test Scan Port) 3= dpaux, Input, dp_aux_ + * data_in- (Dp Aux Data) = dpaux, Output, dp_aux_data_out- (Dp Aux Data) +*/ #undef IOU_SLCR_MIO_PIN_36_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_36_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_36_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_36_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_36_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_36_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_36_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_36_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_36_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[10]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[10]- (GPIO bank 1) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1 - so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace - Output, tracedq[14]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[10]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[10]- (GPIO bank 1) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= s + * pi1, Output, spi1_so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Cl + * ock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, + * Output, tracedq[14]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_36_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_36_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_36_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_36_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_36_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_36_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_36_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_36_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_36_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_ctl- (RX RGMII control )*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_c + * tl- (RX RGMII control ) +*/ #undef IOU_SLCR_MIO_PIN_37_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_37_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_37_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_37_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_37_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_37_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_37_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_37_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_37_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + * PCIE Reset signal) +*/ #undef IOU_SLCR_MIO_PIN_37_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_37_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_37_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_37_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_37_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_37_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_37_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_37_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_37_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[5]- (PMU GPI) 2= test_scan, Input, test_scan_in[37]- (Test S - an Port) = test_scan, Output, test_scan_out[37]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[5]- (PM + * U GPI) 2= test_scan, Input, test_scan_in[37]- (Test Scan Port) = test_sc + * an, Output, test_scan_out[37]- (Test Scan Port) 3= dpaux, Input, dp_hot_ + * plug_detect- (Dp Aux Hot Plug) +*/ #undef IOU_SLCR_MIO_PIN_37_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_37_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_37_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_37_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_37_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_37_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_37_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_37_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_37_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[11]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[11]- (GPIO bank 1) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, sp - 1_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) - 7= trace, Output, tracedq[15]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[11]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[11]- (GPIO bank 1) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4 + * = spi1, Input, spi1_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (T + * TC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) + * 7= trace, Output, tracedq[15]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_37_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_37_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_37_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_37_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_37_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_37_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_37_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_37_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_37_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_clk- (TX RGMII clock)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ + * clk- (TX RGMII clock) +*/ #undef IOU_SLCR_MIO_PIN_38_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_38_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_38_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_38_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_38_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_38_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_38_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_38_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_38_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_38_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_38_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_38_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_38_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_38_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_38_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_38_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_38_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_38_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= Not Used 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- + * (SDSDIO clock) 2= Not Used 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_38_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_38_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_38_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_38_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_38_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_38_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_38_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_38_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_38_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[12]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[12]- (GPIO bank 1) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Clo - k) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, trace_clk- - (Trace Port Clock)*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[12]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[12]- (GPIO bank 1) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTA + * G TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_s + * clk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, In + * put, ua0_rxd- (UART receiver serial input) 7= trace, Output, trace_clk- + * (Trace Port Clock) +*/ #undef IOU_SLCR_MIO_PIN_38_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_38_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_38_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_38_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_38_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_38_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_38_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_38_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_38_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[0]- (TX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd + * [0]- (TX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_39_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_39_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_39_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_39_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_39_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_39_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_39_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_39_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_39_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_39_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_39_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_39_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_39_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_39_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_39_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_39_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_39_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_39_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= sd1, Input, sd1_data_i - [4]- (8-bit Data bus) = sd1, Output, sdio1_data_out[4]- (8-bit Data bus) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD + * card detect from connector) 2= sd1, Input, sd1_data_in[4]- (8-bit Data b + * us) = sd1, Output, sdio1_data_out[4]- (8-bit Data bus) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_39_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_39_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_39_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_39_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_39_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_39_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_39_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_39_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_39_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[13]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[13]- (GPIO bank 1) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc0, Output, ttc0_wav - _out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, trace_ctl- (Trace Port - Control Signal)*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[13]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[13]- (GPIO bank 1) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJT + * AG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc0, + * Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (U + * ART transmitter serial output) 7= trace, Output, trace_ctl- (Trace Port + * Control Signal) +*/ #undef IOU_SLCR_MIO_PIN_39_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_39_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_39_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_39_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_39_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_39_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_39_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_39_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_39_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[1]- (TX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd + * [1]- (TX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_40_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_40_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_40_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_40_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_40_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_40_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_40_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_40_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_40_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_40_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_40_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_40_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_40_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_40_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_40_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_40_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_40_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_40_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Comman - Indicator) 2= sd1, Input, sd1_data_in[5]- (8-bit Data bus) = sd1, Output, sdio1_data_out[5]- (8-bit Data bus) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Com + * mand Indicator) = sd0, Output, sdio0_cmd_out- (Command Indicator) 2= sd1 + * , Input, sd1_data_in[5]- (8-bit Data bus) = sd1, Output, sdio1_data_out[ + * 5]- (8-bit Data bus) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_40_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_40_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_40_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_40_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_40_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_40_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_40_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_40_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_40_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[14]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[14]- (GPIO bank 1) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc3, Input, ttc3_clk - in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[0]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[14]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[14]- (GPIO bank 1) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJ + * TAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc3 + * , Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmi + * tter serial output) 7= trace, Output, tracedq[0]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_40_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_40_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_40_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_40_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_40_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_40_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_40_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_40_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_40_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[2]- (TX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd + * [2]- (TX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_41_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_41_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_41_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_41_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_41_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_41_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_41_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_41_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_41_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_41_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_41_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_41_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_41_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_41_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_41_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_41_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_41_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_41_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8 - bit Data bus) 2= sd1, Input, sd1_data_in[6]- (8-bit Data bus) = sd1, Output, sdio1_data_out[6]- (8-bit Data bus) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[6]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[6]- (8-bit Data bus) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_41_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_41_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_41_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_41_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_41_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_41_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_41_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_41_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_41_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[15]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[15]- (GPIO bank 1) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[ - ]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial in - ut) 7= trace, Output, tracedq[1]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[15]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[15]- (GPIO bank 1) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTA + * G TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Outpu + * t, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out + * - (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial inp + * ut) 7= trace, Output, tracedq[1]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_41_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_41_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_41_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_41_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_41_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_41_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_41_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_41_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_41_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[3]- (TX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd + * [3]- (TX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_42_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_42_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_42_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_42_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_42_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_42_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_42_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_42_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_42_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_42_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_42_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_42_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_42_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_42_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_42_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_42_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_42_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_42_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8 - bit Data bus) 2= sd1, Input, sd1_data_in[7]- (8-bit Data bus) = sd1, Output, sdio1_data_out[7]- (8-bit Data bus) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[7]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[7]- (8-bit Data bus) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_42_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_42_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_42_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_42_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_42_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_42_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_42_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_42_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_42_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_ - o- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outp - t, tracedq[2]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= sp + * i0, Output, spi0_so- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clo + * ck) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outpu + * t, tracedq[2]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_42_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_42_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_42_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_42_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_42_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_42_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_42_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_42_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_42_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ctl- (TX RGMII control)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ + * ctl- (TX RGMII control) +*/ #undef IOU_SLCR_MIO_PIN_43_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_43_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_43_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_43_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_43_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_43_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_43_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_43_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_43_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_43_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_43_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_43_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_43_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_43_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_43_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_43_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_43_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_43_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8 - bit Data bus) 2= sd1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8-bit Data bus) 2= s + * d1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_43_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_43_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_43_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_43_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_43_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_43_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_43_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_43_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_43_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, s - i0_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o - tput) 7= trace, Output, tracedq[3]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) + * 4= spi0, Input, spi0_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- ( + * TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial ou + * tput) 7= trace, Output, tracedq[3]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_43_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_43_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_43_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_43_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_43_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_43_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_43_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_43_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_43_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_clk- (RX RGMII clock)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_c + * lk- (RX RGMII clock) +*/ #undef IOU_SLCR_MIO_PIN_44_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_44_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_44_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_44_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_44_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_44_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_44_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_44_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_44_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_44_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_44_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_44_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_44_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_44_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_44_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_44_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_44_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_44_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8 - bit Data bus) 2= sd1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8-bit Data bus) 2= s + * d1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_44_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_44_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_44_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_44_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_44_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_44_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_44_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_44_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_44_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[18]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[18]- (GPIO bank 1) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, s - i1_sclk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7 - Not Used*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[18]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[18]- (GPIO bank 1) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4 + * = spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- + * (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= + * Not Used +*/ #undef IOU_SLCR_MIO_PIN_44_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_44_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_44_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_44_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_44_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_44_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_44_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_44_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_44_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[0]- (RX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[ + * 0]- (RX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_45_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_45_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_45_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_45_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_45_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_45_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_45_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_45_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_45_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_45_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_45_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_45_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_45_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_45_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_45_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_45_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_45_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_45_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8 - bit Data bus) 2= sd1, Input, sdio1_cd_n- (SD card detect from connector) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8-bit Data bus) 2= s + * d1, Input, sdio1_cd_n- (SD card detect from connector) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_45_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_45_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_45_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_45_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_45_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_45_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_45_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_45_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_45_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[19]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[19]- (GPIO bank 1) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= - ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[19]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[19]- (GPIO bank 1) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI M + * aster Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= u + * a1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used +*/ #undef IOU_SLCR_MIO_PIN_45_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_45_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_45_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_45_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_45_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_45_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_45_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_45_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_45_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[1]- (RX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[ + * 1]- (RX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_46_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_46_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_46_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_46_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_46_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_46_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_46_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_46_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_46_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_46_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_46_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_46_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_46_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_46_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_46_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_46_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_46_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_46_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8 - bit Data bus) 2= sd1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_out[0]- (8-bit Data bus) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[0]- (8-bit Data bus) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_46_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_46_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_46_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_46_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_46_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_46_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_46_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_46_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_46_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= tt - 0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Mast + * er Selects) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_ + * rxd- (UART receiver serial input) 7= Not Used +*/ #undef IOU_SLCR_MIO_PIN_46_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_46_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_46_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_46_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_46_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_46_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_46_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_46_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_46_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[2]- (RX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[ + * 2]- (RX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_47_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_47_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_47_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_47_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_47_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_47_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_47_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_47_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_47_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_47_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_47_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_47_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_47_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_47_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_47_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_47_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_47_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_47_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8 - bit Data bus) 2= sd1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_out[1]- (8-bit Data bus) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[1]- (8-bit Data bus) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_47_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_47_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_47_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_47_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_47_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_47_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_47_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_47_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_47_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi - , Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd - (UART transmitter serial output) 7= Not Used*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Maste + * r Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= tt + * c0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- + * (UART transmitter serial output) 7= Not Used +*/ #undef IOU_SLCR_MIO_PIN_47_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_47_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_47_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_47_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_47_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_47_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_47_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_47_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_47_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[3]- (RX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[ + * 3]- (RX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_48_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_48_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_48_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_48_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_48_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_48_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_48_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_48_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_48_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_48_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_48_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_48_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_48_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_48_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_48_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_48_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_48_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_48_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8 - bit Data bus) 2= sd1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_out[2]- (8-bit Data bus) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[2]- (8-bit Data bus) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_48_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_48_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_48_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_48_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_48_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_48_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_48_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_48_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_48_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[22]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[22]- (GPIO bank 1) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1 - so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not U - ed*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[22]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[22]- (GPIO bank 1) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= s + * pi1, Output, spi1_so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Cl + * ock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Us + * ed +*/ #undef IOU_SLCR_MIO_PIN_48_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_48_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_48_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_48_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_48_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_48_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_48_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_48_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_48_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_ctl- (RX RGMII control )*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_c + * tl- (RX RGMII control ) +*/ #undef IOU_SLCR_MIO_PIN_49_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_49_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_49_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_49_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_49_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_49_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_49_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_49_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_49_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_49_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_49_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_49_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_49_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_49_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_49_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_49_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_49_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_49_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= sd1, Input, sd1_data_in[3]- (8 - bit Data bus) = sd1, Output, sdio1_data_out[3]- (8-bit Data bus) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- + * (SD card bus power) 2= sd1, Input, sd1_data_in[3]- (8-bit Data bus) = sd + * 1, Output, sdio1_data_out[3]- (8-bit Data bus) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_49_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_49_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_49_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_49_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_49_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_49_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_49_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_49_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_49_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[23]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[23]- (GPIO bank 1) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, sp - 1_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) - 7= Not Used*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[23]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[23]- (GPIO bank 1) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4 + * = spi1, Input, spi1_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (T + * TC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) + * 7= Not Used +*/ #undef IOU_SLCR_MIO_PIN_49_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_49_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_49_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_49_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_49_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_49_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_49_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_49_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_49_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- (TSU clock)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- + * (TSU clock) +*/ #undef IOU_SLCR_MIO_PIN_50_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_50_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_50_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_50_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_50_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_50_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_50_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_50_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_50_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_50_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_50_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_50_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_50_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_50_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_50_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_50_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_50_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_50_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= sd1, Input, sd1_c - d_in- (Command Indicator) = sd1, Output, sdio1_cmd_out- (Command Indicator) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD ca + * rd write protect from connector) 2= sd1, Input, sd1_cmd_in- (Command Ind + * icator) = sd1, Output, sdio1_cmd_out- (Command Indicator) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_50_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_50_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_50_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_50_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_50_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_50_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_50_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_50_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_50_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[24]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[24]- (GPIO bank 1) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= ttc2, Input, ttc2 - clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[24]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[24]- (GPIO bank 1) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= + * ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART rece + * iver serial input) 7= Not Used +*/ #undef IOU_SLCR_MIO_PIN_50_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_50_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_50_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_50_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_50_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_50_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_50_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_50_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_50_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- (TSU clock)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- + * (TSU clock) +*/ #undef IOU_SLCR_MIO_PIN_51_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_51_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_51_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_51_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_51_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_51_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_51_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_51_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_51_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_51_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_51_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_51_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_51_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_51_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_51_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_51_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_51_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_51_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Output, sdio1_clk_out- (SDSDIO clock) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Output, sdi + * o1_clk_out- (SDSDIO clock) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_51_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_51_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_51_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_51_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_51_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_51_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_51_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_51_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_51_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[25]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[25]- (GPIO bank 1) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= mdio1, Input, gem1_mdio_in- (MDIO Data) 4= mdio1, Outp - t, gem1_mdio_out- (MDIO Data) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter - serial output) 7= Not Used*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[25]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[25]- (GPIO bank 1) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= mdio1, Input, gem1_mdio_in- (MDIO Dat + * a) 4= mdio1, Output, gem1_mdio_out- (MDIO Data) 5= ttc2, Output, ttc2_wa + * ve_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter + * serial output) 7= Not Used +*/ #undef IOU_SLCR_MIO_PIN_51_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_51_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_51_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_51_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_51_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_51_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_51_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_51_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_51_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_clk- (TX RGMII clock)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_ + * clk- (TX RGMII clock) +*/ #undef IOU_SLCR_MIO_PIN_52_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_52_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_52_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_52_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_52_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_52_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_52_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_52_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_52_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_clk_in- (ULPI Clock)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_clk_i + * n- (ULPI Clock) +*/ #undef IOU_SLCR_MIO_PIN_52_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_52_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_52_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_52_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_52_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_52_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_52_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_52_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_52_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used +*/ #undef IOU_SLCR_MIO_PIN_52_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_52_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_52_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_52_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_52_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_52_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_52_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_52_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_52_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[0]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[0]- (GPIO bank 2) 1= can - , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa - ) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Cloc - ) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_ - lk- (Trace Port Clock)*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[0]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[0]- (GPIO bank 2) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG + * TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sc + * lk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Out + * put, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_c + * lk- (Trace Port Clock) +*/ #undef IOU_SLCR_MIO_PIN_52_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_52_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_52_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_52_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_52_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_52_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_52_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_52_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_52_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[0]- (TX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd + * [0]- (TX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_53_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_53_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_53_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_53_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_53_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_53_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_53_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_53_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_53_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_dir- (Data bus direction control)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_dir- + * (Data bus direction control) +*/ #undef IOU_SLCR_MIO_PIN_53_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_53_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_53_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_53_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_53_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_53_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_53_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_53_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_53_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used +*/ #undef IOU_SLCR_MIO_PIN_53_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_53_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_53_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_53_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_53_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_53_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_53_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_53_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_53_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[1]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[1]- (GPIO bank 2) 1= can - , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal - 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_o - t- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control - Signal)*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[1]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[1]- (GPIO bank 2) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG + * TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Ou + * tput, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART + * receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control + * Signal) +*/ #undef IOU_SLCR_MIO_PIN_53_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_53_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_53_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_53_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_53_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_53_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_53_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_53_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_53_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[1]- (TX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd + * [1]- (TX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_54_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_54_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_54_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_54_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_54_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_54_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_54_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_54_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_54_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[2]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_ - ata[2]- (ULPI data bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[2]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[2]- (ULPI data + * bus) +*/ #undef IOU_SLCR_MIO_PIN_54_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_54_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_54_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_54_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_54_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_54_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_54_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_54_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_54_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used +*/ #undef IOU_SLCR_MIO_PIN_54_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_54_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_54_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_54_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_54_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_54_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_54_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_54_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_54_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[2]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[2]- (GPIO bank 2) 1= can - , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal - 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, Input, ttc0_clk_in - (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[0]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[2]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[2]- (GPIO bank 2) 1= can0, Input, can0_phy_ + * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + * , Output, i2c0_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTAG + * TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, I + * nput, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver se + * rial input) 7= trace, Output, tracedq[0]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_54_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_54_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_54_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_54_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_54_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_54_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_54_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_54_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_54_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[2]- (TX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd + * [2]- (TX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_55_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_55_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_55_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_55_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_55_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_55_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_55_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_55_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_55_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_nxt- (Data flow control signal from the PHY)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_nxt- + * (Data flow control signal from the PHY) +*/ #undef IOU_SLCR_MIO_PIN_55_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_55_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_55_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_55_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_55_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_55_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_55_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_55_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_55_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used +*/ #undef IOU_SLCR_MIO_PIN_55_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_55_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_55_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_55_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_55_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_55_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_55_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_55_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_55_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[3]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[3]- (GPIO bank 2) 1= can - , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa - ) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0 - - (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial - output) 7= trace, Output, tracedq[1]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[3]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[3]- (GPIO bank 2) 1= can0, Output, can0_phy + * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + * 0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG + * TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output + * , spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- + * (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial + * output) 7= trace, Output, tracedq[1]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_55_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_55_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_55_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_55_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_55_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_55_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_55_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_55_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_55_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[3]- (TX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd + * [3]- (TX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_56_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_56_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_56_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_56_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_56_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_56_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_56_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_56_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_56_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[0]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_ - ata[0]- (ULPI data bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[0]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[0]- (ULPI data + * bus) +*/ #undef IOU_SLCR_MIO_PIN_56_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_56_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_56_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_56_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_56_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_56_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_56_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_56_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_56_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used +*/ #undef IOU_SLCR_MIO_PIN_56_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_56_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_56_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_56_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_56_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_56_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_56_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_56_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_56_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[4]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[4]- (GPIO bank 2) 1= can - , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa - ) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_s - - (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, - utput, tracedq[2]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[4]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[4]- (GPIO bank 2) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Wa + * tch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi + * 0, Output, spi0_so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Cloc + * k) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, O + * utput, tracedq[2]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_56_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_56_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_56_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_56_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_56_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_56_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_56_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_56_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_56_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_ctl- (TX RGMII control)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_ + * ctl- (TX RGMII control) +*/ #undef IOU_SLCR_MIO_PIN_57_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_57_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_57_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_57_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_57_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_57_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_57_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_57_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_57_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[1]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_ - ata[1]- (ULPI data bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[1]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[1]- (ULPI data + * bus) +*/ #undef IOU_SLCR_MIO_PIN_57_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_57_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_57_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_57_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_57_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_57_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_57_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_57_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_57_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used +*/ #undef IOU_SLCR_MIO_PIN_57_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_57_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_57_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_57_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_57_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_57_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_57_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_57_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_57_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[5]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[5]- (GPIO bank 2) 1= can - , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal - 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi0 - si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7 - trace, Output, tracedq[3]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[5]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[5]- (GPIO bank 2) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (W + * atch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= + * spi0, Input, spi0_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC + * Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= + * trace, Output, tracedq[3]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_57_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_57_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_57_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_57_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_57_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_57_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_57_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_57_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_57_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_clk- (RX RGMII clock)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_c + * lk- (RX RGMII clock) +*/ #undef IOU_SLCR_MIO_PIN_58_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_58_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_58_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_58_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_58_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_58_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_58_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_58_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_58_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Output, usb0_ulpi_stp- (Asserted to end or interrupt transfers)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Output, usb0_ulpi_stp- + * (Asserted to end or interrupt transfers) +*/ #undef IOU_SLCR_MIO_PIN_58_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_58_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_58_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_58_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_58_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_58_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_58_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_58_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_58_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used +*/ #undef IOU_SLCR_MIO_PIN_58_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_58_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_58_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_58_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_58_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_58_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_58_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_58_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_58_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[6]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[6]- (GPIO bank 2) 1= can - , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal - 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1_sclk_out- (SPI Clock - 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- - Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[6]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[6]- (GPIO bank 2) 1= can0, Input, can0_phy_ + * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + * , Output, i2c0_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG + * TCK) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1_scl + * k_out- (SPI Clock) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Inpu + * t, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- ( + * Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_58_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_58_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_58_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_58_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_58_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_58_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_58_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_58_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_58_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[0]- (RX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[ + * 0]- (RX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_59_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_59_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_59_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_59_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_59_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_59_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_59_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_59_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_59_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[3]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_ - ata[3]- (ULPI data bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[3]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[3]- (ULPI data + * bus) +*/ #undef IOU_SLCR_MIO_PIN_59_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_59_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_59_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_59_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_59_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_59_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_59_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_59_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_59_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used +*/ #undef IOU_SLCR_MIO_PIN_59_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_59_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_59_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_59_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_59_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_59_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_59_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_59_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_59_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[7]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[7]- (GPIO bank 2) 1= can - , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa - ) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_ - ut- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port - atabus)*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[7]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[7]- (GPIO bank 2) 1= can0, Output, can0_phy + * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + * 0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG + * TDI) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= ttc2, O + * utput, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UAR + * T transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port D + * atabus) +*/ #undef IOU_SLCR_MIO_PIN_59_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_59_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_59_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_59_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_59_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_59_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_59_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_59_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_59_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[1]- (RX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[ + * 1]- (RX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_60_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_60_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_60_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_60_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_60_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_60_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_60_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_60_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_60_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[4]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_ - ata[4]- (ULPI data bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[4]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[4]- (ULPI data + * bus) +*/ #undef IOU_SLCR_MIO_PIN_60_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_60_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_60_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_60_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_60_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_60_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_60_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_60_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_60_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used +*/ #undef IOU_SLCR_MIO_PIN_60_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_60_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_60_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_60_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_60_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_60_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_60_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_60_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_60_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[8]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[8]- (GPIO bank 2) 1= can - , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa - ) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc1, Input, ttc1_clk_i - - (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[8]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[8]- (GPIO bank 2) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTA + * G TDO) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc1, + * Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitt + * er serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_60_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_60_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_60_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_60_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_60_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_60_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_60_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_60_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_60_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[2]- (RX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[ + * 2]- (RX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_61_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_61_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_61_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_61_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_61_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_61_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_61_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_61_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_61_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[5]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_ - ata[5]- (ULPI data bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[5]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[5]- (ULPI data + * bus) +*/ #undef IOU_SLCR_MIO_PIN_61_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_61_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_61_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_61_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_61_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_61_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_61_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_61_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_61_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used +*/ #undef IOU_SLCR_MIO_PIN_61_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_61_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_61_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_61_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_61_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_61_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_61_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_61_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_61_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[9]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[9]- (GPIO bank 2) 1= can - , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal - 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, Output, spi1_n_ss_out[0] - (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial inpu - ) 7= trace, Output, tracedq[7]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[9]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[9]- (GPIO bank 2) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG + * TMS) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, Output, + * spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- + * (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input + * ) 7= trace, Output, tracedq[7]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_61_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_61_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_61_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_61_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_61_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_61_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_61_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_61_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_61_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[3]- (RX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[ + * 3]- (RX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_62_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_62_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_62_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_62_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_62_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_62_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_62_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_62_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_62_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[6]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_ - ata[6]- (ULPI data bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[6]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[6]- (ULPI data + * bus) +*/ #undef IOU_SLCR_MIO_PIN_62_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_62_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_62_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_62_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_62_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_62_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_62_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_62_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_62_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used +*/ #undef IOU_SLCR_MIO_PIN_62_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_62_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_62_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_62_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_62_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_62_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_62_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_62_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_62_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[10]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[10]- (GPIO bank 2) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_ - o- (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outp - t, tracedq[8]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[10]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[10]- (GPIO bank 2) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= sp + * i1, Output, spi1_so- (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clo + * ck) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outpu + * t, tracedq[8]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_62_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_62_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_62_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_62_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_62_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_62_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_62_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_62_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_62_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_ctl- (RX RGMII control )*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_c + * tl- (RX RGMII control ) +*/ #undef IOU_SLCR_MIO_PIN_63_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_63_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_63_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_63_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_63_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_63_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_63_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_63_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_63_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[7]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_ - ata[7]- (ULPI data bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[7]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[7]- (ULPI data + * bus) +*/ #undef IOU_SLCR_MIO_PIN_63_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_63_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_63_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_63_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_63_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_63_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_63_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_63_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_63_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used +*/ #undef IOU_SLCR_MIO_PIN_63_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_63_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_63_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_63_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_63_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_63_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_63_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_63_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_63_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[11]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[11]- (GPIO bank 2) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s - i1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o - tput) 7= trace, Output, tracedq[9]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[11]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[11]- (GPIO bank 2) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) + * 4= spi1, Input, spi1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- ( + * TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial ou + * tput) 7= trace, Output, tracedq[9]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_63_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_63_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_63_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_63_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_63_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_63_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_63_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_63_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_63_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_clk- (TX RGMII clock)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_ + * clk- (TX RGMII clock) +*/ #undef IOU_SLCR_MIO_PIN_64_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_64_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_64_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_64_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_64_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_64_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_64_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_64_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_64_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_clk_in- (ULPI Clock)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_clk_i + * n- (ULPI Clock) +*/ #undef IOU_SLCR_MIO_PIN_64_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_64_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_64_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_64_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_64_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_64_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_64_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_64_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_64_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= Not Used 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- + * (SDSDIO clock) 2= Not Used 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_64_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_64_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_64_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_64_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_64_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_64_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_64_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_64_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_64_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[12]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[12]- (GPIO bank 2) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, s - i0_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7 - trace, Output, tracedq[10]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[12]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[12]- (GPIO bank 2) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4 + * = spi0, Output, spi0_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- + * (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= + * trace, Output, tracedq[10]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_64_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_64_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_64_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_64_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_64_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_64_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_64_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_64_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_64_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[0]- (TX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd + * [0]- (TX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_65_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_65_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_65_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_65_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_65_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_65_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_65_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_65_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_65_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_dir- (Data bus direction control)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_dir- + * (Data bus direction control) +*/ #undef IOU_SLCR_MIO_PIN_65_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_65_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_65_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_65_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_65_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_65_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_65_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_65_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_65_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= Not Used 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD + * card detect from connector) 2= Not Used 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_65_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_65_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_65_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_65_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_65_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_65_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_65_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_65_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_65_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[13]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[13]- (GPIO bank 2) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= - ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trac - dq[11]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[13]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[13]- (GPIO bank 2) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi0, Output, spi0_n_ss_out[2]- (SPI M + * aster Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= u + * a1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trace + * dq[11]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_65_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_65_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_65_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_65_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_65_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_65_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_65_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_65_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_65_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[1]- (TX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd + * [1]- (TX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_66_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_66_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_66_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_66_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_66_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_66_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_66_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_66_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_66_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[2]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_ - ata[2]- (ULPI data bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[2]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[2]- (ULPI data + * bus) +*/ #undef IOU_SLCR_MIO_PIN_66_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_66_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_66_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_66_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_66_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_66_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_66_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_66_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_66_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Comman - Indicator) 2= Not Used 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Com + * mand Indicator) = sd0, Output, sdio0_cmd_out- (Command Indicator) 2= Not + * Used 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_66_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_66_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_66_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_66_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_66_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_66_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_66_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_66_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_66_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[14]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[14]- (GPIO bank 2) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= tt - 2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace - Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[14]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[14]- (GPIO bank 2) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Mast + * er Selects) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_ + * rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace + * Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_66_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_66_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_66_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_66_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_66_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_66_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_66_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_66_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_66_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[2]- (TX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd + * [2]- (TX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_67_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_67_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_67_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_67_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_67_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_67_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_67_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_67_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_67_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_nxt- (Data flow control signal from the PHY)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_nxt- + * (Data flow control signal from the PHY) +*/ #undef IOU_SLCR_MIO_PIN_67_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_67_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_67_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_67_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_67_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_67_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_67_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_67_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_67_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8 - bit Data bus) 2= Not Used 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8-bit Data bus) 2= N + * ot Used 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_67_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_67_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_67_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_67_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_67_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_67_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_67_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_67_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_67_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[15]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[15]- (GPIO bank 2) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi - , Output, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd - (UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[15]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[15]- (GPIO bank 2) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi0, Input, spi0_n_ss_in- (SPI Maste + * r Selects) 4= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 5= tt + * c2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- + * (UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace + * Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_67_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_67_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_67_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_67_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_67_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_67_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_67_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_67_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_67_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[3]- (TX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd + * [3]- (TX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_68_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_68_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_68_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_68_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_68_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_68_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_68_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_68_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_68_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[0]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_ - ata[0]- (ULPI data bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[0]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[0]- (ULPI data + * bus) +*/ #undef IOU_SLCR_MIO_PIN_68_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_68_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_68_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_68_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_68_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_68_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_68_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_68_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_68_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8 - bit Data bus) 2= Not Used 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8-bit Data bus) 2= N + * ot Used 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_68_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_68_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_68_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_68_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_68_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_68_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_68_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_68_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_68_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[16]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[16]- (GPIO bank 2) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0 - so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace - Output, tracedq[14]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[16]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[16]- (GPIO bank 2) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= s + * pi0, Output, spi0_so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Cl + * ock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, + * Output, tracedq[14]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_68_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_68_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_68_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_68_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_68_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_68_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_68_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_68_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_68_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_ctl- (TX RGMII control)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_ + * ctl- (TX RGMII control) +*/ #undef IOU_SLCR_MIO_PIN_69_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_69_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_69_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_69_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_69_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_69_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_69_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_69_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_69_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[1]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_ - ata[1]- (ULPI data bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[1]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[1]- (ULPI data + * bus) +*/ #undef IOU_SLCR_MIO_PIN_69_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_69_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_69_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_69_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_69_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_69_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_69_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_69_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_69_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8 - bit Data bus) 2= sd1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8-bit Data bus) 2= s + * d1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_69_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_69_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_69_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_69_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_69_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_69_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_69_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_69_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_69_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[17]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[17]- (GPIO bank 2) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, sp - 0_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) - 7= trace, Output, tracedq[15]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[17]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[17]- (GPIO bank 2) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4 + * = spi0, Input, spi0_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (T + * TC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) + * 7= trace, Output, tracedq[15]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_69_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_69_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_69_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_69_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_69_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_69_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_69_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_69_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_69_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_clk- (RX RGMII clock)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_c + * lk- (RX RGMII clock) +*/ #undef IOU_SLCR_MIO_PIN_70_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_70_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_70_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_70_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_70_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_70_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_70_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_70_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_70_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Output, usb1_ulpi_stp- (Asserted to end or interrupt transfers)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Output, usb1_ulpi_stp- + * (Asserted to end or interrupt transfers) +*/ #undef IOU_SLCR_MIO_PIN_70_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_70_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_70_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_70_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_70_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_70_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_70_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_70_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_70_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8 - bit Data bus) 2= sd1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8-bit Data bus) 2= s + * d1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_70_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_70_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_70_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_70_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_70_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_70_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_70_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_70_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_70_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[18]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[18]- (GPIO bank 2) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, sp - 1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not - sed*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[18]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[18]- (GPIO bank 2) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= + * spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- ( + * TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not U + * sed +*/ #undef IOU_SLCR_MIO_PIN_70_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_70_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_70_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_70_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_70_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_70_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_70_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_70_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_70_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[0]- (RX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[ + * 0]- (RX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_71_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_71_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_71_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_71_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_71_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_71_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_71_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_71_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_71_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[3]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_ - ata[3]- (ULPI data bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[3]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[3]- (ULPI data + * bus) +*/ #undef IOU_SLCR_MIO_PIN_71_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_71_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_71_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_71_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_71_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_71_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_71_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_71_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_71_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8 - bit Data bus) 2= sd1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_out[0]- (8-bit Data bus) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[0]- (8-bit Data bus) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_71_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_71_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_71_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_71_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_71_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_71_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_71_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_71_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_71_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[19]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[19]- (GPIO bank 2) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5 - ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[19]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[19]- (GPIO bank 2) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI + * Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= + * ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used +*/ #undef IOU_SLCR_MIO_PIN_71_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_71_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_71_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_71_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_71_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_71_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_71_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_71_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_71_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[1]- (RX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[ + * 1]- (RX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_72_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_72_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_72_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_72_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_72_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_72_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_72_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_72_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_72_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[4]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_ - ata[4]- (ULPI data bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[4]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[4]- (ULPI data + * bus) +*/ #undef IOU_SLCR_MIO_PIN_72_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_72_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_72_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_72_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_72_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_72_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_72_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_72_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_72_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8 - bit Data bus) 2= sd1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_out[1]- (8-bit Data bus) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[1]- (8-bit Data bus) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_72_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_72_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_72_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_72_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_72_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_72_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_72_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_72_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_72_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[20]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[20]- (GPIO bank 2) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= N - t Used 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Used*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[20]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[20]- (GPIO bank 2) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Mas + * ter Selects) 5= Not Used 6= ua1, Output, ua1_txd- (UART transmitter seri + * al output) 7= Not Used +*/ #undef IOU_SLCR_MIO_PIN_72_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_72_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_72_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_72_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_72_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_72_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_72_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_72_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_72_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[2]- (RX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[ + * 2]- (RX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_73_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_73_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_73_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_73_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_73_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_73_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_73_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_73_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_73_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_ - ata[5]- (ULPI data bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[5]- (ULPI data + * bus) +*/ #undef IOU_SLCR_MIO_PIN_73_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_73_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_73_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_73_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_73_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_73_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_73_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_73_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_73_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8 - bit Data bus) 2= sd1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_out[2]- (8-bit Data bus) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[2]- (8-bit Data bus) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_73_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_73_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_73_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_73_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_73_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_73_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_73_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_73_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_73_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[21]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[21]- (GPIO bank 2) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1 - Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= Not Used 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[21]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[21]- (GPIO bank 2) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master + * Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= Not + * Used 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used +*/ #undef IOU_SLCR_MIO_PIN_73_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_73_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_73_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_73_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_73_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_73_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_73_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_73_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_73_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[3]- (RX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[ + * 3]- (RX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_74_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_74_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_74_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_74_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_74_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_74_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_74_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_74_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_74_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[6]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_ - ata[6]- (ULPI data bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[6]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[6]- (ULPI data + * bus) +*/ #undef IOU_SLCR_MIO_PIN_74_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_74_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_74_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_74_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_74_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_74_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_74_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_74_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_74_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8 - bit Data bus) 2= sd1, Input, sd1_data_in[3]- (8-bit Data bus) = sd1, Output, sdio1_data_out[3]- (8-bit Data bus) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[3]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[3]- (8-bit Data bus) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_74_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_74_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_74_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_74_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_74_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_74_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_74_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_74_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_74_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[22]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[22]- (GPIO bank 2) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_ - o- (MISO signal) 5= Not Used 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[22]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[22]- (GPIO bank 2) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= sp + * i1, Output, spi1_so- (MISO signal) 5= Not Used 6= ua0, Input, ua0_rxd- ( + * UART receiver serial input) 7= Not Used +*/ #undef IOU_SLCR_MIO_PIN_74_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_74_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_74_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_74_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_74_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_74_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_74_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_74_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_74_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_ctl- (RX RGMII control )*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_c + * tl- (RX RGMII control ) +*/ #undef IOU_SLCR_MIO_PIN_75_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_75_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_75_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_75_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_75_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_75_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_75_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_75_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_75_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[7]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_ - ata[7]- (ULPI data bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[7]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[7]- (ULPI data + * bus) +*/ #undef IOU_SLCR_MIO_PIN_75_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_75_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_75_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_75_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_75_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_75_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_75_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_75_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_75_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= sd1, Input, sd1_cmd_in- (Comma - d Indicator) = sd1, Output, sdio1_cmd_out- (Command Indicator) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- + * (SD card bus power) 2= sd1, Input, sd1_cmd_in- (Command Indicator) = sd1 + * , Output, sdio1_cmd_out- (Command Indicator) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_75_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_75_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_75_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_75_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_75_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_75_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_75_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_75_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_75_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[23]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[23]- (GPIO bank 2) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s - i1_si- (MOSI signal) 5= Not Used 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[23]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[23]- (GPIO bank 2) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) + * 4= spi1, Input, spi1_si- (MOSI signal) 5= Not Used 6= ua0, Output, ua0_t + * xd- (UART transmitter serial output) 7= Not Used +*/ #undef IOU_SLCR_MIO_PIN_75_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_75_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_75_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_75_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_75_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_75_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_75_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_75_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_75_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_76_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_76_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_76_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_76_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_76_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_76_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_76_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_76_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_76_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_76_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_76_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_76_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_76_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_76_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_76_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_76_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_76_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_76_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= sd1, Output, sdio - _clk_out- (SDSDIO clock) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD ca + * rd write protect from connector) 2= sd1, Output, sdio1_clk_out- (SDSDIO + * clock) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_76_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_76_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_76_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_76_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_76_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_76_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_76_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_76_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_76_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[24]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[24]- (GPIO bank 2) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= mdio0, Output, gem0_mdc- (MDIO Clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= mdio2, Output, gem2_mdc- (MDIO Clock - 6= mdio3, Output, gem3_mdc- (MDIO Clock) 7= Not Used*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[24]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[24]- (GPIO bank 2) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= mdio0, Output, gem0_mdc- (MDI + * O Clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= mdio2, Output, gem2 + * _mdc- (MDIO Clock) 6= mdio3, Output, gem3_mdc- (MDIO Clock) 7= Not Used +*/ #undef IOU_SLCR_MIO_PIN_76_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_76_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_76_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_76_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_76_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_76_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_76_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_76_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_76_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_77_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_77_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_77_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_77_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_77_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_77_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_77_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_77_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_77_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_77_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_77_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_77_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_77_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_77_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_77_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_77_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_77_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_77_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Input, sdio1_cd_n- (SD card detect from connector) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Input, sdio + * 1_cd_n- (SD card detect from connector) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_77_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_77_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_77_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_77_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_77_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_77_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_77_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_77_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_77_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[25]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[25]- (GPIO bank 2) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= mdio0, Input, gem0_mdio_in- (MDIO Data) 3= mdio0, Output, gem0_mdio_out- (MDIO Data) 4= mdio1, Input, gem1_mdio_in- (MD - O Data) 4= mdio1, Output, gem1_mdio_out- (MDIO Data) 5= mdio2, Input, gem2_mdio_in- (MDIO Data) 5= mdio2, Output, gem2_mdio_o - t- (MDIO Data) 6= mdio3, Input, gem3_mdio_in- (MDIO Data) 6= mdio3, Output, gem3_mdio_out- (MDIO Data) 7= Not Used*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[25]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[25]- (GPIO bank 2) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= mdio0, Input, gem0_mdio_in- (M + * DIO Data) 3= mdio0, Output, gem0_mdio_out- (MDIO Data) 4= mdio1, Input, + * gem1_mdio_in- (MDIO Data) 4= mdio1, Output, gem1_mdio_out- (MDIO Data) 5 + * = mdio2, Input, gem2_mdio_in- (MDIO Data) 5= mdio2, Output, gem2_mdio_ou + * t- (MDIO Data) 6= mdio3, Input, gem3_mdio_in- (MDIO Data) 6= mdio3, Outp + * ut, gem3_mdio_out- (MDIO Data) 7= Not Used +*/ #undef IOU_SLCR_MIO_PIN_77_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_77_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_77_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_77_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_77_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_77_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_77_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_77_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_77_L3_SEL_MASK 0x000000E0U -/*Master Tri-state Enable for pin 0, active high*/ +/* +* Master Tri-state Enable for pin 0, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_SHIFT 0 -#define IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_MASK 0x00000001U +#define IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_SHIFT 0 +#define IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_MASK 0x00000001U -/*Master Tri-state Enable for pin 1, active high*/ +/* +* Master Tri-state Enable for pin 1, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_SHIFT 1 -#define IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_MASK 0x00000002U +#define IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_SHIFT 1 +#define IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_MASK 0x00000002U -/*Master Tri-state Enable for pin 2, active high*/ +/* +* Master Tri-state Enable for pin 2, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_SHIFT 2 -#define IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_MASK 0x00000004U +#define IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_SHIFT 2 +#define IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_MASK 0x00000004U -/*Master Tri-state Enable for pin 3, active high*/ +/* +* Master Tri-state Enable for pin 3, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_SHIFT 3 -#define IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_MASK 0x00000008U +#define IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_SHIFT 3 +#define IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_MASK 0x00000008U -/*Master Tri-state Enable for pin 4, active high*/ +/* +* Master Tri-state Enable for pin 4, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_SHIFT 4 -#define IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_MASK 0x00000010U +#define IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_SHIFT 4 +#define IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_MASK 0x00000010U -/*Master Tri-state Enable for pin 5, active high*/ +/* +* Master Tri-state Enable for pin 5, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_SHIFT 5 -#define IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_MASK 0x00000020U +#define IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_SHIFT 5 +#define IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_MASK 0x00000020U -/*Master Tri-state Enable for pin 6, active high*/ +/* +* Master Tri-state Enable for pin 6, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_SHIFT 6 -#define IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_MASK 0x00000040U +#define IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_SHIFT 6 +#define IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_MASK 0x00000040U -/*Master Tri-state Enable for pin 7, active high*/ +/* +* Master Tri-state Enable for pin 7, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_SHIFT 7 -#define IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_MASK 0x00000080U +#define IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_SHIFT 7 +#define IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_MASK 0x00000080U -/*Master Tri-state Enable for pin 8, active high*/ +/* +* Master Tri-state Enable for pin 8, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_SHIFT 8 -#define IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_MASK 0x00000100U +#define IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_SHIFT 8 +#define IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_MASK 0x00000100U -/*Master Tri-state Enable for pin 9, active high*/ +/* +* Master Tri-state Enable for pin 9, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_SHIFT 9 -#define IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_MASK 0x00000200U +#define IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_SHIFT 9 +#define IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_MASK 0x00000200U -/*Master Tri-state Enable for pin 10, active high*/ +/* +* Master Tri-state Enable for pin 10, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_SHIFT 10 -#define IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_MASK 0x00000400U +#define IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_SHIFT 10 +#define IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_MASK 0x00000400U -/*Master Tri-state Enable for pin 11, active high*/ +/* +* Master Tri-state Enable for pin 11, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_SHIFT 11 -#define IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_MASK 0x00000800U +#define IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_SHIFT 11 +#define IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_MASK 0x00000800U -/*Master Tri-state Enable for pin 12, active high*/ +/* +* Master Tri-state Enable for pin 12, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_SHIFT 12 -#define IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_MASK 0x00001000U +#define IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_SHIFT 12 +#define IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_MASK 0x00001000U -/*Master Tri-state Enable for pin 13, active high*/ +/* +* Master Tri-state Enable for pin 13, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_SHIFT 13 -#define IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_MASK 0x00002000U +#define IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_SHIFT 13 +#define IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_MASK 0x00002000U -/*Master Tri-state Enable for pin 14, active high*/ +/* +* Master Tri-state Enable for pin 14, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_SHIFT 14 -#define IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_MASK 0x00004000U +#define IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_SHIFT 14 +#define IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_MASK 0x00004000U -/*Master Tri-state Enable for pin 15, active high*/ +/* +* Master Tri-state Enable for pin 15, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_SHIFT 15 -#define IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_MASK 0x00008000U +#define IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_SHIFT 15 +#define IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_MASK 0x00008000U -/*Master Tri-state Enable for pin 16, active high*/ +/* +* Master Tri-state Enable for pin 16, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_SHIFT 16 -#define IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_MASK 0x00010000U +#define IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_SHIFT 16 +#define IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_MASK 0x00010000U -/*Master Tri-state Enable for pin 17, active high*/ +/* +* Master Tri-state Enable for pin 17, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_SHIFT 17 -#define IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_MASK 0x00020000U +#define IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_SHIFT 17 +#define IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_MASK 0x00020000U -/*Master Tri-state Enable for pin 18, active high*/ +/* +* Master Tri-state Enable for pin 18, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_SHIFT 18 -#define IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_MASK 0x00040000U +#define IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_SHIFT 18 +#define IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_MASK 0x00040000U -/*Master Tri-state Enable for pin 19, active high*/ +/* +* Master Tri-state Enable for pin 19, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_SHIFT 19 -#define IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_MASK 0x00080000U +#define IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_SHIFT 19 +#define IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_MASK 0x00080000U -/*Master Tri-state Enable for pin 20, active high*/ +/* +* Master Tri-state Enable for pin 20, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_SHIFT 20 -#define IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_MASK 0x00100000U +#define IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_SHIFT 20 +#define IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_MASK 0x00100000U -/*Master Tri-state Enable for pin 21, active high*/ +/* +* Master Tri-state Enable for pin 21, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_SHIFT 21 -#define IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_MASK 0x00200000U +#define IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_SHIFT 21 +#define IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_MASK 0x00200000U -/*Master Tri-state Enable for pin 22, active high*/ +/* +* Master Tri-state Enable for pin 22, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_SHIFT 22 -#define IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_MASK 0x00400000U +#define IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_SHIFT 22 +#define IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_MASK 0x00400000U -/*Master Tri-state Enable for pin 23, active high*/ +/* +* Master Tri-state Enable for pin 23, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_SHIFT 23 -#define IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_MASK 0x00800000U +#define IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_SHIFT 23 +#define IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_MASK 0x00800000U -/*Master Tri-state Enable for pin 24, active high*/ +/* +* Master Tri-state Enable for pin 24, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_SHIFT 24 -#define IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_MASK 0x01000000U +#define IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_SHIFT 24 +#define IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_MASK 0x01000000U -/*Master Tri-state Enable for pin 25, active high*/ +/* +* Master Tri-state Enable for pin 25, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_SHIFT 25 -#define IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_MASK 0x02000000U +#define IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_SHIFT 25 +#define IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_MASK 0x02000000U -/*Master Tri-state Enable for pin 26, active high*/ +/* +* Master Tri-state Enable for pin 26, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_SHIFT 26 -#define IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_MASK 0x04000000U +#define IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_SHIFT 26 +#define IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_MASK 0x04000000U -/*Master Tri-state Enable for pin 27, active high*/ +/* +* Master Tri-state Enable for pin 27, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_SHIFT 27 -#define IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_MASK 0x08000000U +#define IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_SHIFT 27 +#define IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_MASK 0x08000000U -/*Master Tri-state Enable for pin 28, active high*/ +/* +* Master Tri-state Enable for pin 28, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_SHIFT 28 -#define IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_MASK 0x10000000U +#define IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_SHIFT 28 +#define IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_MASK 0x10000000U -/*Master Tri-state Enable for pin 29, active high*/ +/* +* Master Tri-state Enable for pin 29, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_SHIFT 29 -#define IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_MASK 0x20000000U +#define IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_SHIFT 29 +#define IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_MASK 0x20000000U -/*Master Tri-state Enable for pin 30, active high*/ +/* +* Master Tri-state Enable for pin 30, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_SHIFT 30 -#define IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_MASK 0x40000000U +#define IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_SHIFT 30 +#define IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_MASK 0x40000000U -/*Master Tri-state Enable for pin 31, active high*/ +/* +* Master Tri-state Enable for pin 31, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_SHIFT 31 -#define IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_MASK 0x80000000U +#define IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_SHIFT 31 +#define IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_MASK 0x80000000U -/*Master Tri-state Enable for pin 32, active high*/ +/* +* Master Tri-state Enable for pin 32, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_SHIFT 0 -#define IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_MASK 0x00000001U +#define IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_SHIFT 0 +#define IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_MASK 0x00000001U -/*Master Tri-state Enable for pin 33, active high*/ +/* +* Master Tri-state Enable for pin 33, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_SHIFT 1 -#define IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_MASK 0x00000002U +#define IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_SHIFT 1 +#define IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_MASK 0x00000002U -/*Master Tri-state Enable for pin 34, active high*/ +/* +* Master Tri-state Enable for pin 34, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_SHIFT 2 -#define IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_MASK 0x00000004U +#define IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_SHIFT 2 +#define IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_MASK 0x00000004U -/*Master Tri-state Enable for pin 35, active high*/ +/* +* Master Tri-state Enable for pin 35, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_SHIFT 3 -#define IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_MASK 0x00000008U +#define IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_SHIFT 3 +#define IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_MASK 0x00000008U -/*Master Tri-state Enable for pin 36, active high*/ +/* +* Master Tri-state Enable for pin 36, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_SHIFT 4 -#define IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_MASK 0x00000010U +#define IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_SHIFT 4 +#define IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_MASK 0x00000010U -/*Master Tri-state Enable for pin 37, active high*/ +/* +* Master Tri-state Enable for pin 37, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_SHIFT 5 -#define IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_MASK 0x00000020U +#define IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_SHIFT 5 +#define IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_MASK 0x00000020U -/*Master Tri-state Enable for pin 38, active high*/ +/* +* Master Tri-state Enable for pin 38, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_SHIFT 6 -#define IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_MASK 0x00000040U +#define IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_SHIFT 6 +#define IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_MASK 0x00000040U -/*Master Tri-state Enable for pin 39, active high*/ +/* +* Master Tri-state Enable for pin 39, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_SHIFT 7 -#define IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_MASK 0x00000080U +#define IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_SHIFT 7 +#define IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_MASK 0x00000080U -/*Master Tri-state Enable for pin 40, active high*/ +/* +* Master Tri-state Enable for pin 40, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_SHIFT 8 -#define IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_MASK 0x00000100U +#define IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_SHIFT 8 +#define IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_MASK 0x00000100U -/*Master Tri-state Enable for pin 41, active high*/ +/* +* Master Tri-state Enable for pin 41, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_SHIFT 9 -#define IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_MASK 0x00000200U +#define IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_SHIFT 9 +#define IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_MASK 0x00000200U -/*Master Tri-state Enable for pin 42, active high*/ +/* +* Master Tri-state Enable for pin 42, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_SHIFT 10 -#define IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_MASK 0x00000400U +#define IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_SHIFT 10 +#define IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_MASK 0x00000400U -/*Master Tri-state Enable for pin 43, active high*/ +/* +* Master Tri-state Enable for pin 43, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_SHIFT 11 -#define IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_MASK 0x00000800U +#define IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_SHIFT 11 +#define IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_MASK 0x00000800U -/*Master Tri-state Enable for pin 44, active high*/ +/* +* Master Tri-state Enable for pin 44, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_SHIFT 12 -#define IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_MASK 0x00001000U +#define IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_SHIFT 12 +#define IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_MASK 0x00001000U -/*Master Tri-state Enable for pin 45, active high*/ +/* +* Master Tri-state Enable for pin 45, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_SHIFT 13 -#define IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_MASK 0x00002000U +#define IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_SHIFT 13 +#define IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_MASK 0x00002000U -/*Master Tri-state Enable for pin 46, active high*/ +/* +* Master Tri-state Enable for pin 46, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_SHIFT 14 -#define IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_MASK 0x00004000U +#define IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_SHIFT 14 +#define IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_MASK 0x00004000U -/*Master Tri-state Enable for pin 47, active high*/ +/* +* Master Tri-state Enable for pin 47, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_SHIFT 15 -#define IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_MASK 0x00008000U +#define IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_SHIFT 15 +#define IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_MASK 0x00008000U -/*Master Tri-state Enable for pin 48, active high*/ +/* +* Master Tri-state Enable for pin 48, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_SHIFT 16 -#define IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_MASK 0x00010000U +#define IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_SHIFT 16 +#define IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_MASK 0x00010000U -/*Master Tri-state Enable for pin 49, active high*/ +/* +* Master Tri-state Enable for pin 49, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_SHIFT 17 -#define IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_MASK 0x00020000U +#define IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_SHIFT 17 +#define IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_MASK 0x00020000U -/*Master Tri-state Enable for pin 50, active high*/ +/* +* Master Tri-state Enable for pin 50, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_SHIFT 18 -#define IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_MASK 0x00040000U +#define IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_SHIFT 18 +#define IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_MASK 0x00040000U -/*Master Tri-state Enable for pin 51, active high*/ +/* +* Master Tri-state Enable for pin 51, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_SHIFT 19 -#define IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_MASK 0x00080000U +#define IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_SHIFT 19 +#define IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_MASK 0x00080000U -/*Master Tri-state Enable for pin 52, active high*/ +/* +* Master Tri-state Enable for pin 52, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_SHIFT 20 -#define IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_MASK 0x00100000U +#define IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_SHIFT 20 +#define IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_MASK 0x00100000U -/*Master Tri-state Enable for pin 53, active high*/ +/* +* Master Tri-state Enable for pin 53, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_SHIFT 21 -#define IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_MASK 0x00200000U +#define IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_SHIFT 21 +#define IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_MASK 0x00200000U -/*Master Tri-state Enable for pin 54, active high*/ +/* +* Master Tri-state Enable for pin 54, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_SHIFT 22 -#define IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_MASK 0x00400000U +#define IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_SHIFT 22 +#define IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_MASK 0x00400000U -/*Master Tri-state Enable for pin 55, active high*/ +/* +* Master Tri-state Enable for pin 55, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_SHIFT 23 -#define IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_MASK 0x00800000U +#define IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_SHIFT 23 +#define IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_MASK 0x00800000U -/*Master Tri-state Enable for pin 56, active high*/ +/* +* Master Tri-state Enable for pin 56, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_SHIFT 24 -#define IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_MASK 0x01000000U +#define IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_SHIFT 24 +#define IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_MASK 0x01000000U -/*Master Tri-state Enable for pin 57, active high*/ +/* +* Master Tri-state Enable for pin 57, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_SHIFT 25 -#define IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_MASK 0x02000000U +#define IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_SHIFT 25 +#define IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_MASK 0x02000000U -/*Master Tri-state Enable for pin 58, active high*/ +/* +* Master Tri-state Enable for pin 58, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_SHIFT 26 -#define IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_MASK 0x04000000U +#define IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_SHIFT 26 +#define IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_MASK 0x04000000U -/*Master Tri-state Enable for pin 59, active high*/ +/* +* Master Tri-state Enable for pin 59, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_SHIFT 27 -#define IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_MASK 0x08000000U +#define IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_SHIFT 27 +#define IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_MASK 0x08000000U -/*Master Tri-state Enable for pin 60, active high*/ +/* +* Master Tri-state Enable for pin 60, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_SHIFT 28 -#define IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_MASK 0x10000000U +#define IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_SHIFT 28 +#define IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_MASK 0x10000000U -/*Master Tri-state Enable for pin 61, active high*/ +/* +* Master Tri-state Enable for pin 61, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_SHIFT 29 -#define IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_MASK 0x20000000U +#define IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_SHIFT 29 +#define IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_MASK 0x20000000U -/*Master Tri-state Enable for pin 62, active high*/ +/* +* Master Tri-state Enable for pin 62, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_SHIFT 30 -#define IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_MASK 0x40000000U +#define IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_SHIFT 30 +#define IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_MASK 0x40000000U -/*Master Tri-state Enable for pin 63, active high*/ +/* +* Master Tri-state Enable for pin 63, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_SHIFT 31 -#define IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_MASK 0x80000000U +#define IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_SHIFT 31 +#define IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_MASK 0x80000000U -/*Master Tri-state Enable for pin 64, active high*/ +/* +* Master Tri-state Enable for pin 64, active high +*/ #undef IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_DEFVAL 0x00003FFF -#define IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_SHIFT 0 -#define IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_MASK 0x00000001U +#define IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_DEFVAL 0x00003FFF +#define IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_SHIFT 0 +#define IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_MASK 0x00000001U -/*Master Tri-state Enable for pin 65, active high*/ +/* +* Master Tri-state Enable for pin 65, active high +*/ #undef IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_DEFVAL 0x00003FFF -#define IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_SHIFT 1 -#define IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_MASK 0x00000002U +#define IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_DEFVAL 0x00003FFF +#define IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_SHIFT 1 +#define IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_MASK 0x00000002U -/*Master Tri-state Enable for pin 66, active high*/ +/* +* Master Tri-state Enable for pin 66, active high +*/ #undef IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_DEFVAL 0x00003FFF -#define IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_SHIFT 2 -#define IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_MASK 0x00000004U +#define IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_DEFVAL 0x00003FFF +#define IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_SHIFT 2 +#define IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_MASK 0x00000004U -/*Master Tri-state Enable for pin 67, active high*/ +/* +* Master Tri-state Enable for pin 67, active high +*/ #undef IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_DEFVAL 0x00003FFF -#define IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_SHIFT 3 -#define IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_MASK 0x00000008U +#define IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_DEFVAL 0x00003FFF +#define IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_SHIFT 3 +#define IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_MASK 0x00000008U -/*Master Tri-state Enable for pin 68, active high*/ +/* +* Master Tri-state Enable for pin 68, active high +*/ #undef IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_DEFVAL 0x00003FFF -#define IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_SHIFT 4 -#define IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_MASK 0x00000010U +#define IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_DEFVAL 0x00003FFF +#define IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_SHIFT 4 +#define IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_MASK 0x00000010U -/*Master Tri-state Enable for pin 69, active high*/ +/* +* Master Tri-state Enable for pin 69, active high +*/ #undef IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_DEFVAL 0x00003FFF -#define IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_SHIFT 5 -#define IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_MASK 0x00000020U +#define IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_DEFVAL 0x00003FFF +#define IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_SHIFT 5 +#define IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_MASK 0x00000020U -/*Master Tri-state Enable for pin 70, active high*/ +/* +* Master Tri-state Enable for pin 70, active high +*/ #undef IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_DEFVAL 0x00003FFF -#define IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_SHIFT 6 -#define IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_MASK 0x00000040U +#define IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_DEFVAL 0x00003FFF +#define IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_SHIFT 6 +#define IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_MASK 0x00000040U -/*Master Tri-state Enable for pin 71, active high*/ +/* +* Master Tri-state Enable for pin 71, active high +*/ #undef IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_DEFVAL 0x00003FFF -#define IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_SHIFT 7 -#define IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_MASK 0x00000080U +#define IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_DEFVAL 0x00003FFF +#define IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_SHIFT 7 +#define IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_MASK 0x00000080U -/*Master Tri-state Enable for pin 72, active high*/ +/* +* Master Tri-state Enable for pin 72, active high +*/ #undef IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_DEFVAL 0x00003FFF -#define IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_SHIFT 8 -#define IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_MASK 0x00000100U +#define IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_DEFVAL 0x00003FFF +#define IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_SHIFT 8 +#define IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_MASK 0x00000100U -/*Master Tri-state Enable for pin 73, active high*/ +/* +* Master Tri-state Enable for pin 73, active high +*/ #undef IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_DEFVAL 0x00003FFF -#define IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_SHIFT 9 -#define IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_MASK 0x00000200U +#define IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_DEFVAL 0x00003FFF +#define IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_SHIFT 9 +#define IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_MASK 0x00000200U -/*Master Tri-state Enable for pin 74, active high*/ +/* +* Master Tri-state Enable for pin 74, active high +*/ #undef IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_DEFVAL 0x00003FFF -#define IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_SHIFT 10 -#define IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_MASK 0x00000400U +#define IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_DEFVAL 0x00003FFF +#define IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_SHIFT 10 +#define IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_MASK 0x00000400U -/*Master Tri-state Enable for pin 75, active high*/ +/* +* Master Tri-state Enable for pin 75, active high +*/ #undef IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_DEFVAL 0x00003FFF -#define IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_SHIFT 11 -#define IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_MASK 0x00000800U +#define IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_DEFVAL 0x00003FFF +#define IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_SHIFT 11 +#define IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_MASK 0x00000800U -/*Master Tri-state Enable for pin 76, active high*/ +/* +* Master Tri-state Enable for pin 76, active high +*/ #undef IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_DEFVAL 0x00003FFF -#define IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_SHIFT 12 -#define IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_MASK 0x00001000U +#define IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_DEFVAL 0x00003FFF +#define IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_SHIFT 12 +#define IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_MASK 0x00001000U -/*Master Tri-state Enable for pin 77, active high*/ +/* +* Master Tri-state Enable for pin 77, active high +*/ #undef IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_DEFVAL 0x00003FFF -#define IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_SHIFT 13 -#define IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_MASK 0x00002000U +#define IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_DEFVAL 0x00003FFF +#define IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_SHIFT 13 +#define IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_MASK 0x00002000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_SHIFT 0 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_MASK 0x00000001U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_MASK 0x00000001U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_SHIFT 1 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_MASK 0x00000002U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_MASK 0x00000002U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_SHIFT 2 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_MASK 0x00000004U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_MASK 0x00000004U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_SHIFT 3 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_MASK 0x00000008U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_MASK 0x00000008U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_SHIFT 4 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_MASK 0x00000010U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_MASK 0x00000010U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_SHIFT 5 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_MASK 0x00000020U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_MASK 0x00000020U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_SHIFT 6 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_MASK 0x00000040U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_MASK 0x00000040U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_SHIFT 7 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_MASK 0x00000080U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_MASK 0x00000080U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_SHIFT 8 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_MASK 0x00000100U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_MASK 0x00000100U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_SHIFT 9 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_MASK 0x00000200U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_MASK 0x00000200U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_SHIFT 10 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_MASK 0x00000400U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_MASK 0x00000400U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_SHIFT 11 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_MASK 0x00000800U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_MASK 0x00000800U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_SHIFT 12 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_MASK 0x00001000U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_MASK 0x00001000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_SHIFT 13 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_MASK 0x00002000U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_MASK 0x00002000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_SHIFT 14 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_MASK 0x00004000U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_MASK 0x00004000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_SHIFT 15 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_MASK 0x00008000U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_MASK 0x00008000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_SHIFT 16 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_MASK 0x00010000U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_MASK 0x00010000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_SHIFT 17 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_MASK 0x00020000U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_MASK 0x00020000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_SHIFT 18 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_MASK 0x00040000U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_MASK 0x00040000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_SHIFT 19 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_MASK 0x00080000U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_MASK 0x00080000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_SHIFT 20 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_MASK 0x00100000U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_MASK 0x00100000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_SHIFT 21 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_MASK 0x00200000U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_MASK 0x00200000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_SHIFT 22 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_MASK 0x00400000U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_MASK 0x00400000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_SHIFT 23 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_MASK 0x00800000U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_MASK 0x00800000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_SHIFT 24 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_MASK 0x01000000U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_MASK 0x01000000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_SHIFT 25 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_MASK 0x02000000U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_MASK 0x02000000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_SHIFT 0 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_MASK 0x00000001U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_MASK 0x00000001U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_SHIFT 1 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_MASK 0x00000002U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_MASK 0x00000002U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_SHIFT 2 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_MASK 0x00000004U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_MASK 0x00000004U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_SHIFT 3 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_MASK 0x00000008U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_MASK 0x00000008U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_SHIFT 4 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_MASK 0x00000010U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_MASK 0x00000010U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_SHIFT 5 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_MASK 0x00000020U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_MASK 0x00000020U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_SHIFT 6 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_MASK 0x00000040U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_MASK 0x00000040U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_SHIFT 7 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_MASK 0x00000080U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_MASK 0x00000080U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_SHIFT 8 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_MASK 0x00000100U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_MASK 0x00000100U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_SHIFT 9 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_MASK 0x00000200U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_MASK 0x00000200U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_SHIFT 10 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_MASK 0x00000400U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_MASK 0x00000400U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_SHIFT 11 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_MASK 0x00000800U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_MASK 0x00000800U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_SHIFT 12 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_MASK 0x00001000U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_MASK 0x00001000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_SHIFT 13 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_MASK 0x00002000U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_MASK 0x00002000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_SHIFT 14 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_MASK 0x00004000U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_MASK 0x00004000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_SHIFT 15 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_MASK 0x00008000U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_MASK 0x00008000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_SHIFT 16 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_MASK 0x00010000U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_MASK 0x00010000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_SHIFT 17 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_MASK 0x00020000U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_MASK 0x00020000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_SHIFT 18 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_MASK 0x00040000U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_MASK 0x00040000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_SHIFT 19 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_MASK 0x00080000U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_MASK 0x00080000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_SHIFT 20 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_MASK 0x00100000U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_MASK 0x00100000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_SHIFT 21 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_MASK 0x00200000U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_MASK 0x00200000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_SHIFT 22 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_MASK 0x00400000U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_MASK 0x00400000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_SHIFT 23 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_MASK 0x00800000U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_MASK 0x00800000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_SHIFT 24 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_MASK 0x01000000U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_MASK 0x01000000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_SHIFT 25 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_MASK 0x02000000U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_MASK 0x02000000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT 0 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK 0x00000001U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK 0x00000001U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT 1 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK 0x00000002U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK 0x00000002U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT 2 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK 0x00000004U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK 0x00000004U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT 3 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK 0x00000008U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK 0x00000008U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT 4 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK 0x00000010U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK 0x00000010U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT 5 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK 0x00000020U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK 0x00000020U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT 6 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK 0x00000040U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK 0x00000040U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT 7 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK 0x00000080U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK 0x00000080U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT 8 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK 0x00000100U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK 0x00000100U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT 9 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK 0x00000200U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK 0x00000200U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT 10 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK 0x00000400U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK 0x00000400U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT 11 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK 0x00000800U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK 0x00000800U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT 12 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK 0x00001000U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK 0x00001000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT 13 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK 0x00002000U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK 0x00002000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT 14 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK 0x00004000U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK 0x00004000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT 15 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK 0x00008000U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK 0x00008000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT 16 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK 0x00010000U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK 0x00010000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT 17 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK 0x00020000U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK 0x00020000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT 18 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK 0x00040000U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK 0x00040000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT 19 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK 0x00080000U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK 0x00080000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT 20 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK 0x00100000U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK 0x00100000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT 21 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK 0x00200000U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK 0x00200000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT 22 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK 0x00400000U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK 0x00400000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT 23 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK 0x00800000U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK 0x00800000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT 24 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK 0x01000000U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK 0x01000000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT 25 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK 0x02000000U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK 0x02000000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT 0 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK 0x00000001U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK 0x00000001U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT 1 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK 0x00000002U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK 0x00000002U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT 2 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK 0x00000004U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK 0x00000004U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT 3 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK 0x00000008U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK 0x00000008U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT 4 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK 0x00000010U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK 0x00000010U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT 5 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK 0x00000020U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK 0x00000020U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT 6 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK 0x00000040U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK 0x00000040U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT 7 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK 0x00000080U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK 0x00000080U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT 8 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK 0x00000100U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK 0x00000100U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT 9 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK 0x00000200U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK 0x00000200U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT 10 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK 0x00000400U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK 0x00000400U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT 11 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK 0x00000800U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK 0x00000800U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT 12 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK 0x00001000U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK 0x00001000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT 13 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK 0x00002000U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK 0x00002000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT 14 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK 0x00004000U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK 0x00004000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT 15 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK 0x00008000U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK 0x00008000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT 16 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK 0x00010000U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK 0x00010000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT 17 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK 0x00020000U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK 0x00020000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT 18 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK 0x00040000U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK 0x00040000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT 19 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK 0x00080000U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK 0x00080000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT 20 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK 0x00100000U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK 0x00100000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT 21 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK 0x00200000U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK 0x00200000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT 22 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK 0x00400000U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK 0x00400000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT 23 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK 0x00800000U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK 0x00800000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT 24 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK 0x01000000U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK 0x01000000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT 25 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK 0x02000000U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK 0x02000000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_SHIFT 0 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_MASK 0x00000001U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_MASK 0x00000001U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_SHIFT 1 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_MASK 0x00000002U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_MASK 0x00000002U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_SHIFT 2 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_MASK 0x00000004U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_MASK 0x00000004U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_SHIFT 3 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_MASK 0x00000008U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_MASK 0x00000008U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_SHIFT 4 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_MASK 0x00000010U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_MASK 0x00000010U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_SHIFT 5 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_MASK 0x00000020U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_MASK 0x00000020U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_SHIFT 6 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_MASK 0x00000040U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_MASK 0x00000040U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_SHIFT 7 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_MASK 0x00000080U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_MASK 0x00000080U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_SHIFT 8 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_MASK 0x00000100U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_MASK 0x00000100U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_SHIFT 9 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_MASK 0x00000200U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_MASK 0x00000200U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_SHIFT 10 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_MASK 0x00000400U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_MASK 0x00000400U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_SHIFT 11 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_MASK 0x00000800U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_MASK 0x00000800U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_SHIFT 12 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_MASK 0x00001000U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_MASK 0x00001000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_SHIFT 13 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_MASK 0x00002000U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_MASK 0x00002000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_SHIFT 14 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_MASK 0x00004000U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_MASK 0x00004000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_SHIFT 15 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_MASK 0x00008000U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_MASK 0x00008000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_SHIFT 16 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_MASK 0x00010000U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_MASK 0x00010000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_SHIFT 17 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_MASK 0x00020000U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_MASK 0x00020000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_SHIFT 18 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_MASK 0x00040000U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_MASK 0x00040000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_SHIFT 19 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_MASK 0x00080000U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_MASK 0x00080000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_SHIFT 20 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_MASK 0x00100000U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_MASK 0x00100000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_SHIFT 21 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_MASK 0x00200000U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_MASK 0x00200000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_SHIFT 22 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_MASK 0x00400000U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_MASK 0x00400000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_SHIFT 23 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_MASK 0x00800000U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_MASK 0x00800000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_SHIFT 24 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_MASK 0x01000000U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_MASK 0x01000000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_SHIFT 25 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_MASK 0x02000000U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_MASK 0x02000000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT 0 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK 0x00000001U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK 0x00000001U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT 1 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK 0x00000002U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK 0x00000002U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT 2 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK 0x00000004U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK 0x00000004U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT 3 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK 0x00000008U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK 0x00000008U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT 4 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK 0x00000010U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK 0x00000010U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT 5 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK 0x00000020U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK 0x00000020U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT 6 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK 0x00000040U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK 0x00000040U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT 7 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK 0x00000080U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK 0x00000080U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT 8 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK 0x00000100U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK 0x00000100U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT 9 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK 0x00000200U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK 0x00000200U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT 10 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK 0x00000400U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK 0x00000400U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT 11 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK 0x00000800U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK 0x00000800U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT 12 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK 0x00001000U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK 0x00001000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT 13 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK 0x00002000U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK 0x00002000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT 14 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK 0x00004000U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK 0x00004000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT 15 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK 0x00008000U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK 0x00008000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT 16 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK 0x00010000U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK 0x00010000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT 17 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK 0x00020000U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK 0x00020000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT 18 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK 0x00040000U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK 0x00040000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT 19 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK 0x00080000U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK 0x00080000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT 20 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK 0x00100000U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK 0x00100000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT 21 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK 0x00200000U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK 0x00200000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT 22 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK 0x00400000U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK 0x00400000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT 23 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK 0x00800000U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK 0x00800000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT 24 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK 0x01000000U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK 0x01000000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT 25 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK 0x02000000U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK 0x02000000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_SHIFT 0 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_MASK 0x00000001U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_MASK 0x00000001U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_SHIFT 1 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_MASK 0x00000002U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_MASK 0x00000002U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_SHIFT 2 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_MASK 0x00000004U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_MASK 0x00000004U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_SHIFT 3 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_MASK 0x00000008U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_MASK 0x00000008U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_SHIFT 4 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_MASK 0x00000010U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_MASK 0x00000010U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_SHIFT 5 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_MASK 0x00000020U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_MASK 0x00000020U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_SHIFT 6 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_MASK 0x00000040U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_MASK 0x00000040U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_SHIFT 7 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_MASK 0x00000080U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_MASK 0x00000080U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_SHIFT 8 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_MASK 0x00000100U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_MASK 0x00000100U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_SHIFT 9 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_MASK 0x00000200U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_MASK 0x00000200U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_SHIFT 10 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_MASK 0x00000400U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_MASK 0x00000400U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_SHIFT 11 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_MASK 0x00000800U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_MASK 0x00000800U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_SHIFT 12 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_MASK 0x00001000U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_MASK 0x00001000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_SHIFT 13 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_MASK 0x00002000U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_MASK 0x00002000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_SHIFT 14 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_MASK 0x00004000U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_MASK 0x00004000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_SHIFT 15 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_MASK 0x00008000U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_MASK 0x00008000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_SHIFT 16 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_MASK 0x00010000U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_MASK 0x00010000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_SHIFT 17 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_MASK 0x00020000U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_MASK 0x00020000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_SHIFT 18 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_MASK 0x00040000U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_MASK 0x00040000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_SHIFT 19 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_MASK 0x00080000U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_MASK 0x00080000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_SHIFT 20 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_MASK 0x00100000U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_MASK 0x00100000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_SHIFT 21 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_MASK 0x00200000U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_MASK 0x00200000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_SHIFT 22 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_MASK 0x00400000U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_MASK 0x00400000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_SHIFT 23 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_MASK 0x00800000U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_MASK 0x00800000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_SHIFT 24 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_MASK 0x01000000U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_MASK 0x01000000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_SHIFT 25 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_MASK 0x02000000U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_MASK 0x02000000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_SHIFT 0 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_MASK 0x00000001U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_MASK 0x00000001U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_SHIFT 1 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_MASK 0x00000002U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_MASK 0x00000002U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_SHIFT 2 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_MASK 0x00000004U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_MASK 0x00000004U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_SHIFT 3 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_MASK 0x00000008U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_MASK 0x00000008U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_SHIFT 4 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_MASK 0x00000010U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_MASK 0x00000010U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_SHIFT 5 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_MASK 0x00000020U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_MASK 0x00000020U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_SHIFT 6 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_MASK 0x00000040U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_MASK 0x00000040U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_SHIFT 7 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_MASK 0x00000080U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_MASK 0x00000080U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_SHIFT 8 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_MASK 0x00000100U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_MASK 0x00000100U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_SHIFT 9 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_MASK 0x00000200U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_MASK 0x00000200U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_SHIFT 10 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_MASK 0x00000400U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_MASK 0x00000400U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_SHIFT 11 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_MASK 0x00000800U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_MASK 0x00000800U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_SHIFT 12 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_MASK 0x00001000U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_MASK 0x00001000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_SHIFT 13 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_MASK 0x00002000U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_MASK 0x00002000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_SHIFT 14 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_MASK 0x00004000U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_MASK 0x00004000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_SHIFT 15 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_MASK 0x00008000U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_MASK 0x00008000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_SHIFT 16 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_MASK 0x00010000U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_MASK 0x00010000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_SHIFT 17 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_MASK 0x00020000U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_MASK 0x00020000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_SHIFT 18 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_MASK 0x00040000U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_MASK 0x00040000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_SHIFT 19 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_MASK 0x00080000U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_MASK 0x00080000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_SHIFT 20 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_MASK 0x00100000U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_MASK 0x00100000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_SHIFT 21 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_MASK 0x00200000U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_MASK 0x00200000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_SHIFT 22 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_MASK 0x00400000U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_MASK 0x00400000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_SHIFT 23 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_MASK 0x00800000U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_MASK 0x00800000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_SHIFT 24 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_MASK 0x01000000U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_MASK 0x01000000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_SHIFT 25 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_MASK 0x02000000U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_MASK 0x02000000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT 0 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK 0x00000001U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK 0x00000001U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT 1 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK 0x00000002U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK 0x00000002U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT 2 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK 0x00000004U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK 0x00000004U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT 3 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK 0x00000008U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK 0x00000008U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT 4 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK 0x00000010U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK 0x00000010U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT 5 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK 0x00000020U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK 0x00000020U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT 6 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK 0x00000040U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK 0x00000040U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT 7 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK 0x00000080U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK 0x00000080U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT 8 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK 0x00000100U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK 0x00000100U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT 9 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK 0x00000200U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK 0x00000200U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT 10 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK 0x00000400U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK 0x00000400U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT 11 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK 0x00000800U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK 0x00000800U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT 12 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK 0x00001000U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK 0x00001000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT 13 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK 0x00002000U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK 0x00002000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT 14 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK 0x00004000U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK 0x00004000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT 15 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK 0x00008000U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK 0x00008000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT 16 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK 0x00010000U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK 0x00010000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT 17 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK 0x00020000U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK 0x00020000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT 18 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK 0x00040000U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK 0x00040000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT 19 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK 0x00080000U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK 0x00080000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT 20 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK 0x00100000U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK 0x00100000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT 21 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK 0x00200000U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK 0x00200000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT 22 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK 0x00400000U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK 0x00400000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT 23 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK 0x00800000U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK 0x00800000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT 24 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK 0x01000000U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK 0x01000000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT 25 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK 0x02000000U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK 0x02000000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT 0 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK 0x00000001U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK 0x00000001U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT 1 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK 0x00000002U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK 0x00000002U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT 2 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK 0x00000004U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK 0x00000004U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT 3 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK 0x00000008U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK 0x00000008U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT 4 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK 0x00000010U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK 0x00000010U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT 5 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK 0x00000020U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK 0x00000020U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT 6 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK 0x00000040U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK 0x00000040U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT 7 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK 0x00000080U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK 0x00000080U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT 8 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK 0x00000100U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK 0x00000100U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT 9 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK 0x00000200U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK 0x00000200U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT 10 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK 0x00000400U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK 0x00000400U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT 11 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK 0x00000800U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK 0x00000800U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT 12 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK 0x00001000U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK 0x00001000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT 13 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK 0x00002000U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK 0x00002000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT 14 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK 0x00004000U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK 0x00004000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT 15 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK 0x00008000U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK 0x00008000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT 16 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK 0x00010000U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK 0x00010000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT 17 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK 0x00020000U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK 0x00020000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT 18 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK 0x00040000U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK 0x00040000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT 19 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK 0x00080000U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK 0x00080000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT 20 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK 0x00100000U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK 0x00100000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT 21 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK 0x00200000U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK 0x00200000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT 22 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK 0x00400000U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK 0x00400000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT 23 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK 0x00800000U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK 0x00800000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT 24 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK 0x01000000U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK 0x01000000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT 25 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK 0x02000000U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK 0x02000000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_SHIFT 12 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_MASK 0x00001000U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_SHIFT 12 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_MASK 0x00001000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_SHIFT 13 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_MASK 0x00002000U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_SHIFT 13 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_MASK 0x00002000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_SHIFT 14 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_MASK 0x00004000U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_SHIFT 14 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_MASK 0x00004000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_SHIFT 15 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_MASK 0x00008000U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_SHIFT 15 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_MASK 0x00008000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_SHIFT 16 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_MASK 0x00010000U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_SHIFT 16 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_MASK 0x00010000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_SHIFT 17 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_MASK 0x00020000U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_SHIFT 17 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_MASK 0x00020000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_SHIFT 18 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_MASK 0x00040000U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_SHIFT 18 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_MASK 0x00040000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_SHIFT 19 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_MASK 0x00080000U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_SHIFT 19 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_MASK 0x00080000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_SHIFT 20 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_MASK 0x00100000U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_SHIFT 20 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_MASK 0x00100000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_SHIFT 21 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_MASK 0x00200000U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_SHIFT 21 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_MASK 0x00200000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_SHIFT 22 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_MASK 0x00400000U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_SHIFT 22 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_MASK 0x00400000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_SHIFT 23 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_MASK 0x00800000U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_SHIFT 23 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_MASK 0x00800000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_SHIFT 24 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_MASK 0x01000000U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_SHIFT 24 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_MASK 0x01000000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_SHIFT 25 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_MASK 0x02000000U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_SHIFT 25 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_MASK 0x02000000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_SHIFT 0 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_MASK 0x00000001U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_SHIFT 0 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_MASK 0x00000001U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_SHIFT 1 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_MASK 0x00000002U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_SHIFT 1 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_MASK 0x00000002U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_SHIFT 2 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_MASK 0x00000004U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_SHIFT 2 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_MASK 0x00000004U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_SHIFT 3 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_MASK 0x00000008U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_SHIFT 3 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_MASK 0x00000008U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_SHIFT 4 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_MASK 0x00000010U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_SHIFT 4 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_MASK 0x00000010U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_SHIFT 5 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_MASK 0x00000020U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_SHIFT 5 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_MASK 0x00000020U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_SHIFT 6 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_MASK 0x00000040U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_SHIFT 6 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_MASK 0x00000040U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_SHIFT 7 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_MASK 0x00000080U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_SHIFT 7 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_MASK 0x00000080U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_SHIFT 8 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_MASK 0x00000100U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_SHIFT 8 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_MASK 0x00000100U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_SHIFT 9 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_MASK 0x00000200U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_SHIFT 9 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_MASK 0x00000200U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_SHIFT 10 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_MASK 0x00000400U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_SHIFT 10 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_MASK 0x00000400U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_SHIFT 11 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_MASK 0x00000800U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_SHIFT 11 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_MASK 0x00000800U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT 0 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK 0x00000001U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK 0x00000001U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT 1 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK 0x00000002U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK 0x00000002U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT 2 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK 0x00000004U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK 0x00000004U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT 3 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK 0x00000008U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK 0x00000008U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT 4 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK 0x00000010U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK 0x00000010U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT 5 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK 0x00000020U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK 0x00000020U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT 6 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK 0x00000040U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK 0x00000040U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT 7 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK 0x00000080U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK 0x00000080U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT 8 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK 0x00000100U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK 0x00000100U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT 9 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK 0x00000200U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK 0x00000200U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT 10 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK 0x00000400U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK 0x00000400U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT 11 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK 0x00000800U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK 0x00000800U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT 12 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK 0x00001000U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK 0x00001000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT 13 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK 0x00002000U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK 0x00002000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT 14 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK 0x00004000U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK 0x00004000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT 15 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK 0x00008000U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK 0x00008000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT 16 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK 0x00010000U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK 0x00010000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT 17 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK 0x00020000U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK 0x00020000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT 18 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK 0x00040000U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK 0x00040000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT 19 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK 0x00080000U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK 0x00080000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT 20 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK 0x00100000U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK 0x00100000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT 21 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK 0x00200000U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK 0x00200000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT 22 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK 0x00400000U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK 0x00400000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT 23 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK 0x00800000U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK 0x00800000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT 24 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK 0x01000000U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK 0x01000000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT 25 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK 0x02000000U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK 0x02000000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_SHIFT 0 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_MASK 0x00000001U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_MASK 0x00000001U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_SHIFT 1 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_MASK 0x00000002U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_MASK 0x00000002U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_SHIFT 2 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_MASK 0x00000004U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_MASK 0x00000004U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_SHIFT 3 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_MASK 0x00000008U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_MASK 0x00000008U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_SHIFT 4 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_MASK 0x00000010U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_MASK 0x00000010U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_SHIFT 5 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_MASK 0x00000020U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_MASK 0x00000020U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_SHIFT 6 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_MASK 0x00000040U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_MASK 0x00000040U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_SHIFT 7 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_MASK 0x00000080U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_MASK 0x00000080U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_SHIFT 8 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_MASK 0x00000100U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_MASK 0x00000100U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_SHIFT 9 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_MASK 0x00000200U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_MASK 0x00000200U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_SHIFT 10 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_MASK 0x00000400U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_MASK 0x00000400U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_SHIFT 11 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_MASK 0x00000800U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_MASK 0x00000800U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_SHIFT 12 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_MASK 0x00001000U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_MASK 0x00001000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_SHIFT 13 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_MASK 0x00002000U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_MASK 0x00002000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_SHIFT 14 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_MASK 0x00004000U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_MASK 0x00004000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_SHIFT 15 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_MASK 0x00008000U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_MASK 0x00008000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_SHIFT 16 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_MASK 0x00010000U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_MASK 0x00010000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_SHIFT 17 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_MASK 0x00020000U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_MASK 0x00020000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_SHIFT 18 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_MASK 0x00040000U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_MASK 0x00040000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_SHIFT 19 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_MASK 0x00080000U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_MASK 0x00080000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_SHIFT 20 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_MASK 0x00100000U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_MASK 0x00100000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_SHIFT 21 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_MASK 0x00200000U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_MASK 0x00200000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_SHIFT 22 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_MASK 0x00400000U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_MASK 0x00400000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_SHIFT 23 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_MASK 0x00800000U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_MASK 0x00800000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_SHIFT 24 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_MASK 0x01000000U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_MASK 0x01000000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_SHIFT 25 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_MASK 0x02000000U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_MASK 0x02000000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_SHIFT 0 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_MASK 0x00000001U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_MASK 0x00000001U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_SHIFT 1 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_MASK 0x00000002U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_MASK 0x00000002U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_SHIFT 2 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_MASK 0x00000004U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_MASK 0x00000004U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_SHIFT 3 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_MASK 0x00000008U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_MASK 0x00000008U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_SHIFT 4 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_MASK 0x00000010U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_MASK 0x00000010U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_SHIFT 5 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_MASK 0x00000020U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_MASK 0x00000020U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_SHIFT 6 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_MASK 0x00000040U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_MASK 0x00000040U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_SHIFT 7 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_MASK 0x00000080U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_MASK 0x00000080U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_SHIFT 8 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_MASK 0x00000100U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_MASK 0x00000100U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_SHIFT 9 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_MASK 0x00000200U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_MASK 0x00000200U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_SHIFT 10 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_MASK 0x00000400U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_MASK 0x00000400U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_SHIFT 11 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_MASK 0x00000800U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_MASK 0x00000800U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_SHIFT 12 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_MASK 0x00001000U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_MASK 0x00001000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_SHIFT 13 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_MASK 0x00002000U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_MASK 0x00002000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_SHIFT 14 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_MASK 0x00004000U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_MASK 0x00004000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_SHIFT 15 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_MASK 0x00008000U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_MASK 0x00008000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_SHIFT 16 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_MASK 0x00010000U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_MASK 0x00010000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_SHIFT 17 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_MASK 0x00020000U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_MASK 0x00020000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_SHIFT 18 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_MASK 0x00040000U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_MASK 0x00040000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_SHIFT 19 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_MASK 0x00080000U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_MASK 0x00080000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_SHIFT 20 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_MASK 0x00100000U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_MASK 0x00100000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_SHIFT 21 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_MASK 0x00200000U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_MASK 0x00200000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_SHIFT 22 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_MASK 0x00400000U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_MASK 0x00400000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_SHIFT 23 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_MASK 0x00800000U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_MASK 0x00800000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_SHIFT 24 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_MASK 0x01000000U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_MASK 0x01000000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_SHIFT 25 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_MASK 0x02000000U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_MASK 0x02000000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT 0 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK 0x00000001U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK 0x00000001U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT 1 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK 0x00000002U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK 0x00000002U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT 2 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK 0x00000004U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK 0x00000004U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT 3 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK 0x00000008U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK 0x00000008U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT 4 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK 0x00000010U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK 0x00000010U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT 5 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK 0x00000020U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK 0x00000020U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT 6 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK 0x00000040U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK 0x00000040U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT 7 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK 0x00000080U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK 0x00000080U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT 8 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK 0x00000100U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK 0x00000100U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT 9 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK 0x00000200U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK 0x00000200U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT 10 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK 0x00000400U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK 0x00000400U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT 11 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK 0x00000800U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK 0x00000800U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT 12 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK 0x00001000U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK 0x00001000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT 13 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK 0x00002000U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK 0x00002000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT 14 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK 0x00004000U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK 0x00004000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT 15 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK 0x00008000U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK 0x00008000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT 16 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK 0x00010000U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK 0x00010000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT 17 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK 0x00020000U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK 0x00020000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT 18 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK 0x00040000U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK 0x00040000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT 19 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK 0x00080000U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK 0x00080000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT 20 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK 0x00100000U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK 0x00100000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT 21 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK 0x00200000U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK 0x00200000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT 22 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK 0x00400000U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK 0x00400000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT 23 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK 0x00800000U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK 0x00800000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT 24 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK 0x01000000U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK 0x01000000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT 25 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK 0x02000000U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK 0x02000000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT 0 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK 0x00000001U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK 0x00000001U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT 1 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK 0x00000002U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK 0x00000002U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT 2 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK 0x00000004U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK 0x00000004U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT 3 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK 0x00000008U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK 0x00000008U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT 4 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK 0x00000010U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK 0x00000010U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT 5 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK 0x00000020U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK 0x00000020U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT 6 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK 0x00000040U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK 0x00000040U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT 7 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK 0x00000080U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK 0x00000080U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT 8 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK 0x00000100U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK 0x00000100U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT 9 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK 0x00000200U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK 0x00000200U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT 10 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK 0x00000400U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK 0x00000400U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT 11 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK 0x00000800U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK 0x00000800U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT 12 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK 0x00001000U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK 0x00001000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT 13 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK 0x00002000U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK 0x00002000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT 14 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK 0x00004000U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK 0x00004000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT 15 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK 0x00008000U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK 0x00008000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT 16 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK 0x00010000U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK 0x00010000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT 17 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK 0x00020000U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK 0x00020000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT 18 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK 0x00040000U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK 0x00040000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT 19 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK 0x00080000U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK 0x00080000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT 20 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK 0x00100000U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK 0x00100000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT 21 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK 0x00200000U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK 0x00200000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT 22 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK 0x00400000U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK 0x00400000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT 23 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK 0x00800000U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK 0x00800000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT 24 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK 0x01000000U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK 0x01000000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT 25 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK 0x02000000U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK 0x02000000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_SHIFT 0 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_MASK 0x00000001U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_MASK 0x00000001U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_SHIFT 1 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_MASK 0x00000002U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_MASK 0x00000002U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_SHIFT 2 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_MASK 0x00000004U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_MASK 0x00000004U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_SHIFT 3 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_MASK 0x00000008U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_MASK 0x00000008U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_SHIFT 4 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_MASK 0x00000010U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_MASK 0x00000010U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_SHIFT 5 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_MASK 0x00000020U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_MASK 0x00000020U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_SHIFT 6 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_MASK 0x00000040U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_MASK 0x00000040U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_SHIFT 7 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_MASK 0x00000080U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_MASK 0x00000080U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_SHIFT 8 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_MASK 0x00000100U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_MASK 0x00000100U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_SHIFT 9 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_MASK 0x00000200U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_MASK 0x00000200U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_SHIFT 10 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_MASK 0x00000400U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_MASK 0x00000400U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_SHIFT 11 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_MASK 0x00000800U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_MASK 0x00000800U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_SHIFT 12 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_MASK 0x00001000U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_MASK 0x00001000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_SHIFT 13 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_MASK 0x00002000U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_MASK 0x00002000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_SHIFT 14 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_MASK 0x00004000U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_MASK 0x00004000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_SHIFT 15 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_MASK 0x00008000U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_MASK 0x00008000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_SHIFT 16 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_MASK 0x00010000U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_MASK 0x00010000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_SHIFT 17 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_MASK 0x00020000U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_MASK 0x00020000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_SHIFT 18 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_MASK 0x00040000U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_MASK 0x00040000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_SHIFT 19 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_MASK 0x00080000U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_MASK 0x00080000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_SHIFT 20 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_MASK 0x00100000U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_MASK 0x00100000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_SHIFT 21 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_MASK 0x00200000U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_MASK 0x00200000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_SHIFT 22 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_MASK 0x00400000U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_MASK 0x00400000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_SHIFT 23 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_MASK 0x00800000U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_MASK 0x00800000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_SHIFT 24 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_MASK 0x01000000U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_MASK 0x01000000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_SHIFT 25 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_MASK 0x02000000U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_MASK 0x02000000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT 0 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK 0x00000001U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK 0x00000001U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT 1 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK 0x00000002U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK 0x00000002U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT 2 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK 0x00000004U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK 0x00000004U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT 3 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK 0x00000008U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK 0x00000008U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT 4 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK 0x00000010U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK 0x00000010U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT 5 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK 0x00000020U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK 0x00000020U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT 6 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK 0x00000040U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK 0x00000040U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT 7 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK 0x00000080U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK 0x00000080U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT 8 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK 0x00000100U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK 0x00000100U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT 9 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK 0x00000200U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK 0x00000200U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT 10 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK 0x00000400U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK 0x00000400U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT 11 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK 0x00000800U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK 0x00000800U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT 12 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK 0x00001000U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK 0x00001000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT 13 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK 0x00002000U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK 0x00002000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT 14 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK 0x00004000U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK 0x00004000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT 15 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK 0x00008000U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK 0x00008000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT 16 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK 0x00010000U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK 0x00010000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT 17 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK 0x00020000U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK 0x00020000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT 18 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK 0x00040000U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK 0x00040000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT 19 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK 0x00080000U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK 0x00080000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT 20 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK 0x00100000U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK 0x00100000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT 21 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK 0x00200000U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK 0x00200000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT 22 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK 0x00400000U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK 0x00400000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT 23 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK 0x00800000U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK 0x00800000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT 24 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK 0x01000000U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK 0x01000000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT 25 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK 0x02000000U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK 0x02000000U -/*I2C Loopback Control. 0 = Connect I2C inputs according to MIO mapping. 1 = Loop I2C 0 outputs to I2C 1 inputs, and I2C 1 outp - ts to I2C 0 inputs.*/ +/* +* I2C Loopback Control. 0 = Connect I2C inputs according to MIO mapping. 1 + * = Loop I2C 0 outputs to I2C 1 inputs, and I2C 1 outputs to I2C 0 inputs + * . +*/ #undef IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_DEFVAL #undef IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_SHIFT #undef IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_MASK -#define IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_SHIFT 3 -#define IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_MASK 0x00000008U +#define IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_SHIFT 3 +#define IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_MASK 0x00000008U -/*CAN Loopback Control. 0 = Connect CAN inputs according to MIO mapping. 1 = Loop CAN 0 Tx to CAN 1 Rx, and CAN 1 Tx to CAN 0 R - .*/ +/* +* CAN Loopback Control. 0 = Connect CAN inputs according to MIO mapping. 1 + * = Loop CAN 0 Tx to CAN 1 Rx, and CAN 1 Tx to CAN 0 Rx. +*/ #undef IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_DEFVAL #undef IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_SHIFT #undef IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_MASK -#define IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_SHIFT 2 -#define IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_MASK 0x00000004U +#define IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_SHIFT 2 +#define IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_MASK 0x00000004U -/*UART Loopback Control. 0 = Connect UART inputs according to MIO mapping. 1 = Loop UART 0 outputs to UART 1 inputs, and UART 1 - outputs to UART 0 inputs. RXD/TXD cross-connected. RTS/CTS cross-connected. DSR, DTR, DCD and RI not used.*/ +/* +* UART Loopback Control. 0 = Connect UART inputs according to MIO mapping. + * 1 = Loop UART 0 outputs to UART 1 inputs, and UART 1 outputs to UART 0 + * inputs. RXD/TXD cross-connected. RTS/CTS cross-connected. DSR, DTR, DCD + * and RI not used. +*/ #undef IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_DEFVAL #undef IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_SHIFT #undef IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_MASK -#define IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_SHIFT 1 -#define IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_MASK 0x00000002U +#define IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_SHIFT 1 +#define IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_MASK 0x00000002U -/*SPI Loopback Control. 0 = Connect SPI inputs according to MIO mapping. 1 = Loop SPI 0 outputs to SPI 1 inputs, and SPI 1 outp - ts to SPI 0 inputs. The other SPI core will appear on the LS Slave Select.*/ +/* +* SPI Loopback Control. 0 = Connect SPI inputs according to MIO mapping. 1 + * = Loop SPI 0 outputs to SPI 1 inputs, and SPI 1 outputs to SPI 0 inputs + * . The other SPI core will appear on the LS Slave Select. +*/ #undef IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_DEFVAL #undef IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_SHIFT #undef IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_MASK -#define IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_SHIFT 0 -#define IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_MASK 0x00000001U +#define IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_SHIFT 0 +#define IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_MASK 0x00000001U +#undef CRF_APB_RST_FPD_TOP_OFFSET +#define CRF_APB_RST_FPD_TOP_OFFSET 0XFD1A0100 #undef CRL_APB_RST_LPD_IOU2_OFFSET #define CRL_APB_RST_LPD_IOU2_OFFSET 0XFF5E0238 +#undef CRL_APB_RST_LPD_TOP_OFFSET +#define CRL_APB_RST_LPD_TOP_OFFSET 0XFF5E023C #undef CRL_APB_RST_LPD_IOU0_OFFSET #define CRL_APB_RST_LPD_IOU0_OFFSET 0XFF5E0230 #undef CRL_APB_RST_LPD_IOU2_OFFSET @@ -24442,8 +31089,10 @@ #define IOU_SLCR_IOU_TAPDLY_BYPASS_OFFSET 0XFF180390 #undef CRL_APB_RST_LPD_TOP_OFFSET #define CRL_APB_RST_LPD_TOP_OFFSET 0XFF5E023C -#undef CRF_APB_RST_FPD_TOP_OFFSET -#define CRF_APB_RST_FPD_TOP_OFFSET 0XFD1A0100 +#undef USB3_0_FPD_POWER_PRSNT_OFFSET +#define USB3_0_FPD_POWER_PRSNT_OFFSET 0XFF9D0080 +#undef USB3_0_FPD_PIPE_CLK_OFFSET +#define USB3_0_FPD_PIPE_CLK_OFFSET 0XFF9D007C #undef CRL_APB_RST_LPD_IOU2_OFFSET #define CRL_APB_RST_LPD_IOU2_OFFSET 0XFF5E0238 #undef IOU_SLCR_CTRL_REG_SD_OFFSET @@ -24452,6 +31101,8 @@ #define IOU_SLCR_SD_CONFIG_REG2_OFFSET 0XFF180320 #undef IOU_SLCR_SD_CONFIG_REG1_OFFSET #define IOU_SLCR_SD_CONFIG_REG1_OFFSET 0XFF18031C +#undef IOU_SLCR_SD_DLL_CTRL_OFFSET +#define IOU_SLCR_SD_DLL_CTRL_OFFSET 0XFF180358 #undef IOU_SLCR_SD_CONFIG_REG3_OFFSET #define IOU_SLCR_SD_CONFIG_REG3_OFFSET 0XFF180324 #undef CRL_APB_RST_LPD_IOU2_OFFSET @@ -24480,6 +31131,8 @@ #define UART1_CONTROL_REG0_OFFSET 0XFF010000 #undef UART1_MODE_REG0_OFFSET #define UART1_MODE_REG0_OFFSET 0XFF010004 +#undef CRL_APB_RST_LPD_IOU2_OFFSET +#define CRL_APB_RST_LPD_IOU2_OFFSET 0XFF5E0238 #undef LPD_SLCR_SECURE_SLCR_ADMA_OFFSET #define LPD_SLCR_SECURE_SLCR_ADMA_OFFSET 0XFF4B0024 #undef CSU_TAMPER_STATUS_OFFSET @@ -24492,782 +31145,1656 @@ #define IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_OFFSET 0XFF260020 #undef IOU_SCNTRS_COUNTER_CONTROL_REGISTER_OFFSET #define IOU_SCNTRS_COUNTER_CONTROL_REGISTER_OFFSET 0XFF260000 +#undef GPIO_DIRM_1_OFFSET +#define GPIO_DIRM_1_OFFSET 0XFF0A0244 +#undef GPIO_OEN_1_OFFSET +#define GPIO_OEN_1_OFFSET 0XFF0A0248 +#undef GPIO_MASK_DATA_1_LSW_OFFSET +#define GPIO_MASK_DATA_1_LSW_OFFSET 0XFF0A0008 +#undef GPIO_MASK_DATA_1_LSW_OFFSET +#define GPIO_MASK_DATA_1_LSW_OFFSET 0XFF0A0008 -/*Block level reset*/ -#undef CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_DEFVAL -#undef CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_SHIFT -#undef CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_MASK -#define CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_DEFVAL 0x0017FFFF -#define CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_SHIFT 20 -#define CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_MASK 0x00100000U - -/*GEM 3 reset*/ -#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL -#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT -#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK -#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL 0x0000000F -#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT 3 -#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK 0x00000008U - -/*Block level reset*/ -#undef CRL_APB_RST_LPD_IOU2_QSPI_RESET_DEFVAL -#undef CRL_APB_RST_LPD_IOU2_QSPI_RESET_SHIFT -#undef CRL_APB_RST_LPD_IOU2_QSPI_RESET_MASK -#define CRL_APB_RST_LPD_IOU2_QSPI_RESET_DEFVAL 0x0017FFFF -#define CRL_APB_RST_LPD_IOU2_QSPI_RESET_SHIFT 0 -#define CRL_APB_RST_LPD_IOU2_QSPI_RESET_MASK 0x00000001U - -/*0: Do not by pass the tap delays on the Rx clock signal of LQSPI 1: Bypass the Tap delay on the Rx clock signal of LQSPI*/ -#undef IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_DEFVAL -#undef IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_SHIFT -#undef IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_MASK -#define IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_DEFVAL 0x00000007 -#define IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_SHIFT 2 -#define IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_MASK 0x00000004U - -/*USB 0 reset for control registers*/ -#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL -#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT -#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK -#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL 0x00188FDF -#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT 10 -#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK 0x00000400U - -/*USB 0 sleep circuit reset*/ -#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL -#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT -#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK -#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL 0x00188FDF -#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT 8 -#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK 0x00000100U - -/*USB 0 reset*/ -#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL -#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT -#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK -#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL 0x00188FDF -#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT 6 -#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK 0x00000040U - -/*PCIE config reset*/ +/* +* PCIE config reset +*/ #undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL #undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT #undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK -#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL 0x000F9FFE -#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT 19 -#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK 0x00080000U +#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT 19 +#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK 0x00080000U -/*PCIE control block level reset*/ +/* +* PCIE control block level reset +*/ #undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL #undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT #undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK -#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL 0x000F9FFE -#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT 17 -#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK 0x00020000U +#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT 17 +#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK 0x00020000U -/*PCIE bridge block level reset (AXI interface)*/ +/* +* PCIE bridge block level reset (AXI interface) +*/ #undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL #undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT #undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK -#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL 0x000F9FFE -#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT 18 -#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK 0x00040000U +#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT 18 +#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK 0x00040000U -/*Display Port block level reset (includes DPDMA)*/ +/* +* Display Port block level reset (includes DPDMA) +*/ #undef CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL #undef CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT #undef CRF_APB_RST_FPD_TOP_DP_RESET_MASK -#define CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL 0x000F9FFE -#define CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT 16 -#define CRF_APB_RST_FPD_TOP_DP_RESET_MASK 0x00010000U +#define CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT 16 +#define CRF_APB_RST_FPD_TOP_DP_RESET_MASK 0x00010000U -/*FPD WDT reset*/ +/* +* FPD WDT reset +*/ #undef CRF_APB_RST_FPD_TOP_SWDT_RESET_DEFVAL #undef CRF_APB_RST_FPD_TOP_SWDT_RESET_SHIFT #undef CRF_APB_RST_FPD_TOP_SWDT_RESET_MASK -#define CRF_APB_RST_FPD_TOP_SWDT_RESET_DEFVAL 0x000F9FFE -#define CRF_APB_RST_FPD_TOP_SWDT_RESET_SHIFT 15 -#define CRF_APB_RST_FPD_TOP_SWDT_RESET_MASK 0x00008000U +#define CRF_APB_RST_FPD_TOP_SWDT_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_SWDT_RESET_SHIFT 15 +#define CRF_APB_RST_FPD_TOP_SWDT_RESET_MASK 0x00008000U -/*GDMA block level reset*/ +/* +* GDMA block level reset +*/ #undef CRF_APB_RST_FPD_TOP_GDMA_RESET_DEFVAL #undef CRF_APB_RST_FPD_TOP_GDMA_RESET_SHIFT #undef CRF_APB_RST_FPD_TOP_GDMA_RESET_MASK -#define CRF_APB_RST_FPD_TOP_GDMA_RESET_DEFVAL 0x000F9FFE -#define CRF_APB_RST_FPD_TOP_GDMA_RESET_SHIFT 6 -#define CRF_APB_RST_FPD_TOP_GDMA_RESET_MASK 0x00000040U +#define CRF_APB_RST_FPD_TOP_GDMA_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_GDMA_RESET_SHIFT 6 +#define CRF_APB_RST_FPD_TOP_GDMA_RESET_MASK 0x00000040U -/*Pixel Processor (submodule of GPU) block level reset*/ +/* +* Pixel Processor (submodule of GPU) block level reset +*/ #undef CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_DEFVAL #undef CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_SHIFT #undef CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_MASK -#define CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_DEFVAL 0x000F9FFE -#define CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_SHIFT 4 -#define CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_MASK 0x00000010U +#define CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_SHIFT 4 +#define CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_MASK 0x00000010U -/*Pixel Processor (submodule of GPU) block level reset*/ +/* +* Pixel Processor (submodule of GPU) block level reset +*/ #undef CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_DEFVAL #undef CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_SHIFT #undef CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_MASK -#define CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_DEFVAL 0x000F9FFE -#define CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_SHIFT 5 -#define CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_MASK 0x00000020U +#define CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_SHIFT 5 +#define CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_MASK 0x00000020U -/*GPU block level reset*/ +/* +* GPU block level reset +*/ #undef CRF_APB_RST_FPD_TOP_GPU_RESET_DEFVAL #undef CRF_APB_RST_FPD_TOP_GPU_RESET_SHIFT #undef CRF_APB_RST_FPD_TOP_GPU_RESET_MASK -#define CRF_APB_RST_FPD_TOP_GPU_RESET_DEFVAL 0x000F9FFE -#define CRF_APB_RST_FPD_TOP_GPU_RESET_SHIFT 3 -#define CRF_APB_RST_FPD_TOP_GPU_RESET_MASK 0x00000008U +#define CRF_APB_RST_FPD_TOP_GPU_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_GPU_RESET_SHIFT 3 +#define CRF_APB_RST_FPD_TOP_GPU_RESET_MASK 0x00000008U -/*GT block level reset*/ +/* +* GT block level reset +*/ #undef CRF_APB_RST_FPD_TOP_GT_RESET_DEFVAL #undef CRF_APB_RST_FPD_TOP_GT_RESET_SHIFT #undef CRF_APB_RST_FPD_TOP_GT_RESET_MASK -#define CRF_APB_RST_FPD_TOP_GT_RESET_DEFVAL 0x000F9FFE -#define CRF_APB_RST_FPD_TOP_GT_RESET_SHIFT 2 -#define CRF_APB_RST_FPD_TOP_GT_RESET_MASK 0x00000004U +#define CRF_APB_RST_FPD_TOP_GT_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_GT_RESET_SHIFT 2 +#define CRF_APB_RST_FPD_TOP_GT_RESET_MASK 0x00000004U -/*Sata block level reset*/ +/* +* Sata block level reset +*/ #undef CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL #undef CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT #undef CRF_APB_RST_FPD_TOP_SATA_RESET_MASK -#define CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL 0x000F9FFE -#define CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT 1 -#define CRF_APB_RST_FPD_TOP_SATA_RESET_MASK 0x00000002U +#define CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT 1 +#define CRF_APB_RST_FPD_TOP_SATA_RESET_MASK 0x00000002U -/*Block level reset*/ +/* +* Block level reset +*/ +#undef CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_DEFVAL +#undef CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_SHIFT +#undef CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_MASK +#define CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_SHIFT 20 +#define CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_MASK 0x00100000U + +/* +* Block level reset +*/ +#undef CRL_APB_RST_LPD_IOU2_IOU_CC_RESET_DEFVAL +#undef CRL_APB_RST_LPD_IOU2_IOU_CC_RESET_SHIFT +#undef CRL_APB_RST_LPD_IOU2_IOU_CC_RESET_MASK +#define CRL_APB_RST_LPD_IOU2_IOU_CC_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_IOU_CC_RESET_SHIFT 19 +#define CRL_APB_RST_LPD_IOU2_IOU_CC_RESET_MASK 0x00080000U + +/* +* Block level reset +*/ +#undef CRL_APB_RST_LPD_IOU2_ADMA_RESET_DEFVAL +#undef CRL_APB_RST_LPD_IOU2_ADMA_RESET_SHIFT +#undef CRL_APB_RST_LPD_IOU2_ADMA_RESET_MASK +#define CRL_APB_RST_LPD_IOU2_ADMA_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_ADMA_RESET_SHIFT 17 +#define CRL_APB_RST_LPD_IOU2_ADMA_RESET_MASK 0x00020000U + +/* +* Reset entire full power domain. +*/ +#undef CRL_APB_RST_LPD_TOP_FPD_RESET_DEFVAL +#undef CRL_APB_RST_LPD_TOP_FPD_RESET_SHIFT +#undef CRL_APB_RST_LPD_TOP_FPD_RESET_MASK +#define CRL_APB_RST_LPD_TOP_FPD_RESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_FPD_RESET_SHIFT 23 +#define CRL_APB_RST_LPD_TOP_FPD_RESET_MASK 0x00800000U + +/* +* LPD SWDT +*/ +#undef CRL_APB_RST_LPD_TOP_LPD_SWDT_RESET_DEFVAL +#undef CRL_APB_RST_LPD_TOP_LPD_SWDT_RESET_SHIFT +#undef CRL_APB_RST_LPD_TOP_LPD_SWDT_RESET_MASK +#define CRL_APB_RST_LPD_TOP_LPD_SWDT_RESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_LPD_SWDT_RESET_SHIFT 20 +#define CRL_APB_RST_LPD_TOP_LPD_SWDT_RESET_MASK 0x00100000U + +/* +* Sysmonitor reset +*/ +#undef CRL_APB_RST_LPD_TOP_SYSMON_RESET_DEFVAL +#undef CRL_APB_RST_LPD_TOP_SYSMON_RESET_SHIFT +#undef CRL_APB_RST_LPD_TOP_SYSMON_RESET_MASK +#define CRL_APB_RST_LPD_TOP_SYSMON_RESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_SYSMON_RESET_SHIFT 17 +#define CRL_APB_RST_LPD_TOP_SYSMON_RESET_MASK 0x00020000U + +/* +* Real Time Clock reset +*/ +#undef CRL_APB_RST_LPD_TOP_RTC_RESET_DEFVAL +#undef CRL_APB_RST_LPD_TOP_RTC_RESET_SHIFT +#undef CRL_APB_RST_LPD_TOP_RTC_RESET_MASK +#define CRL_APB_RST_LPD_TOP_RTC_RESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_RTC_RESET_SHIFT 16 +#define CRL_APB_RST_LPD_TOP_RTC_RESET_MASK 0x00010000U + +/* +* APM reset +*/ +#undef CRL_APB_RST_LPD_TOP_APM_RESET_DEFVAL +#undef CRL_APB_RST_LPD_TOP_APM_RESET_SHIFT +#undef CRL_APB_RST_LPD_TOP_APM_RESET_MASK +#define CRL_APB_RST_LPD_TOP_APM_RESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_APM_RESET_SHIFT 15 +#define CRL_APB_RST_LPD_TOP_APM_RESET_MASK 0x00008000U + +/* +* IPI reset +*/ +#undef CRL_APB_RST_LPD_TOP_IPI_RESET_DEFVAL +#undef CRL_APB_RST_LPD_TOP_IPI_RESET_SHIFT +#undef CRL_APB_RST_LPD_TOP_IPI_RESET_MASK +#define CRL_APB_RST_LPD_TOP_IPI_RESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_IPI_RESET_SHIFT 14 +#define CRL_APB_RST_LPD_TOP_IPI_RESET_MASK 0x00004000U + +/* +* reset entire RPU power island +*/ +#undef CRL_APB_RST_LPD_TOP_RPU_PGE_RESET_DEFVAL +#undef CRL_APB_RST_LPD_TOP_RPU_PGE_RESET_SHIFT +#undef CRL_APB_RST_LPD_TOP_RPU_PGE_RESET_MASK +#define CRL_APB_RST_LPD_TOP_RPU_PGE_RESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_RPU_PGE_RESET_SHIFT 4 +#define CRL_APB_RST_LPD_TOP_RPU_PGE_RESET_MASK 0x00000010U + +/* +* reset ocm +*/ +#undef CRL_APB_RST_LPD_TOP_OCM_RESET_DEFVAL +#undef CRL_APB_RST_LPD_TOP_OCM_RESET_SHIFT +#undef CRL_APB_RST_LPD_TOP_OCM_RESET_MASK +#define CRL_APB_RST_LPD_TOP_OCM_RESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_OCM_RESET_SHIFT 3 +#define CRL_APB_RST_LPD_TOP_OCM_RESET_MASK 0x00000008U + +/* +* GEM 3 reset +*/ +#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL +#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT +#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK +#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL 0x0000000F +#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT 3 +#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK 0x00000008U + +/* +* Block level reset +*/ +#undef CRL_APB_RST_LPD_IOU2_QSPI_RESET_DEFVAL +#undef CRL_APB_RST_LPD_IOU2_QSPI_RESET_SHIFT +#undef CRL_APB_RST_LPD_IOU2_QSPI_RESET_MASK +#define CRL_APB_RST_LPD_IOU2_QSPI_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_QSPI_RESET_SHIFT 0 +#define CRL_APB_RST_LPD_IOU2_QSPI_RESET_MASK 0x00000001U + +/* +* 0: Do not by pass the tap delays on the Rx clock signal of LQSPI 1: Bypa + * ss the Tap delay on the Rx clock signal of LQSPI +*/ +#undef IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_DEFVAL +#undef IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_SHIFT +#undef IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_MASK +#define IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_DEFVAL 0x00000007 +#define IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_SHIFT 2 +#define IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_MASK 0x00000004U + +/* +* USB 0 reset for control registers +*/ +#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL +#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT +#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK +#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT 10 +#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK 0x00000400U + +/* +* USB 0 sleep circuit reset +*/ +#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL +#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT +#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK +#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT 8 +#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK 0x00000100U + +/* +* USB 0 reset +*/ +#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL +#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT +#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK +#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT 6 +#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK 0x00000040U + +/* +* This bit is used to choose between PIPE power present and 1'b1 +*/ +#undef USB3_0_FPD_POWER_PRSNT_OPTION_DEFVAL +#undef USB3_0_FPD_POWER_PRSNT_OPTION_SHIFT +#undef USB3_0_FPD_POWER_PRSNT_OPTION_MASK +#define USB3_0_FPD_POWER_PRSNT_OPTION_DEFVAL +#define USB3_0_FPD_POWER_PRSNT_OPTION_SHIFT 0 +#define USB3_0_FPD_POWER_PRSNT_OPTION_MASK 0x00000001U + +/* +* This bit is used to choose between PIPE clock coming from SerDes and the + * suspend clk +*/ +#undef USB3_0_FPD_PIPE_CLK_OPTION_DEFVAL +#undef USB3_0_FPD_PIPE_CLK_OPTION_SHIFT +#undef USB3_0_FPD_PIPE_CLK_OPTION_MASK +#define USB3_0_FPD_PIPE_CLK_OPTION_DEFVAL +#define USB3_0_FPD_PIPE_CLK_OPTION_SHIFT 0 +#define USB3_0_FPD_PIPE_CLK_OPTION_MASK 0x00000001U + +/* +* Block level reset +*/ #undef CRL_APB_RST_LPD_IOU2_SDIO1_RESET_DEFVAL #undef CRL_APB_RST_LPD_IOU2_SDIO1_RESET_SHIFT #undef CRL_APB_RST_LPD_IOU2_SDIO1_RESET_MASK -#define CRL_APB_RST_LPD_IOU2_SDIO1_RESET_DEFVAL 0x0017FFFF -#define CRL_APB_RST_LPD_IOU2_SDIO1_RESET_SHIFT 6 -#define CRL_APB_RST_LPD_IOU2_SDIO1_RESET_MASK 0x00000040U +#define CRL_APB_RST_LPD_IOU2_SDIO1_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_SDIO1_RESET_SHIFT 6 +#define CRL_APB_RST_LPD_IOU2_SDIO1_RESET_MASK 0x00000040U -/*SD or eMMC selection on SDIO1 0: SD enabled 1: eMMC enabled*/ +/* +* SD or eMMC selection on SDIO1 0: SD enabled 1: eMMC enabled +*/ #undef IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_DEFVAL #undef IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_SHIFT #undef IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_MASK -#define IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_SHIFT 15 -#define IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_MASK 0x00008000U +#define IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_SHIFT 15 +#define IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_MASK 0x00008000U -/*Should be set based on the final product usage 00 - Removable SCard Slot 01 - Embedded Slot for One Device 10 - Shared Bus Sl - t 11 - Reserved*/ +/* +* Should be set based on the final product usage 00 - Removable SCard Slot + * 01 - Embedded Slot for One Device 10 - Shared Bus Slot 11 - Reserved +*/ #undef IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_DEFVAL #undef IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_SHIFT #undef IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_MASK -#define IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_DEFVAL 0x0FFC0FFC -#define IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_SHIFT 28 -#define IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_MASK 0x30000000U +#define IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_DEFVAL 0x0FFC0FFC +#define IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_SHIFT 28 +#define IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_MASK 0x30000000U -/*1.8V Support 1: 1.8V supported 0: 1.8V not supported support*/ +/* +* 1.8V Support 1: 1.8V supported 0: 1.8V not supported support +*/ #undef IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_DEFVAL #undef IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_SHIFT #undef IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_MASK -#define IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_DEFVAL 0x0FFC0FFC -#define IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_SHIFT 25 -#define IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_MASK 0x02000000U +#define IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_DEFVAL 0x0FFC0FFC +#define IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_SHIFT 25 +#define IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_MASK 0x02000000U -/*3.0V Support 1: 3.0V supported 0: 3.0V not supported support*/ +/* +* 3.0V Support 1: 3.0V supported 0: 3.0V not supported support +*/ #undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_DEFVAL #undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_SHIFT #undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_MASK -#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_DEFVAL 0x0FFC0FFC -#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_SHIFT 24 -#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_MASK 0x01000000U +#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_DEFVAL 0x0FFC0FFC +#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_SHIFT 24 +#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_MASK 0x01000000U -/*3.3V Support 1: 3.3V supported 0: 3.3V not supported support*/ +/* +* 3.3V Support 1: 3.3V supported 0: 3.3V not supported support +*/ #undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_DEFVAL #undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_SHIFT #undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_MASK -#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_DEFVAL 0x0FFC0FFC -#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_SHIFT 23 -#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_MASK 0x00800000U +#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_DEFVAL 0x0FFC0FFC +#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_SHIFT 23 +#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_MASK 0x00800000U -/*Base Clock Frequency for SD Clock. This is the frequency of the xin_clk.*/ +/* +* Base Clock Frequency for SD Clock. This is the frequency of the xin_clk. +*/ #undef IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_DEFVAL #undef IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_SHIFT #undef IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_MASK -#define IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_DEFVAL 0x32403240 -#define IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_SHIFT 23 -#define IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_MASK 0x7F800000U +#define IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_DEFVAL 0x32403240 +#define IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_SHIFT 23 +#define IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_MASK 0x7F800000U -/*This is the Timer Count for Re-Tuning Timer for Re-Tuning Mode 1 to 3. Setting to 4'b0 disables Re-Tuning Timer. 0h - Get inf - rmation via other source 1h = 1 seconds 2h = 2 seconds 3h = 4 seconds 4h = 8 seconds -- n = 2(n-1) seconds -- Bh = 1024 secon - s Fh - Ch = Reserved*/ +/* +* Configures the Number of Taps (Phases) of the rxclk_in that is supported + * . +*/ +#undef IOU_SLCR_SD_CONFIG_REG1_SD1_TUNIGCOUNT_DEFVAL +#undef IOU_SLCR_SD_CONFIG_REG1_SD1_TUNIGCOUNT_SHIFT +#undef IOU_SLCR_SD_CONFIG_REG1_SD1_TUNIGCOUNT_MASK +#define IOU_SLCR_SD_CONFIG_REG1_SD1_TUNIGCOUNT_DEFVAL 0x32403240 +#define IOU_SLCR_SD_CONFIG_REG1_SD1_TUNIGCOUNT_SHIFT 17 +#define IOU_SLCR_SD_CONFIG_REG1_SD1_TUNIGCOUNT_MASK 0x007E0000U + +/* +* Reserved. +*/ +#undef IOU_SLCR_SD_DLL_CTRL_RESERVED_DEFVAL +#undef IOU_SLCR_SD_DLL_CTRL_RESERVED_SHIFT +#undef IOU_SLCR_SD_DLL_CTRL_RESERVED_MASK +#define IOU_SLCR_SD_DLL_CTRL_RESERVED_DEFVAL 0x00080008 +#define IOU_SLCR_SD_DLL_CTRL_RESERVED_SHIFT 3 +#define IOU_SLCR_SD_DLL_CTRL_RESERVED_MASK 0x00000008U + +/* +* This is the Timer Count for Re-Tuning Timer for Re-Tuning Mode 1 to 3. S + * etting to 4'b0 disables Re-Tuning Timer. 0h - Get information via other + * source 1h = 1 seconds 2h = 2 seconds 3h = 4 seconds 4h = 8 seconds -- n + * = 2(n-1) seconds -- Bh = 1024 seconds Fh - Ch = Reserved +*/ #undef IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_DEFVAL #undef IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_SHIFT #undef IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_MASK -#define IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_DEFVAL 0x06070607 -#define IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_SHIFT 22 -#define IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_MASK 0x03C00000U +#define IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_DEFVAL 0x06070607 +#define IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_SHIFT 22 +#define IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_MASK 0x03C00000U -/*Block level reset*/ +/* +* Block level reset +*/ #undef CRL_APB_RST_LPD_IOU2_CAN1_RESET_DEFVAL #undef CRL_APB_RST_LPD_IOU2_CAN1_RESET_SHIFT #undef CRL_APB_RST_LPD_IOU2_CAN1_RESET_MASK -#define CRL_APB_RST_LPD_IOU2_CAN1_RESET_DEFVAL 0x0017FFFF -#define CRL_APB_RST_LPD_IOU2_CAN1_RESET_SHIFT 8 -#define CRL_APB_RST_LPD_IOU2_CAN1_RESET_MASK 0x00000100U +#define CRL_APB_RST_LPD_IOU2_CAN1_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_CAN1_RESET_SHIFT 8 +#define CRL_APB_RST_LPD_IOU2_CAN1_RESET_MASK 0x00000100U -/*Block level reset*/ +/* +* Block level reset +*/ #undef CRL_APB_RST_LPD_IOU2_I2C0_RESET_DEFVAL #undef CRL_APB_RST_LPD_IOU2_I2C0_RESET_SHIFT #undef CRL_APB_RST_LPD_IOU2_I2C0_RESET_MASK -#define CRL_APB_RST_LPD_IOU2_I2C0_RESET_DEFVAL 0x0017FFFF -#define CRL_APB_RST_LPD_IOU2_I2C0_RESET_SHIFT 9 -#define CRL_APB_RST_LPD_IOU2_I2C0_RESET_MASK 0x00000200U +#define CRL_APB_RST_LPD_IOU2_I2C0_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_I2C0_RESET_SHIFT 9 +#define CRL_APB_RST_LPD_IOU2_I2C0_RESET_MASK 0x00000200U -/*Block level reset*/ +/* +* Block level reset +*/ #undef CRL_APB_RST_LPD_IOU2_I2C1_RESET_DEFVAL #undef CRL_APB_RST_LPD_IOU2_I2C1_RESET_SHIFT #undef CRL_APB_RST_LPD_IOU2_I2C1_RESET_MASK -#define CRL_APB_RST_LPD_IOU2_I2C1_RESET_DEFVAL 0x0017FFFF -#define CRL_APB_RST_LPD_IOU2_I2C1_RESET_SHIFT 10 -#define CRL_APB_RST_LPD_IOU2_I2C1_RESET_MASK 0x00000400U +#define CRL_APB_RST_LPD_IOU2_I2C1_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_I2C1_RESET_SHIFT 10 +#define CRL_APB_RST_LPD_IOU2_I2C1_RESET_MASK 0x00000400U -/*Block level reset*/ +/* +* Block level reset +*/ #undef CRL_APB_RST_LPD_IOU2_SWDT_RESET_DEFVAL #undef CRL_APB_RST_LPD_IOU2_SWDT_RESET_SHIFT #undef CRL_APB_RST_LPD_IOU2_SWDT_RESET_MASK -#define CRL_APB_RST_LPD_IOU2_SWDT_RESET_DEFVAL 0x0017FFFF -#define CRL_APB_RST_LPD_IOU2_SWDT_RESET_SHIFT 15 -#define CRL_APB_RST_LPD_IOU2_SWDT_RESET_MASK 0x00008000U +#define CRL_APB_RST_LPD_IOU2_SWDT_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_SWDT_RESET_SHIFT 15 +#define CRL_APB_RST_LPD_IOU2_SWDT_RESET_MASK 0x00008000U -/*Block level reset*/ +/* +* Block level reset +*/ #undef CRL_APB_RST_LPD_IOU2_TTC0_RESET_DEFVAL #undef CRL_APB_RST_LPD_IOU2_TTC0_RESET_SHIFT #undef CRL_APB_RST_LPD_IOU2_TTC0_RESET_MASK -#define CRL_APB_RST_LPD_IOU2_TTC0_RESET_DEFVAL 0x0017FFFF -#define CRL_APB_RST_LPD_IOU2_TTC0_RESET_SHIFT 11 -#define CRL_APB_RST_LPD_IOU2_TTC0_RESET_MASK 0x00000800U +#define CRL_APB_RST_LPD_IOU2_TTC0_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_TTC0_RESET_SHIFT 11 +#define CRL_APB_RST_LPD_IOU2_TTC0_RESET_MASK 0x00000800U -/*Block level reset*/ +/* +* Block level reset +*/ #undef CRL_APB_RST_LPD_IOU2_TTC1_RESET_DEFVAL #undef CRL_APB_RST_LPD_IOU2_TTC1_RESET_SHIFT #undef CRL_APB_RST_LPD_IOU2_TTC1_RESET_MASK -#define CRL_APB_RST_LPD_IOU2_TTC1_RESET_DEFVAL 0x0017FFFF -#define CRL_APB_RST_LPD_IOU2_TTC1_RESET_SHIFT 12 -#define CRL_APB_RST_LPD_IOU2_TTC1_RESET_MASK 0x00001000U +#define CRL_APB_RST_LPD_IOU2_TTC1_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_TTC1_RESET_SHIFT 12 +#define CRL_APB_RST_LPD_IOU2_TTC1_RESET_MASK 0x00001000U -/*Block level reset*/ +/* +* Block level reset +*/ #undef CRL_APB_RST_LPD_IOU2_TTC2_RESET_DEFVAL #undef CRL_APB_RST_LPD_IOU2_TTC2_RESET_SHIFT #undef CRL_APB_RST_LPD_IOU2_TTC2_RESET_MASK -#define CRL_APB_RST_LPD_IOU2_TTC2_RESET_DEFVAL 0x0017FFFF -#define CRL_APB_RST_LPD_IOU2_TTC2_RESET_SHIFT 13 -#define CRL_APB_RST_LPD_IOU2_TTC2_RESET_MASK 0x00002000U +#define CRL_APB_RST_LPD_IOU2_TTC2_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_TTC2_RESET_SHIFT 13 +#define CRL_APB_RST_LPD_IOU2_TTC2_RESET_MASK 0x00002000U -/*Block level reset*/ +/* +* Block level reset +*/ #undef CRL_APB_RST_LPD_IOU2_TTC3_RESET_DEFVAL #undef CRL_APB_RST_LPD_IOU2_TTC3_RESET_SHIFT #undef CRL_APB_RST_LPD_IOU2_TTC3_RESET_MASK -#define CRL_APB_RST_LPD_IOU2_TTC3_RESET_DEFVAL 0x0017FFFF -#define CRL_APB_RST_LPD_IOU2_TTC3_RESET_SHIFT 14 -#define CRL_APB_RST_LPD_IOU2_TTC3_RESET_MASK 0x00004000U +#define CRL_APB_RST_LPD_IOU2_TTC3_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_TTC3_RESET_SHIFT 14 +#define CRL_APB_RST_LPD_IOU2_TTC3_RESET_MASK 0x00004000U -/*Block level reset*/ +/* +* Block level reset +*/ #undef CRL_APB_RST_LPD_IOU2_UART0_RESET_DEFVAL #undef CRL_APB_RST_LPD_IOU2_UART0_RESET_SHIFT #undef CRL_APB_RST_LPD_IOU2_UART0_RESET_MASK -#define CRL_APB_RST_LPD_IOU2_UART0_RESET_DEFVAL 0x0017FFFF -#define CRL_APB_RST_LPD_IOU2_UART0_RESET_SHIFT 1 -#define CRL_APB_RST_LPD_IOU2_UART0_RESET_MASK 0x00000002U +#define CRL_APB_RST_LPD_IOU2_UART0_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_UART0_RESET_SHIFT 1 +#define CRL_APB_RST_LPD_IOU2_UART0_RESET_MASK 0x00000002U -/*Block level reset*/ +/* +* Block level reset +*/ #undef CRL_APB_RST_LPD_IOU2_UART1_RESET_DEFVAL #undef CRL_APB_RST_LPD_IOU2_UART1_RESET_SHIFT #undef CRL_APB_RST_LPD_IOU2_UART1_RESET_MASK -#define CRL_APB_RST_LPD_IOU2_UART1_RESET_DEFVAL 0x0017FFFF -#define CRL_APB_RST_LPD_IOU2_UART1_RESET_SHIFT 2 -#define CRL_APB_RST_LPD_IOU2_UART1_RESET_MASK 0x00000004U +#define CRL_APB_RST_LPD_IOU2_UART1_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_UART1_RESET_SHIFT 2 +#define CRL_APB_RST_LPD_IOU2_UART1_RESET_MASK 0x00000004U -/*Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate*/ +/* +* Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate +*/ #undef UART0_BAUD_RATE_DIVIDER_REG0_BDIV_DEFVAL #undef UART0_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT #undef UART0_BAUD_RATE_DIVIDER_REG0_BDIV_MASK -#define UART0_BAUD_RATE_DIVIDER_REG0_BDIV_DEFVAL 0x0000000F -#define UART0_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT 0 -#define UART0_BAUD_RATE_DIVIDER_REG0_BDIV_MASK 0x000000FFU +#define UART0_BAUD_RATE_DIVIDER_REG0_BDIV_DEFVAL 0x0000000F +#define UART0_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT 0 +#define UART0_BAUD_RATE_DIVIDER_REG0_BDIV_MASK 0x000000FFU -/*Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample*/ +/* +* Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor + * bypass (baud_sample = sel_clk) 2 - 65535: baud_sample +*/ #undef UART0_BAUD_RATE_GEN_REG0_CD_DEFVAL #undef UART0_BAUD_RATE_GEN_REG0_CD_SHIFT #undef UART0_BAUD_RATE_GEN_REG0_CD_MASK -#define UART0_BAUD_RATE_GEN_REG0_CD_DEFVAL 0x0000028B -#define UART0_BAUD_RATE_GEN_REG0_CD_SHIFT 0 -#define UART0_BAUD_RATE_GEN_REG0_CD_MASK 0x0000FFFFU +#define UART0_BAUD_RATE_GEN_REG0_CD_DEFVAL 0x0000028B +#define UART0_BAUD_RATE_GEN_REG0_CD_SHIFT 0 +#define UART0_BAUD_RATE_GEN_REG0_CD_MASK 0x0000FFFFU -/*Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a - high level during 12 bit periods. It can be set regardless of the value of STTBRK.*/ +/* +* Stop transmitter break: 0: no affect 1: stop transmission of the break a + * fter a minimum of one character length and transmit a high level during + * 12 bit periods. It can be set regardless of the value of STTBRK. +*/ #undef UART0_CONTROL_REG0_STPBRK_DEFVAL #undef UART0_CONTROL_REG0_STPBRK_SHIFT #undef UART0_CONTROL_REG0_STPBRK_MASK -#define UART0_CONTROL_REG0_STPBRK_DEFVAL 0x00000128 -#define UART0_CONTROL_REG0_STPBRK_SHIFT 8 -#define UART0_CONTROL_REG0_STPBRK_MASK 0x00000100U +#define UART0_CONTROL_REG0_STPBRK_DEFVAL 0x00000128 +#define UART0_CONTROL_REG0_STPBRK_SHIFT 8 +#define UART0_CONTROL_REG0_STPBRK_MASK 0x00000100U -/*Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the - transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high.*/ +/* +* Start transmitter break: 0: no affect 1: start to transmit a break after + * the characters currently present in the FIFO and the transmit shift reg + * ister have been transmitted. It can only be set if STPBRK (Stop transmit + * ter break) is not high. +*/ #undef UART0_CONTROL_REG0_STTBRK_DEFVAL #undef UART0_CONTROL_REG0_STTBRK_SHIFT #undef UART0_CONTROL_REG0_STTBRK_MASK -#define UART0_CONTROL_REG0_STTBRK_DEFVAL 0x00000128 -#define UART0_CONTROL_REG0_STTBRK_SHIFT 7 -#define UART0_CONTROL_REG0_STTBRK_MASK 0x00000080U +#define UART0_CONTROL_REG0_STTBRK_DEFVAL 0x00000128 +#define UART0_CONTROL_REG0_STTBRK_SHIFT 7 +#define UART0_CONTROL_REG0_STTBRK_MASK 0x00000080U -/*Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has co - pleted.*/ +/* +* Restart receiver timeout counter: 1: receiver timeout counter is restart + * ed. This bit is self clearing once the restart has completed. +*/ #undef UART0_CONTROL_REG0_RSTTO_DEFVAL #undef UART0_CONTROL_REG0_RSTTO_SHIFT #undef UART0_CONTROL_REG0_RSTTO_MASK -#define UART0_CONTROL_REG0_RSTTO_DEFVAL 0x00000128 -#define UART0_CONTROL_REG0_RSTTO_SHIFT 6 -#define UART0_CONTROL_REG0_RSTTO_MASK 0x00000040U +#define UART0_CONTROL_REG0_RSTTO_DEFVAL 0x00000128 +#define UART0_CONTROL_REG0_RSTTO_SHIFT 6 +#define UART0_CONTROL_REG0_RSTTO_MASK 0x00000040U -/*Transmit disable: 0: enable transmitter 1: disable transmitter*/ +/* +* Transmit disable: 0: enable transmitter 1: disable transmitter +*/ #undef UART0_CONTROL_REG0_TXDIS_DEFVAL #undef UART0_CONTROL_REG0_TXDIS_SHIFT #undef UART0_CONTROL_REG0_TXDIS_MASK -#define UART0_CONTROL_REG0_TXDIS_DEFVAL 0x00000128 -#define UART0_CONTROL_REG0_TXDIS_SHIFT 5 -#define UART0_CONTROL_REG0_TXDIS_MASK 0x00000020U +#define UART0_CONTROL_REG0_TXDIS_DEFVAL 0x00000128 +#define UART0_CONTROL_REG0_TXDIS_SHIFT 5 +#define UART0_CONTROL_REG0_TXDIS_MASK 0x00000020U -/*Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0.*/ +/* +* Transmit enable: 0: disable transmitter 1: enable transmitter, provided + * the TXDIS field is set to 0. +*/ #undef UART0_CONTROL_REG0_TXEN_DEFVAL #undef UART0_CONTROL_REG0_TXEN_SHIFT #undef UART0_CONTROL_REG0_TXEN_MASK -#define UART0_CONTROL_REG0_TXEN_DEFVAL 0x00000128 -#define UART0_CONTROL_REG0_TXEN_SHIFT 4 -#define UART0_CONTROL_REG0_TXEN_MASK 0x00000010U +#define UART0_CONTROL_REG0_TXEN_DEFVAL 0x00000128 +#define UART0_CONTROL_REG0_TXEN_SHIFT 4 +#define UART0_CONTROL_REG0_TXEN_MASK 0x00000010U -/*Receive disable: 0: enable 1: disable, regardless of the value of RXEN*/ +/* +* Receive disable: 0: enable 1: disable, regardless of the value of RXEN +*/ #undef UART0_CONTROL_REG0_RXDIS_DEFVAL #undef UART0_CONTROL_REG0_RXDIS_SHIFT #undef UART0_CONTROL_REG0_RXDIS_MASK -#define UART0_CONTROL_REG0_RXDIS_DEFVAL 0x00000128 -#define UART0_CONTROL_REG0_RXDIS_SHIFT 3 -#define UART0_CONTROL_REG0_RXDIS_MASK 0x00000008U +#define UART0_CONTROL_REG0_RXDIS_DEFVAL 0x00000128 +#define UART0_CONTROL_REG0_RXDIS_SHIFT 3 +#define UART0_CONTROL_REG0_RXDIS_MASK 0x00000008U -/*Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero.*/ +/* +* Receive enable: 0: disable 1: enable When set to one, the receiver logic + * is enabled, provided the RXDIS field is set to zero. +*/ #undef UART0_CONTROL_REG0_RXEN_DEFVAL #undef UART0_CONTROL_REG0_RXEN_SHIFT #undef UART0_CONTROL_REG0_RXEN_MASK -#define UART0_CONTROL_REG0_RXEN_DEFVAL 0x00000128 -#define UART0_CONTROL_REG0_RXEN_SHIFT 2 -#define UART0_CONTROL_REG0_RXEN_MASK 0x00000004U +#define UART0_CONTROL_REG0_RXEN_DEFVAL 0x00000128 +#define UART0_CONTROL_REG0_RXEN_SHIFT 2 +#define UART0_CONTROL_REG0_RXEN_MASK 0x00000004U -/*Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded Thi - bit is self clearing once the reset has completed.*/ +/* +* Software reset for Tx data path: 0: no affect 1: transmitter logic is re + * set and all pending transmitter data is discarded This bit is self clear + * ing once the reset has completed. +*/ #undef UART0_CONTROL_REG0_TXRES_DEFVAL #undef UART0_CONTROL_REG0_TXRES_SHIFT #undef UART0_CONTROL_REG0_TXRES_MASK -#define UART0_CONTROL_REG0_TXRES_DEFVAL 0x00000128 -#define UART0_CONTROL_REG0_TXRES_SHIFT 1 -#define UART0_CONTROL_REG0_TXRES_MASK 0x00000002U +#define UART0_CONTROL_REG0_TXRES_DEFVAL 0x00000128 +#define UART0_CONTROL_REG0_TXRES_SHIFT 1 +#define UART0_CONTROL_REG0_TXRES_MASK 0x00000002U -/*Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit - is self clearing once the reset has completed.*/ +/* +* Software reset for Rx data path: 0: no affect 1: receiver logic is reset + * and all pending receiver data is discarded. This bit is self clearing o + * nce the reset has completed. +*/ #undef UART0_CONTROL_REG0_RXRES_DEFVAL #undef UART0_CONTROL_REG0_RXRES_SHIFT #undef UART0_CONTROL_REG0_RXRES_MASK -#define UART0_CONTROL_REG0_RXRES_DEFVAL 0x00000128 -#define UART0_CONTROL_REG0_RXRES_SHIFT 0 -#define UART0_CONTROL_REG0_RXRES_MASK 0x00000001U +#define UART0_CONTROL_REG0_RXRES_DEFVAL 0x00000128 +#define UART0_CONTROL_REG0_RXRES_SHIFT 0 +#define UART0_CONTROL_REG0_RXRES_MASK 0x00000001U -/*Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback*/ +/* +* Channel mode: Defines the mode of operation of the UART. 00: normal 01: + * automatic echo 10: local loopback 11: remote loopback +*/ #undef UART0_MODE_REG0_CHMODE_DEFVAL #undef UART0_MODE_REG0_CHMODE_SHIFT #undef UART0_MODE_REG0_CHMODE_MASK -#define UART0_MODE_REG0_CHMODE_DEFVAL 0x00000000 -#define UART0_MODE_REG0_CHMODE_SHIFT 8 -#define UART0_MODE_REG0_CHMODE_MASK 0x00000300U +#define UART0_MODE_REG0_CHMODE_DEFVAL 0x00000000 +#define UART0_MODE_REG0_CHMODE_SHIFT 8 +#define UART0_MODE_REG0_CHMODE_MASK 0x00000300U -/*Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5 - stop bits 10: 2 stop bits 11: reserved*/ +/* +* Number of stop bits: Defines the number of stop bits to detect on receiv + * e and to generate on transmit. 00: 1 stop bit 01: 1.5 stop bits 10: 2 st + * op bits 11: reserved +*/ #undef UART0_MODE_REG0_NBSTOP_DEFVAL #undef UART0_MODE_REG0_NBSTOP_SHIFT #undef UART0_MODE_REG0_NBSTOP_MASK -#define UART0_MODE_REG0_NBSTOP_DEFVAL 0x00000000 -#define UART0_MODE_REG0_NBSTOP_SHIFT 6 -#define UART0_MODE_REG0_NBSTOP_MASK 0x000000C0U +#define UART0_MODE_REG0_NBSTOP_DEFVAL 0x00000000 +#define UART0_MODE_REG0_NBSTOP_SHIFT 6 +#define UART0_MODE_REG0_NBSTOP_MASK 0x000000C0U -/*Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity - 01: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity*/ +/* +* Parity type select: Defines the expected parity to check on receive and + * the parity to generate on transmit. 000: even parity 001: odd parity 010 + * : forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no pari + * ty +*/ #undef UART0_MODE_REG0_PAR_DEFVAL #undef UART0_MODE_REG0_PAR_SHIFT #undef UART0_MODE_REG0_PAR_MASK -#define UART0_MODE_REG0_PAR_DEFVAL 0x00000000 -#define UART0_MODE_REG0_PAR_SHIFT 3 -#define UART0_MODE_REG0_PAR_MASK 0x00000038U +#define UART0_MODE_REG0_PAR_DEFVAL 0x00000000 +#define UART0_MODE_REG0_PAR_SHIFT 3 +#define UART0_MODE_REG0_PAR_MASK 0x00000038U -/*Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits*/ +/* +* Character length select: Defines the number of bits in each character. 1 + * 1: 6 bits 10: 7 bits 0x: 8 bits +*/ #undef UART0_MODE_REG0_CHRL_DEFVAL #undef UART0_MODE_REG0_CHRL_SHIFT #undef UART0_MODE_REG0_CHRL_MASK -#define UART0_MODE_REG0_CHRL_DEFVAL 0x00000000 -#define UART0_MODE_REG0_CHRL_SHIFT 1 -#define UART0_MODE_REG0_CHRL_MASK 0x00000006U +#define UART0_MODE_REG0_CHRL_DEFVAL 0x00000000 +#define UART0_MODE_REG0_CHRL_SHIFT 1 +#define UART0_MODE_REG0_CHRL_MASK 0x00000006U -/*Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock - source is uart_ref_clk 1: clock source is uart_ref_clk/8*/ +/* +* Clock source select: This field defines whether a pre-scalar of 8 is app + * lied to the baud rate generator input clock. 0: clock source is uart_ref + * _clk 1: clock source is uart_ref_clk/8 +*/ #undef UART0_MODE_REG0_CLKS_DEFVAL #undef UART0_MODE_REG0_CLKS_SHIFT #undef UART0_MODE_REG0_CLKS_MASK -#define UART0_MODE_REG0_CLKS_DEFVAL 0x00000000 -#define UART0_MODE_REG0_CLKS_SHIFT 0 -#define UART0_MODE_REG0_CLKS_MASK 0x00000001U +#define UART0_MODE_REG0_CLKS_DEFVAL 0x00000000 +#define UART0_MODE_REG0_CLKS_SHIFT 0 +#define UART0_MODE_REG0_CLKS_MASK 0x00000001U -/*Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate*/ +/* +* Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate +*/ #undef UART1_BAUD_RATE_DIVIDER_REG0_BDIV_DEFVAL #undef UART1_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT #undef UART1_BAUD_RATE_DIVIDER_REG0_BDIV_MASK -#define UART1_BAUD_RATE_DIVIDER_REG0_BDIV_DEFVAL 0x0000000F -#define UART1_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT 0 -#define UART1_BAUD_RATE_DIVIDER_REG0_BDIV_MASK 0x000000FFU +#define UART1_BAUD_RATE_DIVIDER_REG0_BDIV_DEFVAL 0x0000000F +#define UART1_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT 0 +#define UART1_BAUD_RATE_DIVIDER_REG0_BDIV_MASK 0x000000FFU -/*Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample*/ +/* +* Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor + * bypass (baud_sample = sel_clk) 2 - 65535: baud_sample +*/ #undef UART1_BAUD_RATE_GEN_REG0_CD_DEFVAL #undef UART1_BAUD_RATE_GEN_REG0_CD_SHIFT #undef UART1_BAUD_RATE_GEN_REG0_CD_MASK -#define UART1_BAUD_RATE_GEN_REG0_CD_DEFVAL 0x0000028B -#define UART1_BAUD_RATE_GEN_REG0_CD_SHIFT 0 -#define UART1_BAUD_RATE_GEN_REG0_CD_MASK 0x0000FFFFU +#define UART1_BAUD_RATE_GEN_REG0_CD_DEFVAL 0x0000028B +#define UART1_BAUD_RATE_GEN_REG0_CD_SHIFT 0 +#define UART1_BAUD_RATE_GEN_REG0_CD_MASK 0x0000FFFFU -/*Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a - high level during 12 bit periods. It can be set regardless of the value of STTBRK.*/ +/* +* Stop transmitter break: 0: no affect 1: stop transmission of the break a + * fter a minimum of one character length and transmit a high level during + * 12 bit periods. It can be set regardless of the value of STTBRK. +*/ #undef UART1_CONTROL_REG0_STPBRK_DEFVAL #undef UART1_CONTROL_REG0_STPBRK_SHIFT #undef UART1_CONTROL_REG0_STPBRK_MASK -#define UART1_CONTROL_REG0_STPBRK_DEFVAL 0x00000128 -#define UART1_CONTROL_REG0_STPBRK_SHIFT 8 -#define UART1_CONTROL_REG0_STPBRK_MASK 0x00000100U +#define UART1_CONTROL_REG0_STPBRK_DEFVAL 0x00000128 +#define UART1_CONTROL_REG0_STPBRK_SHIFT 8 +#define UART1_CONTROL_REG0_STPBRK_MASK 0x00000100U -/*Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the - transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high.*/ +/* +* Start transmitter break: 0: no affect 1: start to transmit a break after + * the characters currently present in the FIFO and the transmit shift reg + * ister have been transmitted. It can only be set if STPBRK (Stop transmit + * ter break) is not high. +*/ #undef UART1_CONTROL_REG0_STTBRK_DEFVAL #undef UART1_CONTROL_REG0_STTBRK_SHIFT #undef UART1_CONTROL_REG0_STTBRK_MASK -#define UART1_CONTROL_REG0_STTBRK_DEFVAL 0x00000128 -#define UART1_CONTROL_REG0_STTBRK_SHIFT 7 -#define UART1_CONTROL_REG0_STTBRK_MASK 0x00000080U +#define UART1_CONTROL_REG0_STTBRK_DEFVAL 0x00000128 +#define UART1_CONTROL_REG0_STTBRK_SHIFT 7 +#define UART1_CONTROL_REG0_STTBRK_MASK 0x00000080U -/*Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has co - pleted.*/ +/* +* Restart receiver timeout counter: 1: receiver timeout counter is restart + * ed. This bit is self clearing once the restart has completed. +*/ #undef UART1_CONTROL_REG0_RSTTO_DEFVAL #undef UART1_CONTROL_REG0_RSTTO_SHIFT #undef UART1_CONTROL_REG0_RSTTO_MASK -#define UART1_CONTROL_REG0_RSTTO_DEFVAL 0x00000128 -#define UART1_CONTROL_REG0_RSTTO_SHIFT 6 -#define UART1_CONTROL_REG0_RSTTO_MASK 0x00000040U +#define UART1_CONTROL_REG0_RSTTO_DEFVAL 0x00000128 +#define UART1_CONTROL_REG0_RSTTO_SHIFT 6 +#define UART1_CONTROL_REG0_RSTTO_MASK 0x00000040U -/*Transmit disable: 0: enable transmitter 1: disable transmitter*/ +/* +* Transmit disable: 0: enable transmitter 1: disable transmitter +*/ #undef UART1_CONTROL_REG0_TXDIS_DEFVAL #undef UART1_CONTROL_REG0_TXDIS_SHIFT #undef UART1_CONTROL_REG0_TXDIS_MASK -#define UART1_CONTROL_REG0_TXDIS_DEFVAL 0x00000128 -#define UART1_CONTROL_REG0_TXDIS_SHIFT 5 -#define UART1_CONTROL_REG0_TXDIS_MASK 0x00000020U +#define UART1_CONTROL_REG0_TXDIS_DEFVAL 0x00000128 +#define UART1_CONTROL_REG0_TXDIS_SHIFT 5 +#define UART1_CONTROL_REG0_TXDIS_MASK 0x00000020U -/*Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0.*/ +/* +* Transmit enable: 0: disable transmitter 1: enable transmitter, provided + * the TXDIS field is set to 0. +*/ #undef UART1_CONTROL_REG0_TXEN_DEFVAL #undef UART1_CONTROL_REG0_TXEN_SHIFT #undef UART1_CONTROL_REG0_TXEN_MASK -#define UART1_CONTROL_REG0_TXEN_DEFVAL 0x00000128 -#define UART1_CONTROL_REG0_TXEN_SHIFT 4 -#define UART1_CONTROL_REG0_TXEN_MASK 0x00000010U +#define UART1_CONTROL_REG0_TXEN_DEFVAL 0x00000128 +#define UART1_CONTROL_REG0_TXEN_SHIFT 4 +#define UART1_CONTROL_REG0_TXEN_MASK 0x00000010U -/*Receive disable: 0: enable 1: disable, regardless of the value of RXEN*/ +/* +* Receive disable: 0: enable 1: disable, regardless of the value of RXEN +*/ #undef UART1_CONTROL_REG0_RXDIS_DEFVAL #undef UART1_CONTROL_REG0_RXDIS_SHIFT #undef UART1_CONTROL_REG0_RXDIS_MASK -#define UART1_CONTROL_REG0_RXDIS_DEFVAL 0x00000128 -#define UART1_CONTROL_REG0_RXDIS_SHIFT 3 -#define UART1_CONTROL_REG0_RXDIS_MASK 0x00000008U +#define UART1_CONTROL_REG0_RXDIS_DEFVAL 0x00000128 +#define UART1_CONTROL_REG0_RXDIS_SHIFT 3 +#define UART1_CONTROL_REG0_RXDIS_MASK 0x00000008U -/*Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero.*/ +/* +* Receive enable: 0: disable 1: enable When set to one, the receiver logic + * is enabled, provided the RXDIS field is set to zero. +*/ #undef UART1_CONTROL_REG0_RXEN_DEFVAL #undef UART1_CONTROL_REG0_RXEN_SHIFT #undef UART1_CONTROL_REG0_RXEN_MASK -#define UART1_CONTROL_REG0_RXEN_DEFVAL 0x00000128 -#define UART1_CONTROL_REG0_RXEN_SHIFT 2 -#define UART1_CONTROL_REG0_RXEN_MASK 0x00000004U +#define UART1_CONTROL_REG0_RXEN_DEFVAL 0x00000128 +#define UART1_CONTROL_REG0_RXEN_SHIFT 2 +#define UART1_CONTROL_REG0_RXEN_MASK 0x00000004U -/*Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded Thi - bit is self clearing once the reset has completed.*/ +/* +* Software reset for Tx data path: 0: no affect 1: transmitter logic is re + * set and all pending transmitter data is discarded This bit is self clear + * ing once the reset has completed. +*/ #undef UART1_CONTROL_REG0_TXRES_DEFVAL #undef UART1_CONTROL_REG0_TXRES_SHIFT #undef UART1_CONTROL_REG0_TXRES_MASK -#define UART1_CONTROL_REG0_TXRES_DEFVAL 0x00000128 -#define UART1_CONTROL_REG0_TXRES_SHIFT 1 -#define UART1_CONTROL_REG0_TXRES_MASK 0x00000002U +#define UART1_CONTROL_REG0_TXRES_DEFVAL 0x00000128 +#define UART1_CONTROL_REG0_TXRES_SHIFT 1 +#define UART1_CONTROL_REG0_TXRES_MASK 0x00000002U -/*Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit - is self clearing once the reset has completed.*/ +/* +* Software reset for Rx data path: 0: no affect 1: receiver logic is reset + * and all pending receiver data is discarded. This bit is self clearing o + * nce the reset has completed. +*/ #undef UART1_CONTROL_REG0_RXRES_DEFVAL #undef UART1_CONTROL_REG0_RXRES_SHIFT #undef UART1_CONTROL_REG0_RXRES_MASK -#define UART1_CONTROL_REG0_RXRES_DEFVAL 0x00000128 -#define UART1_CONTROL_REG0_RXRES_SHIFT 0 -#define UART1_CONTROL_REG0_RXRES_MASK 0x00000001U +#define UART1_CONTROL_REG0_RXRES_DEFVAL 0x00000128 +#define UART1_CONTROL_REG0_RXRES_SHIFT 0 +#define UART1_CONTROL_REG0_RXRES_MASK 0x00000001U -/*Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback*/ +/* +* Channel mode: Defines the mode of operation of the UART. 00: normal 01: + * automatic echo 10: local loopback 11: remote loopback +*/ #undef UART1_MODE_REG0_CHMODE_DEFVAL #undef UART1_MODE_REG0_CHMODE_SHIFT #undef UART1_MODE_REG0_CHMODE_MASK -#define UART1_MODE_REG0_CHMODE_DEFVAL 0x00000000 -#define UART1_MODE_REG0_CHMODE_SHIFT 8 -#define UART1_MODE_REG0_CHMODE_MASK 0x00000300U +#define UART1_MODE_REG0_CHMODE_DEFVAL 0x00000000 +#define UART1_MODE_REG0_CHMODE_SHIFT 8 +#define UART1_MODE_REG0_CHMODE_MASK 0x00000300U -/*Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5 - stop bits 10: 2 stop bits 11: reserved*/ +/* +* Number of stop bits: Defines the number of stop bits to detect on receiv + * e and to generate on transmit. 00: 1 stop bit 01: 1.5 stop bits 10: 2 st + * op bits 11: reserved +*/ #undef UART1_MODE_REG0_NBSTOP_DEFVAL #undef UART1_MODE_REG0_NBSTOP_SHIFT #undef UART1_MODE_REG0_NBSTOP_MASK -#define UART1_MODE_REG0_NBSTOP_DEFVAL 0x00000000 -#define UART1_MODE_REG0_NBSTOP_SHIFT 6 -#define UART1_MODE_REG0_NBSTOP_MASK 0x000000C0U +#define UART1_MODE_REG0_NBSTOP_DEFVAL 0x00000000 +#define UART1_MODE_REG0_NBSTOP_SHIFT 6 +#define UART1_MODE_REG0_NBSTOP_MASK 0x000000C0U -/*Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity - 01: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity*/ +/* +* Parity type select: Defines the expected parity to check on receive and + * the parity to generate on transmit. 000: even parity 001: odd parity 010 + * : forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no pari + * ty +*/ #undef UART1_MODE_REG0_PAR_DEFVAL #undef UART1_MODE_REG0_PAR_SHIFT #undef UART1_MODE_REG0_PAR_MASK -#define UART1_MODE_REG0_PAR_DEFVAL 0x00000000 -#define UART1_MODE_REG0_PAR_SHIFT 3 -#define UART1_MODE_REG0_PAR_MASK 0x00000038U +#define UART1_MODE_REG0_PAR_DEFVAL 0x00000000 +#define UART1_MODE_REG0_PAR_SHIFT 3 +#define UART1_MODE_REG0_PAR_MASK 0x00000038U -/*Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits*/ +/* +* Character length select: Defines the number of bits in each character. 1 + * 1: 6 bits 10: 7 bits 0x: 8 bits +*/ #undef UART1_MODE_REG0_CHRL_DEFVAL #undef UART1_MODE_REG0_CHRL_SHIFT #undef UART1_MODE_REG0_CHRL_MASK -#define UART1_MODE_REG0_CHRL_DEFVAL 0x00000000 -#define UART1_MODE_REG0_CHRL_SHIFT 1 -#define UART1_MODE_REG0_CHRL_MASK 0x00000006U +#define UART1_MODE_REG0_CHRL_DEFVAL 0x00000000 +#define UART1_MODE_REG0_CHRL_SHIFT 1 +#define UART1_MODE_REG0_CHRL_MASK 0x00000006U -/*Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock - source is uart_ref_clk 1: clock source is uart_ref_clk/8*/ +/* +* Clock source select: This field defines whether a pre-scalar of 8 is app + * lied to the baud rate generator input clock. 0: clock source is uart_ref + * _clk 1: clock source is uart_ref_clk/8 +*/ #undef UART1_MODE_REG0_CLKS_DEFVAL #undef UART1_MODE_REG0_CLKS_SHIFT #undef UART1_MODE_REG0_CLKS_MASK -#define UART1_MODE_REG0_CLKS_DEFVAL 0x00000000 -#define UART1_MODE_REG0_CLKS_SHIFT 0 -#define UART1_MODE_REG0_CLKS_MASK 0x00000001U +#define UART1_MODE_REG0_CLKS_DEFVAL 0x00000000 +#define UART1_MODE_REG0_CLKS_SHIFT 0 +#define UART1_MODE_REG0_CLKS_MASK 0x00000001U -/*TrustZone Classification for ADMA*/ +/* +* Block level reset +*/ +#undef CRL_APB_RST_LPD_IOU2_GPIO_RESET_DEFVAL +#undef CRL_APB_RST_LPD_IOU2_GPIO_RESET_SHIFT +#undef CRL_APB_RST_LPD_IOU2_GPIO_RESET_MASK +#define CRL_APB_RST_LPD_IOU2_GPIO_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_GPIO_RESET_SHIFT 18 +#define CRL_APB_RST_LPD_IOU2_GPIO_RESET_MASK 0x00040000U + +/* +* TrustZone Classification for ADMA +*/ #undef LPD_SLCR_SECURE_SLCR_ADMA_TZ_DEFVAL #undef LPD_SLCR_SECURE_SLCR_ADMA_TZ_SHIFT #undef LPD_SLCR_SECURE_SLCR_ADMA_TZ_MASK -#define LPD_SLCR_SECURE_SLCR_ADMA_TZ_DEFVAL -#define LPD_SLCR_SECURE_SLCR_ADMA_TZ_SHIFT 0 -#define LPD_SLCR_SECURE_SLCR_ADMA_TZ_MASK 0x000000FFU +#define LPD_SLCR_SECURE_SLCR_ADMA_TZ_DEFVAL +#define LPD_SLCR_SECURE_SLCR_ADMA_TZ_SHIFT 0 +#define LPD_SLCR_SECURE_SLCR_ADMA_TZ_MASK 0x000000FFU -/*CSU regsiter*/ +/* +* CSU regsiter +*/ #undef CSU_TAMPER_STATUS_TAMPER_0_DEFVAL #undef CSU_TAMPER_STATUS_TAMPER_0_SHIFT #undef CSU_TAMPER_STATUS_TAMPER_0_MASK -#define CSU_TAMPER_STATUS_TAMPER_0_DEFVAL 0x00000000 -#define CSU_TAMPER_STATUS_TAMPER_0_SHIFT 0 -#define CSU_TAMPER_STATUS_TAMPER_0_MASK 0x00000001U +#define CSU_TAMPER_STATUS_TAMPER_0_DEFVAL 0x00000000 +#define CSU_TAMPER_STATUS_TAMPER_0_SHIFT 0 +#define CSU_TAMPER_STATUS_TAMPER_0_MASK 0x00000001U -/*External MIO*/ +/* +* External MIO +*/ #undef CSU_TAMPER_STATUS_TAMPER_1_DEFVAL #undef CSU_TAMPER_STATUS_TAMPER_1_SHIFT #undef CSU_TAMPER_STATUS_TAMPER_1_MASK -#define CSU_TAMPER_STATUS_TAMPER_1_DEFVAL 0x00000000 -#define CSU_TAMPER_STATUS_TAMPER_1_SHIFT 1 -#define CSU_TAMPER_STATUS_TAMPER_1_MASK 0x00000002U +#define CSU_TAMPER_STATUS_TAMPER_1_DEFVAL 0x00000000 +#define CSU_TAMPER_STATUS_TAMPER_1_SHIFT 1 +#define CSU_TAMPER_STATUS_TAMPER_1_MASK 0x00000002U -/*JTAG toggle detect*/ +/* +* JTAG toggle detect +*/ #undef CSU_TAMPER_STATUS_TAMPER_2_DEFVAL #undef CSU_TAMPER_STATUS_TAMPER_2_SHIFT #undef CSU_TAMPER_STATUS_TAMPER_2_MASK -#define CSU_TAMPER_STATUS_TAMPER_2_DEFVAL 0x00000000 -#define CSU_TAMPER_STATUS_TAMPER_2_SHIFT 2 -#define CSU_TAMPER_STATUS_TAMPER_2_MASK 0x00000004U +#define CSU_TAMPER_STATUS_TAMPER_2_DEFVAL 0x00000000 +#define CSU_TAMPER_STATUS_TAMPER_2_SHIFT 2 +#define CSU_TAMPER_STATUS_TAMPER_2_MASK 0x00000004U -/*PL SEU error*/ +/* +* PL SEU error +*/ #undef CSU_TAMPER_STATUS_TAMPER_3_DEFVAL #undef CSU_TAMPER_STATUS_TAMPER_3_SHIFT #undef CSU_TAMPER_STATUS_TAMPER_3_MASK -#define CSU_TAMPER_STATUS_TAMPER_3_DEFVAL 0x00000000 -#define CSU_TAMPER_STATUS_TAMPER_3_SHIFT 3 -#define CSU_TAMPER_STATUS_TAMPER_3_MASK 0x00000008U +#define CSU_TAMPER_STATUS_TAMPER_3_DEFVAL 0x00000000 +#define CSU_TAMPER_STATUS_TAMPER_3_SHIFT 3 +#define CSU_TAMPER_STATUS_TAMPER_3_MASK 0x00000008U -/*AMS over temperature alarm for LPD*/ +/* +* AMS over temperature alarm for LPD +*/ #undef CSU_TAMPER_STATUS_TAMPER_4_DEFVAL #undef CSU_TAMPER_STATUS_TAMPER_4_SHIFT #undef CSU_TAMPER_STATUS_TAMPER_4_MASK -#define CSU_TAMPER_STATUS_TAMPER_4_DEFVAL 0x00000000 -#define CSU_TAMPER_STATUS_TAMPER_4_SHIFT 4 -#define CSU_TAMPER_STATUS_TAMPER_4_MASK 0x00000010U +#define CSU_TAMPER_STATUS_TAMPER_4_DEFVAL 0x00000000 +#define CSU_TAMPER_STATUS_TAMPER_4_SHIFT 4 +#define CSU_TAMPER_STATUS_TAMPER_4_MASK 0x00000010U -/*AMS over temperature alarm for APU*/ +/* +* AMS over temperature alarm for APU +*/ #undef CSU_TAMPER_STATUS_TAMPER_5_DEFVAL #undef CSU_TAMPER_STATUS_TAMPER_5_SHIFT #undef CSU_TAMPER_STATUS_TAMPER_5_MASK -#define CSU_TAMPER_STATUS_TAMPER_5_DEFVAL 0x00000000 -#define CSU_TAMPER_STATUS_TAMPER_5_SHIFT 5 -#define CSU_TAMPER_STATUS_TAMPER_5_MASK 0x00000020U +#define CSU_TAMPER_STATUS_TAMPER_5_DEFVAL 0x00000000 +#define CSU_TAMPER_STATUS_TAMPER_5_SHIFT 5 +#define CSU_TAMPER_STATUS_TAMPER_5_MASK 0x00000020U -/*AMS voltage alarm for VCCPINT_FPD*/ +/* +* AMS voltage alarm for VCCPINT_FPD +*/ #undef CSU_TAMPER_STATUS_TAMPER_6_DEFVAL #undef CSU_TAMPER_STATUS_TAMPER_6_SHIFT #undef CSU_TAMPER_STATUS_TAMPER_6_MASK -#define CSU_TAMPER_STATUS_TAMPER_6_DEFVAL 0x00000000 -#define CSU_TAMPER_STATUS_TAMPER_6_SHIFT 6 -#define CSU_TAMPER_STATUS_TAMPER_6_MASK 0x00000040U +#define CSU_TAMPER_STATUS_TAMPER_6_DEFVAL 0x00000000 +#define CSU_TAMPER_STATUS_TAMPER_6_SHIFT 6 +#define CSU_TAMPER_STATUS_TAMPER_6_MASK 0x00000040U -/*AMS voltage alarm for VCCPINT_LPD*/ +/* +* AMS voltage alarm for VCCPINT_LPD +*/ #undef CSU_TAMPER_STATUS_TAMPER_7_DEFVAL #undef CSU_TAMPER_STATUS_TAMPER_7_SHIFT #undef CSU_TAMPER_STATUS_TAMPER_7_MASK -#define CSU_TAMPER_STATUS_TAMPER_7_DEFVAL 0x00000000 -#define CSU_TAMPER_STATUS_TAMPER_7_SHIFT 7 -#define CSU_TAMPER_STATUS_TAMPER_7_MASK 0x00000080U +#define CSU_TAMPER_STATUS_TAMPER_7_DEFVAL 0x00000000 +#define CSU_TAMPER_STATUS_TAMPER_7_SHIFT 7 +#define CSU_TAMPER_STATUS_TAMPER_7_MASK 0x00000080U -/*AMS voltage alarm for VCCPAUX*/ +/* +* AMS voltage alarm for VCCPAUX +*/ #undef CSU_TAMPER_STATUS_TAMPER_8_DEFVAL #undef CSU_TAMPER_STATUS_TAMPER_8_SHIFT #undef CSU_TAMPER_STATUS_TAMPER_8_MASK -#define CSU_TAMPER_STATUS_TAMPER_8_DEFVAL 0x00000000 -#define CSU_TAMPER_STATUS_TAMPER_8_SHIFT 8 -#define CSU_TAMPER_STATUS_TAMPER_8_MASK 0x00000100U +#define CSU_TAMPER_STATUS_TAMPER_8_DEFVAL 0x00000000 +#define CSU_TAMPER_STATUS_TAMPER_8_SHIFT 8 +#define CSU_TAMPER_STATUS_TAMPER_8_MASK 0x00000100U -/*AMS voltage alarm for DDRPHY*/ +/* +* AMS voltage alarm for DDRPHY +*/ #undef CSU_TAMPER_STATUS_TAMPER_9_DEFVAL #undef CSU_TAMPER_STATUS_TAMPER_9_SHIFT #undef CSU_TAMPER_STATUS_TAMPER_9_MASK -#define CSU_TAMPER_STATUS_TAMPER_9_DEFVAL 0x00000000 -#define CSU_TAMPER_STATUS_TAMPER_9_SHIFT 9 -#define CSU_TAMPER_STATUS_TAMPER_9_MASK 0x00000200U +#define CSU_TAMPER_STATUS_TAMPER_9_DEFVAL 0x00000000 +#define CSU_TAMPER_STATUS_TAMPER_9_SHIFT 9 +#define CSU_TAMPER_STATUS_TAMPER_9_MASK 0x00000200U -/*AMS voltage alarm for PSIO bank 0/1/2*/ +/* +* AMS voltage alarm for PSIO bank 0/1/2 +*/ #undef CSU_TAMPER_STATUS_TAMPER_10_DEFVAL #undef CSU_TAMPER_STATUS_TAMPER_10_SHIFT #undef CSU_TAMPER_STATUS_TAMPER_10_MASK -#define CSU_TAMPER_STATUS_TAMPER_10_DEFVAL 0x00000000 -#define CSU_TAMPER_STATUS_TAMPER_10_SHIFT 10 -#define CSU_TAMPER_STATUS_TAMPER_10_MASK 0x00000400U +#define CSU_TAMPER_STATUS_TAMPER_10_DEFVAL 0x00000000 +#define CSU_TAMPER_STATUS_TAMPER_10_SHIFT 10 +#define CSU_TAMPER_STATUS_TAMPER_10_MASK 0x00000400U -/*AMS voltage alarm for PSIO bank 3 (dedicated pins)*/ +/* +* AMS voltage alarm for PSIO bank 3 (dedicated pins) +*/ #undef CSU_TAMPER_STATUS_TAMPER_11_DEFVAL #undef CSU_TAMPER_STATUS_TAMPER_11_SHIFT #undef CSU_TAMPER_STATUS_TAMPER_11_MASK -#define CSU_TAMPER_STATUS_TAMPER_11_DEFVAL 0x00000000 -#define CSU_TAMPER_STATUS_TAMPER_11_SHIFT 11 -#define CSU_TAMPER_STATUS_TAMPER_11_MASK 0x00000800U +#define CSU_TAMPER_STATUS_TAMPER_11_DEFVAL 0x00000000 +#define CSU_TAMPER_STATUS_TAMPER_11_SHIFT 11 +#define CSU_TAMPER_STATUS_TAMPER_11_MASK 0x00000800U -/*AMS voltaage alarm for GT*/ +/* +* AMS voltaage alarm for GT +*/ #undef CSU_TAMPER_STATUS_TAMPER_12_DEFVAL #undef CSU_TAMPER_STATUS_TAMPER_12_SHIFT #undef CSU_TAMPER_STATUS_TAMPER_12_MASK -#define CSU_TAMPER_STATUS_TAMPER_12_DEFVAL 0x00000000 -#define CSU_TAMPER_STATUS_TAMPER_12_SHIFT 12 -#define CSU_TAMPER_STATUS_TAMPER_12_MASK 0x00001000U +#define CSU_TAMPER_STATUS_TAMPER_12_DEFVAL 0x00000000 +#define CSU_TAMPER_STATUS_TAMPER_12_SHIFT 12 +#define CSU_TAMPER_STATUS_TAMPER_12_MASK 0x00001000U -/*Set ACE outgoing AWQOS value*/ +/* +* Set ACE outgoing AWQOS value +*/ #undef APU_ACE_CTRL_AWQOS_DEFVAL #undef APU_ACE_CTRL_AWQOS_SHIFT #undef APU_ACE_CTRL_AWQOS_MASK -#define APU_ACE_CTRL_AWQOS_DEFVAL 0x000F000F -#define APU_ACE_CTRL_AWQOS_SHIFT 16 -#define APU_ACE_CTRL_AWQOS_MASK 0x000F0000U +#define APU_ACE_CTRL_AWQOS_DEFVAL 0x000F000F +#define APU_ACE_CTRL_AWQOS_SHIFT 16 +#define APU_ACE_CTRL_AWQOS_MASK 0x000F0000U -/*Set ACE outgoing ARQOS value*/ +/* +* Set ACE outgoing ARQOS value +*/ #undef APU_ACE_CTRL_ARQOS_DEFVAL #undef APU_ACE_CTRL_ARQOS_SHIFT #undef APU_ACE_CTRL_ARQOS_MASK -#define APU_ACE_CTRL_ARQOS_DEFVAL 0x000F000F -#define APU_ACE_CTRL_ARQOS_SHIFT 0 -#define APU_ACE_CTRL_ARQOS_MASK 0x0000000FU +#define APU_ACE_CTRL_ARQOS_DEFVAL 0x000F000F +#define APU_ACE_CTRL_ARQOS_SHIFT 0 +#define APU_ACE_CTRL_ARQOS_MASK 0x0000000FU -/*Enables the RTC. By writing a 0 to this bit, RTC will be powered off and the only module that potentially draws current from - he battery will be BBRAM. The value read through this bit does not necessarily reflect whether RTC is enabled or not. It is e - pected that RTC is enabled every time it is being configured. If RTC is not used in the design, FSBL will disable it by writi - g a 0 to this bit.*/ +/* +* Enables the RTC. By writing a 0 to this bit, RTC will be powered off and + * the only module that potentially draws current from the battery will be + * BBRAM. The value read through this bit does not necessarily reflect whe + * ther RTC is enabled or not. It is expected that RTC is enabled every tim + * e it is being configured. If RTC is not used in the design, FSBL will di + * sable it by writing a 0 to this bit. +*/ #undef RTC_CONTROL_BATTERY_DISABLE_DEFVAL #undef RTC_CONTROL_BATTERY_DISABLE_SHIFT #undef RTC_CONTROL_BATTERY_DISABLE_MASK -#define RTC_CONTROL_BATTERY_DISABLE_DEFVAL 0x01000000 -#define RTC_CONTROL_BATTERY_DISABLE_SHIFT 31 -#define RTC_CONTROL_BATTERY_DISABLE_MASK 0x80000000U +#define RTC_CONTROL_BATTERY_DISABLE_DEFVAL 0x01000000 +#define RTC_CONTROL_BATTERY_DISABLE_SHIFT 31 +#define RTC_CONTROL_BATTERY_DISABLE_MASK 0x80000000U -/*Frequency in number of ticks per second. Valid range from 10 MHz to 100 MHz.*/ +/* +* Frequency in number of ticks per second. Valid range from 10 MHz to 100 + * MHz. +*/ #undef IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_DEFVAL #undef IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_SHIFT #undef IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_MASK -#define IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_DEFVAL -#define IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_SHIFT 0 -#define IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_MASK 0xFFFFFFFFU +#define IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_DEFVAL +#define IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_SHIFT 0 +#define IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_MASK 0xFFFFFFFFU -/*Enable 0: The counter is disabled and not incrementing. 1: The counter is enabled and is incrementing.*/ +/* +* Enable 0: The counter is disabled and not incrementing. 1: The counter i + * s enabled and is incrementing. +*/ #undef IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_DEFVAL #undef IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_SHIFT #undef IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_MASK -#define IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_DEFVAL 0x00000000 -#define IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_SHIFT 0 -#define IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_MASK 0x00000001U -#undef LPD_XPPU_CFG_IEN_OFFSET -#define LPD_XPPU_CFG_IEN_OFFSET 0XFF980018 +#define IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_DEFVAL 0x00000000 +#define IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_SHIFT 0 +#define IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_MASK 0x00000001U -/*See Interuppt Status Register for details*/ -#undef LPD_XPPU_CFG_IEN_APER_PARITY_DEFVAL -#undef LPD_XPPU_CFG_IEN_APER_PARITY_SHIFT -#undef LPD_XPPU_CFG_IEN_APER_PARITY_MASK -#define LPD_XPPU_CFG_IEN_APER_PARITY_DEFVAL 0x00000000 -#define LPD_XPPU_CFG_IEN_APER_PARITY_SHIFT 7 -#define LPD_XPPU_CFG_IEN_APER_PARITY_MASK 0x00000080U +/* +* Operation is the same as DIRM_0[DIRECTION_0] +*/ +#undef GPIO_DIRM_1_DIRECTION_1_DEFVAL +#undef GPIO_DIRM_1_DIRECTION_1_SHIFT +#undef GPIO_DIRM_1_DIRECTION_1_MASK +#define GPIO_DIRM_1_DIRECTION_1_DEFVAL 0x00000000 +#define GPIO_DIRM_1_DIRECTION_1_SHIFT 0 +#define GPIO_DIRM_1_DIRECTION_1_MASK 0x03FFFFFFU -/*See Interuppt Status Register for details*/ -#undef LPD_XPPU_CFG_IEN_APER_TZ_DEFVAL -#undef LPD_XPPU_CFG_IEN_APER_TZ_SHIFT -#undef LPD_XPPU_CFG_IEN_APER_TZ_MASK -#define LPD_XPPU_CFG_IEN_APER_TZ_DEFVAL 0x00000000 -#define LPD_XPPU_CFG_IEN_APER_TZ_SHIFT 6 -#define LPD_XPPU_CFG_IEN_APER_TZ_MASK 0x00000040U +/* +* Operation is the same as OEN_0[OP_ENABLE_0] +*/ +#undef GPIO_OEN_1_OP_ENABLE_1_DEFVAL +#undef GPIO_OEN_1_OP_ENABLE_1_SHIFT +#undef GPIO_OEN_1_OP_ENABLE_1_MASK +#define GPIO_OEN_1_OP_ENABLE_1_DEFVAL 0x00000000 +#define GPIO_OEN_1_OP_ENABLE_1_SHIFT 0 +#define GPIO_OEN_1_OP_ENABLE_1_MASK 0x03FFFFFFU -/*See Interuppt Status Register for details*/ -#undef LPD_XPPU_CFG_IEN_APER_PERM_DEFVAL -#undef LPD_XPPU_CFG_IEN_APER_PERM_SHIFT -#undef LPD_XPPU_CFG_IEN_APER_PERM_MASK -#define LPD_XPPU_CFG_IEN_APER_PERM_DEFVAL 0x00000000 -#define LPD_XPPU_CFG_IEN_APER_PERM_SHIFT 5 -#define LPD_XPPU_CFG_IEN_APER_PERM_MASK 0x00000020U +/* +* Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW] +*/ +#undef GPIO_MASK_DATA_1_LSW_MASK_1_LSW_DEFVAL +#undef GPIO_MASK_DATA_1_LSW_MASK_1_LSW_SHIFT +#undef GPIO_MASK_DATA_1_LSW_MASK_1_LSW_MASK +#define GPIO_MASK_DATA_1_LSW_MASK_1_LSW_DEFVAL 0x00000000 +#define GPIO_MASK_DATA_1_LSW_MASK_1_LSW_SHIFT 16 +#define GPIO_MASK_DATA_1_LSW_MASK_1_LSW_MASK 0xFFFF0000U -/*See Interuppt Status Register for details*/ -#undef LPD_XPPU_CFG_IEN_MID_PARITY_DEFVAL -#undef LPD_XPPU_CFG_IEN_MID_PARITY_SHIFT -#undef LPD_XPPU_CFG_IEN_MID_PARITY_MASK -#define LPD_XPPU_CFG_IEN_MID_PARITY_DEFVAL 0x00000000 -#define LPD_XPPU_CFG_IEN_MID_PARITY_SHIFT 3 -#define LPD_XPPU_CFG_IEN_MID_PARITY_MASK 0x00000008U +/* +* Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW] +*/ +#undef GPIO_MASK_DATA_1_LSW_DATA_1_LSW_DEFVAL +#undef GPIO_MASK_DATA_1_LSW_DATA_1_LSW_SHIFT +#undef GPIO_MASK_DATA_1_LSW_DATA_1_LSW_MASK +#define GPIO_MASK_DATA_1_LSW_DATA_1_LSW_DEFVAL 0x00000000 +#define GPIO_MASK_DATA_1_LSW_DATA_1_LSW_SHIFT 0 +#define GPIO_MASK_DATA_1_LSW_DATA_1_LSW_MASK 0x0000FFFFU -/*See Interuppt Status Register for details*/ -#undef LPD_XPPU_CFG_IEN_MID_RO_DEFVAL -#undef LPD_XPPU_CFG_IEN_MID_RO_SHIFT -#undef LPD_XPPU_CFG_IEN_MID_RO_MASK -#define LPD_XPPU_CFG_IEN_MID_RO_DEFVAL 0x00000000 -#define LPD_XPPU_CFG_IEN_MID_RO_SHIFT 2 -#define LPD_XPPU_CFG_IEN_MID_RO_MASK 0x00000004U +/* +* Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW] +*/ +#undef GPIO_MASK_DATA_1_LSW_MASK_1_LSW_DEFVAL +#undef GPIO_MASK_DATA_1_LSW_MASK_1_LSW_SHIFT +#undef GPIO_MASK_DATA_1_LSW_MASK_1_LSW_MASK +#define GPIO_MASK_DATA_1_LSW_MASK_1_LSW_DEFVAL 0x00000000 +#define GPIO_MASK_DATA_1_LSW_MASK_1_LSW_SHIFT 16 +#define GPIO_MASK_DATA_1_LSW_MASK_1_LSW_MASK 0xFFFF0000U -/*See Interuppt Status Register for details*/ -#undef LPD_XPPU_CFG_IEN_MID_MISS_DEFVAL -#undef LPD_XPPU_CFG_IEN_MID_MISS_SHIFT -#undef LPD_XPPU_CFG_IEN_MID_MISS_MASK -#define LPD_XPPU_CFG_IEN_MID_MISS_DEFVAL 0x00000000 -#define LPD_XPPU_CFG_IEN_MID_MISS_SHIFT 1 -#define LPD_XPPU_CFG_IEN_MID_MISS_MASK 0x00000002U +/* +* Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW] +*/ +#undef GPIO_MASK_DATA_1_LSW_DATA_1_LSW_DEFVAL +#undef GPIO_MASK_DATA_1_LSW_DATA_1_LSW_SHIFT +#undef GPIO_MASK_DATA_1_LSW_DATA_1_LSW_MASK +#define GPIO_MASK_DATA_1_LSW_DATA_1_LSW_DEFVAL 0x00000000 +#define GPIO_MASK_DATA_1_LSW_DATA_1_LSW_SHIFT 0 +#define GPIO_MASK_DATA_1_LSW_DATA_1_LSW_MASK 0x0000FFFFU +#undef FPD_SLCR_SECURE_SLCR_DPDMA_OFFSET +#define FPD_SLCR_SECURE_SLCR_DPDMA_OFFSET 0XFD690040 +#undef FPD_SLCR_SECURE_SLCR_PCIE_OFFSET +#define FPD_SLCR_SECURE_SLCR_PCIE_OFFSET 0XFD690030 +#undef LPD_SLCR_SECURE_SLCR_USB_OFFSET +#define LPD_SLCR_SECURE_SLCR_USB_OFFSET 0XFF4B0034 +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_OFFSET +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_OFFSET 0XFF240004 +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET 0XFF240000 +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_OFFSET +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_OFFSET 0XFF240004 +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET 0XFF240000 +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET 0XFF240000 +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_OFFSET +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_OFFSET 0XFF240004 +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET 0XFF240000 +#undef LPD_SLCR_SECURE_SLCR_ADMA_OFFSET +#define LPD_SLCR_SECURE_SLCR_ADMA_OFFSET 0XFF4B0024 +#undef FPD_SLCR_SECURE_SLCR_GDMA_OFFSET +#define FPD_SLCR_SECURE_SLCR_GDMA_OFFSET 0XFD690050 -/*See Interuppt Status Register for details*/ -#undef LPD_XPPU_CFG_IEN_INV_APB_DEFVAL -#undef LPD_XPPU_CFG_IEN_INV_APB_SHIFT -#undef LPD_XPPU_CFG_IEN_INV_APB_MASK -#define LPD_XPPU_CFG_IEN_INV_APB_DEFVAL 0x00000000 -#define LPD_XPPU_CFG_IEN_INV_APB_SHIFT 0 -#define LPD_XPPU_CFG_IEN_INV_APB_MASK 0x00000001U +/* +* TrustZone classification for DisplayPort DMA +*/ +#undef FPD_SLCR_SECURE_SLCR_DPDMA_TZ_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_DPDMA_TZ_SHIFT +#undef FPD_SLCR_SECURE_SLCR_DPDMA_TZ_MASK +#define FPD_SLCR_SECURE_SLCR_DPDMA_TZ_DEFVAL 0x00000001 +#define FPD_SLCR_SECURE_SLCR_DPDMA_TZ_SHIFT 0 +#define FPD_SLCR_SECURE_SLCR_DPDMA_TZ_MASK 0x00000001U + +/* +* TrustZone classification for DMA Channel 0 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_0_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_0_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_0_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_0_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_0_SHIFT 21 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_0_MASK 0x00200000U + +/* +* TrustZone classification for DMA Channel 1 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_1_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_1_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_1_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_1_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_1_SHIFT 22 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_1_MASK 0x00400000U + +/* +* TrustZone classification for DMA Channel 2 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_2_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_2_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_2_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_2_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_2_SHIFT 23 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_2_MASK 0x00800000U + +/* +* TrustZone classification for DMA Channel 3 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_3_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_3_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_3_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_3_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_3_SHIFT 24 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_3_MASK 0x01000000U + +/* +* TrustZone classification for Ingress Address Translation 0 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_0_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_0_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_0_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_0_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_0_SHIFT 13 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_0_MASK 0x00002000U + +/* +* TrustZone classification for Ingress Address Translation 1 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_1_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_1_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_1_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_1_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_1_SHIFT 14 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_1_MASK 0x00004000U + +/* +* TrustZone classification for Ingress Address Translation 2 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_2_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_2_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_2_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_2_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_2_SHIFT 15 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_2_MASK 0x00008000U + +/* +* TrustZone classification for Ingress Address Translation 3 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_3_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_3_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_3_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_3_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_3_SHIFT 16 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_3_MASK 0x00010000U + +/* +* TrustZone classification for Ingress Address Translation 4 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_4_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_4_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_4_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_4_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_4_SHIFT 17 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_4_MASK 0x00020000U + +/* +* TrustZone classification for Ingress Address Translation 5 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_5_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_5_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_5_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_5_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_5_SHIFT 18 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_5_MASK 0x00040000U + +/* +* TrustZone classification for Ingress Address Translation 6 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_6_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_6_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_6_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_6_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_6_SHIFT 19 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_6_MASK 0x00080000U + +/* +* TrustZone classification for Ingress Address Translation 7 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_7_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_7_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_7_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_7_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_7_SHIFT 20 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_7_MASK 0x00100000U + +/* +* TrustZone classification for Egress Address Translation 0 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_0_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_0_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_0_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_0_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_0_SHIFT 5 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_0_MASK 0x00000020U + +/* +* TrustZone classification for Egress Address Translation 1 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_1_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_1_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_1_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_1_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_1_SHIFT 6 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_1_MASK 0x00000040U + +/* +* TrustZone classification for Egress Address Translation 2 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_2_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_2_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_2_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_2_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_2_SHIFT 7 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_2_MASK 0x00000080U + +/* +* TrustZone classification for Egress Address Translation 3 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_3_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_3_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_3_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_3_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_3_SHIFT 8 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_3_MASK 0x00000100U + +/* +* TrustZone classification for Egress Address Translation 4 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_4_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_4_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_4_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_4_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_4_SHIFT 9 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_4_MASK 0x00000200U + +/* +* TrustZone classification for Egress Address Translation 5 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_5_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_5_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_5_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_5_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_5_SHIFT 10 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_5_MASK 0x00000400U + +/* +* TrustZone classification for Egress Address Translation 6 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_6_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_6_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_6_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_6_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_6_SHIFT 11 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_6_MASK 0x00000800U + +/* +* TrustZone classification for Egress Address Translation 7 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_7_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_7_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_7_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_7_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_7_SHIFT 12 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_7_MASK 0x00001000U + +/* +* TrustZone classification for DMA Registers +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_REGS_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_REGS_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_REGS_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_REGS_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_REGS_SHIFT 4 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_REGS_MASK 0x00000010U + +/* +* TrustZone classification for MSIx Table +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_TABLE_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_TABLE_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_TABLE_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_TABLE_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_TABLE_SHIFT 2 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_TABLE_MASK 0x00000004U + +/* +* TrustZone classification for MSIx PBA +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_PBA_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_PBA_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_PBA_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_PBA_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_PBA_SHIFT 3 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_PBA_MASK 0x00000008U + +/* +* TrustZone classification for ECAM +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_ECAM_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_ECAM_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_ECAM_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_ECAM_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_ECAM_SHIFT 1 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_ECAM_MASK 0x00000002U + +/* +* TrustZone classification for Bridge Common Registers +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_BRIDGE_REGS_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_BRIDGE_REGS_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_BRIDGE_REGS_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_BRIDGE_REGS_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_BRIDGE_REGS_SHIFT 0 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_BRIDGE_REGS_MASK 0x00000001U + +/* +* TrustZone Classification for USB3_0 +*/ +#undef LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_0_DEFVAL +#undef LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_0_SHIFT +#undef LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_0_MASK +#define LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_0_DEFVAL 0x00000003 +#define LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_0_SHIFT 0 +#define LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_0_MASK 0x00000001U + +/* +* TrustZone Classification for USB3_1 +*/ +#undef LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_1_DEFVAL +#undef LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_1_SHIFT +#undef LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_1_MASK +#define LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_1_DEFVAL 0x00000003 +#define LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_1_SHIFT 1 +#define LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_1_MASK 0x00000002U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD0_AXI_ARPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD0_AXI_ARPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD0_AXI_ARPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD0_AXI_ARPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD0_AXI_ARPROT_SHIFT 16 +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD0_AXI_ARPROT_MASK 0x00070000U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD1_AXI_ARPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD1_AXI_ARPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD1_AXI_ARPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD1_AXI_ARPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD1_AXI_ARPROT_SHIFT 19 +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD1_AXI_ARPROT_MASK 0x00380000U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD0_AXI_AWPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD0_AXI_AWPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD0_AXI_AWPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD0_AXI_AWPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD0_AXI_AWPROT_SHIFT 16 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD0_AXI_AWPROT_MASK 0x00070000U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD1_AXI_AWPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD1_AXI_AWPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD1_AXI_AWPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD1_AXI_AWPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD1_AXI_AWPROT_SHIFT 19 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD1_AXI_AWPROT_MASK 0x00380000U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM0_AXI_ARPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM0_AXI_ARPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM0_AXI_ARPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM0_AXI_ARPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM0_AXI_ARPROT_SHIFT 0 +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM0_AXI_ARPROT_MASK 0x00000007U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM1_AXI_ARPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM1_AXI_ARPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM1_AXI_ARPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM1_AXI_ARPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM1_AXI_ARPROT_SHIFT 3 +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM1_AXI_ARPROT_MASK 0x00000038U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM2_AXI_ARPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM2_AXI_ARPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM2_AXI_ARPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM2_AXI_ARPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM2_AXI_ARPROT_SHIFT 6 +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM2_AXI_ARPROT_MASK 0x000001C0U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM3_AXI_ARPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM3_AXI_ARPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM3_AXI_ARPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM3_AXI_ARPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM3_AXI_ARPROT_SHIFT 9 +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM3_AXI_ARPROT_MASK 0x00000E00U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM0_AXI_AWPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM0_AXI_AWPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM0_AXI_AWPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM0_AXI_AWPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM0_AXI_AWPROT_SHIFT 0 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM0_AXI_AWPROT_MASK 0x00000007U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM1_AXI_AWPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM1_AXI_AWPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM1_AXI_AWPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM1_AXI_AWPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM1_AXI_AWPROT_SHIFT 3 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM1_AXI_AWPROT_MASK 0x00000038U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM2_AXI_AWPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM2_AXI_AWPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM2_AXI_AWPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM2_AXI_AWPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM2_AXI_AWPROT_SHIFT 6 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM2_AXI_AWPROT_MASK 0x000001C0U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM3_AXI_AWPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM3_AXI_AWPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM3_AXI_AWPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM3_AXI_AWPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM3_AXI_AWPROT_SHIFT 9 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM3_AXI_AWPROT_MASK 0x00000E00U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_QSPI_AXI_AWPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_QSPI_AXI_AWPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_QSPI_AXI_AWPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_QSPI_AXI_AWPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_QSPI_AXI_AWPROT_SHIFT 25 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_QSPI_AXI_AWPROT_MASK 0x0E000000U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_NAND_AXI_ARPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_NAND_AXI_ARPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_NAND_AXI_ARPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_NAND_AXI_ARPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_NAND_AXI_ARPROT_SHIFT 22 +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_NAND_AXI_ARPROT_MASK 0x01C00000U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_NAND_AXI_AWPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_NAND_AXI_AWPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_NAND_AXI_AWPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_NAND_AXI_AWPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_NAND_AXI_AWPROT_SHIFT 22 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_NAND_AXI_AWPROT_MASK 0x01C00000U + +/* +* TrustZone Classification for ADMA +*/ +#undef LPD_SLCR_SECURE_SLCR_ADMA_TZ_DEFVAL +#undef LPD_SLCR_SECURE_SLCR_ADMA_TZ_SHIFT +#undef LPD_SLCR_SECURE_SLCR_ADMA_TZ_MASK +#define LPD_SLCR_SECURE_SLCR_ADMA_TZ_DEFVAL +#define LPD_SLCR_SECURE_SLCR_ADMA_TZ_SHIFT 0 +#define LPD_SLCR_SECURE_SLCR_ADMA_TZ_MASK 0x000000FFU + +/* +* TrustZone Classification for GDMA +*/ +#undef FPD_SLCR_SECURE_SLCR_GDMA_TZ_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_GDMA_TZ_SHIFT +#undef FPD_SLCR_SECURE_SLCR_GDMA_TZ_MASK +#define FPD_SLCR_SECURE_SLCR_GDMA_TZ_DEFVAL +#define FPD_SLCR_SECURE_SLCR_GDMA_TZ_SHIFT 0 +#define FPD_SLCR_SECURE_SLCR_GDMA_TZ_MASK 0x000000FFU #undef SERDES_PLL_REF_SEL0_OFFSET #define SERDES_PLL_REF_SEL0_OFFSET 0XFD410000 #undef SERDES_PLL_REF_SEL1_OFFSET @@ -25332,8 +32859,6 @@ #define SERDES_L3_TM_DIG_6_OFFSET 0XFD40D06C #undef SERDES_L3_TX_DIG_TM_61_OFFSET #define SERDES_L3_TX_DIG_TM_61_OFFSET 0XFD40C0F4 -#undef SERDES_L3_TXPMA_ST_0_OFFSET -#define SERDES_L3_TXPMA_ST_0_OFFSET 0XFD40CB00 #undef SERDES_L0_TM_AUX_0_OFFSET #define SERDES_L0_TM_AUX_0_OFFSET 0XFD4010CC #undef SERDES_L2_TM_AUX_0_OFFSET @@ -25372,6 +32897,10 @@ #define SERDES_L0_TM_E_ILL8_OFFSET 0XFD401940 #undef SERDES_L0_TM_E_ILL9_OFFSET #define SERDES_L0_TM_E_ILL9_OFFSET 0XFD401944 +#undef SERDES_L0_TM_ILL13_OFFSET +#define SERDES_L0_TM_ILL13_OFFSET 0XFD401994 +#undef SERDES_L1_TM_ILL13_OFFSET +#define SERDES_L1_TM_ILL13_OFFSET 0XFD405994 #undef SERDES_L2_TM_MISC2_OFFSET #define SERDES_L2_TM_MISC2_OFFSET 0XFD40989C #undef SERDES_L2_TM_IQ_ILL1_OFFSET @@ -25398,6 +32927,8 @@ #define SERDES_L2_TM_E_ILL8_OFFSET 0XFD409940 #undef SERDES_L2_TM_E_ILL9_OFFSET #define SERDES_L2_TM_E_ILL9_OFFSET 0XFD409944 +#undef SERDES_L2_TM_ILL13_OFFSET +#define SERDES_L2_TM_ILL13_OFFSET 0XFD409994 #undef SERDES_L3_TM_MISC2_OFFSET #define SERDES_L3_TM_MISC2_OFFSET 0XFD40D89C #undef SERDES_L3_TM_IQ_ILL1_OFFSET @@ -25426,10 +32957,16 @@ #define SERDES_L3_TM_E_ILL8_OFFSET 0XFD40D940 #undef SERDES_L3_TM_E_ILL9_OFFSET #define SERDES_L3_TM_E_ILL9_OFFSET 0XFD40D944 -#undef SERDES_L0_TM_DIG_21_OFFSET -#define SERDES_L0_TM_DIG_21_OFFSET 0XFD4010A8 +#undef SERDES_L3_TM_ILL13_OFFSET +#define SERDES_L3_TM_ILL13_OFFSET 0XFD40D994 #undef SERDES_L0_TM_DIG_10_OFFSET #define SERDES_L0_TM_DIG_10_OFFSET 0XFD40107C +#undef SERDES_L1_TM_DIG_10_OFFSET +#define SERDES_L1_TM_DIG_10_OFFSET 0XFD40507C +#undef SERDES_L2_TM_DIG_10_OFFSET +#define SERDES_L2_TM_DIG_10_OFFSET 0XFD40907C +#undef SERDES_L3_TM_DIG_10_OFFSET +#define SERDES_L3_TM_DIG_10_OFFSET 0XFD40D07C #undef SERDES_L0_TM_RST_DLY_OFFSET #define SERDES_L0_TM_RST_DLY_OFFSET 0XFD4019A4 #undef SERDES_L0_TM_ANA_BYP_15_OFFSET @@ -25454,6 +32991,24 @@ #define SERDES_L3_TM_ANA_BYP_15_OFFSET 0XFD40D038 #undef SERDES_L3_TM_ANA_BYP_12_OFFSET #define SERDES_L3_TM_ANA_BYP_12_OFFSET 0XFD40D02C +#undef SERDES_L0_TM_MISC3_OFFSET +#define SERDES_L0_TM_MISC3_OFFSET 0XFD4019AC +#undef SERDES_L1_TM_MISC3_OFFSET +#define SERDES_L1_TM_MISC3_OFFSET 0XFD4059AC +#undef SERDES_L2_TM_MISC3_OFFSET +#define SERDES_L2_TM_MISC3_OFFSET 0XFD4099AC +#undef SERDES_L3_TM_MISC3_OFFSET +#define SERDES_L3_TM_MISC3_OFFSET 0XFD40D9AC +#undef SERDES_L0_TM_EQ11_OFFSET +#define SERDES_L0_TM_EQ11_OFFSET 0XFD401978 +#undef SERDES_L1_TM_EQ11_OFFSET +#define SERDES_L1_TM_EQ11_OFFSET 0XFD405978 +#undef SERDES_L2_TM_EQ11_OFFSET +#define SERDES_L2_TM_EQ11_OFFSET 0XFD409978 +#undef SERDES_L3_TM_EQ11_OFFSET +#define SERDES_L3_TM_EQ11_OFFSET 0XFD40D978 +#undef SIOU_ECO_0_OFFSET +#define SIOU_ECO_0_OFFSET 0XFD3D001C #undef SERDES_ICM_CFG0_OFFSET #define SERDES_ICM_CFG0_OFFSET 0XFD410010 #undef SERDES_ICM_CFG1_OFFSET @@ -25479,1055 +33034,1511 @@ #undef SERDES_L3_TX_ANA_TM_18_OFFSET #define SERDES_L3_TX_ANA_TM_18_OFFSET 0XFD40C048 -/*PLL0 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - - 4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135 - Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved*/ +/* +* PLL0 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 1 + * 2MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 24MHz, 0x8 - 26MHz, + * 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE + * - 108MHz, 0xF - 125MHz, 0x10 - 135MHz, 0x11 - 150 MHz. 0x12 to 0x1F - R + * eserved +*/ #undef SERDES_PLL_REF_SEL0_PLLREFSEL0_DEFVAL #undef SERDES_PLL_REF_SEL0_PLLREFSEL0_SHIFT #undef SERDES_PLL_REF_SEL0_PLLREFSEL0_MASK -#define SERDES_PLL_REF_SEL0_PLLREFSEL0_DEFVAL 0x0000000D -#define SERDES_PLL_REF_SEL0_PLLREFSEL0_SHIFT 0 -#define SERDES_PLL_REF_SEL0_PLLREFSEL0_MASK 0x0000001FU +#define SERDES_PLL_REF_SEL0_PLLREFSEL0_DEFVAL 0x0000000D +#define SERDES_PLL_REF_SEL0_PLLREFSEL0_SHIFT 0 +#define SERDES_PLL_REF_SEL0_PLLREFSEL0_MASK 0x0000001FU -/*PLL1 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - - 4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135 - Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved*/ +/* +* PLL1 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 1 + * 2MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 24MHz, 0x8 - 26MHz, + * 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE + * - 108MHz, 0xF - 125MHz, 0x10 - 135MHz, 0x11 - 150 MHz. 0x12 to 0x1F - R + * eserved +*/ #undef SERDES_PLL_REF_SEL1_PLLREFSEL1_DEFVAL #undef SERDES_PLL_REF_SEL1_PLLREFSEL1_SHIFT #undef SERDES_PLL_REF_SEL1_PLLREFSEL1_MASK -#define SERDES_PLL_REF_SEL1_PLLREFSEL1_DEFVAL 0x00000008 -#define SERDES_PLL_REF_SEL1_PLLREFSEL1_SHIFT 0 -#define SERDES_PLL_REF_SEL1_PLLREFSEL1_MASK 0x0000001FU +#define SERDES_PLL_REF_SEL1_PLLREFSEL1_DEFVAL 0x00000008 +#define SERDES_PLL_REF_SEL1_PLLREFSEL1_SHIFT 0 +#define SERDES_PLL_REF_SEL1_PLLREFSEL1_MASK 0x0000001FU -/*PLL2 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - - 4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135 - Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved*/ +/* +* PLL2 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 1 + * 2MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 24MHz, 0x8 - 26MHz, + * 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE + * - 108MHz, 0xF - 125MHz, 0x10 - 135MHz, 0x11 - 150 MHz. 0x12 to 0x1F - R + * eserved +*/ #undef SERDES_PLL_REF_SEL2_PLLREFSEL2_DEFVAL #undef SERDES_PLL_REF_SEL2_PLLREFSEL2_SHIFT #undef SERDES_PLL_REF_SEL2_PLLREFSEL2_MASK -#define SERDES_PLL_REF_SEL2_PLLREFSEL2_DEFVAL 0x0000000F -#define SERDES_PLL_REF_SEL2_PLLREFSEL2_SHIFT 0 -#define SERDES_PLL_REF_SEL2_PLLREFSEL2_MASK 0x0000001FU +#define SERDES_PLL_REF_SEL2_PLLREFSEL2_DEFVAL 0x0000000F +#define SERDES_PLL_REF_SEL2_PLLREFSEL2_SHIFT 0 +#define SERDES_PLL_REF_SEL2_PLLREFSEL2_MASK 0x0000001FU -/*PLL3 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - - 4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135 - Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved*/ +/* +* PLL3 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 1 + * 2MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 24MHz, 0x8 - 26MHz, + * 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE + * - 108MHz, 0xF - 125MHz, 0x10 - 135MHz, 0x11 - 150 MHz. 0x12 to 0x1F - R + * eserved +*/ #undef SERDES_PLL_REF_SEL3_PLLREFSEL3_DEFVAL #undef SERDES_PLL_REF_SEL3_PLLREFSEL3_SHIFT #undef SERDES_PLL_REF_SEL3_PLLREFSEL3_MASK -#define SERDES_PLL_REF_SEL3_PLLREFSEL3_DEFVAL 0x0000000E -#define SERDES_PLL_REF_SEL3_PLLREFSEL3_SHIFT 0 -#define SERDES_PLL_REF_SEL3_PLLREFSEL3_MASK 0x0000001FU +#define SERDES_PLL_REF_SEL3_PLLREFSEL3_DEFVAL 0x0000000E +#define SERDES_PLL_REF_SEL3_PLLREFSEL3_SHIFT 0 +#define SERDES_PLL_REF_SEL3_PLLREFSEL3_MASK 0x0000001FU -/*Sel of lane 0 ref clock local mux. Set to 1 to select lane 0 slicer output. Set to 0 to select lane0 ref clock mux output.*/ +/* +* Sel of lane 0 ref clock local mux. Set to 1 to select lane 0 slicer outp + * ut. Set to 0 to select lane0 ref clock mux output. +*/ #undef SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_DEFVAL #undef SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_SHIFT #undef SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_MASK -#define SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_DEFVAL 0x00000080 -#define SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_SHIFT 7 -#define SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_MASK 0x00000080U +#define SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_DEFVAL 0x00000080 +#define SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_SHIFT 7 +#define SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_MASK 0x00000080U -/*Sel of lane 1 ref clock local mux. Set to 1 to select lane 1 slicer output. Set to 0 to select lane1 ref clock mux output.*/ +/* +* Sel of lane 1 ref clock local mux. Set to 1 to select lane 1 slicer outp + * ut. Set to 0 to select lane1 ref clock mux output. +*/ #undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_DEFVAL #undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_SHIFT #undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_MASK -#define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_DEFVAL 0x00000080 -#define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_SHIFT 7 -#define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_MASK 0x00000080U +#define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_DEFVAL 0x00000080 +#define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_SHIFT 7 +#define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_MASK 0x00000080U -/*Bit 3 of lane 1 ref clock mux one hot sel. Set to 1 to select lane 3 slicer output from ref clock network*/ +/* +* Bit 3 of lane 1 ref clock mux one hot sel. Set to 1 to select lane 3 sli + * cer output from ref clock network +*/ #undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_DEFVAL #undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_SHIFT #undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_MASK -#define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_DEFVAL 0x00000080 -#define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_SHIFT 3 -#define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_MASK 0x00000008U +#define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_DEFVAL 0x00000080 +#define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_SHIFT 3 +#define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_MASK 0x00000008U -/*Sel of lane 2 ref clock local mux. Set to 1 to select lane 1 slicer output. Set to 0 to select lane2 ref clock mux output.*/ +/* +* Sel of lane 2 ref clock local mux. Set to 1 to select lane 1 slicer outp + * ut. Set to 0 to select lane2 ref clock mux output. +*/ #undef SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_DEFVAL #undef SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_SHIFT #undef SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_MASK -#define SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_DEFVAL 0x00000080 -#define SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_SHIFT 7 -#define SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_MASK 0x00000080U +#define SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_DEFVAL 0x00000080 +#define SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_SHIFT 7 +#define SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_MASK 0x00000080U -/*Sel of lane 3 ref clock local mux. Set to 1 to select lane 3 slicer output. Set to 0 to select lane3 ref clock mux output.*/ +/* +* Sel of lane 3 ref clock local mux. Set to 1 to select lane 3 slicer outp + * ut. Set to 0 to select lane3 ref clock mux output. +*/ #undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_DEFVAL #undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_SHIFT #undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_MASK -#define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_DEFVAL 0x00000080 -#define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_SHIFT 7 -#define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_MASK 0x00000080U +#define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_DEFVAL 0x00000080 +#define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_SHIFT 7 +#define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_MASK 0x00000080U -/*Bit 1 of lane 3 ref clock mux one hot sel. Set to 1 to select lane 1 slicer output from ref clock network*/ +/* +* Bit 1 of lane 3 ref clock mux one hot sel. Set to 1 to select lane 1 sli + * cer output from ref clock network +*/ #undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_DEFVAL #undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_SHIFT #undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_MASK -#define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_DEFVAL 0x00000080 -#define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_SHIFT 1 -#define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_MASK 0x00000002U +#define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_DEFVAL 0x00000080 +#define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_SHIFT 1 +#define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_MASK 0x00000002U -/*Enable/Disable coarse code satureation limiting logic*/ +/* +* Enable/Disable coarse code satureation limiting logic +*/ #undef SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_DEFVAL #undef SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_SHIFT #undef SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_MASK -#define SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_DEFVAL 0x00000000 -#define SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_SHIFT 4 -#define SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_MASK 0x00000010U +#define SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_DEFVAL 0x00000000 +#define SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_SHIFT 4 +#define SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_MASK 0x00000010U -/*Spread Spectrum No of Steps [7:0]*/ +/* +* Spread Spectrum No of Steps [7:0] +*/ #undef SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL #undef SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT #undef SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK -#define SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL 0x00000000 -#define SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT 0 -#define SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK 0x000000FFU +#define SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL 0x00000000 +#define SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT 0 +#define SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK 0x000000FFU -/*Spread Spectrum No of Steps [10:8]*/ +/* +* Spread Spectrum No of Steps [10:8] +*/ #undef SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL #undef SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT #undef SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK -#define SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL 0x00000000 -#define SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT 0 -#define SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK 0x00000007U +#define SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL 0x00000000 +#define SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT 0 +#define SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK 0x00000007U -/*Spread Spectrum No of Steps [7:0]*/ +/* +* Spread Spectrum No of Steps [7:0] +*/ #undef SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL #undef SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT #undef SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK -#define SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL 0x00000000 -#define SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT 0 -#define SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK 0x000000FFU +#define SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL 0x00000000 +#define SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT 0 +#define SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK 0x000000FFU -/*Spread Spectrum No of Steps [10:8]*/ +/* +* Spread Spectrum No of Steps [10:8] +*/ #undef SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL #undef SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT #undef SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK -#define SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL 0x00000000 -#define SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT 0 -#define SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK 0x00000007U +#define SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL 0x00000000 +#define SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT 0 +#define SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK 0x00000007U -/*Spread Spectrum No of Steps [7:0]*/ +/* +* Spread Spectrum No of Steps [7:0] +*/ #undef SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL #undef SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT #undef SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK -#define SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL 0x00000000 -#define SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT 0 -#define SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK 0x000000FFU +#define SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL 0x00000000 +#define SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT 0 +#define SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK 0x000000FFU -/*Spread Spectrum No of Steps [10:8]*/ +/* +* Spread Spectrum No of Steps [10:8] +*/ #undef SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL #undef SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT #undef SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK -#define SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL 0x00000000 -#define SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT 0 -#define SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK 0x00000007U +#define SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL 0x00000000 +#define SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT 0 +#define SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK 0x00000007U -/*Step Size for Spread Spectrum [7:0]*/ +/* +* Step Size for Spread Spectrum [7:0] +*/ #undef SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL #undef SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT #undef SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK -#define SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL 0x00000000 -#define SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT 0 -#define SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK 0x000000FFU +#define SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL 0x00000000 +#define SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT 0 +#define SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK 0x000000FFU -/*Step Size for Spread Spectrum [15:8]*/ +/* +* Step Size for Spread Spectrum [15:8] +*/ #undef SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL #undef SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT #undef SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK -#define SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL 0x00000000 -#define SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT 0 -#define SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK 0x000000FFU +#define SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL 0x00000000 +#define SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT 0 +#define SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK 0x000000FFU -/*Step Size for Spread Spectrum [23:16]*/ +/* +* Step Size for Spread Spectrum [23:16] +*/ #undef SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL #undef SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT #undef SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK -#define SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL 0x00000000 -#define SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT 0 -#define SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK 0x000000FFU +#define SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL 0x00000000 +#define SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT 0 +#define SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK 0x000000FFU -/*Step Size for Spread Spectrum [25:24]*/ +/* +* Step Size for Spread Spectrum [25:24] +*/ #undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL #undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT #undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK -#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL 0x00000000 -#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT 0 -#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK 0x00000003U +#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL 0x00000000 +#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT 0 +#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK 0x00000003U -/*Enable/Disable test mode force on SS step size*/ +/* +* Enable/Disable test mode force on SS step size +*/ #undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL #undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT #undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK -#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL 0x00000000 -#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT 4 -#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK 0x00000010U +#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL 0x00000000 +#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT 4 +#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK 0x00000010U -/*Enable/Disable test mode force on SS no of steps*/ +/* +* Enable/Disable test mode force on SS no of steps +*/ #undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL #undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT #undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK -#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL 0x00000000 -#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT 5 -#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK 0x00000020U +#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL 0x00000000 +#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT 5 +#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK 0x00000020U -/*Step Size for Spread Spectrum [7:0]*/ +/* +* Step Size for Spread Spectrum [7:0] +*/ #undef SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL #undef SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT #undef SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK -#define SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL 0x00000000 -#define SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT 0 -#define SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK 0x000000FFU +#define SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL 0x00000000 +#define SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT 0 +#define SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK 0x000000FFU -/*Step Size for Spread Spectrum [15:8]*/ +/* +* Step Size for Spread Spectrum [15:8] +*/ #undef SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL #undef SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT #undef SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK -#define SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL 0x00000000 -#define SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT 0 -#define SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK 0x000000FFU +#define SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL 0x00000000 +#define SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT 0 +#define SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK 0x000000FFU -/*Step Size for Spread Spectrum [23:16]*/ +/* +* Step Size for Spread Spectrum [23:16] +*/ #undef SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL #undef SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT #undef SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK -#define SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL 0x00000000 -#define SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT 0 -#define SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK 0x000000FFU +#define SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL 0x00000000 +#define SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT 0 +#define SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK 0x000000FFU -/*Step Size for Spread Spectrum [25:24]*/ +/* +* Step Size for Spread Spectrum [25:24] +*/ #undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL #undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT #undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK -#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL 0x00000000 -#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT 0 -#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK 0x00000003U +#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL 0x00000000 +#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT 0 +#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK 0x00000003U -/*Enable/Disable test mode force on SS step size*/ +/* +* Enable/Disable test mode force on SS step size +*/ #undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL #undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT #undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK -#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL 0x00000000 -#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT 4 -#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK 0x00000010U +#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL 0x00000000 +#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT 4 +#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK 0x00000010U -/*Enable/Disable test mode force on SS no of steps*/ +/* +* Enable/Disable test mode force on SS no of steps +*/ #undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL #undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT #undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK -#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL 0x00000000 -#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT 5 -#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK 0x00000020U +#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL 0x00000000 +#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT 5 +#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK 0x00000020U -/*Step Size for Spread Spectrum [7:0]*/ +/* +* Step Size for Spread Spectrum [7:0] +*/ #undef SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL #undef SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT #undef SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK -#define SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL 0x00000000 -#define SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT 0 -#define SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK 0x000000FFU +#define SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL 0x00000000 +#define SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT 0 +#define SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK 0x000000FFU -/*Step Size for Spread Spectrum [15:8]*/ +/* +* Step Size for Spread Spectrum [15:8] +*/ #undef SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL #undef SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT #undef SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK -#define SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL 0x00000000 -#define SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT 0 -#define SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK 0x000000FFU +#define SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL 0x00000000 +#define SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT 0 +#define SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK 0x000000FFU -/*Step Size for Spread Spectrum [23:16]*/ +/* +* Step Size for Spread Spectrum [23:16] +*/ #undef SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL #undef SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT #undef SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK -#define SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL 0x00000000 -#define SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT 0 -#define SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK 0x000000FFU +#define SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL 0x00000000 +#define SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT 0 +#define SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK 0x000000FFU -/*Step Size for Spread Spectrum [25:24]*/ +/* +* Step Size for Spread Spectrum [25:24] +*/ #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK -#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL 0x00000000 -#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT 0 -#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK 0x00000003U +#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL 0x00000000 +#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT 0 +#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK 0x00000003U -/*Enable/Disable test mode force on SS step size*/ +/* +* Enable/Disable test mode force on SS step size +*/ #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK -#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL 0x00000000 -#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT 4 -#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK 0x00000010U +#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL 0x00000000 +#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT 4 +#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK 0x00000010U -/*Enable/Disable test mode force on SS no of steps*/ +/* +* Enable/Disable test mode force on SS no of steps +*/ #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK -#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL 0x00000000 -#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT 5 -#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK 0x00000020U +#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL 0x00000000 +#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT 5 +#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK 0x00000020U -/*Enable test mode forcing on enable Spread Spectrum*/ +/* +* Enable test mode forcing on enable Spread Spectrum +*/ #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_DEFVAL #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_SHIFT #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_MASK -#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_DEFVAL 0x00000000 -#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_SHIFT 7 -#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_MASK 0x00000080U +#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_DEFVAL 0x00000000 +#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_SHIFT 7 +#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_MASK 0x00000080U -/*Bypass Descrambler*/ +/* +* Bypass Descrambler +*/ #undef SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_DEFVAL #undef SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_SHIFT #undef SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_MASK -#define SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_DEFVAL 0x00000000 -#define SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_SHIFT 1 -#define SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_MASK 0x00000002U +#define SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_DEFVAL 0x00000000 +#define SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_SHIFT 1 +#define SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_MASK 0x00000002U -/*Enable Bypass for <1> TM_DIG_CTRL_6*/ +/* +* Enable Bypass for <1> TM_DIG_CTRL_6 +*/ #undef SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_DEFVAL #undef SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_SHIFT #undef SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_MASK -#define SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_DEFVAL 0x00000000 -#define SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_SHIFT 0 -#define SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_MASK 0x00000001U +#define SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_DEFVAL 0x00000000 +#define SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_SHIFT 0 +#define SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_MASK 0x00000001U -/*Bypass scrambler signal*/ +/* +* Bypass scrambler signal +*/ #undef SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_DEFVAL #undef SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_SHIFT #undef SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_MASK -#define SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_DEFVAL 0x00000000 -#define SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_SHIFT 1 -#define SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_MASK 0x00000002U +#define SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_DEFVAL 0x00000000 +#define SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_SHIFT 1 +#define SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_MASK 0x00000002U -/*Enable/disable scrambler bypass signal*/ +/* +* Enable/disable scrambler bypass signal +*/ #undef SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_DEFVAL #undef SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_SHIFT #undef SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_MASK -#define SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_DEFVAL 0x00000000 -#define SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_SHIFT 0 -#define SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_MASK 0x00000001U +#define SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_DEFVAL 0x00000000 +#define SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_SHIFT 0 +#define SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_MASK 0x00000001U -/*Enable test mode force on fractional mode enable*/ +/* +* Enable test mode force on fractional mode enable +*/ #undef SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_DEFVAL #undef SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_SHIFT #undef SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_MASK -#define SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_DEFVAL 0x00000000 -#define SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_SHIFT 6 -#define SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_MASK 0x00000040U +#define SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_DEFVAL 0x00000000 +#define SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_SHIFT 6 +#define SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_MASK 0x00000040U -/*Bypass 8b10b decoder*/ +/* +* Bypass 8b10b decoder +*/ #undef SERDES_L3_TM_DIG_6_BYPASS_DECODER_DEFVAL #undef SERDES_L3_TM_DIG_6_BYPASS_DECODER_SHIFT #undef SERDES_L3_TM_DIG_6_BYPASS_DECODER_MASK -#define SERDES_L3_TM_DIG_6_BYPASS_DECODER_DEFVAL 0x00000000 -#define SERDES_L3_TM_DIG_6_BYPASS_DECODER_SHIFT 3 -#define SERDES_L3_TM_DIG_6_BYPASS_DECODER_MASK 0x00000008U +#define SERDES_L3_TM_DIG_6_BYPASS_DECODER_DEFVAL 0x00000000 +#define SERDES_L3_TM_DIG_6_BYPASS_DECODER_SHIFT 3 +#define SERDES_L3_TM_DIG_6_BYPASS_DECODER_MASK 0x00000008U -/*Enable Bypass for <3> TM_DIG_CTRL_6*/ +/* +* Enable Bypass for <3> TM_DIG_CTRL_6 +*/ #undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_DEFVAL #undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_SHIFT #undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_MASK -#define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_DEFVAL 0x00000000 -#define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_SHIFT 2 -#define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_MASK 0x00000004U +#define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_DEFVAL 0x00000000 +#define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_SHIFT 2 +#define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_MASK 0x00000004U -/*Bypass Descrambler*/ +/* +* Bypass Descrambler +*/ #undef SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_DEFVAL #undef SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_SHIFT #undef SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_MASK -#define SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_DEFVAL 0x00000000 -#define SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_SHIFT 1 -#define SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_MASK 0x00000002U +#define SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_DEFVAL 0x00000000 +#define SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_SHIFT 1 +#define SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_MASK 0x00000002U -/*Enable Bypass for <1> TM_DIG_CTRL_6*/ +/* +* Enable Bypass for <1> TM_DIG_CTRL_6 +*/ #undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_DEFVAL #undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_SHIFT #undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_MASK -#define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_DEFVAL 0x00000000 -#define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_SHIFT 0 -#define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_MASK 0x00000001U +#define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_DEFVAL 0x00000000 +#define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_SHIFT 0 +#define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_MASK 0x00000001U -/*Enable/disable encoder bypass signal*/ +/* +* Enable/disable encoder bypass signal +*/ #undef SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_DEFVAL #undef SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_SHIFT #undef SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_MASK -#define SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_DEFVAL 0x00000000 -#define SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_SHIFT 3 -#define SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_MASK 0x00000008U +#define SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_DEFVAL 0x00000000 +#define SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_SHIFT 3 +#define SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_MASK 0x00000008U -/*Bypass scrambler signal*/ +/* +* Bypass scrambler signal +*/ #undef SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_DEFVAL #undef SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_SHIFT #undef SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_MASK -#define SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_DEFVAL 0x00000000 -#define SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_SHIFT 1 -#define SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_MASK 0x00000002U +#define SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_DEFVAL 0x00000000 +#define SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_SHIFT 1 +#define SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_MASK 0x00000002U -/*Enable/disable scrambler bypass signal*/ +/* +* Enable/disable scrambler bypass signal +*/ #undef SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_DEFVAL #undef SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_SHIFT #undef SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_MASK -#define SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_DEFVAL 0x00000000 -#define SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_SHIFT 0 -#define SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_MASK 0x00000001U +#define SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_DEFVAL 0x00000000 +#define SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_SHIFT 0 +#define SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_MASK 0x00000001U -/*PHY Mode: 4'b000 - PCIe, 4'b001 - USB3, 4'b0010 - SATA, 4'b0100 - SGMII, 4'b0101 - DP, 4'b1000 - MPHY*/ -#undef SERDES_L3_TXPMA_ST_0_TX_PHY_MODE_DEFVAL -#undef SERDES_L3_TXPMA_ST_0_TX_PHY_MODE_SHIFT -#undef SERDES_L3_TXPMA_ST_0_TX_PHY_MODE_MASK -#define SERDES_L3_TXPMA_ST_0_TX_PHY_MODE_DEFVAL 0x00000001 -#define SERDES_L3_TXPMA_ST_0_TX_PHY_MODE_SHIFT 4 -#define SERDES_L3_TXPMA_ST_0_TX_PHY_MODE_MASK 0x000000F0U - -/*Spare- not used*/ +/* +* Spare- not used +*/ #undef SERDES_L0_TM_AUX_0_BIT_2_DEFVAL #undef SERDES_L0_TM_AUX_0_BIT_2_SHIFT #undef SERDES_L0_TM_AUX_0_BIT_2_MASK -#define SERDES_L0_TM_AUX_0_BIT_2_DEFVAL 0x00000000 -#define SERDES_L0_TM_AUX_0_BIT_2_SHIFT 5 -#define SERDES_L0_TM_AUX_0_BIT_2_MASK 0x00000020U +#define SERDES_L0_TM_AUX_0_BIT_2_DEFVAL 0x00000000 +#define SERDES_L0_TM_AUX_0_BIT_2_SHIFT 5 +#define SERDES_L0_TM_AUX_0_BIT_2_MASK 0x00000020U -/*Spare- not used*/ +/* +* Spare- not used +*/ #undef SERDES_L2_TM_AUX_0_BIT_2_DEFVAL #undef SERDES_L2_TM_AUX_0_BIT_2_SHIFT #undef SERDES_L2_TM_AUX_0_BIT_2_MASK -#define SERDES_L2_TM_AUX_0_BIT_2_DEFVAL 0x00000000 -#define SERDES_L2_TM_AUX_0_BIT_2_SHIFT 5 -#define SERDES_L2_TM_AUX_0_BIT_2_MASK 0x00000020U +#define SERDES_L2_TM_AUX_0_BIT_2_DEFVAL 0x00000000 +#define SERDES_L2_TM_AUX_0_BIT_2_SHIFT 5 +#define SERDES_L2_TM_AUX_0_BIT_2_MASK 0x00000020U -/*Enable Eye Surf*/ +/* +* Enable Eye Surf +*/ #undef SERDES_L0_TM_DIG_8_EYESURF_ENABLE_DEFVAL #undef SERDES_L0_TM_DIG_8_EYESURF_ENABLE_SHIFT #undef SERDES_L0_TM_DIG_8_EYESURF_ENABLE_MASK -#define SERDES_L0_TM_DIG_8_EYESURF_ENABLE_DEFVAL 0x00000000 -#define SERDES_L0_TM_DIG_8_EYESURF_ENABLE_SHIFT 4 -#define SERDES_L0_TM_DIG_8_EYESURF_ENABLE_MASK 0x00000010U +#define SERDES_L0_TM_DIG_8_EYESURF_ENABLE_DEFVAL 0x00000000 +#define SERDES_L0_TM_DIG_8_EYESURF_ENABLE_SHIFT 4 +#define SERDES_L0_TM_DIG_8_EYESURF_ENABLE_MASK 0x00000010U -/*Enable Eye Surf*/ +/* +* Enable Eye Surf +*/ #undef SERDES_L1_TM_DIG_8_EYESURF_ENABLE_DEFVAL #undef SERDES_L1_TM_DIG_8_EYESURF_ENABLE_SHIFT #undef SERDES_L1_TM_DIG_8_EYESURF_ENABLE_MASK -#define SERDES_L1_TM_DIG_8_EYESURF_ENABLE_DEFVAL 0x00000000 -#define SERDES_L1_TM_DIG_8_EYESURF_ENABLE_SHIFT 4 -#define SERDES_L1_TM_DIG_8_EYESURF_ENABLE_MASK 0x00000010U +#define SERDES_L1_TM_DIG_8_EYESURF_ENABLE_DEFVAL 0x00000000 +#define SERDES_L1_TM_DIG_8_EYESURF_ENABLE_SHIFT 4 +#define SERDES_L1_TM_DIG_8_EYESURF_ENABLE_MASK 0x00000010U -/*Enable Eye Surf*/ +/* +* Enable Eye Surf +*/ #undef SERDES_L2_TM_DIG_8_EYESURF_ENABLE_DEFVAL #undef SERDES_L2_TM_DIG_8_EYESURF_ENABLE_SHIFT #undef SERDES_L2_TM_DIG_8_EYESURF_ENABLE_MASK -#define SERDES_L2_TM_DIG_8_EYESURF_ENABLE_DEFVAL 0x00000000 -#define SERDES_L2_TM_DIG_8_EYESURF_ENABLE_SHIFT 4 -#define SERDES_L2_TM_DIG_8_EYESURF_ENABLE_MASK 0x00000010U +#define SERDES_L2_TM_DIG_8_EYESURF_ENABLE_DEFVAL 0x00000000 +#define SERDES_L2_TM_DIG_8_EYESURF_ENABLE_SHIFT 4 +#define SERDES_L2_TM_DIG_8_EYESURF_ENABLE_MASK 0x00000010U -/*Enable Eye Surf*/ +/* +* Enable Eye Surf +*/ #undef SERDES_L3_TM_DIG_8_EYESURF_ENABLE_DEFVAL #undef SERDES_L3_TM_DIG_8_EYESURF_ENABLE_SHIFT #undef SERDES_L3_TM_DIG_8_EYESURF_ENABLE_MASK -#define SERDES_L3_TM_DIG_8_EYESURF_ENABLE_DEFVAL 0x00000000 -#define SERDES_L3_TM_DIG_8_EYESURF_ENABLE_SHIFT 4 -#define SERDES_L3_TM_DIG_8_EYESURF_ENABLE_MASK 0x00000010U +#define SERDES_L3_TM_DIG_8_EYESURF_ENABLE_DEFVAL 0x00000000 +#define SERDES_L3_TM_DIG_8_EYESURF_ENABLE_SHIFT 4 +#define SERDES_L3_TM_DIG_8_EYESURF_ENABLE_MASK 0x00000010U -/*ILL calib counts BYPASSED with calcode bits*/ +/* +* ILL calib counts BYPASSED with calcode bits +*/ #undef SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL #undef SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT #undef SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK -#define SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL 0x00000000 -#define SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT 7 -#define SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK 0x00000080U +#define SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL 0x00000000 +#define SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT 7 +#define SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK 0x00000080U -/*IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS*/ +/* +* IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , + * USB3 : SS +*/ #undef SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL #undef SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT #undef SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK -#define SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL 0x00000000 -#define SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT 0 -#define SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK 0x000000FFU +#define SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL 0x00000000 +#define SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT 0 +#define SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK 0x000000FFU -/*IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2*/ +/* +* IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 +*/ #undef SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL #undef SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT #undef SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK -#define SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL 0x00000000 -#define SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT 0 -#define SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK 0x000000FFU +#define SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL 0x00000000 +#define SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT 0 +#define SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK 0x000000FFU -/*G1A pll ctr bypass value*/ +/* +* G1A pll ctr bypass value +*/ #undef SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL #undef SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT #undef SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK -#define SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL 0x00000000 -#define SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT 0 -#define SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK 0x000000FFU +#define SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL 0x00000000 +#define SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT 0 +#define SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK 0x000000FFU -/*E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS*/ +/* +* E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , U + * SB3 : SS +*/ #undef SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL #undef SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT #undef SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK -#define SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL 0x00000000 -#define SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT 0 -#define SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK 0x000000FFU +#define SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL 0x00000000 +#define SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT 0 +#define SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK 0x000000FFU -/*E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2*/ +/* +* E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 +*/ #undef SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL #undef SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT #undef SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK -#define SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL 0x00000000 -#define SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT 0 -#define SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK 0x000000FFU +#define SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL 0x00000000 +#define SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT 0 +#define SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK 0x000000FFU -/*IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3*/ +/* +* IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 +*/ #undef SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL #undef SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT #undef SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK -#define SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL 0x00000000 -#define SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT 0 -#define SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK 0x000000FFU +#define SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL 0x00000000 +#define SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT 0 +#define SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK 0x000000FFU -/*E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3*/ +/* +* E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 +*/ #undef SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL #undef SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT #undef SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK -#define SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL 0x00000000 -#define SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT 0 -#define SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK 0x000000FFU +#define SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL 0x00000000 +#define SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT 0 +#define SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK 0x000000FFU -/*ILL calibration code change wait time*/ +/* +* ILL calibration code change wait time +*/ #undef SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL #undef SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT #undef SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_MASK -#define SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL 0x00000002 -#define SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT 0 -#define SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_MASK 0x000000FFU +#define SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL 0x00000002 +#define SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT 0 +#define SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_MASK 0x000000FFU -/*IQ ILL polytrim bypass value*/ +/* +* IQ ILL polytrim bypass value +*/ #undef SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL #undef SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT #undef SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK -#define SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL 0x00000000 -#define SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT 0 -#define SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK 0x000000FFU +#define SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL 0x00000000 +#define SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT 0 +#define SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK 0x000000FFU -/*bypass IQ polytrim*/ +/* +* bypass IQ polytrim +*/ #undef SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL #undef SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT #undef SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK -#define SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL 0x00000000 -#define SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT 0 -#define SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK 0x00000001U +#define SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL 0x00000000 +#define SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT 0 +#define SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK 0x00000001U -/*E ILL polytrim bypass value*/ +/* +* E ILL polytrim bypass value +*/ #undef SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL #undef SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT #undef SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK -#define SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL 0x00000000 -#define SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT 0 -#define SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK 0x000000FFU +#define SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL 0x00000000 +#define SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT 0 +#define SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK 0x000000FFU -/*bypass E polytrim*/ +/* +* bypass E polytrim +*/ #undef SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL #undef SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT #undef SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK -#define SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL 0x00000000 -#define SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT 0 -#define SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK 0x00000001U +#define SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL 0x00000000 +#define SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT 0 +#define SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK 0x00000001U -/*ILL calib counts BYPASSED with calcode bits*/ +/* +* ILL cal idle val refcnt +*/ +#undef SERDES_L0_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_DEFVAL +#undef SERDES_L0_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_SHIFT +#undef SERDES_L0_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_MASK +#define SERDES_L0_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_DEFVAL 0x00000001 +#define SERDES_L0_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_SHIFT 0 +#define SERDES_L0_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_MASK 0x00000007U + +/* +* ILL cal idle val refcnt +*/ +#undef SERDES_L1_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_DEFVAL +#undef SERDES_L1_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_SHIFT +#undef SERDES_L1_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_MASK +#define SERDES_L1_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_DEFVAL 0x00000001 +#define SERDES_L1_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_SHIFT 0 +#define SERDES_L1_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_MASK 0x00000007U + +/* +* ILL calib counts BYPASSED with calcode bits +*/ #undef SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL #undef SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT #undef SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK -#define SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL 0x00000000 -#define SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT 7 -#define SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK 0x00000080U +#define SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL 0x00000000 +#define SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT 7 +#define SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK 0x00000080U -/*IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS*/ +/* +* IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , + * USB3 : SS +*/ #undef SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL #undef SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT #undef SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK -#define SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL 0x00000000 -#define SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT 0 -#define SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK 0x000000FFU +#define SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL 0x00000000 +#define SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT 0 +#define SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK 0x000000FFU -/*IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2*/ +/* +* IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 +*/ #undef SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL #undef SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT #undef SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK -#define SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL 0x00000000 -#define SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT 0 -#define SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK 0x000000FFU +#define SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL 0x00000000 +#define SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT 0 +#define SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK 0x000000FFU -/*G1A pll ctr bypass value*/ +/* +* G1A pll ctr bypass value +*/ #undef SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL #undef SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT #undef SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK -#define SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL 0x00000000 -#define SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT 0 -#define SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK 0x000000FFU +#define SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL 0x00000000 +#define SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT 0 +#define SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK 0x000000FFU -/*E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS*/ +/* +* E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , U + * SB3 : SS +*/ #undef SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL #undef SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT #undef SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK -#define SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL 0x00000000 -#define SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT 0 -#define SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK 0x000000FFU +#define SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL 0x00000000 +#define SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT 0 +#define SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK 0x000000FFU -/*E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2*/ +/* +* E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 +*/ #undef SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL #undef SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT #undef SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK -#define SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL 0x00000000 -#define SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT 0 -#define SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK 0x000000FFU +#define SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL 0x00000000 +#define SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT 0 +#define SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK 0x000000FFU -/*IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3*/ +/* +* IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 +*/ #undef SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL #undef SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT #undef SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK -#define SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL 0x00000000 -#define SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT 0 -#define SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK 0x000000FFU +#define SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL 0x00000000 +#define SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT 0 +#define SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK 0x000000FFU -/*E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3*/ +/* +* E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 +*/ #undef SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL #undef SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT #undef SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK -#define SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL 0x00000000 -#define SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT 0 -#define SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK 0x000000FFU +#define SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL 0x00000000 +#define SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT 0 +#define SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK 0x000000FFU -/*ILL calibration code change wait time*/ +/* +* ILL calibration code change wait time +*/ #undef SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL #undef SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT #undef SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_MASK -#define SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL 0x00000002 -#define SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT 0 -#define SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_MASK 0x000000FFU +#define SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL 0x00000002 +#define SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT 0 +#define SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_MASK 0x000000FFU -/*IQ ILL polytrim bypass value*/ +/* +* IQ ILL polytrim bypass value +*/ #undef SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL #undef SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT #undef SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK -#define SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL 0x00000000 -#define SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT 0 -#define SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK 0x000000FFU +#define SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL 0x00000000 +#define SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT 0 +#define SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK 0x000000FFU -/*bypass IQ polytrim*/ +/* +* bypass IQ polytrim +*/ #undef SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL #undef SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT #undef SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK -#define SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL 0x00000000 -#define SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT 0 -#define SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK 0x00000001U +#define SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL 0x00000000 +#define SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT 0 +#define SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK 0x00000001U -/*E ILL polytrim bypass value*/ +/* +* E ILL polytrim bypass value +*/ #undef SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL #undef SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT #undef SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK -#define SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL 0x00000000 -#define SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT 0 -#define SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK 0x000000FFU +#define SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL 0x00000000 +#define SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT 0 +#define SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK 0x000000FFU -/*bypass E polytrim*/ +/* +* bypass E polytrim +*/ #undef SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL #undef SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT #undef SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK -#define SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL 0x00000000 -#define SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT 0 -#define SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK 0x00000001U +#define SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL 0x00000000 +#define SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT 0 +#define SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK 0x00000001U -/*ILL calib counts BYPASSED with calcode bits*/ +/* +* ILL cal idle val refcnt +*/ +#undef SERDES_L2_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_DEFVAL +#undef SERDES_L2_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_SHIFT +#undef SERDES_L2_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_MASK +#define SERDES_L2_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_DEFVAL 0x00000001 +#define SERDES_L2_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_SHIFT 0 +#define SERDES_L2_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_MASK 0x00000007U + +/* +* ILL calib counts BYPASSED with calcode bits +*/ #undef SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL #undef SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT #undef SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK -#define SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL 0x00000000 -#define SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT 7 -#define SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK 0x00000080U +#define SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL 0x00000000 +#define SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT 7 +#define SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK 0x00000080U -/*IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS*/ +/* +* IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , + * USB3 : SS +*/ #undef SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL #undef SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT #undef SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK -#define SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL 0x00000000 -#define SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT 0 -#define SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK 0x000000FFU +#define SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL 0x00000000 +#define SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT 0 +#define SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK 0x000000FFU -/*IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2*/ +/* +* IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 +*/ #undef SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL #undef SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT #undef SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK -#define SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL 0x00000000 -#define SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT 0 -#define SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK 0x000000FFU +#define SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL 0x00000000 +#define SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT 0 +#define SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK 0x000000FFU -/*G1A pll ctr bypass value*/ +/* +* G1A pll ctr bypass value +*/ #undef SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL #undef SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT #undef SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK -#define SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL 0x00000000 -#define SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT 0 -#define SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK 0x000000FFU +#define SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL 0x00000000 +#define SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT 0 +#define SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK 0x000000FFU -/*E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS*/ +/* +* E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , U + * SB3 : SS +*/ #undef SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL #undef SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT #undef SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK -#define SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL 0x00000000 -#define SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT 0 -#define SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK 0x000000FFU +#define SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL 0x00000000 +#define SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT 0 +#define SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK 0x000000FFU -/*E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2*/ +/* +* E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 +*/ #undef SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL #undef SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT #undef SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK -#define SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL 0x00000000 -#define SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT 0 -#define SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK 0x000000FFU +#define SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL 0x00000000 +#define SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT 0 +#define SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK 0x000000FFU -/*G2A_PCIe1 PLL ctr bypass value*/ +/* +* G2A_PCIe1 PLL ctr bypass value +*/ #undef SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_DEFVAL #undef SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_SHIFT #undef SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_MASK -#define SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_DEFVAL 0x00000000 -#define SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_SHIFT 4 -#define SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_MASK 0x000000F0U +#define SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_DEFVAL 0x00000000 +#define SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_SHIFT 4 +#define SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_MASK 0x000000F0U -/*IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3*/ +/* +* IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 +*/ #undef SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL #undef SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT #undef SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK -#define SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL 0x00000000 -#define SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT 0 -#define SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK 0x000000FFU +#define SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL 0x00000000 +#define SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT 0 +#define SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK 0x000000FFU -/*E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3*/ +/* +* E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 +*/ #undef SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL #undef SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT #undef SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK -#define SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL 0x00000000 -#define SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT 0 -#define SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK 0x000000FFU +#define SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL 0x00000000 +#define SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT 0 +#define SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK 0x000000FFU -/*ILL calibration code change wait time*/ +/* +* ILL calibration code change wait time +*/ #undef SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL #undef SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT #undef SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_MASK -#define SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL 0x00000002 -#define SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT 0 -#define SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_MASK 0x000000FFU +#define SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL 0x00000002 +#define SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT 0 +#define SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_MASK 0x000000FFU -/*IQ ILL polytrim bypass value*/ +/* +* IQ ILL polytrim bypass value +*/ #undef SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL #undef SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT #undef SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK -#define SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL 0x00000000 -#define SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT 0 -#define SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK 0x000000FFU +#define SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL 0x00000000 +#define SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT 0 +#define SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK 0x000000FFU -/*bypass IQ polytrim*/ +/* +* bypass IQ polytrim +*/ #undef SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL #undef SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT #undef SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK -#define SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL 0x00000000 -#define SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT 0 -#define SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK 0x00000001U +#define SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL 0x00000000 +#define SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT 0 +#define SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK 0x00000001U -/*E ILL polytrim bypass value*/ +/* +* E ILL polytrim bypass value +*/ #undef SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL #undef SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT #undef SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK -#define SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL 0x00000000 -#define SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT 0 -#define SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK 0x000000FFU +#define SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL 0x00000000 +#define SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT 0 +#define SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK 0x000000FFU -/*bypass E polytrim*/ +/* +* bypass E polytrim +*/ #undef SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL #undef SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT #undef SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK -#define SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL 0x00000000 -#define SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT 0 -#define SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK 0x00000001U +#define SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL 0x00000000 +#define SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT 0 +#define SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK 0x00000001U -/*pre lock comma count threshold. 2'b 00 : 3, 2'b 01 : 5, 2'b 10 : 10, 2'b 11 : 20*/ -#undef SERDES_L0_TM_DIG_21_COMMA_PRE_LOCK_THRESH_DEFVAL -#undef SERDES_L0_TM_DIG_21_COMMA_PRE_LOCK_THRESH_SHIFT -#undef SERDES_L0_TM_DIG_21_COMMA_PRE_LOCK_THRESH_MASK -#define SERDES_L0_TM_DIG_21_COMMA_PRE_LOCK_THRESH_DEFVAL 0x00000000 -#define SERDES_L0_TM_DIG_21_COMMA_PRE_LOCK_THRESH_SHIFT 0 -#define SERDES_L0_TM_DIG_21_COMMA_PRE_LOCK_THRESH_MASK 0x00000003U +/* +* ILL cal idle val refcnt +*/ +#undef SERDES_L3_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_DEFVAL +#undef SERDES_L3_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_SHIFT +#undef SERDES_L3_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_MASK +#define SERDES_L3_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_DEFVAL 0x00000001 +#define SERDES_L3_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_SHIFT 0 +#define SERDES_L3_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_MASK 0x00000007U -/*CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001*/ +/* +* CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001 +*/ #undef SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL #undef SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT #undef SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK -#define SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL 0x00000001 -#define SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT 0 -#define SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK 0x0000000FU +#define SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL 0x00000001 +#define SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT 0 +#define SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK 0x0000000FU -/*Delay apb reset by specified amount*/ +/* +* CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001 +*/ +#undef SERDES_L1_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL +#undef SERDES_L1_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT +#undef SERDES_L1_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK +#define SERDES_L1_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL 0x00000001 +#define SERDES_L1_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT 0 +#define SERDES_L1_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK 0x0000000FU + +/* +* CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001 +*/ +#undef SERDES_L2_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL +#undef SERDES_L2_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT +#undef SERDES_L2_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK +#define SERDES_L2_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL 0x00000001 +#define SERDES_L2_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT 0 +#define SERDES_L2_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK 0x0000000FU + +/* +* CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001 +*/ +#undef SERDES_L3_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL +#undef SERDES_L3_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT +#undef SERDES_L3_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK +#define SERDES_L3_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL 0x00000001 +#define SERDES_L3_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT 0 +#define SERDES_L3_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK 0x0000000FU + +/* +* Delay apb reset by specified amount +*/ #undef SERDES_L0_TM_RST_DLY_APB_RST_DLY_DEFVAL #undef SERDES_L0_TM_RST_DLY_APB_RST_DLY_SHIFT #undef SERDES_L0_TM_RST_DLY_APB_RST_DLY_MASK -#define SERDES_L0_TM_RST_DLY_APB_RST_DLY_DEFVAL 0x00000000 -#define SERDES_L0_TM_RST_DLY_APB_RST_DLY_SHIFT 0 -#define SERDES_L0_TM_RST_DLY_APB_RST_DLY_MASK 0x000000FFU +#define SERDES_L0_TM_RST_DLY_APB_RST_DLY_DEFVAL 0x00000000 +#define SERDES_L0_TM_RST_DLY_APB_RST_DLY_SHIFT 0 +#define SERDES_L0_TM_RST_DLY_APB_RST_DLY_MASK 0x000000FFU -/*Enable Bypass for <7> of TM_ANA_BYPS_15*/ +/* +* Enable Bypass for <7> of TM_ANA_BYPS_15 +*/ #undef SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL #undef SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT #undef SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK -#define SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL 0x00000000 -#define SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT 6 -#define SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK 0x00000040U +#define SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL 0x00000000 +#define SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT 6 +#define SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK 0x00000040U -/*Enable Bypass for <7> of TM_ANA_BYPS_12*/ +/* +* Enable Bypass for <7> of TM_ANA_BYPS_12 +*/ #undef SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL #undef SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT #undef SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK -#define SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL 0x00000000 -#define SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT 6 -#define SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK 0x00000040U +#define SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL 0x00000000 +#define SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT 6 +#define SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK 0x00000040U -/*Delay apb reset by specified amount*/ +/* +* Delay apb reset by specified amount +*/ #undef SERDES_L1_TM_RST_DLY_APB_RST_DLY_DEFVAL #undef SERDES_L1_TM_RST_DLY_APB_RST_DLY_SHIFT #undef SERDES_L1_TM_RST_DLY_APB_RST_DLY_MASK -#define SERDES_L1_TM_RST_DLY_APB_RST_DLY_DEFVAL 0x00000000 -#define SERDES_L1_TM_RST_DLY_APB_RST_DLY_SHIFT 0 -#define SERDES_L1_TM_RST_DLY_APB_RST_DLY_MASK 0x000000FFU +#define SERDES_L1_TM_RST_DLY_APB_RST_DLY_DEFVAL 0x00000000 +#define SERDES_L1_TM_RST_DLY_APB_RST_DLY_SHIFT 0 +#define SERDES_L1_TM_RST_DLY_APB_RST_DLY_MASK 0x000000FFU -/*Enable Bypass for <7> of TM_ANA_BYPS_15*/ +/* +* Enable Bypass for <7> of TM_ANA_BYPS_15 +*/ #undef SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL #undef SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT #undef SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK -#define SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL 0x00000000 -#define SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT 6 -#define SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK 0x00000040U +#define SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL 0x00000000 +#define SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT 6 +#define SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK 0x00000040U -/*Enable Bypass for <7> of TM_ANA_BYPS_12*/ +/* +* Enable Bypass for <7> of TM_ANA_BYPS_12 +*/ #undef SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL #undef SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT #undef SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK -#define SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL 0x00000000 -#define SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT 6 -#define SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK 0x00000040U +#define SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL 0x00000000 +#define SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT 6 +#define SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK 0x00000040U -/*Delay apb reset by specified amount*/ +/* +* Delay apb reset by specified amount +*/ #undef SERDES_L2_TM_RST_DLY_APB_RST_DLY_DEFVAL #undef SERDES_L2_TM_RST_DLY_APB_RST_DLY_SHIFT #undef SERDES_L2_TM_RST_DLY_APB_RST_DLY_MASK -#define SERDES_L2_TM_RST_DLY_APB_RST_DLY_DEFVAL 0x00000000 -#define SERDES_L2_TM_RST_DLY_APB_RST_DLY_SHIFT 0 -#define SERDES_L2_TM_RST_DLY_APB_RST_DLY_MASK 0x000000FFU +#define SERDES_L2_TM_RST_DLY_APB_RST_DLY_DEFVAL 0x00000000 +#define SERDES_L2_TM_RST_DLY_APB_RST_DLY_SHIFT 0 +#define SERDES_L2_TM_RST_DLY_APB_RST_DLY_MASK 0x000000FFU -/*Enable Bypass for <7> of TM_ANA_BYPS_15*/ +/* +* Enable Bypass for <7> of TM_ANA_BYPS_15 +*/ #undef SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL #undef SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT #undef SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK -#define SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL 0x00000000 -#define SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT 6 -#define SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK 0x00000040U +#define SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL 0x00000000 +#define SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT 6 +#define SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK 0x00000040U -/*Enable Bypass for <7> of TM_ANA_BYPS_12*/ +/* +* Enable Bypass for <7> of TM_ANA_BYPS_12 +*/ #undef SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL #undef SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT #undef SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK -#define SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL 0x00000000 -#define SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT 6 -#define SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK 0x00000040U +#define SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL 0x00000000 +#define SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT 6 +#define SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK 0x00000040U -/*Delay apb reset by specified amount*/ +/* +* Delay apb reset by specified amount +*/ #undef SERDES_L3_TM_RST_DLY_APB_RST_DLY_DEFVAL #undef SERDES_L3_TM_RST_DLY_APB_RST_DLY_SHIFT #undef SERDES_L3_TM_RST_DLY_APB_RST_DLY_MASK -#define SERDES_L3_TM_RST_DLY_APB_RST_DLY_DEFVAL 0x00000000 -#define SERDES_L3_TM_RST_DLY_APB_RST_DLY_SHIFT 0 -#define SERDES_L3_TM_RST_DLY_APB_RST_DLY_MASK 0x000000FFU +#define SERDES_L3_TM_RST_DLY_APB_RST_DLY_DEFVAL 0x00000000 +#define SERDES_L3_TM_RST_DLY_APB_RST_DLY_SHIFT 0 +#define SERDES_L3_TM_RST_DLY_APB_RST_DLY_MASK 0x000000FFU -/*Enable Bypass for <7> of TM_ANA_BYPS_15*/ +/* +* Enable Bypass for <7> of TM_ANA_BYPS_15 +*/ #undef SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL #undef SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT #undef SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK -#define SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL 0x00000000 -#define SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT 6 -#define SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK 0x00000040U +#define SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL 0x00000000 +#define SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT 6 +#define SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK 0x00000040U -/*Enable Bypass for <7> of TM_ANA_BYPS_12*/ +/* +* Enable Bypass for <7> of TM_ANA_BYPS_12 +*/ #undef SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL #undef SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT #undef SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK -#define SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL 0x00000000 -#define SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT 6 -#define SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK 0x00000040U +#define SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL 0x00000000 +#define SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT 6 +#define SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK 0x00000040U -/*Controls UPHY Lane 0 protocol configuration. 0 - PowerDown, 1 - PCIe .0, 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII0, 6 - Unuse - , 7 - Unused*/ +/* +* CDR fast phase lock control +*/ +#undef SERDES_L0_TM_MISC3_CDR_EN_FPL_DEFVAL +#undef SERDES_L0_TM_MISC3_CDR_EN_FPL_SHIFT +#undef SERDES_L0_TM_MISC3_CDR_EN_FPL_MASK +#define SERDES_L0_TM_MISC3_CDR_EN_FPL_DEFVAL 0x00000003 +#define SERDES_L0_TM_MISC3_CDR_EN_FPL_SHIFT 1 +#define SERDES_L0_TM_MISC3_CDR_EN_FPL_MASK 0x00000002U + +/* +* CDR fast frequency lock control +*/ +#undef SERDES_L0_TM_MISC3_CDR_EN_FFL_DEFVAL +#undef SERDES_L0_TM_MISC3_CDR_EN_FFL_SHIFT +#undef SERDES_L0_TM_MISC3_CDR_EN_FFL_MASK +#define SERDES_L0_TM_MISC3_CDR_EN_FFL_DEFVAL 0x00000003 +#define SERDES_L0_TM_MISC3_CDR_EN_FFL_SHIFT 0 +#define SERDES_L0_TM_MISC3_CDR_EN_FFL_MASK 0x00000001U + +/* +* CDR fast phase lock control +*/ +#undef SERDES_L1_TM_MISC3_CDR_EN_FPL_DEFVAL +#undef SERDES_L1_TM_MISC3_CDR_EN_FPL_SHIFT +#undef SERDES_L1_TM_MISC3_CDR_EN_FPL_MASK +#define SERDES_L1_TM_MISC3_CDR_EN_FPL_DEFVAL 0x00000003 +#define SERDES_L1_TM_MISC3_CDR_EN_FPL_SHIFT 1 +#define SERDES_L1_TM_MISC3_CDR_EN_FPL_MASK 0x00000002U + +/* +* CDR fast frequency lock control +*/ +#undef SERDES_L1_TM_MISC3_CDR_EN_FFL_DEFVAL +#undef SERDES_L1_TM_MISC3_CDR_EN_FFL_SHIFT +#undef SERDES_L1_TM_MISC3_CDR_EN_FFL_MASK +#define SERDES_L1_TM_MISC3_CDR_EN_FFL_DEFVAL 0x00000003 +#define SERDES_L1_TM_MISC3_CDR_EN_FFL_SHIFT 0 +#define SERDES_L1_TM_MISC3_CDR_EN_FFL_MASK 0x00000001U + +/* +* CDR fast phase lock control +*/ +#undef SERDES_L2_TM_MISC3_CDR_EN_FPL_DEFVAL +#undef SERDES_L2_TM_MISC3_CDR_EN_FPL_SHIFT +#undef SERDES_L2_TM_MISC3_CDR_EN_FPL_MASK +#define SERDES_L2_TM_MISC3_CDR_EN_FPL_DEFVAL 0x00000003 +#define SERDES_L2_TM_MISC3_CDR_EN_FPL_SHIFT 1 +#define SERDES_L2_TM_MISC3_CDR_EN_FPL_MASK 0x00000002U + +/* +* CDR fast frequency lock control +*/ +#undef SERDES_L2_TM_MISC3_CDR_EN_FFL_DEFVAL +#undef SERDES_L2_TM_MISC3_CDR_EN_FFL_SHIFT +#undef SERDES_L2_TM_MISC3_CDR_EN_FFL_MASK +#define SERDES_L2_TM_MISC3_CDR_EN_FFL_DEFVAL 0x00000003 +#define SERDES_L2_TM_MISC3_CDR_EN_FFL_SHIFT 0 +#define SERDES_L2_TM_MISC3_CDR_EN_FFL_MASK 0x00000001U + +/* +* CDR fast phase lock control +*/ +#undef SERDES_L3_TM_MISC3_CDR_EN_FPL_DEFVAL +#undef SERDES_L3_TM_MISC3_CDR_EN_FPL_SHIFT +#undef SERDES_L3_TM_MISC3_CDR_EN_FPL_MASK +#define SERDES_L3_TM_MISC3_CDR_EN_FPL_DEFVAL 0x00000003 +#define SERDES_L3_TM_MISC3_CDR_EN_FPL_SHIFT 1 +#define SERDES_L3_TM_MISC3_CDR_EN_FPL_MASK 0x00000002U + +/* +* CDR fast frequency lock control +*/ +#undef SERDES_L3_TM_MISC3_CDR_EN_FFL_DEFVAL +#undef SERDES_L3_TM_MISC3_CDR_EN_FFL_SHIFT +#undef SERDES_L3_TM_MISC3_CDR_EN_FFL_MASK +#define SERDES_L3_TM_MISC3_CDR_EN_FFL_DEFVAL 0x00000003 +#define SERDES_L3_TM_MISC3_CDR_EN_FFL_SHIFT 0 +#define SERDES_L3_TM_MISC3_CDR_EN_FFL_MASK 0x00000001U + +/* +* Force EQ offset correction algo off if not forced on +*/ +#undef SERDES_L0_TM_EQ11_FORCE_EQ_OFFS_OFF_DEFVAL +#undef SERDES_L0_TM_EQ11_FORCE_EQ_OFFS_OFF_SHIFT +#undef SERDES_L0_TM_EQ11_FORCE_EQ_OFFS_OFF_MASK +#define SERDES_L0_TM_EQ11_FORCE_EQ_OFFS_OFF_DEFVAL 0x00000000 +#define SERDES_L0_TM_EQ11_FORCE_EQ_OFFS_OFF_SHIFT 4 +#define SERDES_L0_TM_EQ11_FORCE_EQ_OFFS_OFF_MASK 0x00000010U + +/* +* Force EQ offset correction algo off if not forced on +*/ +#undef SERDES_L1_TM_EQ11_FORCE_EQ_OFFS_OFF_DEFVAL +#undef SERDES_L1_TM_EQ11_FORCE_EQ_OFFS_OFF_SHIFT +#undef SERDES_L1_TM_EQ11_FORCE_EQ_OFFS_OFF_MASK +#define SERDES_L1_TM_EQ11_FORCE_EQ_OFFS_OFF_DEFVAL 0x00000000 +#define SERDES_L1_TM_EQ11_FORCE_EQ_OFFS_OFF_SHIFT 4 +#define SERDES_L1_TM_EQ11_FORCE_EQ_OFFS_OFF_MASK 0x00000010U + +/* +* Force EQ offset correction algo off if not forced on +*/ +#undef SERDES_L2_TM_EQ11_FORCE_EQ_OFFS_OFF_DEFVAL +#undef SERDES_L2_TM_EQ11_FORCE_EQ_OFFS_OFF_SHIFT +#undef SERDES_L2_TM_EQ11_FORCE_EQ_OFFS_OFF_MASK +#define SERDES_L2_TM_EQ11_FORCE_EQ_OFFS_OFF_DEFVAL 0x00000000 +#define SERDES_L2_TM_EQ11_FORCE_EQ_OFFS_OFF_SHIFT 4 +#define SERDES_L2_TM_EQ11_FORCE_EQ_OFFS_OFF_MASK 0x00000010U + +/* +* Force EQ offset correction algo off if not forced on +*/ +#undef SERDES_L3_TM_EQ11_FORCE_EQ_OFFS_OFF_DEFVAL +#undef SERDES_L3_TM_EQ11_FORCE_EQ_OFFS_OFF_SHIFT +#undef SERDES_L3_TM_EQ11_FORCE_EQ_OFFS_OFF_MASK +#define SERDES_L3_TM_EQ11_FORCE_EQ_OFFS_OFF_DEFVAL 0x00000000 +#define SERDES_L3_TM_EQ11_FORCE_EQ_OFFS_OFF_SHIFT 4 +#define SERDES_L3_TM_EQ11_FORCE_EQ_OFFS_OFF_MASK 0x00000010U + +/* +* For future use +*/ +#undef SIOU_ECO_0_FIELD_DEFVAL +#undef SIOU_ECO_0_FIELD_SHIFT +#undef SIOU_ECO_0_FIELD_MASK +#define SIOU_ECO_0_FIELD_DEFVAL +#define SIOU_ECO_0_FIELD_SHIFT 0 +#define SIOU_ECO_0_FIELD_MASK 0xFFFFFFFFU + +/* +* Controls UPHY Lane 0 protocol configuration. 0 - PowerDown, 1 - PCIe .0, + * 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII0, 6 - Unused, 7 - Unused +*/ #undef SERDES_ICM_CFG0_L0_ICM_CFG_DEFVAL #undef SERDES_ICM_CFG0_L0_ICM_CFG_SHIFT #undef SERDES_ICM_CFG0_L0_ICM_CFG_MASK -#define SERDES_ICM_CFG0_L0_ICM_CFG_DEFVAL 0x00000000 -#define SERDES_ICM_CFG0_L0_ICM_CFG_SHIFT 0 -#define SERDES_ICM_CFG0_L0_ICM_CFG_MASK 0x00000007U +#define SERDES_ICM_CFG0_L0_ICM_CFG_DEFVAL 0x00000000 +#define SERDES_ICM_CFG0_L0_ICM_CFG_SHIFT 0 +#define SERDES_ICM_CFG0_L0_ICM_CFG_MASK 0x00000007U -/*Controls UPHY Lane 1 protocol configuration. 0 - PowerDown, 1 - PCIe.1, 2 - Sata1, 3 - USB0, 4 - DP.0, 5 - SGMII1, 6 - Unused - 7 - Unused*/ +/* +* Controls UPHY Lane 1 protocol configuration. 0 - PowerDown, 1 - PCIe.1, + * 2 - Sata1, 3 - USB0, 4 - DP.0, 5 - SGMII1, 6 - Unused, 7 - Unused +*/ #undef SERDES_ICM_CFG0_L1_ICM_CFG_DEFVAL #undef SERDES_ICM_CFG0_L1_ICM_CFG_SHIFT #undef SERDES_ICM_CFG0_L1_ICM_CFG_MASK -#define SERDES_ICM_CFG0_L1_ICM_CFG_DEFVAL 0x00000000 -#define SERDES_ICM_CFG0_L1_ICM_CFG_SHIFT 4 -#define SERDES_ICM_CFG0_L1_ICM_CFG_MASK 0x00000070U +#define SERDES_ICM_CFG0_L1_ICM_CFG_DEFVAL 0x00000000 +#define SERDES_ICM_CFG0_L1_ICM_CFG_SHIFT 4 +#define SERDES_ICM_CFG0_L1_ICM_CFG_MASK 0x00000070U -/*Controls UPHY Lane 2 protocol configuration. 0 - PowerDown, 1 - PCIe.1, 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII2, 6 - Unused - 7 - Unused*/ +/* +* Controls UPHY Lane 2 protocol configuration. 0 - PowerDown, 1 - PCIe.1, + * 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII2, 6 - Unused, 7 - Unused +*/ #undef SERDES_ICM_CFG1_L2_ICM_CFG_DEFVAL #undef SERDES_ICM_CFG1_L2_ICM_CFG_SHIFT #undef SERDES_ICM_CFG1_L2_ICM_CFG_MASK -#define SERDES_ICM_CFG1_L2_ICM_CFG_DEFVAL 0x00000000 -#define SERDES_ICM_CFG1_L2_ICM_CFG_SHIFT 0 -#define SERDES_ICM_CFG1_L2_ICM_CFG_MASK 0x00000007U +#define SERDES_ICM_CFG1_L2_ICM_CFG_DEFVAL 0x00000000 +#define SERDES_ICM_CFG1_L2_ICM_CFG_SHIFT 0 +#define SERDES_ICM_CFG1_L2_ICM_CFG_MASK 0x00000007U -/*Controls UPHY Lane 3 protocol configuration. 0 - PowerDown, 1 - PCIe.3, 2 - Sata1, 3 - USB1, 4 - DP.0, 5 - SGMII3, 6 - Unused - 7 - Unused*/ +/* +* Controls UPHY Lane 3 protocol configuration. 0 - PowerDown, 1 - PCIe.3, + * 2 - Sata1, 3 - USB1, 4 - DP.0, 5 - SGMII3, 6 - Unused, 7 - Unused +*/ #undef SERDES_ICM_CFG1_L3_ICM_CFG_DEFVAL #undef SERDES_ICM_CFG1_L3_ICM_CFG_SHIFT #undef SERDES_ICM_CFG1_L3_ICM_CFG_MASK -#define SERDES_ICM_CFG1_L3_ICM_CFG_DEFVAL 0x00000000 -#define SERDES_ICM_CFG1_L3_ICM_CFG_SHIFT 4 -#define SERDES_ICM_CFG1_L3_ICM_CFG_MASK 0x00000070U +#define SERDES_ICM_CFG1_L3_ICM_CFG_DEFVAL 0x00000000 +#define SERDES_ICM_CFG1_L3_ICM_CFG_SHIFT 4 +#define SERDES_ICM_CFG1_L3_ICM_CFG_MASK 0x00000070U -/*Enable/disable DP post2 path*/ +/* +* Enable/disable DP post2 path +*/ #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_DEFVAL #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_SHIFT #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_MASK -#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_DEFVAL 0x00000000 -#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_SHIFT 5 -#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_MASK 0x00000020U +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_DEFVAL 0x00000000 +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_SHIFT 5 +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_MASK 0x00000020U -/*Override enable/disable of DP post2 path*/ +/* +* Override enable/disable of DP post2 path +*/ #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_DEFVAL #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_SHIFT #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_MASK -#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_DEFVAL 0x00000000 -#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_SHIFT 4 -#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_MASK 0x00000010U +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_DEFVAL 0x00000000 +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_SHIFT 4 +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_MASK 0x00000010U -/*Override enable/disable of DP post1 path*/ +/* +* Override enable/disable of DP post1 path +*/ #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_DEFVAL #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_SHIFT #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_MASK -#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_DEFVAL 0x00000000 -#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_SHIFT 2 -#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_MASK 0x00000004U +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_DEFVAL 0x00000000 +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_SHIFT 2 +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_MASK 0x00000004U -/*Enable/disable DP main path*/ +/* +* Enable/disable DP main path +*/ #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_DEFVAL #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_SHIFT #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_MASK -#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_DEFVAL 0x00000000 -#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_SHIFT 1 -#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_MASK 0x00000002U +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_DEFVAL 0x00000000 +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_SHIFT 1 +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_MASK 0x00000002U -/*Override enable/disable of DP main path*/ +/* +* Override enable/disable of DP main path +*/ #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_DEFVAL #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_SHIFT #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_MASK -#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_DEFVAL 0x00000000 -#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_SHIFT 0 -#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_MASK 0x00000001U +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_DEFVAL 0x00000000 +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_SHIFT 0 +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_MASK 0x00000001U -/*Test register force for enabling/disablign TX deemphasis bits <17:0>*/ +/* +* Test register force for enabling/disablign TX deemphasis bits <17:0> +*/ #undef SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_DEFVAL #undef SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT #undef SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK -#define SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_DEFVAL 0x00000000 -#define SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT 0 -#define SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK 0x00000001U +#define SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_DEFVAL 0x00000000 +#define SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT 0 +#define SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK 0x00000001U -/*Test register force for enabling/disablign TX deemphasis bits <17:0>*/ +/* +* Test register force for enabling/disablign TX deemphasis bits <17:0> +*/ #undef SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_DEFVAL #undef SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT #undef SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK -#define SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_DEFVAL 0x00000000 -#define SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT 0 -#define SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK 0x00000001U +#define SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_DEFVAL 0x00000000 +#define SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT 0 +#define SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK 0x00000001U -/*FPHL FSM accumulate cycles*/ +/* +* FPHL FSM accumulate cycles +*/ #undef SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_DEFVAL #undef SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_SHIFT #undef SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_MASK -#define SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_DEFVAL 0x00000000 -#define SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_SHIFT 5 -#define SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_MASK 0x000000E0U +#define SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_DEFVAL 0x00000000 +#define SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_SHIFT 5 +#define SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_MASK 0x000000E0U -/*FFL Phase0 int gain aka 2ol SD update rate*/ +/* +* FFL Phase0 int gain aka 2ol SD update rate +*/ #undef SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_DEFVAL #undef SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_SHIFT #undef SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_MASK -#define SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_DEFVAL 0x00000000 -#define SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_SHIFT 0 -#define SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_MASK 0x0000001FU +#define SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_DEFVAL 0x00000000 +#define SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_SHIFT 0 +#define SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_MASK 0x0000001FU -/*FFL Phase0 prop gain aka 1ol SD update rate*/ +/* +* FFL Phase0 prop gain aka 1ol SD update rate +*/ #undef SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_DEFVAL #undef SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_SHIFT #undef SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_MASK -#define SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_DEFVAL 0x00000000 -#define SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_SHIFT 0 -#define SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_MASK 0x0000001FU +#define SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_DEFVAL 0x00000000 +#define SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_SHIFT 0 +#define SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_MASK 0x0000001FU -/*EQ stg 2 controls BYPASSED*/ +/* +* EQ stg 2 controls BYPASSED +*/ #undef SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_DEFVAL #undef SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_SHIFT #undef SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_MASK -#define SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_DEFVAL 0x00000000 -#define SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_SHIFT 5 -#define SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_MASK 0x00000020U +#define SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_DEFVAL 0x00000000 +#define SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_SHIFT 5 +#define SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_MASK 0x00000020U -/*EQ STG2 RL PROG*/ +/* +* EQ STG2 RL PROG +*/ #undef SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_DEFVAL #undef SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_SHIFT #undef SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_MASK -#define SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_DEFVAL 0x00000000 -#define SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_SHIFT 0 -#define SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_MASK 0x00000003U +#define SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_DEFVAL 0x00000000 +#define SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_SHIFT 0 +#define SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_MASK 0x00000003U -/*EQ stg 2 preamp mode val*/ +/* +* EQ stg 2 preamp mode val +*/ #undef SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_DEFVAL #undef SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_SHIFT #undef SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_MASK -#define SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_DEFVAL 0x00000000 -#define SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_SHIFT 2 -#define SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_MASK 0x00000004U +#define SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_DEFVAL 0x00000000 +#define SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_SHIFT 2 +#define SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_MASK 0x00000004U -/*Margining factor value*/ +/* +* Margining factor value +*/ #undef SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_DEFVAL #undef SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_SHIFT #undef SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_MASK -#define SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_DEFVAL 0x00000000 -#define SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_SHIFT 0 -#define SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_MASK 0x0000001FU +#define SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_DEFVAL 0x00000000 +#define SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_SHIFT 0 +#define SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_MASK 0x0000001FU -/*pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-emphasis, Others: reserved*/ +/* +* pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-em + * phasis, Others: reserved +*/ #undef SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_DEFVAL #undef SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT #undef SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK -#define SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_DEFVAL 0x00000002 -#define SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT 0 -#define SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK 0x000000FFU +#define SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_DEFVAL 0x00000002 +#define SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT 0 +#define SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK 0x000000FFU -/*pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-emphasis, Others: reserved*/ +/* +* pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-em + * phasis, Others: reserved +*/ #undef SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_DEFVAL #undef SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT #undef SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK -#define SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_DEFVAL 0x00000002 -#define SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT 0 -#define SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK 0x000000FFU +#define SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_DEFVAL 0x00000002 +#define SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT 0 +#define SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK 0x000000FFU #undef CRL_APB_RST_LPD_TOP_OFFSET #define CRL_APB_RST_LPD_TOP_OFFSET 0XFF5E023C -#undef USB3_0_FPD_POWER_PRSNT_OFFSET -#define USB3_0_FPD_POWER_PRSNT_OFFSET 0XFF9D0080 -#undef USB3_0_FPD_PIPE_CLK_OFFSET -#define USB3_0_FPD_PIPE_CLK_OFFSET 0XFF9D007C #undef CRL_APB_RST_LPD_TOP_OFFSET #define CRL_APB_RST_LPD_TOP_OFFSET 0XFF5E023C #undef CRL_APB_RST_LPD_IOU0_OFFSET @@ -26548,6 +34559,10 @@ #define USB3_0_XHCI_GUSB2PHYCFG_OFFSET 0XFE20C200 #undef USB3_0_XHCI_GFLADJ_OFFSET #define USB3_0_XHCI_GFLADJ_OFFSET 0XFE20C630 +#undef USB3_0_XHCI_GUCTL1_OFFSET +#define USB3_0_XHCI_GUCTL1_OFFSET 0XFE20C11C +#undef USB3_0_XHCI_GUCTL_OFFSET +#define USB3_0_XHCI_GUCTL_OFFSET 0XFE20C12C #undef PCIE_ATTRIB_ATTR_25_OFFSET #define PCIE_ATTRIB_ATTR_25_OFFSET 0XFD480064 #undef PCIE_ATTRIB_ATTR_7_OFFSET @@ -26638,6 +34653,8 @@ #define PCIE_ATTRIB_ATTR_35_OFFSET 0XFD48008C #undef CRF_APB_RST_FPD_TOP_OFFSET #define CRF_APB_RST_FPD_TOP_OFFSET 0XFD1A0100 +#undef GPIO_MASK_DATA_1_LSW_OFFSET +#define GPIO_MASK_DATA_1_LSW_OFFSET 0XFF0A0008 #undef SATA_AHCI_VENDOR_PP2C_OFFSET #define SATA_AHCI_VENDOR_PP2C_OFFSET 0XFD0C00AC #undef SATA_AHCI_VENDOR_PP3C_OFFSET @@ -26647,1015 +34664,1462 @@ #undef SATA_AHCI_VENDOR_PP5C_OFFSET #define SATA_AHCI_VENDOR_PP5C_OFFSET 0XFD0C00B8 -/*USB 0 reset for control registers*/ +/* +* USB 0 reset for control registers +*/ #undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL #undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT #undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK -#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL 0x00188FDF -#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT 10 -#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK 0x00000400U +#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT 10 +#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK 0x00000400U -/*This bit is used to choose between PIPE power present and 1'b1*/ -#undef USB3_0_FPD_POWER_PRSNT_OPTION_DEFVAL -#undef USB3_0_FPD_POWER_PRSNT_OPTION_SHIFT -#undef USB3_0_FPD_POWER_PRSNT_OPTION_MASK -#define USB3_0_FPD_POWER_PRSNT_OPTION_DEFVAL -#define USB3_0_FPD_POWER_PRSNT_OPTION_SHIFT 0 -#define USB3_0_FPD_POWER_PRSNT_OPTION_MASK 0x00000001U - -/*This bit is used to choose between PIPE clock coming from SerDes and the suspend clk*/ -#undef USB3_0_FPD_PIPE_CLK_OPTION_DEFVAL -#undef USB3_0_FPD_PIPE_CLK_OPTION_SHIFT -#undef USB3_0_FPD_PIPE_CLK_OPTION_MASK -#define USB3_0_FPD_PIPE_CLK_OPTION_DEFVAL -#define USB3_0_FPD_PIPE_CLK_OPTION_SHIFT 0 -#define USB3_0_FPD_PIPE_CLK_OPTION_MASK 0x00000001U - -/*USB 0 sleep circuit reset*/ +/* +* USB 0 sleep circuit reset +*/ #undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL #undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT #undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK -#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL 0x00188FDF -#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT 8 -#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK 0x00000100U +#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT 8 +#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK 0x00000100U -/*USB 0 reset*/ +/* +* USB 0 reset +*/ #undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL #undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT #undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK -#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL 0x00188FDF -#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT 6 -#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK 0x00000040U +#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT 6 +#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK 0x00000040U -/*GEM 3 reset*/ +/* +* GEM 3 reset +*/ #undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL #undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT #undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK -#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL 0x0000000F -#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT 3 -#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK 0x00000008U +#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL 0x0000000F +#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT 3 +#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK 0x00000008U -/*Sata PM clock control select*/ +/* +* Sata PM clock control select +*/ #undef SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_DEFVAL #undef SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_SHIFT #undef SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_MASK -#define SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_DEFVAL -#define SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_SHIFT 0 -#define SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_MASK 0x00000003U +#define SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_DEFVAL +#define SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_SHIFT 0 +#define SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_MASK 0x00000003U -/*Sata block level reset*/ +/* +* Sata block level reset +*/ #undef CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL #undef CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT #undef CRF_APB_RST_FPD_TOP_SATA_RESET_MASK -#define CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL 0x000F9FFE -#define CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT 1 -#define CRF_APB_RST_FPD_TOP_SATA_RESET_MASK 0x00000002U +#define CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT 1 +#define CRF_APB_RST_FPD_TOP_SATA_RESET_MASK 0x00000002U -/*PCIE config reset*/ +/* +* PCIE config reset +*/ #undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL #undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT #undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK -#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL 0x000F9FFE -#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT 19 -#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK 0x00080000U +#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT 19 +#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK 0x00080000U -/*PCIE bridge block level reset (AXI interface)*/ +/* +* PCIE bridge block level reset (AXI interface) +*/ #undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL #undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT #undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK -#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL 0x000F9FFE -#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT 18 -#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK 0x00040000U +#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT 18 +#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK 0x00040000U -/*Display Port block level reset (includes DPDMA)*/ +/* +* Display Port block level reset (includes DPDMA) +*/ #undef CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL #undef CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT #undef CRF_APB_RST_FPD_TOP_DP_RESET_MASK -#define CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL 0x000F9FFE -#define CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT 16 -#define CRF_APB_RST_FPD_TOP_DP_RESET_MASK 0x00010000U +#define CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT 16 +#define CRF_APB_RST_FPD_TOP_DP_RESET_MASK 0x00010000U -/*Set to '1' to hold the GT in reset. Clear to release.*/ +/* +* Set to '1' to hold the GT in reset. Clear to release. +*/ #undef DP_DP_PHY_RESET_GT_RESET_DEFVAL #undef DP_DP_PHY_RESET_GT_RESET_SHIFT #undef DP_DP_PHY_RESET_GT_RESET_MASK -#define DP_DP_PHY_RESET_GT_RESET_DEFVAL 0x00010003 -#define DP_DP_PHY_RESET_GT_RESET_SHIFT 1 -#define DP_DP_PHY_RESET_GT_RESET_MASK 0x00000002U +#define DP_DP_PHY_RESET_GT_RESET_DEFVAL 0x00010003 +#define DP_DP_PHY_RESET_GT_RESET_SHIFT 1 +#define DP_DP_PHY_RESET_GT_RESET_MASK 0x00000002U -/*Two bits per lane. When set to 11, moves the GT to power down mode. When set to 00, GT will be in active state. bits [1:0] - - ane0 Bits [3:2] - lane 1*/ +/* +* Two bits per lane. When set to 11, moves the GT to power down mode. When + * set to 00, GT will be in active state. bits [1:0] - lane0 Bits [3:2] - + * lane 1 +*/ #undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_DEFVAL #undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT #undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK -#define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_DEFVAL 0x00000000 -#define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT 0 -#define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK 0x0000000FU +#define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_DEFVAL 0x00000000 +#define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT 0 +#define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK 0x0000000FU -/*USB 2.0 Turnaround Time (USBTrdTim) Sets the turnaround time in PHY clocks. Specifies the response time for a MAC request to - he Packet FIFO Controller (PFC) to fetch data from the DFIFO (SPRAM). The following are the required values for the minimum S - C bus frequency of 60 MHz. USB turnaround time is a critical certification criteria when using long cables and five hub level - . The required values for this field: - 4'h5: When the MAC interface is 16-bit UTMI+. - 4'h9: When the MAC interface is 8-bit - UTMI+/ULPI. If SoC bus clock is less than 60 MHz, and USB turnaround time is not critical, this field can be set to a larger - alue. Note: This field is valid only in device mode.*/ +/* +* USB 2.0 Turnaround Time (USBTrdTim) Sets the turnaround time in PHY cloc + * ks. Specifies the response time for a MAC request to the Packet FIFO Con + * troller (PFC) to fetch data from the DFIFO (SPRAM). The following are th + * e required values for the minimum SoC bus frequency of 60 MHz. USB turna + * round time is a critical certification criteria when using long cables a + * nd five hub levels. The required values for this field: - 4'h5: When the + * MAC interface is 16-bit UTMI+. - 4'h9: When the MAC interface is 8-bit + * UTMI+/ULPI. If SoC bus clock is less than 60 MHz, and USB turnaround tim + * e is not critical, this field can be set to a larger value. Note: This f + * ield is valid only in device mode. +*/ #undef USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_DEFVAL #undef USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_SHIFT #undef USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_MASK -#define USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_DEFVAL 0x00000000 -#define USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_SHIFT 10 -#define USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_MASK 0x00003C00U +#define USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_DEFVAL 0x00000000 +#define USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_SHIFT 10 +#define USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_MASK 0x00003C00U -/*Transceiver Delay: Enables a delay between the assertion of the UTMI/ULPI Transceiver Select signal (for HS) and the assertio - of the TxValid signal during a HS Chirp. When this bit is set to 1, a delay (of approximately 2.5 us) is introduced from the - time when the Transceiver Select is set to 2'b00 (HS) to the time the TxValid is driven to 0 for sending the chirp-K. This de - ay is required for some UTMI/ULPI PHYs. Note: - If you enable the hibernation feature when the device core comes out of power - off, you must re-initialize this bit with the appropriate value because the core does not save and restore this bit value dur - ng hibernation. - This bit is valid only in device mode.*/ +/* +* Transceiver Delay: Enables a delay between the assertion of the UTMI/ULP + * I Transceiver Select signal (for HS) and the assertion of the TxValid si + * gnal during a HS Chirp. When this bit is set to 1, a delay (of approxima + * tely 2.5 us) is introduced from the time when the Transceiver Select is + * set to 2'b00 (HS) to the time the TxValid is driven to 0 for sending the + * chirp-K. This delay is required for some UTMI/ULPI PHYs. Note: - If you + * enable the hibernation feature when the device core comes out of power- + * off, you must re-initialize this bit with the appropriate value because + * the core does not save and restore this bit value during hibernation. - + * This bit is valid only in device mode. +*/ #undef USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_DEFVAL #undef USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_SHIFT #undef USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_MASK -#define USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_DEFVAL 0x00000000 -#define USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_SHIFT 9 -#define USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_MASK 0x00000200U +#define USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_DEFVAL 0x00000000 +#define USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_SHIFT 9 +#define USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_MASK 0x00000200U -/*Enable utmi_sleep_n and utmi_l1_suspend_n (EnblSlpM) The application uses this bit to control utmi_sleep_n and utmi_l1_suspen - _n assertion to the PHY in the L1 state. - 1'b0: utmi_sleep_n and utmi_l1_suspend_n assertion from the core is not transferre - to the external PHY. - 1'b1: utmi_sleep_n and utmi_l1_suspend_n assertion from the core is transferred to the external PHY. - ote: This bit must be set high for Port0 if PHY is used. Note: In Device mode - Before issuing any device endpoint command wh - n operating in 2.0 speeds, disable this bit and enable it after the command completes. Without disabling this bit, if a comma - d is issued when the device is in L1 state and if mac2_clk (utmi_clk/ulpi_clk) is gated off, the command will not get complet - d.*/ +/* +* Enable utmi_sleep_n and utmi_l1_suspend_n (EnblSlpM) The application use + * s this bit to control utmi_sleep_n and utmi_l1_suspend_n assertion to th + * e PHY in the L1 state. - 1'b0: utmi_sleep_n and utmi_l1_suspend_n assert + * ion from the core is not transferred to the external PHY. - 1'b1: utmi_s + * leep_n and utmi_l1_suspend_n assertion from the core is transferred to t + * he external PHY. Note: This bit must be set high for Port0 if PHY is use + * d. Note: In Device mode - Before issuing any device endpoint command whe + * n operating in 2.0 speeds, disable this bit and enable it after the comm + * and completes. Without disabling this bit, if a command is issued when t + * he device is in L1 state and if mac2_clk (utmi_clk/ulpi_clk) is gated of + * f, the command will not get completed. +*/ #undef USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_DEFVAL #undef USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_SHIFT #undef USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_MASK -#define USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_DEFVAL 0x00000000 -#define USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_SHIFT 8 -#define USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_MASK 0x00000100U +#define USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_DEFVAL 0x00000000 +#define USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_SHIFT 8 +#define USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_MASK 0x00000100U -/*USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial Transceiver Select The application uses this bit to select a high-speed P - Y or a full-speed transceiver. - 1'b0: USB 2.0 high-speed UTMI+ or ULPI PHY. This bit is always 0, with Write Only access. - - 'b1: USB 1.1 full-speed serial transceiver. This bit is always 1, with Write Only access. If both interface types are selecte - in coreConsultant (that is, parameters' values are not zero), the application uses this bit to select the active interface i - active, with Read-Write bit access. Note: USB 1.1 full-serial transceiver is not supported. This bit always reads as 1'b0.*/ +/* +* USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial Transceiver Select T + * he application uses this bit to select a high-speed PHY or a full-speed + * transceiver. - 1'b0: USB 2.0 high-speed UTMI+ or ULPI PHY. This bit is a + * lways 0, with Write Only access. - 1'b1: USB 1.1 full-speed serial trans + * ceiver. This bit is always 1, with Write Only access. If both interface + * types are selected in coreConsultant (that is, parameters' values are no + * t zero), the application uses this bit to select the active interface is + * active, with Read-Write bit access. Note: USB 1.1 full-serial transceiv + * er is not supported. This bit always reads as 1'b0. +*/ #undef USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_DEFVAL #undef USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_SHIFT #undef USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_MASK -#define USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_DEFVAL 0x00000000 -#define USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_SHIFT 7 -#define USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_MASK 0x00000080U +#define USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_DEFVAL 0x00000000 +#define USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_SHIFT 7 +#define USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_MASK 0x00000080U -/*Full-Speed Serial Interface Select (FSIntf) The application uses this bit to select a unidirectional or bidirectional USB 1.1 - full-speed serial transceiver interface. - 1'b0: 6-pin unidirectional full-speed serial interface. This bit is set to 0 with - ead Only access. - 1'b1: 3-pin bidirectional full-speed serial interface. This bit is set to 0 with Read Only access. Note: U - B 1.1 full-speed serial interface is not supported. This bit always reads as 1'b0.*/ +/* +* Suspend USB2.0 HS/FS/LS PHY (SusPHY) When set, USB2.0 PHY enters Suspend + * mode if Suspend conditions are valid. For DRD/OTG configurations, it is + * recommended that this bit is set to 0 during coreConsultant configurati + * on. If it is set to 1, then the application must clear this bit after po + * wer-on reset. Application needs to set it to 1 after the core initializa + * tion completes. For all other configurations, this bit can be set to 1 d + * uring core configuration. Note: - In host mode, on reset, this bit is se + * t to 1. Software can override this bit after reset. - In device mode, be + * fore issuing any device endpoint command when operating in 2.0 speeds, d + * isable this bit and enable it after the command completes. If you issue + * a command without disabling this bit when the device is in L2 state and + * if mac2_clk (utmi_clk/ulpi_clk) is gated off, the command will not get c + * ompleted. +*/ +#undef USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_DEFVAL +#undef USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_SHIFT +#undef USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_MASK +#define USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_DEFVAL 0x00000000 +#define USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_SHIFT 6 +#define USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_MASK 0x00000040U + +/* +* Full-Speed Serial Interface Select (FSIntf) The application uses this bi + * t to select a unidirectional or bidirectional USB 1.1 full-speed serial + * transceiver interface. - 1'b0: 6-pin unidirectional full-speed serial in + * terface. This bit is set to 0 with Read Only access. - 1'b1: 3-pin bidir + * ectional full-speed serial interface. This bit is set to 0 with Read Onl + * y access. Note: USB 1.1 full-speed serial interface is not supported. Th + * is bit always reads as 1'b0. +*/ #undef USB3_0_XHCI_GUSB2PHYCFG_FSINTF_DEFVAL #undef USB3_0_XHCI_GUSB2PHYCFG_FSINTF_SHIFT #undef USB3_0_XHCI_GUSB2PHYCFG_FSINTF_MASK -#define USB3_0_XHCI_GUSB2PHYCFG_FSINTF_DEFVAL 0x00000000 -#define USB3_0_XHCI_GUSB2PHYCFG_FSINTF_SHIFT 5 -#define USB3_0_XHCI_GUSB2PHYCFG_FSINTF_MASK 0x00000020U +#define USB3_0_XHCI_GUSB2PHYCFG_FSINTF_DEFVAL 0x00000000 +#define USB3_0_XHCI_GUSB2PHYCFG_FSINTF_SHIFT 5 +#define USB3_0_XHCI_GUSB2PHYCFG_FSINTF_MASK 0x00000020U -/*ULPI or UTMI+ Select (ULPI_UTMI_Sel) The application uses this bit to select a UTMI+ or ULPI Interface. - 1'b0: UTMI+ Interfa - e - 1'b1: ULPI Interface This bit is writable only if UTMI+ and ULPI is specified for High-Speed PHY Interface(s) in coreCons - ltant configuration (DWC_USB3_HSPHY_INTERFACE = 3). Otherwise, this bit is read-only and the value depends on the interface s - lected through DWC_USB3_HSPHY_INTERFACE.*/ +/* +* ULPI or UTMI+ Select (ULPI_UTMI_Sel) The application uses this bit to se + * lect a UTMI+ or ULPI Interface. - 1'b0: UTMI+ Interface - 1'b1: ULPI Int + * erface This bit is writable only if UTMI+ and ULPI is specified for High + * -Speed PHY Interface(s) in coreConsultant configuration (DWC_USB3_HSPHY_ + * INTERFACE = 3). Otherwise, this bit is read-only and the value depends o + * n the interface selected through DWC_USB3_HSPHY_INTERFACE. +*/ #undef USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_DEFVAL #undef USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_SHIFT #undef USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_MASK -#define USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_DEFVAL 0x00000000 -#define USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_SHIFT 4 -#define USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_MASK 0x00000010U +#define USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_DEFVAL 0x00000000 +#define USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_SHIFT 4 +#define USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_MASK 0x00000010U -/*PHY Interface (PHYIf) If UTMI+ is selected, the application uses this bit to configure the core to support a UTMI+ PHY with a - 8- or 16-bit interface. - 1'b0: 8 bits - 1'b1: 16 bits ULPI Mode: 1'b0 Note: - All the enabled 2.0 ports must have the same - lock frequency as Port0 clock frequency (utmi_clk[0]). - The UTMI 8-bit and 16-bit modes cannot be used together for differen - ports at the same time (that is, all the ports must be in 8-bit mode, or all of them must be in 16-bit mode, at a time). - I - any of the USB 2.0 ports is selected as ULPI port for operation, then all the USB 2.0 ports must be operating at 60 MHz.*/ +/* +* PHY Interface (PHYIf) If UTMI+ is selected, the application uses this bi + * t to configure the core to support a UTMI+ PHY with an 8- or 16-bit inte + * rface. - 1'b0: 8 bits - 1'b1: 16 bits ULPI Mode: 1'b0 Note: - All the en + * abled 2.0 ports must have the same clock frequency as Port0 clock freque + * ncy (utmi_clk[0]). - The UTMI 8-bit and 16-bit modes cannot be used toge + * ther for different ports at the same time (that is, all the ports must b + * e in 8-bit mode, or all of them must be in 16-bit mode, at a time). - If + * any of the USB 2.0 ports is selected as ULPI port for operation, then a + * ll the USB 2.0 ports must be operating at 60 MHz. +*/ #undef USB3_0_XHCI_GUSB2PHYCFG_PHYIF_DEFVAL #undef USB3_0_XHCI_GUSB2PHYCFG_PHYIF_SHIFT #undef USB3_0_XHCI_GUSB2PHYCFG_PHYIF_MASK -#define USB3_0_XHCI_GUSB2PHYCFG_PHYIF_DEFVAL 0x00000000 -#define USB3_0_XHCI_GUSB2PHYCFG_PHYIF_SHIFT 3 -#define USB3_0_XHCI_GUSB2PHYCFG_PHYIF_MASK 0x00000008U +#define USB3_0_XHCI_GUSB2PHYCFG_PHYIF_DEFVAL 0x00000000 +#define USB3_0_XHCI_GUSB2PHYCFG_PHYIF_SHIFT 3 +#define USB3_0_XHCI_GUSB2PHYCFG_PHYIF_MASK 0x00000008U -/*HS/FS Timeout Calibration (TOutCal) The number of PHY clocks, as indicated by the application in this field, is multiplied by - a bit-time factor; this factor is added to the high-speed/full-speed interpacket timeout duration in the core to account for - dditional delays introduced by the PHY. This may be required, since the delay introduced by the PHY in generating the linesta - e condition may vary among PHYs. The USB standard timeout value for high-speed operation is 736 to 816 (inclusive) bit times. - The USB standard timeout value for full-speed operation is 16 to 18 (inclusive) bit times. The application must program this - ield based on the speed of connection. The number of bit times added per PHY clock are: High-speed operation: - One 30-MHz PH - clock = 16 bit times - One 60-MHz PHY clock = 8 bit times Full-speed operation: - One 30-MHz PHY clock = 0.4 bit times - One - 60-MHz PHY clock = 0.2 bit times - One 48-MHz PHY clock = 0.25 bit times*/ +/* +* HS/FS Timeout Calibration (TOutCal) The number of PHY clocks, as indicat + * ed by the application in this field, is multiplied by a bit-time factor; + * this factor is added to the high-speed/full-speed interpacket timeout d + * uration in the core to account for additional delays introduced by the P + * HY. This may be required, since the delay introduced by the PHY in gener + * ating the linestate condition may vary among PHYs. The USB standard time + * out value for high-speed operation is 736 to 816 (inclusive) bit times. + * The USB standard timeout value for full-speed operation is 16 to 18 (inc + * lusive) bit times. The application must program this field based on the + * speed of connection. The number of bit times added per PHY clock are: Hi + * gh-speed operation: - One 30-MHz PHY clock = 16 bit times - One 60-MHz P + * HY clock = 8 bit times Full-speed operation: - One 30-MHz PHY clock = 0. + * 4 bit times - One 60-MHz PHY clock = 0.2 bit times - One 48-MHz PHY cloc + * k = 0.25 bit times +*/ #undef USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_DEFVAL #undef USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_SHIFT #undef USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_MASK -#define USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_DEFVAL 0x00000000 -#define USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_SHIFT 0 -#define USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_MASK 0x00000007U +#define USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_DEFVAL 0x00000000 +#define USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_SHIFT 0 +#define USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_MASK 0x00000007U -/*This field indicates the frame length adjustment to be applied when SOF/ITP counter is running on the ref_clk. This register - alue is used to adjust the ITP interval when GCTL[SOFITPSYNC] is set to '1'; SOF and ITP interval when GLADJ.GFLADJ_REFCLK_LP - _SEL is set to '1'. This field must be programmed to a non-zero value only if GFLADJ_REFCLK_LPM_SEL is set to '1' or GCTL.SOF - TPSYNC is set to '1'. The value is derived as follows: FLADJ_REF_CLK_FLADJ=((125000/ref_clk_period_integer)-(125000/ref_clk_p - riod)) * ref_clk_period where - the ref_clk_period_integer is the integer value of the ref_clk period got by truncating the d - cimal (fractional) value that is programmed in the GUCTL.REF_CLK_PERIOD field. - the ref_clk_period is the ref_clk period inc - uding the fractional value. Examples: If the ref_clk is 24 MHz then - GUCTL.REF_CLK_PERIOD = 41 - GFLADJ.GLADJ_REFCLK_FLADJ = - ((125000/41)-(125000/41.6666))*41.6666 = 2032 (ignoring the fractional value) If the ref_clk is 48 MHz then - GUCTL.REF_CLK_P - RIOD = 20 - GFLADJ.GLADJ_REFCLK_FLADJ = ((125000/20)-(125000/20.8333))*20.8333 = 5208 (ignoring the fractional value)*/ +/* +* ULPI External VBUS Drive (ULPIExtVbusDrv) Selects supply source to drive + * 5V on VBUS, in the ULPI PHY. - 1'b0: PHY drives VBUS with internal char + * ge pump (default). - 1'b1: PHY drives VBUS with an external supply. (Onl + * y when RTL parameter DWC_USB3_HSPHY_INTERFACE = 2 or 3) +*/ +#undef USB3_0_XHCI_GUSB2PHYCFG_ULPIEXTVBUSDRV_DEFVAL +#undef USB3_0_XHCI_GUSB2PHYCFG_ULPIEXTVBUSDRV_SHIFT +#undef USB3_0_XHCI_GUSB2PHYCFG_ULPIEXTVBUSDRV_MASK +#define USB3_0_XHCI_GUSB2PHYCFG_ULPIEXTVBUSDRV_DEFVAL 0x00000000 +#define USB3_0_XHCI_GUSB2PHYCFG_ULPIEXTVBUSDRV_SHIFT 17 +#define USB3_0_XHCI_GUSB2PHYCFG_ULPIEXTVBUSDRV_MASK 0x00020000U + +/* +* This field indicates the frame length adjustment to be applied when SOF/ + * ITP counter is running on the ref_clk. This register value is used to ad + * just the ITP interval when GCTL[SOFITPSYNC] is set to '1'; SOF and ITP i + * nterval when GLADJ.GFLADJ_REFCLK_LPM_SEL is set to '1'. This field must + * be programmed to a non-zero value only if GFLADJ_REFCLK_LPM_SEL is set t + * o '1' or GCTL.SOFITPSYNC is set to '1'. The value is derived as follows: + * FLADJ_REF_CLK_FLADJ=((125000/ref_clk_period_integer)-(125000/ref_clk_pe + * riod)) * ref_clk_period where - the ref_clk_period_integer is the intege + * r value of the ref_clk period got by truncating the decimal (fractional) + * value that is programmed in the GUCTL.REF_CLK_PERIOD field. - the ref_c + * lk_period is the ref_clk period including the fractional value. Examples + * : If the ref_clk is 24 MHz then - GUCTL.REF_CLK_PERIOD = 41 - GFLADJ.GLA + * DJ_REFCLK_FLADJ = ((125000/41)-(125000/41.6666))*41.6666 = 2032 (ignorin + * g the fractional value) If the ref_clk is 48 MHz then - GUCTL.REF_CLK_PE + * RIOD = 20 - GFLADJ.GLADJ_REFCLK_FLADJ = ((125000/20)-(125000/20.8333))*2 + * 0.8333 = 5208 (ignoring the fractional value) +*/ #undef USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_DEFVAL #undef USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_SHIFT #undef USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_MASK -#define USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_DEFVAL 0x00000000 -#define USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_SHIFT 8 -#define USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_MASK 0x003FFF00U +#define USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_DEFVAL 0x00000000 +#define USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_SHIFT 8 +#define USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_MASK 0x003FFF00U -/*If TRUE Completion Timeout Disable is supported. This is required to be TRUE for Endpoint and either setting allowed for Root - ports. Drives Device Capability 2 [4]; EP=0x0001; RP=0x0001*/ +/* +* When this bit is set to '0', termsel, xcvrsel will become 0 during end o + * f resume while the opmode will become 0 once controller completes end of + * resume and enters U0 state (2 separate commandswill be issued). When th + * is bit is set to '1', all the termsel, xcvrsel, opmode becomes 0 during + * end of resume itself (only 1 command will be issued) +*/ +#undef USB3_0_XHCI_GUCTL1_RESUME_TERMSEL_XCVRSEL_UNIFY_DEFVAL +#undef USB3_0_XHCI_GUCTL1_RESUME_TERMSEL_XCVRSEL_UNIFY_SHIFT +#undef USB3_0_XHCI_GUCTL1_RESUME_TERMSEL_XCVRSEL_UNIFY_MASK +#define USB3_0_XHCI_GUCTL1_RESUME_TERMSEL_XCVRSEL_UNIFY_DEFVAL 0x00000000 +#define USB3_0_XHCI_GUCTL1_RESUME_TERMSEL_XCVRSEL_UNIFY_SHIFT 10 +#define USB3_0_XHCI_GUCTL1_RESUME_TERMSEL_XCVRSEL_UNIFY_MASK 0x00000400U + +/* +* Reserved +*/ +#undef USB3_0_XHCI_GUCTL1_RESERVED_9_DEFVAL +#undef USB3_0_XHCI_GUCTL1_RESERVED_9_SHIFT +#undef USB3_0_XHCI_GUCTL1_RESERVED_9_MASK +#define USB3_0_XHCI_GUCTL1_RESERVED_9_DEFVAL 0x00000000 +#define USB3_0_XHCI_GUCTL1_RESERVED_9_SHIFT 9 +#define USB3_0_XHCI_GUCTL1_RESERVED_9_MASK 0x00000200U + +/* +* Host IN Auto Retry (USBHstInAutoRetryEn) When set, this field enables th + * e Auto Retry feature. For IN transfers (non-isochronous) that encounter + * data packets with CRC errors or internal overrun scenarios, the auto ret + * ry feature causes the Host core to reply to the device with a non-termin + * ating retry ACK (that is, an ACK transaction packet with Retry = 1 and N + * umP != 0). If the Auto Retry feature is disabled (default), the core wil + * l respond with a terminating retry ACK (that is, an ACK transaction pack + * et with Retry = 1 and NumP = 0). - 1'b0: Auto Retry Disabled - 1'b1: Aut + * o Retry Enabled Note: This bit is also applicable to the device mode. +*/ +#undef USB3_0_XHCI_GUCTL_USBHSTINAUTORETRYEN_DEFVAL +#undef USB3_0_XHCI_GUCTL_USBHSTINAUTORETRYEN_SHIFT +#undef USB3_0_XHCI_GUCTL_USBHSTINAUTORETRYEN_MASK +#define USB3_0_XHCI_GUCTL_USBHSTINAUTORETRYEN_DEFVAL 0x00000000 +#define USB3_0_XHCI_GUCTL_USBHSTINAUTORETRYEN_SHIFT 14 +#define USB3_0_XHCI_GUCTL_USBHSTINAUTORETRYEN_MASK 0x00004000U + +/* +* If TRUE Completion Timeout Disable is supported. This is required to be + * TRUE for Endpoint and either setting allowed for Root ports. Drives Devi + * ce Capability 2 [4]; EP=0x0001; RP=0x0001 +*/ #undef PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_DEFVAL #undef PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_SHIFT #undef PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_MASK -#define PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_DEFVAL 0x00000905 -#define PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_SHIFT 9 -#define PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_MASK 0x00000200U +#define PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_DEFVAL 0x00000905 +#define PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_SHIFT 9 +#define PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_MASK 0x00000200U -/*Specifies mask/settings for Base Address Register (BAR) 0. If BAR is not to be implemented, set to 32'h00000000. Bits are def - ned as follows: Memory Space BAR [0] = Mem Space Indicator (set to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = - Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory a - erture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR1,BAR0\'7d to 1. IO Space BAR 0] = IO Space Indicator - set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o apert - re size in bytes.; EP=0x0004; RP=0x0000*/ +/* +* Specifies mask/settings for Base Address Register (BAR) 0. If BAR is not + * to be implemented, set to 32'h00000000. Bits are defined as follows: Me + * mory Space BAR [0] = Mem Space Indicator (set to 0) [2:1] = Type field ( + * 10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask + * for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to 1, w + * here 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63: + * n bits of \'7bBAR1,BAR0\'7d to 1. IO Space BAR 0] = IO Space Indicator ( + * set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of B + * AR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; + * EP=0x0004; RP=0x0000 +*/ #undef PCIE_ATTRIB_ATTR_7_ATTR_BAR0_DEFVAL #undef PCIE_ATTRIB_ATTR_7_ATTR_BAR0_SHIFT #undef PCIE_ATTRIB_ATTR_7_ATTR_BAR0_MASK -#define PCIE_ATTRIB_ATTR_7_ATTR_BAR0_DEFVAL -#define PCIE_ATTRIB_ATTR_7_ATTR_BAR0_SHIFT 0 -#define PCIE_ATTRIB_ATTR_7_ATTR_BAR0_MASK 0x0000FFFFU +#define PCIE_ATTRIB_ATTR_7_ATTR_BAR0_DEFVAL +#define PCIE_ATTRIB_ATTR_7_ATTR_BAR0_SHIFT 0 +#define PCIE_ATTRIB_ATTR_7_ATTR_BAR0_MASK 0x0000FFFFU -/*Specifies mask/settings for Base Address Register (BAR) 0. If BAR is not to be implemented, set to 32'h00000000. Bits are def - ned as follows: Memory Space BAR [0] = Mem Space Indicator (set to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = - Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory a - erture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR1,BAR0\'7d to 1. IO Space BAR 0] = IO Space Indicator - set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o apert - re size in bytes.; EP=0xFFF0; RP=0x0000*/ +/* +* Specifies mask/settings for Base Address Register (BAR) 0. If BAR is not + * to be implemented, set to 32'h00000000. Bits are defined as follows: Me + * mory Space BAR [0] = Mem Space Indicator (set to 0) [2:1] = Type field ( + * 10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask + * for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to 1, w + * here 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63: + * n bits of \'7bBAR1,BAR0\'7d to 1. IO Space BAR 0] = IO Space Indicator ( + * set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of B + * AR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; + * EP=0xFFF0; RP=0x0000 +*/ #undef PCIE_ATTRIB_ATTR_8_ATTR_BAR0_DEFVAL #undef PCIE_ATTRIB_ATTR_8_ATTR_BAR0_SHIFT #undef PCIE_ATTRIB_ATTR_8_ATTR_BAR0_MASK -#define PCIE_ATTRIB_ATTR_8_ATTR_BAR0_DEFVAL -#define PCIE_ATTRIB_ATTR_8_ATTR_BAR0_SHIFT 0 -#define PCIE_ATTRIB_ATTR_8_ATTR_BAR0_MASK 0x0000FFFFU +#define PCIE_ATTRIB_ATTR_8_ATTR_BAR0_DEFVAL +#define PCIE_ATTRIB_ATTR_8_ATTR_BAR0_SHIFT 0 +#define PCIE_ATTRIB_ATTR_8_ATTR_BAR0_MASK 0x0000FFFFU -/*Specifies mask/settings for Base Address Register (BAR) 1 if BAR0 is a 32-bit BAR, or the upper bits of \'7bBAR1,BAR0\'7d if - AR0 is a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR0 description if this functions as the uppe - bits of a 64-bit BAR. Bits are defined as follows: Memory Space BAR (not upper bits of BAR0) [0] = Mem Space Indicator (set - o 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if - 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of - '7bBAR2,BAR1\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable b - ts of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000*/ +/* +* Specifies mask/settings for Base Address Register (BAR) 1 if BAR0 is a 3 + * 2-bit BAR, or the upper bits of \'7bBAR1,BAR0\'7d if BAR0 is a 64-bit BA + * R. If BAR is not to be implemented, set to 32'h00000000. See BAR0 descri + * ption if this functions as the upper bits of a 64-bit BAR. Bits are defi + * ned as follows: Memory Space BAR (not upper bits of BAR0) [0] = Mem Spac + * e Indicator (set to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) + * [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if + * 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size + * in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR2,BAR1\'7d t + * o 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set + * to 0) [31:2] = Mask for writable bits of BAR; set uppermost 31:n bits t + * o 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000 +*/ #undef PCIE_ATTRIB_ATTR_9_ATTR_BAR1_DEFVAL #undef PCIE_ATTRIB_ATTR_9_ATTR_BAR1_SHIFT #undef PCIE_ATTRIB_ATTR_9_ATTR_BAR1_MASK -#define PCIE_ATTRIB_ATTR_9_ATTR_BAR1_DEFVAL -#define PCIE_ATTRIB_ATTR_9_ATTR_BAR1_SHIFT 0 -#define PCIE_ATTRIB_ATTR_9_ATTR_BAR1_MASK 0x0000FFFFU +#define PCIE_ATTRIB_ATTR_9_ATTR_BAR1_DEFVAL +#define PCIE_ATTRIB_ATTR_9_ATTR_BAR1_SHIFT 0 +#define PCIE_ATTRIB_ATTR_9_ATTR_BAR1_MASK 0x0000FFFFU -/*Specifies mask/settings for Base Address Register (BAR) 1 if BAR0 is a 32-bit BAR, or the upper bits of \'7bBAR1,BAR0\'7d if - AR0 is a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR0 description if this functions as the uppe - bits of a 64-bit BAR. Bits are defined as follows: Memory Space BAR (not upper bits of BAR0) [0] = Mem Space Indicator (set - o 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if - 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of - '7bBAR2,BAR1\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable b - ts of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000*/ +/* +* Specifies mask/settings for Base Address Register (BAR) 1 if BAR0 is a 3 + * 2-bit BAR, or the upper bits of \'7bBAR1,BAR0\'7d if BAR0 is a 64-bit BA + * R. If BAR is not to be implemented, set to 32'h00000000. See BAR0 descri + * ption if this functions as the upper bits of a 64-bit BAR. Bits are defi + * ned as follows: Memory Space BAR (not upper bits of BAR0) [0] = Mem Spac + * e Indicator (set to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) + * [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if + * 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size + * in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR2,BAR1\'7d t + * o 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set + * to 0) [31:2] = Mask for writable bits of BAR; set uppermost 31:n bits t + * o 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000 +*/ #undef PCIE_ATTRIB_ATTR_10_ATTR_BAR1_DEFVAL #undef PCIE_ATTRIB_ATTR_10_ATTR_BAR1_SHIFT #undef PCIE_ATTRIB_ATTR_10_ATTR_BAR1_MASK -#define PCIE_ATTRIB_ATTR_10_ATTR_BAR1_DEFVAL -#define PCIE_ATTRIB_ATTR_10_ATTR_BAR1_SHIFT 0 -#define PCIE_ATTRIB_ATTR_10_ATTR_BAR1_MASK 0x0000FFFFU +#define PCIE_ATTRIB_ATTR_10_ATTR_BAR1_DEFVAL +#define PCIE_ATTRIB_ATTR_10_ATTR_BAR1_SHIFT 0 +#define PCIE_ATTRIB_ATTR_10_ATTR_BAR1_MASK 0x0000FFFFU -/*For an endpoint, specifies mask/settings for Base Address Register (BAR) 2 if BAR1 is a 32-bit BAR, or the upper bits of \'7b - AR2,BAR1\'7d if BAR1 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR1 descri - tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to 00FF_FFFF. For an endpoin - , bits are defined as follows: Memory Space BAR (not upper bits of BAR1) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi - ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe - most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR3,BAR2\'7d to - . IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper - ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0x0004; RP=0xFFFF*/ +/* +* For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 2 if BAR1 is a 32-bit BAR, or the upper bits of \'7bBAR2,BAR1\'7d if BA + * R1 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR1 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root: This must be set to 00FF_FFF + * F. For an endpoint, bits are defined as follows: Memory Space BAR (not u + * pper bits of BAR1) [0] = Mem Space Indicator (set to 0) [2:1] = Type fie + * ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = M + * ask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to + * 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost + * 63:n bits of \'7bBAR3,BAR2\'7d to 1. IO Space BAR 0] = IO Space Indicat + * or (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits + * of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in byt + * es.; EP=0x0004; RP=0xFFFF +*/ #undef PCIE_ATTRIB_ATTR_11_ATTR_BAR2_DEFVAL #undef PCIE_ATTRIB_ATTR_11_ATTR_BAR2_SHIFT #undef PCIE_ATTRIB_ATTR_11_ATTR_BAR2_MASK -#define PCIE_ATTRIB_ATTR_11_ATTR_BAR2_DEFVAL -#define PCIE_ATTRIB_ATTR_11_ATTR_BAR2_SHIFT 0 -#define PCIE_ATTRIB_ATTR_11_ATTR_BAR2_MASK 0x0000FFFFU +#define PCIE_ATTRIB_ATTR_11_ATTR_BAR2_DEFVAL +#define PCIE_ATTRIB_ATTR_11_ATTR_BAR2_SHIFT 0 +#define PCIE_ATTRIB_ATTR_11_ATTR_BAR2_MASK 0x0000FFFFU -/*For an endpoint, specifies mask/settings for Base Address Register (BAR) 2 if BAR1 is a 32-bit BAR, or the upper bits of \'7b - AR2,BAR1\'7d if BAR1 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR1 descri - tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to 00FF_FFFF. For an endpoin - , bits are defined as follows: Memory Space BAR (not upper bits of BAR1) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi - ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe - most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR3,BAR2\'7d to - . IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper - ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFF0; RP=0x00FF*/ +/* +* For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 2 if BAR1 is a 32-bit BAR, or the upper bits of \'7bBAR2,BAR1\'7d if BA + * R1 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR1 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root: This must be set to 00FF_FFF + * F. For an endpoint, bits are defined as follows: Memory Space BAR (not u + * pper bits of BAR1) [0] = Mem Space Indicator (set to 0) [2:1] = Type fie + * ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = M + * ask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to + * 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost + * 63:n bits of \'7bBAR3,BAR2\'7d to 1. IO Space BAR 0] = IO Space Indicat + * or (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits + * of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in byt + * es.; EP=0xFFF0; RP=0x00FF +*/ #undef PCIE_ATTRIB_ATTR_12_ATTR_BAR2_DEFVAL #undef PCIE_ATTRIB_ATTR_12_ATTR_BAR2_SHIFT #undef PCIE_ATTRIB_ATTR_12_ATTR_BAR2_MASK -#define PCIE_ATTRIB_ATTR_12_ATTR_BAR2_DEFVAL -#define PCIE_ATTRIB_ATTR_12_ATTR_BAR2_SHIFT 0 -#define PCIE_ATTRIB_ATTR_12_ATTR_BAR2_MASK 0x0000FFFFU +#define PCIE_ATTRIB_ATTR_12_ATTR_BAR2_DEFVAL +#define PCIE_ATTRIB_ATTR_12_ATTR_BAR2_SHIFT 0 +#define PCIE_ATTRIB_ATTR_12_ATTR_BAR2_MASK 0x0000FFFFU -/*For an endpoint, specifies mask/settings for Base Address Register (BAR) 3 if BAR2 is a 32-bit BAR, or the upper bits of \'7b - AR3,BAR2\'7d if BAR2 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR2 descri - tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: FFFF_0000 = IO Limit/Bas - Registers not implemented FFFF_F0F0 = IO Limit/Base Registers use 16-bit decode FFFF_F1F1 = IO Limit/Base Registers use 32-b - t decode For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of BAR2) [0] = Mem Space Indicator (s - t to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; - if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits - f \'7bBAR4,BAR3\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writabl - bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000*/ +/* +* For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 3 if BAR2 is a 32-bit BAR, or the upper bits of \'7bBAR3,BAR2\'7d if BA + * R2 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR2 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root, this must be set to: FFFF_00 + * 00 = IO Limit/Base Registers not implemented FFFF_F0F0 = IO Limit/Base R + * egisters use 16-bit decode FFFF_F1F1 = IO Limit/Base Registers use 32-bi + * t decode For an endpoint, bits are defined as follows: Memory Space BAR + * (not upper bits of BAR2) [0] = Mem Space Indicator (set to 0) [2:1] = Ty + * pe field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31: + * 4] = Mask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bi + * ts to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set upp + * ermost 63:n bits of \'7bBAR4,BAR3\'7d to 1. IO Space BAR 0] = IO Space I + * ndicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable + * bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size + * in bytes.; EP=0xFFFF; RP=0x0000 +*/ #undef PCIE_ATTRIB_ATTR_13_ATTR_BAR3_DEFVAL #undef PCIE_ATTRIB_ATTR_13_ATTR_BAR3_SHIFT #undef PCIE_ATTRIB_ATTR_13_ATTR_BAR3_MASK -#define PCIE_ATTRIB_ATTR_13_ATTR_BAR3_DEFVAL -#define PCIE_ATTRIB_ATTR_13_ATTR_BAR3_SHIFT 0 -#define PCIE_ATTRIB_ATTR_13_ATTR_BAR3_MASK 0x0000FFFFU +#define PCIE_ATTRIB_ATTR_13_ATTR_BAR3_DEFVAL +#define PCIE_ATTRIB_ATTR_13_ATTR_BAR3_SHIFT 0 +#define PCIE_ATTRIB_ATTR_13_ATTR_BAR3_MASK 0x0000FFFFU -/*For an endpoint, specifies mask/settings for Base Address Register (BAR) 3 if BAR2 is a 32-bit BAR, or the upper bits of \'7b - AR3,BAR2\'7d if BAR2 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR2 descri - tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: FFFF_0000 = IO Limit/Bas - Registers not implemented FFFF_F0F0 = IO Limit/Base Registers use 16-bit decode FFFF_F1F1 = IO Limit/Base Registers use 32-b - t decode For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of BAR2) [0] = Mem Space Indicator (s - t to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; - if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits - f \'7bBAR4,BAR3\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writabl - bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0xFFFF*/ +/* +* For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 3 if BAR2 is a 32-bit BAR, or the upper bits of \'7bBAR3,BAR2\'7d if BA + * R2 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR2 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root, this must be set to: FFFF_00 + * 00 = IO Limit/Base Registers not implemented FFFF_F0F0 = IO Limit/Base R + * egisters use 16-bit decode FFFF_F1F1 = IO Limit/Base Registers use 32-bi + * t decode For an endpoint, bits are defined as follows: Memory Space BAR + * (not upper bits of BAR2) [0] = Mem Space Indicator (set to 0) [2:1] = Ty + * pe field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31: + * 4] = Mask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bi + * ts to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set upp + * ermost 63:n bits of \'7bBAR4,BAR3\'7d to 1. IO Space BAR 0] = IO Space I + * ndicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable + * bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size + * in bytes.; EP=0xFFFF; RP=0xFFFF +*/ #undef PCIE_ATTRIB_ATTR_14_ATTR_BAR3_DEFVAL #undef PCIE_ATTRIB_ATTR_14_ATTR_BAR3_SHIFT #undef PCIE_ATTRIB_ATTR_14_ATTR_BAR3_MASK -#define PCIE_ATTRIB_ATTR_14_ATTR_BAR3_DEFVAL -#define PCIE_ATTRIB_ATTR_14_ATTR_BAR3_SHIFT 0 -#define PCIE_ATTRIB_ATTR_14_ATTR_BAR3_MASK 0x0000FFFFU +#define PCIE_ATTRIB_ATTR_14_ATTR_BAR3_DEFVAL +#define PCIE_ATTRIB_ATTR_14_ATTR_BAR3_SHIFT 0 +#define PCIE_ATTRIB_ATTR_14_ATTR_BAR3_MASK 0x0000FFFFU -/*For an endpoint, specifies mask/settings for Base Address Register (BAR) 4 if BAR3 is a 32-bit BAR, or the upper bits of \'7b - AR4,BAR3\'7d if BAR3 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR3 descri - tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to FFF0_FFF0. For an endpoin - , bits are defined as follows: Memory Space BAR (not upper bits of BAR3) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi - ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe - most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR5,BAR4\'7d to - . IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper - ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0x0004; RP=0xFFF0*/ +/* +* For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 4 if BAR3 is a 32-bit BAR, or the upper bits of \'7bBAR4,BAR3\'7d if BA + * R3 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR3 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root: This must be set to FFF0_FFF + * 0. For an endpoint, bits are defined as follows: Memory Space BAR (not u + * pper bits of BAR3) [0] = Mem Space Indicator (set to 0) [2:1] = Type fie + * ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = M + * ask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to + * 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost + * 63:n bits of \'7bBAR5,BAR4\'7d to 1. IO Space BAR 0] = IO Space Indicat + * or (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits + * of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in byt + * es.; EP=0x0004; RP=0xFFF0 +*/ #undef PCIE_ATTRIB_ATTR_15_ATTR_BAR4_DEFVAL #undef PCIE_ATTRIB_ATTR_15_ATTR_BAR4_SHIFT #undef PCIE_ATTRIB_ATTR_15_ATTR_BAR4_MASK -#define PCIE_ATTRIB_ATTR_15_ATTR_BAR4_DEFVAL -#define PCIE_ATTRIB_ATTR_15_ATTR_BAR4_SHIFT 0 -#define PCIE_ATTRIB_ATTR_15_ATTR_BAR4_MASK 0x0000FFFFU +#define PCIE_ATTRIB_ATTR_15_ATTR_BAR4_DEFVAL +#define PCIE_ATTRIB_ATTR_15_ATTR_BAR4_SHIFT 0 +#define PCIE_ATTRIB_ATTR_15_ATTR_BAR4_MASK 0x0000FFFFU -/*For an endpoint, specifies mask/settings for Base Address Register (BAR) 4 if BAR3 is a 32-bit BAR, or the upper bits of \'7b - AR4,BAR3\'7d if BAR3 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR3 descri - tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to FFF0_FFF0. For an endpoin - , bits are defined as follows: Memory Space BAR (not upper bits of BAR3) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi - ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe - most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR5,BAR4\'7d to - . IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper - ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFF0; RP=0xFFF0*/ +/* +* For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 4 if BAR3 is a 32-bit BAR, or the upper bits of \'7bBAR4,BAR3\'7d if BA + * R3 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR3 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root: This must be set to FFF0_FFF + * 0. For an endpoint, bits are defined as follows: Memory Space BAR (not u + * pper bits of BAR3) [0] = Mem Space Indicator (set to 0) [2:1] = Type fie + * ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = M + * ask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to + * 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost + * 63:n bits of \'7bBAR5,BAR4\'7d to 1. IO Space BAR 0] = IO Space Indicat + * or (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits + * of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in byt + * es.; EP=0xFFF0; RP=0xFFF0 +*/ #undef PCIE_ATTRIB_ATTR_16_ATTR_BAR4_DEFVAL #undef PCIE_ATTRIB_ATTR_16_ATTR_BAR4_SHIFT #undef PCIE_ATTRIB_ATTR_16_ATTR_BAR4_MASK -#define PCIE_ATTRIB_ATTR_16_ATTR_BAR4_DEFVAL -#define PCIE_ATTRIB_ATTR_16_ATTR_BAR4_SHIFT 0 -#define PCIE_ATTRIB_ATTR_16_ATTR_BAR4_MASK 0x0000FFFFU +#define PCIE_ATTRIB_ATTR_16_ATTR_BAR4_DEFVAL +#define PCIE_ATTRIB_ATTR_16_ATTR_BAR4_SHIFT 0 +#define PCIE_ATTRIB_ATTR_16_ATTR_BAR4_MASK 0x0000FFFFU -/*For an endpoint, specifies mask/settings for Base Address Register (BAR) 5 if BAR4 is a 32-bit BAR, or the upper bits of \'7b - AR5,BAR4\'7d if BAR4 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR4 descri - tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: 0000_0000 = Prefetchable - Memory Limit/Base Registers not implemented FFF0_FFF0 = 32-bit Prefetchable Memory Limit/Base implemented FFF1_FFF1 = 64-bit - refetchable Memory Limit/Base implemented For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of B - R4) [0] = Mem Space Indicator (set to 0) [2:1] = Type field (00 for 32-bit; BAR5 cannot be lower part of a 64-bit BAR) [3] = - refetchable (0 or 1) [31:4] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=memory aperture size in - ytes. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set u - permost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0xFFF1*/ +/* +* For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 5 if BAR4 is a 32-bit BAR, or the upper bits of \'7bBAR5,BAR4\'7d if BA + * R4 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR4 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root, this must be set to: 0000_00 + * 00 = Prefetchable Memory Limit/Base Registers not implemented FFF0_FFF0 + * = 32-bit Prefetchable Memory Limit/Base implemented FFF1_FFF1 = 64-bit P + * refetchable Memory Limit/Base implemented For an endpoint, bits are defi + * ned as follows: Memory Space BAR (not upper bits of BAR4) [0] = Mem Spac + * e Indicator (set to 0) [2:1] = Type field (00 for 32-bit; BAR5 cannot be + * lower part of a 64-bit BAR) [3] = Prefetchable (0 or 1) [31:4] = Mask f + * or writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=memory + * aperture size in bytes. IO Space BAR 0] = IO Space Indicator (set to 1) + * [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set up + * permost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF + * ; RP=0xFFF1 +*/ #undef PCIE_ATTRIB_ATTR_17_ATTR_BAR5_DEFVAL #undef PCIE_ATTRIB_ATTR_17_ATTR_BAR5_SHIFT #undef PCIE_ATTRIB_ATTR_17_ATTR_BAR5_MASK -#define PCIE_ATTRIB_ATTR_17_ATTR_BAR5_DEFVAL -#define PCIE_ATTRIB_ATTR_17_ATTR_BAR5_SHIFT 0 -#define PCIE_ATTRIB_ATTR_17_ATTR_BAR5_MASK 0x0000FFFFU +#define PCIE_ATTRIB_ATTR_17_ATTR_BAR5_DEFVAL +#define PCIE_ATTRIB_ATTR_17_ATTR_BAR5_SHIFT 0 +#define PCIE_ATTRIB_ATTR_17_ATTR_BAR5_MASK 0x0000FFFFU -/*For an endpoint, specifies mask/settings for Base Address Register (BAR) 5 if BAR4 is a 32-bit BAR, or the upper bits of \'7b - AR5,BAR4\'7d if BAR4 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR4 descri - tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: 0000_0000 = Prefetchable - Memory Limit/Base Registers not implemented FFF0_FFF0 = 32-bit Prefetchable Memory Limit/Base implemented FFF1_FFF1 = 64-bit - refetchable Memory Limit/Base implemented For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of B - R4) [0] = Mem Space Indicator (set to 0) [2:1] = Type field (00 for 32-bit; BAR5 cannot be lower part of a 64-bit BAR) [3] = - refetchable (0 or 1) [31:4] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=memory aperture size in - ytes. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set u - permost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0xFFF1*/ +/* +* For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 5 if BAR4 is a 32-bit BAR, or the upper bits of \'7bBAR5,BAR4\'7d if BA + * R4 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR4 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root, this must be set to: 0000_00 + * 00 = Prefetchable Memory Limit/Base Registers not implemented FFF0_FFF0 + * = 32-bit Prefetchable Memory Limit/Base implemented FFF1_FFF1 = 64-bit P + * refetchable Memory Limit/Base implemented For an endpoint, bits are defi + * ned as follows: Memory Space BAR (not upper bits of BAR4) [0] = Mem Spac + * e Indicator (set to 0) [2:1] = Type field (00 for 32-bit; BAR5 cannot be + * lower part of a 64-bit BAR) [3] = Prefetchable (0 or 1) [31:4] = Mask f + * or writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=memory + * aperture size in bytes. IO Space BAR 0] = IO Space Indicator (set to 1) + * [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set up + * permost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF + * ; RP=0xFFF1 +*/ #undef PCIE_ATTRIB_ATTR_18_ATTR_BAR5_DEFVAL #undef PCIE_ATTRIB_ATTR_18_ATTR_BAR5_SHIFT #undef PCIE_ATTRIB_ATTR_18_ATTR_BAR5_MASK -#define PCIE_ATTRIB_ATTR_18_ATTR_BAR5_DEFVAL -#define PCIE_ATTRIB_ATTR_18_ATTR_BAR5_SHIFT 0 -#define PCIE_ATTRIB_ATTR_18_ATTR_BAR5_MASK 0x0000FFFFU +#define PCIE_ATTRIB_ATTR_18_ATTR_BAR5_DEFVAL +#define PCIE_ATTRIB_ATTR_18_ATTR_BAR5_SHIFT 0 +#define PCIE_ATTRIB_ATTR_18_ATTR_BAR5_MASK 0x0000FFFFU -/*Specifies maximum payload supported. Valid settings are: 0- 128 bytes, 1- 256 bytes, 2- 512 bytes, 3- 1024 bytes. Transferred - to the Device Capabilities register. The values: 4-2048 bytes, 5- 4096 bytes are not supported; EP=0x0001; RP=0x0001*/ +/* +* Specifies maximum payload supported. Valid settings are: 0- 128 bytes, 1 + * - 256 bytes, 2- 512 bytes, 3- 1024 bytes. Transferred to the Device Capa + * bilities register. The values: 4-2048 bytes, 5- 4096 bytes are not suppo + * rted; EP=0x0001; RP=0x0001 +*/ #undef PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_DEFVAL #undef PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_SHIFT #undef PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_MASK -#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_DEFVAL 0x00002138 -#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_SHIFT 8 -#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_MASK 0x00000700U +#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_DEFVAL 0x00002138 +#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_SHIFT 8 +#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_MASK 0x00000700U -/*Endpoint L1 Acceptable Latency. Records the latency that the endpoint can withstand on transitions from L1 state to L0 (if L1 - state supported). Valid settings are: 0h less than 1us, 1h 1 to 2us, 2h 2 to 4us, 3h 4 to 8us, 4h 8 to 16us, 5h 16 to 32us, 6 - 32 to 64us, 7h more than 64us. For Endpoints only. Must be 0h for other devices.; EP=0x0007; RP=0x0000*/ +/* +* Endpoint L1 Acceptable Latency. Records the latency that the endpoint ca + * n withstand on transitions from L1 state to L0 (if L1 state supported). + * Valid settings are: 0h less than 1us, 1h 1 to 2us, 2h 2 to 4us, 3h 4 to + * 8us, 4h 8 to 16us, 5h 16 to 32us, 6h 32 to 64us, 7h more than 64us. For + * Endpoints only. Must be 0h for other devices.; EP=0x0007; RP=0x0000 +*/ #undef PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_DEFVAL #undef PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_SHIFT #undef PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_MASK -#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_DEFVAL 0x00002138 -#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_SHIFT 3 -#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_MASK 0x00000038U +#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_DEFVAL 0x00002138 +#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_SHIFT 3 +#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_MASK 0x00000038U -/*Identifies the type of device/port as follows: 0000b PCI Express Endpoint device, 0001b Legacy PCI Express Endpoint device, 0 - 00b Root Port of PCI Express Root Complex, 0101b Upstream Port of PCI Express Switch, 0110b Downstream Port of PCI Express Sw - tch, 0111b PCIE Express to PCI/PCI-X Bridge, 1000b PCI/PCI-X to PCI Express Bridge. Transferred to PCI Express Capabilities r - gister. Must be consistent with IS_SWITCH and UPSTREAM_FACING settings.; EP=0x0000; RP=0x0004*/ +/* +* Identifies the type of device/port as follows: 0000b PCI Express Endpoin + * t device, 0001b Legacy PCI Express Endpoint device, 0100b Root Port of P + * CI Express Root Complex, 0101b Upstream Port of PCI Express Switch, 0110 + * b Downstream Port of PCI Express Switch, 0111b PCIE Express to PCI/PCI-X + * Bridge, 1000b PCI/PCI-X to PCI Express Bridge. Transferred to PCI Expre + * ss Capabilities register. Must be consistent with IS_SWITCH and UPSTREAM + * _FACING settings.; EP=0x0000; RP=0x0004 +*/ #undef PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_DEFVAL #undef PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_SHIFT #undef PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_MASK -#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_DEFVAL 0x00009C02 -#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_SHIFT 4 -#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_MASK 0x000000F0U +#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_DEFVAL 0x00009C02 +#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_SHIFT 4 +#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_MASK 0x000000F0U -/*PCIe Capability's Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capab - lity.; EP=0x009C; RP=0x0000*/ +/* +* PCIe Capability's Next Capability Offset pointer to the next item in the + * capabilities list, or 00h if this is the final capability.; EP=0x009C; + * RP=0x0000 +*/ #undef PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_DEFVAL #undef PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_SHIFT #undef PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_MASK -#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_DEFVAL 0x00009C02 -#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_SHIFT 8 -#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_MASK 0x0000FF00U +#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_DEFVAL 0x00009C02 +#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_SHIFT 8 +#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_MASK 0x0000FF00U -/*Number of credits that should be advertised for Completion data received on Virtual Channel 0. The bytes advertised must be l - ss than or equal to the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0172; RP=0x00CD*/ +/* +* Number of credits that should be advertised for Completion data received + * on Virtual Channel 0. The bytes advertised must be less than or equal t + * o the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0172; RP=0x00CD +*/ #undef PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_DEFVAL #undef PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_SHIFT #undef PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_MASK -#define PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_DEFVAL -#define PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_SHIFT 0 -#define PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_MASK 0x000007FFU +#define PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_DEFVAL +#define PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_SHIFT 0 +#define PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_MASK 0x000007FFU -/*Number of credits that should be advertised for Completion headers received on Virtual Channel 0. The sum of the posted, non - osted, and completion header credits must be <= 80; EP=0x0048; RP=0x0024*/ +/* +* Number of credits that should be advertised for Completion headers recei + * ved on Virtual Channel 0. The sum of the posted, non posted, and complet + * ion header credits must be <= 80; EP=0x0048; RP=0x0024 +*/ #undef PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_DEFVAL #undef PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_SHIFT #undef PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_MASK -#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_DEFVAL 0x00000248 -#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_SHIFT 0 -#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_MASK 0x0000007FU +#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_DEFVAL 0x00000248 +#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_SHIFT 0 +#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_MASK 0x0000007FU -/*Number of credits that should be advertised for Non-Posted headers received on Virtual Channel 0. The number of non posted da - a credits advertised by the block is equal to the number of non posted header credits. The sum of the posted, non posted, and - completion header credits must be <= 80; EP=0x0004; RP=0x000C*/ +/* +* Number of credits that should be advertised for Non-Posted headers recei + * ved on Virtual Channel 0. The number of non posted data credits advertis + * ed by the block is equal to the number of non posted header credits. The + * sum of the posted, non posted, and completion header credits must be <= + * 80; EP=0x0004; RP=0x000C +*/ #undef PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_DEFVAL #undef PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_SHIFT #undef PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_MASK -#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_DEFVAL 0x00000248 -#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_SHIFT 7 -#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_MASK 0x00003F80U +#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_DEFVAL 0x00000248 +#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_SHIFT 7 +#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_MASK 0x00003F80U -/*Number of credits that should be advertised for Non-Posted data received on Virtual Channel 0. The number of non posted data - redits advertised by the block is equal to two times the number of non posted header credits if atomic operations are support - d or is equal to the number of non posted header credits if atomic operations are not supported. The bytes advertised must be - less than or equal to the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0008; RP=0x0018*/ +/* +* Number of credits that should be advertised for Non-Posted data received + * on Virtual Channel 0. The number of non posted data credits advertised + * by the block is equal to two times the number of non posted header credi + * ts if atomic operations are supported or is equal to the number of non p + * osted header credits if atomic operations are not supported. The bytes a + * dvertised must be less than or equal to the bram bytes available. See VC + * 0_RX_RAM_LIMIT; EP=0x0008; RP=0x0018 +*/ #undef PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_DEFVAL #undef PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_SHIFT #undef PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_MASK -#define PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_DEFVAL -#define PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_SHIFT 0 -#define PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_MASK 0x000007FFU +#define PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_DEFVAL +#define PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_SHIFT 0 +#define PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_MASK 0x000007FFU -/*Number of credits that should be advertised for Posted data received on Virtual Channel 0. The bytes advertised must be less - han or equal to the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0020; RP=0x00B5*/ +/* +* Number of credits that should be advertised for Posted data received on + * Virtual Channel 0. The bytes advertised must be less than or equal to th + * e bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0020; RP=0x00B5 +*/ #undef PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_DEFVAL #undef PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_SHIFT #undef PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_MASK -#define PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_DEFVAL -#define PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_SHIFT 0 -#define PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_MASK 0x000007FFU +#define PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_DEFVAL +#define PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_SHIFT 0 +#define PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_MASK 0x000007FFU -/*Not currently in use. Invert ECRC generated by block when trn_tecrc_gen_n and trn_terrfwd_n are asserted.; EP=0x0000; RP=0x00 - 0*/ +/* +* Not currently in use. Invert ECRC generated by block when trn_tecrc_gen_ + * n and trn_terrfwd_n are asserted.; EP=0x0000; RP=0x0000 +*/ #undef PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_DEFVAL #undef PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_SHIFT #undef PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_MASK -#define PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_DEFVAL 0x00007E04 -#define PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_SHIFT 15 -#define PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_MASK 0x00008000U +#define PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_DEFVAL 0x00007E04 +#define PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_SHIFT 15 +#define PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_MASK 0x00008000U -/*Enables td bit clear and ECRC trim on received TLP's FALSE == don't trim TRUE == trim.; EP=0x0001; RP=0x0001*/ +/* +* Enables td bit clear and ECRC trim on received TLP's FALSE == don't trim + * TRUE == trim.; EP=0x0001; RP=0x0001 +*/ #undef PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_DEFVAL #undef PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_SHIFT #undef PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_MASK -#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_DEFVAL 0x00007E04 -#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_SHIFT 14 -#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_MASK 0x00004000U +#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_DEFVAL 0x00007E04 +#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_SHIFT 14 +#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_MASK 0x00004000U -/*Enables ECRC check on received TLP's 0 == don't check 1 == always check 3 == check if enabled by ECRC check enable bit of AER - cap structure; EP=0x0003; RP=0x0003*/ +/* +* Enables ECRC check on received TLP's 0 == don't check 1 == always check + * 3 == check if enabled by ECRC check enable bit of AER cap structure; EP= + * 0x0003; RP=0x0003 +*/ #undef PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_DEFVAL #undef PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_SHIFT #undef PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_MASK -#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_DEFVAL 0x00007E04 -#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_SHIFT 12 -#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_MASK 0x00003000U +#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_DEFVAL 0x00007E04 +#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_SHIFT 12 +#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_MASK 0x00003000U -/*Index of last packet buffer used by TX TLM (i.e. number of buffers - 1). Calculated from max payload size supported and the n - mber of brams configured for transmit; EP=0x001C; RP=0x001C*/ +/* +* Index of last packet buffer used by TX TLM (i.e. number of buffers - 1). + * Calculated from max payload size supported and the number of brams conf + * igured for transmit; EP=0x001C; RP=0x001C +*/ #undef PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_DEFVAL #undef PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_SHIFT #undef PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_MASK -#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_DEFVAL 0x00007E04 -#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_SHIFT 7 -#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_MASK 0x00000F80U +#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_DEFVAL 0x00007E04 +#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_SHIFT 7 +#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_MASK 0x00000F80U -/*Number of credits that should be advertised for Posted headers received on Virtual Channel 0. The sum of the posted, non post - d, and completion header credits must be <= 80; EP=0x0004; RP=0x0020*/ +/* +* Number of credits that should be advertised for Posted headers received + * on Virtual Channel 0. The sum of the posted, non posted, and completion + * header credits must be <= 80; EP=0x0004; RP=0x0020 +*/ #undef PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_DEFVAL #undef PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_SHIFT #undef PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_MASK -#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_DEFVAL 0x00007E04 -#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_SHIFT 0 -#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_MASK 0x0000007FU +#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_DEFVAL 0x00007E04 +#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_SHIFT 0 +#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_MASK 0x0000007FU -/*Specifies values to be transferred to Header Type register. Bit 7 should be set to '0' indicating single-function device. Bit - 0 identifies header as Type 0 or Type 1, with '0' indicating a Type 0 header.; EP=0x0000; RP=0x0001*/ +/* +* Specifies values to be transferred to Header Type register. Bit 7 should + * be set to '0' indicating single-function device. Bit 0 identifies heade + * r as Type 0 or Type 1, with '0' indicating a Type 0 header.; EP=0x0000; + * RP=0x0001 +*/ #undef PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_DEFVAL #undef PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_SHIFT #undef PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_MASK -#define PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_DEFVAL 0x00000100 -#define PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_SHIFT 0 -#define PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_MASK 0x000000FFU +#define PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_DEFVAL 0x00000100 +#define PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_SHIFT 0 +#define PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_MASK 0x000000FFU -/*PM Capability's Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capabil - ty.; EP=0x0048; RP=0x0060*/ +/* +* PM Capability's Next Capability Offset pointer to the next item in the c + * apabilities list, or 00h if this is the final capability.; EP=0x0048; RP + * =0x0060 +*/ #undef PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_DEFVAL #undef PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_SHIFT #undef PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_MASK -#define PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_DEFVAL 0x00003D48 -#define PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_SHIFT 0 -#define PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_MASK 0x000000FFU +#define PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_DEFVAL 0x00003D48 +#define PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_SHIFT 0 +#define PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_MASK 0x000000FFU -/*MSI Per-Vector Masking Capable. The value is transferred to the MSI Control Register[8]. When set, adds Mask and Pending Dwor - to Cap structure; EP=0x0000; RP=0x0000*/ +/* +* MSI Per-Vector Masking Capable. The value is transferred to the MSI Cont + * rol Register[8]. When set, adds Mask and Pending Dword to Cap structure; + * EP=0x0000; RP=0x0000 +*/ #undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_DEFVAL #undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_SHIFT #undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_MASK -#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_DEFVAL 0x00000160 -#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_SHIFT 9 -#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_MASK 0x00000200U +#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_DEFVAL 0x00000160 +#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_SHIFT 9 +#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_MASK 0x00000200U -/*Indicates that the MSI structures exists. If this is FALSE, then the MSI structure cannot be accessed via either the link or - he management port.; EP=0x0001; RP=0x0000*/ +/* +* Indicates that the MSI structures exists. If this is FALSE, then the MSI + * structure cannot be accessed via either the link or the management port + * .; EP=0x0001; RP=0x0000 +*/ #undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_DEFVAL #undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_SHIFT #undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_MASK -#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_DEFVAL 0x00000160 -#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_SHIFT 8 -#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_MASK 0x00000100U +#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_DEFVAL 0x00000160 +#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_SHIFT 8 +#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_MASK 0x00000100U -/*MSI Capability's Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capabi - ity.; EP=0x0060; RP=0x0000*/ +/* +* MSI Capability's Next Capability Offset pointer to the next item in the + * capabilities list, or 00h if this is the final capability.; EP=0x0060; R + * P=0x0000 +*/ #undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_DEFVAL #undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_SHIFT #undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_MASK -#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_DEFVAL 0x00000160 -#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_SHIFT 0 -#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_MASK 0x000000FFU +#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_DEFVAL 0x00000160 +#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_SHIFT 0 +#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_MASK 0x000000FFU -/*Indicates that the MSI structures exists. If this is FALSE, then the MSI structure cannot be accessed via either the link or - he management port.; EP=0x0001; RP=0x0000*/ +/* +* Indicates that the MSI structures exists. If this is FALSE, then the MSI + * structure cannot be accessed via either the link or the management port + * .; EP=0x0001; RP=0x0000 +*/ #undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_DEFVAL #undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_SHIFT #undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_MASK -#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_DEFVAL 0x00000160 -#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_SHIFT 8 -#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_MASK 0x00000100U +#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_DEFVAL 0x00000160 +#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_SHIFT 8 +#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_MASK 0x00000100U -/*Maximum Link Width. Valid settings are: 000001b x1, 000010b x2, 000100b x4, 001000b x8.; EP=0x0004; RP=0x0004*/ +/* +* Maximum Link Width. Valid settings are: 000001b x1, 000010b x2, 000100b + * x4, 001000b x8.; EP=0x0004; RP=0x0004 +*/ #undef PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_DEFVAL #undef PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_SHIFT #undef PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_MASK -#define PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_DEFVAL 0x00000104 -#define PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_SHIFT 0 -#define PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_MASK 0x0000003FU +#define PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_DEFVAL 0x00000104 +#define PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_SHIFT 0 +#define PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_MASK 0x0000003FU -/*Used by LTSSM to set Maximum Link Width. Valid settings are: 000001b [x1], 000010b [x2], 000100b [x4], 001000b [x8].; EP=0x00 - 4; RP=0x0004*/ +/* +* Used by LTSSM to set Maximum Link Width. Valid settings are: 000001b [x1 + * ], 000010b [x2], 000100b [x4], 001000b [x8].; EP=0x0004; RP=0x0004 +*/ #undef PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_DEFVAL #undef PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_SHIFT #undef PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_MASK -#define PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_DEFVAL 0x00000104 -#define PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_SHIFT 6 -#define PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_MASK 0x00000FC0U +#define PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_DEFVAL 0x00000104 +#define PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_SHIFT 6 +#define PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_MASK 0x00000FC0U -/*TRUE specifies upstream-facing port. FALSE specifies downstream-facing port.; EP=0x0001; RP=0x0000*/ +/* +* TRUE specifies upstream-facing port. FALSE specifies downstream-facing p + * ort.; EP=0x0001; RP=0x0000 +*/ #undef PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_DEFVAL #undef PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_SHIFT #undef PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_MASK -#define PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_DEFVAL 0x000000F0 -#define PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_SHIFT 6 -#define PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_MASK 0x00000040U +#define PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_DEFVAL 0x000000F0 +#define PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_SHIFT 6 +#define PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_MASK 0x00000040U -/*Enable the routing of message TLPs to the user through the TRN RX interface. A bit value of 1 enables routing of the message - LP to the user. Messages are always decoded by the message decoder. Bit 0 - ERR COR, Bit 1 - ERR NONFATAL, Bit 2 - ERR FATAL, - Bit 3 - INTA Bit 4 - INTB, Bit 5 - INTC, Bit 6 - INTD, Bit 7 PM_PME, Bit 8 - PME_TO_ACK, Bit 9 - unlock, Bit 10 PME_Turn_Off; - EP=0x0000; RP=0x07FF*/ +/* +* Enable the routing of message TLPs to the user through the TRN RX interf + * ace. A bit value of 1 enables routing of the message TLP to the user. Me + * ssages are always decoded by the message decoder. Bit 0 - ERR COR, Bit 1 + * - ERR NONFATAL, Bit 2 - ERR FATAL, Bit 3 - INTA Bit 4 - INTB, Bit 5 - I + * NTC, Bit 6 - INTD, Bit 7 PM_PME, Bit 8 - PME_TO_ACK, Bit 9 - unlock, Bit + * 10 PME_Turn_Off; EP=0x0000; RP=0x07FF +*/ #undef PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_DEFVAL #undef PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_SHIFT #undef PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_MASK -#define PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_DEFVAL 0x00000000 -#define PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_SHIFT 5 -#define PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_MASK 0x0000FFE0U +#define PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_DEFVAL 0x00000000 +#define PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_SHIFT 5 +#define PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_MASK 0x0000FFE0U -/*Disable BAR filtering. Does not change the behavior of the bar hit outputs; EP=0x0000; RP=0x0001*/ +/* +* Disable BAR filtering. Does not change the behavior of the bar hit outpu + * ts; EP=0x0000; RP=0x0001 +*/ #undef PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_DEFVAL #undef PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_SHIFT #undef PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_MASK -#define PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_DEFVAL 0x00000000 -#define PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_SHIFT 1 -#define PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_MASK 0x00000002U +#define PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_DEFVAL 0x00000000 +#define PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_SHIFT 1 +#define PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_MASK 0x00000002U -/*Link Bandwidth notification capability. Indicates support for the link bandwidth notification status and interrupt mechanism. - Required for Root.; EP=0x0000; RP=0x0001*/ +/* +* Link Bandwidth notification capability. Indicates support for the link b + * andwidth notification status and interrupt mechanism. Required for Root. + * ; EP=0x0000; RP=0x0001 +*/ #undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_DEFVAL #undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_SHIFT #undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_MASK -#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_DEFVAL 0x000009FF -#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_SHIFT 9 -#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_MASK 0x00000200U +#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_DEFVAL 0x000009FF +#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_SHIFT 9 +#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_MASK 0x00000200U -/*Sets the ASPM Optionality Compliance bit, to comply with the 2.1 ASPM Optionality ECN. Transferred to the Link Capabilities r - gister.; EP=0x0001; RP=0x0001*/ +/* +* Sets the ASPM Optionality Compliance bit, to comply with the 2.1 ASPM Op + * tionality ECN. Transferred to the Link Capabilities register.; EP=0x0001 + * ; RP=0x0001 +*/ #undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_DEFVAL #undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_SHIFT #undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_MASK -#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_DEFVAL 0x000009FF -#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_SHIFT 14 -#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_MASK 0x00004000U +#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_DEFVAL 0x000009FF +#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_SHIFT 14 +#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_MASK 0x00004000U -/*Enables the Replay Timer to use the user-defined LL_REPLAY_TIMEOUT value (or combined with the built-in value, depending on L - _REPLAY_TIMEOUT_FUNC). If FALSE, the built-in value is used.; EP=0x0000; RP=0x0000*/ +/* +* Enables the Replay Timer to use the user-defined LL_REPLAY_TIMEOUT value + * (or combined with the built-in value, depending on LL_REPLAY_TIMEOUT_FU + * NC). If FALSE, the built-in value is used.; EP=0x0000; RP=0x0000 +*/ #undef PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_DEFVAL #undef PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_SHIFT #undef PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_MASK -#define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_DEFVAL 0x00000000 -#define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_SHIFT 15 -#define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_MASK 0x00008000U +#define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_DEFVAL 0x00000000 +#define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_SHIFT 15 +#define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_MASK 0x00008000U -/*Sets a user-defined timeout for the Replay Timer to force cause the retransmission of unacknowledged TLPs; refer to LL_REPLAY - TIMEOUT_EN and LL_REPLAY_TIMEOUT_FUNC to see how this value is used. The unit for this attribute is in symbol times, which is - 4ns at GEN1 speeds and 2ns at GEN2.; EP=0x0000; RP=0x0000*/ +/* +* Sets a user-defined timeout for the Replay Timer to force cause the retr + * ansmission of unacknowledged TLPs; refer to LL_REPLAY_TIMEOUT_EN and LL_ + * REPLAY_TIMEOUT_FUNC to see how this value is used. The unit for this att + * ribute is in symbol times, which is 4ns at GEN1 speeds and 2ns at GEN2.; + * EP=0x0000; RP=0x0000 +*/ #undef PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_DEFVAL #undef PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_SHIFT #undef PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_MASK -#define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_DEFVAL 0x00000000 -#define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_SHIFT 0 -#define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_MASK 0x00007FFFU +#define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_DEFVAL 0x00000000 +#define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_SHIFT 0 +#define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_MASK 0x00007FFFU -/*Device ID for the the PCIe Cap Structure Device ID field*/ +/* +* Device ID for the the PCIe Cap Structure Device ID field +*/ #undef PCIE_ATTRIB_ID_CFG_DEV_ID_DEFVAL #undef PCIE_ATTRIB_ID_CFG_DEV_ID_SHIFT #undef PCIE_ATTRIB_ID_CFG_DEV_ID_MASK -#define PCIE_ATTRIB_ID_CFG_DEV_ID_DEFVAL 0x10EE7024 -#define PCIE_ATTRIB_ID_CFG_DEV_ID_SHIFT 0 -#define PCIE_ATTRIB_ID_CFG_DEV_ID_MASK 0x0000FFFFU +#define PCIE_ATTRIB_ID_CFG_DEV_ID_DEFVAL 0x10EE7024 +#define PCIE_ATTRIB_ID_CFG_DEV_ID_SHIFT 0 +#define PCIE_ATTRIB_ID_CFG_DEV_ID_MASK 0x0000FFFFU -/*Vendor ID for the PCIe Cap Structure Vendor ID field*/ +/* +* Vendor ID for the PCIe Cap Structure Vendor ID field +*/ #undef PCIE_ATTRIB_ID_CFG_VEND_ID_DEFVAL #undef PCIE_ATTRIB_ID_CFG_VEND_ID_SHIFT #undef PCIE_ATTRIB_ID_CFG_VEND_ID_MASK -#define PCIE_ATTRIB_ID_CFG_VEND_ID_DEFVAL 0x10EE7024 -#define PCIE_ATTRIB_ID_CFG_VEND_ID_SHIFT 16 -#define PCIE_ATTRIB_ID_CFG_VEND_ID_MASK 0xFFFF0000U +#define PCIE_ATTRIB_ID_CFG_VEND_ID_DEFVAL 0x10EE7024 +#define PCIE_ATTRIB_ID_CFG_VEND_ID_SHIFT 16 +#define PCIE_ATTRIB_ID_CFG_VEND_ID_MASK 0xFFFF0000U -/*Subsystem ID for the the PCIe Cap Structure Subsystem ID field*/ +/* +* Subsystem ID for the the PCIe Cap Structure Subsystem ID field +*/ #undef PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_DEFVAL #undef PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_SHIFT #undef PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_MASK -#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_DEFVAL 0x10EE0007 -#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_SHIFT 0 -#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_MASK 0x0000FFFFU +#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_DEFVAL 0x10EE0007 +#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_SHIFT 0 +#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_MASK 0x0000FFFFU -/*Subsystem Vendor ID for the PCIe Cap Structure Subsystem Vendor ID field*/ +/* +* Subsystem Vendor ID for the PCIe Cap Structure Subsystem Vendor ID field +*/ #undef PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_DEFVAL #undef PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_SHIFT #undef PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_MASK -#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_DEFVAL 0x10EE0007 -#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_SHIFT 16 -#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_MASK 0xFFFF0000U +#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_DEFVAL 0x10EE0007 +#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_SHIFT 16 +#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_MASK 0xFFFF0000U -/*Revision ID for the the PCIe Cap Structure*/ +/* +* Revision ID for the the PCIe Cap Structure +*/ #undef PCIE_ATTRIB_REV_ID_CFG_REV_ID_DEFVAL #undef PCIE_ATTRIB_REV_ID_CFG_REV_ID_SHIFT #undef PCIE_ATTRIB_REV_ID_CFG_REV_ID_MASK -#define PCIE_ATTRIB_REV_ID_CFG_REV_ID_DEFVAL -#define PCIE_ATTRIB_REV_ID_CFG_REV_ID_SHIFT 0 -#define PCIE_ATTRIB_REV_ID_CFG_REV_ID_MASK 0x000000FFU +#define PCIE_ATTRIB_REV_ID_CFG_REV_ID_DEFVAL +#define PCIE_ATTRIB_REV_ID_CFG_REV_ID_SHIFT 0 +#define PCIE_ATTRIB_REV_ID_CFG_REV_ID_MASK 0x000000FFU -/*Code identifying basic function, subclass and applicable programming interface. Transferred to the Class Code register.; EP=0 - 8000; RP=0x8000*/ +/* +* Code identifying basic function, subclass and applicable programming int + * erface. Transferred to the Class Code register.; EP=0x8000; RP=0x8000 +*/ #undef PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_DEFVAL #undef PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_SHIFT #undef PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_MASK -#define PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_DEFVAL -#define PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_SHIFT 0 -#define PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_MASK 0x0000FFFFU +#define PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_DEFVAL +#define PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_SHIFT 0 +#define PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_MASK 0x0000FFFFU -/*Code identifying basic function, subclass and applicable programming interface. Transferred to the Class Code register.; EP=0 - 0005; RP=0x0006*/ +/* +* Code identifying basic function, subclass and applicable programming int + * erface. Transferred to the Class Code register.; EP=0x0005; RP=0x0006 +*/ #undef PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_DEFVAL #undef PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_SHIFT #undef PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_MASK -#define PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_DEFVAL 0x00000905 -#define PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_SHIFT 0 -#define PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_MASK 0x000000FFU +#define PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_DEFVAL 0x00000905 +#define PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_SHIFT 0 +#define PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_MASK 0x000000FFU -/*INTX Interrupt Generation Capable. If FALSE, this will cause Command[10] to be hardwired to 0.; EP=0x0001; RP=0x0001*/ +/* +* INTX Interrupt Generation Capable. If FALSE, this will cause Command[10] + * to be hardwired to 0.; EP=0x0001; RP=0x0001 +*/ #undef PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_DEFVAL #undef PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_SHIFT #undef PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_MASK -#define PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_DEFVAL 0x00000905 -#define PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_SHIFT 8 -#define PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_MASK 0x00000100U +#define PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_DEFVAL 0x00000905 +#define PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_SHIFT 8 +#define PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_MASK 0x00000100U -/*Indicates that the AER structures exists. If this is FALSE, then the AER structure cannot be accessed via either the link or - he management port, and AER will be considered to not be present for error management tasks (such as what types of error mess - ges are sent if an error is detected).; EP=0x0001; RP=0x0001*/ +/* +* Indicates that the AER structures exists. If this is FALSE, then the AER + * structure cannot be accessed via either the link or the management port + * , and AER will be considered to not be present for error management task + * s (such as what types of error messages are sent if an error is detected + * ).; EP=0x0001; RP=0x0001 +*/ #undef PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_DEFVAL #undef PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_SHIFT #undef PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_MASK -#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_DEFVAL 0x00001000 -#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_SHIFT 12 -#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_MASK 0x00001000U +#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_DEFVAL 0x00001000 +#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_SHIFT 12 +#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_MASK 0x00001000U -/*Indicates that the AER structures exists. If this is FALSE, then the AER structure cannot be accessed via either the link or - he management port, and AER will be considered to not be present for error management tasks (such as what types of error mess - ges are sent if an error is detected).; EP=0x0001; RP=0x0001*/ +/* +* Indicates that the AER structures exists. If this is FALSE, then the AER + * structure cannot be accessed via either the link or the management port + * , and AER will be considered to not be present for error management task + * s (such as what types of error messages are sent if an error is detected + * ).; EP=0x0001; RP=0x0001 +*/ #undef PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_DEFVAL #undef PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_SHIFT #undef PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_MASK -#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_DEFVAL 0x00001000 -#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_SHIFT 12 -#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_MASK 0x00001000U +#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_DEFVAL 0x00001000 +#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_SHIFT 12 +#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_MASK 0x00001000U -/*VSEC's Next Capability Offset pointer to the next item in the capabilities list, or 000h if this is the final capability.; EP - 0x0140; RP=0x0140*/ +/* +* VSEC's Next Capability Offset pointer to the next item in the capabiliti + * es list, or 000h if this is the final capability.; EP=0x0140; RP=0x0140 +*/ #undef PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_DEFVAL #undef PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_SHIFT #undef PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_MASK -#define PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_DEFVAL 0x00002281 -#define PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_SHIFT 1 -#define PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_MASK 0x00001FFEU +#define PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_DEFVAL 0x00002281 +#define PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_SHIFT 1 +#define PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_MASK 0x00001FFEU -/*CRS SW Visibility. Indicates RC can return CRS to SW. Transferred to the Root Capabilities register.; EP=0x0000; RP=0x0000*/ +/* +* CRS SW Visibility. Indicates RC can return CRS to SW. Transferred to the + * Root Capabilities register.; EP=0x0000; RP=0x0000 +*/ #undef PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_DEFVAL #undef PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_SHIFT #undef PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_MASK -#define PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_DEFVAL 0x00000000 -#define PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_SHIFT 5 -#define PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_MASK 0x00000020U +#define PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_DEFVAL 0x00000000 +#define PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_SHIFT 5 +#define PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_MASK 0x00000020U -/*Indicates that the MSIX structures exists. If this is FALSE, then the MSIX structure cannot be accessed via either the link o - the management port.; EP=0x0001; RP=0x0000*/ +/* +* Indicates that the MSIX structures exists. If this is FALSE, then the MS + * IX structure cannot be accessed via either the link or the management po + * rt.; EP=0x0001; RP=0x0000 +*/ #undef PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_DEFVAL #undef PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_SHIFT #undef PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_MASK -#define PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_DEFVAL 0x00000100 -#define PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_SHIFT 8 -#define PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_MASK 0x00000100U +#define PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_DEFVAL 0x00000100 +#define PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_SHIFT 8 +#define PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_MASK 0x00000100U -/*MSI-X Table Size. This value is transferred to the MSI-X Message Control[10:0] field. Set to 0 if MSI-X is not enabled. Note - hat the core does not implement the table; that must be implemented in user logic.; EP=0x0003; RP=0x0000*/ +/* +* MSI-X Table Size. This value is transferred to the MSI-X Message Control + * [10:0] field. Set to 0 if MSI-X is not enabled. Note that the core does + * not implement the table; that must be implemented in user logic.; EP=0x0 + * 003; RP=0x0000 +*/ #undef PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_DEFVAL #undef PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_SHIFT #undef PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_MASK -#define PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_DEFVAL -#define PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_SHIFT 0 -#define PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_MASK 0x000007FFU +#define PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_DEFVAL +#define PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_SHIFT 0 +#define PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_MASK 0x000007FFU -/*MSI-X Table Offset. This value is transferred to the MSI-X Table Offset field. Set to 0 if MSI-X is not enabled.; EP=0x0001; - P=0x0000*/ +/* +* MSI-X Table Offset. This value is transferred to the MSI-X Table Offset + * field. Set to 0 if MSI-X is not enabled.; EP=0x0001; RP=0x0000 +*/ #undef PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_DEFVAL #undef PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_SHIFT #undef PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_MASK -#define PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_DEFVAL -#define PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_SHIFT 0 -#define PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_MASK 0x0000FFFFU +#define PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_DEFVAL +#define PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_SHIFT 0 +#define PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_MASK 0x0000FFFFU -/*MSI-X Table Offset. This value is transferred to the MSI-X Table Offset field. Set to 0 if MSI-X is not enabled.; EP=0x0000; - P=0x0000*/ +/* +* MSI-X Table Offset. This value is transferred to the MSI-X Table Offset + * field. Set to 0 if MSI-X is not enabled.; EP=0x0000; RP=0x0000 +*/ #undef PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_DEFVAL #undef PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_SHIFT #undef PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_MASK -#define PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_DEFVAL -#define PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_SHIFT 0 -#define PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_MASK 0x00001FFFU +#define PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_DEFVAL +#define PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_SHIFT 0 +#define PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_MASK 0x00001FFFU -/*MSI-X Pending Bit Array Offset This value is transferred to the MSI-X PBA Offset field. Set to 0 if MSI-X is not enabled.; EP - 0x0001; RP=0x0000*/ +/* +* MSI-X Pending Bit Array Offset This value is transferred to the MSI-X PB + * A Offset field. Set to 0 if MSI-X is not enabled.; EP=0x0001; RP=0x0000 +*/ #undef PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_DEFVAL #undef PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_SHIFT #undef PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_MASK -#define PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_DEFVAL -#define PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_SHIFT 0 -#define PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_MASK 0x0000FFFFU +#define PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_DEFVAL +#define PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_SHIFT 0 +#define PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_MASK 0x0000FFFFU -/*MSI-X Pending Bit Array Offset This value is transferred to the MSI-X PBA Offset field. Set to 0 if MSI-X is not enabled.; EP - 0x1000; RP=0x0000*/ +/* +* MSI-X Pending Bit Array Offset This value is transferred to the MSI-X PB + * A Offset field. Set to 0 if MSI-X is not enabled.; EP=0x1000; RP=0x0000 +*/ #undef PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_DEFVAL #undef PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_SHIFT #undef PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_MASK -#define PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_DEFVAL 0x00008000 -#define PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_SHIFT 3 -#define PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_MASK 0x0000FFF8U +#define PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_DEFVAL 0x00008000 +#define PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_SHIFT 3 +#define PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_MASK 0x0000FFF8U -/*DT837748 Enable*/ +/* +* DT837748 Enable +*/ #undef PCIE_ATTRIB_CB_CB1_DEFVAL #undef PCIE_ATTRIB_CB_CB1_SHIFT #undef PCIE_ATTRIB_CB_CB1_MASK -#define PCIE_ATTRIB_CB_CB1_DEFVAL 0x00000001 -#define PCIE_ATTRIB_CB_CB1_SHIFT 1 -#define PCIE_ATTRIB_CB_CB1_MASK 0x00000002U +#define PCIE_ATTRIB_CB_CB1_DEFVAL 0x00000001 +#define PCIE_ATTRIB_CB_CB1_SHIFT 1 +#define PCIE_ATTRIB_CB_CB1_MASK 0x00000002U -/*Active State PM Support. Indicates the level of active state power management supported by the selected PCI Express Link, enc - ded as follows: 0 Reserved, 1 L0s entry supported, 2 Reserved, 3 L0s and L1 entry supported.; EP=0x0001; RP=0x0001*/ +/* +* Active State PM Support. Indicates the level of active state power manag + * ement supported by the selected PCI Express Link, encoded as follows: 0 + * Reserved, 1 L0s entry supported, 2 Reserved, 3 L0s and L1 entry supporte + * d.; EP=0x0001; RP=0x0001 +*/ #undef PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_DEFVAL #undef PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_SHIFT #undef PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_MASK -#define PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_DEFVAL 0x00001FFD -#define PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_SHIFT 12 -#define PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_MASK 0x00003000U +#define PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_DEFVAL 0x00001FFD +#define PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_SHIFT 12 +#define PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_MASK 0x00003000U -/*PCIE control block level reset*/ +/* +* PCIE control block level reset +*/ #undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL #undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT #undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK -#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL 0x000F9FFE -#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT 17 -#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK 0x00020000U +#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT 17 +#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK 0x00020000U -/*Status Read value of PLL Lock*/ +/* +* Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW] +*/ +#undef GPIO_MASK_DATA_1_LSW_MASK_1_LSW_DEFVAL +#undef GPIO_MASK_DATA_1_LSW_MASK_1_LSW_SHIFT +#undef GPIO_MASK_DATA_1_LSW_MASK_1_LSW_MASK +#define GPIO_MASK_DATA_1_LSW_MASK_1_LSW_DEFVAL 0x00000000 +#define GPIO_MASK_DATA_1_LSW_MASK_1_LSW_SHIFT 16 +#define GPIO_MASK_DATA_1_LSW_MASK_1_LSW_MASK 0xFFFF0000U + +/* +* Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW] +*/ +#undef GPIO_MASK_DATA_1_LSW_DATA_1_LSW_DEFVAL +#undef GPIO_MASK_DATA_1_LSW_DATA_1_LSW_SHIFT +#undef GPIO_MASK_DATA_1_LSW_DATA_1_LSW_MASK +#define GPIO_MASK_DATA_1_LSW_DATA_1_LSW_DEFVAL 0x00000000 +#define GPIO_MASK_DATA_1_LSW_DATA_1_LSW_SHIFT 0 +#define GPIO_MASK_DATA_1_LSW_DATA_1_LSW_MASK 0x0000FFFFU + +/* +* Status Read value of PLL Lock +*/ #undef SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL #undef SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT #undef SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK -#define SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL 0x00000001 -#define SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT 4 -#define SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK 0x00000010U +#define SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL 0x00000001 +#define SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT 4 +#define SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK 0x00000010U #define SERDES_L0_PLL_STATUS_READ_1_OFFSET 0XFD4023E4 -/*Status Read value of PLL Lock*/ +/* +* Status Read value of PLL Lock +*/ #undef SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL #undef SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT #undef SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK -#define SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL 0x00000001 -#define SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT 4 -#define SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK 0x00000010U +#define SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL 0x00000001 +#define SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT 4 +#define SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK 0x00000010U #define SERDES_L1_PLL_STATUS_READ_1_OFFSET 0XFD4063E4 -/*Status Read value of PLL Lock*/ +/* +* Status Read value of PLL Lock +*/ #undef SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL #undef SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT #undef SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK -#define SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL 0x00000001 -#define SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT 4 -#define SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK 0x00000010U +#define SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL 0x00000001 +#define SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT 4 +#define SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK 0x00000010U #define SERDES_L2_PLL_STATUS_READ_1_OFFSET 0XFD40A3E4 -/*Status Read value of PLL Lock*/ +/* +* Status Read value of PLL Lock +*/ #undef SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL #undef SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT #undef SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK -#define SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL 0x00000001 -#define SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT 4 -#define SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK 0x00000010U +#define SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL 0x00000001 +#define SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT 4 +#define SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK 0x00000010U #define SERDES_L3_PLL_STATUS_READ_1_OFFSET 0XFD40E3E4 -/*CIBGMN: COMINIT Burst Gap Minimum.*/ +/* +* CIBGMN: COMINIT Burst Gap Minimum. +*/ #undef SATA_AHCI_VENDOR_PP2C_CIBGMN_DEFVAL #undef SATA_AHCI_VENDOR_PP2C_CIBGMN_SHIFT #undef SATA_AHCI_VENDOR_PP2C_CIBGMN_MASK -#define SATA_AHCI_VENDOR_PP2C_CIBGMN_DEFVAL 0x28184D1B -#define SATA_AHCI_VENDOR_PP2C_CIBGMN_SHIFT 0 -#define SATA_AHCI_VENDOR_PP2C_CIBGMN_MASK 0x000000FFU +#define SATA_AHCI_VENDOR_PP2C_CIBGMN_DEFVAL 0x28184D1B +#define SATA_AHCI_VENDOR_PP2C_CIBGMN_SHIFT 0 +#define SATA_AHCI_VENDOR_PP2C_CIBGMN_MASK 0x000000FFU -/*CIBGMX: COMINIT Burst Gap Maximum.*/ +/* +* CIBGMX: COMINIT Burst Gap Maximum. +*/ #undef SATA_AHCI_VENDOR_PP2C_CIBGMX_DEFVAL #undef SATA_AHCI_VENDOR_PP2C_CIBGMX_SHIFT #undef SATA_AHCI_VENDOR_PP2C_CIBGMX_MASK -#define SATA_AHCI_VENDOR_PP2C_CIBGMX_DEFVAL 0x28184D1B -#define SATA_AHCI_VENDOR_PP2C_CIBGMX_SHIFT 8 -#define SATA_AHCI_VENDOR_PP2C_CIBGMX_MASK 0x0000FF00U +#define SATA_AHCI_VENDOR_PP2C_CIBGMX_DEFVAL 0x28184D1B +#define SATA_AHCI_VENDOR_PP2C_CIBGMX_SHIFT 8 +#define SATA_AHCI_VENDOR_PP2C_CIBGMX_MASK 0x0000FF00U -/*CIBGN: COMINIT Burst Gap Nominal.*/ +/* +* CIBGN: COMINIT Burst Gap Nominal. +*/ #undef SATA_AHCI_VENDOR_PP2C_CIBGN_DEFVAL #undef SATA_AHCI_VENDOR_PP2C_CIBGN_SHIFT #undef SATA_AHCI_VENDOR_PP2C_CIBGN_MASK -#define SATA_AHCI_VENDOR_PP2C_CIBGN_DEFVAL 0x28184D1B -#define SATA_AHCI_VENDOR_PP2C_CIBGN_SHIFT 16 -#define SATA_AHCI_VENDOR_PP2C_CIBGN_MASK 0x00FF0000U +#define SATA_AHCI_VENDOR_PP2C_CIBGN_DEFVAL 0x28184D1B +#define SATA_AHCI_VENDOR_PP2C_CIBGN_SHIFT 16 +#define SATA_AHCI_VENDOR_PP2C_CIBGN_MASK 0x00FF0000U -/*CINMP: COMINIT Negate Minimum Period.*/ +/* +* CINMP: COMINIT Negate Minimum Period. +*/ #undef SATA_AHCI_VENDOR_PP2C_CINMP_DEFVAL #undef SATA_AHCI_VENDOR_PP2C_CINMP_SHIFT #undef SATA_AHCI_VENDOR_PP2C_CINMP_MASK -#define SATA_AHCI_VENDOR_PP2C_CINMP_DEFVAL 0x28184D1B -#define SATA_AHCI_VENDOR_PP2C_CINMP_SHIFT 24 -#define SATA_AHCI_VENDOR_PP2C_CINMP_MASK 0xFF000000U +#define SATA_AHCI_VENDOR_PP2C_CINMP_DEFVAL 0x28184D1B +#define SATA_AHCI_VENDOR_PP2C_CINMP_SHIFT 24 +#define SATA_AHCI_VENDOR_PP2C_CINMP_MASK 0xFF000000U -/*CWBGMN: COMWAKE Burst Gap Minimum.*/ +/* +* CWBGMN: COMWAKE Burst Gap Minimum. +*/ #undef SATA_AHCI_VENDOR_PP3C_CWBGMN_DEFVAL #undef SATA_AHCI_VENDOR_PP3C_CWBGMN_SHIFT #undef SATA_AHCI_VENDOR_PP3C_CWBGMN_MASK -#define SATA_AHCI_VENDOR_PP3C_CWBGMN_DEFVAL 0x0E081906 -#define SATA_AHCI_VENDOR_PP3C_CWBGMN_SHIFT 0 -#define SATA_AHCI_VENDOR_PP3C_CWBGMN_MASK 0x000000FFU +#define SATA_AHCI_VENDOR_PP3C_CWBGMN_DEFVAL 0x0E081906 +#define SATA_AHCI_VENDOR_PP3C_CWBGMN_SHIFT 0 +#define SATA_AHCI_VENDOR_PP3C_CWBGMN_MASK 0x000000FFU -/*CWBGMX: COMWAKE Burst Gap Maximum.*/ +/* +* CWBGMX: COMWAKE Burst Gap Maximum. +*/ #undef SATA_AHCI_VENDOR_PP3C_CWBGMX_DEFVAL #undef SATA_AHCI_VENDOR_PP3C_CWBGMX_SHIFT #undef SATA_AHCI_VENDOR_PP3C_CWBGMX_MASK -#define SATA_AHCI_VENDOR_PP3C_CWBGMX_DEFVAL 0x0E081906 -#define SATA_AHCI_VENDOR_PP3C_CWBGMX_SHIFT 8 -#define SATA_AHCI_VENDOR_PP3C_CWBGMX_MASK 0x0000FF00U +#define SATA_AHCI_VENDOR_PP3C_CWBGMX_DEFVAL 0x0E081906 +#define SATA_AHCI_VENDOR_PP3C_CWBGMX_SHIFT 8 +#define SATA_AHCI_VENDOR_PP3C_CWBGMX_MASK 0x0000FF00U -/*CWBGN: COMWAKE Burst Gap Nominal.*/ +/* +* CWBGN: COMWAKE Burst Gap Nominal. +*/ #undef SATA_AHCI_VENDOR_PP3C_CWBGN_DEFVAL #undef SATA_AHCI_VENDOR_PP3C_CWBGN_SHIFT #undef SATA_AHCI_VENDOR_PP3C_CWBGN_MASK -#define SATA_AHCI_VENDOR_PP3C_CWBGN_DEFVAL 0x0E081906 -#define SATA_AHCI_VENDOR_PP3C_CWBGN_SHIFT 16 -#define SATA_AHCI_VENDOR_PP3C_CWBGN_MASK 0x00FF0000U +#define SATA_AHCI_VENDOR_PP3C_CWBGN_DEFVAL 0x0E081906 +#define SATA_AHCI_VENDOR_PP3C_CWBGN_SHIFT 16 +#define SATA_AHCI_VENDOR_PP3C_CWBGN_MASK 0x00FF0000U -/*CWNMP: COMWAKE Negate Minimum Period.*/ +/* +* CWNMP: COMWAKE Negate Minimum Period. +*/ #undef SATA_AHCI_VENDOR_PP3C_CWNMP_DEFVAL #undef SATA_AHCI_VENDOR_PP3C_CWNMP_SHIFT #undef SATA_AHCI_VENDOR_PP3C_CWNMP_MASK -#define SATA_AHCI_VENDOR_PP3C_CWNMP_DEFVAL 0x0E081906 -#define SATA_AHCI_VENDOR_PP3C_CWNMP_SHIFT 24 -#define SATA_AHCI_VENDOR_PP3C_CWNMP_MASK 0xFF000000U +#define SATA_AHCI_VENDOR_PP3C_CWNMP_DEFVAL 0x0E081906 +#define SATA_AHCI_VENDOR_PP3C_CWNMP_SHIFT 24 +#define SATA_AHCI_VENDOR_PP3C_CWNMP_MASK 0xFF000000U -/*BMX: COM Burst Maximum.*/ +/* +* BMX: COM Burst Maximum. +*/ #undef SATA_AHCI_VENDOR_PP4C_BMX_DEFVAL #undef SATA_AHCI_VENDOR_PP4C_BMX_SHIFT #undef SATA_AHCI_VENDOR_PP4C_BMX_MASK -#define SATA_AHCI_VENDOR_PP4C_BMX_DEFVAL 0x064A0813 -#define SATA_AHCI_VENDOR_PP4C_BMX_SHIFT 0 -#define SATA_AHCI_VENDOR_PP4C_BMX_MASK 0x000000FFU +#define SATA_AHCI_VENDOR_PP4C_BMX_DEFVAL 0x064A0813 +#define SATA_AHCI_VENDOR_PP4C_BMX_SHIFT 0 +#define SATA_AHCI_VENDOR_PP4C_BMX_MASK 0x000000FFU -/*BNM: COM Burst Nominal.*/ +/* +* BNM: COM Burst Nominal. +*/ #undef SATA_AHCI_VENDOR_PP4C_BNM_DEFVAL #undef SATA_AHCI_VENDOR_PP4C_BNM_SHIFT #undef SATA_AHCI_VENDOR_PP4C_BNM_MASK -#define SATA_AHCI_VENDOR_PP4C_BNM_DEFVAL 0x064A0813 -#define SATA_AHCI_VENDOR_PP4C_BNM_SHIFT 8 -#define SATA_AHCI_VENDOR_PP4C_BNM_MASK 0x0000FF00U +#define SATA_AHCI_VENDOR_PP4C_BNM_DEFVAL 0x064A0813 +#define SATA_AHCI_VENDOR_PP4C_BNM_SHIFT 8 +#define SATA_AHCI_VENDOR_PP4C_BNM_MASK 0x0000FF00U -/*SFD: Signal Failure Detection, if the signal detection de-asserts for a time greater than this then the OOB detector will det - rmine this is a line idle and cause the PhyInit state machine to exit the Phy Ready State. A value of zero disables the Signa - Failure Detector. The value is based on the OOB Detector Clock typically (PMCLK Clock Period) * SFD giving a nominal time of - 500ns based on a 150MHz PMCLK.*/ +/* +* SFD: Signal Failure Detection, if the signal detection de-asserts for a + * time greater than this then the OOB detector will determine this is a li + * ne idle and cause the PhyInit state machine to exit the Phy Ready State. + * A value of zero disables the Signal Failure Detector. The value is base + * d on the OOB Detector Clock typically (PMCLK Clock Period) * SFD giving + * a nominal time of 500ns based on a 150MHz PMCLK. +*/ #undef SATA_AHCI_VENDOR_PP4C_SFD_DEFVAL #undef SATA_AHCI_VENDOR_PP4C_SFD_SHIFT #undef SATA_AHCI_VENDOR_PP4C_SFD_MASK -#define SATA_AHCI_VENDOR_PP4C_SFD_DEFVAL 0x064A0813 -#define SATA_AHCI_VENDOR_PP4C_SFD_SHIFT 16 -#define SATA_AHCI_VENDOR_PP4C_SFD_MASK 0x00FF0000U +#define SATA_AHCI_VENDOR_PP4C_SFD_DEFVAL 0x064A0813 +#define SATA_AHCI_VENDOR_PP4C_SFD_SHIFT 16 +#define SATA_AHCI_VENDOR_PP4C_SFD_MASK 0x00FF0000U -/*PTST: Partial to Slumber timer value, specific delay the controller should apply while in partial before entering slumber. Th - value is bases on the system clock divided by 128, total delay = (Sys Clock Period) * PTST * 128*/ +/* +* PTST: Partial to Slumber timer value, specific delay the controller shou + * ld apply while in partial before entering slumber. The value is bases on + * the system clock divided by 128, total delay = (Sys Clock Period) * PTS + * T * 128 +*/ #undef SATA_AHCI_VENDOR_PP4C_PTST_DEFVAL #undef SATA_AHCI_VENDOR_PP4C_PTST_SHIFT #undef SATA_AHCI_VENDOR_PP4C_PTST_MASK -#define SATA_AHCI_VENDOR_PP4C_PTST_DEFVAL 0x064A0813 -#define SATA_AHCI_VENDOR_PP4C_PTST_SHIFT 24 -#define SATA_AHCI_VENDOR_PP4C_PTST_MASK 0xFF000000U +#define SATA_AHCI_VENDOR_PP4C_PTST_DEFVAL 0x064A0813 +#define SATA_AHCI_VENDOR_PP4C_PTST_SHIFT 24 +#define SATA_AHCI_VENDOR_PP4C_PTST_MASK 0xFF000000U -/*RIT: Retry Interval Timer. The calculated value divided by two, the lower digit of precision is not needed.*/ +/* +* RIT: Retry Interval Timer. The calculated value divided by two, the lowe + * r digit of precision is not needed. +*/ #undef SATA_AHCI_VENDOR_PP5C_RIT_DEFVAL #undef SATA_AHCI_VENDOR_PP5C_RIT_SHIFT #undef SATA_AHCI_VENDOR_PP5C_RIT_MASK -#define SATA_AHCI_VENDOR_PP5C_RIT_DEFVAL 0x3FFC96A4 -#define SATA_AHCI_VENDOR_PP5C_RIT_SHIFT 0 -#define SATA_AHCI_VENDOR_PP5C_RIT_MASK 0x000FFFFFU +#define SATA_AHCI_VENDOR_PP5C_RIT_DEFVAL 0x3FFC96A4 +#define SATA_AHCI_VENDOR_PP5C_RIT_SHIFT 0 +#define SATA_AHCI_VENDOR_PP5C_RIT_MASK 0x000FFFFFU -/*RCT: Rate Change Timer, a value based on the 54.2us for which a SATA device will transmit at a fixed rate ALIGNp after OOB ha - completed, for a fast SERDES it is suggested that this value be 54.2us / 4*/ +/* +* RCT: Rate Change Timer, a value based on the 54.2us for which a SATA dev + * ice will transmit at a fixed rate ALIGNp after OOB has completed, for a + * fast SERDES it is suggested that this value be 54.2us / 4 +*/ #undef SATA_AHCI_VENDOR_PP5C_RCT_DEFVAL #undef SATA_AHCI_VENDOR_PP5C_RCT_SHIFT #undef SATA_AHCI_VENDOR_PP5C_RCT_MASK -#define SATA_AHCI_VENDOR_PP5C_RCT_DEFVAL 0x3FFC96A4 -#define SATA_AHCI_VENDOR_PP5C_RCT_SHIFT 20 -#define SATA_AHCI_VENDOR_PP5C_RCT_MASK 0xFFF00000U +#define SATA_AHCI_VENDOR_PP5C_RCT_DEFVAL 0x3FFC96A4 +#define SATA_AHCI_VENDOR_PP5C_RCT_SHIFT 20 +#define SATA_AHCI_VENDOR_PP5C_RCT_MASK 0xFFF00000U #undef CRL_APB_RST_LPD_TOP_OFFSET #define CRL_APB_RST_LPD_TOP_OFFSET 0XFF5E023C #undef CRL_APB_RST_LPD_IOU0_OFFSET @@ -27671,123 +36135,252 @@ #undef CRF_APB_RST_FPD_TOP_OFFSET #define CRF_APB_RST_FPD_TOP_OFFSET 0XFD1A0100 -/*USB 0 reset for control registers*/ +/* +* USB 0 reset for control registers +*/ #undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL #undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT #undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK -#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL 0x00188FDF -#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT 10 -#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK 0x00000400U +#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT 10 +#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK 0x00000400U -/*USB 0 sleep circuit reset*/ +/* +* USB 0 sleep circuit reset +*/ #undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL #undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT #undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK -#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL 0x00188FDF -#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT 8 -#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK 0x00000100U +#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT 8 +#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK 0x00000100U -/*USB 0 reset*/ +/* +* USB 0 reset +*/ #undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL #undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT #undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK -#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL 0x00188FDF -#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT 6 -#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK 0x00000040U +#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT 6 +#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK 0x00000040U -/*GEM 3 reset*/ +/* +* GEM 3 reset +*/ #undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL #undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT #undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK -#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL 0x0000000F -#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT 3 -#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK 0x00000008U +#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL 0x0000000F +#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT 3 +#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK 0x00000008U -/*Sata block level reset*/ +/* +* Sata block level reset +*/ #undef CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL #undef CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT #undef CRF_APB_RST_FPD_TOP_SATA_RESET_MASK -#define CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL 0x000F9FFE -#define CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT 1 -#define CRF_APB_RST_FPD_TOP_SATA_RESET_MASK 0x00000002U +#define CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT 1 +#define CRF_APB_RST_FPD_TOP_SATA_RESET_MASK 0x00000002U -/*PCIE config reset*/ +/* +* PCIE config reset +*/ #undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL #undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT #undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK -#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL 0x000F9FFE -#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT 19 -#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK 0x00080000U +#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT 19 +#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK 0x00080000U -/*PCIE control block level reset*/ +/* +* PCIE control block level reset +*/ #undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL #undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT #undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK -#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL 0x000F9FFE -#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT 17 -#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK 0x00020000U +#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT 17 +#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK 0x00020000U -/*PCIE bridge block level reset (AXI interface)*/ +/* +* PCIE bridge block level reset (AXI interface) +*/ #undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL #undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT #undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK -#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL 0x000F9FFE -#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT 18 -#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK 0x00040000U +#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT 18 +#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK 0x00040000U -/*Two bits per lane. When set to 11, moves the GT to power down mode. When set to 00, GT will be in active state. bits [1:0] - - ane0 Bits [3:2] - lane 1*/ +/* +* Two bits per lane. When set to 11, moves the GT to power down mode. When + * set to 00, GT will be in active state. bits [1:0] - lane0 Bits [3:2] - + * lane 1 +*/ #undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_DEFVAL #undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT #undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK -#define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_DEFVAL 0x00000000 -#define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT 0 -#define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK 0x0000000FU +#define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_DEFVAL 0x00000000 +#define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT 0 +#define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK 0x0000000FU -/*Set to '1' to hold the GT in reset. Clear to release.*/ +/* +* Set to '1' to hold the GT in reset. Clear to release. +*/ #undef DP_DP_PHY_RESET_GT_RESET_DEFVAL #undef DP_DP_PHY_RESET_GT_RESET_SHIFT #undef DP_DP_PHY_RESET_GT_RESET_MASK -#define DP_DP_PHY_RESET_GT_RESET_DEFVAL 0x00010003 -#define DP_DP_PHY_RESET_GT_RESET_SHIFT 1 -#define DP_DP_PHY_RESET_GT_RESET_MASK 0x00000002U +#define DP_DP_PHY_RESET_GT_RESET_DEFVAL 0x00010003 +#define DP_DP_PHY_RESET_GT_RESET_SHIFT 1 +#define DP_DP_PHY_RESET_GT_RESET_MASK 0x00000002U -/*Display Port block level reset (includes DPDMA)*/ +/* +* Display Port block level reset (includes DPDMA) +*/ #undef CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL #undef CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT #undef CRF_APB_RST_FPD_TOP_DP_RESET_MASK -#define CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL 0x000F9FFE -#define CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT 16 -#define CRF_APB_RST_FPD_TOP_DP_RESET_MASK 0x00010000U +#define CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT 16 +#define CRF_APB_RST_FPD_TOP_DP_RESET_MASK 0x00010000U #undef PMU_GLOBAL_REQ_PWRUP_INT_EN_OFFSET #define PMU_GLOBAL_REQ_PWRUP_INT_EN_OFFSET 0XFFD80118 #undef PMU_GLOBAL_REQ_PWRUP_TRIG_OFFSET #define PMU_GLOBAL_REQ_PWRUP_TRIG_OFFSET 0XFFD80120 -/*Power-up Request Interrupt Enable for PL*/ +/* +* Power-up Request Interrupt Enable for PL +*/ #undef PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_DEFVAL #undef PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_SHIFT #undef PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_MASK -#define PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_DEFVAL 0x00000000 -#define PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_SHIFT 23 -#define PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_MASK 0x00800000U +#define PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_DEFVAL 0x00000000 +#define PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_SHIFT 23 +#define PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_MASK 0x00800000U -/*Power-up Request Trigger for PL*/ +/* +* Power-up Request Trigger for PL +*/ #undef PMU_GLOBAL_REQ_PWRUP_TRIG_PL_DEFVAL #undef PMU_GLOBAL_REQ_PWRUP_TRIG_PL_SHIFT #undef PMU_GLOBAL_REQ_PWRUP_TRIG_PL_MASK -#define PMU_GLOBAL_REQ_PWRUP_TRIG_PL_DEFVAL 0x00000000 -#define PMU_GLOBAL_REQ_PWRUP_TRIG_PL_SHIFT 23 -#define PMU_GLOBAL_REQ_PWRUP_TRIG_PL_MASK 0x00800000U +#define PMU_GLOBAL_REQ_PWRUP_TRIG_PL_DEFVAL 0x00000000 +#define PMU_GLOBAL_REQ_PWRUP_TRIG_PL_SHIFT 23 +#define PMU_GLOBAL_REQ_PWRUP_TRIG_PL_MASK 0x00800000U -/*Power-up Request Status for PL*/ +/* +* Power-up Request Status for PL +*/ #undef PMU_GLOBAL_REQ_PWRUP_STATUS_PL_DEFVAL #undef PMU_GLOBAL_REQ_PWRUP_STATUS_PL_SHIFT #undef PMU_GLOBAL_REQ_PWRUP_STATUS_PL_MASK -#define PMU_GLOBAL_REQ_PWRUP_STATUS_PL_DEFVAL 0x00000000 -#define PMU_GLOBAL_REQ_PWRUP_STATUS_PL_SHIFT 23 -#define PMU_GLOBAL_REQ_PWRUP_STATUS_PL_MASK 0x00800000U +#define PMU_GLOBAL_REQ_PWRUP_STATUS_PL_DEFVAL 0x00000000 +#define PMU_GLOBAL_REQ_PWRUP_STATUS_PL_SHIFT 23 +#define PMU_GLOBAL_REQ_PWRUP_STATUS_PL_MASK 0x00800000U #define PMU_GLOBAL_REQ_PWRUP_STATUS_OFFSET 0XFFD80110 +#undef CRF_APB_RST_FPD_TOP_OFFSET +#define CRF_APB_RST_FPD_TOP_OFFSET 0XFD1A0100 +#undef CRL_APB_RST_LPD_TOP_OFFSET +#define CRL_APB_RST_LPD_TOP_OFFSET 0XFF5E023C +#undef FPD_SLCR_AFI_FS_OFFSET +#define FPD_SLCR_AFI_FS_OFFSET 0XFD615000 + +/* +* AF_FM0 block level reset +*/ +#undef CRF_APB_RST_FPD_TOP_AFI_FM0_RESET_DEFVAL +#undef CRF_APB_RST_FPD_TOP_AFI_FM0_RESET_SHIFT +#undef CRF_APB_RST_FPD_TOP_AFI_FM0_RESET_MASK +#define CRF_APB_RST_FPD_TOP_AFI_FM0_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_AFI_FM0_RESET_SHIFT 7 +#define CRF_APB_RST_FPD_TOP_AFI_FM0_RESET_MASK 0x00000080U + +/* +* AF_FM1 block level reset +*/ +#undef CRF_APB_RST_FPD_TOP_AFI_FM1_RESET_DEFVAL +#undef CRF_APB_RST_FPD_TOP_AFI_FM1_RESET_SHIFT +#undef CRF_APB_RST_FPD_TOP_AFI_FM1_RESET_MASK +#define CRF_APB_RST_FPD_TOP_AFI_FM1_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_AFI_FM1_RESET_SHIFT 8 +#define CRF_APB_RST_FPD_TOP_AFI_FM1_RESET_MASK 0x00000100U + +/* +* AF_FM2 block level reset +*/ +#undef CRF_APB_RST_FPD_TOP_AFI_FM2_RESET_DEFVAL +#undef CRF_APB_RST_FPD_TOP_AFI_FM2_RESET_SHIFT +#undef CRF_APB_RST_FPD_TOP_AFI_FM2_RESET_MASK +#define CRF_APB_RST_FPD_TOP_AFI_FM2_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_AFI_FM2_RESET_SHIFT 9 +#define CRF_APB_RST_FPD_TOP_AFI_FM2_RESET_MASK 0x00000200U + +/* +* AF_FM3 block level reset +*/ +#undef CRF_APB_RST_FPD_TOP_AFI_FM3_RESET_DEFVAL +#undef CRF_APB_RST_FPD_TOP_AFI_FM3_RESET_SHIFT +#undef CRF_APB_RST_FPD_TOP_AFI_FM3_RESET_MASK +#define CRF_APB_RST_FPD_TOP_AFI_FM3_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_AFI_FM3_RESET_SHIFT 10 +#define CRF_APB_RST_FPD_TOP_AFI_FM3_RESET_MASK 0x00000400U + +/* +* AF_FM4 block level reset +*/ +#undef CRF_APB_RST_FPD_TOP_AFI_FM4_RESET_DEFVAL +#undef CRF_APB_RST_FPD_TOP_AFI_FM4_RESET_SHIFT +#undef CRF_APB_RST_FPD_TOP_AFI_FM4_RESET_MASK +#define CRF_APB_RST_FPD_TOP_AFI_FM4_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_AFI_FM4_RESET_SHIFT 11 +#define CRF_APB_RST_FPD_TOP_AFI_FM4_RESET_MASK 0x00000800U + +/* +* AF_FM5 block level reset +*/ +#undef CRF_APB_RST_FPD_TOP_AFI_FM5_RESET_DEFVAL +#undef CRF_APB_RST_FPD_TOP_AFI_FM5_RESET_SHIFT +#undef CRF_APB_RST_FPD_TOP_AFI_FM5_RESET_MASK +#define CRF_APB_RST_FPD_TOP_AFI_FM5_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_AFI_FM5_RESET_SHIFT 12 +#define CRF_APB_RST_FPD_TOP_AFI_FM5_RESET_MASK 0x00001000U + +/* +* AFI FM 6 +*/ +#undef CRL_APB_RST_LPD_TOP_AFI_FM6_RESET_DEFVAL +#undef CRL_APB_RST_LPD_TOP_AFI_FM6_RESET_SHIFT +#undef CRL_APB_RST_LPD_TOP_AFI_FM6_RESET_MASK +#define CRL_APB_RST_LPD_TOP_AFI_FM6_RESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_AFI_FM6_RESET_SHIFT 19 +#define CRL_APB_RST_LPD_TOP_AFI_FM6_RESET_MASK 0x00080000U + +/* +* Select the 32/64/128-bit data width selection for the Slave 0 00: 32-bit + * AXI data width (default) 01: 64-bit AXI data width 10: 128-bit AXI data + * width 11: reserved +*/ +#undef FPD_SLCR_AFI_FS_DW_SS0_SEL_DEFVAL +#undef FPD_SLCR_AFI_FS_DW_SS0_SEL_SHIFT +#undef FPD_SLCR_AFI_FS_DW_SS0_SEL_MASK +#define FPD_SLCR_AFI_FS_DW_SS0_SEL_DEFVAL 0x00000A00 +#define FPD_SLCR_AFI_FS_DW_SS0_SEL_SHIFT 8 +#define FPD_SLCR_AFI_FS_DW_SS0_SEL_MASK 0x00000300U + +/* +* Select the 32/64/128-bit data width selection for the Slave 1 00: 32-bit + * AXI data width (default) 01: 64-bit AXI data width 10: 128-bit AXI data + * width 11: reserved +*/ +#undef FPD_SLCR_AFI_FS_DW_SS1_SEL_DEFVAL +#undef FPD_SLCR_AFI_FS_DW_SS1_SEL_SHIFT +#undef FPD_SLCR_AFI_FS_DW_SS1_SEL_MASK +#define FPD_SLCR_AFI_FS_DW_SS1_SEL_DEFVAL 0x00000A00 +#define FPD_SLCR_AFI_FS_DW_SS1_SEL_SHIFT 10 +#define FPD_SLCR_AFI_FS_DW_SS1_SEL_MASK 0x00000C00U #undef GPIO_MASK_DATA_5_MSW_OFFSET #define GPIO_MASK_DATA_5_MSW_OFFSET 0XFF0A002C #undef GPIO_DIRM_5_OFFSET @@ -27801,53 +36394,65 @@ #undef GPIO_DATA_5_OFFSET #define GPIO_DATA_5_OFFSET 0XFF0A0054 -/*Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW]*/ +/* +* Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW] +*/ #undef GPIO_MASK_DATA_5_MSW_MASK_5_MSW_DEFVAL #undef GPIO_MASK_DATA_5_MSW_MASK_5_MSW_SHIFT #undef GPIO_MASK_DATA_5_MSW_MASK_5_MSW_MASK -#define GPIO_MASK_DATA_5_MSW_MASK_5_MSW_DEFVAL 0x00000000 -#define GPIO_MASK_DATA_5_MSW_MASK_5_MSW_SHIFT 16 -#define GPIO_MASK_DATA_5_MSW_MASK_5_MSW_MASK 0xFFFF0000U +#define GPIO_MASK_DATA_5_MSW_MASK_5_MSW_DEFVAL 0x00000000 +#define GPIO_MASK_DATA_5_MSW_MASK_5_MSW_SHIFT 16 +#define GPIO_MASK_DATA_5_MSW_MASK_5_MSW_MASK 0xFFFF0000U -/*Operation is the same as DIRM_0[DIRECTION_0]*/ +/* +* Operation is the same as DIRM_0[DIRECTION_0] +*/ #undef GPIO_DIRM_5_DIRECTION_5_DEFVAL #undef GPIO_DIRM_5_DIRECTION_5_SHIFT #undef GPIO_DIRM_5_DIRECTION_5_MASK -#define GPIO_DIRM_5_DIRECTION_5_DEFVAL -#define GPIO_DIRM_5_DIRECTION_5_SHIFT 0 -#define GPIO_DIRM_5_DIRECTION_5_MASK 0xFFFFFFFFU +#define GPIO_DIRM_5_DIRECTION_5_DEFVAL +#define GPIO_DIRM_5_DIRECTION_5_SHIFT 0 +#define GPIO_DIRM_5_DIRECTION_5_MASK 0xFFFFFFFFU -/*Operation is the same as OEN_0[OP_ENABLE_0]*/ +/* +* Operation is the same as OEN_0[OP_ENABLE_0] +*/ #undef GPIO_OEN_5_OP_ENABLE_5_DEFVAL #undef GPIO_OEN_5_OP_ENABLE_5_SHIFT #undef GPIO_OEN_5_OP_ENABLE_5_MASK -#define GPIO_OEN_5_OP_ENABLE_5_DEFVAL -#define GPIO_OEN_5_OP_ENABLE_5_SHIFT 0 -#define GPIO_OEN_5_OP_ENABLE_5_MASK 0xFFFFFFFFU +#define GPIO_OEN_5_OP_ENABLE_5_DEFVAL +#define GPIO_OEN_5_OP_ENABLE_5_SHIFT 0 +#define GPIO_OEN_5_OP_ENABLE_5_MASK 0xFFFFFFFFU -/*Output Data*/ +/* +* Output Data +*/ #undef GPIO_DATA_5_DATA_5_DEFVAL #undef GPIO_DATA_5_DATA_5_SHIFT #undef GPIO_DATA_5_DATA_5_MASK -#define GPIO_DATA_5_DATA_5_DEFVAL -#define GPIO_DATA_5_DATA_5_SHIFT 0 -#define GPIO_DATA_5_DATA_5_MASK 0xFFFFFFFFU +#define GPIO_DATA_5_DATA_5_DEFVAL +#define GPIO_DATA_5_DATA_5_SHIFT 0 +#define GPIO_DATA_5_DATA_5_MASK 0xFFFFFFFFU -/*Output Data*/ +/* +* Output Data +*/ #undef GPIO_DATA_5_DATA_5_DEFVAL #undef GPIO_DATA_5_DATA_5_SHIFT #undef GPIO_DATA_5_DATA_5_MASK -#define GPIO_DATA_5_DATA_5_DEFVAL -#define GPIO_DATA_5_DATA_5_SHIFT 0 -#define GPIO_DATA_5_DATA_5_MASK 0xFFFFFFFFU +#define GPIO_DATA_5_DATA_5_DEFVAL +#define GPIO_DATA_5_DATA_5_SHIFT 0 +#define GPIO_DATA_5_DATA_5_MASK 0xFFFFFFFFU -/*Output Data*/ +/* +* Output Data +*/ #undef GPIO_DATA_5_DATA_5_DEFVAL #undef GPIO_DATA_5_DATA_5_SHIFT #undef GPIO_DATA_5_DATA_5_MASK -#define GPIO_DATA_5_DATA_5_DEFVAL -#define GPIO_DATA_5_DATA_5_SHIFT 0 -#define GPIO_DATA_5_DATA_5_MASK 0xFFFFFFFFU +#define GPIO_DATA_5_DATA_5_DEFVAL +#define GPIO_DATA_5_DATA_5_SHIFT 0 +#define GPIO_DATA_5_DATA_5_MASK 0xFFFFFFFFU #ifdef __cplusplus extern "C" { #endif @@ -27860,6 +36465,7 @@ extern "C" { int psu_ddr_protection(); int psu_lpd_protection(); int psu_protection_lock(); + unsigned long psu_ddr_qos_init_data(void); unsigned long psu_apply_master_tz(); #ifdef __cplusplus } diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init.tcl b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init.tcl index b6d9c0418..bcdd9de80 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init.tcl +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init.tcl @@ -11,7 +11,7 @@ set psu_pll_init_data { # Register : RPLL_CFG @ 0XFF5E0034

# PLL loop filter resistor control - # PSU_CRL_APB_RPLL_CFG_RES 0x2 + # PSU_CRL_APB_RPLL_CFG_RES 0xc # PLL charge pump control # PSU_CRL_APB_RPLL_CFG_CP 0x3 @@ -20,35 +20,39 @@ set psu_pll_init_data { # PSU_CRL_APB_RPLL_CFG_LFHF 0x3 # Lock circuit counter setting - # PSU_CRL_APB_RPLL_CFG_LOCK_CNT 0x258 + # PSU_CRL_APB_RPLL_CFG_LOCK_CNT 0x339 # Lock circuit configuration settings for lock windowsize # PSU_CRL_APB_RPLL_CFG_LOCK_DLY 0x3f # Helper data. Values are to be looked up in a table from Data Sheet - #(OFFSET, MASK, VALUE) (0XFF5E0034, 0xFE7FEDEFU ,0x7E4B0C62U) */ - mask_write 0XFF5E0034 0xFE7FEDEF 0x7E4B0C62 + #(OFFSET, MASK, VALUE) (0XFF5E0034, 0xFE7FEDEFU ,0x7E672C6CU) */ + mask_write 0XFF5E0034 0xFE7FEDEF 0x7E672C6C # : UPDATE FB_DIV # Register : RPLL_CTRL @ 0XFF5E0030

- # Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_ - # ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source + # Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i + # s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour + # ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source # PSU_CRL_APB_RPLL_CTRL_PRE_SRC 0x0 # The integer portion of the feedback divider to the PLL - # PSU_CRL_APB_RPLL_CTRL_FBDIV 0x48 + # PSU_CRL_APB_RPLL_CTRL_FBDIV 0x2d - # This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency + # This turns on the divide by 2 that is inside of the PLL. This does not c + # hange the VCO frequency, just the output frequency # PSU_CRL_APB_RPLL_CTRL_DIV2 0x1 # PLL Basic Control - #(OFFSET, MASK, VALUE) (0XFF5E0030, 0x00717F00U ,0x00014800U) */ - mask_write 0XFF5E0030 0x00717F00 0x00014800 + #(OFFSET, MASK, VALUE) (0XFF5E0030, 0x00717F00U ,0x00012D00U) */ + mask_write 0XFF5E0030 0x00717F00 0x00012D00 # : BY PASS PLL # Register : RPLL_CTRL @ 0XFF5E0030

- # Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - # cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.) + # Bypasses the PLL clock. The usable clock will be determined from the POS + # T_SRC field. (This signal may only be toggled after 4 cycles of the old + # clock and 4 cycles of the new clock. This is not usually an issue, but d + # esigners must be aware.) # PSU_CRL_APB_RPLL_CTRL_BYPASS 1 # PLL Basic Control @@ -57,7 +61,8 @@ set psu_pll_init_data { # : ASSERT RESET # Register : RPLL_CTRL @ 0XFF5E0030

- # Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS. + # Asserts Reset to the PLL. When asserting reset, the PLL must already be + # in BYPASS. # PSU_CRL_APB_RPLL_CTRL_RESET 1 # PLL Basic Control @@ -66,7 +71,8 @@ set psu_pll_init_data { # : DEASSERT RESET # Register : RPLL_CTRL @ 0XFF5E0030

- # Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS. + # Asserts Reset to the PLL. When asserting reset, the PLL must already be + # in BYPASS. # PSU_CRL_APB_RPLL_CTRL_RESET 0 # PLL Basic Control @@ -81,8 +87,10 @@ set psu_pll_init_data { # : REMOVE PLL BY PASS # Register : RPLL_CTRL @ 0XFF5E0030

- # Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - # cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.) + # Bypasses the PLL clock. The usable clock will be determined from the POS + # T_SRC field. (This signal may only be toggled after 4 cycles of the old + # clock and 4 cycles of the new clock. This is not usually an issue, but d + # esigners must be aware.) # PSU_CRL_APB_RPLL_CTRL_BYPASS 0 # PLL Basic Control @@ -91,66 +99,59 @@ set psu_pll_init_data { # Register : RPLL_TO_FPD_CTRL @ 0XFF5E0048

# Divisor value for this clock. - # PSU_CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0 0x3 + # PSU_CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0 0x2 - # Control for a clock that will be generated in the LPD, but used in the FPD as a clock source for the peripheral clock muxes. - #(OFFSET, MASK, VALUE) (0XFF5E0048, 0x00003F00U ,0x00000300U) */ - mask_write 0XFF5E0048 0x00003F00 0x00000300 + # Control for a clock that will be generated in the LPD, but used in the F + # PD as a clock source for the peripheral clock muxes. + #(OFFSET, MASK, VALUE) (0XFF5E0048, 0x00003F00U ,0x00000200U) */ + mask_write 0XFF5E0048 0x00003F00 0x00000200 # : RPLL FRAC CFG - # Register : RPLL_FRAC_CFG @ 0XFF5E0038

- - # Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona - # mode and uses DATA of this register for the fractional portion of the feedback divider. - # PSU_CRL_APB_RPLL_FRAC_CFG_ENABLED 0x0 - - # Fractional value for the Feedback value. - # PSU_CRL_APB_RPLL_FRAC_CFG_DATA 0x0 - - # Fractional control for the PLL - #(OFFSET, MASK, VALUE) (0XFF5E0038, 0x8000FFFFU ,0x00000000U) */ - mask_write 0XFF5E0038 0x8000FFFF 0x00000000 # : IOPLL INIT # Register : IOPLL_CFG @ 0XFF5E0024

# PLL loop filter resistor control - # PSU_CRL_APB_IOPLL_CFG_RES 0xc + # PSU_CRL_APB_IOPLL_CFG_RES 0x2 # PLL charge pump control - # PSU_CRL_APB_IOPLL_CFG_CP 0x3 + # PSU_CRL_APB_IOPLL_CFG_CP 0x4 # PLL loop filter high frequency capacitor control # PSU_CRL_APB_IOPLL_CFG_LFHF 0x3 # Lock circuit counter setting - # PSU_CRL_APB_IOPLL_CFG_LOCK_CNT 0x339 + # PSU_CRL_APB_IOPLL_CFG_LOCK_CNT 0x258 # Lock circuit configuration settings for lock windowsize # PSU_CRL_APB_IOPLL_CFG_LOCK_DLY 0x3f # Helper data. Values are to be looked up in a table from Data Sheet - #(OFFSET, MASK, VALUE) (0XFF5E0024, 0xFE7FEDEFU ,0x7E672C6CU) */ - mask_write 0XFF5E0024 0xFE7FEDEF 0x7E672C6C + #(OFFSET, MASK, VALUE) (0XFF5E0024, 0xFE7FEDEFU ,0x7E4B0C82U) */ + mask_write 0XFF5E0024 0xFE7FEDEF 0x7E4B0C82 # : UPDATE FB_DIV # Register : IOPLL_CTRL @ 0XFF5E0020

- # Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_ - # ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source + # Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i + # s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour + # ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source # PSU_CRL_APB_IOPLL_CTRL_PRE_SRC 0x0 # The integer portion of the feedback divider to the PLL - # PSU_CRL_APB_IOPLL_CTRL_FBDIV 0x2d + # PSU_CRL_APB_IOPLL_CTRL_FBDIV 0x5a - # This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency - # PSU_CRL_APB_IOPLL_CTRL_DIV2 0x0 + # This turns on the divide by 2 that is inside of the PLL. This does not c + # hange the VCO frequency, just the output frequency + # PSU_CRL_APB_IOPLL_CTRL_DIV2 0x1 # PLL Basic Control - #(OFFSET, MASK, VALUE) (0XFF5E0020, 0x00717F00U ,0x00002D00U) */ - mask_write 0XFF5E0020 0x00717F00 0x00002D00 + #(OFFSET, MASK, VALUE) (0XFF5E0020, 0x00717F00U ,0x00015A00U) */ + mask_write 0XFF5E0020 0x00717F00 0x00015A00 # : BY PASS PLL # Register : IOPLL_CTRL @ 0XFF5E0020

- # Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - # cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.) + # Bypasses the PLL clock. The usable clock will be determined from the POS + # T_SRC field. (This signal may only be toggled after 4 cycles of the old + # clock and 4 cycles of the new clock. This is not usually an issue, but d + # esigners must be aware.) # PSU_CRL_APB_IOPLL_CTRL_BYPASS 1 # PLL Basic Control @@ -159,7 +160,8 @@ set psu_pll_init_data { # : ASSERT RESET # Register : IOPLL_CTRL @ 0XFF5E0020

- # Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS. + # Asserts Reset to the PLL. When asserting reset, the PLL must already be + # in BYPASS. # PSU_CRL_APB_IOPLL_CTRL_RESET 1 # PLL Basic Control @@ -168,7 +170,8 @@ set psu_pll_init_data { # : DEASSERT RESET # Register : IOPLL_CTRL @ 0XFF5E0020

- # Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS. + # Asserts Reset to the PLL. When asserting reset, the PLL must already be + # in BYPASS. # PSU_CRL_APB_IOPLL_CTRL_RESET 0 # PLL Basic Control @@ -183,8 +186,10 @@ set psu_pll_init_data { # : REMOVE PLL BY PASS # Register : IOPLL_CTRL @ 0XFF5E0020

- # Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - # cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.) + # Bypasses the PLL clock. The usable clock will be determined from the POS + # T_SRC field. (This signal may only be toggled after 4 cycles of the old + # clock and 4 cycles of the new clock. This is not usually an issue, but d + # esigners must be aware.) # PSU_CRL_APB_IOPLL_CTRL_BYPASS 0 # PLL Basic Control @@ -195,22 +200,11 @@ set psu_pll_init_data { # Divisor value for this clock. # PSU_CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0 0x3 - # Control for a clock that will be generated in the LPD, but used in the FPD as a clock source for the peripheral clock muxes. + # Control for a clock that will be generated in the LPD, but used in the F + # PD as a clock source for the peripheral clock muxes. #(OFFSET, MASK, VALUE) (0XFF5E0044, 0x00003F00U ,0x00000300U) */ mask_write 0XFF5E0044 0x00003F00 0x00000300 # : IOPLL FRAC CFG - # Register : IOPLL_FRAC_CFG @ 0XFF5E0028

- - # Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona - # mode and uses DATA of this register for the fractional portion of the feedback divider. - # PSU_CRL_APB_IOPLL_FRAC_CFG_ENABLED 0x0 - - # Fractional value for the Feedback value. - # PSU_CRL_APB_IOPLL_FRAC_CFG_DATA 0x0 - - # Fractional control for the PLL - #(OFFSET, MASK, VALUE) (0XFF5E0028, 0x8000FFFFU ,0x00000000U) */ - mask_write 0XFF5E0028 0x8000FFFF 0x00000000 # : APU_PLL INIT # Register : APLL_CFG @ 0XFD1A0024

@@ -235,24 +229,28 @@ set psu_pll_init_data { # : UPDATE FB_DIV # Register : APLL_CTRL @ 0XFD1A0020

- # Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_ - # ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source + # Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i + # s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour + # ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source # PSU_CRF_APB_APLL_CTRL_PRE_SRC 0x0 # The integer portion of the feedback divider to the PLL - # PSU_CRF_APB_APLL_CTRL_FBDIV 0x42 + # PSU_CRF_APB_APLL_CTRL_FBDIV 0x48 - # This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency + # This turns on the divide by 2 that is inside of the PLL. This does not c + # hange the VCO frequency, just the output frequency # PSU_CRF_APB_APLL_CTRL_DIV2 0x1 # PLL Basic Control - #(OFFSET, MASK, VALUE) (0XFD1A0020, 0x00717F00U ,0x00014200U) */ - mask_write 0XFD1A0020 0x00717F00 0x00014200 + #(OFFSET, MASK, VALUE) (0XFD1A0020, 0x00717F00U ,0x00014800U) */ + mask_write 0XFD1A0020 0x00717F00 0x00014800 # : BY PASS PLL # Register : APLL_CTRL @ 0XFD1A0020

- # Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - # cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.) + # Bypasses the PLL clock. The usable clock will be determined from the POS + # T_SRC field. (This signal may only be toggled after 4 cycles of the old + # clock and 4 cycles of the new clock. This is not usually an issue, but d + # esigners must be aware.) # PSU_CRF_APB_APLL_CTRL_BYPASS 1 # PLL Basic Control @@ -261,7 +259,8 @@ set psu_pll_init_data { # : ASSERT RESET # Register : APLL_CTRL @ 0XFD1A0020

- # Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS. + # Asserts Reset to the PLL. When asserting reset, the PLL must already be + # in BYPASS. # PSU_CRF_APB_APLL_CTRL_RESET 1 # PLL Basic Control @@ -270,7 +269,8 @@ set psu_pll_init_data { # : DEASSERT RESET # Register : APLL_CTRL @ 0XFD1A0020

- # Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS. + # Asserts Reset to the PLL. When asserting reset, the PLL must already be + # in BYPASS. # PSU_CRF_APB_APLL_CTRL_RESET 0 # PLL Basic Control @@ -285,8 +285,10 @@ set psu_pll_init_data { # : REMOVE PLL BY PASS # Register : APLL_CTRL @ 0XFD1A0020

- # Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - # cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.) + # Bypasses the PLL clock. The usable clock will be determined from the POS + # T_SRC field. (This signal may only be toggled after 4 cycles of the old + # clock and 4 cycles of the new clock. This is not usually an issue, but d + # esigners must be aware.) # PSU_CRF_APB_APLL_CTRL_BYPASS 0 # PLL Basic Control @@ -297,22 +299,11 @@ set psu_pll_init_data { # Divisor value for this clock. # PSU_CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0 0x3 - # Control for a clock that will be generated in the FPD, but used in the LPD as a clock source for the peripheral clock muxes. + # Control for a clock that will be generated in the FPD, but used in the L + # PD as a clock source for the peripheral clock muxes. #(OFFSET, MASK, VALUE) (0XFD1A0048, 0x00003F00U ,0x00000300U) */ mask_write 0XFD1A0048 0x00003F00 0x00000300 # : APLL FRAC CFG - # Register : APLL_FRAC_CFG @ 0XFD1A0028

- - # Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona - # mode and uses DATA of this register for the fractional portion of the feedback divider. - # PSU_CRF_APB_APLL_FRAC_CFG_ENABLED 0x0 - - # Fractional value for the Feedback value. - # PSU_CRF_APB_APLL_FRAC_CFG_DATA 0x0 - - # Fractional control for the PLL - #(OFFSET, MASK, VALUE) (0XFD1A0028, 0x8000FFFFU ,0x00000000U) */ - mask_write 0XFD1A0028 0x8000FFFF 0x00000000 # : DDR_PLL INIT # Register : DPLL_CFG @ 0XFD1A0030

@@ -337,14 +328,16 @@ set psu_pll_init_data { # : UPDATE FB_DIV # Register : DPLL_CTRL @ 0XFD1A002C

- # Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_ - # ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source + # Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i + # s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour + # ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source # PSU_CRF_APB_DPLL_CTRL_PRE_SRC 0x0 # The integer portion of the feedback divider to the PLL # PSU_CRF_APB_DPLL_CTRL_FBDIV 0x40 - # This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency + # This turns on the divide by 2 that is inside of the PLL. This does not c + # hange the VCO frequency, just the output frequency # PSU_CRF_APB_DPLL_CTRL_DIV2 0x1 # PLL Basic Control @@ -353,8 +346,10 @@ set psu_pll_init_data { # : BY PASS PLL # Register : DPLL_CTRL @ 0XFD1A002C

- # Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - # cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.) + # Bypasses the PLL clock. The usable clock will be determined from the POS + # T_SRC field. (This signal may only be toggled after 4 cycles of the old + # clock and 4 cycles of the new clock. This is not usually an issue, but d + # esigners must be aware.) # PSU_CRF_APB_DPLL_CTRL_BYPASS 1 # PLL Basic Control @@ -363,7 +358,8 @@ set psu_pll_init_data { # : ASSERT RESET # Register : DPLL_CTRL @ 0XFD1A002C

- # Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS. + # Asserts Reset to the PLL. When asserting reset, the PLL must already be + # in BYPASS. # PSU_CRF_APB_DPLL_CTRL_RESET 1 # PLL Basic Control @@ -372,7 +368,8 @@ set psu_pll_init_data { # : DEASSERT RESET # Register : DPLL_CTRL @ 0XFD1A002C

- # Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS. + # Asserts Reset to the PLL. When asserting reset, the PLL must already be + # in BYPASS. # PSU_CRF_APB_DPLL_CTRL_RESET 0 # PLL Basic Control @@ -387,8 +384,10 @@ set psu_pll_init_data { # : REMOVE PLL BY PASS # Register : DPLL_CTRL @ 0XFD1A002C

- # Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - # cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.) + # Bypasses the PLL clock. The usable clock will be determined from the POS + # T_SRC field. (This signal may only be toggled after 4 cycles of the old + # clock and 4 cycles of the new clock. This is not usually an issue, but d + # esigners must be aware.) # PSU_CRF_APB_DPLL_CTRL_BYPASS 0 # PLL Basic Control @@ -397,24 +396,13 @@ set psu_pll_init_data { # Register : DPLL_TO_LPD_CTRL @ 0XFD1A004C

# Divisor value for this clock. - # PSU_CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0 0x3 + # PSU_CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0 0x2 - # Control for a clock that will be generated in the FPD, but used in the LPD as a clock source for the peripheral clock muxes. - #(OFFSET, MASK, VALUE) (0XFD1A004C, 0x00003F00U ,0x00000300U) */ - mask_write 0XFD1A004C 0x00003F00 0x00000300 + # Control for a clock that will be generated in the FPD, but used in the L + # PD as a clock source for the peripheral clock muxes. + #(OFFSET, MASK, VALUE) (0XFD1A004C, 0x00003F00U ,0x00000200U) */ + mask_write 0XFD1A004C 0x00003F00 0x00000200 # : DPLL FRAC CFG - # Register : DPLL_FRAC_CFG @ 0XFD1A0034

- - # Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona - # mode and uses DATA of this register for the fractional portion of the feedback divider. - # PSU_CRF_APB_DPLL_FRAC_CFG_ENABLED 0x0 - - # Fractional value for the Feedback value. - # PSU_CRF_APB_DPLL_FRAC_CFG_DATA 0x0 - - # Fractional control for the PLL - #(OFFSET, MASK, VALUE) (0XFD1A0034, 0x8000FFFFU ,0x00000000U) */ - mask_write 0XFD1A0034 0x8000FFFF 0x00000000 # : VIDEO_PLL INIT # Register : VPLL_CFG @ 0XFD1A003C

@@ -422,41 +410,45 @@ set psu_pll_init_data { # PSU_CRF_APB_VPLL_CFG_RES 0x2 # PLL charge pump control - # PSU_CRF_APB_VPLL_CFG_CP 0x3 + # PSU_CRF_APB_VPLL_CFG_CP 0x4 # PLL loop filter high frequency capacitor control # PSU_CRF_APB_VPLL_CFG_LFHF 0x3 # Lock circuit counter setting - # PSU_CRF_APB_VPLL_CFG_LOCK_CNT 0x28a + # PSU_CRF_APB_VPLL_CFG_LOCK_CNT 0x258 # Lock circuit configuration settings for lock windowsize # PSU_CRF_APB_VPLL_CFG_LOCK_DLY 0x3f # Helper data. Values are to be looked up in a table from Data Sheet - #(OFFSET, MASK, VALUE) (0XFD1A003C, 0xFE7FEDEFU ,0x7E514C62U) */ - mask_write 0XFD1A003C 0xFE7FEDEF 0x7E514C62 + #(OFFSET, MASK, VALUE) (0XFD1A003C, 0xFE7FEDEFU ,0x7E4B0C82U) */ + mask_write 0XFD1A003C 0xFE7FEDEF 0x7E4B0C82 # : UPDATE FB_DIV # Register : VPLL_CTRL @ 0XFD1A0038

- # Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_ - # ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source + # Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i + # s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour + # ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source # PSU_CRF_APB_VPLL_CTRL_PRE_SRC 0x0 # The integer portion of the feedback divider to the PLL - # PSU_CRF_APB_VPLL_CTRL_FBDIV 0x39 + # PSU_CRF_APB_VPLL_CTRL_FBDIV 0x5a - # This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency + # This turns on the divide by 2 that is inside of the PLL. This does not c + # hange the VCO frequency, just the output frequency # PSU_CRF_APB_VPLL_CTRL_DIV2 0x1 # PLL Basic Control - #(OFFSET, MASK, VALUE) (0XFD1A0038, 0x00717F00U ,0x00013900U) */ - mask_write 0XFD1A0038 0x00717F00 0x00013900 + #(OFFSET, MASK, VALUE) (0XFD1A0038, 0x00717F00U ,0x00015A00U) */ + mask_write 0XFD1A0038 0x00717F00 0x00015A00 # : BY PASS PLL # Register : VPLL_CTRL @ 0XFD1A0038

- # Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - # cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.) + # Bypasses the PLL clock. The usable clock will be determined from the POS + # T_SRC field. (This signal may only be toggled after 4 cycles of the old + # clock and 4 cycles of the new clock. This is not usually an issue, but d + # esigners must be aware.) # PSU_CRF_APB_VPLL_CTRL_BYPASS 1 # PLL Basic Control @@ -465,7 +457,8 @@ set psu_pll_init_data { # : ASSERT RESET # Register : VPLL_CTRL @ 0XFD1A0038

- # Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS. + # Asserts Reset to the PLL. When asserting reset, the PLL must already be + # in BYPASS. # PSU_CRF_APB_VPLL_CTRL_RESET 1 # PLL Basic Control @@ -474,7 +467,8 @@ set psu_pll_init_data { # : DEASSERT RESET # Register : VPLL_CTRL @ 0XFD1A0038

- # Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS. + # Asserts Reset to the PLL. When asserting reset, the PLL must already be + # in BYPASS. # PSU_CRF_APB_VPLL_CTRL_RESET 0 # PLL Basic Control @@ -489,8 +483,10 @@ set psu_pll_init_data { # : REMOVE PLL BY PASS # Register : VPLL_CTRL @ 0XFD1A0038

- # Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - # cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.) + # Bypasses the PLL clock. The usable clock will be determined from the POS + # T_SRC field. (This signal may only be toggled after 4 cycles of the old + # clock and 4 cycles of the new clock. This is not usually an issue, but d + # esigners must be aware.) # PSU_CRF_APB_VPLL_CTRL_BYPASS 0 # PLL Basic Control @@ -501,22 +497,11 @@ set psu_pll_init_data { # Divisor value for this clock. # PSU_CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0 0x3 - # Control for a clock that will be generated in the FPD, but used in the LPD as a clock source for the peripheral clock muxes. + # Control for a clock that will be generated in the FPD, but used in the L + # PD as a clock source for the peripheral clock muxes. #(OFFSET, MASK, VALUE) (0XFD1A0050, 0x00003F00U ,0x00000300U) */ mask_write 0XFD1A0050 0x00003F00 0x00000300 # : VIDEO FRAC CFG - # Register : VPLL_FRAC_CFG @ 0XFD1A0040

- - # Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona - # mode and uses DATA of this register for the fractional portion of the feedback divider. - # PSU_CRF_APB_VPLL_FRAC_CFG_ENABLED 0x1 - - # Fractional value for the Feedback value. - # PSU_CRF_APB_VPLL_FRAC_CFG_DATA 0x820c - - # Fractional control for the PLL - #(OFFSET, MASK, VALUE) (0XFD1A0040, 0x8000FFFFU ,0x8000820CU) */ - mask_write 0XFD1A0040 0x8000FFFF 0x8000820C } set psu_clock_init_data { @@ -535,13 +520,33 @@ set psu_clock_init_data { # 6 bit divider # PSU_CRL_APB_GEM3_REF_CTRL_DIVISOR0 0xc - # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - # clock. This is not usually an issue, but designers must be aware.) + # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + # ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + # usually an issue, but designers must be aware.) # PSU_CRL_APB_GEM3_REF_CTRL_SRCSEL 0x0 # This register controls this reference clock #(OFFSET, MASK, VALUE) (0XFF5E005C, 0x063F3F07U ,0x06010C00U) */ mask_write 0XFF5E005C 0x063F3F07 0x06010C00 + # Register : GEM_TSU_REF_CTRL @ 0XFF5E0100

+ + # 6 bit divider + # PSU_CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0 0x6 + + # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + # ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + # usually an issue, but designers must be aware.) + # PSU_CRL_APB_GEM_TSU_REF_CTRL_SRCSEL 0x0 + + # 6 bit divider + # PSU_CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1 0x1 + + # Clock active signal. Switch to 0 to disable the clock + # PSU_CRL_APB_GEM_TSU_REF_CTRL_CLKACT 0x1 + + # This register controls this reference clock + #(OFFSET, MASK, VALUE) (0XFF5E0100, 0x013F3F07U ,0x01010600U) */ + mask_write 0XFF5E0100 0x013F3F07 0x01010600 # Register : USB0_BUS_REF_CTRL @ 0XFF5E0060

# Clock active signal. Switch to 0 to disable the clock @@ -553,8 +558,9 @@ set psu_clock_init_data { # 6 bit divider # PSU_CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0 0x6 - # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - # clock. This is not usually an issue, but designers must be aware.) + # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + # ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + # usually an issue, but designers must be aware.) # PSU_CRL_APB_USB0_BUS_REF_CTRL_SRCSEL 0x0 # This register controls this reference clock @@ -566,18 +572,19 @@ set psu_clock_init_data { # PSU_CRL_APB_USB3_DUAL_REF_CTRL_CLKACT 0x1 # 6 bit divider - # PSU_CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1 0xf + # PSU_CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1 0x3 # 6 bit divider - # PSU_CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0 0x5 + # PSU_CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0 0x19 - # 000 = IOPLL; 010 = RPLL; 011 = DPLL. (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - # clock. This is not usually an issue, but designers must be aware.) + # 000 = IOPLL; 010 = RPLL; 011 = DPLL. (This signal may only be toggled af + # ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + # usually an issue, but designers must be aware.) # PSU_CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL 0x0 # This register controls this reference clock - #(OFFSET, MASK, VALUE) (0XFF5E004C, 0x023F3F07U ,0x020F0500U) */ - mask_write 0XFF5E004C 0x023F3F07 0x020F0500 + #(OFFSET, MASK, VALUE) (0XFF5E004C, 0x023F3F07U ,0x02031900U) */ + mask_write 0XFF5E004C 0x023F3F07 0x02031900 # Register : QSPI_REF_CTRL @ 0XFF5E0068

# Clock active signal. Switch to 0 to disable the clock @@ -589,8 +596,9 @@ set psu_clock_init_data { # 6 bit divider # PSU_CRL_APB_QSPI_REF_CTRL_DIVISOR0 0xc - # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - # clock. This is not usually an issue, but designers must be aware.) + # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + # ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + # usually an issue, but designers must be aware.) # PSU_CRL_APB_QSPI_REF_CTRL_SRCSEL 0x0 # This register controls this reference clock @@ -605,18 +613,20 @@ set psu_clock_init_data { # PSU_CRL_APB_SDIO1_REF_CTRL_DIVISOR1 0x1 # 6 bit divider - # PSU_CRL_APB_SDIO1_REF_CTRL_DIVISOR0 0x6 + # PSU_CRL_APB_SDIO1_REF_CTRL_DIVISOR0 0x8 - # 000 = IOPLL; 010 = RPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - # clock. This is not usually an issue, but designers must be aware.) - # PSU_CRL_APB_SDIO1_REF_CTRL_SRCSEL 0x2 + # 000 = IOPLL; 010 = RPLL; 011 = VPLL; (This signal may only be toggled af + # ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + # usually an issue, but designers must be aware.) + # PSU_CRL_APB_SDIO1_REF_CTRL_SRCSEL 0x0 # This register controls this reference clock - #(OFFSET, MASK, VALUE) (0XFF5E0070, 0x013F3F07U ,0x01010602U) */ - mask_write 0XFF5E0070 0x013F3F07 0x01010602 + #(OFFSET, MASK, VALUE) (0XFF5E0070, 0x013F3F07U ,0x01010800U) */ + mask_write 0XFF5E0070 0x013F3F07 0x01010800 # Register : SDIO_CLK_CTRL @ 0XFF18030C

- # MIO pad selection for sdio1_rx_clk (feedback clock from the PAD) 0: MIO [51] 1: MIO [76] + # MIO pad selection for sdio1_rx_clk (feedback clock from the PAD) 0: MIO + # [51] 1: MIO [76] # PSU_IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL 0 # SoC Debug Clock Control @@ -633,8 +643,9 @@ set psu_clock_init_data { # 6 bit divider # PSU_CRL_APB_UART0_REF_CTRL_DIVISOR0 0xf - # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - # clock. This is not usually an issue, but designers must be aware.) + # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + # ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + # usually an issue, but designers must be aware.) # PSU_CRL_APB_UART0_REF_CTRL_SRCSEL 0x0 # This register controls this reference clock @@ -651,8 +662,9 @@ set psu_clock_init_data { # 6 bit divider # PSU_CRL_APB_UART1_REF_CTRL_DIVISOR0 0xf - # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - # clock. This is not usually an issue, but designers must be aware.) + # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + # ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + # usually an issue, but designers must be aware.) # PSU_CRL_APB_UART1_REF_CTRL_SRCSEL 0x0 # This register controls this reference clock @@ -669,8 +681,9 @@ set psu_clock_init_data { # 6 bit divider # PSU_CRL_APB_I2C0_REF_CTRL_DIVISOR0 0xf - # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - # clock. This is not usually an issue, but designers must be aware.) + # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + # ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + # usually an issue, but designers must be aware.) # PSU_CRL_APB_I2C0_REF_CTRL_SRCSEL 0x0 # This register controls this reference clock @@ -687,8 +700,9 @@ set psu_clock_init_data { # 6 bit divider # PSU_CRL_APB_I2C1_REF_CTRL_DIVISOR0 0xf - # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - # clock. This is not usually an issue, but designers must be aware.) + # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + # ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + # usually an issue, but designers must be aware.) # PSU_CRL_APB_I2C1_REF_CTRL_SRCSEL 0x0 # This register controls this reference clock @@ -705,8 +719,9 @@ set psu_clock_init_data { # 6 bit divider # PSU_CRL_APB_CAN1_REF_CTRL_DIVISOR0 0xf - # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - # clock. This is not usually an issue, but designers must be aware.) + # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + # ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + # usually an issue, but designers must be aware.) # PSU_CRL_APB_CAN1_REF_CTRL_SRCSEL 0x0 # This register controls this reference clock @@ -714,15 +729,17 @@ set psu_clock_init_data { mask_write 0XFF5E0088 0x013F3F07 0x01010F00 # Register : CPU_R5_CTRL @ 0XFF5E0090

- # Turing this off will shut down the OCM, some parts of the APM, and prevent transactions going from the FPD to the LPD and cou - # d lead to system hang + # Turing this off will shut down the OCM, some parts of the APM, and preve + # nt transactions going from the FPD to the LPD and could lead to system h + # ang # PSU_CRL_APB_CPU_R5_CTRL_CLKACT 0x1 # 6 bit divider # PSU_CRL_APB_CPU_R5_CTRL_DIVISOR0 0x3 - # 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - # clock. This is not usually an issue, but designers must be aware.) + # 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + # ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + # usually an issue, but designers must be aware.) # PSU_CRL_APB_CPU_R5_CTRL_SRCSEL 0x2 # This register controls this reference clock @@ -736,8 +753,9 @@ set psu_clock_init_data { # 6 bit divider # PSU_CRL_APB_IOU_SWITCH_CTRL_DIVISOR0 0x6 - # 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - # clock. This is not usually an issue, but designers must be aware.) + # 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + # ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + # usually an issue, but designers must be aware.) # PSU_CRL_APB_IOU_SWITCH_CTRL_SRCSEL 0x2 # This register controls this reference clock @@ -749,15 +767,16 @@ set psu_clock_init_data { # PSU_CRL_APB_PCAP_CTRL_CLKACT 0x1 # 6 bit divider - # PSU_CRL_APB_PCAP_CTRL_DIVISOR0 0x6 + # PSU_CRL_APB_PCAP_CTRL_DIVISOR0 0x8 - # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - # clock. This is not usually an issue, but designers must be aware.) - # PSU_CRL_APB_PCAP_CTRL_SRCSEL 0x2 + # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + # ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + # usually an issue, but designers must be aware.) + # PSU_CRL_APB_PCAP_CTRL_SRCSEL 0x0 # This register controls this reference clock - #(OFFSET, MASK, VALUE) (0XFF5E00A4, 0x01003F07U ,0x01000602U) */ - mask_write 0XFF5E00A4 0x01003F07 0x01000602 + #(OFFSET, MASK, VALUE) (0XFF5E00A4, 0x01003F07U ,0x01000800U) */ + mask_write 0XFF5E00A4 0x01003F07 0x01000800 # Register : LPD_SWITCH_CTRL @ 0XFF5E00A8

# Clock active signal. Switch to 0 to disable the clock @@ -766,8 +785,9 @@ set psu_clock_init_data { # 6 bit divider # PSU_CRL_APB_LPD_SWITCH_CTRL_DIVISOR0 0x3 - # 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - # clock. This is not usually an issue, but designers must be aware.) + # 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + # ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + # usually an issue, but designers must be aware.) # PSU_CRL_APB_LPD_SWITCH_CTRL_SRCSEL 0x2 # This register controls this reference clock @@ -781,8 +801,9 @@ set psu_clock_init_data { # 6 bit divider # PSU_CRL_APB_LPD_LSBUS_CTRL_DIVISOR0 0xf - # 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - # clock. This is not usually an issue, but designers must be aware.) + # 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + # ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + # usually an issue, but designers must be aware.) # PSU_CRL_APB_LPD_LSBUS_CTRL_SRCSEL 0x2 # This register controls this reference clock @@ -796,8 +817,9 @@ set psu_clock_init_data { # 6 bit divider # PSU_CRL_APB_DBG_LPD_CTRL_DIVISOR0 0x6 - # 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - # clock. This is not usually an issue, but designers must be aware.) + # 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + # ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + # usually an issue, but designers must be aware.) # PSU_CRL_APB_DBG_LPD_CTRL_SRCSEL 0x2 # This register controls this reference clock @@ -811,8 +833,9 @@ set psu_clock_init_data { # 6 bit divider # PSU_CRL_APB_ADMA_REF_CTRL_DIVISOR0 0x3 - # 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - # clock. This is not usually an issue, but designers must be aware.) + # 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + # ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + # usually an issue, but designers must be aware.) # PSU_CRL_APB_ADMA_REF_CTRL_SRCSEL 0x2 # This register controls this reference clock @@ -829,89 +852,38 @@ set psu_clock_init_data { # 6 bit divider # PSU_CRL_APB_PL0_REF_CTRL_DIVISOR0 0xf - # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - # clock. This is not usually an issue, but designers must be aware.) + # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + # ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + # usually an issue, but designers must be aware.) # PSU_CRL_APB_PL0_REF_CTRL_SRCSEL 0x0 # This register controls this reference clock #(OFFSET, MASK, VALUE) (0XFF5E00C0, 0x013F3F07U ,0x01010F00U) */ mask_write 0XFF5E00C0 0x013F3F07 0x01010F00 - # Register : PL1_REF_CTRL @ 0XFF5E00C4

- - # Clock active signal. Switch to 0 to disable the clock - # PSU_CRL_APB_PL1_REF_CTRL_CLKACT 0x1 - - # 6 bit divider - # PSU_CRL_APB_PL1_REF_CTRL_DIVISOR1 0x4 - - # 6 bit divider - # PSU_CRL_APB_PL1_REF_CTRL_DIVISOR0 0xf - - # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - # clock. This is not usually an issue, but designers must be aware.) - # PSU_CRL_APB_PL1_REF_CTRL_SRCSEL 0x0 - - # This register controls this reference clock - #(OFFSET, MASK, VALUE) (0XFF5E00C4, 0x013F3F07U ,0x01040F00U) */ - mask_write 0XFF5E00C4 0x013F3F07 0x01040F00 - # Register : PL2_REF_CTRL @ 0XFF5E00C8

- - # Clock active signal. Switch to 0 to disable the clock - # PSU_CRL_APB_PL2_REF_CTRL_CLKACT 0x1 - - # 6 bit divider - # PSU_CRL_APB_PL2_REF_CTRL_DIVISOR1 0x1 - - # 6 bit divider - # PSU_CRL_APB_PL2_REF_CTRL_DIVISOR0 0x4 - - # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - # clock. This is not usually an issue, but designers must be aware.) - # PSU_CRL_APB_PL2_REF_CTRL_SRCSEL 0x2 - - # This register controls this reference clock - #(OFFSET, MASK, VALUE) (0XFF5E00C8, 0x013F3F07U ,0x01010402U) */ - mask_write 0XFF5E00C8 0x013F3F07 0x01010402 - # Register : PL3_REF_CTRL @ 0XFF5E00CC

- - # Clock active signal. Switch to 0 to disable the clock - # PSU_CRL_APB_PL3_REF_CTRL_CLKACT 0x1 - - # 6 bit divider - # PSU_CRL_APB_PL3_REF_CTRL_DIVISOR1 0x1 - - # 6 bit divider - # PSU_CRL_APB_PL3_REF_CTRL_DIVISOR0 0x3 - - # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - # clock. This is not usually an issue, but designers must be aware.) - # PSU_CRL_APB_PL3_REF_CTRL_SRCSEL 0x2 - - # This register controls this reference clock - #(OFFSET, MASK, VALUE) (0XFF5E00CC, 0x013F3F07U ,0x01010302U) */ - mask_write 0XFF5E00CC 0x013F3F07 0x01010302 # Register : AMS_REF_CTRL @ 0XFF5E0108

# 6 bit divider # PSU_CRL_APB_AMS_REF_CTRL_DIVISOR1 0x1 # 6 bit divider - # PSU_CRL_APB_AMS_REF_CTRL_DIVISOR0 0x1d + # PSU_CRL_APB_AMS_REF_CTRL_DIVISOR0 0x1e - # 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - # clock. This is not usually an issue, but designers must be aware.) + # 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + # ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + # usually an issue, but designers must be aware.) # PSU_CRL_APB_AMS_REF_CTRL_SRCSEL 0x2 # Clock active signal. Switch to 0 to disable the clock # PSU_CRL_APB_AMS_REF_CTRL_CLKACT 0x1 # This register controls this reference clock - #(OFFSET, MASK, VALUE) (0XFF5E0108, 0x013F3F07U ,0x01011D02U) */ - mask_write 0XFF5E0108 0x013F3F07 0x01011D02 + #(OFFSET, MASK, VALUE) (0XFF5E0108, 0x013F3F07U ,0x01011E02U) */ + mask_write 0XFF5E0108 0x013F3F07 0x01011E02 # Register : DLL_REF_CTRL @ 0XFF5E0104

- # 000 = IOPLL; 001 = RPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This - # is not usually an issue, but designers must be aware.) + # 000 = IOPLL; 001 = RPLL; (This signal may only be toggled after 4 cycles + # of the old clock and 4 cycles of the new clock. This is not usually an + # issue, but designers must be aware.) # PSU_CRL_APB_DLL_REF_CTRL_SRCSEL 0 # This register controls this reference clock @@ -922,8 +894,9 @@ set psu_clock_init_data { # 6 bit divider # PSU_CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0 0xf - # 1XX = pss_ref_clk; 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and - # cycles of the new clock. This is not usually an issue, but designers must be aware.) + # 1XX = pss_ref_clk; 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may + # only be toggled after 4 cycles of the old clock and 4 cycles of the new + # clock. This is not usually an issue, but designers must be aware.) # PSU_CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL 0x0 # Clock active signal. Switch to 0 to disable the clock @@ -934,8 +907,9 @@ set psu_clock_init_data { mask_write 0XFF5E0128 0x01003F07 0x01000F00 # Register : SATA_REF_CTRL @ 0XFD1A00A0

- # 000 = IOPLL_TO_FPD; 010 = APLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of - # he new clock. This is not usually an issue, but designers must be aware.) + # 000 = IOPLL_TO_FPD; 010 = APLL; 011 = DPLL; (This signal may only be tog + # gled after 4 cycles of the old clock and 4 cycles of the new clock. This + # is not usually an issue, but designers must be aware.) # PSU_CRF_APB_SATA_REF_CTRL_SRCSEL 0x0 # Clock active signal. Switch to 0 to disable the clock @@ -949,8 +923,9 @@ set psu_clock_init_data { mask_write 0XFD1A00A0 0x01003F07 0x01000200 # Register : PCIE_REF_CTRL @ 0XFD1A00B4

- # 000 = IOPLL_TO_FPD; 010 = RPLL_TO_FPD; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cyc - # es of the new clock. This is not usually an issue, but designers must be aware.) + # 000 = IOPLL_TO_FPD; 010 = RPLL_TO_FPD; 011 = DPLL; (This signal may only + # be toggled after 4 cycles of the old clock and 4 cycles of the new cloc + # k. This is not usually an issue, but designers must be aware.) # PSU_CRF_APB_PCIE_REF_CTRL_SRCSEL 0x0 # Clock active signal. Switch to 0 to disable the clock @@ -968,95 +943,88 @@ set psu_clock_init_data { # PSU_CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1 0x1 # 6 bit divider - # PSU_CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0 0x3 + # PSU_CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0 0x5 - # 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (This signal may only be toggled after 4 cycles of the - # ld clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.) - # PSU_CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL 0x3 + # 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (T + # his signal may only be toggled after 4 cycles of the old clock and 4 cyc + # les of the new clock. This is not usually an issue, but designers must b + # e aware.) + # PSU_CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL 0x0 # Clock active signal. Switch to 0 to disable the clock # PSU_CRF_APB_DP_VIDEO_REF_CTRL_CLKACT 0x1 # This register controls this reference clock - #(OFFSET, MASK, VALUE) (0XFD1A0070, 0x013F3F07U ,0x01010303U) */ - mask_write 0XFD1A0070 0x013F3F07 0x01010303 + #(OFFSET, MASK, VALUE) (0XFD1A0070, 0x013F3F07U ,0x01010500U) */ + mask_write 0XFD1A0070 0x013F3F07 0x01010500 # Register : DP_AUDIO_REF_CTRL @ 0XFD1A0074

# 6 bit divider # PSU_CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1 0x1 # 6 bit divider - # PSU_CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0 0x27 + # PSU_CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0 0xf - # 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (This signal may only be toggled after 4 cycles of the - # ld clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.) - # PSU_CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL 0x0 + # 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (T + # his signal may only be toggled after 4 cycles of the old clock and 4 cyc + # les of the new clock. This is not usually an issue, but designers must b + # e aware.) + # PSU_CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL 0x3 # Clock active signal. Switch to 0 to disable the clock # PSU_CRF_APB_DP_AUDIO_REF_CTRL_CLKACT 0x1 # This register controls this reference clock - #(OFFSET, MASK, VALUE) (0XFD1A0074, 0x013F3F07U ,0x01012700U) */ - mask_write 0XFD1A0074 0x013F3F07 0x01012700 + #(OFFSET, MASK, VALUE) (0XFD1A0074, 0x013F3F07U ,0x01010F03U) */ + mask_write 0XFD1A0074 0x013F3F07 0x01010F03 # Register : DP_STC_REF_CTRL @ 0XFD1A007C

# 6 bit divider # PSU_CRF_APB_DP_STC_REF_CTRL_DIVISOR1 0x1 # 6 bit divider - # PSU_CRF_APB_DP_STC_REF_CTRL_DIVISOR0 0x11 + # PSU_CRF_APB_DP_STC_REF_CTRL_DIVISOR0 0xe - # 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of t - # e new clock. This is not usually an issue, but designers must be aware.) + # 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD; (This signal may only be togg + # led after 4 cycles of the old clock and 4 cycles of the new clock. This + # is not usually an issue, but designers must be aware.) # PSU_CRF_APB_DP_STC_REF_CTRL_SRCSEL 0x3 # Clock active signal. Switch to 0 to disable the clock # PSU_CRF_APB_DP_STC_REF_CTRL_CLKACT 0x1 # This register controls this reference clock - #(OFFSET, MASK, VALUE) (0XFD1A007C, 0x013F3F07U ,0x01011103U) */ - mask_write 0XFD1A007C 0x013F3F07 0x01011103 + #(OFFSET, MASK, VALUE) (0XFD1A007C, 0x013F3F07U ,0x01010E03U) */ + mask_write 0XFD1A007C 0x013F3F07 0x01010E03 # Register : ACPU_CTRL @ 0XFD1A0060

# 6 bit divider # PSU_CRF_APB_ACPU_CTRL_DIVISOR0 0x1 - # 000 = APLL; 010 = DPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - # lock. This is not usually an issue, but designers must be aware.) + # 000 = APLL; 010 = DPLL; 011 = VPLL; (This signal may only be toggled aft + # er 4 cycles of the old clock and 4 cycles of the new clock. This is not + # usually an issue, but designers must be aware.) # PSU_CRF_APB_ACPU_CTRL_SRCSEL 0x0 - # Clock active signal. Switch to 0 to disable the clock. For the half speed APU Clock + # Clock active signal. Switch to 0 to disable the clock. For the half spee + # d APU Clock # PSU_CRF_APB_ACPU_CTRL_CLKACT_HALF 0x1 - # Clock active signal. Switch to 0 to disable the clock. For the full speed ACPUX Clock. This will shut off the high speed cloc - # to the entire APU + # Clock active signal. Switch to 0 to disable the clock. For the full spee + # d ACPUX Clock. This will shut off the high speed clock to the entire APU # PSU_CRF_APB_ACPU_CTRL_CLKACT_FULL 0x1 # This register controls this reference clock #(OFFSET, MASK, VALUE) (0XFD1A0060, 0x03003F07U ,0x03000100U) */ mask_write 0XFD1A0060 0x03003F07 0x03000100 - # Register : DBG_TRACE_CTRL @ 0XFD1A0064

- - # 6 bit divider - # PSU_CRF_APB_DBG_TRACE_CTRL_DIVISOR0 0x2 - - # 000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of - # he new clock. This is not usually an issue, but designers must be aware.) - # PSU_CRF_APB_DBG_TRACE_CTRL_SRCSEL 0x0 - - # Clock active signal. Switch to 0 to disable the clock - # PSU_CRF_APB_DBG_TRACE_CTRL_CLKACT 0x1 - - # This register controls this reference clock - #(OFFSET, MASK, VALUE) (0XFD1A0064, 0x01003F07U ,0x01000200U) */ - mask_write 0XFD1A0064 0x01003F07 0x01000200 # Register : DBG_FPD_CTRL @ 0XFD1A0068

# 6 bit divider # PSU_CRF_APB_DBG_FPD_CTRL_DIVISOR0 0x2 - # 000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of - # he new clock. This is not usually an issue, but designers must be aware.) + # 000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be tog + # gled after 4 cycles of the old clock and 4 cycles of the new clock. This + # is not usually an issue, but designers must be aware.) # PSU_CRF_APB_DBG_FPD_CTRL_SRCSEL 0x0 # Clock active signal. Switch to 0 to disable the clock @@ -1070,8 +1038,9 @@ set psu_clock_init_data { # 6 bit divider # PSU_CRF_APB_DDR_CTRL_DIVISOR0 0x2 - # 000 = DPLL; 001 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This - # s not usually an issue, but designers must be aware.) + # 000 = DPLL; 001 = VPLL; (This signal may only be toggled after 4 cycles + # of the old clock and 4 cycles of the new clock. This is not usually an i + # ssue, but designers must be aware.) # PSU_CRF_APB_DDR_CTRL_SRCSEL 0x0 # This register controls this reference clock @@ -1082,17 +1051,21 @@ set psu_clock_init_data { # 6 bit divider # PSU_CRF_APB_GPU_REF_CTRL_DIVISOR0 0x1 - # 000 = IOPLL_TO_FPD; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of - # he new clock. This is not usually an issue, but designers must be aware.) + # 000 = IOPLL_TO_FPD; 010 = VPLL; 011 = DPLL; (This signal may only be tog + # gled after 4 cycles of the old clock and 4 cycles of the new clock. This + # is not usually an issue, but designers must be aware.) # PSU_CRF_APB_GPU_REF_CTRL_SRCSEL 0x0 - # Clock active signal. Switch to 0 to disable the clock, which will stop clock for GPU (and both Pixel Processors). + # Clock active signal. Switch to 0 to disable the clock, which will stop c + # lock for GPU (and both Pixel Processors). # PSU_CRF_APB_GPU_REF_CTRL_CLKACT 0x1 - # Clock active signal for Pixel Processor. Switch to 0 to disable the clock only to this Pixel Processor + # Clock active signal for Pixel Processor. Switch to 0 to disable the cloc + # k only to this Pixel Processor # PSU_CRF_APB_GPU_REF_CTRL_PP0_CLKACT 0x1 - # Clock active signal for Pixel Processor. Switch to 0 to disable the clock only to this Pixel Processor + # Clock active signal for Pixel Processor. Switch to 0 to disable the cloc + # k only to this Pixel Processor # PSU_CRF_APB_GPU_REF_CTRL_PP1_CLKACT 0x1 # This register controls this reference clock @@ -1103,8 +1076,9 @@ set psu_clock_init_data { # 6 bit divider # PSU_CRF_APB_GDMA_REF_CTRL_DIVISOR0 0x2 - # 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - # lock. This is not usually an issue, but designers must be aware.) + # 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled aft + # er 4 cycles of the old clock and 4 cycles of the new clock. This is not + # usually an issue, but designers must be aware.) # PSU_CRF_APB_GDMA_REF_CTRL_SRCSEL 0x0 # Clock active signal. Switch to 0 to disable the clock @@ -1118,8 +1092,9 @@ set psu_clock_init_data { # 6 bit divider # PSU_CRF_APB_DPDMA_REF_CTRL_DIVISOR0 0x2 - # 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - # lock. This is not usually an issue, but designers must be aware.) + # 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled aft + # er 4 cycles of the old clock and 4 cycles of the new clock. This is not + # usually an issue, but designers must be aware.) # PSU_CRF_APB_DPDMA_REF_CTRL_SRCSEL 0x0 # Clock active signal. Switch to 0 to disable the clock @@ -1133,23 +1108,25 @@ set psu_clock_init_data { # 6 bit divider # PSU_CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0 0x2 - # 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - # lock. This is not usually an issue, but designers must be aware.) - # PSU_CRF_APB_TOPSW_MAIN_CTRL_SRCSEL 0x2 + # 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled aft + # er 4 cycles of the old clock and 4 cycles of the new clock. This is not + # usually an issue, but designers must be aware.) + # PSU_CRF_APB_TOPSW_MAIN_CTRL_SRCSEL 0x3 # Clock active signal. Switch to 0 to disable the clock # PSU_CRF_APB_TOPSW_MAIN_CTRL_CLKACT 0x1 # This register controls this reference clock - #(OFFSET, MASK, VALUE) (0XFD1A00C0, 0x01003F07U ,0x01000202U) */ - mask_write 0XFD1A00C0 0x01003F07 0x01000202 + #(OFFSET, MASK, VALUE) (0XFD1A00C0, 0x01003F07U ,0x01000203U) */ + mask_write 0XFD1A00C0 0x01003F07 0x01000203 # Register : TOPSW_LSBUS_CTRL @ 0XFD1A00C4

# 6 bit divider # PSU_CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0 0x5 - # 000 = APLL; 010 = IOPLL_TO_FPD; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of - # he new clock. This is not usually an issue, but designers must be aware.) + # 000 = APLL; 010 = IOPLL_TO_FPD; 011 = DPLL; (This signal may only be tog + # gled after 4 cycles of the old clock and 4 cycles of the new clock. This + # is not usually an issue, but designers must be aware.) # PSU_CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL 0x2 # Clock active signal. Switch to 0 to disable the clock @@ -1163,8 +1140,9 @@ set psu_clock_init_data { # 6 bit divider # PSU_CRF_APB_DBG_TSTMP_CTRL_DIVISOR0 0x2 - # 000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of - # he new clock. This is not usually an issue, but designers must be aware.) + # 000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be tog + # gled after 4 cycles of the old clock and 4 cycles of the new clock. This + # is not usually an issue, but designers must be aware.) # PSU_CRF_APB_DBG_TSTMP_CTRL_SRCSEL 0x0 # This register controls this reference clock @@ -1172,20 +1150,24 @@ set psu_clock_init_data { mask_write 0XFD1A00F8 0x00003F07 0x00000200 # Register : IOU_TTC_APB_CLK @ 0XFF180380

- # 00" = Select the APB switch clock for the APB interface of TTC0'01" = Select the PLL ref clock for the APB interface of TTC0' - # 0" = Select the R5 clock for the APB interface of TTC0 + # 00" = Select the APB switch clock for the APB interface of TTC0'01" = Se + # lect the PLL ref clock for the APB interface of TTC0'10" = Select the R5 + # clock for the APB interface of TTC0 # PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL 0 - # 00" = Select the APB switch clock for the APB interface of TTC1'01" = Select the PLL ref clock for the APB interface of TTC1' - # 0" = Select the R5 clock for the APB interface of TTC1 + # 00" = Select the APB switch clock for the APB interface of TTC1'01" = Se + # lect the PLL ref clock for the APB interface of TTC1'10" = Select the R5 + # clock for the APB interface of TTC1 # PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL 0 - # 00" = Select the APB switch clock for the APB interface of TTC2'01" = Select the PLL ref clock for the APB interface of TTC2' - # 0" = Select the R5 clock for the APB interface of TTC2 + # 00" = Select the APB switch clock for the APB interface of TTC2'01" = Se + # lect the PLL ref clock for the APB interface of TTC2'10" = Select the R5 + # clock for the APB interface of TTC2 # PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL 0 - # 00" = Select the APB switch clock for the APB interface of TTC3'01" = Select the PLL ref clock for the APB interface of TTC3' - # 0" = Select the R5 clock for the APB interface of TTC3 + # 00" = Select the APB switch clock for the APB interface of TTC3'01" = Se + # lect the PLL ref clock for the APB interface of TTC3'10" = Select the R5 + # clock for the APB interface of TTC3 # PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL 0 # TTC APB clock select @@ -1193,7 +1175,8 @@ set psu_clock_init_data { mask_write 0XFF180380 0x000000FF 0x00000000 # Register : WDT_CLK_SEL @ 0XFD610100

- # System watchdog timer clock source selection: 0: Internal APB clock 1: External (PL clock via EMIO or Pinout clock via MIO) + # System watchdog timer clock source selection: 0: Internal APB clock 1: E + # xternal (PL clock via EMIO or Pinout clock via MIO) # PSU_FPD_SLCR_WDT_CLK_SEL_SELECT 0 # SWDT clock source select @@ -1201,8 +1184,8 @@ set psu_clock_init_data { mask_write 0XFD610100 0x00000001 0x00000000 # Register : WDT_CLK_SEL @ 0XFF180300

- # System watchdog timer clock source selection: 0: internal clock APB clock 1: external clock from PL via EMIO, or from pinout - # ia MIO + # System watchdog timer clock source selection: 0: internal clock APB cloc + # k 1: external clock from PL via EMIO, or from pinout via MIO # PSU_IOU_SLCR_WDT_CLK_SEL_SELECT 0 # SWDT clock source select @@ -1210,7 +1193,8 @@ set psu_clock_init_data { mask_write 0XFF180300 0x00000001 0x00000000 # Register : CSUPMU_WDT_CLK_SEL @ 0XFF410050

- # System watchdog timer clock source selection: 0: internal clock APB clock 1: external clock pss_ref_clk + # System watchdog timer clock source selection: 0: internal clock APB cloc + # k 1: external clock pss_ref_clk # PSU_LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT 0 # SWDT clock source select @@ -1231,72 +1215,90 @@ set psu_ddr_init_data { mask_write 0XFD1A0108 0x00000008 0x00000008 # Register : MSTR @ 0XFD070000

- # Indicates the configuration of the device used in the system. - 00 - x4 device - 01 - x8 device - 10 - x16 device - 11 - x32 - # evice + # Indicates the configuration of the device used in the system. - 00 - x4 + # device - 01 - x8 device - 10 - x16 device - 11 - x32 device # PSU_DDRC_MSTR_DEVICE_CONFIG 0x1 - # Choose which registers are used. - 0 - Original registers - 1 - Shadow registers + # Choose which registers are used. - 0 - Original registers - 1 - Shadow r + # egisters # PSU_DDRC_MSTR_FREQUENCY_MODE 0x0 - # Only present for multi-rank configurations. Each bit represents one rank. For two-rank configurations, only bits[25:24] are p - # esent. - 1 - populated - 0 - unpopulated LSB is the lowest rank number. For 2 ranks following combinations are legal: - 01 - - # ne rank - 11 - Two ranks - Others - Reserved. For 4 ranks following combinations are legal: - 0001 - One rank - 0011 - Two ra - # ks - 1111 - Four ranks + # Only present for multi-rank configurations. Each bit represents one rank + # . For two-rank configurations, only bits[25:24] are present. - 1 - popul + # ated - 0 - unpopulated LSB is the lowest rank number. For 2 ranks follow + # ing combinations are legal: - 01 - One rank - 11 - Two ranks - Others - + # Reserved. For 4 ranks following combinations are legal: - 0001 - One ran + # k - 0011 - Two ranks - 1111 - Four ranks # PSU_DDRC_MSTR_ACTIVE_RANKS 0x1 - # SDRAM burst length used: - 0001 - Burst length of 2 (only supported for mDDR) - 0010 - Burst length of 4 - 0100 - Burst lengt - # of 8 - 1000 - Burst length of 16 (only supported for mDDR, LPDDR2, and LPDDR4) All other values are reserved. This controls - # he burst size used to access the SDRAM. This must match the burst length mode register setting in the SDRAM. (For BC4/8 on-th - # -fly mode of DDR3 and DDR4, set this field to 0x0100) Burst length of 2 is not supported with AXI ports when MEMC_BURST_LENGT - # is 8. Burst length of 2 is only supported with MEMC_FREQ_RATIO = 1 + # SDRAM burst length used: - 0001 - Burst length of 2 (only supported for + # mDDR) - 0010 - Burst length of 4 - 0100 - Burst length of 8 - 1000 - Bur + # st length of 16 (only supported for mDDR, LPDDR2, and LPDDR4) All other + # values are reserved. This controls the burst size used to access the SDR + # AM. This must match the burst length mode register setting in the SDRAM. + # (For BC4/8 on-the-fly mode of DDR3 and DDR4, set this field to 0x0100) + # Burst length of 2 is not supported with AXI ports when MEMC_BURST_LENGTH + # is 8. Burst length of 2 is only supported with MEMC_FREQ_RATIO = 1 # PSU_DDRC_MSTR_BURST_RDWR 0x4 - # Set to 1 when the uMCTL2 and DRAM has to be put in DLL-off mode for low frequency operation. Set to 0 to put uMCTL2 and DRAM - # n DLL-on mode for normal frequency operation. If DDR4 CRC/parity retry is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), d - # l_off_mode is not supported, and this bit must be set to '0'. + # Set to 1 when the uMCTL2 and DRAM has to be put in DLL-off mode for low + # frequency operation. Set to 0 to put uMCTL2 and DRAM in DLL-on mode for + # normal frequency operation. If DDR4 CRC/parity retry is enabled (CRCPARC + # TL1.crc_parity_retry_enable = 1), dll_off_mode is not supported, and thi + # s bit must be set to '0'. # PSU_DDRC_MSTR_DLL_OFF_MODE 0x0 - # Selects proportion of DQ bus width that is used by the SDRAM - 00 - Full DQ bus width to SDRAM - 01 - Half DQ bus width to SD - # AM - 10 - Quarter DQ bus width to SDRAM - 11 - Reserved. Note that half bus width mode is only supported when the SDRAM bus w - # dth is a multiple of 16, and quarter bus width mode is only supported when the SDRAM bus width is a multiple of 32 and the co - # figuration parameter MEMC_QBUS_SUPPORT is set. Bus width refers to DQ bus width (excluding any ECC width). + # Selects proportion of DQ bus width that is used by the SDRAM - 00 - Full + # DQ bus width to SDRAM - 01 - Half DQ bus width to SDRAM - 10 - Quarter + # DQ bus width to SDRAM - 11 - Reserved. Note that half bus width mode is + # only supported when the SDRAM bus width is a multiple of 16, and quarter + # bus width mode is only supported when the SDRAM bus width is a multiple + # of 32 and the configuration parameter MEMC_QBUS_SUPPORT is set. Bus wid + # th refers to DQ bus width (excluding any ECC width). # PSU_DDRC_MSTR_DATA_BUS_WIDTH 0x0 - # 1 indicates put the DRAM in geardown mode (2N) and 0 indicates put the DRAM in normal mode (1N). This register can be changed - # only when the Controller is in self-refresh mode. This signal must be set the same value as MR3 bit A3. Note: Geardown mode - # s not supported if the configuration parameter MEMC_CMD_RTN2IDLE is set + # 1 indicates put the DRAM in geardown mode (2N) and 0 indicates put the D + # RAM in normal mode (1N). This register can be changed, only when the Con + # troller is in self-refresh mode. This signal must be set the same value + # as MR3 bit A3. Note: Geardown mode is not supported if the configuration + # parameter MEMC_CMD_RTN2IDLE is set # PSU_DDRC_MSTR_GEARDOWN_MODE 0x0 - # If 1, then uMCTL2 uses 2T timing. Otherwise, uses 1T timing. In 2T timing, all command signals (except chip select) are held - # or 2 clocks on the SDRAM bus. Chip select is asserted on the second cycle of the command Note: 2T timing is not supported in - # PDDR2/LPDDR3/LPDDR4 mode Note: 2T timing is not supported if the configuration parameter MEMC_CMD_RTN2IDLE is set Note: 2T ti - # ing is not supported in DDR4 geardown mode. + # If 1, then uMCTL2 uses 2T timing. Otherwise, uses 1T timing. In 2T timin + # g, all command signals (except chip select) are held for 2 clocks on the + # SDRAM bus. Chip select is asserted on the second cycle of the command N + # ote: 2T timing is not supported in LPDDR2/LPDDR3/LPDDR4 mode Note: 2T ti + # ming is not supported if the configuration parameter MEMC_CMD_RTN2IDLE i + # s set Note: 2T timing is not supported in DDR4 geardown mode. # PSU_DDRC_MSTR_EN_2T_TIMING_MODE 0x0 - # When set, enable burst-chop in DDR3/DDR4. Burst Chop for Reads is exercised only in HIF configurations (UMCTL2_INCL_ARB not s - # t) and if in full bus width mode (MSTR.data_bus_width = 00). Burst Chop for Writes is exercised only if Partial Writes enable - # (UMCTL2_PARTIAL_WR=1) and if CRC is disabled (CRCPARCTL1.crc_enable = 0). If DDR4 CRC/parity retry is enabled (CRCPARCTL1.cr - # _parity_retry_enable = 1), burst chop is not supported, and this bit must be set to '0' + # When set, enable burst-chop in DDR3/DDR4. Burst Chop for Reads is exerci + # sed only in HIF configurations (UMCTL2_INCL_ARB not set) and if in full + # bus width mode (MSTR.data_bus_width = 00). Burst Chop for Writes is exer + # cised only if Partial Writes enabled (UMCTL2_PARTIAL_WR=1) and if CRC is + # disabled (CRCPARCTL1.crc_enable = 0). If DDR4 CRC/parity retry is enabl + # ed (CRCPARCTL1.crc_parity_retry_enable = 1), burst chop is not supported + # , and this bit must be set to '0' # PSU_DDRC_MSTR_BURSTCHOP 0x0 - # Select LPDDR4 SDRAM - 1 - LPDDR4 SDRAM device in use. - 0 - non-LPDDR4 device in use Present only in designs configured to su - # port LPDDR4. + # Select LPDDR4 SDRAM - 1 - LPDDR4 SDRAM device in use. - 0 - non-LPDDR4 d + # evice in use Present only in designs configured to support LPDDR4. # PSU_DDRC_MSTR_LPDDR4 0x0 - # Select DDR4 SDRAM - 1 - DDR4 SDRAM device in use. - 0 - non-DDR4 device in use Present only in designs configured to support - # DR4. + # Select DDR4 SDRAM - 1 - DDR4 SDRAM device in use. - 0 - non-DDR4 device + # in use Present only in designs configured to support DDR4. # PSU_DDRC_MSTR_DDR4 0x1 - # Select LPDDR3 SDRAM - 1 - LPDDR3 SDRAM device in use. - 0 - non-LPDDR3 device in use Present only in designs configured to su - # port LPDDR3. + # Select LPDDR3 SDRAM - 1 - LPDDR3 SDRAM device in use. - 0 - non-LPDDR3 d + # evice in use Present only in designs configured to support LPDDR3. # PSU_DDRC_MSTR_LPDDR3 0x0 - # Select LPDDR2 SDRAM - 1 - LPDDR2 SDRAM device in use. - 0 - non-LPDDR2 device in use Present only in designs configured to su - # port LPDDR2. + # Select LPDDR2 SDRAM - 1 - LPDDR2 SDRAM device in use. - 0 - non-LPDDR2 d + # evice in use Present only in designs configured to support LPDDR2. # PSU_DDRC_MSTR_LPDDR2 0x0 - # Select DDR3 SDRAM - 1 - DDR3 SDRAM device in use - 0 - non-DDR3 SDRAM device in use Only present in designs that support DDR3 - # + # Select DDR3 SDRAM - 1 - DDR3 SDRAM device in use - 0 - non-DDR3 SDRAM de + # vice in use Only present in designs that support DDR3. # PSU_DDRC_MSTR_DDR3 0x0 # Master Register @@ -1304,74 +1306,97 @@ set psu_ddr_init_data { mask_write 0XFD070000 0xE30FBE3D 0x41040010 # Register : MRCTRL0 @ 0XFD070010

- # Setting this register bit to 1 triggers a mode register read or write operation. When the MR operation is complete, the uMCTL - # automatically clears this bit. The other register fields of this register must be written in a separate APB transaction, bef - # re setting this mr_wr bit. It is recommended NOT to set this signal if in Init, Deep power-down or MPSM operating modes. + # Setting this register bit to 1 triggers a mode register read or write op + # eration. When the MR operation is complete, the uMCTL2 automatically cle + # ars this bit. The other register fields of this register must be written + # in a separate APB transaction, before setting this mr_wr bit. It is rec + # ommended NOT to set this signal if in Init, Deep power-down or MPSM oper + # ating modes. # PSU_DDRC_MRCTRL0_MR_WR 0x0 - # Address of the mode register that is to be written to. - 0000 - MR0 - 0001 - MR1 - 0010 - MR2 - 0011 - MR3 - 0100 - MR4 - 010 - # - MR5 - 0110 - MR6 - 0111 - MR7 Don't Care for LPDDR2/LPDDR3/LPDDR4 (see MRCTRL1.mr_data for mode register addressing in LPD - # R2/LPDDR3/LPDDR4) This signal is also used for writing to control words of RDIMMs. In that case, it corresponds to the bank a - # dress bits sent to the RDIMM In case of DDR4, the bit[3:2] corresponds to the bank group bits. Therefore, the bit[3] as well - # s the bit[2:0] must be set to an appropriate value which is considered both the Address Mirroring of UDIMMs/RDIMMs and the Ou - # put Inversion of RDIMMs. + # Address of the mode register that is to be written to. - 0000 - MR0 - 00 + # 01 - MR1 - 0010 - MR2 - 0011 - MR3 - 0100 - MR4 - 0101 - MR5 - 0110 - MR + # 6 - 0111 - MR7 Don't Care for LPDDR2/LPDDR3/LPDDR4 (see MRCTRL1.mr_data + # for mode register addressing in LPDDR2/LPDDR3/LPDDR4) This signal is als + # o used for writing to control words of RDIMMs. In that case, it correspo + # nds to the bank address bits sent to the RDIMM In case of DDR4, the bit[ + # 3:2] corresponds to the bank group bits. Therefore, the bit[3] as well a + # s the bit[2:0] must be set to an appropriate value which is considered b + # oth the Address Mirroring of UDIMMs/RDIMMs and the Output Inversion of R + # DIMMs. # PSU_DDRC_MRCTRL0_MR_ADDR 0x0 - # Controls which rank is accessed by MRCTRL0.mr_wr. Normally, it is desired to access all ranks, so all bits should be set to 1 - # However, for multi-rank UDIMMs/RDIMMs which implement address mirroring, it may be necessary to access ranks individually. E - # amples (assume uMCTL2 is configured for 4 ranks): - 0x1 - select rank 0 only - 0x2 - select rank 1 only - 0x5 - select ranks - # and 2 - 0xA - select ranks 1 and 3 - 0xF - select ranks 0, 1, 2 and 3 + # Controls which rank is accessed by MRCTRL0.mr_wr. Normally, it is desire + # d to access all ranks, so all bits should be set to 1. However, for mult + # i-rank UDIMMs/RDIMMs which implement address mirroring, it may be necess + # ary to access ranks individually. Examples (assume uMCTL2 is configured + # for 4 ranks): - 0x1 - select rank 0 only - 0x2 - select rank 1 only - 0x + # 5 - select ranks 0 and 2 - 0xA - select ranks 1 and 3 - 0xF - select ran + # ks 0, 1, 2 and 3 # PSU_DDRC_MRCTRL0_MR_RANK 0x3 - # Indicates whether Software intervention is allowed via MRCTRL0/MRCTRL1 before automatic SDRAM initialization routine or not. - # or DDR4, this bit can be used to initialize the DDR4 RCD (MR7) before automatic SDRAM initialization. For LPDDR4, this bit ca - # be used to program additional mode registers before automatic SDRAM initialization if necessary. Note: This must be cleared - # o 0 after completing Software operation. Otherwise, SDRAM initialization routine will not re-start. - 0 - Software interventi - # n is not allowed - 1 - Software intervention is allowed + # Indicates whether Software intervention is allowed via MRCTRL0/MRCTRL1 b + # efore automatic SDRAM initialization routine or not. For DDR4, this bit + # can be used to initialize the DDR4 RCD (MR7) before automatic SDRAM init + # ialization. For LPDDR4, this bit can be used to program additional mode + # registers before automatic SDRAM initialization if necessary. Note: This + # must be cleared to 0 after completing Software operation. Otherwise, SD + # RAM initialization routine will not re-start. - 0 - Software interventio + # n is not allowed - 1 - Software intervention is allowed # PSU_DDRC_MRCTRL0_SW_INIT_INT 0x0 - # Indicates whether the mode register operation is MRS in PDA mode or not - 0 - MRS - 1 - MRS in Per DRAM Addressability mode + # Indicates whether the mode register operation is MRS in PDA mode or not + # - 0 - MRS - 1 - MRS in Per DRAM Addressability mode # PSU_DDRC_MRCTRL0_PDA_EN 0x0 - # Indicates whether the mode register operation is MRS or WR/RD for MPR (only supported for DDR4) - 0 - MRS - 1 - WR/RD for MPR + # Indicates whether the mode register operation is MRS or WR/RD for MPR (o + # nly supported for DDR4) - 0 - MRS - 1 - WR/RD for MPR # PSU_DDRC_MRCTRL0_MPR_EN 0x0 - # Indicates whether the mode register operation is read or write. Only used for LPDDR2/LPDDR3/LPDDR4/DDR4. - 0 - Write - 1 - Re - # d + # Indicates whether the mode register operation is read or write. Only use + # d for LPDDR2/LPDDR3/LPDDR4/DDR4. - 0 - Write - 1 - Read # PSU_DDRC_MRCTRL0_MR_TYPE 0x0 - # Mode Register Read/Write Control Register 0. Note: Do not enable more than one of the following fields simultaneously: - sw_i - # it_int - pda_en - mpr_en + # Mode Register Read/Write Control Register 0. Note: Do not enable more th + # an one of the following fields simultaneously: - sw_init_int - pda_en - + # mpr_en #(OFFSET, MASK, VALUE) (0XFD070010, 0x8000F03FU ,0x00000030U) */ mask_write 0XFD070010 0x8000F03F 0x00000030 # Register : DERATEEN @ 0XFD070020

- # Derate value of tRC for LPDDR4 - 0 - Derating uses +1. - 1 - Derating uses +2. - 2 - Derating uses +3. - 3 - Derating uses +4 - # Present only in designs configured to support LPDDR4. The required number of cycles for derating can be determined by dividi - # g 3.75ns by the core_ddrc_core_clk period, and rounding up the next integer. - # PSU_DDRC_DERATEEN_RC_DERATE_VALUE 0x3 + # Derate value of tRC for LPDDR4 - 0 - Derating uses +1. - 1 - Derating us + # es +2. - 2 - Derating uses +3. - 3 - Derating uses +4. Present only in d + # esigns configured to support LPDDR4. The required number of cycles for d + # erating can be determined by dividing 3.75ns by the core_ddrc_core_clk p + # eriod, and rounding up the next integer. + # PSU_DDRC_DERATEEN_RC_DERATE_VALUE 0x2 - # Derate byte Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4 Indicates which byte of the MRR data is used f - # r derating. The maximum valid value depends on MEMC_DRAM_TOTAL_DATA_WIDTH. + # Derate byte Present only in designs configured to support LPDDR2/LPDDR3/ + # LPDDR4 Indicates which byte of the MRR data is used for derating. The ma + # ximum valid value depends on MEMC_DRAM_TOTAL_DATA_WIDTH. # PSU_DDRC_DERATEEN_DERATE_BYTE 0x0 - # Derate value - 0 - Derating uses +1. - 1 - Derating uses +2. Present only in designs configured to support LPDDR2/LPDDR3/LPDD - # 4 Set to 0 for all LPDDR2 speed grades as derating value of +1.875 ns is less than a core_ddrc_core_clk period. Can be 0 or 1 - # for LPDDR3/LPDDR4, depending if +1.875 ns is less than a core_ddrc_core_clk period or not. + # Derate value - 0 - Derating uses +1. - 1 - Derating uses +2. Present onl + # y in designs configured to support LPDDR2/LPDDR3/LPDDR4 Set to 0 for all + # LPDDR2 speed grades as derating value of +1.875 ns is less than a core_ + # ddrc_core_clk period. Can be 0 or 1 for LPDDR3/LPDDR4, depending if +1.8 + # 75 ns is less than a core_ddrc_core_clk period or not. # PSU_DDRC_DERATEEN_DERATE_VALUE 0x0 - # Enables derating - 0 - Timing parameter derating is disabled - 1 - Timing parameter derating is enabled using MR4 read value. - # Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4 This field must be set to '0' for non-LPDDR2/LPDDR3/LPDDR4 - # mode. + # Enables derating - 0 - Timing parameter derating is disabled - 1 - Timin + # g parameter derating is enabled using MR4 read value. Present only in de + # signs configured to support LPDDR2/LPDDR3/LPDDR4 This field must be set + # to '0' for non-LPDDR2/LPDDR3/LPDDR4 mode. # PSU_DDRC_DERATEEN_DERATE_ENABLE 0x0 # Temperature Derate Enable Register - #(OFFSET, MASK, VALUE) (0XFD070020, 0x000003F3U ,0x00000300U) */ - mask_write 0XFD070020 0x000003F3 0x00000300 + #(OFFSET, MASK, VALUE) (0XFD070020, 0x000003F3U ,0x00000200U) */ + mask_write 0XFD070020 0x000003F3 0x00000200 # Register : DERATEINT @ 0XFD070024

- # Interval between two MR4 reads, used to derate the timing parameters. Present only in designs configured to support LPDDR2/LP - # DR3/LPDDR4. This register must not be set to zero + # Interval between two MR4 reads, used to derate the timing parameters. Pr + # esent only in designs configured to support LPDDR2/LPDDR3/LPDDR4. This r + # egister must not be set to zero # PSU_DDRC_DERATEINT_MR4_READ_INTERVAL 0x800000 # Temperature Derate Interval Register @@ -1379,41 +1404,57 @@ set psu_ddr_init_data { mask_write 0XFD070024 0xFFFFFFFF 0x00800000 # Register : PWRCTL @ 0XFD070030

- # Self refresh state is an intermediate state to enter to Self refresh power down state or exit Self refresh power down state f - # r LPDDR4. This register controls transition from the Self refresh state. - 1 - Prohibit transition from Self refresh state - - # - Allow transition from Self refresh state + # Self refresh state is an intermediate state to enter to Self refresh pow + # er down state or exit Self refresh power down state for LPDDR4. This reg + # ister controls transition from the Self refresh state. - 1 - Prohibit tr + # ansition from Self refresh state - 0 - Allow transition from Self refres + # h state # PSU_DDRC_PWRCTL_STAY_IN_SELFREF 0x0 - # A value of 1 to this register causes system to move to Self Refresh state immediately, as long as it is not in INIT or DPD/MP - # M operating_mode. This is referred to as Software Entry/Exit to Self Refresh. - 1 - Software Entry to Self Refresh - 0 - Soft - # are Exit from Self Refresh + # A value of 1 to this register causes system to move to Self Refresh stat + # e immediately, as long as it is not in INIT or DPD/MPSM operating_mode. + # This is referred to as Software Entry/Exit to Self Refresh. - 1 - Softwa + # re Entry to Self Refresh - 0 - Software Exit from Self Refresh # PSU_DDRC_PWRCTL_SELFREF_SW 0x0 - # When this is 1, the uMCTL2 puts the SDRAM into maximum power saving mode when the transaction store is empty. This register m - # st be reset to '0' to bring uMCTL2 out of maximum power saving mode. Present only in designs configured to support DDR4. For - # on-DDR4, this register should not be set to 1. Note that MPSM is not supported when using a DWC DDR PHY, if the PHY parameter - # DWC_AC_CS_USE is disabled, as the MPSM exit sequence requires the chip-select signal to toggle. FOR PERFORMANCE ONLY. + # When this is 1, the uMCTL2 puts the SDRAM into maximum power saving mode + # when the transaction store is empty. This register must be reset to '0' + # to bring uMCTL2 out of maximum power saving mode. Present only in desig + # ns configured to support DDR4. For non-DDR4, this register should not be + # set to 1. Note that MPSM is not supported when using a DWC DDR PHY, if + # the PHY parameter DWC_AC_CS_USE is disabled, as the MPSM exit sequence r + # equires the chip-select signal to toggle. FOR PERFORMANCE ONLY. # PSU_DDRC_PWRCTL_MPSM_EN 0x0 - # Enable the assertion of dfi_dram_clk_disable whenever a clock is not required by the SDRAM. If set to 0, dfi_dram_clk_disable - # is never asserted. Assertion of dfi_dram_clk_disable is as follows: In DDR2/DDR3, can only be asserted in Self Refresh. In DD - # 4, can be asserted in following: - in Self Refresh. - in Maximum Power Saving Mode In mDDR/LPDDR2/LPDDR3, can be asserted in - # ollowing: - in Self Refresh - in Power Down - in Deep Power Down - during Normal operation (Clock Stop) In LPDDR4, can be ass - # rted in following: - in Self Refresh Power Down - in Power Down - during Normal operation (Clock Stop) + # Enable the assertion of dfi_dram_clk_disable whenever a clock is not req + # uired by the SDRAM. If set to 0, dfi_dram_clk_disable is never asserted. + # Assertion of dfi_dram_clk_disable is as follows: In DDR2/DDR3, can only + # be asserted in Self Refresh. In DDR4, can be asserted in following: - i + # n Self Refresh. - in Maximum Power Saving Mode In mDDR/LPDDR2/LPDDR3, ca + # n be asserted in following: - in Self Refresh - in Power Down - in Deep + # Power Down - during Normal operation (Clock Stop) In LPDDR4, can be asse + # rted in following: - in Self Refresh Power Down - in Power Down - during + # Normal operation (Clock Stop) # PSU_DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE 0x0 - # When this is 1, uMCTL2 puts the SDRAM into deep power-down mode when the transaction store is empty. This register must be re - # et to '0' to bring uMCTL2 out of deep power-down mode. Controller performs automatic SDRAM initialization on deep power-down - # xit. Present only in designs configured to support mDDR or LPDDR2 or LPDDR3. For non-mDDR/non-LPDDR2/non-LPDDR3, this registe - # should not be set to 1. FOR PERFORMANCE ONLY. + # When this is 1, uMCTL2 puts the SDRAM into deep power-down mode when the + # transaction store is empty. This register must be reset to '0' to bring + # uMCTL2 out of deep power-down mode. Controller performs automatic SDRAM + # initialization on deep power-down exit. Present only in designs configu + # red to support mDDR or LPDDR2 or LPDDR3. For non-mDDR/non-LPDDR2/non-LPD + # DR3, this register should not be set to 1. FOR PERFORMANCE ONLY. # PSU_DDRC_PWRCTL_DEEPPOWERDOWN_EN 0x0 - # If true then the uMCTL2 goes into power-down after a programmable number of cycles 'maximum idle clocks before power down' (P - # RTMG.powerdown_to_x32). This register bit may be re-programmed during the course of normal operation. + # If true then the uMCTL2 goes into power-down after a programmable number + # of cycles 'maximum idle clocks before power down' (PWRTMG.powerdown_to_ + # x32). This register bit may be re-programmed during the course of normal + # operation. # PSU_DDRC_PWRCTL_POWERDOWN_EN 0x0 - # If true then the uMCTL2 puts the SDRAM into Self Refresh after a programmable number of cycles 'maximum idle clocks before Se - # f Refresh (PWRTMG.selfref_to_x32)'. This register bit may be re-programmed during the course of normal operation. + # If true then the uMCTL2 puts the SDRAM into Self Refresh after a program + # mable number of cycles 'maximum idle clocks before Self Refresh (PWRTMG. + # selfref_to_x32)'. This register bit may be re-programmed during the cour + # se of normal operation. # PSU_DDRC_PWRCTL_SELFREF_EN 0x0 # Low Power Control Register @@ -1421,17 +1462,22 @@ set psu_ddr_init_data { mask_write 0XFD070030 0x0000007F 0x00000000 # Register : PWRTMG @ 0XFD070034

- # After this many clocks of NOP or deselect the uMCTL2 automatically puts the SDRAM into Self Refresh. This must be enabled in - # he PWRCTL.selfref_en. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY. + # After this many clocks of NOP or deselect the uMCTL2 automatically puts + # the SDRAM into Self Refresh. This must be enabled in the PWRCTL.selfref_ + # en. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY. # PSU_DDRC_PWRTMG_SELFREF_TO_X32 0x40 - # Minimum deep power-down time. For mDDR, value from the JEDEC specification is 0 as mDDR exits from deep power-down mode immed - # ately after PWRCTL.deeppowerdown_en is de-asserted. For LPDDR2/LPDDR3, value from the JEDEC specification is 500us. Unit: Mul - # iples of 4096 clocks. Present only in designs configured to support mDDR, LPDDR2 or LPDDR3. FOR PERFORMANCE ONLY. + # Minimum deep power-down time. For mDDR, value from the JEDEC specificati + # on is 0 as mDDR exits from deep power-down mode immediately after PWRCTL + # .deeppowerdown_en is de-asserted. For LPDDR2/LPDDR3, value from the JEDE + # C specification is 500us. Unit: Multiples of 4096 clocks. Present only i + # n designs configured to support mDDR, LPDDR2 or LPDDR3. FOR PERFORMANCE + # ONLY. # PSU_DDRC_PWRTMG_T_DPD_X4096 0x84 - # After this many clocks of NOP or deselect the uMCTL2 automatically puts the SDRAM into power-down. This must be enabled in th - # PWRCTL.powerdown_en. Unit: Multiples of 32 clocks FOR PERFORMANCE ONLY. + # After this many clocks of NOP or deselect the uMCTL2 automatically puts + # the SDRAM into power-down. This must be enabled in the PWRCTL.powerdown_ + # en. Unit: Multiples of 32 clocks FOR PERFORMANCE ONLY. # PSU_DDRC_PWRTMG_POWERDOWN_TO_X32 0x10 # Low Power Timing Register @@ -1439,60 +1485,100 @@ set psu_ddr_init_data { mask_write 0XFD070034 0x00FFFF1F 0x00408410 # Register : RFSHCTL0 @ 0XFD070050

- # Threshold value in number of clock cycles before the critical refresh or page timer expires. A critical refresh is to be issu - # d before this threshold is reached. It is recommended that this not be changed from the default value, currently shown as 0x2 - # It must always be less than internally used t_rfc_nom_x32. Note that, in LPDDR2/LPDDR3/LPDDR4, internally used t_rfc_nom_x32 - # may be equal to RFSHTMG.t_rfc_nom_x32>>2 if derating is enabled (DERATEEN.derate_enable=1). Otherwise, internally used t_rfc_ - # om_x32 will be equal to RFSHTMG.t_rfc_nom_x32. Unit: Multiples of 32 clocks. + # Threshold value in number of clock cycles before the critical refresh or + # page timer expires. A critical refresh is to be issued before this thre + # shold is reached. It is recommended that this not be changed from the de + # fault value, currently shown as 0x2. It must always be less than interna + # lly used t_rfc_nom_x32. Note that, in LPDDR2/LPDDR3/LPDDR4, internally u + # sed t_rfc_nom_x32 may be equal to RFSHTMG.t_rfc_nom_x32>>2 if derating i + # s enabled (DERATEEN.derate_enable=1). Otherwise, internally used t_rfc_n + # om_x32 will be equal to RFSHTMG.t_rfc_nom_x32. Unit: Multiples of 32 clo + # cks. # PSU_DDRC_RFSHCTL0_REFRESH_MARGIN 0x2 - # If the refresh timer (tRFCnom, also known as tREFI) has expired at least once, but it has not expired (RFSHCTL0.refresh_burst - # 1) times yet, then a speculative refresh may be performed. A speculative refresh is a refresh performed at a time when refres - # would be useful, but before it is absolutely required. When the SDRAM bus is idle for a period of time determined by this RF - # HCTL0.refresh_to_x32 and the refresh timer has expired at least once since the last refresh, then a speculative refresh is pe - # formed. Speculative refreshes continues successively until there are no refreshes pending or until new reads or writes are is - # ued to the uMCTL2. FOR PERFORMANCE ONLY. + # If the refresh timer (tRFCnom, also known as tREFI) has expired at least + # once, but it has not expired (RFSHCTL0.refresh_burst+1) times yet, then + # a speculative refresh may be performed. A speculative refresh is a refr + # esh performed at a time when refresh would be useful, but before it is a + # bsolutely required. When the SDRAM bus is idle for a period of time dete + # rmined by this RFSHCTL0.refresh_to_x32 and the refresh timer has expired + # at least once since the last refresh, then a speculative refresh is per + # formed. Speculative refreshes continues successively until there are no + # refreshes pending or until new reads or writes are issued to the uMCTL2. + # FOR PERFORMANCE ONLY. # PSU_DDRC_RFSHCTL0_REFRESH_TO_X32 0x10 - # The programmed value + 1 is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the re - # reshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of re - # reshes. Therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for - # RFSHCTL.refresh_burst slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshe - # . - 0 - single refresh - 1 - burst-of-2 refresh - 7 - burst-of-8 refresh For information on burst refresh feature refer to se - # tion 3.9 of DDR2 JEDEC specification - JESD79-2F.pdf. For DDR2/3, the refresh is always per-rank and not per-bank. The rank r - # fresh can be accumulated over 8*tREFI cycles using the burst refresh feature. In DDR4 mode, according to Fine Granularity fea - # ure, 8 refreshes can be postponed in 1X mode, 16 refreshes in 2X mode and 32 refreshes in 4X mode. If using PHY-initiated upd - # tes, care must be taken in the setting of RFSHCTL0.refresh_burst, to ensure that tRFCmax is not violated due to a PHY-initiat - # d update occurring shortly before a refresh burst was due. In this situation, the refresh burst will be delayed until the PHY - # initiated update is complete. + # The programmed value + 1 is the number of refresh timeouts that is allow + # ed to accumulate before traffic is blocked and the refreshes are forced + # to execute. Closing pages to perform a refresh is a one-time penalty tha + # t must be paid for each group of refreshes. Therefore, performing refres + # hes in a burst reduces the per-refresh penalty of these page closings. H + # igher numbers for RFSHCTL.refresh_burst slightly increases utilization; + # lower numbers decreases the worst-case latency associated with refreshes + # . - 0 - single refresh - 1 - burst-of-2 refresh - 7 - burst-of-8 refresh + # For information on burst refresh feature refer to section 3.9 of DDR2 J + # EDEC specification - JESD79-2F.pdf. For DDR2/3, the refresh is always pe + # r-rank and not per-bank. The rank refresh can be accumulated over 8*tREF + # I cycles using the burst refresh feature. In DDR4 mode, according to Fin + # e Granularity feature, 8 refreshes can be postponed in 1X mode, 16 refre + # shes in 2X mode and 32 refreshes in 4X mode. If using PHY-initiated upda + # tes, care must be taken in the setting of RFSHCTL0.refresh_burst, to ens + # ure that tRFCmax is not violated due to a PHY-initiated update occurring + # shortly before a refresh burst was due. In this situation, the refresh + # burst will be delayed until the PHY-initiated update is complete. # PSU_DDRC_RFSHCTL0_REFRESH_BURST 0x0 - # - 1 - Per bank refresh; - 0 - All bank refresh. Per bank refresh allows traffic to flow to other banks. Per bank refresh is n - # t supported by all LPDDR2 devices but should be supported by all LPDDR3/LPDDR4 devices. Present only in designs configured to - # support LPDDR2/LPDDR3/LPDDR4 + # - 1 - Per bank refresh; - 0 - All bank refresh. Per bank refresh allows + # traffic to flow to other banks. Per bank refresh is not supported by all + # LPDDR2 devices but should be supported by all LPDDR3/LPDDR4 devices. Pr + # esent only in designs configured to support LPDDR2/LPDDR3/LPDDR4 # PSU_DDRC_RFSHCTL0_PER_BANK_REFRESH 0x0 # Refresh Control Register 0 #(OFFSET, MASK, VALUE) (0XFD070050, 0x00F1F1F4U ,0x00210000U) */ mask_write 0XFD070050 0x00F1F1F4 0x00210000 + # Register : RFSHCTL1 @ 0XFD070054

+ + # Refresh timer start for rank 1 (only present in multi-rank configuration + # s). This is useful in staggering the refreshes to multiple ranks to help + # traffic to proceed. This is explained in Refresh Controls section of ar + # chitecture chapter. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY. + # PSU_DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32 0x0 + + # Refresh timer start for rank 0 (only present in multi-rank configuration + # s). This is useful in staggering the refreshes to multiple ranks to help + # traffic to proceed. This is explained in Refresh Controls section of ar + # chitecture chapter. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY. + # PSU_DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32 0x0 + + # Refresh Control Register 1 + #(OFFSET, MASK, VALUE) (0XFD070054, 0x0FFF0FFFU ,0x00000000U) */ + mask_write 0XFD070054 0x0FFF0FFF 0x00000000 # Register : RFSHCTL3 @ 0XFD070060

- # Fine Granularity Refresh Mode - 000 - Fixed 1x (Normal mode) - 001 - Fixed 2x - 010 - Fixed 4x - 101 - Enable on the fly 2x ( - # ot supported) - 110 - Enable on the fly 4x (not supported) - Everything else - reserved Note: The on-the-fly modes is not sup - # orted in this version of the uMCTL2. Note: This must be set up while the Controller is in reset or while the Controller is in - # self-refresh mode. Changing this during normal operation is not allowed. Making this a dynamic register will be supported in - # uture version of the uMCTL2. + # Fine Granularity Refresh Mode - 000 - Fixed 1x (Normal mode) - 001 - Fix + # ed 2x - 010 - Fixed 4x - 101 - Enable on the fly 2x (not supported) - 11 + # 0 - Enable on the fly 4x (not supported) - Everything else - reserved No + # te: The on-the-fly modes is not supported in this version of the uMCTL2. + # Note: This must be set up while the Controller is in reset or while the + # Controller is in self-refresh mode. Changing this during normal operati + # on is not allowed. Making this a dynamic register will be supported in f + # uture version of the uMCTL2. # PSU_DDRC_RFSHCTL3_REFRESH_MODE 0x0 - # Toggle this signal (either from 0 to 1 or from 1 to 0) to indicate that the refresh register(s) have been updated. The value - # s automatically updated when exiting reset, so it does not need to be toggled initially. + # Toggle this signal (either from 0 to 1 or from 1 to 0) to indicate that + # the refresh register(s) have been updated. The value is automatically up + # dated when exiting reset, so it does not need to be toggled initially. # PSU_DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL 0x0 - # When '1', disable auto-refresh generated by the uMCTL2. When auto-refresh is disabled, the SoC core must generate refreshes u - # ing the registers reg_ddrc_rank0_refresh, reg_ddrc_rank1_refresh, reg_ddrc_rank2_refresh and reg_ddrc_rank3_refresh. When dis - # auto_refresh transitions from 0 to 1, any pending refreshes are immediately scheduled by the uMCTL2. If DDR4 CRC/parity retry - # is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), disable auto-refresh is not supported, and this bit must be set to '0'. - # his register field is changeable on the fly. + # When '1', disable auto-refresh generated by the uMCTL2. When auto-refres + # h is disabled, the SoC core must generate refreshes using the registers + # reg_ddrc_rank0_refresh, reg_ddrc_rank1_refresh, reg_ddrc_rank2_refresh a + # nd reg_ddrc_rank3_refresh. When dis_auto_refresh transitions from 0 to 1 + # , any pending refreshes are immediately scheduled by the uMCTL2. If DDR4 + # CRC/parity retry is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), d + # isable auto-refresh is not supported, and this bit must be set to '0'. T + # his register field is changeable on the fly. # PSU_DDRC_RFSHCTL3_DIS_AUTO_REFRESH 0x1 # Refresh Control Register 3 @@ -1500,38 +1586,51 @@ set psu_ddr_init_data { mask_write 0XFD070060 0x00000073 0x00000001 # Register : RFSHTMG @ 0XFD070064

- # tREFI: Average time interval between refreshes per rank (Specification: 7.8us for DDR2, DDR3 and DDR4. See JEDEC specificatio - # for mDDR, LPDDR2, LPDDR3 and LPDDR4). For LPDDR2/LPDDR3/LPDDR4: - if using all-bank refreshes (RFSHCTL0.per_bank_refresh = 0 - # , this register should be set to tREFIab - if using per-bank refreshes (RFSHCTL0.per_bank_refresh = 1), this register should - # e set to tREFIpb For configurations with MEMC_FREQ_RATIO=2, program this to (tREFI/2), no rounding up. In DDR4 mode, tREFI va - # ue is different depending on the refresh mode. The user should program the appropriate value from the spec based on the value - # programmed in the refresh mode register. Note that RFSHTMG.t_rfc_nom_x32 * 32 must be greater than RFSHTMG.t_rfc_min, and RFS - # TMG.t_rfc_nom_x32 must be greater than 0x1. Unit: Multiples of 32 clocks. - # PSU_DDRC_RFSHTMG_T_RFC_NOM_X32 0x82 + # tREFI: Average time interval between refreshes per rank (Specification: + # 7.8us for DDR2, DDR3 and DDR4. See JEDEC specification for mDDR, LPDDR2, + # LPDDR3 and LPDDR4). For LPDDR2/LPDDR3/LPDDR4: - if using all-bank refre + # shes (RFSHCTL0.per_bank_refresh = 0), this register should be set to tRE + # FIab - if using per-bank refreshes (RFSHCTL0.per_bank_refresh = 1), this + # register should be set to tREFIpb For configurations with MEMC_FREQ_RAT + # IO=2, program this to (tREFI/2), no rounding up. In DDR4 mode, tREFI val + # ue is different depending on the refresh mode. The user should program t + # he appropriate value from the spec based on the value programmed in the + # refresh mode register. Note that RFSHTMG.t_rfc_nom_x32 * 32 must be grea + # ter than RFSHTMG.t_rfc_min, and RFSHTMG.t_rfc_nom_x32 must be greater th + # an 0x1. Unit: Multiples of 32 clocks. + # PSU_DDRC_RFSHTMG_T_RFC_NOM_X32 0x81 - # Used only when LPDDR3 memory type is connected. Should only be changed when uMCTL2 is in reset. Specifies whether to use the - # REFBW parameter (required by some LPDDR3 devices which comply with earlier versions of the LPDDR3 JEDEC specification) or not - # - 0 - tREFBW parameter not used - 1 - tREFBW parameter used + # Used only when LPDDR3 memory type is connected. Should only be changed w + # hen uMCTL2 is in reset. Specifies whether to use the tREFBW parameter (r + # equired by some LPDDR3 devices which comply with earlier versions of the + # LPDDR3 JEDEC specification) or not: - 0 - tREFBW parameter not used - 1 + # - tREFBW parameter used # PSU_DDRC_RFSHTMG_LPDDR3_TREFBW_EN 0x1 - # tRFC (min): Minimum time from refresh to refresh or activate. For MEMC_FREQ_RATIO=1 configurations, t_rfc_min should be set t - # RoundUp(tRFCmin/tCK). For MEMC_FREQ_RATIO=2 configurations, t_rfc_min should be set to RoundUp(RoundUp(tRFCmin/tCK)/2). In L - # DDR2/LPDDR3/LPDDR4 mode: - if using all-bank refreshes, the tRFCmin value in the above equations is equal to tRFCab - if usin - # per-bank refreshes, the tRFCmin value in the above equations is equal to tRFCpb In DDR4 mode, the tRFCmin value in the above - # equations is different depending on the refresh mode (fixed 1X,2X,4X) and the device density. The user should program the app - # opriate value from the spec based on the 'refresh_mode' and the device density that is used. Unit: Clocks. + # tRFC (min): Minimum time from refresh to refresh or activate. For MEMC_F + # REQ_RATIO=1 configurations, t_rfc_min should be set to RoundUp(tRFCmin/t + # CK). For MEMC_FREQ_RATIO=2 configurations, t_rfc_min should be set to Ro + # undUp(RoundUp(tRFCmin/tCK)/2). In LPDDR2/LPDDR3/LPDDR4 mode: - if using + # all-bank refreshes, the tRFCmin value in the above equations is equal to + # tRFCab - if using per-bank refreshes, the tRFCmin value in the above eq + # uations is equal to tRFCpb In DDR4 mode, the tRFCmin value in the above + # equations is different depending on the refresh mode (fixed 1X,2X,4X) an + # d the device density. The user should program the appropriate value from + # the spec based on the 'refresh_mode' and the device density that is use + # d. Unit: Clocks. # PSU_DDRC_RFSHTMG_T_RFC_MIN 0x8b # Refresh Timing Register - #(OFFSET, MASK, VALUE) (0XFD070064, 0x0FFF83FFU ,0x0082808BU) */ - mask_write 0XFD070064 0x0FFF83FF 0x0082808B + #(OFFSET, MASK, VALUE) (0XFD070064, 0x0FFF83FFU ,0x0081808BU) */ + mask_write 0XFD070064 0x0FFF83FF 0x0081808B # Register : ECCCFG0 @ 0XFD070070

- # Disable ECC scrubs. Valid only when ECCCFG0.ecc_mode = 3'b100 and MEMC_USE_RMW is defined + # Disable ECC scrubs. Valid only when ECCCFG0.ecc_mode = 3'b100 and MEMC_U + # SE_RMW is defined # PSU_DDRC_ECCCFG0_DIS_SCRUB 0x1 - # ECC mode indicator - 000 - ECC disabled - 100 - ECC enabled - SEC/DED over 1 beat - all other settings are reserved for futur - # use + # ECC mode indicator - 000 - ECC disabled - 100 - ECC enabled - SEC/DED ov + # er 1 beat - all other settings are reserved for future use # PSU_DDRC_ECCCFG0_ECC_MODE 0x0 # ECC Configuration Register 0 @@ -1539,11 +1638,13 @@ set psu_ddr_init_data { mask_write 0XFD070070 0x00000017 0x00000010 # Register : ECCCFG1 @ 0XFD070074

- # Selects whether to poison 1 or 2 bits - if 0 -> 2-bit (uncorrectable) data poisoning, if 1 -> 1-bit (correctable) data poison - # ng, if ECCCFG1.data_poison_en=1 + # Selects whether to poison 1 or 2 bits - if 0 -> 2-bit (uncorrectable) da + # ta poisoning, if 1 -> 1-bit (correctable) data poisoning, if ECCCFG1.dat + # a_poison_en=1 # PSU_DDRC_ECCCFG1_DATA_POISON_BIT 0x0 - # Enable ECC data poisoning - introduces ECC errors on writes to address specified by the ECCPOISONADDR0/1 registers + # Enable ECC data poisoning - introduces ECC errors on writes to address s + # pecified by the ECCPOISONADDR0/1 registers # PSU_DDRC_ECCCFG1_DATA_POISON_EN 0x0 # ECC Configuration Register 1 @@ -1551,43 +1652,60 @@ set psu_ddr_init_data { mask_write 0XFD070074 0x00000003 0x00000000 # Register : CRCPARCTL1 @ 0XFD0700C4

- # The maximum number of DFI PHY clock cycles allowed from the assertion of the dfi_rddata_en signal to the assertion of each of - # the corresponding bits of the dfi_rddata_valid signal. This corresponds to the DFI timing parameter tphy_rdlat. Refer to PHY - # pecification for correct value. This value it only used for detecting read data timeout when DDR4 retry is enabled by CRCPARC - # L1.crc_parity_retry_enable=1. Maximum supported value: - 1:1 Frequency mode : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_ - # dlat < 'd114 - 1:2 Frequency mode ANDAND DFITMG0.dfi_rddata_use_sdr == 1 : CRCPARCTL1.dfi_t_phy_rdlat < 64 - 1:2 Frequency mo - # e ANDAND DFITMG0.dfi_rddata_use_sdr == 0 : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_rdlat < 'd114 Unit: DFI Clocks + # The maximum number of DFI PHY clock cycles allowed from the assertion of + # the dfi_rddata_en signal to the assertion of each of the corresponding + # bits of the dfi_rddata_valid signal. This corresponds to the DFI timing + # parameter tphy_rdlat. Refer to PHY specification for correct value. This + # value it only used for detecting read data timeout when DDR4 retry is e + # nabled by CRCPARCTL1.crc_parity_retry_enable=1. Maximum supported value: + # - 1:1 Frequency mode : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_r + # dlat < 'd114 - 1:2 Frequency mode ANDAND DFITMG0.dfi_rddata_use_sdr == 1 + # : CRCPARCTL1.dfi_t_phy_rdlat < 64 - 1:2 Frequency mode ANDAND DFITMG0.d + # fi_rddata_use_sdr == 0 : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_ + # rdlat < 'd114 Unit: DFI Clocks # PSU_DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT 0x10 - # After a Parity or CRC error is flagged on dfi_alert_n signal, the software has an option to read the mode registers in the DR - # M before the hardware begins the retry process - 1: Wait for software to read/write the mode registers before hardware begins - # the retry. After software is done with its operations, it will clear the alert interrupt register bit - 0: Hardware can begin - # the retry right away after the dfi_alert_n pulse goes away. The value on this register is valid only when retry is enabled (P - # RCTRL.crc_parity_retry_enable = 1) If this register is set to 1 and if the software doesn't clear the interrupt register afte - # handling the parity/CRC error, then the hardware will not begin the retry process and the system will hang. In the case of P - # rity/CRC error, there are two possibilities when the software doesn't reset MR5[4] to 0. - (i) If 'Persistent parity' mode re - # ister bit is NOT set: the commands sent during retry and normal operation are executed without parity checking. The value in - # he Parity error log register MPR Page 1 is valid. - (ii) If 'Persistent parity' mode register bit is SET: Parity checking is - # one for commands sent during retry and normal operation. If multiple errors occur before MR5[4] is cleared, the error log in - # PR Page 1 should be treated as 'Don't care'. + # After a Parity or CRC error is flagged on dfi_alert_n signal, the softwa + # re has an option to read the mode registers in the DRAM before the hardw + # are begins the retry process - 1: Wait for software to read/write the mo + # de registers before hardware begins the retry. After software is done wi + # th its operations, it will clear the alert interrupt register bit - 0: H + # ardware can begin the retry right away after the dfi_alert_n pulse goes + # away. The value on this register is valid only when retry is enabled (PA + # RCTRL.crc_parity_retry_enable = 1) If this register is set to 1 and if t + # he software doesn't clear the interrupt register after handling the pari + # ty/CRC error, then the hardware will not begin the retry process and the + # system will hang. In the case of Parity/CRC error, there are two possib + # ilities when the software doesn't reset MR5[4] to 0. - (i) If 'Persisten + # t parity' mode register bit is NOT set: the commands sent during retry a + # nd normal operation are executed without parity checking. The value in t + # he Parity error log register MPR Page 1 is valid. - (ii) If 'Persistent + # parity' mode register bit is SET: Parity checking is done for commands s + # ent during retry and normal operation. If multiple errors occur before M + # R5[4] is cleared, the error log in MPR Page 1 should be treated as 'Don' + # t care'. # PSU_DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW 0x1 - # - 1: Enable command retry mechanism in case of C/A Parity or CRC error - 0: Disable command retry mechanism when C/A Parity o - # CRC features are enabled. Note that retry functionality is not supported if burst chop is enabled (MSTR.burstchop = 1) and/o - # disable auto-refresh is enabled (RFSHCTL3.dis_auto_refresh = 1) + # - 1: Enable command retry mechanism in case of C/A Parity or CRC error - + # 0: Disable command retry mechanism when C/A Parity or CRC features are + # enabled. Note that retry functionality is not supported if burst chop is + # enabled (MSTR.burstchop = 1) and/or disable auto-refresh is enabled (RF + # SHCTL3.dis_auto_refresh = 1) # PSU_DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE 0x0 - # CRC Calculation setting register - 1: CRC includes DM signal - 0: CRC not includes DM signal Present only in designs configur - # d to support DDR4. + # CRC Calculation setting register - 1: CRC includes DM signal - 0: CRC no + # t includes DM signal Present only in designs configured to support DDR4. # PSU_DDRC_CRCPARCTL1_CRC_INC_DM 0x0 - # CRC enable Register - 1: Enable generation of CRC - 0: Disable generation of CRC The setting of this register should match th - # CRC mode register setting in the DRAM. + # CRC enable Register - 1: Enable generation of CRC - 0: Disable generatio + # n of CRC The setting of this register should match the CRC mode register + # setting in the DRAM. # PSU_DDRC_CRCPARCTL1_CRC_ENABLE 0x0 - # C/A Parity enable register - 1: Enable generation of C/A parity and detection of C/A parity error - 0: Disable generation of - # /A parity and disable detection of C/A parity error If RCD's parity error detection or SDRAM's parity detection is enabled, t - # is register should be 1. + # C/A Parity enable register - 1: Enable generation of C/A parity and dete + # ction of C/A parity error - 0: Disable generation of C/A parity and disa + # ble detection of C/A parity error If RCD's parity error detection or SDR + # AM's parity detection is enabled, this register should be 1. # PSU_DDRC_CRCPARCTL1_PARITY_ENABLE 0x0 # CRC Parity Control Register1 @@ -1595,35 +1713,53 @@ set psu_ddr_init_data { mask_write 0XFD0700C4 0x3F000391 0x10000200 # Register : CRCPARCTL2 @ 0XFD0700C8

- # Value from the DRAM spec indicating the maximum width of the dfi_alert_n pulse when a parity error occurs. Recommended values - # - tPAR_ALERT_PW.MAX For configurations with MEMC_FREQ_RATIO=2, program this to tPAR_ALERT_PW.MAX/2 and round up to next inte - # er value. Values of 0, 1 and 2 are illegal. This value must be greater than CRCPARCTL2.t_crc_alert_pw_max. + # Value from the DRAM spec indicating the maximum width of the dfi_alert_n + # pulse when a parity error occurs. Recommended values: - tPAR_ALERT_PW.M + # AX For configurations with MEMC_FREQ_RATIO=2, program this to tPAR_ALERT + # _PW.MAX/2 and round up to next integer value. Values of 0, 1 and 2 are i + # llegal. This value must be greater than CRCPARCTL2.t_crc_alert_pw_max. # PSU_DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX 0x40 - # Value from the DRAM spec indicating the maximum width of the dfi_alert_n pulse when a CRC error occurs. Recommended values: - - # tCRC_ALERT_PW.MAX For configurations with MEMC_FREQ_RATIO=2, program this to tCRC_ALERT_PW.MAX/2 and round up to next integer - # value. Values of 0, 1 and 2 are illegal. This value must be less than CRCPARCTL2.t_par_alert_pw_max. + # Value from the DRAM spec indicating the maximum width of the dfi_alert_n + # pulse when a CRC error occurs. Recommended values: - tCRC_ALERT_PW.MAX + # For configurations with MEMC_FREQ_RATIO=2, program this to tCRC_ALERT_PW + # .MAX/2 and round up to next integer value. Values of 0, 1 and 2 are ille + # gal. This value must be less than CRCPARCTL2.t_par_alert_pw_max. # PSU_DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX 0x5 - # Indicates the maximum duration in number of DRAM clock cycles for which a command should be held in the Command Retry FIFO be - # ore it is popped out. Every location in the Command Retry FIFO has an associated down counting timer that will use this regis - # er as the start value. The down counting starts when a command is loaded into the FIFO. The timer counts down every 4 DRAM cy - # les. When the counter reaches zero, the entry is popped from the FIFO. All the counters are frozen, if a C/A Parity or CRC er - # or occurs before the counter reaches zero. The counter is reset to 0, after all the commands in the FIFO are retried. Recomme - # ded(minimum) values: - Only C/A Parity is enabled. RoundUp((PHY Command Latency(DRAM CLK) + CAL + RDIMM delay + tPAR_ALERT_ON - # max + tPAR_UNKNOWN + PHY Alert Latency(DRAM CLK) + board delay) / 4) + 2 - Both C/A Parity and CRC is enabled/ Only CRC is en - # bled. RoundUp((PHY Command Latency(DRAM CLK) + CAL + RDIMM delay + WL + 5(BL10)+ tCRC_ALERT.max + PHY Alert Latency(DRAM CLK) - # + board delay) / 4) + 2 Note 1: All value (e.g. tPAR_ALERT_ON) should be in terms of DRAM Clock and round up Note 2: Board de - # ay(Command/Alert_n) should be considered. Note 3: Use the worst case(longer) value for PHY Latencies/Board delay Note 4: The - # ecommended values are minimum value to be set. For mode detail, See 'Calculation of FIFO Depth' section. Max value can be set - # to this register is defined below: - MEMC_BURST_LENGTH == 16 Full bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH- - # Full bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Half bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_D - # PTH-4 Half bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-6 Quarter bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CM - # _FIFO_DEPTH-8 Quarter bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-12 - MEMC_BURST_LENGTH != 16 Full bus Mode (C - # C=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-1 Full bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mo - # e (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Quarte - # bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-4 Quarter bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEP - # H-6 Values of 0, 1 and 2 are illegal. + # Indicates the maximum duration in number of DRAM clock cycles for which + # a command should be held in the Command Retry FIFO before it is popped o + # ut. Every location in the Command Retry FIFO has an associated down coun + # ting timer that will use this register as the start value. The down coun + # ting starts when a command is loaded into the FIFO. The timer counts dow + # n every 4 DRAM cycles. When the counter reaches zero, the entry is poppe + # d from the FIFO. All the counters are frozen, if a C/A Parity or CRC err + # or occurs before the counter reaches zero. The counter is reset to 0, af + # ter all the commands in the FIFO are retried. Recommended(minimum) value + # s: - Only C/A Parity is enabled. RoundUp((PHY Command Latency(DRAM CLK) + # + CAL + RDIMM delay + tPAR_ALERT_ON.max + tPAR_UNKNOWN + PHY Alert Laten + # cy(DRAM CLK) + board delay) / 4) + 2 - Both C/A Parity and CRC is enable + # d/ Only CRC is enabled. RoundUp((PHY Command Latency(DRAM CLK) + CAL + R + # DIMM delay + WL + 5(BL10)+ tCRC_ALERT.max + PHY Alert Latency(DRAM CLK) + # + board delay) / 4) + 2 Note 1: All value (e.g. tPAR_ALERT_ON) should be + # in terms of DRAM Clock and round up Note 2: Board delay(Command/Alert_n + # ) should be considered. Note 3: Use the worst case(longer) value for PHY + # Latencies/Board delay Note 4: The Recommended values are minimum value + # to be set. For mode detail, See 'Calculation of FIFO Depth' section. Max + # value can be set to this register is defined below: - MEMC_BURST_LENGTH + # == 16 Full bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 + # Full bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Half b + # us Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-4 Half bus Mod + # e (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-6 Quarter bus Mode (C + # RC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-8 Quarter bus Mode (CRC= + # ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-12 - MEMC_BURST_LENGTH != 16 + # Full bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-1 Full + # bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mod + # e (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mode (CRC + # =ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Quarter bus Mode (CRC=OFF + # ) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-4 Quarter bus Mode (CRC=ON) Ma + # x value = UMCTL2_RETRY_CMD_FIFO_DEPTH-6 Values of 0, 1 and 2 are illegal + # . # PSU_DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4 0x1f # CRC Parity Control Register2 @@ -1631,23 +1767,31 @@ set psu_ddr_init_data { mask_write 0XFD0700C8 0x01FF1F3F 0x0040051F # Register : INIT0 @ 0XFD0700D0

- # If lower bit is enabled the SDRAM initialization routine is skipped. The upper bit decides what state the controller starts u - # in when reset is removed - 00 - SDRAM Intialization routine is run after power-up - 01 - SDRAM Intialization routine is skip - # ed after power-up. Controller starts up in Normal Mode - 11 - SDRAM Intialization routine is skipped after power-up. Controll - # r starts up in Self-refresh Mode - 10 - SDRAM Intialization routine is run after power-up. Note: The only 2'b00 is supported - # or LPDDR4 in this version of the uMCTL2. + # If lower bit is enabled the SDRAM initialization routine is skipped. The + # upper bit decides what state the controller starts up in when reset is + # removed - 00 - SDRAM Intialization routine is run after power-up - 01 - + # SDRAM Intialization routine is skipped after power-up. Controller starts + # up in Normal Mode - 11 - SDRAM Intialization routine is skipped after p + # ower-up. Controller starts up in Self-refresh Mode - 10 - SDRAM Intializ + # ation routine is run after power-up. Note: The only 2'b00 is supported f + # or LPDDR4 in this version of the uMCTL2. # PSU_DDRC_INIT0_SKIP_DRAM_INIT 0x0 - # Cycles to wait after driving CKE high to start the SDRAM initialization sequence. Unit: 1024 clocks. DDR2 typically requires - # 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2/LPDDR3 typically requires this to be pr - # grammed for a delay of 200 us. LPDDR4 typically requires this to be programmed for a delay of 2 us. For configurations with M - # MC_FREQ_RATIO=2, program this to JEDEC spec value divided by 2, and round it up to next integer value. + # Cycles to wait after driving CKE high to start the SDRAM initialization + # sequence. Unit: 1024 clocks. DDR2 typically requires a 400 ns delay, req + # uiring this value to be programmed to 2 at all clock speeds. LPDDR2/LPDD + # R3 typically requires this to be programmed for a delay of 200 us. LPDDR + # 4 typically requires this to be programmed for a delay of 2 us. For conf + # igurations with MEMC_FREQ_RATIO=2, program this to JEDEC spec value divi + # ded by 2, and round it up to next integer value. # PSU_DDRC_INIT0_POST_CKE_X1024 0x2 - # Cycles to wait after reset before driving CKE high to start the SDRAM initialization sequence. Unit: 1024 clock cycles. DDR2 - # pecifications typically require this to be programmed for a delay of >= 200 us. LPDDR2/LPDDR3: tINIT1 of 100 ns (min) LPDDR4: - # tINIT3 of 2 ms (min) For configurations with MEMC_FREQ_RATIO=2, program this to JEDEC spec value divided by 2, and round it u - # to next integer value. + # Cycles to wait after reset before driving CKE high to start the SDRAM in + # itialization sequence. Unit: 1024 clock cycles. DDR2 specifications typi + # cally require this to be programmed for a delay of >= 200 us. LPDDR2/LPD + # DR3: tINIT1 of 100 ns (min) LPDDR4: tINIT3 of 2 ms (min) For configurati + # ons with MEMC_FREQ_RATIO=2, program this to JEDEC spec value divided by + # 2, and round it up to next integer value. # PSU_DDRC_INIT0_PRE_CKE_X1024 0x106 # SDRAM Initialization Register 0 @@ -1655,16 +1799,20 @@ set psu_ddr_init_data { mask_write 0XFD0700D0 0xC3FF0FFF 0x00020106 # Register : INIT1 @ 0XFD0700D4

- # Number of cycles to assert SDRAM reset signal during init sequence. This is only present for designs supporting DDR3, DDR4 or - # LPDDR4 devices. For use with a DDR PHY, this should be set to a minimum of 1 + # Number of cycles to assert SDRAM reset signal during init sequence. This + # is only present for designs supporting DDR3, DDR4 or LPDDR4 devices. Fo + # r use with a DDR PHY, this should be set to a minimum of 1 # PSU_DDRC_INIT1_DRAM_RSTN_X1024 0x2 - # Cycles to wait after completing the SDRAM initialization sequence before starting the dynamic scheduler. Unit: Counts of a gl - # bal timer that pulses every 32 clock cycles. There is no known specific requirement for this; it may be set to zero. + # Cycles to wait after completing the SDRAM initialization sequence before + # starting the dynamic scheduler. Unit: Counts of a global timer that pul + # ses every 32 clock cycles. There is no known specific requirement for th + # is; it may be set to zero. # PSU_DDRC_INIT1_FINAL_WAIT_X32 0x0 - # Wait period before driving the OCD complete command to SDRAM. Unit: Counts of a global timer that pulses every 32 clock cycle - # . There is no known specific requirement for this; it may be set to zero. + # Wait period before driving the OCD complete command to SDRAM. Unit: Coun + # ts of a global timer that pulses every 32 clock cycles. There is no know + # n specific requirement for this; it may be set to zero. # PSU_DDRC_INIT1_PRE_OCD_X32 0x0 # SDRAM Initialization Register 1 @@ -1672,11 +1820,13 @@ set psu_ddr_init_data { mask_write 0XFD0700D4 0x01FF7F0F 0x00020000 # Register : INIT2 @ 0XFD0700D8

- # Idle time after the reset command, tINIT4. Present only in designs configured to support LPDDR2. Unit: 32 clock cycles. + # Idle time after the reset command, tINIT4. Present only in designs confi + # gured to support LPDDR2. Unit: 32 clock cycles. # PSU_DDRC_INIT2_IDLE_AFTER_RESET_X32 0x23 - # Time to wait after the first CKE high, tINIT2. Present only in designs configured to support LPDDR2/LPDDR3. Unit: 1 clock cyc - # e. LPDDR2/LPDDR3 typically requires 5 x tCK delay. + # Time to wait after the first CKE high, tINIT2. Present only in designs c + # onfigured to support LPDDR2/LPDDR3. Unit: 1 clock cycle. LPDDR2/LPDDR3 t + # ypically requires 5 x tCK delay. # PSU_DDRC_INIT2_MIN_STABLE_CLOCK_X1 0x5 # SDRAM Initialization Register 2 @@ -1684,28 +1834,33 @@ set psu_ddr_init_data { mask_write 0XFD0700D8 0x0000FF0F 0x00002305 # Register : INIT3 @ 0XFD0700DC

- # DDR2: Value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The uMCTL2 sets this bit appropriately - # DDR3/DDR4: Value loaded into MR0 register. mDDR: Value to write to MR register. LPDDR2/LPDDR3/LPDDR4 - Value to write to MR1 - # register - # PSU_DDRC_INIT3_MR 0x930 + # DDR2: Value to write to MR register. Bit 8 is for DLL and the setting he + # re is ignored. The uMCTL2 sets this bit appropriately. DDR3/DDR4: Value + # loaded into MR0 register. mDDR: Value to write to MR register. LPDDR2/LP + # DDR3/LPDDR4 - Value to write to MR1 register + # PSU_DDRC_INIT3_MR 0x730 - # DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setting in this register is ignored. The uMCTL2 sets those - # bits appropriately. DDR3/DDR4: Value to write to MR1 register Set bit 7 to 0. If PHY-evaluation mode training is enabled, thi - # bit is set appropriately by the uMCTL2 during write leveling. mDDR: Value to write to EMR register. LPDDR2/LPDDR3/LPDDR4 - V - # lue to write to MR2 register + # DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setti + # ng in this register is ignored. The uMCTL2 sets those bits appropriately + # . DDR3/DDR4: Value to write to MR1 register Set bit 7 to 0. If PHY-evalu + # ation mode training is enabled, this bit is set appropriately by the uMC + # TL2 during write leveling. mDDR: Value to write to EMR register. LPDDR2/ + # LPDDR3/LPDDR4 - Value to write to MR2 register # PSU_DDRC_INIT3_EMR 0x301 # SDRAM Initialization Register 3 - #(OFFSET, MASK, VALUE) (0XFD0700DC, 0xFFFFFFFFU ,0x09300301U) */ - mask_write 0XFD0700DC 0xFFFFFFFF 0x09300301 + #(OFFSET, MASK, VALUE) (0XFD0700DC, 0xFFFFFFFFU ,0x07300301U) */ + mask_write 0XFD0700DC 0xFFFFFFFF 0x07300301 # Register : INIT4 @ 0XFD0700E0

- # DDR2: Value to write to EMR2 register. DDR3/DDR4: Value to write to MR2 register LPDDR2/LPDDR3/LPDDR4: Value to write to MR3 - # egister mDDR: Unused + # DDR2: Value to write to EMR2 register. DDR3/DDR4: Value to write to MR2 + # register LPDDR2/LPDDR3/LPDDR4: Value to write to MR3 register mDDR: Unus + # ed # PSU_DDRC_INIT4_EMR2 0x20 - # DDR2: Value to write to EMR3 register. DDR3/DDR4: Value to write to MR3 register mDDR/LPDDR2/LPDDR3: Unused LPDDR4: Value to - # rite to MR13 register + # DDR2: Value to write to EMR3 register. DDR3/DDR4: Value to write to MR3 + # register mDDR/LPDDR2/LPDDR3: Unused LPDDR4: Value to write to MR13 regis + # ter # PSU_DDRC_INIT4_EMR3 0x200 # SDRAM Initialization Register 4 @@ -1713,12 +1868,15 @@ set psu_ddr_init_data { mask_write 0XFD0700E0 0xFFFFFFFF 0x00200200 # Register : INIT5 @ 0XFD0700E4

- # ZQ initial calibration, tZQINIT. Present only in designs configured to support DDR3 or DDR4 or LPDDR2/LPDDR3. Unit: 32 clock - # ycles. DDR3 typically requires 512 clocks. DDR4 requires 1024 clocks. LPDDR2/LPDDR3 requires 1 us. + # ZQ initial calibration, tZQINIT. Present only in designs configured to s + # upport DDR3 or DDR4 or LPDDR2/LPDDR3. Unit: 32 clock cycles. DDR3 typica + # lly requires 512 clocks. DDR4 requires 1024 clocks. LPDDR2/LPDDR3 requir + # es 1 us. # PSU_DDRC_INIT5_DEV_ZQINIT_X32 0x21 - # Maximum duration of the auto initialization, tINIT5. Present only in designs configured to support LPDDR2/LPDDR3. LPDDR2/LPDD - # 3 typically requires 10 us. + # Maximum duration of the auto initialization, tINIT5. Present only in des + # igns configured to support LPDDR2/LPDDR3. LPDDR2/LPDDR3 typically requir + # es 10 us. # PSU_DDRC_INIT5_MAX_AUTO_INIT_X1024 0x4 # SDRAM Initialization Register 5 @@ -1726,10 +1884,12 @@ set psu_ddr_init_data { mask_write 0XFD0700E4 0x00FF03FF 0x00210004 # Register : INIT6 @ 0XFD0700E8

- # DDR4- Value to be loaded into SDRAM MR4 registers. Used in DDR4 designs only. + # DDR4- Value to be loaded into SDRAM MR4 registers. Used in DDR4 designs + # only. # PSU_DDRC_INIT6_MR4 0x0 - # DDR4- Value to be loaded into SDRAM MR5 registers. Used in DDR4 designs only. + # DDR4- Value to be loaded into SDRAM MR5 registers. Used in DDR4 designs + # only. # PSU_DDRC_INIT6_MR5 0x6c0 # SDRAM Initialization Register 6 @@ -1737,7 +1897,8 @@ set psu_ddr_init_data { mask_write 0XFD0700E8 0xFFFFFFFF 0x000006C0 # Register : INIT7 @ 0XFD0700EC

- # DDR4- Value to be loaded into SDRAM MR6 registers. Used in DDR4 designs only. + # DDR4- Value to be loaded into SDRAM MR6 registers. Used in DDR4 designs + # only. # PSU_DDRC_INIT7_MR6 0x819 # SDRAM Initialization Register 7 @@ -1745,50 +1906,73 @@ set psu_ddr_init_data { mask_write 0XFD0700EC 0xFFFF0000 0x08190000 # Register : DIMMCTL @ 0XFD0700F0

- # Disabling Address Mirroring for BG bits. When this is set to 1, BG0 and BG1 are NOT swapped even if Address Mirroring is enab - # ed. This will be required for DDR4 DIMMs with x16 devices. - 1 - BG0 and BG1 are NOT swapped. - 0 - BG0 and BG1 are swapped i - # address mirroring is enabled. + # Disabling Address Mirroring for BG bits. When this is set to 1, BG0 and + # BG1 are NOT swapped even if Address Mirroring is enabled. This will be r + # equired for DDR4 DIMMs with x16 devices. - 1 - BG0 and BG1 are NOT swapp + # ed. - 0 - BG0 and BG1 are swapped if address mirroring is enabled. # PSU_DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING 0x0 - # Enable for BG1 bit of MRS command. BG1 bit of the mode register address is specified as RFU (Reserved for Future Use) and mus - # be programmed to 0 during MRS. In case where DRAMs which do not have BG1 are attached and both the CA parity and the Output - # nversion are enabled, this must be set to 0, so that the calculation of CA parity will not include BG1 bit. Note: This has no - # effect on the address of any other memory accesses, or of software-driven mode register accesses. If address mirroring is ena - # led, this is applied to BG1 of even ranks and BG0 of odd ranks. - 1 - Enabled - 0 - Disabled + # Enable for BG1 bit of MRS command. BG1 bit of the mode register address + # is specified as RFU (Reserved for Future Use) and must be programmed to + # 0 during MRS. In case where DRAMs which do not have BG1 are attached and + # both the CA parity and the Output Inversion are enabled, this must be s + # et to 0, so that the calculation of CA parity will not include BG1 bit. + # Note: This has no effect on the address of any other memory accesses, or + # of software-driven mode register accesses. If address mirroring is enab + # led, this is applied to BG1 of even ranks and BG0 of odd ranks. - 1 - En + # abled - 0 - Disabled # PSU_DDRC_DIMMCTL_MRS_BG1_EN 0x1 - # Enable for A17 bit of MRS command. A17 bit of the mode register address is specified as RFU (Reserved for Future Use) and mus - # be programmed to 0 during MRS. In case where DRAMs which do not have A17 are attached and the Output Inversion are enabled, - # his must be set to 0, so that the calculation of CA parity will not include A17 bit. Note: This has no effect on the address - # f any other memory accesses, or of software-driven mode register accesses. - 1 - Enabled - 0 - Disabled + # Enable for A17 bit of MRS command. A17 bit of the mode register address + # is specified as RFU (Reserved for Future Use) and must be programmed to + # 0 during MRS. In case where DRAMs which do not have A17 are attached and + # the Output Inversion are enabled, this must be set to 0, so that the ca + # lculation of CA parity will not include A17 bit. Note: This has no effec + # t on the address of any other memory accesses, or of software-driven mod + # e register accesses. - 1 - Enabled - 0 - Disabled # PSU_DDRC_DIMMCTL_MRS_A17_EN 0x0 - # Output Inversion Enable (for DDR4 RDIMM implementations only). DDR4 RDIMM implements the Output Inversion feature by default, - # which means that the following address, bank address and bank group bits of B-side DRAMs are inverted: A3-A9, A11, A13, A17, - # A0-BA1, BG0-BG1. Setting this bit ensures that, for mode register accesses generated by the uMCTL2 during the automatic initi - # lization routine and enabling of a particular DDR4 feature, separate A-side and B-side mode register accesses are generated. - # or B-side mode register accesses, these bits are inverted within the uMCTL2 to compensate for this RDIMM inversion. Note: Thi - # has no effect on the address of any other memory accesses, or of software-driven mode register accesses. - 1 - Implement out - # ut inversion for B-side DRAMs. - 0 - Do not implement output inversion for B-side DRAMs. + # Output Inversion Enable (for DDR4 RDIMM implementations only). DDR4 RDIM + # M implements the Output Inversion feature by default, which means that t + # he following address, bank address and bank group bits of B-side DRAMs a + # re inverted: A3-A9, A11, A13, A17, BA0-BA1, BG0-BG1. Setting this bit en + # sures that, for mode register accesses generated by the uMCTL2 during th + # e automatic initialization routine and enabling of a particular DDR4 fea + # ture, separate A-side and B-side mode register accesses are generated. F + # or B-side mode register accesses, these bits are inverted within the uMC + # TL2 to compensate for this RDIMM inversion. Note: This has no effect on + # the address of any other memory accesses, or of software-driven mode reg + # ister accesses. - 1 - Implement output inversion for B-side DRAMs. - 0 - + # Do not implement output inversion for B-side DRAMs. # PSU_DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN 0x0 - # Address Mirroring Enable (for multi-rank UDIMM implementations and multi-rank DDR4 RDIMM implementations). Some UDIMMs and DD - # 4 RDIMMs implement address mirroring for odd ranks, which means that the following address, bank address and bank group bits - # re swapped: (A3, A4), (A5, A6), (A7, A8), (BA0, BA1) and also (A11, A13), (BG0, BG1) for the DDR4. Setting this bit ensures t - # at, for mode register accesses during the automatic initialization routine, these bits are swapped within the uMCTL2 to compe - # sate for this UDIMM/RDIMM swapping. In addition to the automatic initialization routine, in case of DDR4 UDIMM/RDIMM, they ar - # swapped during the automatic MRS access to enable/disable of a particular DDR4 feature. Note: This has no effect on the addr - # ss of any other memory accesses, or of software-driven mode register accesses. This is not supported for mDDR, LPDDR2, LPDDR3 - # or LPDDR4 SDRAMs. Note: In case of x16 DDR4 DIMMs, BG1 output of MRS for the odd ranks is same as BG0 because BG1 is invalid, - # hence dimm_dis_bg_mirroring register must be set to 1. - 1 - For odd ranks, implement address mirroring for MRS commands to d - # ring initialization and for any automatic DDR4 MRS commands (to be used if UDIMM/RDIMM implements address mirroring) - 0 - Do - # not implement address mirroring + # Address Mirroring Enable (for multi-rank UDIMM implementations and multi + # -rank DDR4 RDIMM implementations). Some UDIMMs and DDR4 RDIMMs implement + # address mirroring for odd ranks, which means that the following address + # , bank address and bank group bits are swapped: (A3, A4), (A5, A6), (A7, + # A8), (BA0, BA1) and also (A11, A13), (BG0, BG1) for the DDR4. Setting t + # his bit ensures that, for mode register accesses during the automatic in + # itialization routine, these bits are swapped within the uMCTL2 to compen + # sate for this UDIMM/RDIMM swapping. In addition to the automatic initial + # ization routine, in case of DDR4 UDIMM/RDIMM, they are swapped during th + # e automatic MRS access to enable/disable of a particular DDR4 feature. N + # ote: This has no effect on the address of any other memory accesses, or + # of software-driven mode register accesses. This is not supported for mDD + # R, LPDDR2, LPDDR3 or LPDDR4 SDRAMs. Note: In case of x16 DDR4 DIMMs, BG1 + # output of MRS for the odd ranks is same as BG0 because BG1 is invalid, + # hence dimm_dis_bg_mirroring register must be set to 1. - 1 - For odd ran + # ks, implement address mirroring for MRS commands to during initializatio + # n and for any automatic DDR4 MRS commands (to be used if UDIMM/RDIMM imp + # lements address mirroring) - 0 - Do not implement address mirroring # PSU_DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN 0x0 - # Staggering enable for multi-rank accesses (for multi-rank UDIMM and RDIMM implementations only). This is not supported for mD - # R, LPDDR2, LPDDR3 or LPDDR4 SDRAMs. Note: Even if this bit is set it does not take care of software driven MR commands (via M - # CTRL0/MRCTRL1), where software is responsible to send them to seperate ranks as appropriate. - 1 - (DDR4) Send MRS commands t - # each ranks seperately - 1 - (non-DDR4) Send all commands to even and odd ranks seperately - 0 - Do not stagger accesses + # Staggering enable for multi-rank accesses (for multi-rank UDIMM and RDIM + # M implementations only). This is not supported for mDDR, LPDDR2, LPDDR3 + # or LPDDR4 SDRAMs. Note: Even if this bit is set it does not take care of + # software driven MR commands (via MRCTRL0/MRCTRL1), where software is re + # sponsible to send them to seperate ranks as appropriate. - 1 - (DDR4) Se + # nd MRS commands to each ranks seperately - 1 - (non-DDR4) Send all comma + # nds to even and odd ranks seperately - 0 - Do not stagger accesses # PSU_DDRC_DIMMCTL_DIMM_STAGGER_CS_EN 0x0 # DIMM Control Register @@ -1796,38 +1980,56 @@ set psu_ddr_init_data { mask_write 0XFD0700F0 0x0000003F 0x00000010 # Register : RANKCTL @ 0XFD0700F4

- # Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecuti - # e writes to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This value should c - # nsider both PHY requirement and ODT requirement. - PHY requirement: tphy_wrcsgap + 1 (see PHY databook for value of tphy_wrcs - # ap) If CRC feature is enabled, should be increased by 1. If write preamble is set to 2tCK(DDR4/LPDDR4 only), should be increa - # ed by 1. If write postamble is set to 1.5tCK(LPDDR4 only), should be increased by 1. - ODT requirement: The value programmed - # n this register takes care of the ODT switch off timing requirement when switching ranks during writes. For LPDDR4, the requi - # ement is ODTLoff - ODTLon - BL/2 + 1 For configurations with MEMC_FREQ_RATIO=1, program this to the larger of PHY requirement - # or ODT requirement. For configurations with MEMC_FREQ_RATIO=2, program this to the larger value divided by two and round it u - # to the next integer. + # Only present for multi-rank configurations. Indicates the number of cloc + # ks of gap in data responses when performing consecutive writes to differ + # ent ranks. This is used to switch the delays in the PHY to match the ran + # k requirements. This value should consider both PHY requirement and ODT + # requirement. - PHY requirement: tphy_wrcsgap + 1 (see PHY databook for v + # alue of tphy_wrcsgap) If CRC feature is enabled, should be increased by + # 1. If write preamble is set to 2tCK(DDR4/LPDDR4 only), should be increas + # ed by 1. If write postamble is set to 1.5tCK(LPDDR4 only), should be inc + # reased by 1. - ODT requirement: The value programmed in this register ta + # kes care of the ODT switch off timing requirement when switching ranks d + # uring writes. For LPDDR4, the requirement is ODTLoff - ODTLon - BL/2 + 1 + # For configurations with MEMC_FREQ_RATIO=1, program this to the larger o + # f PHY requirement or ODT requirement. For configurations with MEMC_FREQ_ + # RATIO=2, program this to the larger value divided by two and round it up + # to the next integer. # PSU_DDRC_RANKCTL_DIFF_RANK_WR_GAP 0x6 - # Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecuti - # e reads to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This value should co - # sider both PHY requirement and ODT requirement. - PHY requirement: tphy_rdcsgap + 1 (see PHY databook for value of tphy_rdcsg - # p) If read preamble is set to 2tCK(DDR4/LPDDR4 only), should be increased by 1. If read postamble is set to 1.5tCK(LPDDR4 onl - # ), should be increased by 1. - ODT requirement: The value programmed in this register takes care of the ODT switch off timing - # requirement when switching ranks during reads. For configurations with MEMC_FREQ_RATIO=1, program this to the larger of PHY r - # quirement or ODT requirement. For configurations with MEMC_FREQ_RATIO=2, program this to the larger value divided by two and - # ound it up to the next integer. + # Only present for multi-rank configurations. Indicates the number of cloc + # ks of gap in data responses when performing consecutive reads to differe + # nt ranks. This is used to switch the delays in the PHY to match the rank + # requirements. This value should consider both PHY requirement and ODT r + # equirement. - PHY requirement: tphy_rdcsgap + 1 (see PHY databook for va + # lue of tphy_rdcsgap) If read preamble is set to 2tCK(DDR4/LPDDR4 only), + # should be increased by 1. If read postamble is set to 1.5tCK(LPDDR4 only + # ), should be increased by 1. - ODT requirement: The value programmed in + # this register takes care of the ODT switch off timing requirement when s + # witching ranks during reads. For configurations with MEMC_FREQ_RATIO=1, + # program this to the larger of PHY requirement or ODT requirement. For co + # nfigurations with MEMC_FREQ_RATIO=2, program this to the larger value di + # vided by two and round it up to the next integer. # PSU_DDRC_RANKCTL_DIFF_RANK_RD_GAP 0x6 - # Only present for multi-rank configurations. Background: Reads to the same rank can be performed back-to-back. Reads to differ - # nt ranks require additional gap dictated by the register RANKCTL.diff_rank_rd_gap. This is to avoid possible data bus content - # on as well as to give PHY enough time to switch the delay when changing ranks. The uMCTL2 arbitrates for bus access on a cycl - # -by-cycle basis; therefore after a read is scheduled, there are few clock cycles (determined by the value on RANKCTL.diff_ran - # _rd_gap register) in which only reads from the same rank are eligible to be scheduled. This prevents reads from other ranks f - # om having fair access to the data bus. This parameter represents the maximum number of reads that can be scheduled consecutiv - # ly to the same rank. After this number is reached, a delay equal to RANKCTL.diff_rank_rd_gap is inserted by the scheduler to - # llow all ranks a fair opportunity to be scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fair - # ess. This feature can be DISABLED by setting this register to 0. When set to 0, the Controller will stay on the same rank as - # ong as commands are available for it. Minimum programmable value is 0 (feature disabled) and maximum programmable value is 0x - # . FOR PERFORMANCE ONLY. + # Only present for multi-rank configurations. Background: Reads to the sam + # e rank can be performed back-to-back. Reads to different ranks require a + # dditional gap dictated by the register RANKCTL.diff_rank_rd_gap. This is + # to avoid possible data bus contention as well as to give PHY enough tim + # e to switch the delay when changing ranks. The uMCTL2 arbitrates for bus + # access on a cycle-by-cycle basis; therefore after a read is scheduled, + # there are few clock cycles (determined by the value on RANKCTL.diff_rank + # _rd_gap register) in which only reads from the same rank are eligible to + # be scheduled. This prevents reads from other ranks from having fair acc + # ess to the data bus. This parameter represents the maximum number of rea + # ds that can be scheduled consecutively to the same rank. After this numb + # er is reached, a delay equal to RANKCTL.diff_rank_rd_gap is inserted by + # the scheduler to allow all ranks a fair opportunity to be scheduled. Hig + # her numbers increase bandwidth utilization, lower numbers increase fairn + # ess. This feature can be DISABLED by setting this register to 0. When se + # t to 0, the Controller will stay on the same rank as long as commands ar + # e available for it. Minimum programmable value is 0 (feature disabled) a + # nd maximum programmable value is 0xF. FOR PERFORMANCE ONLY. # PSU_DDRC_RANKCTL_MAX_RANK_RD 0xf # Rank Control Register @@ -1835,110 +2037,155 @@ set psu_ddr_init_data { mask_write 0XFD0700F4 0x00000FFF 0x0000066F # Register : DRAMTMG0 @ 0XFD070100

- # Minimum time between write and precharge to same bank. Unit: Clocks Specifications: WL + BL/2 + tWR = approximately 8 cycles - # 15 ns = 14 clocks @400MHz and less for lower frequencies where: - WL = write latency - BL = burst length. This must match th - # value programmed in the BL bit of the mode register to the SDRAM. BST (burst terminate) is not supported at present. - tWR = - # Write recovery time. This comes directly from the SDRAM specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 for this - # arameter. For configurations with MEMC_FREQ_RATIO=2, 1T mode, divide the above value by 2. No rounding up. For configurations - # with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, divide the above value by 2 and round it up to the next integer value. + # Minimum time between write and precharge to same bank. Unit: Clocks Spec + # ifications: WL + BL/2 + tWR = approximately 8 cycles + 15 ns = 14 clocks + # @400MHz and less for lower frequencies where: - WL = write latency - BL + # = burst length. This must match the value programmed in the BL bit of t + # he mode register to the SDRAM. BST (burst terminate) is not supported at + # present. - tWR = Write recovery time. This comes directly from the SDRA + # M specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 for this p + # arameter. For configurations with MEMC_FREQ_RATIO=2, 1T mode, divide the + # above value by 2. No rounding up. For configurations with MEMC_FREQ_RAT + # IO=2, 2T mode or LPDDR4 mode, divide the above value by 2 and round it u + # p to the next integer value. # PSU_DDRC_DRAMTMG0_WR2PRE 0x11 - # tFAW Valid only when 8 or more banks(or banks x bank groups) are present. In 8-bank design, at most 4 banks must be activated - # in a rolling window of tFAW cycles. For configurations with MEMC_FREQ_RATIO=2, program this to (tFAW/2) and round up to next - # nteger value. In a 4-bank design, set this register to 0x1 independent of the MEMC_FREQ_RATIO configuration. Unit: Clocks - # PSU_DDRC_DRAMTMG0_T_FAW 0xc + # tFAW Valid only when 8 or more banks(or banks x bank groups) are present + # . In 8-bank design, at most 4 banks must be activated in a rolling windo + # w of tFAW cycles. For configurations with MEMC_FREQ_RATIO=2, program thi + # s to (tFAW/2) and round up to next integer value. In a 4-bank design, se + # t this register to 0x1 independent of the MEMC_FREQ_RATIO configuration. + # Unit: Clocks + # PSU_DDRC_DRAMTMG0_T_FAW 0x10 - # tRAS(max): Maximum time between activate and precharge to same bank. This is the maximum time that a page can be kept open Mi - # imum value of this register is 1. Zero is invalid. For configurations with MEMC_FREQ_RATIO=2, program this to (tRAS(max)-1)/2 - # No rounding up. Unit: Multiples of 1024 clocks. + # tRAS(max): Maximum time between activate and precharge to same bank. Thi + # s is the maximum time that a page can be kept open Minimum value of this + # register is 1. Zero is invalid. For configurations with MEMC_FREQ_RATIO + # =2, program this to (tRAS(max)-1)/2. No rounding up. Unit: Multiples of + # 1024 clocks. # PSU_DDRC_DRAMTMG0_T_RAS_MAX 0x24 - # tRAS(min): Minimum time between activate and precharge to the same bank. For configurations with MEMC_FREQ_RATIO=2, 1T mode, - # rogram this to tRAS(min)/2. No rounding up. For configurations with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, program this t - # (tRAS(min)/2) and round it up to the next integer value. Unit: Clocks + # tRAS(min): Minimum time between activate and precharge to the same bank. + # For configurations with MEMC_FREQ_RATIO=2, 1T mode, program this to tRA + # S(min)/2. No rounding up. For configurations with MEMC_FREQ_RATIO=2, 2T + # mode or LPDDR4 mode, program this to (tRAS(min)/2) and round it up to th + # e next integer value. Unit: Clocks # PSU_DDRC_DRAMTMG0_T_RAS_MIN 0x12 # SDRAM Timing Register 0 - #(OFFSET, MASK, VALUE) (0XFD070100, 0x7F3F7F3FU ,0x110C2412U) */ - mask_write 0XFD070100 0x7F3F7F3F 0x110C2412 + #(OFFSET, MASK, VALUE) (0XFD070100, 0x7F3F7F3FU ,0x11102412U) */ + mask_write 0XFD070100 0x7F3F7F3F 0x11102412 # Register : DRAMTMG1 @ 0XFD070104

- # tXP: Minimum time after power-down exit to any operation. For DDR3, this should be programmed to tXPDLL if slow powerdown exi - # is selected in MR0[12]. If C/A parity for DDR4 is used, set to (tXP+PL) instead. For configurations with MEMC_FREQ_RATIO=2, - # rogram this to (tXP/2) and round it up to the next integer value. Units: Clocks + # tXP: Minimum time after power-down exit to any operation. For DDR3, this + # should be programmed to tXPDLL if slow powerdown exit is selected in MR + # 0[12]. If C/A parity for DDR4 is used, set to (tXP+PL) instead. For conf + # igurations with MEMC_FREQ_RATIO=2, program this to (tXP/2) and round it + # up to the next integer value. Units: Clocks # PSU_DDRC_DRAMTMG1_T_XP 0x4 - # tRTP: Minimum time from read to precharge of same bank. - DDR2: tAL + BL/2 + max(tRTP, 2) - 2 - DDR3: tAL + max (tRTP, 4) - D - # R4: Max of following two equations: tAL + max (tRTP, 4) or, RL + BL/2 - tRP. - mDDR: BL/2 - LPDDR2: Depends on if it's LPDDR2 - # S2 or LPDDR2-S4: LPDDR2-S2: BL/2 + tRTP - 1. LPDDR2-S4: BL/2 + max(tRTP,2) - 2. - LPDDR3: BL/2 + max(tRTP,4) - 4 - LPDDR4: BL - # 2 + max(tRTP,8) - 8 For configurations with MEMC_FREQ_RATIO=2, 1T mode, divide the above value by 2. No rounding up. For conf - # gurations with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, divide the above value by 2 and round it up to the next integer val - # e. Unit: Clocks. + # tRTP: Minimum time from read to precharge of same bank. - DDR2: tAL + BL + # /2 + max(tRTP, 2) - 2 - DDR3: tAL + max (tRTP, 4) - DDR4: Max of followi + # ng two equations: tAL + max (tRTP, 4) or, RL + BL/2 - tRP. - mDDR: BL/2 + # - LPDDR2: Depends on if it's LPDDR2-S2 or LPDDR2-S4: LPDDR2-S2: BL/2 + t + # RTP - 1. LPDDR2-S4: BL/2 + max(tRTP,2) - 2. - LPDDR3: BL/2 + max(tRTP,4) + # - 4 - LPDDR4: BL/2 + max(tRTP,8) - 8 For configurations with MEMC_FREQ_ + # RATIO=2, 1T mode, divide the above value by 2. No rounding up. For confi + # gurations with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, divide the abo + # ve value by 2 and round it up to the next integer value. Unit: Clocks. # PSU_DDRC_DRAMTMG1_RD2PRE 0x4 - # tRC: Minimum time between activates to same bank. For configurations with MEMC_FREQ_RATIO=2, program this to (tRC/2) and roun - # up to next integer value. Unit: Clocks. - # PSU_DDRC_DRAMTMG1_T_RC 0x19 + # tRC: Minimum time between activates to same bank. For configurations wit + # h MEMC_FREQ_RATIO=2, program this to (tRC/2) and round up to next intege + # r value. Unit: Clocks. + # PSU_DDRC_DRAMTMG1_T_RC 0x1a # SDRAM Timing Register 1 - #(OFFSET, MASK, VALUE) (0XFD070104, 0x001F1F7FU ,0x00040419U) */ - mask_write 0XFD070104 0x001F1F7F 0x00040419 + #(OFFSET, MASK, VALUE) (0XFD070104, 0x001F1F7FU ,0x0004041AU) */ + mask_write 0XFD070104 0x001F1F7F 0x0004041A # Register : DRAMTMG2 @ 0XFD070108

- # Set to WL Time from write command to write data on SDRAM interface. This must be set to WL. For mDDR, it should normally be s - # t to 1. Note that, depending on the PHY, if using RDIMM, it may be necessary to use a value of WL + 1 to compensate for the e - # tra cycle of latency through the RDIMM For configurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above - # equation by 2, and round it up to next integer. This register field is not required for DDR2 and DDR3 (except if MEMC_TRAININ - # is set), as the DFI read and write latencies defined in DFITMG0 and DFITMG1 are sufficient for those protocols Unit: clocks + # Set to WL Time from write command to write data on SDRAM interface. This + # must be set to WL. For mDDR, it should normally be set to 1. Note that, + # depending on the PHY, if using RDIMM, it may be necessary to use a valu + # e of WL + 1 to compensate for the extra cycle of latency through the RDI + # MM For configurations with MEMC_FREQ_RATIO=2, divide the value calculate + # d using the above equation by 2, and round it up to next integer. This r + # egister field is not required for DDR2 and DDR3 (except if MEMC_TRAINING + # is set), as the DFI read and write latencies defined in DFITMG0 and DFI + # TMG1 are sufficient for those protocols Unit: clocks # PSU_DDRC_DRAMTMG2_WRITE_LATENCY 0x7 - # Set to RL Time from read command to read data on SDRAM interface. This must be set to RL. Note that, depending on the PHY, if - # using RDIMM, it mat be necessary to use a value of RL + 1 to compensate for the extra cycle of latency through the RDIMM For - # onfigurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next inte - # er. This register field is not required for DDR2 and DDR3 (except if MEMC_TRAINING is set), as the DFI read and write latenci - # s defined in DFITMG0 and DFITMG1 are sufficient for those protocols Unit: clocks + # Set to RL Time from read command to read data on SDRAM interface. This m + # ust be set to RL. Note that, depending on the PHY, if using RDIMM, it ma + # t be necessary to use a value of RL + 1 to compensate for the extra cycl + # e of latency through the RDIMM For configurations with MEMC_FREQ_RATIO=2 + # , divide the value calculated using the above equation by 2, and round i + # t up to next integer. This register field is not required for DDR2 and D + # DR3 (except if MEMC_TRAINING is set), as the DFI read and write latencie + # s defined in DFITMG0 and DFITMG1 are sufficient for those protocols Unit + # : clocks # PSU_DDRC_DRAMTMG2_READ_LATENCY 0x8 - # DDR2/3/mDDR: RL + BL/2 + 2 - WL DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL LPDDR2/LPDDR3: RL + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL - # PDDR4(DQ ODT is Disabled): RL + BL/2 + RU(tDQSCKmax/tCK) + WR_PREAMBLE + RD_POSTAMBLE - WL LPDDR4(DQ ODT is Enabled) : RL + B - # /2 + RU(tDQSCKmax/tCK) + RD_POSTAMBLE - ODTLon - RU(tODTon(min)/tCK) Minimum time from read command to write command. Include - # time for bus turnaround and all per-bank, per-rank, and global constraints. Unit: Clocks. Where: - WL = write latency - BL = - # urst length. This must match the value programmed in the BL bit of the mode register to the SDRAM - RL = read latency = CAS l - # tency - WR_PREAMBLE = write preamble. This is unique to DDR4 and LPDDR4. - RD_POSTAMBLE = read postamble. This is unique to L - # DDR4. For LPDDR2/LPDDR3/LPDDR4, if derating is enabled (DERATEEN.derate_enable=1), derated tDQSCKmax should be used. For conf - # gurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next integer. + # DDR2/3/mDDR: RL + BL/2 + 2 - WL DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL L + # PDDR2/LPDDR3: RL + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL LPDDR4(DQ ODT is Di + # sabled): RL + BL/2 + RU(tDQSCKmax/tCK) + WR_PREAMBLE + RD_POSTAMBLE - WL + # LPDDR4(DQ ODT is Enabled) : RL + BL/2 + RU(tDQSCKmax/tCK) + RD_POSTAMBL + # E - ODTLon - RU(tODTon(min)/tCK) Minimum time from read command to write + # command. Include time for bus turnaround and all per-bank, per-rank, an + # d global constraints. Unit: Clocks. Where: - WL = write latency - BL = b + # urst length. This must match the value programmed in the BL bit of the m + # ode register to the SDRAM - RL = read latency = CAS latency - WR_PREAMBL + # E = write preamble. This is unique to DDR4 and LPDDR4. - RD_POSTAMBLE = + # read postamble. This is unique to LPDDR4. For LPDDR2/LPDDR3/LPDDR4, if d + # erating is enabled (DERATEEN.derate_enable=1), derated tDQSCKmax should + # be used. For configurations with MEMC_FREQ_RATIO=2, divide the value cal + # culated using the above equation by 2, and round it up to next integer. # PSU_DDRC_DRAMTMG2_RD2WR 0x6 - # DDR4: CWL + PL + BL/2 + tWTR_L Others: CWL + BL/2 + tWTR In DDR4, minimum time from write command to read command for same ba - # k group. In others, minimum time from write command to read command. Includes time for bus turnaround, recovery times, and al - # per-bank, per-rank, and global constraints. Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity latency - BL = burs - # length. This must match the value programmed in the BL bit of the mode register to the SDRAM - tWTR_L = internal write to re - # d command delay for same bank group. This comes directly from the SDRAM specification. - tWTR = internal write to read comman - # delay. This comes directly from the SDRAM specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 operation. For configu - # ations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next integer. - # PSU_DDRC_DRAMTMG2_WR2RD 0xe + # DDR4: CWL + PL + BL/2 + tWTR_L Others: CWL + BL/2 + tWTR In DDR4, minimu + # m time from write command to read command for same bank group. In others + # , minimum time from write command to read command. Includes time for bus + # turnaround, recovery times, and all per-bank, per-rank, and global cons + # traints. Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity la + # tency - BL = burst length. This must match the value programmed in the B + # L bit of the mode register to the SDRAM - tWTR_L = internal write to rea + # d command delay for same bank group. This comes directly from the SDRAM + # specification. - tWTR = internal write to read command delay. This comes + # directly from the SDRAM specification. Add one extra cycle for LPDDR2/L + # PDDR3/LPDDR4 operation. For configurations with MEMC_FREQ_RATIO=2, divid + # e the value calculated using the above equation by 2, and round it up to + # next integer. + # PSU_DDRC_DRAMTMG2_WR2RD 0xd # SDRAM Timing Register 2 - #(OFFSET, MASK, VALUE) (0XFD070108, 0x3F3F3F3FU ,0x0708060EU) */ - mask_write 0XFD070108 0x3F3F3F3F 0x0708060E + #(OFFSET, MASK, VALUE) (0XFD070108, 0x3F3F3F3FU ,0x0708060DU) */ + mask_write 0XFD070108 0x3F3F3F3F 0x0708060D # Register : DRAMTMG3 @ 0XFD07010C

- # Time to wait after a mode register write or read (MRW or MRR). Present only in designs configured to support LPDDR2, LPDDR3 o - # LPDDR4. LPDDR2 typically requires value of 5. LPDDR3 typically requires value of 10. LPDDR4: Set this to the larger of tMRW - # nd tMRWCKEL. For LPDDR2, this register is used for the time from a MRW/MRR to all other commands. For LDPDR3, this register i - # used for the time from a MRW/MRR to a MRW/MRR. + # Time to wait after a mode register write or read (MRW or MRR). Present o + # nly in designs configured to support LPDDR2, LPDDR3 or LPDDR4. LPDDR2 ty + # pically requires value of 5. LPDDR3 typically requires value of 10. LPDD + # R4: Set this to the larger of tMRW and tMRWCKEL. For LPDDR2, this regist + # er is used for the time from a MRW/MRR to all other commands. For LDPDR3 + # , this register is used for the time from a MRW/MRR to a MRW/MRR. # PSU_DDRC_DRAMTMG3_T_MRW 0x5 - # tMRD: Cycles to wait after a mode register write or read. Depending on the connected SDRAM, tMRD represents: DDR2/mDDR: Time - # rom MRS to any command DDR3/4: Time from MRS to MRS command LPDDR2: not used LPDDR3/4: Time from MRS to non-MRS command For c - # nfigurations with MEMC_FREQ_RATIO=2, program this to (tMRD/2) and round it up to the next integer value. If C/A parity for DD - # 4 is used, set to tMRD_PAR(tMOD+PL) instead. + # tMRD: Cycles to wait after a mode register write or read. Depending on t + # he connected SDRAM, tMRD represents: DDR2/mDDR: Time from MRS to any com + # mand DDR3/4: Time from MRS to MRS command LPDDR2: not used LPDDR3/4: Tim + # e from MRS to non-MRS command For configurations with MEMC_FREQ_RATIO=2, + # program this to (tMRD/2) and round it up to the next integer value. If + # C/A parity for DDR4 is used, set to tMRD_PAR(tMOD+PL) instead. # PSU_DDRC_DRAMTMG3_T_MRD 0x4 - # tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode command and following non-load mode command. If C/A pari - # y for DDR4 is used, set to tMOD_PAR(tMOD+PL) instead. Set to tMOD if MEMC_FREQ_RATIO=1, or tMOD/2 (rounded up to next integer - # if MEMC_FREQ_RATIO=2. Note that if using RDIMM, depending on the PHY, it may be necessary to use a value of tMOD + 1 or (tMO - # + 1)/2 to compensate for the extra cycle of latency applied to mode register writes by the RDIMM chip. + # tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode com + # mand and following non-load mode command. If C/A parity for DDR4 is used + # , set to tMOD_PAR(tMOD+PL) instead. Set to tMOD if MEMC_FREQ_RATIO=1, or + # tMOD/2 (rounded up to next integer) if MEMC_FREQ_RATIO=2. Note that if + # using RDIMM, depending on the PHY, it may be necessary to use a value of + # tMOD + 1 or (tMOD + 1)/2 to compensate for the extra cycle of latency a + # pplied to mode register writes by the RDIMM chip. # PSU_DDRC_DRAMTMG3_T_MOD 0xc # SDRAM Timing Register 3 @@ -1946,24 +2193,32 @@ set psu_ddr_init_data { mask_write 0XFD07010C 0x3FF3F3FF 0x0050400C # Register : DRAMTMG4 @ 0XFD070110

- # tRCD - tAL: Minimum time from activate to read or write command to same bank. For configurations with MEMC_FREQ_RATIO=2, prog - # am this to ((tRCD - tAL)/2) and round it up to the next integer value. Minimum value allowed for this register is 1, which im - # lies minimum (tRCD - tAL) value to be 2 in configurations with MEMC_FREQ_RATIO=2. Unit: Clocks. + # tRCD - tAL: Minimum time from activate to read or write command to same + # bank. For configurations with MEMC_FREQ_RATIO=2, program this to ((tRCD + # - tAL)/2) and round it up to the next integer value. Minimum value allow + # ed for this register is 1, which implies minimum (tRCD - tAL) value to b + # e 2 in configurations with MEMC_FREQ_RATIO=2. Unit: Clocks. # PSU_DDRC_DRAMTMG4_T_RCD 0x8 - # DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank group. Others: tCCD: This is the minimum - # time between two reads or two writes. For configurations with MEMC_FREQ_RATIO=2, program this to (tCCD_L/2 or tCCD/2) and rou - # d it up to the next integer value. Unit: clocks. + # DDR4: tCCD_L: This is the minimum time between two reads or two writes f + # or same bank group. Others: tCCD: This is the minimum time between two r + # eads or two writes. For configurations with MEMC_FREQ_RATIO=2, program t + # his to (tCCD_L/2 or tCCD/2) and round it up to the next integer value. U + # nit: clocks. # PSU_DDRC_DRAMTMG4_T_CCD 0x3 - # DDR4: tRRD_L: Minimum time between activates from bank 'a' to bank 'b' for same bank group. Others: tRRD: Minimum time betwee - # activates from bank 'a' to bank 'b'For configurations with MEMC_FREQ_RATIO=2, program this to (tRRD_L/2 or tRRD/2) and round - # it up to the next integer value. Unit: Clocks. + # DDR4: tRRD_L: Minimum time between activates from bank 'a' to bank 'b' f + # or same bank group. Others: tRRD: Minimum time between activates from ba + # nk 'a' to bank 'b'For configurations with MEMC_FREQ_RATIO=2, program thi + # s to (tRRD_L/2 or tRRD/2) and round it up to the next integer value. Uni + # t: Clocks. # PSU_DDRC_DRAMTMG4_T_RRD 0x3 - # tRP: Minimum time from precharge to activate of same bank. For MEMC_FREQ_RATIO=1 configurations, t_rp should be set to RoundU - # (tRP/tCK). For MEMC_FREQ_RATIO=2 configurations, t_rp should be set to RoundDown(RoundUp(tRP/tCK)/2) + 1. For MEMC_FREQ_RATIO - # 2 configurations in LPDDR4, t_rp should be set to RoundUp(RoundUp(tRP/tCK)/2). Unit: Clocks. + # tRP: Minimum time from precharge to activate of same bank. For MEMC_FREQ + # _RATIO=1 configurations, t_rp should be set to RoundUp(tRP/tCK). For MEM + # C_FREQ_RATIO=2 configurations, t_rp should be set to RoundDown(RoundUp(t + # RP/tCK)/2) + 1. For MEMC_FREQ_RATIO=2 configurations in LPDDR4, t_rp sho + # uld be set to RoundUp(RoundUp(tRP/tCK)/2). Unit: Clocks. # PSU_DDRC_DRAMTMG4_T_RP 0x9 # SDRAM Timing Register 4 @@ -1971,28 +2226,36 @@ set psu_ddr_init_data { mask_write 0XFD070110 0x1F0F0F1F 0x08030309 # Register : DRAMTMG5 @ 0XFD070114

- # This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stab - # e time before SRX. Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEH - DDR2: 1 - DDR3: tCKSRX - DDR4: - # tCKSRX For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it up to next in - # eger. + # This is the time before Self Refresh Exit that CK is maintained as a val + # id clock before issuing SRX. Specifies the clock stable time before SRX. + # Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCK + # EH - DDR2: 1 - DDR3: tCKSRX - DDR4: tCKSRX For configurations with MEMC_ + # FREQ_RATIO=2, program this to recommended value divided by two and round + # it up to next integer. # PSU_DDRC_DRAMTMG5_T_CKSRX 0x6 - # This is the time after Self Refresh Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay afte - # SRE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL - DDR2: 1 - DDR3: max (10 ns, 5 tCK) - DDR4: - # ax (10 ns, 5 tCK) For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it up - # to next integer. + # This is the time after Self Refresh Down Entry that CK is maintained as + # a valid clock. Specifies the clock disable delay after SRE. Recommended + # settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL - DDR2: 1 + # - DDR3: max (10 ns, 5 tCK) - DDR4: max (10 ns, 5 tCK) For configurations + # with MEMC_FREQ_RATIO=2, program this to recommended value divided by tw + # o and round it up to next integer. # PSU_DDRC_DRAMTMG5_T_CKSRE 0x6 - # Minimum CKE low width for Self refresh or Self refresh power down entry to exit timing in memory clock cycles. Recommended se - # tings: - mDDR: tRFC - LPDDR2: tCKESR - LPDDR3: tCKESR - LPDDR4: max(tCKELPD, tSR) - DDR2: tCKE - DDR3: tCKE + 1 - DDR4: tCKE - # 1 For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it up to next intege - # . + # Minimum CKE low width for Self refresh or Self refresh power down entry + # to exit timing in memory clock cycles. Recommended settings: - mDDR: tRF + # C - LPDDR2: tCKESR - LPDDR3: tCKESR - LPDDR4: max(tCKELPD, tSR) - DDR2: + # tCKE - DDR3: tCKE + 1 - DDR4: tCKE + 1 For configurations with MEMC_FREQ + # _RATIO=2, program this to recommended value divided by two and round it + # up to next integer. # PSU_DDRC_DRAMTMG5_T_CKESR 0x4 - # Minimum number of cycles of CKE HIGH/LOW during power-down and self refresh. - LPDDR2/LPDDR3 mode: Set this to the larger of - # CKE or tCKESR - LPDDR4 mode: Set this to the larger of tCKE, tCKELPD or tSR. - Non-LPDDR2/non-LPDDR3/non-LPDDR4 designs: Set - # his to tCKE value. For configurations with MEMC_FREQ_RATIO=2, program this to (value described above)/2 and round it up to th - # next integer value. Unit: Clocks. + # Minimum number of cycles of CKE HIGH/LOW during power-down and self refr + # esh. - LPDDR2/LPDDR3 mode: Set this to the larger of tCKE or tCKESR - LP + # DDR4 mode: Set this to the larger of tCKE, tCKELPD or tSR. - Non-LPDDR2/ + # non-LPDDR3/non-LPDDR4 designs: Set this to tCKE value. For configuration + # s with MEMC_FREQ_RATIO=2, program this to (value described above)/2 and + # round it up to the next integer value. Unit: Clocks. # PSU_DDRC_DRAMTMG5_T_CKE 0x3 # SDRAM Timing Register 5 @@ -2000,22 +2263,29 @@ set psu_ddr_init_data { mask_write 0XFD070114 0x0F0F3F1F 0x06060403 # Register : DRAMTMG6 @ 0XFD070118

- # This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after - # PDE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 For configurations with MEMC_FREQ_RATIO=2, program this to recom - # ended value divided by two and round it up to next integer. This is only present for designs supporting mDDR or LPDDR2/LPDDR3 - # devices. + # This is the time after Deep Power Down Entry that CK is maintained as a + # valid clock. Specifies the clock disable delay after DPDE. Recommended s + # ettings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 For configurations with MEMC_ + # FREQ_RATIO=2, program this to recommended value divided by two and round + # it up to next integer. This is only present for designs supporting mDDR + # or LPDDR2/LPDDR3 devices. # PSU_DDRC_DRAMTMG6_T_CKDPDE 0x1 - # This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock - # table time before DPDX. Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 For configurations with MEMC_FREQ_RATIO=2, pr - # gram this to recommended value divided by two and round it up to next integer. This is only present for designs supporting mD - # R or LPDDR2 devices. + # This is the time before Deep Power Down Exit that CK is maintained as a + # valid clock before issuing DPDX. Specifies the clock stable time before + # DPDX. Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 For config + # urations with MEMC_FREQ_RATIO=2, program this to recommended value divid + # ed by two and round it up to next integer. This is only present for desi + # gns supporting mDDR or LPDDR2 devices. # PSU_DDRC_DRAMTMG6_T_CKDPDX 0x1 - # This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing Clock Stop Exit. Specifies the - # lock stable time before next command after Clock Stop Exit. Recommended settings: - mDDR: 1 - LPDDR2: tXP + 2 - LPDDR3: tXP + - # 2 - LPDDR4: tXP + 2 For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it - # p to next integer. This is only present for designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices. + # This is the time before Clock Stop Exit that CK is maintained as a valid + # clock before issuing Clock Stop Exit. Specifies the clock stable time b + # efore next command after Clock Stop Exit. Recommended settings: - mDDR: + # 1 - LPDDR2: tXP + 2 - LPDDR3: tXP + 2 - LPDDR4: tXP + 2 For configuratio + # ns with MEMC_FREQ_RATIO=2, program this to recommended value divided by + # two and round it up to next integer. This is only present for designs su + # pporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices. # PSU_DDRC_DRAMTMG6_T_CKCSX 0x4 # SDRAM Timing Register 6 @@ -2023,16 +2293,20 @@ set psu_ddr_init_data { mask_write 0XFD070118 0x0F0F000F 0x01010004 # Register : DRAMTMG7 @ 0XFD07011C

- # This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. - # ecommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL For configurations with MEMC_FREQ_RATIO=2, program t - # is to recommended value divided by two and round it up to next integer. This is only present for designs supporting mDDR or L - # DDR2/LPDDR3/LPDDR4 devices. + # This is the time after Power Down Entry that CK is maintained as a valid + # clock. Specifies the clock disable delay after PDE. Recommended setting + # s: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL For configuration + # s with MEMC_FREQ_RATIO=2, program this to recommended value divided by t + # wo and round it up to next integer. This is only present for designs sup + # porting mDDR or LPDDR2/LPDDR3/LPDDR4 devices. # PSU_DDRC_DRAMTMG7_T_CKPDE 0x6 - # This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable - # time before PDX. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: 2 For configurations with MEMC_FREQ_RATIO= - # , program this to recommended value divided by two and round it up to next integer. This is only present for designs supporti - # g mDDR or LPDDR2/LPDDR3/LPDDR4 devices. + # This is the time before Power Down Exit that CK is maintained as a valid + # clock before issuing PDX. Specifies the clock stable time before PDX. R + # ecommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: 2 For c + # onfigurations with MEMC_FREQ_RATIO=2, program this to recommended value + # divided by two and round it up to next integer. This is only present for + # designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices. # PSU_DDRC_DRAMTMG7_T_CKPDX 0x6 # SDRAM Timing Register 7 @@ -2040,50 +2314,64 @@ set psu_ddr_init_data { mask_write 0XFD07011C 0x00000F0F 0x00000606 # Register : DRAMTMG8 @ 0XFD070120

- # tXS_FAST: Exit Self Refresh to ZQCL, ZQCS and MRS (only CL, WR, RTP and Geardown mode). For configurations with MEMC_FREQ_RAT - # O=2, program this to the above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: Thi - # is applicable to only ZQCL/ZQCS commands. Note: Ensure this is less than or equal to t_xs_x32. - # PSU_DDRC_DRAMTMG8_T_XS_FAST_X32 0x4 + # tXS_FAST: Exit Self Refresh to ZQCL, ZQCS and MRS (only CL, WR, RTP and + # Geardown mode). For configurations with MEMC_FREQ_RATIO=2, program this + # to the above value divided by 2 and round up to next integer value. Unit + # : Multiples of 32 clocks. Note: This is applicable to only ZQCL/ZQCS com + # mands. Note: Ensure this is less than or equal to t_xs_x32. + # PSU_DDRC_DRAMTMG8_T_XS_FAST_X32 0x3 - # tXS_ABORT: Exit Self Refresh to commands not requiring a locked DLL in Self Refresh Abort. For configurations with MEMC_FREQ_ - # ATIO=2, program this to the above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: - # nsure this is less than or equal to t_xs_x32. - # PSU_DDRC_DRAMTMG8_T_XS_ABORT_X32 0x4 + # tXS_ABORT: Exit Self Refresh to commands not requiring a locked DLL in S + # elf Refresh Abort. For configurations with MEMC_FREQ_RATIO=2, program th + # is to the above value divided by 2 and round up to next integer value. U + # nit: Multiples of 32 clocks. Note: Ensure this is less than or equal to + # t_xs_x32. + # PSU_DDRC_DRAMTMG8_T_XS_ABORT_X32 0x3 - # tXSDLL: Exit Self Refresh to commands requiring a locked DLL. For configurations with MEMC_FREQ_RATIO=2, program this to the - # bove value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: Used only for DDR2, DDR3 and - # DR4 SDRAMs. + # tXSDLL: Exit Self Refresh to commands requiring a locked DLL. For config + # urations with MEMC_FREQ_RATIO=2, program this to the above value divided + # by 2 and round up to next integer value. Unit: Multiples of 32 clocks. + # Note: Used only for DDR2, DDR3 and DDR4 SDRAMs. # PSU_DDRC_DRAMTMG8_T_XS_DLL_X32 0xd - # tXS: Exit Self Refresh to commands not requiring a locked DLL. For configurations with MEMC_FREQ_RATIO=2, program this to the - # above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: Used only for DDR2, DDR3 and - # DDR4 SDRAMs. + # tXS: Exit Self Refresh to commands not requiring a locked DLL. For confi + # gurations with MEMC_FREQ_RATIO=2, program this to the above value divide + # d by 2 and round up to next integer value. Unit: Multiples of 32 clocks. + # Note: Used only for DDR2, DDR3 and DDR4 SDRAMs. # PSU_DDRC_DRAMTMG8_T_XS_X32 0x6 # SDRAM Timing Register 8 - #(OFFSET, MASK, VALUE) (0XFD070120, 0x7F7F7F7FU ,0x04040D06U) */ - mask_write 0XFD070120 0x7F7F7F7F 0x04040D06 + #(OFFSET, MASK, VALUE) (0XFD070120, 0x7F7F7F7FU ,0x03030D06U) */ + mask_write 0XFD070120 0x7F7F7F7F 0x03030D06 # Register : DRAMTMG9 @ 0XFD070124

- # DDR4 Write preamble mode - 0: 1tCK preamble - 1: 2tCK preamble Present only with MEMC_FREQ_RATIO=2 + # DDR4 Write preamble mode - 0: 1tCK preamble - 1: 2tCK preamble Present o + # nly with MEMC_FREQ_RATIO=2 # PSU_DDRC_DRAMTMG9_DDR4_WR_PREAMBLE 0x0 - # tCCD_S: This is the minimum time between two reads or two writes for different bank group. For bank switching (from bank 'a' - # o bank 'b'), the minimum time is this value + 1. For configurations with MEMC_FREQ_RATIO=2, program this to (tCCD_S/2) and ro - # nd it up to the next integer value. Present only in designs configured to support DDR4. Unit: clocks. + # tCCD_S: This is the minimum time between two reads or two writes for dif + # ferent bank group. For bank switching (from bank 'a' to bank 'b'), the m + # inimum time is this value + 1. For configurations with MEMC_FREQ_RATIO=2 + # , program this to (tCCD_S/2) and round it up to the next integer value. + # Present only in designs configured to support DDR4. Unit: clocks. # PSU_DDRC_DRAMTMG9_T_CCD_S 0x2 - # tRRD_S: Minimum time between activates from bank 'a' to bank 'b' for different bank group. For configurations with MEMC_FREQ_ - # ATIO=2, program this to (tRRD_S/2) and round it up to the next integer value. Present only in designs configured to support D - # R4. Unit: Clocks. + # tRRD_S: Minimum time between activates from bank 'a' to bank 'b' for dif + # ferent bank group. For configurations with MEMC_FREQ_RATIO=2, program th + # is to (tRRD_S/2) and round it up to the next integer value. Present only + # in designs configured to support DDR4. Unit: Clocks. # PSU_DDRC_DRAMTMG9_T_RRD_S 0x2 - # CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command for different bank group. Includes time for bus turn - # round, recovery times, and all per-bank, per-rank, and global constraints. Present only in designs configured to support DDR4 - # Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity latency - BL = burst length. This must match the value programm - # d in the BL bit of the mode register to the SDRAM - tWTR_S = internal write to read command delay for different bank group. T - # is comes directly from the SDRAM specification. For configurations with MEMC_FREQ_RATIO=2, divide the value calculated using - # he above equation by 2, and round it up to next integer. + # CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command + # for different bank group. Includes time for bus turnaround, recovery ti + # mes, and all per-bank, per-rank, and global constraints. Present only in + # designs configured to support DDR4. Unit: Clocks. Where: - CWL = CAS wr + # ite latency - PL = Parity latency - BL = burst length. This must match t + # he value programmed in the BL bit of the mode register to the SDRAM - tW + # TR_S = internal write to read command delay for different bank group. Th + # is comes directly from the SDRAM specification. For configurations with + # MEMC_FREQ_RATIO=2, divide the value calculated using the above equation + # by 2, and round it up to next integer. # PSU_DDRC_DRAMTMG9_WR2RD_S 0xb # SDRAM Timing Register 9 @@ -2091,39 +2379,48 @@ set psu_ddr_init_data { mask_write 0XFD070124 0x40070F3F 0x0002020B # Register : DRAMTMG11 @ 0XFD07012C

- # tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DLL. For configurations with MEMC_FREQ_RATIO=2, program - # this to (tXMPDLL/2) and round it up to the next integer value. Present only in designs configured to support DDR4. Unit: Mult - # ples of 32 clocks. - # PSU_DDRC_DRAMTMG11_POST_MPSM_GAP_X32 0x6f + # tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DL + # L. For configurations with MEMC_FREQ_RATIO=2, program this to (tXMPDLL/2 + # ) and round it up to the next integer value. Present only in designs con + # figured to support DDR4. Unit: Multiples of 32 clocks. + # PSU_DDRC_DRAMTMG11_POST_MPSM_GAP_X32 0x70 - # tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge. For configurations with MEMC_FREQ_RATIO=2, program this t - # RoundUp(tMPX_LH/2)+1. Present only in designs configured to support DDR4. Unit: clocks. + # tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge. For + # configurations with MEMC_FREQ_RATIO=2, program this to RoundUp(tMPX_LH/2 + # )+1. Present only in designs configured to support DDR4. Unit: clocks. # PSU_DDRC_DRAMTMG11_T_MPX_LH 0x7 - # tMPX_S: Minimum time CS setup time to CKE. For configurations with MEMC_FREQ_RATIO=2, program this to (tMPX_S/2) and round it - # up to the next integer value. Present only in designs configured to support DDR4. Unit: Clocks. + # tMPX_S: Minimum time CS setup time to CKE. For configurations with MEMC_ + # FREQ_RATIO=2, program this to (tMPX_S/2) and round it up to the next int + # eger value. Present only in designs configured to support DDR4. Unit: Cl + # ocks. # PSU_DDRC_DRAMTMG11_T_MPX_S 0x1 - # tCKMPE: Minimum valid clock requirement after MPSM entry. Present only in designs configured to support DDR4. Unit: Clocks. F - # r configurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next i - # teger. + # tCKMPE: Minimum valid clock requirement after MPSM entry. Present only i + # n designs configured to support DDR4. Unit: Clocks. For configurations w + # ith MEMC_FREQ_RATIO=2, divide the value calculated using the above equat + # ion by 2, and round it up to next integer. # PSU_DDRC_DRAMTMG11_T_CKMPE 0xe # SDRAM Timing Register 11 - #(OFFSET, MASK, VALUE) (0XFD07012C, 0x7F1F031FU ,0x6F07010EU) */ - mask_write 0XFD07012C 0x7F1F031F 0x6F07010E + #(OFFSET, MASK, VALUE) (0XFD07012C, 0x7F1F031FU ,0x7007010EU) */ + mask_write 0XFD07012C 0x7F1F031F 0x7007010E # Register : DRAMTMG12 @ 0XFD070130

- # tCMDCKE: Delay from valid command to CKE input LOW. Set this to the larger of tESCKE or tCMDCKE For configurations with MEMC_ - # REQ_RATIO=2, program this to (max(tESCKE, tCMDCKE)/2) and round it up to next integer value. + # tCMDCKE: Delay from valid command to CKE input LOW. Set this to the larg + # er of tESCKE or tCMDCKE For configurations with MEMC_FREQ_RATIO=2, progr + # am this to (max(tESCKE, tCMDCKE)/2) and round it up to next integer valu + # e. # PSU_DDRC_DRAMTMG12_T_CMDCKE 0x2 - # tCKEHCMD: Valid command requirement after CKE input HIGH. For configurations with MEMC_FREQ_RATIO=2, program this to (tCKEHCM - # /2) and round it up to next integer value. + # tCKEHCMD: Valid command requirement after CKE input HIGH. For configurat + # ions with MEMC_FREQ_RATIO=2, program this to (tCKEHCMD/2) and round it u + # p to next integer value. # PSU_DDRC_DRAMTMG12_T_CKEHCMD 0x6 - # tMRD_PDA: This is the Mode Register Set command cycle time in PDA mode. For configurations with MEMC_FREQ_RATIO=2, program th - # s to (tMRD_PDA/2) and round it up to next integer value. + # tMRD_PDA: This is the Mode Register Set command cycle time in PDA mode. + # For configurations with MEMC_FREQ_RATIO=2, program this to (tMRD_PDA/2) + # and round it up to next integer value. # PSU_DDRC_DRAMTMG12_T_MRD_PDA 0x8 # SDRAM Timing Register 12 @@ -2131,38 +2428,51 @@ set psu_ddr_init_data { mask_write 0XFD070130 0x00030F1F 0x00020608 # Register : ZQCTL0 @ 0XFD070180

- # - 1 - Disable uMCTL2 generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used instead to is - # ue ZQ calibration request from APB module. - 0 - Internally generate ZQCS/MPC(ZQ calibration) commands based on ZQCTL1.t_zq_s - # ort_interval_x1024. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. + # - 1 - Disable uMCTL2 generation of ZQCS/MPC(ZQ calibration) command. Reg + # ister DBGCMD.zq_calib_short can be used instead to issue ZQ calibration + # request from APB module. - 0 - Internally generate ZQCS/MPC(ZQ calibrati + # on) commands based on ZQCTL1.t_zq_short_interval_x1024. This is only pre + # sent for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. # PSU_DDRC_ZQCTL0_DIS_AUTO_ZQ 0x1 - # - 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable when run in DDR3 - # or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. - 0 - Enable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Power - # own exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. This is only present for designs suppo - # ting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. + # - 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refres + # h/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 + # or LPDDR3 or LPDDR4 mode. - 0 - Enable issuing of ZQCL/MPC(ZQ calibratio + # n) command at Self-Refresh/SR-Powerdown exit. Only applicable when run i + # n DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. This is only present + # for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. # PSU_DDRC_ZQCTL0_DIS_SRX_ZQCL 0x0 - # - 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are sent to one r - # nk at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to different ranks do not ov - # rlap. - 0 - ZQ resistor is not shared. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. + # - 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQC + # L/ZQCS/MPC(ZQ calibration) commands are sent to one rank at a time with + # tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that co + # mmands to different ranks do not overlap. - 0 - ZQ resistor is not share + # d. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR + # 3/LPDDR4 devices. # PSU_DDRC_ZQCTL0_ZQ_RESISTOR_SHARED 0x0 - # - 1 - Disable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode. - 0 - Enable - # ssuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode. This is only present for des - # gns supporting DDR4 devices. + # - 1 - Disable issuing of ZQCL command at Maximum Power Saving Mode exit. + # Only applicable when run in DDR4 mode. - 0 - Enable issuing of ZQCL com + # mand at Maximum Power Saving Mode exit. Only applicable when run in DDR4 + # mode. This is only present for designs supporting DDR4 devices. # PSU_DDRC_ZQCTL0_DIS_MPSMX_ZQCL 0x0 - # tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Number of cycles of NOP required after a ZQCL (ZQ calibrat - # on long)/MPC(ZQ Start) command is issued to SDRAM. For configurations with MEMC_FREQ_RATIO=2: DDR3/DDR4: program this to tZQo - # er/2 and round it up to the next integer value. LPDDR2/LPDDR3: program this to tZQCL/2 and round it up to the next integer va - # ue. LPDDR4: program this to tZQCAL/2 and round it up to the next integer value. Unit: Clock cycles. This is only present for - # esigns supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. + # tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Numbe + # r of cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ St + # art) command is issued to SDRAM. For configurations with MEMC_FREQ_RATIO + # =2: DDR3/DDR4: program this to tZQoper/2 and round it up to the next int + # eger value. LPDDR2/LPDDR3: program this to tZQCL/2 and round it up to th + # e next integer value. LPDDR4: program this to tZQCAL/2 and round it up t + # o the next integer value. Unit: Clock cycles. This is only present for d + # esigns supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. # PSU_DDRC_ZQCTL0_T_ZQ_LONG_NOP 0x100 - # tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of cycles of NOP required after a ZQCS (ZQ calibration short)/MPC - # ZQ Latch) command is issued to SDRAM. For configurations with MEMC_FREQ_RATIO=2, program this to tZQCS/2 and round it up to t - # e next integer value. Unit: Clock cycles. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devic - # s. + # tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of cycles of + # NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command + # is issued to SDRAM. For configurations with MEMC_FREQ_RATIO=2, program t + # his to tZQCS/2 and round it up to the next integer value. Unit: Clock cy + # cles. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LP + # DDR3/LPDDR4 devices. # PSU_DDRC_ZQCTL0_T_ZQ_SHORT_NOP 0x40 # ZQ Control Register 0 @@ -2170,53 +2480,70 @@ set psu_ddr_init_data { mask_write 0XFD070180 0xF7FF03FF 0x81000040 # Register : ZQCTL1 @ 0XFD070184

- # tZQReset: Number of cycles of NOP required after a ZQReset (ZQ calibration Reset) command is issued to SDRAM. For configurati - # ns with MEMC_FREQ_RATIO=2, program this to tZQReset/2 and round it up to the next integer value. Unit: Clock cycles. This is - # nly present for designs supporting LPDDR2/LPDDR3/LPDDR4 devices. + # tZQReset: Number of cycles of NOP required after a ZQReset (ZQ calibrati + # on Reset) command is issued to SDRAM. For configurations with MEMC_FREQ_ + # RATIO=2, program this to tZQReset/2 and round it up to the next integer + # value. Unit: Clock cycles. This is only present for designs supporting L + # PDDR2/LPDDR3/LPDDR4 devices. # PSU_DDRC_ZQCTL1_T_ZQ_RESET_NOP 0x20 - # Average interval to wait between automatically issuing ZQCS (ZQ calibration short)/MPC(ZQ calibration) commands to DDR3/DDR4/ - # PDDR2/LPDDR3/LPDDR4 devices. Meaningless, if ZQCTL0.dis_auto_zq=1. Unit: 1024 clock cycles. This is only present for designs - # upporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. - # PSU_DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024 0x19707 + # Average interval to wait between automatically issuing ZQCS (ZQ calibrat + # ion short)/MPC(ZQ calibration) commands to DDR3/DDR4/LPDDR2/LPDDR3/LPDDR + # 4 devices. Meaningless, if ZQCTL0.dis_auto_zq=1. Unit: 1024 clock cycles + # . This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3 + # /LPDDR4 devices. + # PSU_DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024 0x196dc # ZQ Control Register 1 - #(OFFSET, MASK, VALUE) (0XFD070184, 0x3FFFFFFFU ,0x02019707U) */ - mask_write 0XFD070184 0x3FFFFFFF 0x02019707 + #(OFFSET, MASK, VALUE) (0XFD070184, 0x3FFFFFFFU ,0x020196DCU) */ + mask_write 0XFD070184 0x3FFFFFFF 0x020196DC # Register : DFITMG0 @ 0XFD070190

- # Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signa - # s at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligne - # , this timing parameter should be rounded up to the next integer value. Note that if using RDIMM, it is necessary to incremen - # this parameter by RDIMM's extra cycle of latency in terms of DFI clock. + # Specifies the number of DFI clock cycles after an assertion or de-assert + # ion of the DFI control signals that the control signals at the PHY-DRAM + # interface reflect the assertion or de-assertion. If the DFI clock and th + # e memory clock are not phase-aligned, this timing parameter should be ro + # unded up to the next integer value. Note that if using RDIMM, it is nece + # ssary to increment this parameter by RDIMM's extra cycle of latency in t + # erms of DFI clock. # PSU_DDRC_DFITMG0_DFI_T_CTRL_DELAY 0x4 - # Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR or SDR values Selects whether value in DFITM - # 0.dfi_t_rddata_en is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles R - # fer to PHY specification for correct value. + # Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated u + # sing HDR or SDR values Selects whether value in DFITMG0.dfi_t_rddata_en + # is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles + # - 1 in terms of SDR clock cycles Refer to PHY specification for correct + # value. # PSU_DDRC_DFITMG0_DFI_RDDATA_USE_SDR 0x1 - # Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. Refer to PHY spe - # ification for correct value. This corresponds to the DFI parameter trddata_en. Note that, depending on the PHY, if using RDIM - # , it may be necessary to use the value (CL + 1) in the calculation of trddata_en. This is to compensate for the extra cycle o - # latency through the RDIMM. Unit: Clocks + # Time from the assertion of a read command on the DFI interface to the as + # sertion of the dfi_rddata_en signal. Refer to PHY specification for corr + # ect value. This corresponds to the DFI parameter trddata_en. Note that, + # depending on the PHY, if using RDIMM, it may be necessary to use the val + # ue (CL + 1) in the calculation of trddata_en. This is to compensate for + # the extra cycle of latency through the RDIMM. Unit: Clocks # PSU_DDRC_DFITMG0_DFI_T_RDDATA_EN 0xb - # Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using HDR or SDR values Selects whether value in DFITMG - # .dfi_tphy_wrlat is in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.dfi_tphy_wrdata is in terms of SDR or - # HDR clock cycles - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles Refer to PHY specification for correct val - # e. + # Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated us + # ing HDR or SDR values Selects whether value in DFITMG0.dfi_tphy_wrlat is + # in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.df + # i_tphy_wrdata is in terms of SDR or HDR clock cycles - 0 in terms of HDR + # clock cycles - 1 in terms of SDR clock cycles Refer to PHY specificatio + # n for correct value. # PSU_DDRC_DFITMG0_DFI_WRDATA_USE_SDR 0x1 - # Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on th - # dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. N - # te, max supported value is 8. Unit: Clocks + # Specifies the number of clock cycles between when dfi_wrdata_en is asser + # ted to when the associated write data is driven on the dfi_wrdata signal + # . This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY + # specification for correct value. Note, max supported value is 8. Unit: + # Clocks # PSU_DDRC_DFITMG0_DFI_TPHY_WRDATA 0x2 - # Write latency Number of clocks from the write command to write data enable (dfi_wrdata_en). This corresponds to the DFI timin - # parameter tphy_wrlat. Refer to PHY specification for correct value.Note that, depending on the PHY, if using RDIMM, it may b - # necessary to use the value (CL + 1) in the calculation of tphy_wrlat. This is to compensate for the extra cycle of latency t - # rough the RDIMM. + # Write latency Number of clocks from the write command to write data enab + # le (dfi_wrdata_en). This corresponds to the DFI timing parameter tphy_wr + # lat. Refer to PHY specification for correct value.Note that, depending o + # n the PHY, if using RDIMM, it may be necessary to use the value (CL + 1) + # in the calculation of tphy_wrlat. This is to compensate for the extra c + # ycle of latency through the RDIMM. # PSU_DDRC_DFITMG0_DFI_TPHY_WRLAT 0xb # DFI Timing Register 0 @@ -2224,31 +2551,40 @@ set psu_ddr_init_data { mask_write 0XFD070190 0x1FBFBF3F 0x048B820B # Register : DFITMG1 @ 0XFD070194

- # Specifies the number of DFI PHY clocks between when the dfi_cs signal is asserted and when the associated command is driven. - # his field is used for CAL mode, should be set to '0' or the value which matches the CAL mode register setting in the DRAM. If - # the PHY can add the latency for CAL mode, this should be set to '0'. Valid Range: 0, 3, 4, 5, 6, and 8 + # Specifies the number of DFI PHY clocks between when the dfi_cs signal is + # asserted and when the associated command is driven. This field is used + # for CAL mode, should be set to '0' or the value which matches the CAL mo + # de register setting in the DRAM. If the PHY can add the latency for CAL + # mode, this should be set to '0'. Valid Range: 0, 3, 4, 5, 6, and 8 # PSU_DDRC_DFITMG1_DFI_T_CMD_LAT 0x0 - # Specifies the number of DFI PHY clocks between when the dfi_cs signal is asserted and when the associated dfi_parity_in signa - # is driven. + # Specifies the number of DFI PHY clocks between when the dfi_cs signal is + # asserted and when the associated dfi_parity_in signal is driven. # PSU_DDRC_DFITMG1_DFI_T_PARIN_LAT 0x0 - # Specifies the number of DFI clocks between when the dfi_wrdata_en signal is asserted and when the corresponding write data tr - # nsfer is completed on the DRAM bus. This corresponds to the DFI timing parameter twrdata_delay. Refer to PHY specification fo - # correct value. For DFI 3.0 PHY, set to twrdata_delay, a new timing parameter introduced in DFI 3.0. For DFI 2.1 PHY, set to - # phy_wrdata + (delay of DFI write data to the DRAM). Value to be programmed is in terms of DFI clocks, not PHY clocks. In FREQ - # RATIO=2, divide PHY's value by 2 and round up to next integer. If using DFITMG0.dfi_wrdata_use_sdr=1, add 1 to the value. Uni - # : Clocks + # Specifies the number of DFI clocks between when the dfi_wrdata_en signal + # is asserted and when the corresponding write data transfer is completed + # on the DRAM bus. This corresponds to the DFI timing parameter twrdata_d + # elay. Refer to PHY specification for correct value. For DFI 3.0 PHY, set + # to twrdata_delay, a new timing parameter introduced in DFI 3.0. For DFI + # 2.1 PHY, set to tphy_wrdata + (delay of DFI write data to the DRAM). Va + # lue to be programmed is in terms of DFI clocks, not PHY clocks. In FREQ_ + # RATIO=2, divide PHY's value by 2 and round up to next integer. If using + # DFITMG0.dfi_wrdata_use_sdr=1, add 1 to the value. Unit: Clocks # PSU_DDRC_DFITMG1_DFI_T_WRDATA_DELAY 0x3 - # Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to - # he DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase - # ligned, this timing parameter should be rounded up to the next integer value. + # Specifies the number of DFI clock cycles from the assertion of the dfi_d + # ram_clk_disable signal on the DFI until the clock to the DRAM memory dev + # ices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock + # and the memory clock are not phase aligned, this timing parameter should + # be rounded up to the next integer value. # PSU_DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE 0x3 - # Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first - # alid rising edge of the clock to the DRAM memory devices, at the PHY-DRAM boundary. If the DFI clock and the memory clock are - # not phase aligned, this timing parameter should be rounded up to the next integer value. + # Specifies the number of DFI clock cycles from the de-assertion of the df + # i_dram_clk_disable signal on the DFI until the first valid rising edge o + # f the clock to the DRAM memory devices, at the PHY-DRAM boundary. If the + # DFI clock and the memory clock are not phase aligned, this timing param + # eter should be rounded up to the next integer value. # PSU_DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE 0x4 # DFI Timing Register 1 @@ -2256,37 +2592,48 @@ set psu_ddr_init_data { mask_write 0XFD070194 0xF31F0F0F 0x00030304 # Register : DFILPCFG0 @ 0XFD070198

- # Setting for DFI's tlp_resp time. Same value is used for both Power Down, Self Refresh, Deep Power Down and Maximum Power Savi - # g modes. DFI 2.1 specification onwards, recommends using a fixed value of 7 always. + # Setting for DFI's tlp_resp time. Same value is used for both Power Down, + # Self Refresh, Deep Power Down and Maximum Power Saving modes. DFI 2.1 s + # pecification onwards, recommends using a fixed value of 7 always. # PSU_DDRC_DFILPCFG0_DFI_TLP_RESP 0x7 - # Value to drive on dfi_lp_wakeup signal when Deep Power Down mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 - # cycles - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles - 0x7 - # - 2048 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0xD - - # 31072 cycles - 0xE - 262144 cycles - 0xF - Unlimited This is only present for designs supporting mDDR or LPDDR2/LPDDR3 device - # . + # Value to drive on dfi_lp_wakeup signal when Deep Power Down mode is ente + # red. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32 + # cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 5 + # 12 cycles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycles - + # 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 6553 + # 6 cycles - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited T + # his is only present for designs supporting mDDR or LPDDR2/LPDDR3 devices + # . # PSU_DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD 0x0 - # Enables DFI Low Power interface handshaking during Deep Power Down Entry/Exit. - 0 - Disabled - 1 - Enabled This is only pres - # nt for designs supporting mDDR or LPDDR2/LPDDR3 devices. + # Enables DFI Low Power interface handshaking during Deep Power Down Entry + # /Exit. - 0 - Disabled - 1 - Enabled This is only present for designs sup + # porting mDDR or LPDDR2/LPDDR3 devices. # PSU_DDRC_DFILPCFG0_DFI_LP_EN_DPD 0x0 - # Value to drive on dfi_lp_wakeup signal when Self Refresh mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cy - # les - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles - 0x7 - - # 048 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0xD - 131 - # 72 cycles - 0xE - 262144 cycles - 0xF - Unlimited + # Value to drive on dfi_lp_wakeup signal when Self Refresh mode is entered + # . Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32 cyc + # les - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 + # cycles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycles - 0x9 + # - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 c + # ycles - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited # PSU_DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR 0x0 - # Enables DFI Low Power interface handshaking during Self Refresh Entry/Exit. - 0 - Disabled - 1 - Enabled + # Enables DFI Low Power interface handshaking during Self Refresh Entry/Ex + # it. - 0 - Disabled - 1 - Enabled # PSU_DDRC_DFILPCFG0_DFI_LP_EN_SR 0x1 - # Value to drive on dfi_lp_wakeup signal when Power Down mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycl - # s - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles - 0x7 - 20 - # 8 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0xD - 13107 - # cycles - 0xE - 262144 cycles - 0xF - Unlimited + # Value to drive on dfi_lp_wakeup signal when Power Down mode is entered. + # Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32 cycle + # s - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cy + # cles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycles - 0x9 - + # 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cyc + # les - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited # PSU_DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD 0x0 - # Enables DFI Low Power interface handshaking during Power Down Entry/Exit. - 0 - Disabled - 1 - Enabled + # Enables DFI Low Power interface handshaking during Power Down Entry/Exit + # . - 0 - Disabled - 1 - Enabled # PSU_DDRC_DFILPCFG0_DFI_LP_EN_PD 0x1 # DFI Low Power Configuration Register 0 @@ -2294,48 +2641,88 @@ set psu_ddr_init_data { mask_write 0XFD070198 0x0FF1F1F1 0x07000101 # Register : DFILPCFG1 @ 0XFD07019C

- # Value to drive on dfi_lp_wakeup signal when Maximum Power Saving Mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - # - 16 cycles - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles - # 0x7 - 2048 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0 - # D - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited This is only present for designs supporting DDR4 devices. + # Value to drive on dfi_lp_wakeup signal when Maximum Power Saving Mode is + # entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 + # - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x + # 5 - 512 cycles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycl + # es - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - + # 65536 cycles - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimi + # ted This is only present for designs supporting DDR4 devices. # PSU_DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM 0x2 - # Enables DFI Low Power interface handshaking during Maximum Power Saving Mode Entry/Exit. - 0 - Disabled - 1 - Enabled This is - # only present for designs supporting DDR4 devices. + # Enables DFI Low Power interface handshaking during Maximum Power Saving + # Mode Entry/Exit. - 0 - Disabled - 1 - Enabled This is only present for d + # esigns supporting DDR4 devices. # PSU_DDRC_DFILPCFG1_DFI_LP_EN_MPSM 0x1 # DFI Low Power Configuration Register 1 #(OFFSET, MASK, VALUE) (0XFD07019C, 0x000000F1U ,0x00000021U) */ mask_write 0XFD07019C 0x000000F1 0x00000021 + # Register : DFIUPD0 @ 0XFD0701A0

+ + # When '1', disable the automatic dfi_ctrlupd_req generation by the uMCTL2 + # . The core must issue the dfi_ctrlupd_req signal using register reg_ddrc + # _ctrlupd. When '0', uMCTL2 issues dfi_ctrlupd_req periodically. + # PSU_DDRC_DFIUPD0_DIS_AUTO_CTRLUPD 0x0 + + # When '1', disable the automatic dfi_ctrlupd_req generation by the uMCTL2 + # following a self-refresh exit. The core must issue the dfi_ctrlupd_req + # signal using register reg_ddrc_ctrlupd. When '0', uMCTL2 issues a dfi_ct + # rlupd_req after exiting self-refresh. + # PSU_DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX 0x0 + + # Specifies the maximum number of clock cycles that the dfi_ctrlupd_req si + # gnal can assert. Lowest value to assign to this variable is 0x40. Unit: + # Clocks + # PSU_DDRC_DFIUPD0_DFI_T_CTRLUP_MAX 0x40 + + # Specifies the minimum number of clock cycles that the dfi_ctrlupd_req si + # gnal must be asserted. The uMCTL2 expects the PHY to respond within this + # time. If the PHY does not respond, the uMCTL2 will de-assert dfi_ctrlup + # d_req after dfi_t_ctrlup_min + 2 cycles. Lowest value to assign to this + # variable is 0x3. Unit: Clocks + # PSU_DDRC_DFIUPD0_DFI_T_CTRLUP_MIN 0x3 + + # DFI Update Register 0 + #(OFFSET, MASK, VALUE) (0XFD0701A0, 0xC3FF03FFU ,0x00400003U) */ + mask_write 0XFD0701A0 0xC3FF03FF 0x00400003 # Register : DFIUPD1 @ 0XFD0701A4

- # This is the minimum amount of time between uMCTL2 initiated DFI update requests (which is executed whenever the uMCTL2 is idl - # ). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the fir - # t read request when the uMCTL2 is idle. Unit: 1024 clocks + # This is the minimum amount of time between uMCTL2 initiated DFI update r + # equests (which is executed whenever the uMCTL2 is idle). Set this number + # higher to reduce the frequency of update requests, which can have a sma + # ll impact on the latency of the first read request when the uMCTL2 is id + # le. Unit: 1024 clocks # PSU_DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024 0x41 - # This is the maximum amount of time between uMCTL2 initiated DFI update requests. This timer resets with each update request; - # hen the timer expires dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd_ackx is received. PHY can use this - # idle time to recalibrate the delay lines to the DLLs. The DFI controller update is also used to reset PHY FIFO pointers in ca - # e of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. - # Note: Value programmed for DFIUPD1.dfi_t_ctrlupd_interval_max_x1024 must be greater than DFIUPD1.dfi_t_ctrlupd_interval_min_x - # 024. Unit: 1024 clocks - # PSU_DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024 0xe2 + # This is the maximum amount of time between uMCTL2 initiated DFI update r + # equests. This timer resets with each update request; when the timer expi + # res dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd + # _ackx is received. PHY can use this idle time to recalibrate the delay l + # ines to the DLLs. The DFI controller update is also used to reset PHY FI + # FO pointers in case of data capture errors. Updates are required to main + # tain calibration over PVT, but frequent updates may impact performance. + # Note: Value programmed for DFIUPD1.dfi_t_ctrlupd_interval_max_x1024 must + # be greater than DFIUPD1.dfi_t_ctrlupd_interval_min_x1024. Unit: 1024 cl + # ocks + # PSU_DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024 0xe1 # DFI Update Register 1 - #(OFFSET, MASK, VALUE) (0XFD0701A4, 0x00FF00FFU ,0x004100E2U) */ - mask_write 0XFD0701A4 0x00FF00FF 0x004100E2 + #(OFFSET, MASK, VALUE) (0XFD0701A4, 0x00FF00FFU ,0x004100E1U) */ + mask_write 0XFD0701A4 0x00FF00FF 0x004100E1 # Register : DFIMISC @ 0XFD0701B0

- # Defines polarity of dfi_wrdata_cs and dfi_rddata_cs signals. - 0: Signals are active low - 1: Signals are active high + # Defines polarity of dfi_wrdata_cs and dfi_rddata_cs signals. - 0: Signal + # s are active low - 1: Signals are active high # PSU_DDRC_DFIMISC_DFI_DATA_CS_POLARITY 0x0 - # DBI implemented in DDRC or PHY. - 0 - DDRC implements DBI functionality. - 1 - PHY implements DBI functionality. Present only - # in designs configured to support DDR4 and LPDDR4. + # DBI implemented in DDRC or PHY. - 0 - DDRC implements DBI functionality. + # - 1 - PHY implements DBI functionality. Present only in designs configu + # red to support DDR4 and LPDDR4. # PSU_DDRC_DFIMISC_PHY_DBI_MODE 0x0 - # PHY initialization complete enable signal. When asserted the dfi_init_complete signal can be used to trigger SDRAM initialisa - # ion + # PHY initialization complete enable signal. When asserted the dfi_init_co + # mplete signal can be used to trigger SDRAM initialisation # PSU_DDRC_DFIMISC_DFI_INIT_COMPLETE_EN 0x0 # DFI Miscellaneous Control Register @@ -2343,12 +2730,16 @@ set psu_ddr_init_data { mask_write 0XFD0701B0 0x00000007 0x00000000 # Register : DFITMG2 @ 0XFD0701B4

- # >Number of clocks between when a read command is sent on the DFI control interface and when the associated dfi_rddata_cs sign - # l is asserted. This corresponds to the DFI timing parameter tphy_rdcslat. Refer to PHY specification for correct value. + # >Number of clocks between when a read command is sent on the DFI control + # interface and when the associated dfi_rddata_cs signal is asserted. Thi + # s corresponds to the DFI timing parameter tphy_rdcslat. Refer to PHY spe + # cification for correct value. # PSU_DDRC_DFITMG2_DFI_TPHY_RDCSLAT 0x9 - # Number of clocks between when a write command is sent on the DFI control interface and when the associated dfi_wrdata_cs sign - # l is asserted. This corresponds to the DFI timing parameter tphy_wrcslat. Refer to PHY specification for correct value. + # Number of clocks between when a write command is sent on the DFI control + # interface and when the associated dfi_wrdata_cs signal is asserted. Thi + # s corresponds to the DFI timing parameter tphy_wrcslat. Refer to PHY spe + # cification for correct value. # PSU_DDRC_DFITMG2_DFI_TPHY_WRCSLAT 0x6 # DFI Timing Register 2 @@ -2356,17 +2747,23 @@ set psu_ddr_init_data { mask_write 0XFD0701B4 0x00003F3F 0x00000906 # Register : DBICTL @ 0XFD0701C0

- # Read DBI enable signal in DDRC. - 0 - Read DBI is disabled. - 1 - Read DBI is enabled. This signal must be set the same value - # as DRAM's mode register. - DDR4: MR5 bit A12. When x4 devices are used, this signal must be set to 0. - LPDDR4: MR3[6] + # Read DBI enable signal in DDRC. - 0 - Read DBI is disabled. - 1 - Read D + # BI is enabled. This signal must be set the same value as DRAM's mode reg + # ister. - DDR4: MR5 bit A12. When x4 devices are used, this signal must b + # e set to 0. - LPDDR4: MR3[6] # PSU_DDRC_DBICTL_RD_DBI_EN 0x0 - # Write DBI enable signal in DDRC. - 0 - Write DBI is disabled. - 1 - Write DBI is enabled. This signal must be set the same va - # ue as DRAM's mode register. - DDR4: MR5 bit A11. When x4 devices are used, this signal must be set to 0. - LPDDR4: MR3[7] + # Write DBI enable signal in DDRC. - 0 - Write DBI is disabled. - 1 - Writ + # e DBI is enabled. This signal must be set the same value as DRAM's mode + # register. - DDR4: MR5 bit A11. When x4 devices are used, this signal mus + # t be set to 0. - LPDDR4: MR3[7] # PSU_DDRC_DBICTL_WR_DBI_EN 0x0 - # DM enable signal in DDRC. - 0 - DM is disabled. - 1 - DM is enabled. This signal must be set the same logical value as DRAM's - # mode register. - DDR4: Set this to same value as MR5 bit A10. When x4 devices are used, this signal must be set to 0. - LPDDR - # : Set this to inverted value of MR13[5] which is opposite polarity from this signal + # DM enable signal in DDRC. - 0 - DM is disabled. - 1 - DM is enabled. Thi + # s signal must be set the same logical value as DRAM's mode register. - D + # DR4: Set this to same value as MR5 bit A10. When x4 devices are used, th + # is signal must be set to 0. - LPDDR4: Set this to inverted value of MR13 + # [5] which is opposite polarity from this signal # PSU_DDRC_DBICTL_DM_EN 0x1 # DM/DBI Control Register @@ -2374,8 +2771,10 @@ set psu_ddr_init_data { mask_write 0XFD0701C0 0x00000007 0x00000001 # Register : ADDRMAP0 @ 0XFD070200

- # Selects the HIF address bit used as rank address bit 0. Valid Range: 0 to 27, and 31 Internal Base: 6 The selected HIF addres - # bit is determined by adding the internal base to the value of this field. If set to 31, rank address bit 0 is set to 0. + # Selects the HIF address bit used as rank address bit 0. Valid Range: 0 t + # o 27, and 31 Internal Base: 6 The selected HIF address bit is determined + # by adding the internal base to the value of this field. If set to 31, r + # ank address bit 0 is set to 0. # PSU_DDRC_ADDRMAP0_ADDRMAP_CS_BIT0 0x1f # Address Map Register 0 @@ -2383,16 +2782,22 @@ set psu_ddr_init_data { mask_write 0XFD070200 0x0000001F 0x0000001F # Register : ADDRMAP1 @ 0XFD070204

- # Selects the HIF address bit used as bank address bit 2. Valid Range: 0 to 29 and 31 Internal Base: 4 The selected HIF address - # bit is determined by adding the internal base to the value of this field. If set to 31, bank address bit 2 is set to 0. + # Selects the HIF address bit used as bank address bit 2. Valid Range: 0 t + # o 29 and 31 Internal Base: 4 The selected HIF address bit is determined + # by adding the internal base to the value of this field. If set to 31, ba + # nk address bit 2 is set to 0. # PSU_DDRC_ADDRMAP1_ADDRMAP_BANK_B2 0x1f - # Selects the HIF address bits used as bank address bit 1. Valid Range: 0 to 30 Internal Base: 3 The selected HIF address bit f - # r each of the bank address bits is determined by adding the internal base to the value of this field. + # Selects the HIF address bits used as bank address bit 1. Valid Range: 0 + # to 30 Internal Base: 3 The selected HIF address bit for each of the bank + # address bits is determined by adding the internal base to the value of + # this field. # PSU_DDRC_ADDRMAP1_ADDRMAP_BANK_B1 0xa - # Selects the HIF address bits used as bank address bit 0. Valid Range: 0 to 30 Internal Base: 2 The selected HIF address bit f - # r each of the bank address bits is determined by adding the internal base to the value of this field. + # Selects the HIF address bits used as bank address bit 0. Valid Range: 0 + # to 30 Internal Base: 2 The selected HIF address bit for each of the bank + # address bits is determined by adding the internal base to the value of + # this field. # PSU_DDRC_ADDRMAP1_ADDRMAP_BANK_B0 0xa # Address Map Register 1 @@ -2400,29 +2805,41 @@ set psu_ddr_init_data { mask_write 0XFD070204 0x001F1F1F 0x001F0A0A # Register : ADDRMAP2 @ 0XFD070208

- # - Full bus width mode: Selects the HIF address bit used as column address bit 5. - Half bus width mode: Selects the HIF addre - # s bit used as column address bit 6. - Quarter bus width mode: Selects the HIF address bit used as column address bit 7 . Vali - # Range: 0 to 7, and 15 Internal Base: 5 The selected HIF address bit is determined by adding the internal base to the value o - # this field. If set to 15, this column address bit is set to 0. + # - Full bus width mode: Selects the HIF address bit used as column addres + # s bit 5. - Half bus width mode: Selects the HIF address bit used as colu + # mn address bit 6. - Quarter bus width mode: Selects the HIF address bit + # used as column address bit 7 . Valid Range: 0 to 7, and 15 Internal Base + # : 5 The selected HIF address bit is determined by adding the internal ba + # se to the value of this field. If set to 15, this column address bit is + # set to 0. # PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B5 0x0 - # - Full bus width mode: Selects the HIF address bit used as column address bit 4. - Half bus width mode: Selects the HIF addre - # s bit used as column address bit 5. - Quarter bus width mode: Selects the HIF address bit used as column address bit 6. Valid - # Range: 0 to 7, and 15 Internal Base: 4 The selected HIF address bit is determined by adding the internal base to the value of - # this field. If set to 15, this column address bit is set to 0. + # - Full bus width mode: Selects the HIF address bit used as column addres + # s bit 4. - Half bus width mode: Selects the HIF address bit used as colu + # mn address bit 5. - Quarter bus width mode: Selects the HIF address bit + # used as column address bit 6. Valid Range: 0 to 7, and 15 Internal Base: + # 4 The selected HIF address bit is determined by adding the internal bas + # e to the value of this field. If set to 15, this column address bit is s + # et to 0. # PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B4 0x0 - # - Full bus width mode: Selects the HIF address bit used as column address bit 3. - Half bus width mode: Selects the HIF addre - # s bit used as column address bit 4. - Quarter bus width mode: Selects the HIF address bit used as column address bit 5. Valid - # Range: 0 to 7 Internal Base: 3 The selected HIF address bit is determined by adding the internal base to the value of this fi - # ld. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=16, it is required to program this to 0, hence register does not exist i - # this case. + # - Full bus width mode: Selects the HIF address bit used as column addres + # s bit 3. - Half bus width mode: Selects the HIF address bit used as colu + # mn address bit 4. - Quarter bus width mode: Selects the HIF address bit + # used as column address bit 5. Valid Range: 0 to 7 Internal Base: 3 The s + # elected HIF address bit is determined by adding the internal base to the + # value of this field. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=1 + # 6, it is required to program this to 0, hence register does not exist in + # this case. # PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B3 0x0 - # - Full bus width mode: Selects the HIF address bit used as column address bit 2. - Half bus width mode: Selects the HIF addre - # s bit used as column address bit 3. - Quarter bus width mode: Selects the HIF address bit used as column address bit 4. Valid - # Range: 0 to 7 Internal Base: 2 The selected HIF address bit is determined by adding the internal base to the value of this fi - # ld. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=8 or 16, it is required to program this to 0. + # - Full bus width mode: Selects the HIF address bit used as column addres + # s bit 2. - Half bus width mode: Selects the HIF address bit used as colu + # mn address bit 3. - Quarter bus width mode: Selects the HIF address bit + # used as column address bit 4. Valid Range: 0 to 7 Internal Base: 2 The s + # elected HIF address bit is determined by adding the internal base to the + # value of this field. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=8 + # or 16, it is required to program this to 0. # PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B2 0x0 # Address Map Register 2 @@ -2430,34 +2847,48 @@ set psu_ddr_init_data { mask_write 0XFD070208 0x0F0F0F0F 0x00000000 # Register : ADDRMAP3 @ 0XFD07020C

- # - Full bus width mode: Selects the HIF address bit used as column address bit 9. - Half bus width mode: Selects the HIF addre - # s bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). - Quarter bus width mode: Selects the HIF address bit used as - # column address bit 13 (11 in LPDDR2/LPDDR3 mode). Valid Range: 0 to 7, and 15 Internal Base: 9 The selected HIF address bit i - # determined by adding the internal base to the value of this field. If set to 15, this column address bit is set to 0. Note: - # er JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source addr - # ss bit can be mapped to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus an - # hence column bit 10 is used. + # - Full bus width mode: Selects the HIF address bit used as column addres + # s bit 9. - Half bus width mode: Selects the HIF address bit used as colu + # mn address bit 11 (10 in LPDDR2/LPDDR3 mode). - Quarter bus width mode: + # Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/ + # LPDDR3 mode). Valid Range: 0 to 7, and 15 Internal Base: 9 The selected + # HIF address bit is determined by adding the internal base to the value o + # f this field. If set to 15, this column address bit is set to 0. Note: P + # er JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved fo + # r indicating auto-precharge, and hence no source address bit can be mapp + # ed to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit + # for auto-precharge in the CA bus and hence column bit 10 is used. # PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B9 0x0 - # - Full bus width mode: Selects the HIF address bit used as column address bit 8. - Half bus width mode: Selects the HIF addre - # s bit used as column address bit 9. - Quarter bus width mode: Selects the HIF address bit used as column address bit 11 (10 i - # LPDDR2/LPDDR3 mode). Valid Range: 0 to 7, and 15 Internal Base: 8 The selected HIF address bit is determined by adding the i - # ternal base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specif - # cation, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to col - # mn address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and hence column bit 10 is use - # . + # - Full bus width mode: Selects the HIF address bit used as column addres + # s bit 8. - Half bus width mode: Selects the HIF address bit used as colu + # mn address bit 9. - Quarter bus width mode: Selects the HIF address bit + # used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). Valid Range: 0 + # to 7, and 15 Internal Base: 8 The selected HIF address bit is determine + # d by adding the internal base to the value of this field. If set to 15, + # this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specifi + # cation, column address bit 10 is reserved for indicating auto-precharge, + # and hence no source address bit can be mapped to column address bit 10. + # In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA + # bus and hence column bit 10 is used. # PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B8 0x0 - # - Full bus width mode: Selects the HIF address bit used as column address bit 7. - Half bus width mode: Selects the HIF addre - # s bit used as column address bit 8. - Quarter bus width mode: Selects the HIF address bit used as column address bit 9. Valid - # Range: 0 to 7, and 15 Internal Base: 7 The selected HIF address bit is determined by adding the internal base to the value of - # this field. If set to 15, this column address bit is set to 0. + # - Full bus width mode: Selects the HIF address bit used as column addres + # s bit 7. - Half bus width mode: Selects the HIF address bit used as colu + # mn address bit 8. - Quarter bus width mode: Selects the HIF address bit + # used as column address bit 9. Valid Range: 0 to 7, and 15 Internal Base: + # 7 The selected HIF address bit is determined by adding the internal bas + # e to the value of this field. If set to 15, this column address bit is s + # et to 0. # PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B7 0x0 - # - Full bus width mode: Selects the HIF address bit used as column address bit 6. - Half bus width mode: Selects the HIF addre - # s bit used as column address bit 7. - Quarter bus width mode: Selects the HIF address bit used as column address bit 8. Valid - # Range: 0 to 7, and 15 Internal Base: 6 The selected HIF address bit is determined by adding the internal base to the value of - # this field. If set to 15, this column address bit is set to 0. + # - Full bus width mode: Selects the HIF address bit used as column addres + # s bit 6. - Half bus width mode: Selects the HIF address bit used as colu + # mn address bit 7. - Quarter bus width mode: Selects the HIF address bit + # used as column address bit 8. Valid Range: 0 to 7, and 15 Internal Base: + # 6 The selected HIF address bit is determined by adding the internal bas + # e to the value of this field. If set to 15, this column address bit is s + # et to 0. # PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B6 0x0 # Address Map Register 3 @@ -2465,21 +2896,30 @@ set psu_ddr_init_data { mask_write 0XFD07020C 0x0F0F0F0F 0x00000000 # Register : ADDRMAP4 @ 0XFD070210

- # - Full bus width mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode). - Half bus width - # mode: Unused. To make it unused, this should be tied to 4'hF. - Quarter bus width mode: Unused. To make it unused, this must - # e tied to 4'hF. Valid Range: 0 to 7, and 15 Internal Base: 11 The selected HIF address bit is determined by adding the intern - # l base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specificati - # n, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column a - # dress bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and hence column bit 10 is used. + # - Full bus width mode: Selects the HIF address bit used as column addres + # s bit 13 (11 in LPDDR2/LPDDR3 mode). - Half bus width mode: Unused. To m + # ake it unused, this should be tied to 4'hF. - Quarter bus width mode: Un + # used. To make it unused, this must be tied to 4'hF. Valid Range: 0 to 7, + # and 15 Internal Base: 11 The selected HIF address bit is determined by + # adding the internal base to the value of this field. If set to 15, this + # column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specificatio + # n, column address bit 10 is reserved for indicating auto-precharge, and + # hence no source address bit can be mapped to column address bit 10. In L + # PDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus + # and hence column bit 10 is used. # PSU_DDRC_ADDRMAP4_ADDRMAP_COL_B11 0xf - # - Full bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). - Half bus width - # mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode). - Quarter bus width mode: UNUSED. - # To make it unused, this must be tied to 4'hF. Valid Range: 0 to 7, and 15 Internal Base: 10 The selected HIF address bit is d - # termined by adding the internal base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per - # JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source address - # bit can be mapped to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and h - # nce column bit 10 is used. + # - Full bus width mode: Selects the HIF address bit used as column addres + # s bit 11 (10 in LPDDR2/LPDDR3 mode). - Half bus width mode: Selects the + # HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode) + # . - Quarter bus width mode: UNUSED. To make it unused, this must be tied + # to 4'hF. Valid Range: 0 to 7, and 15 Internal Base: 10 The selected HIF + # address bit is determined by adding the internal base to the value of t + # his field. If set to 15, this column address bit is set to 0. Note: Per + # JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for i + # ndicating auto-precharge, and hence no source address bit can be mapped + # to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for + # auto-precharge in the CA bus and hence column bit 10 is used. # PSU_DDRC_ADDRMAP4_ADDRMAP_COL_B10 0xf # Address Map Register 4 @@ -2487,22 +2927,31 @@ set psu_ddr_init_data { mask_write 0XFD070210 0x00000F0F 0x00000F0F # Register : ADDRMAP5 @ 0XFD070214

- # Selects the HIF address bit used as row address bit 11. Valid Range: 0 to 11, and 15 Internal Base: 17 The selected HIF addre - # s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 11 is set to 0. + # Selects the HIF address bit used as row address bit 11. Valid Range: 0 t + # o 11, and 15 Internal Base: 17 The selected HIF address bit is determine + # d by adding the internal base to the value of this field. If set to 15, + # row address bit 11 is set to 0. # PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B11 0x8 - # Selects the HIF address bits used as row address bits 2 to 10. Valid Range: 0 to 11, and 15 Internal Base: 8 (for row address - # bit 2), 9 (for row address bit 3), 10 (for row address bit 4) etc increasing to 16 (for row address bit 10) The selected HIF - # ddress bit for each of the row address bits is determined by adding the internal base to the value of this field. When value - # 5 is used the values of row address bits 2 to 10 are defined by registers ADDRMAP9, ADDRMAP10, ADDRMAP11. + # Selects the HIF address bits used as row address bits 2 to 10. Valid Ran + # ge: 0 to 11, and 15 Internal Base: 8 (for row address bit 2), 9 (for row + # address bit 3), 10 (for row address bit 4) etc increasing to 16 (for ro + # w address bit 10) The selected HIF address bit for each of the row addre + # ss bits is determined by adding the internal base to the value of this f + # ield. When value 15 is used the values of row address bits 2 to 10 are d + # efined by registers ADDRMAP9, ADDRMAP10, ADDRMAP11. # PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10 0xf - # Selects the HIF address bits used as row address bit 1. Valid Range: 0 to 11 Internal Base: 7 The selected HIF address bit fo - # each of the row address bits is determined by adding the internal base to the value of this field. + # Selects the HIF address bits used as row address bit 1. Valid Range: 0 t + # o 11 Internal Base: 7 The selected HIF address bit for each of the row a + # ddress bits is determined by adding the internal base to the value of th + # is field. # PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B1 0x8 - # Selects the HIF address bits used as row address bit 0. Valid Range: 0 to 11 Internal Base: 6 The selected HIF address bit fo - # each of the row address bits is determined by adding the internal base to the value of this field. + # Selects the HIF address bits used as row address bit 0. Valid Range: 0 t + # o 11 Internal Base: 6 The selected HIF address bit for each of the row a + # ddress bits is determined by adding the internal base to the value of th + # is field. # PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B0 0x8 # Address Map Register 5 @@ -2510,25 +2959,35 @@ set psu_ddr_init_data { mask_write 0XFD070214 0x0F0F0F0F 0x080F0808 # Register : ADDRMAP6 @ 0XFD070218

- # Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use. - 1 - LPDDR3 SDRAM 6Gb/12Gb device in use. Every address - # having row[14:13]==2'b11 is considered as invalid - 0 - non-LPDDR3 6Gb/12Gb device in use. All addresses are valid Present on - # y in designs configured to support LPDDR3. + # Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use. - 1 + # - LPDDR3 SDRAM 6Gb/12Gb device in use. Every address having row[14:13]= + # =2'b11 is considered as invalid - 0 - non-LPDDR3 6Gb/12Gb device in use. + # All addresses are valid Present only in designs configured to support L + # PDDR3. # PSU_DDRC_ADDRMAP6_LPDDR3_6GB_12GB 0x0 - # Selects the HIF address bit used as row address bit 15. Valid Range: 0 to 11, and 15 Internal Base: 21 The selected HIF addre - # s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 15 is set to 0. + # Selects the HIF address bit used as row address bit 15. Valid Range: 0 t + # o 11, and 15 Internal Base: 21 The selected HIF address bit is determine + # d by adding the internal base to the value of this field. If set to 15, + # row address bit 15 is set to 0. # PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B15 0xf - # Selects the HIF address bit used as row address bit 14. Valid Range: 0 to 11, and 15 Internal Base: 20 The selected HIF addre - # s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 14 is set to 0. + # Selects the HIF address bit used as row address bit 14. Valid Range: 0 t + # o 11, and 15 Internal Base: 20 The selected HIF address bit is determine + # d by adding the internal base to the value of this field. If set to 15, + # row address bit 14 is set to 0. # PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B14 0x8 - # Selects the HIF address bit used as row address bit 13. Valid Range: 0 to 11, and 15 Internal Base: 19 The selected HIF addre - # s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 13 is set to 0. + # Selects the HIF address bit used as row address bit 13. Valid Range: 0 t + # o 11, and 15 Internal Base: 19 The selected HIF address bit is determine + # d by adding the internal base to the value of this field. If set to 15, + # row address bit 13 is set to 0. # PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B13 0x8 - # Selects the HIF address bit used as row address bit 12. Valid Range: 0 to 11, and 15 Internal Base: 18 The selected HIF addre - # s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 12 is set to 0. + # Selects the HIF address bit used as row address bit 12. Valid Range: 0 t + # o 11, and 15 Internal Base: 18 The selected HIF address bit is determine + # d by adding the internal base to the value of this field. If set to 15, + # row address bit 12 is set to 0. # PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B12 0x8 # Address Map Register 6 @@ -2536,12 +2995,16 @@ set psu_ddr_init_data { mask_write 0XFD070218 0x8F0F0F0F 0x0F080808 # Register : ADDRMAP7 @ 0XFD07021C

- # Selects the HIF address bit used as row address bit 17. Valid Range: 0 to 10, and 15 Internal Base: 23 The selected HIF addre - # s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 17 is set to 0. + # Selects the HIF address bit used as row address bit 17. Valid Range: 0 t + # o 10, and 15 Internal Base: 23 The selected HIF address bit is determine + # d by adding the internal base to the value of this field. If set to 15, + # row address bit 17 is set to 0. # PSU_DDRC_ADDRMAP7_ADDRMAP_ROW_B17 0xf - # Selects the HIF address bit used as row address bit 16. Valid Range: 0 to 11, and 15 Internal Base: 22 The selected HIF addre - # s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 16 is set to 0. + # Selects the HIF address bit used as row address bit 16. Valid Range: 0 t + # o 11, and 15 Internal Base: 22 The selected HIF address bit is determine + # d by adding the internal base to the value of this field. If set to 15, + # row address bit 16 is set to 0. # PSU_DDRC_ADDRMAP7_ADDRMAP_ROW_B16 0xf # Address Map Register 7 @@ -2549,13 +3012,17 @@ set psu_ddr_init_data { mask_write 0XFD07021C 0x00000F0F 0x00000F0F # Register : ADDRMAP8 @ 0XFD070220

- # Selects the HIF address bits used as bank group address bit 1. Valid Range: 0 to 30, and 31 Internal Base: 3 The selected HIF - # address bit for each of the bank group address bits is determined by adding the internal base to the value of this field. If - # et to 31, bank group address bit 1 is set to 0. + # Selects the HIF address bits used as bank group address bit 1. Valid Ran + # ge: 0 to 30, and 31 Internal Base: 3 The selected HIF address bit for ea + # ch of the bank group address bits is determined by adding the internal b + # ase to the value of this field. If set to 31, bank group address bit 1 i + # s set to 0. # PSU_DDRC_ADDRMAP8_ADDRMAP_BG_B1 0x8 - # Selects the HIF address bits used as bank group address bit 0. Valid Range: 0 to 30 Internal Base: 2 The selected HIF address - # bit for each of the bank group address bits is determined by adding the internal base to the value of this field. + # Selects the HIF address bits used as bank group address bit 0. Valid Ran + # ge: 0 to 30 Internal Base: 2 The selected HIF address bit for each of th + # e bank group address bits is determined by adding the internal base to t + # he value of this field. # PSU_DDRC_ADDRMAP8_ADDRMAP_BG_B0 0x8 # Address Map Register 8 @@ -2563,24 +3030,32 @@ set psu_ddr_init_data { mask_write 0XFD070220 0x00001F1F 0x00000808 # Register : ADDRMAP9 @ 0XFD070224

- # Selects the HIF address bits used as row address bit 5. Valid Range: 0 to 11 Internal Base: 11 The selected HIF address bit f - # r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u - # ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15. + # Selects the HIF address bits used as row address bit 5. Valid Range: 0 t + # o 11 Internal Base: 11 The selected HIF address bit for each of the row + # address bits is determined by adding the internal base to the value of t + # his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + # _10 is set to value 15. # PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B5 0x8 - # Selects the HIF address bits used as row address bit 4. Valid Range: 0 to 11 Internal Base: 10 The selected HIF address bit f - # r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u - # ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15. + # Selects the HIF address bits used as row address bit 4. Valid Range: 0 t + # o 11 Internal Base: 10 The selected HIF address bit for each of the row + # address bits is determined by adding the internal base to the value of t + # his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + # _10 is set to value 15. # PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B4 0x8 - # Selects the HIF address bits used as row address bit 3. Valid Range: 0 to 11 Internal Base: 9 The selected HIF address bit fo - # each of the row address bits is determined by adding the internal base to the value of this field. This register field is us - # d only when ADDRMAP5.addrmap_row_b2_10 is set to value 15. + # Selects the HIF address bits used as row address bit 3. Valid Range: 0 t + # o 11 Internal Base: 9 The selected HIF address bit for each of the row a + # ddress bits is determined by adding the internal base to the value of th + # is field. This register field is used only when ADDRMAP5.addrmap_row_b2_ + # 10 is set to value 15. # PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B3 0x8 - # Selects the HIF address bits used as row address bit 2. Valid Range: 0 to 11 Internal Base: 8 The selected HIF address bit fo - # each of the row address bits is determined by adding the internal base to the value of this field. This register field is us - # d only when ADDRMAP5.addrmap_row_b2_10 is set to value 15. + # Selects the HIF address bits used as row address bit 2. Valid Range: 0 t + # o 11 Internal Base: 8 The selected HIF address bit for each of the row a + # ddress bits is determined by adding the internal base to the value of th + # is field. This register field is used only when ADDRMAP5.addrmap_row_b2_ + # 10 is set to value 15. # PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B2 0x8 # Address Map Register 9 @@ -2588,24 +3063,32 @@ set psu_ddr_init_data { mask_write 0XFD070224 0x0F0F0F0F 0x08080808 # Register : ADDRMAP10 @ 0XFD070228

- # Selects the HIF address bits used as row address bit 9. Valid Range: 0 to 11 Internal Base: 15 The selected HIF address bit f - # r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u - # ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15. + # Selects the HIF address bits used as row address bit 9. Valid Range: 0 t + # o 11 Internal Base: 15 The selected HIF address bit for each of the row + # address bits is determined by adding the internal base to the value of t + # his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + # _10 is set to value 15. # PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B9 0x8 - # Selects the HIF address bits used as row address bit 8. Valid Range: 0 to 11 Internal Base: 14 The selected HIF address bit f - # r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u - # ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15. + # Selects the HIF address bits used as row address bit 8. Valid Range: 0 t + # o 11 Internal Base: 14 The selected HIF address bit for each of the row + # address bits is determined by adding the internal base to the value of t + # his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + # _10 is set to value 15. # PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B8 0x8 - # Selects the HIF address bits used as row address bit 7. Valid Range: 0 to 11 Internal Base: 13 The selected HIF address bit f - # r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u - # ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15. + # Selects the HIF address bits used as row address bit 7. Valid Range: 0 t + # o 11 Internal Base: 13 The selected HIF address bit for each of the row + # address bits is determined by adding the internal base to the value of t + # his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + # _10 is set to value 15. # PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B7 0x8 - # Selects the HIF address bits used as row address bit 6. Valid Range: 0 to 11 Internal Base: 12 The selected HIF address bit f - # r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u - # ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15. + # Selects the HIF address bits used as row address bit 6. Valid Range: 0 t + # o 11 Internal Base: 12 The selected HIF address bit for each of the row + # address bits is determined by adding the internal base to the value of t + # his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + # _10 is set to value 15. # PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B6 0x8 # Address Map Register 10 @@ -2613,9 +3096,11 @@ set psu_ddr_init_data { mask_write 0XFD070228 0x0F0F0F0F 0x08080808 # Register : ADDRMAP11 @ 0XFD07022C

- # Selects the HIF address bits used as row address bit 10. Valid Range: 0 to 11 Internal Base: 16 The selected HIF address bit - # or each of the row address bits is determined by adding the internal base to the value of this field. This register field is - # sed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15. + # Selects the HIF address bits used as row address bit 10. Valid Range: 0 + # to 11 Internal Base: 16 The selected HIF address bit for each of the row + # address bits is determined by adding the internal base to the value of + # this field. This register field is used only when ADDRMAP5.addrmap_row_b + # 2_10 is set to value 15. # PSU_DDRC_ADDRMAP11_ADDRMAP_ROW_B10 0x8 # Address Map Register 11 @@ -2623,30 +3108,42 @@ set psu_ddr_init_data { mask_write 0XFD07022C 0x0000000F 0x00000008 # Register : ODTCFG @ 0XFD070240

- # Cycles to hold ODT for a write command. The minimum supported value is 2. Recommended values: DDR2: - BL8: 0x5 (DDR2-400/533/ - # 67), 0x6 (DDR2-800), 0x7 (DDR2-1066) - BL4: 0x3 (DDR2-400/533/667), 0x4 (DDR2-800), 0x5 (DDR2-1066) DDR3: - BL8: 0x6 DDR4: - - # L8: 5 + WR_PREAMBLE + CRC_MODE WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) CRC_MODE = 0 (not CRC mode), 1 - # CRC mode) LPDDR3: - BL8: 7 + RU(tODTon(max)/tCK) + # Cycles to hold ODT for a write command. The minimum supported value is 2 + # . Recommended values: DDR2: - BL8: 0x5 (DDR2-400/533/667), 0x6 (DDR2-800 + # ), 0x7 (DDR2-1066) - BL4: 0x3 (DDR2-400/533/667), 0x4 (DDR2-800), 0x5 (D + # DR2-1066) DDR3: - BL8: 0x6 DDR4: - BL8: 5 + WR_PREAMBLE + CRC_MODE WR_PR + # EAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) CRC_MODE = 0 ( + # not CRC mode), 1 (CRC mode) LPDDR3: - BL8: 7 + RU(tODTon(max)/tCK) # PSU_DDRC_ODTCFG_WR_ODT_HOLD 0x6 - # The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting must - # remain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: - CWL + AL - 3 (DDR2-400/533/ - # 67), CWL + AL - 4 (DDR2-800), CWL + AL - 5 (DDR2-1066) If (CWL + AL - 3 < 0), uMCTL2 does not support ODT for write operation - # DDR3: - 0x0 DDR4: - DFITMG1.dfi_t_cmd_lat (to adjust for CAL mode) LPDDR3: - WL - 1 - RU(tODTon(max)/tCK)) + # The delay, in clock cycles, from issuing a write command to setting ODT + # values associated with that command. ODT setting must remain constant fo + # r the entire time that DQS is driven by the uMCTL2. Recommended values: + # DDR2: - CWL + AL - 3 (DDR2-400/533/667), CWL + AL - 4 (DDR2-800), CWL + + # AL - 5 (DDR2-1066) If (CWL + AL - 3 < 0), uMCTL2 does not support ODT fo + # r write operation. DDR3: - 0x0 DDR4: - DFITMG1.dfi_t_cmd_lat (to adjust + # for CAL mode) LPDDR3: - WL - 1 - RU(tODTon(max)/tCK)) # PSU_DDRC_ODTCFG_WR_ODT_DELAY 0x0 - # Cycles to hold ODT for a read command. The minimum supported value is 2. Recommended values: DDR2: - BL8: 0x6 (not DDR2-1066) - # 0x7 (DDR2-1066) - BL4: 0x4 (not DDR2-1066), 0x5 (DDR2-1066) DDR3: - BL8 - 0x6 DDR4: - BL8: 5 + RD_PREAMBLE RD_PREAMBLE = 1 ( - # tCK write preamble), 2 (2tCK write preamble) LPDDR3: - BL8: 5 + RU(tDQSCK(max)/tCK) - RD(tDQSCK(min)/tCK) + RU(tODTon(max)/tC - # ) + # Cycles to hold ODT for a read command. The minimum supported value is 2. + # Recommended values: DDR2: - BL8: 0x6 (not DDR2-1066), 0x7 (DDR2-1066) - + # BL4: 0x4 (not DDR2-1066), 0x5 (DDR2-1066) DDR3: - BL8 - 0x6 DDR4: - BL8 + # : 5 + RD_PREAMBLE RD_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write p + # reamble) LPDDR3: - BL8: 5 + RU(tDQSCK(max)/tCK) - RD(tDQSCK(min)/tCK) + + # RU(tODTon(max)/tCK) # PSU_DDRC_ODTCFG_RD_ODT_HOLD 0x6 - # The delay, in clock cycles, from issuing a read command to setting ODT values associated with that command. ODT setting must - # emain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: - CL + AL - 4 (not DDR2-1066), - # CL + AL - 5 (DDR2-1066) If (CL + AL - 4 < 0), uMCTL2 does not support ODT for read operation. DDR3: - CL - CWL DDR4: - CL - C - # L - RD_PREAMBLE + WR_PREAMBLE + DFITMG1.dfi_t_cmd_lat (to adjust for CAL mode) WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK - # write preamble) RD_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) If (CL - CWL - RD_PREAMBLE + WR_PREAMBLE) < 0, - # uMCTL2 does not support ODT for read operation. LPDDR3: - RL + RD(tDQSCK(min)/tCK) - 1 - RU(tODTon(max)/tCK) + # The delay, in clock cycles, from issuing a read command to setting ODT v + # alues associated with that command. ODT setting must remain constant for + # the entire time that DQS is driven by the uMCTL2. Recommended values: D + # DR2: - CL + AL - 4 (not DDR2-1066), CL + AL - 5 (DDR2-1066) If (CL + AL + # - 4 < 0), uMCTL2 does not support ODT for read operation. DDR3: - CL - C + # WL DDR4: - CL - CWL - RD_PREAMBLE + WR_PREAMBLE + DFITMG1.dfi_t_cmd_lat + # (to adjust for CAL mode) WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK + # write preamble) RD_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write pre + # amble) If (CL - CWL - RD_PREAMBLE + WR_PREAMBLE) < 0, uMCTL2 does not su + # pport ODT for read operation. LPDDR3: - RL + RD(tDQSCK(min)/tCK) - 1 - R + # U(tODTon(max)/tCK) # PSU_DDRC_ODTCFG_RD_ODT_DELAY 0x0 # ODT Configuration Register @@ -2654,24 +3151,34 @@ set psu_ddr_init_data { mask_write 0XFD070240 0x0F1F0F7C 0x06000600 # Register : ODTMAP @ 0XFD070244

- # Indicates which remote ODTs must be turned on during a read from rank 1. Each rank has a remote ODT (in the SDRAM) which can - # e turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB - # etc. For each rank, set its bit to 1 to enable its ODT. Present only in configurations that have 2 or more ranks + # Indicates which remote ODTs must be turned on during a read from rank 1. + # Each rank has a remote ODT (in the SDRAM) which can be turned on by set + # ting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 i + # s controlled by bit next to the LSB, etc. For each rank, set its bit to + # 1 to enable its ODT. Present only in configurations that have 2 or more + # ranks # PSU_DDRC_ODTMAP_RANK1_RD_ODT 0x0 - # Indicates which remote ODTs must be turned on during a write to rank 1. Each rank has a remote ODT (in the SDRAM) which can b - # turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB, - # etc. For each rank, set its bit to 1 to enable its ODT. Present only in configurations that have 2 or more ranks + # Indicates which remote ODTs must be turned on during a write to rank 1. + # Each rank has a remote ODT (in the SDRAM) which can be turned on by sett + # ing the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is + # controlled by bit next to the LSB, etc. For each rank, set its bit to 1 + # to enable its ODT. Present only in configurations that have 2 or more r + # anks # PSU_DDRC_ODTMAP_RANK1_WR_ODT 0x0 - # Indicates which remote ODTs must be turned on during a read from rank 0. Each rank has a remote ODT (in the SDRAM) which can - # e turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB - # etc. For each rank, set its bit to 1 to enable its ODT. + # Indicates which remote ODTs must be turned on during a read from rank 0. + # Each rank has a remote ODT (in the SDRAM) which can be turned on by set + # ting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 i + # s controlled by bit next to the LSB, etc. For each rank, set its bit to + # 1 to enable its ODT. # PSU_DDRC_ODTMAP_RANK0_RD_ODT 0x0 - # Indicates which remote ODTs must be turned on during a write to rank 0. Each rank has a remote ODT (in the SDRAM) which can b - # turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB, - # etc. For each rank, set its bit to 1 to enable its ODT. + # Indicates which remote ODTs must be turned on during a write to rank 0. + # Each rank has a remote ODT (in the SDRAM) which can be turned on by sett + # ing the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is + # controlled by bit next to the LSB, etc. For each rank, set its bit to 1 + # to enable its ODT. # PSU_DDRC_ODTMAP_RANK0_WR_ODT 0x1 # ODT/Rank Map Register @@ -2679,41 +3186,57 @@ set psu_ddr_init_data { mask_write 0XFD070244 0x00003333 0x00000001 # Register : SCHED @ 0XFD070250

- # When the preferred transaction store is empty for these many clock cycles, switch to the alternate transaction store if it is - # non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write t - # ansaction store is the alternative store. When prefer write over read is set this is reversed. 0x0 is a legal value for this - # egister. When set to 0x0, the transaction store switching will happen immediately when the switching conditions become true. - # OR PERFORMANCE ONLY + # When the preferred transaction store is empty for these many clock cycle + # s, switch to the alternate transaction store if it is non-empty. The rea + # d transaction store (both high and low priority) is the default preferre + # d transaction store and the write transaction store is the alternative s + # tore. When prefer write over read is set this is reversed. 0x0 is a lega + # l value for this register. When set to 0x0, the transaction store switch + # ing will happen immediately when the switching conditions become true. F + # OR PERFORMANCE ONLY # PSU_DDRC_SCHED_RDWR_IDLE_GAP 0x1 # UNUSED # PSU_DDRC_SCHED_GO2CRITICAL_HYSTERESIS 0x0 - # Number of entries in the low priority transaction store is this value + 1. (MEMC_NO_OF_ENTRY - (SCHED.lpr_num_entries + 1)) i - # the number of entries available for the high priority transaction store. Setting this to maximum value allocates all entries - # to low priority transaction store. Setting this to 0 allocates 1 entry to low priority transaction store and the rest to high - # priority transaction store. Note: In ECC configurations, the numbers of write and low priority read credits issued is one les - # than in the non-ECC case. One entry each is reserved in the write and low-priority read CAMs for storing the RMW requests ar - # sing out of single bit error correction RMW operation. + # Number of entries in the low priority transaction store is this value + + # 1. (MEMC_NO_OF_ENTRY - (SCHED.lpr_num_entries + 1)) is the number of ent + # ries available for the high priority transaction store. Setting this to + # maximum value allocates all entries to low priority transaction store. S + # etting this to 0 allocates 1 entry to low priority transaction store and + # the rest to high priority transaction store. Note: In ECC configuration + # s, the numbers of write and low priority read credits issued is one less + # than in the non-ECC case. One entry each is reserved in the write and l + # ow-priority read CAMs for storing the RMW requests arising out of single + # bit error correction RMW operation. # PSU_DDRC_SCHED_LPR_NUM_ENTRIES 0x20 - # If true, bank is kept open only while there are page hit transactions available in the CAM to that bank. The last read or wri - # e command in the CAM with a bank and page hit will be executed with auto-precharge if SCHED1.pageclose_timer=0. Even if this - # egister set to 1 and SCHED1.pageclose_timer is set to 0, explicit precharge (and not auto-precharge) may be issued in some ca - # es where there is a mode switch between Write and Read or between LPR and HPR. The Read and Write commands that are executed - # s part of the ECC scrub requests are also executed without auto-precharge. If false, the bank remains open until there is a n - # ed to close it (to open a different page, or for page timeout or refresh timeout) - also known as open page policy. The open - # age policy can be overridden by setting the per-command-autopre bit on the HIF interface (hif_cmd_autopre). The pageclose fea - # ure provids a midway between Open and Close page policies. FOR PERFORMANCE ONLY. + # If true, bank is kept open only while there are page hit transactions av + # ailable in the CAM to that bank. The last read or write command in the C + # AM with a bank and page hit will be executed with auto-precharge if SCHE + # D1.pageclose_timer=0. Even if this register set to 1 and SCHED1.pageclos + # e_timer is set to 0, explicit precharge (and not auto-precharge) may be + # issued in some cases where there is a mode switch between Write and Read + # or between LPR and HPR. The Read and Write commands that are executed a + # s part of the ECC scrub requests are also executed without auto-precharg + # e. If false, the bank remains open until there is a need to close it (to + # open a different page, or for page timeout or refresh timeout) - also k + # nown as open page policy. The open page policy can be overridden by sett + # ing the per-command-autopre bit on the HIF interface (hif_cmd_autopre). + # The pageclose feature provids a midway between Open and Close page polic + # ies. FOR PERFORMANCE ONLY. # PSU_DDRC_SCHED_PAGECLOSE 0x0 # If set then the bank selector prefers writes over reads. FOR DEBUG ONLY. # PSU_DDRC_SCHED_PREFER_WRITE 0x0 - # Active low signal. When asserted ('0'), all incoming transactions are forced to low priority. This implies that all High Prio - # ity Read (HPR) and Variable Priority Read commands (VPR) will be treated as Low Priority Read (LPR) commands. On the write si - # e, all Variable Priority Write (VPW) commands will be treated as Normal Priority Write (NPW) commands. Forcing the incoming t - # ansactions to low priority implicitly turns off Bypass path for read commands. FOR PERFORMANCE ONLY. + # Active low signal. When asserted ('0'), all incoming transactions are fo + # rced to low priority. This implies that all High Priority Read (HPR) and + # Variable Priority Read commands (VPR) will be treated as Low Priority R + # ead (LPR) commands. On the write side, all Variable Priority Write (VPW) + # commands will be treated as Normal Priority Write (NPW) commands. Forci + # ng the incoming transactions to low priority implicitly turns off Bypass + # path for read commands. FOR PERFORMANCE ONLY. # PSU_DDRC_SCHED_FORCE_LOW_PRI_N 0x1 # Scheduler Control Register @@ -2721,13 +3244,16 @@ set psu_ddr_init_data { mask_write 0XFD070250 0x7FFF3F07 0x01002001 # Register : PERFLPR1 @ 0XFD070264

- # Number of transactions that are serviced once the LPR queue goes critical is the smaller of: - (a) This number - (b) Number o - # transactions available. Unit: Transaction. FOR PERFORMANCE ONLY. + # Number of transactions that are serviced once the LPR queue goes critica + # l is the smaller of: - (a) This number - (b) Number of transactions avai + # lable. Unit: Transaction. FOR PERFORMANCE ONLY. # PSU_DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH 0x8 - # Number of clocks that the LPR queue can be starved before it goes critical. The minimum valid functional value for this regis - # er is 0x1. Programming it to 0x0 will disable the starvation functionality; during normal operation, this function should not - # be disabled as it will cause excessive latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY. + # Number of clocks that the LPR queue can be starved before it goes critic + # al. The minimum valid functional value for this register is 0x1. Program + # ming it to 0x0 will disable the starvation functionality; during normal + # operation, this function should not be disabled as it will cause excessi + # ve latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY. # PSU_DDRC_PERFLPR1_LPR_MAX_STARVE 0x40 # Low Priority Read CAM Register 1 @@ -2735,24 +3261,126 @@ set psu_ddr_init_data { mask_write 0XFD070264 0xFF00FFFF 0x08000040 # Register : PERFWR1 @ 0XFD07026C

- # Number of transactions that are serviced once the WR queue goes critical is the smaller of: - (a) This number - (b) Number of - # transactions available. Unit: Transaction. FOR PERFORMANCE ONLY. + # Number of transactions that are serviced once the WR queue goes critical + # is the smaller of: - (a) This number - (b) Number of transactions avail + # able. Unit: Transaction. FOR PERFORMANCE ONLY. # PSU_DDRC_PERFWR1_W_XACT_RUN_LENGTH 0x8 - # Number of clocks that the WR queue can be starved before it goes critical. The minimum valid functional value for this regist - # r is 0x1. Programming it to 0x0 will disable the starvation functionality; during normal operation, this function should not - # e disabled as it will cause excessive latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY. + # Number of clocks that the WR queue can be starved before it goes critica + # l. The minimum valid functional value for this register is 0x1. Programm + # ing it to 0x0 will disable the starvation functionality; during normal o + # peration, this function should not be disabled as it will cause excessiv + # e latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY. # PSU_DDRC_PERFWR1_W_MAX_STARVE 0x40 # Write CAM Register 1 #(OFFSET, MASK, VALUE) (0XFD07026C, 0xFF00FFFFU ,0x08000040U) */ mask_write 0XFD07026C 0xFF00FFFF 0x08000040 + # Register : DQMAP0 @ 0XFD070280

+ + # DQ nibble map for DQ bits [12-15] Present only in designs configured to + # support DDR4. + # PSU_DDRC_DQMAP0_DQ_NIBBLE_MAP_12_15 0x0 + + # DQ nibble map for DQ bits [8-11] Present only in designs configured to s + # upport DDR4. + # PSU_DDRC_DQMAP0_DQ_NIBBLE_MAP_8_11 0x0 + + # DQ nibble map for DQ bits [4-7] Present only in designs configured to su + # pport DDR4. + # PSU_DDRC_DQMAP0_DQ_NIBBLE_MAP_4_7 0x0 + + # DQ nibble map for DQ bits [0-3] Present only in designs configured to su + # pport DDR4. + # PSU_DDRC_DQMAP0_DQ_NIBBLE_MAP_0_3 0x0 + + # DQ Map Register 0 + #(OFFSET, MASK, VALUE) (0XFD070280, 0xFFFFFFFFU ,0x00000000U) */ + mask_write 0XFD070280 0xFFFFFFFF 0x00000000 + # Register : DQMAP1 @ 0XFD070284

+ + # DQ nibble map for DQ bits [28-31] Present only in designs configured to + # support DDR4. + # PSU_DDRC_DQMAP1_DQ_NIBBLE_MAP_28_31 0x0 + + # DQ nibble map for DQ bits [24-27] Present only in designs configured to + # support DDR4. + # PSU_DDRC_DQMAP1_DQ_NIBBLE_MAP_24_27 0x0 + + # DQ nibble map for DQ bits [20-23] Present only in designs configured to + # support DDR4. + # PSU_DDRC_DQMAP1_DQ_NIBBLE_MAP_20_23 0x0 + + # DQ nibble map for DQ bits [16-19] Present only in designs configured to + # support DDR4. + # PSU_DDRC_DQMAP1_DQ_NIBBLE_MAP_16_19 0x0 + + # DQ Map Register 1 + #(OFFSET, MASK, VALUE) (0XFD070284, 0xFFFFFFFFU ,0x00000000U) */ + mask_write 0XFD070284 0xFFFFFFFF 0x00000000 + # Register : DQMAP2 @ 0XFD070288

+ + # DQ nibble map for DQ bits [44-47] Present only in designs configured to + # support DDR4. + # PSU_DDRC_DQMAP2_DQ_NIBBLE_MAP_44_47 0x0 + + # DQ nibble map for DQ bits [40-43] Present only in designs configured to + # support DDR4. + # PSU_DDRC_DQMAP2_DQ_NIBBLE_MAP_40_43 0x0 + + # DQ nibble map for DQ bits [36-39] Present only in designs configured to + # support DDR4. + # PSU_DDRC_DQMAP2_DQ_NIBBLE_MAP_36_39 0x0 + + # DQ nibble map for DQ bits [32-35] Present only in designs configured to + # support DDR4. + # PSU_DDRC_DQMAP2_DQ_NIBBLE_MAP_32_35 0x0 + + # DQ Map Register 2 + #(OFFSET, MASK, VALUE) (0XFD070288, 0xFFFFFFFFU ,0x00000000U) */ + mask_write 0XFD070288 0xFFFFFFFF 0x00000000 + # Register : DQMAP3 @ 0XFD07028C

+ + # DQ nibble map for DQ bits [60-63] Present only in designs configured to + # support DDR4. + # PSU_DDRC_DQMAP3_DQ_NIBBLE_MAP_60_63 0x0 + + # DQ nibble map for DQ bits [56-59] Present only in designs configured to + # support DDR4. + # PSU_DDRC_DQMAP3_DQ_NIBBLE_MAP_56_59 0x0 + + # DQ nibble map for DQ bits [52-55] Present only in designs configured to + # support DDR4. + # PSU_DDRC_DQMAP3_DQ_NIBBLE_MAP_52_55 0x0 + + # DQ nibble map for DQ bits [48-51] Present only in designs configured to + # support DDR4. + # PSU_DDRC_DQMAP3_DQ_NIBBLE_MAP_48_51 0x0 + + # DQ Map Register 3 + #(OFFSET, MASK, VALUE) (0XFD07028C, 0xFFFFFFFFU ,0x00000000U) */ + mask_write 0XFD07028C 0xFFFFFFFF 0x00000000 + # Register : DQMAP4 @ 0XFD070290

+ + # DQ nibble map for DIMM ECC check bits [4-7] Present only in designs conf + # igured to support DDR4. + # PSU_DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_4_7 0x0 + + # DQ nibble map for DIMM ECC check bits [0-3] Present only in designs conf + # igured to support DDR4. + # PSU_DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_0_3 0x0 + + # DQ Map Register 4 + #(OFFSET, MASK, VALUE) (0XFD070290, 0x0000FFFFU ,0x00000000U) */ + mask_write 0XFD070290 0x0000FFFF 0x00000000 # Register : DQMAP5 @ 0XFD070294

- # All even ranks have the same DQ mapping controled by DQMAP0-4 register as rank 0. This register provides DQ swap function for - # all odd ranks to support CRC feature. rank based DQ swapping is: swap bit 0 with 1, swap bit 2 with 3, swap bit 4 with 5 and - # wap bit 6 with 7. 1: Disable rank based DQ swapping 0: Enable rank based DQ swapping Present only in designs configured to su - # port DDR4. + # All even ranks have the same DQ mapping controled by DQMAP0-4 register a + # s rank 0. This register provides DQ swap function for all odd ranks to s + # upport CRC feature. rank based DQ swapping is: swap bit 0 with 1, swap b + # it 2 with 3, swap bit 4 with 5 and swap bit 6 with 7. 1: Disable rank ba + # sed DQ swapping 0: Enable rank based DQ swapping Present only in designs + # configured to support DDR4. # PSU_DDRC_DQMAP5_DIS_DQ_RANK_SWAP 0x1 # DQ Map Register 5 @@ -2760,9 +3388,12 @@ set psu_ddr_init_data { mask_write 0XFD070294 0x00000001 0x00000001 # Register : DBG0 @ 0XFD070300

- # When this is set to '0', auto-precharge is disabled for the flushed command in a collision case. Collision cases are write fo - # lowed by read to same address, read followed by write to same address, or write followed by write to same address with DBG0.d - # s_wc bit = 1 (where same address comparisons exclude the two address bits representing critical word). FOR DEBUG ONLY. + # When this is set to '0', auto-precharge is disabled for the flushed comm + # and in a collision case. Collision cases are write followed by read to s + # ame address, read followed by write to same address, or write followed b + # y write to same address with DBG0.dis_wc bit = 1 (where same address com + # parisons exclude the two address bits representing critical word). FOR D + # EBUG ONLY. # PSU_DDRC_DBG0_DIS_COLLISION_PAGE_OPT 0x0 # When 1, disable write combine. FOR DEBUG ONLY @@ -2773,34 +3404,47 @@ set psu_ddr_init_data { mask_write 0XFD070300 0x00000011 0x00000000 # Register : DBGCMD @ 0XFD07030C

- # Setting this register bit to 1 allows refresh and ZQCS commands to be triggered from hardware via the IOs ext_*. If set to 1, - # the fields DBGCMD.zq_calib_short and DBGCMD.rank*_refresh have no function, and are ignored by the uMCTL2 logic. Setting this - # register bit to 0 allows refresh and ZQCS to be triggered from software, via the fields DBGCMD.zq_calib_short and DBGCMD.rank - # _refresh. If set to 0, the hardware pins ext_* have no function, and are ignored by the uMCTL2 logic. This register is static - # and may only be changed when the DDRC reset signal, core_ddrc_rstn, is asserted (0). + # Setting this register bit to 1 allows refresh and ZQCS commands to be tr + # iggered from hardware via the IOs ext_*. If set to 1, the fields DBGCMD. + # zq_calib_short and DBGCMD.rank*_refresh have no function, and are ignore + # d by the uMCTL2 logic. Setting this register bit to 0 allows refresh and + # ZQCS to be triggered from software, via the fields DBGCMD.zq_calib_shor + # t and DBGCMD.rank*_refresh. If set to 0, the hardware pins ext_* have no + # function, and are ignored by the uMCTL2 logic. This register is static, + # and may only be changed when the DDRC reset signal, core_ddrc_rstn, is + # asserted (0). # PSU_DDRC_DBGCMD_HW_REF_ZQ_EN 0x0 - # Setting this register bit to 1 indicates to the uMCTL2 to issue a dfi_ctrlupd_req to the PHY. When this request is stored in - # he uMCTL2, the bit is automatically cleared. This operation must only be performed when DFIUPD0.dis_auto_ctrlupd=1. + # Setting this register bit to 1 indicates to the uMCTL2 to issue a dfi_ct + # rlupd_req to the PHY. When this request is stored in the uMCTL2, the bit + # is automatically cleared. This operation must only be performed when DF + # IUPD0.dis_auto_ctrlupd=1. # PSU_DDRC_DBGCMD_CTRLUPD 0x0 - # Setting this register bit to 1 indicates to the uMCTL2 to issue a ZQCS (ZQ calibration short)/MPC(ZQ calibration) command to - # he SDRAM. When this request is stored in the uMCTL2, the bit is automatically cleared. This operation can be performed only w - # en ZQCTL0.dis_auto_zq=1. It is recommended NOT to set this register bit if in Init operating mode. This register bit is ignor - # d when in Self-Refresh(except LPDDR4) and SR-Powerdown(LPDDR4) and Deep power-down operating modes and Maximum Power Saving M - # de. + # Setting this register bit to 1 indicates to the uMCTL2 to issue a ZQCS ( + # ZQ calibration short)/MPC(ZQ calibration) command to the SDRAM. When thi + # s request is stored in the uMCTL2, the bit is automatically cleared. Thi + # s operation can be performed only when ZQCTL0.dis_auto_zq=1. It is recom + # mended NOT to set this register bit if in Init operating mode. This regi + # ster bit is ignored when in Self-Refresh(except LPDDR4) and SR-Powerdown + # (LPDDR4) and Deep power-down operating modes and Maximum Power Saving Mo + # de. # PSU_DDRC_DBGCMD_ZQ_CALIB_SHORT 0x0 - # Setting this register bit to 1 indicates to the uMCTL2 to issue a refresh to rank 1. Writing to this bit causes DBGSTAT.rank1 - # refresh_busy to be set. When DBGSTAT.rank1_refresh_busy is cleared, the command has been stored in uMCTL2. This operation can - # be performed only when RFSHCTL3.dis_auto_refresh=1. It is recommended NOT to set this register bit if in Init or Deep power-d - # wn operating modes or Maximum Power Saving Mode. + # Setting this register bit to 1 indicates to the uMCTL2 to issue a refres + # h to rank 1. Writing to this bit causes DBGSTAT.rank1_refresh_busy to be + # set. When DBGSTAT.rank1_refresh_busy is cleared, the command has been s + # tored in uMCTL2. This operation can be performed only when RFSHCTL3.dis_ + # auto_refresh=1. It is recommended NOT to set this register bit if in Ini + # t or Deep power-down operating modes or Maximum Power Saving Mode. # PSU_DDRC_DBGCMD_RANK1_REFRESH 0x0 - # Setting this register bit to 1 indicates to the uMCTL2 to issue a refresh to rank 0. Writing to this bit causes DBGSTAT.rank0 - # refresh_busy to be set. When DBGSTAT.rank0_refresh_busy is cleared, the command has been stored in uMCTL2. This operation can - # be performed only when RFSHCTL3.dis_auto_refresh=1. It is recommended NOT to set this register bit if in Init or Deep power-d - # wn operating modes or Maximum Power Saving Mode. + # Setting this register bit to 1 indicates to the uMCTL2 to issue a refres + # h to rank 0. Writing to this bit causes DBGSTAT.rank0_refresh_busy to be + # set. When DBGSTAT.rank0_refresh_busy is cleared, the command has been s + # tored in uMCTL2. This operation can be performed only when RFSHCTL3.dis_ + # auto_refresh=1. It is recommended NOT to set this register bit if in Ini + # t or Deep power-down operating modes or Maximum Power Saving Mode. # PSU_DDRC_DBGCMD_RANK0_REFRESH 0x0 # Command Debug Register @@ -2808,8 +3452,9 @@ set psu_ddr_init_data { mask_write 0XFD07030C 0x80000033 0x00000000 # Register : SWCTL @ 0XFD070320

- # Enable quasi-dynamic register programming outside reset. Program register to 0 to enable quasi-dynamic programming. Set back - # egister to 1 once programming is done. + # Enable quasi-dynamic register programming outside reset. Program registe + # r to 0 to enable quasi-dynamic programming. Set back register to 1 once + # programming is done. # PSU_DDRC_SWCTL_SW_DONE 0x0 # Software register programming control enable @@ -2817,25 +3462,34 @@ set psu_ddr_init_data { mask_write 0XFD070320 0x00000001 0x00000000 # Register : PCCFG @ 0XFD070400

- # Burst length expansion mode. By default (i.e. bl_exp_mode==0) XPI expands every AXI burst into multiple HIF commands, using t - # e memory burst length as a unit. If set to 1, then XPI will use half of the memory burst length as a unit. This applies to bo - # h reads and writes. When MSTR.data_bus_width==00, setting bl_exp_mode to 1 has no effect. This can be used in cases where Par - # ial Writes is enabled (UMCTL2_PARTIAL_WR=1) and DBG0.dis_wc=1, in order to avoid or minimize t_ccd_l penalty in DDR4 and t_cc - # _mw penalty in LPDDR4. Note that if DBICTL.reg_ddrc_dm_en=0, functionality is not supported in the following cases: - UMCTL2_ - # ARTIAL_WR=0 - UMCTL2_PARTIAL_WR=1, MSTR.reg_ddrc_data_bus_width=01, MEMC_BURST_LENGTH=8 and MSTR.reg_ddrc_burst_rdwr=1000 (LP - # DR4 only) - UMCTL2_PARTIAL_WR=1, MSTR.reg_ddrc_data_bus_width=01, MEMC_BURST_LENGTH=4 and MSTR.reg_ddrc_burst_rdwr=0100 (DDR4 - # only), with either MSTR.reg_ddrc_burstchop=0 or CRCPARCTL1.reg_ddrc_crc_enable=1 Functionality is also not supported if Share - # -AC is enabled + # Burst length expansion mode. By default (i.e. bl_exp_mode==0) XPI expand + # s every AXI burst into multiple HIF commands, using the memory burst len + # gth as a unit. If set to 1, then XPI will use half of the memory burst l + # ength as a unit. This applies to both reads and writes. When MSTR.data_b + # us_width==00, setting bl_exp_mode to 1 has no effect. This can be used i + # n cases where Partial Writes is enabled (UMCTL2_PARTIAL_WR=1) and DBG0.d + # is_wc=1, in order to avoid or minimize t_ccd_l penalty in DDR4 and t_ccd + # _mw penalty in LPDDR4. Note that if DBICTL.reg_ddrc_dm_en=0, functionali + # ty is not supported in the following cases: - UMCTL2_PARTIAL_WR=0 - UMCT + # L2_PARTIAL_WR=1, MSTR.reg_ddrc_data_bus_width=01, MEMC_BURST_LENGTH=8 an + # d MSTR.reg_ddrc_burst_rdwr=1000 (LPDDR4 only) - UMCTL2_PARTIAL_WR=1, MST + # R.reg_ddrc_data_bus_width=01, MEMC_BURST_LENGTH=4 and MSTR.reg_ddrc_burs + # t_rdwr=0100 (DDR4 only), with either MSTR.reg_ddrc_burstchop=0 or CRCPAR + # CTL1.reg_ddrc_crc_enable=1 Functionality is also not supported if Shared + # -AC is enabled # PSU_DDRC_PCCFG_BL_EXP_MODE 0x0 - # Page match four limit. If set to 1, limits the number of consecutive same page DDRC transactions that can be granted by the P - # rt Arbiter to four when Page Match feature is enabled. If set to 0, there is no limit imposed on number of consecutive same p - # ge DDRC transactions. + # Page match four limit. If set to 1, limits the number of consecutive sam + # e page DDRC transactions that can be granted by the Port Arbiter to four + # when Page Match feature is enabled. If set to 0, there is no limit impo + # sed on number of consecutive same page DDRC transactions. # PSU_DDRC_PCCFG_PAGEMATCH_LIMIT 0x0 - # If set to 1 (enabled), sets co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals going to DDRC based - # n urgent input (awurgent, arurgent) coming from AXI master. If set to 0 (disabled), co_gs_go2critical_wr and co_gs_go2critica - # _lpr/co_gs_go2critical_hpr signals at DDRC are driven to 1b'0. + # If set to 1 (enabled), sets co_gs_go2critical_wr and co_gs_go2critical_l + # pr/co_gs_go2critical_hpr signals going to DDRC based on urgent input (aw + # urgent, arurgent) coming from AXI master. If set to 0 (disabled), co_gs_ + # go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals a + # t DDRC are driven to 1b'0. # PSU_DDRC_PCCFG_GO2CRITICAL_EN 0x1 # Port Common Configuration Register @@ -2843,30 +3497,41 @@ set psu_ddr_init_data { mask_write 0XFD070400 0x00000111 0x00000001 # Register : PCFGR_0 @ 0XFD070404

- # If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - # d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - # imit register. + # If set to 1, enables the Page Match feature. If enabled, once a requesti + # ng port is granted, the port is continued to be granted if the following + # immediate commands are to the same memory page (same bank and same row) + # . See also related PCCFG.pagematch_limit register. # PSU_DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN 0x0 - # If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por - # becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG. - # o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add - # ess handshaking (it is not associated with any particular command). + # If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + # bled and arurgent is asserted by the master, that port becomes the highe + # st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + # RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + # urgent signal can be asserted anytime and as long as required which is i + # ndependent of address handshaking (it is not associated with any particu + # lar command). # PSU_DDRC_PCFGR_0_RD_PORT_URGENT_EN 0x1 # If set to 1, enables aging function for the read channel of the port. # PSU_DDRC_PCFGR_0_RD_PORT_AGING_EN 0x0 - # Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g - # ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - # he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority - # will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre - # ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the - # aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st - # ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w - # ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D - # RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: - # he two LSBs of this register field are tied internally to 2'b00. + # Determines the initial load value of read aging counters. These counters + # will be parallel loaded after reset, or after each grant to the corresp + # onding port. The aging counters down-count every clock cycle where the p + # ort is requesting but not granted. The higher significant 5-bits of the + # read aging counter sets the priority of the read channel of a given port + # . Port's priority will increase as the higher significant 5-bits of the + # counter starts to decrease. When the aging counter becomes 0, the corres + # ponding port channel will have the highest priority level (timeout condi + # tion - Priority0). For multi-port configurations, the aging counters can + # not be used to set port priorities when external dynamic priority inputs + # (arqos) are enabled (timeout is still applicable). For single port conf + # igurations, the aging counters are only used when they timeout (become 0 + # ) to force read-write direction switching. In this case, external dynami + # c priority input, arqos (for reads only) can still be used to set the DD + # RC read priority (2 priority levels: low priority read - LPR, high prior + # ity read - HPR) on a command by command basis. Note: The two LSBs of thi + # s register field are tied internally to 2'b00. # PSU_DDRC_PCFGR_0_RD_PORT_PRIORITY 0xf # Port n Configuration Read Register @@ -2874,33 +3539,42 @@ set psu_ddr_init_data { mask_write 0XFD070404 0x000073FF 0x0000200F # Register : PCFGW_0 @ 0XFD070408

- # If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - # d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - # imit register. - # PSU_DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN 0x1 + # If set to 1, enables the Page Match feature. If enabled, once a requesti + # ng port is granted, the port is continued to be granted if the following + # immediate commands are to the same memory page (same bank and same row) + # . See also related PCCFG.pagematch_limit register. + # PSU_DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN 0x0 - # If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por - # becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register - # Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is - # not associated with any particular command). + # If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + # bled and awurgent is asserted by the master, that port becomes the highe + # st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + # ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + # serted anytime and as long as required which is independent of address h + # andshaking (it is not associated with any particular command). # PSU_DDRC_PCFGW_0_WR_PORT_URGENT_EN 0x1 # If set to 1, enables aging function for the write channel of the port. # PSU_DDRC_PCFGW_0_WR_PORT_AGING_EN 0x0 - # Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each - # rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - # The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port - # s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0 - # the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno - # be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For - # ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch - # ng. Note: The two LSBs of this register field are tied internally to 2'b00. + # Determines the initial load value of write aging counters. These counter + # s will be parallel loaded after reset, or after each grant to the corres + # ponding port. The aging counters down-count every clock cycle where the + # port is requesting but not granted. The higher significant 5-bits of the + # write aging counter sets the initial priority of the write channel of a + # given port. Port's priority will increase as the higher significant 5-b + # its of the counter starts to decrease. When the aging counter becomes 0, + # the corresponding port channel will have the highest priority level. Fo + # r multi-port configurations, the aging counters cannot be used to set po + # rt priorities when external dynamic priority inputs (awqos) are enabled + # (timeout is still applicable). For single port configurations, the aging + # counters are only used when they timeout (become 0) to force read-write + # direction switching. Note: The two LSBs of this register field are tied + # internally to 2'b00. # PSU_DDRC_PCFGW_0_WR_PORT_PRIORITY 0xf # Port n Configuration Write Register - #(OFFSET, MASK, VALUE) (0XFD070408, 0x000073FFU ,0x0000600FU) */ - mask_write 0XFD070408 0x000073FF 0x0000600F + #(OFFSET, MASK, VALUE) (0XFD070408, 0x000073FFU ,0x0000200FU) */ + mask_write 0XFD070408 0x000073FF 0x0000200F # Register : PCTRL_0 @ 0XFD070490

# Enables port n. @@ -2911,20 +3585,28 @@ set psu_ddr_init_data { mask_write 0XFD070490 0x00000001 0x00000001 # Register : PCFGQOS0_0 @ 0XFD070494

- # This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf - # gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is - # disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. + # This bitfield indicates the traffic class of region 1. Valid values are: + # 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + # maps to the blue address queue. In this case, valid values are 0: LPR a + # nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + # ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + # traffic. # PSU_DDRC_PCFGQOS0_0_RQOS_MAP_REGION1 0x2 - # This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi - # urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i - # disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. + # This bitfield indicates the traffic class of region 0. Valid values are: + # 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + # maps to the blue address queue. In this case, valid values are: 0: LPR + # and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + # affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + # traffic. # PSU_DDRC_PCFGQOS0_0_RQOS_MAP_REGION0 0x0 - # Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d - # al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio - # ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc - # values. + # Separation level1 indicating the end of region0 mapping; start of region + # 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + # (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + # lues are used directly as port priorities, where the higher the value co + # rresponds to higher port priority. All of the map_level* registers must + # be set to distinct values. # PSU_DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1 0xb # Port n Read QoS Configuration Register 0 @@ -2932,10 +3614,12 @@ set psu_ddr_init_data { mask_write 0XFD070494 0x0033000F 0x0020000B # Register : PCFGQOS1_0 @ 0XFD070498

- # Specifies the timeout value for transactions mapped to the red address queue. + # Specifies the timeout value for transactions mapped to the red address q + # ueue. # PSU_DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR 0x0 - # Specifies the timeout value for transactions mapped to the blue address queue. + # Specifies the timeout value for transactions mapped to the blue address + # queue. # PSU_DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB 0x0 # Port n Read QoS Configuration Register 1 @@ -2943,30 +3627,41 @@ set psu_ddr_init_data { mask_write 0XFD070498 0x07FF07FF 0x00000000 # Register : PCFGR_1 @ 0XFD0704B4

- # If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - # d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - # imit register. + # If set to 1, enables the Page Match feature. If enabled, once a requesti + # ng port is granted, the port is continued to be granted if the following + # immediate commands are to the same memory page (same bank and same row) + # . See also related PCCFG.pagematch_limit register. # PSU_DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN 0x0 - # If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por - # becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG. - # o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add - # ess handshaking (it is not associated with any particular command). + # If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + # bled and arurgent is asserted by the master, that port becomes the highe + # st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + # RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + # urgent signal can be asserted anytime and as long as required which is i + # ndependent of address handshaking (it is not associated with any particu + # lar command). # PSU_DDRC_PCFGR_1_RD_PORT_URGENT_EN 0x1 # If set to 1, enables aging function for the read channel of the port. # PSU_DDRC_PCFGR_1_RD_PORT_AGING_EN 0x0 - # Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g - # ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - # he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority - # will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre - # ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the - # aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st - # ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w - # ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D - # RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: - # he two LSBs of this register field are tied internally to 2'b00. + # Determines the initial load value of read aging counters. These counters + # will be parallel loaded after reset, or after each grant to the corresp + # onding port. The aging counters down-count every clock cycle where the p + # ort is requesting but not granted. The higher significant 5-bits of the + # read aging counter sets the priority of the read channel of a given port + # . Port's priority will increase as the higher significant 5-bits of the + # counter starts to decrease. When the aging counter becomes 0, the corres + # ponding port channel will have the highest priority level (timeout condi + # tion - Priority0). For multi-port configurations, the aging counters can + # not be used to set port priorities when external dynamic priority inputs + # (arqos) are enabled (timeout is still applicable). For single port conf + # igurations, the aging counters are only used when they timeout (become 0 + # ) to force read-write direction switching. In this case, external dynami + # c priority input, arqos (for reads only) can still be used to set the DD + # RC read priority (2 priority levels: low priority read - LPR, high prior + # ity read - HPR) on a command by command basis. Note: The two LSBs of thi + # s register field are tied internally to 2'b00. # PSU_DDRC_PCFGR_1_RD_PORT_PRIORITY 0xf # Port n Configuration Read Register @@ -2974,33 +3669,42 @@ set psu_ddr_init_data { mask_write 0XFD0704B4 0x000073FF 0x0000200F # Register : PCFGW_1 @ 0XFD0704B8

- # If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - # d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - # imit register. - # PSU_DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN 0x1 + # If set to 1, enables the Page Match feature. If enabled, once a requesti + # ng port is granted, the port is continued to be granted if the following + # immediate commands are to the same memory page (same bank and same row) + # . See also related PCCFG.pagematch_limit register. + # PSU_DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN 0x0 - # If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por - # becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register - # Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is - # not associated with any particular command). + # If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + # bled and awurgent is asserted by the master, that port becomes the highe + # st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + # ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + # serted anytime and as long as required which is independent of address h + # andshaking (it is not associated with any particular command). # PSU_DDRC_PCFGW_1_WR_PORT_URGENT_EN 0x1 # If set to 1, enables aging function for the write channel of the port. # PSU_DDRC_PCFGW_1_WR_PORT_AGING_EN 0x0 - # Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each - # rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - # The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port - # s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0 - # the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno - # be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For - # ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch - # ng. Note: The two LSBs of this register field are tied internally to 2'b00. + # Determines the initial load value of write aging counters. These counter + # s will be parallel loaded after reset, or after each grant to the corres + # ponding port. The aging counters down-count every clock cycle where the + # port is requesting but not granted. The higher significant 5-bits of the + # write aging counter sets the initial priority of the write channel of a + # given port. Port's priority will increase as the higher significant 5-b + # its of the counter starts to decrease. When the aging counter becomes 0, + # the corresponding port channel will have the highest priority level. Fo + # r multi-port configurations, the aging counters cannot be used to set po + # rt priorities when external dynamic priority inputs (awqos) are enabled + # (timeout is still applicable). For single port configurations, the aging + # counters are only used when they timeout (become 0) to force read-write + # direction switching. Note: The two LSBs of this register field are tied + # internally to 2'b00. # PSU_DDRC_PCFGW_1_WR_PORT_PRIORITY 0xf # Port n Configuration Write Register - #(OFFSET, MASK, VALUE) (0XFD0704B8, 0x000073FFU ,0x0000600FU) */ - mask_write 0XFD0704B8 0x000073FF 0x0000600F + #(OFFSET, MASK, VALUE) (0XFD0704B8, 0x000073FFU ,0x0000200FU) */ + mask_write 0XFD0704B8 0x000073FF 0x0000200F # Register : PCTRL_1 @ 0XFD070540

# Enables port n. @@ -3011,31 +3715,43 @@ set psu_ddr_init_data { mask_write 0XFD070540 0x00000001 0x00000001 # Register : PCFGQOS0_1 @ 0XFD070544

- # This bitfield indicates the traffic class of region2. For dual address queue configurations, region2 maps to the red address - # ueue. Valid values are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and traffic class of region2 - # s set to 1 (VPR), VPR traffic is aliased to LPR traffic. + # This bitfield indicates the traffic class of region2. For dual address q + # ueue configurations, region2 maps to the red address queue. Valid values + # are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN + # = 0) and traffic class of region2 is set to 1 (VPR), VPR traffic is ali + # ased to LPR traffic. # PSU_DDRC_PCFGQOS0_1_RQOS_MAP_REGION2 0x2 - # This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf - # gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is - # disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. + # This bitfield indicates the traffic class of region 1. Valid values are: + # 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + # maps to the blue address queue. In this case, valid values are 0: LPR a + # nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + # ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + # traffic. # PSU_DDRC_PCFGQOS0_1_RQOS_MAP_REGION1 0x0 - # This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi - # urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i - # disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. + # This bitfield indicates the traffic class of region 0. Valid values are: + # 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + # maps to the blue address queue. In this case, valid values are: 0: LPR + # and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + # affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + # traffic. # PSU_DDRC_PCFGQOS0_1_RQOS_MAP_REGION0 0x0 - # Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (le - # el1 + 1) to 14 which corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note that for PA, arqos values are used - # directly as port priorities, where the higher the value corresponds to higher port priority. All of the map_level* registers - # ust be set to distinct values. + # Separation level2 indicating the end of region1 mapping; start of region + # 1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 whi + # ch corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note + # that for PA, arqos values are used directly as port priorities, where t + # he higher the value corresponds to higher port priority. All of the map_ + # level* registers must be set to distinct values. # PSU_DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2 0xb - # Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d - # al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio - # ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc - # values. + # Separation level1 indicating the end of region0 mapping; start of region + # 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + # (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + # lues are used directly as port priorities, where the higher the value co + # rresponds to higher port priority. All of the map_level* registers must + # be set to distinct values. # PSU_DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1 0x3 # Port n Read QoS Configuration Register 0 @@ -3043,10 +3759,12 @@ set psu_ddr_init_data { mask_write 0XFD070544 0x03330F0F 0x02000B03 # Register : PCFGQOS1_1 @ 0XFD070548

- # Specifies the timeout value for transactions mapped to the red address queue. + # Specifies the timeout value for transactions mapped to the red address q + # ueue. # PSU_DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR 0x0 - # Specifies the timeout value for transactions mapped to the blue address queue. + # Specifies the timeout value for transactions mapped to the blue address + # queue. # PSU_DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB 0x0 # Port n Read QoS Configuration Register 1 @@ -3054,30 +3772,41 @@ set psu_ddr_init_data { mask_write 0XFD070548 0x07FF07FF 0x00000000 # Register : PCFGR_2 @ 0XFD070564

- # If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - # d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - # imit register. + # If set to 1, enables the Page Match feature. If enabled, once a requesti + # ng port is granted, the port is continued to be granted if the following + # immediate commands are to the same memory page (same bank and same row) + # . See also related PCCFG.pagematch_limit register. # PSU_DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN 0x0 - # If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por - # becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG. - # o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add - # ess handshaking (it is not associated with any particular command). + # If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + # bled and arurgent is asserted by the master, that port becomes the highe + # st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + # RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + # urgent signal can be asserted anytime and as long as required which is i + # ndependent of address handshaking (it is not associated with any particu + # lar command). # PSU_DDRC_PCFGR_2_RD_PORT_URGENT_EN 0x1 # If set to 1, enables aging function for the read channel of the port. # PSU_DDRC_PCFGR_2_RD_PORT_AGING_EN 0x0 - # Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g - # ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - # he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority - # will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre - # ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the - # aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st - # ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w - # ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D - # RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: - # he two LSBs of this register field are tied internally to 2'b00. + # Determines the initial load value of read aging counters. These counters + # will be parallel loaded after reset, or after each grant to the corresp + # onding port. The aging counters down-count every clock cycle where the p + # ort is requesting but not granted. The higher significant 5-bits of the + # read aging counter sets the priority of the read channel of a given port + # . Port's priority will increase as the higher significant 5-bits of the + # counter starts to decrease. When the aging counter becomes 0, the corres + # ponding port channel will have the highest priority level (timeout condi + # tion - Priority0). For multi-port configurations, the aging counters can + # not be used to set port priorities when external dynamic priority inputs + # (arqos) are enabled (timeout is still applicable). For single port conf + # igurations, the aging counters are only used when they timeout (become 0 + # ) to force read-write direction switching. In this case, external dynami + # c priority input, arqos (for reads only) can still be used to set the DD + # RC read priority (2 priority levels: low priority read - LPR, high prior + # ity read - HPR) on a command by command basis. Note: The two LSBs of thi + # s register field are tied internally to 2'b00. # PSU_DDRC_PCFGR_2_RD_PORT_PRIORITY 0xf # Port n Configuration Read Register @@ -3085,33 +3814,42 @@ set psu_ddr_init_data { mask_write 0XFD070564 0x000073FF 0x0000200F # Register : PCFGW_2 @ 0XFD070568

- # If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - # d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - # imit register. - # PSU_DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN 0x1 + # If set to 1, enables the Page Match feature. If enabled, once a requesti + # ng port is granted, the port is continued to be granted if the following + # immediate commands are to the same memory page (same bank and same row) + # . See also related PCCFG.pagematch_limit register. + # PSU_DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN 0x0 - # If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por - # becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register - # Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is - # not associated with any particular command). + # If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + # bled and awurgent is asserted by the master, that port becomes the highe + # st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + # ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + # serted anytime and as long as required which is independent of address h + # andshaking (it is not associated with any particular command). # PSU_DDRC_PCFGW_2_WR_PORT_URGENT_EN 0x1 # If set to 1, enables aging function for the write channel of the port. # PSU_DDRC_PCFGW_2_WR_PORT_AGING_EN 0x0 - # Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each - # rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - # The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port - # s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0 - # the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno - # be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For - # ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch - # ng. Note: The two LSBs of this register field are tied internally to 2'b00. + # Determines the initial load value of write aging counters. These counter + # s will be parallel loaded after reset, or after each grant to the corres + # ponding port. The aging counters down-count every clock cycle where the + # port is requesting but not granted. The higher significant 5-bits of the + # write aging counter sets the initial priority of the write channel of a + # given port. Port's priority will increase as the higher significant 5-b + # its of the counter starts to decrease. When the aging counter becomes 0, + # the corresponding port channel will have the highest priority level. Fo + # r multi-port configurations, the aging counters cannot be used to set po + # rt priorities when external dynamic priority inputs (awqos) are enabled + # (timeout is still applicable). For single port configurations, the aging + # counters are only used when they timeout (become 0) to force read-write + # direction switching. Note: The two LSBs of this register field are tied + # internally to 2'b00. # PSU_DDRC_PCFGW_2_WR_PORT_PRIORITY 0xf # Port n Configuration Write Register - #(OFFSET, MASK, VALUE) (0XFD070568, 0x000073FFU ,0x0000600FU) */ - mask_write 0XFD070568 0x000073FF 0x0000600F + #(OFFSET, MASK, VALUE) (0XFD070568, 0x000073FFU ,0x0000200FU) */ + mask_write 0XFD070568 0x000073FF 0x0000200F # Register : PCTRL_2 @ 0XFD0705F0

# Enables port n. @@ -3122,31 +3860,43 @@ set psu_ddr_init_data { mask_write 0XFD0705F0 0x00000001 0x00000001 # Register : PCFGQOS0_2 @ 0XFD0705F4

- # This bitfield indicates the traffic class of region2. For dual address queue configurations, region2 maps to the red address - # ueue. Valid values are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and traffic class of region2 - # s set to 1 (VPR), VPR traffic is aliased to LPR traffic. + # This bitfield indicates the traffic class of region2. For dual address q + # ueue configurations, region2 maps to the red address queue. Valid values + # are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN + # = 0) and traffic class of region2 is set to 1 (VPR), VPR traffic is ali + # ased to LPR traffic. # PSU_DDRC_PCFGQOS0_2_RQOS_MAP_REGION2 0x2 - # This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf - # gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is - # disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. + # This bitfield indicates the traffic class of region 1. Valid values are: + # 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + # maps to the blue address queue. In this case, valid values are 0: LPR a + # nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + # ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + # traffic. # PSU_DDRC_PCFGQOS0_2_RQOS_MAP_REGION1 0x0 - # This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi - # urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i - # disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. + # This bitfield indicates the traffic class of region 0. Valid values are: + # 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + # maps to the blue address queue. In this case, valid values are: 0: LPR + # and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + # affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + # traffic. # PSU_DDRC_PCFGQOS0_2_RQOS_MAP_REGION0 0x0 - # Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (le - # el1 + 1) to 14 which corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note that for PA, arqos values are used - # directly as port priorities, where the higher the value corresponds to higher port priority. All of the map_level* registers - # ust be set to distinct values. + # Separation level2 indicating the end of region1 mapping; start of region + # 1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 whi + # ch corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note + # that for PA, arqos values are used directly as port priorities, where t + # he higher the value corresponds to higher port priority. All of the map_ + # level* registers must be set to distinct values. # PSU_DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2 0xb - # Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d - # al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio - # ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc - # values. + # Separation level1 indicating the end of region0 mapping; start of region + # 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + # (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + # lues are used directly as port priorities, where the higher the value co + # rresponds to higher port priority. All of the map_level* registers must + # be set to distinct values. # PSU_DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1 0x3 # Port n Read QoS Configuration Register 0 @@ -3154,10 +3904,12 @@ set psu_ddr_init_data { mask_write 0XFD0705F4 0x03330F0F 0x02000B03 # Register : PCFGQOS1_2 @ 0XFD0705F8

- # Specifies the timeout value for transactions mapped to the red address queue. + # Specifies the timeout value for transactions mapped to the red address q + # ueue. # PSU_DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR 0x0 - # Specifies the timeout value for transactions mapped to the blue address queue. + # Specifies the timeout value for transactions mapped to the blue address + # queue. # PSU_DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB 0x0 # Port n Read QoS Configuration Register 1 @@ -3165,30 +3917,41 @@ set psu_ddr_init_data { mask_write 0XFD0705F8 0x07FF07FF 0x00000000 # Register : PCFGR_3 @ 0XFD070614

- # If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - # d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - # imit register. + # If set to 1, enables the Page Match feature. If enabled, once a requesti + # ng port is granted, the port is continued to be granted if the following + # immediate commands are to the same memory page (same bank and same row) + # . See also related PCCFG.pagematch_limit register. # PSU_DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN 0x0 - # If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por - # becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG. - # o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add - # ess handshaking (it is not associated with any particular command). + # If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + # bled and arurgent is asserted by the master, that port becomes the highe + # st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + # RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + # urgent signal can be asserted anytime and as long as required which is i + # ndependent of address handshaking (it is not associated with any particu + # lar command). # PSU_DDRC_PCFGR_3_RD_PORT_URGENT_EN 0x1 # If set to 1, enables aging function for the read channel of the port. # PSU_DDRC_PCFGR_3_RD_PORT_AGING_EN 0x0 - # Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g - # ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - # he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority - # will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre - # ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the - # aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st - # ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w - # ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D - # RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: - # he two LSBs of this register field are tied internally to 2'b00. + # Determines the initial load value of read aging counters. These counters + # will be parallel loaded after reset, or after each grant to the corresp + # onding port. The aging counters down-count every clock cycle where the p + # ort is requesting but not granted. The higher significant 5-bits of the + # read aging counter sets the priority of the read channel of a given port + # . Port's priority will increase as the higher significant 5-bits of the + # counter starts to decrease. When the aging counter becomes 0, the corres + # ponding port channel will have the highest priority level (timeout condi + # tion - Priority0). For multi-port configurations, the aging counters can + # not be used to set port priorities when external dynamic priority inputs + # (arqos) are enabled (timeout is still applicable). For single port conf + # igurations, the aging counters are only used when they timeout (become 0 + # ) to force read-write direction switching. In this case, external dynami + # c priority input, arqos (for reads only) can still be used to set the DD + # RC read priority (2 priority levels: low priority read - LPR, high prior + # ity read - HPR) on a command by command basis. Note: The two LSBs of thi + # s register field are tied internally to 2'b00. # PSU_DDRC_PCFGR_3_RD_PORT_PRIORITY 0xf # Port n Configuration Read Register @@ -3196,33 +3959,42 @@ set psu_ddr_init_data { mask_write 0XFD070614 0x000073FF 0x0000200F # Register : PCFGW_3 @ 0XFD070618

- # If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - # d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - # imit register. - # PSU_DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN 0x1 + # If set to 1, enables the Page Match feature. If enabled, once a requesti + # ng port is granted, the port is continued to be granted if the following + # immediate commands are to the same memory page (same bank and same row) + # . See also related PCCFG.pagematch_limit register. + # PSU_DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN 0x0 - # If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por - # becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register - # Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is - # not associated with any particular command). + # If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + # bled and awurgent is asserted by the master, that port becomes the highe + # st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + # ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + # serted anytime and as long as required which is independent of address h + # andshaking (it is not associated with any particular command). # PSU_DDRC_PCFGW_3_WR_PORT_URGENT_EN 0x1 # If set to 1, enables aging function for the write channel of the port. # PSU_DDRC_PCFGW_3_WR_PORT_AGING_EN 0x0 - # Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each - # rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - # The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port - # s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0 - # the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno - # be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For - # ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch - # ng. Note: The two LSBs of this register field are tied internally to 2'b00. + # Determines the initial load value of write aging counters. These counter + # s will be parallel loaded after reset, or after each grant to the corres + # ponding port. The aging counters down-count every clock cycle where the + # port is requesting but not granted. The higher significant 5-bits of the + # write aging counter sets the initial priority of the write channel of a + # given port. Port's priority will increase as the higher significant 5-b + # its of the counter starts to decrease. When the aging counter becomes 0, + # the corresponding port channel will have the highest priority level. Fo + # r multi-port configurations, the aging counters cannot be used to set po + # rt priorities when external dynamic priority inputs (awqos) are enabled + # (timeout is still applicable). For single port configurations, the aging + # counters are only used when they timeout (become 0) to force read-write + # direction switching. Note: The two LSBs of this register field are tied + # internally to 2'b00. # PSU_DDRC_PCFGW_3_WR_PORT_PRIORITY 0xf # Port n Configuration Write Register - #(OFFSET, MASK, VALUE) (0XFD070618, 0x000073FFU ,0x0000600FU) */ - mask_write 0XFD070618 0x000073FF 0x0000600F + #(OFFSET, MASK, VALUE) (0XFD070618, 0x000073FFU ,0x0000200FU) */ + mask_write 0XFD070618 0x000073FF 0x0000200F # Register : PCTRL_3 @ 0XFD0706A0

# Enables port n. @@ -3233,20 +4005,28 @@ set psu_ddr_init_data { mask_write 0XFD0706A0 0x00000001 0x00000001 # Register : PCFGQOS0_3 @ 0XFD0706A4

- # This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf - # gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is - # disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. + # This bitfield indicates the traffic class of region 1. Valid values are: + # 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + # maps to the blue address queue. In this case, valid values are 0: LPR a + # nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + # ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + # traffic. # PSU_DDRC_PCFGQOS0_3_RQOS_MAP_REGION1 0x1 - # This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi - # urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i - # disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. + # This bitfield indicates the traffic class of region 0. Valid values are: + # 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + # maps to the blue address queue. In this case, valid values are: 0: LPR + # and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + # affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + # traffic. # PSU_DDRC_PCFGQOS0_3_RQOS_MAP_REGION0 0x0 - # Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d - # al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio - # ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc - # values. + # Separation level1 indicating the end of region0 mapping; start of region + # 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + # (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + # lues are used directly as port priorities, where the higher the value co + # rresponds to higher port priority. All of the map_level* registers must + # be set to distinct values. # PSU_DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1 0x3 # Port n Read QoS Configuration Register 0 @@ -3254,10 +4034,12 @@ set psu_ddr_init_data { mask_write 0XFD0706A4 0x0033000F 0x00100003 # Register : PCFGQOS1_3 @ 0XFD0706A8

- # Specifies the timeout value for transactions mapped to the red address queue. + # Specifies the timeout value for transactions mapped to the red address q + # ueue. # PSU_DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR 0x0 - # Specifies the timeout value for transactions mapped to the blue address queue. + # Specifies the timeout value for transactions mapped to the blue address + # queue. # PSU_DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB 0x4f # Port n Read QoS Configuration Register 1 @@ -3265,17 +4047,22 @@ set psu_ddr_init_data { mask_write 0XFD0706A8 0x07FF07FF 0x0000004F # Register : PCFGWQOS0_3 @ 0XFD0706AC

- # This bitfield indicates the traffic class of region 1. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2 - # VPW_EN = 0) and traffic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW traffic. + # This bitfield indicates the traffic class of region 1. Valid values are: + # 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + # affic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW + # traffic. # PSU_DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1 0x1 - # This bitfield indicates the traffic class of region 0. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2 - # VPW_EN = 0) and traffic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW traffic. + # This bitfield indicates the traffic class of region 0. Valid values are: + # 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + # affic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW + # traffic. # PSU_DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0 0x0 - # Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 14 which c - # rresponds to awqos. Note that for PA, awqos values are used directly as port priorities, where the higher the value correspon - # s to higher port priority. + # Separation level indicating the end of region0 mapping; start of region0 + # is 0. Possible values for level1 are 0 to 14 which corresponds to awqos + # . Note that for PA, awqos values are used directly as port priorities, w + # here the higher the value corresponds to higher port priority. # PSU_DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL 0x3 # Port n Write QoS Configuration Register 0 @@ -3291,64 +4078,84 @@ set psu_ddr_init_data { mask_write 0XFD0706B0 0x000007FF 0x0000004F # Register : PCFGR_4 @ 0XFD0706C4

- # If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - # d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - # imit register. - # PSU_DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN 0x1 + # If set to 1, enables the Page Match feature. If enabled, once a requesti + # ng port is granted, the port is continued to be granted if the following + # immediate commands are to the same memory page (same bank and same row) + # . See also related PCCFG.pagematch_limit register. + # PSU_DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN 0x0 - # If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por - # becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG. - # o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add - # ess handshaking (it is not associated with any particular command). + # If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + # bled and arurgent is asserted by the master, that port becomes the highe + # st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + # RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + # urgent signal can be asserted anytime and as long as required which is i + # ndependent of address handshaking (it is not associated with any particu + # lar command). # PSU_DDRC_PCFGR_4_RD_PORT_URGENT_EN 0x1 # If set to 1, enables aging function for the read channel of the port. # PSU_DDRC_PCFGR_4_RD_PORT_AGING_EN 0x0 - # Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g - # ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - # he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority - # will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre - # ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the - # aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st - # ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w - # ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D - # RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: - # he two LSBs of this register field are tied internally to 2'b00. + # Determines the initial load value of read aging counters. These counters + # will be parallel loaded after reset, or after each grant to the corresp + # onding port. The aging counters down-count every clock cycle where the p + # ort is requesting but not granted. The higher significant 5-bits of the + # read aging counter sets the priority of the read channel of a given port + # . Port's priority will increase as the higher significant 5-bits of the + # counter starts to decrease. When the aging counter becomes 0, the corres + # ponding port channel will have the highest priority level (timeout condi + # tion - Priority0). For multi-port configurations, the aging counters can + # not be used to set port priorities when external dynamic priority inputs + # (arqos) are enabled (timeout is still applicable). For single port conf + # igurations, the aging counters are only used when they timeout (become 0 + # ) to force read-write direction switching. In this case, external dynami + # c priority input, arqos (for reads only) can still be used to set the DD + # RC read priority (2 priority levels: low priority read - LPR, high prior + # ity read - HPR) on a command by command basis. Note: The two LSBs of thi + # s register field are tied internally to 2'b00. # PSU_DDRC_PCFGR_4_RD_PORT_PRIORITY 0xf # Port n Configuration Read Register - #(OFFSET, MASK, VALUE) (0XFD0706C4, 0x000073FFU ,0x0000600FU) */ - mask_write 0XFD0706C4 0x000073FF 0x0000600F + #(OFFSET, MASK, VALUE) (0XFD0706C4, 0x000073FFU ,0x0000200FU) */ + mask_write 0XFD0706C4 0x000073FF 0x0000200F # Register : PCFGW_4 @ 0XFD0706C8

- # If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - # d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - # imit register. - # PSU_DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN 0x1 + # If set to 1, enables the Page Match feature. If enabled, once a requesti + # ng port is granted, the port is continued to be granted if the following + # immediate commands are to the same memory page (same bank and same row) + # . See also related PCCFG.pagematch_limit register. + # PSU_DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN 0x0 - # If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por - # becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register - # Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is - # not associated with any particular command). + # If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + # bled and awurgent is asserted by the master, that port becomes the highe + # st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + # ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + # serted anytime and as long as required which is independent of address h + # andshaking (it is not associated with any particular command). # PSU_DDRC_PCFGW_4_WR_PORT_URGENT_EN 0x1 # If set to 1, enables aging function for the write channel of the port. # PSU_DDRC_PCFGW_4_WR_PORT_AGING_EN 0x0 - # Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each - # rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - # The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port - # s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0 - # the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno - # be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For - # ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch - # ng. Note: The two LSBs of this register field are tied internally to 2'b00. + # Determines the initial load value of write aging counters. These counter + # s will be parallel loaded after reset, or after each grant to the corres + # ponding port. The aging counters down-count every clock cycle where the + # port is requesting but not granted. The higher significant 5-bits of the + # write aging counter sets the initial priority of the write channel of a + # given port. Port's priority will increase as the higher significant 5-b + # its of the counter starts to decrease. When the aging counter becomes 0, + # the corresponding port channel will have the highest priority level. Fo + # r multi-port configurations, the aging counters cannot be used to set po + # rt priorities when external dynamic priority inputs (awqos) are enabled + # (timeout is still applicable). For single port configurations, the aging + # counters are only used when they timeout (become 0) to force read-write + # direction switching. Note: The two LSBs of this register field are tied + # internally to 2'b00. # PSU_DDRC_PCFGW_4_WR_PORT_PRIORITY 0xf # Port n Configuration Write Register - #(OFFSET, MASK, VALUE) (0XFD0706C8, 0x000073FFU ,0x0000600FU) */ - mask_write 0XFD0706C8 0x000073FF 0x0000600F + #(OFFSET, MASK, VALUE) (0XFD0706C8, 0x000073FFU ,0x0000200FU) */ + mask_write 0XFD0706C8 0x000073FF 0x0000200F # Register : PCTRL_4 @ 0XFD070750

# Enables port n. @@ -3359,20 +4166,28 @@ set psu_ddr_init_data { mask_write 0XFD070750 0x00000001 0x00000001 # Register : PCFGQOS0_4 @ 0XFD070754

- # This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf - # gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is - # disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. + # This bitfield indicates the traffic class of region 1. Valid values are: + # 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + # maps to the blue address queue. In this case, valid values are 0: LPR a + # nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + # ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + # traffic. # PSU_DDRC_PCFGQOS0_4_RQOS_MAP_REGION1 0x1 - # This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi - # urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i - # disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. + # This bitfield indicates the traffic class of region 0. Valid values are: + # 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + # maps to the blue address queue. In this case, valid values are: 0: LPR + # and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + # affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + # traffic. # PSU_DDRC_PCFGQOS0_4_RQOS_MAP_REGION0 0x0 - # Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d - # al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio - # ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc - # values. + # Separation level1 indicating the end of region0 mapping; start of region + # 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + # (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + # lues are used directly as port priorities, where the higher the value co + # rresponds to higher port priority. All of the map_level* registers must + # be set to distinct values. # PSU_DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1 0x3 # Port n Read QoS Configuration Register 0 @@ -3380,10 +4195,12 @@ set psu_ddr_init_data { mask_write 0XFD070754 0x0033000F 0x00100003 # Register : PCFGQOS1_4 @ 0XFD070758

- # Specifies the timeout value for transactions mapped to the red address queue. + # Specifies the timeout value for transactions mapped to the red address q + # ueue. # PSU_DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR 0x0 - # Specifies the timeout value for transactions mapped to the blue address queue. + # Specifies the timeout value for transactions mapped to the blue address + # queue. # PSU_DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB 0x4f # Port n Read QoS Configuration Register 1 @@ -3391,17 +4208,22 @@ set psu_ddr_init_data { mask_write 0XFD070758 0x07FF07FF 0x0000004F # Register : PCFGWQOS0_4 @ 0XFD07075C

- # This bitfield indicates the traffic class of region 1. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2 - # VPW_EN = 0) and traffic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW traffic. + # This bitfield indicates the traffic class of region 1. Valid values are: + # 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + # affic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW + # traffic. # PSU_DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1 0x1 - # This bitfield indicates the traffic class of region 0. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2 - # VPW_EN = 0) and traffic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW traffic. + # This bitfield indicates the traffic class of region 0. Valid values are: + # 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + # affic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW + # traffic. # PSU_DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0 0x0 - # Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 14 which c - # rresponds to awqos. Note that for PA, awqos values are used directly as port priorities, where the higher the value correspon - # s to higher port priority. + # Separation level indicating the end of region0 mapping; start of region0 + # is 0. Possible values for level1 are 0 to 14 which corresponds to awqos + # . Note that for PA, awqos values are used directly as port priorities, w + # here the higher the value corresponds to higher port priority. # PSU_DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL 0x3 # Port n Write QoS Configuration Register 0 @@ -3417,30 +4239,41 @@ set psu_ddr_init_data { mask_write 0XFD070760 0x000007FF 0x0000004F # Register : PCFGR_5 @ 0XFD070774

- # If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - # d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - # imit register. + # If set to 1, enables the Page Match feature. If enabled, once a requesti + # ng port is granted, the port is continued to be granted if the following + # immediate commands are to the same memory page (same bank and same row) + # . See also related PCCFG.pagematch_limit register. # PSU_DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN 0x0 - # If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por - # becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG. - # o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add - # ess handshaking (it is not associated with any particular command). + # If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + # bled and arurgent is asserted by the master, that port becomes the highe + # st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + # RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + # urgent signal can be asserted anytime and as long as required which is i + # ndependent of address handshaking (it is not associated with any particu + # lar command). # PSU_DDRC_PCFGR_5_RD_PORT_URGENT_EN 0x1 # If set to 1, enables aging function for the read channel of the port. # PSU_DDRC_PCFGR_5_RD_PORT_AGING_EN 0x0 - # Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g - # ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - # he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority - # will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre - # ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the - # aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st - # ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w - # ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D - # RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: - # he two LSBs of this register field are tied internally to 2'b00. + # Determines the initial load value of read aging counters. These counters + # will be parallel loaded after reset, or after each grant to the corresp + # onding port. The aging counters down-count every clock cycle where the p + # ort is requesting but not granted. The higher significant 5-bits of the + # read aging counter sets the priority of the read channel of a given port + # . Port's priority will increase as the higher significant 5-bits of the + # counter starts to decrease. When the aging counter becomes 0, the corres + # ponding port channel will have the highest priority level (timeout condi + # tion - Priority0). For multi-port configurations, the aging counters can + # not be used to set port priorities when external dynamic priority inputs + # (arqos) are enabled (timeout is still applicable). For single port conf + # igurations, the aging counters are only used when they timeout (become 0 + # ) to force read-write direction switching. In this case, external dynami + # c priority input, arqos (for reads only) can still be used to set the DD + # RC read priority (2 priority levels: low priority read - LPR, high prior + # ity read - HPR) on a command by command basis. Note: The two LSBs of thi + # s register field are tied internally to 2'b00. # PSU_DDRC_PCFGR_5_RD_PORT_PRIORITY 0xf # Port n Configuration Read Register @@ -3448,33 +4281,42 @@ set psu_ddr_init_data { mask_write 0XFD070774 0x000073FF 0x0000200F # Register : PCFGW_5 @ 0XFD070778

- # If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - # d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - # imit register. - # PSU_DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN 0x1 + # If set to 1, enables the Page Match feature. If enabled, once a requesti + # ng port is granted, the port is continued to be granted if the following + # immediate commands are to the same memory page (same bank and same row) + # . See also related PCCFG.pagematch_limit register. + # PSU_DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN 0x0 - # If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por - # becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register - # Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is - # not associated with any particular command). + # If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + # bled and awurgent is asserted by the master, that port becomes the highe + # st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + # ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + # serted anytime and as long as required which is independent of address h + # andshaking (it is not associated with any particular command). # PSU_DDRC_PCFGW_5_WR_PORT_URGENT_EN 0x1 # If set to 1, enables aging function for the write channel of the port. # PSU_DDRC_PCFGW_5_WR_PORT_AGING_EN 0x0 - # Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each - # rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - # The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port - # s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0 - # the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno - # be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For - # ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch - # ng. Note: The two LSBs of this register field are tied internally to 2'b00. + # Determines the initial load value of write aging counters. These counter + # s will be parallel loaded after reset, or after each grant to the corres + # ponding port. The aging counters down-count every clock cycle where the + # port is requesting but not granted. The higher significant 5-bits of the + # write aging counter sets the initial priority of the write channel of a + # given port. Port's priority will increase as the higher significant 5-b + # its of the counter starts to decrease. When the aging counter becomes 0, + # the corresponding port channel will have the highest priority level. Fo + # r multi-port configurations, the aging counters cannot be used to set po + # rt priorities when external dynamic priority inputs (awqos) are enabled + # (timeout is still applicable). For single port configurations, the aging + # counters are only used when they timeout (become 0) to force read-write + # direction switching. Note: The two LSBs of this register field are tied + # internally to 2'b00. # PSU_DDRC_PCFGW_5_WR_PORT_PRIORITY 0xf # Port n Configuration Write Register - #(OFFSET, MASK, VALUE) (0XFD070778, 0x000073FFU ,0x0000600FU) */ - mask_write 0XFD070778 0x000073FF 0x0000600F + #(OFFSET, MASK, VALUE) (0XFD070778, 0x000073FFU ,0x0000200FU) */ + mask_write 0XFD070778 0x000073FF 0x0000200F # Register : PCTRL_5 @ 0XFD070800

# Enables port n. @@ -3485,20 +4327,28 @@ set psu_ddr_init_data { mask_write 0XFD070800 0x00000001 0x00000001 # Register : PCFGQOS0_5 @ 0XFD070804

- # This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf - # gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is - # disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. + # This bitfield indicates the traffic class of region 1. Valid values are: + # 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + # maps to the blue address queue. In this case, valid values are 0: LPR a + # nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + # ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + # traffic. # PSU_DDRC_PCFGQOS0_5_RQOS_MAP_REGION1 0x1 - # This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi - # urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i - # disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. + # This bitfield indicates the traffic class of region 0. Valid values are: + # 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + # maps to the blue address queue. In this case, valid values are: 0: LPR + # and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + # affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + # traffic. # PSU_DDRC_PCFGQOS0_5_RQOS_MAP_REGION0 0x0 - # Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d - # al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio - # ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc - # values. + # Separation level1 indicating the end of region0 mapping; start of region + # 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + # (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + # lues are used directly as port priorities, where the higher the value co + # rresponds to higher port priority. All of the map_level* registers must + # be set to distinct values. # PSU_DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1 0x3 # Port n Read QoS Configuration Register 0 @@ -3506,10 +4356,12 @@ set psu_ddr_init_data { mask_write 0XFD070804 0x0033000F 0x00100003 # Register : PCFGQOS1_5 @ 0XFD070808

- # Specifies the timeout value for transactions mapped to the red address queue. + # Specifies the timeout value for transactions mapped to the red address q + # ueue. # PSU_DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR 0x0 - # Specifies the timeout value for transactions mapped to the blue address queue. + # Specifies the timeout value for transactions mapped to the blue address + # queue. # PSU_DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB 0x4f # Port n Read QoS Configuration Register 1 @@ -3517,17 +4369,22 @@ set psu_ddr_init_data { mask_write 0XFD070808 0x07FF07FF 0x0000004F # Register : PCFGWQOS0_5 @ 0XFD07080C

- # This bitfield indicates the traffic class of region 1. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2 - # VPW_EN = 0) and traffic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW traffic. + # This bitfield indicates the traffic class of region 1. Valid values are: + # 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + # affic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW + # traffic. # PSU_DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1 0x1 - # This bitfield indicates the traffic class of region 0. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2 - # VPW_EN = 0) and traffic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW traffic. + # This bitfield indicates the traffic class of region 0. Valid values are: + # 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + # affic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW + # traffic. # PSU_DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0 0x0 - # Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 14 which c - # rresponds to awqos. Note that for PA, awqos values are used directly as port priorities, where the higher the value correspon - # s to higher port priority. + # Separation level indicating the end of region0 mapping; start of region0 + # is 0. Possible values for level1 are 0 to 14 which corresponds to awqos + # . Note that for PA, awqos values are used directly as port priorities, w + # here the higher the value corresponds to higher port priority. # PSU_DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL 0x3 # Port n Write QoS Configuration Register 0 @@ -3543,8 +4400,9 @@ set psu_ddr_init_data { mask_write 0XFD070810 0x000007FF 0x0000004F # Register : SARBASE0 @ 0XFD070F04

- # Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x] and araddr[UMCTL2_A_ADDRW-1:x] where x is determine - # by the minimum block size parameter UMCTL2_SARMINSIZE: (x=log2(block size)). + # Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x + # ] and araddr[UMCTL2_A_ADDRW-1:x] where x is determined by the minimum bl + # ock size parameter UMCTL2_SARMINSIZE: (x=log2(block size)). # PSU_DDRC_SARBASE0_BASE_ADDR 0x0 # SAR Base Address Register n @@ -3552,9 +4410,11 @@ set psu_ddr_init_data { mask_write 0XFD070F04 0x000001FF 0x00000000 # Register : SARSIZE0 @ 0XFD070F08

- # Number of blocks for address region n. This register determines the total size of the region in multiples of minimum block si - # e as specified by the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded as number of blocks = nblocks + 1. - # or example, if register is programmed to 0, region will have 1 block. + # Number of blocks for address region n. This register determines the tota + # l size of the region in multiples of minimum block size as specified by + # the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded + # as number of blocks = nblocks + 1. For example, if register is programme + # d to 0, region will have 1 block. # PSU_DDRC_SARSIZE0_NBLOCKS 0x0 # SAR Size Register n @@ -3562,8 +4422,9 @@ set psu_ddr_init_data { mask_write 0XFD070F08 0x000000FF 0x00000000 # Register : SARBASE1 @ 0XFD070F0C

- # Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x] and araddr[UMCTL2_A_ADDRW-1:x] where x is determine - # by the minimum block size parameter UMCTL2_SARMINSIZE: (x=log2(block size)). + # Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x + # ] and araddr[UMCTL2_A_ADDRW-1:x] where x is determined by the minimum bl + # ock size parameter UMCTL2_SARMINSIZE: (x=log2(block size)). # PSU_DDRC_SARBASE1_BASE_ADDR 0x10 # SAR Base Address Register n @@ -3571,9 +4432,11 @@ set psu_ddr_init_data { mask_write 0XFD070F0C 0x000001FF 0x00000010 # Register : SARSIZE1 @ 0XFD070F10

- # Number of blocks for address region n. This register determines the total size of the region in multiples of minimum block si - # e as specified by the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded as number of blocks = nblocks + 1. - # or example, if register is programmed to 0, region will have 1 block. + # Number of blocks for address region n. This register determines the tota + # l size of the region in multiples of minimum block size as specified by + # the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded + # as number of blocks = nblocks + 1. For example, if register is programme + # d to 0, region will have 1 block. # PSU_DDRC_SARSIZE1_NBLOCKS 0xf # SAR Size Register n @@ -3581,38 +4444,51 @@ set psu_ddr_init_data { mask_write 0XFD070F10 0x000000FF 0x0000000F # Register : DFITMG0_SHADOW @ 0XFD072190

- # Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signa - # s at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligne - # , this timing parameter should be rounded up to the next integer value. Note that if using RDIMM, it is necessary to incremen - # this parameter by RDIMM's extra cycle of latency in terms of DFI clock. + # Specifies the number of DFI clock cycles after an assertion or de-assert + # ion of the DFI control signals that the control signals at the PHY-DRAM + # interface reflect the assertion or de-assertion. If the DFI clock and th + # e memory clock are not phase-aligned, this timing parameter should be ro + # unded up to the next integer value. Note that if using RDIMM, it is nece + # ssary to increment this parameter by RDIMM's extra cycle of latency in t + # erms of DFI clock. # PSU_DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY 0x7 - # Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR or SDR values Selects whether value in DFITM - # 0.dfi_t_rddata_en is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles R - # fer to PHY specification for correct value. + # Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated u + # sing HDR or SDR values Selects whether value in DFITMG0.dfi_t_rddata_en + # is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles + # - 1 in terms of SDR clock cycles Refer to PHY specification for correct + # value. # PSU_DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR 0x1 - # Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. Refer to PHY spe - # ification for correct value. This corresponds to the DFI parameter trddata_en. Note that, depending on the PHY, if using RDIM - # , it may be necessary to use the value (CL + 1) in the calculation of trddata_en. This is to compensate for the extra cycle o - # latency through the RDIMM. Unit: Clocks + # Time from the assertion of a read command on the DFI interface to the as + # sertion of the dfi_rddata_en signal. Refer to PHY specification for corr + # ect value. This corresponds to the DFI parameter trddata_en. Note that, + # depending on the PHY, if using RDIMM, it may be necessary to use the val + # ue (CL + 1) in the calculation of trddata_en. This is to compensate for + # the extra cycle of latency through the RDIMM. Unit: Clocks # PSU_DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN 0x2 - # Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using HDR or SDR values Selects whether value in DFITMG - # .dfi_tphy_wrlat is in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.dfi_tphy_wrdata is in terms of SDR or - # HDR clock cycles - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles Refer to PHY specification for correct val - # e. + # Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated us + # ing HDR or SDR values Selects whether value in DFITMG0.dfi_tphy_wrlat is + # in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.df + # i_tphy_wrdata is in terms of SDR or HDR clock cycles - 0 in terms of HDR + # clock cycles - 1 in terms of SDR clock cycles Refer to PHY specificatio + # n for correct value. # PSU_DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR 0x1 - # Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on th - # dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. N - # te, max supported value is 8. Unit: Clocks + # Specifies the number of clock cycles between when dfi_wrdata_en is asser + # ted to when the associated write data is driven on the dfi_wrdata signal + # . This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY + # specification for correct value. Note, max supported value is 8. Unit: + # Clocks # PSU_DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA 0x0 - # Write latency Number of clocks from the write command to write data enable (dfi_wrdata_en). This corresponds to the DFI timin - # parameter tphy_wrlat. Refer to PHY specification for correct value.Note that, depending on the PHY, if using RDIMM, it may b - # necessary to use the value (CL + 1) in the calculation of tphy_wrlat. This is to compensate for the extra cycle of latency t - # rough the RDIMM. + # Write latency Number of clocks from the write command to write data enab + # le (dfi_wrdata_en). This corresponds to the DFI timing parameter tphy_wr + # lat. Refer to PHY specification for correct value.Note that, depending o + # n the PHY, if using RDIMM, it may be necessary to use the value (CL + 1) + # in the calculation of tphy_wrlat. This is to compensate for the extra c + # ycle of latency through the RDIMM. # PSU_DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT 0x2 # DFI Timing Shadow Register 0 @@ -3624,9 +4500,12 @@ set psu_ddr_init_data { # DDR block level reset inside of the DDR Sub System # PSU_CRF_APB_RST_DDR_SS_DDR_RESET 0X0 + # APM block level reset inside of the DDR Sub System + # PSU_CRF_APB_RST_DDR_SS_APM_RESET 0X0 + # DDR sub system block level reset - #(OFFSET, MASK, VALUE) (0XFD1A0108, 0x00000008U ,0x00000000U) */ - mask_write 0XFD1A0108 0x00000008 0x00000000 + #(OFFSET, MASK, VALUE) (0XFD1A0108, 0x0000000CU ,0x00000000U) */ + mask_write 0XFD1A0108 0x0000000C 0x00000000 # : DDR PHY # Register : PGCR0 @ 0XFD080010

@@ -3687,11 +4566,11 @@ set psu_ddr_init_data { # PSU_DDR_PHY_PGCR2_PLLFSMBYP 0x0 # Refresh Period - # PSU_DDR_PHY_PGCR2_TREFPRD 0x10028 + # PSU_DDR_PHY_PGCR2_TREFPRD 0x10010 # PHY General Configuration Register 2 - #(OFFSET, MASK, VALUE) (0XFD080018, 0xFFFFFFFFU ,0x00F10028U) */ - mask_write 0XFD080018 0xFFFFFFFF 0x00F10028 + #(OFFSET, MASK, VALUE) (0XFD080018, 0xFFFFFFFFU ,0x00F10010U) */ + mask_write 0XFD080018 0xFFFFFFFF 0x00F10010 # Register : PGCR3 @ 0XFD08001C

# CKN Enable @@ -3765,41 +4644,86 @@ set psu_ddr_init_data { # Register : PTR0 @ 0XFD080040

# PLL Power-Down Time - # PSU_DDR_PHY_PTR0_TPLLPD 0x2f0 + # PSU_DDR_PHY_PTR0_TPLLPD 0x56 # PLL Gear Shift Time - # PSU_DDR_PHY_PTR0_TPLLGS 0x60 + # PSU_DDR_PHY_PTR0_TPLLGS 0x2155 # PHY Reset Time # PSU_DDR_PHY_PTR0_TPHYRST 0x10 # PHY Timing Register 0 - #(OFFSET, MASK, VALUE) (0XFD080040, 0xFFFFFFFFU ,0x5E001810U) */ - mask_write 0XFD080040 0xFFFFFFFF 0x5E001810 + #(OFFSET, MASK, VALUE) (0XFD080040, 0xFFFFFFFFU ,0x0AC85550U) */ + mask_write 0XFD080040 0xFFFFFFFF 0x0AC85550 # Register : PTR1 @ 0XFD080044

# PLL Lock Time - # PSU_DDR_PHY_PTR1_TPLLLOCK 0x80 + # PSU_DDR_PHY_PTR1_TPLLLOCK 0x4141 # Reserved. Returns zeroes on reads. # PSU_DDR_PHY_PTR1_RESERVED_15_13 0x0 # PLL Reset Time - # PSU_DDR_PHY_PTR1_TPLLRST 0x5f0 + # PSU_DDR_PHY_PTR1_TPLLRST 0xaff # PHY Timing Register 1 - #(OFFSET, MASK, VALUE) (0XFD080044, 0xFFFFFFFFU ,0x008005F0U) */ - mask_write 0XFD080044 0xFFFFFFFF 0x008005F0 + #(OFFSET, MASK, VALUE) (0XFD080044, 0xFFFFFFFFU ,0x41410AFFU) */ + mask_write 0XFD080044 0xFFFFFFFF 0x41410AFF + # Register : PLLCR0 @ 0XFD080068

+ + # PLL Bypass + # PSU_DDR_PHY_PLLCR0_PLLBYP 0x0 + + # PLL Reset + # PSU_DDR_PHY_PLLCR0_PLLRST 0x0 + + # PLL Power Down + # PSU_DDR_PHY_PLLCR0_PLLPD 0x0 + + # Reference Stop Mode + # PSU_DDR_PHY_PLLCR0_RSTOPM 0x0 + + # PLL Frequency Select + # PSU_DDR_PHY_PLLCR0_FRQSEL 0x1 + + # Relock Mode + # PSU_DDR_PHY_PLLCR0_RLOCKM 0x0 + + # Charge Pump Proportional Current Control + # PSU_DDR_PHY_PLLCR0_CPPC 0x8 + + # Charge Pump Integrating Current Control + # PSU_DDR_PHY_PLLCR0_CPIC 0x0 + + # Gear Shift + # PSU_DDR_PHY_PLLCR0_GSHIFT 0x0 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_PLLCR0_RESERVED_11_9 0x0 + + # Analog Test Enable + # PSU_DDR_PHY_PLLCR0_ATOEN 0x0 + + # Analog Test Control + # PSU_DDR_PHY_PLLCR0_ATC 0x0 + + # Digital Test Control + # PSU_DDR_PHY_PLLCR0_DTC 0x0 + + # PLL Control Register 0 (Type B PLL Only) + #(OFFSET, MASK, VALUE) (0XFD080068, 0xFFFFFFFFU ,0x01100000U) */ + mask_write 0XFD080068 0xFFFFFFFF 0x01100000 # Register : DSGCR @ 0XFD080090

# Reserved. Return zeroes on reads. # PSU_DDR_PHY_DSGCR_RESERVED_31_28 0x0 - # When RDBI enabled, this bit is used to select RDBI CL calculation, if it is 1b1, calculation will use RDBICL, otherwise use d - # fault calculation. + # When RDBI enabled, this bit is used to select RDBI CL calculation, if it + # is 1b1, calculation will use RDBICL, otherwise use default calculation. # PSU_DDR_PHY_DSGCR_RDBICLSEL 0x0 - # When RDBI enabled, if RDBICLSEL is asserted, RDBI CL adjust using this value. + # When RDBI enabled, if RDBICLSEL is asserted, RDBI CL adjust using this v + # alue. # PSU_DDR_PHY_DSGCR_RDBICL 0x2 # PHY Impedance Update Enable @@ -3836,7 +4760,7 @@ set psu_ddr_init_data { # PSU_DDR_PHY_DSGCR_DTOODT 0x0 # PHY Update Acknowledge Delay - # PSU_DDR_PHY_DSGCR_PUAD 0x4 + # PSU_DDR_PHY_DSGCR_PUAD 0x5 # Controller Update Acknowledge Enable # PSU_DDR_PHY_DSGCR_CUAEN 0x1 @@ -3854,8 +4778,16 @@ set psu_ddr_init_data { # PSU_DDR_PHY_DSGCR_PUREN 0x1 # DDR System General Configuration Register - #(OFFSET, MASK, VALUE) (0XFD080090, 0xFFFFFFFFU ,0x02A04121U) */ - mask_write 0XFD080090 0xFFFFFFFF 0x02A04121 + #(OFFSET, MASK, VALUE) (0XFD080090, 0xFFFFFFFFU ,0x02A04161U) */ + mask_write 0XFD080090 0xFFFFFFFF 0x02A04161 + # Register : GPR0 @ 0XFD0800C0

+ + # General Purpose Register 0 + # PSU_DDR_PHY_GPR0_GPR0 0xd3 + + # General Purpose Register 0 + #(OFFSET, MASK, VALUE) (0XFD0800C0, 0xFFFFFFFFU ,0x000000D3U) */ + mask_write 0XFD0800C0 0xFFFFFFFF 0x000000D3 # Register : DCR @ 0XFD080100

# DDR4 Gear Down Timing. @@ -3921,30 +4853,31 @@ set psu_ddr_init_data { # PSU_DDR_PHY_DTPR0_RESERVED_7_5 0x0 # Internal read to precharge command delay - # PSU_DDR_PHY_DTPR0_TRTP 0x9 + # PSU_DDR_PHY_DTPR0_TRTP 0x8 # DRAM Timing Parameters Register 0 - #(OFFSET, MASK, VALUE) (0XFD080110, 0xFFFFFFFFU ,0x06240F09U) */ - mask_write 0XFD080110 0xFFFFFFFF 0x06240F09 + #(OFFSET, MASK, VALUE) (0XFD080110, 0xFFFFFFFFU ,0x06240F08U) */ + mask_write 0XFD080110 0xFFFFFFFF 0x06240F08 # Register : DTPR1 @ 0XFD080114

# Reserved. Return zeroes on reads. # PSU_DDR_PHY_DTPR1_RESERVED_31 0x0 - # Minimum delay from when write leveling mode is programmed to the first DQS/DQS# rising edge. + # Minimum delay from when write leveling mode is programmed to the first D + # QS/DQS# rising edge. # PSU_DDR_PHY_DTPR1_TWLMRD 0x28 # Reserved. Return zeroes on reads. # PSU_DDR_PHY_DTPR1_RESERVED_23 0x0 # 4-bank activate period - # PSU_DDR_PHY_DTPR1_TFAW 0x18 + # PSU_DDR_PHY_DTPR1_TFAW 0x20 # Reserved. Return zeroes on reads. # PSU_DDR_PHY_DTPR1_RESERVED_15_11 0x0 # Load mode update delay (DDR4 and DDR3 only) - # PSU_DDR_PHY_DTPR1_TMOD 0x7 + # PSU_DDR_PHY_DTPR1_TMOD 0x0 # Reserved. Return zeroes on reads. # PSU_DDR_PHY_DTPR1_RESERVED_7_5 0x0 @@ -3953,8 +4886,8 @@ set psu_ddr_init_data { # PSU_DDR_PHY_DTPR1_TMRD 0x8 # DRAM Timing Parameters Register 1 - #(OFFSET, MASK, VALUE) (0XFD080114, 0xFFFFFFFFU ,0x28180708U) */ - mask_write 0XFD080114 0xFFFFFFFF 0x28180708 + #(OFFSET, MASK, VALUE) (0XFD080114, 0xFFFFFFFFU ,0x28200008U) */ + mask_write 0XFD080114 0xFFFFFFFF 0x28200008 # Register : DTPR2 @ 0XFD080118

# Reserved. Return zeroes on reads. @@ -3973,17 +4906,17 @@ set psu_ddr_init_data { # PSU_DDR_PHY_DTPR2_RESERVED_23_20 0x0 # CKE minimum pulse width - # PSU_DDR_PHY_DTPR2_TCKE 0x8 + # PSU_DDR_PHY_DTPR2_TCKE 0x7 # Reserved. Return zeroes on reads. # PSU_DDR_PHY_DTPR2_RESERVED_15_10 0x0 # Self refresh exit delay - # PSU_DDR_PHY_DTPR2_TXS 0x200 + # PSU_DDR_PHY_DTPR2_TXS 0x300 # DRAM Timing Parameters Register 2 - #(OFFSET, MASK, VALUE) (0XFD080118, 0xFFFFFFFFU ,0x00080200U) */ - mask_write 0XFD080118 0xFFFFFFFF 0x00080200 + #(OFFSET, MASK, VALUE) (0XFD080118, 0xFFFFFFFFU ,0x00070300U) */ + mask_write 0XFD080118 0xFFFFFFFF 0x00070300 # Register : DTPR3 @ 0XFD08011C

# ODT turn-off delay extension @@ -4034,18 +4967,18 @@ set psu_ddr_init_data { # PSU_DDR_PHY_DTPR4_RESERVED_7_5 0x0 # Power down exit delay - # PSU_DDR_PHY_DTPR4_TXP 0x8 + # PSU_DDR_PHY_DTPR4_TXP 0x7 # DRAM Timing Parameters Register 4 - #(OFFSET, MASK, VALUE) (0XFD080120, 0xFFFFFFFFU ,0x01162B08U) */ - mask_write 0XFD080120 0xFFFFFFFF 0x01162B08 + #(OFFSET, MASK, VALUE) (0XFD080120, 0xFFFFFFFFU ,0x01162B07U) */ + mask_write 0XFD080120 0xFFFFFFFF 0x01162B07 # Register : DTPR5 @ 0XFD080124

# Reserved. Return zeroes on reads. # PSU_DDR_PHY_DTPR5_RESERVED_31_24 0x0 # Activate to activate command delay (same bank) - # PSU_DDR_PHY_DTPR5_TRC 0x32 + # PSU_DDR_PHY_DTPR5_TRC 0x33 # Reserved. Return zeroes on reads. # PSU_DDR_PHY_DTPR5_RESERVED_15 0x0 @@ -4057,11 +4990,11 @@ set psu_ddr_init_data { # PSU_DDR_PHY_DTPR5_RESERVED_7_5 0x0 # Internal write to read command delay - # PSU_DDR_PHY_DTPR5_TWTR 0x9 + # PSU_DDR_PHY_DTPR5_TWTR 0x8 # DRAM Timing Parameters Register 5 - #(OFFSET, MASK, VALUE) (0XFD080124, 0xFFFFFFFFU ,0x00320F09U) */ - mask_write 0XFD080124 0xFFFFFFFF 0x00320F09 + #(OFFSET, MASK, VALUE) (0XFD080124, 0xFFFFFFFFU ,0x00330F08U) */ + mask_write 0XFD080124 0xFFFFFFFF 0x00330F08 # Register : DTPR6 @ 0XFD080128

# PUB Write Latency Enable @@ -4193,15 +5126,18 @@ set psu_ddr_init_data { # DDR4/DDR3 Control Word 5 (CK Driver Characteristics Control Word) # PSU_DDR_PHY_RDIMMCR0_RC5 0x0 - # DDR4 Control Word 4 (ODT and CKE Signals Driver Characteristics Control Word) / DDR3 Control Word 4 (Control Signals Driver C - # aracteristics Control Word) + # DDR4 Control Word 4 (ODT and CKE Signals Driver Characteristics Control + # Word) / DDR3 Control Word 4 (Control Signals Driver Characteristics Cont + # rol Word) # PSU_DDR_PHY_RDIMMCR0_RC4 0x0 - # DDR4 Control Word 3 (CA and CS Signals Driver Characteristics Control Word) / DDR3 Control Word 3 (Command/Address Signals Dr - # ver Characteristrics Control Word) + # DDR4 Control Word 3 (CA and CS Signals Driver Characteristics Control Wo + # rd) / DDR3 Control Word 3 (Command/Address Signals Driver Characteristri + # cs Control Word) # PSU_DDR_PHY_RDIMMCR0_RC3 0x0 - # DDR4 Control Word 2 (Timing and IBT Control Word) / DDR3 Control Word 2 (Timing Control Word) + # DDR4 Control Word 2 (Timing and IBT Control Word) / DDR3 Control Word 2 + # (Timing Control Word) # PSU_DDR_PHY_RDIMMCR0_RC2 0x0 # DDR4/DDR3 Control Word 1 (Clock Driver Enable Control Word) @@ -4227,8 +5163,8 @@ set psu_ddr_init_data { # DDR4 Control Word 12 (Training Control Word) / DDR3 Reserved # PSU_DDR_PHY_RDIMMCR1_RC12 0x0 - # DDR4 Control Word 11 (Operating Voltage VDD and VREFCA Source Control Word) / DDR3 Control Word 11 (Operation Voltage VDD Con - # rol Word) + # DDR4 Control Word 11 (Operating Voltage VDD and VREFCA Source Control Wo + # rd) / DDR3 Control Word 11 (Operation Voltage VDD Control Word) # PSU_DDR_PHY_RDIMMCR1_RC11 0x0 # DDR4/DDR3 Control Word 10 (RDIMM Operating Speed Control Word) @@ -4237,8 +5173,8 @@ set psu_ddr_init_data { # DDR4/DDR3 Control Word 9 (Power Saving Settings Control Word) # PSU_DDR_PHY_RDIMMCR1_RC9 0x0 - # DDR4 Control Word 8 (Input/Output Configuration Control Word) / DDR3 Control Word 8 (Additional Input Bus Termination Setting - # Control Word) + # DDR4 Control Word 8 (Input/Output Configuration Control Word) / DDR3 Con + # trol Word 8 (Additional Input Bus Termination Setting Control Word) # PSU_DDR_PHY_RDIMMCR1_RC8 0x0 # RDIMM Control Register 1 @@ -4247,23 +5183,25 @@ set psu_ddr_init_data { # Register : MR0 @ 0XFD080180

# Reserved. Return zeroes on reads. - # PSU_DDR_PHY_MR0_RESERVED_31_8 0x8 + # PSU_DDR_PHY_MR0_RESERVED_31_8 0x6 # CA Terminating Rank # PSU_DDR_PHY_MR0_CATR 0x0 - # Reserved. These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0. + # Reserved. These are JEDEC reserved bits and are recommended by JEDEC to + # be programmed to 0x0. # PSU_DDR_PHY_MR0_RSVD_6_5 0x1 # Built-in Self-Test for RZQ # PSU_DDR_PHY_MR0_RZQI 0x2 - # Reserved. These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0. + # Reserved. These are JEDEC reserved bits and are recommended by JEDEC to + # be programmed to 0x0. # PSU_DDR_PHY_MR0_RSVD_2_0 0x0 # LPDDR4 Mode Register 0 - #(OFFSET, MASK, VALUE) (0XFD080180, 0xFFFFFFFFU ,0x00000830U) */ - mask_write 0XFD080180 0xFFFFFFFF 0x00000830 + #(OFFSET, MASK, VALUE) (0XFD080180, 0xFFFFFFFFU ,0x00000630U) */ + mask_write 0XFD080180 0xFFFFFFFF 0x00000630 # Register : MR1 @ 0XFD080184

# Reserved. Return zeroes on reads. @@ -4321,7 +5259,8 @@ set psu_ddr_init_data { # Pull-down Drive Strength # PSU_DDR_PHY_MR3_PDDS 0x0 - # These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0. + # These are JEDEC reserved bits and are recommended by JEDEC to be program + # med to 0x0. # PSU_DDR_PHY_MR3_RSVD 0x0 # Write Postamble Length @@ -4338,7 +5277,8 @@ set psu_ddr_init_data { # Reserved. Return zeroes on reads. # PSU_DDR_PHY_MR4_RESERVED_31_16 0x0 - # These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0. + # These are JEDEC reserved bits and are recommended by JEDEC to be program + # med to 0x0. # PSU_DDR_PHY_MR4_RSVD_15_13 0x0 # Write Preamble @@ -4356,7 +5296,8 @@ set psu_ddr_init_data { # CS to Command Latency Mode # PSU_DDR_PHY_MR4_CS2CMDL 0x0 - # These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0. + # These are JEDEC reserved bits and are recommended by JEDEC to be program + # med to 0x0. # PSU_DDR_PHY_MR4_RSVD1 0x0 # Internal VREF Monitor @@ -4371,7 +5312,8 @@ set psu_ddr_init_data { # Maximum Power Down Mode # PSU_DDR_PHY_MR4_MPDM 0x0 - # This is a JEDEC reserved bit and is recommended by JEDEC to be programmed to 0x0. + # This is a JEDEC reserved bit and is recommended by JEDEC to be programme + # d to 0x0. # PSU_DDR_PHY_MR4_RSVD_0 0x0 # DDR4 Mode Register 4 @@ -4382,7 +5324,8 @@ set psu_ddr_init_data { # Reserved. Return zeroes on reads. # PSU_DDR_PHY_MR5_RESERVED_31_16 0x0 - # These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0. + # These are JEDEC reserved bits and are recommended by JEDEC to be program + # med to 0x0. # PSU_DDR_PHY_MR5_RSVD 0x0 # Read DBI @@ -4420,13 +5363,15 @@ set psu_ddr_init_data { # Reserved. Return zeroes on reads. # PSU_DDR_PHY_MR6_RESERVED_31_16 0x0 - # These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0. + # These are JEDEC reserved bits and are recommended by JEDEC to be program + # med to 0x0. # PSU_DDR_PHY_MR6_RSVD_15_13 0x0 # CAS_n to CAS_n command delay for same bank group (tCCD_L) # PSU_DDR_PHY_MR6_TCCDL 0x2 - # These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0. + # These are JEDEC reserved bits and are recommended by JEDEC to be program + # med to 0x0. # PSU_DDR_PHY_MR6_RSVD_9_8 0x0 # VrefDQ Training Enable @@ -4446,7 +5391,8 @@ set psu_ddr_init_data { # Reserved. Return zeroes on reads. # PSU_DDR_PHY_MR11_RESERVED_31_8 0x0 - # These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0. + # These are JEDEC reserved bits and are recommended by JEDEC to be program + # med to 0x0. # PSU_DDR_PHY_MR11_RSVD 0x0 # Power Down Control @@ -4463,7 +5409,8 @@ set psu_ddr_init_data { # Reserved. Return zeroes on reads. # PSU_DDR_PHY_MR12_RESERVED_31_8 0x0 - # These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0. + # These are JEDEC reserved bits and are recommended by JEDEC to be program + # med to 0x0. # PSU_DDR_PHY_MR12_RSVD 0x0 # VREF_CA Range Select. @@ -4512,7 +5459,8 @@ set psu_ddr_init_data { # Reserved. Return zeroes on reads. # PSU_DDR_PHY_MR14_RESERVED_31_8 0x0 - # These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0. + # These are JEDEC reserved bits and are recommended by JEDEC to be program + # med to 0x0. # PSU_DDR_PHY_MR14_RSVD 0x0 # VREFDQ Range Selects. @@ -4529,7 +5477,8 @@ set psu_ddr_init_data { # Reserved. Return zeroes on reads. # PSU_DDR_PHY_MR22_RESERVED_31_8 0x0 - # These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0. + # These are JEDEC reserved bits and are recommended by JEDEC to be program + # med to 0x0. # PSU_DDR_PHY_MR22_RSVD 0x0 # CA ODT termination disable. @@ -4646,14 +5595,16 @@ set psu_ddr_init_data { # Reserved. Return zeroes on reads. # PSU_DDR_PHY_CATR0_RESERVED_31_21 0x0 - # Minimum time (in terms of number of dram clocks) between two consectuve CA calibration command + # Minimum time (in terms of number of dram clocks) between two consectuve + # CA calibration command # PSU_DDR_PHY_CATR0_CACD 0x14 # Reserved. Return zeroes on reads. # PSU_DDR_PHY_CATR0_RESERVED_15_13 0x0 - # Minimum time (in terms of number of dram clocks) PUB should wait before sampling the CA response after Calibration command ha - # been sent to the memory + # Minimum time (in terms of number of dram clocks) PUB should wait before + # sampling the CA response after Calibration command has been sent to the + # memory # PSU_DDR_PHY_CATR0_CAADR 0x10 # CA_1 Response Byte Lane 1 @@ -4665,6 +5616,48 @@ set psu_ddr_init_data { # CA Training Register 0 #(OFFSET, MASK, VALUE) (0XFD080240, 0xFFFFFFFFU ,0x00141054U) */ mask_write 0XFD080240 0xFFFFFFFF 0x00141054 + # Register : DQSDR0 @ 0XFD080250

+ + # Number of delay taps by which the DQS gate LCDL will be updated when DQS + # drift is detected + # PSU_DDR_PHY_DQSDR0_DFTDLY 0x0 + + # Drift Impedance Update + # PSU_DDR_PHY_DQSDR0_DFTZQUP 0x0 + + # Drift DDL Update + # PSU_DDR_PHY_DQSDR0_DFTDDLUP 0x0 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DQSDR0_RESERVED_25_22 0x0 + + # Drift Read Spacing + # PSU_DDR_PHY_DQSDR0_DFTRDSPC 0x0 + + # Drift Back-to-Back Reads + # PSU_DDR_PHY_DQSDR0_DFTB2BRD 0x8 + + # Drift Idle Reads + # PSU_DDR_PHY_DQSDR0_DFTIDLRD 0x8 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DQSDR0_RESERVED_11_8 0x0 + + # Gate Pulse Enable + # PSU_DDR_PHY_DQSDR0_DFTGPULSE 0x0 + + # DQS Drift Update Mode + # PSU_DDR_PHY_DQSDR0_DFTUPMODE 0x0 + + # DQS Drift Detection Mode + # PSU_DDR_PHY_DQSDR0_DFTDTMODE 0x0 + + # DQS Drift Detection Enable + # PSU_DDR_PHY_DQSDR0_DFTDTEN 0x0 + + # DQS Drift Register 0 + #(OFFSET, MASK, VALUE) (0XFD080250, 0xFFFFFFFFU ,0x00088000U) */ + mask_write 0XFD080250 0xFFFFFFFF 0x00088000 # Register : BISTLSR @ 0XFD080414

# LFSR seed for pseudo-random BIST patterns @@ -4727,7 +5720,8 @@ set psu_ddr_init_data { mask_write 0XFD080500 0xFFFFFFFF 0x30000028 # Register : ACIOCR2 @ 0XFD080508

- # Clock gating for glue logic inside CLKGEN and glue logic inside CONTROL slice + # Clock gating for glue logic inside CLKGEN and glue logic inside CONTROL + # slice # PSU_DDR_PHY_ACIOCR2_CLKGENCLKGATE 0x0 # Clock gating for Output Enable D slices [0] @@ -4842,14 +5836,15 @@ set psu_ddr_init_data { # PSU_DDR_PHY_IOVCR0_ACVREFISELRANGE 0x1 # REFSEL Control for internal AC IOs - # PSU_DDR_PHY_IOVCR0_ACVREFISEL 0x30 + # PSU_DDR_PHY_IOVCR0_ACVREFISEL 0x4e # IO VREF Control Register 0 - #(OFFSET, MASK, VALUE) (0XFD080520, 0xFFFFFFFFU ,0x0300B0B0U) */ - mask_write 0XFD080520 0xFFFFFFFF 0x0300B0B0 + #(OFFSET, MASK, VALUE) (0XFD080520, 0xFFFFFFFFU ,0x0300B0CEU) */ + mask_write 0XFD080520 0xFFFFFFFF 0x0300B0CE # Register : VTCR0 @ 0XFD080528

- # Number of ctl_clk required to meet (> 150ns) timing requirements during DRAM DQ VREF training + # Number of ctl_clk required to meet (> 150ns) timing requirements during + # DRAM DQ VREF training # PSU_DDR_PHY_VTCR0_TVREF 0x7 # DRM DQ VREF training Enable @@ -4881,7 +5876,8 @@ set psu_ddr_init_data { mask_write 0XFD080528 0xFFFFFFFF 0xF9032019 # Register : VTCR1 @ 0XFD08052C

- # Host VREF step size used during VREF training. The register value of N indicates step size of (N+1) + # Host VREF step size used during VREF training. The register value of N i + # ndicates step size of (N+1) # PSU_DDR_PHY_VTCR1_HVSS 0x0 # Reserved. Returns zeroes on reads. @@ -4905,7 +5901,8 @@ set psu_ddr_init_data { # Static Host Vref Rank Enable # PSU_DDR_PHY_VTCR1_SHREN 0x1 - # Number of ctl_clk required to meet (> 200ns) VREF Settling timing requirements during Host IO VREF training + # Number of ctl_clk required to meet (> 200ns) VREF Settling timing requir + # ements during Host IO VREF training # PSU_DDR_PHY_VTCR1_TVREFIO 0x7 # Eye LCDL Offset value for VREF training @@ -4934,13 +5931,15 @@ set psu_ddr_init_data { # Reserved. Return zeroes on reads. # PSU_DDR_PHY_ACBDLR1_RESERVED_23_22 0x0 - # Delay select for the BDL on Address A[16]. In DDR3 mode this pin is connected to WE. + # Delay select for the BDL on Address A[16]. In DDR3 mode this pin is conn + # ected to WE. # PSU_DDR_PHY_ACBDLR1_A16BD 0x0 # Reserved. Return zeroes on reads. # PSU_DDR_PHY_ACBDLR1_RESERVED_15_14 0x0 - # Delay select for the BDL on Address A[17]. When not in DDR4 modemode this pin is connected to CAS. + # Delay select for the BDL on Address A[17]. When not in DDR4 modemode thi + # s pin is connected to CAS. # PSU_DDR_PHY_ACBDLR1_A17BD 0x0 # Reserved. Return zeroes on reads. @@ -5109,7 +6108,7 @@ set psu_ddr_init_data { # PSU_DDR_PHY_ZQCR_PGWAIT_FRQB 0x11 # Programmable Wait for Frequency A - # PSU_DDR_PHY_ZQCR_PGWAIT_FRQA 0x11 + # PSU_DDR_PHY_ZQCR_PGWAIT_FRQA 0x15 # ZQ VREF Pad Enable # PSU_DDR_PHY_ZQCR_ZQREFPEN 0x0 @@ -5139,8 +6138,8 @@ set psu_ddr_init_data { # PSU_DDR_PHY_ZQCR_ZQPD 0x0 # ZQ Impedance Control Register - #(OFFSET, MASK, VALUE) (0XFD080680, 0xFFFFFFFFU ,0x008A2A58U) */ - mask_write 0XFD080680 0xFFFFFFFF 0x008A2A58 + #(OFFSET, MASK, VALUE) (0XFD080680, 0xFFFFFFFFU ,0x008AAA58U) */ + mask_write 0XFD080680 0xFFFFFFFF 0x008AAA58 # Register : ZQ0PR0 @ 0XFD080684

# Pull-down drive strength ZCTRL over-ride enable @@ -5158,7 +6157,8 @@ set psu_ddr_init_data { # Calibration segment bypass # PSU_DDR_PHY_ZQ0PR0_ZSEGBYP 0x0 - # VREF latch mode controls the mode in which the ZLE pin of the PVREF cell is driven by the PUB + # VREF latch mode controls the mode in which the ZLE pin of the PVREF cell + # is driven by the PUB # PSU_DDR_PHY_ZQ0PR0_ZLE_MODE 0x0 # Termination adjustment @@ -5174,17 +6174,19 @@ set psu_ddr_init_data { # PSU_DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT 0x7 # HOST Impedance Divide Ratio - # PSU_DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT 0x7 + # PSU_DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT 0x9 - # Impedance Divide Ratio (pulldown drive calibration during asymmetric drive strength calibration) + # Impedance Divide Ratio (pulldown drive calibration during asymmetric dri + # ve strength calibration) # PSU_DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD 0xd - # Impedance Divide Ratio (pullup drive calibration during asymmetric drive strength calibration) + # Impedance Divide Ratio (pullup drive calibration during asymmetric drive + # strength calibration) # PSU_DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU 0xd # ZQ n Impedance Control Program Register 0 - #(OFFSET, MASK, VALUE) (0XFD080684, 0xFFFFFFFFU ,0x000077DDU) */ - mask_write 0XFD080684 0xFFFFFFFF 0x000077DD + #(OFFSET, MASK, VALUE) (0XFD080684, 0xFFFFFFFFU ,0x000079DDU) */ + mask_write 0XFD080684 0xFFFFFFFF 0x000079DD # Register : ZQ0OR0 @ 0XFD080694

# Reserved. Return zeros on reads. @@ -5236,7 +6238,8 @@ set psu_ddr_init_data { # Calibration segment bypass # PSU_DDR_PHY_ZQ1PR0_ZSEGBYP 0x0 - # VREF latch mode controls the mode in which the ZLE pin of the PVREF cell is driven by the PUB + # VREF latch mode controls the mode in which the ZLE pin of the PVREF cell + # is driven by the PUB # PSU_DDR_PHY_ZQ1PR0_ZLE_MODE 0x0 # Termination adjustment @@ -5254,10 +6257,12 @@ set psu_ddr_init_data { # HOST Impedance Divide Ratio # PSU_DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT 0xb - # Impedance Divide Ratio (pulldown drive calibration during asymmetric drive strength calibration) + # Impedance Divide Ratio (pulldown drive calibration during asymmetric dri + # ve strength calibration) # PSU_DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD 0xd - # Impedance Divide Ratio (pullup drive calibration during asymmetric drive strength calibration) + # Impedance Divide Ratio (pullup drive calibration during asymmetric drive + # strength calibration) # PSU_DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU 0xb # ZQ n Impedance Control Program Register 0 @@ -5277,7 +6282,8 @@ set psu_ddr_init_data { # DQS Duty Cycle Correction # PSU_DDR_PHY_DX0GCR0_DQSDCC 0x0 - # Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY + # Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + # input for the respective bypte lane of the PHY # PSU_DDR_PHY_DX0GCR0_RDDLY 0x8 # Reserved. Return zeroes on reads. @@ -5378,17 +6384,17 @@ set psu_ddr_init_data { # PSU_DDR_PHY_DX0GCR5_RESERVED_15 0x0 # Byte Lane internal VREF Select for Rank 1 - # PSU_DDR_PHY_DX0GCR5_DXREFISELR1 0x4f + # PSU_DDR_PHY_DX0GCR5_DXREFISELR1 0x55 # Reserved. Returns zeros on reads. # PSU_DDR_PHY_DX0GCR5_RESERVED_7 0x0 # Byte Lane internal VREF Select for Rank 0 - # PSU_DDR_PHY_DX0GCR5_DXREFISELR0 0x4f + # PSU_DDR_PHY_DX0GCR5_DXREFISELR0 0x55 # DATX8 n General Configuration Register 5 - #(OFFSET, MASK, VALUE) (0XFD080714, 0xFFFFFFFFU ,0x09094F4FU) */ - mask_write 0XFD080714 0xFFFFFFFF 0x09094F4F + #(OFFSET, MASK, VALUE) (0XFD080714, 0xFFFFFFFFU ,0x09095555U) */ + mask_write 0XFD080714 0xFFFFFFFF 0x09095555 # Register : DX0GCR6 @ 0XFD080718

# Reserved. Returns zeros on reads. @@ -5418,52 +6424,6 @@ set psu_ddr_init_data { # DATX8 n General Configuration Register 6 #(OFFSET, MASK, VALUE) (0XFD080718, 0xFFFFFFFFU ,0x09092B2BU) */ mask_write 0XFD080718 0xFFFFFFFF 0x09092B2B - # Register : DX0LCDLR2 @ 0XFD080788

- - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX0LCDLR2_RESERVED_31_25 0x0 - - # Reserved. Caution, do not write to this register field. - # PSU_DDR_PHY_DX0LCDLR2_RESERVED_24_16 0x0 - - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX0LCDLR2_RESERVED_15_9 0x0 - - # Read DQS Gating Delay - # PSU_DDR_PHY_DX0LCDLR2_DQSGD 0x0 - - # DATX8 n Local Calibrated Delay Line Register 2 - #(OFFSET, MASK, VALUE) (0XFD080788, 0xFFFFFFFFU ,0x00000000U) */ - mask_write 0XFD080788 0xFFFFFFFF 0x00000000 - # Register : DX0GTR0 @ 0XFD0807C0

- - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX0GTR0_RESERVED_31_24 0x0 - - # DQ Write Path Latency Pipeline - # PSU_DDR_PHY_DX0GTR0_WDQSL 0x0 - - # Reserved. Caution, do not write to this register field. - # PSU_DDR_PHY_DX0GTR0_RESERVED_23_20 0x0 - - # Write Leveling System Latency - # PSU_DDR_PHY_DX0GTR0_WLSL 0x2 - - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX0GTR0_RESERVED_15_13 0x0 - - # Reserved. Caution, do not write to this register field. - # PSU_DDR_PHY_DX0GTR0_RESERVED_12_8 0x0 - - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX0GTR0_RESERVED_7_5 0x0 - - # DQS Gating System Latency - # PSU_DDR_PHY_DX0GTR0_DGSL 0x0 - - # DATX8 n General Timing Register 0 - #(OFFSET, MASK, VALUE) (0XFD0807C0, 0xFFFFFFFFU ,0x00020000U) */ - mask_write 0XFD0807C0 0xFFFFFFFF 0x00020000 # Register : DX1GCR0 @ 0XFD080800

# Calibration Bypass @@ -5478,7 +6438,8 @@ set psu_ddr_init_data { # DQS Duty Cycle Correction # PSU_DDR_PHY_DX1GCR0_DQSDCC 0x0 - # Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY + # Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + # input for the respective bypte lane of the PHY # PSU_DDR_PHY_DX1GCR0_RDDLY 0x8 # Reserved. Return zeroes on reads. @@ -5579,17 +6540,17 @@ set psu_ddr_init_data { # PSU_DDR_PHY_DX1GCR5_RESERVED_15 0x0 # Byte Lane internal VREF Select for Rank 1 - # PSU_DDR_PHY_DX1GCR5_DXREFISELR1 0x4f + # PSU_DDR_PHY_DX1GCR5_DXREFISELR1 0x55 # Reserved. Returns zeros on reads. # PSU_DDR_PHY_DX1GCR5_RESERVED_7 0x0 # Byte Lane internal VREF Select for Rank 0 - # PSU_DDR_PHY_DX1GCR5_DXREFISELR0 0x4f + # PSU_DDR_PHY_DX1GCR5_DXREFISELR0 0x55 # DATX8 n General Configuration Register 5 - #(OFFSET, MASK, VALUE) (0XFD080814, 0xFFFFFFFFU ,0x09094F4FU) */ - mask_write 0XFD080814 0xFFFFFFFF 0x09094F4F + #(OFFSET, MASK, VALUE) (0XFD080814, 0xFFFFFFFFU ,0x09095555U) */ + mask_write 0XFD080814 0xFFFFFFFF 0x09095555 # Register : DX1GCR6 @ 0XFD080818

# Reserved. Returns zeros on reads. @@ -5619,52 +6580,6 @@ set psu_ddr_init_data { # DATX8 n General Configuration Register 6 #(OFFSET, MASK, VALUE) (0XFD080818, 0xFFFFFFFFU ,0x09092B2BU) */ mask_write 0XFD080818 0xFFFFFFFF 0x09092B2B - # Register : DX1LCDLR2 @ 0XFD080888

- - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX1LCDLR2_RESERVED_31_25 0x0 - - # Reserved. Caution, do not write to this register field. - # PSU_DDR_PHY_DX1LCDLR2_RESERVED_24_16 0x0 - - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX1LCDLR2_RESERVED_15_9 0x0 - - # Read DQS Gating Delay - # PSU_DDR_PHY_DX1LCDLR2_DQSGD 0x0 - - # DATX8 n Local Calibrated Delay Line Register 2 - #(OFFSET, MASK, VALUE) (0XFD080888, 0xFFFFFFFFU ,0x00000000U) */ - mask_write 0XFD080888 0xFFFFFFFF 0x00000000 - # Register : DX1GTR0 @ 0XFD0808C0

- - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX1GTR0_RESERVED_31_24 0x0 - - # DQ Write Path Latency Pipeline - # PSU_DDR_PHY_DX1GTR0_WDQSL 0x0 - - # Reserved. Caution, do not write to this register field. - # PSU_DDR_PHY_DX1GTR0_RESERVED_23_20 0x0 - - # Write Leveling System Latency - # PSU_DDR_PHY_DX1GTR0_WLSL 0x2 - - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX1GTR0_RESERVED_15_13 0x0 - - # Reserved. Caution, do not write to this register field. - # PSU_DDR_PHY_DX1GTR0_RESERVED_12_8 0x0 - - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX1GTR0_RESERVED_7_5 0x0 - - # DQS Gating System Latency - # PSU_DDR_PHY_DX1GTR0_DGSL 0x0 - - # DATX8 n General Timing Register 0 - #(OFFSET, MASK, VALUE) (0XFD0808C0, 0xFFFFFFFFU ,0x00020000U) */ - mask_write 0XFD0808C0 0xFFFFFFFF 0x00020000 # Register : DX2GCR0 @ 0XFD080900

# Calibration Bypass @@ -5679,7 +6594,8 @@ set psu_ddr_init_data { # DQS Duty Cycle Correction # PSU_DDR_PHY_DX2GCR0_DQSDCC 0x0 - # Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY + # Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + # input for the respective bypte lane of the PHY # PSU_DDR_PHY_DX2GCR0_RDDLY 0x8 # Reserved. Return zeroes on reads. @@ -5815,17 +6731,17 @@ set psu_ddr_init_data { # PSU_DDR_PHY_DX2GCR5_RESERVED_15 0x0 # Byte Lane internal VREF Select for Rank 1 - # PSU_DDR_PHY_DX2GCR5_DXREFISELR1 0x4f + # PSU_DDR_PHY_DX2GCR5_DXREFISELR1 0x55 # Reserved. Returns zeros on reads. # PSU_DDR_PHY_DX2GCR5_RESERVED_7 0x0 # Byte Lane internal VREF Select for Rank 0 - # PSU_DDR_PHY_DX2GCR5_DXREFISELR0 0x4f + # PSU_DDR_PHY_DX2GCR5_DXREFISELR0 0x55 # DATX8 n General Configuration Register 5 - #(OFFSET, MASK, VALUE) (0XFD080914, 0xFFFFFFFFU ,0x09094F4FU) */ - mask_write 0XFD080914 0xFFFFFFFF 0x09094F4F + #(OFFSET, MASK, VALUE) (0XFD080914, 0xFFFFFFFFU ,0x09095555U) */ + mask_write 0XFD080914 0xFFFFFFFF 0x09095555 # Register : DX2GCR6 @ 0XFD080918

# Reserved. Returns zeros on reads. @@ -5855,52 +6771,6 @@ set psu_ddr_init_data { # DATX8 n General Configuration Register 6 #(OFFSET, MASK, VALUE) (0XFD080918, 0xFFFFFFFFU ,0x09092B2BU) */ mask_write 0XFD080918 0xFFFFFFFF 0x09092B2B - # Register : DX2LCDLR2 @ 0XFD080988

- - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX2LCDLR2_RESERVED_31_25 0x0 - - # Reserved. Caution, do not write to this register field. - # PSU_DDR_PHY_DX2LCDLR2_RESERVED_24_16 0x0 - - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX2LCDLR2_RESERVED_15_9 0x0 - - # Read DQS Gating Delay - # PSU_DDR_PHY_DX2LCDLR2_DQSGD 0x0 - - # DATX8 n Local Calibrated Delay Line Register 2 - #(OFFSET, MASK, VALUE) (0XFD080988, 0xFFFFFFFFU ,0x00000000U) */ - mask_write 0XFD080988 0xFFFFFFFF 0x00000000 - # Register : DX2GTR0 @ 0XFD0809C0

- - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX2GTR0_RESERVED_31_24 0x0 - - # DQ Write Path Latency Pipeline - # PSU_DDR_PHY_DX2GTR0_WDQSL 0x0 - - # Reserved. Caution, do not write to this register field. - # PSU_DDR_PHY_DX2GTR0_RESERVED_23_20 0x0 - - # Write Leveling System Latency - # PSU_DDR_PHY_DX2GTR0_WLSL 0x2 - - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX2GTR0_RESERVED_15_13 0x0 - - # Reserved. Caution, do not write to this register field. - # PSU_DDR_PHY_DX2GTR0_RESERVED_12_8 0x0 - - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX2GTR0_RESERVED_7_5 0x0 - - # DQS Gating System Latency - # PSU_DDR_PHY_DX2GTR0_DGSL 0x0 - - # DATX8 n General Timing Register 0 - #(OFFSET, MASK, VALUE) (0XFD0809C0, 0xFFFFFFFFU ,0x00020000U) */ - mask_write 0XFD0809C0 0xFFFFFFFF 0x00020000 # Register : DX3GCR0 @ 0XFD080A00

# Calibration Bypass @@ -5915,7 +6785,8 @@ set psu_ddr_init_data { # DQS Duty Cycle Correction # PSU_DDR_PHY_DX3GCR0_DQSDCC 0x0 - # Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY + # Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + # input for the respective bypte lane of the PHY # PSU_DDR_PHY_DX3GCR0_RDDLY 0x8 # Reserved. Return zeroes on reads. @@ -6051,17 +6922,17 @@ set psu_ddr_init_data { # PSU_DDR_PHY_DX3GCR5_RESERVED_15 0x0 # Byte Lane internal VREF Select for Rank 1 - # PSU_DDR_PHY_DX3GCR5_DXREFISELR1 0x4f + # PSU_DDR_PHY_DX3GCR5_DXREFISELR1 0x55 # Reserved. Returns zeros on reads. # PSU_DDR_PHY_DX3GCR5_RESERVED_7 0x0 # Byte Lane internal VREF Select for Rank 0 - # PSU_DDR_PHY_DX3GCR5_DXREFISELR0 0x4f + # PSU_DDR_PHY_DX3GCR5_DXREFISELR0 0x55 # DATX8 n General Configuration Register 5 - #(OFFSET, MASK, VALUE) (0XFD080A14, 0xFFFFFFFFU ,0x09094F4FU) */ - mask_write 0XFD080A14 0xFFFFFFFF 0x09094F4F + #(OFFSET, MASK, VALUE) (0XFD080A14, 0xFFFFFFFFU ,0x09095555U) */ + mask_write 0XFD080A14 0xFFFFFFFF 0x09095555 # Register : DX3GCR6 @ 0XFD080A18

# Reserved. Returns zeros on reads. @@ -6091,52 +6962,6 @@ set psu_ddr_init_data { # DATX8 n General Configuration Register 6 #(OFFSET, MASK, VALUE) (0XFD080A18, 0xFFFFFFFFU ,0x09092B2BU) */ mask_write 0XFD080A18 0xFFFFFFFF 0x09092B2B - # Register : DX3LCDLR2 @ 0XFD080A88

- - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX3LCDLR2_RESERVED_31_25 0x0 - - # Reserved. Caution, do not write to this register field. - # PSU_DDR_PHY_DX3LCDLR2_RESERVED_24_16 0x0 - - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX3LCDLR2_RESERVED_15_9 0x0 - - # Read DQS Gating Delay - # PSU_DDR_PHY_DX3LCDLR2_DQSGD 0x0 - - # DATX8 n Local Calibrated Delay Line Register 2 - #(OFFSET, MASK, VALUE) (0XFD080A88, 0xFFFFFFFFU ,0x00000000U) */ - mask_write 0XFD080A88 0xFFFFFFFF 0x00000000 - # Register : DX3GTR0 @ 0XFD080AC0

- - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX3GTR0_RESERVED_31_24 0x0 - - # DQ Write Path Latency Pipeline - # PSU_DDR_PHY_DX3GTR0_WDQSL 0x0 - - # Reserved. Caution, do not write to this register field. - # PSU_DDR_PHY_DX3GTR0_RESERVED_23_20 0x0 - - # Write Leveling System Latency - # PSU_DDR_PHY_DX3GTR0_WLSL 0x2 - - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX3GTR0_RESERVED_15_13 0x0 - - # Reserved. Caution, do not write to this register field. - # PSU_DDR_PHY_DX3GTR0_RESERVED_12_8 0x0 - - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX3GTR0_RESERVED_7_5 0x0 - - # DQS Gating System Latency - # PSU_DDR_PHY_DX3GTR0_DGSL 0x0 - - # DATX8 n General Timing Register 0 - #(OFFSET, MASK, VALUE) (0XFD080AC0, 0xFFFFFFFFU ,0x00020000U) */ - mask_write 0XFD080AC0 0xFFFFFFFF 0x00020000 # Register : DX4GCR0 @ 0XFD080B00

# Calibration Bypass @@ -6151,7 +6976,8 @@ set psu_ddr_init_data { # DQS Duty Cycle Correction # PSU_DDR_PHY_DX4GCR0_DQSDCC 0x0 - # Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY + # Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + # input for the respective bypte lane of the PHY # PSU_DDR_PHY_DX4GCR0_RDDLY 0x8 # Reserved. Return zeroes on reads. @@ -6287,17 +7113,17 @@ set psu_ddr_init_data { # PSU_DDR_PHY_DX4GCR5_RESERVED_15 0x0 # Byte Lane internal VREF Select for Rank 1 - # PSU_DDR_PHY_DX4GCR5_DXREFISELR1 0x4f + # PSU_DDR_PHY_DX4GCR5_DXREFISELR1 0x55 # Reserved. Returns zeros on reads. # PSU_DDR_PHY_DX4GCR5_RESERVED_7 0x0 # Byte Lane internal VREF Select for Rank 0 - # PSU_DDR_PHY_DX4GCR5_DXREFISELR0 0x4f + # PSU_DDR_PHY_DX4GCR5_DXREFISELR0 0x55 # DATX8 n General Configuration Register 5 - #(OFFSET, MASK, VALUE) (0XFD080B14, 0xFFFFFFFFU ,0x09094F4FU) */ - mask_write 0XFD080B14 0xFFFFFFFF 0x09094F4F + #(OFFSET, MASK, VALUE) (0XFD080B14, 0xFFFFFFFFU ,0x09095555U) */ + mask_write 0XFD080B14 0xFFFFFFFF 0x09095555 # Register : DX4GCR6 @ 0XFD080B18

# Reserved. Returns zeros on reads. @@ -6327,52 +7153,6 @@ set psu_ddr_init_data { # DATX8 n General Configuration Register 6 #(OFFSET, MASK, VALUE) (0XFD080B18, 0xFFFFFFFFU ,0x09092B2BU) */ mask_write 0XFD080B18 0xFFFFFFFF 0x09092B2B - # Register : DX4LCDLR2 @ 0XFD080B88

- - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX4LCDLR2_RESERVED_31_25 0x0 - - # Reserved. Caution, do not write to this register field. - # PSU_DDR_PHY_DX4LCDLR2_RESERVED_24_16 0x0 - - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX4LCDLR2_RESERVED_15_9 0x0 - - # Read DQS Gating Delay - # PSU_DDR_PHY_DX4LCDLR2_DQSGD 0x0 - - # DATX8 n Local Calibrated Delay Line Register 2 - #(OFFSET, MASK, VALUE) (0XFD080B88, 0xFFFFFFFFU ,0x00000000U) */ - mask_write 0XFD080B88 0xFFFFFFFF 0x00000000 - # Register : DX4GTR0 @ 0XFD080BC0

- - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX4GTR0_RESERVED_31_24 0x0 - - # DQ Write Path Latency Pipeline - # PSU_DDR_PHY_DX4GTR0_WDQSL 0x0 - - # Reserved. Caution, do not write to this register field. - # PSU_DDR_PHY_DX4GTR0_RESERVED_23_20 0x0 - - # Write Leveling System Latency - # PSU_DDR_PHY_DX4GTR0_WLSL 0x2 - - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX4GTR0_RESERVED_15_13 0x0 - - # Reserved. Caution, do not write to this register field. - # PSU_DDR_PHY_DX4GTR0_RESERVED_12_8 0x0 - - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX4GTR0_RESERVED_7_5 0x0 - - # DQS Gating System Latency - # PSU_DDR_PHY_DX4GTR0_DGSL 0x0 - - # DATX8 n General Timing Register 0 - #(OFFSET, MASK, VALUE) (0XFD080BC0, 0xFFFFFFFFU ,0x00020000U) */ - mask_write 0XFD080BC0 0xFFFFFFFF 0x00020000 # Register : DX5GCR0 @ 0XFD080C00

# Calibration Bypass @@ -6387,7 +7167,8 @@ set psu_ddr_init_data { # DQS Duty Cycle Correction # PSU_DDR_PHY_DX5GCR0_DQSDCC 0x0 - # Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY + # Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + # input for the respective bypte lane of the PHY # PSU_DDR_PHY_DX5GCR0_RDDLY 0x8 # Reserved. Return zeroes on reads. @@ -6523,17 +7304,17 @@ set psu_ddr_init_data { # PSU_DDR_PHY_DX5GCR5_RESERVED_15 0x0 # Byte Lane internal VREF Select for Rank 1 - # PSU_DDR_PHY_DX5GCR5_DXREFISELR1 0x4f + # PSU_DDR_PHY_DX5GCR5_DXREFISELR1 0x55 # Reserved. Returns zeros on reads. # PSU_DDR_PHY_DX5GCR5_RESERVED_7 0x0 # Byte Lane internal VREF Select for Rank 0 - # PSU_DDR_PHY_DX5GCR5_DXREFISELR0 0x4f + # PSU_DDR_PHY_DX5GCR5_DXREFISELR0 0x55 # DATX8 n General Configuration Register 5 - #(OFFSET, MASK, VALUE) (0XFD080C14, 0xFFFFFFFFU ,0x09094F4FU) */ - mask_write 0XFD080C14 0xFFFFFFFF 0x09094F4F + #(OFFSET, MASK, VALUE) (0XFD080C14, 0xFFFFFFFFU ,0x09095555U) */ + mask_write 0XFD080C14 0xFFFFFFFF 0x09095555 # Register : DX5GCR6 @ 0XFD080C18

# Reserved. Returns zeros on reads. @@ -6563,52 +7344,6 @@ set psu_ddr_init_data { # DATX8 n General Configuration Register 6 #(OFFSET, MASK, VALUE) (0XFD080C18, 0xFFFFFFFFU ,0x09092B2BU) */ mask_write 0XFD080C18 0xFFFFFFFF 0x09092B2B - # Register : DX5LCDLR2 @ 0XFD080C88

- - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX5LCDLR2_RESERVED_31_25 0x0 - - # Reserved. Caution, do not write to this register field. - # PSU_DDR_PHY_DX5LCDLR2_RESERVED_24_16 0x0 - - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX5LCDLR2_RESERVED_15_9 0x0 - - # Read DQS Gating Delay - # PSU_DDR_PHY_DX5LCDLR2_DQSGD 0x0 - - # DATX8 n Local Calibrated Delay Line Register 2 - #(OFFSET, MASK, VALUE) (0XFD080C88, 0xFFFFFFFFU ,0x00000000U) */ - mask_write 0XFD080C88 0xFFFFFFFF 0x00000000 - # Register : DX5GTR0 @ 0XFD080CC0

- - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX5GTR0_RESERVED_31_24 0x0 - - # DQ Write Path Latency Pipeline - # PSU_DDR_PHY_DX5GTR0_WDQSL 0x0 - - # Reserved. Caution, do not write to this register field. - # PSU_DDR_PHY_DX5GTR0_RESERVED_23_20 0x0 - - # Write Leveling System Latency - # PSU_DDR_PHY_DX5GTR0_WLSL 0x2 - - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX5GTR0_RESERVED_15_13 0x0 - - # Reserved. Caution, do not write to this register field. - # PSU_DDR_PHY_DX5GTR0_RESERVED_12_8 0x0 - - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX5GTR0_RESERVED_7_5 0x0 - - # DQS Gating System Latency - # PSU_DDR_PHY_DX5GTR0_DGSL 0x0 - - # DATX8 n General Timing Register 0 - #(OFFSET, MASK, VALUE) (0XFD080CC0, 0xFFFFFFFFU ,0x00020000U) */ - mask_write 0XFD080CC0 0xFFFFFFFF 0x00020000 # Register : DX6GCR0 @ 0XFD080D00

# Calibration Bypass @@ -6623,7 +7358,8 @@ set psu_ddr_init_data { # DQS Duty Cycle Correction # PSU_DDR_PHY_DX6GCR0_DQSDCC 0x0 - # Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY + # Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + # input for the respective bypte lane of the PHY # PSU_DDR_PHY_DX6GCR0_RDDLY 0x8 # Reserved. Return zeroes on reads. @@ -6759,17 +7495,17 @@ set psu_ddr_init_data { # PSU_DDR_PHY_DX6GCR5_RESERVED_15 0x0 # Byte Lane internal VREF Select for Rank 1 - # PSU_DDR_PHY_DX6GCR5_DXREFISELR1 0x4f + # PSU_DDR_PHY_DX6GCR5_DXREFISELR1 0x55 # Reserved. Returns zeros on reads. # PSU_DDR_PHY_DX6GCR5_RESERVED_7 0x0 # Byte Lane internal VREF Select for Rank 0 - # PSU_DDR_PHY_DX6GCR5_DXREFISELR0 0x4f + # PSU_DDR_PHY_DX6GCR5_DXREFISELR0 0x55 # DATX8 n General Configuration Register 5 - #(OFFSET, MASK, VALUE) (0XFD080D14, 0xFFFFFFFFU ,0x09094F4FU) */ - mask_write 0XFD080D14 0xFFFFFFFF 0x09094F4F + #(OFFSET, MASK, VALUE) (0XFD080D14, 0xFFFFFFFFU ,0x09095555U) */ + mask_write 0XFD080D14 0xFFFFFFFF 0x09095555 # Register : DX6GCR6 @ 0XFD080D18

# Reserved. Returns zeros on reads. @@ -6799,52 +7535,6 @@ set psu_ddr_init_data { # DATX8 n General Configuration Register 6 #(OFFSET, MASK, VALUE) (0XFD080D18, 0xFFFFFFFFU ,0x09092B2BU) */ mask_write 0XFD080D18 0xFFFFFFFF 0x09092B2B - # Register : DX6LCDLR2 @ 0XFD080D88

- - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX6LCDLR2_RESERVED_31_25 0x0 - - # Reserved. Caution, do not write to this register field. - # PSU_DDR_PHY_DX6LCDLR2_RESERVED_24_16 0x0 - - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX6LCDLR2_RESERVED_15_9 0x0 - - # Read DQS Gating Delay - # PSU_DDR_PHY_DX6LCDLR2_DQSGD 0x0 - - # DATX8 n Local Calibrated Delay Line Register 2 - #(OFFSET, MASK, VALUE) (0XFD080D88, 0xFFFFFFFFU ,0x00000000U) */ - mask_write 0XFD080D88 0xFFFFFFFF 0x00000000 - # Register : DX6GTR0 @ 0XFD080DC0

- - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX6GTR0_RESERVED_31_24 0x0 - - # DQ Write Path Latency Pipeline - # PSU_DDR_PHY_DX6GTR0_WDQSL 0x0 - - # Reserved. Caution, do not write to this register field. - # PSU_DDR_PHY_DX6GTR0_RESERVED_23_20 0x0 - - # Write Leveling System Latency - # PSU_DDR_PHY_DX6GTR0_WLSL 0x2 - - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX6GTR0_RESERVED_15_13 0x0 - - # Reserved. Caution, do not write to this register field. - # PSU_DDR_PHY_DX6GTR0_RESERVED_12_8 0x0 - - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX6GTR0_RESERVED_7_5 0x0 - - # DQS Gating System Latency - # PSU_DDR_PHY_DX6GTR0_DGSL 0x0 - - # DATX8 n General Timing Register 0 - #(OFFSET, MASK, VALUE) (0XFD080DC0, 0xFFFFFFFFU ,0x00020000U) */ - mask_write 0XFD080DC0 0xFFFFFFFF 0x00020000 # Register : DX7GCR0 @ 0XFD080E00

# Calibration Bypass @@ -6859,7 +7549,8 @@ set psu_ddr_init_data { # DQS Duty Cycle Correction # PSU_DDR_PHY_DX7GCR0_DQSDCC 0x0 - # Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY + # Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + # input for the respective bypte lane of the PHY # PSU_DDR_PHY_DX7GCR0_RDDLY 0x8 # Reserved. Return zeroes on reads. @@ -6995,17 +7686,17 @@ set psu_ddr_init_data { # PSU_DDR_PHY_DX7GCR5_RESERVED_15 0x0 # Byte Lane internal VREF Select for Rank 1 - # PSU_DDR_PHY_DX7GCR5_DXREFISELR1 0x4f + # PSU_DDR_PHY_DX7GCR5_DXREFISELR1 0x55 # Reserved. Returns zeros on reads. # PSU_DDR_PHY_DX7GCR5_RESERVED_7 0x0 # Byte Lane internal VREF Select for Rank 0 - # PSU_DDR_PHY_DX7GCR5_DXREFISELR0 0x4f + # PSU_DDR_PHY_DX7GCR5_DXREFISELR0 0x55 # DATX8 n General Configuration Register 5 - #(OFFSET, MASK, VALUE) (0XFD080E14, 0xFFFFFFFFU ,0x09094F4FU) */ - mask_write 0XFD080E14 0xFFFFFFFF 0x09094F4F + #(OFFSET, MASK, VALUE) (0XFD080E14, 0xFFFFFFFFU ,0x09095555U) */ + mask_write 0XFD080E14 0xFFFFFFFF 0x09095555 # Register : DX7GCR6 @ 0XFD080E18

# Reserved. Returns zeros on reads. @@ -7035,52 +7726,6 @@ set psu_ddr_init_data { # DATX8 n General Configuration Register 6 #(OFFSET, MASK, VALUE) (0XFD080E18, 0xFFFFFFFFU ,0x09092B2BU) */ mask_write 0XFD080E18 0xFFFFFFFF 0x09092B2B - # Register : DX7LCDLR2 @ 0XFD080E88

- - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX7LCDLR2_RESERVED_31_25 0x0 - - # Reserved. Caution, do not write to this register field. - # PSU_DDR_PHY_DX7LCDLR2_RESERVED_24_16 0x0 - - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX7LCDLR2_RESERVED_15_9 0x0 - - # Read DQS Gating Delay - # PSU_DDR_PHY_DX7LCDLR2_DQSGD 0xa - - # DATX8 n Local Calibrated Delay Line Register 2 - #(OFFSET, MASK, VALUE) (0XFD080E88, 0xFFFFFFFFU ,0x0000000AU) */ - mask_write 0XFD080E88 0xFFFFFFFF 0x0000000A - # Register : DX7GTR0 @ 0XFD080EC0

- - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX7GTR0_RESERVED_31_24 0x0 - - # DQ Write Path Latency Pipeline - # PSU_DDR_PHY_DX7GTR0_WDQSL 0x0 - - # Reserved. Caution, do not write to this register field. - # PSU_DDR_PHY_DX7GTR0_RESERVED_23_20 0x0 - - # Write Leveling System Latency - # PSU_DDR_PHY_DX7GTR0_WLSL 0x2 - - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX7GTR0_RESERVED_15_13 0x0 - - # Reserved. Caution, do not write to this register field. - # PSU_DDR_PHY_DX7GTR0_RESERVED_12_8 0x0 - - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX7GTR0_RESERVED_7_5 0x0 - - # DQS Gating System Latency - # PSU_DDR_PHY_DX7GTR0_DGSL 0x0 - - # DATX8 n General Timing Register 0 - #(OFFSET, MASK, VALUE) (0XFD080EC0, 0xFFFFFFFFU ,0x00020000U) */ - mask_write 0XFD080EC0 0xFFFFFFFF 0x00020000 # Register : DX8GCR0 @ 0XFD080F00

# Calibration Bypass @@ -7095,7 +7740,8 @@ set psu_ddr_init_data { # DQS Duty Cycle Correction # PSU_DDR_PHY_DX8GCR0_DQSDCC 0x0 - # Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY + # Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + # input for the respective bypte lane of the PHY # PSU_DDR_PHY_DX8GCR0_RDDLY 0x8 # Reserved. Return zeroes on reads. @@ -7231,17 +7877,17 @@ set psu_ddr_init_data { # PSU_DDR_PHY_DX8GCR5_RESERVED_15 0x0 # Byte Lane internal VREF Select for Rank 1 - # PSU_DDR_PHY_DX8GCR5_DXREFISELR1 0x4f + # PSU_DDR_PHY_DX8GCR5_DXREFISELR1 0x55 # Reserved. Returns zeros on reads. # PSU_DDR_PHY_DX8GCR5_RESERVED_7 0x0 # Byte Lane internal VREF Select for Rank 0 - # PSU_DDR_PHY_DX8GCR5_DXREFISELR0 0x4f + # PSU_DDR_PHY_DX8GCR5_DXREFISELR0 0x55 # DATX8 n General Configuration Register 5 - #(OFFSET, MASK, VALUE) (0XFD080F14, 0xFFFFFFFFU ,0x09094F4FU) */ - mask_write 0XFD080F14 0xFFFFFFFF 0x09094F4F + #(OFFSET, MASK, VALUE) (0XFD080F14, 0xFFFFFFFFU ,0x09095555U) */ + mask_write 0XFD080F14 0xFFFFFFFF 0x09095555 # Register : DX8GCR6 @ 0XFD080F18

# Reserved. Returns zeros on reads. @@ -7271,52 +7917,6 @@ set psu_ddr_init_data { # DATX8 n General Configuration Register 6 #(OFFSET, MASK, VALUE) (0XFD080F18, 0xFFFFFFFFU ,0x09092B2BU) */ mask_write 0XFD080F18 0xFFFFFFFF 0x09092B2B - # Register : DX8LCDLR2 @ 0XFD080F88

- - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX8LCDLR2_RESERVED_31_25 0x0 - - # Reserved. Caution, do not write to this register field. - # PSU_DDR_PHY_DX8LCDLR2_RESERVED_24_16 0x0 - - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX8LCDLR2_RESERVED_15_9 0x0 - - # Read DQS Gating Delay - # PSU_DDR_PHY_DX8LCDLR2_DQSGD 0x0 - - # DATX8 n Local Calibrated Delay Line Register 2 - #(OFFSET, MASK, VALUE) (0XFD080F88, 0xFFFFFFFFU ,0x00000000U) */ - mask_write 0XFD080F88 0xFFFFFFFF 0x00000000 - # Register : DX8GTR0 @ 0XFD080FC0

- - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX8GTR0_RESERVED_31_24 0x0 - - # DQ Write Path Latency Pipeline - # PSU_DDR_PHY_DX8GTR0_WDQSL 0x0 - - # Reserved. Caution, do not write to this register field. - # PSU_DDR_PHY_DX8GTR0_RESERVED_23_20 0x0 - - # Write Leveling System Latency - # PSU_DDR_PHY_DX8GTR0_WLSL 0x2 - - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX8GTR0_RESERVED_15_13 0x0 - - # Reserved. Caution, do not write to this register field. - # PSU_DDR_PHY_DX8GTR0_RESERVED_12_8 0x0 - - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX8GTR0_RESERVED_7_5 0x0 - - # DQS Gating System Latency - # PSU_DDR_PHY_DX8GTR0_DGSL 0x0 - - # DATX8 n General Timing Register 0 - #(OFFSET, MASK, VALUE) (0XFD080FC0, 0xFFFFFFFFU ,0x00020000U) */ - mask_write 0XFD080FC0 0xFFFFFFFF 0x00020000 # Register : DX8SL0OSC @ 0XFD081400

# Reserved. Return zeroes on reads. @@ -7331,7 +7931,8 @@ set psu_ddr_init_data { # Enable Clock Gating for DX ctl_clk # PSU_DDR_PHY_DX8SL0OSC_GATEDXCTLCLK 0x2 - # Selects the level to which clocks will be stalled when clock gating is enabled. + # Selects the level to which clocks will be stalled when clock gating is e + # nabled. # PSU_DDR_PHY_DX8SL0OSC_CLKLEVEL 0x0 # Loopback Mode @@ -7376,9 +7977,54 @@ set psu_ddr_init_data { # Oscillator Enable # PSU_DDR_PHY_DX8SL0OSC_OSCEN 0x0 - # DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register + # DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Lo + # opback, and Gated Clock Control Register #(OFFSET, MASK, VALUE) (0XFD081400, 0xFFFFFFFFU ,0x2A019FFEU) */ mask_write 0XFD081400 0xFFFFFFFF 0x2A019FFE + # Register : DX8SL0PLLCR0 @ 0XFD081404

+ + # PLL Bypass + # PSU_DDR_PHY_DX8SL0PLLCR0_PLLBYP 0x0 + + # PLL Reset + # PSU_DDR_PHY_DX8SL0PLLCR0_PLLRST 0x0 + + # PLL Power Down + # PSU_DDR_PHY_DX8SL0PLLCR0_PLLPD 0x0 + + # Reference Stop Mode + # PSU_DDR_PHY_DX8SL0PLLCR0_RSTOPM 0x0 + + # PLL Frequency Select + # PSU_DDR_PHY_DX8SL0PLLCR0_FRQSEL 0x1 + + # Relock Mode + # PSU_DDR_PHY_DX8SL0PLLCR0_RLOCKM 0x0 + + # Charge Pump Proportional Current Control + # PSU_DDR_PHY_DX8SL0PLLCR0_CPPC 0x8 + + # Charge Pump Integrating Current Control + # PSU_DDR_PHY_DX8SL0PLLCR0_CPIC 0x0 + + # Gear Shift + # PSU_DDR_PHY_DX8SL0PLLCR0_GSHIFT 0x0 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX8SL0PLLCR0_RESERVED_11_9 0x0 + + # Analog Test Enable (ATOEN) + # PSU_DDR_PHY_DX8SL0PLLCR0_ATOEN 0x0 + + # Analog Test Control + # PSU_DDR_PHY_DX8SL0PLLCR0_ATC 0x0 + + # Digital Test Control + # PSU_DDR_PHY_DX8SL0PLLCR0_DTC 0x0 + + # DAXT8 0-1 PLL Control Register 0 + #(OFFSET, MASK, VALUE) (0XFD081404, 0xFFFFFFFFU ,0x01100000U) */ + mask_write 0XFD081404 0xFFFFFFFF 0x01100000 # Register : DX8SL0DQSCTL @ 0XFD08141C

# Reserved. Return zeroes on reads. @@ -7516,7 +8162,8 @@ set psu_ddr_init_data { # Enable Clock Gating for DX ctl_clk # PSU_DDR_PHY_DX8SL1OSC_GATEDXCTLCLK 0x2 - # Selects the level to which clocks will be stalled when clock gating is enabled. + # Selects the level to which clocks will be stalled when clock gating is e + # nabled. # PSU_DDR_PHY_DX8SL1OSC_CLKLEVEL 0x0 # Loopback Mode @@ -7561,9 +8208,54 @@ set psu_ddr_init_data { # Oscillator Enable # PSU_DDR_PHY_DX8SL1OSC_OSCEN 0x0 - # DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register + # DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Lo + # opback, and Gated Clock Control Register #(OFFSET, MASK, VALUE) (0XFD081440, 0xFFFFFFFFU ,0x2A019FFEU) */ mask_write 0XFD081440 0xFFFFFFFF 0x2A019FFE + # Register : DX8SL1PLLCR0 @ 0XFD081444

+ + # PLL Bypass + # PSU_DDR_PHY_DX8SL1PLLCR0_PLLBYP 0x0 + + # PLL Reset + # PSU_DDR_PHY_DX8SL1PLLCR0_PLLRST 0x0 + + # PLL Power Down + # PSU_DDR_PHY_DX8SL1PLLCR0_PLLPD 0x0 + + # Reference Stop Mode + # PSU_DDR_PHY_DX8SL1PLLCR0_RSTOPM 0x0 + + # PLL Frequency Select + # PSU_DDR_PHY_DX8SL1PLLCR0_FRQSEL 0x1 + + # Relock Mode + # PSU_DDR_PHY_DX8SL1PLLCR0_RLOCKM 0x0 + + # Charge Pump Proportional Current Control + # PSU_DDR_PHY_DX8SL1PLLCR0_CPPC 0x8 + + # Charge Pump Integrating Current Control + # PSU_DDR_PHY_DX8SL1PLLCR0_CPIC 0x0 + + # Gear Shift + # PSU_DDR_PHY_DX8SL1PLLCR0_GSHIFT 0x0 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX8SL1PLLCR0_RESERVED_11_9 0x0 + + # Analog Test Enable (ATOEN) + # PSU_DDR_PHY_DX8SL1PLLCR0_ATOEN 0x0 + + # Analog Test Control + # PSU_DDR_PHY_DX8SL1PLLCR0_ATC 0x0 + + # Digital Test Control + # PSU_DDR_PHY_DX8SL1PLLCR0_DTC 0x0 + + # DAXT8 0-1 PLL Control Register 0 + #(OFFSET, MASK, VALUE) (0XFD081444, 0xFFFFFFFFU ,0x01100000U) */ + mask_write 0XFD081444 0xFFFFFFFF 0x01100000 # Register : DX8SL1DQSCTL @ 0XFD08145C

# Reserved. Return zeroes on reads. @@ -7701,7 +8393,8 @@ set psu_ddr_init_data { # Enable Clock Gating for DX ctl_clk # PSU_DDR_PHY_DX8SL2OSC_GATEDXCTLCLK 0x2 - # Selects the level to which clocks will be stalled when clock gating is enabled. + # Selects the level to which clocks will be stalled when clock gating is e + # nabled. # PSU_DDR_PHY_DX8SL2OSC_CLKLEVEL 0x0 # Loopback Mode @@ -7746,9 +8439,54 @@ set psu_ddr_init_data { # Oscillator Enable # PSU_DDR_PHY_DX8SL2OSC_OSCEN 0x0 - # DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register + # DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Lo + # opback, and Gated Clock Control Register #(OFFSET, MASK, VALUE) (0XFD081480, 0xFFFFFFFFU ,0x2A019FFEU) */ mask_write 0XFD081480 0xFFFFFFFF 0x2A019FFE + # Register : DX8SL2PLLCR0 @ 0XFD081484

+ + # PLL Bypass + # PSU_DDR_PHY_DX8SL2PLLCR0_PLLBYP 0x0 + + # PLL Reset + # PSU_DDR_PHY_DX8SL2PLLCR0_PLLRST 0x0 + + # PLL Power Down + # PSU_DDR_PHY_DX8SL2PLLCR0_PLLPD 0x0 + + # Reference Stop Mode + # PSU_DDR_PHY_DX8SL2PLLCR0_RSTOPM 0x0 + + # PLL Frequency Select + # PSU_DDR_PHY_DX8SL2PLLCR0_FRQSEL 0x1 + + # Relock Mode + # PSU_DDR_PHY_DX8SL2PLLCR0_RLOCKM 0x0 + + # Charge Pump Proportional Current Control + # PSU_DDR_PHY_DX8SL2PLLCR0_CPPC 0x8 + + # Charge Pump Integrating Current Control + # PSU_DDR_PHY_DX8SL2PLLCR0_CPIC 0x0 + + # Gear Shift + # PSU_DDR_PHY_DX8SL2PLLCR0_GSHIFT 0x0 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX8SL2PLLCR0_RESERVED_11_9 0x0 + + # Analog Test Enable (ATOEN) + # PSU_DDR_PHY_DX8SL2PLLCR0_ATOEN 0x0 + + # Analog Test Control + # PSU_DDR_PHY_DX8SL2PLLCR0_ATC 0x0 + + # Digital Test Control + # PSU_DDR_PHY_DX8SL2PLLCR0_DTC 0x0 + + # DAXT8 0-1 PLL Control Register 0 + #(OFFSET, MASK, VALUE) (0XFD081484, 0xFFFFFFFFU ,0x01100000U) */ + mask_write 0XFD081484 0xFFFFFFFF 0x01100000 # Register : DX8SL2DQSCTL @ 0XFD08149C

# Reserved. Return zeroes on reads. @@ -7886,7 +8624,8 @@ set psu_ddr_init_data { # Enable Clock Gating for DX ctl_clk # PSU_DDR_PHY_DX8SL3OSC_GATEDXCTLCLK 0x2 - # Selects the level to which clocks will be stalled when clock gating is enabled. + # Selects the level to which clocks will be stalled when clock gating is e + # nabled. # PSU_DDR_PHY_DX8SL3OSC_CLKLEVEL 0x0 # Loopback Mode @@ -7931,9 +8670,54 @@ set psu_ddr_init_data { # Oscillator Enable # PSU_DDR_PHY_DX8SL3OSC_OSCEN 0x0 - # DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register + # DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Lo + # opback, and Gated Clock Control Register #(OFFSET, MASK, VALUE) (0XFD0814C0, 0xFFFFFFFFU ,0x2A019FFEU) */ mask_write 0XFD0814C0 0xFFFFFFFF 0x2A019FFE + # Register : DX8SL3PLLCR0 @ 0XFD0814C4

+ + # PLL Bypass + # PSU_DDR_PHY_DX8SL3PLLCR0_PLLBYP 0x0 + + # PLL Reset + # PSU_DDR_PHY_DX8SL3PLLCR0_PLLRST 0x0 + + # PLL Power Down + # PSU_DDR_PHY_DX8SL3PLLCR0_PLLPD 0x0 + + # Reference Stop Mode + # PSU_DDR_PHY_DX8SL3PLLCR0_RSTOPM 0x0 + + # PLL Frequency Select + # PSU_DDR_PHY_DX8SL3PLLCR0_FRQSEL 0x1 + + # Relock Mode + # PSU_DDR_PHY_DX8SL3PLLCR0_RLOCKM 0x0 + + # Charge Pump Proportional Current Control + # PSU_DDR_PHY_DX8SL3PLLCR0_CPPC 0x8 + + # Charge Pump Integrating Current Control + # PSU_DDR_PHY_DX8SL3PLLCR0_CPIC 0x0 + + # Gear Shift + # PSU_DDR_PHY_DX8SL3PLLCR0_GSHIFT 0x0 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX8SL3PLLCR0_RESERVED_11_9 0x0 + + # Analog Test Enable (ATOEN) + # PSU_DDR_PHY_DX8SL3PLLCR0_ATOEN 0x0 + + # Analog Test Control + # PSU_DDR_PHY_DX8SL3PLLCR0_ATC 0x0 + + # Digital Test Control + # PSU_DDR_PHY_DX8SL3PLLCR0_DTC 0x0 + + # DAXT8 0-1 PLL Control Register 0 + #(OFFSET, MASK, VALUE) (0XFD0814C4, 0xFFFFFFFFU ,0x01100000U) */ + mask_write 0XFD0814C4 0xFFFFFFFF 0x01100000 # Register : DX8SL3DQSCTL @ 0XFD0814DC

# Reserved. Return zeroes on reads. @@ -8071,7 +8855,8 @@ set psu_ddr_init_data { # Enable Clock Gating for DX ctl_clk # PSU_DDR_PHY_DX8SL4OSC_GATEDXCTLCLK 0x2 - # Selects the level to which clocks will be stalled when clock gating is enabled. + # Selects the level to which clocks will be stalled when clock gating is e + # nabled. # PSU_DDR_PHY_DX8SL4OSC_CLKLEVEL 0x0 # Loopback Mode @@ -8116,9 +8901,54 @@ set psu_ddr_init_data { # Oscillator Enable # PSU_DDR_PHY_DX8SL4OSC_OSCEN 0x0 - # DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register + # DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Lo + # opback, and Gated Clock Control Register #(OFFSET, MASK, VALUE) (0XFD081500, 0xFFFFFFFFU ,0x2A019FFEU) */ mask_write 0XFD081500 0xFFFFFFFF 0x2A019FFE + # Register : DX8SL4PLLCR0 @ 0XFD081504

+ + # PLL Bypass + # PSU_DDR_PHY_DX8SL4PLLCR0_PLLBYP 0x0 + + # PLL Reset + # PSU_DDR_PHY_DX8SL4PLLCR0_PLLRST 0x0 + + # PLL Power Down + # PSU_DDR_PHY_DX8SL4PLLCR0_PLLPD 0x0 + + # Reference Stop Mode + # PSU_DDR_PHY_DX8SL4PLLCR0_RSTOPM 0x0 + + # PLL Frequency Select + # PSU_DDR_PHY_DX8SL4PLLCR0_FRQSEL 0x1 + + # Relock Mode + # PSU_DDR_PHY_DX8SL4PLLCR0_RLOCKM 0x0 + + # Charge Pump Proportional Current Control + # PSU_DDR_PHY_DX8SL4PLLCR0_CPPC 0x8 + + # Charge Pump Integrating Current Control + # PSU_DDR_PHY_DX8SL4PLLCR0_CPIC 0x0 + + # Gear Shift + # PSU_DDR_PHY_DX8SL4PLLCR0_GSHIFT 0x0 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX8SL4PLLCR0_RESERVED_11_9 0x0 + + # Analog Test Enable (ATOEN) + # PSU_DDR_PHY_DX8SL4PLLCR0_ATOEN 0x0 + + # Analog Test Control + # PSU_DDR_PHY_DX8SL4PLLCR0_ATC 0x0 + + # Digital Test Control + # PSU_DDR_PHY_DX8SL4PLLCR0_DTC 0x0 + + # DAXT8 0-1 PLL Control Register 0 + #(OFFSET, MASK, VALUE) (0XFD081504, 0xFFFFFFFFU ,0x01100000U) */ + mask_write 0XFD081504 0xFFFFFFFF 0x01100000 # Register : DX8SL4DQSCTL @ 0XFD08151C

# Reserved. Return zeroes on reads. @@ -8242,6 +9072,50 @@ set psu_ddr_init_data { # DATX8 0-1 I/O Configuration Register #(OFFSET, MASK, VALUE) (0XFD081530, 0xFFFFFFFFU ,0x70800000U) */ mask_write 0XFD081530 0xFFFFFFFF 0x70800000 + # Register : DX8SLbPLLCR0 @ 0XFD0817C4

+ + # PLL Bypass + # PSU_DDR_PHY_DX8SLBPLLCR0_PLLBYP 0x0 + + # PLL Reset + # PSU_DDR_PHY_DX8SLBPLLCR0_PLLRST 0x0 + + # PLL Power Down + # PSU_DDR_PHY_DX8SLBPLLCR0_PLLPD 0x0 + + # Reference Stop Mode + # PSU_DDR_PHY_DX8SLBPLLCR0_RSTOPM 0x0 + + # PLL Frequency Select + # PSU_DDR_PHY_DX8SLBPLLCR0_FRQSEL 0x1 + + # Relock Mode + # PSU_DDR_PHY_DX8SLBPLLCR0_RLOCKM 0x0 + + # Charge Pump Proportional Current Control + # PSU_DDR_PHY_DX8SLBPLLCR0_CPPC 0x8 + + # Charge Pump Integrating Current Control + # PSU_DDR_PHY_DX8SLBPLLCR0_CPIC 0x0 + + # Gear Shift + # PSU_DDR_PHY_DX8SLBPLLCR0_GSHIFT 0x0 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX8SLBPLLCR0_RESERVED_11_9 0x0 + + # Analog Test Enable (ATOEN) + # PSU_DDR_PHY_DX8SLBPLLCR0_ATOEN 0x0 + + # Analog Test Control + # PSU_DDR_PHY_DX8SLBPLLCR0_ATC 0x0 + + # Digital Test Control + # PSU_DDR_PHY_DX8SLBPLLCR0_DTC 0x0 + + # DAXT8 0-8 PLL Control Register 0 + #(OFFSET, MASK, VALUE) (0XFD0817C4, 0xFFFFFFFFU ,0x01100000U) */ + mask_write 0XFD0817C4 0xFFFFFFFF 0x01100000 # Register : DX8SLbDQSCTL @ 0XFD0817DC

# Reserved. Return zeroes on reads. @@ -8289,107 +9163,35 @@ set psu_ddr_init_data { # DATX8 0-8 DQS Control Register #(OFFSET, MASK, VALUE) (0XFD0817DC, 0xFFFFFFFFU ,0x012643C4U) */ mask_write 0XFD0817DC 0xFFFFFFFF 0x012643C4 - # Register : PIR @ 0XFD080004

+} - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_PIR_RESERVED_31 0x0 - - # Impedance Calibration Bypass - # PSU_DDR_PHY_PIR_ZCALBYP 0x0 - - # Digital Delay Line (DDL) Calibration Pause - # PSU_DDR_PHY_PIR_DCALPSE 0x0 - - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_PIR_RESERVED_28_21 0x0 - - # Write DQS2DQ Training - # PSU_DDR_PHY_PIR_DQS2DQ 0x0 - - # RDIMM Initialization - # PSU_DDR_PHY_PIR_RDIMMINIT 0x0 - - # Controller DRAM Initialization - # PSU_DDR_PHY_PIR_CTLDINIT 0x1 - - # VREF Training - # PSU_DDR_PHY_PIR_VREF 0x0 - - # Static Read Training - # PSU_DDR_PHY_PIR_SRD 0x0 - - # Write Data Eye Training - # PSU_DDR_PHY_PIR_WREYE 0x0 - - # Read Data Eye Training - # PSU_DDR_PHY_PIR_RDEYE 0x0 - - # Write Data Bit Deskew - # PSU_DDR_PHY_PIR_WRDSKW 0x0 - - # Read Data Bit Deskew - # PSU_DDR_PHY_PIR_RDDSKW 0x0 - - # Write Leveling Adjust - # PSU_DDR_PHY_PIR_WLADJ 0x0 - - # Read DQS Gate Training - # PSU_DDR_PHY_PIR_QSGATE 0x0 - - # Write Leveling - # PSU_DDR_PHY_PIR_WL 0x0 - - # DRAM Initialization - # PSU_DDR_PHY_PIR_DRAMINIT 0x0 - - # DRAM Reset (DDR3/DDR4/LPDDR4 Only) - # PSU_DDR_PHY_PIR_DRAMRST 0x0 - - # PHY Reset - # PSU_DDR_PHY_PIR_PHYRST 0x1 - - # Digital Delay Line (DDL) Calibration - # PSU_DDR_PHY_PIR_DCAL 0x1 - - # PLL Initialiazation - # PSU_DDR_PHY_PIR_PLLINIT 0x1 - - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_PIR_RESERVED_3 0x0 - - # CA Training - # PSU_DDR_PHY_PIR_CA 0x0 - - # Impedance Calibration - # PSU_DDR_PHY_PIR_ZCAL 0x1 - - # Initialization Trigger - # PSU_DDR_PHY_PIR_INIT 0x1 - - # PHY Initialization Register - #(OFFSET, MASK, VALUE) (0XFD080004, 0xFFFFFFFFU ,0x00040073U) */ - mask_write 0XFD080004 0xFFFFFFFF 0x00040073 +set psu_ddr_qos_init_data { } set psu_mio_init_data { # : MIO PROGRAMMING # Register : MIO_PIN_0 @ 0XFF180000

- # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out- (QSPI Clock) + # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out- + # (QSPI Clock) # PSU_IOU_SLCR_MIO_PIN_0_L0_SEL 1 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used # PSU_IOU_SLCR_MIO_PIN_0_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[0]- (Test Scan Port) = test_scan, Outp - # t, test_scan_out[0]- (Test Scan Port) 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + # , test_scan_in[0]- (Test Scan Port) = test_scan, Output, test_scan_out[0 + # ]- (Test Scan Port) 3= Not Used # PSU_IOU_SLCR_MIO_PIN_0_L2_SEL 0 - # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[0]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[0]- (GPIO bank 0) 1= can - # , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa - # ) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Cloc - # ) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_ - # lk- (Trace Port Clock) + # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[0]- (GPIO bank 0) 0= g + # pio0, Output, gpio_0_pin_out[0]- (GPIO bank 0) 1= can1, Output, can1_phy + # _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + # 1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG + # TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sc + # lk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Out + # put, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_c + # lk- (Trace Port Clock) # PSU_IOU_SLCR_MIO_PIN_0_L3_SEL 0 # Configures MIO Pin 0 peripheral interface mapping. S @@ -8397,22 +9199,26 @@ set psu_mio_init_data { mask_write 0XFF180000 0x000000FE 0x00000002 # Register : MIO_PIN_1 @ 0XFF180004

- # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (QSPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Data - # us) + # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (Q + # SPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Databus) # PSU_IOU_SLCR_MIO_PIN_1_L0_SEL 1 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used # PSU_IOU_SLCR_MIO_PIN_1_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[1]- (Test Scan Port) = test_scan, Outp - # t, test_scan_out[1]- (Test Scan Port) 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + # , test_scan_in[1]- (Test Scan Port) = test_scan, Output, test_scan_out[1 + # ]- (Test Scan Port) 3= Not Used # PSU_IOU_SLCR_MIO_PIN_1_L2_SEL 0 - # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[1]- (GPIO bank 0) 1= can - # , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal - # 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_o - # t- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control - # Signal) + # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0) 0= g + # pio0, Output, gpio_0_pin_out[1]- (GPIO bank 0) 1= can1, Input, can1_phy_ + # rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + # , Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG + # TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc3, Ou + # tput, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART + # receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control + # Signal) # PSU_IOU_SLCR_MIO_PIN_1_L3_SEL 0 # Configures MIO Pin 1 peripheral interface mapping @@ -8420,20 +9226,25 @@ set psu_mio_init_data { mask_write 0XFF180004 0x000000FE 0x00000002 # Register : MIO_PIN_2 @ 0XFF180008

- # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus) + # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI + # Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus) # PSU_IOU_SLCR_MIO_PIN_2_L0_SEL 1 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used # PSU_IOU_SLCR_MIO_PIN_2_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[2]- (Test Scan Port) = test_scan, Outp - # t, test_scan_out[2]- (Test Scan Port) 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + # , test_scan_in[2]- (Test Scan Port) = test_scan, Output, test_scan_out[2 + # ]- (Test Scan Port) 3= Not Used # PSU_IOU_SLCR_MIO_PIN_2_L2_SEL 0 - # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[2]- (GPIO bank 0) 1= can - # , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal - # 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc2, Input, ttc2_clk_in - # (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[0]- (Trace Port Databus) + # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0) 0= g + # pio0, Output, gpio_0_pin_out[2]- (GPIO bank 0) 1= can0, Input, can0_phy_ + # rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + # , Output, i2c0_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTAG + # TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc2, I + # nput, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver se + # rial input) 7= trace, Output, tracedq[0]- (Trace Port Databus) # PSU_IOU_SLCR_MIO_PIN_2_L3_SEL 0 # Configures MIO Pin 2 peripheral interface mapping @@ -8441,21 +9252,26 @@ set psu_mio_init_data { mask_write 0XFF180008 0x000000FE 0x00000002 # Register : MIO_PIN_3 @ 0XFF18000C

- # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus) + # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI + # Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus) # PSU_IOU_SLCR_MIO_PIN_3_L0_SEL 1 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used # PSU_IOU_SLCR_MIO_PIN_3_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[3]- (Test Scan Port) = test_scan, Outp - # t, test_scan_out[3]- (Test Scan Port) 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + # , test_scan_in[3]- (Test Scan Port) = test_scan, Output, test_scan_out[3 + # ]- (Test Scan Port) 3= Not Used # PSU_IOU_SLCR_MIO_PIN_3_L2_SEL 0 - # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[3]- (GPIO bank 0) 1= can - # , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa - # ) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0 - # - (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial - # output) 7= trace, Output, tracedq[1]- (Trace Port Databus) + # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0) 0= g + # pio0, Output, gpio_0_pin_out[3]- (GPIO bank 0) 1= can0, Output, can0_phy + # _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + # 0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG + # TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output + # , spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- + # (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial + # output) 7= trace, Output, tracedq[1]- (Trace Port Databus) # PSU_IOU_SLCR_MIO_PIN_3_L3_SEL 0 # Configures MIO Pin 3 peripheral interface mapping @@ -8463,22 +9279,26 @@ set psu_mio_init_data { mask_write 0XFF18000C 0x000000FE 0x00000002 # Register : MIO_PIN_4 @ 0XFF180010

- # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- (QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Data - # us) + # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- ( + # QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Databus) # PSU_IOU_SLCR_MIO_PIN_4_L0_SEL 1 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used # PSU_IOU_SLCR_MIO_PIN_4_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[4]- (Test Scan Port) = test_scan, Outp - # t, test_scan_out[4]- (Test Scan Port) 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + # , test_scan_in[4]- (Test Scan Port) = test_scan, Output, test_scan_out[4 + # ]- (Test Scan Port) 3= Not Used # PSU_IOU_SLCR_MIO_PIN_4_L2_SEL 0 - # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[4]- (GPIO bank 0) 1= can - # , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa - # ) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_s - # - (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, - # utput, tracedq[2]- (Trace Port Databus) + # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0) 0= g + # pio0, Output, gpio_0_pin_out[4]- (GPIO bank 0) 1= can1, Output, can1_phy + # _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + # 1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Wa + # tch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi + # 0, Output, spi0_so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Cloc + # k) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, O + # utput, tracedq[2]- (Trace Port Databus) # PSU_IOU_SLCR_MIO_PIN_4_L3_SEL 0 # Configures MIO Pin 4 peripheral interface mapping @@ -8486,21 +9306,26 @@ set psu_mio_init_data { mask_write 0XFF180010 0x000000FE 0x00000002 # Register : MIO_PIN_5 @ 0XFF180014

- # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out- (QSPI Slave Select) + # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out- + # (QSPI Slave Select) # PSU_IOU_SLCR_MIO_PIN_5_L0_SEL 1 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used # PSU_IOU_SLCR_MIO_PIN_5_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[5]- (Test Scan Port) = test_scan, Outp - # t, test_scan_out[5]- (Test Scan Port) 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + # , test_scan_in[5]- (Test Scan Port) = test_scan, Output, test_scan_out[5 + # ]- (Test Scan Port) 3= Not Used # PSU_IOU_SLCR_MIO_PIN_5_L2_SEL 0 - # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[5]- (GPIO bank 0) 1= can - # , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal - # 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi0 - # si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7 - # trace, Output, tracedq[3]- (Trace Port Databus) + # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0) 0= g + # pio0, Output, gpio_0_pin_out[5]- (GPIO bank 0) 1= can1, Input, can1_phy_ + # rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + # , Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (W + # atch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= + # spi0, Input, spi0_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC + # Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= + # trace, Output, tracedq[3]- (Trace Port Databus) # PSU_IOU_SLCR_MIO_PIN_5_L3_SEL 0 # Configures MIO Pin 5 peripheral interface mapping @@ -8508,21 +9333,26 @@ set psu_mio_init_data { mask_write 0XFF180014 0x000000FE 0x00000002 # Register : MIO_PIN_6 @ 0XFF180018

- # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_clk_for_lpbk- (QSPI Clock to be fed-back) + # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_clk_for_l + # pbk- (QSPI Clock to be fed-back) # PSU_IOU_SLCR_MIO_PIN_6_L0_SEL 1 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used # PSU_IOU_SLCR_MIO_PIN_6_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[6]- (Test Scan Port) = test_scan, Outp - # t, test_scan_out[6]- (Test Scan Port) 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + # , test_scan_in[6]- (Test Scan Port) = test_scan, Output, test_scan_out[6 + # ]- (Test Scan Port) 3= Not Used # PSU_IOU_SLCR_MIO_PIN_6_L2_SEL 0 - # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[6]- (GPIO bank 0) 1= can - # , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal - # 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1 - # sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, - # Output, tracedq[4]- (Trace Port Databus) + # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0) 0= g + # pio0, Output, gpio_0_pin_out[6]- (GPIO bank 0) 1= can0, Input, can0_phy_ + # rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + # , Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Wat + # ch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= s + # pi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TT + # C Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, + # Output, tracedq[4]- (Trace Port Databus) # PSU_IOU_SLCR_MIO_PIN_6_L3_SEL 0 # Configures MIO Pin 6 peripheral interface mapping @@ -8530,21 +9360,26 @@ set psu_mio_init_data { mask_write 0XFF180018 0x000000FE 0x00000002 # Register : MIO_PIN_7 @ 0XFF18001C

- # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out_upper- (QSPI Slave Select upper) + # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out_ + # upper- (QSPI Slave Select upper) # PSU_IOU_SLCR_MIO_PIN_7_L0_SEL 1 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used # PSU_IOU_SLCR_MIO_PIN_7_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[7]- (Test Scan Port) = test_scan, Outp - # t, test_scan_out[7]- (Test Scan Port) 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + # , test_scan_in[7]- (Test Scan Port) = test_scan, Output, test_scan_out[7 + # ]- (Test Scan Port) 3= Not Used # PSU_IOU_SLCR_MIO_PIN_7_L2_SEL 0 - # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[7]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[7]- (GPIO bank 0) 1= can - # , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa - # ) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= - # tc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, - # racedq[5]- (Trace Port Databus) + # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[7]- (GPIO bank 0) 0= g + # pio0, Output, gpio_0_pin_out[7]- (GPIO bank 0) 1= can0, Output, can0_phy + # _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + # 0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- ( + # Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Ma + # ster Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua + # 0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, t + # racedq[5]- (Trace Port Databus) # PSU_IOU_SLCR_MIO_PIN_7_L3_SEL 0 # Configures MIO Pin 7 peripheral interface mapping @@ -8552,22 +9387,27 @@ set psu_mio_init_data { mask_write 0XFF18001C 0x000000FE 0x00000002 # Register : MIO_PIN_8 @ 0XFF180020

- # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[0]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe - # [0]- (QSPI Upper Databus) + # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[0 + # ]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[0]- (QSPI Upper D + # atabus) # PSU_IOU_SLCR_MIO_PIN_8_L0_SEL 1 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used # PSU_IOU_SLCR_MIO_PIN_8_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[8]- (Test Scan Port) = test_scan, Outp - # t, test_scan_out[8]- (Test Scan Port) 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + # , test_scan_in[8]- (Test Scan Port) = test_scan, Output, test_scan_out[8 + # ]- (Test Scan Port) 3= Not Used # PSU_IOU_SLCR_MIO_PIN_8_L2_SEL 0 - # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[8]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[8]- (GPIO bank 0) 1= can - # , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa - # ) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc - # , Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Tr - # ce Port Databus) + # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[8]- (GPIO bank 0) 0= g + # pio0, Output, gpio_0_pin_out[8]- (GPIO bank 0) 1= can1, Output, can1_phy + # _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + # 1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Wa + # tch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Maste + # r Selects) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_ + # txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Tra + # ce Port Databus) # PSU_IOU_SLCR_MIO_PIN_8_L3_SEL 0 # Configures MIO Pin 8 peripheral interface mapping @@ -8575,22 +9415,29 @@ set psu_mio_init_data { mask_write 0XFF180020 0x000000FE 0x00000002 # Register : MIO_PIN_9 @ 0XFF180024

- # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[1]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe - # [1]- (QSPI Upper Databus) + # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[1 + # ]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[1]- (QSPI Upper D + # atabus) # PSU_IOU_SLCR_MIO_PIN_9_L0_SEL 1 - # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NAND chip enable) + # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NA + # ND chip enable) # PSU_IOU_SLCR_MIO_PIN_9_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[9]- (Test Scan Port) = test_scan, Outp - # t, test_scan_out[9]- (Test Scan Port) 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + # , test_scan_in[9]- (Test Scan Port) = test_scan, Output, test_scan_out[9 + # ]- (Test Scan Port) 3= Not Used # PSU_IOU_SLCR_MIO_PIN_9_L2_SEL 0 - # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[9]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[9]- (GPIO bank 0) 1= can - # , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal - # 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, - # utput, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (U - # RT receiver serial input) 7= trace, Output, tracedq[7]- (Trace Port Databus) + # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[9]- (GPIO bank 0) 0= g + # pio0, Output, gpio_0_pin_out[9]- (GPIO bank 0) 1= can1, Input, can1_phy_ + # rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + # , Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (W + # atch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master S + # elects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc3, + # Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UA + # RT receiver serial input) 7= trace, Output, tracedq[7]- (Trace Port Data + # bus) # PSU_IOU_SLCR_MIO_PIN_9_L3_SEL 0 # Configures MIO Pin 9 peripheral interface mapping @@ -8598,22 +9445,28 @@ set psu_mio_init_data { mask_write 0XFF180024 0x000000FE 0x00000002 # Register : MIO_PIN_10 @ 0XFF180028

- # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[2]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe - # [2]- (QSPI Upper Databus) + # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[2 + # ]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[2]- (QSPI Upper D + # atabus) # PSU_IOU_SLCR_MIO_PIN_10_L0_SEL 1 - # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (NAND Ready/Busy) + # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (N + # AND Ready/Busy) # PSU_IOU_SLCR_MIO_PIN_10_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[10]- (Test Scan Port) = test_scan, Out - # ut, test_scan_out[10]- (Test Scan Port) 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + # , test_scan_in[10]- (Test Scan Port) = test_scan, Output, test_scan_out[ + # 10]- (Test Scan Port) 3= Not Used # PSU_IOU_SLCR_MIO_PIN_10_L2_SEL 0 - # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[10]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[10]- (GPIO bank 0) 1= c - # n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - # l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_ - # o- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outp - # t, tracedq[8]- (Trace Port Databus) + # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[10]- (GPIO bank 0) 0= + # gpio0, Output, gpio_0_pin_out[10]- (GPIO bank 0) 1= can0, Input, can0_ph + # y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + # c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + # atch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= sp + # i1, Output, spi1_so- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clo + # ck) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outpu + # t, tracedq[8]- (Trace Port Databus) # PSU_IOU_SLCR_MIO_PIN_10_L3_SEL 0 # Configures MIO Pin 10 peripheral interface mapping @@ -8621,22 +9474,28 @@ set psu_mio_init_data { mask_write 0XFF180028 0x000000FE 0x00000002 # Register : MIO_PIN_11 @ 0XFF18002C

- # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[3]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe - # [3]- (QSPI Upper Databus) + # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[3 + # ]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[3]- (QSPI Upper D + # atabus) # PSU_IOU_SLCR_MIO_PIN_11_L0_SEL 1 - # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (NAND Ready/Busy) + # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (N + # AND Ready/Busy) # PSU_IOU_SLCR_MIO_PIN_11_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[11]- (Test Scan Port) = test_scan, Out - # ut, test_scan_out[11]- (Test Scan Port) 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + # , test_scan_in[11]- (Test Scan Port) = test_scan, Output, test_scan_out[ + # 11]- (Test Scan Port) 3= Not Used # PSU_IOU_SLCR_MIO_PIN_11_L2_SEL 0 - # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0) 1= c - # n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - # al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s - # i1_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o - # tput) 7= trace, Output, tracedq[9]- (Trace Port Databus) + # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0) 0= + # gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0) 1= can0, Output, can0_p + # hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + # 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + # (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) + # 4= spi1, Input, spi1_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- ( + # TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial ou + # tput) 7= trace, Output, tracedq[9]- (Trace Port Databus) # PSU_IOU_SLCR_MIO_PIN_11_L3_SEL 0 # Configures MIO Pin 11 peripheral interface mapping @@ -8644,22 +9503,27 @@ set psu_mio_init_data { mask_write 0XFF18002C 0x000000FE 0x00000002 # Register : MIO_PIN_12 @ 0XFF180030

- # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out_upper- (QSPI Upper Clock) + # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out_ + # upper- (QSPI Upper Clock) # PSU_IOU_SLCR_MIO_PIN_12_L0_SEL 1 - # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NAND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe - # + # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NA + # ND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe) # PSU_IOU_SLCR_MIO_PIN_12_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[12]- (Test Scan Port) = test_scan, Out - # ut, test_scan_out[12]- (Test Scan Port) 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + # , test_scan_in[12]- (Test Scan Port) = test_scan, Output, test_scan_out[ + # 12]- (Test Scan Port) 3= Not Used # PSU_IOU_SLCR_MIO_PIN_12_L2_SEL 0 - # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[12]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[12]- (GPIO bank 0) 1= c - # n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - # al) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Cl - # ck) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trac - # dq[10]- (Trace Port Databus) + # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[12]- (GPIO bank 0) 0= + # gpio0, Output, gpio_0_pin_out[12]- (GPIO bank 0) 1= can1, Output, can1_p + # hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + # 2c1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJT + # AG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_ + # sclk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, O + # utput, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace + # dq[10]- (Trace Port Databus) # PSU_IOU_SLCR_MIO_PIN_12_L3_SEL 0 # Configures MIO Pin 12 peripheral interface mapping @@ -8670,19 +9534,24 @@ set psu_mio_init_data { # Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used # PSU_IOU_SLCR_MIO_PIN_13_L0_SEL 0 - # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[0]- (NAND chip enable) + # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[0]- (NA + # ND chip enable) # PSU_IOU_SLCR_MIO_PIN_13_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8 - # bit Data bus) 2= test_scan, Input, test_scan_in[13]- (Test Scan Port) = test_scan, Output, test_scan_out[13]- (Test Scan Port - # 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- + # (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8-bit Data bus) 2= t + # est_scan, Input, test_scan_in[13]- (Test Scan Port) = test_scan, Output, + # test_scan_out[13]- (Test Scan Port) 3= Not Used # PSU_IOU_SLCR_MIO_PIN_13_L2_SEL 0 - # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[13]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[13]- (GPIO bank 0) 1= c - # n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - # l) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave - # out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq[11]- (Trace Port Dat - # bus) + # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[13]- (GPIO bank 0) 0= + # gpio0, Output, gpio_0_pin_out[13]- (GPIO bank 0) 1= can1, Input, can1_ph + # y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + # c1, Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTA + # G TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, + # Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UAR + # T receiver serial input) 7= trace, Output, tracedq[11]- (Trace Port Data + # bus) # PSU_IOU_SLCR_MIO_PIN_13_L3_SEL 0 # Configures MIO Pin 13 peripheral interface mapping @@ -8693,18 +9562,23 @@ set psu_mio_init_data { # Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used # PSU_IOU_SLCR_MIO_PIN_14_L0_SEL 0 - # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_cle- (NAND Command Latch Enable) + # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_cle- (NAND + # Command Latch Enable) # PSU_IOU_SLCR_MIO_PIN_14_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8 - # bit Data bus) 2= test_scan, Input, test_scan_in[14]- (Test Scan Port) = test_scan, Output, test_scan_out[14]- (Test Scan Port - # 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- + # (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8-bit Data bus) 2= t + # est_scan, Input, test_scan_in[14]- (Test Scan Port) = test_scan, Output, + # test_scan_out[14]- (Test Scan Port) 3= Not Used # PSU_IOU_SLCR_MIO_PIN_14_L2_SEL 0 - # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0) 1= c - # n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - # l) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, Input, ttc0_clk_ - # n- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace Port Databus) + # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0) 0= + # gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0) 1= can0, Input, can0_ph + # y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + # c0, Output, i2c0_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJT + # AG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, + # Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver + # serial input) 7= trace, Output, tracedq[12]- (Trace Port Databus) # PSU_IOU_SLCR_MIO_PIN_14_L3_SEL 2 # Configures MIO Pin 14 peripheral interface mapping @@ -8715,19 +9589,24 @@ set psu_mio_init_data { # Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used # PSU_IOU_SLCR_MIO_PIN_15_L0_SEL 0 - # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ale- (NAND Address Latch Enable) + # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ale- (NAND + # Address Latch Enable) # PSU_IOU_SLCR_MIO_PIN_15_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8 - # bit Data bus) 2= test_scan, Input, test_scan_in[15]- (Test Scan Port) = test_scan, Output, test_scan_out[15]- (Test Scan Port - # 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- + # (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8-bit Data bus) 2= t + # est_scan, Input, test_scan_in[15]- (Test Scan Port) = test_scan, Output, + # test_scan_out[15]- (Test Scan Port) 3= Not Used # PSU_IOU_SLCR_MIO_PIN_15_L2_SEL 0 - # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[15]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[15]- (GPIO bank 0) 1= c - # n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - # al) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out - # 0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter seri - # l output) 7= trace, Output, tracedq[13]- (Trace Port Databus) + # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[15]- (GPIO bank 0) 0= + # gpio0, Output, gpio_0_pin_out[15]- (GPIO bank 0) 1= can0, Output, can0_p + # hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + # 2c0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJT + # AG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Outp + # ut, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_ou + # t- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter seria + # l output) 7= trace, Output, tracedq[13]- (Trace Port Databus) # PSU_IOU_SLCR_MIO_PIN_15_L3_SEL 2 # Configures MIO Pin 15 peripheral interface mapping @@ -8738,20 +9617,24 @@ set psu_mio_init_data { # Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used # PSU_IOU_SLCR_MIO_PIN_16_L0_SEL 0 - # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[0]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[0]- (NAND - # ata Bus) + # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[0]- ( + # NAND Data Bus) 1= nand, Output, nfc_dq_out[0]- (NAND Data Bus) # PSU_IOU_SLCR_MIO_PIN_16_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8 - # bit Data bus) 2= test_scan, Input, test_scan_in[16]- (Test Scan Port) = test_scan, Output, test_scan_out[16]- (Test Scan Port - # 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- + # (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8-bit Data bus) 2= t + # est_scan, Input, test_scan_in[16]- (Test Scan Port) = test_scan, Output, + # test_scan_out[16]- (Test Scan Port) 3= Not Used # PSU_IOU_SLCR_MIO_PIN_16_L2_SEL 0 - # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[16]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[16]- (GPIO bank 0) 1= c - # n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - # al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0 - # so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace - # Output, tracedq[14]- (Trace Port Databus) + # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[16]- (GPIO bank 0) 0= + # gpio0, Output, gpio_0_pin_out[16]- (GPIO bank 0) 1= can1, Output, can1_p + # hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + # 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + # Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= s + # pi0, Output, spi0_so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Cl + # ock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, + # Output, tracedq[14]- (Trace Port Databus) # PSU_IOU_SLCR_MIO_PIN_16_L3_SEL 2 # Configures MIO Pin 16 peripheral interface mapping @@ -8762,20 +9645,24 @@ set psu_mio_init_data { # Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used # PSU_IOU_SLCR_MIO_PIN_17_L0_SEL 0 - # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[1]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[1]- (NAND - # ata Bus) + # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[1]- ( + # NAND Data Bus) 1= nand, Output, nfc_dq_out[1]- (NAND Data Bus) # PSU_IOU_SLCR_MIO_PIN_17_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8 - # bit Data bus) 2= test_scan, Input, test_scan_in[17]- (Test Scan Port) = test_scan, Output, test_scan_out[17]- (Test Scan Port - # 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- + # (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8-bit Data bus) 2= t + # est_scan, Input, test_scan_in[17]- (Test Scan Port) = test_scan, Output, + # test_scan_out[17]- (Test Scan Port) 3= Not Used # PSU_IOU_SLCR_MIO_PIN_17_L2_SEL 0 - # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[17]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[17]- (GPIO bank 0) 1= c - # n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - # l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, sp - # 0_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) - # 7= trace, Output, tracedq[15]- (Trace Port Databus) + # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[17]- (GPIO bank 0) 0= + # gpio0, Output, gpio_0_pin_out[17]- (GPIO bank 0) 1= can1, Input, can1_ph + # y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + # c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + # (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4 + # = spi0, Input, spi0_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (T + # TC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) + # 7= trace, Output, tracedq[15]- (Trace Port Databus) # PSU_IOU_SLCR_MIO_PIN_17_L3_SEL 2 # Configures MIO Pin 17 peripheral interface mapping @@ -8786,19 +9673,24 @@ set psu_mio_init_data { # Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used # PSU_IOU_SLCR_MIO_PIN_18_L0_SEL 0 - # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[2]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[2]- (NAND - # ata Bus) + # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[2]- ( + # NAND Data Bus) 1= nand, Output, nfc_dq_out[2]- (NAND Data Bus) # PSU_IOU_SLCR_MIO_PIN_18_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8 - # bit Data bus) 2= test_scan, Input, test_scan_in[18]- (Test Scan Port) = test_scan, Output, test_scan_out[18]- (Test Scan Port - # 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper) + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- + # (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8-bit Data bus) 2= t + # est_scan, Input, test_scan_in[18]- (Test Scan Port) = test_scan, Output, + # test_scan_out[18]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU + # Ext Tamper) # PSU_IOU_SLCR_MIO_PIN_18_L2_SEL 0 - # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[18]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[18]- (GPIO bank 0) 1= c - # n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - # l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_ - # o- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used + # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[18]- (GPIO bank 0) 0= + # gpio0, Output, gpio_0_pin_out[18]- (GPIO bank 0) 1= can0, Input, can0_ph + # y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + # c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + # atch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= sp + # i1, Output, spi1_so- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clo + # ck) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used # PSU_IOU_SLCR_MIO_PIN_18_L3_SEL 6 # Configures MIO Pin 18 peripheral interface mapping @@ -8809,19 +9701,24 @@ set psu_mio_init_data { # Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used # PSU_IOU_SLCR_MIO_PIN_19_L0_SEL 0 - # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[3]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[3]- (NAND - # ata Bus) + # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[3]- ( + # NAND Data Bus) 1= nand, Output, nfc_dq_out[3]- (NAND Data Bus) # PSU_IOU_SLCR_MIO_PIN_19_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8 - # bit Data bus) 2= test_scan, Input, test_scan_in[19]- (Test Scan Port) = test_scan, Output, test_scan_out[19]- (Test Scan Port - # 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper) + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- + # (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8-bit Data bus) 2= t + # est_scan, Input, test_scan_in[19]- (Test Scan Port) = test_scan, Output, + # test_scan_out[19]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU + # Ext Tamper) # PSU_IOU_SLCR_MIO_PIN_19_L2_SEL 0 - # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[19]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[19]- (GPIO bank 0) 1= c - # n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - # al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5 - # ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used + # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[19]- (GPIO bank 0) 0= + # gpio0, Output, gpio_0_pin_out[19]- (GPIO bank 0) 1= can0, Output, can0_p + # hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + # 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + # (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI + # Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= + # ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used # PSU_IOU_SLCR_MIO_PIN_19_L3_SEL 6 # Configures MIO Pin 19 peripheral interface mapping @@ -8832,19 +9729,24 @@ set psu_mio_init_data { # Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used # PSU_IOU_SLCR_MIO_PIN_20_L0_SEL 0 - # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[4]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[4]- (NAND - # ata Bus) + # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[4]- ( + # NAND Data Bus) 1= nand, Output, nfc_dq_out[4]- (NAND Data Bus) # PSU_IOU_SLCR_MIO_PIN_20_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8 - # bit Data bus) 2= test_scan, Input, test_scan_in[20]- (Test Scan Port) = test_scan, Output, test_scan_out[20]- (Test Scan Port - # 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper) + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- + # (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8-bit Data bus) 2= t + # est_scan, Input, test_scan_in[20]- (Test Scan Port) = test_scan, Output, + # test_scan_out[20]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU + # Ext Tamper) # PSU_IOU_SLCR_MIO_PIN_20_L2_SEL 0 - # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[20]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[20]- (GPIO bank 0) 1= c - # n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - # al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= t - # c1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Used + # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[20]- (GPIO bank 0) 0= + # gpio0, Output, gpio_0_pin_out[20]- (GPIO bank 0) 1= can1, Output, can1_p + # hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + # 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + # Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Mas + # ter Selects) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua + # 1_txd- (UART transmitter serial output) 7= Not Used # PSU_IOU_SLCR_MIO_PIN_20_L3_SEL 6 # Configures MIO Pin 20 peripheral interface mapping @@ -8855,20 +9757,25 @@ set psu_mio_init_data { # Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used # PSU_IOU_SLCR_MIO_PIN_21_L0_SEL 0 - # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[5]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[5]- (NAND - # ata Bus) + # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[5]- ( + # NAND Data Bus) 1= nand, Output, nfc_dq_out[5]- (NAND Data Bus) # PSU_IOU_SLCR_MIO_PIN_21_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Comman - # Indicator) 2= test_scan, Input, test_scan_in[21]- (Test Scan Port) = test_scan, Output, test_scan_out[21]- (Test Scan Port) - # = csu, Input, csu_ext_tamper- (CSU Ext Tamper) + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Com + # mand Indicator) = sd0, Output, sdio0_cmd_out- (Command Indicator) 2= tes + # t_scan, Input, test_scan_in[21]- (Test Scan Port) = test_scan, Output, t + # est_scan_out[21]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU E + # xt Tamper) # PSU_IOU_SLCR_MIO_PIN_21_L2_SEL 0 - # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[21]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[21]- (GPIO bank 0) 1= c - # n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - # l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1 - # Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- - # UART receiver serial input) 7= Not Used + # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[21]- (GPIO bank 0) 0= + # gpio0, Output, gpio_0_pin_out[21]- (GPIO bank 0) 1= can1, Input, can1_ph + # y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + # c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + # (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master + # Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc + # 1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- ( + # UART receiver serial input) 7= Not Used # PSU_IOU_SLCR_MIO_PIN_21_L3_SEL 6 # Configures MIO Pin 21 peripheral interface mapping @@ -8879,18 +9786,24 @@ set psu_mio_init_data { # Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used # PSU_IOU_SLCR_MIO_PIN_22_L0_SEL 0 - # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_we_b- (NAND Write Enable) + # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_we_b- (NAN + # D Write Enable) # PSU_IOU_SLCR_MIO_PIN_22_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= test_scan, Input, test_scan_in[22]- - # (Test Scan Port) = test_scan, Output, test_scan_out[22]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper) + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- + # (SDSDIO clock) 2= test_scan, Input, test_scan_in[22]- (Test Scan Port) = + # test_scan, Output, test_scan_out[22]- (Test Scan Port) 3= csu, Input, c + # su_ext_tamper- (CSU Ext Tamper) # PSU_IOU_SLCR_MIO_PIN_22_L2_SEL 0 - # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[22]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[22]- (GPIO bank 0) 1= c - # n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - # l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, sp - # 1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not - # sed + # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[22]- (GPIO bank 0) 0= + # gpio0, Output, gpio_0_pin_out[22]- (GPIO bank 0) 1= can0, Input, can0_ph + # y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + # c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + # atch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= + # spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- ( + # TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not U + # sed # PSU_IOU_SLCR_MIO_PIN_22_L3_SEL 0 # Configures MIO Pin 22 peripheral interface mapping @@ -8901,20 +9814,24 @@ set psu_mio_init_data { # Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used # PSU_IOU_SLCR_MIO_PIN_23_L0_SEL 0 - # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[6]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[6]- (NAND - # ata Bus) + # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[6]- ( + # NAND Data Bus) 1= nand, Output, nfc_dq_out[6]- (NAND Data Bus) # PSU_IOU_SLCR_MIO_PIN_23_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= test_scan, Input, test_scan_in - # 23]- (Test Scan Port) = test_scan, Output, test_scan_out[23]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper - # + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- + # (SD card bus power) 2= test_scan, Input, test_scan_in[23]- (Test Scan Po + # rt) = test_scan, Output, test_scan_out[23]- (Test Scan Port) 3= csu, Inp + # ut, csu_ext_tamper- (CSU Ext Tamper) # PSU_IOU_SLCR_MIO_PIN_23_L2_SEL 0 - # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[23]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[23]- (GPIO bank 0) 1= c - # n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - # al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s - # i1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o - # tput) 7= Not Used + # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[23]- (GPIO bank 0) 0= + # gpio0, Output, gpio_0_pin_out[23]- (GPIO bank 0) 1= can0, Output, can0_p + # hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + # 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + # (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) + # 4= spi1, Input, spi1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- ( + # TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial ou + # tput) 7= Not Used # PSU_IOU_SLCR_MIO_PIN_23_L3_SEL 0 # Configures MIO Pin 23 peripheral interface mapping @@ -8925,19 +9842,23 @@ set psu_mio_init_data { # Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used # PSU_IOU_SLCR_MIO_PIN_24_L0_SEL 0 - # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[7]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[7]- (NAND - # ata Bus) + # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[7]- ( + # NAND Data Bus) 1= nand, Output, nfc_dq_out[7]- (NAND Data Bus) # PSU_IOU_SLCR_MIO_PIN_24_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= test_scan, Input, test - # scan_in[24]- (Test Scan Port) = test_scan, Output, test_scan_out[24]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ex - # Tamper) + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD + # card detect from connector) 2= test_scan, Input, test_scan_in[24]- (Test + # Scan Port) = test_scan, Output, test_scan_out[24]- (Test Scan Port) 3= + # csu, Input, csu_ext_tamper- (CSU Ext Tamper) # PSU_IOU_SLCR_MIO_PIN_24_L2_SEL 0 - # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[24]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[24]- (GPIO bank 0) 1= c - # n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - # al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= Not Used 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, - # Output, ua1_txd- (UART transmitter serial output) 7= Not Used + # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[24]- (GPIO bank 0) 0= + # gpio0, Output, gpio_0_pin_out[24]- (GPIO bank 0) 1= can1, Output, can1_p + # hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + # 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + # Watch Dog Timer Input clock) 4= Not Used 5= ttc3, Input, ttc3_clk_in- (T + # TC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= N + # ot Used # PSU_IOU_SLCR_MIO_PIN_24_L3_SEL 1 # Configures MIO Pin 24 peripheral interface mapping @@ -8948,18 +9869,23 @@ set psu_mio_init_data { # Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used # PSU_IOU_SLCR_MIO_PIN_25_L0_SEL 0 - # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_re_n- (NAND Read Enable) + # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_re_n- (NAN + # D Read Enable) # PSU_IOU_SLCR_MIO_PIN_25_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= test_scan, Input, - # test_scan_in[25]- (Test Scan Port) = test_scan, Output, test_scan_out[25]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (C - # U Ext Tamper) + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD ca + # rd write protect from connector) 2= test_scan, Input, test_scan_in[25]- + # (Test Scan Port) = test_scan, Output, test_scan_out[25]- (Test Scan Port + # ) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper) # PSU_IOU_SLCR_MIO_PIN_25_L2_SEL 0 - # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[25]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[25]- (GPIO bank 0) 1= c - # n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - # l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= Not Used 5= ttc3, Output, ttc3_wave_out- (TTC Waveform - # lock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used + # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[25]- (GPIO bank 0) 0= + # gpio0, Output, gpio_0_pin_out[25]- (GPIO bank 0) 1= can1, Input, can1_ph + # y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + # c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + # (Watch Dog Timer Output clock) 4= Not Used 5= ttc3, Output, ttc3_wave_ou + # t- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial in + # put) 7= Not Used # PSU_IOU_SLCR_MIO_PIN_25_L3_SEL 1 # Configures MIO Pin 25 peripheral interface mapping @@ -8967,21 +9893,28 @@ set psu_mio_init_data { mask_write 0XFF180064 0x000000FE 0x00000020 # Register : MIO_PIN_26 @ 0XFF180068

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_clk- (TX RGMII clock) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ + # clk- (TX RGMII clock) # PSU_IOU_SLCR_MIO_PIN_26_L0_SEL 0 - # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NAND chip enable) + # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NA + # ND chip enable) # PSU_IOU_SLCR_MIO_PIN_26_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[0]- (PMU GPI) 2= test_scan, Input, test_scan_in[26]- (Test Sc - # n Port) = test_scan, Output, test_scan_out[26]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper) + # Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[0]- (PMU + # GPI) 2= test_scan, Input, test_scan_in[26]- (Test Scan Port) = test_sca + # n, Output, test_scan_out[26]- (Test Scan Port) 3= csu, Input, csu_ext_ta + # mper- (CSU Ext Tamper) # PSU_IOU_SLCR_MIO_PIN_26_L2_SEL 0 - # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[0]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[0]- (GPIO bank 1) 1= can - # , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal - # 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Clock - # 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- - # Trace Port Databus) + # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[0]- (GPIO bank 1) 0= g + # pio1, Output, gpio_1_pin_out[0]- (GPIO bank 1) 1= can0, Input, can0_phy_ + # rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + # , Output, i2c0_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG + # TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_scl + # k_out- (SPI Clock) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Inpu + # t, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- ( + # Trace Port Databus) # PSU_IOU_SLCR_MIO_PIN_26_L3_SEL 0 # Configures MIO Pin 26 peripheral interface mapping @@ -8989,22 +9922,28 @@ set psu_mio_init_data { mask_write 0XFF180068 0x000000FE 0x00000000 # Register : MIO_PIN_27 @ 0XFF18006C

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[0]- (TX RGMII data) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd + # [0]- (TX RGMII data) # PSU_IOU_SLCR_MIO_PIN_27_L0_SEL 0 - # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (NAND Ready/Busy) + # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (N + # AND Ready/Busy) # PSU_IOU_SLCR_MIO_PIN_27_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[1]- (PMU GPI) 2= test_scan, Input, test_scan_in[27]- (Test Sc - # n Port) = test_scan, Output, test_scan_out[27]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Outp - # t, dp_aux_data_out- (Dp Aux Data) + # Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[1]- (PMU + # GPI) 2= test_scan, Input, test_scan_in[27]- (Test Scan Port) = test_sca + # n, Output, test_scan_out[27]- (Test Scan Port) 3= dpaux, Input, dp_aux_d + # ata_in- (Dp Aux Data) = dpaux, Output, dp_aux_data_out- (Dp Aux Data) # PSU_IOU_SLCR_MIO_PIN_27_L2_SEL 3 - # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[1]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[1]- (GPIO bank 1) 1= can - # , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa - # ) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_ - # ut- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port - # atabus) + # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[1]- (GPIO bank 1) 0= g + # pio1, Output, gpio_1_pin_out[1]- (GPIO bank 1) 1= can0, Output, can0_phy + # _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + # 0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG + # TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc2, O + # utput, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UAR + # T transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port D + # atabus) # PSU_IOU_SLCR_MIO_PIN_27_L3_SEL 0 # Configures MIO Pin 27 peripheral interface mapping @@ -9012,20 +9951,27 @@ set psu_mio_init_data { mask_write 0XFF18006C 0x000000FE 0x00000018 # Register : MIO_PIN_28 @ 0XFF180070

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[1]- (TX RGMII data) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd + # [1]- (TX RGMII data) # PSU_IOU_SLCR_MIO_PIN_28_L0_SEL 0 - # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (NAND Ready/Busy) + # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (N + # AND Ready/Busy) # PSU_IOU_SLCR_MIO_PIN_28_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[2]- (PMU GPI) 2= test_scan, Input, test_scan_in[28]- (Test Sc - # n Port) = test_scan, Output, test_scan_out[28]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug) + # Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[2]- (PMU + # GPI) 2= test_scan, Input, test_scan_in[28]- (Test Scan Port) = test_sca + # n, Output, test_scan_out[28]- (Test Scan Port) 3= dpaux, Input, dp_hot_p + # lug_detect- (Dp Aux Hot Plug) # PSU_IOU_SLCR_MIO_PIN_28_L2_SEL 3 - # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[2]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[2]- (GPIO bank 1) 1= can - # , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa - # ) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc1, Input, ttc1_clk_i - # - (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus) + # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[2]- (GPIO bank 1) 0= g + # pio1, Output, gpio_1_pin_out[2]- (GPIO bank 1) 1= can1, Output, can1_phy + # _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + # 1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTA + # G TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc1, + # Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitt + # er serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus) # PSU_IOU_SLCR_MIO_PIN_28_L3_SEL 0 # Configures MIO Pin 28 peripheral interface mapping @@ -9033,22 +9979,28 @@ set psu_mio_init_data { mask_write 0XFF180070 0x000000FE 0x00000018 # Register : MIO_PIN_29 @ 0XFF180074

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[2]- (TX RGMII data) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd + # [2]- (TX RGMII data) # PSU_IOU_SLCR_MIO_PIN_29_L0_SEL 0 - # Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal) + # Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + # PCIE Reset signal) # PSU_IOU_SLCR_MIO_PIN_29_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[3]- (PMU GPI) 2= test_scan, Input, test_scan_in[29]- (Test Sc - # n Port) = test_scan, Output, test_scan_out[29]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Outp - # t, dp_aux_data_out- (Dp Aux Data) + # Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[3]- (PMU + # GPI) 2= test_scan, Input, test_scan_in[29]- (Test Scan Port) = test_sca + # n, Output, test_scan_out[29]- (Test Scan Port) 3= dpaux, Input, dp_aux_d + # ata_in- (Dp Aux Data) = dpaux, Output, dp_aux_data_out- (Dp Aux Data) # PSU_IOU_SLCR_MIO_PIN_29_L2_SEL 3 - # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[3]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[3]- (GPIO bank 1) 1= can - # , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal - # 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0] - # (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial inpu - # ) 7= trace, Output, tracedq[7]- (Trace Port Databus) + # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[3]- (GPIO bank 1) 0= g + # pio1, Output, gpio_1_pin_out[3]- (GPIO bank 1) 1= can1, Input, can1_phy_ + # rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + # , Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG + # TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, + # spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- + # (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input + # ) 7= trace, Output, tracedq[7]- (Trace Port Databus) # PSU_IOU_SLCR_MIO_PIN_29_L3_SEL 0 # Configures MIO Pin 29 peripheral interface mapping @@ -9056,21 +10008,28 @@ set psu_mio_init_data { mask_write 0XFF180074 0x000000FE 0x00000018 # Register : MIO_PIN_30 @ 0XFF180078

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[3]- (TX RGMII data) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd + # [3]- (TX RGMII data) # PSU_IOU_SLCR_MIO_PIN_30_L0_SEL 0 - # Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal) + # Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + # PCIE Reset signal) # PSU_IOU_SLCR_MIO_PIN_30_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[4]- (PMU GPI) 2= test_scan, Input, test_scan_in[30]- (Test Sc - # n Port) = test_scan, Output, test_scan_out[30]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug) + # Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[4]- (PMU + # GPI) 2= test_scan, Input, test_scan_in[30]- (Test Scan Port) = test_sca + # n, Output, test_scan_out[30]- (Test Scan Port) 3= dpaux, Input, dp_hot_p + # lug_detect- (Dp Aux Hot Plug) # PSU_IOU_SLCR_MIO_PIN_30_L2_SEL 3 - # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[4]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[4]- (GPIO bank 1) 1= can - # , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal - # 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_so - # (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output - # tracedq[8]- (Trace Port Databus) + # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[4]- (GPIO bank 1) 0= g + # pio1, Output, gpio_1_pin_out[4]- (GPIO bank 1) 1= can0, Input, can0_phy_ + # rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + # , Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Wat + # ch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0 + # , Output, spi0_so- (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clock + # ) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, + # tracedq[8]- (Trace Port Databus) # PSU_IOU_SLCR_MIO_PIN_30_L3_SEL 0 # Configures MIO Pin 30 peripheral interface mapping @@ -9078,21 +10037,28 @@ set psu_mio_init_data { mask_write 0XFF180078 0x000000FE 0x00000018 # Register : MIO_PIN_31 @ 0XFF18007C

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ctl- (TX RGMII control) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ + # ctl- (TX RGMII control) # PSU_IOU_SLCR_MIO_PIN_31_L0_SEL 0 - # Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal) + # Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + # PCIE Reset signal) # PSU_IOU_SLCR_MIO_PIN_31_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[5]- (PMU GPI) 2= test_scan, Input, test_scan_in[31]- (Test Sc - # n Port) = test_scan, Output, test_scan_out[31]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper) + # Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[5]- (PMU + # GPI) 2= test_scan, Input, test_scan_in[31]- (Test Scan Port) = test_sca + # n, Output, test_scan_out[31]- (Test Scan Port) 3= csu, Input, csu_ext_ta + # mper- (CSU Ext Tamper) # PSU_IOU_SLCR_MIO_PIN_31_L2_SEL 0 - # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[5]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[5]- (GPIO bank 1) 1= can - # , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa - # ) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi - # _si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial out - # ut) 7= trace, Output, tracedq[9]- (Trace Port Databus) + # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[5]- (GPIO bank 1) 0= g + # pio1, Output, gpio_1_pin_out[5]- (GPIO bank 1) 1= can0, Output, can0_phy + # _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + # 0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- ( + # Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= + # spi0, Input, spi0_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TT + # C Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial outp + # ut) 7= trace, Output, tracedq[9]- (Trace Port Databus) # PSU_IOU_SLCR_MIO_PIN_31_L3_SEL 0 # Configures MIO Pin 31 peripheral interface mapping @@ -9100,22 +10066,28 @@ set psu_mio_init_data { mask_write 0XFF18007C 0x000000FE 0x00000000 # Register : MIO_PIN_32 @ 0XFF180080

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_clk- (RX RGMII clock) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_c + # lk- (RX RGMII clock) # PSU_IOU_SLCR_MIO_PIN_32_L0_SEL 0 - # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NAND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe - # + # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NA + # ND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe) # PSU_IOU_SLCR_MIO_PIN_32_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[0]- (PMU GPI) 2= test_scan, Input, test_scan_in[32]- (Test S - # an Port) = test_scan, Output, test_scan_out[32]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper) + # Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[0]- (PM + # U GPI) 2= test_scan, Input, test_scan_in[32]- (Test Scan Port) = test_sc + # an, Output, test_scan_out[32]- (Test Scan Port) 3= csu, Input, csu_ext_t + # amper- (CSU Ext Tamper) # PSU_IOU_SLCR_MIO_PIN_32_L2_SEL 1 - # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[6]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[6]- (GPIO bank 1) 1= can - # , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa - # ) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi - # _sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= - # race, Output, tracedq[10]- (Trace Port Databus) + # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[6]- (GPIO bank 1) 0= g + # pio1, Output, gpio_1_pin_out[6]- (GPIO bank 1) 1= can1, Output, can1_phy + # _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + # 1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Wa + # tch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= + # spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (T + # TC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= t + # race, Output, tracedq[10]- (Trace Port Databus) # PSU_IOU_SLCR_MIO_PIN_32_L3_SEL 0 # Configures MIO Pin 32 peripheral interface mapping @@ -9123,21 +10095,28 @@ set psu_mio_init_data { mask_write 0XFF180080 0x000000FE 0x00000008 # Register : MIO_PIN_33 @ 0XFF180084

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[0]- (RX RGMII data) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[ + # 0]- (RX RGMII data) # PSU_IOU_SLCR_MIO_PIN_33_L0_SEL 0 - # Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal) + # Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + # PCIE Reset signal) # PSU_IOU_SLCR_MIO_PIN_33_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[1]- (PMU GPI) 2= test_scan, Input, test_scan_in[33]- (Test S - # an Port) = test_scan, Output, test_scan_out[33]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper) + # Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[1]- (PM + # U GPI) 2= test_scan, Input, test_scan_in[33]- (Test Scan Port) = test_sc + # an, Output, test_scan_out[33]- (Test Scan Port) 3= csu, Input, csu_ext_t + # amper- (CSU Ext Tamper) # PSU_IOU_SLCR_MIO_PIN_33_L2_SEL 1 - # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[7]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[7]- (GPIO bank 1) 1= can - # , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal - # 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= t - # c3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, traced - # [11]- (Trace Port Databus) + # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[7]- (GPIO bank 1) 0= g + # pio1, Output, gpio_1_pin_out[7]- (GPIO bank 1) 1= can1, Input, can1_phy_ + # rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + # , Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (W + # atch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Mas + # ter Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1 + # , Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq + # [11]- (Trace Port Databus) # PSU_IOU_SLCR_MIO_PIN_33_L3_SEL 0 # Configures MIO Pin 33 peripheral interface mapping @@ -9145,22 +10124,28 @@ set psu_mio_init_data { mask_write 0XFF180084 0x000000FE 0x00000008 # Register : MIO_PIN_34 @ 0XFF180088

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[1]- (RX RGMII data) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[ + # 1]- (RX RGMII data) # PSU_IOU_SLCR_MIO_PIN_34_L0_SEL 0 - # Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal) + # Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + # PCIE Reset signal) # PSU_IOU_SLCR_MIO_PIN_34_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[2]- (PMU GPI) 2= test_scan, Input, test_scan_in[34]- (Test S - # an Port) = test_scan, Output, test_scan_out[34]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Out - # ut, dp_aux_data_out- (Dp Aux Data) + # Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[2]- (PM + # U GPI) 2= test_scan, Input, test_scan_in[34]- (Test Scan Port) = test_sc + # an, Output, test_scan_out[34]- (Test Scan Port) 3= dpaux, Input, dp_aux_ + # data_in- (Dp Aux Data) = dpaux, Output, dp_aux_data_out- (Dp Aux Data) # PSU_IOU_SLCR_MIO_PIN_34_L2_SEL 1 - # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[8]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[8]- (GPIO bank 1) 1= can - # , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal - # 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc2 - # Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace P - # rt Databus) + # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[8]- (GPIO bank 1) 0= g + # pio1, Output, gpio_1_pin_out[8]- (GPIO bank 1) 1= can0, Input, can0_phy_ + # rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + # , Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Wat + # ch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master + # Selects) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rx + # d- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace Po + # rt Databus) # PSU_IOU_SLCR_MIO_PIN_34_L3_SEL 0 # Configures MIO Pin 34 peripheral interface mapping @@ -9168,21 +10153,29 @@ set psu_mio_init_data { mask_write 0XFF180088 0x000000FE 0x00000008 # Register : MIO_PIN_35 @ 0XFF18008C

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[2]- (RX RGMII data) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[ + # 2]- (RX RGMII data) # PSU_IOU_SLCR_MIO_PIN_35_L0_SEL 0 - # Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal) + # Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + # PCIE Reset signal) # PSU_IOU_SLCR_MIO_PIN_35_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[3]- (PMU GPI) 2= test_scan, Input, test_scan_in[35]- (Test S - # an Port) = test_scan, Output, test_scan_out[35]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug) + # Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[3]- (PM + # U GPI) 2= test_scan, Input, test_scan_in[35]- (Test Scan Port) = test_sc + # an, Output, test_scan_out[35]- (Test Scan Port) 3= dpaux, Input, dp_hot_ + # plug_detect- (Dp Aux Hot Plug) # PSU_IOU_SLCR_MIO_PIN_35_L2_SEL 1 - # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[9]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[9]- (GPIO bank 1) 1= can - # , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa - # ) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, - # Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- - # UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace Port Databus) + # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[9]- (GPIO bank 1) 0= g + # pio1, Output, gpio_1_pin_out[9]- (GPIO bank 1) 1= can0, Output, can0_phy + # _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + # 0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- ( + # Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master + # Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc2 + # , Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- ( + # UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace Po + # rt Databus) # PSU_IOU_SLCR_MIO_PIN_35_L3_SEL 0 # Configures MIO Pin 35 peripheral interface mapping @@ -9190,22 +10183,28 @@ set psu_mio_init_data { mask_write 0XFF18008C 0x000000FE 0x00000008 # Register : MIO_PIN_36 @ 0XFF180090

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[3]- (RX RGMII data) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[ + # 3]- (RX RGMII data) # PSU_IOU_SLCR_MIO_PIN_36_L0_SEL 0 - # Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal) + # Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + # PCIE Reset signal) # PSU_IOU_SLCR_MIO_PIN_36_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[4]- (PMU GPI) 2= test_scan, Input, test_scan_in[36]- (Test S - # an Port) = test_scan, Output, test_scan_out[36]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Out - # ut, dp_aux_data_out- (Dp Aux Data) + # Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[4]- (PM + # U GPI) 2= test_scan, Input, test_scan_in[36]- (Test Scan Port) = test_sc + # an, Output, test_scan_out[36]- (Test Scan Port) 3= dpaux, Input, dp_aux_ + # data_in- (Dp Aux Data) = dpaux, Output, dp_aux_data_out- (Dp Aux Data) # PSU_IOU_SLCR_MIO_PIN_36_L2_SEL 1 - # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[10]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[10]- (GPIO bank 1) 1= c - # n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - # al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1 - # so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace - # Output, tracedq[14]- (Trace Port Databus) + # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[10]- (GPIO bank 1) 0= + # gpio1, Output, gpio_1_pin_out[10]- (GPIO bank 1) 1= can1, Output, can1_p + # hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + # 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + # Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= s + # pi1, Output, spi1_so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Cl + # ock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, + # Output, tracedq[14]- (Trace Port Databus) # PSU_IOU_SLCR_MIO_PIN_36_L3_SEL 0 # Configures MIO Pin 36 peripheral interface mapping @@ -9213,21 +10212,28 @@ set psu_mio_init_data { mask_write 0XFF180090 0x000000FE 0x00000008 # Register : MIO_PIN_37 @ 0XFF180094

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_ctl- (RX RGMII control ) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_c + # tl- (RX RGMII control ) # PSU_IOU_SLCR_MIO_PIN_37_L0_SEL 0 - # Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal) + # Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + # PCIE Reset signal) # PSU_IOU_SLCR_MIO_PIN_37_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[5]- (PMU GPI) 2= test_scan, Input, test_scan_in[37]- (Test S - # an Port) = test_scan, Output, test_scan_out[37]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug) + # Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[5]- (PM + # U GPI) 2= test_scan, Input, test_scan_in[37]- (Test Scan Port) = test_sc + # an, Output, test_scan_out[37]- (Test Scan Port) 3= dpaux, Input, dp_hot_ + # plug_detect- (Dp Aux Hot Plug) # PSU_IOU_SLCR_MIO_PIN_37_L2_SEL 1 - # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[11]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[11]- (GPIO bank 1) 1= c - # n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - # l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, sp - # 1_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) - # 7= trace, Output, tracedq[15]- (Trace Port Databus) + # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[11]- (GPIO bank 1) 0= + # gpio1, Output, gpio_1_pin_out[11]- (GPIO bank 1) 1= can1, Input, can1_ph + # y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + # c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + # (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4 + # = spi1, Input, spi1_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (T + # TC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) + # 7= trace, Output, tracedq[15]- (Trace Port Databus) # PSU_IOU_SLCR_MIO_PIN_37_L3_SEL 0 # Configures MIO Pin 37 peripheral interface mapping @@ -9235,20 +10241,25 @@ set psu_mio_init_data { mask_write 0XFF180094 0x000000FE 0x00000008 # Register : MIO_PIN_38 @ 0XFF180098

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_clk- (TX RGMII clock) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ + # clk- (TX RGMII clock) # PSU_IOU_SLCR_MIO_PIN_38_L0_SEL 0 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used # PSU_IOU_SLCR_MIO_PIN_38_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= Not Used 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- + # (SDSDIO clock) 2= Not Used 3= Not Used # PSU_IOU_SLCR_MIO_PIN_38_L2_SEL 0 - # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[12]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[12]- (GPIO bank 1) 1= c - # n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - # l) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Clo - # k) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, trace_clk- - # (Trace Port Clock) + # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[12]- (GPIO bank 1) 0= + # gpio1, Output, gpio_1_pin_out[12]- (GPIO bank 1) 1= can0, Input, can0_ph + # y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + # c0, Output, i2c0_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTA + # G TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_s + # clk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, In + # put, ua0_rxd- (UART receiver serial input) 7= trace, Output, trace_clk- + # (Trace Port Clock) # PSU_IOU_SLCR_MIO_PIN_38_L3_SEL 0 # Configures MIO Pin 38 peripheral interface mapping @@ -9256,130 +10267,163 @@ set psu_mio_init_data { mask_write 0XFF180098 0x000000FE 0x00000000 # Register : MIO_PIN_39 @ 0XFF18009C

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[0]- (TX RGMII data) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd + # [0]- (TX RGMII data) # PSU_IOU_SLCR_MIO_PIN_39_L0_SEL 0 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used # PSU_IOU_SLCR_MIO_PIN_39_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= sd1, Input, sd1_data_i - # [4]- (8-bit Data bus) = sd1, Output, sdio1_data_out[4]- (8-bit Data bus) 3= Not Used - # PSU_IOU_SLCR_MIO_PIN_39_L2_SEL 0 + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD + # card detect from connector) 2= sd1, Input, sd1_data_in[4]- (8-bit Data b + # us) = sd1, Output, sdio1_data_out[4]- (8-bit Data bus) 3= Not Used + # PSU_IOU_SLCR_MIO_PIN_39_L2_SEL 2 - # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[13]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[13]- (GPIO bank 1) 1= c - # n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - # al) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc0, Output, ttc0_wav - # _out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, trace_ctl- (Trace Port - # Control Signal) + # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[13]- (GPIO bank 1) 0= + # gpio1, Output, gpio_1_pin_out[13]- (GPIO bank 1) 1= can0, Output, can0_p + # hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + # 2c0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJT + # AG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc0, + # Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (U + # ART transmitter serial output) 7= trace, Output, trace_ctl- (Trace Port + # Control Signal) # PSU_IOU_SLCR_MIO_PIN_39_L3_SEL 0 # Configures MIO Pin 39 peripheral interface mapping - #(OFFSET, MASK, VALUE) (0XFF18009C, 0x000000FEU ,0x00000000U) */ - mask_write 0XFF18009C 0x000000FE 0x00000000 + #(OFFSET, MASK, VALUE) (0XFF18009C, 0x000000FEU ,0x00000010U) */ + mask_write 0XFF18009C 0x000000FE 0x00000010 # Register : MIO_PIN_40 @ 0XFF1800A0

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[1]- (TX RGMII data) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd + # [1]- (TX RGMII data) # PSU_IOU_SLCR_MIO_PIN_40_L0_SEL 0 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used # PSU_IOU_SLCR_MIO_PIN_40_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Comman - # Indicator) 2= sd1, Input, sd1_data_in[5]- (8-bit Data bus) = sd1, Output, sdio1_data_out[5]- (8-bit Data bus) 3= Not Used - # PSU_IOU_SLCR_MIO_PIN_40_L2_SEL 0 + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Com + # mand Indicator) = sd0, Output, sdio0_cmd_out- (Command Indicator) 2= sd1 + # , Input, sd1_data_in[5]- (8-bit Data bus) = sd1, Output, sdio1_data_out[ + # 5]- (8-bit Data bus) 3= Not Used + # PSU_IOU_SLCR_MIO_PIN_40_L2_SEL 2 - # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[14]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[14]- (GPIO bank 1) 1= c - # n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - # al) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc3, Input, ttc3_clk - # in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[0]- (Trace Port Databus) + # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[14]- (GPIO bank 1) 0= + # gpio1, Output, gpio_1_pin_out[14]- (GPIO bank 1) 1= can1, Output, can1_p + # hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + # 2c1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJ + # TAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc3 + # , Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmi + # tter serial output) 7= trace, Output, tracedq[0]- (Trace Port Databus) # PSU_IOU_SLCR_MIO_PIN_40_L3_SEL 0 # Configures MIO Pin 40 peripheral interface mapping - #(OFFSET, MASK, VALUE) (0XFF1800A0, 0x000000FEU ,0x00000000U) */ - mask_write 0XFF1800A0 0x000000FE 0x00000000 + #(OFFSET, MASK, VALUE) (0XFF1800A0, 0x000000FEU ,0x00000010U) */ + mask_write 0XFF1800A0 0x000000FE 0x00000010 # Register : MIO_PIN_41 @ 0XFF1800A4

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[2]- (TX RGMII data) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd + # [2]- (TX RGMII data) # PSU_IOU_SLCR_MIO_PIN_41_L0_SEL 0 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used # PSU_IOU_SLCR_MIO_PIN_41_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8 - # bit Data bus) 2= sd1, Input, sd1_data_in[6]- (8-bit Data bus) = sd1, Output, sdio1_data_out[6]- (8-bit Data bus) 3= Not Used - # PSU_IOU_SLCR_MIO_PIN_41_L2_SEL 0 + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- + # (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8-bit Data bus) 2= s + # d1, Input, sd1_data_in[6]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + # t[6]- (8-bit Data bus) 3= Not Used + # PSU_IOU_SLCR_MIO_PIN_41_L2_SEL 2 - # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[15]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[15]- (GPIO bank 1) 1= c - # n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - # l) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[ - # ]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial in - # ut) 7= trace, Output, tracedq[1]- (Trace Port Databus) + # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[15]- (GPIO bank 1) 0= + # gpio1, Output, gpio_1_pin_out[15]- (GPIO bank 1) 1= can1, Input, can1_ph + # y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + # c1, Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTA + # G TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Outpu + # t, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out + # - (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial inp + # ut) 7= trace, Output, tracedq[1]- (Trace Port Databus) # PSU_IOU_SLCR_MIO_PIN_41_L3_SEL 0 # Configures MIO Pin 41 peripheral interface mapping - #(OFFSET, MASK, VALUE) (0XFF1800A4, 0x000000FEU ,0x00000000U) */ - mask_write 0XFF1800A4 0x000000FE 0x00000000 + #(OFFSET, MASK, VALUE) (0XFF1800A4, 0x000000FEU ,0x00000010U) */ + mask_write 0XFF1800A4 0x000000FE 0x00000010 # Register : MIO_PIN_42 @ 0XFF1800A8

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[3]- (TX RGMII data) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd + # [3]- (TX RGMII data) # PSU_IOU_SLCR_MIO_PIN_42_L0_SEL 0 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used # PSU_IOU_SLCR_MIO_PIN_42_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8 - # bit Data bus) 2= sd1, Input, sd1_data_in[7]- (8-bit Data bus) = sd1, Output, sdio1_data_out[7]- (8-bit Data bus) 3= Not Used - # PSU_IOU_SLCR_MIO_PIN_42_L2_SEL 0 + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- + # (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8-bit Data bus) 2= s + # d1, Input, sd1_data_in[7]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + # t[7]- (8-bit Data bus) 3= Not Used + # PSU_IOU_SLCR_MIO_PIN_42_L2_SEL 2 - # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1) 1= c - # n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - # l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_ - # o- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outp - # t, tracedq[2]- (Trace Port Databus) + # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1) 0= + # gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1) 1= can0, Input, can0_ph + # y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + # c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + # atch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= sp + # i0, Output, spi0_so- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clo + # ck) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outpu + # t, tracedq[2]- (Trace Port Databus) # PSU_IOU_SLCR_MIO_PIN_42_L3_SEL 0 # Configures MIO Pin 42 peripheral interface mapping - #(OFFSET, MASK, VALUE) (0XFF1800A8, 0x000000FEU ,0x00000000U) */ - mask_write 0XFF1800A8 0x000000FE 0x00000000 + #(OFFSET, MASK, VALUE) (0XFF1800A8, 0x000000FEU ,0x00000010U) */ + mask_write 0XFF1800A8 0x000000FE 0x00000010 # Register : MIO_PIN_43 @ 0XFF1800AC

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ctl- (TX RGMII control) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ + # ctl- (TX RGMII control) # PSU_IOU_SLCR_MIO_PIN_43_L0_SEL 0 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used # PSU_IOU_SLCR_MIO_PIN_43_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8 - # bit Data bus) 2= sd1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used - # PSU_IOU_SLCR_MIO_PIN_43_L2_SEL 2 + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- + # (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8-bit Data bus) 2= s + # d1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used + # PSU_IOU_SLCR_MIO_PIN_43_L2_SEL 0 - # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1) 1= c - # n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - # al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, s - # i0_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o - # tput) 7= trace, Output, tracedq[3]- (Trace Port Databus) + # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1) 0= + # gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1) 1= can0, Output, can0_p + # hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + # 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + # (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) + # 4= spi0, Input, spi0_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- ( + # TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial ou + # tput) 7= trace, Output, tracedq[3]- (Trace Port Databus) # PSU_IOU_SLCR_MIO_PIN_43_L3_SEL 0 # Configures MIO Pin 43 peripheral interface mapping - #(OFFSET, MASK, VALUE) (0XFF1800AC, 0x000000FEU ,0x00000010U) */ - mask_write 0XFF1800AC 0x000000FE 0x00000010 + #(OFFSET, MASK, VALUE) (0XFF1800AC, 0x000000FEU ,0x00000000U) */ + mask_write 0XFF1800AC 0x000000FE 0x00000000 # Register : MIO_PIN_44 @ 0XFF1800B0

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_clk- (RX RGMII clock) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_c + # lk- (RX RGMII clock) # PSU_IOU_SLCR_MIO_PIN_44_L0_SEL 0 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used # PSU_IOU_SLCR_MIO_PIN_44_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8 - # bit Data bus) 2= sd1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- + # (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8-bit Data bus) 2= s + # d1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used # PSU_IOU_SLCR_MIO_PIN_44_L2_SEL 2 - # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[18]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[18]- (GPIO bank 1) 1= c - # n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - # al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, s - # i1_sclk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7 - # Not Used + # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[18]- (GPIO bank 1) 0= + # gpio1, Output, gpio_1_pin_out[18]- (GPIO bank 1) 1= can1, Output, can1_p + # hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + # 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + # Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4 + # = spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- + # (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= + # Not Used # PSU_IOU_SLCR_MIO_PIN_44_L3_SEL 0 # Configures MIO Pin 44 peripheral interface mapping @@ -9387,20 +10431,25 @@ set psu_mio_init_data { mask_write 0XFF1800B0 0x000000FE 0x00000010 # Register : MIO_PIN_45 @ 0XFF1800B4

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[0]- (RX RGMII data) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[ + # 0]- (RX RGMII data) # PSU_IOU_SLCR_MIO_PIN_45_L0_SEL 0 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used # PSU_IOU_SLCR_MIO_PIN_45_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8 - # bit Data bus) 2= sd1, Input, sdio1_cd_n- (SD card detect from connector) 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- + # (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8-bit Data bus) 2= s + # d1, Input, sdio1_cd_n- (SD card detect from connector) 3= Not Used # PSU_IOU_SLCR_MIO_PIN_45_L2_SEL 2 - # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[19]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[19]- (GPIO bank 1) 1= c - # n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - # l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= - # ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used + # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[19]- (GPIO bank 1) 0= + # gpio1, Output, gpio_1_pin_out[19]- (GPIO bank 1) 1= can1, Input, can1_ph + # y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + # c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + # (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI M + # aster Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= u + # a1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used # PSU_IOU_SLCR_MIO_PIN_45_L3_SEL 0 # Configures MIO Pin 45 peripheral interface mapping @@ -9408,20 +10457,26 @@ set psu_mio_init_data { mask_write 0XFF1800B4 0x000000FE 0x00000010 # Register : MIO_PIN_46 @ 0XFF1800B8

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[1]- (RX RGMII data) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[ + # 1]- (RX RGMII data) # PSU_IOU_SLCR_MIO_PIN_46_L0_SEL 0 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used # PSU_IOU_SLCR_MIO_PIN_46_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8 - # bit Data bus) 2= sd1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_out[0]- (8-bit Data bus) 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- + # (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8-bit Data bus) 2= s + # d1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + # t[0]- (8-bit Data bus) 3= Not Used # PSU_IOU_SLCR_MIO_PIN_46_L2_SEL 2 - # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1) 1= c - # n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - # l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= tt - # 0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used + # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1) 0= + # gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1) 1= can0, Input, can0_ph + # y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + # c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + # atch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Mast + # er Selects) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_ + # rxd- (UART receiver serial input) 7= Not Used # PSU_IOU_SLCR_MIO_PIN_46_L3_SEL 0 # Configures MIO Pin 46 peripheral interface mapping @@ -9429,21 +10484,27 @@ set psu_mio_init_data { mask_write 0XFF1800B8 0x000000FE 0x00000010 # Register : MIO_PIN_47 @ 0XFF1800BC

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[2]- (RX RGMII data) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[ + # 2]- (RX RGMII data) # PSU_IOU_SLCR_MIO_PIN_47_L0_SEL 0 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used # PSU_IOU_SLCR_MIO_PIN_47_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8 - # bit Data bus) 2= sd1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_out[1]- (8-bit Data bus) 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- + # (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8-bit Data bus) 2= s + # d1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + # t[1]- (8-bit Data bus) 3= Not Used # PSU_IOU_SLCR_MIO_PIN_47_L2_SEL 2 - # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1) 1= c - # n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - # al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi - # , Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd - # (UART transmitter serial output) 7= Not Used + # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1) 0= + # gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1) 1= can0, Output, can0_p + # hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + # 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + # (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Maste + # r Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= tt + # c0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- + # (UART transmitter serial output) 7= Not Used # PSU_IOU_SLCR_MIO_PIN_47_L3_SEL 0 # Configures MIO Pin 47 peripheral interface mapping @@ -9451,21 +10512,27 @@ set psu_mio_init_data { mask_write 0XFF1800BC 0x000000FE 0x00000010 # Register : MIO_PIN_48 @ 0XFF1800C0

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[3]- (RX RGMII data) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[ + # 3]- (RX RGMII data) # PSU_IOU_SLCR_MIO_PIN_48_L0_SEL 0 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used # PSU_IOU_SLCR_MIO_PIN_48_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8 - # bit Data bus) 2= sd1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_out[2]- (8-bit Data bus) 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- + # (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8-bit Data bus) 2= s + # d1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + # t[2]- (8-bit Data bus) 3= Not Used # PSU_IOU_SLCR_MIO_PIN_48_L2_SEL 2 - # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[22]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[22]- (GPIO bank 1) 1= c - # n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - # al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1 - # so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not U - # ed + # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[22]- (GPIO bank 1) 0= + # gpio1, Output, gpio_1_pin_out[22]- (GPIO bank 1) 1= can1, Output, can1_p + # hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + # 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + # Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= s + # pi1, Output, spi1_so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Cl + # ock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Us + # ed # PSU_IOU_SLCR_MIO_PIN_48_L3_SEL 0 # Configures MIO Pin 48 peripheral interface mapping @@ -9473,21 +10540,26 @@ set psu_mio_init_data { mask_write 0XFF1800C0 0x000000FE 0x00000010 # Register : MIO_PIN_49 @ 0XFF1800C4

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_ctl- (RX RGMII control ) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_c + # tl- (RX RGMII control ) # PSU_IOU_SLCR_MIO_PIN_49_L0_SEL 0 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used # PSU_IOU_SLCR_MIO_PIN_49_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= sd1, Input, sd1_data_in[3]- (8 - # bit Data bus) = sd1, Output, sdio1_data_out[3]- (8-bit Data bus) 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- + # (SD card bus power) 2= sd1, Input, sd1_data_in[3]- (8-bit Data bus) = sd + # 1, Output, sdio1_data_out[3]- (8-bit Data bus) 3= Not Used # PSU_IOU_SLCR_MIO_PIN_49_L2_SEL 2 - # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[23]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[23]- (GPIO bank 1) 1= c - # n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - # l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, sp - # 1_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) - # 7= Not Used + # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[23]- (GPIO bank 1) 0= + # gpio1, Output, gpio_1_pin_out[23]- (GPIO bank 1) 1= can1, Input, can1_ph + # y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + # c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + # (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4 + # = spi1, Input, spi1_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (T + # TC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) + # 7= Not Used # PSU_IOU_SLCR_MIO_PIN_49_L3_SEL 0 # Configures MIO Pin 49 peripheral interface mapping @@ -9495,20 +10567,25 @@ set psu_mio_init_data { mask_write 0XFF1800C4 0x000000FE 0x00000010 # Register : MIO_PIN_50 @ 0XFF1800C8

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- (TSU clock) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- + # (TSU clock) # PSU_IOU_SLCR_MIO_PIN_50_L0_SEL 0 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used # PSU_IOU_SLCR_MIO_PIN_50_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= sd1, Input, sd1_c - # d_in- (Command Indicator) = sd1, Output, sdio1_cmd_out- (Command Indicator) 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD ca + # rd write protect from connector) 2= sd1, Input, sd1_cmd_in- (Command Ind + # icator) = sd1, Output, sdio1_cmd_out- (Command Indicator) 3= Not Used # PSU_IOU_SLCR_MIO_PIN_50_L2_SEL 2 - # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[24]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[24]- (GPIO bank 1) 1= c - # n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - # l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= ttc2, Input, ttc2 - # clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used + # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[24]- (GPIO bank 1) 0= + # gpio1, Output, gpio_1_pin_out[24]- (GPIO bank 1) 1= can0, Input, can0_ph + # y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + # c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + # atch Dog Timer Input clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= + # ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART rece + # iver serial input) 7= Not Used # PSU_IOU_SLCR_MIO_PIN_50_L3_SEL 0 # Configures MIO Pin 50 peripheral interface mapping @@ -9516,20 +10593,25 @@ set psu_mio_init_data { mask_write 0XFF1800C8 0x000000FE 0x00000010 # Register : MIO_PIN_51 @ 0XFF1800CC

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- (TSU clock) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- + # (TSU clock) # PSU_IOU_SLCR_MIO_PIN_51_L0_SEL 0 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used # PSU_IOU_SLCR_MIO_PIN_51_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Output, sdio1_clk_out- (SDSDIO clock) 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Output, sdi + # o1_clk_out- (SDSDIO clock) 3= Not Used # PSU_IOU_SLCR_MIO_PIN_51_L2_SEL 2 - # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[25]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[25]- (GPIO bank 1) 1= c - # n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - # al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= mdio1, Input, gem1_mdio_in- (MDIO Data) 4= mdio1, Outp - # t, gem1_mdio_out- (MDIO Data) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter - # serial output) 7= Not Used + # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[25]- (GPIO bank 1) 0= + # gpio1, Output, gpio_1_pin_out[25]- (GPIO bank 1) 1= can0, Output, can0_p + # hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + # 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + # (Watch Dog Timer Output clock) 4= mdio1, Input, gem1_mdio_in- (MDIO Dat + # a) 4= mdio1, Output, gem1_mdio_out- (MDIO Data) 5= ttc2, Output, ttc2_wa + # ve_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter + # serial output) 7= Not Used # PSU_IOU_SLCR_MIO_PIN_51_L3_SEL 0 # Configures MIO Pin 51 peripheral interface mapping @@ -9537,20 +10619,26 @@ set psu_mio_init_data { mask_write 0XFF1800CC 0x000000FE 0x00000010 # Register : MIO_PIN_52 @ 0XFF1800D0

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_clk- (TX RGMII clock) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_ + # clk- (TX RGMII clock) # PSU_IOU_SLCR_MIO_PIN_52_L0_SEL 0 - # Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_clk_in- (ULPI Clock) + # Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_clk_i + # n- (ULPI Clock) # PSU_IOU_SLCR_MIO_PIN_52_L1_SEL 1 - # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + # Used # PSU_IOU_SLCR_MIO_PIN_52_L2_SEL 0 - # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[0]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[0]- (GPIO bank 2) 1= can - # , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa - # ) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Cloc - # ) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_ - # lk- (Trace Port Clock) + # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[0]- (GPIO bank 2) 0= g + # pio2, Output, gpio_2_pin_out[0]- (GPIO bank 2) 1= can1, Output, can1_phy + # _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + # 1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG + # TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sc + # lk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Out + # put, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_c + # lk- (Trace Port Clock) # PSU_IOU_SLCR_MIO_PIN_52_L3_SEL 0 # Configures MIO Pin 52 peripheral interface mapping @@ -9558,20 +10646,26 @@ set psu_mio_init_data { mask_write 0XFF1800D0 0x000000FE 0x00000004 # Register : MIO_PIN_53 @ 0XFF1800D4

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[0]- (TX RGMII data) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd + # [0]- (TX RGMII data) # PSU_IOU_SLCR_MIO_PIN_53_L0_SEL 0 - # Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_dir- (Data bus direction control) + # Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_dir- + # (Data bus direction control) # PSU_IOU_SLCR_MIO_PIN_53_L1_SEL 1 - # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + # Used # PSU_IOU_SLCR_MIO_PIN_53_L2_SEL 0 - # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[1]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[1]- (GPIO bank 2) 1= can - # , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal - # 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_o - # t- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control - # Signal) + # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[1]- (GPIO bank 2) 0= g + # pio2, Output, gpio_2_pin_out[1]- (GPIO bank 2) 1= can1, Input, can1_phy_ + # rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + # , Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG + # TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Ou + # tput, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART + # receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control + # Signal) # PSU_IOU_SLCR_MIO_PIN_53_L3_SEL 0 # Configures MIO Pin 53 peripheral interface mapping @@ -9579,20 +10673,26 @@ set psu_mio_init_data { mask_write 0XFF1800D4 0x000000FE 0x00000004 # Register : MIO_PIN_54 @ 0XFF1800D8

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[1]- (TX RGMII data) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd + # [1]- (TX RGMII data) # PSU_IOU_SLCR_MIO_PIN_54_L0_SEL 0 - # Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[2]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_ - # ata[2]- (ULPI data bus) + # Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + # ta[2]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[2]- (ULPI data + # bus) # PSU_IOU_SLCR_MIO_PIN_54_L1_SEL 1 - # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + # Used # PSU_IOU_SLCR_MIO_PIN_54_L2_SEL 0 - # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[2]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[2]- (GPIO bank 2) 1= can - # , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal - # 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, Input, ttc0_clk_in - # (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[0]- (Trace Port Databus) + # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[2]- (GPIO bank 2) 0= g + # pio2, Output, gpio_2_pin_out[2]- (GPIO bank 2) 1= can0, Input, can0_phy_ + # rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + # , Output, i2c0_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTAG + # TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, I + # nput, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver se + # rial input) 7= trace, Output, tracedq[0]- (Trace Port Databus) # PSU_IOU_SLCR_MIO_PIN_54_L3_SEL 0 # Configures MIO Pin 54 peripheral interface mapping @@ -9600,20 +10700,26 @@ set psu_mio_init_data { mask_write 0XFF1800D8 0x000000FE 0x00000004 # Register : MIO_PIN_55 @ 0XFF1800DC

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[2]- (TX RGMII data) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd + # [2]- (TX RGMII data) # PSU_IOU_SLCR_MIO_PIN_55_L0_SEL 0 - # Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_nxt- (Data flow control signal from the PHY) + # Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_nxt- + # (Data flow control signal from the PHY) # PSU_IOU_SLCR_MIO_PIN_55_L1_SEL 1 - # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + # Used # PSU_IOU_SLCR_MIO_PIN_55_L2_SEL 0 - # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[3]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[3]- (GPIO bank 2) 1= can - # , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa - # ) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0 - # - (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial - # output) 7= trace, Output, tracedq[1]- (Trace Port Databus) + # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[3]- (GPIO bank 2) 0= g + # pio2, Output, gpio_2_pin_out[3]- (GPIO bank 2) 1= can0, Output, can0_phy + # _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + # 0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG + # TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output + # , spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- + # (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial + # output) 7= trace, Output, tracedq[1]- (Trace Port Databus) # PSU_IOU_SLCR_MIO_PIN_55_L3_SEL 0 # Configures MIO Pin 55 peripheral interface mapping @@ -9621,21 +10727,27 @@ set psu_mio_init_data { mask_write 0XFF1800DC 0x000000FE 0x00000004 # Register : MIO_PIN_56 @ 0XFF1800E0

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[3]- (TX RGMII data) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd + # [3]- (TX RGMII data) # PSU_IOU_SLCR_MIO_PIN_56_L0_SEL 0 - # Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[0]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_ - # ata[0]- (ULPI data bus) + # Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + # ta[0]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[0]- (ULPI data + # bus) # PSU_IOU_SLCR_MIO_PIN_56_L1_SEL 1 - # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + # Used # PSU_IOU_SLCR_MIO_PIN_56_L2_SEL 0 - # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[4]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[4]- (GPIO bank 2) 1= can - # , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa - # ) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_s - # - (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, - # utput, tracedq[2]- (Trace Port Databus) + # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[4]- (GPIO bank 2) 0= g + # pio2, Output, gpio_2_pin_out[4]- (GPIO bank 2) 1= can1, Output, can1_phy + # _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + # 1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Wa + # tch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi + # 0, Output, spi0_so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Cloc + # k) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, O + # utput, tracedq[2]- (Trace Port Databus) # PSU_IOU_SLCR_MIO_PIN_56_L3_SEL 0 # Configures MIO Pin 56 peripheral interface mapping @@ -9643,21 +10755,27 @@ set psu_mio_init_data { mask_write 0XFF1800E0 0x000000FE 0x00000004 # Register : MIO_PIN_57 @ 0XFF1800E4

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_ctl- (TX RGMII control) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_ + # ctl- (TX RGMII control) # PSU_IOU_SLCR_MIO_PIN_57_L0_SEL 0 - # Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[1]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_ - # ata[1]- (ULPI data bus) + # Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + # ta[1]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[1]- (ULPI data + # bus) # PSU_IOU_SLCR_MIO_PIN_57_L1_SEL 1 - # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + # Used # PSU_IOU_SLCR_MIO_PIN_57_L2_SEL 0 - # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[5]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[5]- (GPIO bank 2) 1= can - # , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal - # 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi0 - # si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7 - # trace, Output, tracedq[3]- (Trace Port Databus) + # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[5]- (GPIO bank 2) 0= g + # pio2, Output, gpio_2_pin_out[5]- (GPIO bank 2) 1= can1, Input, can1_phy_ + # rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + # , Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (W + # atch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= + # spi0, Input, spi0_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC + # Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= + # trace, Output, tracedq[3]- (Trace Port Databus) # PSU_IOU_SLCR_MIO_PIN_57_L3_SEL 0 # Configures MIO Pin 57 peripheral interface mapping @@ -9665,20 +10783,26 @@ set psu_mio_init_data { mask_write 0XFF1800E4 0x000000FE 0x00000004 # Register : MIO_PIN_58 @ 0XFF1800E8

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_clk- (RX RGMII clock) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_c + # lk- (RX RGMII clock) # PSU_IOU_SLCR_MIO_PIN_58_L0_SEL 0 - # Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Output, usb0_ulpi_stp- (Asserted to end or interrupt transfers) + # Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Output, usb0_ulpi_stp- + # (Asserted to end or interrupt transfers) # PSU_IOU_SLCR_MIO_PIN_58_L1_SEL 1 - # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + # Used # PSU_IOU_SLCR_MIO_PIN_58_L2_SEL 0 - # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[6]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[6]- (GPIO bank 2) 1= can - # , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal - # 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1_sclk_out- (SPI Clock - # 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- - # Trace Port Databus) + # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[6]- (GPIO bank 2) 0= g + # pio2, Output, gpio_2_pin_out[6]- (GPIO bank 2) 1= can0, Input, can0_phy_ + # rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + # , Output, i2c0_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG + # TCK) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1_scl + # k_out- (SPI Clock) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Inpu + # t, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- ( + # Trace Port Databus) # PSU_IOU_SLCR_MIO_PIN_58_L3_SEL 0 # Configures MIO Pin 58 peripheral interface mapping @@ -9686,21 +10810,27 @@ set psu_mio_init_data { mask_write 0XFF1800E8 0x000000FE 0x00000004 # Register : MIO_PIN_59 @ 0XFF1800EC

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[0]- (RX RGMII data) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[ + # 0]- (RX RGMII data) # PSU_IOU_SLCR_MIO_PIN_59_L0_SEL 0 - # Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[3]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_ - # ata[3]- (ULPI data bus) + # Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + # ta[3]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[3]- (ULPI data + # bus) # PSU_IOU_SLCR_MIO_PIN_59_L1_SEL 1 - # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + # Used # PSU_IOU_SLCR_MIO_PIN_59_L2_SEL 0 - # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[7]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[7]- (GPIO bank 2) 1= can - # , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa - # ) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_ - # ut- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port - # atabus) + # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[7]- (GPIO bank 2) 0= g + # pio2, Output, gpio_2_pin_out[7]- (GPIO bank 2) 1= can0, Output, can0_phy + # _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + # 0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG + # TDI) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= ttc2, O + # utput, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UAR + # T transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port D + # atabus) # PSU_IOU_SLCR_MIO_PIN_59_L3_SEL 0 # Configures MIO Pin 59 peripheral interface mapping @@ -9708,20 +10838,26 @@ set psu_mio_init_data { mask_write 0XFF1800EC 0x000000FE 0x00000004 # Register : MIO_PIN_60 @ 0XFF1800F0

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[1]- (RX RGMII data) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[ + # 1]- (RX RGMII data) # PSU_IOU_SLCR_MIO_PIN_60_L0_SEL 0 - # Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[4]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_ - # ata[4]- (ULPI data bus) + # Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + # ta[4]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[4]- (ULPI data + # bus) # PSU_IOU_SLCR_MIO_PIN_60_L1_SEL 1 - # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + # Used # PSU_IOU_SLCR_MIO_PIN_60_L2_SEL 0 - # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[8]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[8]- (GPIO bank 2) 1= can - # , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa - # ) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc1, Input, ttc1_clk_i - # - (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus) + # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[8]- (GPIO bank 2) 0= g + # pio2, Output, gpio_2_pin_out[8]- (GPIO bank 2) 1= can1, Output, can1_phy + # _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + # 1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTA + # G TDO) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc1, + # Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitt + # er serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus) # PSU_IOU_SLCR_MIO_PIN_60_L3_SEL 0 # Configures MIO Pin 60 peripheral interface mapping @@ -9729,21 +10865,27 @@ set psu_mio_init_data { mask_write 0XFF1800F0 0x000000FE 0x00000004 # Register : MIO_PIN_61 @ 0XFF1800F4

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[2]- (RX RGMII data) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[ + # 2]- (RX RGMII data) # PSU_IOU_SLCR_MIO_PIN_61_L0_SEL 0 - # Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[5]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_ - # ata[5]- (ULPI data bus) + # Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + # ta[5]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[5]- (ULPI data + # bus) # PSU_IOU_SLCR_MIO_PIN_61_L1_SEL 1 - # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + # Used # PSU_IOU_SLCR_MIO_PIN_61_L2_SEL 0 - # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[9]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[9]- (GPIO bank 2) 1= can - # , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal - # 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, Output, spi1_n_ss_out[0] - # (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial inpu - # ) 7= trace, Output, tracedq[7]- (Trace Port Databus) + # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[9]- (GPIO bank 2) 0= g + # pio2, Output, gpio_2_pin_out[9]- (GPIO bank 2) 1= can1, Input, can1_phy_ + # rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + # , Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG + # TMS) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, Output, + # spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- + # (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input + # ) 7= trace, Output, tracedq[7]- (Trace Port Databus) # PSU_IOU_SLCR_MIO_PIN_61_L3_SEL 0 # Configures MIO Pin 61 peripheral interface mapping @@ -9751,21 +10893,27 @@ set psu_mio_init_data { mask_write 0XFF1800F4 0x000000FE 0x00000004 # Register : MIO_PIN_62 @ 0XFF1800F8

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[3]- (RX RGMII data) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[ + # 3]- (RX RGMII data) # PSU_IOU_SLCR_MIO_PIN_62_L0_SEL 0 - # Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[6]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_ - # ata[6]- (ULPI data bus) + # Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + # ta[6]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[6]- (ULPI data + # bus) # PSU_IOU_SLCR_MIO_PIN_62_L1_SEL 1 - # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + # Used # PSU_IOU_SLCR_MIO_PIN_62_L2_SEL 0 - # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[10]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[10]- (GPIO bank 2) 1= c - # n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - # l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_ - # o- (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outp - # t, tracedq[8]- (Trace Port Databus) + # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[10]- (GPIO bank 2) 0= + # gpio2, Output, gpio_2_pin_out[10]- (GPIO bank 2) 1= can0, Input, can0_ph + # y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + # c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + # atch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= sp + # i1, Output, spi1_so- (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clo + # ck) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outpu + # t, tracedq[8]- (Trace Port Databus) # PSU_IOU_SLCR_MIO_PIN_62_L3_SEL 0 # Configures MIO Pin 62 peripheral interface mapping @@ -9773,21 +10921,27 @@ set psu_mio_init_data { mask_write 0XFF1800F8 0x000000FE 0x00000004 # Register : MIO_PIN_63 @ 0XFF1800FC

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_ctl- (RX RGMII control ) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_c + # tl- (RX RGMII control ) # PSU_IOU_SLCR_MIO_PIN_63_L0_SEL 0 - # Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[7]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_ - # ata[7]- (ULPI data bus) + # Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + # ta[7]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[7]- (ULPI data + # bus) # PSU_IOU_SLCR_MIO_PIN_63_L1_SEL 1 - # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + # Used # PSU_IOU_SLCR_MIO_PIN_63_L2_SEL 0 - # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[11]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[11]- (GPIO bank 2) 1= c - # n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - # al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s - # i1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o - # tput) 7= trace, Output, tracedq[9]- (Trace Port Databus) + # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[11]- (GPIO bank 2) 0= + # gpio2, Output, gpio_2_pin_out[11]- (GPIO bank 2) 1= can0, Output, can0_p + # hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + # 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + # (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) + # 4= spi1, Input, spi1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- ( + # TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial ou + # tput) 7= trace, Output, tracedq[9]- (Trace Port Databus) # PSU_IOU_SLCR_MIO_PIN_63_L3_SEL 0 # Configures MIO Pin 63 peripheral interface mapping @@ -9795,20 +10949,26 @@ set psu_mio_init_data { mask_write 0XFF1800FC 0x000000FE 0x00000004 # Register : MIO_PIN_64 @ 0XFF180100

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_clk- (TX RGMII clock) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_ + # clk- (TX RGMII clock) # PSU_IOU_SLCR_MIO_PIN_64_L0_SEL 1 - # Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_clk_in- (ULPI Clock) + # Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_clk_i + # n- (ULPI Clock) # PSU_IOU_SLCR_MIO_PIN_64_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= Not Used 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- + # (SDSDIO clock) 2= Not Used 3= Not Used # PSU_IOU_SLCR_MIO_PIN_64_L2_SEL 0 - # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[12]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[12]- (GPIO bank 2) 1= c - # n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - # al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, s - # i0_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7 - # trace, Output, tracedq[10]- (Trace Port Databus) + # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[12]- (GPIO bank 2) 0= + # gpio2, Output, gpio_2_pin_out[12]- (GPIO bank 2) 1= can1, Output, can1_p + # hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + # 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + # Watch Dog Timer Input clock) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4 + # = spi0, Output, spi0_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- + # (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= + # trace, Output, tracedq[10]- (Trace Port Databus) # PSU_IOU_SLCR_MIO_PIN_64_L3_SEL 0 # Configures MIO Pin 64 peripheral interface mapping @@ -9816,20 +10976,26 @@ set psu_mio_init_data { mask_write 0XFF180100 0x000000FE 0x00000002 # Register : MIO_PIN_65 @ 0XFF180104

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[0]- (TX RGMII data) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd + # [0]- (TX RGMII data) # PSU_IOU_SLCR_MIO_PIN_65_L0_SEL 1 - # Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_dir- (Data bus direction control) + # Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_dir- + # (Data bus direction control) # PSU_IOU_SLCR_MIO_PIN_65_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= Not Used 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD + # card detect from connector) 2= Not Used 3= Not Used # PSU_IOU_SLCR_MIO_PIN_65_L2_SEL 0 - # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[13]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[13]- (GPIO bank 2) 1= c - # n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - # l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= - # ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trac - # dq[11]- (Trace Port Databus) + # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[13]- (GPIO bank 2) 0= + # gpio2, Output, gpio_2_pin_out[13]- (GPIO bank 2) 1= can1, Input, can1_ph + # y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + # c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + # (Watch Dog Timer Output clock) 4= spi0, Output, spi0_n_ss_out[2]- (SPI M + # aster Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= u + # a1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trace + # dq[11]- (Trace Port Databus) # PSU_IOU_SLCR_MIO_PIN_65_L3_SEL 0 # Configures MIO Pin 65 peripheral interface mapping @@ -9837,22 +11003,28 @@ set psu_mio_init_data { mask_write 0XFF180104 0x000000FE 0x00000002 # Register : MIO_PIN_66 @ 0XFF180108

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[1]- (TX RGMII data) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd + # [1]- (TX RGMII data) # PSU_IOU_SLCR_MIO_PIN_66_L0_SEL 1 - # Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[2]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_ - # ata[2]- (ULPI data bus) + # Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + # ta[2]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[2]- (ULPI data + # bus) # PSU_IOU_SLCR_MIO_PIN_66_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Comman - # Indicator) 2= Not Used 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Com + # mand Indicator) = sd0, Output, sdio0_cmd_out- (Command Indicator) 2= Not + # Used 3= Not Used # PSU_IOU_SLCR_MIO_PIN_66_L2_SEL 0 - # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[14]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[14]- (GPIO bank 2) 1= c - # n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - # l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= tt - # 2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace - # Port Databus) + # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[14]- (GPIO bank 2) 0= + # gpio2, Output, gpio_2_pin_out[14]- (GPIO bank 2) 1= can0, Input, can0_ph + # y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + # c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + # atch Dog Timer Input clock) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Mast + # er Selects) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_ + # rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace + # Port Databus) # PSU_IOU_SLCR_MIO_PIN_66_L3_SEL 0 # Configures MIO Pin 66 peripheral interface mapping @@ -9860,21 +11032,28 @@ set psu_mio_init_data { mask_write 0XFF180108 0x000000FE 0x00000002 # Register : MIO_PIN_67 @ 0XFF18010C

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[2]- (TX RGMII data) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd + # [2]- (TX RGMII data) # PSU_IOU_SLCR_MIO_PIN_67_L0_SEL 1 - # Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_nxt- (Data flow control signal from the PHY) + # Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_nxt- + # (Data flow control signal from the PHY) # PSU_IOU_SLCR_MIO_PIN_67_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8 - # bit Data bus) 2= Not Used 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- + # (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8-bit Data bus) 2= N + # ot Used 3= Not Used # PSU_IOU_SLCR_MIO_PIN_67_L2_SEL 0 - # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[15]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[15]- (GPIO bank 2) 1= c - # n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - # al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi - # , Output, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd - # (UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace Port Databus) + # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[15]- (GPIO bank 2) 0= + # gpio2, Output, gpio_2_pin_out[15]- (GPIO bank 2) 1= can0, Output, can0_p + # hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + # 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + # (Watch Dog Timer Output clock) 4= spi0, Input, spi0_n_ss_in- (SPI Maste + # r Selects) 4= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 5= tt + # c2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- + # (UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace + # Port Databus) # PSU_IOU_SLCR_MIO_PIN_67_L3_SEL 0 # Configures MIO Pin 67 peripheral interface mapping @@ -9882,22 +11061,28 @@ set psu_mio_init_data { mask_write 0XFF18010C 0x000000FE 0x00000002 # Register : MIO_PIN_68 @ 0XFF180110

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[3]- (TX RGMII data) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd + # [3]- (TX RGMII data) # PSU_IOU_SLCR_MIO_PIN_68_L0_SEL 1 - # Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[0]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_ - # ata[0]- (ULPI data bus) + # Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + # ta[0]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[0]- (ULPI data + # bus) # PSU_IOU_SLCR_MIO_PIN_68_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8 - # bit Data bus) 2= Not Used 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- + # (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8-bit Data bus) 2= N + # ot Used 3= Not Used # PSU_IOU_SLCR_MIO_PIN_68_L2_SEL 0 - # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[16]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[16]- (GPIO bank 2) 1= c - # n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - # al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0 - # so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace - # Output, tracedq[14]- (Trace Port Databus) + # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[16]- (GPIO bank 2) 0= + # gpio2, Output, gpio_2_pin_out[16]- (GPIO bank 2) 1= can1, Output, can1_p + # hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + # 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + # Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= s + # pi0, Output, spi0_so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Cl + # ock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, + # Output, tracedq[14]- (Trace Port Databus) # PSU_IOU_SLCR_MIO_PIN_68_L3_SEL 0 # Configures MIO Pin 68 peripheral interface mapping @@ -9905,22 +11090,28 @@ set psu_mio_init_data { mask_write 0XFF180110 0x000000FE 0x00000002 # Register : MIO_PIN_69 @ 0XFF180114

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_ctl- (TX RGMII control) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_ + # ctl- (TX RGMII control) # PSU_IOU_SLCR_MIO_PIN_69_L0_SEL 1 - # Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[1]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_ - # ata[1]- (ULPI data bus) + # Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + # ta[1]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[1]- (ULPI data + # bus) # PSU_IOU_SLCR_MIO_PIN_69_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8 - # bit Data bus) 2= sd1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- + # (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8-bit Data bus) 2= s + # d1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used # PSU_IOU_SLCR_MIO_PIN_69_L2_SEL 0 - # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[17]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[17]- (GPIO bank 2) 1= c - # n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - # l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, sp - # 0_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) - # 7= trace, Output, tracedq[15]- (Trace Port Databus) + # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[17]- (GPIO bank 2) 0= + # gpio2, Output, gpio_2_pin_out[17]- (GPIO bank 2) 1= can1, Input, can1_ph + # y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + # c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + # (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4 + # = spi0, Input, spi0_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (T + # TC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) + # 7= trace, Output, tracedq[15]- (Trace Port Databus) # PSU_IOU_SLCR_MIO_PIN_69_L3_SEL 0 # Configures MIO Pin 69 peripheral interface mapping @@ -9928,21 +11119,27 @@ set psu_mio_init_data { mask_write 0XFF180114 0x000000FE 0x00000002 # Register : MIO_PIN_70 @ 0XFF180118

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_clk- (RX RGMII clock) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_c + # lk- (RX RGMII clock) # PSU_IOU_SLCR_MIO_PIN_70_L0_SEL 1 - # Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Output, usb1_ulpi_stp- (Asserted to end or interrupt transfers) + # Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Output, usb1_ulpi_stp- + # (Asserted to end or interrupt transfers) # PSU_IOU_SLCR_MIO_PIN_70_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8 - # bit Data bus) 2= sd1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- + # (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8-bit Data bus) 2= s + # d1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used # PSU_IOU_SLCR_MIO_PIN_70_L2_SEL 0 - # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[18]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[18]- (GPIO bank 2) 1= c - # n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - # l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, sp - # 1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not - # sed + # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[18]- (GPIO bank 2) 0= + # gpio2, Output, gpio_2_pin_out[18]- (GPIO bank 2) 1= can0, Input, can0_ph + # y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + # c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + # atch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= + # spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- ( + # TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not U + # sed # PSU_IOU_SLCR_MIO_PIN_70_L3_SEL 0 # Configures MIO Pin 70 peripheral interface mapping @@ -9950,21 +11147,28 @@ set psu_mio_init_data { mask_write 0XFF180118 0x000000FE 0x00000002 # Register : MIO_PIN_71 @ 0XFF18011C

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[0]- (RX RGMII data) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[ + # 0]- (RX RGMII data) # PSU_IOU_SLCR_MIO_PIN_71_L0_SEL 1 - # Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[3]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_ - # ata[3]- (ULPI data bus) + # Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + # ta[3]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[3]- (ULPI data + # bus) # PSU_IOU_SLCR_MIO_PIN_71_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8 - # bit Data bus) 2= sd1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_out[0]- (8-bit Data bus) 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- + # (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8-bit Data bus) 2= s + # d1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + # t[0]- (8-bit Data bus) 3= Not Used # PSU_IOU_SLCR_MIO_PIN_71_L2_SEL 0 - # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[19]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[19]- (GPIO bank 2) 1= c - # n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - # al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5 - # ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used + # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[19]- (GPIO bank 2) 0= + # gpio2, Output, gpio_2_pin_out[19]- (GPIO bank 2) 1= can0, Output, can0_p + # hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + # 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + # (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI + # Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= + # ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used # PSU_IOU_SLCR_MIO_PIN_71_L3_SEL 0 # Configures MIO Pin 71 peripheral interface mapping @@ -9972,21 +11176,28 @@ set psu_mio_init_data { mask_write 0XFF18011C 0x000000FE 0x00000002 # Register : MIO_PIN_72 @ 0XFF180120

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[1]- (RX RGMII data) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[ + # 1]- (RX RGMII data) # PSU_IOU_SLCR_MIO_PIN_72_L0_SEL 1 - # Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[4]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_ - # ata[4]- (ULPI data bus) + # Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + # ta[4]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[4]- (ULPI data + # bus) # PSU_IOU_SLCR_MIO_PIN_72_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8 - # bit Data bus) 2= sd1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_out[1]- (8-bit Data bus) 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- + # (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8-bit Data bus) 2= s + # d1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + # t[1]- (8-bit Data bus) 3= Not Used # PSU_IOU_SLCR_MIO_PIN_72_L2_SEL 0 - # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[20]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[20]- (GPIO bank 2) 1= c - # n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - # al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= N - # t Used 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Used + # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[20]- (GPIO bank 2) 0= + # gpio2, Output, gpio_2_pin_out[20]- (GPIO bank 2) 1= can1, Output, can1_p + # hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + # 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + # Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Mas + # ter Selects) 5= Not Used 6= ua1, Output, ua1_txd- (UART transmitter seri + # al output) 7= Not Used # PSU_IOU_SLCR_MIO_PIN_72_L3_SEL 0 # Configures MIO Pin 72 peripheral interface mapping @@ -9994,21 +11205,28 @@ set psu_mio_init_data { mask_write 0XFF180120 0x000000FE 0x00000002 # Register : MIO_PIN_73 @ 0XFF180124

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[2]- (RX RGMII data) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[ + # 2]- (RX RGMII data) # PSU_IOU_SLCR_MIO_PIN_73_L0_SEL 1 - # Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_ - # ata[5]- (ULPI data bus) + # Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + # ta[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[5]- (ULPI data + # bus) # PSU_IOU_SLCR_MIO_PIN_73_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8 - # bit Data bus) 2= sd1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_out[2]- (8-bit Data bus) 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- + # (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8-bit Data bus) 2= s + # d1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + # t[2]- (8-bit Data bus) 3= Not Used # PSU_IOU_SLCR_MIO_PIN_73_L2_SEL 0 - # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[21]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[21]- (GPIO bank 2) 1= c - # n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - # l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1 - # Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= Not Used 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used + # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[21]- (GPIO bank 2) 0= + # gpio2, Output, gpio_2_pin_out[21]- (GPIO bank 2) 1= can1, Input, can1_ph + # y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + # c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + # (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master + # Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= Not + # Used 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used # PSU_IOU_SLCR_MIO_PIN_73_L3_SEL 0 # Configures MIO Pin 73 peripheral interface mapping @@ -10016,21 +11234,28 @@ set psu_mio_init_data { mask_write 0XFF180124 0x000000FE 0x00000002 # Register : MIO_PIN_74 @ 0XFF180128

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[3]- (RX RGMII data) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[ + # 3]- (RX RGMII data) # PSU_IOU_SLCR_MIO_PIN_74_L0_SEL 1 - # Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[6]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_ - # ata[6]- (ULPI data bus) + # Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + # ta[6]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[6]- (ULPI data + # bus) # PSU_IOU_SLCR_MIO_PIN_74_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8 - # bit Data bus) 2= sd1, Input, sd1_data_in[3]- (8-bit Data bus) = sd1, Output, sdio1_data_out[3]- (8-bit Data bus) 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- + # (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8-bit Data bus) 2= s + # d1, Input, sd1_data_in[3]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + # t[3]- (8-bit Data bus) 3= Not Used # PSU_IOU_SLCR_MIO_PIN_74_L2_SEL 0 - # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[22]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[22]- (GPIO bank 2) 1= c - # n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - # l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_ - # o- (MISO signal) 5= Not Used 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used + # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[22]- (GPIO bank 2) 0= + # gpio2, Output, gpio_2_pin_out[22]- (GPIO bank 2) 1= can0, Input, can0_ph + # y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + # c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + # atch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= sp + # i1, Output, spi1_so- (MISO signal) 5= Not Used 6= ua0, Input, ua0_rxd- ( + # UART receiver serial input) 7= Not Used # PSU_IOU_SLCR_MIO_PIN_74_L3_SEL 0 # Configures MIO Pin 74 peripheral interface mapping @@ -10038,21 +11263,27 @@ set psu_mio_init_data { mask_write 0XFF180128 0x000000FE 0x00000002 # Register : MIO_PIN_75 @ 0XFF18012C

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_ctl- (RX RGMII control ) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_c + # tl- (RX RGMII control ) # PSU_IOU_SLCR_MIO_PIN_75_L0_SEL 1 - # Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[7]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_ - # ata[7]- (ULPI data bus) + # Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + # ta[7]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[7]- (ULPI data + # bus) # PSU_IOU_SLCR_MIO_PIN_75_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= sd1, Input, sd1_cmd_in- (Comma - # d Indicator) = sd1, Output, sdio1_cmd_out- (Command Indicator) 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- + # (SD card bus power) 2= sd1, Input, sd1_cmd_in- (Command Indicator) = sd1 + # , Output, sdio1_cmd_out- (Command Indicator) 3= Not Used # PSU_IOU_SLCR_MIO_PIN_75_L2_SEL 0 - # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[23]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[23]- (GPIO bank 2) 1= c - # n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - # al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s - # i1_si- (MOSI signal) 5= Not Used 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used + # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[23]- (GPIO bank 2) 0= + # gpio2, Output, gpio_2_pin_out[23]- (GPIO bank 2) 1= can0, Output, can0_p + # hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + # 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + # (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) + # 4= spi1, Input, spi1_si- (MOSI signal) 5= Not Used 6= ua0, Output, ua0_t + # xd- (UART transmitter serial output) 7= Not Used # PSU_IOU_SLCR_MIO_PIN_75_L3_SEL 0 # Configures MIO Pin 75 peripheral interface mapping @@ -10066,14 +11297,17 @@ set psu_mio_init_data { # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used # PSU_IOU_SLCR_MIO_PIN_76_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= sd1, Output, sdio - # _clk_out- (SDSDIO clock) 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD ca + # rd write protect from connector) 2= sd1, Output, sdio1_clk_out- (SDSDIO + # clock) 3= Not Used # PSU_IOU_SLCR_MIO_PIN_76_L2_SEL 0 - # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[24]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[24]- (GPIO bank 2) 1= c - # n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - # al) 3= mdio0, Output, gem0_mdc- (MDIO Clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= mdio2, Output, gem2_mdc- (MDIO Clock - # 6= mdio3, Output, gem3_mdc- (MDIO Clock) 7= Not Used + # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[24]- (GPIO bank 2) 0= + # gpio2, Output, gpio_2_pin_out[24]- (GPIO bank 2) 1= can1, Output, can1_p + # hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + # 2c1, Output, i2c1_scl_out- (SCL signal) 3= mdio0, Output, gem0_mdc- (MDI + # O Clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= mdio2, Output, gem2 + # _mdc- (MDIO Clock) 6= mdio3, Output, gem3_mdc- (MDIO Clock) 7= Not Used # PSU_IOU_SLCR_MIO_PIN_76_L3_SEL 6 # Configures MIO Pin 76 peripheral interface mapping @@ -10087,14 +11321,19 @@ set psu_mio_init_data { # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used # PSU_IOU_SLCR_MIO_PIN_77_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Input, sdio1_cd_n- (SD card detect from connector) 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Input, sdio + # 1_cd_n- (SD card detect from connector) 3= Not Used # PSU_IOU_SLCR_MIO_PIN_77_L2_SEL 0 - # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[25]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[25]- (GPIO bank 2) 1= c - # n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - # l) 3= mdio0, Input, gem0_mdio_in- (MDIO Data) 3= mdio0, Output, gem0_mdio_out- (MDIO Data) 4= mdio1, Input, gem1_mdio_in- (MD - # O Data) 4= mdio1, Output, gem1_mdio_out- (MDIO Data) 5= mdio2, Input, gem2_mdio_in- (MDIO Data) 5= mdio2, Output, gem2_mdio_o - # t- (MDIO Data) 6= mdio3, Input, gem3_mdio_in- (MDIO Data) 6= mdio3, Output, gem3_mdio_out- (MDIO Data) 7= Not Used + # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[25]- (GPIO bank 2) 0= + # gpio2, Output, gpio_2_pin_out[25]- (GPIO bank 2) 1= can1, Input, can1_ph + # y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + # c1, Output, i2c1_sda_out- (SDA signal) 3= mdio0, Input, gem0_mdio_in- (M + # DIO Data) 3= mdio0, Output, gem0_mdio_out- (MDIO Data) 4= mdio1, Input, + # gem1_mdio_in- (MDIO Data) 4= mdio1, Output, gem1_mdio_out- (MDIO Data) 5 + # = mdio2, Input, gem2_mdio_in- (MDIO Data) 5= mdio2, Output, gem2_mdio_ou + # t- (MDIO Data) 6= mdio3, Input, gem3_mdio_in- (MDIO Data) 6= mdio3, Outp + # ut, gem3_mdio_out- (MDIO Data) 7= Not Used # PSU_IOU_SLCR_MIO_PIN_77_L3_SEL 6 # Configures MIO Pin 77 peripheral interface mapping @@ -10678,7 +11917,8 @@ set psu_mio_init_data { # Each bit applies to a single IO. Bit 0 for MIO[0]. # PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25 1 - # When mio_bank0_pull_enable is set, this selects pull up or pull down for MIO Bank 0 - control MIO[25:0] + # When mio_bank0_pull_enable is set, this selects pull up or pull down for + # MIO Bank 0 - control MIO[25:0] #(OFFSET, MASK, VALUE) (0XFF180144, 0x03FFFFFFU ,0x03FFFFFFU) */ mask_write 0XFF180144 0x03FFFFFF 0x03FFFFFF # Register : bank0_ctrl5 @ 0XFF180148

@@ -10761,7 +12001,8 @@ set psu_mio_init_data { # Each bit applies to a single IO. Bit 0 for MIO[0]. # PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25 1 - # When set, this enables mio_bank0_pullupdown to selects pull up or pull down for MIO Bank 0 - control MIO[25:0] + # When set, this enables mio_bank0_pullupdown to selects pull up or pull d + # own for MIO Bank 0 - control MIO[25:0] #(OFFSET, MASK, VALUE) (0XFF180148, 0x03FFFFFFU ,0x03FFFFFFU) */ mask_write 0XFF180148 0x03FFFFFF 0x03FFFFFF # Register : bank0_ctrl6 @ 0XFF18014C

@@ -11176,7 +12417,8 @@ set psu_mio_init_data { # Each bit applies to a single IO. Bit 0 for MIO[26]. # PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25 1 - # When mio_bank1_pull_enable is set, this selects pull up or pull down for MIO Bank 1 - control MIO[51:26] + # When mio_bank1_pull_enable is set, this selects pull up or pull down for + # MIO Bank 1 - control MIO[51:26] #(OFFSET, MASK, VALUE) (0XFF180160, 0x03FFFFFFU ,0x03FFFFFFU) */ mask_write 0XFF180160 0x03FFFFFF 0x03FFFFFF # Register : bank1_ctrl5 @ 0XFF180164

@@ -11259,7 +12501,8 @@ set psu_mio_init_data { # Each bit applies to a single IO. Bit 0 for MIO[26]. # PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25 1 - # When set, this enables mio_bank1_pullupdown to selects pull up or pull down for MIO Bank 1 - control MIO[51:26] + # When set, this enables mio_bank1_pullupdown to selects pull up or pull d + # own for MIO Bank 1 - control MIO[51:26] #(OFFSET, MASK, VALUE) (0XFF180164, 0x03FFFFFFU ,0x03FFFFFFU) */ mask_write 0XFF180164 0x03FFFFFF 0x03FFFFFF # Register : bank1_ctrl6 @ 0XFF180168

@@ -11674,7 +12917,8 @@ set psu_mio_init_data { # Each bit applies to a single IO. Bit 0 for MIO[52]. # PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25 1 - # When mio_bank2_pull_enable is set, this selects pull up or pull down for MIO Bank 2 - control MIO[77:52] + # When mio_bank2_pull_enable is set, this selects pull up or pull down for + # MIO Bank 2 - control MIO[77:52] #(OFFSET, MASK, VALUE) (0XFF18017C, 0x03FFFFFFU ,0x03FFFFFFU) */ mask_write 0XFF18017C 0x03FFFFFF 0x03FFFFFF # Register : bank2_ctrl5 @ 0XFF180180

@@ -11757,7 +13001,8 @@ set psu_mio_init_data { # Each bit applies to a single IO. Bit 0 for MIO[52]. # PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25 1 - # When set, this enables mio_bank2_pullupdown to selects pull up or pull down for MIO Bank 2 - control MIO[77:52] + # When set, this enables mio_bank2_pullupdown to selects pull up or pull d + # own for MIO Bank 2 - control MIO[77:52] #(OFFSET, MASK, VALUE) (0XFF180180, 0x03FFFFFFU ,0x03FFFFFFU) */ mask_write 0XFF180180 0x03FFFFFF 0x03FFFFFF # Register : bank2_ctrl6 @ 0XFF180184

@@ -11846,20 +13091,24 @@ set psu_mio_init_data { # : LOOPBACK # Register : MIO_LOOPBACK @ 0XFF180200

- # I2C Loopback Control. 0 = Connect I2C inputs according to MIO mapping. 1 = Loop I2C 0 outputs to I2C 1 inputs, and I2C 1 outp - # ts to I2C 0 inputs. + # I2C Loopback Control. 0 = Connect I2C inputs according to MIO mapping. 1 + # = Loop I2C 0 outputs to I2C 1 inputs, and I2C 1 outputs to I2C 0 inputs + # . # PSU_IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1 0 - # CAN Loopback Control. 0 = Connect CAN inputs according to MIO mapping. 1 = Loop CAN 0 Tx to CAN 1 Rx, and CAN 1 Tx to CAN 0 R - # . + # CAN Loopback Control. 0 = Connect CAN inputs according to MIO mapping. 1 + # = Loop CAN 0 Tx to CAN 1 Rx, and CAN 1 Tx to CAN 0 Rx. # PSU_IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1 0 - # UART Loopback Control. 0 = Connect UART inputs according to MIO mapping. 1 = Loop UART 0 outputs to UART 1 inputs, and UART 1 - # outputs to UART 0 inputs. RXD/TXD cross-connected. RTS/CTS cross-connected. DSR, DTR, DCD and RI not used. + # UART Loopback Control. 0 = Connect UART inputs according to MIO mapping. + # 1 = Loop UART 0 outputs to UART 1 inputs, and UART 1 outputs to UART 0 + # inputs. RXD/TXD cross-connected. RTS/CTS cross-connected. DSR, DTR, DCD + # and RI not used. # PSU_IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1 0 - # SPI Loopback Control. 0 = Connect SPI inputs according to MIO mapping. 1 = Loop SPI 0 outputs to SPI 1 inputs, and SPI 1 outp - # ts to SPI 0 inputs. The other SPI core will appear on the LS Slave Select. + # SPI Loopback Control. 0 = Connect SPI inputs according to MIO mapping. 1 + # = Loop SPI 0 outputs to SPI 1 inputs, and SPI 1 outputs to SPI 0 inputs + # . The other SPI core will appear on the LS Slave Select. # PSU_IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1 0 # Loopback function within MIO @@ -11868,59 +13117,7 @@ set psu_mio_init_data { } set psu_peripherals_init_data { - # : RESET BLOCKS - # : TIMESTAMP - # Register : RST_LPD_IOU2 @ 0XFF5E0238

- - # Block level reset - # PSU_CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET 0 - - # Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset. - #(OFFSET, MASK, VALUE) (0XFF5E0238, 0x00100000U ,0x00000000U) */ - mask_write 0XFF5E0238 0x00100000 0x00000000 - # : ENET - # Register : RST_LPD_IOU0 @ 0XFF5E0230

- - # GEM 3 reset - # PSU_CRL_APB_RST_LPD_IOU0_GEM3_RESET 0 - - # Software controlled reset for the GEMs - #(OFFSET, MASK, VALUE) (0XFF5E0230, 0x00000008U ,0x00000000U) */ - mask_write 0XFF5E0230 0x00000008 0x00000000 - # : QSPI - # Register : RST_LPD_IOU2 @ 0XFF5E0238

- - # Block level reset - # PSU_CRL_APB_RST_LPD_IOU2_QSPI_RESET 0 - - # Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset. - #(OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000001U ,0x00000000U) */ - mask_write 0XFF5E0238 0x00000001 0x00000000 - # : QSPI TAP DELAY - # Register : IOU_TAPDLY_BYPASS @ 0XFF180390

- - # 0: Do not by pass the tap delays on the Rx clock signal of LQSPI 1: Bypass the Tap delay on the Rx clock signal of LQSPI - # PSU_IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX 1 - - # IOU tap delay bypass for the LQSPI and NAND controllers - #(OFFSET, MASK, VALUE) (0XFF180390, 0x00000004U ,0x00000004U) */ - mask_write 0XFF180390 0x00000004 0x00000004 - # : NAND - # : USB - # Register : RST_LPD_TOP @ 0XFF5E023C

- - # USB 0 reset for control registers - # PSU_CRL_APB_RST_LPD_TOP_USB0_APB_RESET 0 - - # USB 0 sleep circuit reset - # PSU_CRL_APB_RST_LPD_TOP_USB0_HIBERRESET 0 - - # USB 0 reset - # PSU_CRL_APB_RST_LPD_TOP_USB0_CORERESET 0 - - # Software control register for the LPD block. - #(OFFSET, MASK, VALUE) (0XFF5E023C, 0x00000540U ,0x00000000U) */ - mask_write 0XFF5E023C 0x00000540 0x00000000 + # : COHERENCY # : FPD RESET # Register : RST_FPD_TOP @ 0XFD1A0100

@@ -11960,13 +13157,123 @@ set psu_peripherals_init_data { # FPD Block level software controlled reset #(OFFSET, MASK, VALUE) (0XFD1A0100, 0x000F807EU ,0x00000000U) */ mask_write 0XFD1A0100 0x000F807E 0x00000000 + # : RESET BLOCKS + # : TIMESTAMP + # Register : RST_LPD_IOU2 @ 0XFF5E0238

+ + # Block level reset + # PSU_CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET 0 + + # Block level reset + # PSU_CRL_APB_RST_LPD_IOU2_IOU_CC_RESET 0 + + # Block level reset + # PSU_CRL_APB_RST_LPD_IOU2_ADMA_RESET 0 + + # Software control register for the IOU block. Each bit will cause a singl + # erperipheral or part of the peripheral to be reset. + #(OFFSET, MASK, VALUE) (0XFF5E0238, 0x001A0000U ,0x00000000U) */ + mask_write 0XFF5E0238 0x001A0000 0x00000000 + # Register : RST_LPD_TOP @ 0XFF5E023C

+ + # Reset entire full power domain. + # PSU_CRL_APB_RST_LPD_TOP_FPD_RESET 0 + + # LPD SWDT + # PSU_CRL_APB_RST_LPD_TOP_LPD_SWDT_RESET 0 + + # Sysmonitor reset + # PSU_CRL_APB_RST_LPD_TOP_SYSMON_RESET 0 + + # Real Time Clock reset + # PSU_CRL_APB_RST_LPD_TOP_RTC_RESET 0 + + # APM reset + # PSU_CRL_APB_RST_LPD_TOP_APM_RESET 0 + + # IPI reset + # PSU_CRL_APB_RST_LPD_TOP_IPI_RESET 0 + + # reset entire RPU power island + # PSU_CRL_APB_RST_LPD_TOP_RPU_PGE_RESET 0 + + # reset ocm + # PSU_CRL_APB_RST_LPD_TOP_OCM_RESET 0 + + # Software control register for the LPD block. + #(OFFSET, MASK, VALUE) (0XFF5E023C, 0x0093C018U ,0x00000000U) */ + mask_write 0XFF5E023C 0x0093C018 0x00000000 + # : ENET + # Register : RST_LPD_IOU0 @ 0XFF5E0230

+ + # GEM 3 reset + # PSU_CRL_APB_RST_LPD_IOU0_GEM3_RESET 0 + + # Software controlled reset for the GEMs + #(OFFSET, MASK, VALUE) (0XFF5E0230, 0x00000008U ,0x00000000U) */ + mask_write 0XFF5E0230 0x00000008 0x00000000 + # : QSPI + # Register : RST_LPD_IOU2 @ 0XFF5E0238

+ + # Block level reset + # PSU_CRL_APB_RST_LPD_IOU2_QSPI_RESET 0 + + # Software control register for the IOU block. Each bit will cause a singl + # erperipheral or part of the peripheral to be reset. + #(OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000001U ,0x00000000U) */ + mask_write 0XFF5E0238 0x00000001 0x00000000 + # : QSPI TAP DELAY + # Register : IOU_TAPDLY_BYPASS @ 0XFF180390

+ + # 0: Do not by pass the tap delays on the Rx clock signal of LQSPI 1: Bypa + # ss the Tap delay on the Rx clock signal of LQSPI + # PSU_IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX 1 + + # IOU tap delay bypass for the LQSPI and NAND controllers + #(OFFSET, MASK, VALUE) (0XFF180390, 0x00000004U ,0x00000004U) */ + mask_write 0XFF180390 0x00000004 0x00000004 + # : NAND + # : USB + # Register : RST_LPD_TOP @ 0XFF5E023C

+ + # USB 0 reset for control registers + # PSU_CRL_APB_RST_LPD_TOP_USB0_APB_RESET 0 + + # USB 0 sleep circuit reset + # PSU_CRL_APB_RST_LPD_TOP_USB0_HIBERRESET 0 + + # USB 0 reset + # PSU_CRL_APB_RST_LPD_TOP_USB0_CORERESET 0 + + # Software control register for the LPD block. + #(OFFSET, MASK, VALUE) (0XFF5E023C, 0x00000540U ,0x00000000U) */ + mask_write 0XFF5E023C 0x00000540 0x00000000 + # : USB0 PIPE POWER PRESENT + # Register : fpd_power_prsnt @ 0XFF9D0080

+ + # This bit is used to choose between PIPE power present and 1'b1 + # PSU_USB3_0_FPD_POWER_PRSNT_OPTION 0X1 + + # fpd_power_prsnt + #(OFFSET, MASK, VALUE) (0XFF9D0080, 0x00000001U ,0x00000001U) */ + mask_write 0XFF9D0080 0x00000001 0x00000001 + # Register : fpd_pipe_clk @ 0XFF9D007C

+ + # This bit is used to choose between PIPE clock coming from SerDes and the + # suspend clk + # PSU_USB3_0_FPD_PIPE_CLK_OPTION 0x0 + + # fpd_pipe_clk + #(OFFSET, MASK, VALUE) (0XFF9D007C, 0x00000001U ,0x00000000U) */ + mask_write 0XFF9D007C 0x00000001 0x00000000 # : SD # Register : RST_LPD_IOU2 @ 0XFF5E0238

# Block level reset # PSU_CRL_APB_RST_LPD_IOU2_SDIO1_RESET 0 - # Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset. + # Software control register for the IOU block. Each bit will cause a singl + # erperipheral or part of the peripheral to be reset. #(OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000040U ,0x00000000U) */ mask_write 0XFF5E0238 0x00000040 0x00000000 # Register : CTRL_REG_SD @ 0XFF180310

@@ -11979,12 +13286,12 @@ set psu_peripherals_init_data { mask_write 0XFF180310 0x00008000 0x00000000 # Register : SD_CONFIG_REG2 @ 0XFF180320

- # Should be set based on the final product usage 00 - Removable SCard Slot 01 - Embedded Slot for One Device 10 - Shared Bus Sl - # t 11 - Reserved + # Should be set based on the final product usage 00 - Removable SCard Slot + # 01 - Embedded Slot for One Device 10 - Shared Bus Slot 11 - Reserved # PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE 0 # 1.8V Support 1: 1.8V supported 0: 1.8V not supported support - # PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V 0 + # PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V 1 # 3.0V Support 1: 3.0V supported 0: 3.0V not supported support # PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V 0 @@ -11993,23 +13300,36 @@ set psu_peripherals_init_data { # PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V 1 # SD Config Register 2 - #(OFFSET, MASK, VALUE) (0XFF180320, 0x33800000U ,0x00800000U) */ - mask_write 0XFF180320 0x33800000 0x00800000 + #(OFFSET, MASK, VALUE) (0XFF180320, 0x33800000U ,0x02800000U) */ + mask_write 0XFF180320 0x33800000 0x02800000 # : SD1 BASE CLOCK # Register : SD_CONFIG_REG1 @ 0XFF18031C

# Base Clock Frequency for SD Clock. This is the frequency of the xin_clk. - # PSU_IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK 0xc7 + # PSU_IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK 0xc8 + + # Configures the Number of Taps (Phases) of the rxclk_in that is supported + # . + # PSU_IOU_SLCR_SD_CONFIG_REG1_SD1_TUNIGCOUNT 0x28 # SD Config Register 1 - #(OFFSET, MASK, VALUE) (0XFF18031C, 0x7F800000U ,0x63800000U) */ - mask_write 0XFF18031C 0x7F800000 0x63800000 + #(OFFSET, MASK, VALUE) (0XFF18031C, 0x7FFE0000U ,0x64500000U) */ + mask_write 0XFF18031C 0x7FFE0000 0x64500000 + # Register : SD_DLL_CTRL @ 0XFF180358

+ + # Reserved. + # PSU_IOU_SLCR_SD_DLL_CTRL_RESERVED 1 + + # SDIO status register + #(OFFSET, MASK, VALUE) (0XFF180358, 0x00000008U ,0x00000008U) */ + mask_write 0XFF180358 0x00000008 0x00000008 # : SD1 RETUNER # Register : SD_CONFIG_REG3 @ 0XFF180324

- # This is the Timer Count for Re-Tuning Timer for Re-Tuning Mode 1 to 3. Setting to 4'b0 disables Re-Tuning Timer. 0h - Get inf - # rmation via other source 1h = 1 seconds 2h = 2 seconds 3h = 4 seconds 4h = 8 seconds -- n = 2(n-1) seconds -- Bh = 1024 secon - # s Fh - Ch = Reserved + # This is the Timer Count for Re-Tuning Timer for Re-Tuning Mode 1 to 3. S + # etting to 4'b0 disables Re-Tuning Timer. 0h - Get information via other + # source 1h = 1 seconds 2h = 2 seconds 3h = 4 seconds 4h = 8 seconds -- n + # = 2(n-1) seconds -- Bh = 1024 seconds Fh - Ch = Reserved # PSU_IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR 0X0 # SD Config Register 3 @@ -12021,7 +13341,8 @@ set psu_peripherals_init_data { # Block level reset # PSU_CRL_APB_RST_LPD_IOU2_CAN1_RESET 0 - # Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset. + # Software control register for the IOU block. Each bit will cause a singl + # erperipheral or part of the peripheral to be reset. #(OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000100U ,0x00000000U) */ mask_write 0XFF5E0238 0x00000100 0x00000000 # : I2C @@ -12033,7 +13354,8 @@ set psu_peripherals_init_data { # Block level reset # PSU_CRL_APB_RST_LPD_IOU2_I2C1_RESET 0 - # Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset. + # Software control register for the IOU block. Each bit will cause a singl + # erperipheral or part of the peripheral to be reset. #(OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000600U ,0x00000000U) */ mask_write 0XFF5E0238 0x00000600 0x00000000 # : SWDT @@ -12042,7 +13364,8 @@ set psu_peripherals_init_data { # Block level reset # PSU_CRL_APB_RST_LPD_IOU2_SWDT_RESET 0 - # Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset. + # Software control register for the IOU block. Each bit will cause a singl + # erperipheral or part of the peripheral to be reset. #(OFFSET, MASK, VALUE) (0XFF5E0238, 0x00008000U ,0x00000000U) */ mask_write 0XFF5E0238 0x00008000 0x00000000 # : SPI @@ -12061,7 +13384,8 @@ set psu_peripherals_init_data { # Block level reset # PSU_CRL_APB_RST_LPD_IOU2_TTC3_RESET 0 - # Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset. + # Software control register for the IOU block. Each bit will cause a singl + # erperipheral or part of the peripheral to be reset. #(OFFSET, MASK, VALUE) (0XFF5E0238, 0x00007800U ,0x00000000U) */ mask_write 0XFF5E0238 0x00007800 0x00000000 # : UART @@ -12073,7 +13397,8 @@ set psu_peripherals_init_data { # Block level reset # PSU_CRL_APB_RST_LPD_IOU2_UART1_RESET 0 - # Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset. + # Software control register for the IOU block. Each bit will cause a singl + # erperipheral or part of the peripheral to be reset. #(OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000006U ,0x00000000U) */ mask_write 0XFF5E0238 0x00000006 0x00000000 # : UART BAUD RATE @@ -12087,7 +13412,8 @@ set psu_peripherals_init_data { mask_write 0XFF000034 0x000000FF 0x00000005 # Register : Baud_rate_gen_reg0 @ 0XFF000018

- # Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample + # Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor + # bypass (baud_sample = sel_clk) 2 - 65535: baud_sample # PSU_UART0_BAUD_RATE_GEN_REG0_CD 0x8f # Baud Rate Generator Register. @@ -12095,36 +13421,43 @@ set psu_peripherals_init_data { mask_write 0XFF000018 0x0000FFFF 0x0000008F # Register : Control_reg0 @ 0XFF000000

- # Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a - # high level during 12 bit periods. It can be set regardless of the value of STTBRK. + # Stop transmitter break: 0: no affect 1: stop transmission of the break a + # fter a minimum of one character length and transmit a high level during + # 12 bit periods. It can be set regardless of the value of STTBRK. # PSU_UART0_CONTROL_REG0_STPBRK 0x0 - # Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the - # transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high. + # Start transmitter break: 0: no affect 1: start to transmit a break after + # the characters currently present in the FIFO and the transmit shift reg + # ister have been transmitted. It can only be set if STPBRK (Stop transmit + # ter break) is not high. # PSU_UART0_CONTROL_REG0_STTBRK 0x0 - # Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has co - # pleted. + # Restart receiver timeout counter: 1: receiver timeout counter is restart + # ed. This bit is self clearing once the restart has completed. # PSU_UART0_CONTROL_REG0_RSTTO 0x0 # Transmit disable: 0: enable transmitter 1: disable transmitter # PSU_UART0_CONTROL_REG0_TXDIS 0x0 - # Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0. + # Transmit enable: 0: disable transmitter 1: enable transmitter, provided + # the TXDIS field is set to 0. # PSU_UART0_CONTROL_REG0_TXEN 0x1 # Receive disable: 0: enable 1: disable, regardless of the value of RXEN # PSU_UART0_CONTROL_REG0_RXDIS 0x0 - # Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero. + # Receive enable: 0: disable 1: enable When set to one, the receiver logic + # is enabled, provided the RXDIS field is set to zero. # PSU_UART0_CONTROL_REG0_RXEN 0x1 - # Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded Thi - # bit is self clearing once the reset has completed. + # Software reset for Tx data path: 0: no affect 1: transmitter logic is re + # set and all pending transmitter data is discarded This bit is self clear + # ing once the reset has completed. # PSU_UART0_CONTROL_REG0_TXRES 0x1 - # Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit - # is self clearing once the reset has completed. + # Software reset for Rx data path: 0: no affect 1: receiver logic is reset + # and all pending receiver data is discarded. This bit is self clearing o + # nce the reset has completed. # PSU_UART0_CONTROL_REG0_RXRES 0x1 # UART Control Register @@ -12132,22 +13465,28 @@ set psu_peripherals_init_data { mask_write 0XFF000000 0x000001FF 0x00000017 # Register : mode_reg0 @ 0XFF000004

- # Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback + # Channel mode: Defines the mode of operation of the UART. 00: normal 01: + # automatic echo 10: local loopback 11: remote loopback # PSU_UART0_MODE_REG0_CHMODE 0x0 - # Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5 - # stop bits 10: 2 stop bits 11: reserved + # Number of stop bits: Defines the number of stop bits to detect on receiv + # e and to generate on transmit. 00: 1 stop bit 01: 1.5 stop bits 10: 2 st + # op bits 11: reserved # PSU_UART0_MODE_REG0_NBSTOP 0x0 - # Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity - # 01: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity + # Parity type select: Defines the expected parity to check on receive and + # the parity to generate on transmit. 000: even parity 001: odd parity 010 + # : forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no pari + # ty # PSU_UART0_MODE_REG0_PAR 0x4 - # Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits + # Character length select: Defines the number of bits in each character. 1 + # 1: 6 bits 10: 7 bits 0x: 8 bits # PSU_UART0_MODE_REG0_CHRL 0x0 - # Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock - # source is uart_ref_clk 1: clock source is uart_ref_clk/8 + # Clock source select: This field defines whether a pre-scalar of 8 is app + # lied to the baud rate generator input clock. 0: clock source is uart_ref + # _clk 1: clock source is uart_ref_clk/8 # PSU_UART0_MODE_REG0_CLKS 0x0 # UART Mode Register @@ -12163,7 +13502,8 @@ set psu_peripherals_init_data { mask_write 0XFF010034 0x000000FF 0x00000005 # Register : Baud_rate_gen_reg0 @ 0XFF010018

- # Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample + # Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor + # bypass (baud_sample = sel_clk) 2 - 65535: baud_sample # PSU_UART1_BAUD_RATE_GEN_REG0_CD 0x8f # Baud Rate Generator Register. @@ -12171,36 +13511,43 @@ set psu_peripherals_init_data { mask_write 0XFF010018 0x0000FFFF 0x0000008F # Register : Control_reg0 @ 0XFF010000

- # Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a - # high level during 12 bit periods. It can be set regardless of the value of STTBRK. + # Stop transmitter break: 0: no affect 1: stop transmission of the break a + # fter a minimum of one character length and transmit a high level during + # 12 bit periods. It can be set regardless of the value of STTBRK. # PSU_UART1_CONTROL_REG0_STPBRK 0x0 - # Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the - # transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high. + # Start transmitter break: 0: no affect 1: start to transmit a break after + # the characters currently present in the FIFO and the transmit shift reg + # ister have been transmitted. It can only be set if STPBRK (Stop transmit + # ter break) is not high. # PSU_UART1_CONTROL_REG0_STTBRK 0x0 - # Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has co - # pleted. + # Restart receiver timeout counter: 1: receiver timeout counter is restart + # ed. This bit is self clearing once the restart has completed. # PSU_UART1_CONTROL_REG0_RSTTO 0x0 # Transmit disable: 0: enable transmitter 1: disable transmitter # PSU_UART1_CONTROL_REG0_TXDIS 0x0 - # Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0. + # Transmit enable: 0: disable transmitter 1: enable transmitter, provided + # the TXDIS field is set to 0. # PSU_UART1_CONTROL_REG0_TXEN 0x1 # Receive disable: 0: enable 1: disable, regardless of the value of RXEN # PSU_UART1_CONTROL_REG0_RXDIS 0x0 - # Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero. + # Receive enable: 0: disable 1: enable When set to one, the receiver logic + # is enabled, provided the RXDIS field is set to zero. # PSU_UART1_CONTROL_REG0_RXEN 0x1 - # Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded Thi - # bit is self clearing once the reset has completed. + # Software reset for Tx data path: 0: no affect 1: transmitter logic is re + # set and all pending transmitter data is discarded This bit is self clear + # ing once the reset has completed. # PSU_UART1_CONTROL_REG0_TXRES 0x1 - # Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit - # is self clearing once the reset has completed. + # Software reset for Rx data path: 0: no affect 1: receiver logic is reset + # and all pending receiver data is discarded. This bit is self clearing o + # nce the reset has completed. # PSU_UART1_CONTROL_REG0_RXRES 0x1 # UART Control Register @@ -12208,28 +13555,43 @@ set psu_peripherals_init_data { mask_write 0XFF010000 0x000001FF 0x00000017 # Register : mode_reg0 @ 0XFF010004

- # Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback + # Channel mode: Defines the mode of operation of the UART. 00: normal 01: + # automatic echo 10: local loopback 11: remote loopback # PSU_UART1_MODE_REG0_CHMODE 0x0 - # Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5 - # stop bits 10: 2 stop bits 11: reserved + # Number of stop bits: Defines the number of stop bits to detect on receiv + # e and to generate on transmit. 00: 1 stop bit 01: 1.5 stop bits 10: 2 st + # op bits 11: reserved # PSU_UART1_MODE_REG0_NBSTOP 0x0 - # Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity - # 01: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity + # Parity type select: Defines the expected parity to check on receive and + # the parity to generate on transmit. 000: even parity 001: odd parity 010 + # : forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no pari + # ty # PSU_UART1_MODE_REG0_PAR 0x4 - # Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits + # Character length select: Defines the number of bits in each character. 1 + # 1: 6 bits 10: 7 bits 0x: 8 bits # PSU_UART1_MODE_REG0_CHRL 0x0 - # Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock - # source is uart_ref_clk 1: clock source is uart_ref_clk/8 + # Clock source select: This field defines whether a pre-scalar of 8 is app + # lied to the baud rate generator input clock. 0: clock source is uart_ref + # _clk 1: clock source is uart_ref_clk/8 # PSU_UART1_MODE_REG0_CLKS 0x0 # UART Mode Register #(OFFSET, MASK, VALUE) (0XFF010004, 0x000003FFU ,0x00000020U) */ mask_write 0XFF010004 0x000003FF 0x00000020 # : GPIO + # Register : RST_LPD_IOU2 @ 0XFF5E0238

+ + # Block level reset + # PSU_CRL_APB_RST_LPD_IOU2_GPIO_RESET 0 + + # Software control register for the IOU block. Each bit will cause a singl + # erperipheral or part of the peripheral to be reset. + #(OFFSET, MASK, VALUE) (0XFF5E0238, 0x00040000U ,0x00000000U) */ + mask_write 0XFF5E0238 0x00040000 0x00000000 # : ADMA TZ # Register : slcr_adma @ 0XFF4B0024

@@ -12286,7 +13648,6 @@ set psu_peripherals_init_data { #(OFFSET, MASK, VALUE) (0XFFCA5000, 0x00001FFFU ,0x00000000U) */ mask_write 0XFFCA5000 0x00001FFF 0x00000000 # : CSU TAMPER RESPONSE - # : AFIFM INTERFACE WIDTH # : CPU QOS DEFAULT # Register : ACE_CTRL @ 0XFD5C0060

@@ -12302,10 +13663,12 @@ set psu_peripherals_init_data { # : ENABLES RTC SWITCH TO BATTERY WHEN VCC_PSAUX IS NOT AVAILABLE # Register : CONTROL @ 0XFFA60040

- # Enables the RTC. By writing a 0 to this bit, RTC will be powered off and the only module that potentially draws current from - # he battery will be BBRAM. The value read through this bit does not necessarily reflect whether RTC is enabled or not. It is e - # pected that RTC is enabled every time it is being configured. If RTC is not used in the design, FSBL will disable it by writi - # g a 0 to this bit. + # Enables the RTC. By writing a 0 to this bit, RTC will be powered off and + # the only module that potentially draws current from the battery will be + # BBRAM. The value read through this bit does not necessarily reflect whe + # ther RTC is enabled or not. It is expected that RTC is enabled every tim + # e it is being configured. If RTC is not used in the design, FSBL will di + # sable it by writing a 0 to this bit. # PSU_RTC_CONTROL_BATTERY_DISABLE 0X1 # This register controls various functionalities within the RTC @@ -12314,22 +13677,89 @@ set psu_peripherals_init_data { # : TIMESTAMP COUNTER # Register : base_frequency_ID_register @ 0XFF260020

- # Frequency in number of ticks per second. Valid range from 10 MHz to 100 MHz. - # PSU_IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ 0x5f5e100 + # Frequency in number of ticks per second. Valid range from 10 MHz to 100 + # MHz. + # PSU_IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ 0x5f5b9f0 - # Program this register to match the clock frequency of the timestamp generator, in ticks per second. For example, for a 50 MHz - # clock, program 0x02FAF080. This register is not accessible to the read-only programming interface. - #(OFFSET, MASK, VALUE) (0XFF260020, 0xFFFFFFFFU ,0x05F5E100U) */ - mask_write 0XFF260020 0xFFFFFFFF 0x05F5E100 + # Program this register to match the clock frequency of the timestamp gene + # rator, in ticks per second. For example, for a 50 MHz clock, program 0x0 + # 2FAF080. This register is not accessible to the read-only programming in + # terface. + #(OFFSET, MASK, VALUE) (0XFF260020, 0xFFFFFFFFU ,0x05F5B9F0U) */ + mask_write 0XFF260020 0xFFFFFFFF 0x05F5B9F0 # Register : counter_control_register @ 0XFF260000

- # Enable 0: The counter is disabled and not incrementing. 1: The counter is enabled and is incrementing. + # Enable 0: The counter is disabled and not incrementing. 1: The counter i + # s enabled and is incrementing. # PSU_IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN 0x1 - # Controls the counter increments. This register is not accessible to the read-only programming interface. + # Controls the counter increments. This register is not accessible to the + # read-only programming interface. #(OFFSET, MASK, VALUE) (0XFF260000, 0x00000001U ,0x00000001U) */ mask_write 0XFF260000 0x00000001 0x00000001 # : TTC SRC SELECT + # : PCIE GPIO RESET + # : PCIE RESET + # : DIR MODE BANK 0 + # : DIR MODE BANK 1 + # Register : DIRM_1 @ 0XFF0A0244

+ + # Operation is the same as DIRM_0[DIRECTION_0] + # PSU_GPIO_DIRM_1_DIRECTION_1 0x20 + + # Direction mode (GPIO Bank1, MIO) + #(OFFSET, MASK, VALUE) (0XFF0A0244, 0x03FFFFFFU ,0x00000020U) */ + mask_write 0XFF0A0244 0x03FFFFFF 0x00000020 + # : DIR MODE BANK 2 + # : OUTPUT ENABLE BANK 0 + # : OUTPUT ENABLE BANK 1 + # Register : OEN_1 @ 0XFF0A0248

+ + # Operation is the same as OEN_0[OP_ENABLE_0] + # PSU_GPIO_OEN_1_OP_ENABLE_1 0x20 + + # Output enable (GPIO Bank1, MIO) + #(OFFSET, MASK, VALUE) (0XFF0A0248, 0x03FFFFFFU ,0x00000020U) */ + mask_write 0XFF0A0248 0x03FFFFFF 0x00000020 + # : OUTPUT ENABLE BANK 2 + # : MASK_DATA_0_LSW LOW BANK [15:0] + # : MASK_DATA_0_MSW LOW BANK [25:16] + # : MASK_DATA_1_LSW LOW BANK [41:26] + # Register : MASK_DATA_1_LSW @ 0XFF0A0008

+ + # Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW] + # PSU_GPIO_MASK_DATA_1_LSW_MASK_1_LSW 0xffdf + + # Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW] + # PSU_GPIO_MASK_DATA_1_LSW_DATA_1_LSW 0x20 + + # Maskable Output Data (GPIO Bank1, MIO, Lower 16bits) + #(OFFSET, MASK, VALUE) (0XFF0A0008, 0xFFFFFFFFU ,0xFFDF0020U) */ + mask_write 0XFF0A0008 0xFFFFFFFF 0xFFDF0020 + # : MASK_DATA_1_MSW HIGH BANK [51:42] + # : MASK_DATA_1_LSW HIGH BANK [67:52] + # : MASK_DATA_1_LSW HIGH BANK [77:68] + # : ADD 1 MS DELAY + mask_delay 0x00000000 1 + # : MASK_DATA_0_LSW LOW BANK [15:0] + # : MASK_DATA_0_MSW LOW BANK [25:16] + # : MASK_DATA_1_LSW LOW BANK [41:26] + # Register : MASK_DATA_1_LSW @ 0XFF0A0008

+ + # Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW] + # PSU_GPIO_MASK_DATA_1_LSW_MASK_1_LSW 0xffdf + + # Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW] + # PSU_GPIO_MASK_DATA_1_LSW_DATA_1_LSW 0x0 + + # Maskable Output Data (GPIO Bank1, MIO, Lower 16bits) + #(OFFSET, MASK, VALUE) (0XFF0A0008, 0xFFFFFFFFU ,0xFFDF0000U) */ + mask_write 0XFF0A0008 0xFFFFFFFF 0xFFDF0000 + # : MASK_DATA_1_MSW HIGH BANK [51:42] + # : MASK_DATA_1_LSW HIGH BANK [67:52] + # : MASK_DATA_1_LSW HIGH BANK [77:68] + # : ADD 5 MS DELAY + mask_delay 0x00000000 5 } set psu_post_config_data { @@ -12342,72 +13772,695 @@ set psu_peripherals_powerdwn_data { } set psu_lpd_xppu_data { - # : XPPU INTERRUPT ENABLE - # Register : IEN @ 0XFF980018

- - # See Interuppt Status Register for details - # PSU_LPD_XPPU_CFG_IEN_APER_PARITY 0X1 - - # See Interuppt Status Register for details - # PSU_LPD_XPPU_CFG_IEN_APER_TZ 0X1 - - # See Interuppt Status Register for details - # PSU_LPD_XPPU_CFG_IEN_APER_PERM 0X1 - - # See Interuppt Status Register for details - # PSU_LPD_XPPU_CFG_IEN_MID_PARITY 0X1 - - # See Interuppt Status Register for details - # PSU_LPD_XPPU_CFG_IEN_MID_RO 0X1 - - # See Interuppt Status Register for details - # PSU_LPD_XPPU_CFG_IEN_MID_MISS 0X1 - - # See Interuppt Status Register for details - # PSU_LPD_XPPU_CFG_IEN_INV_APB 0X1 - - # Interrupt Enable Register - #(OFFSET, MASK, VALUE) (0XFF980018, 0x000000EFU ,0x000000EFU) */ - mask_write 0XFF980018 0x000000EF 0x000000EF + # : MASTER ID LIST + # : APERTURE PERMISIION LIST + # : APERTURE NAME: UART0, START ADDRESS: FF000000, END ADDRESS: FF00FFFF + # : APERTURE NAME: UART1, START ADDRESS: FF010000, END ADDRESS: FF01FFFF + # : APERTURE NAME: I2C0, START ADDRESS: FF020000, END ADDRESS: FF02FFFF + # : APERTURE NAME: I2C1, START ADDRESS: FF030000, END ADDRESS: FF03FFFF + # : APERTURE NAME: SPI0, START ADDRESS: FF040000, END ADDRESS: FF04FFFF + # : APERTURE NAME: SPI1, START ADDRESS: FF050000, END ADDRESS: FF05FFFF + # : APERTURE NAME: CAN0, START ADDRESS: FF060000, END ADDRESS: FF06FFFF + # : APERTURE NAME: CAN1, START ADDRESS: FF070000, END ADDRESS: FF07FFFF + # : APERTURE NAME: RPU_UNUSED_12, START ADDRESS: FF080000, END ADDRESS: FF09FFFF + # : APERTURE NAME: RPU_UNUSED_12, START ADDRESS: FF080000, END ADDRESS: FF09FFFF + # : APERTURE NAME: GPIO, START ADDRESS: FF0A0000, END ADDRESS: FF0AFFFF + # : APERTURE NAME: GEM0, START ADDRESS: FF0B0000, END ADDRESS: FF0BFFFF + # : APERTURE NAME: GEM1, START ADDRESS: FF0C0000, END ADDRESS: FF0CFFFF + # : APERTURE NAME: GEM2, START ADDRESS: FF0D0000, END ADDRESS: FF0DFFFF + # : APERTURE NAME: GEM3, START ADDRESS: FF0E0000, END ADDRESS: FF0EFFFF + # : APERTURE NAME: QSPI, START ADDRESS: FF0F0000, END ADDRESS: FF0FFFFF + # : APERTURE NAME: NAND, START ADDRESS: FF100000, END ADDRESS: FF10FFFF + # : APERTURE NAME: TTC0, START ADDRESS: FF110000, END ADDRESS: FF11FFFF + # : APERTURE NAME: TTC1, START ADDRESS: FF120000, END ADDRESS: FF12FFFF + # : APERTURE NAME: TTC2, START ADDRESS: FF130000, END ADDRESS: FF13FFFF + # : APERTURE NAME: TTC3, START ADDRESS: FF140000, END ADDRESS: FF14FFFF + # : APERTURE NAME: SWDT, START ADDRESS: FF150000, END ADDRESS: FF15FFFF + # : APERTURE NAME: SD0, START ADDRESS: FF160000, END ADDRESS: FF16FFFF + # : APERTURE NAME: SD1, START ADDRESS: FF170000, END ADDRESS: FF17FFFF + # : APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + # : APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + # : APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + # : APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + # : APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + # : APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + # : APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + # : APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + # : APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + # : APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + # : APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + # : APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + # : APERTURE NAME: IOU_SECURE_SLCR, START ADDRESS: FF240000, END ADDRESS: FF24FFFF + # : APERTURE NAME: IOU_SCNTR, START ADDRESS: FF250000, END ADDRESS: FF25FFFF + # : APERTURE NAME: IOU_SCNTRS, START ADDRESS: FF260000, END ADDRESS: FF26FFFF + # : APERTURE NAME: RPU_UNUSED_11, START ADDRESS: FF270000, END ADDRESS: FF2AFFFF + # : APERTURE NAME: RPU_UNUSED_11, START ADDRESS: FF270000, END ADDRESS: FF2AFFFF + # : APERTURE NAME: RPU_UNUSED_11, START ADDRESS: FF270000, END ADDRESS: FF2AFFFF + # : APERTURE NAME: RPU_UNUSED_11, START ADDRESS: FF270000, END ADDRESS: FF2AFFFF + # : APERTURE NAME: LPD_UNUSED_14, START ADDRESS: FF2B0000, END ADDRESS: FF2FFFFF + # : APERTURE NAME: LPD_UNUSED_14, START ADDRESS: FF2B0000, END ADDRESS: FF2FFFFF + # : APERTURE NAME: LPD_UNUSED_14, START ADDRESS: FF2B0000, END ADDRESS: FF2FFFFF + # : APERTURE NAME: LPD_UNUSED_14, START ADDRESS: FF2B0000, END ADDRESS: FF2FFFFF + # : APERTURE NAME: LPD_UNUSED_14, START ADDRESS: FF2B0000, END ADDRESS: FF2FFFFF + # : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + # : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + # : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + # : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + # : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + # : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + # : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + # : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + # : APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF + # : APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF + # : APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF + # : APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF + # : APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF + # : APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF + # : APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF + # : APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF + # : APERTURE NAME: LPD_UNUSED_1, START ADDRESS: FF400000, END ADDRESS: FF40FFFF + # : APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + # : APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + # : APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + # : APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + # : APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + # : APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + # : APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + # : APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + # : APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + # : APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + # : APERTURE NAME: LPD_SLCR_SECURE, START ADDRESS: FF4B0000, END ADDRESS: FF4DFFFF + # : APERTURE NAME: LPD_SLCR_SECURE, START ADDRESS: FF4B0000, END ADDRESS: FF4DFFFF + # : APERTURE NAME: LPD_SLCR_SECURE, START ADDRESS: FF4B0000, END ADDRESS: FF4DFFFF + # : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF + # : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF + # : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF + # : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF + # : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF + # : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF + # : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF + # : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF + # : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF + # : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF + # : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF + # : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF + # : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF + # : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF + # : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF + # : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF + # : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF + # : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF + # : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF + # : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF + # : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF + # : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF + # : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF + # : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF + # : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF + # : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF + # : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF + # : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF + # : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF + # : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF + # : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF + # : APERTURE NAME: OCM_SLCR, START ADDRESS: FF960000, END ADDRESS: FF96FFFF + # : APERTURE NAME: LPD_UNUSED_4, START ADDRESS: FF970000, END ADDRESS: FF97FFFF + # : APERTURE NAME: LPD_XPPU, START ADDRESS: FF980000, END ADDRESS: FF99FFFF + # : APERTURE NAME: RPU, START ADDRESS: FF9A0000, END ADDRESS: FF9AFFFF + # : APERTURE NAME: AFIFM6, START ADDRESS: FF9B0000, END ADDRESS: FF9BFFFF + # : APERTURE NAME: LPD_XPPU_SINK, START ADDRESS: FF9C0000, END ADDRESS: FF9CFFFF + # : APERTURE NAME: USB3_0, START ADDRESS: FF9D0000, END ADDRESS: FF9DFFFF + # : APERTURE NAME: USB3_1, START ADDRESS: FF9E0000, END ADDRESS: FF9EFFFF + # : APERTURE NAME: LPD_UNUSED_5, START ADDRESS: FF9F0000, END ADDRESS: FF9FFFFF + # : APERTURE NAME: APM0, START ADDRESS: FFA00000, END ADDRESS: FFA0FFFF + # : APERTURE NAME: APM1, START ADDRESS: FFA10000, END ADDRESS: FFA1FFFF + # : APERTURE NAME: APM_INTC_IOU, START ADDRESS: FFA20000, END ADDRESS: FFA2FFFF + # : APERTURE NAME: APM_FPD_LPD, START ADDRESS: FFA30000, END ADDRESS: FFA3FFFF + # : APERTURE NAME: LPD_UNUSED_6, START ADDRESS: FFA40000, END ADDRESS: FFA4FFFF + # : APERTURE NAME: AMS, START ADDRESS: FFA50000, END ADDRESS: FFA5FFFF + # : APERTURE NAME: RTC, START ADDRESS: FFA60000, END ADDRESS: FFA6FFFF + # : APERTURE NAME: OCM_XMPU_CFG, START ADDRESS: FFA70000, END ADDRESS: FFA7FFFF + # : APERTURE NAME: ADMA_0, START ADDRESS: FFA80000, END ADDRESS: FFA8FFFF + # : APERTURE NAME: ADMA_1, START ADDRESS: FFA90000, END ADDRESS: FFA9FFFF + # : APERTURE NAME: ADMA_2, START ADDRESS: FFAA0000, END ADDRESS: FFAAFFFF + # : APERTURE NAME: ADMA_3, START ADDRESS: FFAB0000, END ADDRESS: FFABFFFF + # : APERTURE NAME: ADMA_4, START ADDRESS: FFAC0000, END ADDRESS: FFACFFFF + # : APERTURE NAME: ADMA_5, START ADDRESS: FFAD0000, END ADDRESS: FFADFFFF + # : APERTURE NAME: ADMA_6, START ADDRESS: FFAE0000, END ADDRESS: FFAEFFFF + # : APERTURE NAME: ADMA_7, START ADDRESS: FFAF0000, END ADDRESS: FFAFFFFF + # : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF + # : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF + # : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF + # : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF + # : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF + # : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF + # : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF + # : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF + # : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF + # : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF + # : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF + # : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF + # : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF + # : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF + # : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF + # : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF + # : APERTURE NAME: CSU_ROM, START ADDRESS: FFC00000, END ADDRESS: FFC1FFFF + # : APERTURE NAME: CSU_ROM, START ADDRESS: FFC00000, END ADDRESS: FFC1FFFF + # : APERTURE NAME: CSU_LOCAL, START ADDRESS: FFC20000, END ADDRESS: FFC2FFFF + # : APERTURE NAME: PUF, START ADDRESS: FFC30000, END ADDRESS: FFC3FFFF + # : APERTURE NAME: CSU_RAM, START ADDRESS: FFC40000, END ADDRESS: FFC5FFFF + # : APERTURE NAME: CSU_RAM, START ADDRESS: FFC40000, END ADDRESS: FFC5FFFF + # : APERTURE NAME: CSU_IOMODULE, START ADDRESS: FFC60000, END ADDRESS: FFC7FFFF + # : APERTURE NAME: CSU_IOMODULE, START ADDRESS: FFC60000, END ADDRESS: FFC7FFFF + # : APERTURE NAME: CSUDMA, START ADDRESS: FFC80000, END ADDRESS: FFC9FFFF + # : APERTURE NAME: CSUDMA, START ADDRESS: FFC80000, END ADDRESS: FFC9FFFF + # : APERTURE NAME: CSU, START ADDRESS: FFCA0000, END ADDRESS: FFCAFFFF + # : APERTURE NAME: CSU_WDT, START ADDRESS: FFCB0000, END ADDRESS: FFCBFFFF + # : APERTURE NAME: EFUSE, START ADDRESS: FFCC0000, END ADDRESS: FFCCFFFF + # : APERTURE NAME: BBRAM, START ADDRESS: FFCD0000, END ADDRESS: FFCDFFFF + # : APERTURE NAME: RSA_CORE, START ADDRESS: FFCE0000, END ADDRESS: FFCEFFFF + # : APERTURE NAME: MBISTJTAG, START ADDRESS: FFCF0000, END ADDRESS: FFCFFFFF + # : APERTURE NAME: PMU_ROM, START ADDRESS: FFD00000, END ADDRESS: FFD3FFFF + # : APERTURE NAME: PMU_ROM, START ADDRESS: FFD00000, END ADDRESS: FFD3FFFF + # : APERTURE NAME: PMU_ROM, START ADDRESS: FFD00000, END ADDRESS: FFD3FFFF + # : APERTURE NAME: PMU_ROM, START ADDRESS: FFD00000, END ADDRESS: FFD3FFFF + # : APERTURE NAME: PMU_IOMODULE, START ADDRESS: FFD40000, END ADDRESS: FFD5FFFF + # : APERTURE NAME: PMU_IOMODULE, START ADDRESS: FFD40000, END ADDRESS: FFD5FFFF + # : APERTURE NAME: PMU_LOCAL, START ADDRESS: FFD60000, END ADDRESS: FFD7FFFF + # : APERTURE NAME: PMU_LOCAL, START ADDRESS: FFD60000, END ADDRESS: FFD7FFFF + # : APERTURE NAME: PMU_GLOBAL, START ADDRESS: FFD80000, END ADDRESS: FFDBFFFF + # : APERTURE NAME: PMU_GLOBAL, START ADDRESS: FFD80000, END ADDRESS: FFDBFFFF + # : APERTURE NAME: PMU_GLOBAL, START ADDRESS: FFD80000, END ADDRESS: FFDBFFFF + # : APERTURE NAME: PMU_GLOBAL, START ADDRESS: FFD80000, END ADDRESS: FFDBFFFF + # : APERTURE NAME: PMU_RAM, START ADDRESS: FFDC0000, END ADDRESS: FFDFFFFF + # : APERTURE NAME: PMU_RAM, START ADDRESS: FFDC0000, END ADDRESS: FFDFFFFF + # : APERTURE NAME: PMU_RAM, START ADDRESS: FFDC0000, END ADDRESS: FFDFFFFF + # : APERTURE NAME: PMU_RAM, START ADDRESS: FFDC0000, END ADDRESS: FFDFFFFF + # : APERTURE NAME: R5_0_ATCM, START ADDRESS: FFE00000, END ADDRESS: FFE0FFFF + # : APERTURE NAME: R5_0_ATCM_LOCKSTEP, START ADDRESS: FFE10000, END ADDRESS: FFE1FFFF + # : APERTURE NAME: R5_0_BTCM, START ADDRESS: FFE20000, END ADDRESS: FFE2FFFF + # : APERTURE NAME: R5_0_BTCM_LOCKSTEP, START ADDRESS: FFE30000, END ADDRESS: FFE3FFFF + # : APERTURE NAME: R5_0_INSTRUCTION_CACHE, START ADDRESS: FFE40000, END ADDRESS: FFE4FFFF + # : APERTURE NAME: R5_0_DATA_CACHE, START ADDRESS: FFE50000, END ADDRESS: FFE5FFFF + # : APERTURE NAME: LPD_UNUSED_8, START ADDRESS: FFE60000, END ADDRESS: FFE8FFFF + # : APERTURE NAME: LPD_UNUSED_8, START ADDRESS: FFE60000, END ADDRESS: FFE8FFFF + # : APERTURE NAME: LPD_UNUSED_8, START ADDRESS: FFE60000, END ADDRESS: FFE8FFFF + # : APERTURE NAME: R5_1_ATCM_, START ADDRESS: FFE90000, END ADDRESS: FFE9FFFF + # : APERTURE NAME: RPU_UNUSED_10, START ADDRESS: FFEA0000, END ADDRESS: FFEAFFFF + # : APERTURE NAME: R5_1_BTCM_, START ADDRESS: FFEB0000, END ADDRESS: FFEBFFFF + # : APERTURE NAME: R5_1_INSTRUCTION_CACHE, START ADDRESS: FFEC0000, END ADDRESS: FFECFFFF + # : APERTURE NAME: R5_1_DATA_CACHE, START ADDRESS: FFED0000, END ADDRESS: FFEDFFFF + # : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF + # : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF + # : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF + # : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF + # : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF + # : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF + # : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF + # : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF + # : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF + # : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF + # : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF + # : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF + # : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF + # : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF + # : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF + # : APERTURE NAME: LPD_UNUSED_15, START ADDRESS: FFFD0000, END ADDRESS: FFFFFFFF + # : APERTURE NAME: LPD_UNUSED_15, START ADDRESS: FFFD0000, END ADDRESS: FFFFFFFF + # : APERTURE NAME: LPD_UNUSED_15, START ADDRESS: FFFD0000, END ADDRESS: FFFFFFFF + # : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + # : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + # : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + # : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + # : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + # : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + # : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + # : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + # : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + # : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + # : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + # : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + # : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + # : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + # : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + # : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + # : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + # : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + # : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + # : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + # : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + # : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + # : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + # : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + # : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + # : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + # : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + # : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + # : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + # : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + # : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + # : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + # : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + # : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + # : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + # : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + # : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + # : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + # : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + # : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + # : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + # : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + # : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + # : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + # : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + # : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + # : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + # : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + # : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + # : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + # : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + # : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + # : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + # : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + # : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + # : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + # : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + # : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + # : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + # : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + # : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + # : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + # : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + # : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + # : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + # : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + # : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + # : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + # : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + # : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + # : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + # : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + # : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + # : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + # : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + # : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + # : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + # : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + # : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + # : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + # : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + # : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + # : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + # : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + # : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + # : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + # : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + # : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + # : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + # : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + # : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + # : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + # : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + # : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + # : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + # : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + # : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + # : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + # : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + # : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + # : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + # : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + # : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + # : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + # : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + # : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + # : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + # : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + # : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + # : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + # : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + # : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + # : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + # : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + # : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + # : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + # : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + # : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + # : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + # : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + # : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + # : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + # : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + # : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + # : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + # : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + # : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + # : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + # : APERTURE NAME: IOU_GPV, START ADDRESS: FE000000, END ADDRESS: FE0FFFFF + # : APERTURE NAME: LPD_GPV, START ADDRESS: FE100000, END ADDRESS: FE1FFFFF + # : APERTURE NAME: USB3_0_XHCI, START ADDRESS: FE200000, END ADDRESS: FE2FFFFF + # : APERTURE NAME: USB3_1_XHCI, START ADDRESS: FE300000, END ADDRESS: FE3FFFFF + # : APERTURE NAME: LPD_UNUSED_13, START ADDRESS: FE400000, END ADDRESS: FE7FFFFF + # : APERTURE NAME: LPD_UNUSED_13, START ADDRESS: FE400000, END ADDRESS: FE7FFFFF + # : APERTURE NAME: LPD_UNUSED_13, START ADDRESS: FE400000, END ADDRESS: FE7FFFFF + # : APERTURE NAME: LPD_UNUSED_13, START ADDRESS: FE400000, END ADDRESS: FE7FFFFF + # : APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF + # : APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF + # : APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF + # : APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF + # : APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF + # : APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF + # : APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF + # : APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF + # : APERTURE NAME: QSPI_LINEAR_ADDRESS, START ADDRESS: C0000000, END ADDRESS: DFFFFFFF + # : XPPU CONTROL } set psu_ddr_xmpu0_data { + # : DDR XMPU0 } set psu_ddr_xmpu1_data { + # : DDR XMPU1 } set psu_ddr_xmpu2_data { + # : DDR XMPU2 } set psu_ddr_xmpu3_data { + # : DDR XMPU3 } set psu_ddr_xmpu4_data { + # : DDR XMPU4 } set psu_ddr_xmpu5_data { + # : DDR XMPU5 } set psu_ocm_xmpu_data { + # : OCM XMPU } set psu_fpd_xmpu_data { + # : FPD XMPU } set psu_protection_lock_data { + # : LOCKING PROTECTION MODULE + # : XPPU LOCK + # : APERTURE NAME: LPD_XPPU, START ADDRESS: FF980000, END ADDRESS: FF99FFFF + # : XMPU LOCK + # : LOCK OCM XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER + # : LOCK FPD XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER + # : LOCK DDR XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER + # : LOCK DDR XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER + # : LOCK DDR XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER + # : LOCK DDR XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER + # : LOCK DDR XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER + # : LOCK DDR XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER } set psu_apply_master_tz { # : RPU # : DP TZ + # Register : slcr_dpdma @ 0XFD690040

+ + # TrustZone classification for DisplayPort DMA + # PSU_FPD_SLCR_SECURE_SLCR_DPDMA_TZ 1 + + # DPDMA TrustZone Settings + #(OFFSET, MASK, VALUE) (0XFD690040, 0x00000001U ,0x00000001U) */ + mask_write 0XFD690040 0x00000001 0x00000001 # : SATA TZ # : PCIE TZ + # Register : slcr_pcie @ 0XFD690030

+ + # TrustZone classification for DMA Channel 0 + # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_0 1 + + # TrustZone classification for DMA Channel 1 + # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_1 1 + + # TrustZone classification for DMA Channel 2 + # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_2 1 + + # TrustZone classification for DMA Channel 3 + # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_3 1 + + # TrustZone classification for Ingress Address Translation 0 + # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_0 1 + + # TrustZone classification for Ingress Address Translation 1 + # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_1 1 + + # TrustZone classification for Ingress Address Translation 2 + # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_2 1 + + # TrustZone classification for Ingress Address Translation 3 + # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_3 1 + + # TrustZone classification for Ingress Address Translation 4 + # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_4 1 + + # TrustZone classification for Ingress Address Translation 5 + # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_5 1 + + # TrustZone classification for Ingress Address Translation 6 + # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_6 1 + + # TrustZone classification for Ingress Address Translation 7 + # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_7 1 + + # TrustZone classification for Egress Address Translation 0 + # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_0 1 + + # TrustZone classification for Egress Address Translation 1 + # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_1 1 + + # TrustZone classification for Egress Address Translation 2 + # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_2 1 + + # TrustZone classification for Egress Address Translation 3 + # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_3 1 + + # TrustZone classification for Egress Address Translation 4 + # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_4 1 + + # TrustZone classification for Egress Address Translation 5 + # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_5 1 + + # TrustZone classification for Egress Address Translation 6 + # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_6 1 + + # TrustZone classification for Egress Address Translation 7 + # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_7 1 + + # TrustZone classification for DMA Registers + # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_REGS 1 + + # TrustZone classification for MSIx Table + # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_TABLE 1 + + # TrustZone classification for MSIx PBA + # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_PBA 1 + + # TrustZone classification for ECAM + # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_ECAM 1 + + # TrustZone classification for Bridge Common Registers + # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_BRIDGE_REGS 1 + + # PCIe TrustZone settings. This register may only be modified during bootu + # p (while PCIe block is disabled) + #(OFFSET, MASK, VALUE) (0XFD690030, 0x01FFFFFFU ,0x01FFFFFFU) */ + mask_write 0XFD690030 0x01FFFFFF 0x01FFFFFF # : USB TZ + # Register : slcr_usb @ 0XFF4B0034

+ + # TrustZone Classification for USB3_0 + # PSU_LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_0 1 + + # TrustZone Classification for USB3_1 + # PSU_LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_1 1 + + # USB3 TrustZone settings + #(OFFSET, MASK, VALUE) (0XFF4B0034, 0x00000003U ,0x00000003U) */ + mask_write 0XFF4B0034 0x00000003 0x00000003 # : SD TZ + # Register : IOU_AXI_RPRTCN @ 0XFF240004

+ + # AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + # 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + # ccess [2] = '1'' : Instruction access + # PSU_IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD0_AXI_ARPROT 2 + + # AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + # 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + # ccess [2] = '1'' : Instruction access + # PSU_IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD1_AXI_ARPROT 2 + + # AXI read protection type selection + #(OFFSET, MASK, VALUE) (0XFF240004, 0x003F0000U ,0x00120000U) */ + mask_write 0XFF240004 0x003F0000 0x00120000 + # Register : IOU_AXI_WPRTCN @ 0XFF240000

+ + # AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + # 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + # ccess [2] = '1'' : Instruction access + # PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD0_AXI_AWPROT 2 + + # AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + # 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + # ccess [2] = '1'' : Instruction access + # PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD1_AXI_AWPROT 2 + + # AXI write protection type selection + #(OFFSET, MASK, VALUE) (0XFF240000, 0x003F0000U ,0x00120000U) */ + mask_write 0XFF240000 0x003F0000 0x00120000 # : GEM TZ + # Register : IOU_AXI_RPRTCN @ 0XFF240004

+ + # AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + # 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + # ccess [2] = '1'' : Instruction access + # PSU_IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM0_AXI_ARPROT 2 + + # AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + # 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + # ccess [2] = '1'' : Instruction access + # PSU_IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM1_AXI_ARPROT 2 + + # AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + # 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + # ccess [2] = '1'' : Instruction access + # PSU_IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM2_AXI_ARPROT 2 + + # AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + # 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + # ccess [2] = '1'' : Instruction access + # PSU_IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM3_AXI_ARPROT 2 + + # AXI read protection type selection + #(OFFSET, MASK, VALUE) (0XFF240004, 0x00000FFFU ,0x00000492U) */ + mask_write 0XFF240004 0x00000FFF 0x00000492 + # Register : IOU_AXI_WPRTCN @ 0XFF240000

+ + # AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + # 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + # ccess [2] = '1'' : Instruction access + # PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM0_AXI_AWPROT 2 + + # AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + # 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + # ccess [2] = '1'' : Instruction access + # PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM1_AXI_AWPROT 2 + + # AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + # 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + # ccess [2] = '1'' : Instruction access + # PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM2_AXI_AWPROT 2 + + # AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + # 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + # ccess [2] = '1'' : Instruction access + # PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM3_AXI_AWPROT 2 + + # AXI write protection type selection + #(OFFSET, MASK, VALUE) (0XFF240000, 0x00000FFFU ,0x00000492U) */ + mask_write 0XFF240000 0x00000FFF 0x00000492 # : QSPI TZ + # Register : IOU_AXI_WPRTCN @ 0XFF240000

+ + # AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + # 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + # ccess [2] = '1'' : Instruction access + # PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_QSPI_AXI_AWPROT 2 + + # AXI write protection type selection + #(OFFSET, MASK, VALUE) (0XFF240000, 0x0E000000U ,0x04000000U) */ + mask_write 0XFF240000 0x0E000000 0x04000000 # : NAND TZ + # Register : IOU_AXI_RPRTCN @ 0XFF240004

+ + # AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + # 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + # ccess [2] = '1'' : Instruction access + # PSU_IOU_SECURE_SLCR_IOU_AXI_RPRTCN_NAND_AXI_ARPROT 2 + + # AXI read protection type selection + #(OFFSET, MASK, VALUE) (0XFF240004, 0x01C00000U ,0x00800000U) */ + mask_write 0XFF240004 0x01C00000 0x00800000 + # Register : IOU_AXI_WPRTCN @ 0XFF240000

+ + # AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + # 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + # ccess [2] = '1'' : Instruction access + # PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_NAND_AXI_AWPROT 2 + + # AXI write protection type selection + #(OFFSET, MASK, VALUE) (0XFF240000, 0x01C00000U ,0x00800000U) */ + mask_write 0XFF240000 0x01C00000 0x00800000 + # : DMA TZ + # Register : slcr_adma @ 0XFF4B0024

+ + # TrustZone Classification for ADMA + # PSU_LPD_SLCR_SECURE_SLCR_ADMA_TZ 0xFF + + # RPU TrustZone settings + #(OFFSET, MASK, VALUE) (0XFF4B0024, 0x000000FFU ,0x000000FFU) */ + mask_write 0XFF4B0024 0x000000FF 0x000000FF + # Register : slcr_gdma @ 0XFD690050

+ + # TrustZone Classification for GDMA + # PSU_FPD_SLCR_SECURE_SLCR_GDMA_TZ 0xFF + + # GDMA Trustzone Settings + #(OFFSET, MASK, VALUE) (0XFD690050, 0x000000FFU ,0x000000FFU) */ + mask_write 0XFD690050 0x000000FF 0x000000FF } set psu_serdes_init_data { @@ -12415,9 +14468,11 @@ set psu_serdes_init_data { # : GT REFERENCE CLOCK SOURCE SELECTION # Register : PLL_REF_SEL0 @ 0XFD410000

- # PLL0 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - - # 4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135 - # Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved + # PLL0 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 1 + # 2MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 24MHz, 0x8 - 26MHz, + # 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE + # - 108MHz, 0xF - 125MHz, 0x10 - 135MHz, 0x11 - 150 MHz. 0x12 to 0x1F - R + # eserved # PSU_SERDES_PLL_REF_SEL0_PLLREFSEL0 0xD # PLL0 Reference Selection Register @@ -12425,9 +14480,11 @@ set psu_serdes_init_data { mask_write 0XFD410000 0x0000001F 0x0000000D # Register : PLL_REF_SEL1 @ 0XFD410004

- # PLL1 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - - # 4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135 - # Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved + # PLL1 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 1 + # 2MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 24MHz, 0x8 - 26MHz, + # 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE + # - 108MHz, 0xF - 125MHz, 0x10 - 135MHz, 0x11 - 150 MHz. 0x12 to 0x1F - R + # eserved # PSU_SERDES_PLL_REF_SEL1_PLLREFSEL1 0x9 # PLL1 Reference Selection Register @@ -12435,9 +14492,11 @@ set psu_serdes_init_data { mask_write 0XFD410004 0x0000001F 0x00000009 # Register : PLL_REF_SEL2 @ 0XFD410008

- # PLL2 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - - # 4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135 - # Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved + # PLL2 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 1 + # 2MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 24MHz, 0x8 - 26MHz, + # 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE + # - 108MHz, 0xF - 125MHz, 0x10 - 135MHz, 0x11 - 150 MHz. 0x12 to 0x1F - R + # eserved # PSU_SERDES_PLL_REF_SEL2_PLLREFSEL2 0x8 # PLL2 Reference Selection Register @@ -12445,9 +14504,11 @@ set psu_serdes_init_data { mask_write 0XFD410008 0x0000001F 0x00000008 # Register : PLL_REF_SEL3 @ 0XFD41000C

- # PLL3 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - - # 4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135 - # Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved + # PLL3 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 1 + # 2MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 24MHz, 0x8 - 26MHz, + # 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE + # - 108MHz, 0xF - 125MHz, 0x10 - 135MHz, 0x11 - 150 MHz. 0x12 to 0x1F - R + # eserved # PSU_SERDES_PLL_REF_SEL3_PLLREFSEL3 0xF # PLL3 Reference Selection Register @@ -12456,7 +14517,8 @@ set psu_serdes_init_data { # : GT REFERENCE CLOCK FREQUENCY SELECTION # Register : L0_L0_REF_CLK_SEL @ 0XFD402860

- # Sel of lane 0 ref clock local mux. Set to 1 to select lane 0 slicer output. Set to 0 to select lane0 ref clock mux output. + # Sel of lane 0 ref clock local mux. Set to 1 to select lane 0 slicer outp + # ut. Set to 0 to select lane0 ref clock mux output. # PSU_SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL 0x1 # Lane0 Ref Clock Selection Register @@ -12464,10 +14526,12 @@ set psu_serdes_init_data { mask_write 0XFD402860 0x00000080 0x00000080 # Register : L0_L1_REF_CLK_SEL @ 0XFD402864

- # Sel of lane 1 ref clock local mux. Set to 1 to select lane 1 slicer output. Set to 0 to select lane1 ref clock mux output. + # Sel of lane 1 ref clock local mux. Set to 1 to select lane 1 slicer outp + # ut. Set to 0 to select lane1 ref clock mux output. # PSU_SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL 0x0 - # Bit 3 of lane 1 ref clock mux one hot sel. Set to 1 to select lane 3 slicer output from ref clock network + # Bit 3 of lane 1 ref clock mux one hot sel. Set to 1 to select lane 3 sli + # cer output from ref clock network # PSU_SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3 0x1 # Lane1 Ref Clock Selection Register @@ -12475,7 +14539,8 @@ set psu_serdes_init_data { mask_write 0XFD402864 0x00000088 0x00000008 # Register : L0_L2_REF_CLK_SEL @ 0XFD402868

- # Sel of lane 2 ref clock local mux. Set to 1 to select lane 1 slicer output. Set to 0 to select lane2 ref clock mux output. + # Sel of lane 2 ref clock local mux. Set to 1 to select lane 1 slicer outp + # ut. Set to 0 to select lane2 ref clock mux output. # PSU_SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL 0x1 # Lane2 Ref Clock Selection Register @@ -12483,10 +14548,12 @@ set psu_serdes_init_data { mask_write 0XFD402868 0x00000080 0x00000080 # Register : L0_L3_REF_CLK_SEL @ 0XFD40286C

- # Sel of lane 3 ref clock local mux. Set to 1 to select lane 3 slicer output. Set to 0 to select lane3 ref clock mux output. + # Sel of lane 3 ref clock local mux. Set to 1 to select lane 3 slicer outp + # ut. Set to 0 to select lane3 ref clock mux output. # PSU_SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL 0x0 - # Bit 1 of lane 3 ref clock mux one hot sel. Set to 1 to select lane 1 slicer output from ref clock network + # Bit 1 of lane 3 ref clock mux one hot sel. Set to 1 to select lane 1 sli + # cer output from ref clock network # PSU_SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1 0x1 # Lane3 Ref Clock Selection Register @@ -12693,7 +14760,8 @@ set psu_serdes_init_data { # Enable test mode force on fractional mode enable # PSU_SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC 0x1 - # Fractional feedback division control and fractional value for feedback division bits 26:24 + # Fractional feedback division control and fractional value for feedback d + # ivision bits 26:24 #(OFFSET, MASK, VALUE) (0XFD40E360, 0x00000040U ,0x00000040U) */ mask_write 0XFD40E360 0x00000040 0x00000040 # Register : L3_TM_DIG_6 @ 0XFD40D06C

@@ -12727,14 +14795,6 @@ set psu_serdes_init_data { # MPHY PLL Gear and bypass scrambler #(OFFSET, MASK, VALUE) (0XFD40C0F4, 0x0000000BU ,0x0000000BU) */ mask_write 0XFD40C0F4 0x0000000B 0x0000000B - # Register : L3_TXPMA_ST_0 @ 0XFD40CB00

- - # PHY Mode: 4'b000 - PCIe, 4'b001 - USB3, 4'b0010 - SATA, 4'b0100 - SGMII, 4'b0101 - DP, 4'b1000 - MPHY - # PSU_SERDES_L3_TXPMA_ST_0_TX_PHY_MODE 0x21 - - # Opmode Info - #(OFFSET, MASK, VALUE) (0XFD40CB00, 0x000000F0U ,0x000000F0U) */ - mask_write 0XFD40CB00 0x000000F0 0x000000F0 # : ENABLE CHICKEN BIT FOR PCIE AND USB # Register : L0_TM_AUX_0 @ 0XFD4010CC

@@ -12796,7 +14856,8 @@ set psu_serdes_init_data { mask_write 0XFD40189C 0x00000080 0x00000080 # Register : L0_TM_IQ_ILL1 @ 0XFD4018F8

- # IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS + # IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , + # USB3 : SS # PSU_SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0 0x64 # iqpi cal code @@ -12820,7 +14881,8 @@ set psu_serdes_init_data { mask_write 0XFD401990 0x000000FF 0x00000011 # Register : L0_TM_E_ILL1 @ 0XFD401924

- # E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS + # E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , U + # SB3 : SS # PSU_SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0 0x4 # epi cal code @@ -12890,6 +14952,22 @@ set psu_serdes_init_data { # enables for lf,constant gm trim and polytirm #(OFFSET, MASK, VALUE) (0XFD401944, 0x00000001U ,0x00000001U) */ mask_write 0XFD401944 0x00000001 0x00000001 + # Register : L0_TM_ILL13 @ 0XFD401994

+ + # ILL cal idle val refcnt + # PSU_SERDES_L0_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT 0x7 + + # ill cal idle value count + #(OFFSET, MASK, VALUE) (0XFD401994, 0x00000007U ,0x00000007U) */ + mask_write 0XFD401994 0x00000007 0x00000007 + # Register : L1_TM_ILL13 @ 0XFD405994

+ + # ILL cal idle val refcnt + # PSU_SERDES_L1_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT 0x7 + + # ill cal idle value count + #(OFFSET, MASK, VALUE) (0XFD405994, 0x00000007U ,0x00000007U) */ + mask_write 0XFD405994 0x00000007 0x00000007 # Register : L2_TM_MISC2 @ 0XFD40989C

# ILL calib counts BYPASSED with calcode bits @@ -12900,7 +14978,8 @@ set psu_serdes_init_data { mask_write 0XFD40989C 0x00000080 0x00000080 # Register : L2_TM_IQ_ILL1 @ 0XFD4098F8

- # IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS + # IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , + # USB3 : SS # PSU_SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0 0x1A # iqpi cal code @@ -12924,7 +15003,8 @@ set psu_serdes_init_data { mask_write 0XFD409990 0x000000FF 0x00000010 # Register : L2_TM_E_ILL1 @ 0XFD409924

- # E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS + # E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , U + # SB3 : SS # PSU_SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0 0xFE # epi cal code @@ -12994,6 +15074,14 @@ set psu_serdes_init_data { # enables for lf,constant gm trim and polytirm #(OFFSET, MASK, VALUE) (0XFD409944, 0x00000001U ,0x00000001U) */ mask_write 0XFD409944 0x00000001 0x00000001 + # Register : L2_TM_ILL13 @ 0XFD409994

+ + # ILL cal idle val refcnt + # PSU_SERDES_L2_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT 0x7 + + # ill cal idle value count + #(OFFSET, MASK, VALUE) (0XFD409994, 0x00000007U ,0x00000007U) */ + mask_write 0XFD409994 0x00000007 0x00000007 # Register : L3_TM_MISC2 @ 0XFD40D89C

# ILL calib counts BYPASSED with calcode bits @@ -13004,7 +15092,8 @@ set psu_serdes_init_data { mask_write 0XFD40D89C 0x00000080 0x00000080 # Register : L3_TM_IQ_ILL1 @ 0XFD40D8F8

- # IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS + # IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , + # USB3 : SS # PSU_SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0 0x7D # iqpi cal code @@ -13028,7 +15117,8 @@ set psu_serdes_init_data { mask_write 0XFD40D990 0x000000FF 0x00000001 # Register : L3_TM_E_ILL1 @ 0XFD40D924

- # E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS + # E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , U + # SB3 : SS # PSU_SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0 0x9C # epi cal code @@ -13106,23 +15196,47 @@ set psu_serdes_init_data { # enables for lf,constant gm trim and polytirm #(OFFSET, MASK, VALUE) (0XFD40D944, 0x00000001U ,0x00000001U) */ mask_write 0XFD40D944 0x00000001 0x00000001 + # Register : L3_TM_ILL13 @ 0XFD40D994

+ + # ILL cal idle val refcnt + # PSU_SERDES_L3_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT 0x7 + + # ill cal idle value count + #(OFFSET, MASK, VALUE) (0XFD40D994, 0x00000007U ,0x00000007U) */ + mask_write 0XFD40D994 0x00000007 0x00000007 # : SYMBOL LOCK AND WAIT - # Register : L0_TM_DIG_21 @ 0XFD4010A8

- - # pre lock comma count threshold. 2'b 00 : 3, 2'b 01 : 5, 2'b 10 : 10, 2'b 11 : 20 - # PSU_SERDES_L0_TM_DIG_21_COMMA_PRE_LOCK_THRESH 0x11 - - # Control symbol alignment locking - wait counts - #(OFFSET, MASK, VALUE) (0XFD4010A8, 0x00000003U ,0x00000003U) */ - mask_write 0XFD4010A8 0x00000003 0x00000003 # Register : L0_TM_DIG_10 @ 0XFD40107C

# CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001 - # PSU_SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME 0xF + # PSU_SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME 0x1 # test control for changing cdr lock wait time - #(OFFSET, MASK, VALUE) (0XFD40107C, 0x0000000FU ,0x0000000FU) */ - mask_write 0XFD40107C 0x0000000F 0x0000000F + #(OFFSET, MASK, VALUE) (0XFD40107C, 0x0000000FU ,0x00000001U) */ + mask_write 0XFD40107C 0x0000000F 0x00000001 + # Register : L1_TM_DIG_10 @ 0XFD40507C

+ + # CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001 + # PSU_SERDES_L1_TM_DIG_10_CDR_BIT_LOCK_TIME 0x1 + + # test control for changing cdr lock wait time + #(OFFSET, MASK, VALUE) (0XFD40507C, 0x0000000FU ,0x00000001U) */ + mask_write 0XFD40507C 0x0000000F 0x00000001 + # Register : L2_TM_DIG_10 @ 0XFD40907C

+ + # CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001 + # PSU_SERDES_L2_TM_DIG_10_CDR_BIT_LOCK_TIME 0x1 + + # test control for changing cdr lock wait time + #(OFFSET, MASK, VALUE) (0XFD40907C, 0x0000000FU ,0x00000001U) */ + mask_write 0XFD40907C 0x0000000F 0x00000001 + # Register : L3_TM_DIG_10 @ 0XFD40D07C

+ + # CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001 + # PSU_SERDES_L3_TM_DIG_10_CDR_BIT_LOCK_TIME 0x1 + + # test control for changing cdr lock wait time + #(OFFSET, MASK, VALUE) (0XFD40D07C, 0x0000000FU ,0x00000001U) */ + mask_write 0XFD40D07C 0x0000000F 0x00000001 # : SIOU SETTINGS FOR BYPASS CONTROL,HSRX-DIG # Register : L0_TM_RST_DLY @ 0XFD4019A4

@@ -13137,7 +15251,8 @@ set psu_serdes_init_data { # Enable Bypass for <7> of TM_ANA_BYPS_15 # PSU_SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE 0x1 - # Bypass control for pcs-pma interface. EQ supplies, main master supply and ps for samp c2c + # Bypass control for pcs-pma interface. EQ supplies, main master supply an + # d ps for samp c2c #(OFFSET, MASK, VALUE) (0XFD401038, 0x00000040U ,0x00000040U) */ mask_write 0XFD401038 0x00000040 0x00000040 # Register : L0_TM_ANA_BYP_12 @ 0XFD40102C

@@ -13145,7 +15260,8 @@ set psu_serdes_init_data { # Enable Bypass for <7> of TM_ANA_BYPS_12 # PSU_SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG 0x1 - # Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr enable controls + # Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr ena + # ble controls #(OFFSET, MASK, VALUE) (0XFD40102C, 0x00000040U ,0x00000040U) */ mask_write 0XFD40102C 0x00000040 0x00000040 # Register : L1_TM_RST_DLY @ 0XFD4059A4

@@ -13161,7 +15277,8 @@ set psu_serdes_init_data { # Enable Bypass for <7> of TM_ANA_BYPS_15 # PSU_SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE 0x1 - # Bypass control for pcs-pma interface. EQ supplies, main master supply and ps for samp c2c + # Bypass control for pcs-pma interface. EQ supplies, main master supply an + # d ps for samp c2c #(OFFSET, MASK, VALUE) (0XFD405038, 0x00000040U ,0x00000040U) */ mask_write 0XFD405038 0x00000040 0x00000040 # Register : L1_TM_ANA_BYP_12 @ 0XFD40502C

@@ -13169,7 +15286,8 @@ set psu_serdes_init_data { # Enable Bypass for <7> of TM_ANA_BYPS_12 # PSU_SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG 0x1 - # Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr enable controls + # Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr ena + # ble controls #(OFFSET, MASK, VALUE) (0XFD40502C, 0x00000040U ,0x00000040U) */ mask_write 0XFD40502C 0x00000040 0x00000040 # Register : L2_TM_RST_DLY @ 0XFD4099A4

@@ -13185,7 +15303,8 @@ set psu_serdes_init_data { # Enable Bypass for <7> of TM_ANA_BYPS_15 # PSU_SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE 0x1 - # Bypass control for pcs-pma interface. EQ supplies, main master supply and ps for samp c2c + # Bypass control for pcs-pma interface. EQ supplies, main master supply an + # d ps for samp c2c #(OFFSET, MASK, VALUE) (0XFD409038, 0x00000040U ,0x00000040U) */ mask_write 0XFD409038 0x00000040 0x00000040 # Register : L2_TM_ANA_BYP_12 @ 0XFD40902C

@@ -13193,7 +15312,8 @@ set psu_serdes_init_data { # Enable Bypass for <7> of TM_ANA_BYPS_12 # PSU_SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG 0x1 - # Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr enable controls + # Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr ena + # ble controls #(OFFSET, MASK, VALUE) (0XFD40902C, 0x00000040U ,0x00000040U) */ mask_write 0XFD40902C 0x00000040 0x00000040 # Register : L3_TM_RST_DLY @ 0XFD40D9A4

@@ -13209,7 +15329,8 @@ set psu_serdes_init_data { # Enable Bypass for <7> of TM_ANA_BYPS_15 # PSU_SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE 0x1 - # Bypass control for pcs-pma interface. EQ supplies, main master supply and ps for samp c2c + # Bypass control for pcs-pma interface. EQ supplies, main master supply an + # d ps for samp c2c #(OFFSET, MASK, VALUE) (0XFD40D038, 0x00000040U ,0x00000040U) */ mask_write 0XFD40D038 0x00000040 0x00000040 # Register : L3_TM_ANA_BYP_12 @ 0XFD40D02C

@@ -13217,18 +15338,106 @@ set psu_serdes_init_data { # Enable Bypass for <7> of TM_ANA_BYPS_12 # PSU_SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG 0x1 - # Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr enable controls + # Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr ena + # ble controls #(OFFSET, MASK, VALUE) (0XFD40D02C, 0x00000040U ,0x00000040U) */ mask_write 0XFD40D02C 0x00000040 0x00000040 + # : DISABLE FPL/FFL + # Register : L0_TM_MISC3 @ 0XFD4019AC

+ + # CDR fast phase lock control + # PSU_SERDES_L0_TM_MISC3_CDR_EN_FPL 0x0 + + # CDR fast frequency lock control + # PSU_SERDES_L0_TM_MISC3_CDR_EN_FFL 0x0 + + # debug bus selection bit, cdr fast phase and freq controls + #(OFFSET, MASK, VALUE) (0XFD4019AC, 0x00000003U ,0x00000000U) */ + mask_write 0XFD4019AC 0x00000003 0x00000000 + # Register : L1_TM_MISC3 @ 0XFD4059AC

+ + # CDR fast phase lock control + # PSU_SERDES_L1_TM_MISC3_CDR_EN_FPL 0x0 + + # CDR fast frequency lock control + # PSU_SERDES_L1_TM_MISC3_CDR_EN_FFL 0x0 + + # debug bus selection bit, cdr fast phase and freq controls + #(OFFSET, MASK, VALUE) (0XFD4059AC, 0x00000003U ,0x00000000U) */ + mask_write 0XFD4059AC 0x00000003 0x00000000 + # Register : L2_TM_MISC3 @ 0XFD4099AC

+ + # CDR fast phase lock control + # PSU_SERDES_L2_TM_MISC3_CDR_EN_FPL 0x0 + + # CDR fast frequency lock control + # PSU_SERDES_L2_TM_MISC3_CDR_EN_FFL 0x0 + + # debug bus selection bit, cdr fast phase and freq controls + #(OFFSET, MASK, VALUE) (0XFD4099AC, 0x00000003U ,0x00000000U) */ + mask_write 0XFD4099AC 0x00000003 0x00000000 + # Register : L3_TM_MISC3 @ 0XFD40D9AC

+ + # CDR fast phase lock control + # PSU_SERDES_L3_TM_MISC3_CDR_EN_FPL 0x0 + + # CDR fast frequency lock control + # PSU_SERDES_L3_TM_MISC3_CDR_EN_FFL 0x0 + + # debug bus selection bit, cdr fast phase and freq controls + #(OFFSET, MASK, VALUE) (0XFD40D9AC, 0x00000003U ,0x00000000U) */ + mask_write 0XFD40D9AC 0x00000003 0x00000000 + # : DISABLE DYNAMIC OFFSET CALIBRATION + # Register : L0_TM_EQ11 @ 0XFD401978

+ + # Force EQ offset correction algo off if not forced on + # PSU_SERDES_L0_TM_EQ11_FORCE_EQ_OFFS_OFF 0x1 + + # eq dynamic offset correction + #(OFFSET, MASK, VALUE) (0XFD401978, 0x00000010U ,0x00000010U) */ + mask_write 0XFD401978 0x00000010 0x00000010 + # Register : L1_TM_EQ11 @ 0XFD405978

+ + # Force EQ offset correction algo off if not forced on + # PSU_SERDES_L1_TM_EQ11_FORCE_EQ_OFFS_OFF 0x1 + + # eq dynamic offset correction + #(OFFSET, MASK, VALUE) (0XFD405978, 0x00000010U ,0x00000010U) */ + mask_write 0XFD405978 0x00000010 0x00000010 + # Register : L2_TM_EQ11 @ 0XFD409978

+ + # Force EQ offset correction algo off if not forced on + # PSU_SERDES_L2_TM_EQ11_FORCE_EQ_OFFS_OFF 0x1 + + # eq dynamic offset correction + #(OFFSET, MASK, VALUE) (0XFD409978, 0x00000010U ,0x00000010U) */ + mask_write 0XFD409978 0x00000010 0x00000010 + # Register : L3_TM_EQ11 @ 0XFD40D978

+ + # Force EQ offset correction algo off if not forced on + # PSU_SERDES_L3_TM_EQ11_FORCE_EQ_OFFS_OFF 0x1 + + # eq dynamic offset correction + #(OFFSET, MASK, VALUE) (0XFD40D978, 0x00000010U ,0x00000010U) */ + mask_write 0XFD40D978 0x00000010 0x00000010 + # : DISABLE ECO FOR PCIE + # Register : eco_0 @ 0XFD3D001C

+ + # For future use + # PSU_SIOU_ECO_0_FIELD 0x1 + + # ECO Register for future use + #(OFFSET, MASK, VALUE) (0XFD3D001C, 0xFFFFFFFFU ,0x00000001U) */ + mask_write 0XFD3D001C 0xFFFFFFFF 0x00000001 # : GT LANE SETTINGS # Register : ICM_CFG0 @ 0XFD410010

- # Controls UPHY Lane 0 protocol configuration. 0 - PowerDown, 1 - PCIe .0, 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII0, 6 - Unuse - # , 7 - Unused + # Controls UPHY Lane 0 protocol configuration. 0 - PowerDown, 1 - PCIe .0, + # 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII0, 6 - Unused, 7 - Unused # PSU_SERDES_ICM_CFG0_L0_ICM_CFG 1 - # Controls UPHY Lane 1 protocol configuration. 0 - PowerDown, 1 - PCIe.1, 2 - Sata1, 3 - USB0, 4 - DP.0, 5 - SGMII1, 6 - Unused - # 7 - Unused + # Controls UPHY Lane 1 protocol configuration. 0 - PowerDown, 1 - PCIe.1, + # 2 - Sata1, 3 - USB0, 4 - DP.0, 5 - SGMII1, 6 - Unused, 7 - Unused # PSU_SERDES_ICM_CFG0_L1_ICM_CFG 4 # ICM Configuration Register 0 @@ -13236,12 +15445,12 @@ set psu_serdes_init_data { mask_write 0XFD410010 0x00000077 0x00000041 # Register : ICM_CFG1 @ 0XFD410014

- # Controls UPHY Lane 2 protocol configuration. 0 - PowerDown, 1 - PCIe.1, 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII2, 6 - Unused - # 7 - Unused + # Controls UPHY Lane 2 protocol configuration. 0 - PowerDown, 1 - PCIe.1, + # 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII2, 6 - Unused, 7 - Unused # PSU_SERDES_ICM_CFG1_L2_ICM_CFG 3 - # Controls UPHY Lane 3 protocol configuration. 0 - PowerDown, 1 - PCIe.3, 2 - Sata1, 3 - USB1, 4 - DP.0, 5 - SGMII3, 6 - Unused - # 7 - Unused + # Controls UPHY Lane 3 protocol configuration. 0 - PowerDown, 1 - PCIe.3, + # 2 - Sata1, 3 - USB1, 4 - DP.0, 5 - SGMII3, 6 - Unused, 7 - Unused # PSU_SERDES_ICM_CFG1_L3_ICM_CFG 2 # ICM Configuration Register 1 @@ -13294,7 +15503,8 @@ set psu_serdes_init_data { # FFL Phase0 int gain aka 2ol SD update rate # PSU_SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN 0x6 - # Fast phase lock controls -- FSM accumulator cycle control and phase 0 int gain control. + # Fast phase lock controls -- FSM accumulator cycle control and phase 0 in + # t gain control. #(OFFSET, MASK, VALUE) (0XFD40DC14, 0x000000FFU ,0x000000E6U) */ mask_write 0XFD40DC14 0x000000FF 0x000000E6 # Register : L3_TM_CDR16 @ 0XFD40DC40

@@ -13336,7 +15546,8 @@ set psu_serdes_init_data { mask_write 0XFD404CC0 0x0000001F 0x00000000 # Register : L1_TX_ANA_TM_18 @ 0XFD404048

- # pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-emphasis, Others: reserved + # pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-em + # phasis, Others: reserved # PSU_SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0 0 # Override for PIPE TX de-emphasis @@ -13344,7 +15555,8 @@ set psu_serdes_init_data { mask_write 0XFD404048 0x000000FF 0x00000000 # Register : L3_TX_ANA_TM_18 @ 0XFD40C048

- # pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-emphasis, Others: reserved + # pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-em + # phasis, Others: reserved # PSU_SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0 0x1 # Override for PIPE TX de-emphasis @@ -13363,24 +15575,7 @@ set psu_resetout_init_data { # Software control register for the LPD block. #(OFFSET, MASK, VALUE) (0XFF5E023C, 0x00000400U ,0x00000000U) */ mask_write 0XFF5E023C 0x00000400 0x00000000 - # : USB0 PIPE POWER PRESENT - # Register : fpd_power_prsnt @ 0XFF9D0080

- - # This bit is used to choose between PIPE power present and 1'b1 - # PSU_USB3_0_FPD_POWER_PRSNT_OPTION 0X1 - - # fpd_power_prsnt - #(OFFSET, MASK, VALUE) (0XFF9D0080, 0x00000001U ,0x00000001U) */ - mask_write 0XFF9D0080 0x00000001 0x00000001 - # Register : fpd_pipe_clk @ 0XFF9D007C

- - # This bit is used to choose between PIPE clock coming from SerDes and the suspend clk - # PSU_USB3_0_FPD_PIPE_CLK_OPTION 0x0 - - # fpd_pipe_clk - #(OFFSET, MASK, VALUE) (0XFF9D007C, 0x00000001U ,0x00000000U) */ - mask_write 0XFF9D007C 0x00000001 0x00000000 - # : + # : HIBERREST # Register : RST_LPD_TOP @ 0XFF5E023C

# USB 0 sleep circuit reset @@ -13407,7 +15602,8 @@ set psu_resetout_init_data { # Sata PM clock control select # PSU_SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL 0x3 - # Misc Contorls for SATA.This register may only be modified during bootup (while SATA block is disabled) + # Misc Contorls for SATA.This register may only be modified during bootup + # (while SATA block is disabled) #(OFFSET, MASK, VALUE) (0XFD3D0100, 0x00000003U ,0x00000003U) */ mask_write 0XFD3D0100 0x00000003 0x00000003 # Register : RST_FPD_TOP @ 0XFD1A0100

@@ -13449,8 +15645,9 @@ set psu_resetout_init_data { mask_write 0XFD4A0200 0x00000002 0x00000000 # Register : DP_TX_PHY_POWER_DOWN @ 0XFD4A0238

- # Two bits per lane. When set to 11, moves the GT to power down mode. When set to 00, GT will be in active state. bits [1:0] - - # ane0 Bits [3:2] - lane 1 + # Two bits per lane. When set to 11, moves the GT to power down mode. When + # set to 00, GT will be in active state. bits [1:0] - lane0 Bits [3:2] - + # lane 1 # PSU_DP_DP_TX_PHY_POWER_DOWN_POWER_DWN 0X0 # Control PHY Power down @@ -13459,96 +15656,194 @@ set psu_resetout_init_data { # : USB0 GFLADJ # Register : GUSB2PHYCFG @ 0XFE20C200

- # USB 2.0 Turnaround Time (USBTrdTim) Sets the turnaround time in PHY clocks. Specifies the response time for a MAC request to - # he Packet FIFO Controller (PFC) to fetch data from the DFIFO (SPRAM). The following are the required values for the minimum S - # C bus frequency of 60 MHz. USB turnaround time is a critical certification criteria when using long cables and five hub level - # . The required values for this field: - 4'h5: When the MAC interface is 16-bit UTMI+. - 4'h9: When the MAC interface is 8-bit - # UTMI+/ULPI. If SoC bus clock is less than 60 MHz, and USB turnaround time is not critical, this field can be set to a larger - # alue. Note: This field is valid only in device mode. + # USB 2.0 Turnaround Time (USBTrdTim) Sets the turnaround time in PHY cloc + # ks. Specifies the response time for a MAC request to the Packet FIFO Con + # troller (PFC) to fetch data from the DFIFO (SPRAM). The following are th + # e required values for the minimum SoC bus frequency of 60 MHz. USB turna + # round time is a critical certification criteria when using long cables a + # nd five hub levels. The required values for this field: - 4'h5: When the + # MAC interface is 16-bit UTMI+. - 4'h9: When the MAC interface is 8-bit + # UTMI+/ULPI. If SoC bus clock is less than 60 MHz, and USB turnaround tim + # e is not critical, this field can be set to a larger value. Note: This f + # ield is valid only in device mode. # PSU_USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM 0x9 - # Transceiver Delay: Enables a delay between the assertion of the UTMI/ULPI Transceiver Select signal (for HS) and the assertio - # of the TxValid signal during a HS Chirp. When this bit is set to 1, a delay (of approximately 2.5 us) is introduced from the - # time when the Transceiver Select is set to 2'b00 (HS) to the time the TxValid is driven to 0 for sending the chirp-K. This de - # ay is required for some UTMI/ULPI PHYs. Note: - If you enable the hibernation feature when the device core comes out of power - # off, you must re-initialize this bit with the appropriate value because the core does not save and restore this bit value dur - # ng hibernation. - This bit is valid only in device mode. + # Transceiver Delay: Enables a delay between the assertion of the UTMI/ULP + # I Transceiver Select signal (for HS) and the assertion of the TxValid si + # gnal during a HS Chirp. When this bit is set to 1, a delay (of approxima + # tely 2.5 us) is introduced from the time when the Transceiver Select is + # set to 2'b00 (HS) to the time the TxValid is driven to 0 for sending the + # chirp-K. This delay is required for some UTMI/ULPI PHYs. Note: - If you + # enable the hibernation feature when the device core comes out of power- + # off, you must re-initialize this bit with the appropriate value because + # the core does not save and restore this bit value during hibernation. - + # This bit is valid only in device mode. # PSU_USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY 0x0 - # Enable utmi_sleep_n and utmi_l1_suspend_n (EnblSlpM) The application uses this bit to control utmi_sleep_n and utmi_l1_suspen - # _n assertion to the PHY in the L1 state. - 1'b0: utmi_sleep_n and utmi_l1_suspend_n assertion from the core is not transferre - # to the external PHY. - 1'b1: utmi_sleep_n and utmi_l1_suspend_n assertion from the core is transferred to the external PHY. - # ote: This bit must be set high for Port0 if PHY is used. Note: In Device mode - Before issuing any device endpoint command wh - # n operating in 2.0 speeds, disable this bit and enable it after the command completes. Without disabling this bit, if a comma - # d is issued when the device is in L1 state and if mac2_clk (utmi_clk/ulpi_clk) is gated off, the command will not get complet - # d. + # Enable utmi_sleep_n and utmi_l1_suspend_n (EnblSlpM) The application use + # s this bit to control utmi_sleep_n and utmi_l1_suspend_n assertion to th + # e PHY in the L1 state. - 1'b0: utmi_sleep_n and utmi_l1_suspend_n assert + # ion from the core is not transferred to the external PHY. - 1'b1: utmi_s + # leep_n and utmi_l1_suspend_n assertion from the core is transferred to t + # he external PHY. Note: This bit must be set high for Port0 if PHY is use + # d. Note: In Device mode - Before issuing any device endpoint command whe + # n operating in 2.0 speeds, disable this bit and enable it after the comm + # and completes. Without disabling this bit, if a command is issued when t + # he device is in L1 state and if mac2_clk (utmi_clk/ulpi_clk) is gated of + # f, the command will not get completed. # PSU_USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM 0x0 - # USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial Transceiver Select The application uses this bit to select a high-speed P - # Y or a full-speed transceiver. - 1'b0: USB 2.0 high-speed UTMI+ or ULPI PHY. This bit is always 0, with Write Only access. - - # 'b1: USB 1.1 full-speed serial transceiver. This bit is always 1, with Write Only access. If both interface types are selecte - # in coreConsultant (that is, parameters' values are not zero), the application uses this bit to select the active interface i - # active, with Read-Write bit access. Note: USB 1.1 full-serial transceiver is not supported. This bit always reads as 1'b0. + # USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial Transceiver Select T + # he application uses this bit to select a high-speed PHY or a full-speed + # transceiver. - 1'b0: USB 2.0 high-speed UTMI+ or ULPI PHY. This bit is a + # lways 0, with Write Only access. - 1'b1: USB 1.1 full-speed serial trans + # ceiver. This bit is always 1, with Write Only access. If both interface + # types are selected in coreConsultant (that is, parameters' values are no + # t zero), the application uses this bit to select the active interface is + # active, with Read-Write bit access. Note: USB 1.1 full-serial transceiv + # er is not supported. This bit always reads as 1'b0. # PSU_USB3_0_XHCI_GUSB2PHYCFG_PHYSEL 0x0 - # Full-Speed Serial Interface Select (FSIntf) The application uses this bit to select a unidirectional or bidirectional USB 1.1 - # full-speed serial transceiver interface. - 1'b0: 6-pin unidirectional full-speed serial interface. This bit is set to 0 with - # ead Only access. - 1'b1: 3-pin bidirectional full-speed serial interface. This bit is set to 0 with Read Only access. Note: U - # B 1.1 full-speed serial interface is not supported. This bit always reads as 1'b0. + # Suspend USB2.0 HS/FS/LS PHY (SusPHY) When set, USB2.0 PHY enters Suspend + # mode if Suspend conditions are valid. For DRD/OTG configurations, it is + # recommended that this bit is set to 0 during coreConsultant configurati + # on. If it is set to 1, then the application must clear this bit after po + # wer-on reset. Application needs to set it to 1 after the core initializa + # tion completes. For all other configurations, this bit can be set to 1 d + # uring core configuration. Note: - In host mode, on reset, this bit is se + # t to 1. Software can override this bit after reset. - In device mode, be + # fore issuing any device endpoint command when operating in 2.0 speeds, d + # isable this bit and enable it after the command completes. If you issue + # a command without disabling this bit when the device is in L2 state and + # if mac2_clk (utmi_clk/ulpi_clk) is gated off, the command will not get c + # ompleted. + # PSU_USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20 0x1 + + # Full-Speed Serial Interface Select (FSIntf) The application uses this bi + # t to select a unidirectional or bidirectional USB 1.1 full-speed serial + # transceiver interface. - 1'b0: 6-pin unidirectional full-speed serial in + # terface. This bit is set to 0 with Read Only access. - 1'b1: 3-pin bidir + # ectional full-speed serial interface. This bit is set to 0 with Read Onl + # y access. Note: USB 1.1 full-speed serial interface is not supported. Th + # is bit always reads as 1'b0. # PSU_USB3_0_XHCI_GUSB2PHYCFG_FSINTF 0x0 - # ULPI or UTMI+ Select (ULPI_UTMI_Sel) The application uses this bit to select a UTMI+ or ULPI Interface. - 1'b0: UTMI+ Interfa - # e - 1'b1: ULPI Interface This bit is writable only if UTMI+ and ULPI is specified for High-Speed PHY Interface(s) in coreCons - # ltant configuration (DWC_USB3_HSPHY_INTERFACE = 3). Otherwise, this bit is read-only and the value depends on the interface s - # lected through DWC_USB3_HSPHY_INTERFACE. + # ULPI or UTMI+ Select (ULPI_UTMI_Sel) The application uses this bit to se + # lect a UTMI+ or ULPI Interface. - 1'b0: UTMI+ Interface - 1'b1: ULPI Int + # erface This bit is writable only if UTMI+ and ULPI is specified for High + # -Speed PHY Interface(s) in coreConsultant configuration (DWC_USB3_HSPHY_ + # INTERFACE = 3). Otherwise, this bit is read-only and the value depends o + # n the interface selected through DWC_USB3_HSPHY_INTERFACE. # PSU_USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL 0x1 - # PHY Interface (PHYIf) If UTMI+ is selected, the application uses this bit to configure the core to support a UTMI+ PHY with a - # 8- or 16-bit interface. - 1'b0: 8 bits - 1'b1: 16 bits ULPI Mode: 1'b0 Note: - All the enabled 2.0 ports must have the same - # lock frequency as Port0 clock frequency (utmi_clk[0]). - The UTMI 8-bit and 16-bit modes cannot be used together for differen - # ports at the same time (that is, all the ports must be in 8-bit mode, or all of them must be in 16-bit mode, at a time). - I - # any of the USB 2.0 ports is selected as ULPI port for operation, then all the USB 2.0 ports must be operating at 60 MHz. + # PHY Interface (PHYIf) If UTMI+ is selected, the application uses this bi + # t to configure the core to support a UTMI+ PHY with an 8- or 16-bit inte + # rface. - 1'b0: 8 bits - 1'b1: 16 bits ULPI Mode: 1'b0 Note: - All the en + # abled 2.0 ports must have the same clock frequency as Port0 clock freque + # ncy (utmi_clk[0]). - The UTMI 8-bit and 16-bit modes cannot be used toge + # ther for different ports at the same time (that is, all the ports must b + # e in 8-bit mode, or all of them must be in 16-bit mode, at a time). - If + # any of the USB 2.0 ports is selected as ULPI port for operation, then a + # ll the USB 2.0 ports must be operating at 60 MHz. # PSU_USB3_0_XHCI_GUSB2PHYCFG_PHYIF 0x0 - # HS/FS Timeout Calibration (TOutCal) The number of PHY clocks, as indicated by the application in this field, is multiplied by - # a bit-time factor; this factor is added to the high-speed/full-speed interpacket timeout duration in the core to account for - # dditional delays introduced by the PHY. This may be required, since the delay introduced by the PHY in generating the linesta - # e condition may vary among PHYs. The USB standard timeout value for high-speed operation is 736 to 816 (inclusive) bit times. - # The USB standard timeout value for full-speed operation is 16 to 18 (inclusive) bit times. The application must program this - # ield based on the speed of connection. The number of bit times added per PHY clock are: High-speed operation: - One 30-MHz PH - # clock = 16 bit times - One 60-MHz PHY clock = 8 bit times Full-speed operation: - One 30-MHz PHY clock = 0.4 bit times - One - # 60-MHz PHY clock = 0.2 bit times - One 48-MHz PHY clock = 0.25 bit times + # HS/FS Timeout Calibration (TOutCal) The number of PHY clocks, as indicat + # ed by the application in this field, is multiplied by a bit-time factor; + # this factor is added to the high-speed/full-speed interpacket timeout d + # uration in the core to account for additional delays introduced by the P + # HY. This may be required, since the delay introduced by the PHY in gener + # ating the linestate condition may vary among PHYs. The USB standard time + # out value for high-speed operation is 736 to 816 (inclusive) bit times. + # The USB standard timeout value for full-speed operation is 16 to 18 (inc + # lusive) bit times. The application must program this field based on the + # speed of connection. The number of bit times added per PHY clock are: Hi + # gh-speed operation: - One 30-MHz PHY clock = 16 bit times - One 60-MHz P + # HY clock = 8 bit times Full-speed operation: - One 30-MHz PHY clock = 0. + # 4 bit times - One 60-MHz PHY clock = 0.2 bit times - One 48-MHz PHY cloc + # k = 0.25 bit times # PSU_USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL 0x7 - # Global USB2 PHY Configuration Register The application must program this register before starting any transactions on either - # he SoC bus or the USB. In Device-only configurations, only one register is needed. In Host mode, per-port registers are imple - # ented. - #(OFFSET, MASK, VALUE) (0XFE20C200, 0x00003FBFU ,0x00002417U) */ - mask_write 0XFE20C200 0x00003FBF 0x00002417 + # ULPI External VBUS Drive (ULPIExtVbusDrv) Selects supply source to drive + # 5V on VBUS, in the ULPI PHY. - 1'b0: PHY drives VBUS with internal char + # ge pump (default). - 1'b1: PHY drives VBUS with an external supply. (Onl + # y when RTL parameter DWC_USB3_HSPHY_INTERFACE = 2 or 3) + # PSU_USB3_0_XHCI_GUSB2PHYCFG_ULPIEXTVBUSDRV 0x1 + + # Global USB2 PHY Configuration Register The application must program this + # register before starting any transactions on either the SoC bus or the + # USB. In Device-only configurations, only one register is needed. In Host + # mode, per-port registers are implemented. + #(OFFSET, MASK, VALUE) (0XFE20C200, 0x00023FFFU ,0x00022457U) */ + mask_write 0XFE20C200 0x00023FFF 0x00022457 # Register : GFLADJ @ 0XFE20C630

- # This field indicates the frame length adjustment to be applied when SOF/ITP counter is running on the ref_clk. This register - # alue is used to adjust the ITP interval when GCTL[SOFITPSYNC] is set to '1'; SOF and ITP interval when GLADJ.GFLADJ_REFCLK_LP - # _SEL is set to '1'. This field must be programmed to a non-zero value only if GFLADJ_REFCLK_LPM_SEL is set to '1' or GCTL.SOF - # TPSYNC is set to '1'. The value is derived as follows: FLADJ_REF_CLK_FLADJ=((125000/ref_clk_period_integer)-(125000/ref_clk_p - # riod)) * ref_clk_period where - the ref_clk_period_integer is the integer value of the ref_clk period got by truncating the d - # cimal (fractional) value that is programmed in the GUCTL.REF_CLK_PERIOD field. - the ref_clk_period is the ref_clk period inc - # uding the fractional value. Examples: If the ref_clk is 24 MHz then - GUCTL.REF_CLK_PERIOD = 41 - GFLADJ.GLADJ_REFCLK_FLADJ = - # ((125000/41)-(125000/41.6666))*41.6666 = 2032 (ignoring the fractional value) If the ref_clk is 48 MHz then - GUCTL.REF_CLK_P - # RIOD = 20 - GFLADJ.GLADJ_REFCLK_FLADJ = ((125000/20)-(125000/20.8333))*20.8333 = 5208 (ignoring the fractional value) + # This field indicates the frame length adjustment to be applied when SOF/ + # ITP counter is running on the ref_clk. This register value is used to ad + # just the ITP interval when GCTL[SOFITPSYNC] is set to '1'; SOF and ITP i + # nterval when GLADJ.GFLADJ_REFCLK_LPM_SEL is set to '1'. This field must + # be programmed to a non-zero value only if GFLADJ_REFCLK_LPM_SEL is set t + # o '1' or GCTL.SOFITPSYNC is set to '1'. The value is derived as follows: + # FLADJ_REF_CLK_FLADJ=((125000/ref_clk_period_integer)-(125000/ref_clk_pe + # riod)) * ref_clk_period where - the ref_clk_period_integer is the intege + # r value of the ref_clk period got by truncating the decimal (fractional) + # value that is programmed in the GUCTL.REF_CLK_PERIOD field. - the ref_c + # lk_period is the ref_clk period including the fractional value. Examples + # : If the ref_clk is 24 MHz then - GUCTL.REF_CLK_PERIOD = 41 - GFLADJ.GLA + # DJ_REFCLK_FLADJ = ((125000/41)-(125000/41.6666))*41.6666 = 2032 (ignorin + # g the fractional value) If the ref_clk is 48 MHz then - GUCTL.REF_CLK_PE + # RIOD = 20 - GFLADJ.GLADJ_REFCLK_FLADJ = ((125000/20)-(125000/20.8333))*2 + # 0.8333 = 5208 (ignoring the fractional value) # PSU_USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ 0x0 - # Global Frame Length Adjustment Register This register provides options for the software to control the core behavior with res - # ect to SOF (Start of Frame) and ITP (Isochronous Timestamp Packet) timers and frame timer functionality. It provides an optio - # to override the fladj_30mhz_reg sideband signal. In addition, it enables running SOF or ITP frame timer counters completely - # rom the ref_clk. This facilitates hardware LPM in host mode with the SOF or ITP counters being run from the ref_clk signal. + # Global Frame Length Adjustment Register This register provides options f + # or the software to control the core behavior with respect to SOF (Start + # of Frame) and ITP (Isochronous Timestamp Packet) timers and frame timer + # functionality. It provides an option to override the fladj_30mhz_reg sid + # eband signal. In addition, it enables running SOF or ITP frame timer cou + # nters completely from the ref_clk. This facilitates hardware LPM in host + # mode with the SOF or ITP counters being run from the ref_clk signal. #(OFFSET, MASK, VALUE) (0XFE20C630, 0x003FFF00U ,0x00000000U) */ mask_write 0XFE20C630 0x003FFF00 0x00000000 + # Register : GUCTL1 @ 0XFE20C11C

+ + # When this bit is set to '0', termsel, xcvrsel will become 0 during end o + # f resume while the opmode will become 0 once controller completes end of + # resume and enters U0 state (2 separate commandswill be issued). When th + # is bit is set to '1', all the termsel, xcvrsel, opmode becomes 0 during + # end of resume itself (only 1 command will be issued) + # PSU_USB3_0_XHCI_GUCTL1_RESUME_TERMSEL_XCVRSEL_UNIFY 0x1 + + # Reserved + # PSU_USB3_0_XHCI_GUCTL1_RESERVED_9 0x1 + + # Global User Control Register 1 + #(OFFSET, MASK, VALUE) (0XFE20C11C, 0x00000600U ,0x00000600U) */ + mask_write 0XFE20C11C 0x00000600 0x00000600 + # Register : GUCTL @ 0XFE20C12C

+ + # Host IN Auto Retry (USBHstInAutoRetryEn) When set, this field enables th + # e Auto Retry feature. For IN transfers (non-isochronous) that encounter + # data packets with CRC errors or internal overrun scenarios, the auto ret + # ry feature causes the Host core to reply to the device with a non-termin + # ating retry ACK (that is, an ACK transaction packet with Retry = 1 and N + # umP != 0). If the Auto Retry feature is disabled (default), the core wil + # l respond with a terminating retry ACK (that is, an ACK transaction pack + # et with Retry = 1 and NumP = 0). - 1'b0: Auto Retry Disabled - 1'b1: Aut + # o Retry Enabled Note: This bit is also applicable to the device mode. + # PSU_USB3_0_XHCI_GUCTL_USBHSTINAUTORETRYEN 0x1 + + # Global User Control Register: This register provides a few options for t + # he software to control the core behavior in the Host mode. Most of the o + # ptions are used to improve host inter-operability with different devices + # . + #(OFFSET, MASK, VALUE) (0XFE20C12C, 0x00004000U ,0x00004000U) */ + mask_write 0XFE20C12C 0x00004000 0x00004000 # : UPDATING TWO PCIE REGISTERS DEFAULT VALUES, AS THESE REGISTERS HAVE INCORRECT RESET VALUES IN SILICON. # Register : ATTR_25 @ 0XFD480064

- # If TRUE Completion Timeout Disable is supported. This is required to be TRUE for Endpoint and either setting allowed for Root - # ports. Drives Device Capability 2 [4]; EP=0x0001; RP=0x0001 + # If TRUE Completion Timeout Disable is supported. This is required to be + # TRUE for Endpoint and either setting allowed for Root ports. Drives Devi + # ce Capability 2 [4]; EP=0x0001; RP=0x0001 # PSU_PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED 0X1 # ATTR_25 @@ -13557,12 +15852,16 @@ set psu_resetout_init_data { # : PCIE SETTINGS # Register : ATTR_7 @ 0XFD48001C

- # Specifies mask/settings for Base Address Register (BAR) 0. If BAR is not to be implemented, set to 32'h00000000. Bits are def - # ned as follows: Memory Space BAR [0] = Mem Space Indicator (set to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = - # Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory a - # erture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR1,BAR0\'7d to 1. IO Space BAR 0] = IO Space Indicator - # set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o apert - # re size in bytes.; EP=0x0004; RP=0x0000 + # Specifies mask/settings for Base Address Register (BAR) 0. If BAR is not + # to be implemented, set to 32'h00000000. Bits are defined as follows: Me + # mory Space BAR [0] = Mem Space Indicator (set to 0) [2:1] = Type field ( + # 10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask + # for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to 1, w + # here 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63: + # n bits of \'7bBAR1,BAR0\'7d to 1. IO Space BAR 0] = IO Space Indicator ( + # set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of B + # AR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; + # EP=0x0004; RP=0x0000 # PSU_PCIE_ATTRIB_ATTR_7_ATTR_BAR0 0x0 # ATTR_7 @@ -13570,12 +15869,16 @@ set psu_resetout_init_data { mask_write 0XFD48001C 0x0000FFFF 0x00000000 # Register : ATTR_8 @ 0XFD480020

- # Specifies mask/settings for Base Address Register (BAR) 0. If BAR is not to be implemented, set to 32'h00000000. Bits are def - # ned as follows: Memory Space BAR [0] = Mem Space Indicator (set to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = - # Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory a - # erture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR1,BAR0\'7d to 1. IO Space BAR 0] = IO Space Indicator - # set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o apert - # re size in bytes.; EP=0xFFF0; RP=0x0000 + # Specifies mask/settings for Base Address Register (BAR) 0. If BAR is not + # to be implemented, set to 32'h00000000. Bits are defined as follows: Me + # mory Space BAR [0] = Mem Space Indicator (set to 0) [2:1] = Type field ( + # 10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask + # for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to 1, w + # here 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63: + # n bits of \'7bBAR1,BAR0\'7d to 1. IO Space BAR 0] = IO Space Indicator ( + # set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of B + # AR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; + # EP=0xFFF0; RP=0x0000 # PSU_PCIE_ATTRIB_ATTR_8_ATTR_BAR0 0x0 # ATTR_8 @@ -13583,13 +15886,18 @@ set psu_resetout_init_data { mask_write 0XFD480020 0x0000FFFF 0x00000000 # Register : ATTR_9 @ 0XFD480024

- # Specifies mask/settings for Base Address Register (BAR) 1 if BAR0 is a 32-bit BAR, or the upper bits of \'7bBAR1,BAR0\'7d if - # AR0 is a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR0 description if this functions as the uppe - # bits of a 64-bit BAR. Bits are defined as follows: Memory Space BAR (not upper bits of BAR0) [0] = Mem Space Indicator (set - # o 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if - # 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of - # '7bBAR2,BAR1\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable b - # ts of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000 + # Specifies mask/settings for Base Address Register (BAR) 1 if BAR0 is a 3 + # 2-bit BAR, or the upper bits of \'7bBAR1,BAR0\'7d if BAR0 is a 64-bit BA + # R. If BAR is not to be implemented, set to 32'h00000000. See BAR0 descri + # ption if this functions as the upper bits of a 64-bit BAR. Bits are defi + # ned as follows: Memory Space BAR (not upper bits of BAR0) [0] = Mem Spac + # e Indicator (set to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) + # [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if + # 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size + # in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR2,BAR1\'7d t + # o 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set + # to 0) [31:2] = Mask for writable bits of BAR; set uppermost 31:n bits t + # o 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000 # PSU_PCIE_ATTRIB_ATTR_9_ATTR_BAR1 0x0 # ATTR_9 @@ -13597,13 +15905,18 @@ set psu_resetout_init_data { mask_write 0XFD480024 0x0000FFFF 0x00000000 # Register : ATTR_10 @ 0XFD480028

- # Specifies mask/settings for Base Address Register (BAR) 1 if BAR0 is a 32-bit BAR, or the upper bits of \'7bBAR1,BAR0\'7d if - # AR0 is a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR0 description if this functions as the uppe - # bits of a 64-bit BAR. Bits are defined as follows: Memory Space BAR (not upper bits of BAR0) [0] = Mem Space Indicator (set - # o 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if - # 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of - # '7bBAR2,BAR1\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable b - # ts of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000 + # Specifies mask/settings for Base Address Register (BAR) 1 if BAR0 is a 3 + # 2-bit BAR, or the upper bits of \'7bBAR1,BAR0\'7d if BAR0 is a 64-bit BA + # R. If BAR is not to be implemented, set to 32'h00000000. See BAR0 descri + # ption if this functions as the upper bits of a 64-bit BAR. Bits are defi + # ned as follows: Memory Space BAR (not upper bits of BAR0) [0] = Mem Spac + # e Indicator (set to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) + # [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if + # 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size + # in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR2,BAR1\'7d t + # o 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set + # to 0) [31:2] = Mask for writable bits of BAR; set uppermost 31:n bits t + # o 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000 # PSU_PCIE_ATTRIB_ATTR_10_ATTR_BAR1 0x0 # ATTR_10 @@ -13611,14 +15924,20 @@ set psu_resetout_init_data { mask_write 0XFD480028 0x0000FFFF 0x00000000 # Register : ATTR_11 @ 0XFD48002C

- # For an endpoint, specifies mask/settings for Base Address Register (BAR) 2 if BAR1 is a 32-bit BAR, or the upper bits of \'7b - # AR2,BAR1\'7d if BAR1 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR1 descri - # tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to 00FF_FFFF. For an endpoin - # , bits are defined as follows: Memory Space BAR (not upper bits of BAR1) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi - # ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe - # most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR3,BAR2\'7d to - # . IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper - # ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0x0004; RP=0xFFFF + # For an endpoint, specifies mask/settings for Base Address Register (BAR) + # 2 if BAR1 is a 32-bit BAR, or the upper bits of \'7bBAR2,BAR1\'7d if BA + # R1 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + # et to 32'h00000000. See BAR1 description if this functions as the upper + # bits of a 64-bit BAR. For a switch or root: This must be set to 00FF_FFF + # F. For an endpoint, bits are defined as follows: Memory Space BAR (not u + # pper bits of BAR1) [0] = Mem Space Indicator (set to 0) [2:1] = Type fie + # ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = M + # ask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to + # 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost + # 63:n bits of \'7bBAR3,BAR2\'7d to 1. IO Space BAR 0] = IO Space Indicat + # or (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits + # of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in byt + # es.; EP=0x0004; RP=0xFFFF # PSU_PCIE_ATTRIB_ATTR_11_ATTR_BAR2 0xFFFF # ATTR_11 @@ -13626,14 +15945,20 @@ set psu_resetout_init_data { mask_write 0XFD48002C 0x0000FFFF 0x0000FFFF # Register : ATTR_12 @ 0XFD480030

- # For an endpoint, specifies mask/settings for Base Address Register (BAR) 2 if BAR1 is a 32-bit BAR, or the upper bits of \'7b - # AR2,BAR1\'7d if BAR1 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR1 descri - # tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to 00FF_FFFF. For an endpoin - # , bits are defined as follows: Memory Space BAR (not upper bits of BAR1) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi - # ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe - # most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR3,BAR2\'7d to - # . IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper - # ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFF0; RP=0x00FF + # For an endpoint, specifies mask/settings for Base Address Register (BAR) + # 2 if BAR1 is a 32-bit BAR, or the upper bits of \'7bBAR2,BAR1\'7d if BA + # R1 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + # et to 32'h00000000. See BAR1 description if this functions as the upper + # bits of a 64-bit BAR. For a switch or root: This must be set to 00FF_FFF + # F. For an endpoint, bits are defined as follows: Memory Space BAR (not u + # pper bits of BAR1) [0] = Mem Space Indicator (set to 0) [2:1] = Type fie + # ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = M + # ask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to + # 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost + # 63:n bits of \'7bBAR3,BAR2\'7d to 1. IO Space BAR 0] = IO Space Indicat + # or (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits + # of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in byt + # es.; EP=0xFFF0; RP=0x00FF # PSU_PCIE_ATTRIB_ATTR_12_ATTR_BAR2 0xFF # ATTR_12 @@ -13641,15 +15966,22 @@ set psu_resetout_init_data { mask_write 0XFD480030 0x0000FFFF 0x000000FF # Register : ATTR_13 @ 0XFD480034

- # For an endpoint, specifies mask/settings for Base Address Register (BAR) 3 if BAR2 is a 32-bit BAR, or the upper bits of \'7b - # AR3,BAR2\'7d if BAR2 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR2 descri - # tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: FFFF_0000 = IO Limit/Bas - # Registers not implemented FFFF_F0F0 = IO Limit/Base Registers use 16-bit decode FFFF_F1F1 = IO Limit/Base Registers use 32-b - # t decode For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of BAR2) [0] = Mem Space Indicator (s - # t to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; - # if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits - # f \'7bBAR4,BAR3\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writabl - # bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000 + # For an endpoint, specifies mask/settings for Base Address Register (BAR) + # 3 if BAR2 is a 32-bit BAR, or the upper bits of \'7bBAR3,BAR2\'7d if BA + # R2 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + # et to 32'h00000000. See BAR2 description if this functions as the upper + # bits of a 64-bit BAR. For a switch or root, this must be set to: FFFF_00 + # 00 = IO Limit/Base Registers not implemented FFFF_F0F0 = IO Limit/Base R + # egisters use 16-bit decode FFFF_F1F1 = IO Limit/Base Registers use 32-bi + # t decode For an endpoint, bits are defined as follows: Memory Space BAR + # (not upper bits of BAR2) [0] = Mem Space Indicator (set to 0) [2:1] = Ty + # pe field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31: + # 4] = Mask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bi + # ts to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set upp + # ermost 63:n bits of \'7bBAR4,BAR3\'7d to 1. IO Space BAR 0] = IO Space I + # ndicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable + # bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size + # in bytes.; EP=0xFFFF; RP=0x0000 # PSU_PCIE_ATTRIB_ATTR_13_ATTR_BAR3 0x0 # ATTR_13 @@ -13657,15 +15989,22 @@ set psu_resetout_init_data { mask_write 0XFD480034 0x0000FFFF 0x00000000 # Register : ATTR_14 @ 0XFD480038

- # For an endpoint, specifies mask/settings for Base Address Register (BAR) 3 if BAR2 is a 32-bit BAR, or the upper bits of \'7b - # AR3,BAR2\'7d if BAR2 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR2 descri - # tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: FFFF_0000 = IO Limit/Bas - # Registers not implemented FFFF_F0F0 = IO Limit/Base Registers use 16-bit decode FFFF_F1F1 = IO Limit/Base Registers use 32-b - # t decode For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of BAR2) [0] = Mem Space Indicator (s - # t to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; - # if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits - # f \'7bBAR4,BAR3\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writabl - # bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0xFFFF + # For an endpoint, specifies mask/settings for Base Address Register (BAR) + # 3 if BAR2 is a 32-bit BAR, or the upper bits of \'7bBAR3,BAR2\'7d if BA + # R2 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + # et to 32'h00000000. See BAR2 description if this functions as the upper + # bits of a 64-bit BAR. For a switch or root, this must be set to: FFFF_00 + # 00 = IO Limit/Base Registers not implemented FFFF_F0F0 = IO Limit/Base R + # egisters use 16-bit decode FFFF_F1F1 = IO Limit/Base Registers use 32-bi + # t decode For an endpoint, bits are defined as follows: Memory Space BAR + # (not upper bits of BAR2) [0] = Mem Space Indicator (set to 0) [2:1] = Ty + # pe field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31: + # 4] = Mask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bi + # ts to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set upp + # ermost 63:n bits of \'7bBAR4,BAR3\'7d to 1. IO Space BAR 0] = IO Space I + # ndicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable + # bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size + # in bytes.; EP=0xFFFF; RP=0xFFFF # PSU_PCIE_ATTRIB_ATTR_14_ATTR_BAR3 0xFFFF # ATTR_14 @@ -13673,14 +16012,20 @@ set psu_resetout_init_data { mask_write 0XFD480038 0x0000FFFF 0x0000FFFF # Register : ATTR_15 @ 0XFD48003C

- # For an endpoint, specifies mask/settings for Base Address Register (BAR) 4 if BAR3 is a 32-bit BAR, or the upper bits of \'7b - # AR4,BAR3\'7d if BAR3 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR3 descri - # tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to FFF0_FFF0. For an endpoin - # , bits are defined as follows: Memory Space BAR (not upper bits of BAR3) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi - # ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe - # most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR5,BAR4\'7d to - # . IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper - # ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0x0004; RP=0xFFF0 + # For an endpoint, specifies mask/settings for Base Address Register (BAR) + # 4 if BAR3 is a 32-bit BAR, or the upper bits of \'7bBAR4,BAR3\'7d if BA + # R3 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + # et to 32'h00000000. See BAR3 description if this functions as the upper + # bits of a 64-bit BAR. For a switch or root: This must be set to FFF0_FFF + # 0. For an endpoint, bits are defined as follows: Memory Space BAR (not u + # pper bits of BAR3) [0] = Mem Space Indicator (set to 0) [2:1] = Type fie + # ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = M + # ask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to + # 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost + # 63:n bits of \'7bBAR5,BAR4\'7d to 1. IO Space BAR 0] = IO Space Indicat + # or (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits + # of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in byt + # es.; EP=0x0004; RP=0xFFF0 # PSU_PCIE_ATTRIB_ATTR_15_ATTR_BAR4 0xFFF0 # ATTR_15 @@ -13688,14 +16033,20 @@ set psu_resetout_init_data { mask_write 0XFD48003C 0x0000FFFF 0x0000FFF0 # Register : ATTR_16 @ 0XFD480040

- # For an endpoint, specifies mask/settings for Base Address Register (BAR) 4 if BAR3 is a 32-bit BAR, or the upper bits of \'7b - # AR4,BAR3\'7d if BAR3 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR3 descri - # tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to FFF0_FFF0. For an endpoin - # , bits are defined as follows: Memory Space BAR (not upper bits of BAR3) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi - # ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe - # most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR5,BAR4\'7d to - # . IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper - # ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFF0; RP=0xFFF0 + # For an endpoint, specifies mask/settings for Base Address Register (BAR) + # 4 if BAR3 is a 32-bit BAR, or the upper bits of \'7bBAR4,BAR3\'7d if BA + # R3 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + # et to 32'h00000000. See BAR3 description if this functions as the upper + # bits of a 64-bit BAR. For a switch or root: This must be set to FFF0_FFF + # 0. For an endpoint, bits are defined as follows: Memory Space BAR (not u + # pper bits of BAR3) [0] = Mem Space Indicator (set to 0) [2:1] = Type fie + # ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = M + # ask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to + # 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost + # 63:n bits of \'7bBAR5,BAR4\'7d to 1. IO Space BAR 0] = IO Space Indicat + # or (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits + # of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in byt + # es.; EP=0xFFF0; RP=0xFFF0 # PSU_PCIE_ATTRIB_ATTR_16_ATTR_BAR4 0xFFF0 # ATTR_16 @@ -13703,15 +16054,22 @@ set psu_resetout_init_data { mask_write 0XFD480040 0x0000FFFF 0x0000FFF0 # Register : ATTR_17 @ 0XFD480044

- # For an endpoint, specifies mask/settings for Base Address Register (BAR) 5 if BAR4 is a 32-bit BAR, or the upper bits of \'7b - # AR5,BAR4\'7d if BAR4 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR4 descri - # tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: 0000_0000 = Prefetchable - # Memory Limit/Base Registers not implemented FFF0_FFF0 = 32-bit Prefetchable Memory Limit/Base implemented FFF1_FFF1 = 64-bit - # refetchable Memory Limit/Base implemented For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of B - # R4) [0] = Mem Space Indicator (set to 0) [2:1] = Type field (00 for 32-bit; BAR5 cannot be lower part of a 64-bit BAR) [3] = - # refetchable (0 or 1) [31:4] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=memory aperture size in - # ytes. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set u - # permost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0xFFF1 + # For an endpoint, specifies mask/settings for Base Address Register (BAR) + # 5 if BAR4 is a 32-bit BAR, or the upper bits of \'7bBAR5,BAR4\'7d if BA + # R4 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + # et to 32'h00000000. See BAR4 description if this functions as the upper + # bits of a 64-bit BAR. For a switch or root, this must be set to: 0000_00 + # 00 = Prefetchable Memory Limit/Base Registers not implemented FFF0_FFF0 + # = 32-bit Prefetchable Memory Limit/Base implemented FFF1_FFF1 = 64-bit P + # refetchable Memory Limit/Base implemented For an endpoint, bits are defi + # ned as follows: Memory Space BAR (not upper bits of BAR4) [0] = Mem Spac + # e Indicator (set to 0) [2:1] = Type field (00 for 32-bit; BAR5 cannot be + # lower part of a 64-bit BAR) [3] = Prefetchable (0 or 1) [31:4] = Mask f + # or writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=memory + # aperture size in bytes. IO Space BAR 0] = IO Space Indicator (set to 1) + # [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set up + # permost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF + # ; RP=0xFFF1 # PSU_PCIE_ATTRIB_ATTR_17_ATTR_BAR5 0xFFF1 # ATTR_17 @@ -13719,15 +16077,22 @@ set psu_resetout_init_data { mask_write 0XFD480044 0x0000FFFF 0x0000FFF1 # Register : ATTR_18 @ 0XFD480048

- # For an endpoint, specifies mask/settings for Base Address Register (BAR) 5 if BAR4 is a 32-bit BAR, or the upper bits of \'7b - # AR5,BAR4\'7d if BAR4 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR4 descri - # tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: 0000_0000 = Prefetchable - # Memory Limit/Base Registers not implemented FFF0_FFF0 = 32-bit Prefetchable Memory Limit/Base implemented FFF1_FFF1 = 64-bit - # refetchable Memory Limit/Base implemented For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of B - # R4) [0] = Mem Space Indicator (set to 0) [2:1] = Type field (00 for 32-bit; BAR5 cannot be lower part of a 64-bit BAR) [3] = - # refetchable (0 or 1) [31:4] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=memory aperture size in - # ytes. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set u - # permost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0xFFF1 + # For an endpoint, specifies mask/settings for Base Address Register (BAR) + # 5 if BAR4 is a 32-bit BAR, or the upper bits of \'7bBAR5,BAR4\'7d if BA + # R4 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + # et to 32'h00000000. See BAR4 description if this functions as the upper + # bits of a 64-bit BAR. For a switch or root, this must be set to: 0000_00 + # 00 = Prefetchable Memory Limit/Base Registers not implemented FFF0_FFF0 + # = 32-bit Prefetchable Memory Limit/Base implemented FFF1_FFF1 = 64-bit P + # refetchable Memory Limit/Base implemented For an endpoint, bits are defi + # ned as follows: Memory Space BAR (not upper bits of BAR4) [0] = Mem Spac + # e Indicator (set to 0) [2:1] = Type field (00 for 32-bit; BAR5 cannot be + # lower part of a 64-bit BAR) [3] = Prefetchable (0 or 1) [31:4] = Mask f + # or writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=memory + # aperture size in bytes. IO Space BAR 0] = IO Space Indicator (set to 1) + # [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set up + # permost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF + # ; RP=0xFFF1 # PSU_PCIE_ATTRIB_ATTR_18_ATTR_BAR5 0xFFF1 # ATTR_18 @@ -13735,13 +16100,17 @@ set psu_resetout_init_data { mask_write 0XFD480048 0x0000FFFF 0x0000FFF1 # Register : ATTR_27 @ 0XFD48006C

- # Specifies maximum payload supported. Valid settings are: 0- 128 bytes, 1- 256 bytes, 2- 512 bytes, 3- 1024 bytes. Transferred - # to the Device Capabilities register. The values: 4-2048 bytes, 5- 4096 bytes are not supported; EP=0x0001; RP=0x0001 + # Specifies maximum payload supported. Valid settings are: 0- 128 bytes, 1 + # - 256 bytes, 2- 512 bytes, 3- 1024 bytes. Transferred to the Device Capa + # bilities register. The values: 4-2048 bytes, 5- 4096 bytes are not suppo + # rted; EP=0x0001; RP=0x0001 # PSU_PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED 1 - # Endpoint L1 Acceptable Latency. Records the latency that the endpoint can withstand on transitions from L1 state to L0 (if L1 - # state supported). Valid settings are: 0h less than 1us, 1h 1 to 2us, 2h 2 to 4us, 3h 4 to 8us, 4h 8 to 16us, 5h 16 to 32us, 6 - # 32 to 64us, 7h more than 64us. For Endpoints only. Must be 0h for other devices.; EP=0x0007; RP=0x0000 + # Endpoint L1 Acceptable Latency. Records the latency that the endpoint ca + # n withstand on transitions from L1 state to L0 (if L1 state supported). + # Valid settings are: 0h less than 1us, 1h 1 to 2us, 2h 2 to 4us, 3h 4 to + # 8us, 4h 8 to 16us, 5h 16 to 32us, 6h 32 to 64us, 7h more than 64us. For + # Endpoints only. Must be 0h for other devices.; EP=0x0007; RP=0x0000 # PSU_PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY 0x0 # ATTR_27 @@ -13749,14 +16118,18 @@ set psu_resetout_init_data { mask_write 0XFD48006C 0x00000738 0x00000100 # Register : ATTR_50 @ 0XFD4800C8

- # Identifies the type of device/port as follows: 0000b PCI Express Endpoint device, 0001b Legacy PCI Express Endpoint device, 0 - # 00b Root Port of PCI Express Root Complex, 0101b Upstream Port of PCI Express Switch, 0110b Downstream Port of PCI Express Sw - # tch, 0111b PCIE Express to PCI/PCI-X Bridge, 1000b PCI/PCI-X to PCI Express Bridge. Transferred to PCI Express Capabilities r - # gister. Must be consistent with IS_SWITCH and UPSTREAM_FACING settings.; EP=0x0000; RP=0x0004 + # Identifies the type of device/port as follows: 0000b PCI Express Endpoin + # t device, 0001b Legacy PCI Express Endpoint device, 0100b Root Port of P + # CI Express Root Complex, 0101b Upstream Port of PCI Express Switch, 0110 + # b Downstream Port of PCI Express Switch, 0111b PCIE Express to PCI/PCI-X + # Bridge, 1000b PCI/PCI-X to PCI Express Bridge. Transferred to PCI Expre + # ss Capabilities register. Must be consistent with IS_SWITCH and UPSTREAM + # _FACING settings.; EP=0x0000; RP=0x0004 # PSU_PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE 4 - # PCIe Capability's Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capab - # lity.; EP=0x009C; RP=0x0000 + # PCIe Capability's Next Capability Offset pointer to the next item in the + # capabilities list, or 00h if this is the final capability.; EP=0x009C; + # RP=0x0000 # PSU_PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR 0 # ATTR_50 @@ -13764,8 +16137,9 @@ set psu_resetout_init_data { mask_write 0XFD4800C8 0x0000FFF0 0x00000040 # Register : ATTR_105 @ 0XFD4801A4

- # Number of credits that should be advertised for Completion data received on Virtual Channel 0. The bytes advertised must be l - # ss than or equal to the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0172; RP=0x00CD + # Number of credits that should be advertised for Completion data received + # on Virtual Channel 0. The bytes advertised must be less than or equal t + # o the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0172; RP=0x00CD # PSU_PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD 0xCD # ATTR_105 @@ -13773,13 +16147,16 @@ set psu_resetout_init_data { mask_write 0XFD4801A4 0x000007FF 0x000000CD # Register : ATTR_106 @ 0XFD4801A8

- # Number of credits that should be advertised for Completion headers received on Virtual Channel 0. The sum of the posted, non - # osted, and completion header credits must be <= 80; EP=0x0048; RP=0x0024 + # Number of credits that should be advertised for Completion headers recei + # ved on Virtual Channel 0. The sum of the posted, non posted, and complet + # ion header credits must be <= 80; EP=0x0048; RP=0x0024 # PSU_PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH 0x24 - # Number of credits that should be advertised for Non-Posted headers received on Virtual Channel 0. The number of non posted da - # a credits advertised by the block is equal to the number of non posted header credits. The sum of the posted, non posted, and - # completion header credits must be <= 80; EP=0x0004; RP=0x000C + # Number of credits that should be advertised for Non-Posted headers recei + # ved on Virtual Channel 0. The number of non posted data credits advertis + # ed by the block is equal to the number of non posted header credits. The + # sum of the posted, non posted, and completion header credits must be <= + # 80; EP=0x0004; RP=0x000C # PSU_PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH 0xC # ATTR_106 @@ -13787,10 +16164,13 @@ set psu_resetout_init_data { mask_write 0XFD4801A8 0x00003FFF 0x00000624 # Register : ATTR_107 @ 0XFD4801AC

- # Number of credits that should be advertised for Non-Posted data received on Virtual Channel 0. The number of non posted data - # redits advertised by the block is equal to two times the number of non posted header credits if atomic operations are support - # d or is equal to the number of non posted header credits if atomic operations are not supported. The bytes advertised must be - # less than or equal to the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0008; RP=0x0018 + # Number of credits that should be advertised for Non-Posted data received + # on Virtual Channel 0. The number of non posted data credits advertised + # by the block is equal to two times the number of non posted header credi + # ts if atomic operations are supported or is equal to the number of non p + # osted header credits if atomic operations are not supported. The bytes a + # dvertised must be less than or equal to the bram bytes available. See VC + # 0_RX_RAM_LIMIT; EP=0x0008; RP=0x0018 # PSU_PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD 0x18 # ATTR_107 @@ -13798,8 +16178,9 @@ set psu_resetout_init_data { mask_write 0XFD4801AC 0x000007FF 0x00000018 # Register : ATTR_108 @ 0XFD4801B0

- # Number of credits that should be advertised for Posted data received on Virtual Channel 0. The bytes advertised must be less - # han or equal to the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0020; RP=0x00B5 + # Number of credits that should be advertised for Posted data received on + # Virtual Channel 0. The bytes advertised must be less than or equal to th + # e bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0020; RP=0x00B5 # PSU_PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD 0xB5 # ATTR_108 @@ -13807,23 +16188,27 @@ set psu_resetout_init_data { mask_write 0XFD4801B0 0x000007FF 0x000000B5 # Register : ATTR_109 @ 0XFD4801B4

- # Not currently in use. Invert ECRC generated by block when trn_tecrc_gen_n and trn_terrfwd_n are asserted.; EP=0x0000; RP=0x00 - # 0 + # Not currently in use. Invert ECRC generated by block when trn_tecrc_gen_ + # n and trn_terrfwd_n are asserted.; EP=0x0000; RP=0x0000 # PSU_PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV 0x0 - # Enables td bit clear and ECRC trim on received TLP's FALSE == don't trim TRUE == trim.; EP=0x0001; RP=0x0001 + # Enables td bit clear and ECRC trim on received TLP's FALSE == don't trim + # TRUE == trim.; EP=0x0001; RP=0x0001 # PSU_PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM 0x1 - # Enables ECRC check on received TLP's 0 == don't check 1 == always check 3 == check if enabled by ECRC check enable bit of AER - # cap structure; EP=0x0003; RP=0x0003 + # Enables ECRC check on received TLP's 0 == don't check 1 == always check + # 3 == check if enabled by ECRC check enable bit of AER cap structure; EP= + # 0x0003; RP=0x0003 # PSU_PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK 0x3 - # Index of last packet buffer used by TX TLM (i.e. number of buffers - 1). Calculated from max payload size supported and the n - # mber of brams configured for transmit; EP=0x001C; RP=0x001C + # Index of last packet buffer used by TX TLM (i.e. number of buffers - 1). + # Calculated from max payload size supported and the number of brams conf + # igured for transmit; EP=0x001C; RP=0x001C # PSU_PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET 0x1c - # Number of credits that should be advertised for Posted headers received on Virtual Channel 0. The sum of the posted, non post - # d, and completion header credits must be <= 80; EP=0x0004; RP=0x0020 + # Number of credits that should be advertised for Posted headers received + # on Virtual Channel 0. The sum of the posted, non posted, and completion + # header credits must be <= 80; EP=0x0004; RP=0x0020 # PSU_PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH 0x20 # ATTR_109 @@ -13831,8 +16216,10 @@ set psu_resetout_init_data { mask_write 0XFD4801B4 0x0000FFFF 0x00007E20 # Register : ATTR_34 @ 0XFD480088

- # Specifies values to be transferred to Header Type register. Bit 7 should be set to '0' indicating single-function device. Bit - # 0 identifies header as Type 0 or Type 1, with '0' indicating a Type 0 header.; EP=0x0000; RP=0x0001 + # Specifies values to be transferred to Header Type register. Bit 7 should + # be set to '0' indicating single-function device. Bit 0 identifies heade + # r as Type 0 or Type 1, with '0' indicating a Type 0 header.; EP=0x0000; + # RP=0x0001 # PSU_PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE 0x1 # ATTR_34 @@ -13840,8 +16227,9 @@ set psu_resetout_init_data { mask_write 0XFD480088 0x000000FF 0x00000001 # Register : ATTR_53 @ 0XFD4800D4

- # PM Capability's Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capabil - # ty.; EP=0x0048; RP=0x0060 + # PM Capability's Next Capability Offset pointer to the next item in the c + # apabilities list, or 00h if this is the final capability.; EP=0x0048; RP + # =0x0060 # PSU_PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR 0x60 # ATTR_53 @@ -13849,20 +16237,24 @@ set psu_resetout_init_data { mask_write 0XFD4800D4 0x000000FF 0x00000060 # Register : ATTR_41 @ 0XFD4800A4

- # MSI Per-Vector Masking Capable. The value is transferred to the MSI Control Register[8]. When set, adds Mask and Pending Dwor - # to Cap structure; EP=0x0000; RP=0x0000 + # MSI Per-Vector Masking Capable. The value is transferred to the MSI Cont + # rol Register[8]. When set, adds Mask and Pending Dword to Cap structure; + # EP=0x0000; RP=0x0000 # PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE 0x0 - # Indicates that the MSI structures exists. If this is FALSE, then the MSI structure cannot be accessed via either the link or - # he management port.; EP=0x0001; RP=0x0000 + # Indicates that the MSI structures exists. If this is FALSE, then the MSI + # structure cannot be accessed via either the link or the management port + # .; EP=0x0001; RP=0x0000 # PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON 0 - # MSI Capability's Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capabi - # ity.; EP=0x0060; RP=0x0000 + # MSI Capability's Next Capability Offset pointer to the next item in the + # capabilities list, or 00h if this is the final capability.; EP=0x0060; R + # P=0x0000 # PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR 0x0 - # Indicates that the MSI structures exists. If this is FALSE, then the MSI structure cannot be accessed via either the link or - # he management port.; EP=0x0001; RP=0x0000 + # Indicates that the MSI structures exists. If this is FALSE, then the MSI + # structure cannot be accessed via either the link or the management port + # .; EP=0x0001; RP=0x0000 # PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON 0 # ATTR_41 @@ -13870,11 +16262,12 @@ set psu_resetout_init_data { mask_write 0XFD4800A4 0x000003FF 0x00000000 # Register : ATTR_97 @ 0XFD480184

- # Maximum Link Width. Valid settings are: 000001b x1, 000010b x2, 000100b x4, 001000b x8.; EP=0x0004; RP=0x0004 + # Maximum Link Width. Valid settings are: 000001b x1, 000010b x2, 000100b + # x4, 001000b x8.; EP=0x0004; RP=0x0004 # PSU_PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH 0x1 - # Used by LTSSM to set Maximum Link Width. Valid settings are: 000001b [x1], 000010b [x2], 000100b [x4], 001000b [x8].; EP=0x00 - # 4; RP=0x0004 + # Used by LTSSM to set Maximum Link Width. Valid settings are: 000001b [x1 + # ], 000010b [x2], 000100b [x4], 001000b [x8].; EP=0x0004; RP=0x0004 # PSU_PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH 0x1 # ATTR_97 @@ -13882,7 +16275,8 @@ set psu_resetout_init_data { mask_write 0XFD480184 0x00000FFF 0x00000041 # Register : ATTR_100 @ 0XFD480190

- # TRUE specifies upstream-facing port. FALSE specifies downstream-facing port.; EP=0x0001; RP=0x0000 + # TRUE specifies upstream-facing port. FALSE specifies downstream-facing p + # ort.; EP=0x0001; RP=0x0000 # PSU_PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING 0x0 # ATTR_100 @@ -13890,13 +16284,16 @@ set psu_resetout_init_data { mask_write 0XFD480190 0x00000040 0x00000000 # Register : ATTR_101 @ 0XFD480194

- # Enable the routing of message TLPs to the user through the TRN RX interface. A bit value of 1 enables routing of the message - # LP to the user. Messages are always decoded by the message decoder. Bit 0 - ERR COR, Bit 1 - ERR NONFATAL, Bit 2 - ERR FATAL, - # Bit 3 - INTA Bit 4 - INTB, Bit 5 - INTC, Bit 6 - INTD, Bit 7 PM_PME, Bit 8 - PME_TO_ACK, Bit 9 - unlock, Bit 10 PME_Turn_Off; - # EP=0x0000; RP=0x07FF + # Enable the routing of message TLPs to the user through the TRN RX interf + # ace. A bit value of 1 enables routing of the message TLP to the user. Me + # ssages are always decoded by the message decoder. Bit 0 - ERR COR, Bit 1 + # - ERR NONFATAL, Bit 2 - ERR FATAL, Bit 3 - INTA Bit 4 - INTB, Bit 5 - I + # NTC, Bit 6 - INTD, Bit 7 PM_PME, Bit 8 - PME_TO_ACK, Bit 9 - unlock, Bit + # 10 PME_Turn_Off; EP=0x0000; RP=0x07FF # PSU_PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE 0x7FF - # Disable BAR filtering. Does not change the behavior of the bar hit outputs; EP=0x0000; RP=0x0001 + # Disable BAR filtering. Does not change the behavior of the bar hit outpu + # ts; EP=0x0000; RP=0x0001 # PSU_PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING 0x1 # ATTR_101 @@ -13904,12 +16301,14 @@ set psu_resetout_init_data { mask_write 0XFD480194 0x0000FFE2 0x0000FFE2 # Register : ATTR_37 @ 0XFD480094

- # Link Bandwidth notification capability. Indicates support for the link bandwidth notification status and interrupt mechanism. - # Required for Root.; EP=0x0000; RP=0x0001 + # Link Bandwidth notification capability. Indicates support for the link b + # andwidth notification status and interrupt mechanism. Required for Root. + # ; EP=0x0000; RP=0x0001 # PSU_PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP 0x1 - # Sets the ASPM Optionality Compliance bit, to comply with the 2.1 ASPM Optionality ECN. Transferred to the Link Capabilities r - # gister.; EP=0x0001; RP=0x0001 + # Sets the ASPM Optionality Compliance bit, to comply with the 2.1 ASPM Op + # tionality ECN. Transferred to the Link Capabilities register.; EP=0x0001 + # ; RP=0x0001 # PSU_PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY 0x1 # ATTR_37 @@ -13917,13 +16316,16 @@ set psu_resetout_init_data { mask_write 0XFD480094 0x00004200 0x00004200 # Register : ATTR_93 @ 0XFD480174

- # Enables the Replay Timer to use the user-defined LL_REPLAY_TIMEOUT value (or combined with the built-in value, depending on L - # _REPLAY_TIMEOUT_FUNC). If FALSE, the built-in value is used.; EP=0x0000; RP=0x0000 + # Enables the Replay Timer to use the user-defined LL_REPLAY_TIMEOUT value + # (or combined with the built-in value, depending on LL_REPLAY_TIMEOUT_FU + # NC). If FALSE, the built-in value is used.; EP=0x0000; RP=0x0000 # PSU_PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN 0x1 - # Sets a user-defined timeout for the Replay Timer to force cause the retransmission of unacknowledged TLPs; refer to LL_REPLAY - # TIMEOUT_EN and LL_REPLAY_TIMEOUT_FUNC to see how this value is used. The unit for this attribute is in symbol times, which is - # 4ns at GEN1 speeds and 2ns at GEN2.; EP=0x0000; RP=0x0000 + # Sets a user-defined timeout for the Replay Timer to force cause the retr + # ansmission of unacknowledged TLPs; refer to LL_REPLAY_TIMEOUT_EN and LL_ + # REPLAY_TIMEOUT_FUNC to see how this value is used. The unit for this att + # ribute is in symbol times, which is 4ns at GEN1 speeds and 2ns at GEN2.; + # EP=0x0000; RP=0x0000 # PSU_PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT 0x1000 # ATTR_93 @@ -13961,8 +16363,8 @@ set psu_resetout_init_data { mask_write 0XFD480208 0x000000FF 0x00000000 # Register : ATTR_24 @ 0XFD480060

- # Code identifying basic function, subclass and applicable programming interface. Transferred to the Class Code register.; EP=0 - # 8000; RP=0x8000 + # Code identifying basic function, subclass and applicable programming int + # erface. Transferred to the Class Code register.; EP=0x8000; RP=0x8000 # PSU_PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE 0x400 # ATTR_24 @@ -13970,11 +16372,12 @@ set psu_resetout_init_data { mask_write 0XFD480060 0x0000FFFF 0x00000400 # Register : ATTR_25 @ 0XFD480064

- # Code identifying basic function, subclass and applicable programming interface. Transferred to the Class Code register.; EP=0 - # 0005; RP=0x0006 + # Code identifying basic function, subclass and applicable programming int + # erface. Transferred to the Class Code register.; EP=0x0005; RP=0x0006 # PSU_PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE 0x6 - # INTX Interrupt Generation Capable. If FALSE, this will cause Command[10] to be hardwired to 0.; EP=0x0001; RP=0x0001 + # INTX Interrupt Generation Capable. If FALSE, this will cause Command[10] + # to be hardwired to 0.; EP=0x0001; RP=0x0001 # PSU_PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED 0 # ATTR_25 @@ -13982,14 +16385,18 @@ set psu_resetout_init_data { mask_write 0XFD480064 0x000001FF 0x00000006 # Register : ATTR_4 @ 0XFD480010

- # Indicates that the AER structures exists. If this is FALSE, then the AER structure cannot be accessed via either the link or - # he management port, and AER will be considered to not be present for error management tasks (such as what types of error mess - # ges are sent if an error is detected).; EP=0x0001; RP=0x0001 + # Indicates that the AER structures exists. If this is FALSE, then the AER + # structure cannot be accessed via either the link or the management port + # , and AER will be considered to not be present for error management task + # s (such as what types of error messages are sent if an error is detected + # ).; EP=0x0001; RP=0x0001 # PSU_PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON 0 - # Indicates that the AER structures exists. If this is FALSE, then the AER structure cannot be accessed via either the link or - # he management port, and AER will be considered to not be present for error management tasks (such as what types of error mess - # ges are sent if an error is detected).; EP=0x0001; RP=0x0001 + # Indicates that the AER structures exists. If this is FALSE, then the AER + # structure cannot be accessed via either the link or the management port + # , and AER will be considered to not be present for error management task + # s (such as what types of error messages are sent if an error is detected + # ).; EP=0x0001; RP=0x0001 # PSU_PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON 0 # ATTR_4 @@ -13997,8 +16404,8 @@ set psu_resetout_init_data { mask_write 0XFD480010 0x00001000 0x00000000 # Register : ATTR_89 @ 0XFD480164

- # VSEC's Next Capability Offset pointer to the next item in the capabilities list, or 000h if this is the final capability.; EP - # 0x0140; RP=0x0140 + # VSEC's Next Capability Offset pointer to the next item in the capabiliti + # es list, or 000h if this is the final capability.; EP=0x0140; RP=0x0140 # PSU_PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR 0 # ATTR_89 @@ -14006,7 +16413,8 @@ set psu_resetout_init_data { mask_write 0XFD480164 0x00001FFE 0x00000000 # Register : ATTR_79 @ 0XFD48013C

- # CRS SW Visibility. Indicates RC can return CRS to SW. Transferred to the Root Capabilities register.; EP=0x0000; RP=0x0000 + # CRS SW Visibility. Indicates RC can return CRS to SW. Transferred to the + # Root Capabilities register.; EP=0x0000; RP=0x0000 # PSU_PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY 1 # ATTR_79 @@ -14014,8 +16422,9 @@ set psu_resetout_init_data { mask_write 0XFD48013C 0x00000020 0x00000020 # Register : ATTR_43 @ 0XFD4800AC

- # Indicates that the MSIX structures exists. If this is FALSE, then the MSIX structure cannot be accessed via either the link o - # the management port.; EP=0x0001; RP=0x0000 + # Indicates that the MSIX structures exists. If this is FALSE, then the MS + # IX structure cannot be accessed via either the link or the management po + # rt.; EP=0x0001; RP=0x0000 # PSU_PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON 0 # ATTR_43 @@ -14023,8 +16432,10 @@ set psu_resetout_init_data { mask_write 0XFD4800AC 0x00000100 0x00000000 # Register : ATTR_48 @ 0XFD4800C0

- # MSI-X Table Size. This value is transferred to the MSI-X Message Control[10:0] field. Set to 0 if MSI-X is not enabled. Note - # hat the core does not implement the table; that must be implemented in user logic.; EP=0x0003; RP=0x0000 + # MSI-X Table Size. This value is transferred to the MSI-X Message Control + # [10:0] field. Set to 0 if MSI-X is not enabled. Note that the core does + # not implement the table; that must be implemented in user logic.; EP=0x0 + # 003; RP=0x0000 # PSU_PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE 0 # ATTR_48 @@ -14032,8 +16443,8 @@ set psu_resetout_init_data { mask_write 0XFD4800C0 0x000007FF 0x00000000 # Register : ATTR_46 @ 0XFD4800B8

- # MSI-X Table Offset. This value is transferred to the MSI-X Table Offset field. Set to 0 if MSI-X is not enabled.; EP=0x0001; - # P=0x0000 + # MSI-X Table Offset. This value is transferred to the MSI-X Table Offset + # field. Set to 0 if MSI-X is not enabled.; EP=0x0001; RP=0x0000 # PSU_PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET 0 # ATTR_46 @@ -14041,8 +16452,8 @@ set psu_resetout_init_data { mask_write 0XFD4800B8 0x0000FFFF 0x00000000 # Register : ATTR_47 @ 0XFD4800BC

- # MSI-X Table Offset. This value is transferred to the MSI-X Table Offset field. Set to 0 if MSI-X is not enabled.; EP=0x0000; - # P=0x0000 + # MSI-X Table Offset. This value is transferred to the MSI-X Table Offset + # field. Set to 0 if MSI-X is not enabled.; EP=0x0000; RP=0x0000 # PSU_PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET 0 # ATTR_47 @@ -14050,8 +16461,8 @@ set psu_resetout_init_data { mask_write 0XFD4800BC 0x00001FFF 0x00000000 # Register : ATTR_44 @ 0XFD4800B0

- # MSI-X Pending Bit Array Offset This value is transferred to the MSI-X PBA Offset field. Set to 0 if MSI-X is not enabled.; EP - # 0x0001; RP=0x0000 + # MSI-X Pending Bit Array Offset This value is transferred to the MSI-X PB + # A Offset field. Set to 0 if MSI-X is not enabled.; EP=0x0001; RP=0x0000 # PSU_PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET 0 # ATTR_44 @@ -14059,8 +16470,8 @@ set psu_resetout_init_data { mask_write 0XFD4800B0 0x0000FFFF 0x00000000 # Register : ATTR_45 @ 0XFD4800B4

- # MSI-X Pending Bit Array Offset This value is transferred to the MSI-X PBA Offset field. Set to 0 if MSI-X is not enabled.; EP - # 0x1000; RP=0x0000 + # MSI-X Pending Bit Array Offset This value is transferred to the MSI-X PB + # A Offset field. Set to 0 if MSI-X is not enabled.; EP=0x1000; RP=0x0000 # PSU_PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET 0 # ATTR_45 @@ -14076,8 +16487,10 @@ set psu_resetout_init_data { mask_write 0XFD48031C 0x00000002 0x00000000 # Register : ATTR_35 @ 0XFD48008C

- # Active State PM Support. Indicates the level of active state power management supported by the selected PCI Express Link, enc - # ded as follows: 0 Reserved, 1 L0s entry supported, 2 Reserved, 3 L0s and L1 entry supported.; EP=0x0001; RP=0x0001 + # Active State PM Support. Indicates the level of active state power manag + # ement supported by the selected PCI Express Link, encoded as follows: 0 + # Reserved, 1 L0s entry supported, 2 Reserved, 3 L0s and L1 entry supporte + # d.; EP=0x0001; RP=0x0001 # PSU_PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT 0x0 # ATTR_35 @@ -14092,6 +16505,24 @@ set psu_resetout_init_data { # FPD Block level software controlled reset #(OFFSET, MASK, VALUE) (0XFD1A0100, 0x00020000U ,0x00000000U) */ mask_write 0XFD1A0100 0x00020000 0x00000000 + # : PCIE GPIO RESET + # : MASK_DATA_0_LSW LOW BANK [15:0] + # : MASK_DATA_0_MSW LOW BANK [25:16] + # : MASK_DATA_1_LSW LOW BANK [41:26] + # Register : MASK_DATA_1_LSW @ 0XFF0A0008

+ + # Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW] + # PSU_GPIO_MASK_DATA_1_LSW_MASK_1_LSW 0xffdf + + # Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW] + # PSU_GPIO_MASK_DATA_1_LSW_DATA_1_LSW 0x20 + + # Maskable Output Data (GPIO Bank1, MIO, Lower 16bits) + #(OFFSET, MASK, VALUE) (0XFF0A0008, 0xFFFFFFFFU ,0xFFDF0020U) */ + mask_write 0XFF0A0008 0xFFFFFFFF 0xFFDF0020 + # : MASK_DATA_1_MSW HIGH BANK [51:42] + # : MASK_DATA_1_LSW HIGH BANK [67:52] + # : MASK_DATA_1_LSW HIGH BANK [77:68] # : CHECK PLL LOCK FOR LANE0 # Register : L0_PLL_STATUS_READ_1 @ 0XFD4023E4

@@ -14131,8 +16562,10 @@ set psu_resetout_init_data { # CINMP: COMINIT Negate Minimum Period. # PSU_SATA_AHCI_VENDOR_PP2C_CINMP 0x28 - # PP2C - Port Phy2Cfg Register. This register controls the configuration of the Phy Control OOB timing for the COMINIT paramete - # s for either Port 0 or Port 1. The Port configured is controlled by the value programmed into the Port Config Register. + # PP2C - Port Phy2Cfg Register. This register controls the configuration o + # f the Phy Control OOB timing for the COMINIT parameters for either Port + # 0 or Port 1. The Port configured is controlled by the value programmed i + # nto the Port Config Register. #(OFFSET, MASK, VALUE) (0XFD0C00AC, 0xFFFFFFFFU ,0x28184018U) */ mask_write 0XFD0C00AC 0xFFFFFFFF 0x28184018 # Register : PP3C @ 0XFD0C00B0

@@ -14149,8 +16582,10 @@ set psu_resetout_init_data { # CWNMP: COMWAKE Negate Minimum Period. # PSU_SATA_AHCI_VENDOR_PP3C_CWNMP 0x0E - # PP3C - Port Phy3CfgRegister. This register controls the configuration of the Phy Control OOB timing for the COMWAKE parameter - # for either Port 0 or Port 1. The Port configured is controlled by the value programmed into the Port Config Register. + # PP3C - Port Phy3CfgRegister. This register controls the configuration of + # the Phy Control OOB timing for the COMWAKE parameters for either Port 0 + # or Port 1. The Port configured is controlled by the value programmed in + # to the Port Config Register. #(OFFSET, MASK, VALUE) (0XFD0C00B0, 0xFFFFFFFFU ,0x0E081406U) */ mask_write 0XFD0C00B0 0xFFFFFFFF 0x0E081406 # Register : PP4C @ 0XFD0C00B4

@@ -14161,31 +16596,41 @@ set psu_resetout_init_data { # BNM: COM Burst Nominal. # PSU_SATA_AHCI_VENDOR_PP4C_BNM 0x08 - # SFD: Signal Failure Detection, if the signal detection de-asserts for a time greater than this then the OOB detector will det - # rmine this is a line idle and cause the PhyInit state machine to exit the Phy Ready State. A value of zero disables the Signa - # Failure Detector. The value is based on the OOB Detector Clock typically (PMCLK Clock Period) * SFD giving a nominal time of - # 500ns based on a 150MHz PMCLK. + # SFD: Signal Failure Detection, if the signal detection de-asserts for a + # time greater than this then the OOB detector will determine this is a li + # ne idle and cause the PhyInit state machine to exit the Phy Ready State. + # A value of zero disables the Signal Failure Detector. The value is base + # d on the OOB Detector Clock typically (PMCLK Clock Period) * SFD giving + # a nominal time of 500ns based on a 150MHz PMCLK. # PSU_SATA_AHCI_VENDOR_PP4C_SFD 0x4A - # PTST: Partial to Slumber timer value, specific delay the controller should apply while in partial before entering slumber. Th - # value is bases on the system clock divided by 128, total delay = (Sys Clock Period) * PTST * 128 + # PTST: Partial to Slumber timer value, specific delay the controller shou + # ld apply while in partial before entering slumber. The value is bases on + # the system clock divided by 128, total delay = (Sys Clock Period) * PTS + # T * 128 # PSU_SATA_AHCI_VENDOR_PP4C_PTST 0x06 - # PP4C - Port Phy4Cfg Register. This register controls the configuration of the Phy Control Burst timing for the COM parameters - # for either Port 0 or Port 1. The Port configured is controlled by the value programmed into the Port Config Register. + # PP4C - Port Phy4Cfg Register. This register controls the configuration o + # f the Phy Control Burst timing for the COM parameters for either Port 0 + # or Port 1. The Port configured is controlled by the value programmed int + # o the Port Config Register. #(OFFSET, MASK, VALUE) (0XFD0C00B4, 0xFFFFFFFFU ,0x064A0813U) */ mask_write 0XFD0C00B4 0xFFFFFFFF 0x064A0813 # Register : PP5C @ 0XFD0C00B8

- # RIT: Retry Interval Timer. The calculated value divided by two, the lower digit of precision is not needed. + # RIT: Retry Interval Timer. The calculated value divided by two, the lowe + # r digit of precision is not needed. # PSU_SATA_AHCI_VENDOR_PP5C_RIT 0xC96A4 - # RCT: Rate Change Timer, a value based on the 54.2us for which a SATA device will transmit at a fixed rate ALIGNp after OOB ha - # completed, for a fast SERDES it is suggested that this value be 54.2us / 4 + # RCT: Rate Change Timer, a value based on the 54.2us for which a SATA dev + # ice will transmit at a fixed rate ALIGNp after OOB has completed, for a + # fast SERDES it is suggested that this value be 54.2us / 4 # PSU_SATA_AHCI_VENDOR_PP5C_RCT 0x3FF - # PP5C - Port Phy5Cfg Register. This register controls the configuration of the Phy Control Retry Interval timing for either Po - # t 0 or Port 1. The Port configured is controlled by the value programmed into the Port Config Register. + # PP5C - Port Phy5Cfg Register. This register controls the configuration o + # f the Phy Control Retry Interval timing for either Port 0 or Port 1. The + # Port configured is controlled by the value programmed into the Port Con + # fig Register. #(OFFSET, MASK, VALUE) (0XFD0C00B8, 0xFFFFFFFFU ,0x3FFC96A4U) */ mask_write 0XFD0C00B8 0xFFFFFFFF 0x3FFC96A4 } @@ -14243,8 +16688,9 @@ set psu_resetin_init_data { # : PUTTING DP IN RESET # Register : DP_TX_PHY_POWER_DOWN @ 0XFD4A0238

- # Two bits per lane. When set to 11, moves the GT to power down mode. When set to 00, GT will be in active state. bits [1:0] - - # ane0 Bits [3:2] - lane 1 + # Two bits per lane. When set to 11, moves the GT to power down mode. When + # set to 00, GT will be in active state. bits [1:0] - lane0 Bits [3:2] - + # lane 1 # PSU_DP_DP_TX_PHY_POWER_DOWN_POWER_DWN 0XA # Control PHY Power down @@ -14275,7 +16721,8 @@ set psu_ps_pl_isolation_removal_data { # Power-up Request Interrupt Enable for PL # PSU_PMU_GLOBAL_REQ_PWRUP_INT_EN_PL 1 - # Power-up Request Interrupt Enable Register. Writing a 1 to this location will unmask the interrupt. + # Power-up Request Interrupt Enable Register. Writing a 1 to this location + # will unmask the interrupt. #(OFFSET, MASK, VALUE) (0XFFD80118, 0x00800000U ,0x00800000U) */ mask_write 0XFFD80118 0x00800000 0x00800000 # Register : REQ_PWRUP_TRIG @ 0XFFD80120

@@ -14283,7 +16730,8 @@ set psu_ps_pl_isolation_removal_data { # Power-up Request Trigger for PL # PSU_PMU_GLOBAL_REQ_PWRUP_TRIG_PL 1 - # Power-up Request Trigger Register. A write of one to this location will generate a power-up request to the PMU. + # Power-up Request Trigger Register. A write of one to this location will + # generate a power-up request to the PMU. #(OFFSET, MASK, VALUE) (0XFFD80120, 0x00800000U ,0x00800000U) */ mask_write 0XFFD80120 0x00800000 0x00800000 # : POLL ON PL POWER STATUS @@ -14294,6 +16742,58 @@ set psu_ps_pl_isolation_removal_data { mask_poll 0XFFD80110 0x00800000 0x00000000 } +set psu_afi_config { + # : AFI RESET + # Register : RST_FPD_TOP @ 0XFD1A0100

+ + # AF_FM0 block level reset + # PSU_CRF_APB_RST_FPD_TOP_AFI_FM0_RESET 0 + + # AF_FM1 block level reset + # PSU_CRF_APB_RST_FPD_TOP_AFI_FM1_RESET 0 + + # AF_FM2 block level reset + # PSU_CRF_APB_RST_FPD_TOP_AFI_FM2_RESET 0 + + # AF_FM3 block level reset + # PSU_CRF_APB_RST_FPD_TOP_AFI_FM3_RESET 0 + + # AF_FM4 block level reset + # PSU_CRF_APB_RST_FPD_TOP_AFI_FM4_RESET 0 + + # AF_FM5 block level reset + # PSU_CRF_APB_RST_FPD_TOP_AFI_FM5_RESET 0 + + # FPD Block level software controlled reset + #(OFFSET, MASK, VALUE) (0XFD1A0100, 0x00001F80U ,0x00000000U) */ + mask_write 0XFD1A0100 0x00001F80 0x00000000 + # Register : RST_LPD_TOP @ 0XFF5E023C

+ + # AFI FM 6 + # PSU_CRL_APB_RST_LPD_TOP_AFI_FM6_RESET 0 + + # Software control register for the LPD block. + #(OFFSET, MASK, VALUE) (0XFF5E023C, 0x00080000U ,0x00000000U) */ + mask_write 0XFF5E023C 0x00080000 0x00000000 + # : AFIFM INTERFACE WIDTH + # Register : afi_fs @ 0XFD615000

+ + # Select the 32/64/128-bit data width selection for the Slave 0 00: 32-bit + # AXI data width (default) 01: 64-bit AXI data width 10: 128-bit AXI data + # width 11: reserved + # PSU_FPD_SLCR_AFI_FS_DW_SS0_SEL 0x2 + + # Select the 32/64/128-bit data width selection for the Slave 1 00: 32-bit + # AXI data width (default) 01: 64-bit AXI data width 10: 128-bit AXI data + # width 11: reserved + # PSU_FPD_SLCR_AFI_FS_DW_SS1_SEL 0x2 + + # afi fs SLCR control register. This register is static and should not be + # modified during operation. + #(OFFSET, MASK, VALUE) (0XFD615000, 0x00000F00U ,0x00000A00U) */ + mask_write 0XFD615000 0x00000F00 0x00000A00 +} + set psu_ps_pl_reset_config_data { # : PS PL RESET SEQUENCE # : FABRIC RESET USING EMIO @@ -14366,6 +16866,7 @@ proc psu_init {} { variable psu_serdes_init_data variable psu_resetin_init_data variable psu_peripherals_powerdwn_data + variable psu_afi_config init_ps [subst {$psu_mio_init_data $psu_pll_init_data $psu_clock_init_data $psu_ddr_init_data }] psu_ddr_phybringup_data @@ -14374,6 +16875,7 @@ proc psu_init {} { init_ps [subst {$psu_serdes_init_data $psu_resetout_init_data }] init_peripheral init_ps [subst {$psu_peripherals_powerdwn_data }] + init_ps [subst {$psu_afi_config }] # restore original mode configparams force-mem-accesses $saved_mode } @@ -14409,7 +16911,7 @@ proc mask_poll { addr mask } { set curval "0x[string range [mrd -force $addr] end-8 end]" set maskedval [expr {$curval & $mask}] set count [ expr { $count + 1 } ] - if { $count == 100000000 } { + if { $count == 1000 } { puts "Timeout Reached. Mask poll failed at ADDRESS: $addr MASK: $mask" break } @@ -14424,48 +16926,195 @@ proc psu_mask_write { addr mask value } { mwr -force $addr $maskedval } +proc serdes_fixcal_code {} { + + set MaskStatus 1 + array set match_pmos_code {} + array set match_nmos_code {} + array set match_ical_code {} + array set match_rcal_code {} + set p_code 0 + set n_code 0 + set i_code 0 + set r_code 0 + set repeat_count 0 + set L3_TM_CALIB_DIG20 0 + set L3_TM_CALIB_DIG19 0 + set L3_TM_CALIB_DIG18 0 + set L3_TM_CALIB_DIG16 0 + set L3_TM_CALIB_DIG15 0 + set L3_TM_CALIB_DIG14 0 -proc serdes_fixcal_code {} { - #/* - # * L3_TM_CALIB_DIG19 - # */ - mask_write 0xFD40EC4C 0xFFFFFFFF 0x00000020 + set rdata 0 + + set rdata [mask_read 0XFD40289C 0xFFFFFFFF] + set rdata [expr $rdata & ~0x03 ] + set rdata [expr $rdata | 0x1] + mask_write 0XFD40289C 0xFFFFFFFF $rdata + #check supply good status before starting AFE sequencing + set count 1 + while 1 { + set rdata [mask_read 0xFD402B1C 0xFFFFFFFF] + set count [ expr { $count + 1 } ] + if { [expr $rdata & 0x0000000E] == 0x0000000E } { + break; + } + if { $count == 1000 } { + break; + } + } + + + for {set i 0} {$i<23 } {incr i } { + set match_pmos_code($i) 0; + set match_nmos_code($i) 0; + } + + for {set i 0} {$i<7} {incr i} { + set match_ical_code($i) 0; + set match_rcal_code($i) 0; + } + + while 1 { + #Clear ICM_CFG value + mask_write 0xFD410010 0xFFFFFFFF 0x00000000 + mask_write 0xFD410014 0xFFFFFFFF 0x00000000 + + #Set ICM_CFG value + #This will trigger recalibration of all stages + mask_write 0xFD410010 0xFFFFFFFF 0x00000001 + mask_write 0xFD410014 0xFFFFFFFF 0x00000000; + + #is calibration done? polling on L3_CALIB_DONE_STATUS + mask_poll 0xFD40EF14 0x2; + + #PMOS code + set p_code [mask_read 0xFD40EF18 0xFFFFFFFF]; + #NMOS code + set n_code [mask_read 0xFD40EF1C 0xFFFFFFFF]; + #ICAL code + set i_code [mask_read 0xFD40EF24 0xFFFFFFFF]; + #RX code + set r_code [mask_read 0xFD40EF28 0xFFFFFFFF]; + + + #xil_printf("#SERDES initialization VALUES NMOS = 0x%x, PMOS = 0x%x, ICAL = 0x%x, RCAL = 0x%x\n\r", p_code, n_code, i_code, r_code); + #PMOS code in acceptable range + if {($p_code >= 0x26) && ($p_code <= 0x3C)} { + set index [expr $p_code - 0x26] + set value $match_pmos_code($index) + incr value + set match_pmos_code($index) $value; + } + #NMOS code in acceptable range + if {($n_code >= 0x26) && ($n_code <= 0x3C)} { + set index [expr $n_code - 0x26] + set value $match_nmos_code($index) + incr value + set match_nmos_code($index) $value; + } + #PMOS code in acceptable range + if {($i_code >= 0xC) && ($i_code <= 0x12)} { + + set index [expr $i_code - 0xC] + set value $match_ical_code($index) + incr value + set match_ical_code($index) $value; + + } + #NMOS code in acceptable range + if {($r_code >= 0x6) && ($r_code <= 0xC)} { + set index [expr $r_code - 0x6] + set value $match_rcal_code($index) + incr value + set match_rcal_code($index) $value; + } + + incr repeat_count + if {$repeat_count > 10} { + break + } + } + + + #find the valid code which resulted in maximum times in 10 iterations + for {set i 0 } {$i < 23} {incr i} { - #/* - # * ICM_CFG0 - # */ - mask_write 0xFD410010 0xFFFFFFFF 0x00000001 + if {$match_pmos_code($i) >= $match_pmos_code(0) } { + set match_pmos_code(0) $match_pmos_code($i) + set p_code [expr 0x26 + $i] + } + if {$match_nmos_code($i) >= $match_nmos_code(0)} { + + set match_nmos_code(0) $match_nmos_code($i) + set n_code [expr 0x26 + $i]; + } + } - - #/* - # * is calibration done, polling on L3_CALIB_DONE_STATUS - # */ - mask_poll 0xFD40EF14 0x2 - - #unsigned int tmp_0_1; - set tmp_0_1 [mrd -force -value 0xFD400B0C] - set tmp_0_1 [expr {$tmp_0_1 & 0x3F}] - - set tmp_0_2 [expr {$tmp_0_1 & 0x7}] - set tmp_0_3 [expr {$tmp_0_1 & 0x38}] - - #Configure ICM for de-asserting CMN_Resetn - mask_write 0xFD410010 0xFFFFFFFF 0x00000000 - mask_write 0xFD410014 0xFFFFFFFF 0x00000000 - - set tmp_0_2_mod [expr {($tmp_0_2 << 1) | (0x1)}] - set tmp_0_2_mod [expr {$tmp_0_2_mod << 4}] - - set tmp_0_3 [expr {$tmp_0_3 >> 3}] - mask_write 0xFD40EC4C 0xFFFFFFFF $tmp_0_3 - - #L3_TM_CALIB_DIG18 - mask_write 0xFD40EC48 0xFFFFFFFF $tmp_0_2_mod + for {set $i 0} {$i<7} {incr i} { + if {$match_ical_code($i) >= $match_ical_code(0)} { + set match_ical_code(0) $match_ical_code($i) + set i_code [expr 0xC + $i] + } + if {$match_rcal_code($i) >= $match_rcal_code(0)} { + set match_rcal_code(0) $match_rcal_code($i) + set r_code [expr 0x6 + $i] + } + } + #xil_printf("#SERDES initialization PASSED NMOS = 0x%x, PMOS = 0x%x, ICAL = 0x%x, RCAL = 0x%x\n\r", p_code, n_code, i_code, r_code); + #L3_TM_CALIB_DIG20[3] PSW MSB Override + #L3_TM_CALIB_DIG20[2:0] PSW Code [4:2] + #read DIG20 + set L3_TM_CALIB_DIG20 [mask_read 0xFD40EC50 0xFFFFFFF0]; + set L3_TM_CALIB_DIG20 [expr $L3_TM_CALIB_DIG20 | 0x8 | (($p_code>>2)&0x7)] -} + #L3_TM_CALIB_DIG19[7:6] PSW Code [1:0] + #L3_TM_CALIB_DIG19[5] PSW Override + #L3_TM_CALIB_DIG19[2] NSW MSB Override + #L3_TM_CALIB_DIG19[1:0] NSW Code [4:3] + #read DIG19 + set L3_TM_CALIB_DIG19 [mask_read 0xFD40EC4C 0xFFFFFF18] + set L3_TM_CALIB_DIG19 [expr $L3_TM_CALIB_DIG19 | (($p_code&0x3)<<6) | 0x20 | 0x4 | (($n_code>>3)&0x3)] + #L3_TM_CALIB_DIG18[7:5] NSW Code [2:0] + #L3_TM_CALIB_DIG18[4] NSW Override + #read DIG18 + set L3_TM_CALIB_DIG18 [mask_read 0xFD40EC48 0xFFFFFF0F] + set L3_TM_CALIB_DIG18 [expr $L3_TM_CALIB_DIG18 | (($n_code&0x7)<<5) | 0x10] + + + #L3_TM_CALIB_DIG16[2:0] RX Code [3:1] + #read DIG16 + set L3_TM_CALIB_DIG16 [mask_read 0xFD40EC40 0xFFFFFFF8] + set L3_TM_CALIB_DIG16 [expr $L3_TM_CALIB_DIG16 | (($r_code>>1)&0x7)] + + #L3_TM_CALIB_DIG15[7] RX Code [0] + #L3_TM_CALIB_DIG15[6] RX CODE Override + #L3_TM_CALIB_DIG15[3] ICAL MSB Override + #L3_TM_CALIB_DIG15[2:0] ICAL Code [3:1] + #read DIG15 + set L3_TM_CALIB_DIG15 [mask_read 0xFD40EC3C 0xFFFFFF30] + set L3_TM_CALIB_DIG15 [expr $L3_TM_CALIB_DIG15 | (($r_code&0x1)<<7) | 0x40 | 0x8 | (($i_code>>1)&0x7)] + + #L3_TM_CALIB_DIG14[7] ICAL Code [0] + #L3_TM_CALIB_DIG14[6] ICAL Override + #read DIG14 + set L3_TM_CALIB_DIG14 [mask_read 0xFD40EC38 0xFFFFFF3F] + set L3_TM_CALIB_DIG14 [expr $L3_TM_CALIB_DIG14 | (($i_code&0x1)<<7) | 0x40] + + #Forces the calibration values + mask_write 0xFD40EC50 0xFFFFFFFF $L3_TM_CALIB_DIG20 + mask_write 0xFD40EC4C 0xFFFFFFFF $L3_TM_CALIB_DIG19 + mask_write 0xFD40EC48 0xFFFFFFFF $L3_TM_CALIB_DIG18 + mask_write 0xFD40EC40 0xFFFFFFFF $L3_TM_CALIB_DIG16 + mask_write 0xFD40EC3C 0xFFFFFFFF $L3_TM_CALIB_DIG15 + mask_write 0xFD40EC38 0xFFFFFFFF $L3_TM_CALIB_DIG14 + + + return $MaskStatus; + } proc serdes_enb_coarse_saturation {} { #/* # * Enable PLL Coarse Code saturation Logic @@ -14477,9 +17126,7 @@ proc serdes_enb_coarse_saturation {} { } - proc init_serdes {} { - serdes_fixcal_code serdes_enb_coarse_saturation @@ -14501,48 +17148,15 @@ proc poll { addr mask data} { } proc init_peripheral {} { - - # Release all resets in the IOU */ - mask_write 0xFF5E0230 0xFFFFFFFF 0x00000000 - mask_write 0xFF5E0234 0xFFFFFFFF 0x00000000 - mask_write 0xFF5E0238 0xFFFFFFFF 0x00000000 - - # Take LPD out of reset except R5 */ - set tmp_0_1 [mrd -force -value 0xFF5E023C] - set tmp_0_1 [expr {$tmp_0_1 & 0x7}] - mask_write 0xFF5E023C 0xFFFFFFFF $tmp_0_1 - - # Take most of FPD out of reset */ - mask_write 0XFD1A0100 0xFFFFFFFF 0x00000000 - - # Making DPDMA as secure - mask_write 0xFD690040 0x00000001 0x00000000 - # Making PCIe as secure - mask_write 0xFD690030 0x00000001 0x00000000 - +#SMMU_REG Interrrupt Enable: Followig register need to be written all the time to properly catch SMMU messages. + mask_write 0xFD5F0018 0x8000001F 0x8000001F } proc psu_init_xppu_aper_ram {} { - set APER_OFFSET 0xFF981000 - set i 0 - while { $i <= 400 } { - mask_write $APER_OFFSET 0xF80FFFFF 0x08080000 - set APER_OFFSET [ expr $APER_OFFSET + 4 ] - set APER_OFFSET "0x[format %08X [ expr $APER_OFFSET] ]" - set i [ expr { $i + 1 } ] - } } proc psu_lpd_protection {} { - set saved_mode [configparams force-mem-accesses] - configparams force-mem-accesses 1 - - psu_init_xppu_aper_ram; - variable psu_lpd_xppu_data - init_ps [subst {$psu_lpd_xppu_data }] - - configparams force-mem-accesses $saved_mode } proc psu_ddr_protection {} { @@ -14591,6 +17205,8 @@ proc psu_protection_lock {} { } proc psu_protection {} { + variable psu_apply_master_tz + init_ps [subst {$psu_apply_master_tz }] psu_ddr_protection psu_ocm_protection psu_fpd_protection @@ -14598,26 +17214,34 @@ proc psu_protection {} { } proc psu_ddr_phybringup_data {} { -set dpll_divisor [expr {(0x00003F00 & [mrd -force -value 0xFD1A0080]) >> 0x00000008 }] - psu_mask_write 0xFD1A0080 0x00003F00 0x00000500 - psu_mask_write 0xFD080028 0x00000001 0x00000001 -mwr -force 0xFD080004 0x00040003 -mask_poll 0xFD080030 0x00000001 - psu_mask_write 0xFD080684 0x06000000 0x02000000 - psu_mask_write 0xFD0806A4 0x06000000 0x02000000 - psu_mask_write 0xFD0806C4 0x06000000 0x02000000 - psu_mask_write 0xFD0806E4 0x06000000 0x02000000 - psu_mask_write 0xFD1A0080 0x3F00 [expr {($dpll_divisor << 8)}] -mwr -force 0xFD080004 0x40040071 -mask_poll 0xFD080030 0x00000001 -mwr -force 0xFD080004 0x40040001 -mask_poll 0xFD080030 0x00000001 +mwr -force 0xFD080004 0x00040073 poll 0xFD080030 0x0000000F 0x0000000F psu_mask_write 0xFD080004 0x00000001 0x00000001 #poll for PHY initialization to complete poll 0xFD080030 0x000000FF 0x0000001F + psu_mask_write 0xFD070010 0x00000008 0x00000008 + psu_mask_write 0xFD0701B0 0x00000001 0x00000001 + psu_mask_write 0xFD070010 0x00000030 0x00000010 + psu_mask_write 0xFD070010 0x00000001 0x00000000 + psu_mask_write 0xFD070010 0x0000F000 0x00006000 + psu_mask_write 0xFD070014 0x0003FFFF 0x00000819 + psu_mask_write 0xFD070010 0x80000000 0x80000000 +poll 0xFD070018 0x00000001 0 + psu_mask_write 0xFD070010 0x00000030 0x00000010 + psu_mask_write 0xFD070010 0x00000001 0x00000000 + psu_mask_write 0xFD070010 0x0000F000 0x00006000 + psu_mask_write 0xFD070014 0x0003FFFF 0x00000899 + psu_mask_write 0xFD070010 0x80000000 0x80000000 +poll 0xFD070018 0x00000001 0 + psu_mask_write 0xFD070010 0x00000030 0x00000010 + psu_mask_write 0xFD070010 0x00000001 0x00000000 + psu_mask_write 0xFD070010 0x0000F000 0x00006000 + psu_mask_write 0xFD070014 0x0003FFFF 0x00000819 + psu_mask_write 0xFD070010 0x80000000 0x80000000 +poll 0xFD070018 0x00000001 0 + psu_mask_write 0xFD070010 0x00000008 0x00000000 mwr -force 0xFD0701B0 0x00000001 mwr -force 0xFD070320 0x00000001 #//poll for DDR initialization to complete @@ -14646,31 +17270,29 @@ poll 0xFD080030 0x00000FFF 0x00000FFF # Run Vref training in static read mode mwr -force 0xFD080200 0x100091C7 -mwr -force 0xFD080018 0x00F01EF2 -mwr -force 0xFD08001C 0x55AA5498 -mwr -force 0xFD08142C 0x00041830 -mwr -force 0xFD08146C 0x00041830 -mwr -force 0xFD0814AC 0x00041830 -mwr -force 0xFD0814EC 0x00041830 -mwr -force 0xFD08152C 0x00041830 +mwr -force 0xFD080018 0x00F01EEF + psu_mask_write 0xFD08142C 0x00000030 0x00000030 + psu_mask_write 0xFD08146C 0x00000030 0x00000030 + psu_mask_write 0xFD0814AC 0x00000030 0x00000030 + psu_mask_write 0xFD0814EC 0x00000030 0x00000030 + psu_mask_write 0xFD08152C 0x00000030 0x00000030 psu_mask_write 0xFD080004 0xFFFFFFFF 0x00060001 #trigger VreFPHY training -poll 0xFD080030 0x00000C01 0x00000C01 +poll 0xFD080030 0x00004001 0x00004001 #//Poll PUB_PGSR0 for Trng complete mwr -force 0xFD080200 0x800091C7 -mwr -force 0xFD080018 0x00F12302 -mwr -force 0xFD08001C 0x55AA5480 -mwr -force 0xFD08142C 0x00041800 -mwr -force 0xFD08146C 0x00041800 -mwr -force 0xFD0814AC 0x00041800 -mwr -force 0xFD0814EC 0x00041800 -mwr -force 0xFD08152C 0x00041800 +mwr -force 0xFD080018 0x00F122E7 + psu_mask_write 0xFD08142C 0x00000030 0x00000000 + psu_mask_write 0xFD08146C 0x00000030 0x00000000 + psu_mask_write 0xFD0814AC 0x00000030 0x00000000 + psu_mask_write 0xFD0814EC 0x00000030 0x00000000 + psu_mask_write 0xFD08152C 0x00000030 0x00000000 psu_mask_write 0xFD080004 0xFFFFFFFF 0x0000C001 #trigger VreFPHY training -poll 0xFD080030 0x00004001 0x00004001 +poll 0xFD080030 0x00000C01 0x00000C01 #//Poll PUB_PGSR0 for Trng complete mwr -force 0xFD070180 0x01000040 diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init_gpl.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init_gpl.c index 8ed7cf1dc..d75ebacb3 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init_gpl.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init_gpl.c @@ -1,7 +1,7 @@ /****************************************************************************** * * Copyright (C) 2015 Xilinx, Inc. All rights reserved. -* +* * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or @@ -11,21103 +11,21793 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. -* +* * You should have received a copy of the GNU General Public License along * with this program; if not, see -* -* -******************************************************************************/ +* +* +******************************************************************************/ #include #include #include "psu_init_gpl.h" +#define DPLL_CFG_LOCK_DLY 63 +#define DPLL_CFG_LOCK_CNT 625 +#define DPLL_CFG_LFHF 3 +#define DPLL_CFG_CP 3 +#define DPLL_CFG_RES 2 -int mask_pollOnValue(u32 add , u32 mask, u32 value ); +static int mask_pollOnValue(u32 add, u32 mask, u32 value); -int mask_poll(u32 add , u32 mask ); +static int mask_poll(u32 add, u32 mask); -void mask_delay(u32 delay); +static void mask_delay(u32 delay); -u32 mask_read(u32 add , u32 mask ); +static u32 mask_read(u32 add, u32 mask); -static void PSU_Mask_Write (unsigned long offset, unsigned long mask, unsigned long val) +static void dpll_prog(int ddr_pll_fbdiv, int d_lock_dly, + int d_lock_cnt, int d_lfhf, int d_cp, int d_res); + +static +void PSU_Mask_Write(unsigned long offset, unsigned long mask, + unsigned long val) { unsigned long RegVal = 0x0; - RegVal = Xil_In32 (offset); + + RegVal = Xil_In32(offset); RegVal &= ~(mask); RegVal |= (val & mask); - Xil_Out32 (offset, RegVal); + Xil_Out32(offset, RegVal); } - void prog_reg (unsigned long addr, unsigned long mask, unsigned long shift, unsigned long value) { - int rdata =0; +static +void prog_reg(unsigned long addr, unsigned long mask, + unsigned long shift, + unsigned long value) +{ + int rdata = 0; + rdata = Xil_In32(addr); rdata = rdata & (~mask); rdata = rdata | (value << shift); - Xil_Out32(addr,rdata); - } - -unsigned long psu_pll_init_data() { - // : RPLL INIT - /*Register : RPLL_CFG @ 0XFF5E0034

- - PLL loop filter resistor control - PSU_CRL_APB_RPLL_CFG_RES 0x2 - - PLL charge pump control - PSU_CRL_APB_RPLL_CFG_CP 0x3 - - PLL loop filter high frequency capacitor control - PSU_CRL_APB_RPLL_CFG_LFHF 0x3 - - Lock circuit counter setting - PSU_CRL_APB_RPLL_CFG_LOCK_CNT 0x258 - - Lock circuit configuration settings for lock windowsize - PSU_CRL_APB_RPLL_CFG_LOCK_DLY 0x3f - - Helper data. Values are to be looked up in a table from Data Sheet - (OFFSET, MASK, VALUE) (0XFF5E0034, 0xFE7FEDEFU ,0x7E4B0C62U) - RegMask = (CRL_APB_RPLL_CFG_RES_MASK | CRL_APB_RPLL_CFG_CP_MASK | CRL_APB_RPLL_CFG_LFHF_MASK | CRL_APB_RPLL_CFG_LOCK_CNT_MASK | CRL_APB_RPLL_CFG_LOCK_DLY_MASK | 0 ); - - RegVal = ((0x00000002U << CRL_APB_RPLL_CFG_RES_SHIFT - | 0x00000003U << CRL_APB_RPLL_CFG_CP_SHIFT - | 0x00000003U << CRL_APB_RPLL_CFG_LFHF_SHIFT - | 0x00000258U << CRL_APB_RPLL_CFG_LOCK_CNT_SHIFT - | 0x0000003FU << CRL_APB_RPLL_CFG_LOCK_DLY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RPLL_CFG_OFFSET ,0xFE7FEDEFU ,0x7E4B0C62U); - /*############################################################################################################################ */ - - // : UPDATE FB_DIV - /*Register : RPLL_CTRL @ 0XFF5E0030

- - Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_ - ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source - PSU_CRL_APB_RPLL_CTRL_PRE_SRC 0x0 - - The integer portion of the feedback divider to the PLL - PSU_CRL_APB_RPLL_CTRL_FBDIV 0x48 - - This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency - PSU_CRL_APB_RPLL_CTRL_DIV2 0x1 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFF5E0030, 0x00717F00U ,0x00014800U) - RegMask = (CRL_APB_RPLL_CTRL_PRE_SRC_MASK | CRL_APB_RPLL_CTRL_FBDIV_MASK | CRL_APB_RPLL_CTRL_DIV2_MASK | 0 ); - - RegVal = ((0x00000000U << CRL_APB_RPLL_CTRL_PRE_SRC_SHIFT - | 0x00000048U << CRL_APB_RPLL_CTRL_FBDIV_SHIFT - | 0x00000001U << CRL_APB_RPLL_CTRL_DIV2_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RPLL_CTRL_OFFSET ,0x00717F00U ,0x00014800U); - /*############################################################################################################################ */ - - // : BY PASS PLL - /*Register : RPLL_CTRL @ 0XFF5E0030

- - Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_RPLL_CTRL_BYPASS 1 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFF5E0030, 0x00000008U ,0x00000008U) - RegMask = (CRL_APB_RPLL_CTRL_BYPASS_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_RPLL_CTRL_BYPASS_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RPLL_CTRL_OFFSET ,0x00000008U ,0x00000008U); - /*############################################################################################################################ */ - - // : ASSERT RESET - /*Register : RPLL_CTRL @ 0XFF5E0030

- - Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS. - PSU_CRL_APB_RPLL_CTRL_RESET 1 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFF5E0030, 0x00000001U ,0x00000001U) - RegMask = (CRL_APB_RPLL_CTRL_RESET_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_RPLL_CTRL_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RPLL_CTRL_OFFSET ,0x00000001U ,0x00000001U); - /*############################################################################################################################ */ - - // : DEASSERT RESET - /*Register : RPLL_CTRL @ 0XFF5E0030

- - Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS. - PSU_CRL_APB_RPLL_CTRL_RESET 0 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFF5E0030, 0x00000001U ,0x00000000U) - RegMask = (CRL_APB_RPLL_CTRL_RESET_MASK | 0 ); - - RegVal = ((0x00000000U << CRL_APB_RPLL_CTRL_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RPLL_CTRL_OFFSET ,0x00000001U ,0x00000000U); - /*############################################################################################################################ */ - - // : CHECK PLL STATUS - /*Register : PLL_STATUS @ 0XFF5E0040

- - RPLL is locked - PSU_CRL_APB_PLL_STATUS_RPLL_LOCK 1 - (OFFSET, MASK, VALUE) (0XFF5E0040, 0x00000002U ,0x00000002U) */ - mask_poll(CRL_APB_PLL_STATUS_OFFSET,0x00000002U); - - /*############################################################################################################################ */ - - // : REMOVE PLL BY PASS - /*Register : RPLL_CTRL @ 0XFF5E0030

- - Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_RPLL_CTRL_BYPASS 0 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFF5E0030, 0x00000008U ,0x00000000U) - RegMask = (CRL_APB_RPLL_CTRL_BYPASS_MASK | 0 ); - - RegVal = ((0x00000000U << CRL_APB_RPLL_CTRL_BYPASS_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RPLL_CTRL_OFFSET ,0x00000008U ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : RPLL_TO_FPD_CTRL @ 0XFF5E0048

- - Divisor value for this clock. - PSU_CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0 0x3 - - Control for a clock that will be generated in the LPD, but used in the FPD as a clock source for the peripheral clock muxes. - (OFFSET, MASK, VALUE) (0XFF5E0048, 0x00003F00U ,0x00000300U) - RegMask = (CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_MASK | 0 ); - - RegVal = ((0x00000003U << CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RPLL_TO_FPD_CTRL_OFFSET ,0x00003F00U ,0x00000300U); - /*############################################################################################################################ */ - - // : RPLL FRAC CFG - /*Register : RPLL_FRAC_CFG @ 0XFF5E0038

- - Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona - mode and uses DATA of this register for the fractional portion of the feedback divider. - PSU_CRL_APB_RPLL_FRAC_CFG_ENABLED 0x0 - - Fractional value for the Feedback value. - PSU_CRL_APB_RPLL_FRAC_CFG_DATA 0x0 - - Fractional control for the PLL - (OFFSET, MASK, VALUE) (0XFF5E0038, 0x8000FFFFU ,0x00000000U) - RegMask = (CRL_APB_RPLL_FRAC_CFG_ENABLED_MASK | CRL_APB_RPLL_FRAC_CFG_DATA_MASK | 0 ); - - RegVal = ((0x00000000U << CRL_APB_RPLL_FRAC_CFG_ENABLED_SHIFT - | 0x00000000U << CRL_APB_RPLL_FRAC_CFG_DATA_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RPLL_FRAC_CFG_OFFSET ,0x8000FFFFU ,0x00000000U); - /*############################################################################################################################ */ - - // : IOPLL INIT - /*Register : IOPLL_CFG @ 0XFF5E0024

- - PLL loop filter resistor control - PSU_CRL_APB_IOPLL_CFG_RES 0xc - - PLL charge pump control - PSU_CRL_APB_IOPLL_CFG_CP 0x3 - - PLL loop filter high frequency capacitor control - PSU_CRL_APB_IOPLL_CFG_LFHF 0x3 - - Lock circuit counter setting - PSU_CRL_APB_IOPLL_CFG_LOCK_CNT 0x339 - - Lock circuit configuration settings for lock windowsize - PSU_CRL_APB_IOPLL_CFG_LOCK_DLY 0x3f - - Helper data. Values are to be looked up in a table from Data Sheet - (OFFSET, MASK, VALUE) (0XFF5E0024, 0xFE7FEDEFU ,0x7E672C6CU) - RegMask = (CRL_APB_IOPLL_CFG_RES_MASK | CRL_APB_IOPLL_CFG_CP_MASK | CRL_APB_IOPLL_CFG_LFHF_MASK | CRL_APB_IOPLL_CFG_LOCK_CNT_MASK | CRL_APB_IOPLL_CFG_LOCK_DLY_MASK | 0 ); - - RegVal = ((0x0000000CU << CRL_APB_IOPLL_CFG_RES_SHIFT - | 0x00000003U << CRL_APB_IOPLL_CFG_CP_SHIFT - | 0x00000003U << CRL_APB_IOPLL_CFG_LFHF_SHIFT - | 0x00000339U << CRL_APB_IOPLL_CFG_LOCK_CNT_SHIFT - | 0x0000003FU << CRL_APB_IOPLL_CFG_LOCK_DLY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_IOPLL_CFG_OFFSET ,0xFE7FEDEFU ,0x7E672C6CU); - /*############################################################################################################################ */ - - // : UPDATE FB_DIV - /*Register : IOPLL_CTRL @ 0XFF5E0020

- - Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_ - ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source - PSU_CRL_APB_IOPLL_CTRL_PRE_SRC 0x0 - - The integer portion of the feedback divider to the PLL - PSU_CRL_APB_IOPLL_CTRL_FBDIV 0x2d - - This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency - PSU_CRL_APB_IOPLL_CTRL_DIV2 0x0 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFF5E0020, 0x00717F00U ,0x00002D00U) - RegMask = (CRL_APB_IOPLL_CTRL_PRE_SRC_MASK | CRL_APB_IOPLL_CTRL_FBDIV_MASK | CRL_APB_IOPLL_CTRL_DIV2_MASK | 0 ); - - RegVal = ((0x00000000U << CRL_APB_IOPLL_CTRL_PRE_SRC_SHIFT - | 0x0000002DU << CRL_APB_IOPLL_CTRL_FBDIV_SHIFT - | 0x00000000U << CRL_APB_IOPLL_CTRL_DIV2_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_IOPLL_CTRL_OFFSET ,0x00717F00U ,0x00002D00U); - /*############################################################################################################################ */ - - // : BY PASS PLL - /*Register : IOPLL_CTRL @ 0XFF5E0020

- - Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_IOPLL_CTRL_BYPASS 1 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFF5E0020, 0x00000008U ,0x00000008U) - RegMask = (CRL_APB_IOPLL_CTRL_BYPASS_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_IOPLL_CTRL_BYPASS_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_IOPLL_CTRL_OFFSET ,0x00000008U ,0x00000008U); - /*############################################################################################################################ */ - - // : ASSERT RESET - /*Register : IOPLL_CTRL @ 0XFF5E0020

- - Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS. - PSU_CRL_APB_IOPLL_CTRL_RESET 1 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFF5E0020, 0x00000001U ,0x00000001U) - RegMask = (CRL_APB_IOPLL_CTRL_RESET_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_IOPLL_CTRL_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_IOPLL_CTRL_OFFSET ,0x00000001U ,0x00000001U); - /*############################################################################################################################ */ - - // : DEASSERT RESET - /*Register : IOPLL_CTRL @ 0XFF5E0020

- - Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS. - PSU_CRL_APB_IOPLL_CTRL_RESET 0 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFF5E0020, 0x00000001U ,0x00000000U) - RegMask = (CRL_APB_IOPLL_CTRL_RESET_MASK | 0 ); - - RegVal = ((0x00000000U << CRL_APB_IOPLL_CTRL_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_IOPLL_CTRL_OFFSET ,0x00000001U ,0x00000000U); - /*############################################################################################################################ */ - - // : CHECK PLL STATUS - /*Register : PLL_STATUS @ 0XFF5E0040

- - IOPLL is locked - PSU_CRL_APB_PLL_STATUS_IOPLL_LOCK 1 - (OFFSET, MASK, VALUE) (0XFF5E0040, 0x00000001U ,0x00000001U) */ - mask_poll(CRL_APB_PLL_STATUS_OFFSET,0x00000001U); - - /*############################################################################################################################ */ - - // : REMOVE PLL BY PASS - /*Register : IOPLL_CTRL @ 0XFF5E0020

- - Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_IOPLL_CTRL_BYPASS 0 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFF5E0020, 0x00000008U ,0x00000000U) - RegMask = (CRL_APB_IOPLL_CTRL_BYPASS_MASK | 0 ); - - RegVal = ((0x00000000U << CRL_APB_IOPLL_CTRL_BYPASS_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_IOPLL_CTRL_OFFSET ,0x00000008U ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : IOPLL_TO_FPD_CTRL @ 0XFF5E0044

- - Divisor value for this clock. - PSU_CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0 0x3 - - Control for a clock that will be generated in the LPD, but used in the FPD as a clock source for the peripheral clock muxes. - (OFFSET, MASK, VALUE) (0XFF5E0044, 0x00003F00U ,0x00000300U) - RegMask = (CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_MASK | 0 ); - - RegVal = ((0x00000003U << CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_IOPLL_TO_FPD_CTRL_OFFSET ,0x00003F00U ,0x00000300U); - /*############################################################################################################################ */ - - // : IOPLL FRAC CFG - /*Register : IOPLL_FRAC_CFG @ 0XFF5E0028

- - Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona - mode and uses DATA of this register for the fractional portion of the feedback divider. - PSU_CRL_APB_IOPLL_FRAC_CFG_ENABLED 0x0 - - Fractional value for the Feedback value. - PSU_CRL_APB_IOPLL_FRAC_CFG_DATA 0x0 - - Fractional control for the PLL - (OFFSET, MASK, VALUE) (0XFF5E0028, 0x8000FFFFU ,0x00000000U) - RegMask = (CRL_APB_IOPLL_FRAC_CFG_ENABLED_MASK | CRL_APB_IOPLL_FRAC_CFG_DATA_MASK | 0 ); - - RegVal = ((0x00000000U << CRL_APB_IOPLL_FRAC_CFG_ENABLED_SHIFT - | 0x00000000U << CRL_APB_IOPLL_FRAC_CFG_DATA_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_IOPLL_FRAC_CFG_OFFSET ,0x8000FFFFU ,0x00000000U); - /*############################################################################################################################ */ - - // : APU_PLL INIT - /*Register : APLL_CFG @ 0XFD1A0024

- - PLL loop filter resistor control - PSU_CRF_APB_APLL_CFG_RES 0x2 - - PLL charge pump control - PSU_CRF_APB_APLL_CFG_CP 0x3 - - PLL loop filter high frequency capacitor control - PSU_CRF_APB_APLL_CFG_LFHF 0x3 - - Lock circuit counter setting - PSU_CRF_APB_APLL_CFG_LOCK_CNT 0x258 - - Lock circuit configuration settings for lock windowsize - PSU_CRF_APB_APLL_CFG_LOCK_DLY 0x3f - - Helper data. Values are to be looked up in a table from Data Sheet - (OFFSET, MASK, VALUE) (0XFD1A0024, 0xFE7FEDEFU ,0x7E4B0C62U) - RegMask = (CRF_APB_APLL_CFG_RES_MASK | CRF_APB_APLL_CFG_CP_MASK | CRF_APB_APLL_CFG_LFHF_MASK | CRF_APB_APLL_CFG_LOCK_CNT_MASK | CRF_APB_APLL_CFG_LOCK_DLY_MASK | 0 ); - - RegVal = ((0x00000002U << CRF_APB_APLL_CFG_RES_SHIFT - | 0x00000003U << CRF_APB_APLL_CFG_CP_SHIFT - | 0x00000003U << CRF_APB_APLL_CFG_LFHF_SHIFT - | 0x00000258U << CRF_APB_APLL_CFG_LOCK_CNT_SHIFT - | 0x0000003FU << CRF_APB_APLL_CFG_LOCK_DLY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_APLL_CFG_OFFSET ,0xFE7FEDEFU ,0x7E4B0C62U); - /*############################################################################################################################ */ - - // : UPDATE FB_DIV - /*Register : APLL_CTRL @ 0XFD1A0020

- - Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_ - ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source - PSU_CRF_APB_APLL_CTRL_PRE_SRC 0x0 - - The integer portion of the feedback divider to the PLL - PSU_CRF_APB_APLL_CTRL_FBDIV 0x42 - - This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency - PSU_CRF_APB_APLL_CTRL_DIV2 0x1 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFD1A0020, 0x00717F00U ,0x00014200U) - RegMask = (CRF_APB_APLL_CTRL_PRE_SRC_MASK | CRF_APB_APLL_CTRL_FBDIV_MASK | CRF_APB_APLL_CTRL_DIV2_MASK | 0 ); - - RegVal = ((0x00000000U << CRF_APB_APLL_CTRL_PRE_SRC_SHIFT - | 0x00000042U << CRF_APB_APLL_CTRL_FBDIV_SHIFT - | 0x00000001U << CRF_APB_APLL_CTRL_DIV2_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_APLL_CTRL_OFFSET ,0x00717F00U ,0x00014200U); - /*############################################################################################################################ */ - - // : BY PASS PLL - /*Register : APLL_CTRL @ 0XFD1A0020

- - Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.) - PSU_CRF_APB_APLL_CTRL_BYPASS 1 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFD1A0020, 0x00000008U ,0x00000008U) - RegMask = (CRF_APB_APLL_CTRL_BYPASS_MASK | 0 ); - - RegVal = ((0x00000001U << CRF_APB_APLL_CTRL_BYPASS_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_APLL_CTRL_OFFSET ,0x00000008U ,0x00000008U); - /*############################################################################################################################ */ - - // : ASSERT RESET - /*Register : APLL_CTRL @ 0XFD1A0020

- - Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS. - PSU_CRF_APB_APLL_CTRL_RESET 1 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFD1A0020, 0x00000001U ,0x00000001U) - RegMask = (CRF_APB_APLL_CTRL_RESET_MASK | 0 ); - - RegVal = ((0x00000001U << CRF_APB_APLL_CTRL_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_APLL_CTRL_OFFSET ,0x00000001U ,0x00000001U); - /*############################################################################################################################ */ - - // : DEASSERT RESET - /*Register : APLL_CTRL @ 0XFD1A0020

- - Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS. - PSU_CRF_APB_APLL_CTRL_RESET 0 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFD1A0020, 0x00000001U ,0x00000000U) - RegMask = (CRF_APB_APLL_CTRL_RESET_MASK | 0 ); - - RegVal = ((0x00000000U << CRF_APB_APLL_CTRL_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_APLL_CTRL_OFFSET ,0x00000001U ,0x00000000U); - /*############################################################################################################################ */ - - // : CHECK PLL STATUS - /*Register : PLL_STATUS @ 0XFD1A0044

- - APLL is locked - PSU_CRF_APB_PLL_STATUS_APLL_LOCK 1 - (OFFSET, MASK, VALUE) (0XFD1A0044, 0x00000001U ,0x00000001U) */ - mask_poll(CRF_APB_PLL_STATUS_OFFSET,0x00000001U); - - /*############################################################################################################################ */ - - // : REMOVE PLL BY PASS - /*Register : APLL_CTRL @ 0XFD1A0020

- - Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.) - PSU_CRF_APB_APLL_CTRL_BYPASS 0 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFD1A0020, 0x00000008U ,0x00000000U) - RegMask = (CRF_APB_APLL_CTRL_BYPASS_MASK | 0 ); - - RegVal = ((0x00000000U << CRF_APB_APLL_CTRL_BYPASS_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_APLL_CTRL_OFFSET ,0x00000008U ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : APLL_TO_LPD_CTRL @ 0XFD1A0048

- - Divisor value for this clock. - PSU_CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0 0x3 - - Control for a clock that will be generated in the FPD, but used in the LPD as a clock source for the peripheral clock muxes. - (OFFSET, MASK, VALUE) (0XFD1A0048, 0x00003F00U ,0x00000300U) - RegMask = (CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_MASK | 0 ); - - RegVal = ((0x00000003U << CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_APLL_TO_LPD_CTRL_OFFSET ,0x00003F00U ,0x00000300U); - /*############################################################################################################################ */ - - // : APLL FRAC CFG - /*Register : APLL_FRAC_CFG @ 0XFD1A0028

- - Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona - mode and uses DATA of this register for the fractional portion of the feedback divider. - PSU_CRF_APB_APLL_FRAC_CFG_ENABLED 0x0 - - Fractional value for the Feedback value. - PSU_CRF_APB_APLL_FRAC_CFG_DATA 0x0 - - Fractional control for the PLL - (OFFSET, MASK, VALUE) (0XFD1A0028, 0x8000FFFFU ,0x00000000U) - RegMask = (CRF_APB_APLL_FRAC_CFG_ENABLED_MASK | CRF_APB_APLL_FRAC_CFG_DATA_MASK | 0 ); - - RegVal = ((0x00000000U << CRF_APB_APLL_FRAC_CFG_ENABLED_SHIFT - | 0x00000000U << CRF_APB_APLL_FRAC_CFG_DATA_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_APLL_FRAC_CFG_OFFSET ,0x8000FFFFU ,0x00000000U); - /*############################################################################################################################ */ - - // : DDR_PLL INIT - /*Register : DPLL_CFG @ 0XFD1A0030

- - PLL loop filter resistor control - PSU_CRF_APB_DPLL_CFG_RES 0x2 - - PLL charge pump control - PSU_CRF_APB_DPLL_CFG_CP 0x3 - - PLL loop filter high frequency capacitor control - PSU_CRF_APB_DPLL_CFG_LFHF 0x3 - - Lock circuit counter setting - PSU_CRF_APB_DPLL_CFG_LOCK_CNT 0x258 - - Lock circuit configuration settings for lock windowsize - PSU_CRF_APB_DPLL_CFG_LOCK_DLY 0x3f - - Helper data. Values are to be looked up in a table from Data Sheet - (OFFSET, MASK, VALUE) (0XFD1A0030, 0xFE7FEDEFU ,0x7E4B0C62U) - RegMask = (CRF_APB_DPLL_CFG_RES_MASK | CRF_APB_DPLL_CFG_CP_MASK | CRF_APB_DPLL_CFG_LFHF_MASK | CRF_APB_DPLL_CFG_LOCK_CNT_MASK | CRF_APB_DPLL_CFG_LOCK_DLY_MASK | 0 ); - - RegVal = ((0x00000002U << CRF_APB_DPLL_CFG_RES_SHIFT - | 0x00000003U << CRF_APB_DPLL_CFG_CP_SHIFT - | 0x00000003U << CRF_APB_DPLL_CFG_LFHF_SHIFT - | 0x00000258U << CRF_APB_DPLL_CFG_LOCK_CNT_SHIFT - | 0x0000003FU << CRF_APB_DPLL_CFG_LOCK_DLY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_DPLL_CFG_OFFSET ,0xFE7FEDEFU ,0x7E4B0C62U); - /*############################################################################################################################ */ - - // : UPDATE FB_DIV - /*Register : DPLL_CTRL @ 0XFD1A002C

- - Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_ - ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source - PSU_CRF_APB_DPLL_CTRL_PRE_SRC 0x0 - - The integer portion of the feedback divider to the PLL - PSU_CRF_APB_DPLL_CTRL_FBDIV 0x40 - - This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency - PSU_CRF_APB_DPLL_CTRL_DIV2 0x1 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFD1A002C, 0x00717F00U ,0x00014000U) - RegMask = (CRF_APB_DPLL_CTRL_PRE_SRC_MASK | CRF_APB_DPLL_CTRL_FBDIV_MASK | CRF_APB_DPLL_CTRL_DIV2_MASK | 0 ); - - RegVal = ((0x00000000U << CRF_APB_DPLL_CTRL_PRE_SRC_SHIFT - | 0x00000040U << CRF_APB_DPLL_CTRL_FBDIV_SHIFT - | 0x00000001U << CRF_APB_DPLL_CTRL_DIV2_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_DPLL_CTRL_OFFSET ,0x00717F00U ,0x00014000U); - /*############################################################################################################################ */ - - // : BY PASS PLL - /*Register : DPLL_CTRL @ 0XFD1A002C

- - Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.) - PSU_CRF_APB_DPLL_CTRL_BYPASS 1 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFD1A002C, 0x00000008U ,0x00000008U) - RegMask = (CRF_APB_DPLL_CTRL_BYPASS_MASK | 0 ); - - RegVal = ((0x00000001U << CRF_APB_DPLL_CTRL_BYPASS_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_DPLL_CTRL_OFFSET ,0x00000008U ,0x00000008U); - /*############################################################################################################################ */ - - // : ASSERT RESET - /*Register : DPLL_CTRL @ 0XFD1A002C

- - Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS. - PSU_CRF_APB_DPLL_CTRL_RESET 1 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFD1A002C, 0x00000001U ,0x00000001U) - RegMask = (CRF_APB_DPLL_CTRL_RESET_MASK | 0 ); - - RegVal = ((0x00000001U << CRF_APB_DPLL_CTRL_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_DPLL_CTRL_OFFSET ,0x00000001U ,0x00000001U); - /*############################################################################################################################ */ - - // : DEASSERT RESET - /*Register : DPLL_CTRL @ 0XFD1A002C

- - Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS. - PSU_CRF_APB_DPLL_CTRL_RESET 0 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFD1A002C, 0x00000001U ,0x00000000U) - RegMask = (CRF_APB_DPLL_CTRL_RESET_MASK | 0 ); - - RegVal = ((0x00000000U << CRF_APB_DPLL_CTRL_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_DPLL_CTRL_OFFSET ,0x00000001U ,0x00000000U); - /*############################################################################################################################ */ - - // : CHECK PLL STATUS - /*Register : PLL_STATUS @ 0XFD1A0044

- - DPLL is locked - PSU_CRF_APB_PLL_STATUS_DPLL_LOCK 1 - (OFFSET, MASK, VALUE) (0XFD1A0044, 0x00000002U ,0x00000002U) */ - mask_poll(CRF_APB_PLL_STATUS_OFFSET,0x00000002U); - - /*############################################################################################################################ */ - - // : REMOVE PLL BY PASS - /*Register : DPLL_CTRL @ 0XFD1A002C

- - Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.) - PSU_CRF_APB_DPLL_CTRL_BYPASS 0 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFD1A002C, 0x00000008U ,0x00000000U) - RegMask = (CRF_APB_DPLL_CTRL_BYPASS_MASK | 0 ); - - RegVal = ((0x00000000U << CRF_APB_DPLL_CTRL_BYPASS_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_DPLL_CTRL_OFFSET ,0x00000008U ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : DPLL_TO_LPD_CTRL @ 0XFD1A004C

- - Divisor value for this clock. - PSU_CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0 0x3 - - Control for a clock that will be generated in the FPD, but used in the LPD as a clock source for the peripheral clock muxes. - (OFFSET, MASK, VALUE) (0XFD1A004C, 0x00003F00U ,0x00000300U) - RegMask = (CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_MASK | 0 ); - - RegVal = ((0x00000003U << CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_DPLL_TO_LPD_CTRL_OFFSET ,0x00003F00U ,0x00000300U); - /*############################################################################################################################ */ - - // : DPLL FRAC CFG - /*Register : DPLL_FRAC_CFG @ 0XFD1A0034

- - Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona - mode and uses DATA of this register for the fractional portion of the feedback divider. - PSU_CRF_APB_DPLL_FRAC_CFG_ENABLED 0x0 - - Fractional value for the Feedback value. - PSU_CRF_APB_DPLL_FRAC_CFG_DATA 0x0 - - Fractional control for the PLL - (OFFSET, MASK, VALUE) (0XFD1A0034, 0x8000FFFFU ,0x00000000U) - RegMask = (CRF_APB_DPLL_FRAC_CFG_ENABLED_MASK | CRF_APB_DPLL_FRAC_CFG_DATA_MASK | 0 ); - - RegVal = ((0x00000000U << CRF_APB_DPLL_FRAC_CFG_ENABLED_SHIFT - | 0x00000000U << CRF_APB_DPLL_FRAC_CFG_DATA_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_DPLL_FRAC_CFG_OFFSET ,0x8000FFFFU ,0x00000000U); - /*############################################################################################################################ */ - - // : VIDEO_PLL INIT - /*Register : VPLL_CFG @ 0XFD1A003C

- - PLL loop filter resistor control - PSU_CRF_APB_VPLL_CFG_RES 0x2 - - PLL charge pump control - PSU_CRF_APB_VPLL_CFG_CP 0x3 - - PLL loop filter high frequency capacitor control - PSU_CRF_APB_VPLL_CFG_LFHF 0x3 - - Lock circuit counter setting - PSU_CRF_APB_VPLL_CFG_LOCK_CNT 0x28a - - Lock circuit configuration settings for lock windowsize - PSU_CRF_APB_VPLL_CFG_LOCK_DLY 0x3f - - Helper data. Values are to be looked up in a table from Data Sheet - (OFFSET, MASK, VALUE) (0XFD1A003C, 0xFE7FEDEFU ,0x7E514C62U) - RegMask = (CRF_APB_VPLL_CFG_RES_MASK | CRF_APB_VPLL_CFG_CP_MASK | CRF_APB_VPLL_CFG_LFHF_MASK | CRF_APB_VPLL_CFG_LOCK_CNT_MASK | CRF_APB_VPLL_CFG_LOCK_DLY_MASK | 0 ); - - RegVal = ((0x00000002U << CRF_APB_VPLL_CFG_RES_SHIFT - | 0x00000003U << CRF_APB_VPLL_CFG_CP_SHIFT - | 0x00000003U << CRF_APB_VPLL_CFG_LFHF_SHIFT - | 0x0000028AU << CRF_APB_VPLL_CFG_LOCK_CNT_SHIFT - | 0x0000003FU << CRF_APB_VPLL_CFG_LOCK_DLY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_VPLL_CFG_OFFSET ,0xFE7FEDEFU ,0x7E514C62U); - /*############################################################################################################################ */ - - // : UPDATE FB_DIV - /*Register : VPLL_CTRL @ 0XFD1A0038

- - Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_ - ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source - PSU_CRF_APB_VPLL_CTRL_PRE_SRC 0x0 - - The integer portion of the feedback divider to the PLL - PSU_CRF_APB_VPLL_CTRL_FBDIV 0x39 - - This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency - PSU_CRF_APB_VPLL_CTRL_DIV2 0x1 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFD1A0038, 0x00717F00U ,0x00013900U) - RegMask = (CRF_APB_VPLL_CTRL_PRE_SRC_MASK | CRF_APB_VPLL_CTRL_FBDIV_MASK | CRF_APB_VPLL_CTRL_DIV2_MASK | 0 ); - - RegVal = ((0x00000000U << CRF_APB_VPLL_CTRL_PRE_SRC_SHIFT - | 0x00000039U << CRF_APB_VPLL_CTRL_FBDIV_SHIFT - | 0x00000001U << CRF_APB_VPLL_CTRL_DIV2_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_VPLL_CTRL_OFFSET ,0x00717F00U ,0x00013900U); - /*############################################################################################################################ */ - - // : BY PASS PLL - /*Register : VPLL_CTRL @ 0XFD1A0038

- - Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.) - PSU_CRF_APB_VPLL_CTRL_BYPASS 1 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFD1A0038, 0x00000008U ,0x00000008U) - RegMask = (CRF_APB_VPLL_CTRL_BYPASS_MASK | 0 ); - - RegVal = ((0x00000001U << CRF_APB_VPLL_CTRL_BYPASS_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_VPLL_CTRL_OFFSET ,0x00000008U ,0x00000008U); - /*############################################################################################################################ */ - - // : ASSERT RESET - /*Register : VPLL_CTRL @ 0XFD1A0038

- - Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS. - PSU_CRF_APB_VPLL_CTRL_RESET 1 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFD1A0038, 0x00000001U ,0x00000001U) - RegMask = (CRF_APB_VPLL_CTRL_RESET_MASK | 0 ); - - RegVal = ((0x00000001U << CRF_APB_VPLL_CTRL_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_VPLL_CTRL_OFFSET ,0x00000001U ,0x00000001U); - /*############################################################################################################################ */ - - // : DEASSERT RESET - /*Register : VPLL_CTRL @ 0XFD1A0038

- - Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS. - PSU_CRF_APB_VPLL_CTRL_RESET 0 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFD1A0038, 0x00000001U ,0x00000000U) - RegMask = (CRF_APB_VPLL_CTRL_RESET_MASK | 0 ); - - RegVal = ((0x00000000U << CRF_APB_VPLL_CTRL_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_VPLL_CTRL_OFFSET ,0x00000001U ,0x00000000U); - /*############################################################################################################################ */ - - // : CHECK PLL STATUS - /*Register : PLL_STATUS @ 0XFD1A0044

- - VPLL is locked - PSU_CRF_APB_PLL_STATUS_VPLL_LOCK 1 - (OFFSET, MASK, VALUE) (0XFD1A0044, 0x00000004U ,0x00000004U) */ - mask_poll(CRF_APB_PLL_STATUS_OFFSET,0x00000004U); - - /*############################################################################################################################ */ - - // : REMOVE PLL BY PASS - /*Register : VPLL_CTRL @ 0XFD1A0038

- - Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.) - PSU_CRF_APB_VPLL_CTRL_BYPASS 0 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFD1A0038, 0x00000008U ,0x00000000U) - RegMask = (CRF_APB_VPLL_CTRL_BYPASS_MASK | 0 ); - - RegVal = ((0x00000000U << CRF_APB_VPLL_CTRL_BYPASS_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_VPLL_CTRL_OFFSET ,0x00000008U ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : VPLL_TO_LPD_CTRL @ 0XFD1A0050

- - Divisor value for this clock. - PSU_CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0 0x3 - - Control for a clock that will be generated in the FPD, but used in the LPD as a clock source for the peripheral clock muxes. - (OFFSET, MASK, VALUE) (0XFD1A0050, 0x00003F00U ,0x00000300U) - RegMask = (CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_MASK | 0 ); - - RegVal = ((0x00000003U << CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_VPLL_TO_LPD_CTRL_OFFSET ,0x00003F00U ,0x00000300U); - /*############################################################################################################################ */ - - // : VIDEO FRAC CFG - /*Register : VPLL_FRAC_CFG @ 0XFD1A0040

- - Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona - mode and uses DATA of this register for the fractional portion of the feedback divider. - PSU_CRF_APB_VPLL_FRAC_CFG_ENABLED 0x1 - - Fractional value for the Feedback value. - PSU_CRF_APB_VPLL_FRAC_CFG_DATA 0x820c - - Fractional control for the PLL - (OFFSET, MASK, VALUE) (0XFD1A0040, 0x8000FFFFU ,0x8000820CU) - RegMask = (CRF_APB_VPLL_FRAC_CFG_ENABLED_MASK | CRF_APB_VPLL_FRAC_CFG_DATA_MASK | 0 ); - - RegVal = ((0x00000001U << CRF_APB_VPLL_FRAC_CFG_ENABLED_SHIFT - | 0x0000820CU << CRF_APB_VPLL_FRAC_CFG_DATA_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_VPLL_FRAC_CFG_OFFSET ,0x8000FFFFU ,0x8000820CU); - /*############################################################################################################################ */ - - - return 1; + Xil_Out32(addr, rdata); + } + +unsigned long psu_pll_init_data(void) +{ + /* + * RPLL INIT + */ + /* + * Register : RPLL_CFG @ 0XFF5E0034 + + * PLL loop filter resistor control + * PSU_CRL_APB_RPLL_CFG_RES 0xc + + * PLL charge pump control + * PSU_CRL_APB_RPLL_CFG_CP 0x3 + + * PLL loop filter high frequency capacitor control + * PSU_CRL_APB_RPLL_CFG_LFHF 0x3 + + * Lock circuit counter setting + * PSU_CRL_APB_RPLL_CFG_LOCK_CNT 0x339 + + * Lock circuit configuration settings for lock windowsize + * PSU_CRL_APB_RPLL_CFG_LOCK_DLY 0x3f + + * Helper data. Values are to be looked up in a table from Data Sheet + * (OFFSET, MASK, VALUE) (0XFF5E0034, 0xFE7FEDEFU ,0x7E672C6CU) + */ + PSU_Mask_Write(CRL_APB_RPLL_CFG_OFFSET, 0xFE7FEDEFU, 0x7E672C6CU); +/*##################################################################### */ + + /* + * UPDATE FB_DIV + */ + /* + * Register : RPLL_CTRL @ 0XFF5E0030 + + * Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i + * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour + * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source + * PSU_CRL_APB_RPLL_CTRL_PRE_SRC 0x0 + + * The integer portion of the feedback divider to the PLL + * PSU_CRL_APB_RPLL_CTRL_FBDIV 0x2d + + * This turns on the divide by 2 that is inside of the PLL. This does not c + * hange the VCO frequency, just the output frequency + * PSU_CRL_APB_RPLL_CTRL_DIV2 0x1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFF5E0030, 0x00717F00U ,0x00012D00U) + */ + PSU_Mask_Write(CRL_APB_RPLL_CTRL_OFFSET, 0x00717F00U, 0x00012D00U); +/*##################################################################### */ + + /* + * BY PASS PLL + */ + /* + * Register : RPLL_CTRL @ 0XFF5E0030 + + * Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) + * PSU_CRL_APB_RPLL_CTRL_BYPASS 1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFF5E0030, 0x00000008U ,0x00000008U) + */ + PSU_Mask_Write(CRL_APB_RPLL_CTRL_OFFSET, 0x00000008U, 0x00000008U); +/*##################################################################### */ + + /* + * ASSERT RESET + */ + /* + * Register : RPLL_CTRL @ 0XFF5E0030 + + * Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. + * PSU_CRL_APB_RPLL_CTRL_RESET 1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFF5E0030, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(CRL_APB_RPLL_CTRL_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * DEASSERT RESET + */ + /* + * Register : RPLL_CTRL @ 0XFF5E0030 + + * Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. + * PSU_CRL_APB_RPLL_CTRL_RESET 0 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFF5E0030, 0x00000001U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RPLL_CTRL_OFFSET, 0x00000001U, 0x00000000U); +/*##################################################################### */ + + /* + * CHECK PLL STATUS + */ + /* + * Register : PLL_STATUS @ 0XFF5E0040 + + * RPLL is locked + * PSU_CRL_APB_PLL_STATUS_RPLL_LOCK 1 + * (OFFSET, MASK, VALUE) (0XFF5E0040, 0x00000002U ,0x00000002U) + */ + mask_poll(CRL_APB_PLL_STATUS_OFFSET, 0x00000002U); + +/*##################################################################### */ + + /* + * REMOVE PLL BY PASS + */ + /* + * Register : RPLL_CTRL @ 0XFF5E0030 + + * Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) + * PSU_CRL_APB_RPLL_CTRL_BYPASS 0 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFF5E0030, 0x00000008U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RPLL_CTRL_OFFSET, 0x00000008U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : RPLL_TO_FPD_CTRL @ 0XFF5E0048 + + * Divisor value for this clock. + * PSU_CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0 0x2 + + * Control for a clock that will be generated in the LPD, but used in the F + * PD as a clock source for the peripheral clock muxes. + * (OFFSET, MASK, VALUE) (0XFF5E0048, 0x00003F00U ,0x00000200U) + */ + PSU_Mask_Write(CRL_APB_RPLL_TO_FPD_CTRL_OFFSET, + 0x00003F00U, 0x00000200U); +/*##################################################################### */ + + /* + * RPLL FRAC CFG + */ + /* + * IOPLL INIT + */ + /* + * Register : IOPLL_CFG @ 0XFF5E0024 + + * PLL loop filter resistor control + * PSU_CRL_APB_IOPLL_CFG_RES 0x2 + + * PLL charge pump control + * PSU_CRL_APB_IOPLL_CFG_CP 0x4 + + * PLL loop filter high frequency capacitor control + * PSU_CRL_APB_IOPLL_CFG_LFHF 0x3 + + * Lock circuit counter setting + * PSU_CRL_APB_IOPLL_CFG_LOCK_CNT 0x258 + + * Lock circuit configuration settings for lock windowsize + * PSU_CRL_APB_IOPLL_CFG_LOCK_DLY 0x3f + + * Helper data. Values are to be looked up in a table from Data Sheet + * (OFFSET, MASK, VALUE) (0XFF5E0024, 0xFE7FEDEFU ,0x7E4B0C82U) + */ + PSU_Mask_Write(CRL_APB_IOPLL_CFG_OFFSET, 0xFE7FEDEFU, 0x7E4B0C82U); +/*##################################################################### */ + + /* + * UPDATE FB_DIV + */ + /* + * Register : IOPLL_CTRL @ 0XFF5E0020 + + * Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i + * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour + * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source + * PSU_CRL_APB_IOPLL_CTRL_PRE_SRC 0x0 + + * The integer portion of the feedback divider to the PLL + * PSU_CRL_APB_IOPLL_CTRL_FBDIV 0x5a + + * This turns on the divide by 2 that is inside of the PLL. This does not c + * hange the VCO frequency, just the output frequency + * PSU_CRL_APB_IOPLL_CTRL_DIV2 0x1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFF5E0020, 0x00717F00U ,0x00015A00U) + */ + PSU_Mask_Write(CRL_APB_IOPLL_CTRL_OFFSET, 0x00717F00U, 0x00015A00U); +/*##################################################################### */ + + /* + * BY PASS PLL + */ + /* + * Register : IOPLL_CTRL @ 0XFF5E0020 + + * Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) + * PSU_CRL_APB_IOPLL_CTRL_BYPASS 1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFF5E0020, 0x00000008U ,0x00000008U) + */ + PSU_Mask_Write(CRL_APB_IOPLL_CTRL_OFFSET, 0x00000008U, 0x00000008U); +/*##################################################################### */ + + /* + * ASSERT RESET + */ + /* + * Register : IOPLL_CTRL @ 0XFF5E0020 + + * Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. + * PSU_CRL_APB_IOPLL_CTRL_RESET 1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFF5E0020, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(CRL_APB_IOPLL_CTRL_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * DEASSERT RESET + */ + /* + * Register : IOPLL_CTRL @ 0XFF5E0020 + + * Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. + * PSU_CRL_APB_IOPLL_CTRL_RESET 0 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFF5E0020, 0x00000001U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_IOPLL_CTRL_OFFSET, 0x00000001U, 0x00000000U); +/*##################################################################### */ + + /* + * CHECK PLL STATUS + */ + /* + * Register : PLL_STATUS @ 0XFF5E0040 + + * IOPLL is locked + * PSU_CRL_APB_PLL_STATUS_IOPLL_LOCK 1 + * (OFFSET, MASK, VALUE) (0XFF5E0040, 0x00000001U ,0x00000001U) + */ + mask_poll(CRL_APB_PLL_STATUS_OFFSET, 0x00000001U); + +/*##################################################################### */ + + /* + * REMOVE PLL BY PASS + */ + /* + * Register : IOPLL_CTRL @ 0XFF5E0020 + + * Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) + * PSU_CRL_APB_IOPLL_CTRL_BYPASS 0 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFF5E0020, 0x00000008U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_IOPLL_CTRL_OFFSET, 0x00000008U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : IOPLL_TO_FPD_CTRL @ 0XFF5E0044 + + * Divisor value for this clock. + * PSU_CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0 0x3 + + * Control for a clock that will be generated in the LPD, but used in the F + * PD as a clock source for the peripheral clock muxes. + * (OFFSET, MASK, VALUE) (0XFF5E0044, 0x00003F00U ,0x00000300U) + */ + PSU_Mask_Write(CRL_APB_IOPLL_TO_FPD_CTRL_OFFSET, + 0x00003F00U, 0x00000300U); +/*##################################################################### */ + + /* + * IOPLL FRAC CFG + */ + /* + * APU_PLL INIT + */ + /* + * Register : APLL_CFG @ 0XFD1A0024 + + * PLL loop filter resistor control + * PSU_CRF_APB_APLL_CFG_RES 0x2 + + * PLL charge pump control + * PSU_CRF_APB_APLL_CFG_CP 0x3 + + * PLL loop filter high frequency capacitor control + * PSU_CRF_APB_APLL_CFG_LFHF 0x3 + + * Lock circuit counter setting + * PSU_CRF_APB_APLL_CFG_LOCK_CNT 0x258 + + * Lock circuit configuration settings for lock windowsize + * PSU_CRF_APB_APLL_CFG_LOCK_DLY 0x3f + + * Helper data. Values are to be looked up in a table from Data Sheet + * (OFFSET, MASK, VALUE) (0XFD1A0024, 0xFE7FEDEFU ,0x7E4B0C62U) + */ + PSU_Mask_Write(CRF_APB_APLL_CFG_OFFSET, 0xFE7FEDEFU, 0x7E4B0C62U); +/*##################################################################### */ + + /* + * UPDATE FB_DIV + */ + /* + * Register : APLL_CTRL @ 0XFD1A0020 + + * Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i + * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour + * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source + * PSU_CRF_APB_APLL_CTRL_PRE_SRC 0x0 + + * The integer portion of the feedback divider to the PLL + * PSU_CRF_APB_APLL_CTRL_FBDIV 0x48 + + * This turns on the divide by 2 that is inside of the PLL. This does not c + * hange the VCO frequency, just the output frequency + * PSU_CRF_APB_APLL_CTRL_DIV2 0x1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A0020, 0x00717F00U ,0x00014800U) + */ + PSU_Mask_Write(CRF_APB_APLL_CTRL_OFFSET, 0x00717F00U, 0x00014800U); +/*##################################################################### */ + + /* + * BY PASS PLL + */ + /* + * Register : APLL_CTRL @ 0XFD1A0020 + + * Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) + * PSU_CRF_APB_APLL_CTRL_BYPASS 1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A0020, 0x00000008U ,0x00000008U) + */ + PSU_Mask_Write(CRF_APB_APLL_CTRL_OFFSET, 0x00000008U, 0x00000008U); +/*##################################################################### */ + + /* + * ASSERT RESET + */ + /* + * Register : APLL_CTRL @ 0XFD1A0020 + + * Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. + * PSU_CRF_APB_APLL_CTRL_RESET 1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A0020, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(CRF_APB_APLL_CTRL_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * DEASSERT RESET + */ + /* + * Register : APLL_CTRL @ 0XFD1A0020 + + * Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. + * PSU_CRF_APB_APLL_CTRL_RESET 0 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A0020, 0x00000001U ,0x00000000U) + */ + PSU_Mask_Write(CRF_APB_APLL_CTRL_OFFSET, 0x00000001U, 0x00000000U); +/*##################################################################### */ + + /* + * CHECK PLL STATUS + */ + /* + * Register : PLL_STATUS @ 0XFD1A0044 + + * APLL is locked + * PSU_CRF_APB_PLL_STATUS_APLL_LOCK 1 + * (OFFSET, MASK, VALUE) (0XFD1A0044, 0x00000001U ,0x00000001U) + */ + mask_poll(CRF_APB_PLL_STATUS_OFFSET, 0x00000001U); + +/*##################################################################### */ + + /* + * REMOVE PLL BY PASS + */ + /* + * Register : APLL_CTRL @ 0XFD1A0020 + + * Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) + * PSU_CRF_APB_APLL_CTRL_BYPASS 0 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A0020, 0x00000008U ,0x00000000U) + */ + PSU_Mask_Write(CRF_APB_APLL_CTRL_OFFSET, 0x00000008U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : APLL_TO_LPD_CTRL @ 0XFD1A0048 + + * Divisor value for this clock. + * PSU_CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0 0x3 + + * Control for a clock that will be generated in the FPD, but used in the L + * PD as a clock source for the peripheral clock muxes. + * (OFFSET, MASK, VALUE) (0XFD1A0048, 0x00003F00U ,0x00000300U) + */ + PSU_Mask_Write(CRF_APB_APLL_TO_LPD_CTRL_OFFSET, + 0x00003F00U, 0x00000300U); +/*##################################################################### */ + + /* + * APLL FRAC CFG + */ + /* + * DDR_PLL INIT + */ + /* + * Register : DPLL_CFG @ 0XFD1A0030 + + * PLL loop filter resistor control + * PSU_CRF_APB_DPLL_CFG_RES 0x2 + + * PLL charge pump control + * PSU_CRF_APB_DPLL_CFG_CP 0x3 + + * PLL loop filter high frequency capacitor control + * PSU_CRF_APB_DPLL_CFG_LFHF 0x3 + + * Lock circuit counter setting + * PSU_CRF_APB_DPLL_CFG_LOCK_CNT 0x258 + + * Lock circuit configuration settings for lock windowsize + * PSU_CRF_APB_DPLL_CFG_LOCK_DLY 0x3f + + * Helper data. Values are to be looked up in a table from Data Sheet + * (OFFSET, MASK, VALUE) (0XFD1A0030, 0xFE7FEDEFU ,0x7E4B0C62U) + */ + PSU_Mask_Write(CRF_APB_DPLL_CFG_OFFSET, 0xFE7FEDEFU, 0x7E4B0C62U); +/*##################################################################### */ + + /* + * UPDATE FB_DIV + */ + /* + * Register : DPLL_CTRL @ 0XFD1A002C + + * Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i + * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour + * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source + * PSU_CRF_APB_DPLL_CTRL_PRE_SRC 0x0 + + * The integer portion of the feedback divider to the PLL + * PSU_CRF_APB_DPLL_CTRL_FBDIV 0x40 + + * This turns on the divide by 2 that is inside of the PLL. This does not c + * hange the VCO frequency, just the output frequency + * PSU_CRF_APB_DPLL_CTRL_DIV2 0x1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A002C, 0x00717F00U ,0x00014000U) + */ + PSU_Mask_Write(CRF_APB_DPLL_CTRL_OFFSET, 0x00717F00U, 0x00014000U); +/*##################################################################### */ + + /* + * BY PASS PLL + */ + /* + * Register : DPLL_CTRL @ 0XFD1A002C + + * Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) + * PSU_CRF_APB_DPLL_CTRL_BYPASS 1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A002C, 0x00000008U ,0x00000008U) + */ + PSU_Mask_Write(CRF_APB_DPLL_CTRL_OFFSET, 0x00000008U, 0x00000008U); +/*##################################################################### */ + + /* + * ASSERT RESET + */ + /* + * Register : DPLL_CTRL @ 0XFD1A002C + + * Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. + * PSU_CRF_APB_DPLL_CTRL_RESET 1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A002C, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(CRF_APB_DPLL_CTRL_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * DEASSERT RESET + */ + /* + * Register : DPLL_CTRL @ 0XFD1A002C + + * Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. + * PSU_CRF_APB_DPLL_CTRL_RESET 0 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A002C, 0x00000001U ,0x00000000U) + */ + PSU_Mask_Write(CRF_APB_DPLL_CTRL_OFFSET, 0x00000001U, 0x00000000U); +/*##################################################################### */ + + /* + * CHECK PLL STATUS + */ + /* + * Register : PLL_STATUS @ 0XFD1A0044 + + * DPLL is locked + * PSU_CRF_APB_PLL_STATUS_DPLL_LOCK 1 + * (OFFSET, MASK, VALUE) (0XFD1A0044, 0x00000002U ,0x00000002U) + */ + mask_poll(CRF_APB_PLL_STATUS_OFFSET, 0x00000002U); + +/*##################################################################### */ + + /* + * REMOVE PLL BY PASS + */ + /* + * Register : DPLL_CTRL @ 0XFD1A002C + + * Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) + * PSU_CRF_APB_DPLL_CTRL_BYPASS 0 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A002C, 0x00000008U ,0x00000000U) + */ + PSU_Mask_Write(CRF_APB_DPLL_CTRL_OFFSET, 0x00000008U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : DPLL_TO_LPD_CTRL @ 0XFD1A004C + + * Divisor value for this clock. + * PSU_CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0 0x2 + + * Control for a clock that will be generated in the FPD, but used in the L + * PD as a clock source for the peripheral clock muxes. + * (OFFSET, MASK, VALUE) (0XFD1A004C, 0x00003F00U ,0x00000200U) + */ + PSU_Mask_Write(CRF_APB_DPLL_TO_LPD_CTRL_OFFSET, + 0x00003F00U, 0x00000200U); +/*##################################################################### */ + + /* + * DPLL FRAC CFG + */ + /* + * VIDEO_PLL INIT + */ + /* + * Register : VPLL_CFG @ 0XFD1A003C + + * PLL loop filter resistor control + * PSU_CRF_APB_VPLL_CFG_RES 0x2 + + * PLL charge pump control + * PSU_CRF_APB_VPLL_CFG_CP 0x4 + + * PLL loop filter high frequency capacitor control + * PSU_CRF_APB_VPLL_CFG_LFHF 0x3 + + * Lock circuit counter setting + * PSU_CRF_APB_VPLL_CFG_LOCK_CNT 0x258 + + * Lock circuit configuration settings for lock windowsize + * PSU_CRF_APB_VPLL_CFG_LOCK_DLY 0x3f + + * Helper data. Values are to be looked up in a table from Data Sheet + * (OFFSET, MASK, VALUE) (0XFD1A003C, 0xFE7FEDEFU ,0x7E4B0C82U) + */ + PSU_Mask_Write(CRF_APB_VPLL_CFG_OFFSET, 0xFE7FEDEFU, 0x7E4B0C82U); +/*##################################################################### */ + + /* + * UPDATE FB_DIV + */ + /* + * Register : VPLL_CTRL @ 0XFD1A0038 + + * Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i + * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour + * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source + * PSU_CRF_APB_VPLL_CTRL_PRE_SRC 0x0 + + * The integer portion of the feedback divider to the PLL + * PSU_CRF_APB_VPLL_CTRL_FBDIV 0x5a + + * This turns on the divide by 2 that is inside of the PLL. This does not c + * hange the VCO frequency, just the output frequency + * PSU_CRF_APB_VPLL_CTRL_DIV2 0x1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A0038, 0x00717F00U ,0x00015A00U) + */ + PSU_Mask_Write(CRF_APB_VPLL_CTRL_OFFSET, 0x00717F00U, 0x00015A00U); +/*##################################################################### */ + + /* + * BY PASS PLL + */ + /* + * Register : VPLL_CTRL @ 0XFD1A0038 + + * Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) + * PSU_CRF_APB_VPLL_CTRL_BYPASS 1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A0038, 0x00000008U ,0x00000008U) + */ + PSU_Mask_Write(CRF_APB_VPLL_CTRL_OFFSET, 0x00000008U, 0x00000008U); +/*##################################################################### */ + + /* + * ASSERT RESET + */ + /* + * Register : VPLL_CTRL @ 0XFD1A0038 + + * Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. + * PSU_CRF_APB_VPLL_CTRL_RESET 1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A0038, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(CRF_APB_VPLL_CTRL_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * DEASSERT RESET + */ + /* + * Register : VPLL_CTRL @ 0XFD1A0038 + + * Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. + * PSU_CRF_APB_VPLL_CTRL_RESET 0 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A0038, 0x00000001U ,0x00000000U) + */ + PSU_Mask_Write(CRF_APB_VPLL_CTRL_OFFSET, 0x00000001U, 0x00000000U); +/*##################################################################### */ + + /* + * CHECK PLL STATUS + */ + /* + * Register : PLL_STATUS @ 0XFD1A0044 + + * VPLL is locked + * PSU_CRF_APB_PLL_STATUS_VPLL_LOCK 1 + * (OFFSET, MASK, VALUE) (0XFD1A0044, 0x00000004U ,0x00000004U) + */ + mask_poll(CRF_APB_PLL_STATUS_OFFSET, 0x00000004U); + +/*##################################################################### */ + + /* + * REMOVE PLL BY PASS + */ + /* + * Register : VPLL_CTRL @ 0XFD1A0038 + + * Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) + * PSU_CRF_APB_VPLL_CTRL_BYPASS 0 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A0038, 0x00000008U ,0x00000000U) + */ + PSU_Mask_Write(CRF_APB_VPLL_CTRL_OFFSET, 0x00000008U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : VPLL_TO_LPD_CTRL @ 0XFD1A0050 + + * Divisor value for this clock. + * PSU_CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0 0x3 + + * Control for a clock that will be generated in the FPD, but used in the L + * PD as a clock source for the peripheral clock muxes. + * (OFFSET, MASK, VALUE) (0XFD1A0050, 0x00003F00U ,0x00000300U) + */ + PSU_Mask_Write(CRF_APB_VPLL_TO_LPD_CTRL_OFFSET, + 0x00003F00U, 0x00000300U); +/*##################################################################### */ + + /* + * VIDEO FRAC CFG + */ + + return 1; } -unsigned long psu_clock_init_data() { - // : CLOCK CONTROL SLCR REGISTER - /*Register : GEM3_REF_CTRL @ 0XFF5E005C

+unsigned long psu_clock_init_data(void) +{ + /* + * CLOCK CONTROL SLCR REGISTER + */ + /* + * Register : GEM3_REF_CTRL @ 0XFF5E005C + + * Clock active for the RX channel + * PSU_CRL_APB_GEM3_REF_CTRL_RX_CLKACT 0x1 - Clock active for the RX channel - PSU_CRL_APB_GEM3_REF_CTRL_RX_CLKACT 0x1 + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_GEM3_REF_CTRL_CLKACT 0x1 - Clock active signal. Switch to 0 to disable the clock - PSU_CRL_APB_GEM3_REF_CTRL_CLKACT 0x1 + * 6 bit divider + * PSU_CRL_APB_GEM3_REF_CTRL_DIVISOR1 0x1 - 6 bit divider - PSU_CRL_APB_GEM3_REF_CTRL_DIVISOR1 0x1 + * 6 bit divider + * PSU_CRL_APB_GEM3_REF_CTRL_DIVISOR0 0xc + + * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_GEM3_REF_CTRL_SRCSEL 0x0 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E005C, 0x063F3F07U ,0x06010C00U) + */ + PSU_Mask_Write(CRL_APB_GEM3_REF_CTRL_OFFSET, + 0x063F3F07U, 0x06010C00U); +/*##################################################################### */ + + /* + * Register : GEM_TSU_REF_CTRL @ 0XFF5E0100 - 6 bit divider - PSU_CRL_APB_GEM3_REF_CTRL_DIVISOR0 0xc + * 6 bit divider + * PSU_CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0 0x6 - 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_GEM3_REF_CTRL_SRCSEL 0x0 + * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_GEM_TSU_REF_CTRL_SRCSEL 0x0 - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E005C, 0x063F3F07U ,0x06010C00U) - RegMask = (CRL_APB_GEM3_REF_CTRL_RX_CLKACT_MASK | CRL_APB_GEM3_REF_CTRL_CLKACT_MASK | CRL_APB_GEM3_REF_CTRL_DIVISOR1_MASK | CRL_APB_GEM3_REF_CTRL_DIVISOR0_MASK | CRL_APB_GEM3_REF_CTRL_SRCSEL_MASK | 0 ); + * 6 bit divider + * PSU_CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1 0x1 - RegVal = ((0x00000001U << CRL_APB_GEM3_REF_CTRL_RX_CLKACT_SHIFT - | 0x00000001U << CRL_APB_GEM3_REF_CTRL_CLKACT_SHIFT - | 0x00000001U << CRL_APB_GEM3_REF_CTRL_DIVISOR1_SHIFT - | 0x0000000CU << CRL_APB_GEM3_REF_CTRL_DIVISOR0_SHIFT - | 0x00000000U << CRL_APB_GEM3_REF_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_GEM3_REF_CTRL_OFFSET ,0x063F3F07U ,0x06010C00U); - /*############################################################################################################################ */ + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_GEM_TSU_REF_CTRL_CLKACT 0x1 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E0100, 0x013F3F07U ,0x01010600U) + */ + PSU_Mask_Write(CRL_APB_GEM_TSU_REF_CTRL_OFFSET, + 0x013F3F07U, 0x01010600U); +/*##################################################################### */ + + /* + * Register : USB0_BUS_REF_CTRL @ 0XFF5E0060 - /*Register : USB0_BUS_REF_CTRL @ 0XFF5E0060

+ * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_USB0_BUS_REF_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1 0x1 + + * 6 bit divider + * PSU_CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0 0x6 + + * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_USB0_BUS_REF_CTRL_SRCSEL 0x0 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E0060, 0x023F3F07U ,0x02010600U) + */ + PSU_Mask_Write(CRL_APB_USB0_BUS_REF_CTRL_OFFSET, + 0x023F3F07U, 0x02010600U); +/*##################################################################### */ + + /* + * Register : USB3_DUAL_REF_CTRL @ 0XFF5E004C - Clock active signal. Switch to 0 to disable the clock - PSU_CRL_APB_USB0_BUS_REF_CTRL_CLKACT 0x1 + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_USB3_DUAL_REF_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1 0x3 + + * 6 bit divider + * PSU_CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0 0x19 + + * 000 = IOPLL; 010 = RPLL; 011 = DPLL. (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL 0x0 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E004C, 0x023F3F07U ,0x02031900U) + */ + PSU_Mask_Write(CRL_APB_USB3_DUAL_REF_CTRL_OFFSET, + 0x023F3F07U, 0x02031900U); +/*##################################################################### */ - 6 bit divider - PSU_CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1 0x1 + /* + * Register : QSPI_REF_CTRL @ 0XFF5E0068 - 6 bit divider - PSU_CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0 0x6 + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_QSPI_REF_CTRL_CLKACT 0x1 - 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_USB0_BUS_REF_CTRL_SRCSEL 0x0 + * 6 bit divider + * PSU_CRL_APB_QSPI_REF_CTRL_DIVISOR1 0x1 + + * 6 bit divider + * PSU_CRL_APB_QSPI_REF_CTRL_DIVISOR0 0xc + + * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_QSPI_REF_CTRL_SRCSEL 0x0 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E0068, 0x013F3F07U ,0x01010C00U) + */ + PSU_Mask_Write(CRL_APB_QSPI_REF_CTRL_OFFSET, + 0x013F3F07U, 0x01010C00U); +/*##################################################################### */ - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E0060, 0x023F3F07U ,0x02010600U) - RegMask = (CRL_APB_USB0_BUS_REF_CTRL_CLKACT_MASK | CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_MASK | CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_MASK | CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_MASK | 0 ); + /* + * Register : SDIO1_REF_CTRL @ 0XFF5E0070 - RegVal = ((0x00000001U << CRL_APB_USB0_BUS_REF_CTRL_CLKACT_SHIFT - | 0x00000001U << CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_SHIFT - | 0x00000006U << CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_SHIFT - | 0x00000000U << CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_USB0_BUS_REF_CTRL_OFFSET ,0x023F3F07U ,0x02010600U); - /*############################################################################################################################ */ + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_SDIO1_REF_CTRL_CLKACT 0x1 - /*Register : USB3_DUAL_REF_CTRL @ 0XFF5E004C

+ * 6 bit divider + * PSU_CRL_APB_SDIO1_REF_CTRL_DIVISOR1 0x1 + + * 6 bit divider + * PSU_CRL_APB_SDIO1_REF_CTRL_DIVISOR0 0x8 + + * 000 = IOPLL; 010 = RPLL; 011 = VPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_SDIO1_REF_CTRL_SRCSEL 0x0 - Clock active signal. Switch to 0 to disable the clock - PSU_CRL_APB_USB3_DUAL_REF_CTRL_CLKACT 0x1 + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E0070, 0x013F3F07U ,0x01010800U) + */ + PSU_Mask_Write(CRL_APB_SDIO1_REF_CTRL_OFFSET, + 0x013F3F07U, 0x01010800U); +/*##################################################################### */ - 6 bit divider - PSU_CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1 0xf + /* + * Register : SDIO_CLK_CTRL @ 0XFF18030C - 6 bit divider - PSU_CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0 0x5 + * MIO pad selection for sdio1_rx_clk (feedback clock from the PAD) 0: MIO + * [51] 1: MIO [76] + * PSU_IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL 0 - 000 = IOPLL; 010 = RPLL; 011 = DPLL. (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL 0x0 + * SoC Debug Clock Control + * (OFFSET, MASK, VALUE) (0XFF18030C, 0x00020000U ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_SDIO_CLK_CTRL_OFFSET, + 0x00020000U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : UART0_REF_CTRL @ 0XFF5E0074 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_UART0_REF_CTRL_CLKACT 0x1 - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E004C, 0x023F3F07U ,0x020F0500U) - RegMask = (CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_MASK | CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_MASK | CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_MASK | CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_MASK | 0 ); + * 6 bit divider + * PSU_CRL_APB_UART0_REF_CTRL_DIVISOR1 0x1 - RegVal = ((0x00000001U << CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_SHIFT - | 0x0000000FU << CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_SHIFT - | 0x00000005U << CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_SHIFT - | 0x00000000U << CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_USB3_DUAL_REF_CTRL_OFFSET ,0x023F3F07U ,0x020F0500U); - /*############################################################################################################################ */ + * 6 bit divider + * PSU_CRL_APB_UART0_REF_CTRL_DIVISOR0 0xf - /*Register : QSPI_REF_CTRL @ 0XFF5E0068

+ * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_UART0_REF_CTRL_SRCSEL 0x0 - Clock active signal. Switch to 0 to disable the clock - PSU_CRL_APB_QSPI_REF_CTRL_CLKACT 0x1 + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E0074, 0x013F3F07U ,0x01010F00U) + */ + PSU_Mask_Write(CRL_APB_UART0_REF_CTRL_OFFSET, + 0x013F3F07U, 0x01010F00U); +/*##################################################################### */ + + /* + * Register : UART1_REF_CTRL @ 0XFF5E0078 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_UART1_REF_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_UART1_REF_CTRL_DIVISOR1 0x1 + + * 6 bit divider + * PSU_CRL_APB_UART1_REF_CTRL_DIVISOR0 0xf - 6 bit divider - PSU_CRL_APB_QSPI_REF_CTRL_DIVISOR1 0x1 + * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_UART1_REF_CTRL_SRCSEL 0x0 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E0078, 0x013F3F07U ,0x01010F00U) + */ + PSU_Mask_Write(CRL_APB_UART1_REF_CTRL_OFFSET, + 0x013F3F07U, 0x01010F00U); +/*##################################################################### */ + + /* + * Register : I2C0_REF_CTRL @ 0XFF5E0120 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_I2C0_REF_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_I2C0_REF_CTRL_DIVISOR1 0x1 + + * 6 bit divider + * PSU_CRL_APB_I2C0_REF_CTRL_DIVISOR0 0xf + + * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_I2C0_REF_CTRL_SRCSEL 0x0 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E0120, 0x013F3F07U ,0x01010F00U) + */ + PSU_Mask_Write(CRL_APB_I2C0_REF_CTRL_OFFSET, + 0x013F3F07U, 0x01010F00U); +/*##################################################################### */ + + /* + * Register : I2C1_REF_CTRL @ 0XFF5E0124 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_I2C1_REF_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_I2C1_REF_CTRL_DIVISOR1 0x1 + + * 6 bit divider + * PSU_CRL_APB_I2C1_REF_CTRL_DIVISOR0 0xf + + * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_I2C1_REF_CTRL_SRCSEL 0x0 - 6 bit divider - PSU_CRL_APB_QSPI_REF_CTRL_DIVISOR0 0xc + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E0124, 0x013F3F07U ,0x01010F00U) + */ + PSU_Mask_Write(CRL_APB_I2C1_REF_CTRL_OFFSET, + 0x013F3F07U, 0x01010F00U); +/*##################################################################### */ + + /* + * Register : CAN1_REF_CTRL @ 0XFF5E0088 - 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_QSPI_REF_CTRL_SRCSEL 0x0 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E0068, 0x013F3F07U ,0x01010C00U) - RegMask = (CRL_APB_QSPI_REF_CTRL_CLKACT_MASK | CRL_APB_QSPI_REF_CTRL_DIVISOR1_MASK | CRL_APB_QSPI_REF_CTRL_DIVISOR0_MASK | CRL_APB_QSPI_REF_CTRL_SRCSEL_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_QSPI_REF_CTRL_CLKACT_SHIFT - | 0x00000001U << CRL_APB_QSPI_REF_CTRL_DIVISOR1_SHIFT - | 0x0000000CU << CRL_APB_QSPI_REF_CTRL_DIVISOR0_SHIFT - | 0x00000000U << CRL_APB_QSPI_REF_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_QSPI_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010C00U); - /*############################################################################################################################ */ - - /*Register : SDIO1_REF_CTRL @ 0XFF5E0070

- - Clock active signal. Switch to 0 to disable the clock - PSU_CRL_APB_SDIO1_REF_CTRL_CLKACT 0x1 - - 6 bit divider - PSU_CRL_APB_SDIO1_REF_CTRL_DIVISOR1 0x1 - - 6 bit divider - PSU_CRL_APB_SDIO1_REF_CTRL_DIVISOR0 0x6 - - 000 = IOPLL; 010 = RPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_SDIO1_REF_CTRL_SRCSEL 0x2 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E0070, 0x013F3F07U ,0x01010602U) - RegMask = (CRL_APB_SDIO1_REF_CTRL_CLKACT_MASK | CRL_APB_SDIO1_REF_CTRL_DIVISOR1_MASK | CRL_APB_SDIO1_REF_CTRL_DIVISOR0_MASK | CRL_APB_SDIO1_REF_CTRL_SRCSEL_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_SDIO1_REF_CTRL_CLKACT_SHIFT - | 0x00000001U << CRL_APB_SDIO1_REF_CTRL_DIVISOR1_SHIFT - | 0x00000006U << CRL_APB_SDIO1_REF_CTRL_DIVISOR0_SHIFT - | 0x00000002U << CRL_APB_SDIO1_REF_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_SDIO1_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010602U); - /*############################################################################################################################ */ - - /*Register : SDIO_CLK_CTRL @ 0XFF18030C

- - MIO pad selection for sdio1_rx_clk (feedback clock from the PAD) 0: MIO [51] 1: MIO [76] - PSU_IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL 0 - - SoC Debug Clock Control - (OFFSET, MASK, VALUE) (0XFF18030C, 0x00020000U ,0x00000000U) - RegMask = (IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_SDIO_CLK_CTRL_OFFSET ,0x00020000U ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : UART0_REF_CTRL @ 0XFF5E0074

- - Clock active signal. Switch to 0 to disable the clock - PSU_CRL_APB_UART0_REF_CTRL_CLKACT 0x1 - - 6 bit divider - PSU_CRL_APB_UART0_REF_CTRL_DIVISOR1 0x1 - - 6 bit divider - PSU_CRL_APB_UART0_REF_CTRL_DIVISOR0 0xf - - 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_UART0_REF_CTRL_SRCSEL 0x0 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E0074, 0x013F3F07U ,0x01010F00U) - RegMask = (CRL_APB_UART0_REF_CTRL_CLKACT_MASK | CRL_APB_UART0_REF_CTRL_DIVISOR1_MASK | CRL_APB_UART0_REF_CTRL_DIVISOR0_MASK | CRL_APB_UART0_REF_CTRL_SRCSEL_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_UART0_REF_CTRL_CLKACT_SHIFT - | 0x00000001U << CRL_APB_UART0_REF_CTRL_DIVISOR1_SHIFT - | 0x0000000FU << CRL_APB_UART0_REF_CTRL_DIVISOR0_SHIFT - | 0x00000000U << CRL_APB_UART0_REF_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_UART0_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010F00U); - /*############################################################################################################################ */ - - /*Register : UART1_REF_CTRL @ 0XFF5E0078

- - Clock active signal. Switch to 0 to disable the clock - PSU_CRL_APB_UART1_REF_CTRL_CLKACT 0x1 - - 6 bit divider - PSU_CRL_APB_UART1_REF_CTRL_DIVISOR1 0x1 - - 6 bit divider - PSU_CRL_APB_UART1_REF_CTRL_DIVISOR0 0xf - - 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_UART1_REF_CTRL_SRCSEL 0x0 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E0078, 0x013F3F07U ,0x01010F00U) - RegMask = (CRL_APB_UART1_REF_CTRL_CLKACT_MASK | CRL_APB_UART1_REF_CTRL_DIVISOR1_MASK | CRL_APB_UART1_REF_CTRL_DIVISOR0_MASK | CRL_APB_UART1_REF_CTRL_SRCSEL_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_UART1_REF_CTRL_CLKACT_SHIFT - | 0x00000001U << CRL_APB_UART1_REF_CTRL_DIVISOR1_SHIFT - | 0x0000000FU << CRL_APB_UART1_REF_CTRL_DIVISOR0_SHIFT - | 0x00000000U << CRL_APB_UART1_REF_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_UART1_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010F00U); - /*############################################################################################################################ */ - - /*Register : I2C0_REF_CTRL @ 0XFF5E0120

- - Clock active signal. Switch to 0 to disable the clock - PSU_CRL_APB_I2C0_REF_CTRL_CLKACT 0x1 - - 6 bit divider - PSU_CRL_APB_I2C0_REF_CTRL_DIVISOR1 0x1 - - 6 bit divider - PSU_CRL_APB_I2C0_REF_CTRL_DIVISOR0 0xf - - 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_I2C0_REF_CTRL_SRCSEL 0x0 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E0120, 0x013F3F07U ,0x01010F00U) - RegMask = (CRL_APB_I2C0_REF_CTRL_CLKACT_MASK | CRL_APB_I2C0_REF_CTRL_DIVISOR1_MASK | CRL_APB_I2C0_REF_CTRL_DIVISOR0_MASK | CRL_APB_I2C0_REF_CTRL_SRCSEL_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_I2C0_REF_CTRL_CLKACT_SHIFT - | 0x00000001U << CRL_APB_I2C0_REF_CTRL_DIVISOR1_SHIFT - | 0x0000000FU << CRL_APB_I2C0_REF_CTRL_DIVISOR0_SHIFT - | 0x00000000U << CRL_APB_I2C0_REF_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_I2C0_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010F00U); - /*############################################################################################################################ */ - - /*Register : I2C1_REF_CTRL @ 0XFF5E0124

- - Clock active signal. Switch to 0 to disable the clock - PSU_CRL_APB_I2C1_REF_CTRL_CLKACT 0x1 - - 6 bit divider - PSU_CRL_APB_I2C1_REF_CTRL_DIVISOR1 0x1 - - 6 bit divider - PSU_CRL_APB_I2C1_REF_CTRL_DIVISOR0 0xf - - 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_I2C1_REF_CTRL_SRCSEL 0x0 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E0124, 0x013F3F07U ,0x01010F00U) - RegMask = (CRL_APB_I2C1_REF_CTRL_CLKACT_MASK | CRL_APB_I2C1_REF_CTRL_DIVISOR1_MASK | CRL_APB_I2C1_REF_CTRL_DIVISOR0_MASK | CRL_APB_I2C1_REF_CTRL_SRCSEL_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_I2C1_REF_CTRL_CLKACT_SHIFT - | 0x00000001U << CRL_APB_I2C1_REF_CTRL_DIVISOR1_SHIFT - | 0x0000000FU << CRL_APB_I2C1_REF_CTRL_DIVISOR0_SHIFT - | 0x00000000U << CRL_APB_I2C1_REF_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_I2C1_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010F00U); - /*############################################################################################################################ */ - - /*Register : CAN1_REF_CTRL @ 0XFF5E0088

- - Clock active signal. Switch to 0 to disable the clock - PSU_CRL_APB_CAN1_REF_CTRL_CLKACT 0x1 - - 6 bit divider - PSU_CRL_APB_CAN1_REF_CTRL_DIVISOR1 0x1 - - 6 bit divider - PSU_CRL_APB_CAN1_REF_CTRL_DIVISOR0 0xf - - 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_CAN1_REF_CTRL_SRCSEL 0x0 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E0088, 0x013F3F07U ,0x01010F00U) - RegMask = (CRL_APB_CAN1_REF_CTRL_CLKACT_MASK | CRL_APB_CAN1_REF_CTRL_DIVISOR1_MASK | CRL_APB_CAN1_REF_CTRL_DIVISOR0_MASK | CRL_APB_CAN1_REF_CTRL_SRCSEL_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_CAN1_REF_CTRL_CLKACT_SHIFT - | 0x00000001U << CRL_APB_CAN1_REF_CTRL_DIVISOR1_SHIFT - | 0x0000000FU << CRL_APB_CAN1_REF_CTRL_DIVISOR0_SHIFT - | 0x00000000U << CRL_APB_CAN1_REF_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_CAN1_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010F00U); - /*############################################################################################################################ */ - - /*Register : CPU_R5_CTRL @ 0XFF5E0090

- - Turing this off will shut down the OCM, some parts of the APM, and prevent transactions going from the FPD to the LPD and cou - d lead to system hang - PSU_CRL_APB_CPU_R5_CTRL_CLKACT 0x1 - - 6 bit divider - PSU_CRL_APB_CPU_R5_CTRL_DIVISOR0 0x3 - - 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_CPU_R5_CTRL_SRCSEL 0x2 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E0090, 0x01003F07U ,0x01000302U) - RegMask = (CRL_APB_CPU_R5_CTRL_CLKACT_MASK | CRL_APB_CPU_R5_CTRL_DIVISOR0_MASK | CRL_APB_CPU_R5_CTRL_SRCSEL_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_CPU_R5_CTRL_CLKACT_SHIFT - | 0x00000003U << CRL_APB_CPU_R5_CTRL_DIVISOR0_SHIFT - | 0x00000002U << CRL_APB_CPU_R5_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_CPU_R5_CTRL_OFFSET ,0x01003F07U ,0x01000302U); - /*############################################################################################################################ */ - - /*Register : IOU_SWITCH_CTRL @ 0XFF5E009C

- - Clock active signal. Switch to 0 to disable the clock - PSU_CRL_APB_IOU_SWITCH_CTRL_CLKACT 0x1 - - 6 bit divider - PSU_CRL_APB_IOU_SWITCH_CTRL_DIVISOR0 0x6 - - 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_IOU_SWITCH_CTRL_SRCSEL 0x2 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E009C, 0x01003F07U ,0x01000602U) - RegMask = (CRL_APB_IOU_SWITCH_CTRL_CLKACT_MASK | CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_MASK | CRL_APB_IOU_SWITCH_CTRL_SRCSEL_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_IOU_SWITCH_CTRL_CLKACT_SHIFT - | 0x00000006U << CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_SHIFT - | 0x00000002U << CRL_APB_IOU_SWITCH_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_IOU_SWITCH_CTRL_OFFSET ,0x01003F07U ,0x01000602U); - /*############################################################################################################################ */ - - /*Register : PCAP_CTRL @ 0XFF5E00A4

- - Clock active signal. Switch to 0 to disable the clock - PSU_CRL_APB_PCAP_CTRL_CLKACT 0x1 - - 6 bit divider - PSU_CRL_APB_PCAP_CTRL_DIVISOR0 0x6 - - 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_PCAP_CTRL_SRCSEL 0x2 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E00A4, 0x01003F07U ,0x01000602U) - RegMask = (CRL_APB_PCAP_CTRL_CLKACT_MASK | CRL_APB_PCAP_CTRL_DIVISOR0_MASK | CRL_APB_PCAP_CTRL_SRCSEL_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_PCAP_CTRL_CLKACT_SHIFT - | 0x00000006U << CRL_APB_PCAP_CTRL_DIVISOR0_SHIFT - | 0x00000002U << CRL_APB_PCAP_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_PCAP_CTRL_OFFSET ,0x01003F07U ,0x01000602U); - /*############################################################################################################################ */ - - /*Register : LPD_SWITCH_CTRL @ 0XFF5E00A8

- - Clock active signal. Switch to 0 to disable the clock - PSU_CRL_APB_LPD_SWITCH_CTRL_CLKACT 0x1 - - 6 bit divider - PSU_CRL_APB_LPD_SWITCH_CTRL_DIVISOR0 0x3 - - 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_LPD_SWITCH_CTRL_SRCSEL 0x2 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E00A8, 0x01003F07U ,0x01000302U) - RegMask = (CRL_APB_LPD_SWITCH_CTRL_CLKACT_MASK | CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_MASK | CRL_APB_LPD_SWITCH_CTRL_SRCSEL_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_LPD_SWITCH_CTRL_CLKACT_SHIFT - | 0x00000003U << CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_SHIFT - | 0x00000002U << CRL_APB_LPD_SWITCH_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_LPD_SWITCH_CTRL_OFFSET ,0x01003F07U ,0x01000302U); - /*############################################################################################################################ */ - - /*Register : LPD_LSBUS_CTRL @ 0XFF5E00AC

- - Clock active signal. Switch to 0 to disable the clock - PSU_CRL_APB_LPD_LSBUS_CTRL_CLKACT 0x1 - - 6 bit divider - PSU_CRL_APB_LPD_LSBUS_CTRL_DIVISOR0 0xf - - 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_LPD_LSBUS_CTRL_SRCSEL 0x2 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E00AC, 0x01003F07U ,0x01000F02U) - RegMask = (CRL_APB_LPD_LSBUS_CTRL_CLKACT_MASK | CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_MASK | CRL_APB_LPD_LSBUS_CTRL_SRCSEL_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_LPD_LSBUS_CTRL_CLKACT_SHIFT - | 0x0000000FU << CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_SHIFT - | 0x00000002U << CRL_APB_LPD_LSBUS_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_LPD_LSBUS_CTRL_OFFSET ,0x01003F07U ,0x01000F02U); - /*############################################################################################################################ */ - - /*Register : DBG_LPD_CTRL @ 0XFF5E00B0

- - Clock active signal. Switch to 0 to disable the clock - PSU_CRL_APB_DBG_LPD_CTRL_CLKACT 0x1 - - 6 bit divider - PSU_CRL_APB_DBG_LPD_CTRL_DIVISOR0 0x6 - - 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_DBG_LPD_CTRL_SRCSEL 0x2 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E00B0, 0x01003F07U ,0x01000602U) - RegMask = (CRL_APB_DBG_LPD_CTRL_CLKACT_MASK | CRL_APB_DBG_LPD_CTRL_DIVISOR0_MASK | CRL_APB_DBG_LPD_CTRL_SRCSEL_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_DBG_LPD_CTRL_CLKACT_SHIFT - | 0x00000006U << CRL_APB_DBG_LPD_CTRL_DIVISOR0_SHIFT - | 0x00000002U << CRL_APB_DBG_LPD_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_DBG_LPD_CTRL_OFFSET ,0x01003F07U ,0x01000602U); - /*############################################################################################################################ */ - - /*Register : ADMA_REF_CTRL @ 0XFF5E00B8

- - Clock active signal. Switch to 0 to disable the clock - PSU_CRL_APB_ADMA_REF_CTRL_CLKACT 0x1 - - 6 bit divider - PSU_CRL_APB_ADMA_REF_CTRL_DIVISOR0 0x3 - - 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_ADMA_REF_CTRL_SRCSEL 0x2 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E00B8, 0x01003F07U ,0x01000302U) - RegMask = (CRL_APB_ADMA_REF_CTRL_CLKACT_MASK | CRL_APB_ADMA_REF_CTRL_DIVISOR0_MASK | CRL_APB_ADMA_REF_CTRL_SRCSEL_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_ADMA_REF_CTRL_CLKACT_SHIFT - | 0x00000003U << CRL_APB_ADMA_REF_CTRL_DIVISOR0_SHIFT - | 0x00000002U << CRL_APB_ADMA_REF_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_ADMA_REF_CTRL_OFFSET ,0x01003F07U ,0x01000302U); - /*############################################################################################################################ */ - - /*Register : PL0_REF_CTRL @ 0XFF5E00C0

- - Clock active signal. Switch to 0 to disable the clock - PSU_CRL_APB_PL0_REF_CTRL_CLKACT 0x1 - - 6 bit divider - PSU_CRL_APB_PL0_REF_CTRL_DIVISOR1 0x1 - - 6 bit divider - PSU_CRL_APB_PL0_REF_CTRL_DIVISOR0 0xf - - 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_PL0_REF_CTRL_SRCSEL 0x0 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E00C0, 0x013F3F07U ,0x01010F00U) - RegMask = (CRL_APB_PL0_REF_CTRL_CLKACT_MASK | CRL_APB_PL0_REF_CTRL_DIVISOR1_MASK | CRL_APB_PL0_REF_CTRL_DIVISOR0_MASK | CRL_APB_PL0_REF_CTRL_SRCSEL_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_PL0_REF_CTRL_CLKACT_SHIFT - | 0x00000001U << CRL_APB_PL0_REF_CTRL_DIVISOR1_SHIFT - | 0x0000000FU << CRL_APB_PL0_REF_CTRL_DIVISOR0_SHIFT - | 0x00000000U << CRL_APB_PL0_REF_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_PL0_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010F00U); - /*############################################################################################################################ */ - - /*Register : PL1_REF_CTRL @ 0XFF5E00C4

- - Clock active signal. Switch to 0 to disable the clock - PSU_CRL_APB_PL1_REF_CTRL_CLKACT 0x1 - - 6 bit divider - PSU_CRL_APB_PL1_REF_CTRL_DIVISOR1 0x4 - - 6 bit divider - PSU_CRL_APB_PL1_REF_CTRL_DIVISOR0 0xf - - 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_PL1_REF_CTRL_SRCSEL 0x0 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E00C4, 0x013F3F07U ,0x01040F00U) - RegMask = (CRL_APB_PL1_REF_CTRL_CLKACT_MASK | CRL_APB_PL1_REF_CTRL_DIVISOR1_MASK | CRL_APB_PL1_REF_CTRL_DIVISOR0_MASK | CRL_APB_PL1_REF_CTRL_SRCSEL_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_PL1_REF_CTRL_CLKACT_SHIFT - | 0x00000004U << CRL_APB_PL1_REF_CTRL_DIVISOR1_SHIFT - | 0x0000000FU << CRL_APB_PL1_REF_CTRL_DIVISOR0_SHIFT - | 0x00000000U << CRL_APB_PL1_REF_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_PL1_REF_CTRL_OFFSET ,0x013F3F07U ,0x01040F00U); - /*############################################################################################################################ */ - - /*Register : PL2_REF_CTRL @ 0XFF5E00C8

- - Clock active signal. Switch to 0 to disable the clock - PSU_CRL_APB_PL2_REF_CTRL_CLKACT 0x1 - - 6 bit divider - PSU_CRL_APB_PL2_REF_CTRL_DIVISOR1 0x1 - - 6 bit divider - PSU_CRL_APB_PL2_REF_CTRL_DIVISOR0 0x4 - - 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_PL2_REF_CTRL_SRCSEL 0x2 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E00C8, 0x013F3F07U ,0x01010402U) - RegMask = (CRL_APB_PL2_REF_CTRL_CLKACT_MASK | CRL_APB_PL2_REF_CTRL_DIVISOR1_MASK | CRL_APB_PL2_REF_CTRL_DIVISOR0_MASK | CRL_APB_PL2_REF_CTRL_SRCSEL_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_PL2_REF_CTRL_CLKACT_SHIFT - | 0x00000001U << CRL_APB_PL2_REF_CTRL_DIVISOR1_SHIFT - | 0x00000004U << CRL_APB_PL2_REF_CTRL_DIVISOR0_SHIFT - | 0x00000002U << CRL_APB_PL2_REF_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_PL2_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010402U); - /*############################################################################################################################ */ - - /*Register : PL3_REF_CTRL @ 0XFF5E00CC

- - Clock active signal. Switch to 0 to disable the clock - PSU_CRL_APB_PL3_REF_CTRL_CLKACT 0x1 - - 6 bit divider - PSU_CRL_APB_PL3_REF_CTRL_DIVISOR1 0x1 - - 6 bit divider - PSU_CRL_APB_PL3_REF_CTRL_DIVISOR0 0x3 - - 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_PL3_REF_CTRL_SRCSEL 0x2 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E00CC, 0x013F3F07U ,0x01010302U) - RegMask = (CRL_APB_PL3_REF_CTRL_CLKACT_MASK | CRL_APB_PL3_REF_CTRL_DIVISOR1_MASK | CRL_APB_PL3_REF_CTRL_DIVISOR0_MASK | CRL_APB_PL3_REF_CTRL_SRCSEL_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_PL3_REF_CTRL_CLKACT_SHIFT - | 0x00000001U << CRL_APB_PL3_REF_CTRL_DIVISOR1_SHIFT - | 0x00000003U << CRL_APB_PL3_REF_CTRL_DIVISOR0_SHIFT - | 0x00000002U << CRL_APB_PL3_REF_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_PL3_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010302U); - /*############################################################################################################################ */ - - /*Register : AMS_REF_CTRL @ 0XFF5E0108

- - 6 bit divider - PSU_CRL_APB_AMS_REF_CTRL_DIVISOR1 0x1 - - 6 bit divider - PSU_CRL_APB_AMS_REF_CTRL_DIVISOR0 0x1d - - 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_AMS_REF_CTRL_SRCSEL 0x2 - - Clock active signal. Switch to 0 to disable the clock - PSU_CRL_APB_AMS_REF_CTRL_CLKACT 0x1 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E0108, 0x013F3F07U ,0x01011D02U) - RegMask = (CRL_APB_AMS_REF_CTRL_DIVISOR1_MASK | CRL_APB_AMS_REF_CTRL_DIVISOR0_MASK | CRL_APB_AMS_REF_CTRL_SRCSEL_MASK | CRL_APB_AMS_REF_CTRL_CLKACT_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_AMS_REF_CTRL_DIVISOR1_SHIFT - | 0x0000001DU << CRL_APB_AMS_REF_CTRL_DIVISOR0_SHIFT - | 0x00000002U << CRL_APB_AMS_REF_CTRL_SRCSEL_SHIFT - | 0x00000001U << CRL_APB_AMS_REF_CTRL_CLKACT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_AMS_REF_CTRL_OFFSET ,0x013F3F07U ,0x01011D02U); - /*############################################################################################################################ */ - - /*Register : DLL_REF_CTRL @ 0XFF5E0104

- - 000 = IOPLL; 001 = RPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This - is not usually an issue, but designers must be aware.) - PSU_CRL_APB_DLL_REF_CTRL_SRCSEL 0 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E0104, 0x00000007U ,0x00000000U) - RegMask = (CRL_APB_DLL_REF_CTRL_SRCSEL_MASK | 0 ); - - RegVal = ((0x00000000U << CRL_APB_DLL_REF_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_DLL_REF_CTRL_OFFSET ,0x00000007U ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : TIMESTAMP_REF_CTRL @ 0XFF5E0128

- - 6 bit divider - PSU_CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0 0xf - - 1XX = pss_ref_clk; 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and - cycles of the new clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL 0x0 - - Clock active signal. Switch to 0 to disable the clock - PSU_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT 0x1 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E0128, 0x01003F07U ,0x01000F00U) - RegMask = (CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_MASK | CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_MASK | CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_MASK | 0 ); - - RegVal = ((0x0000000FU << CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_SHIFT - | 0x00000000U << CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_SHIFT - | 0x00000001U << CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_TIMESTAMP_REF_CTRL_OFFSET ,0x01003F07U ,0x01000F00U); - /*############################################################################################################################ */ - - /*Register : SATA_REF_CTRL @ 0XFD1A00A0

- - 000 = IOPLL_TO_FPD; 010 = APLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of - he new clock. This is not usually an issue, but designers must be aware.) - PSU_CRF_APB_SATA_REF_CTRL_SRCSEL 0x0 - - Clock active signal. Switch to 0 to disable the clock - PSU_CRF_APB_SATA_REF_CTRL_CLKACT 0x1 - - 6 bit divider - PSU_CRF_APB_SATA_REF_CTRL_DIVISOR0 0x2 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFD1A00A0, 0x01003F07U ,0x01000200U) - RegMask = (CRF_APB_SATA_REF_CTRL_SRCSEL_MASK | CRF_APB_SATA_REF_CTRL_CLKACT_MASK | CRF_APB_SATA_REF_CTRL_DIVISOR0_MASK | 0 ); - - RegVal = ((0x00000000U << CRF_APB_SATA_REF_CTRL_SRCSEL_SHIFT - | 0x00000001U << CRF_APB_SATA_REF_CTRL_CLKACT_SHIFT - | 0x00000002U << CRF_APB_SATA_REF_CTRL_DIVISOR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_SATA_REF_CTRL_OFFSET ,0x01003F07U ,0x01000200U); - /*############################################################################################################################ */ - - /*Register : PCIE_REF_CTRL @ 0XFD1A00B4

- - 000 = IOPLL_TO_FPD; 010 = RPLL_TO_FPD; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cyc - es of the new clock. This is not usually an issue, but designers must be aware.) - PSU_CRF_APB_PCIE_REF_CTRL_SRCSEL 0x0 - - Clock active signal. Switch to 0 to disable the clock - PSU_CRF_APB_PCIE_REF_CTRL_CLKACT 0x1 - - 6 bit divider - PSU_CRF_APB_PCIE_REF_CTRL_DIVISOR0 0x2 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFD1A00B4, 0x01003F07U ,0x01000200U) - RegMask = (CRF_APB_PCIE_REF_CTRL_SRCSEL_MASK | CRF_APB_PCIE_REF_CTRL_CLKACT_MASK | CRF_APB_PCIE_REF_CTRL_DIVISOR0_MASK | 0 ); - - RegVal = ((0x00000000U << CRF_APB_PCIE_REF_CTRL_SRCSEL_SHIFT - | 0x00000001U << CRF_APB_PCIE_REF_CTRL_CLKACT_SHIFT - | 0x00000002U << CRF_APB_PCIE_REF_CTRL_DIVISOR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_PCIE_REF_CTRL_OFFSET ,0x01003F07U ,0x01000200U); - /*############################################################################################################################ */ - - /*Register : DP_VIDEO_REF_CTRL @ 0XFD1A0070

- - 6 bit divider - PSU_CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1 0x1 - - 6 bit divider - PSU_CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0 0x3 - - 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (This signal may only be toggled after 4 cycles of the - ld clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.) - PSU_CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL 0x3 - - Clock active signal. Switch to 0 to disable the clock - PSU_CRF_APB_DP_VIDEO_REF_CTRL_CLKACT 0x1 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFD1A0070, 0x013F3F07U ,0x01010303U) - RegMask = (CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_MASK | CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_MASK | CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_MASK | CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_MASK | 0 ); - - RegVal = ((0x00000001U << CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_SHIFT - | 0x00000003U << CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_SHIFT - | 0x00000003U << CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_SHIFT - | 0x00000001U << CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_DP_VIDEO_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010303U); - /*############################################################################################################################ */ - - /*Register : DP_AUDIO_REF_CTRL @ 0XFD1A0074

- - 6 bit divider - PSU_CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1 0x1 - - 6 bit divider - PSU_CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0 0x27 - - 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (This signal may only be toggled after 4 cycles of the - ld clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.) - PSU_CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL 0x0 - - Clock active signal. Switch to 0 to disable the clock - PSU_CRF_APB_DP_AUDIO_REF_CTRL_CLKACT 0x1 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFD1A0074, 0x013F3F07U ,0x01012700U) - RegMask = (CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_MASK | CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_MASK | CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_MASK | CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_MASK | 0 ); - - RegVal = ((0x00000001U << CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_SHIFT - | 0x00000027U << CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_SHIFT - | 0x00000000U << CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_SHIFT - | 0x00000001U << CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_DP_AUDIO_REF_CTRL_OFFSET ,0x013F3F07U ,0x01012700U); - /*############################################################################################################################ */ - - /*Register : DP_STC_REF_CTRL @ 0XFD1A007C

- - 6 bit divider - PSU_CRF_APB_DP_STC_REF_CTRL_DIVISOR1 0x1 - - 6 bit divider - PSU_CRF_APB_DP_STC_REF_CTRL_DIVISOR0 0x11 - - 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of t - e new clock. This is not usually an issue, but designers must be aware.) - PSU_CRF_APB_DP_STC_REF_CTRL_SRCSEL 0x3 - - Clock active signal. Switch to 0 to disable the clock - PSU_CRF_APB_DP_STC_REF_CTRL_CLKACT 0x1 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFD1A007C, 0x013F3F07U ,0x01011103U) - RegMask = (CRF_APB_DP_STC_REF_CTRL_DIVISOR1_MASK | CRF_APB_DP_STC_REF_CTRL_DIVISOR0_MASK | CRF_APB_DP_STC_REF_CTRL_SRCSEL_MASK | CRF_APB_DP_STC_REF_CTRL_CLKACT_MASK | 0 ); - - RegVal = ((0x00000001U << CRF_APB_DP_STC_REF_CTRL_DIVISOR1_SHIFT - | 0x00000011U << CRF_APB_DP_STC_REF_CTRL_DIVISOR0_SHIFT - | 0x00000003U << CRF_APB_DP_STC_REF_CTRL_SRCSEL_SHIFT - | 0x00000001U << CRF_APB_DP_STC_REF_CTRL_CLKACT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_DP_STC_REF_CTRL_OFFSET ,0x013F3F07U ,0x01011103U); - /*############################################################################################################################ */ - - /*Register : ACPU_CTRL @ 0XFD1A0060

- - 6 bit divider - PSU_CRF_APB_ACPU_CTRL_DIVISOR0 0x1 - - 000 = APLL; 010 = DPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - lock. This is not usually an issue, but designers must be aware.) - PSU_CRF_APB_ACPU_CTRL_SRCSEL 0x0 - - Clock active signal. Switch to 0 to disable the clock. For the half speed APU Clock - PSU_CRF_APB_ACPU_CTRL_CLKACT_HALF 0x1 - - Clock active signal. Switch to 0 to disable the clock. For the full speed ACPUX Clock. This will shut off the high speed cloc - to the entire APU - PSU_CRF_APB_ACPU_CTRL_CLKACT_FULL 0x1 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFD1A0060, 0x03003F07U ,0x03000100U) - RegMask = (CRF_APB_ACPU_CTRL_DIVISOR0_MASK | CRF_APB_ACPU_CTRL_SRCSEL_MASK | CRF_APB_ACPU_CTRL_CLKACT_HALF_MASK | CRF_APB_ACPU_CTRL_CLKACT_FULL_MASK | 0 ); - - RegVal = ((0x00000001U << CRF_APB_ACPU_CTRL_DIVISOR0_SHIFT - | 0x00000000U << CRF_APB_ACPU_CTRL_SRCSEL_SHIFT - | 0x00000001U << CRF_APB_ACPU_CTRL_CLKACT_HALF_SHIFT - | 0x00000001U << CRF_APB_ACPU_CTRL_CLKACT_FULL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_ACPU_CTRL_OFFSET ,0x03003F07U ,0x03000100U); - /*############################################################################################################################ */ - - /*Register : DBG_TRACE_CTRL @ 0XFD1A0064

- - 6 bit divider - PSU_CRF_APB_DBG_TRACE_CTRL_DIVISOR0 0x2 - - 000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of - he new clock. This is not usually an issue, but designers must be aware.) - PSU_CRF_APB_DBG_TRACE_CTRL_SRCSEL 0x0 - - Clock active signal. Switch to 0 to disable the clock - PSU_CRF_APB_DBG_TRACE_CTRL_CLKACT 0x1 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFD1A0064, 0x01003F07U ,0x01000200U) - RegMask = (CRF_APB_DBG_TRACE_CTRL_DIVISOR0_MASK | CRF_APB_DBG_TRACE_CTRL_SRCSEL_MASK | CRF_APB_DBG_TRACE_CTRL_CLKACT_MASK | 0 ); - - RegVal = ((0x00000002U << CRF_APB_DBG_TRACE_CTRL_DIVISOR0_SHIFT - | 0x00000000U << CRF_APB_DBG_TRACE_CTRL_SRCSEL_SHIFT - | 0x00000001U << CRF_APB_DBG_TRACE_CTRL_CLKACT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_DBG_TRACE_CTRL_OFFSET ,0x01003F07U ,0x01000200U); - /*############################################################################################################################ */ - - /*Register : DBG_FPD_CTRL @ 0XFD1A0068

- - 6 bit divider - PSU_CRF_APB_DBG_FPD_CTRL_DIVISOR0 0x2 - - 000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of - he new clock. This is not usually an issue, but designers must be aware.) - PSU_CRF_APB_DBG_FPD_CTRL_SRCSEL 0x0 - - Clock active signal. Switch to 0 to disable the clock - PSU_CRF_APB_DBG_FPD_CTRL_CLKACT 0x1 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFD1A0068, 0x01003F07U ,0x01000200U) - RegMask = (CRF_APB_DBG_FPD_CTRL_DIVISOR0_MASK | CRF_APB_DBG_FPD_CTRL_SRCSEL_MASK | CRF_APB_DBG_FPD_CTRL_CLKACT_MASK | 0 ); - - RegVal = ((0x00000002U << CRF_APB_DBG_FPD_CTRL_DIVISOR0_SHIFT - | 0x00000000U << CRF_APB_DBG_FPD_CTRL_SRCSEL_SHIFT - | 0x00000001U << CRF_APB_DBG_FPD_CTRL_CLKACT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_DBG_FPD_CTRL_OFFSET ,0x01003F07U ,0x01000200U); - /*############################################################################################################################ */ - - /*Register : DDR_CTRL @ 0XFD1A0080

- - 6 bit divider - PSU_CRF_APB_DDR_CTRL_DIVISOR0 0x2 - - 000 = DPLL; 001 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This - s not usually an issue, but designers must be aware.) - PSU_CRF_APB_DDR_CTRL_SRCSEL 0x0 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFD1A0080, 0x00003F07U ,0x00000200U) - RegMask = (CRF_APB_DDR_CTRL_DIVISOR0_MASK | CRF_APB_DDR_CTRL_SRCSEL_MASK | 0 ); - - RegVal = ((0x00000002U << CRF_APB_DDR_CTRL_DIVISOR0_SHIFT - | 0x00000000U << CRF_APB_DDR_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_DDR_CTRL_OFFSET ,0x00003F07U ,0x00000200U); - /*############################################################################################################################ */ - - /*Register : GPU_REF_CTRL @ 0XFD1A0084

- - 6 bit divider - PSU_CRF_APB_GPU_REF_CTRL_DIVISOR0 0x1 - - 000 = IOPLL_TO_FPD; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of - he new clock. This is not usually an issue, but designers must be aware.) - PSU_CRF_APB_GPU_REF_CTRL_SRCSEL 0x0 - - Clock active signal. Switch to 0 to disable the clock, which will stop clock for GPU (and both Pixel Processors). - PSU_CRF_APB_GPU_REF_CTRL_CLKACT 0x1 - - Clock active signal for Pixel Processor. Switch to 0 to disable the clock only to this Pixel Processor - PSU_CRF_APB_GPU_REF_CTRL_PP0_CLKACT 0x1 - - Clock active signal for Pixel Processor. Switch to 0 to disable the clock only to this Pixel Processor - PSU_CRF_APB_GPU_REF_CTRL_PP1_CLKACT 0x1 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFD1A0084, 0x07003F07U ,0x07000100U) - RegMask = (CRF_APB_GPU_REF_CTRL_DIVISOR0_MASK | CRF_APB_GPU_REF_CTRL_SRCSEL_MASK | CRF_APB_GPU_REF_CTRL_CLKACT_MASK | CRF_APB_GPU_REF_CTRL_PP0_CLKACT_MASK | CRF_APB_GPU_REF_CTRL_PP1_CLKACT_MASK | 0 ); - - RegVal = ((0x00000001U << CRF_APB_GPU_REF_CTRL_DIVISOR0_SHIFT - | 0x00000000U << CRF_APB_GPU_REF_CTRL_SRCSEL_SHIFT - | 0x00000001U << CRF_APB_GPU_REF_CTRL_CLKACT_SHIFT - | 0x00000001U << CRF_APB_GPU_REF_CTRL_PP0_CLKACT_SHIFT - | 0x00000001U << CRF_APB_GPU_REF_CTRL_PP1_CLKACT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_GPU_REF_CTRL_OFFSET ,0x07003F07U ,0x07000100U); - /*############################################################################################################################ */ - - /*Register : GDMA_REF_CTRL @ 0XFD1A00B8

- - 6 bit divider - PSU_CRF_APB_GDMA_REF_CTRL_DIVISOR0 0x2 - - 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - lock. This is not usually an issue, but designers must be aware.) - PSU_CRF_APB_GDMA_REF_CTRL_SRCSEL 0x0 - - Clock active signal. Switch to 0 to disable the clock - PSU_CRF_APB_GDMA_REF_CTRL_CLKACT 0x1 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFD1A00B8, 0x01003F07U ,0x01000200U) - RegMask = (CRF_APB_GDMA_REF_CTRL_DIVISOR0_MASK | CRF_APB_GDMA_REF_CTRL_SRCSEL_MASK | CRF_APB_GDMA_REF_CTRL_CLKACT_MASK | 0 ); - - RegVal = ((0x00000002U << CRF_APB_GDMA_REF_CTRL_DIVISOR0_SHIFT - | 0x00000000U << CRF_APB_GDMA_REF_CTRL_SRCSEL_SHIFT - | 0x00000001U << CRF_APB_GDMA_REF_CTRL_CLKACT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_GDMA_REF_CTRL_OFFSET ,0x01003F07U ,0x01000200U); - /*############################################################################################################################ */ - - /*Register : DPDMA_REF_CTRL @ 0XFD1A00BC

- - 6 bit divider - PSU_CRF_APB_DPDMA_REF_CTRL_DIVISOR0 0x2 - - 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - lock. This is not usually an issue, but designers must be aware.) - PSU_CRF_APB_DPDMA_REF_CTRL_SRCSEL 0x0 - - Clock active signal. Switch to 0 to disable the clock - PSU_CRF_APB_DPDMA_REF_CTRL_CLKACT 0x1 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFD1A00BC, 0x01003F07U ,0x01000200U) - RegMask = (CRF_APB_DPDMA_REF_CTRL_DIVISOR0_MASK | CRF_APB_DPDMA_REF_CTRL_SRCSEL_MASK | CRF_APB_DPDMA_REF_CTRL_CLKACT_MASK | 0 ); - - RegVal = ((0x00000002U << CRF_APB_DPDMA_REF_CTRL_DIVISOR0_SHIFT - | 0x00000000U << CRF_APB_DPDMA_REF_CTRL_SRCSEL_SHIFT - | 0x00000001U << CRF_APB_DPDMA_REF_CTRL_CLKACT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_DPDMA_REF_CTRL_OFFSET ,0x01003F07U ,0x01000200U); - /*############################################################################################################################ */ - - /*Register : TOPSW_MAIN_CTRL @ 0XFD1A00C0

- - 6 bit divider - PSU_CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0 0x2 - - 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - lock. This is not usually an issue, but designers must be aware.) - PSU_CRF_APB_TOPSW_MAIN_CTRL_SRCSEL 0x2 - - Clock active signal. Switch to 0 to disable the clock - PSU_CRF_APB_TOPSW_MAIN_CTRL_CLKACT 0x1 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFD1A00C0, 0x01003F07U ,0x01000202U) - RegMask = (CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_MASK | CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_MASK | CRF_APB_TOPSW_MAIN_CTRL_CLKACT_MASK | 0 ); - - RegVal = ((0x00000002U << CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_SHIFT - | 0x00000002U << CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_SHIFT - | 0x00000001U << CRF_APB_TOPSW_MAIN_CTRL_CLKACT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_TOPSW_MAIN_CTRL_OFFSET ,0x01003F07U ,0x01000202U); - /*############################################################################################################################ */ - - /*Register : TOPSW_LSBUS_CTRL @ 0XFD1A00C4

- - 6 bit divider - PSU_CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0 0x5 - - 000 = APLL; 010 = IOPLL_TO_FPD; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of - he new clock. This is not usually an issue, but designers must be aware.) - PSU_CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL 0x2 - - Clock active signal. Switch to 0 to disable the clock - PSU_CRF_APB_TOPSW_LSBUS_CTRL_CLKACT 0x1 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFD1A00C4, 0x01003F07U ,0x01000502U) - RegMask = (CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_MASK | CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_MASK | CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_MASK | 0 ); - - RegVal = ((0x00000005U << CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_SHIFT - | 0x00000002U << CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_SHIFT - | 0x00000001U << CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_TOPSW_LSBUS_CTRL_OFFSET ,0x01003F07U ,0x01000502U); - /*############################################################################################################################ */ - - /*Register : DBG_TSTMP_CTRL @ 0XFD1A00F8

- - 6 bit divider - PSU_CRF_APB_DBG_TSTMP_CTRL_DIVISOR0 0x2 - - 000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of - he new clock. This is not usually an issue, but designers must be aware.) - PSU_CRF_APB_DBG_TSTMP_CTRL_SRCSEL 0x0 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFD1A00F8, 0x00003F07U ,0x00000200U) - RegMask = (CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_MASK | CRF_APB_DBG_TSTMP_CTRL_SRCSEL_MASK | 0 ); - - RegVal = ((0x00000002U << CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_SHIFT - | 0x00000000U << CRF_APB_DBG_TSTMP_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_DBG_TSTMP_CTRL_OFFSET ,0x00003F07U ,0x00000200U); - /*############################################################################################################################ */ - - /*Register : IOU_TTC_APB_CLK @ 0XFF180380

- - 00" = Select the APB switch clock for the APB interface of TTC0'01" = Select the PLL ref clock for the APB interface of TTC0' - 0" = Select the R5 clock for the APB interface of TTC0 - PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL 0 - - 00" = Select the APB switch clock for the APB interface of TTC1'01" = Select the PLL ref clock for the APB interface of TTC1' - 0" = Select the R5 clock for the APB interface of TTC1 - PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL 0 - - 00" = Select the APB switch clock for the APB interface of TTC2'01" = Select the PLL ref clock for the APB interface of TTC2' - 0" = Select the R5 clock for the APB interface of TTC2 - PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL 0 - - 00" = Select the APB switch clock for the APB interface of TTC3'01" = Select the PLL ref clock for the APB interface of TTC3' - 0" = Select the R5 clock for the APB interface of TTC3 - PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL 0 - - TTC APB clock select - (OFFSET, MASK, VALUE) (0XFF180380, 0x000000FFU ,0x00000000U) - RegMask = (IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_MASK | IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_MASK | IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_MASK | IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_IOU_TTC_APB_CLK_OFFSET ,0x000000FFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : WDT_CLK_SEL @ 0XFD610100

- - System watchdog timer clock source selection: 0: Internal APB clock 1: External (PL clock via EMIO or Pinout clock via MIO) - PSU_FPD_SLCR_WDT_CLK_SEL_SELECT 0 - - SWDT clock source select - (OFFSET, MASK, VALUE) (0XFD610100, 0x00000001U ,0x00000000U) - RegMask = (FPD_SLCR_WDT_CLK_SEL_SELECT_MASK | 0 ); - - RegVal = ((0x00000000U << FPD_SLCR_WDT_CLK_SEL_SELECT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (FPD_SLCR_WDT_CLK_SEL_OFFSET ,0x00000001U ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : WDT_CLK_SEL @ 0XFF180300

- - System watchdog timer clock source selection: 0: internal clock APB clock 1: external clock from PL via EMIO, or from pinout - ia MIO - PSU_IOU_SLCR_WDT_CLK_SEL_SELECT 0 - - SWDT clock source select - (OFFSET, MASK, VALUE) (0XFF180300, 0x00000001U ,0x00000000U) - RegMask = (IOU_SLCR_WDT_CLK_SEL_SELECT_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_WDT_CLK_SEL_SELECT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_WDT_CLK_SEL_OFFSET ,0x00000001U ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : CSUPMU_WDT_CLK_SEL @ 0XFF410050

- - System watchdog timer clock source selection: 0: internal clock APB clock 1: external clock pss_ref_clk - PSU_LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT 0 - - SWDT clock source select - (OFFSET, MASK, VALUE) (0XFF410050, 0x00000001U ,0x00000000U) - RegMask = (LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_MASK | 0 ); - - RegVal = ((0x00000000U << LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (LPD_SLCR_CSUPMU_WDT_CLK_SEL_OFFSET ,0x00000001U ,0x00000000U); - /*############################################################################################################################ */ - - - return 1; + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_CAN1_REF_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_CAN1_REF_CTRL_DIVISOR1 0x1 + + * 6 bit divider + * PSU_CRL_APB_CAN1_REF_CTRL_DIVISOR0 0xf + + * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_CAN1_REF_CTRL_SRCSEL 0x0 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E0088, 0x013F3F07U ,0x01010F00U) + */ + PSU_Mask_Write(CRL_APB_CAN1_REF_CTRL_OFFSET, + 0x013F3F07U, 0x01010F00U); +/*##################################################################### */ + + /* + * Register : CPU_R5_CTRL @ 0XFF5E0090 + + * Turing this off will shut down the OCM, some parts of the APM, and preve + * nt transactions going from the FPD to the LPD and could lead to system h + * ang + * PSU_CRL_APB_CPU_R5_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_CPU_R5_CTRL_DIVISOR0 0x3 + + * 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_CPU_R5_CTRL_SRCSEL 0x2 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E0090, 0x01003F07U ,0x01000302U) + */ + PSU_Mask_Write(CRL_APB_CPU_R5_CTRL_OFFSET, 0x01003F07U, 0x01000302U); +/*##################################################################### */ + + /* + * Register : IOU_SWITCH_CTRL @ 0XFF5E009C + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_IOU_SWITCH_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_IOU_SWITCH_CTRL_DIVISOR0 0x6 + + * 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_IOU_SWITCH_CTRL_SRCSEL 0x2 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E009C, 0x01003F07U ,0x01000602U) + */ + PSU_Mask_Write(CRL_APB_IOU_SWITCH_CTRL_OFFSET, + 0x01003F07U, 0x01000602U); +/*##################################################################### */ + + /* + * Register : PCAP_CTRL @ 0XFF5E00A4 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_PCAP_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_PCAP_CTRL_DIVISOR0 0x8 + + * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_PCAP_CTRL_SRCSEL 0x0 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E00A4, 0x01003F07U ,0x01000800U) + */ + PSU_Mask_Write(CRL_APB_PCAP_CTRL_OFFSET, 0x01003F07U, 0x01000800U); +/*##################################################################### */ + + /* + * Register : LPD_SWITCH_CTRL @ 0XFF5E00A8 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_LPD_SWITCH_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_LPD_SWITCH_CTRL_DIVISOR0 0x3 + + * 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_LPD_SWITCH_CTRL_SRCSEL 0x2 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E00A8, 0x01003F07U ,0x01000302U) + */ + PSU_Mask_Write(CRL_APB_LPD_SWITCH_CTRL_OFFSET, + 0x01003F07U, 0x01000302U); +/*##################################################################### */ + + /* + * Register : LPD_LSBUS_CTRL @ 0XFF5E00AC + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_LPD_LSBUS_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_LPD_LSBUS_CTRL_DIVISOR0 0xf + + * 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_LPD_LSBUS_CTRL_SRCSEL 0x2 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E00AC, 0x01003F07U ,0x01000F02U) + */ + PSU_Mask_Write(CRL_APB_LPD_LSBUS_CTRL_OFFSET, + 0x01003F07U, 0x01000F02U); +/*##################################################################### */ + + /* + * Register : DBG_LPD_CTRL @ 0XFF5E00B0 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_DBG_LPD_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_DBG_LPD_CTRL_DIVISOR0 0x6 + + * 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_DBG_LPD_CTRL_SRCSEL 0x2 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E00B0, 0x01003F07U ,0x01000602U) + */ + PSU_Mask_Write(CRL_APB_DBG_LPD_CTRL_OFFSET, + 0x01003F07U, 0x01000602U); +/*##################################################################### */ + + /* + * Register : ADMA_REF_CTRL @ 0XFF5E00B8 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_ADMA_REF_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_ADMA_REF_CTRL_DIVISOR0 0x3 + + * 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_ADMA_REF_CTRL_SRCSEL 0x2 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E00B8, 0x01003F07U ,0x01000302U) + */ + PSU_Mask_Write(CRL_APB_ADMA_REF_CTRL_OFFSET, + 0x01003F07U, 0x01000302U); +/*##################################################################### */ + + /* + * Register : PL0_REF_CTRL @ 0XFF5E00C0 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_PL0_REF_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_PL0_REF_CTRL_DIVISOR1 0x1 + + * 6 bit divider + * PSU_CRL_APB_PL0_REF_CTRL_DIVISOR0 0xf + + * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_PL0_REF_CTRL_SRCSEL 0x0 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E00C0, 0x013F3F07U ,0x01010F00U) + */ + PSU_Mask_Write(CRL_APB_PL0_REF_CTRL_OFFSET, + 0x013F3F07U, 0x01010F00U); +/*##################################################################### */ + + /* + * Register : AMS_REF_CTRL @ 0XFF5E0108 + + * 6 bit divider + * PSU_CRL_APB_AMS_REF_CTRL_DIVISOR1 0x1 + + * 6 bit divider + * PSU_CRL_APB_AMS_REF_CTRL_DIVISOR0 0x1e + + * 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_AMS_REF_CTRL_SRCSEL 0x2 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_AMS_REF_CTRL_CLKACT 0x1 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E0108, 0x013F3F07U ,0x01011E02U) + */ + PSU_Mask_Write(CRL_APB_AMS_REF_CTRL_OFFSET, + 0x013F3F07U, 0x01011E02U); +/*##################################################################### */ + + /* + * Register : DLL_REF_CTRL @ 0XFF5E0104 + + * 000 = IOPLL; 001 = RPLL; (This signal may only be toggled after 4 cycles + * of the old clock and 4 cycles of the new clock. This is not usually an + * issue, but designers must be aware.) + * PSU_CRL_APB_DLL_REF_CTRL_SRCSEL 0 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E0104, 0x00000007U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_DLL_REF_CTRL_OFFSET, + 0x00000007U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : TIMESTAMP_REF_CTRL @ 0XFF5E0128 + + * 6 bit divider + * PSU_CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0 0xf + + * 1XX = pss_ref_clk; 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may + * only be toggled after 4 cycles of the old clock and 4 cycles of the new + * clock. This is not usually an issue, but designers must be aware.) + * PSU_CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL 0x0 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT 0x1 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E0128, 0x01003F07U ,0x01000F00U) + */ + PSU_Mask_Write(CRL_APB_TIMESTAMP_REF_CTRL_OFFSET, + 0x01003F07U, 0x01000F00U); +/*##################################################################### */ + + /* + * Register : SATA_REF_CTRL @ 0XFD1A00A0 + + * 000 = IOPLL_TO_FPD; 010 = APLL; 011 = DPLL; (This signal may only be tog + * gled after 4 cycles of the old clock and 4 cycles of the new clock. This + * is not usually an issue, but designers must be aware.) + * PSU_CRF_APB_SATA_REF_CTRL_SRCSEL 0x0 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRF_APB_SATA_REF_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRF_APB_SATA_REF_CTRL_DIVISOR0 0x2 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFD1A00A0, 0x01003F07U ,0x01000200U) + */ + PSU_Mask_Write(CRF_APB_SATA_REF_CTRL_OFFSET, + 0x01003F07U, 0x01000200U); +/*##################################################################### */ + + /* + * Register : PCIE_REF_CTRL @ 0XFD1A00B4 + + * 000 = IOPLL_TO_FPD; 010 = RPLL_TO_FPD; 011 = DPLL; (This signal may only + * be toggled after 4 cycles of the old clock and 4 cycles of the new cloc + * k. This is not usually an issue, but designers must be aware.) + * PSU_CRF_APB_PCIE_REF_CTRL_SRCSEL 0x0 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRF_APB_PCIE_REF_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRF_APB_PCIE_REF_CTRL_DIVISOR0 0x2 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFD1A00B4, 0x01003F07U ,0x01000200U) + */ + PSU_Mask_Write(CRF_APB_PCIE_REF_CTRL_OFFSET, + 0x01003F07U, 0x01000200U); +/*##################################################################### */ + + /* + * Register : DP_VIDEO_REF_CTRL @ 0XFD1A0070 + + * 6 bit divider + * PSU_CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1 0x1 + + * 6 bit divider + * PSU_CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0 0x5 + + * 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (T + * his signal may only be toggled after 4 cycles of the old clock and 4 cyc + * les of the new clock. This is not usually an issue, but designers must b + * e aware.) + * PSU_CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL 0x0 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRF_APB_DP_VIDEO_REF_CTRL_CLKACT 0x1 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFD1A0070, 0x013F3F07U ,0x01010500U) + */ + PSU_Mask_Write(CRF_APB_DP_VIDEO_REF_CTRL_OFFSET, + 0x013F3F07U, 0x01010500U); +/*##################################################################### */ + + /* + * Register : DP_AUDIO_REF_CTRL @ 0XFD1A0074 + + * 6 bit divider + * PSU_CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1 0x1 + + * 6 bit divider + * PSU_CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0 0xf + + * 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (T + * his signal may only be toggled after 4 cycles of the old clock and 4 cyc + * les of the new clock. This is not usually an issue, but designers must b + * e aware.) + * PSU_CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL 0x3 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRF_APB_DP_AUDIO_REF_CTRL_CLKACT 0x1 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFD1A0074, 0x013F3F07U ,0x01010F03U) + */ + PSU_Mask_Write(CRF_APB_DP_AUDIO_REF_CTRL_OFFSET, + 0x013F3F07U, 0x01010F03U); +/*##################################################################### */ + + /* + * Register : DP_STC_REF_CTRL @ 0XFD1A007C + + * 6 bit divider + * PSU_CRF_APB_DP_STC_REF_CTRL_DIVISOR1 0x1 + + * 6 bit divider + * PSU_CRF_APB_DP_STC_REF_CTRL_DIVISOR0 0xe + + * 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD; (This signal may only be togg + * led after 4 cycles of the old clock and 4 cycles of the new clock. This + * is not usually an issue, but designers must be aware.) + * PSU_CRF_APB_DP_STC_REF_CTRL_SRCSEL 0x3 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRF_APB_DP_STC_REF_CTRL_CLKACT 0x1 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFD1A007C, 0x013F3F07U ,0x01010E03U) + */ + PSU_Mask_Write(CRF_APB_DP_STC_REF_CTRL_OFFSET, + 0x013F3F07U, 0x01010E03U); +/*##################################################################### */ + + /* + * Register : ACPU_CTRL @ 0XFD1A0060 + + * 6 bit divider + * PSU_CRF_APB_ACPU_CTRL_DIVISOR0 0x1 + + * 000 = APLL; 010 = DPLL; 011 = VPLL; (This signal may only be toggled aft + * er 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRF_APB_ACPU_CTRL_SRCSEL 0x0 + + * Clock active signal. Switch to 0 to disable the clock. For the half spee + * d APU Clock + * PSU_CRF_APB_ACPU_CTRL_CLKACT_HALF 0x1 + + * Clock active signal. Switch to 0 to disable the clock. For the full spee + * d ACPUX Clock. This will shut off the high speed clock to the entire APU + * PSU_CRF_APB_ACPU_CTRL_CLKACT_FULL 0x1 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFD1A0060, 0x03003F07U ,0x03000100U) + */ + PSU_Mask_Write(CRF_APB_ACPU_CTRL_OFFSET, 0x03003F07U, 0x03000100U); +/*##################################################################### */ + + /* + * Register : DBG_FPD_CTRL @ 0XFD1A0068 + + * 6 bit divider + * PSU_CRF_APB_DBG_FPD_CTRL_DIVISOR0 0x2 + + * 000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be tog + * gled after 4 cycles of the old clock and 4 cycles of the new clock. This + * is not usually an issue, but designers must be aware.) + * PSU_CRF_APB_DBG_FPD_CTRL_SRCSEL 0x0 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRF_APB_DBG_FPD_CTRL_CLKACT 0x1 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFD1A0068, 0x01003F07U ,0x01000200U) + */ + PSU_Mask_Write(CRF_APB_DBG_FPD_CTRL_OFFSET, + 0x01003F07U, 0x01000200U); +/*##################################################################### */ + + /* + * Register : DDR_CTRL @ 0XFD1A0080 + + * 6 bit divider + * PSU_CRF_APB_DDR_CTRL_DIVISOR0 0x2 + + * 000 = DPLL; 001 = VPLL; (This signal may only be toggled after 4 cycles + * of the old clock and 4 cycles of the new clock. This is not usually an i + * ssue, but designers must be aware.) + * PSU_CRF_APB_DDR_CTRL_SRCSEL 0x0 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFD1A0080, 0x00003F07U ,0x00000200U) + */ + PSU_Mask_Write(CRF_APB_DDR_CTRL_OFFSET, 0x00003F07U, 0x00000200U); +/*##################################################################### */ + + /* + * Register : GPU_REF_CTRL @ 0XFD1A0084 + + * 6 bit divider + * PSU_CRF_APB_GPU_REF_CTRL_DIVISOR0 0x1 + + * 000 = IOPLL_TO_FPD; 010 = VPLL; 011 = DPLL; (This signal may only be tog + * gled after 4 cycles of the old clock and 4 cycles of the new clock. This + * is not usually an issue, but designers must be aware.) + * PSU_CRF_APB_GPU_REF_CTRL_SRCSEL 0x0 + + * Clock active signal. Switch to 0 to disable the clock, which will stop c + * lock for GPU (and both Pixel Processors). + * PSU_CRF_APB_GPU_REF_CTRL_CLKACT 0x1 + + * Clock active signal for Pixel Processor. Switch to 0 to disable the cloc + * k only to this Pixel Processor + * PSU_CRF_APB_GPU_REF_CTRL_PP0_CLKACT 0x1 + + * Clock active signal for Pixel Processor. Switch to 0 to disable the cloc + * k only to this Pixel Processor + * PSU_CRF_APB_GPU_REF_CTRL_PP1_CLKACT 0x1 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFD1A0084, 0x07003F07U ,0x07000100U) + */ + PSU_Mask_Write(CRF_APB_GPU_REF_CTRL_OFFSET, + 0x07003F07U, 0x07000100U); +/*##################################################################### */ + + /* + * Register : GDMA_REF_CTRL @ 0XFD1A00B8 + + * 6 bit divider + * PSU_CRF_APB_GDMA_REF_CTRL_DIVISOR0 0x2 + + * 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled aft + * er 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRF_APB_GDMA_REF_CTRL_SRCSEL 0x0 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRF_APB_GDMA_REF_CTRL_CLKACT 0x1 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFD1A00B8, 0x01003F07U ,0x01000200U) + */ + PSU_Mask_Write(CRF_APB_GDMA_REF_CTRL_OFFSET, + 0x01003F07U, 0x01000200U); +/*##################################################################### */ + + /* + * Register : DPDMA_REF_CTRL @ 0XFD1A00BC + + * 6 bit divider + * PSU_CRF_APB_DPDMA_REF_CTRL_DIVISOR0 0x2 + + * 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled aft + * er 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRF_APB_DPDMA_REF_CTRL_SRCSEL 0x0 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRF_APB_DPDMA_REF_CTRL_CLKACT 0x1 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFD1A00BC, 0x01003F07U ,0x01000200U) + */ + PSU_Mask_Write(CRF_APB_DPDMA_REF_CTRL_OFFSET, + 0x01003F07U, 0x01000200U); +/*##################################################################### */ + + /* + * Register : TOPSW_MAIN_CTRL @ 0XFD1A00C0 + + * 6 bit divider + * PSU_CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0 0x2 + + * 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled aft + * er 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRF_APB_TOPSW_MAIN_CTRL_SRCSEL 0x3 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRF_APB_TOPSW_MAIN_CTRL_CLKACT 0x1 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFD1A00C0, 0x01003F07U ,0x01000203U) + */ + PSU_Mask_Write(CRF_APB_TOPSW_MAIN_CTRL_OFFSET, + 0x01003F07U, 0x01000203U); +/*##################################################################### */ + + /* + * Register : TOPSW_LSBUS_CTRL @ 0XFD1A00C4 + + * 6 bit divider + * PSU_CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0 0x5 + + * 000 = APLL; 010 = IOPLL_TO_FPD; 011 = DPLL; (This signal may only be tog + * gled after 4 cycles of the old clock and 4 cycles of the new clock. This + * is not usually an issue, but designers must be aware.) + * PSU_CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL 0x2 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRF_APB_TOPSW_LSBUS_CTRL_CLKACT 0x1 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFD1A00C4, 0x01003F07U ,0x01000502U) + */ + PSU_Mask_Write(CRF_APB_TOPSW_LSBUS_CTRL_OFFSET, + 0x01003F07U, 0x01000502U); +/*##################################################################### */ + + /* + * Register : DBG_TSTMP_CTRL @ 0XFD1A00F8 + + * 6 bit divider + * PSU_CRF_APB_DBG_TSTMP_CTRL_DIVISOR0 0x2 + + * 000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be tog + * gled after 4 cycles of the old clock and 4 cycles of the new clock. This + * is not usually an issue, but designers must be aware.) + * PSU_CRF_APB_DBG_TSTMP_CTRL_SRCSEL 0x0 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFD1A00F8, 0x00003F07U ,0x00000200U) + */ + PSU_Mask_Write(CRF_APB_DBG_TSTMP_CTRL_OFFSET, + 0x00003F07U, 0x00000200U); +/*##################################################################### */ + + /* + * Register : IOU_TTC_APB_CLK @ 0XFF180380 + + * 00" = Select the APB switch clock for the APB interface of TTC0'01" = Se + * lect the PLL ref clock for the APB interface of TTC0'10" = Select the R5 + * clock for the APB interface of TTC0 + * PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL 0 + + * 00" = Select the APB switch clock for the APB interface of TTC1'01" = Se + * lect the PLL ref clock for the APB interface of TTC1'10" = Select the R5 + * clock for the APB interface of TTC1 + * PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL 0 + + * 00" = Select the APB switch clock for the APB interface of TTC2'01" = Se + * lect the PLL ref clock for the APB interface of TTC2'10" = Select the R5 + * clock for the APB interface of TTC2 + * PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL 0 + + * 00" = Select the APB switch clock for the APB interface of TTC3'01" = Se + * lect the PLL ref clock for the APB interface of TTC3'10" = Select the R5 + * clock for the APB interface of TTC3 + * PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL 0 + + * TTC APB clock select + * (OFFSET, MASK, VALUE) (0XFF180380, 0x000000FFU ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_IOU_TTC_APB_CLK_OFFSET, + 0x000000FFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : WDT_CLK_SEL @ 0XFD610100 + + * System watchdog timer clock source selection: 0: Internal APB clock 1: E + * xternal (PL clock via EMIO or Pinout clock via MIO) + * PSU_FPD_SLCR_WDT_CLK_SEL_SELECT 0 + + * SWDT clock source select + * (OFFSET, MASK, VALUE) (0XFD610100, 0x00000001U ,0x00000000U) + */ + PSU_Mask_Write(FPD_SLCR_WDT_CLK_SEL_OFFSET, + 0x00000001U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : WDT_CLK_SEL @ 0XFF180300 + + * System watchdog timer clock source selection: 0: internal clock APB cloc + * k 1: external clock from PL via EMIO, or from pinout via MIO + * PSU_IOU_SLCR_WDT_CLK_SEL_SELECT 0 + + * SWDT clock source select + * (OFFSET, MASK, VALUE) (0XFF180300, 0x00000001U ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_WDT_CLK_SEL_OFFSET, + 0x00000001U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : CSUPMU_WDT_CLK_SEL @ 0XFF410050 + + * System watchdog timer clock source selection: 0: internal clock APB cloc + * k 1: external clock pss_ref_clk + * PSU_LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT 0 + + * SWDT clock source select + * (OFFSET, MASK, VALUE) (0XFF410050, 0x00000001U ,0x00000000U) + */ + PSU_Mask_Write(LPD_SLCR_CSUPMU_WDT_CLK_SEL_OFFSET, + 0x00000001U, 0x00000000U); +/*##################################################################### */ + + + return 1; } -unsigned long psu_ddr_init_data() { - // : DDR INITIALIZATION - // : DDR CONTROLLER RESET - /*Register : RST_DDR_SS @ 0XFD1A0108

- - DDR block level reset inside of the DDR Sub System - PSU_CRF_APB_RST_DDR_SS_DDR_RESET 0X1 - - DDR sub system block level reset - (OFFSET, MASK, VALUE) (0XFD1A0108, 0x00000008U ,0x00000008U) - RegMask = (CRF_APB_RST_DDR_SS_DDR_RESET_MASK | 0 ); - - RegVal = ((0x00000001U << CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_RST_DDR_SS_OFFSET ,0x00000008U ,0x00000008U); - /*############################################################################################################################ */ - - /*Register : MSTR @ 0XFD070000

- - Indicates the configuration of the device used in the system. - 00 - x4 device - 01 - x8 device - 10 - x16 device - 11 - x32 - evice - PSU_DDRC_MSTR_DEVICE_CONFIG 0x1 - - Choose which registers are used. - 0 - Original registers - 1 - Shadow registers - PSU_DDRC_MSTR_FREQUENCY_MODE 0x0 - - Only present for multi-rank configurations. Each bit represents one rank. For two-rank configurations, only bits[25:24] are p - esent. - 1 - populated - 0 - unpopulated LSB is the lowest rank number. For 2 ranks following combinations are legal: - 01 - - ne rank - 11 - Two ranks - Others - Reserved. For 4 ranks following combinations are legal: - 0001 - One rank - 0011 - Two ra - ks - 1111 - Four ranks - PSU_DDRC_MSTR_ACTIVE_RANKS 0x1 - - SDRAM burst length used: - 0001 - Burst length of 2 (only supported for mDDR) - 0010 - Burst length of 4 - 0100 - Burst lengt - of 8 - 1000 - Burst length of 16 (only supported for mDDR, LPDDR2, and LPDDR4) All other values are reserved. This controls - he burst size used to access the SDRAM. This must match the burst length mode register setting in the SDRAM. (For BC4/8 on-th - -fly mode of DDR3 and DDR4, set this field to 0x0100) Burst length of 2 is not supported with AXI ports when MEMC_BURST_LENGT - is 8. Burst length of 2 is only supported with MEMC_FREQ_RATIO = 1 - PSU_DDRC_MSTR_BURST_RDWR 0x4 - - Set to 1 when the uMCTL2 and DRAM has to be put in DLL-off mode for low frequency operation. Set to 0 to put uMCTL2 and DRAM - n DLL-on mode for normal frequency operation. If DDR4 CRC/parity retry is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), d - l_off_mode is not supported, and this bit must be set to '0'. - PSU_DDRC_MSTR_DLL_OFF_MODE 0x0 - - Selects proportion of DQ bus width that is used by the SDRAM - 00 - Full DQ bus width to SDRAM - 01 - Half DQ bus width to SD - AM - 10 - Quarter DQ bus width to SDRAM - 11 - Reserved. Note that half bus width mode is only supported when the SDRAM bus w - dth is a multiple of 16, and quarter bus width mode is only supported when the SDRAM bus width is a multiple of 32 and the co - figuration parameter MEMC_QBUS_SUPPORT is set. Bus width refers to DQ bus width (excluding any ECC width). - PSU_DDRC_MSTR_DATA_BUS_WIDTH 0x0 - - 1 indicates put the DRAM in geardown mode (2N) and 0 indicates put the DRAM in normal mode (1N). This register can be changed - only when the Controller is in self-refresh mode. This signal must be set the same value as MR3 bit A3. Note: Geardown mode - s not supported if the configuration parameter MEMC_CMD_RTN2IDLE is set - PSU_DDRC_MSTR_GEARDOWN_MODE 0x0 - - If 1, then uMCTL2 uses 2T timing. Otherwise, uses 1T timing. In 2T timing, all command signals (except chip select) are held - or 2 clocks on the SDRAM bus. Chip select is asserted on the second cycle of the command Note: 2T timing is not supported in - PDDR2/LPDDR3/LPDDR4 mode Note: 2T timing is not supported if the configuration parameter MEMC_CMD_RTN2IDLE is set Note: 2T ti - ing is not supported in DDR4 geardown mode. - PSU_DDRC_MSTR_EN_2T_TIMING_MODE 0x0 - - When set, enable burst-chop in DDR3/DDR4. Burst Chop for Reads is exercised only in HIF configurations (UMCTL2_INCL_ARB not s - t) and if in full bus width mode (MSTR.data_bus_width = 00). Burst Chop for Writes is exercised only if Partial Writes enable - (UMCTL2_PARTIAL_WR=1) and if CRC is disabled (CRCPARCTL1.crc_enable = 0). If DDR4 CRC/parity retry is enabled (CRCPARCTL1.cr - _parity_retry_enable = 1), burst chop is not supported, and this bit must be set to '0' - PSU_DDRC_MSTR_BURSTCHOP 0x0 - - Select LPDDR4 SDRAM - 1 - LPDDR4 SDRAM device in use. - 0 - non-LPDDR4 device in use Present only in designs configured to su - port LPDDR4. - PSU_DDRC_MSTR_LPDDR4 0x0 - - Select DDR4 SDRAM - 1 - DDR4 SDRAM device in use. - 0 - non-DDR4 device in use Present only in designs configured to support - DR4. - PSU_DDRC_MSTR_DDR4 0x1 - - Select LPDDR3 SDRAM - 1 - LPDDR3 SDRAM device in use. - 0 - non-LPDDR3 device in use Present only in designs configured to su - port LPDDR3. - PSU_DDRC_MSTR_LPDDR3 0x0 - - Select LPDDR2 SDRAM - 1 - LPDDR2 SDRAM device in use. - 0 - non-LPDDR2 device in use Present only in designs configured to su - port LPDDR2. - PSU_DDRC_MSTR_LPDDR2 0x0 - - Select DDR3 SDRAM - 1 - DDR3 SDRAM device in use - 0 - non-DDR3 SDRAM device in use Only present in designs that support DDR3 - - PSU_DDRC_MSTR_DDR3 0x0 - - Master Register - (OFFSET, MASK, VALUE) (0XFD070000, 0xE30FBE3DU ,0x41040010U) - RegMask = (DDRC_MSTR_DEVICE_CONFIG_MASK | DDRC_MSTR_FREQUENCY_MODE_MASK | DDRC_MSTR_ACTIVE_RANKS_MASK | DDRC_MSTR_BURST_RDWR_MASK | DDRC_MSTR_DLL_OFF_MODE_MASK | DDRC_MSTR_DATA_BUS_WIDTH_MASK | DDRC_MSTR_GEARDOWN_MODE_MASK | DDRC_MSTR_EN_2T_TIMING_MODE_MASK | DDRC_MSTR_BURSTCHOP_MASK | DDRC_MSTR_LPDDR4_MASK | DDRC_MSTR_DDR4_MASK | DDRC_MSTR_LPDDR3_MASK | DDRC_MSTR_LPDDR2_MASK | DDRC_MSTR_DDR3_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_MSTR_DEVICE_CONFIG_SHIFT - | 0x00000000U << DDRC_MSTR_FREQUENCY_MODE_SHIFT - | 0x00000001U << DDRC_MSTR_ACTIVE_RANKS_SHIFT - | 0x00000004U << DDRC_MSTR_BURST_RDWR_SHIFT - | 0x00000000U << DDRC_MSTR_DLL_OFF_MODE_SHIFT - | 0x00000000U << DDRC_MSTR_DATA_BUS_WIDTH_SHIFT - | 0x00000000U << DDRC_MSTR_GEARDOWN_MODE_SHIFT - | 0x00000000U << DDRC_MSTR_EN_2T_TIMING_MODE_SHIFT - | 0x00000000U << DDRC_MSTR_BURSTCHOP_SHIFT - | 0x00000000U << DDRC_MSTR_LPDDR4_SHIFT - | 0x00000001U << DDRC_MSTR_DDR4_SHIFT - | 0x00000000U << DDRC_MSTR_LPDDR3_SHIFT - | 0x00000000U << DDRC_MSTR_LPDDR2_SHIFT - | 0x00000000U << DDRC_MSTR_DDR3_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_MSTR_OFFSET ,0xE30FBE3DU ,0x41040010U); - /*############################################################################################################################ */ - - /*Register : MRCTRL0 @ 0XFD070010

- - Setting this register bit to 1 triggers a mode register read or write operation. When the MR operation is complete, the uMCTL - automatically clears this bit. The other register fields of this register must be written in a separate APB transaction, bef - re setting this mr_wr bit. It is recommended NOT to set this signal if in Init, Deep power-down or MPSM operating modes. - PSU_DDRC_MRCTRL0_MR_WR 0x0 - - Address of the mode register that is to be written to. - 0000 - MR0 - 0001 - MR1 - 0010 - MR2 - 0011 - MR3 - 0100 - MR4 - 010 - - MR5 - 0110 - MR6 - 0111 - MR7 Don't Care for LPDDR2/LPDDR3/LPDDR4 (see MRCTRL1.mr_data for mode register addressing in LPD - R2/LPDDR3/LPDDR4) This signal is also used for writing to control words of RDIMMs. In that case, it corresponds to the bank a - dress bits sent to the RDIMM In case of DDR4, the bit[3:2] corresponds to the bank group bits. Therefore, the bit[3] as well - s the bit[2:0] must be set to an appropriate value which is considered both the Address Mirroring of UDIMMs/RDIMMs and the Ou - put Inversion of RDIMMs. - PSU_DDRC_MRCTRL0_MR_ADDR 0x0 - - Controls which rank is accessed by MRCTRL0.mr_wr. Normally, it is desired to access all ranks, so all bits should be set to 1 - However, for multi-rank UDIMMs/RDIMMs which implement address mirroring, it may be necessary to access ranks individually. E - amples (assume uMCTL2 is configured for 4 ranks): - 0x1 - select rank 0 only - 0x2 - select rank 1 only - 0x5 - select ranks - and 2 - 0xA - select ranks 1 and 3 - 0xF - select ranks 0, 1, 2 and 3 - PSU_DDRC_MRCTRL0_MR_RANK 0x3 - - Indicates whether Software intervention is allowed via MRCTRL0/MRCTRL1 before automatic SDRAM initialization routine or not. - or DDR4, this bit can be used to initialize the DDR4 RCD (MR7) before automatic SDRAM initialization. For LPDDR4, this bit ca - be used to program additional mode registers before automatic SDRAM initialization if necessary. Note: This must be cleared - o 0 after completing Software operation. Otherwise, SDRAM initialization routine will not re-start. - 0 - Software interventi - n is not allowed - 1 - Software intervention is allowed - PSU_DDRC_MRCTRL0_SW_INIT_INT 0x0 - - Indicates whether the mode register operation is MRS in PDA mode or not - 0 - MRS - 1 - MRS in Per DRAM Addressability mode - PSU_DDRC_MRCTRL0_PDA_EN 0x0 - - Indicates whether the mode register operation is MRS or WR/RD for MPR (only supported for DDR4) - 0 - MRS - 1 - WR/RD for MPR - PSU_DDRC_MRCTRL0_MPR_EN 0x0 - - Indicates whether the mode register operation is read or write. Only used for LPDDR2/LPDDR3/LPDDR4/DDR4. - 0 - Write - 1 - Re - d - PSU_DDRC_MRCTRL0_MR_TYPE 0x0 - - Mode Register Read/Write Control Register 0. Note: Do not enable more than one of the following fields simultaneously: - sw_i - it_int - pda_en - mpr_en - (OFFSET, MASK, VALUE) (0XFD070010, 0x8000F03FU ,0x00000030U) - RegMask = (DDRC_MRCTRL0_MR_WR_MASK | DDRC_MRCTRL0_MR_ADDR_MASK | DDRC_MRCTRL0_MR_RANK_MASK | DDRC_MRCTRL0_SW_INIT_INT_MASK | DDRC_MRCTRL0_PDA_EN_MASK | DDRC_MRCTRL0_MPR_EN_MASK | DDRC_MRCTRL0_MR_TYPE_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_MRCTRL0_MR_WR_SHIFT - | 0x00000000U << DDRC_MRCTRL0_MR_ADDR_SHIFT - | 0x00000003U << DDRC_MRCTRL0_MR_RANK_SHIFT - | 0x00000000U << DDRC_MRCTRL0_SW_INIT_INT_SHIFT - | 0x00000000U << DDRC_MRCTRL0_PDA_EN_SHIFT - | 0x00000000U << DDRC_MRCTRL0_MPR_EN_SHIFT - | 0x00000000U << DDRC_MRCTRL0_MR_TYPE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_MRCTRL0_OFFSET ,0x8000F03FU ,0x00000030U); - /*############################################################################################################################ */ - - /*Register : DERATEEN @ 0XFD070020

- - Derate value of tRC for LPDDR4 - 0 - Derating uses +1. - 1 - Derating uses +2. - 2 - Derating uses +3. - 3 - Derating uses +4 - Present only in designs configured to support LPDDR4. The required number of cycles for derating can be determined by dividi - g 3.75ns by the core_ddrc_core_clk period, and rounding up the next integer. - PSU_DDRC_DERATEEN_RC_DERATE_VALUE 0x3 - - Derate byte Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4 Indicates which byte of the MRR data is used f - r derating. The maximum valid value depends on MEMC_DRAM_TOTAL_DATA_WIDTH. - PSU_DDRC_DERATEEN_DERATE_BYTE 0x0 - - Derate value - 0 - Derating uses +1. - 1 - Derating uses +2. Present only in designs configured to support LPDDR2/LPDDR3/LPDD - 4 Set to 0 for all LPDDR2 speed grades as derating value of +1.875 ns is less than a core_ddrc_core_clk period. Can be 0 or 1 - for LPDDR3/LPDDR4, depending if +1.875 ns is less than a core_ddrc_core_clk period or not. - PSU_DDRC_DERATEEN_DERATE_VALUE 0x0 - - Enables derating - 0 - Timing parameter derating is disabled - 1 - Timing parameter derating is enabled using MR4 read value. - Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4 This field must be set to '0' for non-LPDDR2/LPDDR3/LPDDR4 - mode. - PSU_DDRC_DERATEEN_DERATE_ENABLE 0x0 - - Temperature Derate Enable Register - (OFFSET, MASK, VALUE) (0XFD070020, 0x000003F3U ,0x00000300U) - RegMask = (DDRC_DERATEEN_RC_DERATE_VALUE_MASK | DDRC_DERATEEN_DERATE_BYTE_MASK | DDRC_DERATEEN_DERATE_VALUE_MASK | DDRC_DERATEEN_DERATE_ENABLE_MASK | 0 ); - - RegVal = ((0x00000003U << DDRC_DERATEEN_RC_DERATE_VALUE_SHIFT - | 0x00000000U << DDRC_DERATEEN_DERATE_BYTE_SHIFT - | 0x00000000U << DDRC_DERATEEN_DERATE_VALUE_SHIFT - | 0x00000000U << DDRC_DERATEEN_DERATE_ENABLE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DERATEEN_OFFSET ,0x000003F3U ,0x00000300U); - /*############################################################################################################################ */ - - /*Register : DERATEINT @ 0XFD070024

- - Interval between two MR4 reads, used to derate the timing parameters. Present only in designs configured to support LPDDR2/LP - DR3/LPDDR4. This register must not be set to zero - PSU_DDRC_DERATEINT_MR4_READ_INTERVAL 0x800000 - - Temperature Derate Interval Register - (OFFSET, MASK, VALUE) (0XFD070024, 0xFFFFFFFFU ,0x00800000U) - RegMask = (DDRC_DERATEINT_MR4_READ_INTERVAL_MASK | 0 ); - - RegVal = ((0x00800000U << DDRC_DERATEINT_MR4_READ_INTERVAL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DERATEINT_OFFSET ,0xFFFFFFFFU ,0x00800000U); - /*############################################################################################################################ */ - - /*Register : PWRCTL @ 0XFD070030

- - Self refresh state is an intermediate state to enter to Self refresh power down state or exit Self refresh power down state f - r LPDDR4. This register controls transition from the Self refresh state. - 1 - Prohibit transition from Self refresh state - - - Allow transition from Self refresh state - PSU_DDRC_PWRCTL_STAY_IN_SELFREF 0x0 - - A value of 1 to this register causes system to move to Self Refresh state immediately, as long as it is not in INIT or DPD/MP - M operating_mode. This is referred to as Software Entry/Exit to Self Refresh. - 1 - Software Entry to Self Refresh - 0 - Soft - are Exit from Self Refresh - PSU_DDRC_PWRCTL_SELFREF_SW 0x0 - - When this is 1, the uMCTL2 puts the SDRAM into maximum power saving mode when the transaction store is empty. This register m - st be reset to '0' to bring uMCTL2 out of maximum power saving mode. Present only in designs configured to support DDR4. For - on-DDR4, this register should not be set to 1. Note that MPSM is not supported when using a DWC DDR PHY, if the PHY parameter - DWC_AC_CS_USE is disabled, as the MPSM exit sequence requires the chip-select signal to toggle. FOR PERFORMANCE ONLY. - PSU_DDRC_PWRCTL_MPSM_EN 0x0 - - Enable the assertion of dfi_dram_clk_disable whenever a clock is not required by the SDRAM. If set to 0, dfi_dram_clk_disable - is never asserted. Assertion of dfi_dram_clk_disable is as follows: In DDR2/DDR3, can only be asserted in Self Refresh. In DD - 4, can be asserted in following: - in Self Refresh. - in Maximum Power Saving Mode In mDDR/LPDDR2/LPDDR3, can be asserted in - ollowing: - in Self Refresh - in Power Down - in Deep Power Down - during Normal operation (Clock Stop) In LPDDR4, can be ass - rted in following: - in Self Refresh Power Down - in Power Down - during Normal operation (Clock Stop) - PSU_DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE 0x0 - - When this is 1, uMCTL2 puts the SDRAM into deep power-down mode when the transaction store is empty. This register must be re - et to '0' to bring uMCTL2 out of deep power-down mode. Controller performs automatic SDRAM initialization on deep power-down - xit. Present only in designs configured to support mDDR or LPDDR2 or LPDDR3. For non-mDDR/non-LPDDR2/non-LPDDR3, this registe - should not be set to 1. FOR PERFORMANCE ONLY. - PSU_DDRC_PWRCTL_DEEPPOWERDOWN_EN 0x0 - - If true then the uMCTL2 goes into power-down after a programmable number of cycles 'maximum idle clocks before power down' (P - RTMG.powerdown_to_x32). This register bit may be re-programmed during the course of normal operation. - PSU_DDRC_PWRCTL_POWERDOWN_EN 0x0 - - If true then the uMCTL2 puts the SDRAM into Self Refresh after a programmable number of cycles 'maximum idle clocks before Se - f Refresh (PWRTMG.selfref_to_x32)'. This register bit may be re-programmed during the course of normal operation. - PSU_DDRC_PWRCTL_SELFREF_EN 0x0 - - Low Power Control Register - (OFFSET, MASK, VALUE) (0XFD070030, 0x0000007FU ,0x00000000U) - RegMask = (DDRC_PWRCTL_STAY_IN_SELFREF_MASK | DDRC_PWRCTL_SELFREF_SW_MASK | DDRC_PWRCTL_MPSM_EN_MASK | DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_MASK | DDRC_PWRCTL_DEEPPOWERDOWN_EN_MASK | DDRC_PWRCTL_POWERDOWN_EN_MASK | DDRC_PWRCTL_SELFREF_EN_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_PWRCTL_STAY_IN_SELFREF_SHIFT - | 0x00000000U << DDRC_PWRCTL_SELFREF_SW_SHIFT - | 0x00000000U << DDRC_PWRCTL_MPSM_EN_SHIFT - | 0x00000000U << DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_SHIFT - | 0x00000000U << DDRC_PWRCTL_DEEPPOWERDOWN_EN_SHIFT - | 0x00000000U << DDRC_PWRCTL_POWERDOWN_EN_SHIFT - | 0x00000000U << DDRC_PWRCTL_SELFREF_EN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PWRCTL_OFFSET ,0x0000007FU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : PWRTMG @ 0XFD070034

- - After this many clocks of NOP or deselect the uMCTL2 automatically puts the SDRAM into Self Refresh. This must be enabled in - he PWRCTL.selfref_en. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY. - PSU_DDRC_PWRTMG_SELFREF_TO_X32 0x40 - - Minimum deep power-down time. For mDDR, value from the JEDEC specification is 0 as mDDR exits from deep power-down mode immed - ately after PWRCTL.deeppowerdown_en is de-asserted. For LPDDR2/LPDDR3, value from the JEDEC specification is 500us. Unit: Mul - iples of 4096 clocks. Present only in designs configured to support mDDR, LPDDR2 or LPDDR3. FOR PERFORMANCE ONLY. - PSU_DDRC_PWRTMG_T_DPD_X4096 0x84 - - After this many clocks of NOP or deselect the uMCTL2 automatically puts the SDRAM into power-down. This must be enabled in th - PWRCTL.powerdown_en. Unit: Multiples of 32 clocks FOR PERFORMANCE ONLY. - PSU_DDRC_PWRTMG_POWERDOWN_TO_X32 0x10 - - Low Power Timing Register - (OFFSET, MASK, VALUE) (0XFD070034, 0x00FFFF1FU ,0x00408410U) - RegMask = (DDRC_PWRTMG_SELFREF_TO_X32_MASK | DDRC_PWRTMG_T_DPD_X4096_MASK | DDRC_PWRTMG_POWERDOWN_TO_X32_MASK | 0 ); - - RegVal = ((0x00000040U << DDRC_PWRTMG_SELFREF_TO_X32_SHIFT - | 0x00000084U << DDRC_PWRTMG_T_DPD_X4096_SHIFT - | 0x00000010U << DDRC_PWRTMG_POWERDOWN_TO_X32_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PWRTMG_OFFSET ,0x00FFFF1FU ,0x00408410U); - /*############################################################################################################################ */ - - /*Register : RFSHCTL0 @ 0XFD070050

- - Threshold value in number of clock cycles before the critical refresh or page timer expires. A critical refresh is to be issu - d before this threshold is reached. It is recommended that this not be changed from the default value, currently shown as 0x2 - It must always be less than internally used t_rfc_nom_x32. Note that, in LPDDR2/LPDDR3/LPDDR4, internally used t_rfc_nom_x32 - may be equal to RFSHTMG.t_rfc_nom_x32>>2 if derating is enabled (DERATEEN.derate_enable=1). Otherwise, internally used t_rfc_ - om_x32 will be equal to RFSHTMG.t_rfc_nom_x32. Unit: Multiples of 32 clocks. - PSU_DDRC_RFSHCTL0_REFRESH_MARGIN 0x2 - - If the refresh timer (tRFCnom, also known as tREFI) has expired at least once, but it has not expired (RFSHCTL0.refresh_burst - 1) times yet, then a speculative refresh may be performed. A speculative refresh is a refresh performed at a time when refres - would be useful, but before it is absolutely required. When the SDRAM bus is idle for a period of time determined by this RF - HCTL0.refresh_to_x32 and the refresh timer has expired at least once since the last refresh, then a speculative refresh is pe - formed. Speculative refreshes continues successively until there are no refreshes pending or until new reads or writes are is - ued to the uMCTL2. FOR PERFORMANCE ONLY. - PSU_DDRC_RFSHCTL0_REFRESH_TO_X32 0x10 - - The programmed value + 1 is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the re - reshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of re - reshes. Therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for - RFSHCTL.refresh_burst slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshe - . - 0 - single refresh - 1 - burst-of-2 refresh - 7 - burst-of-8 refresh For information on burst refresh feature refer to se - tion 3.9 of DDR2 JEDEC specification - JESD79-2F.pdf. For DDR2/3, the refresh is always per-rank and not per-bank. The rank r - fresh can be accumulated over 8*tREFI cycles using the burst refresh feature. In DDR4 mode, according to Fine Granularity fea - ure, 8 refreshes can be postponed in 1X mode, 16 refreshes in 2X mode and 32 refreshes in 4X mode. If using PHY-initiated upd - tes, care must be taken in the setting of RFSHCTL0.refresh_burst, to ensure that tRFCmax is not violated due to a PHY-initiat - d update occurring shortly before a refresh burst was due. In this situation, the refresh burst will be delayed until the PHY - initiated update is complete. - PSU_DDRC_RFSHCTL0_REFRESH_BURST 0x0 - - - 1 - Per bank refresh; - 0 - All bank refresh. Per bank refresh allows traffic to flow to other banks. Per bank refresh is n - t supported by all LPDDR2 devices but should be supported by all LPDDR3/LPDDR4 devices. Present only in designs configured to - support LPDDR2/LPDDR3/LPDDR4 - PSU_DDRC_RFSHCTL0_PER_BANK_REFRESH 0x0 - - Refresh Control Register 0 - (OFFSET, MASK, VALUE) (0XFD070050, 0x00F1F1F4U ,0x00210000U) - RegMask = (DDRC_RFSHCTL0_REFRESH_MARGIN_MASK | DDRC_RFSHCTL0_REFRESH_TO_X32_MASK | DDRC_RFSHCTL0_REFRESH_BURST_MASK | DDRC_RFSHCTL0_PER_BANK_REFRESH_MASK | 0 ); - - RegVal = ((0x00000002U << DDRC_RFSHCTL0_REFRESH_MARGIN_SHIFT - | 0x00000010U << DDRC_RFSHCTL0_REFRESH_TO_X32_SHIFT - | 0x00000000U << DDRC_RFSHCTL0_REFRESH_BURST_SHIFT - | 0x00000000U << DDRC_RFSHCTL0_PER_BANK_REFRESH_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_RFSHCTL0_OFFSET ,0x00F1F1F4U ,0x00210000U); - /*############################################################################################################################ */ - - /*Register : RFSHCTL3 @ 0XFD070060

- - Fine Granularity Refresh Mode - 000 - Fixed 1x (Normal mode) - 001 - Fixed 2x - 010 - Fixed 4x - 101 - Enable on the fly 2x ( - ot supported) - 110 - Enable on the fly 4x (not supported) - Everything else - reserved Note: The on-the-fly modes is not sup - orted in this version of the uMCTL2. Note: This must be set up while the Controller is in reset or while the Controller is in - self-refresh mode. Changing this during normal operation is not allowed. Making this a dynamic register will be supported in - uture version of the uMCTL2. - PSU_DDRC_RFSHCTL3_REFRESH_MODE 0x0 - - Toggle this signal (either from 0 to 1 or from 1 to 0) to indicate that the refresh register(s) have been updated. The value - s automatically updated when exiting reset, so it does not need to be toggled initially. - PSU_DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL 0x0 - - When '1', disable auto-refresh generated by the uMCTL2. When auto-refresh is disabled, the SoC core must generate refreshes u - ing the registers reg_ddrc_rank0_refresh, reg_ddrc_rank1_refresh, reg_ddrc_rank2_refresh and reg_ddrc_rank3_refresh. When dis - auto_refresh transitions from 0 to 1, any pending refreshes are immediately scheduled by the uMCTL2. If DDR4 CRC/parity retry - is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), disable auto-refresh is not supported, and this bit must be set to '0'. - his register field is changeable on the fly. - PSU_DDRC_RFSHCTL3_DIS_AUTO_REFRESH 0x1 - - Refresh Control Register 3 - (OFFSET, MASK, VALUE) (0XFD070060, 0x00000073U ,0x00000001U) - RegMask = (DDRC_RFSHCTL3_REFRESH_MODE_MASK | DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_MASK | DDRC_RFSHCTL3_DIS_AUTO_REFRESH_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_RFSHCTL3_REFRESH_MODE_SHIFT - | 0x00000000U << DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_SHIFT - | 0x00000001U << DDRC_RFSHCTL3_DIS_AUTO_REFRESH_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_RFSHCTL3_OFFSET ,0x00000073U ,0x00000001U); - /*############################################################################################################################ */ - - /*Register : RFSHTMG @ 0XFD070064

- - tREFI: Average time interval between refreshes per rank (Specification: 7.8us for DDR2, DDR3 and DDR4. See JEDEC specificatio - for mDDR, LPDDR2, LPDDR3 and LPDDR4). For LPDDR2/LPDDR3/LPDDR4: - if using all-bank refreshes (RFSHCTL0.per_bank_refresh = 0 - , this register should be set to tREFIab - if using per-bank refreshes (RFSHCTL0.per_bank_refresh = 1), this register should - e set to tREFIpb For configurations with MEMC_FREQ_RATIO=2, program this to (tREFI/2), no rounding up. In DDR4 mode, tREFI va - ue is different depending on the refresh mode. The user should program the appropriate value from the spec based on the value - programmed in the refresh mode register. Note that RFSHTMG.t_rfc_nom_x32 * 32 must be greater than RFSHTMG.t_rfc_min, and RFS - TMG.t_rfc_nom_x32 must be greater than 0x1. Unit: Multiples of 32 clocks. - PSU_DDRC_RFSHTMG_T_RFC_NOM_X32 0x82 - - Used only when LPDDR3 memory type is connected. Should only be changed when uMCTL2 is in reset. Specifies whether to use the - REFBW parameter (required by some LPDDR3 devices which comply with earlier versions of the LPDDR3 JEDEC specification) or not - - 0 - tREFBW parameter not used - 1 - tREFBW parameter used - PSU_DDRC_RFSHTMG_LPDDR3_TREFBW_EN 0x1 - - tRFC (min): Minimum time from refresh to refresh or activate. For MEMC_FREQ_RATIO=1 configurations, t_rfc_min should be set t - RoundUp(tRFCmin/tCK). For MEMC_FREQ_RATIO=2 configurations, t_rfc_min should be set to RoundUp(RoundUp(tRFCmin/tCK)/2). In L - DDR2/LPDDR3/LPDDR4 mode: - if using all-bank refreshes, the tRFCmin value in the above equations is equal to tRFCab - if usin - per-bank refreshes, the tRFCmin value in the above equations is equal to tRFCpb In DDR4 mode, the tRFCmin value in the above - equations is different depending on the refresh mode (fixed 1X,2X,4X) and the device density. The user should program the app - opriate value from the spec based on the 'refresh_mode' and the device density that is used. Unit: Clocks. - PSU_DDRC_RFSHTMG_T_RFC_MIN 0x8b - - Refresh Timing Register - (OFFSET, MASK, VALUE) (0XFD070064, 0x0FFF83FFU ,0x0082808BU) - RegMask = (DDRC_RFSHTMG_T_RFC_NOM_X32_MASK | DDRC_RFSHTMG_LPDDR3_TREFBW_EN_MASK | DDRC_RFSHTMG_T_RFC_MIN_MASK | 0 ); - - RegVal = ((0x00000082U << DDRC_RFSHTMG_T_RFC_NOM_X32_SHIFT - | 0x00000001U << DDRC_RFSHTMG_LPDDR3_TREFBW_EN_SHIFT - | 0x0000008BU << DDRC_RFSHTMG_T_RFC_MIN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_RFSHTMG_OFFSET ,0x0FFF83FFU ,0x0082808BU); - /*############################################################################################################################ */ - - /*Register : ECCCFG0 @ 0XFD070070

- - Disable ECC scrubs. Valid only when ECCCFG0.ecc_mode = 3'b100 and MEMC_USE_RMW is defined - PSU_DDRC_ECCCFG0_DIS_SCRUB 0x1 - - ECC mode indicator - 000 - ECC disabled - 100 - ECC enabled - SEC/DED over 1 beat - all other settings are reserved for futur - use - PSU_DDRC_ECCCFG0_ECC_MODE 0x0 - - ECC Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD070070, 0x00000017U ,0x00000010U) - RegMask = (DDRC_ECCCFG0_DIS_SCRUB_MASK | DDRC_ECCCFG0_ECC_MODE_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_ECCCFG0_DIS_SCRUB_SHIFT - | 0x00000000U << DDRC_ECCCFG0_ECC_MODE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_ECCCFG0_OFFSET ,0x00000017U ,0x00000010U); - /*############################################################################################################################ */ - - /*Register : ECCCFG1 @ 0XFD070074

- - Selects whether to poison 1 or 2 bits - if 0 -> 2-bit (uncorrectable) data poisoning, if 1 -> 1-bit (correctable) data poison - ng, if ECCCFG1.data_poison_en=1 - PSU_DDRC_ECCCFG1_DATA_POISON_BIT 0x0 - - Enable ECC data poisoning - introduces ECC errors on writes to address specified by the ECCPOISONADDR0/1 registers - PSU_DDRC_ECCCFG1_DATA_POISON_EN 0x0 - - ECC Configuration Register 1 - (OFFSET, MASK, VALUE) (0XFD070074, 0x00000003U ,0x00000000U) - RegMask = (DDRC_ECCCFG1_DATA_POISON_BIT_MASK | DDRC_ECCCFG1_DATA_POISON_EN_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_ECCCFG1_DATA_POISON_BIT_SHIFT - | 0x00000000U << DDRC_ECCCFG1_DATA_POISON_EN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_ECCCFG1_OFFSET ,0x00000003U ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : CRCPARCTL1 @ 0XFD0700C4

- - The maximum number of DFI PHY clock cycles allowed from the assertion of the dfi_rddata_en signal to the assertion of each of - the corresponding bits of the dfi_rddata_valid signal. This corresponds to the DFI timing parameter tphy_rdlat. Refer to PHY - pecification for correct value. This value it only used for detecting read data timeout when DDR4 retry is enabled by CRCPARC - L1.crc_parity_retry_enable=1. Maximum supported value: - 1:1 Frequency mode : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_ - dlat < 'd114 - 1:2 Frequency mode ANDAND DFITMG0.dfi_rddata_use_sdr == 1 : CRCPARCTL1.dfi_t_phy_rdlat < 64 - 1:2 Frequency mo - e ANDAND DFITMG0.dfi_rddata_use_sdr == 0 : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_rdlat < 'd114 Unit: DFI Clocks - PSU_DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT 0x10 - - After a Parity or CRC error is flagged on dfi_alert_n signal, the software has an option to read the mode registers in the DR - M before the hardware begins the retry process - 1: Wait for software to read/write the mode registers before hardware begins - the retry. After software is done with its operations, it will clear the alert interrupt register bit - 0: Hardware can begin - the retry right away after the dfi_alert_n pulse goes away. The value on this register is valid only when retry is enabled (P - RCTRL.crc_parity_retry_enable = 1) If this register is set to 1 and if the software doesn't clear the interrupt register afte - handling the parity/CRC error, then the hardware will not begin the retry process and the system will hang. In the case of P - rity/CRC error, there are two possibilities when the software doesn't reset MR5[4] to 0. - (i) If 'Persistent parity' mode re - ister bit is NOT set: the commands sent during retry and normal operation are executed without parity checking. The value in - he Parity error log register MPR Page 1 is valid. - (ii) If 'Persistent parity' mode register bit is SET: Parity checking is - one for commands sent during retry and normal operation. If multiple errors occur before MR5[4] is cleared, the error log in - PR Page 1 should be treated as 'Don't care'. - PSU_DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW 0x1 - - - 1: Enable command retry mechanism in case of C/A Parity or CRC error - 0: Disable command retry mechanism when C/A Parity o - CRC features are enabled. Note that retry functionality is not supported if burst chop is enabled (MSTR.burstchop = 1) and/o - disable auto-refresh is enabled (RFSHCTL3.dis_auto_refresh = 1) - PSU_DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE 0x0 - - CRC Calculation setting register - 1: CRC includes DM signal - 0: CRC not includes DM signal Present only in designs configur - d to support DDR4. - PSU_DDRC_CRCPARCTL1_CRC_INC_DM 0x0 - - CRC enable Register - 1: Enable generation of CRC - 0: Disable generation of CRC The setting of this register should match th - CRC mode register setting in the DRAM. - PSU_DDRC_CRCPARCTL1_CRC_ENABLE 0x0 - - C/A Parity enable register - 1: Enable generation of C/A parity and detection of C/A parity error - 0: Disable generation of - /A parity and disable detection of C/A parity error If RCD's parity error detection or SDRAM's parity detection is enabled, t - is register should be 1. - PSU_DDRC_CRCPARCTL1_PARITY_ENABLE 0x0 - - CRC Parity Control Register1 - (OFFSET, MASK, VALUE) (0XFD0700C4, 0x3F000391U ,0x10000200U) - RegMask = (DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_MASK | DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_MASK | DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_MASK | DDRC_CRCPARCTL1_CRC_INC_DM_MASK | DDRC_CRCPARCTL1_CRC_ENABLE_MASK | DDRC_CRCPARCTL1_PARITY_ENABLE_MASK | 0 ); - - RegVal = ((0x00000010U << DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_SHIFT - | 0x00000001U << DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_SHIFT - | 0x00000000U << DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_SHIFT - | 0x00000000U << DDRC_CRCPARCTL1_CRC_INC_DM_SHIFT - | 0x00000000U << DDRC_CRCPARCTL1_CRC_ENABLE_SHIFT - | 0x00000000U << DDRC_CRCPARCTL1_PARITY_ENABLE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_CRCPARCTL1_OFFSET ,0x3F000391U ,0x10000200U); - /*############################################################################################################################ */ - - /*Register : CRCPARCTL2 @ 0XFD0700C8

- - Value from the DRAM spec indicating the maximum width of the dfi_alert_n pulse when a parity error occurs. Recommended values - - tPAR_ALERT_PW.MAX For configurations with MEMC_FREQ_RATIO=2, program this to tPAR_ALERT_PW.MAX/2 and round up to next inte - er value. Values of 0, 1 and 2 are illegal. This value must be greater than CRCPARCTL2.t_crc_alert_pw_max. - PSU_DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX 0x40 - - Value from the DRAM spec indicating the maximum width of the dfi_alert_n pulse when a CRC error occurs. Recommended values: - - tCRC_ALERT_PW.MAX For configurations with MEMC_FREQ_RATIO=2, program this to tCRC_ALERT_PW.MAX/2 and round up to next integer - value. Values of 0, 1 and 2 are illegal. This value must be less than CRCPARCTL2.t_par_alert_pw_max. - PSU_DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX 0x5 - - Indicates the maximum duration in number of DRAM clock cycles for which a command should be held in the Command Retry FIFO be - ore it is popped out. Every location in the Command Retry FIFO has an associated down counting timer that will use this regis - er as the start value. The down counting starts when a command is loaded into the FIFO. The timer counts down every 4 DRAM cy - les. When the counter reaches zero, the entry is popped from the FIFO. All the counters are frozen, if a C/A Parity or CRC er - or occurs before the counter reaches zero. The counter is reset to 0, after all the commands in the FIFO are retried. Recomme - ded(minimum) values: - Only C/A Parity is enabled. RoundUp((PHY Command Latency(DRAM CLK) + CAL + RDIMM delay + tPAR_ALERT_ON - max + tPAR_UNKNOWN + PHY Alert Latency(DRAM CLK) + board delay) / 4) + 2 - Both C/A Parity and CRC is enabled/ Only CRC is en - bled. RoundUp((PHY Command Latency(DRAM CLK) + CAL + RDIMM delay + WL + 5(BL10)+ tCRC_ALERT.max + PHY Alert Latency(DRAM CLK) - + board delay) / 4) + 2 Note 1: All value (e.g. tPAR_ALERT_ON) should be in terms of DRAM Clock and round up Note 2: Board de - ay(Command/Alert_n) should be considered. Note 3: Use the worst case(longer) value for PHY Latencies/Board delay Note 4: The - ecommended values are minimum value to be set. For mode detail, See 'Calculation of FIFO Depth' section. Max value can be set - to this register is defined below: - MEMC_BURST_LENGTH == 16 Full bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH- - Full bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Half bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_D - PTH-4 Half bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-6 Quarter bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CM - _FIFO_DEPTH-8 Quarter bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-12 - MEMC_BURST_LENGTH != 16 Full bus Mode (C - C=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-1 Full bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mo - e (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Quarte - bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-4 Quarter bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEP - H-6 Values of 0, 1 and 2 are illegal. - PSU_DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4 0x1f - - CRC Parity Control Register2 - (OFFSET, MASK, VALUE) (0XFD0700C8, 0x01FF1F3FU ,0x0040051FU) - RegMask = (DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_MASK | DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_MASK | DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_MASK | 0 ); - - RegVal = ((0x00000040U << DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_SHIFT - | 0x00000005U << DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_SHIFT - | 0x0000001FU << DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_CRCPARCTL2_OFFSET ,0x01FF1F3FU ,0x0040051FU); - /*############################################################################################################################ */ - - /*Register : INIT0 @ 0XFD0700D0

- - If lower bit is enabled the SDRAM initialization routine is skipped. The upper bit decides what state the controller starts u - in when reset is removed - 00 - SDRAM Intialization routine is run after power-up - 01 - SDRAM Intialization routine is skip - ed after power-up. Controller starts up in Normal Mode - 11 - SDRAM Intialization routine is skipped after power-up. Controll - r starts up in Self-refresh Mode - 10 - SDRAM Intialization routine is run after power-up. Note: The only 2'b00 is supported - or LPDDR4 in this version of the uMCTL2. - PSU_DDRC_INIT0_SKIP_DRAM_INIT 0x0 - - Cycles to wait after driving CKE high to start the SDRAM initialization sequence. Unit: 1024 clocks. DDR2 typically requires - 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2/LPDDR3 typically requires this to be pr - grammed for a delay of 200 us. LPDDR4 typically requires this to be programmed for a delay of 2 us. For configurations with M - MC_FREQ_RATIO=2, program this to JEDEC spec value divided by 2, and round it up to next integer value. - PSU_DDRC_INIT0_POST_CKE_X1024 0x2 - - Cycles to wait after reset before driving CKE high to start the SDRAM initialization sequence. Unit: 1024 clock cycles. DDR2 - pecifications typically require this to be programmed for a delay of >= 200 us. LPDDR2/LPDDR3: tINIT1 of 100 ns (min) LPDDR4: - tINIT3 of 2 ms (min) For configurations with MEMC_FREQ_RATIO=2, program this to JEDEC spec value divided by 2, and round it u - to next integer value. - PSU_DDRC_INIT0_PRE_CKE_X1024 0x106 - - SDRAM Initialization Register 0 - (OFFSET, MASK, VALUE) (0XFD0700D0, 0xC3FF0FFFU ,0x00020106U) - RegMask = (DDRC_INIT0_SKIP_DRAM_INIT_MASK | DDRC_INIT0_POST_CKE_X1024_MASK | DDRC_INIT0_PRE_CKE_X1024_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_INIT0_SKIP_DRAM_INIT_SHIFT - | 0x00000002U << DDRC_INIT0_POST_CKE_X1024_SHIFT - | 0x00000106U << DDRC_INIT0_PRE_CKE_X1024_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_INIT0_OFFSET ,0xC3FF0FFFU ,0x00020106U); - /*############################################################################################################################ */ - - /*Register : INIT1 @ 0XFD0700D4

- - Number of cycles to assert SDRAM reset signal during init sequence. This is only present for designs supporting DDR3, DDR4 or - LPDDR4 devices. For use with a DDR PHY, this should be set to a minimum of 1 - PSU_DDRC_INIT1_DRAM_RSTN_X1024 0x2 - - Cycles to wait after completing the SDRAM initialization sequence before starting the dynamic scheduler. Unit: Counts of a gl - bal timer that pulses every 32 clock cycles. There is no known specific requirement for this; it may be set to zero. - PSU_DDRC_INIT1_FINAL_WAIT_X32 0x0 - - Wait period before driving the OCD complete command to SDRAM. Unit: Counts of a global timer that pulses every 32 clock cycle - . There is no known specific requirement for this; it may be set to zero. - PSU_DDRC_INIT1_PRE_OCD_X32 0x0 - - SDRAM Initialization Register 1 - (OFFSET, MASK, VALUE) (0XFD0700D4, 0x01FF7F0FU ,0x00020000U) - RegMask = (DDRC_INIT1_DRAM_RSTN_X1024_MASK | DDRC_INIT1_FINAL_WAIT_X32_MASK | DDRC_INIT1_PRE_OCD_X32_MASK | 0 ); - - RegVal = ((0x00000002U << DDRC_INIT1_DRAM_RSTN_X1024_SHIFT - | 0x00000000U << DDRC_INIT1_FINAL_WAIT_X32_SHIFT - | 0x00000000U << DDRC_INIT1_PRE_OCD_X32_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_INIT1_OFFSET ,0x01FF7F0FU ,0x00020000U); - /*############################################################################################################################ */ - - /*Register : INIT2 @ 0XFD0700D8

- - Idle time after the reset command, tINIT4. Present only in designs configured to support LPDDR2. Unit: 32 clock cycles. - PSU_DDRC_INIT2_IDLE_AFTER_RESET_X32 0x23 - - Time to wait after the first CKE high, tINIT2. Present only in designs configured to support LPDDR2/LPDDR3. Unit: 1 clock cyc - e. LPDDR2/LPDDR3 typically requires 5 x tCK delay. - PSU_DDRC_INIT2_MIN_STABLE_CLOCK_X1 0x5 - - SDRAM Initialization Register 2 - (OFFSET, MASK, VALUE) (0XFD0700D8, 0x0000FF0FU ,0x00002305U) - RegMask = (DDRC_INIT2_IDLE_AFTER_RESET_X32_MASK | DDRC_INIT2_MIN_STABLE_CLOCK_X1_MASK | 0 ); - - RegVal = ((0x00000023U << DDRC_INIT2_IDLE_AFTER_RESET_X32_SHIFT - | 0x00000005U << DDRC_INIT2_MIN_STABLE_CLOCK_X1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_INIT2_OFFSET ,0x0000FF0FU ,0x00002305U); - /*############################################################################################################################ */ - - /*Register : INIT3 @ 0XFD0700DC

- - DDR2: Value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The uMCTL2 sets this bit appropriately - DDR3/DDR4: Value loaded into MR0 register. mDDR: Value to write to MR register. LPDDR2/LPDDR3/LPDDR4 - Value to write to MR1 - register - PSU_DDRC_INIT3_MR 0x930 - - DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setting in this register is ignored. The uMCTL2 sets those - bits appropriately. DDR3/DDR4: Value to write to MR1 register Set bit 7 to 0. If PHY-evaluation mode training is enabled, thi - bit is set appropriately by the uMCTL2 during write leveling. mDDR: Value to write to EMR register. LPDDR2/LPDDR3/LPDDR4 - V - lue to write to MR2 register - PSU_DDRC_INIT3_EMR 0x301 - - SDRAM Initialization Register 3 - (OFFSET, MASK, VALUE) (0XFD0700DC, 0xFFFFFFFFU ,0x09300301U) - RegMask = (DDRC_INIT3_MR_MASK | DDRC_INIT3_EMR_MASK | 0 ); - - RegVal = ((0x00000930U << DDRC_INIT3_MR_SHIFT - | 0x00000301U << DDRC_INIT3_EMR_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_INIT3_OFFSET ,0xFFFFFFFFU ,0x09300301U); - /*############################################################################################################################ */ - - /*Register : INIT4 @ 0XFD0700E0

- - DDR2: Value to write to EMR2 register. DDR3/DDR4: Value to write to MR2 register LPDDR2/LPDDR3/LPDDR4: Value to write to MR3 - egister mDDR: Unused - PSU_DDRC_INIT4_EMR2 0x20 - - DDR2: Value to write to EMR3 register. DDR3/DDR4: Value to write to MR3 register mDDR/LPDDR2/LPDDR3: Unused LPDDR4: Value to - rite to MR13 register - PSU_DDRC_INIT4_EMR3 0x200 - - SDRAM Initialization Register 4 - (OFFSET, MASK, VALUE) (0XFD0700E0, 0xFFFFFFFFU ,0x00200200U) - RegMask = (DDRC_INIT4_EMR2_MASK | DDRC_INIT4_EMR3_MASK | 0 ); - - RegVal = ((0x00000020U << DDRC_INIT4_EMR2_SHIFT - | 0x00000200U << DDRC_INIT4_EMR3_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_INIT4_OFFSET ,0xFFFFFFFFU ,0x00200200U); - /*############################################################################################################################ */ - - /*Register : INIT5 @ 0XFD0700E4

- - ZQ initial calibration, tZQINIT. Present only in designs configured to support DDR3 or DDR4 or LPDDR2/LPDDR3. Unit: 32 clock - ycles. DDR3 typically requires 512 clocks. DDR4 requires 1024 clocks. LPDDR2/LPDDR3 requires 1 us. - PSU_DDRC_INIT5_DEV_ZQINIT_X32 0x21 - - Maximum duration of the auto initialization, tINIT5. Present only in designs configured to support LPDDR2/LPDDR3. LPDDR2/LPDD - 3 typically requires 10 us. - PSU_DDRC_INIT5_MAX_AUTO_INIT_X1024 0x4 - - SDRAM Initialization Register 5 - (OFFSET, MASK, VALUE) (0XFD0700E4, 0x00FF03FFU ,0x00210004U) - RegMask = (DDRC_INIT5_DEV_ZQINIT_X32_MASK | DDRC_INIT5_MAX_AUTO_INIT_X1024_MASK | 0 ); - - RegVal = ((0x00000021U << DDRC_INIT5_DEV_ZQINIT_X32_SHIFT - | 0x00000004U << DDRC_INIT5_MAX_AUTO_INIT_X1024_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_INIT5_OFFSET ,0x00FF03FFU ,0x00210004U); - /*############################################################################################################################ */ - - /*Register : INIT6 @ 0XFD0700E8

- - DDR4- Value to be loaded into SDRAM MR4 registers. Used in DDR4 designs only. - PSU_DDRC_INIT6_MR4 0x0 - - DDR4- Value to be loaded into SDRAM MR5 registers. Used in DDR4 designs only. - PSU_DDRC_INIT6_MR5 0x6c0 - - SDRAM Initialization Register 6 - (OFFSET, MASK, VALUE) (0XFD0700E8, 0xFFFFFFFFU ,0x000006C0U) - RegMask = (DDRC_INIT6_MR4_MASK | DDRC_INIT6_MR5_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_INIT6_MR4_SHIFT - | 0x000006C0U << DDRC_INIT6_MR5_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_INIT6_OFFSET ,0xFFFFFFFFU ,0x000006C0U); - /*############################################################################################################################ */ - - /*Register : INIT7 @ 0XFD0700EC

- - DDR4- Value to be loaded into SDRAM MR6 registers. Used in DDR4 designs only. - PSU_DDRC_INIT7_MR6 0x819 - - SDRAM Initialization Register 7 - (OFFSET, MASK, VALUE) (0XFD0700EC, 0xFFFF0000U ,0x08190000U) - RegMask = (DDRC_INIT7_MR6_MASK | 0 ); - - RegVal = ((0x00000819U << DDRC_INIT7_MR6_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_INIT7_OFFSET ,0xFFFF0000U ,0x08190000U); - /*############################################################################################################################ */ - - /*Register : DIMMCTL @ 0XFD0700F0

- - Disabling Address Mirroring for BG bits. When this is set to 1, BG0 and BG1 are NOT swapped even if Address Mirroring is enab - ed. This will be required for DDR4 DIMMs with x16 devices. - 1 - BG0 and BG1 are NOT swapped. - 0 - BG0 and BG1 are swapped i - address mirroring is enabled. - PSU_DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING 0x0 - - Enable for BG1 bit of MRS command. BG1 bit of the mode register address is specified as RFU (Reserved for Future Use) and mus - be programmed to 0 during MRS. In case where DRAMs which do not have BG1 are attached and both the CA parity and the Output - nversion are enabled, this must be set to 0, so that the calculation of CA parity will not include BG1 bit. Note: This has no - effect on the address of any other memory accesses, or of software-driven mode register accesses. If address mirroring is ena - led, this is applied to BG1 of even ranks and BG0 of odd ranks. - 1 - Enabled - 0 - Disabled - PSU_DDRC_DIMMCTL_MRS_BG1_EN 0x1 - - Enable for A17 bit of MRS command. A17 bit of the mode register address is specified as RFU (Reserved for Future Use) and mus - be programmed to 0 during MRS. In case where DRAMs which do not have A17 are attached and the Output Inversion are enabled, - his must be set to 0, so that the calculation of CA parity will not include A17 bit. Note: This has no effect on the address - f any other memory accesses, or of software-driven mode register accesses. - 1 - Enabled - 0 - Disabled - PSU_DDRC_DIMMCTL_MRS_A17_EN 0x0 - - Output Inversion Enable (for DDR4 RDIMM implementations only). DDR4 RDIMM implements the Output Inversion feature by default, - which means that the following address, bank address and bank group bits of B-side DRAMs are inverted: A3-A9, A11, A13, A17, - A0-BA1, BG0-BG1. Setting this bit ensures that, for mode register accesses generated by the uMCTL2 during the automatic initi - lization routine and enabling of a particular DDR4 feature, separate A-side and B-side mode register accesses are generated. - or B-side mode register accesses, these bits are inverted within the uMCTL2 to compensate for this RDIMM inversion. Note: Thi - has no effect on the address of any other memory accesses, or of software-driven mode register accesses. - 1 - Implement out - ut inversion for B-side DRAMs. - 0 - Do not implement output inversion for B-side DRAMs. - PSU_DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN 0x0 - - Address Mirroring Enable (for multi-rank UDIMM implementations and multi-rank DDR4 RDIMM implementations). Some UDIMMs and DD - 4 RDIMMs implement address mirroring for odd ranks, which means that the following address, bank address and bank group bits - re swapped: (A3, A4), (A5, A6), (A7, A8), (BA0, BA1) and also (A11, A13), (BG0, BG1) for the DDR4. Setting this bit ensures t - at, for mode register accesses during the automatic initialization routine, these bits are swapped within the uMCTL2 to compe - sate for this UDIMM/RDIMM swapping. In addition to the automatic initialization routine, in case of DDR4 UDIMM/RDIMM, they ar - swapped during the automatic MRS access to enable/disable of a particular DDR4 feature. Note: This has no effect on the addr - ss of any other memory accesses, or of software-driven mode register accesses. This is not supported for mDDR, LPDDR2, LPDDR3 - or LPDDR4 SDRAMs. Note: In case of x16 DDR4 DIMMs, BG1 output of MRS for the odd ranks is same as BG0 because BG1 is invalid, - hence dimm_dis_bg_mirroring register must be set to 1. - 1 - For odd ranks, implement address mirroring for MRS commands to d - ring initialization and for any automatic DDR4 MRS commands (to be used if UDIMM/RDIMM implements address mirroring) - 0 - Do - not implement address mirroring - PSU_DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN 0x0 - - Staggering enable for multi-rank accesses (for multi-rank UDIMM and RDIMM implementations only). This is not supported for mD - R, LPDDR2, LPDDR3 or LPDDR4 SDRAMs. Note: Even if this bit is set it does not take care of software driven MR commands (via M - CTRL0/MRCTRL1), where software is responsible to send them to seperate ranks as appropriate. - 1 - (DDR4) Send MRS commands t - each ranks seperately - 1 - (non-DDR4) Send all commands to even and odd ranks seperately - 0 - Do not stagger accesses - PSU_DDRC_DIMMCTL_DIMM_STAGGER_CS_EN 0x0 - - DIMM Control Register - (OFFSET, MASK, VALUE) (0XFD0700F0, 0x0000003FU ,0x00000010U) - RegMask = (DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_MASK | DDRC_DIMMCTL_MRS_BG1_EN_MASK | DDRC_DIMMCTL_MRS_A17_EN_MASK | DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_MASK | DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_MASK | DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_SHIFT - | 0x00000001U << DDRC_DIMMCTL_MRS_BG1_EN_SHIFT - | 0x00000000U << DDRC_DIMMCTL_MRS_A17_EN_SHIFT - | 0x00000000U << DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_SHIFT - | 0x00000000U << DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_SHIFT - | 0x00000000U << DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DIMMCTL_OFFSET ,0x0000003FU ,0x00000010U); - /*############################################################################################################################ */ - - /*Register : RANKCTL @ 0XFD0700F4

- - Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecuti - e writes to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This value should c - nsider both PHY requirement and ODT requirement. - PHY requirement: tphy_wrcsgap + 1 (see PHY databook for value of tphy_wrcs - ap) If CRC feature is enabled, should be increased by 1. If write preamble is set to 2tCK(DDR4/LPDDR4 only), should be increa - ed by 1. If write postamble is set to 1.5tCK(LPDDR4 only), should be increased by 1. - ODT requirement: The value programmed - n this register takes care of the ODT switch off timing requirement when switching ranks during writes. For LPDDR4, the requi - ement is ODTLoff - ODTLon - BL/2 + 1 For configurations with MEMC_FREQ_RATIO=1, program this to the larger of PHY requirement - or ODT requirement. For configurations with MEMC_FREQ_RATIO=2, program this to the larger value divided by two and round it u - to the next integer. - PSU_DDRC_RANKCTL_DIFF_RANK_WR_GAP 0x6 - - Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecuti - e reads to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This value should co - sider both PHY requirement and ODT requirement. - PHY requirement: tphy_rdcsgap + 1 (see PHY databook for value of tphy_rdcsg - p) If read preamble is set to 2tCK(DDR4/LPDDR4 only), should be increased by 1. If read postamble is set to 1.5tCK(LPDDR4 onl - ), should be increased by 1. - ODT requirement: The value programmed in this register takes care of the ODT switch off timing - requirement when switching ranks during reads. For configurations with MEMC_FREQ_RATIO=1, program this to the larger of PHY r - quirement or ODT requirement. For configurations with MEMC_FREQ_RATIO=2, program this to the larger value divided by two and - ound it up to the next integer. - PSU_DDRC_RANKCTL_DIFF_RANK_RD_GAP 0x6 - - Only present for multi-rank configurations. Background: Reads to the same rank can be performed back-to-back. Reads to differ - nt ranks require additional gap dictated by the register RANKCTL.diff_rank_rd_gap. This is to avoid possible data bus content - on as well as to give PHY enough time to switch the delay when changing ranks. The uMCTL2 arbitrates for bus access on a cycl - -by-cycle basis; therefore after a read is scheduled, there are few clock cycles (determined by the value on RANKCTL.diff_ran - _rd_gap register) in which only reads from the same rank are eligible to be scheduled. This prevents reads from other ranks f - om having fair access to the data bus. This parameter represents the maximum number of reads that can be scheduled consecutiv - ly to the same rank. After this number is reached, a delay equal to RANKCTL.diff_rank_rd_gap is inserted by the scheduler to - llow all ranks a fair opportunity to be scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fair - ess. This feature can be DISABLED by setting this register to 0. When set to 0, the Controller will stay on the same rank as - ong as commands are available for it. Minimum programmable value is 0 (feature disabled) and maximum programmable value is 0x - . FOR PERFORMANCE ONLY. - PSU_DDRC_RANKCTL_MAX_RANK_RD 0xf - - Rank Control Register - (OFFSET, MASK, VALUE) (0XFD0700F4, 0x00000FFFU ,0x0000066FU) - RegMask = (DDRC_RANKCTL_DIFF_RANK_WR_GAP_MASK | DDRC_RANKCTL_DIFF_RANK_RD_GAP_MASK | DDRC_RANKCTL_MAX_RANK_RD_MASK | 0 ); - - RegVal = ((0x00000006U << DDRC_RANKCTL_DIFF_RANK_WR_GAP_SHIFT - | 0x00000006U << DDRC_RANKCTL_DIFF_RANK_RD_GAP_SHIFT - | 0x0000000FU << DDRC_RANKCTL_MAX_RANK_RD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_RANKCTL_OFFSET ,0x00000FFFU ,0x0000066FU); - /*############################################################################################################################ */ - - /*Register : DRAMTMG0 @ 0XFD070100

- - Minimum time between write and precharge to same bank. Unit: Clocks Specifications: WL + BL/2 + tWR = approximately 8 cycles - 15 ns = 14 clocks @400MHz and less for lower frequencies where: - WL = write latency - BL = burst length. This must match th - value programmed in the BL bit of the mode register to the SDRAM. BST (burst terminate) is not supported at present. - tWR = - Write recovery time. This comes directly from the SDRAM specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 for this - arameter. For configurations with MEMC_FREQ_RATIO=2, 1T mode, divide the above value by 2. No rounding up. For configurations - with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, divide the above value by 2 and round it up to the next integer value. - PSU_DDRC_DRAMTMG0_WR2PRE 0x11 - - tFAW Valid only when 8 or more banks(or banks x bank groups) are present. In 8-bank design, at most 4 banks must be activated - in a rolling window of tFAW cycles. For configurations with MEMC_FREQ_RATIO=2, program this to (tFAW/2) and round up to next - nteger value. In a 4-bank design, set this register to 0x1 independent of the MEMC_FREQ_RATIO configuration. Unit: Clocks - PSU_DDRC_DRAMTMG0_T_FAW 0xc - - tRAS(max): Maximum time between activate and precharge to same bank. This is the maximum time that a page can be kept open Mi - imum value of this register is 1. Zero is invalid. For configurations with MEMC_FREQ_RATIO=2, program this to (tRAS(max)-1)/2 - No rounding up. Unit: Multiples of 1024 clocks. - PSU_DDRC_DRAMTMG0_T_RAS_MAX 0x24 - - tRAS(min): Minimum time between activate and precharge to the same bank. For configurations with MEMC_FREQ_RATIO=2, 1T mode, - rogram this to tRAS(min)/2. No rounding up. For configurations with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, program this t - (tRAS(min)/2) and round it up to the next integer value. Unit: Clocks - PSU_DDRC_DRAMTMG0_T_RAS_MIN 0x12 - - SDRAM Timing Register 0 - (OFFSET, MASK, VALUE) (0XFD070100, 0x7F3F7F3FU ,0x110C2412U) - RegMask = (DDRC_DRAMTMG0_WR2PRE_MASK | DDRC_DRAMTMG0_T_FAW_MASK | DDRC_DRAMTMG0_T_RAS_MAX_MASK | DDRC_DRAMTMG0_T_RAS_MIN_MASK | 0 ); - - RegVal = ((0x00000011U << DDRC_DRAMTMG0_WR2PRE_SHIFT - | 0x0000000CU << DDRC_DRAMTMG0_T_FAW_SHIFT - | 0x00000024U << DDRC_DRAMTMG0_T_RAS_MAX_SHIFT - | 0x00000012U << DDRC_DRAMTMG0_T_RAS_MIN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DRAMTMG0_OFFSET ,0x7F3F7F3FU ,0x110C2412U); - /*############################################################################################################################ */ - - /*Register : DRAMTMG1 @ 0XFD070104

- - tXP: Minimum time after power-down exit to any operation. For DDR3, this should be programmed to tXPDLL if slow powerdown exi - is selected in MR0[12]. If C/A parity for DDR4 is used, set to (tXP+PL) instead. For configurations with MEMC_FREQ_RATIO=2, - rogram this to (tXP/2) and round it up to the next integer value. Units: Clocks - PSU_DDRC_DRAMTMG1_T_XP 0x4 - - tRTP: Minimum time from read to precharge of same bank. - DDR2: tAL + BL/2 + max(tRTP, 2) - 2 - DDR3: tAL + max (tRTP, 4) - D - R4: Max of following two equations: tAL + max (tRTP, 4) or, RL + BL/2 - tRP. - mDDR: BL/2 - LPDDR2: Depends on if it's LPDDR2 - S2 or LPDDR2-S4: LPDDR2-S2: BL/2 + tRTP - 1. LPDDR2-S4: BL/2 + max(tRTP,2) - 2. - LPDDR3: BL/2 + max(tRTP,4) - 4 - LPDDR4: BL - 2 + max(tRTP,8) - 8 For configurations with MEMC_FREQ_RATIO=2, 1T mode, divide the above value by 2. No rounding up. For conf - gurations with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, divide the above value by 2 and round it up to the next integer val - e. Unit: Clocks. - PSU_DDRC_DRAMTMG1_RD2PRE 0x4 - - tRC: Minimum time between activates to same bank. For configurations with MEMC_FREQ_RATIO=2, program this to (tRC/2) and roun - up to next integer value. Unit: Clocks. - PSU_DDRC_DRAMTMG1_T_RC 0x19 - - SDRAM Timing Register 1 - (OFFSET, MASK, VALUE) (0XFD070104, 0x001F1F7FU ,0x00040419U) - RegMask = (DDRC_DRAMTMG1_T_XP_MASK | DDRC_DRAMTMG1_RD2PRE_MASK | DDRC_DRAMTMG1_T_RC_MASK | 0 ); - - RegVal = ((0x00000004U << DDRC_DRAMTMG1_T_XP_SHIFT - | 0x00000004U << DDRC_DRAMTMG1_RD2PRE_SHIFT - | 0x00000019U << DDRC_DRAMTMG1_T_RC_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DRAMTMG1_OFFSET ,0x001F1F7FU ,0x00040419U); - /*############################################################################################################################ */ - - /*Register : DRAMTMG2 @ 0XFD070108

- - Set to WL Time from write command to write data on SDRAM interface. This must be set to WL. For mDDR, it should normally be s - t to 1. Note that, depending on the PHY, if using RDIMM, it may be necessary to use a value of WL + 1 to compensate for the e - tra cycle of latency through the RDIMM For configurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above - equation by 2, and round it up to next integer. This register field is not required for DDR2 and DDR3 (except if MEMC_TRAININ - is set), as the DFI read and write latencies defined in DFITMG0 and DFITMG1 are sufficient for those protocols Unit: clocks - PSU_DDRC_DRAMTMG2_WRITE_LATENCY 0x7 - - Set to RL Time from read command to read data on SDRAM interface. This must be set to RL. Note that, depending on the PHY, if - using RDIMM, it mat be necessary to use a value of RL + 1 to compensate for the extra cycle of latency through the RDIMM For - onfigurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next inte - er. This register field is not required for DDR2 and DDR3 (except if MEMC_TRAINING is set), as the DFI read and write latenci - s defined in DFITMG0 and DFITMG1 are sufficient for those protocols Unit: clocks - PSU_DDRC_DRAMTMG2_READ_LATENCY 0x8 - - DDR2/3/mDDR: RL + BL/2 + 2 - WL DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL LPDDR2/LPDDR3: RL + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL - PDDR4(DQ ODT is Disabled): RL + BL/2 + RU(tDQSCKmax/tCK) + WR_PREAMBLE + RD_POSTAMBLE - WL LPDDR4(DQ ODT is Enabled) : RL + B - /2 + RU(tDQSCKmax/tCK) + RD_POSTAMBLE - ODTLon - RU(tODTon(min)/tCK) Minimum time from read command to write command. Include - time for bus turnaround and all per-bank, per-rank, and global constraints. Unit: Clocks. Where: - WL = write latency - BL = - urst length. This must match the value programmed in the BL bit of the mode register to the SDRAM - RL = read latency = CAS l - tency - WR_PREAMBLE = write preamble. This is unique to DDR4 and LPDDR4. - RD_POSTAMBLE = read postamble. This is unique to L - DDR4. For LPDDR2/LPDDR3/LPDDR4, if derating is enabled (DERATEEN.derate_enable=1), derated tDQSCKmax should be used. For conf - gurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next integer. - PSU_DDRC_DRAMTMG2_RD2WR 0x6 - - DDR4: CWL + PL + BL/2 + tWTR_L Others: CWL + BL/2 + tWTR In DDR4, minimum time from write command to read command for same ba - k group. In others, minimum time from write command to read command. Includes time for bus turnaround, recovery times, and al - per-bank, per-rank, and global constraints. Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity latency - BL = burs - length. This must match the value programmed in the BL bit of the mode register to the SDRAM - tWTR_L = internal write to re - d command delay for same bank group. This comes directly from the SDRAM specification. - tWTR = internal write to read comman - delay. This comes directly from the SDRAM specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 operation. For configu - ations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next integer. - PSU_DDRC_DRAMTMG2_WR2RD 0xe - - SDRAM Timing Register 2 - (OFFSET, MASK, VALUE) (0XFD070108, 0x3F3F3F3FU ,0x0708060EU) - RegMask = (DDRC_DRAMTMG2_WRITE_LATENCY_MASK | DDRC_DRAMTMG2_READ_LATENCY_MASK | DDRC_DRAMTMG2_RD2WR_MASK | DDRC_DRAMTMG2_WR2RD_MASK | 0 ); - - RegVal = ((0x00000007U << DDRC_DRAMTMG2_WRITE_LATENCY_SHIFT - | 0x00000008U << DDRC_DRAMTMG2_READ_LATENCY_SHIFT - | 0x00000006U << DDRC_DRAMTMG2_RD2WR_SHIFT - | 0x0000000EU << DDRC_DRAMTMG2_WR2RD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DRAMTMG2_OFFSET ,0x3F3F3F3FU ,0x0708060EU); - /*############################################################################################################################ */ - - /*Register : DRAMTMG3 @ 0XFD07010C

- - Time to wait after a mode register write or read (MRW or MRR). Present only in designs configured to support LPDDR2, LPDDR3 o - LPDDR4. LPDDR2 typically requires value of 5. LPDDR3 typically requires value of 10. LPDDR4: Set this to the larger of tMRW - nd tMRWCKEL. For LPDDR2, this register is used for the time from a MRW/MRR to all other commands. For LDPDR3, this register i - used for the time from a MRW/MRR to a MRW/MRR. - PSU_DDRC_DRAMTMG3_T_MRW 0x5 - - tMRD: Cycles to wait after a mode register write or read. Depending on the connected SDRAM, tMRD represents: DDR2/mDDR: Time - rom MRS to any command DDR3/4: Time from MRS to MRS command LPDDR2: not used LPDDR3/4: Time from MRS to non-MRS command For c - nfigurations with MEMC_FREQ_RATIO=2, program this to (tMRD/2) and round it up to the next integer value. If C/A parity for DD - 4 is used, set to tMRD_PAR(tMOD+PL) instead. - PSU_DDRC_DRAMTMG3_T_MRD 0x4 - - tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode command and following non-load mode command. If C/A pari - y for DDR4 is used, set to tMOD_PAR(tMOD+PL) instead. Set to tMOD if MEMC_FREQ_RATIO=1, or tMOD/2 (rounded up to next integer - if MEMC_FREQ_RATIO=2. Note that if using RDIMM, depending on the PHY, it may be necessary to use a value of tMOD + 1 or (tMO - + 1)/2 to compensate for the extra cycle of latency applied to mode register writes by the RDIMM chip. - PSU_DDRC_DRAMTMG3_T_MOD 0xc - - SDRAM Timing Register 3 - (OFFSET, MASK, VALUE) (0XFD07010C, 0x3FF3F3FFU ,0x0050400CU) - RegMask = (DDRC_DRAMTMG3_T_MRW_MASK | DDRC_DRAMTMG3_T_MRD_MASK | DDRC_DRAMTMG3_T_MOD_MASK | 0 ); - - RegVal = ((0x00000005U << DDRC_DRAMTMG3_T_MRW_SHIFT - | 0x00000004U << DDRC_DRAMTMG3_T_MRD_SHIFT - | 0x0000000CU << DDRC_DRAMTMG3_T_MOD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DRAMTMG3_OFFSET ,0x3FF3F3FFU ,0x0050400CU); - /*############################################################################################################################ */ - - /*Register : DRAMTMG4 @ 0XFD070110

- - tRCD - tAL: Minimum time from activate to read or write command to same bank. For configurations with MEMC_FREQ_RATIO=2, prog - am this to ((tRCD - tAL)/2) and round it up to the next integer value. Minimum value allowed for this register is 1, which im - lies minimum (tRCD - tAL) value to be 2 in configurations with MEMC_FREQ_RATIO=2. Unit: Clocks. - PSU_DDRC_DRAMTMG4_T_RCD 0x8 - - DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank group. Others: tCCD: This is the minimum - time between two reads or two writes. For configurations with MEMC_FREQ_RATIO=2, program this to (tCCD_L/2 or tCCD/2) and rou - d it up to the next integer value. Unit: clocks. - PSU_DDRC_DRAMTMG4_T_CCD 0x3 - - DDR4: tRRD_L: Minimum time between activates from bank 'a' to bank 'b' for same bank group. Others: tRRD: Minimum time betwee - activates from bank 'a' to bank 'b'For configurations with MEMC_FREQ_RATIO=2, program this to (tRRD_L/2 or tRRD/2) and round - it up to the next integer value. Unit: Clocks. - PSU_DDRC_DRAMTMG4_T_RRD 0x3 - - tRP: Minimum time from precharge to activate of same bank. For MEMC_FREQ_RATIO=1 configurations, t_rp should be set to RoundU - (tRP/tCK). For MEMC_FREQ_RATIO=2 configurations, t_rp should be set to RoundDown(RoundUp(tRP/tCK)/2) + 1. For MEMC_FREQ_RATIO - 2 configurations in LPDDR4, t_rp should be set to RoundUp(RoundUp(tRP/tCK)/2). Unit: Clocks. - PSU_DDRC_DRAMTMG4_T_RP 0x9 - - SDRAM Timing Register 4 - (OFFSET, MASK, VALUE) (0XFD070110, 0x1F0F0F1FU ,0x08030309U) - RegMask = (DDRC_DRAMTMG4_T_RCD_MASK | DDRC_DRAMTMG4_T_CCD_MASK | DDRC_DRAMTMG4_T_RRD_MASK | DDRC_DRAMTMG4_T_RP_MASK | 0 ); - - RegVal = ((0x00000008U << DDRC_DRAMTMG4_T_RCD_SHIFT - | 0x00000003U << DDRC_DRAMTMG4_T_CCD_SHIFT - | 0x00000003U << DDRC_DRAMTMG4_T_RRD_SHIFT - | 0x00000009U << DDRC_DRAMTMG4_T_RP_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DRAMTMG4_OFFSET ,0x1F0F0F1FU ,0x08030309U); - /*############################################################################################################################ */ - - /*Register : DRAMTMG5 @ 0XFD070114

- - This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stab - e time before SRX. Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEH - DDR2: 1 - DDR3: tCKSRX - DDR4: - tCKSRX For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it up to next in - eger. - PSU_DDRC_DRAMTMG5_T_CKSRX 0x6 - - This is the time after Self Refresh Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay afte - SRE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL - DDR2: 1 - DDR3: max (10 ns, 5 tCK) - DDR4: - ax (10 ns, 5 tCK) For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it up - to next integer. - PSU_DDRC_DRAMTMG5_T_CKSRE 0x6 - - Minimum CKE low width for Self refresh or Self refresh power down entry to exit timing in memory clock cycles. Recommended se - tings: - mDDR: tRFC - LPDDR2: tCKESR - LPDDR3: tCKESR - LPDDR4: max(tCKELPD, tSR) - DDR2: tCKE - DDR3: tCKE + 1 - DDR4: tCKE - 1 For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it up to next intege - . - PSU_DDRC_DRAMTMG5_T_CKESR 0x4 - - Minimum number of cycles of CKE HIGH/LOW during power-down and self refresh. - LPDDR2/LPDDR3 mode: Set this to the larger of - CKE or tCKESR - LPDDR4 mode: Set this to the larger of tCKE, tCKELPD or tSR. - Non-LPDDR2/non-LPDDR3/non-LPDDR4 designs: Set - his to tCKE value. For configurations with MEMC_FREQ_RATIO=2, program this to (value described above)/2 and round it up to th - next integer value. Unit: Clocks. - PSU_DDRC_DRAMTMG5_T_CKE 0x3 - - SDRAM Timing Register 5 - (OFFSET, MASK, VALUE) (0XFD070114, 0x0F0F3F1FU ,0x06060403U) - RegMask = (DDRC_DRAMTMG5_T_CKSRX_MASK | DDRC_DRAMTMG5_T_CKSRE_MASK | DDRC_DRAMTMG5_T_CKESR_MASK | DDRC_DRAMTMG5_T_CKE_MASK | 0 ); - - RegVal = ((0x00000006U << DDRC_DRAMTMG5_T_CKSRX_SHIFT - | 0x00000006U << DDRC_DRAMTMG5_T_CKSRE_SHIFT - | 0x00000004U << DDRC_DRAMTMG5_T_CKESR_SHIFT - | 0x00000003U << DDRC_DRAMTMG5_T_CKE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DRAMTMG5_OFFSET ,0x0F0F3F1FU ,0x06060403U); - /*############################################################################################################################ */ - - /*Register : DRAMTMG6 @ 0XFD070118

- - This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after - PDE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 For configurations with MEMC_FREQ_RATIO=2, program this to recom - ended value divided by two and round it up to next integer. This is only present for designs supporting mDDR or LPDDR2/LPDDR3 - devices. - PSU_DDRC_DRAMTMG6_T_CKDPDE 0x1 - - This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock - table time before DPDX. Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 For configurations with MEMC_FREQ_RATIO=2, pr - gram this to recommended value divided by two and round it up to next integer. This is only present for designs supporting mD - R or LPDDR2 devices. - PSU_DDRC_DRAMTMG6_T_CKDPDX 0x1 - - This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing Clock Stop Exit. Specifies the - lock stable time before next command after Clock Stop Exit. Recommended settings: - mDDR: 1 - LPDDR2: tXP + 2 - LPDDR3: tXP + - 2 - LPDDR4: tXP + 2 For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it - p to next integer. This is only present for designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices. - PSU_DDRC_DRAMTMG6_T_CKCSX 0x4 - - SDRAM Timing Register 6 - (OFFSET, MASK, VALUE) (0XFD070118, 0x0F0F000FU ,0x01010004U) - RegMask = (DDRC_DRAMTMG6_T_CKDPDE_MASK | DDRC_DRAMTMG6_T_CKDPDX_MASK | DDRC_DRAMTMG6_T_CKCSX_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_DRAMTMG6_T_CKDPDE_SHIFT - | 0x00000001U << DDRC_DRAMTMG6_T_CKDPDX_SHIFT - | 0x00000004U << DDRC_DRAMTMG6_T_CKCSX_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DRAMTMG6_OFFSET ,0x0F0F000FU ,0x01010004U); - /*############################################################################################################################ */ - - /*Register : DRAMTMG7 @ 0XFD07011C

- - This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. - ecommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL For configurations with MEMC_FREQ_RATIO=2, program t - is to recommended value divided by two and round it up to next integer. This is only present for designs supporting mDDR or L - DDR2/LPDDR3/LPDDR4 devices. - PSU_DDRC_DRAMTMG7_T_CKPDE 0x6 - - This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable - time before PDX. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: 2 For configurations with MEMC_FREQ_RATIO= - , program this to recommended value divided by two and round it up to next integer. This is only present for designs supporti - g mDDR or LPDDR2/LPDDR3/LPDDR4 devices. - PSU_DDRC_DRAMTMG7_T_CKPDX 0x6 - - SDRAM Timing Register 7 - (OFFSET, MASK, VALUE) (0XFD07011C, 0x00000F0FU ,0x00000606U) - RegMask = (DDRC_DRAMTMG7_T_CKPDE_MASK | DDRC_DRAMTMG7_T_CKPDX_MASK | 0 ); - - RegVal = ((0x00000006U << DDRC_DRAMTMG7_T_CKPDE_SHIFT - | 0x00000006U << DDRC_DRAMTMG7_T_CKPDX_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DRAMTMG7_OFFSET ,0x00000F0FU ,0x00000606U); - /*############################################################################################################################ */ - - /*Register : DRAMTMG8 @ 0XFD070120

- - tXS_FAST: Exit Self Refresh to ZQCL, ZQCS and MRS (only CL, WR, RTP and Geardown mode). For configurations with MEMC_FREQ_RAT - O=2, program this to the above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: Thi - is applicable to only ZQCL/ZQCS commands. Note: Ensure this is less than or equal to t_xs_x32. - PSU_DDRC_DRAMTMG8_T_XS_FAST_X32 0x4 - - tXS_ABORT: Exit Self Refresh to commands not requiring a locked DLL in Self Refresh Abort. For configurations with MEMC_FREQ_ - ATIO=2, program this to the above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: - nsure this is less than or equal to t_xs_x32. - PSU_DDRC_DRAMTMG8_T_XS_ABORT_X32 0x4 - - tXSDLL: Exit Self Refresh to commands requiring a locked DLL. For configurations with MEMC_FREQ_RATIO=2, program this to the - bove value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: Used only for DDR2, DDR3 and - DR4 SDRAMs. - PSU_DDRC_DRAMTMG8_T_XS_DLL_X32 0xd - - tXS: Exit Self Refresh to commands not requiring a locked DLL. For configurations with MEMC_FREQ_RATIO=2, program this to the - above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: Used only for DDR2, DDR3 and - DDR4 SDRAMs. - PSU_DDRC_DRAMTMG8_T_XS_X32 0x6 - - SDRAM Timing Register 8 - (OFFSET, MASK, VALUE) (0XFD070120, 0x7F7F7F7FU ,0x04040D06U) - RegMask = (DDRC_DRAMTMG8_T_XS_FAST_X32_MASK | DDRC_DRAMTMG8_T_XS_ABORT_X32_MASK | DDRC_DRAMTMG8_T_XS_DLL_X32_MASK | DDRC_DRAMTMG8_T_XS_X32_MASK | 0 ); - - RegVal = ((0x00000004U << DDRC_DRAMTMG8_T_XS_FAST_X32_SHIFT - | 0x00000004U << DDRC_DRAMTMG8_T_XS_ABORT_X32_SHIFT - | 0x0000000DU << DDRC_DRAMTMG8_T_XS_DLL_X32_SHIFT - | 0x00000006U << DDRC_DRAMTMG8_T_XS_X32_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DRAMTMG8_OFFSET ,0x7F7F7F7FU ,0x04040D06U); - /*############################################################################################################################ */ - - /*Register : DRAMTMG9 @ 0XFD070124

- - DDR4 Write preamble mode - 0: 1tCK preamble - 1: 2tCK preamble Present only with MEMC_FREQ_RATIO=2 - PSU_DDRC_DRAMTMG9_DDR4_WR_PREAMBLE 0x0 - - tCCD_S: This is the minimum time between two reads or two writes for different bank group. For bank switching (from bank 'a' - o bank 'b'), the minimum time is this value + 1. For configurations with MEMC_FREQ_RATIO=2, program this to (tCCD_S/2) and ro - nd it up to the next integer value. Present only in designs configured to support DDR4. Unit: clocks. - PSU_DDRC_DRAMTMG9_T_CCD_S 0x2 - - tRRD_S: Minimum time between activates from bank 'a' to bank 'b' for different bank group. For configurations with MEMC_FREQ_ - ATIO=2, program this to (tRRD_S/2) and round it up to the next integer value. Present only in designs configured to support D - R4. Unit: Clocks. - PSU_DDRC_DRAMTMG9_T_RRD_S 0x2 - - CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command for different bank group. Includes time for bus turn - round, recovery times, and all per-bank, per-rank, and global constraints. Present only in designs configured to support DDR4 - Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity latency - BL = burst length. This must match the value programm - d in the BL bit of the mode register to the SDRAM - tWTR_S = internal write to read command delay for different bank group. T - is comes directly from the SDRAM specification. For configurations with MEMC_FREQ_RATIO=2, divide the value calculated using - he above equation by 2, and round it up to next integer. - PSU_DDRC_DRAMTMG9_WR2RD_S 0xb - - SDRAM Timing Register 9 - (OFFSET, MASK, VALUE) (0XFD070124, 0x40070F3FU ,0x0002020BU) - RegMask = (DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_MASK | DDRC_DRAMTMG9_T_CCD_S_MASK | DDRC_DRAMTMG9_T_RRD_S_MASK | DDRC_DRAMTMG9_WR2RD_S_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_SHIFT - | 0x00000002U << DDRC_DRAMTMG9_T_CCD_S_SHIFT - | 0x00000002U << DDRC_DRAMTMG9_T_RRD_S_SHIFT - | 0x0000000BU << DDRC_DRAMTMG9_WR2RD_S_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DRAMTMG9_OFFSET ,0x40070F3FU ,0x0002020BU); - /*############################################################################################################################ */ - - /*Register : DRAMTMG11 @ 0XFD07012C

- - tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DLL. For configurations with MEMC_FREQ_RATIO=2, program - this to (tXMPDLL/2) and round it up to the next integer value. Present only in designs configured to support DDR4. Unit: Mult - ples of 32 clocks. - PSU_DDRC_DRAMTMG11_POST_MPSM_GAP_X32 0x6f - - tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge. For configurations with MEMC_FREQ_RATIO=2, program this t - RoundUp(tMPX_LH/2)+1. Present only in designs configured to support DDR4. Unit: clocks. - PSU_DDRC_DRAMTMG11_T_MPX_LH 0x7 - - tMPX_S: Minimum time CS setup time to CKE. For configurations with MEMC_FREQ_RATIO=2, program this to (tMPX_S/2) and round it - up to the next integer value. Present only in designs configured to support DDR4. Unit: Clocks. - PSU_DDRC_DRAMTMG11_T_MPX_S 0x1 - - tCKMPE: Minimum valid clock requirement after MPSM entry. Present only in designs configured to support DDR4. Unit: Clocks. F - r configurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next i - teger. - PSU_DDRC_DRAMTMG11_T_CKMPE 0xe - - SDRAM Timing Register 11 - (OFFSET, MASK, VALUE) (0XFD07012C, 0x7F1F031FU ,0x6F07010EU) - RegMask = (DDRC_DRAMTMG11_POST_MPSM_GAP_X32_MASK | DDRC_DRAMTMG11_T_MPX_LH_MASK | DDRC_DRAMTMG11_T_MPX_S_MASK | DDRC_DRAMTMG11_T_CKMPE_MASK | 0 ); - - RegVal = ((0x0000006FU << DDRC_DRAMTMG11_POST_MPSM_GAP_X32_SHIFT - | 0x00000007U << DDRC_DRAMTMG11_T_MPX_LH_SHIFT - | 0x00000001U << DDRC_DRAMTMG11_T_MPX_S_SHIFT - | 0x0000000EU << DDRC_DRAMTMG11_T_CKMPE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DRAMTMG11_OFFSET ,0x7F1F031FU ,0x6F07010EU); - /*############################################################################################################################ */ - - /*Register : DRAMTMG12 @ 0XFD070130

- - tCMDCKE: Delay from valid command to CKE input LOW. Set this to the larger of tESCKE or tCMDCKE For configurations with MEMC_ - REQ_RATIO=2, program this to (max(tESCKE, tCMDCKE)/2) and round it up to next integer value. - PSU_DDRC_DRAMTMG12_T_CMDCKE 0x2 - - tCKEHCMD: Valid command requirement after CKE input HIGH. For configurations with MEMC_FREQ_RATIO=2, program this to (tCKEHCM - /2) and round it up to next integer value. - PSU_DDRC_DRAMTMG12_T_CKEHCMD 0x6 - - tMRD_PDA: This is the Mode Register Set command cycle time in PDA mode. For configurations with MEMC_FREQ_RATIO=2, program th - s to (tMRD_PDA/2) and round it up to next integer value. - PSU_DDRC_DRAMTMG12_T_MRD_PDA 0x8 - - SDRAM Timing Register 12 - (OFFSET, MASK, VALUE) (0XFD070130, 0x00030F1FU ,0x00020608U) - RegMask = (DDRC_DRAMTMG12_T_CMDCKE_MASK | DDRC_DRAMTMG12_T_CKEHCMD_MASK | DDRC_DRAMTMG12_T_MRD_PDA_MASK | 0 ); - - RegVal = ((0x00000002U << DDRC_DRAMTMG12_T_CMDCKE_SHIFT - | 0x00000006U << DDRC_DRAMTMG12_T_CKEHCMD_SHIFT - | 0x00000008U << DDRC_DRAMTMG12_T_MRD_PDA_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DRAMTMG12_OFFSET ,0x00030F1FU ,0x00020608U); - /*############################################################################################################################ */ - - /*Register : ZQCTL0 @ 0XFD070180

- - - 1 - Disable uMCTL2 generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used instead to is - ue ZQ calibration request from APB module. - 0 - Internally generate ZQCS/MPC(ZQ calibration) commands based on ZQCTL1.t_zq_s - ort_interval_x1024. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. - PSU_DDRC_ZQCTL0_DIS_AUTO_ZQ 0x1 - - - 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable when run in DDR3 - or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. - 0 - Enable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Power - own exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. This is only present for designs suppo - ting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. - PSU_DDRC_ZQCTL0_DIS_SRX_ZQCL 0x0 - - - 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are sent to one r - nk at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to different ranks do not ov - rlap. - 0 - ZQ resistor is not shared. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. - PSU_DDRC_ZQCTL0_ZQ_RESISTOR_SHARED 0x0 - - - 1 - Disable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode. - 0 - Enable - ssuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode. This is only present for des - gns supporting DDR4 devices. - PSU_DDRC_ZQCTL0_DIS_MPSMX_ZQCL 0x0 - - tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Number of cycles of NOP required after a ZQCL (ZQ calibrat - on long)/MPC(ZQ Start) command is issued to SDRAM. For configurations with MEMC_FREQ_RATIO=2: DDR3/DDR4: program this to tZQo - er/2 and round it up to the next integer value. LPDDR2/LPDDR3: program this to tZQCL/2 and round it up to the next integer va - ue. LPDDR4: program this to tZQCAL/2 and round it up to the next integer value. Unit: Clock cycles. This is only present for - esigns supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. - PSU_DDRC_ZQCTL0_T_ZQ_LONG_NOP 0x100 - - tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of cycles of NOP required after a ZQCS (ZQ calibration short)/MPC - ZQ Latch) command is issued to SDRAM. For configurations with MEMC_FREQ_RATIO=2, program this to tZQCS/2 and round it up to t - e next integer value. Unit: Clock cycles. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devic - s. - PSU_DDRC_ZQCTL0_T_ZQ_SHORT_NOP 0x40 - - ZQ Control Register 0 - (OFFSET, MASK, VALUE) (0XFD070180, 0xF7FF03FFU ,0x81000040U) - RegMask = (DDRC_ZQCTL0_DIS_AUTO_ZQ_MASK | DDRC_ZQCTL0_DIS_SRX_ZQCL_MASK | DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_MASK | DDRC_ZQCTL0_DIS_MPSMX_ZQCL_MASK | DDRC_ZQCTL0_T_ZQ_LONG_NOP_MASK | DDRC_ZQCTL0_T_ZQ_SHORT_NOP_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_ZQCTL0_DIS_AUTO_ZQ_SHIFT - | 0x00000000U << DDRC_ZQCTL0_DIS_SRX_ZQCL_SHIFT - | 0x00000000U << DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_SHIFT - | 0x00000000U << DDRC_ZQCTL0_DIS_MPSMX_ZQCL_SHIFT - | 0x00000100U << DDRC_ZQCTL0_T_ZQ_LONG_NOP_SHIFT - | 0x00000040U << DDRC_ZQCTL0_T_ZQ_SHORT_NOP_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_ZQCTL0_OFFSET ,0xF7FF03FFU ,0x81000040U); - /*############################################################################################################################ */ - - /*Register : ZQCTL1 @ 0XFD070184

- - tZQReset: Number of cycles of NOP required after a ZQReset (ZQ calibration Reset) command is issued to SDRAM. For configurati - ns with MEMC_FREQ_RATIO=2, program this to tZQReset/2 and round it up to the next integer value. Unit: Clock cycles. This is - nly present for designs supporting LPDDR2/LPDDR3/LPDDR4 devices. - PSU_DDRC_ZQCTL1_T_ZQ_RESET_NOP 0x20 - - Average interval to wait between automatically issuing ZQCS (ZQ calibration short)/MPC(ZQ calibration) commands to DDR3/DDR4/ - PDDR2/LPDDR3/LPDDR4 devices. Meaningless, if ZQCTL0.dis_auto_zq=1. Unit: 1024 clock cycles. This is only present for designs - upporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. - PSU_DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024 0x19707 - - ZQ Control Register 1 - (OFFSET, MASK, VALUE) (0XFD070184, 0x3FFFFFFFU ,0x02019707U) - RegMask = (DDRC_ZQCTL1_T_ZQ_RESET_NOP_MASK | DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_MASK | 0 ); - - RegVal = ((0x00000020U << DDRC_ZQCTL1_T_ZQ_RESET_NOP_SHIFT - | 0x00019707U << DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_ZQCTL1_OFFSET ,0x3FFFFFFFU ,0x02019707U); - /*############################################################################################################################ */ - - /*Register : DFITMG0 @ 0XFD070190

- - Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signa - s at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligne - , this timing parameter should be rounded up to the next integer value. Note that if using RDIMM, it is necessary to incremen - this parameter by RDIMM's extra cycle of latency in terms of DFI clock. - PSU_DDRC_DFITMG0_DFI_T_CTRL_DELAY 0x4 - - Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR or SDR values Selects whether value in DFITM - 0.dfi_t_rddata_en is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles R - fer to PHY specification for correct value. - PSU_DDRC_DFITMG0_DFI_RDDATA_USE_SDR 0x1 - - Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. Refer to PHY spe - ification for correct value. This corresponds to the DFI parameter trddata_en. Note that, depending on the PHY, if using RDIM - , it may be necessary to use the value (CL + 1) in the calculation of trddata_en. This is to compensate for the extra cycle o - latency through the RDIMM. Unit: Clocks - PSU_DDRC_DFITMG0_DFI_T_RDDATA_EN 0xb - - Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using HDR or SDR values Selects whether value in DFITMG - .dfi_tphy_wrlat is in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.dfi_tphy_wrdata is in terms of SDR or - HDR clock cycles - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles Refer to PHY specification for correct val - e. - PSU_DDRC_DFITMG0_DFI_WRDATA_USE_SDR 0x1 - - Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on th - dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. N - te, max supported value is 8. Unit: Clocks - PSU_DDRC_DFITMG0_DFI_TPHY_WRDATA 0x2 - - Write latency Number of clocks from the write command to write data enable (dfi_wrdata_en). This corresponds to the DFI timin - parameter tphy_wrlat. Refer to PHY specification for correct value.Note that, depending on the PHY, if using RDIMM, it may b - necessary to use the value (CL + 1) in the calculation of tphy_wrlat. This is to compensate for the extra cycle of latency t - rough the RDIMM. - PSU_DDRC_DFITMG0_DFI_TPHY_WRLAT 0xb - - DFI Timing Register 0 - (OFFSET, MASK, VALUE) (0XFD070190, 0x1FBFBF3FU ,0x048B820BU) - RegMask = (DDRC_DFITMG0_DFI_T_CTRL_DELAY_MASK | DDRC_DFITMG0_DFI_RDDATA_USE_SDR_MASK | DDRC_DFITMG0_DFI_T_RDDATA_EN_MASK | DDRC_DFITMG0_DFI_WRDATA_USE_SDR_MASK | DDRC_DFITMG0_DFI_TPHY_WRDATA_MASK | DDRC_DFITMG0_DFI_TPHY_WRLAT_MASK | 0 ); - - RegVal = ((0x00000004U << DDRC_DFITMG0_DFI_T_CTRL_DELAY_SHIFT - | 0x00000001U << DDRC_DFITMG0_DFI_RDDATA_USE_SDR_SHIFT - | 0x0000000BU << DDRC_DFITMG0_DFI_T_RDDATA_EN_SHIFT - | 0x00000001U << DDRC_DFITMG0_DFI_WRDATA_USE_SDR_SHIFT - | 0x00000002U << DDRC_DFITMG0_DFI_TPHY_WRDATA_SHIFT - | 0x0000000BU << DDRC_DFITMG0_DFI_TPHY_WRLAT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DFITMG0_OFFSET ,0x1FBFBF3FU ,0x048B820BU); - /*############################################################################################################################ */ - - /*Register : DFITMG1 @ 0XFD070194

- - Specifies the number of DFI PHY clocks between when the dfi_cs signal is asserted and when the associated command is driven. - his field is used for CAL mode, should be set to '0' or the value which matches the CAL mode register setting in the DRAM. If - the PHY can add the latency for CAL mode, this should be set to '0'. Valid Range: 0, 3, 4, 5, 6, and 8 - PSU_DDRC_DFITMG1_DFI_T_CMD_LAT 0x0 - - Specifies the number of DFI PHY clocks between when the dfi_cs signal is asserted and when the associated dfi_parity_in signa - is driven. - PSU_DDRC_DFITMG1_DFI_T_PARIN_LAT 0x0 - - Specifies the number of DFI clocks between when the dfi_wrdata_en signal is asserted and when the corresponding write data tr - nsfer is completed on the DRAM bus. This corresponds to the DFI timing parameter twrdata_delay. Refer to PHY specification fo - correct value. For DFI 3.0 PHY, set to twrdata_delay, a new timing parameter introduced in DFI 3.0. For DFI 2.1 PHY, set to - phy_wrdata + (delay of DFI write data to the DRAM). Value to be programmed is in terms of DFI clocks, not PHY clocks. In FREQ - RATIO=2, divide PHY's value by 2 and round up to next integer. If using DFITMG0.dfi_wrdata_use_sdr=1, add 1 to the value. Uni - : Clocks - PSU_DDRC_DFITMG1_DFI_T_WRDATA_DELAY 0x3 - - Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to - he DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase - ligned, this timing parameter should be rounded up to the next integer value. - PSU_DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE 0x3 - - Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first - alid rising edge of the clock to the DRAM memory devices, at the PHY-DRAM boundary. If the DFI clock and the memory clock are - not phase aligned, this timing parameter should be rounded up to the next integer value. - PSU_DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE 0x4 - - DFI Timing Register 1 - (OFFSET, MASK, VALUE) (0XFD070194, 0xF31F0F0FU ,0x00030304U) - RegMask = (DDRC_DFITMG1_DFI_T_CMD_LAT_MASK | DDRC_DFITMG1_DFI_T_PARIN_LAT_MASK | DDRC_DFITMG1_DFI_T_WRDATA_DELAY_MASK | DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_MASK | DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_DFITMG1_DFI_T_CMD_LAT_SHIFT - | 0x00000000U << DDRC_DFITMG1_DFI_T_PARIN_LAT_SHIFT - | 0x00000003U << DDRC_DFITMG1_DFI_T_WRDATA_DELAY_SHIFT - | 0x00000003U << DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_SHIFT - | 0x00000004U << DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DFITMG1_OFFSET ,0xF31F0F0FU ,0x00030304U); - /*############################################################################################################################ */ - - /*Register : DFILPCFG0 @ 0XFD070198

- - Setting for DFI's tlp_resp time. Same value is used for both Power Down, Self Refresh, Deep Power Down and Maximum Power Savi - g modes. DFI 2.1 specification onwards, recommends using a fixed value of 7 always. - PSU_DDRC_DFILPCFG0_DFI_TLP_RESP 0x7 - - Value to drive on dfi_lp_wakeup signal when Deep Power Down mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 - cycles - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles - 0x7 - - 2048 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0xD - - 31072 cycles - 0xE - 262144 cycles - 0xF - Unlimited This is only present for designs supporting mDDR or LPDDR2/LPDDR3 device - . - PSU_DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD 0x0 - - Enables DFI Low Power interface handshaking during Deep Power Down Entry/Exit. - 0 - Disabled - 1 - Enabled This is only pres - nt for designs supporting mDDR or LPDDR2/LPDDR3 devices. - PSU_DDRC_DFILPCFG0_DFI_LP_EN_DPD 0x0 - - Value to drive on dfi_lp_wakeup signal when Self Refresh mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cy - les - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles - 0x7 - - 048 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0xD - 131 - 72 cycles - 0xE - 262144 cycles - 0xF - Unlimited - PSU_DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR 0x0 - - Enables DFI Low Power interface handshaking during Self Refresh Entry/Exit. - 0 - Disabled - 1 - Enabled - PSU_DDRC_DFILPCFG0_DFI_LP_EN_SR 0x1 - - Value to drive on dfi_lp_wakeup signal when Power Down mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycl - s - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles - 0x7 - 20 - 8 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0xD - 13107 - cycles - 0xE - 262144 cycles - 0xF - Unlimited - PSU_DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD 0x0 - - Enables DFI Low Power interface handshaking during Power Down Entry/Exit. - 0 - Disabled - 1 - Enabled - PSU_DDRC_DFILPCFG0_DFI_LP_EN_PD 0x1 - - DFI Low Power Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD070198, 0x0FF1F1F1U ,0x07000101U) - RegMask = (DDRC_DFILPCFG0_DFI_TLP_RESP_MASK | DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_MASK | DDRC_DFILPCFG0_DFI_LP_EN_DPD_MASK | DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_MASK | DDRC_DFILPCFG0_DFI_LP_EN_SR_MASK | DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_MASK | DDRC_DFILPCFG0_DFI_LP_EN_PD_MASK | 0 ); - - RegVal = ((0x00000007U << DDRC_DFILPCFG0_DFI_TLP_RESP_SHIFT - | 0x00000000U << DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_SHIFT - | 0x00000000U << DDRC_DFILPCFG0_DFI_LP_EN_DPD_SHIFT - | 0x00000000U << DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_SHIFT - | 0x00000001U << DDRC_DFILPCFG0_DFI_LP_EN_SR_SHIFT - | 0x00000000U << DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_SHIFT - | 0x00000001U << DDRC_DFILPCFG0_DFI_LP_EN_PD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DFILPCFG0_OFFSET ,0x0FF1F1F1U ,0x07000101U); - /*############################################################################################################################ */ - - /*Register : DFILPCFG1 @ 0XFD07019C

- - Value to drive on dfi_lp_wakeup signal when Maximum Power Saving Mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - - 16 cycles - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0 - D - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited This is only present for designs supporting DDR4 devices. - PSU_DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM 0x2 - - Enables DFI Low Power interface handshaking during Maximum Power Saving Mode Entry/Exit. - 0 - Disabled - 1 - Enabled This is - only present for designs supporting DDR4 devices. - PSU_DDRC_DFILPCFG1_DFI_LP_EN_MPSM 0x1 - - DFI Low Power Configuration Register 1 - (OFFSET, MASK, VALUE) (0XFD07019C, 0x000000F1U ,0x00000021U) - RegMask = (DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_MASK | DDRC_DFILPCFG1_DFI_LP_EN_MPSM_MASK | 0 ); - - RegVal = ((0x00000002U << DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_SHIFT - | 0x00000001U << DDRC_DFILPCFG1_DFI_LP_EN_MPSM_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DFILPCFG1_OFFSET ,0x000000F1U ,0x00000021U); - /*############################################################################################################################ */ - - /*Register : DFIUPD1 @ 0XFD0701A4

- - This is the minimum amount of time between uMCTL2 initiated DFI update requests (which is executed whenever the uMCTL2 is idl - ). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the fir - t read request when the uMCTL2 is idle. Unit: 1024 clocks - PSU_DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024 0x41 - - This is the maximum amount of time between uMCTL2 initiated DFI update requests. This timer resets with each update request; - hen the timer expires dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd_ackx is received. PHY can use this - idle time to recalibrate the delay lines to the DLLs. The DFI controller update is also used to reset PHY FIFO pointers in ca - e of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. - Note: Value programmed for DFIUPD1.dfi_t_ctrlupd_interval_max_x1024 must be greater than DFIUPD1.dfi_t_ctrlupd_interval_min_x - 024. Unit: 1024 clocks - PSU_DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024 0xe2 - - DFI Update Register 1 - (OFFSET, MASK, VALUE) (0XFD0701A4, 0x00FF00FFU ,0x004100E2U) - RegMask = (DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_MASK | DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_MASK | 0 ); - - RegVal = ((0x00000041U << DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_SHIFT - | 0x000000E2U << DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DFIUPD1_OFFSET ,0x00FF00FFU ,0x004100E2U); - /*############################################################################################################################ */ - - /*Register : DFIMISC @ 0XFD0701B0

- - Defines polarity of dfi_wrdata_cs and dfi_rddata_cs signals. - 0: Signals are active low - 1: Signals are active high - PSU_DDRC_DFIMISC_DFI_DATA_CS_POLARITY 0x0 - - DBI implemented in DDRC or PHY. - 0 - DDRC implements DBI functionality. - 1 - PHY implements DBI functionality. Present only - in designs configured to support DDR4 and LPDDR4. - PSU_DDRC_DFIMISC_PHY_DBI_MODE 0x0 - - PHY initialization complete enable signal. When asserted the dfi_init_complete signal can be used to trigger SDRAM initialisa - ion - PSU_DDRC_DFIMISC_DFI_INIT_COMPLETE_EN 0x0 - - DFI Miscellaneous Control Register - (OFFSET, MASK, VALUE) (0XFD0701B0, 0x00000007U ,0x00000000U) - RegMask = (DDRC_DFIMISC_DFI_DATA_CS_POLARITY_MASK | DDRC_DFIMISC_PHY_DBI_MODE_MASK | DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_DFIMISC_DFI_DATA_CS_POLARITY_SHIFT - | 0x00000000U << DDRC_DFIMISC_PHY_DBI_MODE_SHIFT - | 0x00000000U << DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DFIMISC_OFFSET ,0x00000007U ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : DFITMG2 @ 0XFD0701B4

- - >Number of clocks between when a read command is sent on the DFI control interface and when the associated dfi_rddata_cs sign - l is asserted. This corresponds to the DFI timing parameter tphy_rdcslat. Refer to PHY specification for correct value. - PSU_DDRC_DFITMG2_DFI_TPHY_RDCSLAT 0x9 - - Number of clocks between when a write command is sent on the DFI control interface and when the associated dfi_wrdata_cs sign - l is asserted. This corresponds to the DFI timing parameter tphy_wrcslat. Refer to PHY specification for correct value. - PSU_DDRC_DFITMG2_DFI_TPHY_WRCSLAT 0x6 - - DFI Timing Register 2 - (OFFSET, MASK, VALUE) (0XFD0701B4, 0x00003F3FU ,0x00000906U) - RegMask = (DDRC_DFITMG2_DFI_TPHY_RDCSLAT_MASK | DDRC_DFITMG2_DFI_TPHY_WRCSLAT_MASK | 0 ); - - RegVal = ((0x00000009U << DDRC_DFITMG2_DFI_TPHY_RDCSLAT_SHIFT - | 0x00000006U << DDRC_DFITMG2_DFI_TPHY_WRCSLAT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DFITMG2_OFFSET ,0x00003F3FU ,0x00000906U); - /*############################################################################################################################ */ - - /*Register : DBICTL @ 0XFD0701C0

- - Read DBI enable signal in DDRC. - 0 - Read DBI is disabled. - 1 - Read DBI is enabled. This signal must be set the same value - as DRAM's mode register. - DDR4: MR5 bit A12. When x4 devices are used, this signal must be set to 0. - LPDDR4: MR3[6] - PSU_DDRC_DBICTL_RD_DBI_EN 0x0 - - Write DBI enable signal in DDRC. - 0 - Write DBI is disabled. - 1 - Write DBI is enabled. This signal must be set the same va - ue as DRAM's mode register. - DDR4: MR5 bit A11. When x4 devices are used, this signal must be set to 0. - LPDDR4: MR3[7] - PSU_DDRC_DBICTL_WR_DBI_EN 0x0 - - DM enable signal in DDRC. - 0 - DM is disabled. - 1 - DM is enabled. This signal must be set the same logical value as DRAM's - mode register. - DDR4: Set this to same value as MR5 bit A10. When x4 devices are used, this signal must be set to 0. - LPDDR - : Set this to inverted value of MR13[5] which is opposite polarity from this signal - PSU_DDRC_DBICTL_DM_EN 0x1 - - DM/DBI Control Register - (OFFSET, MASK, VALUE) (0XFD0701C0, 0x00000007U ,0x00000001U) - RegMask = (DDRC_DBICTL_RD_DBI_EN_MASK | DDRC_DBICTL_WR_DBI_EN_MASK | DDRC_DBICTL_DM_EN_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_DBICTL_RD_DBI_EN_SHIFT - | 0x00000000U << DDRC_DBICTL_WR_DBI_EN_SHIFT - | 0x00000001U << DDRC_DBICTL_DM_EN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DBICTL_OFFSET ,0x00000007U ,0x00000001U); - /*############################################################################################################################ */ - - /*Register : ADDRMAP0 @ 0XFD070200

- - Selects the HIF address bit used as rank address bit 0. Valid Range: 0 to 27, and 31 Internal Base: 6 The selected HIF addres - bit is determined by adding the internal base to the value of this field. If set to 31, rank address bit 0 is set to 0. - PSU_DDRC_ADDRMAP0_ADDRMAP_CS_BIT0 0x1f - - Address Map Register 0 - (OFFSET, MASK, VALUE) (0XFD070200, 0x0000001FU ,0x0000001FU) - RegMask = (DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_MASK | 0 ); - - RegVal = ((0x0000001FU << DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_ADDRMAP0_OFFSET ,0x0000001FU ,0x0000001FU); - /*############################################################################################################################ */ - - /*Register : ADDRMAP1 @ 0XFD070204

- - Selects the HIF address bit used as bank address bit 2. Valid Range: 0 to 29 and 31 Internal Base: 4 The selected HIF address - bit is determined by adding the internal base to the value of this field. If set to 31, bank address bit 2 is set to 0. - PSU_DDRC_ADDRMAP1_ADDRMAP_BANK_B2 0x1f - - Selects the HIF address bits used as bank address bit 1. Valid Range: 0 to 30 Internal Base: 3 The selected HIF address bit f - r each of the bank address bits is determined by adding the internal base to the value of this field. - PSU_DDRC_ADDRMAP1_ADDRMAP_BANK_B1 0xa - - Selects the HIF address bits used as bank address bit 0. Valid Range: 0 to 30 Internal Base: 2 The selected HIF address bit f - r each of the bank address bits is determined by adding the internal base to the value of this field. - PSU_DDRC_ADDRMAP1_ADDRMAP_BANK_B0 0xa - - Address Map Register 1 - (OFFSET, MASK, VALUE) (0XFD070204, 0x001F1F1FU ,0x001F0A0AU) - RegMask = (DDRC_ADDRMAP1_ADDRMAP_BANK_B2_MASK | DDRC_ADDRMAP1_ADDRMAP_BANK_B1_MASK | DDRC_ADDRMAP1_ADDRMAP_BANK_B0_MASK | 0 ); - - RegVal = ((0x0000001FU << DDRC_ADDRMAP1_ADDRMAP_BANK_B2_SHIFT - | 0x0000000AU << DDRC_ADDRMAP1_ADDRMAP_BANK_B1_SHIFT - | 0x0000000AU << DDRC_ADDRMAP1_ADDRMAP_BANK_B0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_ADDRMAP1_OFFSET ,0x001F1F1FU ,0x001F0A0AU); - /*############################################################################################################################ */ - - /*Register : ADDRMAP2 @ 0XFD070208

- - - Full bus width mode: Selects the HIF address bit used as column address bit 5. - Half bus width mode: Selects the HIF addre - s bit used as column address bit 6. - Quarter bus width mode: Selects the HIF address bit used as column address bit 7 . Vali - Range: 0 to 7, and 15 Internal Base: 5 The selected HIF address bit is determined by adding the internal base to the value o - this field. If set to 15, this column address bit is set to 0. - PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B5 0x0 - - - Full bus width mode: Selects the HIF address bit used as column address bit 4. - Half bus width mode: Selects the HIF addre - s bit used as column address bit 5. - Quarter bus width mode: Selects the HIF address bit used as column address bit 6. Valid - Range: 0 to 7, and 15 Internal Base: 4 The selected HIF address bit is determined by adding the internal base to the value of - this field. If set to 15, this column address bit is set to 0. - PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B4 0x0 - - - Full bus width mode: Selects the HIF address bit used as column address bit 3. - Half bus width mode: Selects the HIF addre - s bit used as column address bit 4. - Quarter bus width mode: Selects the HIF address bit used as column address bit 5. Valid - Range: 0 to 7 Internal Base: 3 The selected HIF address bit is determined by adding the internal base to the value of this fi - ld. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=16, it is required to program this to 0, hence register does not exist i - this case. - PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B3 0x0 - - - Full bus width mode: Selects the HIF address bit used as column address bit 2. - Half bus width mode: Selects the HIF addre - s bit used as column address bit 3. - Quarter bus width mode: Selects the HIF address bit used as column address bit 4. Valid - Range: 0 to 7 Internal Base: 2 The selected HIF address bit is determined by adding the internal base to the value of this fi - ld. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=8 or 16, it is required to program this to 0. - PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B2 0x0 - - Address Map Register 2 - (OFFSET, MASK, VALUE) (0XFD070208, 0x0F0F0F0FU ,0x00000000U) - RegMask = (DDRC_ADDRMAP2_ADDRMAP_COL_B5_MASK | DDRC_ADDRMAP2_ADDRMAP_COL_B4_MASK | DDRC_ADDRMAP2_ADDRMAP_COL_B3_MASK | DDRC_ADDRMAP2_ADDRMAP_COL_B2_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_ADDRMAP2_ADDRMAP_COL_B5_SHIFT - | 0x00000000U << DDRC_ADDRMAP2_ADDRMAP_COL_B4_SHIFT - | 0x00000000U << DDRC_ADDRMAP2_ADDRMAP_COL_B3_SHIFT - | 0x00000000U << DDRC_ADDRMAP2_ADDRMAP_COL_B2_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_ADDRMAP2_OFFSET ,0x0F0F0F0FU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : ADDRMAP3 @ 0XFD07020C

- - - Full bus width mode: Selects the HIF address bit used as column address bit 9. - Half bus width mode: Selects the HIF addre - s bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). - Quarter bus width mode: Selects the HIF address bit used as - column address bit 13 (11 in LPDDR2/LPDDR3 mode). Valid Range: 0 to 7, and 15 Internal Base: 9 The selected HIF address bit i - determined by adding the internal base to the value of this field. If set to 15, this column address bit is set to 0. Note: - er JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source addr - ss bit can be mapped to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus an - hence column bit 10 is used. - PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B9 0x0 - - - Full bus width mode: Selects the HIF address bit used as column address bit 8. - Half bus width mode: Selects the HIF addre - s bit used as column address bit 9. - Quarter bus width mode: Selects the HIF address bit used as column address bit 11 (10 i - LPDDR2/LPDDR3 mode). Valid Range: 0 to 7, and 15 Internal Base: 8 The selected HIF address bit is determined by adding the i - ternal base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specif - cation, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to col - mn address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and hence column bit 10 is use - . - PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B8 0x0 - - - Full bus width mode: Selects the HIF address bit used as column address bit 7. - Half bus width mode: Selects the HIF addre - s bit used as column address bit 8. - Quarter bus width mode: Selects the HIF address bit used as column address bit 9. Valid - Range: 0 to 7, and 15 Internal Base: 7 The selected HIF address bit is determined by adding the internal base to the value of - this field. If set to 15, this column address bit is set to 0. - PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B7 0x0 - - - Full bus width mode: Selects the HIF address bit used as column address bit 6. - Half bus width mode: Selects the HIF addre - s bit used as column address bit 7. - Quarter bus width mode: Selects the HIF address bit used as column address bit 8. Valid - Range: 0 to 7, and 15 Internal Base: 6 The selected HIF address bit is determined by adding the internal base to the value of - this field. If set to 15, this column address bit is set to 0. - PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B6 0x0 - - Address Map Register 3 - (OFFSET, MASK, VALUE) (0XFD07020C, 0x0F0F0F0FU ,0x00000000U) - RegMask = (DDRC_ADDRMAP3_ADDRMAP_COL_B9_MASK | DDRC_ADDRMAP3_ADDRMAP_COL_B8_MASK | DDRC_ADDRMAP3_ADDRMAP_COL_B7_MASK | DDRC_ADDRMAP3_ADDRMAP_COL_B6_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_ADDRMAP3_ADDRMAP_COL_B9_SHIFT - | 0x00000000U << DDRC_ADDRMAP3_ADDRMAP_COL_B8_SHIFT - | 0x00000000U << DDRC_ADDRMAP3_ADDRMAP_COL_B7_SHIFT - | 0x00000000U << DDRC_ADDRMAP3_ADDRMAP_COL_B6_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_ADDRMAP3_OFFSET ,0x0F0F0F0FU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : ADDRMAP4 @ 0XFD070210

- - - Full bus width mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode). - Half bus width - mode: Unused. To make it unused, this should be tied to 4'hF. - Quarter bus width mode: Unused. To make it unused, this must - e tied to 4'hF. Valid Range: 0 to 7, and 15 Internal Base: 11 The selected HIF address bit is determined by adding the intern - l base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specificati - n, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column a - dress bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and hence column bit 10 is used. - PSU_DDRC_ADDRMAP4_ADDRMAP_COL_B11 0xf - - - Full bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). - Half bus width - mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode). - Quarter bus width mode: UNUSED. - To make it unused, this must be tied to 4'hF. Valid Range: 0 to 7, and 15 Internal Base: 10 The selected HIF address bit is d - termined by adding the internal base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per - JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source address - bit can be mapped to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and h - nce column bit 10 is used. - PSU_DDRC_ADDRMAP4_ADDRMAP_COL_B10 0xf - - Address Map Register 4 - (OFFSET, MASK, VALUE) (0XFD070210, 0x00000F0FU ,0x00000F0FU) - RegMask = (DDRC_ADDRMAP4_ADDRMAP_COL_B11_MASK | DDRC_ADDRMAP4_ADDRMAP_COL_B10_MASK | 0 ); - - RegVal = ((0x0000000FU << DDRC_ADDRMAP4_ADDRMAP_COL_B11_SHIFT - | 0x0000000FU << DDRC_ADDRMAP4_ADDRMAP_COL_B10_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_ADDRMAP4_OFFSET ,0x00000F0FU ,0x00000F0FU); - /*############################################################################################################################ */ - - /*Register : ADDRMAP5 @ 0XFD070214

- - Selects the HIF address bit used as row address bit 11. Valid Range: 0 to 11, and 15 Internal Base: 17 The selected HIF addre - s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 11 is set to 0. - PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B11 0x8 - - Selects the HIF address bits used as row address bits 2 to 10. Valid Range: 0 to 11, and 15 Internal Base: 8 (for row address - bit 2), 9 (for row address bit 3), 10 (for row address bit 4) etc increasing to 16 (for row address bit 10) The selected HIF - ddress bit for each of the row address bits is determined by adding the internal base to the value of this field. When value - 5 is used the values of row address bits 2 to 10 are defined by registers ADDRMAP9, ADDRMAP10, ADDRMAP11. - PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10 0xf - - Selects the HIF address bits used as row address bit 1. Valid Range: 0 to 11 Internal Base: 7 The selected HIF address bit fo - each of the row address bits is determined by adding the internal base to the value of this field. - PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B1 0x8 - - Selects the HIF address bits used as row address bit 0. Valid Range: 0 to 11 Internal Base: 6 The selected HIF address bit fo - each of the row address bits is determined by adding the internal base to the value of this field. - PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B0 0x8 - - Address Map Register 5 - (OFFSET, MASK, VALUE) (0XFD070214, 0x0F0F0F0FU ,0x080F0808U) - RegMask = (DDRC_ADDRMAP5_ADDRMAP_ROW_B11_MASK | DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_MASK | DDRC_ADDRMAP5_ADDRMAP_ROW_B1_MASK | DDRC_ADDRMAP5_ADDRMAP_ROW_B0_MASK | 0 ); - - RegVal = ((0x00000008U << DDRC_ADDRMAP5_ADDRMAP_ROW_B11_SHIFT - | 0x0000000FU << DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_SHIFT - | 0x00000008U << DDRC_ADDRMAP5_ADDRMAP_ROW_B1_SHIFT - | 0x00000008U << DDRC_ADDRMAP5_ADDRMAP_ROW_B0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_ADDRMAP5_OFFSET ,0x0F0F0F0FU ,0x080F0808U); - /*############################################################################################################################ */ - - /*Register : ADDRMAP6 @ 0XFD070218

- - Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use. - 1 - LPDDR3 SDRAM 6Gb/12Gb device in use. Every address - having row[14:13]==2'b11 is considered as invalid - 0 - non-LPDDR3 6Gb/12Gb device in use. All addresses are valid Present on - y in designs configured to support LPDDR3. - PSU_DDRC_ADDRMAP6_LPDDR3_6GB_12GB 0x0 - - Selects the HIF address bit used as row address bit 15. Valid Range: 0 to 11, and 15 Internal Base: 21 The selected HIF addre - s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 15 is set to 0. - PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B15 0xf - - Selects the HIF address bit used as row address bit 14. Valid Range: 0 to 11, and 15 Internal Base: 20 The selected HIF addre - s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 14 is set to 0. - PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B14 0x8 - - Selects the HIF address bit used as row address bit 13. Valid Range: 0 to 11, and 15 Internal Base: 19 The selected HIF addre - s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 13 is set to 0. - PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B13 0x8 - - Selects the HIF address bit used as row address bit 12. Valid Range: 0 to 11, and 15 Internal Base: 18 The selected HIF addre - s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 12 is set to 0. - PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B12 0x8 - - Address Map Register 6 - (OFFSET, MASK, VALUE) (0XFD070218, 0x8F0F0F0FU ,0x0F080808U) - RegMask = (DDRC_ADDRMAP6_LPDDR3_6GB_12GB_MASK | DDRC_ADDRMAP6_ADDRMAP_ROW_B15_MASK | DDRC_ADDRMAP6_ADDRMAP_ROW_B14_MASK | DDRC_ADDRMAP6_ADDRMAP_ROW_B13_MASK | DDRC_ADDRMAP6_ADDRMAP_ROW_B12_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_ADDRMAP6_LPDDR3_6GB_12GB_SHIFT - | 0x0000000FU << DDRC_ADDRMAP6_ADDRMAP_ROW_B15_SHIFT - | 0x00000008U << DDRC_ADDRMAP6_ADDRMAP_ROW_B14_SHIFT - | 0x00000008U << DDRC_ADDRMAP6_ADDRMAP_ROW_B13_SHIFT - | 0x00000008U << DDRC_ADDRMAP6_ADDRMAP_ROW_B12_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_ADDRMAP6_OFFSET ,0x8F0F0F0FU ,0x0F080808U); - /*############################################################################################################################ */ - - /*Register : ADDRMAP7 @ 0XFD07021C

- - Selects the HIF address bit used as row address bit 17. Valid Range: 0 to 10, and 15 Internal Base: 23 The selected HIF addre - s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 17 is set to 0. - PSU_DDRC_ADDRMAP7_ADDRMAP_ROW_B17 0xf - - Selects the HIF address bit used as row address bit 16. Valid Range: 0 to 11, and 15 Internal Base: 22 The selected HIF addre - s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 16 is set to 0. - PSU_DDRC_ADDRMAP7_ADDRMAP_ROW_B16 0xf - - Address Map Register 7 - (OFFSET, MASK, VALUE) (0XFD07021C, 0x00000F0FU ,0x00000F0FU) - RegMask = (DDRC_ADDRMAP7_ADDRMAP_ROW_B17_MASK | DDRC_ADDRMAP7_ADDRMAP_ROW_B16_MASK | 0 ); - - RegVal = ((0x0000000FU << DDRC_ADDRMAP7_ADDRMAP_ROW_B17_SHIFT - | 0x0000000FU << DDRC_ADDRMAP7_ADDRMAP_ROW_B16_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_ADDRMAP7_OFFSET ,0x00000F0FU ,0x00000F0FU); - /*############################################################################################################################ */ - - /*Register : ADDRMAP8 @ 0XFD070220

- - Selects the HIF address bits used as bank group address bit 1. Valid Range: 0 to 30, and 31 Internal Base: 3 The selected HIF - address bit for each of the bank group address bits is determined by adding the internal base to the value of this field. If - et to 31, bank group address bit 1 is set to 0. - PSU_DDRC_ADDRMAP8_ADDRMAP_BG_B1 0x8 - - Selects the HIF address bits used as bank group address bit 0. Valid Range: 0 to 30 Internal Base: 2 The selected HIF address - bit for each of the bank group address bits is determined by adding the internal base to the value of this field. - PSU_DDRC_ADDRMAP8_ADDRMAP_BG_B0 0x8 - - Address Map Register 8 - (OFFSET, MASK, VALUE) (0XFD070220, 0x00001F1FU ,0x00000808U) - RegMask = (DDRC_ADDRMAP8_ADDRMAP_BG_B1_MASK | DDRC_ADDRMAP8_ADDRMAP_BG_B0_MASK | 0 ); - - RegVal = ((0x00000008U << DDRC_ADDRMAP8_ADDRMAP_BG_B1_SHIFT - | 0x00000008U << DDRC_ADDRMAP8_ADDRMAP_BG_B0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_ADDRMAP8_OFFSET ,0x00001F1FU ,0x00000808U); - /*############################################################################################################################ */ - - /*Register : ADDRMAP9 @ 0XFD070224

- - Selects the HIF address bits used as row address bit 5. Valid Range: 0 to 11 Internal Base: 11 The selected HIF address bit f - r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u - ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15. - PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B5 0x8 - - Selects the HIF address bits used as row address bit 4. Valid Range: 0 to 11 Internal Base: 10 The selected HIF address bit f - r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u - ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15. - PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B4 0x8 - - Selects the HIF address bits used as row address bit 3. Valid Range: 0 to 11 Internal Base: 9 The selected HIF address bit fo - each of the row address bits is determined by adding the internal base to the value of this field. This register field is us - d only when ADDRMAP5.addrmap_row_b2_10 is set to value 15. - PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B3 0x8 - - Selects the HIF address bits used as row address bit 2. Valid Range: 0 to 11 Internal Base: 8 The selected HIF address bit fo - each of the row address bits is determined by adding the internal base to the value of this field. This register field is us - d only when ADDRMAP5.addrmap_row_b2_10 is set to value 15. - PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B2 0x8 - - Address Map Register 9 - (OFFSET, MASK, VALUE) (0XFD070224, 0x0F0F0F0FU ,0x08080808U) - RegMask = (DDRC_ADDRMAP9_ADDRMAP_ROW_B5_MASK | DDRC_ADDRMAP9_ADDRMAP_ROW_B4_MASK | DDRC_ADDRMAP9_ADDRMAP_ROW_B3_MASK | DDRC_ADDRMAP9_ADDRMAP_ROW_B2_MASK | 0 ); - - RegVal = ((0x00000008U << DDRC_ADDRMAP9_ADDRMAP_ROW_B5_SHIFT - | 0x00000008U << DDRC_ADDRMAP9_ADDRMAP_ROW_B4_SHIFT - | 0x00000008U << DDRC_ADDRMAP9_ADDRMAP_ROW_B3_SHIFT - | 0x00000008U << DDRC_ADDRMAP9_ADDRMAP_ROW_B2_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_ADDRMAP9_OFFSET ,0x0F0F0F0FU ,0x08080808U); - /*############################################################################################################################ */ - - /*Register : ADDRMAP10 @ 0XFD070228

- - Selects the HIF address bits used as row address bit 9. Valid Range: 0 to 11 Internal Base: 15 The selected HIF address bit f - r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u - ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15. - PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B9 0x8 - - Selects the HIF address bits used as row address bit 8. Valid Range: 0 to 11 Internal Base: 14 The selected HIF address bit f - r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u - ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15. - PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B8 0x8 - - Selects the HIF address bits used as row address bit 7. Valid Range: 0 to 11 Internal Base: 13 The selected HIF address bit f - r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u - ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15. - PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B7 0x8 - - Selects the HIF address bits used as row address bit 6. Valid Range: 0 to 11 Internal Base: 12 The selected HIF address bit f - r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u - ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15. - PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B6 0x8 - - Address Map Register 10 - (OFFSET, MASK, VALUE) (0XFD070228, 0x0F0F0F0FU ,0x08080808U) - RegMask = (DDRC_ADDRMAP10_ADDRMAP_ROW_B9_MASK | DDRC_ADDRMAP10_ADDRMAP_ROW_B8_MASK | DDRC_ADDRMAP10_ADDRMAP_ROW_B7_MASK | DDRC_ADDRMAP10_ADDRMAP_ROW_B6_MASK | 0 ); - - RegVal = ((0x00000008U << DDRC_ADDRMAP10_ADDRMAP_ROW_B9_SHIFT - | 0x00000008U << DDRC_ADDRMAP10_ADDRMAP_ROW_B8_SHIFT - | 0x00000008U << DDRC_ADDRMAP10_ADDRMAP_ROW_B7_SHIFT - | 0x00000008U << DDRC_ADDRMAP10_ADDRMAP_ROW_B6_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_ADDRMAP10_OFFSET ,0x0F0F0F0FU ,0x08080808U); - /*############################################################################################################################ */ - - /*Register : ADDRMAP11 @ 0XFD07022C

- - Selects the HIF address bits used as row address bit 10. Valid Range: 0 to 11 Internal Base: 16 The selected HIF address bit - or each of the row address bits is determined by adding the internal base to the value of this field. This register field is - sed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15. - PSU_DDRC_ADDRMAP11_ADDRMAP_ROW_B10 0x8 - - Address Map Register 11 - (OFFSET, MASK, VALUE) (0XFD07022C, 0x0000000FU ,0x00000008U) - RegMask = (DDRC_ADDRMAP11_ADDRMAP_ROW_B10_MASK | 0 ); - - RegVal = ((0x00000008U << DDRC_ADDRMAP11_ADDRMAP_ROW_B10_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_ADDRMAP11_OFFSET ,0x0000000FU ,0x00000008U); - /*############################################################################################################################ */ - - /*Register : ODTCFG @ 0XFD070240

- - Cycles to hold ODT for a write command. The minimum supported value is 2. Recommended values: DDR2: - BL8: 0x5 (DDR2-400/533/ - 67), 0x6 (DDR2-800), 0x7 (DDR2-1066) - BL4: 0x3 (DDR2-400/533/667), 0x4 (DDR2-800), 0x5 (DDR2-1066) DDR3: - BL8: 0x6 DDR4: - - L8: 5 + WR_PREAMBLE + CRC_MODE WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) CRC_MODE = 0 (not CRC mode), 1 - CRC mode) LPDDR3: - BL8: 7 + RU(tODTon(max)/tCK) - PSU_DDRC_ODTCFG_WR_ODT_HOLD 0x6 - - The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting must - remain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: - CWL + AL - 3 (DDR2-400/533/ - 67), CWL + AL - 4 (DDR2-800), CWL + AL - 5 (DDR2-1066) If (CWL + AL - 3 < 0), uMCTL2 does not support ODT for write operation - DDR3: - 0x0 DDR4: - DFITMG1.dfi_t_cmd_lat (to adjust for CAL mode) LPDDR3: - WL - 1 - RU(tODTon(max)/tCK)) - PSU_DDRC_ODTCFG_WR_ODT_DELAY 0x0 - - Cycles to hold ODT for a read command. The minimum supported value is 2. Recommended values: DDR2: - BL8: 0x6 (not DDR2-1066) - 0x7 (DDR2-1066) - BL4: 0x4 (not DDR2-1066), 0x5 (DDR2-1066) DDR3: - BL8 - 0x6 DDR4: - BL8: 5 + RD_PREAMBLE RD_PREAMBLE = 1 ( - tCK write preamble), 2 (2tCK write preamble) LPDDR3: - BL8: 5 + RU(tDQSCK(max)/tCK) - RD(tDQSCK(min)/tCK) + RU(tODTon(max)/tC - ) - PSU_DDRC_ODTCFG_RD_ODT_HOLD 0x6 - - The delay, in clock cycles, from issuing a read command to setting ODT values associated with that command. ODT setting must - emain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: - CL + AL - 4 (not DDR2-1066), - CL + AL - 5 (DDR2-1066) If (CL + AL - 4 < 0), uMCTL2 does not support ODT for read operation. DDR3: - CL - CWL DDR4: - CL - C - L - RD_PREAMBLE + WR_PREAMBLE + DFITMG1.dfi_t_cmd_lat (to adjust for CAL mode) WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK - write preamble) RD_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) If (CL - CWL - RD_PREAMBLE + WR_PREAMBLE) < 0, - uMCTL2 does not support ODT for read operation. LPDDR3: - RL + RD(tDQSCK(min)/tCK) - 1 - RU(tODTon(max)/tCK) - PSU_DDRC_ODTCFG_RD_ODT_DELAY 0x0 - - ODT Configuration Register - (OFFSET, MASK, VALUE) (0XFD070240, 0x0F1F0F7CU ,0x06000600U) - RegMask = (DDRC_ODTCFG_WR_ODT_HOLD_MASK | DDRC_ODTCFG_WR_ODT_DELAY_MASK | DDRC_ODTCFG_RD_ODT_HOLD_MASK | DDRC_ODTCFG_RD_ODT_DELAY_MASK | 0 ); - - RegVal = ((0x00000006U << DDRC_ODTCFG_WR_ODT_HOLD_SHIFT - | 0x00000000U << DDRC_ODTCFG_WR_ODT_DELAY_SHIFT - | 0x00000006U << DDRC_ODTCFG_RD_ODT_HOLD_SHIFT - | 0x00000000U << DDRC_ODTCFG_RD_ODT_DELAY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_ODTCFG_OFFSET ,0x0F1F0F7CU ,0x06000600U); - /*############################################################################################################################ */ - - /*Register : ODTMAP @ 0XFD070244

- - Indicates which remote ODTs must be turned on during a read from rank 1. Each rank has a remote ODT (in the SDRAM) which can - e turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB - etc. For each rank, set its bit to 1 to enable its ODT. Present only in configurations that have 2 or more ranks - PSU_DDRC_ODTMAP_RANK1_RD_ODT 0x0 - - Indicates which remote ODTs must be turned on during a write to rank 1. Each rank has a remote ODT (in the SDRAM) which can b - turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB, - etc. For each rank, set its bit to 1 to enable its ODT. Present only in configurations that have 2 or more ranks - PSU_DDRC_ODTMAP_RANK1_WR_ODT 0x0 - - Indicates which remote ODTs must be turned on during a read from rank 0. Each rank has a remote ODT (in the SDRAM) which can - e turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB - etc. For each rank, set its bit to 1 to enable its ODT. - PSU_DDRC_ODTMAP_RANK0_RD_ODT 0x0 - - Indicates which remote ODTs must be turned on during a write to rank 0. Each rank has a remote ODT (in the SDRAM) which can b - turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB, - etc. For each rank, set its bit to 1 to enable its ODT. - PSU_DDRC_ODTMAP_RANK0_WR_ODT 0x1 - - ODT/Rank Map Register - (OFFSET, MASK, VALUE) (0XFD070244, 0x00003333U ,0x00000001U) - RegMask = (DDRC_ODTMAP_RANK1_RD_ODT_MASK | DDRC_ODTMAP_RANK1_WR_ODT_MASK | DDRC_ODTMAP_RANK0_RD_ODT_MASK | DDRC_ODTMAP_RANK0_WR_ODT_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_ODTMAP_RANK1_RD_ODT_SHIFT - | 0x00000000U << DDRC_ODTMAP_RANK1_WR_ODT_SHIFT - | 0x00000000U << DDRC_ODTMAP_RANK0_RD_ODT_SHIFT - | 0x00000001U << DDRC_ODTMAP_RANK0_WR_ODT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_ODTMAP_OFFSET ,0x00003333U ,0x00000001U); - /*############################################################################################################################ */ - - /*Register : SCHED @ 0XFD070250

- - When the preferred transaction store is empty for these many clock cycles, switch to the alternate transaction store if it is - non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write t - ansaction store is the alternative store. When prefer write over read is set this is reversed. 0x0 is a legal value for this - egister. When set to 0x0, the transaction store switching will happen immediately when the switching conditions become true. - OR PERFORMANCE ONLY - PSU_DDRC_SCHED_RDWR_IDLE_GAP 0x1 - - UNUSED - PSU_DDRC_SCHED_GO2CRITICAL_HYSTERESIS 0x0 - - Number of entries in the low priority transaction store is this value + 1. (MEMC_NO_OF_ENTRY - (SCHED.lpr_num_entries + 1)) i - the number of entries available for the high priority transaction store. Setting this to maximum value allocates all entries - to low priority transaction store. Setting this to 0 allocates 1 entry to low priority transaction store and the rest to high - priority transaction store. Note: In ECC configurations, the numbers of write and low priority read credits issued is one les - than in the non-ECC case. One entry each is reserved in the write and low-priority read CAMs for storing the RMW requests ar - sing out of single bit error correction RMW operation. - PSU_DDRC_SCHED_LPR_NUM_ENTRIES 0x20 - - If true, bank is kept open only while there are page hit transactions available in the CAM to that bank. The last read or wri - e command in the CAM with a bank and page hit will be executed with auto-precharge if SCHED1.pageclose_timer=0. Even if this - egister set to 1 and SCHED1.pageclose_timer is set to 0, explicit precharge (and not auto-precharge) may be issued in some ca - es where there is a mode switch between Write and Read or between LPR and HPR. The Read and Write commands that are executed - s part of the ECC scrub requests are also executed without auto-precharge. If false, the bank remains open until there is a n - ed to close it (to open a different page, or for page timeout or refresh timeout) - also known as open page policy. The open - age policy can be overridden by setting the per-command-autopre bit on the HIF interface (hif_cmd_autopre). The pageclose fea - ure provids a midway between Open and Close page policies. FOR PERFORMANCE ONLY. - PSU_DDRC_SCHED_PAGECLOSE 0x0 - - If set then the bank selector prefers writes over reads. FOR DEBUG ONLY. - PSU_DDRC_SCHED_PREFER_WRITE 0x0 - - Active low signal. When asserted ('0'), all incoming transactions are forced to low priority. This implies that all High Prio - ity Read (HPR) and Variable Priority Read commands (VPR) will be treated as Low Priority Read (LPR) commands. On the write si - e, all Variable Priority Write (VPW) commands will be treated as Normal Priority Write (NPW) commands. Forcing the incoming t - ansactions to low priority implicitly turns off Bypass path for read commands. FOR PERFORMANCE ONLY. - PSU_DDRC_SCHED_FORCE_LOW_PRI_N 0x1 - - Scheduler Control Register - (OFFSET, MASK, VALUE) (0XFD070250, 0x7FFF3F07U ,0x01002001U) - RegMask = (DDRC_SCHED_RDWR_IDLE_GAP_MASK | DDRC_SCHED_GO2CRITICAL_HYSTERESIS_MASK | DDRC_SCHED_LPR_NUM_ENTRIES_MASK | DDRC_SCHED_PAGECLOSE_MASK | DDRC_SCHED_PREFER_WRITE_MASK | DDRC_SCHED_FORCE_LOW_PRI_N_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_SCHED_RDWR_IDLE_GAP_SHIFT - | 0x00000000U << DDRC_SCHED_GO2CRITICAL_HYSTERESIS_SHIFT - | 0x00000020U << DDRC_SCHED_LPR_NUM_ENTRIES_SHIFT - | 0x00000000U << DDRC_SCHED_PAGECLOSE_SHIFT - | 0x00000000U << DDRC_SCHED_PREFER_WRITE_SHIFT - | 0x00000001U << DDRC_SCHED_FORCE_LOW_PRI_N_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_SCHED_OFFSET ,0x7FFF3F07U ,0x01002001U); - /*############################################################################################################################ */ - - /*Register : PERFLPR1 @ 0XFD070264

- - Number of transactions that are serviced once the LPR queue goes critical is the smaller of: - (a) This number - (b) Number o - transactions available. Unit: Transaction. FOR PERFORMANCE ONLY. - PSU_DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH 0x8 - - Number of clocks that the LPR queue can be starved before it goes critical. The minimum valid functional value for this regis - er is 0x1. Programming it to 0x0 will disable the starvation functionality; during normal operation, this function should not - be disabled as it will cause excessive latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY. - PSU_DDRC_PERFLPR1_LPR_MAX_STARVE 0x40 - - Low Priority Read CAM Register 1 - (OFFSET, MASK, VALUE) (0XFD070264, 0xFF00FFFFU ,0x08000040U) - RegMask = (DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_MASK | DDRC_PERFLPR1_LPR_MAX_STARVE_MASK | 0 ); - - RegVal = ((0x00000008U << DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_SHIFT - | 0x00000040U << DDRC_PERFLPR1_LPR_MAX_STARVE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PERFLPR1_OFFSET ,0xFF00FFFFU ,0x08000040U); - /*############################################################################################################################ */ - - /*Register : PERFWR1 @ 0XFD07026C

- - Number of transactions that are serviced once the WR queue goes critical is the smaller of: - (a) This number - (b) Number of - transactions available. Unit: Transaction. FOR PERFORMANCE ONLY. - PSU_DDRC_PERFWR1_W_XACT_RUN_LENGTH 0x8 - - Number of clocks that the WR queue can be starved before it goes critical. The minimum valid functional value for this regist - r is 0x1. Programming it to 0x0 will disable the starvation functionality; during normal operation, this function should not - e disabled as it will cause excessive latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY. - PSU_DDRC_PERFWR1_W_MAX_STARVE 0x40 - - Write CAM Register 1 - (OFFSET, MASK, VALUE) (0XFD07026C, 0xFF00FFFFU ,0x08000040U) - RegMask = (DDRC_PERFWR1_W_XACT_RUN_LENGTH_MASK | DDRC_PERFWR1_W_MAX_STARVE_MASK | 0 ); - - RegVal = ((0x00000008U << DDRC_PERFWR1_W_XACT_RUN_LENGTH_SHIFT - | 0x00000040U << DDRC_PERFWR1_W_MAX_STARVE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PERFWR1_OFFSET ,0xFF00FFFFU ,0x08000040U); - /*############################################################################################################################ */ - - /*Register : DQMAP5 @ 0XFD070294

- - All even ranks have the same DQ mapping controled by DQMAP0-4 register as rank 0. This register provides DQ swap function for - all odd ranks to support CRC feature. rank based DQ swapping is: swap bit 0 with 1, swap bit 2 with 3, swap bit 4 with 5 and - wap bit 6 with 7. 1: Disable rank based DQ swapping 0: Enable rank based DQ swapping Present only in designs configured to su - port DDR4. - PSU_DDRC_DQMAP5_DIS_DQ_RANK_SWAP 0x1 - - DQ Map Register 5 - (OFFSET, MASK, VALUE) (0XFD070294, 0x00000001U ,0x00000001U) - RegMask = (DDRC_DQMAP5_DIS_DQ_RANK_SWAP_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_DQMAP5_DIS_DQ_RANK_SWAP_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DQMAP5_OFFSET ,0x00000001U ,0x00000001U); - /*############################################################################################################################ */ - - /*Register : DBG0 @ 0XFD070300

- - When this is set to '0', auto-precharge is disabled for the flushed command in a collision case. Collision cases are write fo - lowed by read to same address, read followed by write to same address, or write followed by write to same address with DBG0.d - s_wc bit = 1 (where same address comparisons exclude the two address bits representing critical word). FOR DEBUG ONLY. - PSU_DDRC_DBG0_DIS_COLLISION_PAGE_OPT 0x0 - - When 1, disable write combine. FOR DEBUG ONLY - PSU_DDRC_DBG0_DIS_WC 0x0 - - Debug Register 0 - (OFFSET, MASK, VALUE) (0XFD070300, 0x00000011U ,0x00000000U) - RegMask = (DDRC_DBG0_DIS_COLLISION_PAGE_OPT_MASK | DDRC_DBG0_DIS_WC_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_DBG0_DIS_COLLISION_PAGE_OPT_SHIFT - | 0x00000000U << DDRC_DBG0_DIS_WC_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DBG0_OFFSET ,0x00000011U ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : DBGCMD @ 0XFD07030C

- - Setting this register bit to 1 allows refresh and ZQCS commands to be triggered from hardware via the IOs ext_*. If set to 1, - the fields DBGCMD.zq_calib_short and DBGCMD.rank*_refresh have no function, and are ignored by the uMCTL2 logic. Setting this - register bit to 0 allows refresh and ZQCS to be triggered from software, via the fields DBGCMD.zq_calib_short and DBGCMD.rank - _refresh. If set to 0, the hardware pins ext_* have no function, and are ignored by the uMCTL2 logic. This register is static - and may only be changed when the DDRC reset signal, core_ddrc_rstn, is asserted (0). - PSU_DDRC_DBGCMD_HW_REF_ZQ_EN 0x0 - - Setting this register bit to 1 indicates to the uMCTL2 to issue a dfi_ctrlupd_req to the PHY. When this request is stored in - he uMCTL2, the bit is automatically cleared. This operation must only be performed when DFIUPD0.dis_auto_ctrlupd=1. - PSU_DDRC_DBGCMD_CTRLUPD 0x0 - - Setting this register bit to 1 indicates to the uMCTL2 to issue a ZQCS (ZQ calibration short)/MPC(ZQ calibration) command to - he SDRAM. When this request is stored in the uMCTL2, the bit is automatically cleared. This operation can be performed only w - en ZQCTL0.dis_auto_zq=1. It is recommended NOT to set this register bit if in Init operating mode. This register bit is ignor - d when in Self-Refresh(except LPDDR4) and SR-Powerdown(LPDDR4) and Deep power-down operating modes and Maximum Power Saving M - de. - PSU_DDRC_DBGCMD_ZQ_CALIB_SHORT 0x0 - - Setting this register bit to 1 indicates to the uMCTL2 to issue a refresh to rank 1. Writing to this bit causes DBGSTAT.rank1 - refresh_busy to be set. When DBGSTAT.rank1_refresh_busy is cleared, the command has been stored in uMCTL2. This operation can - be performed only when RFSHCTL3.dis_auto_refresh=1. It is recommended NOT to set this register bit if in Init or Deep power-d - wn operating modes or Maximum Power Saving Mode. - PSU_DDRC_DBGCMD_RANK1_REFRESH 0x0 - - Setting this register bit to 1 indicates to the uMCTL2 to issue a refresh to rank 0. Writing to this bit causes DBGSTAT.rank0 - refresh_busy to be set. When DBGSTAT.rank0_refresh_busy is cleared, the command has been stored in uMCTL2. This operation can - be performed only when RFSHCTL3.dis_auto_refresh=1. It is recommended NOT to set this register bit if in Init or Deep power-d - wn operating modes or Maximum Power Saving Mode. - PSU_DDRC_DBGCMD_RANK0_REFRESH 0x0 - - Command Debug Register - (OFFSET, MASK, VALUE) (0XFD07030C, 0x80000033U ,0x00000000U) - RegMask = (DDRC_DBGCMD_HW_REF_ZQ_EN_MASK | DDRC_DBGCMD_CTRLUPD_MASK | DDRC_DBGCMD_ZQ_CALIB_SHORT_MASK | DDRC_DBGCMD_RANK1_REFRESH_MASK | DDRC_DBGCMD_RANK0_REFRESH_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_DBGCMD_HW_REF_ZQ_EN_SHIFT - | 0x00000000U << DDRC_DBGCMD_CTRLUPD_SHIFT - | 0x00000000U << DDRC_DBGCMD_ZQ_CALIB_SHORT_SHIFT - | 0x00000000U << DDRC_DBGCMD_RANK1_REFRESH_SHIFT - | 0x00000000U << DDRC_DBGCMD_RANK0_REFRESH_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DBGCMD_OFFSET ,0x80000033U ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : SWCTL @ 0XFD070320

- - Enable quasi-dynamic register programming outside reset. Program register to 0 to enable quasi-dynamic programming. Set back - egister to 1 once programming is done. - PSU_DDRC_SWCTL_SW_DONE 0x0 - - Software register programming control enable - (OFFSET, MASK, VALUE) (0XFD070320, 0x00000001U ,0x00000000U) - RegMask = (DDRC_SWCTL_SW_DONE_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_SWCTL_SW_DONE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_SWCTL_OFFSET ,0x00000001U ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : PCCFG @ 0XFD070400

- - Burst length expansion mode. By default (i.e. bl_exp_mode==0) XPI expands every AXI burst into multiple HIF commands, using t - e memory burst length as a unit. If set to 1, then XPI will use half of the memory burst length as a unit. This applies to bo - h reads and writes. When MSTR.data_bus_width==00, setting bl_exp_mode to 1 has no effect. This can be used in cases where Par - ial Writes is enabled (UMCTL2_PARTIAL_WR=1) and DBG0.dis_wc=1, in order to avoid or minimize t_ccd_l penalty in DDR4 and t_cc - _mw penalty in LPDDR4. Note that if DBICTL.reg_ddrc_dm_en=0, functionality is not supported in the following cases: - UMCTL2_ - ARTIAL_WR=0 - UMCTL2_PARTIAL_WR=1, MSTR.reg_ddrc_data_bus_width=01, MEMC_BURST_LENGTH=8 and MSTR.reg_ddrc_burst_rdwr=1000 (LP - DR4 only) - UMCTL2_PARTIAL_WR=1, MSTR.reg_ddrc_data_bus_width=01, MEMC_BURST_LENGTH=4 and MSTR.reg_ddrc_burst_rdwr=0100 (DDR4 - only), with either MSTR.reg_ddrc_burstchop=0 or CRCPARCTL1.reg_ddrc_crc_enable=1 Functionality is also not supported if Share - -AC is enabled - PSU_DDRC_PCCFG_BL_EXP_MODE 0x0 - - Page match four limit. If set to 1, limits the number of consecutive same page DDRC transactions that can be granted by the P - rt Arbiter to four when Page Match feature is enabled. If set to 0, there is no limit imposed on number of consecutive same p - ge DDRC transactions. - PSU_DDRC_PCCFG_PAGEMATCH_LIMIT 0x0 - - If set to 1 (enabled), sets co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals going to DDRC based - n urgent input (awurgent, arurgent) coming from AXI master. If set to 0 (disabled), co_gs_go2critical_wr and co_gs_go2critica - _lpr/co_gs_go2critical_hpr signals at DDRC are driven to 1b'0. - PSU_DDRC_PCCFG_GO2CRITICAL_EN 0x1 - - Port Common Configuration Register - (OFFSET, MASK, VALUE) (0XFD070400, 0x00000111U ,0x00000001U) - RegMask = (DDRC_PCCFG_BL_EXP_MODE_MASK | DDRC_PCCFG_PAGEMATCH_LIMIT_MASK | DDRC_PCCFG_GO2CRITICAL_EN_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_PCCFG_BL_EXP_MODE_SHIFT - | 0x00000000U << DDRC_PCCFG_PAGEMATCH_LIMIT_SHIFT - | 0x00000001U << DDRC_PCCFG_GO2CRITICAL_EN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCCFG_OFFSET ,0x00000111U ,0x00000001U); - /*############################################################################################################################ */ - - /*Register : PCFGR_0 @ 0XFD070404

- - If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register. - PSU_DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN 0x0 - - If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG. - o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add - ess handshaking (it is not associated with any particular command). - PSU_DDRC_PCFGR_0_RD_PORT_URGENT_EN 0x1 - - If set to 1, enables aging function for the read channel of the port. - PSU_DDRC_PCFGR_0_RD_PORT_AGING_EN 0x0 - - Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g - ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority - will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre - ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the - aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st - ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w - ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D - RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: - he two LSBs of this register field are tied internally to 2'b00. - PSU_DDRC_PCFGR_0_RD_PORT_PRIORITY 0xf - - Port n Configuration Read Register - (OFFSET, MASK, VALUE) (0XFD070404, 0x000073FFU ,0x0000200FU) - RegMask = (DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGR_0_RD_PORT_URGENT_EN_MASK | DDRC_PCFGR_0_RD_PORT_AGING_EN_MASK | DDRC_PCFGR_0_RD_PORT_PRIORITY_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_SHIFT - | 0x00000001U << DDRC_PCFGR_0_RD_PORT_URGENT_EN_SHIFT - | 0x00000000U << DDRC_PCFGR_0_RD_PORT_AGING_EN_SHIFT - | 0x0000000FU << DDRC_PCFGR_0_RD_PORT_PRIORITY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGR_0_OFFSET ,0x000073FFU ,0x0000200FU); - /*############################################################################################################################ */ - - /*Register : PCFGW_0 @ 0XFD070408

- - If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register. - PSU_DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN 0x1 - - If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register - Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is - not associated with any particular command). - PSU_DDRC_PCFGW_0_WR_PORT_URGENT_EN 0x1 - - If set to 1, enables aging function for the write channel of the port. - PSU_DDRC_PCFGW_0_WR_PORT_AGING_EN 0x0 - - Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each - rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port - s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0 - the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno - be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For - ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch - ng. Note: The two LSBs of this register field are tied internally to 2'b00. - PSU_DDRC_PCFGW_0_WR_PORT_PRIORITY 0xf - - Port n Configuration Write Register - (OFFSET, MASK, VALUE) (0XFD070408, 0x000073FFU ,0x0000600FU) - RegMask = (DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGW_0_WR_PORT_URGENT_EN_MASK | DDRC_PCFGW_0_WR_PORT_AGING_EN_MASK | DDRC_PCFGW_0_WR_PORT_PRIORITY_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_SHIFT - | 0x00000001U << DDRC_PCFGW_0_WR_PORT_URGENT_EN_SHIFT - | 0x00000000U << DDRC_PCFGW_0_WR_PORT_AGING_EN_SHIFT - | 0x0000000FU << DDRC_PCFGW_0_WR_PORT_PRIORITY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGW_0_OFFSET ,0x000073FFU ,0x0000600FU); - /*############################################################################################################################ */ - - /*Register : PCTRL_0 @ 0XFD070490

- - Enables port n. - PSU_DDRC_PCTRL_0_PORT_EN 0x1 - - Port n Control Register - (OFFSET, MASK, VALUE) (0XFD070490, 0x00000001U ,0x00000001U) - RegMask = (DDRC_PCTRL_0_PORT_EN_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_PCTRL_0_PORT_EN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCTRL_0_OFFSET ,0x00000001U ,0x00000001U); - /*############################################################################################################################ */ - - /*Register : PCFGQOS0_0 @ 0XFD070494

- - This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf - gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is - disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. - PSU_DDRC_PCFGQOS0_0_RQOS_MAP_REGION1 0x2 - - This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi - urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i - disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. - PSU_DDRC_PCFGQOS0_0_RQOS_MAP_REGION0 0x0 - - Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d - al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio - ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc - values. - PSU_DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1 0xb - - Port n Read QoS Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD070494, 0x0033000FU ,0x0020000BU) - RegMask = (DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_MASK | DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_MASK | DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_MASK | 0 ); - - RegVal = ((0x00000002U << DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_SHIFT - | 0x00000000U << DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_SHIFT - | 0x0000000BU << DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGQOS0_0_OFFSET ,0x0033000FU ,0x0020000BU); - /*############################################################################################################################ */ - - /*Register : PCFGQOS1_0 @ 0XFD070498

- - Specifies the timeout value for transactions mapped to the red address queue. - PSU_DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR 0x0 - - Specifies the timeout value for transactions mapped to the blue address queue. - PSU_DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB 0x0 - - Port n Read QoS Configuration Register 1 - (OFFSET, MASK, VALUE) (0XFD070498, 0x07FF07FFU ,0x00000000U) - RegMask = (DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_MASK | DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_SHIFT - | 0x00000000U << DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGQOS1_0_OFFSET ,0x07FF07FFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : PCFGR_1 @ 0XFD0704B4

- - If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register. - PSU_DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN 0x0 - - If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG. - o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add - ess handshaking (it is not associated with any particular command). - PSU_DDRC_PCFGR_1_RD_PORT_URGENT_EN 0x1 - - If set to 1, enables aging function for the read channel of the port. - PSU_DDRC_PCFGR_1_RD_PORT_AGING_EN 0x0 - - Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g - ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority - will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre - ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the - aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st - ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w - ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D - RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: - he two LSBs of this register field are tied internally to 2'b00. - PSU_DDRC_PCFGR_1_RD_PORT_PRIORITY 0xf - - Port n Configuration Read Register - (OFFSET, MASK, VALUE) (0XFD0704B4, 0x000073FFU ,0x0000200FU) - RegMask = (DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGR_1_RD_PORT_URGENT_EN_MASK | DDRC_PCFGR_1_RD_PORT_AGING_EN_MASK | DDRC_PCFGR_1_RD_PORT_PRIORITY_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_SHIFT - | 0x00000001U << DDRC_PCFGR_1_RD_PORT_URGENT_EN_SHIFT - | 0x00000000U << DDRC_PCFGR_1_RD_PORT_AGING_EN_SHIFT - | 0x0000000FU << DDRC_PCFGR_1_RD_PORT_PRIORITY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGR_1_OFFSET ,0x000073FFU ,0x0000200FU); - /*############################################################################################################################ */ - - /*Register : PCFGW_1 @ 0XFD0704B8

- - If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register. - PSU_DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN 0x1 - - If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register - Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is - not associated with any particular command). - PSU_DDRC_PCFGW_1_WR_PORT_URGENT_EN 0x1 - - If set to 1, enables aging function for the write channel of the port. - PSU_DDRC_PCFGW_1_WR_PORT_AGING_EN 0x0 - - Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each - rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port - s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0 - the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno - be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For - ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch - ng. Note: The two LSBs of this register field are tied internally to 2'b00. - PSU_DDRC_PCFGW_1_WR_PORT_PRIORITY 0xf - - Port n Configuration Write Register - (OFFSET, MASK, VALUE) (0XFD0704B8, 0x000073FFU ,0x0000600FU) - RegMask = (DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGW_1_WR_PORT_URGENT_EN_MASK | DDRC_PCFGW_1_WR_PORT_AGING_EN_MASK | DDRC_PCFGW_1_WR_PORT_PRIORITY_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_SHIFT - | 0x00000001U << DDRC_PCFGW_1_WR_PORT_URGENT_EN_SHIFT - | 0x00000000U << DDRC_PCFGW_1_WR_PORT_AGING_EN_SHIFT - | 0x0000000FU << DDRC_PCFGW_1_WR_PORT_PRIORITY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGW_1_OFFSET ,0x000073FFU ,0x0000600FU); - /*############################################################################################################################ */ - - /*Register : PCTRL_1 @ 0XFD070540

- - Enables port n. - PSU_DDRC_PCTRL_1_PORT_EN 0x1 - - Port n Control Register - (OFFSET, MASK, VALUE) (0XFD070540, 0x00000001U ,0x00000001U) - RegMask = (DDRC_PCTRL_1_PORT_EN_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_PCTRL_1_PORT_EN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCTRL_1_OFFSET ,0x00000001U ,0x00000001U); - /*############################################################################################################################ */ - - /*Register : PCFGQOS0_1 @ 0XFD070544

- - This bitfield indicates the traffic class of region2. For dual address queue configurations, region2 maps to the red address - ueue. Valid values are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and traffic class of region2 - s set to 1 (VPR), VPR traffic is aliased to LPR traffic. - PSU_DDRC_PCFGQOS0_1_RQOS_MAP_REGION2 0x2 - - This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf - gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is - disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. - PSU_DDRC_PCFGQOS0_1_RQOS_MAP_REGION1 0x0 - - This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi - urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i - disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. - PSU_DDRC_PCFGQOS0_1_RQOS_MAP_REGION0 0x0 - - Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (le - el1 + 1) to 14 which corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note that for PA, arqos values are used - directly as port priorities, where the higher the value corresponds to higher port priority. All of the map_level* registers - ust be set to distinct values. - PSU_DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2 0xb - - Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d - al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio - ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc - values. - PSU_DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1 0x3 - - Port n Read QoS Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD070544, 0x03330F0FU ,0x02000B03U) - RegMask = (DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_MASK | DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_MASK | DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_MASK | DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_MASK | DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_MASK | 0 ); - - RegVal = ((0x00000002U << DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_SHIFT - | 0x00000000U << DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_SHIFT - | 0x00000000U << DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_SHIFT - | 0x0000000BU << DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_SHIFT - | 0x00000003U << DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGQOS0_1_OFFSET ,0x03330F0FU ,0x02000B03U); - /*############################################################################################################################ */ - - /*Register : PCFGQOS1_1 @ 0XFD070548

- - Specifies the timeout value for transactions mapped to the red address queue. - PSU_DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR 0x0 - - Specifies the timeout value for transactions mapped to the blue address queue. - PSU_DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB 0x0 - - Port n Read QoS Configuration Register 1 - (OFFSET, MASK, VALUE) (0XFD070548, 0x07FF07FFU ,0x00000000U) - RegMask = (DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_MASK | DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_SHIFT - | 0x00000000U << DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGQOS1_1_OFFSET ,0x07FF07FFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : PCFGR_2 @ 0XFD070564

- - If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register. - PSU_DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN 0x0 - - If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG. - o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add - ess handshaking (it is not associated with any particular command). - PSU_DDRC_PCFGR_2_RD_PORT_URGENT_EN 0x1 - - If set to 1, enables aging function for the read channel of the port. - PSU_DDRC_PCFGR_2_RD_PORT_AGING_EN 0x0 - - Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g - ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority - will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre - ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the - aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st - ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w - ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D - RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: - he two LSBs of this register field are tied internally to 2'b00. - PSU_DDRC_PCFGR_2_RD_PORT_PRIORITY 0xf - - Port n Configuration Read Register - (OFFSET, MASK, VALUE) (0XFD070564, 0x000073FFU ,0x0000200FU) - RegMask = (DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGR_2_RD_PORT_URGENT_EN_MASK | DDRC_PCFGR_2_RD_PORT_AGING_EN_MASK | DDRC_PCFGR_2_RD_PORT_PRIORITY_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_SHIFT - | 0x00000001U << DDRC_PCFGR_2_RD_PORT_URGENT_EN_SHIFT - | 0x00000000U << DDRC_PCFGR_2_RD_PORT_AGING_EN_SHIFT - | 0x0000000FU << DDRC_PCFGR_2_RD_PORT_PRIORITY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGR_2_OFFSET ,0x000073FFU ,0x0000200FU); - /*############################################################################################################################ */ - - /*Register : PCFGW_2 @ 0XFD070568

- - If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register. - PSU_DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN 0x1 - - If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register - Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is - not associated with any particular command). - PSU_DDRC_PCFGW_2_WR_PORT_URGENT_EN 0x1 - - If set to 1, enables aging function for the write channel of the port. - PSU_DDRC_PCFGW_2_WR_PORT_AGING_EN 0x0 - - Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each - rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port - s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0 - the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno - be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For - ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch - ng. Note: The two LSBs of this register field are tied internally to 2'b00. - PSU_DDRC_PCFGW_2_WR_PORT_PRIORITY 0xf - - Port n Configuration Write Register - (OFFSET, MASK, VALUE) (0XFD070568, 0x000073FFU ,0x0000600FU) - RegMask = (DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGW_2_WR_PORT_URGENT_EN_MASK | DDRC_PCFGW_2_WR_PORT_AGING_EN_MASK | DDRC_PCFGW_2_WR_PORT_PRIORITY_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_SHIFT - | 0x00000001U << DDRC_PCFGW_2_WR_PORT_URGENT_EN_SHIFT - | 0x00000000U << DDRC_PCFGW_2_WR_PORT_AGING_EN_SHIFT - | 0x0000000FU << DDRC_PCFGW_2_WR_PORT_PRIORITY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGW_2_OFFSET ,0x000073FFU ,0x0000600FU); - /*############################################################################################################################ */ - - /*Register : PCTRL_2 @ 0XFD0705F0

- - Enables port n. - PSU_DDRC_PCTRL_2_PORT_EN 0x1 - - Port n Control Register - (OFFSET, MASK, VALUE) (0XFD0705F0, 0x00000001U ,0x00000001U) - RegMask = (DDRC_PCTRL_2_PORT_EN_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_PCTRL_2_PORT_EN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCTRL_2_OFFSET ,0x00000001U ,0x00000001U); - /*############################################################################################################################ */ - - /*Register : PCFGQOS0_2 @ 0XFD0705F4

- - This bitfield indicates the traffic class of region2. For dual address queue configurations, region2 maps to the red address - ueue. Valid values are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and traffic class of region2 - s set to 1 (VPR), VPR traffic is aliased to LPR traffic. - PSU_DDRC_PCFGQOS0_2_RQOS_MAP_REGION2 0x2 - - This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf - gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is - disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. - PSU_DDRC_PCFGQOS0_2_RQOS_MAP_REGION1 0x0 - - This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi - urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i - disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. - PSU_DDRC_PCFGQOS0_2_RQOS_MAP_REGION0 0x0 - - Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (le - el1 + 1) to 14 which corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note that for PA, arqos values are used - directly as port priorities, where the higher the value corresponds to higher port priority. All of the map_level* registers - ust be set to distinct values. - PSU_DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2 0xb - - Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d - al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio - ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc - values. - PSU_DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1 0x3 - - Port n Read QoS Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD0705F4, 0x03330F0FU ,0x02000B03U) - RegMask = (DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_MASK | DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_MASK | DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_MASK | DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_MASK | DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_MASK | 0 ); - - RegVal = ((0x00000002U << DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_SHIFT - | 0x00000000U << DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_SHIFT - | 0x00000000U << DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_SHIFT - | 0x0000000BU << DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_SHIFT - | 0x00000003U << DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGQOS0_2_OFFSET ,0x03330F0FU ,0x02000B03U); - /*############################################################################################################################ */ - - /*Register : PCFGQOS1_2 @ 0XFD0705F8

- - Specifies the timeout value for transactions mapped to the red address queue. - PSU_DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR 0x0 - - Specifies the timeout value for transactions mapped to the blue address queue. - PSU_DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB 0x0 - - Port n Read QoS Configuration Register 1 - (OFFSET, MASK, VALUE) (0XFD0705F8, 0x07FF07FFU ,0x00000000U) - RegMask = (DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_MASK | DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_SHIFT - | 0x00000000U << DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGQOS1_2_OFFSET ,0x07FF07FFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : PCFGR_3 @ 0XFD070614

- - If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register. - PSU_DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN 0x0 - - If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG. - o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add - ess handshaking (it is not associated with any particular command). - PSU_DDRC_PCFGR_3_RD_PORT_URGENT_EN 0x1 - - If set to 1, enables aging function for the read channel of the port. - PSU_DDRC_PCFGR_3_RD_PORT_AGING_EN 0x0 - - Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g - ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority - will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre - ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the - aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st - ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w - ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D - RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: - he two LSBs of this register field are tied internally to 2'b00. - PSU_DDRC_PCFGR_3_RD_PORT_PRIORITY 0xf - - Port n Configuration Read Register - (OFFSET, MASK, VALUE) (0XFD070614, 0x000073FFU ,0x0000200FU) - RegMask = (DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGR_3_RD_PORT_URGENT_EN_MASK | DDRC_PCFGR_3_RD_PORT_AGING_EN_MASK | DDRC_PCFGR_3_RD_PORT_PRIORITY_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_SHIFT - | 0x00000001U << DDRC_PCFGR_3_RD_PORT_URGENT_EN_SHIFT - | 0x00000000U << DDRC_PCFGR_3_RD_PORT_AGING_EN_SHIFT - | 0x0000000FU << DDRC_PCFGR_3_RD_PORT_PRIORITY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGR_3_OFFSET ,0x000073FFU ,0x0000200FU); - /*############################################################################################################################ */ - - /*Register : PCFGW_3 @ 0XFD070618

- - If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register. - PSU_DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN 0x1 - - If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register - Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is - not associated with any particular command). - PSU_DDRC_PCFGW_3_WR_PORT_URGENT_EN 0x1 - - If set to 1, enables aging function for the write channel of the port. - PSU_DDRC_PCFGW_3_WR_PORT_AGING_EN 0x0 - - Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each - rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port - s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0 - the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno - be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For - ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch - ng. Note: The two LSBs of this register field are tied internally to 2'b00. - PSU_DDRC_PCFGW_3_WR_PORT_PRIORITY 0xf - - Port n Configuration Write Register - (OFFSET, MASK, VALUE) (0XFD070618, 0x000073FFU ,0x0000600FU) - RegMask = (DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGW_3_WR_PORT_URGENT_EN_MASK | DDRC_PCFGW_3_WR_PORT_AGING_EN_MASK | DDRC_PCFGW_3_WR_PORT_PRIORITY_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_SHIFT - | 0x00000001U << DDRC_PCFGW_3_WR_PORT_URGENT_EN_SHIFT - | 0x00000000U << DDRC_PCFGW_3_WR_PORT_AGING_EN_SHIFT - | 0x0000000FU << DDRC_PCFGW_3_WR_PORT_PRIORITY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGW_3_OFFSET ,0x000073FFU ,0x0000600FU); - /*############################################################################################################################ */ - - /*Register : PCTRL_3 @ 0XFD0706A0

- - Enables port n. - PSU_DDRC_PCTRL_3_PORT_EN 0x1 - - Port n Control Register - (OFFSET, MASK, VALUE) (0XFD0706A0, 0x00000001U ,0x00000001U) - RegMask = (DDRC_PCTRL_3_PORT_EN_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_PCTRL_3_PORT_EN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCTRL_3_OFFSET ,0x00000001U ,0x00000001U); - /*############################################################################################################################ */ - - /*Register : PCFGQOS0_3 @ 0XFD0706A4

- - This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf - gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is - disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. - PSU_DDRC_PCFGQOS0_3_RQOS_MAP_REGION1 0x1 - - This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi - urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i - disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. - PSU_DDRC_PCFGQOS0_3_RQOS_MAP_REGION0 0x0 - - Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d - al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio - ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc - values. - PSU_DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1 0x3 - - Port n Read QoS Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD0706A4, 0x0033000FU ,0x00100003U) - RegMask = (DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_MASK | DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_MASK | DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_SHIFT - | 0x00000000U << DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_SHIFT - | 0x00000003U << DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGQOS0_3_OFFSET ,0x0033000FU ,0x00100003U); - /*############################################################################################################################ */ - - /*Register : PCFGQOS1_3 @ 0XFD0706A8

- - Specifies the timeout value for transactions mapped to the red address queue. - PSU_DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR 0x0 - - Specifies the timeout value for transactions mapped to the blue address queue. - PSU_DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB 0x4f - - Port n Read QoS Configuration Register 1 - (OFFSET, MASK, VALUE) (0XFD0706A8, 0x07FF07FFU ,0x0000004FU) - RegMask = (DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_MASK | DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_SHIFT - | 0x0000004FU << DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGQOS1_3_OFFSET ,0x07FF07FFU ,0x0000004FU); - /*############################################################################################################################ */ - - /*Register : PCFGWQOS0_3 @ 0XFD0706AC

- - This bitfield indicates the traffic class of region 1. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2 - VPW_EN = 0) and traffic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW traffic. - PSU_DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1 0x1 - - This bitfield indicates the traffic class of region 0. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2 - VPW_EN = 0) and traffic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW traffic. - PSU_DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0 0x0 - - Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 14 which c - rresponds to awqos. Note that for PA, awqos values are used directly as port priorities, where the higher the value correspon - s to higher port priority. - PSU_DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL 0x3 - - Port n Write QoS Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD0706AC, 0x0033000FU ,0x00100003U) - RegMask = (DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_MASK | DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_MASK | DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_SHIFT - | 0x00000000U << DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_SHIFT - | 0x00000003U << DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGWQOS0_3_OFFSET ,0x0033000FU ,0x00100003U); - /*############################################################################################################################ */ - - /*Register : PCFGWQOS1_3 @ 0XFD0706B0

- - Specifies the timeout value for write transactions. - PSU_DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT 0x4f - - Port n Write QoS Configuration Register 1 - (OFFSET, MASK, VALUE) (0XFD0706B0, 0x000007FFU ,0x0000004FU) - RegMask = (DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_MASK | 0 ); - - RegVal = ((0x0000004FU << DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGWQOS1_3_OFFSET ,0x000007FFU ,0x0000004FU); - /*############################################################################################################################ */ - - /*Register : PCFGR_4 @ 0XFD0706C4

- - If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register. - PSU_DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN 0x1 - - If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG. - o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add - ess handshaking (it is not associated with any particular command). - PSU_DDRC_PCFGR_4_RD_PORT_URGENT_EN 0x1 - - If set to 1, enables aging function for the read channel of the port. - PSU_DDRC_PCFGR_4_RD_PORT_AGING_EN 0x0 - - Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g - ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority - will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre - ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the - aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st - ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w - ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D - RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: - he two LSBs of this register field are tied internally to 2'b00. - PSU_DDRC_PCFGR_4_RD_PORT_PRIORITY 0xf - - Port n Configuration Read Register - (OFFSET, MASK, VALUE) (0XFD0706C4, 0x000073FFU ,0x0000600FU) - RegMask = (DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGR_4_RD_PORT_URGENT_EN_MASK | DDRC_PCFGR_4_RD_PORT_AGING_EN_MASK | DDRC_PCFGR_4_RD_PORT_PRIORITY_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_SHIFT - | 0x00000001U << DDRC_PCFGR_4_RD_PORT_URGENT_EN_SHIFT - | 0x00000000U << DDRC_PCFGR_4_RD_PORT_AGING_EN_SHIFT - | 0x0000000FU << DDRC_PCFGR_4_RD_PORT_PRIORITY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGR_4_OFFSET ,0x000073FFU ,0x0000600FU); - /*############################################################################################################################ */ - - /*Register : PCFGW_4 @ 0XFD0706C8

- - If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register. - PSU_DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN 0x1 - - If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register - Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is - not associated with any particular command). - PSU_DDRC_PCFGW_4_WR_PORT_URGENT_EN 0x1 - - If set to 1, enables aging function for the write channel of the port. - PSU_DDRC_PCFGW_4_WR_PORT_AGING_EN 0x0 - - Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each - rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port - s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0 - the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno - be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For - ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch - ng. Note: The two LSBs of this register field are tied internally to 2'b00. - PSU_DDRC_PCFGW_4_WR_PORT_PRIORITY 0xf - - Port n Configuration Write Register - (OFFSET, MASK, VALUE) (0XFD0706C8, 0x000073FFU ,0x0000600FU) - RegMask = (DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGW_4_WR_PORT_URGENT_EN_MASK | DDRC_PCFGW_4_WR_PORT_AGING_EN_MASK | DDRC_PCFGW_4_WR_PORT_PRIORITY_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_SHIFT - | 0x00000001U << DDRC_PCFGW_4_WR_PORT_URGENT_EN_SHIFT - | 0x00000000U << DDRC_PCFGW_4_WR_PORT_AGING_EN_SHIFT - | 0x0000000FU << DDRC_PCFGW_4_WR_PORT_PRIORITY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGW_4_OFFSET ,0x000073FFU ,0x0000600FU); - /*############################################################################################################################ */ - - /*Register : PCTRL_4 @ 0XFD070750

- - Enables port n. - PSU_DDRC_PCTRL_4_PORT_EN 0x1 - - Port n Control Register - (OFFSET, MASK, VALUE) (0XFD070750, 0x00000001U ,0x00000001U) - RegMask = (DDRC_PCTRL_4_PORT_EN_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_PCTRL_4_PORT_EN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCTRL_4_OFFSET ,0x00000001U ,0x00000001U); - /*############################################################################################################################ */ - - /*Register : PCFGQOS0_4 @ 0XFD070754

- - This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf - gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is - disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. - PSU_DDRC_PCFGQOS0_4_RQOS_MAP_REGION1 0x1 - - This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi - urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i - disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. - PSU_DDRC_PCFGQOS0_4_RQOS_MAP_REGION0 0x0 - - Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d - al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio - ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc - values. - PSU_DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1 0x3 - - Port n Read QoS Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD070754, 0x0033000FU ,0x00100003U) - RegMask = (DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_MASK | DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_MASK | DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_SHIFT - | 0x00000000U << DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_SHIFT - | 0x00000003U << DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGQOS0_4_OFFSET ,0x0033000FU ,0x00100003U); - /*############################################################################################################################ */ - - /*Register : PCFGQOS1_4 @ 0XFD070758

- - Specifies the timeout value for transactions mapped to the red address queue. - PSU_DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR 0x0 - - Specifies the timeout value for transactions mapped to the blue address queue. - PSU_DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB 0x4f - - Port n Read QoS Configuration Register 1 - (OFFSET, MASK, VALUE) (0XFD070758, 0x07FF07FFU ,0x0000004FU) - RegMask = (DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_MASK | DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_SHIFT - | 0x0000004FU << DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGQOS1_4_OFFSET ,0x07FF07FFU ,0x0000004FU); - /*############################################################################################################################ */ - - /*Register : PCFGWQOS0_4 @ 0XFD07075C

- - This bitfield indicates the traffic class of region 1. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2 - VPW_EN = 0) and traffic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW traffic. - PSU_DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1 0x1 - - This bitfield indicates the traffic class of region 0. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2 - VPW_EN = 0) and traffic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW traffic. - PSU_DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0 0x0 - - Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 14 which c - rresponds to awqos. Note that for PA, awqos values are used directly as port priorities, where the higher the value correspon - s to higher port priority. - PSU_DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL 0x3 - - Port n Write QoS Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD07075C, 0x0033000FU ,0x00100003U) - RegMask = (DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_MASK | DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_MASK | DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_SHIFT - | 0x00000000U << DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_SHIFT - | 0x00000003U << DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGWQOS0_4_OFFSET ,0x0033000FU ,0x00100003U); - /*############################################################################################################################ */ - - /*Register : PCFGWQOS1_4 @ 0XFD070760

- - Specifies the timeout value for write transactions. - PSU_DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT 0x4f - - Port n Write QoS Configuration Register 1 - (OFFSET, MASK, VALUE) (0XFD070760, 0x000007FFU ,0x0000004FU) - RegMask = (DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_MASK | 0 ); - - RegVal = ((0x0000004FU << DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGWQOS1_4_OFFSET ,0x000007FFU ,0x0000004FU); - /*############################################################################################################################ */ - - /*Register : PCFGR_5 @ 0XFD070774

- - If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register. - PSU_DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN 0x0 - - If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG. - o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add - ess handshaking (it is not associated with any particular command). - PSU_DDRC_PCFGR_5_RD_PORT_URGENT_EN 0x1 - - If set to 1, enables aging function for the read channel of the port. - PSU_DDRC_PCFGR_5_RD_PORT_AGING_EN 0x0 - - Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g - ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority - will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre - ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the - aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st - ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w - ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D - RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: - he two LSBs of this register field are tied internally to 2'b00. - PSU_DDRC_PCFGR_5_RD_PORT_PRIORITY 0xf - - Port n Configuration Read Register - (OFFSET, MASK, VALUE) (0XFD070774, 0x000073FFU ,0x0000200FU) - RegMask = (DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGR_5_RD_PORT_URGENT_EN_MASK | DDRC_PCFGR_5_RD_PORT_AGING_EN_MASK | DDRC_PCFGR_5_RD_PORT_PRIORITY_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_SHIFT - | 0x00000001U << DDRC_PCFGR_5_RD_PORT_URGENT_EN_SHIFT - | 0x00000000U << DDRC_PCFGR_5_RD_PORT_AGING_EN_SHIFT - | 0x0000000FU << DDRC_PCFGR_5_RD_PORT_PRIORITY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGR_5_OFFSET ,0x000073FFU ,0x0000200FU); - /*############################################################################################################################ */ - - /*Register : PCFGW_5 @ 0XFD070778

- - If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register. - PSU_DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN 0x1 - - If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register - Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is - not associated with any particular command). - PSU_DDRC_PCFGW_5_WR_PORT_URGENT_EN 0x1 - - If set to 1, enables aging function for the write channel of the port. - PSU_DDRC_PCFGW_5_WR_PORT_AGING_EN 0x0 - - Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each - rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port - s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0 - the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno - be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For - ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch - ng. Note: The two LSBs of this register field are tied internally to 2'b00. - PSU_DDRC_PCFGW_5_WR_PORT_PRIORITY 0xf - - Port n Configuration Write Register - (OFFSET, MASK, VALUE) (0XFD070778, 0x000073FFU ,0x0000600FU) - RegMask = (DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGW_5_WR_PORT_URGENT_EN_MASK | DDRC_PCFGW_5_WR_PORT_AGING_EN_MASK | DDRC_PCFGW_5_WR_PORT_PRIORITY_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_SHIFT - | 0x00000001U << DDRC_PCFGW_5_WR_PORT_URGENT_EN_SHIFT - | 0x00000000U << DDRC_PCFGW_5_WR_PORT_AGING_EN_SHIFT - | 0x0000000FU << DDRC_PCFGW_5_WR_PORT_PRIORITY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGW_5_OFFSET ,0x000073FFU ,0x0000600FU); - /*############################################################################################################################ */ - - /*Register : PCTRL_5 @ 0XFD070800

- - Enables port n. - PSU_DDRC_PCTRL_5_PORT_EN 0x1 - - Port n Control Register - (OFFSET, MASK, VALUE) (0XFD070800, 0x00000001U ,0x00000001U) - RegMask = (DDRC_PCTRL_5_PORT_EN_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_PCTRL_5_PORT_EN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCTRL_5_OFFSET ,0x00000001U ,0x00000001U); - /*############################################################################################################################ */ - - /*Register : PCFGQOS0_5 @ 0XFD070804

- - This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf - gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is - disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. - PSU_DDRC_PCFGQOS0_5_RQOS_MAP_REGION1 0x1 - - This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi - urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i - disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. - PSU_DDRC_PCFGQOS0_5_RQOS_MAP_REGION0 0x0 - - Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d - al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio - ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc - values. - PSU_DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1 0x3 - - Port n Read QoS Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD070804, 0x0033000FU ,0x00100003U) - RegMask = (DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_MASK | DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_MASK | DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_SHIFT - | 0x00000000U << DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_SHIFT - | 0x00000003U << DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGQOS0_5_OFFSET ,0x0033000FU ,0x00100003U); - /*############################################################################################################################ */ - - /*Register : PCFGQOS1_5 @ 0XFD070808

- - Specifies the timeout value for transactions mapped to the red address queue. - PSU_DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR 0x0 - - Specifies the timeout value for transactions mapped to the blue address queue. - PSU_DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB 0x4f - - Port n Read QoS Configuration Register 1 - (OFFSET, MASK, VALUE) (0XFD070808, 0x07FF07FFU ,0x0000004FU) - RegMask = (DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_MASK | DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_SHIFT - | 0x0000004FU << DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGQOS1_5_OFFSET ,0x07FF07FFU ,0x0000004FU); - /*############################################################################################################################ */ - - /*Register : PCFGWQOS0_5 @ 0XFD07080C

- - This bitfield indicates the traffic class of region 1. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2 - VPW_EN = 0) and traffic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW traffic. - PSU_DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1 0x1 - - This bitfield indicates the traffic class of region 0. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2 - VPW_EN = 0) and traffic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW traffic. - PSU_DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0 0x0 - - Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 14 which c - rresponds to awqos. Note that for PA, awqos values are used directly as port priorities, where the higher the value correspon - s to higher port priority. - PSU_DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL 0x3 - - Port n Write QoS Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD07080C, 0x0033000FU ,0x00100003U) - RegMask = (DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_MASK | DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_MASK | DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_SHIFT - | 0x00000000U << DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_SHIFT - | 0x00000003U << DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGWQOS0_5_OFFSET ,0x0033000FU ,0x00100003U); - /*############################################################################################################################ */ - - /*Register : PCFGWQOS1_5 @ 0XFD070810

- - Specifies the timeout value for write transactions. - PSU_DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT 0x4f - - Port n Write QoS Configuration Register 1 - (OFFSET, MASK, VALUE) (0XFD070810, 0x000007FFU ,0x0000004FU) - RegMask = (DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_MASK | 0 ); - - RegVal = ((0x0000004FU << DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGWQOS1_5_OFFSET ,0x000007FFU ,0x0000004FU); - /*############################################################################################################################ */ - - /*Register : SARBASE0 @ 0XFD070F04

- - Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x] and araddr[UMCTL2_A_ADDRW-1:x] where x is determine - by the minimum block size parameter UMCTL2_SARMINSIZE: (x=log2(block size)). - PSU_DDRC_SARBASE0_BASE_ADDR 0x0 - - SAR Base Address Register n - (OFFSET, MASK, VALUE) (0XFD070F04, 0x000001FFU ,0x00000000U) - RegMask = (DDRC_SARBASE0_BASE_ADDR_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_SARBASE0_BASE_ADDR_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_SARBASE0_OFFSET ,0x000001FFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : SARSIZE0 @ 0XFD070F08

- - Number of blocks for address region n. This register determines the total size of the region in multiples of minimum block si - e as specified by the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded as number of blocks = nblocks + 1. - or example, if register is programmed to 0, region will have 1 block. - PSU_DDRC_SARSIZE0_NBLOCKS 0x0 - - SAR Size Register n - (OFFSET, MASK, VALUE) (0XFD070F08, 0x000000FFU ,0x00000000U) - RegMask = (DDRC_SARSIZE0_NBLOCKS_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_SARSIZE0_NBLOCKS_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_SARSIZE0_OFFSET ,0x000000FFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : SARBASE1 @ 0XFD070F0C

- - Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x] and araddr[UMCTL2_A_ADDRW-1:x] where x is determine - by the minimum block size parameter UMCTL2_SARMINSIZE: (x=log2(block size)). - PSU_DDRC_SARBASE1_BASE_ADDR 0x10 - - SAR Base Address Register n - (OFFSET, MASK, VALUE) (0XFD070F0C, 0x000001FFU ,0x00000010U) - RegMask = (DDRC_SARBASE1_BASE_ADDR_MASK | 0 ); - - RegVal = ((0x00000010U << DDRC_SARBASE1_BASE_ADDR_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_SARBASE1_OFFSET ,0x000001FFU ,0x00000010U); - /*############################################################################################################################ */ - - /*Register : SARSIZE1 @ 0XFD070F10

- - Number of blocks for address region n. This register determines the total size of the region in multiples of minimum block si - e as specified by the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded as number of blocks = nblocks + 1. - or example, if register is programmed to 0, region will have 1 block. - PSU_DDRC_SARSIZE1_NBLOCKS 0xf - - SAR Size Register n - (OFFSET, MASK, VALUE) (0XFD070F10, 0x000000FFU ,0x0000000FU) - RegMask = (DDRC_SARSIZE1_NBLOCKS_MASK | 0 ); +unsigned long psu_ddr_init_data(void) +{ + /* + * DDR INITIALIZATION + */ + /* + * DDR CONTROLLER RESET + */ + /* + * Register : RST_DDR_SS @ 0XFD1A0108 + + * DDR block level reset inside of the DDR Sub System + * PSU_CRF_APB_RST_DDR_SS_DDR_RESET 0X1 + + * DDR sub system block level reset + * (OFFSET, MASK, VALUE) (0XFD1A0108, 0x00000008U ,0x00000008U) + */ + PSU_Mask_Write(CRF_APB_RST_DDR_SS_OFFSET, 0x00000008U, 0x00000008U); +/*##################################################################### */ + + /* + * Register : MSTR @ 0XFD070000 + + * Indicates the configuration of the device used in the system. - 00 - x4 + * device - 01 - x8 device - 10 - x16 device - 11 - x32 device + * PSU_DDRC_MSTR_DEVICE_CONFIG 0x1 + + * Choose which registers are used. - 0 - Original registers - 1 - Shadow r + * egisters + * PSU_DDRC_MSTR_FREQUENCY_MODE 0x0 + + * Only present for multi-rank configurations. Each bit represents one rank + * . For two-rank configurations, only bits[25:24] are present. - 1 - popul + * ated - 0 - unpopulated LSB is the lowest rank number. For 2 ranks follow + * ing combinations are legal: - 01 - One rank - 11 - Two ranks - Others - + * Reserved. For 4 ranks following combinations are legal: - 0001 - One ran + * k - 0011 - Two ranks - 1111 - Four ranks + * PSU_DDRC_MSTR_ACTIVE_RANKS 0x1 + + * SDRAM burst length used: - 0001 - Burst length of 2 (only supported for + * mDDR) - 0010 - Burst length of 4 - 0100 - Burst length of 8 - 1000 - Bur + * st length of 16 (only supported for mDDR, LPDDR2, and LPDDR4) All other + * values are reserved. This controls the burst size used to access the SDR + * AM. This must match the burst length mode register setting in the SDRAM. + * (For BC4/8 on-the-fly mode of DDR3 and DDR4, set this field to 0x0100) + * Burst length of 2 is not supported with AXI ports when MEMC_BURST_LENGTH + * is 8. Burst length of 2 is only supported with MEMC_FREQ_RATIO = 1 + * PSU_DDRC_MSTR_BURST_RDWR 0x4 + + * Set to 1 when the uMCTL2 and DRAM has to be put in DLL-off mode for low + * frequency operation. Set to 0 to put uMCTL2 and DRAM in DLL-on mode for + * normal frequency operation. If DDR4 CRC/parity retry is enabled (CRCPARC + * TL1.crc_parity_retry_enable = 1), dll_off_mode is not supported, and thi + * s bit must be set to '0'. + * PSU_DDRC_MSTR_DLL_OFF_MODE 0x0 + + * Selects proportion of DQ bus width that is used by the SDRAM - 00 - Full + * DQ bus width to SDRAM - 01 - Half DQ bus width to SDRAM - 10 - Quarter + * DQ bus width to SDRAM - 11 - Reserved. Note that half bus width mode is + * only supported when the SDRAM bus width is a multiple of 16, and quarter + * bus width mode is only supported when the SDRAM bus width is a multiple + * of 32 and the configuration parameter MEMC_QBUS_SUPPORT is set. Bus wid + * th refers to DQ bus width (excluding any ECC width). + * PSU_DDRC_MSTR_DATA_BUS_WIDTH 0x0 + + * 1 indicates put the DRAM in geardown mode (2N) and 0 indicates put the D + * RAM in normal mode (1N). This register can be changed, only when the Con + * troller is in self-refresh mode. This signal must be set the same value + * as MR3 bit A3. Note: Geardown mode is not supported if the configuration + * parameter MEMC_CMD_RTN2IDLE is set + * PSU_DDRC_MSTR_GEARDOWN_MODE 0x0 + + * If 1, then uMCTL2 uses 2T timing. Otherwise, uses 1T timing. In 2T timin + * g, all command signals (except chip select) are held for 2 clocks on the + * SDRAM bus. Chip select is asserted on the second cycle of the command N + * ote: 2T timing is not supported in LPDDR2/LPDDR3/LPDDR4 mode Note: 2T ti + * ming is not supported if the configuration parameter MEMC_CMD_RTN2IDLE i + * s set Note: 2T timing is not supported in DDR4 geardown mode. + * PSU_DDRC_MSTR_EN_2T_TIMING_MODE 0x0 + + * When set, enable burst-chop in DDR3/DDR4. Burst Chop for Reads is exerci + * sed only in HIF configurations (UMCTL2_INCL_ARB not set) and if in full + * bus width mode (MSTR.data_bus_width = 00). Burst Chop for Writes is exer + * cised only if Partial Writes enabled (UMCTL2_PARTIAL_WR=1) and if CRC is + * disabled (CRCPARCTL1.crc_enable = 0). If DDR4 CRC/parity retry is enabl + * ed (CRCPARCTL1.crc_parity_retry_enable = 1), burst chop is not supported + * , and this bit must be set to '0' + * PSU_DDRC_MSTR_BURSTCHOP 0x0 + + * Select LPDDR4 SDRAM - 1 - LPDDR4 SDRAM device in use. - 0 - non-LPDDR4 d + * evice in use Present only in designs configured to support LPDDR4. + * PSU_DDRC_MSTR_LPDDR4 0x0 + + * Select DDR4 SDRAM - 1 - DDR4 SDRAM device in use. - 0 - non-DDR4 device + * in use Present only in designs configured to support DDR4. + * PSU_DDRC_MSTR_DDR4 0x1 + + * Select LPDDR3 SDRAM - 1 - LPDDR3 SDRAM device in use. - 0 - non-LPDDR3 d + * evice in use Present only in designs configured to support LPDDR3. + * PSU_DDRC_MSTR_LPDDR3 0x0 + + * Select LPDDR2 SDRAM - 1 - LPDDR2 SDRAM device in use. - 0 - non-LPDDR2 d + * evice in use Present only in designs configured to support LPDDR2. + * PSU_DDRC_MSTR_LPDDR2 0x0 + + * Select DDR3 SDRAM - 1 - DDR3 SDRAM device in use - 0 - non-DDR3 SDRAM de + * vice in use Only present in designs that support DDR3. + * PSU_DDRC_MSTR_DDR3 0x0 + + * Master Register + * (OFFSET, MASK, VALUE) (0XFD070000, 0xE30FBE3DU ,0x41040010U) + */ + PSU_Mask_Write(DDRC_MSTR_OFFSET, 0xE30FBE3DU, 0x41040010U); +/*##################################################################### */ + + /* + * Register : MRCTRL0 @ 0XFD070010 + + * Setting this register bit to 1 triggers a mode register read or write op + * eration. When the MR operation is complete, the uMCTL2 automatically cle + * ars this bit. The other register fields of this register must be written + * in a separate APB transaction, before setting this mr_wr bit. It is rec + * ommended NOT to set this signal if in Init, Deep power-down or MPSM oper + * ating modes. + * PSU_DDRC_MRCTRL0_MR_WR 0x0 + + * Address of the mode register that is to be written to. - 0000 - MR0 - 00 + * 01 - MR1 - 0010 - MR2 - 0011 - MR3 - 0100 - MR4 - 0101 - MR5 - 0110 - MR + * 6 - 0111 - MR7 Don't Care for LPDDR2/LPDDR3/LPDDR4 (see MRCTRL1.mr_data + * for mode register addressing in LPDDR2/LPDDR3/LPDDR4) This signal is als + * o used for writing to control words of RDIMMs. In that case, it correspo + * nds to the bank address bits sent to the RDIMM In case of DDR4, the bit[ + * 3:2] corresponds to the bank group bits. Therefore, the bit[3] as well a + * s the bit[2:0] must be set to an appropriate value which is considered b + * oth the Address Mirroring of UDIMMs/RDIMMs and the Output Inversion of R + * DIMMs. + * PSU_DDRC_MRCTRL0_MR_ADDR 0x0 + + * Controls which rank is accessed by MRCTRL0.mr_wr. Normally, it is desire + * d to access all ranks, so all bits should be set to 1. However, for mult + * i-rank UDIMMs/RDIMMs which implement address mirroring, it may be necess + * ary to access ranks individually. Examples (assume uMCTL2 is configured + * for 4 ranks): - 0x1 - select rank 0 only - 0x2 - select rank 1 only - 0x + * 5 - select ranks 0 and 2 - 0xA - select ranks 1 and 3 - 0xF - select ran + * ks 0, 1, 2 and 3 + * PSU_DDRC_MRCTRL0_MR_RANK 0x3 + + * Indicates whether Software intervention is allowed via MRCTRL0/MRCTRL1 b + * efore automatic SDRAM initialization routine or not. For DDR4, this bit + * can be used to initialize the DDR4 RCD (MR7) before automatic SDRAM init + * ialization. For LPDDR4, this bit can be used to program additional mode + * registers before automatic SDRAM initialization if necessary. Note: This + * must be cleared to 0 after completing Software operation. Otherwise, SD + * RAM initialization routine will not re-start. - 0 - Software interventio + * n is not allowed - 1 - Software intervention is allowed + * PSU_DDRC_MRCTRL0_SW_INIT_INT 0x0 + + * Indicates whether the mode register operation is MRS in PDA mode or not + * - 0 - MRS - 1 - MRS in Per DRAM Addressability mode + * PSU_DDRC_MRCTRL0_PDA_EN 0x0 + + * Indicates whether the mode register operation is MRS or WR/RD for MPR (o + * nly supported for DDR4) - 0 - MRS - 1 - WR/RD for MPR + * PSU_DDRC_MRCTRL0_MPR_EN 0x0 + + * Indicates whether the mode register operation is read or write. Only use + * d for LPDDR2/LPDDR3/LPDDR4/DDR4. - 0 - Write - 1 - Read + * PSU_DDRC_MRCTRL0_MR_TYPE 0x0 + + * Mode Register Read/Write Control Register 0. Note: Do not enable more th + * an one of the following fields simultaneously: - sw_init_int - pda_en - + * mpr_en + * (OFFSET, MASK, VALUE) (0XFD070010, 0x8000F03FU ,0x00000030U) + */ + PSU_Mask_Write(DDRC_MRCTRL0_OFFSET, 0x8000F03FU, 0x00000030U); +/*##################################################################### */ + + /* + * Register : DERATEEN @ 0XFD070020 + + * Derate value of tRC for LPDDR4 - 0 - Derating uses +1. - 1 - Derating us + * es +2. - 2 - Derating uses +3. - 3 - Derating uses +4. Present only in d + * esigns configured to support LPDDR4. The required number of cycles for d + * erating can be determined by dividing 3.75ns by the core_ddrc_core_clk p + * eriod, and rounding up the next integer. + * PSU_DDRC_DERATEEN_RC_DERATE_VALUE 0x2 + + * Derate byte Present only in designs configured to support LPDDR2/LPDDR3/ + * LPDDR4 Indicates which byte of the MRR data is used for derating. The ma + * ximum valid value depends on MEMC_DRAM_TOTAL_DATA_WIDTH. + * PSU_DDRC_DERATEEN_DERATE_BYTE 0x0 + + * Derate value - 0 - Derating uses +1. - 1 - Derating uses +2. Present onl + * y in designs configured to support LPDDR2/LPDDR3/LPDDR4 Set to 0 for all + * LPDDR2 speed grades as derating value of +1.875 ns is less than a core_ + * ddrc_core_clk period. Can be 0 or 1 for LPDDR3/LPDDR4, depending if +1.8 + * 75 ns is less than a core_ddrc_core_clk period or not. + * PSU_DDRC_DERATEEN_DERATE_VALUE 0x0 + + * Enables derating - 0 - Timing parameter derating is disabled - 1 - Timin + * g parameter derating is enabled using MR4 read value. Present only in de + * signs configured to support LPDDR2/LPDDR3/LPDDR4 This field must be set + * to '0' for non-LPDDR2/LPDDR3/LPDDR4 mode. + * PSU_DDRC_DERATEEN_DERATE_ENABLE 0x0 + + * Temperature Derate Enable Register + * (OFFSET, MASK, VALUE) (0XFD070020, 0x000003F3U ,0x00000200U) + */ + PSU_Mask_Write(DDRC_DERATEEN_OFFSET, 0x000003F3U, 0x00000200U); +/*##################################################################### */ + + /* + * Register : DERATEINT @ 0XFD070024 + + * Interval between two MR4 reads, used to derate the timing parameters. Pr + * esent only in designs configured to support LPDDR2/LPDDR3/LPDDR4. This r + * egister must not be set to zero + * PSU_DDRC_DERATEINT_MR4_READ_INTERVAL 0x800000 + + * Temperature Derate Interval Register + * (OFFSET, MASK, VALUE) (0XFD070024, 0xFFFFFFFFU ,0x00800000U) + */ + PSU_Mask_Write(DDRC_DERATEINT_OFFSET, 0xFFFFFFFFU, 0x00800000U); +/*##################################################################### */ + + /* + * Register : PWRCTL @ 0XFD070030 + + * Self refresh state is an intermediate state to enter to Self refresh pow + * er down state or exit Self refresh power down state for LPDDR4. This reg + * ister controls transition from the Self refresh state. - 1 - Prohibit tr + * ansition from Self refresh state - 0 - Allow transition from Self refres + * h state + * PSU_DDRC_PWRCTL_STAY_IN_SELFREF 0x0 + + * A value of 1 to this register causes system to move to Self Refresh stat + * e immediately, as long as it is not in INIT or DPD/MPSM operating_mode. + * This is referred to as Software Entry/Exit to Self Refresh. - 1 - Softwa + * re Entry to Self Refresh - 0 - Software Exit from Self Refresh + * PSU_DDRC_PWRCTL_SELFREF_SW 0x0 + + * When this is 1, the uMCTL2 puts the SDRAM into maximum power saving mode + * when the transaction store is empty. This register must be reset to '0' + * to bring uMCTL2 out of maximum power saving mode. Present only in desig + * ns configured to support DDR4. For non-DDR4, this register should not be + * set to 1. Note that MPSM is not supported when using a DWC DDR PHY, if + * the PHY parameter DWC_AC_CS_USE is disabled, as the MPSM exit sequence r + * equires the chip-select signal to toggle. FOR PERFORMANCE ONLY. + * PSU_DDRC_PWRCTL_MPSM_EN 0x0 + + * Enable the assertion of dfi_dram_clk_disable whenever a clock is not req + * uired by the SDRAM. If set to 0, dfi_dram_clk_disable is never asserted. + * Assertion of dfi_dram_clk_disable is as follows: In DDR2/DDR3, can only + * be asserted in Self Refresh. In DDR4, can be asserted in following: - i + * n Self Refresh. - in Maximum Power Saving Mode In mDDR/LPDDR2/LPDDR3, ca + * n be asserted in following: - in Self Refresh - in Power Down - in Deep + * Power Down - during Normal operation (Clock Stop) In LPDDR4, can be asse + * rted in following: - in Self Refresh Power Down - in Power Down - during + * Normal operation (Clock Stop) + * PSU_DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE 0x0 + + * When this is 1, uMCTL2 puts the SDRAM into deep power-down mode when the + * transaction store is empty. This register must be reset to '0' to bring + * uMCTL2 out of deep power-down mode. Controller performs automatic SDRAM + * initialization on deep power-down exit. Present only in designs configu + * red to support mDDR or LPDDR2 or LPDDR3. For non-mDDR/non-LPDDR2/non-LPD + * DR3, this register should not be set to 1. FOR PERFORMANCE ONLY. + * PSU_DDRC_PWRCTL_DEEPPOWERDOWN_EN 0x0 + + * If true then the uMCTL2 goes into power-down after a programmable number + * of cycles 'maximum idle clocks before power down' (PWRTMG.powerdown_to_ + * x32). This register bit may be re-programmed during the course of normal + * operation. + * PSU_DDRC_PWRCTL_POWERDOWN_EN 0x0 + + * If true then the uMCTL2 puts the SDRAM into Self Refresh after a program + * mable number of cycles 'maximum idle clocks before Self Refresh (PWRTMG. + * selfref_to_x32)'. This register bit may be re-programmed during the cour + * se of normal operation. + * PSU_DDRC_PWRCTL_SELFREF_EN 0x0 + + * Low Power Control Register + * (OFFSET, MASK, VALUE) (0XFD070030, 0x0000007FU ,0x00000000U) + */ + PSU_Mask_Write(DDRC_PWRCTL_OFFSET, 0x0000007FU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : PWRTMG @ 0XFD070034 + + * After this many clocks of NOP or deselect the uMCTL2 automatically puts + * the SDRAM into Self Refresh. This must be enabled in the PWRCTL.selfref_ + * en. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY. + * PSU_DDRC_PWRTMG_SELFREF_TO_X32 0x40 + + * Minimum deep power-down time. For mDDR, value from the JEDEC specificati + * on is 0 as mDDR exits from deep power-down mode immediately after PWRCTL + * .deeppowerdown_en is de-asserted. For LPDDR2/LPDDR3, value from the JEDE + * C specification is 500us. Unit: Multiples of 4096 clocks. Present only i + * n designs configured to support mDDR, LPDDR2 or LPDDR3. FOR PERFORMANCE + * ONLY. + * PSU_DDRC_PWRTMG_T_DPD_X4096 0x84 + + * After this many clocks of NOP or deselect the uMCTL2 automatically puts + * the SDRAM into power-down. This must be enabled in the PWRCTL.powerdown_ + * en. Unit: Multiples of 32 clocks FOR PERFORMANCE ONLY. + * PSU_DDRC_PWRTMG_POWERDOWN_TO_X32 0x10 + + * Low Power Timing Register + * (OFFSET, MASK, VALUE) (0XFD070034, 0x00FFFF1FU ,0x00408410U) + */ + PSU_Mask_Write(DDRC_PWRTMG_OFFSET, 0x00FFFF1FU, 0x00408410U); +/*##################################################################### */ + + /* + * Register : RFSHCTL0 @ 0XFD070050 + + * Threshold value in number of clock cycles before the critical refresh or + * page timer expires. A critical refresh is to be issued before this thre + * shold is reached. It is recommended that this not be changed from the de + * fault value, currently shown as 0x2. It must always be less than interna + * lly used t_rfc_nom_x32. Note that, in LPDDR2/LPDDR3/LPDDR4, internally u + * sed t_rfc_nom_x32 may be equal to RFSHTMG.t_rfc_nom_x32>>2 if derating i + * s enabled (DERATEEN.derate_enable=1). Otherwise, internally used t_rfc_n + * om_x32 will be equal to RFSHTMG.t_rfc_nom_x32. Unit: Multiples of 32 clo + * cks. + * PSU_DDRC_RFSHCTL0_REFRESH_MARGIN 0x2 + + * If the refresh timer (tRFCnom, also known as tREFI) has expired at least + * once, but it has not expired (RFSHCTL0.refresh_burst+1) times yet, then + * a speculative refresh may be performed. A speculative refresh is a refr + * esh performed at a time when refresh would be useful, but before it is a + * bsolutely required. When the SDRAM bus is idle for a period of time dete + * rmined by this RFSHCTL0.refresh_to_x32 and the refresh timer has expired + * at least once since the last refresh, then a speculative refresh is per + * formed. Speculative refreshes continues successively until there are no + * refreshes pending or until new reads or writes are issued to the uMCTL2. + * FOR PERFORMANCE ONLY. + * PSU_DDRC_RFSHCTL0_REFRESH_TO_X32 0x10 + + * The programmed value + 1 is the number of refresh timeouts that is allow + * ed to accumulate before traffic is blocked and the refreshes are forced + * to execute. Closing pages to perform a refresh is a one-time penalty tha + * t must be paid for each group of refreshes. Therefore, performing refres + * hes in a burst reduces the per-refresh penalty of these page closings. H + * igher numbers for RFSHCTL.refresh_burst slightly increases utilization; + * lower numbers decreases the worst-case latency associated with refreshes + * . - 0 - single refresh - 1 - burst-of-2 refresh - 7 - burst-of-8 refresh + * For information on burst refresh feature refer to section 3.9 of DDR2 J + * EDEC specification - JESD79-2F.pdf. For DDR2/3, the refresh is always pe + * r-rank and not per-bank. The rank refresh can be accumulated over 8*tREF + * I cycles using the burst refresh feature. In DDR4 mode, according to Fin + * e Granularity feature, 8 refreshes can be postponed in 1X mode, 16 refre + * shes in 2X mode and 32 refreshes in 4X mode. If using PHY-initiated upda + * tes, care must be taken in the setting of RFSHCTL0.refresh_burst, to ens + * ure that tRFCmax is not violated due to a PHY-initiated update occurring + * shortly before a refresh burst was due. In this situation, the refresh + * burst will be delayed until the PHY-initiated update is complete. + * PSU_DDRC_RFSHCTL0_REFRESH_BURST 0x0 + + * - 1 - Per bank refresh; - 0 - All bank refresh. Per bank refresh allows + * traffic to flow to other banks. Per bank refresh is not supported by all + * LPDDR2 devices but should be supported by all LPDDR3/LPDDR4 devices. Pr + * esent only in designs configured to support LPDDR2/LPDDR3/LPDDR4 + * PSU_DDRC_RFSHCTL0_PER_BANK_REFRESH 0x0 + + * Refresh Control Register 0 + * (OFFSET, MASK, VALUE) (0XFD070050, 0x00F1F1F4U ,0x00210000U) + */ + PSU_Mask_Write(DDRC_RFSHCTL0_OFFSET, 0x00F1F1F4U, 0x00210000U); +/*##################################################################### */ + + /* + * Register : RFSHCTL1 @ 0XFD070054 + + * Refresh timer start for rank 1 (only present in multi-rank configuration + * s). This is useful in staggering the refreshes to multiple ranks to help + * traffic to proceed. This is explained in Refresh Controls section of ar + * chitecture chapter. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY. + * PSU_DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32 0x0 + + * Refresh timer start for rank 0 (only present in multi-rank configuration + * s). This is useful in staggering the refreshes to multiple ranks to help + * traffic to proceed. This is explained in Refresh Controls section of ar + * chitecture chapter. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY. + * PSU_DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32 0x0 + + * Refresh Control Register 1 + * (OFFSET, MASK, VALUE) (0XFD070054, 0x0FFF0FFFU ,0x00000000U) + */ + PSU_Mask_Write(DDRC_RFSHCTL1_OFFSET, 0x0FFF0FFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : RFSHCTL3 @ 0XFD070060 + + * Fine Granularity Refresh Mode - 000 - Fixed 1x (Normal mode) - 001 - Fix + * ed 2x - 010 - Fixed 4x - 101 - Enable on the fly 2x (not supported) - 11 + * 0 - Enable on the fly 4x (not supported) - Everything else - reserved No + * te: The on-the-fly modes is not supported in this version of the uMCTL2. + * Note: This must be set up while the Controller is in reset or while the + * Controller is in self-refresh mode. Changing this during normal operati + * on is not allowed. Making this a dynamic register will be supported in f + * uture version of the uMCTL2. + * PSU_DDRC_RFSHCTL3_REFRESH_MODE 0x0 + + * Toggle this signal (either from 0 to 1 or from 1 to 0) to indicate that + * the refresh register(s) have been updated. The value is automatically up + * dated when exiting reset, so it does not need to be toggled initially. + * PSU_DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL 0x0 + + * When '1', disable auto-refresh generated by the uMCTL2. When auto-refres + * h is disabled, the SoC core must generate refreshes using the registers + * reg_ddrc_rank0_refresh, reg_ddrc_rank1_refresh, reg_ddrc_rank2_refresh a + * nd reg_ddrc_rank3_refresh. When dis_auto_refresh transitions from 0 to 1 + * , any pending refreshes are immediately scheduled by the uMCTL2. If DDR4 + * CRC/parity retry is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), d + * isable auto-refresh is not supported, and this bit must be set to '0'. T + * his register field is changeable on the fly. + * PSU_DDRC_RFSHCTL3_DIS_AUTO_REFRESH 0x1 + + * Refresh Control Register 3 + * (OFFSET, MASK, VALUE) (0XFD070060, 0x00000073U ,0x00000001U) + */ + PSU_Mask_Write(DDRC_RFSHCTL3_OFFSET, 0x00000073U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : RFSHTMG @ 0XFD070064 + + * tREFI: Average time interval between refreshes per rank (Specification: + * 7.8us for DDR2, DDR3 and DDR4. See JEDEC specification for mDDR, LPDDR2, + * LPDDR3 and LPDDR4). For LPDDR2/LPDDR3/LPDDR4: - if using all-bank refre + * shes (RFSHCTL0.per_bank_refresh = 0), this register should be set to tRE + * FIab - if using per-bank refreshes (RFSHCTL0.per_bank_refresh = 1), this + * register should be set to tREFIpb For configurations with MEMC_FREQ_RAT + * IO=2, program this to (tREFI/2), no rounding up. In DDR4 mode, tREFI val + * ue is different depending on the refresh mode. The user should program t + * he appropriate value from the spec based on the value programmed in the + * refresh mode register. Note that RFSHTMG.t_rfc_nom_x32 * 32 must be grea + * ter than RFSHTMG.t_rfc_min, and RFSHTMG.t_rfc_nom_x32 must be greater th + * an 0x1. Unit: Multiples of 32 clocks. + * PSU_DDRC_RFSHTMG_T_RFC_NOM_X32 0x81 + + * Used only when LPDDR3 memory type is connected. Should only be changed w + * hen uMCTL2 is in reset. Specifies whether to use the tREFBW parameter (r + * equired by some LPDDR3 devices which comply with earlier versions of the + * LPDDR3 JEDEC specification) or not: - 0 - tREFBW parameter not used - 1 + * - tREFBW parameter used + * PSU_DDRC_RFSHTMG_LPDDR3_TREFBW_EN 0x1 + + * tRFC (min): Minimum time from refresh to refresh or activate. For MEMC_F + * REQ_RATIO=1 configurations, t_rfc_min should be set to RoundUp(tRFCmin/t + * CK). For MEMC_FREQ_RATIO=2 configurations, t_rfc_min should be set to Ro + * undUp(RoundUp(tRFCmin/tCK)/2). In LPDDR2/LPDDR3/LPDDR4 mode: - if using + * all-bank refreshes, the tRFCmin value in the above equations is equal to + * tRFCab - if using per-bank refreshes, the tRFCmin value in the above eq + * uations is equal to tRFCpb In DDR4 mode, the tRFCmin value in the above + * equations is different depending on the refresh mode (fixed 1X,2X,4X) an + * d the device density. The user should program the appropriate value from + * the spec based on the 'refresh_mode' and the device density that is use + * d. Unit: Clocks. + * PSU_DDRC_RFSHTMG_T_RFC_MIN 0x8b + + * Refresh Timing Register + * (OFFSET, MASK, VALUE) (0XFD070064, 0x0FFF83FFU ,0x0081808BU) + */ + PSU_Mask_Write(DDRC_RFSHTMG_OFFSET, 0x0FFF83FFU, 0x0081808BU); +/*##################################################################### */ + + /* + * Register : ECCCFG0 @ 0XFD070070 + + * Disable ECC scrubs. Valid only when ECCCFG0.ecc_mode = 3'b100 and MEMC_U + * SE_RMW is defined + * PSU_DDRC_ECCCFG0_DIS_SCRUB 0x1 + + * ECC mode indicator - 000 - ECC disabled - 100 - ECC enabled - SEC/DED ov + * er 1 beat - all other settings are reserved for future use + * PSU_DDRC_ECCCFG0_ECC_MODE 0x0 + + * ECC Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD070070, 0x00000017U ,0x00000010U) + */ + PSU_Mask_Write(DDRC_ECCCFG0_OFFSET, 0x00000017U, 0x00000010U); +/*##################################################################### */ + + /* + * Register : ECCCFG1 @ 0XFD070074 + + * Selects whether to poison 1 or 2 bits - if 0 -> 2-bit (uncorrectable) da + * ta poisoning, if 1 -> 1-bit (correctable) data poisoning, if ECCCFG1.dat + * a_poison_en=1 + * PSU_DDRC_ECCCFG1_DATA_POISON_BIT 0x0 + + * Enable ECC data poisoning - introduces ECC errors on writes to address s + * pecified by the ECCPOISONADDR0/1 registers + * PSU_DDRC_ECCCFG1_DATA_POISON_EN 0x0 + + * ECC Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD070074, 0x00000003U ,0x00000000U) + */ + PSU_Mask_Write(DDRC_ECCCFG1_OFFSET, 0x00000003U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : CRCPARCTL1 @ 0XFD0700C4 + + * The maximum number of DFI PHY clock cycles allowed from the assertion of + * the dfi_rddata_en signal to the assertion of each of the corresponding + * bits of the dfi_rddata_valid signal. This corresponds to the DFI timing + * parameter tphy_rdlat. Refer to PHY specification for correct value. This + * value it only used for detecting read data timeout when DDR4 retry is e + * nabled by CRCPARCTL1.crc_parity_retry_enable=1. Maximum supported value: + * - 1:1 Frequency mode : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_r + * dlat < 'd114 - 1:2 Frequency mode ANDAND DFITMG0.dfi_rddata_use_sdr == 1 + * : CRCPARCTL1.dfi_t_phy_rdlat < 64 - 1:2 Frequency mode ANDAND DFITMG0.d + * fi_rddata_use_sdr == 0 : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_ + * rdlat < 'd114 Unit: DFI Clocks + * PSU_DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT 0x10 + + * After a Parity or CRC error is flagged on dfi_alert_n signal, the softwa + * re has an option to read the mode registers in the DRAM before the hardw + * are begins the retry process - 1: Wait for software to read/write the mo + * de registers before hardware begins the retry. After software is done wi + * th its operations, it will clear the alert interrupt register bit - 0: H + * ardware can begin the retry right away after the dfi_alert_n pulse goes + * away. The value on this register is valid only when retry is enabled (PA + * RCTRL.crc_parity_retry_enable = 1) If this register is set to 1 and if t + * he software doesn't clear the interrupt register after handling the pari + * ty/CRC error, then the hardware will not begin the retry process and the + * system will hang. In the case of Parity/CRC error, there are two possib + * ilities when the software doesn't reset MR5[4] to 0. - (i) If 'Persisten + * t parity' mode register bit is NOT set: the commands sent during retry a + * nd normal operation are executed without parity checking. The value in t + * he Parity error log register MPR Page 1 is valid. - (ii) If 'Persistent + * parity' mode register bit is SET: Parity checking is done for commands s + * ent during retry and normal operation. If multiple errors occur before M + * R5[4] is cleared, the error log in MPR Page 1 should be treated as 'Don' + * t care'. + * PSU_DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW 0x1 + + * - 1: Enable command retry mechanism in case of C/A Parity or CRC error - + * 0: Disable command retry mechanism when C/A Parity or CRC features are + * enabled. Note that retry functionality is not supported if burst chop is + * enabled (MSTR.burstchop = 1) and/or disable auto-refresh is enabled (RF + * SHCTL3.dis_auto_refresh = 1) + * PSU_DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE 0x0 + + * CRC Calculation setting register - 1: CRC includes DM signal - 0: CRC no + * t includes DM signal Present only in designs configured to support DDR4. + * PSU_DDRC_CRCPARCTL1_CRC_INC_DM 0x0 + + * CRC enable Register - 1: Enable generation of CRC - 0: Disable generatio + * n of CRC The setting of this register should match the CRC mode register + * setting in the DRAM. + * PSU_DDRC_CRCPARCTL1_CRC_ENABLE 0x0 + + * C/A Parity enable register - 1: Enable generation of C/A parity and dete + * ction of C/A parity error - 0: Disable generation of C/A parity and disa + * ble detection of C/A parity error If RCD's parity error detection or SDR + * AM's parity detection is enabled, this register should be 1. + * PSU_DDRC_CRCPARCTL1_PARITY_ENABLE 0x0 + + * CRC Parity Control Register1 + * (OFFSET, MASK, VALUE) (0XFD0700C4, 0x3F000391U ,0x10000200U) + */ + PSU_Mask_Write(DDRC_CRCPARCTL1_OFFSET, 0x3F000391U, 0x10000200U); +/*##################################################################### */ + + /* + * Register : CRCPARCTL2 @ 0XFD0700C8 + + * Value from the DRAM spec indicating the maximum width of the dfi_alert_n + * pulse when a parity error occurs. Recommended values: - tPAR_ALERT_PW.M + * AX For configurations with MEMC_FREQ_RATIO=2, program this to tPAR_ALERT + * _PW.MAX/2 and round up to next integer value. Values of 0, 1 and 2 are i + * llegal. This value must be greater than CRCPARCTL2.t_crc_alert_pw_max. + * PSU_DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX 0x40 + + * Value from the DRAM spec indicating the maximum width of the dfi_alert_n + * pulse when a CRC error occurs. Recommended values: - tCRC_ALERT_PW.MAX + * For configurations with MEMC_FREQ_RATIO=2, program this to tCRC_ALERT_PW + * .MAX/2 and round up to next integer value. Values of 0, 1 and 2 are ille + * gal. This value must be less than CRCPARCTL2.t_par_alert_pw_max. + * PSU_DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX 0x5 + + * Indicates the maximum duration in number of DRAM clock cycles for which + * a command should be held in the Command Retry FIFO before it is popped o + * ut. Every location in the Command Retry FIFO has an associated down coun + * ting timer that will use this register as the start value. The down coun + * ting starts when a command is loaded into the FIFO. The timer counts dow + * n every 4 DRAM cycles. When the counter reaches zero, the entry is poppe + * d from the FIFO. All the counters are frozen, if a C/A Parity or CRC err + * or occurs before the counter reaches zero. The counter is reset to 0, af + * ter all the commands in the FIFO are retried. Recommended(minimum) value + * s: - Only C/A Parity is enabled. RoundUp((PHY Command Latency(DRAM CLK) + * + CAL + RDIMM delay + tPAR_ALERT_ON.max + tPAR_UNKNOWN + PHY Alert Laten + * cy(DRAM CLK) + board delay) / 4) + 2 - Both C/A Parity and CRC is enable + * d/ Only CRC is enabled. RoundUp((PHY Command Latency(DRAM CLK) + CAL + R + * DIMM delay + WL + 5(BL10)+ tCRC_ALERT.max + PHY Alert Latency(DRAM CLK) + * + board delay) / 4) + 2 Note 1: All value (e.g. tPAR_ALERT_ON) should be + * in terms of DRAM Clock and round up Note 2: Board delay(Command/Alert_n + * ) should be considered. Note 3: Use the worst case(longer) value for PHY + * Latencies/Board delay Note 4: The Recommended values are minimum value + * to be set. For mode detail, See 'Calculation of FIFO Depth' section. Max + * value can be set to this register is defined below: - MEMC_BURST_LENGTH + * == 16 Full bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 + * Full bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Half b + * us Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-4 Half bus Mod + * e (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-6 Quarter bus Mode (C + * RC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-8 Quarter bus Mode (CRC= + * ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-12 - MEMC_BURST_LENGTH != 16 + * Full bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-1 Full + * bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mod + * e (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mode (CRC + * =ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Quarter bus Mode (CRC=OFF + * ) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-4 Quarter bus Mode (CRC=ON) Ma + * x value = UMCTL2_RETRY_CMD_FIFO_DEPTH-6 Values of 0, 1 and 2 are illegal + * . + * PSU_DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4 0x1f + + * CRC Parity Control Register2 + * (OFFSET, MASK, VALUE) (0XFD0700C8, 0x01FF1F3FU ,0x0040051FU) + */ + PSU_Mask_Write(DDRC_CRCPARCTL2_OFFSET, 0x01FF1F3FU, 0x0040051FU); +/*##################################################################### */ + + /* + * Register : INIT0 @ 0XFD0700D0 + + * If lower bit is enabled the SDRAM initialization routine is skipped. The + * upper bit decides what state the controller starts up in when reset is + * removed - 00 - SDRAM Intialization routine is run after power-up - 01 - + * SDRAM Intialization routine is skipped after power-up. Controller starts + * up in Normal Mode - 11 - SDRAM Intialization routine is skipped after p + * ower-up. Controller starts up in Self-refresh Mode - 10 - SDRAM Intializ + * ation routine is run after power-up. Note: The only 2'b00 is supported f + * or LPDDR4 in this version of the uMCTL2. + * PSU_DDRC_INIT0_SKIP_DRAM_INIT 0x0 + + * Cycles to wait after driving CKE high to start the SDRAM initialization + * sequence. Unit: 1024 clocks. DDR2 typically requires a 400 ns delay, req + * uiring this value to be programmed to 2 at all clock speeds. LPDDR2/LPDD + * R3 typically requires this to be programmed for a delay of 200 us. LPDDR + * 4 typically requires this to be programmed for a delay of 2 us. For conf + * igurations with MEMC_FREQ_RATIO=2, program this to JEDEC spec value divi + * ded by 2, and round it up to next integer value. + * PSU_DDRC_INIT0_POST_CKE_X1024 0x2 + + * Cycles to wait after reset before driving CKE high to start the SDRAM in + * itialization sequence. Unit: 1024 clock cycles. DDR2 specifications typi + * cally require this to be programmed for a delay of >= 200 us. LPDDR2/LPD + * DR3: tINIT1 of 100 ns (min) LPDDR4: tINIT3 of 2 ms (min) For configurati + * ons with MEMC_FREQ_RATIO=2, program this to JEDEC spec value divided by + * 2, and round it up to next integer value. + * PSU_DDRC_INIT0_PRE_CKE_X1024 0x106 + + * SDRAM Initialization Register 0 + * (OFFSET, MASK, VALUE) (0XFD0700D0, 0xC3FF0FFFU ,0x00020106U) + */ + PSU_Mask_Write(DDRC_INIT0_OFFSET, 0xC3FF0FFFU, 0x00020106U); +/*##################################################################### */ + + /* + * Register : INIT1 @ 0XFD0700D4 + + * Number of cycles to assert SDRAM reset signal during init sequence. This + * is only present for designs supporting DDR3, DDR4 or LPDDR4 devices. Fo + * r use with a DDR PHY, this should be set to a minimum of 1 + * PSU_DDRC_INIT1_DRAM_RSTN_X1024 0x2 + + * Cycles to wait after completing the SDRAM initialization sequence before + * starting the dynamic scheduler. Unit: Counts of a global timer that pul + * ses every 32 clock cycles. There is no known specific requirement for th + * is; it may be set to zero. + * PSU_DDRC_INIT1_FINAL_WAIT_X32 0x0 + + * Wait period before driving the OCD complete command to SDRAM. Unit: Coun + * ts of a global timer that pulses every 32 clock cycles. There is no know + * n specific requirement for this; it may be set to zero. + * PSU_DDRC_INIT1_PRE_OCD_X32 0x0 + + * SDRAM Initialization Register 1 + * (OFFSET, MASK, VALUE) (0XFD0700D4, 0x01FF7F0FU ,0x00020000U) + */ + PSU_Mask_Write(DDRC_INIT1_OFFSET, 0x01FF7F0FU, 0x00020000U); +/*##################################################################### */ + + /* + * Register : INIT2 @ 0XFD0700D8 + + * Idle time after the reset command, tINIT4. Present only in designs confi + * gured to support LPDDR2. Unit: 32 clock cycles. + * PSU_DDRC_INIT2_IDLE_AFTER_RESET_X32 0x23 + + * Time to wait after the first CKE high, tINIT2. Present only in designs c + * onfigured to support LPDDR2/LPDDR3. Unit: 1 clock cycle. LPDDR2/LPDDR3 t + * ypically requires 5 x tCK delay. + * PSU_DDRC_INIT2_MIN_STABLE_CLOCK_X1 0x5 + + * SDRAM Initialization Register 2 + * (OFFSET, MASK, VALUE) (0XFD0700D8, 0x0000FF0FU ,0x00002305U) + */ + PSU_Mask_Write(DDRC_INIT2_OFFSET, 0x0000FF0FU, 0x00002305U); +/*##################################################################### */ + + /* + * Register : INIT3 @ 0XFD0700DC + + * DDR2: Value to write to MR register. Bit 8 is for DLL and the setting he + * re is ignored. The uMCTL2 sets this bit appropriately. DDR3/DDR4: Value + * loaded into MR0 register. mDDR: Value to write to MR register. LPDDR2/LP + * DDR3/LPDDR4 - Value to write to MR1 register + * PSU_DDRC_INIT3_MR 0x730 + + * DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setti + * ng in this register is ignored. The uMCTL2 sets those bits appropriately + * . DDR3/DDR4: Value to write to MR1 register Set bit 7 to 0. If PHY-evalu + * ation mode training is enabled, this bit is set appropriately by the uMC + * TL2 during write leveling. mDDR: Value to write to EMR register. LPDDR2/ + * LPDDR3/LPDDR4 - Value to write to MR2 register + * PSU_DDRC_INIT3_EMR 0x301 + + * SDRAM Initialization Register 3 + * (OFFSET, MASK, VALUE) (0XFD0700DC, 0xFFFFFFFFU ,0x07300301U) + */ + PSU_Mask_Write(DDRC_INIT3_OFFSET, 0xFFFFFFFFU, 0x07300301U); +/*##################################################################### */ + + /* + * Register : INIT4 @ 0XFD0700E0 + + * DDR2: Value to write to EMR2 register. DDR3/DDR4: Value to write to MR2 + * register LPDDR2/LPDDR3/LPDDR4: Value to write to MR3 register mDDR: Unus + * ed + * PSU_DDRC_INIT4_EMR2 0x20 + + * DDR2: Value to write to EMR3 register. DDR3/DDR4: Value to write to MR3 + * register mDDR/LPDDR2/LPDDR3: Unused LPDDR4: Value to write to MR13 regis + * ter + * PSU_DDRC_INIT4_EMR3 0x200 + + * SDRAM Initialization Register 4 + * (OFFSET, MASK, VALUE) (0XFD0700E0, 0xFFFFFFFFU ,0x00200200U) + */ + PSU_Mask_Write(DDRC_INIT4_OFFSET, 0xFFFFFFFFU, 0x00200200U); +/*##################################################################### */ + + /* + * Register : INIT5 @ 0XFD0700E4 + + * ZQ initial calibration, tZQINIT. Present only in designs configured to s + * upport DDR3 or DDR4 or LPDDR2/LPDDR3. Unit: 32 clock cycles. DDR3 typica + * lly requires 512 clocks. DDR4 requires 1024 clocks. LPDDR2/LPDDR3 requir + * es 1 us. + * PSU_DDRC_INIT5_DEV_ZQINIT_X32 0x21 + + * Maximum duration of the auto initialization, tINIT5. Present only in des + * igns configured to support LPDDR2/LPDDR3. LPDDR2/LPDDR3 typically requir + * es 10 us. + * PSU_DDRC_INIT5_MAX_AUTO_INIT_X1024 0x4 + + * SDRAM Initialization Register 5 + * (OFFSET, MASK, VALUE) (0XFD0700E4, 0x00FF03FFU ,0x00210004U) + */ + PSU_Mask_Write(DDRC_INIT5_OFFSET, 0x00FF03FFU, 0x00210004U); +/*##################################################################### */ + + /* + * Register : INIT6 @ 0XFD0700E8 + + * DDR4- Value to be loaded into SDRAM MR4 registers. Used in DDR4 designs + * only. + * PSU_DDRC_INIT6_MR4 0x0 + + * DDR4- Value to be loaded into SDRAM MR5 registers. Used in DDR4 designs + * only. + * PSU_DDRC_INIT6_MR5 0x6c0 + + * SDRAM Initialization Register 6 + * (OFFSET, MASK, VALUE) (0XFD0700E8, 0xFFFFFFFFU ,0x000006C0U) + */ + PSU_Mask_Write(DDRC_INIT6_OFFSET, 0xFFFFFFFFU, 0x000006C0U); +/*##################################################################### */ + + /* + * Register : INIT7 @ 0XFD0700EC + + * DDR4- Value to be loaded into SDRAM MR6 registers. Used in DDR4 designs + * only. + * PSU_DDRC_INIT7_MR6 0x819 + + * SDRAM Initialization Register 7 + * (OFFSET, MASK, VALUE) (0XFD0700EC, 0xFFFF0000U ,0x08190000U) + */ + PSU_Mask_Write(DDRC_INIT7_OFFSET, 0xFFFF0000U, 0x08190000U); +/*##################################################################### */ + + /* + * Register : DIMMCTL @ 0XFD0700F0 + + * Disabling Address Mirroring for BG bits. When this is set to 1, BG0 and + * BG1 are NOT swapped even if Address Mirroring is enabled. This will be r + * equired for DDR4 DIMMs with x16 devices. - 1 - BG0 and BG1 are NOT swapp + * ed. - 0 - BG0 and BG1 are swapped if address mirroring is enabled. + * PSU_DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING 0x0 + + * Enable for BG1 bit of MRS command. BG1 bit of the mode register address + * is specified as RFU (Reserved for Future Use) and must be programmed to + * 0 during MRS. In case where DRAMs which do not have BG1 are attached and + * both the CA parity and the Output Inversion are enabled, this must be s + * et to 0, so that the calculation of CA parity will not include BG1 bit. + * Note: This has no effect on the address of any other memory accesses, or + * of software-driven mode register accesses. If address mirroring is enab + * led, this is applied to BG1 of even ranks and BG0 of odd ranks. - 1 - En + * abled - 0 - Disabled + * PSU_DDRC_DIMMCTL_MRS_BG1_EN 0x1 + + * Enable for A17 bit of MRS command. A17 bit of the mode register address + * is specified as RFU (Reserved for Future Use) and must be programmed to + * 0 during MRS. In case where DRAMs which do not have A17 are attached and + * the Output Inversion are enabled, this must be set to 0, so that the ca + * lculation of CA parity will not include A17 bit. Note: This has no effec + * t on the address of any other memory accesses, or of software-driven mod + * e register accesses. - 1 - Enabled - 0 - Disabled + * PSU_DDRC_DIMMCTL_MRS_A17_EN 0x0 + + * Output Inversion Enable (for DDR4 RDIMM implementations only). DDR4 RDIM + * M implements the Output Inversion feature by default, which means that t + * he following address, bank address and bank group bits of B-side DRAMs a + * re inverted: A3-A9, A11, A13, A17, BA0-BA1, BG0-BG1. Setting this bit en + * sures that, for mode register accesses generated by the uMCTL2 during th + * e automatic initialization routine and enabling of a particular DDR4 fea + * ture, separate A-side and B-side mode register accesses are generated. F + * or B-side mode register accesses, these bits are inverted within the uMC + * TL2 to compensate for this RDIMM inversion. Note: This has no effect on + * the address of any other memory accesses, or of software-driven mode reg + * ister accesses. - 1 - Implement output inversion for B-side DRAMs. - 0 - + * Do not implement output inversion for B-side DRAMs. + * PSU_DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN 0x0 + + * Address Mirroring Enable (for multi-rank UDIMM implementations and multi + * -rank DDR4 RDIMM implementations). Some UDIMMs and DDR4 RDIMMs implement + * address mirroring for odd ranks, which means that the following address + * , bank address and bank group bits are swapped: (A3, A4), (A5, A6), (A7, + * A8), (BA0, BA1) and also (A11, A13), (BG0, BG1) for the DDR4. Setting t + * his bit ensures that, for mode register accesses during the automatic in + * itialization routine, these bits are swapped within the uMCTL2 to compen + * sate for this UDIMM/RDIMM swapping. In addition to the automatic initial + * ization routine, in case of DDR4 UDIMM/RDIMM, they are swapped during th + * e automatic MRS access to enable/disable of a particular DDR4 feature. N + * ote: This has no effect on the address of any other memory accesses, or + * of software-driven mode register accesses. This is not supported for mDD + * R, LPDDR2, LPDDR3 or LPDDR4 SDRAMs. Note: In case of x16 DDR4 DIMMs, BG1 + * output of MRS for the odd ranks is same as BG0 because BG1 is invalid, + * hence dimm_dis_bg_mirroring register must be set to 1. - 1 - For odd ran + * ks, implement address mirroring for MRS commands to during initializatio + * n and for any automatic DDR4 MRS commands (to be used if UDIMM/RDIMM imp + * lements address mirroring) - 0 - Do not implement address mirroring + * PSU_DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN 0x0 + + * Staggering enable for multi-rank accesses (for multi-rank UDIMM and RDIM + * M implementations only). This is not supported for mDDR, LPDDR2, LPDDR3 + * or LPDDR4 SDRAMs. Note: Even if this bit is set it does not take care of + * software driven MR commands (via MRCTRL0/MRCTRL1), where software is re + * sponsible to send them to seperate ranks as appropriate. - 1 - (DDR4) Se + * nd MRS commands to each ranks seperately - 1 - (non-DDR4) Send all comma + * nds to even and odd ranks seperately - 0 - Do not stagger accesses + * PSU_DDRC_DIMMCTL_DIMM_STAGGER_CS_EN 0x0 + + * DIMM Control Register + * (OFFSET, MASK, VALUE) (0XFD0700F0, 0x0000003FU ,0x00000010U) + */ + PSU_Mask_Write(DDRC_DIMMCTL_OFFSET, 0x0000003FU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : RANKCTL @ 0XFD0700F4 + + * Only present for multi-rank configurations. Indicates the number of cloc + * ks of gap in data responses when performing consecutive writes to differ + * ent ranks. This is used to switch the delays in the PHY to match the ran + * k requirements. This value should consider both PHY requirement and ODT + * requirement. - PHY requirement: tphy_wrcsgap + 1 (see PHY databook for v + * alue of tphy_wrcsgap) If CRC feature is enabled, should be increased by + * 1. If write preamble is set to 2tCK(DDR4/LPDDR4 only), should be increas + * ed by 1. If write postamble is set to 1.5tCK(LPDDR4 only), should be inc + * reased by 1. - ODT requirement: The value programmed in this register ta + * kes care of the ODT switch off timing requirement when switching ranks d + * uring writes. For LPDDR4, the requirement is ODTLoff - ODTLon - BL/2 + 1 + * For configurations with MEMC_FREQ_RATIO=1, program this to the larger o + * f PHY requirement or ODT requirement. For configurations with MEMC_FREQ_ + * RATIO=2, program this to the larger value divided by two and round it up + * to the next integer. + * PSU_DDRC_RANKCTL_DIFF_RANK_WR_GAP 0x6 + + * Only present for multi-rank configurations. Indicates the number of cloc + * ks of gap in data responses when performing consecutive reads to differe + * nt ranks. This is used to switch the delays in the PHY to match the rank + * requirements. This value should consider both PHY requirement and ODT r + * equirement. - PHY requirement: tphy_rdcsgap + 1 (see PHY databook for va + * lue of tphy_rdcsgap) If read preamble is set to 2tCK(DDR4/LPDDR4 only), + * should be increased by 1. If read postamble is set to 1.5tCK(LPDDR4 only + * ), should be increased by 1. - ODT requirement: The value programmed in + * this register takes care of the ODT switch off timing requirement when s + * witching ranks during reads. For configurations with MEMC_FREQ_RATIO=1, + * program this to the larger of PHY requirement or ODT requirement. For co + * nfigurations with MEMC_FREQ_RATIO=2, program this to the larger value di + * vided by two and round it up to the next integer. + * PSU_DDRC_RANKCTL_DIFF_RANK_RD_GAP 0x6 + + * Only present for multi-rank configurations. Background: Reads to the sam + * e rank can be performed back-to-back. Reads to different ranks require a + * dditional gap dictated by the register RANKCTL.diff_rank_rd_gap. This is + * to avoid possible data bus contention as well as to give PHY enough tim + * e to switch the delay when changing ranks. The uMCTL2 arbitrates for bus + * access on a cycle-by-cycle basis; therefore after a read is scheduled, + * there are few clock cycles (determined by the value on RANKCTL.diff_rank + * _rd_gap register) in which only reads from the same rank are eligible to + * be scheduled. This prevents reads from other ranks from having fair acc + * ess to the data bus. This parameter represents the maximum number of rea + * ds that can be scheduled consecutively to the same rank. After this numb + * er is reached, a delay equal to RANKCTL.diff_rank_rd_gap is inserted by + * the scheduler to allow all ranks a fair opportunity to be scheduled. Hig + * her numbers increase bandwidth utilization, lower numbers increase fairn + * ess. This feature can be DISABLED by setting this register to 0. When se + * t to 0, the Controller will stay on the same rank as long as commands ar + * e available for it. Minimum programmable value is 0 (feature disabled) a + * nd maximum programmable value is 0xF. FOR PERFORMANCE ONLY. + * PSU_DDRC_RANKCTL_MAX_RANK_RD 0xf + + * Rank Control Register + * (OFFSET, MASK, VALUE) (0XFD0700F4, 0x00000FFFU ,0x0000066FU) + */ + PSU_Mask_Write(DDRC_RANKCTL_OFFSET, 0x00000FFFU, 0x0000066FU); +/*##################################################################### */ + + /* + * Register : DRAMTMG0 @ 0XFD070100 + + * Minimum time between write and precharge to same bank. Unit: Clocks Spec + * ifications: WL + BL/2 + tWR = approximately 8 cycles + 15 ns = 14 clocks + * @400MHz and less for lower frequencies where: - WL = write latency - BL + * = burst length. This must match the value programmed in the BL bit of t + * he mode register to the SDRAM. BST (burst terminate) is not supported at + * present. - tWR = Write recovery time. This comes directly from the SDRA + * M specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 for this p + * arameter. For configurations with MEMC_FREQ_RATIO=2, 1T mode, divide the + * above value by 2. No rounding up. For configurations with MEMC_FREQ_RAT + * IO=2, 2T mode or LPDDR4 mode, divide the above value by 2 and round it u + * p to the next integer value. + * PSU_DDRC_DRAMTMG0_WR2PRE 0x11 + + * tFAW Valid only when 8 or more banks(or banks x bank groups) are present + * . In 8-bank design, at most 4 banks must be activated in a rolling windo + * w of tFAW cycles. For configurations with MEMC_FREQ_RATIO=2, program thi + * s to (tFAW/2) and round up to next integer value. In a 4-bank design, se + * t this register to 0x1 independent of the MEMC_FREQ_RATIO configuration. + * Unit: Clocks + * PSU_DDRC_DRAMTMG0_T_FAW 0x10 + + * tRAS(max): Maximum time between activate and precharge to same bank. Thi + * s is the maximum time that a page can be kept open Minimum value of this + * register is 1. Zero is invalid. For configurations with MEMC_FREQ_RATIO + * =2, program this to (tRAS(max)-1)/2. No rounding up. Unit: Multiples of + * 1024 clocks. + * PSU_DDRC_DRAMTMG0_T_RAS_MAX 0x24 + + * tRAS(min): Minimum time between activate and precharge to the same bank. + * For configurations with MEMC_FREQ_RATIO=2, 1T mode, program this to tRA + * S(min)/2. No rounding up. For configurations with MEMC_FREQ_RATIO=2, 2T + * mode or LPDDR4 mode, program this to (tRAS(min)/2) and round it up to th + * e next integer value. Unit: Clocks + * PSU_DDRC_DRAMTMG0_T_RAS_MIN 0x12 + + * SDRAM Timing Register 0 + * (OFFSET, MASK, VALUE) (0XFD070100, 0x7F3F7F3FU ,0x11102412U) + */ + PSU_Mask_Write(DDRC_DRAMTMG0_OFFSET, 0x7F3F7F3FU, 0x11102412U); +/*##################################################################### */ + + /* + * Register : DRAMTMG1 @ 0XFD070104 + + * tXP: Minimum time after power-down exit to any operation. For DDR3, this + * should be programmed to tXPDLL if slow powerdown exit is selected in MR + * 0[12]. If C/A parity for DDR4 is used, set to (tXP+PL) instead. For conf + * igurations with MEMC_FREQ_RATIO=2, program this to (tXP/2) and round it + * up to the next integer value. Units: Clocks + * PSU_DDRC_DRAMTMG1_T_XP 0x4 + + * tRTP: Minimum time from read to precharge of same bank. - DDR2: tAL + BL + * /2 + max(tRTP, 2) - 2 - DDR3: tAL + max (tRTP, 4) - DDR4: Max of followi + * ng two equations: tAL + max (tRTP, 4) or, RL + BL/2 - tRP. - mDDR: BL/2 + * - LPDDR2: Depends on if it's LPDDR2-S2 or LPDDR2-S4: LPDDR2-S2: BL/2 + t + * RTP - 1. LPDDR2-S4: BL/2 + max(tRTP,2) - 2. - LPDDR3: BL/2 + max(tRTP,4) + * - 4 - LPDDR4: BL/2 + max(tRTP,8) - 8 For configurations with MEMC_FREQ_ + * RATIO=2, 1T mode, divide the above value by 2. No rounding up. For confi + * gurations with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, divide the abo + * ve value by 2 and round it up to the next integer value. Unit: Clocks. + * PSU_DDRC_DRAMTMG1_RD2PRE 0x4 + + * tRC: Minimum time between activates to same bank. For configurations wit + * h MEMC_FREQ_RATIO=2, program this to (tRC/2) and round up to next intege + * r value. Unit: Clocks. + * PSU_DDRC_DRAMTMG1_T_RC 0x1a + + * SDRAM Timing Register 1 + * (OFFSET, MASK, VALUE) (0XFD070104, 0x001F1F7FU ,0x0004041AU) + */ + PSU_Mask_Write(DDRC_DRAMTMG1_OFFSET, 0x001F1F7FU, 0x0004041AU); +/*##################################################################### */ + + /* + * Register : DRAMTMG2 @ 0XFD070108 + + * Set to WL Time from write command to write data on SDRAM interface. This + * must be set to WL. For mDDR, it should normally be set to 1. Note that, + * depending on the PHY, if using RDIMM, it may be necessary to use a valu + * e of WL + 1 to compensate for the extra cycle of latency through the RDI + * MM For configurations with MEMC_FREQ_RATIO=2, divide the value calculate + * d using the above equation by 2, and round it up to next integer. This r + * egister field is not required for DDR2 and DDR3 (except if MEMC_TRAINING + * is set), as the DFI read and write latencies defined in DFITMG0 and DFI + * TMG1 are sufficient for those protocols Unit: clocks + * PSU_DDRC_DRAMTMG2_WRITE_LATENCY 0x7 + + * Set to RL Time from read command to read data on SDRAM interface. This m + * ust be set to RL. Note that, depending on the PHY, if using RDIMM, it ma + * t be necessary to use a value of RL + 1 to compensate for the extra cycl + * e of latency through the RDIMM For configurations with MEMC_FREQ_RATIO=2 + * , divide the value calculated using the above equation by 2, and round i + * t up to next integer. This register field is not required for DDR2 and D + * DR3 (except if MEMC_TRAINING is set), as the DFI read and write latencie + * s defined in DFITMG0 and DFITMG1 are sufficient for those protocols Unit + * : clocks + * PSU_DDRC_DRAMTMG2_READ_LATENCY 0x8 + + * DDR2/3/mDDR: RL + BL/2 + 2 - WL DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL L + * PDDR2/LPDDR3: RL + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL LPDDR4(DQ ODT is Di + * sabled): RL + BL/2 + RU(tDQSCKmax/tCK) + WR_PREAMBLE + RD_POSTAMBLE - WL + * LPDDR4(DQ ODT is Enabled) : RL + BL/2 + RU(tDQSCKmax/tCK) + RD_POSTAMBL + * E - ODTLon - RU(tODTon(min)/tCK) Minimum time from read command to write + * command. Include time for bus turnaround and all per-bank, per-rank, an + * d global constraints. Unit: Clocks. Where: - WL = write latency - BL = b + * urst length. This must match the value programmed in the BL bit of the m + * ode register to the SDRAM - RL = read latency = CAS latency - WR_PREAMBL + * E = write preamble. This is unique to DDR4 and LPDDR4. - RD_POSTAMBLE = + * read postamble. This is unique to LPDDR4. For LPDDR2/LPDDR3/LPDDR4, if d + * erating is enabled (DERATEEN.derate_enable=1), derated tDQSCKmax should + * be used. For configurations with MEMC_FREQ_RATIO=2, divide the value cal + * culated using the above equation by 2, and round it up to next integer. + * PSU_DDRC_DRAMTMG2_RD2WR 0x6 + + * DDR4: CWL + PL + BL/2 + tWTR_L Others: CWL + BL/2 + tWTR In DDR4, minimu + * m time from write command to read command for same bank group. In others + * , minimum time from write command to read command. Includes time for bus + * turnaround, recovery times, and all per-bank, per-rank, and global cons + * traints. Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity la + * tency - BL = burst length. This must match the value programmed in the B + * L bit of the mode register to the SDRAM - tWTR_L = internal write to rea + * d command delay for same bank group. This comes directly from the SDRAM + * specification. - tWTR = internal write to read command delay. This comes + * directly from the SDRAM specification. Add one extra cycle for LPDDR2/L + * PDDR3/LPDDR4 operation. For configurations with MEMC_FREQ_RATIO=2, divid + * e the value calculated using the above equation by 2, and round it up to + * next integer. + * PSU_DDRC_DRAMTMG2_WR2RD 0xd + + * SDRAM Timing Register 2 + * (OFFSET, MASK, VALUE) (0XFD070108, 0x3F3F3F3FU ,0x0708060DU) + */ + PSU_Mask_Write(DDRC_DRAMTMG2_OFFSET, 0x3F3F3F3FU, 0x0708060DU); +/*##################################################################### */ + + /* + * Register : DRAMTMG3 @ 0XFD07010C + + * Time to wait after a mode register write or read (MRW or MRR). Present o + * nly in designs configured to support LPDDR2, LPDDR3 or LPDDR4. LPDDR2 ty + * pically requires value of 5. LPDDR3 typically requires value of 10. LPDD + * R4: Set this to the larger of tMRW and tMRWCKEL. For LPDDR2, this regist + * er is used for the time from a MRW/MRR to all other commands. For LDPDR3 + * , this register is used for the time from a MRW/MRR to a MRW/MRR. + * PSU_DDRC_DRAMTMG3_T_MRW 0x5 + + * tMRD: Cycles to wait after a mode register write or read. Depending on t + * he connected SDRAM, tMRD represents: DDR2/mDDR: Time from MRS to any com + * mand DDR3/4: Time from MRS to MRS command LPDDR2: not used LPDDR3/4: Tim + * e from MRS to non-MRS command For configurations with MEMC_FREQ_RATIO=2, + * program this to (tMRD/2) and round it up to the next integer value. If + * C/A parity for DDR4 is used, set to tMRD_PAR(tMOD+PL) instead. + * PSU_DDRC_DRAMTMG3_T_MRD 0x4 + + * tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode com + * mand and following non-load mode command. If C/A parity for DDR4 is used + * , set to tMOD_PAR(tMOD+PL) instead. Set to tMOD if MEMC_FREQ_RATIO=1, or + * tMOD/2 (rounded up to next integer) if MEMC_FREQ_RATIO=2. Note that if + * using RDIMM, depending on the PHY, it may be necessary to use a value of + * tMOD + 1 or (tMOD + 1)/2 to compensate for the extra cycle of latency a + * pplied to mode register writes by the RDIMM chip. + * PSU_DDRC_DRAMTMG3_T_MOD 0xc + + * SDRAM Timing Register 3 + * (OFFSET, MASK, VALUE) (0XFD07010C, 0x3FF3F3FFU ,0x0050400CU) + */ + PSU_Mask_Write(DDRC_DRAMTMG3_OFFSET, 0x3FF3F3FFU, 0x0050400CU); +/*##################################################################### */ + + /* + * Register : DRAMTMG4 @ 0XFD070110 + + * tRCD - tAL: Minimum time from activate to read or write command to same + * bank. For configurations with MEMC_FREQ_RATIO=2, program this to ((tRCD + * - tAL)/2) and round it up to the next integer value. Minimum value allow + * ed for this register is 1, which implies minimum (tRCD - tAL) value to b + * e 2 in configurations with MEMC_FREQ_RATIO=2. Unit: Clocks. + * PSU_DDRC_DRAMTMG4_T_RCD 0x8 + + * DDR4: tCCD_L: This is the minimum time between two reads or two writes f + * or same bank group. Others: tCCD: This is the minimum time between two r + * eads or two writes. For configurations with MEMC_FREQ_RATIO=2, program t + * his to (tCCD_L/2 or tCCD/2) and round it up to the next integer value. U + * nit: clocks. + * PSU_DDRC_DRAMTMG4_T_CCD 0x3 + + * DDR4: tRRD_L: Minimum time between activates from bank 'a' to bank 'b' f + * or same bank group. Others: tRRD: Minimum time between activates from ba + * nk 'a' to bank 'b'For configurations with MEMC_FREQ_RATIO=2, program thi + * s to (tRRD_L/2 or tRRD/2) and round it up to the next integer value. Uni + * t: Clocks. + * PSU_DDRC_DRAMTMG4_T_RRD 0x3 + + * tRP: Minimum time from precharge to activate of same bank. For MEMC_FREQ + * _RATIO=1 configurations, t_rp should be set to RoundUp(tRP/tCK). For MEM + * C_FREQ_RATIO=2 configurations, t_rp should be set to RoundDown(RoundUp(t + * RP/tCK)/2) + 1. For MEMC_FREQ_RATIO=2 configurations in LPDDR4, t_rp sho + * uld be set to RoundUp(RoundUp(tRP/tCK)/2). Unit: Clocks. + * PSU_DDRC_DRAMTMG4_T_RP 0x9 + + * SDRAM Timing Register 4 + * (OFFSET, MASK, VALUE) (0XFD070110, 0x1F0F0F1FU ,0x08030309U) + */ + PSU_Mask_Write(DDRC_DRAMTMG4_OFFSET, 0x1F0F0F1FU, 0x08030309U); +/*##################################################################### */ + + /* + * Register : DRAMTMG5 @ 0XFD070114 + + * This is the time before Self Refresh Exit that CK is maintained as a val + * id clock before issuing SRX. Specifies the clock stable time before SRX. + * Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCK + * EH - DDR2: 1 - DDR3: tCKSRX - DDR4: tCKSRX For configurations with MEMC_ + * FREQ_RATIO=2, program this to recommended value divided by two and round + * it up to next integer. + * PSU_DDRC_DRAMTMG5_T_CKSRX 0x6 + + * This is the time after Self Refresh Down Entry that CK is maintained as + * a valid clock. Specifies the clock disable delay after SRE. Recommended + * settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL - DDR2: 1 + * - DDR3: max (10 ns, 5 tCK) - DDR4: max (10 ns, 5 tCK) For configurations + * with MEMC_FREQ_RATIO=2, program this to recommended value divided by tw + * o and round it up to next integer. + * PSU_DDRC_DRAMTMG5_T_CKSRE 0x6 + + * Minimum CKE low width for Self refresh or Self refresh power down entry + * to exit timing in memory clock cycles. Recommended settings: - mDDR: tRF + * C - LPDDR2: tCKESR - LPDDR3: tCKESR - LPDDR4: max(tCKELPD, tSR) - DDR2: + * tCKE - DDR3: tCKE + 1 - DDR4: tCKE + 1 For configurations with MEMC_FREQ + * _RATIO=2, program this to recommended value divided by two and round it + * up to next integer. + * PSU_DDRC_DRAMTMG5_T_CKESR 0x4 + + * Minimum number of cycles of CKE HIGH/LOW during power-down and self refr + * esh. - LPDDR2/LPDDR3 mode: Set this to the larger of tCKE or tCKESR - LP + * DDR4 mode: Set this to the larger of tCKE, tCKELPD or tSR. - Non-LPDDR2/ + * non-LPDDR3/non-LPDDR4 designs: Set this to tCKE value. For configuration + * s with MEMC_FREQ_RATIO=2, program this to (value described above)/2 and + * round it up to the next integer value. Unit: Clocks. + * PSU_DDRC_DRAMTMG5_T_CKE 0x3 + + * SDRAM Timing Register 5 + * (OFFSET, MASK, VALUE) (0XFD070114, 0x0F0F3F1FU ,0x06060403U) + */ + PSU_Mask_Write(DDRC_DRAMTMG5_OFFSET, 0x0F0F3F1FU, 0x06060403U); +/*##################################################################### */ + + /* + * Register : DRAMTMG6 @ 0XFD070118 + + * This is the time after Deep Power Down Entry that CK is maintained as a + * valid clock. Specifies the clock disable delay after DPDE. Recommended s + * ettings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 For configurations with MEMC_ + * FREQ_RATIO=2, program this to recommended value divided by two and round + * it up to next integer. This is only present for designs supporting mDDR + * or LPDDR2/LPDDR3 devices. + * PSU_DDRC_DRAMTMG6_T_CKDPDE 0x1 + + * This is the time before Deep Power Down Exit that CK is maintained as a + * valid clock before issuing DPDX. Specifies the clock stable time before + * DPDX. Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 For config + * urations with MEMC_FREQ_RATIO=2, program this to recommended value divid + * ed by two and round it up to next integer. This is only present for desi + * gns supporting mDDR or LPDDR2 devices. + * PSU_DDRC_DRAMTMG6_T_CKDPDX 0x1 + + * This is the time before Clock Stop Exit that CK is maintained as a valid + * clock before issuing Clock Stop Exit. Specifies the clock stable time b + * efore next command after Clock Stop Exit. Recommended settings: - mDDR: + * 1 - LPDDR2: tXP + 2 - LPDDR3: tXP + 2 - LPDDR4: tXP + 2 For configuratio + * ns with MEMC_FREQ_RATIO=2, program this to recommended value divided by + * two and round it up to next integer. This is only present for designs su + * pporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices. + * PSU_DDRC_DRAMTMG6_T_CKCSX 0x4 + + * SDRAM Timing Register 6 + * (OFFSET, MASK, VALUE) (0XFD070118, 0x0F0F000FU ,0x01010004U) + */ + PSU_Mask_Write(DDRC_DRAMTMG6_OFFSET, 0x0F0F000FU, 0x01010004U); +/*##################################################################### */ + + /* + * Register : DRAMTMG7 @ 0XFD07011C + + * This is the time after Power Down Entry that CK is maintained as a valid + * clock. Specifies the clock disable delay after PDE. Recommended setting + * s: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL For configuration + * s with MEMC_FREQ_RATIO=2, program this to recommended value divided by t + * wo and round it up to next integer. This is only present for designs sup + * porting mDDR or LPDDR2/LPDDR3/LPDDR4 devices. + * PSU_DDRC_DRAMTMG7_T_CKPDE 0x6 + + * This is the time before Power Down Exit that CK is maintained as a valid + * clock before issuing PDX. Specifies the clock stable time before PDX. R + * ecommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: 2 For c + * onfigurations with MEMC_FREQ_RATIO=2, program this to recommended value + * divided by two and round it up to next integer. This is only present for + * designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices. + * PSU_DDRC_DRAMTMG7_T_CKPDX 0x6 + + * SDRAM Timing Register 7 + * (OFFSET, MASK, VALUE) (0XFD07011C, 0x00000F0FU ,0x00000606U) + */ + PSU_Mask_Write(DDRC_DRAMTMG7_OFFSET, 0x00000F0FU, 0x00000606U); +/*##################################################################### */ + + /* + * Register : DRAMTMG8 @ 0XFD070120 + + * tXS_FAST: Exit Self Refresh to ZQCL, ZQCS and MRS (only CL, WR, RTP and + * Geardown mode). For configurations with MEMC_FREQ_RATIO=2, program this + * to the above value divided by 2 and round up to next integer value. Unit + * : Multiples of 32 clocks. Note: This is applicable to only ZQCL/ZQCS com + * mands. Note: Ensure this is less than or equal to t_xs_x32. + * PSU_DDRC_DRAMTMG8_T_XS_FAST_X32 0x3 + + * tXS_ABORT: Exit Self Refresh to commands not requiring a locked DLL in S + * elf Refresh Abort. For configurations with MEMC_FREQ_RATIO=2, program th + * is to the above value divided by 2 and round up to next integer value. U + * nit: Multiples of 32 clocks. Note: Ensure this is less than or equal to + * t_xs_x32. + * PSU_DDRC_DRAMTMG8_T_XS_ABORT_X32 0x3 + + * tXSDLL: Exit Self Refresh to commands requiring a locked DLL. For config + * urations with MEMC_FREQ_RATIO=2, program this to the above value divided + * by 2 and round up to next integer value. Unit: Multiples of 32 clocks. + * Note: Used only for DDR2, DDR3 and DDR4 SDRAMs. + * PSU_DDRC_DRAMTMG8_T_XS_DLL_X32 0xd + + * tXS: Exit Self Refresh to commands not requiring a locked DLL. For confi + * gurations with MEMC_FREQ_RATIO=2, program this to the above value divide + * d by 2 and round up to next integer value. Unit: Multiples of 32 clocks. + * Note: Used only for DDR2, DDR3 and DDR4 SDRAMs. + * PSU_DDRC_DRAMTMG8_T_XS_X32 0x6 + + * SDRAM Timing Register 8 + * (OFFSET, MASK, VALUE) (0XFD070120, 0x7F7F7F7FU ,0x03030D06U) + */ + PSU_Mask_Write(DDRC_DRAMTMG8_OFFSET, 0x7F7F7F7FU, 0x03030D06U); +/*##################################################################### */ + + /* + * Register : DRAMTMG9 @ 0XFD070124 + + * DDR4 Write preamble mode - 0: 1tCK preamble - 1: 2tCK preamble Present o + * nly with MEMC_FREQ_RATIO=2 + * PSU_DDRC_DRAMTMG9_DDR4_WR_PREAMBLE 0x0 + + * tCCD_S: This is the minimum time between two reads or two writes for dif + * ferent bank group. For bank switching (from bank 'a' to bank 'b'), the m + * inimum time is this value + 1. For configurations with MEMC_FREQ_RATIO=2 + * , program this to (tCCD_S/2) and round it up to the next integer value. + * Present only in designs configured to support DDR4. Unit: clocks. + * PSU_DDRC_DRAMTMG9_T_CCD_S 0x2 + + * tRRD_S: Minimum time between activates from bank 'a' to bank 'b' for dif + * ferent bank group. For configurations with MEMC_FREQ_RATIO=2, program th + * is to (tRRD_S/2) and round it up to the next integer value. Present only + * in designs configured to support DDR4. Unit: Clocks. + * PSU_DDRC_DRAMTMG9_T_RRD_S 0x2 + + * CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command + * for different bank group. Includes time for bus turnaround, recovery ti + * mes, and all per-bank, per-rank, and global constraints. Present only in + * designs configured to support DDR4. Unit: Clocks. Where: - CWL = CAS wr + * ite latency - PL = Parity latency - BL = burst length. This must match t + * he value programmed in the BL bit of the mode register to the SDRAM - tW + * TR_S = internal write to read command delay for different bank group. Th + * is comes directly from the SDRAM specification. For configurations with + * MEMC_FREQ_RATIO=2, divide the value calculated using the above equation + * by 2, and round it up to next integer. + * PSU_DDRC_DRAMTMG9_WR2RD_S 0xb + + * SDRAM Timing Register 9 + * (OFFSET, MASK, VALUE) (0XFD070124, 0x40070F3FU ,0x0002020BU) + */ + PSU_Mask_Write(DDRC_DRAMTMG9_OFFSET, 0x40070F3FU, 0x0002020BU); +/*##################################################################### */ + + /* + * Register : DRAMTMG11 @ 0XFD07012C + + * tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DL + * L. For configurations with MEMC_FREQ_RATIO=2, program this to (tXMPDLL/2 + * ) and round it up to the next integer value. Present only in designs con + * figured to support DDR4. Unit: Multiples of 32 clocks. + * PSU_DDRC_DRAMTMG11_POST_MPSM_GAP_X32 0x70 + + * tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge. For + * configurations with MEMC_FREQ_RATIO=2, program this to RoundUp(tMPX_LH/2 + * )+1. Present only in designs configured to support DDR4. Unit: clocks. + * PSU_DDRC_DRAMTMG11_T_MPX_LH 0x7 + + * tMPX_S: Minimum time CS setup time to CKE. For configurations with MEMC_ + * FREQ_RATIO=2, program this to (tMPX_S/2) and round it up to the next int + * eger value. Present only in designs configured to support DDR4. Unit: Cl + * ocks. + * PSU_DDRC_DRAMTMG11_T_MPX_S 0x1 + + * tCKMPE: Minimum valid clock requirement after MPSM entry. Present only i + * n designs configured to support DDR4. Unit: Clocks. For configurations w + * ith MEMC_FREQ_RATIO=2, divide the value calculated using the above equat + * ion by 2, and round it up to next integer. + * PSU_DDRC_DRAMTMG11_T_CKMPE 0xe + + * SDRAM Timing Register 11 + * (OFFSET, MASK, VALUE) (0XFD07012C, 0x7F1F031FU ,0x7007010EU) + */ + PSU_Mask_Write(DDRC_DRAMTMG11_OFFSET, 0x7F1F031FU, 0x7007010EU); +/*##################################################################### */ + + /* + * Register : DRAMTMG12 @ 0XFD070130 + + * tCMDCKE: Delay from valid command to CKE input LOW. Set this to the larg + * er of tESCKE or tCMDCKE For configurations with MEMC_FREQ_RATIO=2, progr + * am this to (max(tESCKE, tCMDCKE)/2) and round it up to next integer valu + * e. + * PSU_DDRC_DRAMTMG12_T_CMDCKE 0x2 + + * tCKEHCMD: Valid command requirement after CKE input HIGH. For configurat + * ions with MEMC_FREQ_RATIO=2, program this to (tCKEHCMD/2) and round it u + * p to next integer value. + * PSU_DDRC_DRAMTMG12_T_CKEHCMD 0x6 + + * tMRD_PDA: This is the Mode Register Set command cycle time in PDA mode. + * For configurations with MEMC_FREQ_RATIO=2, program this to (tMRD_PDA/2) + * and round it up to next integer value. + * PSU_DDRC_DRAMTMG12_T_MRD_PDA 0x8 + + * SDRAM Timing Register 12 + * (OFFSET, MASK, VALUE) (0XFD070130, 0x00030F1FU ,0x00020608U) + */ + PSU_Mask_Write(DDRC_DRAMTMG12_OFFSET, 0x00030F1FU, 0x00020608U); +/*##################################################################### */ + + /* + * Register : ZQCTL0 @ 0XFD070180 + + * - 1 - Disable uMCTL2 generation of ZQCS/MPC(ZQ calibration) command. Reg + * ister DBGCMD.zq_calib_short can be used instead to issue ZQ calibration + * request from APB module. - 0 - Internally generate ZQCS/MPC(ZQ calibrati + * on) commands based on ZQCTL1.t_zq_short_interval_x1024. This is only pre + * sent for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. + * PSU_DDRC_ZQCTL0_DIS_AUTO_ZQ 0x1 + + * - 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refres + * h/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 + * or LPDDR3 or LPDDR4 mode. - 0 - Enable issuing of ZQCL/MPC(ZQ calibratio + * n) command at Self-Refresh/SR-Powerdown exit. Only applicable when run i + * n DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. This is only present + * for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. + * PSU_DDRC_ZQCTL0_DIS_SRX_ZQCL 0x0 + + * - 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQC + * L/ZQCS/MPC(ZQ calibration) commands are sent to one rank at a time with + * tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that co + * mmands to different ranks do not overlap. - 0 - ZQ resistor is not share + * d. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR + * 3/LPDDR4 devices. + * PSU_DDRC_ZQCTL0_ZQ_RESISTOR_SHARED 0x0 + + * - 1 - Disable issuing of ZQCL command at Maximum Power Saving Mode exit. + * Only applicable when run in DDR4 mode. - 0 - Enable issuing of ZQCL com + * mand at Maximum Power Saving Mode exit. Only applicable when run in DDR4 + * mode. This is only present for designs supporting DDR4 devices. + * PSU_DDRC_ZQCTL0_DIS_MPSMX_ZQCL 0x0 + + * tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Numbe + * r of cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ St + * art) command is issued to SDRAM. For configurations with MEMC_FREQ_RATIO + * =2: DDR3/DDR4: program this to tZQoper/2 and round it up to the next int + * eger value. LPDDR2/LPDDR3: program this to tZQCL/2 and round it up to th + * e next integer value. LPDDR4: program this to tZQCAL/2 and round it up t + * o the next integer value. Unit: Clock cycles. This is only present for d + * esigns supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. + * PSU_DDRC_ZQCTL0_T_ZQ_LONG_NOP 0x100 + + * tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of cycles of + * NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command + * is issued to SDRAM. For configurations with MEMC_FREQ_RATIO=2, program t + * his to tZQCS/2 and round it up to the next integer value. Unit: Clock cy + * cles. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LP + * DDR3/LPDDR4 devices. + * PSU_DDRC_ZQCTL0_T_ZQ_SHORT_NOP 0x40 + + * ZQ Control Register 0 + * (OFFSET, MASK, VALUE) (0XFD070180, 0xF7FF03FFU ,0x81000040U) + */ + PSU_Mask_Write(DDRC_ZQCTL0_OFFSET, 0xF7FF03FFU, 0x81000040U); +/*##################################################################### */ + + /* + * Register : ZQCTL1 @ 0XFD070184 + + * tZQReset: Number of cycles of NOP required after a ZQReset (ZQ calibrati + * on Reset) command is issued to SDRAM. For configurations with MEMC_FREQ_ + * RATIO=2, program this to tZQReset/2 and round it up to the next integer + * value. Unit: Clock cycles. This is only present for designs supporting L + * PDDR2/LPDDR3/LPDDR4 devices. + * PSU_DDRC_ZQCTL1_T_ZQ_RESET_NOP 0x20 + + * Average interval to wait between automatically issuing ZQCS (ZQ calibrat + * ion short)/MPC(ZQ calibration) commands to DDR3/DDR4/LPDDR2/LPDDR3/LPDDR + * 4 devices. Meaningless, if ZQCTL0.dis_auto_zq=1. Unit: 1024 clock cycles + * . This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3 + * /LPDDR4 devices. + * PSU_DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024 0x196dc + + * ZQ Control Register 1 + * (OFFSET, MASK, VALUE) (0XFD070184, 0x3FFFFFFFU ,0x020196DCU) + */ + PSU_Mask_Write(DDRC_ZQCTL1_OFFSET, 0x3FFFFFFFU, 0x020196DCU); +/*##################################################################### */ + + /* + * Register : DFITMG0 @ 0XFD070190 + + * Specifies the number of DFI clock cycles after an assertion or de-assert + * ion of the DFI control signals that the control signals at the PHY-DRAM + * interface reflect the assertion or de-assertion. If the DFI clock and th + * e memory clock are not phase-aligned, this timing parameter should be ro + * unded up to the next integer value. Note that if using RDIMM, it is nece + * ssary to increment this parameter by RDIMM's extra cycle of latency in t + * erms of DFI clock. + * PSU_DDRC_DFITMG0_DFI_T_CTRL_DELAY 0x4 + + * Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated u + * sing HDR or SDR values Selects whether value in DFITMG0.dfi_t_rddata_en + * is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles + * - 1 in terms of SDR clock cycles Refer to PHY specification for correct + * value. + * PSU_DDRC_DFITMG0_DFI_RDDATA_USE_SDR 0x1 + + * Time from the assertion of a read command on the DFI interface to the as + * sertion of the dfi_rddata_en signal. Refer to PHY specification for corr + * ect value. This corresponds to the DFI parameter trddata_en. Note that, + * depending on the PHY, if using RDIMM, it may be necessary to use the val + * ue (CL + 1) in the calculation of trddata_en. This is to compensate for + * the extra cycle of latency through the RDIMM. Unit: Clocks + * PSU_DDRC_DFITMG0_DFI_T_RDDATA_EN 0xb + + * Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated us + * ing HDR or SDR values Selects whether value in DFITMG0.dfi_tphy_wrlat is + * in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.df + * i_tphy_wrdata is in terms of SDR or HDR clock cycles - 0 in terms of HDR + * clock cycles - 1 in terms of SDR clock cycles Refer to PHY specificatio + * n for correct value. + * PSU_DDRC_DFITMG0_DFI_WRDATA_USE_SDR 0x1 + + * Specifies the number of clock cycles between when dfi_wrdata_en is asser + * ted to when the associated write data is driven on the dfi_wrdata signal + * . This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY + * specification for correct value. Note, max supported value is 8. Unit: + * Clocks + * PSU_DDRC_DFITMG0_DFI_TPHY_WRDATA 0x2 + + * Write latency Number of clocks from the write command to write data enab + * le (dfi_wrdata_en). This corresponds to the DFI timing parameter tphy_wr + * lat. Refer to PHY specification for correct value.Note that, depending o + * n the PHY, if using RDIMM, it may be necessary to use the value (CL + 1) + * in the calculation of tphy_wrlat. This is to compensate for the extra c + * ycle of latency through the RDIMM. + * PSU_DDRC_DFITMG0_DFI_TPHY_WRLAT 0xb + + * DFI Timing Register 0 + * (OFFSET, MASK, VALUE) (0XFD070190, 0x1FBFBF3FU ,0x048B820BU) + */ + PSU_Mask_Write(DDRC_DFITMG0_OFFSET, 0x1FBFBF3FU, 0x048B820BU); +/*##################################################################### */ + + /* + * Register : DFITMG1 @ 0XFD070194 + + * Specifies the number of DFI PHY clocks between when the dfi_cs signal is + * asserted and when the associated command is driven. This field is used + * for CAL mode, should be set to '0' or the value which matches the CAL mo + * de register setting in the DRAM. If the PHY can add the latency for CAL + * mode, this should be set to '0'. Valid Range: 0, 3, 4, 5, 6, and 8 + * PSU_DDRC_DFITMG1_DFI_T_CMD_LAT 0x0 + + * Specifies the number of DFI PHY clocks between when the dfi_cs signal is + * asserted and when the associated dfi_parity_in signal is driven. + * PSU_DDRC_DFITMG1_DFI_T_PARIN_LAT 0x0 + + * Specifies the number of DFI clocks between when the dfi_wrdata_en signal + * is asserted and when the corresponding write data transfer is completed + * on the DRAM bus. This corresponds to the DFI timing parameter twrdata_d + * elay. Refer to PHY specification for correct value. For DFI 3.0 PHY, set + * to twrdata_delay, a new timing parameter introduced in DFI 3.0. For DFI + * 2.1 PHY, set to tphy_wrdata + (delay of DFI write data to the DRAM). Va + * lue to be programmed is in terms of DFI clocks, not PHY clocks. In FREQ_ + * RATIO=2, divide PHY's value by 2 and round up to next integer. If using + * DFITMG0.dfi_wrdata_use_sdr=1, add 1 to the value. Unit: Clocks + * PSU_DDRC_DFITMG1_DFI_T_WRDATA_DELAY 0x3 + + * Specifies the number of DFI clock cycles from the assertion of the dfi_d + * ram_clk_disable signal on the DFI until the clock to the DRAM memory dev + * ices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock + * and the memory clock are not phase aligned, this timing parameter should + * be rounded up to the next integer value. + * PSU_DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE 0x3 + + * Specifies the number of DFI clock cycles from the de-assertion of the df + * i_dram_clk_disable signal on the DFI until the first valid rising edge o + * f the clock to the DRAM memory devices, at the PHY-DRAM boundary. If the + * DFI clock and the memory clock are not phase aligned, this timing param + * eter should be rounded up to the next integer value. + * PSU_DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE 0x4 + + * DFI Timing Register 1 + * (OFFSET, MASK, VALUE) (0XFD070194, 0xF31F0F0FU ,0x00030304U) + */ + PSU_Mask_Write(DDRC_DFITMG1_OFFSET, 0xF31F0F0FU, 0x00030304U); +/*##################################################################### */ + + /* + * Register : DFILPCFG0 @ 0XFD070198 + + * Setting for DFI's tlp_resp time. Same value is used for both Power Down, + * Self Refresh, Deep Power Down and Maximum Power Saving modes. DFI 2.1 s + * pecification onwards, recommends using a fixed value of 7 always. + * PSU_DDRC_DFILPCFG0_DFI_TLP_RESP 0x7 + + * Value to drive on dfi_lp_wakeup signal when Deep Power Down mode is ente + * red. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32 + * cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 5 + * 12 cycles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycles - + * 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 6553 + * 6 cycles - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited T + * his is only present for designs supporting mDDR or LPDDR2/LPDDR3 devices + * . + * PSU_DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD 0x0 + + * Enables DFI Low Power interface handshaking during Deep Power Down Entry + * /Exit. - 0 - Disabled - 1 - Enabled This is only present for designs sup + * porting mDDR or LPDDR2/LPDDR3 devices. + * PSU_DDRC_DFILPCFG0_DFI_LP_EN_DPD 0x0 + + * Value to drive on dfi_lp_wakeup signal when Self Refresh mode is entered + * . Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32 cyc + * les - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 + * cycles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycles - 0x9 + * - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 c + * ycles - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited + * PSU_DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR 0x0 + + * Enables DFI Low Power interface handshaking during Self Refresh Entry/Ex + * it. - 0 - Disabled - 1 - Enabled + * PSU_DDRC_DFILPCFG0_DFI_LP_EN_SR 0x1 + + * Value to drive on dfi_lp_wakeup signal when Power Down mode is entered. + * Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32 cycle + * s - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cy + * cles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycles - 0x9 - + * 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cyc + * les - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited + * PSU_DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD 0x0 + + * Enables DFI Low Power interface handshaking during Power Down Entry/Exit + * . - 0 - Disabled - 1 - Enabled + * PSU_DDRC_DFILPCFG0_DFI_LP_EN_PD 0x1 + + * DFI Low Power Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD070198, 0x0FF1F1F1U ,0x07000101U) + */ + PSU_Mask_Write(DDRC_DFILPCFG0_OFFSET, 0x0FF1F1F1U, 0x07000101U); +/*##################################################################### */ + + /* + * Register : DFILPCFG1 @ 0XFD07019C + + * Value to drive on dfi_lp_wakeup signal when Maximum Power Saving Mode is + * entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 + * - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x + * 5 - 512 cycles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycl + * es - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - + * 65536 cycles - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimi + * ted This is only present for designs supporting DDR4 devices. + * PSU_DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM 0x2 + + * Enables DFI Low Power interface handshaking during Maximum Power Saving + * Mode Entry/Exit. - 0 - Disabled - 1 - Enabled This is only present for d + * esigns supporting DDR4 devices. + * PSU_DDRC_DFILPCFG1_DFI_LP_EN_MPSM 0x1 + + * DFI Low Power Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD07019C, 0x000000F1U ,0x00000021U) + */ + PSU_Mask_Write(DDRC_DFILPCFG1_OFFSET, 0x000000F1U, 0x00000021U); +/*##################################################################### */ + + /* + * Register : DFIUPD0 @ 0XFD0701A0 + + * When '1', disable the automatic dfi_ctrlupd_req generation by the uMCTL2 + * . The core must issue the dfi_ctrlupd_req signal using register reg_ddrc + * _ctrlupd. When '0', uMCTL2 issues dfi_ctrlupd_req periodically. + * PSU_DDRC_DFIUPD0_DIS_AUTO_CTRLUPD 0x0 + + * When '1', disable the automatic dfi_ctrlupd_req generation by the uMCTL2 + * following a self-refresh exit. The core must issue the dfi_ctrlupd_req + * signal using register reg_ddrc_ctrlupd. When '0', uMCTL2 issues a dfi_ct + * rlupd_req after exiting self-refresh. + * PSU_DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX 0x0 + + * Specifies the maximum number of clock cycles that the dfi_ctrlupd_req si + * gnal can assert. Lowest value to assign to this variable is 0x40. Unit: + * Clocks + * PSU_DDRC_DFIUPD0_DFI_T_CTRLUP_MAX 0x40 + + * Specifies the minimum number of clock cycles that the dfi_ctrlupd_req si + * gnal must be asserted. The uMCTL2 expects the PHY to respond within this + * time. If the PHY does not respond, the uMCTL2 will de-assert dfi_ctrlup + * d_req after dfi_t_ctrlup_min + 2 cycles. Lowest value to assign to this + * variable is 0x3. Unit: Clocks + * PSU_DDRC_DFIUPD0_DFI_T_CTRLUP_MIN 0x3 + + * DFI Update Register 0 + * (OFFSET, MASK, VALUE) (0XFD0701A0, 0xC3FF03FFU ,0x00400003U) + */ + PSU_Mask_Write(DDRC_DFIUPD0_OFFSET, 0xC3FF03FFU, 0x00400003U); +/*##################################################################### */ + + /* + * Register : DFIUPD1 @ 0XFD0701A4 + + * This is the minimum amount of time between uMCTL2 initiated DFI update r + * equests (which is executed whenever the uMCTL2 is idle). Set this number + * higher to reduce the frequency of update requests, which can have a sma + * ll impact on the latency of the first read request when the uMCTL2 is id + * le. Unit: 1024 clocks + * PSU_DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024 0x41 + + * This is the maximum amount of time between uMCTL2 initiated DFI update r + * equests. This timer resets with each update request; when the timer expi + * res dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd + * _ackx is received. PHY can use this idle time to recalibrate the delay l + * ines to the DLLs. The DFI controller update is also used to reset PHY FI + * FO pointers in case of data capture errors. Updates are required to main + * tain calibration over PVT, but frequent updates may impact performance. + * Note: Value programmed for DFIUPD1.dfi_t_ctrlupd_interval_max_x1024 must + * be greater than DFIUPD1.dfi_t_ctrlupd_interval_min_x1024. Unit: 1024 cl + * ocks + * PSU_DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024 0xe1 + + * DFI Update Register 1 + * (OFFSET, MASK, VALUE) (0XFD0701A4, 0x00FF00FFU ,0x004100E1U) + */ + PSU_Mask_Write(DDRC_DFIUPD1_OFFSET, 0x00FF00FFU, 0x004100E1U); +/*##################################################################### */ + + /* + * Register : DFIMISC @ 0XFD0701B0 + + * Defines polarity of dfi_wrdata_cs and dfi_rddata_cs signals. - 0: Signal + * s are active low - 1: Signals are active high + * PSU_DDRC_DFIMISC_DFI_DATA_CS_POLARITY 0x0 + + * DBI implemented in DDRC or PHY. - 0 - DDRC implements DBI functionality. + * - 1 - PHY implements DBI functionality. Present only in designs configu + * red to support DDR4 and LPDDR4. + * PSU_DDRC_DFIMISC_PHY_DBI_MODE 0x0 + + * PHY initialization complete enable signal. When asserted the dfi_init_co + * mplete signal can be used to trigger SDRAM initialisation + * PSU_DDRC_DFIMISC_DFI_INIT_COMPLETE_EN 0x0 + + * DFI Miscellaneous Control Register + * (OFFSET, MASK, VALUE) (0XFD0701B0, 0x00000007U ,0x00000000U) + */ + PSU_Mask_Write(DDRC_DFIMISC_OFFSET, 0x00000007U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : DFITMG2 @ 0XFD0701B4 + + * >Number of clocks between when a read command is sent on the DFI control + * interface and when the associated dfi_rddata_cs signal is asserted. Thi + * s corresponds to the DFI timing parameter tphy_rdcslat. Refer to PHY spe + * cification for correct value. + * PSU_DDRC_DFITMG2_DFI_TPHY_RDCSLAT 0x9 + + * Number of clocks between when a write command is sent on the DFI control + * interface and when the associated dfi_wrdata_cs signal is asserted. Thi + * s corresponds to the DFI timing parameter tphy_wrcslat. Refer to PHY spe + * cification for correct value. + * PSU_DDRC_DFITMG2_DFI_TPHY_WRCSLAT 0x6 + + * DFI Timing Register 2 + * (OFFSET, MASK, VALUE) (0XFD0701B4, 0x00003F3FU ,0x00000906U) + */ + PSU_Mask_Write(DDRC_DFITMG2_OFFSET, 0x00003F3FU, 0x00000906U); +/*##################################################################### */ + + /* + * Register : DBICTL @ 0XFD0701C0 + + * Read DBI enable signal in DDRC. - 0 - Read DBI is disabled. - 1 - Read D + * BI is enabled. This signal must be set the same value as DRAM's mode reg + * ister. - DDR4: MR5 bit A12. When x4 devices are used, this signal must b + * e set to 0. - LPDDR4: MR3[6] + * PSU_DDRC_DBICTL_RD_DBI_EN 0x0 + + * Write DBI enable signal in DDRC. - 0 - Write DBI is disabled. - 1 - Writ + * e DBI is enabled. This signal must be set the same value as DRAM's mode + * register. - DDR4: MR5 bit A11. When x4 devices are used, this signal mus + * t be set to 0. - LPDDR4: MR3[7] + * PSU_DDRC_DBICTL_WR_DBI_EN 0x0 + + * DM enable signal in DDRC. - 0 - DM is disabled. - 1 - DM is enabled. Thi + * s signal must be set the same logical value as DRAM's mode register. - D + * DR4: Set this to same value as MR5 bit A10. When x4 devices are used, th + * is signal must be set to 0. - LPDDR4: Set this to inverted value of MR13 + * [5] which is opposite polarity from this signal + * PSU_DDRC_DBICTL_DM_EN 0x1 + + * DM/DBI Control Register + * (OFFSET, MASK, VALUE) (0XFD0701C0, 0x00000007U ,0x00000001U) + */ + PSU_Mask_Write(DDRC_DBICTL_OFFSET, 0x00000007U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : ADDRMAP0 @ 0XFD070200 + + * Selects the HIF address bit used as rank address bit 0. Valid Range: 0 t + * o 27, and 31 Internal Base: 6 The selected HIF address bit is determined + * by adding the internal base to the value of this field. If set to 31, r + * ank address bit 0 is set to 0. + * PSU_DDRC_ADDRMAP0_ADDRMAP_CS_BIT0 0x1f + + * Address Map Register 0 + * (OFFSET, MASK, VALUE) (0XFD070200, 0x0000001FU ,0x0000001FU) + */ + PSU_Mask_Write(DDRC_ADDRMAP0_OFFSET, 0x0000001FU, 0x0000001FU); +/*##################################################################### */ + + /* + * Register : ADDRMAP1 @ 0XFD070204 + + * Selects the HIF address bit used as bank address bit 2. Valid Range: 0 t + * o 29 and 31 Internal Base: 4 The selected HIF address bit is determined + * by adding the internal base to the value of this field. If set to 31, ba + * nk address bit 2 is set to 0. + * PSU_DDRC_ADDRMAP1_ADDRMAP_BANK_B2 0x1f + + * Selects the HIF address bits used as bank address bit 1. Valid Range: 0 + * to 30 Internal Base: 3 The selected HIF address bit for each of the bank + * address bits is determined by adding the internal base to the value of + * this field. + * PSU_DDRC_ADDRMAP1_ADDRMAP_BANK_B1 0xa + + * Selects the HIF address bits used as bank address bit 0. Valid Range: 0 + * to 30 Internal Base: 2 The selected HIF address bit for each of the bank + * address bits is determined by adding the internal base to the value of + * this field. + * PSU_DDRC_ADDRMAP1_ADDRMAP_BANK_B0 0xa + + * Address Map Register 1 + * (OFFSET, MASK, VALUE) (0XFD070204, 0x001F1F1FU ,0x001F0A0AU) + */ + PSU_Mask_Write(DDRC_ADDRMAP1_OFFSET, 0x001F1F1FU, 0x001F0A0AU); +/*##################################################################### */ + + /* + * Register : ADDRMAP2 @ 0XFD070208 + + * - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 5. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 6. - Quarter bus width mode: Selects the HIF address bit + * used as column address bit 7 . Valid Range: 0 to 7, and 15 Internal Base + * : 5 The selected HIF address bit is determined by adding the internal ba + * se to the value of this field. If set to 15, this column address bit is + * set to 0. + * PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B5 0x0 + + * - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 4. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 5. - Quarter bus width mode: Selects the HIF address bit + * used as column address bit 6. Valid Range: 0 to 7, and 15 Internal Base: + * 4 The selected HIF address bit is determined by adding the internal bas + * e to the value of this field. If set to 15, this column address bit is s + * et to 0. + * PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B4 0x0 + + * - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 3. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 4. - Quarter bus width mode: Selects the HIF address bit + * used as column address bit 5. Valid Range: 0 to 7 Internal Base: 3 The s + * elected HIF address bit is determined by adding the internal base to the + * value of this field. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=1 + * 6, it is required to program this to 0, hence register does not exist in + * this case. + * PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B3 0x0 + + * - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 2. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 3. - Quarter bus width mode: Selects the HIF address bit + * used as column address bit 4. Valid Range: 0 to 7 Internal Base: 2 The s + * elected HIF address bit is determined by adding the internal base to the + * value of this field. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=8 + * or 16, it is required to program this to 0. + * PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B2 0x0 + + * Address Map Register 2 + * (OFFSET, MASK, VALUE) (0XFD070208, 0x0F0F0F0FU ,0x00000000U) + */ + PSU_Mask_Write(DDRC_ADDRMAP2_OFFSET, 0x0F0F0F0FU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ADDRMAP3 @ 0XFD07020C + + * - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 9. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 11 (10 in LPDDR2/LPDDR3 mode). - Quarter bus width mode: + * Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/ + * LPDDR3 mode). Valid Range: 0 to 7, and 15 Internal Base: 9 The selected + * HIF address bit is determined by adding the internal base to the value o + * f this field. If set to 15, this column address bit is set to 0. Note: P + * er JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved fo + * r indicating auto-precharge, and hence no source address bit can be mapp + * ed to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit + * for auto-precharge in the CA bus and hence column bit 10 is used. + * PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B9 0x0 + + * - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 8. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 9. - Quarter bus width mode: Selects the HIF address bit + * used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). Valid Range: 0 + * to 7, and 15 Internal Base: 8 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specifi + * cation, column address bit 10 is reserved for indicating auto-precharge, + * and hence no source address bit can be mapped to column address bit 10. + * In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA + * bus and hence column bit 10 is used. + * PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B8 0x0 + + * - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 7. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 8. - Quarter bus width mode: Selects the HIF address bit + * used as column address bit 9. Valid Range: 0 to 7, and 15 Internal Base: + * 7 The selected HIF address bit is determined by adding the internal bas + * e to the value of this field. If set to 15, this column address bit is s + * et to 0. + * PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B7 0x0 + + * - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 6. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 7. - Quarter bus width mode: Selects the HIF address bit + * used as column address bit 8. Valid Range: 0 to 7, and 15 Internal Base: + * 6 The selected HIF address bit is determined by adding the internal bas + * e to the value of this field. If set to 15, this column address bit is s + * et to 0. + * PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B6 0x0 + + * Address Map Register 3 + * (OFFSET, MASK, VALUE) (0XFD07020C, 0x0F0F0F0FU ,0x00000000U) + */ + PSU_Mask_Write(DDRC_ADDRMAP3_OFFSET, 0x0F0F0F0FU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ADDRMAP4 @ 0XFD070210 + + * - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 13 (11 in LPDDR2/LPDDR3 mode). - Half bus width mode: Unused. To m + * ake it unused, this should be tied to 4'hF. - Quarter bus width mode: Un + * used. To make it unused, this must be tied to 4'hF. Valid Range: 0 to 7, + * and 15 Internal Base: 11 The selected HIF address bit is determined by + * adding the internal base to the value of this field. If set to 15, this + * column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specificatio + * n, column address bit 10 is reserved for indicating auto-precharge, and + * hence no source address bit can be mapped to column address bit 10. In L + * PDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus + * and hence column bit 10 is used. + * PSU_DDRC_ADDRMAP4_ADDRMAP_COL_B11 0xf + + * - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 11 (10 in LPDDR2/LPDDR3 mode). - Half bus width mode: Selects the + * HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode) + * . - Quarter bus width mode: UNUSED. To make it unused, this must be tied + * to 4'hF. Valid Range: 0 to 7, and 15 Internal Base: 10 The selected HIF + * address bit is determined by adding the internal base to the value of t + * his field. If set to 15, this column address bit is set to 0. Note: Per + * JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for i + * ndicating auto-precharge, and hence no source address bit can be mapped + * to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for + * auto-precharge in the CA bus and hence column bit 10 is used. + * PSU_DDRC_ADDRMAP4_ADDRMAP_COL_B10 0xf + + * Address Map Register 4 + * (OFFSET, MASK, VALUE) (0XFD070210, 0x00000F0FU ,0x00000F0FU) + */ + PSU_Mask_Write(DDRC_ADDRMAP4_OFFSET, 0x00000F0FU, 0x00000F0FU); +/*##################################################################### */ + + /* + * Register : ADDRMAP5 @ 0XFD070214 + + * Selects the HIF address bit used as row address bit 11. Valid Range: 0 t + * o 11, and 15 Internal Base: 17 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * row address bit 11 is set to 0. + * PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B11 0x8 + + * Selects the HIF address bits used as row address bits 2 to 10. Valid Ran + * ge: 0 to 11, and 15 Internal Base: 8 (for row address bit 2), 9 (for row + * address bit 3), 10 (for row address bit 4) etc increasing to 16 (for ro + * w address bit 10) The selected HIF address bit for each of the row addre + * ss bits is determined by adding the internal base to the value of this f + * ield. When value 15 is used the values of row address bits 2 to 10 are d + * efined by registers ADDRMAP9, ADDRMAP10, ADDRMAP11. + * PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10 0xf + + * Selects the HIF address bits used as row address bit 1. Valid Range: 0 t + * o 11 Internal Base: 7 The selected HIF address bit for each of the row a + * ddress bits is determined by adding the internal base to the value of th + * is field. + * PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B1 0x8 + + * Selects the HIF address bits used as row address bit 0. Valid Range: 0 t + * o 11 Internal Base: 6 The selected HIF address bit for each of the row a + * ddress bits is determined by adding the internal base to the value of th + * is field. + * PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B0 0x8 + + * Address Map Register 5 + * (OFFSET, MASK, VALUE) (0XFD070214, 0x0F0F0F0FU ,0x080F0808U) + */ + PSU_Mask_Write(DDRC_ADDRMAP5_OFFSET, 0x0F0F0F0FU, 0x080F0808U); +/*##################################################################### */ + + /* + * Register : ADDRMAP6 @ 0XFD070218 + + * Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use. - 1 + * - LPDDR3 SDRAM 6Gb/12Gb device in use. Every address having row[14:13]= + * =2'b11 is considered as invalid - 0 - non-LPDDR3 6Gb/12Gb device in use. + * All addresses are valid Present only in designs configured to support L + * PDDR3. + * PSU_DDRC_ADDRMAP6_LPDDR3_6GB_12GB 0x0 + + * Selects the HIF address bit used as row address bit 15. Valid Range: 0 t + * o 11, and 15 Internal Base: 21 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * row address bit 15 is set to 0. + * PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B15 0xf + + * Selects the HIF address bit used as row address bit 14. Valid Range: 0 t + * o 11, and 15 Internal Base: 20 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * row address bit 14 is set to 0. + * PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B14 0x8 + + * Selects the HIF address bit used as row address bit 13. Valid Range: 0 t + * o 11, and 15 Internal Base: 19 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * row address bit 13 is set to 0. + * PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B13 0x8 + + * Selects the HIF address bit used as row address bit 12. Valid Range: 0 t + * o 11, and 15 Internal Base: 18 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * row address bit 12 is set to 0. + * PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B12 0x8 + + * Address Map Register 6 + * (OFFSET, MASK, VALUE) (0XFD070218, 0x8F0F0F0FU ,0x0F080808U) + */ + PSU_Mask_Write(DDRC_ADDRMAP6_OFFSET, 0x8F0F0F0FU, 0x0F080808U); +/*##################################################################### */ + + /* + * Register : ADDRMAP7 @ 0XFD07021C + + * Selects the HIF address bit used as row address bit 17. Valid Range: 0 t + * o 10, and 15 Internal Base: 23 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * row address bit 17 is set to 0. + * PSU_DDRC_ADDRMAP7_ADDRMAP_ROW_B17 0xf + + * Selects the HIF address bit used as row address bit 16. Valid Range: 0 t + * o 11, and 15 Internal Base: 22 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * row address bit 16 is set to 0. + * PSU_DDRC_ADDRMAP7_ADDRMAP_ROW_B16 0xf + + * Address Map Register 7 + * (OFFSET, MASK, VALUE) (0XFD07021C, 0x00000F0FU ,0x00000F0FU) + */ + PSU_Mask_Write(DDRC_ADDRMAP7_OFFSET, 0x00000F0FU, 0x00000F0FU); +/*##################################################################### */ + + /* + * Register : ADDRMAP8 @ 0XFD070220 + + * Selects the HIF address bits used as bank group address bit 1. Valid Ran + * ge: 0 to 30, and 31 Internal Base: 3 The selected HIF address bit for ea + * ch of the bank group address bits is determined by adding the internal b + * ase to the value of this field. If set to 31, bank group address bit 1 i + * s set to 0. + * PSU_DDRC_ADDRMAP8_ADDRMAP_BG_B1 0x8 + + * Selects the HIF address bits used as bank group address bit 0. Valid Ran + * ge: 0 to 30 Internal Base: 2 The selected HIF address bit for each of th + * e bank group address bits is determined by adding the internal base to t + * he value of this field. + * PSU_DDRC_ADDRMAP8_ADDRMAP_BG_B0 0x8 + + * Address Map Register 8 + * (OFFSET, MASK, VALUE) (0XFD070220, 0x00001F1FU ,0x00000808U) + */ + PSU_Mask_Write(DDRC_ADDRMAP8_OFFSET, 0x00001F1FU, 0x00000808U); +/*##################################################################### */ + + /* + * Register : ADDRMAP9 @ 0XFD070224 + + * Selects the HIF address bits used as row address bit 5. Valid Range: 0 t + * o 11 Internal Base: 11 The selected HIF address bit for each of the row + * address bits is determined by adding the internal base to the value of t + * his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + * _10 is set to value 15. + * PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B5 0x8 + + * Selects the HIF address bits used as row address bit 4. Valid Range: 0 t + * o 11 Internal Base: 10 The selected HIF address bit for each of the row + * address bits is determined by adding the internal base to the value of t + * his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + * _10 is set to value 15. + * PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B4 0x8 + + * Selects the HIF address bits used as row address bit 3. Valid Range: 0 t + * o 11 Internal Base: 9 The selected HIF address bit for each of the row a + * ddress bits is determined by adding the internal base to the value of th + * is field. This register field is used only when ADDRMAP5.addrmap_row_b2_ + * 10 is set to value 15. + * PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B3 0x8 + + * Selects the HIF address bits used as row address bit 2. Valid Range: 0 t + * o 11 Internal Base: 8 The selected HIF address bit for each of the row a + * ddress bits is determined by adding the internal base to the value of th + * is field. This register field is used only when ADDRMAP5.addrmap_row_b2_ + * 10 is set to value 15. + * PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B2 0x8 + + * Address Map Register 9 + * (OFFSET, MASK, VALUE) (0XFD070224, 0x0F0F0F0FU ,0x08080808U) + */ + PSU_Mask_Write(DDRC_ADDRMAP9_OFFSET, 0x0F0F0F0FU, 0x08080808U); +/*##################################################################### */ + + /* + * Register : ADDRMAP10 @ 0XFD070228 + + * Selects the HIF address bits used as row address bit 9. Valid Range: 0 t + * o 11 Internal Base: 15 The selected HIF address bit for each of the row + * address bits is determined by adding the internal base to the value of t + * his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + * _10 is set to value 15. + * PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B9 0x8 + + * Selects the HIF address bits used as row address bit 8. Valid Range: 0 t + * o 11 Internal Base: 14 The selected HIF address bit for each of the row + * address bits is determined by adding the internal base to the value of t + * his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + * _10 is set to value 15. + * PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B8 0x8 + + * Selects the HIF address bits used as row address bit 7. Valid Range: 0 t + * o 11 Internal Base: 13 The selected HIF address bit for each of the row + * address bits is determined by adding the internal base to the value of t + * his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + * _10 is set to value 15. + * PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B7 0x8 + + * Selects the HIF address bits used as row address bit 6. Valid Range: 0 t + * o 11 Internal Base: 12 The selected HIF address bit for each of the row + * address bits is determined by adding the internal base to the value of t + * his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + * _10 is set to value 15. + * PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B6 0x8 + + * Address Map Register 10 + * (OFFSET, MASK, VALUE) (0XFD070228, 0x0F0F0F0FU ,0x08080808U) + */ + PSU_Mask_Write(DDRC_ADDRMAP10_OFFSET, 0x0F0F0F0FU, 0x08080808U); +/*##################################################################### */ + + /* + * Register : ADDRMAP11 @ 0XFD07022C + + * Selects the HIF address bits used as row address bit 10. Valid Range: 0 + * to 11 Internal Base: 16 The selected HIF address bit for each of the row + * address bits is determined by adding the internal base to the value of + * this field. This register field is used only when ADDRMAP5.addrmap_row_b + * 2_10 is set to value 15. + * PSU_DDRC_ADDRMAP11_ADDRMAP_ROW_B10 0x8 + + * Address Map Register 11 + * (OFFSET, MASK, VALUE) (0XFD07022C, 0x0000000FU ,0x00000008U) + */ + PSU_Mask_Write(DDRC_ADDRMAP11_OFFSET, 0x0000000FU, 0x00000008U); +/*##################################################################### */ + + /* + * Register : ODTCFG @ 0XFD070240 + + * Cycles to hold ODT for a write command. The minimum supported value is 2 + * . Recommended values: DDR2: - BL8: 0x5 (DDR2-400/533/667), 0x6 (DDR2-800 + * ), 0x7 (DDR2-1066) - BL4: 0x3 (DDR2-400/533/667), 0x4 (DDR2-800), 0x5 (D + * DR2-1066) DDR3: - BL8: 0x6 DDR4: - BL8: 5 + WR_PREAMBLE + CRC_MODE WR_PR + * EAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) CRC_MODE = 0 ( + * not CRC mode), 1 (CRC mode) LPDDR3: - BL8: 7 + RU(tODTon(max)/tCK) + * PSU_DDRC_ODTCFG_WR_ODT_HOLD 0x6 + + * The delay, in clock cycles, from issuing a write command to setting ODT + * values associated with that command. ODT setting must remain constant fo + * r the entire time that DQS is driven by the uMCTL2. Recommended values: + * DDR2: - CWL + AL - 3 (DDR2-400/533/667), CWL + AL - 4 (DDR2-800), CWL + + * AL - 5 (DDR2-1066) If (CWL + AL - 3 < 0), uMCTL2 does not support ODT fo + * r write operation. DDR3: - 0x0 DDR4: - DFITMG1.dfi_t_cmd_lat (to adjust + * for CAL mode) LPDDR3: - WL - 1 - RU(tODTon(max)/tCK)) + * PSU_DDRC_ODTCFG_WR_ODT_DELAY 0x0 + + * Cycles to hold ODT for a read command. The minimum supported value is 2. + * Recommended values: DDR2: - BL8: 0x6 (not DDR2-1066), 0x7 (DDR2-1066) - + * BL4: 0x4 (not DDR2-1066), 0x5 (DDR2-1066) DDR3: - BL8 - 0x6 DDR4: - BL8 + * : 5 + RD_PREAMBLE RD_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write p + * reamble) LPDDR3: - BL8: 5 + RU(tDQSCK(max)/tCK) - RD(tDQSCK(min)/tCK) + + * RU(tODTon(max)/tCK) + * PSU_DDRC_ODTCFG_RD_ODT_HOLD 0x6 + + * The delay, in clock cycles, from issuing a read command to setting ODT v + * alues associated with that command. ODT setting must remain constant for + * the entire time that DQS is driven by the uMCTL2. Recommended values: D + * DR2: - CL + AL - 4 (not DDR2-1066), CL + AL - 5 (DDR2-1066) If (CL + AL + * - 4 < 0), uMCTL2 does not support ODT for read operation. DDR3: - CL - C + * WL DDR4: - CL - CWL - RD_PREAMBLE + WR_PREAMBLE + DFITMG1.dfi_t_cmd_lat + * (to adjust for CAL mode) WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK + * write preamble) RD_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write pre + * amble) If (CL - CWL - RD_PREAMBLE + WR_PREAMBLE) < 0, uMCTL2 does not su + * pport ODT for read operation. LPDDR3: - RL + RD(tDQSCK(min)/tCK) - 1 - R + * U(tODTon(max)/tCK) + * PSU_DDRC_ODTCFG_RD_ODT_DELAY 0x0 + + * ODT Configuration Register + * (OFFSET, MASK, VALUE) (0XFD070240, 0x0F1F0F7CU ,0x06000600U) + */ + PSU_Mask_Write(DDRC_ODTCFG_OFFSET, 0x0F1F0F7CU, 0x06000600U); +/*##################################################################### */ + + /* + * Register : ODTMAP @ 0XFD070244 + + * Indicates which remote ODTs must be turned on during a read from rank 1. + * Each rank has a remote ODT (in the SDRAM) which can be turned on by set + * ting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 i + * s controlled by bit next to the LSB, etc. For each rank, set its bit to + * 1 to enable its ODT. Present only in configurations that have 2 or more + * ranks + * PSU_DDRC_ODTMAP_RANK1_RD_ODT 0x0 + + * Indicates which remote ODTs must be turned on during a write to rank 1. + * Each rank has a remote ODT (in the SDRAM) which can be turned on by sett + * ing the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is + * controlled by bit next to the LSB, etc. For each rank, set its bit to 1 + * to enable its ODT. Present only in configurations that have 2 or more r + * anks + * PSU_DDRC_ODTMAP_RANK1_WR_ODT 0x0 + + * Indicates which remote ODTs must be turned on during a read from rank 0. + * Each rank has a remote ODT (in the SDRAM) which can be turned on by set + * ting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 i + * s controlled by bit next to the LSB, etc. For each rank, set its bit to + * 1 to enable its ODT. + * PSU_DDRC_ODTMAP_RANK0_RD_ODT 0x0 + + * Indicates which remote ODTs must be turned on during a write to rank 0. + * Each rank has a remote ODT (in the SDRAM) which can be turned on by sett + * ing the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is + * controlled by bit next to the LSB, etc. For each rank, set its bit to 1 + * to enable its ODT. + * PSU_DDRC_ODTMAP_RANK0_WR_ODT 0x1 + + * ODT/Rank Map Register + * (OFFSET, MASK, VALUE) (0XFD070244, 0x00003333U ,0x00000001U) + */ + PSU_Mask_Write(DDRC_ODTMAP_OFFSET, 0x00003333U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : SCHED @ 0XFD070250 + + * When the preferred transaction store is empty for these many clock cycle + * s, switch to the alternate transaction store if it is non-empty. The rea + * d transaction store (both high and low priority) is the default preferre + * d transaction store and the write transaction store is the alternative s + * tore. When prefer write over read is set this is reversed. 0x0 is a lega + * l value for this register. When set to 0x0, the transaction store switch + * ing will happen immediately when the switching conditions become true. F + * OR PERFORMANCE ONLY + * PSU_DDRC_SCHED_RDWR_IDLE_GAP 0x1 + + * UNUSED + * PSU_DDRC_SCHED_GO2CRITICAL_HYSTERESIS 0x0 + + * Number of entries in the low priority transaction store is this value + + * 1. (MEMC_NO_OF_ENTRY - (SCHED.lpr_num_entries + 1)) is the number of ent + * ries available for the high priority transaction store. Setting this to + * maximum value allocates all entries to low priority transaction store. S + * etting this to 0 allocates 1 entry to low priority transaction store and + * the rest to high priority transaction store. Note: In ECC configuration + * s, the numbers of write and low priority read credits issued is one less + * than in the non-ECC case. One entry each is reserved in the write and l + * ow-priority read CAMs for storing the RMW requests arising out of single + * bit error correction RMW operation. + * PSU_DDRC_SCHED_LPR_NUM_ENTRIES 0x20 + + * If true, bank is kept open only while there are page hit transactions av + * ailable in the CAM to that bank. The last read or write command in the C + * AM with a bank and page hit will be executed with auto-precharge if SCHE + * D1.pageclose_timer=0. Even if this register set to 1 and SCHED1.pageclos + * e_timer is set to 0, explicit precharge (and not auto-precharge) may be + * issued in some cases where there is a mode switch between Write and Read + * or between LPR and HPR. The Read and Write commands that are executed a + * s part of the ECC scrub requests are also executed without auto-precharg + * e. If false, the bank remains open until there is a need to close it (to + * open a different page, or for page timeout or refresh timeout) - also k + * nown as open page policy. The open page policy can be overridden by sett + * ing the per-command-autopre bit on the HIF interface (hif_cmd_autopre). + * The pageclose feature provids a midway between Open and Close page polic + * ies. FOR PERFORMANCE ONLY. + * PSU_DDRC_SCHED_PAGECLOSE 0x0 + + * If set then the bank selector prefers writes over reads. FOR DEBUG ONLY. + * PSU_DDRC_SCHED_PREFER_WRITE 0x0 + + * Active low signal. When asserted ('0'), all incoming transactions are fo + * rced to low priority. This implies that all High Priority Read (HPR) and + * Variable Priority Read commands (VPR) will be treated as Low Priority R + * ead (LPR) commands. On the write side, all Variable Priority Write (VPW) + * commands will be treated as Normal Priority Write (NPW) commands. Forci + * ng the incoming transactions to low priority implicitly turns off Bypass + * path for read commands. FOR PERFORMANCE ONLY. + * PSU_DDRC_SCHED_FORCE_LOW_PRI_N 0x1 + + * Scheduler Control Register + * (OFFSET, MASK, VALUE) (0XFD070250, 0x7FFF3F07U ,0x01002001U) + */ + PSU_Mask_Write(DDRC_SCHED_OFFSET, 0x7FFF3F07U, 0x01002001U); +/*##################################################################### */ + + /* + * Register : PERFLPR1 @ 0XFD070264 + + * Number of transactions that are serviced once the LPR queue goes critica + * l is the smaller of: - (a) This number - (b) Number of transactions avai + * lable. Unit: Transaction. FOR PERFORMANCE ONLY. + * PSU_DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH 0x8 + + * Number of clocks that the LPR queue can be starved before it goes critic + * al. The minimum valid functional value for this register is 0x1. Program + * ming it to 0x0 will disable the starvation functionality; during normal + * operation, this function should not be disabled as it will cause excessi + * ve latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY. + * PSU_DDRC_PERFLPR1_LPR_MAX_STARVE 0x40 + + * Low Priority Read CAM Register 1 + * (OFFSET, MASK, VALUE) (0XFD070264, 0xFF00FFFFU ,0x08000040U) + */ + PSU_Mask_Write(DDRC_PERFLPR1_OFFSET, 0xFF00FFFFU, 0x08000040U); +/*##################################################################### */ + + /* + * Register : PERFWR1 @ 0XFD07026C + + * Number of transactions that are serviced once the WR queue goes critical + * is the smaller of: - (a) This number - (b) Number of transactions avail + * able. Unit: Transaction. FOR PERFORMANCE ONLY. + * PSU_DDRC_PERFWR1_W_XACT_RUN_LENGTH 0x8 + + * Number of clocks that the WR queue can be starved before it goes critica + * l. The minimum valid functional value for this register is 0x1. Programm + * ing it to 0x0 will disable the starvation functionality; during normal o + * peration, this function should not be disabled as it will cause excessiv + * e latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY. + * PSU_DDRC_PERFWR1_W_MAX_STARVE 0x40 + + * Write CAM Register 1 + * (OFFSET, MASK, VALUE) (0XFD07026C, 0xFF00FFFFU ,0x08000040U) + */ + PSU_Mask_Write(DDRC_PERFWR1_OFFSET, 0xFF00FFFFU, 0x08000040U); +/*##################################################################### */ + + /* + * Register : DQMAP0 @ 0XFD070280 + + * DQ nibble map for DQ bits [12-15] Present only in designs configured to + * support DDR4. + * PSU_DDRC_DQMAP0_DQ_NIBBLE_MAP_12_15 0x0 + + * DQ nibble map for DQ bits [8-11] Present only in designs configured to s + * upport DDR4. + * PSU_DDRC_DQMAP0_DQ_NIBBLE_MAP_8_11 0x0 + + * DQ nibble map for DQ bits [4-7] Present only in designs configured to su + * pport DDR4. + * PSU_DDRC_DQMAP0_DQ_NIBBLE_MAP_4_7 0x0 + + * DQ nibble map for DQ bits [0-3] Present only in designs configured to su + * pport DDR4. + * PSU_DDRC_DQMAP0_DQ_NIBBLE_MAP_0_3 0x0 + + * DQ Map Register 0 + * (OFFSET, MASK, VALUE) (0XFD070280, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDRC_DQMAP0_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : DQMAP1 @ 0XFD070284 + + * DQ nibble map for DQ bits [28-31] Present only in designs configured to + * support DDR4. + * PSU_DDRC_DQMAP1_DQ_NIBBLE_MAP_28_31 0x0 + + * DQ nibble map for DQ bits [24-27] Present only in designs configured to + * support DDR4. + * PSU_DDRC_DQMAP1_DQ_NIBBLE_MAP_24_27 0x0 + + * DQ nibble map for DQ bits [20-23] Present only in designs configured to + * support DDR4. + * PSU_DDRC_DQMAP1_DQ_NIBBLE_MAP_20_23 0x0 + + * DQ nibble map for DQ bits [16-19] Present only in designs configured to + * support DDR4. + * PSU_DDRC_DQMAP1_DQ_NIBBLE_MAP_16_19 0x0 + + * DQ Map Register 1 + * (OFFSET, MASK, VALUE) (0XFD070284, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDRC_DQMAP1_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : DQMAP2 @ 0XFD070288 + + * DQ nibble map for DQ bits [44-47] Present only in designs configured to + * support DDR4. + * PSU_DDRC_DQMAP2_DQ_NIBBLE_MAP_44_47 0x0 + + * DQ nibble map for DQ bits [40-43] Present only in designs configured to + * support DDR4. + * PSU_DDRC_DQMAP2_DQ_NIBBLE_MAP_40_43 0x0 + + * DQ nibble map for DQ bits [36-39] Present only in designs configured to + * support DDR4. + * PSU_DDRC_DQMAP2_DQ_NIBBLE_MAP_36_39 0x0 + + * DQ nibble map for DQ bits [32-35] Present only in designs configured to + * support DDR4. + * PSU_DDRC_DQMAP2_DQ_NIBBLE_MAP_32_35 0x0 + + * DQ Map Register 2 + * (OFFSET, MASK, VALUE) (0XFD070288, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDRC_DQMAP2_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : DQMAP3 @ 0XFD07028C + + * DQ nibble map for DQ bits [60-63] Present only in designs configured to + * support DDR4. + * PSU_DDRC_DQMAP3_DQ_NIBBLE_MAP_60_63 0x0 + + * DQ nibble map for DQ bits [56-59] Present only in designs configured to + * support DDR4. + * PSU_DDRC_DQMAP3_DQ_NIBBLE_MAP_56_59 0x0 + + * DQ nibble map for DQ bits [52-55] Present only in designs configured to + * support DDR4. + * PSU_DDRC_DQMAP3_DQ_NIBBLE_MAP_52_55 0x0 + + * DQ nibble map for DQ bits [48-51] Present only in designs configured to + * support DDR4. + * PSU_DDRC_DQMAP3_DQ_NIBBLE_MAP_48_51 0x0 + + * DQ Map Register 3 + * (OFFSET, MASK, VALUE) (0XFD07028C, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDRC_DQMAP3_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : DQMAP4 @ 0XFD070290 + + * DQ nibble map for DIMM ECC check bits [4-7] Present only in designs conf + * igured to support DDR4. + * PSU_DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_4_7 0x0 + + * DQ nibble map for DIMM ECC check bits [0-3] Present only in designs conf + * igured to support DDR4. + * PSU_DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_0_3 0x0 + + * DQ Map Register 4 + * (OFFSET, MASK, VALUE) (0XFD070290, 0x0000FFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDRC_DQMAP4_OFFSET, 0x0000FFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : DQMAP5 @ 0XFD070294 + + * All even ranks have the same DQ mapping controled by DQMAP0-4 register a + * s rank 0. This register provides DQ swap function for all odd ranks to s + * upport CRC feature. rank based DQ swapping is: swap bit 0 with 1, swap b + * it 2 with 3, swap bit 4 with 5 and swap bit 6 with 7. 1: Disable rank ba + * sed DQ swapping 0: Enable rank based DQ swapping Present only in designs + * configured to support DDR4. + * PSU_DDRC_DQMAP5_DIS_DQ_RANK_SWAP 0x1 + + * DQ Map Register 5 + * (OFFSET, MASK, VALUE) (0XFD070294, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(DDRC_DQMAP5_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : DBG0 @ 0XFD070300 + + * When this is set to '0', auto-precharge is disabled for the flushed comm + * and in a collision case. Collision cases are write followed by read to s + * ame address, read followed by write to same address, or write followed b + * y write to same address with DBG0.dis_wc bit = 1 (where same address com + * parisons exclude the two address bits representing critical word). FOR D + * EBUG ONLY. + * PSU_DDRC_DBG0_DIS_COLLISION_PAGE_OPT 0x0 + + * When 1, disable write combine. FOR DEBUG ONLY + * PSU_DDRC_DBG0_DIS_WC 0x0 + + * Debug Register 0 + * (OFFSET, MASK, VALUE) (0XFD070300, 0x00000011U ,0x00000000U) + */ + PSU_Mask_Write(DDRC_DBG0_OFFSET, 0x00000011U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : DBGCMD @ 0XFD07030C + + * Setting this register bit to 1 allows refresh and ZQCS commands to be tr + * iggered from hardware via the IOs ext_*. If set to 1, the fields DBGCMD. + * zq_calib_short and DBGCMD.rank*_refresh have no function, and are ignore + * d by the uMCTL2 logic. Setting this register bit to 0 allows refresh and + * ZQCS to be triggered from software, via the fields DBGCMD.zq_calib_shor + * t and DBGCMD.rank*_refresh. If set to 0, the hardware pins ext_* have no + * function, and are ignored by the uMCTL2 logic. This register is static, + * and may only be changed when the DDRC reset signal, core_ddrc_rstn, is + * asserted (0). + * PSU_DDRC_DBGCMD_HW_REF_ZQ_EN 0x0 + + * Setting this register bit to 1 indicates to the uMCTL2 to issue a dfi_ct + * rlupd_req to the PHY. When this request is stored in the uMCTL2, the bit + * is automatically cleared. This operation must only be performed when DF + * IUPD0.dis_auto_ctrlupd=1. + * PSU_DDRC_DBGCMD_CTRLUPD 0x0 + + * Setting this register bit to 1 indicates to the uMCTL2 to issue a ZQCS ( + * ZQ calibration short)/MPC(ZQ calibration) command to the SDRAM. When thi + * s request is stored in the uMCTL2, the bit is automatically cleared. Thi + * s operation can be performed only when ZQCTL0.dis_auto_zq=1. It is recom + * mended NOT to set this register bit if in Init operating mode. This regi + * ster bit is ignored when in Self-Refresh(except LPDDR4) and SR-Powerdown + * (LPDDR4) and Deep power-down operating modes and Maximum Power Saving Mo + * de. + * PSU_DDRC_DBGCMD_ZQ_CALIB_SHORT 0x0 + + * Setting this register bit to 1 indicates to the uMCTL2 to issue a refres + * h to rank 1. Writing to this bit causes DBGSTAT.rank1_refresh_busy to be + * set. When DBGSTAT.rank1_refresh_busy is cleared, the command has been s + * tored in uMCTL2. This operation can be performed only when RFSHCTL3.dis_ + * auto_refresh=1. It is recommended NOT to set this register bit if in Ini + * t or Deep power-down operating modes or Maximum Power Saving Mode. + * PSU_DDRC_DBGCMD_RANK1_REFRESH 0x0 + + * Setting this register bit to 1 indicates to the uMCTL2 to issue a refres + * h to rank 0. Writing to this bit causes DBGSTAT.rank0_refresh_busy to be + * set. When DBGSTAT.rank0_refresh_busy is cleared, the command has been s + * tored in uMCTL2. This operation can be performed only when RFSHCTL3.dis_ + * auto_refresh=1. It is recommended NOT to set this register bit if in Ini + * t or Deep power-down operating modes or Maximum Power Saving Mode. + * PSU_DDRC_DBGCMD_RANK0_REFRESH 0x0 + + * Command Debug Register + * (OFFSET, MASK, VALUE) (0XFD07030C, 0x80000033U ,0x00000000U) + */ + PSU_Mask_Write(DDRC_DBGCMD_OFFSET, 0x80000033U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : SWCTL @ 0XFD070320 + + * Enable quasi-dynamic register programming outside reset. Program registe + * r to 0 to enable quasi-dynamic programming. Set back register to 1 once + * programming is done. + * PSU_DDRC_SWCTL_SW_DONE 0x0 + + * Software register programming control enable + * (OFFSET, MASK, VALUE) (0XFD070320, 0x00000001U ,0x00000000U) + */ + PSU_Mask_Write(DDRC_SWCTL_OFFSET, 0x00000001U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : PCCFG @ 0XFD070400 + + * Burst length expansion mode. By default (i.e. bl_exp_mode==0) XPI expand + * s every AXI burst into multiple HIF commands, using the memory burst len + * gth as a unit. If set to 1, then XPI will use half of the memory burst l + * ength as a unit. This applies to both reads and writes. When MSTR.data_b + * us_width==00, setting bl_exp_mode to 1 has no effect. This can be used i + * n cases where Partial Writes is enabled (UMCTL2_PARTIAL_WR=1) and DBG0.d + * is_wc=1, in order to avoid or minimize t_ccd_l penalty in DDR4 and t_ccd + * _mw penalty in LPDDR4. Note that if DBICTL.reg_ddrc_dm_en=0, functionali + * ty is not supported in the following cases: - UMCTL2_PARTIAL_WR=0 - UMCT + * L2_PARTIAL_WR=1, MSTR.reg_ddrc_data_bus_width=01, MEMC_BURST_LENGTH=8 an + * d MSTR.reg_ddrc_burst_rdwr=1000 (LPDDR4 only) - UMCTL2_PARTIAL_WR=1, MST + * R.reg_ddrc_data_bus_width=01, MEMC_BURST_LENGTH=4 and MSTR.reg_ddrc_burs + * t_rdwr=0100 (DDR4 only), with either MSTR.reg_ddrc_burstchop=0 or CRCPAR + * CTL1.reg_ddrc_crc_enable=1 Functionality is also not supported if Shared + * -AC is enabled + * PSU_DDRC_PCCFG_BL_EXP_MODE 0x0 + + * Page match four limit. If set to 1, limits the number of consecutive sam + * e page DDRC transactions that can be granted by the Port Arbiter to four + * when Page Match feature is enabled. If set to 0, there is no limit impo + * sed on number of consecutive same page DDRC transactions. + * PSU_DDRC_PCCFG_PAGEMATCH_LIMIT 0x0 + + * If set to 1 (enabled), sets co_gs_go2critical_wr and co_gs_go2critical_l + * pr/co_gs_go2critical_hpr signals going to DDRC based on urgent input (aw + * urgent, arurgent) coming from AXI master. If set to 0 (disabled), co_gs_ + * go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals a + * t DDRC are driven to 1b'0. + * PSU_DDRC_PCCFG_GO2CRITICAL_EN 0x1 + + * Port Common Configuration Register + * (OFFSET, MASK, VALUE) (0XFD070400, 0x00000111U ,0x00000001U) + */ + PSU_Mask_Write(DDRC_PCCFG_OFFSET, 0x00000111U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : PCFGR_0 @ 0XFD070404 + + * If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. + * PSU_DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN 0x0 + + * If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + * bled and arurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + * urgent signal can be asserted anytime and as long as required which is i + * ndependent of address handshaking (it is not associated with any particu + * lar command). + * PSU_DDRC_PCFGR_0_RD_PORT_URGENT_EN 0x1 + + * If set to 1, enables aging function for the read channel of the port. + * PSU_DDRC_PCFGR_0_RD_PORT_AGING_EN 0x0 + + * Determines the initial load value of read aging counters. These counters + * will be parallel loaded after reset, or after each grant to the corresp + * onding port. The aging counters down-count every clock cycle where the p + * ort is requesting but not granted. The higher significant 5-bits of the + * read aging counter sets the priority of the read channel of a given port + * . Port's priority will increase as the higher significant 5-bits of the + * counter starts to decrease. When the aging counter becomes 0, the corres + * ponding port channel will have the highest priority level (timeout condi + * tion - Priority0). For multi-port configurations, the aging counters can + * not be used to set port priorities when external dynamic priority inputs + * (arqos) are enabled (timeout is still applicable). For single port conf + * igurations, the aging counters are only used when they timeout (become 0 + * ) to force read-write direction switching. In this case, external dynami + * c priority input, arqos (for reads only) can still be used to set the DD + * RC read priority (2 priority levels: low priority read - LPR, high prior + * ity read - HPR) on a command by command basis. Note: The two LSBs of thi + * s register field are tied internally to 2'b00. + * PSU_DDRC_PCFGR_0_RD_PORT_PRIORITY 0xf + + * Port n Configuration Read Register + * (OFFSET, MASK, VALUE) (0XFD070404, 0x000073FFU ,0x0000200FU) + */ + PSU_Mask_Write(DDRC_PCFGR_0_OFFSET, 0x000073FFU, 0x0000200FU); +/*##################################################################### */ + + /* + * Register : PCFGW_0 @ 0XFD070408 + + * If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. + * PSU_DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN 0x0 + + * If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + * bled and awurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + * serted anytime and as long as required which is independent of address h + * andshaking (it is not associated with any particular command). + * PSU_DDRC_PCFGW_0_WR_PORT_URGENT_EN 0x1 + + * If set to 1, enables aging function for the write channel of the port. + * PSU_DDRC_PCFGW_0_WR_PORT_AGING_EN 0x0 + + * Determines the initial load value of write aging counters. These counter + * s will be parallel loaded after reset, or after each grant to the corres + * ponding port. The aging counters down-count every clock cycle where the + * port is requesting but not granted. The higher significant 5-bits of the + * write aging counter sets the initial priority of the write channel of a + * given port. Port's priority will increase as the higher significant 5-b + * its of the counter starts to decrease. When the aging counter becomes 0, + * the corresponding port channel will have the highest priority level. Fo + * r multi-port configurations, the aging counters cannot be used to set po + * rt priorities when external dynamic priority inputs (awqos) are enabled + * (timeout is still applicable). For single port configurations, the aging + * counters are only used when they timeout (become 0) to force read-write + * direction switching. Note: The two LSBs of this register field are tied + * internally to 2'b00. + * PSU_DDRC_PCFGW_0_WR_PORT_PRIORITY 0xf + + * Port n Configuration Write Register + * (OFFSET, MASK, VALUE) (0XFD070408, 0x000073FFU ,0x0000200FU) + */ + PSU_Mask_Write(DDRC_PCFGW_0_OFFSET, 0x000073FFU, 0x0000200FU); +/*##################################################################### */ + + /* + * Register : PCTRL_0 @ 0XFD070490 + + * Enables port n. + * PSU_DDRC_PCTRL_0_PORT_EN 0x1 + + * Port n Control Register + * (OFFSET, MASK, VALUE) (0XFD070490, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(DDRC_PCTRL_0_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : PCFGQOS0_0 @ 0XFD070494 + + * This bitfield indicates the traffic class of region 1. Valid values are: + * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + * maps to the blue address queue. In this case, valid values are 0: LPR a + * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. + * PSU_DDRC_PCFGQOS0_0_RQOS_MAP_REGION1 0x2 + + * This bitfield indicates the traffic class of region 0. Valid values are: + * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + * maps to the blue address queue. In this case, valid values are: 0: LPR + * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. + * PSU_DDRC_PCFGQOS0_0_RQOS_MAP_REGION0 0x0 + + * Separation level1 indicating the end of region0 mapping; start of region + * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + * lues are used directly as port priorities, where the higher the value co + * rresponds to higher port priority. All of the map_level* registers must + * be set to distinct values. + * PSU_DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1 0xb + + * Port n Read QoS Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD070494, 0x0033000FU ,0x0020000BU) + */ + PSU_Mask_Write(DDRC_PCFGQOS0_0_OFFSET, 0x0033000FU, 0x0020000BU); +/*##################################################################### */ + + /* + * Register : PCFGQOS1_0 @ 0XFD070498 + + * Specifies the timeout value for transactions mapped to the red address q + * ueue. + * PSU_DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR 0x0 + + * Specifies the timeout value for transactions mapped to the blue address + * queue. + * PSU_DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB 0x0 + + * Port n Read QoS Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD070498, 0x07FF07FFU ,0x00000000U) + */ + PSU_Mask_Write(DDRC_PCFGQOS1_0_OFFSET, 0x07FF07FFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : PCFGR_1 @ 0XFD0704B4 + + * If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. + * PSU_DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN 0x0 + + * If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + * bled and arurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + * urgent signal can be asserted anytime and as long as required which is i + * ndependent of address handshaking (it is not associated with any particu + * lar command). + * PSU_DDRC_PCFGR_1_RD_PORT_URGENT_EN 0x1 + + * If set to 1, enables aging function for the read channel of the port. + * PSU_DDRC_PCFGR_1_RD_PORT_AGING_EN 0x0 + + * Determines the initial load value of read aging counters. These counters + * will be parallel loaded after reset, or after each grant to the corresp + * onding port. The aging counters down-count every clock cycle where the p + * ort is requesting but not granted. The higher significant 5-bits of the + * read aging counter sets the priority of the read channel of a given port + * . Port's priority will increase as the higher significant 5-bits of the + * counter starts to decrease. When the aging counter becomes 0, the corres + * ponding port channel will have the highest priority level (timeout condi + * tion - Priority0). For multi-port configurations, the aging counters can + * not be used to set port priorities when external dynamic priority inputs + * (arqos) are enabled (timeout is still applicable). For single port conf + * igurations, the aging counters are only used when they timeout (become 0 + * ) to force read-write direction switching. In this case, external dynami + * c priority input, arqos (for reads only) can still be used to set the DD + * RC read priority (2 priority levels: low priority read - LPR, high prior + * ity read - HPR) on a command by command basis. Note: The two LSBs of thi + * s register field are tied internally to 2'b00. + * PSU_DDRC_PCFGR_1_RD_PORT_PRIORITY 0xf + + * Port n Configuration Read Register + * (OFFSET, MASK, VALUE) (0XFD0704B4, 0x000073FFU ,0x0000200FU) + */ + PSU_Mask_Write(DDRC_PCFGR_1_OFFSET, 0x000073FFU, 0x0000200FU); +/*##################################################################### */ + + /* + * Register : PCFGW_1 @ 0XFD0704B8 + + * If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. + * PSU_DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN 0x0 + + * If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + * bled and awurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + * serted anytime and as long as required which is independent of address h + * andshaking (it is not associated with any particular command). + * PSU_DDRC_PCFGW_1_WR_PORT_URGENT_EN 0x1 + + * If set to 1, enables aging function for the write channel of the port. + * PSU_DDRC_PCFGW_1_WR_PORT_AGING_EN 0x0 + + * Determines the initial load value of write aging counters. These counter + * s will be parallel loaded after reset, or after each grant to the corres + * ponding port. The aging counters down-count every clock cycle where the + * port is requesting but not granted. The higher significant 5-bits of the + * write aging counter sets the initial priority of the write channel of a + * given port. Port's priority will increase as the higher significant 5-b + * its of the counter starts to decrease. When the aging counter becomes 0, + * the corresponding port channel will have the highest priority level. Fo + * r multi-port configurations, the aging counters cannot be used to set po + * rt priorities when external dynamic priority inputs (awqos) are enabled + * (timeout is still applicable). For single port configurations, the aging + * counters are only used when they timeout (become 0) to force read-write + * direction switching. Note: The two LSBs of this register field are tied + * internally to 2'b00. + * PSU_DDRC_PCFGW_1_WR_PORT_PRIORITY 0xf + + * Port n Configuration Write Register + * (OFFSET, MASK, VALUE) (0XFD0704B8, 0x000073FFU ,0x0000200FU) + */ + PSU_Mask_Write(DDRC_PCFGW_1_OFFSET, 0x000073FFU, 0x0000200FU); +/*##################################################################### */ + + /* + * Register : PCTRL_1 @ 0XFD070540 + + * Enables port n. + * PSU_DDRC_PCTRL_1_PORT_EN 0x1 + + * Port n Control Register + * (OFFSET, MASK, VALUE) (0XFD070540, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(DDRC_PCTRL_1_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : PCFGQOS0_1 @ 0XFD070544 + + * This bitfield indicates the traffic class of region2. For dual address q + * ueue configurations, region2 maps to the red address queue. Valid values + * are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN + * = 0) and traffic class of region2 is set to 1 (VPR), VPR traffic is ali + * ased to LPR traffic. + * PSU_DDRC_PCFGQOS0_1_RQOS_MAP_REGION2 0x2 + + * This bitfield indicates the traffic class of region 1. Valid values are: + * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + * maps to the blue address queue. In this case, valid values are 0: LPR a + * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. + * PSU_DDRC_PCFGQOS0_1_RQOS_MAP_REGION1 0x0 + + * This bitfield indicates the traffic class of region 0. Valid values are: + * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + * maps to the blue address queue. In this case, valid values are: 0: LPR + * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. + * PSU_DDRC_PCFGQOS0_1_RQOS_MAP_REGION0 0x0 + + * Separation level2 indicating the end of region1 mapping; start of region + * 1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 whi + * ch corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note + * that for PA, arqos values are used directly as port priorities, where t + * he higher the value corresponds to higher port priority. All of the map_ + * level* registers must be set to distinct values. + * PSU_DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2 0xb + + * Separation level1 indicating the end of region0 mapping; start of region + * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + * lues are used directly as port priorities, where the higher the value co + * rresponds to higher port priority. All of the map_level* registers must + * be set to distinct values. + * PSU_DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1 0x3 + + * Port n Read QoS Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD070544, 0x03330F0FU ,0x02000B03U) + */ + PSU_Mask_Write(DDRC_PCFGQOS0_1_OFFSET, 0x03330F0FU, 0x02000B03U); +/*##################################################################### */ + + /* + * Register : PCFGQOS1_1 @ 0XFD070548 + + * Specifies the timeout value for transactions mapped to the red address q + * ueue. + * PSU_DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR 0x0 + + * Specifies the timeout value for transactions mapped to the blue address + * queue. + * PSU_DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB 0x0 + + * Port n Read QoS Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD070548, 0x07FF07FFU ,0x00000000U) + */ + PSU_Mask_Write(DDRC_PCFGQOS1_1_OFFSET, 0x07FF07FFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : PCFGR_2 @ 0XFD070564 + + * If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. + * PSU_DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN 0x0 + + * If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + * bled and arurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + * urgent signal can be asserted anytime and as long as required which is i + * ndependent of address handshaking (it is not associated with any particu + * lar command). + * PSU_DDRC_PCFGR_2_RD_PORT_URGENT_EN 0x1 + + * If set to 1, enables aging function for the read channel of the port. + * PSU_DDRC_PCFGR_2_RD_PORT_AGING_EN 0x0 + + * Determines the initial load value of read aging counters. These counters + * will be parallel loaded after reset, or after each grant to the corresp + * onding port. The aging counters down-count every clock cycle where the p + * ort is requesting but not granted. The higher significant 5-bits of the + * read aging counter sets the priority of the read channel of a given port + * . Port's priority will increase as the higher significant 5-bits of the + * counter starts to decrease. When the aging counter becomes 0, the corres + * ponding port channel will have the highest priority level (timeout condi + * tion - Priority0). For multi-port configurations, the aging counters can + * not be used to set port priorities when external dynamic priority inputs + * (arqos) are enabled (timeout is still applicable). For single port conf + * igurations, the aging counters are only used when they timeout (become 0 + * ) to force read-write direction switching. In this case, external dynami + * c priority input, arqos (for reads only) can still be used to set the DD + * RC read priority (2 priority levels: low priority read - LPR, high prior + * ity read - HPR) on a command by command basis. Note: The two LSBs of thi + * s register field are tied internally to 2'b00. + * PSU_DDRC_PCFGR_2_RD_PORT_PRIORITY 0xf + + * Port n Configuration Read Register + * (OFFSET, MASK, VALUE) (0XFD070564, 0x000073FFU ,0x0000200FU) + */ + PSU_Mask_Write(DDRC_PCFGR_2_OFFSET, 0x000073FFU, 0x0000200FU); +/*##################################################################### */ + + /* + * Register : PCFGW_2 @ 0XFD070568 + + * If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. + * PSU_DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN 0x0 + + * If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + * bled and awurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + * serted anytime and as long as required which is independent of address h + * andshaking (it is not associated with any particular command). + * PSU_DDRC_PCFGW_2_WR_PORT_URGENT_EN 0x1 + + * If set to 1, enables aging function for the write channel of the port. + * PSU_DDRC_PCFGW_2_WR_PORT_AGING_EN 0x0 + + * Determines the initial load value of write aging counters. These counter + * s will be parallel loaded after reset, or after each grant to the corres + * ponding port. The aging counters down-count every clock cycle where the + * port is requesting but not granted. The higher significant 5-bits of the + * write aging counter sets the initial priority of the write channel of a + * given port. Port's priority will increase as the higher significant 5-b + * its of the counter starts to decrease. When the aging counter becomes 0, + * the corresponding port channel will have the highest priority level. Fo + * r multi-port configurations, the aging counters cannot be used to set po + * rt priorities when external dynamic priority inputs (awqos) are enabled + * (timeout is still applicable). For single port configurations, the aging + * counters are only used when they timeout (become 0) to force read-write + * direction switching. Note: The two LSBs of this register field are tied + * internally to 2'b00. + * PSU_DDRC_PCFGW_2_WR_PORT_PRIORITY 0xf + + * Port n Configuration Write Register + * (OFFSET, MASK, VALUE) (0XFD070568, 0x000073FFU ,0x0000200FU) + */ + PSU_Mask_Write(DDRC_PCFGW_2_OFFSET, 0x000073FFU, 0x0000200FU); +/*##################################################################### */ + + /* + * Register : PCTRL_2 @ 0XFD0705F0 + + * Enables port n. + * PSU_DDRC_PCTRL_2_PORT_EN 0x1 + + * Port n Control Register + * (OFFSET, MASK, VALUE) (0XFD0705F0, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(DDRC_PCTRL_2_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : PCFGQOS0_2 @ 0XFD0705F4 + + * This bitfield indicates the traffic class of region2. For dual address q + * ueue configurations, region2 maps to the red address queue. Valid values + * are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN + * = 0) and traffic class of region2 is set to 1 (VPR), VPR traffic is ali + * ased to LPR traffic. + * PSU_DDRC_PCFGQOS0_2_RQOS_MAP_REGION2 0x2 + + * This bitfield indicates the traffic class of region 1. Valid values are: + * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + * maps to the blue address queue. In this case, valid values are 0: LPR a + * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. + * PSU_DDRC_PCFGQOS0_2_RQOS_MAP_REGION1 0x0 + + * This bitfield indicates the traffic class of region 0. Valid values are: + * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + * maps to the blue address queue. In this case, valid values are: 0: LPR + * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. + * PSU_DDRC_PCFGQOS0_2_RQOS_MAP_REGION0 0x0 + + * Separation level2 indicating the end of region1 mapping; start of region + * 1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 whi + * ch corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note + * that for PA, arqos values are used directly as port priorities, where t + * he higher the value corresponds to higher port priority. All of the map_ + * level* registers must be set to distinct values. + * PSU_DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2 0xb + + * Separation level1 indicating the end of region0 mapping; start of region + * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + * lues are used directly as port priorities, where the higher the value co + * rresponds to higher port priority. All of the map_level* registers must + * be set to distinct values. + * PSU_DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1 0x3 + + * Port n Read QoS Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD0705F4, 0x03330F0FU ,0x02000B03U) + */ + PSU_Mask_Write(DDRC_PCFGQOS0_2_OFFSET, 0x03330F0FU, 0x02000B03U); +/*##################################################################### */ + + /* + * Register : PCFGQOS1_2 @ 0XFD0705F8 + + * Specifies the timeout value for transactions mapped to the red address q + * ueue. + * PSU_DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR 0x0 + + * Specifies the timeout value for transactions mapped to the blue address + * queue. + * PSU_DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB 0x0 + + * Port n Read QoS Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD0705F8, 0x07FF07FFU ,0x00000000U) + */ + PSU_Mask_Write(DDRC_PCFGQOS1_2_OFFSET, 0x07FF07FFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : PCFGR_3 @ 0XFD070614 + + * If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. + * PSU_DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN 0x0 + + * If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + * bled and arurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + * urgent signal can be asserted anytime and as long as required which is i + * ndependent of address handshaking (it is not associated with any particu + * lar command). + * PSU_DDRC_PCFGR_3_RD_PORT_URGENT_EN 0x1 + + * If set to 1, enables aging function for the read channel of the port. + * PSU_DDRC_PCFGR_3_RD_PORT_AGING_EN 0x0 + + * Determines the initial load value of read aging counters. These counters + * will be parallel loaded after reset, or after each grant to the corresp + * onding port. The aging counters down-count every clock cycle where the p + * ort is requesting but not granted. The higher significant 5-bits of the + * read aging counter sets the priority of the read channel of a given port + * . Port's priority will increase as the higher significant 5-bits of the + * counter starts to decrease. When the aging counter becomes 0, the corres + * ponding port channel will have the highest priority level (timeout condi + * tion - Priority0). For multi-port configurations, the aging counters can + * not be used to set port priorities when external dynamic priority inputs + * (arqos) are enabled (timeout is still applicable). For single port conf + * igurations, the aging counters are only used when they timeout (become 0 + * ) to force read-write direction switching. In this case, external dynami + * c priority input, arqos (for reads only) can still be used to set the DD + * RC read priority (2 priority levels: low priority read - LPR, high prior + * ity read - HPR) on a command by command basis. Note: The two LSBs of thi + * s register field are tied internally to 2'b00. + * PSU_DDRC_PCFGR_3_RD_PORT_PRIORITY 0xf + + * Port n Configuration Read Register + * (OFFSET, MASK, VALUE) (0XFD070614, 0x000073FFU ,0x0000200FU) + */ + PSU_Mask_Write(DDRC_PCFGR_3_OFFSET, 0x000073FFU, 0x0000200FU); +/*##################################################################### */ + + /* + * Register : PCFGW_3 @ 0XFD070618 + + * If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. + * PSU_DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN 0x0 + + * If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + * bled and awurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + * serted anytime and as long as required which is independent of address h + * andshaking (it is not associated with any particular command). + * PSU_DDRC_PCFGW_3_WR_PORT_URGENT_EN 0x1 + + * If set to 1, enables aging function for the write channel of the port. + * PSU_DDRC_PCFGW_3_WR_PORT_AGING_EN 0x0 + + * Determines the initial load value of write aging counters. These counter + * s will be parallel loaded after reset, or after each grant to the corres + * ponding port. The aging counters down-count every clock cycle where the + * port is requesting but not granted. The higher significant 5-bits of the + * write aging counter sets the initial priority of the write channel of a + * given port. Port's priority will increase as the higher significant 5-b + * its of the counter starts to decrease. When the aging counter becomes 0, + * the corresponding port channel will have the highest priority level. Fo + * r multi-port configurations, the aging counters cannot be used to set po + * rt priorities when external dynamic priority inputs (awqos) are enabled + * (timeout is still applicable). For single port configurations, the aging + * counters are only used when they timeout (become 0) to force read-write + * direction switching. Note: The two LSBs of this register field are tied + * internally to 2'b00. + * PSU_DDRC_PCFGW_3_WR_PORT_PRIORITY 0xf + + * Port n Configuration Write Register + * (OFFSET, MASK, VALUE) (0XFD070618, 0x000073FFU ,0x0000200FU) + */ + PSU_Mask_Write(DDRC_PCFGW_3_OFFSET, 0x000073FFU, 0x0000200FU); +/*##################################################################### */ + + /* + * Register : PCTRL_3 @ 0XFD0706A0 + + * Enables port n. + * PSU_DDRC_PCTRL_3_PORT_EN 0x1 + + * Port n Control Register + * (OFFSET, MASK, VALUE) (0XFD0706A0, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(DDRC_PCTRL_3_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : PCFGQOS0_3 @ 0XFD0706A4 + + * This bitfield indicates the traffic class of region 1. Valid values are: + * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + * maps to the blue address queue. In this case, valid values are 0: LPR a + * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. + * PSU_DDRC_PCFGQOS0_3_RQOS_MAP_REGION1 0x1 + + * This bitfield indicates the traffic class of region 0. Valid values are: + * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + * maps to the blue address queue. In this case, valid values are: 0: LPR + * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. + * PSU_DDRC_PCFGQOS0_3_RQOS_MAP_REGION0 0x0 + + * Separation level1 indicating the end of region0 mapping; start of region + * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + * lues are used directly as port priorities, where the higher the value co + * rresponds to higher port priority. All of the map_level* registers must + * be set to distinct values. + * PSU_DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1 0x3 + + * Port n Read QoS Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD0706A4, 0x0033000FU ,0x00100003U) + */ + PSU_Mask_Write(DDRC_PCFGQOS0_3_OFFSET, 0x0033000FU, 0x00100003U); +/*##################################################################### */ + + /* + * Register : PCFGQOS1_3 @ 0XFD0706A8 + + * Specifies the timeout value for transactions mapped to the red address q + * ueue. + * PSU_DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR 0x0 + + * Specifies the timeout value for transactions mapped to the blue address + * queue. + * PSU_DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB 0x4f + + * Port n Read QoS Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD0706A8, 0x07FF07FFU ,0x0000004FU) + */ + PSU_Mask_Write(DDRC_PCFGQOS1_3_OFFSET, 0x07FF07FFU, 0x0000004FU); +/*##################################################################### */ + + /* + * Register : PCFGWQOS0_3 @ 0XFD0706AC + + * This bitfield indicates the traffic class of region 1. Valid values are: + * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + * affic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW + * traffic. + * PSU_DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1 0x1 + + * This bitfield indicates the traffic class of region 0. Valid values are: + * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + * affic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW + * traffic. + * PSU_DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0 0x0 + + * Separation level indicating the end of region0 mapping; start of region0 + * is 0. Possible values for level1 are 0 to 14 which corresponds to awqos + * . Note that for PA, awqos values are used directly as port priorities, w + * here the higher the value corresponds to higher port priority. + * PSU_DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL 0x3 + + * Port n Write QoS Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD0706AC, 0x0033000FU ,0x00100003U) + */ + PSU_Mask_Write(DDRC_PCFGWQOS0_3_OFFSET, 0x0033000FU, 0x00100003U); +/*##################################################################### */ + + /* + * Register : PCFGWQOS1_3 @ 0XFD0706B0 + + * Specifies the timeout value for write transactions. + * PSU_DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT 0x4f + + * Port n Write QoS Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD0706B0, 0x000007FFU ,0x0000004FU) + */ + PSU_Mask_Write(DDRC_PCFGWQOS1_3_OFFSET, 0x000007FFU, 0x0000004FU); +/*##################################################################### */ + + /* + * Register : PCFGR_4 @ 0XFD0706C4 + + * If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. + * PSU_DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN 0x0 + + * If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + * bled and arurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + * urgent signal can be asserted anytime and as long as required which is i + * ndependent of address handshaking (it is not associated with any particu + * lar command). + * PSU_DDRC_PCFGR_4_RD_PORT_URGENT_EN 0x1 + + * If set to 1, enables aging function for the read channel of the port. + * PSU_DDRC_PCFGR_4_RD_PORT_AGING_EN 0x0 + + * Determines the initial load value of read aging counters. These counters + * will be parallel loaded after reset, or after each grant to the corresp + * onding port. The aging counters down-count every clock cycle where the p + * ort is requesting but not granted. The higher significant 5-bits of the + * read aging counter sets the priority of the read channel of a given port + * . Port's priority will increase as the higher significant 5-bits of the + * counter starts to decrease. When the aging counter becomes 0, the corres + * ponding port channel will have the highest priority level (timeout condi + * tion - Priority0). For multi-port configurations, the aging counters can + * not be used to set port priorities when external dynamic priority inputs + * (arqos) are enabled (timeout is still applicable). For single port conf + * igurations, the aging counters are only used when they timeout (become 0 + * ) to force read-write direction switching. In this case, external dynami + * c priority input, arqos (for reads only) can still be used to set the DD + * RC read priority (2 priority levels: low priority read - LPR, high prior + * ity read - HPR) on a command by command basis. Note: The two LSBs of thi + * s register field are tied internally to 2'b00. + * PSU_DDRC_PCFGR_4_RD_PORT_PRIORITY 0xf + + * Port n Configuration Read Register + * (OFFSET, MASK, VALUE) (0XFD0706C4, 0x000073FFU ,0x0000200FU) + */ + PSU_Mask_Write(DDRC_PCFGR_4_OFFSET, 0x000073FFU, 0x0000200FU); +/*##################################################################### */ + + /* + * Register : PCFGW_4 @ 0XFD0706C8 + + * If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. + * PSU_DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN 0x0 + + * If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + * bled and awurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + * serted anytime and as long as required which is independent of address h + * andshaking (it is not associated with any particular command). + * PSU_DDRC_PCFGW_4_WR_PORT_URGENT_EN 0x1 + + * If set to 1, enables aging function for the write channel of the port. + * PSU_DDRC_PCFGW_4_WR_PORT_AGING_EN 0x0 + + * Determines the initial load value of write aging counters. These counter + * s will be parallel loaded after reset, or after each grant to the corres + * ponding port. The aging counters down-count every clock cycle where the + * port is requesting but not granted. The higher significant 5-bits of the + * write aging counter sets the initial priority of the write channel of a + * given port. Port's priority will increase as the higher significant 5-b + * its of the counter starts to decrease. When the aging counter becomes 0, + * the corresponding port channel will have the highest priority level. Fo + * r multi-port configurations, the aging counters cannot be used to set po + * rt priorities when external dynamic priority inputs (awqos) are enabled + * (timeout is still applicable). For single port configurations, the aging + * counters are only used when they timeout (become 0) to force read-write + * direction switching. Note: The two LSBs of this register field are tied + * internally to 2'b00. + * PSU_DDRC_PCFGW_4_WR_PORT_PRIORITY 0xf + + * Port n Configuration Write Register + * (OFFSET, MASK, VALUE) (0XFD0706C8, 0x000073FFU ,0x0000200FU) + */ + PSU_Mask_Write(DDRC_PCFGW_4_OFFSET, 0x000073FFU, 0x0000200FU); +/*##################################################################### */ + + /* + * Register : PCTRL_4 @ 0XFD070750 + + * Enables port n. + * PSU_DDRC_PCTRL_4_PORT_EN 0x1 + + * Port n Control Register + * (OFFSET, MASK, VALUE) (0XFD070750, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(DDRC_PCTRL_4_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : PCFGQOS0_4 @ 0XFD070754 + + * This bitfield indicates the traffic class of region 1. Valid values are: + * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + * maps to the blue address queue. In this case, valid values are 0: LPR a + * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. + * PSU_DDRC_PCFGQOS0_4_RQOS_MAP_REGION1 0x1 + + * This bitfield indicates the traffic class of region 0. Valid values are: + * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + * maps to the blue address queue. In this case, valid values are: 0: LPR + * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. + * PSU_DDRC_PCFGQOS0_4_RQOS_MAP_REGION0 0x0 + + * Separation level1 indicating the end of region0 mapping; start of region + * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + * lues are used directly as port priorities, where the higher the value co + * rresponds to higher port priority. All of the map_level* registers must + * be set to distinct values. + * PSU_DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1 0x3 + + * Port n Read QoS Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD070754, 0x0033000FU ,0x00100003U) + */ + PSU_Mask_Write(DDRC_PCFGQOS0_4_OFFSET, 0x0033000FU, 0x00100003U); +/*##################################################################### */ + + /* + * Register : PCFGQOS1_4 @ 0XFD070758 + + * Specifies the timeout value for transactions mapped to the red address q + * ueue. + * PSU_DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR 0x0 + + * Specifies the timeout value for transactions mapped to the blue address + * queue. + * PSU_DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB 0x4f + + * Port n Read QoS Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD070758, 0x07FF07FFU ,0x0000004FU) + */ + PSU_Mask_Write(DDRC_PCFGQOS1_4_OFFSET, 0x07FF07FFU, 0x0000004FU); +/*##################################################################### */ + + /* + * Register : PCFGWQOS0_4 @ 0XFD07075C + + * This bitfield indicates the traffic class of region 1. Valid values are: + * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + * affic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW + * traffic. + * PSU_DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1 0x1 + + * This bitfield indicates the traffic class of region 0. Valid values are: + * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + * affic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW + * traffic. + * PSU_DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0 0x0 + + * Separation level indicating the end of region0 mapping; start of region0 + * is 0. Possible values for level1 are 0 to 14 which corresponds to awqos + * . Note that for PA, awqos values are used directly as port priorities, w + * here the higher the value corresponds to higher port priority. + * PSU_DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL 0x3 + + * Port n Write QoS Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD07075C, 0x0033000FU ,0x00100003U) + */ + PSU_Mask_Write(DDRC_PCFGWQOS0_4_OFFSET, 0x0033000FU, 0x00100003U); +/*##################################################################### */ + + /* + * Register : PCFGWQOS1_4 @ 0XFD070760 + + * Specifies the timeout value for write transactions. + * PSU_DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT 0x4f + + * Port n Write QoS Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD070760, 0x000007FFU ,0x0000004FU) + */ + PSU_Mask_Write(DDRC_PCFGWQOS1_4_OFFSET, 0x000007FFU, 0x0000004FU); +/*##################################################################### */ + + /* + * Register : PCFGR_5 @ 0XFD070774 + + * If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. + * PSU_DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN 0x0 + + * If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + * bled and arurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + * urgent signal can be asserted anytime and as long as required which is i + * ndependent of address handshaking (it is not associated with any particu + * lar command). + * PSU_DDRC_PCFGR_5_RD_PORT_URGENT_EN 0x1 + + * If set to 1, enables aging function for the read channel of the port. + * PSU_DDRC_PCFGR_5_RD_PORT_AGING_EN 0x0 + + * Determines the initial load value of read aging counters. These counters + * will be parallel loaded after reset, or after each grant to the corresp + * onding port. The aging counters down-count every clock cycle where the p + * ort is requesting but not granted. The higher significant 5-bits of the + * read aging counter sets the priority of the read channel of a given port + * . Port's priority will increase as the higher significant 5-bits of the + * counter starts to decrease. When the aging counter becomes 0, the corres + * ponding port channel will have the highest priority level (timeout condi + * tion - Priority0). For multi-port configurations, the aging counters can + * not be used to set port priorities when external dynamic priority inputs + * (arqos) are enabled (timeout is still applicable). For single port conf + * igurations, the aging counters are only used when they timeout (become 0 + * ) to force read-write direction switching. In this case, external dynami + * c priority input, arqos (for reads only) can still be used to set the DD + * RC read priority (2 priority levels: low priority read - LPR, high prior + * ity read - HPR) on a command by command basis. Note: The two LSBs of thi + * s register field are tied internally to 2'b00. + * PSU_DDRC_PCFGR_5_RD_PORT_PRIORITY 0xf + + * Port n Configuration Read Register + * (OFFSET, MASK, VALUE) (0XFD070774, 0x000073FFU ,0x0000200FU) + */ + PSU_Mask_Write(DDRC_PCFGR_5_OFFSET, 0x000073FFU, 0x0000200FU); +/*##################################################################### */ + + /* + * Register : PCFGW_5 @ 0XFD070778 + + * If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. + * PSU_DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN 0x0 + + * If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + * bled and awurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + * serted anytime and as long as required which is independent of address h + * andshaking (it is not associated with any particular command). + * PSU_DDRC_PCFGW_5_WR_PORT_URGENT_EN 0x1 + + * If set to 1, enables aging function for the write channel of the port. + * PSU_DDRC_PCFGW_5_WR_PORT_AGING_EN 0x0 + + * Determines the initial load value of write aging counters. These counter + * s will be parallel loaded after reset, or after each grant to the corres + * ponding port. The aging counters down-count every clock cycle where the + * port is requesting but not granted. The higher significant 5-bits of the + * write aging counter sets the initial priority of the write channel of a + * given port. Port's priority will increase as the higher significant 5-b + * its of the counter starts to decrease. When the aging counter becomes 0, + * the corresponding port channel will have the highest priority level. Fo + * r multi-port configurations, the aging counters cannot be used to set po + * rt priorities when external dynamic priority inputs (awqos) are enabled + * (timeout is still applicable). For single port configurations, the aging + * counters are only used when they timeout (become 0) to force read-write + * direction switching. Note: The two LSBs of this register field are tied + * internally to 2'b00. + * PSU_DDRC_PCFGW_5_WR_PORT_PRIORITY 0xf + + * Port n Configuration Write Register + * (OFFSET, MASK, VALUE) (0XFD070778, 0x000073FFU ,0x0000200FU) + */ + PSU_Mask_Write(DDRC_PCFGW_5_OFFSET, 0x000073FFU, 0x0000200FU); +/*##################################################################### */ + + /* + * Register : PCTRL_5 @ 0XFD070800 + + * Enables port n. + * PSU_DDRC_PCTRL_5_PORT_EN 0x1 + + * Port n Control Register + * (OFFSET, MASK, VALUE) (0XFD070800, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(DDRC_PCTRL_5_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : PCFGQOS0_5 @ 0XFD070804 + + * This bitfield indicates the traffic class of region 1. Valid values are: + * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + * maps to the blue address queue. In this case, valid values are 0: LPR a + * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. + * PSU_DDRC_PCFGQOS0_5_RQOS_MAP_REGION1 0x1 + + * This bitfield indicates the traffic class of region 0. Valid values are: + * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + * maps to the blue address queue. In this case, valid values are: 0: LPR + * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. + * PSU_DDRC_PCFGQOS0_5_RQOS_MAP_REGION0 0x0 + + * Separation level1 indicating the end of region0 mapping; start of region + * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + * lues are used directly as port priorities, where the higher the value co + * rresponds to higher port priority. All of the map_level* registers must + * be set to distinct values. + * PSU_DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1 0x3 + + * Port n Read QoS Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD070804, 0x0033000FU ,0x00100003U) + */ + PSU_Mask_Write(DDRC_PCFGQOS0_5_OFFSET, 0x0033000FU, 0x00100003U); +/*##################################################################### */ + + /* + * Register : PCFGQOS1_5 @ 0XFD070808 + + * Specifies the timeout value for transactions mapped to the red address q + * ueue. + * PSU_DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR 0x0 + + * Specifies the timeout value for transactions mapped to the blue address + * queue. + * PSU_DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB 0x4f + + * Port n Read QoS Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD070808, 0x07FF07FFU ,0x0000004FU) + */ + PSU_Mask_Write(DDRC_PCFGQOS1_5_OFFSET, 0x07FF07FFU, 0x0000004FU); +/*##################################################################### */ + + /* + * Register : PCFGWQOS0_5 @ 0XFD07080C + + * This bitfield indicates the traffic class of region 1. Valid values are: + * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + * affic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW + * traffic. + * PSU_DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1 0x1 + + * This bitfield indicates the traffic class of region 0. Valid values are: + * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + * affic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW + * traffic. + * PSU_DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0 0x0 + + * Separation level indicating the end of region0 mapping; start of region0 + * is 0. Possible values for level1 are 0 to 14 which corresponds to awqos + * . Note that for PA, awqos values are used directly as port priorities, w + * here the higher the value corresponds to higher port priority. + * PSU_DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL 0x3 + + * Port n Write QoS Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD07080C, 0x0033000FU ,0x00100003U) + */ + PSU_Mask_Write(DDRC_PCFGWQOS0_5_OFFSET, 0x0033000FU, 0x00100003U); +/*##################################################################### */ + + /* + * Register : PCFGWQOS1_5 @ 0XFD070810 + + * Specifies the timeout value for write transactions. + * PSU_DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT 0x4f + + * Port n Write QoS Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD070810, 0x000007FFU ,0x0000004FU) + */ + PSU_Mask_Write(DDRC_PCFGWQOS1_5_OFFSET, 0x000007FFU, 0x0000004FU); +/*##################################################################### */ + + /* + * Register : SARBASE0 @ 0XFD070F04 + + * Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x + * ] and araddr[UMCTL2_A_ADDRW-1:x] where x is determined by the minimum bl + * ock size parameter UMCTL2_SARMINSIZE: (x=log2(block size)). + * PSU_DDRC_SARBASE0_BASE_ADDR 0x0 + + * SAR Base Address Register n + * (OFFSET, MASK, VALUE) (0XFD070F04, 0x000001FFU ,0x00000000U) + */ + PSU_Mask_Write(DDRC_SARBASE0_OFFSET, 0x000001FFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : SARSIZE0 @ 0XFD070F08 + + * Number of blocks for address region n. This register determines the tota + * l size of the region in multiples of minimum block size as specified by + * the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded + * as number of blocks = nblocks + 1. For example, if register is programme + * d to 0, region will have 1 block. + * PSU_DDRC_SARSIZE0_NBLOCKS 0x0 + + * SAR Size Register n + * (OFFSET, MASK, VALUE) (0XFD070F08, 0x000000FFU ,0x00000000U) + */ + PSU_Mask_Write(DDRC_SARSIZE0_OFFSET, 0x000000FFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : SARBASE1 @ 0XFD070F0C + + * Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x + * ] and araddr[UMCTL2_A_ADDRW-1:x] where x is determined by the minimum bl + * ock size parameter UMCTL2_SARMINSIZE: (x=log2(block size)). + * PSU_DDRC_SARBASE1_BASE_ADDR 0x10 + + * SAR Base Address Register n + * (OFFSET, MASK, VALUE) (0XFD070F0C, 0x000001FFU ,0x00000010U) + */ + PSU_Mask_Write(DDRC_SARBASE1_OFFSET, 0x000001FFU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : SARSIZE1 @ 0XFD070F10 + + * Number of blocks for address region n. This register determines the tota + * l size of the region in multiples of minimum block size as specified by + * the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded + * as number of blocks = nblocks + 1. For example, if register is programme + * d to 0, region will have 1 block. + * PSU_DDRC_SARSIZE1_NBLOCKS 0xf + + * SAR Size Register n + * (OFFSET, MASK, VALUE) (0XFD070F10, 0x000000FFU ,0x0000000FU) + */ + PSU_Mask_Write(DDRC_SARSIZE1_OFFSET, 0x000000FFU, 0x0000000FU); +/*##################################################################### */ + + /* + * Register : DFITMG0_SHADOW @ 0XFD072190 + + * Specifies the number of DFI clock cycles after an assertion or de-assert + * ion of the DFI control signals that the control signals at the PHY-DRAM + * interface reflect the assertion or de-assertion. If the DFI clock and th + * e memory clock are not phase-aligned, this timing parameter should be ro + * unded up to the next integer value. Note that if using RDIMM, it is nece + * ssary to increment this parameter by RDIMM's extra cycle of latency in t + * erms of DFI clock. + * PSU_DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY 0x7 + + * Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated u + * sing HDR or SDR values Selects whether value in DFITMG0.dfi_t_rddata_en + * is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles + * - 1 in terms of SDR clock cycles Refer to PHY specification for correct + * value. + * PSU_DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR 0x1 + + * Time from the assertion of a read command on the DFI interface to the as + * sertion of the dfi_rddata_en signal. Refer to PHY specification for corr + * ect value. This corresponds to the DFI parameter trddata_en. Note that, + * depending on the PHY, if using RDIMM, it may be necessary to use the val + * ue (CL + 1) in the calculation of trddata_en. This is to compensate for + * the extra cycle of latency through the RDIMM. Unit: Clocks + * PSU_DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN 0x2 + + * Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated us + * ing HDR or SDR values Selects whether value in DFITMG0.dfi_tphy_wrlat is + * in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.df + * i_tphy_wrdata is in terms of SDR or HDR clock cycles - 0 in terms of HDR + * clock cycles - 1 in terms of SDR clock cycles Refer to PHY specificatio + * n for correct value. + * PSU_DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR 0x1 + + * Specifies the number of clock cycles between when dfi_wrdata_en is asser + * ted to when the associated write data is driven on the dfi_wrdata signal + * . This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY + * specification for correct value. Note, max supported value is 8. Unit: + * Clocks + * PSU_DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA 0x0 + + * Write latency Number of clocks from the write command to write data enab + * le (dfi_wrdata_en). This corresponds to the DFI timing parameter tphy_wr + * lat. Refer to PHY specification for correct value.Note that, depending o + * n the PHY, if using RDIMM, it may be necessary to use the value (CL + 1) + * in the calculation of tphy_wrlat. This is to compensate for the extra c + * ycle of latency through the RDIMM. + * PSU_DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT 0x2 + + * DFI Timing Shadow Register 0 + * (OFFSET, MASK, VALUE) (0XFD072190, 0x1FBFBF3FU ,0x07828002U) + */ + PSU_Mask_Write(DDRC_DFITMG0_SHADOW_OFFSET, 0x1FBFBF3FU, 0x07828002U); +/*##################################################################### */ + + /* + * DDR CONTROLLER RESET + */ + /* + * Register : RST_DDR_SS @ 0XFD1A0108 + + * DDR block level reset inside of the DDR Sub System + * PSU_CRF_APB_RST_DDR_SS_DDR_RESET 0X0 + + * APM block level reset inside of the DDR Sub System + * PSU_CRF_APB_RST_DDR_SS_APM_RESET 0X0 + + * DDR sub system block level reset + * (OFFSET, MASK, VALUE) (0XFD1A0108, 0x0000000CU ,0x00000000U) + */ + PSU_Mask_Write(CRF_APB_RST_DDR_SS_OFFSET, 0x0000000CU, 0x00000000U); +/*##################################################################### */ + + /* + * DDR PHY + */ + /* + * Register : PGCR0 @ 0XFD080010 + + * Address Copy + * PSU_DDR_PHY_PGCR0_ADCP 0x0 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_PGCR0_RESERVED_30_27 0x0 + + * PHY FIFO Reset + * PSU_DDR_PHY_PGCR0_PHYFRST 0x1 + + * Oscillator Mode Address/Command Delay Line Select + * PSU_DDR_PHY_PGCR0_OSCACDL 0x3 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_PGCR0_RESERVED_23_19 0x0 + + * Digital Test Output Select + * PSU_DDR_PHY_PGCR0_DTOSEL 0x0 - RegVal = ((0x0000000FU << DDRC_SARSIZE1_NBLOCKS_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_SARSIZE1_OFFSET ,0x000000FFU ,0x0000000FU); - /*############################################################################################################################ */ + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_PGCR0_RESERVED_13 0x0 - /*Register : DFITMG0_SHADOW @ 0XFD072190

+ * Oscillator Mode Division + * PSU_DDR_PHY_PGCR0_OSCDIV 0xf - Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signa - s at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligne - , this timing parameter should be rounded up to the next integer value. Note that if using RDIMM, it is necessary to incremen - this parameter by RDIMM's extra cycle of latency in terms of DFI clock. - PSU_DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY 0x7 - - Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR or SDR values Selects whether value in DFITM - 0.dfi_t_rddata_en is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles R - fer to PHY specification for correct value. - PSU_DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR 0x1 - - Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. Refer to PHY spe - ification for correct value. This corresponds to the DFI parameter trddata_en. Note that, depending on the PHY, if using RDIM - , it may be necessary to use the value (CL + 1) in the calculation of trddata_en. This is to compensate for the extra cycle o - latency through the RDIMM. Unit: Clocks - PSU_DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN 0x2 - - Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using HDR or SDR values Selects whether value in DFITMG - .dfi_tphy_wrlat is in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.dfi_tphy_wrdata is in terms of SDR or - HDR clock cycles - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles Refer to PHY specification for correct val - e. - PSU_DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR 0x1 - - Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on th - dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. N - te, max supported value is 8. Unit: Clocks - PSU_DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA 0x0 - - Write latency Number of clocks from the write command to write data enable (dfi_wrdata_en). This corresponds to the DFI timin - parameter tphy_wrlat. Refer to PHY specification for correct value.Note that, depending on the PHY, if using RDIMM, it may b - necessary to use the value (CL + 1) in the calculation of tphy_wrlat. This is to compensate for the extra cycle of latency t - rough the RDIMM. - PSU_DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT 0x2 + * Oscillator Enable + * PSU_DDR_PHY_PGCR0_OSCEN 0x0 - DFI Timing Shadow Register 0 - (OFFSET, MASK, VALUE) (0XFD072190, 0x1FBFBF3FU ,0x07828002U) - RegMask = (DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_MASK | DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_MASK | DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_MASK | DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_MASK | DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_MASK | DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_MASK | 0 ); + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_PGCR0_RESERVED_7_0 0x0 - RegVal = ((0x00000007U << DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_SHIFT - | 0x00000001U << DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_SHIFT - | 0x00000002U << DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_SHIFT - | 0x00000001U << DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_SHIFT - | 0x00000000U << DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_SHIFT - | 0x00000002U << DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DFITMG0_SHADOW_OFFSET ,0x1FBFBF3FU ,0x07828002U); - /*############################################################################################################################ */ - - // : DDR CONTROLLER RESET - /*Register : RST_DDR_SS @ 0XFD1A0108

- - DDR block level reset inside of the DDR Sub System - PSU_CRF_APB_RST_DDR_SS_DDR_RESET 0X0 - - DDR sub system block level reset - (OFFSET, MASK, VALUE) (0XFD1A0108, 0x00000008U ,0x00000000U) - RegMask = (CRF_APB_RST_DDR_SS_DDR_RESET_MASK | 0 ); - - RegVal = ((0x00000000U << CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_RST_DDR_SS_OFFSET ,0x00000008U ,0x00000000U); - /*############################################################################################################################ */ - - // : DDR PHY - /*Register : PGCR0 @ 0XFD080010

- - Address Copy - PSU_DDR_PHY_PGCR0_ADCP 0x0 - - Reserved. Returns zeroes on reads. - PSU_DDR_PHY_PGCR0_RESERVED_30_27 0x0 - - PHY FIFO Reset - PSU_DDR_PHY_PGCR0_PHYFRST 0x1 - - Oscillator Mode Address/Command Delay Line Select - PSU_DDR_PHY_PGCR0_OSCACDL 0x3 - - Reserved. Returns zeroes on reads. - PSU_DDR_PHY_PGCR0_RESERVED_23_19 0x0 + * PHY General Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD080010, 0xFFFFFFFFU ,0x07001E00U) + */ + PSU_Mask_Write(DDR_PHY_PGCR0_OFFSET, 0xFFFFFFFFU, 0x07001E00U); +/*##################################################################### */ - Digital Test Output Select - PSU_DDR_PHY_PGCR0_DTOSEL 0x0 + /* + * Register : PGCR2 @ 0XFD080018 - Reserved. Returns zeroes on reads. - PSU_DDR_PHY_PGCR0_RESERVED_13 0x0 + * Clear Training Status Registers + * PSU_DDR_PHY_PGCR2_CLRTSTAT 0x0 - Oscillator Mode Division - PSU_DDR_PHY_PGCR0_OSCDIV 0xf + * Clear Impedance Calibration + * PSU_DDR_PHY_PGCR2_CLRZCAL 0x0 - Oscillator Enable - PSU_DDR_PHY_PGCR0_OSCEN 0x0 + * Clear Parity Error + * PSU_DDR_PHY_PGCR2_CLRPERR 0x0 - Reserved. Returns zeroes on reads. - PSU_DDR_PHY_PGCR0_RESERVED_7_0 0x0 + * Initialization Complete Pin Configuration + * PSU_DDR_PHY_PGCR2_ICPC 0x0 - PHY General Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD080010, 0xFFFFFFFFU ,0x07001E00U) - RegMask = (DDR_PHY_PGCR0_ADCP_MASK | DDR_PHY_PGCR0_RESERVED_30_27_MASK | DDR_PHY_PGCR0_PHYFRST_MASK | DDR_PHY_PGCR0_OSCACDL_MASK | DDR_PHY_PGCR0_RESERVED_23_19_MASK | DDR_PHY_PGCR0_DTOSEL_MASK | DDR_PHY_PGCR0_RESERVED_13_MASK | DDR_PHY_PGCR0_OSCDIV_MASK | DDR_PHY_PGCR0_OSCEN_MASK | DDR_PHY_PGCR0_RESERVED_7_0_MASK | 0 ); + * Data Training PUB Mode Exit Timer + * PSU_DDR_PHY_PGCR2_DTPMXTMR 0xf - RegVal = ((0x00000000U << DDR_PHY_PGCR0_ADCP_SHIFT - | 0x00000000U << DDR_PHY_PGCR0_RESERVED_30_27_SHIFT - | 0x00000001U << DDR_PHY_PGCR0_PHYFRST_SHIFT - | 0x00000003U << DDR_PHY_PGCR0_OSCACDL_SHIFT - | 0x00000000U << DDR_PHY_PGCR0_RESERVED_23_19_SHIFT - | 0x00000000U << DDR_PHY_PGCR0_DTOSEL_SHIFT - | 0x00000000U << DDR_PHY_PGCR0_RESERVED_13_SHIFT - | 0x0000000FU << DDR_PHY_PGCR0_OSCDIV_SHIFT - | 0x00000000U << DDR_PHY_PGCR0_OSCEN_SHIFT - | 0x00000000U << DDR_PHY_PGCR0_RESERVED_7_0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_PGCR0_OFFSET ,0xFFFFFFFFU ,0x07001E00U); - /*############################################################################################################################ */ - - /*Register : PGCR2 @ 0XFD080018

+ * Initialization Bypass + * PSU_DDR_PHY_PGCR2_INITFSMBYP 0x0 - Clear Training Status Registers - PSU_DDR_PHY_PGCR2_CLRTSTAT 0x0 + * PLL FSM Bypass + * PSU_DDR_PHY_PGCR2_PLLFSMBYP 0x0 - Clear Impedance Calibration - PSU_DDR_PHY_PGCR2_CLRZCAL 0x0 + * Refresh Period + * PSU_DDR_PHY_PGCR2_TREFPRD 0x10010 - Clear Parity Error - PSU_DDR_PHY_PGCR2_CLRPERR 0x0 + * PHY General Configuration Register 2 + * (OFFSET, MASK, VALUE) (0XFD080018, 0xFFFFFFFFU ,0x00F10010U) + */ + PSU_Mask_Write(DDR_PHY_PGCR2_OFFSET, 0xFFFFFFFFU, 0x00F10010U); +/*##################################################################### */ - Initialization Complete Pin Configuration - PSU_DDR_PHY_PGCR2_ICPC 0x0 + /* + * Register : PGCR3 @ 0XFD08001C - Data Training PUB Mode Exit Timer - PSU_DDR_PHY_PGCR2_DTPMXTMR 0xf + * CKN Enable + * PSU_DDR_PHY_PGCR3_CKNEN 0x55 - Initialization Bypass - PSU_DDR_PHY_PGCR2_INITFSMBYP 0x0 + * CK Enable + * PSU_DDR_PHY_PGCR3_CKEN 0xaa - PLL FSM Bypass - PSU_DDR_PHY_PGCR2_PLLFSMBYP 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_PGCR3_RESERVED_15 0x0 - Refresh Period - PSU_DDR_PHY_PGCR2_TREFPRD 0x10028 + * Enable Clock Gating for AC [0] ctl_rd_clk + * PSU_DDR_PHY_PGCR3_GATEACRDCLK 0x2 - PHY General Configuration Register 2 - (OFFSET, MASK, VALUE) (0XFD080018, 0xFFFFFFFFU ,0x00F10028U) - RegMask = (DDR_PHY_PGCR2_CLRTSTAT_MASK | DDR_PHY_PGCR2_CLRZCAL_MASK | DDR_PHY_PGCR2_CLRPERR_MASK | DDR_PHY_PGCR2_ICPC_MASK | DDR_PHY_PGCR2_DTPMXTMR_MASK | DDR_PHY_PGCR2_INITFSMBYP_MASK | DDR_PHY_PGCR2_PLLFSMBYP_MASK | DDR_PHY_PGCR2_TREFPRD_MASK | 0 ); + * Enable Clock Gating for AC [0] ddr_clk + * PSU_DDR_PHY_PGCR3_GATEACDDRCLK 0x2 - RegVal = ((0x00000000U << DDR_PHY_PGCR2_CLRTSTAT_SHIFT - | 0x00000000U << DDR_PHY_PGCR2_CLRZCAL_SHIFT - | 0x00000000U << DDR_PHY_PGCR2_CLRPERR_SHIFT - | 0x00000000U << DDR_PHY_PGCR2_ICPC_SHIFT - | 0x0000000FU << DDR_PHY_PGCR2_DTPMXTMR_SHIFT - | 0x00000000U << DDR_PHY_PGCR2_INITFSMBYP_SHIFT - | 0x00000000U << DDR_PHY_PGCR2_PLLFSMBYP_SHIFT - | 0x00010028U << DDR_PHY_PGCR2_TREFPRD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_PGCR2_OFFSET ,0xFFFFFFFFU ,0x00F10028U); - /*############################################################################################################################ */ + * Enable Clock Gating for AC [0] ctl_clk + * PSU_DDR_PHY_PGCR3_GATEACCTLCLK 0x2 - /*Register : PGCR3 @ 0XFD08001C

+ * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_PGCR3_RESERVED_8 0x0 - CKN Enable - PSU_DDR_PHY_PGCR3_CKNEN 0x55 + * Controls DDL Bypass Modes + * PSU_DDR_PHY_PGCR3_DDLBYPMODE 0x2 - CK Enable - PSU_DDR_PHY_PGCR3_CKEN 0xaa + * IO Loop-Back Select + * PSU_DDR_PHY_PGCR3_IOLB 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_PGCR3_RESERVED_15 0x0 + * AC Receive FIFO Read Mode + * PSU_DDR_PHY_PGCR3_RDMODE 0x0 - Enable Clock Gating for AC [0] ctl_rd_clk - PSU_DDR_PHY_PGCR3_GATEACRDCLK 0x2 + * Read FIFO Reset Disable + * PSU_DDR_PHY_PGCR3_DISRST 0x0 - Enable Clock Gating for AC [0] ddr_clk - PSU_DDR_PHY_PGCR3_GATEACDDRCLK 0x2 + * Clock Level when Clock Gating + * PSU_DDR_PHY_PGCR3_CLKLEVEL 0x0 - Enable Clock Gating for AC [0] ctl_clk - PSU_DDR_PHY_PGCR3_GATEACCTLCLK 0x2 + * PHY General Configuration Register 3 + * (OFFSET, MASK, VALUE) (0XFD08001C, 0xFFFFFFFFU ,0x55AA5480U) + */ + PSU_Mask_Write(DDR_PHY_PGCR3_OFFSET, 0xFFFFFFFFU, 0x55AA5480U); +/*##################################################################### */ - Reserved. Return zeroes on reads. - PSU_DDR_PHY_PGCR3_RESERVED_8 0x0 + /* + * Register : PGCR5 @ 0XFD080024 - Controls DDL Bypass Modes - PSU_DDR_PHY_PGCR3_DDLBYPMODE 0x2 + * Frequency B Ratio Term + * PSU_DDR_PHY_PGCR5_FRQBT 0x1 - IO Loop-Back Select - PSU_DDR_PHY_PGCR3_IOLB 0x0 + * Frequency A Ratio Term + * PSU_DDR_PHY_PGCR5_FRQAT 0x1 - AC Receive FIFO Read Mode - PSU_DDR_PHY_PGCR3_RDMODE 0x0 + * DFI Disconnect Time Period + * PSU_DDR_PHY_PGCR5_DISCNPERIOD 0x0 - Read FIFO Reset Disable - PSU_DDR_PHY_PGCR3_DISRST 0x0 + * Receiver bias core side control + * PSU_DDR_PHY_PGCR5_VREF_RBCTRL 0xf - Clock Level when Clock Gating - PSU_DDR_PHY_PGCR3_CLKLEVEL 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_PGCR5_RESERVED_3 0x0 - PHY General Configuration Register 3 - (OFFSET, MASK, VALUE) (0XFD08001C, 0xFFFFFFFFU ,0x55AA5480U) - RegMask = (DDR_PHY_PGCR3_CKNEN_MASK | DDR_PHY_PGCR3_CKEN_MASK | DDR_PHY_PGCR3_RESERVED_15_MASK | DDR_PHY_PGCR3_GATEACRDCLK_MASK | DDR_PHY_PGCR3_GATEACDDRCLK_MASK | DDR_PHY_PGCR3_GATEACCTLCLK_MASK | DDR_PHY_PGCR3_RESERVED_8_MASK | DDR_PHY_PGCR3_DDLBYPMODE_MASK | DDR_PHY_PGCR3_IOLB_MASK | DDR_PHY_PGCR3_RDMODE_MASK | DDR_PHY_PGCR3_DISRST_MASK | DDR_PHY_PGCR3_CLKLEVEL_MASK | 0 ); + * Internal VREF generator REFSEL ragne select + * PSU_DDR_PHY_PGCR5_DXREFISELRANGE 0x1 - RegVal = ((0x00000055U << DDR_PHY_PGCR3_CKNEN_SHIFT - | 0x000000AAU << DDR_PHY_PGCR3_CKEN_SHIFT - | 0x00000000U << DDR_PHY_PGCR3_RESERVED_15_SHIFT - | 0x00000002U << DDR_PHY_PGCR3_GATEACRDCLK_SHIFT - | 0x00000002U << DDR_PHY_PGCR3_GATEACDDRCLK_SHIFT - | 0x00000002U << DDR_PHY_PGCR3_GATEACCTLCLK_SHIFT - | 0x00000000U << DDR_PHY_PGCR3_RESERVED_8_SHIFT - | 0x00000002U << DDR_PHY_PGCR3_DDLBYPMODE_SHIFT - | 0x00000000U << DDR_PHY_PGCR3_IOLB_SHIFT - | 0x00000000U << DDR_PHY_PGCR3_RDMODE_SHIFT - | 0x00000000U << DDR_PHY_PGCR3_DISRST_SHIFT - | 0x00000000U << DDR_PHY_PGCR3_CLKLEVEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_PGCR3_OFFSET ,0xFFFFFFFFU ,0x55AA5480U); - /*############################################################################################################################ */ + * DDL Page Read Write select + * PSU_DDR_PHY_PGCR5_DDLPGACT 0x0 - /*Register : PGCR5 @ 0XFD080024

+ * DDL Page Read Write select + * PSU_DDR_PHY_PGCR5_DDLPGRW 0x0 - Frequency B Ratio Term - PSU_DDR_PHY_PGCR5_FRQBT 0x1 + * PHY General Configuration Register 5 + * (OFFSET, MASK, VALUE) (0XFD080024, 0xFFFFFFFFU ,0x010100F4U) + */ + PSU_Mask_Write(DDR_PHY_PGCR5_OFFSET, 0xFFFFFFFFU, 0x010100F4U); +/*##################################################################### */ - Frequency A Ratio Term - PSU_DDR_PHY_PGCR5_FRQAT 0x1 + /* + * Register : PTR0 @ 0XFD080040 - DFI Disconnect Time Period - PSU_DDR_PHY_PGCR5_DISCNPERIOD 0x0 + * PLL Power-Down Time + * PSU_DDR_PHY_PTR0_TPLLPD 0x56 - Receiver bias core side control - PSU_DDR_PHY_PGCR5_VREF_RBCTRL 0xf + * PLL Gear Shift Time + * PSU_DDR_PHY_PTR0_TPLLGS 0x2155 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_PGCR5_RESERVED_3 0x0 + * PHY Reset Time + * PSU_DDR_PHY_PTR0_TPHYRST 0x10 - Internal VREF generator REFSEL ragne select - PSU_DDR_PHY_PGCR5_DXREFISELRANGE 0x1 + * PHY Timing Register 0 + * (OFFSET, MASK, VALUE) (0XFD080040, 0xFFFFFFFFU ,0x0AC85550U) + */ + PSU_Mask_Write(DDR_PHY_PTR0_OFFSET, 0xFFFFFFFFU, 0x0AC85550U); +/*##################################################################### */ - DDL Page Read Write select - PSU_DDR_PHY_PGCR5_DDLPGACT 0x0 + /* + * Register : PTR1 @ 0XFD080044 - DDL Page Read Write select - PSU_DDR_PHY_PGCR5_DDLPGRW 0x0 + * PLL Lock Time + * PSU_DDR_PHY_PTR1_TPLLLOCK 0x4141 - PHY General Configuration Register 5 - (OFFSET, MASK, VALUE) (0XFD080024, 0xFFFFFFFFU ,0x010100F4U) - RegMask = (DDR_PHY_PGCR5_FRQBT_MASK | DDR_PHY_PGCR5_FRQAT_MASK | DDR_PHY_PGCR5_DISCNPERIOD_MASK | DDR_PHY_PGCR5_VREF_RBCTRL_MASK | DDR_PHY_PGCR5_RESERVED_3_MASK | DDR_PHY_PGCR5_DXREFISELRANGE_MASK | DDR_PHY_PGCR5_DDLPGACT_MASK | DDR_PHY_PGCR5_DDLPGRW_MASK | 0 ); + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_PTR1_RESERVED_15_13 0x0 - RegVal = ((0x00000001U << DDR_PHY_PGCR5_FRQBT_SHIFT - | 0x00000001U << DDR_PHY_PGCR5_FRQAT_SHIFT - | 0x00000000U << DDR_PHY_PGCR5_DISCNPERIOD_SHIFT - | 0x0000000FU << DDR_PHY_PGCR5_VREF_RBCTRL_SHIFT - | 0x00000000U << DDR_PHY_PGCR5_RESERVED_3_SHIFT - | 0x00000001U << DDR_PHY_PGCR5_DXREFISELRANGE_SHIFT - | 0x00000000U << DDR_PHY_PGCR5_DDLPGACT_SHIFT - | 0x00000000U << DDR_PHY_PGCR5_DDLPGRW_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_PGCR5_OFFSET ,0xFFFFFFFFU ,0x010100F4U); - /*############################################################################################################################ */ + * PLL Reset Time + * PSU_DDR_PHY_PTR1_TPLLRST 0xaff - /*Register : PTR0 @ 0XFD080040

+ * PHY Timing Register 1 + * (OFFSET, MASK, VALUE) (0XFD080044, 0xFFFFFFFFU ,0x41410AFFU) + */ + PSU_Mask_Write(DDR_PHY_PTR1_OFFSET, 0xFFFFFFFFU, 0x41410AFFU); +/*##################################################################### */ - PLL Power-Down Time - PSU_DDR_PHY_PTR0_TPLLPD 0x2f0 + /* + * Register : PLLCR0 @ 0XFD080068 - PLL Gear Shift Time - PSU_DDR_PHY_PTR0_TPLLGS 0x60 + * PLL Bypass + * PSU_DDR_PHY_PLLCR0_PLLBYP 0x0 - PHY Reset Time - PSU_DDR_PHY_PTR0_TPHYRST 0x10 + * PLL Reset + * PSU_DDR_PHY_PLLCR0_PLLRST 0x0 - PHY Timing Register 0 - (OFFSET, MASK, VALUE) (0XFD080040, 0xFFFFFFFFU ,0x5E001810U) - RegMask = (DDR_PHY_PTR0_TPLLPD_MASK | DDR_PHY_PTR0_TPLLGS_MASK | DDR_PHY_PTR0_TPHYRST_MASK | 0 ); + * PLL Power Down + * PSU_DDR_PHY_PLLCR0_PLLPD 0x0 - RegVal = ((0x000002F0U << DDR_PHY_PTR0_TPLLPD_SHIFT - | 0x00000060U << DDR_PHY_PTR0_TPLLGS_SHIFT - | 0x00000010U << DDR_PHY_PTR0_TPHYRST_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_PTR0_OFFSET ,0xFFFFFFFFU ,0x5E001810U); - /*############################################################################################################################ */ + * Reference Stop Mode + * PSU_DDR_PHY_PLLCR0_RSTOPM 0x0 - /*Register : PTR1 @ 0XFD080044

+ * PLL Frequency Select + * PSU_DDR_PHY_PLLCR0_FRQSEL 0x1 - PLL Lock Time - PSU_DDR_PHY_PTR1_TPLLLOCK 0x80 + * Relock Mode + * PSU_DDR_PHY_PLLCR0_RLOCKM 0x0 - Reserved. Returns zeroes on reads. - PSU_DDR_PHY_PTR1_RESERVED_15_13 0x0 + * Charge Pump Proportional Current Control + * PSU_DDR_PHY_PLLCR0_CPPC 0x8 - PLL Reset Time - PSU_DDR_PHY_PTR1_TPLLRST 0x5f0 - - PHY Timing Register 1 - (OFFSET, MASK, VALUE) (0XFD080044, 0xFFFFFFFFU ,0x008005F0U) - RegMask = (DDR_PHY_PTR1_TPLLLOCK_MASK | DDR_PHY_PTR1_RESERVED_15_13_MASK | DDR_PHY_PTR1_TPLLRST_MASK | 0 ); + * Charge Pump Integrating Current Control + * PSU_DDR_PHY_PLLCR0_CPIC 0x0 - RegVal = ((0x00000080U << DDR_PHY_PTR1_TPLLLOCK_SHIFT - | 0x00000000U << DDR_PHY_PTR1_RESERVED_15_13_SHIFT - | 0x000005F0U << DDR_PHY_PTR1_TPLLRST_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_PTR1_OFFSET ,0xFFFFFFFFU ,0x008005F0U); - /*############################################################################################################################ */ + * Gear Shift + * PSU_DDR_PHY_PLLCR0_GSHIFT 0x0 - /*Register : DSGCR @ 0XFD080090

+ * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_PLLCR0_RESERVED_11_9 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DSGCR_RESERVED_31_28 0x0 + * Analog Test Enable + * PSU_DDR_PHY_PLLCR0_ATOEN 0x0 - When RDBI enabled, this bit is used to select RDBI CL calculation, if it is 1b1, calculation will use RDBICL, otherwise use d - fault calculation. - PSU_DDR_PHY_DSGCR_RDBICLSEL 0x0 + * Analog Test Control + * PSU_DDR_PHY_PLLCR0_ATC 0x0 - When RDBI enabled, if RDBICLSEL is asserted, RDBI CL adjust using this value. - PSU_DDR_PHY_DSGCR_RDBICL 0x2 + * Digital Test Control + * PSU_DDR_PHY_PLLCR0_DTC 0x0 - PHY Impedance Update Enable - PSU_DDR_PHY_DSGCR_PHYZUEN 0x1 + * PLL Control Register 0 (Type B PLL Only) + * (OFFSET, MASK, VALUE) (0XFD080068, 0xFFFFFFFFU ,0x01100000U) + */ + PSU_Mask_Write(DDR_PHY_PLLCR0_OFFSET, 0xFFFFFFFFU, 0x01100000U); +/*##################################################################### */ - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DSGCR_RESERVED_22 0x0 + /* + * Register : DSGCR @ 0XFD080090 - SDRAM Reset Output Enable - PSU_DDR_PHY_DSGCR_RSTOE 0x1 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DSGCR_RESERVED_31_28 0x0 - Single Data Rate Mode - PSU_DDR_PHY_DSGCR_SDRMODE 0x0 + * When RDBI enabled, this bit is used to select RDBI CL calculation, if it + * is 1b1, calculation will use RDBICL, otherwise use default calculation. + * PSU_DDR_PHY_DSGCR_RDBICLSEL 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DSGCR_RESERVED_18 0x0 + * When RDBI enabled, if RDBICLSEL is asserted, RDBI CL adjust using this v + * alue. + * PSU_DDR_PHY_DSGCR_RDBICL 0x2 - ATO Analog Test Enable - PSU_DDR_PHY_DSGCR_ATOAE 0x0 + * PHY Impedance Update Enable + * PSU_DDR_PHY_DSGCR_PHYZUEN 0x1 - DTO Output Enable - PSU_DDR_PHY_DSGCR_DTOOE 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DSGCR_RESERVED_22 0x0 - DTO I/O Mode - PSU_DDR_PHY_DSGCR_DTOIOM 0x0 + * SDRAM Reset Output Enable + * PSU_DDR_PHY_DSGCR_RSTOE 0x1 - DTO Power Down Receiver - PSU_DDR_PHY_DSGCR_DTOPDR 0x1 + * Single Data Rate Mode + * PSU_DDR_PHY_DSGCR_SDRMODE 0x0 - Reserved. Return zeroes on reads - PSU_DDR_PHY_DSGCR_RESERVED_13 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DSGCR_RESERVED_18 0x0 - DTO On-Die Termination - PSU_DDR_PHY_DSGCR_DTOODT 0x0 + * ATO Analog Test Enable + * PSU_DDR_PHY_DSGCR_ATOAE 0x0 - PHY Update Acknowledge Delay - PSU_DDR_PHY_DSGCR_PUAD 0x4 + * DTO Output Enable + * PSU_DDR_PHY_DSGCR_DTOOE 0x0 - Controller Update Acknowledge Enable - PSU_DDR_PHY_DSGCR_CUAEN 0x1 + * DTO I/O Mode + * PSU_DDR_PHY_DSGCR_DTOIOM 0x0 - Reserved. Return zeroes on reads - PSU_DDR_PHY_DSGCR_RESERVED_4_3 0x0 + * DTO Power Down Receiver + * PSU_DDR_PHY_DSGCR_DTOPDR 0x1 - Controller Impedance Update Enable - PSU_DDR_PHY_DSGCR_CTLZUEN 0x0 + * Reserved. Return zeroes on reads + * PSU_DDR_PHY_DSGCR_RESERVED_13 0x0 - Reserved. Return zeroes on reads - PSU_DDR_PHY_DSGCR_RESERVED_1 0x0 + * DTO On-Die Termination + * PSU_DDR_PHY_DSGCR_DTOODT 0x0 - PHY Update Request Enable - PSU_DDR_PHY_DSGCR_PUREN 0x1 + * PHY Update Acknowledge Delay + * PSU_DDR_PHY_DSGCR_PUAD 0x5 - DDR System General Configuration Register - (OFFSET, MASK, VALUE) (0XFD080090, 0xFFFFFFFFU ,0x02A04121U) - RegMask = (DDR_PHY_DSGCR_RESERVED_31_28_MASK | DDR_PHY_DSGCR_RDBICLSEL_MASK | DDR_PHY_DSGCR_RDBICL_MASK | DDR_PHY_DSGCR_PHYZUEN_MASK | DDR_PHY_DSGCR_RESERVED_22_MASK | DDR_PHY_DSGCR_RSTOE_MASK | DDR_PHY_DSGCR_SDRMODE_MASK | DDR_PHY_DSGCR_RESERVED_18_MASK | DDR_PHY_DSGCR_ATOAE_MASK | DDR_PHY_DSGCR_DTOOE_MASK | DDR_PHY_DSGCR_DTOIOM_MASK | DDR_PHY_DSGCR_DTOPDR_MASK | DDR_PHY_DSGCR_RESERVED_13_MASK | DDR_PHY_DSGCR_DTOODT_MASK | DDR_PHY_DSGCR_PUAD_MASK | DDR_PHY_DSGCR_CUAEN_MASK | DDR_PHY_DSGCR_RESERVED_4_3_MASK | DDR_PHY_DSGCR_CTLZUEN_MASK | DDR_PHY_DSGCR_RESERVED_1_MASK | DDR_PHY_DSGCR_PUREN_MASK | 0 ); + * Controller Update Acknowledge Enable + * PSU_DDR_PHY_DSGCR_CUAEN 0x1 - RegVal = ((0x00000000U << DDR_PHY_DSGCR_RESERVED_31_28_SHIFT - | 0x00000000U << DDR_PHY_DSGCR_RDBICLSEL_SHIFT - | 0x00000002U << DDR_PHY_DSGCR_RDBICL_SHIFT - | 0x00000001U << DDR_PHY_DSGCR_PHYZUEN_SHIFT - | 0x00000000U << DDR_PHY_DSGCR_RESERVED_22_SHIFT - | 0x00000001U << DDR_PHY_DSGCR_RSTOE_SHIFT - | 0x00000000U << DDR_PHY_DSGCR_SDRMODE_SHIFT - | 0x00000000U << DDR_PHY_DSGCR_RESERVED_18_SHIFT - | 0x00000000U << DDR_PHY_DSGCR_ATOAE_SHIFT - | 0x00000000U << DDR_PHY_DSGCR_DTOOE_SHIFT - | 0x00000000U << DDR_PHY_DSGCR_DTOIOM_SHIFT - | 0x00000001U << DDR_PHY_DSGCR_DTOPDR_SHIFT - | 0x00000000U << DDR_PHY_DSGCR_RESERVED_13_SHIFT - | 0x00000000U << DDR_PHY_DSGCR_DTOODT_SHIFT - | 0x00000004U << DDR_PHY_DSGCR_PUAD_SHIFT - | 0x00000001U << DDR_PHY_DSGCR_CUAEN_SHIFT - | 0x00000000U << DDR_PHY_DSGCR_RESERVED_4_3_SHIFT - | 0x00000000U << DDR_PHY_DSGCR_CTLZUEN_SHIFT - | 0x00000000U << DDR_PHY_DSGCR_RESERVED_1_SHIFT - | 0x00000001U << DDR_PHY_DSGCR_PUREN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DSGCR_OFFSET ,0xFFFFFFFFU ,0x02A04121U); - /*############################################################################################################################ */ + * Reserved. Return zeroes on reads + * PSU_DDR_PHY_DSGCR_RESERVED_4_3 0x0 - /*Register : DCR @ 0XFD080100

+ * Controller Impedance Update Enable + * PSU_DDR_PHY_DSGCR_CTLZUEN 0x0 - DDR4 Gear Down Timing. - PSU_DDR_PHY_DCR_GEARDN 0x0 + * Reserved. Return zeroes on reads + * PSU_DDR_PHY_DSGCR_RESERVED_1 0x0 - Un-used Bank Group - PSU_DDR_PHY_DCR_UBG 0x0 + * PHY Update Request Enable + * PSU_DDR_PHY_DSGCR_PUREN 0x1 - Un-buffered DIMM Address Mirroring - PSU_DDR_PHY_DCR_UDIMM 0x0 + * DDR System General Configuration Register + * (OFFSET, MASK, VALUE) (0XFD080090, 0xFFFFFFFFU ,0x02A04161U) + */ + PSU_Mask_Write(DDR_PHY_DSGCR_OFFSET, 0xFFFFFFFFU, 0x02A04161U); +/*##################################################################### */ - DDR 2T Timing - PSU_DDR_PHY_DCR_DDR2T 0x0 + /* + * Register : GPR0 @ 0XFD0800C0 - No Simultaneous Rank Access - PSU_DDR_PHY_DCR_NOSRA 0x1 + * General Purpose Register 0 + * PSU_DDR_PHY_GPR0_GPR0 0xd3 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DCR_RESERVED_26_18 0x0 + * General Purpose Register 0 + * (OFFSET, MASK, VALUE) (0XFD0800C0, 0xFFFFFFFFU ,0x000000D3U) + */ + PSU_Mask_Write(DDR_PHY_GPR0_OFFSET, 0xFFFFFFFFU, 0x000000D3U); +/*##################################################################### */ - Byte Mask - PSU_DDR_PHY_DCR_BYTEMASK 0x1 + /* + * Register : DCR @ 0XFD080100 - DDR Type - PSU_DDR_PHY_DCR_DDRTYPE 0x0 + * DDR4 Gear Down Timing. + * PSU_DDR_PHY_DCR_GEARDN 0x0 - Multi-Purpose Register (MPR) DQ (DDR3 Only) - PSU_DDR_PHY_DCR_MPRDQ 0x0 + * Un-used Bank Group + * PSU_DDR_PHY_DCR_UBG 0x0 - Primary DQ (DDR3 Only) - PSU_DDR_PHY_DCR_PDQ 0x0 + * Un-buffered DIMM Address Mirroring + * PSU_DDR_PHY_DCR_UDIMM 0x0 - DDR 8-Bank - PSU_DDR_PHY_DCR_DDR8BNK 0x1 + * DDR 2T Timing + * PSU_DDR_PHY_DCR_DDR2T 0x0 - DDR Mode - PSU_DDR_PHY_DCR_DDRMD 0x4 + * No Simultaneous Rank Access + * PSU_DDR_PHY_DCR_NOSRA 0x1 - DRAM Configuration Register - (OFFSET, MASK, VALUE) (0XFD080100, 0xFFFFFFFFU ,0x0800040CU) - RegMask = (DDR_PHY_DCR_GEARDN_MASK | DDR_PHY_DCR_UBG_MASK | DDR_PHY_DCR_UDIMM_MASK | DDR_PHY_DCR_DDR2T_MASK | DDR_PHY_DCR_NOSRA_MASK | DDR_PHY_DCR_RESERVED_26_18_MASK | DDR_PHY_DCR_BYTEMASK_MASK | DDR_PHY_DCR_DDRTYPE_MASK | DDR_PHY_DCR_MPRDQ_MASK | DDR_PHY_DCR_PDQ_MASK | DDR_PHY_DCR_DDR8BNK_MASK | DDR_PHY_DCR_DDRMD_MASK | 0 ); + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DCR_RESERVED_26_18 0x0 - RegVal = ((0x00000000U << DDR_PHY_DCR_GEARDN_SHIFT - | 0x00000000U << DDR_PHY_DCR_UBG_SHIFT - | 0x00000000U << DDR_PHY_DCR_UDIMM_SHIFT - | 0x00000000U << DDR_PHY_DCR_DDR2T_SHIFT - | 0x00000001U << DDR_PHY_DCR_NOSRA_SHIFT - | 0x00000000U << DDR_PHY_DCR_RESERVED_26_18_SHIFT - | 0x00000001U << DDR_PHY_DCR_BYTEMASK_SHIFT - | 0x00000000U << DDR_PHY_DCR_DDRTYPE_SHIFT - | 0x00000000U << DDR_PHY_DCR_MPRDQ_SHIFT - | 0x00000000U << DDR_PHY_DCR_PDQ_SHIFT - | 0x00000001U << DDR_PHY_DCR_DDR8BNK_SHIFT - | 0x00000004U << DDR_PHY_DCR_DDRMD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DCR_OFFSET ,0xFFFFFFFFU ,0x0800040CU); - /*############################################################################################################################ */ - - /*Register : DTPR0 @ 0XFD080110

+ * Byte Mask + * PSU_DDR_PHY_DCR_BYTEMASK 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR0_RESERVED_31_29 0x0 + * DDR Type + * PSU_DDR_PHY_DCR_DDRTYPE 0x0 - Activate to activate command delay (different banks) - PSU_DDR_PHY_DTPR0_TRRD 0x6 + * Multi-Purpose Register (MPR) DQ (DDR3 Only) + * PSU_DDR_PHY_DCR_MPRDQ 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR0_RESERVED_23 0x0 + * Primary DQ (DDR3 Only) + * PSU_DDR_PHY_DCR_PDQ 0x0 - Activate to precharge command delay - PSU_DDR_PHY_DTPR0_TRAS 0x24 + * DDR 8-Bank + * PSU_DDR_PHY_DCR_DDR8BNK 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR0_RESERVED_15 0x0 - - Precharge command period - PSU_DDR_PHY_DTPR0_TRP 0xf - - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR0_RESERVED_7_5 0x0 - - Internal read to precharge command delay - PSU_DDR_PHY_DTPR0_TRTP 0x9 - - DRAM Timing Parameters Register 0 - (OFFSET, MASK, VALUE) (0XFD080110, 0xFFFFFFFFU ,0x06240F09U) - RegMask = (DDR_PHY_DTPR0_RESERVED_31_29_MASK | DDR_PHY_DTPR0_TRRD_MASK | DDR_PHY_DTPR0_RESERVED_23_MASK | DDR_PHY_DTPR0_TRAS_MASK | DDR_PHY_DTPR0_RESERVED_15_MASK | DDR_PHY_DTPR0_TRP_MASK | DDR_PHY_DTPR0_RESERVED_7_5_MASK | DDR_PHY_DTPR0_TRTP_MASK | 0 ); + * DDR Mode + * PSU_DDR_PHY_DCR_DDRMD 0x4 - RegVal = ((0x00000000U << DDR_PHY_DTPR0_RESERVED_31_29_SHIFT - | 0x00000006U << DDR_PHY_DTPR0_TRRD_SHIFT - | 0x00000000U << DDR_PHY_DTPR0_RESERVED_23_SHIFT - | 0x00000024U << DDR_PHY_DTPR0_TRAS_SHIFT - | 0x00000000U << DDR_PHY_DTPR0_RESERVED_15_SHIFT - | 0x0000000FU << DDR_PHY_DTPR0_TRP_SHIFT - | 0x00000000U << DDR_PHY_DTPR0_RESERVED_7_5_SHIFT - | 0x00000009U << DDR_PHY_DTPR0_TRTP_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DTPR0_OFFSET ,0xFFFFFFFFU ,0x06240F09U); - /*############################################################################################################################ */ + * DRAM Configuration Register + * (OFFSET, MASK, VALUE) (0XFD080100, 0xFFFFFFFFU ,0x0800040CU) + */ + PSU_Mask_Write(DDR_PHY_DCR_OFFSET, 0xFFFFFFFFU, 0x0800040CU); +/*##################################################################### */ - /*Register : DTPR1 @ 0XFD080114

+ /* + * Register : DTPR0 @ 0XFD080110 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR1_RESERVED_31 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR0_RESERVED_31_29 0x0 - Minimum delay from when write leveling mode is programmed to the first DQS/DQS# rising edge. - PSU_DDR_PHY_DTPR1_TWLMRD 0x28 + * Activate to activate command delay (different banks) + * PSU_DDR_PHY_DTPR0_TRRD 0x6 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR1_RESERVED_23 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR0_RESERVED_23 0x0 - 4-bank activate period - PSU_DDR_PHY_DTPR1_TFAW 0x18 + * Activate to precharge command delay + * PSU_DDR_PHY_DTPR0_TRAS 0x24 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR1_RESERVED_15_11 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR0_RESERVED_15 0x0 - Load mode update delay (DDR4 and DDR3 only) - PSU_DDR_PHY_DTPR1_TMOD 0x7 + * Precharge command period + * PSU_DDR_PHY_DTPR0_TRP 0xf - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR1_RESERVED_7_5 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR0_RESERVED_7_5 0x0 - Load mode cycle time - PSU_DDR_PHY_DTPR1_TMRD 0x8 + * Internal read to precharge command delay + * PSU_DDR_PHY_DTPR0_TRTP 0x8 - DRAM Timing Parameters Register 1 - (OFFSET, MASK, VALUE) (0XFD080114, 0xFFFFFFFFU ,0x28180708U) - RegMask = (DDR_PHY_DTPR1_RESERVED_31_MASK | DDR_PHY_DTPR1_TWLMRD_MASK | DDR_PHY_DTPR1_RESERVED_23_MASK | DDR_PHY_DTPR1_TFAW_MASK | DDR_PHY_DTPR1_RESERVED_15_11_MASK | DDR_PHY_DTPR1_TMOD_MASK | DDR_PHY_DTPR1_RESERVED_7_5_MASK | DDR_PHY_DTPR1_TMRD_MASK | 0 ); + * DRAM Timing Parameters Register 0 + * (OFFSET, MASK, VALUE) (0XFD080110, 0xFFFFFFFFU ,0x06240F08U) + */ + PSU_Mask_Write(DDR_PHY_DTPR0_OFFSET, 0xFFFFFFFFU, 0x06240F08U); +/*##################################################################### */ - RegVal = ((0x00000000U << DDR_PHY_DTPR1_RESERVED_31_SHIFT - | 0x00000028U << DDR_PHY_DTPR1_TWLMRD_SHIFT - | 0x00000000U << DDR_PHY_DTPR1_RESERVED_23_SHIFT - | 0x00000018U << DDR_PHY_DTPR1_TFAW_SHIFT - | 0x00000000U << DDR_PHY_DTPR1_RESERVED_15_11_SHIFT - | 0x00000007U << DDR_PHY_DTPR1_TMOD_SHIFT - | 0x00000000U << DDR_PHY_DTPR1_RESERVED_7_5_SHIFT - | 0x00000008U << DDR_PHY_DTPR1_TMRD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DTPR1_OFFSET ,0xFFFFFFFFU ,0x28180708U); - /*############################################################################################################################ */ + /* + * Register : DTPR1 @ 0XFD080114 - /*Register : DTPR2 @ 0XFD080118

+ * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR1_RESERVED_31 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR2_RESERVED_31_29 0x0 + * Minimum delay from when write leveling mode is programmed to the first D + * QS/DQS# rising edge. + * PSU_DDR_PHY_DTPR1_TWLMRD 0x28 - Read to Write command delay. Valid values are - PSU_DDR_PHY_DTPR2_TRTW 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR1_RESERVED_23 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR2_RESERVED_27_25 0x0 + * 4-bank activate period + * PSU_DDR_PHY_DTPR1_TFAW 0x20 - Read to ODT delay (DDR3 only) - PSU_DDR_PHY_DTPR2_TRTODT 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR1_RESERVED_15_11 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR2_RESERVED_23_20 0x0 + * Load mode update delay (DDR4 and DDR3 only) + * PSU_DDR_PHY_DTPR1_TMOD 0x0 - CKE minimum pulse width - PSU_DDR_PHY_DTPR2_TCKE 0x8 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR1_RESERVED_7_5 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR2_RESERVED_15_10 0x0 + * Load mode cycle time + * PSU_DDR_PHY_DTPR1_TMRD 0x8 - Self refresh exit delay - PSU_DDR_PHY_DTPR2_TXS 0x200 + * DRAM Timing Parameters Register 1 + * (OFFSET, MASK, VALUE) (0XFD080114, 0xFFFFFFFFU ,0x28200008U) + */ + PSU_Mask_Write(DDR_PHY_DTPR1_OFFSET, 0xFFFFFFFFU, 0x28200008U); +/*##################################################################### */ - DRAM Timing Parameters Register 2 - (OFFSET, MASK, VALUE) (0XFD080118, 0xFFFFFFFFU ,0x00080200U) - RegMask = (DDR_PHY_DTPR2_RESERVED_31_29_MASK | DDR_PHY_DTPR2_TRTW_MASK | DDR_PHY_DTPR2_RESERVED_27_25_MASK | DDR_PHY_DTPR2_TRTODT_MASK | DDR_PHY_DTPR2_RESERVED_23_20_MASK | DDR_PHY_DTPR2_TCKE_MASK | DDR_PHY_DTPR2_RESERVED_15_10_MASK | DDR_PHY_DTPR2_TXS_MASK | 0 ); + /* + * Register : DTPR2 @ 0XFD080118 - RegVal = ((0x00000000U << DDR_PHY_DTPR2_RESERVED_31_29_SHIFT - | 0x00000000U << DDR_PHY_DTPR2_TRTW_SHIFT - | 0x00000000U << DDR_PHY_DTPR2_RESERVED_27_25_SHIFT - | 0x00000000U << DDR_PHY_DTPR2_TRTODT_SHIFT - | 0x00000000U << DDR_PHY_DTPR2_RESERVED_23_20_SHIFT - | 0x00000008U << DDR_PHY_DTPR2_TCKE_SHIFT - | 0x00000000U << DDR_PHY_DTPR2_RESERVED_15_10_SHIFT - | 0x00000200U << DDR_PHY_DTPR2_TXS_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DTPR2_OFFSET ,0xFFFFFFFFU ,0x00080200U); - /*############################################################################################################################ */ + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR2_RESERVED_31_29 0x0 - /*Register : DTPR3 @ 0XFD08011C

+ * Read to Write command delay. Valid values are + * PSU_DDR_PHY_DTPR2_TRTW 0x0 - ODT turn-off delay extension - PSU_DDR_PHY_DTPR3_TOFDX 0x4 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR2_RESERVED_27_25 0x0 - Read to read and write to write command delay - PSU_DDR_PHY_DTPR3_TCCD 0x0 + * Read to ODT delay (DDR3 only) + * PSU_DDR_PHY_DTPR2_TRTODT 0x0 - DLL locking time - PSU_DDR_PHY_DTPR3_TDLLK 0x300 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR2_RESERVED_23_20 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR3_RESERVED_15_12 0x0 + * CKE minimum pulse width + * PSU_DDR_PHY_DTPR2_TCKE 0x7 - Maximum DQS output access time from CK/CK# (LPDDR2/3 only) - PSU_DDR_PHY_DTPR3_TDQSCKMAX 0x8 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR2_RESERVED_15_10 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR3_RESERVED_7_3 0x0 + * Self refresh exit delay + * PSU_DDR_PHY_DTPR2_TXS 0x300 - DQS output access time from CK/CK# (LPDDR2/3 only) - PSU_DDR_PHY_DTPR3_TDQSCK 0x0 + * DRAM Timing Parameters Register 2 + * (OFFSET, MASK, VALUE) (0XFD080118, 0xFFFFFFFFU ,0x00070300U) + */ + PSU_Mask_Write(DDR_PHY_DTPR2_OFFSET, 0xFFFFFFFFU, 0x00070300U); +/*##################################################################### */ - DRAM Timing Parameters Register 3 - (OFFSET, MASK, VALUE) (0XFD08011C, 0xFFFFFFFFU ,0x83000800U) - RegMask = (DDR_PHY_DTPR3_TOFDX_MASK | DDR_PHY_DTPR3_TCCD_MASK | DDR_PHY_DTPR3_TDLLK_MASK | DDR_PHY_DTPR3_RESERVED_15_12_MASK | DDR_PHY_DTPR3_TDQSCKMAX_MASK | DDR_PHY_DTPR3_RESERVED_7_3_MASK | DDR_PHY_DTPR3_TDQSCK_MASK | 0 ); + /* + * Register : DTPR3 @ 0XFD08011C - RegVal = ((0x00000004U << DDR_PHY_DTPR3_TOFDX_SHIFT - | 0x00000000U << DDR_PHY_DTPR3_TCCD_SHIFT - | 0x00000300U << DDR_PHY_DTPR3_TDLLK_SHIFT - | 0x00000000U << DDR_PHY_DTPR3_RESERVED_15_12_SHIFT - | 0x00000008U << DDR_PHY_DTPR3_TDQSCKMAX_SHIFT - | 0x00000000U << DDR_PHY_DTPR3_RESERVED_7_3_SHIFT - | 0x00000000U << DDR_PHY_DTPR3_TDQSCK_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DTPR3_OFFSET ,0xFFFFFFFFU ,0x83000800U); - /*############################################################################################################################ */ + * ODT turn-off delay extension + * PSU_DDR_PHY_DTPR3_TOFDX 0x4 - /*Register : DTPR4 @ 0XFD080120

+ * Read to read and write to write command delay + * PSU_DDR_PHY_DTPR3_TCCD 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR4_RESERVED_31_30 0x0 + * DLL locking time + * PSU_DDR_PHY_DTPR3_TDLLK 0x300 - ODT turn-on/turn-off delays (DDR2 only) - PSU_DDR_PHY_DTPR4_TAOND_TAOFD 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR3_RESERVED_15_12 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR4_RESERVED_27_26 0x0 + * Maximum DQS output access time from CK/CK# (LPDDR2/3 only) + * PSU_DDR_PHY_DTPR3_TDQSCKMAX 0x8 - Refresh-to-Refresh - PSU_DDR_PHY_DTPR4_TRFC 0x116 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR3_RESERVED_7_3 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR4_RESERVED_15_14 0x0 + * DQS output access time from CK/CK# (LPDDR2/3 only) + * PSU_DDR_PHY_DTPR3_TDQSCK 0x0 - Write leveling output delay - PSU_DDR_PHY_DTPR4_TWLO 0x2b + * DRAM Timing Parameters Register 3 + * (OFFSET, MASK, VALUE) (0XFD08011C, 0xFFFFFFFFU ,0x83000800U) + */ + PSU_Mask_Write(DDR_PHY_DTPR3_OFFSET, 0xFFFFFFFFU, 0x83000800U); +/*##################################################################### */ - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR4_RESERVED_7_5 0x0 + /* + * Register : DTPR4 @ 0XFD080120 - Power down exit delay - PSU_DDR_PHY_DTPR4_TXP 0x8 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR4_RESERVED_31_30 0x0 - DRAM Timing Parameters Register 4 - (OFFSET, MASK, VALUE) (0XFD080120, 0xFFFFFFFFU ,0x01162B08U) - RegMask = (DDR_PHY_DTPR4_RESERVED_31_30_MASK | DDR_PHY_DTPR4_TAOND_TAOFD_MASK | DDR_PHY_DTPR4_RESERVED_27_26_MASK | DDR_PHY_DTPR4_TRFC_MASK | DDR_PHY_DTPR4_RESERVED_15_14_MASK | DDR_PHY_DTPR4_TWLO_MASK | DDR_PHY_DTPR4_RESERVED_7_5_MASK | DDR_PHY_DTPR4_TXP_MASK | 0 ); + * ODT turn-on/turn-off delays (DDR2 only) + * PSU_DDR_PHY_DTPR4_TAOND_TAOFD 0x0 - RegVal = ((0x00000000U << DDR_PHY_DTPR4_RESERVED_31_30_SHIFT - | 0x00000000U << DDR_PHY_DTPR4_TAOND_TAOFD_SHIFT - | 0x00000000U << DDR_PHY_DTPR4_RESERVED_27_26_SHIFT - | 0x00000116U << DDR_PHY_DTPR4_TRFC_SHIFT - | 0x00000000U << DDR_PHY_DTPR4_RESERVED_15_14_SHIFT - | 0x0000002BU << DDR_PHY_DTPR4_TWLO_SHIFT - | 0x00000000U << DDR_PHY_DTPR4_RESERVED_7_5_SHIFT - | 0x00000008U << DDR_PHY_DTPR4_TXP_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DTPR4_OFFSET ,0xFFFFFFFFU ,0x01162B08U); - /*############################################################################################################################ */ + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR4_RESERVED_27_26 0x0 - /*Register : DTPR5 @ 0XFD080124

+ * Refresh-to-Refresh + * PSU_DDR_PHY_DTPR4_TRFC 0x116 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR5_RESERVED_31_24 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR4_RESERVED_15_14 0x0 - Activate to activate command delay (same bank) - PSU_DDR_PHY_DTPR5_TRC 0x32 + * Write leveling output delay + * PSU_DDR_PHY_DTPR4_TWLO 0x2b - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR5_RESERVED_15 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR4_RESERVED_7_5 0x0 - Activate to read or write delay - PSU_DDR_PHY_DTPR5_TRCD 0xf + * Power down exit delay + * PSU_DDR_PHY_DTPR4_TXP 0x7 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR5_RESERVED_7_5 0x0 + * DRAM Timing Parameters Register 4 + * (OFFSET, MASK, VALUE) (0XFD080120, 0xFFFFFFFFU ,0x01162B07U) + */ + PSU_Mask_Write(DDR_PHY_DTPR4_OFFSET, 0xFFFFFFFFU, 0x01162B07U); +/*##################################################################### */ - Internal write to read command delay - PSU_DDR_PHY_DTPR5_TWTR 0x9 + /* + * Register : DTPR5 @ 0XFD080124 - DRAM Timing Parameters Register 5 - (OFFSET, MASK, VALUE) (0XFD080124, 0xFFFFFFFFU ,0x00320F09U) - RegMask = (DDR_PHY_DTPR5_RESERVED_31_24_MASK | DDR_PHY_DTPR5_TRC_MASK | DDR_PHY_DTPR5_RESERVED_15_MASK | DDR_PHY_DTPR5_TRCD_MASK | DDR_PHY_DTPR5_RESERVED_7_5_MASK | DDR_PHY_DTPR5_TWTR_MASK | 0 ); + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR5_RESERVED_31_24 0x0 - RegVal = ((0x00000000U << DDR_PHY_DTPR5_RESERVED_31_24_SHIFT - | 0x00000032U << DDR_PHY_DTPR5_TRC_SHIFT - | 0x00000000U << DDR_PHY_DTPR5_RESERVED_15_SHIFT - | 0x0000000FU << DDR_PHY_DTPR5_TRCD_SHIFT - | 0x00000000U << DDR_PHY_DTPR5_RESERVED_7_5_SHIFT - | 0x00000009U << DDR_PHY_DTPR5_TWTR_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DTPR5_OFFSET ,0xFFFFFFFFU ,0x00320F09U); - /*############################################################################################################################ */ + * Activate to activate command delay (same bank) + * PSU_DDR_PHY_DTPR5_TRC 0x33 - /*Register : DTPR6 @ 0XFD080128

+ * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR5_RESERVED_15 0x0 - PUB Write Latency Enable - PSU_DDR_PHY_DTPR6_PUBWLEN 0x0 + * Activate to read or write delay + * PSU_DDR_PHY_DTPR5_TRCD 0xf - PUB Read Latency Enable - PSU_DDR_PHY_DTPR6_PUBRLEN 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR5_RESERVED_7_5 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR6_RESERVED_29_14 0x0 + * Internal write to read command delay + * PSU_DDR_PHY_DTPR5_TWTR 0x8 - Write Latency - PSU_DDR_PHY_DTPR6_PUBWL 0xe + * DRAM Timing Parameters Register 5 + * (OFFSET, MASK, VALUE) (0XFD080124, 0xFFFFFFFFU ,0x00330F08U) + */ + PSU_Mask_Write(DDR_PHY_DTPR5_OFFSET, 0xFFFFFFFFU, 0x00330F08U); +/*##################################################################### */ - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR6_RESERVED_7_6 0x0 + /* + * Register : DTPR6 @ 0XFD080128 - Read Latency - PSU_DDR_PHY_DTPR6_PUBRL 0xf + * PUB Write Latency Enable + * PSU_DDR_PHY_DTPR6_PUBWLEN 0x0 - DRAM Timing Parameters Register 6 - (OFFSET, MASK, VALUE) (0XFD080128, 0xFFFFFFFFU ,0x00000E0FU) - RegMask = (DDR_PHY_DTPR6_PUBWLEN_MASK | DDR_PHY_DTPR6_PUBRLEN_MASK | DDR_PHY_DTPR6_RESERVED_29_14_MASK | DDR_PHY_DTPR6_PUBWL_MASK | DDR_PHY_DTPR6_RESERVED_7_6_MASK | DDR_PHY_DTPR6_PUBRL_MASK | 0 ); + * PUB Read Latency Enable + * PSU_DDR_PHY_DTPR6_PUBRLEN 0x0 - RegVal = ((0x00000000U << DDR_PHY_DTPR6_PUBWLEN_SHIFT - | 0x00000000U << DDR_PHY_DTPR6_PUBRLEN_SHIFT - | 0x00000000U << DDR_PHY_DTPR6_RESERVED_29_14_SHIFT - | 0x0000000EU << DDR_PHY_DTPR6_PUBWL_SHIFT - | 0x00000000U << DDR_PHY_DTPR6_RESERVED_7_6_SHIFT - | 0x0000000FU << DDR_PHY_DTPR6_PUBRL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DTPR6_OFFSET ,0xFFFFFFFFU ,0x00000E0FU); - /*############################################################################################################################ */ + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR6_RESERVED_29_14 0x0 - /*Register : RDIMMGCR0 @ 0XFD080140

+ * Write Latency + * PSU_DDR_PHY_DTPR6_PUBWL 0xe - Reserved. Return zeroes on reads. - PSU_DDR_PHY_RDIMMGCR0_RESERVED_31 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR6_RESERVED_7_6 0x0 - RDMIMM Quad CS Enable - PSU_DDR_PHY_RDIMMGCR0_QCSEN 0x0 + * Read Latency + * PSU_DDR_PHY_DTPR6_PUBRL 0xf - Reserved. Return zeroes on reads. - PSU_DDR_PHY_RDIMMGCR0_RESERVED_29_28 0x0 + * DRAM Timing Parameters Register 6 + * (OFFSET, MASK, VALUE) (0XFD080128, 0xFFFFFFFFU ,0x00000E0FU) + */ + PSU_Mask_Write(DDR_PHY_DTPR6_OFFSET, 0xFFFFFFFFU, 0x00000E0FU); +/*##################################################################### */ - RDIMM Outputs I/O Mode - PSU_DDR_PHY_RDIMMGCR0_RDIMMIOM 0x1 + /* + * Register : RDIMMGCR0 @ 0XFD080140 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_RDIMMGCR0_RESERVED_26_24 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_RDIMMGCR0_RESERVED_31 0x0 - ERROUT# Output Enable - PSU_DDR_PHY_RDIMMGCR0_ERROUTOE 0x0 + * RDMIMM Quad CS Enable + * PSU_DDR_PHY_RDIMMGCR0_QCSEN 0x0 - ERROUT# I/O Mode - PSU_DDR_PHY_RDIMMGCR0_ERROUTIOM 0x1 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_RDIMMGCR0_RESERVED_29_28 0x0 - ERROUT# Power Down Receiver - PSU_DDR_PHY_RDIMMGCR0_ERROUTPDR 0x0 + * RDIMM Outputs I/O Mode + * PSU_DDR_PHY_RDIMMGCR0_RDIMMIOM 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_RDIMMGCR0_RESERVED_20 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_RDIMMGCR0_RESERVED_26_24 0x0 - ERROUT# On-Die Termination - PSU_DDR_PHY_RDIMMGCR0_ERROUTODT 0x0 + * ERROUT# Output Enable + * PSU_DDR_PHY_RDIMMGCR0_ERROUTOE 0x0 - Load Reduced DIMM - PSU_DDR_PHY_RDIMMGCR0_LRDIMM 0x0 + * ERROUT# I/O Mode + * PSU_DDR_PHY_RDIMMGCR0_ERROUTIOM 0x1 - PAR_IN I/O Mode - PSU_DDR_PHY_RDIMMGCR0_PARINIOM 0x0 + * ERROUT# Power Down Receiver + * PSU_DDR_PHY_RDIMMGCR0_ERROUTPDR 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_RDIMMGCR0_RESERVED_16_8 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_RDIMMGCR0_RESERVED_20 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD 0x0 + * ERROUT# On-Die Termination + * PSU_DDR_PHY_RDIMMGCR0_ERROUTODT 0x0 - Rank Mirror Enable. - PSU_DDR_PHY_RDIMMGCR0_RNKMRREN 0x2 + * Load Reduced DIMM + * PSU_DDR_PHY_RDIMMGCR0_LRDIMM 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_RDIMMGCR0_RESERVED_3 0x0 + * PAR_IN I/O Mode + * PSU_DDR_PHY_RDIMMGCR0_PARINIOM 0x0 - Stop on Parity Error - PSU_DDR_PHY_RDIMMGCR0_SOPERR 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_RDIMMGCR0_RESERVED_16_8 0x0 - Parity Error No Registering - PSU_DDR_PHY_RDIMMGCR0_ERRNOREG 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD 0x0 - Registered DIMM - PSU_DDR_PHY_RDIMMGCR0_RDIMM 0x0 + * Rank Mirror Enable. + * PSU_DDR_PHY_RDIMMGCR0_RNKMRREN 0x2 - RDIMM General Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD080140, 0xFFFFFFFFU ,0x08400020U) - RegMask = (DDR_PHY_RDIMMGCR0_RESERVED_31_MASK | DDR_PHY_RDIMMGCR0_QCSEN_MASK | DDR_PHY_RDIMMGCR0_RESERVED_29_28_MASK | DDR_PHY_RDIMMGCR0_RDIMMIOM_MASK | DDR_PHY_RDIMMGCR0_RESERVED_26_24_MASK | DDR_PHY_RDIMMGCR0_ERROUTOE_MASK | DDR_PHY_RDIMMGCR0_ERROUTIOM_MASK | DDR_PHY_RDIMMGCR0_ERROUTPDR_MASK | DDR_PHY_RDIMMGCR0_RESERVED_20_MASK | DDR_PHY_RDIMMGCR0_ERROUTODT_MASK | DDR_PHY_RDIMMGCR0_LRDIMM_MASK | DDR_PHY_RDIMMGCR0_PARINIOM_MASK | DDR_PHY_RDIMMGCR0_RESERVED_16_8_MASK | DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_MASK | DDR_PHY_RDIMMGCR0_RNKMRREN_MASK | DDR_PHY_RDIMMGCR0_RESERVED_3_MASK | DDR_PHY_RDIMMGCR0_SOPERR_MASK | DDR_PHY_RDIMMGCR0_ERRNOREG_MASK | DDR_PHY_RDIMMGCR0_RDIMM_MASK | 0 ); + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_RDIMMGCR0_RESERVED_3 0x0 - RegVal = ((0x00000000U << DDR_PHY_RDIMMGCR0_RESERVED_31_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR0_QCSEN_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR0_RESERVED_29_28_SHIFT - | 0x00000001U << DDR_PHY_RDIMMGCR0_RDIMMIOM_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR0_RESERVED_26_24_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR0_ERROUTOE_SHIFT - | 0x00000001U << DDR_PHY_RDIMMGCR0_ERROUTIOM_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR0_ERROUTPDR_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR0_RESERVED_20_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR0_ERROUTODT_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR0_LRDIMM_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR0_PARINIOM_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR0_RESERVED_16_8_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_SHIFT - | 0x00000002U << DDR_PHY_RDIMMGCR0_RNKMRREN_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR0_RESERVED_3_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR0_SOPERR_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR0_ERRNOREG_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR0_RDIMM_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_RDIMMGCR0_OFFSET ,0xFFFFFFFFU ,0x08400020U); - /*############################################################################################################################ */ + * Stop on Parity Error + * PSU_DDR_PHY_RDIMMGCR0_SOPERR 0x0 - /*Register : RDIMMGCR1 @ 0XFD080144

+ * Parity Error No Registering + * PSU_DDR_PHY_RDIMMGCR0_ERRNOREG 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_RDIMMGCR1_RESERVED_31_29 0x0 + * Registered DIMM + * PSU_DDR_PHY_RDIMMGCR0_RDIMM 0x0 - Address [17] B-side Inversion Disable - PSU_DDR_PHY_RDIMMGCR1_A17BID 0x0 + * RDIMM General Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD080140, 0xFFFFFFFFU ,0x08400020U) + */ + PSU_Mask_Write(DDR_PHY_RDIMMGCR0_OFFSET, 0xFFFFFFFFU, 0x08400020U); +/*##################################################################### */ - Reserved. Return zeroes on reads. - PSU_DDR_PHY_RDIMMGCR1_RESERVED_27 0x0 + /* + * Register : RDIMMGCR1 @ 0XFD080144 - Command word to command word programming delay - PSU_DDR_PHY_RDIMMGCR1_TBCMRD_L2 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_RDIMMGCR1_RESERVED_31_29 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_RDIMMGCR1_RESERVED_23 0x0 + * Address [17] B-side Inversion Disable + * PSU_DDR_PHY_RDIMMGCR1_A17BID 0x0 - Command word to command word programming delay - PSU_DDR_PHY_RDIMMGCR1_TBCMRD_L 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_RDIMMGCR1_RESERVED_27 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_RDIMMGCR1_RESERVED_19 0x0 + * Command word to command word programming delay + * PSU_DDR_PHY_RDIMMGCR1_TBCMRD_L2 0x0 - Command word to command word programming delay - PSU_DDR_PHY_RDIMMGCR1_TBCMRD 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_RDIMMGCR1_RESERVED_23 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_RDIMMGCR1_RESERVED_15_14 0x0 + * Command word to command word programming delay + * PSU_DDR_PHY_RDIMMGCR1_TBCMRD_L 0x0 - Stabilization time - PSU_DDR_PHY_RDIMMGCR1_TBCSTAB 0xc80 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_RDIMMGCR1_RESERVED_19 0x0 - RDIMM General Configuration Register 1 - (OFFSET, MASK, VALUE) (0XFD080144, 0xFFFFFFFFU ,0x00000C80U) - RegMask = (DDR_PHY_RDIMMGCR1_RESERVED_31_29_MASK | DDR_PHY_RDIMMGCR1_A17BID_MASK | DDR_PHY_RDIMMGCR1_RESERVED_27_MASK | DDR_PHY_RDIMMGCR1_TBCMRD_L2_MASK | DDR_PHY_RDIMMGCR1_RESERVED_23_MASK | DDR_PHY_RDIMMGCR1_TBCMRD_L_MASK | DDR_PHY_RDIMMGCR1_RESERVED_19_MASK | DDR_PHY_RDIMMGCR1_TBCMRD_MASK | DDR_PHY_RDIMMGCR1_RESERVED_15_14_MASK | DDR_PHY_RDIMMGCR1_TBCSTAB_MASK | 0 ); - - RegVal = ((0x00000000U << DDR_PHY_RDIMMGCR1_RESERVED_31_29_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR1_A17BID_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR1_RESERVED_27_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR1_TBCMRD_L2_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR1_RESERVED_23_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR1_TBCMRD_L_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR1_RESERVED_19_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR1_TBCMRD_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR1_RESERVED_15_14_SHIFT - | 0x00000C80U << DDR_PHY_RDIMMGCR1_TBCSTAB_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_RDIMMGCR1_OFFSET ,0xFFFFFFFFU ,0x00000C80U); - /*############################################################################################################################ */ - - /*Register : RDIMMCR0 @ 0XFD080150

+ * Command word to command word programming delay + * PSU_DDR_PHY_RDIMMGCR1_TBCMRD 0x0 - DDR4/DDR3 Control Word 7 - PSU_DDR_PHY_RDIMMCR0_RC7 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_RDIMMGCR1_RESERVED_15_14 0x0 - DDR4 Control Word 6 (Comman space Control Word) / DDR3 Reserved - PSU_DDR_PHY_RDIMMCR0_RC6 0x0 - - DDR4/DDR3 Control Word 5 (CK Driver Characteristics Control Word) - PSU_DDR_PHY_RDIMMCR0_RC5 0x0 - - DDR4 Control Word 4 (ODT and CKE Signals Driver Characteristics Control Word) / DDR3 Control Word 4 (Control Signals Driver C - aracteristics Control Word) - PSU_DDR_PHY_RDIMMCR0_RC4 0x0 - - DDR4 Control Word 3 (CA and CS Signals Driver Characteristics Control Word) / DDR3 Control Word 3 (Command/Address Signals Dr - ver Characteristrics Control Word) - PSU_DDR_PHY_RDIMMCR0_RC3 0x0 - - DDR4 Control Word 2 (Timing and IBT Control Word) / DDR3 Control Word 2 (Timing Control Word) - PSU_DDR_PHY_RDIMMCR0_RC2 0x0 - - DDR4/DDR3 Control Word 1 (Clock Driver Enable Control Word) - PSU_DDR_PHY_RDIMMCR0_RC1 0x0 - - DDR4/DDR3 Control Word 0 (Global Features Control Word) - PSU_DDR_PHY_RDIMMCR0_RC0 0x0 - - RDIMM Control Register 0 - (OFFSET, MASK, VALUE) (0XFD080150, 0xFFFFFFFFU ,0x00000000U) - RegMask = (DDR_PHY_RDIMMCR0_RC7_MASK | DDR_PHY_RDIMMCR0_RC6_MASK | DDR_PHY_RDIMMCR0_RC5_MASK | DDR_PHY_RDIMMCR0_RC4_MASK | DDR_PHY_RDIMMCR0_RC3_MASK | DDR_PHY_RDIMMCR0_RC2_MASK | DDR_PHY_RDIMMCR0_RC1_MASK | DDR_PHY_RDIMMCR0_RC0_MASK | 0 ); - - RegVal = ((0x00000000U << DDR_PHY_RDIMMCR0_RC7_SHIFT - | 0x00000000U << DDR_PHY_RDIMMCR0_RC6_SHIFT - | 0x00000000U << DDR_PHY_RDIMMCR0_RC5_SHIFT - | 0x00000000U << DDR_PHY_RDIMMCR0_RC4_SHIFT - | 0x00000000U << DDR_PHY_RDIMMCR0_RC3_SHIFT - | 0x00000000U << DDR_PHY_RDIMMCR0_RC2_SHIFT - | 0x00000000U << DDR_PHY_RDIMMCR0_RC1_SHIFT - | 0x00000000U << DDR_PHY_RDIMMCR0_RC0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_RDIMMCR0_OFFSET ,0xFFFFFFFFU ,0x00000000U); - /*############################################################################################################################ */ + * Stabilization time + * PSU_DDR_PHY_RDIMMGCR1_TBCSTAB 0xc80 - /*Register : RDIMMCR1 @ 0XFD080154

+ * RDIMM General Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD080144, 0xFFFFFFFFU ,0x00000C80U) + */ + PSU_Mask_Write(DDR_PHY_RDIMMGCR1_OFFSET, 0xFFFFFFFFU, 0x00000C80U); +/*##################################################################### */ - Control Word 15 - PSU_DDR_PHY_RDIMMCR1_RC15 0x0 + /* + * Register : RDIMMCR0 @ 0XFD080150 - DDR4 Control Word 14 (Parity Control Word) / DDR3 Reserved - PSU_DDR_PHY_RDIMMCR1_RC14 0x0 + * DDR4/DDR3 Control Word 7 + * PSU_DDR_PHY_RDIMMCR0_RC7 0x0 - DDR4 Control Word 13 (DIMM Configuration Control Word) / DDR3 Reserved - PSU_DDR_PHY_RDIMMCR1_RC13 0x0 + * DDR4 Control Word 6 (Comman space Control Word) / DDR3 Reserved + * PSU_DDR_PHY_RDIMMCR0_RC6 0x0 - DDR4 Control Word 12 (Training Control Word) / DDR3 Reserved - PSU_DDR_PHY_RDIMMCR1_RC12 0x0 + * DDR4/DDR3 Control Word 5 (CK Driver Characteristics Control Word) + * PSU_DDR_PHY_RDIMMCR0_RC5 0x0 - DDR4 Control Word 11 (Operating Voltage VDD and VREFCA Source Control Word) / DDR3 Control Word 11 (Operation Voltage VDD Con - rol Word) - PSU_DDR_PHY_RDIMMCR1_RC11 0x0 + * DDR4 Control Word 4 (ODT and CKE Signals Driver Characteristics Control + * Word) / DDR3 Control Word 4 (Control Signals Driver Characteristics Cont + * rol Word) + * PSU_DDR_PHY_RDIMMCR0_RC4 0x0 - DDR4/DDR3 Control Word 10 (RDIMM Operating Speed Control Word) - PSU_DDR_PHY_RDIMMCR1_RC10 0x2 + * DDR4 Control Word 3 (CA and CS Signals Driver Characteristics Control Wo + * rd) / DDR3 Control Word 3 (Command/Address Signals Driver Characteristri + * cs Control Word) + * PSU_DDR_PHY_RDIMMCR0_RC3 0x0 - DDR4/DDR3 Control Word 9 (Power Saving Settings Control Word) - PSU_DDR_PHY_RDIMMCR1_RC9 0x0 + * DDR4 Control Word 2 (Timing and IBT Control Word) / DDR3 Control Word 2 + * (Timing Control Word) + * PSU_DDR_PHY_RDIMMCR0_RC2 0x0 - DDR4 Control Word 8 (Input/Output Configuration Control Word) / DDR3 Control Word 8 (Additional Input Bus Termination Setting - Control Word) - PSU_DDR_PHY_RDIMMCR1_RC8 0x0 + * DDR4/DDR3 Control Word 1 (Clock Driver Enable Control Word) + * PSU_DDR_PHY_RDIMMCR0_RC1 0x0 - RDIMM Control Register 1 - (OFFSET, MASK, VALUE) (0XFD080154, 0xFFFFFFFFU ,0x00000200U) - RegMask = (DDR_PHY_RDIMMCR1_RC15_MASK | DDR_PHY_RDIMMCR1_RC14_MASK | DDR_PHY_RDIMMCR1_RC13_MASK | DDR_PHY_RDIMMCR1_RC12_MASK | DDR_PHY_RDIMMCR1_RC11_MASK | DDR_PHY_RDIMMCR1_RC10_MASK | DDR_PHY_RDIMMCR1_RC9_MASK | DDR_PHY_RDIMMCR1_RC8_MASK | 0 ); + * DDR4/DDR3 Control Word 0 (Global Features Control Word) + * PSU_DDR_PHY_RDIMMCR0_RC0 0x0 - RegVal = ((0x00000000U << DDR_PHY_RDIMMCR1_RC15_SHIFT - | 0x00000000U << DDR_PHY_RDIMMCR1_RC14_SHIFT - | 0x00000000U << DDR_PHY_RDIMMCR1_RC13_SHIFT - | 0x00000000U << DDR_PHY_RDIMMCR1_RC12_SHIFT - | 0x00000000U << DDR_PHY_RDIMMCR1_RC11_SHIFT - | 0x00000002U << DDR_PHY_RDIMMCR1_RC10_SHIFT - | 0x00000000U << DDR_PHY_RDIMMCR1_RC9_SHIFT - | 0x00000000U << DDR_PHY_RDIMMCR1_RC8_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_RDIMMCR1_OFFSET ,0xFFFFFFFFU ,0x00000200U); - /*############################################################################################################################ */ + * RDIMM Control Register 0 + * (OFFSET, MASK, VALUE) (0XFD080150, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDR_PHY_RDIMMCR0_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ - /*Register : MR0 @ 0XFD080180

+ /* + * Register : RDIMMCR1 @ 0XFD080154 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_MR0_RESERVED_31_8 0x8 + * Control Word 15 + * PSU_DDR_PHY_RDIMMCR1_RC15 0x0 - CA Terminating Rank - PSU_DDR_PHY_MR0_CATR 0x0 + * DDR4 Control Word 14 (Parity Control Word) / DDR3 Reserved + * PSU_DDR_PHY_RDIMMCR1_RC14 0x0 - Reserved. These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0. - PSU_DDR_PHY_MR0_RSVD_6_5 0x1 + * DDR4 Control Word 13 (DIMM Configuration Control Word) / DDR3 Reserved + * PSU_DDR_PHY_RDIMMCR1_RC13 0x0 - Built-in Self-Test for RZQ - PSU_DDR_PHY_MR0_RZQI 0x2 + * DDR4 Control Word 12 (Training Control Word) / DDR3 Reserved + * PSU_DDR_PHY_RDIMMCR1_RC12 0x0 - Reserved. These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0. - PSU_DDR_PHY_MR0_RSVD_2_0 0x0 + * DDR4 Control Word 11 (Operating Voltage VDD and VREFCA Source Control Wo + * rd) / DDR3 Control Word 11 (Operation Voltage VDD Control Word) + * PSU_DDR_PHY_RDIMMCR1_RC11 0x0 - LPDDR4 Mode Register 0 - (OFFSET, MASK, VALUE) (0XFD080180, 0xFFFFFFFFU ,0x00000830U) - RegMask = (DDR_PHY_MR0_RESERVED_31_8_MASK | DDR_PHY_MR0_CATR_MASK | DDR_PHY_MR0_RSVD_6_5_MASK | DDR_PHY_MR0_RZQI_MASK | DDR_PHY_MR0_RSVD_2_0_MASK | 0 ); + * DDR4/DDR3 Control Word 10 (RDIMM Operating Speed Control Word) + * PSU_DDR_PHY_RDIMMCR1_RC10 0x2 - RegVal = ((0x00000008U << DDR_PHY_MR0_RESERVED_31_8_SHIFT - | 0x00000000U << DDR_PHY_MR0_CATR_SHIFT - | 0x00000001U << DDR_PHY_MR0_RSVD_6_5_SHIFT - | 0x00000002U << DDR_PHY_MR0_RZQI_SHIFT - | 0x00000000U << DDR_PHY_MR0_RSVD_2_0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_MR0_OFFSET ,0xFFFFFFFFU ,0x00000830U); - /*############################################################################################################################ */ + * DDR4/DDR3 Control Word 9 (Power Saving Settings Control Word) + * PSU_DDR_PHY_RDIMMCR1_RC9 0x0 - /*Register : MR1 @ 0XFD080184

+ * DDR4 Control Word 8 (Input/Output Configuration Control Word) / DDR3 Con + * trol Word 8 (Additional Input Bus Termination Setting Control Word) + * PSU_DDR_PHY_RDIMMCR1_RC8 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_MR1_RESERVED_31_8 0x3 + * RDIMM Control Register 1 + * (OFFSET, MASK, VALUE) (0XFD080154, 0xFFFFFFFFU ,0x00000200U) + */ + PSU_Mask_Write(DDR_PHY_RDIMMCR1_OFFSET, 0xFFFFFFFFU, 0x00000200U); +/*##################################################################### */ - Read Postamble Length - PSU_DDR_PHY_MR1_RDPST 0x0 + /* + * Register : MR0 @ 0XFD080180 - Write-recovery for auto-precharge command - PSU_DDR_PHY_MR1_NWR 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_MR0_RESERVED_31_8 0x6 - Read Preamble Length - PSU_DDR_PHY_MR1_RDPRE 0x0 + * CA Terminating Rank + * PSU_DDR_PHY_MR0_CATR 0x0 - Write Preamble Length - PSU_DDR_PHY_MR1_WRPRE 0x0 + * Reserved. These are JEDEC reserved bits and are recommended by JEDEC to + * be programmed to 0x0. + * PSU_DDR_PHY_MR0_RSVD_6_5 0x1 - Burst Length - PSU_DDR_PHY_MR1_BL 0x1 + * Built-in Self-Test for RZQ + * PSU_DDR_PHY_MR0_RZQI 0x2 - LPDDR4 Mode Register 1 - (OFFSET, MASK, VALUE) (0XFD080184, 0xFFFFFFFFU ,0x00000301U) - RegMask = (DDR_PHY_MR1_RESERVED_31_8_MASK | DDR_PHY_MR1_RDPST_MASK | DDR_PHY_MR1_NWR_MASK | DDR_PHY_MR1_RDPRE_MASK | DDR_PHY_MR1_WRPRE_MASK | DDR_PHY_MR1_BL_MASK | 0 ); + * Reserved. These are JEDEC reserved bits and are recommended by JEDEC to + * be programmed to 0x0. + * PSU_DDR_PHY_MR0_RSVD_2_0 0x0 - RegVal = ((0x00000003U << DDR_PHY_MR1_RESERVED_31_8_SHIFT - | 0x00000000U << DDR_PHY_MR1_RDPST_SHIFT - | 0x00000000U << DDR_PHY_MR1_NWR_SHIFT - | 0x00000000U << DDR_PHY_MR1_RDPRE_SHIFT - | 0x00000000U << DDR_PHY_MR1_WRPRE_SHIFT - | 0x00000001U << DDR_PHY_MR1_BL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_MR1_OFFSET ,0xFFFFFFFFU ,0x00000301U); - /*############################################################################################################################ */ + * LPDDR4 Mode Register 0 + * (OFFSET, MASK, VALUE) (0XFD080180, 0xFFFFFFFFU ,0x00000630U) + */ + PSU_Mask_Write(DDR_PHY_MR0_OFFSET, 0xFFFFFFFFU, 0x00000630U); +/*##################################################################### */ - /*Register : MR2 @ 0XFD080188

+ /* + * Register : MR1 @ 0XFD080184 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_MR2_RESERVED_31_8 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_MR1_RESERVED_31_8 0x3 - Write Leveling - PSU_DDR_PHY_MR2_WRL 0x0 + * Read Postamble Length + * PSU_DDR_PHY_MR1_RDPST 0x0 - Write Latency Set - PSU_DDR_PHY_MR2_WLS 0x0 + * Write-recovery for auto-precharge command + * PSU_DDR_PHY_MR1_NWR 0x0 - Write Latency - PSU_DDR_PHY_MR2_WL 0x4 + * Read Preamble Length + * PSU_DDR_PHY_MR1_RDPRE 0x0 - Read Latency - PSU_DDR_PHY_MR2_RL 0x0 + * Write Preamble Length + * PSU_DDR_PHY_MR1_WRPRE 0x0 - LPDDR4 Mode Register 2 - (OFFSET, MASK, VALUE) (0XFD080188, 0xFFFFFFFFU ,0x00000020U) - RegMask = (DDR_PHY_MR2_RESERVED_31_8_MASK | DDR_PHY_MR2_WRL_MASK | DDR_PHY_MR2_WLS_MASK | DDR_PHY_MR2_WL_MASK | DDR_PHY_MR2_RL_MASK | 0 ); + * Burst Length + * PSU_DDR_PHY_MR1_BL 0x1 - RegVal = ((0x00000000U << DDR_PHY_MR2_RESERVED_31_8_SHIFT - | 0x00000000U << DDR_PHY_MR2_WRL_SHIFT - | 0x00000000U << DDR_PHY_MR2_WLS_SHIFT - | 0x00000004U << DDR_PHY_MR2_WL_SHIFT - | 0x00000000U << DDR_PHY_MR2_RL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_MR2_OFFSET ,0xFFFFFFFFU ,0x00000020U); - /*############################################################################################################################ */ + * LPDDR4 Mode Register 1 + * (OFFSET, MASK, VALUE) (0XFD080184, 0xFFFFFFFFU ,0x00000301U) + */ + PSU_Mask_Write(DDR_PHY_MR1_OFFSET, 0xFFFFFFFFU, 0x00000301U); +/*##################################################################### */ - /*Register : MR3 @ 0XFD08018C

+ /* + * Register : MR2 @ 0XFD080188 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_MR3_RESERVED_31_8 0x2 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_MR2_RESERVED_31_8 0x0 - DBI-Write Enable - PSU_DDR_PHY_MR3_DBIWR 0x0 + * Write Leveling + * PSU_DDR_PHY_MR2_WRL 0x0 - DBI-Read Enable - PSU_DDR_PHY_MR3_DBIRD 0x0 + * Write Latency Set + * PSU_DDR_PHY_MR2_WLS 0x0 - Pull-down Drive Strength - PSU_DDR_PHY_MR3_PDDS 0x0 + * Write Latency + * PSU_DDR_PHY_MR2_WL 0x4 - These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0. - PSU_DDR_PHY_MR3_RSVD 0x0 + * Read Latency + * PSU_DDR_PHY_MR2_RL 0x0 - Write Postamble Length - PSU_DDR_PHY_MR3_WRPST 0x0 + * LPDDR4 Mode Register 2 + * (OFFSET, MASK, VALUE) (0XFD080188, 0xFFFFFFFFU ,0x00000020U) + */ + PSU_Mask_Write(DDR_PHY_MR2_OFFSET, 0xFFFFFFFFU, 0x00000020U); +/*##################################################################### */ - Pull-up Calibration Point - PSU_DDR_PHY_MR3_PUCAL 0x0 + /* + * Register : MR3 @ 0XFD08018C - LPDDR4 Mode Register 3 - (OFFSET, MASK, VALUE) (0XFD08018C, 0xFFFFFFFFU ,0x00000200U) - RegMask = (DDR_PHY_MR3_RESERVED_31_8_MASK | DDR_PHY_MR3_DBIWR_MASK | DDR_PHY_MR3_DBIRD_MASK | DDR_PHY_MR3_PDDS_MASK | DDR_PHY_MR3_RSVD_MASK | DDR_PHY_MR3_WRPST_MASK | DDR_PHY_MR3_PUCAL_MASK | 0 ); + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_MR3_RESERVED_31_8 0x2 - RegVal = ((0x00000002U << DDR_PHY_MR3_RESERVED_31_8_SHIFT - | 0x00000000U << DDR_PHY_MR3_DBIWR_SHIFT - | 0x00000000U << DDR_PHY_MR3_DBIRD_SHIFT - | 0x00000000U << DDR_PHY_MR3_PDDS_SHIFT - | 0x00000000U << DDR_PHY_MR3_RSVD_SHIFT - | 0x00000000U << DDR_PHY_MR3_WRPST_SHIFT - | 0x00000000U << DDR_PHY_MR3_PUCAL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_MR3_OFFSET ,0xFFFFFFFFU ,0x00000200U); - /*############################################################################################################################ */ + * DBI-Write Enable + * PSU_DDR_PHY_MR3_DBIWR 0x0 - /*Register : MR4 @ 0XFD080190

+ * DBI-Read Enable + * PSU_DDR_PHY_MR3_DBIRD 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_MR4_RESERVED_31_16 0x0 + * Pull-down Drive Strength + * PSU_DDR_PHY_MR3_PDDS 0x0 - These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0. - PSU_DDR_PHY_MR4_RSVD_15_13 0x0 + * These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. + * PSU_DDR_PHY_MR3_RSVD 0x0 - Write Preamble - PSU_DDR_PHY_MR4_WRP 0x0 + * Write Postamble Length + * PSU_DDR_PHY_MR3_WRPST 0x0 - Read Preamble - PSU_DDR_PHY_MR4_RDP 0x0 + * Pull-up Calibration Point + * PSU_DDR_PHY_MR3_PUCAL 0x0 - Read Preamble Training Mode - PSU_DDR_PHY_MR4_RPTM 0x0 + * LPDDR4 Mode Register 3 + * (OFFSET, MASK, VALUE) (0XFD08018C, 0xFFFFFFFFU ,0x00000200U) + */ + PSU_Mask_Write(DDR_PHY_MR3_OFFSET, 0xFFFFFFFFU, 0x00000200U); +/*##################################################################### */ - Self Refresh Abort - PSU_DDR_PHY_MR4_SRA 0x0 + /* + * Register : MR4 @ 0XFD080190 - CS to Command Latency Mode - PSU_DDR_PHY_MR4_CS2CMDL 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_MR4_RESERVED_31_16 0x0 - These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0. - PSU_DDR_PHY_MR4_RSVD1 0x0 + * These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. + * PSU_DDR_PHY_MR4_RSVD_15_13 0x0 - Internal VREF Monitor - PSU_DDR_PHY_MR4_IVM 0x0 + * Write Preamble + * PSU_DDR_PHY_MR4_WRP 0x0 - Temperature Controlled Refresh Mode - PSU_DDR_PHY_MR4_TCRM 0x0 + * Read Preamble + * PSU_DDR_PHY_MR4_RDP 0x0 - Temperature Controlled Refresh Range - PSU_DDR_PHY_MR4_TCRR 0x0 + * Read Preamble Training Mode + * PSU_DDR_PHY_MR4_RPTM 0x0 - Maximum Power Down Mode - PSU_DDR_PHY_MR4_MPDM 0x0 + * Self Refresh Abort + * PSU_DDR_PHY_MR4_SRA 0x0 - This is a JEDEC reserved bit and is recommended by JEDEC to be programmed to 0x0. - PSU_DDR_PHY_MR4_RSVD_0 0x0 + * CS to Command Latency Mode + * PSU_DDR_PHY_MR4_CS2CMDL 0x0 - DDR4 Mode Register 4 - (OFFSET, MASK, VALUE) (0XFD080190, 0xFFFFFFFFU ,0x00000000U) - RegMask = (DDR_PHY_MR4_RESERVED_31_16_MASK | DDR_PHY_MR4_RSVD_15_13_MASK | DDR_PHY_MR4_WRP_MASK | DDR_PHY_MR4_RDP_MASK | DDR_PHY_MR4_RPTM_MASK | DDR_PHY_MR4_SRA_MASK | DDR_PHY_MR4_CS2CMDL_MASK | DDR_PHY_MR4_RSVD1_MASK | DDR_PHY_MR4_IVM_MASK | DDR_PHY_MR4_TCRM_MASK | DDR_PHY_MR4_TCRR_MASK | DDR_PHY_MR4_MPDM_MASK | DDR_PHY_MR4_RSVD_0_MASK | 0 ); + * These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. + * PSU_DDR_PHY_MR4_RSVD1 0x0 - RegVal = ((0x00000000U << DDR_PHY_MR4_RESERVED_31_16_SHIFT - | 0x00000000U << DDR_PHY_MR4_RSVD_15_13_SHIFT - | 0x00000000U << DDR_PHY_MR4_WRP_SHIFT - | 0x00000000U << DDR_PHY_MR4_RDP_SHIFT - | 0x00000000U << DDR_PHY_MR4_RPTM_SHIFT - | 0x00000000U << DDR_PHY_MR4_SRA_SHIFT - | 0x00000000U << DDR_PHY_MR4_CS2CMDL_SHIFT - | 0x00000000U << DDR_PHY_MR4_RSVD1_SHIFT - | 0x00000000U << DDR_PHY_MR4_IVM_SHIFT - | 0x00000000U << DDR_PHY_MR4_TCRM_SHIFT - | 0x00000000U << DDR_PHY_MR4_TCRR_SHIFT - | 0x00000000U << DDR_PHY_MR4_MPDM_SHIFT - | 0x00000000U << DDR_PHY_MR4_RSVD_0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_MR4_OFFSET ,0xFFFFFFFFU ,0x00000000U); - /*############################################################################################################################ */ + * Internal VREF Monitor + * PSU_DDR_PHY_MR4_IVM 0x0 - /*Register : MR5 @ 0XFD080194

+ * Temperature Controlled Refresh Mode + * PSU_DDR_PHY_MR4_TCRM 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_MR5_RESERVED_31_16 0x0 + * Temperature Controlled Refresh Range + * PSU_DDR_PHY_MR4_TCRR 0x0 - These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0. - PSU_DDR_PHY_MR5_RSVD 0x0 + * Maximum Power Down Mode + * PSU_DDR_PHY_MR4_MPDM 0x0 - Read DBI - PSU_DDR_PHY_MR5_RDBI 0x0 + * This is a JEDEC reserved bit and is recommended by JEDEC to be programme + * d to 0x0. + * PSU_DDR_PHY_MR4_RSVD_0 0x0 - Write DBI - PSU_DDR_PHY_MR5_WDBI 0x0 + * DDR4 Mode Register 4 + * (OFFSET, MASK, VALUE) (0XFD080190, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDR_PHY_MR4_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ - Data Mask - PSU_DDR_PHY_MR5_DM 0x1 + /* + * Register : MR5 @ 0XFD080194 - CA Parity Persistent Error - PSU_DDR_PHY_MR5_CAPPE 0x1 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_MR5_RESERVED_31_16 0x0 - RTT_PARK - PSU_DDR_PHY_MR5_RTTPARK 0x3 + * These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. + * PSU_DDR_PHY_MR5_RSVD 0x0 - ODT Input Buffer during Power Down mode - PSU_DDR_PHY_MR5_ODTIBPD 0x0 + * Read DBI + * PSU_DDR_PHY_MR5_RDBI 0x0 - C/A Parity Error Status - PSU_DDR_PHY_MR5_CAPES 0x0 + * Write DBI + * PSU_DDR_PHY_MR5_WDBI 0x0 - CRC Error Clear - PSU_DDR_PHY_MR5_CRCEC 0x0 + * Data Mask + * PSU_DDR_PHY_MR5_DM 0x1 - C/A Parity Latency Mode - PSU_DDR_PHY_MR5_CAPM 0x0 + * CA Parity Persistent Error + * PSU_DDR_PHY_MR5_CAPPE 0x1 - DDR4 Mode Register 5 - (OFFSET, MASK, VALUE) (0XFD080194, 0xFFFFFFFFU ,0x000006C0U) - RegMask = (DDR_PHY_MR5_RESERVED_31_16_MASK | DDR_PHY_MR5_RSVD_MASK | DDR_PHY_MR5_RDBI_MASK | DDR_PHY_MR5_WDBI_MASK | DDR_PHY_MR5_DM_MASK | DDR_PHY_MR5_CAPPE_MASK | DDR_PHY_MR5_RTTPARK_MASK | DDR_PHY_MR5_ODTIBPD_MASK | DDR_PHY_MR5_CAPES_MASK | DDR_PHY_MR5_CRCEC_MASK | DDR_PHY_MR5_CAPM_MASK | 0 ); + * RTT_PARK + * PSU_DDR_PHY_MR5_RTTPARK 0x3 - RegVal = ((0x00000000U << DDR_PHY_MR5_RESERVED_31_16_SHIFT - | 0x00000000U << DDR_PHY_MR5_RSVD_SHIFT - | 0x00000000U << DDR_PHY_MR5_RDBI_SHIFT - | 0x00000000U << DDR_PHY_MR5_WDBI_SHIFT - | 0x00000001U << DDR_PHY_MR5_DM_SHIFT - | 0x00000001U << DDR_PHY_MR5_CAPPE_SHIFT - | 0x00000003U << DDR_PHY_MR5_RTTPARK_SHIFT - | 0x00000000U << DDR_PHY_MR5_ODTIBPD_SHIFT - | 0x00000000U << DDR_PHY_MR5_CAPES_SHIFT - | 0x00000000U << DDR_PHY_MR5_CRCEC_SHIFT - | 0x00000000U << DDR_PHY_MR5_CAPM_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_MR5_OFFSET ,0xFFFFFFFFU ,0x000006C0U); - /*############################################################################################################################ */ + * ODT Input Buffer during Power Down mode + * PSU_DDR_PHY_MR5_ODTIBPD 0x0 - /*Register : MR6 @ 0XFD080198

+ * C/A Parity Error Status + * PSU_DDR_PHY_MR5_CAPES 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_MR6_RESERVED_31_16 0x0 + * CRC Error Clear + * PSU_DDR_PHY_MR5_CRCEC 0x0 - These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0. - PSU_DDR_PHY_MR6_RSVD_15_13 0x0 + * C/A Parity Latency Mode + * PSU_DDR_PHY_MR5_CAPM 0x0 - CAS_n to CAS_n command delay for same bank group (tCCD_L) - PSU_DDR_PHY_MR6_TCCDL 0x2 + * DDR4 Mode Register 5 + * (OFFSET, MASK, VALUE) (0XFD080194, 0xFFFFFFFFU ,0x000006C0U) + */ + PSU_Mask_Write(DDR_PHY_MR5_OFFSET, 0xFFFFFFFFU, 0x000006C0U); +/*##################################################################### */ - These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0. - PSU_DDR_PHY_MR6_RSVD_9_8 0x0 + /* + * Register : MR6 @ 0XFD080198 - VrefDQ Training Enable - PSU_DDR_PHY_MR6_VDDQTEN 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_MR6_RESERVED_31_16 0x0 - VrefDQ Training Range - PSU_DDR_PHY_MR6_VDQTRG 0x0 + * These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. + * PSU_DDR_PHY_MR6_RSVD_15_13 0x0 - VrefDQ Training Values - PSU_DDR_PHY_MR6_VDQTVAL 0x19 + * CAS_n to CAS_n command delay for same bank group (tCCD_L) + * PSU_DDR_PHY_MR6_TCCDL 0x2 - DDR4 Mode Register 6 - (OFFSET, MASK, VALUE) (0XFD080198, 0xFFFFFFFFU ,0x00000819U) - RegMask = (DDR_PHY_MR6_RESERVED_31_16_MASK | DDR_PHY_MR6_RSVD_15_13_MASK | DDR_PHY_MR6_TCCDL_MASK | DDR_PHY_MR6_RSVD_9_8_MASK | DDR_PHY_MR6_VDDQTEN_MASK | DDR_PHY_MR6_VDQTRG_MASK | DDR_PHY_MR6_VDQTVAL_MASK | 0 ); + * These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. + * PSU_DDR_PHY_MR6_RSVD_9_8 0x0 - RegVal = ((0x00000000U << DDR_PHY_MR6_RESERVED_31_16_SHIFT - | 0x00000000U << DDR_PHY_MR6_RSVD_15_13_SHIFT - | 0x00000002U << DDR_PHY_MR6_TCCDL_SHIFT - | 0x00000000U << DDR_PHY_MR6_RSVD_9_8_SHIFT - | 0x00000000U << DDR_PHY_MR6_VDDQTEN_SHIFT - | 0x00000000U << DDR_PHY_MR6_VDQTRG_SHIFT - | 0x00000019U << DDR_PHY_MR6_VDQTVAL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_MR6_OFFSET ,0xFFFFFFFFU ,0x00000819U); - /*############################################################################################################################ */ + * VrefDQ Training Enable + * PSU_DDR_PHY_MR6_VDDQTEN 0x0 - /*Register : MR11 @ 0XFD0801AC

+ * VrefDQ Training Range + * PSU_DDR_PHY_MR6_VDQTRG 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_MR11_RESERVED_31_8 0x0 + * VrefDQ Training Values + * PSU_DDR_PHY_MR6_VDQTVAL 0x19 - These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0. - PSU_DDR_PHY_MR11_RSVD 0x0 + * DDR4 Mode Register 6 + * (OFFSET, MASK, VALUE) (0XFD080198, 0xFFFFFFFFU ,0x00000819U) + */ + PSU_Mask_Write(DDR_PHY_MR6_OFFSET, 0xFFFFFFFFU, 0x00000819U); +/*##################################################################### */ - Power Down Control - PSU_DDR_PHY_MR11_PDCTL 0x0 + /* + * Register : MR11 @ 0XFD0801AC - DQ Bus Receiver On-Die-Termination - PSU_DDR_PHY_MR11_DQODT 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_MR11_RESERVED_31_8 0x0 - LPDDR4 Mode Register 11 - (OFFSET, MASK, VALUE) (0XFD0801AC, 0xFFFFFFFFU ,0x00000000U) - RegMask = (DDR_PHY_MR11_RESERVED_31_8_MASK | DDR_PHY_MR11_RSVD_MASK | DDR_PHY_MR11_PDCTL_MASK | DDR_PHY_MR11_DQODT_MASK | 0 ); + * These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. + * PSU_DDR_PHY_MR11_RSVD 0x0 - RegVal = ((0x00000000U << DDR_PHY_MR11_RESERVED_31_8_SHIFT - | 0x00000000U << DDR_PHY_MR11_RSVD_SHIFT - | 0x00000000U << DDR_PHY_MR11_PDCTL_SHIFT - | 0x00000000U << DDR_PHY_MR11_DQODT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_MR11_OFFSET ,0xFFFFFFFFU ,0x00000000U); - /*############################################################################################################################ */ + * Power Down Control + * PSU_DDR_PHY_MR11_PDCTL 0x0 - /*Register : MR12 @ 0XFD0801B0

+ * DQ Bus Receiver On-Die-Termination + * PSU_DDR_PHY_MR11_DQODT 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_MR12_RESERVED_31_8 0x0 + * LPDDR4 Mode Register 11 + * (OFFSET, MASK, VALUE) (0XFD0801AC, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDR_PHY_MR11_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ - These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0. - PSU_DDR_PHY_MR12_RSVD 0x0 + /* + * Register : MR12 @ 0XFD0801B0 - VREF_CA Range Select. - PSU_DDR_PHY_MR12_VR_CA 0x1 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_MR12_RESERVED_31_8 0x0 - Controls the VREF(ca) levels for Frequency-Set-Point[1:0]. - PSU_DDR_PHY_MR12_VREF_CA 0xd + * These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. + * PSU_DDR_PHY_MR12_RSVD 0x0 - LPDDR4 Mode Register 12 - (OFFSET, MASK, VALUE) (0XFD0801B0, 0xFFFFFFFFU ,0x0000004DU) - RegMask = (DDR_PHY_MR12_RESERVED_31_8_MASK | DDR_PHY_MR12_RSVD_MASK | DDR_PHY_MR12_VR_CA_MASK | DDR_PHY_MR12_VREF_CA_MASK | 0 ); + * VREF_CA Range Select. + * PSU_DDR_PHY_MR12_VR_CA 0x1 - RegVal = ((0x00000000U << DDR_PHY_MR12_RESERVED_31_8_SHIFT - | 0x00000000U << DDR_PHY_MR12_RSVD_SHIFT - | 0x00000001U << DDR_PHY_MR12_VR_CA_SHIFT - | 0x0000000DU << DDR_PHY_MR12_VREF_CA_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_MR12_OFFSET ,0xFFFFFFFFU ,0x0000004DU); - /*############################################################################################################################ */ + * Controls the VREF(ca) levels for Frequency-Set-Point[1:0]. + * PSU_DDR_PHY_MR12_VREF_CA 0xd - /*Register : MR13 @ 0XFD0801B4

+ * LPDDR4 Mode Register 12 + * (OFFSET, MASK, VALUE) (0XFD0801B0, 0xFFFFFFFFU ,0x0000004DU) + */ + PSU_Mask_Write(DDR_PHY_MR12_OFFSET, 0xFFFFFFFFU, 0x0000004DU); +/*##################################################################### */ - Reserved. Return zeroes on reads. - PSU_DDR_PHY_MR13_RESERVED_31_8 0x0 + /* + * Register : MR13 @ 0XFD0801B4 - Frequency Set Point Operation Mode - PSU_DDR_PHY_MR13_FSPOP 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_MR13_RESERVED_31_8 0x0 - Frequency Set Point Write Enable - PSU_DDR_PHY_MR13_FSPWR 0x0 + * Frequency Set Point Operation Mode + * PSU_DDR_PHY_MR13_FSPOP 0x0 - Data Mask Enable - PSU_DDR_PHY_MR13_DMD 0x0 + * Frequency Set Point Write Enable + * PSU_DDR_PHY_MR13_FSPWR 0x0 - Refresh Rate Option - PSU_DDR_PHY_MR13_RRO 0x0 + * Data Mask Enable + * PSU_DDR_PHY_MR13_DMD 0x0 - VREF Current Generator - PSU_DDR_PHY_MR13_VRCG 0x1 + * Refresh Rate Option + * PSU_DDR_PHY_MR13_RRO 0x0 - VREF Output - PSU_DDR_PHY_MR13_VRO 0x0 + * VREF Current Generator + * PSU_DDR_PHY_MR13_VRCG 0x1 - Read Preamble Training Mode - PSU_DDR_PHY_MR13_RPT 0x0 + * VREF Output + * PSU_DDR_PHY_MR13_VRO 0x0 - Command Bus Training - PSU_DDR_PHY_MR13_CBT 0x0 + * Read Preamble Training Mode + * PSU_DDR_PHY_MR13_RPT 0x0 - LPDDR4 Mode Register 13 - (OFFSET, MASK, VALUE) (0XFD0801B4, 0xFFFFFFFFU ,0x00000008U) - RegMask = (DDR_PHY_MR13_RESERVED_31_8_MASK | DDR_PHY_MR13_FSPOP_MASK | DDR_PHY_MR13_FSPWR_MASK | DDR_PHY_MR13_DMD_MASK | DDR_PHY_MR13_RRO_MASK | DDR_PHY_MR13_VRCG_MASK | DDR_PHY_MR13_VRO_MASK | DDR_PHY_MR13_RPT_MASK | DDR_PHY_MR13_CBT_MASK | 0 ); + * Command Bus Training + * PSU_DDR_PHY_MR13_CBT 0x0 - RegVal = ((0x00000000U << DDR_PHY_MR13_RESERVED_31_8_SHIFT - | 0x00000000U << DDR_PHY_MR13_FSPOP_SHIFT - | 0x00000000U << DDR_PHY_MR13_FSPWR_SHIFT - | 0x00000000U << DDR_PHY_MR13_DMD_SHIFT - | 0x00000000U << DDR_PHY_MR13_RRO_SHIFT - | 0x00000001U << DDR_PHY_MR13_VRCG_SHIFT - | 0x00000000U << DDR_PHY_MR13_VRO_SHIFT - | 0x00000000U << DDR_PHY_MR13_RPT_SHIFT - | 0x00000000U << DDR_PHY_MR13_CBT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_MR13_OFFSET ,0xFFFFFFFFU ,0x00000008U); - /*############################################################################################################################ */ + * LPDDR4 Mode Register 13 + * (OFFSET, MASK, VALUE) (0XFD0801B4, 0xFFFFFFFFU ,0x00000008U) + */ + PSU_Mask_Write(DDR_PHY_MR13_OFFSET, 0xFFFFFFFFU, 0x00000008U); +/*##################################################################### */ - /*Register : MR14 @ 0XFD0801B8

+ /* + * Register : MR14 @ 0XFD0801B8 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_MR14_RESERVED_31_8 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_MR14_RESERVED_31_8 0x0 - These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0. - PSU_DDR_PHY_MR14_RSVD 0x0 + * These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. + * PSU_DDR_PHY_MR14_RSVD 0x0 - VREFDQ Range Selects. - PSU_DDR_PHY_MR14_VR_DQ 0x1 + * VREFDQ Range Selects. + * PSU_DDR_PHY_MR14_VR_DQ 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_MR14_VREF_DQ 0xd + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_MR14_VREF_DQ 0xd - LPDDR4 Mode Register 14 - (OFFSET, MASK, VALUE) (0XFD0801B8, 0xFFFFFFFFU ,0x0000004DU) - RegMask = (DDR_PHY_MR14_RESERVED_31_8_MASK | DDR_PHY_MR14_RSVD_MASK | DDR_PHY_MR14_VR_DQ_MASK | DDR_PHY_MR14_VREF_DQ_MASK | 0 ); + * LPDDR4 Mode Register 14 + * (OFFSET, MASK, VALUE) (0XFD0801B8, 0xFFFFFFFFU ,0x0000004DU) + */ + PSU_Mask_Write(DDR_PHY_MR14_OFFSET, 0xFFFFFFFFU, 0x0000004DU); +/*##################################################################### */ - RegVal = ((0x00000000U << DDR_PHY_MR14_RESERVED_31_8_SHIFT - | 0x00000000U << DDR_PHY_MR14_RSVD_SHIFT - | 0x00000001U << DDR_PHY_MR14_VR_DQ_SHIFT - | 0x0000000DU << DDR_PHY_MR14_VREF_DQ_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_MR14_OFFSET ,0xFFFFFFFFU ,0x0000004DU); - /*############################################################################################################################ */ + /* + * Register : MR22 @ 0XFD0801D8 - /*Register : MR22 @ 0XFD0801D8

+ * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_MR22_RESERVED_31_8 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_MR22_RESERVED_31_8 0x0 + * These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. + * PSU_DDR_PHY_MR22_RSVD 0x0 - These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0. - PSU_DDR_PHY_MR22_RSVD 0x0 + * CA ODT termination disable. + * PSU_DDR_PHY_MR22_ODTD_CA 0x0 - CA ODT termination disable. - PSU_DDR_PHY_MR22_ODTD_CA 0x0 + * ODT CS override. + * PSU_DDR_PHY_MR22_ODTE_CS 0x0 - ODT CS override. - PSU_DDR_PHY_MR22_ODTE_CS 0x0 + * ODT CK override. + * PSU_DDR_PHY_MR22_ODTE_CK 0x0 - ODT CK override. - PSU_DDR_PHY_MR22_ODTE_CK 0x0 + * Controller ODT value for VOH calibration. + * PSU_DDR_PHY_MR22_CODT 0x0 - Controller ODT value for VOH calibration. - PSU_DDR_PHY_MR22_CODT 0x0 + * LPDDR4 Mode Register 22 + * (OFFSET, MASK, VALUE) (0XFD0801D8, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDR_PHY_MR22_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ - LPDDR4 Mode Register 22 - (OFFSET, MASK, VALUE) (0XFD0801D8, 0xFFFFFFFFU ,0x00000000U) - RegMask = (DDR_PHY_MR22_RESERVED_31_8_MASK | DDR_PHY_MR22_RSVD_MASK | DDR_PHY_MR22_ODTD_CA_MASK | DDR_PHY_MR22_ODTE_CS_MASK | DDR_PHY_MR22_ODTE_CK_MASK | DDR_PHY_MR22_CODT_MASK | 0 ); + /* + * Register : DTCR0 @ 0XFD080200 - RegVal = ((0x00000000U << DDR_PHY_MR22_RESERVED_31_8_SHIFT - | 0x00000000U << DDR_PHY_MR22_RSVD_SHIFT - | 0x00000000U << DDR_PHY_MR22_ODTD_CA_SHIFT - | 0x00000000U << DDR_PHY_MR22_ODTE_CS_SHIFT - | 0x00000000U << DDR_PHY_MR22_ODTE_CK_SHIFT - | 0x00000000U << DDR_PHY_MR22_CODT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_MR22_OFFSET ,0xFFFFFFFFU ,0x00000000U); - /*############################################################################################################################ */ + * Refresh During Training + * PSU_DDR_PHY_DTCR0_RFSHDT 0x8 - /*Register : DTCR0 @ 0XFD080200

+ * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTCR0_RESERVED_27_26 0x0 - Refresh During Training - PSU_DDR_PHY_DTCR0_RFSHDT 0x8 + * Data Training Debug Rank Select + * PSU_DDR_PHY_DTCR0_DTDRS 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTCR0_RESERVED_27_26 0x0 + * Data Training with Early/Extended Gate + * PSU_DDR_PHY_DTCR0_DTEXG 0x0 - Data Training Debug Rank Select - PSU_DDR_PHY_DTCR0_DTDRS 0x0 + * Data Training Extended Write DQS + * PSU_DDR_PHY_DTCR0_DTEXD 0x0 - Data Training with Early/Extended Gate - PSU_DDR_PHY_DTCR0_DTEXG 0x0 + * Data Training Debug Step + * PSU_DDR_PHY_DTCR0_DTDSTP 0x0 - Data Training Extended Write DQS - PSU_DDR_PHY_DTCR0_DTEXD 0x0 + * Data Training Debug Enable + * PSU_DDR_PHY_DTCR0_DTDEN 0x0 - Data Training Debug Step - PSU_DDR_PHY_DTCR0_DTDSTP 0x0 + * Data Training Debug Byte Select + * PSU_DDR_PHY_DTCR0_DTDBS 0x0 - Data Training Debug Enable - PSU_DDR_PHY_DTCR0_DTDEN 0x0 + * Data Training read DBI deskewing configuration + * PSU_DDR_PHY_DTCR0_DTRDBITR 0x2 - Data Training Debug Byte Select - PSU_DDR_PHY_DTCR0_DTDBS 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTCR0_RESERVED_13 0x0 - Data Training read DBI deskewing configuration - PSU_DDR_PHY_DTCR0_DTRDBITR 0x2 + * Data Training Write Bit Deskew Data Mask + * PSU_DDR_PHY_DTCR0_DTWBDDM 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTCR0_RESERVED_13 0x0 + * Refreshes Issued During Entry to Training + * PSU_DDR_PHY_DTCR0_RFSHEN 0x1 - Data Training Write Bit Deskew Data Mask - PSU_DDR_PHY_DTCR0_DTWBDDM 0x1 + * Data Training Compare Data + * PSU_DDR_PHY_DTCR0_DTCMPD 0x1 - Refreshes Issued During Entry to Training - PSU_DDR_PHY_DTCR0_RFSHEN 0x1 + * Data Training Using MPR + * PSU_DDR_PHY_DTCR0_DTMPR 0x1 - Data Training Compare Data - PSU_DDR_PHY_DTCR0_DTCMPD 0x1 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTCR0_RESERVED_5_4 0x0 - Data Training Using MPR - PSU_DDR_PHY_DTCR0_DTMPR 0x1 + * Data Training Repeat Number + * PSU_DDR_PHY_DTCR0_DTRPTN 0x7 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTCR0_RESERVED_5_4 0x0 + * Data Training Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD080200, 0xFFFFFFFFU ,0x800091C7U) + */ + PSU_Mask_Write(DDR_PHY_DTCR0_OFFSET, 0xFFFFFFFFU, 0x800091C7U); +/*##################################################################### */ - Data Training Repeat Number - PSU_DDR_PHY_DTCR0_DTRPTN 0x7 + /* + * Register : DTCR1 @ 0XFD080204 - Data Training Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD080200, 0xFFFFFFFFU ,0x800091C7U) - RegMask = (DDR_PHY_DTCR0_RFSHDT_MASK | DDR_PHY_DTCR0_RESERVED_27_26_MASK | DDR_PHY_DTCR0_DTDRS_MASK | DDR_PHY_DTCR0_DTEXG_MASK | DDR_PHY_DTCR0_DTEXD_MASK | DDR_PHY_DTCR0_DTDSTP_MASK | DDR_PHY_DTCR0_DTDEN_MASK | DDR_PHY_DTCR0_DTDBS_MASK | DDR_PHY_DTCR0_DTRDBITR_MASK | DDR_PHY_DTCR0_RESERVED_13_MASK | DDR_PHY_DTCR0_DTWBDDM_MASK | DDR_PHY_DTCR0_RFSHEN_MASK | DDR_PHY_DTCR0_DTCMPD_MASK | DDR_PHY_DTCR0_DTMPR_MASK | DDR_PHY_DTCR0_RESERVED_5_4_MASK | DDR_PHY_DTCR0_DTRPTN_MASK | 0 ); + * Rank Enable. + * PSU_DDR_PHY_DTCR1_RANKEN_RSVD 0x0 - RegVal = ((0x00000008U << DDR_PHY_DTCR0_RFSHDT_SHIFT - | 0x00000000U << DDR_PHY_DTCR0_RESERVED_27_26_SHIFT - | 0x00000000U << DDR_PHY_DTCR0_DTDRS_SHIFT - | 0x00000000U << DDR_PHY_DTCR0_DTEXG_SHIFT - | 0x00000000U << DDR_PHY_DTCR0_DTEXD_SHIFT - | 0x00000000U << DDR_PHY_DTCR0_DTDSTP_SHIFT - | 0x00000000U << DDR_PHY_DTCR0_DTDEN_SHIFT - | 0x00000000U << DDR_PHY_DTCR0_DTDBS_SHIFT - | 0x00000002U << DDR_PHY_DTCR0_DTRDBITR_SHIFT - | 0x00000000U << DDR_PHY_DTCR0_RESERVED_13_SHIFT - | 0x00000001U << DDR_PHY_DTCR0_DTWBDDM_SHIFT - | 0x00000001U << DDR_PHY_DTCR0_RFSHEN_SHIFT - | 0x00000001U << DDR_PHY_DTCR0_DTCMPD_SHIFT - | 0x00000001U << DDR_PHY_DTCR0_DTMPR_SHIFT - | 0x00000000U << DDR_PHY_DTCR0_RESERVED_5_4_SHIFT - | 0x00000007U << DDR_PHY_DTCR0_DTRPTN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DTCR0_OFFSET ,0xFFFFFFFFU ,0x800091C7U); - /*############################################################################################################################ */ + * Rank Enable. + * PSU_DDR_PHY_DTCR1_RANKEN 0x1 - /*Register : DTCR1 @ 0XFD080204

+ * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTCR1_RESERVED_15_14 0x0 - Rank Enable. - PSU_DDR_PHY_DTCR1_RANKEN_RSVD 0x0 + * Data Training Rank + * PSU_DDR_PHY_DTCR1_DTRANK 0x0 - Rank Enable. - PSU_DDR_PHY_DTCR1_RANKEN 0x1 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTCR1_RESERVED_11 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTCR1_RESERVED_15_14 0x0 + * Read Leveling Gate Sampling Difference + * PSU_DDR_PHY_DTCR1_RDLVLGDIFF 0x2 - Data Training Rank - PSU_DDR_PHY_DTCR1_DTRANK 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTCR1_RESERVED_7 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTCR1_RESERVED_11 0x0 + * Read Leveling Gate Shift + * PSU_DDR_PHY_DTCR1_RDLVLGS 0x3 - Read Leveling Gate Sampling Difference - PSU_DDR_PHY_DTCR1_RDLVLGDIFF 0x2 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTCR1_RESERVED_3 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTCR1_RESERVED_7 0x0 + * Read Preamble Training enable + * PSU_DDR_PHY_DTCR1_RDPRMVL_TRN 0x1 - Read Leveling Gate Shift - PSU_DDR_PHY_DTCR1_RDLVLGS 0x3 + * Read Leveling Enable + * PSU_DDR_PHY_DTCR1_RDLVLEN 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTCR1_RESERVED_3 0x0 + * Basic Gate Training Enable + * PSU_DDR_PHY_DTCR1_BSTEN 0x0 - Read Preamble Training enable - PSU_DDR_PHY_DTCR1_RDPRMVL_TRN 0x1 + * Data Training Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD080204, 0xFFFFFFFFU ,0x00010236U) + */ + PSU_Mask_Write(DDR_PHY_DTCR1_OFFSET, 0xFFFFFFFFU, 0x00010236U); +/*##################################################################### */ - Read Leveling Enable - PSU_DDR_PHY_DTCR1_RDLVLEN 0x1 + /* + * Register : CATR0 @ 0XFD080240 - Basic Gate Training Enable - PSU_DDR_PHY_DTCR1_BSTEN 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_CATR0_RESERVED_31_21 0x0 - Data Training Configuration Register 1 - (OFFSET, MASK, VALUE) (0XFD080204, 0xFFFFFFFFU ,0x00010236U) - RegMask = (DDR_PHY_DTCR1_RANKEN_RSVD_MASK | DDR_PHY_DTCR1_RANKEN_MASK | DDR_PHY_DTCR1_RESERVED_15_14_MASK | DDR_PHY_DTCR1_DTRANK_MASK | DDR_PHY_DTCR1_RESERVED_11_MASK | DDR_PHY_DTCR1_RDLVLGDIFF_MASK | DDR_PHY_DTCR1_RESERVED_7_MASK | DDR_PHY_DTCR1_RDLVLGS_MASK | DDR_PHY_DTCR1_RESERVED_3_MASK | DDR_PHY_DTCR1_RDPRMVL_TRN_MASK | DDR_PHY_DTCR1_RDLVLEN_MASK | DDR_PHY_DTCR1_BSTEN_MASK | 0 ); + * Minimum time (in terms of number of dram clocks) between two consectuve + * CA calibration command + * PSU_DDR_PHY_CATR0_CACD 0x14 - RegVal = ((0x00000000U << DDR_PHY_DTCR1_RANKEN_RSVD_SHIFT - | 0x00000001U << DDR_PHY_DTCR1_RANKEN_SHIFT - | 0x00000000U << DDR_PHY_DTCR1_RESERVED_15_14_SHIFT - | 0x00000000U << DDR_PHY_DTCR1_DTRANK_SHIFT - | 0x00000000U << DDR_PHY_DTCR1_RESERVED_11_SHIFT - | 0x00000002U << DDR_PHY_DTCR1_RDLVLGDIFF_SHIFT - | 0x00000000U << DDR_PHY_DTCR1_RESERVED_7_SHIFT - | 0x00000003U << DDR_PHY_DTCR1_RDLVLGS_SHIFT - | 0x00000000U << DDR_PHY_DTCR1_RESERVED_3_SHIFT - | 0x00000001U << DDR_PHY_DTCR1_RDPRMVL_TRN_SHIFT - | 0x00000001U << DDR_PHY_DTCR1_RDLVLEN_SHIFT - | 0x00000000U << DDR_PHY_DTCR1_BSTEN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DTCR1_OFFSET ,0xFFFFFFFFU ,0x00010236U); - /*############################################################################################################################ */ + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_CATR0_RESERVED_15_13 0x0 - /*Register : CATR0 @ 0XFD080240

+ * Minimum time (in terms of number of dram clocks) PUB should wait before + * sampling the CA response after Calibration command has been sent to the + * memory + * PSU_DDR_PHY_CATR0_CAADR 0x10 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_CATR0_RESERVED_31_21 0x0 + * CA_1 Response Byte Lane 1 + * PSU_DDR_PHY_CATR0_CA1BYTE1 0x5 - Minimum time (in terms of number of dram clocks) between two consectuve CA calibration command - PSU_DDR_PHY_CATR0_CACD 0x14 + * CA_1 Response Byte Lane 0 + * PSU_DDR_PHY_CATR0_CA1BYTE0 0x4 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_CATR0_RESERVED_15_13 0x0 + * CA Training Register 0 + * (OFFSET, MASK, VALUE) (0XFD080240, 0xFFFFFFFFU ,0x00141054U) + */ + PSU_Mask_Write(DDR_PHY_CATR0_OFFSET, 0xFFFFFFFFU, 0x00141054U); +/*##################################################################### */ - Minimum time (in terms of number of dram clocks) PUB should wait before sampling the CA response after Calibration command ha - been sent to the memory - PSU_DDR_PHY_CATR0_CAADR 0x10 + /* + * Register : DQSDR0 @ 0XFD080250 - CA_1 Response Byte Lane 1 - PSU_DDR_PHY_CATR0_CA1BYTE1 0x5 + * Number of delay taps by which the DQS gate LCDL will be updated when DQS + * drift is detected + * PSU_DDR_PHY_DQSDR0_DFTDLY 0x0 - CA_1 Response Byte Lane 0 - PSU_DDR_PHY_CATR0_CA1BYTE0 0x4 - - CA Training Register 0 - (OFFSET, MASK, VALUE) (0XFD080240, 0xFFFFFFFFU ,0x00141054U) - RegMask = (DDR_PHY_CATR0_RESERVED_31_21_MASK | DDR_PHY_CATR0_CACD_MASK | DDR_PHY_CATR0_RESERVED_15_13_MASK | DDR_PHY_CATR0_CAADR_MASK | DDR_PHY_CATR0_CA1BYTE1_MASK | DDR_PHY_CATR0_CA1BYTE0_MASK | 0 ); - - RegVal = ((0x00000000U << DDR_PHY_CATR0_RESERVED_31_21_SHIFT - | 0x00000014U << DDR_PHY_CATR0_CACD_SHIFT - | 0x00000000U << DDR_PHY_CATR0_RESERVED_15_13_SHIFT - | 0x00000010U << DDR_PHY_CATR0_CAADR_SHIFT - | 0x00000005U << DDR_PHY_CATR0_CA1BYTE1_SHIFT - | 0x00000004U << DDR_PHY_CATR0_CA1BYTE0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_CATR0_OFFSET ,0xFFFFFFFFU ,0x00141054U); - /*############################################################################################################################ */ + * Drift Impedance Update + * PSU_DDR_PHY_DQSDR0_DFTZQUP 0x0 - /*Register : BISTLSR @ 0XFD080414

+ * Drift DDL Update + * PSU_DDR_PHY_DQSDR0_DFTDDLUP 0x0 - LFSR seed for pseudo-random BIST patterns - PSU_DDR_PHY_BISTLSR_SEED 0x12341000 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DQSDR0_RESERVED_25_22 0x0 - BIST LFSR Seed Register - (OFFSET, MASK, VALUE) (0XFD080414, 0xFFFFFFFFU ,0x12341000U) - RegMask = (DDR_PHY_BISTLSR_SEED_MASK | 0 ); + * Drift Read Spacing + * PSU_DDR_PHY_DQSDR0_DFTRDSPC 0x0 - RegVal = ((0x12341000U << DDR_PHY_BISTLSR_SEED_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_BISTLSR_OFFSET ,0xFFFFFFFFU ,0x12341000U); - /*############################################################################################################################ */ + * Drift Back-to-Back Reads + * PSU_DDR_PHY_DQSDR0_DFTB2BRD 0x8 - /*Register : RIOCR5 @ 0XFD0804F4

+ * Drift Idle Reads + * PSU_DDR_PHY_DQSDR0_DFTIDLRD 0x8 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_RIOCR5_RESERVED_31_16 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DQSDR0_RESERVED_11_8 0x0 - Reserved. Return zeros on reads. - PSU_DDR_PHY_RIOCR5_ODTOEMODE_RSVD 0x0 + * Gate Pulse Enable + * PSU_DDR_PHY_DQSDR0_DFTGPULSE 0x0 - SDRAM On-die Termination Output Enable (OE) Mode Selection. - PSU_DDR_PHY_RIOCR5_ODTOEMODE 0x5 + * DQS Drift Update Mode + * PSU_DDR_PHY_DQSDR0_DFTUPMODE 0x0 - Rank I/O Configuration Register 5 - (OFFSET, MASK, VALUE) (0XFD0804F4, 0xFFFFFFFFU ,0x00000005U) - RegMask = (DDR_PHY_RIOCR5_RESERVED_31_16_MASK | DDR_PHY_RIOCR5_ODTOEMODE_RSVD_MASK | DDR_PHY_RIOCR5_ODTOEMODE_MASK | 0 ); + * DQS Drift Detection Mode + * PSU_DDR_PHY_DQSDR0_DFTDTMODE 0x0 - RegVal = ((0x00000000U << DDR_PHY_RIOCR5_RESERVED_31_16_SHIFT - | 0x00000000U << DDR_PHY_RIOCR5_ODTOEMODE_RSVD_SHIFT - | 0x00000005U << DDR_PHY_RIOCR5_ODTOEMODE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_RIOCR5_OFFSET ,0xFFFFFFFFU ,0x00000005U); - /*############################################################################################################################ */ + * DQS Drift Detection Enable + * PSU_DDR_PHY_DQSDR0_DFTDTEN 0x0 - /*Register : ACIOCR0 @ 0XFD080500

+ * DQS Drift Register 0 + * (OFFSET, MASK, VALUE) (0XFD080250, 0xFFFFFFFFU ,0x00088000U) + */ + PSU_Mask_Write(DDR_PHY_DQSDR0_OFFSET, 0xFFFFFFFFU, 0x00088000U); +/*##################################################################### */ - Address/Command Slew Rate (D3F I/O Only) - PSU_DDR_PHY_ACIOCR0_ACSR 0x0 + /* + * Register : BISTLSR @ 0XFD080414 - SDRAM Reset I/O Mode - PSU_DDR_PHY_ACIOCR0_RSTIOM 0x1 + * LFSR seed for pseudo-random BIST patterns + * PSU_DDR_PHY_BISTLSR_SEED 0x12341000 - SDRAM Reset Power Down Receiver - PSU_DDR_PHY_ACIOCR0_RSTPDR 0x1 + * BIST LFSR Seed Register + * (OFFSET, MASK, VALUE) (0XFD080414, 0xFFFFFFFFU ,0x12341000U) + */ + PSU_Mask_Write(DDR_PHY_BISTLSR_OFFSET, 0xFFFFFFFFU, 0x12341000U); +/*##################################################################### */ - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACIOCR0_RESERVED_27 0x0 + /* + * Register : RIOCR5 @ 0XFD0804F4 - SDRAM Reset On-Die Termination - PSU_DDR_PHY_ACIOCR0_RSTODT 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_RIOCR5_RESERVED_31_16 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACIOCR0_RESERVED_25_10 0x0 + * Reserved. Return zeros on reads. + * PSU_DDR_PHY_RIOCR5_ODTOEMODE_RSVD 0x0 - CK Duty Cycle Correction - PSU_DDR_PHY_ACIOCR0_CKDCC 0x0 + * SDRAM On-die Termination Output Enable (OE) Mode Selection. + * PSU_DDR_PHY_RIOCR5_ODTOEMODE 0x5 - AC Power Down Receiver Mode - PSU_DDR_PHY_ACIOCR0_ACPDRMODE 0x2 + * Rank I/O Configuration Register 5 + * (OFFSET, MASK, VALUE) (0XFD0804F4, 0xFFFFFFFFU ,0x00000005U) + */ + PSU_Mask_Write(DDR_PHY_RIOCR5_OFFSET, 0xFFFFFFFFU, 0x00000005U); +/*##################################################################### */ - AC On-die Termination Mode - PSU_DDR_PHY_ACIOCR0_ACODTMODE 0x2 + /* + * Register : ACIOCR0 @ 0XFD080500 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACIOCR0_RESERVED_1 0x0 + * Address/Command Slew Rate (D3F I/O Only) + * PSU_DDR_PHY_ACIOCR0_ACSR 0x0 - Control delayed or non-delayed clock to CS_N/ODT?CKE AC slices. - PSU_DDR_PHY_ACIOCR0_ACRANKCLKSEL 0x0 + * SDRAM Reset I/O Mode + * PSU_DDR_PHY_ACIOCR0_RSTIOM 0x1 - AC I/O Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD080500, 0xFFFFFFFFU ,0x30000028U) - RegMask = (DDR_PHY_ACIOCR0_ACSR_MASK | DDR_PHY_ACIOCR0_RSTIOM_MASK | DDR_PHY_ACIOCR0_RSTPDR_MASK | DDR_PHY_ACIOCR0_RESERVED_27_MASK | DDR_PHY_ACIOCR0_RSTODT_MASK | DDR_PHY_ACIOCR0_RESERVED_25_10_MASK | DDR_PHY_ACIOCR0_CKDCC_MASK | DDR_PHY_ACIOCR0_ACPDRMODE_MASK | DDR_PHY_ACIOCR0_ACODTMODE_MASK | DDR_PHY_ACIOCR0_RESERVED_1_MASK | DDR_PHY_ACIOCR0_ACRANKCLKSEL_MASK | 0 ); + * SDRAM Reset Power Down Receiver + * PSU_DDR_PHY_ACIOCR0_RSTPDR 0x1 - RegVal = ((0x00000000U << DDR_PHY_ACIOCR0_ACSR_SHIFT - | 0x00000001U << DDR_PHY_ACIOCR0_RSTIOM_SHIFT - | 0x00000001U << DDR_PHY_ACIOCR0_RSTPDR_SHIFT - | 0x00000000U << DDR_PHY_ACIOCR0_RESERVED_27_SHIFT - | 0x00000000U << DDR_PHY_ACIOCR0_RSTODT_SHIFT - | 0x00000000U << DDR_PHY_ACIOCR0_RESERVED_25_10_SHIFT - | 0x00000000U << DDR_PHY_ACIOCR0_CKDCC_SHIFT - | 0x00000002U << DDR_PHY_ACIOCR0_ACPDRMODE_SHIFT - | 0x00000002U << DDR_PHY_ACIOCR0_ACODTMODE_SHIFT - | 0x00000000U << DDR_PHY_ACIOCR0_RESERVED_1_SHIFT - | 0x00000000U << DDR_PHY_ACIOCR0_ACRANKCLKSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_ACIOCR0_OFFSET ,0xFFFFFFFFU ,0x30000028U); - /*############################################################################################################################ */ + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACIOCR0_RESERVED_27 0x0 - /*Register : ACIOCR2 @ 0XFD080508

+ * SDRAM Reset On-Die Termination + * PSU_DDR_PHY_ACIOCR0_RSTODT 0x0 - Clock gating for glue logic inside CLKGEN and glue logic inside CONTROL slice - PSU_DDR_PHY_ACIOCR2_CLKGENCLKGATE 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACIOCR0_RESERVED_25_10 0x0 - Clock gating for Output Enable D slices [0] - PSU_DDR_PHY_ACIOCR2_ACOECLKGATE0 0x0 + * CK Duty Cycle Correction + * PSU_DDR_PHY_ACIOCR0_CKDCC 0x0 - Clock gating for Power Down Receiver D slices [0] - PSU_DDR_PHY_ACIOCR2_ACPDRCLKGATE0 0x0 + * AC Power Down Receiver Mode + * PSU_DDR_PHY_ACIOCR0_ACPDRMODE 0x2 - Clock gating for Termination Enable D slices [0] - PSU_DDR_PHY_ACIOCR2_ACTECLKGATE0 0x0 + * AC On-die Termination Mode + * PSU_DDR_PHY_ACIOCR0_ACODTMODE 0x2 - Clock gating for CK# D slices [1:0] - PSU_DDR_PHY_ACIOCR2_CKNCLKGATE0 0x2 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACIOCR0_RESERVED_1 0x0 - Clock gating for CK D slices [1:0] - PSU_DDR_PHY_ACIOCR2_CKCLKGATE0 0x2 + * Control delayed or non-delayed clock to CS_N/ODT?CKE AC slices. + * PSU_DDR_PHY_ACIOCR0_ACRANKCLKSEL 0x0 - Clock gating for AC D slices [23:0] - PSU_DDR_PHY_ACIOCR2_ACCLKGATE0 0x0 + * AC I/O Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD080500, 0xFFFFFFFFU ,0x30000028U) + */ + PSU_Mask_Write(DDR_PHY_ACIOCR0_OFFSET, 0xFFFFFFFFU, 0x30000028U); +/*##################################################################### */ - AC I/O Configuration Register 2 - (OFFSET, MASK, VALUE) (0XFD080508, 0xFFFFFFFFU ,0x0A000000U) - RegMask = (DDR_PHY_ACIOCR2_CLKGENCLKGATE_MASK | DDR_PHY_ACIOCR2_ACOECLKGATE0_MASK | DDR_PHY_ACIOCR2_ACPDRCLKGATE0_MASK | DDR_PHY_ACIOCR2_ACTECLKGATE0_MASK | DDR_PHY_ACIOCR2_CKNCLKGATE0_MASK | DDR_PHY_ACIOCR2_CKCLKGATE0_MASK | DDR_PHY_ACIOCR2_ACCLKGATE0_MASK | 0 ); + /* + * Register : ACIOCR2 @ 0XFD080508 - RegVal = ((0x00000000U << DDR_PHY_ACIOCR2_CLKGENCLKGATE_SHIFT - | 0x00000000U << DDR_PHY_ACIOCR2_ACOECLKGATE0_SHIFT - | 0x00000000U << DDR_PHY_ACIOCR2_ACPDRCLKGATE0_SHIFT - | 0x00000000U << DDR_PHY_ACIOCR2_ACTECLKGATE0_SHIFT - | 0x00000002U << DDR_PHY_ACIOCR2_CKNCLKGATE0_SHIFT - | 0x00000002U << DDR_PHY_ACIOCR2_CKCLKGATE0_SHIFT - | 0x00000000U << DDR_PHY_ACIOCR2_ACCLKGATE0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_ACIOCR2_OFFSET ,0xFFFFFFFFU ,0x0A000000U); - /*############################################################################################################################ */ + * Clock gating for glue logic inside CLKGEN and glue logic inside CONTROL + * slice + * PSU_DDR_PHY_ACIOCR2_CLKGENCLKGATE 0x0 - /*Register : ACIOCR3 @ 0XFD08050C

+ * Clock gating for Output Enable D slices [0] + * PSU_DDR_PHY_ACIOCR2_ACOECLKGATE0 0x0 - SDRAM Parity Output Enable (OE) Mode Selection - PSU_DDR_PHY_ACIOCR3_PAROEMODE 0x0 + * Clock gating for Power Down Receiver D slices [0] + * PSU_DDR_PHY_ACIOCR2_ACPDRCLKGATE0 0x0 - SDRAM Bank Group Output Enable (OE) Mode Selection - PSU_DDR_PHY_ACIOCR3_BGOEMODE 0x0 + * Clock gating for Termination Enable D slices [0] + * PSU_DDR_PHY_ACIOCR2_ACTECLKGATE0 0x0 - SDRAM Bank Address Output Enable (OE) Mode Selection - PSU_DDR_PHY_ACIOCR3_BAOEMODE 0x0 + * Clock gating for CK# D slices [1:0] + * PSU_DDR_PHY_ACIOCR2_CKNCLKGATE0 0x2 - SDRAM A[17] Output Enable (OE) Mode Selection - PSU_DDR_PHY_ACIOCR3_A17OEMODE 0x0 + * Clock gating for CK D slices [1:0] + * PSU_DDR_PHY_ACIOCR2_CKCLKGATE0 0x2 - SDRAM A[16] / RAS_n Output Enable (OE) Mode Selection - PSU_DDR_PHY_ACIOCR3_A16OEMODE 0x0 + * Clock gating for AC D slices [23:0] + * PSU_DDR_PHY_ACIOCR2_ACCLKGATE0 0x0 - SDRAM ACT_n Output Enable (OE) Mode Selection (DDR4 only) - PSU_DDR_PHY_ACIOCR3_ACTOEMODE 0x0 + * AC I/O Configuration Register 2 + * (OFFSET, MASK, VALUE) (0XFD080508, 0xFFFFFFFFU ,0x0A000000U) + */ + PSU_Mask_Write(DDR_PHY_ACIOCR2_OFFSET, 0xFFFFFFFFU, 0x0A000000U); +/*##################################################################### */ - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACIOCR3_RESERVED_15_8 0x0 + /* + * Register : ACIOCR3 @ 0XFD08050C - Reserved. Return zeros on reads. - PSU_DDR_PHY_ACIOCR3_CKOEMODE_RSVD 0x0 + * SDRAM Parity Output Enable (OE) Mode Selection + * PSU_DDR_PHY_ACIOCR3_PAROEMODE 0x0 - SDRAM CK Output Enable (OE) Mode Selection. - PSU_DDR_PHY_ACIOCR3_CKOEMODE 0x9 + * SDRAM Bank Group Output Enable (OE) Mode Selection + * PSU_DDR_PHY_ACIOCR3_BGOEMODE 0x0 - AC I/O Configuration Register 3 - (OFFSET, MASK, VALUE) (0XFD08050C, 0xFFFFFFFFU ,0x00000009U) - RegMask = (DDR_PHY_ACIOCR3_PAROEMODE_MASK | DDR_PHY_ACIOCR3_BGOEMODE_MASK | DDR_PHY_ACIOCR3_BAOEMODE_MASK | DDR_PHY_ACIOCR3_A17OEMODE_MASK | DDR_PHY_ACIOCR3_A16OEMODE_MASK | DDR_PHY_ACIOCR3_ACTOEMODE_MASK | DDR_PHY_ACIOCR3_RESERVED_15_8_MASK | DDR_PHY_ACIOCR3_CKOEMODE_RSVD_MASK | DDR_PHY_ACIOCR3_CKOEMODE_MASK | 0 ); + * SDRAM Bank Address Output Enable (OE) Mode Selection + * PSU_DDR_PHY_ACIOCR3_BAOEMODE 0x0 - RegVal = ((0x00000000U << DDR_PHY_ACIOCR3_PAROEMODE_SHIFT - | 0x00000000U << DDR_PHY_ACIOCR3_BGOEMODE_SHIFT - | 0x00000000U << DDR_PHY_ACIOCR3_BAOEMODE_SHIFT - | 0x00000000U << DDR_PHY_ACIOCR3_A17OEMODE_SHIFT - | 0x00000000U << DDR_PHY_ACIOCR3_A16OEMODE_SHIFT - | 0x00000000U << DDR_PHY_ACIOCR3_ACTOEMODE_SHIFT - | 0x00000000U << DDR_PHY_ACIOCR3_RESERVED_15_8_SHIFT - | 0x00000000U << DDR_PHY_ACIOCR3_CKOEMODE_RSVD_SHIFT - | 0x00000009U << DDR_PHY_ACIOCR3_CKOEMODE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_ACIOCR3_OFFSET ,0xFFFFFFFFU ,0x00000009U); - /*############################################################################################################################ */ + * SDRAM A[17] Output Enable (OE) Mode Selection + * PSU_DDR_PHY_ACIOCR3_A17OEMODE 0x0 - /*Register : ACIOCR4 @ 0XFD080510

+ * SDRAM A[16] / RAS_n Output Enable (OE) Mode Selection + * PSU_DDR_PHY_ACIOCR3_A16OEMODE 0x0 - Clock gating for AC LB slices and loopback read valid slices - PSU_DDR_PHY_ACIOCR4_LBCLKGATE 0x0 + * SDRAM ACT_n Output Enable (OE) Mode Selection (DDR4 only) + * PSU_DDR_PHY_ACIOCR3_ACTOEMODE 0x0 - Clock gating for Output Enable D slices [1] - PSU_DDR_PHY_ACIOCR4_ACOECLKGATE1 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACIOCR3_RESERVED_15_8 0x0 - Clock gating for Power Down Receiver D slices [1] - PSU_DDR_PHY_ACIOCR4_ACPDRCLKGATE1 0x0 + * Reserved. Return zeros on reads. + * PSU_DDR_PHY_ACIOCR3_CKOEMODE_RSVD 0x0 - Clock gating for Termination Enable D slices [1] - PSU_DDR_PHY_ACIOCR4_ACTECLKGATE1 0x0 + * SDRAM CK Output Enable (OE) Mode Selection. + * PSU_DDR_PHY_ACIOCR3_CKOEMODE 0x9 - Clock gating for CK# D slices [3:2] - PSU_DDR_PHY_ACIOCR4_CKNCLKGATE1 0x2 + * AC I/O Configuration Register 3 + * (OFFSET, MASK, VALUE) (0XFD08050C, 0xFFFFFFFFU ,0x00000009U) + */ + PSU_Mask_Write(DDR_PHY_ACIOCR3_OFFSET, 0xFFFFFFFFU, 0x00000009U); +/*##################################################################### */ - Clock gating for CK D slices [3:2] - PSU_DDR_PHY_ACIOCR4_CKCLKGATE1 0x2 + /* + * Register : ACIOCR4 @ 0XFD080510 - Clock gating for AC D slices [47:24] - PSU_DDR_PHY_ACIOCR4_ACCLKGATE1 0x0 + * Clock gating for AC LB slices and loopback read valid slices + * PSU_DDR_PHY_ACIOCR4_LBCLKGATE 0x0 - AC I/O Configuration Register 4 - (OFFSET, MASK, VALUE) (0XFD080510, 0xFFFFFFFFU ,0x0A000000U) - RegMask = (DDR_PHY_ACIOCR4_LBCLKGATE_MASK | DDR_PHY_ACIOCR4_ACOECLKGATE1_MASK | DDR_PHY_ACIOCR4_ACPDRCLKGATE1_MASK | DDR_PHY_ACIOCR4_ACTECLKGATE1_MASK | DDR_PHY_ACIOCR4_CKNCLKGATE1_MASK | DDR_PHY_ACIOCR4_CKCLKGATE1_MASK | DDR_PHY_ACIOCR4_ACCLKGATE1_MASK | 0 ); + * Clock gating for Output Enable D slices [1] + * PSU_DDR_PHY_ACIOCR4_ACOECLKGATE1 0x0 - RegVal = ((0x00000000U << DDR_PHY_ACIOCR4_LBCLKGATE_SHIFT - | 0x00000000U << DDR_PHY_ACIOCR4_ACOECLKGATE1_SHIFT - | 0x00000000U << DDR_PHY_ACIOCR4_ACPDRCLKGATE1_SHIFT - | 0x00000000U << DDR_PHY_ACIOCR4_ACTECLKGATE1_SHIFT - | 0x00000002U << DDR_PHY_ACIOCR4_CKNCLKGATE1_SHIFT - | 0x00000002U << DDR_PHY_ACIOCR4_CKCLKGATE1_SHIFT - | 0x00000000U << DDR_PHY_ACIOCR4_ACCLKGATE1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_ACIOCR4_OFFSET ,0xFFFFFFFFU ,0x0A000000U); - /*############################################################################################################################ */ + * Clock gating for Power Down Receiver D slices [1] + * PSU_DDR_PHY_ACIOCR4_ACPDRCLKGATE1 0x0 - /*Register : IOVCR0 @ 0XFD080520

+ * Clock gating for Termination Enable D slices [1] + * PSU_DDR_PHY_ACIOCR4_ACTECLKGATE1 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_IOVCR0_RESERVED_31_29 0x0 + * Clock gating for CK# D slices [3:2] + * PSU_DDR_PHY_ACIOCR4_CKNCLKGATE1 0x2 - Address/command lane VREF Pad Enable - PSU_DDR_PHY_IOVCR0_ACREFPEN 0x0 + * Clock gating for CK D slices [3:2] + * PSU_DDR_PHY_ACIOCR4_CKCLKGATE1 0x2 - Address/command lane Internal VREF Enable - PSU_DDR_PHY_IOVCR0_ACREFEEN 0x0 + * Clock gating for AC D slices [47:24] + * PSU_DDR_PHY_ACIOCR4_ACCLKGATE1 0x0 - Address/command lane Single-End VREF Enable - PSU_DDR_PHY_IOVCR0_ACREFSEN 0x1 + * AC I/O Configuration Register 4 + * (OFFSET, MASK, VALUE) (0XFD080510, 0xFFFFFFFFU ,0x0A000000U) + */ + PSU_Mask_Write(DDR_PHY_ACIOCR4_OFFSET, 0xFFFFFFFFU, 0x0A000000U); +/*##################################################################### */ - Address/command lane Internal VREF Enable - PSU_DDR_PHY_IOVCR0_ACREFIEN 0x1 + /* + * Register : IOVCR0 @ 0XFD080520 - External VREF generato REFSEL range select - PSU_DDR_PHY_IOVCR0_ACREFESELRANGE 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_IOVCR0_RESERVED_31_29 0x0 - Address/command lane External VREF Select - PSU_DDR_PHY_IOVCR0_ACREFESEL 0x0 + * Address/command lane VREF Pad Enable + * PSU_DDR_PHY_IOVCR0_ACREFPEN 0x0 - Single ended VREF generator REFSEL range select - PSU_DDR_PHY_IOVCR0_ACREFSSELRANGE 0x1 + * Address/command lane Internal VREF Enable + * PSU_DDR_PHY_IOVCR0_ACREFEEN 0x0 - Address/command lane Single-End VREF Select - PSU_DDR_PHY_IOVCR0_ACREFSSEL 0x30 + * Address/command lane Single-End VREF Enable + * PSU_DDR_PHY_IOVCR0_ACREFSEN 0x1 - Internal VREF generator REFSEL ragne select - PSU_DDR_PHY_IOVCR0_ACVREFISELRANGE 0x1 + * Address/command lane Internal VREF Enable + * PSU_DDR_PHY_IOVCR0_ACREFIEN 0x1 - REFSEL Control for internal AC IOs - PSU_DDR_PHY_IOVCR0_ACVREFISEL 0x30 + * External VREF generato REFSEL range select + * PSU_DDR_PHY_IOVCR0_ACREFESELRANGE 0x0 - IO VREF Control Register 0 - (OFFSET, MASK, VALUE) (0XFD080520, 0xFFFFFFFFU ,0x0300B0B0U) - RegMask = (DDR_PHY_IOVCR0_RESERVED_31_29_MASK | DDR_PHY_IOVCR0_ACREFPEN_MASK | DDR_PHY_IOVCR0_ACREFEEN_MASK | DDR_PHY_IOVCR0_ACREFSEN_MASK | DDR_PHY_IOVCR0_ACREFIEN_MASK | DDR_PHY_IOVCR0_ACREFESELRANGE_MASK | DDR_PHY_IOVCR0_ACREFESEL_MASK | DDR_PHY_IOVCR0_ACREFSSELRANGE_MASK | DDR_PHY_IOVCR0_ACREFSSEL_MASK | DDR_PHY_IOVCR0_ACVREFISELRANGE_MASK | DDR_PHY_IOVCR0_ACVREFISEL_MASK | 0 ); + * Address/command lane External VREF Select + * PSU_DDR_PHY_IOVCR0_ACREFESEL 0x0 - RegVal = ((0x00000000U << DDR_PHY_IOVCR0_RESERVED_31_29_SHIFT - | 0x00000000U << DDR_PHY_IOVCR0_ACREFPEN_SHIFT - | 0x00000000U << DDR_PHY_IOVCR0_ACREFEEN_SHIFT - | 0x00000001U << DDR_PHY_IOVCR0_ACREFSEN_SHIFT - | 0x00000001U << DDR_PHY_IOVCR0_ACREFIEN_SHIFT - | 0x00000000U << DDR_PHY_IOVCR0_ACREFESELRANGE_SHIFT - | 0x00000000U << DDR_PHY_IOVCR0_ACREFESEL_SHIFT - | 0x00000001U << DDR_PHY_IOVCR0_ACREFSSELRANGE_SHIFT - | 0x00000030U << DDR_PHY_IOVCR0_ACREFSSEL_SHIFT - | 0x00000001U << DDR_PHY_IOVCR0_ACVREFISELRANGE_SHIFT - | 0x00000030U << DDR_PHY_IOVCR0_ACVREFISEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_IOVCR0_OFFSET ,0xFFFFFFFFU ,0x0300B0B0U); - /*############################################################################################################################ */ + * Single ended VREF generator REFSEL range select + * PSU_DDR_PHY_IOVCR0_ACREFSSELRANGE 0x1 - /*Register : VTCR0 @ 0XFD080528

+ * Address/command lane Single-End VREF Select + * PSU_DDR_PHY_IOVCR0_ACREFSSEL 0x30 - Number of ctl_clk required to meet (> 150ns) timing requirements during DRAM DQ VREF training - PSU_DDR_PHY_VTCR0_TVREF 0x7 + * Internal VREF generator REFSEL ragne select + * PSU_DDR_PHY_IOVCR0_ACVREFISELRANGE 0x1 - DRM DQ VREF training Enable - PSU_DDR_PHY_VTCR0_DVEN 0x1 + * REFSEL Control for internal AC IOs + * PSU_DDR_PHY_IOVCR0_ACVREFISEL 0x4e - Per Device Addressability Enable - PSU_DDR_PHY_VTCR0_PDAEN 0x1 + * IO VREF Control Register 0 + * (OFFSET, MASK, VALUE) (0XFD080520, 0xFFFFFFFFU ,0x0300B0CEU) + */ + PSU_Mask_Write(DDR_PHY_IOVCR0_OFFSET, 0xFFFFFFFFU, 0x0300B0CEU); +/*##################################################################### */ - Reserved. Returns zeroes on reads. - PSU_DDR_PHY_VTCR0_RESERVED_26 0x0 + /* + * Register : VTCR0 @ 0XFD080528 - VREF Word Count - PSU_DDR_PHY_VTCR0_VWCR 0x4 + * Number of ctl_clk required to meet (> 150ns) timing requirements during + * DRAM DQ VREF training + * PSU_DDR_PHY_VTCR0_TVREF 0x7 - DRAM DQ VREF step size used during DRAM VREF training - PSU_DDR_PHY_VTCR0_DVSS 0x0 + * DRM DQ VREF training Enable + * PSU_DDR_PHY_VTCR0_DVEN 0x1 - Maximum VREF limit value used during DRAM VREF training - PSU_DDR_PHY_VTCR0_DVMAX 0x32 + * Per Device Addressability Enable + * PSU_DDR_PHY_VTCR0_PDAEN 0x1 - Minimum VREF limit value used during DRAM VREF training - PSU_DDR_PHY_VTCR0_DVMIN 0x0 + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_VTCR0_RESERVED_26 0x0 - Initial DRAM DQ VREF value used during DRAM VREF training - PSU_DDR_PHY_VTCR0_DVINIT 0x19 + * VREF Word Count + * PSU_DDR_PHY_VTCR0_VWCR 0x4 - VREF Training Control Register 0 - (OFFSET, MASK, VALUE) (0XFD080528, 0xFFFFFFFFU ,0xF9032019U) - RegMask = (DDR_PHY_VTCR0_TVREF_MASK | DDR_PHY_VTCR0_DVEN_MASK | DDR_PHY_VTCR0_PDAEN_MASK | DDR_PHY_VTCR0_RESERVED_26_MASK | DDR_PHY_VTCR0_VWCR_MASK | DDR_PHY_VTCR0_DVSS_MASK | DDR_PHY_VTCR0_DVMAX_MASK | DDR_PHY_VTCR0_DVMIN_MASK | DDR_PHY_VTCR0_DVINIT_MASK | 0 ); + * DRAM DQ VREF step size used during DRAM VREF training + * PSU_DDR_PHY_VTCR0_DVSS 0x0 - RegVal = ((0x00000007U << DDR_PHY_VTCR0_TVREF_SHIFT - | 0x00000001U << DDR_PHY_VTCR0_DVEN_SHIFT - | 0x00000001U << DDR_PHY_VTCR0_PDAEN_SHIFT - | 0x00000000U << DDR_PHY_VTCR0_RESERVED_26_SHIFT - | 0x00000004U << DDR_PHY_VTCR0_VWCR_SHIFT - | 0x00000000U << DDR_PHY_VTCR0_DVSS_SHIFT - | 0x00000032U << DDR_PHY_VTCR0_DVMAX_SHIFT - | 0x00000000U << DDR_PHY_VTCR0_DVMIN_SHIFT - | 0x00000019U << DDR_PHY_VTCR0_DVINIT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_VTCR0_OFFSET ,0xFFFFFFFFU ,0xF9032019U); - /*############################################################################################################################ */ + * Maximum VREF limit value used during DRAM VREF training + * PSU_DDR_PHY_VTCR0_DVMAX 0x32 - /*Register : VTCR1 @ 0XFD08052C

+ * Minimum VREF limit value used during DRAM VREF training + * PSU_DDR_PHY_VTCR0_DVMIN 0x0 - Host VREF step size used during VREF training. The register value of N indicates step size of (N+1) - PSU_DDR_PHY_VTCR1_HVSS 0x0 + * Initial DRAM DQ VREF value used during DRAM VREF training + * PSU_DDR_PHY_VTCR0_DVINIT 0x19 - Reserved. Returns zeroes on reads. - PSU_DDR_PHY_VTCR1_RESERVED_27 0x0 + * VREF Training Control Register 0 + * (OFFSET, MASK, VALUE) (0XFD080528, 0xFFFFFFFFU ,0xF9032019U) + */ + PSU_Mask_Write(DDR_PHY_VTCR0_OFFSET, 0xFFFFFFFFU, 0xF9032019U); +/*##################################################################### */ - Maximum VREF limit value used during DRAM VREF training. - PSU_DDR_PHY_VTCR1_HVMAX 0x7f + /* + * Register : VTCR1 @ 0XFD08052C - Reserved. Returns zeroes on reads. - PSU_DDR_PHY_VTCR1_RESERVED_19 0x0 + * Host VREF step size used during VREF training. The register value of N i + * ndicates step size of (N+1) + * PSU_DDR_PHY_VTCR1_HVSS 0x0 - Minimum VREF limit value used during DRAM VREF training. - PSU_DDR_PHY_VTCR1_HVMIN 0x0 + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_VTCR1_RESERVED_27 0x0 - Reserved. Returns zeroes on reads. - PSU_DDR_PHY_VTCR1_RESERVED_11 0x0 + * Maximum VREF limit value used during DRAM VREF training. + * PSU_DDR_PHY_VTCR1_HVMAX 0x7f - Static Host Vref Rank Value - PSU_DDR_PHY_VTCR1_SHRNK 0x0 + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_VTCR1_RESERVED_19 0x0 - Static Host Vref Rank Enable - PSU_DDR_PHY_VTCR1_SHREN 0x1 + * Minimum VREF limit value used during DRAM VREF training. + * PSU_DDR_PHY_VTCR1_HVMIN 0x0 - Number of ctl_clk required to meet (> 200ns) VREF Settling timing requirements during Host IO VREF training - PSU_DDR_PHY_VTCR1_TVREFIO 0x7 + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_VTCR1_RESERVED_11 0x0 - Eye LCDL Offset value for VREF training - PSU_DDR_PHY_VTCR1_EOFF 0x0 + * Static Host Vref Rank Value + * PSU_DDR_PHY_VTCR1_SHRNK 0x0 - Number of LCDL Eye points for which VREF training is repeated - PSU_DDR_PHY_VTCR1_ENUM 0x0 + * Static Host Vref Rank Enable + * PSU_DDR_PHY_VTCR1_SHREN 0x1 - HOST (IO) internal VREF training Enable - PSU_DDR_PHY_VTCR1_HVEN 0x1 + * Number of ctl_clk required to meet (> 200ns) VREF Settling timing requir + * ements during Host IO VREF training + * PSU_DDR_PHY_VTCR1_TVREFIO 0x7 - Host IO Type Control - PSU_DDR_PHY_VTCR1_HVIO 0x1 + * Eye LCDL Offset value for VREF training + * PSU_DDR_PHY_VTCR1_EOFF 0x0 - VREF Training Control Register 1 - (OFFSET, MASK, VALUE) (0XFD08052C, 0xFFFFFFFFU ,0x07F001E3U) - RegMask = (DDR_PHY_VTCR1_HVSS_MASK | DDR_PHY_VTCR1_RESERVED_27_MASK | DDR_PHY_VTCR1_HVMAX_MASK | DDR_PHY_VTCR1_RESERVED_19_MASK | DDR_PHY_VTCR1_HVMIN_MASK | DDR_PHY_VTCR1_RESERVED_11_MASK | DDR_PHY_VTCR1_SHRNK_MASK | DDR_PHY_VTCR1_SHREN_MASK | DDR_PHY_VTCR1_TVREFIO_MASK | DDR_PHY_VTCR1_EOFF_MASK | DDR_PHY_VTCR1_ENUM_MASK | DDR_PHY_VTCR1_HVEN_MASK | DDR_PHY_VTCR1_HVIO_MASK | 0 ); + * Number of LCDL Eye points for which VREF training is repeated + * PSU_DDR_PHY_VTCR1_ENUM 0x0 - RegVal = ((0x00000000U << DDR_PHY_VTCR1_HVSS_SHIFT - | 0x00000000U << DDR_PHY_VTCR1_RESERVED_27_SHIFT - | 0x0000007FU << DDR_PHY_VTCR1_HVMAX_SHIFT - | 0x00000000U << DDR_PHY_VTCR1_RESERVED_19_SHIFT - | 0x00000000U << DDR_PHY_VTCR1_HVMIN_SHIFT - | 0x00000000U << DDR_PHY_VTCR1_RESERVED_11_SHIFT - | 0x00000000U << DDR_PHY_VTCR1_SHRNK_SHIFT - | 0x00000001U << DDR_PHY_VTCR1_SHREN_SHIFT - | 0x00000007U << DDR_PHY_VTCR1_TVREFIO_SHIFT - | 0x00000000U << DDR_PHY_VTCR1_EOFF_SHIFT - | 0x00000000U << DDR_PHY_VTCR1_ENUM_SHIFT - | 0x00000001U << DDR_PHY_VTCR1_HVEN_SHIFT - | 0x00000001U << DDR_PHY_VTCR1_HVIO_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_VTCR1_OFFSET ,0xFFFFFFFFU ,0x07F001E3U); - /*############################################################################################################################ */ + * HOST (IO) internal VREF training Enable + * PSU_DDR_PHY_VTCR1_HVEN 0x1 - /*Register : ACBDLR1 @ 0XFD080544

+ * Host IO Type Control + * PSU_DDR_PHY_VTCR1_HVIO 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR1_RESERVED_31_30 0x0 + * VREF Training Control Register 1 + * (OFFSET, MASK, VALUE) (0XFD08052C, 0xFFFFFFFFU ,0x07F001E3U) + */ + PSU_Mask_Write(DDR_PHY_VTCR1_OFFSET, 0xFFFFFFFFU, 0x07F001E3U); +/*##################################################################### */ - Delay select for the BDL on Parity. - PSU_DDR_PHY_ACBDLR1_PARBD 0x0 + /* + * Register : ACBDLR1 @ 0XFD080544 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR1_RESERVED_23_22 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR1_RESERVED_31_30 0x0 - Delay select for the BDL on Address A[16]. In DDR3 mode this pin is connected to WE. - PSU_DDR_PHY_ACBDLR1_A16BD 0x0 + * Delay select for the BDL on Parity. + * PSU_DDR_PHY_ACBDLR1_PARBD 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR1_RESERVED_15_14 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR1_RESERVED_23_22 0x0 - Delay select for the BDL on Address A[17]. When not in DDR4 modemode this pin is connected to CAS. - PSU_DDR_PHY_ACBDLR1_A17BD 0x0 + * Delay select for the BDL on Address A[16]. In DDR3 mode this pin is conn + * ected to WE. + * PSU_DDR_PHY_ACBDLR1_A16BD 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR1_RESERVED_7_6 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR1_RESERVED_15_14 0x0 - Delay select for the BDL on ACTN. - PSU_DDR_PHY_ACBDLR1_ACTBD 0x0 + * Delay select for the BDL on Address A[17]. When not in DDR4 modemode thi + * s pin is connected to CAS. + * PSU_DDR_PHY_ACBDLR1_A17BD 0x0 - AC Bit Delay Line Register 1 - (OFFSET, MASK, VALUE) (0XFD080544, 0xFFFFFFFFU ,0x00000000U) - RegMask = (DDR_PHY_ACBDLR1_RESERVED_31_30_MASK | DDR_PHY_ACBDLR1_PARBD_MASK | DDR_PHY_ACBDLR1_RESERVED_23_22_MASK | DDR_PHY_ACBDLR1_A16BD_MASK | DDR_PHY_ACBDLR1_RESERVED_15_14_MASK | DDR_PHY_ACBDLR1_A17BD_MASK | DDR_PHY_ACBDLR1_RESERVED_7_6_MASK | DDR_PHY_ACBDLR1_ACTBD_MASK | 0 ); + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR1_RESERVED_7_6 0x0 - RegVal = ((0x00000000U << DDR_PHY_ACBDLR1_RESERVED_31_30_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR1_PARBD_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR1_RESERVED_23_22_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR1_A16BD_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR1_RESERVED_15_14_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR1_A17BD_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR1_RESERVED_7_6_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR1_ACTBD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_ACBDLR1_OFFSET ,0xFFFFFFFFU ,0x00000000U); - /*############################################################################################################################ */ + * Delay select for the BDL on ACTN. + * PSU_DDR_PHY_ACBDLR1_ACTBD 0x0 - /*Register : ACBDLR2 @ 0XFD080548

+ * AC Bit Delay Line Register 1 + * (OFFSET, MASK, VALUE) (0XFD080544, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDR_PHY_ACBDLR1_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR2_RESERVED_31_30 0x0 + /* + * Register : ACBDLR2 @ 0XFD080548 - Delay select for the BDL on BG[1]. - PSU_DDR_PHY_ACBDLR2_BG1BD 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR2_RESERVED_31_30 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR2_RESERVED_23_22 0x0 + * Delay select for the BDL on BG[1]. + * PSU_DDR_PHY_ACBDLR2_BG1BD 0x0 - Delay select for the BDL on BG[0]. - PSU_DDR_PHY_ACBDLR2_BG0BD 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR2_RESERVED_23_22 0x0 - Reser.ved Return zeroes on reads. - PSU_DDR_PHY_ACBDLR2_RESERVED_15_14 0x0 + * Delay select for the BDL on BG[0]. + * PSU_DDR_PHY_ACBDLR2_BG0BD 0x0 - Delay select for the BDL on BA[1]. - PSU_DDR_PHY_ACBDLR2_BA1BD 0x0 + * Reser.ved Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR2_RESERVED_15_14 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR2_RESERVED_7_6 0x0 + * Delay select for the BDL on BA[1]. + * PSU_DDR_PHY_ACBDLR2_BA1BD 0x0 - Delay select for the BDL on BA[0]. - PSU_DDR_PHY_ACBDLR2_BA0BD 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR2_RESERVED_7_6 0x0 - AC Bit Delay Line Register 2 - (OFFSET, MASK, VALUE) (0XFD080548, 0xFFFFFFFFU ,0x00000000U) - RegMask = (DDR_PHY_ACBDLR2_RESERVED_31_30_MASK | DDR_PHY_ACBDLR2_BG1BD_MASK | DDR_PHY_ACBDLR2_RESERVED_23_22_MASK | DDR_PHY_ACBDLR2_BG0BD_MASK | DDR_PHY_ACBDLR2_RESERVED_15_14_MASK | DDR_PHY_ACBDLR2_BA1BD_MASK | DDR_PHY_ACBDLR2_RESERVED_7_6_MASK | DDR_PHY_ACBDLR2_BA0BD_MASK | 0 ); + * Delay select for the BDL on BA[0]. + * PSU_DDR_PHY_ACBDLR2_BA0BD 0x0 - RegVal = ((0x00000000U << DDR_PHY_ACBDLR2_RESERVED_31_30_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR2_BG1BD_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR2_RESERVED_23_22_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR2_BG0BD_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR2_RESERVED_15_14_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR2_BA1BD_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR2_RESERVED_7_6_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR2_BA0BD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_ACBDLR2_OFFSET ,0xFFFFFFFFU ,0x00000000U); - /*############################################################################################################################ */ + * AC Bit Delay Line Register 2 + * (OFFSET, MASK, VALUE) (0XFD080548, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDR_PHY_ACBDLR2_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ - /*Register : ACBDLR6 @ 0XFD080558

+ /* + * Register : ACBDLR6 @ 0XFD080558 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR6_RESERVED_31_30 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR6_RESERVED_31_30 0x0 - Delay select for the BDL on Address A[3]. - PSU_DDR_PHY_ACBDLR6_A03BD 0x0 + * Delay select for the BDL on Address A[3]. + * PSU_DDR_PHY_ACBDLR6_A03BD 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR6_RESERVED_23_22 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR6_RESERVED_23_22 0x0 - Delay select for the BDL on Address A[2]. - PSU_DDR_PHY_ACBDLR6_A02BD 0x0 + * Delay select for the BDL on Address A[2]. + * PSU_DDR_PHY_ACBDLR6_A02BD 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR6_RESERVED_15_14 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR6_RESERVED_15_14 0x0 - Delay select for the BDL on Address A[1]. - PSU_DDR_PHY_ACBDLR6_A01BD 0x0 + * Delay select for the BDL on Address A[1]. + * PSU_DDR_PHY_ACBDLR6_A01BD 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR6_RESERVED_7_6 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR6_RESERVED_7_6 0x0 - Delay select for the BDL on Address A[0]. - PSU_DDR_PHY_ACBDLR6_A00BD 0x0 + * Delay select for the BDL on Address A[0]. + * PSU_DDR_PHY_ACBDLR6_A00BD 0x0 - AC Bit Delay Line Register 6 - (OFFSET, MASK, VALUE) (0XFD080558, 0xFFFFFFFFU ,0x00000000U) - RegMask = (DDR_PHY_ACBDLR6_RESERVED_31_30_MASK | DDR_PHY_ACBDLR6_A03BD_MASK | DDR_PHY_ACBDLR6_RESERVED_23_22_MASK | DDR_PHY_ACBDLR6_A02BD_MASK | DDR_PHY_ACBDLR6_RESERVED_15_14_MASK | DDR_PHY_ACBDLR6_A01BD_MASK | DDR_PHY_ACBDLR6_RESERVED_7_6_MASK | DDR_PHY_ACBDLR6_A00BD_MASK | 0 ); + * AC Bit Delay Line Register 6 + * (OFFSET, MASK, VALUE) (0XFD080558, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDR_PHY_ACBDLR6_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ - RegVal = ((0x00000000U << DDR_PHY_ACBDLR6_RESERVED_31_30_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR6_A03BD_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR6_RESERVED_23_22_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR6_A02BD_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR6_RESERVED_15_14_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR6_A01BD_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR6_RESERVED_7_6_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR6_A00BD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_ACBDLR6_OFFSET ,0xFFFFFFFFU ,0x00000000U); - /*############################################################################################################################ */ + /* + * Register : ACBDLR7 @ 0XFD08055C - /*Register : ACBDLR7 @ 0XFD08055C

+ * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR7_RESERVED_31_30 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR7_RESERVED_31_30 0x0 + * Delay select for the BDL on Address A[7]. + * PSU_DDR_PHY_ACBDLR7_A07BD 0x0 - Delay select for the BDL on Address A[7]. - PSU_DDR_PHY_ACBDLR7_A07BD 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR7_RESERVED_23_22 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR7_RESERVED_23_22 0x0 + * Delay select for the BDL on Address A[6]. + * PSU_DDR_PHY_ACBDLR7_A06BD 0x0 - Delay select for the BDL on Address A[6]. - PSU_DDR_PHY_ACBDLR7_A06BD 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR7_RESERVED_15_14 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR7_RESERVED_15_14 0x0 + * Delay select for the BDL on Address A[5]. + * PSU_DDR_PHY_ACBDLR7_A05BD 0x0 - Delay select for the BDL on Address A[5]. - PSU_DDR_PHY_ACBDLR7_A05BD 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR7_RESERVED_7_6 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR7_RESERVED_7_6 0x0 + * Delay select for the BDL on Address A[4]. + * PSU_DDR_PHY_ACBDLR7_A04BD 0x0 - Delay select for the BDL on Address A[4]. - PSU_DDR_PHY_ACBDLR7_A04BD 0x0 + * AC Bit Delay Line Register 7 + * (OFFSET, MASK, VALUE) (0XFD08055C, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDR_PHY_ACBDLR7_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ - AC Bit Delay Line Register 7 - (OFFSET, MASK, VALUE) (0XFD08055C, 0xFFFFFFFFU ,0x00000000U) - RegMask = (DDR_PHY_ACBDLR7_RESERVED_31_30_MASK | DDR_PHY_ACBDLR7_A07BD_MASK | DDR_PHY_ACBDLR7_RESERVED_23_22_MASK | DDR_PHY_ACBDLR7_A06BD_MASK | DDR_PHY_ACBDLR7_RESERVED_15_14_MASK | DDR_PHY_ACBDLR7_A05BD_MASK | DDR_PHY_ACBDLR7_RESERVED_7_6_MASK | DDR_PHY_ACBDLR7_A04BD_MASK | 0 ); + /* + * Register : ACBDLR8 @ 0XFD080560 - RegVal = ((0x00000000U << DDR_PHY_ACBDLR7_RESERVED_31_30_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR7_A07BD_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR7_RESERVED_23_22_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR7_A06BD_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR7_RESERVED_15_14_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR7_A05BD_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR7_RESERVED_7_6_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR7_A04BD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_ACBDLR7_OFFSET ,0xFFFFFFFFU ,0x00000000U); - /*############################################################################################################################ */ + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR8_RESERVED_31_30 0x0 - /*Register : ACBDLR8 @ 0XFD080560

+ * Delay select for the BDL on Address A[11]. + * PSU_DDR_PHY_ACBDLR8_A11BD 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR8_RESERVED_31_30 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR8_RESERVED_23_22 0x0 - Delay select for the BDL on Address A[11]. - PSU_DDR_PHY_ACBDLR8_A11BD 0x0 + * Delay select for the BDL on Address A[10]. + * PSU_DDR_PHY_ACBDLR8_A10BD 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR8_RESERVED_23_22 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR8_RESERVED_15_14 0x0 - Delay select for the BDL on Address A[10]. - PSU_DDR_PHY_ACBDLR8_A10BD 0x0 + * Delay select for the BDL on Address A[9]. + * PSU_DDR_PHY_ACBDLR8_A09BD 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR8_RESERVED_15_14 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR8_RESERVED_7_6 0x0 - Delay select for the BDL on Address A[9]. - PSU_DDR_PHY_ACBDLR8_A09BD 0x0 + * Delay select for the BDL on Address A[8]. + * PSU_DDR_PHY_ACBDLR8_A08BD 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR8_RESERVED_7_6 0x0 + * AC Bit Delay Line Register 8 + * (OFFSET, MASK, VALUE) (0XFD080560, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDR_PHY_ACBDLR8_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ - Delay select for the BDL on Address A[8]. - PSU_DDR_PHY_ACBDLR8_A08BD 0x0 + /* + * Register : ACBDLR9 @ 0XFD080564 - AC Bit Delay Line Register 8 - (OFFSET, MASK, VALUE) (0XFD080560, 0xFFFFFFFFU ,0x00000000U) - RegMask = (DDR_PHY_ACBDLR8_RESERVED_31_30_MASK | DDR_PHY_ACBDLR8_A11BD_MASK | DDR_PHY_ACBDLR8_RESERVED_23_22_MASK | DDR_PHY_ACBDLR8_A10BD_MASK | DDR_PHY_ACBDLR8_RESERVED_15_14_MASK | DDR_PHY_ACBDLR8_A09BD_MASK | DDR_PHY_ACBDLR8_RESERVED_7_6_MASK | DDR_PHY_ACBDLR8_A08BD_MASK | 0 ); + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR9_RESERVED_31_30 0x0 - RegVal = ((0x00000000U << DDR_PHY_ACBDLR8_RESERVED_31_30_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR8_A11BD_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR8_RESERVED_23_22_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR8_A10BD_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR8_RESERVED_15_14_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR8_A09BD_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR8_RESERVED_7_6_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR8_A08BD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_ACBDLR8_OFFSET ,0xFFFFFFFFU ,0x00000000U); - /*############################################################################################################################ */ + * Delay select for the BDL on Address A[15]. + * PSU_DDR_PHY_ACBDLR9_A15BD 0x0 - /*Register : ACBDLR9 @ 0XFD080564

+ * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR9_RESERVED_23_22 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR9_RESERVED_31_30 0x0 + * Delay select for the BDL on Address A[14]. + * PSU_DDR_PHY_ACBDLR9_A14BD 0x0 - Delay select for the BDL on Address A[15]. - PSU_DDR_PHY_ACBDLR9_A15BD 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR9_RESERVED_15_14 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR9_RESERVED_23_22 0x0 + * Delay select for the BDL on Address A[13]. + * PSU_DDR_PHY_ACBDLR9_A13BD 0x0 - Delay select for the BDL on Address A[14]. - PSU_DDR_PHY_ACBDLR9_A14BD 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR9_RESERVED_7_6 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR9_RESERVED_15_14 0x0 + * Delay select for the BDL on Address A[12]. + * PSU_DDR_PHY_ACBDLR9_A12BD 0x0 - Delay select for the BDL on Address A[13]. - PSU_DDR_PHY_ACBDLR9_A13BD 0x0 + * AC Bit Delay Line Register 9 + * (OFFSET, MASK, VALUE) (0XFD080564, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDR_PHY_ACBDLR9_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR9_RESERVED_7_6 0x0 + /* + * Register : ZQCR @ 0XFD080680 - Delay select for the BDL on Address A[12]. - PSU_DDR_PHY_ACBDLR9_A12BD 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ZQCR_RESERVED_31_26 0x0 - AC Bit Delay Line Register 9 - (OFFSET, MASK, VALUE) (0XFD080564, 0xFFFFFFFFU ,0x00000000U) - RegMask = (DDR_PHY_ACBDLR9_RESERVED_31_30_MASK | DDR_PHY_ACBDLR9_A15BD_MASK | DDR_PHY_ACBDLR9_RESERVED_23_22_MASK | DDR_PHY_ACBDLR9_A14BD_MASK | DDR_PHY_ACBDLR9_RESERVED_15_14_MASK | DDR_PHY_ACBDLR9_A13BD_MASK | DDR_PHY_ACBDLR9_RESERVED_7_6_MASK | DDR_PHY_ACBDLR9_A12BD_MASK | 0 ); + * ZQ VREF Range + * PSU_DDR_PHY_ZQCR_ZQREFISELRANGE 0x0 - RegVal = ((0x00000000U << DDR_PHY_ACBDLR9_RESERVED_31_30_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR9_A15BD_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR9_RESERVED_23_22_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR9_A14BD_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR9_RESERVED_15_14_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR9_A13BD_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR9_RESERVED_7_6_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR9_A12BD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_ACBDLR9_OFFSET ,0xFFFFFFFFU ,0x00000000U); - /*############################################################################################################################ */ + * Programmable Wait for Frequency B + * PSU_DDR_PHY_ZQCR_PGWAIT_FRQB 0x11 - /*Register : ZQCR @ 0XFD080680

+ * Programmable Wait for Frequency A + * PSU_DDR_PHY_ZQCR_PGWAIT_FRQA 0x15 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ZQCR_RESERVED_31_26 0x0 + * ZQ VREF Pad Enable + * PSU_DDR_PHY_ZQCR_ZQREFPEN 0x0 - ZQ VREF Range - PSU_DDR_PHY_ZQCR_ZQREFISELRANGE 0x0 + * ZQ Internal VREF Enable + * PSU_DDR_PHY_ZQCR_ZQREFIEN 0x1 - Programmable Wait for Frequency B - PSU_DDR_PHY_ZQCR_PGWAIT_FRQB 0x11 + * Choice of termination mode + * PSU_DDR_PHY_ZQCR_ODT_MODE 0x1 - Programmable Wait for Frequency A - PSU_DDR_PHY_ZQCR_PGWAIT_FRQA 0x11 + * Force ZCAL VT update + * PSU_DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE 0x0 - ZQ VREF Pad Enable - PSU_DDR_PHY_ZQCR_ZQREFPEN 0x0 + * IO VT Drift Limit + * PSU_DDR_PHY_ZQCR_IODLMT 0x2 - ZQ Internal VREF Enable - PSU_DDR_PHY_ZQCR_ZQREFIEN 0x1 + * Averaging algorithm enable, if set, enables averaging algorithm + * PSU_DDR_PHY_ZQCR_AVGEN 0x1 - Choice of termination mode - PSU_DDR_PHY_ZQCR_ODT_MODE 0x1 + * Maximum number of averaging rounds to be used by averaging algorithm + * PSU_DDR_PHY_ZQCR_AVGMAX 0x2 - Force ZCAL VT update - PSU_DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE 0x0 + * ZQ Calibration Type + * PSU_DDR_PHY_ZQCR_ZCALT 0x0 - IO VT Drift Limit - PSU_DDR_PHY_ZQCR_IODLMT 0x2 + * ZQ Power Down + * PSU_DDR_PHY_ZQCR_ZQPD 0x0 - Averaging algorithm enable, if set, enables averaging algorithm - PSU_DDR_PHY_ZQCR_AVGEN 0x1 + * ZQ Impedance Control Register + * (OFFSET, MASK, VALUE) (0XFD080680, 0xFFFFFFFFU ,0x008AAA58U) + */ + PSU_Mask_Write(DDR_PHY_ZQCR_OFFSET, 0xFFFFFFFFU, 0x008AAA58U); +/*##################################################################### */ - Maximum number of averaging rounds to be used by averaging algorithm - PSU_DDR_PHY_ZQCR_AVGMAX 0x2 + /* + * Register : ZQ0PR0 @ 0XFD080684 - ZQ Calibration Type - PSU_DDR_PHY_ZQCR_ZCALT 0x0 + * Pull-down drive strength ZCTRL over-ride enable + * PSU_DDR_PHY_ZQ0PR0_PD_DRV_ZDEN 0x0 - ZQ Power Down - PSU_DDR_PHY_ZQCR_ZQPD 0x0 + * Pull-up drive strength ZCTRL over-ride enable + * PSU_DDR_PHY_ZQ0PR0_PU_DRV_ZDEN 0x0 - ZQ Impedance Control Register - (OFFSET, MASK, VALUE) (0XFD080680, 0xFFFFFFFFU ,0x008A2A58U) - RegMask = (DDR_PHY_ZQCR_RESERVED_31_26_MASK | DDR_PHY_ZQCR_ZQREFISELRANGE_MASK | DDR_PHY_ZQCR_PGWAIT_FRQB_MASK | DDR_PHY_ZQCR_PGWAIT_FRQA_MASK | DDR_PHY_ZQCR_ZQREFPEN_MASK | DDR_PHY_ZQCR_ZQREFIEN_MASK | DDR_PHY_ZQCR_ODT_MODE_MASK | DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_MASK | DDR_PHY_ZQCR_IODLMT_MASK | DDR_PHY_ZQCR_AVGEN_MASK | DDR_PHY_ZQCR_AVGMAX_MASK | DDR_PHY_ZQCR_ZCALT_MASK | DDR_PHY_ZQCR_ZQPD_MASK | 0 ); + * Pull-down termination ZCTRL over-ride enable + * PSU_DDR_PHY_ZQ0PR0_PD_ODT_ZDEN 0x0 - RegVal = ((0x00000000U << DDR_PHY_ZQCR_RESERVED_31_26_SHIFT - | 0x00000000U << DDR_PHY_ZQCR_ZQREFISELRANGE_SHIFT - | 0x00000011U << DDR_PHY_ZQCR_PGWAIT_FRQB_SHIFT - | 0x00000011U << DDR_PHY_ZQCR_PGWAIT_FRQA_SHIFT - | 0x00000000U << DDR_PHY_ZQCR_ZQREFPEN_SHIFT - | 0x00000001U << DDR_PHY_ZQCR_ZQREFIEN_SHIFT - | 0x00000001U << DDR_PHY_ZQCR_ODT_MODE_SHIFT - | 0x00000000U << DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_SHIFT - | 0x00000002U << DDR_PHY_ZQCR_IODLMT_SHIFT - | 0x00000001U << DDR_PHY_ZQCR_AVGEN_SHIFT - | 0x00000002U << DDR_PHY_ZQCR_AVGMAX_SHIFT - | 0x00000000U << DDR_PHY_ZQCR_ZCALT_SHIFT - | 0x00000000U << DDR_PHY_ZQCR_ZQPD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_ZQCR_OFFSET ,0xFFFFFFFFU ,0x008A2A58U); - /*############################################################################################################################ */ + * Pull-up termination ZCTRL over-ride enable + * PSU_DDR_PHY_ZQ0PR0_PU_ODT_ZDEN 0x0 - /*Register : ZQ0PR0 @ 0XFD080684

+ * Calibration segment bypass + * PSU_DDR_PHY_ZQ0PR0_ZSEGBYP 0x0 - Pull-down drive strength ZCTRL over-ride enable - PSU_DDR_PHY_ZQ0PR0_PD_DRV_ZDEN 0x0 + * VREF latch mode controls the mode in which the ZLE pin of the PVREF cell + * is driven by the PUB + * PSU_DDR_PHY_ZQ0PR0_ZLE_MODE 0x0 - Pull-up drive strength ZCTRL over-ride enable - PSU_DDR_PHY_ZQ0PR0_PU_DRV_ZDEN 0x0 + * Termination adjustment + * PSU_DDR_PHY_ZQ0PR0_ODT_ADJUST 0x0 - Pull-down termination ZCTRL over-ride enable - PSU_DDR_PHY_ZQ0PR0_PD_ODT_ZDEN 0x0 + * Pulldown drive strength adjustment + * PSU_DDR_PHY_ZQ0PR0_PD_DRV_ADJUST 0x0 - Pull-up termination ZCTRL over-ride enable - PSU_DDR_PHY_ZQ0PR0_PU_ODT_ZDEN 0x0 + * Pullup drive strength adjustment + * PSU_DDR_PHY_ZQ0PR0_PU_DRV_ADJUST 0x0 - Calibration segment bypass - PSU_DDR_PHY_ZQ0PR0_ZSEGBYP 0x0 + * DRAM Impedance Divide Ratio + * PSU_DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT 0x7 - VREF latch mode controls the mode in which the ZLE pin of the PVREF cell is driven by the PUB - PSU_DDR_PHY_ZQ0PR0_ZLE_MODE 0x0 + * HOST Impedance Divide Ratio + * PSU_DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT 0x9 - Termination adjustment - PSU_DDR_PHY_ZQ0PR0_ODT_ADJUST 0x0 + * Impedance Divide Ratio (pulldown drive calibration during asymmetric dri + * ve strength calibration) + * PSU_DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD 0xd - Pulldown drive strength adjustment - PSU_DDR_PHY_ZQ0PR0_PD_DRV_ADJUST 0x0 + * Impedance Divide Ratio (pullup drive calibration during asymmetric drive + * strength calibration) + * PSU_DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU 0xd - Pullup drive strength adjustment - PSU_DDR_PHY_ZQ0PR0_PU_DRV_ADJUST 0x0 + * ZQ n Impedance Control Program Register 0 + * (OFFSET, MASK, VALUE) (0XFD080684, 0xFFFFFFFFU ,0x000079DDU) + */ + PSU_Mask_Write(DDR_PHY_ZQ0PR0_OFFSET, 0xFFFFFFFFU, 0x000079DDU); +/*##################################################################### */ - DRAM Impedance Divide Ratio - PSU_DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT 0x7 + /* + * Register : ZQ0OR0 @ 0XFD080694 - HOST Impedance Divide Ratio - PSU_DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT 0x7 + * Reserved. Return zeros on reads. + * PSU_DDR_PHY_ZQ0OR0_RESERVED_31_26 0x0 - Impedance Divide Ratio (pulldown drive calibration during asymmetric drive strength calibration) - PSU_DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD 0xd + * Override value for the pull-up output impedance + * PSU_DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD 0x1e1 - Impedance Divide Ratio (pullup drive calibration during asymmetric drive strength calibration) - PSU_DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU 0xd + * Reserved. Return zeros on reads. + * PSU_DDR_PHY_ZQ0OR0_RESERVED_15_10 0x0 - ZQ n Impedance Control Program Register 0 - (OFFSET, MASK, VALUE) (0XFD080684, 0xFFFFFFFFU ,0x000077DDU) - RegMask = (DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_MASK | DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_MASK | DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_MASK | DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_MASK | DDR_PHY_ZQ0PR0_ZSEGBYP_MASK | DDR_PHY_ZQ0PR0_ZLE_MODE_MASK | DDR_PHY_ZQ0PR0_ODT_ADJUST_MASK | DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_MASK | DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_MASK | DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_MASK | DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_MASK | DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_MASK | DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_MASK | 0 ); + * Override value for the pull-down output impedance + * PSU_DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD 0x210 - RegVal = ((0x00000000U << DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_SHIFT - | 0x00000000U << DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_SHIFT - | 0x00000000U << DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_SHIFT - | 0x00000000U << DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_SHIFT - | 0x00000000U << DDR_PHY_ZQ0PR0_ZSEGBYP_SHIFT - | 0x00000000U << DDR_PHY_ZQ0PR0_ZLE_MODE_SHIFT - | 0x00000000U << DDR_PHY_ZQ0PR0_ODT_ADJUST_SHIFT - | 0x00000000U << DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_SHIFT - | 0x00000000U << DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_SHIFT - | 0x00000007U << DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_SHIFT - | 0x00000007U << DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_SHIFT - | 0x0000000DU << DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_SHIFT - | 0x0000000DU << DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_ZQ0PR0_OFFSET ,0xFFFFFFFFU ,0x000077DDU); - /*############################################################################################################################ */ + * ZQ n Impedance Control Override Data Register 0 + * (OFFSET, MASK, VALUE) (0XFD080694, 0xFFFFFFFFU ,0x01E10210U) + */ + PSU_Mask_Write(DDR_PHY_ZQ0OR0_OFFSET, 0xFFFFFFFFU, 0x01E10210U); +/*##################################################################### */ - /*Register : ZQ0OR0 @ 0XFD080694

+ /* + * Register : ZQ0OR1 @ 0XFD080698 - Reserved. Return zeros on reads. - PSU_DDR_PHY_ZQ0OR0_RESERVED_31_26 0x0 + * Reserved. Return zeros on reads. + * PSU_DDR_PHY_ZQ0OR1_RESERVED_31_26 0x0 - Override value for the pull-up output impedance - PSU_DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD 0x1e1 + * Override value for the pull-up termination + * PSU_DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD 0x1e1 - Reserved. Return zeros on reads. - PSU_DDR_PHY_ZQ0OR0_RESERVED_15_10 0x0 + * Reserved. Return zeros on reads. + * PSU_DDR_PHY_ZQ0OR1_RESERVED_15_10 0x0 - Override value for the pull-down output impedance - PSU_DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD 0x210 + * Override value for the pull-down termination + * PSU_DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD 0x0 - ZQ n Impedance Control Override Data Register 0 - (OFFSET, MASK, VALUE) (0XFD080694, 0xFFFFFFFFU ,0x01E10210U) - RegMask = (DDR_PHY_ZQ0OR0_RESERVED_31_26_MASK | DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_MASK | DDR_PHY_ZQ0OR0_RESERVED_15_10_MASK | DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_MASK | 0 ); - - RegVal = ((0x00000000U << DDR_PHY_ZQ0OR0_RESERVED_31_26_SHIFT - | 0x000001E1U << DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_SHIFT - | 0x00000000U << DDR_PHY_ZQ0OR0_RESERVED_15_10_SHIFT - | 0x00000210U << DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_ZQ0OR0_OFFSET ,0xFFFFFFFFU ,0x01E10210U); - /*############################################################################################################################ */ + * ZQ n Impedance Control Override Data Register 1 + * (OFFSET, MASK, VALUE) (0XFD080698, 0xFFFFFFFFU ,0x01E10000U) + */ + PSU_Mask_Write(DDR_PHY_ZQ0OR1_OFFSET, 0xFFFFFFFFU, 0x01E10000U); +/*##################################################################### */ - /*Register : ZQ0OR1 @ 0XFD080698

+ /* + * Register : ZQ1PR0 @ 0XFD0806A4 - Reserved. Return zeros on reads. - PSU_DDR_PHY_ZQ0OR1_RESERVED_31_26 0x0 + * Pull-down drive strength ZCTRL over-ride enable + * PSU_DDR_PHY_ZQ1PR0_PD_DRV_ZDEN 0x0 - Override value for the pull-up termination - PSU_DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD 0x1e1 + * Pull-up drive strength ZCTRL over-ride enable + * PSU_DDR_PHY_ZQ1PR0_PU_DRV_ZDEN 0x0 - Reserved. Return zeros on reads. - PSU_DDR_PHY_ZQ0OR1_RESERVED_15_10 0x0 + * Pull-down termination ZCTRL over-ride enable + * PSU_DDR_PHY_ZQ1PR0_PD_ODT_ZDEN 0x0 - Override value for the pull-down termination - PSU_DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD 0x0 + * Pull-up termination ZCTRL over-ride enable + * PSU_DDR_PHY_ZQ1PR0_PU_ODT_ZDEN 0x0 - ZQ n Impedance Control Override Data Register 1 - (OFFSET, MASK, VALUE) (0XFD080698, 0xFFFFFFFFU ,0x01E10000U) - RegMask = (DDR_PHY_ZQ0OR1_RESERVED_31_26_MASK | DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_MASK | DDR_PHY_ZQ0OR1_RESERVED_15_10_MASK | DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_MASK | 0 ); + * Calibration segment bypass + * PSU_DDR_PHY_ZQ1PR0_ZSEGBYP 0x0 - RegVal = ((0x00000000U << DDR_PHY_ZQ0OR1_RESERVED_31_26_SHIFT - | 0x000001E1U << DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_SHIFT - | 0x00000000U << DDR_PHY_ZQ0OR1_RESERVED_15_10_SHIFT - | 0x00000000U << DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_ZQ0OR1_OFFSET ,0xFFFFFFFFU ,0x01E10000U); - /*############################################################################################################################ */ + * VREF latch mode controls the mode in which the ZLE pin of the PVREF cell + * is driven by the PUB + * PSU_DDR_PHY_ZQ1PR0_ZLE_MODE 0x0 - /*Register : ZQ1PR0 @ 0XFD0806A4

+ * Termination adjustment + * PSU_DDR_PHY_ZQ1PR0_ODT_ADJUST 0x0 - Pull-down drive strength ZCTRL over-ride enable - PSU_DDR_PHY_ZQ1PR0_PD_DRV_ZDEN 0x0 + * Pulldown drive strength adjustment + * PSU_DDR_PHY_ZQ1PR0_PD_DRV_ADJUST 0x1 - Pull-up drive strength ZCTRL over-ride enable - PSU_DDR_PHY_ZQ1PR0_PU_DRV_ZDEN 0x0 + * Pullup drive strength adjustment + * PSU_DDR_PHY_ZQ1PR0_PU_DRV_ADJUST 0x0 - Pull-down termination ZCTRL over-ride enable - PSU_DDR_PHY_ZQ1PR0_PD_ODT_ZDEN 0x0 + * DRAM Impedance Divide Ratio + * PSU_DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT 0x7 - Pull-up termination ZCTRL over-ride enable - PSU_DDR_PHY_ZQ1PR0_PU_ODT_ZDEN 0x0 + * HOST Impedance Divide Ratio + * PSU_DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT 0xb - Calibration segment bypass - PSU_DDR_PHY_ZQ1PR0_ZSEGBYP 0x0 + * Impedance Divide Ratio (pulldown drive calibration during asymmetric dri + * ve strength calibration) + * PSU_DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD 0xd - VREF latch mode controls the mode in which the ZLE pin of the PVREF cell is driven by the PUB - PSU_DDR_PHY_ZQ1PR0_ZLE_MODE 0x0 + * Impedance Divide Ratio (pullup drive calibration during asymmetric drive + * strength calibration) + * PSU_DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU 0xb - Termination adjustment - PSU_DDR_PHY_ZQ1PR0_ODT_ADJUST 0x0 + * ZQ n Impedance Control Program Register 0 + * (OFFSET, MASK, VALUE) (0XFD0806A4, 0xFFFFFFFFU ,0x00087BDBU) + */ + PSU_Mask_Write(DDR_PHY_ZQ1PR0_OFFSET, 0xFFFFFFFFU, 0x00087BDBU); +/*##################################################################### */ - Pulldown drive strength adjustment - PSU_DDR_PHY_ZQ1PR0_PD_DRV_ADJUST 0x1 + /* + * Register : DX0GCR0 @ 0XFD080700 - Pullup drive strength adjustment - PSU_DDR_PHY_ZQ1PR0_PU_DRV_ADJUST 0x0 + * Calibration Bypass + * PSU_DDR_PHY_DX0GCR0_CALBYP 0x0 - DRAM Impedance Divide Ratio - PSU_DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT 0x7 + * Master Delay Line Enable + * PSU_DDR_PHY_DX0GCR0_MDLEN 0x1 - HOST Impedance Divide Ratio - PSU_DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT 0xb + * Configurable ODT(TE) Phase Shift + * PSU_DDR_PHY_DX0GCR0_CODTSHFT 0x0 - Impedance Divide Ratio (pulldown drive calibration during asymmetric drive strength calibration) - PSU_DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD 0xd + * DQS Duty Cycle Correction + * PSU_DDR_PHY_DX0GCR0_DQSDCC 0x0 - Impedance Divide Ratio (pullup drive calibration during asymmetric drive strength calibration) - PSU_DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU 0xb + * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY + * PSU_DDR_PHY_DX0GCR0_RDDLY 0x8 - ZQ n Impedance Control Program Register 0 - (OFFSET, MASK, VALUE) (0XFD0806A4, 0xFFFFFFFFU ,0x00087BDBU) - RegMask = (DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_MASK | DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_MASK | DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_MASK | DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_MASK | DDR_PHY_ZQ1PR0_ZSEGBYP_MASK | DDR_PHY_ZQ1PR0_ZLE_MODE_MASK | DDR_PHY_ZQ1PR0_ODT_ADJUST_MASK | DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_MASK | DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_MASK | DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_MASK | DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_MASK | DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_MASK | DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_MASK | 0 ); + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX0GCR0_RESERVED_19_14 0x0 - RegVal = ((0x00000000U << DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_SHIFT - | 0x00000000U << DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_SHIFT - | 0x00000000U << DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_SHIFT - | 0x00000000U << DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_SHIFT - | 0x00000000U << DDR_PHY_ZQ1PR0_ZSEGBYP_SHIFT - | 0x00000000U << DDR_PHY_ZQ1PR0_ZLE_MODE_SHIFT - | 0x00000000U << DDR_PHY_ZQ1PR0_ODT_ADJUST_SHIFT - | 0x00000001U << DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_SHIFT - | 0x00000000U << DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_SHIFT - | 0x00000007U << DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_SHIFT - | 0x0000000BU << DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_SHIFT - | 0x0000000DU << DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_SHIFT - | 0x0000000BU << DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_ZQ1PR0_OFFSET ,0xFFFFFFFFU ,0x00087BDBU); - /*############################################################################################################################ */ + * DQSNSE Power Down Receiver + * PSU_DDR_PHY_DX0GCR0_DQSNSEPDR 0x0 - /*Register : DX0GCR0 @ 0XFD080700

+ * DQSSE Power Down Receiver + * PSU_DDR_PHY_DX0GCR0_DQSSEPDR 0x0 - Calibration Bypass - PSU_DDR_PHY_DX0GCR0_CALBYP 0x0 + * RTT On Additive Latency + * PSU_DDR_PHY_DX0GCR0_RTTOAL 0x0 - Master Delay Line Enable - PSU_DDR_PHY_DX0GCR0_MDLEN 0x1 + * RTT Output Hold + * PSU_DDR_PHY_DX0GCR0_RTTOH 0x3 - Configurable ODT(TE) Phase Shift - PSU_DDR_PHY_DX0GCR0_CODTSHFT 0x0 + * Configurable PDR Phase Shift + * PSU_DDR_PHY_DX0GCR0_CPDRSHFT 0x0 - DQS Duty Cycle Correction - PSU_DDR_PHY_DX0GCR0_DQSDCC 0x0 + * DQSR Power Down + * PSU_DDR_PHY_DX0GCR0_DQSRPD 0x0 - Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY - PSU_DDR_PHY_DX0GCR0_RDDLY 0x8 + * DQSG Power Down Receiver + * PSU_DDR_PHY_DX0GCR0_DQSGPDR 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX0GCR0_RESERVED_19_14 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX0GCR0_RESERVED_4 0x0 - DQSNSE Power Down Receiver - PSU_DDR_PHY_DX0GCR0_DQSNSEPDR 0x0 + * DQSG On-Die Termination + * PSU_DDR_PHY_DX0GCR0_DQSGODT 0x0 - DQSSE Power Down Receiver - PSU_DDR_PHY_DX0GCR0_DQSSEPDR 0x0 + * DQSG Output Enable + * PSU_DDR_PHY_DX0GCR0_DQSGOE 0x1 - RTT On Additive Latency - PSU_DDR_PHY_DX0GCR0_RTTOAL 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX0GCR0_RESERVED_1_0 0x0 - RTT Output Hold - PSU_DDR_PHY_DX0GCR0_RTTOH 0x3 + * DATX8 n General Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD080700, 0xFFFFFFFFU ,0x40800604U) + */ + PSU_Mask_Write(DDR_PHY_DX0GCR0_OFFSET, 0xFFFFFFFFU, 0x40800604U); +/*##################################################################### */ - Configurable PDR Phase Shift - PSU_DDR_PHY_DX0GCR0_CPDRSHFT 0x0 + /* + * Register : DX0GCR4 @ 0XFD080710 - DQSR Power Down - PSU_DDR_PHY_DX0GCR0_DQSRPD 0x0 + * Byte lane VREF IOM (Used only by D4MU IOs) + * PSU_DDR_PHY_DX0GCR4_RESERVED_31_29 0x0 - DQSG Power Down Receiver - PSU_DDR_PHY_DX0GCR0_DQSGPDR 0x0 + * Byte Lane VREF Pad Enable + * PSU_DDR_PHY_DX0GCR4_DXREFPEN 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX0GCR0_RESERVED_4 0x0 + * Byte Lane Internal VREF Enable + * PSU_DDR_PHY_DX0GCR4_DXREFEEN 0x3 - DQSG On-Die Termination - PSU_DDR_PHY_DX0GCR0_DQSGODT 0x0 + * Byte Lane Single-End VREF Enable + * PSU_DDR_PHY_DX0GCR4_DXREFSEN 0x1 - DQSG Output Enable - PSU_DDR_PHY_DX0GCR0_DQSGOE 0x1 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX0GCR4_RESERVED_24 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX0GCR0_RESERVED_1_0 0x0 + * External VREF generator REFSEL range select + * PSU_DDR_PHY_DX0GCR4_DXREFESELRANGE 0x0 - DATX8 n General Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD080700, 0xFFFFFFFFU ,0x40800604U) - RegMask = (DDR_PHY_DX0GCR0_CALBYP_MASK | DDR_PHY_DX0GCR0_MDLEN_MASK | DDR_PHY_DX0GCR0_CODTSHFT_MASK | DDR_PHY_DX0GCR0_DQSDCC_MASK | DDR_PHY_DX0GCR0_RDDLY_MASK | DDR_PHY_DX0GCR0_RESERVED_19_14_MASK | DDR_PHY_DX0GCR0_DQSNSEPDR_MASK | DDR_PHY_DX0GCR0_DQSSEPDR_MASK | DDR_PHY_DX0GCR0_RTTOAL_MASK | DDR_PHY_DX0GCR0_RTTOH_MASK | DDR_PHY_DX0GCR0_CPDRSHFT_MASK | DDR_PHY_DX0GCR0_DQSRPD_MASK | DDR_PHY_DX0GCR0_DQSGPDR_MASK | DDR_PHY_DX0GCR0_RESERVED_4_MASK | DDR_PHY_DX0GCR0_DQSGODT_MASK | DDR_PHY_DX0GCR0_DQSGOE_MASK | DDR_PHY_DX0GCR0_RESERVED_1_0_MASK | 0 ); + * Byte Lane External VREF Select + * PSU_DDR_PHY_DX0GCR4_DXREFESEL 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX0GCR0_CALBYP_SHIFT - | 0x00000001U << DDR_PHY_DX0GCR0_MDLEN_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR0_CODTSHFT_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR0_DQSDCC_SHIFT - | 0x00000008U << DDR_PHY_DX0GCR0_RDDLY_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR0_RESERVED_19_14_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR0_DQSNSEPDR_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR0_DQSSEPDR_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR0_RTTOAL_SHIFT - | 0x00000003U << DDR_PHY_DX0GCR0_RTTOH_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR0_CPDRSHFT_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR0_DQSRPD_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR0_DQSGPDR_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR0_RESERVED_4_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR0_DQSGODT_SHIFT - | 0x00000001U << DDR_PHY_DX0GCR0_DQSGOE_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR0_RESERVED_1_0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX0GCR0_OFFSET ,0xFFFFFFFFU ,0x40800604U); - /*############################################################################################################################ */ - - /*Register : DX0GCR4 @ 0XFD080710

- - Byte lane VREF IOM (Used only by D4MU IOs) - PSU_DDR_PHY_DX0GCR4_RESERVED_31_29 0x0 + * Single ended VREF generator REFSEL range select + * PSU_DDR_PHY_DX0GCR4_DXREFSSELRANGE 0x1 - Byte Lane VREF Pad Enable - PSU_DDR_PHY_DX0GCR4_DXREFPEN 0x0 + * Byte Lane Single-End VREF Select + * PSU_DDR_PHY_DX0GCR4_DXREFSSEL 0x30 - Byte Lane Internal VREF Enable - PSU_DDR_PHY_DX0GCR4_DXREFEEN 0x3 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX0GCR4_RESERVED_7_6 0x0 - Byte Lane Single-End VREF Enable - PSU_DDR_PHY_DX0GCR4_DXREFSEN 0x1 + * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX0GCR4_DXREFIEN 0xf - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX0GCR4_RESERVED_24 0x0 + * VRMON control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX0GCR4_DXREFIMON 0x0 - External VREF generator REFSEL range select - PSU_DDR_PHY_DX0GCR4_DXREFESELRANGE 0x0 + * DATX8 n General Configuration Register 4 + * (OFFSET, MASK, VALUE) (0XFD080710, 0xFFFFFFFFU ,0x0E00B03CU) + */ + PSU_Mask_Write(DDR_PHY_DX0GCR4_OFFSET, 0xFFFFFFFFU, 0x0E00B03CU); +/*##################################################################### */ - Byte Lane External VREF Select - PSU_DDR_PHY_DX0GCR4_DXREFESEL 0x0 + /* + * Register : DX0GCR5 @ 0XFD080714 - Single ended VREF generator REFSEL range select - PSU_DDR_PHY_DX0GCR4_DXREFSSELRANGE 0x1 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX0GCR5_RESERVED_31 0x0 - Byte Lane Single-End VREF Select - PSU_DDR_PHY_DX0GCR4_DXREFSSEL 0x30 + * Byte Lane internal VREF Select for Rank 3 + * PSU_DDR_PHY_DX0GCR5_DXREFISELR3 0x9 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX0GCR4_RESERVED_7_6 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX0GCR5_RESERVED_23 0x0 - VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. - PSU_DDR_PHY_DX0GCR4_DXREFIEN 0xf + * Byte Lane internal VREF Select for Rank 2 + * PSU_DDR_PHY_DX0GCR5_DXREFISELR2 0x9 - VRMON control for DQ IO (Single Ended) buffers of a byte lane. - PSU_DDR_PHY_DX0GCR4_DXREFIMON 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX0GCR5_RESERVED_15 0x0 - DATX8 n General Configuration Register 4 - (OFFSET, MASK, VALUE) (0XFD080710, 0xFFFFFFFFU ,0x0E00B03CU) - RegMask = (DDR_PHY_DX0GCR4_RESERVED_31_29_MASK | DDR_PHY_DX0GCR4_DXREFPEN_MASK | DDR_PHY_DX0GCR4_DXREFEEN_MASK | DDR_PHY_DX0GCR4_DXREFSEN_MASK | DDR_PHY_DX0GCR4_RESERVED_24_MASK | DDR_PHY_DX0GCR4_DXREFESELRANGE_MASK | DDR_PHY_DX0GCR4_DXREFESEL_MASK | DDR_PHY_DX0GCR4_DXREFSSELRANGE_MASK | DDR_PHY_DX0GCR4_DXREFSSEL_MASK | DDR_PHY_DX0GCR4_RESERVED_7_6_MASK | DDR_PHY_DX0GCR4_DXREFIEN_MASK | DDR_PHY_DX0GCR4_DXREFIMON_MASK | 0 ); + * Byte Lane internal VREF Select for Rank 1 + * PSU_DDR_PHY_DX0GCR5_DXREFISELR1 0x55 - RegVal = ((0x00000000U << DDR_PHY_DX0GCR4_RESERVED_31_29_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR4_DXREFPEN_SHIFT - | 0x00000003U << DDR_PHY_DX0GCR4_DXREFEEN_SHIFT - | 0x00000001U << DDR_PHY_DX0GCR4_DXREFSEN_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR4_RESERVED_24_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR4_DXREFESELRANGE_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR4_DXREFESEL_SHIFT - | 0x00000001U << DDR_PHY_DX0GCR4_DXREFSSELRANGE_SHIFT - | 0x00000030U << DDR_PHY_DX0GCR4_DXREFSSEL_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR4_RESERVED_7_6_SHIFT - | 0x0000000FU << DDR_PHY_DX0GCR4_DXREFIEN_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR4_DXREFIMON_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX0GCR4_OFFSET ,0xFFFFFFFFU ,0x0E00B03CU); - /*############################################################################################################################ */ + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX0GCR5_RESERVED_7 0x0 - /*Register : DX0GCR5 @ 0XFD080714

+ * Byte Lane internal VREF Select for Rank 0 + * PSU_DDR_PHY_DX0GCR5_DXREFISELR0 0x55 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX0GCR5_RESERVED_31 0x0 + * DATX8 n General Configuration Register 5 + * (OFFSET, MASK, VALUE) (0XFD080714, 0xFFFFFFFFU ,0x09095555U) + */ + PSU_Mask_Write(DDR_PHY_DX0GCR5_OFFSET, 0xFFFFFFFFU, 0x09095555U); +/*##################################################################### */ - Byte Lane internal VREF Select for Rank 3 - PSU_DDR_PHY_DX0GCR5_DXREFISELR3 0x9 - - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX0GCR5_RESERVED_23 0x0 - - Byte Lane internal VREF Select for Rank 2 - PSU_DDR_PHY_DX0GCR5_DXREFISELR2 0x9 - - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX0GCR5_RESERVED_15 0x0 - - Byte Lane internal VREF Select for Rank 1 - PSU_DDR_PHY_DX0GCR5_DXREFISELR1 0x4f - - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX0GCR5_RESERVED_7 0x0 - - Byte Lane internal VREF Select for Rank 0 - PSU_DDR_PHY_DX0GCR5_DXREFISELR0 0x4f + /* + * Register : DX0GCR6 @ 0XFD080718 - DATX8 n General Configuration Register 5 - (OFFSET, MASK, VALUE) (0XFD080714, 0xFFFFFFFFU ,0x09094F4FU) - RegMask = (DDR_PHY_DX0GCR5_RESERVED_31_MASK | DDR_PHY_DX0GCR5_DXREFISELR3_MASK | DDR_PHY_DX0GCR5_RESERVED_23_MASK | DDR_PHY_DX0GCR5_DXREFISELR2_MASK | DDR_PHY_DX0GCR5_RESERVED_15_MASK | DDR_PHY_DX0GCR5_DXREFISELR1_MASK | DDR_PHY_DX0GCR5_RESERVED_7_MASK | DDR_PHY_DX0GCR5_DXREFISELR0_MASK | 0 ); + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX0GCR6_RESERVED_31_30 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX0GCR5_RESERVED_31_SHIFT - | 0x00000009U << DDR_PHY_DX0GCR5_DXREFISELR3_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR5_RESERVED_23_SHIFT - | 0x00000009U << DDR_PHY_DX0GCR5_DXREFISELR2_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR5_RESERVED_15_SHIFT - | 0x0000004FU << DDR_PHY_DX0GCR5_DXREFISELR1_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR5_RESERVED_7_SHIFT - | 0x0000004FU << DDR_PHY_DX0GCR5_DXREFISELR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX0GCR5_OFFSET ,0xFFFFFFFFU ,0x09094F4FU); - /*############################################################################################################################ */ + * DRAM DQ VREF Select for Rank3 + * PSU_DDR_PHY_DX0GCR6_DXDQVREFR3 0x9 - /*Register : DX0GCR6 @ 0XFD080718

+ * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX0GCR6_RESERVED_23_22 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX0GCR6_RESERVED_31_30 0x0 + * DRAM DQ VREF Select for Rank2 + * PSU_DDR_PHY_DX0GCR6_DXDQVREFR2 0x9 - DRAM DQ VREF Select for Rank3 - PSU_DDR_PHY_DX0GCR6_DXDQVREFR3 0x9 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX0GCR6_RESERVED_15_14 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX0GCR6_RESERVED_23_22 0x0 + * DRAM DQ VREF Select for Rank1 + * PSU_DDR_PHY_DX0GCR6_DXDQVREFR1 0x2b - DRAM DQ VREF Select for Rank2 - PSU_DDR_PHY_DX0GCR6_DXDQVREFR2 0x9 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX0GCR6_RESERVED_7_6 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX0GCR6_RESERVED_15_14 0x0 + * DRAM DQ VREF Select for Rank0 + * PSU_DDR_PHY_DX0GCR6_DXDQVREFR0 0x2b - DRAM DQ VREF Select for Rank1 - PSU_DDR_PHY_DX0GCR6_DXDQVREFR1 0x2b + * DATX8 n General Configuration Register 6 + * (OFFSET, MASK, VALUE) (0XFD080718, 0xFFFFFFFFU ,0x09092B2BU) + */ + PSU_Mask_Write(DDR_PHY_DX0GCR6_OFFSET, 0xFFFFFFFFU, 0x09092B2BU); +/*##################################################################### */ - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX0GCR6_RESERVED_7_6 0x0 + /* + * Register : DX1GCR0 @ 0XFD080800 - DRAM DQ VREF Select for Rank0 - PSU_DDR_PHY_DX0GCR6_DXDQVREFR0 0x2b + * Calibration Bypass + * PSU_DDR_PHY_DX1GCR0_CALBYP 0x0 - DATX8 n General Configuration Register 6 - (OFFSET, MASK, VALUE) (0XFD080718, 0xFFFFFFFFU ,0x09092B2BU) - RegMask = (DDR_PHY_DX0GCR6_RESERVED_31_30_MASK | DDR_PHY_DX0GCR6_DXDQVREFR3_MASK | DDR_PHY_DX0GCR6_RESERVED_23_22_MASK | DDR_PHY_DX0GCR6_DXDQVREFR2_MASK | DDR_PHY_DX0GCR6_RESERVED_15_14_MASK | DDR_PHY_DX0GCR6_DXDQVREFR1_MASK | DDR_PHY_DX0GCR6_RESERVED_7_6_MASK | DDR_PHY_DX0GCR6_DXDQVREFR0_MASK | 0 ); + * Master Delay Line Enable + * PSU_DDR_PHY_DX1GCR0_MDLEN 0x1 - RegVal = ((0x00000000U << DDR_PHY_DX0GCR6_RESERVED_31_30_SHIFT - | 0x00000009U << DDR_PHY_DX0GCR6_DXDQVREFR3_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR6_RESERVED_23_22_SHIFT - | 0x00000009U << DDR_PHY_DX0GCR6_DXDQVREFR2_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR6_RESERVED_15_14_SHIFT - | 0x0000002BU << DDR_PHY_DX0GCR6_DXDQVREFR1_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR6_RESERVED_7_6_SHIFT - | 0x0000002BU << DDR_PHY_DX0GCR6_DXDQVREFR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX0GCR6_OFFSET ,0xFFFFFFFFU ,0x09092B2BU); - /*############################################################################################################################ */ + * Configurable ODT(TE) Phase Shift + * PSU_DDR_PHY_DX1GCR0_CODTSHFT 0x0 - /*Register : DX0LCDLR2 @ 0XFD080788

+ * DQS Duty Cycle Correction + * PSU_DDR_PHY_DX1GCR0_DQSDCC 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX0LCDLR2_RESERVED_31_25 0x0 + * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY + * PSU_DDR_PHY_DX1GCR0_RDDLY 0x8 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX0LCDLR2_RESERVED_24_16 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX1GCR0_RESERVED_19_14 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX0LCDLR2_RESERVED_15_9 0x0 + * DQSNSE Power Down Receiver + * PSU_DDR_PHY_DX1GCR0_DQSNSEPDR 0x0 - Read DQS Gating Delay - PSU_DDR_PHY_DX0LCDLR2_DQSGD 0x0 + * DQSSE Power Down Receiver + * PSU_DDR_PHY_DX1GCR0_DQSSEPDR 0x0 - DATX8 n Local Calibrated Delay Line Register 2 - (OFFSET, MASK, VALUE) (0XFD080788, 0xFFFFFFFFU ,0x00000000U) - RegMask = (DDR_PHY_DX0LCDLR2_RESERVED_31_25_MASK | DDR_PHY_DX0LCDLR2_RESERVED_24_16_MASK | DDR_PHY_DX0LCDLR2_RESERVED_15_9_MASK | DDR_PHY_DX0LCDLR2_DQSGD_MASK | 0 ); + * RTT On Additive Latency + * PSU_DDR_PHY_DX1GCR0_RTTOAL 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX0LCDLR2_RESERVED_31_25_SHIFT - | 0x00000000U << DDR_PHY_DX0LCDLR2_RESERVED_24_16_SHIFT - | 0x00000000U << DDR_PHY_DX0LCDLR2_RESERVED_15_9_SHIFT - | 0x00000000U << DDR_PHY_DX0LCDLR2_DQSGD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX0LCDLR2_OFFSET ,0xFFFFFFFFU ,0x00000000U); - /*############################################################################################################################ */ + * RTT Output Hold + * PSU_DDR_PHY_DX1GCR0_RTTOH 0x3 - /*Register : DX0GTR0 @ 0XFD0807C0

+ * Configurable PDR Phase Shift + * PSU_DDR_PHY_DX1GCR0_CPDRSHFT 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX0GTR0_RESERVED_31_24 0x0 + * DQSR Power Down + * PSU_DDR_PHY_DX1GCR0_DQSRPD 0x0 - DQ Write Path Latency Pipeline - PSU_DDR_PHY_DX0GTR0_WDQSL 0x0 + * DQSG Power Down Receiver + * PSU_DDR_PHY_DX1GCR0_DQSGPDR 0x0 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX0GTR0_RESERVED_23_20 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX1GCR0_RESERVED_4 0x0 - Write Leveling System Latency - PSU_DDR_PHY_DX0GTR0_WLSL 0x2 + * DQSG On-Die Termination + * PSU_DDR_PHY_DX1GCR0_DQSGODT 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX0GTR0_RESERVED_15_13 0x0 + * DQSG Output Enable + * PSU_DDR_PHY_DX1GCR0_DQSGOE 0x1 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX0GTR0_RESERVED_12_8 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX1GCR0_RESERVED_1_0 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX0GTR0_RESERVED_7_5 0x0 + * DATX8 n General Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD080800, 0xFFFFFFFFU ,0x40800604U) + */ + PSU_Mask_Write(DDR_PHY_DX1GCR0_OFFSET, 0xFFFFFFFFU, 0x40800604U); +/*##################################################################### */ - DQS Gating System Latency - PSU_DDR_PHY_DX0GTR0_DGSL 0x0 + /* + * Register : DX1GCR4 @ 0XFD080810 - DATX8 n General Timing Register 0 - (OFFSET, MASK, VALUE) (0XFD0807C0, 0xFFFFFFFFU ,0x00020000U) - RegMask = (DDR_PHY_DX0GTR0_RESERVED_31_24_MASK | DDR_PHY_DX0GTR0_WDQSL_MASK | DDR_PHY_DX0GTR0_RESERVED_23_20_MASK | DDR_PHY_DX0GTR0_WLSL_MASK | DDR_PHY_DX0GTR0_RESERVED_15_13_MASK | DDR_PHY_DX0GTR0_RESERVED_12_8_MASK | DDR_PHY_DX0GTR0_RESERVED_7_5_MASK | DDR_PHY_DX0GTR0_DGSL_MASK | 0 ); + * Byte lane VREF IOM (Used only by D4MU IOs) + * PSU_DDR_PHY_DX1GCR4_RESERVED_31_29 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX0GTR0_RESERVED_31_24_SHIFT - | 0x00000000U << DDR_PHY_DX0GTR0_WDQSL_SHIFT - | 0x00000000U << DDR_PHY_DX0GTR0_RESERVED_23_20_SHIFT - | 0x00000002U << DDR_PHY_DX0GTR0_WLSL_SHIFT - | 0x00000000U << DDR_PHY_DX0GTR0_RESERVED_15_13_SHIFT - | 0x00000000U << DDR_PHY_DX0GTR0_RESERVED_12_8_SHIFT - | 0x00000000U << DDR_PHY_DX0GTR0_RESERVED_7_5_SHIFT - | 0x00000000U << DDR_PHY_DX0GTR0_DGSL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX0GTR0_OFFSET ,0xFFFFFFFFU ,0x00020000U); - /*############################################################################################################################ */ + * Byte Lane VREF Pad Enable + * PSU_DDR_PHY_DX1GCR4_DXREFPEN 0x0 - /*Register : DX1GCR0 @ 0XFD080800

+ * Byte Lane Internal VREF Enable + * PSU_DDR_PHY_DX1GCR4_DXREFEEN 0x3 - Calibration Bypass - PSU_DDR_PHY_DX1GCR0_CALBYP 0x0 + * Byte Lane Single-End VREF Enable + * PSU_DDR_PHY_DX1GCR4_DXREFSEN 0x1 - Master Delay Line Enable - PSU_DDR_PHY_DX1GCR0_MDLEN 0x1 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX1GCR4_RESERVED_24 0x0 - Configurable ODT(TE) Phase Shift - PSU_DDR_PHY_DX1GCR0_CODTSHFT 0x0 + * External VREF generator REFSEL range select + * PSU_DDR_PHY_DX1GCR4_DXREFESELRANGE 0x0 - DQS Duty Cycle Correction - PSU_DDR_PHY_DX1GCR0_DQSDCC 0x0 + * Byte Lane External VREF Select + * PSU_DDR_PHY_DX1GCR4_DXREFESEL 0x0 - Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY - PSU_DDR_PHY_DX1GCR0_RDDLY 0x8 + * Single ended VREF generator REFSEL range select + * PSU_DDR_PHY_DX1GCR4_DXREFSSELRANGE 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX1GCR0_RESERVED_19_14 0x0 + * Byte Lane Single-End VREF Select + * PSU_DDR_PHY_DX1GCR4_DXREFSSEL 0x30 - DQSNSE Power Down Receiver - PSU_DDR_PHY_DX1GCR0_DQSNSEPDR 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX1GCR4_RESERVED_7_6 0x0 - DQSSE Power Down Receiver - PSU_DDR_PHY_DX1GCR0_DQSSEPDR 0x0 + * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX1GCR4_DXREFIEN 0xf - RTT On Additive Latency - PSU_DDR_PHY_DX1GCR0_RTTOAL 0x0 + * VRMON control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX1GCR4_DXREFIMON 0x0 - RTT Output Hold - PSU_DDR_PHY_DX1GCR0_RTTOH 0x3 + * DATX8 n General Configuration Register 4 + * (OFFSET, MASK, VALUE) (0XFD080810, 0xFFFFFFFFU ,0x0E00B03CU) + */ + PSU_Mask_Write(DDR_PHY_DX1GCR4_OFFSET, 0xFFFFFFFFU, 0x0E00B03CU); +/*##################################################################### */ - Configurable PDR Phase Shift - PSU_DDR_PHY_DX1GCR0_CPDRSHFT 0x0 + /* + * Register : DX1GCR5 @ 0XFD080814 - DQSR Power Down - PSU_DDR_PHY_DX1GCR0_DQSRPD 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX1GCR5_RESERVED_31 0x0 - DQSG Power Down Receiver - PSU_DDR_PHY_DX1GCR0_DQSGPDR 0x0 + * Byte Lane internal VREF Select for Rank 3 + * PSU_DDR_PHY_DX1GCR5_DXREFISELR3 0x9 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX1GCR0_RESERVED_4 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX1GCR5_RESERVED_23 0x0 - DQSG On-Die Termination - PSU_DDR_PHY_DX1GCR0_DQSGODT 0x0 + * Byte Lane internal VREF Select for Rank 2 + * PSU_DDR_PHY_DX1GCR5_DXREFISELR2 0x9 - DQSG Output Enable - PSU_DDR_PHY_DX1GCR0_DQSGOE 0x1 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX1GCR5_RESERVED_15 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX1GCR0_RESERVED_1_0 0x0 + * Byte Lane internal VREF Select for Rank 1 + * PSU_DDR_PHY_DX1GCR5_DXREFISELR1 0x55 - DATX8 n General Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD080800, 0xFFFFFFFFU ,0x40800604U) - RegMask = (DDR_PHY_DX1GCR0_CALBYP_MASK | DDR_PHY_DX1GCR0_MDLEN_MASK | DDR_PHY_DX1GCR0_CODTSHFT_MASK | DDR_PHY_DX1GCR0_DQSDCC_MASK | DDR_PHY_DX1GCR0_RDDLY_MASK | DDR_PHY_DX1GCR0_RESERVED_19_14_MASK | DDR_PHY_DX1GCR0_DQSNSEPDR_MASK | DDR_PHY_DX1GCR0_DQSSEPDR_MASK | DDR_PHY_DX1GCR0_RTTOAL_MASK | DDR_PHY_DX1GCR0_RTTOH_MASK | DDR_PHY_DX1GCR0_CPDRSHFT_MASK | DDR_PHY_DX1GCR0_DQSRPD_MASK | DDR_PHY_DX1GCR0_DQSGPDR_MASK | DDR_PHY_DX1GCR0_RESERVED_4_MASK | DDR_PHY_DX1GCR0_DQSGODT_MASK | DDR_PHY_DX1GCR0_DQSGOE_MASK | DDR_PHY_DX1GCR0_RESERVED_1_0_MASK | 0 ); + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX1GCR5_RESERVED_7 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX1GCR0_CALBYP_SHIFT - | 0x00000001U << DDR_PHY_DX1GCR0_MDLEN_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR0_CODTSHFT_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR0_DQSDCC_SHIFT - | 0x00000008U << DDR_PHY_DX1GCR0_RDDLY_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR0_RESERVED_19_14_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR0_DQSNSEPDR_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR0_DQSSEPDR_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR0_RTTOAL_SHIFT - | 0x00000003U << DDR_PHY_DX1GCR0_RTTOH_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR0_CPDRSHFT_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR0_DQSRPD_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR0_DQSGPDR_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR0_RESERVED_4_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR0_DQSGODT_SHIFT - | 0x00000001U << DDR_PHY_DX1GCR0_DQSGOE_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR0_RESERVED_1_0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX1GCR0_OFFSET ,0xFFFFFFFFU ,0x40800604U); - /*############################################################################################################################ */ + * Byte Lane internal VREF Select for Rank 0 + * PSU_DDR_PHY_DX1GCR5_DXREFISELR0 0x55 - /*Register : DX1GCR4 @ 0XFD080810

+ * DATX8 n General Configuration Register 5 + * (OFFSET, MASK, VALUE) (0XFD080814, 0xFFFFFFFFU ,0x09095555U) + */ + PSU_Mask_Write(DDR_PHY_DX1GCR5_OFFSET, 0xFFFFFFFFU, 0x09095555U); +/*##################################################################### */ - Byte lane VREF IOM (Used only by D4MU IOs) - PSU_DDR_PHY_DX1GCR4_RESERVED_31_29 0x0 + /* + * Register : DX1GCR6 @ 0XFD080818 - Byte Lane VREF Pad Enable - PSU_DDR_PHY_DX1GCR4_DXREFPEN 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX1GCR6_RESERVED_31_30 0x0 - Byte Lane Internal VREF Enable - PSU_DDR_PHY_DX1GCR4_DXREFEEN 0x3 + * DRAM DQ VREF Select for Rank3 + * PSU_DDR_PHY_DX1GCR6_DXDQVREFR3 0x9 - Byte Lane Single-End VREF Enable - PSU_DDR_PHY_DX1GCR4_DXREFSEN 0x1 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX1GCR6_RESERVED_23_22 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX1GCR4_RESERVED_24 0x0 + * DRAM DQ VREF Select for Rank2 + * PSU_DDR_PHY_DX1GCR6_DXDQVREFR2 0x9 - External VREF generator REFSEL range select - PSU_DDR_PHY_DX1GCR4_DXREFESELRANGE 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX1GCR6_RESERVED_15_14 0x0 - Byte Lane External VREF Select - PSU_DDR_PHY_DX1GCR4_DXREFESEL 0x0 + * DRAM DQ VREF Select for Rank1 + * PSU_DDR_PHY_DX1GCR6_DXDQVREFR1 0x2b - Single ended VREF generator REFSEL range select - PSU_DDR_PHY_DX1GCR4_DXREFSSELRANGE 0x1 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX1GCR6_RESERVED_7_6 0x0 - Byte Lane Single-End VREF Select - PSU_DDR_PHY_DX1GCR4_DXREFSSEL 0x30 + * DRAM DQ VREF Select for Rank0 + * PSU_DDR_PHY_DX1GCR6_DXDQVREFR0 0x2b - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX1GCR4_RESERVED_7_6 0x0 + * DATX8 n General Configuration Register 6 + * (OFFSET, MASK, VALUE) (0XFD080818, 0xFFFFFFFFU ,0x09092B2BU) + */ + PSU_Mask_Write(DDR_PHY_DX1GCR6_OFFSET, 0xFFFFFFFFU, 0x09092B2BU); +/*##################################################################### */ - VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. - PSU_DDR_PHY_DX1GCR4_DXREFIEN 0xf + /* + * Register : DX2GCR0 @ 0XFD080900 - VRMON control for DQ IO (Single Ended) buffers of a byte lane. - PSU_DDR_PHY_DX1GCR4_DXREFIMON 0x0 + * Calibration Bypass + * PSU_DDR_PHY_DX2GCR0_CALBYP 0x0 - DATX8 n General Configuration Register 4 - (OFFSET, MASK, VALUE) (0XFD080810, 0xFFFFFFFFU ,0x0E00B03CU) - RegMask = (DDR_PHY_DX1GCR4_RESERVED_31_29_MASK | DDR_PHY_DX1GCR4_DXREFPEN_MASK | DDR_PHY_DX1GCR4_DXREFEEN_MASK | DDR_PHY_DX1GCR4_DXREFSEN_MASK | DDR_PHY_DX1GCR4_RESERVED_24_MASK | DDR_PHY_DX1GCR4_DXREFESELRANGE_MASK | DDR_PHY_DX1GCR4_DXREFESEL_MASK | DDR_PHY_DX1GCR4_DXREFSSELRANGE_MASK | DDR_PHY_DX1GCR4_DXREFSSEL_MASK | DDR_PHY_DX1GCR4_RESERVED_7_6_MASK | DDR_PHY_DX1GCR4_DXREFIEN_MASK | DDR_PHY_DX1GCR4_DXREFIMON_MASK | 0 ); + * Master Delay Line Enable + * PSU_DDR_PHY_DX2GCR0_MDLEN 0x1 - RegVal = ((0x00000000U << DDR_PHY_DX1GCR4_RESERVED_31_29_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR4_DXREFPEN_SHIFT - | 0x00000003U << DDR_PHY_DX1GCR4_DXREFEEN_SHIFT - | 0x00000001U << DDR_PHY_DX1GCR4_DXREFSEN_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR4_RESERVED_24_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR4_DXREFESELRANGE_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR4_DXREFESEL_SHIFT - | 0x00000001U << DDR_PHY_DX1GCR4_DXREFSSELRANGE_SHIFT - | 0x00000030U << DDR_PHY_DX1GCR4_DXREFSSEL_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR4_RESERVED_7_6_SHIFT - | 0x0000000FU << DDR_PHY_DX1GCR4_DXREFIEN_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR4_DXREFIMON_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX1GCR4_OFFSET ,0xFFFFFFFFU ,0x0E00B03CU); - /*############################################################################################################################ */ + * Configurable ODT(TE) Phase Shift + * PSU_DDR_PHY_DX2GCR0_CODTSHFT 0x0 - /*Register : DX1GCR5 @ 0XFD080814

+ * DQS Duty Cycle Correction + * PSU_DDR_PHY_DX2GCR0_DQSDCC 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX1GCR5_RESERVED_31 0x0 + * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY + * PSU_DDR_PHY_DX2GCR0_RDDLY 0x8 - Byte Lane internal VREF Select for Rank 3 - PSU_DDR_PHY_DX1GCR5_DXREFISELR3 0x9 - - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX1GCR5_RESERVED_23 0x0 - - Byte Lane internal VREF Select for Rank 2 - PSU_DDR_PHY_DX1GCR5_DXREFISELR2 0x9 - - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX1GCR5_RESERVED_15 0x0 - - Byte Lane internal VREF Select for Rank 1 - PSU_DDR_PHY_DX1GCR5_DXREFISELR1 0x4f - - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX1GCR5_RESERVED_7 0x0 - - Byte Lane internal VREF Select for Rank 0 - PSU_DDR_PHY_DX1GCR5_DXREFISELR0 0x4f + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX2GCR0_RESERVED_19_14 0x0 - DATX8 n General Configuration Register 5 - (OFFSET, MASK, VALUE) (0XFD080814, 0xFFFFFFFFU ,0x09094F4FU) - RegMask = (DDR_PHY_DX1GCR5_RESERVED_31_MASK | DDR_PHY_DX1GCR5_DXREFISELR3_MASK | DDR_PHY_DX1GCR5_RESERVED_23_MASK | DDR_PHY_DX1GCR5_DXREFISELR2_MASK | DDR_PHY_DX1GCR5_RESERVED_15_MASK | DDR_PHY_DX1GCR5_DXREFISELR1_MASK | DDR_PHY_DX1GCR5_RESERVED_7_MASK | DDR_PHY_DX1GCR5_DXREFISELR0_MASK | 0 ); + * DQSNSE Power Down Receiver + * PSU_DDR_PHY_DX2GCR0_DQSNSEPDR 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX1GCR5_RESERVED_31_SHIFT - | 0x00000009U << DDR_PHY_DX1GCR5_DXREFISELR3_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR5_RESERVED_23_SHIFT - | 0x00000009U << DDR_PHY_DX1GCR5_DXREFISELR2_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR5_RESERVED_15_SHIFT - | 0x0000004FU << DDR_PHY_DX1GCR5_DXREFISELR1_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR5_RESERVED_7_SHIFT - | 0x0000004FU << DDR_PHY_DX1GCR5_DXREFISELR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX1GCR5_OFFSET ,0xFFFFFFFFU ,0x09094F4FU); - /*############################################################################################################################ */ + * DQSSE Power Down Receiver + * PSU_DDR_PHY_DX2GCR0_DQSSEPDR 0x0 - /*Register : DX1GCR6 @ 0XFD080818

+ * RTT On Additive Latency + * PSU_DDR_PHY_DX2GCR0_RTTOAL 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX1GCR6_RESERVED_31_30 0x0 + * RTT Output Hold + * PSU_DDR_PHY_DX2GCR0_RTTOH 0x3 - DRAM DQ VREF Select for Rank3 - PSU_DDR_PHY_DX1GCR6_DXDQVREFR3 0x9 + * Configurable PDR Phase Shift + * PSU_DDR_PHY_DX2GCR0_CPDRSHFT 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX1GCR6_RESERVED_23_22 0x0 + * DQSR Power Down + * PSU_DDR_PHY_DX2GCR0_DQSRPD 0x0 - DRAM DQ VREF Select for Rank2 - PSU_DDR_PHY_DX1GCR6_DXDQVREFR2 0x9 + * DQSG Power Down Receiver + * PSU_DDR_PHY_DX2GCR0_DQSGPDR 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX1GCR6_RESERVED_15_14 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX2GCR0_RESERVED_4 0x0 - DRAM DQ VREF Select for Rank1 - PSU_DDR_PHY_DX1GCR6_DXDQVREFR1 0x2b + * DQSG On-Die Termination + * PSU_DDR_PHY_DX2GCR0_DQSGODT 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX1GCR6_RESERVED_7_6 0x0 + * DQSG Output Enable + * PSU_DDR_PHY_DX2GCR0_DQSGOE 0x1 - DRAM DQ VREF Select for Rank0 - PSU_DDR_PHY_DX1GCR6_DXDQVREFR0 0x2b + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX2GCR0_RESERVED_1_0 0x0 - DATX8 n General Configuration Register 6 - (OFFSET, MASK, VALUE) (0XFD080818, 0xFFFFFFFFU ,0x09092B2BU) - RegMask = (DDR_PHY_DX1GCR6_RESERVED_31_30_MASK | DDR_PHY_DX1GCR6_DXDQVREFR3_MASK | DDR_PHY_DX1GCR6_RESERVED_23_22_MASK | DDR_PHY_DX1GCR6_DXDQVREFR2_MASK | DDR_PHY_DX1GCR6_RESERVED_15_14_MASK | DDR_PHY_DX1GCR6_DXDQVREFR1_MASK | DDR_PHY_DX1GCR6_RESERVED_7_6_MASK | DDR_PHY_DX1GCR6_DXDQVREFR0_MASK | 0 ); + * DATX8 n General Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD080900, 0xFFFFFFFFU ,0x40800604U) + */ + PSU_Mask_Write(DDR_PHY_DX2GCR0_OFFSET, 0xFFFFFFFFU, 0x40800604U); +/*##################################################################### */ - RegVal = ((0x00000000U << DDR_PHY_DX1GCR6_RESERVED_31_30_SHIFT - | 0x00000009U << DDR_PHY_DX1GCR6_DXDQVREFR3_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR6_RESERVED_23_22_SHIFT - | 0x00000009U << DDR_PHY_DX1GCR6_DXDQVREFR2_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR6_RESERVED_15_14_SHIFT - | 0x0000002BU << DDR_PHY_DX1GCR6_DXDQVREFR1_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR6_RESERVED_7_6_SHIFT - | 0x0000002BU << DDR_PHY_DX1GCR6_DXDQVREFR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX1GCR6_OFFSET ,0xFFFFFFFFU ,0x09092B2BU); - /*############################################################################################################################ */ + /* + * Register : DX2GCR1 @ 0XFD080904 - /*Register : DX1LCDLR2 @ 0XFD080888

+ * Enables the PDR mode for DQ[7:0] + * PSU_DDR_PHY_DX2GCR1_DXPDRMODE 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX1LCDLR2_RESERVED_31_25 0x0 + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX2GCR1_RESERVED_15 0x0 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX1LCDLR2_RESERVED_24_16 0x0 + * Select the delayed or non-delayed read data strobe # + * PSU_DDR_PHY_DX2GCR1_QSNSEL 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX1LCDLR2_RESERVED_15_9 0x0 + * Select the delayed or non-delayed read data strobe + * PSU_DDR_PHY_DX2GCR1_QSSEL 0x1 - Read DQS Gating Delay - PSU_DDR_PHY_DX1LCDLR2_DQSGD 0x0 + * Enables Read Data Strobe in a byte lane + * PSU_DDR_PHY_DX2GCR1_OEEN 0x1 - DATX8 n Local Calibrated Delay Line Register 2 - (OFFSET, MASK, VALUE) (0XFD080888, 0xFFFFFFFFU ,0x00000000U) - RegMask = (DDR_PHY_DX1LCDLR2_RESERVED_31_25_MASK | DDR_PHY_DX1LCDLR2_RESERVED_24_16_MASK | DDR_PHY_DX1LCDLR2_RESERVED_15_9_MASK | DDR_PHY_DX1LCDLR2_DQSGD_MASK | 0 ); + * Enables PDR in a byte lane + * PSU_DDR_PHY_DX2GCR1_PDREN 0x1 - RegVal = ((0x00000000U << DDR_PHY_DX1LCDLR2_RESERVED_31_25_SHIFT - | 0x00000000U << DDR_PHY_DX1LCDLR2_RESERVED_24_16_SHIFT - | 0x00000000U << DDR_PHY_DX1LCDLR2_RESERVED_15_9_SHIFT - | 0x00000000U << DDR_PHY_DX1LCDLR2_DQSGD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX1LCDLR2_OFFSET ,0xFFFFFFFFU ,0x00000000U); - /*############################################################################################################################ */ + * Enables ODT/TE in a byte lane + * PSU_DDR_PHY_DX2GCR1_TEEN 0x1 - /*Register : DX1GTR0 @ 0XFD0808C0

+ * Enables Write Data strobe in a byte lane + * PSU_DDR_PHY_DX2GCR1_DSEN 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX1GTR0_RESERVED_31_24 0x0 + * Enables DM pin in a byte lane + * PSU_DDR_PHY_DX2GCR1_DMEN 0x1 - DQ Write Path Latency Pipeline - PSU_DDR_PHY_DX1GTR0_WDQSL 0x0 + * Enables DQ corresponding to each bit in a byte + * PSU_DDR_PHY_DX2GCR1_DQEN 0xff - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX1GTR0_RESERVED_23_20 0x0 + * DATX8 n General Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD080904, 0xFFFFFFFFU ,0x00007FFFU) + */ + PSU_Mask_Write(DDR_PHY_DX2GCR1_OFFSET, 0xFFFFFFFFU, 0x00007FFFU); +/*##################################################################### */ - Write Leveling System Latency - PSU_DDR_PHY_DX1GTR0_WLSL 0x2 + /* + * Register : DX2GCR4 @ 0XFD080910 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX1GTR0_RESERVED_15_13 0x0 + * Byte lane VREF IOM (Used only by D4MU IOs) + * PSU_DDR_PHY_DX2GCR4_RESERVED_31_29 0x0 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX1GTR0_RESERVED_12_8 0x0 + * Byte Lane VREF Pad Enable + * PSU_DDR_PHY_DX2GCR4_DXREFPEN 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX1GTR0_RESERVED_7_5 0x0 + * Byte Lane Internal VREF Enable + * PSU_DDR_PHY_DX2GCR4_DXREFEEN 0x3 - DQS Gating System Latency - PSU_DDR_PHY_DX1GTR0_DGSL 0x0 + * Byte Lane Single-End VREF Enable + * PSU_DDR_PHY_DX2GCR4_DXREFSEN 0x1 - DATX8 n General Timing Register 0 - (OFFSET, MASK, VALUE) (0XFD0808C0, 0xFFFFFFFFU ,0x00020000U) - RegMask = (DDR_PHY_DX1GTR0_RESERVED_31_24_MASK | DDR_PHY_DX1GTR0_WDQSL_MASK | DDR_PHY_DX1GTR0_RESERVED_23_20_MASK | DDR_PHY_DX1GTR0_WLSL_MASK | DDR_PHY_DX1GTR0_RESERVED_15_13_MASK | DDR_PHY_DX1GTR0_RESERVED_12_8_MASK | DDR_PHY_DX1GTR0_RESERVED_7_5_MASK | DDR_PHY_DX1GTR0_DGSL_MASK | 0 ); + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX2GCR4_RESERVED_24 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX1GTR0_RESERVED_31_24_SHIFT - | 0x00000000U << DDR_PHY_DX1GTR0_WDQSL_SHIFT - | 0x00000000U << DDR_PHY_DX1GTR0_RESERVED_23_20_SHIFT - | 0x00000002U << DDR_PHY_DX1GTR0_WLSL_SHIFT - | 0x00000000U << DDR_PHY_DX1GTR0_RESERVED_15_13_SHIFT - | 0x00000000U << DDR_PHY_DX1GTR0_RESERVED_12_8_SHIFT - | 0x00000000U << DDR_PHY_DX1GTR0_RESERVED_7_5_SHIFT - | 0x00000000U << DDR_PHY_DX1GTR0_DGSL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX1GTR0_OFFSET ,0xFFFFFFFFU ,0x00020000U); - /*############################################################################################################################ */ + * External VREF generator REFSEL range select + * PSU_DDR_PHY_DX2GCR4_DXREFESELRANGE 0x0 - /*Register : DX2GCR0 @ 0XFD080900

+ * Byte Lane External VREF Select + * PSU_DDR_PHY_DX2GCR4_DXREFESEL 0x0 - Calibration Bypass - PSU_DDR_PHY_DX2GCR0_CALBYP 0x0 + * Single ended VREF generator REFSEL range select + * PSU_DDR_PHY_DX2GCR4_DXREFSSELRANGE 0x1 - Master Delay Line Enable - PSU_DDR_PHY_DX2GCR0_MDLEN 0x1 + * Byte Lane Single-End VREF Select + * PSU_DDR_PHY_DX2GCR4_DXREFSSEL 0x30 - Configurable ODT(TE) Phase Shift - PSU_DDR_PHY_DX2GCR0_CODTSHFT 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX2GCR4_RESERVED_7_6 0x0 - DQS Duty Cycle Correction - PSU_DDR_PHY_DX2GCR0_DQSDCC 0x0 + * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX2GCR4_DXREFIEN 0xf - Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY - PSU_DDR_PHY_DX2GCR0_RDDLY 0x8 + * VRMON control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX2GCR4_DXREFIMON 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX2GCR0_RESERVED_19_14 0x0 + * DATX8 n General Configuration Register 4 + * (OFFSET, MASK, VALUE) (0XFD080910, 0xFFFFFFFFU ,0x0E00B03CU) + */ + PSU_Mask_Write(DDR_PHY_DX2GCR4_OFFSET, 0xFFFFFFFFU, 0x0E00B03CU); +/*##################################################################### */ - DQSNSE Power Down Receiver - PSU_DDR_PHY_DX2GCR0_DQSNSEPDR 0x0 + /* + * Register : DX2GCR5 @ 0XFD080914 - DQSSE Power Down Receiver - PSU_DDR_PHY_DX2GCR0_DQSSEPDR 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX2GCR5_RESERVED_31 0x0 - RTT On Additive Latency - PSU_DDR_PHY_DX2GCR0_RTTOAL 0x0 + * Byte Lane internal VREF Select for Rank 3 + * PSU_DDR_PHY_DX2GCR5_DXREFISELR3 0x9 - RTT Output Hold - PSU_DDR_PHY_DX2GCR0_RTTOH 0x3 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX2GCR5_RESERVED_23 0x0 - Configurable PDR Phase Shift - PSU_DDR_PHY_DX2GCR0_CPDRSHFT 0x0 + * Byte Lane internal VREF Select for Rank 2 + * PSU_DDR_PHY_DX2GCR5_DXREFISELR2 0x9 - DQSR Power Down - PSU_DDR_PHY_DX2GCR0_DQSRPD 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX2GCR5_RESERVED_15 0x0 - DQSG Power Down Receiver - PSU_DDR_PHY_DX2GCR0_DQSGPDR 0x0 + * Byte Lane internal VREF Select for Rank 1 + * PSU_DDR_PHY_DX2GCR5_DXREFISELR1 0x55 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX2GCR0_RESERVED_4 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX2GCR5_RESERVED_7 0x0 - DQSG On-Die Termination - PSU_DDR_PHY_DX2GCR0_DQSGODT 0x0 + * Byte Lane internal VREF Select for Rank 0 + * PSU_DDR_PHY_DX2GCR5_DXREFISELR0 0x55 - DQSG Output Enable - PSU_DDR_PHY_DX2GCR0_DQSGOE 0x1 + * DATX8 n General Configuration Register 5 + * (OFFSET, MASK, VALUE) (0XFD080914, 0xFFFFFFFFU ,0x09095555U) + */ + PSU_Mask_Write(DDR_PHY_DX2GCR5_OFFSET, 0xFFFFFFFFU, 0x09095555U); +/*##################################################################### */ - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX2GCR0_RESERVED_1_0 0x0 + /* + * Register : DX2GCR6 @ 0XFD080918 - DATX8 n General Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD080900, 0xFFFFFFFFU ,0x40800604U) - RegMask = (DDR_PHY_DX2GCR0_CALBYP_MASK | DDR_PHY_DX2GCR0_MDLEN_MASK | DDR_PHY_DX2GCR0_CODTSHFT_MASK | DDR_PHY_DX2GCR0_DQSDCC_MASK | DDR_PHY_DX2GCR0_RDDLY_MASK | DDR_PHY_DX2GCR0_RESERVED_19_14_MASK | DDR_PHY_DX2GCR0_DQSNSEPDR_MASK | DDR_PHY_DX2GCR0_DQSSEPDR_MASK | DDR_PHY_DX2GCR0_RTTOAL_MASK | DDR_PHY_DX2GCR0_RTTOH_MASK | DDR_PHY_DX2GCR0_CPDRSHFT_MASK | DDR_PHY_DX2GCR0_DQSRPD_MASK | DDR_PHY_DX2GCR0_DQSGPDR_MASK | DDR_PHY_DX2GCR0_RESERVED_4_MASK | DDR_PHY_DX2GCR0_DQSGODT_MASK | DDR_PHY_DX2GCR0_DQSGOE_MASK | DDR_PHY_DX2GCR0_RESERVED_1_0_MASK | 0 ); + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX2GCR6_RESERVED_31_30 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX2GCR0_CALBYP_SHIFT - | 0x00000001U << DDR_PHY_DX2GCR0_MDLEN_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR0_CODTSHFT_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR0_DQSDCC_SHIFT - | 0x00000008U << DDR_PHY_DX2GCR0_RDDLY_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR0_RESERVED_19_14_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR0_DQSNSEPDR_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR0_DQSSEPDR_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR0_RTTOAL_SHIFT - | 0x00000003U << DDR_PHY_DX2GCR0_RTTOH_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR0_CPDRSHFT_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR0_DQSRPD_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR0_DQSGPDR_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR0_RESERVED_4_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR0_DQSGODT_SHIFT - | 0x00000001U << DDR_PHY_DX2GCR0_DQSGOE_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR0_RESERVED_1_0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX2GCR0_OFFSET ,0xFFFFFFFFU ,0x40800604U); - /*############################################################################################################################ */ + * DRAM DQ VREF Select for Rank3 + * PSU_DDR_PHY_DX2GCR6_DXDQVREFR3 0x9 - /*Register : DX2GCR1 @ 0XFD080904

+ * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX2GCR6_RESERVED_23_22 0x0 - Enables the PDR mode for DQ[7:0] - PSU_DDR_PHY_DX2GCR1_DXPDRMODE 0x0 + * DRAM DQ VREF Select for Rank2 + * PSU_DDR_PHY_DX2GCR6_DXDQVREFR2 0x9 - Reserved. Returns zeroes on reads. - PSU_DDR_PHY_DX2GCR1_RESERVED_15 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX2GCR6_RESERVED_15_14 0x0 - Select the delayed or non-delayed read data strobe # - PSU_DDR_PHY_DX2GCR1_QSNSEL 0x1 + * DRAM DQ VREF Select for Rank1 + * PSU_DDR_PHY_DX2GCR6_DXDQVREFR1 0x2b - Select the delayed or non-delayed read data strobe - PSU_DDR_PHY_DX2GCR1_QSSEL 0x1 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX2GCR6_RESERVED_7_6 0x0 - Enables Read Data Strobe in a byte lane - PSU_DDR_PHY_DX2GCR1_OEEN 0x1 + * DRAM DQ VREF Select for Rank0 + * PSU_DDR_PHY_DX2GCR6_DXDQVREFR0 0x2b - Enables PDR in a byte lane - PSU_DDR_PHY_DX2GCR1_PDREN 0x1 + * DATX8 n General Configuration Register 6 + * (OFFSET, MASK, VALUE) (0XFD080918, 0xFFFFFFFFU ,0x09092B2BU) + */ + PSU_Mask_Write(DDR_PHY_DX2GCR6_OFFSET, 0xFFFFFFFFU, 0x09092B2BU); +/*##################################################################### */ - Enables ODT/TE in a byte lane - PSU_DDR_PHY_DX2GCR1_TEEN 0x1 + /* + * Register : DX3GCR0 @ 0XFD080A00 - Enables Write Data strobe in a byte lane - PSU_DDR_PHY_DX2GCR1_DSEN 0x1 + * Calibration Bypass + * PSU_DDR_PHY_DX3GCR0_CALBYP 0x0 - Enables DM pin in a byte lane - PSU_DDR_PHY_DX2GCR1_DMEN 0x1 + * Master Delay Line Enable + * PSU_DDR_PHY_DX3GCR0_MDLEN 0x1 - Enables DQ corresponding to each bit in a byte - PSU_DDR_PHY_DX2GCR1_DQEN 0xff + * Configurable ODT(TE) Phase Shift + * PSU_DDR_PHY_DX3GCR0_CODTSHFT 0x0 - DATX8 n General Configuration Register 1 - (OFFSET, MASK, VALUE) (0XFD080904, 0xFFFFFFFFU ,0x00007FFFU) - RegMask = (DDR_PHY_DX2GCR1_DXPDRMODE_MASK | DDR_PHY_DX2GCR1_RESERVED_15_MASK | DDR_PHY_DX2GCR1_QSNSEL_MASK | DDR_PHY_DX2GCR1_QSSEL_MASK | DDR_PHY_DX2GCR1_OEEN_MASK | DDR_PHY_DX2GCR1_PDREN_MASK | DDR_PHY_DX2GCR1_TEEN_MASK | DDR_PHY_DX2GCR1_DSEN_MASK | DDR_PHY_DX2GCR1_DMEN_MASK | DDR_PHY_DX2GCR1_DQEN_MASK | 0 ); + * DQS Duty Cycle Correction + * PSU_DDR_PHY_DX3GCR0_DQSDCC 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX2GCR1_DXPDRMODE_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR1_RESERVED_15_SHIFT - | 0x00000001U << DDR_PHY_DX2GCR1_QSNSEL_SHIFT - | 0x00000001U << DDR_PHY_DX2GCR1_QSSEL_SHIFT - | 0x00000001U << DDR_PHY_DX2GCR1_OEEN_SHIFT - | 0x00000001U << DDR_PHY_DX2GCR1_PDREN_SHIFT - | 0x00000001U << DDR_PHY_DX2GCR1_TEEN_SHIFT - | 0x00000001U << DDR_PHY_DX2GCR1_DSEN_SHIFT - | 0x00000001U << DDR_PHY_DX2GCR1_DMEN_SHIFT - | 0x000000FFU << DDR_PHY_DX2GCR1_DQEN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX2GCR1_OFFSET ,0xFFFFFFFFU ,0x00007FFFU); - /*############################################################################################################################ */ + * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY + * PSU_DDR_PHY_DX3GCR0_RDDLY 0x8 - /*Register : DX2GCR4 @ 0XFD080910

+ * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX3GCR0_RESERVED_19_14 0x0 - Byte lane VREF IOM (Used only by D4MU IOs) - PSU_DDR_PHY_DX2GCR4_RESERVED_31_29 0x0 + * DQSNSE Power Down Receiver + * PSU_DDR_PHY_DX3GCR0_DQSNSEPDR 0x0 - Byte Lane VREF Pad Enable - PSU_DDR_PHY_DX2GCR4_DXREFPEN 0x0 + * DQSSE Power Down Receiver + * PSU_DDR_PHY_DX3GCR0_DQSSEPDR 0x0 - Byte Lane Internal VREF Enable - PSU_DDR_PHY_DX2GCR4_DXREFEEN 0x3 + * RTT On Additive Latency + * PSU_DDR_PHY_DX3GCR0_RTTOAL 0x0 - Byte Lane Single-End VREF Enable - PSU_DDR_PHY_DX2GCR4_DXREFSEN 0x1 + * RTT Output Hold + * PSU_DDR_PHY_DX3GCR0_RTTOH 0x3 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX2GCR4_RESERVED_24 0x0 + * Configurable PDR Phase Shift + * PSU_DDR_PHY_DX3GCR0_CPDRSHFT 0x0 - External VREF generator REFSEL range select - PSU_DDR_PHY_DX2GCR4_DXREFESELRANGE 0x0 + * DQSR Power Down + * PSU_DDR_PHY_DX3GCR0_DQSRPD 0x0 - Byte Lane External VREF Select - PSU_DDR_PHY_DX2GCR4_DXREFESEL 0x0 + * DQSG Power Down Receiver + * PSU_DDR_PHY_DX3GCR0_DQSGPDR 0x0 - Single ended VREF generator REFSEL range select - PSU_DDR_PHY_DX2GCR4_DXREFSSELRANGE 0x1 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX3GCR0_RESERVED_4 0x0 - Byte Lane Single-End VREF Select - PSU_DDR_PHY_DX2GCR4_DXREFSSEL 0x30 + * DQSG On-Die Termination + * PSU_DDR_PHY_DX3GCR0_DQSGODT 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX2GCR4_RESERVED_7_6 0x0 + * DQSG Output Enable + * PSU_DDR_PHY_DX3GCR0_DQSGOE 0x1 - VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. - PSU_DDR_PHY_DX2GCR4_DXREFIEN 0xf + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX3GCR0_RESERVED_1_0 0x0 - VRMON control for DQ IO (Single Ended) buffers of a byte lane. - PSU_DDR_PHY_DX2GCR4_DXREFIMON 0x0 + * DATX8 n General Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD080A00, 0xFFFFFFFFU ,0x40800604U) + */ + PSU_Mask_Write(DDR_PHY_DX3GCR0_OFFSET, 0xFFFFFFFFU, 0x40800604U); +/*##################################################################### */ - DATX8 n General Configuration Register 4 - (OFFSET, MASK, VALUE) (0XFD080910, 0xFFFFFFFFU ,0x0E00B03CU) - RegMask = (DDR_PHY_DX2GCR4_RESERVED_31_29_MASK | DDR_PHY_DX2GCR4_DXREFPEN_MASK | DDR_PHY_DX2GCR4_DXREFEEN_MASK | DDR_PHY_DX2GCR4_DXREFSEN_MASK | DDR_PHY_DX2GCR4_RESERVED_24_MASK | DDR_PHY_DX2GCR4_DXREFESELRANGE_MASK | DDR_PHY_DX2GCR4_DXREFESEL_MASK | DDR_PHY_DX2GCR4_DXREFSSELRANGE_MASK | DDR_PHY_DX2GCR4_DXREFSSEL_MASK | DDR_PHY_DX2GCR4_RESERVED_7_6_MASK | DDR_PHY_DX2GCR4_DXREFIEN_MASK | DDR_PHY_DX2GCR4_DXREFIMON_MASK | 0 ); + /* + * Register : DX3GCR1 @ 0XFD080A04 - RegVal = ((0x00000000U << DDR_PHY_DX2GCR4_RESERVED_31_29_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR4_DXREFPEN_SHIFT - | 0x00000003U << DDR_PHY_DX2GCR4_DXREFEEN_SHIFT - | 0x00000001U << DDR_PHY_DX2GCR4_DXREFSEN_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR4_RESERVED_24_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR4_DXREFESELRANGE_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR4_DXREFESEL_SHIFT - | 0x00000001U << DDR_PHY_DX2GCR4_DXREFSSELRANGE_SHIFT - | 0x00000030U << DDR_PHY_DX2GCR4_DXREFSSEL_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR4_RESERVED_7_6_SHIFT - | 0x0000000FU << DDR_PHY_DX2GCR4_DXREFIEN_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR4_DXREFIMON_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX2GCR4_OFFSET ,0xFFFFFFFFU ,0x0E00B03CU); - /*############################################################################################################################ */ + * Enables the PDR mode for DQ[7:0] + * PSU_DDR_PHY_DX3GCR1_DXPDRMODE 0x0 - /*Register : DX2GCR5 @ 0XFD080914

+ * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX3GCR1_RESERVED_15 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX2GCR5_RESERVED_31 0x0 + * Select the delayed or non-delayed read data strobe # + * PSU_DDR_PHY_DX3GCR1_QSNSEL 0x1 - Byte Lane internal VREF Select for Rank 3 - PSU_DDR_PHY_DX2GCR5_DXREFISELR3 0x9 + * Select the delayed or non-delayed read data strobe + * PSU_DDR_PHY_DX3GCR1_QSSEL 0x1 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX2GCR5_RESERVED_23 0x0 + * Enables Read Data Strobe in a byte lane + * PSU_DDR_PHY_DX3GCR1_OEEN 0x1 - Byte Lane internal VREF Select for Rank 2 - PSU_DDR_PHY_DX2GCR5_DXREFISELR2 0x9 + * Enables PDR in a byte lane + * PSU_DDR_PHY_DX3GCR1_PDREN 0x1 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX2GCR5_RESERVED_15 0x0 + * Enables ODT/TE in a byte lane + * PSU_DDR_PHY_DX3GCR1_TEEN 0x1 - Byte Lane internal VREF Select for Rank 1 - PSU_DDR_PHY_DX2GCR5_DXREFISELR1 0x4f + * Enables Write Data strobe in a byte lane + * PSU_DDR_PHY_DX3GCR1_DSEN 0x1 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX2GCR5_RESERVED_7 0x0 + * Enables DM pin in a byte lane + * PSU_DDR_PHY_DX3GCR1_DMEN 0x1 - Byte Lane internal VREF Select for Rank 0 - PSU_DDR_PHY_DX2GCR5_DXREFISELR0 0x4f + * Enables DQ corresponding to each bit in a byte + * PSU_DDR_PHY_DX3GCR1_DQEN 0xff - DATX8 n General Configuration Register 5 - (OFFSET, MASK, VALUE) (0XFD080914, 0xFFFFFFFFU ,0x09094F4FU) - RegMask = (DDR_PHY_DX2GCR5_RESERVED_31_MASK | DDR_PHY_DX2GCR5_DXREFISELR3_MASK | DDR_PHY_DX2GCR5_RESERVED_23_MASK | DDR_PHY_DX2GCR5_DXREFISELR2_MASK | DDR_PHY_DX2GCR5_RESERVED_15_MASK | DDR_PHY_DX2GCR5_DXREFISELR1_MASK | DDR_PHY_DX2GCR5_RESERVED_7_MASK | DDR_PHY_DX2GCR5_DXREFISELR0_MASK | 0 ); + * DATX8 n General Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD080A04, 0xFFFFFFFFU ,0x00007FFFU) + */ + PSU_Mask_Write(DDR_PHY_DX3GCR1_OFFSET, 0xFFFFFFFFU, 0x00007FFFU); +/*##################################################################### */ - RegVal = ((0x00000000U << DDR_PHY_DX2GCR5_RESERVED_31_SHIFT - | 0x00000009U << DDR_PHY_DX2GCR5_DXREFISELR3_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR5_RESERVED_23_SHIFT - | 0x00000009U << DDR_PHY_DX2GCR5_DXREFISELR2_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR5_RESERVED_15_SHIFT - | 0x0000004FU << DDR_PHY_DX2GCR5_DXREFISELR1_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR5_RESERVED_7_SHIFT - | 0x0000004FU << DDR_PHY_DX2GCR5_DXREFISELR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX2GCR5_OFFSET ,0xFFFFFFFFU ,0x09094F4FU); - /*############################################################################################################################ */ + /* + * Register : DX3GCR4 @ 0XFD080A10 - /*Register : DX2GCR6 @ 0XFD080918

+ * Byte lane VREF IOM (Used only by D4MU IOs) + * PSU_DDR_PHY_DX3GCR4_RESERVED_31_29 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX2GCR6_RESERVED_31_30 0x0 + * Byte Lane VREF Pad Enable + * PSU_DDR_PHY_DX3GCR4_DXREFPEN 0x0 - DRAM DQ VREF Select for Rank3 - PSU_DDR_PHY_DX2GCR6_DXDQVREFR3 0x9 + * Byte Lane Internal VREF Enable + * PSU_DDR_PHY_DX3GCR4_DXREFEEN 0x3 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX2GCR6_RESERVED_23_22 0x0 + * Byte Lane Single-End VREF Enable + * PSU_DDR_PHY_DX3GCR4_DXREFSEN 0x1 - DRAM DQ VREF Select for Rank2 - PSU_DDR_PHY_DX2GCR6_DXDQVREFR2 0x9 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX3GCR4_RESERVED_24 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX2GCR6_RESERVED_15_14 0x0 + * External VREF generator REFSEL range select + * PSU_DDR_PHY_DX3GCR4_DXREFESELRANGE 0x0 - DRAM DQ VREF Select for Rank1 - PSU_DDR_PHY_DX2GCR6_DXDQVREFR1 0x2b + * Byte Lane External VREF Select + * PSU_DDR_PHY_DX3GCR4_DXREFESEL 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX2GCR6_RESERVED_7_6 0x0 + * Single ended VREF generator REFSEL range select + * PSU_DDR_PHY_DX3GCR4_DXREFSSELRANGE 0x1 - DRAM DQ VREF Select for Rank0 - PSU_DDR_PHY_DX2GCR6_DXDQVREFR0 0x2b + * Byte Lane Single-End VREF Select + * PSU_DDR_PHY_DX3GCR4_DXREFSSEL 0x30 - DATX8 n General Configuration Register 6 - (OFFSET, MASK, VALUE) (0XFD080918, 0xFFFFFFFFU ,0x09092B2BU) - RegMask = (DDR_PHY_DX2GCR6_RESERVED_31_30_MASK | DDR_PHY_DX2GCR6_DXDQVREFR3_MASK | DDR_PHY_DX2GCR6_RESERVED_23_22_MASK | DDR_PHY_DX2GCR6_DXDQVREFR2_MASK | DDR_PHY_DX2GCR6_RESERVED_15_14_MASK | DDR_PHY_DX2GCR6_DXDQVREFR1_MASK | DDR_PHY_DX2GCR6_RESERVED_7_6_MASK | DDR_PHY_DX2GCR6_DXDQVREFR0_MASK | 0 ); + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX3GCR4_RESERVED_7_6 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX2GCR6_RESERVED_31_30_SHIFT - | 0x00000009U << DDR_PHY_DX2GCR6_DXDQVREFR3_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR6_RESERVED_23_22_SHIFT - | 0x00000009U << DDR_PHY_DX2GCR6_DXDQVREFR2_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR6_RESERVED_15_14_SHIFT - | 0x0000002BU << DDR_PHY_DX2GCR6_DXDQVREFR1_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR6_RESERVED_7_6_SHIFT - | 0x0000002BU << DDR_PHY_DX2GCR6_DXDQVREFR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX2GCR6_OFFSET ,0xFFFFFFFFU ,0x09092B2BU); - /*############################################################################################################################ */ + * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX3GCR4_DXREFIEN 0xf - /*Register : DX2LCDLR2 @ 0XFD080988

+ * VRMON control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX3GCR4_DXREFIMON 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX2LCDLR2_RESERVED_31_25 0x0 + * DATX8 n General Configuration Register 4 + * (OFFSET, MASK, VALUE) (0XFD080A10, 0xFFFFFFFFU ,0x0E00B03CU) + */ + PSU_Mask_Write(DDR_PHY_DX3GCR4_OFFSET, 0xFFFFFFFFU, 0x0E00B03CU); +/*##################################################################### */ - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX2LCDLR2_RESERVED_24_16 0x0 + /* + * Register : DX3GCR5 @ 0XFD080A14 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX2LCDLR2_RESERVED_15_9 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX3GCR5_RESERVED_31 0x0 - Read DQS Gating Delay - PSU_DDR_PHY_DX2LCDLR2_DQSGD 0x0 + * Byte Lane internal VREF Select for Rank 3 + * PSU_DDR_PHY_DX3GCR5_DXREFISELR3 0x9 - DATX8 n Local Calibrated Delay Line Register 2 - (OFFSET, MASK, VALUE) (0XFD080988, 0xFFFFFFFFU ,0x00000000U) - RegMask = (DDR_PHY_DX2LCDLR2_RESERVED_31_25_MASK | DDR_PHY_DX2LCDLR2_RESERVED_24_16_MASK | DDR_PHY_DX2LCDLR2_RESERVED_15_9_MASK | DDR_PHY_DX2LCDLR2_DQSGD_MASK | 0 ); + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX3GCR5_RESERVED_23 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX2LCDLR2_RESERVED_31_25_SHIFT - | 0x00000000U << DDR_PHY_DX2LCDLR2_RESERVED_24_16_SHIFT - | 0x00000000U << DDR_PHY_DX2LCDLR2_RESERVED_15_9_SHIFT - | 0x00000000U << DDR_PHY_DX2LCDLR2_DQSGD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX2LCDLR2_OFFSET ,0xFFFFFFFFU ,0x00000000U); - /*############################################################################################################################ */ + * Byte Lane internal VREF Select for Rank 2 + * PSU_DDR_PHY_DX3GCR5_DXREFISELR2 0x9 - /*Register : DX2GTR0 @ 0XFD0809C0

+ * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX3GCR5_RESERVED_15 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX2GTR0_RESERVED_31_24 0x0 + * Byte Lane internal VREF Select for Rank 1 + * PSU_DDR_PHY_DX3GCR5_DXREFISELR1 0x55 - DQ Write Path Latency Pipeline - PSU_DDR_PHY_DX2GTR0_WDQSL 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX3GCR5_RESERVED_7 0x0 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX2GTR0_RESERVED_23_20 0x0 + * Byte Lane internal VREF Select for Rank 0 + * PSU_DDR_PHY_DX3GCR5_DXREFISELR0 0x55 - Write Leveling System Latency - PSU_DDR_PHY_DX2GTR0_WLSL 0x2 + * DATX8 n General Configuration Register 5 + * (OFFSET, MASK, VALUE) (0XFD080A14, 0xFFFFFFFFU ,0x09095555U) + */ + PSU_Mask_Write(DDR_PHY_DX3GCR5_OFFSET, 0xFFFFFFFFU, 0x09095555U); +/*##################################################################### */ - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX2GTR0_RESERVED_15_13 0x0 + /* + * Register : DX3GCR6 @ 0XFD080A18 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX2GTR0_RESERVED_12_8 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX3GCR6_RESERVED_31_30 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX2GTR0_RESERVED_7_5 0x0 + * DRAM DQ VREF Select for Rank3 + * PSU_DDR_PHY_DX3GCR6_DXDQVREFR3 0x9 - DQS Gating System Latency - PSU_DDR_PHY_DX2GTR0_DGSL 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX3GCR6_RESERVED_23_22 0x0 - DATX8 n General Timing Register 0 - (OFFSET, MASK, VALUE) (0XFD0809C0, 0xFFFFFFFFU ,0x00020000U) - RegMask = (DDR_PHY_DX2GTR0_RESERVED_31_24_MASK | DDR_PHY_DX2GTR0_WDQSL_MASK | DDR_PHY_DX2GTR0_RESERVED_23_20_MASK | DDR_PHY_DX2GTR0_WLSL_MASK | DDR_PHY_DX2GTR0_RESERVED_15_13_MASK | DDR_PHY_DX2GTR0_RESERVED_12_8_MASK | DDR_PHY_DX2GTR0_RESERVED_7_5_MASK | DDR_PHY_DX2GTR0_DGSL_MASK | 0 ); + * DRAM DQ VREF Select for Rank2 + * PSU_DDR_PHY_DX3GCR6_DXDQVREFR2 0x9 - RegVal = ((0x00000000U << DDR_PHY_DX2GTR0_RESERVED_31_24_SHIFT - | 0x00000000U << DDR_PHY_DX2GTR0_WDQSL_SHIFT - | 0x00000000U << DDR_PHY_DX2GTR0_RESERVED_23_20_SHIFT - | 0x00000002U << DDR_PHY_DX2GTR0_WLSL_SHIFT - | 0x00000000U << DDR_PHY_DX2GTR0_RESERVED_15_13_SHIFT - | 0x00000000U << DDR_PHY_DX2GTR0_RESERVED_12_8_SHIFT - | 0x00000000U << DDR_PHY_DX2GTR0_RESERVED_7_5_SHIFT - | 0x00000000U << DDR_PHY_DX2GTR0_DGSL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX2GTR0_OFFSET ,0xFFFFFFFFU ,0x00020000U); - /*############################################################################################################################ */ + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX3GCR6_RESERVED_15_14 0x0 - /*Register : DX3GCR0 @ 0XFD080A00

+ * DRAM DQ VREF Select for Rank1 + * PSU_DDR_PHY_DX3GCR6_DXDQVREFR1 0x2b - Calibration Bypass - PSU_DDR_PHY_DX3GCR0_CALBYP 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX3GCR6_RESERVED_7_6 0x0 - Master Delay Line Enable - PSU_DDR_PHY_DX3GCR0_MDLEN 0x1 + * DRAM DQ VREF Select for Rank0 + * PSU_DDR_PHY_DX3GCR6_DXDQVREFR0 0x2b - Configurable ODT(TE) Phase Shift - PSU_DDR_PHY_DX3GCR0_CODTSHFT 0x0 + * DATX8 n General Configuration Register 6 + * (OFFSET, MASK, VALUE) (0XFD080A18, 0xFFFFFFFFU ,0x09092B2BU) + */ + PSU_Mask_Write(DDR_PHY_DX3GCR6_OFFSET, 0xFFFFFFFFU, 0x09092B2BU); +/*##################################################################### */ - DQS Duty Cycle Correction - PSU_DDR_PHY_DX3GCR0_DQSDCC 0x0 + /* + * Register : DX4GCR0 @ 0XFD080B00 - Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY - PSU_DDR_PHY_DX3GCR0_RDDLY 0x8 + * Calibration Bypass + * PSU_DDR_PHY_DX4GCR0_CALBYP 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX3GCR0_RESERVED_19_14 0x0 + * Master Delay Line Enable + * PSU_DDR_PHY_DX4GCR0_MDLEN 0x1 - DQSNSE Power Down Receiver - PSU_DDR_PHY_DX3GCR0_DQSNSEPDR 0x0 + * Configurable ODT(TE) Phase Shift + * PSU_DDR_PHY_DX4GCR0_CODTSHFT 0x0 - DQSSE Power Down Receiver - PSU_DDR_PHY_DX3GCR0_DQSSEPDR 0x0 + * DQS Duty Cycle Correction + * PSU_DDR_PHY_DX4GCR0_DQSDCC 0x0 - RTT On Additive Latency - PSU_DDR_PHY_DX3GCR0_RTTOAL 0x0 + * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY + * PSU_DDR_PHY_DX4GCR0_RDDLY 0x8 - RTT Output Hold - PSU_DDR_PHY_DX3GCR0_RTTOH 0x3 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX4GCR0_RESERVED_19_14 0x0 - Configurable PDR Phase Shift - PSU_DDR_PHY_DX3GCR0_CPDRSHFT 0x0 + * DQSNSE Power Down Receiver + * PSU_DDR_PHY_DX4GCR0_DQSNSEPDR 0x0 - DQSR Power Down - PSU_DDR_PHY_DX3GCR0_DQSRPD 0x0 + * DQSSE Power Down Receiver + * PSU_DDR_PHY_DX4GCR0_DQSSEPDR 0x0 - DQSG Power Down Receiver - PSU_DDR_PHY_DX3GCR0_DQSGPDR 0x0 + * RTT On Additive Latency + * PSU_DDR_PHY_DX4GCR0_RTTOAL 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX3GCR0_RESERVED_4 0x0 + * RTT Output Hold + * PSU_DDR_PHY_DX4GCR0_RTTOH 0x3 - DQSG On-Die Termination - PSU_DDR_PHY_DX3GCR0_DQSGODT 0x0 + * Configurable PDR Phase Shift + * PSU_DDR_PHY_DX4GCR0_CPDRSHFT 0x0 - DQSG Output Enable - PSU_DDR_PHY_DX3GCR0_DQSGOE 0x1 + * DQSR Power Down + * PSU_DDR_PHY_DX4GCR0_DQSRPD 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX3GCR0_RESERVED_1_0 0x0 + * DQSG Power Down Receiver + * PSU_DDR_PHY_DX4GCR0_DQSGPDR 0x0 - DATX8 n General Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD080A00, 0xFFFFFFFFU ,0x40800604U) - RegMask = (DDR_PHY_DX3GCR0_CALBYP_MASK | DDR_PHY_DX3GCR0_MDLEN_MASK | DDR_PHY_DX3GCR0_CODTSHFT_MASK | DDR_PHY_DX3GCR0_DQSDCC_MASK | DDR_PHY_DX3GCR0_RDDLY_MASK | DDR_PHY_DX3GCR0_RESERVED_19_14_MASK | DDR_PHY_DX3GCR0_DQSNSEPDR_MASK | DDR_PHY_DX3GCR0_DQSSEPDR_MASK | DDR_PHY_DX3GCR0_RTTOAL_MASK | DDR_PHY_DX3GCR0_RTTOH_MASK | DDR_PHY_DX3GCR0_CPDRSHFT_MASK | DDR_PHY_DX3GCR0_DQSRPD_MASK | DDR_PHY_DX3GCR0_DQSGPDR_MASK | DDR_PHY_DX3GCR0_RESERVED_4_MASK | DDR_PHY_DX3GCR0_DQSGODT_MASK | DDR_PHY_DX3GCR0_DQSGOE_MASK | DDR_PHY_DX3GCR0_RESERVED_1_0_MASK | 0 ); + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX4GCR0_RESERVED_4 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX3GCR0_CALBYP_SHIFT - | 0x00000001U << DDR_PHY_DX3GCR0_MDLEN_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR0_CODTSHFT_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR0_DQSDCC_SHIFT - | 0x00000008U << DDR_PHY_DX3GCR0_RDDLY_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR0_RESERVED_19_14_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR0_DQSNSEPDR_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR0_DQSSEPDR_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR0_RTTOAL_SHIFT - | 0x00000003U << DDR_PHY_DX3GCR0_RTTOH_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR0_CPDRSHFT_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR0_DQSRPD_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR0_DQSGPDR_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR0_RESERVED_4_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR0_DQSGODT_SHIFT - | 0x00000001U << DDR_PHY_DX3GCR0_DQSGOE_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR0_RESERVED_1_0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX3GCR0_OFFSET ,0xFFFFFFFFU ,0x40800604U); - /*############################################################################################################################ */ + * DQSG On-Die Termination + * PSU_DDR_PHY_DX4GCR0_DQSGODT 0x0 - /*Register : DX3GCR1 @ 0XFD080A04

+ * DQSG Output Enable + * PSU_DDR_PHY_DX4GCR0_DQSGOE 0x1 - Enables the PDR mode for DQ[7:0] - PSU_DDR_PHY_DX3GCR1_DXPDRMODE 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX4GCR0_RESERVED_1_0 0x0 - Reserved. Returns zeroes on reads. - PSU_DDR_PHY_DX3GCR1_RESERVED_15 0x0 + * DATX8 n General Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD080B00, 0xFFFFFFFFU ,0x40800604U) + */ + PSU_Mask_Write(DDR_PHY_DX4GCR0_OFFSET, 0xFFFFFFFFU, 0x40800604U); +/*##################################################################### */ - Select the delayed or non-delayed read data strobe # - PSU_DDR_PHY_DX3GCR1_QSNSEL 0x1 + /* + * Register : DX4GCR1 @ 0XFD080B04 - Select the delayed or non-delayed read data strobe - PSU_DDR_PHY_DX3GCR1_QSSEL 0x1 + * Enables the PDR mode for DQ[7:0] + * PSU_DDR_PHY_DX4GCR1_DXPDRMODE 0x0 - Enables Read Data Strobe in a byte lane - PSU_DDR_PHY_DX3GCR1_OEEN 0x1 + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX4GCR1_RESERVED_15 0x0 - Enables PDR in a byte lane - PSU_DDR_PHY_DX3GCR1_PDREN 0x1 + * Select the delayed or non-delayed read data strobe # + * PSU_DDR_PHY_DX4GCR1_QSNSEL 0x1 - Enables ODT/TE in a byte lane - PSU_DDR_PHY_DX3GCR1_TEEN 0x1 + * Select the delayed or non-delayed read data strobe + * PSU_DDR_PHY_DX4GCR1_QSSEL 0x1 - Enables Write Data strobe in a byte lane - PSU_DDR_PHY_DX3GCR1_DSEN 0x1 + * Enables Read Data Strobe in a byte lane + * PSU_DDR_PHY_DX4GCR1_OEEN 0x1 - Enables DM pin in a byte lane - PSU_DDR_PHY_DX3GCR1_DMEN 0x1 + * Enables PDR in a byte lane + * PSU_DDR_PHY_DX4GCR1_PDREN 0x1 - Enables DQ corresponding to each bit in a byte - PSU_DDR_PHY_DX3GCR1_DQEN 0xff + * Enables ODT/TE in a byte lane + * PSU_DDR_PHY_DX4GCR1_TEEN 0x1 - DATX8 n General Configuration Register 1 - (OFFSET, MASK, VALUE) (0XFD080A04, 0xFFFFFFFFU ,0x00007FFFU) - RegMask = (DDR_PHY_DX3GCR1_DXPDRMODE_MASK | DDR_PHY_DX3GCR1_RESERVED_15_MASK | DDR_PHY_DX3GCR1_QSNSEL_MASK | DDR_PHY_DX3GCR1_QSSEL_MASK | DDR_PHY_DX3GCR1_OEEN_MASK | DDR_PHY_DX3GCR1_PDREN_MASK | DDR_PHY_DX3GCR1_TEEN_MASK | DDR_PHY_DX3GCR1_DSEN_MASK | DDR_PHY_DX3GCR1_DMEN_MASK | DDR_PHY_DX3GCR1_DQEN_MASK | 0 ); + * Enables Write Data strobe in a byte lane + * PSU_DDR_PHY_DX4GCR1_DSEN 0x1 - RegVal = ((0x00000000U << DDR_PHY_DX3GCR1_DXPDRMODE_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR1_RESERVED_15_SHIFT - | 0x00000001U << DDR_PHY_DX3GCR1_QSNSEL_SHIFT - | 0x00000001U << DDR_PHY_DX3GCR1_QSSEL_SHIFT - | 0x00000001U << DDR_PHY_DX3GCR1_OEEN_SHIFT - | 0x00000001U << DDR_PHY_DX3GCR1_PDREN_SHIFT - | 0x00000001U << DDR_PHY_DX3GCR1_TEEN_SHIFT - | 0x00000001U << DDR_PHY_DX3GCR1_DSEN_SHIFT - | 0x00000001U << DDR_PHY_DX3GCR1_DMEN_SHIFT - | 0x000000FFU << DDR_PHY_DX3GCR1_DQEN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX3GCR1_OFFSET ,0xFFFFFFFFU ,0x00007FFFU); - /*############################################################################################################################ */ + * Enables DM pin in a byte lane + * PSU_DDR_PHY_DX4GCR1_DMEN 0x1 - /*Register : DX3GCR4 @ 0XFD080A10

+ * Enables DQ corresponding to each bit in a byte + * PSU_DDR_PHY_DX4GCR1_DQEN 0xff - Byte lane VREF IOM (Used only by D4MU IOs) - PSU_DDR_PHY_DX3GCR4_RESERVED_31_29 0x0 + * DATX8 n General Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD080B04, 0xFFFFFFFFU ,0x00007FFFU) + */ + PSU_Mask_Write(DDR_PHY_DX4GCR1_OFFSET, 0xFFFFFFFFU, 0x00007FFFU); +/*##################################################################### */ - Byte Lane VREF Pad Enable - PSU_DDR_PHY_DX3GCR4_DXREFPEN 0x0 + /* + * Register : DX4GCR4 @ 0XFD080B10 - Byte Lane Internal VREF Enable - PSU_DDR_PHY_DX3GCR4_DXREFEEN 0x3 + * Byte lane VREF IOM (Used only by D4MU IOs) + * PSU_DDR_PHY_DX4GCR4_RESERVED_31_29 0x0 - Byte Lane Single-End VREF Enable - PSU_DDR_PHY_DX3GCR4_DXREFSEN 0x1 + * Byte Lane VREF Pad Enable + * PSU_DDR_PHY_DX4GCR4_DXREFPEN 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX3GCR4_RESERVED_24 0x0 + * Byte Lane Internal VREF Enable + * PSU_DDR_PHY_DX4GCR4_DXREFEEN 0x3 - External VREF generator REFSEL range select - PSU_DDR_PHY_DX3GCR4_DXREFESELRANGE 0x0 + * Byte Lane Single-End VREF Enable + * PSU_DDR_PHY_DX4GCR4_DXREFSEN 0x1 - Byte Lane External VREF Select - PSU_DDR_PHY_DX3GCR4_DXREFESEL 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX4GCR4_RESERVED_24 0x0 - Single ended VREF generator REFSEL range select - PSU_DDR_PHY_DX3GCR4_DXREFSSELRANGE 0x1 + * External VREF generator REFSEL range select + * PSU_DDR_PHY_DX4GCR4_DXREFESELRANGE 0x0 - Byte Lane Single-End VREF Select - PSU_DDR_PHY_DX3GCR4_DXREFSSEL 0x30 + * Byte Lane External VREF Select + * PSU_DDR_PHY_DX4GCR4_DXREFESEL 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX3GCR4_RESERVED_7_6 0x0 + * Single ended VREF generator REFSEL range select + * PSU_DDR_PHY_DX4GCR4_DXREFSSELRANGE 0x1 - VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. - PSU_DDR_PHY_DX3GCR4_DXREFIEN 0xf + * Byte Lane Single-End VREF Select + * PSU_DDR_PHY_DX4GCR4_DXREFSSEL 0x30 - VRMON control for DQ IO (Single Ended) buffers of a byte lane. - PSU_DDR_PHY_DX3GCR4_DXREFIMON 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX4GCR4_RESERVED_7_6 0x0 - DATX8 n General Configuration Register 4 - (OFFSET, MASK, VALUE) (0XFD080A10, 0xFFFFFFFFU ,0x0E00B03CU) - RegMask = (DDR_PHY_DX3GCR4_RESERVED_31_29_MASK | DDR_PHY_DX3GCR4_DXREFPEN_MASK | DDR_PHY_DX3GCR4_DXREFEEN_MASK | DDR_PHY_DX3GCR4_DXREFSEN_MASK | DDR_PHY_DX3GCR4_RESERVED_24_MASK | DDR_PHY_DX3GCR4_DXREFESELRANGE_MASK | DDR_PHY_DX3GCR4_DXREFESEL_MASK | DDR_PHY_DX3GCR4_DXREFSSELRANGE_MASK | DDR_PHY_DX3GCR4_DXREFSSEL_MASK | DDR_PHY_DX3GCR4_RESERVED_7_6_MASK | DDR_PHY_DX3GCR4_DXREFIEN_MASK | DDR_PHY_DX3GCR4_DXREFIMON_MASK | 0 ); + * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX4GCR4_DXREFIEN 0xf - RegVal = ((0x00000000U << DDR_PHY_DX3GCR4_RESERVED_31_29_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR4_DXREFPEN_SHIFT - | 0x00000003U << DDR_PHY_DX3GCR4_DXREFEEN_SHIFT - | 0x00000001U << DDR_PHY_DX3GCR4_DXREFSEN_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR4_RESERVED_24_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR4_DXREFESELRANGE_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR4_DXREFESEL_SHIFT - | 0x00000001U << DDR_PHY_DX3GCR4_DXREFSSELRANGE_SHIFT - | 0x00000030U << DDR_PHY_DX3GCR4_DXREFSSEL_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR4_RESERVED_7_6_SHIFT - | 0x0000000FU << DDR_PHY_DX3GCR4_DXREFIEN_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR4_DXREFIMON_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX3GCR4_OFFSET ,0xFFFFFFFFU ,0x0E00B03CU); - /*############################################################################################################################ */ + * VRMON control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX4GCR4_DXREFIMON 0x0 - /*Register : DX3GCR5 @ 0XFD080A14

+ * DATX8 n General Configuration Register 4 + * (OFFSET, MASK, VALUE) (0XFD080B10, 0xFFFFFFFFU ,0x0E00B03CU) + */ + PSU_Mask_Write(DDR_PHY_DX4GCR4_OFFSET, 0xFFFFFFFFU, 0x0E00B03CU); +/*##################################################################### */ - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX3GCR5_RESERVED_31 0x0 + /* + * Register : DX4GCR5 @ 0XFD080B14 - Byte Lane internal VREF Select for Rank 3 - PSU_DDR_PHY_DX3GCR5_DXREFISELR3 0x9 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX4GCR5_RESERVED_31 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX3GCR5_RESERVED_23 0x0 + * Byte Lane internal VREF Select for Rank 3 + * PSU_DDR_PHY_DX4GCR5_DXREFISELR3 0x9 - Byte Lane internal VREF Select for Rank 2 - PSU_DDR_PHY_DX3GCR5_DXREFISELR2 0x9 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX4GCR5_RESERVED_23 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX3GCR5_RESERVED_15 0x0 + * Byte Lane internal VREF Select for Rank 2 + * PSU_DDR_PHY_DX4GCR5_DXREFISELR2 0x9 - Byte Lane internal VREF Select for Rank 1 - PSU_DDR_PHY_DX3GCR5_DXREFISELR1 0x4f + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX4GCR5_RESERVED_15 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX3GCR5_RESERVED_7 0x0 + * Byte Lane internal VREF Select for Rank 1 + * PSU_DDR_PHY_DX4GCR5_DXREFISELR1 0x55 - Byte Lane internal VREF Select for Rank 0 - PSU_DDR_PHY_DX3GCR5_DXREFISELR0 0x4f + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX4GCR5_RESERVED_7 0x0 - DATX8 n General Configuration Register 5 - (OFFSET, MASK, VALUE) (0XFD080A14, 0xFFFFFFFFU ,0x09094F4FU) - RegMask = (DDR_PHY_DX3GCR5_RESERVED_31_MASK | DDR_PHY_DX3GCR5_DXREFISELR3_MASK | DDR_PHY_DX3GCR5_RESERVED_23_MASK | DDR_PHY_DX3GCR5_DXREFISELR2_MASK | DDR_PHY_DX3GCR5_RESERVED_15_MASK | DDR_PHY_DX3GCR5_DXREFISELR1_MASK | DDR_PHY_DX3GCR5_RESERVED_7_MASK | DDR_PHY_DX3GCR5_DXREFISELR0_MASK | 0 ); + * Byte Lane internal VREF Select for Rank 0 + * PSU_DDR_PHY_DX4GCR5_DXREFISELR0 0x55 - RegVal = ((0x00000000U << DDR_PHY_DX3GCR5_RESERVED_31_SHIFT - | 0x00000009U << DDR_PHY_DX3GCR5_DXREFISELR3_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR5_RESERVED_23_SHIFT - | 0x00000009U << DDR_PHY_DX3GCR5_DXREFISELR2_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR5_RESERVED_15_SHIFT - | 0x0000004FU << DDR_PHY_DX3GCR5_DXREFISELR1_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR5_RESERVED_7_SHIFT - | 0x0000004FU << DDR_PHY_DX3GCR5_DXREFISELR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX3GCR5_OFFSET ,0xFFFFFFFFU ,0x09094F4FU); - /*############################################################################################################################ */ + * DATX8 n General Configuration Register 5 + * (OFFSET, MASK, VALUE) (0XFD080B14, 0xFFFFFFFFU ,0x09095555U) + */ + PSU_Mask_Write(DDR_PHY_DX4GCR5_OFFSET, 0xFFFFFFFFU, 0x09095555U); +/*##################################################################### */ - /*Register : DX3GCR6 @ 0XFD080A18

+ /* + * Register : DX4GCR6 @ 0XFD080B18 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX3GCR6_RESERVED_31_30 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX4GCR6_RESERVED_31_30 0x0 - DRAM DQ VREF Select for Rank3 - PSU_DDR_PHY_DX3GCR6_DXDQVREFR3 0x9 + * DRAM DQ VREF Select for Rank3 + * PSU_DDR_PHY_DX4GCR6_DXDQVREFR3 0x9 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX3GCR6_RESERVED_23_22 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX4GCR6_RESERVED_23_22 0x0 - DRAM DQ VREF Select for Rank2 - PSU_DDR_PHY_DX3GCR6_DXDQVREFR2 0x9 + * DRAM DQ VREF Select for Rank2 + * PSU_DDR_PHY_DX4GCR6_DXDQVREFR2 0x9 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX3GCR6_RESERVED_15_14 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX4GCR6_RESERVED_15_14 0x0 - DRAM DQ VREF Select for Rank1 - PSU_DDR_PHY_DX3GCR6_DXDQVREFR1 0x2b + * DRAM DQ VREF Select for Rank1 + * PSU_DDR_PHY_DX4GCR6_DXDQVREFR1 0x2b - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX3GCR6_RESERVED_7_6 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX4GCR6_RESERVED_7_6 0x0 - DRAM DQ VREF Select for Rank0 - PSU_DDR_PHY_DX3GCR6_DXDQVREFR0 0x2b + * DRAM DQ VREF Select for Rank0 + * PSU_DDR_PHY_DX4GCR6_DXDQVREFR0 0x2b - DATX8 n General Configuration Register 6 - (OFFSET, MASK, VALUE) (0XFD080A18, 0xFFFFFFFFU ,0x09092B2BU) - RegMask = (DDR_PHY_DX3GCR6_RESERVED_31_30_MASK | DDR_PHY_DX3GCR6_DXDQVREFR3_MASK | DDR_PHY_DX3GCR6_RESERVED_23_22_MASK | DDR_PHY_DX3GCR6_DXDQVREFR2_MASK | DDR_PHY_DX3GCR6_RESERVED_15_14_MASK | DDR_PHY_DX3GCR6_DXDQVREFR1_MASK | DDR_PHY_DX3GCR6_RESERVED_7_6_MASK | DDR_PHY_DX3GCR6_DXDQVREFR0_MASK | 0 ); + * DATX8 n General Configuration Register 6 + * (OFFSET, MASK, VALUE) (0XFD080B18, 0xFFFFFFFFU ,0x09092B2BU) + */ + PSU_Mask_Write(DDR_PHY_DX4GCR6_OFFSET, 0xFFFFFFFFU, 0x09092B2BU); +/*##################################################################### */ - RegVal = ((0x00000000U << DDR_PHY_DX3GCR6_RESERVED_31_30_SHIFT - | 0x00000009U << DDR_PHY_DX3GCR6_DXDQVREFR3_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR6_RESERVED_23_22_SHIFT - | 0x00000009U << DDR_PHY_DX3GCR6_DXDQVREFR2_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR6_RESERVED_15_14_SHIFT - | 0x0000002BU << DDR_PHY_DX3GCR6_DXDQVREFR1_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR6_RESERVED_7_6_SHIFT - | 0x0000002BU << DDR_PHY_DX3GCR6_DXDQVREFR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX3GCR6_OFFSET ,0xFFFFFFFFU ,0x09092B2BU); - /*############################################################################################################################ */ + /* + * Register : DX5GCR0 @ 0XFD080C00 - /*Register : DX3LCDLR2 @ 0XFD080A88

+ * Calibration Bypass + * PSU_DDR_PHY_DX5GCR0_CALBYP 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX3LCDLR2_RESERVED_31_25 0x0 + * Master Delay Line Enable + * PSU_DDR_PHY_DX5GCR0_MDLEN 0x1 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX3LCDLR2_RESERVED_24_16 0x0 + * Configurable ODT(TE) Phase Shift + * PSU_DDR_PHY_DX5GCR0_CODTSHFT 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX3LCDLR2_RESERVED_15_9 0x0 + * DQS Duty Cycle Correction + * PSU_DDR_PHY_DX5GCR0_DQSDCC 0x0 - Read DQS Gating Delay - PSU_DDR_PHY_DX3LCDLR2_DQSGD 0x0 + * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY + * PSU_DDR_PHY_DX5GCR0_RDDLY 0x8 - DATX8 n Local Calibrated Delay Line Register 2 - (OFFSET, MASK, VALUE) (0XFD080A88, 0xFFFFFFFFU ,0x00000000U) - RegMask = (DDR_PHY_DX3LCDLR2_RESERVED_31_25_MASK | DDR_PHY_DX3LCDLR2_RESERVED_24_16_MASK | DDR_PHY_DX3LCDLR2_RESERVED_15_9_MASK | DDR_PHY_DX3LCDLR2_DQSGD_MASK | 0 ); + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX5GCR0_RESERVED_19_14 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX3LCDLR2_RESERVED_31_25_SHIFT - | 0x00000000U << DDR_PHY_DX3LCDLR2_RESERVED_24_16_SHIFT - | 0x00000000U << DDR_PHY_DX3LCDLR2_RESERVED_15_9_SHIFT - | 0x00000000U << DDR_PHY_DX3LCDLR2_DQSGD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX3LCDLR2_OFFSET ,0xFFFFFFFFU ,0x00000000U); - /*############################################################################################################################ */ + * DQSNSE Power Down Receiver + * PSU_DDR_PHY_DX5GCR0_DQSNSEPDR 0x0 - /*Register : DX3GTR0 @ 0XFD080AC0

+ * DQSSE Power Down Receiver + * PSU_DDR_PHY_DX5GCR0_DQSSEPDR 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX3GTR0_RESERVED_31_24 0x0 + * RTT On Additive Latency + * PSU_DDR_PHY_DX5GCR0_RTTOAL 0x0 - DQ Write Path Latency Pipeline - PSU_DDR_PHY_DX3GTR0_WDQSL 0x0 + * RTT Output Hold + * PSU_DDR_PHY_DX5GCR0_RTTOH 0x3 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX3GTR0_RESERVED_23_20 0x0 + * Configurable PDR Phase Shift + * PSU_DDR_PHY_DX5GCR0_CPDRSHFT 0x0 - Write Leveling System Latency - PSU_DDR_PHY_DX3GTR0_WLSL 0x2 + * DQSR Power Down + * PSU_DDR_PHY_DX5GCR0_DQSRPD 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX3GTR0_RESERVED_15_13 0x0 + * DQSG Power Down Receiver + * PSU_DDR_PHY_DX5GCR0_DQSGPDR 0x0 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX3GTR0_RESERVED_12_8 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX5GCR0_RESERVED_4 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX3GTR0_RESERVED_7_5 0x0 + * DQSG On-Die Termination + * PSU_DDR_PHY_DX5GCR0_DQSGODT 0x0 - DQS Gating System Latency - PSU_DDR_PHY_DX3GTR0_DGSL 0x0 + * DQSG Output Enable + * PSU_DDR_PHY_DX5GCR0_DQSGOE 0x1 - DATX8 n General Timing Register 0 - (OFFSET, MASK, VALUE) (0XFD080AC0, 0xFFFFFFFFU ,0x00020000U) - RegMask = (DDR_PHY_DX3GTR0_RESERVED_31_24_MASK | DDR_PHY_DX3GTR0_WDQSL_MASK | DDR_PHY_DX3GTR0_RESERVED_23_20_MASK | DDR_PHY_DX3GTR0_WLSL_MASK | DDR_PHY_DX3GTR0_RESERVED_15_13_MASK | DDR_PHY_DX3GTR0_RESERVED_12_8_MASK | DDR_PHY_DX3GTR0_RESERVED_7_5_MASK | DDR_PHY_DX3GTR0_DGSL_MASK | 0 ); + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX5GCR0_RESERVED_1_0 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX3GTR0_RESERVED_31_24_SHIFT - | 0x00000000U << DDR_PHY_DX3GTR0_WDQSL_SHIFT - | 0x00000000U << DDR_PHY_DX3GTR0_RESERVED_23_20_SHIFT - | 0x00000002U << DDR_PHY_DX3GTR0_WLSL_SHIFT - | 0x00000000U << DDR_PHY_DX3GTR0_RESERVED_15_13_SHIFT - | 0x00000000U << DDR_PHY_DX3GTR0_RESERVED_12_8_SHIFT - | 0x00000000U << DDR_PHY_DX3GTR0_RESERVED_7_5_SHIFT - | 0x00000000U << DDR_PHY_DX3GTR0_DGSL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX3GTR0_OFFSET ,0xFFFFFFFFU ,0x00020000U); - /*############################################################################################################################ */ + * DATX8 n General Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD080C00, 0xFFFFFFFFU ,0x40800604U) + */ + PSU_Mask_Write(DDR_PHY_DX5GCR0_OFFSET, 0xFFFFFFFFU, 0x40800604U); +/*##################################################################### */ - /*Register : DX4GCR0 @ 0XFD080B00

+ /* + * Register : DX5GCR1 @ 0XFD080C04 - Calibration Bypass - PSU_DDR_PHY_DX4GCR0_CALBYP 0x0 + * Enables the PDR mode for DQ[7:0] + * PSU_DDR_PHY_DX5GCR1_DXPDRMODE 0x0 - Master Delay Line Enable - PSU_DDR_PHY_DX4GCR0_MDLEN 0x1 + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX5GCR1_RESERVED_15 0x0 - Configurable ODT(TE) Phase Shift - PSU_DDR_PHY_DX4GCR0_CODTSHFT 0x0 + * Select the delayed or non-delayed read data strobe # + * PSU_DDR_PHY_DX5GCR1_QSNSEL 0x1 - DQS Duty Cycle Correction - PSU_DDR_PHY_DX4GCR0_DQSDCC 0x0 + * Select the delayed or non-delayed read data strobe + * PSU_DDR_PHY_DX5GCR1_QSSEL 0x1 - Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY - PSU_DDR_PHY_DX4GCR0_RDDLY 0x8 + * Enables Read Data Strobe in a byte lane + * PSU_DDR_PHY_DX5GCR1_OEEN 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX4GCR0_RESERVED_19_14 0x0 + * Enables PDR in a byte lane + * PSU_DDR_PHY_DX5GCR1_PDREN 0x1 - DQSNSE Power Down Receiver - PSU_DDR_PHY_DX4GCR0_DQSNSEPDR 0x0 + * Enables ODT/TE in a byte lane + * PSU_DDR_PHY_DX5GCR1_TEEN 0x1 - DQSSE Power Down Receiver - PSU_DDR_PHY_DX4GCR0_DQSSEPDR 0x0 + * Enables Write Data strobe in a byte lane + * PSU_DDR_PHY_DX5GCR1_DSEN 0x1 - RTT On Additive Latency - PSU_DDR_PHY_DX4GCR0_RTTOAL 0x0 + * Enables DM pin in a byte lane + * PSU_DDR_PHY_DX5GCR1_DMEN 0x1 - RTT Output Hold - PSU_DDR_PHY_DX4GCR0_RTTOH 0x3 + * Enables DQ corresponding to each bit in a byte + * PSU_DDR_PHY_DX5GCR1_DQEN 0xff - Configurable PDR Phase Shift - PSU_DDR_PHY_DX4GCR0_CPDRSHFT 0x0 + * DATX8 n General Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD080C04, 0xFFFFFFFFU ,0x00007FFFU) + */ + PSU_Mask_Write(DDR_PHY_DX5GCR1_OFFSET, 0xFFFFFFFFU, 0x00007FFFU); +/*##################################################################### */ - DQSR Power Down - PSU_DDR_PHY_DX4GCR0_DQSRPD 0x0 + /* + * Register : DX5GCR4 @ 0XFD080C10 - DQSG Power Down Receiver - PSU_DDR_PHY_DX4GCR0_DQSGPDR 0x0 + * Byte lane VREF IOM (Used only by D4MU IOs) + * PSU_DDR_PHY_DX5GCR4_RESERVED_31_29 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX4GCR0_RESERVED_4 0x0 + * Byte Lane VREF Pad Enable + * PSU_DDR_PHY_DX5GCR4_DXREFPEN 0x0 - DQSG On-Die Termination - PSU_DDR_PHY_DX4GCR0_DQSGODT 0x0 + * Byte Lane Internal VREF Enable + * PSU_DDR_PHY_DX5GCR4_DXREFEEN 0x3 - DQSG Output Enable - PSU_DDR_PHY_DX4GCR0_DQSGOE 0x1 + * Byte Lane Single-End VREF Enable + * PSU_DDR_PHY_DX5GCR4_DXREFSEN 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX4GCR0_RESERVED_1_0 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX5GCR4_RESERVED_24 0x0 - DATX8 n General Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD080B00, 0xFFFFFFFFU ,0x40800604U) - RegMask = (DDR_PHY_DX4GCR0_CALBYP_MASK | DDR_PHY_DX4GCR0_MDLEN_MASK | DDR_PHY_DX4GCR0_CODTSHFT_MASK | DDR_PHY_DX4GCR0_DQSDCC_MASK | DDR_PHY_DX4GCR0_RDDLY_MASK | DDR_PHY_DX4GCR0_RESERVED_19_14_MASK | DDR_PHY_DX4GCR0_DQSNSEPDR_MASK | DDR_PHY_DX4GCR0_DQSSEPDR_MASK | DDR_PHY_DX4GCR0_RTTOAL_MASK | DDR_PHY_DX4GCR0_RTTOH_MASK | DDR_PHY_DX4GCR0_CPDRSHFT_MASK | DDR_PHY_DX4GCR0_DQSRPD_MASK | DDR_PHY_DX4GCR0_DQSGPDR_MASK | DDR_PHY_DX4GCR0_RESERVED_4_MASK | DDR_PHY_DX4GCR0_DQSGODT_MASK | DDR_PHY_DX4GCR0_DQSGOE_MASK | DDR_PHY_DX4GCR0_RESERVED_1_0_MASK | 0 ); + * External VREF generator REFSEL range select + * PSU_DDR_PHY_DX5GCR4_DXREFESELRANGE 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX4GCR0_CALBYP_SHIFT - | 0x00000001U << DDR_PHY_DX4GCR0_MDLEN_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR0_CODTSHFT_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR0_DQSDCC_SHIFT - | 0x00000008U << DDR_PHY_DX4GCR0_RDDLY_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR0_RESERVED_19_14_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR0_DQSNSEPDR_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR0_DQSSEPDR_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR0_RTTOAL_SHIFT - | 0x00000003U << DDR_PHY_DX4GCR0_RTTOH_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR0_CPDRSHFT_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR0_DQSRPD_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR0_DQSGPDR_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR0_RESERVED_4_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR0_DQSGODT_SHIFT - | 0x00000001U << DDR_PHY_DX4GCR0_DQSGOE_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR0_RESERVED_1_0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX4GCR0_OFFSET ,0xFFFFFFFFU ,0x40800604U); - /*############################################################################################################################ */ + * Byte Lane External VREF Select + * PSU_DDR_PHY_DX5GCR4_DXREFESEL 0x0 - /*Register : DX4GCR1 @ 0XFD080B04

+ * Single ended VREF generator REFSEL range select + * PSU_DDR_PHY_DX5GCR4_DXREFSSELRANGE 0x1 - Enables the PDR mode for DQ[7:0] - PSU_DDR_PHY_DX4GCR1_DXPDRMODE 0x0 + * Byte Lane Single-End VREF Select + * PSU_DDR_PHY_DX5GCR4_DXREFSSEL 0x30 - Reserved. Returns zeroes on reads. - PSU_DDR_PHY_DX4GCR1_RESERVED_15 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX5GCR4_RESERVED_7_6 0x0 - Select the delayed or non-delayed read data strobe # - PSU_DDR_PHY_DX4GCR1_QSNSEL 0x1 + * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX5GCR4_DXREFIEN 0xf - Select the delayed or non-delayed read data strobe - PSU_DDR_PHY_DX4GCR1_QSSEL 0x1 + * VRMON control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX5GCR4_DXREFIMON 0x0 - Enables Read Data Strobe in a byte lane - PSU_DDR_PHY_DX4GCR1_OEEN 0x1 + * DATX8 n General Configuration Register 4 + * (OFFSET, MASK, VALUE) (0XFD080C10, 0xFFFFFFFFU ,0x0E00B03CU) + */ + PSU_Mask_Write(DDR_PHY_DX5GCR4_OFFSET, 0xFFFFFFFFU, 0x0E00B03CU); +/*##################################################################### */ - Enables PDR in a byte lane - PSU_DDR_PHY_DX4GCR1_PDREN 0x1 + /* + * Register : DX5GCR5 @ 0XFD080C14 - Enables ODT/TE in a byte lane - PSU_DDR_PHY_DX4GCR1_TEEN 0x1 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX5GCR5_RESERVED_31 0x0 - Enables Write Data strobe in a byte lane - PSU_DDR_PHY_DX4GCR1_DSEN 0x1 + * Byte Lane internal VREF Select for Rank 3 + * PSU_DDR_PHY_DX5GCR5_DXREFISELR3 0x9 - Enables DM pin in a byte lane - PSU_DDR_PHY_DX4GCR1_DMEN 0x1 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX5GCR5_RESERVED_23 0x0 - Enables DQ corresponding to each bit in a byte - PSU_DDR_PHY_DX4GCR1_DQEN 0xff + * Byte Lane internal VREF Select for Rank 2 + * PSU_DDR_PHY_DX5GCR5_DXREFISELR2 0x9 - DATX8 n General Configuration Register 1 - (OFFSET, MASK, VALUE) (0XFD080B04, 0xFFFFFFFFU ,0x00007FFFU) - RegMask = (DDR_PHY_DX4GCR1_DXPDRMODE_MASK | DDR_PHY_DX4GCR1_RESERVED_15_MASK | DDR_PHY_DX4GCR1_QSNSEL_MASK | DDR_PHY_DX4GCR1_QSSEL_MASK | DDR_PHY_DX4GCR1_OEEN_MASK | DDR_PHY_DX4GCR1_PDREN_MASK | DDR_PHY_DX4GCR1_TEEN_MASK | DDR_PHY_DX4GCR1_DSEN_MASK | DDR_PHY_DX4GCR1_DMEN_MASK | DDR_PHY_DX4GCR1_DQEN_MASK | 0 ); + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX5GCR5_RESERVED_15 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX4GCR1_DXPDRMODE_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR1_RESERVED_15_SHIFT - | 0x00000001U << DDR_PHY_DX4GCR1_QSNSEL_SHIFT - | 0x00000001U << DDR_PHY_DX4GCR1_QSSEL_SHIFT - | 0x00000001U << DDR_PHY_DX4GCR1_OEEN_SHIFT - | 0x00000001U << DDR_PHY_DX4GCR1_PDREN_SHIFT - | 0x00000001U << DDR_PHY_DX4GCR1_TEEN_SHIFT - | 0x00000001U << DDR_PHY_DX4GCR1_DSEN_SHIFT - | 0x00000001U << DDR_PHY_DX4GCR1_DMEN_SHIFT - | 0x000000FFU << DDR_PHY_DX4GCR1_DQEN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX4GCR1_OFFSET ,0xFFFFFFFFU ,0x00007FFFU); - /*############################################################################################################################ */ + * Byte Lane internal VREF Select for Rank 1 + * PSU_DDR_PHY_DX5GCR5_DXREFISELR1 0x55 - /*Register : DX4GCR4 @ 0XFD080B10

+ * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX5GCR5_RESERVED_7 0x0 - Byte lane VREF IOM (Used only by D4MU IOs) - PSU_DDR_PHY_DX4GCR4_RESERVED_31_29 0x0 + * Byte Lane internal VREF Select for Rank 0 + * PSU_DDR_PHY_DX5GCR5_DXREFISELR0 0x55 - Byte Lane VREF Pad Enable - PSU_DDR_PHY_DX4GCR4_DXREFPEN 0x0 + * DATX8 n General Configuration Register 5 + * (OFFSET, MASK, VALUE) (0XFD080C14, 0xFFFFFFFFU ,0x09095555U) + */ + PSU_Mask_Write(DDR_PHY_DX5GCR5_OFFSET, 0xFFFFFFFFU, 0x09095555U); +/*##################################################################### */ - Byte Lane Internal VREF Enable - PSU_DDR_PHY_DX4GCR4_DXREFEEN 0x3 + /* + * Register : DX5GCR6 @ 0XFD080C18 - Byte Lane Single-End VREF Enable - PSU_DDR_PHY_DX4GCR4_DXREFSEN 0x1 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX5GCR6_RESERVED_31_30 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX4GCR4_RESERVED_24 0x0 + * DRAM DQ VREF Select for Rank3 + * PSU_DDR_PHY_DX5GCR6_DXDQVREFR3 0x9 - External VREF generator REFSEL range select - PSU_DDR_PHY_DX4GCR4_DXREFESELRANGE 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX5GCR6_RESERVED_23_22 0x0 - Byte Lane External VREF Select - PSU_DDR_PHY_DX4GCR4_DXREFESEL 0x0 + * DRAM DQ VREF Select for Rank2 + * PSU_DDR_PHY_DX5GCR6_DXDQVREFR2 0x9 - Single ended VREF generator REFSEL range select - PSU_DDR_PHY_DX4GCR4_DXREFSSELRANGE 0x1 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX5GCR6_RESERVED_15_14 0x0 - Byte Lane Single-End VREF Select - PSU_DDR_PHY_DX4GCR4_DXREFSSEL 0x30 + * DRAM DQ VREF Select for Rank1 + * PSU_DDR_PHY_DX5GCR6_DXDQVREFR1 0x2b - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX4GCR4_RESERVED_7_6 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX5GCR6_RESERVED_7_6 0x0 - VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. - PSU_DDR_PHY_DX4GCR4_DXREFIEN 0xf + * DRAM DQ VREF Select for Rank0 + * PSU_DDR_PHY_DX5GCR6_DXDQVREFR0 0x2b - VRMON control for DQ IO (Single Ended) buffers of a byte lane. - PSU_DDR_PHY_DX4GCR4_DXREFIMON 0x0 + * DATX8 n General Configuration Register 6 + * (OFFSET, MASK, VALUE) (0XFD080C18, 0xFFFFFFFFU ,0x09092B2BU) + */ + PSU_Mask_Write(DDR_PHY_DX5GCR6_OFFSET, 0xFFFFFFFFU, 0x09092B2BU); +/*##################################################################### */ - DATX8 n General Configuration Register 4 - (OFFSET, MASK, VALUE) (0XFD080B10, 0xFFFFFFFFU ,0x0E00B03CU) - RegMask = (DDR_PHY_DX4GCR4_RESERVED_31_29_MASK | DDR_PHY_DX4GCR4_DXREFPEN_MASK | DDR_PHY_DX4GCR4_DXREFEEN_MASK | DDR_PHY_DX4GCR4_DXREFSEN_MASK | DDR_PHY_DX4GCR4_RESERVED_24_MASK | DDR_PHY_DX4GCR4_DXREFESELRANGE_MASK | DDR_PHY_DX4GCR4_DXREFESEL_MASK | DDR_PHY_DX4GCR4_DXREFSSELRANGE_MASK | DDR_PHY_DX4GCR4_DXREFSSEL_MASK | DDR_PHY_DX4GCR4_RESERVED_7_6_MASK | DDR_PHY_DX4GCR4_DXREFIEN_MASK | DDR_PHY_DX4GCR4_DXREFIMON_MASK | 0 ); + /* + * Register : DX6GCR0 @ 0XFD080D00 - RegVal = ((0x00000000U << DDR_PHY_DX4GCR4_RESERVED_31_29_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR4_DXREFPEN_SHIFT - | 0x00000003U << DDR_PHY_DX4GCR4_DXREFEEN_SHIFT - | 0x00000001U << DDR_PHY_DX4GCR4_DXREFSEN_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR4_RESERVED_24_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR4_DXREFESELRANGE_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR4_DXREFESEL_SHIFT - | 0x00000001U << DDR_PHY_DX4GCR4_DXREFSSELRANGE_SHIFT - | 0x00000030U << DDR_PHY_DX4GCR4_DXREFSSEL_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR4_RESERVED_7_6_SHIFT - | 0x0000000FU << DDR_PHY_DX4GCR4_DXREFIEN_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR4_DXREFIMON_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX4GCR4_OFFSET ,0xFFFFFFFFU ,0x0E00B03CU); - /*############################################################################################################################ */ + * Calibration Bypass + * PSU_DDR_PHY_DX6GCR0_CALBYP 0x0 - /*Register : DX4GCR5 @ 0XFD080B14

+ * Master Delay Line Enable + * PSU_DDR_PHY_DX6GCR0_MDLEN 0x1 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX4GCR5_RESERVED_31 0x0 + * Configurable ODT(TE) Phase Shift + * PSU_DDR_PHY_DX6GCR0_CODTSHFT 0x0 - Byte Lane internal VREF Select for Rank 3 - PSU_DDR_PHY_DX4GCR5_DXREFISELR3 0x9 + * DQS Duty Cycle Correction + * PSU_DDR_PHY_DX6GCR0_DQSDCC 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX4GCR5_RESERVED_23 0x0 + * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY + * PSU_DDR_PHY_DX6GCR0_RDDLY 0x8 - Byte Lane internal VREF Select for Rank 2 - PSU_DDR_PHY_DX4GCR5_DXREFISELR2 0x9 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX6GCR0_RESERVED_19_14 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX4GCR5_RESERVED_15 0x0 + * DQSNSE Power Down Receiver + * PSU_DDR_PHY_DX6GCR0_DQSNSEPDR 0x0 - Byte Lane internal VREF Select for Rank 1 - PSU_DDR_PHY_DX4GCR5_DXREFISELR1 0x4f + * DQSSE Power Down Receiver + * PSU_DDR_PHY_DX6GCR0_DQSSEPDR 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX4GCR5_RESERVED_7 0x0 + * RTT On Additive Latency + * PSU_DDR_PHY_DX6GCR0_RTTOAL 0x0 - Byte Lane internal VREF Select for Rank 0 - PSU_DDR_PHY_DX4GCR5_DXREFISELR0 0x4f + * RTT Output Hold + * PSU_DDR_PHY_DX6GCR0_RTTOH 0x3 - DATX8 n General Configuration Register 5 - (OFFSET, MASK, VALUE) (0XFD080B14, 0xFFFFFFFFU ,0x09094F4FU) - RegMask = (DDR_PHY_DX4GCR5_RESERVED_31_MASK | DDR_PHY_DX4GCR5_DXREFISELR3_MASK | DDR_PHY_DX4GCR5_RESERVED_23_MASK | DDR_PHY_DX4GCR5_DXREFISELR2_MASK | DDR_PHY_DX4GCR5_RESERVED_15_MASK | DDR_PHY_DX4GCR5_DXREFISELR1_MASK | DDR_PHY_DX4GCR5_RESERVED_7_MASK | DDR_PHY_DX4GCR5_DXREFISELR0_MASK | 0 ); + * Configurable PDR Phase Shift + * PSU_DDR_PHY_DX6GCR0_CPDRSHFT 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX4GCR5_RESERVED_31_SHIFT - | 0x00000009U << DDR_PHY_DX4GCR5_DXREFISELR3_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR5_RESERVED_23_SHIFT - | 0x00000009U << DDR_PHY_DX4GCR5_DXREFISELR2_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR5_RESERVED_15_SHIFT - | 0x0000004FU << DDR_PHY_DX4GCR5_DXREFISELR1_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR5_RESERVED_7_SHIFT - | 0x0000004FU << DDR_PHY_DX4GCR5_DXREFISELR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX4GCR5_OFFSET ,0xFFFFFFFFU ,0x09094F4FU); - /*############################################################################################################################ */ + * DQSR Power Down + * PSU_DDR_PHY_DX6GCR0_DQSRPD 0x0 - /*Register : DX4GCR6 @ 0XFD080B18

+ * DQSG Power Down Receiver + * PSU_DDR_PHY_DX6GCR0_DQSGPDR 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX4GCR6_RESERVED_31_30 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX6GCR0_RESERVED_4 0x0 - DRAM DQ VREF Select for Rank3 - PSU_DDR_PHY_DX4GCR6_DXDQVREFR3 0x9 + * DQSG On-Die Termination + * PSU_DDR_PHY_DX6GCR0_DQSGODT 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX4GCR6_RESERVED_23_22 0x0 + * DQSG Output Enable + * PSU_DDR_PHY_DX6GCR0_DQSGOE 0x1 - DRAM DQ VREF Select for Rank2 - PSU_DDR_PHY_DX4GCR6_DXDQVREFR2 0x9 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX6GCR0_RESERVED_1_0 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX4GCR6_RESERVED_15_14 0x0 + * DATX8 n General Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD080D00, 0xFFFFFFFFU ,0x40800604U) + */ + PSU_Mask_Write(DDR_PHY_DX6GCR0_OFFSET, 0xFFFFFFFFU, 0x40800604U); +/*##################################################################### */ - DRAM DQ VREF Select for Rank1 - PSU_DDR_PHY_DX4GCR6_DXDQVREFR1 0x2b + /* + * Register : DX6GCR1 @ 0XFD080D04 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX4GCR6_RESERVED_7_6 0x0 + * Enables the PDR mode for DQ[7:0] + * PSU_DDR_PHY_DX6GCR1_DXPDRMODE 0x0 - DRAM DQ VREF Select for Rank0 - PSU_DDR_PHY_DX4GCR6_DXDQVREFR0 0x2b + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX6GCR1_RESERVED_15 0x0 - DATX8 n General Configuration Register 6 - (OFFSET, MASK, VALUE) (0XFD080B18, 0xFFFFFFFFU ,0x09092B2BU) - RegMask = (DDR_PHY_DX4GCR6_RESERVED_31_30_MASK | DDR_PHY_DX4GCR6_DXDQVREFR3_MASK | DDR_PHY_DX4GCR6_RESERVED_23_22_MASK | DDR_PHY_DX4GCR6_DXDQVREFR2_MASK | DDR_PHY_DX4GCR6_RESERVED_15_14_MASK | DDR_PHY_DX4GCR6_DXDQVREFR1_MASK | DDR_PHY_DX4GCR6_RESERVED_7_6_MASK | DDR_PHY_DX4GCR6_DXDQVREFR0_MASK | 0 ); + * Select the delayed or non-delayed read data strobe # + * PSU_DDR_PHY_DX6GCR1_QSNSEL 0x1 - RegVal = ((0x00000000U << DDR_PHY_DX4GCR6_RESERVED_31_30_SHIFT - | 0x00000009U << DDR_PHY_DX4GCR6_DXDQVREFR3_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR6_RESERVED_23_22_SHIFT - | 0x00000009U << DDR_PHY_DX4GCR6_DXDQVREFR2_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR6_RESERVED_15_14_SHIFT - | 0x0000002BU << DDR_PHY_DX4GCR6_DXDQVREFR1_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR6_RESERVED_7_6_SHIFT - | 0x0000002BU << DDR_PHY_DX4GCR6_DXDQVREFR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX4GCR6_OFFSET ,0xFFFFFFFFU ,0x09092B2BU); - /*############################################################################################################################ */ + * Select the delayed or non-delayed read data strobe + * PSU_DDR_PHY_DX6GCR1_QSSEL 0x1 - /*Register : DX4LCDLR2 @ 0XFD080B88

+ * Enables Read Data Strobe in a byte lane + * PSU_DDR_PHY_DX6GCR1_OEEN 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX4LCDLR2_RESERVED_31_25 0x0 + * Enables PDR in a byte lane + * PSU_DDR_PHY_DX6GCR1_PDREN 0x1 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX4LCDLR2_RESERVED_24_16 0x0 + * Enables ODT/TE in a byte lane + * PSU_DDR_PHY_DX6GCR1_TEEN 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX4LCDLR2_RESERVED_15_9 0x0 + * Enables Write Data strobe in a byte lane + * PSU_DDR_PHY_DX6GCR1_DSEN 0x1 - Read DQS Gating Delay - PSU_DDR_PHY_DX4LCDLR2_DQSGD 0x0 + * Enables DM pin in a byte lane + * PSU_DDR_PHY_DX6GCR1_DMEN 0x1 - DATX8 n Local Calibrated Delay Line Register 2 - (OFFSET, MASK, VALUE) (0XFD080B88, 0xFFFFFFFFU ,0x00000000U) - RegMask = (DDR_PHY_DX4LCDLR2_RESERVED_31_25_MASK | DDR_PHY_DX4LCDLR2_RESERVED_24_16_MASK | DDR_PHY_DX4LCDLR2_RESERVED_15_9_MASK | DDR_PHY_DX4LCDLR2_DQSGD_MASK | 0 ); + * Enables DQ corresponding to each bit in a byte + * PSU_DDR_PHY_DX6GCR1_DQEN 0xff - RegVal = ((0x00000000U << DDR_PHY_DX4LCDLR2_RESERVED_31_25_SHIFT - | 0x00000000U << DDR_PHY_DX4LCDLR2_RESERVED_24_16_SHIFT - | 0x00000000U << DDR_PHY_DX4LCDLR2_RESERVED_15_9_SHIFT - | 0x00000000U << DDR_PHY_DX4LCDLR2_DQSGD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX4LCDLR2_OFFSET ,0xFFFFFFFFU ,0x00000000U); - /*############################################################################################################################ */ + * DATX8 n General Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD080D04, 0xFFFFFFFFU ,0x00007FFFU) + */ + PSU_Mask_Write(DDR_PHY_DX6GCR1_OFFSET, 0xFFFFFFFFU, 0x00007FFFU); +/*##################################################################### */ - /*Register : DX4GTR0 @ 0XFD080BC0

+ /* + * Register : DX6GCR4 @ 0XFD080D10 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX4GTR0_RESERVED_31_24 0x0 + * Byte lane VREF IOM (Used only by D4MU IOs) + * PSU_DDR_PHY_DX6GCR4_RESERVED_31_29 0x0 - DQ Write Path Latency Pipeline - PSU_DDR_PHY_DX4GTR0_WDQSL 0x0 + * Byte Lane VREF Pad Enable + * PSU_DDR_PHY_DX6GCR4_DXREFPEN 0x0 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX4GTR0_RESERVED_23_20 0x0 + * Byte Lane Internal VREF Enable + * PSU_DDR_PHY_DX6GCR4_DXREFEEN 0x3 - Write Leveling System Latency - PSU_DDR_PHY_DX4GTR0_WLSL 0x2 + * Byte Lane Single-End VREF Enable + * PSU_DDR_PHY_DX6GCR4_DXREFSEN 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX4GTR0_RESERVED_15_13 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX6GCR4_RESERVED_24 0x0 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX4GTR0_RESERVED_12_8 0x0 + * External VREF generator REFSEL range select + * PSU_DDR_PHY_DX6GCR4_DXREFESELRANGE 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX4GTR0_RESERVED_7_5 0x0 + * Byte Lane External VREF Select + * PSU_DDR_PHY_DX6GCR4_DXREFESEL 0x0 - DQS Gating System Latency - PSU_DDR_PHY_DX4GTR0_DGSL 0x0 + * Single ended VREF generator REFSEL range select + * PSU_DDR_PHY_DX6GCR4_DXREFSSELRANGE 0x1 - DATX8 n General Timing Register 0 - (OFFSET, MASK, VALUE) (0XFD080BC0, 0xFFFFFFFFU ,0x00020000U) - RegMask = (DDR_PHY_DX4GTR0_RESERVED_31_24_MASK | DDR_PHY_DX4GTR0_WDQSL_MASK | DDR_PHY_DX4GTR0_RESERVED_23_20_MASK | DDR_PHY_DX4GTR0_WLSL_MASK | DDR_PHY_DX4GTR0_RESERVED_15_13_MASK | DDR_PHY_DX4GTR0_RESERVED_12_8_MASK | DDR_PHY_DX4GTR0_RESERVED_7_5_MASK | DDR_PHY_DX4GTR0_DGSL_MASK | 0 ); + * Byte Lane Single-End VREF Select + * PSU_DDR_PHY_DX6GCR4_DXREFSSEL 0x30 - RegVal = ((0x00000000U << DDR_PHY_DX4GTR0_RESERVED_31_24_SHIFT - | 0x00000000U << DDR_PHY_DX4GTR0_WDQSL_SHIFT - | 0x00000000U << DDR_PHY_DX4GTR0_RESERVED_23_20_SHIFT - | 0x00000002U << DDR_PHY_DX4GTR0_WLSL_SHIFT - | 0x00000000U << DDR_PHY_DX4GTR0_RESERVED_15_13_SHIFT - | 0x00000000U << DDR_PHY_DX4GTR0_RESERVED_12_8_SHIFT - | 0x00000000U << DDR_PHY_DX4GTR0_RESERVED_7_5_SHIFT - | 0x00000000U << DDR_PHY_DX4GTR0_DGSL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX4GTR0_OFFSET ,0xFFFFFFFFU ,0x00020000U); - /*############################################################################################################################ */ + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX6GCR4_RESERVED_7_6 0x0 - /*Register : DX5GCR0 @ 0XFD080C00

+ * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX6GCR4_DXREFIEN 0xf - Calibration Bypass - PSU_DDR_PHY_DX5GCR0_CALBYP 0x0 + * VRMON control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX6GCR4_DXREFIMON 0x0 - Master Delay Line Enable - PSU_DDR_PHY_DX5GCR0_MDLEN 0x1 + * DATX8 n General Configuration Register 4 + * (OFFSET, MASK, VALUE) (0XFD080D10, 0xFFFFFFFFU ,0x0E00B03CU) + */ + PSU_Mask_Write(DDR_PHY_DX6GCR4_OFFSET, 0xFFFFFFFFU, 0x0E00B03CU); +/*##################################################################### */ - Configurable ODT(TE) Phase Shift - PSU_DDR_PHY_DX5GCR0_CODTSHFT 0x0 + /* + * Register : DX6GCR5 @ 0XFD080D14 - DQS Duty Cycle Correction - PSU_DDR_PHY_DX5GCR0_DQSDCC 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX6GCR5_RESERVED_31 0x0 - Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY - PSU_DDR_PHY_DX5GCR0_RDDLY 0x8 + * Byte Lane internal VREF Select for Rank 3 + * PSU_DDR_PHY_DX6GCR5_DXREFISELR3 0x9 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX5GCR0_RESERVED_19_14 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX6GCR5_RESERVED_23 0x0 - DQSNSE Power Down Receiver - PSU_DDR_PHY_DX5GCR0_DQSNSEPDR 0x0 + * Byte Lane internal VREF Select for Rank 2 + * PSU_DDR_PHY_DX6GCR5_DXREFISELR2 0x9 - DQSSE Power Down Receiver - PSU_DDR_PHY_DX5GCR0_DQSSEPDR 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX6GCR5_RESERVED_15 0x0 - RTT On Additive Latency - PSU_DDR_PHY_DX5GCR0_RTTOAL 0x0 + * Byte Lane internal VREF Select for Rank 1 + * PSU_DDR_PHY_DX6GCR5_DXREFISELR1 0x55 - RTT Output Hold - PSU_DDR_PHY_DX5GCR0_RTTOH 0x3 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX6GCR5_RESERVED_7 0x0 - Configurable PDR Phase Shift - PSU_DDR_PHY_DX5GCR0_CPDRSHFT 0x0 + * Byte Lane internal VREF Select for Rank 0 + * PSU_DDR_PHY_DX6GCR5_DXREFISELR0 0x55 - DQSR Power Down - PSU_DDR_PHY_DX5GCR0_DQSRPD 0x0 + * DATX8 n General Configuration Register 5 + * (OFFSET, MASK, VALUE) (0XFD080D14, 0xFFFFFFFFU ,0x09095555U) + */ + PSU_Mask_Write(DDR_PHY_DX6GCR5_OFFSET, 0xFFFFFFFFU, 0x09095555U); +/*##################################################################### */ - DQSG Power Down Receiver - PSU_DDR_PHY_DX5GCR0_DQSGPDR 0x0 + /* + * Register : DX6GCR6 @ 0XFD080D18 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX5GCR0_RESERVED_4 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX6GCR6_RESERVED_31_30 0x0 - DQSG On-Die Termination - PSU_DDR_PHY_DX5GCR0_DQSGODT 0x0 + * DRAM DQ VREF Select for Rank3 + * PSU_DDR_PHY_DX6GCR6_DXDQVREFR3 0x9 - DQSG Output Enable - PSU_DDR_PHY_DX5GCR0_DQSGOE 0x1 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX6GCR6_RESERVED_23_22 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX5GCR0_RESERVED_1_0 0x0 + * DRAM DQ VREF Select for Rank2 + * PSU_DDR_PHY_DX6GCR6_DXDQVREFR2 0x9 - DATX8 n General Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD080C00, 0xFFFFFFFFU ,0x40800604U) - RegMask = (DDR_PHY_DX5GCR0_CALBYP_MASK | DDR_PHY_DX5GCR0_MDLEN_MASK | DDR_PHY_DX5GCR0_CODTSHFT_MASK | DDR_PHY_DX5GCR0_DQSDCC_MASK | DDR_PHY_DX5GCR0_RDDLY_MASK | DDR_PHY_DX5GCR0_RESERVED_19_14_MASK | DDR_PHY_DX5GCR0_DQSNSEPDR_MASK | DDR_PHY_DX5GCR0_DQSSEPDR_MASK | DDR_PHY_DX5GCR0_RTTOAL_MASK | DDR_PHY_DX5GCR0_RTTOH_MASK | DDR_PHY_DX5GCR0_CPDRSHFT_MASK | DDR_PHY_DX5GCR0_DQSRPD_MASK | DDR_PHY_DX5GCR0_DQSGPDR_MASK | DDR_PHY_DX5GCR0_RESERVED_4_MASK | DDR_PHY_DX5GCR0_DQSGODT_MASK | DDR_PHY_DX5GCR0_DQSGOE_MASK | DDR_PHY_DX5GCR0_RESERVED_1_0_MASK | 0 ); + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX6GCR6_RESERVED_15_14 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX5GCR0_CALBYP_SHIFT - | 0x00000001U << DDR_PHY_DX5GCR0_MDLEN_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR0_CODTSHFT_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR0_DQSDCC_SHIFT - | 0x00000008U << DDR_PHY_DX5GCR0_RDDLY_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR0_RESERVED_19_14_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR0_DQSNSEPDR_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR0_DQSSEPDR_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR0_RTTOAL_SHIFT - | 0x00000003U << DDR_PHY_DX5GCR0_RTTOH_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR0_CPDRSHFT_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR0_DQSRPD_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR0_DQSGPDR_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR0_RESERVED_4_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR0_DQSGODT_SHIFT - | 0x00000001U << DDR_PHY_DX5GCR0_DQSGOE_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR0_RESERVED_1_0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX5GCR0_OFFSET ,0xFFFFFFFFU ,0x40800604U); - /*############################################################################################################################ */ + * DRAM DQ VREF Select for Rank1 + * PSU_DDR_PHY_DX6GCR6_DXDQVREFR1 0x2b - /*Register : DX5GCR1 @ 0XFD080C04

+ * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX6GCR6_RESERVED_7_6 0x0 - Enables the PDR mode for DQ[7:0] - PSU_DDR_PHY_DX5GCR1_DXPDRMODE 0x0 + * DRAM DQ VREF Select for Rank0 + * PSU_DDR_PHY_DX6GCR6_DXDQVREFR0 0x2b - Reserved. Returns zeroes on reads. - PSU_DDR_PHY_DX5GCR1_RESERVED_15 0x0 + * DATX8 n General Configuration Register 6 + * (OFFSET, MASK, VALUE) (0XFD080D18, 0xFFFFFFFFU ,0x09092B2BU) + */ + PSU_Mask_Write(DDR_PHY_DX6GCR6_OFFSET, 0xFFFFFFFFU, 0x09092B2BU); +/*##################################################################### */ - Select the delayed or non-delayed read data strobe # - PSU_DDR_PHY_DX5GCR1_QSNSEL 0x1 + /* + * Register : DX7GCR0 @ 0XFD080E00 - Select the delayed or non-delayed read data strobe - PSU_DDR_PHY_DX5GCR1_QSSEL 0x1 + * Calibration Bypass + * PSU_DDR_PHY_DX7GCR0_CALBYP 0x0 - Enables Read Data Strobe in a byte lane - PSU_DDR_PHY_DX5GCR1_OEEN 0x1 + * Master Delay Line Enable + * PSU_DDR_PHY_DX7GCR0_MDLEN 0x1 - Enables PDR in a byte lane - PSU_DDR_PHY_DX5GCR1_PDREN 0x1 + * Configurable ODT(TE) Phase Shift + * PSU_DDR_PHY_DX7GCR0_CODTSHFT 0x0 - Enables ODT/TE in a byte lane - PSU_DDR_PHY_DX5GCR1_TEEN 0x1 + * DQS Duty Cycle Correction + * PSU_DDR_PHY_DX7GCR0_DQSDCC 0x0 - Enables Write Data strobe in a byte lane - PSU_DDR_PHY_DX5GCR1_DSEN 0x1 + * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY + * PSU_DDR_PHY_DX7GCR0_RDDLY 0x8 - Enables DM pin in a byte lane - PSU_DDR_PHY_DX5GCR1_DMEN 0x1 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX7GCR0_RESERVED_19_14 0x0 - Enables DQ corresponding to each bit in a byte - PSU_DDR_PHY_DX5GCR1_DQEN 0xff + * DQSNSE Power Down Receiver + * PSU_DDR_PHY_DX7GCR0_DQSNSEPDR 0x0 - DATX8 n General Configuration Register 1 - (OFFSET, MASK, VALUE) (0XFD080C04, 0xFFFFFFFFU ,0x00007FFFU) - RegMask = (DDR_PHY_DX5GCR1_DXPDRMODE_MASK | DDR_PHY_DX5GCR1_RESERVED_15_MASK | DDR_PHY_DX5GCR1_QSNSEL_MASK | DDR_PHY_DX5GCR1_QSSEL_MASK | DDR_PHY_DX5GCR1_OEEN_MASK | DDR_PHY_DX5GCR1_PDREN_MASK | DDR_PHY_DX5GCR1_TEEN_MASK | DDR_PHY_DX5GCR1_DSEN_MASK | DDR_PHY_DX5GCR1_DMEN_MASK | DDR_PHY_DX5GCR1_DQEN_MASK | 0 ); + * DQSSE Power Down Receiver + * PSU_DDR_PHY_DX7GCR0_DQSSEPDR 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX5GCR1_DXPDRMODE_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR1_RESERVED_15_SHIFT - | 0x00000001U << DDR_PHY_DX5GCR1_QSNSEL_SHIFT - | 0x00000001U << DDR_PHY_DX5GCR1_QSSEL_SHIFT - | 0x00000001U << DDR_PHY_DX5GCR1_OEEN_SHIFT - | 0x00000001U << DDR_PHY_DX5GCR1_PDREN_SHIFT - | 0x00000001U << DDR_PHY_DX5GCR1_TEEN_SHIFT - | 0x00000001U << DDR_PHY_DX5GCR1_DSEN_SHIFT - | 0x00000001U << DDR_PHY_DX5GCR1_DMEN_SHIFT - | 0x000000FFU << DDR_PHY_DX5GCR1_DQEN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX5GCR1_OFFSET ,0xFFFFFFFFU ,0x00007FFFU); - /*############################################################################################################################ */ + * RTT On Additive Latency + * PSU_DDR_PHY_DX7GCR0_RTTOAL 0x0 - /*Register : DX5GCR4 @ 0XFD080C10

+ * RTT Output Hold + * PSU_DDR_PHY_DX7GCR0_RTTOH 0x3 - Byte lane VREF IOM (Used only by D4MU IOs) - PSU_DDR_PHY_DX5GCR4_RESERVED_31_29 0x0 + * Configurable PDR Phase Shift + * PSU_DDR_PHY_DX7GCR0_CPDRSHFT 0x0 - Byte Lane VREF Pad Enable - PSU_DDR_PHY_DX5GCR4_DXREFPEN 0x0 + * DQSR Power Down + * PSU_DDR_PHY_DX7GCR0_DQSRPD 0x0 - Byte Lane Internal VREF Enable - PSU_DDR_PHY_DX5GCR4_DXREFEEN 0x3 + * DQSG Power Down Receiver + * PSU_DDR_PHY_DX7GCR0_DQSGPDR 0x0 - Byte Lane Single-End VREF Enable - PSU_DDR_PHY_DX5GCR4_DXREFSEN 0x1 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX7GCR0_RESERVED_4 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX5GCR4_RESERVED_24 0x0 + * DQSG On-Die Termination + * PSU_DDR_PHY_DX7GCR0_DQSGODT 0x0 - External VREF generator REFSEL range select - PSU_DDR_PHY_DX5GCR4_DXREFESELRANGE 0x0 + * DQSG Output Enable + * PSU_DDR_PHY_DX7GCR0_DQSGOE 0x1 - Byte Lane External VREF Select - PSU_DDR_PHY_DX5GCR4_DXREFESEL 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX7GCR0_RESERVED_1_0 0x0 - Single ended VREF generator REFSEL range select - PSU_DDR_PHY_DX5GCR4_DXREFSSELRANGE 0x1 + * DATX8 n General Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD080E00, 0xFFFFFFFFU ,0x40800604U) + */ + PSU_Mask_Write(DDR_PHY_DX7GCR0_OFFSET, 0xFFFFFFFFU, 0x40800604U); +/*##################################################################### */ - Byte Lane Single-End VREF Select - PSU_DDR_PHY_DX5GCR4_DXREFSSEL 0x30 + /* + * Register : DX7GCR1 @ 0XFD080E04 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX5GCR4_RESERVED_7_6 0x0 + * Enables the PDR mode for DQ[7:0] + * PSU_DDR_PHY_DX7GCR1_DXPDRMODE 0x0 - VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. - PSU_DDR_PHY_DX5GCR4_DXREFIEN 0xf + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX7GCR1_RESERVED_15 0x0 - VRMON control for DQ IO (Single Ended) buffers of a byte lane. - PSU_DDR_PHY_DX5GCR4_DXREFIMON 0x0 + * Select the delayed or non-delayed read data strobe # + * PSU_DDR_PHY_DX7GCR1_QSNSEL 0x1 - DATX8 n General Configuration Register 4 - (OFFSET, MASK, VALUE) (0XFD080C10, 0xFFFFFFFFU ,0x0E00B03CU) - RegMask = (DDR_PHY_DX5GCR4_RESERVED_31_29_MASK | DDR_PHY_DX5GCR4_DXREFPEN_MASK | DDR_PHY_DX5GCR4_DXREFEEN_MASK | DDR_PHY_DX5GCR4_DXREFSEN_MASK | DDR_PHY_DX5GCR4_RESERVED_24_MASK | DDR_PHY_DX5GCR4_DXREFESELRANGE_MASK | DDR_PHY_DX5GCR4_DXREFESEL_MASK | DDR_PHY_DX5GCR4_DXREFSSELRANGE_MASK | DDR_PHY_DX5GCR4_DXREFSSEL_MASK | DDR_PHY_DX5GCR4_RESERVED_7_6_MASK | DDR_PHY_DX5GCR4_DXREFIEN_MASK | DDR_PHY_DX5GCR4_DXREFIMON_MASK | 0 ); + * Select the delayed or non-delayed read data strobe + * PSU_DDR_PHY_DX7GCR1_QSSEL 0x1 - RegVal = ((0x00000000U << DDR_PHY_DX5GCR4_RESERVED_31_29_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR4_DXREFPEN_SHIFT - | 0x00000003U << DDR_PHY_DX5GCR4_DXREFEEN_SHIFT - | 0x00000001U << DDR_PHY_DX5GCR4_DXREFSEN_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR4_RESERVED_24_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR4_DXREFESELRANGE_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR4_DXREFESEL_SHIFT - | 0x00000001U << DDR_PHY_DX5GCR4_DXREFSSELRANGE_SHIFT - | 0x00000030U << DDR_PHY_DX5GCR4_DXREFSSEL_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR4_RESERVED_7_6_SHIFT - | 0x0000000FU << DDR_PHY_DX5GCR4_DXREFIEN_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR4_DXREFIMON_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX5GCR4_OFFSET ,0xFFFFFFFFU ,0x0E00B03CU); - /*############################################################################################################################ */ + * Enables Read Data Strobe in a byte lane + * PSU_DDR_PHY_DX7GCR1_OEEN 0x1 - /*Register : DX5GCR5 @ 0XFD080C14

+ * Enables PDR in a byte lane + * PSU_DDR_PHY_DX7GCR1_PDREN 0x1 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX5GCR5_RESERVED_31 0x0 + * Enables ODT/TE in a byte lane + * PSU_DDR_PHY_DX7GCR1_TEEN 0x1 - Byte Lane internal VREF Select for Rank 3 - PSU_DDR_PHY_DX5GCR5_DXREFISELR3 0x9 + * Enables Write Data strobe in a byte lane + * PSU_DDR_PHY_DX7GCR1_DSEN 0x1 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX5GCR5_RESERVED_23 0x0 + * Enables DM pin in a byte lane + * PSU_DDR_PHY_DX7GCR1_DMEN 0x1 - Byte Lane internal VREF Select for Rank 2 - PSU_DDR_PHY_DX5GCR5_DXREFISELR2 0x9 + * Enables DQ corresponding to each bit in a byte + * PSU_DDR_PHY_DX7GCR1_DQEN 0xff - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX5GCR5_RESERVED_15 0x0 + * DATX8 n General Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD080E04, 0xFFFFFFFFU ,0x00007FFFU) + */ + PSU_Mask_Write(DDR_PHY_DX7GCR1_OFFSET, 0xFFFFFFFFU, 0x00007FFFU); +/*##################################################################### */ - Byte Lane internal VREF Select for Rank 1 - PSU_DDR_PHY_DX5GCR5_DXREFISELR1 0x4f + /* + * Register : DX7GCR4 @ 0XFD080E10 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX5GCR5_RESERVED_7 0x0 + * Byte lane VREF IOM (Used only by D4MU IOs) + * PSU_DDR_PHY_DX7GCR4_RESERVED_31_29 0x0 - Byte Lane internal VREF Select for Rank 0 - PSU_DDR_PHY_DX5GCR5_DXREFISELR0 0x4f + * Byte Lane VREF Pad Enable + * PSU_DDR_PHY_DX7GCR4_DXREFPEN 0x0 - DATX8 n General Configuration Register 5 - (OFFSET, MASK, VALUE) (0XFD080C14, 0xFFFFFFFFU ,0x09094F4FU) - RegMask = (DDR_PHY_DX5GCR5_RESERVED_31_MASK | DDR_PHY_DX5GCR5_DXREFISELR3_MASK | DDR_PHY_DX5GCR5_RESERVED_23_MASK | DDR_PHY_DX5GCR5_DXREFISELR2_MASK | DDR_PHY_DX5GCR5_RESERVED_15_MASK | DDR_PHY_DX5GCR5_DXREFISELR1_MASK | DDR_PHY_DX5GCR5_RESERVED_7_MASK | DDR_PHY_DX5GCR5_DXREFISELR0_MASK | 0 ); + * Byte Lane Internal VREF Enable + * PSU_DDR_PHY_DX7GCR4_DXREFEEN 0x3 - RegVal = ((0x00000000U << DDR_PHY_DX5GCR5_RESERVED_31_SHIFT - | 0x00000009U << DDR_PHY_DX5GCR5_DXREFISELR3_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR5_RESERVED_23_SHIFT - | 0x00000009U << DDR_PHY_DX5GCR5_DXREFISELR2_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR5_RESERVED_15_SHIFT - | 0x0000004FU << DDR_PHY_DX5GCR5_DXREFISELR1_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR5_RESERVED_7_SHIFT - | 0x0000004FU << DDR_PHY_DX5GCR5_DXREFISELR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX5GCR5_OFFSET ,0xFFFFFFFFU ,0x09094F4FU); - /*############################################################################################################################ */ + * Byte Lane Single-End VREF Enable + * PSU_DDR_PHY_DX7GCR4_DXREFSEN 0x1 - /*Register : DX5GCR6 @ 0XFD080C18

+ * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX7GCR4_RESERVED_24 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX5GCR6_RESERVED_31_30 0x0 + * External VREF generator REFSEL range select + * PSU_DDR_PHY_DX7GCR4_DXREFESELRANGE 0x0 - DRAM DQ VREF Select for Rank3 - PSU_DDR_PHY_DX5GCR6_DXDQVREFR3 0x9 + * Byte Lane External VREF Select + * PSU_DDR_PHY_DX7GCR4_DXREFESEL 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX5GCR6_RESERVED_23_22 0x0 + * Single ended VREF generator REFSEL range select + * PSU_DDR_PHY_DX7GCR4_DXREFSSELRANGE 0x1 - DRAM DQ VREF Select for Rank2 - PSU_DDR_PHY_DX5GCR6_DXDQVREFR2 0x9 + * Byte Lane Single-End VREF Select + * PSU_DDR_PHY_DX7GCR4_DXREFSSEL 0x30 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX5GCR6_RESERVED_15_14 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX7GCR4_RESERVED_7_6 0x0 - DRAM DQ VREF Select for Rank1 - PSU_DDR_PHY_DX5GCR6_DXDQVREFR1 0x2b + * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX7GCR4_DXREFIEN 0xf - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX5GCR6_RESERVED_7_6 0x0 + * VRMON control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX7GCR4_DXREFIMON 0x0 - DRAM DQ VREF Select for Rank0 - PSU_DDR_PHY_DX5GCR6_DXDQVREFR0 0x2b + * DATX8 n General Configuration Register 4 + * (OFFSET, MASK, VALUE) (0XFD080E10, 0xFFFFFFFFU ,0x0E00B03CU) + */ + PSU_Mask_Write(DDR_PHY_DX7GCR4_OFFSET, 0xFFFFFFFFU, 0x0E00B03CU); +/*##################################################################### */ - DATX8 n General Configuration Register 6 - (OFFSET, MASK, VALUE) (0XFD080C18, 0xFFFFFFFFU ,0x09092B2BU) - RegMask = (DDR_PHY_DX5GCR6_RESERVED_31_30_MASK | DDR_PHY_DX5GCR6_DXDQVREFR3_MASK | DDR_PHY_DX5GCR6_RESERVED_23_22_MASK | DDR_PHY_DX5GCR6_DXDQVREFR2_MASK | DDR_PHY_DX5GCR6_RESERVED_15_14_MASK | DDR_PHY_DX5GCR6_DXDQVREFR1_MASK | DDR_PHY_DX5GCR6_RESERVED_7_6_MASK | DDR_PHY_DX5GCR6_DXDQVREFR0_MASK | 0 ); + /* + * Register : DX7GCR5 @ 0XFD080E14 - RegVal = ((0x00000000U << DDR_PHY_DX5GCR6_RESERVED_31_30_SHIFT - | 0x00000009U << DDR_PHY_DX5GCR6_DXDQVREFR3_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR6_RESERVED_23_22_SHIFT - | 0x00000009U << DDR_PHY_DX5GCR6_DXDQVREFR2_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR6_RESERVED_15_14_SHIFT - | 0x0000002BU << DDR_PHY_DX5GCR6_DXDQVREFR1_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR6_RESERVED_7_6_SHIFT - | 0x0000002BU << DDR_PHY_DX5GCR6_DXDQVREFR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX5GCR6_OFFSET ,0xFFFFFFFFU ,0x09092B2BU); - /*############################################################################################################################ */ + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX7GCR5_RESERVED_31 0x0 - /*Register : DX5LCDLR2 @ 0XFD080C88

+ * Byte Lane internal VREF Select for Rank 3 + * PSU_DDR_PHY_DX7GCR5_DXREFISELR3 0x9 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX5LCDLR2_RESERVED_31_25 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX7GCR5_RESERVED_23 0x0 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX5LCDLR2_RESERVED_24_16 0x0 + * Byte Lane internal VREF Select for Rank 2 + * PSU_DDR_PHY_DX7GCR5_DXREFISELR2 0x9 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX5LCDLR2_RESERVED_15_9 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX7GCR5_RESERVED_15 0x0 - Read DQS Gating Delay - PSU_DDR_PHY_DX5LCDLR2_DQSGD 0x0 + * Byte Lane internal VREF Select for Rank 1 + * PSU_DDR_PHY_DX7GCR5_DXREFISELR1 0x55 - DATX8 n Local Calibrated Delay Line Register 2 - (OFFSET, MASK, VALUE) (0XFD080C88, 0xFFFFFFFFU ,0x00000000U) - RegMask = (DDR_PHY_DX5LCDLR2_RESERVED_31_25_MASK | DDR_PHY_DX5LCDLR2_RESERVED_24_16_MASK | DDR_PHY_DX5LCDLR2_RESERVED_15_9_MASK | DDR_PHY_DX5LCDLR2_DQSGD_MASK | 0 ); + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX7GCR5_RESERVED_7 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX5LCDLR2_RESERVED_31_25_SHIFT - | 0x00000000U << DDR_PHY_DX5LCDLR2_RESERVED_24_16_SHIFT - | 0x00000000U << DDR_PHY_DX5LCDLR2_RESERVED_15_9_SHIFT - | 0x00000000U << DDR_PHY_DX5LCDLR2_DQSGD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX5LCDLR2_OFFSET ,0xFFFFFFFFU ,0x00000000U); - /*############################################################################################################################ */ + * Byte Lane internal VREF Select for Rank 0 + * PSU_DDR_PHY_DX7GCR5_DXREFISELR0 0x55 - /*Register : DX5GTR0 @ 0XFD080CC0

+ * DATX8 n General Configuration Register 5 + * (OFFSET, MASK, VALUE) (0XFD080E14, 0xFFFFFFFFU ,0x09095555U) + */ + PSU_Mask_Write(DDR_PHY_DX7GCR5_OFFSET, 0xFFFFFFFFU, 0x09095555U); +/*##################################################################### */ - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX5GTR0_RESERVED_31_24 0x0 + /* + * Register : DX7GCR6 @ 0XFD080E18 - DQ Write Path Latency Pipeline - PSU_DDR_PHY_DX5GTR0_WDQSL 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX7GCR6_RESERVED_31_30 0x0 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX5GTR0_RESERVED_23_20 0x0 + * DRAM DQ VREF Select for Rank3 + * PSU_DDR_PHY_DX7GCR6_DXDQVREFR3 0x9 - Write Leveling System Latency - PSU_DDR_PHY_DX5GTR0_WLSL 0x2 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX7GCR6_RESERVED_23_22 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX5GTR0_RESERVED_15_13 0x0 + * DRAM DQ VREF Select for Rank2 + * PSU_DDR_PHY_DX7GCR6_DXDQVREFR2 0x9 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX5GTR0_RESERVED_12_8 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX7GCR6_RESERVED_15_14 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX5GTR0_RESERVED_7_5 0x0 + * DRAM DQ VREF Select for Rank1 + * PSU_DDR_PHY_DX7GCR6_DXDQVREFR1 0x2b - DQS Gating System Latency - PSU_DDR_PHY_DX5GTR0_DGSL 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX7GCR6_RESERVED_7_6 0x0 - DATX8 n General Timing Register 0 - (OFFSET, MASK, VALUE) (0XFD080CC0, 0xFFFFFFFFU ,0x00020000U) - RegMask = (DDR_PHY_DX5GTR0_RESERVED_31_24_MASK | DDR_PHY_DX5GTR0_WDQSL_MASK | DDR_PHY_DX5GTR0_RESERVED_23_20_MASK | DDR_PHY_DX5GTR0_WLSL_MASK | DDR_PHY_DX5GTR0_RESERVED_15_13_MASK | DDR_PHY_DX5GTR0_RESERVED_12_8_MASK | DDR_PHY_DX5GTR0_RESERVED_7_5_MASK | DDR_PHY_DX5GTR0_DGSL_MASK | 0 ); + * DRAM DQ VREF Select for Rank0 + * PSU_DDR_PHY_DX7GCR6_DXDQVREFR0 0x2b - RegVal = ((0x00000000U << DDR_PHY_DX5GTR0_RESERVED_31_24_SHIFT - | 0x00000000U << DDR_PHY_DX5GTR0_WDQSL_SHIFT - | 0x00000000U << DDR_PHY_DX5GTR0_RESERVED_23_20_SHIFT - | 0x00000002U << DDR_PHY_DX5GTR0_WLSL_SHIFT - | 0x00000000U << DDR_PHY_DX5GTR0_RESERVED_15_13_SHIFT - | 0x00000000U << DDR_PHY_DX5GTR0_RESERVED_12_8_SHIFT - | 0x00000000U << DDR_PHY_DX5GTR0_RESERVED_7_5_SHIFT - | 0x00000000U << DDR_PHY_DX5GTR0_DGSL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX5GTR0_OFFSET ,0xFFFFFFFFU ,0x00020000U); - /*############################################################################################################################ */ + * DATX8 n General Configuration Register 6 + * (OFFSET, MASK, VALUE) (0XFD080E18, 0xFFFFFFFFU ,0x09092B2BU) + */ + PSU_Mask_Write(DDR_PHY_DX7GCR6_OFFSET, 0xFFFFFFFFU, 0x09092B2BU); +/*##################################################################### */ - /*Register : DX6GCR0 @ 0XFD080D00

+ /* + * Register : DX8GCR0 @ 0XFD080F00 - Calibration Bypass - PSU_DDR_PHY_DX6GCR0_CALBYP 0x0 + * Calibration Bypass + * PSU_DDR_PHY_DX8GCR0_CALBYP 0x0 - Master Delay Line Enable - PSU_DDR_PHY_DX6GCR0_MDLEN 0x1 + * Master Delay Line Enable + * PSU_DDR_PHY_DX8GCR0_MDLEN 0x1 - Configurable ODT(TE) Phase Shift - PSU_DDR_PHY_DX6GCR0_CODTSHFT 0x0 + * Configurable ODT(TE) Phase Shift + * PSU_DDR_PHY_DX8GCR0_CODTSHFT 0x0 - DQS Duty Cycle Correction - PSU_DDR_PHY_DX6GCR0_DQSDCC 0x0 + * DQS Duty Cycle Correction + * PSU_DDR_PHY_DX8GCR0_DQSDCC 0x0 - Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY - PSU_DDR_PHY_DX6GCR0_RDDLY 0x8 + * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY + * PSU_DDR_PHY_DX8GCR0_RDDLY 0x8 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX6GCR0_RESERVED_19_14 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8GCR0_RESERVED_19_14 0x0 - DQSNSE Power Down Receiver - PSU_DDR_PHY_DX6GCR0_DQSNSEPDR 0x0 + * DQSNSE Power Down Receiver + * PSU_DDR_PHY_DX8GCR0_DQSNSEPDR 0x0 - DQSSE Power Down Receiver - PSU_DDR_PHY_DX6GCR0_DQSSEPDR 0x0 + * DQSSE Power Down Receiver + * PSU_DDR_PHY_DX8GCR0_DQSSEPDR 0x0 - RTT On Additive Latency - PSU_DDR_PHY_DX6GCR0_RTTOAL 0x0 + * RTT On Additive Latency + * PSU_DDR_PHY_DX8GCR0_RTTOAL 0x0 - RTT Output Hold - PSU_DDR_PHY_DX6GCR0_RTTOH 0x3 + * RTT Output Hold + * PSU_DDR_PHY_DX8GCR0_RTTOH 0x3 - Configurable PDR Phase Shift - PSU_DDR_PHY_DX6GCR0_CPDRSHFT 0x0 + * Configurable PDR Phase Shift + * PSU_DDR_PHY_DX8GCR0_CPDRSHFT 0x0 - DQSR Power Down - PSU_DDR_PHY_DX6GCR0_DQSRPD 0x0 + * DQSR Power Down + * PSU_DDR_PHY_DX8GCR0_DQSRPD 0x0 - DQSG Power Down Receiver - PSU_DDR_PHY_DX6GCR0_DQSGPDR 0x0 + * DQSG Power Down Receiver + * PSU_DDR_PHY_DX8GCR0_DQSGPDR 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX6GCR0_RESERVED_4 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8GCR0_RESERVED_4 0x0 - DQSG On-Die Termination - PSU_DDR_PHY_DX6GCR0_DQSGODT 0x0 + * DQSG On-Die Termination + * PSU_DDR_PHY_DX8GCR0_DQSGODT 0x0 - DQSG Output Enable - PSU_DDR_PHY_DX6GCR0_DQSGOE 0x1 + * DQSG Output Enable + * PSU_DDR_PHY_DX8GCR0_DQSGOE 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX6GCR0_RESERVED_1_0 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8GCR0_RESERVED_1_0 0x0 - DATX8 n General Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD080D00, 0xFFFFFFFFU ,0x40800604U) - RegMask = (DDR_PHY_DX6GCR0_CALBYP_MASK | DDR_PHY_DX6GCR0_MDLEN_MASK | DDR_PHY_DX6GCR0_CODTSHFT_MASK | DDR_PHY_DX6GCR0_DQSDCC_MASK | DDR_PHY_DX6GCR0_RDDLY_MASK | DDR_PHY_DX6GCR0_RESERVED_19_14_MASK | DDR_PHY_DX6GCR0_DQSNSEPDR_MASK | DDR_PHY_DX6GCR0_DQSSEPDR_MASK | DDR_PHY_DX6GCR0_RTTOAL_MASK | DDR_PHY_DX6GCR0_RTTOH_MASK | DDR_PHY_DX6GCR0_CPDRSHFT_MASK | DDR_PHY_DX6GCR0_DQSRPD_MASK | DDR_PHY_DX6GCR0_DQSGPDR_MASK | DDR_PHY_DX6GCR0_RESERVED_4_MASK | DDR_PHY_DX6GCR0_DQSGODT_MASK | DDR_PHY_DX6GCR0_DQSGOE_MASK | DDR_PHY_DX6GCR0_RESERVED_1_0_MASK | 0 ); + * DATX8 n General Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD080F00, 0xFFFFFFFFU ,0x40800624U) + */ + PSU_Mask_Write(DDR_PHY_DX8GCR0_OFFSET, 0xFFFFFFFFU, 0x40800624U); +/*##################################################################### */ - RegVal = ((0x00000000U << DDR_PHY_DX6GCR0_CALBYP_SHIFT - | 0x00000001U << DDR_PHY_DX6GCR0_MDLEN_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR0_CODTSHFT_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR0_DQSDCC_SHIFT - | 0x00000008U << DDR_PHY_DX6GCR0_RDDLY_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR0_RESERVED_19_14_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR0_DQSNSEPDR_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR0_DQSSEPDR_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR0_RTTOAL_SHIFT - | 0x00000003U << DDR_PHY_DX6GCR0_RTTOH_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR0_CPDRSHFT_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR0_DQSRPD_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR0_DQSGPDR_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR0_RESERVED_4_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR0_DQSGODT_SHIFT - | 0x00000001U << DDR_PHY_DX6GCR0_DQSGOE_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR0_RESERVED_1_0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX6GCR0_OFFSET ,0xFFFFFFFFU ,0x40800604U); - /*############################################################################################################################ */ + /* + * Register : DX8GCR1 @ 0XFD080F04 - /*Register : DX6GCR1 @ 0XFD080D04

+ * Enables the PDR mode for DQ[7:0] + * PSU_DDR_PHY_DX8GCR1_DXPDRMODE 0x0 - Enables the PDR mode for DQ[7:0] - PSU_DDR_PHY_DX6GCR1_DXPDRMODE 0x0 + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX8GCR1_RESERVED_15 0x0 - Reserved. Returns zeroes on reads. - PSU_DDR_PHY_DX6GCR1_RESERVED_15 0x0 + * Select the delayed or non-delayed read data strobe # + * PSU_DDR_PHY_DX8GCR1_QSNSEL 0x1 - Select the delayed or non-delayed read data strobe # - PSU_DDR_PHY_DX6GCR1_QSNSEL 0x1 + * Select the delayed or non-delayed read data strobe + * PSU_DDR_PHY_DX8GCR1_QSSEL 0x1 - Select the delayed or non-delayed read data strobe - PSU_DDR_PHY_DX6GCR1_QSSEL 0x1 + * Enables Read Data Strobe in a byte lane + * PSU_DDR_PHY_DX8GCR1_OEEN 0x1 - Enables Read Data Strobe in a byte lane - PSU_DDR_PHY_DX6GCR1_OEEN 0x1 + * Enables PDR in a byte lane + * PSU_DDR_PHY_DX8GCR1_PDREN 0x1 - Enables PDR in a byte lane - PSU_DDR_PHY_DX6GCR1_PDREN 0x1 + * Enables ODT/TE in a byte lane + * PSU_DDR_PHY_DX8GCR1_TEEN 0x1 - Enables ODT/TE in a byte lane - PSU_DDR_PHY_DX6GCR1_TEEN 0x1 + * Enables Write Data strobe in a byte lane + * PSU_DDR_PHY_DX8GCR1_DSEN 0x1 - Enables Write Data strobe in a byte lane - PSU_DDR_PHY_DX6GCR1_DSEN 0x1 + * Enables DM pin in a byte lane + * PSU_DDR_PHY_DX8GCR1_DMEN 0x1 - Enables DM pin in a byte lane - PSU_DDR_PHY_DX6GCR1_DMEN 0x1 + * Enables DQ corresponding to each bit in a byte + * PSU_DDR_PHY_DX8GCR1_DQEN 0x0 - Enables DQ corresponding to each bit in a byte - PSU_DDR_PHY_DX6GCR1_DQEN 0xff + * DATX8 n General Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD080F04, 0xFFFFFFFFU ,0x00007F00U) + */ + PSU_Mask_Write(DDR_PHY_DX8GCR1_OFFSET, 0xFFFFFFFFU, 0x00007F00U); +/*##################################################################### */ - DATX8 n General Configuration Register 1 - (OFFSET, MASK, VALUE) (0XFD080D04, 0xFFFFFFFFU ,0x00007FFFU) - RegMask = (DDR_PHY_DX6GCR1_DXPDRMODE_MASK | DDR_PHY_DX6GCR1_RESERVED_15_MASK | DDR_PHY_DX6GCR1_QSNSEL_MASK | DDR_PHY_DX6GCR1_QSSEL_MASK | DDR_PHY_DX6GCR1_OEEN_MASK | DDR_PHY_DX6GCR1_PDREN_MASK | DDR_PHY_DX6GCR1_TEEN_MASK | DDR_PHY_DX6GCR1_DSEN_MASK | DDR_PHY_DX6GCR1_DMEN_MASK | DDR_PHY_DX6GCR1_DQEN_MASK | 0 ); + /* + * Register : DX8GCR4 @ 0XFD080F10 - RegVal = ((0x00000000U << DDR_PHY_DX6GCR1_DXPDRMODE_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR1_RESERVED_15_SHIFT - | 0x00000001U << DDR_PHY_DX6GCR1_QSNSEL_SHIFT - | 0x00000001U << DDR_PHY_DX6GCR1_QSSEL_SHIFT - | 0x00000001U << DDR_PHY_DX6GCR1_OEEN_SHIFT - | 0x00000001U << DDR_PHY_DX6GCR1_PDREN_SHIFT - | 0x00000001U << DDR_PHY_DX6GCR1_TEEN_SHIFT - | 0x00000001U << DDR_PHY_DX6GCR1_DSEN_SHIFT - | 0x00000001U << DDR_PHY_DX6GCR1_DMEN_SHIFT - | 0x000000FFU << DDR_PHY_DX6GCR1_DQEN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX6GCR1_OFFSET ,0xFFFFFFFFU ,0x00007FFFU); - /*############################################################################################################################ */ + * Byte lane VREF IOM (Used only by D4MU IOs) + * PSU_DDR_PHY_DX8GCR4_RESERVED_31_29 0x0 - /*Register : DX6GCR4 @ 0XFD080D10

+ * Byte Lane VREF Pad Enable + * PSU_DDR_PHY_DX8GCR4_DXREFPEN 0x0 - Byte lane VREF IOM (Used only by D4MU IOs) - PSU_DDR_PHY_DX6GCR4_RESERVED_31_29 0x0 + * Byte Lane Internal VREF Enable + * PSU_DDR_PHY_DX8GCR4_DXREFEEN 0x3 - Byte Lane VREF Pad Enable - PSU_DDR_PHY_DX6GCR4_DXREFPEN 0x0 + * Byte Lane Single-End VREF Enable + * PSU_DDR_PHY_DX8GCR4_DXREFSEN 0x1 - Byte Lane Internal VREF Enable - PSU_DDR_PHY_DX6GCR4_DXREFEEN 0x3 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX8GCR4_RESERVED_24 0x0 - Byte Lane Single-End VREF Enable - PSU_DDR_PHY_DX6GCR4_DXREFSEN 0x1 + * External VREF generator REFSEL range select + * PSU_DDR_PHY_DX8GCR4_DXREFESELRANGE 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX6GCR4_RESERVED_24 0x0 + * Byte Lane External VREF Select + * PSU_DDR_PHY_DX8GCR4_DXREFESEL 0x0 - External VREF generator REFSEL range select - PSU_DDR_PHY_DX6GCR4_DXREFESELRANGE 0x0 + * Single ended VREF generator REFSEL range select + * PSU_DDR_PHY_DX8GCR4_DXREFSSELRANGE 0x1 - Byte Lane External VREF Select - PSU_DDR_PHY_DX6GCR4_DXREFESEL 0x0 + * Byte Lane Single-End VREF Select + * PSU_DDR_PHY_DX8GCR4_DXREFSSEL 0x30 - Single ended VREF generator REFSEL range select - PSU_DDR_PHY_DX6GCR4_DXREFSSELRANGE 0x1 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX8GCR4_RESERVED_7_6 0x0 - Byte Lane Single-End VREF Select - PSU_DDR_PHY_DX6GCR4_DXREFSSEL 0x30 + * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX8GCR4_DXREFIEN 0xf - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX6GCR4_RESERVED_7_6 0x0 + * VRMON control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX8GCR4_DXREFIMON 0x0 - VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. - PSU_DDR_PHY_DX6GCR4_DXREFIEN 0xf + * DATX8 n General Configuration Register 4 + * (OFFSET, MASK, VALUE) (0XFD080F10, 0xFFFFFFFFU ,0x0E00B03CU) + */ + PSU_Mask_Write(DDR_PHY_DX8GCR4_OFFSET, 0xFFFFFFFFU, 0x0E00B03CU); +/*##################################################################### */ - VRMON control for DQ IO (Single Ended) buffers of a byte lane. - PSU_DDR_PHY_DX6GCR4_DXREFIMON 0x0 + /* + * Register : DX8GCR5 @ 0XFD080F14 - DATX8 n General Configuration Register 4 - (OFFSET, MASK, VALUE) (0XFD080D10, 0xFFFFFFFFU ,0x0E00B03CU) - RegMask = (DDR_PHY_DX6GCR4_RESERVED_31_29_MASK | DDR_PHY_DX6GCR4_DXREFPEN_MASK | DDR_PHY_DX6GCR4_DXREFEEN_MASK | DDR_PHY_DX6GCR4_DXREFSEN_MASK | DDR_PHY_DX6GCR4_RESERVED_24_MASK | DDR_PHY_DX6GCR4_DXREFESELRANGE_MASK | DDR_PHY_DX6GCR4_DXREFESEL_MASK | DDR_PHY_DX6GCR4_DXREFSSELRANGE_MASK | DDR_PHY_DX6GCR4_DXREFSSEL_MASK | DDR_PHY_DX6GCR4_RESERVED_7_6_MASK | DDR_PHY_DX6GCR4_DXREFIEN_MASK | DDR_PHY_DX6GCR4_DXREFIMON_MASK | 0 ); + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX8GCR5_RESERVED_31 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX6GCR4_RESERVED_31_29_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR4_DXREFPEN_SHIFT - | 0x00000003U << DDR_PHY_DX6GCR4_DXREFEEN_SHIFT - | 0x00000001U << DDR_PHY_DX6GCR4_DXREFSEN_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR4_RESERVED_24_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR4_DXREFESELRANGE_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR4_DXREFESEL_SHIFT - | 0x00000001U << DDR_PHY_DX6GCR4_DXREFSSELRANGE_SHIFT - | 0x00000030U << DDR_PHY_DX6GCR4_DXREFSSEL_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR4_RESERVED_7_6_SHIFT - | 0x0000000FU << DDR_PHY_DX6GCR4_DXREFIEN_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR4_DXREFIMON_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX6GCR4_OFFSET ,0xFFFFFFFFU ,0x0E00B03CU); - /*############################################################################################################################ */ + * Byte Lane internal VREF Select for Rank 3 + * PSU_DDR_PHY_DX8GCR5_DXREFISELR3 0x9 - /*Register : DX6GCR5 @ 0XFD080D14

+ * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX8GCR5_RESERVED_23 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX6GCR5_RESERVED_31 0x0 + * Byte Lane internal VREF Select for Rank 2 + * PSU_DDR_PHY_DX8GCR5_DXREFISELR2 0x9 - Byte Lane internal VREF Select for Rank 3 - PSU_DDR_PHY_DX6GCR5_DXREFISELR3 0x9 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX8GCR5_RESERVED_15 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX6GCR5_RESERVED_23 0x0 + * Byte Lane internal VREF Select for Rank 1 + * PSU_DDR_PHY_DX8GCR5_DXREFISELR1 0x55 - Byte Lane internal VREF Select for Rank 2 - PSU_DDR_PHY_DX6GCR5_DXREFISELR2 0x9 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX8GCR5_RESERVED_7 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX6GCR5_RESERVED_15 0x0 + * Byte Lane internal VREF Select for Rank 0 + * PSU_DDR_PHY_DX8GCR5_DXREFISELR0 0x55 - Byte Lane internal VREF Select for Rank 1 - PSU_DDR_PHY_DX6GCR5_DXREFISELR1 0x4f + * DATX8 n General Configuration Register 5 + * (OFFSET, MASK, VALUE) (0XFD080F14, 0xFFFFFFFFU ,0x09095555U) + */ + PSU_Mask_Write(DDR_PHY_DX8GCR5_OFFSET, 0xFFFFFFFFU, 0x09095555U); +/*##################################################################### */ - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX6GCR5_RESERVED_7 0x0 + /* + * Register : DX8GCR6 @ 0XFD080F18 - Byte Lane internal VREF Select for Rank 0 - PSU_DDR_PHY_DX6GCR5_DXREFISELR0 0x4f + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX8GCR6_RESERVED_31_30 0x0 - DATX8 n General Configuration Register 5 - (OFFSET, MASK, VALUE) (0XFD080D14, 0xFFFFFFFFU ,0x09094F4FU) - RegMask = (DDR_PHY_DX6GCR5_RESERVED_31_MASK | DDR_PHY_DX6GCR5_DXREFISELR3_MASK | DDR_PHY_DX6GCR5_RESERVED_23_MASK | DDR_PHY_DX6GCR5_DXREFISELR2_MASK | DDR_PHY_DX6GCR5_RESERVED_15_MASK | DDR_PHY_DX6GCR5_DXREFISELR1_MASK | DDR_PHY_DX6GCR5_RESERVED_7_MASK | DDR_PHY_DX6GCR5_DXREFISELR0_MASK | 0 ); + * DRAM DQ VREF Select for Rank3 + * PSU_DDR_PHY_DX8GCR6_DXDQVREFR3 0x9 - RegVal = ((0x00000000U << DDR_PHY_DX6GCR5_RESERVED_31_SHIFT - | 0x00000009U << DDR_PHY_DX6GCR5_DXREFISELR3_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR5_RESERVED_23_SHIFT - | 0x00000009U << DDR_PHY_DX6GCR5_DXREFISELR2_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR5_RESERVED_15_SHIFT - | 0x0000004FU << DDR_PHY_DX6GCR5_DXREFISELR1_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR5_RESERVED_7_SHIFT - | 0x0000004FU << DDR_PHY_DX6GCR5_DXREFISELR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX6GCR5_OFFSET ,0xFFFFFFFFU ,0x09094F4FU); - /*############################################################################################################################ */ + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX8GCR6_RESERVED_23_22 0x0 - /*Register : DX6GCR6 @ 0XFD080D18

+ * DRAM DQ VREF Select for Rank2 + * PSU_DDR_PHY_DX8GCR6_DXDQVREFR2 0x9 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX6GCR6_RESERVED_31_30 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX8GCR6_RESERVED_15_14 0x0 - DRAM DQ VREF Select for Rank3 - PSU_DDR_PHY_DX6GCR6_DXDQVREFR3 0x9 + * DRAM DQ VREF Select for Rank1 + * PSU_DDR_PHY_DX8GCR6_DXDQVREFR1 0x2b - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX6GCR6_RESERVED_23_22 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX8GCR6_RESERVED_7_6 0x0 - DRAM DQ VREF Select for Rank2 - PSU_DDR_PHY_DX6GCR6_DXDQVREFR2 0x9 + * DRAM DQ VREF Select for Rank0 + * PSU_DDR_PHY_DX8GCR6_DXDQVREFR0 0x2b - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX6GCR6_RESERVED_15_14 0x0 + * DATX8 n General Configuration Register 6 + * (OFFSET, MASK, VALUE) (0XFD080F18, 0xFFFFFFFFU ,0x09092B2BU) + */ + PSU_Mask_Write(DDR_PHY_DX8GCR6_OFFSET, 0xFFFFFFFFU, 0x09092B2BU); +/*##################################################################### */ - DRAM DQ VREF Select for Rank1 - PSU_DDR_PHY_DX6GCR6_DXDQVREFR1 0x2b + /* + * Register : DX8SL0OSC @ 0XFD081400 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX6GCR6_RESERVED_7_6 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL0OSC_RESERVED_31_30 0x0 - DRAM DQ VREF Select for Rank0 - PSU_DDR_PHY_DX6GCR6_DXDQVREFR0 0x2b + * Enable Clock Gating for DX ddr_clk + * PSU_DDR_PHY_DX8SL0OSC_GATEDXRDCLK 0x2 - DATX8 n General Configuration Register 6 - (OFFSET, MASK, VALUE) (0XFD080D18, 0xFFFFFFFFU ,0x09092B2BU) - RegMask = (DDR_PHY_DX6GCR6_RESERVED_31_30_MASK | DDR_PHY_DX6GCR6_DXDQVREFR3_MASK | DDR_PHY_DX6GCR6_RESERVED_23_22_MASK | DDR_PHY_DX6GCR6_DXDQVREFR2_MASK | DDR_PHY_DX6GCR6_RESERVED_15_14_MASK | DDR_PHY_DX6GCR6_DXDQVREFR1_MASK | DDR_PHY_DX6GCR6_RESERVED_7_6_MASK | DDR_PHY_DX6GCR6_DXDQVREFR0_MASK | 0 ); + * Enable Clock Gating for DX ctl_rd_clk + * PSU_DDR_PHY_DX8SL0OSC_GATEDXDDRCLK 0x2 - RegVal = ((0x00000000U << DDR_PHY_DX6GCR6_RESERVED_31_30_SHIFT - | 0x00000009U << DDR_PHY_DX6GCR6_DXDQVREFR3_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR6_RESERVED_23_22_SHIFT - | 0x00000009U << DDR_PHY_DX6GCR6_DXDQVREFR2_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR6_RESERVED_15_14_SHIFT - | 0x0000002BU << DDR_PHY_DX6GCR6_DXDQVREFR1_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR6_RESERVED_7_6_SHIFT - | 0x0000002BU << DDR_PHY_DX6GCR6_DXDQVREFR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX6GCR6_OFFSET ,0xFFFFFFFFU ,0x09092B2BU); - /*############################################################################################################################ */ + * Enable Clock Gating for DX ctl_clk + * PSU_DDR_PHY_DX8SL0OSC_GATEDXCTLCLK 0x2 - /*Register : DX6LCDLR2 @ 0XFD080D88

+ * Selects the level to which clocks will be stalled when clock gating is e + * nabled. + * PSU_DDR_PHY_DX8SL0OSC_CLKLEVEL 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX6LCDLR2_RESERVED_31_25 0x0 + * Loopback Mode + * PSU_DDR_PHY_DX8SL0OSC_LBMODE 0x0 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX6LCDLR2_RESERVED_24_16 0x0 + * Load GSDQS LCDL with 2x the calibrated GSDQSPRD value + * PSU_DDR_PHY_DX8SL0OSC_LBGSDQS 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX6LCDLR2_RESERVED_15_9 0x0 + * Loopback DQS Gating + * PSU_DDR_PHY_DX8SL0OSC_LBGDQS 0x0 - Read DQS Gating Delay - PSU_DDR_PHY_DX6LCDLR2_DQSGD 0x0 + * Loopback DQS Shift + * PSU_DDR_PHY_DX8SL0OSC_LBDQSS 0x0 - DATX8 n Local Calibrated Delay Line Register 2 - (OFFSET, MASK, VALUE) (0XFD080D88, 0xFFFFFFFFU ,0x00000000U) - RegMask = (DDR_PHY_DX6LCDLR2_RESERVED_31_25_MASK | DDR_PHY_DX6LCDLR2_RESERVED_24_16_MASK | DDR_PHY_DX6LCDLR2_RESERVED_15_9_MASK | DDR_PHY_DX6LCDLR2_DQSGD_MASK | 0 ); + * PHY High-Speed Reset + * PSU_DDR_PHY_DX8SL0OSC_PHYHRST 0x1 - RegVal = ((0x00000000U << DDR_PHY_DX6LCDLR2_RESERVED_31_25_SHIFT - | 0x00000000U << DDR_PHY_DX6LCDLR2_RESERVED_24_16_SHIFT - | 0x00000000U << DDR_PHY_DX6LCDLR2_RESERVED_15_9_SHIFT - | 0x00000000U << DDR_PHY_DX6LCDLR2_DQSGD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX6LCDLR2_OFFSET ,0xFFFFFFFFU ,0x00000000U); - /*############################################################################################################################ */ + * PHY FIFO Reset + * PSU_DDR_PHY_DX8SL0OSC_PHYFRST 0x1 - /*Register : DX6GTR0 @ 0XFD080DC0

+ * Delay Line Test Start + * PSU_DDR_PHY_DX8SL0OSC_DLTST 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX6GTR0_RESERVED_31_24 0x0 + * Delay Line Test Mode + * PSU_DDR_PHY_DX8SL0OSC_DLTMODE 0x0 - DQ Write Path Latency Pipeline - PSU_DDR_PHY_DX6GTR0_WDQSL 0x0 + * Reserved. Caution, do not write to this register field. + * PSU_DDR_PHY_DX8SL0OSC_RESERVED_12_11 0x3 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX6GTR0_RESERVED_23_20 0x0 + * Oscillator Mode Write-Data Delay Line Select + * PSU_DDR_PHY_DX8SL0OSC_OSCWDDL 0x3 - Write Leveling System Latency - PSU_DDR_PHY_DX6GTR0_WLSL 0x2 + * Reserved. Caution, do not write to this register field. + * PSU_DDR_PHY_DX8SL0OSC_RESERVED_8_7 0x3 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX6GTR0_RESERVED_15_13 0x0 + * Oscillator Mode Write-Leveling Delay Line Select + * PSU_DDR_PHY_DX8SL0OSC_OSCWDL 0x3 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX6GTR0_RESERVED_12_8 0x0 + * Oscillator Mode Division + * PSU_DDR_PHY_DX8SL0OSC_OSCDIV 0xf - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX6GTR0_RESERVED_7_5 0x0 + * Oscillator Enable + * PSU_DDR_PHY_DX8SL0OSC_OSCEN 0x0 - DQS Gating System Latency - PSU_DDR_PHY_DX6GTR0_DGSL 0x0 + * DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Lo + * opback, and Gated Clock Control Register + * (OFFSET, MASK, VALUE) (0XFD081400, 0xFFFFFFFFU ,0x2A019FFEU) + */ + PSU_Mask_Write(DDR_PHY_DX8SL0OSC_OFFSET, 0xFFFFFFFFU, 0x2A019FFEU); +/*##################################################################### */ - DATX8 n General Timing Register 0 - (OFFSET, MASK, VALUE) (0XFD080DC0, 0xFFFFFFFFU ,0x00020000U) - RegMask = (DDR_PHY_DX6GTR0_RESERVED_31_24_MASK | DDR_PHY_DX6GTR0_WDQSL_MASK | DDR_PHY_DX6GTR0_RESERVED_23_20_MASK | DDR_PHY_DX6GTR0_WLSL_MASK | DDR_PHY_DX6GTR0_RESERVED_15_13_MASK | DDR_PHY_DX6GTR0_RESERVED_12_8_MASK | DDR_PHY_DX6GTR0_RESERVED_7_5_MASK | DDR_PHY_DX6GTR0_DGSL_MASK | 0 ); + /* + * Register : DX8SL0PLLCR0 @ 0XFD081404 - RegVal = ((0x00000000U << DDR_PHY_DX6GTR0_RESERVED_31_24_SHIFT - | 0x00000000U << DDR_PHY_DX6GTR0_WDQSL_SHIFT - | 0x00000000U << DDR_PHY_DX6GTR0_RESERVED_23_20_SHIFT - | 0x00000002U << DDR_PHY_DX6GTR0_WLSL_SHIFT - | 0x00000000U << DDR_PHY_DX6GTR0_RESERVED_15_13_SHIFT - | 0x00000000U << DDR_PHY_DX6GTR0_RESERVED_12_8_SHIFT - | 0x00000000U << DDR_PHY_DX6GTR0_RESERVED_7_5_SHIFT - | 0x00000000U << DDR_PHY_DX6GTR0_DGSL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX6GTR0_OFFSET ,0xFFFFFFFFU ,0x00020000U); - /*############################################################################################################################ */ + * PLL Bypass + * PSU_DDR_PHY_DX8SL0PLLCR0_PLLBYP 0x0 - /*Register : DX7GCR0 @ 0XFD080E00

+ * PLL Reset + * PSU_DDR_PHY_DX8SL0PLLCR0_PLLRST 0x0 - Calibration Bypass - PSU_DDR_PHY_DX7GCR0_CALBYP 0x0 + * PLL Power Down + * PSU_DDR_PHY_DX8SL0PLLCR0_PLLPD 0x0 - Master Delay Line Enable - PSU_DDR_PHY_DX7GCR0_MDLEN 0x1 + * Reference Stop Mode + * PSU_DDR_PHY_DX8SL0PLLCR0_RSTOPM 0x0 - Configurable ODT(TE) Phase Shift - PSU_DDR_PHY_DX7GCR0_CODTSHFT 0x0 + * PLL Frequency Select + * PSU_DDR_PHY_DX8SL0PLLCR0_FRQSEL 0x1 - DQS Duty Cycle Correction - PSU_DDR_PHY_DX7GCR0_DQSDCC 0x0 + * Relock Mode + * PSU_DDR_PHY_DX8SL0PLLCR0_RLOCKM 0x0 - Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY - PSU_DDR_PHY_DX7GCR0_RDDLY 0x8 + * Charge Pump Proportional Current Control + * PSU_DDR_PHY_DX8SL0PLLCR0_CPPC 0x8 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX7GCR0_RESERVED_19_14 0x0 + * Charge Pump Integrating Current Control + * PSU_DDR_PHY_DX8SL0PLLCR0_CPIC 0x0 - DQSNSE Power Down Receiver - PSU_DDR_PHY_DX7GCR0_DQSNSEPDR 0x0 + * Gear Shift + * PSU_DDR_PHY_DX8SL0PLLCR0_GSHIFT 0x0 - DQSSE Power Down Receiver - PSU_DDR_PHY_DX7GCR0_DQSSEPDR 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL0PLLCR0_RESERVED_11_9 0x0 - RTT On Additive Latency - PSU_DDR_PHY_DX7GCR0_RTTOAL 0x0 + * Analog Test Enable (ATOEN) + * PSU_DDR_PHY_DX8SL0PLLCR0_ATOEN 0x0 - RTT Output Hold - PSU_DDR_PHY_DX7GCR0_RTTOH 0x3 + * Analog Test Control + * PSU_DDR_PHY_DX8SL0PLLCR0_ATC 0x0 - Configurable PDR Phase Shift - PSU_DDR_PHY_DX7GCR0_CPDRSHFT 0x0 + * Digital Test Control + * PSU_DDR_PHY_DX8SL0PLLCR0_DTC 0x0 - DQSR Power Down - PSU_DDR_PHY_DX7GCR0_DQSRPD 0x0 + * DAXT8 0-1 PLL Control Register 0 + * (OFFSET, MASK, VALUE) (0XFD081404, 0xFFFFFFFFU ,0x01100000U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL0PLLCR0_OFFSET, + 0xFFFFFFFFU, 0x01100000U); +/*##################################################################### */ - DQSG Power Down Receiver - PSU_DDR_PHY_DX7GCR0_DQSGPDR 0x0 + /* + * Register : DX8SL0DQSCTL @ 0XFD08141C - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX7GCR0_RESERVED_4 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25 0x0 - DQSG On-Die Termination - PSU_DDR_PHY_DX7GCR0_DQSGODT 0x0 + * Read Path Rise-to-Rise Mode + * PSU_DDR_PHY_DX8SL0DQSCTL_RRRMODE 0x1 - DQSG Output Enable - PSU_DDR_PHY_DX7GCR0_DQSGOE 0x1 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX7GCR0_RESERVED_1_0 0x0 + * Write Path Rise-to-Rise Mode + * PSU_DDR_PHY_DX8SL0DQSCTL_WRRMODE 0x1 - DATX8 n General Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD080E00, 0xFFFFFFFFU ,0x40800604U) - RegMask = (DDR_PHY_DX7GCR0_CALBYP_MASK | DDR_PHY_DX7GCR0_MDLEN_MASK | DDR_PHY_DX7GCR0_CODTSHFT_MASK | DDR_PHY_DX7GCR0_DQSDCC_MASK | DDR_PHY_DX7GCR0_RDDLY_MASK | DDR_PHY_DX7GCR0_RESERVED_19_14_MASK | DDR_PHY_DX7GCR0_DQSNSEPDR_MASK | DDR_PHY_DX7GCR0_DQSSEPDR_MASK | DDR_PHY_DX7GCR0_RTTOAL_MASK | DDR_PHY_DX7GCR0_RTTOH_MASK | DDR_PHY_DX7GCR0_CPDRSHFT_MASK | DDR_PHY_DX7GCR0_DQSRPD_MASK | DDR_PHY_DX7GCR0_DQSGPDR_MASK | DDR_PHY_DX7GCR0_RESERVED_4_MASK | DDR_PHY_DX7GCR0_DQSGODT_MASK | DDR_PHY_DX7GCR0_DQSGOE_MASK | DDR_PHY_DX7GCR0_RESERVED_1_0_MASK | 0 ); + * DQS Gate Extension + * PSU_DDR_PHY_DX8SL0DQSCTL_DQSGX 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX7GCR0_CALBYP_SHIFT - | 0x00000001U << DDR_PHY_DX7GCR0_MDLEN_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR0_CODTSHFT_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR0_DQSDCC_SHIFT - | 0x00000008U << DDR_PHY_DX7GCR0_RDDLY_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR0_RESERVED_19_14_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR0_DQSNSEPDR_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR0_DQSSEPDR_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR0_RTTOAL_SHIFT - | 0x00000003U << DDR_PHY_DX7GCR0_RTTOH_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR0_CPDRSHFT_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR0_DQSRPD_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR0_DQSGPDR_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR0_RESERVED_4_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR0_DQSGODT_SHIFT - | 0x00000001U << DDR_PHY_DX7GCR0_DQSGOE_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR0_RESERVED_1_0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX7GCR0_OFFSET ,0xFFFFFFFFU ,0x40800604U); - /*############################################################################################################################ */ + * Low Power PLL Power Down + * PSU_DDR_PHY_DX8SL0DQSCTL_LPPLLPD 0x1 - /*Register : DX7GCR1 @ 0XFD080E04

+ * Low Power I/O Power Down + * PSU_DDR_PHY_DX8SL0DQSCTL_LPIOPD 0x1 - Enables the PDR mode for DQ[7:0] - PSU_DDR_PHY_DX7GCR1_DXPDRMODE 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15 0x0 - Reserved. Returns zeroes on reads. - PSU_DDR_PHY_DX7GCR1_RESERVED_15 0x0 + * QS Counter Enable + * PSU_DDR_PHY_DX8SL0DQSCTL_QSCNTEN 0x1 - Select the delayed or non-delayed read data strobe # - PSU_DDR_PHY_DX7GCR1_QSNSEL 0x1 + * Unused DQ I/O Mode + * PSU_DDR_PHY_DX8SL0DQSCTL_UDQIOM 0x0 - Select the delayed or non-delayed read data strobe - PSU_DDR_PHY_DX7GCR1_QSSEL 0x1 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10 0x0 - Enables Read Data Strobe in a byte lane - PSU_DDR_PHY_DX7GCR1_OEEN 0x1 + * Data Slew Rate + * PSU_DDR_PHY_DX8SL0DQSCTL_DXSR 0x3 - Enables PDR in a byte lane - PSU_DDR_PHY_DX7GCR1_PDREN 0x1 + * DQS_N Resistor + * PSU_DDR_PHY_DX8SL0DQSCTL_DQSNRES 0x0 - Enables ODT/TE in a byte lane - PSU_DDR_PHY_DX7GCR1_TEEN 0x1 + * DQS Resistor + * PSU_DDR_PHY_DX8SL0DQSCTL_DQSRES 0x0 - Enables Write Data strobe in a byte lane - PSU_DDR_PHY_DX7GCR1_DSEN 0x1 + * DATX8 0-1 DQS Control Register + * (OFFSET, MASK, VALUE) (0XFD08141C, 0xFFFFFFFFU ,0x01264300U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL0DQSCTL_OFFSET, + 0xFFFFFFFFU, 0x01264300U); +/*##################################################################### */ - Enables DM pin in a byte lane - PSU_DDR_PHY_DX7GCR1_DMEN 0x1 + /* + * Register : DX8SL0DXCTL2 @ 0XFD08142C - Enables DQ corresponding to each bit in a byte - PSU_DDR_PHY_DX7GCR1_DQEN 0xff + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24 0x0 - DATX8 n General Configuration Register 1 - (OFFSET, MASK, VALUE) (0XFD080E04, 0xFFFFFFFFU ,0x00007FFFU) - RegMask = (DDR_PHY_DX7GCR1_DXPDRMODE_MASK | DDR_PHY_DX7GCR1_RESERVED_15_MASK | DDR_PHY_DX7GCR1_QSNSEL_MASK | DDR_PHY_DX7GCR1_QSSEL_MASK | DDR_PHY_DX7GCR1_OEEN_MASK | DDR_PHY_DX7GCR1_PDREN_MASK | DDR_PHY_DX7GCR1_TEEN_MASK | DDR_PHY_DX7GCR1_DSEN_MASK | DDR_PHY_DX7GCR1_DMEN_MASK | DDR_PHY_DX7GCR1_DQEN_MASK | 0 ); + * Configurable Read Data Enable + * PSU_DDR_PHY_DX8SL0DXCTL2_CRDEN 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX7GCR1_DXPDRMODE_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR1_RESERVED_15_SHIFT - | 0x00000001U << DDR_PHY_DX7GCR1_QSNSEL_SHIFT - | 0x00000001U << DDR_PHY_DX7GCR1_QSSEL_SHIFT - | 0x00000001U << DDR_PHY_DX7GCR1_OEEN_SHIFT - | 0x00000001U << DDR_PHY_DX7GCR1_PDREN_SHIFT - | 0x00000001U << DDR_PHY_DX7GCR1_TEEN_SHIFT - | 0x00000001U << DDR_PHY_DX7GCR1_DSEN_SHIFT - | 0x00000001U << DDR_PHY_DX7GCR1_DMEN_SHIFT - | 0x000000FFU << DDR_PHY_DX7GCR1_DQEN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX7GCR1_OFFSET ,0xFFFFFFFFU ,0x00007FFFU); - /*############################################################################################################################ */ + * OX Extension during Post-amble + * PSU_DDR_PHY_DX8SL0DXCTL2_POSOEX 0x0 - /*Register : DX7GCR4 @ 0XFD080E10

+ * OE Extension during Pre-amble + * PSU_DDR_PHY_DX8SL0DXCTL2_PREOEX 0x1 - Byte lane VREF IOM (Used only by D4MU IOs) - PSU_DDR_PHY_DX7GCR4_RESERVED_31_29 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_17 0x0 - Byte Lane VREF Pad Enable - PSU_DDR_PHY_DX7GCR4_DXREFPEN 0x0 + * I/O Assisted Gate Select + * PSU_DDR_PHY_DX8SL0DXCTL2_IOAG 0x0 - Byte Lane Internal VREF Enable - PSU_DDR_PHY_DX7GCR4_DXREFEEN 0x3 + * I/O Loopback Select + * PSU_DDR_PHY_DX8SL0DXCTL2_IOLB 0x0 - Byte Lane Single-End VREF Enable - PSU_DDR_PHY_DX7GCR4_DXREFSEN 0x1 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX7GCR4_RESERVED_24 0x0 + * Low Power Wakeup Threshold + * PSU_DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH 0xc - External VREF generator REFSEL range select - PSU_DDR_PHY_DX7GCR4_DXREFESELRANGE 0x0 + * Read Data Bus Inversion Enable + * PSU_DDR_PHY_DX8SL0DXCTL2_RDBI 0x0 - Byte Lane External VREF Select - PSU_DDR_PHY_DX7GCR4_DXREFESEL 0x0 + * Write Data Bus Inversion Enable + * PSU_DDR_PHY_DX8SL0DXCTL2_WDBI 0x0 - Single ended VREF generator REFSEL range select - PSU_DDR_PHY_DX7GCR4_DXREFSSELRANGE 0x1 + * PUB Read FIFO Bypass + * PSU_DDR_PHY_DX8SL0DXCTL2_PRFBYP 0x0 - Byte Lane Single-End VREF Select - PSU_DDR_PHY_DX7GCR4_DXREFSSEL 0x30 + * DATX8 Receive FIFO Read Mode + * PSU_DDR_PHY_DX8SL0DXCTL2_RDMODE 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX7GCR4_RESERVED_7_6 0x0 + * Disables the Read FIFO Reset + * PSU_DDR_PHY_DX8SL0DXCTL2_DISRST 0x0 - VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. - PSU_DDR_PHY_DX7GCR4_DXREFIEN 0xf + * Read DQS Gate I/O Loopback + * PSU_DDR_PHY_DX8SL0DXCTL2_DQSGLB 0x0 - VRMON control for DQ IO (Single Ended) buffers of a byte lane. - PSU_DDR_PHY_DX7GCR4_DXREFIMON 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_0 0x0 - DATX8 n General Configuration Register 4 - (OFFSET, MASK, VALUE) (0XFD080E10, 0xFFFFFFFFU ,0x0E00B03CU) - RegMask = (DDR_PHY_DX7GCR4_RESERVED_31_29_MASK | DDR_PHY_DX7GCR4_DXREFPEN_MASK | DDR_PHY_DX7GCR4_DXREFEEN_MASK | DDR_PHY_DX7GCR4_DXREFSEN_MASK | DDR_PHY_DX7GCR4_RESERVED_24_MASK | DDR_PHY_DX7GCR4_DXREFESELRANGE_MASK | DDR_PHY_DX7GCR4_DXREFESEL_MASK | DDR_PHY_DX7GCR4_DXREFSSELRANGE_MASK | DDR_PHY_DX7GCR4_DXREFSSEL_MASK | DDR_PHY_DX7GCR4_RESERVED_7_6_MASK | DDR_PHY_DX7GCR4_DXREFIEN_MASK | DDR_PHY_DX7GCR4_DXREFIMON_MASK | 0 ); + * DATX8 0-1 DX Control Register 2 + * (OFFSET, MASK, VALUE) (0XFD08142C, 0xFFFFFFFFU ,0x00041800U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL0DXCTL2_OFFSET, + 0xFFFFFFFFU, 0x00041800U); +/*##################################################################### */ - RegVal = ((0x00000000U << DDR_PHY_DX7GCR4_RESERVED_31_29_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR4_DXREFPEN_SHIFT - | 0x00000003U << DDR_PHY_DX7GCR4_DXREFEEN_SHIFT - | 0x00000001U << DDR_PHY_DX7GCR4_DXREFSEN_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR4_RESERVED_24_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR4_DXREFESELRANGE_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR4_DXREFESEL_SHIFT - | 0x00000001U << DDR_PHY_DX7GCR4_DXREFSSELRANGE_SHIFT - | 0x00000030U << DDR_PHY_DX7GCR4_DXREFSSEL_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR4_RESERVED_7_6_SHIFT - | 0x0000000FU << DDR_PHY_DX7GCR4_DXREFIEN_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR4_DXREFIMON_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX7GCR4_OFFSET ,0xFFFFFFFFU ,0x0E00B03CU); - /*############################################################################################################################ */ + /* + * Register : DX8SL0IOCR @ 0XFD081430 - /*Register : DX7GCR5 @ 0XFD080E14

+ * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL0IOCR_RESERVED_31 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX7GCR5_RESERVED_31 0x0 + * PVREF_DAC REFSEL range select + * PSU_DDR_PHY_DX8SL0IOCR_DXDACRANGE 0x7 - Byte Lane internal VREF Select for Rank 3 - PSU_DDR_PHY_DX7GCR5_DXREFISELR3 0x9 + * IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring + * PSU_DDR_PHY_DX8SL0IOCR_DXVREFIOM 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX7GCR5_RESERVED_23 0x0 + * DX IO Mode + * PSU_DDR_PHY_DX8SL0IOCR_DXIOM 0x2 - Byte Lane internal VREF Select for Rank 2 - PSU_DDR_PHY_DX7GCR5_DXREFISELR2 0x9 + * DX IO Transmitter Mode + * PSU_DDR_PHY_DX8SL0IOCR_DXTXM 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX7GCR5_RESERVED_15 0x0 + * DX IO Receiver Mode + * PSU_DDR_PHY_DX8SL0IOCR_DXRXM 0x0 - Byte Lane internal VREF Select for Rank 1 - PSU_DDR_PHY_DX7GCR5_DXREFISELR1 0x4f + * DATX8 0-1 I/O Configuration Register + * (OFFSET, MASK, VALUE) (0XFD081430, 0xFFFFFFFFU ,0x70800000U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL0IOCR_OFFSET, 0xFFFFFFFFU, 0x70800000U); +/*##################################################################### */ - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX7GCR5_RESERVED_7 0x0 + /* + * Register : DX8SL1OSC @ 0XFD081440 - Byte Lane internal VREF Select for Rank 0 - PSU_DDR_PHY_DX7GCR5_DXREFISELR0 0x4f + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL1OSC_RESERVED_31_30 0x0 - DATX8 n General Configuration Register 5 - (OFFSET, MASK, VALUE) (0XFD080E14, 0xFFFFFFFFU ,0x09094F4FU) - RegMask = (DDR_PHY_DX7GCR5_RESERVED_31_MASK | DDR_PHY_DX7GCR5_DXREFISELR3_MASK | DDR_PHY_DX7GCR5_RESERVED_23_MASK | DDR_PHY_DX7GCR5_DXREFISELR2_MASK | DDR_PHY_DX7GCR5_RESERVED_15_MASK | DDR_PHY_DX7GCR5_DXREFISELR1_MASK | DDR_PHY_DX7GCR5_RESERVED_7_MASK | DDR_PHY_DX7GCR5_DXREFISELR0_MASK | 0 ); + * Enable Clock Gating for DX ddr_clk + * PSU_DDR_PHY_DX8SL1OSC_GATEDXRDCLK 0x2 - RegVal = ((0x00000000U << DDR_PHY_DX7GCR5_RESERVED_31_SHIFT - | 0x00000009U << DDR_PHY_DX7GCR5_DXREFISELR3_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR5_RESERVED_23_SHIFT - | 0x00000009U << DDR_PHY_DX7GCR5_DXREFISELR2_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR5_RESERVED_15_SHIFT - | 0x0000004FU << DDR_PHY_DX7GCR5_DXREFISELR1_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR5_RESERVED_7_SHIFT - | 0x0000004FU << DDR_PHY_DX7GCR5_DXREFISELR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX7GCR5_OFFSET ,0xFFFFFFFFU ,0x09094F4FU); - /*############################################################################################################################ */ + * Enable Clock Gating for DX ctl_rd_clk + * PSU_DDR_PHY_DX8SL1OSC_GATEDXDDRCLK 0x2 - /*Register : DX7GCR6 @ 0XFD080E18

+ * Enable Clock Gating for DX ctl_clk + * PSU_DDR_PHY_DX8SL1OSC_GATEDXCTLCLK 0x2 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX7GCR6_RESERVED_31_30 0x0 + * Selects the level to which clocks will be stalled when clock gating is e + * nabled. + * PSU_DDR_PHY_DX8SL1OSC_CLKLEVEL 0x0 - DRAM DQ VREF Select for Rank3 - PSU_DDR_PHY_DX7GCR6_DXDQVREFR3 0x9 + * Loopback Mode + * PSU_DDR_PHY_DX8SL1OSC_LBMODE 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX7GCR6_RESERVED_23_22 0x0 + * Load GSDQS LCDL with 2x the calibrated GSDQSPRD value + * PSU_DDR_PHY_DX8SL1OSC_LBGSDQS 0x0 - DRAM DQ VREF Select for Rank2 - PSU_DDR_PHY_DX7GCR6_DXDQVREFR2 0x9 + * Loopback DQS Gating + * PSU_DDR_PHY_DX8SL1OSC_LBGDQS 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX7GCR6_RESERVED_15_14 0x0 + * Loopback DQS Shift + * PSU_DDR_PHY_DX8SL1OSC_LBDQSS 0x0 - DRAM DQ VREF Select for Rank1 - PSU_DDR_PHY_DX7GCR6_DXDQVREFR1 0x2b + * PHY High-Speed Reset + * PSU_DDR_PHY_DX8SL1OSC_PHYHRST 0x1 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX7GCR6_RESERVED_7_6 0x0 + * PHY FIFO Reset + * PSU_DDR_PHY_DX8SL1OSC_PHYFRST 0x1 - DRAM DQ VREF Select for Rank0 - PSU_DDR_PHY_DX7GCR6_DXDQVREFR0 0x2b + * Delay Line Test Start + * PSU_DDR_PHY_DX8SL1OSC_DLTST 0x0 - DATX8 n General Configuration Register 6 - (OFFSET, MASK, VALUE) (0XFD080E18, 0xFFFFFFFFU ,0x09092B2BU) - RegMask = (DDR_PHY_DX7GCR6_RESERVED_31_30_MASK | DDR_PHY_DX7GCR6_DXDQVREFR3_MASK | DDR_PHY_DX7GCR6_RESERVED_23_22_MASK | DDR_PHY_DX7GCR6_DXDQVREFR2_MASK | DDR_PHY_DX7GCR6_RESERVED_15_14_MASK | DDR_PHY_DX7GCR6_DXDQVREFR1_MASK | DDR_PHY_DX7GCR6_RESERVED_7_6_MASK | DDR_PHY_DX7GCR6_DXDQVREFR0_MASK | 0 ); + * Delay Line Test Mode + * PSU_DDR_PHY_DX8SL1OSC_DLTMODE 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX7GCR6_RESERVED_31_30_SHIFT - | 0x00000009U << DDR_PHY_DX7GCR6_DXDQVREFR3_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR6_RESERVED_23_22_SHIFT - | 0x00000009U << DDR_PHY_DX7GCR6_DXDQVREFR2_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR6_RESERVED_15_14_SHIFT - | 0x0000002BU << DDR_PHY_DX7GCR6_DXDQVREFR1_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR6_RESERVED_7_6_SHIFT - | 0x0000002BU << DDR_PHY_DX7GCR6_DXDQVREFR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX7GCR6_OFFSET ,0xFFFFFFFFU ,0x09092B2BU); - /*############################################################################################################################ */ + * Reserved. Caution, do not write to this register field. + * PSU_DDR_PHY_DX8SL1OSC_RESERVED_12_11 0x3 - /*Register : DX7LCDLR2 @ 0XFD080E88

+ * Oscillator Mode Write-Data Delay Line Select + * PSU_DDR_PHY_DX8SL1OSC_OSCWDDL 0x3 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX7LCDLR2_RESERVED_31_25 0x0 + * Reserved. Caution, do not write to this register field. + * PSU_DDR_PHY_DX8SL1OSC_RESERVED_8_7 0x3 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX7LCDLR2_RESERVED_24_16 0x0 + * Oscillator Mode Write-Leveling Delay Line Select + * PSU_DDR_PHY_DX8SL1OSC_OSCWDL 0x3 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX7LCDLR2_RESERVED_15_9 0x0 + * Oscillator Mode Division + * PSU_DDR_PHY_DX8SL1OSC_OSCDIV 0xf - Read DQS Gating Delay - PSU_DDR_PHY_DX7LCDLR2_DQSGD 0xa + * Oscillator Enable + * PSU_DDR_PHY_DX8SL1OSC_OSCEN 0x0 - DATX8 n Local Calibrated Delay Line Register 2 - (OFFSET, MASK, VALUE) (0XFD080E88, 0xFFFFFFFFU ,0x0000000AU) - RegMask = (DDR_PHY_DX7LCDLR2_RESERVED_31_25_MASK | DDR_PHY_DX7LCDLR2_RESERVED_24_16_MASK | DDR_PHY_DX7LCDLR2_RESERVED_15_9_MASK | DDR_PHY_DX7LCDLR2_DQSGD_MASK | 0 ); + * DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Lo + * opback, and Gated Clock Control Register + * (OFFSET, MASK, VALUE) (0XFD081440, 0xFFFFFFFFU ,0x2A019FFEU) + */ + PSU_Mask_Write(DDR_PHY_DX8SL1OSC_OFFSET, 0xFFFFFFFFU, 0x2A019FFEU); +/*##################################################################### */ - RegVal = ((0x00000000U << DDR_PHY_DX7LCDLR2_RESERVED_31_25_SHIFT - | 0x00000000U << DDR_PHY_DX7LCDLR2_RESERVED_24_16_SHIFT - | 0x00000000U << DDR_PHY_DX7LCDLR2_RESERVED_15_9_SHIFT - | 0x0000000AU << DDR_PHY_DX7LCDLR2_DQSGD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX7LCDLR2_OFFSET ,0xFFFFFFFFU ,0x0000000AU); - /*############################################################################################################################ */ + /* + * Register : DX8SL1PLLCR0 @ 0XFD081444 - /*Register : DX7GTR0 @ 0XFD080EC0

+ * PLL Bypass + * PSU_DDR_PHY_DX8SL1PLLCR0_PLLBYP 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX7GTR0_RESERVED_31_24 0x0 + * PLL Reset + * PSU_DDR_PHY_DX8SL1PLLCR0_PLLRST 0x0 - DQ Write Path Latency Pipeline - PSU_DDR_PHY_DX7GTR0_WDQSL 0x0 + * PLL Power Down + * PSU_DDR_PHY_DX8SL1PLLCR0_PLLPD 0x0 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX7GTR0_RESERVED_23_20 0x0 + * Reference Stop Mode + * PSU_DDR_PHY_DX8SL1PLLCR0_RSTOPM 0x0 - Write Leveling System Latency - PSU_DDR_PHY_DX7GTR0_WLSL 0x2 + * PLL Frequency Select + * PSU_DDR_PHY_DX8SL1PLLCR0_FRQSEL 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX7GTR0_RESERVED_15_13 0x0 + * Relock Mode + * PSU_DDR_PHY_DX8SL1PLLCR0_RLOCKM 0x0 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX7GTR0_RESERVED_12_8 0x0 + * Charge Pump Proportional Current Control + * PSU_DDR_PHY_DX8SL1PLLCR0_CPPC 0x8 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX7GTR0_RESERVED_7_5 0x0 + * Charge Pump Integrating Current Control + * PSU_DDR_PHY_DX8SL1PLLCR0_CPIC 0x0 - DQS Gating System Latency - PSU_DDR_PHY_DX7GTR0_DGSL 0x0 + * Gear Shift + * PSU_DDR_PHY_DX8SL1PLLCR0_GSHIFT 0x0 - DATX8 n General Timing Register 0 - (OFFSET, MASK, VALUE) (0XFD080EC0, 0xFFFFFFFFU ,0x00020000U) - RegMask = (DDR_PHY_DX7GTR0_RESERVED_31_24_MASK | DDR_PHY_DX7GTR0_WDQSL_MASK | DDR_PHY_DX7GTR0_RESERVED_23_20_MASK | DDR_PHY_DX7GTR0_WLSL_MASK | DDR_PHY_DX7GTR0_RESERVED_15_13_MASK | DDR_PHY_DX7GTR0_RESERVED_12_8_MASK | DDR_PHY_DX7GTR0_RESERVED_7_5_MASK | DDR_PHY_DX7GTR0_DGSL_MASK | 0 ); + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL1PLLCR0_RESERVED_11_9 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX7GTR0_RESERVED_31_24_SHIFT - | 0x00000000U << DDR_PHY_DX7GTR0_WDQSL_SHIFT - | 0x00000000U << DDR_PHY_DX7GTR0_RESERVED_23_20_SHIFT - | 0x00000002U << DDR_PHY_DX7GTR0_WLSL_SHIFT - | 0x00000000U << DDR_PHY_DX7GTR0_RESERVED_15_13_SHIFT - | 0x00000000U << DDR_PHY_DX7GTR0_RESERVED_12_8_SHIFT - | 0x00000000U << DDR_PHY_DX7GTR0_RESERVED_7_5_SHIFT - | 0x00000000U << DDR_PHY_DX7GTR0_DGSL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX7GTR0_OFFSET ,0xFFFFFFFFU ,0x00020000U); - /*############################################################################################################################ */ + * Analog Test Enable (ATOEN) + * PSU_DDR_PHY_DX8SL1PLLCR0_ATOEN 0x0 - /*Register : DX8GCR0 @ 0XFD080F00

+ * Analog Test Control + * PSU_DDR_PHY_DX8SL1PLLCR0_ATC 0x0 - Calibration Bypass - PSU_DDR_PHY_DX8GCR0_CALBYP 0x0 + * Digital Test Control + * PSU_DDR_PHY_DX8SL1PLLCR0_DTC 0x0 - Master Delay Line Enable - PSU_DDR_PHY_DX8GCR0_MDLEN 0x1 + * DAXT8 0-1 PLL Control Register 0 + * (OFFSET, MASK, VALUE) (0XFD081444, 0xFFFFFFFFU ,0x01100000U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL1PLLCR0_OFFSET, + 0xFFFFFFFFU, 0x01100000U); +/*##################################################################### */ - Configurable ODT(TE) Phase Shift - PSU_DDR_PHY_DX8GCR0_CODTSHFT 0x0 + /* + * Register : DX8SL1DQSCTL @ 0XFD08145C - DQS Duty Cycle Correction - PSU_DDR_PHY_DX8GCR0_DQSDCC 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25 0x0 - Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY - PSU_DDR_PHY_DX8GCR0_RDDLY 0x8 + * Read Path Rise-to-Rise Mode + * PSU_DDR_PHY_DX8SL1DQSCTL_RRRMODE 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8GCR0_RESERVED_19_14 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22 0x0 - DQSNSE Power Down Receiver - PSU_DDR_PHY_DX8GCR0_DQSNSEPDR 0x0 + * Write Path Rise-to-Rise Mode + * PSU_DDR_PHY_DX8SL1DQSCTL_WRRMODE 0x1 - DQSSE Power Down Receiver - PSU_DDR_PHY_DX8GCR0_DQSSEPDR 0x0 + * DQS Gate Extension + * PSU_DDR_PHY_DX8SL1DQSCTL_DQSGX 0x0 - RTT On Additive Latency - PSU_DDR_PHY_DX8GCR0_RTTOAL 0x0 + * Low Power PLL Power Down + * PSU_DDR_PHY_DX8SL1DQSCTL_LPPLLPD 0x1 - RTT Output Hold - PSU_DDR_PHY_DX8GCR0_RTTOH 0x3 + * Low Power I/O Power Down + * PSU_DDR_PHY_DX8SL1DQSCTL_LPIOPD 0x1 - Configurable PDR Phase Shift - PSU_DDR_PHY_DX8GCR0_CPDRSHFT 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15 0x0 - DQSR Power Down - PSU_DDR_PHY_DX8GCR0_DQSRPD 0x0 + * QS Counter Enable + * PSU_DDR_PHY_DX8SL1DQSCTL_QSCNTEN 0x1 - DQSG Power Down Receiver - PSU_DDR_PHY_DX8GCR0_DQSGPDR 0x1 + * Unused DQ I/O Mode + * PSU_DDR_PHY_DX8SL1DQSCTL_UDQIOM 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8GCR0_RESERVED_4 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10 0x0 - DQSG On-Die Termination - PSU_DDR_PHY_DX8GCR0_DQSGODT 0x0 + * Data Slew Rate + * PSU_DDR_PHY_DX8SL1DQSCTL_DXSR 0x3 - DQSG Output Enable - PSU_DDR_PHY_DX8GCR0_DQSGOE 0x1 + * DQS_N Resistor + * PSU_DDR_PHY_DX8SL1DQSCTL_DQSNRES 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8GCR0_RESERVED_1_0 0x0 + * DQS Resistor + * PSU_DDR_PHY_DX8SL1DQSCTL_DQSRES 0x0 - DATX8 n General Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD080F00, 0xFFFFFFFFU ,0x40800624U) - RegMask = (DDR_PHY_DX8GCR0_CALBYP_MASK | DDR_PHY_DX8GCR0_MDLEN_MASK | DDR_PHY_DX8GCR0_CODTSHFT_MASK | DDR_PHY_DX8GCR0_DQSDCC_MASK | DDR_PHY_DX8GCR0_RDDLY_MASK | DDR_PHY_DX8GCR0_RESERVED_19_14_MASK | DDR_PHY_DX8GCR0_DQSNSEPDR_MASK | DDR_PHY_DX8GCR0_DQSSEPDR_MASK | DDR_PHY_DX8GCR0_RTTOAL_MASK | DDR_PHY_DX8GCR0_RTTOH_MASK | DDR_PHY_DX8GCR0_CPDRSHFT_MASK | DDR_PHY_DX8GCR0_DQSRPD_MASK | DDR_PHY_DX8GCR0_DQSGPDR_MASK | DDR_PHY_DX8GCR0_RESERVED_4_MASK | DDR_PHY_DX8GCR0_DQSGODT_MASK | DDR_PHY_DX8GCR0_DQSGOE_MASK | DDR_PHY_DX8GCR0_RESERVED_1_0_MASK | 0 ); + * DATX8 0-1 DQS Control Register + * (OFFSET, MASK, VALUE) (0XFD08145C, 0xFFFFFFFFU ,0x01264300U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL1DQSCTL_OFFSET, + 0xFFFFFFFFU, 0x01264300U); +/*##################################################################### */ - RegVal = ((0x00000000U << DDR_PHY_DX8GCR0_CALBYP_SHIFT - | 0x00000001U << DDR_PHY_DX8GCR0_MDLEN_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR0_CODTSHFT_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR0_DQSDCC_SHIFT - | 0x00000008U << DDR_PHY_DX8GCR0_RDDLY_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR0_RESERVED_19_14_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR0_DQSNSEPDR_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR0_DQSSEPDR_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR0_RTTOAL_SHIFT - | 0x00000003U << DDR_PHY_DX8GCR0_RTTOH_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR0_CPDRSHFT_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR0_DQSRPD_SHIFT - | 0x00000001U << DDR_PHY_DX8GCR0_DQSGPDR_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR0_RESERVED_4_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR0_DQSGODT_SHIFT - | 0x00000001U << DDR_PHY_DX8GCR0_DQSGOE_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR0_RESERVED_1_0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8GCR0_OFFSET ,0xFFFFFFFFU ,0x40800624U); - /*############################################################################################################################ */ + /* + * Register : DX8SL1DXCTL2 @ 0XFD08146C - /*Register : DX8GCR1 @ 0XFD080F04

+ * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24 0x0 - Enables the PDR mode for DQ[7:0] - PSU_DDR_PHY_DX8GCR1_DXPDRMODE 0x0 + * Configurable Read Data Enable + * PSU_DDR_PHY_DX8SL1DXCTL2_CRDEN 0x0 - Reserved. Returns zeroes on reads. - PSU_DDR_PHY_DX8GCR1_RESERVED_15 0x0 + * OX Extension during Post-amble + * PSU_DDR_PHY_DX8SL1DXCTL2_POSOEX 0x0 - Select the delayed or non-delayed read data strobe # - PSU_DDR_PHY_DX8GCR1_QSNSEL 0x1 + * OE Extension during Pre-amble + * PSU_DDR_PHY_DX8SL1DXCTL2_PREOEX 0x1 - Select the delayed or non-delayed read data strobe - PSU_DDR_PHY_DX8GCR1_QSSEL 0x1 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_17 0x0 - Enables Read Data Strobe in a byte lane - PSU_DDR_PHY_DX8GCR1_OEEN 0x1 + * I/O Assisted Gate Select + * PSU_DDR_PHY_DX8SL1DXCTL2_IOAG 0x0 - Enables PDR in a byte lane - PSU_DDR_PHY_DX8GCR1_PDREN 0x1 + * I/O Loopback Select + * PSU_DDR_PHY_DX8SL1DXCTL2_IOLB 0x0 - Enables ODT/TE in a byte lane - PSU_DDR_PHY_DX8GCR1_TEEN 0x1 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13 0x0 - Enables Write Data strobe in a byte lane - PSU_DDR_PHY_DX8GCR1_DSEN 0x1 + * Low Power Wakeup Threshold + * PSU_DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH 0xc - Enables DM pin in a byte lane - PSU_DDR_PHY_DX8GCR1_DMEN 0x1 + * Read Data Bus Inversion Enable + * PSU_DDR_PHY_DX8SL1DXCTL2_RDBI 0x0 - Enables DQ corresponding to each bit in a byte - PSU_DDR_PHY_DX8GCR1_DQEN 0x0 + * Write Data Bus Inversion Enable + * PSU_DDR_PHY_DX8SL1DXCTL2_WDBI 0x0 - DATX8 n General Configuration Register 1 - (OFFSET, MASK, VALUE) (0XFD080F04, 0xFFFFFFFFU ,0x00007F00U) - RegMask = (DDR_PHY_DX8GCR1_DXPDRMODE_MASK | DDR_PHY_DX8GCR1_RESERVED_15_MASK | DDR_PHY_DX8GCR1_QSNSEL_MASK | DDR_PHY_DX8GCR1_QSSEL_MASK | DDR_PHY_DX8GCR1_OEEN_MASK | DDR_PHY_DX8GCR1_PDREN_MASK | DDR_PHY_DX8GCR1_TEEN_MASK | DDR_PHY_DX8GCR1_DSEN_MASK | DDR_PHY_DX8GCR1_DMEN_MASK | DDR_PHY_DX8GCR1_DQEN_MASK | 0 ); + * PUB Read FIFO Bypass + * PSU_DDR_PHY_DX8SL1DXCTL2_PRFBYP 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX8GCR1_DXPDRMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR1_RESERVED_15_SHIFT - | 0x00000001U << DDR_PHY_DX8GCR1_QSNSEL_SHIFT - | 0x00000001U << DDR_PHY_DX8GCR1_QSSEL_SHIFT - | 0x00000001U << DDR_PHY_DX8GCR1_OEEN_SHIFT - | 0x00000001U << DDR_PHY_DX8GCR1_PDREN_SHIFT - | 0x00000001U << DDR_PHY_DX8GCR1_TEEN_SHIFT - | 0x00000001U << DDR_PHY_DX8GCR1_DSEN_SHIFT - | 0x00000001U << DDR_PHY_DX8GCR1_DMEN_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR1_DQEN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8GCR1_OFFSET ,0xFFFFFFFFU ,0x00007F00U); - /*############################################################################################################################ */ + * DATX8 Receive FIFO Read Mode + * PSU_DDR_PHY_DX8SL1DXCTL2_RDMODE 0x0 - /*Register : DX8GCR4 @ 0XFD080F10

+ * Disables the Read FIFO Reset + * PSU_DDR_PHY_DX8SL1DXCTL2_DISRST 0x0 - Byte lane VREF IOM (Used only by D4MU IOs) - PSU_DDR_PHY_DX8GCR4_RESERVED_31_29 0x0 + * Read DQS Gate I/O Loopback + * PSU_DDR_PHY_DX8SL1DXCTL2_DQSGLB 0x0 - Byte Lane VREF Pad Enable - PSU_DDR_PHY_DX8GCR4_DXREFPEN 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_0 0x0 - Byte Lane Internal VREF Enable - PSU_DDR_PHY_DX8GCR4_DXREFEEN 0x3 + * DATX8 0-1 DX Control Register 2 + * (OFFSET, MASK, VALUE) (0XFD08146C, 0xFFFFFFFFU ,0x00041800U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL1DXCTL2_OFFSET, + 0xFFFFFFFFU, 0x00041800U); +/*##################################################################### */ - Byte Lane Single-End VREF Enable - PSU_DDR_PHY_DX8GCR4_DXREFSEN 0x1 + /* + * Register : DX8SL1IOCR @ 0XFD081470 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX8GCR4_RESERVED_24 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL1IOCR_RESERVED_31 0x0 - External VREF generator REFSEL range select - PSU_DDR_PHY_DX8GCR4_DXREFESELRANGE 0x0 + * PVREF_DAC REFSEL range select + * PSU_DDR_PHY_DX8SL1IOCR_DXDACRANGE 0x7 - Byte Lane External VREF Select - PSU_DDR_PHY_DX8GCR4_DXREFESEL 0x0 + * IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring + * PSU_DDR_PHY_DX8SL1IOCR_DXVREFIOM 0x0 - Single ended VREF generator REFSEL range select - PSU_DDR_PHY_DX8GCR4_DXREFSSELRANGE 0x1 + * DX IO Mode + * PSU_DDR_PHY_DX8SL1IOCR_DXIOM 0x2 - Byte Lane Single-End VREF Select - PSU_DDR_PHY_DX8GCR4_DXREFSSEL 0x30 + * DX IO Transmitter Mode + * PSU_DDR_PHY_DX8SL1IOCR_DXTXM 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX8GCR4_RESERVED_7_6 0x0 + * DX IO Receiver Mode + * PSU_DDR_PHY_DX8SL1IOCR_DXRXM 0x0 - VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. - PSU_DDR_PHY_DX8GCR4_DXREFIEN 0xf + * DATX8 0-1 I/O Configuration Register + * (OFFSET, MASK, VALUE) (0XFD081470, 0xFFFFFFFFU ,0x70800000U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL1IOCR_OFFSET, 0xFFFFFFFFU, 0x70800000U); +/*##################################################################### */ - VRMON control for DQ IO (Single Ended) buffers of a byte lane. - PSU_DDR_PHY_DX8GCR4_DXREFIMON 0x0 + /* + * Register : DX8SL2OSC @ 0XFD081480 - DATX8 n General Configuration Register 4 - (OFFSET, MASK, VALUE) (0XFD080F10, 0xFFFFFFFFU ,0x0E00B03CU) - RegMask = (DDR_PHY_DX8GCR4_RESERVED_31_29_MASK | DDR_PHY_DX8GCR4_DXREFPEN_MASK | DDR_PHY_DX8GCR4_DXREFEEN_MASK | DDR_PHY_DX8GCR4_DXREFSEN_MASK | DDR_PHY_DX8GCR4_RESERVED_24_MASK | DDR_PHY_DX8GCR4_DXREFESELRANGE_MASK | DDR_PHY_DX8GCR4_DXREFESEL_MASK | DDR_PHY_DX8GCR4_DXREFSSELRANGE_MASK | DDR_PHY_DX8GCR4_DXREFSSEL_MASK | DDR_PHY_DX8GCR4_RESERVED_7_6_MASK | DDR_PHY_DX8GCR4_DXREFIEN_MASK | DDR_PHY_DX8GCR4_DXREFIMON_MASK | 0 ); + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL2OSC_RESERVED_31_30 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX8GCR4_RESERVED_31_29_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR4_DXREFPEN_SHIFT - | 0x00000003U << DDR_PHY_DX8GCR4_DXREFEEN_SHIFT - | 0x00000001U << DDR_PHY_DX8GCR4_DXREFSEN_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR4_RESERVED_24_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR4_DXREFESELRANGE_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR4_DXREFESEL_SHIFT - | 0x00000001U << DDR_PHY_DX8GCR4_DXREFSSELRANGE_SHIFT - | 0x00000030U << DDR_PHY_DX8GCR4_DXREFSSEL_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR4_RESERVED_7_6_SHIFT - | 0x0000000FU << DDR_PHY_DX8GCR4_DXREFIEN_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR4_DXREFIMON_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8GCR4_OFFSET ,0xFFFFFFFFU ,0x0E00B03CU); - /*############################################################################################################################ */ + * Enable Clock Gating for DX ddr_clk + * PSU_DDR_PHY_DX8SL2OSC_GATEDXRDCLK 0x2 - /*Register : DX8GCR5 @ 0XFD080F14

+ * Enable Clock Gating for DX ctl_rd_clk + * PSU_DDR_PHY_DX8SL2OSC_GATEDXDDRCLK 0x2 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX8GCR5_RESERVED_31 0x0 + * Enable Clock Gating for DX ctl_clk + * PSU_DDR_PHY_DX8SL2OSC_GATEDXCTLCLK 0x2 - Byte Lane internal VREF Select for Rank 3 - PSU_DDR_PHY_DX8GCR5_DXREFISELR3 0x9 + * Selects the level to which clocks will be stalled when clock gating is e + * nabled. + * PSU_DDR_PHY_DX8SL2OSC_CLKLEVEL 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX8GCR5_RESERVED_23 0x0 + * Loopback Mode + * PSU_DDR_PHY_DX8SL2OSC_LBMODE 0x0 - Byte Lane internal VREF Select for Rank 2 - PSU_DDR_PHY_DX8GCR5_DXREFISELR2 0x9 + * Load GSDQS LCDL with 2x the calibrated GSDQSPRD value + * PSU_DDR_PHY_DX8SL2OSC_LBGSDQS 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX8GCR5_RESERVED_15 0x0 + * Loopback DQS Gating + * PSU_DDR_PHY_DX8SL2OSC_LBGDQS 0x0 - Byte Lane internal VREF Select for Rank 1 - PSU_DDR_PHY_DX8GCR5_DXREFISELR1 0x4f + * Loopback DQS Shift + * PSU_DDR_PHY_DX8SL2OSC_LBDQSS 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX8GCR5_RESERVED_7 0x0 + * PHY High-Speed Reset + * PSU_DDR_PHY_DX8SL2OSC_PHYHRST 0x1 - Byte Lane internal VREF Select for Rank 0 - PSU_DDR_PHY_DX8GCR5_DXREFISELR0 0x4f + * PHY FIFO Reset + * PSU_DDR_PHY_DX8SL2OSC_PHYFRST 0x1 - DATX8 n General Configuration Register 5 - (OFFSET, MASK, VALUE) (0XFD080F14, 0xFFFFFFFFU ,0x09094F4FU) - RegMask = (DDR_PHY_DX8GCR5_RESERVED_31_MASK | DDR_PHY_DX8GCR5_DXREFISELR3_MASK | DDR_PHY_DX8GCR5_RESERVED_23_MASK | DDR_PHY_DX8GCR5_DXREFISELR2_MASK | DDR_PHY_DX8GCR5_RESERVED_15_MASK | DDR_PHY_DX8GCR5_DXREFISELR1_MASK | DDR_PHY_DX8GCR5_RESERVED_7_MASK | DDR_PHY_DX8GCR5_DXREFISELR0_MASK | 0 ); + * Delay Line Test Start + * PSU_DDR_PHY_DX8SL2OSC_DLTST 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX8GCR5_RESERVED_31_SHIFT - | 0x00000009U << DDR_PHY_DX8GCR5_DXREFISELR3_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR5_RESERVED_23_SHIFT - | 0x00000009U << DDR_PHY_DX8GCR5_DXREFISELR2_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR5_RESERVED_15_SHIFT - | 0x0000004FU << DDR_PHY_DX8GCR5_DXREFISELR1_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR5_RESERVED_7_SHIFT - | 0x0000004FU << DDR_PHY_DX8GCR5_DXREFISELR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8GCR5_OFFSET ,0xFFFFFFFFU ,0x09094F4FU); - /*############################################################################################################################ */ + * Delay Line Test Mode + * PSU_DDR_PHY_DX8SL2OSC_DLTMODE 0x0 - /*Register : DX8GCR6 @ 0XFD080F18

+ * Reserved. Caution, do not write to this register field. + * PSU_DDR_PHY_DX8SL2OSC_RESERVED_12_11 0x3 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX8GCR6_RESERVED_31_30 0x0 + * Oscillator Mode Write-Data Delay Line Select + * PSU_DDR_PHY_DX8SL2OSC_OSCWDDL 0x3 - DRAM DQ VREF Select for Rank3 - PSU_DDR_PHY_DX8GCR6_DXDQVREFR3 0x9 + * Reserved. Caution, do not write to this register field. + * PSU_DDR_PHY_DX8SL2OSC_RESERVED_8_7 0x3 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX8GCR6_RESERVED_23_22 0x0 + * Oscillator Mode Write-Leveling Delay Line Select + * PSU_DDR_PHY_DX8SL2OSC_OSCWDL 0x3 - DRAM DQ VREF Select for Rank2 - PSU_DDR_PHY_DX8GCR6_DXDQVREFR2 0x9 + * Oscillator Mode Division + * PSU_DDR_PHY_DX8SL2OSC_OSCDIV 0xf - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX8GCR6_RESERVED_15_14 0x0 + * Oscillator Enable + * PSU_DDR_PHY_DX8SL2OSC_OSCEN 0x0 - DRAM DQ VREF Select for Rank1 - PSU_DDR_PHY_DX8GCR6_DXDQVREFR1 0x2b + * DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Lo + * opback, and Gated Clock Control Register + * (OFFSET, MASK, VALUE) (0XFD081480, 0xFFFFFFFFU ,0x2A019FFEU) + */ + PSU_Mask_Write(DDR_PHY_DX8SL2OSC_OFFSET, 0xFFFFFFFFU, 0x2A019FFEU); +/*##################################################################### */ - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX8GCR6_RESERVED_7_6 0x0 + /* + * Register : DX8SL2PLLCR0 @ 0XFD081484 - DRAM DQ VREF Select for Rank0 - PSU_DDR_PHY_DX8GCR6_DXDQVREFR0 0x2b + * PLL Bypass + * PSU_DDR_PHY_DX8SL2PLLCR0_PLLBYP 0x0 - DATX8 n General Configuration Register 6 - (OFFSET, MASK, VALUE) (0XFD080F18, 0xFFFFFFFFU ,0x09092B2BU) - RegMask = (DDR_PHY_DX8GCR6_RESERVED_31_30_MASK | DDR_PHY_DX8GCR6_DXDQVREFR3_MASK | DDR_PHY_DX8GCR6_RESERVED_23_22_MASK | DDR_PHY_DX8GCR6_DXDQVREFR2_MASK | DDR_PHY_DX8GCR6_RESERVED_15_14_MASK | DDR_PHY_DX8GCR6_DXDQVREFR1_MASK | DDR_PHY_DX8GCR6_RESERVED_7_6_MASK | DDR_PHY_DX8GCR6_DXDQVREFR0_MASK | 0 ); + * PLL Reset + * PSU_DDR_PHY_DX8SL2PLLCR0_PLLRST 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX8GCR6_RESERVED_31_30_SHIFT - | 0x00000009U << DDR_PHY_DX8GCR6_DXDQVREFR3_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR6_RESERVED_23_22_SHIFT - | 0x00000009U << DDR_PHY_DX8GCR6_DXDQVREFR2_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR6_RESERVED_15_14_SHIFT - | 0x0000002BU << DDR_PHY_DX8GCR6_DXDQVREFR1_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR6_RESERVED_7_6_SHIFT - | 0x0000002BU << DDR_PHY_DX8GCR6_DXDQVREFR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8GCR6_OFFSET ,0xFFFFFFFFU ,0x09092B2BU); - /*############################################################################################################################ */ + * PLL Power Down + * PSU_DDR_PHY_DX8SL2PLLCR0_PLLPD 0x0 - /*Register : DX8LCDLR2 @ 0XFD080F88

+ * Reference Stop Mode + * PSU_DDR_PHY_DX8SL2PLLCR0_RSTOPM 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8LCDLR2_RESERVED_31_25 0x0 + * PLL Frequency Select + * PSU_DDR_PHY_DX8SL2PLLCR0_FRQSEL 0x1 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX8LCDLR2_RESERVED_24_16 0x0 + * Relock Mode + * PSU_DDR_PHY_DX8SL2PLLCR0_RLOCKM 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8LCDLR2_RESERVED_15_9 0x0 + * Charge Pump Proportional Current Control + * PSU_DDR_PHY_DX8SL2PLLCR0_CPPC 0x8 - Read DQS Gating Delay - PSU_DDR_PHY_DX8LCDLR2_DQSGD 0x0 + * Charge Pump Integrating Current Control + * PSU_DDR_PHY_DX8SL2PLLCR0_CPIC 0x0 - DATX8 n Local Calibrated Delay Line Register 2 - (OFFSET, MASK, VALUE) (0XFD080F88, 0xFFFFFFFFU ,0x00000000U) - RegMask = (DDR_PHY_DX8LCDLR2_RESERVED_31_25_MASK | DDR_PHY_DX8LCDLR2_RESERVED_24_16_MASK | DDR_PHY_DX8LCDLR2_RESERVED_15_9_MASK | DDR_PHY_DX8LCDLR2_DQSGD_MASK | 0 ); + * Gear Shift + * PSU_DDR_PHY_DX8SL2PLLCR0_GSHIFT 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX8LCDLR2_RESERVED_31_25_SHIFT - | 0x00000000U << DDR_PHY_DX8LCDLR2_RESERVED_24_16_SHIFT - | 0x00000000U << DDR_PHY_DX8LCDLR2_RESERVED_15_9_SHIFT - | 0x00000000U << DDR_PHY_DX8LCDLR2_DQSGD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8LCDLR2_OFFSET ,0xFFFFFFFFU ,0x00000000U); - /*############################################################################################################################ */ + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL2PLLCR0_RESERVED_11_9 0x0 - /*Register : DX8GTR0 @ 0XFD080FC0

+ * Analog Test Enable (ATOEN) + * PSU_DDR_PHY_DX8SL2PLLCR0_ATOEN 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8GTR0_RESERVED_31_24 0x0 + * Analog Test Control + * PSU_DDR_PHY_DX8SL2PLLCR0_ATC 0x0 - DQ Write Path Latency Pipeline - PSU_DDR_PHY_DX8GTR0_WDQSL 0x0 + * Digital Test Control + * PSU_DDR_PHY_DX8SL2PLLCR0_DTC 0x0 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX8GTR0_RESERVED_23_20 0x0 + * DAXT8 0-1 PLL Control Register 0 + * (OFFSET, MASK, VALUE) (0XFD081484, 0xFFFFFFFFU ,0x01100000U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL2PLLCR0_OFFSET, + 0xFFFFFFFFU, 0x01100000U); +/*##################################################################### */ - Write Leveling System Latency - PSU_DDR_PHY_DX8GTR0_WLSL 0x2 + /* + * Register : DX8SL2DQSCTL @ 0XFD08149C - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8GTR0_RESERVED_15_13 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25 0x0 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX8GTR0_RESERVED_12_8 0x0 + * Read Path Rise-to-Rise Mode + * PSU_DDR_PHY_DX8SL2DQSCTL_RRRMODE 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8GTR0_RESERVED_7_5 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22 0x0 - DQS Gating System Latency - PSU_DDR_PHY_DX8GTR0_DGSL 0x0 + * Write Path Rise-to-Rise Mode + * PSU_DDR_PHY_DX8SL2DQSCTL_WRRMODE 0x1 - DATX8 n General Timing Register 0 - (OFFSET, MASK, VALUE) (0XFD080FC0, 0xFFFFFFFFU ,0x00020000U) - RegMask = (DDR_PHY_DX8GTR0_RESERVED_31_24_MASK | DDR_PHY_DX8GTR0_WDQSL_MASK | DDR_PHY_DX8GTR0_RESERVED_23_20_MASK | DDR_PHY_DX8GTR0_WLSL_MASK | DDR_PHY_DX8GTR0_RESERVED_15_13_MASK | DDR_PHY_DX8GTR0_RESERVED_12_8_MASK | DDR_PHY_DX8GTR0_RESERVED_7_5_MASK | DDR_PHY_DX8GTR0_DGSL_MASK | 0 ); + * DQS Gate Extension + * PSU_DDR_PHY_DX8SL2DQSCTL_DQSGX 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX8GTR0_RESERVED_31_24_SHIFT - | 0x00000000U << DDR_PHY_DX8GTR0_WDQSL_SHIFT - | 0x00000000U << DDR_PHY_DX8GTR0_RESERVED_23_20_SHIFT - | 0x00000002U << DDR_PHY_DX8GTR0_WLSL_SHIFT - | 0x00000000U << DDR_PHY_DX8GTR0_RESERVED_15_13_SHIFT - | 0x00000000U << DDR_PHY_DX8GTR0_RESERVED_12_8_SHIFT - | 0x00000000U << DDR_PHY_DX8GTR0_RESERVED_7_5_SHIFT - | 0x00000000U << DDR_PHY_DX8GTR0_DGSL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8GTR0_OFFSET ,0xFFFFFFFFU ,0x00020000U); - /*############################################################################################################################ */ + * Low Power PLL Power Down + * PSU_DDR_PHY_DX8SL2DQSCTL_LPPLLPD 0x1 - /*Register : DX8SL0OSC @ 0XFD081400

+ * Low Power I/O Power Down + * PSU_DDR_PHY_DX8SL2DQSCTL_LPIOPD 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL0OSC_RESERVED_31_30 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15 0x0 - Enable Clock Gating for DX ddr_clk - PSU_DDR_PHY_DX8SL0OSC_GATEDXRDCLK 0x2 + * QS Counter Enable + * PSU_DDR_PHY_DX8SL2DQSCTL_QSCNTEN 0x1 - Enable Clock Gating for DX ctl_rd_clk - PSU_DDR_PHY_DX8SL0OSC_GATEDXDDRCLK 0x2 + * Unused DQ I/O Mode + * PSU_DDR_PHY_DX8SL2DQSCTL_UDQIOM 0x0 - Enable Clock Gating for DX ctl_clk - PSU_DDR_PHY_DX8SL0OSC_GATEDXCTLCLK 0x2 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10 0x0 - Selects the level to which clocks will be stalled when clock gating is enabled. - PSU_DDR_PHY_DX8SL0OSC_CLKLEVEL 0x0 + * Data Slew Rate + * PSU_DDR_PHY_DX8SL2DQSCTL_DXSR 0x3 - Loopback Mode - PSU_DDR_PHY_DX8SL0OSC_LBMODE 0x0 + * DQS_N Resistor + * PSU_DDR_PHY_DX8SL2DQSCTL_DQSNRES 0x0 - Load GSDQS LCDL with 2x the calibrated GSDQSPRD value - PSU_DDR_PHY_DX8SL0OSC_LBGSDQS 0x0 + * DQS Resistor + * PSU_DDR_PHY_DX8SL2DQSCTL_DQSRES 0x0 - Loopback DQS Gating - PSU_DDR_PHY_DX8SL0OSC_LBGDQS 0x0 + * DATX8 0-1 DQS Control Register + * (OFFSET, MASK, VALUE) (0XFD08149C, 0xFFFFFFFFU ,0x01264300U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL2DQSCTL_OFFSET, + 0xFFFFFFFFU, 0x01264300U); +/*##################################################################### */ - Loopback DQS Shift - PSU_DDR_PHY_DX8SL0OSC_LBDQSS 0x0 + /* + * Register : DX8SL2DXCTL2 @ 0XFD0814AC - PHY High-Speed Reset - PSU_DDR_PHY_DX8SL0OSC_PHYHRST 0x1 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24 0x0 - PHY FIFO Reset - PSU_DDR_PHY_DX8SL0OSC_PHYFRST 0x1 + * Configurable Read Data Enable + * PSU_DDR_PHY_DX8SL2DXCTL2_CRDEN 0x0 - Delay Line Test Start - PSU_DDR_PHY_DX8SL0OSC_DLTST 0x0 + * OX Extension during Post-amble + * PSU_DDR_PHY_DX8SL2DXCTL2_POSOEX 0x0 - Delay Line Test Mode - PSU_DDR_PHY_DX8SL0OSC_DLTMODE 0x0 + * OE Extension during Pre-amble + * PSU_DDR_PHY_DX8SL2DXCTL2_PREOEX 0x1 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX8SL0OSC_RESERVED_12_11 0x3 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_17 0x0 - Oscillator Mode Write-Data Delay Line Select - PSU_DDR_PHY_DX8SL0OSC_OSCWDDL 0x3 + * I/O Assisted Gate Select + * PSU_DDR_PHY_DX8SL2DXCTL2_IOAG 0x0 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX8SL0OSC_RESERVED_8_7 0x3 + * I/O Loopback Select + * PSU_DDR_PHY_DX8SL2DXCTL2_IOLB 0x0 - Oscillator Mode Write-Leveling Delay Line Select - PSU_DDR_PHY_DX8SL0OSC_OSCWDL 0x3 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13 0x0 - Oscillator Mode Division - PSU_DDR_PHY_DX8SL0OSC_OSCDIV 0xf + * Low Power Wakeup Threshold + * PSU_DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH 0xc - Oscillator Enable - PSU_DDR_PHY_DX8SL0OSC_OSCEN 0x0 + * Read Data Bus Inversion Enable + * PSU_DDR_PHY_DX8SL2DXCTL2_RDBI 0x0 - DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register - (OFFSET, MASK, VALUE) (0XFD081400, 0xFFFFFFFFU ,0x2A019FFEU) - RegMask = (DDR_PHY_DX8SL0OSC_RESERVED_31_30_MASK | DDR_PHY_DX8SL0OSC_GATEDXRDCLK_MASK | DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_MASK | DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_MASK | DDR_PHY_DX8SL0OSC_CLKLEVEL_MASK | DDR_PHY_DX8SL0OSC_LBMODE_MASK | DDR_PHY_DX8SL0OSC_LBGSDQS_MASK | DDR_PHY_DX8SL0OSC_LBGDQS_MASK | DDR_PHY_DX8SL0OSC_LBDQSS_MASK | DDR_PHY_DX8SL0OSC_PHYHRST_MASK | DDR_PHY_DX8SL0OSC_PHYFRST_MASK | DDR_PHY_DX8SL0OSC_DLTST_MASK | DDR_PHY_DX8SL0OSC_DLTMODE_MASK | DDR_PHY_DX8SL0OSC_RESERVED_12_11_MASK | DDR_PHY_DX8SL0OSC_OSCWDDL_MASK | DDR_PHY_DX8SL0OSC_RESERVED_8_7_MASK | DDR_PHY_DX8SL0OSC_OSCWDL_MASK | DDR_PHY_DX8SL0OSC_OSCDIV_MASK | DDR_PHY_DX8SL0OSC_OSCEN_MASK | 0 ); + * Write Data Bus Inversion Enable + * PSU_DDR_PHY_DX8SL2DXCTL2_WDBI 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX8SL0OSC_RESERVED_31_30_SHIFT - | 0x00000002U << DDR_PHY_DX8SL0OSC_GATEDXRDCLK_SHIFT - | 0x00000002U << DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_SHIFT - | 0x00000002U << DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0OSC_CLKLEVEL_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0OSC_LBMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0OSC_LBGSDQS_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0OSC_LBGDQS_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0OSC_LBDQSS_SHIFT - | 0x00000001U << DDR_PHY_DX8SL0OSC_PHYHRST_SHIFT - | 0x00000001U << DDR_PHY_DX8SL0OSC_PHYFRST_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0OSC_DLTST_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0OSC_DLTMODE_SHIFT - | 0x00000003U << DDR_PHY_DX8SL0OSC_RESERVED_12_11_SHIFT - | 0x00000003U << DDR_PHY_DX8SL0OSC_OSCWDDL_SHIFT - | 0x00000003U << DDR_PHY_DX8SL0OSC_RESERVED_8_7_SHIFT - | 0x00000003U << DDR_PHY_DX8SL0OSC_OSCWDL_SHIFT - | 0x0000000FU << DDR_PHY_DX8SL0OSC_OSCDIV_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0OSC_OSCEN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8SL0OSC_OFFSET ,0xFFFFFFFFU ,0x2A019FFEU); - /*############################################################################################################################ */ + * PUB Read FIFO Bypass + * PSU_DDR_PHY_DX8SL2DXCTL2_PRFBYP 0x0 - /*Register : DX8SL0DQSCTL @ 0XFD08141C

+ * DATX8 Receive FIFO Read Mode + * PSU_DDR_PHY_DX8SL2DXCTL2_RDMODE 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25 0x0 + * Disables the Read FIFO Reset + * PSU_DDR_PHY_DX8SL2DXCTL2_DISRST 0x0 - Read Path Rise-to-Rise Mode - PSU_DDR_PHY_DX8SL0DQSCTL_RRRMODE 0x1 + * Read DQS Gate I/O Loopback + * PSU_DDR_PHY_DX8SL2DXCTL2_DQSGLB 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_0 0x0 - Write Path Rise-to-Rise Mode - PSU_DDR_PHY_DX8SL0DQSCTL_WRRMODE 0x1 + * DATX8 0-1 DX Control Register 2 + * (OFFSET, MASK, VALUE) (0XFD0814AC, 0xFFFFFFFFU ,0x00041800U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL2DXCTL2_OFFSET, + 0xFFFFFFFFU, 0x00041800U); +/*##################################################################### */ - DQS Gate Extension - PSU_DDR_PHY_DX8SL0DQSCTL_DQSGX 0x0 + /* + * Register : DX8SL2IOCR @ 0XFD0814B0 - Low Power PLL Power Down - PSU_DDR_PHY_DX8SL0DQSCTL_LPPLLPD 0x1 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL2IOCR_RESERVED_31 0x0 - Low Power I/O Power Down - PSU_DDR_PHY_DX8SL0DQSCTL_LPIOPD 0x1 + * PVREF_DAC REFSEL range select + * PSU_DDR_PHY_DX8SL2IOCR_DXDACRANGE 0x7 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15 0x0 + * IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring + * PSU_DDR_PHY_DX8SL2IOCR_DXVREFIOM 0x0 - QS Counter Enable - PSU_DDR_PHY_DX8SL0DQSCTL_QSCNTEN 0x1 + * DX IO Mode + * PSU_DDR_PHY_DX8SL2IOCR_DXIOM 0x2 - Unused DQ I/O Mode - PSU_DDR_PHY_DX8SL0DQSCTL_UDQIOM 0x0 + * DX IO Transmitter Mode + * PSU_DDR_PHY_DX8SL2IOCR_DXTXM 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10 0x0 + * DX IO Receiver Mode + * PSU_DDR_PHY_DX8SL2IOCR_DXRXM 0x0 - Data Slew Rate - PSU_DDR_PHY_DX8SL0DQSCTL_DXSR 0x3 - - DQS_N Resistor - PSU_DDR_PHY_DX8SL0DQSCTL_DQSNRES 0x0 - - DQS Resistor - PSU_DDR_PHY_DX8SL0DQSCTL_DQSRES 0x0 - - DATX8 0-1 DQS Control Register - (OFFSET, MASK, VALUE) (0XFD08141C, 0xFFFFFFFFU ,0x01264300U) - RegMask = (DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_MASK | DDR_PHY_DX8SL0DQSCTL_RRRMODE_MASK | DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_MASK | DDR_PHY_DX8SL0DQSCTL_WRRMODE_MASK | DDR_PHY_DX8SL0DQSCTL_DQSGX_MASK | DDR_PHY_DX8SL0DQSCTL_LPPLLPD_MASK | DDR_PHY_DX8SL0DQSCTL_LPIOPD_MASK | DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_MASK | DDR_PHY_DX8SL0DQSCTL_QSCNTEN_MASK | DDR_PHY_DX8SL0DQSCTL_UDQIOM_MASK | DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_MASK | DDR_PHY_DX8SL0DQSCTL_DXSR_MASK | DDR_PHY_DX8SL0DQSCTL_DQSNRES_MASK | DDR_PHY_DX8SL0DQSCTL_DQSRES_MASK | 0 ); + * DATX8 0-1 I/O Configuration Register + * (OFFSET, MASK, VALUE) (0XFD0814B0, 0xFFFFFFFFU ,0x70800000U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL2IOCR_OFFSET, 0xFFFFFFFFU, 0x70800000U); +/*##################################################################### */ - RegVal = ((0x00000000U << DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_SHIFT - | 0x00000001U << DDR_PHY_DX8SL0DQSCTL_RRRMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_SHIFT - | 0x00000001U << DDR_PHY_DX8SL0DQSCTL_WRRMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0DQSCTL_DQSGX_SHIFT - | 0x00000001U << DDR_PHY_DX8SL0DQSCTL_LPPLLPD_SHIFT - | 0x00000001U << DDR_PHY_DX8SL0DQSCTL_LPIOPD_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_SHIFT - | 0x00000001U << DDR_PHY_DX8SL0DQSCTL_QSCNTEN_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0DQSCTL_UDQIOM_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_SHIFT - | 0x00000003U << DDR_PHY_DX8SL0DQSCTL_DXSR_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0DQSCTL_DQSNRES_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0DQSCTL_DQSRES_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8SL0DQSCTL_OFFSET ,0xFFFFFFFFU ,0x01264300U); - /*############################################################################################################################ */ - - /*Register : DX8SL0DXCTL2 @ 0XFD08142C

- - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24 0x0 - - Configurable Read Data Enable - PSU_DDR_PHY_DX8SL0DXCTL2_CRDEN 0x0 - - OX Extension during Post-amble - PSU_DDR_PHY_DX8SL0DXCTL2_POSOEX 0x0 - - OE Extension during Pre-amble - PSU_DDR_PHY_DX8SL0DXCTL2_PREOEX 0x1 - - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_17 0x0 - - I/O Assisted Gate Select - PSU_DDR_PHY_DX8SL0DXCTL2_IOAG 0x0 + /* + * Register : DX8SL3OSC @ 0XFD0814C0 - I/O Loopback Select - PSU_DDR_PHY_DX8SL0DXCTL2_IOLB 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL3OSC_RESERVED_31_30 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13 0x0 + * Enable Clock Gating for DX ddr_clk + * PSU_DDR_PHY_DX8SL3OSC_GATEDXRDCLK 0x2 - Low Power Wakeup Threshold - PSU_DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH 0xc + * Enable Clock Gating for DX ctl_rd_clk + * PSU_DDR_PHY_DX8SL3OSC_GATEDXDDRCLK 0x2 - Read Data Bus Inversion Enable - PSU_DDR_PHY_DX8SL0DXCTL2_RDBI 0x0 + * Enable Clock Gating for DX ctl_clk + * PSU_DDR_PHY_DX8SL3OSC_GATEDXCTLCLK 0x2 - Write Data Bus Inversion Enable - PSU_DDR_PHY_DX8SL0DXCTL2_WDBI 0x0 + * Selects the level to which clocks will be stalled when clock gating is e + * nabled. + * PSU_DDR_PHY_DX8SL3OSC_CLKLEVEL 0x0 - PUB Read FIFO Bypass - PSU_DDR_PHY_DX8SL0DXCTL2_PRFBYP 0x0 + * Loopback Mode + * PSU_DDR_PHY_DX8SL3OSC_LBMODE 0x0 - DATX8 Receive FIFO Read Mode - PSU_DDR_PHY_DX8SL0DXCTL2_RDMODE 0x0 + * Load GSDQS LCDL with 2x the calibrated GSDQSPRD value + * PSU_DDR_PHY_DX8SL3OSC_LBGSDQS 0x0 - Disables the Read FIFO Reset - PSU_DDR_PHY_DX8SL0DXCTL2_DISRST 0x0 + * Loopback DQS Gating + * PSU_DDR_PHY_DX8SL3OSC_LBGDQS 0x0 - Read DQS Gate I/O Loopback - PSU_DDR_PHY_DX8SL0DXCTL2_DQSGLB 0x0 + * Loopback DQS Shift + * PSU_DDR_PHY_DX8SL3OSC_LBDQSS 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_0 0x0 + * PHY High-Speed Reset + * PSU_DDR_PHY_DX8SL3OSC_PHYHRST 0x1 - DATX8 0-1 DX Control Register 2 - (OFFSET, MASK, VALUE) (0XFD08142C, 0xFFFFFFFFU ,0x00041800U) - RegMask = (DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_MASK | DDR_PHY_DX8SL0DXCTL2_CRDEN_MASK | DDR_PHY_DX8SL0DXCTL2_POSOEX_MASK | DDR_PHY_DX8SL0DXCTL2_PREOEX_MASK | DDR_PHY_DX8SL0DXCTL2_RESERVED_17_MASK | DDR_PHY_DX8SL0DXCTL2_IOAG_MASK | DDR_PHY_DX8SL0DXCTL2_IOLB_MASK | DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_MASK | DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_MASK | DDR_PHY_DX8SL0DXCTL2_RDBI_MASK | DDR_PHY_DX8SL0DXCTL2_WDBI_MASK | DDR_PHY_DX8SL0DXCTL2_PRFBYP_MASK | DDR_PHY_DX8SL0DXCTL2_RDMODE_MASK | DDR_PHY_DX8SL0DXCTL2_DISRST_MASK | DDR_PHY_DX8SL0DXCTL2_DQSGLB_MASK | DDR_PHY_DX8SL0DXCTL2_RESERVED_0_MASK | 0 ); + * PHY FIFO Reset + * PSU_DDR_PHY_DX8SL3OSC_PHYFRST 0x1 - RegVal = ((0x00000000U << DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_CRDEN_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_POSOEX_SHIFT - | 0x00000001U << DDR_PHY_DX8SL0DXCTL2_PREOEX_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_RESERVED_17_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_IOAG_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_IOLB_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_SHIFT - | 0x0000000CU << DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_RDBI_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_WDBI_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_PRFBYP_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_RDMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_DISRST_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_DQSGLB_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_RESERVED_0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8SL0DXCTL2_OFFSET ,0xFFFFFFFFU ,0x00041800U); - /*############################################################################################################################ */ + * Delay Line Test Start + * PSU_DDR_PHY_DX8SL3OSC_DLTST 0x0 - /*Register : DX8SL0IOCR @ 0XFD081430

+ * Delay Line Test Mode + * PSU_DDR_PHY_DX8SL3OSC_DLTMODE 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL0IOCR_RESERVED_31 0x0 + * Reserved. Caution, do not write to this register field. + * PSU_DDR_PHY_DX8SL3OSC_RESERVED_12_11 0x3 - PVREF_DAC REFSEL range select - PSU_DDR_PHY_DX8SL0IOCR_DXDACRANGE 0x7 + * Oscillator Mode Write-Data Delay Line Select + * PSU_DDR_PHY_DX8SL3OSC_OSCWDDL 0x3 - IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring - PSU_DDR_PHY_DX8SL0IOCR_DXVREFIOM 0x0 + * Reserved. Caution, do not write to this register field. + * PSU_DDR_PHY_DX8SL3OSC_RESERVED_8_7 0x3 - DX IO Mode - PSU_DDR_PHY_DX8SL0IOCR_DXIOM 0x2 + * Oscillator Mode Write-Leveling Delay Line Select + * PSU_DDR_PHY_DX8SL3OSC_OSCWDL 0x3 - DX IO Transmitter Mode - PSU_DDR_PHY_DX8SL0IOCR_DXTXM 0x0 + * Oscillator Mode Division + * PSU_DDR_PHY_DX8SL3OSC_OSCDIV 0xf - DX IO Receiver Mode - PSU_DDR_PHY_DX8SL0IOCR_DXRXM 0x0 + * Oscillator Enable + * PSU_DDR_PHY_DX8SL3OSC_OSCEN 0x0 - DATX8 0-1 I/O Configuration Register - (OFFSET, MASK, VALUE) (0XFD081430, 0xFFFFFFFFU ,0x70800000U) - RegMask = (DDR_PHY_DX8SL0IOCR_RESERVED_31_MASK | DDR_PHY_DX8SL0IOCR_DXDACRANGE_MASK | DDR_PHY_DX8SL0IOCR_DXVREFIOM_MASK | DDR_PHY_DX8SL0IOCR_DXIOM_MASK | DDR_PHY_DX8SL0IOCR_DXTXM_MASK | DDR_PHY_DX8SL0IOCR_DXRXM_MASK | 0 ); + * DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Lo + * opback, and Gated Clock Control Register + * (OFFSET, MASK, VALUE) (0XFD0814C0, 0xFFFFFFFFU ,0x2A019FFEU) + */ + PSU_Mask_Write(DDR_PHY_DX8SL3OSC_OFFSET, 0xFFFFFFFFU, 0x2A019FFEU); +/*##################################################################### */ - RegVal = ((0x00000000U << DDR_PHY_DX8SL0IOCR_RESERVED_31_SHIFT - | 0x00000007U << DDR_PHY_DX8SL0IOCR_DXDACRANGE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0IOCR_DXVREFIOM_SHIFT - | 0x00000002U << DDR_PHY_DX8SL0IOCR_DXIOM_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0IOCR_DXTXM_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0IOCR_DXRXM_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8SL0IOCR_OFFSET ,0xFFFFFFFFU ,0x70800000U); - /*############################################################################################################################ */ + /* + * Register : DX8SL3PLLCR0 @ 0XFD0814C4 - /*Register : DX8SL1OSC @ 0XFD081440

+ * PLL Bypass + * PSU_DDR_PHY_DX8SL3PLLCR0_PLLBYP 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL1OSC_RESERVED_31_30 0x0 + * PLL Reset + * PSU_DDR_PHY_DX8SL3PLLCR0_PLLRST 0x0 - Enable Clock Gating for DX ddr_clk - PSU_DDR_PHY_DX8SL1OSC_GATEDXRDCLK 0x2 + * PLL Power Down + * PSU_DDR_PHY_DX8SL3PLLCR0_PLLPD 0x0 - Enable Clock Gating for DX ctl_rd_clk - PSU_DDR_PHY_DX8SL1OSC_GATEDXDDRCLK 0x2 + * Reference Stop Mode + * PSU_DDR_PHY_DX8SL3PLLCR0_RSTOPM 0x0 - Enable Clock Gating for DX ctl_clk - PSU_DDR_PHY_DX8SL1OSC_GATEDXCTLCLK 0x2 + * PLL Frequency Select + * PSU_DDR_PHY_DX8SL3PLLCR0_FRQSEL 0x1 - Selects the level to which clocks will be stalled when clock gating is enabled. - PSU_DDR_PHY_DX8SL1OSC_CLKLEVEL 0x0 + * Relock Mode + * PSU_DDR_PHY_DX8SL3PLLCR0_RLOCKM 0x0 - Loopback Mode - PSU_DDR_PHY_DX8SL1OSC_LBMODE 0x0 + * Charge Pump Proportional Current Control + * PSU_DDR_PHY_DX8SL3PLLCR0_CPPC 0x8 - Load GSDQS LCDL with 2x the calibrated GSDQSPRD value - PSU_DDR_PHY_DX8SL1OSC_LBGSDQS 0x0 + * Charge Pump Integrating Current Control + * PSU_DDR_PHY_DX8SL3PLLCR0_CPIC 0x0 - Loopback DQS Gating - PSU_DDR_PHY_DX8SL1OSC_LBGDQS 0x0 + * Gear Shift + * PSU_DDR_PHY_DX8SL3PLLCR0_GSHIFT 0x0 - Loopback DQS Shift - PSU_DDR_PHY_DX8SL1OSC_LBDQSS 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL3PLLCR0_RESERVED_11_9 0x0 - PHY High-Speed Reset - PSU_DDR_PHY_DX8SL1OSC_PHYHRST 0x1 + * Analog Test Enable (ATOEN) + * PSU_DDR_PHY_DX8SL3PLLCR0_ATOEN 0x0 - PHY FIFO Reset - PSU_DDR_PHY_DX8SL1OSC_PHYFRST 0x1 + * Analog Test Control + * PSU_DDR_PHY_DX8SL3PLLCR0_ATC 0x0 - Delay Line Test Start - PSU_DDR_PHY_DX8SL1OSC_DLTST 0x0 + * Digital Test Control + * PSU_DDR_PHY_DX8SL3PLLCR0_DTC 0x0 - Delay Line Test Mode - PSU_DDR_PHY_DX8SL1OSC_DLTMODE 0x0 + * DAXT8 0-1 PLL Control Register 0 + * (OFFSET, MASK, VALUE) (0XFD0814C4, 0xFFFFFFFFU ,0x01100000U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL3PLLCR0_OFFSET, + 0xFFFFFFFFU, 0x01100000U); +/*##################################################################### */ - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX8SL1OSC_RESERVED_12_11 0x3 - - Oscillator Mode Write-Data Delay Line Select - PSU_DDR_PHY_DX8SL1OSC_OSCWDDL 0x3 - - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX8SL1OSC_RESERVED_8_7 0x3 - - Oscillator Mode Write-Leveling Delay Line Select - PSU_DDR_PHY_DX8SL1OSC_OSCWDL 0x3 - - Oscillator Mode Division - PSU_DDR_PHY_DX8SL1OSC_OSCDIV 0xf + /* + * Register : DX8SL3DQSCTL @ 0XFD0814DC - Oscillator Enable - PSU_DDR_PHY_DX8SL1OSC_OSCEN 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25 0x0 - DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register - (OFFSET, MASK, VALUE) (0XFD081440, 0xFFFFFFFFU ,0x2A019FFEU) - RegMask = (DDR_PHY_DX8SL1OSC_RESERVED_31_30_MASK | DDR_PHY_DX8SL1OSC_GATEDXRDCLK_MASK | DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_MASK | DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_MASK | DDR_PHY_DX8SL1OSC_CLKLEVEL_MASK | DDR_PHY_DX8SL1OSC_LBMODE_MASK | DDR_PHY_DX8SL1OSC_LBGSDQS_MASK | DDR_PHY_DX8SL1OSC_LBGDQS_MASK | DDR_PHY_DX8SL1OSC_LBDQSS_MASK | DDR_PHY_DX8SL1OSC_PHYHRST_MASK | DDR_PHY_DX8SL1OSC_PHYFRST_MASK | DDR_PHY_DX8SL1OSC_DLTST_MASK | DDR_PHY_DX8SL1OSC_DLTMODE_MASK | DDR_PHY_DX8SL1OSC_RESERVED_12_11_MASK | DDR_PHY_DX8SL1OSC_OSCWDDL_MASK | DDR_PHY_DX8SL1OSC_RESERVED_8_7_MASK | DDR_PHY_DX8SL1OSC_OSCWDL_MASK | DDR_PHY_DX8SL1OSC_OSCDIV_MASK | DDR_PHY_DX8SL1OSC_OSCEN_MASK | 0 ); + * Read Path Rise-to-Rise Mode + * PSU_DDR_PHY_DX8SL3DQSCTL_RRRMODE 0x1 - RegVal = ((0x00000000U << DDR_PHY_DX8SL1OSC_RESERVED_31_30_SHIFT - | 0x00000002U << DDR_PHY_DX8SL1OSC_GATEDXRDCLK_SHIFT - | 0x00000002U << DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_SHIFT - | 0x00000002U << DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1OSC_CLKLEVEL_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1OSC_LBMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1OSC_LBGSDQS_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1OSC_LBGDQS_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1OSC_LBDQSS_SHIFT - | 0x00000001U << DDR_PHY_DX8SL1OSC_PHYHRST_SHIFT - | 0x00000001U << DDR_PHY_DX8SL1OSC_PHYFRST_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1OSC_DLTST_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1OSC_DLTMODE_SHIFT - | 0x00000003U << DDR_PHY_DX8SL1OSC_RESERVED_12_11_SHIFT - | 0x00000003U << DDR_PHY_DX8SL1OSC_OSCWDDL_SHIFT - | 0x00000003U << DDR_PHY_DX8SL1OSC_RESERVED_8_7_SHIFT - | 0x00000003U << DDR_PHY_DX8SL1OSC_OSCWDL_SHIFT - | 0x0000000FU << DDR_PHY_DX8SL1OSC_OSCDIV_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1OSC_OSCEN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8SL1OSC_OFFSET ,0xFFFFFFFFU ,0x2A019FFEU); - /*############################################################################################################################ */ + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22 0x0 - /*Register : DX8SL1DQSCTL @ 0XFD08145C

+ * Write Path Rise-to-Rise Mode + * PSU_DDR_PHY_DX8SL3DQSCTL_WRRMODE 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25 0x0 + * DQS Gate Extension + * PSU_DDR_PHY_DX8SL3DQSCTL_DQSGX 0x0 - Read Path Rise-to-Rise Mode - PSU_DDR_PHY_DX8SL1DQSCTL_RRRMODE 0x1 + * Low Power PLL Power Down + * PSU_DDR_PHY_DX8SL3DQSCTL_LPPLLPD 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22 0x0 + * Low Power I/O Power Down + * PSU_DDR_PHY_DX8SL3DQSCTL_LPIOPD 0x1 - Write Path Rise-to-Rise Mode - PSU_DDR_PHY_DX8SL1DQSCTL_WRRMODE 0x1 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15 0x0 - DQS Gate Extension - PSU_DDR_PHY_DX8SL1DQSCTL_DQSGX 0x0 + * QS Counter Enable + * PSU_DDR_PHY_DX8SL3DQSCTL_QSCNTEN 0x1 - Low Power PLL Power Down - PSU_DDR_PHY_DX8SL1DQSCTL_LPPLLPD 0x1 + * Unused DQ I/O Mode + * PSU_DDR_PHY_DX8SL3DQSCTL_UDQIOM 0x0 - Low Power I/O Power Down - PSU_DDR_PHY_DX8SL1DQSCTL_LPIOPD 0x1 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15 0x0 + * Data Slew Rate + * PSU_DDR_PHY_DX8SL3DQSCTL_DXSR 0x3 - QS Counter Enable - PSU_DDR_PHY_DX8SL1DQSCTL_QSCNTEN 0x1 + * DQS_N Resistor + * PSU_DDR_PHY_DX8SL3DQSCTL_DQSNRES 0x0 - Unused DQ I/O Mode - PSU_DDR_PHY_DX8SL1DQSCTL_UDQIOM 0x0 + * DQS Resistor + * PSU_DDR_PHY_DX8SL3DQSCTL_DQSRES 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10 0x0 + * DATX8 0-1 DQS Control Register + * (OFFSET, MASK, VALUE) (0XFD0814DC, 0xFFFFFFFFU ,0x01264300U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL3DQSCTL_OFFSET, + 0xFFFFFFFFU, 0x01264300U); +/*##################################################################### */ - Data Slew Rate - PSU_DDR_PHY_DX8SL1DQSCTL_DXSR 0x3 - - DQS_N Resistor - PSU_DDR_PHY_DX8SL1DQSCTL_DQSNRES 0x0 - - DQS Resistor - PSU_DDR_PHY_DX8SL1DQSCTL_DQSRES 0x0 - - DATX8 0-1 DQS Control Register - (OFFSET, MASK, VALUE) (0XFD08145C, 0xFFFFFFFFU ,0x01264300U) - RegMask = (DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_MASK | DDR_PHY_DX8SL1DQSCTL_RRRMODE_MASK | DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_MASK | DDR_PHY_DX8SL1DQSCTL_WRRMODE_MASK | DDR_PHY_DX8SL1DQSCTL_DQSGX_MASK | DDR_PHY_DX8SL1DQSCTL_LPPLLPD_MASK | DDR_PHY_DX8SL1DQSCTL_LPIOPD_MASK | DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_MASK | DDR_PHY_DX8SL1DQSCTL_QSCNTEN_MASK | DDR_PHY_DX8SL1DQSCTL_UDQIOM_MASK | DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_MASK | DDR_PHY_DX8SL1DQSCTL_DXSR_MASK | DDR_PHY_DX8SL1DQSCTL_DQSNRES_MASK | DDR_PHY_DX8SL1DQSCTL_DQSRES_MASK | 0 ); + /* + * Register : DX8SL3DXCTL2 @ 0XFD0814EC - RegVal = ((0x00000000U << DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_SHIFT - | 0x00000001U << DDR_PHY_DX8SL1DQSCTL_RRRMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_SHIFT - | 0x00000001U << DDR_PHY_DX8SL1DQSCTL_WRRMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1DQSCTL_DQSGX_SHIFT - | 0x00000001U << DDR_PHY_DX8SL1DQSCTL_LPPLLPD_SHIFT - | 0x00000001U << DDR_PHY_DX8SL1DQSCTL_LPIOPD_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_SHIFT - | 0x00000001U << DDR_PHY_DX8SL1DQSCTL_QSCNTEN_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1DQSCTL_UDQIOM_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_SHIFT - | 0x00000003U << DDR_PHY_DX8SL1DQSCTL_DXSR_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1DQSCTL_DQSNRES_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1DQSCTL_DQSRES_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8SL1DQSCTL_OFFSET ,0xFFFFFFFFU ,0x01264300U); - /*############################################################################################################################ */ - - /*Register : DX8SL1DXCTL2 @ 0XFD08146C

- - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24 0x0 - - Configurable Read Data Enable - PSU_DDR_PHY_DX8SL1DXCTL2_CRDEN 0x0 - - OX Extension during Post-amble - PSU_DDR_PHY_DX8SL1DXCTL2_POSOEX 0x0 - - OE Extension during Pre-amble - PSU_DDR_PHY_DX8SL1DXCTL2_PREOEX 0x1 - - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_17 0x0 - - I/O Assisted Gate Select - PSU_DDR_PHY_DX8SL1DXCTL2_IOAG 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24 0x0 - I/O Loopback Select - PSU_DDR_PHY_DX8SL1DXCTL2_IOLB 0x0 + * Configurable Read Data Enable + * PSU_DDR_PHY_DX8SL3DXCTL2_CRDEN 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13 0x0 + * OX Extension during Post-amble + * PSU_DDR_PHY_DX8SL3DXCTL2_POSOEX 0x0 - Low Power Wakeup Threshold - PSU_DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH 0xc + * OE Extension during Pre-amble + * PSU_DDR_PHY_DX8SL3DXCTL2_PREOEX 0x1 - Read Data Bus Inversion Enable - PSU_DDR_PHY_DX8SL1DXCTL2_RDBI 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_17 0x0 - Write Data Bus Inversion Enable - PSU_DDR_PHY_DX8SL1DXCTL2_WDBI 0x0 + * I/O Assisted Gate Select + * PSU_DDR_PHY_DX8SL3DXCTL2_IOAG 0x0 - PUB Read FIFO Bypass - PSU_DDR_PHY_DX8SL1DXCTL2_PRFBYP 0x0 + * I/O Loopback Select + * PSU_DDR_PHY_DX8SL3DXCTL2_IOLB 0x0 - DATX8 Receive FIFO Read Mode - PSU_DDR_PHY_DX8SL1DXCTL2_RDMODE 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13 0x0 - Disables the Read FIFO Reset - PSU_DDR_PHY_DX8SL1DXCTL2_DISRST 0x0 + * Low Power Wakeup Threshold + * PSU_DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH 0xc - Read DQS Gate I/O Loopback - PSU_DDR_PHY_DX8SL1DXCTL2_DQSGLB 0x0 + * Read Data Bus Inversion Enable + * PSU_DDR_PHY_DX8SL3DXCTL2_RDBI 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_0 0x0 + * Write Data Bus Inversion Enable + * PSU_DDR_PHY_DX8SL3DXCTL2_WDBI 0x0 - DATX8 0-1 DX Control Register 2 - (OFFSET, MASK, VALUE) (0XFD08146C, 0xFFFFFFFFU ,0x00041800U) - RegMask = (DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_MASK | DDR_PHY_DX8SL1DXCTL2_CRDEN_MASK | DDR_PHY_DX8SL1DXCTL2_POSOEX_MASK | DDR_PHY_DX8SL1DXCTL2_PREOEX_MASK | DDR_PHY_DX8SL1DXCTL2_RESERVED_17_MASK | DDR_PHY_DX8SL1DXCTL2_IOAG_MASK | DDR_PHY_DX8SL1DXCTL2_IOLB_MASK | DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_MASK | DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_MASK | DDR_PHY_DX8SL1DXCTL2_RDBI_MASK | DDR_PHY_DX8SL1DXCTL2_WDBI_MASK | DDR_PHY_DX8SL1DXCTL2_PRFBYP_MASK | DDR_PHY_DX8SL1DXCTL2_RDMODE_MASK | DDR_PHY_DX8SL1DXCTL2_DISRST_MASK | DDR_PHY_DX8SL1DXCTL2_DQSGLB_MASK | DDR_PHY_DX8SL1DXCTL2_RESERVED_0_MASK | 0 ); + * PUB Read FIFO Bypass + * PSU_DDR_PHY_DX8SL3DXCTL2_PRFBYP 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_CRDEN_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_POSOEX_SHIFT - | 0x00000001U << DDR_PHY_DX8SL1DXCTL2_PREOEX_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_RESERVED_17_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_IOAG_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_IOLB_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_SHIFT - | 0x0000000CU << DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_RDBI_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_WDBI_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_PRFBYP_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_RDMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_DISRST_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_DQSGLB_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_RESERVED_0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8SL1DXCTL2_OFFSET ,0xFFFFFFFFU ,0x00041800U); - /*############################################################################################################################ */ + * DATX8 Receive FIFO Read Mode + * PSU_DDR_PHY_DX8SL3DXCTL2_RDMODE 0x0 - /*Register : DX8SL1IOCR @ 0XFD081470

+ * Disables the Read FIFO Reset + * PSU_DDR_PHY_DX8SL3DXCTL2_DISRST 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL1IOCR_RESERVED_31 0x0 + * Read DQS Gate I/O Loopback + * PSU_DDR_PHY_DX8SL3DXCTL2_DQSGLB 0x0 - PVREF_DAC REFSEL range select - PSU_DDR_PHY_DX8SL1IOCR_DXDACRANGE 0x7 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_0 0x0 - IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring - PSU_DDR_PHY_DX8SL1IOCR_DXVREFIOM 0x0 + * DATX8 0-1 DX Control Register 2 + * (OFFSET, MASK, VALUE) (0XFD0814EC, 0xFFFFFFFFU ,0x00041800U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL3DXCTL2_OFFSET, + 0xFFFFFFFFU, 0x00041800U); +/*##################################################################### */ - DX IO Mode - PSU_DDR_PHY_DX8SL1IOCR_DXIOM 0x2 + /* + * Register : DX8SL3IOCR @ 0XFD0814F0 - DX IO Transmitter Mode - PSU_DDR_PHY_DX8SL1IOCR_DXTXM 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL3IOCR_RESERVED_31 0x0 - DX IO Receiver Mode - PSU_DDR_PHY_DX8SL1IOCR_DXRXM 0x0 + * PVREF_DAC REFSEL range select + * PSU_DDR_PHY_DX8SL3IOCR_DXDACRANGE 0x7 - DATX8 0-1 I/O Configuration Register - (OFFSET, MASK, VALUE) (0XFD081470, 0xFFFFFFFFU ,0x70800000U) - RegMask = (DDR_PHY_DX8SL1IOCR_RESERVED_31_MASK | DDR_PHY_DX8SL1IOCR_DXDACRANGE_MASK | DDR_PHY_DX8SL1IOCR_DXVREFIOM_MASK | DDR_PHY_DX8SL1IOCR_DXIOM_MASK | DDR_PHY_DX8SL1IOCR_DXTXM_MASK | DDR_PHY_DX8SL1IOCR_DXRXM_MASK | 0 ); + * IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring + * PSU_DDR_PHY_DX8SL3IOCR_DXVREFIOM 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX8SL1IOCR_RESERVED_31_SHIFT - | 0x00000007U << DDR_PHY_DX8SL1IOCR_DXDACRANGE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1IOCR_DXVREFIOM_SHIFT - | 0x00000002U << DDR_PHY_DX8SL1IOCR_DXIOM_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1IOCR_DXTXM_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1IOCR_DXRXM_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8SL1IOCR_OFFSET ,0xFFFFFFFFU ,0x70800000U); - /*############################################################################################################################ */ + * DX IO Mode + * PSU_DDR_PHY_DX8SL3IOCR_DXIOM 0x2 - /*Register : DX8SL2OSC @ 0XFD081480

+ * DX IO Transmitter Mode + * PSU_DDR_PHY_DX8SL3IOCR_DXTXM 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL2OSC_RESERVED_31_30 0x0 + * DX IO Receiver Mode + * PSU_DDR_PHY_DX8SL3IOCR_DXRXM 0x0 - Enable Clock Gating for DX ddr_clk - PSU_DDR_PHY_DX8SL2OSC_GATEDXRDCLK 0x2 + * DATX8 0-1 I/O Configuration Register + * (OFFSET, MASK, VALUE) (0XFD0814F0, 0xFFFFFFFFU ,0x70800000U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL3IOCR_OFFSET, 0xFFFFFFFFU, 0x70800000U); +/*##################################################################### */ - Enable Clock Gating for DX ctl_rd_clk - PSU_DDR_PHY_DX8SL2OSC_GATEDXDDRCLK 0x2 + /* + * Register : DX8SL4OSC @ 0XFD081500 - Enable Clock Gating for DX ctl_clk - PSU_DDR_PHY_DX8SL2OSC_GATEDXCTLCLK 0x2 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL4OSC_RESERVED_31_30 0x0 - Selects the level to which clocks will be stalled when clock gating is enabled. - PSU_DDR_PHY_DX8SL2OSC_CLKLEVEL 0x0 + * Enable Clock Gating for DX ddr_clk + * PSU_DDR_PHY_DX8SL4OSC_GATEDXRDCLK 0x2 - Loopback Mode - PSU_DDR_PHY_DX8SL2OSC_LBMODE 0x0 + * Enable Clock Gating for DX ctl_rd_clk + * PSU_DDR_PHY_DX8SL4OSC_GATEDXDDRCLK 0x2 - Load GSDQS LCDL with 2x the calibrated GSDQSPRD value - PSU_DDR_PHY_DX8SL2OSC_LBGSDQS 0x0 + * Enable Clock Gating for DX ctl_clk + * PSU_DDR_PHY_DX8SL4OSC_GATEDXCTLCLK 0x2 - Loopback DQS Gating - PSU_DDR_PHY_DX8SL2OSC_LBGDQS 0x0 + * Selects the level to which clocks will be stalled when clock gating is e + * nabled. + * PSU_DDR_PHY_DX8SL4OSC_CLKLEVEL 0x0 - Loopback DQS Shift - PSU_DDR_PHY_DX8SL2OSC_LBDQSS 0x0 + * Loopback Mode + * PSU_DDR_PHY_DX8SL4OSC_LBMODE 0x0 - PHY High-Speed Reset - PSU_DDR_PHY_DX8SL2OSC_PHYHRST 0x1 + * Load GSDQS LCDL with 2x the calibrated GSDQSPRD value + * PSU_DDR_PHY_DX8SL4OSC_LBGSDQS 0x0 - PHY FIFO Reset - PSU_DDR_PHY_DX8SL2OSC_PHYFRST 0x1 + * Loopback DQS Gating + * PSU_DDR_PHY_DX8SL4OSC_LBGDQS 0x0 - Delay Line Test Start - PSU_DDR_PHY_DX8SL2OSC_DLTST 0x0 + * Loopback DQS Shift + * PSU_DDR_PHY_DX8SL4OSC_LBDQSS 0x0 - Delay Line Test Mode - PSU_DDR_PHY_DX8SL2OSC_DLTMODE 0x0 + * PHY High-Speed Reset + * PSU_DDR_PHY_DX8SL4OSC_PHYHRST 0x1 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX8SL2OSC_RESERVED_12_11 0x3 - - Oscillator Mode Write-Data Delay Line Select - PSU_DDR_PHY_DX8SL2OSC_OSCWDDL 0x3 - - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX8SL2OSC_RESERVED_8_7 0x3 - - Oscillator Mode Write-Leveling Delay Line Select - PSU_DDR_PHY_DX8SL2OSC_OSCWDL 0x3 - - Oscillator Mode Division - PSU_DDR_PHY_DX8SL2OSC_OSCDIV 0xf + * PHY FIFO Reset + * PSU_DDR_PHY_DX8SL4OSC_PHYFRST 0x1 - Oscillator Enable - PSU_DDR_PHY_DX8SL2OSC_OSCEN 0x0 + * Delay Line Test Start + * PSU_DDR_PHY_DX8SL4OSC_DLTST 0x0 - DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register - (OFFSET, MASK, VALUE) (0XFD081480, 0xFFFFFFFFU ,0x2A019FFEU) - RegMask = (DDR_PHY_DX8SL2OSC_RESERVED_31_30_MASK | DDR_PHY_DX8SL2OSC_GATEDXRDCLK_MASK | DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_MASK | DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_MASK | DDR_PHY_DX8SL2OSC_CLKLEVEL_MASK | DDR_PHY_DX8SL2OSC_LBMODE_MASK | DDR_PHY_DX8SL2OSC_LBGSDQS_MASK | DDR_PHY_DX8SL2OSC_LBGDQS_MASK | DDR_PHY_DX8SL2OSC_LBDQSS_MASK | DDR_PHY_DX8SL2OSC_PHYHRST_MASK | DDR_PHY_DX8SL2OSC_PHYFRST_MASK | DDR_PHY_DX8SL2OSC_DLTST_MASK | DDR_PHY_DX8SL2OSC_DLTMODE_MASK | DDR_PHY_DX8SL2OSC_RESERVED_12_11_MASK | DDR_PHY_DX8SL2OSC_OSCWDDL_MASK | DDR_PHY_DX8SL2OSC_RESERVED_8_7_MASK | DDR_PHY_DX8SL2OSC_OSCWDL_MASK | DDR_PHY_DX8SL2OSC_OSCDIV_MASK | DDR_PHY_DX8SL2OSC_OSCEN_MASK | 0 ); + * Delay Line Test Mode + * PSU_DDR_PHY_DX8SL4OSC_DLTMODE 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX8SL2OSC_RESERVED_31_30_SHIFT - | 0x00000002U << DDR_PHY_DX8SL2OSC_GATEDXRDCLK_SHIFT - | 0x00000002U << DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_SHIFT - | 0x00000002U << DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2OSC_CLKLEVEL_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2OSC_LBMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2OSC_LBGSDQS_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2OSC_LBGDQS_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2OSC_LBDQSS_SHIFT - | 0x00000001U << DDR_PHY_DX8SL2OSC_PHYHRST_SHIFT - | 0x00000001U << DDR_PHY_DX8SL2OSC_PHYFRST_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2OSC_DLTST_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2OSC_DLTMODE_SHIFT - | 0x00000003U << DDR_PHY_DX8SL2OSC_RESERVED_12_11_SHIFT - | 0x00000003U << DDR_PHY_DX8SL2OSC_OSCWDDL_SHIFT - | 0x00000003U << DDR_PHY_DX8SL2OSC_RESERVED_8_7_SHIFT - | 0x00000003U << DDR_PHY_DX8SL2OSC_OSCWDL_SHIFT - | 0x0000000FU << DDR_PHY_DX8SL2OSC_OSCDIV_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2OSC_OSCEN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8SL2OSC_OFFSET ,0xFFFFFFFFU ,0x2A019FFEU); - /*############################################################################################################################ */ + * Reserved. Caution, do not write to this register field. + * PSU_DDR_PHY_DX8SL4OSC_RESERVED_12_11 0x3 - /*Register : DX8SL2DQSCTL @ 0XFD08149C

+ * Oscillator Mode Write-Data Delay Line Select + * PSU_DDR_PHY_DX8SL4OSC_OSCWDDL 0x3 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25 0x0 + * Reserved. Caution, do not write to this register field. + * PSU_DDR_PHY_DX8SL4OSC_RESERVED_8_7 0x3 - Read Path Rise-to-Rise Mode - PSU_DDR_PHY_DX8SL2DQSCTL_RRRMODE 0x1 + * Oscillator Mode Write-Leveling Delay Line Select + * PSU_DDR_PHY_DX8SL4OSC_OSCWDL 0x3 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22 0x0 + * Oscillator Mode Division + * PSU_DDR_PHY_DX8SL4OSC_OSCDIV 0xf - Write Path Rise-to-Rise Mode - PSU_DDR_PHY_DX8SL2DQSCTL_WRRMODE 0x1 + * Oscillator Enable + * PSU_DDR_PHY_DX8SL4OSC_OSCEN 0x0 - DQS Gate Extension - PSU_DDR_PHY_DX8SL2DQSCTL_DQSGX 0x0 + * DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Lo + * opback, and Gated Clock Control Register + * (OFFSET, MASK, VALUE) (0XFD081500, 0xFFFFFFFFU ,0x2A019FFEU) + */ + PSU_Mask_Write(DDR_PHY_DX8SL4OSC_OFFSET, 0xFFFFFFFFU, 0x2A019FFEU); +/*##################################################################### */ - Low Power PLL Power Down - PSU_DDR_PHY_DX8SL2DQSCTL_LPPLLPD 0x1 + /* + * Register : DX8SL4PLLCR0 @ 0XFD081504 - Low Power I/O Power Down - PSU_DDR_PHY_DX8SL2DQSCTL_LPIOPD 0x1 + * PLL Bypass + * PSU_DDR_PHY_DX8SL4PLLCR0_PLLBYP 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15 0x0 + * PLL Reset + * PSU_DDR_PHY_DX8SL4PLLCR0_PLLRST 0x0 - QS Counter Enable - PSU_DDR_PHY_DX8SL2DQSCTL_QSCNTEN 0x1 + * PLL Power Down + * PSU_DDR_PHY_DX8SL4PLLCR0_PLLPD 0x0 - Unused DQ I/O Mode - PSU_DDR_PHY_DX8SL2DQSCTL_UDQIOM 0x0 + * Reference Stop Mode + * PSU_DDR_PHY_DX8SL4PLLCR0_RSTOPM 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10 0x0 + * PLL Frequency Select + * PSU_DDR_PHY_DX8SL4PLLCR0_FRQSEL 0x1 - Data Slew Rate - PSU_DDR_PHY_DX8SL2DQSCTL_DXSR 0x3 - - DQS_N Resistor - PSU_DDR_PHY_DX8SL2DQSCTL_DQSNRES 0x0 - - DQS Resistor - PSU_DDR_PHY_DX8SL2DQSCTL_DQSRES 0x0 - - DATX8 0-1 DQS Control Register - (OFFSET, MASK, VALUE) (0XFD08149C, 0xFFFFFFFFU ,0x01264300U) - RegMask = (DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_MASK | DDR_PHY_DX8SL2DQSCTL_RRRMODE_MASK | DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_MASK | DDR_PHY_DX8SL2DQSCTL_WRRMODE_MASK | DDR_PHY_DX8SL2DQSCTL_DQSGX_MASK | DDR_PHY_DX8SL2DQSCTL_LPPLLPD_MASK | DDR_PHY_DX8SL2DQSCTL_LPIOPD_MASK | DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_MASK | DDR_PHY_DX8SL2DQSCTL_QSCNTEN_MASK | DDR_PHY_DX8SL2DQSCTL_UDQIOM_MASK | DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_MASK | DDR_PHY_DX8SL2DQSCTL_DXSR_MASK | DDR_PHY_DX8SL2DQSCTL_DQSNRES_MASK | DDR_PHY_DX8SL2DQSCTL_DQSRES_MASK | 0 ); + * Relock Mode + * PSU_DDR_PHY_DX8SL4PLLCR0_RLOCKM 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_SHIFT - | 0x00000001U << DDR_PHY_DX8SL2DQSCTL_RRRMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_SHIFT - | 0x00000001U << DDR_PHY_DX8SL2DQSCTL_WRRMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2DQSCTL_DQSGX_SHIFT - | 0x00000001U << DDR_PHY_DX8SL2DQSCTL_LPPLLPD_SHIFT - | 0x00000001U << DDR_PHY_DX8SL2DQSCTL_LPIOPD_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_SHIFT - | 0x00000001U << DDR_PHY_DX8SL2DQSCTL_QSCNTEN_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2DQSCTL_UDQIOM_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_SHIFT - | 0x00000003U << DDR_PHY_DX8SL2DQSCTL_DXSR_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2DQSCTL_DQSNRES_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2DQSCTL_DQSRES_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8SL2DQSCTL_OFFSET ,0xFFFFFFFFU ,0x01264300U); - /*############################################################################################################################ */ - - /*Register : DX8SL2DXCTL2 @ 0XFD0814AC

- - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24 0x0 - - Configurable Read Data Enable - PSU_DDR_PHY_DX8SL2DXCTL2_CRDEN 0x0 - - OX Extension during Post-amble - PSU_DDR_PHY_DX8SL2DXCTL2_POSOEX 0x0 - - OE Extension during Pre-amble - PSU_DDR_PHY_DX8SL2DXCTL2_PREOEX 0x1 - - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_17 0x0 - - I/O Assisted Gate Select - PSU_DDR_PHY_DX8SL2DXCTL2_IOAG 0x0 + * Charge Pump Proportional Current Control + * PSU_DDR_PHY_DX8SL4PLLCR0_CPPC 0x8 - I/O Loopback Select - PSU_DDR_PHY_DX8SL2DXCTL2_IOLB 0x0 + * Charge Pump Integrating Current Control + * PSU_DDR_PHY_DX8SL4PLLCR0_CPIC 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13 0x0 + * Gear Shift + * PSU_DDR_PHY_DX8SL4PLLCR0_GSHIFT 0x0 - Low Power Wakeup Threshold - PSU_DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH 0xc + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL4PLLCR0_RESERVED_11_9 0x0 - Read Data Bus Inversion Enable - PSU_DDR_PHY_DX8SL2DXCTL2_RDBI 0x0 + * Analog Test Enable (ATOEN) + * PSU_DDR_PHY_DX8SL4PLLCR0_ATOEN 0x0 - Write Data Bus Inversion Enable - PSU_DDR_PHY_DX8SL2DXCTL2_WDBI 0x0 + * Analog Test Control + * PSU_DDR_PHY_DX8SL4PLLCR0_ATC 0x0 - PUB Read FIFO Bypass - PSU_DDR_PHY_DX8SL2DXCTL2_PRFBYP 0x0 + * Digital Test Control + * PSU_DDR_PHY_DX8SL4PLLCR0_DTC 0x0 - DATX8 Receive FIFO Read Mode - PSU_DDR_PHY_DX8SL2DXCTL2_RDMODE 0x0 + * DAXT8 0-1 PLL Control Register 0 + * (OFFSET, MASK, VALUE) (0XFD081504, 0xFFFFFFFFU ,0x01100000U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL4PLLCR0_OFFSET, + 0xFFFFFFFFU, 0x01100000U); +/*##################################################################### */ - Disables the Read FIFO Reset - PSU_DDR_PHY_DX8SL2DXCTL2_DISRST 0x0 + /* + * Register : DX8SL4DQSCTL @ 0XFD08151C - Read DQS Gate I/O Loopback - PSU_DDR_PHY_DX8SL2DXCTL2_DQSGLB 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_0 0x0 + * Read Path Rise-to-Rise Mode + * PSU_DDR_PHY_DX8SL4DQSCTL_RRRMODE 0x1 - DATX8 0-1 DX Control Register 2 - (OFFSET, MASK, VALUE) (0XFD0814AC, 0xFFFFFFFFU ,0x00041800U) - RegMask = (DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_MASK | DDR_PHY_DX8SL2DXCTL2_CRDEN_MASK | DDR_PHY_DX8SL2DXCTL2_POSOEX_MASK | DDR_PHY_DX8SL2DXCTL2_PREOEX_MASK | DDR_PHY_DX8SL2DXCTL2_RESERVED_17_MASK | DDR_PHY_DX8SL2DXCTL2_IOAG_MASK | DDR_PHY_DX8SL2DXCTL2_IOLB_MASK | DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_MASK | DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_MASK | DDR_PHY_DX8SL2DXCTL2_RDBI_MASK | DDR_PHY_DX8SL2DXCTL2_WDBI_MASK | DDR_PHY_DX8SL2DXCTL2_PRFBYP_MASK | DDR_PHY_DX8SL2DXCTL2_RDMODE_MASK | DDR_PHY_DX8SL2DXCTL2_DISRST_MASK | DDR_PHY_DX8SL2DXCTL2_DQSGLB_MASK | DDR_PHY_DX8SL2DXCTL2_RESERVED_0_MASK | 0 ); + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_CRDEN_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_POSOEX_SHIFT - | 0x00000001U << DDR_PHY_DX8SL2DXCTL2_PREOEX_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_RESERVED_17_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_IOAG_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_IOLB_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_SHIFT - | 0x0000000CU << DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_RDBI_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_WDBI_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_PRFBYP_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_RDMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_DISRST_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_DQSGLB_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_RESERVED_0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8SL2DXCTL2_OFFSET ,0xFFFFFFFFU ,0x00041800U); - /*############################################################################################################################ */ + * Write Path Rise-to-Rise Mode + * PSU_DDR_PHY_DX8SL4DQSCTL_WRRMODE 0x1 - /*Register : DX8SL2IOCR @ 0XFD0814B0

+ * DQS Gate Extension + * PSU_DDR_PHY_DX8SL4DQSCTL_DQSGX 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL2IOCR_RESERVED_31 0x0 + * Low Power PLL Power Down + * PSU_DDR_PHY_DX8SL4DQSCTL_LPPLLPD 0x1 - PVREF_DAC REFSEL range select - PSU_DDR_PHY_DX8SL2IOCR_DXDACRANGE 0x7 + * Low Power I/O Power Down + * PSU_DDR_PHY_DX8SL4DQSCTL_LPIOPD 0x1 - IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring - PSU_DDR_PHY_DX8SL2IOCR_DXVREFIOM 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15 0x0 - DX IO Mode - PSU_DDR_PHY_DX8SL2IOCR_DXIOM 0x2 + * QS Counter Enable + * PSU_DDR_PHY_DX8SL4DQSCTL_QSCNTEN 0x1 - DX IO Transmitter Mode - PSU_DDR_PHY_DX8SL2IOCR_DXTXM 0x0 + * Unused DQ I/O Mode + * PSU_DDR_PHY_DX8SL4DQSCTL_UDQIOM 0x0 - DX IO Receiver Mode - PSU_DDR_PHY_DX8SL2IOCR_DXRXM 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10 0x0 - DATX8 0-1 I/O Configuration Register - (OFFSET, MASK, VALUE) (0XFD0814B0, 0xFFFFFFFFU ,0x70800000U) - RegMask = (DDR_PHY_DX8SL2IOCR_RESERVED_31_MASK | DDR_PHY_DX8SL2IOCR_DXDACRANGE_MASK | DDR_PHY_DX8SL2IOCR_DXVREFIOM_MASK | DDR_PHY_DX8SL2IOCR_DXIOM_MASK | DDR_PHY_DX8SL2IOCR_DXTXM_MASK | DDR_PHY_DX8SL2IOCR_DXRXM_MASK | 0 ); + * Data Slew Rate + * PSU_DDR_PHY_DX8SL4DQSCTL_DXSR 0x3 - RegVal = ((0x00000000U << DDR_PHY_DX8SL2IOCR_RESERVED_31_SHIFT - | 0x00000007U << DDR_PHY_DX8SL2IOCR_DXDACRANGE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2IOCR_DXVREFIOM_SHIFT - | 0x00000002U << DDR_PHY_DX8SL2IOCR_DXIOM_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2IOCR_DXTXM_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2IOCR_DXRXM_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8SL2IOCR_OFFSET ,0xFFFFFFFFU ,0x70800000U); - /*############################################################################################################################ */ + * DQS_N Resistor + * PSU_DDR_PHY_DX8SL4DQSCTL_DQSNRES 0x0 - /*Register : DX8SL3OSC @ 0XFD0814C0

+ * DQS Resistor + * PSU_DDR_PHY_DX8SL4DQSCTL_DQSRES 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL3OSC_RESERVED_31_30 0x0 + * DATX8 0-1 DQS Control Register + * (OFFSET, MASK, VALUE) (0XFD08151C, 0xFFFFFFFFU ,0x01264300U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL4DQSCTL_OFFSET, + 0xFFFFFFFFU, 0x01264300U); +/*##################################################################### */ - Enable Clock Gating for DX ddr_clk - PSU_DDR_PHY_DX8SL3OSC_GATEDXRDCLK 0x2 + /* + * Register : DX8SL4DXCTL2 @ 0XFD08152C - Enable Clock Gating for DX ctl_rd_clk - PSU_DDR_PHY_DX8SL3OSC_GATEDXDDRCLK 0x2 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24 0x0 - Enable Clock Gating for DX ctl_clk - PSU_DDR_PHY_DX8SL3OSC_GATEDXCTLCLK 0x2 + * Configurable Read Data Enable + * PSU_DDR_PHY_DX8SL4DXCTL2_CRDEN 0x0 - Selects the level to which clocks will be stalled when clock gating is enabled. - PSU_DDR_PHY_DX8SL3OSC_CLKLEVEL 0x0 + * OX Extension during Post-amble + * PSU_DDR_PHY_DX8SL4DXCTL2_POSOEX 0x0 - Loopback Mode - PSU_DDR_PHY_DX8SL3OSC_LBMODE 0x0 + * OE Extension during Pre-amble + * PSU_DDR_PHY_DX8SL4DXCTL2_PREOEX 0x1 - Load GSDQS LCDL with 2x the calibrated GSDQSPRD value - PSU_DDR_PHY_DX8SL3OSC_LBGSDQS 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_17 0x0 - Loopback DQS Gating - PSU_DDR_PHY_DX8SL3OSC_LBGDQS 0x0 + * I/O Assisted Gate Select + * PSU_DDR_PHY_DX8SL4DXCTL2_IOAG 0x0 - Loopback DQS Shift - PSU_DDR_PHY_DX8SL3OSC_LBDQSS 0x0 + * I/O Loopback Select + * PSU_DDR_PHY_DX8SL4DXCTL2_IOLB 0x0 - PHY High-Speed Reset - PSU_DDR_PHY_DX8SL3OSC_PHYHRST 0x1 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13 0x0 - PHY FIFO Reset - PSU_DDR_PHY_DX8SL3OSC_PHYFRST 0x1 + * Low Power Wakeup Threshold + * PSU_DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH 0xc - Delay Line Test Start - PSU_DDR_PHY_DX8SL3OSC_DLTST 0x0 + * Read Data Bus Inversion Enable + * PSU_DDR_PHY_DX8SL4DXCTL2_RDBI 0x0 - Delay Line Test Mode - PSU_DDR_PHY_DX8SL3OSC_DLTMODE 0x0 + * Write Data Bus Inversion Enable + * PSU_DDR_PHY_DX8SL4DXCTL2_WDBI 0x0 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX8SL3OSC_RESERVED_12_11 0x3 - - Oscillator Mode Write-Data Delay Line Select - PSU_DDR_PHY_DX8SL3OSC_OSCWDDL 0x3 - - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX8SL3OSC_RESERVED_8_7 0x3 - - Oscillator Mode Write-Leveling Delay Line Select - PSU_DDR_PHY_DX8SL3OSC_OSCWDL 0x3 - - Oscillator Mode Division - PSU_DDR_PHY_DX8SL3OSC_OSCDIV 0xf + * PUB Read FIFO Bypass + * PSU_DDR_PHY_DX8SL4DXCTL2_PRFBYP 0x0 - Oscillator Enable - PSU_DDR_PHY_DX8SL3OSC_OSCEN 0x0 + * DATX8 Receive FIFO Read Mode + * PSU_DDR_PHY_DX8SL4DXCTL2_RDMODE 0x0 - DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register - (OFFSET, MASK, VALUE) (0XFD0814C0, 0xFFFFFFFFU ,0x2A019FFEU) - RegMask = (DDR_PHY_DX8SL3OSC_RESERVED_31_30_MASK | DDR_PHY_DX8SL3OSC_GATEDXRDCLK_MASK | DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_MASK | DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_MASK | DDR_PHY_DX8SL3OSC_CLKLEVEL_MASK | DDR_PHY_DX8SL3OSC_LBMODE_MASK | DDR_PHY_DX8SL3OSC_LBGSDQS_MASK | DDR_PHY_DX8SL3OSC_LBGDQS_MASK | DDR_PHY_DX8SL3OSC_LBDQSS_MASK | DDR_PHY_DX8SL3OSC_PHYHRST_MASK | DDR_PHY_DX8SL3OSC_PHYFRST_MASK | DDR_PHY_DX8SL3OSC_DLTST_MASK | DDR_PHY_DX8SL3OSC_DLTMODE_MASK | DDR_PHY_DX8SL3OSC_RESERVED_12_11_MASK | DDR_PHY_DX8SL3OSC_OSCWDDL_MASK | DDR_PHY_DX8SL3OSC_RESERVED_8_7_MASK | DDR_PHY_DX8SL3OSC_OSCWDL_MASK | DDR_PHY_DX8SL3OSC_OSCDIV_MASK | DDR_PHY_DX8SL3OSC_OSCEN_MASK | 0 ); + * Disables the Read FIFO Reset + * PSU_DDR_PHY_DX8SL4DXCTL2_DISRST 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX8SL3OSC_RESERVED_31_30_SHIFT - | 0x00000002U << DDR_PHY_DX8SL3OSC_GATEDXRDCLK_SHIFT - | 0x00000002U << DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_SHIFT - | 0x00000002U << DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3OSC_CLKLEVEL_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3OSC_LBMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3OSC_LBGSDQS_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3OSC_LBGDQS_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3OSC_LBDQSS_SHIFT - | 0x00000001U << DDR_PHY_DX8SL3OSC_PHYHRST_SHIFT - | 0x00000001U << DDR_PHY_DX8SL3OSC_PHYFRST_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3OSC_DLTST_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3OSC_DLTMODE_SHIFT - | 0x00000003U << DDR_PHY_DX8SL3OSC_RESERVED_12_11_SHIFT - | 0x00000003U << DDR_PHY_DX8SL3OSC_OSCWDDL_SHIFT - | 0x00000003U << DDR_PHY_DX8SL3OSC_RESERVED_8_7_SHIFT - | 0x00000003U << DDR_PHY_DX8SL3OSC_OSCWDL_SHIFT - | 0x0000000FU << DDR_PHY_DX8SL3OSC_OSCDIV_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3OSC_OSCEN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8SL3OSC_OFFSET ,0xFFFFFFFFU ,0x2A019FFEU); - /*############################################################################################################################ */ + * Read DQS Gate I/O Loopback + * PSU_DDR_PHY_DX8SL4DXCTL2_DQSGLB 0x0 - /*Register : DX8SL3DQSCTL @ 0XFD0814DC

+ * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_0 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25 0x0 + * DATX8 0-1 DX Control Register 2 + * (OFFSET, MASK, VALUE) (0XFD08152C, 0xFFFFFFFFU ,0x00041800U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL4DXCTL2_OFFSET, + 0xFFFFFFFFU, 0x00041800U); +/*##################################################################### */ - Read Path Rise-to-Rise Mode - PSU_DDR_PHY_DX8SL3DQSCTL_RRRMODE 0x1 + /* + * Register : DX8SL4IOCR @ 0XFD081530 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL4IOCR_RESERVED_31 0x0 - Write Path Rise-to-Rise Mode - PSU_DDR_PHY_DX8SL3DQSCTL_WRRMODE 0x1 + * PVREF_DAC REFSEL range select + * PSU_DDR_PHY_DX8SL4IOCR_DXDACRANGE 0x7 - DQS Gate Extension - PSU_DDR_PHY_DX8SL3DQSCTL_DQSGX 0x0 + * IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring + * PSU_DDR_PHY_DX8SL4IOCR_DXVREFIOM 0x0 - Low Power PLL Power Down - PSU_DDR_PHY_DX8SL3DQSCTL_LPPLLPD 0x1 + * DX IO Mode + * PSU_DDR_PHY_DX8SL4IOCR_DXIOM 0x2 - Low Power I/O Power Down - PSU_DDR_PHY_DX8SL3DQSCTL_LPIOPD 0x1 + * DX IO Transmitter Mode + * PSU_DDR_PHY_DX8SL4IOCR_DXTXM 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15 0x0 + * DX IO Receiver Mode + * PSU_DDR_PHY_DX8SL4IOCR_DXRXM 0x0 - QS Counter Enable - PSU_DDR_PHY_DX8SL3DQSCTL_QSCNTEN 0x1 + * DATX8 0-1 I/O Configuration Register + * (OFFSET, MASK, VALUE) (0XFD081530, 0xFFFFFFFFU ,0x70800000U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL4IOCR_OFFSET, 0xFFFFFFFFU, 0x70800000U); +/*##################################################################### */ - Unused DQ I/O Mode - PSU_DDR_PHY_DX8SL3DQSCTL_UDQIOM 0x0 + /* + * Register : DX8SLbPLLCR0 @ 0XFD0817C4 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10 0x0 + * PLL Bypass + * PSU_DDR_PHY_DX8SLBPLLCR0_PLLBYP 0x0 - Data Slew Rate - PSU_DDR_PHY_DX8SL3DQSCTL_DXSR 0x3 - - DQS_N Resistor - PSU_DDR_PHY_DX8SL3DQSCTL_DQSNRES 0x0 - - DQS Resistor - PSU_DDR_PHY_DX8SL3DQSCTL_DQSRES 0x0 - - DATX8 0-1 DQS Control Register - (OFFSET, MASK, VALUE) (0XFD0814DC, 0xFFFFFFFFU ,0x01264300U) - RegMask = (DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_MASK | DDR_PHY_DX8SL3DQSCTL_RRRMODE_MASK | DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_MASK | DDR_PHY_DX8SL3DQSCTL_WRRMODE_MASK | DDR_PHY_DX8SL3DQSCTL_DQSGX_MASK | DDR_PHY_DX8SL3DQSCTL_LPPLLPD_MASK | DDR_PHY_DX8SL3DQSCTL_LPIOPD_MASK | DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_MASK | DDR_PHY_DX8SL3DQSCTL_QSCNTEN_MASK | DDR_PHY_DX8SL3DQSCTL_UDQIOM_MASK | DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_MASK | DDR_PHY_DX8SL3DQSCTL_DXSR_MASK | DDR_PHY_DX8SL3DQSCTL_DQSNRES_MASK | DDR_PHY_DX8SL3DQSCTL_DQSRES_MASK | 0 ); + * PLL Reset + * PSU_DDR_PHY_DX8SLBPLLCR0_PLLRST 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_SHIFT - | 0x00000001U << DDR_PHY_DX8SL3DQSCTL_RRRMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_SHIFT - | 0x00000001U << DDR_PHY_DX8SL3DQSCTL_WRRMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3DQSCTL_DQSGX_SHIFT - | 0x00000001U << DDR_PHY_DX8SL3DQSCTL_LPPLLPD_SHIFT - | 0x00000001U << DDR_PHY_DX8SL3DQSCTL_LPIOPD_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_SHIFT - | 0x00000001U << DDR_PHY_DX8SL3DQSCTL_QSCNTEN_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3DQSCTL_UDQIOM_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_SHIFT - | 0x00000003U << DDR_PHY_DX8SL3DQSCTL_DXSR_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3DQSCTL_DQSNRES_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3DQSCTL_DQSRES_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8SL3DQSCTL_OFFSET ,0xFFFFFFFFU ,0x01264300U); - /*############################################################################################################################ */ - - /*Register : DX8SL3DXCTL2 @ 0XFD0814EC

- - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24 0x0 - - Configurable Read Data Enable - PSU_DDR_PHY_DX8SL3DXCTL2_CRDEN 0x0 - - OX Extension during Post-amble - PSU_DDR_PHY_DX8SL3DXCTL2_POSOEX 0x0 - - OE Extension during Pre-amble - PSU_DDR_PHY_DX8SL3DXCTL2_PREOEX 0x1 - - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_17 0x0 - - I/O Assisted Gate Select - PSU_DDR_PHY_DX8SL3DXCTL2_IOAG 0x0 + * PLL Power Down + * PSU_DDR_PHY_DX8SLBPLLCR0_PLLPD 0x0 - I/O Loopback Select - PSU_DDR_PHY_DX8SL3DXCTL2_IOLB 0x0 + * Reference Stop Mode + * PSU_DDR_PHY_DX8SLBPLLCR0_RSTOPM 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13 0x0 + * PLL Frequency Select + * PSU_DDR_PHY_DX8SLBPLLCR0_FRQSEL 0x1 - Low Power Wakeup Threshold - PSU_DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH 0xc + * Relock Mode + * PSU_DDR_PHY_DX8SLBPLLCR0_RLOCKM 0x0 - Read Data Bus Inversion Enable - PSU_DDR_PHY_DX8SL3DXCTL2_RDBI 0x0 + * Charge Pump Proportional Current Control + * PSU_DDR_PHY_DX8SLBPLLCR0_CPPC 0x8 - Write Data Bus Inversion Enable - PSU_DDR_PHY_DX8SL3DXCTL2_WDBI 0x0 + * Charge Pump Integrating Current Control + * PSU_DDR_PHY_DX8SLBPLLCR0_CPIC 0x0 - PUB Read FIFO Bypass - PSU_DDR_PHY_DX8SL3DXCTL2_PRFBYP 0x0 + * Gear Shift + * PSU_DDR_PHY_DX8SLBPLLCR0_GSHIFT 0x0 - DATX8 Receive FIFO Read Mode - PSU_DDR_PHY_DX8SL3DXCTL2_RDMODE 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SLBPLLCR0_RESERVED_11_9 0x0 - Disables the Read FIFO Reset - PSU_DDR_PHY_DX8SL3DXCTL2_DISRST 0x0 + * Analog Test Enable (ATOEN) + * PSU_DDR_PHY_DX8SLBPLLCR0_ATOEN 0x0 - Read DQS Gate I/O Loopback - PSU_DDR_PHY_DX8SL3DXCTL2_DQSGLB 0x0 + * Analog Test Control + * PSU_DDR_PHY_DX8SLBPLLCR0_ATC 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_0 0x0 + * Digital Test Control + * PSU_DDR_PHY_DX8SLBPLLCR0_DTC 0x0 - DATX8 0-1 DX Control Register 2 - (OFFSET, MASK, VALUE) (0XFD0814EC, 0xFFFFFFFFU ,0x00041800U) - RegMask = (DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_MASK | DDR_PHY_DX8SL3DXCTL2_CRDEN_MASK | DDR_PHY_DX8SL3DXCTL2_POSOEX_MASK | DDR_PHY_DX8SL3DXCTL2_PREOEX_MASK | DDR_PHY_DX8SL3DXCTL2_RESERVED_17_MASK | DDR_PHY_DX8SL3DXCTL2_IOAG_MASK | DDR_PHY_DX8SL3DXCTL2_IOLB_MASK | DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_MASK | DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_MASK | DDR_PHY_DX8SL3DXCTL2_RDBI_MASK | DDR_PHY_DX8SL3DXCTL2_WDBI_MASK | DDR_PHY_DX8SL3DXCTL2_PRFBYP_MASK | DDR_PHY_DX8SL3DXCTL2_RDMODE_MASK | DDR_PHY_DX8SL3DXCTL2_DISRST_MASK | DDR_PHY_DX8SL3DXCTL2_DQSGLB_MASK | DDR_PHY_DX8SL3DXCTL2_RESERVED_0_MASK | 0 ); + * DAXT8 0-8 PLL Control Register 0 + * (OFFSET, MASK, VALUE) (0XFD0817C4, 0xFFFFFFFFU ,0x01100000U) + */ + PSU_Mask_Write(DDR_PHY_DX8SLBPLLCR0_OFFSET, + 0xFFFFFFFFU, 0x01100000U); +/*##################################################################### */ - RegVal = ((0x00000000U << DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_CRDEN_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_POSOEX_SHIFT - | 0x00000001U << DDR_PHY_DX8SL3DXCTL2_PREOEX_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_RESERVED_17_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_IOAG_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_IOLB_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_SHIFT - | 0x0000000CU << DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_RDBI_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_WDBI_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_PRFBYP_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_RDMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_DISRST_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_DQSGLB_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_RESERVED_0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8SL3DXCTL2_OFFSET ,0xFFFFFFFFU ,0x00041800U); - /*############################################################################################################################ */ + /* + * Register : DX8SLbDQSCTL @ 0XFD0817DC - /*Register : DX8SL3IOCR @ 0XFD0814F0

+ * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL3IOCR_RESERVED_31 0x0 + * Read Path Rise-to-Rise Mode + * PSU_DDR_PHY_DX8SLBDQSCTL_RRRMODE 0x1 - PVREF_DAC REFSEL range select - PSU_DDR_PHY_DX8SL3IOCR_DXDACRANGE 0x7 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22 0x0 - IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring - PSU_DDR_PHY_DX8SL3IOCR_DXVREFIOM 0x0 + * Write Path Rise-to-Rise Mode + * PSU_DDR_PHY_DX8SLBDQSCTL_WRRMODE 0x1 - DX IO Mode - PSU_DDR_PHY_DX8SL3IOCR_DXIOM 0x2 + * DQS Gate Extension + * PSU_DDR_PHY_DX8SLBDQSCTL_DQSGX 0x0 - DX IO Transmitter Mode - PSU_DDR_PHY_DX8SL3IOCR_DXTXM 0x0 + * Low Power PLL Power Down + * PSU_DDR_PHY_DX8SLBDQSCTL_LPPLLPD 0x1 - DX IO Receiver Mode - PSU_DDR_PHY_DX8SL3IOCR_DXRXM 0x0 + * Low Power I/O Power Down + * PSU_DDR_PHY_DX8SLBDQSCTL_LPIOPD 0x1 - DATX8 0-1 I/O Configuration Register - (OFFSET, MASK, VALUE) (0XFD0814F0, 0xFFFFFFFFU ,0x70800000U) - RegMask = (DDR_PHY_DX8SL3IOCR_RESERVED_31_MASK | DDR_PHY_DX8SL3IOCR_DXDACRANGE_MASK | DDR_PHY_DX8SL3IOCR_DXVREFIOM_MASK | DDR_PHY_DX8SL3IOCR_DXIOM_MASK | DDR_PHY_DX8SL3IOCR_DXTXM_MASK | DDR_PHY_DX8SL3IOCR_DXRXM_MASK | 0 ); + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX8SL3IOCR_RESERVED_31_SHIFT - | 0x00000007U << DDR_PHY_DX8SL3IOCR_DXDACRANGE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3IOCR_DXVREFIOM_SHIFT - | 0x00000002U << DDR_PHY_DX8SL3IOCR_DXIOM_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3IOCR_DXTXM_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3IOCR_DXRXM_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8SL3IOCR_OFFSET ,0xFFFFFFFFU ,0x70800000U); - /*############################################################################################################################ */ + * QS Counter Enable + * PSU_DDR_PHY_DX8SLBDQSCTL_QSCNTEN 0x1 - /*Register : DX8SL4OSC @ 0XFD081500

+ * Unused DQ I/O Mode + * PSU_DDR_PHY_DX8SLBDQSCTL_UDQIOM 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL4OSC_RESERVED_31_30 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10 0x0 - Enable Clock Gating for DX ddr_clk - PSU_DDR_PHY_DX8SL4OSC_GATEDXRDCLK 0x2 + * Data Slew Rate + * PSU_DDR_PHY_DX8SLBDQSCTL_DXSR 0x3 - Enable Clock Gating for DX ctl_rd_clk - PSU_DDR_PHY_DX8SL4OSC_GATEDXDDRCLK 0x2 + * DQS# Resistor + * PSU_DDR_PHY_DX8SLBDQSCTL_DQSNRES 0xc - Enable Clock Gating for DX ctl_clk - PSU_DDR_PHY_DX8SL4OSC_GATEDXCTLCLK 0x2 + * DQS Resistor + * PSU_DDR_PHY_DX8SLBDQSCTL_DQSRES 0x4 - Selects the level to which clocks will be stalled when clock gating is enabled. - PSU_DDR_PHY_DX8SL4OSC_CLKLEVEL 0x0 + * DATX8 0-8 DQS Control Register + * (OFFSET, MASK, VALUE) (0XFD0817DC, 0xFFFFFFFFU ,0x012643C4U) + */ + PSU_Mask_Write(DDR_PHY_DX8SLBDQSCTL_OFFSET, + 0xFFFFFFFFU, 0x012643C4U); +/*##################################################################### */ - Loopback Mode - PSU_DDR_PHY_DX8SL4OSC_LBMODE 0x0 - Load GSDQS LCDL with 2x the calibrated GSDQSPRD value - PSU_DDR_PHY_DX8SL4OSC_LBGSDQS 0x0 - - Loopback DQS Gating - PSU_DDR_PHY_DX8SL4OSC_LBGDQS 0x0 - - Loopback DQS Shift - PSU_DDR_PHY_DX8SL4OSC_LBDQSS 0x0 - - PHY High-Speed Reset - PSU_DDR_PHY_DX8SL4OSC_PHYHRST 0x1 - - PHY FIFO Reset - PSU_DDR_PHY_DX8SL4OSC_PHYFRST 0x1 - - Delay Line Test Start - PSU_DDR_PHY_DX8SL4OSC_DLTST 0x0 - - Delay Line Test Mode - PSU_DDR_PHY_DX8SL4OSC_DLTMODE 0x0 - - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX8SL4OSC_RESERVED_12_11 0x3 - - Oscillator Mode Write-Data Delay Line Select - PSU_DDR_PHY_DX8SL4OSC_OSCWDDL 0x3 - - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX8SL4OSC_RESERVED_8_7 0x3 - - Oscillator Mode Write-Leveling Delay Line Select - PSU_DDR_PHY_DX8SL4OSC_OSCWDL 0x3 - - Oscillator Mode Division - PSU_DDR_PHY_DX8SL4OSC_OSCDIV 0xf - - Oscillator Enable - PSU_DDR_PHY_DX8SL4OSC_OSCEN 0x0 - - DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register - (OFFSET, MASK, VALUE) (0XFD081500, 0xFFFFFFFFU ,0x2A019FFEU) - RegMask = (DDR_PHY_DX8SL4OSC_RESERVED_31_30_MASK | DDR_PHY_DX8SL4OSC_GATEDXRDCLK_MASK | DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_MASK | DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_MASK | DDR_PHY_DX8SL4OSC_CLKLEVEL_MASK | DDR_PHY_DX8SL4OSC_LBMODE_MASK | DDR_PHY_DX8SL4OSC_LBGSDQS_MASK | DDR_PHY_DX8SL4OSC_LBGDQS_MASK | DDR_PHY_DX8SL4OSC_LBDQSS_MASK | DDR_PHY_DX8SL4OSC_PHYHRST_MASK | DDR_PHY_DX8SL4OSC_PHYFRST_MASK | DDR_PHY_DX8SL4OSC_DLTST_MASK | DDR_PHY_DX8SL4OSC_DLTMODE_MASK | DDR_PHY_DX8SL4OSC_RESERVED_12_11_MASK | DDR_PHY_DX8SL4OSC_OSCWDDL_MASK | DDR_PHY_DX8SL4OSC_RESERVED_8_7_MASK | DDR_PHY_DX8SL4OSC_OSCWDL_MASK | DDR_PHY_DX8SL4OSC_OSCDIV_MASK | DDR_PHY_DX8SL4OSC_OSCEN_MASK | 0 ); - - RegVal = ((0x00000000U << DDR_PHY_DX8SL4OSC_RESERVED_31_30_SHIFT - | 0x00000002U << DDR_PHY_DX8SL4OSC_GATEDXRDCLK_SHIFT - | 0x00000002U << DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_SHIFT - | 0x00000002U << DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4OSC_CLKLEVEL_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4OSC_LBMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4OSC_LBGSDQS_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4OSC_LBGDQS_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4OSC_LBDQSS_SHIFT - | 0x00000001U << DDR_PHY_DX8SL4OSC_PHYHRST_SHIFT - | 0x00000001U << DDR_PHY_DX8SL4OSC_PHYFRST_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4OSC_DLTST_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4OSC_DLTMODE_SHIFT - | 0x00000003U << DDR_PHY_DX8SL4OSC_RESERVED_12_11_SHIFT - | 0x00000003U << DDR_PHY_DX8SL4OSC_OSCWDDL_SHIFT - | 0x00000003U << DDR_PHY_DX8SL4OSC_RESERVED_8_7_SHIFT - | 0x00000003U << DDR_PHY_DX8SL4OSC_OSCWDL_SHIFT - | 0x0000000FU << DDR_PHY_DX8SL4OSC_OSCDIV_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4OSC_OSCEN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8SL4OSC_OFFSET ,0xFFFFFFFFU ,0x2A019FFEU); - /*############################################################################################################################ */ - - /*Register : DX8SL4DQSCTL @ 0XFD08151C

- - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25 0x0 - - Read Path Rise-to-Rise Mode - PSU_DDR_PHY_DX8SL4DQSCTL_RRRMODE 0x1 - - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22 0x0 - - Write Path Rise-to-Rise Mode - PSU_DDR_PHY_DX8SL4DQSCTL_WRRMODE 0x1 - - DQS Gate Extension - PSU_DDR_PHY_DX8SL4DQSCTL_DQSGX 0x0 - - Low Power PLL Power Down - PSU_DDR_PHY_DX8SL4DQSCTL_LPPLLPD 0x1 - - Low Power I/O Power Down - PSU_DDR_PHY_DX8SL4DQSCTL_LPIOPD 0x1 - - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15 0x0 - - QS Counter Enable - PSU_DDR_PHY_DX8SL4DQSCTL_QSCNTEN 0x1 - - Unused DQ I/O Mode - PSU_DDR_PHY_DX8SL4DQSCTL_UDQIOM 0x0 - - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10 0x0 - - Data Slew Rate - PSU_DDR_PHY_DX8SL4DQSCTL_DXSR 0x3 - - DQS_N Resistor - PSU_DDR_PHY_DX8SL4DQSCTL_DQSNRES 0x0 - - DQS Resistor - PSU_DDR_PHY_DX8SL4DQSCTL_DQSRES 0x0 - - DATX8 0-1 DQS Control Register - (OFFSET, MASK, VALUE) (0XFD08151C, 0xFFFFFFFFU ,0x01264300U) - RegMask = (DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_MASK | DDR_PHY_DX8SL4DQSCTL_RRRMODE_MASK | DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_MASK | DDR_PHY_DX8SL4DQSCTL_WRRMODE_MASK | DDR_PHY_DX8SL4DQSCTL_DQSGX_MASK | DDR_PHY_DX8SL4DQSCTL_LPPLLPD_MASK | DDR_PHY_DX8SL4DQSCTL_LPIOPD_MASK | DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_MASK | DDR_PHY_DX8SL4DQSCTL_QSCNTEN_MASK | DDR_PHY_DX8SL4DQSCTL_UDQIOM_MASK | DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_MASK | DDR_PHY_DX8SL4DQSCTL_DXSR_MASK | DDR_PHY_DX8SL4DQSCTL_DQSNRES_MASK | DDR_PHY_DX8SL4DQSCTL_DQSRES_MASK | 0 ); - - RegVal = ((0x00000000U << DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_SHIFT - | 0x00000001U << DDR_PHY_DX8SL4DQSCTL_RRRMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_SHIFT - | 0x00000001U << DDR_PHY_DX8SL4DQSCTL_WRRMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4DQSCTL_DQSGX_SHIFT - | 0x00000001U << DDR_PHY_DX8SL4DQSCTL_LPPLLPD_SHIFT - | 0x00000001U << DDR_PHY_DX8SL4DQSCTL_LPIOPD_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_SHIFT - | 0x00000001U << DDR_PHY_DX8SL4DQSCTL_QSCNTEN_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4DQSCTL_UDQIOM_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_SHIFT - | 0x00000003U << DDR_PHY_DX8SL4DQSCTL_DXSR_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4DQSCTL_DQSNRES_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4DQSCTL_DQSRES_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8SL4DQSCTL_OFFSET ,0xFFFFFFFFU ,0x01264300U); - /*############################################################################################################################ */ - - /*Register : DX8SL4DXCTL2 @ 0XFD08152C

- - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24 0x0 - - Configurable Read Data Enable - PSU_DDR_PHY_DX8SL4DXCTL2_CRDEN 0x0 - - OX Extension during Post-amble - PSU_DDR_PHY_DX8SL4DXCTL2_POSOEX 0x0 - - OE Extension during Pre-amble - PSU_DDR_PHY_DX8SL4DXCTL2_PREOEX 0x1 - - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_17 0x0 - - I/O Assisted Gate Select - PSU_DDR_PHY_DX8SL4DXCTL2_IOAG 0x0 - - I/O Loopback Select - PSU_DDR_PHY_DX8SL4DXCTL2_IOLB 0x0 - - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13 0x0 - - Low Power Wakeup Threshold - PSU_DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH 0xc - - Read Data Bus Inversion Enable - PSU_DDR_PHY_DX8SL4DXCTL2_RDBI 0x0 - - Write Data Bus Inversion Enable - PSU_DDR_PHY_DX8SL4DXCTL2_WDBI 0x0 - - PUB Read FIFO Bypass - PSU_DDR_PHY_DX8SL4DXCTL2_PRFBYP 0x0 - - DATX8 Receive FIFO Read Mode - PSU_DDR_PHY_DX8SL4DXCTL2_RDMODE 0x0 - - Disables the Read FIFO Reset - PSU_DDR_PHY_DX8SL4DXCTL2_DISRST 0x0 - - Read DQS Gate I/O Loopback - PSU_DDR_PHY_DX8SL4DXCTL2_DQSGLB 0x0 - - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_0 0x0 - - DATX8 0-1 DX Control Register 2 - (OFFSET, MASK, VALUE) (0XFD08152C, 0xFFFFFFFFU ,0x00041800U) - RegMask = (DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_MASK | DDR_PHY_DX8SL4DXCTL2_CRDEN_MASK | DDR_PHY_DX8SL4DXCTL2_POSOEX_MASK | DDR_PHY_DX8SL4DXCTL2_PREOEX_MASK | DDR_PHY_DX8SL4DXCTL2_RESERVED_17_MASK | DDR_PHY_DX8SL4DXCTL2_IOAG_MASK | DDR_PHY_DX8SL4DXCTL2_IOLB_MASK | DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_MASK | DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_MASK | DDR_PHY_DX8SL4DXCTL2_RDBI_MASK | DDR_PHY_DX8SL4DXCTL2_WDBI_MASK | DDR_PHY_DX8SL4DXCTL2_PRFBYP_MASK | DDR_PHY_DX8SL4DXCTL2_RDMODE_MASK | DDR_PHY_DX8SL4DXCTL2_DISRST_MASK | DDR_PHY_DX8SL4DXCTL2_DQSGLB_MASK | DDR_PHY_DX8SL4DXCTL2_RESERVED_0_MASK | 0 ); - - RegVal = ((0x00000000U << DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_CRDEN_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_POSOEX_SHIFT - | 0x00000001U << DDR_PHY_DX8SL4DXCTL2_PREOEX_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_RESERVED_17_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_IOAG_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_IOLB_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_SHIFT - | 0x0000000CU << DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_RDBI_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_WDBI_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_PRFBYP_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_RDMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_DISRST_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_DQSGLB_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_RESERVED_0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8SL4DXCTL2_OFFSET ,0xFFFFFFFFU ,0x00041800U); - /*############################################################################################################################ */ - - /*Register : DX8SL4IOCR @ 0XFD081530

- - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL4IOCR_RESERVED_31 0x0 - - PVREF_DAC REFSEL range select - PSU_DDR_PHY_DX8SL4IOCR_DXDACRANGE 0x7 - - IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring - PSU_DDR_PHY_DX8SL4IOCR_DXVREFIOM 0x0 - - DX IO Mode - PSU_DDR_PHY_DX8SL4IOCR_DXIOM 0x2 - - DX IO Transmitter Mode - PSU_DDR_PHY_DX8SL4IOCR_DXTXM 0x0 - - DX IO Receiver Mode - PSU_DDR_PHY_DX8SL4IOCR_DXRXM 0x0 - - DATX8 0-1 I/O Configuration Register - (OFFSET, MASK, VALUE) (0XFD081530, 0xFFFFFFFFU ,0x70800000U) - RegMask = (DDR_PHY_DX8SL4IOCR_RESERVED_31_MASK | DDR_PHY_DX8SL4IOCR_DXDACRANGE_MASK | DDR_PHY_DX8SL4IOCR_DXVREFIOM_MASK | DDR_PHY_DX8SL4IOCR_DXIOM_MASK | DDR_PHY_DX8SL4IOCR_DXTXM_MASK | DDR_PHY_DX8SL4IOCR_DXRXM_MASK | 0 ); - - RegVal = ((0x00000000U << DDR_PHY_DX8SL4IOCR_RESERVED_31_SHIFT - | 0x00000007U << DDR_PHY_DX8SL4IOCR_DXDACRANGE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4IOCR_DXVREFIOM_SHIFT - | 0x00000002U << DDR_PHY_DX8SL4IOCR_DXIOM_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4IOCR_DXTXM_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4IOCR_DXRXM_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8SL4IOCR_OFFSET ,0xFFFFFFFFU ,0x70800000U); - /*############################################################################################################################ */ - - /*Register : DX8SLbDQSCTL @ 0XFD0817DC

- - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25 0x0 - - Read Path Rise-to-Rise Mode - PSU_DDR_PHY_DX8SLBDQSCTL_RRRMODE 0x1 - - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22 0x0 - - Write Path Rise-to-Rise Mode - PSU_DDR_PHY_DX8SLBDQSCTL_WRRMODE 0x1 - - DQS Gate Extension - PSU_DDR_PHY_DX8SLBDQSCTL_DQSGX 0x0 - - Low Power PLL Power Down - PSU_DDR_PHY_DX8SLBDQSCTL_LPPLLPD 0x1 - - Low Power I/O Power Down - PSU_DDR_PHY_DX8SLBDQSCTL_LPIOPD 0x1 - - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15 0x0 - - QS Counter Enable - PSU_DDR_PHY_DX8SLBDQSCTL_QSCNTEN 0x1 - - Unused DQ I/O Mode - PSU_DDR_PHY_DX8SLBDQSCTL_UDQIOM 0x0 - - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10 0x0 - - Data Slew Rate - PSU_DDR_PHY_DX8SLBDQSCTL_DXSR 0x3 - - DQS# Resistor - PSU_DDR_PHY_DX8SLBDQSCTL_DQSNRES 0xc - - DQS Resistor - PSU_DDR_PHY_DX8SLBDQSCTL_DQSRES 0x4 - - DATX8 0-8 DQS Control Register - (OFFSET, MASK, VALUE) (0XFD0817DC, 0xFFFFFFFFU ,0x012643C4U) - RegMask = (DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_MASK | DDR_PHY_DX8SLBDQSCTL_RRRMODE_MASK | DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_MASK | DDR_PHY_DX8SLBDQSCTL_WRRMODE_MASK | DDR_PHY_DX8SLBDQSCTL_DQSGX_MASK | DDR_PHY_DX8SLBDQSCTL_LPPLLPD_MASK | DDR_PHY_DX8SLBDQSCTL_LPIOPD_MASK | DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_MASK | DDR_PHY_DX8SLBDQSCTL_QSCNTEN_MASK | DDR_PHY_DX8SLBDQSCTL_UDQIOM_MASK | DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_MASK | DDR_PHY_DX8SLBDQSCTL_DXSR_MASK | DDR_PHY_DX8SLBDQSCTL_DQSNRES_MASK | DDR_PHY_DX8SLBDQSCTL_DQSRES_MASK | 0 ); - - RegVal = ((0x00000000U << DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_SHIFT - | 0x00000001U << DDR_PHY_DX8SLBDQSCTL_RRRMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_SHIFT - | 0x00000001U << DDR_PHY_DX8SLBDQSCTL_WRRMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8SLBDQSCTL_DQSGX_SHIFT - | 0x00000001U << DDR_PHY_DX8SLBDQSCTL_LPPLLPD_SHIFT - | 0x00000001U << DDR_PHY_DX8SLBDQSCTL_LPIOPD_SHIFT - | 0x00000000U << DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_SHIFT - | 0x00000001U << DDR_PHY_DX8SLBDQSCTL_QSCNTEN_SHIFT - | 0x00000000U << DDR_PHY_DX8SLBDQSCTL_UDQIOM_SHIFT - | 0x00000000U << DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_SHIFT - | 0x00000003U << DDR_PHY_DX8SLBDQSCTL_DXSR_SHIFT - | 0x0000000CU << DDR_PHY_DX8SLBDQSCTL_DQSNRES_SHIFT - | 0x00000004U << DDR_PHY_DX8SLBDQSCTL_DQSRES_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8SLBDQSCTL_OFFSET ,0xFFFFFFFFU ,0x012643C4U); - /*############################################################################################################################ */ - - /*Register : PIR @ 0XFD080004

- - Reserved. Return zeroes on reads. - PSU_DDR_PHY_PIR_RESERVED_31 0x0 - - Impedance Calibration Bypass - PSU_DDR_PHY_PIR_ZCALBYP 0x0 - - Digital Delay Line (DDL) Calibration Pause - PSU_DDR_PHY_PIR_DCALPSE 0x0 - - Reserved. Return zeroes on reads. - PSU_DDR_PHY_PIR_RESERVED_28_21 0x0 - - Write DQS2DQ Training - PSU_DDR_PHY_PIR_DQS2DQ 0x0 - - RDIMM Initialization - PSU_DDR_PHY_PIR_RDIMMINIT 0x0 - - Controller DRAM Initialization - PSU_DDR_PHY_PIR_CTLDINIT 0x1 - - VREF Training - PSU_DDR_PHY_PIR_VREF 0x0 - - Static Read Training - PSU_DDR_PHY_PIR_SRD 0x0 - - Write Data Eye Training - PSU_DDR_PHY_PIR_WREYE 0x0 - - Read Data Eye Training - PSU_DDR_PHY_PIR_RDEYE 0x0 - - Write Data Bit Deskew - PSU_DDR_PHY_PIR_WRDSKW 0x0 - - Read Data Bit Deskew - PSU_DDR_PHY_PIR_RDDSKW 0x0 - - Write Leveling Adjust - PSU_DDR_PHY_PIR_WLADJ 0x0 - - Read DQS Gate Training - PSU_DDR_PHY_PIR_QSGATE 0x0 - - Write Leveling - PSU_DDR_PHY_PIR_WL 0x0 - - DRAM Initialization - PSU_DDR_PHY_PIR_DRAMINIT 0x0 - - DRAM Reset (DDR3/DDR4/LPDDR4 Only) - PSU_DDR_PHY_PIR_DRAMRST 0x0 - - PHY Reset - PSU_DDR_PHY_PIR_PHYRST 0x1 - - Digital Delay Line (DDL) Calibration - PSU_DDR_PHY_PIR_DCAL 0x1 - - PLL Initialiazation - PSU_DDR_PHY_PIR_PLLINIT 0x1 - - Reserved. Return zeroes on reads. - PSU_DDR_PHY_PIR_RESERVED_3 0x0 - - CA Training - PSU_DDR_PHY_PIR_CA 0x0 - - Impedance Calibration - PSU_DDR_PHY_PIR_ZCAL 0x1 - - Initialization Trigger - PSU_DDR_PHY_PIR_INIT 0x1 - - PHY Initialization Register - (OFFSET, MASK, VALUE) (0XFD080004, 0xFFFFFFFFU ,0x00040073U) - RegMask = (DDR_PHY_PIR_RESERVED_31_MASK | DDR_PHY_PIR_ZCALBYP_MASK | DDR_PHY_PIR_DCALPSE_MASK | DDR_PHY_PIR_RESERVED_28_21_MASK | DDR_PHY_PIR_DQS2DQ_MASK | DDR_PHY_PIR_RDIMMINIT_MASK | DDR_PHY_PIR_CTLDINIT_MASK | DDR_PHY_PIR_VREF_MASK | DDR_PHY_PIR_SRD_MASK | DDR_PHY_PIR_WREYE_MASK | DDR_PHY_PIR_RDEYE_MASK | DDR_PHY_PIR_WRDSKW_MASK | DDR_PHY_PIR_RDDSKW_MASK | DDR_PHY_PIR_WLADJ_MASK | DDR_PHY_PIR_QSGATE_MASK | DDR_PHY_PIR_WL_MASK | DDR_PHY_PIR_DRAMINIT_MASK | DDR_PHY_PIR_DRAMRST_MASK | DDR_PHY_PIR_PHYRST_MASK | DDR_PHY_PIR_DCAL_MASK | DDR_PHY_PIR_PLLINIT_MASK | DDR_PHY_PIR_RESERVED_3_MASK | DDR_PHY_PIR_CA_MASK | DDR_PHY_PIR_ZCAL_MASK | DDR_PHY_PIR_INIT_MASK | 0 ); - - RegVal = ((0x00000000U << DDR_PHY_PIR_RESERVED_31_SHIFT - | 0x00000000U << DDR_PHY_PIR_ZCALBYP_SHIFT - | 0x00000000U << DDR_PHY_PIR_DCALPSE_SHIFT - | 0x00000000U << DDR_PHY_PIR_RESERVED_28_21_SHIFT - | 0x00000000U << DDR_PHY_PIR_DQS2DQ_SHIFT - | 0x00000000U << DDR_PHY_PIR_RDIMMINIT_SHIFT - | 0x00000001U << DDR_PHY_PIR_CTLDINIT_SHIFT - | 0x00000000U << DDR_PHY_PIR_VREF_SHIFT - | 0x00000000U << DDR_PHY_PIR_SRD_SHIFT - | 0x00000000U << DDR_PHY_PIR_WREYE_SHIFT - | 0x00000000U << DDR_PHY_PIR_RDEYE_SHIFT - | 0x00000000U << DDR_PHY_PIR_WRDSKW_SHIFT - | 0x00000000U << DDR_PHY_PIR_RDDSKW_SHIFT - | 0x00000000U << DDR_PHY_PIR_WLADJ_SHIFT - | 0x00000000U << DDR_PHY_PIR_QSGATE_SHIFT - | 0x00000000U << DDR_PHY_PIR_WL_SHIFT - | 0x00000000U << DDR_PHY_PIR_DRAMINIT_SHIFT - | 0x00000000U << DDR_PHY_PIR_DRAMRST_SHIFT - | 0x00000001U << DDR_PHY_PIR_PHYRST_SHIFT - | 0x00000001U << DDR_PHY_PIR_DCAL_SHIFT - | 0x00000001U << DDR_PHY_PIR_PLLINIT_SHIFT - | 0x00000000U << DDR_PHY_PIR_RESERVED_3_SHIFT - | 0x00000000U << DDR_PHY_PIR_CA_SHIFT - | 0x00000001U << DDR_PHY_PIR_ZCAL_SHIFT - | 0x00000001U << DDR_PHY_PIR_INIT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_PIR_OFFSET ,0xFFFFFFFFU ,0x00040073U); - /*############################################################################################################################ */ - - - return 1; + return 1; } -unsigned long psu_mio_init_data() { - // : MIO PROGRAMMING - /*Register : MIO_PIN_0 @ 0XFF180000

+unsigned long psu_ddr_qos_init_data(void) +{ - Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out- (QSPI Clock) - PSU_IOU_SLCR_MIO_PIN_0_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_0_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[0]- (Test Scan Port) = test_scan, Outp - t, test_scan_out[0]- (Test Scan Port) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_0_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[0]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[0]- (GPIO bank 0) 1= can - , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa - ) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Cloc - ) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_ - lk- (Trace Port Clock) - PSU_IOU_SLCR_MIO_PIN_0_L3_SEL 0 - - Configures MIO Pin 0 peripheral interface mapping. S - (OFFSET, MASK, VALUE) (0XFF180000, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_0_L0_SEL_MASK | IOU_SLCR_MIO_PIN_0_L1_SEL_MASK | IOU_SLCR_MIO_PIN_0_L2_SEL_MASK | IOU_SLCR_MIO_PIN_0_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_0_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_0_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_0_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_0_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_0_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_1 @ 0XFF180004

- - Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (QSPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Data - us) - PSU_IOU_SLCR_MIO_PIN_1_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_1_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[1]- (Test Scan Port) = test_scan, Outp - t, test_scan_out[1]- (Test Scan Port) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_1_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[1]- (GPIO bank 0) 1= can - , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal - 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_o - t- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control - Signal) - PSU_IOU_SLCR_MIO_PIN_1_L3_SEL 0 - - Configures MIO Pin 1 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180004, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_1_L0_SEL_MASK | IOU_SLCR_MIO_PIN_1_L1_SEL_MASK | IOU_SLCR_MIO_PIN_1_L2_SEL_MASK | IOU_SLCR_MIO_PIN_1_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_1_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_1_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_1_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_1_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_1_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_2 @ 0XFF180008

- - Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus) - PSU_IOU_SLCR_MIO_PIN_2_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_2_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[2]- (Test Scan Port) = test_scan, Outp - t, test_scan_out[2]- (Test Scan Port) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_2_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[2]- (GPIO bank 0) 1= can - , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal - 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc2, Input, ttc2_clk_in - (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[0]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_2_L3_SEL 0 - - Configures MIO Pin 2 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180008, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_2_L0_SEL_MASK | IOU_SLCR_MIO_PIN_2_L1_SEL_MASK | IOU_SLCR_MIO_PIN_2_L2_SEL_MASK | IOU_SLCR_MIO_PIN_2_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_2_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_2_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_2_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_2_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_2_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_3 @ 0XFF18000C

- - Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus) - PSU_IOU_SLCR_MIO_PIN_3_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_3_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[3]- (Test Scan Port) = test_scan, Outp - t, test_scan_out[3]- (Test Scan Port) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_3_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[3]- (GPIO bank 0) 1= can - , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa - ) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0 - - (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial - output) 7= trace, Output, tracedq[1]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_3_L3_SEL 0 - - Configures MIO Pin 3 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF18000C, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_3_L0_SEL_MASK | IOU_SLCR_MIO_PIN_3_L1_SEL_MASK | IOU_SLCR_MIO_PIN_3_L2_SEL_MASK | IOU_SLCR_MIO_PIN_3_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_3_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_3_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_3_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_3_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_3_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_4 @ 0XFF180010

- - Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- (QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Data - us) - PSU_IOU_SLCR_MIO_PIN_4_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_4_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[4]- (Test Scan Port) = test_scan, Outp - t, test_scan_out[4]- (Test Scan Port) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_4_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[4]- (GPIO bank 0) 1= can - , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa - ) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_s - - (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, - utput, tracedq[2]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_4_L3_SEL 0 - - Configures MIO Pin 4 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180010, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_4_L0_SEL_MASK | IOU_SLCR_MIO_PIN_4_L1_SEL_MASK | IOU_SLCR_MIO_PIN_4_L2_SEL_MASK | IOU_SLCR_MIO_PIN_4_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_4_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_4_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_4_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_4_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_4_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_5 @ 0XFF180014

- - Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out- (QSPI Slave Select) - PSU_IOU_SLCR_MIO_PIN_5_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_5_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[5]- (Test Scan Port) = test_scan, Outp - t, test_scan_out[5]- (Test Scan Port) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_5_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[5]- (GPIO bank 0) 1= can - , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal - 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi0 - si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7 - trace, Output, tracedq[3]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_5_L3_SEL 0 - - Configures MIO Pin 5 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180014, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_5_L0_SEL_MASK | IOU_SLCR_MIO_PIN_5_L1_SEL_MASK | IOU_SLCR_MIO_PIN_5_L2_SEL_MASK | IOU_SLCR_MIO_PIN_5_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_5_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_5_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_5_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_5_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_5_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_6 @ 0XFF180018

- - Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_clk_for_lpbk- (QSPI Clock to be fed-back) - PSU_IOU_SLCR_MIO_PIN_6_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_6_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[6]- (Test Scan Port) = test_scan, Outp - t, test_scan_out[6]- (Test Scan Port) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_6_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[6]- (GPIO bank 0) 1= can - , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal - 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1 - sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, - Output, tracedq[4]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_6_L3_SEL 0 - - Configures MIO Pin 6 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180018, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_6_L0_SEL_MASK | IOU_SLCR_MIO_PIN_6_L1_SEL_MASK | IOU_SLCR_MIO_PIN_6_L2_SEL_MASK | IOU_SLCR_MIO_PIN_6_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_6_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_6_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_6_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_6_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_6_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_7 @ 0XFF18001C

- - Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out_upper- (QSPI Slave Select upper) - PSU_IOU_SLCR_MIO_PIN_7_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_7_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[7]- (Test Scan Port) = test_scan, Outp - t, test_scan_out[7]- (Test Scan Port) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_7_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[7]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[7]- (GPIO bank 0) 1= can - , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa - ) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= - tc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, - racedq[5]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_7_L3_SEL 0 - - Configures MIO Pin 7 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF18001C, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_7_L0_SEL_MASK | IOU_SLCR_MIO_PIN_7_L1_SEL_MASK | IOU_SLCR_MIO_PIN_7_L2_SEL_MASK | IOU_SLCR_MIO_PIN_7_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_7_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_7_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_7_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_7_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_7_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_8 @ 0XFF180020

- - Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[0]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe - [0]- (QSPI Upper Databus) - PSU_IOU_SLCR_MIO_PIN_8_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_8_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[8]- (Test Scan Port) = test_scan, Outp - t, test_scan_out[8]- (Test Scan Port) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_8_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[8]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[8]- (GPIO bank 0) 1= can - , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa - ) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc - , Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Tr - ce Port Databus) - PSU_IOU_SLCR_MIO_PIN_8_L3_SEL 0 - - Configures MIO Pin 8 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180020, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_8_L0_SEL_MASK | IOU_SLCR_MIO_PIN_8_L1_SEL_MASK | IOU_SLCR_MIO_PIN_8_L2_SEL_MASK | IOU_SLCR_MIO_PIN_8_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_8_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_8_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_8_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_8_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_8_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_9 @ 0XFF180024

- - Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[1]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe - [1]- (QSPI Upper Databus) - PSU_IOU_SLCR_MIO_PIN_9_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NAND chip enable) - PSU_IOU_SLCR_MIO_PIN_9_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[9]- (Test Scan Port) = test_scan, Outp - t, test_scan_out[9]- (Test Scan Port) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_9_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[9]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[9]- (GPIO bank 0) 1= can - , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal - 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, - utput, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (U - RT receiver serial input) 7= trace, Output, tracedq[7]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_9_L3_SEL 0 - - Configures MIO Pin 9 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180024, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_9_L0_SEL_MASK | IOU_SLCR_MIO_PIN_9_L1_SEL_MASK | IOU_SLCR_MIO_PIN_9_L2_SEL_MASK | IOU_SLCR_MIO_PIN_9_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_9_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_9_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_9_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_9_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_9_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_10 @ 0XFF180028

- - Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[2]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe - [2]- (QSPI Upper Databus) - PSU_IOU_SLCR_MIO_PIN_10_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (NAND Ready/Busy) - PSU_IOU_SLCR_MIO_PIN_10_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[10]- (Test Scan Port) = test_scan, Out - ut, test_scan_out[10]- (Test Scan Port) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_10_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[10]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[10]- (GPIO bank 0) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_ - o- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outp - t, tracedq[8]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_10_L3_SEL 0 - - Configures MIO Pin 10 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180028, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_10_L0_SEL_MASK | IOU_SLCR_MIO_PIN_10_L1_SEL_MASK | IOU_SLCR_MIO_PIN_10_L2_SEL_MASK | IOU_SLCR_MIO_PIN_10_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_10_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_10_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_10_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_10_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_10_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_11 @ 0XFF18002C

- - Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[3]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe - [3]- (QSPI Upper Databus) - PSU_IOU_SLCR_MIO_PIN_11_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (NAND Ready/Busy) - PSU_IOU_SLCR_MIO_PIN_11_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[11]- (Test Scan Port) = test_scan, Out - ut, test_scan_out[11]- (Test Scan Port) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_11_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s - i1_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o - tput) 7= trace, Output, tracedq[9]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_11_L3_SEL 0 - - Configures MIO Pin 11 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF18002C, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_11_L0_SEL_MASK | IOU_SLCR_MIO_PIN_11_L1_SEL_MASK | IOU_SLCR_MIO_PIN_11_L2_SEL_MASK | IOU_SLCR_MIO_PIN_11_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_11_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_11_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_11_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_11_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_11_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_12 @ 0XFF180030

- - Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out_upper- (QSPI Upper Clock) - PSU_IOU_SLCR_MIO_PIN_12_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NAND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe - - PSU_IOU_SLCR_MIO_PIN_12_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[12]- (Test Scan Port) = test_scan, Out - ut, test_scan_out[12]- (Test Scan Port) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_12_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[12]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[12]- (GPIO bank 0) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Cl - ck) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trac - dq[10]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_12_L3_SEL 0 - - Configures MIO Pin 12 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180030, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_12_L0_SEL_MASK | IOU_SLCR_MIO_PIN_12_L1_SEL_MASK | IOU_SLCR_MIO_PIN_12_L2_SEL_MASK | IOU_SLCR_MIO_PIN_12_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_12_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_12_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_12_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_12_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_12_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_13 @ 0XFF180034

- - Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_13_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[0]- (NAND chip enable) - PSU_IOU_SLCR_MIO_PIN_13_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8 - bit Data bus) 2= test_scan, Input, test_scan_in[13]- (Test Scan Port) = test_scan, Output, test_scan_out[13]- (Test Scan Port - 3= Not Used - PSU_IOU_SLCR_MIO_PIN_13_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[13]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[13]- (GPIO bank 0) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave - out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq[11]- (Trace Port Dat - bus) - PSU_IOU_SLCR_MIO_PIN_13_L3_SEL 0 - - Configures MIO Pin 13 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180034, 0x000000FEU ,0x00000000U) - RegMask = (IOU_SLCR_MIO_PIN_13_L0_SEL_MASK | IOU_SLCR_MIO_PIN_13_L1_SEL_MASK | IOU_SLCR_MIO_PIN_13_L2_SEL_MASK | IOU_SLCR_MIO_PIN_13_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_13_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_13_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_13_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_13_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_13_OFFSET ,0x000000FEU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_14 @ 0XFF180038

- - Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_14_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_cle- (NAND Command Latch Enable) - PSU_IOU_SLCR_MIO_PIN_14_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8 - bit Data bus) 2= test_scan, Input, test_scan_in[14]- (Test Scan Port) = test_scan, Output, test_scan_out[14]- (Test Scan Port - 3= Not Used - PSU_IOU_SLCR_MIO_PIN_14_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, Input, ttc0_clk_ - n- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_14_L3_SEL 2 - - Configures MIO Pin 14 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180038, 0x000000FEU ,0x00000040U) - RegMask = (IOU_SLCR_MIO_PIN_14_L0_SEL_MASK | IOU_SLCR_MIO_PIN_14_L1_SEL_MASK | IOU_SLCR_MIO_PIN_14_L2_SEL_MASK | IOU_SLCR_MIO_PIN_14_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_14_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_14_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_14_L2_SEL_SHIFT - | 0x00000002U << IOU_SLCR_MIO_PIN_14_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_14_OFFSET ,0x000000FEU ,0x00000040U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_15 @ 0XFF18003C

- - Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_15_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ale- (NAND Address Latch Enable) - PSU_IOU_SLCR_MIO_PIN_15_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8 - bit Data bus) 2= test_scan, Input, test_scan_in[15]- (Test Scan Port) = test_scan, Output, test_scan_out[15]- (Test Scan Port - 3= Not Used - PSU_IOU_SLCR_MIO_PIN_15_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[15]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[15]- (GPIO bank 0) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out - 0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter seri - l output) 7= trace, Output, tracedq[13]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_15_L3_SEL 2 - - Configures MIO Pin 15 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF18003C, 0x000000FEU ,0x00000040U) - RegMask = (IOU_SLCR_MIO_PIN_15_L0_SEL_MASK | IOU_SLCR_MIO_PIN_15_L1_SEL_MASK | IOU_SLCR_MIO_PIN_15_L2_SEL_MASK | IOU_SLCR_MIO_PIN_15_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_15_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_15_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_15_L2_SEL_SHIFT - | 0x00000002U << IOU_SLCR_MIO_PIN_15_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_15_OFFSET ,0x000000FEU ,0x00000040U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_16 @ 0XFF180040

- - Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_16_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[0]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[0]- (NAND - ata Bus) - PSU_IOU_SLCR_MIO_PIN_16_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8 - bit Data bus) 2= test_scan, Input, test_scan_in[16]- (Test Scan Port) = test_scan, Output, test_scan_out[16]- (Test Scan Port - 3= Not Used - PSU_IOU_SLCR_MIO_PIN_16_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[16]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[16]- (GPIO bank 0) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0 - so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace - Output, tracedq[14]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_16_L3_SEL 2 - - Configures MIO Pin 16 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180040, 0x000000FEU ,0x00000040U) - RegMask = (IOU_SLCR_MIO_PIN_16_L0_SEL_MASK | IOU_SLCR_MIO_PIN_16_L1_SEL_MASK | IOU_SLCR_MIO_PIN_16_L2_SEL_MASK | IOU_SLCR_MIO_PIN_16_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_16_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_16_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_16_L2_SEL_SHIFT - | 0x00000002U << IOU_SLCR_MIO_PIN_16_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_16_OFFSET ,0x000000FEU ,0x00000040U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_17 @ 0XFF180044

- - Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_17_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[1]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[1]- (NAND - ata Bus) - PSU_IOU_SLCR_MIO_PIN_17_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8 - bit Data bus) 2= test_scan, Input, test_scan_in[17]- (Test Scan Port) = test_scan, Output, test_scan_out[17]- (Test Scan Port - 3= Not Used - PSU_IOU_SLCR_MIO_PIN_17_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[17]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[17]- (GPIO bank 0) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, sp - 0_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) - 7= trace, Output, tracedq[15]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_17_L3_SEL 2 - - Configures MIO Pin 17 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180044, 0x000000FEU ,0x00000040U) - RegMask = (IOU_SLCR_MIO_PIN_17_L0_SEL_MASK | IOU_SLCR_MIO_PIN_17_L1_SEL_MASK | IOU_SLCR_MIO_PIN_17_L2_SEL_MASK | IOU_SLCR_MIO_PIN_17_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_17_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_17_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_17_L2_SEL_SHIFT - | 0x00000002U << IOU_SLCR_MIO_PIN_17_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_17_OFFSET ,0x000000FEU ,0x00000040U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_18 @ 0XFF180048

- - Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_18_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[2]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[2]- (NAND - ata Bus) - PSU_IOU_SLCR_MIO_PIN_18_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8 - bit Data bus) 2= test_scan, Input, test_scan_in[18]- (Test Scan Port) = test_scan, Output, test_scan_out[18]- (Test Scan Port - 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper) - PSU_IOU_SLCR_MIO_PIN_18_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[18]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[18]- (GPIO bank 0) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_ - o- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used - PSU_IOU_SLCR_MIO_PIN_18_L3_SEL 6 - - Configures MIO Pin 18 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180048, 0x000000FEU ,0x000000C0U) - RegMask = (IOU_SLCR_MIO_PIN_18_L0_SEL_MASK | IOU_SLCR_MIO_PIN_18_L1_SEL_MASK | IOU_SLCR_MIO_PIN_18_L2_SEL_MASK | IOU_SLCR_MIO_PIN_18_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_18_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_18_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_18_L2_SEL_SHIFT - | 0x00000006U << IOU_SLCR_MIO_PIN_18_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_18_OFFSET ,0x000000FEU ,0x000000C0U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_19 @ 0XFF18004C

- - Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_19_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[3]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[3]- (NAND - ata Bus) - PSU_IOU_SLCR_MIO_PIN_19_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8 - bit Data bus) 2= test_scan, Input, test_scan_in[19]- (Test Scan Port) = test_scan, Output, test_scan_out[19]- (Test Scan Port - 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper) - PSU_IOU_SLCR_MIO_PIN_19_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[19]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[19]- (GPIO bank 0) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5 - ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used - PSU_IOU_SLCR_MIO_PIN_19_L3_SEL 6 - - Configures MIO Pin 19 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF18004C, 0x000000FEU ,0x000000C0U) - RegMask = (IOU_SLCR_MIO_PIN_19_L0_SEL_MASK | IOU_SLCR_MIO_PIN_19_L1_SEL_MASK | IOU_SLCR_MIO_PIN_19_L2_SEL_MASK | IOU_SLCR_MIO_PIN_19_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_19_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_19_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_19_L2_SEL_SHIFT - | 0x00000006U << IOU_SLCR_MIO_PIN_19_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_19_OFFSET ,0x000000FEU ,0x000000C0U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_20 @ 0XFF180050

- - Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_20_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[4]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[4]- (NAND - ata Bus) - PSU_IOU_SLCR_MIO_PIN_20_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8 - bit Data bus) 2= test_scan, Input, test_scan_in[20]- (Test Scan Port) = test_scan, Output, test_scan_out[20]- (Test Scan Port - 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper) - PSU_IOU_SLCR_MIO_PIN_20_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[20]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[20]- (GPIO bank 0) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= t - c1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Used - PSU_IOU_SLCR_MIO_PIN_20_L3_SEL 6 - - Configures MIO Pin 20 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180050, 0x000000FEU ,0x000000C0U) - RegMask = (IOU_SLCR_MIO_PIN_20_L0_SEL_MASK | IOU_SLCR_MIO_PIN_20_L1_SEL_MASK | IOU_SLCR_MIO_PIN_20_L2_SEL_MASK | IOU_SLCR_MIO_PIN_20_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_20_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_20_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_20_L2_SEL_SHIFT - | 0x00000006U << IOU_SLCR_MIO_PIN_20_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_20_OFFSET ,0x000000FEU ,0x000000C0U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_21 @ 0XFF180054

- - Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_21_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[5]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[5]- (NAND - ata Bus) - PSU_IOU_SLCR_MIO_PIN_21_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Comman - Indicator) 2= test_scan, Input, test_scan_in[21]- (Test Scan Port) = test_scan, Output, test_scan_out[21]- (Test Scan Port) - = csu, Input, csu_ext_tamper- (CSU Ext Tamper) - PSU_IOU_SLCR_MIO_PIN_21_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[21]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[21]- (GPIO bank 0) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1 - Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- - UART receiver serial input) 7= Not Used - PSU_IOU_SLCR_MIO_PIN_21_L3_SEL 6 - - Configures MIO Pin 21 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180054, 0x000000FEU ,0x000000C0U) - RegMask = (IOU_SLCR_MIO_PIN_21_L0_SEL_MASK | IOU_SLCR_MIO_PIN_21_L1_SEL_MASK | IOU_SLCR_MIO_PIN_21_L2_SEL_MASK | IOU_SLCR_MIO_PIN_21_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_21_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_21_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_21_L2_SEL_SHIFT - | 0x00000006U << IOU_SLCR_MIO_PIN_21_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_21_OFFSET ,0x000000FEU ,0x000000C0U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_22 @ 0XFF180058

- - Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_22_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_we_b- (NAND Write Enable) - PSU_IOU_SLCR_MIO_PIN_22_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= test_scan, Input, test_scan_in[22]- - (Test Scan Port) = test_scan, Output, test_scan_out[22]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper) - PSU_IOU_SLCR_MIO_PIN_22_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[22]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[22]- (GPIO bank 0) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, sp - 1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not - sed - PSU_IOU_SLCR_MIO_PIN_22_L3_SEL 0 - - Configures MIO Pin 22 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180058, 0x000000FEU ,0x00000000U) - RegMask = (IOU_SLCR_MIO_PIN_22_L0_SEL_MASK | IOU_SLCR_MIO_PIN_22_L1_SEL_MASK | IOU_SLCR_MIO_PIN_22_L2_SEL_MASK | IOU_SLCR_MIO_PIN_22_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_22_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_22_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_22_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_22_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_22_OFFSET ,0x000000FEU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_23 @ 0XFF18005C

- - Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_23_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[6]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[6]- (NAND - ata Bus) - PSU_IOU_SLCR_MIO_PIN_23_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= test_scan, Input, test_scan_in - 23]- (Test Scan Port) = test_scan, Output, test_scan_out[23]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper - - PSU_IOU_SLCR_MIO_PIN_23_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[23]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[23]- (GPIO bank 0) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s - i1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o - tput) 7= Not Used - PSU_IOU_SLCR_MIO_PIN_23_L3_SEL 0 - - Configures MIO Pin 23 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF18005C, 0x000000FEU ,0x00000000U) - RegMask = (IOU_SLCR_MIO_PIN_23_L0_SEL_MASK | IOU_SLCR_MIO_PIN_23_L1_SEL_MASK | IOU_SLCR_MIO_PIN_23_L2_SEL_MASK | IOU_SLCR_MIO_PIN_23_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_23_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_23_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_23_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_23_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_23_OFFSET ,0x000000FEU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_24 @ 0XFF180060

- - Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_24_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[7]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[7]- (NAND - ata Bus) - PSU_IOU_SLCR_MIO_PIN_24_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= test_scan, Input, test - scan_in[24]- (Test Scan Port) = test_scan, Output, test_scan_out[24]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ex - Tamper) - PSU_IOU_SLCR_MIO_PIN_24_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[24]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[24]- (GPIO bank 0) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= Not Used 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, - Output, ua1_txd- (UART transmitter serial output) 7= Not Used - PSU_IOU_SLCR_MIO_PIN_24_L3_SEL 1 - - Configures MIO Pin 24 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180060, 0x000000FEU ,0x00000020U) - RegMask = (IOU_SLCR_MIO_PIN_24_L0_SEL_MASK | IOU_SLCR_MIO_PIN_24_L1_SEL_MASK | IOU_SLCR_MIO_PIN_24_L2_SEL_MASK | IOU_SLCR_MIO_PIN_24_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_24_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_24_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_24_L2_SEL_SHIFT - | 0x00000001U << IOU_SLCR_MIO_PIN_24_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_24_OFFSET ,0x000000FEU ,0x00000020U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_25 @ 0XFF180064

- - Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_25_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_re_n- (NAND Read Enable) - PSU_IOU_SLCR_MIO_PIN_25_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= test_scan, Input, - test_scan_in[25]- (Test Scan Port) = test_scan, Output, test_scan_out[25]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (C - U Ext Tamper) - PSU_IOU_SLCR_MIO_PIN_25_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[25]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[25]- (GPIO bank 0) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= Not Used 5= ttc3, Output, ttc3_wave_out- (TTC Waveform - lock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used - PSU_IOU_SLCR_MIO_PIN_25_L3_SEL 1 - - Configures MIO Pin 25 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180064, 0x000000FEU ,0x00000020U) - RegMask = (IOU_SLCR_MIO_PIN_25_L0_SEL_MASK | IOU_SLCR_MIO_PIN_25_L1_SEL_MASK | IOU_SLCR_MIO_PIN_25_L2_SEL_MASK | IOU_SLCR_MIO_PIN_25_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_25_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_25_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_25_L2_SEL_SHIFT - | 0x00000001U << IOU_SLCR_MIO_PIN_25_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_25_OFFSET ,0x000000FEU ,0x00000020U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_26 @ 0XFF180068

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_clk- (TX RGMII clock) - PSU_IOU_SLCR_MIO_PIN_26_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NAND chip enable) - PSU_IOU_SLCR_MIO_PIN_26_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[0]- (PMU GPI) 2= test_scan, Input, test_scan_in[26]- (Test Sc - n Port) = test_scan, Output, test_scan_out[26]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper) - PSU_IOU_SLCR_MIO_PIN_26_L2_SEL 0 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[0]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[0]- (GPIO bank 1) 1= can - , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal - 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Clock - 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- - Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_26_L3_SEL 0 - - Configures MIO Pin 26 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180068, 0x000000FEU ,0x00000000U) - RegMask = (IOU_SLCR_MIO_PIN_26_L0_SEL_MASK | IOU_SLCR_MIO_PIN_26_L1_SEL_MASK | IOU_SLCR_MIO_PIN_26_L2_SEL_MASK | IOU_SLCR_MIO_PIN_26_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_26_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_26_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_26_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_26_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_26_OFFSET ,0x000000FEU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_27 @ 0XFF18006C

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[0]- (TX RGMII data) - PSU_IOU_SLCR_MIO_PIN_27_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (NAND Ready/Busy) - PSU_IOU_SLCR_MIO_PIN_27_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[1]- (PMU GPI) 2= test_scan, Input, test_scan_in[27]- (Test Sc - n Port) = test_scan, Output, test_scan_out[27]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Outp - t, dp_aux_data_out- (Dp Aux Data) - PSU_IOU_SLCR_MIO_PIN_27_L2_SEL 3 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[1]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[1]- (GPIO bank 1) 1= can - , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa - ) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_ - ut- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port - atabus) - PSU_IOU_SLCR_MIO_PIN_27_L3_SEL 0 - - Configures MIO Pin 27 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF18006C, 0x000000FEU ,0x00000018U) - RegMask = (IOU_SLCR_MIO_PIN_27_L0_SEL_MASK | IOU_SLCR_MIO_PIN_27_L1_SEL_MASK | IOU_SLCR_MIO_PIN_27_L2_SEL_MASK | IOU_SLCR_MIO_PIN_27_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_27_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_27_L1_SEL_SHIFT - | 0x00000003U << IOU_SLCR_MIO_PIN_27_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_27_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_27_OFFSET ,0x000000FEU ,0x00000018U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_28 @ 0XFF180070

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[1]- (TX RGMII data) - PSU_IOU_SLCR_MIO_PIN_28_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (NAND Ready/Busy) - PSU_IOU_SLCR_MIO_PIN_28_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[2]- (PMU GPI) 2= test_scan, Input, test_scan_in[28]- (Test Sc - n Port) = test_scan, Output, test_scan_out[28]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug) - PSU_IOU_SLCR_MIO_PIN_28_L2_SEL 3 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[2]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[2]- (GPIO bank 1) 1= can - , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa - ) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc1, Input, ttc1_clk_i - - (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_28_L3_SEL 0 - - Configures MIO Pin 28 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180070, 0x000000FEU ,0x00000018U) - RegMask = (IOU_SLCR_MIO_PIN_28_L0_SEL_MASK | IOU_SLCR_MIO_PIN_28_L1_SEL_MASK | IOU_SLCR_MIO_PIN_28_L2_SEL_MASK | IOU_SLCR_MIO_PIN_28_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_28_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_28_L1_SEL_SHIFT - | 0x00000003U << IOU_SLCR_MIO_PIN_28_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_28_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_28_OFFSET ,0x000000FEU ,0x00000018U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_29 @ 0XFF180074

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[2]- (TX RGMII data) - PSU_IOU_SLCR_MIO_PIN_29_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal) - PSU_IOU_SLCR_MIO_PIN_29_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[3]- (PMU GPI) 2= test_scan, Input, test_scan_in[29]- (Test Sc - n Port) = test_scan, Output, test_scan_out[29]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Outp - t, dp_aux_data_out- (Dp Aux Data) - PSU_IOU_SLCR_MIO_PIN_29_L2_SEL 3 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[3]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[3]- (GPIO bank 1) 1= can - , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal - 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0] - (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial inpu - ) 7= trace, Output, tracedq[7]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_29_L3_SEL 0 - - Configures MIO Pin 29 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180074, 0x000000FEU ,0x00000018U) - RegMask = (IOU_SLCR_MIO_PIN_29_L0_SEL_MASK | IOU_SLCR_MIO_PIN_29_L1_SEL_MASK | IOU_SLCR_MIO_PIN_29_L2_SEL_MASK | IOU_SLCR_MIO_PIN_29_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_29_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_29_L1_SEL_SHIFT - | 0x00000003U << IOU_SLCR_MIO_PIN_29_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_29_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_29_OFFSET ,0x000000FEU ,0x00000018U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_30 @ 0XFF180078

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[3]- (TX RGMII data) - PSU_IOU_SLCR_MIO_PIN_30_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal) - PSU_IOU_SLCR_MIO_PIN_30_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[4]- (PMU GPI) 2= test_scan, Input, test_scan_in[30]- (Test Sc - n Port) = test_scan, Output, test_scan_out[30]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug) - PSU_IOU_SLCR_MIO_PIN_30_L2_SEL 3 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[4]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[4]- (GPIO bank 1) 1= can - , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal - 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_so - (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output - tracedq[8]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_30_L3_SEL 0 - - Configures MIO Pin 30 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180078, 0x000000FEU ,0x00000018U) - RegMask = (IOU_SLCR_MIO_PIN_30_L0_SEL_MASK | IOU_SLCR_MIO_PIN_30_L1_SEL_MASK | IOU_SLCR_MIO_PIN_30_L2_SEL_MASK | IOU_SLCR_MIO_PIN_30_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_30_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_30_L1_SEL_SHIFT - | 0x00000003U << IOU_SLCR_MIO_PIN_30_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_30_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_30_OFFSET ,0x000000FEU ,0x00000018U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_31 @ 0XFF18007C

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ctl- (TX RGMII control) - PSU_IOU_SLCR_MIO_PIN_31_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal) - PSU_IOU_SLCR_MIO_PIN_31_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[5]- (PMU GPI) 2= test_scan, Input, test_scan_in[31]- (Test Sc - n Port) = test_scan, Output, test_scan_out[31]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper) - PSU_IOU_SLCR_MIO_PIN_31_L2_SEL 0 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[5]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[5]- (GPIO bank 1) 1= can - , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa - ) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi - _si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial out - ut) 7= trace, Output, tracedq[9]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_31_L3_SEL 0 - - Configures MIO Pin 31 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF18007C, 0x000000FEU ,0x00000000U) - RegMask = (IOU_SLCR_MIO_PIN_31_L0_SEL_MASK | IOU_SLCR_MIO_PIN_31_L1_SEL_MASK | IOU_SLCR_MIO_PIN_31_L2_SEL_MASK | IOU_SLCR_MIO_PIN_31_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_31_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_31_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_31_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_31_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_31_OFFSET ,0x000000FEU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_32 @ 0XFF180080

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_clk- (RX RGMII clock) - PSU_IOU_SLCR_MIO_PIN_32_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NAND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe - - PSU_IOU_SLCR_MIO_PIN_32_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[0]- (PMU GPI) 2= test_scan, Input, test_scan_in[32]- (Test S - an Port) = test_scan, Output, test_scan_out[32]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper) - PSU_IOU_SLCR_MIO_PIN_32_L2_SEL 1 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[6]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[6]- (GPIO bank 1) 1= can - , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa - ) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi - _sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= - race, Output, tracedq[10]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_32_L3_SEL 0 - - Configures MIO Pin 32 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180080, 0x000000FEU ,0x00000008U) - RegMask = (IOU_SLCR_MIO_PIN_32_L0_SEL_MASK | IOU_SLCR_MIO_PIN_32_L1_SEL_MASK | IOU_SLCR_MIO_PIN_32_L2_SEL_MASK | IOU_SLCR_MIO_PIN_32_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_32_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_32_L1_SEL_SHIFT - | 0x00000001U << IOU_SLCR_MIO_PIN_32_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_32_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_32_OFFSET ,0x000000FEU ,0x00000008U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_33 @ 0XFF180084

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[0]- (RX RGMII data) - PSU_IOU_SLCR_MIO_PIN_33_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal) - PSU_IOU_SLCR_MIO_PIN_33_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[1]- (PMU GPI) 2= test_scan, Input, test_scan_in[33]- (Test S - an Port) = test_scan, Output, test_scan_out[33]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper) - PSU_IOU_SLCR_MIO_PIN_33_L2_SEL 1 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[7]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[7]- (GPIO bank 1) 1= can - , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal - 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= t - c3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, traced - [11]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_33_L3_SEL 0 - - Configures MIO Pin 33 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180084, 0x000000FEU ,0x00000008U) - RegMask = (IOU_SLCR_MIO_PIN_33_L0_SEL_MASK | IOU_SLCR_MIO_PIN_33_L1_SEL_MASK | IOU_SLCR_MIO_PIN_33_L2_SEL_MASK | IOU_SLCR_MIO_PIN_33_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_33_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_33_L1_SEL_SHIFT - | 0x00000001U << IOU_SLCR_MIO_PIN_33_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_33_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_33_OFFSET ,0x000000FEU ,0x00000008U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_34 @ 0XFF180088

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[1]- (RX RGMII data) - PSU_IOU_SLCR_MIO_PIN_34_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal) - PSU_IOU_SLCR_MIO_PIN_34_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[2]- (PMU GPI) 2= test_scan, Input, test_scan_in[34]- (Test S - an Port) = test_scan, Output, test_scan_out[34]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Out - ut, dp_aux_data_out- (Dp Aux Data) - PSU_IOU_SLCR_MIO_PIN_34_L2_SEL 1 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[8]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[8]- (GPIO bank 1) 1= can - , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal - 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc2 - Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace P - rt Databus) - PSU_IOU_SLCR_MIO_PIN_34_L3_SEL 0 - - Configures MIO Pin 34 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180088, 0x000000FEU ,0x00000008U) - RegMask = (IOU_SLCR_MIO_PIN_34_L0_SEL_MASK | IOU_SLCR_MIO_PIN_34_L1_SEL_MASK | IOU_SLCR_MIO_PIN_34_L2_SEL_MASK | IOU_SLCR_MIO_PIN_34_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_34_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_34_L1_SEL_SHIFT - | 0x00000001U << IOU_SLCR_MIO_PIN_34_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_34_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_34_OFFSET ,0x000000FEU ,0x00000008U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_35 @ 0XFF18008C

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[2]- (RX RGMII data) - PSU_IOU_SLCR_MIO_PIN_35_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal) - PSU_IOU_SLCR_MIO_PIN_35_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[3]- (PMU GPI) 2= test_scan, Input, test_scan_in[35]- (Test S - an Port) = test_scan, Output, test_scan_out[35]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug) - PSU_IOU_SLCR_MIO_PIN_35_L2_SEL 1 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[9]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[9]- (GPIO bank 1) 1= can - , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa - ) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, - Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- - UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_35_L3_SEL 0 - - Configures MIO Pin 35 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF18008C, 0x000000FEU ,0x00000008U) - RegMask = (IOU_SLCR_MIO_PIN_35_L0_SEL_MASK | IOU_SLCR_MIO_PIN_35_L1_SEL_MASK | IOU_SLCR_MIO_PIN_35_L2_SEL_MASK | IOU_SLCR_MIO_PIN_35_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_35_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_35_L1_SEL_SHIFT - | 0x00000001U << IOU_SLCR_MIO_PIN_35_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_35_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_35_OFFSET ,0x000000FEU ,0x00000008U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_36 @ 0XFF180090

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[3]- (RX RGMII data) - PSU_IOU_SLCR_MIO_PIN_36_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal) - PSU_IOU_SLCR_MIO_PIN_36_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[4]- (PMU GPI) 2= test_scan, Input, test_scan_in[36]- (Test S - an Port) = test_scan, Output, test_scan_out[36]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Out - ut, dp_aux_data_out- (Dp Aux Data) - PSU_IOU_SLCR_MIO_PIN_36_L2_SEL 1 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[10]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[10]- (GPIO bank 1) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1 - so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace - Output, tracedq[14]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_36_L3_SEL 0 - - Configures MIO Pin 36 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180090, 0x000000FEU ,0x00000008U) - RegMask = (IOU_SLCR_MIO_PIN_36_L0_SEL_MASK | IOU_SLCR_MIO_PIN_36_L1_SEL_MASK | IOU_SLCR_MIO_PIN_36_L2_SEL_MASK | IOU_SLCR_MIO_PIN_36_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_36_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_36_L1_SEL_SHIFT - | 0x00000001U << IOU_SLCR_MIO_PIN_36_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_36_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_36_OFFSET ,0x000000FEU ,0x00000008U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_37 @ 0XFF180094

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_ctl- (RX RGMII control ) - PSU_IOU_SLCR_MIO_PIN_37_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal) - PSU_IOU_SLCR_MIO_PIN_37_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[5]- (PMU GPI) 2= test_scan, Input, test_scan_in[37]- (Test S - an Port) = test_scan, Output, test_scan_out[37]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug) - PSU_IOU_SLCR_MIO_PIN_37_L2_SEL 1 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[11]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[11]- (GPIO bank 1) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, sp - 1_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) - 7= trace, Output, tracedq[15]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_37_L3_SEL 0 - - Configures MIO Pin 37 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180094, 0x000000FEU ,0x00000008U) - RegMask = (IOU_SLCR_MIO_PIN_37_L0_SEL_MASK | IOU_SLCR_MIO_PIN_37_L1_SEL_MASK | IOU_SLCR_MIO_PIN_37_L2_SEL_MASK | IOU_SLCR_MIO_PIN_37_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_37_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_37_L1_SEL_SHIFT - | 0x00000001U << IOU_SLCR_MIO_PIN_37_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_37_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_37_OFFSET ,0x000000FEU ,0x00000008U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_38 @ 0XFF180098

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_clk- (TX RGMII clock) - PSU_IOU_SLCR_MIO_PIN_38_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_38_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= Not Used 3= Not Used - PSU_IOU_SLCR_MIO_PIN_38_L2_SEL 0 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[12]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[12]- (GPIO bank 1) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Clo - k) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, trace_clk- - (Trace Port Clock) - PSU_IOU_SLCR_MIO_PIN_38_L3_SEL 0 - - Configures MIO Pin 38 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180098, 0x000000FEU ,0x00000000U) - RegMask = (IOU_SLCR_MIO_PIN_38_L0_SEL_MASK | IOU_SLCR_MIO_PIN_38_L1_SEL_MASK | IOU_SLCR_MIO_PIN_38_L2_SEL_MASK | IOU_SLCR_MIO_PIN_38_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_38_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_38_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_38_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_38_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_38_OFFSET ,0x000000FEU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_39 @ 0XFF18009C

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[0]- (TX RGMII data) - PSU_IOU_SLCR_MIO_PIN_39_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_39_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= sd1, Input, sd1_data_i - [4]- (8-bit Data bus) = sd1, Output, sdio1_data_out[4]- (8-bit Data bus) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_39_L2_SEL 0 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[13]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[13]- (GPIO bank 1) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc0, Output, ttc0_wav - _out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, trace_ctl- (Trace Port - Control Signal) - PSU_IOU_SLCR_MIO_PIN_39_L3_SEL 0 - - Configures MIO Pin 39 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF18009C, 0x000000FEU ,0x00000000U) - RegMask = (IOU_SLCR_MIO_PIN_39_L0_SEL_MASK | IOU_SLCR_MIO_PIN_39_L1_SEL_MASK | IOU_SLCR_MIO_PIN_39_L2_SEL_MASK | IOU_SLCR_MIO_PIN_39_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_39_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_39_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_39_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_39_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_39_OFFSET ,0x000000FEU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_40 @ 0XFF1800A0

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[1]- (TX RGMII data) - PSU_IOU_SLCR_MIO_PIN_40_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_40_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Comman - Indicator) 2= sd1, Input, sd1_data_in[5]- (8-bit Data bus) = sd1, Output, sdio1_data_out[5]- (8-bit Data bus) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_40_L2_SEL 0 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[14]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[14]- (GPIO bank 1) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc3, Input, ttc3_clk - in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[0]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_40_L3_SEL 0 - - Configures MIO Pin 40 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800A0, 0x000000FEU ,0x00000000U) - RegMask = (IOU_SLCR_MIO_PIN_40_L0_SEL_MASK | IOU_SLCR_MIO_PIN_40_L1_SEL_MASK | IOU_SLCR_MIO_PIN_40_L2_SEL_MASK | IOU_SLCR_MIO_PIN_40_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_40_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_40_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_40_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_40_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_40_OFFSET ,0x000000FEU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_41 @ 0XFF1800A4

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[2]- (TX RGMII data) - PSU_IOU_SLCR_MIO_PIN_41_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_41_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8 - bit Data bus) 2= sd1, Input, sd1_data_in[6]- (8-bit Data bus) = sd1, Output, sdio1_data_out[6]- (8-bit Data bus) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_41_L2_SEL 0 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[15]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[15]- (GPIO bank 1) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[ - ]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial in - ut) 7= trace, Output, tracedq[1]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_41_L3_SEL 0 - - Configures MIO Pin 41 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800A4, 0x000000FEU ,0x00000000U) - RegMask = (IOU_SLCR_MIO_PIN_41_L0_SEL_MASK | IOU_SLCR_MIO_PIN_41_L1_SEL_MASK | IOU_SLCR_MIO_PIN_41_L2_SEL_MASK | IOU_SLCR_MIO_PIN_41_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_41_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_41_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_41_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_41_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_41_OFFSET ,0x000000FEU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_42 @ 0XFF1800A8

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[3]- (TX RGMII data) - PSU_IOU_SLCR_MIO_PIN_42_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_42_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8 - bit Data bus) 2= sd1, Input, sd1_data_in[7]- (8-bit Data bus) = sd1, Output, sdio1_data_out[7]- (8-bit Data bus) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_42_L2_SEL 0 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_ - o- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outp - t, tracedq[2]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_42_L3_SEL 0 - - Configures MIO Pin 42 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800A8, 0x000000FEU ,0x00000000U) - RegMask = (IOU_SLCR_MIO_PIN_42_L0_SEL_MASK | IOU_SLCR_MIO_PIN_42_L1_SEL_MASK | IOU_SLCR_MIO_PIN_42_L2_SEL_MASK | IOU_SLCR_MIO_PIN_42_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_42_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_42_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_42_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_42_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_42_OFFSET ,0x000000FEU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_43 @ 0XFF1800AC

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ctl- (TX RGMII control) - PSU_IOU_SLCR_MIO_PIN_43_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_43_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8 - bit Data bus) 2= sd1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_43_L2_SEL 2 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, s - i0_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o - tput) 7= trace, Output, tracedq[3]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_43_L3_SEL 0 - - Configures MIO Pin 43 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800AC, 0x000000FEU ,0x00000010U) - RegMask = (IOU_SLCR_MIO_PIN_43_L0_SEL_MASK | IOU_SLCR_MIO_PIN_43_L1_SEL_MASK | IOU_SLCR_MIO_PIN_43_L2_SEL_MASK | IOU_SLCR_MIO_PIN_43_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_43_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_43_L1_SEL_SHIFT - | 0x00000002U << IOU_SLCR_MIO_PIN_43_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_43_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_43_OFFSET ,0x000000FEU ,0x00000010U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_44 @ 0XFF1800B0

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_clk- (RX RGMII clock) - PSU_IOU_SLCR_MIO_PIN_44_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_44_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8 - bit Data bus) 2= sd1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_44_L2_SEL 2 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[18]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[18]- (GPIO bank 1) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, s - i1_sclk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7 - Not Used - PSU_IOU_SLCR_MIO_PIN_44_L3_SEL 0 - - Configures MIO Pin 44 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800B0, 0x000000FEU ,0x00000010U) - RegMask = (IOU_SLCR_MIO_PIN_44_L0_SEL_MASK | IOU_SLCR_MIO_PIN_44_L1_SEL_MASK | IOU_SLCR_MIO_PIN_44_L2_SEL_MASK | IOU_SLCR_MIO_PIN_44_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_44_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_44_L1_SEL_SHIFT - | 0x00000002U << IOU_SLCR_MIO_PIN_44_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_44_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_44_OFFSET ,0x000000FEU ,0x00000010U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_45 @ 0XFF1800B4

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[0]- (RX RGMII data) - PSU_IOU_SLCR_MIO_PIN_45_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_45_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8 - bit Data bus) 2= sd1, Input, sdio1_cd_n- (SD card detect from connector) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_45_L2_SEL 2 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[19]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[19]- (GPIO bank 1) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= - ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used - PSU_IOU_SLCR_MIO_PIN_45_L3_SEL 0 - - Configures MIO Pin 45 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800B4, 0x000000FEU ,0x00000010U) - RegMask = (IOU_SLCR_MIO_PIN_45_L0_SEL_MASK | IOU_SLCR_MIO_PIN_45_L1_SEL_MASK | IOU_SLCR_MIO_PIN_45_L2_SEL_MASK | IOU_SLCR_MIO_PIN_45_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_45_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_45_L1_SEL_SHIFT - | 0x00000002U << IOU_SLCR_MIO_PIN_45_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_45_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_45_OFFSET ,0x000000FEU ,0x00000010U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_46 @ 0XFF1800B8

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[1]- (RX RGMII data) - PSU_IOU_SLCR_MIO_PIN_46_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_46_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8 - bit Data bus) 2= sd1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_out[0]- (8-bit Data bus) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_46_L2_SEL 2 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= tt - 0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used - PSU_IOU_SLCR_MIO_PIN_46_L3_SEL 0 - - Configures MIO Pin 46 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800B8, 0x000000FEU ,0x00000010U) - RegMask = (IOU_SLCR_MIO_PIN_46_L0_SEL_MASK | IOU_SLCR_MIO_PIN_46_L1_SEL_MASK | IOU_SLCR_MIO_PIN_46_L2_SEL_MASK | IOU_SLCR_MIO_PIN_46_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_46_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_46_L1_SEL_SHIFT - | 0x00000002U << IOU_SLCR_MIO_PIN_46_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_46_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_46_OFFSET ,0x000000FEU ,0x00000010U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_47 @ 0XFF1800BC

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[2]- (RX RGMII data) - PSU_IOU_SLCR_MIO_PIN_47_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_47_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8 - bit Data bus) 2= sd1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_out[1]- (8-bit Data bus) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_47_L2_SEL 2 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi - , Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd - (UART transmitter serial output) 7= Not Used - PSU_IOU_SLCR_MIO_PIN_47_L3_SEL 0 - - Configures MIO Pin 47 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800BC, 0x000000FEU ,0x00000010U) - RegMask = (IOU_SLCR_MIO_PIN_47_L0_SEL_MASK | IOU_SLCR_MIO_PIN_47_L1_SEL_MASK | IOU_SLCR_MIO_PIN_47_L2_SEL_MASK | IOU_SLCR_MIO_PIN_47_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_47_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_47_L1_SEL_SHIFT - | 0x00000002U << IOU_SLCR_MIO_PIN_47_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_47_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_47_OFFSET ,0x000000FEU ,0x00000010U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_48 @ 0XFF1800C0

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[3]- (RX RGMII data) - PSU_IOU_SLCR_MIO_PIN_48_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_48_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8 - bit Data bus) 2= sd1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_out[2]- (8-bit Data bus) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_48_L2_SEL 2 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[22]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[22]- (GPIO bank 1) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1 - so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not U - ed - PSU_IOU_SLCR_MIO_PIN_48_L3_SEL 0 - - Configures MIO Pin 48 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800C0, 0x000000FEU ,0x00000010U) - RegMask = (IOU_SLCR_MIO_PIN_48_L0_SEL_MASK | IOU_SLCR_MIO_PIN_48_L1_SEL_MASK | IOU_SLCR_MIO_PIN_48_L2_SEL_MASK | IOU_SLCR_MIO_PIN_48_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_48_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_48_L1_SEL_SHIFT - | 0x00000002U << IOU_SLCR_MIO_PIN_48_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_48_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_48_OFFSET ,0x000000FEU ,0x00000010U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_49 @ 0XFF1800C4

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_ctl- (RX RGMII control ) - PSU_IOU_SLCR_MIO_PIN_49_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_49_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= sd1, Input, sd1_data_in[3]- (8 - bit Data bus) = sd1, Output, sdio1_data_out[3]- (8-bit Data bus) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_49_L2_SEL 2 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[23]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[23]- (GPIO bank 1) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, sp - 1_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) - 7= Not Used - PSU_IOU_SLCR_MIO_PIN_49_L3_SEL 0 - - Configures MIO Pin 49 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800C4, 0x000000FEU ,0x00000010U) - RegMask = (IOU_SLCR_MIO_PIN_49_L0_SEL_MASK | IOU_SLCR_MIO_PIN_49_L1_SEL_MASK | IOU_SLCR_MIO_PIN_49_L2_SEL_MASK | IOU_SLCR_MIO_PIN_49_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_49_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_49_L1_SEL_SHIFT - | 0x00000002U << IOU_SLCR_MIO_PIN_49_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_49_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_49_OFFSET ,0x000000FEU ,0x00000010U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_50 @ 0XFF1800C8

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- (TSU clock) - PSU_IOU_SLCR_MIO_PIN_50_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_50_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= sd1, Input, sd1_c - d_in- (Command Indicator) = sd1, Output, sdio1_cmd_out- (Command Indicator) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_50_L2_SEL 2 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[24]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[24]- (GPIO bank 1) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= ttc2, Input, ttc2 - clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used - PSU_IOU_SLCR_MIO_PIN_50_L3_SEL 0 - - Configures MIO Pin 50 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800C8, 0x000000FEU ,0x00000010U) - RegMask = (IOU_SLCR_MIO_PIN_50_L0_SEL_MASK | IOU_SLCR_MIO_PIN_50_L1_SEL_MASK | IOU_SLCR_MIO_PIN_50_L2_SEL_MASK | IOU_SLCR_MIO_PIN_50_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_50_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_50_L1_SEL_SHIFT - | 0x00000002U << IOU_SLCR_MIO_PIN_50_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_50_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_50_OFFSET ,0x000000FEU ,0x00000010U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_51 @ 0XFF1800CC

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- (TSU clock) - PSU_IOU_SLCR_MIO_PIN_51_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_51_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Output, sdio1_clk_out- (SDSDIO clock) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_51_L2_SEL 2 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[25]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[25]- (GPIO bank 1) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= mdio1, Input, gem1_mdio_in- (MDIO Data) 4= mdio1, Outp - t, gem1_mdio_out- (MDIO Data) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter - serial output) 7= Not Used - PSU_IOU_SLCR_MIO_PIN_51_L3_SEL 0 - - Configures MIO Pin 51 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800CC, 0x000000FEU ,0x00000010U) - RegMask = (IOU_SLCR_MIO_PIN_51_L0_SEL_MASK | IOU_SLCR_MIO_PIN_51_L1_SEL_MASK | IOU_SLCR_MIO_PIN_51_L2_SEL_MASK | IOU_SLCR_MIO_PIN_51_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_51_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_51_L1_SEL_SHIFT - | 0x00000002U << IOU_SLCR_MIO_PIN_51_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_51_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_51_OFFSET ,0x000000FEU ,0x00000010U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_52 @ 0XFF1800D0

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_clk- (TX RGMII clock) - PSU_IOU_SLCR_MIO_PIN_52_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_clk_in- (ULPI Clock) - PSU_IOU_SLCR_MIO_PIN_52_L1_SEL 1 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used - PSU_IOU_SLCR_MIO_PIN_52_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[0]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[0]- (GPIO bank 2) 1= can - , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa - ) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Cloc - ) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_ - lk- (Trace Port Clock) - PSU_IOU_SLCR_MIO_PIN_52_L3_SEL 0 - - Configures MIO Pin 52 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800D0, 0x000000FEU ,0x00000004U) - RegMask = (IOU_SLCR_MIO_PIN_52_L0_SEL_MASK | IOU_SLCR_MIO_PIN_52_L1_SEL_MASK | IOU_SLCR_MIO_PIN_52_L2_SEL_MASK | IOU_SLCR_MIO_PIN_52_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_52_L0_SEL_SHIFT - | 0x00000001U << IOU_SLCR_MIO_PIN_52_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_52_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_52_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_52_OFFSET ,0x000000FEU ,0x00000004U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_53 @ 0XFF1800D4

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[0]- (TX RGMII data) - PSU_IOU_SLCR_MIO_PIN_53_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_dir- (Data bus direction control) - PSU_IOU_SLCR_MIO_PIN_53_L1_SEL 1 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used - PSU_IOU_SLCR_MIO_PIN_53_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[1]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[1]- (GPIO bank 2) 1= can - , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal - 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_o - t- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control - Signal) - PSU_IOU_SLCR_MIO_PIN_53_L3_SEL 0 - - Configures MIO Pin 53 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800D4, 0x000000FEU ,0x00000004U) - RegMask = (IOU_SLCR_MIO_PIN_53_L0_SEL_MASK | IOU_SLCR_MIO_PIN_53_L1_SEL_MASK | IOU_SLCR_MIO_PIN_53_L2_SEL_MASK | IOU_SLCR_MIO_PIN_53_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_53_L0_SEL_SHIFT - | 0x00000001U << IOU_SLCR_MIO_PIN_53_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_53_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_53_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_53_OFFSET ,0x000000FEU ,0x00000004U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_54 @ 0XFF1800D8

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[1]- (TX RGMII data) - PSU_IOU_SLCR_MIO_PIN_54_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[2]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_ - ata[2]- (ULPI data bus) - PSU_IOU_SLCR_MIO_PIN_54_L1_SEL 1 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used - PSU_IOU_SLCR_MIO_PIN_54_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[2]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[2]- (GPIO bank 2) 1= can - , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal - 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, Input, ttc0_clk_in - (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[0]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_54_L3_SEL 0 - - Configures MIO Pin 54 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800D8, 0x000000FEU ,0x00000004U) - RegMask = (IOU_SLCR_MIO_PIN_54_L0_SEL_MASK | IOU_SLCR_MIO_PIN_54_L1_SEL_MASK | IOU_SLCR_MIO_PIN_54_L2_SEL_MASK | IOU_SLCR_MIO_PIN_54_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_54_L0_SEL_SHIFT - | 0x00000001U << IOU_SLCR_MIO_PIN_54_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_54_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_54_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_54_OFFSET ,0x000000FEU ,0x00000004U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_55 @ 0XFF1800DC

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[2]- (TX RGMII data) - PSU_IOU_SLCR_MIO_PIN_55_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_nxt- (Data flow control signal from the PHY) - PSU_IOU_SLCR_MIO_PIN_55_L1_SEL 1 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used - PSU_IOU_SLCR_MIO_PIN_55_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[3]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[3]- (GPIO bank 2) 1= can - , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa - ) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0 - - (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial - output) 7= trace, Output, tracedq[1]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_55_L3_SEL 0 - - Configures MIO Pin 55 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800DC, 0x000000FEU ,0x00000004U) - RegMask = (IOU_SLCR_MIO_PIN_55_L0_SEL_MASK | IOU_SLCR_MIO_PIN_55_L1_SEL_MASK | IOU_SLCR_MIO_PIN_55_L2_SEL_MASK | IOU_SLCR_MIO_PIN_55_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_55_L0_SEL_SHIFT - | 0x00000001U << IOU_SLCR_MIO_PIN_55_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_55_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_55_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_55_OFFSET ,0x000000FEU ,0x00000004U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_56 @ 0XFF1800E0

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[3]- (TX RGMII data) - PSU_IOU_SLCR_MIO_PIN_56_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[0]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_ - ata[0]- (ULPI data bus) - PSU_IOU_SLCR_MIO_PIN_56_L1_SEL 1 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used - PSU_IOU_SLCR_MIO_PIN_56_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[4]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[4]- (GPIO bank 2) 1= can - , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa - ) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_s - - (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, - utput, tracedq[2]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_56_L3_SEL 0 - - Configures MIO Pin 56 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800E0, 0x000000FEU ,0x00000004U) - RegMask = (IOU_SLCR_MIO_PIN_56_L0_SEL_MASK | IOU_SLCR_MIO_PIN_56_L1_SEL_MASK | IOU_SLCR_MIO_PIN_56_L2_SEL_MASK | IOU_SLCR_MIO_PIN_56_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_56_L0_SEL_SHIFT - | 0x00000001U << IOU_SLCR_MIO_PIN_56_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_56_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_56_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_56_OFFSET ,0x000000FEU ,0x00000004U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_57 @ 0XFF1800E4

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_ctl- (TX RGMII control) - PSU_IOU_SLCR_MIO_PIN_57_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[1]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_ - ata[1]- (ULPI data bus) - PSU_IOU_SLCR_MIO_PIN_57_L1_SEL 1 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used - PSU_IOU_SLCR_MIO_PIN_57_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[5]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[5]- (GPIO bank 2) 1= can - , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal - 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi0 - si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7 - trace, Output, tracedq[3]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_57_L3_SEL 0 - - Configures MIO Pin 57 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800E4, 0x000000FEU ,0x00000004U) - RegMask = (IOU_SLCR_MIO_PIN_57_L0_SEL_MASK | IOU_SLCR_MIO_PIN_57_L1_SEL_MASK | IOU_SLCR_MIO_PIN_57_L2_SEL_MASK | IOU_SLCR_MIO_PIN_57_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_57_L0_SEL_SHIFT - | 0x00000001U << IOU_SLCR_MIO_PIN_57_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_57_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_57_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_57_OFFSET ,0x000000FEU ,0x00000004U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_58 @ 0XFF1800E8

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_clk- (RX RGMII clock) - PSU_IOU_SLCR_MIO_PIN_58_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Output, usb0_ulpi_stp- (Asserted to end or interrupt transfers) - PSU_IOU_SLCR_MIO_PIN_58_L1_SEL 1 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used - PSU_IOU_SLCR_MIO_PIN_58_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[6]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[6]- (GPIO bank 2) 1= can - , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal - 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1_sclk_out- (SPI Clock - 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- - Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_58_L3_SEL 0 - - Configures MIO Pin 58 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800E8, 0x000000FEU ,0x00000004U) - RegMask = (IOU_SLCR_MIO_PIN_58_L0_SEL_MASK | IOU_SLCR_MIO_PIN_58_L1_SEL_MASK | IOU_SLCR_MIO_PIN_58_L2_SEL_MASK | IOU_SLCR_MIO_PIN_58_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_58_L0_SEL_SHIFT - | 0x00000001U << IOU_SLCR_MIO_PIN_58_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_58_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_58_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_58_OFFSET ,0x000000FEU ,0x00000004U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_59 @ 0XFF1800EC

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[0]- (RX RGMII data) - PSU_IOU_SLCR_MIO_PIN_59_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[3]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_ - ata[3]- (ULPI data bus) - PSU_IOU_SLCR_MIO_PIN_59_L1_SEL 1 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used - PSU_IOU_SLCR_MIO_PIN_59_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[7]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[7]- (GPIO bank 2) 1= can - , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa - ) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_ - ut- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port - atabus) - PSU_IOU_SLCR_MIO_PIN_59_L3_SEL 0 - - Configures MIO Pin 59 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800EC, 0x000000FEU ,0x00000004U) - RegMask = (IOU_SLCR_MIO_PIN_59_L0_SEL_MASK | IOU_SLCR_MIO_PIN_59_L1_SEL_MASK | IOU_SLCR_MIO_PIN_59_L2_SEL_MASK | IOU_SLCR_MIO_PIN_59_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_59_L0_SEL_SHIFT - | 0x00000001U << IOU_SLCR_MIO_PIN_59_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_59_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_59_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_59_OFFSET ,0x000000FEU ,0x00000004U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_60 @ 0XFF1800F0

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[1]- (RX RGMII data) - PSU_IOU_SLCR_MIO_PIN_60_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[4]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_ - ata[4]- (ULPI data bus) - PSU_IOU_SLCR_MIO_PIN_60_L1_SEL 1 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used - PSU_IOU_SLCR_MIO_PIN_60_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[8]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[8]- (GPIO bank 2) 1= can - , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa - ) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc1, Input, ttc1_clk_i - - (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_60_L3_SEL 0 - - Configures MIO Pin 60 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800F0, 0x000000FEU ,0x00000004U) - RegMask = (IOU_SLCR_MIO_PIN_60_L0_SEL_MASK | IOU_SLCR_MIO_PIN_60_L1_SEL_MASK | IOU_SLCR_MIO_PIN_60_L2_SEL_MASK | IOU_SLCR_MIO_PIN_60_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_60_L0_SEL_SHIFT - | 0x00000001U << IOU_SLCR_MIO_PIN_60_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_60_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_60_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_60_OFFSET ,0x000000FEU ,0x00000004U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_61 @ 0XFF1800F4

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[2]- (RX RGMII data) - PSU_IOU_SLCR_MIO_PIN_61_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[5]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_ - ata[5]- (ULPI data bus) - PSU_IOU_SLCR_MIO_PIN_61_L1_SEL 1 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used - PSU_IOU_SLCR_MIO_PIN_61_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[9]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[9]- (GPIO bank 2) 1= can - , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal - 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, Output, spi1_n_ss_out[0] - (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial inpu - ) 7= trace, Output, tracedq[7]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_61_L3_SEL 0 - - Configures MIO Pin 61 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800F4, 0x000000FEU ,0x00000004U) - RegMask = (IOU_SLCR_MIO_PIN_61_L0_SEL_MASK | IOU_SLCR_MIO_PIN_61_L1_SEL_MASK | IOU_SLCR_MIO_PIN_61_L2_SEL_MASK | IOU_SLCR_MIO_PIN_61_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_61_L0_SEL_SHIFT - | 0x00000001U << IOU_SLCR_MIO_PIN_61_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_61_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_61_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_61_OFFSET ,0x000000FEU ,0x00000004U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_62 @ 0XFF1800F8

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[3]- (RX RGMII data) - PSU_IOU_SLCR_MIO_PIN_62_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[6]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_ - ata[6]- (ULPI data bus) - PSU_IOU_SLCR_MIO_PIN_62_L1_SEL 1 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used - PSU_IOU_SLCR_MIO_PIN_62_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[10]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[10]- (GPIO bank 2) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_ - o- (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outp - t, tracedq[8]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_62_L3_SEL 0 - - Configures MIO Pin 62 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800F8, 0x000000FEU ,0x00000004U) - RegMask = (IOU_SLCR_MIO_PIN_62_L0_SEL_MASK | IOU_SLCR_MIO_PIN_62_L1_SEL_MASK | IOU_SLCR_MIO_PIN_62_L2_SEL_MASK | IOU_SLCR_MIO_PIN_62_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_62_L0_SEL_SHIFT - | 0x00000001U << IOU_SLCR_MIO_PIN_62_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_62_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_62_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_62_OFFSET ,0x000000FEU ,0x00000004U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_63 @ 0XFF1800FC

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_ctl- (RX RGMII control ) - PSU_IOU_SLCR_MIO_PIN_63_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[7]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_ - ata[7]- (ULPI data bus) - PSU_IOU_SLCR_MIO_PIN_63_L1_SEL 1 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used - PSU_IOU_SLCR_MIO_PIN_63_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[11]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[11]- (GPIO bank 2) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s - i1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o - tput) 7= trace, Output, tracedq[9]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_63_L3_SEL 0 - - Configures MIO Pin 63 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800FC, 0x000000FEU ,0x00000004U) - RegMask = (IOU_SLCR_MIO_PIN_63_L0_SEL_MASK | IOU_SLCR_MIO_PIN_63_L1_SEL_MASK | IOU_SLCR_MIO_PIN_63_L2_SEL_MASK | IOU_SLCR_MIO_PIN_63_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_63_L0_SEL_SHIFT - | 0x00000001U << IOU_SLCR_MIO_PIN_63_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_63_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_63_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_63_OFFSET ,0x000000FEU ,0x00000004U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_64 @ 0XFF180100

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_clk- (TX RGMII clock) - PSU_IOU_SLCR_MIO_PIN_64_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_clk_in- (ULPI Clock) - PSU_IOU_SLCR_MIO_PIN_64_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= Not Used 3= Not Used - PSU_IOU_SLCR_MIO_PIN_64_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[12]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[12]- (GPIO bank 2) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, s - i0_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7 - trace, Output, tracedq[10]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_64_L3_SEL 0 - - Configures MIO Pin 64 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180100, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_64_L0_SEL_MASK | IOU_SLCR_MIO_PIN_64_L1_SEL_MASK | IOU_SLCR_MIO_PIN_64_L2_SEL_MASK | IOU_SLCR_MIO_PIN_64_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_64_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_64_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_64_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_64_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_64_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_65 @ 0XFF180104

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[0]- (TX RGMII data) - PSU_IOU_SLCR_MIO_PIN_65_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_dir- (Data bus direction control) - PSU_IOU_SLCR_MIO_PIN_65_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= Not Used 3= Not Used - PSU_IOU_SLCR_MIO_PIN_65_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[13]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[13]- (GPIO bank 2) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= - ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trac - dq[11]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_65_L3_SEL 0 - - Configures MIO Pin 65 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180104, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_65_L0_SEL_MASK | IOU_SLCR_MIO_PIN_65_L1_SEL_MASK | IOU_SLCR_MIO_PIN_65_L2_SEL_MASK | IOU_SLCR_MIO_PIN_65_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_65_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_65_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_65_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_65_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_65_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_66 @ 0XFF180108

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[1]- (TX RGMII data) - PSU_IOU_SLCR_MIO_PIN_66_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[2]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_ - ata[2]- (ULPI data bus) - PSU_IOU_SLCR_MIO_PIN_66_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Comman - Indicator) 2= Not Used 3= Not Used - PSU_IOU_SLCR_MIO_PIN_66_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[14]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[14]- (GPIO bank 2) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= tt - 2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace - Port Databus) - PSU_IOU_SLCR_MIO_PIN_66_L3_SEL 0 - - Configures MIO Pin 66 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180108, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_66_L0_SEL_MASK | IOU_SLCR_MIO_PIN_66_L1_SEL_MASK | IOU_SLCR_MIO_PIN_66_L2_SEL_MASK | IOU_SLCR_MIO_PIN_66_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_66_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_66_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_66_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_66_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_66_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_67 @ 0XFF18010C

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[2]- (TX RGMII data) - PSU_IOU_SLCR_MIO_PIN_67_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_nxt- (Data flow control signal from the PHY) - PSU_IOU_SLCR_MIO_PIN_67_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8 - bit Data bus) 2= Not Used 3= Not Used - PSU_IOU_SLCR_MIO_PIN_67_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[15]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[15]- (GPIO bank 2) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi - , Output, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd - (UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_67_L3_SEL 0 - - Configures MIO Pin 67 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF18010C, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_67_L0_SEL_MASK | IOU_SLCR_MIO_PIN_67_L1_SEL_MASK | IOU_SLCR_MIO_PIN_67_L2_SEL_MASK | IOU_SLCR_MIO_PIN_67_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_67_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_67_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_67_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_67_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_67_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_68 @ 0XFF180110

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[3]- (TX RGMII data) - PSU_IOU_SLCR_MIO_PIN_68_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[0]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_ - ata[0]- (ULPI data bus) - PSU_IOU_SLCR_MIO_PIN_68_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8 - bit Data bus) 2= Not Used 3= Not Used - PSU_IOU_SLCR_MIO_PIN_68_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[16]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[16]- (GPIO bank 2) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0 - so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace - Output, tracedq[14]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_68_L3_SEL 0 - - Configures MIO Pin 68 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180110, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_68_L0_SEL_MASK | IOU_SLCR_MIO_PIN_68_L1_SEL_MASK | IOU_SLCR_MIO_PIN_68_L2_SEL_MASK | IOU_SLCR_MIO_PIN_68_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_68_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_68_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_68_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_68_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_68_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_69 @ 0XFF180114

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_ctl- (TX RGMII control) - PSU_IOU_SLCR_MIO_PIN_69_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[1]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_ - ata[1]- (ULPI data bus) - PSU_IOU_SLCR_MIO_PIN_69_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8 - bit Data bus) 2= sd1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_69_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[17]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[17]- (GPIO bank 2) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, sp - 0_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) - 7= trace, Output, tracedq[15]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_69_L3_SEL 0 - - Configures MIO Pin 69 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180114, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_69_L0_SEL_MASK | IOU_SLCR_MIO_PIN_69_L1_SEL_MASK | IOU_SLCR_MIO_PIN_69_L2_SEL_MASK | IOU_SLCR_MIO_PIN_69_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_69_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_69_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_69_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_69_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_69_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_70 @ 0XFF180118

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_clk- (RX RGMII clock) - PSU_IOU_SLCR_MIO_PIN_70_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Output, usb1_ulpi_stp- (Asserted to end or interrupt transfers) - PSU_IOU_SLCR_MIO_PIN_70_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8 - bit Data bus) 2= sd1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_70_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[18]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[18]- (GPIO bank 2) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, sp - 1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not - sed - PSU_IOU_SLCR_MIO_PIN_70_L3_SEL 0 - - Configures MIO Pin 70 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180118, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_70_L0_SEL_MASK | IOU_SLCR_MIO_PIN_70_L1_SEL_MASK | IOU_SLCR_MIO_PIN_70_L2_SEL_MASK | IOU_SLCR_MIO_PIN_70_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_70_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_70_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_70_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_70_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_70_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_71 @ 0XFF18011C

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[0]- (RX RGMII data) - PSU_IOU_SLCR_MIO_PIN_71_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[3]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_ - ata[3]- (ULPI data bus) - PSU_IOU_SLCR_MIO_PIN_71_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8 - bit Data bus) 2= sd1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_out[0]- (8-bit Data bus) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_71_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[19]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[19]- (GPIO bank 2) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5 - ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used - PSU_IOU_SLCR_MIO_PIN_71_L3_SEL 0 - - Configures MIO Pin 71 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF18011C, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_71_L0_SEL_MASK | IOU_SLCR_MIO_PIN_71_L1_SEL_MASK | IOU_SLCR_MIO_PIN_71_L2_SEL_MASK | IOU_SLCR_MIO_PIN_71_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_71_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_71_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_71_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_71_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_71_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_72 @ 0XFF180120

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[1]- (RX RGMII data) - PSU_IOU_SLCR_MIO_PIN_72_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[4]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_ - ata[4]- (ULPI data bus) - PSU_IOU_SLCR_MIO_PIN_72_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8 - bit Data bus) 2= sd1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_out[1]- (8-bit Data bus) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_72_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[20]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[20]- (GPIO bank 2) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= N - t Used 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Used - PSU_IOU_SLCR_MIO_PIN_72_L3_SEL 0 - - Configures MIO Pin 72 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180120, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_72_L0_SEL_MASK | IOU_SLCR_MIO_PIN_72_L1_SEL_MASK | IOU_SLCR_MIO_PIN_72_L2_SEL_MASK | IOU_SLCR_MIO_PIN_72_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_72_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_72_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_72_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_72_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_72_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_73 @ 0XFF180124

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[2]- (RX RGMII data) - PSU_IOU_SLCR_MIO_PIN_73_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_ - ata[5]- (ULPI data bus) - PSU_IOU_SLCR_MIO_PIN_73_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8 - bit Data bus) 2= sd1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_out[2]- (8-bit Data bus) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_73_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[21]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[21]- (GPIO bank 2) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1 - Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= Not Used 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used - PSU_IOU_SLCR_MIO_PIN_73_L3_SEL 0 - - Configures MIO Pin 73 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180124, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_73_L0_SEL_MASK | IOU_SLCR_MIO_PIN_73_L1_SEL_MASK | IOU_SLCR_MIO_PIN_73_L2_SEL_MASK | IOU_SLCR_MIO_PIN_73_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_73_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_73_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_73_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_73_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_73_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_74 @ 0XFF180128

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[3]- (RX RGMII data) - PSU_IOU_SLCR_MIO_PIN_74_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[6]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_ - ata[6]- (ULPI data bus) - PSU_IOU_SLCR_MIO_PIN_74_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8 - bit Data bus) 2= sd1, Input, sd1_data_in[3]- (8-bit Data bus) = sd1, Output, sdio1_data_out[3]- (8-bit Data bus) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_74_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[22]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[22]- (GPIO bank 2) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_ - o- (MISO signal) 5= Not Used 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used - PSU_IOU_SLCR_MIO_PIN_74_L3_SEL 0 - - Configures MIO Pin 74 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180128, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_74_L0_SEL_MASK | IOU_SLCR_MIO_PIN_74_L1_SEL_MASK | IOU_SLCR_MIO_PIN_74_L2_SEL_MASK | IOU_SLCR_MIO_PIN_74_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_74_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_74_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_74_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_74_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_74_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_75 @ 0XFF18012C

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_ctl- (RX RGMII control ) - PSU_IOU_SLCR_MIO_PIN_75_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[7]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_ - ata[7]- (ULPI data bus) - PSU_IOU_SLCR_MIO_PIN_75_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= sd1, Input, sd1_cmd_in- (Comma - d Indicator) = sd1, Output, sdio1_cmd_out- (Command Indicator) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_75_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[23]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[23]- (GPIO bank 2) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s - i1_si- (MOSI signal) 5= Not Used 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used - PSU_IOU_SLCR_MIO_PIN_75_L3_SEL 0 - - Configures MIO Pin 75 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF18012C, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_75_L0_SEL_MASK | IOU_SLCR_MIO_PIN_75_L1_SEL_MASK | IOU_SLCR_MIO_PIN_75_L2_SEL_MASK | IOU_SLCR_MIO_PIN_75_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_75_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_75_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_75_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_75_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_75_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_76 @ 0XFF180130

- - Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_76_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_76_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= sd1, Output, sdio - _clk_out- (SDSDIO clock) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_76_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[24]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[24]- (GPIO bank 2) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= mdio0, Output, gem0_mdc- (MDIO Clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= mdio2, Output, gem2_mdc- (MDIO Clock - 6= mdio3, Output, gem3_mdc- (MDIO Clock) 7= Not Used - PSU_IOU_SLCR_MIO_PIN_76_L3_SEL 6 - - Configures MIO Pin 76 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180130, 0x000000FEU ,0x000000C0U) - RegMask = (IOU_SLCR_MIO_PIN_76_L0_SEL_MASK | IOU_SLCR_MIO_PIN_76_L1_SEL_MASK | IOU_SLCR_MIO_PIN_76_L2_SEL_MASK | IOU_SLCR_MIO_PIN_76_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_76_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_76_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_76_L2_SEL_SHIFT - | 0x00000006U << IOU_SLCR_MIO_PIN_76_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_76_OFFSET ,0x000000FEU ,0x000000C0U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_77 @ 0XFF180134

- - Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_77_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_77_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Input, sdio1_cd_n- (SD card detect from connector) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_77_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[25]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[25]- (GPIO bank 2) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= mdio0, Input, gem0_mdio_in- (MDIO Data) 3= mdio0, Output, gem0_mdio_out- (MDIO Data) 4= mdio1, Input, gem1_mdio_in- (MD - O Data) 4= mdio1, Output, gem1_mdio_out- (MDIO Data) 5= mdio2, Input, gem2_mdio_in- (MDIO Data) 5= mdio2, Output, gem2_mdio_o - t- (MDIO Data) 6= mdio3, Input, gem3_mdio_in- (MDIO Data) 6= mdio3, Output, gem3_mdio_out- (MDIO Data) 7= Not Used - PSU_IOU_SLCR_MIO_PIN_77_L3_SEL 6 - - Configures MIO Pin 77 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180134, 0x000000FEU ,0x000000C0U) - RegMask = (IOU_SLCR_MIO_PIN_77_L0_SEL_MASK | IOU_SLCR_MIO_PIN_77_L1_SEL_MASK | IOU_SLCR_MIO_PIN_77_L2_SEL_MASK | IOU_SLCR_MIO_PIN_77_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_77_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_77_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_77_L2_SEL_SHIFT - | 0x00000006U << IOU_SLCR_MIO_PIN_77_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_77_OFFSET ,0x000000FEU ,0x000000C0U); - /*############################################################################################################################ */ - - /*Register : MIO_MST_TRI0 @ 0XFF180204

- - Master Tri-state Enable for pin 0, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI 0 - - Master Tri-state Enable for pin 1, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI 0 - - Master Tri-state Enable for pin 2, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI 0 - - Master Tri-state Enable for pin 3, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI 0 - - Master Tri-state Enable for pin 4, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI 0 - - Master Tri-state Enable for pin 5, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI 0 - - Master Tri-state Enable for pin 6, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI 0 - - Master Tri-state Enable for pin 7, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI 0 - - Master Tri-state Enable for pin 8, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI 0 - - Master Tri-state Enable for pin 9, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI 0 - - Master Tri-state Enable for pin 10, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI 0 - - Master Tri-state Enable for pin 11, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI 0 - - Master Tri-state Enable for pin 12, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI 0 - - Master Tri-state Enable for pin 13, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI 0 - - Master Tri-state Enable for pin 14, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI 0 - - Master Tri-state Enable for pin 15, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI 0 - - Master Tri-state Enable for pin 16, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI 0 - - Master Tri-state Enable for pin 17, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI 0 - - Master Tri-state Enable for pin 18, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI 1 - - Master Tri-state Enable for pin 19, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI 0 - - Master Tri-state Enable for pin 20, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI 0 - - Master Tri-state Enable for pin 21, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI 1 - - Master Tri-state Enable for pin 22, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI 0 - - Master Tri-state Enable for pin 23, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI 0 - - Master Tri-state Enable for pin 24, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI 0 - - Master Tri-state Enable for pin 25, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI 1 - - Master Tri-state Enable for pin 26, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI 0 - - Master Tri-state Enable for pin 27, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI 0 - - Master Tri-state Enable for pin 28, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI 1 - - Master Tri-state Enable for pin 29, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI 0 - - Master Tri-state Enable for pin 30, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI 1 - - Master Tri-state Enable for pin 31, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI 0 - - MIO pin Tri-state Enables, 31:0 - (OFFSET, MASK, VALUE) (0XFF180204, 0xFFFFFFFFU ,0x52240000U) - RegMask = (IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_SHIFT - | 0x00000001U << IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_SHIFT - | 0x00000001U << IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_SHIFT - | 0x00000001U << IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_SHIFT - | 0x00000001U << IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_SHIFT - | 0x00000001U << IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_MST_TRI0_OFFSET ,0xFFFFFFFFU ,0x52240000U); - /*############################################################################################################################ */ - - /*Register : MIO_MST_TRI1 @ 0XFF180208

- - Master Tri-state Enable for pin 32, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI 0 - - Master Tri-state Enable for pin 33, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI 0 - - Master Tri-state Enable for pin 34, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI 0 - - Master Tri-state Enable for pin 35, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI 0 - - Master Tri-state Enable for pin 36, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI 0 - - Master Tri-state Enable for pin 37, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI 0 - - Master Tri-state Enable for pin 38, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI 0 - - Master Tri-state Enable for pin 39, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI 0 - - Master Tri-state Enable for pin 40, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI 0 - - Master Tri-state Enable for pin 41, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI 0 - - Master Tri-state Enable for pin 42, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI 0 - - Master Tri-state Enable for pin 43, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI 0 - - Master Tri-state Enable for pin 44, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI 1 - - Master Tri-state Enable for pin 45, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI 1 - - Master Tri-state Enable for pin 46, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI 0 - - Master Tri-state Enable for pin 47, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI 0 - - Master Tri-state Enable for pin 48, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI 0 - - Master Tri-state Enable for pin 49, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI 0 - - Master Tri-state Enable for pin 50, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI 0 - - Master Tri-state Enable for pin 51, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI 0 - - Master Tri-state Enable for pin 52, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI 1 - - Master Tri-state Enable for pin 53, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI 1 - - Master Tri-state Enable for pin 54, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI 0 - - Master Tri-state Enable for pin 55, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI 1 - - Master Tri-state Enable for pin 56, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI 0 - - Master Tri-state Enable for pin 57, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI 0 - - Master Tri-state Enable for pin 58, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI 0 - - Master Tri-state Enable for pin 59, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI 0 - - Master Tri-state Enable for pin 60, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI 0 - - Master Tri-state Enable for pin 61, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI 0 - - Master Tri-state Enable for pin 62, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI 0 - - Master Tri-state Enable for pin 63, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI 0 - - MIO pin Tri-state Enables, 63:32 - (OFFSET, MASK, VALUE) (0XFF180208, 0xFFFFFFFFU ,0x00B03000U) - RegMask = (IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_SHIFT - | 0x00000001U << IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_SHIFT - | 0x00000001U << IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_SHIFT - | 0x00000001U << IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_SHIFT - | 0x00000001U << IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_SHIFT - | 0x00000001U << IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_MST_TRI1_OFFSET ,0xFFFFFFFFU ,0x00B03000U); - /*############################################################################################################################ */ - - /*Register : MIO_MST_TRI2 @ 0XFF18020C

- - Master Tri-state Enable for pin 64, active high - PSU_IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI 0 - - Master Tri-state Enable for pin 65, active high - PSU_IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI 0 - - Master Tri-state Enable for pin 66, active high - PSU_IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI 0 - - Master Tri-state Enable for pin 67, active high - PSU_IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI 0 - - Master Tri-state Enable for pin 68, active high - PSU_IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI 0 - - Master Tri-state Enable for pin 69, active high - PSU_IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI 0 - - Master Tri-state Enable for pin 70, active high - PSU_IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI 1 - - Master Tri-state Enable for pin 71, active high - PSU_IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI 1 - - Master Tri-state Enable for pin 72, active high - PSU_IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI 1 - - Master Tri-state Enable for pin 73, active high - PSU_IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI 1 - - Master Tri-state Enable for pin 74, active high - PSU_IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI 1 - - Master Tri-state Enable for pin 75, active high - PSU_IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI 1 - - Master Tri-state Enable for pin 76, active high - PSU_IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI 0 - - Master Tri-state Enable for pin 77, active high - PSU_IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI 0 - - MIO pin Tri-state Enables, 77:64 - (OFFSET, MASK, VALUE) (0XFF18020C, 0x00003FFFU ,0x00000FC0U) - RegMask = (IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_SHIFT - | 0x00000001U << IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_SHIFT - | 0x00000001U << IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_SHIFT - | 0x00000001U << IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_SHIFT - | 0x00000001U << IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_SHIFT - | 0x00000001U << IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_SHIFT - | 0x00000001U << IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_MST_TRI2_OFFSET ,0x00003FFFU ,0x00000FC0U); - /*############################################################################################################################ */ - - /*Register : bank0_ctrl0 @ 0XFF180138

- - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25 1 - - Drive0 control to MIO Bank 0 - control MIO[25:0] - (OFFSET, MASK, VALUE) (0XFF180138, 0x03FFFFFFU ,0x03FFFFFFU) - RegMask = (IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_BANK0_CTRL0_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU); - /*############################################################################################################################ */ - - /*Register : bank0_ctrl1 @ 0XFF18013C

- - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25 1 - - Drive1 control to MIO Bank 0 - control MIO[25:0] - (OFFSET, MASK, VALUE) (0XFF18013C, 0x03FFFFFFU ,0x03FFFFFFU) - RegMask = (IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_BANK0_CTRL1_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU); - /*############################################################################################################################ */ - - /*Register : bank0_ctrl3 @ 0XFF180140

- - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25 0 - - Selects either Schmitt or CMOS input for MIO Bank 0 - control MIO[25:0] - (OFFSET, MASK, VALUE) (0XFF180140, 0x03FFFFFFU ,0x00000000U) - RegMask = (IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_BANK0_CTRL3_OFFSET ,0x03FFFFFFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : bank0_ctrl4 @ 0XFF180144

- - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25 1 - - When mio_bank0_pull_enable is set, this selects pull up or pull down for MIO Bank 0 - control MIO[25:0] - (OFFSET, MASK, VALUE) (0XFF180144, 0x03FFFFFFU ,0x03FFFFFFU) - RegMask = (IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_BANK0_CTRL4_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU); - /*############################################################################################################################ */ - - /*Register : bank0_ctrl5 @ 0XFF180148

- - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25 1 - - When set, this enables mio_bank0_pullupdown to selects pull up or pull down for MIO Bank 0 - control MIO[25:0] - (OFFSET, MASK, VALUE) (0XFF180148, 0x03FFFFFFU ,0x03FFFFFFU) - RegMask = (IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_BANK0_CTRL5_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU); - /*############################################################################################################################ */ - - /*Register : bank0_ctrl6 @ 0XFF18014C

- - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25 0 - - Slew rate control to MIO Bank 0 - control MIO[25:0] - (OFFSET, MASK, VALUE) (0XFF18014C, 0x03FFFFFFU ,0x00000000U) - RegMask = (IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_BANK0_CTRL6_OFFSET ,0x03FFFFFFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : bank1_ctrl0 @ 0XFF180154

- - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25 1 - - Drive0 control to MIO Bank 1 - control MIO[51:26] - (OFFSET, MASK, VALUE) (0XFF180154, 0x03FFFFFFU ,0x03FFFFFFU) - RegMask = (IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_BANK1_CTRL0_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU); - /*############################################################################################################################ */ - - /*Register : bank1_ctrl1 @ 0XFF180158

- - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25 1 - - Drive1 control to MIO Bank 1 - control MIO[51:26] - (OFFSET, MASK, VALUE) (0XFF180158, 0x03FFFFFFU ,0x03FFFFFFU) - RegMask = (IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_BANK1_CTRL1_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU); - /*############################################################################################################################ */ - - /*Register : bank1_ctrl3 @ 0XFF18015C

- - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25 0 - - Selects either Schmitt or CMOS input for MIO Bank 1 - control MIO[51:26] - (OFFSET, MASK, VALUE) (0XFF18015C, 0x03FFFFFFU ,0x00000000U) - RegMask = (IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_BANK1_CTRL3_OFFSET ,0x03FFFFFFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : bank1_ctrl4 @ 0XFF180160

- - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25 1 - - When mio_bank1_pull_enable is set, this selects pull up or pull down for MIO Bank 1 - control MIO[51:26] - (OFFSET, MASK, VALUE) (0XFF180160, 0x03FFFFFFU ,0x03FFFFFFU) - RegMask = (IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_BANK1_CTRL4_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU); - /*############################################################################################################################ */ - - /*Register : bank1_ctrl5 @ 0XFF180164

- - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25 1 - - When set, this enables mio_bank1_pullupdown to selects pull up or pull down for MIO Bank 1 - control MIO[51:26] - (OFFSET, MASK, VALUE) (0XFF180164, 0x03FFFFFFU ,0x03FFFFFFU) - RegMask = (IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_BANK1_CTRL5_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU); - /*############################################################################################################################ */ - - /*Register : bank1_ctrl6 @ 0XFF180168

- - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25 0 - - Slew rate control to MIO Bank 1 - control MIO[51:26] - (OFFSET, MASK, VALUE) (0XFF180168, 0x03FFFFFFU ,0x00000000U) - RegMask = (IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_BANK1_CTRL6_OFFSET ,0x03FFFFFFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : bank2_ctrl0 @ 0XFF180170

- - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25 1 - - Drive0 control to MIO Bank 2 - control MIO[77:52] - (OFFSET, MASK, VALUE) (0XFF180170, 0x03FFFFFFU ,0x03FFFFFFU) - RegMask = (IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_BANK2_CTRL0_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU); - /*############################################################################################################################ */ - - /*Register : bank2_ctrl1 @ 0XFF180174

- - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25 1 - - Drive1 control to MIO Bank 2 - control MIO[77:52] - (OFFSET, MASK, VALUE) (0XFF180174, 0x03FFFFFFU ,0x03FFFFFFU) - RegMask = (IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_BANK2_CTRL1_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU); - /*############################################################################################################################ */ - - /*Register : bank2_ctrl3 @ 0XFF180178

- - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25 0 - - Selects either Schmitt or CMOS input for MIO Bank 2 - control MIO[77:52] - (OFFSET, MASK, VALUE) (0XFF180178, 0x03FFFFFFU ,0x00000000U) - RegMask = (IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_BANK2_CTRL3_OFFSET ,0x03FFFFFFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : bank2_ctrl4 @ 0XFF18017C

- - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25 1 - - When mio_bank2_pull_enable is set, this selects pull up or pull down for MIO Bank 2 - control MIO[77:52] - (OFFSET, MASK, VALUE) (0XFF18017C, 0x03FFFFFFU ,0x03FFFFFFU) - RegMask = (IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_BANK2_CTRL4_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU); - /*############################################################################################################################ */ - - /*Register : bank2_ctrl5 @ 0XFF180180

- - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25 1 - - When set, this enables mio_bank2_pullupdown to selects pull up or pull down for MIO Bank 2 - control MIO[77:52] - (OFFSET, MASK, VALUE) (0XFF180180, 0x03FFFFFFU ,0x03FFFFFFU) - RegMask = (IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_BANK2_CTRL5_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU); - /*############################################################################################################################ */ - - /*Register : bank2_ctrl6 @ 0XFF180184

- - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25 0 - - Slew rate control to MIO Bank 2 - control MIO[77:52] - (OFFSET, MASK, VALUE) (0XFF180184, 0x03FFFFFFU ,0x00000000U) - RegMask = (IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_BANK2_CTRL6_OFFSET ,0x03FFFFFFU ,0x00000000U); - /*############################################################################################################################ */ - - // : LOOPBACK - /*Register : MIO_LOOPBACK @ 0XFF180200

- - I2C Loopback Control. 0 = Connect I2C inputs according to MIO mapping. 1 = Loop I2C 0 outputs to I2C 1 inputs, and I2C 1 outp - ts to I2C 0 inputs. - PSU_IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1 0 - - CAN Loopback Control. 0 = Connect CAN inputs according to MIO mapping. 1 = Loop CAN 0 Tx to CAN 1 Rx, and CAN 1 Tx to CAN 0 R - . - PSU_IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1 0 - - UART Loopback Control. 0 = Connect UART inputs according to MIO mapping. 1 = Loop UART 0 outputs to UART 1 inputs, and UART 1 - outputs to UART 0 inputs. RXD/TXD cross-connected. RTS/CTS cross-connected. DSR, DTR, DCD and RI not used. - PSU_IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1 0 - - SPI Loopback Control. 0 = Connect SPI inputs according to MIO mapping. 1 = Loop SPI 0 outputs to SPI 1 inputs, and SPI 1 outp - ts to SPI 0 inputs. The other SPI core will appear on the LS Slave Select. - PSU_IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1 0 - - Loopback function within MIO - (OFFSET, MASK, VALUE) (0XFF180200, 0x0000000FU ,0x00000000U) - RegMask = (IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_MASK | IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_MASK | IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_MASK | IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_SHIFT - | 0x00000000U << IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_SHIFT - | 0x00000000U << IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_SHIFT - | 0x00000000U << IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_LOOPBACK_OFFSET ,0x0000000FU ,0x00000000U); - /*############################################################################################################################ */ - - - return 1; + return 1; } -unsigned long psu_peripherals_init_data() { - // : RESET BLOCKS - // : TIMESTAMP - /*Register : RST_LPD_IOU2 @ 0XFF5E0238

+unsigned long psu_mio_init_data(void) +{ + /* + * MIO PROGRAMMING + */ + /* + * Register : MIO_PIN_0 @ 0XFF180000 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out- + * (QSPI Clock) + * PSU_IOU_SLCR_MIO_PIN_0_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_0_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[0]- (Test Scan Port) = test_scan, Output, test_scan_out[0 + * ]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_0_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[0]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[0]- (GPIO bank 0) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG + * TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sc + * lk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Out + * put, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_c + * lk- (Trace Port Clock) + * PSU_IOU_SLCR_MIO_PIN_0_L3_SEL 0 + + * Configures MIO Pin 0 peripheral interface mapping. S + * (OFFSET, MASK, VALUE) (0XFF180000, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_0_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_1 @ 0XFF180004 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (Q + * SPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Databus) + * PSU_IOU_SLCR_MIO_PIN_1_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_1_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[1]- (Test Scan Port) = test_scan, Output, test_scan_out[1 + * ]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_1_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[1]- (GPIO bank 0) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG + * TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc3, Ou + * tput, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART + * receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control + * Signal) + * PSU_IOU_SLCR_MIO_PIN_1_L3_SEL 0 + + * Configures MIO Pin 1 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180004, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_1_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_2 @ 0XFF180008 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI + * Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus) + * PSU_IOU_SLCR_MIO_PIN_2_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_2_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[2]- (Test Scan Port) = test_scan, Output, test_scan_out[2 + * ]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_2_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[2]- (GPIO bank 0) 1= can0, Input, can0_phy_ + * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + * , Output, i2c0_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTAG + * TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc2, I + * nput, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver se + * rial input) 7= trace, Output, tracedq[0]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_2_L3_SEL 0 + + * Configures MIO Pin 2 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180008, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_2_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_3 @ 0XFF18000C + + * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI + * Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus) + * PSU_IOU_SLCR_MIO_PIN_3_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_3_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[3]- (Test Scan Port) = test_scan, Output, test_scan_out[3 + * ]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_3_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[3]- (GPIO bank 0) 1= can0, Output, can0_phy + * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + * 0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG + * TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output + * , spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- + * (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial + * output) 7= trace, Output, tracedq[1]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_3_L3_SEL 0 + + * Configures MIO Pin 3 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF18000C, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_3_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_4 @ 0XFF180010 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- ( + * QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Databus) + * PSU_IOU_SLCR_MIO_PIN_4_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_4_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[4]- (Test Scan Port) = test_scan, Output, test_scan_out[4 + * ]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_4_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[4]- (GPIO bank 0) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Wa + * tch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi + * 0, Output, spi0_so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Cloc + * k) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, O + * utput, tracedq[2]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_4_L3_SEL 0 + + * Configures MIO Pin 4 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180010, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_4_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_5 @ 0XFF180014 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out- + * (QSPI Slave Select) + * PSU_IOU_SLCR_MIO_PIN_5_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_5_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[5]- (Test Scan Port) = test_scan, Output, test_scan_out[5 + * ]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_5_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[5]- (GPIO bank 0) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (W + * atch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= + * spi0, Input, spi0_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC + * Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= + * trace, Output, tracedq[3]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_5_L3_SEL 0 + + * Configures MIO Pin 5 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180014, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_5_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_6 @ 0XFF180018 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_clk_for_l + * pbk- (QSPI Clock to be fed-back) + * PSU_IOU_SLCR_MIO_PIN_6_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_6_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[6]- (Test Scan Port) = test_scan, Output, test_scan_out[6 + * ]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_6_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[6]- (GPIO bank 0) 1= can0, Input, can0_phy_ + * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + * , Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Wat + * ch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= s + * pi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TT + * C Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, + * Output, tracedq[4]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_6_L3_SEL 0 + + * Configures MIO Pin 6 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180018, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_6_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_7 @ 0XFF18001C + + * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out_ + * upper- (QSPI Slave Select upper) + * PSU_IOU_SLCR_MIO_PIN_7_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_7_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[7]- (Test Scan Port) = test_scan, Output, test_scan_out[7 + * ]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_7_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[7]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[7]- (GPIO bank 0) 1= can0, Output, can0_phy + * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + * 0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- ( + * Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Ma + * ster Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua + * 0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, t + * racedq[5]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_7_L3_SEL 0 + + * Configures MIO Pin 7 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF18001C, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_7_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_8 @ 0XFF180020 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[0 + * ]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[0]- (QSPI Upper D + * atabus) + * PSU_IOU_SLCR_MIO_PIN_8_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_8_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[8]- (Test Scan Port) = test_scan, Output, test_scan_out[8 + * ]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_8_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[8]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[8]- (GPIO bank 0) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Wa + * tch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Maste + * r Selects) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_ + * txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Tra + * ce Port Databus) + * PSU_IOU_SLCR_MIO_PIN_8_L3_SEL 0 + + * Configures MIO Pin 8 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180020, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_8_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_9 @ 0XFF180024 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[1 + * ]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[1]- (QSPI Upper D + * atabus) + * PSU_IOU_SLCR_MIO_PIN_9_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NA + * ND chip enable) + * PSU_IOU_SLCR_MIO_PIN_9_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[9]- (Test Scan Port) = test_scan, Output, test_scan_out[9 + * ]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_9_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[9]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[9]- (GPIO bank 0) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (W + * atch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master S + * elects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc3, + * Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UA + * RT receiver serial input) 7= trace, Output, tracedq[7]- (Trace Port Data + * bus) + * PSU_IOU_SLCR_MIO_PIN_9_L3_SEL 0 + + * Configures MIO Pin 9 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180024, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_9_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_10 @ 0XFF180028 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[2 + * ]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[2]- (QSPI Upper D + * atabus) + * PSU_IOU_SLCR_MIO_PIN_10_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (N + * AND Ready/Busy) + * PSU_IOU_SLCR_MIO_PIN_10_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[10]- (Test Scan Port) = test_scan, Output, test_scan_out[ + * 10]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_10_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[10]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[10]- (GPIO bank 0) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= sp + * i1, Output, spi1_so- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clo + * ck) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outpu + * t, tracedq[8]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_10_L3_SEL 0 + + * Configures MIO Pin 10 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180028, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_10_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_11 @ 0XFF18002C + + * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[3 + * ]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[3]- (QSPI Upper D + * atabus) + * PSU_IOU_SLCR_MIO_PIN_11_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (N + * AND Ready/Busy) + * PSU_IOU_SLCR_MIO_PIN_11_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[11]- (Test Scan Port) = test_scan, Output, test_scan_out[ + * 11]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_11_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) + * 4= spi1, Input, spi1_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- ( + * TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial ou + * tput) 7= trace, Output, tracedq[9]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_11_L3_SEL 0 + + * Configures MIO Pin 11 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF18002C, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_11_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_12 @ 0XFF180030 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out_ + * upper- (QSPI Upper Clock) + * PSU_IOU_SLCR_MIO_PIN_12_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NA + * ND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe) + * PSU_IOU_SLCR_MIO_PIN_12_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[12]- (Test Scan Port) = test_scan, Output, test_scan_out[ + * 12]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_12_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[12]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[12]- (GPIO bank 0) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJT + * AG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_ + * sclk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, O + * utput, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace + * dq[10]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_12_L3_SEL 0 + + * Configures MIO Pin 12 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180030, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_12_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_13 @ 0XFF180034 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_13_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[0]- (NA + * ND chip enable) + * PSU_IOU_SLCR_MIO_PIN_13_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[13]- (Test Scan Port) = test_scan, Output, + * test_scan_out[13]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_13_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[13]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[13]- (GPIO bank 0) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTA + * G TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, + * Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UAR + * T receiver serial input) 7= trace, Output, tracedq[11]- (Trace Port Data + * bus) + * PSU_IOU_SLCR_MIO_PIN_13_L3_SEL 0 + + * Configures MIO Pin 13 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180034, 0x000000FEU ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_13_OFFSET, 0x000000FEU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_14 @ 0XFF180038 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_14_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_cle- (NAND + * Command Latch Enable) + * PSU_IOU_SLCR_MIO_PIN_14_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[14]- (Test Scan Port) = test_scan, Output, + * test_scan_out[14]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_14_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJT + * AG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, + * Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver + * serial input) 7= trace, Output, tracedq[12]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_14_L3_SEL 2 + + * Configures MIO Pin 14 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180038, 0x000000FEU ,0x00000040U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_14_OFFSET, 0x000000FEU, 0x00000040U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_15 @ 0XFF18003C + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_15_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ale- (NAND + * Address Latch Enable) + * PSU_IOU_SLCR_MIO_PIN_15_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[15]- (Test Scan Port) = test_scan, Output, + * test_scan_out[15]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_15_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[15]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[15]- (GPIO bank 0) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJT + * AG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Outp + * ut, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_ou + * t- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter seria + * l output) 7= trace, Output, tracedq[13]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_15_L3_SEL 2 + + * Configures MIO Pin 15 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF18003C, 0x000000FEU ,0x00000040U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_15_OFFSET, 0x000000FEU, 0x00000040U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_16 @ 0XFF180040 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_16_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[0]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[0]- (NAND Data Bus) + * PSU_IOU_SLCR_MIO_PIN_16_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[16]- (Test Scan Port) = test_scan, Output, + * test_scan_out[16]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_16_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[16]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[16]- (GPIO bank 0) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= s + * pi0, Output, spi0_so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Cl + * ock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, + * Output, tracedq[14]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_16_L3_SEL 2 + + * Configures MIO Pin 16 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180040, 0x000000FEU ,0x00000040U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_16_OFFSET, 0x000000FEU, 0x00000040U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_17 @ 0XFF180044 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_17_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[1]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[1]- (NAND Data Bus) + * PSU_IOU_SLCR_MIO_PIN_17_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[17]- (Test Scan Port) = test_scan, Output, + * test_scan_out[17]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_17_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[17]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[17]- (GPIO bank 0) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4 + * = spi0, Input, spi0_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (T + * TC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) + * 7= trace, Output, tracedq[15]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_17_L3_SEL 2 + + * Configures MIO Pin 17 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180044, 0x000000FEU ,0x00000040U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_17_OFFSET, 0x000000FEU, 0x00000040U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_18 @ 0XFF180048 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_18_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[2]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[2]- (NAND Data Bus) + * PSU_IOU_SLCR_MIO_PIN_18_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[18]- (Test Scan Port) = test_scan, Output, + * test_scan_out[18]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU + * Ext Tamper) + * PSU_IOU_SLCR_MIO_PIN_18_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[18]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[18]- (GPIO bank 0) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= sp + * i1, Output, spi1_so- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clo + * ck) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_18_L3_SEL 6 + + * Configures MIO Pin 18 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180048, 0x000000FEU ,0x000000C0U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_18_OFFSET, 0x000000FEU, 0x000000C0U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_19 @ 0XFF18004C + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_19_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[3]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[3]- (NAND Data Bus) + * PSU_IOU_SLCR_MIO_PIN_19_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[19]- (Test Scan Port) = test_scan, Output, + * test_scan_out[19]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU + * Ext Tamper) + * PSU_IOU_SLCR_MIO_PIN_19_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[19]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[19]- (GPIO bank 0) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI + * Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= + * ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_19_L3_SEL 6 + + * Configures MIO Pin 19 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF18004C, 0x000000FEU ,0x000000C0U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_19_OFFSET, 0x000000FEU, 0x000000C0U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_20 @ 0XFF180050 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_20_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[4]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[4]- (NAND Data Bus) + * PSU_IOU_SLCR_MIO_PIN_20_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[20]- (Test Scan Port) = test_scan, Output, + * test_scan_out[20]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU + * Ext Tamper) + * PSU_IOU_SLCR_MIO_PIN_20_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[20]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[20]- (GPIO bank 0) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Mas + * ter Selects) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua + * 1_txd- (UART transmitter serial output) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_20_L3_SEL 6 + + * Configures MIO Pin 20 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180050, 0x000000FEU ,0x000000C0U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_20_OFFSET, 0x000000FEU, 0x000000C0U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_21 @ 0XFF180054 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_21_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[5]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[5]- (NAND Data Bus) + * PSU_IOU_SLCR_MIO_PIN_21_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Com + * mand Indicator) = sd0, Output, sdio0_cmd_out- (Command Indicator) 2= tes + * t_scan, Input, test_scan_in[21]- (Test Scan Port) = test_scan, Output, t + * est_scan_out[21]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU E + * xt Tamper) + * PSU_IOU_SLCR_MIO_PIN_21_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[21]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[21]- (GPIO bank 0) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master + * Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc + * 1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- ( + * UART receiver serial input) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_21_L3_SEL 6 + + * Configures MIO Pin 21 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180054, 0x000000FEU ,0x000000C0U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_21_OFFSET, 0x000000FEU, 0x000000C0U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_22 @ 0XFF180058 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_22_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_we_b- (NAN + * D Write Enable) + * PSU_IOU_SLCR_MIO_PIN_22_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- + * (SDSDIO clock) 2= test_scan, Input, test_scan_in[22]- (Test Scan Port) = + * test_scan, Output, test_scan_out[22]- (Test Scan Port) 3= csu, Input, c + * su_ext_tamper- (CSU Ext Tamper) + * PSU_IOU_SLCR_MIO_PIN_22_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[22]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[22]- (GPIO bank 0) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= + * spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- ( + * TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not U + * sed + * PSU_IOU_SLCR_MIO_PIN_22_L3_SEL 0 + + * Configures MIO Pin 22 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180058, 0x000000FEU ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_22_OFFSET, 0x000000FEU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_23 @ 0XFF18005C + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_23_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[6]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[6]- (NAND Data Bus) + * PSU_IOU_SLCR_MIO_PIN_23_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- + * (SD card bus power) 2= test_scan, Input, test_scan_in[23]- (Test Scan Po + * rt) = test_scan, Output, test_scan_out[23]- (Test Scan Port) 3= csu, Inp + * ut, csu_ext_tamper- (CSU Ext Tamper) + * PSU_IOU_SLCR_MIO_PIN_23_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[23]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[23]- (GPIO bank 0) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) + * 4= spi1, Input, spi1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- ( + * TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial ou + * tput) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_23_L3_SEL 0 + + * Configures MIO Pin 23 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF18005C, 0x000000FEU ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_23_OFFSET, 0x000000FEU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_24 @ 0XFF180060 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_24_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[7]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[7]- (NAND Data Bus) + * PSU_IOU_SLCR_MIO_PIN_24_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD + * card detect from connector) 2= test_scan, Input, test_scan_in[24]- (Test + * Scan Port) = test_scan, Output, test_scan_out[24]- (Test Scan Port) 3= + * csu, Input, csu_ext_tamper- (CSU Ext Tamper) + * PSU_IOU_SLCR_MIO_PIN_24_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[24]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[24]- (GPIO bank 0) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= Not Used 5= ttc3, Input, ttc3_clk_in- (T + * TC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= N + * ot Used + * PSU_IOU_SLCR_MIO_PIN_24_L3_SEL 1 + + * Configures MIO Pin 24 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180060, 0x000000FEU ,0x00000020U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_24_OFFSET, 0x000000FEU, 0x00000020U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_25 @ 0XFF180064 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_25_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_re_n- (NAN + * D Read Enable) + * PSU_IOU_SLCR_MIO_PIN_25_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD ca + * rd write protect from connector) 2= test_scan, Input, test_scan_in[25]- + * (Test Scan Port) = test_scan, Output, test_scan_out[25]- (Test Scan Port + * ) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper) + * PSU_IOU_SLCR_MIO_PIN_25_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[25]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[25]- (GPIO bank 0) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= Not Used 5= ttc3, Output, ttc3_wave_ou + * t- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial in + * put) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_25_L3_SEL 1 + + * Configures MIO Pin 25 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180064, 0x000000FEU ,0x00000020U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_25_OFFSET, 0x000000FEU, 0x00000020U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_26 @ 0XFF180068 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ + * clk- (TX RGMII clock) + * PSU_IOU_SLCR_MIO_PIN_26_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NA + * ND chip enable) + * PSU_IOU_SLCR_MIO_PIN_26_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[0]- (PMU + * GPI) 2= test_scan, Input, test_scan_in[26]- (Test Scan Port) = test_sca + * n, Output, test_scan_out[26]- (Test Scan Port) 3= csu, Input, csu_ext_ta + * mper- (CSU Ext Tamper) + * PSU_IOU_SLCR_MIO_PIN_26_L2_SEL 0 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[0]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[0]- (GPIO bank 1) 1= can0, Input, can0_phy_ + * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + * , Output, i2c0_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG + * TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_scl + * k_out- (SPI Clock) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Inpu + * t, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- ( + * Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_26_L3_SEL 0 + + * Configures MIO Pin 26 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180068, 0x000000FEU ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_26_OFFSET, 0x000000FEU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_27 @ 0XFF18006C + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd + * [0]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_27_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (N + * AND Ready/Busy) + * PSU_IOU_SLCR_MIO_PIN_27_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[1]- (PMU + * GPI) 2= test_scan, Input, test_scan_in[27]- (Test Scan Port) = test_sca + * n, Output, test_scan_out[27]- (Test Scan Port) 3= dpaux, Input, dp_aux_d + * ata_in- (Dp Aux Data) = dpaux, Output, dp_aux_data_out- (Dp Aux Data) + * PSU_IOU_SLCR_MIO_PIN_27_L2_SEL 3 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[1]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[1]- (GPIO bank 1) 1= can0, Output, can0_phy + * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + * 0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG + * TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc2, O + * utput, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UAR + * T transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port D + * atabus) + * PSU_IOU_SLCR_MIO_PIN_27_L3_SEL 0 + + * Configures MIO Pin 27 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF18006C, 0x000000FEU ,0x00000018U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_27_OFFSET, 0x000000FEU, 0x00000018U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_28 @ 0XFF180070 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd + * [1]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_28_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (N + * AND Ready/Busy) + * PSU_IOU_SLCR_MIO_PIN_28_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[2]- (PMU + * GPI) 2= test_scan, Input, test_scan_in[28]- (Test Scan Port) = test_sca + * n, Output, test_scan_out[28]- (Test Scan Port) 3= dpaux, Input, dp_hot_p + * lug_detect- (Dp Aux Hot Plug) + * PSU_IOU_SLCR_MIO_PIN_28_L2_SEL 3 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[2]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[2]- (GPIO bank 1) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTA + * G TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc1, + * Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitt + * er serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_28_L3_SEL 0 + + * Configures MIO Pin 28 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180070, 0x000000FEU ,0x00000018U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_28_OFFSET, 0x000000FEU, 0x00000018U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_29 @ 0XFF180074 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd + * [2]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_29_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + * PCIE Reset signal) + * PSU_IOU_SLCR_MIO_PIN_29_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[3]- (PMU + * GPI) 2= test_scan, Input, test_scan_in[29]- (Test Scan Port) = test_sca + * n, Output, test_scan_out[29]- (Test Scan Port) 3= dpaux, Input, dp_aux_d + * ata_in- (Dp Aux Data) = dpaux, Output, dp_aux_data_out- (Dp Aux Data) + * PSU_IOU_SLCR_MIO_PIN_29_L2_SEL 3 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[3]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[3]- (GPIO bank 1) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG + * TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, + * spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- + * (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input + * ) 7= trace, Output, tracedq[7]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_29_L3_SEL 0 + + * Configures MIO Pin 29 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180074, 0x000000FEU ,0x00000018U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_29_OFFSET, 0x000000FEU, 0x00000018U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_30 @ 0XFF180078 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd + * [3]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_30_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + * PCIE Reset signal) + * PSU_IOU_SLCR_MIO_PIN_30_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[4]- (PMU + * GPI) 2= test_scan, Input, test_scan_in[30]- (Test Scan Port) = test_sca + * n, Output, test_scan_out[30]- (Test Scan Port) 3= dpaux, Input, dp_hot_p + * lug_detect- (Dp Aux Hot Plug) + * PSU_IOU_SLCR_MIO_PIN_30_L2_SEL 3 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[4]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[4]- (GPIO bank 1) 1= can0, Input, can0_phy_ + * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + * , Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Wat + * ch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0 + * , Output, spi0_so- (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clock + * ) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, + * tracedq[8]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_30_L3_SEL 0 + + * Configures MIO Pin 30 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180078, 0x000000FEU ,0x00000018U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_30_OFFSET, 0x000000FEU, 0x00000018U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_31 @ 0XFF18007C + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ + * ctl- (TX RGMII control) + * PSU_IOU_SLCR_MIO_PIN_31_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + * PCIE Reset signal) + * PSU_IOU_SLCR_MIO_PIN_31_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[5]- (PMU + * GPI) 2= test_scan, Input, test_scan_in[31]- (Test Scan Port) = test_sca + * n, Output, test_scan_out[31]- (Test Scan Port) 3= csu, Input, csu_ext_ta + * mper- (CSU Ext Tamper) + * PSU_IOU_SLCR_MIO_PIN_31_L2_SEL 0 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[5]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[5]- (GPIO bank 1) 1= can0, Output, can0_phy + * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + * 0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- ( + * Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= + * spi0, Input, spi0_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TT + * C Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial outp + * ut) 7= trace, Output, tracedq[9]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_31_L3_SEL 0 + + * Configures MIO Pin 31 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF18007C, 0x000000FEU ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_31_OFFSET, 0x000000FEU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_32 @ 0XFF180080 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_c + * lk- (RX RGMII clock) + * PSU_IOU_SLCR_MIO_PIN_32_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NA + * ND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe) + * PSU_IOU_SLCR_MIO_PIN_32_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[0]- (PM + * U GPI) 2= test_scan, Input, test_scan_in[32]- (Test Scan Port) = test_sc + * an, Output, test_scan_out[32]- (Test Scan Port) 3= csu, Input, csu_ext_t + * amper- (CSU Ext Tamper) + * PSU_IOU_SLCR_MIO_PIN_32_L2_SEL 1 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[6]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[6]- (GPIO bank 1) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Wa + * tch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= + * spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (T + * TC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= t + * race, Output, tracedq[10]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_32_L3_SEL 0 + + * Configures MIO Pin 32 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180080, 0x000000FEU ,0x00000008U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_32_OFFSET, 0x000000FEU, 0x00000008U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_33 @ 0XFF180084 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[ + * 0]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_33_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + * PCIE Reset signal) + * PSU_IOU_SLCR_MIO_PIN_33_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[1]- (PM + * U GPI) 2= test_scan, Input, test_scan_in[33]- (Test Scan Port) = test_sc + * an, Output, test_scan_out[33]- (Test Scan Port) 3= csu, Input, csu_ext_t + * amper- (CSU Ext Tamper) + * PSU_IOU_SLCR_MIO_PIN_33_L2_SEL 1 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[7]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[7]- (GPIO bank 1) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (W + * atch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Mas + * ter Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1 + * , Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq + * [11]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_33_L3_SEL 0 + + * Configures MIO Pin 33 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180084, 0x000000FEU ,0x00000008U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_33_OFFSET, 0x000000FEU, 0x00000008U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_34 @ 0XFF180088 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[ + * 1]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_34_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + * PCIE Reset signal) + * PSU_IOU_SLCR_MIO_PIN_34_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[2]- (PM + * U GPI) 2= test_scan, Input, test_scan_in[34]- (Test Scan Port) = test_sc + * an, Output, test_scan_out[34]- (Test Scan Port) 3= dpaux, Input, dp_aux_ + * data_in- (Dp Aux Data) = dpaux, Output, dp_aux_data_out- (Dp Aux Data) + * PSU_IOU_SLCR_MIO_PIN_34_L2_SEL 1 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[8]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[8]- (GPIO bank 1) 1= can0, Input, can0_phy_ + * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + * , Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Wat + * ch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master + * Selects) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rx + * d- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace Po + * rt Databus) + * PSU_IOU_SLCR_MIO_PIN_34_L3_SEL 0 + + * Configures MIO Pin 34 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180088, 0x000000FEU ,0x00000008U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_34_OFFSET, 0x000000FEU, 0x00000008U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_35 @ 0XFF18008C + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[ + * 2]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_35_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + * PCIE Reset signal) + * PSU_IOU_SLCR_MIO_PIN_35_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[3]- (PM + * U GPI) 2= test_scan, Input, test_scan_in[35]- (Test Scan Port) = test_sc + * an, Output, test_scan_out[35]- (Test Scan Port) 3= dpaux, Input, dp_hot_ + * plug_detect- (Dp Aux Hot Plug) + * PSU_IOU_SLCR_MIO_PIN_35_L2_SEL 1 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[9]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[9]- (GPIO bank 1) 1= can0, Output, can0_phy + * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + * 0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- ( + * Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master + * Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc2 + * , Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- ( + * UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace Po + * rt Databus) + * PSU_IOU_SLCR_MIO_PIN_35_L3_SEL 0 + + * Configures MIO Pin 35 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF18008C, 0x000000FEU ,0x00000008U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_35_OFFSET, 0x000000FEU, 0x00000008U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_36 @ 0XFF180090 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[ + * 3]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_36_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + * PCIE Reset signal) + * PSU_IOU_SLCR_MIO_PIN_36_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[4]- (PM + * U GPI) 2= test_scan, Input, test_scan_in[36]- (Test Scan Port) = test_sc + * an, Output, test_scan_out[36]- (Test Scan Port) 3= dpaux, Input, dp_aux_ + * data_in- (Dp Aux Data) = dpaux, Output, dp_aux_data_out- (Dp Aux Data) + * PSU_IOU_SLCR_MIO_PIN_36_L2_SEL 1 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[10]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[10]- (GPIO bank 1) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= s + * pi1, Output, spi1_so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Cl + * ock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, + * Output, tracedq[14]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_36_L3_SEL 0 + + * Configures MIO Pin 36 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180090, 0x000000FEU ,0x00000008U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_36_OFFSET, 0x000000FEU, 0x00000008U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_37 @ 0XFF180094 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_c + * tl- (RX RGMII control ) + * PSU_IOU_SLCR_MIO_PIN_37_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + * PCIE Reset signal) + * PSU_IOU_SLCR_MIO_PIN_37_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[5]- (PM + * U GPI) 2= test_scan, Input, test_scan_in[37]- (Test Scan Port) = test_sc + * an, Output, test_scan_out[37]- (Test Scan Port) 3= dpaux, Input, dp_hot_ + * plug_detect- (Dp Aux Hot Plug) + * PSU_IOU_SLCR_MIO_PIN_37_L2_SEL 1 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[11]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[11]- (GPIO bank 1) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4 + * = spi1, Input, spi1_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (T + * TC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) + * 7= trace, Output, tracedq[15]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_37_L3_SEL 0 + + * Configures MIO Pin 37 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180094, 0x000000FEU ,0x00000008U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_37_OFFSET, 0x000000FEU, 0x00000008U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_38 @ 0XFF180098 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ + * clk- (TX RGMII clock) + * PSU_IOU_SLCR_MIO_PIN_38_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_38_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- + * (SDSDIO clock) 2= Not Used 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_38_L2_SEL 0 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[12]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[12]- (GPIO bank 1) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTA + * G TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_s + * clk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, In + * put, ua0_rxd- (UART receiver serial input) 7= trace, Output, trace_clk- + * (Trace Port Clock) + * PSU_IOU_SLCR_MIO_PIN_38_L3_SEL 0 + + * Configures MIO Pin 38 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180098, 0x000000FEU ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_38_OFFSET, 0x000000FEU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_39 @ 0XFF18009C + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd + * [0]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_39_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_39_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD + * card detect from connector) 2= sd1, Input, sd1_data_in[4]- (8-bit Data b + * us) = sd1, Output, sdio1_data_out[4]- (8-bit Data bus) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_39_L2_SEL 2 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[13]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[13]- (GPIO bank 1) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJT + * AG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc0, + * Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (U + * ART transmitter serial output) 7= trace, Output, trace_ctl- (Trace Port + * Control Signal) + * PSU_IOU_SLCR_MIO_PIN_39_L3_SEL 0 + + * Configures MIO Pin 39 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF18009C, 0x000000FEU ,0x00000010U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_39_OFFSET, 0x000000FEU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_40 @ 0XFF1800A0 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd + * [1]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_40_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_40_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Com + * mand Indicator) = sd0, Output, sdio0_cmd_out- (Command Indicator) 2= sd1 + * , Input, sd1_data_in[5]- (8-bit Data bus) = sd1, Output, sdio1_data_out[ + * 5]- (8-bit Data bus) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_40_L2_SEL 2 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[14]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[14]- (GPIO bank 1) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJ + * TAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc3 + * , Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmi + * tter serial output) 7= trace, Output, tracedq[0]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_40_L3_SEL 0 + + * Configures MIO Pin 40 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800A0, 0x000000FEU ,0x00000010U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_40_OFFSET, 0x000000FEU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_41 @ 0XFF1800A4 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd + * [2]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_41_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_41_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[6]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[6]- (8-bit Data bus) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_41_L2_SEL 2 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[15]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[15]- (GPIO bank 1) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTA + * G TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Outpu + * t, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out + * - (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial inp + * ut) 7= trace, Output, tracedq[1]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_41_L3_SEL 0 + + * Configures MIO Pin 41 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800A4, 0x000000FEU ,0x00000010U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_41_OFFSET, 0x000000FEU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_42 @ 0XFF1800A8 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd + * [3]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_42_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_42_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[7]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[7]- (8-bit Data bus) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_42_L2_SEL 2 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= sp + * i0, Output, spi0_so- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clo + * ck) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outpu + * t, tracedq[2]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_42_L3_SEL 0 + + * Configures MIO Pin 42 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800A8, 0x000000FEU ,0x00000010U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_42_OFFSET, 0x000000FEU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_43 @ 0XFF1800AC + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ + * ctl- (TX RGMII control) + * PSU_IOU_SLCR_MIO_PIN_43_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_43_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8-bit Data bus) 2= s + * d1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_43_L2_SEL 0 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) + * 4= spi0, Input, spi0_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- ( + * TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial ou + * tput) 7= trace, Output, tracedq[3]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_43_L3_SEL 0 + + * Configures MIO Pin 43 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800AC, 0x000000FEU ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_43_OFFSET, 0x000000FEU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_44 @ 0XFF1800B0 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_c + * lk- (RX RGMII clock) + * PSU_IOU_SLCR_MIO_PIN_44_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_44_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8-bit Data bus) 2= s + * d1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_44_L2_SEL 2 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[18]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[18]- (GPIO bank 1) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4 + * = spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- + * (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= + * Not Used + * PSU_IOU_SLCR_MIO_PIN_44_L3_SEL 0 + + * Configures MIO Pin 44 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800B0, 0x000000FEU ,0x00000010U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_44_OFFSET, 0x000000FEU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_45 @ 0XFF1800B4 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[ + * 0]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_45_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_45_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8-bit Data bus) 2= s + * d1, Input, sdio1_cd_n- (SD card detect from connector) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_45_L2_SEL 2 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[19]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[19]- (GPIO bank 1) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI M + * aster Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= u + * a1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_45_L3_SEL 0 + + * Configures MIO Pin 45 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800B4, 0x000000FEU ,0x00000010U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_45_OFFSET, 0x000000FEU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_46 @ 0XFF1800B8 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[ + * 1]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_46_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_46_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[0]- (8-bit Data bus) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_46_L2_SEL 2 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Mast + * er Selects) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_ + * rxd- (UART receiver serial input) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_46_L3_SEL 0 + + * Configures MIO Pin 46 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800B8, 0x000000FEU ,0x00000010U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_46_OFFSET, 0x000000FEU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_47 @ 0XFF1800BC + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[ + * 2]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_47_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_47_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[1]- (8-bit Data bus) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_47_L2_SEL 2 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Maste + * r Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= tt + * c0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- + * (UART transmitter serial output) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_47_L3_SEL 0 + + * Configures MIO Pin 47 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800BC, 0x000000FEU ,0x00000010U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_47_OFFSET, 0x000000FEU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_48 @ 0XFF1800C0 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[ + * 3]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_48_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_48_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[2]- (8-bit Data bus) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_48_L2_SEL 2 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[22]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[22]- (GPIO bank 1) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= s + * pi1, Output, spi1_so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Cl + * ock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Us + * ed + * PSU_IOU_SLCR_MIO_PIN_48_L3_SEL 0 + + * Configures MIO Pin 48 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800C0, 0x000000FEU ,0x00000010U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_48_OFFSET, 0x000000FEU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_49 @ 0XFF1800C4 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_c + * tl- (RX RGMII control ) + * PSU_IOU_SLCR_MIO_PIN_49_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_49_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- + * (SD card bus power) 2= sd1, Input, sd1_data_in[3]- (8-bit Data bus) = sd + * 1, Output, sdio1_data_out[3]- (8-bit Data bus) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_49_L2_SEL 2 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[23]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[23]- (GPIO bank 1) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4 + * = spi1, Input, spi1_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (T + * TC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) + * 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_49_L3_SEL 0 + + * Configures MIO Pin 49 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800C4, 0x000000FEU ,0x00000010U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_49_OFFSET, 0x000000FEU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_50 @ 0XFF1800C8 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- + * (TSU clock) + * PSU_IOU_SLCR_MIO_PIN_50_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_50_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD ca + * rd write protect from connector) 2= sd1, Input, sd1_cmd_in- (Command Ind + * icator) = sd1, Output, sdio1_cmd_out- (Command Indicator) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_50_L2_SEL 2 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[24]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[24]- (GPIO bank 1) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= + * ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART rece + * iver serial input) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_50_L3_SEL 0 + + * Configures MIO Pin 50 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800C8, 0x000000FEU ,0x00000010U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_50_OFFSET, 0x000000FEU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_51 @ 0XFF1800CC + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- + * (TSU clock) + * PSU_IOU_SLCR_MIO_PIN_51_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_51_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Output, sdi + * o1_clk_out- (SDSDIO clock) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_51_L2_SEL 2 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[25]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[25]- (GPIO bank 1) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= mdio1, Input, gem1_mdio_in- (MDIO Dat + * a) 4= mdio1, Output, gem1_mdio_out- (MDIO Data) 5= ttc2, Output, ttc2_wa + * ve_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter + * serial output) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_51_L3_SEL 0 + + * Configures MIO Pin 51 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800CC, 0x000000FEU ,0x00000010U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_51_OFFSET, 0x000000FEU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_52 @ 0XFF1800D0 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_ + * clk- (TX RGMII clock) + * PSU_IOU_SLCR_MIO_PIN_52_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_clk_i + * n- (ULPI Clock) + * PSU_IOU_SLCR_MIO_PIN_52_L1_SEL 1 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used + * PSU_IOU_SLCR_MIO_PIN_52_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[0]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[0]- (GPIO bank 2) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG + * TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sc + * lk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Out + * put, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_c + * lk- (Trace Port Clock) + * PSU_IOU_SLCR_MIO_PIN_52_L3_SEL 0 + + * Configures MIO Pin 52 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800D0, 0x000000FEU ,0x00000004U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_52_OFFSET, 0x000000FEU, 0x00000004U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_53 @ 0XFF1800D4 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd + * [0]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_53_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_dir- + * (Data bus direction control) + * PSU_IOU_SLCR_MIO_PIN_53_L1_SEL 1 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used + * PSU_IOU_SLCR_MIO_PIN_53_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[1]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[1]- (GPIO bank 2) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG + * TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Ou + * tput, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART + * receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control + * Signal) + * PSU_IOU_SLCR_MIO_PIN_53_L3_SEL 0 + + * Configures MIO Pin 53 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800D4, 0x000000FEU ,0x00000004U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_53_OFFSET, 0x000000FEU, 0x00000004U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_54 @ 0XFF1800D8 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd + * [1]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_54_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[2]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[2]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_54_L1_SEL 1 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used + * PSU_IOU_SLCR_MIO_PIN_54_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[2]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[2]- (GPIO bank 2) 1= can0, Input, can0_phy_ + * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + * , Output, i2c0_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTAG + * TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, I + * nput, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver se + * rial input) 7= trace, Output, tracedq[0]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_54_L3_SEL 0 + + * Configures MIO Pin 54 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800D8, 0x000000FEU ,0x00000004U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_54_OFFSET, 0x000000FEU, 0x00000004U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_55 @ 0XFF1800DC + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd + * [2]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_55_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_nxt- + * (Data flow control signal from the PHY) + * PSU_IOU_SLCR_MIO_PIN_55_L1_SEL 1 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used + * PSU_IOU_SLCR_MIO_PIN_55_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[3]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[3]- (GPIO bank 2) 1= can0, Output, can0_phy + * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + * 0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG + * TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output + * , spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- + * (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial + * output) 7= trace, Output, tracedq[1]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_55_L3_SEL 0 + + * Configures MIO Pin 55 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800DC, 0x000000FEU ,0x00000004U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_55_OFFSET, 0x000000FEU, 0x00000004U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_56 @ 0XFF1800E0 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd + * [3]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_56_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[0]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[0]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_56_L1_SEL 1 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used + * PSU_IOU_SLCR_MIO_PIN_56_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[4]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[4]- (GPIO bank 2) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Wa + * tch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi + * 0, Output, spi0_so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Cloc + * k) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, O + * utput, tracedq[2]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_56_L3_SEL 0 + + * Configures MIO Pin 56 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800E0, 0x000000FEU ,0x00000004U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_56_OFFSET, 0x000000FEU, 0x00000004U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_57 @ 0XFF1800E4 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_ + * ctl- (TX RGMII control) + * PSU_IOU_SLCR_MIO_PIN_57_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[1]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[1]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_57_L1_SEL 1 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used + * PSU_IOU_SLCR_MIO_PIN_57_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[5]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[5]- (GPIO bank 2) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (W + * atch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= + * spi0, Input, spi0_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC + * Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= + * trace, Output, tracedq[3]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_57_L3_SEL 0 + + * Configures MIO Pin 57 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800E4, 0x000000FEU ,0x00000004U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_57_OFFSET, 0x000000FEU, 0x00000004U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_58 @ 0XFF1800E8 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_c + * lk- (RX RGMII clock) + * PSU_IOU_SLCR_MIO_PIN_58_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Output, usb0_ulpi_stp- + * (Asserted to end or interrupt transfers) + * PSU_IOU_SLCR_MIO_PIN_58_L1_SEL 1 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used + * PSU_IOU_SLCR_MIO_PIN_58_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[6]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[6]- (GPIO bank 2) 1= can0, Input, can0_phy_ + * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + * , Output, i2c0_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG + * TCK) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1_scl + * k_out- (SPI Clock) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Inpu + * t, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- ( + * Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_58_L3_SEL 0 + + * Configures MIO Pin 58 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800E8, 0x000000FEU ,0x00000004U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_58_OFFSET, 0x000000FEU, 0x00000004U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_59 @ 0XFF1800EC + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[ + * 0]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_59_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[3]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[3]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_59_L1_SEL 1 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used + * PSU_IOU_SLCR_MIO_PIN_59_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[7]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[7]- (GPIO bank 2) 1= can0, Output, can0_phy + * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + * 0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG + * TDI) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= ttc2, O + * utput, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UAR + * T transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port D + * atabus) + * PSU_IOU_SLCR_MIO_PIN_59_L3_SEL 0 + + * Configures MIO Pin 59 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800EC, 0x000000FEU ,0x00000004U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_59_OFFSET, 0x000000FEU, 0x00000004U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_60 @ 0XFF1800F0 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[ + * 1]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_60_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[4]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[4]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_60_L1_SEL 1 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used + * PSU_IOU_SLCR_MIO_PIN_60_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[8]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[8]- (GPIO bank 2) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTA + * G TDO) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc1, + * Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitt + * er serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_60_L3_SEL 0 + + * Configures MIO Pin 60 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800F0, 0x000000FEU ,0x00000004U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_60_OFFSET, 0x000000FEU, 0x00000004U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_61 @ 0XFF1800F4 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[ + * 2]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_61_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[5]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[5]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_61_L1_SEL 1 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used + * PSU_IOU_SLCR_MIO_PIN_61_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[9]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[9]- (GPIO bank 2) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG + * TMS) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, Output, + * spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- + * (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input + * ) 7= trace, Output, tracedq[7]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_61_L3_SEL 0 + + * Configures MIO Pin 61 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800F4, 0x000000FEU ,0x00000004U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_61_OFFSET, 0x000000FEU, 0x00000004U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_62 @ 0XFF1800F8 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[ + * 3]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_62_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[6]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[6]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_62_L1_SEL 1 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used + * PSU_IOU_SLCR_MIO_PIN_62_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[10]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[10]- (GPIO bank 2) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= sp + * i1, Output, spi1_so- (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clo + * ck) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outpu + * t, tracedq[8]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_62_L3_SEL 0 + + * Configures MIO Pin 62 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800F8, 0x000000FEU ,0x00000004U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_62_OFFSET, 0x000000FEU, 0x00000004U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_63 @ 0XFF1800FC + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_c + * tl- (RX RGMII control ) + * PSU_IOU_SLCR_MIO_PIN_63_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[7]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[7]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_63_L1_SEL 1 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used + * PSU_IOU_SLCR_MIO_PIN_63_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[11]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[11]- (GPIO bank 2) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) + * 4= spi1, Input, spi1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- ( + * TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial ou + * tput) 7= trace, Output, tracedq[9]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_63_L3_SEL 0 + + * Configures MIO Pin 63 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800FC, 0x000000FEU ,0x00000004U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_63_OFFSET, 0x000000FEU, 0x00000004U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_64 @ 0XFF180100 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_ + * clk- (TX RGMII clock) + * PSU_IOU_SLCR_MIO_PIN_64_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_clk_i + * n- (ULPI Clock) + * PSU_IOU_SLCR_MIO_PIN_64_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- + * (SDSDIO clock) 2= Not Used 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_64_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[12]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[12]- (GPIO bank 2) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4 + * = spi0, Output, spi0_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- + * (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= + * trace, Output, tracedq[10]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_64_L3_SEL 0 + + * Configures MIO Pin 64 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180100, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_64_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_65 @ 0XFF180104 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd + * [0]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_65_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_dir- + * (Data bus direction control) + * PSU_IOU_SLCR_MIO_PIN_65_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD + * card detect from connector) 2= Not Used 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_65_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[13]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[13]- (GPIO bank 2) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi0, Output, spi0_n_ss_out[2]- (SPI M + * aster Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= u + * a1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trace + * dq[11]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_65_L3_SEL 0 + + * Configures MIO Pin 65 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180104, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_65_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_66 @ 0XFF180108 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd + * [1]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_66_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[2]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[2]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_66_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Com + * mand Indicator) = sd0, Output, sdio0_cmd_out- (Command Indicator) 2= Not + * Used 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_66_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[14]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[14]- (GPIO bank 2) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Mast + * er Selects) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_ + * rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace + * Port Databus) + * PSU_IOU_SLCR_MIO_PIN_66_L3_SEL 0 + + * Configures MIO Pin 66 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180108, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_66_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_67 @ 0XFF18010C + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd + * [2]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_67_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_nxt- + * (Data flow control signal from the PHY) + * PSU_IOU_SLCR_MIO_PIN_67_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8-bit Data bus) 2= N + * ot Used 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_67_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[15]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[15]- (GPIO bank 2) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi0, Input, spi0_n_ss_in- (SPI Maste + * r Selects) 4= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 5= tt + * c2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- + * (UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace + * Port Databus) + * PSU_IOU_SLCR_MIO_PIN_67_L3_SEL 0 + + * Configures MIO Pin 67 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF18010C, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_67_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_68 @ 0XFF180110 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd + * [3]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_68_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[0]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[0]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_68_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8-bit Data bus) 2= N + * ot Used 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_68_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[16]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[16]- (GPIO bank 2) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= s + * pi0, Output, spi0_so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Cl + * ock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, + * Output, tracedq[14]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_68_L3_SEL 0 + + * Configures MIO Pin 68 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180110, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_68_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_69 @ 0XFF180114 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_ + * ctl- (TX RGMII control) + * PSU_IOU_SLCR_MIO_PIN_69_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[1]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[1]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_69_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8-bit Data bus) 2= s + * d1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_69_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[17]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[17]- (GPIO bank 2) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4 + * = spi0, Input, spi0_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (T + * TC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) + * 7= trace, Output, tracedq[15]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_69_L3_SEL 0 + + * Configures MIO Pin 69 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180114, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_69_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_70 @ 0XFF180118 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_c + * lk- (RX RGMII clock) + * PSU_IOU_SLCR_MIO_PIN_70_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Output, usb1_ulpi_stp- + * (Asserted to end or interrupt transfers) + * PSU_IOU_SLCR_MIO_PIN_70_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8-bit Data bus) 2= s + * d1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_70_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[18]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[18]- (GPIO bank 2) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= + * spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- ( + * TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not U + * sed + * PSU_IOU_SLCR_MIO_PIN_70_L3_SEL 0 + + * Configures MIO Pin 70 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180118, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_70_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_71 @ 0XFF18011C + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[ + * 0]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_71_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[3]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[3]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_71_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[0]- (8-bit Data bus) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_71_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[19]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[19]- (GPIO bank 2) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI + * Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= + * ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_71_L3_SEL 0 + + * Configures MIO Pin 71 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF18011C, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_71_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_72 @ 0XFF180120 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[ + * 1]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_72_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[4]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[4]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_72_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[1]- (8-bit Data bus) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_72_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[20]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[20]- (GPIO bank 2) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Mas + * ter Selects) 5= Not Used 6= ua1, Output, ua1_txd- (UART transmitter seri + * al output) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_72_L3_SEL 0 + + * Configures MIO Pin 72 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180120, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_72_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_73 @ 0XFF180124 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[ + * 2]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_73_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[5]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_73_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[2]- (8-bit Data bus) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_73_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[21]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[21]- (GPIO bank 2) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master + * Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= Not + * Used 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_73_L3_SEL 0 + + * Configures MIO Pin 73 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180124, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_73_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_74 @ 0XFF180128 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[ + * 3]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_74_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[6]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[6]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_74_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[3]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[3]- (8-bit Data bus) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_74_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[22]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[22]- (GPIO bank 2) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= sp + * i1, Output, spi1_so- (MISO signal) 5= Not Used 6= ua0, Input, ua0_rxd- ( + * UART receiver serial input) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_74_L3_SEL 0 + + * Configures MIO Pin 74 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180128, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_74_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_75 @ 0XFF18012C + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_c + * tl- (RX RGMII control ) + * PSU_IOU_SLCR_MIO_PIN_75_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[7]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[7]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_75_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- + * (SD card bus power) 2= sd1, Input, sd1_cmd_in- (Command Indicator) = sd1 + * , Output, sdio1_cmd_out- (Command Indicator) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_75_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[23]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[23]- (GPIO bank 2) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) + * 4= spi1, Input, spi1_si- (MOSI signal) 5= Not Used 6= ua0, Output, ua0_t + * xd- (UART transmitter serial output) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_75_L3_SEL 0 + + * Configures MIO Pin 75 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF18012C, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_75_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_76 @ 0XFF180130 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_76_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_76_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD ca + * rd write protect from connector) 2= sd1, Output, sdio1_clk_out- (SDSDIO + * clock) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_76_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[24]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[24]- (GPIO bank 2) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= mdio0, Output, gem0_mdc- (MDI + * O Clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= mdio2, Output, gem2 + * _mdc- (MDIO Clock) 6= mdio3, Output, gem3_mdc- (MDIO Clock) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_76_L3_SEL 6 + + * Configures MIO Pin 76 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180130, 0x000000FEU ,0x000000C0U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_76_OFFSET, 0x000000FEU, 0x000000C0U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_77 @ 0XFF180134 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_77_L0_SEL 0 - Block level reset - PSU_CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET 0 + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_77_L1_SEL 0 - Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset. - (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00100000U ,0x00000000U) - RegMask = (CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_MASK | 0 ); + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Input, sdio + * 1_cd_n- (SD card detect from connector) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_77_L2_SEL 0 - RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RST_LPD_IOU2_OFFSET ,0x00100000U ,0x00000000U); - /*############################################################################################################################ */ + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[25]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[25]- (GPIO bank 2) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= mdio0, Input, gem0_mdio_in- (M + * DIO Data) 3= mdio0, Output, gem0_mdio_out- (MDIO Data) 4= mdio1, Input, + * gem1_mdio_in- (MDIO Data) 4= mdio1, Output, gem1_mdio_out- (MDIO Data) 5 + * = mdio2, Input, gem2_mdio_in- (MDIO Data) 5= mdio2, Output, gem2_mdio_ou + * t- (MDIO Data) 6= mdio3, Input, gem3_mdio_in- (MDIO Data) 6= mdio3, Outp + * ut, gem3_mdio_out- (MDIO Data) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_77_L3_SEL 6 - // : ENET - /*Register : RST_LPD_IOU0 @ 0XFF5E0230

+ * Configures MIO Pin 77 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180134, 0x000000FEU ,0x000000C0U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_77_OFFSET, 0x000000FEU, 0x000000C0U); +/*##################################################################### */ - GEM 3 reset - PSU_CRL_APB_RST_LPD_IOU0_GEM3_RESET 0 + /* + * Register : MIO_MST_TRI0 @ 0XFF180204 - Software controlled reset for the GEMs - (OFFSET, MASK, VALUE) (0XFF5E0230, 0x00000008U ,0x00000000U) - RegMask = (CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK | 0 ); + * Master Tri-state Enable for pin 0, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI 0 - RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RST_LPD_IOU0_OFFSET ,0x00000008U ,0x00000000U); - /*############################################################################################################################ */ + * Master Tri-state Enable for pin 1, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI 0 - // : QSPI - /*Register : RST_LPD_IOU2 @ 0XFF5E0238

+ * Master Tri-state Enable for pin 2, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI 0 - Block level reset - PSU_CRL_APB_RST_LPD_IOU2_QSPI_RESET 0 + * Master Tri-state Enable for pin 3, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI 0 - Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset. - (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000001U ,0x00000000U) - RegMask = (CRL_APB_RST_LPD_IOU2_QSPI_RESET_MASK | 0 ); + * Master Tri-state Enable for pin 4, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI 0 - RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU2_QSPI_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RST_LPD_IOU2_OFFSET ,0x00000001U ,0x00000000U); - /*############################################################################################################################ */ + * Master Tri-state Enable for pin 5, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI 0 - // : QSPI TAP DELAY - /*Register : IOU_TAPDLY_BYPASS @ 0XFF180390

+ * Master Tri-state Enable for pin 6, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI 0 - 0: Do not by pass the tap delays on the Rx clock signal of LQSPI 1: Bypass the Tap delay on the Rx clock signal of LQSPI - PSU_IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX 1 + * Master Tri-state Enable for pin 7, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI 0 - IOU tap delay bypass for the LQSPI and NAND controllers - (OFFSET, MASK, VALUE) (0XFF180390, 0x00000004U ,0x00000004U) - RegMask = (IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_MASK | 0 ); + * Master Tri-state Enable for pin 8, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI 0 - RegVal = ((0x00000001U << IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_IOU_TAPDLY_BYPASS_OFFSET ,0x00000004U ,0x00000004U); - /*############################################################################################################################ */ + * Master Tri-state Enable for pin 9, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI 0 - // : NAND - // : USB - /*Register : RST_LPD_TOP @ 0XFF5E023C

+ * Master Tri-state Enable for pin 10, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI 0 - USB 0 reset for control registers - PSU_CRL_APB_RST_LPD_TOP_USB0_APB_RESET 0 + * Master Tri-state Enable for pin 11, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI 0 - USB 0 sleep circuit reset - PSU_CRL_APB_RST_LPD_TOP_USB0_HIBERRESET 0 + * Master Tri-state Enable for pin 12, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI 0 - USB 0 reset - PSU_CRL_APB_RST_LPD_TOP_USB0_CORERESET 0 + * Master Tri-state Enable for pin 13, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI 0 - Software control register for the LPD block. - (OFFSET, MASK, VALUE) (0XFF5E023C, 0x00000540U ,0x00000000U) - RegMask = (CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK | CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK | CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK | 0 ); + * Master Tri-state Enable for pin 14, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI 0 - RegVal = ((0x00000000U << CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT - | 0x00000000U << CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT - | 0x00000000U << CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RST_LPD_TOP_OFFSET ,0x00000540U ,0x00000000U); - /*############################################################################################################################ */ + * Master Tri-state Enable for pin 15, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI 0 - // : FPD RESET - /*Register : RST_FPD_TOP @ 0XFD1A0100

+ * Master Tri-state Enable for pin 16, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI 0 - PCIE config reset - PSU_CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET 0 + * Master Tri-state Enable for pin 17, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI 0 - PCIE control block level reset - PSU_CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET 0 + * Master Tri-state Enable for pin 18, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI 1 - PCIE bridge block level reset (AXI interface) - PSU_CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET 0 + * Master Tri-state Enable for pin 19, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI 0 - Display Port block level reset (includes DPDMA) - PSU_CRF_APB_RST_FPD_TOP_DP_RESET 0 + * Master Tri-state Enable for pin 20, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI 0 - FPD WDT reset - PSU_CRF_APB_RST_FPD_TOP_SWDT_RESET 0 + * Master Tri-state Enable for pin 21, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI 1 - GDMA block level reset - PSU_CRF_APB_RST_FPD_TOP_GDMA_RESET 0 + * Master Tri-state Enable for pin 22, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI 0 - Pixel Processor (submodule of GPU) block level reset - PSU_CRF_APB_RST_FPD_TOP_GPU_PP0_RESET 0 + * Master Tri-state Enable for pin 23, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI 0 - Pixel Processor (submodule of GPU) block level reset - PSU_CRF_APB_RST_FPD_TOP_GPU_PP1_RESET 0 + * Master Tri-state Enable for pin 24, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI 0 - GPU block level reset - PSU_CRF_APB_RST_FPD_TOP_GPU_RESET 0 + * Master Tri-state Enable for pin 25, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI 1 - GT block level reset - PSU_CRF_APB_RST_FPD_TOP_GT_RESET 0 + * Master Tri-state Enable for pin 26, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI 0 - Sata block level reset - PSU_CRF_APB_RST_FPD_TOP_SATA_RESET 0 + * Master Tri-state Enable for pin 27, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI 0 - FPD Block level software controlled reset - (OFFSET, MASK, VALUE) (0XFD1A0100, 0x000F807EU ,0x00000000U) - RegMask = (CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK | CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK | CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK | CRF_APB_RST_FPD_TOP_DP_RESET_MASK | CRF_APB_RST_FPD_TOP_SWDT_RESET_MASK | CRF_APB_RST_FPD_TOP_GDMA_RESET_MASK | CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_MASK | CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_MASK | CRF_APB_RST_FPD_TOP_GPU_RESET_MASK | CRF_APB_RST_FPD_TOP_GT_RESET_MASK | CRF_APB_RST_FPD_TOP_SATA_RESET_MASK | 0 ); + * Master Tri-state Enable for pin 28, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI 1 - RegVal = ((0x00000000U << CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT - | 0x00000000U << CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT - | 0x00000000U << CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT - | 0x00000000U << CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT - | 0x00000000U << CRF_APB_RST_FPD_TOP_SWDT_RESET_SHIFT - | 0x00000000U << CRF_APB_RST_FPD_TOP_GDMA_RESET_SHIFT - | 0x00000000U << CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_SHIFT - | 0x00000000U << CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_SHIFT - | 0x00000000U << CRF_APB_RST_FPD_TOP_GPU_RESET_SHIFT - | 0x00000000U << CRF_APB_RST_FPD_TOP_GT_RESET_SHIFT - | 0x00000000U << CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_RST_FPD_TOP_OFFSET ,0x000F807EU ,0x00000000U); - /*############################################################################################################################ */ + * Master Tri-state Enable for pin 29, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI 0 - // : SD - /*Register : RST_LPD_IOU2 @ 0XFF5E0238

+ * Master Tri-state Enable for pin 30, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI 1 - Block level reset - PSU_CRL_APB_RST_LPD_IOU2_SDIO1_RESET 0 + * Master Tri-state Enable for pin 31, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI 0 - Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset. - (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000040U ,0x00000000U) - RegMask = (CRL_APB_RST_LPD_IOU2_SDIO1_RESET_MASK | 0 ); + * MIO pin Tri-state Enables, 31:0 + * (OFFSET, MASK, VALUE) (0XFF180204, 0xFFFFFFFFU ,0x52240000U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_MST_TRI0_OFFSET, + 0xFFFFFFFFU, 0x52240000U); +/*##################################################################### */ - RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU2_SDIO1_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RST_LPD_IOU2_OFFSET ,0x00000040U ,0x00000000U); - /*############################################################################################################################ */ + /* + * Register : MIO_MST_TRI1 @ 0XFF180208 - /*Register : CTRL_REG_SD @ 0XFF180310

+ * Master Tri-state Enable for pin 32, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI 0 - SD or eMMC selection on SDIO1 0: SD enabled 1: eMMC enabled - PSU_IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL 0 + * Master Tri-state Enable for pin 33, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI 0 - SD eMMC selection - (OFFSET, MASK, VALUE) (0XFF180310, 0x00008000U ,0x00000000U) - RegMask = (IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_MASK | 0 ); + * Master Tri-state Enable for pin 34, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI 0 - RegVal = ((0x00000000U << IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_CTRL_REG_SD_OFFSET ,0x00008000U ,0x00000000U); - /*############################################################################################################################ */ + * Master Tri-state Enable for pin 35, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI 0 - /*Register : SD_CONFIG_REG2 @ 0XFF180320

+ * Master Tri-state Enable for pin 36, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI 0 - Should be set based on the final product usage 00 - Removable SCard Slot 01 - Embedded Slot for One Device 10 - Shared Bus Sl - t 11 - Reserved - PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE 0 + * Master Tri-state Enable for pin 37, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI 0 - 1.8V Support 1: 1.8V supported 0: 1.8V not supported support - PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V 0 + * Master Tri-state Enable for pin 38, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI 0 - 3.0V Support 1: 3.0V supported 0: 3.0V not supported support - PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V 0 + * Master Tri-state Enable for pin 39, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI 0 - 3.3V Support 1: 3.3V supported 0: 3.3V not supported support - PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V 1 + * Master Tri-state Enable for pin 40, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI 0 - SD Config Register 2 - (OFFSET, MASK, VALUE) (0XFF180320, 0x33800000U ,0x00800000U) - RegMask = (IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_MASK | IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_MASK | IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_MASK | IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_MASK | 0 ); + * Master Tri-state Enable for pin 41, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI 0 - RegVal = ((0x00000000U << IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_SHIFT - | 0x00000000U << IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_SHIFT - | 0x00000000U << IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_SHIFT - | 0x00000001U << IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_SD_CONFIG_REG2_OFFSET ,0x33800000U ,0x00800000U); - /*############################################################################################################################ */ + * Master Tri-state Enable for pin 42, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI 0 - // : SD1 BASE CLOCK - /*Register : SD_CONFIG_REG1 @ 0XFF18031C

+ * Master Tri-state Enable for pin 43, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI 0 - Base Clock Frequency for SD Clock. This is the frequency of the xin_clk. - PSU_IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK 0xc7 + * Master Tri-state Enable for pin 44, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI 1 - SD Config Register 1 - (OFFSET, MASK, VALUE) (0XFF18031C, 0x7F800000U ,0x63800000U) - RegMask = (IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_MASK | 0 ); + * Master Tri-state Enable for pin 45, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI 1 - RegVal = ((0x000000C7U << IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_SD_CONFIG_REG1_OFFSET ,0x7F800000U ,0x63800000U); - /*############################################################################################################################ */ + * Master Tri-state Enable for pin 46, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI 0 - // : SD1 RETUNER - /*Register : SD_CONFIG_REG3 @ 0XFF180324

+ * Master Tri-state Enable for pin 47, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI 0 - This is the Timer Count for Re-Tuning Timer for Re-Tuning Mode 1 to 3. Setting to 4'b0 disables Re-Tuning Timer. 0h - Get inf - rmation via other source 1h = 1 seconds 2h = 2 seconds 3h = 4 seconds 4h = 8 seconds -- n = 2(n-1) seconds -- Bh = 1024 secon - s Fh - Ch = Reserved - PSU_IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR 0X0 + * Master Tri-state Enable for pin 48, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI 0 - SD Config Register 3 - (OFFSET, MASK, VALUE) (0XFF180324, 0x03C00000U ,0x00000000U) - RegMask = (IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_SD_CONFIG_REG3_OFFSET ,0x03C00000U ,0x00000000U); - /*############################################################################################################################ */ + * Master Tri-state Enable for pin 49, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI 0 - // : CAN - /*Register : RST_LPD_IOU2 @ 0XFF5E0238

+ * Master Tri-state Enable for pin 50, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI 0 - Block level reset - PSU_CRL_APB_RST_LPD_IOU2_CAN1_RESET 0 + * Master Tri-state Enable for pin 51, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI 0 - Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset. - (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000100U ,0x00000000U) - RegMask = (CRL_APB_RST_LPD_IOU2_CAN1_RESET_MASK | 0 ); + * Master Tri-state Enable for pin 52, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI 1 - RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU2_CAN1_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RST_LPD_IOU2_OFFSET ,0x00000100U ,0x00000000U); - /*############################################################################################################################ */ + * Master Tri-state Enable for pin 53, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI 1 - // : I2C - /*Register : RST_LPD_IOU2 @ 0XFF5E0238

+ * Master Tri-state Enable for pin 54, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI 0 - Block level reset - PSU_CRL_APB_RST_LPD_IOU2_I2C0_RESET 0 + * Master Tri-state Enable for pin 55, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI 1 - Block level reset - PSU_CRL_APB_RST_LPD_IOU2_I2C1_RESET 0 + * Master Tri-state Enable for pin 56, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI 0 - Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset. - (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000600U ,0x00000000U) - RegMask = (CRL_APB_RST_LPD_IOU2_I2C0_RESET_MASK | CRL_APB_RST_LPD_IOU2_I2C1_RESET_MASK | 0 ); + * Master Tri-state Enable for pin 57, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI 0 - RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU2_I2C0_RESET_SHIFT - | 0x00000000U << CRL_APB_RST_LPD_IOU2_I2C1_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RST_LPD_IOU2_OFFSET ,0x00000600U ,0x00000000U); - /*############################################################################################################################ */ + * Master Tri-state Enable for pin 58, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI 0 - // : SWDT - /*Register : RST_LPD_IOU2 @ 0XFF5E0238

+ * Master Tri-state Enable for pin 59, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI 0 - Block level reset - PSU_CRL_APB_RST_LPD_IOU2_SWDT_RESET 0 + * Master Tri-state Enable for pin 60, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI 0 - Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset. - (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00008000U ,0x00000000U) - RegMask = (CRL_APB_RST_LPD_IOU2_SWDT_RESET_MASK | 0 ); + * Master Tri-state Enable for pin 61, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI 0 - RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU2_SWDT_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RST_LPD_IOU2_OFFSET ,0x00008000U ,0x00000000U); - /*############################################################################################################################ */ + * Master Tri-state Enable for pin 62, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI 0 - // : SPI - // : TTC - /*Register : RST_LPD_IOU2 @ 0XFF5E0238

+ * Master Tri-state Enable for pin 63, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI 0 - Block level reset - PSU_CRL_APB_RST_LPD_IOU2_TTC0_RESET 0 + * MIO pin Tri-state Enables, 63:32 + * (OFFSET, MASK, VALUE) (0XFF180208, 0xFFFFFFFFU ,0x00B03000U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_MST_TRI1_OFFSET, + 0xFFFFFFFFU, 0x00B03000U); +/*##################################################################### */ - Block level reset - PSU_CRL_APB_RST_LPD_IOU2_TTC1_RESET 0 + /* + * Register : MIO_MST_TRI2 @ 0XFF18020C - Block level reset - PSU_CRL_APB_RST_LPD_IOU2_TTC2_RESET 0 + * Master Tri-state Enable for pin 64, active high + * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI 0 - Block level reset - PSU_CRL_APB_RST_LPD_IOU2_TTC3_RESET 0 + * Master Tri-state Enable for pin 65, active high + * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI 0 - Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset. - (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00007800U ,0x00000000U) - RegMask = (CRL_APB_RST_LPD_IOU2_TTC0_RESET_MASK | CRL_APB_RST_LPD_IOU2_TTC1_RESET_MASK | CRL_APB_RST_LPD_IOU2_TTC2_RESET_MASK | CRL_APB_RST_LPD_IOU2_TTC3_RESET_MASK | 0 ); + * Master Tri-state Enable for pin 66, active high + * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI 0 - RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU2_TTC0_RESET_SHIFT - | 0x00000000U << CRL_APB_RST_LPD_IOU2_TTC1_RESET_SHIFT - | 0x00000000U << CRL_APB_RST_LPD_IOU2_TTC2_RESET_SHIFT - | 0x00000000U << CRL_APB_RST_LPD_IOU2_TTC3_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RST_LPD_IOU2_OFFSET ,0x00007800U ,0x00000000U); - /*############################################################################################################################ */ + * Master Tri-state Enable for pin 67, active high + * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI 0 - // : UART - /*Register : RST_LPD_IOU2 @ 0XFF5E0238

+ * Master Tri-state Enable for pin 68, active high + * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI 0 - Block level reset - PSU_CRL_APB_RST_LPD_IOU2_UART0_RESET 0 + * Master Tri-state Enable for pin 69, active high + * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI 0 - Block level reset - PSU_CRL_APB_RST_LPD_IOU2_UART1_RESET 0 + * Master Tri-state Enable for pin 70, active high + * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI 1 - Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset. - (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000006U ,0x00000000U) - RegMask = (CRL_APB_RST_LPD_IOU2_UART0_RESET_MASK | CRL_APB_RST_LPD_IOU2_UART1_RESET_MASK | 0 ); + * Master Tri-state Enable for pin 71, active high + * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI 1 - RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU2_UART0_RESET_SHIFT - | 0x00000000U << CRL_APB_RST_LPD_IOU2_UART1_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RST_LPD_IOU2_OFFSET ,0x00000006U ,0x00000000U); - /*############################################################################################################################ */ + * Master Tri-state Enable for pin 72, active high + * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI 1 - // : UART BAUD RATE - /*Register : Baud_rate_divider_reg0 @ 0XFF000034

+ * Master Tri-state Enable for pin 73, active high + * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI 1 - Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate - PSU_UART0_BAUD_RATE_DIVIDER_REG0_BDIV 0x5 + * Master Tri-state Enable for pin 74, active high + * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI 1 - Baud Rate Divider Register - (OFFSET, MASK, VALUE) (0XFF000034, 0x000000FFU ,0x00000005U) - RegMask = (UART0_BAUD_RATE_DIVIDER_REG0_BDIV_MASK | 0 ); + * Master Tri-state Enable for pin 75, active high + * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI 1 - RegVal = ((0x00000005U << UART0_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (UART0_BAUD_RATE_DIVIDER_REG0_OFFSET ,0x000000FFU ,0x00000005U); - /*############################################################################################################################ */ + * Master Tri-state Enable for pin 76, active high + * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI 0 - /*Register : Baud_rate_gen_reg0 @ 0XFF000018

+ * Master Tri-state Enable for pin 77, active high + * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI 0 - Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample - PSU_UART0_BAUD_RATE_GEN_REG0_CD 0x8f + * MIO pin Tri-state Enables, 77:64 + * (OFFSET, MASK, VALUE) (0XFF18020C, 0x00003FFFU ,0x00000FC0U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_MST_TRI2_OFFSET, + 0x00003FFFU, 0x00000FC0U); +/*##################################################################### */ - Baud Rate Generator Register. - (OFFSET, MASK, VALUE) (0XFF000018, 0x0000FFFFU ,0x0000008FU) - RegMask = (UART0_BAUD_RATE_GEN_REG0_CD_MASK | 0 ); + /* + * Register : bank0_ctrl0 @ 0XFF180138 - RegVal = ((0x0000008FU << UART0_BAUD_RATE_GEN_REG0_CD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (UART0_BAUD_RATE_GEN_REG0_OFFSET ,0x0000FFFFU ,0x0000008FU); - /*############################################################################################################################ */ + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0 1 - /*Register : Control_reg0 @ 0XFF000000

+ * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1 1 - Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a - high level during 12 bit periods. It can be set regardless of the value of STTBRK. - PSU_UART0_CONTROL_REG0_STPBRK 0x0 + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2 1 - Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the - transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high. - PSU_UART0_CONTROL_REG0_STTBRK 0x0 + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3 1 - Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has co - pleted. - PSU_UART0_CONTROL_REG0_RSTTO 0x0 + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4 1 - Transmit disable: 0: enable transmitter 1: disable transmitter - PSU_UART0_CONTROL_REG0_TXDIS 0x0 + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5 1 - Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0. - PSU_UART0_CONTROL_REG0_TXEN 0x1 + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6 1 - Receive disable: 0: enable 1: disable, regardless of the value of RXEN - PSU_UART0_CONTROL_REG0_RXDIS 0x0 + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7 1 - Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero. - PSU_UART0_CONTROL_REG0_RXEN 0x1 + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8 1 - Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded Thi - bit is self clearing once the reset has completed. - PSU_UART0_CONTROL_REG0_TXRES 0x1 + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9 1 - Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit - is self clearing once the reset has completed. - PSU_UART0_CONTROL_REG0_RXRES 0x1 + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10 1 - UART Control Register - (OFFSET, MASK, VALUE) (0XFF000000, 0x000001FFU ,0x00000017U) - RegMask = (UART0_CONTROL_REG0_STPBRK_MASK | UART0_CONTROL_REG0_STTBRK_MASK | UART0_CONTROL_REG0_RSTTO_MASK | UART0_CONTROL_REG0_TXDIS_MASK | UART0_CONTROL_REG0_TXEN_MASK | UART0_CONTROL_REG0_RXDIS_MASK | UART0_CONTROL_REG0_RXEN_MASK | UART0_CONTROL_REG0_TXRES_MASK | UART0_CONTROL_REG0_RXRES_MASK | 0 ); + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11 1 - RegVal = ((0x00000000U << UART0_CONTROL_REG0_STPBRK_SHIFT - | 0x00000000U << UART0_CONTROL_REG0_STTBRK_SHIFT - | 0x00000000U << UART0_CONTROL_REG0_RSTTO_SHIFT - | 0x00000000U << UART0_CONTROL_REG0_TXDIS_SHIFT - | 0x00000001U << UART0_CONTROL_REG0_TXEN_SHIFT - | 0x00000000U << UART0_CONTROL_REG0_RXDIS_SHIFT - | 0x00000001U << UART0_CONTROL_REG0_RXEN_SHIFT - | 0x00000001U << UART0_CONTROL_REG0_TXRES_SHIFT - | 0x00000001U << UART0_CONTROL_REG0_RXRES_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (UART0_CONTROL_REG0_OFFSET ,0x000001FFU ,0x00000017U); - /*############################################################################################################################ */ + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12 1 - /*Register : mode_reg0 @ 0XFF000004

+ * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13 1 - Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback - PSU_UART0_MODE_REG0_CHMODE 0x0 + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14 1 - Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5 - stop bits 10: 2 stop bits 11: reserved - PSU_UART0_MODE_REG0_NBSTOP 0x0 + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15 1 - Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity - 01: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity - PSU_UART0_MODE_REG0_PAR 0x4 + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16 1 - Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits - PSU_UART0_MODE_REG0_CHRL 0x0 + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17 1 - Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock - source is uart_ref_clk 1: clock source is uart_ref_clk/8 - PSU_UART0_MODE_REG0_CLKS 0x0 + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18 1 - UART Mode Register - (OFFSET, MASK, VALUE) (0XFF000004, 0x000003FFU ,0x00000020U) - RegMask = (UART0_MODE_REG0_CHMODE_MASK | UART0_MODE_REG0_NBSTOP_MASK | UART0_MODE_REG0_PAR_MASK | UART0_MODE_REG0_CHRL_MASK | UART0_MODE_REG0_CLKS_MASK | 0 ); + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19 1 - RegVal = ((0x00000000U << UART0_MODE_REG0_CHMODE_SHIFT - | 0x00000000U << UART0_MODE_REG0_NBSTOP_SHIFT - | 0x00000004U << UART0_MODE_REG0_PAR_SHIFT - | 0x00000000U << UART0_MODE_REG0_CHRL_SHIFT - | 0x00000000U << UART0_MODE_REG0_CLKS_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (UART0_MODE_REG0_OFFSET ,0x000003FFU ,0x00000020U); - /*############################################################################################################################ */ + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20 1 - /*Register : Baud_rate_divider_reg0 @ 0XFF010034

+ * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21 1 - Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate - PSU_UART1_BAUD_RATE_DIVIDER_REG0_BDIV 0x5 + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22 1 - Baud Rate Divider Register - (OFFSET, MASK, VALUE) (0XFF010034, 0x000000FFU ,0x00000005U) - RegMask = (UART1_BAUD_RATE_DIVIDER_REG0_BDIV_MASK | 0 ); - - RegVal = ((0x00000005U << UART1_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (UART1_BAUD_RATE_DIVIDER_REG0_OFFSET ,0x000000FFU ,0x00000005U); - /*############################################################################################################################ */ - - /*Register : Baud_rate_gen_reg0 @ 0XFF010018

+ * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23 1 - Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample - PSU_UART1_BAUD_RATE_GEN_REG0_CD 0x8f - - Baud Rate Generator Register. - (OFFSET, MASK, VALUE) (0XFF010018, 0x0000FFFFU ,0x0000008FU) - RegMask = (UART1_BAUD_RATE_GEN_REG0_CD_MASK | 0 ); - - RegVal = ((0x0000008FU << UART1_BAUD_RATE_GEN_REG0_CD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (UART1_BAUD_RATE_GEN_REG0_OFFSET ,0x0000FFFFU ,0x0000008FU); - /*############################################################################################################################ */ - - /*Register : Control_reg0 @ 0XFF010000

- - Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a - high level during 12 bit periods. It can be set regardless of the value of STTBRK. - PSU_UART1_CONTROL_REG0_STPBRK 0x0 - - Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the - transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high. - PSU_UART1_CONTROL_REG0_STTBRK 0x0 - - Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has co - pleted. - PSU_UART1_CONTROL_REG0_RSTTO 0x0 - - Transmit disable: 0: enable transmitter 1: disable transmitter - PSU_UART1_CONTROL_REG0_TXDIS 0x0 - - Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0. - PSU_UART1_CONTROL_REG0_TXEN 0x1 - - Receive disable: 0: enable 1: disable, regardless of the value of RXEN - PSU_UART1_CONTROL_REG0_RXDIS 0x0 - - Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero. - PSU_UART1_CONTROL_REG0_RXEN 0x1 + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24 1 - Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded Thi - bit is self clearing once the reset has completed. - PSU_UART1_CONTROL_REG0_TXRES 0x1 + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25 1 - Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit - is self clearing once the reset has completed. - PSU_UART1_CONTROL_REG0_RXRES 0x1 + * Drive0 control to MIO Bank 0 - control MIO[25:0] + * (OFFSET, MASK, VALUE) (0XFF180138, 0x03FFFFFFU ,0x03FFFFFFU) + */ + PSU_Mask_Write(IOU_SLCR_BANK0_CTRL0_OFFSET, + 0x03FFFFFFU, 0x03FFFFFFU); +/*##################################################################### */ - UART Control Register - (OFFSET, MASK, VALUE) (0XFF010000, 0x000001FFU ,0x00000017U) - RegMask = (UART1_CONTROL_REG0_STPBRK_MASK | UART1_CONTROL_REG0_STTBRK_MASK | UART1_CONTROL_REG0_RSTTO_MASK | UART1_CONTROL_REG0_TXDIS_MASK | UART1_CONTROL_REG0_TXEN_MASK | UART1_CONTROL_REG0_RXDIS_MASK | UART1_CONTROL_REG0_RXEN_MASK | UART1_CONTROL_REG0_TXRES_MASK | UART1_CONTROL_REG0_RXRES_MASK | 0 ); + /* + * Register : bank0_ctrl1 @ 0XFF18013C - RegVal = ((0x00000000U << UART1_CONTROL_REG0_STPBRK_SHIFT - | 0x00000000U << UART1_CONTROL_REG0_STTBRK_SHIFT - | 0x00000000U << UART1_CONTROL_REG0_RSTTO_SHIFT - | 0x00000000U << UART1_CONTROL_REG0_TXDIS_SHIFT - | 0x00000001U << UART1_CONTROL_REG0_TXEN_SHIFT - | 0x00000000U << UART1_CONTROL_REG0_RXDIS_SHIFT - | 0x00000001U << UART1_CONTROL_REG0_RXEN_SHIFT - | 0x00000001U << UART1_CONTROL_REG0_TXRES_SHIFT - | 0x00000001U << UART1_CONTROL_REG0_RXRES_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (UART1_CONTROL_REG0_OFFSET ,0x000001FFU ,0x00000017U); - /*############################################################################################################################ */ + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0 1 - /*Register : mode_reg0 @ 0XFF010004

+ * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1 1 - Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback - PSU_UART1_MODE_REG0_CHMODE 0x0 + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2 1 - Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5 - stop bits 10: 2 stop bits 11: reserved - PSU_UART1_MODE_REG0_NBSTOP 0x0 - - Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity - 01: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity - PSU_UART1_MODE_REG0_PAR 0x4 - - Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits - PSU_UART1_MODE_REG0_CHRL 0x0 - - Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock - source is uart_ref_clk 1: clock source is uart_ref_clk/8 - PSU_UART1_MODE_REG0_CLKS 0x0 + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3 1 - UART Mode Register - (OFFSET, MASK, VALUE) (0XFF010004, 0x000003FFU ,0x00000020U) - RegMask = (UART1_MODE_REG0_CHMODE_MASK | UART1_MODE_REG0_NBSTOP_MASK | UART1_MODE_REG0_PAR_MASK | UART1_MODE_REG0_CHRL_MASK | UART1_MODE_REG0_CLKS_MASK | 0 ); + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4 1 - RegVal = ((0x00000000U << UART1_MODE_REG0_CHMODE_SHIFT - | 0x00000000U << UART1_MODE_REG0_NBSTOP_SHIFT - | 0x00000004U << UART1_MODE_REG0_PAR_SHIFT - | 0x00000000U << UART1_MODE_REG0_CHRL_SHIFT - | 0x00000000U << UART1_MODE_REG0_CLKS_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (UART1_MODE_REG0_OFFSET ,0x000003FFU ,0x00000020U); - /*############################################################################################################################ */ - - // : GPIO - // : ADMA TZ - /*Register : slcr_adma @ 0XFF4B0024

+ * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5 1 - TrustZone Classification for ADMA - PSU_LPD_SLCR_SECURE_SLCR_ADMA_TZ 0XFF - - RPU TrustZone settings - (OFFSET, MASK, VALUE) (0XFF4B0024, 0x000000FFU ,0x000000FFU) - RegMask = (LPD_SLCR_SECURE_SLCR_ADMA_TZ_MASK | 0 ); - - RegVal = ((0x000000FFU << LPD_SLCR_SECURE_SLCR_ADMA_TZ_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (LPD_SLCR_SECURE_SLCR_ADMA_OFFSET ,0x000000FFU ,0x000000FFU); - /*############################################################################################################################ */ - - // : CSU TAMPERING - // : CSU TAMPER STATUS - /*Register : tamper_status @ 0XFFCA5000

- - CSU regsiter - PSU_CSU_TAMPER_STATUS_TAMPER_0 0 - - External MIO - PSU_CSU_TAMPER_STATUS_TAMPER_1 0 - - JTAG toggle detect - PSU_CSU_TAMPER_STATUS_TAMPER_2 0 - - PL SEU error - PSU_CSU_TAMPER_STATUS_TAMPER_3 0 - - AMS over temperature alarm for LPD - PSU_CSU_TAMPER_STATUS_TAMPER_4 0 - - AMS over temperature alarm for APU - PSU_CSU_TAMPER_STATUS_TAMPER_5 0 - - AMS voltage alarm for VCCPINT_FPD - PSU_CSU_TAMPER_STATUS_TAMPER_6 0 - - AMS voltage alarm for VCCPINT_LPD - PSU_CSU_TAMPER_STATUS_TAMPER_7 0 - - AMS voltage alarm for VCCPAUX - PSU_CSU_TAMPER_STATUS_TAMPER_8 0 - - AMS voltage alarm for DDRPHY - PSU_CSU_TAMPER_STATUS_TAMPER_9 0 - - AMS voltage alarm for PSIO bank 0/1/2 - PSU_CSU_TAMPER_STATUS_TAMPER_10 0 - - AMS voltage alarm for PSIO bank 3 (dedicated pins) - PSU_CSU_TAMPER_STATUS_TAMPER_11 0 - - AMS voltaage alarm for GT - PSU_CSU_TAMPER_STATUS_TAMPER_12 0 - - Tamper Response Status - (OFFSET, MASK, VALUE) (0XFFCA5000, 0x00001FFFU ,0x00000000U) - RegMask = (CSU_TAMPER_STATUS_TAMPER_0_MASK | CSU_TAMPER_STATUS_TAMPER_1_MASK | CSU_TAMPER_STATUS_TAMPER_2_MASK | CSU_TAMPER_STATUS_TAMPER_3_MASK | CSU_TAMPER_STATUS_TAMPER_4_MASK | CSU_TAMPER_STATUS_TAMPER_5_MASK | CSU_TAMPER_STATUS_TAMPER_6_MASK | CSU_TAMPER_STATUS_TAMPER_7_MASK | CSU_TAMPER_STATUS_TAMPER_8_MASK | CSU_TAMPER_STATUS_TAMPER_9_MASK | CSU_TAMPER_STATUS_TAMPER_10_MASK | CSU_TAMPER_STATUS_TAMPER_11_MASK | CSU_TAMPER_STATUS_TAMPER_12_MASK | 0 ); + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6 1 - RegVal = ((0x00000000U << CSU_TAMPER_STATUS_TAMPER_0_SHIFT - | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_1_SHIFT - | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_2_SHIFT - | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_3_SHIFT - | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_4_SHIFT - | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_5_SHIFT - | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_6_SHIFT - | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_7_SHIFT - | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_8_SHIFT - | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_9_SHIFT - | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_10_SHIFT - | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_11_SHIFT - | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_12_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CSU_TAMPER_STATUS_OFFSET ,0x00001FFFU ,0x00000000U); - /*############################################################################################################################ */ + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7 1 - // : CSU TAMPER RESPONSE - // : AFIFM INTERFACE WIDTH - // : CPU QOS DEFAULT - /*Register : ACE_CTRL @ 0XFD5C0060

- - Set ACE outgoing AWQOS value - PSU_APU_ACE_CTRL_AWQOS 0X0 - - Set ACE outgoing ARQOS value - PSU_APU_ACE_CTRL_ARQOS 0X0 + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8 1 - ACE Control Register - (OFFSET, MASK, VALUE) (0XFD5C0060, 0x000F000FU ,0x00000000U) - RegMask = (APU_ACE_CTRL_AWQOS_MASK | APU_ACE_CTRL_ARQOS_MASK | 0 ); + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9 1 - RegVal = ((0x00000000U << APU_ACE_CTRL_AWQOS_SHIFT - | 0x00000000U << APU_ACE_CTRL_ARQOS_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (APU_ACE_CTRL_OFFSET ,0x000F000FU ,0x00000000U); - /*############################################################################################################################ */ + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10 1 - // : ENABLES RTC SWITCH TO BATTERY WHEN VCC_PSAUX IS NOT AVAILABLE - /*Register : CONTROL @ 0XFFA60040

+ * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11 1 - Enables the RTC. By writing a 0 to this bit, RTC will be powered off and the only module that potentially draws current from - he battery will be BBRAM. The value read through this bit does not necessarily reflect whether RTC is enabled or not. It is e - pected that RTC is enabled every time it is being configured. If RTC is not used in the design, FSBL will disable it by writi - g a 0 to this bit. - PSU_RTC_CONTROL_BATTERY_DISABLE 0X1 + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12 1 - This register controls various functionalities within the RTC - (OFFSET, MASK, VALUE) (0XFFA60040, 0x80000000U ,0x80000000U) - RegMask = (RTC_CONTROL_BATTERY_DISABLE_MASK | 0 ); + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13 1 - RegVal = ((0x00000001U << RTC_CONTROL_BATTERY_DISABLE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (RTC_CONTROL_OFFSET ,0x80000000U ,0x80000000U); - /*############################################################################################################################ */ + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14 1 - // : TIMESTAMP COUNTER - /*Register : base_frequency_ID_register @ 0XFF260020

+ * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15 1 - Frequency in number of ticks per second. Valid range from 10 MHz to 100 MHz. - PSU_IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ 0x5f5e100 + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16 1 - Program this register to match the clock frequency of the timestamp generator, in ticks per second. For example, for a 50 MHz - clock, program 0x02FAF080. This register is not accessible to the read-only programming interface. - (OFFSET, MASK, VALUE) (0XFF260020, 0xFFFFFFFFU ,0x05F5E100U) - RegMask = (IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_MASK | 0 ); + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17 1 - RegVal = ((0x05F5E100U << IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_OFFSET ,0xFFFFFFFFU ,0x05F5E100U); - /*############################################################################################################################ */ + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18 1 - /*Register : counter_control_register @ 0XFF260000

- - Enable 0: The counter is disabled and not incrementing. 1: The counter is enabled and is incrementing. - PSU_IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN 0x1 - - Controls the counter increments. This register is not accessible to the read-only programming interface. - (OFFSET, MASK, VALUE) (0XFF260000, 0x00000001U ,0x00000001U) - RegMask = (IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SCNTRS_COUNTER_CONTROL_REGISTER_OFFSET ,0x00000001U ,0x00000001U); - /*############################################################################################################################ */ - - // : TTC SRC SELECT - - return 1; + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25 1 + + * Drive1 control to MIO Bank 0 - control MIO[25:0] + * (OFFSET, MASK, VALUE) (0XFF18013C, 0x03FFFFFFU ,0x03FFFFFFU) + */ + PSU_Mask_Write(IOU_SLCR_BANK0_CTRL1_OFFSET, + 0x03FFFFFFU, 0x03FFFFFFU); +/*##################################################################### */ + + /* + * Register : bank0_ctrl3 @ 0XFF180140 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25 0 + + * Selects either Schmitt or CMOS input for MIO Bank 0 - control MIO[25:0] + * (OFFSET, MASK, VALUE) (0XFF180140, 0x03FFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_BANK0_CTRL3_OFFSET, + 0x03FFFFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : bank0_ctrl4 @ 0XFF180144 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25 1 + + * When mio_bank0_pull_enable is set, this selects pull up or pull down for + * MIO Bank 0 - control MIO[25:0] + * (OFFSET, MASK, VALUE) (0XFF180144, 0x03FFFFFFU ,0x03FFFFFFU) + */ + PSU_Mask_Write(IOU_SLCR_BANK0_CTRL4_OFFSET, + 0x03FFFFFFU, 0x03FFFFFFU); +/*##################################################################### */ + + /* + * Register : bank0_ctrl5 @ 0XFF180148 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25 1 + + * When set, this enables mio_bank0_pullupdown to selects pull up or pull d + * own for MIO Bank 0 - control MIO[25:0] + * (OFFSET, MASK, VALUE) (0XFF180148, 0x03FFFFFFU ,0x03FFFFFFU) + */ + PSU_Mask_Write(IOU_SLCR_BANK0_CTRL5_OFFSET, + 0x03FFFFFFU, 0x03FFFFFFU); +/*##################################################################### */ + + /* + * Register : bank0_ctrl6 @ 0XFF18014C + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25 0 + + * Slew rate control to MIO Bank 0 - control MIO[25:0] + * (OFFSET, MASK, VALUE) (0XFF18014C, 0x03FFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_BANK0_CTRL6_OFFSET, + 0x03FFFFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : bank1_ctrl0 @ 0XFF180154 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25 1 + + * Drive0 control to MIO Bank 1 - control MIO[51:26] + * (OFFSET, MASK, VALUE) (0XFF180154, 0x03FFFFFFU ,0x03FFFFFFU) + */ + PSU_Mask_Write(IOU_SLCR_BANK1_CTRL0_OFFSET, + 0x03FFFFFFU, 0x03FFFFFFU); +/*##################################################################### */ + + /* + * Register : bank1_ctrl1 @ 0XFF180158 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25 1 + + * Drive1 control to MIO Bank 1 - control MIO[51:26] + * (OFFSET, MASK, VALUE) (0XFF180158, 0x03FFFFFFU ,0x03FFFFFFU) + */ + PSU_Mask_Write(IOU_SLCR_BANK1_CTRL1_OFFSET, + 0x03FFFFFFU, 0x03FFFFFFU); +/*##################################################################### */ + + /* + * Register : bank1_ctrl3 @ 0XFF18015C + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25 0 + + * Selects either Schmitt or CMOS input for MIO Bank 1 - control MIO[51:26] + * (OFFSET, MASK, VALUE) (0XFF18015C, 0x03FFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_BANK1_CTRL3_OFFSET, + 0x03FFFFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : bank1_ctrl4 @ 0XFF180160 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25 1 + + * When mio_bank1_pull_enable is set, this selects pull up or pull down for + * MIO Bank 1 - control MIO[51:26] + * (OFFSET, MASK, VALUE) (0XFF180160, 0x03FFFFFFU ,0x03FFFFFFU) + */ + PSU_Mask_Write(IOU_SLCR_BANK1_CTRL4_OFFSET, + 0x03FFFFFFU, 0x03FFFFFFU); +/*##################################################################### */ + + /* + * Register : bank1_ctrl5 @ 0XFF180164 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25 1 + + * When set, this enables mio_bank1_pullupdown to selects pull up or pull d + * own for MIO Bank 1 - control MIO[51:26] + * (OFFSET, MASK, VALUE) (0XFF180164, 0x03FFFFFFU ,0x03FFFFFFU) + */ + PSU_Mask_Write(IOU_SLCR_BANK1_CTRL5_OFFSET, + 0x03FFFFFFU, 0x03FFFFFFU); +/*##################################################################### */ + + /* + * Register : bank1_ctrl6 @ 0XFF180168 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25 0 + + * Slew rate control to MIO Bank 1 - control MIO[51:26] + * (OFFSET, MASK, VALUE) (0XFF180168, 0x03FFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_BANK1_CTRL6_OFFSET, + 0x03FFFFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : bank2_ctrl0 @ 0XFF180170 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25 1 + + * Drive0 control to MIO Bank 2 - control MIO[77:52] + * (OFFSET, MASK, VALUE) (0XFF180170, 0x03FFFFFFU ,0x03FFFFFFU) + */ + PSU_Mask_Write(IOU_SLCR_BANK2_CTRL0_OFFSET, + 0x03FFFFFFU, 0x03FFFFFFU); +/*##################################################################### */ + + /* + * Register : bank2_ctrl1 @ 0XFF180174 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25 1 + + * Drive1 control to MIO Bank 2 - control MIO[77:52] + * (OFFSET, MASK, VALUE) (0XFF180174, 0x03FFFFFFU ,0x03FFFFFFU) + */ + PSU_Mask_Write(IOU_SLCR_BANK2_CTRL1_OFFSET, + 0x03FFFFFFU, 0x03FFFFFFU); +/*##################################################################### */ + + /* + * Register : bank2_ctrl3 @ 0XFF180178 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25 0 + + * Selects either Schmitt or CMOS input for MIO Bank 2 - control MIO[77:52] + * (OFFSET, MASK, VALUE) (0XFF180178, 0x03FFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_BANK2_CTRL3_OFFSET, + 0x03FFFFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : bank2_ctrl4 @ 0XFF18017C + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25 1 + + * When mio_bank2_pull_enable is set, this selects pull up or pull down for + * MIO Bank 2 - control MIO[77:52] + * (OFFSET, MASK, VALUE) (0XFF18017C, 0x03FFFFFFU ,0x03FFFFFFU) + */ + PSU_Mask_Write(IOU_SLCR_BANK2_CTRL4_OFFSET, + 0x03FFFFFFU, 0x03FFFFFFU); +/*##################################################################### */ + + /* + * Register : bank2_ctrl5 @ 0XFF180180 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25 1 + + * When set, this enables mio_bank2_pullupdown to selects pull up or pull d + * own for MIO Bank 2 - control MIO[77:52] + * (OFFSET, MASK, VALUE) (0XFF180180, 0x03FFFFFFU ,0x03FFFFFFU) + */ + PSU_Mask_Write(IOU_SLCR_BANK2_CTRL5_OFFSET, + 0x03FFFFFFU, 0x03FFFFFFU); +/*##################################################################### */ + + /* + * Register : bank2_ctrl6 @ 0XFF180184 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25 0 + + * Slew rate control to MIO Bank 2 - control MIO[77:52] + * (OFFSET, MASK, VALUE) (0XFF180184, 0x03FFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_BANK2_CTRL6_OFFSET, + 0x03FFFFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * LOOPBACK + */ + /* + * Register : MIO_LOOPBACK @ 0XFF180200 + + * I2C Loopback Control. 0 = Connect I2C inputs according to MIO mapping. 1 + * = Loop I2C 0 outputs to I2C 1 inputs, and I2C 1 outputs to I2C 0 inputs + * . + * PSU_IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1 0 + + * CAN Loopback Control. 0 = Connect CAN inputs according to MIO mapping. 1 + * = Loop CAN 0 Tx to CAN 1 Rx, and CAN 1 Tx to CAN 0 Rx. + * PSU_IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1 0 + + * UART Loopback Control. 0 = Connect UART inputs according to MIO mapping. + * 1 = Loop UART 0 outputs to UART 1 inputs, and UART 1 outputs to UART 0 + * inputs. RXD/TXD cross-connected. RTS/CTS cross-connected. DSR, DTR, DCD + * and RI not used. + * PSU_IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1 0 + + * SPI Loopback Control. 0 = Connect SPI inputs according to MIO mapping. 1 + * = Loop SPI 0 outputs to SPI 1 inputs, and SPI 1 outputs to SPI 0 inputs + * . The other SPI core will appear on the LS Slave Select. + * PSU_IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1 0 + + * Loopback function within MIO + * (OFFSET, MASK, VALUE) (0XFF180200, 0x0000000FU ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_LOOPBACK_OFFSET, + 0x0000000FU, 0x00000000U); +/*##################################################################### */ + + + return 1; } -unsigned long psu_post_config_data() { - // : POST_CONFIG +unsigned long psu_peripherals_init_data(void) +{ + /* + * COHERENCY + */ + /* + * FPD RESET + */ + /* + * Register : RST_FPD_TOP @ 0XFD1A0100 - return 1; + * PCIE config reset + * PSU_CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET 0 + + * PCIE control block level reset + * PSU_CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET 0 + + * PCIE bridge block level reset (AXI interface) + * PSU_CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET 0 + + * Display Port block level reset (includes DPDMA) + * PSU_CRF_APB_RST_FPD_TOP_DP_RESET 0 + + * FPD WDT reset + * PSU_CRF_APB_RST_FPD_TOP_SWDT_RESET 0 + + * GDMA block level reset + * PSU_CRF_APB_RST_FPD_TOP_GDMA_RESET 0 + + * Pixel Processor (submodule of GPU) block level reset + * PSU_CRF_APB_RST_FPD_TOP_GPU_PP0_RESET 0 + + * Pixel Processor (submodule of GPU) block level reset + * PSU_CRF_APB_RST_FPD_TOP_GPU_PP1_RESET 0 + + * GPU block level reset + * PSU_CRF_APB_RST_FPD_TOP_GPU_RESET 0 + + * GT block level reset + * PSU_CRF_APB_RST_FPD_TOP_GT_RESET 0 + + * Sata block level reset + * PSU_CRF_APB_RST_FPD_TOP_SATA_RESET 0 + + * FPD Block level software controlled reset + * (OFFSET, MASK, VALUE) (0XFD1A0100, 0x000F807EU ,0x00000000U) + */ + PSU_Mask_Write(CRF_APB_RST_FPD_TOP_OFFSET, 0x000F807EU, 0x00000000U); +/*##################################################################### */ + + /* + * RESET BLOCKS + */ + /* + * TIMESTAMP + */ + /* + * Register : RST_LPD_IOU2 @ 0XFF5E0238 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET 0 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_IOU_CC_RESET 0 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_ADMA_RESET 0 + + * Software control register for the IOU block. Each bit will cause a singl + * erperipheral or part of the peripheral to be reset. + * (OFFSET, MASK, VALUE) (0XFF5E0238, 0x001A0000U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_IOU2_OFFSET, + 0x001A0000U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : RST_LPD_TOP @ 0XFF5E023C + + * Reset entire full power domain. + * PSU_CRL_APB_RST_LPD_TOP_FPD_RESET 0 + + * LPD SWDT + * PSU_CRL_APB_RST_LPD_TOP_LPD_SWDT_RESET 0 + + * Sysmonitor reset + * PSU_CRL_APB_RST_LPD_TOP_SYSMON_RESET 0 + + * Real Time Clock reset + * PSU_CRL_APB_RST_LPD_TOP_RTC_RESET 0 + + * APM reset + * PSU_CRL_APB_RST_LPD_TOP_APM_RESET 0 + + * IPI reset + * PSU_CRL_APB_RST_LPD_TOP_IPI_RESET 0 + + * reset entire RPU power island + * PSU_CRL_APB_RST_LPD_TOP_RPU_PGE_RESET 0 + + * reset ocm + * PSU_CRL_APB_RST_LPD_TOP_OCM_RESET 0 + + * Software control register for the LPD block. + * (OFFSET, MASK, VALUE) (0XFF5E023C, 0x0093C018U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_TOP_OFFSET, 0x0093C018U, 0x00000000U); +/*##################################################################### */ + + /* + * ENET + */ + /* + * Register : RST_LPD_IOU0 @ 0XFF5E0230 + + * GEM 3 reset + * PSU_CRL_APB_RST_LPD_IOU0_GEM3_RESET 0 + + * Software controlled reset for the GEMs + * (OFFSET, MASK, VALUE) (0XFF5E0230, 0x00000008U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_IOU0_OFFSET, + 0x00000008U, 0x00000000U); +/*##################################################################### */ + + /* + * QSPI + */ + /* + * Register : RST_LPD_IOU2 @ 0XFF5E0238 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_QSPI_RESET 0 + + * Software control register for the IOU block. Each bit will cause a singl + * erperipheral or part of the peripheral to be reset. + * (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000001U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_IOU2_OFFSET, + 0x00000001U, 0x00000000U); +/*##################################################################### */ + + /* + * QSPI TAP DELAY + */ + /* + * Register : IOU_TAPDLY_BYPASS @ 0XFF180390 + + * 0: Do not by pass the tap delays on the Rx clock signal of LQSPI 1: Bypa + * ss the Tap delay on the Rx clock signal of LQSPI + * PSU_IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX 1 + + * IOU tap delay bypass for the LQSPI and NAND controllers + * (OFFSET, MASK, VALUE) (0XFF180390, 0x00000004U ,0x00000004U) + */ + PSU_Mask_Write(IOU_SLCR_IOU_TAPDLY_BYPASS_OFFSET, + 0x00000004U, 0x00000004U); +/*##################################################################### */ + + /* + * NAND + */ + /* + * USB + */ + /* + * Register : RST_LPD_TOP @ 0XFF5E023C + + * USB 0 reset for control registers + * PSU_CRL_APB_RST_LPD_TOP_USB0_APB_RESET 0 + + * USB 0 sleep circuit reset + * PSU_CRL_APB_RST_LPD_TOP_USB0_HIBERRESET 0 + + * USB 0 reset + * PSU_CRL_APB_RST_LPD_TOP_USB0_CORERESET 0 + + * Software control register for the LPD block. + * (OFFSET, MASK, VALUE) (0XFF5E023C, 0x00000540U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_TOP_OFFSET, 0x00000540U, 0x00000000U); +/*##################################################################### */ + + /* + * USB0 PIPE POWER PRESENT + */ + /* + * Register : fpd_power_prsnt @ 0XFF9D0080 + + * This bit is used to choose between PIPE power present and 1'b1 + * PSU_USB3_0_FPD_POWER_PRSNT_OPTION 0X1 + + * fpd_power_prsnt + * (OFFSET, MASK, VALUE) (0XFF9D0080, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(USB3_0_FPD_POWER_PRSNT_OFFSET, + 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : fpd_pipe_clk @ 0XFF9D007C + + * This bit is used to choose between PIPE clock coming from SerDes and the + * suspend clk + * PSU_USB3_0_FPD_PIPE_CLK_OPTION 0x0 + + * fpd_pipe_clk + * (OFFSET, MASK, VALUE) (0XFF9D007C, 0x00000001U ,0x00000000U) + */ + PSU_Mask_Write(USB3_0_FPD_PIPE_CLK_OFFSET, 0x00000001U, 0x00000000U); +/*##################################################################### */ + + /* + * SD + */ + /* + * Register : RST_LPD_IOU2 @ 0XFF5E0238 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_SDIO1_RESET 0 + + * Software control register for the IOU block. Each bit will cause a singl + * erperipheral or part of the peripheral to be reset. + * (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000040U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_IOU2_OFFSET, + 0x00000040U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : CTRL_REG_SD @ 0XFF180310 + + * SD or eMMC selection on SDIO1 0: SD enabled 1: eMMC enabled + * PSU_IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL 0 + + * SD eMMC selection + * (OFFSET, MASK, VALUE) (0XFF180310, 0x00008000U ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_CTRL_REG_SD_OFFSET, + 0x00008000U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : SD_CONFIG_REG2 @ 0XFF180320 + + * Should be set based on the final product usage 00 - Removable SCard Slot + * 01 - Embedded Slot for One Device 10 - Shared Bus Slot 11 - Reserved + * PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE 0 + + * 1.8V Support 1: 1.8V supported 0: 1.8V not supported support + * PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V 1 + + * 3.0V Support 1: 3.0V supported 0: 3.0V not supported support + * PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V 0 + + * 3.3V Support 1: 3.3V supported 0: 3.3V not supported support + * PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V 1 + + * SD Config Register 2 + * (OFFSET, MASK, VALUE) (0XFF180320, 0x33800000U ,0x02800000U) + */ + PSU_Mask_Write(IOU_SLCR_SD_CONFIG_REG2_OFFSET, + 0x33800000U, 0x02800000U); +/*##################################################################### */ + + /* + * SD1 BASE CLOCK + */ + /* + * Register : SD_CONFIG_REG1 @ 0XFF18031C + + * Base Clock Frequency for SD Clock. This is the frequency of the xin_clk. + * PSU_IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK 0xc8 + + * Configures the Number of Taps (Phases) of the rxclk_in that is supported + * . + * PSU_IOU_SLCR_SD_CONFIG_REG1_SD1_TUNIGCOUNT 0x28 + + * SD Config Register 1 + * (OFFSET, MASK, VALUE) (0XFF18031C, 0x7FFE0000U ,0x64500000U) + */ + PSU_Mask_Write(IOU_SLCR_SD_CONFIG_REG1_OFFSET, + 0x7FFE0000U, 0x64500000U); +/*##################################################################### */ + + /* + * Register : SD_DLL_CTRL @ 0XFF180358 + + * Reserved. + * PSU_IOU_SLCR_SD_DLL_CTRL_RESERVED 1 + + * SDIO status register + * (OFFSET, MASK, VALUE) (0XFF180358, 0x00000008U ,0x00000008U) + */ + PSU_Mask_Write(IOU_SLCR_SD_DLL_CTRL_OFFSET, + 0x00000008U, 0x00000008U); +/*##################################################################### */ + + /* + * SD1 RETUNER + */ + /* + * Register : SD_CONFIG_REG3 @ 0XFF180324 + + * This is the Timer Count for Re-Tuning Timer for Re-Tuning Mode 1 to 3. S + * etting to 4'b0 disables Re-Tuning Timer. 0h - Get information via other + * source 1h = 1 seconds 2h = 2 seconds 3h = 4 seconds 4h = 8 seconds -- n + * = 2(n-1) seconds -- Bh = 1024 seconds Fh - Ch = Reserved + * PSU_IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR 0X0 + + * SD Config Register 3 + * (OFFSET, MASK, VALUE) (0XFF180324, 0x03C00000U ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_SD_CONFIG_REG3_OFFSET, + 0x03C00000U, 0x00000000U); +/*##################################################################### */ + + /* + * CAN + */ + /* + * Register : RST_LPD_IOU2 @ 0XFF5E0238 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_CAN1_RESET 0 + + * Software control register for the IOU block. Each bit will cause a singl + * erperipheral or part of the peripheral to be reset. + * (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000100U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_IOU2_OFFSET, + 0x00000100U, 0x00000000U); +/*##################################################################### */ + + /* + * I2C + */ + /* + * Register : RST_LPD_IOU2 @ 0XFF5E0238 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_I2C0_RESET 0 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_I2C1_RESET 0 + + * Software control register for the IOU block. Each bit will cause a singl + * erperipheral or part of the peripheral to be reset. + * (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000600U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_IOU2_OFFSET, + 0x00000600U, 0x00000000U); +/*##################################################################### */ + + /* + * SWDT + */ + /* + * Register : RST_LPD_IOU2 @ 0XFF5E0238 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_SWDT_RESET 0 + + * Software control register for the IOU block. Each bit will cause a singl + * erperipheral or part of the peripheral to be reset. + * (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00008000U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_IOU2_OFFSET, + 0x00008000U, 0x00000000U); +/*##################################################################### */ + + /* + * SPI + */ + /* + * TTC + */ + /* + * Register : RST_LPD_IOU2 @ 0XFF5E0238 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_TTC0_RESET 0 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_TTC1_RESET 0 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_TTC2_RESET 0 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_TTC3_RESET 0 + + * Software control register for the IOU block. Each bit will cause a singl + * erperipheral or part of the peripheral to be reset. + * (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00007800U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_IOU2_OFFSET, + 0x00007800U, 0x00000000U); +/*##################################################################### */ + + /* + * UART + */ + /* + * Register : RST_LPD_IOU2 @ 0XFF5E0238 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_UART0_RESET 0 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_UART1_RESET 0 + + * Software control register for the IOU block. Each bit will cause a singl + * erperipheral or part of the peripheral to be reset. + * (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000006U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_IOU2_OFFSET, + 0x00000006U, 0x00000000U); +/*##################################################################### */ + + /* + * UART BAUD RATE + */ + /* + * Register : Baud_rate_divider_reg0 @ 0XFF000034 + + * Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate + * PSU_UART0_BAUD_RATE_DIVIDER_REG0_BDIV 0x5 + + * Baud Rate Divider Register + * (OFFSET, MASK, VALUE) (0XFF000034, 0x000000FFU ,0x00000005U) + */ + PSU_Mask_Write(UART0_BAUD_RATE_DIVIDER_REG0_OFFSET, + 0x000000FFU, 0x00000005U); +/*##################################################################### */ + + /* + * Register : Baud_rate_gen_reg0 @ 0XFF000018 + + * Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor + * bypass (baud_sample = sel_clk) 2 - 65535: baud_sample + * PSU_UART0_BAUD_RATE_GEN_REG0_CD 0x8f + + * Baud Rate Generator Register. + * (OFFSET, MASK, VALUE) (0XFF000018, 0x0000FFFFU ,0x0000008FU) + */ + PSU_Mask_Write(UART0_BAUD_RATE_GEN_REG0_OFFSET, + 0x0000FFFFU, 0x0000008FU); +/*##################################################################### */ + + /* + * Register : Control_reg0 @ 0XFF000000 + + * Stop transmitter break: 0: no affect 1: stop transmission of the break a + * fter a minimum of one character length and transmit a high level during + * 12 bit periods. It can be set regardless of the value of STTBRK. + * PSU_UART0_CONTROL_REG0_STPBRK 0x0 + + * Start transmitter break: 0: no affect 1: start to transmit a break after + * the characters currently present in the FIFO and the transmit shift reg + * ister have been transmitted. It can only be set if STPBRK (Stop transmit + * ter break) is not high. + * PSU_UART0_CONTROL_REG0_STTBRK 0x0 + + * Restart receiver timeout counter: 1: receiver timeout counter is restart + * ed. This bit is self clearing once the restart has completed. + * PSU_UART0_CONTROL_REG0_RSTTO 0x0 + + * Transmit disable: 0: enable transmitter 1: disable transmitter + * PSU_UART0_CONTROL_REG0_TXDIS 0x0 + + * Transmit enable: 0: disable transmitter 1: enable transmitter, provided + * the TXDIS field is set to 0. + * PSU_UART0_CONTROL_REG0_TXEN 0x1 + + * Receive disable: 0: enable 1: disable, regardless of the value of RXEN + * PSU_UART0_CONTROL_REG0_RXDIS 0x0 + + * Receive enable: 0: disable 1: enable When set to one, the receiver logic + * is enabled, provided the RXDIS field is set to zero. + * PSU_UART0_CONTROL_REG0_RXEN 0x1 + + * Software reset for Tx data path: 0: no affect 1: transmitter logic is re + * set and all pending transmitter data is discarded This bit is self clear + * ing once the reset has completed. + * PSU_UART0_CONTROL_REG0_TXRES 0x1 + + * Software reset for Rx data path: 0: no affect 1: receiver logic is reset + * and all pending receiver data is discarded. This bit is self clearing o + * nce the reset has completed. + * PSU_UART0_CONTROL_REG0_RXRES 0x1 + + * UART Control Register + * (OFFSET, MASK, VALUE) (0XFF000000, 0x000001FFU ,0x00000017U) + */ + PSU_Mask_Write(UART0_CONTROL_REG0_OFFSET, 0x000001FFU, 0x00000017U); +/*##################################################################### */ + + /* + * Register : mode_reg0 @ 0XFF000004 + + * Channel mode: Defines the mode of operation of the UART. 00: normal 01: + * automatic echo 10: local loopback 11: remote loopback + * PSU_UART0_MODE_REG0_CHMODE 0x0 + + * Number of stop bits: Defines the number of stop bits to detect on receiv + * e and to generate on transmit. 00: 1 stop bit 01: 1.5 stop bits 10: 2 st + * op bits 11: reserved + * PSU_UART0_MODE_REG0_NBSTOP 0x0 + + * Parity type select: Defines the expected parity to check on receive and + * the parity to generate on transmit. 000: even parity 001: odd parity 010 + * : forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no pari + * ty + * PSU_UART0_MODE_REG0_PAR 0x4 + + * Character length select: Defines the number of bits in each character. 1 + * 1: 6 bits 10: 7 bits 0x: 8 bits + * PSU_UART0_MODE_REG0_CHRL 0x0 + + * Clock source select: This field defines whether a pre-scalar of 8 is app + * lied to the baud rate generator input clock. 0: clock source is uart_ref + * _clk 1: clock source is uart_ref_clk/8 + * PSU_UART0_MODE_REG0_CLKS 0x0 + + * UART Mode Register + * (OFFSET, MASK, VALUE) (0XFF000004, 0x000003FFU ,0x00000020U) + */ + PSU_Mask_Write(UART0_MODE_REG0_OFFSET, 0x000003FFU, 0x00000020U); +/*##################################################################### */ + + /* + * Register : Baud_rate_divider_reg0 @ 0XFF010034 + + * Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate + * PSU_UART1_BAUD_RATE_DIVIDER_REG0_BDIV 0x5 + + * Baud Rate Divider Register + * (OFFSET, MASK, VALUE) (0XFF010034, 0x000000FFU ,0x00000005U) + */ + PSU_Mask_Write(UART1_BAUD_RATE_DIVIDER_REG0_OFFSET, + 0x000000FFU, 0x00000005U); +/*##################################################################### */ + + /* + * Register : Baud_rate_gen_reg0 @ 0XFF010018 + + * Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor + * bypass (baud_sample = sel_clk) 2 - 65535: baud_sample + * PSU_UART1_BAUD_RATE_GEN_REG0_CD 0x8f + + * Baud Rate Generator Register. + * (OFFSET, MASK, VALUE) (0XFF010018, 0x0000FFFFU ,0x0000008FU) + */ + PSU_Mask_Write(UART1_BAUD_RATE_GEN_REG0_OFFSET, + 0x0000FFFFU, 0x0000008FU); +/*##################################################################### */ + + /* + * Register : Control_reg0 @ 0XFF010000 + + * Stop transmitter break: 0: no affect 1: stop transmission of the break a + * fter a minimum of one character length and transmit a high level during + * 12 bit periods. It can be set regardless of the value of STTBRK. + * PSU_UART1_CONTROL_REG0_STPBRK 0x0 + + * Start transmitter break: 0: no affect 1: start to transmit a break after + * the characters currently present in the FIFO and the transmit shift reg + * ister have been transmitted. It can only be set if STPBRK (Stop transmit + * ter break) is not high. + * PSU_UART1_CONTROL_REG0_STTBRK 0x0 + + * Restart receiver timeout counter: 1: receiver timeout counter is restart + * ed. This bit is self clearing once the restart has completed. + * PSU_UART1_CONTROL_REG0_RSTTO 0x0 + + * Transmit disable: 0: enable transmitter 1: disable transmitter + * PSU_UART1_CONTROL_REG0_TXDIS 0x0 + + * Transmit enable: 0: disable transmitter 1: enable transmitter, provided + * the TXDIS field is set to 0. + * PSU_UART1_CONTROL_REG0_TXEN 0x1 + + * Receive disable: 0: enable 1: disable, regardless of the value of RXEN + * PSU_UART1_CONTROL_REG0_RXDIS 0x0 + + * Receive enable: 0: disable 1: enable When set to one, the receiver logic + * is enabled, provided the RXDIS field is set to zero. + * PSU_UART1_CONTROL_REG0_RXEN 0x1 + + * Software reset for Tx data path: 0: no affect 1: transmitter logic is re + * set and all pending transmitter data is discarded This bit is self clear + * ing once the reset has completed. + * PSU_UART1_CONTROL_REG0_TXRES 0x1 + + * Software reset for Rx data path: 0: no affect 1: receiver logic is reset + * and all pending receiver data is discarded. This bit is self clearing o + * nce the reset has completed. + * PSU_UART1_CONTROL_REG0_RXRES 0x1 + + * UART Control Register + * (OFFSET, MASK, VALUE) (0XFF010000, 0x000001FFU ,0x00000017U) + */ + PSU_Mask_Write(UART1_CONTROL_REG0_OFFSET, 0x000001FFU, 0x00000017U); +/*##################################################################### */ + + /* + * Register : mode_reg0 @ 0XFF010004 + + * Channel mode: Defines the mode of operation of the UART. 00: normal 01: + * automatic echo 10: local loopback 11: remote loopback + * PSU_UART1_MODE_REG0_CHMODE 0x0 + + * Number of stop bits: Defines the number of stop bits to detect on receiv + * e and to generate on transmit. 00: 1 stop bit 01: 1.5 stop bits 10: 2 st + * op bits 11: reserved + * PSU_UART1_MODE_REG0_NBSTOP 0x0 + + * Parity type select: Defines the expected parity to check on receive and + * the parity to generate on transmit. 000: even parity 001: odd parity 010 + * : forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no pari + * ty + * PSU_UART1_MODE_REG0_PAR 0x4 + + * Character length select: Defines the number of bits in each character. 1 + * 1: 6 bits 10: 7 bits 0x: 8 bits + * PSU_UART1_MODE_REG0_CHRL 0x0 + + * Clock source select: This field defines whether a pre-scalar of 8 is app + * lied to the baud rate generator input clock. 0: clock source is uart_ref + * _clk 1: clock source is uart_ref_clk/8 + * PSU_UART1_MODE_REG0_CLKS 0x0 + + * UART Mode Register + * (OFFSET, MASK, VALUE) (0XFF010004, 0x000003FFU ,0x00000020U) + */ + PSU_Mask_Write(UART1_MODE_REG0_OFFSET, 0x000003FFU, 0x00000020U); +/*##################################################################### */ + + /* + * GPIO + */ + /* + * Register : RST_LPD_IOU2 @ 0XFF5E0238 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_GPIO_RESET 0 + + * Software control register for the IOU block. Each bit will cause a singl + * erperipheral or part of the peripheral to be reset. + * (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00040000U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_IOU2_OFFSET, + 0x00040000U, 0x00000000U); +/*##################################################################### */ + + /* + * ADMA TZ + */ + /* + * Register : slcr_adma @ 0XFF4B0024 + + * TrustZone Classification for ADMA + * PSU_LPD_SLCR_SECURE_SLCR_ADMA_TZ 0XFF + + * RPU TrustZone settings + * (OFFSET, MASK, VALUE) (0XFF4B0024, 0x000000FFU ,0x000000FFU) + */ + PSU_Mask_Write(LPD_SLCR_SECURE_SLCR_ADMA_OFFSET, + 0x000000FFU, 0x000000FFU); +/*##################################################################### */ + + /* + * CSU TAMPERING + */ + /* + * CSU TAMPER STATUS + */ + /* + * Register : tamper_status @ 0XFFCA5000 + + * CSU regsiter + * PSU_CSU_TAMPER_STATUS_TAMPER_0 0 + + * External MIO + * PSU_CSU_TAMPER_STATUS_TAMPER_1 0 + + * JTAG toggle detect + * PSU_CSU_TAMPER_STATUS_TAMPER_2 0 + + * PL SEU error + * PSU_CSU_TAMPER_STATUS_TAMPER_3 0 + + * AMS over temperature alarm for LPD + * PSU_CSU_TAMPER_STATUS_TAMPER_4 0 + + * AMS over temperature alarm for APU + * PSU_CSU_TAMPER_STATUS_TAMPER_5 0 + + * AMS voltage alarm for VCCPINT_FPD + * PSU_CSU_TAMPER_STATUS_TAMPER_6 0 + + * AMS voltage alarm for VCCPINT_LPD + * PSU_CSU_TAMPER_STATUS_TAMPER_7 0 + + * AMS voltage alarm for VCCPAUX + * PSU_CSU_TAMPER_STATUS_TAMPER_8 0 + + * AMS voltage alarm for DDRPHY + * PSU_CSU_TAMPER_STATUS_TAMPER_9 0 + + * AMS voltage alarm for PSIO bank 0/1/2 + * PSU_CSU_TAMPER_STATUS_TAMPER_10 0 + + * AMS voltage alarm for PSIO bank 3 (dedicated pins) + * PSU_CSU_TAMPER_STATUS_TAMPER_11 0 + + * AMS voltaage alarm for GT + * PSU_CSU_TAMPER_STATUS_TAMPER_12 0 + + * Tamper Response Status + * (OFFSET, MASK, VALUE) (0XFFCA5000, 0x00001FFFU ,0x00000000U) + */ + PSU_Mask_Write(CSU_TAMPER_STATUS_OFFSET, 0x00001FFFU, 0x00000000U); +/*##################################################################### */ + + /* + * CSU TAMPER RESPONSE + */ + /* + * CPU QOS DEFAULT + */ + /* + * Register : ACE_CTRL @ 0XFD5C0060 + + * Set ACE outgoing AWQOS value + * PSU_APU_ACE_CTRL_AWQOS 0X0 + + * Set ACE outgoing ARQOS value + * PSU_APU_ACE_CTRL_ARQOS 0X0 + + * ACE Control Register + * (OFFSET, MASK, VALUE) (0XFD5C0060, 0x000F000FU ,0x00000000U) + */ + PSU_Mask_Write(APU_ACE_CTRL_OFFSET, 0x000F000FU, 0x00000000U); +/*##################################################################### */ + + /* + * ENABLES RTC SWITCH TO BATTERY WHEN VCC_PSAUX IS NOT AVAILABLE + */ + /* + * Register : CONTROL @ 0XFFA60040 + + * Enables the RTC. By writing a 0 to this bit, RTC will be powered off and + * the only module that potentially draws current from the battery will be + * BBRAM. The value read through this bit does not necessarily reflect whe + * ther RTC is enabled or not. It is expected that RTC is enabled every tim + * e it is being configured. If RTC is not used in the design, FSBL will di + * sable it by writing a 0 to this bit. + * PSU_RTC_CONTROL_BATTERY_DISABLE 0X1 + + * This register controls various functionalities within the RTC + * (OFFSET, MASK, VALUE) (0XFFA60040, 0x80000000U ,0x80000000U) + */ + PSU_Mask_Write(RTC_CONTROL_OFFSET, 0x80000000U, 0x80000000U); +/*##################################################################### */ + + /* + * TIMESTAMP COUNTER + */ + /* + * Register : base_frequency_ID_register @ 0XFF260020 + + * Frequency in number of ticks per second. Valid range from 10 MHz to 100 + * MHz. + * PSU_IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ 0x5f5b9f0 + + * Program this register to match the clock frequency of the timestamp gene + * rator, in ticks per second. For example, for a 50 MHz clock, program 0x0 + * 2FAF080. This register is not accessible to the read-only programming in + * terface. + * (OFFSET, MASK, VALUE) (0XFF260020, 0xFFFFFFFFU ,0x05F5B9F0U) + */ + PSU_Mask_Write(IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_OFFSET, + 0xFFFFFFFFU, 0x05F5B9F0U); +/*##################################################################### */ + + /* + * Register : counter_control_register @ 0XFF260000 + + * Enable 0: The counter is disabled and not incrementing. 1: The counter i + * s enabled and is incrementing. + * PSU_IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN 0x1 + + * Controls the counter increments. This register is not accessible to the + * read-only programming interface. + * (OFFSET, MASK, VALUE) (0XFF260000, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(IOU_SCNTRS_COUNTER_CONTROL_REGISTER_OFFSET, + 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * TTC SRC SELECT + */ + /* + * PCIE GPIO RESET + */ + /* + * PCIE RESET + */ + /* + * DIR MODE BANK 0 + */ + /* + * DIR MODE BANK 1 + */ + /* + * Register : DIRM_1 @ 0XFF0A0244 + + * Operation is the same as DIRM_0[DIRECTION_0] + * PSU_GPIO_DIRM_1_DIRECTION_1 0x20 + + * Direction mode (GPIO Bank1, MIO) + * (OFFSET, MASK, VALUE) (0XFF0A0244, 0x03FFFFFFU ,0x00000020U) + */ + PSU_Mask_Write(GPIO_DIRM_1_OFFSET, 0x03FFFFFFU, 0x00000020U); +/*##################################################################### */ + + /* + * DIR MODE BANK 2 + */ + /* + * OUTPUT ENABLE BANK 0 + */ + /* + * OUTPUT ENABLE BANK 1 + */ + /* + * Register : OEN_1 @ 0XFF0A0248 + + * Operation is the same as OEN_0[OP_ENABLE_0] + * PSU_GPIO_OEN_1_OP_ENABLE_1 0x20 + + * Output enable (GPIO Bank1, MIO) + * (OFFSET, MASK, VALUE) (0XFF0A0248, 0x03FFFFFFU ,0x00000020U) + */ + PSU_Mask_Write(GPIO_OEN_1_OFFSET, 0x03FFFFFFU, 0x00000020U); +/*##################################################################### */ + + /* + * OUTPUT ENABLE BANK 2 + */ + /* + * MASK_DATA_0_LSW LOW BANK [15:0] + */ + /* + * MASK_DATA_0_MSW LOW BANK [25:16] + */ + /* + * MASK_DATA_1_LSW LOW BANK [41:26] + */ + /* + * Register : MASK_DATA_1_LSW @ 0XFF0A0008 + + * Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW] + * PSU_GPIO_MASK_DATA_1_LSW_MASK_1_LSW 0xffdf + + * Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW] + * PSU_GPIO_MASK_DATA_1_LSW_DATA_1_LSW 0x20 + + * Maskable Output Data (GPIO Bank1, MIO, Lower 16bits) + * (OFFSET, MASK, VALUE) (0XFF0A0008, 0xFFFFFFFFU ,0xFFDF0020U) + */ + PSU_Mask_Write(GPIO_MASK_DATA_1_LSW_OFFSET, + 0xFFFFFFFFU, 0xFFDF0020U); +/*##################################################################### */ + + /* + * MASK_DATA_1_MSW HIGH BANK [51:42] + */ + /* + * MASK_DATA_1_LSW HIGH BANK [67:52] + */ + /* + * MASK_DATA_1_LSW HIGH BANK [77:68] + */ + /* + * ADD 1 MS DELAY + */ + mask_delay(1); + +/*##################################################################### */ + + /* + * MASK_DATA_0_LSW LOW BANK [15:0] + */ + /* + * MASK_DATA_0_MSW LOW BANK [25:16] + */ + /* + * MASK_DATA_1_LSW LOW BANK [41:26] + */ + /* + * Register : MASK_DATA_1_LSW @ 0XFF0A0008 + + * Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW] + * PSU_GPIO_MASK_DATA_1_LSW_MASK_1_LSW 0xffdf + + * Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW] + * PSU_GPIO_MASK_DATA_1_LSW_DATA_1_LSW 0x0 + + * Maskable Output Data (GPIO Bank1, MIO, Lower 16bits) + * (OFFSET, MASK, VALUE) (0XFF0A0008, 0xFFFFFFFFU ,0xFFDF0000U) + */ + PSU_Mask_Write(GPIO_MASK_DATA_1_LSW_OFFSET, + 0xFFFFFFFFU, 0xFFDF0000U); +/*##################################################################### */ + + /* + * MASK_DATA_1_MSW HIGH BANK [51:42] + */ + /* + * MASK_DATA_1_LSW HIGH BANK [67:52] + */ + /* + * MASK_DATA_1_LSW HIGH BANK [77:68] + */ + /* + * ADD 5 MS DELAY + */ + mask_delay(5); + +/*##################################################################### */ + + + return 1; } -unsigned long psu_peripherals_powerdwn_data() { - // : POWER DOWN REQUEST INTERRUPT ENABLE - // : POWER DOWN TRIGGER +unsigned long psu_post_config_data(void) +{ + /* + * POST_CONFIG + */ - return 1; + return 1; } -unsigned long psu_lpd_xppu_data() { - // : XPPU INTERRUPT ENABLE - /*Register : IEN @ 0XFF980018

+unsigned long psu_peripherals_powerdwn_data(void) +{ + /* + * POWER DOWN REQUEST INTERRUPT ENABLE + */ + /* + * POWER DOWN TRIGGER + */ - See Interuppt Status Register for details - PSU_LPD_XPPU_CFG_IEN_APER_PARITY 0X1 - - See Interuppt Status Register for details - PSU_LPD_XPPU_CFG_IEN_APER_TZ 0X1 - - See Interuppt Status Register for details - PSU_LPD_XPPU_CFG_IEN_APER_PERM 0X1 - - See Interuppt Status Register for details - PSU_LPD_XPPU_CFG_IEN_MID_PARITY 0X1 - - See Interuppt Status Register for details - PSU_LPD_XPPU_CFG_IEN_MID_RO 0X1 - - See Interuppt Status Register for details - PSU_LPD_XPPU_CFG_IEN_MID_MISS 0X1 - - See Interuppt Status Register for details - PSU_LPD_XPPU_CFG_IEN_INV_APB 0X1 - - Interrupt Enable Register - (OFFSET, MASK, VALUE) (0XFF980018, 0x000000EFU ,0x000000EFU) - RegMask = (LPD_XPPU_CFG_IEN_APER_PARITY_MASK | LPD_XPPU_CFG_IEN_APER_TZ_MASK | LPD_XPPU_CFG_IEN_APER_PERM_MASK | LPD_XPPU_CFG_IEN_MID_PARITY_MASK | LPD_XPPU_CFG_IEN_MID_RO_MASK | LPD_XPPU_CFG_IEN_MID_MISS_MASK | LPD_XPPU_CFG_IEN_INV_APB_MASK | 0 ); - - RegVal = ((0x00000001U << LPD_XPPU_CFG_IEN_APER_PARITY_SHIFT - | 0x00000001U << LPD_XPPU_CFG_IEN_APER_TZ_SHIFT - | 0x00000001U << LPD_XPPU_CFG_IEN_APER_PERM_SHIFT - | 0x00000001U << LPD_XPPU_CFG_IEN_MID_PARITY_SHIFT - | 0x00000001U << LPD_XPPU_CFG_IEN_MID_RO_SHIFT - | 0x00000001U << LPD_XPPU_CFG_IEN_MID_MISS_SHIFT - | 0x00000001U << LPD_XPPU_CFG_IEN_INV_APB_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (LPD_XPPU_CFG_IEN_OFFSET ,0x000000EFU ,0x000000EFU); - /*############################################################################################################################ */ - - - return 1; + return 1; } -unsigned long psu_ddr_xmpu0_data() { +unsigned long psu_lpd_xppu_data(void) +{ + /* + * MASTER ID LIST + */ + /* + * APERTURE PERMISIION LIST + */ + /* + * APERTURE NAME: UART0, START ADDRESS: FF000000, END ADDRESS: FF00FFFF + */ + /* + * APERTURE NAME: UART1, START ADDRESS: FF010000, END ADDRESS: FF01FFFF + */ + /* + * APERTURE NAME: I2C0, START ADDRESS: FF020000, END ADDRESS: FF02FFFF + */ + /* + * APERTURE NAME: I2C1, START ADDRESS: FF030000, END ADDRESS: FF03FFFF + */ + /* + * APERTURE NAME: SPI0, START ADDRESS: FF040000, END ADDRESS: FF04FFFF + */ + /* + * APERTURE NAME: SPI1, START ADDRESS: FF050000, END ADDRESS: FF05FFFF + */ + /* + * APERTURE NAME: CAN0, START ADDRESS: FF060000, END ADDRESS: FF06FFFF + */ + /* + * APERTURE NAME: CAN1, START ADDRESS: FF070000, END ADDRESS: FF07FFFF + */ + /* + * APERTURE NAME: RPU_UNUSED_12, START ADDRESS: FF080000, END ADDRESS: FF09 + * FFFF + */ + /* + * APERTURE NAME: RPU_UNUSED_12, START ADDRESS: FF080000, END ADDRESS: FF09 + * FFFF + */ + /* + * APERTURE NAME: GPIO, START ADDRESS: FF0A0000, END ADDRESS: FF0AFFFF + */ + /* + * APERTURE NAME: GEM0, START ADDRESS: FF0B0000, END ADDRESS: FF0BFFFF + */ + /* + * APERTURE NAME: GEM1, START ADDRESS: FF0C0000, END ADDRESS: FF0CFFFF + */ + /* + * APERTURE NAME: GEM2, START ADDRESS: FF0D0000, END ADDRESS: FF0DFFFF + */ + /* + * APERTURE NAME: GEM3, START ADDRESS: FF0E0000, END ADDRESS: FF0EFFFF + */ + /* + * APERTURE NAME: QSPI, START ADDRESS: FF0F0000, END ADDRESS: FF0FFFFF + */ + /* + * APERTURE NAME: NAND, START ADDRESS: FF100000, END ADDRESS: FF10FFFF + */ + /* + * APERTURE NAME: TTC0, START ADDRESS: FF110000, END ADDRESS: FF11FFFF + */ + /* + * APERTURE NAME: TTC1, START ADDRESS: FF120000, END ADDRESS: FF12FFFF + */ + /* + * APERTURE NAME: TTC2, START ADDRESS: FF130000, END ADDRESS: FF13FFFF + */ + /* + * APERTURE NAME: TTC3, START ADDRESS: FF140000, END ADDRESS: FF14FFFF + */ + /* + * APERTURE NAME: SWDT, START ADDRESS: FF150000, END ADDRESS: FF15FFFF + */ + /* + * APERTURE NAME: SD0, START ADDRESS: FF160000, END ADDRESS: FF16FFFF + */ + /* + * APERTURE NAME: SD1, START ADDRESS: FF170000, END ADDRESS: FF17FFFF + */ + /* + * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + */ + /* + * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + */ + /* + * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + */ + /* + * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + */ + /* + * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + */ + /* + * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + */ + /* + * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + */ + /* + * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + */ + /* + * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + */ + /* + * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + */ + /* + * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + */ + /* + * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + */ + /* + * APERTURE NAME: IOU_SECURE_SLCR, START ADDRESS: FF240000, END ADDRESS: FF + * 24FFFF + */ + /* + * APERTURE NAME: IOU_SCNTR, START ADDRESS: FF250000, END ADDRESS: FF25FFFF + */ + /* + * APERTURE NAME: IOU_SCNTRS, START ADDRESS: FF260000, END ADDRESS: FF26FFF + * F + */ + /* + * APERTURE NAME: RPU_UNUSED_11, START ADDRESS: FF270000, END ADDRESS: FF2A + * FFFF + */ + /* + * APERTURE NAME: RPU_UNUSED_11, START ADDRESS: FF270000, END ADDRESS: FF2A + * FFFF + */ + /* + * APERTURE NAME: RPU_UNUSED_11, START ADDRESS: FF270000, END ADDRESS: FF2A + * FFFF + */ + /* + * APERTURE NAME: RPU_UNUSED_11, START ADDRESS: FF270000, END ADDRESS: FF2A + * FFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_14, START ADDRESS: FF2B0000, END ADDRESS: FF2F + * FFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_14, START ADDRESS: FF2B0000, END ADDRESS: FF2F + * FFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_14, START ADDRESS: FF2B0000, END ADDRESS: FF2F + * FFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_14, START ADDRESS: FF2B0000, END ADDRESS: FF2F + * FFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_14, START ADDRESS: FF2B0000, END ADDRESS: FF2F + * FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF + */ + /* + * APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF + */ + /* + * APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF + */ + /* + * APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF + */ + /* + * APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF + */ + /* + * APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF + */ + /* + * APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF + */ + /* + * APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_1, START ADDRESS: FF400000, END ADDRESS: FF40F + * FFF + */ + /* + * APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + */ + /* + * APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + */ + /* + * APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + */ + /* + * APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + */ + /* + * APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + */ + /* + * APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + */ + /* + * APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + */ + /* + * APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + */ + /* + * APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + */ + /* + * APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + */ + /* + * APERTURE NAME: LPD_SLCR_SECURE, START ADDRESS: FF4B0000, END ADDRESS: FF + * 4DFFFF + */ + /* + * APERTURE NAME: LPD_SLCR_SECURE, START ADDRESS: FF4B0000, END ADDRESS: FF + * 4DFFFF + */ + /* + * APERTURE NAME: LPD_SLCR_SECURE, START ADDRESS: FF4B0000, END ADDRESS: FF + * 4DFFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: OCM_SLCR, START ADDRESS: FF960000, END ADDRESS: FF96FFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_4, START ADDRESS: FF970000, END ADDRESS: FF97F + * FFF + */ + /* + * APERTURE NAME: LPD_XPPU, START ADDRESS: FF980000, END ADDRESS: FF99FFFF + */ + /* + * APERTURE NAME: RPU, START ADDRESS: FF9A0000, END ADDRESS: FF9AFFFF + */ + /* + * APERTURE NAME: AFIFM6, START ADDRESS: FF9B0000, END ADDRESS: FF9BFFFF + */ + /* + * APERTURE NAME: LPD_XPPU_SINK, START ADDRESS: FF9C0000, END ADDRESS: FF9C + * FFFF + */ + /* + * APERTURE NAME: USB3_0, START ADDRESS: FF9D0000, END ADDRESS: FF9DFFFF + */ + /* + * APERTURE NAME: USB3_1, START ADDRESS: FF9E0000, END ADDRESS: FF9EFFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_5, START ADDRESS: FF9F0000, END ADDRESS: FF9FF + * FFF + */ + /* + * APERTURE NAME: APM0, START ADDRESS: FFA00000, END ADDRESS: FFA0FFFF + */ + /* + * APERTURE NAME: APM1, START ADDRESS: FFA10000, END ADDRESS: FFA1FFFF + */ + /* + * APERTURE NAME: APM_INTC_IOU, START ADDRESS: FFA20000, END ADDRESS: FFA2F + * FFF + */ + /* + * APERTURE NAME: APM_FPD_LPD, START ADDRESS: FFA30000, END ADDRESS: FFA3FF + * FF + */ + /* + * APERTURE NAME: LPD_UNUSED_6, START ADDRESS: FFA40000, END ADDRESS: FFA4F + * FFF + */ + /* + * APERTURE NAME: AMS, START ADDRESS: FFA50000, END ADDRESS: FFA5FFFF + */ + /* + * APERTURE NAME: RTC, START ADDRESS: FFA60000, END ADDRESS: FFA6FFFF + */ + /* + * APERTURE NAME: OCM_XMPU_CFG, START ADDRESS: FFA70000, END ADDRESS: FFA7F + * FFF + */ + /* + * APERTURE NAME: ADMA_0, START ADDRESS: FFA80000, END ADDRESS: FFA8FFFF + */ + /* + * APERTURE NAME: ADMA_1, START ADDRESS: FFA90000, END ADDRESS: FFA9FFFF + */ + /* + * APERTURE NAME: ADMA_2, START ADDRESS: FFAA0000, END ADDRESS: FFAAFFFF + */ + /* + * APERTURE NAME: ADMA_3, START ADDRESS: FFAB0000, END ADDRESS: FFABFFFF + */ + /* + * APERTURE NAME: ADMA_4, START ADDRESS: FFAC0000, END ADDRESS: FFACFFFF + */ + /* + * APERTURE NAME: ADMA_5, START ADDRESS: FFAD0000, END ADDRESS: FFADFFFF + */ + /* + * APERTURE NAME: ADMA_6, START ADDRESS: FFAE0000, END ADDRESS: FFAEFFFF + */ + /* + * APERTURE NAME: ADMA_7, START ADDRESS: FFAF0000, END ADDRESS: FFAFFFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: CSU_ROM, START ADDRESS: FFC00000, END ADDRESS: FFC1FFFF + */ + /* + * APERTURE NAME: CSU_ROM, START ADDRESS: FFC00000, END ADDRESS: FFC1FFFF + */ + /* + * APERTURE NAME: CSU_LOCAL, START ADDRESS: FFC20000, END ADDRESS: FFC2FFFF + */ + /* + * APERTURE NAME: PUF, START ADDRESS: FFC30000, END ADDRESS: FFC3FFFF + */ + /* + * APERTURE NAME: CSU_RAM, START ADDRESS: FFC40000, END ADDRESS: FFC5FFFF + */ + /* + * APERTURE NAME: CSU_RAM, START ADDRESS: FFC40000, END ADDRESS: FFC5FFFF + */ + /* + * APERTURE NAME: CSU_IOMODULE, START ADDRESS: FFC60000, END ADDRESS: FFC7F + * FFF + */ + /* + * APERTURE NAME: CSU_IOMODULE, START ADDRESS: FFC60000, END ADDRESS: FFC7F + * FFF + */ + /* + * APERTURE NAME: CSUDMA, START ADDRESS: FFC80000, END ADDRESS: FFC9FFFF + */ + /* + * APERTURE NAME: CSUDMA, START ADDRESS: FFC80000, END ADDRESS: FFC9FFFF + */ + /* + * APERTURE NAME: CSU, START ADDRESS: FFCA0000, END ADDRESS: FFCAFFFF + */ + /* + * APERTURE NAME: CSU_WDT, START ADDRESS: FFCB0000, END ADDRESS: FFCBFFFF + */ + /* + * APERTURE NAME: EFUSE, START ADDRESS: FFCC0000, END ADDRESS: FFCCFFFF + */ + /* + * APERTURE NAME: BBRAM, START ADDRESS: FFCD0000, END ADDRESS: FFCDFFFF + */ + /* + * APERTURE NAME: RSA_CORE, START ADDRESS: FFCE0000, END ADDRESS: FFCEFFFF + */ + /* + * APERTURE NAME: MBISTJTAG, START ADDRESS: FFCF0000, END ADDRESS: FFCFFFFF + */ + /* + * APERTURE NAME: PMU_ROM, START ADDRESS: FFD00000, END ADDRESS: FFD3FFFF + */ + /* + * APERTURE NAME: PMU_ROM, START ADDRESS: FFD00000, END ADDRESS: FFD3FFFF + */ + /* + * APERTURE NAME: PMU_ROM, START ADDRESS: FFD00000, END ADDRESS: FFD3FFFF + */ + /* + * APERTURE NAME: PMU_ROM, START ADDRESS: FFD00000, END ADDRESS: FFD3FFFF + */ + /* + * APERTURE NAME: PMU_IOMODULE, START ADDRESS: FFD40000, END ADDRESS: FFD5F + * FFF + */ + /* + * APERTURE NAME: PMU_IOMODULE, START ADDRESS: FFD40000, END ADDRESS: FFD5F + * FFF + */ + /* + * APERTURE NAME: PMU_LOCAL, START ADDRESS: FFD60000, END ADDRESS: FFD7FFFF + */ + /* + * APERTURE NAME: PMU_LOCAL, START ADDRESS: FFD60000, END ADDRESS: FFD7FFFF + */ + /* + * APERTURE NAME: PMU_GLOBAL, START ADDRESS: FFD80000, END ADDRESS: FFDBFFF + * F + */ + /* + * APERTURE NAME: PMU_GLOBAL, START ADDRESS: FFD80000, END ADDRESS: FFDBFFF + * F + */ + /* + * APERTURE NAME: PMU_GLOBAL, START ADDRESS: FFD80000, END ADDRESS: FFDBFFF + * F + */ + /* + * APERTURE NAME: PMU_GLOBAL, START ADDRESS: FFD80000, END ADDRESS: FFDBFFF + * F + */ + /* + * APERTURE NAME: PMU_RAM, START ADDRESS: FFDC0000, END ADDRESS: FFDFFFFF + */ + /* + * APERTURE NAME: PMU_RAM, START ADDRESS: FFDC0000, END ADDRESS: FFDFFFFF + */ + /* + * APERTURE NAME: PMU_RAM, START ADDRESS: FFDC0000, END ADDRESS: FFDFFFFF + */ + /* + * APERTURE NAME: PMU_RAM, START ADDRESS: FFDC0000, END ADDRESS: FFDFFFFF + */ + /* + * APERTURE NAME: R5_0_ATCM, START ADDRESS: FFE00000, END ADDRESS: FFE0FFFF + */ + /* + * APERTURE NAME: R5_0_ATCM_LOCKSTEP, START ADDRESS: FFE10000, END ADDRESS: + * FFE1FFFF + */ + /* + * APERTURE NAME: R5_0_BTCM, START ADDRESS: FFE20000, END ADDRESS: FFE2FFFF + */ + /* + * APERTURE NAME: R5_0_BTCM_LOCKSTEP, START ADDRESS: FFE30000, END ADDRESS: + * FFE3FFFF + */ + /* + * APERTURE NAME: R5_0_INSTRUCTION_CACHE, START ADDRESS: FFE40000, END ADDR + * ESS: FFE4FFFF + */ + /* + * APERTURE NAME: R5_0_DATA_CACHE, START ADDRESS: FFE50000, END ADDRESS: FF + * E5FFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_8, START ADDRESS: FFE60000, END ADDRESS: FFE8F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_8, START ADDRESS: FFE60000, END ADDRESS: FFE8F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_8, START ADDRESS: FFE60000, END ADDRESS: FFE8F + * FFF + */ + /* + * APERTURE NAME: R5_1_ATCM_, START ADDRESS: FFE90000, END ADDRESS: FFE9FFF + * F + */ + /* + * APERTURE NAME: RPU_UNUSED_10, START ADDRESS: FFEA0000, END ADDRESS: FFEA + * FFFF + */ + /* + * APERTURE NAME: R5_1_BTCM_, START ADDRESS: FFEB0000, END ADDRESS: FFEBFFF + * F + */ + /* + * APERTURE NAME: R5_1_INSTRUCTION_CACHE, START ADDRESS: FFEC0000, END ADDR + * ESS: FFECFFFF + */ + /* + * APERTURE NAME: R5_1_DATA_CACHE, START ADDRESS: FFED0000, END ADDRESS: FF + * EDFFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_15, START ADDRESS: FFFD0000, END ADDRESS: FFFF + * FFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_15, START ADDRESS: FFFD0000, END ADDRESS: FFFF + * FFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_15, START ADDRESS: FFFD0000, END ADDRESS: FFFF + * FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IOU_GPV, START ADDRESS: FE000000, END ADDRESS: FE0FFFFF + */ + /* + * APERTURE NAME: LPD_GPV, START ADDRESS: FE100000, END ADDRESS: FE1FFFFF + */ + /* + * APERTURE NAME: USB3_0_XHCI, START ADDRESS: FE200000, END ADDRESS: FE2FFF + * FF + */ + /* + * APERTURE NAME: USB3_1_XHCI, START ADDRESS: FE300000, END ADDRESS: FE3FFF + * FF + */ + /* + * APERTURE NAME: LPD_UNUSED_13, START ADDRESS: FE400000, END ADDRESS: FE7F + * FFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_13, START ADDRESS: FE400000, END ADDRESS: FE7F + * FFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_13, START ADDRESS: FE400000, END ADDRESS: FE7F + * FFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_13, START ADDRESS: FE400000, END ADDRESS: FE7F + * FFFF + */ + /* + * APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF + */ + /* + * APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF + */ + /* + * APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF + */ + /* + * APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF + */ + /* + * APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF + */ + /* + * APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF + */ + /* + * APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF + */ + /* + * APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF + */ + /* + * APERTURE NAME: QSPI_LINEAR_ADDRESS, START ADDRESS: C0000000, END ADDRESS + * : DFFFFFFF + */ + /* + * XPPU CONTROL + */ - return 1; + return 1; } -unsigned long psu_ddr_xmpu1_data() { +unsigned long psu_ddr_xmpu0_data(void) +{ + /* + * DDR XMPU0 + */ - return 1; + return 1; } -unsigned long psu_ddr_xmpu2_data() { +unsigned long psu_ddr_xmpu1_data(void) +{ + /* + * DDR XMPU1 + */ - return 1; + return 1; } -unsigned long psu_ddr_xmpu3_data() { +unsigned long psu_ddr_xmpu2_data(void) +{ + /* + * DDR XMPU2 + */ - return 1; + return 1; } -unsigned long psu_ddr_xmpu4_data() { +unsigned long psu_ddr_xmpu3_data(void) +{ + /* + * DDR XMPU3 + */ - return 1; + return 1; } -unsigned long psu_ddr_xmpu5_data() { +unsigned long psu_ddr_xmpu4_data(void) +{ + /* + * DDR XMPU4 + */ - return 1; + return 1; } -unsigned long psu_ocm_xmpu_data() { +unsigned long psu_ddr_xmpu5_data(void) +{ + /* + * DDR XMPU5 + */ - return 1; + return 1; } -unsigned long psu_fpd_xmpu_data() { +unsigned long psu_ocm_xmpu_data(void) +{ + /* + * OCM XMPU + */ - return 1; + return 1; } -unsigned long psu_protection_lock_data() { +unsigned long psu_fpd_xmpu_data(void) +{ + /* + * FPD XMPU + */ - return 1; + return 1; } -unsigned long psu_apply_master_tz() { - // : RPU - // : DP TZ - // : SATA TZ - // : PCIE TZ - // : USB TZ - // : SD TZ - // : GEM TZ - // : QSPI TZ - // : NAND TZ +unsigned long psu_protection_lock_data(void) +{ + /* + * LOCKING PROTECTION MODULE + */ + /* + * XPPU LOCK + */ + /* + * APERTURE NAME: LPD_XPPU, START ADDRESS: FF980000, END ADDRESS: FF99FFFF + */ + /* + * XMPU LOCK + */ + /* + * LOCK OCM XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER + */ + /* + * LOCK FPD XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER + */ + /* + * LOCK DDR XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER + */ + /* + * LOCK DDR XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER + */ + /* + * LOCK DDR XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER + */ + /* + * LOCK DDR XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER + */ + /* + * LOCK DDR XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER + */ + /* + * LOCK DDR XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER + */ - return 1; + return 1; } -unsigned long psu_serdes_init_data() { - // : SERDES INITIALIZATION - // : GT REFERENCE CLOCK SOURCE SELECTION - /*Register : PLL_REF_SEL0 @ 0XFD410000

+unsigned long psu_apply_master_tz(void) +{ + /* + * RPU + */ + /* + * DP TZ + */ + /* + * Register : slcr_dpdma @ 0XFD690040 - PLL0 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - - 4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135 - Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved - PSU_SERDES_PLL_REF_SEL0_PLLREFSEL0 0xD + * TrustZone classification for DisplayPort DMA + * PSU_FPD_SLCR_SECURE_SLCR_DPDMA_TZ 1 - PLL0 Reference Selection Register - (OFFSET, MASK, VALUE) (0XFD410000, 0x0000001FU ,0x0000000DU) - RegMask = (SERDES_PLL_REF_SEL0_PLLREFSEL0_MASK | 0 ); + * DPDMA TrustZone Settings + * (OFFSET, MASK, VALUE) (0XFD690040, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(FPD_SLCR_SECURE_SLCR_DPDMA_OFFSET, + 0x00000001U, 0x00000001U); +/*##################################################################### */ - RegVal = ((0x0000000DU << SERDES_PLL_REF_SEL0_PLLREFSEL0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_PLL_REF_SEL0_OFFSET ,0x0000001FU ,0x0000000DU); - /*############################################################################################################################ */ + /* + * SATA TZ + */ + /* + * PCIE TZ + */ + /* + * Register : slcr_pcie @ 0XFD690030 - /*Register : PLL_REF_SEL1 @ 0XFD410004

+ * TrustZone classification for DMA Channel 0 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_0 1 - PLL1 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - - 4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135 - Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved - PSU_SERDES_PLL_REF_SEL1_PLLREFSEL1 0x9 + * TrustZone classification for DMA Channel 1 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_1 1 - PLL1 Reference Selection Register - (OFFSET, MASK, VALUE) (0XFD410004, 0x0000001FU ,0x00000009U) - RegMask = (SERDES_PLL_REF_SEL1_PLLREFSEL1_MASK | 0 ); + * TrustZone classification for DMA Channel 2 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_2 1 - RegVal = ((0x00000009U << SERDES_PLL_REF_SEL1_PLLREFSEL1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_PLL_REF_SEL1_OFFSET ,0x0000001FU ,0x00000009U); - /*############################################################################################################################ */ + * TrustZone classification for DMA Channel 3 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_3 1 - /*Register : PLL_REF_SEL2 @ 0XFD410008

+ * TrustZone classification for Ingress Address Translation 0 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_0 1 - PLL2 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - - 4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135 - Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved - PSU_SERDES_PLL_REF_SEL2_PLLREFSEL2 0x8 + * TrustZone classification for Ingress Address Translation 1 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_1 1 - PLL2 Reference Selection Register - (OFFSET, MASK, VALUE) (0XFD410008, 0x0000001FU ,0x00000008U) - RegMask = (SERDES_PLL_REF_SEL2_PLLREFSEL2_MASK | 0 ); + * TrustZone classification for Ingress Address Translation 2 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_2 1 - RegVal = ((0x00000008U << SERDES_PLL_REF_SEL2_PLLREFSEL2_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_PLL_REF_SEL2_OFFSET ,0x0000001FU ,0x00000008U); - /*############################################################################################################################ */ + * TrustZone classification for Ingress Address Translation 3 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_3 1 + + * TrustZone classification for Ingress Address Translation 4 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_4 1 + + * TrustZone classification for Ingress Address Translation 5 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_5 1 + + * TrustZone classification for Ingress Address Translation 6 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_6 1 - /*Register : PLL_REF_SEL3 @ 0XFD41000C

- - PLL3 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - - 4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135 - Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved - PSU_SERDES_PLL_REF_SEL3_PLLREFSEL3 0xF - - PLL3 Reference Selection Register - (OFFSET, MASK, VALUE) (0XFD41000C, 0x0000001FU ,0x0000000FU) - RegMask = (SERDES_PLL_REF_SEL3_PLLREFSEL3_MASK | 0 ); - - RegVal = ((0x0000000FU << SERDES_PLL_REF_SEL3_PLLREFSEL3_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_PLL_REF_SEL3_OFFSET ,0x0000001FU ,0x0000000FU); - /*############################################################################################################################ */ - - // : GT REFERENCE CLOCK FREQUENCY SELECTION - /*Register : L0_L0_REF_CLK_SEL @ 0XFD402860

- - Sel of lane 0 ref clock local mux. Set to 1 to select lane 0 slicer output. Set to 0 to select lane0 ref clock mux output. - PSU_SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL 0x1 - - Lane0 Ref Clock Selection Register - (OFFSET, MASK, VALUE) (0XFD402860, 0x00000080U ,0x00000080U) - RegMask = (SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_L0_REF_CLK_SEL_OFFSET ,0x00000080U ,0x00000080U); - /*############################################################################################################################ */ - - /*Register : L0_L1_REF_CLK_SEL @ 0XFD402864

- - Sel of lane 1 ref clock local mux. Set to 1 to select lane 1 slicer output. Set to 0 to select lane1 ref clock mux output. - PSU_SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL 0x0 - - Bit 3 of lane 1 ref clock mux one hot sel. Set to 1 to select lane 3 slicer output from ref clock network - PSU_SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3 0x1 - - Lane1 Ref Clock Selection Register - (OFFSET, MASK, VALUE) (0XFD402864, 0x00000088U ,0x00000008U) - RegMask = (SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_MASK | SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_MASK | 0 ); - - RegVal = ((0x00000000U << SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_SHIFT - | 0x00000001U << SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_L1_REF_CLK_SEL_OFFSET ,0x00000088U ,0x00000008U); - /*############################################################################################################################ */ - - /*Register : L0_L2_REF_CLK_SEL @ 0XFD402868

- - Sel of lane 2 ref clock local mux. Set to 1 to select lane 1 slicer output. Set to 0 to select lane2 ref clock mux output. - PSU_SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL 0x1 - - Lane2 Ref Clock Selection Register - (OFFSET, MASK, VALUE) (0XFD402868, 0x00000080U ,0x00000080U) - RegMask = (SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_L2_REF_CLK_SEL_OFFSET ,0x00000080U ,0x00000080U); - /*############################################################################################################################ */ - - /*Register : L0_L3_REF_CLK_SEL @ 0XFD40286C

- - Sel of lane 3 ref clock local mux. Set to 1 to select lane 3 slicer output. Set to 0 to select lane3 ref clock mux output. - PSU_SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL 0x0 - - Bit 1 of lane 3 ref clock mux one hot sel. Set to 1 to select lane 1 slicer output from ref clock network - PSU_SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1 0x1 - - Lane3 Ref Clock Selection Register - (OFFSET, MASK, VALUE) (0XFD40286C, 0x00000082U ,0x00000002U) - RegMask = (SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_MASK | SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_MASK | 0 ); - - RegVal = ((0x00000000U << SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_SHIFT - | 0x00000001U << SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_L3_REF_CLK_SEL_OFFSET ,0x00000082U ,0x00000002U); - /*############################################################################################################################ */ - - // : ENABLE SPREAD SPECTRUM - /*Register : L2_TM_PLL_DIG_37 @ 0XFD40A094

- - Enable/Disable coarse code satureation limiting logic - PSU_SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION 0x1 - - Test mode register 37 - (OFFSET, MASK, VALUE) (0XFD40A094, 0x00000010U ,0x00000010U) - RegMask = (SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_TM_PLL_DIG_37_OFFSET ,0x00000010U ,0x00000010U); - /*############################################################################################################################ */ - - /*Register : L2_PLL_SS_STEPS_0_LSB @ 0XFD40A368

- - Spread Spectrum No of Steps [7:0] - PSU_SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB 0x38 - - Spread Spectrum No of Steps bits 7:0 - (OFFSET, MASK, VALUE) (0XFD40A368, 0x000000FFU ,0x00000038U) - RegMask = (SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK | 0 ); - - RegVal = ((0x00000038U << SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_PLL_SS_STEPS_0_LSB_OFFSET ,0x000000FFU ,0x00000038U); - /*############################################################################################################################ */ - - /*Register : L2_PLL_SS_STEPS_1_MSB @ 0XFD40A36C

- - Spread Spectrum No of Steps [10:8] - PSU_SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB 0x03 - - Spread Spectrum No of Steps bits 10:8 - (OFFSET, MASK, VALUE) (0XFD40A36C, 0x00000007U ,0x00000003U) - RegMask = (SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK | 0 ); - - RegVal = ((0x00000003U << SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_PLL_SS_STEPS_1_MSB_OFFSET ,0x00000007U ,0x00000003U); - /*############################################################################################################################ */ - - /*Register : L3_PLL_SS_STEPS_0_LSB @ 0XFD40E368

- - Spread Spectrum No of Steps [7:0] - PSU_SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB 0xE0 - - Spread Spectrum No of Steps bits 7:0 - (OFFSET, MASK, VALUE) (0XFD40E368, 0x000000FFU ,0x000000E0U) - RegMask = (SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK | 0 ); - - RegVal = ((0x000000E0U << SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_PLL_SS_STEPS_0_LSB_OFFSET ,0x000000FFU ,0x000000E0U); - /*############################################################################################################################ */ - - /*Register : L3_PLL_SS_STEPS_1_MSB @ 0XFD40E36C

- - Spread Spectrum No of Steps [10:8] - PSU_SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB 0x3 - - Spread Spectrum No of Steps bits 10:8 - (OFFSET, MASK, VALUE) (0XFD40E36C, 0x00000007U ,0x00000003U) - RegMask = (SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK | 0 ); - - RegVal = ((0x00000003U << SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_PLL_SS_STEPS_1_MSB_OFFSET ,0x00000007U ,0x00000003U); - /*############################################################################################################################ */ - - /*Register : L1_PLL_SS_STEPS_0_LSB @ 0XFD406368

- - Spread Spectrum No of Steps [7:0] - PSU_SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB 0x58 - - Spread Spectrum No of Steps bits 7:0 - (OFFSET, MASK, VALUE) (0XFD406368, 0x000000FFU ,0x00000058U) - RegMask = (SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK | 0 ); - - RegVal = ((0x00000058U << SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L1_PLL_SS_STEPS_0_LSB_OFFSET ,0x000000FFU ,0x00000058U); - /*############################################################################################################################ */ - - /*Register : L1_PLL_SS_STEPS_1_MSB @ 0XFD40636C

- - Spread Spectrum No of Steps [10:8] - PSU_SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB 0x3 - - Spread Spectrum No of Steps bits 10:8 - (OFFSET, MASK, VALUE) (0XFD40636C, 0x00000007U ,0x00000003U) - RegMask = (SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK | 0 ); - - RegVal = ((0x00000003U << SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L1_PLL_SS_STEPS_1_MSB_OFFSET ,0x00000007U ,0x00000003U); - /*############################################################################################################################ */ - - /*Register : L1_PLL_SS_STEP_SIZE_0_LSB @ 0XFD406370

- - Step Size for Spread Spectrum [7:0] - PSU_SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB 0x7C - - Step Size for Spread Spectrum LSB - (OFFSET, MASK, VALUE) (0XFD406370, 0x000000FFU ,0x0000007CU) - RegMask = (SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK | 0 ); - - RegVal = ((0x0000007CU << SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_OFFSET ,0x000000FFU ,0x0000007CU); - /*############################################################################################################################ */ - - /*Register : L1_PLL_SS_STEP_SIZE_1 @ 0XFD406374

- - Step Size for Spread Spectrum [15:8] - PSU_SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1 0x33 - - Step Size for Spread Spectrum 1 - (OFFSET, MASK, VALUE) (0XFD406374, 0x000000FFU ,0x00000033U) - RegMask = (SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK | 0 ); - - RegVal = ((0x00000033U << SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L1_PLL_SS_STEP_SIZE_1_OFFSET ,0x000000FFU ,0x00000033U); - /*############################################################################################################################ */ - - /*Register : L1_PLL_SS_STEP_SIZE_2 @ 0XFD406378

- - Step Size for Spread Spectrum [23:16] - PSU_SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2 0x2 - - Step Size for Spread Spectrum 2 - (OFFSET, MASK, VALUE) (0XFD406378, 0x000000FFU ,0x00000002U) - RegMask = (SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK | 0 ); - - RegVal = ((0x00000002U << SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L1_PLL_SS_STEP_SIZE_2_OFFSET ,0x000000FFU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : L1_PLL_SS_STEP_SIZE_3_MSB @ 0XFD40637C

- - Step Size for Spread Spectrum [25:24] - PSU_SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB 0x0 - - Enable/Disable test mode force on SS step size - PSU_SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE 0x1 - - Enable/Disable test mode force on SS no of steps - PSU_SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS 0x1 - - Enable force on enable Spread Spectrum - (OFFSET, MASK, VALUE) (0XFD40637C, 0x00000033U ,0x00000030U) - RegMask = (SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK | SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK | SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK | 0 ); - - RegVal = ((0x00000000U << SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT - | 0x00000001U << SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT - | 0x00000001U << SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_OFFSET ,0x00000033U ,0x00000030U); - /*############################################################################################################################ */ - - /*Register : L2_PLL_SS_STEP_SIZE_0_LSB @ 0XFD40A370

- - Step Size for Spread Spectrum [7:0] - PSU_SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB 0xF4 - - Step Size for Spread Spectrum LSB - (OFFSET, MASK, VALUE) (0XFD40A370, 0x000000FFU ,0x000000F4U) - RegMask = (SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK | 0 ); - - RegVal = ((0x000000F4U << SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_OFFSET ,0x000000FFU ,0x000000F4U); - /*############################################################################################################################ */ - - /*Register : L2_PLL_SS_STEP_SIZE_1 @ 0XFD40A374

- - Step Size for Spread Spectrum [15:8] - PSU_SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1 0x31 - - Step Size for Spread Spectrum 1 - (OFFSET, MASK, VALUE) (0XFD40A374, 0x000000FFU ,0x00000031U) - RegMask = (SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK | 0 ); - - RegVal = ((0x00000031U << SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_PLL_SS_STEP_SIZE_1_OFFSET ,0x000000FFU ,0x00000031U); - /*############################################################################################################################ */ - - /*Register : L2_PLL_SS_STEP_SIZE_2 @ 0XFD40A378

- - Step Size for Spread Spectrum [23:16] - PSU_SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2 0x2 - - Step Size for Spread Spectrum 2 - (OFFSET, MASK, VALUE) (0XFD40A378, 0x000000FFU ,0x00000002U) - RegMask = (SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK | 0 ); - - RegVal = ((0x00000002U << SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_PLL_SS_STEP_SIZE_2_OFFSET ,0x000000FFU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : L2_PLL_SS_STEP_SIZE_3_MSB @ 0XFD40A37C

- - Step Size for Spread Spectrum [25:24] - PSU_SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB 0x0 - - Enable/Disable test mode force on SS step size - PSU_SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE 0x1 - - Enable/Disable test mode force on SS no of steps - PSU_SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS 0x1 - - Enable force on enable Spread Spectrum - (OFFSET, MASK, VALUE) (0XFD40A37C, 0x00000033U ,0x00000030U) - RegMask = (SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK | SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK | SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK | 0 ); - - RegVal = ((0x00000000U << SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT - | 0x00000001U << SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT - | 0x00000001U << SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_OFFSET ,0x00000033U ,0x00000030U); - /*############################################################################################################################ */ - - /*Register : L3_PLL_SS_STEP_SIZE_0_LSB @ 0XFD40E370

- - Step Size for Spread Spectrum [7:0] - PSU_SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB 0xC9 - - Step Size for Spread Spectrum LSB - (OFFSET, MASK, VALUE) (0XFD40E370, 0x000000FFU ,0x000000C9U) - RegMask = (SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK | 0 ); - - RegVal = ((0x000000C9U << SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_OFFSET ,0x000000FFU ,0x000000C9U); - /*############################################################################################################################ */ - - /*Register : L3_PLL_SS_STEP_SIZE_1 @ 0XFD40E374

- - Step Size for Spread Spectrum [15:8] - PSU_SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1 0xD2 - - Step Size for Spread Spectrum 1 - (OFFSET, MASK, VALUE) (0XFD40E374, 0x000000FFU ,0x000000D2U) - RegMask = (SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK | 0 ); - - RegVal = ((0x000000D2U << SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_PLL_SS_STEP_SIZE_1_OFFSET ,0x000000FFU ,0x000000D2U); - /*############################################################################################################################ */ - - /*Register : L3_PLL_SS_STEP_SIZE_2 @ 0XFD40E378

- - Step Size for Spread Spectrum [23:16] - PSU_SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2 0x1 - - Step Size for Spread Spectrum 2 - (OFFSET, MASK, VALUE) (0XFD40E378, 0x000000FFU ,0x00000001U) - RegMask = (SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_PLL_SS_STEP_SIZE_2_OFFSET ,0x000000FFU ,0x00000001U); - /*############################################################################################################################ */ - - /*Register : L3_PLL_SS_STEP_SIZE_3_MSB @ 0XFD40E37C

- - Step Size for Spread Spectrum [25:24] - PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB 0x0 - - Enable/Disable test mode force on SS step size - PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE 0x1 - - Enable/Disable test mode force on SS no of steps - PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS 0x1 - - Enable test mode forcing on enable Spread Spectrum - PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS 0x1 - - Enable force on enable Spread Spectrum - (OFFSET, MASK, VALUE) (0XFD40E37C, 0x000000B3U ,0x000000B0U) - RegMask = (SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK | SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK | SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK | SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_MASK | 0 ); - - RegVal = ((0x00000000U << SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT - | 0x00000001U << SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT - | 0x00000001U << SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT - | 0x00000001U << SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_OFFSET ,0x000000B3U ,0x000000B0U); - /*############################################################################################################################ */ - - /*Register : L2_TM_DIG_6 @ 0XFD40906C

- - Bypass Descrambler - PSU_SERDES_L2_TM_DIG_6_BYPASS_DESCRAM 0x1 - - Enable Bypass for <1> TM_DIG_CTRL_6 - PSU_SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM 0x1 - - Data path test modes in decoder and descram - (OFFSET, MASK, VALUE) (0XFD40906C, 0x00000003U ,0x00000003U) - RegMask = (SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_MASK | SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_SHIFT - | 0x00000001U << SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_TM_DIG_6_OFFSET ,0x00000003U ,0x00000003U); - /*############################################################################################################################ */ - - /*Register : L2_TX_DIG_TM_61 @ 0XFD4080F4

- - Bypass scrambler signal - PSU_SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM 0x1 - - Enable/disable scrambler bypass signal - PSU_SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM 0x1 - - MPHY PLL Gear and bypass scrambler - (OFFSET, MASK, VALUE) (0XFD4080F4, 0x00000003U ,0x00000003U) - RegMask = (SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_MASK | SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_SHIFT - | 0x00000001U << SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_TX_DIG_TM_61_OFFSET ,0x00000003U ,0x00000003U); - /*############################################################################################################################ */ - - /*Register : L3_PLL_FBDIV_FRAC_3_MSB @ 0XFD40E360

- - Enable test mode force on fractional mode enable - PSU_SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC 0x1 - - Fractional feedback division control and fractional value for feedback division bits 26:24 - (OFFSET, MASK, VALUE) (0XFD40E360, 0x00000040U ,0x00000040U) - RegMask = (SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_PLL_FBDIV_FRAC_3_MSB_OFFSET ,0x00000040U ,0x00000040U); - /*############################################################################################################################ */ - - /*Register : L3_TM_DIG_6 @ 0XFD40D06C

- - Bypass 8b10b decoder - PSU_SERDES_L3_TM_DIG_6_BYPASS_DECODER 0x1 - - Enable Bypass for <3> TM_DIG_CTRL_6 - PSU_SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC 0x1 - - Bypass Descrambler - PSU_SERDES_L3_TM_DIG_6_BYPASS_DESCRAM 0x1 - - Enable Bypass for <1> TM_DIG_CTRL_6 - PSU_SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM 0x1 - - Data path test modes in decoder and descram - (OFFSET, MASK, VALUE) (0XFD40D06C, 0x0000000FU ,0x0000000FU) - RegMask = (SERDES_L3_TM_DIG_6_BYPASS_DECODER_MASK | SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_MASK | SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_MASK | SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L3_TM_DIG_6_BYPASS_DECODER_SHIFT - | 0x00000001U << SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_SHIFT - | 0x00000001U << SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_SHIFT - | 0x00000001U << SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_DIG_6_OFFSET ,0x0000000FU ,0x0000000FU); - /*############################################################################################################################ */ - - /*Register : L3_TX_DIG_TM_61 @ 0XFD40C0F4

- - Enable/disable encoder bypass signal - PSU_SERDES_L3_TX_DIG_TM_61_BYPASS_ENC 0x1 - - Bypass scrambler signal - PSU_SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM 0x1 - - Enable/disable scrambler bypass signal - PSU_SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM 0x1 - - MPHY PLL Gear and bypass scrambler - (OFFSET, MASK, VALUE) (0XFD40C0F4, 0x0000000BU ,0x0000000BU) - RegMask = (SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_MASK | SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_MASK | SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_SHIFT - | 0x00000001U << SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_SHIFT - | 0x00000001U << SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TX_DIG_TM_61_OFFSET ,0x0000000BU ,0x0000000BU); - /*############################################################################################################################ */ - - /*Register : L3_TXPMA_ST_0 @ 0XFD40CB00

- - PHY Mode: 4'b000 - PCIe, 4'b001 - USB3, 4'b0010 - SATA, 4'b0100 - SGMII, 4'b0101 - DP, 4'b1000 - MPHY - PSU_SERDES_L3_TXPMA_ST_0_TX_PHY_MODE 0x21 - - Opmode Info - (OFFSET, MASK, VALUE) (0XFD40CB00, 0x000000F0U ,0x000000F0U) - RegMask = (SERDES_L3_TXPMA_ST_0_TX_PHY_MODE_MASK | 0 ); - - RegVal = ((0x00000021U << SERDES_L3_TXPMA_ST_0_TX_PHY_MODE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TXPMA_ST_0_OFFSET ,0x000000F0U ,0x000000F0U); - /*############################################################################################################################ */ - - // : ENABLE CHICKEN BIT FOR PCIE AND USB - /*Register : L0_TM_AUX_0 @ 0XFD4010CC

- - Spare- not used - PSU_SERDES_L0_TM_AUX_0_BIT_2 1 - - Spare registers - (OFFSET, MASK, VALUE) (0XFD4010CC, 0x00000020U ,0x00000020U) - RegMask = (SERDES_L0_TM_AUX_0_BIT_2_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L0_TM_AUX_0_BIT_2_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_TM_AUX_0_OFFSET ,0x00000020U ,0x00000020U); - /*############################################################################################################################ */ - - /*Register : L2_TM_AUX_0 @ 0XFD4090CC

- - Spare- not used - PSU_SERDES_L2_TM_AUX_0_BIT_2 1 - - Spare registers - (OFFSET, MASK, VALUE) (0XFD4090CC, 0x00000020U ,0x00000020U) - RegMask = (SERDES_L2_TM_AUX_0_BIT_2_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L2_TM_AUX_0_BIT_2_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_TM_AUX_0_OFFSET ,0x00000020U ,0x00000020U); - /*############################################################################################################################ */ - - // : ENABLING EYE SURF - /*Register : L0_TM_DIG_8 @ 0XFD401074

- - Enable Eye Surf - PSU_SERDES_L0_TM_DIG_8_EYESURF_ENABLE 0x1 - - Test modes for Elastic buffer and enabling Eye Surf - (OFFSET, MASK, VALUE) (0XFD401074, 0x00000010U ,0x00000010U) - RegMask = (SERDES_L0_TM_DIG_8_EYESURF_ENABLE_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L0_TM_DIG_8_EYESURF_ENABLE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_TM_DIG_8_OFFSET ,0x00000010U ,0x00000010U); - /*############################################################################################################################ */ - - /*Register : L1_TM_DIG_8 @ 0XFD405074

- - Enable Eye Surf - PSU_SERDES_L1_TM_DIG_8_EYESURF_ENABLE 0x1 - - Test modes for Elastic buffer and enabling Eye Surf - (OFFSET, MASK, VALUE) (0XFD405074, 0x00000010U ,0x00000010U) - RegMask = (SERDES_L1_TM_DIG_8_EYESURF_ENABLE_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L1_TM_DIG_8_EYESURF_ENABLE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L1_TM_DIG_8_OFFSET ,0x00000010U ,0x00000010U); - /*############################################################################################################################ */ - - /*Register : L2_TM_DIG_8 @ 0XFD409074

- - Enable Eye Surf - PSU_SERDES_L2_TM_DIG_8_EYESURF_ENABLE 0x1 - - Test modes for Elastic buffer and enabling Eye Surf - (OFFSET, MASK, VALUE) (0XFD409074, 0x00000010U ,0x00000010U) - RegMask = (SERDES_L2_TM_DIG_8_EYESURF_ENABLE_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L2_TM_DIG_8_EYESURF_ENABLE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_TM_DIG_8_OFFSET ,0x00000010U ,0x00000010U); - /*############################################################################################################################ */ - - /*Register : L3_TM_DIG_8 @ 0XFD40D074

- - Enable Eye Surf - PSU_SERDES_L3_TM_DIG_8_EYESURF_ENABLE 0x1 - - Test modes for Elastic buffer and enabling Eye Surf - (OFFSET, MASK, VALUE) (0XFD40D074, 0x00000010U ,0x00000010U) - RegMask = (SERDES_L3_TM_DIG_8_EYESURF_ENABLE_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L3_TM_DIG_8_EYESURF_ENABLE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_DIG_8_OFFSET ,0x00000010U ,0x00000010U); - /*############################################################################################################################ */ - - // : ILL SETTINGS FOR GAIN AND LOCK SETTINGS - /*Register : L0_TM_MISC2 @ 0XFD40189C

- - ILL calib counts BYPASSED with calcode bits - PSU_SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS 0x1 - - sampler cal - (OFFSET, MASK, VALUE) (0XFD40189C, 0x00000080U ,0x00000080U) - RegMask = (SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_TM_MISC2_OFFSET ,0x00000080U ,0x00000080U); - /*############################################################################################################################ */ - - /*Register : L0_TM_IQ_ILL1 @ 0XFD4018F8

- - IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS - PSU_SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0 0x64 - - iqpi cal code - (OFFSET, MASK, VALUE) (0XFD4018F8, 0x000000FFU ,0x00000064U) - RegMask = (SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK | 0 ); - - RegVal = ((0x00000064U << SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_TM_IQ_ILL1_OFFSET ,0x000000FFU ,0x00000064U); - /*############################################################################################################################ */ - - /*Register : L0_TM_IQ_ILL2 @ 0XFD4018FC

- - IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 - PSU_SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1 0x64 - - iqpi cal code - (OFFSET, MASK, VALUE) (0XFD4018FC, 0x000000FFU ,0x00000064U) - RegMask = (SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK | 0 ); - - RegVal = ((0x00000064U << SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_TM_IQ_ILL2_OFFSET ,0x000000FFU ,0x00000064U); - /*############################################################################################################################ */ - - /*Register : L0_TM_ILL12 @ 0XFD401990

- - G1A pll ctr bypass value - PSU_SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL 0x11 - - ill pll counter values - (OFFSET, MASK, VALUE) (0XFD401990, 0x000000FFU ,0x00000011U) - RegMask = (SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK | 0 ); - - RegVal = ((0x00000011U << SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_TM_ILL12_OFFSET ,0x000000FFU ,0x00000011U); - /*############################################################################################################################ */ - - /*Register : L0_TM_E_ILL1 @ 0XFD401924

- - E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS - PSU_SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0 0x4 - - epi cal code - (OFFSET, MASK, VALUE) (0XFD401924, 0x000000FFU ,0x00000004U) - RegMask = (SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK | 0 ); - - RegVal = ((0x00000004U << SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_TM_E_ILL1_OFFSET ,0x000000FFU ,0x00000004U); - /*############################################################################################################################ */ - - /*Register : L0_TM_E_ILL2 @ 0XFD401928

- - E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 - PSU_SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1 0xFE - - epi cal code - (OFFSET, MASK, VALUE) (0XFD401928, 0x000000FFU ,0x000000FEU) - RegMask = (SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK | 0 ); - - RegVal = ((0x000000FEU << SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_TM_E_ILL2_OFFSET ,0x000000FFU ,0x000000FEU); - /*############################################################################################################################ */ - - /*Register : L0_TM_IQ_ILL3 @ 0XFD401900

- - IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 - PSU_SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2 0x64 - - iqpi cal code - (OFFSET, MASK, VALUE) (0XFD401900, 0x000000FFU ,0x00000064U) - RegMask = (SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK | 0 ); - - RegVal = ((0x00000064U << SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_TM_IQ_ILL3_OFFSET ,0x000000FFU ,0x00000064U); - /*############################################################################################################################ */ - - /*Register : L0_TM_E_ILL3 @ 0XFD40192C

- - E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 - PSU_SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2 0x0 - - epi cal code - (OFFSET, MASK, VALUE) (0XFD40192C, 0x000000FFU ,0x00000000U) - RegMask = (SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK | 0 ); - - RegVal = ((0x00000000U << SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_TM_E_ILL3_OFFSET ,0x000000FFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : L0_TM_ILL8 @ 0XFD401980

- - ILL calibration code change wait time - PSU_SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT 0xFF - - ILL cal routine control - (OFFSET, MASK, VALUE) (0XFD401980, 0x000000FFU ,0x000000FFU) - RegMask = (SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_MASK | 0 ); - - RegVal = ((0x000000FFU << SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_TM_ILL8_OFFSET ,0x000000FFU ,0x000000FFU); - /*############################################################################################################################ */ - - /*Register : L0_TM_IQ_ILL8 @ 0XFD401914

- - IQ ILL polytrim bypass value - PSU_SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL 0xF7 - - iqpi polytrim - (OFFSET, MASK, VALUE) (0XFD401914, 0x000000FFU ,0x000000F7U) - RegMask = (SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK | 0 ); - - RegVal = ((0x000000F7U << SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_TM_IQ_ILL8_OFFSET ,0x000000FFU ,0x000000F7U); - /*############################################################################################################################ */ - - /*Register : L0_TM_IQ_ILL9 @ 0XFD401918

- - bypass IQ polytrim - PSU_SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM 0x1 - - enables for lf,constant gm trim and polytirm - (OFFSET, MASK, VALUE) (0XFD401918, 0x00000001U ,0x00000001U) - RegMask = (SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_TM_IQ_ILL9_OFFSET ,0x00000001U ,0x00000001U); - /*############################################################################################################################ */ - - /*Register : L0_TM_E_ILL8 @ 0XFD401940

- - E ILL polytrim bypass value - PSU_SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL 0xF7 - - epi polytrim - (OFFSET, MASK, VALUE) (0XFD401940, 0x000000FFU ,0x000000F7U) - RegMask = (SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK | 0 ); - - RegVal = ((0x000000F7U << SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_TM_E_ILL8_OFFSET ,0x000000FFU ,0x000000F7U); - /*############################################################################################################################ */ - - /*Register : L0_TM_E_ILL9 @ 0XFD401944

- - bypass E polytrim - PSU_SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM 0x1 - - enables for lf,constant gm trim and polytirm - (OFFSET, MASK, VALUE) (0XFD401944, 0x00000001U ,0x00000001U) - RegMask = (SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_TM_E_ILL9_OFFSET ,0x00000001U ,0x00000001U); - /*############################################################################################################################ */ - - /*Register : L2_TM_MISC2 @ 0XFD40989C

- - ILL calib counts BYPASSED with calcode bits - PSU_SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS 0x1 - - sampler cal - (OFFSET, MASK, VALUE) (0XFD40989C, 0x00000080U ,0x00000080U) - RegMask = (SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_TM_MISC2_OFFSET ,0x00000080U ,0x00000080U); - /*############################################################################################################################ */ - - /*Register : L2_TM_IQ_ILL1 @ 0XFD4098F8

- - IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS - PSU_SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0 0x1A - - iqpi cal code - (OFFSET, MASK, VALUE) (0XFD4098F8, 0x000000FFU ,0x0000001AU) - RegMask = (SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK | 0 ); - - RegVal = ((0x0000001AU << SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_TM_IQ_ILL1_OFFSET ,0x000000FFU ,0x0000001AU); - /*############################################################################################################################ */ - - /*Register : L2_TM_IQ_ILL2 @ 0XFD4098FC

- - IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 - PSU_SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1 0x1A - - iqpi cal code - (OFFSET, MASK, VALUE) (0XFD4098FC, 0x000000FFU ,0x0000001AU) - RegMask = (SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK | 0 ); - - RegVal = ((0x0000001AU << SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_TM_IQ_ILL2_OFFSET ,0x000000FFU ,0x0000001AU); - /*############################################################################################################################ */ - - /*Register : L2_TM_ILL12 @ 0XFD409990

- - G1A pll ctr bypass value - PSU_SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL 0x10 - - ill pll counter values - (OFFSET, MASK, VALUE) (0XFD409990, 0x000000FFU ,0x00000010U) - RegMask = (SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK | 0 ); - - RegVal = ((0x00000010U << SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_TM_ILL12_OFFSET ,0x000000FFU ,0x00000010U); - /*############################################################################################################################ */ - - /*Register : L2_TM_E_ILL1 @ 0XFD409924

- - E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS - PSU_SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0 0xFE - - epi cal code - (OFFSET, MASK, VALUE) (0XFD409924, 0x000000FFU ,0x000000FEU) - RegMask = (SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK | 0 ); - - RegVal = ((0x000000FEU << SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_TM_E_ILL1_OFFSET ,0x000000FFU ,0x000000FEU); - /*############################################################################################################################ */ - - /*Register : L2_TM_E_ILL2 @ 0XFD409928

- - E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 - PSU_SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1 0x0 - - epi cal code - (OFFSET, MASK, VALUE) (0XFD409928, 0x000000FFU ,0x00000000U) - RegMask = (SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK | 0 ); - - RegVal = ((0x00000000U << SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_TM_E_ILL2_OFFSET ,0x000000FFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : L2_TM_IQ_ILL3 @ 0XFD409900

- - IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 - PSU_SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2 0x1A - - iqpi cal code - (OFFSET, MASK, VALUE) (0XFD409900, 0x000000FFU ,0x0000001AU) - RegMask = (SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK | 0 ); - - RegVal = ((0x0000001AU << SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_TM_IQ_ILL3_OFFSET ,0x000000FFU ,0x0000001AU); - /*############################################################################################################################ */ - - /*Register : L2_TM_E_ILL3 @ 0XFD40992C

- - E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 - PSU_SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2 0x0 - - epi cal code - (OFFSET, MASK, VALUE) (0XFD40992C, 0x000000FFU ,0x00000000U) - RegMask = (SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK | 0 ); - - RegVal = ((0x00000000U << SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_TM_E_ILL3_OFFSET ,0x000000FFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : L2_TM_ILL8 @ 0XFD409980

- - ILL calibration code change wait time - PSU_SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT 0xFF - - ILL cal routine control - (OFFSET, MASK, VALUE) (0XFD409980, 0x000000FFU ,0x000000FFU) - RegMask = (SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_MASK | 0 ); - - RegVal = ((0x000000FFU << SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_TM_ILL8_OFFSET ,0x000000FFU ,0x000000FFU); - /*############################################################################################################################ */ - - /*Register : L2_TM_IQ_ILL8 @ 0XFD409914

- - IQ ILL polytrim bypass value - PSU_SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL 0xF7 - - iqpi polytrim - (OFFSET, MASK, VALUE) (0XFD409914, 0x000000FFU ,0x000000F7U) - RegMask = (SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK | 0 ); - - RegVal = ((0x000000F7U << SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_TM_IQ_ILL8_OFFSET ,0x000000FFU ,0x000000F7U); - /*############################################################################################################################ */ - - /*Register : L2_TM_IQ_ILL9 @ 0XFD409918

- - bypass IQ polytrim - PSU_SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM 0x1 - - enables for lf,constant gm trim and polytirm - (OFFSET, MASK, VALUE) (0XFD409918, 0x00000001U ,0x00000001U) - RegMask = (SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_TM_IQ_ILL9_OFFSET ,0x00000001U ,0x00000001U); - /*############################################################################################################################ */ - - /*Register : L2_TM_E_ILL8 @ 0XFD409940

- - E ILL polytrim bypass value - PSU_SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL 0xF7 - - epi polytrim - (OFFSET, MASK, VALUE) (0XFD409940, 0x000000FFU ,0x000000F7U) - RegMask = (SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK | 0 ); - - RegVal = ((0x000000F7U << SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_TM_E_ILL8_OFFSET ,0x000000FFU ,0x000000F7U); - /*############################################################################################################################ */ - - /*Register : L2_TM_E_ILL9 @ 0XFD409944

- - bypass E polytrim - PSU_SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM 0x1 - - enables for lf,constant gm trim and polytirm - (OFFSET, MASK, VALUE) (0XFD409944, 0x00000001U ,0x00000001U) - RegMask = (SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_TM_E_ILL9_OFFSET ,0x00000001U ,0x00000001U); - /*############################################################################################################################ */ - - /*Register : L3_TM_MISC2 @ 0XFD40D89C

- - ILL calib counts BYPASSED with calcode bits - PSU_SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS 0x1 - - sampler cal - (OFFSET, MASK, VALUE) (0XFD40D89C, 0x00000080U ,0x00000080U) - RegMask = (SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_MISC2_OFFSET ,0x00000080U ,0x00000080U); - /*############################################################################################################################ */ - - /*Register : L3_TM_IQ_ILL1 @ 0XFD40D8F8

- - IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS - PSU_SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0 0x7D - - iqpi cal code - (OFFSET, MASK, VALUE) (0XFD40D8F8, 0x000000FFU ,0x0000007DU) - RegMask = (SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK | 0 ); - - RegVal = ((0x0000007DU << SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_IQ_ILL1_OFFSET ,0x000000FFU ,0x0000007DU); - /*############################################################################################################################ */ - - /*Register : L3_TM_IQ_ILL2 @ 0XFD40D8FC

- - IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 - PSU_SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1 0x7D - - iqpi cal code - (OFFSET, MASK, VALUE) (0XFD40D8FC, 0x000000FFU ,0x0000007DU) - RegMask = (SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK | 0 ); - - RegVal = ((0x0000007DU << SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_IQ_ILL2_OFFSET ,0x000000FFU ,0x0000007DU); - /*############################################################################################################################ */ - - /*Register : L3_TM_ILL12 @ 0XFD40D990

- - G1A pll ctr bypass value - PSU_SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL 0x1 - - ill pll counter values - (OFFSET, MASK, VALUE) (0XFD40D990, 0x000000FFU ,0x00000001U) - RegMask = (SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_ILL12_OFFSET ,0x000000FFU ,0x00000001U); - /*############################################################################################################################ */ - - /*Register : L3_TM_E_ILL1 @ 0XFD40D924

- - E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS - PSU_SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0 0x9C - - epi cal code - (OFFSET, MASK, VALUE) (0XFD40D924, 0x000000FFU ,0x0000009CU) - RegMask = (SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK | 0 ); - - RegVal = ((0x0000009CU << SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_E_ILL1_OFFSET ,0x000000FFU ,0x0000009CU); - /*############################################################################################################################ */ - - /*Register : L3_TM_E_ILL2 @ 0XFD40D928

- - E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 - PSU_SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1 0x39 - - epi cal code - (OFFSET, MASK, VALUE) (0XFD40D928, 0x000000FFU ,0x00000039U) - RegMask = (SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK | 0 ); - - RegVal = ((0x00000039U << SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_E_ILL2_OFFSET ,0x000000FFU ,0x00000039U); - /*############################################################################################################################ */ - - /*Register : L3_TM_ILL11 @ 0XFD40D98C

- - G2A_PCIe1 PLL ctr bypass value - PSU_SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL 0x2 - - ill pll counter values - (OFFSET, MASK, VALUE) (0XFD40D98C, 0x000000F0U ,0x00000020U) - RegMask = (SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_MASK | 0 ); - - RegVal = ((0x00000002U << SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_ILL11_OFFSET ,0x000000F0U ,0x00000020U); - /*############################################################################################################################ */ - - /*Register : L3_TM_IQ_ILL3 @ 0XFD40D900

- - IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 - PSU_SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2 0x7D - - iqpi cal code - (OFFSET, MASK, VALUE) (0XFD40D900, 0x000000FFU ,0x0000007DU) - RegMask = (SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK | 0 ); - - RegVal = ((0x0000007DU << SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_IQ_ILL3_OFFSET ,0x000000FFU ,0x0000007DU); - /*############################################################################################################################ */ - - /*Register : L3_TM_E_ILL3 @ 0XFD40D92C

- - E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 - PSU_SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2 0x64 - - epi cal code - (OFFSET, MASK, VALUE) (0XFD40D92C, 0x000000FFU ,0x00000064U) - RegMask = (SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK | 0 ); - - RegVal = ((0x00000064U << SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_E_ILL3_OFFSET ,0x000000FFU ,0x00000064U); - /*############################################################################################################################ */ - - /*Register : L3_TM_ILL8 @ 0XFD40D980

- - ILL calibration code change wait time - PSU_SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT 0xFF - - ILL cal routine control - (OFFSET, MASK, VALUE) (0XFD40D980, 0x000000FFU ,0x000000FFU) - RegMask = (SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_MASK | 0 ); - - RegVal = ((0x000000FFU << SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_ILL8_OFFSET ,0x000000FFU ,0x000000FFU); - /*############################################################################################################################ */ - - /*Register : L3_TM_IQ_ILL8 @ 0XFD40D914

- - IQ ILL polytrim bypass value - PSU_SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL 0xF7 - - iqpi polytrim - (OFFSET, MASK, VALUE) (0XFD40D914, 0x000000FFU ,0x000000F7U) - RegMask = (SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK | 0 ); - - RegVal = ((0x000000F7U << SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_IQ_ILL8_OFFSET ,0x000000FFU ,0x000000F7U); - /*############################################################################################################################ */ - - /*Register : L3_TM_IQ_ILL9 @ 0XFD40D918

- - bypass IQ polytrim - PSU_SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM 0x1 - - enables for lf,constant gm trim and polytirm - (OFFSET, MASK, VALUE) (0XFD40D918, 0x00000001U ,0x00000001U) - RegMask = (SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_IQ_ILL9_OFFSET ,0x00000001U ,0x00000001U); - /*############################################################################################################################ */ - - /*Register : L3_TM_E_ILL8 @ 0XFD40D940

- - E ILL polytrim bypass value - PSU_SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL 0xF7 - - epi polytrim - (OFFSET, MASK, VALUE) (0XFD40D940, 0x000000FFU ,0x000000F7U) - RegMask = (SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK | 0 ); - - RegVal = ((0x000000F7U << SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_E_ILL8_OFFSET ,0x000000FFU ,0x000000F7U); - /*############################################################################################################################ */ - - /*Register : L3_TM_E_ILL9 @ 0XFD40D944

- - bypass E polytrim - PSU_SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM 0x1 - - enables for lf,constant gm trim and polytirm - (OFFSET, MASK, VALUE) (0XFD40D944, 0x00000001U ,0x00000001U) - RegMask = (SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_E_ILL9_OFFSET ,0x00000001U ,0x00000001U); - /*############################################################################################################################ */ - - // : SYMBOL LOCK AND WAIT - /*Register : L0_TM_DIG_21 @ 0XFD4010A8

- - pre lock comma count threshold. 2'b 00 : 3, 2'b 01 : 5, 2'b 10 : 10, 2'b 11 : 20 - PSU_SERDES_L0_TM_DIG_21_COMMA_PRE_LOCK_THRESH 0x11 - - Control symbol alignment locking - wait counts - (OFFSET, MASK, VALUE) (0XFD4010A8, 0x00000003U ,0x00000003U) - RegMask = (SERDES_L0_TM_DIG_21_COMMA_PRE_LOCK_THRESH_MASK | 0 ); - - RegVal = ((0x00000011U << SERDES_L0_TM_DIG_21_COMMA_PRE_LOCK_THRESH_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_TM_DIG_21_OFFSET ,0x00000003U ,0x00000003U); - /*############################################################################################################################ */ - - /*Register : L0_TM_DIG_10 @ 0XFD40107C

- - CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001 - PSU_SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME 0xF - - test control for changing cdr lock wait time - (OFFSET, MASK, VALUE) (0XFD40107C, 0x0000000FU ,0x0000000FU) - RegMask = (SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK | 0 ); - - RegVal = ((0x0000000FU << SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_TM_DIG_10_OFFSET ,0x0000000FU ,0x0000000FU); - /*############################################################################################################################ */ - - // : SIOU SETTINGS FOR BYPASS CONTROL,HSRX-DIG - /*Register : L0_TM_RST_DLY @ 0XFD4019A4

- - Delay apb reset by specified amount - PSU_SERDES_L0_TM_RST_DLY_APB_RST_DLY 0xFF - - reset delay for apb reset w.r.t pso of hsrx - (OFFSET, MASK, VALUE) (0XFD4019A4, 0x000000FFU ,0x000000FFU) - RegMask = (SERDES_L0_TM_RST_DLY_APB_RST_DLY_MASK | 0 ); - - RegVal = ((0x000000FFU << SERDES_L0_TM_RST_DLY_APB_RST_DLY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_TM_RST_DLY_OFFSET ,0x000000FFU ,0x000000FFU); - /*############################################################################################################################ */ - - /*Register : L0_TM_ANA_BYP_15 @ 0XFD401038

- - Enable Bypass for <7> of TM_ANA_BYPS_15 - PSU_SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE 0x1 - - Bypass control for pcs-pma interface. EQ supplies, main master supply and ps for samp c2c - (OFFSET, MASK, VALUE) (0XFD401038, 0x00000040U ,0x00000040U) - RegMask = (SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_TM_ANA_BYP_15_OFFSET ,0x00000040U ,0x00000040U); - /*############################################################################################################################ */ - - /*Register : L0_TM_ANA_BYP_12 @ 0XFD40102C

- - Enable Bypass for <7> of TM_ANA_BYPS_12 - PSU_SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG 0x1 - - Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr enable controls - (OFFSET, MASK, VALUE) (0XFD40102C, 0x00000040U ,0x00000040U) - RegMask = (SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_TM_ANA_BYP_12_OFFSET ,0x00000040U ,0x00000040U); - /*############################################################################################################################ */ - - /*Register : L1_TM_RST_DLY @ 0XFD4059A4

- - Delay apb reset by specified amount - PSU_SERDES_L1_TM_RST_DLY_APB_RST_DLY 0xFF - - reset delay for apb reset w.r.t pso of hsrx - (OFFSET, MASK, VALUE) (0XFD4059A4, 0x000000FFU ,0x000000FFU) - RegMask = (SERDES_L1_TM_RST_DLY_APB_RST_DLY_MASK | 0 ); - - RegVal = ((0x000000FFU << SERDES_L1_TM_RST_DLY_APB_RST_DLY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L1_TM_RST_DLY_OFFSET ,0x000000FFU ,0x000000FFU); - /*############################################################################################################################ */ - - /*Register : L1_TM_ANA_BYP_15 @ 0XFD405038

- - Enable Bypass for <7> of TM_ANA_BYPS_15 - PSU_SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE 0x1 - - Bypass control for pcs-pma interface. EQ supplies, main master supply and ps for samp c2c - (OFFSET, MASK, VALUE) (0XFD405038, 0x00000040U ,0x00000040U) - RegMask = (SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L1_TM_ANA_BYP_15_OFFSET ,0x00000040U ,0x00000040U); - /*############################################################################################################################ */ - - /*Register : L1_TM_ANA_BYP_12 @ 0XFD40502C

- - Enable Bypass for <7> of TM_ANA_BYPS_12 - PSU_SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG 0x1 - - Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr enable controls - (OFFSET, MASK, VALUE) (0XFD40502C, 0x00000040U ,0x00000040U) - RegMask = (SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L1_TM_ANA_BYP_12_OFFSET ,0x00000040U ,0x00000040U); - /*############################################################################################################################ */ - - /*Register : L2_TM_RST_DLY @ 0XFD4099A4

- - Delay apb reset by specified amount - PSU_SERDES_L2_TM_RST_DLY_APB_RST_DLY 0xFF - - reset delay for apb reset w.r.t pso of hsrx - (OFFSET, MASK, VALUE) (0XFD4099A4, 0x000000FFU ,0x000000FFU) - RegMask = (SERDES_L2_TM_RST_DLY_APB_RST_DLY_MASK | 0 ); - - RegVal = ((0x000000FFU << SERDES_L2_TM_RST_DLY_APB_RST_DLY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_TM_RST_DLY_OFFSET ,0x000000FFU ,0x000000FFU); - /*############################################################################################################################ */ - - /*Register : L2_TM_ANA_BYP_15 @ 0XFD409038

- - Enable Bypass for <7> of TM_ANA_BYPS_15 - PSU_SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE 0x1 - - Bypass control for pcs-pma interface. EQ supplies, main master supply and ps for samp c2c - (OFFSET, MASK, VALUE) (0XFD409038, 0x00000040U ,0x00000040U) - RegMask = (SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_TM_ANA_BYP_15_OFFSET ,0x00000040U ,0x00000040U); - /*############################################################################################################################ */ - - /*Register : L2_TM_ANA_BYP_12 @ 0XFD40902C

- - Enable Bypass for <7> of TM_ANA_BYPS_12 - PSU_SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG 0x1 - - Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr enable controls - (OFFSET, MASK, VALUE) (0XFD40902C, 0x00000040U ,0x00000040U) - RegMask = (SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_TM_ANA_BYP_12_OFFSET ,0x00000040U ,0x00000040U); - /*############################################################################################################################ */ - - /*Register : L3_TM_RST_DLY @ 0XFD40D9A4

- - Delay apb reset by specified amount - PSU_SERDES_L3_TM_RST_DLY_APB_RST_DLY 0xFF - - reset delay for apb reset w.r.t pso of hsrx - (OFFSET, MASK, VALUE) (0XFD40D9A4, 0x000000FFU ,0x000000FFU) - RegMask = (SERDES_L3_TM_RST_DLY_APB_RST_DLY_MASK | 0 ); - - RegVal = ((0x000000FFU << SERDES_L3_TM_RST_DLY_APB_RST_DLY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_RST_DLY_OFFSET ,0x000000FFU ,0x000000FFU); - /*############################################################################################################################ */ - - /*Register : L3_TM_ANA_BYP_15 @ 0XFD40D038

- - Enable Bypass for <7> of TM_ANA_BYPS_15 - PSU_SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE 0x1 - - Bypass control for pcs-pma interface. EQ supplies, main master supply and ps for samp c2c - (OFFSET, MASK, VALUE) (0XFD40D038, 0x00000040U ,0x00000040U) - RegMask = (SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_ANA_BYP_15_OFFSET ,0x00000040U ,0x00000040U); - /*############################################################################################################################ */ - - /*Register : L3_TM_ANA_BYP_12 @ 0XFD40D02C

- - Enable Bypass for <7> of TM_ANA_BYPS_12 - PSU_SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG 0x1 - - Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr enable controls - (OFFSET, MASK, VALUE) (0XFD40D02C, 0x00000040U ,0x00000040U) - RegMask = (SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_ANA_BYP_12_OFFSET ,0x00000040U ,0x00000040U); - /*############################################################################################################################ */ - - // : GT LANE SETTINGS - /*Register : ICM_CFG0 @ 0XFD410010

- - Controls UPHY Lane 0 protocol configuration. 0 - PowerDown, 1 - PCIe .0, 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII0, 6 - Unuse - , 7 - Unused - PSU_SERDES_ICM_CFG0_L0_ICM_CFG 1 - - Controls UPHY Lane 1 protocol configuration. 0 - PowerDown, 1 - PCIe.1, 2 - Sata1, 3 - USB0, 4 - DP.0, 5 - SGMII1, 6 - Unused - 7 - Unused - PSU_SERDES_ICM_CFG0_L1_ICM_CFG 4 - - ICM Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD410010, 0x00000077U ,0x00000041U) - RegMask = (SERDES_ICM_CFG0_L0_ICM_CFG_MASK | SERDES_ICM_CFG0_L1_ICM_CFG_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_ICM_CFG0_L0_ICM_CFG_SHIFT - | 0x00000004U << SERDES_ICM_CFG0_L1_ICM_CFG_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_ICM_CFG0_OFFSET ,0x00000077U ,0x00000041U); - /*############################################################################################################################ */ - - /*Register : ICM_CFG1 @ 0XFD410014

- - Controls UPHY Lane 2 protocol configuration. 0 - PowerDown, 1 - PCIe.1, 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII2, 6 - Unused - 7 - Unused - PSU_SERDES_ICM_CFG1_L2_ICM_CFG 3 - - Controls UPHY Lane 3 protocol configuration. 0 - PowerDown, 1 - PCIe.3, 2 - Sata1, 3 - USB1, 4 - DP.0, 5 - SGMII3, 6 - Unused - 7 - Unused - PSU_SERDES_ICM_CFG1_L3_ICM_CFG 2 - - ICM Configuration Register 1 - (OFFSET, MASK, VALUE) (0XFD410014, 0x00000077U ,0x00000023U) - RegMask = (SERDES_ICM_CFG1_L2_ICM_CFG_MASK | SERDES_ICM_CFG1_L3_ICM_CFG_MASK | 0 ); - - RegVal = ((0x00000003U << SERDES_ICM_CFG1_L2_ICM_CFG_SHIFT - | 0x00000002U << SERDES_ICM_CFG1_L3_ICM_CFG_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_ICM_CFG1_OFFSET ,0x00000077U ,0x00000023U); - /*############################################################################################################################ */ - - // : CHECKING PLL LOCK - // : ENABLE SERIAL DATA MUX DEEMPH - /*Register : L1_TXPMD_TM_45 @ 0XFD404CB4

- - Enable/disable DP post2 path - PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH 0x1 - - Override enable/disable of DP post2 path - PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH 0x1 - - Override enable/disable of DP post1 path - PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH 0x1 - - Enable/disable DP main path - PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH 0x1 - - Override enable/disable of DP main path - PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH 0x1 - - Post or pre or main DP path selection - (OFFSET, MASK, VALUE) (0XFD404CB4, 0x00000037U ,0x00000037U) - RegMask = (SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_MASK | SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_MASK | SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_MASK | SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_MASK | SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_SHIFT - | 0x00000001U << SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_SHIFT - | 0x00000001U << SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_SHIFT - | 0x00000001U << SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_SHIFT - | 0x00000001U << SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L1_TXPMD_TM_45_OFFSET ,0x00000037U ,0x00000037U); - /*############################################################################################################################ */ - - /*Register : L1_TX_ANA_TM_118 @ 0XFD4041D8

- - Test register force for enabling/disablign TX deemphasis bits <17:0> - PSU_SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0 0x1 - - Enable Override of TX deemphasis - (OFFSET, MASK, VALUE) (0XFD4041D8, 0x00000001U ,0x00000001U) - RegMask = (SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L1_TX_ANA_TM_118_OFFSET ,0x00000001U ,0x00000001U); - /*############################################################################################################################ */ - - /*Register : L3_TX_ANA_TM_118 @ 0XFD40C1D8

- - Test register force for enabling/disablign TX deemphasis bits <17:0> - PSU_SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0 0x1 - - Enable Override of TX deemphasis - (OFFSET, MASK, VALUE) (0XFD40C1D8, 0x00000001U ,0x00000001U) - RegMask = (SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TX_ANA_TM_118_OFFSET ,0x00000001U ,0x00000001U); - /*############################################################################################################################ */ - - // : CDR AND RX EQUALIZATION SETTINGS - /*Register : L3_TM_CDR5 @ 0XFD40DC14

- - FPHL FSM accumulate cycles - PSU_SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES 0x7 - - FFL Phase0 int gain aka 2ol SD update rate - PSU_SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN 0x6 - - Fast phase lock controls -- FSM accumulator cycle control and phase 0 int gain control. - (OFFSET, MASK, VALUE) (0XFD40DC14, 0x000000FFU ,0x000000E6U) - RegMask = (SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_MASK | SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_MASK | 0 ); - - RegVal = ((0x00000007U << SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_SHIFT - | 0x00000006U << SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_CDR5_OFFSET ,0x000000FFU ,0x000000E6U); - /*############################################################################################################################ */ - - /*Register : L3_TM_CDR16 @ 0XFD40DC40

- - FFL Phase0 prop gain aka 1ol SD update rate - PSU_SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN 0xC - - Fast phase lock controls -- phase 0 prop gain - (OFFSET, MASK, VALUE) (0XFD40DC40, 0x0000001FU ,0x0000000CU) - RegMask = (SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_MASK | 0 ); - - RegVal = ((0x0000000CU << SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_CDR16_OFFSET ,0x0000001FU ,0x0000000CU); - /*############################################################################################################################ */ - - /*Register : L3_TM_EQ0 @ 0XFD40D94C

- - EQ stg 2 controls BYPASSED - PSU_SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP 1 - - eq stg1 and stg2 controls - (OFFSET, MASK, VALUE) (0XFD40D94C, 0x00000020U ,0x00000020U) - RegMask = (SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_EQ0_OFFSET ,0x00000020U ,0x00000020U); - /*############################################################################################################################ */ - - /*Register : L3_TM_EQ1 @ 0XFD40D950

- - EQ STG2 RL PROG - PSU_SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG 0x2 - - EQ stg 2 preamp mode val - PSU_SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL 0x1 - - eq stg1 and stg2 controls - (OFFSET, MASK, VALUE) (0XFD40D950, 0x00000007U ,0x00000006U) - RegMask = (SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_MASK | SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_MASK | 0 ); - - RegVal = ((0x00000002U << SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_SHIFT - | 0x00000001U << SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_EQ1_OFFSET ,0x00000007U ,0x00000006U); - /*############################################################################################################################ */ - - // : GEM SERDES SETTINGS - // : ENABLE PRE EMPHAIS AND VOLTAGE SWING - /*Register : L1_TXPMD_TM_48 @ 0XFD404CC0

- - Margining factor value - PSU_SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR 0 - - Margining factor - (OFFSET, MASK, VALUE) (0XFD404CC0, 0x0000001FU ,0x00000000U) - RegMask = (SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_MASK | 0 ); - - RegVal = ((0x00000000U << SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L1_TXPMD_TM_48_OFFSET ,0x0000001FU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : L1_TX_ANA_TM_18 @ 0XFD404048

- - pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-emphasis, Others: reserved - PSU_SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0 0 - - Override for PIPE TX de-emphasis - (OFFSET, MASK, VALUE) (0XFD404048, 0x000000FFU ,0x00000000U) - RegMask = (SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK | 0 ); - - RegVal = ((0x00000000U << SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L1_TX_ANA_TM_18_OFFSET ,0x000000FFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : L3_TX_ANA_TM_18 @ 0XFD40C048

- - pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-emphasis, Others: reserved - PSU_SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0 0x1 - - Override for PIPE TX de-emphasis - (OFFSET, MASK, VALUE) (0XFD40C048, 0x000000FFU ,0x00000001U) - RegMask = (SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TX_ANA_TM_18_OFFSET ,0x000000FFU ,0x00000001U); - /*############################################################################################################################ */ - - - return 1; + * TrustZone classification for Ingress Address Translation 7 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_7 1 + + * TrustZone classification for Egress Address Translation 0 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_0 1 + + * TrustZone classification for Egress Address Translation 1 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_1 1 + + * TrustZone classification for Egress Address Translation 2 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_2 1 + + * TrustZone classification for Egress Address Translation 3 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_3 1 + + * TrustZone classification for Egress Address Translation 4 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_4 1 + + * TrustZone classification for Egress Address Translation 5 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_5 1 + + * TrustZone classification for Egress Address Translation 6 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_6 1 + + * TrustZone classification for Egress Address Translation 7 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_7 1 + + * TrustZone classification for DMA Registers + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_REGS 1 + + * TrustZone classification for MSIx Table + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_TABLE 1 + + * TrustZone classification for MSIx PBA + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_PBA 1 + + * TrustZone classification for ECAM + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_ECAM 1 + + * TrustZone classification for Bridge Common Registers + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_BRIDGE_REGS 1 + + * PCIe TrustZone settings. This register may only be modified during bootu + * p (while PCIe block is disabled) + * (OFFSET, MASK, VALUE) (0XFD690030, 0x01FFFFFFU ,0x01FFFFFFU) + */ + PSU_Mask_Write(FPD_SLCR_SECURE_SLCR_PCIE_OFFSET, + 0x01FFFFFFU, 0x01FFFFFFU); +/*##################################################################### */ + + /* + * USB TZ + */ + /* + * Register : slcr_usb @ 0XFF4B0034 + + * TrustZone Classification for USB3_0 + * PSU_LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_0 1 + + * TrustZone Classification for USB3_1 + * PSU_LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_1 1 + + * USB3 TrustZone settings + * (OFFSET, MASK, VALUE) (0XFF4B0034, 0x00000003U ,0x00000003U) + */ + PSU_Mask_Write(LPD_SLCR_SECURE_SLCR_USB_OFFSET, + 0x00000003U, 0x00000003U); +/*##################################################################### */ + + /* + * SD TZ + */ + /* + * Register : IOU_AXI_RPRTCN @ 0XFF240004 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD0_AXI_ARPROT 2 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD1_AXI_ARPROT 2 + + * AXI read protection type selection + * (OFFSET, MASK, VALUE) (0XFF240004, 0x003F0000U ,0x00120000U) + */ + PSU_Mask_Write(IOU_SECURE_SLCR_IOU_AXI_RPRTCN_OFFSET, + 0x003F0000U, 0x00120000U); +/*##################################################################### */ + + /* + * Register : IOU_AXI_WPRTCN @ 0XFF240000 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD0_AXI_AWPROT 2 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD1_AXI_AWPROT 2 + + * AXI write protection type selection + * (OFFSET, MASK, VALUE) (0XFF240000, 0x003F0000U ,0x00120000U) + */ + PSU_Mask_Write(IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET, + 0x003F0000U, 0x00120000U); +/*##################################################################### */ + + /* + * GEM TZ + */ + /* + * Register : IOU_AXI_RPRTCN @ 0XFF240004 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM0_AXI_ARPROT 2 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM1_AXI_ARPROT 2 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM2_AXI_ARPROT 2 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM3_AXI_ARPROT 2 + + * AXI read protection type selection + * (OFFSET, MASK, VALUE) (0XFF240004, 0x00000FFFU ,0x00000492U) + */ + PSU_Mask_Write(IOU_SECURE_SLCR_IOU_AXI_RPRTCN_OFFSET, + 0x00000FFFU, 0x00000492U); +/*##################################################################### */ + + /* + * Register : IOU_AXI_WPRTCN @ 0XFF240000 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM0_AXI_AWPROT 2 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM1_AXI_AWPROT 2 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM2_AXI_AWPROT 2 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM3_AXI_AWPROT 2 + + * AXI write protection type selection + * (OFFSET, MASK, VALUE) (0XFF240000, 0x00000FFFU ,0x00000492U) + */ + PSU_Mask_Write(IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET, + 0x00000FFFU, 0x00000492U); +/*##################################################################### */ + + /* + * QSPI TZ + */ + /* + * Register : IOU_AXI_WPRTCN @ 0XFF240000 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_QSPI_AXI_AWPROT 2 + + * AXI write protection type selection + * (OFFSET, MASK, VALUE) (0XFF240000, 0x0E000000U ,0x04000000U) + */ + PSU_Mask_Write(IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET, + 0x0E000000U, 0x04000000U); +/*##################################################################### */ + + /* + * NAND TZ + */ + /* + * Register : IOU_AXI_RPRTCN @ 0XFF240004 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_RPRTCN_NAND_AXI_ARPROT 2 + + * AXI read protection type selection + * (OFFSET, MASK, VALUE) (0XFF240004, 0x01C00000U ,0x00800000U) + */ + PSU_Mask_Write(IOU_SECURE_SLCR_IOU_AXI_RPRTCN_OFFSET, + 0x01C00000U, 0x00800000U); +/*##################################################################### */ + + /* + * Register : IOU_AXI_WPRTCN @ 0XFF240000 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_NAND_AXI_AWPROT 2 + + * AXI write protection type selection + * (OFFSET, MASK, VALUE) (0XFF240000, 0x01C00000U ,0x00800000U) + */ + PSU_Mask_Write(IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET, + 0x01C00000U, 0x00800000U); +/*##################################################################### */ + + /* + * DMA TZ + */ + /* + * Register : slcr_adma @ 0XFF4B0024 + + * TrustZone Classification for ADMA + * PSU_LPD_SLCR_SECURE_SLCR_ADMA_TZ 0xFF + + * RPU TrustZone settings + * (OFFSET, MASK, VALUE) (0XFF4B0024, 0x000000FFU ,0x000000FFU) + */ + PSU_Mask_Write(LPD_SLCR_SECURE_SLCR_ADMA_OFFSET, + 0x000000FFU, 0x000000FFU); +/*##################################################################### */ + + /* + * Register : slcr_gdma @ 0XFD690050 + + * TrustZone Classification for GDMA + * PSU_FPD_SLCR_SECURE_SLCR_GDMA_TZ 0xFF + + * GDMA Trustzone Settings + * (OFFSET, MASK, VALUE) (0XFD690050, 0x000000FFU ,0x000000FFU) + */ + PSU_Mask_Write(FPD_SLCR_SECURE_SLCR_GDMA_OFFSET, + 0x000000FFU, 0x000000FFU); +/*##################################################################### */ + + + return 1; } -unsigned long psu_resetout_init_data() { - // : TAKING SERDES PERIPHERAL OUT OF RESET RESET - // : PUTTING USB0 IN RESET - /*Register : RST_LPD_TOP @ 0XFF5E023C

+unsigned long psu_serdes_init_data(void) +{ + /* + * SERDES INITIALIZATION + */ + /* + * GT REFERENCE CLOCK SOURCE SELECTION + */ + /* + * Register : PLL_REF_SEL0 @ 0XFD410000 + + * PLL0 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 1 + * 2MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 24MHz, 0x8 - 26MHz, + * 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE + * - 108MHz, 0xF - 125MHz, 0x10 - 135MHz, 0x11 - 150 MHz. 0x12 to 0x1F - R + * eserved + * PSU_SERDES_PLL_REF_SEL0_PLLREFSEL0 0xD + + * PLL0 Reference Selection Register + * (OFFSET, MASK, VALUE) (0XFD410000, 0x0000001FU ,0x0000000DU) + */ + PSU_Mask_Write(SERDES_PLL_REF_SEL0_OFFSET, 0x0000001FU, 0x0000000DU); +/*##################################################################### */ + + /* + * Register : PLL_REF_SEL1 @ 0XFD410004 + + * PLL1 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 1 + * 2MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 24MHz, 0x8 - 26MHz, + * 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE + * - 108MHz, 0xF - 125MHz, 0x10 - 135MHz, 0x11 - 150 MHz. 0x12 to 0x1F - R + * eserved + * PSU_SERDES_PLL_REF_SEL1_PLLREFSEL1 0x9 + + * PLL1 Reference Selection Register + * (OFFSET, MASK, VALUE) (0XFD410004, 0x0000001FU ,0x00000009U) + */ + PSU_Mask_Write(SERDES_PLL_REF_SEL1_OFFSET, 0x0000001FU, 0x00000009U); +/*##################################################################### */ + + /* + * Register : PLL_REF_SEL2 @ 0XFD410008 + + * PLL2 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 1 + * 2MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 24MHz, 0x8 - 26MHz, + * 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE + * - 108MHz, 0xF - 125MHz, 0x10 - 135MHz, 0x11 - 150 MHz. 0x12 to 0x1F - R + * eserved + * PSU_SERDES_PLL_REF_SEL2_PLLREFSEL2 0x8 + + * PLL2 Reference Selection Register + * (OFFSET, MASK, VALUE) (0XFD410008, 0x0000001FU ,0x00000008U) + */ + PSU_Mask_Write(SERDES_PLL_REF_SEL2_OFFSET, 0x0000001FU, 0x00000008U); +/*##################################################################### */ + + /* + * Register : PLL_REF_SEL3 @ 0XFD41000C + + * PLL3 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 1 + * 2MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 24MHz, 0x8 - 26MHz, + * 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE + * - 108MHz, 0xF - 125MHz, 0x10 - 135MHz, 0x11 - 150 MHz. 0x12 to 0x1F - R + * eserved + * PSU_SERDES_PLL_REF_SEL3_PLLREFSEL3 0xF + + * PLL3 Reference Selection Register + * (OFFSET, MASK, VALUE) (0XFD41000C, 0x0000001FU ,0x0000000FU) + */ + PSU_Mask_Write(SERDES_PLL_REF_SEL3_OFFSET, 0x0000001FU, 0x0000000FU); +/*##################################################################### */ + + /* + * GT REFERENCE CLOCK FREQUENCY SELECTION + */ + /* + * Register : L0_L0_REF_CLK_SEL @ 0XFD402860 + + * Sel of lane 0 ref clock local mux. Set to 1 to select lane 0 slicer outp + * ut. Set to 0 to select lane0 ref clock mux output. + * PSU_SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL 0x1 + + * Lane0 Ref Clock Selection Register + * (OFFSET, MASK, VALUE) (0XFD402860, 0x00000080U ,0x00000080U) + */ + PSU_Mask_Write(SERDES_L0_L0_REF_CLK_SEL_OFFSET, + 0x00000080U, 0x00000080U); +/*##################################################################### */ + + /* + * Register : L0_L1_REF_CLK_SEL @ 0XFD402864 + + * Sel of lane 1 ref clock local mux. Set to 1 to select lane 1 slicer outp + * ut. Set to 0 to select lane1 ref clock mux output. + * PSU_SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL 0x0 + + * Bit 3 of lane 1 ref clock mux one hot sel. Set to 1 to select lane 3 sli + * cer output from ref clock network + * PSU_SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3 0x1 + + * Lane1 Ref Clock Selection Register + * (OFFSET, MASK, VALUE) (0XFD402864, 0x00000088U ,0x00000008U) + */ + PSU_Mask_Write(SERDES_L0_L1_REF_CLK_SEL_OFFSET, + 0x00000088U, 0x00000008U); +/*##################################################################### */ + + /* + * Register : L0_L2_REF_CLK_SEL @ 0XFD402868 + + * Sel of lane 2 ref clock local mux. Set to 1 to select lane 1 slicer outp + * ut. Set to 0 to select lane2 ref clock mux output. + * PSU_SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL 0x1 + + * Lane2 Ref Clock Selection Register + * (OFFSET, MASK, VALUE) (0XFD402868, 0x00000080U ,0x00000080U) + */ + PSU_Mask_Write(SERDES_L0_L2_REF_CLK_SEL_OFFSET, + 0x00000080U, 0x00000080U); +/*##################################################################### */ + + /* + * Register : L0_L3_REF_CLK_SEL @ 0XFD40286C + + * Sel of lane 3 ref clock local mux. Set to 1 to select lane 3 slicer outp + * ut. Set to 0 to select lane3 ref clock mux output. + * PSU_SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL 0x0 + + * Bit 1 of lane 3 ref clock mux one hot sel. Set to 1 to select lane 1 sli + * cer output from ref clock network + * PSU_SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1 0x1 + + * Lane3 Ref Clock Selection Register + * (OFFSET, MASK, VALUE) (0XFD40286C, 0x00000082U ,0x00000002U) + */ + PSU_Mask_Write(SERDES_L0_L3_REF_CLK_SEL_OFFSET, + 0x00000082U, 0x00000002U); +/*##################################################################### */ + + /* + * ENABLE SPREAD SPECTRUM + */ + /* + * Register : L2_TM_PLL_DIG_37 @ 0XFD40A094 + + * Enable/Disable coarse code satureation limiting logic + * PSU_SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION 0x1 + + * Test mode register 37 + * (OFFSET, MASK, VALUE) (0XFD40A094, 0x00000010U ,0x00000010U) + */ + PSU_Mask_Write(SERDES_L2_TM_PLL_DIG_37_OFFSET, + 0x00000010U, 0x00000010U); +/*##################################################################### */ + + /* + * Register : L2_PLL_SS_STEPS_0_LSB @ 0XFD40A368 + + * Spread Spectrum No of Steps [7:0] + * PSU_SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB 0x38 + + * Spread Spectrum No of Steps bits 7:0 + * (OFFSET, MASK, VALUE) (0XFD40A368, 0x000000FFU ,0x00000038U) + */ + PSU_Mask_Write(SERDES_L2_PLL_SS_STEPS_0_LSB_OFFSET, + 0x000000FFU, 0x00000038U); +/*##################################################################### */ + + /* + * Register : L2_PLL_SS_STEPS_1_MSB @ 0XFD40A36C + + * Spread Spectrum No of Steps [10:8] + * PSU_SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB 0x03 + + * Spread Spectrum No of Steps bits 10:8 + * (OFFSET, MASK, VALUE) (0XFD40A36C, 0x00000007U ,0x00000003U) + */ + PSU_Mask_Write(SERDES_L2_PLL_SS_STEPS_1_MSB_OFFSET, + 0x00000007U, 0x00000003U); +/*##################################################################### */ + + /* + * Register : L3_PLL_SS_STEPS_0_LSB @ 0XFD40E368 + + * Spread Spectrum No of Steps [7:0] + * PSU_SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB 0xE0 + + * Spread Spectrum No of Steps bits 7:0 + * (OFFSET, MASK, VALUE) (0XFD40E368, 0x000000FFU ,0x000000E0U) + */ + PSU_Mask_Write(SERDES_L3_PLL_SS_STEPS_0_LSB_OFFSET, + 0x000000FFU, 0x000000E0U); +/*##################################################################### */ + + /* + * Register : L3_PLL_SS_STEPS_1_MSB @ 0XFD40E36C + + * Spread Spectrum No of Steps [10:8] + * PSU_SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB 0x3 + + * Spread Spectrum No of Steps bits 10:8 + * (OFFSET, MASK, VALUE) (0XFD40E36C, 0x00000007U ,0x00000003U) + */ + PSU_Mask_Write(SERDES_L3_PLL_SS_STEPS_1_MSB_OFFSET, + 0x00000007U, 0x00000003U); +/*##################################################################### */ + + /* + * Register : L1_PLL_SS_STEPS_0_LSB @ 0XFD406368 + + * Spread Spectrum No of Steps [7:0] + * PSU_SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB 0x58 + + * Spread Spectrum No of Steps bits 7:0 + * (OFFSET, MASK, VALUE) (0XFD406368, 0x000000FFU ,0x00000058U) + */ + PSU_Mask_Write(SERDES_L1_PLL_SS_STEPS_0_LSB_OFFSET, + 0x000000FFU, 0x00000058U); +/*##################################################################### */ + + /* + * Register : L1_PLL_SS_STEPS_1_MSB @ 0XFD40636C + + * Spread Spectrum No of Steps [10:8] + * PSU_SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB 0x3 + + * Spread Spectrum No of Steps bits 10:8 + * (OFFSET, MASK, VALUE) (0XFD40636C, 0x00000007U ,0x00000003U) + */ + PSU_Mask_Write(SERDES_L1_PLL_SS_STEPS_1_MSB_OFFSET, + 0x00000007U, 0x00000003U); +/*##################################################################### */ + + /* + * Register : L1_PLL_SS_STEP_SIZE_0_LSB @ 0XFD406370 + + * Step Size for Spread Spectrum [7:0] + * PSU_SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB 0x7C + + * Step Size for Spread Spectrum LSB + * (OFFSET, MASK, VALUE) (0XFD406370, 0x000000FFU ,0x0000007CU) + */ + PSU_Mask_Write(SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_OFFSET, + 0x000000FFU, 0x0000007CU); +/*##################################################################### */ + + /* + * Register : L1_PLL_SS_STEP_SIZE_1 @ 0XFD406374 + + * Step Size for Spread Spectrum [15:8] + * PSU_SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1 0x33 + + * Step Size for Spread Spectrum 1 + * (OFFSET, MASK, VALUE) (0XFD406374, 0x000000FFU ,0x00000033U) + */ + PSU_Mask_Write(SERDES_L1_PLL_SS_STEP_SIZE_1_OFFSET, + 0x000000FFU, 0x00000033U); +/*##################################################################### */ + + /* + * Register : L1_PLL_SS_STEP_SIZE_2 @ 0XFD406378 + + * Step Size for Spread Spectrum [23:16] + * PSU_SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2 0x2 + + * Step Size for Spread Spectrum 2 + * (OFFSET, MASK, VALUE) (0XFD406378, 0x000000FFU ,0x00000002U) + */ + PSU_Mask_Write(SERDES_L1_PLL_SS_STEP_SIZE_2_OFFSET, + 0x000000FFU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : L1_PLL_SS_STEP_SIZE_3_MSB @ 0XFD40637C + + * Step Size for Spread Spectrum [25:24] + * PSU_SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB 0x0 + + * Enable/Disable test mode force on SS step size + * PSU_SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE 0x1 + + * Enable/Disable test mode force on SS no of steps + * PSU_SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS 0x1 + + * Enable force on enable Spread Spectrum + * (OFFSET, MASK, VALUE) (0XFD40637C, 0x00000033U ,0x00000030U) + */ + PSU_Mask_Write(SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_OFFSET, + 0x00000033U, 0x00000030U); +/*##################################################################### */ + + /* + * Register : L2_PLL_SS_STEP_SIZE_0_LSB @ 0XFD40A370 + + * Step Size for Spread Spectrum [7:0] + * PSU_SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB 0xF4 + + * Step Size for Spread Spectrum LSB + * (OFFSET, MASK, VALUE) (0XFD40A370, 0x000000FFU ,0x000000F4U) + */ + PSU_Mask_Write(SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_OFFSET, + 0x000000FFU, 0x000000F4U); +/*##################################################################### */ + + /* + * Register : L2_PLL_SS_STEP_SIZE_1 @ 0XFD40A374 + + * Step Size for Spread Spectrum [15:8] + * PSU_SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1 0x31 + + * Step Size for Spread Spectrum 1 + * (OFFSET, MASK, VALUE) (0XFD40A374, 0x000000FFU ,0x00000031U) + */ + PSU_Mask_Write(SERDES_L2_PLL_SS_STEP_SIZE_1_OFFSET, + 0x000000FFU, 0x00000031U); +/*##################################################################### */ + + /* + * Register : L2_PLL_SS_STEP_SIZE_2 @ 0XFD40A378 - USB 0 reset for control registers - PSU_CRL_APB_RST_LPD_TOP_USB0_APB_RESET 0X0 + * Step Size for Spread Spectrum [23:16] + * PSU_SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2 0x2 + + * Step Size for Spread Spectrum 2 + * (OFFSET, MASK, VALUE) (0XFD40A378, 0x000000FFU ,0x00000002U) + */ + PSU_Mask_Write(SERDES_L2_PLL_SS_STEP_SIZE_2_OFFSET, + 0x000000FFU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : L2_PLL_SS_STEP_SIZE_3_MSB @ 0XFD40A37C - Software control register for the LPD block. - (OFFSET, MASK, VALUE) (0XFF5E023C, 0x00000400U ,0x00000000U) - RegMask = (CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK | 0 ); + * Step Size for Spread Spectrum [25:24] + * PSU_SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB 0x0 - RegVal = ((0x00000000U << CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RST_LPD_TOP_OFFSET ,0x00000400U ,0x00000000U); - /*############################################################################################################################ */ + * Enable/Disable test mode force on SS step size + * PSU_SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE 0x1 + + * Enable/Disable test mode force on SS no of steps + * PSU_SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS 0x1 + + * Enable force on enable Spread Spectrum + * (OFFSET, MASK, VALUE) (0XFD40A37C, 0x00000033U ,0x00000030U) + */ + PSU_Mask_Write(SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_OFFSET, + 0x00000033U, 0x00000030U); +/*##################################################################### */ - // : USB0 PIPE POWER PRESENT - /*Register : fpd_power_prsnt @ 0XFF9D0080

+ /* + * Register : L3_PLL_SS_STEP_SIZE_0_LSB @ 0XFD40E370 + + * Step Size for Spread Spectrum [7:0] + * PSU_SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB 0xC9 + + * Step Size for Spread Spectrum LSB + * (OFFSET, MASK, VALUE) (0XFD40E370, 0x000000FFU ,0x000000C9U) + */ + PSU_Mask_Write(SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_OFFSET, + 0x000000FFU, 0x000000C9U); +/*##################################################################### */ - This bit is used to choose between PIPE power present and 1'b1 - PSU_USB3_0_FPD_POWER_PRSNT_OPTION 0X1 + /* + * Register : L3_PLL_SS_STEP_SIZE_1 @ 0XFD40E374 - fpd_power_prsnt - (OFFSET, MASK, VALUE) (0XFF9D0080, 0x00000001U ,0x00000001U) - RegMask = (USB3_0_FPD_POWER_PRSNT_OPTION_MASK | 0 ); + * Step Size for Spread Spectrum [15:8] + * PSU_SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1 0xD2 - RegVal = ((0x00000001U << USB3_0_FPD_POWER_PRSNT_OPTION_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (USB3_0_FPD_POWER_PRSNT_OFFSET ,0x00000001U ,0x00000001U); - /*############################################################################################################################ */ + * Step Size for Spread Spectrum 1 + * (OFFSET, MASK, VALUE) (0XFD40E374, 0x000000FFU ,0x000000D2U) + */ + PSU_Mask_Write(SERDES_L3_PLL_SS_STEP_SIZE_1_OFFSET, + 0x000000FFU, 0x000000D2U); +/*##################################################################### */ - /*Register : fpd_pipe_clk @ 0XFF9D007C

+ /* + * Register : L3_PLL_SS_STEP_SIZE_2 @ 0XFD40E378 - This bit is used to choose between PIPE clock coming from SerDes and the suspend clk - PSU_USB3_0_FPD_PIPE_CLK_OPTION 0x0 + * Step Size for Spread Spectrum [23:16] + * PSU_SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2 0x1 - fpd_pipe_clk - (OFFSET, MASK, VALUE) (0XFF9D007C, 0x00000001U ,0x00000000U) - RegMask = (USB3_0_FPD_PIPE_CLK_OPTION_MASK | 0 ); + * Step Size for Spread Spectrum 2 + * (OFFSET, MASK, VALUE) (0XFD40E378, 0x000000FFU ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L3_PLL_SS_STEP_SIZE_2_OFFSET, + 0x000000FFU, 0x00000001U); +/*##################################################################### */ - RegVal = ((0x00000000U << USB3_0_FPD_PIPE_CLK_OPTION_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (USB3_0_FPD_PIPE_CLK_OFFSET ,0x00000001U ,0x00000000U); - /*############################################################################################################################ */ + /* + * Register : L3_PLL_SS_STEP_SIZE_3_MSB @ 0XFD40E37C - // : - /*Register : RST_LPD_TOP @ 0XFF5E023C

+ * Step Size for Spread Spectrum [25:24] + * PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB 0x0 - USB 0 sleep circuit reset - PSU_CRL_APB_RST_LPD_TOP_USB0_HIBERRESET 0X0 + * Enable/Disable test mode force on SS step size + * PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE 0x1 - USB 0 reset - PSU_CRL_APB_RST_LPD_TOP_USB0_CORERESET 0X0 + * Enable/Disable test mode force on SS no of steps + * PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS 0x1 + + * Enable test mode forcing on enable Spread Spectrum + * PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS 0x1 - Software control register for the LPD block. - (OFFSET, MASK, VALUE) (0XFF5E023C, 0x00000140U ,0x00000000U) - RegMask = (CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK | CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK | 0 ); + * Enable force on enable Spread Spectrum + * (OFFSET, MASK, VALUE) (0XFD40E37C, 0x000000B3U ,0x000000B0U) + */ + PSU_Mask_Write(SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_OFFSET, + 0x000000B3U, 0x000000B0U); +/*##################################################################### */ - RegVal = ((0x00000000U << CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT - | 0x00000000U << CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RST_LPD_TOP_OFFSET ,0x00000140U ,0x00000000U); - /*############################################################################################################################ */ + /* + * Register : L2_TM_DIG_6 @ 0XFD40906C - // : PUTTING GEM0 IN RESET - /*Register : RST_LPD_IOU0 @ 0XFF5E0230

+ * Bypass Descrambler + * PSU_SERDES_L2_TM_DIG_6_BYPASS_DESCRAM 0x1 - GEM 3 reset - PSU_CRL_APB_RST_LPD_IOU0_GEM3_RESET 0X0 + * Enable Bypass for <1> TM_DIG_CTRL_6 + * PSU_SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM 0x1 - Software controlled reset for the GEMs - (OFFSET, MASK, VALUE) (0XFF5E0230, 0x00000008U ,0x00000000U) - RegMask = (CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK | 0 ); + * Data path test modes in decoder and descram + * (OFFSET, MASK, VALUE) (0XFD40906C, 0x00000003U ,0x00000003U) + */ + PSU_Mask_Write(SERDES_L2_TM_DIG_6_OFFSET, 0x00000003U, 0x00000003U); +/*##################################################################### */ + + /* + * Register : L2_TX_DIG_TM_61 @ 0XFD4080F4 - RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RST_LPD_IOU0_OFFSET ,0x00000008U ,0x00000000U); - /*############################################################################################################################ */ + * Bypass scrambler signal + * PSU_SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM 0x1 - // : PUTTING SATA IN RESET - /*Register : sata_misc_ctrl @ 0XFD3D0100

+ * Enable/disable scrambler bypass signal + * PSU_SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM 0x1 + + * MPHY PLL Gear and bypass scrambler + * (OFFSET, MASK, VALUE) (0XFD4080F4, 0x00000003U ,0x00000003U) + */ + PSU_Mask_Write(SERDES_L2_TX_DIG_TM_61_OFFSET, + 0x00000003U, 0x00000003U); +/*##################################################################### */ + + /* + * Register : L3_PLL_FBDIV_FRAC_3_MSB @ 0XFD40E360 + + * Enable test mode force on fractional mode enable + * PSU_SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC 0x1 + + * Fractional feedback division control and fractional value for feedback d + * ivision bits 26:24 + * (OFFSET, MASK, VALUE) (0XFD40E360, 0x00000040U ,0x00000040U) + */ + PSU_Mask_Write(SERDES_L3_PLL_FBDIV_FRAC_3_MSB_OFFSET, + 0x00000040U, 0x00000040U); +/*##################################################################### */ - Sata PM clock control select - PSU_SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL 0x3 + /* + * Register : L3_TM_DIG_6 @ 0XFD40D06C + + * Bypass 8b10b decoder + * PSU_SERDES_L3_TM_DIG_6_BYPASS_DECODER 0x1 - Misc Contorls for SATA.This register may only be modified during bootup (while SATA block is disabled) - (OFFSET, MASK, VALUE) (0XFD3D0100, 0x00000003U ,0x00000003U) - RegMask = (SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_MASK | 0 ); + * Enable Bypass for <3> TM_DIG_CTRL_6 + * PSU_SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC 0x1 - RegVal = ((0x00000003U << SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SIOU_SATA_MISC_CTRL_OFFSET ,0x00000003U ,0x00000003U); - /*############################################################################################################################ */ + * Bypass Descrambler + * PSU_SERDES_L3_TM_DIG_6_BYPASS_DESCRAM 0x1 - /*Register : RST_FPD_TOP @ 0XFD1A0100

+ * Enable Bypass for <1> TM_DIG_CTRL_6 + * PSU_SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM 0x1 + + * Data path test modes in decoder and descram + * (OFFSET, MASK, VALUE) (0XFD40D06C, 0x0000000FU ,0x0000000FU) + */ + PSU_Mask_Write(SERDES_L3_TM_DIG_6_OFFSET, 0x0000000FU, 0x0000000FU); +/*##################################################################### */ + + /* + * Register : L3_TX_DIG_TM_61 @ 0XFD40C0F4 + + * Enable/disable encoder bypass signal + * PSU_SERDES_L3_TX_DIG_TM_61_BYPASS_ENC 0x1 + + * Bypass scrambler signal + * PSU_SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM 0x1 + + * Enable/disable scrambler bypass signal + * PSU_SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM 0x1 - Sata block level reset - PSU_CRF_APB_RST_FPD_TOP_SATA_RESET 0X0 - - FPD Block level software controlled reset - (OFFSET, MASK, VALUE) (0XFD1A0100, 0x00000002U ,0x00000000U) - RegMask = (CRF_APB_RST_FPD_TOP_SATA_RESET_MASK | 0 ); - - RegVal = ((0x00000000U << CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_RST_FPD_TOP_OFFSET ,0x00000002U ,0x00000000U); - /*############################################################################################################################ */ - - // : PUTTING PCIE CFG AND BRIDGE IN RESET - /*Register : RST_FPD_TOP @ 0XFD1A0100

- - PCIE config reset - PSU_CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET 0X0 - - PCIE bridge block level reset (AXI interface) - PSU_CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET 0X0 - - FPD Block level software controlled reset - (OFFSET, MASK, VALUE) (0XFD1A0100, 0x000C0000U ,0x00000000U) - RegMask = (CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK | CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK | 0 ); - - RegVal = ((0x00000000U << CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT - | 0x00000000U << CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_RST_FPD_TOP_OFFSET ,0x000C0000U ,0x00000000U); - /*############################################################################################################################ */ - - // : PUTTING DP IN RESET - /*Register : RST_FPD_TOP @ 0XFD1A0100

- - Display Port block level reset (includes DPDMA) - PSU_CRF_APB_RST_FPD_TOP_DP_RESET 0X0 - - FPD Block level software controlled reset - (OFFSET, MASK, VALUE) (0XFD1A0100, 0x00010000U ,0x00000000U) - RegMask = (CRF_APB_RST_FPD_TOP_DP_RESET_MASK | 0 ); - - RegVal = ((0x00000000U << CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_RST_FPD_TOP_OFFSET ,0x00010000U ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : DP_PHY_RESET @ 0XFD4A0200

- - Set to '1' to hold the GT in reset. Clear to release. - PSU_DP_DP_PHY_RESET_GT_RESET 0X0 - - Reset the transmitter PHY. - (OFFSET, MASK, VALUE) (0XFD4A0200, 0x00000002U ,0x00000000U) - RegMask = (DP_DP_PHY_RESET_GT_RESET_MASK | 0 ); - - RegVal = ((0x00000000U << DP_DP_PHY_RESET_GT_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DP_DP_PHY_RESET_OFFSET ,0x00000002U ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : DP_TX_PHY_POWER_DOWN @ 0XFD4A0238

- - Two bits per lane. When set to 11, moves the GT to power down mode. When set to 00, GT will be in active state. bits [1:0] - - ane0 Bits [3:2] - lane 1 - PSU_DP_DP_TX_PHY_POWER_DOWN_POWER_DWN 0X0 - - Control PHY Power down - (OFFSET, MASK, VALUE) (0XFD4A0238, 0x0000000FU ,0x00000000U) - RegMask = (DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK | 0 ); - - RegVal = ((0x00000000U << DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DP_DP_TX_PHY_POWER_DOWN_OFFSET ,0x0000000FU ,0x00000000U); - /*############################################################################################################################ */ - - // : USB0 GFLADJ - /*Register : GUSB2PHYCFG @ 0XFE20C200

- - USB 2.0 Turnaround Time (USBTrdTim) Sets the turnaround time in PHY clocks. Specifies the response time for a MAC request to - he Packet FIFO Controller (PFC) to fetch data from the DFIFO (SPRAM). The following are the required values for the minimum S - C bus frequency of 60 MHz. USB turnaround time is a critical certification criteria when using long cables and five hub level - . The required values for this field: - 4'h5: When the MAC interface is 16-bit UTMI+. - 4'h9: When the MAC interface is 8-bit - UTMI+/ULPI. If SoC bus clock is less than 60 MHz, and USB turnaround time is not critical, this field can be set to a larger - alue. Note: This field is valid only in device mode. - PSU_USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM 0x9 - - Transceiver Delay: Enables a delay between the assertion of the UTMI/ULPI Transceiver Select signal (for HS) and the assertio - of the TxValid signal during a HS Chirp. When this bit is set to 1, a delay (of approximately 2.5 us) is introduced from the - time when the Transceiver Select is set to 2'b00 (HS) to the time the TxValid is driven to 0 for sending the chirp-K. This de - ay is required for some UTMI/ULPI PHYs. Note: - If you enable the hibernation feature when the device core comes out of power - off, you must re-initialize this bit with the appropriate value because the core does not save and restore this bit value dur - ng hibernation. - This bit is valid only in device mode. - PSU_USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY 0x0 - - Enable utmi_sleep_n and utmi_l1_suspend_n (EnblSlpM) The application uses this bit to control utmi_sleep_n and utmi_l1_suspen - _n assertion to the PHY in the L1 state. - 1'b0: utmi_sleep_n and utmi_l1_suspend_n assertion from the core is not transferre - to the external PHY. - 1'b1: utmi_sleep_n and utmi_l1_suspend_n assertion from the core is transferred to the external PHY. - ote: This bit must be set high for Port0 if PHY is used. Note: In Device mode - Before issuing any device endpoint command wh - n operating in 2.0 speeds, disable this bit and enable it after the command completes. Without disabling this bit, if a comma - d is issued when the device is in L1 state and if mac2_clk (utmi_clk/ulpi_clk) is gated off, the command will not get complet - d. - PSU_USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM 0x0 - - USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial Transceiver Select The application uses this bit to select a high-speed P - Y or a full-speed transceiver. - 1'b0: USB 2.0 high-speed UTMI+ or ULPI PHY. This bit is always 0, with Write Only access. - - 'b1: USB 1.1 full-speed serial transceiver. This bit is always 1, with Write Only access. If both interface types are selecte - in coreConsultant (that is, parameters' values are not zero), the application uses this bit to select the active interface i - active, with Read-Write bit access. Note: USB 1.1 full-serial transceiver is not supported. This bit always reads as 1'b0. - PSU_USB3_0_XHCI_GUSB2PHYCFG_PHYSEL 0x0 - - Full-Speed Serial Interface Select (FSIntf) The application uses this bit to select a unidirectional or bidirectional USB 1.1 - full-speed serial transceiver interface. - 1'b0: 6-pin unidirectional full-speed serial interface. This bit is set to 0 with - ead Only access. - 1'b1: 3-pin bidirectional full-speed serial interface. This bit is set to 0 with Read Only access. Note: U - B 1.1 full-speed serial interface is not supported. This bit always reads as 1'b0. - PSU_USB3_0_XHCI_GUSB2PHYCFG_FSINTF 0x0 - - ULPI or UTMI+ Select (ULPI_UTMI_Sel) The application uses this bit to select a UTMI+ or ULPI Interface. - 1'b0: UTMI+ Interfa - e - 1'b1: ULPI Interface This bit is writable only if UTMI+ and ULPI is specified for High-Speed PHY Interface(s) in coreCons - ltant configuration (DWC_USB3_HSPHY_INTERFACE = 3). Otherwise, this bit is read-only and the value depends on the interface s - lected through DWC_USB3_HSPHY_INTERFACE. - PSU_USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL 0x1 - - PHY Interface (PHYIf) If UTMI+ is selected, the application uses this bit to configure the core to support a UTMI+ PHY with a - 8- or 16-bit interface. - 1'b0: 8 bits - 1'b1: 16 bits ULPI Mode: 1'b0 Note: - All the enabled 2.0 ports must have the same - lock frequency as Port0 clock frequency (utmi_clk[0]). - The UTMI 8-bit and 16-bit modes cannot be used together for differen - ports at the same time (that is, all the ports must be in 8-bit mode, or all of them must be in 16-bit mode, at a time). - I - any of the USB 2.0 ports is selected as ULPI port for operation, then all the USB 2.0 ports must be operating at 60 MHz. - PSU_USB3_0_XHCI_GUSB2PHYCFG_PHYIF 0x0 - - HS/FS Timeout Calibration (TOutCal) The number of PHY clocks, as indicated by the application in this field, is multiplied by - a bit-time factor; this factor is added to the high-speed/full-speed interpacket timeout duration in the core to account for - dditional delays introduced by the PHY. This may be required, since the delay introduced by the PHY in generating the linesta - e condition may vary among PHYs. The USB standard timeout value for high-speed operation is 736 to 816 (inclusive) bit times. - The USB standard timeout value for full-speed operation is 16 to 18 (inclusive) bit times. The application must program this - ield based on the speed of connection. The number of bit times added per PHY clock are: High-speed operation: - One 30-MHz PH - clock = 16 bit times - One 60-MHz PHY clock = 8 bit times Full-speed operation: - One 30-MHz PHY clock = 0.4 bit times - One - 60-MHz PHY clock = 0.2 bit times - One 48-MHz PHY clock = 0.25 bit times - PSU_USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL 0x7 - - Global USB2 PHY Configuration Register The application must program this register before starting any transactions on either - he SoC bus or the USB. In Device-only configurations, only one register is needed. In Host mode, per-port registers are imple - ented. - (OFFSET, MASK, VALUE) (0XFE20C200, 0x00003FBFU ,0x00002417U) - RegMask = (USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_MASK | USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_MASK | USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_MASK | USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_MASK | USB3_0_XHCI_GUSB2PHYCFG_FSINTF_MASK | USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_MASK | USB3_0_XHCI_GUSB2PHYCFG_PHYIF_MASK | USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_MASK | 0 ); - - RegVal = ((0x00000009U << USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_SHIFT - | 0x00000000U << USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_SHIFT - | 0x00000000U << USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_SHIFT - | 0x00000000U << USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_SHIFT - | 0x00000000U << USB3_0_XHCI_GUSB2PHYCFG_FSINTF_SHIFT - | 0x00000001U << USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_SHIFT - | 0x00000000U << USB3_0_XHCI_GUSB2PHYCFG_PHYIF_SHIFT - | 0x00000007U << USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (USB3_0_XHCI_GUSB2PHYCFG_OFFSET ,0x00003FBFU ,0x00002417U); - /*############################################################################################################################ */ - - /*Register : GFLADJ @ 0XFE20C630

- - This field indicates the frame length adjustment to be applied when SOF/ITP counter is running on the ref_clk. This register - alue is used to adjust the ITP interval when GCTL[SOFITPSYNC] is set to '1'; SOF and ITP interval when GLADJ.GFLADJ_REFCLK_LP - _SEL is set to '1'. This field must be programmed to a non-zero value only if GFLADJ_REFCLK_LPM_SEL is set to '1' or GCTL.SOF - TPSYNC is set to '1'. The value is derived as follows: FLADJ_REF_CLK_FLADJ=((125000/ref_clk_period_integer)-(125000/ref_clk_p - riod)) * ref_clk_period where - the ref_clk_period_integer is the integer value of the ref_clk period got by truncating the d - cimal (fractional) value that is programmed in the GUCTL.REF_CLK_PERIOD field. - the ref_clk_period is the ref_clk period inc - uding the fractional value. Examples: If the ref_clk is 24 MHz then - GUCTL.REF_CLK_PERIOD = 41 - GFLADJ.GLADJ_REFCLK_FLADJ = - ((125000/41)-(125000/41.6666))*41.6666 = 2032 (ignoring the fractional value) If the ref_clk is 48 MHz then - GUCTL.REF_CLK_P - RIOD = 20 - GFLADJ.GLADJ_REFCLK_FLADJ = ((125000/20)-(125000/20.8333))*20.8333 = 5208 (ignoring the fractional value) - PSU_USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ 0x0 - - Global Frame Length Adjustment Register This register provides options for the software to control the core behavior with res - ect to SOF (Start of Frame) and ITP (Isochronous Timestamp Packet) timers and frame timer functionality. It provides an optio - to override the fladj_30mhz_reg sideband signal. In addition, it enables running SOF or ITP frame timer counters completely - rom the ref_clk. This facilitates hardware LPM in host mode with the SOF or ITP counters being run from the ref_clk signal. - (OFFSET, MASK, VALUE) (0XFE20C630, 0x003FFF00U ,0x00000000U) - RegMask = (USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_MASK | 0 ); - - RegVal = ((0x00000000U << USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (USB3_0_XHCI_GFLADJ_OFFSET ,0x003FFF00U ,0x00000000U); - /*############################################################################################################################ */ - - // : UPDATING TWO PCIE REGISTERS DEFAULT VALUES, AS THESE REGISTERS HAVE INCORRECT RESET VALUES IN SILICON. - /*Register : ATTR_25 @ 0XFD480064

- - If TRUE Completion Timeout Disable is supported. This is required to be TRUE for Endpoint and either setting allowed for Root - ports. Drives Device Capability 2 [4]; EP=0x0001; RP=0x0001 - PSU_PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED 0X1 - - ATTR_25 - (OFFSET, MASK, VALUE) (0XFD480064, 0x00000200U ,0x00000200U) - RegMask = (PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_MASK | 0 ); - - RegVal = ((0x00000001U << PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_25_OFFSET ,0x00000200U ,0x00000200U); - /*############################################################################################################################ */ - - // : PCIE SETTINGS - /*Register : ATTR_7 @ 0XFD48001C

- - Specifies mask/settings for Base Address Register (BAR) 0. If BAR is not to be implemented, set to 32'h00000000. Bits are def - ned as follows: Memory Space BAR [0] = Mem Space Indicator (set to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = - Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory a - erture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR1,BAR0\'7d to 1. IO Space BAR 0] = IO Space Indicator - set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o apert - re size in bytes.; EP=0x0004; RP=0x0000 - PSU_PCIE_ATTRIB_ATTR_7_ATTR_BAR0 0x0 - - ATTR_7 - (OFFSET, MASK, VALUE) (0XFD48001C, 0x0000FFFFU ,0x00000000U) - RegMask = (PCIE_ATTRIB_ATTR_7_ATTR_BAR0_MASK | 0 ); - - RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_7_ATTR_BAR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_7_OFFSET ,0x0000FFFFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : ATTR_8 @ 0XFD480020

- - Specifies mask/settings for Base Address Register (BAR) 0. If BAR is not to be implemented, set to 32'h00000000. Bits are def - ned as follows: Memory Space BAR [0] = Mem Space Indicator (set to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = - Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory a - erture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR1,BAR0\'7d to 1. IO Space BAR 0] = IO Space Indicator - set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o apert - re size in bytes.; EP=0xFFF0; RP=0x0000 - PSU_PCIE_ATTRIB_ATTR_8_ATTR_BAR0 0x0 - - ATTR_8 - (OFFSET, MASK, VALUE) (0XFD480020, 0x0000FFFFU ,0x00000000U) - RegMask = (PCIE_ATTRIB_ATTR_8_ATTR_BAR0_MASK | 0 ); - - RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_8_ATTR_BAR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_8_OFFSET ,0x0000FFFFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : ATTR_9 @ 0XFD480024

- - Specifies mask/settings for Base Address Register (BAR) 1 if BAR0 is a 32-bit BAR, or the upper bits of \'7bBAR1,BAR0\'7d if - AR0 is a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR0 description if this functions as the uppe - bits of a 64-bit BAR. Bits are defined as follows: Memory Space BAR (not upper bits of BAR0) [0] = Mem Space Indicator (set - o 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if - 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of - '7bBAR2,BAR1\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable b - ts of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000 - PSU_PCIE_ATTRIB_ATTR_9_ATTR_BAR1 0x0 - - ATTR_9 - (OFFSET, MASK, VALUE) (0XFD480024, 0x0000FFFFU ,0x00000000U) - RegMask = (PCIE_ATTRIB_ATTR_9_ATTR_BAR1_MASK | 0 ); - - RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_9_ATTR_BAR1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_9_OFFSET ,0x0000FFFFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : ATTR_10 @ 0XFD480028

- - Specifies mask/settings for Base Address Register (BAR) 1 if BAR0 is a 32-bit BAR, or the upper bits of \'7bBAR1,BAR0\'7d if - AR0 is a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR0 description if this functions as the uppe - bits of a 64-bit BAR. Bits are defined as follows: Memory Space BAR (not upper bits of BAR0) [0] = Mem Space Indicator (set - o 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if - 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of - '7bBAR2,BAR1\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable b - ts of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000 - PSU_PCIE_ATTRIB_ATTR_10_ATTR_BAR1 0x0 - - ATTR_10 - (OFFSET, MASK, VALUE) (0XFD480028, 0x0000FFFFU ,0x00000000U) - RegMask = (PCIE_ATTRIB_ATTR_10_ATTR_BAR1_MASK | 0 ); - - RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_10_ATTR_BAR1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_10_OFFSET ,0x0000FFFFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : ATTR_11 @ 0XFD48002C

- - For an endpoint, specifies mask/settings for Base Address Register (BAR) 2 if BAR1 is a 32-bit BAR, or the upper bits of \'7b - AR2,BAR1\'7d if BAR1 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR1 descri - tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to 00FF_FFFF. For an endpoin - , bits are defined as follows: Memory Space BAR (not upper bits of BAR1) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi - ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe - most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR3,BAR2\'7d to - . IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper - ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0x0004; RP=0xFFFF - PSU_PCIE_ATTRIB_ATTR_11_ATTR_BAR2 0xFFFF - - ATTR_11 - (OFFSET, MASK, VALUE) (0XFD48002C, 0x0000FFFFU ,0x0000FFFFU) - RegMask = (PCIE_ATTRIB_ATTR_11_ATTR_BAR2_MASK | 0 ); - - RegVal = ((0x0000FFFFU << PCIE_ATTRIB_ATTR_11_ATTR_BAR2_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_11_OFFSET ,0x0000FFFFU ,0x0000FFFFU); - /*############################################################################################################################ */ - - /*Register : ATTR_12 @ 0XFD480030

- - For an endpoint, specifies mask/settings for Base Address Register (BAR) 2 if BAR1 is a 32-bit BAR, or the upper bits of \'7b - AR2,BAR1\'7d if BAR1 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR1 descri - tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to 00FF_FFFF. For an endpoin - , bits are defined as follows: Memory Space BAR (not upper bits of BAR1) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi - ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe - most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR3,BAR2\'7d to - . IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper - ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFF0; RP=0x00FF - PSU_PCIE_ATTRIB_ATTR_12_ATTR_BAR2 0xFF - - ATTR_12 - (OFFSET, MASK, VALUE) (0XFD480030, 0x0000FFFFU ,0x000000FFU) - RegMask = (PCIE_ATTRIB_ATTR_12_ATTR_BAR2_MASK | 0 ); - - RegVal = ((0x000000FFU << PCIE_ATTRIB_ATTR_12_ATTR_BAR2_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_12_OFFSET ,0x0000FFFFU ,0x000000FFU); - /*############################################################################################################################ */ - - /*Register : ATTR_13 @ 0XFD480034

- - For an endpoint, specifies mask/settings for Base Address Register (BAR) 3 if BAR2 is a 32-bit BAR, or the upper bits of \'7b - AR3,BAR2\'7d if BAR2 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR2 descri - tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: FFFF_0000 = IO Limit/Bas - Registers not implemented FFFF_F0F0 = IO Limit/Base Registers use 16-bit decode FFFF_F1F1 = IO Limit/Base Registers use 32-b - t decode For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of BAR2) [0] = Mem Space Indicator (s - t to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; - if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits - f \'7bBAR4,BAR3\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writabl - bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000 - PSU_PCIE_ATTRIB_ATTR_13_ATTR_BAR3 0x0 - - ATTR_13 - (OFFSET, MASK, VALUE) (0XFD480034, 0x0000FFFFU ,0x00000000U) - RegMask = (PCIE_ATTRIB_ATTR_13_ATTR_BAR3_MASK | 0 ); - - RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_13_ATTR_BAR3_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_13_OFFSET ,0x0000FFFFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : ATTR_14 @ 0XFD480038

- - For an endpoint, specifies mask/settings for Base Address Register (BAR) 3 if BAR2 is a 32-bit BAR, or the upper bits of \'7b - AR3,BAR2\'7d if BAR2 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR2 descri - tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: FFFF_0000 = IO Limit/Bas - Registers not implemented FFFF_F0F0 = IO Limit/Base Registers use 16-bit decode FFFF_F1F1 = IO Limit/Base Registers use 32-b - t decode For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of BAR2) [0] = Mem Space Indicator (s - t to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; - if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits - f \'7bBAR4,BAR3\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writabl - bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0xFFFF - PSU_PCIE_ATTRIB_ATTR_14_ATTR_BAR3 0xFFFF - - ATTR_14 - (OFFSET, MASK, VALUE) (0XFD480038, 0x0000FFFFU ,0x0000FFFFU) - RegMask = (PCIE_ATTRIB_ATTR_14_ATTR_BAR3_MASK | 0 ); - - RegVal = ((0x0000FFFFU << PCIE_ATTRIB_ATTR_14_ATTR_BAR3_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_14_OFFSET ,0x0000FFFFU ,0x0000FFFFU); - /*############################################################################################################################ */ - - /*Register : ATTR_15 @ 0XFD48003C

- - For an endpoint, specifies mask/settings for Base Address Register (BAR) 4 if BAR3 is a 32-bit BAR, or the upper bits of \'7b - AR4,BAR3\'7d if BAR3 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR3 descri - tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to FFF0_FFF0. For an endpoin - , bits are defined as follows: Memory Space BAR (not upper bits of BAR3) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi - ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe - most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR5,BAR4\'7d to - . IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper - ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0x0004; RP=0xFFF0 - PSU_PCIE_ATTRIB_ATTR_15_ATTR_BAR4 0xFFF0 - - ATTR_15 - (OFFSET, MASK, VALUE) (0XFD48003C, 0x0000FFFFU ,0x0000FFF0U) - RegMask = (PCIE_ATTRIB_ATTR_15_ATTR_BAR4_MASK | 0 ); - - RegVal = ((0x0000FFF0U << PCIE_ATTRIB_ATTR_15_ATTR_BAR4_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_15_OFFSET ,0x0000FFFFU ,0x0000FFF0U); - /*############################################################################################################################ */ - - /*Register : ATTR_16 @ 0XFD480040

- - For an endpoint, specifies mask/settings for Base Address Register (BAR) 4 if BAR3 is a 32-bit BAR, or the upper bits of \'7b - AR4,BAR3\'7d if BAR3 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR3 descri - tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to FFF0_FFF0. For an endpoin - , bits are defined as follows: Memory Space BAR (not upper bits of BAR3) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi - ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe - most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR5,BAR4\'7d to - . IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper - ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFF0; RP=0xFFF0 - PSU_PCIE_ATTRIB_ATTR_16_ATTR_BAR4 0xFFF0 - - ATTR_16 - (OFFSET, MASK, VALUE) (0XFD480040, 0x0000FFFFU ,0x0000FFF0U) - RegMask = (PCIE_ATTRIB_ATTR_16_ATTR_BAR4_MASK | 0 ); - - RegVal = ((0x0000FFF0U << PCIE_ATTRIB_ATTR_16_ATTR_BAR4_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_16_OFFSET ,0x0000FFFFU ,0x0000FFF0U); - /*############################################################################################################################ */ - - /*Register : ATTR_17 @ 0XFD480044

- - For an endpoint, specifies mask/settings for Base Address Register (BAR) 5 if BAR4 is a 32-bit BAR, or the upper bits of \'7b - AR5,BAR4\'7d if BAR4 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR4 descri - tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: 0000_0000 = Prefetchable - Memory Limit/Base Registers not implemented FFF0_FFF0 = 32-bit Prefetchable Memory Limit/Base implemented FFF1_FFF1 = 64-bit - refetchable Memory Limit/Base implemented For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of B - R4) [0] = Mem Space Indicator (set to 0) [2:1] = Type field (00 for 32-bit; BAR5 cannot be lower part of a 64-bit BAR) [3] = - refetchable (0 or 1) [31:4] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=memory aperture size in - ytes. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set u - permost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0xFFF1 - PSU_PCIE_ATTRIB_ATTR_17_ATTR_BAR5 0xFFF1 - - ATTR_17 - (OFFSET, MASK, VALUE) (0XFD480044, 0x0000FFFFU ,0x0000FFF1U) - RegMask = (PCIE_ATTRIB_ATTR_17_ATTR_BAR5_MASK | 0 ); - - RegVal = ((0x0000FFF1U << PCIE_ATTRIB_ATTR_17_ATTR_BAR5_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_17_OFFSET ,0x0000FFFFU ,0x0000FFF1U); - /*############################################################################################################################ */ - - /*Register : ATTR_18 @ 0XFD480048

- - For an endpoint, specifies mask/settings for Base Address Register (BAR) 5 if BAR4 is a 32-bit BAR, or the upper bits of \'7b - AR5,BAR4\'7d if BAR4 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR4 descri - tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: 0000_0000 = Prefetchable - Memory Limit/Base Registers not implemented FFF0_FFF0 = 32-bit Prefetchable Memory Limit/Base implemented FFF1_FFF1 = 64-bit - refetchable Memory Limit/Base implemented For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of B - R4) [0] = Mem Space Indicator (set to 0) [2:1] = Type field (00 for 32-bit; BAR5 cannot be lower part of a 64-bit BAR) [3] = - refetchable (0 or 1) [31:4] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=memory aperture size in - ytes. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set u - permost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0xFFF1 - PSU_PCIE_ATTRIB_ATTR_18_ATTR_BAR5 0xFFF1 - - ATTR_18 - (OFFSET, MASK, VALUE) (0XFD480048, 0x0000FFFFU ,0x0000FFF1U) - RegMask = (PCIE_ATTRIB_ATTR_18_ATTR_BAR5_MASK | 0 ); - - RegVal = ((0x0000FFF1U << PCIE_ATTRIB_ATTR_18_ATTR_BAR5_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_18_OFFSET ,0x0000FFFFU ,0x0000FFF1U); - /*############################################################################################################################ */ - - /*Register : ATTR_27 @ 0XFD48006C

- - Specifies maximum payload supported. Valid settings are: 0- 128 bytes, 1- 256 bytes, 2- 512 bytes, 3- 1024 bytes. Transferred - to the Device Capabilities register. The values: 4-2048 bytes, 5- 4096 bytes are not supported; EP=0x0001; RP=0x0001 - PSU_PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED 1 - - Endpoint L1 Acceptable Latency. Records the latency that the endpoint can withstand on transitions from L1 state to L0 (if L1 - state supported). Valid settings are: 0h less than 1us, 1h 1 to 2us, 2h 2 to 4us, 3h 4 to 8us, 4h 8 to 16us, 5h 16 to 32us, 6 - 32 to 64us, 7h more than 64us. For Endpoints only. Must be 0h for other devices.; EP=0x0007; RP=0x0000 - PSU_PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY 0x0 - - ATTR_27 - (OFFSET, MASK, VALUE) (0XFD48006C, 0x00000738U ,0x00000100U) - RegMask = (PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_MASK | PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_MASK | 0 ); - - RegVal = ((0x00000001U << PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_SHIFT - | 0x00000000U << PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_27_OFFSET ,0x00000738U ,0x00000100U); - /*############################################################################################################################ */ - - /*Register : ATTR_50 @ 0XFD4800C8

- - Identifies the type of device/port as follows: 0000b PCI Express Endpoint device, 0001b Legacy PCI Express Endpoint device, 0 - 00b Root Port of PCI Express Root Complex, 0101b Upstream Port of PCI Express Switch, 0110b Downstream Port of PCI Express Sw - tch, 0111b PCIE Express to PCI/PCI-X Bridge, 1000b PCI/PCI-X to PCI Express Bridge. Transferred to PCI Express Capabilities r - gister. Must be consistent with IS_SWITCH and UPSTREAM_FACING settings.; EP=0x0000; RP=0x0004 - PSU_PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE 4 - - PCIe Capability's Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capab - lity.; EP=0x009C; RP=0x0000 - PSU_PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR 0 - - ATTR_50 - (OFFSET, MASK, VALUE) (0XFD4800C8, 0x0000FFF0U ,0x00000040U) - RegMask = (PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_MASK | PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_MASK | 0 ); - - RegVal = ((0x00000004U << PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_SHIFT - | 0x00000000U << PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_50_OFFSET ,0x0000FFF0U ,0x00000040U); - /*############################################################################################################################ */ - - /*Register : ATTR_105 @ 0XFD4801A4

- - Number of credits that should be advertised for Completion data received on Virtual Channel 0. The bytes advertised must be l - ss than or equal to the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0172; RP=0x00CD - PSU_PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD 0xCD - - ATTR_105 - (OFFSET, MASK, VALUE) (0XFD4801A4, 0x000007FFU ,0x000000CDU) - RegMask = (PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_MASK | 0 ); - - RegVal = ((0x000000CDU << PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_105_OFFSET ,0x000007FFU ,0x000000CDU); - /*############################################################################################################################ */ - - /*Register : ATTR_106 @ 0XFD4801A8

- - Number of credits that should be advertised for Completion headers received on Virtual Channel 0. The sum of the posted, non - osted, and completion header credits must be <= 80; EP=0x0048; RP=0x0024 - PSU_PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH 0x24 - - Number of credits that should be advertised for Non-Posted headers received on Virtual Channel 0. The number of non posted da - a credits advertised by the block is equal to the number of non posted header credits. The sum of the posted, non posted, and - completion header credits must be <= 80; EP=0x0004; RP=0x000C - PSU_PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH 0xC - - ATTR_106 - (OFFSET, MASK, VALUE) (0XFD4801A8, 0x00003FFFU ,0x00000624U) - RegMask = (PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_MASK | PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_MASK | 0 ); - - RegVal = ((0x00000024U << PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_SHIFT - | 0x0000000CU << PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_106_OFFSET ,0x00003FFFU ,0x00000624U); - /*############################################################################################################################ */ - - /*Register : ATTR_107 @ 0XFD4801AC

- - Number of credits that should be advertised for Non-Posted data received on Virtual Channel 0. The number of non posted data - redits advertised by the block is equal to two times the number of non posted header credits if atomic operations are support - d or is equal to the number of non posted header credits if atomic operations are not supported. The bytes advertised must be - less than or equal to the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0008; RP=0x0018 - PSU_PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD 0x18 - - ATTR_107 - (OFFSET, MASK, VALUE) (0XFD4801AC, 0x000007FFU ,0x00000018U) - RegMask = (PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_MASK | 0 ); - - RegVal = ((0x00000018U << PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_107_OFFSET ,0x000007FFU ,0x00000018U); - /*############################################################################################################################ */ - - /*Register : ATTR_108 @ 0XFD4801B0

- - Number of credits that should be advertised for Posted data received on Virtual Channel 0. The bytes advertised must be less - han or equal to the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0020; RP=0x00B5 - PSU_PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD 0xB5 - - ATTR_108 - (OFFSET, MASK, VALUE) (0XFD4801B0, 0x000007FFU ,0x000000B5U) - RegMask = (PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_MASK | 0 ); - - RegVal = ((0x000000B5U << PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_108_OFFSET ,0x000007FFU ,0x000000B5U); - /*############################################################################################################################ */ - - /*Register : ATTR_109 @ 0XFD4801B4

- - Not currently in use. Invert ECRC generated by block when trn_tecrc_gen_n and trn_terrfwd_n are asserted.; EP=0x0000; RP=0x00 - 0 - PSU_PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV 0x0 - - Enables td bit clear and ECRC trim on received TLP's FALSE == don't trim TRUE == trim.; EP=0x0001; RP=0x0001 - PSU_PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM 0x1 - - Enables ECRC check on received TLP's 0 == don't check 1 == always check 3 == check if enabled by ECRC check enable bit of AER - cap structure; EP=0x0003; RP=0x0003 - PSU_PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK 0x3 - - Index of last packet buffer used by TX TLM (i.e. number of buffers - 1). Calculated from max payload size supported and the n - mber of brams configured for transmit; EP=0x001C; RP=0x001C - PSU_PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET 0x1c - - Number of credits that should be advertised for Posted headers received on Virtual Channel 0. The sum of the posted, non post - d, and completion header credits must be <= 80; EP=0x0004; RP=0x0020 - PSU_PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH 0x20 - - ATTR_109 - (OFFSET, MASK, VALUE) (0XFD4801B4, 0x0000FFFFU ,0x00007E20U) - RegMask = (PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_MASK | PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_MASK | PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_MASK | PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_MASK | PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_MASK | 0 ); - - RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_SHIFT - | 0x00000001U << PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_SHIFT - | 0x00000003U << PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_SHIFT - | 0x0000001CU << PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_SHIFT - | 0x00000020U << PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_109_OFFSET ,0x0000FFFFU ,0x00007E20U); - /*############################################################################################################################ */ - - /*Register : ATTR_34 @ 0XFD480088

- - Specifies values to be transferred to Header Type register. Bit 7 should be set to '0' indicating single-function device. Bit - 0 identifies header as Type 0 or Type 1, with '0' indicating a Type 0 header.; EP=0x0000; RP=0x0001 - PSU_PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE 0x1 - - ATTR_34 - (OFFSET, MASK, VALUE) (0XFD480088, 0x000000FFU ,0x00000001U) - RegMask = (PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_MASK | 0 ); - - RegVal = ((0x00000001U << PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_34_OFFSET ,0x000000FFU ,0x00000001U); - /*############################################################################################################################ */ - - /*Register : ATTR_53 @ 0XFD4800D4

- - PM Capability's Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capabil - ty.; EP=0x0048; RP=0x0060 - PSU_PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR 0x60 - - ATTR_53 - (OFFSET, MASK, VALUE) (0XFD4800D4, 0x000000FFU ,0x00000060U) - RegMask = (PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_MASK | 0 ); - - RegVal = ((0x00000060U << PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_53_OFFSET ,0x000000FFU ,0x00000060U); - /*############################################################################################################################ */ - - /*Register : ATTR_41 @ 0XFD4800A4

- - MSI Per-Vector Masking Capable. The value is transferred to the MSI Control Register[8]. When set, adds Mask and Pending Dwor - to Cap structure; EP=0x0000; RP=0x0000 - PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE 0x0 - - Indicates that the MSI structures exists. If this is FALSE, then the MSI structure cannot be accessed via either the link or - he management port.; EP=0x0001; RP=0x0000 - PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON 0 - - MSI Capability's Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capabi - ity.; EP=0x0060; RP=0x0000 - PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR 0x0 - - Indicates that the MSI structures exists. If this is FALSE, then the MSI structure cannot be accessed via either the link or - he management port.; EP=0x0001; RP=0x0000 - PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON 0 - - ATTR_41 - (OFFSET, MASK, VALUE) (0XFD4800A4, 0x000003FFU ,0x00000000U) - RegMask = (PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_MASK | PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_MASK | PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_MASK | PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_MASK | 0 ); - - RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_SHIFT - | 0x00000000U << PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_SHIFT - | 0x00000000U << PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_SHIFT - | 0x00000000U << PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_41_OFFSET ,0x000003FFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : ATTR_97 @ 0XFD480184

- - Maximum Link Width. Valid settings are: 000001b x1, 000010b x2, 000100b x4, 001000b x8.; EP=0x0004; RP=0x0004 - PSU_PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH 0x1 - - Used by LTSSM to set Maximum Link Width. Valid settings are: 000001b [x1], 000010b [x2], 000100b [x4], 001000b [x8].; EP=0x00 - 4; RP=0x0004 - PSU_PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH 0x1 - - ATTR_97 - (OFFSET, MASK, VALUE) (0XFD480184, 0x00000FFFU ,0x00000041U) - RegMask = (PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_MASK | PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_MASK | 0 ); - - RegVal = ((0x00000001U << PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_SHIFT - | 0x00000001U << PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_97_OFFSET ,0x00000FFFU ,0x00000041U); - /*############################################################################################################################ */ - - /*Register : ATTR_100 @ 0XFD480190

- - TRUE specifies upstream-facing port. FALSE specifies downstream-facing port.; EP=0x0001; RP=0x0000 - PSU_PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING 0x0 - - ATTR_100 - (OFFSET, MASK, VALUE) (0XFD480190, 0x00000040U ,0x00000000U) - RegMask = (PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_MASK | 0 ); - - RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_100_OFFSET ,0x00000040U ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : ATTR_101 @ 0XFD480194

- - Enable the routing of message TLPs to the user through the TRN RX interface. A bit value of 1 enables routing of the message - LP to the user. Messages are always decoded by the message decoder. Bit 0 - ERR COR, Bit 1 - ERR NONFATAL, Bit 2 - ERR FATAL, - Bit 3 - INTA Bit 4 - INTB, Bit 5 - INTC, Bit 6 - INTD, Bit 7 PM_PME, Bit 8 - PME_TO_ACK, Bit 9 - unlock, Bit 10 PME_Turn_Off; - EP=0x0000; RP=0x07FF - PSU_PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE 0x7FF - - Disable BAR filtering. Does not change the behavior of the bar hit outputs; EP=0x0000; RP=0x0001 - PSU_PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING 0x1 - - ATTR_101 - (OFFSET, MASK, VALUE) (0XFD480194, 0x0000FFE2U ,0x0000FFE2U) - RegMask = (PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_MASK | PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_MASK | 0 ); - - RegVal = ((0x000007FFU << PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_SHIFT - | 0x00000001U << PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_101_OFFSET ,0x0000FFE2U ,0x0000FFE2U); - /*############################################################################################################################ */ - - /*Register : ATTR_37 @ 0XFD480094

- - Link Bandwidth notification capability. Indicates support for the link bandwidth notification status and interrupt mechanism. - Required for Root.; EP=0x0000; RP=0x0001 - PSU_PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP 0x1 - - Sets the ASPM Optionality Compliance bit, to comply with the 2.1 ASPM Optionality ECN. Transferred to the Link Capabilities r - gister.; EP=0x0001; RP=0x0001 - PSU_PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY 0x1 - - ATTR_37 - (OFFSET, MASK, VALUE) (0XFD480094, 0x00004200U ,0x00004200U) - RegMask = (PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_MASK | PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_MASK | 0 ); - - RegVal = ((0x00000001U << PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_SHIFT - | 0x00000001U << PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_37_OFFSET ,0x00004200U ,0x00004200U); - /*############################################################################################################################ */ - - /*Register : ATTR_93 @ 0XFD480174

- - Enables the Replay Timer to use the user-defined LL_REPLAY_TIMEOUT value (or combined with the built-in value, depending on L - _REPLAY_TIMEOUT_FUNC). If FALSE, the built-in value is used.; EP=0x0000; RP=0x0000 - PSU_PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN 0x1 - - Sets a user-defined timeout for the Replay Timer to force cause the retransmission of unacknowledged TLPs; refer to LL_REPLAY - TIMEOUT_EN and LL_REPLAY_TIMEOUT_FUNC to see how this value is used. The unit for this attribute is in symbol times, which is - 4ns at GEN1 speeds and 2ns at GEN2.; EP=0x0000; RP=0x0000 - PSU_PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT 0x1000 - - ATTR_93 - (OFFSET, MASK, VALUE) (0XFD480174, 0x0000FFFFU ,0x00009000U) - RegMask = (PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_MASK | PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_MASK | 0 ); - - RegVal = ((0x00000001U << PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_SHIFT - | 0x00001000U << PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_93_OFFSET ,0x0000FFFFU ,0x00009000U); - /*############################################################################################################################ */ - - /*Register : ID @ 0XFD480200

- - Device ID for the the PCIe Cap Structure Device ID field - PSU_PCIE_ATTRIB_ID_CFG_DEV_ID 0xd021 - - Vendor ID for the PCIe Cap Structure Vendor ID field - PSU_PCIE_ATTRIB_ID_CFG_VEND_ID 0x10ee - - ID - (OFFSET, MASK, VALUE) (0XFD480200, 0xFFFFFFFFU ,0x10EED021U) - RegMask = (PCIE_ATTRIB_ID_CFG_DEV_ID_MASK | PCIE_ATTRIB_ID_CFG_VEND_ID_MASK | 0 ); - - RegVal = ((0x0000D021U << PCIE_ATTRIB_ID_CFG_DEV_ID_SHIFT - | 0x000010EEU << PCIE_ATTRIB_ID_CFG_VEND_ID_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ID_OFFSET ,0xFFFFFFFFU ,0x10EED021U); - /*############################################################################################################################ */ - - /*Register : SUBSYS_ID @ 0XFD480204

- - Subsystem ID for the the PCIe Cap Structure Subsystem ID field - PSU_PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID 0x7 - - Subsystem Vendor ID for the PCIe Cap Structure Subsystem Vendor ID field - PSU_PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID 0x10ee - - SUBSYS_ID - (OFFSET, MASK, VALUE) (0XFD480204, 0xFFFFFFFFU ,0x10EE0007U) - RegMask = (PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_MASK | PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_MASK | 0 ); - - RegVal = ((0x00000007U << PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_SHIFT - | 0x000010EEU << PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_SUBSYS_ID_OFFSET ,0xFFFFFFFFU ,0x10EE0007U); - /*############################################################################################################################ */ - - /*Register : REV_ID @ 0XFD480208

- - Revision ID for the the PCIe Cap Structure - PSU_PCIE_ATTRIB_REV_ID_CFG_REV_ID 0x0 - - REV_ID - (OFFSET, MASK, VALUE) (0XFD480208, 0x000000FFU ,0x00000000U) - RegMask = (PCIE_ATTRIB_REV_ID_CFG_REV_ID_MASK | 0 ); - - RegVal = ((0x00000000U << PCIE_ATTRIB_REV_ID_CFG_REV_ID_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_REV_ID_OFFSET ,0x000000FFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : ATTR_24 @ 0XFD480060

- - Code identifying basic function, subclass and applicable programming interface. Transferred to the Class Code register.; EP=0 - 8000; RP=0x8000 - PSU_PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE 0x400 - - ATTR_24 - (OFFSET, MASK, VALUE) (0XFD480060, 0x0000FFFFU ,0x00000400U) - RegMask = (PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_MASK | 0 ); - - RegVal = ((0x00000400U << PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_24_OFFSET ,0x0000FFFFU ,0x00000400U); - /*############################################################################################################################ */ - - /*Register : ATTR_25 @ 0XFD480064

- - Code identifying basic function, subclass and applicable programming interface. Transferred to the Class Code register.; EP=0 - 0005; RP=0x0006 - PSU_PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE 0x6 - - INTX Interrupt Generation Capable. If FALSE, this will cause Command[10] to be hardwired to 0.; EP=0x0001; RP=0x0001 - PSU_PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED 0 - - ATTR_25 - (OFFSET, MASK, VALUE) (0XFD480064, 0x000001FFU ,0x00000006U) - RegMask = (PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_MASK | PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_MASK | 0 ); - - RegVal = ((0x00000006U << PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_SHIFT - | 0x00000000U << PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_25_OFFSET ,0x000001FFU ,0x00000006U); - /*############################################################################################################################ */ - - /*Register : ATTR_4 @ 0XFD480010

- - Indicates that the AER structures exists. If this is FALSE, then the AER structure cannot be accessed via either the link or - he management port, and AER will be considered to not be present for error management tasks (such as what types of error mess - ges are sent if an error is detected).; EP=0x0001; RP=0x0001 - PSU_PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON 0 - - Indicates that the AER structures exists. If this is FALSE, then the AER structure cannot be accessed via either the link or - he management port, and AER will be considered to not be present for error management tasks (such as what types of error mess - ges are sent if an error is detected).; EP=0x0001; RP=0x0001 - PSU_PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON 0 - - ATTR_4 - (OFFSET, MASK, VALUE) (0XFD480010, 0x00001000U ,0x00000000U) - RegMask = (PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_MASK | PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_MASK | 0 ); - - RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_SHIFT - | 0x00000000U << PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_4_OFFSET ,0x00001000U ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : ATTR_89 @ 0XFD480164

- - VSEC's Next Capability Offset pointer to the next item in the capabilities list, or 000h if this is the final capability.; EP - 0x0140; RP=0x0140 - PSU_PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR 0 - - ATTR_89 - (OFFSET, MASK, VALUE) (0XFD480164, 0x00001FFEU ,0x00000000U) - RegMask = (PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_MASK | 0 ); - - RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_89_OFFSET ,0x00001FFEU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : ATTR_79 @ 0XFD48013C

- - CRS SW Visibility. Indicates RC can return CRS to SW. Transferred to the Root Capabilities register.; EP=0x0000; RP=0x0000 - PSU_PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY 1 - - ATTR_79 - (OFFSET, MASK, VALUE) (0XFD48013C, 0x00000020U ,0x00000020U) - RegMask = (PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_MASK | 0 ); - - RegVal = ((0x00000001U << PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_79_OFFSET ,0x00000020U ,0x00000020U); - /*############################################################################################################################ */ - - /*Register : ATTR_43 @ 0XFD4800AC

- - Indicates that the MSIX structures exists. If this is FALSE, then the MSIX structure cannot be accessed via either the link o - the management port.; EP=0x0001; RP=0x0000 - PSU_PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON 0 - - ATTR_43 - (OFFSET, MASK, VALUE) (0XFD4800AC, 0x00000100U ,0x00000000U) - RegMask = (PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_MASK | 0 ); - - RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_43_OFFSET ,0x00000100U ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : ATTR_48 @ 0XFD4800C0

- - MSI-X Table Size. This value is transferred to the MSI-X Message Control[10:0] field. Set to 0 if MSI-X is not enabled. Note - hat the core does not implement the table; that must be implemented in user logic.; EP=0x0003; RP=0x0000 - PSU_PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE 0 - - ATTR_48 - (OFFSET, MASK, VALUE) (0XFD4800C0, 0x000007FFU ,0x00000000U) - RegMask = (PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_MASK | 0 ); - - RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_48_OFFSET ,0x000007FFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : ATTR_46 @ 0XFD4800B8

- - MSI-X Table Offset. This value is transferred to the MSI-X Table Offset field. Set to 0 if MSI-X is not enabled.; EP=0x0001; - P=0x0000 - PSU_PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET 0 - - ATTR_46 - (OFFSET, MASK, VALUE) (0XFD4800B8, 0x0000FFFFU ,0x00000000U) - RegMask = (PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_MASK | 0 ); - - RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_46_OFFSET ,0x0000FFFFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : ATTR_47 @ 0XFD4800BC

- - MSI-X Table Offset. This value is transferred to the MSI-X Table Offset field. Set to 0 if MSI-X is not enabled.; EP=0x0000; - P=0x0000 - PSU_PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET 0 - - ATTR_47 - (OFFSET, MASK, VALUE) (0XFD4800BC, 0x00001FFFU ,0x00000000U) - RegMask = (PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_MASK | 0 ); - - RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_47_OFFSET ,0x00001FFFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : ATTR_44 @ 0XFD4800B0

- - MSI-X Pending Bit Array Offset This value is transferred to the MSI-X PBA Offset field. Set to 0 if MSI-X is not enabled.; EP - 0x0001; RP=0x0000 - PSU_PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET 0 - - ATTR_44 - (OFFSET, MASK, VALUE) (0XFD4800B0, 0x0000FFFFU ,0x00000000U) - RegMask = (PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_MASK | 0 ); - - RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_44_OFFSET ,0x0000FFFFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : ATTR_45 @ 0XFD4800B4

- - MSI-X Pending Bit Array Offset This value is transferred to the MSI-X PBA Offset field. Set to 0 if MSI-X is not enabled.; EP - 0x1000; RP=0x0000 - PSU_PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET 0 - - ATTR_45 - (OFFSET, MASK, VALUE) (0XFD4800B4, 0x0000FFF8U ,0x00000000U) - RegMask = (PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_MASK | 0 ); - - RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_45_OFFSET ,0x0000FFF8U ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : CB @ 0XFD48031C

- - DT837748 Enable - PSU_PCIE_ATTRIB_CB_CB1 0x0 - - ECO Register 1 - (OFFSET, MASK, VALUE) (0XFD48031C, 0x00000002U ,0x00000000U) - RegMask = (PCIE_ATTRIB_CB_CB1_MASK | 0 ); - - RegVal = ((0x00000000U << PCIE_ATTRIB_CB_CB1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_CB_OFFSET ,0x00000002U ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : ATTR_35 @ 0XFD48008C

- - Active State PM Support. Indicates the level of active state power management supported by the selected PCI Express Link, enc - ded as follows: 0 Reserved, 1 L0s entry supported, 2 Reserved, 3 L0s and L1 entry supported.; EP=0x0001; RP=0x0001 - PSU_PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT 0x0 - - ATTR_35 - (OFFSET, MASK, VALUE) (0XFD48008C, 0x00003000U ,0x00000000U) - RegMask = (PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_MASK | 0 ); - - RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_35_OFFSET ,0x00003000U ,0x00000000U); - /*############################################################################################################################ */ - - // : PUTTING PCIE CONTROL IN RESET - /*Register : RST_FPD_TOP @ 0XFD1A0100

- - PCIE control block level reset - PSU_CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET 0X0 - - FPD Block level software controlled reset - (OFFSET, MASK, VALUE) (0XFD1A0100, 0x00020000U ,0x00000000U) - RegMask = (CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK | 0 ); - - RegVal = ((0x00000000U << CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_RST_FPD_TOP_OFFSET ,0x00020000U ,0x00000000U); - /*############################################################################################################################ */ - - // : CHECK PLL LOCK FOR LANE0 - /*Register : L0_PLL_STATUS_READ_1 @ 0XFD4023E4

- - Status Read value of PLL Lock - PSU_SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1 - (OFFSET, MASK, VALUE) (0XFD4023E4, 0x00000010U ,0x00000010U) */ - mask_poll(SERDES_L0_PLL_STATUS_READ_1_OFFSET,0x00000010U); - - /*############################################################################################################################ */ - - // : CHECK PLL LOCK FOR LANE1 - /*Register : L1_PLL_STATUS_READ_1 @ 0XFD4063E4

- - Status Read value of PLL Lock - PSU_SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1 - (OFFSET, MASK, VALUE) (0XFD4063E4, 0x00000010U ,0x00000010U) */ - mask_poll(SERDES_L1_PLL_STATUS_READ_1_OFFSET,0x00000010U); - - /*############################################################################################################################ */ - - // : CHECK PLL LOCK FOR LANE2 - /*Register : L2_PLL_STATUS_READ_1 @ 0XFD40A3E4

- - Status Read value of PLL Lock - PSU_SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1 - (OFFSET, MASK, VALUE) (0XFD40A3E4, 0x00000010U ,0x00000010U) */ - mask_poll(SERDES_L2_PLL_STATUS_READ_1_OFFSET,0x00000010U); - - /*############################################################################################################################ */ - - // : CHECK PLL LOCK FOR LANE3 - /*Register : L3_PLL_STATUS_READ_1 @ 0XFD40E3E4

- - Status Read value of PLL Lock - PSU_SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1 - (OFFSET, MASK, VALUE) (0XFD40E3E4, 0x00000010U ,0x00000010U) */ - mask_poll(SERDES_L3_PLL_STATUS_READ_1_OFFSET,0x00000010U); - - /*############################################################################################################################ */ - - // : SATA AHCI VENDOR SETTING - /*Register : PP2C @ 0XFD0C00AC

- - CIBGMN: COMINIT Burst Gap Minimum. - PSU_SATA_AHCI_VENDOR_PP2C_CIBGMN 0x18 - - CIBGMX: COMINIT Burst Gap Maximum. - PSU_SATA_AHCI_VENDOR_PP2C_CIBGMX 0x40 - - CIBGN: COMINIT Burst Gap Nominal. - PSU_SATA_AHCI_VENDOR_PP2C_CIBGN 0x18 - - CINMP: COMINIT Negate Minimum Period. - PSU_SATA_AHCI_VENDOR_PP2C_CINMP 0x28 - - PP2C - Port Phy2Cfg Register. This register controls the configuration of the Phy Control OOB timing for the COMINIT paramete - s for either Port 0 or Port 1. The Port configured is controlled by the value programmed into the Port Config Register. - (OFFSET, MASK, VALUE) (0XFD0C00AC, 0xFFFFFFFFU ,0x28184018U) - RegMask = (SATA_AHCI_VENDOR_PP2C_CIBGMN_MASK | SATA_AHCI_VENDOR_PP2C_CIBGMX_MASK | SATA_AHCI_VENDOR_PP2C_CIBGN_MASK | SATA_AHCI_VENDOR_PP2C_CINMP_MASK | 0 ); - - RegVal = ((0x00000018U << SATA_AHCI_VENDOR_PP2C_CIBGMN_SHIFT - | 0x00000040U << SATA_AHCI_VENDOR_PP2C_CIBGMX_SHIFT - | 0x00000018U << SATA_AHCI_VENDOR_PP2C_CIBGN_SHIFT - | 0x00000028U << SATA_AHCI_VENDOR_PP2C_CINMP_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SATA_AHCI_VENDOR_PP2C_OFFSET ,0xFFFFFFFFU ,0x28184018U); - /*############################################################################################################################ */ - - /*Register : PP3C @ 0XFD0C00B0

- - CWBGMN: COMWAKE Burst Gap Minimum. - PSU_SATA_AHCI_VENDOR_PP3C_CWBGMN 0x06 - - CWBGMX: COMWAKE Burst Gap Maximum. - PSU_SATA_AHCI_VENDOR_PP3C_CWBGMX 0x14 - - CWBGN: COMWAKE Burst Gap Nominal. - PSU_SATA_AHCI_VENDOR_PP3C_CWBGN 0x08 - - CWNMP: COMWAKE Negate Minimum Period. - PSU_SATA_AHCI_VENDOR_PP3C_CWNMP 0x0E - - PP3C - Port Phy3CfgRegister. This register controls the configuration of the Phy Control OOB timing for the COMWAKE parameter - for either Port 0 or Port 1. The Port configured is controlled by the value programmed into the Port Config Register. - (OFFSET, MASK, VALUE) (0XFD0C00B0, 0xFFFFFFFFU ,0x0E081406U) - RegMask = (SATA_AHCI_VENDOR_PP3C_CWBGMN_MASK | SATA_AHCI_VENDOR_PP3C_CWBGMX_MASK | SATA_AHCI_VENDOR_PP3C_CWBGN_MASK | SATA_AHCI_VENDOR_PP3C_CWNMP_MASK | 0 ); - - RegVal = ((0x00000006U << SATA_AHCI_VENDOR_PP3C_CWBGMN_SHIFT - | 0x00000014U << SATA_AHCI_VENDOR_PP3C_CWBGMX_SHIFT - | 0x00000008U << SATA_AHCI_VENDOR_PP3C_CWBGN_SHIFT - | 0x0000000EU << SATA_AHCI_VENDOR_PP3C_CWNMP_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SATA_AHCI_VENDOR_PP3C_OFFSET ,0xFFFFFFFFU ,0x0E081406U); - /*############################################################################################################################ */ - - /*Register : PP4C @ 0XFD0C00B4

- - BMX: COM Burst Maximum. - PSU_SATA_AHCI_VENDOR_PP4C_BMX 0x13 - - BNM: COM Burst Nominal. - PSU_SATA_AHCI_VENDOR_PP4C_BNM 0x08 - - SFD: Signal Failure Detection, if the signal detection de-asserts for a time greater than this then the OOB detector will det - rmine this is a line idle and cause the PhyInit state machine to exit the Phy Ready State. A value of zero disables the Signa - Failure Detector. The value is based on the OOB Detector Clock typically (PMCLK Clock Period) * SFD giving a nominal time of - 500ns based on a 150MHz PMCLK. - PSU_SATA_AHCI_VENDOR_PP4C_SFD 0x4A - - PTST: Partial to Slumber timer value, specific delay the controller should apply while in partial before entering slumber. Th - value is bases on the system clock divided by 128, total delay = (Sys Clock Period) * PTST * 128 - PSU_SATA_AHCI_VENDOR_PP4C_PTST 0x06 - - PP4C - Port Phy4Cfg Register. This register controls the configuration of the Phy Control Burst timing for the COM parameters - for either Port 0 or Port 1. The Port configured is controlled by the value programmed into the Port Config Register. - (OFFSET, MASK, VALUE) (0XFD0C00B4, 0xFFFFFFFFU ,0x064A0813U) - RegMask = (SATA_AHCI_VENDOR_PP4C_BMX_MASK | SATA_AHCI_VENDOR_PP4C_BNM_MASK | SATA_AHCI_VENDOR_PP4C_SFD_MASK | SATA_AHCI_VENDOR_PP4C_PTST_MASK | 0 ); - - RegVal = ((0x00000013U << SATA_AHCI_VENDOR_PP4C_BMX_SHIFT - | 0x00000008U << SATA_AHCI_VENDOR_PP4C_BNM_SHIFT - | 0x0000004AU << SATA_AHCI_VENDOR_PP4C_SFD_SHIFT - | 0x00000006U << SATA_AHCI_VENDOR_PP4C_PTST_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SATA_AHCI_VENDOR_PP4C_OFFSET ,0xFFFFFFFFU ,0x064A0813U); - /*############################################################################################################################ */ - - /*Register : PP5C @ 0XFD0C00B8

- - RIT: Retry Interval Timer. The calculated value divided by two, the lower digit of precision is not needed. - PSU_SATA_AHCI_VENDOR_PP5C_RIT 0xC96A4 - - RCT: Rate Change Timer, a value based on the 54.2us for which a SATA device will transmit at a fixed rate ALIGNp after OOB ha - completed, for a fast SERDES it is suggested that this value be 54.2us / 4 - PSU_SATA_AHCI_VENDOR_PP5C_RCT 0x3FF - - PP5C - Port Phy5Cfg Register. This register controls the configuration of the Phy Control Retry Interval timing for either Po - t 0 or Port 1. The Port configured is controlled by the value programmed into the Port Config Register. - (OFFSET, MASK, VALUE) (0XFD0C00B8, 0xFFFFFFFFU ,0x3FFC96A4U) - RegMask = (SATA_AHCI_VENDOR_PP5C_RIT_MASK | SATA_AHCI_VENDOR_PP5C_RCT_MASK | 0 ); - - RegVal = ((0x000C96A4U << SATA_AHCI_VENDOR_PP5C_RIT_SHIFT - | 0x000003FFU << SATA_AHCI_VENDOR_PP5C_RCT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SATA_AHCI_VENDOR_PP5C_OFFSET ,0xFFFFFFFFU ,0x3FFC96A4U); - /*############################################################################################################################ */ - - - return 1; + * MPHY PLL Gear and bypass scrambler + * (OFFSET, MASK, VALUE) (0XFD40C0F4, 0x0000000BU ,0x0000000BU) + */ + PSU_Mask_Write(SERDES_L3_TX_DIG_TM_61_OFFSET, + 0x0000000BU, 0x0000000BU); +/*##################################################################### */ + + /* + * ENABLE CHICKEN BIT FOR PCIE AND USB + */ + /* + * Register : L0_TM_AUX_0 @ 0XFD4010CC + + * Spare- not used + * PSU_SERDES_L0_TM_AUX_0_BIT_2 1 + + * Spare registers + * (OFFSET, MASK, VALUE) (0XFD4010CC, 0x00000020U ,0x00000020U) + */ + PSU_Mask_Write(SERDES_L0_TM_AUX_0_OFFSET, 0x00000020U, 0x00000020U); +/*##################################################################### */ + + /* + * Register : L2_TM_AUX_0 @ 0XFD4090CC + + * Spare- not used + * PSU_SERDES_L2_TM_AUX_0_BIT_2 1 + + * Spare registers + * (OFFSET, MASK, VALUE) (0XFD4090CC, 0x00000020U ,0x00000020U) + */ + PSU_Mask_Write(SERDES_L2_TM_AUX_0_OFFSET, 0x00000020U, 0x00000020U); +/*##################################################################### */ + + /* + * ENABLING EYE SURF + */ + /* + * Register : L0_TM_DIG_8 @ 0XFD401074 + + * Enable Eye Surf + * PSU_SERDES_L0_TM_DIG_8_EYESURF_ENABLE 0x1 + + * Test modes for Elastic buffer and enabling Eye Surf + * (OFFSET, MASK, VALUE) (0XFD401074, 0x00000010U ,0x00000010U) + */ + PSU_Mask_Write(SERDES_L0_TM_DIG_8_OFFSET, 0x00000010U, 0x00000010U); +/*##################################################################### */ + + /* + * Register : L1_TM_DIG_8 @ 0XFD405074 + + * Enable Eye Surf + * PSU_SERDES_L1_TM_DIG_8_EYESURF_ENABLE 0x1 + + * Test modes for Elastic buffer and enabling Eye Surf + * (OFFSET, MASK, VALUE) (0XFD405074, 0x00000010U ,0x00000010U) + */ + PSU_Mask_Write(SERDES_L1_TM_DIG_8_OFFSET, 0x00000010U, 0x00000010U); +/*##################################################################### */ + + /* + * Register : L2_TM_DIG_8 @ 0XFD409074 + + * Enable Eye Surf + * PSU_SERDES_L2_TM_DIG_8_EYESURF_ENABLE 0x1 + + * Test modes for Elastic buffer and enabling Eye Surf + * (OFFSET, MASK, VALUE) (0XFD409074, 0x00000010U ,0x00000010U) + */ + PSU_Mask_Write(SERDES_L2_TM_DIG_8_OFFSET, 0x00000010U, 0x00000010U); +/*##################################################################### */ + + /* + * Register : L3_TM_DIG_8 @ 0XFD40D074 + + * Enable Eye Surf + * PSU_SERDES_L3_TM_DIG_8_EYESURF_ENABLE 0x1 + + * Test modes for Elastic buffer and enabling Eye Surf + * (OFFSET, MASK, VALUE) (0XFD40D074, 0x00000010U ,0x00000010U) + */ + PSU_Mask_Write(SERDES_L3_TM_DIG_8_OFFSET, 0x00000010U, 0x00000010U); +/*##################################################################### */ + + /* + * ILL SETTINGS FOR GAIN AND LOCK SETTINGS + */ + /* + * Register : L0_TM_MISC2 @ 0XFD40189C + + * ILL calib counts BYPASSED with calcode bits + * PSU_SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS 0x1 + + * sampler cal + * (OFFSET, MASK, VALUE) (0XFD40189C, 0x00000080U ,0x00000080U) + */ + PSU_Mask_Write(SERDES_L0_TM_MISC2_OFFSET, 0x00000080U, 0x00000080U); +/*##################################################################### */ + + /* + * Register : L0_TM_IQ_ILL1 @ 0XFD4018F8 + + * IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , + * USB3 : SS + * PSU_SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0 0x64 + + * iqpi cal code + * (OFFSET, MASK, VALUE) (0XFD4018F8, 0x000000FFU ,0x00000064U) + */ + PSU_Mask_Write(SERDES_L0_TM_IQ_ILL1_OFFSET, + 0x000000FFU, 0x00000064U); +/*##################################################################### */ + + /* + * Register : L0_TM_IQ_ILL2 @ 0XFD4018FC + + * IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 + * PSU_SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1 0x64 + + * iqpi cal code + * (OFFSET, MASK, VALUE) (0XFD4018FC, 0x000000FFU ,0x00000064U) + */ + PSU_Mask_Write(SERDES_L0_TM_IQ_ILL2_OFFSET, + 0x000000FFU, 0x00000064U); +/*##################################################################### */ + + /* + * Register : L0_TM_ILL12 @ 0XFD401990 + + * G1A pll ctr bypass value + * PSU_SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL 0x11 + + * ill pll counter values + * (OFFSET, MASK, VALUE) (0XFD401990, 0x000000FFU ,0x00000011U) + */ + PSU_Mask_Write(SERDES_L0_TM_ILL12_OFFSET, 0x000000FFU, 0x00000011U); +/*##################################################################### */ + + /* + * Register : L0_TM_E_ILL1 @ 0XFD401924 + + * E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , U + * SB3 : SS + * PSU_SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0 0x4 + + * epi cal code + * (OFFSET, MASK, VALUE) (0XFD401924, 0x000000FFU ,0x00000004U) + */ + PSU_Mask_Write(SERDES_L0_TM_E_ILL1_OFFSET, 0x000000FFU, 0x00000004U); +/*##################################################################### */ + + /* + * Register : L0_TM_E_ILL2 @ 0XFD401928 + + * E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 + * PSU_SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1 0xFE + + * epi cal code + * (OFFSET, MASK, VALUE) (0XFD401928, 0x000000FFU ,0x000000FEU) + */ + PSU_Mask_Write(SERDES_L0_TM_E_ILL2_OFFSET, 0x000000FFU, 0x000000FEU); +/*##################################################################### */ + + /* + * Register : L0_TM_IQ_ILL3 @ 0XFD401900 + + * IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 + * PSU_SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2 0x64 + + * iqpi cal code + * (OFFSET, MASK, VALUE) (0XFD401900, 0x000000FFU ,0x00000064U) + */ + PSU_Mask_Write(SERDES_L0_TM_IQ_ILL3_OFFSET, + 0x000000FFU, 0x00000064U); +/*##################################################################### */ + + /* + * Register : L0_TM_E_ILL3 @ 0XFD40192C + + * E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 + * PSU_SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2 0x0 + + * epi cal code + * (OFFSET, MASK, VALUE) (0XFD40192C, 0x000000FFU ,0x00000000U) + */ + PSU_Mask_Write(SERDES_L0_TM_E_ILL3_OFFSET, 0x000000FFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : L0_TM_ILL8 @ 0XFD401980 + + * ILL calibration code change wait time + * PSU_SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT 0xFF + + * ILL cal routine control + * (OFFSET, MASK, VALUE) (0XFD401980, 0x000000FFU ,0x000000FFU) + */ + PSU_Mask_Write(SERDES_L0_TM_ILL8_OFFSET, 0x000000FFU, 0x000000FFU); +/*##################################################################### */ + + /* + * Register : L0_TM_IQ_ILL8 @ 0XFD401914 + + * IQ ILL polytrim bypass value + * PSU_SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL 0xF7 + + * iqpi polytrim + * (OFFSET, MASK, VALUE) (0XFD401914, 0x000000FFU ,0x000000F7U) + */ + PSU_Mask_Write(SERDES_L0_TM_IQ_ILL8_OFFSET, + 0x000000FFU, 0x000000F7U); +/*##################################################################### */ + + /* + * Register : L0_TM_IQ_ILL9 @ 0XFD401918 + + * bypass IQ polytrim + * PSU_SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM 0x1 + + * enables for lf,constant gm trim and polytirm + * (OFFSET, MASK, VALUE) (0XFD401918, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L0_TM_IQ_ILL9_OFFSET, + 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : L0_TM_E_ILL8 @ 0XFD401940 + + * E ILL polytrim bypass value + * PSU_SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL 0xF7 + + * epi polytrim + * (OFFSET, MASK, VALUE) (0XFD401940, 0x000000FFU ,0x000000F7U) + */ + PSU_Mask_Write(SERDES_L0_TM_E_ILL8_OFFSET, 0x000000FFU, 0x000000F7U); +/*##################################################################### */ + + /* + * Register : L0_TM_E_ILL9 @ 0XFD401944 + + * bypass E polytrim + * PSU_SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM 0x1 + + * enables for lf,constant gm trim and polytirm + * (OFFSET, MASK, VALUE) (0XFD401944, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L0_TM_E_ILL9_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : L0_TM_ILL13 @ 0XFD401994 + + * ILL cal idle val refcnt + * PSU_SERDES_L0_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT 0x7 + + * ill cal idle value count + * (OFFSET, MASK, VALUE) (0XFD401994, 0x00000007U ,0x00000007U) + */ + PSU_Mask_Write(SERDES_L0_TM_ILL13_OFFSET, 0x00000007U, 0x00000007U); +/*##################################################################### */ + + /* + * Register : L1_TM_ILL13 @ 0XFD405994 + + * ILL cal idle val refcnt + * PSU_SERDES_L1_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT 0x7 + + * ill cal idle value count + * (OFFSET, MASK, VALUE) (0XFD405994, 0x00000007U ,0x00000007U) + */ + PSU_Mask_Write(SERDES_L1_TM_ILL13_OFFSET, 0x00000007U, 0x00000007U); +/*##################################################################### */ + + /* + * Register : L2_TM_MISC2 @ 0XFD40989C + + * ILL calib counts BYPASSED with calcode bits + * PSU_SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS 0x1 + + * sampler cal + * (OFFSET, MASK, VALUE) (0XFD40989C, 0x00000080U ,0x00000080U) + */ + PSU_Mask_Write(SERDES_L2_TM_MISC2_OFFSET, 0x00000080U, 0x00000080U); +/*##################################################################### */ + + /* + * Register : L2_TM_IQ_ILL1 @ 0XFD4098F8 + + * IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , + * USB3 : SS + * PSU_SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0 0x1A + + * iqpi cal code + * (OFFSET, MASK, VALUE) (0XFD4098F8, 0x000000FFU ,0x0000001AU) + */ + PSU_Mask_Write(SERDES_L2_TM_IQ_ILL1_OFFSET, + 0x000000FFU, 0x0000001AU); +/*##################################################################### */ + + /* + * Register : L2_TM_IQ_ILL2 @ 0XFD4098FC + + * IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 + * PSU_SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1 0x1A + + * iqpi cal code + * (OFFSET, MASK, VALUE) (0XFD4098FC, 0x000000FFU ,0x0000001AU) + */ + PSU_Mask_Write(SERDES_L2_TM_IQ_ILL2_OFFSET, + 0x000000FFU, 0x0000001AU); +/*##################################################################### */ + + /* + * Register : L2_TM_ILL12 @ 0XFD409990 + + * G1A pll ctr bypass value + * PSU_SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL 0x10 + + * ill pll counter values + * (OFFSET, MASK, VALUE) (0XFD409990, 0x000000FFU ,0x00000010U) + */ + PSU_Mask_Write(SERDES_L2_TM_ILL12_OFFSET, 0x000000FFU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : L2_TM_E_ILL1 @ 0XFD409924 + + * E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , U + * SB3 : SS + * PSU_SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0 0xFE + + * epi cal code + * (OFFSET, MASK, VALUE) (0XFD409924, 0x000000FFU ,0x000000FEU) + */ + PSU_Mask_Write(SERDES_L2_TM_E_ILL1_OFFSET, 0x000000FFU, 0x000000FEU); +/*##################################################################### */ + + /* + * Register : L2_TM_E_ILL2 @ 0XFD409928 + + * E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 + * PSU_SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1 0x0 + + * epi cal code + * (OFFSET, MASK, VALUE) (0XFD409928, 0x000000FFU ,0x00000000U) + */ + PSU_Mask_Write(SERDES_L2_TM_E_ILL2_OFFSET, 0x000000FFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : L2_TM_IQ_ILL3 @ 0XFD409900 + + * IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 + * PSU_SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2 0x1A + + * iqpi cal code + * (OFFSET, MASK, VALUE) (0XFD409900, 0x000000FFU ,0x0000001AU) + */ + PSU_Mask_Write(SERDES_L2_TM_IQ_ILL3_OFFSET, + 0x000000FFU, 0x0000001AU); +/*##################################################################### */ + + /* + * Register : L2_TM_E_ILL3 @ 0XFD40992C + + * E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 + * PSU_SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2 0x0 + + * epi cal code + * (OFFSET, MASK, VALUE) (0XFD40992C, 0x000000FFU ,0x00000000U) + */ + PSU_Mask_Write(SERDES_L2_TM_E_ILL3_OFFSET, 0x000000FFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : L2_TM_ILL8 @ 0XFD409980 + + * ILL calibration code change wait time + * PSU_SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT 0xFF + + * ILL cal routine control + * (OFFSET, MASK, VALUE) (0XFD409980, 0x000000FFU ,0x000000FFU) + */ + PSU_Mask_Write(SERDES_L2_TM_ILL8_OFFSET, 0x000000FFU, 0x000000FFU); +/*##################################################################### */ + + /* + * Register : L2_TM_IQ_ILL8 @ 0XFD409914 + + * IQ ILL polytrim bypass value + * PSU_SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL 0xF7 + + * iqpi polytrim + * (OFFSET, MASK, VALUE) (0XFD409914, 0x000000FFU ,0x000000F7U) + */ + PSU_Mask_Write(SERDES_L2_TM_IQ_ILL8_OFFSET, + 0x000000FFU, 0x000000F7U); +/*##################################################################### */ + + /* + * Register : L2_TM_IQ_ILL9 @ 0XFD409918 + + * bypass IQ polytrim + * PSU_SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM 0x1 + + * enables for lf,constant gm trim and polytirm + * (OFFSET, MASK, VALUE) (0XFD409918, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L2_TM_IQ_ILL9_OFFSET, + 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : L2_TM_E_ILL8 @ 0XFD409940 + + * E ILL polytrim bypass value + * PSU_SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL 0xF7 + + * epi polytrim + * (OFFSET, MASK, VALUE) (0XFD409940, 0x000000FFU ,0x000000F7U) + */ + PSU_Mask_Write(SERDES_L2_TM_E_ILL8_OFFSET, 0x000000FFU, 0x000000F7U); +/*##################################################################### */ + + /* + * Register : L2_TM_E_ILL9 @ 0XFD409944 + + * bypass E polytrim + * PSU_SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM 0x1 + + * enables for lf,constant gm trim and polytirm + * (OFFSET, MASK, VALUE) (0XFD409944, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L2_TM_E_ILL9_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : L2_TM_ILL13 @ 0XFD409994 + + * ILL cal idle val refcnt + * PSU_SERDES_L2_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT 0x7 + + * ill cal idle value count + * (OFFSET, MASK, VALUE) (0XFD409994, 0x00000007U ,0x00000007U) + */ + PSU_Mask_Write(SERDES_L2_TM_ILL13_OFFSET, 0x00000007U, 0x00000007U); +/*##################################################################### */ + + /* + * Register : L3_TM_MISC2 @ 0XFD40D89C + + * ILL calib counts BYPASSED with calcode bits + * PSU_SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS 0x1 + + * sampler cal + * (OFFSET, MASK, VALUE) (0XFD40D89C, 0x00000080U ,0x00000080U) + */ + PSU_Mask_Write(SERDES_L3_TM_MISC2_OFFSET, 0x00000080U, 0x00000080U); +/*##################################################################### */ + + /* + * Register : L3_TM_IQ_ILL1 @ 0XFD40D8F8 + + * IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , + * USB3 : SS + * PSU_SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0 0x7D + + * iqpi cal code + * (OFFSET, MASK, VALUE) (0XFD40D8F8, 0x000000FFU ,0x0000007DU) + */ + PSU_Mask_Write(SERDES_L3_TM_IQ_ILL1_OFFSET, + 0x000000FFU, 0x0000007DU); +/*##################################################################### */ + + /* + * Register : L3_TM_IQ_ILL2 @ 0XFD40D8FC + + * IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 + * PSU_SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1 0x7D + + * iqpi cal code + * (OFFSET, MASK, VALUE) (0XFD40D8FC, 0x000000FFU ,0x0000007DU) + */ + PSU_Mask_Write(SERDES_L3_TM_IQ_ILL2_OFFSET, + 0x000000FFU, 0x0000007DU); +/*##################################################################### */ + + /* + * Register : L3_TM_ILL12 @ 0XFD40D990 + + * G1A pll ctr bypass value + * PSU_SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL 0x1 + + * ill pll counter values + * (OFFSET, MASK, VALUE) (0XFD40D990, 0x000000FFU ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L3_TM_ILL12_OFFSET, 0x000000FFU, 0x00000001U); +/*##################################################################### */ + + /* + * Register : L3_TM_E_ILL1 @ 0XFD40D924 + + * E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , U + * SB3 : SS + * PSU_SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0 0x9C + + * epi cal code + * (OFFSET, MASK, VALUE) (0XFD40D924, 0x000000FFU ,0x0000009CU) + */ + PSU_Mask_Write(SERDES_L3_TM_E_ILL1_OFFSET, 0x000000FFU, 0x0000009CU); +/*##################################################################### */ + + /* + * Register : L3_TM_E_ILL2 @ 0XFD40D928 + + * E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 + * PSU_SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1 0x39 + + * epi cal code + * (OFFSET, MASK, VALUE) (0XFD40D928, 0x000000FFU ,0x00000039U) + */ + PSU_Mask_Write(SERDES_L3_TM_E_ILL2_OFFSET, 0x000000FFU, 0x00000039U); +/*##################################################################### */ + + /* + * Register : L3_TM_ILL11 @ 0XFD40D98C + + * G2A_PCIe1 PLL ctr bypass value + * PSU_SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL 0x2 + + * ill pll counter values + * (OFFSET, MASK, VALUE) (0XFD40D98C, 0x000000F0U ,0x00000020U) + */ + PSU_Mask_Write(SERDES_L3_TM_ILL11_OFFSET, 0x000000F0U, 0x00000020U); +/*##################################################################### */ + + /* + * Register : L3_TM_IQ_ILL3 @ 0XFD40D900 + + * IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 + * PSU_SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2 0x7D + + * iqpi cal code + * (OFFSET, MASK, VALUE) (0XFD40D900, 0x000000FFU ,0x0000007DU) + */ + PSU_Mask_Write(SERDES_L3_TM_IQ_ILL3_OFFSET, + 0x000000FFU, 0x0000007DU); +/*##################################################################### */ + + /* + * Register : L3_TM_E_ILL3 @ 0XFD40D92C + + * E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 + * PSU_SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2 0x64 + + * epi cal code + * (OFFSET, MASK, VALUE) (0XFD40D92C, 0x000000FFU ,0x00000064U) + */ + PSU_Mask_Write(SERDES_L3_TM_E_ILL3_OFFSET, 0x000000FFU, 0x00000064U); +/*##################################################################### */ + + /* + * Register : L3_TM_ILL8 @ 0XFD40D980 + + * ILL calibration code change wait time + * PSU_SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT 0xFF + + * ILL cal routine control + * (OFFSET, MASK, VALUE) (0XFD40D980, 0x000000FFU ,0x000000FFU) + */ + PSU_Mask_Write(SERDES_L3_TM_ILL8_OFFSET, 0x000000FFU, 0x000000FFU); +/*##################################################################### */ + + /* + * Register : L3_TM_IQ_ILL8 @ 0XFD40D914 + + * IQ ILL polytrim bypass value + * PSU_SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL 0xF7 + + * iqpi polytrim + * (OFFSET, MASK, VALUE) (0XFD40D914, 0x000000FFU ,0x000000F7U) + */ + PSU_Mask_Write(SERDES_L3_TM_IQ_ILL8_OFFSET, + 0x000000FFU, 0x000000F7U); +/*##################################################################### */ + + /* + * Register : L3_TM_IQ_ILL9 @ 0XFD40D918 + + * bypass IQ polytrim + * PSU_SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM 0x1 + + * enables for lf,constant gm trim and polytirm + * (OFFSET, MASK, VALUE) (0XFD40D918, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L3_TM_IQ_ILL9_OFFSET, + 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : L3_TM_E_ILL8 @ 0XFD40D940 + + * E ILL polytrim bypass value + * PSU_SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL 0xF7 + + * epi polytrim + * (OFFSET, MASK, VALUE) (0XFD40D940, 0x000000FFU ,0x000000F7U) + */ + PSU_Mask_Write(SERDES_L3_TM_E_ILL8_OFFSET, 0x000000FFU, 0x000000F7U); +/*##################################################################### */ + + /* + * Register : L3_TM_E_ILL9 @ 0XFD40D944 + + * bypass E polytrim + * PSU_SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM 0x1 + + * enables for lf,constant gm trim and polytirm + * (OFFSET, MASK, VALUE) (0XFD40D944, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L3_TM_E_ILL9_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : L3_TM_ILL13 @ 0XFD40D994 + + * ILL cal idle val refcnt + * PSU_SERDES_L3_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT 0x7 + + * ill cal idle value count + * (OFFSET, MASK, VALUE) (0XFD40D994, 0x00000007U ,0x00000007U) + */ + PSU_Mask_Write(SERDES_L3_TM_ILL13_OFFSET, 0x00000007U, 0x00000007U); +/*##################################################################### */ + + /* + * SYMBOL LOCK AND WAIT + */ + /* + * Register : L0_TM_DIG_10 @ 0XFD40107C + + * CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001 + * PSU_SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME 0x1 + + * test control for changing cdr lock wait time + * (OFFSET, MASK, VALUE) (0XFD40107C, 0x0000000FU ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L0_TM_DIG_10_OFFSET, 0x0000000FU, 0x00000001U); +/*##################################################################### */ + + /* + * Register : L1_TM_DIG_10 @ 0XFD40507C + + * CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001 + * PSU_SERDES_L1_TM_DIG_10_CDR_BIT_LOCK_TIME 0x1 + + * test control for changing cdr lock wait time + * (OFFSET, MASK, VALUE) (0XFD40507C, 0x0000000FU ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L1_TM_DIG_10_OFFSET, 0x0000000FU, 0x00000001U); +/*##################################################################### */ + + /* + * Register : L2_TM_DIG_10 @ 0XFD40907C + + * CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001 + * PSU_SERDES_L2_TM_DIG_10_CDR_BIT_LOCK_TIME 0x1 + + * test control for changing cdr lock wait time + * (OFFSET, MASK, VALUE) (0XFD40907C, 0x0000000FU ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L2_TM_DIG_10_OFFSET, 0x0000000FU, 0x00000001U); +/*##################################################################### */ + + /* + * Register : L3_TM_DIG_10 @ 0XFD40D07C + + * CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001 + * PSU_SERDES_L3_TM_DIG_10_CDR_BIT_LOCK_TIME 0x1 + + * test control for changing cdr lock wait time + * (OFFSET, MASK, VALUE) (0XFD40D07C, 0x0000000FU ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L3_TM_DIG_10_OFFSET, 0x0000000FU, 0x00000001U); +/*##################################################################### */ + + /* + * SIOU SETTINGS FOR BYPASS CONTROL,HSRX-DIG + */ + /* + * Register : L0_TM_RST_DLY @ 0XFD4019A4 + + * Delay apb reset by specified amount + * PSU_SERDES_L0_TM_RST_DLY_APB_RST_DLY 0xFF + + * reset delay for apb reset w.r.t pso of hsrx + * (OFFSET, MASK, VALUE) (0XFD4019A4, 0x000000FFU ,0x000000FFU) + */ + PSU_Mask_Write(SERDES_L0_TM_RST_DLY_OFFSET, + 0x000000FFU, 0x000000FFU); +/*##################################################################### */ + + /* + * Register : L0_TM_ANA_BYP_15 @ 0XFD401038 + + * Enable Bypass for <7> of TM_ANA_BYPS_15 + * PSU_SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE 0x1 + + * Bypass control for pcs-pma interface. EQ supplies, main master supply an + * d ps for samp c2c + * (OFFSET, MASK, VALUE) (0XFD401038, 0x00000040U ,0x00000040U) + */ + PSU_Mask_Write(SERDES_L0_TM_ANA_BYP_15_OFFSET, + 0x00000040U, 0x00000040U); +/*##################################################################### */ + + /* + * Register : L0_TM_ANA_BYP_12 @ 0XFD40102C + + * Enable Bypass for <7> of TM_ANA_BYPS_12 + * PSU_SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG 0x1 + + * Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr ena + * ble controls + * (OFFSET, MASK, VALUE) (0XFD40102C, 0x00000040U ,0x00000040U) + */ + PSU_Mask_Write(SERDES_L0_TM_ANA_BYP_12_OFFSET, + 0x00000040U, 0x00000040U); +/*##################################################################### */ + + /* + * Register : L1_TM_RST_DLY @ 0XFD4059A4 + + * Delay apb reset by specified amount + * PSU_SERDES_L1_TM_RST_DLY_APB_RST_DLY 0xFF + + * reset delay for apb reset w.r.t pso of hsrx + * (OFFSET, MASK, VALUE) (0XFD4059A4, 0x000000FFU ,0x000000FFU) + */ + PSU_Mask_Write(SERDES_L1_TM_RST_DLY_OFFSET, + 0x000000FFU, 0x000000FFU); +/*##################################################################### */ + + /* + * Register : L1_TM_ANA_BYP_15 @ 0XFD405038 + + * Enable Bypass for <7> of TM_ANA_BYPS_15 + * PSU_SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE 0x1 + + * Bypass control for pcs-pma interface. EQ supplies, main master supply an + * d ps for samp c2c + * (OFFSET, MASK, VALUE) (0XFD405038, 0x00000040U ,0x00000040U) + */ + PSU_Mask_Write(SERDES_L1_TM_ANA_BYP_15_OFFSET, + 0x00000040U, 0x00000040U); +/*##################################################################### */ + + /* + * Register : L1_TM_ANA_BYP_12 @ 0XFD40502C + + * Enable Bypass for <7> of TM_ANA_BYPS_12 + * PSU_SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG 0x1 + + * Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr ena + * ble controls + * (OFFSET, MASK, VALUE) (0XFD40502C, 0x00000040U ,0x00000040U) + */ + PSU_Mask_Write(SERDES_L1_TM_ANA_BYP_12_OFFSET, + 0x00000040U, 0x00000040U); +/*##################################################################### */ + + /* + * Register : L2_TM_RST_DLY @ 0XFD4099A4 + + * Delay apb reset by specified amount + * PSU_SERDES_L2_TM_RST_DLY_APB_RST_DLY 0xFF + + * reset delay for apb reset w.r.t pso of hsrx + * (OFFSET, MASK, VALUE) (0XFD4099A4, 0x000000FFU ,0x000000FFU) + */ + PSU_Mask_Write(SERDES_L2_TM_RST_DLY_OFFSET, + 0x000000FFU, 0x000000FFU); +/*##################################################################### */ + + /* + * Register : L2_TM_ANA_BYP_15 @ 0XFD409038 + + * Enable Bypass for <7> of TM_ANA_BYPS_15 + * PSU_SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE 0x1 + + * Bypass control for pcs-pma interface. EQ supplies, main master supply an + * d ps for samp c2c + * (OFFSET, MASK, VALUE) (0XFD409038, 0x00000040U ,0x00000040U) + */ + PSU_Mask_Write(SERDES_L2_TM_ANA_BYP_15_OFFSET, + 0x00000040U, 0x00000040U); +/*##################################################################### */ + + /* + * Register : L2_TM_ANA_BYP_12 @ 0XFD40902C + + * Enable Bypass for <7> of TM_ANA_BYPS_12 + * PSU_SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG 0x1 + + * Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr ena + * ble controls + * (OFFSET, MASK, VALUE) (0XFD40902C, 0x00000040U ,0x00000040U) + */ + PSU_Mask_Write(SERDES_L2_TM_ANA_BYP_12_OFFSET, + 0x00000040U, 0x00000040U); +/*##################################################################### */ + + /* + * Register : L3_TM_RST_DLY @ 0XFD40D9A4 + + * Delay apb reset by specified amount + * PSU_SERDES_L3_TM_RST_DLY_APB_RST_DLY 0xFF + + * reset delay for apb reset w.r.t pso of hsrx + * (OFFSET, MASK, VALUE) (0XFD40D9A4, 0x000000FFU ,0x000000FFU) + */ + PSU_Mask_Write(SERDES_L3_TM_RST_DLY_OFFSET, + 0x000000FFU, 0x000000FFU); +/*##################################################################### */ + + /* + * Register : L3_TM_ANA_BYP_15 @ 0XFD40D038 + + * Enable Bypass for <7> of TM_ANA_BYPS_15 + * PSU_SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE 0x1 + + * Bypass control for pcs-pma interface. EQ supplies, main master supply an + * d ps for samp c2c + * (OFFSET, MASK, VALUE) (0XFD40D038, 0x00000040U ,0x00000040U) + */ + PSU_Mask_Write(SERDES_L3_TM_ANA_BYP_15_OFFSET, + 0x00000040U, 0x00000040U); +/*##################################################################### */ + + /* + * Register : L3_TM_ANA_BYP_12 @ 0XFD40D02C + + * Enable Bypass for <7> of TM_ANA_BYPS_12 + * PSU_SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG 0x1 + + * Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr ena + * ble controls + * (OFFSET, MASK, VALUE) (0XFD40D02C, 0x00000040U ,0x00000040U) + */ + PSU_Mask_Write(SERDES_L3_TM_ANA_BYP_12_OFFSET, + 0x00000040U, 0x00000040U); +/*##################################################################### */ + + /* + * DISABLE FPL/FFL + */ + /* + * Register : L0_TM_MISC3 @ 0XFD4019AC + + * CDR fast phase lock control + * PSU_SERDES_L0_TM_MISC3_CDR_EN_FPL 0x0 + + * CDR fast frequency lock control + * PSU_SERDES_L0_TM_MISC3_CDR_EN_FFL 0x0 + + * debug bus selection bit, cdr fast phase and freq controls + * (OFFSET, MASK, VALUE) (0XFD4019AC, 0x00000003U ,0x00000000U) + */ + PSU_Mask_Write(SERDES_L0_TM_MISC3_OFFSET, 0x00000003U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : L1_TM_MISC3 @ 0XFD4059AC + + * CDR fast phase lock control + * PSU_SERDES_L1_TM_MISC3_CDR_EN_FPL 0x0 + + * CDR fast frequency lock control + * PSU_SERDES_L1_TM_MISC3_CDR_EN_FFL 0x0 + + * debug bus selection bit, cdr fast phase and freq controls + * (OFFSET, MASK, VALUE) (0XFD4059AC, 0x00000003U ,0x00000000U) + */ + PSU_Mask_Write(SERDES_L1_TM_MISC3_OFFSET, 0x00000003U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : L2_TM_MISC3 @ 0XFD4099AC + + * CDR fast phase lock control + * PSU_SERDES_L2_TM_MISC3_CDR_EN_FPL 0x0 + + * CDR fast frequency lock control + * PSU_SERDES_L2_TM_MISC3_CDR_EN_FFL 0x0 + + * debug bus selection bit, cdr fast phase and freq controls + * (OFFSET, MASK, VALUE) (0XFD4099AC, 0x00000003U ,0x00000000U) + */ + PSU_Mask_Write(SERDES_L2_TM_MISC3_OFFSET, 0x00000003U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : L3_TM_MISC3 @ 0XFD40D9AC + + * CDR fast phase lock control + * PSU_SERDES_L3_TM_MISC3_CDR_EN_FPL 0x0 + + * CDR fast frequency lock control + * PSU_SERDES_L3_TM_MISC3_CDR_EN_FFL 0x0 + + * debug bus selection bit, cdr fast phase and freq controls + * (OFFSET, MASK, VALUE) (0XFD40D9AC, 0x00000003U ,0x00000000U) + */ + PSU_Mask_Write(SERDES_L3_TM_MISC3_OFFSET, 0x00000003U, 0x00000000U); +/*##################################################################### */ + + /* + * DISABLE DYNAMIC OFFSET CALIBRATION + */ + /* + * Register : L0_TM_EQ11 @ 0XFD401978 + + * Force EQ offset correction algo off if not forced on + * PSU_SERDES_L0_TM_EQ11_FORCE_EQ_OFFS_OFF 0x1 + + * eq dynamic offset correction + * (OFFSET, MASK, VALUE) (0XFD401978, 0x00000010U ,0x00000010U) + */ + PSU_Mask_Write(SERDES_L0_TM_EQ11_OFFSET, 0x00000010U, 0x00000010U); +/*##################################################################### */ + + /* + * Register : L1_TM_EQ11 @ 0XFD405978 + + * Force EQ offset correction algo off if not forced on + * PSU_SERDES_L1_TM_EQ11_FORCE_EQ_OFFS_OFF 0x1 + + * eq dynamic offset correction + * (OFFSET, MASK, VALUE) (0XFD405978, 0x00000010U ,0x00000010U) + */ + PSU_Mask_Write(SERDES_L1_TM_EQ11_OFFSET, 0x00000010U, 0x00000010U); +/*##################################################################### */ + + /* + * Register : L2_TM_EQ11 @ 0XFD409978 + + * Force EQ offset correction algo off if not forced on + * PSU_SERDES_L2_TM_EQ11_FORCE_EQ_OFFS_OFF 0x1 + + * eq dynamic offset correction + * (OFFSET, MASK, VALUE) (0XFD409978, 0x00000010U ,0x00000010U) + */ + PSU_Mask_Write(SERDES_L2_TM_EQ11_OFFSET, 0x00000010U, 0x00000010U); +/*##################################################################### */ + + /* + * Register : L3_TM_EQ11 @ 0XFD40D978 + + * Force EQ offset correction algo off if not forced on + * PSU_SERDES_L3_TM_EQ11_FORCE_EQ_OFFS_OFF 0x1 + + * eq dynamic offset correction + * (OFFSET, MASK, VALUE) (0XFD40D978, 0x00000010U ,0x00000010U) + */ + PSU_Mask_Write(SERDES_L3_TM_EQ11_OFFSET, 0x00000010U, 0x00000010U); +/*##################################################################### */ + + /* + * DISABLE ECO FOR PCIE + */ + /* + * Register : eco_0 @ 0XFD3D001C + + * For future use + * PSU_SIOU_ECO_0_FIELD 0x1 + + * ECO Register for future use + * (OFFSET, MASK, VALUE) (0XFD3D001C, 0xFFFFFFFFU ,0x00000001U) + */ + PSU_Mask_Write(SIOU_ECO_0_OFFSET, 0xFFFFFFFFU, 0x00000001U); +/*##################################################################### */ + + /* + * GT LANE SETTINGS + */ + /* + * Register : ICM_CFG0 @ 0XFD410010 + + * Controls UPHY Lane 0 protocol configuration. 0 - PowerDown, 1 - PCIe .0, + * 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII0, 6 - Unused, 7 - Unused + * PSU_SERDES_ICM_CFG0_L0_ICM_CFG 1 + + * Controls UPHY Lane 1 protocol configuration. 0 - PowerDown, 1 - PCIe.1, + * 2 - Sata1, 3 - USB0, 4 - DP.0, 5 - SGMII1, 6 - Unused, 7 - Unused + * PSU_SERDES_ICM_CFG0_L1_ICM_CFG 4 + + * ICM Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD410010, 0x00000077U ,0x00000041U) + */ + PSU_Mask_Write(SERDES_ICM_CFG0_OFFSET, 0x00000077U, 0x00000041U); +/*##################################################################### */ + + /* + * Register : ICM_CFG1 @ 0XFD410014 + + * Controls UPHY Lane 2 protocol configuration. 0 - PowerDown, 1 - PCIe.1, + * 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII2, 6 - Unused, 7 - Unused + * PSU_SERDES_ICM_CFG1_L2_ICM_CFG 3 + + * Controls UPHY Lane 3 protocol configuration. 0 - PowerDown, 1 - PCIe.3, + * 2 - Sata1, 3 - USB1, 4 - DP.0, 5 - SGMII3, 6 - Unused, 7 - Unused + * PSU_SERDES_ICM_CFG1_L3_ICM_CFG 2 + + * ICM Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD410014, 0x00000077U ,0x00000023U) + */ + PSU_Mask_Write(SERDES_ICM_CFG1_OFFSET, 0x00000077U, 0x00000023U); +/*##################################################################### */ + + /* + * CHECKING PLL LOCK + */ + /* + * ENABLE SERIAL DATA MUX DEEMPH + */ + /* + * Register : L1_TXPMD_TM_45 @ 0XFD404CB4 + + * Enable/disable DP post2 path + * PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH 0x1 + + * Override enable/disable of DP post2 path + * PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH 0x1 + + * Override enable/disable of DP post1 path + * PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH 0x1 + + * Enable/disable DP main path + * PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH 0x1 + + * Override enable/disable of DP main path + * PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH 0x1 + + * Post or pre or main DP path selection + * (OFFSET, MASK, VALUE) (0XFD404CB4, 0x00000037U ,0x00000037U) + */ + PSU_Mask_Write(SERDES_L1_TXPMD_TM_45_OFFSET, + 0x00000037U, 0x00000037U); +/*##################################################################### */ + + /* + * Register : L1_TX_ANA_TM_118 @ 0XFD4041D8 + + * Test register force for enabling/disablign TX deemphasis bits <17:0> + * PSU_SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0 0x1 + + * Enable Override of TX deemphasis + * (OFFSET, MASK, VALUE) (0XFD4041D8, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L1_TX_ANA_TM_118_OFFSET, + 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : L3_TX_ANA_TM_118 @ 0XFD40C1D8 + + * Test register force for enabling/disablign TX deemphasis bits <17:0> + * PSU_SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0 0x1 + + * Enable Override of TX deemphasis + * (OFFSET, MASK, VALUE) (0XFD40C1D8, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L3_TX_ANA_TM_118_OFFSET, + 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * CDR AND RX EQUALIZATION SETTINGS + */ + /* + * Register : L3_TM_CDR5 @ 0XFD40DC14 + + * FPHL FSM accumulate cycles + * PSU_SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES 0x7 + + * FFL Phase0 int gain aka 2ol SD update rate + * PSU_SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN 0x6 + + * Fast phase lock controls -- FSM accumulator cycle control and phase 0 in + * t gain control. + * (OFFSET, MASK, VALUE) (0XFD40DC14, 0x000000FFU ,0x000000E6U) + */ + PSU_Mask_Write(SERDES_L3_TM_CDR5_OFFSET, 0x000000FFU, 0x000000E6U); +/*##################################################################### */ + + /* + * Register : L3_TM_CDR16 @ 0XFD40DC40 + + * FFL Phase0 prop gain aka 1ol SD update rate + * PSU_SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN 0xC + + * Fast phase lock controls -- phase 0 prop gain + * (OFFSET, MASK, VALUE) (0XFD40DC40, 0x0000001FU ,0x0000000CU) + */ + PSU_Mask_Write(SERDES_L3_TM_CDR16_OFFSET, 0x0000001FU, 0x0000000CU); +/*##################################################################### */ + + /* + * Register : L3_TM_EQ0 @ 0XFD40D94C + + * EQ stg 2 controls BYPASSED + * PSU_SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP 1 + + * eq stg1 and stg2 controls + * (OFFSET, MASK, VALUE) (0XFD40D94C, 0x00000020U ,0x00000020U) + */ + PSU_Mask_Write(SERDES_L3_TM_EQ0_OFFSET, 0x00000020U, 0x00000020U); +/*##################################################################### */ + + /* + * Register : L3_TM_EQ1 @ 0XFD40D950 + + * EQ STG2 RL PROG + * PSU_SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG 0x2 + + * EQ stg 2 preamp mode val + * PSU_SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL 0x1 + + * eq stg1 and stg2 controls + * (OFFSET, MASK, VALUE) (0XFD40D950, 0x00000007U ,0x00000006U) + */ + PSU_Mask_Write(SERDES_L3_TM_EQ1_OFFSET, 0x00000007U, 0x00000006U); +/*##################################################################### */ + + /* + * GEM SERDES SETTINGS + */ + /* + * ENABLE PRE EMPHAIS AND VOLTAGE SWING + */ + /* + * Register : L1_TXPMD_TM_48 @ 0XFD404CC0 + + * Margining factor value + * PSU_SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR 0 + + * Margining factor + * (OFFSET, MASK, VALUE) (0XFD404CC0, 0x0000001FU ,0x00000000U) + */ + PSU_Mask_Write(SERDES_L1_TXPMD_TM_48_OFFSET, + 0x0000001FU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : L1_TX_ANA_TM_18 @ 0XFD404048 + + * pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-em + * phasis, Others: reserved + * PSU_SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0 0 + + * Override for PIPE TX de-emphasis + * (OFFSET, MASK, VALUE) (0XFD404048, 0x000000FFU ,0x00000000U) + */ + PSU_Mask_Write(SERDES_L1_TX_ANA_TM_18_OFFSET, + 0x000000FFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : L3_TX_ANA_TM_18 @ 0XFD40C048 + + * pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-em + * phasis, Others: reserved + * PSU_SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0 0x1 + + * Override for PIPE TX de-emphasis + * (OFFSET, MASK, VALUE) (0XFD40C048, 0x000000FFU ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L3_TX_ANA_TM_18_OFFSET, + 0x000000FFU, 0x00000001U); +/*##################################################################### */ + + + return 1; } -unsigned long psu_resetin_init_data() { - // : PUTTING SERDES PERIPHERAL IN RESET - // : PUTTING USB0 IN RESET - /*Register : RST_LPD_TOP @ 0XFF5E023C

+unsigned long psu_resetout_init_data(void) +{ + /* + * TAKING SERDES PERIPHERAL OUT OF RESET RESET + */ + /* + * PUTTING USB0 IN RESET + */ + /* + * Register : RST_LPD_TOP @ 0XFF5E023C - USB 0 reset for control registers - PSU_CRL_APB_RST_LPD_TOP_USB0_APB_RESET 0X1 + * USB 0 reset for control registers + * PSU_CRL_APB_RST_LPD_TOP_USB0_APB_RESET 0X0 - USB 0 sleep circuit reset - PSU_CRL_APB_RST_LPD_TOP_USB0_HIBERRESET 0X1 + * Software control register for the LPD block. + * (OFFSET, MASK, VALUE) (0XFF5E023C, 0x00000400U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_TOP_OFFSET, 0x00000400U, 0x00000000U); +/*##################################################################### */ - USB 0 reset - PSU_CRL_APB_RST_LPD_TOP_USB0_CORERESET 0X1 + /* + * HIBERREST + */ + /* + * Register : RST_LPD_TOP @ 0XFF5E023C - Software control register for the LPD block. - (OFFSET, MASK, VALUE) (0XFF5E023C, 0x00000540U ,0x00000540U) - RegMask = (CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK | CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK | CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK | 0 ); + * USB 0 sleep circuit reset + * PSU_CRL_APB_RST_LPD_TOP_USB0_HIBERRESET 0X0 - RegVal = ((0x00000001U << CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT - | 0x00000001U << CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT - | 0x00000001U << CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RST_LPD_TOP_OFFSET ,0x00000540U ,0x00000540U); - /*############################################################################################################################ */ + * USB 0 reset + * PSU_CRL_APB_RST_LPD_TOP_USB0_CORERESET 0X0 - // : PUTTING GEM0 IN RESET - /*Register : RST_LPD_IOU0 @ 0XFF5E0230

+ * Software control register for the LPD block. + * (OFFSET, MASK, VALUE) (0XFF5E023C, 0x00000140U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_TOP_OFFSET, 0x00000140U, 0x00000000U); +/*##################################################################### */ - GEM 3 reset - PSU_CRL_APB_RST_LPD_IOU0_GEM3_RESET 0X1 + /* + * PUTTING GEM0 IN RESET + */ + /* + * Register : RST_LPD_IOU0 @ 0XFF5E0230 - Software controlled reset for the GEMs - (OFFSET, MASK, VALUE) (0XFF5E0230, 0x00000008U ,0x00000008U) - RegMask = (CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK | 0 ); + * GEM 3 reset + * PSU_CRL_APB_RST_LPD_IOU0_GEM3_RESET 0X0 - RegVal = ((0x00000001U << CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RST_LPD_IOU0_OFFSET ,0x00000008U ,0x00000008U); - /*############################################################################################################################ */ + * Software controlled reset for the GEMs + * (OFFSET, MASK, VALUE) (0XFF5E0230, 0x00000008U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_IOU0_OFFSET, + 0x00000008U, 0x00000000U); +/*##################################################################### */ - // : PUTTING SATA IN RESET - /*Register : RST_FPD_TOP @ 0XFD1A0100

+ /* + * PUTTING SATA IN RESET + */ + /* + * Register : sata_misc_ctrl @ 0XFD3D0100 - Sata block level reset - PSU_CRF_APB_RST_FPD_TOP_SATA_RESET 0X1 + * Sata PM clock control select + * PSU_SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL 0x3 - FPD Block level software controlled reset - (OFFSET, MASK, VALUE) (0XFD1A0100, 0x00000002U ,0x00000002U) - RegMask = (CRF_APB_RST_FPD_TOP_SATA_RESET_MASK | 0 ); + * Misc Contorls for SATA.This register may only be modified during bootup + * (while SATA block is disabled) + * (OFFSET, MASK, VALUE) (0XFD3D0100, 0x00000003U ,0x00000003U) + */ + PSU_Mask_Write(SIOU_SATA_MISC_CTRL_OFFSET, 0x00000003U, 0x00000003U); +/*##################################################################### */ - RegVal = ((0x00000001U << CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_RST_FPD_TOP_OFFSET ,0x00000002U ,0x00000002U); - /*############################################################################################################################ */ + /* + * Register : RST_FPD_TOP @ 0XFD1A0100 - // : PUTTING PCIE IN RESET - /*Register : RST_FPD_TOP @ 0XFD1A0100

+ * Sata block level reset + * PSU_CRF_APB_RST_FPD_TOP_SATA_RESET 0X0 - PCIE config reset - PSU_CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET 0X1 + * FPD Block level software controlled reset + * (OFFSET, MASK, VALUE) (0XFD1A0100, 0x00000002U ,0x00000000U) + */ + PSU_Mask_Write(CRF_APB_RST_FPD_TOP_OFFSET, 0x00000002U, 0x00000000U); +/*##################################################################### */ - PCIE control block level reset - PSU_CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET 0X1 + /* + * PUTTING PCIE CFG AND BRIDGE IN RESET + */ + /* + * Register : RST_FPD_TOP @ 0XFD1A0100 - PCIE bridge block level reset (AXI interface) - PSU_CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET 0X1 + * PCIE config reset + * PSU_CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET 0X0 - FPD Block level software controlled reset - (OFFSET, MASK, VALUE) (0XFD1A0100, 0x000E0000U ,0x000E0000U) - RegMask = (CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK | CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK | CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK | 0 ); + * PCIE bridge block level reset (AXI interface) + * PSU_CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET 0X0 - RegVal = ((0x00000001U << CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT - | 0x00000001U << CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT - | 0x00000001U << CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_RST_FPD_TOP_OFFSET ,0x000E0000U ,0x000E0000U); - /*############################################################################################################################ */ + * FPD Block level software controlled reset + * (OFFSET, MASK, VALUE) (0XFD1A0100, 0x000C0000U ,0x00000000U) + */ + PSU_Mask_Write(CRF_APB_RST_FPD_TOP_OFFSET, 0x000C0000U, 0x00000000U); +/*##################################################################### */ - // : PUTTING DP IN RESET - /*Register : DP_TX_PHY_POWER_DOWN @ 0XFD4A0238

+ /* + * PUTTING DP IN RESET + */ + /* + * Register : RST_FPD_TOP @ 0XFD1A0100 - Two bits per lane. When set to 11, moves the GT to power down mode. When set to 00, GT will be in active state. bits [1:0] - - ane0 Bits [3:2] - lane 1 - PSU_DP_DP_TX_PHY_POWER_DOWN_POWER_DWN 0XA + * Display Port block level reset (includes DPDMA) + * PSU_CRF_APB_RST_FPD_TOP_DP_RESET 0X0 - Control PHY Power down - (OFFSET, MASK, VALUE) (0XFD4A0238, 0x0000000FU ,0x0000000AU) - RegMask = (DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK | 0 ); + * FPD Block level software controlled reset + * (OFFSET, MASK, VALUE) (0XFD1A0100, 0x00010000U ,0x00000000U) + */ + PSU_Mask_Write(CRF_APB_RST_FPD_TOP_OFFSET, 0x00010000U, 0x00000000U); +/*##################################################################### */ - RegVal = ((0x0000000AU << DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DP_DP_TX_PHY_POWER_DOWN_OFFSET ,0x0000000FU ,0x0000000AU); - /*############################################################################################################################ */ + /* + * Register : DP_PHY_RESET @ 0XFD4A0200 - /*Register : DP_PHY_RESET @ 0XFD4A0200

+ * Set to '1' to hold the GT in reset. Clear to release. + * PSU_DP_DP_PHY_RESET_GT_RESET 0X0 - Set to '1' to hold the GT in reset. Clear to release. - PSU_DP_DP_PHY_RESET_GT_RESET 0X1 + * Reset the transmitter PHY. + * (OFFSET, MASK, VALUE) (0XFD4A0200, 0x00000002U ,0x00000000U) + */ + PSU_Mask_Write(DP_DP_PHY_RESET_OFFSET, 0x00000002U, 0x00000000U); +/*##################################################################### */ - Reset the transmitter PHY. - (OFFSET, MASK, VALUE) (0XFD4A0200, 0x00000002U ,0x00000002U) - RegMask = (DP_DP_PHY_RESET_GT_RESET_MASK | 0 ); + /* + * Register : DP_TX_PHY_POWER_DOWN @ 0XFD4A0238 - RegVal = ((0x00000001U << DP_DP_PHY_RESET_GT_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DP_DP_PHY_RESET_OFFSET ,0x00000002U ,0x00000002U); - /*############################################################################################################################ */ + * Two bits per lane. When set to 11, moves the GT to power down mode. When + * set to 00, GT will be in active state. bits [1:0] - lane0 Bits [3:2] - + * lane 1 + * PSU_DP_DP_TX_PHY_POWER_DOWN_POWER_DWN 0X0 - /*Register : RST_FPD_TOP @ 0XFD1A0100

+ * Control PHY Power down + * (OFFSET, MASK, VALUE) (0XFD4A0238, 0x0000000FU ,0x00000000U) + */ + PSU_Mask_Write(DP_DP_TX_PHY_POWER_DOWN_OFFSET, + 0x0000000FU, 0x00000000U); +/*##################################################################### */ - Display Port block level reset (includes DPDMA) - PSU_CRF_APB_RST_FPD_TOP_DP_RESET 0X1 + /* + * USB0 GFLADJ + */ + /* + * Register : GUSB2PHYCFG @ 0XFE20C200 - FPD Block level software controlled reset - (OFFSET, MASK, VALUE) (0XFD1A0100, 0x00010000U ,0x00010000U) - RegMask = (CRF_APB_RST_FPD_TOP_DP_RESET_MASK | 0 ); + * USB 2.0 Turnaround Time (USBTrdTim) Sets the turnaround time in PHY cloc + * ks. Specifies the response time for a MAC request to the Packet FIFO Con + * troller (PFC) to fetch data from the DFIFO (SPRAM). The following are th + * e required values for the minimum SoC bus frequency of 60 MHz. USB turna + * round time is a critical certification criteria when using long cables a + * nd five hub levels. The required values for this field: - 4'h5: When the + * MAC interface is 16-bit UTMI+. - 4'h9: When the MAC interface is 8-bit + * UTMI+/ULPI. If SoC bus clock is less than 60 MHz, and USB turnaround tim + * e is not critical, this field can be set to a larger value. Note: This f + * ield is valid only in device mode. + * PSU_USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM 0x9 - RegVal = ((0x00000001U << CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_RST_FPD_TOP_OFFSET ,0x00010000U ,0x00010000U); - /*############################################################################################################################ */ + * Transceiver Delay: Enables a delay between the assertion of the UTMI/ULP + * I Transceiver Select signal (for HS) and the assertion of the TxValid si + * gnal during a HS Chirp. When this bit is set to 1, a delay (of approxima + * tely 2.5 us) is introduced from the time when the Transceiver Select is + * set to 2'b00 (HS) to the time the TxValid is driven to 0 for sending the + * chirp-K. This delay is required for some UTMI/ULPI PHYs. Note: - If you + * enable the hibernation feature when the device core comes out of power- + * off, you must re-initialize this bit with the appropriate value because + * the core does not save and restore this bit value during hibernation. - + * This bit is valid only in device mode. + * PSU_USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY 0x0 + + * Enable utmi_sleep_n and utmi_l1_suspend_n (EnblSlpM) The application use + * s this bit to control utmi_sleep_n and utmi_l1_suspend_n assertion to th + * e PHY in the L1 state. - 1'b0: utmi_sleep_n and utmi_l1_suspend_n assert + * ion from the core is not transferred to the external PHY. - 1'b1: utmi_s + * leep_n and utmi_l1_suspend_n assertion from the core is transferred to t + * he external PHY. Note: This bit must be set high for Port0 if PHY is use + * d. Note: In Device mode - Before issuing any device endpoint command whe + * n operating in 2.0 speeds, disable this bit and enable it after the comm + * and completes. Without disabling this bit, if a command is issued when t + * he device is in L1 state and if mac2_clk (utmi_clk/ulpi_clk) is gated of + * f, the command will not get completed. + * PSU_USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM 0x0 + + * USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial Transceiver Select T + * he application uses this bit to select a high-speed PHY or a full-speed + * transceiver. - 1'b0: USB 2.0 high-speed UTMI+ or ULPI PHY. This bit is a + * lways 0, with Write Only access. - 1'b1: USB 1.1 full-speed serial trans + * ceiver. This bit is always 1, with Write Only access. If both interface + * types are selected in coreConsultant (that is, parameters' values are no + * t zero), the application uses this bit to select the active interface is + * active, with Read-Write bit access. Note: USB 1.1 full-serial transceiv + * er is not supported. This bit always reads as 1'b0. + * PSU_USB3_0_XHCI_GUSB2PHYCFG_PHYSEL 0x0 + + * Suspend USB2.0 HS/FS/LS PHY (SusPHY) When set, USB2.0 PHY enters Suspend + * mode if Suspend conditions are valid. For DRD/OTG configurations, it is + * recommended that this bit is set to 0 during coreConsultant configurati + * on. If it is set to 1, then the application must clear this bit after po + * wer-on reset. Application needs to set it to 1 after the core initializa + * tion completes. For all other configurations, this bit can be set to 1 d + * uring core configuration. Note: - In host mode, on reset, this bit is se + * t to 1. Software can override this bit after reset. - In device mode, be + * fore issuing any device endpoint command when operating in 2.0 speeds, d + * isable this bit and enable it after the command completes. If you issue + * a command without disabling this bit when the device is in L2 state and + * if mac2_clk (utmi_clk/ulpi_clk) is gated off, the command will not get c + * ompleted. + * PSU_USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20 0x1 + + * Full-Speed Serial Interface Select (FSIntf) The application uses this bi + * t to select a unidirectional or bidirectional USB 1.1 full-speed serial + * transceiver interface. - 1'b0: 6-pin unidirectional full-speed serial in + * terface. This bit is set to 0 with Read Only access. - 1'b1: 3-pin bidir + * ectional full-speed serial interface. This bit is set to 0 with Read Onl + * y access. Note: USB 1.1 full-speed serial interface is not supported. Th + * is bit always reads as 1'b0. + * PSU_USB3_0_XHCI_GUSB2PHYCFG_FSINTF 0x0 + + * ULPI or UTMI+ Select (ULPI_UTMI_Sel) The application uses this bit to se + * lect a UTMI+ or ULPI Interface. - 1'b0: UTMI+ Interface - 1'b1: ULPI Int + * erface This bit is writable only if UTMI+ and ULPI is specified for High + * -Speed PHY Interface(s) in coreConsultant configuration (DWC_USB3_HSPHY_ + * INTERFACE = 3). Otherwise, this bit is read-only and the value depends o + * n the interface selected through DWC_USB3_HSPHY_INTERFACE. + * PSU_USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL 0x1 + + * PHY Interface (PHYIf) If UTMI+ is selected, the application uses this bi + * t to configure the core to support a UTMI+ PHY with an 8- or 16-bit inte + * rface. - 1'b0: 8 bits - 1'b1: 16 bits ULPI Mode: 1'b0 Note: - All the en + * abled 2.0 ports must have the same clock frequency as Port0 clock freque + * ncy (utmi_clk[0]). - The UTMI 8-bit and 16-bit modes cannot be used toge + * ther for different ports at the same time (that is, all the ports must b + * e in 8-bit mode, or all of them must be in 16-bit mode, at a time). - If + * any of the USB 2.0 ports is selected as ULPI port for operation, then a + * ll the USB 2.0 ports must be operating at 60 MHz. + * PSU_USB3_0_XHCI_GUSB2PHYCFG_PHYIF 0x0 + + * HS/FS Timeout Calibration (TOutCal) The number of PHY clocks, as indicat + * ed by the application in this field, is multiplied by a bit-time factor; + * this factor is added to the high-speed/full-speed interpacket timeout d + * uration in the core to account for additional delays introduced by the P + * HY. This may be required, since the delay introduced by the PHY in gener + * ating the linestate condition may vary among PHYs. The USB standard time + * out value for high-speed operation is 736 to 816 (inclusive) bit times. + * The USB standard timeout value for full-speed operation is 16 to 18 (inc + * lusive) bit times. The application must program this field based on the + * speed of connection. The number of bit times added per PHY clock are: Hi + * gh-speed operation: - One 30-MHz PHY clock = 16 bit times - One 60-MHz P + * HY clock = 8 bit times Full-speed operation: - One 30-MHz PHY clock = 0. + * 4 bit times - One 60-MHz PHY clock = 0.2 bit times - One 48-MHz PHY cloc + * k = 0.25 bit times + * PSU_USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL 0x7 + + * ULPI External VBUS Drive (ULPIExtVbusDrv) Selects supply source to drive + * 5V on VBUS, in the ULPI PHY. - 1'b0: PHY drives VBUS with internal char + * ge pump (default). - 1'b1: PHY drives VBUS with an external supply. (Onl + * y when RTL parameter DWC_USB3_HSPHY_INTERFACE = 2 or 3) + * PSU_USB3_0_XHCI_GUSB2PHYCFG_ULPIEXTVBUSDRV 0x1 + + * Global USB2 PHY Configuration Register The application must program this + * register before starting any transactions on either the SoC bus or the + * USB. In Device-only configurations, only one register is needed. In Host + * mode, per-port registers are implemented. + * (OFFSET, MASK, VALUE) (0XFE20C200, 0x00023FFFU ,0x00022457U) + */ + PSU_Mask_Write(USB3_0_XHCI_GUSB2PHYCFG_OFFSET, + 0x00023FFFU, 0x00022457U); +/*##################################################################### */ + + /* + * Register : GFLADJ @ 0XFE20C630 + + * This field indicates the frame length adjustment to be applied when SOF/ + * ITP counter is running on the ref_clk. This register value is used to ad + * just the ITP interval when GCTL[SOFITPSYNC] is set to '1'; SOF and ITP i + * nterval when GLADJ.GFLADJ_REFCLK_LPM_SEL is set to '1'. This field must + * be programmed to a non-zero value only if GFLADJ_REFCLK_LPM_SEL is set t + * o '1' or GCTL.SOFITPSYNC is set to '1'. The value is derived as follows: + * FLADJ_REF_CLK_FLADJ=((125000/ref_clk_period_integer)-(125000/ref_clk_pe + * riod)) * ref_clk_period where - the ref_clk_period_integer is the intege + * r value of the ref_clk period got by truncating the decimal (fractional) + * value that is programmed in the GUCTL.REF_CLK_PERIOD field. - the ref_c + * lk_period is the ref_clk period including the fractional value. Examples + * : If the ref_clk is 24 MHz then - GUCTL.REF_CLK_PERIOD = 41 - GFLADJ.GLA + * DJ_REFCLK_FLADJ = ((125000/41)-(125000/41.6666))*41.6666 = 2032 (ignorin + * g the fractional value) If the ref_clk is 48 MHz then - GUCTL.REF_CLK_PE + * RIOD = 20 - GFLADJ.GLADJ_REFCLK_FLADJ = ((125000/20)-(125000/20.8333))*2 + * 0.8333 = 5208 (ignoring the fractional value) + * PSU_USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ 0x0 + + * Global Frame Length Adjustment Register This register provides options f + * or the software to control the core behavior with respect to SOF (Start + * of Frame) and ITP (Isochronous Timestamp Packet) timers and frame timer + * functionality. It provides an option to override the fladj_30mhz_reg sid + * eband signal. In addition, it enables running SOF or ITP frame timer cou + * nters completely from the ref_clk. This facilitates hardware LPM in host + * mode with the SOF or ITP counters being run from the ref_clk signal. + * (OFFSET, MASK, VALUE) (0XFE20C630, 0x003FFF00U ,0x00000000U) + */ + PSU_Mask_Write(USB3_0_XHCI_GFLADJ_OFFSET, 0x003FFF00U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : GUCTL1 @ 0XFE20C11C + + * When this bit is set to '0', termsel, xcvrsel will become 0 during end o + * f resume while the opmode will become 0 once controller completes end of + * resume and enters U0 state (2 separate commandswill be issued). When th + * is bit is set to '1', all the termsel, xcvrsel, opmode becomes 0 during + * end of resume itself (only 1 command will be issued) + * PSU_USB3_0_XHCI_GUCTL1_RESUME_TERMSEL_XCVRSEL_UNIFY 0x1 + + * Reserved + * PSU_USB3_0_XHCI_GUCTL1_RESERVED_9 0x1 + + * Global User Control Register 1 + * (OFFSET, MASK, VALUE) (0XFE20C11C, 0x00000600U ,0x00000600U) + */ + PSU_Mask_Write(USB3_0_XHCI_GUCTL1_OFFSET, 0x00000600U, 0x00000600U); +/*##################################################################### */ + + /* + * Register : GUCTL @ 0XFE20C12C + + * Host IN Auto Retry (USBHstInAutoRetryEn) When set, this field enables th + * e Auto Retry feature. For IN transfers (non-isochronous) that encounter + * data packets with CRC errors or internal overrun scenarios, the auto ret + * ry feature causes the Host core to reply to the device with a non-termin + * ating retry ACK (that is, an ACK transaction packet with Retry = 1 and N + * umP != 0). If the Auto Retry feature is disabled (default), the core wil + * l respond with a terminating retry ACK (that is, an ACK transaction pack + * et with Retry = 1 and NumP = 0). - 1'b0: Auto Retry Disabled - 1'b1: Aut + * o Retry Enabled Note: This bit is also applicable to the device mode. + * PSU_USB3_0_XHCI_GUCTL_USBHSTINAUTORETRYEN 0x1 + + * Global User Control Register: This register provides a few options for t + * he software to control the core behavior in the Host mode. Most of the o + * ptions are used to improve host inter-operability with different devices + * . + * (OFFSET, MASK, VALUE) (0XFE20C12C, 0x00004000U ,0x00004000U) + */ + PSU_Mask_Write(USB3_0_XHCI_GUCTL_OFFSET, 0x00004000U, 0x00004000U); +/*##################################################################### */ + + /* + * UPDATING TWO PCIE REGISTERS DEFAULT VALUES, AS THESE REGISTERS HAVE INCO + * RRECT RESET VALUES IN SILICON. + */ + /* + * Register : ATTR_25 @ 0XFD480064 + + * If TRUE Completion Timeout Disable is supported. This is required to be + * TRUE for Endpoint and either setting allowed for Root ports. Drives Devi + * ce Capability 2 [4]; EP=0x0001; RP=0x0001 + * PSU_PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED 0X1 + + * ATTR_25 + * (OFFSET, MASK, VALUE) (0XFD480064, 0x00000200U ,0x00000200U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_25_OFFSET, 0x00000200U, 0x00000200U); +/*##################################################################### */ + + /* + * PCIE SETTINGS + */ + /* + * Register : ATTR_7 @ 0XFD48001C + + * Specifies mask/settings for Base Address Register (BAR) 0. If BAR is not + * to be implemented, set to 32'h00000000. Bits are defined as follows: Me + * mory Space BAR [0] = Mem Space Indicator (set to 0) [2:1] = Type field ( + * 10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask + * for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to 1, w + * here 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63: + * n bits of \'7bBAR1,BAR0\'7d to 1. IO Space BAR 0] = IO Space Indicator ( + * set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of B + * AR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; + * EP=0x0004; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_7_ATTR_BAR0 0x0 + + * ATTR_7 + * (OFFSET, MASK, VALUE) (0XFD48001C, 0x0000FFFFU ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_7_OFFSET, 0x0000FFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_8 @ 0XFD480020 + + * Specifies mask/settings for Base Address Register (BAR) 0. If BAR is not + * to be implemented, set to 32'h00000000. Bits are defined as follows: Me + * mory Space BAR [0] = Mem Space Indicator (set to 0) [2:1] = Type field ( + * 10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask + * for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to 1, w + * here 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63: + * n bits of \'7bBAR1,BAR0\'7d to 1. IO Space BAR 0] = IO Space Indicator ( + * set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of B + * AR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; + * EP=0xFFF0; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_8_ATTR_BAR0 0x0 + + * ATTR_8 + * (OFFSET, MASK, VALUE) (0XFD480020, 0x0000FFFFU ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_8_OFFSET, 0x0000FFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_9 @ 0XFD480024 + + * Specifies mask/settings for Base Address Register (BAR) 1 if BAR0 is a 3 + * 2-bit BAR, or the upper bits of \'7bBAR1,BAR0\'7d if BAR0 is a 64-bit BA + * R. If BAR is not to be implemented, set to 32'h00000000. See BAR0 descri + * ption if this functions as the upper bits of a 64-bit BAR. Bits are defi + * ned as follows: Memory Space BAR (not upper bits of BAR0) [0] = Mem Spac + * e Indicator (set to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) + * [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if + * 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size + * in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR2,BAR1\'7d t + * o 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set + * to 0) [31:2] = Mask for writable bits of BAR; set uppermost 31:n bits t + * o 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_9_ATTR_BAR1 0x0 + + * ATTR_9 + * (OFFSET, MASK, VALUE) (0XFD480024, 0x0000FFFFU ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_9_OFFSET, 0x0000FFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_10 @ 0XFD480028 + + * Specifies mask/settings for Base Address Register (BAR) 1 if BAR0 is a 3 + * 2-bit BAR, or the upper bits of \'7bBAR1,BAR0\'7d if BAR0 is a 64-bit BA + * R. If BAR is not to be implemented, set to 32'h00000000. See BAR0 descri + * ption if this functions as the upper bits of a 64-bit BAR. Bits are defi + * ned as follows: Memory Space BAR (not upper bits of BAR0) [0] = Mem Spac + * e Indicator (set to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) + * [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if + * 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size + * in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR2,BAR1\'7d t + * o 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set + * to 0) [31:2] = Mask for writable bits of BAR; set uppermost 31:n bits t + * o 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_10_ATTR_BAR1 0x0 + + * ATTR_10 + * (OFFSET, MASK, VALUE) (0XFD480028, 0x0000FFFFU ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_10_OFFSET, 0x0000FFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_11 @ 0XFD48002C + + * For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 2 if BAR1 is a 32-bit BAR, or the upper bits of \'7bBAR2,BAR1\'7d if BA + * R1 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR1 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root: This must be set to 00FF_FFF + * F. For an endpoint, bits are defined as follows: Memory Space BAR (not u + * pper bits of BAR1) [0] = Mem Space Indicator (set to 0) [2:1] = Type fie + * ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = M + * ask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to + * 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost + * 63:n bits of \'7bBAR3,BAR2\'7d to 1. IO Space BAR 0] = IO Space Indicat + * or (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits + * of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in byt + * es.; EP=0x0004; RP=0xFFFF + * PSU_PCIE_ATTRIB_ATTR_11_ATTR_BAR2 0xFFFF + + * ATTR_11 + * (OFFSET, MASK, VALUE) (0XFD48002C, 0x0000FFFFU ,0x0000FFFFU) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_11_OFFSET, 0x0000FFFFU, 0x0000FFFFU); +/*##################################################################### */ + + /* + * Register : ATTR_12 @ 0XFD480030 + + * For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 2 if BAR1 is a 32-bit BAR, or the upper bits of \'7bBAR2,BAR1\'7d if BA + * R1 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR1 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root: This must be set to 00FF_FFF + * F. For an endpoint, bits are defined as follows: Memory Space BAR (not u + * pper bits of BAR1) [0] = Mem Space Indicator (set to 0) [2:1] = Type fie + * ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = M + * ask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to + * 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost + * 63:n bits of \'7bBAR3,BAR2\'7d to 1. IO Space BAR 0] = IO Space Indicat + * or (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits + * of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in byt + * es.; EP=0xFFF0; RP=0x00FF + * PSU_PCIE_ATTRIB_ATTR_12_ATTR_BAR2 0xFF + + * ATTR_12 + * (OFFSET, MASK, VALUE) (0XFD480030, 0x0000FFFFU ,0x000000FFU) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_12_OFFSET, 0x0000FFFFU, 0x000000FFU); +/*##################################################################### */ + + /* + * Register : ATTR_13 @ 0XFD480034 + + * For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 3 if BAR2 is a 32-bit BAR, or the upper bits of \'7bBAR3,BAR2\'7d if BA + * R2 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR2 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root, this must be set to: FFFF_00 + * 00 = IO Limit/Base Registers not implemented FFFF_F0F0 = IO Limit/Base R + * egisters use 16-bit decode FFFF_F1F1 = IO Limit/Base Registers use 32-bi + * t decode For an endpoint, bits are defined as follows: Memory Space BAR + * (not upper bits of BAR2) [0] = Mem Space Indicator (set to 0) [2:1] = Ty + * pe field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31: + * 4] = Mask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bi + * ts to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set upp + * ermost 63:n bits of \'7bBAR4,BAR3\'7d to 1. IO Space BAR 0] = IO Space I + * ndicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable + * bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size + * in bytes.; EP=0xFFFF; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_13_ATTR_BAR3 0x0 + + * ATTR_13 + * (OFFSET, MASK, VALUE) (0XFD480034, 0x0000FFFFU ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_13_OFFSET, 0x0000FFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_14 @ 0XFD480038 + + * For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 3 if BAR2 is a 32-bit BAR, or the upper bits of \'7bBAR3,BAR2\'7d if BA + * R2 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR2 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root, this must be set to: FFFF_00 + * 00 = IO Limit/Base Registers not implemented FFFF_F0F0 = IO Limit/Base R + * egisters use 16-bit decode FFFF_F1F1 = IO Limit/Base Registers use 32-bi + * t decode For an endpoint, bits are defined as follows: Memory Space BAR + * (not upper bits of BAR2) [0] = Mem Space Indicator (set to 0) [2:1] = Ty + * pe field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31: + * 4] = Mask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bi + * ts to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set upp + * ermost 63:n bits of \'7bBAR4,BAR3\'7d to 1. IO Space BAR 0] = IO Space I + * ndicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable + * bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size + * in bytes.; EP=0xFFFF; RP=0xFFFF + * PSU_PCIE_ATTRIB_ATTR_14_ATTR_BAR3 0xFFFF + + * ATTR_14 + * (OFFSET, MASK, VALUE) (0XFD480038, 0x0000FFFFU ,0x0000FFFFU) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_14_OFFSET, 0x0000FFFFU, 0x0000FFFFU); +/*##################################################################### */ + + /* + * Register : ATTR_15 @ 0XFD48003C + + * For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 4 if BAR3 is a 32-bit BAR, or the upper bits of \'7bBAR4,BAR3\'7d if BA + * R3 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR3 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root: This must be set to FFF0_FFF + * 0. For an endpoint, bits are defined as follows: Memory Space BAR (not u + * pper bits of BAR3) [0] = Mem Space Indicator (set to 0) [2:1] = Type fie + * ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = M + * ask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to + * 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost + * 63:n bits of \'7bBAR5,BAR4\'7d to 1. IO Space BAR 0] = IO Space Indicat + * or (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits + * of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in byt + * es.; EP=0x0004; RP=0xFFF0 + * PSU_PCIE_ATTRIB_ATTR_15_ATTR_BAR4 0xFFF0 + + * ATTR_15 + * (OFFSET, MASK, VALUE) (0XFD48003C, 0x0000FFFFU ,0x0000FFF0U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_15_OFFSET, 0x0000FFFFU, 0x0000FFF0U); +/*##################################################################### */ + + /* + * Register : ATTR_16 @ 0XFD480040 + + * For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 4 if BAR3 is a 32-bit BAR, or the upper bits of \'7bBAR4,BAR3\'7d if BA + * R3 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR3 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root: This must be set to FFF0_FFF + * 0. For an endpoint, bits are defined as follows: Memory Space BAR (not u + * pper bits of BAR3) [0] = Mem Space Indicator (set to 0) [2:1] = Type fie + * ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = M + * ask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to + * 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost + * 63:n bits of \'7bBAR5,BAR4\'7d to 1. IO Space BAR 0] = IO Space Indicat + * or (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits + * of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in byt + * es.; EP=0xFFF0; RP=0xFFF0 + * PSU_PCIE_ATTRIB_ATTR_16_ATTR_BAR4 0xFFF0 + + * ATTR_16 + * (OFFSET, MASK, VALUE) (0XFD480040, 0x0000FFFFU ,0x0000FFF0U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_16_OFFSET, 0x0000FFFFU, 0x0000FFF0U); +/*##################################################################### */ + + /* + * Register : ATTR_17 @ 0XFD480044 + + * For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 5 if BAR4 is a 32-bit BAR, or the upper bits of \'7bBAR5,BAR4\'7d if BA + * R4 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR4 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root, this must be set to: 0000_00 + * 00 = Prefetchable Memory Limit/Base Registers not implemented FFF0_FFF0 + * = 32-bit Prefetchable Memory Limit/Base implemented FFF1_FFF1 = 64-bit P + * refetchable Memory Limit/Base implemented For an endpoint, bits are defi + * ned as follows: Memory Space BAR (not upper bits of BAR4) [0] = Mem Spac + * e Indicator (set to 0) [2:1] = Type field (00 for 32-bit; BAR5 cannot be + * lower part of a 64-bit BAR) [3] = Prefetchable (0 or 1) [31:4] = Mask f + * or writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=memory + * aperture size in bytes. IO Space BAR 0] = IO Space Indicator (set to 1) + * [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set up + * permost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF + * ; RP=0xFFF1 + * PSU_PCIE_ATTRIB_ATTR_17_ATTR_BAR5 0xFFF1 + + * ATTR_17 + * (OFFSET, MASK, VALUE) (0XFD480044, 0x0000FFFFU ,0x0000FFF1U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_17_OFFSET, 0x0000FFFFU, 0x0000FFF1U); +/*##################################################################### */ + + /* + * Register : ATTR_18 @ 0XFD480048 + + * For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 5 if BAR4 is a 32-bit BAR, or the upper bits of \'7bBAR5,BAR4\'7d if BA + * R4 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR4 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root, this must be set to: 0000_00 + * 00 = Prefetchable Memory Limit/Base Registers not implemented FFF0_FFF0 + * = 32-bit Prefetchable Memory Limit/Base implemented FFF1_FFF1 = 64-bit P + * refetchable Memory Limit/Base implemented For an endpoint, bits are defi + * ned as follows: Memory Space BAR (not upper bits of BAR4) [0] = Mem Spac + * e Indicator (set to 0) [2:1] = Type field (00 for 32-bit; BAR5 cannot be + * lower part of a 64-bit BAR) [3] = Prefetchable (0 or 1) [31:4] = Mask f + * or writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=memory + * aperture size in bytes. IO Space BAR 0] = IO Space Indicator (set to 1) + * [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set up + * permost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF + * ; RP=0xFFF1 + * PSU_PCIE_ATTRIB_ATTR_18_ATTR_BAR5 0xFFF1 + + * ATTR_18 + * (OFFSET, MASK, VALUE) (0XFD480048, 0x0000FFFFU ,0x0000FFF1U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_18_OFFSET, 0x0000FFFFU, 0x0000FFF1U); +/*##################################################################### */ + + /* + * Register : ATTR_27 @ 0XFD48006C + + * Specifies maximum payload supported. Valid settings are: 0- 128 bytes, 1 + * - 256 bytes, 2- 512 bytes, 3- 1024 bytes. Transferred to the Device Capa + * bilities register. The values: 4-2048 bytes, 5- 4096 bytes are not suppo + * rted; EP=0x0001; RP=0x0001 + * PSU_PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED 1 + + * Endpoint L1 Acceptable Latency. Records the latency that the endpoint ca + * n withstand on transitions from L1 state to L0 (if L1 state supported). + * Valid settings are: 0h less than 1us, 1h 1 to 2us, 2h 2 to 4us, 3h 4 to + * 8us, 4h 8 to 16us, 5h 16 to 32us, 6h 32 to 64us, 7h more than 64us. For + * Endpoints only. Must be 0h for other devices.; EP=0x0007; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY 0x0 + + * ATTR_27 + * (OFFSET, MASK, VALUE) (0XFD48006C, 0x00000738U ,0x00000100U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_27_OFFSET, 0x00000738U, 0x00000100U); +/*##################################################################### */ + + /* + * Register : ATTR_50 @ 0XFD4800C8 + + * Identifies the type of device/port as follows: 0000b PCI Express Endpoin + * t device, 0001b Legacy PCI Express Endpoint device, 0100b Root Port of P + * CI Express Root Complex, 0101b Upstream Port of PCI Express Switch, 0110 + * b Downstream Port of PCI Express Switch, 0111b PCIE Express to PCI/PCI-X + * Bridge, 1000b PCI/PCI-X to PCI Express Bridge. Transferred to PCI Expre + * ss Capabilities register. Must be consistent with IS_SWITCH and UPSTREAM + * _FACING settings.; EP=0x0000; RP=0x0004 + * PSU_PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE 4 + + * PCIe Capability's Next Capability Offset pointer to the next item in the + * capabilities list, or 00h if this is the final capability.; EP=0x009C; + * RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR 0 + + * ATTR_50 + * (OFFSET, MASK, VALUE) (0XFD4800C8, 0x0000FFF0U ,0x00000040U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_50_OFFSET, 0x0000FFF0U, 0x00000040U); +/*##################################################################### */ + + /* + * Register : ATTR_105 @ 0XFD4801A4 + + * Number of credits that should be advertised for Completion data received + * on Virtual Channel 0. The bytes advertised must be less than or equal t + * o the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0172; RP=0x00CD + * PSU_PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD 0xCD + + * ATTR_105 + * (OFFSET, MASK, VALUE) (0XFD4801A4, 0x000007FFU ,0x000000CDU) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_105_OFFSET, + 0x000007FFU, 0x000000CDU); +/*##################################################################### */ + + /* + * Register : ATTR_106 @ 0XFD4801A8 + + * Number of credits that should be advertised for Completion headers recei + * ved on Virtual Channel 0. The sum of the posted, non posted, and complet + * ion header credits must be <= 80; EP=0x0048; RP=0x0024 + * PSU_PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH 0x24 + + * Number of credits that should be advertised for Non-Posted headers recei + * ved on Virtual Channel 0. The number of non posted data credits advertis + * ed by the block is equal to the number of non posted header credits. The + * sum of the posted, non posted, and completion header credits must be <= + * 80; EP=0x0004; RP=0x000C + * PSU_PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH 0xC + + * ATTR_106 + * (OFFSET, MASK, VALUE) (0XFD4801A8, 0x00003FFFU ,0x00000624U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_106_OFFSET, + 0x00003FFFU, 0x00000624U); +/*##################################################################### */ + + /* + * Register : ATTR_107 @ 0XFD4801AC + + * Number of credits that should be advertised for Non-Posted data received + * on Virtual Channel 0. The number of non posted data credits advertised + * by the block is equal to two times the number of non posted header credi + * ts if atomic operations are supported or is equal to the number of non p + * osted header credits if atomic operations are not supported. The bytes a + * dvertised must be less than or equal to the bram bytes available. See VC + * 0_RX_RAM_LIMIT; EP=0x0008; RP=0x0018 + * PSU_PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD 0x18 + + * ATTR_107 + * (OFFSET, MASK, VALUE) (0XFD4801AC, 0x000007FFU ,0x00000018U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_107_OFFSET, + 0x000007FFU, 0x00000018U); +/*##################################################################### */ + + /* + * Register : ATTR_108 @ 0XFD4801B0 + + * Number of credits that should be advertised for Posted data received on + * Virtual Channel 0. The bytes advertised must be less than or equal to th + * e bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0020; RP=0x00B5 + * PSU_PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD 0xB5 + + * ATTR_108 + * (OFFSET, MASK, VALUE) (0XFD4801B0, 0x000007FFU ,0x000000B5U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_108_OFFSET, + 0x000007FFU, 0x000000B5U); +/*##################################################################### */ + + /* + * Register : ATTR_109 @ 0XFD4801B4 + + * Not currently in use. Invert ECRC generated by block when trn_tecrc_gen_ + * n and trn_terrfwd_n are asserted.; EP=0x0000; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV 0x0 + + * Enables td bit clear and ECRC trim on received TLP's FALSE == don't trim + * TRUE == trim.; EP=0x0001; RP=0x0001 + * PSU_PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM 0x1 + + * Enables ECRC check on received TLP's 0 == don't check 1 == always check + * 3 == check if enabled by ECRC check enable bit of AER cap structure; EP= + * 0x0003; RP=0x0003 + * PSU_PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK 0x3 + + * Index of last packet buffer used by TX TLM (i.e. number of buffers - 1). + * Calculated from max payload size supported and the number of brams conf + * igured for transmit; EP=0x001C; RP=0x001C + * PSU_PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET 0x1c + + * Number of credits that should be advertised for Posted headers received + * on Virtual Channel 0. The sum of the posted, non posted, and completion + * header credits must be <= 80; EP=0x0004; RP=0x0020 + * PSU_PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH 0x20 + + * ATTR_109 + * (OFFSET, MASK, VALUE) (0XFD4801B4, 0x0000FFFFU ,0x00007E20U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_109_OFFSET, + 0x0000FFFFU, 0x00007E20U); +/*##################################################################### */ + + /* + * Register : ATTR_34 @ 0XFD480088 + + * Specifies values to be transferred to Header Type register. Bit 7 should + * be set to '0' indicating single-function device. Bit 0 identifies heade + * r as Type 0 or Type 1, with '0' indicating a Type 0 header.; EP=0x0000; + * RP=0x0001 + * PSU_PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE 0x1 + + * ATTR_34 + * (OFFSET, MASK, VALUE) (0XFD480088, 0x000000FFU ,0x00000001U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_34_OFFSET, 0x000000FFU, 0x00000001U); +/*##################################################################### */ + + /* + * Register : ATTR_53 @ 0XFD4800D4 + + * PM Capability's Next Capability Offset pointer to the next item in the c + * apabilities list, or 00h if this is the final capability.; EP=0x0048; RP + * =0x0060 + * PSU_PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR 0x60 + + * ATTR_53 + * (OFFSET, MASK, VALUE) (0XFD4800D4, 0x000000FFU ,0x00000060U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_53_OFFSET, 0x000000FFU, 0x00000060U); +/*##################################################################### */ + + /* + * Register : ATTR_41 @ 0XFD4800A4 + + * MSI Per-Vector Masking Capable. The value is transferred to the MSI Cont + * rol Register[8]. When set, adds Mask and Pending Dword to Cap structure; + * EP=0x0000; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE 0x0 + + * Indicates that the MSI structures exists. If this is FALSE, then the MSI + * structure cannot be accessed via either the link or the management port + * .; EP=0x0001; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON 0 + + * MSI Capability's Next Capability Offset pointer to the next item in the + * capabilities list, or 00h if this is the final capability.; EP=0x0060; R + * P=0x0000 + * PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR 0x0 + + * Indicates that the MSI structures exists. If this is FALSE, then the MSI + * structure cannot be accessed via either the link or the management port + * .; EP=0x0001; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON 0 + + * ATTR_41 + * (OFFSET, MASK, VALUE) (0XFD4800A4, 0x000003FFU ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_41_OFFSET, 0x000003FFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_97 @ 0XFD480184 + + * Maximum Link Width. Valid settings are: 000001b x1, 000010b x2, 000100b + * x4, 001000b x8.; EP=0x0004; RP=0x0004 + * PSU_PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH 0x1 + + * Used by LTSSM to set Maximum Link Width. Valid settings are: 000001b [x1 + * ], 000010b [x2], 000100b [x4], 001000b [x8].; EP=0x0004; RP=0x0004 + * PSU_PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH 0x1 + + * ATTR_97 + * (OFFSET, MASK, VALUE) (0XFD480184, 0x00000FFFU ,0x00000041U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_97_OFFSET, 0x00000FFFU, 0x00000041U); +/*##################################################################### */ + + /* + * Register : ATTR_100 @ 0XFD480190 + + * TRUE specifies upstream-facing port. FALSE specifies downstream-facing p + * ort.; EP=0x0001; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING 0x0 + + * ATTR_100 + * (OFFSET, MASK, VALUE) (0XFD480190, 0x00000040U ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_100_OFFSET, + 0x00000040U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_101 @ 0XFD480194 + + * Enable the routing of message TLPs to the user through the TRN RX interf + * ace. A bit value of 1 enables routing of the message TLP to the user. Me + * ssages are always decoded by the message decoder. Bit 0 - ERR COR, Bit 1 + * - ERR NONFATAL, Bit 2 - ERR FATAL, Bit 3 - INTA Bit 4 - INTB, Bit 5 - I + * NTC, Bit 6 - INTD, Bit 7 PM_PME, Bit 8 - PME_TO_ACK, Bit 9 - unlock, Bit + * 10 PME_Turn_Off; EP=0x0000; RP=0x07FF + * PSU_PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE 0x7FF + + * Disable BAR filtering. Does not change the behavior of the bar hit outpu + * ts; EP=0x0000; RP=0x0001 + * PSU_PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING 0x1 + + * ATTR_101 + * (OFFSET, MASK, VALUE) (0XFD480194, 0x0000FFE2U ,0x0000FFE2U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_101_OFFSET, + 0x0000FFE2U, 0x0000FFE2U); +/*##################################################################### */ + + /* + * Register : ATTR_37 @ 0XFD480094 + + * Link Bandwidth notification capability. Indicates support for the link b + * andwidth notification status and interrupt mechanism. Required for Root. + * ; EP=0x0000; RP=0x0001 + * PSU_PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP 0x1 + + * Sets the ASPM Optionality Compliance bit, to comply with the 2.1 ASPM Op + * tionality ECN. Transferred to the Link Capabilities register.; EP=0x0001 + * ; RP=0x0001 + * PSU_PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY 0x1 + + * ATTR_37 + * (OFFSET, MASK, VALUE) (0XFD480094, 0x00004200U ,0x00004200U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_37_OFFSET, 0x00004200U, 0x00004200U); +/*##################################################################### */ + + /* + * Register : ATTR_93 @ 0XFD480174 + + * Enables the Replay Timer to use the user-defined LL_REPLAY_TIMEOUT value + * (or combined with the built-in value, depending on LL_REPLAY_TIMEOUT_FU + * NC). If FALSE, the built-in value is used.; EP=0x0000; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN 0x1 + + * Sets a user-defined timeout for the Replay Timer to force cause the retr + * ansmission of unacknowledged TLPs; refer to LL_REPLAY_TIMEOUT_EN and LL_ + * REPLAY_TIMEOUT_FUNC to see how this value is used. The unit for this att + * ribute is in symbol times, which is 4ns at GEN1 speeds and 2ns at GEN2.; + * EP=0x0000; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT 0x1000 + + * ATTR_93 + * (OFFSET, MASK, VALUE) (0XFD480174, 0x0000FFFFU ,0x00009000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_93_OFFSET, 0x0000FFFFU, 0x00009000U); +/*##################################################################### */ + + /* + * Register : ID @ 0XFD480200 + + * Device ID for the the PCIe Cap Structure Device ID field + * PSU_PCIE_ATTRIB_ID_CFG_DEV_ID 0xd021 + + * Vendor ID for the PCIe Cap Structure Vendor ID field + * PSU_PCIE_ATTRIB_ID_CFG_VEND_ID 0x10ee + + * ID + * (OFFSET, MASK, VALUE) (0XFD480200, 0xFFFFFFFFU ,0x10EED021U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ID_OFFSET, 0xFFFFFFFFU, 0x10EED021U); +/*##################################################################### */ + + /* + * Register : SUBSYS_ID @ 0XFD480204 + + * Subsystem ID for the the PCIe Cap Structure Subsystem ID field + * PSU_PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID 0x7 + + * Subsystem Vendor ID for the PCIe Cap Structure Subsystem Vendor ID field + * PSU_PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID 0x10ee + + * SUBSYS_ID + * (OFFSET, MASK, VALUE) (0XFD480204, 0xFFFFFFFFU ,0x10EE0007U) + */ + PSU_Mask_Write(PCIE_ATTRIB_SUBSYS_ID_OFFSET, + 0xFFFFFFFFU, 0x10EE0007U); +/*##################################################################### */ + + /* + * Register : REV_ID @ 0XFD480208 + + * Revision ID for the the PCIe Cap Structure + * PSU_PCIE_ATTRIB_REV_ID_CFG_REV_ID 0x0 + + * REV_ID + * (OFFSET, MASK, VALUE) (0XFD480208, 0x000000FFU ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_REV_ID_OFFSET, 0x000000FFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_24 @ 0XFD480060 + + * Code identifying basic function, subclass and applicable programming int + * erface. Transferred to the Class Code register.; EP=0x8000; RP=0x8000 + * PSU_PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE 0x400 + + * ATTR_24 + * (OFFSET, MASK, VALUE) (0XFD480060, 0x0000FFFFU ,0x00000400U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_24_OFFSET, 0x0000FFFFU, 0x00000400U); +/*##################################################################### */ + + /* + * Register : ATTR_25 @ 0XFD480064 + + * Code identifying basic function, subclass and applicable programming int + * erface. Transferred to the Class Code register.; EP=0x0005; RP=0x0006 + * PSU_PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE 0x6 + + * INTX Interrupt Generation Capable. If FALSE, this will cause Command[10] + * to be hardwired to 0.; EP=0x0001; RP=0x0001 + * PSU_PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED 0 + + * ATTR_25 + * (OFFSET, MASK, VALUE) (0XFD480064, 0x000001FFU ,0x00000006U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_25_OFFSET, 0x000001FFU, 0x00000006U); +/*##################################################################### */ + + /* + * Register : ATTR_4 @ 0XFD480010 + + * Indicates that the AER structures exists. If this is FALSE, then the AER + * structure cannot be accessed via either the link or the management port + * , and AER will be considered to not be present for error management task + * s (such as what types of error messages are sent if an error is detected + * ).; EP=0x0001; RP=0x0001 + * PSU_PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON 0 + + * Indicates that the AER structures exists. If this is FALSE, then the AER + * structure cannot be accessed via either the link or the management port + * , and AER will be considered to not be present for error management task + * s (such as what types of error messages are sent if an error is detected + * ).; EP=0x0001; RP=0x0001 + * PSU_PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON 0 + + * ATTR_4 + * (OFFSET, MASK, VALUE) (0XFD480010, 0x00001000U ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_4_OFFSET, 0x00001000U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_89 @ 0XFD480164 + + * VSEC's Next Capability Offset pointer to the next item in the capabiliti + * es list, or 000h if this is the final capability.; EP=0x0140; RP=0x0140 + * PSU_PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR 0 + + * ATTR_89 + * (OFFSET, MASK, VALUE) (0XFD480164, 0x00001FFEU ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_89_OFFSET, 0x00001FFEU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_79 @ 0XFD48013C + + * CRS SW Visibility. Indicates RC can return CRS to SW. Transferred to the + * Root Capabilities register.; EP=0x0000; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY 1 + + * ATTR_79 + * (OFFSET, MASK, VALUE) (0XFD48013C, 0x00000020U ,0x00000020U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_79_OFFSET, 0x00000020U, 0x00000020U); +/*##################################################################### */ + + /* + * Register : ATTR_43 @ 0XFD4800AC + + * Indicates that the MSIX structures exists. If this is FALSE, then the MS + * IX structure cannot be accessed via either the link or the management po + * rt.; EP=0x0001; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON 0 + + * ATTR_43 + * (OFFSET, MASK, VALUE) (0XFD4800AC, 0x00000100U ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_43_OFFSET, 0x00000100U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_48 @ 0XFD4800C0 + + * MSI-X Table Size. This value is transferred to the MSI-X Message Control + * [10:0] field. Set to 0 if MSI-X is not enabled. Note that the core does + * not implement the table; that must be implemented in user logic.; EP=0x0 + * 003; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE 0 + + * ATTR_48 + * (OFFSET, MASK, VALUE) (0XFD4800C0, 0x000007FFU ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_48_OFFSET, 0x000007FFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_46 @ 0XFD4800B8 + + * MSI-X Table Offset. This value is transferred to the MSI-X Table Offset + * field. Set to 0 if MSI-X is not enabled.; EP=0x0001; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET 0 + + * ATTR_46 + * (OFFSET, MASK, VALUE) (0XFD4800B8, 0x0000FFFFU ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_46_OFFSET, 0x0000FFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_47 @ 0XFD4800BC + + * MSI-X Table Offset. This value is transferred to the MSI-X Table Offset + * field. Set to 0 if MSI-X is not enabled.; EP=0x0000; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET 0 + + * ATTR_47 + * (OFFSET, MASK, VALUE) (0XFD4800BC, 0x00001FFFU ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_47_OFFSET, 0x00001FFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_44 @ 0XFD4800B0 + + * MSI-X Pending Bit Array Offset This value is transferred to the MSI-X PB + * A Offset field. Set to 0 if MSI-X is not enabled.; EP=0x0001; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET 0 + + * ATTR_44 + * (OFFSET, MASK, VALUE) (0XFD4800B0, 0x0000FFFFU ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_44_OFFSET, 0x0000FFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_45 @ 0XFD4800B4 + + * MSI-X Pending Bit Array Offset This value is transferred to the MSI-X PB + * A Offset field. Set to 0 if MSI-X is not enabled.; EP=0x1000; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET 0 + + * ATTR_45 + * (OFFSET, MASK, VALUE) (0XFD4800B4, 0x0000FFF8U ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_45_OFFSET, 0x0000FFF8U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : CB @ 0XFD48031C + + * DT837748 Enable + * PSU_PCIE_ATTRIB_CB_CB1 0x0 + + * ECO Register 1 + * (OFFSET, MASK, VALUE) (0XFD48031C, 0x00000002U ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_CB_OFFSET, 0x00000002U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_35 @ 0XFD48008C + + * Active State PM Support. Indicates the level of active state power manag + * ement supported by the selected PCI Express Link, encoded as follows: 0 + * Reserved, 1 L0s entry supported, 2 Reserved, 3 L0s and L1 entry supporte + * d.; EP=0x0001; RP=0x0001 + * PSU_PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT 0x0 + + * ATTR_35 + * (OFFSET, MASK, VALUE) (0XFD48008C, 0x00003000U ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_35_OFFSET, 0x00003000U, 0x00000000U); +/*##################################################################### */ + + /* + * PUTTING PCIE CONTROL IN RESET + */ + /* + * Register : RST_FPD_TOP @ 0XFD1A0100 + + * PCIE control block level reset + * PSU_CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET 0X0 + + * FPD Block level software controlled reset + * (OFFSET, MASK, VALUE) (0XFD1A0100, 0x00020000U ,0x00000000U) + */ + PSU_Mask_Write(CRF_APB_RST_FPD_TOP_OFFSET, 0x00020000U, 0x00000000U); +/*##################################################################### */ + + /* + * PCIE GPIO RESET + */ + /* + * MASK_DATA_0_LSW LOW BANK [15:0] + */ + /* + * MASK_DATA_0_MSW LOW BANK [25:16] + */ + /* + * MASK_DATA_1_LSW LOW BANK [41:26] + */ + /* + * Register : MASK_DATA_1_LSW @ 0XFF0A0008 + + * Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW] + * PSU_GPIO_MASK_DATA_1_LSW_MASK_1_LSW 0xffdf + + * Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW] + * PSU_GPIO_MASK_DATA_1_LSW_DATA_1_LSW 0x20 + + * Maskable Output Data (GPIO Bank1, MIO, Lower 16bits) + * (OFFSET, MASK, VALUE) (0XFF0A0008, 0xFFFFFFFFU ,0xFFDF0020U) + */ + PSU_Mask_Write(GPIO_MASK_DATA_1_LSW_OFFSET, + 0xFFFFFFFFU, 0xFFDF0020U); +/*##################################################################### */ + + /* + * MASK_DATA_1_MSW HIGH BANK [51:42] + */ + /* + * MASK_DATA_1_LSW HIGH BANK [67:52] + */ + /* + * MASK_DATA_1_LSW HIGH BANK [77:68] + */ + /* + * CHECK PLL LOCK FOR LANE0 + */ + /* + * Register : L0_PLL_STATUS_READ_1 @ 0XFD4023E4 + + * Status Read value of PLL Lock + * PSU_SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1 + * (OFFSET, MASK, VALUE) (0XFD4023E4, 0x00000010U ,0x00000010U) + */ + mask_poll(SERDES_L0_PLL_STATUS_READ_1_OFFSET, 0x00000010U); + +/*##################################################################### */ + + /* + * CHECK PLL LOCK FOR LANE1 + */ + /* + * Register : L1_PLL_STATUS_READ_1 @ 0XFD4063E4 + + * Status Read value of PLL Lock + * PSU_SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1 + * (OFFSET, MASK, VALUE) (0XFD4063E4, 0x00000010U ,0x00000010U) + */ + mask_poll(SERDES_L1_PLL_STATUS_READ_1_OFFSET, 0x00000010U); + +/*##################################################################### */ + + /* + * CHECK PLL LOCK FOR LANE2 + */ + /* + * Register : L2_PLL_STATUS_READ_1 @ 0XFD40A3E4 + + * Status Read value of PLL Lock + * PSU_SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1 + * (OFFSET, MASK, VALUE) (0XFD40A3E4, 0x00000010U ,0x00000010U) + */ + mask_poll(SERDES_L2_PLL_STATUS_READ_1_OFFSET, 0x00000010U); + +/*##################################################################### */ + + /* + * CHECK PLL LOCK FOR LANE3 + */ + /* + * Register : L3_PLL_STATUS_READ_1 @ 0XFD40E3E4 + + * Status Read value of PLL Lock + * PSU_SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1 + * (OFFSET, MASK, VALUE) (0XFD40E3E4, 0x00000010U ,0x00000010U) + */ + mask_poll(SERDES_L3_PLL_STATUS_READ_1_OFFSET, 0x00000010U); + +/*##################################################################### */ + + /* + * SATA AHCI VENDOR SETTING + */ + /* + * Register : PP2C @ 0XFD0C00AC + + * CIBGMN: COMINIT Burst Gap Minimum. + * PSU_SATA_AHCI_VENDOR_PP2C_CIBGMN 0x18 + + * CIBGMX: COMINIT Burst Gap Maximum. + * PSU_SATA_AHCI_VENDOR_PP2C_CIBGMX 0x40 + + * CIBGN: COMINIT Burst Gap Nominal. + * PSU_SATA_AHCI_VENDOR_PP2C_CIBGN 0x18 + + * CINMP: COMINIT Negate Minimum Period. + * PSU_SATA_AHCI_VENDOR_PP2C_CINMP 0x28 + + * PP2C - Port Phy2Cfg Register. This register controls the configuration o + * f the Phy Control OOB timing for the COMINIT parameters for either Port + * 0 or Port 1. The Port configured is controlled by the value programmed i + * nto the Port Config Register. + * (OFFSET, MASK, VALUE) (0XFD0C00AC, 0xFFFFFFFFU ,0x28184018U) + */ + PSU_Mask_Write(SATA_AHCI_VENDOR_PP2C_OFFSET, + 0xFFFFFFFFU, 0x28184018U); +/*##################################################################### */ + + /* + * Register : PP3C @ 0XFD0C00B0 + + * CWBGMN: COMWAKE Burst Gap Minimum. + * PSU_SATA_AHCI_VENDOR_PP3C_CWBGMN 0x06 + + * CWBGMX: COMWAKE Burst Gap Maximum. + * PSU_SATA_AHCI_VENDOR_PP3C_CWBGMX 0x14 + + * CWBGN: COMWAKE Burst Gap Nominal. + * PSU_SATA_AHCI_VENDOR_PP3C_CWBGN 0x08 + + * CWNMP: COMWAKE Negate Minimum Period. + * PSU_SATA_AHCI_VENDOR_PP3C_CWNMP 0x0E + + * PP3C - Port Phy3CfgRegister. This register controls the configuration of + * the Phy Control OOB timing for the COMWAKE parameters for either Port 0 + * or Port 1. The Port configured is controlled by the value programmed in + * to the Port Config Register. + * (OFFSET, MASK, VALUE) (0XFD0C00B0, 0xFFFFFFFFU ,0x0E081406U) + */ + PSU_Mask_Write(SATA_AHCI_VENDOR_PP3C_OFFSET, + 0xFFFFFFFFU, 0x0E081406U); +/*##################################################################### */ + + /* + * Register : PP4C @ 0XFD0C00B4 + + * BMX: COM Burst Maximum. + * PSU_SATA_AHCI_VENDOR_PP4C_BMX 0x13 + + * BNM: COM Burst Nominal. + * PSU_SATA_AHCI_VENDOR_PP4C_BNM 0x08 + + * SFD: Signal Failure Detection, if the signal detection de-asserts for a + * time greater than this then the OOB detector will determine this is a li + * ne idle and cause the PhyInit state machine to exit the Phy Ready State. + * A value of zero disables the Signal Failure Detector. The value is base + * d on the OOB Detector Clock typically (PMCLK Clock Period) * SFD giving + * a nominal time of 500ns based on a 150MHz PMCLK. + * PSU_SATA_AHCI_VENDOR_PP4C_SFD 0x4A + + * PTST: Partial to Slumber timer value, specific delay the controller shou + * ld apply while in partial before entering slumber. The value is bases on + * the system clock divided by 128, total delay = (Sys Clock Period) * PTS + * T * 128 + * PSU_SATA_AHCI_VENDOR_PP4C_PTST 0x06 + + * PP4C - Port Phy4Cfg Register. This register controls the configuration o + * f the Phy Control Burst timing for the COM parameters for either Port 0 + * or Port 1. The Port configured is controlled by the value programmed int + * o the Port Config Register. + * (OFFSET, MASK, VALUE) (0XFD0C00B4, 0xFFFFFFFFU ,0x064A0813U) + */ + PSU_Mask_Write(SATA_AHCI_VENDOR_PP4C_OFFSET, + 0xFFFFFFFFU, 0x064A0813U); +/*##################################################################### */ + + /* + * Register : PP5C @ 0XFD0C00B8 + + * RIT: Retry Interval Timer. The calculated value divided by two, the lowe + * r digit of precision is not needed. + * PSU_SATA_AHCI_VENDOR_PP5C_RIT 0xC96A4 + + * RCT: Rate Change Timer, a value based on the 54.2us for which a SATA dev + * ice will transmit at a fixed rate ALIGNp after OOB has completed, for a + * fast SERDES it is suggested that this value be 54.2us / 4 + * PSU_SATA_AHCI_VENDOR_PP5C_RCT 0x3FF + + * PP5C - Port Phy5Cfg Register. This register controls the configuration o + * f the Phy Control Retry Interval timing for either Port 0 or Port 1. The + * Port configured is controlled by the value programmed into the Port Con + * fig Register. + * (OFFSET, MASK, VALUE) (0XFD0C00B8, 0xFFFFFFFFU ,0x3FFC96A4U) + */ + PSU_Mask_Write(SATA_AHCI_VENDOR_PP5C_OFFSET, + 0xFFFFFFFFU, 0x3FFC96A4U); +/*##################################################################### */ - return 1; + return 1; } -unsigned long psu_ps_pl_isolation_removal_data() { - // : PS-PL POWER UP REQUEST - /*Register : REQ_PWRUP_INT_EN @ 0XFFD80118

+unsigned long psu_resetin_init_data(void) +{ + /* + * PUTTING SERDES PERIPHERAL IN RESET + */ + /* + * PUTTING USB0 IN RESET + */ + /* + * Register : RST_LPD_TOP @ 0XFF5E023C - Power-up Request Interrupt Enable for PL - PSU_PMU_GLOBAL_REQ_PWRUP_INT_EN_PL 1 + * USB 0 reset for control registers + * PSU_CRL_APB_RST_LPD_TOP_USB0_APB_RESET 0X1 - Power-up Request Interrupt Enable Register. Writing a 1 to this location will unmask the interrupt. - (OFFSET, MASK, VALUE) (0XFFD80118, 0x00800000U ,0x00800000U) - RegMask = (PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_MASK | 0 ); + * USB 0 sleep circuit reset + * PSU_CRL_APB_RST_LPD_TOP_USB0_HIBERRESET 0X1 - RegVal = ((0x00000001U << PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PMU_GLOBAL_REQ_PWRUP_INT_EN_OFFSET ,0x00800000U ,0x00800000U); - /*############################################################################################################################ */ + * USB 0 reset + * PSU_CRL_APB_RST_LPD_TOP_USB0_CORERESET 0X1 - /*Register : REQ_PWRUP_TRIG @ 0XFFD80120

+ * Software control register for the LPD block. + * (OFFSET, MASK, VALUE) (0XFF5E023C, 0x00000540U ,0x00000540U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_TOP_OFFSET, 0x00000540U, 0x00000540U); +/*##################################################################### */ - Power-up Request Trigger for PL - PSU_PMU_GLOBAL_REQ_PWRUP_TRIG_PL 1 + /* + * PUTTING GEM0 IN RESET + */ + /* + * Register : RST_LPD_IOU0 @ 0XFF5E0230 - Power-up Request Trigger Register. A write of one to this location will generate a power-up request to the PMU. - (OFFSET, MASK, VALUE) (0XFFD80120, 0x00800000U ,0x00800000U) - RegMask = (PMU_GLOBAL_REQ_PWRUP_TRIG_PL_MASK | 0 ); + * GEM 3 reset + * PSU_CRL_APB_RST_LPD_IOU0_GEM3_RESET 0X1 - RegVal = ((0x00000001U << PMU_GLOBAL_REQ_PWRUP_TRIG_PL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PMU_GLOBAL_REQ_PWRUP_TRIG_OFFSET ,0x00800000U ,0x00800000U); - /*############################################################################################################################ */ + * Software controlled reset for the GEMs + * (OFFSET, MASK, VALUE) (0XFF5E0230, 0x00000008U ,0x00000008U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_IOU0_OFFSET, + 0x00000008U, 0x00000008U); +/*##################################################################### */ - // : POLL ON PL POWER STATUS - /*Register : REQ_PWRUP_STATUS @ 0XFFD80110

+ /* + * PUTTING SATA IN RESET + */ + /* + * Register : RST_FPD_TOP @ 0XFD1A0100 - Power-up Request Status for PL - PSU_PMU_GLOBAL_REQ_PWRUP_STATUS_PL 1 - (OFFSET, MASK, VALUE) (0XFFD80110, 0x00800000U ,0x00000000U) */ - mask_pollOnValue(PMU_GLOBAL_REQ_PWRUP_STATUS_OFFSET,0x00800000U,0x00000000U); + * Sata block level reset + * PSU_CRF_APB_RST_FPD_TOP_SATA_RESET 0X1 - /*############################################################################################################################ */ + * FPD Block level software controlled reset + * (OFFSET, MASK, VALUE) (0XFD1A0100, 0x00000002U ,0x00000002U) + */ + PSU_Mask_Write(CRF_APB_RST_FPD_TOP_OFFSET, 0x00000002U, 0x00000002U); +/*##################################################################### */ + + /* + * PUTTING PCIE IN RESET + */ + /* + * Register : RST_FPD_TOP @ 0XFD1A0100 + + * PCIE config reset + * PSU_CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET 0X1 + + * PCIE control block level reset + * PSU_CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET 0X1 + + * PCIE bridge block level reset (AXI interface) + * PSU_CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET 0X1 + + * FPD Block level software controlled reset + * (OFFSET, MASK, VALUE) (0XFD1A0100, 0x000E0000U ,0x000E0000U) + */ + PSU_Mask_Write(CRF_APB_RST_FPD_TOP_OFFSET, 0x000E0000U, 0x000E0000U); +/*##################################################################### */ + + /* + * PUTTING DP IN RESET + */ + /* + * Register : DP_TX_PHY_POWER_DOWN @ 0XFD4A0238 + + * Two bits per lane. When set to 11, moves the GT to power down mode. When + * set to 00, GT will be in active state. bits [1:0] - lane0 Bits [3:2] - + * lane 1 + * PSU_DP_DP_TX_PHY_POWER_DOWN_POWER_DWN 0XA + + * Control PHY Power down + * (OFFSET, MASK, VALUE) (0XFD4A0238, 0x0000000FU ,0x0000000AU) + */ + PSU_Mask_Write(DP_DP_TX_PHY_POWER_DOWN_OFFSET, + 0x0000000FU, 0x0000000AU); +/*##################################################################### */ + + /* + * Register : DP_PHY_RESET @ 0XFD4A0200 + + * Set to '1' to hold the GT in reset. Clear to release. + * PSU_DP_DP_PHY_RESET_GT_RESET 0X1 + + * Reset the transmitter PHY. + * (OFFSET, MASK, VALUE) (0XFD4A0200, 0x00000002U ,0x00000002U) + */ + PSU_Mask_Write(DP_DP_PHY_RESET_OFFSET, 0x00000002U, 0x00000002U); +/*##################################################################### */ + + /* + * Register : RST_FPD_TOP @ 0XFD1A0100 + + * Display Port block level reset (includes DPDMA) + * PSU_CRF_APB_RST_FPD_TOP_DP_RESET 0X1 + + * FPD Block level software controlled reset + * (OFFSET, MASK, VALUE) (0XFD1A0100, 0x00010000U ,0x00010000U) + */ + PSU_Mask_Write(CRF_APB_RST_FPD_TOP_OFFSET, 0x00010000U, 0x00010000U); +/*##################################################################### */ - return 1; + return 1; } -unsigned long psu_ps_pl_reset_config_data() { - // : PS PL RESET SEQUENCE - // : FABRIC RESET USING EMIO - /*Register : MASK_DATA_5_MSW @ 0XFF0A002C

+unsigned long psu_ps_pl_isolation_removal_data(void) +{ + /* + * PS-PL POWER UP REQUEST + */ + /* + * Register : REQ_PWRUP_INT_EN @ 0XFFD80118 - Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW] - PSU_GPIO_MASK_DATA_5_MSW_MASK_5_MSW 0x8000 + * Power-up Request Interrupt Enable for PL + * PSU_PMU_GLOBAL_REQ_PWRUP_INT_EN_PL 1 - Maskable Output Data (GPIO Bank5, EMIO, Upper 16bits) - (OFFSET, MASK, VALUE) (0XFF0A002C, 0xFFFF0000U ,0x80000000U) - RegMask = (GPIO_MASK_DATA_5_MSW_MASK_5_MSW_MASK | 0 ); + * Power-up Request Interrupt Enable Register. Writing a 1 to this location + * will unmask the interrupt. + * (OFFSET, MASK, VALUE) (0XFFD80118, 0x00800000U ,0x00800000U) + */ + PSU_Mask_Write(PMU_GLOBAL_REQ_PWRUP_INT_EN_OFFSET, + 0x00800000U, 0x00800000U); +/*##################################################################### */ - RegVal = ((0x00008000U << GPIO_MASK_DATA_5_MSW_MASK_5_MSW_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (GPIO_MASK_DATA_5_MSW_OFFSET ,0xFFFF0000U ,0x80000000U); - /*############################################################################################################################ */ + /* + * Register : REQ_PWRUP_TRIG @ 0XFFD80120 - /*Register : DIRM_5 @ 0XFF0A0344

+ * Power-up Request Trigger for PL + * PSU_PMU_GLOBAL_REQ_PWRUP_TRIG_PL 1 - Operation is the same as DIRM_0[DIRECTION_0] - PSU_GPIO_DIRM_5_DIRECTION_5 0x80000000 + * Power-up Request Trigger Register. A write of one to this location will + * generate a power-up request to the PMU. + * (OFFSET, MASK, VALUE) (0XFFD80120, 0x00800000U ,0x00800000U) + */ + PSU_Mask_Write(PMU_GLOBAL_REQ_PWRUP_TRIG_OFFSET, + 0x00800000U, 0x00800000U); +/*##################################################################### */ - Direction mode (GPIO Bank5, EMIO) - (OFFSET, MASK, VALUE) (0XFF0A0344, 0xFFFFFFFFU ,0x80000000U) - RegMask = (GPIO_DIRM_5_DIRECTION_5_MASK | 0 ); + /* + * POLL ON PL POWER STATUS + */ + /* + * Register : REQ_PWRUP_STATUS @ 0XFFD80110 - RegVal = ((0x80000000U << GPIO_DIRM_5_DIRECTION_5_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (GPIO_DIRM_5_OFFSET ,0xFFFFFFFFU ,0x80000000U); - /*############################################################################################################################ */ + * Power-up Request Status for PL + * PSU_PMU_GLOBAL_REQ_PWRUP_STATUS_PL 1 + * (OFFSET, MASK, VALUE) (0XFFD80110, 0x00800000U ,0x00000000U) + */ + mask_pollOnValue(PMU_GLOBAL_REQ_PWRUP_STATUS_OFFSET, + 0x00800000U, 0x00000000U); - /*Register : OEN_5 @ 0XFF0A0348

+/*##################################################################### */ - Operation is the same as OEN_0[OP_ENABLE_0] - PSU_GPIO_OEN_5_OP_ENABLE_5 0x80000000 - Output enable (GPIO Bank5, EMIO) - (OFFSET, MASK, VALUE) (0XFF0A0348, 0xFFFFFFFFU ,0x80000000U) - RegMask = (GPIO_OEN_5_OP_ENABLE_5_MASK | 0 ); + return 1; +} +unsigned long psu_afi_config(void) +{ + /* + * AFI RESET + */ + /* + * Register : RST_FPD_TOP @ 0XFD1A0100 - RegVal = ((0x80000000U << GPIO_OEN_5_OP_ENABLE_5_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (GPIO_OEN_5_OFFSET ,0xFFFFFFFFU ,0x80000000U); - /*############################################################################################################################ */ + * AF_FM0 block level reset + * PSU_CRF_APB_RST_FPD_TOP_AFI_FM0_RESET 0 - /*Register : DATA_5 @ 0XFF0A0054

+ * AF_FM1 block level reset + * PSU_CRF_APB_RST_FPD_TOP_AFI_FM1_RESET 0 - Output Data - PSU_GPIO_DATA_5_DATA_5 0x80000000 + * AF_FM2 block level reset + * PSU_CRF_APB_RST_FPD_TOP_AFI_FM2_RESET 0 - Output Data (GPIO Bank5, EMIO) - (OFFSET, MASK, VALUE) (0XFF0A0054, 0xFFFFFFFFU ,0x80000000U) - RegMask = (GPIO_DATA_5_DATA_5_MASK | 0 ); + * AF_FM3 block level reset + * PSU_CRF_APB_RST_FPD_TOP_AFI_FM3_RESET 0 - RegVal = ((0x80000000U << GPIO_DATA_5_DATA_5_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (GPIO_DATA_5_OFFSET ,0xFFFFFFFFU ,0x80000000U); - /*############################################################################################################################ */ + * AF_FM4 block level reset + * PSU_CRF_APB_RST_FPD_TOP_AFI_FM4_RESET 0 + + * AF_FM5 block level reset + * PSU_CRF_APB_RST_FPD_TOP_AFI_FM5_RESET 0 + + * FPD Block level software controlled reset + * (OFFSET, MASK, VALUE) (0XFD1A0100, 0x00001F80U ,0x00000000U) + */ + PSU_Mask_Write(CRF_APB_RST_FPD_TOP_OFFSET, 0x00001F80U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : RST_LPD_TOP @ 0XFF5E023C + + * AFI FM 6 + * PSU_CRL_APB_RST_LPD_TOP_AFI_FM6_RESET 0 + + * Software control register for the LPD block. + * (OFFSET, MASK, VALUE) (0XFF5E023C, 0x00080000U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_TOP_OFFSET, 0x00080000U, 0x00000000U); +/*##################################################################### */ + + /* + * AFIFM INTERFACE WIDTH + */ + /* + * Register : afi_fs @ 0XFD615000 + + * Select the 32/64/128-bit data width selection for the Slave 0 00: 32-bit + * AXI data width (default) 01: 64-bit AXI data width 10: 128-bit AXI data + * width 11: reserved + * PSU_FPD_SLCR_AFI_FS_DW_SS0_SEL 0x2 + + * Select the 32/64/128-bit data width selection for the Slave 1 00: 32-bit + * AXI data width (default) 01: 64-bit AXI data width 10: 128-bit AXI data + * width 11: reserved + * PSU_FPD_SLCR_AFI_FS_DW_SS1_SEL 0x2 + + * afi fs SLCR control register. This register is static and should not be + * modified during operation. + * (OFFSET, MASK, VALUE) (0XFD615000, 0x00000F00U ,0x00000A00U) + */ + PSU_Mask_Write(FPD_SLCR_AFI_FS_OFFSET, 0x00000F00U, 0x00000A00U); +/*##################################################################### */ + + + return 1; +} +unsigned long psu_ps_pl_reset_config_data(void) +{ + /* + * PS PL RESET SEQUENCE + */ + /* + * FABRIC RESET USING EMIO + */ + /* + * Register : MASK_DATA_5_MSW @ 0XFF0A002C + + * Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW] + * PSU_GPIO_MASK_DATA_5_MSW_MASK_5_MSW 0x8000 + + * Maskable Output Data (GPIO Bank5, EMIO, Upper 16bits) + * (OFFSET, MASK, VALUE) (0XFF0A002C, 0xFFFF0000U ,0x80000000U) + */ + PSU_Mask_Write(GPIO_MASK_DATA_5_MSW_OFFSET, + 0xFFFF0000U, 0x80000000U); +/*##################################################################### */ + + /* + * Register : DIRM_5 @ 0XFF0A0344 + + * Operation is the same as DIRM_0[DIRECTION_0] + * PSU_GPIO_DIRM_5_DIRECTION_5 0x80000000 + + * Direction mode (GPIO Bank5, EMIO) + * (OFFSET, MASK, VALUE) (0XFF0A0344, 0xFFFFFFFFU ,0x80000000U) + */ + PSU_Mask_Write(GPIO_DIRM_5_OFFSET, 0xFFFFFFFFU, 0x80000000U); +/*##################################################################### */ + + /* + * Register : OEN_5 @ 0XFF0A0348 + + * Operation is the same as OEN_0[OP_ENABLE_0] + * PSU_GPIO_OEN_5_OP_ENABLE_5 0x80000000 + + * Output enable (GPIO Bank5, EMIO) + * (OFFSET, MASK, VALUE) (0XFF0A0348, 0xFFFFFFFFU ,0x80000000U) + */ + PSU_Mask_Write(GPIO_OEN_5_OFFSET, 0xFFFFFFFFU, 0x80000000U); +/*##################################################################### */ + + /* + * Register : DATA_5 @ 0XFF0A0054 + + * Output Data + * PSU_GPIO_DATA_5_DATA_5 0x80000000 + + * Output Data (GPIO Bank5, EMIO) + * (OFFSET, MASK, VALUE) (0XFF0A0054, 0xFFFFFFFFU ,0x80000000U) + */ + PSU_Mask_Write(GPIO_DATA_5_OFFSET, 0xFFFFFFFFU, 0x80000000U); +/*##################################################################### */ mask_delay(1); - /*############################################################################################################################ */ +/*##################################################################### */ - // : FABRIC RESET USING DATA_5 TOGGLE - /*Register : DATA_5 @ 0XFF0A0054

+ /* + * FABRIC RESET USING DATA_5 TOGGLE + */ + /* + * Register : DATA_5 @ 0XFF0A0054 - Output Data - PSU_GPIO_DATA_5_DATA_5 0X00000000 + * Output Data + * PSU_GPIO_DATA_5_DATA_5 0X00000000 - Output Data (GPIO Bank5, EMIO) - (OFFSET, MASK, VALUE) (0XFF0A0054, 0xFFFFFFFFU ,0x00000000U) - RegMask = (GPIO_DATA_5_DATA_5_MASK | 0 ); - - RegVal = ((0x00000000U << GPIO_DATA_5_DATA_5_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (GPIO_DATA_5_OFFSET ,0xFFFFFFFFU ,0x00000000U); - /*############################################################################################################################ */ + * Output Data (GPIO Bank5, EMIO) + * (OFFSET, MASK, VALUE) (0XFF0A0054, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(GPIO_DATA_5_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ mask_delay(1); - /*############################################################################################################################ */ +/*##################################################################### */ - // : FABRIC RESET USING DATA_5 TOGGLE - /*Register : DATA_5 @ 0XFF0A0054

+ /* + * FABRIC RESET USING DATA_5 TOGGLE + */ + /* + * Register : DATA_5 @ 0XFF0A0054 - Output Data - PSU_GPIO_DATA_5_DATA_5 0x80000000 + * Output Data + * PSU_GPIO_DATA_5_DATA_5 0x80000000 - Output Data (GPIO Bank5, EMIO) - (OFFSET, MASK, VALUE) (0XFF0A0054, 0xFFFFFFFFU ,0x80000000U) - RegMask = (GPIO_DATA_5_DATA_5_MASK | 0 ); - - RegVal = ((0x80000000U << GPIO_DATA_5_DATA_5_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (GPIO_DATA_5_OFFSET ,0xFFFFFFFFU ,0x80000000U); - /*############################################################################################################################ */ + * Output Data (GPIO Bank5, EMIO) + * (OFFSET, MASK, VALUE) (0XFF0A0054, 0xFFFFFFFFU ,0x80000000U) + */ + PSU_Mask_Write(GPIO_DATA_5_OFFSET, 0xFFFFFFFFU, 0x80000000U); +/*##################################################################### */ - return 1; + return 1; } -unsigned long psu_ddr_phybringup_data() { +unsigned long psu_ddr_phybringup_data(void) +{ + + + unsigned int regval = 0; + + unsigned int pll_retry = 10; + + unsigned int pll_locked = 0; + + + while ((pll_retry > 0) && (!pll_locked)) { + + Xil_Out32(0xFD080004, 0x00040010);/*PIR*/ + Xil_Out32(0xFD080004, 0x00040011);/*PIR*/ + + while ((Xil_In32(0xFD080030) & 0x1) != 1) { + /*****TODO*****/ + + /*TIMEOUT poll mechanism need to be inserted in this block*/ + + } + + + pll_locked = (Xil_In32(0xFD080030) & 0x80000000) + >> 31;/*PGSR0*/ + pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000) + >> 16;/*DX0GSR0*/ + pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000) + >> 16;/*DX2GSR0*/ + pll_locked &= (Xil_In32(0xFD080BE0) & 0x10000) + >> 16;/*DX4GSR0*/ + pll_locked &= (Xil_In32(0xFD080DE0) & 0x10000) + >> 16;/*DX6GSR0*/ + pll_retry--; + } + Xil_Out32(0xFD0800C0, Xil_In32(0xFD0800C0) | + (pll_retry << 16));/*GPR0*/ + Xil_Out32(0xFD080004U, 0x00040063U); + /* PHY BRINGUP SEQ */ + while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU) { + /*****TODO*****/ + + /*TIMEOUT poll mechanism need to be inserted in this block*/ + + } + + prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U); + /* poll for PHY initialization to complete */ + while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU) { + /*****TODO*****/ + + /*TIMEOUT poll mechanism need to be inserted in this block*/ + + } - unsigned int regval = 0; - int dpll_divisor; - dpll_divisor = (Xil_In32(0xFD1A0080U) & 0x00003F00U) >> 0x00000008U; - prog_reg (0xFD1A0080U, 0x00003F00U, 0x00000008U, 0x00000005U); - prog_reg (0xFD080028U, 0x00000001U, 0x00000000U, 0x00000001U); - Xil_Out32(0xFD080004U, 0x00040003U); - while ((Xil_In32(0xFD080030U) & 0x00000001U) != 0x00000001U); - prog_reg (0xFD080684U, 0x06000000U, 0x00000019U, 0x00000001U); - prog_reg (0xFD0806A4U, 0x06000000U, 0x00000019U, 0x00000001U); - prog_reg (0xFD0806C4U, 0x06000000U, 0x00000019U, 0x00000001U); - prog_reg (0xFD0806E4U, 0x06000000U, 0x00000019U, 0x00000001U); - prog_reg (0xFD1A0080, 0x3F00, 0x8, dpll_divisor); - Xil_Out32(0xFD080004U, 0x40040071U); - while ((Xil_In32(0xFD080030U) & 0x00000001U) != 0x00000001U); - Xil_Out32(0xFD080004U, 0x40040001U); - while ((Xil_In32(0xFD080030U) & 0x00000001U) != 0x00000001U); - // PHY BRINGUP SEQ - while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU); - prog_reg (0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U); - //poll for PHY initialization to complete - while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU); - Xil_Out32(0xFD0701B0U, 0x00000001U); Xil_Out32(0xFD070320U, 0x00000001U); - while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U); - prog_reg (0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U); - Xil_Out32(0xFD080004, 0x0004FE01); //PUB_PIR - regval = Xil_In32(0xFD080030); //PUB_PGSR0 - while(regval != 0x80000FFF){ - regval = Xil_In32(0xFD080030); //PUB_PGSR0 - } + while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U) { + /*****TODO*****/ - - // Run Vref training in static read mode + /*TIMEOUT poll mechanism need to be inserted in this block*/ + + } + + prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U); + Xil_Out32(0xFD080004, 0x0004FE01); /*PUB_PIR*/ + regval = Xil_In32(0xFD080030); /*PUB_PGSR0*/ + while (regval != 0x80000FFF) + regval = Xil_In32(0xFD080030); /*PUB_PGSR0*/ + +/* Run Vref training in static read mode*/ Xil_Out32(0xFD080200U, 0x100091C7U); - Xil_Out32(0xFD080018U, 0x00F01EF2U); - Xil_Out32(0xFD08001CU, 0x55AA5498U); - Xil_Out32(0xFD08142CU, 0x00041830U); - Xil_Out32(0xFD08146CU, 0x00041830U); - Xil_Out32(0xFD0814ACU, 0x00041830U); - Xil_Out32(0xFD0814ECU, 0x00041830U); - Xil_Out32(0xFD08152CU, 0x00041830U); - + Xil_Out32(0xFD080018U, 0x00F01EEFU); + prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U); + prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U); - Xil_Out32(0xFD080004, 0x00060001); //PUB_PIR - regval = Xil_In32(0xFD080030); //PUB_PGSR0 - while((regval & 0x80004001) != 0x80004001){ - regval = Xil_In32(0xFD080030); //PUB_PGSR0 - } - // Vref training is complete, disabling static read mode + Xil_Out32(0xFD080004, 0x00060001); /*PUB_PIR*/ + regval = Xil_In32(0xFD080030); /*PUB_PGSR0*/ + while ((regval & 0x80004001) != 0x80004001) { + /*PUB_PGSR0*/ + regval = Xil_In32(0xFD080030); + } + + prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U); + prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U); +/*Vref training is complete, disabling static read mode*/ Xil_Out32(0xFD080200U, 0x800091C7U); - Xil_Out32(0xFD080018U, 0x00F12302U); - Xil_Out32(0xFD08001CU, 0x55AA5480U); - Xil_Out32(0xFD08142CU, 0x00041800U); - Xil_Out32(0xFD08146CU, 0x00041800U); - Xil_Out32(0xFD0814ACU, 0x00041800U); - Xil_Out32(0xFD0814ECU, 0x00041800U); - Xil_Out32(0xFD08152CU, 0x00041800U); - + Xil_Out32(0xFD080018U, 0x00F122E7U); - Xil_Out32(0xFD080004, 0x0000C001); //PUB_PIR - regval = Xil_In32(0xFD080030); //PUB_PGSR0 - while((regval & 0x80000C01) != 0x80000C01){ - regval = Xil_In32(0xFD080030); //PUB_PGSR0 - } + + Xil_Out32(0xFD080004, 0x0000C001); /*PUB_PIR*/ + regval = Xil_In32(0xFD080030); /*PUB_PGSR0*/ + while ((regval & 0x80000C01) != 0x80000C01) { + /*PUB_PGSR0*/ + regval = Xil_In32(0xFD080030); + } Xil_Out32(0xFD070180U, 0x01000040U); Xil_Out32(0xFD070060U, 0x00000000U); - prog_reg (0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U); + prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U); -return 1; +return 1; } /** * CRL_APB Base Address */ #define CRL_APB_BASEADDR 0XFF5E0000U -#define CRL_APB_RST_LPD_IOU0 ( ( CRL_APB_BASEADDR ) + 0X00000230U ) -#define CRL_APB_RST_LPD_IOU1 ( ( CRL_APB_BASEADDR ) + 0X00000234U ) -#define CRL_APB_RST_LPD_IOU2 ( ( CRL_APB_BASEADDR ) + 0X00000238U ) -#define CRL_APB_RST_LPD_TOP ( ( CRL_APB_BASEADDR ) + 0X0000023CU ) -#define CRL_APB_IOU_SWITCH_CTRL ( ( CRL_APB_BASEADDR ) + 0X0000009CU ) +#define CRL_APB_RST_LPD_IOU0 ((CRL_APB_BASEADDR) + 0X00000230U) +#define CRL_APB_RST_LPD_IOU1 ((CRL_APB_BASEADDR) + 0X00000234U) +#define CRL_APB_RST_LPD_IOU2 ((CRL_APB_BASEADDR) + 0X00000238U) +#define CRL_APB_RST_LPD_TOP ((CRL_APB_BASEADDR) + 0X0000023CU) +#define CRL_APB_IOU_SWITCH_CTRL ((CRL_APB_BASEADDR) + 0X0000009CU) /** * CRF_APB Base Address */ #define CRF_APB_BASEADDR 0XFD1A0000U -#define CRF_APB_RST_FPD_TOP ( ( CRF_APB_BASEADDR ) + 0X00000100U ) -#define CRF_APB_GPU_REF_CTRL ( ( CRF_APB_BASEADDR ) + 0X00000084U ) -#define CRF_APB_RST_DDR_SS ( ( CRF_APB_BASEADDR ) + 0X00000108U ) +#define CRF_APB_RST_FPD_TOP ((CRF_APB_BASEADDR) + 0X00000100U) +#define CRF_APB_GPU_REF_CTRL ((CRF_APB_BASEADDR) + 0X00000084U) +#define CRF_APB_RST_DDR_SS ((CRF_APB_BASEADDR) + 0X00000108U) #define PSU_MASK_POLL_TIME 1100000 +/** + * * Register: CRF_APB_DPLL_CTRL + */ +#define CRF_APB_DPLL_CTRL ((CRF_APB_BASEADDR) + 0X0000002C) -int mask_pollOnValue(u32 add , u32 mask, u32 value ) { - volatile u32 *addr = (volatile u32*)(unsigned long) add; + +#define CRF_APB_DPLL_CTRL_DIV2_SHIFT 16 +#define CRF_APB_DPLL_CTRL_DIV2_WIDTH 1 + +#define CRF_APB_DPLL_CTRL_FBDIV_SHIFT 8 +#define CRF_APB_DPLL_CTRL_FBDIV_WIDTH 7 + +#define CRF_APB_DPLL_CTRL_BYPASS_SHIFT 3 +#define CRF_APB_DPLL_CTRL_BYPASS_WIDTH 1 + +#define CRF_APB_DPLL_CTRL_RESET_SHIFT 0 +#define CRF_APB_DPLL_CTRL_RESET_WIDTH 1 + +/** + * * Register: CRF_APB_DPLL_CFG + */ +#define CRF_APB_DPLL_CFG ((CRF_APB_BASEADDR) + 0X00000030) + +#define CRF_APB_DPLL_CFG_LOCK_DLY_SHIFT 25 +#define CRF_APB_DPLL_CFG_LOCK_DLY_WIDTH 7 + +#define CRF_APB_DPLL_CFG_LOCK_CNT_SHIFT 13 +#define CRF_APB_DPLL_CFG_LOCK_CNT_WIDTH 10 + +#define CRF_APB_DPLL_CFG_LFHF_SHIFT 10 +#define CRF_APB_DPLL_CFG_LFHF_WIDTH 2 + +#define CRF_APB_DPLL_CFG_CP_SHIFT 5 +#define CRF_APB_DPLL_CFG_CP_WIDTH 4 + +#define CRF_APB_DPLL_CFG_RES_SHIFT 0 +#define CRF_APB_DPLL_CFG_RES_WIDTH 4 + +/** + * Register: CRF_APB_PLL_STATUS + */ +#define CRF_APB_PLL_STATUS ((CRF_APB_BASEADDR) + 0X00000044) + + +static int mask_pollOnValue(u32 add, u32 mask, u32 value) +{ + volatile u32 *addr = (volatile u32 *)(unsigned long) add; int i = 0; - while ((*addr & mask)!= value) { - if (i == PSU_MASK_POLL_TIME) { + + while ((*addr & mask) != value) { + if (i == PSU_MASK_POLL_TIME) return 0; - } i++; } - return 1; - //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr); + return 1; } -int mask_poll(u32 add , u32 mask) { - volatile u32 *addr = (volatile u32*)(unsigned long) add; +static int mask_poll(u32 add, u32 mask) +{ + volatile u32 *addr = (volatile u32 *)(unsigned long) add; int i = 0; + while (!(*addr & mask)) { - if (i == PSU_MASK_POLL_TIME) { + if (i == PSU_MASK_POLL_TIME) return 0; - } i++; } - return 1; - //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr); + return 1; } -void mask_delay(u32 delay) { - usleep (delay); +static void mask_delay(u32 delay) +{ + usleep(delay); } -u32 mask_read(u32 add , u32 mask ) { - volatile u32 *addr = (volatile u32*)(unsigned long) add; - u32 val = (*addr & mask); - //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val); - return val; +static u32 mask_read(u32 add, u32 mask) +{ + volatile u32 *addr = (volatile u32 *)(unsigned long) add; + u32 val = (*addr & mask); + return val; } +static void dpll_prog(int ddr_pll_fbdiv, int d_lock_dly, int d_lock_cnt, + int d_lfhf, int d_cp, int d_res) { -//Following SERDES programming sequences that a user need to follow to work around the known limitation with SERDES. -//These sequences should done before STEP 1 and STEP 2 as described in previous section. These programming steps are -//required for current silicon version and are likely to undergo further changes with subsequent silicon versions. + unsigned int pll_ctrl_regval; + unsigned int pll_status_regval; + + pll_ctrl_regval = Xil_In32(CRF_APB_DPLL_CTRL); + pll_ctrl_regval = pll_ctrl_regval & (~CRF_APB_DPLL_CTRL_DIV2_MASK); + pll_ctrl_regval = pll_ctrl_regval | (1 << CRF_APB_DPLL_CTRL_DIV2_SHIFT); + Xil_Out32(CRF_APB_DPLL_CTRL, pll_ctrl_regval); + + pll_ctrl_regval = Xil_In32(CRF_APB_DPLL_CFG); + pll_ctrl_regval = pll_ctrl_regval & (~CRF_APB_DPLL_CFG_LOCK_DLY_MASK); + pll_ctrl_regval = pll_ctrl_regval | + (d_lock_dly << CRF_APB_DPLL_CFG_LOCK_DLY_SHIFT); + Xil_Out32(CRF_APB_DPLL_CFG, pll_ctrl_regval); + + pll_ctrl_regval = Xil_In32(CRF_APB_DPLL_CFG); + pll_ctrl_regval = pll_ctrl_regval & (~CRF_APB_DPLL_CFG_LOCK_CNT_MASK); + pll_ctrl_regval = pll_ctrl_regval | + (d_lock_cnt << CRF_APB_DPLL_CFG_LOCK_CNT_SHIFT); + Xil_Out32(CRF_APB_DPLL_CFG, pll_ctrl_regval); + + pll_ctrl_regval = Xil_In32(CRF_APB_DPLL_CFG); + pll_ctrl_regval = pll_ctrl_regval & (~CRF_APB_DPLL_CFG_LFHF_MASK); + pll_ctrl_regval = pll_ctrl_regval | + (d_lfhf << CRF_APB_DPLL_CFG_LFHF_SHIFT); + Xil_Out32(CRF_APB_DPLL_CFG, pll_ctrl_regval); + + pll_ctrl_regval = Xil_In32(CRF_APB_DPLL_CFG); + pll_ctrl_regval = pll_ctrl_regval & (~CRF_APB_DPLL_CFG_CP_MASK); + pll_ctrl_regval = pll_ctrl_regval | + (d_cp << CRF_APB_DPLL_CFG_CP_SHIFT); + Xil_Out32(CRF_APB_DPLL_CFG, pll_ctrl_regval); + + pll_ctrl_regval = Xil_In32(CRF_APB_DPLL_CFG); + pll_ctrl_regval = pll_ctrl_regval & (~CRF_APB_DPLL_CFG_RES_MASK); + pll_ctrl_regval = pll_ctrl_regval | + (d_res << CRF_APB_DPLL_CFG_RES_SHIFT); + Xil_Out32(CRF_APB_DPLL_CFG, pll_ctrl_regval); + + pll_ctrl_regval = Xil_In32(CRF_APB_DPLL_CTRL); + pll_ctrl_regval = pll_ctrl_regval & (~CRF_APB_DPLL_CTRL_FBDIV_MASK); + pll_ctrl_regval = pll_ctrl_regval | + (ddr_pll_fbdiv << CRF_APB_DPLL_CTRL_FBDIV_SHIFT); + Xil_Out32(CRF_APB_DPLL_CTRL, pll_ctrl_regval); + + /*Setting PLL BYPASS*/ + pll_ctrl_regval = Xil_In32(CRF_APB_DPLL_CTRL); + pll_ctrl_regval = pll_ctrl_regval & (~CRF_APB_DPLL_CTRL_BYPASS_MASK); + pll_ctrl_regval = pll_ctrl_regval | + (1 << CRF_APB_DPLL_CTRL_BYPASS_SHIFT); + Xil_Out32(CRF_APB_DPLL_CTRL, pll_ctrl_regval); + + /*Setting PLL RESET*/ + pll_ctrl_regval = Xil_In32(CRF_APB_DPLL_CTRL); + pll_ctrl_regval = pll_ctrl_regval & (~CRF_APB_DPLL_CTRL_RESET_MASK); + pll_ctrl_regval = pll_ctrl_regval | + (1 << CRF_APB_DPLL_CTRL_RESET_SHIFT); + Xil_Out32(CRF_APB_DPLL_CTRL, pll_ctrl_regval); + + /*Clearing PLL RESET*/ + pll_ctrl_regval = Xil_In32(CRF_APB_DPLL_CTRL); + pll_ctrl_regval = pll_ctrl_regval & (~CRF_APB_DPLL_CTRL_RESET_MASK); + pll_ctrl_regval = pll_ctrl_regval | + (0 << CRF_APB_DPLL_CTRL_RESET_SHIFT); + Xil_Out32(CRF_APB_DPLL_CTRL, pll_ctrl_regval); + + /*Checking PLL lock*/ + pll_status_regval = 0x00000000; + while ((pll_status_regval & CRF_APB_PLL_STATUS_DPLL_LOCK_MASK) != + CRF_APB_PLL_STATUS_DPLL_LOCK_MASK) + pll_status_regval = Xil_In32(CRF_APB_PLL_STATUS); -int serdes_fixcal_code() { + + /*Clearing PLL BYPASS*/ + pll_ctrl_regval = Xil_In32(CRF_APB_DPLL_CTRL); + pll_ctrl_regval = pll_ctrl_regval & (~CRF_APB_DPLL_CTRL_BYPASS_MASK); + pll_ctrl_regval = pll_ctrl_regval | + (0 << CRF_APB_DPLL_CTRL_BYPASS_SHIFT); + Xil_Out32(CRF_APB_DPLL_CTRL, pll_ctrl_regval); + +} + +/*Following SERDES programming sequences that a user need to follow to work + * around the known limitation with SERDES. These sequences should done + * before STEP 1 and STEP 2 as described in previous section. These + * programming steps are *required for current silicon version and are + * likely to undergo further changes with subsequent silicon versions. + */ + + +static int serdes_enb_coarse_saturation(void) +{ + /*Enable PLL Coarse Code saturation Logic*/ + Xil_Out32(0xFD402094, 0x00000010); + Xil_Out32(0xFD406094, 0x00000010); + Xil_Out32(0xFD40A094, 0x00000010); + Xil_Out32(0xFD40E094, 0x00000010); + return 1; +} + +int serdes_fixcal_code(void) +{ int MaskStatus = 1; - // L3_TM_CALIB_DIG19 - Xil_Out32(0xFD40EC4C,0x00000020); - //ICM_CFG0 - Xil_Out32(0xFD410010,0x00000001); + unsigned int rdata = 0; + + /*The valid codes are from 0x26 to 0x3C. + *There are 23 valid codes in total. + */ + /*Each element of array stands for count of occurence of valid code.*/ + unsigned int match_pmos_code[23]; + /*Each element of array stands for count of occurence of valid code.*/ + /*The valid codes are from 0xC to 0x12. + *There are 7 valid codes in total. + */ + unsigned int match_nmos_code[23]; + /*Each element of array stands for count of occurence of valid code.*/ + /*The valid codes are from 0x6 to 0xC. + * There are 7 valid codes in total. + */ + unsigned int match_ical_code[7]; + /*Each element of array stands for count of occurence of valid code.*/ + unsigned int match_rcal_code[7]; - //is calibration done, polling on L3_CALIB_DONE_STATUS - MaskStatus = mask_poll(0xFD40EF14, 0x2); - - if (MaskStatus == 0) - { - xil_printf("SERDES initialization timed out\n\r"); - } - - unsigned int tmp_0_1; - tmp_0_1 = mask_read(0xFD400B0C, 0x3F); - - unsigned int tmp_0_2 = tmp_0_1 & (0x7); - unsigned int tmp_0_3 = tmp_0_1 & (0x38); - //Configure ICM for de-asserting CMN_Resetn - Xil_Out32(0xFD410010,0x00000000); - Xil_Out32(0xFD410014,0x00000000); - - unsigned int tmp_0_2_mod = (tmp_0_2 <<1) | (0x1); - tmp_0_2_mod = (tmp_0_2_mod <<4); - - tmp_0_3 = tmp_0_3 >>3; - Xil_Out32(0xFD40EC4C,tmp_0_3); + unsigned int p_code = 0; + unsigned int n_code = 0; + unsigned int i_code = 0; + unsigned int r_code = 0; + unsigned int repeat_count = 0; + unsigned int L3_TM_CALIB_DIG20 = 0; + unsigned int L3_TM_CALIB_DIG19 = 0; + unsigned int L3_TM_CALIB_DIG18 = 0; + unsigned int L3_TM_CALIB_DIG16 = 0; + unsigned int L3_TM_CALIB_DIG15 = 0; + unsigned int L3_TM_CALIB_DIG14 = 0; - //L3_TM_CALIB_DIG18 - Xil_Out32(0xFD40EC48,tmp_0_2_mod); - return MaskStatus; + int i = 0; + rdata = Xil_In32(0XFD40289C); + rdata = rdata & ~0x03; + rdata = rdata | 0x1; + Xil_Out32(0XFD40289C, rdata); + // check supply good status before starting AFE sequencing + int count = 0; + do + { + if (count == PSU_MASK_POLL_TIME) + break; + rdata = Xil_In32(0xFD402B1C); + count++; + }while((rdata&0x0000000E) !=0x0000000E); + + for (i = 0; i < 23; i++) { + match_pmos_code[i] = 0; + match_nmos_code[i] = 0; + } + for (i = 0; i < 7; i++) { + match_ical_code[i] = 0; + match_rcal_code[i] = 0; + } + + + do { + /*Clear ICM_CFG value*/ + Xil_Out32(0xFD410010, 0x00000000); + Xil_Out32(0xFD410014, 0x00000000); + + /*Set ICM_CFG value*/ + /*This will trigger recalibration of all stages*/ + Xil_Out32(0xFD410010, 0x00000001); + Xil_Out32(0xFD410014, 0x00000000); + + /*is calibration done? polling on L3_CALIB_DONE_STATUS*/ + MaskStatus = mask_poll(0xFD40EF14, 0x2); + if (MaskStatus == 0) { + /*failure here is because of calibration done timeout*/ + xil_printf("#SERDES initialization timed out\n\r"); + return MaskStatus; + } + + p_code = mask_read(0xFD40EF18, 0xFFFFFFFF);/*PMOS code*/ + n_code = mask_read(0xFD40EF1C, 0xFFFFFFFF);/*NMOS code*/ + /*m_code = mask_read(0xFD40EF20, 0xFFFFFFFF)*/;/*MPHY code*/ + i_code = mask_read(0xFD40EF24, 0xFFFFFFFF);/*ICAL code*/ + r_code = mask_read(0xFD40EF28, 0xFFFFFFFF);/*RX code*/ + /*u_code = mask_read(0xFD40EF2C, 0xFFFFFFFF)*/;/*USB2 code*/ + + /*PMOS code in acceptable range*/ + if ((p_code >= 0x26) && (p_code <= 0x3C)) + match_pmos_code[p_code - 0x26] += 1; + + /*NMOS code in acceptable range*/ + if ((n_code >= 0x26) && (n_code <= 0x3C)) + match_nmos_code[n_code - 0x26] += 1; + + /*PMOS code in acceptable range*/ + if ((i_code >= 0xC) && (i_code <= 0x12)) + match_ical_code[i_code - 0xC] += 1; + + /*NMOS code in acceptable range*/ + if ((r_code >= 0x6) && (r_code <= 0xC)) + match_rcal_code[r_code - 0x6] += 1; + + + } while (repeat_count++ < 10); + + /*find the valid code which resulted in maximum times in 10 iterations*/ + for (i = 0; i < 23; i++) { + if (match_pmos_code[i] >= match_pmos_code[0]) { + match_pmos_code[0] = match_pmos_code[i]; + p_code = 0x26 + i; + } + if (match_nmos_code[i] >= match_nmos_code[0]) { + match_nmos_code[0] = match_nmos_code[i]; + n_code = 0x26 + i; + } + } + + for (i = 0; i < 7; i++) { + if (match_ical_code[i] >= match_ical_code[0]) { + match_ical_code[0] = match_ical_code[i]; + i_code = 0xC + i; + } + if (match_rcal_code[i] >= match_rcal_code[0]) { + match_rcal_code[0] = match_rcal_code[i]; + r_code = 0x6 + i; + } + } + /*L3_TM_CALIB_DIG20[3] PSW MSB Override*/ + /*L3_TM_CALIB_DIG20[2:0] PSW Code [4:2]*/ + L3_TM_CALIB_DIG20 = mask_read(0xFD40EC50, 0xFFFFFFF0);/*read DIG20*/ + L3_TM_CALIB_DIG20 = L3_TM_CALIB_DIG20 | 0x8 | ((p_code >> 2) & 0x7); + + + /*L3_TM_CALIB_DIG19[7:6] PSW Code [1:0]*/ + /*L3_TM_CALIB_DIG19[5] PSW Override*/ + /*L3_TM_CALIB_DIG19[2] NSW MSB Override*/ + /*L3_TM_CALIB_DIG19[1:0] NSW Code [4:3]*/ + L3_TM_CALIB_DIG19 = mask_read(0xFD40EC4C, 0xFFFFFF18);/*read DIG19*/ + L3_TM_CALIB_DIG19 = L3_TM_CALIB_DIG19 | ((p_code & 0x3) << 6) + | 0x20 | 0x4 | ((n_code >> 3) & 0x3); + + /*L3_TM_CALIB_DIG18[7:5] NSW Code [2:0]*/ + /*L3_TM_CALIB_DIG18[4] NSW Override*/ + L3_TM_CALIB_DIG18 = mask_read(0xFD40EC48, 0xFFFFFF0F);/*read DIG18*/ + L3_TM_CALIB_DIG18 = L3_TM_CALIB_DIG18 | ((n_code & 0x7) << 5) | 0x10; + + + /*L3_TM_CALIB_DIG16[2:0] RX Code [3:1]*/ + L3_TM_CALIB_DIG16 = mask_read(0xFD40EC40, 0xFFFFFFF8);/*read DIG16*/ + L3_TM_CALIB_DIG16 = L3_TM_CALIB_DIG16 | ((r_code >> 1) & 0x7); + + /*L3_TM_CALIB_DIG15[7] RX Code [0]*/ + /*L3_TM_CALIB_DIG15[6] RX CODE Override*/ + /*L3_TM_CALIB_DIG15[3] ICAL MSB Override*/ + /*L3_TM_CALIB_DIG15[2:0] ICAL Code [3:1]*/ + L3_TM_CALIB_DIG15 = mask_read(0xFD40EC3C, 0xFFFFFF30);/*read DIG15*/ + L3_TM_CALIB_DIG15 = L3_TM_CALIB_DIG15 | ((r_code & 0x1) << 7) + | 0x40 | 0x8 | ((i_code >> 1) & 0x7); + + /*L3_TM_CALIB_DIG14[7] ICAL Code [0]*/ + /*L3_TM_CALIB_DIG14[6] ICAL Override*/ + L3_TM_CALIB_DIG14 = mask_read(0xFD40EC38, 0xFFFFFF3F);/*read DIG14*/ + L3_TM_CALIB_DIG14 = L3_TM_CALIB_DIG14 | ((i_code & 0x1) << 7) | 0x40; + + /*Forces the calibration values*/ + Xil_Out32(0xFD40EC50, L3_TM_CALIB_DIG20); + Xil_Out32(0xFD40EC4C, L3_TM_CALIB_DIG19); + Xil_Out32(0xFD40EC48, L3_TM_CALIB_DIG18); + Xil_Out32(0xFD40EC40, L3_TM_CALIB_DIG16); + Xil_Out32(0xFD40EC3C, L3_TM_CALIB_DIG15); + Xil_Out32(0xFD40EC38, L3_TM_CALIB_DIG14); + return MaskStatus; } - -int serdes_enb_coarse_saturation() { - //Enable PLL Coarse Code saturation Logic - Xil_Out32(0xFD402094,0x00000010); - Xil_Out32(0xFD406094,0x00000010); - Xil_Out32(0xFD40A094,0x00000010); - Xil_Out32(0xFD40E094,0x00000010); - return 1; -} - -int init_serdes() { +static int init_serdes(void) +{ int status = 1; + status &= psu_resetin_init_data(); status &= serdes_fixcal_code(); status &= serdes_enb_coarse_saturation(); - status &= psu_serdes_init_data(); + status &= psu_serdes_init_data(); status &= psu_resetout_init_data(); return status; } - - - - -void init_peripheral() +static void init_peripheral(void) { - unsigned int RegValue; - - /* Turn on IOU Clock */ - //Xil_Out32( CRL_APB_IOU_SWITCH_CTRL, 0x01001500); - - /* Release all resets in the IOU */ - Xil_Out32( CRL_APB_RST_LPD_IOU0, 0x00000000); - Xil_Out32( CRL_APB_RST_LPD_IOU1, 0x00000000); - Xil_Out32( CRL_APB_RST_LPD_IOU2, 0x00000000); - - /* Activate GPU clocks */ - //Xil_Out32(CRF_APB_GPU_REF_CTRL, 0x07001500); - - /* Take LPD out of reset except R5 */ - RegValue = Xil_In32(CRL_APB_RST_LPD_TOP); - RegValue &= 0x7; - Xil_Out32( CRL_APB_RST_LPD_TOP, RegValue); - - /* Take most of FPD out of reset */ - Xil_Out32( CRF_APB_RST_FPD_TOP, 0x00000000); - - /* Making DPDMA as secure */ - unsigned int tmp_regval; - tmp_regval = Xil_In32(0xFD690040); - tmp_regval &= ~0x00000001; - Xil_Out32(0xFD690040, tmp_regval); - - /* Making PCIe as secure */ - tmp_regval = Xil_In32(0xFD690030); - tmp_regval &= ~0x00000001; - Xil_Out32(0xFD690030, tmp_regval); +/*SMMU_REG Interrrupt Enable: Followig register need to be written all the time to properly catch SMMU messages.*/ + PSU_Mask_Write(0xFD5F0018, 0x8000001FU, 0x8000001FU); } -int psu_init_xppu_aper_ram() { - unsigned long APER_OFFSET = 0xFF981000; - int i = 0; - for (; i <= 400; i++) { - PSU_Mask_Write (APER_OFFSET ,0xF80FFFFFU ,0x08080000U); - APER_OFFSET = APER_OFFSET + 0x4; - } +static int psu_init_xppu_aper_ram(void) +{ return 0; } -int psu_lpd_protection() { - psu_init_xppu_aper_ram(); - psu_lpd_xppu_data(); - return 0; +int psu_lpd_protection(void) +{ + psu_init_xppu_aper_ram(); + return 0; } -int psu_ddr_protection() { - psu_ddr_xmpu0_data(); - psu_ddr_xmpu1_data(); - psu_ddr_xmpu2_data(); - psu_ddr_xmpu3_data(); - psu_ddr_xmpu4_data(); - psu_ddr_xmpu5_data(); - return 0; +int psu_ddr_protection(void) +{ + psu_ddr_xmpu0_data(); + psu_ddr_xmpu1_data(); + psu_ddr_xmpu2_data(); + psu_ddr_xmpu3_data(); + psu_ddr_xmpu4_data(); + psu_ddr_xmpu5_data(); + return 0; } -int psu_ocm_protection() { - psu_ocm_xmpu_data(); - return 0; +int psu_ocm_protection(void) +{ + psu_ocm_xmpu_data(); + return 0; } -int psu_fpd_protection() { - psu_fpd_xmpu_data(); - return 0; +int psu_fpd_protection(void) +{ + psu_fpd_xmpu_data(); + return 0; } -int psu_protection_lock() { - psu_protection_lock_data(); - return 0; +int psu_protection_lock(void) +{ + psu_protection_lock_data(); + return 0; } -int psu_protection() { - psu_ddr_protection(); - psu_ocm_protection(); - psu_fpd_protection(); - psu_lpd_protection(); - return 0; +int psu_protection(void) +{ + psu_apply_master_tz(); + psu_ddr_protection(); + psu_ocm_protection(); + psu_fpd_protection(); + psu_lpd_protection(); + return 0; } - - int -psu_init() +psu_init(void) { - int status = 1; - status &= psu_mio_init_data (); - status &= psu_pll_init_data (); - status &= psu_clock_init_data (); - - status &= psu_ddr_init_data (); - status &= psu_ddr_phybringup_data (); - status &= psu_peripherals_init_data (); + int status = 1; + status &= psu_mio_init_data(); + status &= psu_pll_init_data(); + status &= psu_clock_init_data(); + status &= psu_ddr_init_data(); + status &= psu_ddr_phybringup_data(); + status &= psu_peripherals_init_data(); status &= init_serdes(); - init_peripheral (); + init_peripheral(); - status &= psu_peripherals_powerdwn_data (); - - if (status == 0) { + status &= psu_peripherals_powerdwn_data(); + status &= psu_afi_config(); + psu_ddr_qos_init_data(); + + if (status == 0) return 1; - } return 0; } diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init_gpl.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init_gpl.h index 0fb578181..7feed7d35 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init_gpl.h +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init_gpl.h @@ -16,13 +16,13 @@ * with this program; if not, see * * -******************************************************************************/ +******************************************************************************/ /****************************************************************************/ /** * * @file psu_init_gpl.h * -* This file is automatically generated +* This file is automatically generated * *****************************************************************************/ @@ -41,8 +41,6 @@ #define CRL_APB_RPLL_CTRL_OFFSET 0XFF5E0030 #undef CRL_APB_RPLL_TO_FPD_CTRL_OFFSET #define CRL_APB_RPLL_TO_FPD_CTRL_OFFSET 0XFF5E0048 -#undef CRL_APB_RPLL_FRAC_CFG_OFFSET -#define CRL_APB_RPLL_FRAC_CFG_OFFSET 0XFF5E0038 #undef CRL_APB_IOPLL_CFG_OFFSET #define CRL_APB_IOPLL_CFG_OFFSET 0XFF5E0024 #undef CRL_APB_IOPLL_CTRL_OFFSET @@ -57,8 +55,6 @@ #define CRL_APB_IOPLL_CTRL_OFFSET 0XFF5E0020 #undef CRL_APB_IOPLL_TO_FPD_CTRL_OFFSET #define CRL_APB_IOPLL_TO_FPD_CTRL_OFFSET 0XFF5E0044 -#undef CRL_APB_IOPLL_FRAC_CFG_OFFSET -#define CRL_APB_IOPLL_FRAC_CFG_OFFSET 0XFF5E0028 #undef CRF_APB_APLL_CFG_OFFSET #define CRF_APB_APLL_CFG_OFFSET 0XFD1A0024 #undef CRF_APB_APLL_CTRL_OFFSET @@ -73,8 +69,6 @@ #define CRF_APB_APLL_CTRL_OFFSET 0XFD1A0020 #undef CRF_APB_APLL_TO_LPD_CTRL_OFFSET #define CRF_APB_APLL_TO_LPD_CTRL_OFFSET 0XFD1A0048 -#undef CRF_APB_APLL_FRAC_CFG_OFFSET -#define CRF_APB_APLL_FRAC_CFG_OFFSET 0XFD1A0028 #undef CRF_APB_DPLL_CFG_OFFSET #define CRF_APB_DPLL_CFG_OFFSET 0XFD1A0030 #undef CRF_APB_DPLL_CTRL_OFFSET @@ -89,8 +83,6 @@ #define CRF_APB_DPLL_CTRL_OFFSET 0XFD1A002C #undef CRF_APB_DPLL_TO_LPD_CTRL_OFFSET #define CRF_APB_DPLL_TO_LPD_CTRL_OFFSET 0XFD1A004C -#undef CRF_APB_DPLL_FRAC_CFG_OFFSET -#define CRF_APB_DPLL_FRAC_CFG_OFFSET 0XFD1A0034 #undef CRF_APB_VPLL_CFG_OFFSET #define CRF_APB_VPLL_CFG_OFFSET 0XFD1A003C #undef CRF_APB_VPLL_CTRL_OFFSET @@ -105,675 +97,770 @@ #define CRF_APB_VPLL_CTRL_OFFSET 0XFD1A0038 #undef CRF_APB_VPLL_TO_LPD_CTRL_OFFSET #define CRF_APB_VPLL_TO_LPD_CTRL_OFFSET 0XFD1A0050 -#undef CRF_APB_VPLL_FRAC_CFG_OFFSET -#define CRF_APB_VPLL_FRAC_CFG_OFFSET 0XFD1A0040 -/*PLL loop filter resistor control*/ +/* +* PLL loop filter resistor control +*/ #undef CRL_APB_RPLL_CFG_RES_DEFVAL #undef CRL_APB_RPLL_CFG_RES_SHIFT #undef CRL_APB_RPLL_CFG_RES_MASK -#define CRL_APB_RPLL_CFG_RES_DEFVAL 0x00000000 -#define CRL_APB_RPLL_CFG_RES_SHIFT 0 -#define CRL_APB_RPLL_CFG_RES_MASK 0x0000000FU +#define CRL_APB_RPLL_CFG_RES_DEFVAL 0x00000000 +#define CRL_APB_RPLL_CFG_RES_SHIFT 0 +#define CRL_APB_RPLL_CFG_RES_MASK 0x0000000FU -/*PLL charge pump control*/ +/* +* PLL charge pump control +*/ #undef CRL_APB_RPLL_CFG_CP_DEFVAL #undef CRL_APB_RPLL_CFG_CP_SHIFT #undef CRL_APB_RPLL_CFG_CP_MASK -#define CRL_APB_RPLL_CFG_CP_DEFVAL 0x00000000 -#define CRL_APB_RPLL_CFG_CP_SHIFT 5 -#define CRL_APB_RPLL_CFG_CP_MASK 0x000001E0U +#define CRL_APB_RPLL_CFG_CP_DEFVAL 0x00000000 +#define CRL_APB_RPLL_CFG_CP_SHIFT 5 +#define CRL_APB_RPLL_CFG_CP_MASK 0x000001E0U -/*PLL loop filter high frequency capacitor control*/ +/* +* PLL loop filter high frequency capacitor control +*/ #undef CRL_APB_RPLL_CFG_LFHF_DEFVAL #undef CRL_APB_RPLL_CFG_LFHF_SHIFT #undef CRL_APB_RPLL_CFG_LFHF_MASK -#define CRL_APB_RPLL_CFG_LFHF_DEFVAL 0x00000000 -#define CRL_APB_RPLL_CFG_LFHF_SHIFT 10 -#define CRL_APB_RPLL_CFG_LFHF_MASK 0x00000C00U +#define CRL_APB_RPLL_CFG_LFHF_DEFVAL 0x00000000 +#define CRL_APB_RPLL_CFG_LFHF_SHIFT 10 +#define CRL_APB_RPLL_CFG_LFHF_MASK 0x00000C00U -/*Lock circuit counter setting*/ +/* +* Lock circuit counter setting +*/ #undef CRL_APB_RPLL_CFG_LOCK_CNT_DEFVAL #undef CRL_APB_RPLL_CFG_LOCK_CNT_SHIFT #undef CRL_APB_RPLL_CFG_LOCK_CNT_MASK -#define CRL_APB_RPLL_CFG_LOCK_CNT_DEFVAL 0x00000000 -#define CRL_APB_RPLL_CFG_LOCK_CNT_SHIFT 13 -#define CRL_APB_RPLL_CFG_LOCK_CNT_MASK 0x007FE000U +#define CRL_APB_RPLL_CFG_LOCK_CNT_DEFVAL 0x00000000 +#define CRL_APB_RPLL_CFG_LOCK_CNT_SHIFT 13 +#define CRL_APB_RPLL_CFG_LOCK_CNT_MASK 0x007FE000U -/*Lock circuit configuration settings for lock windowsize*/ +/* +* Lock circuit configuration settings for lock windowsize +*/ #undef CRL_APB_RPLL_CFG_LOCK_DLY_DEFVAL #undef CRL_APB_RPLL_CFG_LOCK_DLY_SHIFT #undef CRL_APB_RPLL_CFG_LOCK_DLY_MASK -#define CRL_APB_RPLL_CFG_LOCK_DLY_DEFVAL 0x00000000 -#define CRL_APB_RPLL_CFG_LOCK_DLY_SHIFT 25 -#define CRL_APB_RPLL_CFG_LOCK_DLY_MASK 0xFE000000U +#define CRL_APB_RPLL_CFG_LOCK_DLY_DEFVAL 0x00000000 +#define CRL_APB_RPLL_CFG_LOCK_DLY_SHIFT 25 +#define CRL_APB_RPLL_CFG_LOCK_DLY_MASK 0xFE000000U -/*Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_ - ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source*/ +/* +* Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i + * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour + * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source +*/ #undef CRL_APB_RPLL_CTRL_PRE_SRC_DEFVAL #undef CRL_APB_RPLL_CTRL_PRE_SRC_SHIFT #undef CRL_APB_RPLL_CTRL_PRE_SRC_MASK -#define CRL_APB_RPLL_CTRL_PRE_SRC_DEFVAL 0x00012C09 -#define CRL_APB_RPLL_CTRL_PRE_SRC_SHIFT 20 -#define CRL_APB_RPLL_CTRL_PRE_SRC_MASK 0x00700000U +#define CRL_APB_RPLL_CTRL_PRE_SRC_DEFVAL 0x00012C09 +#define CRL_APB_RPLL_CTRL_PRE_SRC_SHIFT 20 +#define CRL_APB_RPLL_CTRL_PRE_SRC_MASK 0x00700000U -/*The integer portion of the feedback divider to the PLL*/ +/* +* The integer portion of the feedback divider to the PLL +*/ #undef CRL_APB_RPLL_CTRL_FBDIV_DEFVAL #undef CRL_APB_RPLL_CTRL_FBDIV_SHIFT #undef CRL_APB_RPLL_CTRL_FBDIV_MASK -#define CRL_APB_RPLL_CTRL_FBDIV_DEFVAL 0x00012C09 -#define CRL_APB_RPLL_CTRL_FBDIV_SHIFT 8 -#define CRL_APB_RPLL_CTRL_FBDIV_MASK 0x00007F00U +#define CRL_APB_RPLL_CTRL_FBDIV_DEFVAL 0x00012C09 +#define CRL_APB_RPLL_CTRL_FBDIV_SHIFT 8 +#define CRL_APB_RPLL_CTRL_FBDIV_MASK 0x00007F00U -/*This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency*/ +/* +* This turns on the divide by 2 that is inside of the PLL. This does not c + * hange the VCO frequency, just the output frequency +*/ #undef CRL_APB_RPLL_CTRL_DIV2_DEFVAL #undef CRL_APB_RPLL_CTRL_DIV2_SHIFT #undef CRL_APB_RPLL_CTRL_DIV2_MASK -#define CRL_APB_RPLL_CTRL_DIV2_DEFVAL 0x00012C09 -#define CRL_APB_RPLL_CTRL_DIV2_SHIFT 16 -#define CRL_APB_RPLL_CTRL_DIV2_MASK 0x00010000U +#define CRL_APB_RPLL_CTRL_DIV2_DEFVAL 0x00012C09 +#define CRL_APB_RPLL_CTRL_DIV2_SHIFT 16 +#define CRL_APB_RPLL_CTRL_DIV2_MASK 0x00010000U -/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/ +/* +* Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) +*/ #undef CRL_APB_RPLL_CTRL_BYPASS_DEFVAL #undef CRL_APB_RPLL_CTRL_BYPASS_SHIFT #undef CRL_APB_RPLL_CTRL_BYPASS_MASK -#define CRL_APB_RPLL_CTRL_BYPASS_DEFVAL 0x00012C09 -#define CRL_APB_RPLL_CTRL_BYPASS_SHIFT 3 -#define CRL_APB_RPLL_CTRL_BYPASS_MASK 0x00000008U +#define CRL_APB_RPLL_CTRL_BYPASS_DEFVAL 0x00012C09 +#define CRL_APB_RPLL_CTRL_BYPASS_SHIFT 3 +#define CRL_APB_RPLL_CTRL_BYPASS_MASK 0x00000008U -/*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/ +/* +* Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. +*/ #undef CRL_APB_RPLL_CTRL_RESET_DEFVAL #undef CRL_APB_RPLL_CTRL_RESET_SHIFT #undef CRL_APB_RPLL_CTRL_RESET_MASK -#define CRL_APB_RPLL_CTRL_RESET_DEFVAL 0x00012C09 -#define CRL_APB_RPLL_CTRL_RESET_SHIFT 0 -#define CRL_APB_RPLL_CTRL_RESET_MASK 0x00000001U +#define CRL_APB_RPLL_CTRL_RESET_DEFVAL 0x00012C09 +#define CRL_APB_RPLL_CTRL_RESET_SHIFT 0 +#define CRL_APB_RPLL_CTRL_RESET_MASK 0x00000001U -/*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/ +/* +* Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. +*/ #undef CRL_APB_RPLL_CTRL_RESET_DEFVAL #undef CRL_APB_RPLL_CTRL_RESET_SHIFT #undef CRL_APB_RPLL_CTRL_RESET_MASK -#define CRL_APB_RPLL_CTRL_RESET_DEFVAL 0x00012C09 -#define CRL_APB_RPLL_CTRL_RESET_SHIFT 0 -#define CRL_APB_RPLL_CTRL_RESET_MASK 0x00000001U +#define CRL_APB_RPLL_CTRL_RESET_DEFVAL 0x00012C09 +#define CRL_APB_RPLL_CTRL_RESET_SHIFT 0 +#define CRL_APB_RPLL_CTRL_RESET_MASK 0x00000001U -/*RPLL is locked*/ +/* +* RPLL is locked +*/ #undef CRL_APB_PLL_STATUS_RPLL_LOCK_DEFVAL #undef CRL_APB_PLL_STATUS_RPLL_LOCK_SHIFT #undef CRL_APB_PLL_STATUS_RPLL_LOCK_MASK -#define CRL_APB_PLL_STATUS_RPLL_LOCK_DEFVAL 0x00000018 -#define CRL_APB_PLL_STATUS_RPLL_LOCK_SHIFT 1 -#define CRL_APB_PLL_STATUS_RPLL_LOCK_MASK 0x00000002U +#define CRL_APB_PLL_STATUS_RPLL_LOCK_DEFVAL 0x00000018 +#define CRL_APB_PLL_STATUS_RPLL_LOCK_SHIFT 1 +#define CRL_APB_PLL_STATUS_RPLL_LOCK_MASK 0x00000002U #define CRL_APB_PLL_STATUS_OFFSET 0XFF5E0040 -/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/ +/* +* Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) +*/ #undef CRL_APB_RPLL_CTRL_BYPASS_DEFVAL #undef CRL_APB_RPLL_CTRL_BYPASS_SHIFT #undef CRL_APB_RPLL_CTRL_BYPASS_MASK -#define CRL_APB_RPLL_CTRL_BYPASS_DEFVAL 0x00012C09 -#define CRL_APB_RPLL_CTRL_BYPASS_SHIFT 3 -#define CRL_APB_RPLL_CTRL_BYPASS_MASK 0x00000008U +#define CRL_APB_RPLL_CTRL_BYPASS_DEFVAL 0x00012C09 +#define CRL_APB_RPLL_CTRL_BYPASS_SHIFT 3 +#define CRL_APB_RPLL_CTRL_BYPASS_MASK 0x00000008U -/*Divisor value for this clock.*/ +/* +* Divisor value for this clock. +*/ #undef CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL #undef CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_SHIFT #undef CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_MASK -#define CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL 0x00000400 -#define CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL 0x00000400 +#define CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_MASK 0x00003F00U -/*Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona - mode and uses DATA of this register for the fractional portion of the feedback divider.*/ -#undef CRL_APB_RPLL_FRAC_CFG_ENABLED_DEFVAL -#undef CRL_APB_RPLL_FRAC_CFG_ENABLED_SHIFT -#undef CRL_APB_RPLL_FRAC_CFG_ENABLED_MASK -#define CRL_APB_RPLL_FRAC_CFG_ENABLED_DEFVAL 0x00000000 -#define CRL_APB_RPLL_FRAC_CFG_ENABLED_SHIFT 31 -#define CRL_APB_RPLL_FRAC_CFG_ENABLED_MASK 0x80000000U - -/*Fractional value for the Feedback value.*/ -#undef CRL_APB_RPLL_FRAC_CFG_DATA_DEFVAL -#undef CRL_APB_RPLL_FRAC_CFG_DATA_SHIFT -#undef CRL_APB_RPLL_FRAC_CFG_DATA_MASK -#define CRL_APB_RPLL_FRAC_CFG_DATA_DEFVAL 0x00000000 -#define CRL_APB_RPLL_FRAC_CFG_DATA_SHIFT 0 -#define CRL_APB_RPLL_FRAC_CFG_DATA_MASK 0x0000FFFFU - -/*PLL loop filter resistor control*/ +/* +* PLL loop filter resistor control +*/ #undef CRL_APB_IOPLL_CFG_RES_DEFVAL #undef CRL_APB_IOPLL_CFG_RES_SHIFT #undef CRL_APB_IOPLL_CFG_RES_MASK -#define CRL_APB_IOPLL_CFG_RES_DEFVAL 0x00000000 -#define CRL_APB_IOPLL_CFG_RES_SHIFT 0 -#define CRL_APB_IOPLL_CFG_RES_MASK 0x0000000FU +#define CRL_APB_IOPLL_CFG_RES_DEFVAL 0x00000000 +#define CRL_APB_IOPLL_CFG_RES_SHIFT 0 +#define CRL_APB_IOPLL_CFG_RES_MASK 0x0000000FU -/*PLL charge pump control*/ +/* +* PLL charge pump control +*/ #undef CRL_APB_IOPLL_CFG_CP_DEFVAL #undef CRL_APB_IOPLL_CFG_CP_SHIFT #undef CRL_APB_IOPLL_CFG_CP_MASK -#define CRL_APB_IOPLL_CFG_CP_DEFVAL 0x00000000 -#define CRL_APB_IOPLL_CFG_CP_SHIFT 5 -#define CRL_APB_IOPLL_CFG_CP_MASK 0x000001E0U +#define CRL_APB_IOPLL_CFG_CP_DEFVAL 0x00000000 +#define CRL_APB_IOPLL_CFG_CP_SHIFT 5 +#define CRL_APB_IOPLL_CFG_CP_MASK 0x000001E0U -/*PLL loop filter high frequency capacitor control*/ +/* +* PLL loop filter high frequency capacitor control +*/ #undef CRL_APB_IOPLL_CFG_LFHF_DEFVAL #undef CRL_APB_IOPLL_CFG_LFHF_SHIFT #undef CRL_APB_IOPLL_CFG_LFHF_MASK -#define CRL_APB_IOPLL_CFG_LFHF_DEFVAL 0x00000000 -#define CRL_APB_IOPLL_CFG_LFHF_SHIFT 10 -#define CRL_APB_IOPLL_CFG_LFHF_MASK 0x00000C00U +#define CRL_APB_IOPLL_CFG_LFHF_DEFVAL 0x00000000 +#define CRL_APB_IOPLL_CFG_LFHF_SHIFT 10 +#define CRL_APB_IOPLL_CFG_LFHF_MASK 0x00000C00U -/*Lock circuit counter setting*/ +/* +* Lock circuit counter setting +*/ #undef CRL_APB_IOPLL_CFG_LOCK_CNT_DEFVAL #undef CRL_APB_IOPLL_CFG_LOCK_CNT_SHIFT #undef CRL_APB_IOPLL_CFG_LOCK_CNT_MASK -#define CRL_APB_IOPLL_CFG_LOCK_CNT_DEFVAL 0x00000000 -#define CRL_APB_IOPLL_CFG_LOCK_CNT_SHIFT 13 -#define CRL_APB_IOPLL_CFG_LOCK_CNT_MASK 0x007FE000U +#define CRL_APB_IOPLL_CFG_LOCK_CNT_DEFVAL 0x00000000 +#define CRL_APB_IOPLL_CFG_LOCK_CNT_SHIFT 13 +#define CRL_APB_IOPLL_CFG_LOCK_CNT_MASK 0x007FE000U -/*Lock circuit configuration settings for lock windowsize*/ +/* +* Lock circuit configuration settings for lock windowsize +*/ #undef CRL_APB_IOPLL_CFG_LOCK_DLY_DEFVAL #undef CRL_APB_IOPLL_CFG_LOCK_DLY_SHIFT #undef CRL_APB_IOPLL_CFG_LOCK_DLY_MASK -#define CRL_APB_IOPLL_CFG_LOCK_DLY_DEFVAL 0x00000000 -#define CRL_APB_IOPLL_CFG_LOCK_DLY_SHIFT 25 -#define CRL_APB_IOPLL_CFG_LOCK_DLY_MASK 0xFE000000U +#define CRL_APB_IOPLL_CFG_LOCK_DLY_DEFVAL 0x00000000 +#define CRL_APB_IOPLL_CFG_LOCK_DLY_SHIFT 25 +#define CRL_APB_IOPLL_CFG_LOCK_DLY_MASK 0xFE000000U -/*Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_ - ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source*/ +/* +* Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i + * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour + * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source +*/ #undef CRL_APB_IOPLL_CTRL_PRE_SRC_DEFVAL #undef CRL_APB_IOPLL_CTRL_PRE_SRC_SHIFT #undef CRL_APB_IOPLL_CTRL_PRE_SRC_MASK -#define CRL_APB_IOPLL_CTRL_PRE_SRC_DEFVAL 0x00012C09 -#define CRL_APB_IOPLL_CTRL_PRE_SRC_SHIFT 20 -#define CRL_APB_IOPLL_CTRL_PRE_SRC_MASK 0x00700000U +#define CRL_APB_IOPLL_CTRL_PRE_SRC_DEFVAL 0x00012C09 +#define CRL_APB_IOPLL_CTRL_PRE_SRC_SHIFT 20 +#define CRL_APB_IOPLL_CTRL_PRE_SRC_MASK 0x00700000U -/*The integer portion of the feedback divider to the PLL*/ +/* +* The integer portion of the feedback divider to the PLL +*/ #undef CRL_APB_IOPLL_CTRL_FBDIV_DEFVAL #undef CRL_APB_IOPLL_CTRL_FBDIV_SHIFT #undef CRL_APB_IOPLL_CTRL_FBDIV_MASK -#define CRL_APB_IOPLL_CTRL_FBDIV_DEFVAL 0x00012C09 -#define CRL_APB_IOPLL_CTRL_FBDIV_SHIFT 8 -#define CRL_APB_IOPLL_CTRL_FBDIV_MASK 0x00007F00U +#define CRL_APB_IOPLL_CTRL_FBDIV_DEFVAL 0x00012C09 +#define CRL_APB_IOPLL_CTRL_FBDIV_SHIFT 8 +#define CRL_APB_IOPLL_CTRL_FBDIV_MASK 0x00007F00U -/*This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency*/ +/* +* This turns on the divide by 2 that is inside of the PLL. This does not c + * hange the VCO frequency, just the output frequency +*/ #undef CRL_APB_IOPLL_CTRL_DIV2_DEFVAL #undef CRL_APB_IOPLL_CTRL_DIV2_SHIFT #undef CRL_APB_IOPLL_CTRL_DIV2_MASK -#define CRL_APB_IOPLL_CTRL_DIV2_DEFVAL 0x00012C09 -#define CRL_APB_IOPLL_CTRL_DIV2_SHIFT 16 -#define CRL_APB_IOPLL_CTRL_DIV2_MASK 0x00010000U +#define CRL_APB_IOPLL_CTRL_DIV2_DEFVAL 0x00012C09 +#define CRL_APB_IOPLL_CTRL_DIV2_SHIFT 16 +#define CRL_APB_IOPLL_CTRL_DIV2_MASK 0x00010000U -/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/ +/* +* Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) +*/ #undef CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL #undef CRL_APB_IOPLL_CTRL_BYPASS_SHIFT #undef CRL_APB_IOPLL_CTRL_BYPASS_MASK -#define CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL 0x00012C09 -#define CRL_APB_IOPLL_CTRL_BYPASS_SHIFT 3 -#define CRL_APB_IOPLL_CTRL_BYPASS_MASK 0x00000008U +#define CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL 0x00012C09 +#define CRL_APB_IOPLL_CTRL_BYPASS_SHIFT 3 +#define CRL_APB_IOPLL_CTRL_BYPASS_MASK 0x00000008U -/*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/ +/* +* Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. +*/ #undef CRL_APB_IOPLL_CTRL_RESET_DEFVAL #undef CRL_APB_IOPLL_CTRL_RESET_SHIFT #undef CRL_APB_IOPLL_CTRL_RESET_MASK -#define CRL_APB_IOPLL_CTRL_RESET_DEFVAL 0x00012C09 -#define CRL_APB_IOPLL_CTRL_RESET_SHIFT 0 -#define CRL_APB_IOPLL_CTRL_RESET_MASK 0x00000001U +#define CRL_APB_IOPLL_CTRL_RESET_DEFVAL 0x00012C09 +#define CRL_APB_IOPLL_CTRL_RESET_SHIFT 0 +#define CRL_APB_IOPLL_CTRL_RESET_MASK 0x00000001U -/*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/ +/* +* Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. +*/ #undef CRL_APB_IOPLL_CTRL_RESET_DEFVAL #undef CRL_APB_IOPLL_CTRL_RESET_SHIFT #undef CRL_APB_IOPLL_CTRL_RESET_MASK -#define CRL_APB_IOPLL_CTRL_RESET_DEFVAL 0x00012C09 -#define CRL_APB_IOPLL_CTRL_RESET_SHIFT 0 -#define CRL_APB_IOPLL_CTRL_RESET_MASK 0x00000001U +#define CRL_APB_IOPLL_CTRL_RESET_DEFVAL 0x00012C09 +#define CRL_APB_IOPLL_CTRL_RESET_SHIFT 0 +#define CRL_APB_IOPLL_CTRL_RESET_MASK 0x00000001U -/*IOPLL is locked*/ +/* +* IOPLL is locked +*/ #undef CRL_APB_PLL_STATUS_IOPLL_LOCK_DEFVAL #undef CRL_APB_PLL_STATUS_IOPLL_LOCK_SHIFT #undef CRL_APB_PLL_STATUS_IOPLL_LOCK_MASK -#define CRL_APB_PLL_STATUS_IOPLL_LOCK_DEFVAL 0x00000018 -#define CRL_APB_PLL_STATUS_IOPLL_LOCK_SHIFT 0 -#define CRL_APB_PLL_STATUS_IOPLL_LOCK_MASK 0x00000001U +#define CRL_APB_PLL_STATUS_IOPLL_LOCK_DEFVAL 0x00000018 +#define CRL_APB_PLL_STATUS_IOPLL_LOCK_SHIFT 0 +#define CRL_APB_PLL_STATUS_IOPLL_LOCK_MASK 0x00000001U #define CRL_APB_PLL_STATUS_OFFSET 0XFF5E0040 -/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/ +/* +* Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) +*/ #undef CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL #undef CRL_APB_IOPLL_CTRL_BYPASS_SHIFT #undef CRL_APB_IOPLL_CTRL_BYPASS_MASK -#define CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL 0x00012C09 -#define CRL_APB_IOPLL_CTRL_BYPASS_SHIFT 3 -#define CRL_APB_IOPLL_CTRL_BYPASS_MASK 0x00000008U +#define CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL 0x00012C09 +#define CRL_APB_IOPLL_CTRL_BYPASS_SHIFT 3 +#define CRL_APB_IOPLL_CTRL_BYPASS_MASK 0x00000008U -/*Divisor value for this clock.*/ +/* +* Divisor value for this clock. +*/ #undef CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL #undef CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_SHIFT #undef CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_MASK -#define CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL 0x00000400 -#define CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL 0x00000400 +#define CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_MASK 0x00003F00U -/*Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona - mode and uses DATA of this register for the fractional portion of the feedback divider.*/ -#undef CRL_APB_IOPLL_FRAC_CFG_ENABLED_DEFVAL -#undef CRL_APB_IOPLL_FRAC_CFG_ENABLED_SHIFT -#undef CRL_APB_IOPLL_FRAC_CFG_ENABLED_MASK -#define CRL_APB_IOPLL_FRAC_CFG_ENABLED_DEFVAL 0x00000000 -#define CRL_APB_IOPLL_FRAC_CFG_ENABLED_SHIFT 31 -#define CRL_APB_IOPLL_FRAC_CFG_ENABLED_MASK 0x80000000U - -/*Fractional value for the Feedback value.*/ -#undef CRL_APB_IOPLL_FRAC_CFG_DATA_DEFVAL -#undef CRL_APB_IOPLL_FRAC_CFG_DATA_SHIFT -#undef CRL_APB_IOPLL_FRAC_CFG_DATA_MASK -#define CRL_APB_IOPLL_FRAC_CFG_DATA_DEFVAL 0x00000000 -#define CRL_APB_IOPLL_FRAC_CFG_DATA_SHIFT 0 -#define CRL_APB_IOPLL_FRAC_CFG_DATA_MASK 0x0000FFFFU - -/*PLL loop filter resistor control*/ +/* +* PLL loop filter resistor control +*/ #undef CRF_APB_APLL_CFG_RES_DEFVAL #undef CRF_APB_APLL_CFG_RES_SHIFT #undef CRF_APB_APLL_CFG_RES_MASK -#define CRF_APB_APLL_CFG_RES_DEFVAL 0x00000000 -#define CRF_APB_APLL_CFG_RES_SHIFT 0 -#define CRF_APB_APLL_CFG_RES_MASK 0x0000000FU +#define CRF_APB_APLL_CFG_RES_DEFVAL 0x00000000 +#define CRF_APB_APLL_CFG_RES_SHIFT 0 +#define CRF_APB_APLL_CFG_RES_MASK 0x0000000FU -/*PLL charge pump control*/ +/* +* PLL charge pump control +*/ #undef CRF_APB_APLL_CFG_CP_DEFVAL #undef CRF_APB_APLL_CFG_CP_SHIFT #undef CRF_APB_APLL_CFG_CP_MASK -#define CRF_APB_APLL_CFG_CP_DEFVAL 0x00000000 -#define CRF_APB_APLL_CFG_CP_SHIFT 5 -#define CRF_APB_APLL_CFG_CP_MASK 0x000001E0U +#define CRF_APB_APLL_CFG_CP_DEFVAL 0x00000000 +#define CRF_APB_APLL_CFG_CP_SHIFT 5 +#define CRF_APB_APLL_CFG_CP_MASK 0x000001E0U -/*PLL loop filter high frequency capacitor control*/ +/* +* PLL loop filter high frequency capacitor control +*/ #undef CRF_APB_APLL_CFG_LFHF_DEFVAL #undef CRF_APB_APLL_CFG_LFHF_SHIFT #undef CRF_APB_APLL_CFG_LFHF_MASK -#define CRF_APB_APLL_CFG_LFHF_DEFVAL 0x00000000 -#define CRF_APB_APLL_CFG_LFHF_SHIFT 10 -#define CRF_APB_APLL_CFG_LFHF_MASK 0x00000C00U +#define CRF_APB_APLL_CFG_LFHF_DEFVAL 0x00000000 +#define CRF_APB_APLL_CFG_LFHF_SHIFT 10 +#define CRF_APB_APLL_CFG_LFHF_MASK 0x00000C00U -/*Lock circuit counter setting*/ +/* +* Lock circuit counter setting +*/ #undef CRF_APB_APLL_CFG_LOCK_CNT_DEFVAL #undef CRF_APB_APLL_CFG_LOCK_CNT_SHIFT #undef CRF_APB_APLL_CFG_LOCK_CNT_MASK -#define CRF_APB_APLL_CFG_LOCK_CNT_DEFVAL 0x00000000 -#define CRF_APB_APLL_CFG_LOCK_CNT_SHIFT 13 -#define CRF_APB_APLL_CFG_LOCK_CNT_MASK 0x007FE000U +#define CRF_APB_APLL_CFG_LOCK_CNT_DEFVAL 0x00000000 +#define CRF_APB_APLL_CFG_LOCK_CNT_SHIFT 13 +#define CRF_APB_APLL_CFG_LOCK_CNT_MASK 0x007FE000U -/*Lock circuit configuration settings for lock windowsize*/ +/* +* Lock circuit configuration settings for lock windowsize +*/ #undef CRF_APB_APLL_CFG_LOCK_DLY_DEFVAL #undef CRF_APB_APLL_CFG_LOCK_DLY_SHIFT #undef CRF_APB_APLL_CFG_LOCK_DLY_MASK -#define CRF_APB_APLL_CFG_LOCK_DLY_DEFVAL 0x00000000 -#define CRF_APB_APLL_CFG_LOCK_DLY_SHIFT 25 -#define CRF_APB_APLL_CFG_LOCK_DLY_MASK 0xFE000000U +#define CRF_APB_APLL_CFG_LOCK_DLY_DEFVAL 0x00000000 +#define CRF_APB_APLL_CFG_LOCK_DLY_SHIFT 25 +#define CRF_APB_APLL_CFG_LOCK_DLY_MASK 0xFE000000U -/*Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_ - ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source*/ +/* +* Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i + * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour + * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source +*/ #undef CRF_APB_APLL_CTRL_PRE_SRC_DEFVAL #undef CRF_APB_APLL_CTRL_PRE_SRC_SHIFT #undef CRF_APB_APLL_CTRL_PRE_SRC_MASK -#define CRF_APB_APLL_CTRL_PRE_SRC_DEFVAL 0x00012C09 -#define CRF_APB_APLL_CTRL_PRE_SRC_SHIFT 20 -#define CRF_APB_APLL_CTRL_PRE_SRC_MASK 0x00700000U +#define CRF_APB_APLL_CTRL_PRE_SRC_DEFVAL 0x00012C09 +#define CRF_APB_APLL_CTRL_PRE_SRC_SHIFT 20 +#define CRF_APB_APLL_CTRL_PRE_SRC_MASK 0x00700000U -/*The integer portion of the feedback divider to the PLL*/ +/* +* The integer portion of the feedback divider to the PLL +*/ #undef CRF_APB_APLL_CTRL_FBDIV_DEFVAL #undef CRF_APB_APLL_CTRL_FBDIV_SHIFT #undef CRF_APB_APLL_CTRL_FBDIV_MASK -#define CRF_APB_APLL_CTRL_FBDIV_DEFVAL 0x00012C09 -#define CRF_APB_APLL_CTRL_FBDIV_SHIFT 8 -#define CRF_APB_APLL_CTRL_FBDIV_MASK 0x00007F00U +#define CRF_APB_APLL_CTRL_FBDIV_DEFVAL 0x00012C09 +#define CRF_APB_APLL_CTRL_FBDIV_SHIFT 8 +#define CRF_APB_APLL_CTRL_FBDIV_MASK 0x00007F00U -/*This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency*/ +/* +* This turns on the divide by 2 that is inside of the PLL. This does not c + * hange the VCO frequency, just the output frequency +*/ #undef CRF_APB_APLL_CTRL_DIV2_DEFVAL #undef CRF_APB_APLL_CTRL_DIV2_SHIFT #undef CRF_APB_APLL_CTRL_DIV2_MASK -#define CRF_APB_APLL_CTRL_DIV2_DEFVAL 0x00012C09 -#define CRF_APB_APLL_CTRL_DIV2_SHIFT 16 -#define CRF_APB_APLL_CTRL_DIV2_MASK 0x00010000U +#define CRF_APB_APLL_CTRL_DIV2_DEFVAL 0x00012C09 +#define CRF_APB_APLL_CTRL_DIV2_SHIFT 16 +#define CRF_APB_APLL_CTRL_DIV2_MASK 0x00010000U -/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/ +/* +* Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) +*/ #undef CRF_APB_APLL_CTRL_BYPASS_DEFVAL #undef CRF_APB_APLL_CTRL_BYPASS_SHIFT #undef CRF_APB_APLL_CTRL_BYPASS_MASK -#define CRF_APB_APLL_CTRL_BYPASS_DEFVAL 0x00012C09 -#define CRF_APB_APLL_CTRL_BYPASS_SHIFT 3 -#define CRF_APB_APLL_CTRL_BYPASS_MASK 0x00000008U +#define CRF_APB_APLL_CTRL_BYPASS_DEFVAL 0x00012C09 +#define CRF_APB_APLL_CTRL_BYPASS_SHIFT 3 +#define CRF_APB_APLL_CTRL_BYPASS_MASK 0x00000008U -/*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/ +/* +* Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. +*/ #undef CRF_APB_APLL_CTRL_RESET_DEFVAL #undef CRF_APB_APLL_CTRL_RESET_SHIFT #undef CRF_APB_APLL_CTRL_RESET_MASK -#define CRF_APB_APLL_CTRL_RESET_DEFVAL 0x00012C09 -#define CRF_APB_APLL_CTRL_RESET_SHIFT 0 -#define CRF_APB_APLL_CTRL_RESET_MASK 0x00000001U +#define CRF_APB_APLL_CTRL_RESET_DEFVAL 0x00012C09 +#define CRF_APB_APLL_CTRL_RESET_SHIFT 0 +#define CRF_APB_APLL_CTRL_RESET_MASK 0x00000001U -/*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/ +/* +* Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. +*/ #undef CRF_APB_APLL_CTRL_RESET_DEFVAL #undef CRF_APB_APLL_CTRL_RESET_SHIFT #undef CRF_APB_APLL_CTRL_RESET_MASK -#define CRF_APB_APLL_CTRL_RESET_DEFVAL 0x00012C09 -#define CRF_APB_APLL_CTRL_RESET_SHIFT 0 -#define CRF_APB_APLL_CTRL_RESET_MASK 0x00000001U +#define CRF_APB_APLL_CTRL_RESET_DEFVAL 0x00012C09 +#define CRF_APB_APLL_CTRL_RESET_SHIFT 0 +#define CRF_APB_APLL_CTRL_RESET_MASK 0x00000001U -/*APLL is locked*/ +/* +* APLL is locked +*/ #undef CRF_APB_PLL_STATUS_APLL_LOCK_DEFVAL #undef CRF_APB_PLL_STATUS_APLL_LOCK_SHIFT #undef CRF_APB_PLL_STATUS_APLL_LOCK_MASK -#define CRF_APB_PLL_STATUS_APLL_LOCK_DEFVAL 0x00000038 -#define CRF_APB_PLL_STATUS_APLL_LOCK_SHIFT 0 -#define CRF_APB_PLL_STATUS_APLL_LOCK_MASK 0x00000001U +#define CRF_APB_PLL_STATUS_APLL_LOCK_DEFVAL 0x00000038 +#define CRF_APB_PLL_STATUS_APLL_LOCK_SHIFT 0 +#define CRF_APB_PLL_STATUS_APLL_LOCK_MASK 0x00000001U #define CRF_APB_PLL_STATUS_OFFSET 0XFD1A0044 -/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/ +/* +* Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) +*/ #undef CRF_APB_APLL_CTRL_BYPASS_DEFVAL #undef CRF_APB_APLL_CTRL_BYPASS_SHIFT #undef CRF_APB_APLL_CTRL_BYPASS_MASK -#define CRF_APB_APLL_CTRL_BYPASS_DEFVAL 0x00012C09 -#define CRF_APB_APLL_CTRL_BYPASS_SHIFT 3 -#define CRF_APB_APLL_CTRL_BYPASS_MASK 0x00000008U +#define CRF_APB_APLL_CTRL_BYPASS_DEFVAL 0x00012C09 +#define CRF_APB_APLL_CTRL_BYPASS_SHIFT 3 +#define CRF_APB_APLL_CTRL_BYPASS_MASK 0x00000008U -/*Divisor value for this clock.*/ +/* +* Divisor value for this clock. +*/ #undef CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_DEFVAL #undef CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_SHIFT #undef CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_MASK -#define CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_DEFVAL 0x00000400 -#define CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_SHIFT 8 -#define CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_DEFVAL 0x00000400 +#define CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_MASK 0x00003F00U -/*Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona - mode and uses DATA of this register for the fractional portion of the feedback divider.*/ -#undef CRF_APB_APLL_FRAC_CFG_ENABLED_DEFVAL -#undef CRF_APB_APLL_FRAC_CFG_ENABLED_SHIFT -#undef CRF_APB_APLL_FRAC_CFG_ENABLED_MASK -#define CRF_APB_APLL_FRAC_CFG_ENABLED_DEFVAL 0x00000000 -#define CRF_APB_APLL_FRAC_CFG_ENABLED_SHIFT 31 -#define CRF_APB_APLL_FRAC_CFG_ENABLED_MASK 0x80000000U - -/*Fractional value for the Feedback value.*/ -#undef CRF_APB_APLL_FRAC_CFG_DATA_DEFVAL -#undef CRF_APB_APLL_FRAC_CFG_DATA_SHIFT -#undef CRF_APB_APLL_FRAC_CFG_DATA_MASK -#define CRF_APB_APLL_FRAC_CFG_DATA_DEFVAL 0x00000000 -#define CRF_APB_APLL_FRAC_CFG_DATA_SHIFT 0 -#define CRF_APB_APLL_FRAC_CFG_DATA_MASK 0x0000FFFFU - -/*PLL loop filter resistor control*/ +/* +* PLL loop filter resistor control +*/ #undef CRF_APB_DPLL_CFG_RES_DEFVAL #undef CRF_APB_DPLL_CFG_RES_SHIFT #undef CRF_APB_DPLL_CFG_RES_MASK -#define CRF_APB_DPLL_CFG_RES_DEFVAL 0x00000000 -#define CRF_APB_DPLL_CFG_RES_SHIFT 0 -#define CRF_APB_DPLL_CFG_RES_MASK 0x0000000FU +#define CRF_APB_DPLL_CFG_RES_DEFVAL 0x00000000 +#define CRF_APB_DPLL_CFG_RES_SHIFT 0 +#define CRF_APB_DPLL_CFG_RES_MASK 0x0000000FU -/*PLL charge pump control*/ +/* +* PLL charge pump control +*/ #undef CRF_APB_DPLL_CFG_CP_DEFVAL #undef CRF_APB_DPLL_CFG_CP_SHIFT #undef CRF_APB_DPLL_CFG_CP_MASK -#define CRF_APB_DPLL_CFG_CP_DEFVAL 0x00000000 -#define CRF_APB_DPLL_CFG_CP_SHIFT 5 -#define CRF_APB_DPLL_CFG_CP_MASK 0x000001E0U +#define CRF_APB_DPLL_CFG_CP_DEFVAL 0x00000000 +#define CRF_APB_DPLL_CFG_CP_SHIFT 5 +#define CRF_APB_DPLL_CFG_CP_MASK 0x000001E0U -/*PLL loop filter high frequency capacitor control*/ +/* +* PLL loop filter high frequency capacitor control +*/ #undef CRF_APB_DPLL_CFG_LFHF_DEFVAL #undef CRF_APB_DPLL_CFG_LFHF_SHIFT #undef CRF_APB_DPLL_CFG_LFHF_MASK -#define CRF_APB_DPLL_CFG_LFHF_DEFVAL 0x00000000 -#define CRF_APB_DPLL_CFG_LFHF_SHIFT 10 -#define CRF_APB_DPLL_CFG_LFHF_MASK 0x00000C00U +#define CRF_APB_DPLL_CFG_LFHF_DEFVAL 0x00000000 +#define CRF_APB_DPLL_CFG_LFHF_SHIFT 10 +#define CRF_APB_DPLL_CFG_LFHF_MASK 0x00000C00U -/*Lock circuit counter setting*/ +/* +* Lock circuit counter setting +*/ #undef CRF_APB_DPLL_CFG_LOCK_CNT_DEFVAL #undef CRF_APB_DPLL_CFG_LOCK_CNT_SHIFT #undef CRF_APB_DPLL_CFG_LOCK_CNT_MASK -#define CRF_APB_DPLL_CFG_LOCK_CNT_DEFVAL 0x00000000 -#define CRF_APB_DPLL_CFG_LOCK_CNT_SHIFT 13 -#define CRF_APB_DPLL_CFG_LOCK_CNT_MASK 0x007FE000U +#define CRF_APB_DPLL_CFG_LOCK_CNT_DEFVAL 0x00000000 +#define CRF_APB_DPLL_CFG_LOCK_CNT_SHIFT 13 +#define CRF_APB_DPLL_CFG_LOCK_CNT_MASK 0x007FE000U -/*Lock circuit configuration settings for lock windowsize*/ +/* +* Lock circuit configuration settings for lock windowsize +*/ #undef CRF_APB_DPLL_CFG_LOCK_DLY_DEFVAL #undef CRF_APB_DPLL_CFG_LOCK_DLY_SHIFT #undef CRF_APB_DPLL_CFG_LOCK_DLY_MASK -#define CRF_APB_DPLL_CFG_LOCK_DLY_DEFVAL 0x00000000 -#define CRF_APB_DPLL_CFG_LOCK_DLY_SHIFT 25 -#define CRF_APB_DPLL_CFG_LOCK_DLY_MASK 0xFE000000U +#define CRF_APB_DPLL_CFG_LOCK_DLY_DEFVAL 0x00000000 +#define CRF_APB_DPLL_CFG_LOCK_DLY_SHIFT 25 +#define CRF_APB_DPLL_CFG_LOCK_DLY_MASK 0xFE000000U -/*Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_ - ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source*/ +/* +* Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i + * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour + * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source +*/ #undef CRF_APB_DPLL_CTRL_PRE_SRC_DEFVAL #undef CRF_APB_DPLL_CTRL_PRE_SRC_SHIFT #undef CRF_APB_DPLL_CTRL_PRE_SRC_MASK -#define CRF_APB_DPLL_CTRL_PRE_SRC_DEFVAL 0x00002C09 -#define CRF_APB_DPLL_CTRL_PRE_SRC_SHIFT 20 -#define CRF_APB_DPLL_CTRL_PRE_SRC_MASK 0x00700000U +#define CRF_APB_DPLL_CTRL_PRE_SRC_DEFVAL 0x00002C09 +#define CRF_APB_DPLL_CTRL_PRE_SRC_SHIFT 20 +#define CRF_APB_DPLL_CTRL_PRE_SRC_MASK 0x00700000U -/*The integer portion of the feedback divider to the PLL*/ +/* +* The integer portion of the feedback divider to the PLL +*/ #undef CRF_APB_DPLL_CTRL_FBDIV_DEFVAL #undef CRF_APB_DPLL_CTRL_FBDIV_SHIFT #undef CRF_APB_DPLL_CTRL_FBDIV_MASK -#define CRF_APB_DPLL_CTRL_FBDIV_DEFVAL 0x00002C09 -#define CRF_APB_DPLL_CTRL_FBDIV_SHIFT 8 -#define CRF_APB_DPLL_CTRL_FBDIV_MASK 0x00007F00U +#define CRF_APB_DPLL_CTRL_FBDIV_DEFVAL 0x00002C09 +#define CRF_APB_DPLL_CTRL_FBDIV_SHIFT 8 +#define CRF_APB_DPLL_CTRL_FBDIV_MASK 0x00007F00U -/*This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency*/ +/* +* This turns on the divide by 2 that is inside of the PLL. This does not c + * hange the VCO frequency, just the output frequency +*/ #undef CRF_APB_DPLL_CTRL_DIV2_DEFVAL #undef CRF_APB_DPLL_CTRL_DIV2_SHIFT #undef CRF_APB_DPLL_CTRL_DIV2_MASK -#define CRF_APB_DPLL_CTRL_DIV2_DEFVAL 0x00002C09 -#define CRF_APB_DPLL_CTRL_DIV2_SHIFT 16 -#define CRF_APB_DPLL_CTRL_DIV2_MASK 0x00010000U +#define CRF_APB_DPLL_CTRL_DIV2_DEFVAL 0x00002C09 +#define CRF_APB_DPLL_CTRL_DIV2_SHIFT 16 +#define CRF_APB_DPLL_CTRL_DIV2_MASK 0x00010000U -/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/ +/* +* Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) +*/ #undef CRF_APB_DPLL_CTRL_BYPASS_DEFVAL #undef CRF_APB_DPLL_CTRL_BYPASS_SHIFT #undef CRF_APB_DPLL_CTRL_BYPASS_MASK -#define CRF_APB_DPLL_CTRL_BYPASS_DEFVAL 0x00002C09 -#define CRF_APB_DPLL_CTRL_BYPASS_SHIFT 3 -#define CRF_APB_DPLL_CTRL_BYPASS_MASK 0x00000008U +#define CRF_APB_DPLL_CTRL_BYPASS_DEFVAL 0x00002C09 +#define CRF_APB_DPLL_CTRL_BYPASS_SHIFT 3 +#define CRF_APB_DPLL_CTRL_BYPASS_MASK 0x00000008U -/*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/ +/* +* Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. +*/ #undef CRF_APB_DPLL_CTRL_RESET_DEFVAL #undef CRF_APB_DPLL_CTRL_RESET_SHIFT #undef CRF_APB_DPLL_CTRL_RESET_MASK -#define CRF_APB_DPLL_CTRL_RESET_DEFVAL 0x00002C09 -#define CRF_APB_DPLL_CTRL_RESET_SHIFT 0 -#define CRF_APB_DPLL_CTRL_RESET_MASK 0x00000001U +#define CRF_APB_DPLL_CTRL_RESET_DEFVAL 0x00002C09 +#define CRF_APB_DPLL_CTRL_RESET_SHIFT 0 +#define CRF_APB_DPLL_CTRL_RESET_MASK 0x00000001U -/*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/ +/* +* Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. +*/ #undef CRF_APB_DPLL_CTRL_RESET_DEFVAL #undef CRF_APB_DPLL_CTRL_RESET_SHIFT #undef CRF_APB_DPLL_CTRL_RESET_MASK -#define CRF_APB_DPLL_CTRL_RESET_DEFVAL 0x00002C09 -#define CRF_APB_DPLL_CTRL_RESET_SHIFT 0 -#define CRF_APB_DPLL_CTRL_RESET_MASK 0x00000001U +#define CRF_APB_DPLL_CTRL_RESET_DEFVAL 0x00002C09 +#define CRF_APB_DPLL_CTRL_RESET_SHIFT 0 +#define CRF_APB_DPLL_CTRL_RESET_MASK 0x00000001U -/*DPLL is locked*/ +/* +* DPLL is locked +*/ #undef CRF_APB_PLL_STATUS_DPLL_LOCK_DEFVAL #undef CRF_APB_PLL_STATUS_DPLL_LOCK_SHIFT #undef CRF_APB_PLL_STATUS_DPLL_LOCK_MASK -#define CRF_APB_PLL_STATUS_DPLL_LOCK_DEFVAL 0x00000038 -#define CRF_APB_PLL_STATUS_DPLL_LOCK_SHIFT 1 -#define CRF_APB_PLL_STATUS_DPLL_LOCK_MASK 0x00000002U +#define CRF_APB_PLL_STATUS_DPLL_LOCK_DEFVAL 0x00000038 +#define CRF_APB_PLL_STATUS_DPLL_LOCK_SHIFT 1 +#define CRF_APB_PLL_STATUS_DPLL_LOCK_MASK 0x00000002U #define CRF_APB_PLL_STATUS_OFFSET 0XFD1A0044 -/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/ +/* +* Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) +*/ #undef CRF_APB_DPLL_CTRL_BYPASS_DEFVAL #undef CRF_APB_DPLL_CTRL_BYPASS_SHIFT #undef CRF_APB_DPLL_CTRL_BYPASS_MASK -#define CRF_APB_DPLL_CTRL_BYPASS_DEFVAL 0x00002C09 -#define CRF_APB_DPLL_CTRL_BYPASS_SHIFT 3 -#define CRF_APB_DPLL_CTRL_BYPASS_MASK 0x00000008U +#define CRF_APB_DPLL_CTRL_BYPASS_DEFVAL 0x00002C09 +#define CRF_APB_DPLL_CTRL_BYPASS_SHIFT 3 +#define CRF_APB_DPLL_CTRL_BYPASS_MASK 0x00000008U -/*Divisor value for this clock.*/ +/* +* Divisor value for this clock. +*/ #undef CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL #undef CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_SHIFT #undef CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_MASK -#define CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL 0x00000400 -#define CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_SHIFT 8 -#define CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL 0x00000400 +#define CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_MASK 0x00003F00U -/*Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona - mode and uses DATA of this register for the fractional portion of the feedback divider.*/ -#undef CRF_APB_DPLL_FRAC_CFG_ENABLED_DEFVAL -#undef CRF_APB_DPLL_FRAC_CFG_ENABLED_SHIFT -#undef CRF_APB_DPLL_FRAC_CFG_ENABLED_MASK -#define CRF_APB_DPLL_FRAC_CFG_ENABLED_DEFVAL 0x00000000 -#define CRF_APB_DPLL_FRAC_CFG_ENABLED_SHIFT 31 -#define CRF_APB_DPLL_FRAC_CFG_ENABLED_MASK 0x80000000U - -/*Fractional value for the Feedback value.*/ -#undef CRF_APB_DPLL_FRAC_CFG_DATA_DEFVAL -#undef CRF_APB_DPLL_FRAC_CFG_DATA_SHIFT -#undef CRF_APB_DPLL_FRAC_CFG_DATA_MASK -#define CRF_APB_DPLL_FRAC_CFG_DATA_DEFVAL 0x00000000 -#define CRF_APB_DPLL_FRAC_CFG_DATA_SHIFT 0 -#define CRF_APB_DPLL_FRAC_CFG_DATA_MASK 0x0000FFFFU - -/*PLL loop filter resistor control*/ +/* +* PLL loop filter resistor control +*/ #undef CRF_APB_VPLL_CFG_RES_DEFVAL #undef CRF_APB_VPLL_CFG_RES_SHIFT #undef CRF_APB_VPLL_CFG_RES_MASK -#define CRF_APB_VPLL_CFG_RES_DEFVAL 0x00000000 -#define CRF_APB_VPLL_CFG_RES_SHIFT 0 -#define CRF_APB_VPLL_CFG_RES_MASK 0x0000000FU +#define CRF_APB_VPLL_CFG_RES_DEFVAL 0x00000000 +#define CRF_APB_VPLL_CFG_RES_SHIFT 0 +#define CRF_APB_VPLL_CFG_RES_MASK 0x0000000FU -/*PLL charge pump control*/ +/* +* PLL charge pump control +*/ #undef CRF_APB_VPLL_CFG_CP_DEFVAL #undef CRF_APB_VPLL_CFG_CP_SHIFT #undef CRF_APB_VPLL_CFG_CP_MASK -#define CRF_APB_VPLL_CFG_CP_DEFVAL 0x00000000 -#define CRF_APB_VPLL_CFG_CP_SHIFT 5 -#define CRF_APB_VPLL_CFG_CP_MASK 0x000001E0U +#define CRF_APB_VPLL_CFG_CP_DEFVAL 0x00000000 +#define CRF_APB_VPLL_CFG_CP_SHIFT 5 +#define CRF_APB_VPLL_CFG_CP_MASK 0x000001E0U -/*PLL loop filter high frequency capacitor control*/ +/* +* PLL loop filter high frequency capacitor control +*/ #undef CRF_APB_VPLL_CFG_LFHF_DEFVAL #undef CRF_APB_VPLL_CFG_LFHF_SHIFT #undef CRF_APB_VPLL_CFG_LFHF_MASK -#define CRF_APB_VPLL_CFG_LFHF_DEFVAL 0x00000000 -#define CRF_APB_VPLL_CFG_LFHF_SHIFT 10 -#define CRF_APB_VPLL_CFG_LFHF_MASK 0x00000C00U +#define CRF_APB_VPLL_CFG_LFHF_DEFVAL 0x00000000 +#define CRF_APB_VPLL_CFG_LFHF_SHIFT 10 +#define CRF_APB_VPLL_CFG_LFHF_MASK 0x00000C00U -/*Lock circuit counter setting*/ +/* +* Lock circuit counter setting +*/ #undef CRF_APB_VPLL_CFG_LOCK_CNT_DEFVAL #undef CRF_APB_VPLL_CFG_LOCK_CNT_SHIFT #undef CRF_APB_VPLL_CFG_LOCK_CNT_MASK -#define CRF_APB_VPLL_CFG_LOCK_CNT_DEFVAL 0x00000000 -#define CRF_APB_VPLL_CFG_LOCK_CNT_SHIFT 13 -#define CRF_APB_VPLL_CFG_LOCK_CNT_MASK 0x007FE000U +#define CRF_APB_VPLL_CFG_LOCK_CNT_DEFVAL 0x00000000 +#define CRF_APB_VPLL_CFG_LOCK_CNT_SHIFT 13 +#define CRF_APB_VPLL_CFG_LOCK_CNT_MASK 0x007FE000U -/*Lock circuit configuration settings for lock windowsize*/ +/* +* Lock circuit configuration settings for lock windowsize +*/ #undef CRF_APB_VPLL_CFG_LOCK_DLY_DEFVAL #undef CRF_APB_VPLL_CFG_LOCK_DLY_SHIFT #undef CRF_APB_VPLL_CFG_LOCK_DLY_MASK -#define CRF_APB_VPLL_CFG_LOCK_DLY_DEFVAL 0x00000000 -#define CRF_APB_VPLL_CFG_LOCK_DLY_SHIFT 25 -#define CRF_APB_VPLL_CFG_LOCK_DLY_MASK 0xFE000000U +#define CRF_APB_VPLL_CFG_LOCK_DLY_DEFVAL 0x00000000 +#define CRF_APB_VPLL_CFG_LOCK_DLY_SHIFT 25 +#define CRF_APB_VPLL_CFG_LOCK_DLY_MASK 0xFE000000U -/*Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_ - ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source*/ +/* +* Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i + * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour + * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source +*/ #undef CRF_APB_VPLL_CTRL_PRE_SRC_DEFVAL #undef CRF_APB_VPLL_CTRL_PRE_SRC_SHIFT #undef CRF_APB_VPLL_CTRL_PRE_SRC_MASK -#define CRF_APB_VPLL_CTRL_PRE_SRC_DEFVAL 0x00012809 -#define CRF_APB_VPLL_CTRL_PRE_SRC_SHIFT 20 -#define CRF_APB_VPLL_CTRL_PRE_SRC_MASK 0x00700000U +#define CRF_APB_VPLL_CTRL_PRE_SRC_DEFVAL 0x00012809 +#define CRF_APB_VPLL_CTRL_PRE_SRC_SHIFT 20 +#define CRF_APB_VPLL_CTRL_PRE_SRC_MASK 0x00700000U -/*The integer portion of the feedback divider to the PLL*/ +/* +* The integer portion of the feedback divider to the PLL +*/ #undef CRF_APB_VPLL_CTRL_FBDIV_DEFVAL #undef CRF_APB_VPLL_CTRL_FBDIV_SHIFT #undef CRF_APB_VPLL_CTRL_FBDIV_MASK -#define CRF_APB_VPLL_CTRL_FBDIV_DEFVAL 0x00012809 -#define CRF_APB_VPLL_CTRL_FBDIV_SHIFT 8 -#define CRF_APB_VPLL_CTRL_FBDIV_MASK 0x00007F00U +#define CRF_APB_VPLL_CTRL_FBDIV_DEFVAL 0x00012809 +#define CRF_APB_VPLL_CTRL_FBDIV_SHIFT 8 +#define CRF_APB_VPLL_CTRL_FBDIV_MASK 0x00007F00U -/*This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency*/ +/* +* This turns on the divide by 2 that is inside of the PLL. This does not c + * hange the VCO frequency, just the output frequency +*/ #undef CRF_APB_VPLL_CTRL_DIV2_DEFVAL #undef CRF_APB_VPLL_CTRL_DIV2_SHIFT #undef CRF_APB_VPLL_CTRL_DIV2_MASK -#define CRF_APB_VPLL_CTRL_DIV2_DEFVAL 0x00012809 -#define CRF_APB_VPLL_CTRL_DIV2_SHIFT 16 -#define CRF_APB_VPLL_CTRL_DIV2_MASK 0x00010000U +#define CRF_APB_VPLL_CTRL_DIV2_DEFVAL 0x00012809 +#define CRF_APB_VPLL_CTRL_DIV2_SHIFT 16 +#define CRF_APB_VPLL_CTRL_DIV2_MASK 0x00010000U -/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/ +/* +* Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) +*/ #undef CRF_APB_VPLL_CTRL_BYPASS_DEFVAL #undef CRF_APB_VPLL_CTRL_BYPASS_SHIFT #undef CRF_APB_VPLL_CTRL_BYPASS_MASK -#define CRF_APB_VPLL_CTRL_BYPASS_DEFVAL 0x00012809 -#define CRF_APB_VPLL_CTRL_BYPASS_SHIFT 3 -#define CRF_APB_VPLL_CTRL_BYPASS_MASK 0x00000008U +#define CRF_APB_VPLL_CTRL_BYPASS_DEFVAL 0x00012809 +#define CRF_APB_VPLL_CTRL_BYPASS_SHIFT 3 +#define CRF_APB_VPLL_CTRL_BYPASS_MASK 0x00000008U -/*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/ +/* +* Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. +*/ #undef CRF_APB_VPLL_CTRL_RESET_DEFVAL #undef CRF_APB_VPLL_CTRL_RESET_SHIFT #undef CRF_APB_VPLL_CTRL_RESET_MASK -#define CRF_APB_VPLL_CTRL_RESET_DEFVAL 0x00012809 -#define CRF_APB_VPLL_CTRL_RESET_SHIFT 0 -#define CRF_APB_VPLL_CTRL_RESET_MASK 0x00000001U +#define CRF_APB_VPLL_CTRL_RESET_DEFVAL 0x00012809 +#define CRF_APB_VPLL_CTRL_RESET_SHIFT 0 +#define CRF_APB_VPLL_CTRL_RESET_MASK 0x00000001U -/*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/ +/* +* Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. +*/ #undef CRF_APB_VPLL_CTRL_RESET_DEFVAL #undef CRF_APB_VPLL_CTRL_RESET_SHIFT #undef CRF_APB_VPLL_CTRL_RESET_MASK -#define CRF_APB_VPLL_CTRL_RESET_DEFVAL 0x00012809 -#define CRF_APB_VPLL_CTRL_RESET_SHIFT 0 -#define CRF_APB_VPLL_CTRL_RESET_MASK 0x00000001U +#define CRF_APB_VPLL_CTRL_RESET_DEFVAL 0x00012809 +#define CRF_APB_VPLL_CTRL_RESET_SHIFT 0 +#define CRF_APB_VPLL_CTRL_RESET_MASK 0x00000001U -/*VPLL is locked*/ +/* +* VPLL is locked +*/ #undef CRF_APB_PLL_STATUS_VPLL_LOCK_DEFVAL #undef CRF_APB_PLL_STATUS_VPLL_LOCK_SHIFT #undef CRF_APB_PLL_STATUS_VPLL_LOCK_MASK -#define CRF_APB_PLL_STATUS_VPLL_LOCK_DEFVAL 0x00000038 -#define CRF_APB_PLL_STATUS_VPLL_LOCK_SHIFT 2 -#define CRF_APB_PLL_STATUS_VPLL_LOCK_MASK 0x00000004U +#define CRF_APB_PLL_STATUS_VPLL_LOCK_DEFVAL 0x00000038 +#define CRF_APB_PLL_STATUS_VPLL_LOCK_SHIFT 2 +#define CRF_APB_PLL_STATUS_VPLL_LOCK_MASK 0x00000004U #define CRF_APB_PLL_STATUS_OFFSET 0XFD1A0044 -/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/ +/* +* Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) +*/ #undef CRF_APB_VPLL_CTRL_BYPASS_DEFVAL #undef CRF_APB_VPLL_CTRL_BYPASS_SHIFT #undef CRF_APB_VPLL_CTRL_BYPASS_MASK -#define CRF_APB_VPLL_CTRL_BYPASS_DEFVAL 0x00012809 -#define CRF_APB_VPLL_CTRL_BYPASS_SHIFT 3 -#define CRF_APB_VPLL_CTRL_BYPASS_MASK 0x00000008U +#define CRF_APB_VPLL_CTRL_BYPASS_DEFVAL 0x00012809 +#define CRF_APB_VPLL_CTRL_BYPASS_SHIFT 3 +#define CRF_APB_VPLL_CTRL_BYPASS_MASK 0x00000008U -/*Divisor value for this clock.*/ +/* +* Divisor value for this clock. +*/ #undef CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL #undef CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_SHIFT #undef CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_MASK -#define CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL 0x00000400 -#define CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_SHIFT 8 -#define CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_MASK 0x00003F00U - -/*Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona - mode and uses DATA of this register for the fractional portion of the feedback divider.*/ -#undef CRF_APB_VPLL_FRAC_CFG_ENABLED_DEFVAL -#undef CRF_APB_VPLL_FRAC_CFG_ENABLED_SHIFT -#undef CRF_APB_VPLL_FRAC_CFG_ENABLED_MASK -#define CRF_APB_VPLL_FRAC_CFG_ENABLED_DEFVAL 0x00000000 -#define CRF_APB_VPLL_FRAC_CFG_ENABLED_SHIFT 31 -#define CRF_APB_VPLL_FRAC_CFG_ENABLED_MASK 0x80000000U - -/*Fractional value for the Feedback value.*/ -#undef CRF_APB_VPLL_FRAC_CFG_DATA_DEFVAL -#undef CRF_APB_VPLL_FRAC_CFG_DATA_SHIFT -#undef CRF_APB_VPLL_FRAC_CFG_DATA_MASK -#define CRF_APB_VPLL_FRAC_CFG_DATA_DEFVAL 0x00000000 -#define CRF_APB_VPLL_FRAC_CFG_DATA_SHIFT 0 -#define CRF_APB_VPLL_FRAC_CFG_DATA_MASK 0x0000FFFFU +#define CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL 0x00000400 +#define CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_MASK 0x00003F00U #undef CRL_APB_GEM3_REF_CTRL_OFFSET #define CRL_APB_GEM3_REF_CTRL_OFFSET 0XFF5E005C +#undef CRL_APB_GEM_TSU_REF_CTRL_OFFSET +#define CRL_APB_GEM_TSU_REF_CTRL_OFFSET 0XFF5E0100 #undef CRL_APB_USB0_BUS_REF_CTRL_OFFSET #define CRL_APB_USB0_BUS_REF_CTRL_OFFSET 0XFF5E0060 #undef CRL_APB_USB3_DUAL_REF_CTRL_OFFSET @@ -810,12 +897,6 @@ #define CRL_APB_ADMA_REF_CTRL_OFFSET 0XFF5E00B8 #undef CRL_APB_PL0_REF_CTRL_OFFSET #define CRL_APB_PL0_REF_CTRL_OFFSET 0XFF5E00C0 -#undef CRL_APB_PL1_REF_CTRL_OFFSET -#define CRL_APB_PL1_REF_CTRL_OFFSET 0XFF5E00C4 -#undef CRL_APB_PL2_REF_CTRL_OFFSET -#define CRL_APB_PL2_REF_CTRL_OFFSET 0XFF5E00C8 -#undef CRL_APB_PL3_REF_CTRL_OFFSET -#define CRL_APB_PL3_REF_CTRL_OFFSET 0XFF5E00CC #undef CRL_APB_AMS_REF_CTRL_OFFSET #define CRL_APB_AMS_REF_CTRL_OFFSET 0XFF5E0108 #undef CRL_APB_DLL_REF_CTRL_OFFSET @@ -834,8 +915,6 @@ #define CRF_APB_DP_STC_REF_CTRL_OFFSET 0XFD1A007C #undef CRF_APB_ACPU_CTRL_OFFSET #define CRF_APB_ACPU_CTRL_OFFSET 0XFD1A0060 -#undef CRF_APB_DBG_TRACE_CTRL_OFFSET -#define CRF_APB_DBG_TRACE_CTRL_OFFSET 0XFD1A0064 #undef CRF_APB_DBG_FPD_CTRL_OFFSET #define CRF_APB_DBG_FPD_CTRL_OFFSET 0XFD1A0068 #undef CRF_APB_DDR_CTRL_OFFSET @@ -861,1195 +940,1418 @@ #undef LPD_SLCR_CSUPMU_WDT_CLK_SEL_OFFSET #define LPD_SLCR_CSUPMU_WDT_CLK_SEL_OFFSET 0XFF410050 -/*Clock active for the RX channel*/ +/* +* Clock active for the RX channel +*/ #undef CRL_APB_GEM3_REF_CTRL_RX_CLKACT_DEFVAL #undef CRL_APB_GEM3_REF_CTRL_RX_CLKACT_SHIFT #undef CRL_APB_GEM3_REF_CTRL_RX_CLKACT_MASK -#define CRL_APB_GEM3_REF_CTRL_RX_CLKACT_DEFVAL 0x00002500 -#define CRL_APB_GEM3_REF_CTRL_RX_CLKACT_SHIFT 26 -#define CRL_APB_GEM3_REF_CTRL_RX_CLKACT_MASK 0x04000000U +#define CRL_APB_GEM3_REF_CTRL_RX_CLKACT_DEFVAL 0x00002500 +#define CRL_APB_GEM3_REF_CTRL_RX_CLKACT_SHIFT 26 +#define CRL_APB_GEM3_REF_CTRL_RX_CLKACT_MASK 0x04000000U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRL_APB_GEM3_REF_CTRL_CLKACT_DEFVAL #undef CRL_APB_GEM3_REF_CTRL_CLKACT_SHIFT #undef CRL_APB_GEM3_REF_CTRL_CLKACT_MASK -#define CRL_APB_GEM3_REF_CTRL_CLKACT_DEFVAL 0x00002500 -#define CRL_APB_GEM3_REF_CTRL_CLKACT_SHIFT 25 -#define CRL_APB_GEM3_REF_CTRL_CLKACT_MASK 0x02000000U +#define CRL_APB_GEM3_REF_CTRL_CLKACT_DEFVAL 0x00002500 +#define CRL_APB_GEM3_REF_CTRL_CLKACT_SHIFT 25 +#define CRL_APB_GEM3_REF_CTRL_CLKACT_MASK 0x02000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_GEM3_REF_CTRL_DIVISOR1_DEFVAL #undef CRL_APB_GEM3_REF_CTRL_DIVISOR1_SHIFT #undef CRL_APB_GEM3_REF_CTRL_DIVISOR1_MASK -#define CRL_APB_GEM3_REF_CTRL_DIVISOR1_DEFVAL 0x00002500 -#define CRL_APB_GEM3_REF_CTRL_DIVISOR1_SHIFT 16 -#define CRL_APB_GEM3_REF_CTRL_DIVISOR1_MASK 0x003F0000U +#define CRL_APB_GEM3_REF_CTRL_DIVISOR1_DEFVAL 0x00002500 +#define CRL_APB_GEM3_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_GEM3_REF_CTRL_DIVISOR1_MASK 0x003F0000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_GEM3_REF_CTRL_DIVISOR0_DEFVAL #undef CRL_APB_GEM3_REF_CTRL_DIVISOR0_SHIFT #undef CRL_APB_GEM3_REF_CTRL_DIVISOR0_MASK -#define CRL_APB_GEM3_REF_CTRL_DIVISOR0_DEFVAL 0x00002500 -#define CRL_APB_GEM3_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_GEM3_REF_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRL_APB_GEM3_REF_CTRL_DIVISOR0_DEFVAL 0x00002500 +#define CRL_APB_GEM3_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_GEM3_REF_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRL_APB_GEM3_REF_CTRL_SRCSEL_DEFVAL #undef CRL_APB_GEM3_REF_CTRL_SRCSEL_SHIFT #undef CRL_APB_GEM3_REF_CTRL_SRCSEL_MASK -#define CRL_APB_GEM3_REF_CTRL_SRCSEL_DEFVAL 0x00002500 -#define CRL_APB_GEM3_REF_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_GEM3_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRL_APB_GEM3_REF_CTRL_SRCSEL_DEFVAL 0x00002500 +#define CRL_APB_GEM3_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_GEM3_REF_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* 6 bit divider +*/ +#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_DEFVAL +#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_SHIFT +#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_MASK +#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_DEFVAL 0x00051000 +#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_MASK 0x00003F00U + +/* +* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ +#undef CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_DEFVAL +#undef CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_SHIFT +#undef CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_MASK +#define CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_DEFVAL 0x00051000 +#define CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_MASK 0x00000007U + +/* +* 6 bit divider +*/ +#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_DEFVAL +#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_SHIFT +#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_MASK +#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_DEFVAL 0x00051000 +#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_MASK 0x003F0000U + +/* +* Clock active signal. Switch to 0 to disable the clock +*/ +#undef CRL_APB_GEM_TSU_REF_CTRL_CLKACT_DEFVAL +#undef CRL_APB_GEM_TSU_REF_CTRL_CLKACT_SHIFT +#undef CRL_APB_GEM_TSU_REF_CTRL_CLKACT_MASK +#define CRL_APB_GEM_TSU_REF_CTRL_CLKACT_DEFVAL 0x00051000 +#define CRL_APB_GEM_TSU_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_GEM_TSU_REF_CTRL_CLKACT_MASK 0x01000000U + +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRL_APB_USB0_BUS_REF_CTRL_CLKACT_DEFVAL #undef CRL_APB_USB0_BUS_REF_CTRL_CLKACT_SHIFT #undef CRL_APB_USB0_BUS_REF_CTRL_CLKACT_MASK -#define CRL_APB_USB0_BUS_REF_CTRL_CLKACT_DEFVAL 0x00052000 -#define CRL_APB_USB0_BUS_REF_CTRL_CLKACT_SHIFT 25 -#define CRL_APB_USB0_BUS_REF_CTRL_CLKACT_MASK 0x02000000U +#define CRL_APB_USB0_BUS_REF_CTRL_CLKACT_DEFVAL 0x00052000 +#define CRL_APB_USB0_BUS_REF_CTRL_CLKACT_SHIFT 25 +#define CRL_APB_USB0_BUS_REF_CTRL_CLKACT_MASK 0x02000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_DEFVAL #undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_SHIFT #undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_MASK -#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_DEFVAL 0x00052000 -#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_SHIFT 16 -#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_MASK 0x003F0000U +#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_DEFVAL 0x00052000 +#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_MASK 0x003F0000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_DEFVAL #undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_SHIFT #undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_MASK -#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_DEFVAL 0x00052000 -#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_DEFVAL 0x00052000 +#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_DEFVAL #undef CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_SHIFT #undef CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_MASK -#define CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_DEFVAL 0x00052000 -#define CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_DEFVAL 0x00052000 +#define CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_DEFVAL #undef CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_SHIFT #undef CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_MASK -#define CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_DEFVAL 0x00052000 -#define CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_SHIFT 25 -#define CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_MASK 0x02000000U +#define CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_DEFVAL 0x00052000 +#define CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_SHIFT 25 +#define CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_MASK 0x02000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_DEFVAL #undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_SHIFT #undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_MASK -#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_DEFVAL 0x00052000 -#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_SHIFT 16 -#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_MASK 0x003F0000U +#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_DEFVAL 0x00052000 +#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_MASK 0x003F0000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_DEFVAL #undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_SHIFT #undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_MASK -#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_DEFVAL 0x00052000 -#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_DEFVAL 0x00052000 +#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = IOPLL; 010 = RPLL; 011 = DPLL. (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = IOPLL; 010 = RPLL; 011 = DPLL. (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_DEFVAL #undef CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_SHIFT #undef CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_MASK -#define CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_DEFVAL 0x00052000 -#define CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_DEFVAL 0x00052000 +#define CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRL_APB_QSPI_REF_CTRL_CLKACT_DEFVAL #undef CRL_APB_QSPI_REF_CTRL_CLKACT_SHIFT #undef CRL_APB_QSPI_REF_CTRL_CLKACT_MASK -#define CRL_APB_QSPI_REF_CTRL_CLKACT_DEFVAL 0x01000800 -#define CRL_APB_QSPI_REF_CTRL_CLKACT_SHIFT 24 -#define CRL_APB_QSPI_REF_CTRL_CLKACT_MASK 0x01000000U +#define CRL_APB_QSPI_REF_CTRL_CLKACT_DEFVAL 0x01000800 +#define CRL_APB_QSPI_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_QSPI_REF_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_QSPI_REF_CTRL_DIVISOR1_DEFVAL #undef CRL_APB_QSPI_REF_CTRL_DIVISOR1_SHIFT #undef CRL_APB_QSPI_REF_CTRL_DIVISOR1_MASK -#define CRL_APB_QSPI_REF_CTRL_DIVISOR1_DEFVAL 0x01000800 -#define CRL_APB_QSPI_REF_CTRL_DIVISOR1_SHIFT 16 -#define CRL_APB_QSPI_REF_CTRL_DIVISOR1_MASK 0x003F0000U +#define CRL_APB_QSPI_REF_CTRL_DIVISOR1_DEFVAL 0x01000800 +#define CRL_APB_QSPI_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_QSPI_REF_CTRL_DIVISOR1_MASK 0x003F0000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_QSPI_REF_CTRL_DIVISOR0_DEFVAL #undef CRL_APB_QSPI_REF_CTRL_DIVISOR0_SHIFT #undef CRL_APB_QSPI_REF_CTRL_DIVISOR0_MASK -#define CRL_APB_QSPI_REF_CTRL_DIVISOR0_DEFVAL 0x01000800 -#define CRL_APB_QSPI_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_QSPI_REF_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRL_APB_QSPI_REF_CTRL_DIVISOR0_DEFVAL 0x01000800 +#define CRL_APB_QSPI_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_QSPI_REF_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRL_APB_QSPI_REF_CTRL_SRCSEL_DEFVAL #undef CRL_APB_QSPI_REF_CTRL_SRCSEL_SHIFT #undef CRL_APB_QSPI_REF_CTRL_SRCSEL_MASK -#define CRL_APB_QSPI_REF_CTRL_SRCSEL_DEFVAL 0x01000800 -#define CRL_APB_QSPI_REF_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_QSPI_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRL_APB_QSPI_REF_CTRL_SRCSEL_DEFVAL 0x01000800 +#define CRL_APB_QSPI_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_QSPI_REF_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRL_APB_SDIO1_REF_CTRL_CLKACT_DEFVAL #undef CRL_APB_SDIO1_REF_CTRL_CLKACT_SHIFT #undef CRL_APB_SDIO1_REF_CTRL_CLKACT_MASK -#define CRL_APB_SDIO1_REF_CTRL_CLKACT_DEFVAL 0x01000F00 -#define CRL_APB_SDIO1_REF_CTRL_CLKACT_SHIFT 24 -#define CRL_APB_SDIO1_REF_CTRL_CLKACT_MASK 0x01000000U +#define CRL_APB_SDIO1_REF_CTRL_CLKACT_DEFVAL 0x01000F00 +#define CRL_APB_SDIO1_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_SDIO1_REF_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_SDIO1_REF_CTRL_DIVISOR1_DEFVAL #undef CRL_APB_SDIO1_REF_CTRL_DIVISOR1_SHIFT #undef CRL_APB_SDIO1_REF_CTRL_DIVISOR1_MASK -#define CRL_APB_SDIO1_REF_CTRL_DIVISOR1_DEFVAL 0x01000F00 -#define CRL_APB_SDIO1_REF_CTRL_DIVISOR1_SHIFT 16 -#define CRL_APB_SDIO1_REF_CTRL_DIVISOR1_MASK 0x003F0000U +#define CRL_APB_SDIO1_REF_CTRL_DIVISOR1_DEFVAL 0x01000F00 +#define CRL_APB_SDIO1_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_SDIO1_REF_CTRL_DIVISOR1_MASK 0x003F0000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_SDIO1_REF_CTRL_DIVISOR0_DEFVAL #undef CRL_APB_SDIO1_REF_CTRL_DIVISOR0_SHIFT #undef CRL_APB_SDIO1_REF_CTRL_DIVISOR0_MASK -#define CRL_APB_SDIO1_REF_CTRL_DIVISOR0_DEFVAL 0x01000F00 -#define CRL_APB_SDIO1_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_SDIO1_REF_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRL_APB_SDIO1_REF_CTRL_DIVISOR0_DEFVAL 0x01000F00 +#define CRL_APB_SDIO1_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_SDIO1_REF_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = IOPLL; 010 = RPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = IOPLL; 010 = RPLL; 011 = VPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRL_APB_SDIO1_REF_CTRL_SRCSEL_DEFVAL #undef CRL_APB_SDIO1_REF_CTRL_SRCSEL_SHIFT #undef CRL_APB_SDIO1_REF_CTRL_SRCSEL_MASK -#define CRL_APB_SDIO1_REF_CTRL_SRCSEL_DEFVAL 0x01000F00 -#define CRL_APB_SDIO1_REF_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_SDIO1_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRL_APB_SDIO1_REF_CTRL_SRCSEL_DEFVAL 0x01000F00 +#define CRL_APB_SDIO1_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_SDIO1_REF_CTRL_SRCSEL_MASK 0x00000007U -/*MIO pad selection for sdio1_rx_clk (feedback clock from the PAD) 0: MIO [51] 1: MIO [76]*/ +/* +* MIO pad selection for sdio1_rx_clk (feedback clock from the PAD) 0: MIO + * [51] 1: MIO [76] +*/ #undef IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_DEFVAL #undef IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_SHIFT #undef IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_MASK -#define IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_SHIFT 17 -#define IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_MASK 0x00020000U +#define IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_SHIFT 17 +#define IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_MASK 0x00020000U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRL_APB_UART0_REF_CTRL_CLKACT_DEFVAL #undef CRL_APB_UART0_REF_CTRL_CLKACT_SHIFT #undef CRL_APB_UART0_REF_CTRL_CLKACT_MASK -#define CRL_APB_UART0_REF_CTRL_CLKACT_DEFVAL 0x01001800 -#define CRL_APB_UART0_REF_CTRL_CLKACT_SHIFT 24 -#define CRL_APB_UART0_REF_CTRL_CLKACT_MASK 0x01000000U +#define CRL_APB_UART0_REF_CTRL_CLKACT_DEFVAL 0x01001800 +#define CRL_APB_UART0_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_UART0_REF_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_UART0_REF_CTRL_DIVISOR1_DEFVAL #undef CRL_APB_UART0_REF_CTRL_DIVISOR1_SHIFT #undef CRL_APB_UART0_REF_CTRL_DIVISOR1_MASK -#define CRL_APB_UART0_REF_CTRL_DIVISOR1_DEFVAL 0x01001800 -#define CRL_APB_UART0_REF_CTRL_DIVISOR1_SHIFT 16 -#define CRL_APB_UART0_REF_CTRL_DIVISOR1_MASK 0x003F0000U +#define CRL_APB_UART0_REF_CTRL_DIVISOR1_DEFVAL 0x01001800 +#define CRL_APB_UART0_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_UART0_REF_CTRL_DIVISOR1_MASK 0x003F0000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_UART0_REF_CTRL_DIVISOR0_DEFVAL #undef CRL_APB_UART0_REF_CTRL_DIVISOR0_SHIFT #undef CRL_APB_UART0_REF_CTRL_DIVISOR0_MASK -#define CRL_APB_UART0_REF_CTRL_DIVISOR0_DEFVAL 0x01001800 -#define CRL_APB_UART0_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_UART0_REF_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRL_APB_UART0_REF_CTRL_DIVISOR0_DEFVAL 0x01001800 +#define CRL_APB_UART0_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_UART0_REF_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRL_APB_UART0_REF_CTRL_SRCSEL_DEFVAL #undef CRL_APB_UART0_REF_CTRL_SRCSEL_SHIFT #undef CRL_APB_UART0_REF_CTRL_SRCSEL_MASK -#define CRL_APB_UART0_REF_CTRL_SRCSEL_DEFVAL 0x01001800 -#define CRL_APB_UART0_REF_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_UART0_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRL_APB_UART0_REF_CTRL_SRCSEL_DEFVAL 0x01001800 +#define CRL_APB_UART0_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_UART0_REF_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRL_APB_UART1_REF_CTRL_CLKACT_DEFVAL #undef CRL_APB_UART1_REF_CTRL_CLKACT_SHIFT #undef CRL_APB_UART1_REF_CTRL_CLKACT_MASK -#define CRL_APB_UART1_REF_CTRL_CLKACT_DEFVAL 0x01001800 -#define CRL_APB_UART1_REF_CTRL_CLKACT_SHIFT 24 -#define CRL_APB_UART1_REF_CTRL_CLKACT_MASK 0x01000000U +#define CRL_APB_UART1_REF_CTRL_CLKACT_DEFVAL 0x01001800 +#define CRL_APB_UART1_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_UART1_REF_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_UART1_REF_CTRL_DIVISOR1_DEFVAL #undef CRL_APB_UART1_REF_CTRL_DIVISOR1_SHIFT #undef CRL_APB_UART1_REF_CTRL_DIVISOR1_MASK -#define CRL_APB_UART1_REF_CTRL_DIVISOR1_DEFVAL 0x01001800 -#define CRL_APB_UART1_REF_CTRL_DIVISOR1_SHIFT 16 -#define CRL_APB_UART1_REF_CTRL_DIVISOR1_MASK 0x003F0000U +#define CRL_APB_UART1_REF_CTRL_DIVISOR1_DEFVAL 0x01001800 +#define CRL_APB_UART1_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_UART1_REF_CTRL_DIVISOR1_MASK 0x003F0000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_UART1_REF_CTRL_DIVISOR0_DEFVAL #undef CRL_APB_UART1_REF_CTRL_DIVISOR0_SHIFT #undef CRL_APB_UART1_REF_CTRL_DIVISOR0_MASK -#define CRL_APB_UART1_REF_CTRL_DIVISOR0_DEFVAL 0x01001800 -#define CRL_APB_UART1_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_UART1_REF_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRL_APB_UART1_REF_CTRL_DIVISOR0_DEFVAL 0x01001800 +#define CRL_APB_UART1_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_UART1_REF_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRL_APB_UART1_REF_CTRL_SRCSEL_DEFVAL #undef CRL_APB_UART1_REF_CTRL_SRCSEL_SHIFT #undef CRL_APB_UART1_REF_CTRL_SRCSEL_MASK -#define CRL_APB_UART1_REF_CTRL_SRCSEL_DEFVAL 0x01001800 -#define CRL_APB_UART1_REF_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_UART1_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRL_APB_UART1_REF_CTRL_SRCSEL_DEFVAL 0x01001800 +#define CRL_APB_UART1_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_UART1_REF_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRL_APB_I2C0_REF_CTRL_CLKACT_DEFVAL #undef CRL_APB_I2C0_REF_CTRL_CLKACT_SHIFT #undef CRL_APB_I2C0_REF_CTRL_CLKACT_MASK -#define CRL_APB_I2C0_REF_CTRL_CLKACT_DEFVAL 0x01000500 -#define CRL_APB_I2C0_REF_CTRL_CLKACT_SHIFT 24 -#define CRL_APB_I2C0_REF_CTRL_CLKACT_MASK 0x01000000U +#define CRL_APB_I2C0_REF_CTRL_CLKACT_DEFVAL 0x01000500 +#define CRL_APB_I2C0_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_I2C0_REF_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_I2C0_REF_CTRL_DIVISOR1_DEFVAL #undef CRL_APB_I2C0_REF_CTRL_DIVISOR1_SHIFT #undef CRL_APB_I2C0_REF_CTRL_DIVISOR1_MASK -#define CRL_APB_I2C0_REF_CTRL_DIVISOR1_DEFVAL 0x01000500 -#define CRL_APB_I2C0_REF_CTRL_DIVISOR1_SHIFT 16 -#define CRL_APB_I2C0_REF_CTRL_DIVISOR1_MASK 0x003F0000U +#define CRL_APB_I2C0_REF_CTRL_DIVISOR1_DEFVAL 0x01000500 +#define CRL_APB_I2C0_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_I2C0_REF_CTRL_DIVISOR1_MASK 0x003F0000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_I2C0_REF_CTRL_DIVISOR0_DEFVAL #undef CRL_APB_I2C0_REF_CTRL_DIVISOR0_SHIFT #undef CRL_APB_I2C0_REF_CTRL_DIVISOR0_MASK -#define CRL_APB_I2C0_REF_CTRL_DIVISOR0_DEFVAL 0x01000500 -#define CRL_APB_I2C0_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_I2C0_REF_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRL_APB_I2C0_REF_CTRL_DIVISOR0_DEFVAL 0x01000500 +#define CRL_APB_I2C0_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_I2C0_REF_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRL_APB_I2C0_REF_CTRL_SRCSEL_DEFVAL #undef CRL_APB_I2C0_REF_CTRL_SRCSEL_SHIFT #undef CRL_APB_I2C0_REF_CTRL_SRCSEL_MASK -#define CRL_APB_I2C0_REF_CTRL_SRCSEL_DEFVAL 0x01000500 -#define CRL_APB_I2C0_REF_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_I2C0_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRL_APB_I2C0_REF_CTRL_SRCSEL_DEFVAL 0x01000500 +#define CRL_APB_I2C0_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_I2C0_REF_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRL_APB_I2C1_REF_CTRL_CLKACT_DEFVAL #undef CRL_APB_I2C1_REF_CTRL_CLKACT_SHIFT #undef CRL_APB_I2C1_REF_CTRL_CLKACT_MASK -#define CRL_APB_I2C1_REF_CTRL_CLKACT_DEFVAL 0x01000500 -#define CRL_APB_I2C1_REF_CTRL_CLKACT_SHIFT 24 -#define CRL_APB_I2C1_REF_CTRL_CLKACT_MASK 0x01000000U +#define CRL_APB_I2C1_REF_CTRL_CLKACT_DEFVAL 0x01000500 +#define CRL_APB_I2C1_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_I2C1_REF_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_I2C1_REF_CTRL_DIVISOR1_DEFVAL #undef CRL_APB_I2C1_REF_CTRL_DIVISOR1_SHIFT #undef CRL_APB_I2C1_REF_CTRL_DIVISOR1_MASK -#define CRL_APB_I2C1_REF_CTRL_DIVISOR1_DEFVAL 0x01000500 -#define CRL_APB_I2C1_REF_CTRL_DIVISOR1_SHIFT 16 -#define CRL_APB_I2C1_REF_CTRL_DIVISOR1_MASK 0x003F0000U +#define CRL_APB_I2C1_REF_CTRL_DIVISOR1_DEFVAL 0x01000500 +#define CRL_APB_I2C1_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_I2C1_REF_CTRL_DIVISOR1_MASK 0x003F0000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_I2C1_REF_CTRL_DIVISOR0_DEFVAL #undef CRL_APB_I2C1_REF_CTRL_DIVISOR0_SHIFT #undef CRL_APB_I2C1_REF_CTRL_DIVISOR0_MASK -#define CRL_APB_I2C1_REF_CTRL_DIVISOR0_DEFVAL 0x01000500 -#define CRL_APB_I2C1_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_I2C1_REF_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRL_APB_I2C1_REF_CTRL_DIVISOR0_DEFVAL 0x01000500 +#define CRL_APB_I2C1_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_I2C1_REF_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRL_APB_I2C1_REF_CTRL_SRCSEL_DEFVAL #undef CRL_APB_I2C1_REF_CTRL_SRCSEL_SHIFT #undef CRL_APB_I2C1_REF_CTRL_SRCSEL_MASK -#define CRL_APB_I2C1_REF_CTRL_SRCSEL_DEFVAL 0x01000500 -#define CRL_APB_I2C1_REF_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_I2C1_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRL_APB_I2C1_REF_CTRL_SRCSEL_DEFVAL 0x01000500 +#define CRL_APB_I2C1_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_I2C1_REF_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRL_APB_CAN1_REF_CTRL_CLKACT_DEFVAL #undef CRL_APB_CAN1_REF_CTRL_CLKACT_SHIFT #undef CRL_APB_CAN1_REF_CTRL_CLKACT_MASK -#define CRL_APB_CAN1_REF_CTRL_CLKACT_DEFVAL 0x01001800 -#define CRL_APB_CAN1_REF_CTRL_CLKACT_SHIFT 24 -#define CRL_APB_CAN1_REF_CTRL_CLKACT_MASK 0x01000000U +#define CRL_APB_CAN1_REF_CTRL_CLKACT_DEFVAL 0x01001800 +#define CRL_APB_CAN1_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_CAN1_REF_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_CAN1_REF_CTRL_DIVISOR1_DEFVAL #undef CRL_APB_CAN1_REF_CTRL_DIVISOR1_SHIFT #undef CRL_APB_CAN1_REF_CTRL_DIVISOR1_MASK -#define CRL_APB_CAN1_REF_CTRL_DIVISOR1_DEFVAL 0x01001800 -#define CRL_APB_CAN1_REF_CTRL_DIVISOR1_SHIFT 16 -#define CRL_APB_CAN1_REF_CTRL_DIVISOR1_MASK 0x003F0000U +#define CRL_APB_CAN1_REF_CTRL_DIVISOR1_DEFVAL 0x01001800 +#define CRL_APB_CAN1_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_CAN1_REF_CTRL_DIVISOR1_MASK 0x003F0000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_CAN1_REF_CTRL_DIVISOR0_DEFVAL #undef CRL_APB_CAN1_REF_CTRL_DIVISOR0_SHIFT #undef CRL_APB_CAN1_REF_CTRL_DIVISOR0_MASK -#define CRL_APB_CAN1_REF_CTRL_DIVISOR0_DEFVAL 0x01001800 -#define CRL_APB_CAN1_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_CAN1_REF_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRL_APB_CAN1_REF_CTRL_DIVISOR0_DEFVAL 0x01001800 +#define CRL_APB_CAN1_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_CAN1_REF_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRL_APB_CAN1_REF_CTRL_SRCSEL_DEFVAL #undef CRL_APB_CAN1_REF_CTRL_SRCSEL_SHIFT #undef CRL_APB_CAN1_REF_CTRL_SRCSEL_MASK -#define CRL_APB_CAN1_REF_CTRL_SRCSEL_DEFVAL 0x01001800 -#define CRL_APB_CAN1_REF_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_CAN1_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRL_APB_CAN1_REF_CTRL_SRCSEL_DEFVAL 0x01001800 +#define CRL_APB_CAN1_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_CAN1_REF_CTRL_SRCSEL_MASK 0x00000007U -/*Turing this off will shut down the OCM, some parts of the APM, and prevent transactions going from the FPD to the LPD and cou - d lead to system hang*/ +/* +* Turing this off will shut down the OCM, some parts of the APM, and preve + * nt transactions going from the FPD to the LPD and could lead to system h + * ang +*/ #undef CRL_APB_CPU_R5_CTRL_CLKACT_DEFVAL #undef CRL_APB_CPU_R5_CTRL_CLKACT_SHIFT #undef CRL_APB_CPU_R5_CTRL_CLKACT_MASK -#define CRL_APB_CPU_R5_CTRL_CLKACT_DEFVAL 0x03000600 -#define CRL_APB_CPU_R5_CTRL_CLKACT_SHIFT 24 -#define CRL_APB_CPU_R5_CTRL_CLKACT_MASK 0x01000000U +#define CRL_APB_CPU_R5_CTRL_CLKACT_DEFVAL 0x03000600 +#define CRL_APB_CPU_R5_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_CPU_R5_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_CPU_R5_CTRL_DIVISOR0_DEFVAL #undef CRL_APB_CPU_R5_CTRL_DIVISOR0_SHIFT #undef CRL_APB_CPU_R5_CTRL_DIVISOR0_MASK -#define CRL_APB_CPU_R5_CTRL_DIVISOR0_DEFVAL 0x03000600 -#define CRL_APB_CPU_R5_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_CPU_R5_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRL_APB_CPU_R5_CTRL_DIVISOR0_DEFVAL 0x03000600 +#define CRL_APB_CPU_R5_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_CPU_R5_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRL_APB_CPU_R5_CTRL_SRCSEL_DEFVAL #undef CRL_APB_CPU_R5_CTRL_SRCSEL_SHIFT #undef CRL_APB_CPU_R5_CTRL_SRCSEL_MASK -#define CRL_APB_CPU_R5_CTRL_SRCSEL_DEFVAL 0x03000600 -#define CRL_APB_CPU_R5_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_CPU_R5_CTRL_SRCSEL_MASK 0x00000007U +#define CRL_APB_CPU_R5_CTRL_SRCSEL_DEFVAL 0x03000600 +#define CRL_APB_CPU_R5_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_CPU_R5_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRL_APB_IOU_SWITCH_CTRL_CLKACT_DEFVAL #undef CRL_APB_IOU_SWITCH_CTRL_CLKACT_SHIFT #undef CRL_APB_IOU_SWITCH_CTRL_CLKACT_MASK -#define CRL_APB_IOU_SWITCH_CTRL_CLKACT_DEFVAL 0x00001500 -#define CRL_APB_IOU_SWITCH_CTRL_CLKACT_SHIFT 24 -#define CRL_APB_IOU_SWITCH_CTRL_CLKACT_MASK 0x01000000U +#define CRL_APB_IOU_SWITCH_CTRL_CLKACT_DEFVAL 0x00001500 +#define CRL_APB_IOU_SWITCH_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_IOU_SWITCH_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_DEFVAL #undef CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_SHIFT #undef CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_MASK -#define CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_DEFVAL 0x00001500 -#define CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_DEFVAL 0x00001500 +#define CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRL_APB_IOU_SWITCH_CTRL_SRCSEL_DEFVAL #undef CRL_APB_IOU_SWITCH_CTRL_SRCSEL_SHIFT #undef CRL_APB_IOU_SWITCH_CTRL_SRCSEL_MASK -#define CRL_APB_IOU_SWITCH_CTRL_SRCSEL_DEFVAL 0x00001500 -#define CRL_APB_IOU_SWITCH_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_IOU_SWITCH_CTRL_SRCSEL_MASK 0x00000007U +#define CRL_APB_IOU_SWITCH_CTRL_SRCSEL_DEFVAL 0x00001500 +#define CRL_APB_IOU_SWITCH_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_IOU_SWITCH_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRL_APB_PCAP_CTRL_CLKACT_DEFVAL #undef CRL_APB_PCAP_CTRL_CLKACT_SHIFT #undef CRL_APB_PCAP_CTRL_CLKACT_MASK -#define CRL_APB_PCAP_CTRL_CLKACT_DEFVAL 0x00001500 -#define CRL_APB_PCAP_CTRL_CLKACT_SHIFT 24 -#define CRL_APB_PCAP_CTRL_CLKACT_MASK 0x01000000U +#define CRL_APB_PCAP_CTRL_CLKACT_DEFVAL 0x00001500 +#define CRL_APB_PCAP_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_PCAP_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_PCAP_CTRL_DIVISOR0_DEFVAL #undef CRL_APB_PCAP_CTRL_DIVISOR0_SHIFT #undef CRL_APB_PCAP_CTRL_DIVISOR0_MASK -#define CRL_APB_PCAP_CTRL_DIVISOR0_DEFVAL 0x00001500 -#define CRL_APB_PCAP_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_PCAP_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRL_APB_PCAP_CTRL_DIVISOR0_DEFVAL 0x00001500 +#define CRL_APB_PCAP_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_PCAP_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRL_APB_PCAP_CTRL_SRCSEL_DEFVAL #undef CRL_APB_PCAP_CTRL_SRCSEL_SHIFT #undef CRL_APB_PCAP_CTRL_SRCSEL_MASK -#define CRL_APB_PCAP_CTRL_SRCSEL_DEFVAL 0x00001500 -#define CRL_APB_PCAP_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_PCAP_CTRL_SRCSEL_MASK 0x00000007U +#define CRL_APB_PCAP_CTRL_SRCSEL_DEFVAL 0x00001500 +#define CRL_APB_PCAP_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_PCAP_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRL_APB_LPD_SWITCH_CTRL_CLKACT_DEFVAL #undef CRL_APB_LPD_SWITCH_CTRL_CLKACT_SHIFT #undef CRL_APB_LPD_SWITCH_CTRL_CLKACT_MASK -#define CRL_APB_LPD_SWITCH_CTRL_CLKACT_DEFVAL 0x01000500 -#define CRL_APB_LPD_SWITCH_CTRL_CLKACT_SHIFT 24 -#define CRL_APB_LPD_SWITCH_CTRL_CLKACT_MASK 0x01000000U +#define CRL_APB_LPD_SWITCH_CTRL_CLKACT_DEFVAL 0x01000500 +#define CRL_APB_LPD_SWITCH_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_LPD_SWITCH_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_DEFVAL #undef CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_SHIFT #undef CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_MASK -#define CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_DEFVAL 0x01000500 -#define CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_DEFVAL 0x01000500 +#define CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRL_APB_LPD_SWITCH_CTRL_SRCSEL_DEFVAL #undef CRL_APB_LPD_SWITCH_CTRL_SRCSEL_SHIFT #undef CRL_APB_LPD_SWITCH_CTRL_SRCSEL_MASK -#define CRL_APB_LPD_SWITCH_CTRL_SRCSEL_DEFVAL 0x01000500 -#define CRL_APB_LPD_SWITCH_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_LPD_SWITCH_CTRL_SRCSEL_MASK 0x00000007U +#define CRL_APB_LPD_SWITCH_CTRL_SRCSEL_DEFVAL 0x01000500 +#define CRL_APB_LPD_SWITCH_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_LPD_SWITCH_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRL_APB_LPD_LSBUS_CTRL_CLKACT_DEFVAL #undef CRL_APB_LPD_LSBUS_CTRL_CLKACT_SHIFT #undef CRL_APB_LPD_LSBUS_CTRL_CLKACT_MASK -#define CRL_APB_LPD_LSBUS_CTRL_CLKACT_DEFVAL 0x01001800 -#define CRL_APB_LPD_LSBUS_CTRL_CLKACT_SHIFT 24 -#define CRL_APB_LPD_LSBUS_CTRL_CLKACT_MASK 0x01000000U +#define CRL_APB_LPD_LSBUS_CTRL_CLKACT_DEFVAL 0x01001800 +#define CRL_APB_LPD_LSBUS_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_LPD_LSBUS_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_DEFVAL #undef CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_SHIFT #undef CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_MASK -#define CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_DEFVAL 0x01001800 -#define CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_DEFVAL 0x01001800 +#define CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRL_APB_LPD_LSBUS_CTRL_SRCSEL_DEFVAL #undef CRL_APB_LPD_LSBUS_CTRL_SRCSEL_SHIFT #undef CRL_APB_LPD_LSBUS_CTRL_SRCSEL_MASK -#define CRL_APB_LPD_LSBUS_CTRL_SRCSEL_DEFVAL 0x01001800 -#define CRL_APB_LPD_LSBUS_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_LPD_LSBUS_CTRL_SRCSEL_MASK 0x00000007U +#define CRL_APB_LPD_LSBUS_CTRL_SRCSEL_DEFVAL 0x01001800 +#define CRL_APB_LPD_LSBUS_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_LPD_LSBUS_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRL_APB_DBG_LPD_CTRL_CLKACT_DEFVAL #undef CRL_APB_DBG_LPD_CTRL_CLKACT_SHIFT #undef CRL_APB_DBG_LPD_CTRL_CLKACT_MASK -#define CRL_APB_DBG_LPD_CTRL_CLKACT_DEFVAL 0x01002000 -#define CRL_APB_DBG_LPD_CTRL_CLKACT_SHIFT 24 -#define CRL_APB_DBG_LPD_CTRL_CLKACT_MASK 0x01000000U +#define CRL_APB_DBG_LPD_CTRL_CLKACT_DEFVAL 0x01002000 +#define CRL_APB_DBG_LPD_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_DBG_LPD_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_DBG_LPD_CTRL_DIVISOR0_DEFVAL #undef CRL_APB_DBG_LPD_CTRL_DIVISOR0_SHIFT #undef CRL_APB_DBG_LPD_CTRL_DIVISOR0_MASK -#define CRL_APB_DBG_LPD_CTRL_DIVISOR0_DEFVAL 0x01002000 -#define CRL_APB_DBG_LPD_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_DBG_LPD_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRL_APB_DBG_LPD_CTRL_DIVISOR0_DEFVAL 0x01002000 +#define CRL_APB_DBG_LPD_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_DBG_LPD_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRL_APB_DBG_LPD_CTRL_SRCSEL_DEFVAL #undef CRL_APB_DBG_LPD_CTRL_SRCSEL_SHIFT #undef CRL_APB_DBG_LPD_CTRL_SRCSEL_MASK -#define CRL_APB_DBG_LPD_CTRL_SRCSEL_DEFVAL 0x01002000 -#define CRL_APB_DBG_LPD_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_DBG_LPD_CTRL_SRCSEL_MASK 0x00000007U +#define CRL_APB_DBG_LPD_CTRL_SRCSEL_DEFVAL 0x01002000 +#define CRL_APB_DBG_LPD_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_DBG_LPD_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRL_APB_ADMA_REF_CTRL_CLKACT_DEFVAL #undef CRL_APB_ADMA_REF_CTRL_CLKACT_SHIFT #undef CRL_APB_ADMA_REF_CTRL_CLKACT_MASK -#define CRL_APB_ADMA_REF_CTRL_CLKACT_DEFVAL 0x00002000 -#define CRL_APB_ADMA_REF_CTRL_CLKACT_SHIFT 24 -#define CRL_APB_ADMA_REF_CTRL_CLKACT_MASK 0x01000000U +#define CRL_APB_ADMA_REF_CTRL_CLKACT_DEFVAL 0x00002000 +#define CRL_APB_ADMA_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_ADMA_REF_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_ADMA_REF_CTRL_DIVISOR0_DEFVAL #undef CRL_APB_ADMA_REF_CTRL_DIVISOR0_SHIFT #undef CRL_APB_ADMA_REF_CTRL_DIVISOR0_MASK -#define CRL_APB_ADMA_REF_CTRL_DIVISOR0_DEFVAL 0x00002000 -#define CRL_APB_ADMA_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_ADMA_REF_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRL_APB_ADMA_REF_CTRL_DIVISOR0_DEFVAL 0x00002000 +#define CRL_APB_ADMA_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_ADMA_REF_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRL_APB_ADMA_REF_CTRL_SRCSEL_DEFVAL #undef CRL_APB_ADMA_REF_CTRL_SRCSEL_SHIFT #undef CRL_APB_ADMA_REF_CTRL_SRCSEL_MASK -#define CRL_APB_ADMA_REF_CTRL_SRCSEL_DEFVAL 0x00002000 -#define CRL_APB_ADMA_REF_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_ADMA_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRL_APB_ADMA_REF_CTRL_SRCSEL_DEFVAL 0x00002000 +#define CRL_APB_ADMA_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_ADMA_REF_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRL_APB_PL0_REF_CTRL_CLKACT_DEFVAL #undef CRL_APB_PL0_REF_CTRL_CLKACT_SHIFT #undef CRL_APB_PL0_REF_CTRL_CLKACT_MASK -#define CRL_APB_PL0_REF_CTRL_CLKACT_DEFVAL 0x00052000 -#define CRL_APB_PL0_REF_CTRL_CLKACT_SHIFT 24 -#define CRL_APB_PL0_REF_CTRL_CLKACT_MASK 0x01000000U +#define CRL_APB_PL0_REF_CTRL_CLKACT_DEFVAL 0x00052000 +#define CRL_APB_PL0_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_PL0_REF_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_PL0_REF_CTRL_DIVISOR1_DEFVAL #undef CRL_APB_PL0_REF_CTRL_DIVISOR1_SHIFT #undef CRL_APB_PL0_REF_CTRL_DIVISOR1_MASK -#define CRL_APB_PL0_REF_CTRL_DIVISOR1_DEFVAL 0x00052000 -#define CRL_APB_PL0_REF_CTRL_DIVISOR1_SHIFT 16 -#define CRL_APB_PL0_REF_CTRL_DIVISOR1_MASK 0x003F0000U +#define CRL_APB_PL0_REF_CTRL_DIVISOR1_DEFVAL 0x00052000 +#define CRL_APB_PL0_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_PL0_REF_CTRL_DIVISOR1_MASK 0x003F0000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_PL0_REF_CTRL_DIVISOR0_DEFVAL #undef CRL_APB_PL0_REF_CTRL_DIVISOR0_SHIFT #undef CRL_APB_PL0_REF_CTRL_DIVISOR0_MASK -#define CRL_APB_PL0_REF_CTRL_DIVISOR0_DEFVAL 0x00052000 -#define CRL_APB_PL0_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_PL0_REF_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRL_APB_PL0_REF_CTRL_DIVISOR0_DEFVAL 0x00052000 +#define CRL_APB_PL0_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_PL0_REF_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRL_APB_PL0_REF_CTRL_SRCSEL_DEFVAL #undef CRL_APB_PL0_REF_CTRL_SRCSEL_SHIFT #undef CRL_APB_PL0_REF_CTRL_SRCSEL_MASK -#define CRL_APB_PL0_REF_CTRL_SRCSEL_DEFVAL 0x00052000 -#define CRL_APB_PL0_REF_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_PL0_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRL_APB_PL0_REF_CTRL_SRCSEL_DEFVAL 0x00052000 +#define CRL_APB_PL0_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_PL0_REF_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ -#undef CRL_APB_PL1_REF_CTRL_CLKACT_DEFVAL -#undef CRL_APB_PL1_REF_CTRL_CLKACT_SHIFT -#undef CRL_APB_PL1_REF_CTRL_CLKACT_MASK -#define CRL_APB_PL1_REF_CTRL_CLKACT_DEFVAL 0x00052000 -#define CRL_APB_PL1_REF_CTRL_CLKACT_SHIFT 24 -#define CRL_APB_PL1_REF_CTRL_CLKACT_MASK 0x01000000U - -/*6 bit divider*/ -#undef CRL_APB_PL1_REF_CTRL_DIVISOR1_DEFVAL -#undef CRL_APB_PL1_REF_CTRL_DIVISOR1_SHIFT -#undef CRL_APB_PL1_REF_CTRL_DIVISOR1_MASK -#define CRL_APB_PL1_REF_CTRL_DIVISOR1_DEFVAL 0x00052000 -#define CRL_APB_PL1_REF_CTRL_DIVISOR1_SHIFT 16 -#define CRL_APB_PL1_REF_CTRL_DIVISOR1_MASK 0x003F0000U - -/*6 bit divider*/ -#undef CRL_APB_PL1_REF_CTRL_DIVISOR0_DEFVAL -#undef CRL_APB_PL1_REF_CTRL_DIVISOR0_SHIFT -#undef CRL_APB_PL1_REF_CTRL_DIVISOR0_MASK -#define CRL_APB_PL1_REF_CTRL_DIVISOR0_DEFVAL 0x00052000 -#define CRL_APB_PL1_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_PL1_REF_CTRL_DIVISOR0_MASK 0x00003F00U - -/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.)*/ -#undef CRL_APB_PL1_REF_CTRL_SRCSEL_DEFVAL -#undef CRL_APB_PL1_REF_CTRL_SRCSEL_SHIFT -#undef CRL_APB_PL1_REF_CTRL_SRCSEL_MASK -#define CRL_APB_PL1_REF_CTRL_SRCSEL_DEFVAL 0x00052000 -#define CRL_APB_PL1_REF_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_PL1_REF_CTRL_SRCSEL_MASK 0x00000007U - -/*Clock active signal. Switch to 0 to disable the clock*/ -#undef CRL_APB_PL2_REF_CTRL_CLKACT_DEFVAL -#undef CRL_APB_PL2_REF_CTRL_CLKACT_SHIFT -#undef CRL_APB_PL2_REF_CTRL_CLKACT_MASK -#define CRL_APB_PL2_REF_CTRL_CLKACT_DEFVAL 0x00052000 -#define CRL_APB_PL2_REF_CTRL_CLKACT_SHIFT 24 -#define CRL_APB_PL2_REF_CTRL_CLKACT_MASK 0x01000000U - -/*6 bit divider*/ -#undef CRL_APB_PL2_REF_CTRL_DIVISOR1_DEFVAL -#undef CRL_APB_PL2_REF_CTRL_DIVISOR1_SHIFT -#undef CRL_APB_PL2_REF_CTRL_DIVISOR1_MASK -#define CRL_APB_PL2_REF_CTRL_DIVISOR1_DEFVAL 0x00052000 -#define CRL_APB_PL2_REF_CTRL_DIVISOR1_SHIFT 16 -#define CRL_APB_PL2_REF_CTRL_DIVISOR1_MASK 0x003F0000U - -/*6 bit divider*/ -#undef CRL_APB_PL2_REF_CTRL_DIVISOR0_DEFVAL -#undef CRL_APB_PL2_REF_CTRL_DIVISOR0_SHIFT -#undef CRL_APB_PL2_REF_CTRL_DIVISOR0_MASK -#define CRL_APB_PL2_REF_CTRL_DIVISOR0_DEFVAL 0x00052000 -#define CRL_APB_PL2_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_PL2_REF_CTRL_DIVISOR0_MASK 0x00003F00U - -/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.)*/ -#undef CRL_APB_PL2_REF_CTRL_SRCSEL_DEFVAL -#undef CRL_APB_PL2_REF_CTRL_SRCSEL_SHIFT -#undef CRL_APB_PL2_REF_CTRL_SRCSEL_MASK -#define CRL_APB_PL2_REF_CTRL_SRCSEL_DEFVAL 0x00052000 -#define CRL_APB_PL2_REF_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_PL2_REF_CTRL_SRCSEL_MASK 0x00000007U - -/*Clock active signal. Switch to 0 to disable the clock*/ -#undef CRL_APB_PL3_REF_CTRL_CLKACT_DEFVAL -#undef CRL_APB_PL3_REF_CTRL_CLKACT_SHIFT -#undef CRL_APB_PL3_REF_CTRL_CLKACT_MASK -#define CRL_APB_PL3_REF_CTRL_CLKACT_DEFVAL 0x00052000 -#define CRL_APB_PL3_REF_CTRL_CLKACT_SHIFT 24 -#define CRL_APB_PL3_REF_CTRL_CLKACT_MASK 0x01000000U - -/*6 bit divider*/ -#undef CRL_APB_PL3_REF_CTRL_DIVISOR1_DEFVAL -#undef CRL_APB_PL3_REF_CTRL_DIVISOR1_SHIFT -#undef CRL_APB_PL3_REF_CTRL_DIVISOR1_MASK -#define CRL_APB_PL3_REF_CTRL_DIVISOR1_DEFVAL 0x00052000 -#define CRL_APB_PL3_REF_CTRL_DIVISOR1_SHIFT 16 -#define CRL_APB_PL3_REF_CTRL_DIVISOR1_MASK 0x003F0000U - -/*6 bit divider*/ -#undef CRL_APB_PL3_REF_CTRL_DIVISOR0_DEFVAL -#undef CRL_APB_PL3_REF_CTRL_DIVISOR0_SHIFT -#undef CRL_APB_PL3_REF_CTRL_DIVISOR0_MASK -#define CRL_APB_PL3_REF_CTRL_DIVISOR0_DEFVAL 0x00052000 -#define CRL_APB_PL3_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_PL3_REF_CTRL_DIVISOR0_MASK 0x00003F00U - -/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.)*/ -#undef CRL_APB_PL3_REF_CTRL_SRCSEL_DEFVAL -#undef CRL_APB_PL3_REF_CTRL_SRCSEL_SHIFT -#undef CRL_APB_PL3_REF_CTRL_SRCSEL_MASK -#define CRL_APB_PL3_REF_CTRL_SRCSEL_DEFVAL 0x00052000 -#define CRL_APB_PL3_REF_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_PL3_REF_CTRL_SRCSEL_MASK 0x00000007U - -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_AMS_REF_CTRL_DIVISOR1_DEFVAL #undef CRL_APB_AMS_REF_CTRL_DIVISOR1_SHIFT #undef CRL_APB_AMS_REF_CTRL_DIVISOR1_MASK -#define CRL_APB_AMS_REF_CTRL_DIVISOR1_DEFVAL 0x01001800 -#define CRL_APB_AMS_REF_CTRL_DIVISOR1_SHIFT 16 -#define CRL_APB_AMS_REF_CTRL_DIVISOR1_MASK 0x003F0000U +#define CRL_APB_AMS_REF_CTRL_DIVISOR1_DEFVAL 0x01001800 +#define CRL_APB_AMS_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_AMS_REF_CTRL_DIVISOR1_MASK 0x003F0000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_AMS_REF_CTRL_DIVISOR0_DEFVAL #undef CRL_APB_AMS_REF_CTRL_DIVISOR0_SHIFT #undef CRL_APB_AMS_REF_CTRL_DIVISOR0_MASK -#define CRL_APB_AMS_REF_CTRL_DIVISOR0_DEFVAL 0x01001800 -#define CRL_APB_AMS_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_AMS_REF_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRL_APB_AMS_REF_CTRL_DIVISOR0_DEFVAL 0x01001800 +#define CRL_APB_AMS_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_AMS_REF_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRL_APB_AMS_REF_CTRL_SRCSEL_DEFVAL #undef CRL_APB_AMS_REF_CTRL_SRCSEL_SHIFT #undef CRL_APB_AMS_REF_CTRL_SRCSEL_MASK -#define CRL_APB_AMS_REF_CTRL_SRCSEL_DEFVAL 0x01001800 -#define CRL_APB_AMS_REF_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_AMS_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRL_APB_AMS_REF_CTRL_SRCSEL_DEFVAL 0x01001800 +#define CRL_APB_AMS_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_AMS_REF_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRL_APB_AMS_REF_CTRL_CLKACT_DEFVAL #undef CRL_APB_AMS_REF_CTRL_CLKACT_SHIFT #undef CRL_APB_AMS_REF_CTRL_CLKACT_MASK -#define CRL_APB_AMS_REF_CTRL_CLKACT_DEFVAL 0x01001800 -#define CRL_APB_AMS_REF_CTRL_CLKACT_SHIFT 24 -#define CRL_APB_AMS_REF_CTRL_CLKACT_MASK 0x01000000U +#define CRL_APB_AMS_REF_CTRL_CLKACT_DEFVAL 0x01001800 +#define CRL_APB_AMS_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_AMS_REF_CTRL_CLKACT_MASK 0x01000000U -/*000 = IOPLL; 001 = RPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This - is not usually an issue, but designers must be aware.)*/ +/* +* 000 = IOPLL; 001 = RPLL; (This signal may only be toggled after 4 cycles + * of the old clock and 4 cycles of the new clock. This is not usually an + * issue, but designers must be aware.) +*/ #undef CRL_APB_DLL_REF_CTRL_SRCSEL_DEFVAL #undef CRL_APB_DLL_REF_CTRL_SRCSEL_SHIFT #undef CRL_APB_DLL_REF_CTRL_SRCSEL_MASK -#define CRL_APB_DLL_REF_CTRL_SRCSEL_DEFVAL 0x00000000 -#define CRL_APB_DLL_REF_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_DLL_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRL_APB_DLL_REF_CTRL_SRCSEL_DEFVAL 0x00000000 +#define CRL_APB_DLL_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_DLL_REF_CTRL_SRCSEL_MASK 0x00000007U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_DEFVAL #undef CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_SHIFT #undef CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_MASK -#define CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_DEFVAL 0x00001800 -#define CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_DEFVAL 0x00001800 +#define CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_MASK 0x00003F00U -/*1XX = pss_ref_clk; 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and - cycles of the new clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 1XX = pss_ref_clk; 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may + * only be toggled after 4 cycles of the old clock and 4 cycles of the new + * clock. This is not usually an issue, but designers must be aware.) +*/ #undef CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_DEFVAL #undef CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_SHIFT #undef CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_MASK -#define CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_DEFVAL 0x00001800 -#define CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_DEFVAL 0x00001800 +#define CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_DEFVAL #undef CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_SHIFT #undef CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_MASK -#define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_DEFVAL 0x00001800 -#define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_SHIFT 24 -#define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_MASK 0x01000000U +#define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_DEFVAL 0x00001800 +#define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_MASK 0x01000000U -/*000 = IOPLL_TO_FPD; 010 = APLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of - he new clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = IOPLL_TO_FPD; 010 = APLL; 011 = DPLL; (This signal may only be tog + * gled after 4 cycles of the old clock and 4 cycles of the new clock. This + * is not usually an issue, but designers must be aware.) +*/ #undef CRF_APB_SATA_REF_CTRL_SRCSEL_DEFVAL #undef CRF_APB_SATA_REF_CTRL_SRCSEL_SHIFT #undef CRF_APB_SATA_REF_CTRL_SRCSEL_MASK -#define CRF_APB_SATA_REF_CTRL_SRCSEL_DEFVAL 0x01001600 -#define CRF_APB_SATA_REF_CTRL_SRCSEL_SHIFT 0 -#define CRF_APB_SATA_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRF_APB_SATA_REF_CTRL_SRCSEL_DEFVAL 0x01001600 +#define CRF_APB_SATA_REF_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_SATA_REF_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRF_APB_SATA_REF_CTRL_CLKACT_DEFVAL #undef CRF_APB_SATA_REF_CTRL_CLKACT_SHIFT #undef CRF_APB_SATA_REF_CTRL_CLKACT_MASK -#define CRF_APB_SATA_REF_CTRL_CLKACT_DEFVAL 0x01001600 -#define CRF_APB_SATA_REF_CTRL_CLKACT_SHIFT 24 -#define CRF_APB_SATA_REF_CTRL_CLKACT_MASK 0x01000000U +#define CRF_APB_SATA_REF_CTRL_CLKACT_DEFVAL 0x01001600 +#define CRF_APB_SATA_REF_CTRL_CLKACT_SHIFT 24 +#define CRF_APB_SATA_REF_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRF_APB_SATA_REF_CTRL_DIVISOR0_DEFVAL #undef CRF_APB_SATA_REF_CTRL_DIVISOR0_SHIFT #undef CRF_APB_SATA_REF_CTRL_DIVISOR0_MASK -#define CRF_APB_SATA_REF_CTRL_DIVISOR0_DEFVAL 0x01001600 -#define CRF_APB_SATA_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRF_APB_SATA_REF_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRF_APB_SATA_REF_CTRL_DIVISOR0_DEFVAL 0x01001600 +#define CRF_APB_SATA_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_SATA_REF_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = IOPLL_TO_FPD; 010 = RPLL_TO_FPD; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cyc - es of the new clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = IOPLL_TO_FPD; 010 = RPLL_TO_FPD; 011 = DPLL; (This signal may only + * be toggled after 4 cycles of the old clock and 4 cycles of the new cloc + * k. This is not usually an issue, but designers must be aware.) +*/ #undef CRF_APB_PCIE_REF_CTRL_SRCSEL_DEFVAL #undef CRF_APB_PCIE_REF_CTRL_SRCSEL_SHIFT #undef CRF_APB_PCIE_REF_CTRL_SRCSEL_MASK -#define CRF_APB_PCIE_REF_CTRL_SRCSEL_DEFVAL 0x00001500 -#define CRF_APB_PCIE_REF_CTRL_SRCSEL_SHIFT 0 -#define CRF_APB_PCIE_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRF_APB_PCIE_REF_CTRL_SRCSEL_DEFVAL 0x00001500 +#define CRF_APB_PCIE_REF_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_PCIE_REF_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRF_APB_PCIE_REF_CTRL_CLKACT_DEFVAL #undef CRF_APB_PCIE_REF_CTRL_CLKACT_SHIFT #undef CRF_APB_PCIE_REF_CTRL_CLKACT_MASK -#define CRF_APB_PCIE_REF_CTRL_CLKACT_DEFVAL 0x00001500 -#define CRF_APB_PCIE_REF_CTRL_CLKACT_SHIFT 24 -#define CRF_APB_PCIE_REF_CTRL_CLKACT_MASK 0x01000000U +#define CRF_APB_PCIE_REF_CTRL_CLKACT_DEFVAL 0x00001500 +#define CRF_APB_PCIE_REF_CTRL_CLKACT_SHIFT 24 +#define CRF_APB_PCIE_REF_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRF_APB_PCIE_REF_CTRL_DIVISOR0_DEFVAL #undef CRF_APB_PCIE_REF_CTRL_DIVISOR0_SHIFT #undef CRF_APB_PCIE_REF_CTRL_DIVISOR0_MASK -#define CRF_APB_PCIE_REF_CTRL_DIVISOR0_DEFVAL 0x00001500 -#define CRF_APB_PCIE_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRF_APB_PCIE_REF_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRF_APB_PCIE_REF_CTRL_DIVISOR0_DEFVAL 0x00001500 +#define CRF_APB_PCIE_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_PCIE_REF_CTRL_DIVISOR0_MASK 0x00003F00U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_DEFVAL #undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_SHIFT #undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_MASK -#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_DEFVAL 0x01002300 -#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_SHIFT 16 -#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_MASK 0x003F0000U +#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_DEFVAL 0x01002300 +#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_MASK 0x003F0000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_DEFVAL #undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_SHIFT #undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_MASK -#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_DEFVAL 0x01002300 -#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_DEFVAL 0x01002300 +#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (This signal may only be toggled after 4 cycles of the - ld clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (T + * his signal may only be toggled after 4 cycles of the old clock and 4 cyc + * les of the new clock. This is not usually an issue, but designers must b + * e aware.) +*/ #undef CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_DEFVAL #undef CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_SHIFT #undef CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_MASK -#define CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_DEFVAL 0x01002300 -#define CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_SHIFT 0 -#define CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_DEFVAL 0x01002300 +#define CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_DEFVAL #undef CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_SHIFT #undef CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_MASK -#define CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_DEFVAL 0x01002300 -#define CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_SHIFT 24 -#define CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_MASK 0x01000000U +#define CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_DEFVAL 0x01002300 +#define CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_SHIFT 24 +#define CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_DEFVAL #undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_SHIFT #undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_MASK -#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_DEFVAL 0x01032300 -#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_SHIFT 16 -#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_MASK 0x003F0000U +#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_DEFVAL 0x01032300 +#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_MASK 0x003F0000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_DEFVAL #undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_SHIFT #undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_MASK -#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_DEFVAL 0x01032300 -#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_DEFVAL 0x01032300 +#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (This signal may only be toggled after 4 cycles of the - ld clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (T + * his signal may only be toggled after 4 cycles of the old clock and 4 cyc + * les of the new clock. This is not usually an issue, but designers must b + * e aware.) +*/ #undef CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_DEFVAL #undef CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_SHIFT #undef CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_MASK -#define CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_DEFVAL 0x01032300 -#define CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_SHIFT 0 -#define CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_DEFVAL 0x01032300 +#define CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_DEFVAL #undef CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_SHIFT #undef CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_MASK -#define CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_DEFVAL 0x01032300 -#define CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_SHIFT 24 -#define CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_MASK 0x01000000U +#define CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_DEFVAL 0x01032300 +#define CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_SHIFT 24 +#define CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRF_APB_DP_STC_REF_CTRL_DIVISOR1_DEFVAL #undef CRF_APB_DP_STC_REF_CTRL_DIVISOR1_SHIFT #undef CRF_APB_DP_STC_REF_CTRL_DIVISOR1_MASK -#define CRF_APB_DP_STC_REF_CTRL_DIVISOR1_DEFVAL 0x01203200 -#define CRF_APB_DP_STC_REF_CTRL_DIVISOR1_SHIFT 16 -#define CRF_APB_DP_STC_REF_CTRL_DIVISOR1_MASK 0x003F0000U +#define CRF_APB_DP_STC_REF_CTRL_DIVISOR1_DEFVAL 0x01203200 +#define CRF_APB_DP_STC_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRF_APB_DP_STC_REF_CTRL_DIVISOR1_MASK 0x003F0000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRF_APB_DP_STC_REF_CTRL_DIVISOR0_DEFVAL #undef CRF_APB_DP_STC_REF_CTRL_DIVISOR0_SHIFT #undef CRF_APB_DP_STC_REF_CTRL_DIVISOR0_MASK -#define CRF_APB_DP_STC_REF_CTRL_DIVISOR0_DEFVAL 0x01203200 -#define CRF_APB_DP_STC_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRF_APB_DP_STC_REF_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRF_APB_DP_STC_REF_CTRL_DIVISOR0_DEFVAL 0x01203200 +#define CRF_APB_DP_STC_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_DP_STC_REF_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of t - e new clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD; (This signal may only be togg + * led after 4 cycles of the old clock and 4 cycles of the new clock. This + * is not usually an issue, but designers must be aware.) +*/ #undef CRF_APB_DP_STC_REF_CTRL_SRCSEL_DEFVAL #undef CRF_APB_DP_STC_REF_CTRL_SRCSEL_SHIFT #undef CRF_APB_DP_STC_REF_CTRL_SRCSEL_MASK -#define CRF_APB_DP_STC_REF_CTRL_SRCSEL_DEFVAL 0x01203200 -#define CRF_APB_DP_STC_REF_CTRL_SRCSEL_SHIFT 0 -#define CRF_APB_DP_STC_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRF_APB_DP_STC_REF_CTRL_SRCSEL_DEFVAL 0x01203200 +#define CRF_APB_DP_STC_REF_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_DP_STC_REF_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRF_APB_DP_STC_REF_CTRL_CLKACT_DEFVAL #undef CRF_APB_DP_STC_REF_CTRL_CLKACT_SHIFT #undef CRF_APB_DP_STC_REF_CTRL_CLKACT_MASK -#define CRF_APB_DP_STC_REF_CTRL_CLKACT_DEFVAL 0x01203200 -#define CRF_APB_DP_STC_REF_CTRL_CLKACT_SHIFT 24 -#define CRF_APB_DP_STC_REF_CTRL_CLKACT_MASK 0x01000000U +#define CRF_APB_DP_STC_REF_CTRL_CLKACT_DEFVAL 0x01203200 +#define CRF_APB_DP_STC_REF_CTRL_CLKACT_SHIFT 24 +#define CRF_APB_DP_STC_REF_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRF_APB_ACPU_CTRL_DIVISOR0_DEFVAL #undef CRF_APB_ACPU_CTRL_DIVISOR0_SHIFT #undef CRF_APB_ACPU_CTRL_DIVISOR0_MASK -#define CRF_APB_ACPU_CTRL_DIVISOR0_DEFVAL 0x03000400 -#define CRF_APB_ACPU_CTRL_DIVISOR0_SHIFT 8 -#define CRF_APB_ACPU_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRF_APB_ACPU_CTRL_DIVISOR0_DEFVAL 0x03000400 +#define CRF_APB_ACPU_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_ACPU_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = APLL; 010 = DPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - lock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = APLL; 010 = DPLL; 011 = VPLL; (This signal may only be toggled aft + * er 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRF_APB_ACPU_CTRL_SRCSEL_DEFVAL #undef CRF_APB_ACPU_CTRL_SRCSEL_SHIFT #undef CRF_APB_ACPU_CTRL_SRCSEL_MASK -#define CRF_APB_ACPU_CTRL_SRCSEL_DEFVAL 0x03000400 -#define CRF_APB_ACPU_CTRL_SRCSEL_SHIFT 0 -#define CRF_APB_ACPU_CTRL_SRCSEL_MASK 0x00000007U +#define CRF_APB_ACPU_CTRL_SRCSEL_DEFVAL 0x03000400 +#define CRF_APB_ACPU_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_ACPU_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock. For the half speed APU Clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock. For the half spee + * d APU Clock +*/ #undef CRF_APB_ACPU_CTRL_CLKACT_HALF_DEFVAL #undef CRF_APB_ACPU_CTRL_CLKACT_HALF_SHIFT #undef CRF_APB_ACPU_CTRL_CLKACT_HALF_MASK -#define CRF_APB_ACPU_CTRL_CLKACT_HALF_DEFVAL 0x03000400 -#define CRF_APB_ACPU_CTRL_CLKACT_HALF_SHIFT 25 -#define CRF_APB_ACPU_CTRL_CLKACT_HALF_MASK 0x02000000U +#define CRF_APB_ACPU_CTRL_CLKACT_HALF_DEFVAL 0x03000400 +#define CRF_APB_ACPU_CTRL_CLKACT_HALF_SHIFT 25 +#define CRF_APB_ACPU_CTRL_CLKACT_HALF_MASK 0x02000000U -/*Clock active signal. Switch to 0 to disable the clock. For the full speed ACPUX Clock. This will shut off the high speed cloc - to the entire APU*/ +/* +* Clock active signal. Switch to 0 to disable the clock. For the full spee + * d ACPUX Clock. This will shut off the high speed clock to the entire APU +*/ #undef CRF_APB_ACPU_CTRL_CLKACT_FULL_DEFVAL #undef CRF_APB_ACPU_CTRL_CLKACT_FULL_SHIFT #undef CRF_APB_ACPU_CTRL_CLKACT_FULL_MASK -#define CRF_APB_ACPU_CTRL_CLKACT_FULL_DEFVAL 0x03000400 -#define CRF_APB_ACPU_CTRL_CLKACT_FULL_SHIFT 24 -#define CRF_APB_ACPU_CTRL_CLKACT_FULL_MASK 0x01000000U +#define CRF_APB_ACPU_CTRL_CLKACT_FULL_DEFVAL 0x03000400 +#define CRF_APB_ACPU_CTRL_CLKACT_FULL_SHIFT 24 +#define CRF_APB_ACPU_CTRL_CLKACT_FULL_MASK 0x01000000U -/*6 bit divider*/ -#undef CRF_APB_DBG_TRACE_CTRL_DIVISOR0_DEFVAL -#undef CRF_APB_DBG_TRACE_CTRL_DIVISOR0_SHIFT -#undef CRF_APB_DBG_TRACE_CTRL_DIVISOR0_MASK -#define CRF_APB_DBG_TRACE_CTRL_DIVISOR0_DEFVAL 0x00002500 -#define CRF_APB_DBG_TRACE_CTRL_DIVISOR0_SHIFT 8 -#define CRF_APB_DBG_TRACE_CTRL_DIVISOR0_MASK 0x00003F00U - -/*000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of - he new clock. This is not usually an issue, but designers must be aware.)*/ -#undef CRF_APB_DBG_TRACE_CTRL_SRCSEL_DEFVAL -#undef CRF_APB_DBG_TRACE_CTRL_SRCSEL_SHIFT -#undef CRF_APB_DBG_TRACE_CTRL_SRCSEL_MASK -#define CRF_APB_DBG_TRACE_CTRL_SRCSEL_DEFVAL 0x00002500 -#define CRF_APB_DBG_TRACE_CTRL_SRCSEL_SHIFT 0 -#define CRF_APB_DBG_TRACE_CTRL_SRCSEL_MASK 0x00000007U - -/*Clock active signal. Switch to 0 to disable the clock*/ -#undef CRF_APB_DBG_TRACE_CTRL_CLKACT_DEFVAL -#undef CRF_APB_DBG_TRACE_CTRL_CLKACT_SHIFT -#undef CRF_APB_DBG_TRACE_CTRL_CLKACT_MASK -#define CRF_APB_DBG_TRACE_CTRL_CLKACT_DEFVAL 0x00002500 -#define CRF_APB_DBG_TRACE_CTRL_CLKACT_SHIFT 24 -#define CRF_APB_DBG_TRACE_CTRL_CLKACT_MASK 0x01000000U - -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRF_APB_DBG_FPD_CTRL_DIVISOR0_DEFVAL #undef CRF_APB_DBG_FPD_CTRL_DIVISOR0_SHIFT #undef CRF_APB_DBG_FPD_CTRL_DIVISOR0_MASK -#define CRF_APB_DBG_FPD_CTRL_DIVISOR0_DEFVAL 0x01002500 -#define CRF_APB_DBG_FPD_CTRL_DIVISOR0_SHIFT 8 -#define CRF_APB_DBG_FPD_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRF_APB_DBG_FPD_CTRL_DIVISOR0_DEFVAL 0x01002500 +#define CRF_APB_DBG_FPD_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_DBG_FPD_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of - he new clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be tog + * gled after 4 cycles of the old clock and 4 cycles of the new clock. This + * is not usually an issue, but designers must be aware.) +*/ #undef CRF_APB_DBG_FPD_CTRL_SRCSEL_DEFVAL #undef CRF_APB_DBG_FPD_CTRL_SRCSEL_SHIFT #undef CRF_APB_DBG_FPD_CTRL_SRCSEL_MASK -#define CRF_APB_DBG_FPD_CTRL_SRCSEL_DEFVAL 0x01002500 -#define CRF_APB_DBG_FPD_CTRL_SRCSEL_SHIFT 0 -#define CRF_APB_DBG_FPD_CTRL_SRCSEL_MASK 0x00000007U +#define CRF_APB_DBG_FPD_CTRL_SRCSEL_DEFVAL 0x01002500 +#define CRF_APB_DBG_FPD_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_DBG_FPD_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRF_APB_DBG_FPD_CTRL_CLKACT_DEFVAL #undef CRF_APB_DBG_FPD_CTRL_CLKACT_SHIFT #undef CRF_APB_DBG_FPD_CTRL_CLKACT_MASK -#define CRF_APB_DBG_FPD_CTRL_CLKACT_DEFVAL 0x01002500 -#define CRF_APB_DBG_FPD_CTRL_CLKACT_SHIFT 24 -#define CRF_APB_DBG_FPD_CTRL_CLKACT_MASK 0x01000000U +#define CRF_APB_DBG_FPD_CTRL_CLKACT_DEFVAL 0x01002500 +#define CRF_APB_DBG_FPD_CTRL_CLKACT_SHIFT 24 +#define CRF_APB_DBG_FPD_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRF_APB_DDR_CTRL_DIVISOR0_DEFVAL #undef CRF_APB_DDR_CTRL_DIVISOR0_SHIFT #undef CRF_APB_DDR_CTRL_DIVISOR0_MASK -#define CRF_APB_DDR_CTRL_DIVISOR0_DEFVAL 0x01000500 -#define CRF_APB_DDR_CTRL_DIVISOR0_SHIFT 8 -#define CRF_APB_DDR_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRF_APB_DDR_CTRL_DIVISOR0_DEFVAL 0x01000500 +#define CRF_APB_DDR_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_DDR_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = DPLL; 001 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This - s not usually an issue, but designers must be aware.)*/ +/* +* 000 = DPLL; 001 = VPLL; (This signal may only be toggled after 4 cycles + * of the old clock and 4 cycles of the new clock. This is not usually an i + * ssue, but designers must be aware.) +*/ #undef CRF_APB_DDR_CTRL_SRCSEL_DEFVAL #undef CRF_APB_DDR_CTRL_SRCSEL_SHIFT #undef CRF_APB_DDR_CTRL_SRCSEL_MASK -#define CRF_APB_DDR_CTRL_SRCSEL_DEFVAL 0x01000500 -#define CRF_APB_DDR_CTRL_SRCSEL_SHIFT 0 -#define CRF_APB_DDR_CTRL_SRCSEL_MASK 0x00000007U +#define CRF_APB_DDR_CTRL_SRCSEL_DEFVAL 0x01000500 +#define CRF_APB_DDR_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_DDR_CTRL_SRCSEL_MASK 0x00000007U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRF_APB_GPU_REF_CTRL_DIVISOR0_DEFVAL #undef CRF_APB_GPU_REF_CTRL_DIVISOR0_SHIFT #undef CRF_APB_GPU_REF_CTRL_DIVISOR0_MASK -#define CRF_APB_GPU_REF_CTRL_DIVISOR0_DEFVAL 0x00001500 -#define CRF_APB_GPU_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRF_APB_GPU_REF_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRF_APB_GPU_REF_CTRL_DIVISOR0_DEFVAL 0x00001500 +#define CRF_APB_GPU_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_GPU_REF_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = IOPLL_TO_FPD; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of - he new clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = IOPLL_TO_FPD; 010 = VPLL; 011 = DPLL; (This signal may only be tog + * gled after 4 cycles of the old clock and 4 cycles of the new clock. This + * is not usually an issue, but designers must be aware.) +*/ #undef CRF_APB_GPU_REF_CTRL_SRCSEL_DEFVAL #undef CRF_APB_GPU_REF_CTRL_SRCSEL_SHIFT #undef CRF_APB_GPU_REF_CTRL_SRCSEL_MASK -#define CRF_APB_GPU_REF_CTRL_SRCSEL_DEFVAL 0x00001500 -#define CRF_APB_GPU_REF_CTRL_SRCSEL_SHIFT 0 -#define CRF_APB_GPU_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRF_APB_GPU_REF_CTRL_SRCSEL_DEFVAL 0x00001500 +#define CRF_APB_GPU_REF_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_GPU_REF_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock, which will stop clock for GPU (and both Pixel Processors).*/ +/* +* Clock active signal. Switch to 0 to disable the clock, which will stop c + * lock for GPU (and both Pixel Processors). +*/ #undef CRF_APB_GPU_REF_CTRL_CLKACT_DEFVAL #undef CRF_APB_GPU_REF_CTRL_CLKACT_SHIFT #undef CRF_APB_GPU_REF_CTRL_CLKACT_MASK -#define CRF_APB_GPU_REF_CTRL_CLKACT_DEFVAL 0x00001500 -#define CRF_APB_GPU_REF_CTRL_CLKACT_SHIFT 24 -#define CRF_APB_GPU_REF_CTRL_CLKACT_MASK 0x01000000U +#define CRF_APB_GPU_REF_CTRL_CLKACT_DEFVAL 0x00001500 +#define CRF_APB_GPU_REF_CTRL_CLKACT_SHIFT 24 +#define CRF_APB_GPU_REF_CTRL_CLKACT_MASK 0x01000000U -/*Clock active signal for Pixel Processor. Switch to 0 to disable the clock only to this Pixel Processor*/ +/* +* Clock active signal for Pixel Processor. Switch to 0 to disable the cloc + * k only to this Pixel Processor +*/ #undef CRF_APB_GPU_REF_CTRL_PP0_CLKACT_DEFVAL #undef CRF_APB_GPU_REF_CTRL_PP0_CLKACT_SHIFT #undef CRF_APB_GPU_REF_CTRL_PP0_CLKACT_MASK -#define CRF_APB_GPU_REF_CTRL_PP0_CLKACT_DEFVAL 0x00001500 -#define CRF_APB_GPU_REF_CTRL_PP0_CLKACT_SHIFT 25 -#define CRF_APB_GPU_REF_CTRL_PP0_CLKACT_MASK 0x02000000U +#define CRF_APB_GPU_REF_CTRL_PP0_CLKACT_DEFVAL 0x00001500 +#define CRF_APB_GPU_REF_CTRL_PP0_CLKACT_SHIFT 25 +#define CRF_APB_GPU_REF_CTRL_PP0_CLKACT_MASK 0x02000000U -/*Clock active signal for Pixel Processor. Switch to 0 to disable the clock only to this Pixel Processor*/ +/* +* Clock active signal for Pixel Processor. Switch to 0 to disable the cloc + * k only to this Pixel Processor +*/ #undef CRF_APB_GPU_REF_CTRL_PP1_CLKACT_DEFVAL #undef CRF_APB_GPU_REF_CTRL_PP1_CLKACT_SHIFT #undef CRF_APB_GPU_REF_CTRL_PP1_CLKACT_MASK -#define CRF_APB_GPU_REF_CTRL_PP1_CLKACT_DEFVAL 0x00001500 -#define CRF_APB_GPU_REF_CTRL_PP1_CLKACT_SHIFT 26 -#define CRF_APB_GPU_REF_CTRL_PP1_CLKACT_MASK 0x04000000U +#define CRF_APB_GPU_REF_CTRL_PP1_CLKACT_DEFVAL 0x00001500 +#define CRF_APB_GPU_REF_CTRL_PP1_CLKACT_SHIFT 26 +#define CRF_APB_GPU_REF_CTRL_PP1_CLKACT_MASK 0x04000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRF_APB_GDMA_REF_CTRL_DIVISOR0_DEFVAL #undef CRF_APB_GDMA_REF_CTRL_DIVISOR0_SHIFT #undef CRF_APB_GDMA_REF_CTRL_DIVISOR0_MASK -#define CRF_APB_GDMA_REF_CTRL_DIVISOR0_DEFVAL 0x01000500 -#define CRF_APB_GDMA_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRF_APB_GDMA_REF_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRF_APB_GDMA_REF_CTRL_DIVISOR0_DEFVAL 0x01000500 +#define CRF_APB_GDMA_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_GDMA_REF_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - lock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled aft + * er 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRF_APB_GDMA_REF_CTRL_SRCSEL_DEFVAL #undef CRF_APB_GDMA_REF_CTRL_SRCSEL_SHIFT #undef CRF_APB_GDMA_REF_CTRL_SRCSEL_MASK -#define CRF_APB_GDMA_REF_CTRL_SRCSEL_DEFVAL 0x01000500 -#define CRF_APB_GDMA_REF_CTRL_SRCSEL_SHIFT 0 -#define CRF_APB_GDMA_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRF_APB_GDMA_REF_CTRL_SRCSEL_DEFVAL 0x01000500 +#define CRF_APB_GDMA_REF_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_GDMA_REF_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRF_APB_GDMA_REF_CTRL_CLKACT_DEFVAL #undef CRF_APB_GDMA_REF_CTRL_CLKACT_SHIFT #undef CRF_APB_GDMA_REF_CTRL_CLKACT_MASK -#define CRF_APB_GDMA_REF_CTRL_CLKACT_DEFVAL 0x01000500 -#define CRF_APB_GDMA_REF_CTRL_CLKACT_SHIFT 24 -#define CRF_APB_GDMA_REF_CTRL_CLKACT_MASK 0x01000000U +#define CRF_APB_GDMA_REF_CTRL_CLKACT_DEFVAL 0x01000500 +#define CRF_APB_GDMA_REF_CTRL_CLKACT_SHIFT 24 +#define CRF_APB_GDMA_REF_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRF_APB_DPDMA_REF_CTRL_DIVISOR0_DEFVAL #undef CRF_APB_DPDMA_REF_CTRL_DIVISOR0_SHIFT #undef CRF_APB_DPDMA_REF_CTRL_DIVISOR0_MASK -#define CRF_APB_DPDMA_REF_CTRL_DIVISOR0_DEFVAL 0x01000500 -#define CRF_APB_DPDMA_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRF_APB_DPDMA_REF_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRF_APB_DPDMA_REF_CTRL_DIVISOR0_DEFVAL 0x01000500 +#define CRF_APB_DPDMA_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_DPDMA_REF_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - lock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled aft + * er 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRF_APB_DPDMA_REF_CTRL_SRCSEL_DEFVAL #undef CRF_APB_DPDMA_REF_CTRL_SRCSEL_SHIFT #undef CRF_APB_DPDMA_REF_CTRL_SRCSEL_MASK -#define CRF_APB_DPDMA_REF_CTRL_SRCSEL_DEFVAL 0x01000500 -#define CRF_APB_DPDMA_REF_CTRL_SRCSEL_SHIFT 0 -#define CRF_APB_DPDMA_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRF_APB_DPDMA_REF_CTRL_SRCSEL_DEFVAL 0x01000500 +#define CRF_APB_DPDMA_REF_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_DPDMA_REF_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRF_APB_DPDMA_REF_CTRL_CLKACT_DEFVAL #undef CRF_APB_DPDMA_REF_CTRL_CLKACT_SHIFT #undef CRF_APB_DPDMA_REF_CTRL_CLKACT_MASK -#define CRF_APB_DPDMA_REF_CTRL_CLKACT_DEFVAL 0x01000500 -#define CRF_APB_DPDMA_REF_CTRL_CLKACT_SHIFT 24 -#define CRF_APB_DPDMA_REF_CTRL_CLKACT_MASK 0x01000000U +#define CRF_APB_DPDMA_REF_CTRL_CLKACT_DEFVAL 0x01000500 +#define CRF_APB_DPDMA_REF_CTRL_CLKACT_SHIFT 24 +#define CRF_APB_DPDMA_REF_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_DEFVAL #undef CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_SHIFT #undef CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_MASK -#define CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_DEFVAL 0x01000400 -#define CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_SHIFT 8 -#define CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_DEFVAL 0x01000400 +#define CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - lock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled aft + * er 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_DEFVAL #undef CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_SHIFT #undef CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_MASK -#define CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_DEFVAL 0x01000400 -#define CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_SHIFT 0 -#define CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_MASK 0x00000007U +#define CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_DEFVAL 0x01000400 +#define CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRF_APB_TOPSW_MAIN_CTRL_CLKACT_DEFVAL #undef CRF_APB_TOPSW_MAIN_CTRL_CLKACT_SHIFT #undef CRF_APB_TOPSW_MAIN_CTRL_CLKACT_MASK -#define CRF_APB_TOPSW_MAIN_CTRL_CLKACT_DEFVAL 0x01000400 -#define CRF_APB_TOPSW_MAIN_CTRL_CLKACT_SHIFT 24 -#define CRF_APB_TOPSW_MAIN_CTRL_CLKACT_MASK 0x01000000U +#define CRF_APB_TOPSW_MAIN_CTRL_CLKACT_DEFVAL 0x01000400 +#define CRF_APB_TOPSW_MAIN_CTRL_CLKACT_SHIFT 24 +#define CRF_APB_TOPSW_MAIN_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_DEFVAL #undef CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_SHIFT #undef CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_MASK -#define CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_DEFVAL 0x01000800 -#define CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_SHIFT 8 -#define CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_DEFVAL 0x01000800 +#define CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = APLL; 010 = IOPLL_TO_FPD; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of - he new clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = APLL; 010 = IOPLL_TO_FPD; 011 = DPLL; (This signal may only be tog + * gled after 4 cycles of the old clock and 4 cycles of the new clock. This + * is not usually an issue, but designers must be aware.) +*/ #undef CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_DEFVAL #undef CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_SHIFT #undef CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_MASK -#define CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_DEFVAL 0x01000800 -#define CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_SHIFT 0 -#define CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_MASK 0x00000007U +#define CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_DEFVAL 0x01000800 +#define CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_DEFVAL #undef CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_SHIFT #undef CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_MASK -#define CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_DEFVAL 0x01000800 -#define CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_SHIFT 24 -#define CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_MASK 0x01000000U +#define CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_DEFVAL 0x01000800 +#define CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_SHIFT 24 +#define CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_DEFVAL #undef CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_SHIFT #undef CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_MASK -#define CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_DEFVAL 0x00000A00 -#define CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_SHIFT 8 -#define CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_DEFVAL 0x00000A00 +#define CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of - he new clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be tog + * gled after 4 cycles of the old clock and 4 cycles of the new clock. This + * is not usually an issue, but designers must be aware.) +*/ #undef CRF_APB_DBG_TSTMP_CTRL_SRCSEL_DEFVAL #undef CRF_APB_DBG_TSTMP_CTRL_SRCSEL_SHIFT #undef CRF_APB_DBG_TSTMP_CTRL_SRCSEL_MASK -#define CRF_APB_DBG_TSTMP_CTRL_SRCSEL_DEFVAL 0x00000A00 -#define CRF_APB_DBG_TSTMP_CTRL_SRCSEL_SHIFT 0 -#define CRF_APB_DBG_TSTMP_CTRL_SRCSEL_MASK 0x00000007U +#define CRF_APB_DBG_TSTMP_CTRL_SRCSEL_DEFVAL 0x00000A00 +#define CRF_APB_DBG_TSTMP_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_DBG_TSTMP_CTRL_SRCSEL_MASK 0x00000007U -/*00" = Select the APB switch clock for the APB interface of TTC0'01" = Select the PLL ref clock for the APB interface of TTC0' - 0" = Select the R5 clock for the APB interface of TTC0*/ +/* +* 00" = Select the APB switch clock for the APB interface of TTC0'01" = Se + * lect the PLL ref clock for the APB interface of TTC0'10" = Select the R5 + * clock for the APB interface of TTC0 +*/ #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_DEFVAL #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_SHIFT #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_MASK -#define IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_SHIFT 0 -#define IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_MASK 0x00000003U +#define IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_SHIFT 0 +#define IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_MASK 0x00000003U -/*00" = Select the APB switch clock for the APB interface of TTC1'01" = Select the PLL ref clock for the APB interface of TTC1' - 0" = Select the R5 clock for the APB interface of TTC1*/ +/* +* 00" = Select the APB switch clock for the APB interface of TTC1'01" = Se + * lect the PLL ref clock for the APB interface of TTC1'10" = Select the R5 + * clock for the APB interface of TTC1 +*/ #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_DEFVAL #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_SHIFT #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_MASK -#define IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_SHIFT 2 -#define IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_MASK 0x0000000CU +#define IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_SHIFT 2 +#define IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_MASK 0x0000000CU -/*00" = Select the APB switch clock for the APB interface of TTC2'01" = Select the PLL ref clock for the APB interface of TTC2' - 0" = Select the R5 clock for the APB interface of TTC2*/ +/* +* 00" = Select the APB switch clock for the APB interface of TTC2'01" = Se + * lect the PLL ref clock for the APB interface of TTC2'10" = Select the R5 + * clock for the APB interface of TTC2 +*/ #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_DEFVAL #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_SHIFT #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_MASK -#define IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_SHIFT 4 -#define IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_MASK 0x00000030U +#define IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_SHIFT 4 +#define IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_MASK 0x00000030U -/*00" = Select the APB switch clock for the APB interface of TTC3'01" = Select the PLL ref clock for the APB interface of TTC3' - 0" = Select the R5 clock for the APB interface of TTC3*/ +/* +* 00" = Select the APB switch clock for the APB interface of TTC3'01" = Se + * lect the PLL ref clock for the APB interface of TTC3'10" = Select the R5 + * clock for the APB interface of TTC3 +*/ #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_DEFVAL #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_SHIFT #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_MASK -#define IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_SHIFT 6 -#define IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_MASK 0x000000C0U +#define IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_SHIFT 6 +#define IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_MASK 0x000000C0U -/*System watchdog timer clock source selection: 0: Internal APB clock 1: External (PL clock via EMIO or Pinout clock via MIO)*/ +/* +* System watchdog timer clock source selection: 0: Internal APB clock 1: E + * xternal (PL clock via EMIO or Pinout clock via MIO) +*/ #undef FPD_SLCR_WDT_CLK_SEL_SELECT_DEFVAL #undef FPD_SLCR_WDT_CLK_SEL_SELECT_SHIFT #undef FPD_SLCR_WDT_CLK_SEL_SELECT_MASK -#define FPD_SLCR_WDT_CLK_SEL_SELECT_DEFVAL 0x00000000 -#define FPD_SLCR_WDT_CLK_SEL_SELECT_SHIFT 0 -#define FPD_SLCR_WDT_CLK_SEL_SELECT_MASK 0x00000001U +#define FPD_SLCR_WDT_CLK_SEL_SELECT_DEFVAL 0x00000000 +#define FPD_SLCR_WDT_CLK_SEL_SELECT_SHIFT 0 +#define FPD_SLCR_WDT_CLK_SEL_SELECT_MASK 0x00000001U -/*System watchdog timer clock source selection: 0: internal clock APB clock 1: external clock from PL via EMIO, or from pinout - ia MIO*/ +/* +* System watchdog timer clock source selection: 0: internal clock APB cloc + * k 1: external clock from PL via EMIO, or from pinout via MIO +*/ #undef IOU_SLCR_WDT_CLK_SEL_SELECT_DEFVAL #undef IOU_SLCR_WDT_CLK_SEL_SELECT_SHIFT #undef IOU_SLCR_WDT_CLK_SEL_SELECT_MASK -#define IOU_SLCR_WDT_CLK_SEL_SELECT_DEFVAL 0x00000000 -#define IOU_SLCR_WDT_CLK_SEL_SELECT_SHIFT 0 -#define IOU_SLCR_WDT_CLK_SEL_SELECT_MASK 0x00000001U +#define IOU_SLCR_WDT_CLK_SEL_SELECT_DEFVAL 0x00000000 +#define IOU_SLCR_WDT_CLK_SEL_SELECT_SHIFT 0 +#define IOU_SLCR_WDT_CLK_SEL_SELECT_MASK 0x00000001U -/*System watchdog timer clock source selection: 0: internal clock APB clock 1: external clock pss_ref_clk*/ +/* +* System watchdog timer clock source selection: 0: internal clock APB cloc + * k 1: external clock pss_ref_clk +*/ #undef LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_DEFVAL #undef LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_SHIFT #undef LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_MASK -#define LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_DEFVAL 0x00000000 -#define LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_SHIFT 0 -#define LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_MASK 0x00000001U +#define LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_DEFVAL 0x00000000 +#define LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_SHIFT 0 +#define LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_MASK 0x00000001U #undef CRF_APB_RST_DDR_SS_OFFSET #define CRF_APB_RST_DDR_SS_OFFSET 0XFD1A0108 #undef DDRC_MSTR_OFFSET @@ -2066,6 +2368,8 @@ #define DDRC_PWRTMG_OFFSET 0XFD070034 #undef DDRC_RFSHCTL0_OFFSET #define DDRC_RFSHCTL0_OFFSET 0XFD070050 +#undef DDRC_RFSHCTL1_OFFSET +#define DDRC_RFSHCTL1_OFFSET 0XFD070054 #undef DDRC_RFSHCTL3_OFFSET #define DDRC_RFSHCTL3_OFFSET 0XFD070060 #undef DDRC_RFSHTMG_OFFSET @@ -2134,6 +2438,8 @@ #define DDRC_DFILPCFG0_OFFSET 0XFD070198 #undef DDRC_DFILPCFG1_OFFSET #define DDRC_DFILPCFG1_OFFSET 0XFD07019C +#undef DDRC_DFIUPD0_OFFSET +#define DDRC_DFIUPD0_OFFSET 0XFD0701A0 #undef DDRC_DFIUPD1_OFFSET #define DDRC_DFIUPD1_OFFSET 0XFD0701A4 #undef DDRC_DFIMISC_OFFSET @@ -2176,6 +2482,16 @@ #define DDRC_PERFLPR1_OFFSET 0XFD070264 #undef DDRC_PERFWR1_OFFSET #define DDRC_PERFWR1_OFFSET 0XFD07026C +#undef DDRC_DQMAP0_OFFSET +#define DDRC_DQMAP0_OFFSET 0XFD070280 +#undef DDRC_DQMAP1_OFFSET +#define DDRC_DQMAP1_OFFSET 0XFD070284 +#undef DDRC_DQMAP2_OFFSET +#define DDRC_DQMAP2_OFFSET 0XFD070288 +#undef DDRC_DQMAP3_OFFSET +#define DDRC_DQMAP3_OFFSET 0XFD07028C +#undef DDRC_DQMAP4_OFFSET +#define DDRC_DQMAP4_OFFSET 0XFD070290 #undef DDRC_DQMAP5_OFFSET #define DDRC_DQMAP5_OFFSET 0XFD070294 #undef DDRC_DBG0_OFFSET @@ -2282,8 +2598,12 @@ #define DDR_PHY_PTR0_OFFSET 0XFD080040 #undef DDR_PHY_PTR1_OFFSET #define DDR_PHY_PTR1_OFFSET 0XFD080044 +#undef DDR_PHY_PLLCR0_OFFSET +#define DDR_PHY_PLLCR0_OFFSET 0XFD080068 #undef DDR_PHY_DSGCR_OFFSET #define DDR_PHY_DSGCR_OFFSET 0XFD080090 +#undef DDR_PHY_GPR0_OFFSET +#define DDR_PHY_GPR0_OFFSET 0XFD0800C0 #undef DDR_PHY_DCR_OFFSET #define DDR_PHY_DCR_OFFSET 0XFD080100 #undef DDR_PHY_DTPR0_OFFSET @@ -2338,6 +2658,8 @@ #define DDR_PHY_DTCR1_OFFSET 0XFD080204 #undef DDR_PHY_CATR0_OFFSET #define DDR_PHY_CATR0_OFFSET 0XFD080240 +#undef DDR_PHY_DQSDR0_OFFSET +#define DDR_PHY_DQSDR0_OFFSET 0XFD080250 #undef DDR_PHY_BISTLSR_OFFSET #define DDR_PHY_BISTLSR_OFFSET 0XFD080414 #undef DDR_PHY_RIOCR5_OFFSET @@ -2386,10 +2708,6 @@ #define DDR_PHY_DX0GCR5_OFFSET 0XFD080714 #undef DDR_PHY_DX0GCR6_OFFSET #define DDR_PHY_DX0GCR6_OFFSET 0XFD080718 -#undef DDR_PHY_DX0LCDLR2_OFFSET -#define DDR_PHY_DX0LCDLR2_OFFSET 0XFD080788 -#undef DDR_PHY_DX0GTR0_OFFSET -#define DDR_PHY_DX0GTR0_OFFSET 0XFD0807C0 #undef DDR_PHY_DX1GCR0_OFFSET #define DDR_PHY_DX1GCR0_OFFSET 0XFD080800 #undef DDR_PHY_DX1GCR4_OFFSET @@ -2398,10 +2716,6 @@ #define DDR_PHY_DX1GCR5_OFFSET 0XFD080814 #undef DDR_PHY_DX1GCR6_OFFSET #define DDR_PHY_DX1GCR6_OFFSET 0XFD080818 -#undef DDR_PHY_DX1LCDLR2_OFFSET -#define DDR_PHY_DX1LCDLR2_OFFSET 0XFD080888 -#undef DDR_PHY_DX1GTR0_OFFSET -#define DDR_PHY_DX1GTR0_OFFSET 0XFD0808C0 #undef DDR_PHY_DX2GCR0_OFFSET #define DDR_PHY_DX2GCR0_OFFSET 0XFD080900 #undef DDR_PHY_DX2GCR1_OFFSET @@ -2412,10 +2726,6 @@ #define DDR_PHY_DX2GCR5_OFFSET 0XFD080914 #undef DDR_PHY_DX2GCR6_OFFSET #define DDR_PHY_DX2GCR6_OFFSET 0XFD080918 -#undef DDR_PHY_DX2LCDLR2_OFFSET -#define DDR_PHY_DX2LCDLR2_OFFSET 0XFD080988 -#undef DDR_PHY_DX2GTR0_OFFSET -#define DDR_PHY_DX2GTR0_OFFSET 0XFD0809C0 #undef DDR_PHY_DX3GCR0_OFFSET #define DDR_PHY_DX3GCR0_OFFSET 0XFD080A00 #undef DDR_PHY_DX3GCR1_OFFSET @@ -2426,10 +2736,6 @@ #define DDR_PHY_DX3GCR5_OFFSET 0XFD080A14 #undef DDR_PHY_DX3GCR6_OFFSET #define DDR_PHY_DX3GCR6_OFFSET 0XFD080A18 -#undef DDR_PHY_DX3LCDLR2_OFFSET -#define DDR_PHY_DX3LCDLR2_OFFSET 0XFD080A88 -#undef DDR_PHY_DX3GTR0_OFFSET -#define DDR_PHY_DX3GTR0_OFFSET 0XFD080AC0 #undef DDR_PHY_DX4GCR0_OFFSET #define DDR_PHY_DX4GCR0_OFFSET 0XFD080B00 #undef DDR_PHY_DX4GCR1_OFFSET @@ -2440,10 +2746,6 @@ #define DDR_PHY_DX4GCR5_OFFSET 0XFD080B14 #undef DDR_PHY_DX4GCR6_OFFSET #define DDR_PHY_DX4GCR6_OFFSET 0XFD080B18 -#undef DDR_PHY_DX4LCDLR2_OFFSET -#define DDR_PHY_DX4LCDLR2_OFFSET 0XFD080B88 -#undef DDR_PHY_DX4GTR0_OFFSET -#define DDR_PHY_DX4GTR0_OFFSET 0XFD080BC0 #undef DDR_PHY_DX5GCR0_OFFSET #define DDR_PHY_DX5GCR0_OFFSET 0XFD080C00 #undef DDR_PHY_DX5GCR1_OFFSET @@ -2454,10 +2756,6 @@ #define DDR_PHY_DX5GCR5_OFFSET 0XFD080C14 #undef DDR_PHY_DX5GCR6_OFFSET #define DDR_PHY_DX5GCR6_OFFSET 0XFD080C18 -#undef DDR_PHY_DX5LCDLR2_OFFSET -#define DDR_PHY_DX5LCDLR2_OFFSET 0XFD080C88 -#undef DDR_PHY_DX5GTR0_OFFSET -#define DDR_PHY_DX5GTR0_OFFSET 0XFD080CC0 #undef DDR_PHY_DX6GCR0_OFFSET #define DDR_PHY_DX6GCR0_OFFSET 0XFD080D00 #undef DDR_PHY_DX6GCR1_OFFSET @@ -2468,10 +2766,6 @@ #define DDR_PHY_DX6GCR5_OFFSET 0XFD080D14 #undef DDR_PHY_DX6GCR6_OFFSET #define DDR_PHY_DX6GCR6_OFFSET 0XFD080D18 -#undef DDR_PHY_DX6LCDLR2_OFFSET -#define DDR_PHY_DX6LCDLR2_OFFSET 0XFD080D88 -#undef DDR_PHY_DX6GTR0_OFFSET -#define DDR_PHY_DX6GTR0_OFFSET 0XFD080DC0 #undef DDR_PHY_DX7GCR0_OFFSET #define DDR_PHY_DX7GCR0_OFFSET 0XFD080E00 #undef DDR_PHY_DX7GCR1_OFFSET @@ -2482,10 +2776,6 @@ #define DDR_PHY_DX7GCR5_OFFSET 0XFD080E14 #undef DDR_PHY_DX7GCR6_OFFSET #define DDR_PHY_DX7GCR6_OFFSET 0XFD080E18 -#undef DDR_PHY_DX7LCDLR2_OFFSET -#define DDR_PHY_DX7LCDLR2_OFFSET 0XFD080E88 -#undef DDR_PHY_DX7GTR0_OFFSET -#define DDR_PHY_DX7GTR0_OFFSET 0XFD080EC0 #undef DDR_PHY_DX8GCR0_OFFSET #define DDR_PHY_DX8GCR0_OFFSET 0XFD080F00 #undef DDR_PHY_DX8GCR1_OFFSET @@ -2496,12 +2786,10 @@ #define DDR_PHY_DX8GCR5_OFFSET 0XFD080F14 #undef DDR_PHY_DX8GCR6_OFFSET #define DDR_PHY_DX8GCR6_OFFSET 0XFD080F18 -#undef DDR_PHY_DX8LCDLR2_OFFSET -#define DDR_PHY_DX8LCDLR2_OFFSET 0XFD080F88 -#undef DDR_PHY_DX8GTR0_OFFSET -#define DDR_PHY_DX8GTR0_OFFSET 0XFD080FC0 #undef DDR_PHY_DX8SL0OSC_OFFSET #define DDR_PHY_DX8SL0OSC_OFFSET 0XFD081400 +#undef DDR_PHY_DX8SL0PLLCR0_OFFSET +#define DDR_PHY_DX8SL0PLLCR0_OFFSET 0XFD081404 #undef DDR_PHY_DX8SL0DQSCTL_OFFSET #define DDR_PHY_DX8SL0DQSCTL_OFFSET 0XFD08141C #undef DDR_PHY_DX8SL0DXCTL2_OFFSET @@ -2510,6 +2798,8 @@ #define DDR_PHY_DX8SL0IOCR_OFFSET 0XFD081430 #undef DDR_PHY_DX8SL1OSC_OFFSET #define DDR_PHY_DX8SL1OSC_OFFSET 0XFD081440 +#undef DDR_PHY_DX8SL1PLLCR0_OFFSET +#define DDR_PHY_DX8SL1PLLCR0_OFFSET 0XFD081444 #undef DDR_PHY_DX8SL1DQSCTL_OFFSET #define DDR_PHY_DX8SL1DQSCTL_OFFSET 0XFD08145C #undef DDR_PHY_DX8SL1DXCTL2_OFFSET @@ -2518,6 +2808,8 @@ #define DDR_PHY_DX8SL1IOCR_OFFSET 0XFD081470 #undef DDR_PHY_DX8SL2OSC_OFFSET #define DDR_PHY_DX8SL2OSC_OFFSET 0XFD081480 +#undef DDR_PHY_DX8SL2PLLCR0_OFFSET +#define DDR_PHY_DX8SL2PLLCR0_OFFSET 0XFD081484 #undef DDR_PHY_DX8SL2DQSCTL_OFFSET #define DDR_PHY_DX8SL2DQSCTL_OFFSET 0XFD08149C #undef DDR_PHY_DX8SL2DXCTL2_OFFSET @@ -2526,6 +2818,8 @@ #define DDR_PHY_DX8SL2IOCR_OFFSET 0XFD0814B0 #undef DDR_PHY_DX8SL3OSC_OFFSET #define DDR_PHY_DX8SL3OSC_OFFSET 0XFD0814C0 +#undef DDR_PHY_DX8SL3PLLCR0_OFFSET +#define DDR_PHY_DX8SL3PLLCR0_OFFSET 0XFD0814C4 #undef DDR_PHY_DX8SL3DQSCTL_OFFSET #define DDR_PHY_DX8SL3DQSCTL_OFFSET 0XFD0814DC #undef DDR_PHY_DX8SL3DXCTL2_OFFSET @@ -2534,14391 +2828,18570 @@ #define DDR_PHY_DX8SL3IOCR_OFFSET 0XFD0814F0 #undef DDR_PHY_DX8SL4OSC_OFFSET #define DDR_PHY_DX8SL4OSC_OFFSET 0XFD081500 +#undef DDR_PHY_DX8SL4PLLCR0_OFFSET +#define DDR_PHY_DX8SL4PLLCR0_OFFSET 0XFD081504 #undef DDR_PHY_DX8SL4DQSCTL_OFFSET #define DDR_PHY_DX8SL4DQSCTL_OFFSET 0XFD08151C #undef DDR_PHY_DX8SL4DXCTL2_OFFSET #define DDR_PHY_DX8SL4DXCTL2_OFFSET 0XFD08152C #undef DDR_PHY_DX8SL4IOCR_OFFSET #define DDR_PHY_DX8SL4IOCR_OFFSET 0XFD081530 +#undef DDR_PHY_DX8SLBPLLCR0_OFFSET +#define DDR_PHY_DX8SLBPLLCR0_OFFSET 0XFD0817C4 #undef DDR_PHY_DX8SLBDQSCTL_OFFSET #define DDR_PHY_DX8SLBDQSCTL_OFFSET 0XFD0817DC -#undef DDR_PHY_PIR_OFFSET -#define DDR_PHY_PIR_OFFSET 0XFD080004 -/*DDR block level reset inside of the DDR Sub System*/ +/* +* DDR block level reset inside of the DDR Sub System +*/ #undef CRF_APB_RST_DDR_SS_DDR_RESET_DEFVAL #undef CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT #undef CRF_APB_RST_DDR_SS_DDR_RESET_MASK -#define CRF_APB_RST_DDR_SS_DDR_RESET_DEFVAL 0x0000000F -#define CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT 3 -#define CRF_APB_RST_DDR_SS_DDR_RESET_MASK 0x00000008U +#define CRF_APB_RST_DDR_SS_DDR_RESET_DEFVAL 0x0000000F +#define CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT 3 +#define CRF_APB_RST_DDR_SS_DDR_RESET_MASK 0x00000008U -/*Indicates the configuration of the device used in the system. - 00 - x4 device - 01 - x8 device - 10 - x16 device - 11 - x32 - evice*/ +/* +* Indicates the configuration of the device used in the system. - 00 - x4 + * device - 01 - x8 device - 10 - x16 device - 11 - x32 device +*/ #undef DDRC_MSTR_DEVICE_CONFIG_DEFVAL #undef DDRC_MSTR_DEVICE_CONFIG_SHIFT #undef DDRC_MSTR_DEVICE_CONFIG_MASK -#define DDRC_MSTR_DEVICE_CONFIG_DEFVAL 0x03040001 -#define DDRC_MSTR_DEVICE_CONFIG_SHIFT 30 -#define DDRC_MSTR_DEVICE_CONFIG_MASK 0xC0000000U +#define DDRC_MSTR_DEVICE_CONFIG_DEFVAL 0x03040001 +#define DDRC_MSTR_DEVICE_CONFIG_SHIFT 30 +#define DDRC_MSTR_DEVICE_CONFIG_MASK 0xC0000000U -/*Choose which registers are used. - 0 - Original registers - 1 - Shadow registers*/ +/* +* Choose which registers are used. - 0 - Original registers - 1 - Shadow r + * egisters +*/ #undef DDRC_MSTR_FREQUENCY_MODE_DEFVAL #undef DDRC_MSTR_FREQUENCY_MODE_SHIFT #undef DDRC_MSTR_FREQUENCY_MODE_MASK -#define DDRC_MSTR_FREQUENCY_MODE_DEFVAL 0x03040001 -#define DDRC_MSTR_FREQUENCY_MODE_SHIFT 29 -#define DDRC_MSTR_FREQUENCY_MODE_MASK 0x20000000U +#define DDRC_MSTR_FREQUENCY_MODE_DEFVAL 0x03040001 +#define DDRC_MSTR_FREQUENCY_MODE_SHIFT 29 +#define DDRC_MSTR_FREQUENCY_MODE_MASK 0x20000000U -/*Only present for multi-rank configurations. Each bit represents one rank. For two-rank configurations, only bits[25:24] are p - esent. - 1 - populated - 0 - unpopulated LSB is the lowest rank number. For 2 ranks following combinations are legal: - 01 - - ne rank - 11 - Two ranks - Others - Reserved. For 4 ranks following combinations are legal: - 0001 - One rank - 0011 - Two ra - ks - 1111 - Four ranks*/ +/* +* Only present for multi-rank configurations. Each bit represents one rank + * . For two-rank configurations, only bits[25:24] are present. - 1 - popul + * ated - 0 - unpopulated LSB is the lowest rank number. For 2 ranks follow + * ing combinations are legal: - 01 - One rank - 11 - Two ranks - Others - + * Reserved. For 4 ranks following combinations are legal: - 0001 - One ran + * k - 0011 - Two ranks - 1111 - Four ranks +*/ #undef DDRC_MSTR_ACTIVE_RANKS_DEFVAL #undef DDRC_MSTR_ACTIVE_RANKS_SHIFT #undef DDRC_MSTR_ACTIVE_RANKS_MASK -#define DDRC_MSTR_ACTIVE_RANKS_DEFVAL 0x03040001 -#define DDRC_MSTR_ACTIVE_RANKS_SHIFT 24 -#define DDRC_MSTR_ACTIVE_RANKS_MASK 0x03000000U +#define DDRC_MSTR_ACTIVE_RANKS_DEFVAL 0x03040001 +#define DDRC_MSTR_ACTIVE_RANKS_SHIFT 24 +#define DDRC_MSTR_ACTIVE_RANKS_MASK 0x03000000U -/*SDRAM burst length used: - 0001 - Burst length of 2 (only supported for mDDR) - 0010 - Burst length of 4 - 0100 - Burst lengt - of 8 - 1000 - Burst length of 16 (only supported for mDDR, LPDDR2, and LPDDR4) All other values are reserved. This controls - he burst size used to access the SDRAM. This must match the burst length mode register setting in the SDRAM. (For BC4/8 on-th - -fly mode of DDR3 and DDR4, set this field to 0x0100) Burst length of 2 is not supported with AXI ports when MEMC_BURST_LENGT - is 8. Burst length of 2 is only supported with MEMC_FREQ_RATIO = 1*/ +/* +* SDRAM burst length used: - 0001 - Burst length of 2 (only supported for + * mDDR) - 0010 - Burst length of 4 - 0100 - Burst length of 8 - 1000 - Bur + * st length of 16 (only supported for mDDR, LPDDR2, and LPDDR4) All other + * values are reserved. This controls the burst size used to access the SDR + * AM. This must match the burst length mode register setting in the SDRAM. + * (For BC4/8 on-the-fly mode of DDR3 and DDR4, set this field to 0x0100) + * Burst length of 2 is not supported with AXI ports when MEMC_BURST_LENGTH + * is 8. Burst length of 2 is only supported with MEMC_FREQ_RATIO = 1 +*/ #undef DDRC_MSTR_BURST_RDWR_DEFVAL #undef DDRC_MSTR_BURST_RDWR_SHIFT #undef DDRC_MSTR_BURST_RDWR_MASK -#define DDRC_MSTR_BURST_RDWR_DEFVAL 0x03040001 -#define DDRC_MSTR_BURST_RDWR_SHIFT 16 -#define DDRC_MSTR_BURST_RDWR_MASK 0x000F0000U +#define DDRC_MSTR_BURST_RDWR_DEFVAL 0x03040001 +#define DDRC_MSTR_BURST_RDWR_SHIFT 16 +#define DDRC_MSTR_BURST_RDWR_MASK 0x000F0000U -/*Set to 1 when the uMCTL2 and DRAM has to be put in DLL-off mode for low frequency operation. Set to 0 to put uMCTL2 and DRAM - n DLL-on mode for normal frequency operation. If DDR4 CRC/parity retry is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), d - l_off_mode is not supported, and this bit must be set to '0'.*/ +/* +* Set to 1 when the uMCTL2 and DRAM has to be put in DLL-off mode for low + * frequency operation. Set to 0 to put uMCTL2 and DRAM in DLL-on mode for + * normal frequency operation. If DDR4 CRC/parity retry is enabled (CRCPARC + * TL1.crc_parity_retry_enable = 1), dll_off_mode is not supported, and thi + * s bit must be set to '0'. +*/ #undef DDRC_MSTR_DLL_OFF_MODE_DEFVAL #undef DDRC_MSTR_DLL_OFF_MODE_SHIFT #undef DDRC_MSTR_DLL_OFF_MODE_MASK -#define DDRC_MSTR_DLL_OFF_MODE_DEFVAL 0x03040001 -#define DDRC_MSTR_DLL_OFF_MODE_SHIFT 15 -#define DDRC_MSTR_DLL_OFF_MODE_MASK 0x00008000U +#define DDRC_MSTR_DLL_OFF_MODE_DEFVAL 0x03040001 +#define DDRC_MSTR_DLL_OFF_MODE_SHIFT 15 +#define DDRC_MSTR_DLL_OFF_MODE_MASK 0x00008000U -/*Selects proportion of DQ bus width that is used by the SDRAM - 00 - Full DQ bus width to SDRAM - 01 - Half DQ bus width to SD - AM - 10 - Quarter DQ bus width to SDRAM - 11 - Reserved. Note that half bus width mode is only supported when the SDRAM bus w - dth is a multiple of 16, and quarter bus width mode is only supported when the SDRAM bus width is a multiple of 32 and the co - figuration parameter MEMC_QBUS_SUPPORT is set. Bus width refers to DQ bus width (excluding any ECC width).*/ +/* +* Selects proportion of DQ bus width that is used by the SDRAM - 00 - Full + * DQ bus width to SDRAM - 01 - Half DQ bus width to SDRAM - 10 - Quarter + * DQ bus width to SDRAM - 11 - Reserved. Note that half bus width mode is + * only supported when the SDRAM bus width is a multiple of 16, and quarter + * bus width mode is only supported when the SDRAM bus width is a multiple + * of 32 and the configuration parameter MEMC_QBUS_SUPPORT is set. Bus wid + * th refers to DQ bus width (excluding any ECC width). +*/ #undef DDRC_MSTR_DATA_BUS_WIDTH_DEFVAL #undef DDRC_MSTR_DATA_BUS_WIDTH_SHIFT #undef DDRC_MSTR_DATA_BUS_WIDTH_MASK -#define DDRC_MSTR_DATA_BUS_WIDTH_DEFVAL 0x03040001 -#define DDRC_MSTR_DATA_BUS_WIDTH_SHIFT 12 -#define DDRC_MSTR_DATA_BUS_WIDTH_MASK 0x00003000U +#define DDRC_MSTR_DATA_BUS_WIDTH_DEFVAL 0x03040001 +#define DDRC_MSTR_DATA_BUS_WIDTH_SHIFT 12 +#define DDRC_MSTR_DATA_BUS_WIDTH_MASK 0x00003000U -/*1 indicates put the DRAM in geardown mode (2N) and 0 indicates put the DRAM in normal mode (1N). This register can be changed - only when the Controller is in self-refresh mode. This signal must be set the same value as MR3 bit A3. Note: Geardown mode - s not supported if the configuration parameter MEMC_CMD_RTN2IDLE is set*/ +/* +* 1 indicates put the DRAM in geardown mode (2N) and 0 indicates put the D + * RAM in normal mode (1N). This register can be changed, only when the Con + * troller is in self-refresh mode. This signal must be set the same value + * as MR3 bit A3. Note: Geardown mode is not supported if the configuration + * parameter MEMC_CMD_RTN2IDLE is set +*/ #undef DDRC_MSTR_GEARDOWN_MODE_DEFVAL #undef DDRC_MSTR_GEARDOWN_MODE_SHIFT #undef DDRC_MSTR_GEARDOWN_MODE_MASK -#define DDRC_MSTR_GEARDOWN_MODE_DEFVAL 0x03040001 -#define DDRC_MSTR_GEARDOWN_MODE_SHIFT 11 -#define DDRC_MSTR_GEARDOWN_MODE_MASK 0x00000800U +#define DDRC_MSTR_GEARDOWN_MODE_DEFVAL 0x03040001 +#define DDRC_MSTR_GEARDOWN_MODE_SHIFT 11 +#define DDRC_MSTR_GEARDOWN_MODE_MASK 0x00000800U -/*If 1, then uMCTL2 uses 2T timing. Otherwise, uses 1T timing. In 2T timing, all command signals (except chip select) are held - or 2 clocks on the SDRAM bus. Chip select is asserted on the second cycle of the command Note: 2T timing is not supported in - PDDR2/LPDDR3/LPDDR4 mode Note: 2T timing is not supported if the configuration parameter MEMC_CMD_RTN2IDLE is set Note: 2T ti - ing is not supported in DDR4 geardown mode.*/ +/* +* If 1, then uMCTL2 uses 2T timing. Otherwise, uses 1T timing. In 2T timin + * g, all command signals (except chip select) are held for 2 clocks on the + * SDRAM bus. Chip select is asserted on the second cycle of the command N + * ote: 2T timing is not supported in LPDDR2/LPDDR3/LPDDR4 mode Note: 2T ti + * ming is not supported if the configuration parameter MEMC_CMD_RTN2IDLE i + * s set Note: 2T timing is not supported in DDR4 geardown mode. +*/ #undef DDRC_MSTR_EN_2T_TIMING_MODE_DEFVAL #undef DDRC_MSTR_EN_2T_TIMING_MODE_SHIFT #undef DDRC_MSTR_EN_2T_TIMING_MODE_MASK -#define DDRC_MSTR_EN_2T_TIMING_MODE_DEFVAL 0x03040001 -#define DDRC_MSTR_EN_2T_TIMING_MODE_SHIFT 10 -#define DDRC_MSTR_EN_2T_TIMING_MODE_MASK 0x00000400U +#define DDRC_MSTR_EN_2T_TIMING_MODE_DEFVAL 0x03040001 +#define DDRC_MSTR_EN_2T_TIMING_MODE_SHIFT 10 +#define DDRC_MSTR_EN_2T_TIMING_MODE_MASK 0x00000400U -/*When set, enable burst-chop in DDR3/DDR4. Burst Chop for Reads is exercised only in HIF configurations (UMCTL2_INCL_ARB not s - t) and if in full bus width mode (MSTR.data_bus_width = 00). Burst Chop for Writes is exercised only if Partial Writes enable - (UMCTL2_PARTIAL_WR=1) and if CRC is disabled (CRCPARCTL1.crc_enable = 0). If DDR4 CRC/parity retry is enabled (CRCPARCTL1.cr - _parity_retry_enable = 1), burst chop is not supported, and this bit must be set to '0'*/ +/* +* When set, enable burst-chop in DDR3/DDR4. Burst Chop for Reads is exerci + * sed only in HIF configurations (UMCTL2_INCL_ARB not set) and if in full + * bus width mode (MSTR.data_bus_width = 00). Burst Chop for Writes is exer + * cised only if Partial Writes enabled (UMCTL2_PARTIAL_WR=1) and if CRC is + * disabled (CRCPARCTL1.crc_enable = 0). If DDR4 CRC/parity retry is enabl + * ed (CRCPARCTL1.crc_parity_retry_enable = 1), burst chop is not supported + * , and this bit must be set to '0' +*/ #undef DDRC_MSTR_BURSTCHOP_DEFVAL #undef DDRC_MSTR_BURSTCHOP_SHIFT #undef DDRC_MSTR_BURSTCHOP_MASK -#define DDRC_MSTR_BURSTCHOP_DEFVAL 0x03040001 -#define DDRC_MSTR_BURSTCHOP_SHIFT 9 -#define DDRC_MSTR_BURSTCHOP_MASK 0x00000200U +#define DDRC_MSTR_BURSTCHOP_DEFVAL 0x03040001 +#define DDRC_MSTR_BURSTCHOP_SHIFT 9 +#define DDRC_MSTR_BURSTCHOP_MASK 0x00000200U -/*Select LPDDR4 SDRAM - 1 - LPDDR4 SDRAM device in use. - 0 - non-LPDDR4 device in use Present only in designs configured to su - port LPDDR4.*/ +/* +* Select LPDDR4 SDRAM - 1 - LPDDR4 SDRAM device in use. - 0 - non-LPDDR4 d + * evice in use Present only in designs configured to support LPDDR4. +*/ #undef DDRC_MSTR_LPDDR4_DEFVAL #undef DDRC_MSTR_LPDDR4_SHIFT #undef DDRC_MSTR_LPDDR4_MASK -#define DDRC_MSTR_LPDDR4_DEFVAL 0x03040001 -#define DDRC_MSTR_LPDDR4_SHIFT 5 -#define DDRC_MSTR_LPDDR4_MASK 0x00000020U +#define DDRC_MSTR_LPDDR4_DEFVAL 0x03040001 +#define DDRC_MSTR_LPDDR4_SHIFT 5 +#define DDRC_MSTR_LPDDR4_MASK 0x00000020U -/*Select DDR4 SDRAM - 1 - DDR4 SDRAM device in use. - 0 - non-DDR4 device in use Present only in designs configured to support - DR4.*/ +/* +* Select DDR4 SDRAM - 1 - DDR4 SDRAM device in use. - 0 - non-DDR4 device + * in use Present only in designs configured to support DDR4. +*/ #undef DDRC_MSTR_DDR4_DEFVAL #undef DDRC_MSTR_DDR4_SHIFT #undef DDRC_MSTR_DDR4_MASK -#define DDRC_MSTR_DDR4_DEFVAL 0x03040001 -#define DDRC_MSTR_DDR4_SHIFT 4 -#define DDRC_MSTR_DDR4_MASK 0x00000010U +#define DDRC_MSTR_DDR4_DEFVAL 0x03040001 +#define DDRC_MSTR_DDR4_SHIFT 4 +#define DDRC_MSTR_DDR4_MASK 0x00000010U -/*Select LPDDR3 SDRAM - 1 - LPDDR3 SDRAM device in use. - 0 - non-LPDDR3 device in use Present only in designs configured to su - port LPDDR3.*/ +/* +* Select LPDDR3 SDRAM - 1 - LPDDR3 SDRAM device in use. - 0 - non-LPDDR3 d + * evice in use Present only in designs configured to support LPDDR3. +*/ #undef DDRC_MSTR_LPDDR3_DEFVAL #undef DDRC_MSTR_LPDDR3_SHIFT #undef DDRC_MSTR_LPDDR3_MASK -#define DDRC_MSTR_LPDDR3_DEFVAL 0x03040001 -#define DDRC_MSTR_LPDDR3_SHIFT 3 -#define DDRC_MSTR_LPDDR3_MASK 0x00000008U +#define DDRC_MSTR_LPDDR3_DEFVAL 0x03040001 +#define DDRC_MSTR_LPDDR3_SHIFT 3 +#define DDRC_MSTR_LPDDR3_MASK 0x00000008U -/*Select LPDDR2 SDRAM - 1 - LPDDR2 SDRAM device in use. - 0 - non-LPDDR2 device in use Present only in designs configured to su - port LPDDR2.*/ +/* +* Select LPDDR2 SDRAM - 1 - LPDDR2 SDRAM device in use. - 0 - non-LPDDR2 d + * evice in use Present only in designs configured to support LPDDR2. +*/ #undef DDRC_MSTR_LPDDR2_DEFVAL #undef DDRC_MSTR_LPDDR2_SHIFT #undef DDRC_MSTR_LPDDR2_MASK -#define DDRC_MSTR_LPDDR2_DEFVAL 0x03040001 -#define DDRC_MSTR_LPDDR2_SHIFT 2 -#define DDRC_MSTR_LPDDR2_MASK 0x00000004U +#define DDRC_MSTR_LPDDR2_DEFVAL 0x03040001 +#define DDRC_MSTR_LPDDR2_SHIFT 2 +#define DDRC_MSTR_LPDDR2_MASK 0x00000004U -/*Select DDR3 SDRAM - 1 - DDR3 SDRAM device in use - 0 - non-DDR3 SDRAM device in use Only present in designs that support DDR3 - */ +/* +* Select DDR3 SDRAM - 1 - DDR3 SDRAM device in use - 0 - non-DDR3 SDRAM de + * vice in use Only present in designs that support DDR3. +*/ #undef DDRC_MSTR_DDR3_DEFVAL #undef DDRC_MSTR_DDR3_SHIFT #undef DDRC_MSTR_DDR3_MASK -#define DDRC_MSTR_DDR3_DEFVAL 0x03040001 -#define DDRC_MSTR_DDR3_SHIFT 0 -#define DDRC_MSTR_DDR3_MASK 0x00000001U +#define DDRC_MSTR_DDR3_DEFVAL 0x03040001 +#define DDRC_MSTR_DDR3_SHIFT 0 +#define DDRC_MSTR_DDR3_MASK 0x00000001U -/*Setting this register bit to 1 triggers a mode register read or write operation. When the MR operation is complete, the uMCTL - automatically clears this bit. The other register fields of this register must be written in a separate APB transaction, bef - re setting this mr_wr bit. It is recommended NOT to set this signal if in Init, Deep power-down or MPSM operating modes.*/ +/* +* Setting this register bit to 1 triggers a mode register read or write op + * eration. When the MR operation is complete, the uMCTL2 automatically cle + * ars this bit. The other register fields of this register must be written + * in a separate APB transaction, before setting this mr_wr bit. It is rec + * ommended NOT to set this signal if in Init, Deep power-down or MPSM oper + * ating modes. +*/ #undef DDRC_MRCTRL0_MR_WR_DEFVAL #undef DDRC_MRCTRL0_MR_WR_SHIFT #undef DDRC_MRCTRL0_MR_WR_MASK -#define DDRC_MRCTRL0_MR_WR_DEFVAL 0x00000030 -#define DDRC_MRCTRL0_MR_WR_SHIFT 31 -#define DDRC_MRCTRL0_MR_WR_MASK 0x80000000U +#define DDRC_MRCTRL0_MR_WR_DEFVAL 0x00000030 +#define DDRC_MRCTRL0_MR_WR_SHIFT 31 +#define DDRC_MRCTRL0_MR_WR_MASK 0x80000000U -/*Address of the mode register that is to be written to. - 0000 - MR0 - 0001 - MR1 - 0010 - MR2 - 0011 - MR3 - 0100 - MR4 - 010 - - MR5 - 0110 - MR6 - 0111 - MR7 Don't Care for LPDDR2/LPDDR3/LPDDR4 (see MRCTRL1.mr_data for mode register addressing in LPD - R2/LPDDR3/LPDDR4) This signal is also used for writing to control words of RDIMMs. In that case, it corresponds to the bank a - dress bits sent to the RDIMM In case of DDR4, the bit[3:2] corresponds to the bank group bits. Therefore, the bit[3] as well - s the bit[2:0] must be set to an appropriate value which is considered both the Address Mirroring of UDIMMs/RDIMMs and the Ou - put Inversion of RDIMMs.*/ +/* +* Address of the mode register that is to be written to. - 0000 - MR0 - 00 + * 01 - MR1 - 0010 - MR2 - 0011 - MR3 - 0100 - MR4 - 0101 - MR5 - 0110 - MR + * 6 - 0111 - MR7 Don't Care for LPDDR2/LPDDR3/LPDDR4 (see MRCTRL1.mr_data + * for mode register addressing in LPDDR2/LPDDR3/LPDDR4) This signal is als + * o used for writing to control words of RDIMMs. In that case, it correspo + * nds to the bank address bits sent to the RDIMM In case of DDR4, the bit[ + * 3:2] corresponds to the bank group bits. Therefore, the bit[3] as well a + * s the bit[2:0] must be set to an appropriate value which is considered b + * oth the Address Mirroring of UDIMMs/RDIMMs and the Output Inversion of R + * DIMMs. +*/ #undef DDRC_MRCTRL0_MR_ADDR_DEFVAL #undef DDRC_MRCTRL0_MR_ADDR_SHIFT #undef DDRC_MRCTRL0_MR_ADDR_MASK -#define DDRC_MRCTRL0_MR_ADDR_DEFVAL 0x00000030 -#define DDRC_MRCTRL0_MR_ADDR_SHIFT 12 -#define DDRC_MRCTRL0_MR_ADDR_MASK 0x0000F000U +#define DDRC_MRCTRL0_MR_ADDR_DEFVAL 0x00000030 +#define DDRC_MRCTRL0_MR_ADDR_SHIFT 12 +#define DDRC_MRCTRL0_MR_ADDR_MASK 0x0000F000U -/*Controls which rank is accessed by MRCTRL0.mr_wr. Normally, it is desired to access all ranks, so all bits should be set to 1 - However, for multi-rank UDIMMs/RDIMMs which implement address mirroring, it may be necessary to access ranks individually. E - amples (assume uMCTL2 is configured for 4 ranks): - 0x1 - select rank 0 only - 0x2 - select rank 1 only - 0x5 - select ranks - and 2 - 0xA - select ranks 1 and 3 - 0xF - select ranks 0, 1, 2 and 3*/ +/* +* Controls which rank is accessed by MRCTRL0.mr_wr. Normally, it is desire + * d to access all ranks, so all bits should be set to 1. However, for mult + * i-rank UDIMMs/RDIMMs which implement address mirroring, it may be necess + * ary to access ranks individually. Examples (assume uMCTL2 is configured + * for 4 ranks): - 0x1 - select rank 0 only - 0x2 - select rank 1 only - 0x + * 5 - select ranks 0 and 2 - 0xA - select ranks 1 and 3 - 0xF - select ran + * ks 0, 1, 2 and 3 +*/ #undef DDRC_MRCTRL0_MR_RANK_DEFVAL #undef DDRC_MRCTRL0_MR_RANK_SHIFT #undef DDRC_MRCTRL0_MR_RANK_MASK -#define DDRC_MRCTRL0_MR_RANK_DEFVAL 0x00000030 -#define DDRC_MRCTRL0_MR_RANK_SHIFT 4 -#define DDRC_MRCTRL0_MR_RANK_MASK 0x00000030U +#define DDRC_MRCTRL0_MR_RANK_DEFVAL 0x00000030 +#define DDRC_MRCTRL0_MR_RANK_SHIFT 4 +#define DDRC_MRCTRL0_MR_RANK_MASK 0x00000030U -/*Indicates whether Software intervention is allowed via MRCTRL0/MRCTRL1 before automatic SDRAM initialization routine or not. - or DDR4, this bit can be used to initialize the DDR4 RCD (MR7) before automatic SDRAM initialization. For LPDDR4, this bit ca - be used to program additional mode registers before automatic SDRAM initialization if necessary. Note: This must be cleared - o 0 after completing Software operation. Otherwise, SDRAM initialization routine will not re-start. - 0 - Software interventi - n is not allowed - 1 - Software intervention is allowed*/ +/* +* Indicates whether Software intervention is allowed via MRCTRL0/MRCTRL1 b + * efore automatic SDRAM initialization routine or not. For DDR4, this bit + * can be used to initialize the DDR4 RCD (MR7) before automatic SDRAM init + * ialization. For LPDDR4, this bit can be used to program additional mode + * registers before automatic SDRAM initialization if necessary. Note: This + * must be cleared to 0 after completing Software operation. Otherwise, SD + * RAM initialization routine will not re-start. - 0 - Software interventio + * n is not allowed - 1 - Software intervention is allowed +*/ #undef DDRC_MRCTRL0_SW_INIT_INT_DEFVAL #undef DDRC_MRCTRL0_SW_INIT_INT_SHIFT #undef DDRC_MRCTRL0_SW_INIT_INT_MASK -#define DDRC_MRCTRL0_SW_INIT_INT_DEFVAL 0x00000030 -#define DDRC_MRCTRL0_SW_INIT_INT_SHIFT 3 -#define DDRC_MRCTRL0_SW_INIT_INT_MASK 0x00000008U +#define DDRC_MRCTRL0_SW_INIT_INT_DEFVAL 0x00000030 +#define DDRC_MRCTRL0_SW_INIT_INT_SHIFT 3 +#define DDRC_MRCTRL0_SW_INIT_INT_MASK 0x00000008U -/*Indicates whether the mode register operation is MRS in PDA mode or not - 0 - MRS - 1 - MRS in Per DRAM Addressability mode*/ +/* +* Indicates whether the mode register operation is MRS in PDA mode or not + * - 0 - MRS - 1 - MRS in Per DRAM Addressability mode +*/ #undef DDRC_MRCTRL0_PDA_EN_DEFVAL #undef DDRC_MRCTRL0_PDA_EN_SHIFT #undef DDRC_MRCTRL0_PDA_EN_MASK -#define DDRC_MRCTRL0_PDA_EN_DEFVAL 0x00000030 -#define DDRC_MRCTRL0_PDA_EN_SHIFT 2 -#define DDRC_MRCTRL0_PDA_EN_MASK 0x00000004U +#define DDRC_MRCTRL0_PDA_EN_DEFVAL 0x00000030 +#define DDRC_MRCTRL0_PDA_EN_SHIFT 2 +#define DDRC_MRCTRL0_PDA_EN_MASK 0x00000004U -/*Indicates whether the mode register operation is MRS or WR/RD for MPR (only supported for DDR4) - 0 - MRS - 1 - WR/RD for MPR*/ +/* +* Indicates whether the mode register operation is MRS or WR/RD for MPR (o + * nly supported for DDR4) - 0 - MRS - 1 - WR/RD for MPR +*/ #undef DDRC_MRCTRL0_MPR_EN_DEFVAL #undef DDRC_MRCTRL0_MPR_EN_SHIFT #undef DDRC_MRCTRL0_MPR_EN_MASK -#define DDRC_MRCTRL0_MPR_EN_DEFVAL 0x00000030 -#define DDRC_MRCTRL0_MPR_EN_SHIFT 1 -#define DDRC_MRCTRL0_MPR_EN_MASK 0x00000002U +#define DDRC_MRCTRL0_MPR_EN_DEFVAL 0x00000030 +#define DDRC_MRCTRL0_MPR_EN_SHIFT 1 +#define DDRC_MRCTRL0_MPR_EN_MASK 0x00000002U -/*Indicates whether the mode register operation is read or write. Only used for LPDDR2/LPDDR3/LPDDR4/DDR4. - 0 - Write - 1 - Re - d*/ +/* +* Indicates whether the mode register operation is read or write. Only use + * d for LPDDR2/LPDDR3/LPDDR4/DDR4. - 0 - Write - 1 - Read +*/ #undef DDRC_MRCTRL0_MR_TYPE_DEFVAL #undef DDRC_MRCTRL0_MR_TYPE_SHIFT #undef DDRC_MRCTRL0_MR_TYPE_MASK -#define DDRC_MRCTRL0_MR_TYPE_DEFVAL 0x00000030 -#define DDRC_MRCTRL0_MR_TYPE_SHIFT 0 -#define DDRC_MRCTRL0_MR_TYPE_MASK 0x00000001U +#define DDRC_MRCTRL0_MR_TYPE_DEFVAL 0x00000030 +#define DDRC_MRCTRL0_MR_TYPE_SHIFT 0 +#define DDRC_MRCTRL0_MR_TYPE_MASK 0x00000001U -/*Derate value of tRC for LPDDR4 - 0 - Derating uses +1. - 1 - Derating uses +2. - 2 - Derating uses +3. - 3 - Derating uses +4 - Present only in designs configured to support LPDDR4. The required number of cycles for derating can be determined by dividi - g 3.75ns by the core_ddrc_core_clk period, and rounding up the next integer.*/ +/* +* Derate value of tRC for LPDDR4 - 0 - Derating uses +1. - 1 - Derating us + * es +2. - 2 - Derating uses +3. - 3 - Derating uses +4. Present only in d + * esigns configured to support LPDDR4. The required number of cycles for d + * erating can be determined by dividing 3.75ns by the core_ddrc_core_clk p + * eriod, and rounding up the next integer. +*/ #undef DDRC_DERATEEN_RC_DERATE_VALUE_DEFVAL #undef DDRC_DERATEEN_RC_DERATE_VALUE_SHIFT #undef DDRC_DERATEEN_RC_DERATE_VALUE_MASK -#define DDRC_DERATEEN_RC_DERATE_VALUE_DEFVAL 0x00000000 -#define DDRC_DERATEEN_RC_DERATE_VALUE_SHIFT 8 -#define DDRC_DERATEEN_RC_DERATE_VALUE_MASK 0x00000300U +#define DDRC_DERATEEN_RC_DERATE_VALUE_DEFVAL 0x00000000 +#define DDRC_DERATEEN_RC_DERATE_VALUE_SHIFT 8 +#define DDRC_DERATEEN_RC_DERATE_VALUE_MASK 0x00000300U -/*Derate byte Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4 Indicates which byte of the MRR data is used f - r derating. The maximum valid value depends on MEMC_DRAM_TOTAL_DATA_WIDTH.*/ +/* +* Derate byte Present only in designs configured to support LPDDR2/LPDDR3/ + * LPDDR4 Indicates which byte of the MRR data is used for derating. The ma + * ximum valid value depends on MEMC_DRAM_TOTAL_DATA_WIDTH. +*/ #undef DDRC_DERATEEN_DERATE_BYTE_DEFVAL #undef DDRC_DERATEEN_DERATE_BYTE_SHIFT #undef DDRC_DERATEEN_DERATE_BYTE_MASK -#define DDRC_DERATEEN_DERATE_BYTE_DEFVAL 0x00000000 -#define DDRC_DERATEEN_DERATE_BYTE_SHIFT 4 -#define DDRC_DERATEEN_DERATE_BYTE_MASK 0x000000F0U +#define DDRC_DERATEEN_DERATE_BYTE_DEFVAL 0x00000000 +#define DDRC_DERATEEN_DERATE_BYTE_SHIFT 4 +#define DDRC_DERATEEN_DERATE_BYTE_MASK 0x000000F0U -/*Derate value - 0 - Derating uses +1. - 1 - Derating uses +2. Present only in designs configured to support LPDDR2/LPDDR3/LPDD - 4 Set to 0 for all LPDDR2 speed grades as derating value of +1.875 ns is less than a core_ddrc_core_clk period. Can be 0 or 1 - for LPDDR3/LPDDR4, depending if +1.875 ns is less than a core_ddrc_core_clk period or not.*/ +/* +* Derate value - 0 - Derating uses +1. - 1 - Derating uses +2. Present onl + * y in designs configured to support LPDDR2/LPDDR3/LPDDR4 Set to 0 for all + * LPDDR2 speed grades as derating value of +1.875 ns is less than a core_ + * ddrc_core_clk period. Can be 0 or 1 for LPDDR3/LPDDR4, depending if +1.8 + * 75 ns is less than a core_ddrc_core_clk period or not. +*/ #undef DDRC_DERATEEN_DERATE_VALUE_DEFVAL #undef DDRC_DERATEEN_DERATE_VALUE_SHIFT #undef DDRC_DERATEEN_DERATE_VALUE_MASK -#define DDRC_DERATEEN_DERATE_VALUE_DEFVAL 0x00000000 -#define DDRC_DERATEEN_DERATE_VALUE_SHIFT 1 -#define DDRC_DERATEEN_DERATE_VALUE_MASK 0x00000002U +#define DDRC_DERATEEN_DERATE_VALUE_DEFVAL 0x00000000 +#define DDRC_DERATEEN_DERATE_VALUE_SHIFT 1 +#define DDRC_DERATEEN_DERATE_VALUE_MASK 0x00000002U -/*Enables derating - 0 - Timing parameter derating is disabled - 1 - Timing parameter derating is enabled using MR4 read value. - Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4 This field must be set to '0' for non-LPDDR2/LPDDR3/LPDDR4 - mode.*/ +/* +* Enables derating - 0 - Timing parameter derating is disabled - 1 - Timin + * g parameter derating is enabled using MR4 read value. Present only in de + * signs configured to support LPDDR2/LPDDR3/LPDDR4 This field must be set + * to '0' for non-LPDDR2/LPDDR3/LPDDR4 mode. +*/ #undef DDRC_DERATEEN_DERATE_ENABLE_DEFVAL #undef DDRC_DERATEEN_DERATE_ENABLE_SHIFT #undef DDRC_DERATEEN_DERATE_ENABLE_MASK -#define DDRC_DERATEEN_DERATE_ENABLE_DEFVAL 0x00000000 -#define DDRC_DERATEEN_DERATE_ENABLE_SHIFT 0 -#define DDRC_DERATEEN_DERATE_ENABLE_MASK 0x00000001U +#define DDRC_DERATEEN_DERATE_ENABLE_DEFVAL 0x00000000 +#define DDRC_DERATEEN_DERATE_ENABLE_SHIFT 0 +#define DDRC_DERATEEN_DERATE_ENABLE_MASK 0x00000001U -/*Interval between two MR4 reads, used to derate the timing parameters. Present only in designs configured to support LPDDR2/LP - DR3/LPDDR4. This register must not be set to zero*/ +/* +* Interval between two MR4 reads, used to derate the timing parameters. Pr + * esent only in designs configured to support LPDDR2/LPDDR3/LPDDR4. This r + * egister must not be set to zero +*/ #undef DDRC_DERATEINT_MR4_READ_INTERVAL_DEFVAL #undef DDRC_DERATEINT_MR4_READ_INTERVAL_SHIFT #undef DDRC_DERATEINT_MR4_READ_INTERVAL_MASK -#define DDRC_DERATEINT_MR4_READ_INTERVAL_DEFVAL -#define DDRC_DERATEINT_MR4_READ_INTERVAL_SHIFT 0 -#define DDRC_DERATEINT_MR4_READ_INTERVAL_MASK 0xFFFFFFFFU +#define DDRC_DERATEINT_MR4_READ_INTERVAL_DEFVAL +#define DDRC_DERATEINT_MR4_READ_INTERVAL_SHIFT 0 +#define DDRC_DERATEINT_MR4_READ_INTERVAL_MASK 0xFFFFFFFFU -/*Self refresh state is an intermediate state to enter to Self refresh power down state or exit Self refresh power down state f - r LPDDR4. This register controls transition from the Self refresh state. - 1 - Prohibit transition from Self refresh state - - - Allow transition from Self refresh state*/ +/* +* Self refresh state is an intermediate state to enter to Self refresh pow + * er down state or exit Self refresh power down state for LPDDR4. This reg + * ister controls transition from the Self refresh state. - 1 - Prohibit tr + * ansition from Self refresh state - 0 - Allow transition from Self refres + * h state +*/ #undef DDRC_PWRCTL_STAY_IN_SELFREF_DEFVAL #undef DDRC_PWRCTL_STAY_IN_SELFREF_SHIFT #undef DDRC_PWRCTL_STAY_IN_SELFREF_MASK -#define DDRC_PWRCTL_STAY_IN_SELFREF_DEFVAL 0x00000000 -#define DDRC_PWRCTL_STAY_IN_SELFREF_SHIFT 6 -#define DDRC_PWRCTL_STAY_IN_SELFREF_MASK 0x00000040U +#define DDRC_PWRCTL_STAY_IN_SELFREF_DEFVAL 0x00000000 +#define DDRC_PWRCTL_STAY_IN_SELFREF_SHIFT 6 +#define DDRC_PWRCTL_STAY_IN_SELFREF_MASK 0x00000040U -/*A value of 1 to this register causes system to move to Self Refresh state immediately, as long as it is not in INIT or DPD/MP - M operating_mode. This is referred to as Software Entry/Exit to Self Refresh. - 1 - Software Entry to Self Refresh - 0 - Soft - are Exit from Self Refresh*/ +/* +* A value of 1 to this register causes system to move to Self Refresh stat + * e immediately, as long as it is not in INIT or DPD/MPSM operating_mode. + * This is referred to as Software Entry/Exit to Self Refresh. - 1 - Softwa + * re Entry to Self Refresh - 0 - Software Exit from Self Refresh +*/ #undef DDRC_PWRCTL_SELFREF_SW_DEFVAL #undef DDRC_PWRCTL_SELFREF_SW_SHIFT #undef DDRC_PWRCTL_SELFREF_SW_MASK -#define DDRC_PWRCTL_SELFREF_SW_DEFVAL 0x00000000 -#define DDRC_PWRCTL_SELFREF_SW_SHIFT 5 -#define DDRC_PWRCTL_SELFREF_SW_MASK 0x00000020U +#define DDRC_PWRCTL_SELFREF_SW_DEFVAL 0x00000000 +#define DDRC_PWRCTL_SELFREF_SW_SHIFT 5 +#define DDRC_PWRCTL_SELFREF_SW_MASK 0x00000020U -/*When this is 1, the uMCTL2 puts the SDRAM into maximum power saving mode when the transaction store is empty. This register m - st be reset to '0' to bring uMCTL2 out of maximum power saving mode. Present only in designs configured to support DDR4. For - on-DDR4, this register should not be set to 1. Note that MPSM is not supported when using a DWC DDR PHY, if the PHY parameter - DWC_AC_CS_USE is disabled, as the MPSM exit sequence requires the chip-select signal to toggle. FOR PERFORMANCE ONLY.*/ +/* +* When this is 1, the uMCTL2 puts the SDRAM into maximum power saving mode + * when the transaction store is empty. This register must be reset to '0' + * to bring uMCTL2 out of maximum power saving mode. Present only in desig + * ns configured to support DDR4. For non-DDR4, this register should not be + * set to 1. Note that MPSM is not supported when using a DWC DDR PHY, if + * the PHY parameter DWC_AC_CS_USE is disabled, as the MPSM exit sequence r + * equires the chip-select signal to toggle. FOR PERFORMANCE ONLY. +*/ #undef DDRC_PWRCTL_MPSM_EN_DEFVAL #undef DDRC_PWRCTL_MPSM_EN_SHIFT #undef DDRC_PWRCTL_MPSM_EN_MASK -#define DDRC_PWRCTL_MPSM_EN_DEFVAL 0x00000000 -#define DDRC_PWRCTL_MPSM_EN_SHIFT 4 -#define DDRC_PWRCTL_MPSM_EN_MASK 0x00000010U +#define DDRC_PWRCTL_MPSM_EN_DEFVAL 0x00000000 +#define DDRC_PWRCTL_MPSM_EN_SHIFT 4 +#define DDRC_PWRCTL_MPSM_EN_MASK 0x00000010U -/*Enable the assertion of dfi_dram_clk_disable whenever a clock is not required by the SDRAM. If set to 0, dfi_dram_clk_disable - is never asserted. Assertion of dfi_dram_clk_disable is as follows: In DDR2/DDR3, can only be asserted in Self Refresh. In DD - 4, can be asserted in following: - in Self Refresh. - in Maximum Power Saving Mode In mDDR/LPDDR2/LPDDR3, can be asserted in - ollowing: - in Self Refresh - in Power Down - in Deep Power Down - during Normal operation (Clock Stop) In LPDDR4, can be ass - rted in following: - in Self Refresh Power Down - in Power Down - during Normal operation (Clock Stop)*/ +/* +* Enable the assertion of dfi_dram_clk_disable whenever a clock is not req + * uired by the SDRAM. If set to 0, dfi_dram_clk_disable is never asserted. + * Assertion of dfi_dram_clk_disable is as follows: In DDR2/DDR3, can only + * be asserted in Self Refresh. In DDR4, can be asserted in following: - i + * n Self Refresh. - in Maximum Power Saving Mode In mDDR/LPDDR2/LPDDR3, ca + * n be asserted in following: - in Self Refresh - in Power Down - in Deep + * Power Down - during Normal operation (Clock Stop) In LPDDR4, can be asse + * rted in following: - in Self Refresh Power Down - in Power Down - during + * Normal operation (Clock Stop) +*/ #undef DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_DEFVAL #undef DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_SHIFT #undef DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_MASK -#define DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_DEFVAL 0x00000000 -#define DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_SHIFT 3 -#define DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_MASK 0x00000008U +#define DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_DEFVAL 0x00000000 +#define DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_SHIFT 3 +#define DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_MASK 0x00000008U -/*When this is 1, uMCTL2 puts the SDRAM into deep power-down mode when the transaction store is empty. This register must be re - et to '0' to bring uMCTL2 out of deep power-down mode. Controller performs automatic SDRAM initialization on deep power-down - xit. Present only in designs configured to support mDDR or LPDDR2 or LPDDR3. For non-mDDR/non-LPDDR2/non-LPDDR3, this registe - should not be set to 1. FOR PERFORMANCE ONLY.*/ +/* +* When this is 1, uMCTL2 puts the SDRAM into deep power-down mode when the + * transaction store is empty. This register must be reset to '0' to bring + * uMCTL2 out of deep power-down mode. Controller performs automatic SDRAM + * initialization on deep power-down exit. Present only in designs configu + * red to support mDDR or LPDDR2 or LPDDR3. For non-mDDR/non-LPDDR2/non-LPD + * DR3, this register should not be set to 1. FOR PERFORMANCE ONLY. +*/ #undef DDRC_PWRCTL_DEEPPOWERDOWN_EN_DEFVAL #undef DDRC_PWRCTL_DEEPPOWERDOWN_EN_SHIFT #undef DDRC_PWRCTL_DEEPPOWERDOWN_EN_MASK -#define DDRC_PWRCTL_DEEPPOWERDOWN_EN_DEFVAL 0x00000000 -#define DDRC_PWRCTL_DEEPPOWERDOWN_EN_SHIFT 2 -#define DDRC_PWRCTL_DEEPPOWERDOWN_EN_MASK 0x00000004U +#define DDRC_PWRCTL_DEEPPOWERDOWN_EN_DEFVAL 0x00000000 +#define DDRC_PWRCTL_DEEPPOWERDOWN_EN_SHIFT 2 +#define DDRC_PWRCTL_DEEPPOWERDOWN_EN_MASK 0x00000004U -/*If true then the uMCTL2 goes into power-down after a programmable number of cycles 'maximum idle clocks before power down' (P - RTMG.powerdown_to_x32). This register bit may be re-programmed during the course of normal operation.*/ +/* +* If true then the uMCTL2 goes into power-down after a programmable number + * of cycles 'maximum idle clocks before power down' (PWRTMG.powerdown_to_ + * x32). This register bit may be re-programmed during the course of normal + * operation. +*/ #undef DDRC_PWRCTL_POWERDOWN_EN_DEFVAL #undef DDRC_PWRCTL_POWERDOWN_EN_SHIFT #undef DDRC_PWRCTL_POWERDOWN_EN_MASK -#define DDRC_PWRCTL_POWERDOWN_EN_DEFVAL 0x00000000 -#define DDRC_PWRCTL_POWERDOWN_EN_SHIFT 1 -#define DDRC_PWRCTL_POWERDOWN_EN_MASK 0x00000002U +#define DDRC_PWRCTL_POWERDOWN_EN_DEFVAL 0x00000000 +#define DDRC_PWRCTL_POWERDOWN_EN_SHIFT 1 +#define DDRC_PWRCTL_POWERDOWN_EN_MASK 0x00000002U -/*If true then the uMCTL2 puts the SDRAM into Self Refresh after a programmable number of cycles 'maximum idle clocks before Se - f Refresh (PWRTMG.selfref_to_x32)'. This register bit may be re-programmed during the course of normal operation.*/ +/* +* If true then the uMCTL2 puts the SDRAM into Self Refresh after a program + * mable number of cycles 'maximum idle clocks before Self Refresh (PWRTMG. + * selfref_to_x32)'. This register bit may be re-programmed during the cour + * se of normal operation. +*/ #undef DDRC_PWRCTL_SELFREF_EN_DEFVAL #undef DDRC_PWRCTL_SELFREF_EN_SHIFT #undef DDRC_PWRCTL_SELFREF_EN_MASK -#define DDRC_PWRCTL_SELFREF_EN_DEFVAL 0x00000000 -#define DDRC_PWRCTL_SELFREF_EN_SHIFT 0 -#define DDRC_PWRCTL_SELFREF_EN_MASK 0x00000001U +#define DDRC_PWRCTL_SELFREF_EN_DEFVAL 0x00000000 +#define DDRC_PWRCTL_SELFREF_EN_SHIFT 0 +#define DDRC_PWRCTL_SELFREF_EN_MASK 0x00000001U -/*After this many clocks of NOP or deselect the uMCTL2 automatically puts the SDRAM into Self Refresh. This must be enabled in - he PWRCTL.selfref_en. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY.*/ +/* +* After this many clocks of NOP or deselect the uMCTL2 automatically puts + * the SDRAM into Self Refresh. This must be enabled in the PWRCTL.selfref_ + * en. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY. +*/ #undef DDRC_PWRTMG_SELFREF_TO_X32_DEFVAL #undef DDRC_PWRTMG_SELFREF_TO_X32_SHIFT #undef DDRC_PWRTMG_SELFREF_TO_X32_MASK -#define DDRC_PWRTMG_SELFREF_TO_X32_DEFVAL 0x00402010 -#define DDRC_PWRTMG_SELFREF_TO_X32_SHIFT 16 -#define DDRC_PWRTMG_SELFREF_TO_X32_MASK 0x00FF0000U +#define DDRC_PWRTMG_SELFREF_TO_X32_DEFVAL 0x00402010 +#define DDRC_PWRTMG_SELFREF_TO_X32_SHIFT 16 +#define DDRC_PWRTMG_SELFREF_TO_X32_MASK 0x00FF0000U -/*Minimum deep power-down time. For mDDR, value from the JEDEC specification is 0 as mDDR exits from deep power-down mode immed - ately after PWRCTL.deeppowerdown_en is de-asserted. For LPDDR2/LPDDR3, value from the JEDEC specification is 500us. Unit: Mul - iples of 4096 clocks. Present only in designs configured to support mDDR, LPDDR2 or LPDDR3. FOR PERFORMANCE ONLY.*/ +/* +* Minimum deep power-down time. For mDDR, value from the JEDEC specificati + * on is 0 as mDDR exits from deep power-down mode immediately after PWRCTL + * .deeppowerdown_en is de-asserted. For LPDDR2/LPDDR3, value from the JEDE + * C specification is 500us. Unit: Multiples of 4096 clocks. Present only i + * n designs configured to support mDDR, LPDDR2 or LPDDR3. FOR PERFORMANCE + * ONLY. +*/ #undef DDRC_PWRTMG_T_DPD_X4096_DEFVAL #undef DDRC_PWRTMG_T_DPD_X4096_SHIFT #undef DDRC_PWRTMG_T_DPD_X4096_MASK -#define DDRC_PWRTMG_T_DPD_X4096_DEFVAL 0x00402010 -#define DDRC_PWRTMG_T_DPD_X4096_SHIFT 8 -#define DDRC_PWRTMG_T_DPD_X4096_MASK 0x0000FF00U +#define DDRC_PWRTMG_T_DPD_X4096_DEFVAL 0x00402010 +#define DDRC_PWRTMG_T_DPD_X4096_SHIFT 8 +#define DDRC_PWRTMG_T_DPD_X4096_MASK 0x0000FF00U -/*After this many clocks of NOP or deselect the uMCTL2 automatically puts the SDRAM into power-down. This must be enabled in th - PWRCTL.powerdown_en. Unit: Multiples of 32 clocks FOR PERFORMANCE ONLY.*/ +/* +* After this many clocks of NOP or deselect the uMCTL2 automatically puts + * the SDRAM into power-down. This must be enabled in the PWRCTL.powerdown_ + * en. Unit: Multiples of 32 clocks FOR PERFORMANCE ONLY. +*/ #undef DDRC_PWRTMG_POWERDOWN_TO_X32_DEFVAL #undef DDRC_PWRTMG_POWERDOWN_TO_X32_SHIFT #undef DDRC_PWRTMG_POWERDOWN_TO_X32_MASK -#define DDRC_PWRTMG_POWERDOWN_TO_X32_DEFVAL 0x00402010 -#define DDRC_PWRTMG_POWERDOWN_TO_X32_SHIFT 0 -#define DDRC_PWRTMG_POWERDOWN_TO_X32_MASK 0x0000001FU +#define DDRC_PWRTMG_POWERDOWN_TO_X32_DEFVAL 0x00402010 +#define DDRC_PWRTMG_POWERDOWN_TO_X32_SHIFT 0 +#define DDRC_PWRTMG_POWERDOWN_TO_X32_MASK 0x0000001FU -/*Threshold value in number of clock cycles before the critical refresh or page timer expires. A critical refresh is to be issu - d before this threshold is reached. It is recommended that this not be changed from the default value, currently shown as 0x2 - It must always be less than internally used t_rfc_nom_x32. Note that, in LPDDR2/LPDDR3/LPDDR4, internally used t_rfc_nom_x32 - may be equal to RFSHTMG.t_rfc_nom_x32>>2 if derating is enabled (DERATEEN.derate_enable=1). Otherwise, internally used t_rfc_ - om_x32 will be equal to RFSHTMG.t_rfc_nom_x32. Unit: Multiples of 32 clocks.*/ +/* +* Threshold value in number of clock cycles before the critical refresh or + * page timer expires. A critical refresh is to be issued before this thre + * shold is reached. It is recommended that this not be changed from the de + * fault value, currently shown as 0x2. It must always be less than interna + * lly used t_rfc_nom_x32. Note that, in LPDDR2/LPDDR3/LPDDR4, internally u + * sed t_rfc_nom_x32 may be equal to RFSHTMG.t_rfc_nom_x32>>2 if derating i + * s enabled (DERATEEN.derate_enable=1). Otherwise, internally used t_rfc_n + * om_x32 will be equal to RFSHTMG.t_rfc_nom_x32. Unit: Multiples of 32 clo + * cks. +*/ #undef DDRC_RFSHCTL0_REFRESH_MARGIN_DEFVAL #undef DDRC_RFSHCTL0_REFRESH_MARGIN_SHIFT #undef DDRC_RFSHCTL0_REFRESH_MARGIN_MASK -#define DDRC_RFSHCTL0_REFRESH_MARGIN_DEFVAL 0x00210000 -#define DDRC_RFSHCTL0_REFRESH_MARGIN_SHIFT 20 -#define DDRC_RFSHCTL0_REFRESH_MARGIN_MASK 0x00F00000U +#define DDRC_RFSHCTL0_REFRESH_MARGIN_DEFVAL 0x00210000 +#define DDRC_RFSHCTL0_REFRESH_MARGIN_SHIFT 20 +#define DDRC_RFSHCTL0_REFRESH_MARGIN_MASK 0x00F00000U -/*If the refresh timer (tRFCnom, also known as tREFI) has expired at least once, but it has not expired (RFSHCTL0.refresh_burst - 1) times yet, then a speculative refresh may be performed. A speculative refresh is a refresh performed at a time when refres - would be useful, but before it is absolutely required. When the SDRAM bus is idle for a period of time determined by this RF - HCTL0.refresh_to_x32 and the refresh timer has expired at least once since the last refresh, then a speculative refresh is pe - formed. Speculative refreshes continues successively until there are no refreshes pending or until new reads or writes are is - ued to the uMCTL2. FOR PERFORMANCE ONLY.*/ +/* +* If the refresh timer (tRFCnom, also known as tREFI) has expired at least + * once, but it has not expired (RFSHCTL0.refresh_burst+1) times yet, then + * a speculative refresh may be performed. A speculative refresh is a refr + * esh performed at a time when refresh would be useful, but before it is a + * bsolutely required. When the SDRAM bus is idle for a period of time dete + * rmined by this RFSHCTL0.refresh_to_x32 and the refresh timer has expired + * at least once since the last refresh, then a speculative refresh is per + * formed. Speculative refreshes continues successively until there are no + * refreshes pending or until new reads or writes are issued to the uMCTL2. + * FOR PERFORMANCE ONLY. +*/ #undef DDRC_RFSHCTL0_REFRESH_TO_X32_DEFVAL #undef DDRC_RFSHCTL0_REFRESH_TO_X32_SHIFT #undef DDRC_RFSHCTL0_REFRESH_TO_X32_MASK -#define DDRC_RFSHCTL0_REFRESH_TO_X32_DEFVAL 0x00210000 -#define DDRC_RFSHCTL0_REFRESH_TO_X32_SHIFT 12 -#define DDRC_RFSHCTL0_REFRESH_TO_X32_MASK 0x0001F000U +#define DDRC_RFSHCTL0_REFRESH_TO_X32_DEFVAL 0x00210000 +#define DDRC_RFSHCTL0_REFRESH_TO_X32_SHIFT 12 +#define DDRC_RFSHCTL0_REFRESH_TO_X32_MASK 0x0001F000U -/*The programmed value + 1 is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the re - reshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of re - reshes. Therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for - RFSHCTL.refresh_burst slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshe - . - 0 - single refresh - 1 - burst-of-2 refresh - 7 - burst-of-8 refresh For information on burst refresh feature refer to se - tion 3.9 of DDR2 JEDEC specification - JESD79-2F.pdf. For DDR2/3, the refresh is always per-rank and not per-bank. The rank r - fresh can be accumulated over 8*tREFI cycles using the burst refresh feature. In DDR4 mode, according to Fine Granularity fea - ure, 8 refreshes can be postponed in 1X mode, 16 refreshes in 2X mode and 32 refreshes in 4X mode. If using PHY-initiated upd - tes, care must be taken in the setting of RFSHCTL0.refresh_burst, to ensure that tRFCmax is not violated due to a PHY-initiat - d update occurring shortly before a refresh burst was due. In this situation, the refresh burst will be delayed until the PHY - initiated update is complete.*/ +/* +* The programmed value + 1 is the number of refresh timeouts that is allow + * ed to accumulate before traffic is blocked and the refreshes are forced + * to execute. Closing pages to perform a refresh is a one-time penalty tha + * t must be paid for each group of refreshes. Therefore, performing refres + * hes in a burst reduces the per-refresh penalty of these page closings. H + * igher numbers for RFSHCTL.refresh_burst slightly increases utilization; + * lower numbers decreases the worst-case latency associated with refreshes + * . - 0 - single refresh - 1 - burst-of-2 refresh - 7 - burst-of-8 refresh + * For information on burst refresh feature refer to section 3.9 of DDR2 J + * EDEC specification - JESD79-2F.pdf. For DDR2/3, the refresh is always pe + * r-rank and not per-bank. The rank refresh can be accumulated over 8*tREF + * I cycles using the burst refresh feature. In DDR4 mode, according to Fin + * e Granularity feature, 8 refreshes can be postponed in 1X mode, 16 refre + * shes in 2X mode and 32 refreshes in 4X mode. If using PHY-initiated upda + * tes, care must be taken in the setting of RFSHCTL0.refresh_burst, to ens + * ure that tRFCmax is not violated due to a PHY-initiated update occurring + * shortly before a refresh burst was due. In this situation, the refresh + * burst will be delayed until the PHY-initiated update is complete. +*/ #undef DDRC_RFSHCTL0_REFRESH_BURST_DEFVAL #undef DDRC_RFSHCTL0_REFRESH_BURST_SHIFT #undef DDRC_RFSHCTL0_REFRESH_BURST_MASK -#define DDRC_RFSHCTL0_REFRESH_BURST_DEFVAL 0x00210000 -#define DDRC_RFSHCTL0_REFRESH_BURST_SHIFT 4 -#define DDRC_RFSHCTL0_REFRESH_BURST_MASK 0x000001F0U +#define DDRC_RFSHCTL0_REFRESH_BURST_DEFVAL 0x00210000 +#define DDRC_RFSHCTL0_REFRESH_BURST_SHIFT 4 +#define DDRC_RFSHCTL0_REFRESH_BURST_MASK 0x000001F0U -/*- 1 - Per bank refresh; - 0 - All bank refresh. Per bank refresh allows traffic to flow to other banks. Per bank refresh is n - t supported by all LPDDR2 devices but should be supported by all LPDDR3/LPDDR4 devices. Present only in designs configured to - support LPDDR2/LPDDR3/LPDDR4*/ +/* +* - 1 - Per bank refresh; - 0 - All bank refresh. Per bank refresh allows + * traffic to flow to other banks. Per bank refresh is not supported by all + * LPDDR2 devices but should be supported by all LPDDR3/LPDDR4 devices. Pr + * esent only in designs configured to support LPDDR2/LPDDR3/LPDDR4 +*/ #undef DDRC_RFSHCTL0_PER_BANK_REFRESH_DEFVAL #undef DDRC_RFSHCTL0_PER_BANK_REFRESH_SHIFT #undef DDRC_RFSHCTL0_PER_BANK_REFRESH_MASK -#define DDRC_RFSHCTL0_PER_BANK_REFRESH_DEFVAL 0x00210000 -#define DDRC_RFSHCTL0_PER_BANK_REFRESH_SHIFT 2 -#define DDRC_RFSHCTL0_PER_BANK_REFRESH_MASK 0x00000004U +#define DDRC_RFSHCTL0_PER_BANK_REFRESH_DEFVAL 0x00210000 +#define DDRC_RFSHCTL0_PER_BANK_REFRESH_SHIFT 2 +#define DDRC_RFSHCTL0_PER_BANK_REFRESH_MASK 0x00000004U -/*Fine Granularity Refresh Mode - 000 - Fixed 1x (Normal mode) - 001 - Fixed 2x - 010 - Fixed 4x - 101 - Enable on the fly 2x ( - ot supported) - 110 - Enable on the fly 4x (not supported) - Everything else - reserved Note: The on-the-fly modes is not sup - orted in this version of the uMCTL2. Note: This must be set up while the Controller is in reset or while the Controller is in - self-refresh mode. Changing this during normal operation is not allowed. Making this a dynamic register will be supported in - uture version of the uMCTL2.*/ +/* +* Refresh timer start for rank 1 (only present in multi-rank configuration + * s). This is useful in staggering the refreshes to multiple ranks to help + * traffic to proceed. This is explained in Refresh Controls section of ar + * chitecture chapter. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY. +*/ +#undef DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_DEFVAL +#undef DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_SHIFT +#undef DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_MASK +#define DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_DEFVAL 0x00000000 +#define DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_SHIFT 16 +#define DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_MASK 0x0FFF0000U + +/* +* Refresh timer start for rank 0 (only present in multi-rank configuration + * s). This is useful in staggering the refreshes to multiple ranks to help + * traffic to proceed. This is explained in Refresh Controls section of ar + * chitecture chapter. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY. +*/ +#undef DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_DEFVAL +#undef DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_SHIFT +#undef DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_MASK +#define DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_DEFVAL 0x00000000 +#define DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_SHIFT 0 +#define DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_MASK 0x00000FFFU + +/* +* Fine Granularity Refresh Mode - 000 - Fixed 1x (Normal mode) - 001 - Fix + * ed 2x - 010 - Fixed 4x - 101 - Enable on the fly 2x (not supported) - 11 + * 0 - Enable on the fly 4x (not supported) - Everything else - reserved No + * te: The on-the-fly modes is not supported in this version of the uMCTL2. + * Note: This must be set up while the Controller is in reset or while the + * Controller is in self-refresh mode. Changing this during normal operati + * on is not allowed. Making this a dynamic register will be supported in f + * uture version of the uMCTL2. +*/ #undef DDRC_RFSHCTL3_REFRESH_MODE_DEFVAL #undef DDRC_RFSHCTL3_REFRESH_MODE_SHIFT #undef DDRC_RFSHCTL3_REFRESH_MODE_MASK -#define DDRC_RFSHCTL3_REFRESH_MODE_DEFVAL 0x00000000 -#define DDRC_RFSHCTL3_REFRESH_MODE_SHIFT 4 -#define DDRC_RFSHCTL3_REFRESH_MODE_MASK 0x00000070U +#define DDRC_RFSHCTL3_REFRESH_MODE_DEFVAL 0x00000000 +#define DDRC_RFSHCTL3_REFRESH_MODE_SHIFT 4 +#define DDRC_RFSHCTL3_REFRESH_MODE_MASK 0x00000070U -/*Toggle this signal (either from 0 to 1 or from 1 to 0) to indicate that the refresh register(s) have been updated. The value - s automatically updated when exiting reset, so it does not need to be toggled initially.*/ +/* +* Toggle this signal (either from 0 to 1 or from 1 to 0) to indicate that + * the refresh register(s) have been updated. The value is automatically up + * dated when exiting reset, so it does not need to be toggled initially. +*/ #undef DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_DEFVAL #undef DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_SHIFT #undef DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_MASK -#define DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_DEFVAL 0x00000000 -#define DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_SHIFT 1 -#define DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_MASK 0x00000002U +#define DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_DEFVAL 0x00000000 +#define DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_SHIFT 1 +#define DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_MASK 0x00000002U -/*When '1', disable auto-refresh generated by the uMCTL2. When auto-refresh is disabled, the SoC core must generate refreshes u - ing the registers reg_ddrc_rank0_refresh, reg_ddrc_rank1_refresh, reg_ddrc_rank2_refresh and reg_ddrc_rank3_refresh. When dis - auto_refresh transitions from 0 to 1, any pending refreshes are immediately scheduled by the uMCTL2. If DDR4 CRC/parity retry - is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), disable auto-refresh is not supported, and this bit must be set to '0'. - his register field is changeable on the fly.*/ +/* +* When '1', disable auto-refresh generated by the uMCTL2. When auto-refres + * h is disabled, the SoC core must generate refreshes using the registers + * reg_ddrc_rank0_refresh, reg_ddrc_rank1_refresh, reg_ddrc_rank2_refresh a + * nd reg_ddrc_rank3_refresh. When dis_auto_refresh transitions from 0 to 1 + * , any pending refreshes are immediately scheduled by the uMCTL2. If DDR4 + * CRC/parity retry is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), d + * isable auto-refresh is not supported, and this bit must be set to '0'. T + * his register field is changeable on the fly. +*/ #undef DDRC_RFSHCTL3_DIS_AUTO_REFRESH_DEFVAL #undef DDRC_RFSHCTL3_DIS_AUTO_REFRESH_SHIFT #undef DDRC_RFSHCTL3_DIS_AUTO_REFRESH_MASK -#define DDRC_RFSHCTL3_DIS_AUTO_REFRESH_DEFVAL 0x00000000 -#define DDRC_RFSHCTL3_DIS_AUTO_REFRESH_SHIFT 0 -#define DDRC_RFSHCTL3_DIS_AUTO_REFRESH_MASK 0x00000001U +#define DDRC_RFSHCTL3_DIS_AUTO_REFRESH_DEFVAL 0x00000000 +#define DDRC_RFSHCTL3_DIS_AUTO_REFRESH_SHIFT 0 +#define DDRC_RFSHCTL3_DIS_AUTO_REFRESH_MASK 0x00000001U -/*tREFI: Average time interval between refreshes per rank (Specification: 7.8us for DDR2, DDR3 and DDR4. See JEDEC specificatio - for mDDR, LPDDR2, LPDDR3 and LPDDR4). For LPDDR2/LPDDR3/LPDDR4: - if using all-bank refreshes (RFSHCTL0.per_bank_refresh = 0 - , this register should be set to tREFIab - if using per-bank refreshes (RFSHCTL0.per_bank_refresh = 1), this register should - e set to tREFIpb For configurations with MEMC_FREQ_RATIO=2, program this to (tREFI/2), no rounding up. In DDR4 mode, tREFI va - ue is different depending on the refresh mode. The user should program the appropriate value from the spec based on the value - programmed in the refresh mode register. Note that RFSHTMG.t_rfc_nom_x32 * 32 must be greater than RFSHTMG.t_rfc_min, and RFS - TMG.t_rfc_nom_x32 must be greater than 0x1. Unit: Multiples of 32 clocks.*/ +/* +* tREFI: Average time interval between refreshes per rank (Specification: + * 7.8us for DDR2, DDR3 and DDR4. See JEDEC specification for mDDR, LPDDR2, + * LPDDR3 and LPDDR4). For LPDDR2/LPDDR3/LPDDR4: - if using all-bank refre + * shes (RFSHCTL0.per_bank_refresh = 0), this register should be set to tRE + * FIab - if using per-bank refreshes (RFSHCTL0.per_bank_refresh = 1), this + * register should be set to tREFIpb For configurations with MEMC_FREQ_RAT + * IO=2, program this to (tREFI/2), no rounding up. In DDR4 mode, tREFI val + * ue is different depending on the refresh mode. The user should program t + * he appropriate value from the spec based on the value programmed in the + * refresh mode register. Note that RFSHTMG.t_rfc_nom_x32 * 32 must be grea + * ter than RFSHTMG.t_rfc_min, and RFSHTMG.t_rfc_nom_x32 must be greater th + * an 0x1. Unit: Multiples of 32 clocks. +*/ #undef DDRC_RFSHTMG_T_RFC_NOM_X32_DEFVAL #undef DDRC_RFSHTMG_T_RFC_NOM_X32_SHIFT #undef DDRC_RFSHTMG_T_RFC_NOM_X32_MASK -#define DDRC_RFSHTMG_T_RFC_NOM_X32_DEFVAL 0x0062008C -#define DDRC_RFSHTMG_T_RFC_NOM_X32_SHIFT 16 -#define DDRC_RFSHTMG_T_RFC_NOM_X32_MASK 0x0FFF0000U +#define DDRC_RFSHTMG_T_RFC_NOM_X32_DEFVAL 0x0062008C +#define DDRC_RFSHTMG_T_RFC_NOM_X32_SHIFT 16 +#define DDRC_RFSHTMG_T_RFC_NOM_X32_MASK 0x0FFF0000U -/*Used only when LPDDR3 memory type is connected. Should only be changed when uMCTL2 is in reset. Specifies whether to use the - REFBW parameter (required by some LPDDR3 devices which comply with earlier versions of the LPDDR3 JEDEC specification) or not - - 0 - tREFBW parameter not used - 1 - tREFBW parameter used*/ +/* +* Used only when LPDDR3 memory type is connected. Should only be changed w + * hen uMCTL2 is in reset. Specifies whether to use the tREFBW parameter (r + * equired by some LPDDR3 devices which comply with earlier versions of the + * LPDDR3 JEDEC specification) or not: - 0 - tREFBW parameter not used - 1 + * - tREFBW parameter used +*/ #undef DDRC_RFSHTMG_LPDDR3_TREFBW_EN_DEFVAL #undef DDRC_RFSHTMG_LPDDR3_TREFBW_EN_SHIFT #undef DDRC_RFSHTMG_LPDDR3_TREFBW_EN_MASK -#define DDRC_RFSHTMG_LPDDR3_TREFBW_EN_DEFVAL 0x0062008C -#define DDRC_RFSHTMG_LPDDR3_TREFBW_EN_SHIFT 15 -#define DDRC_RFSHTMG_LPDDR3_TREFBW_EN_MASK 0x00008000U +#define DDRC_RFSHTMG_LPDDR3_TREFBW_EN_DEFVAL 0x0062008C +#define DDRC_RFSHTMG_LPDDR3_TREFBW_EN_SHIFT 15 +#define DDRC_RFSHTMG_LPDDR3_TREFBW_EN_MASK 0x00008000U -/*tRFC (min): Minimum time from refresh to refresh or activate. For MEMC_FREQ_RATIO=1 configurations, t_rfc_min should be set t - RoundUp(tRFCmin/tCK). For MEMC_FREQ_RATIO=2 configurations, t_rfc_min should be set to RoundUp(RoundUp(tRFCmin/tCK)/2). In L - DDR2/LPDDR3/LPDDR4 mode: - if using all-bank refreshes, the tRFCmin value in the above equations is equal to tRFCab - if usin - per-bank refreshes, the tRFCmin value in the above equations is equal to tRFCpb In DDR4 mode, the tRFCmin value in the above - equations is different depending on the refresh mode (fixed 1X,2X,4X) and the device density. The user should program the app - opriate value from the spec based on the 'refresh_mode' and the device density that is used. Unit: Clocks.*/ +/* +* tRFC (min): Minimum time from refresh to refresh or activate. For MEMC_F + * REQ_RATIO=1 configurations, t_rfc_min should be set to RoundUp(tRFCmin/t + * CK). For MEMC_FREQ_RATIO=2 configurations, t_rfc_min should be set to Ro + * undUp(RoundUp(tRFCmin/tCK)/2). In LPDDR2/LPDDR3/LPDDR4 mode: - if using + * all-bank refreshes, the tRFCmin value in the above equations is equal to + * tRFCab - if using per-bank refreshes, the tRFCmin value in the above eq + * uations is equal to tRFCpb In DDR4 mode, the tRFCmin value in the above + * equations is different depending on the refresh mode (fixed 1X,2X,4X) an + * d the device density. The user should program the appropriate value from + * the spec based on the 'refresh_mode' and the device density that is use + * d. Unit: Clocks. +*/ #undef DDRC_RFSHTMG_T_RFC_MIN_DEFVAL #undef DDRC_RFSHTMG_T_RFC_MIN_SHIFT #undef DDRC_RFSHTMG_T_RFC_MIN_MASK -#define DDRC_RFSHTMG_T_RFC_MIN_DEFVAL 0x0062008C -#define DDRC_RFSHTMG_T_RFC_MIN_SHIFT 0 -#define DDRC_RFSHTMG_T_RFC_MIN_MASK 0x000003FFU +#define DDRC_RFSHTMG_T_RFC_MIN_DEFVAL 0x0062008C +#define DDRC_RFSHTMG_T_RFC_MIN_SHIFT 0 +#define DDRC_RFSHTMG_T_RFC_MIN_MASK 0x000003FFU -/*Disable ECC scrubs. Valid only when ECCCFG0.ecc_mode = 3'b100 and MEMC_USE_RMW is defined*/ +/* +* Disable ECC scrubs. Valid only when ECCCFG0.ecc_mode = 3'b100 and MEMC_U + * SE_RMW is defined +*/ #undef DDRC_ECCCFG0_DIS_SCRUB_DEFVAL #undef DDRC_ECCCFG0_DIS_SCRUB_SHIFT #undef DDRC_ECCCFG0_DIS_SCRUB_MASK -#define DDRC_ECCCFG0_DIS_SCRUB_DEFVAL 0x00000000 -#define DDRC_ECCCFG0_DIS_SCRUB_SHIFT 4 -#define DDRC_ECCCFG0_DIS_SCRUB_MASK 0x00000010U +#define DDRC_ECCCFG0_DIS_SCRUB_DEFVAL 0x00000000 +#define DDRC_ECCCFG0_DIS_SCRUB_SHIFT 4 +#define DDRC_ECCCFG0_DIS_SCRUB_MASK 0x00000010U -/*ECC mode indicator - 000 - ECC disabled - 100 - ECC enabled - SEC/DED over 1 beat - all other settings are reserved for futur - use*/ +/* +* ECC mode indicator - 000 - ECC disabled - 100 - ECC enabled - SEC/DED ov + * er 1 beat - all other settings are reserved for future use +*/ #undef DDRC_ECCCFG0_ECC_MODE_DEFVAL #undef DDRC_ECCCFG0_ECC_MODE_SHIFT #undef DDRC_ECCCFG0_ECC_MODE_MASK -#define DDRC_ECCCFG0_ECC_MODE_DEFVAL 0x00000000 -#define DDRC_ECCCFG0_ECC_MODE_SHIFT 0 -#define DDRC_ECCCFG0_ECC_MODE_MASK 0x00000007U +#define DDRC_ECCCFG0_ECC_MODE_DEFVAL 0x00000000 +#define DDRC_ECCCFG0_ECC_MODE_SHIFT 0 +#define DDRC_ECCCFG0_ECC_MODE_MASK 0x00000007U -/*Selects whether to poison 1 or 2 bits - if 0 -> 2-bit (uncorrectable) data poisoning, if 1 -> 1-bit (correctable) data poison - ng, if ECCCFG1.data_poison_en=1*/ +/* +* Selects whether to poison 1 or 2 bits - if 0 -> 2-bit (uncorrectable) da + * ta poisoning, if 1 -> 1-bit (correctable) data poisoning, if ECCCFG1.dat + * a_poison_en=1 +*/ #undef DDRC_ECCCFG1_DATA_POISON_BIT_DEFVAL #undef DDRC_ECCCFG1_DATA_POISON_BIT_SHIFT #undef DDRC_ECCCFG1_DATA_POISON_BIT_MASK -#define DDRC_ECCCFG1_DATA_POISON_BIT_DEFVAL 0x00000000 -#define DDRC_ECCCFG1_DATA_POISON_BIT_SHIFT 1 -#define DDRC_ECCCFG1_DATA_POISON_BIT_MASK 0x00000002U +#define DDRC_ECCCFG1_DATA_POISON_BIT_DEFVAL 0x00000000 +#define DDRC_ECCCFG1_DATA_POISON_BIT_SHIFT 1 +#define DDRC_ECCCFG1_DATA_POISON_BIT_MASK 0x00000002U -/*Enable ECC data poisoning - introduces ECC errors on writes to address specified by the ECCPOISONADDR0/1 registers*/ +/* +* Enable ECC data poisoning - introduces ECC errors on writes to address s + * pecified by the ECCPOISONADDR0/1 registers +*/ #undef DDRC_ECCCFG1_DATA_POISON_EN_DEFVAL #undef DDRC_ECCCFG1_DATA_POISON_EN_SHIFT #undef DDRC_ECCCFG1_DATA_POISON_EN_MASK -#define DDRC_ECCCFG1_DATA_POISON_EN_DEFVAL 0x00000000 -#define DDRC_ECCCFG1_DATA_POISON_EN_SHIFT 0 -#define DDRC_ECCCFG1_DATA_POISON_EN_MASK 0x00000001U +#define DDRC_ECCCFG1_DATA_POISON_EN_DEFVAL 0x00000000 +#define DDRC_ECCCFG1_DATA_POISON_EN_SHIFT 0 +#define DDRC_ECCCFG1_DATA_POISON_EN_MASK 0x00000001U -/*The maximum number of DFI PHY clock cycles allowed from the assertion of the dfi_rddata_en signal to the assertion of each of - the corresponding bits of the dfi_rddata_valid signal. This corresponds to the DFI timing parameter tphy_rdlat. Refer to PHY - pecification for correct value. This value it only used for detecting read data timeout when DDR4 retry is enabled by CRCPARC - L1.crc_parity_retry_enable=1. Maximum supported value: - 1:1 Frequency mode : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_ - dlat < 'd114 - 1:2 Frequency mode ANDAND DFITMG0.dfi_rddata_use_sdr == 1 : CRCPARCTL1.dfi_t_phy_rdlat < 64 - 1:2 Frequency mo - e ANDAND DFITMG0.dfi_rddata_use_sdr == 0 : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_rdlat < 'd114 Unit: DFI Clocks*/ +/* +* The maximum number of DFI PHY clock cycles allowed from the assertion of + * the dfi_rddata_en signal to the assertion of each of the corresponding + * bits of the dfi_rddata_valid signal. This corresponds to the DFI timing + * parameter tphy_rdlat. Refer to PHY specification for correct value. This + * value it only used for detecting read data timeout when DDR4 retry is e + * nabled by CRCPARCTL1.crc_parity_retry_enable=1. Maximum supported value: + * - 1:1 Frequency mode : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_r + * dlat < 'd114 - 1:2 Frequency mode ANDAND DFITMG0.dfi_rddata_use_sdr == 1 + * : CRCPARCTL1.dfi_t_phy_rdlat < 64 - 1:2 Frequency mode ANDAND DFITMG0.d + * fi_rddata_use_sdr == 0 : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_ + * rdlat < 'd114 Unit: DFI Clocks +*/ #undef DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_DEFVAL #undef DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_SHIFT #undef DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_MASK -#define DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_DEFVAL 0x10000200 -#define DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_SHIFT 24 -#define DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_MASK 0x3F000000U +#define DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_DEFVAL 0x10000200 +#define DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_SHIFT 24 +#define DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_MASK 0x3F000000U -/*After a Parity or CRC error is flagged on dfi_alert_n signal, the software has an option to read the mode registers in the DR - M before the hardware begins the retry process - 1: Wait for software to read/write the mode registers before hardware begins - the retry. After software is done with its operations, it will clear the alert interrupt register bit - 0: Hardware can begin - the retry right away after the dfi_alert_n pulse goes away. The value on this register is valid only when retry is enabled (P - RCTRL.crc_parity_retry_enable = 1) If this register is set to 1 and if the software doesn't clear the interrupt register afte - handling the parity/CRC error, then the hardware will not begin the retry process and the system will hang. In the case of P - rity/CRC error, there are two possibilities when the software doesn't reset MR5[4] to 0. - (i) If 'Persistent parity' mode re - ister bit is NOT set: the commands sent during retry and normal operation are executed without parity checking. The value in - he Parity error log register MPR Page 1 is valid. - (ii) If 'Persistent parity' mode register bit is SET: Parity checking is - one for commands sent during retry and normal operation. If multiple errors occur before MR5[4] is cleared, the error log in - PR Page 1 should be treated as 'Don't care'.*/ +/* +* After a Parity or CRC error is flagged on dfi_alert_n signal, the softwa + * re has an option to read the mode registers in the DRAM before the hardw + * are begins the retry process - 1: Wait for software to read/write the mo + * de registers before hardware begins the retry. After software is done wi + * th its operations, it will clear the alert interrupt register bit - 0: H + * ardware can begin the retry right away after the dfi_alert_n pulse goes + * away. The value on this register is valid only when retry is enabled (PA + * RCTRL.crc_parity_retry_enable = 1) If this register is set to 1 and if t + * he software doesn't clear the interrupt register after handling the pari + * ty/CRC error, then the hardware will not begin the retry process and the + * system will hang. In the case of Parity/CRC error, there are two possib + * ilities when the software doesn't reset MR5[4] to 0. - (i) If 'Persisten + * t parity' mode register bit is NOT set: the commands sent during retry a + * nd normal operation are executed without parity checking. The value in t + * he Parity error log register MPR Page 1 is valid. - (ii) If 'Persistent + * parity' mode register bit is SET: Parity checking is done for commands s + * ent during retry and normal operation. If multiple errors occur before M + * R5[4] is cleared, the error log in MPR Page 1 should be treated as 'Don' + * t care'. +*/ #undef DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_DEFVAL #undef DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_SHIFT #undef DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_MASK -#define DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_DEFVAL 0x10000200 -#define DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_SHIFT 9 -#define DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_MASK 0x00000200U +#define DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_DEFVAL 0x10000200 +#define DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_SHIFT 9 +#define DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_MASK 0x00000200U -/*- 1: Enable command retry mechanism in case of C/A Parity or CRC error - 0: Disable command retry mechanism when C/A Parity o - CRC features are enabled. Note that retry functionality is not supported if burst chop is enabled (MSTR.burstchop = 1) and/o - disable auto-refresh is enabled (RFSHCTL3.dis_auto_refresh = 1)*/ +/* +* - 1: Enable command retry mechanism in case of C/A Parity or CRC error - + * 0: Disable command retry mechanism when C/A Parity or CRC features are + * enabled. Note that retry functionality is not supported if burst chop is + * enabled (MSTR.burstchop = 1) and/or disable auto-refresh is enabled (RF + * SHCTL3.dis_auto_refresh = 1) +*/ #undef DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_DEFVAL #undef DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_SHIFT #undef DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_MASK -#define DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_DEFVAL 0x10000200 -#define DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_SHIFT 8 -#define DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_MASK 0x00000100U +#define DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_DEFVAL 0x10000200 +#define DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_SHIFT 8 +#define DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_MASK 0x00000100U -/*CRC Calculation setting register - 1: CRC includes DM signal - 0: CRC not includes DM signal Present only in designs configur - d to support DDR4.*/ +/* +* CRC Calculation setting register - 1: CRC includes DM signal - 0: CRC no + * t includes DM signal Present only in designs configured to support DDR4. +*/ #undef DDRC_CRCPARCTL1_CRC_INC_DM_DEFVAL #undef DDRC_CRCPARCTL1_CRC_INC_DM_SHIFT #undef DDRC_CRCPARCTL1_CRC_INC_DM_MASK -#define DDRC_CRCPARCTL1_CRC_INC_DM_DEFVAL 0x10000200 -#define DDRC_CRCPARCTL1_CRC_INC_DM_SHIFT 7 -#define DDRC_CRCPARCTL1_CRC_INC_DM_MASK 0x00000080U +#define DDRC_CRCPARCTL1_CRC_INC_DM_DEFVAL 0x10000200 +#define DDRC_CRCPARCTL1_CRC_INC_DM_SHIFT 7 +#define DDRC_CRCPARCTL1_CRC_INC_DM_MASK 0x00000080U -/*CRC enable Register - 1: Enable generation of CRC - 0: Disable generation of CRC The setting of this register should match th - CRC mode register setting in the DRAM.*/ +/* +* CRC enable Register - 1: Enable generation of CRC - 0: Disable generatio + * n of CRC The setting of this register should match the CRC mode register + * setting in the DRAM. +*/ #undef DDRC_CRCPARCTL1_CRC_ENABLE_DEFVAL #undef DDRC_CRCPARCTL1_CRC_ENABLE_SHIFT #undef DDRC_CRCPARCTL1_CRC_ENABLE_MASK -#define DDRC_CRCPARCTL1_CRC_ENABLE_DEFVAL 0x10000200 -#define DDRC_CRCPARCTL1_CRC_ENABLE_SHIFT 4 -#define DDRC_CRCPARCTL1_CRC_ENABLE_MASK 0x00000010U +#define DDRC_CRCPARCTL1_CRC_ENABLE_DEFVAL 0x10000200 +#define DDRC_CRCPARCTL1_CRC_ENABLE_SHIFT 4 +#define DDRC_CRCPARCTL1_CRC_ENABLE_MASK 0x00000010U -/*C/A Parity enable register - 1: Enable generation of C/A parity and detection of C/A parity error - 0: Disable generation of - /A parity and disable detection of C/A parity error If RCD's parity error detection or SDRAM's parity detection is enabled, t - is register should be 1.*/ +/* +* C/A Parity enable register - 1: Enable generation of C/A parity and dete + * ction of C/A parity error - 0: Disable generation of C/A parity and disa + * ble detection of C/A parity error If RCD's parity error detection or SDR + * AM's parity detection is enabled, this register should be 1. +*/ #undef DDRC_CRCPARCTL1_PARITY_ENABLE_DEFVAL #undef DDRC_CRCPARCTL1_PARITY_ENABLE_SHIFT #undef DDRC_CRCPARCTL1_PARITY_ENABLE_MASK -#define DDRC_CRCPARCTL1_PARITY_ENABLE_DEFVAL 0x10000200 -#define DDRC_CRCPARCTL1_PARITY_ENABLE_SHIFT 0 -#define DDRC_CRCPARCTL1_PARITY_ENABLE_MASK 0x00000001U +#define DDRC_CRCPARCTL1_PARITY_ENABLE_DEFVAL 0x10000200 +#define DDRC_CRCPARCTL1_PARITY_ENABLE_SHIFT 0 +#define DDRC_CRCPARCTL1_PARITY_ENABLE_MASK 0x00000001U -/*Value from the DRAM spec indicating the maximum width of the dfi_alert_n pulse when a parity error occurs. Recommended values - - tPAR_ALERT_PW.MAX For configurations with MEMC_FREQ_RATIO=2, program this to tPAR_ALERT_PW.MAX/2 and round up to next inte - er value. Values of 0, 1 and 2 are illegal. This value must be greater than CRCPARCTL2.t_crc_alert_pw_max.*/ +/* +* Value from the DRAM spec indicating the maximum width of the dfi_alert_n + * pulse when a parity error occurs. Recommended values: - tPAR_ALERT_PW.M + * AX For configurations with MEMC_FREQ_RATIO=2, program this to tPAR_ALERT + * _PW.MAX/2 and round up to next integer value. Values of 0, 1 and 2 are i + * llegal. This value must be greater than CRCPARCTL2.t_crc_alert_pw_max. +*/ #undef DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_DEFVAL #undef DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_SHIFT #undef DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_MASK -#define DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_DEFVAL 0x0030050C -#define DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_SHIFT 16 -#define DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_MASK 0x01FF0000U +#define DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_DEFVAL 0x0030050C +#define DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_SHIFT 16 +#define DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_MASK 0x01FF0000U -/*Value from the DRAM spec indicating the maximum width of the dfi_alert_n pulse when a CRC error occurs. Recommended values: - - tCRC_ALERT_PW.MAX For configurations with MEMC_FREQ_RATIO=2, program this to tCRC_ALERT_PW.MAX/2 and round up to next integer - value. Values of 0, 1 and 2 are illegal. This value must be less than CRCPARCTL2.t_par_alert_pw_max.*/ +/* +* Value from the DRAM spec indicating the maximum width of the dfi_alert_n + * pulse when a CRC error occurs. Recommended values: - tCRC_ALERT_PW.MAX + * For configurations with MEMC_FREQ_RATIO=2, program this to tCRC_ALERT_PW + * .MAX/2 and round up to next integer value. Values of 0, 1 and 2 are ille + * gal. This value must be less than CRCPARCTL2.t_par_alert_pw_max. +*/ #undef DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_DEFVAL #undef DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_SHIFT #undef DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_MASK -#define DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_DEFVAL 0x0030050C -#define DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_SHIFT 8 -#define DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_MASK 0x00001F00U +#define DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_DEFVAL 0x0030050C +#define DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_SHIFT 8 +#define DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_MASK 0x00001F00U -/*Indicates the maximum duration in number of DRAM clock cycles for which a command should be held in the Command Retry FIFO be - ore it is popped out. Every location in the Command Retry FIFO has an associated down counting timer that will use this regis - er as the start value. The down counting starts when a command is loaded into the FIFO. The timer counts down every 4 DRAM cy - les. When the counter reaches zero, the entry is popped from the FIFO. All the counters are frozen, if a C/A Parity or CRC er - or occurs before the counter reaches zero. The counter is reset to 0, after all the commands in the FIFO are retried. Recomme - ded(minimum) values: - Only C/A Parity is enabled. RoundUp((PHY Command Latency(DRAM CLK) + CAL + RDIMM delay + tPAR_ALERT_ON - max + tPAR_UNKNOWN + PHY Alert Latency(DRAM CLK) + board delay) / 4) + 2 - Both C/A Parity and CRC is enabled/ Only CRC is en - bled. RoundUp((PHY Command Latency(DRAM CLK) + CAL + RDIMM delay + WL + 5(BL10)+ tCRC_ALERT.max + PHY Alert Latency(DRAM CLK) - + board delay) / 4) + 2 Note 1: All value (e.g. tPAR_ALERT_ON) should be in terms of DRAM Clock and round up Note 2: Board de - ay(Command/Alert_n) should be considered. Note 3: Use the worst case(longer) value for PHY Latencies/Board delay Note 4: The - ecommended values are minimum value to be set. For mode detail, See 'Calculation of FIFO Depth' section. Max value can be set - to this register is defined below: - MEMC_BURST_LENGTH == 16 Full bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH- - Full bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Half bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_D - PTH-4 Half bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-6 Quarter bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CM - _FIFO_DEPTH-8 Quarter bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-12 - MEMC_BURST_LENGTH != 16 Full bus Mode (C - C=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-1 Full bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mo - e (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Quarte - bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-4 Quarter bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEP - H-6 Values of 0, 1 and 2 are illegal.*/ +/* +* Indicates the maximum duration in number of DRAM clock cycles for which + * a command should be held in the Command Retry FIFO before it is popped o + * ut. Every location in the Command Retry FIFO has an associated down coun + * ting timer that will use this register as the start value. The down coun + * ting starts when a command is loaded into the FIFO. The timer counts dow + * n every 4 DRAM cycles. When the counter reaches zero, the entry is poppe + * d from the FIFO. All the counters are frozen, if a C/A Parity or CRC err + * or occurs before the counter reaches zero. The counter is reset to 0, af + * ter all the commands in the FIFO are retried. Recommended(minimum) value + * s: - Only C/A Parity is enabled. RoundUp((PHY Command Latency(DRAM CLK) + * + CAL + RDIMM delay + tPAR_ALERT_ON.max + tPAR_UNKNOWN + PHY Alert Laten + * cy(DRAM CLK) + board delay) / 4) + 2 - Both C/A Parity and CRC is enable + * d/ Only CRC is enabled. RoundUp((PHY Command Latency(DRAM CLK) + CAL + R + * DIMM delay + WL + 5(BL10)+ tCRC_ALERT.max + PHY Alert Latency(DRAM CLK) + * + board delay) / 4) + 2 Note 1: All value (e.g. tPAR_ALERT_ON) should be + * in terms of DRAM Clock and round up Note 2: Board delay(Command/Alert_n + * ) should be considered. Note 3: Use the worst case(longer) value for PHY + * Latencies/Board delay Note 4: The Recommended values are minimum value + * to be set. For mode detail, See 'Calculation of FIFO Depth' section. Max + * value can be set to this register is defined below: - MEMC_BURST_LENGTH + * == 16 Full bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 + * Full bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Half b + * us Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-4 Half bus Mod + * e (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-6 Quarter bus Mode (C + * RC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-8 Quarter bus Mode (CRC= + * ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-12 - MEMC_BURST_LENGTH != 16 + * Full bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-1 Full + * bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mod + * e (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mode (CRC + * =ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Quarter bus Mode (CRC=OFF + * ) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-4 Quarter bus Mode (CRC=ON) Ma + * x value = UMCTL2_RETRY_CMD_FIFO_DEPTH-6 Values of 0, 1 and 2 are illegal + * . +*/ #undef DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_DEFVAL #undef DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_SHIFT #undef DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_MASK -#define DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_DEFVAL 0x0030050C -#define DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_SHIFT 0 -#define DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_MASK 0x0000003FU +#define DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_DEFVAL 0x0030050C +#define DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_SHIFT 0 +#define DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_MASK 0x0000003FU -/*If lower bit is enabled the SDRAM initialization routine is skipped. The upper bit decides what state the controller starts u - in when reset is removed - 00 - SDRAM Intialization routine is run after power-up - 01 - SDRAM Intialization routine is skip - ed after power-up. Controller starts up in Normal Mode - 11 - SDRAM Intialization routine is skipped after power-up. Controll - r starts up in Self-refresh Mode - 10 - SDRAM Intialization routine is run after power-up. Note: The only 2'b00 is supported - or LPDDR4 in this version of the uMCTL2.*/ +/* +* If lower bit is enabled the SDRAM initialization routine is skipped. The + * upper bit decides what state the controller starts up in when reset is + * removed - 00 - SDRAM Intialization routine is run after power-up - 01 - + * SDRAM Intialization routine is skipped after power-up. Controller starts + * up in Normal Mode - 11 - SDRAM Intialization routine is skipped after p + * ower-up. Controller starts up in Self-refresh Mode - 10 - SDRAM Intializ + * ation routine is run after power-up. Note: The only 2'b00 is supported f + * or LPDDR4 in this version of the uMCTL2. +*/ #undef DDRC_INIT0_SKIP_DRAM_INIT_DEFVAL #undef DDRC_INIT0_SKIP_DRAM_INIT_SHIFT #undef DDRC_INIT0_SKIP_DRAM_INIT_MASK -#define DDRC_INIT0_SKIP_DRAM_INIT_DEFVAL 0x0002004E -#define DDRC_INIT0_SKIP_DRAM_INIT_SHIFT 30 -#define DDRC_INIT0_SKIP_DRAM_INIT_MASK 0xC0000000U +#define DDRC_INIT0_SKIP_DRAM_INIT_DEFVAL 0x0002004E +#define DDRC_INIT0_SKIP_DRAM_INIT_SHIFT 30 +#define DDRC_INIT0_SKIP_DRAM_INIT_MASK 0xC0000000U -/*Cycles to wait after driving CKE high to start the SDRAM initialization sequence. Unit: 1024 clocks. DDR2 typically requires - 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2/LPDDR3 typically requires this to be pr - grammed for a delay of 200 us. LPDDR4 typically requires this to be programmed for a delay of 2 us. For configurations with M - MC_FREQ_RATIO=2, program this to JEDEC spec value divided by 2, and round it up to next integer value.*/ +/* +* Cycles to wait after driving CKE high to start the SDRAM initialization + * sequence. Unit: 1024 clocks. DDR2 typically requires a 400 ns delay, req + * uiring this value to be programmed to 2 at all clock speeds. LPDDR2/LPDD + * R3 typically requires this to be programmed for a delay of 200 us. LPDDR + * 4 typically requires this to be programmed for a delay of 2 us. For conf + * igurations with MEMC_FREQ_RATIO=2, program this to JEDEC spec value divi + * ded by 2, and round it up to next integer value. +*/ #undef DDRC_INIT0_POST_CKE_X1024_DEFVAL #undef DDRC_INIT0_POST_CKE_X1024_SHIFT #undef DDRC_INIT0_POST_CKE_X1024_MASK -#define DDRC_INIT0_POST_CKE_X1024_DEFVAL 0x0002004E -#define DDRC_INIT0_POST_CKE_X1024_SHIFT 16 -#define DDRC_INIT0_POST_CKE_X1024_MASK 0x03FF0000U +#define DDRC_INIT0_POST_CKE_X1024_DEFVAL 0x0002004E +#define DDRC_INIT0_POST_CKE_X1024_SHIFT 16 +#define DDRC_INIT0_POST_CKE_X1024_MASK 0x03FF0000U -/*Cycles to wait after reset before driving CKE high to start the SDRAM initialization sequence. Unit: 1024 clock cycles. DDR2 - pecifications typically require this to be programmed for a delay of >= 200 us. LPDDR2/LPDDR3: tINIT1 of 100 ns (min) LPDDR4: - tINIT3 of 2 ms (min) For configurations with MEMC_FREQ_RATIO=2, program this to JEDEC spec value divided by 2, and round it u - to next integer value.*/ +/* +* Cycles to wait after reset before driving CKE high to start the SDRAM in + * itialization sequence. Unit: 1024 clock cycles. DDR2 specifications typi + * cally require this to be programmed for a delay of >= 200 us. LPDDR2/LPD + * DR3: tINIT1 of 100 ns (min) LPDDR4: tINIT3 of 2 ms (min) For configurati + * ons with MEMC_FREQ_RATIO=2, program this to JEDEC spec value divided by + * 2, and round it up to next integer value. +*/ #undef DDRC_INIT0_PRE_CKE_X1024_DEFVAL #undef DDRC_INIT0_PRE_CKE_X1024_SHIFT #undef DDRC_INIT0_PRE_CKE_X1024_MASK -#define DDRC_INIT0_PRE_CKE_X1024_DEFVAL 0x0002004E -#define DDRC_INIT0_PRE_CKE_X1024_SHIFT 0 -#define DDRC_INIT0_PRE_CKE_X1024_MASK 0x00000FFFU +#define DDRC_INIT0_PRE_CKE_X1024_DEFVAL 0x0002004E +#define DDRC_INIT0_PRE_CKE_X1024_SHIFT 0 +#define DDRC_INIT0_PRE_CKE_X1024_MASK 0x00000FFFU -/*Number of cycles to assert SDRAM reset signal during init sequence. This is only present for designs supporting DDR3, DDR4 or - LPDDR4 devices. For use with a DDR PHY, this should be set to a minimum of 1*/ +/* +* Number of cycles to assert SDRAM reset signal during init sequence. This + * is only present for designs supporting DDR3, DDR4 or LPDDR4 devices. Fo + * r use with a DDR PHY, this should be set to a minimum of 1 +*/ #undef DDRC_INIT1_DRAM_RSTN_X1024_DEFVAL #undef DDRC_INIT1_DRAM_RSTN_X1024_SHIFT #undef DDRC_INIT1_DRAM_RSTN_X1024_MASK -#define DDRC_INIT1_DRAM_RSTN_X1024_DEFVAL 0x00000000 -#define DDRC_INIT1_DRAM_RSTN_X1024_SHIFT 16 -#define DDRC_INIT1_DRAM_RSTN_X1024_MASK 0x01FF0000U +#define DDRC_INIT1_DRAM_RSTN_X1024_DEFVAL 0x00000000 +#define DDRC_INIT1_DRAM_RSTN_X1024_SHIFT 16 +#define DDRC_INIT1_DRAM_RSTN_X1024_MASK 0x01FF0000U -/*Cycles to wait after completing the SDRAM initialization sequence before starting the dynamic scheduler. Unit: Counts of a gl - bal timer that pulses every 32 clock cycles. There is no known specific requirement for this; it may be set to zero.*/ +/* +* Cycles to wait after completing the SDRAM initialization sequence before + * starting the dynamic scheduler. Unit: Counts of a global timer that pul + * ses every 32 clock cycles. There is no known specific requirement for th + * is; it may be set to zero. +*/ #undef DDRC_INIT1_FINAL_WAIT_X32_DEFVAL #undef DDRC_INIT1_FINAL_WAIT_X32_SHIFT #undef DDRC_INIT1_FINAL_WAIT_X32_MASK -#define DDRC_INIT1_FINAL_WAIT_X32_DEFVAL 0x00000000 -#define DDRC_INIT1_FINAL_WAIT_X32_SHIFT 8 -#define DDRC_INIT1_FINAL_WAIT_X32_MASK 0x00007F00U +#define DDRC_INIT1_FINAL_WAIT_X32_DEFVAL 0x00000000 +#define DDRC_INIT1_FINAL_WAIT_X32_SHIFT 8 +#define DDRC_INIT1_FINAL_WAIT_X32_MASK 0x00007F00U -/*Wait period before driving the OCD complete command to SDRAM. Unit: Counts of a global timer that pulses every 32 clock cycle - . There is no known specific requirement for this; it may be set to zero.*/ +/* +* Wait period before driving the OCD complete command to SDRAM. Unit: Coun + * ts of a global timer that pulses every 32 clock cycles. There is no know + * n specific requirement for this; it may be set to zero. +*/ #undef DDRC_INIT1_PRE_OCD_X32_DEFVAL #undef DDRC_INIT1_PRE_OCD_X32_SHIFT #undef DDRC_INIT1_PRE_OCD_X32_MASK -#define DDRC_INIT1_PRE_OCD_X32_DEFVAL 0x00000000 -#define DDRC_INIT1_PRE_OCD_X32_SHIFT 0 -#define DDRC_INIT1_PRE_OCD_X32_MASK 0x0000000FU +#define DDRC_INIT1_PRE_OCD_X32_DEFVAL 0x00000000 +#define DDRC_INIT1_PRE_OCD_X32_SHIFT 0 +#define DDRC_INIT1_PRE_OCD_X32_MASK 0x0000000FU -/*Idle time after the reset command, tINIT4. Present only in designs configured to support LPDDR2. Unit: 32 clock cycles.*/ +/* +* Idle time after the reset command, tINIT4. Present only in designs confi + * gured to support LPDDR2. Unit: 32 clock cycles. +*/ #undef DDRC_INIT2_IDLE_AFTER_RESET_X32_DEFVAL #undef DDRC_INIT2_IDLE_AFTER_RESET_X32_SHIFT #undef DDRC_INIT2_IDLE_AFTER_RESET_X32_MASK -#define DDRC_INIT2_IDLE_AFTER_RESET_X32_DEFVAL 0x00000D05 -#define DDRC_INIT2_IDLE_AFTER_RESET_X32_SHIFT 8 -#define DDRC_INIT2_IDLE_AFTER_RESET_X32_MASK 0x0000FF00U +#define DDRC_INIT2_IDLE_AFTER_RESET_X32_DEFVAL 0x00000D05 +#define DDRC_INIT2_IDLE_AFTER_RESET_X32_SHIFT 8 +#define DDRC_INIT2_IDLE_AFTER_RESET_X32_MASK 0x0000FF00U -/*Time to wait after the first CKE high, tINIT2. Present only in designs configured to support LPDDR2/LPDDR3. Unit: 1 clock cyc - e. LPDDR2/LPDDR3 typically requires 5 x tCK delay.*/ +/* +* Time to wait after the first CKE high, tINIT2. Present only in designs c + * onfigured to support LPDDR2/LPDDR3. Unit: 1 clock cycle. LPDDR2/LPDDR3 t + * ypically requires 5 x tCK delay. +*/ #undef DDRC_INIT2_MIN_STABLE_CLOCK_X1_DEFVAL #undef DDRC_INIT2_MIN_STABLE_CLOCK_X1_SHIFT #undef DDRC_INIT2_MIN_STABLE_CLOCK_X1_MASK -#define DDRC_INIT2_MIN_STABLE_CLOCK_X1_DEFVAL 0x00000D05 -#define DDRC_INIT2_MIN_STABLE_CLOCK_X1_SHIFT 0 -#define DDRC_INIT2_MIN_STABLE_CLOCK_X1_MASK 0x0000000FU +#define DDRC_INIT2_MIN_STABLE_CLOCK_X1_DEFVAL 0x00000D05 +#define DDRC_INIT2_MIN_STABLE_CLOCK_X1_SHIFT 0 +#define DDRC_INIT2_MIN_STABLE_CLOCK_X1_MASK 0x0000000FU -/*DDR2: Value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The uMCTL2 sets this bit appropriately - DDR3/DDR4: Value loaded into MR0 register. mDDR: Value to write to MR register. LPDDR2/LPDDR3/LPDDR4 - Value to write to MR1 - register*/ +/* +* DDR2: Value to write to MR register. Bit 8 is for DLL and the setting he + * re is ignored. The uMCTL2 sets this bit appropriately. DDR3/DDR4: Value + * loaded into MR0 register. mDDR: Value to write to MR register. LPDDR2/LP + * DDR3/LPDDR4 - Value to write to MR1 register +*/ #undef DDRC_INIT3_MR_DEFVAL #undef DDRC_INIT3_MR_SHIFT #undef DDRC_INIT3_MR_MASK -#define DDRC_INIT3_MR_DEFVAL 0x00000510 -#define DDRC_INIT3_MR_SHIFT 16 -#define DDRC_INIT3_MR_MASK 0xFFFF0000U +#define DDRC_INIT3_MR_DEFVAL 0x00000510 +#define DDRC_INIT3_MR_SHIFT 16 +#define DDRC_INIT3_MR_MASK 0xFFFF0000U -/*DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setting in this register is ignored. The uMCTL2 sets those - bits appropriately. DDR3/DDR4: Value to write to MR1 register Set bit 7 to 0. If PHY-evaluation mode training is enabled, thi - bit is set appropriately by the uMCTL2 during write leveling. mDDR: Value to write to EMR register. LPDDR2/LPDDR3/LPDDR4 - V - lue to write to MR2 register*/ +/* +* DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setti + * ng in this register is ignored. The uMCTL2 sets those bits appropriately + * . DDR3/DDR4: Value to write to MR1 register Set bit 7 to 0. If PHY-evalu + * ation mode training is enabled, this bit is set appropriately by the uMC + * TL2 during write leveling. mDDR: Value to write to EMR register. LPDDR2/ + * LPDDR3/LPDDR4 - Value to write to MR2 register +*/ #undef DDRC_INIT3_EMR_DEFVAL #undef DDRC_INIT3_EMR_SHIFT #undef DDRC_INIT3_EMR_MASK -#define DDRC_INIT3_EMR_DEFVAL 0x00000510 -#define DDRC_INIT3_EMR_SHIFT 0 -#define DDRC_INIT3_EMR_MASK 0x0000FFFFU +#define DDRC_INIT3_EMR_DEFVAL 0x00000510 +#define DDRC_INIT3_EMR_SHIFT 0 +#define DDRC_INIT3_EMR_MASK 0x0000FFFFU -/*DDR2: Value to write to EMR2 register. DDR3/DDR4: Value to write to MR2 register LPDDR2/LPDDR3/LPDDR4: Value to write to MR3 - egister mDDR: Unused*/ +/* +* DDR2: Value to write to EMR2 register. DDR3/DDR4: Value to write to MR2 + * register LPDDR2/LPDDR3/LPDDR4: Value to write to MR3 register mDDR: Unus + * ed +*/ #undef DDRC_INIT4_EMR2_DEFVAL #undef DDRC_INIT4_EMR2_SHIFT #undef DDRC_INIT4_EMR2_MASK -#define DDRC_INIT4_EMR2_DEFVAL 0x00000000 -#define DDRC_INIT4_EMR2_SHIFT 16 -#define DDRC_INIT4_EMR2_MASK 0xFFFF0000U +#define DDRC_INIT4_EMR2_DEFVAL 0x00000000 +#define DDRC_INIT4_EMR2_SHIFT 16 +#define DDRC_INIT4_EMR2_MASK 0xFFFF0000U -/*DDR2: Value to write to EMR3 register. DDR3/DDR4: Value to write to MR3 register mDDR/LPDDR2/LPDDR3: Unused LPDDR4: Value to - rite to MR13 register*/ +/* +* DDR2: Value to write to EMR3 register. DDR3/DDR4: Value to write to MR3 + * register mDDR/LPDDR2/LPDDR3: Unused LPDDR4: Value to write to MR13 regis + * ter +*/ #undef DDRC_INIT4_EMR3_DEFVAL #undef DDRC_INIT4_EMR3_SHIFT #undef DDRC_INIT4_EMR3_MASK -#define DDRC_INIT4_EMR3_DEFVAL 0x00000000 -#define DDRC_INIT4_EMR3_SHIFT 0 -#define DDRC_INIT4_EMR3_MASK 0x0000FFFFU +#define DDRC_INIT4_EMR3_DEFVAL 0x00000000 +#define DDRC_INIT4_EMR3_SHIFT 0 +#define DDRC_INIT4_EMR3_MASK 0x0000FFFFU -/*ZQ initial calibration, tZQINIT. Present only in designs configured to support DDR3 or DDR4 or LPDDR2/LPDDR3. Unit: 32 clock - ycles. DDR3 typically requires 512 clocks. DDR4 requires 1024 clocks. LPDDR2/LPDDR3 requires 1 us.*/ +/* +* ZQ initial calibration, tZQINIT. Present only in designs configured to s + * upport DDR3 or DDR4 or LPDDR2/LPDDR3. Unit: 32 clock cycles. DDR3 typica + * lly requires 512 clocks. DDR4 requires 1024 clocks. LPDDR2/LPDDR3 requir + * es 1 us. +*/ #undef DDRC_INIT5_DEV_ZQINIT_X32_DEFVAL #undef DDRC_INIT5_DEV_ZQINIT_X32_SHIFT #undef DDRC_INIT5_DEV_ZQINIT_X32_MASK -#define DDRC_INIT5_DEV_ZQINIT_X32_DEFVAL 0x00100004 -#define DDRC_INIT5_DEV_ZQINIT_X32_SHIFT 16 -#define DDRC_INIT5_DEV_ZQINIT_X32_MASK 0x00FF0000U +#define DDRC_INIT5_DEV_ZQINIT_X32_DEFVAL 0x00100004 +#define DDRC_INIT5_DEV_ZQINIT_X32_SHIFT 16 +#define DDRC_INIT5_DEV_ZQINIT_X32_MASK 0x00FF0000U -/*Maximum duration of the auto initialization, tINIT5. Present only in designs configured to support LPDDR2/LPDDR3. LPDDR2/LPDD - 3 typically requires 10 us.*/ +/* +* Maximum duration of the auto initialization, tINIT5. Present only in des + * igns configured to support LPDDR2/LPDDR3. LPDDR2/LPDDR3 typically requir + * es 10 us. +*/ #undef DDRC_INIT5_MAX_AUTO_INIT_X1024_DEFVAL #undef DDRC_INIT5_MAX_AUTO_INIT_X1024_SHIFT #undef DDRC_INIT5_MAX_AUTO_INIT_X1024_MASK -#define DDRC_INIT5_MAX_AUTO_INIT_X1024_DEFVAL 0x00100004 -#define DDRC_INIT5_MAX_AUTO_INIT_X1024_SHIFT 0 -#define DDRC_INIT5_MAX_AUTO_INIT_X1024_MASK 0x000003FFU +#define DDRC_INIT5_MAX_AUTO_INIT_X1024_DEFVAL 0x00100004 +#define DDRC_INIT5_MAX_AUTO_INIT_X1024_SHIFT 0 +#define DDRC_INIT5_MAX_AUTO_INIT_X1024_MASK 0x000003FFU -/*DDR4- Value to be loaded into SDRAM MR4 registers. Used in DDR4 designs only.*/ +/* +* DDR4- Value to be loaded into SDRAM MR4 registers. Used in DDR4 designs + * only. +*/ #undef DDRC_INIT6_MR4_DEFVAL #undef DDRC_INIT6_MR4_SHIFT #undef DDRC_INIT6_MR4_MASK -#define DDRC_INIT6_MR4_DEFVAL 0x00000000 -#define DDRC_INIT6_MR4_SHIFT 16 -#define DDRC_INIT6_MR4_MASK 0xFFFF0000U +#define DDRC_INIT6_MR4_DEFVAL 0x00000000 +#define DDRC_INIT6_MR4_SHIFT 16 +#define DDRC_INIT6_MR4_MASK 0xFFFF0000U -/*DDR4- Value to be loaded into SDRAM MR5 registers. Used in DDR4 designs only.*/ +/* +* DDR4- Value to be loaded into SDRAM MR5 registers. Used in DDR4 designs + * only. +*/ #undef DDRC_INIT6_MR5_DEFVAL #undef DDRC_INIT6_MR5_SHIFT #undef DDRC_INIT6_MR5_MASK -#define DDRC_INIT6_MR5_DEFVAL 0x00000000 -#define DDRC_INIT6_MR5_SHIFT 0 -#define DDRC_INIT6_MR5_MASK 0x0000FFFFU +#define DDRC_INIT6_MR5_DEFVAL 0x00000000 +#define DDRC_INIT6_MR5_SHIFT 0 +#define DDRC_INIT6_MR5_MASK 0x0000FFFFU -/*DDR4- Value to be loaded into SDRAM MR6 registers. Used in DDR4 designs only.*/ +/* +* DDR4- Value to be loaded into SDRAM MR6 registers. Used in DDR4 designs + * only. +*/ #undef DDRC_INIT7_MR6_DEFVAL #undef DDRC_INIT7_MR6_SHIFT #undef DDRC_INIT7_MR6_MASK -#define DDRC_INIT7_MR6_DEFVAL -#define DDRC_INIT7_MR6_SHIFT 16 -#define DDRC_INIT7_MR6_MASK 0xFFFF0000U +#define DDRC_INIT7_MR6_DEFVAL +#define DDRC_INIT7_MR6_SHIFT 16 +#define DDRC_INIT7_MR6_MASK 0xFFFF0000U -/*Disabling Address Mirroring for BG bits. When this is set to 1, BG0 and BG1 are NOT swapped even if Address Mirroring is enab - ed. This will be required for DDR4 DIMMs with x16 devices. - 1 - BG0 and BG1 are NOT swapped. - 0 - BG0 and BG1 are swapped i - address mirroring is enabled.*/ +/* +* Disabling Address Mirroring for BG bits. When this is set to 1, BG0 and + * BG1 are NOT swapped even if Address Mirroring is enabled. This will be r + * equired for DDR4 DIMMs with x16 devices. - 1 - BG0 and BG1 are NOT swapp + * ed. - 0 - BG0 and BG1 are swapped if address mirroring is enabled. +*/ #undef DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_DEFVAL #undef DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_SHIFT #undef DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_MASK -#define DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_DEFVAL 0x00000000 -#define DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_SHIFT 5 -#define DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_MASK 0x00000020U +#define DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_DEFVAL 0x00000000 +#define DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_SHIFT 5 +#define DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_MASK 0x00000020U -/*Enable for BG1 bit of MRS command. BG1 bit of the mode register address is specified as RFU (Reserved for Future Use) and mus - be programmed to 0 during MRS. In case where DRAMs which do not have BG1 are attached and both the CA parity and the Output - nversion are enabled, this must be set to 0, so that the calculation of CA parity will not include BG1 bit. Note: This has no - effect on the address of any other memory accesses, or of software-driven mode register accesses. If address mirroring is ena - led, this is applied to BG1 of even ranks and BG0 of odd ranks. - 1 - Enabled - 0 - Disabled*/ +/* +* Enable for BG1 bit of MRS command. BG1 bit of the mode register address + * is specified as RFU (Reserved for Future Use) and must be programmed to + * 0 during MRS. In case where DRAMs which do not have BG1 are attached and + * both the CA parity and the Output Inversion are enabled, this must be s + * et to 0, so that the calculation of CA parity will not include BG1 bit. + * Note: This has no effect on the address of any other memory accesses, or + * of software-driven mode register accesses. If address mirroring is enab + * led, this is applied to BG1 of even ranks and BG0 of odd ranks. - 1 - En + * abled - 0 - Disabled +*/ #undef DDRC_DIMMCTL_MRS_BG1_EN_DEFVAL #undef DDRC_DIMMCTL_MRS_BG1_EN_SHIFT #undef DDRC_DIMMCTL_MRS_BG1_EN_MASK -#define DDRC_DIMMCTL_MRS_BG1_EN_DEFVAL 0x00000000 -#define DDRC_DIMMCTL_MRS_BG1_EN_SHIFT 4 -#define DDRC_DIMMCTL_MRS_BG1_EN_MASK 0x00000010U +#define DDRC_DIMMCTL_MRS_BG1_EN_DEFVAL 0x00000000 +#define DDRC_DIMMCTL_MRS_BG1_EN_SHIFT 4 +#define DDRC_DIMMCTL_MRS_BG1_EN_MASK 0x00000010U -/*Enable for A17 bit of MRS command. A17 bit of the mode register address is specified as RFU (Reserved for Future Use) and mus - be programmed to 0 during MRS. In case where DRAMs which do not have A17 are attached and the Output Inversion are enabled, - his must be set to 0, so that the calculation of CA parity will not include A17 bit. Note: This has no effect on the address - f any other memory accesses, or of software-driven mode register accesses. - 1 - Enabled - 0 - Disabled*/ +/* +* Enable for A17 bit of MRS command. A17 bit of the mode register address + * is specified as RFU (Reserved for Future Use) and must be programmed to + * 0 during MRS. In case where DRAMs which do not have A17 are attached and + * the Output Inversion are enabled, this must be set to 0, so that the ca + * lculation of CA parity will not include A17 bit. Note: This has no effec + * t on the address of any other memory accesses, or of software-driven mod + * e register accesses. - 1 - Enabled - 0 - Disabled +*/ #undef DDRC_DIMMCTL_MRS_A17_EN_DEFVAL #undef DDRC_DIMMCTL_MRS_A17_EN_SHIFT #undef DDRC_DIMMCTL_MRS_A17_EN_MASK -#define DDRC_DIMMCTL_MRS_A17_EN_DEFVAL 0x00000000 -#define DDRC_DIMMCTL_MRS_A17_EN_SHIFT 3 -#define DDRC_DIMMCTL_MRS_A17_EN_MASK 0x00000008U +#define DDRC_DIMMCTL_MRS_A17_EN_DEFVAL 0x00000000 +#define DDRC_DIMMCTL_MRS_A17_EN_SHIFT 3 +#define DDRC_DIMMCTL_MRS_A17_EN_MASK 0x00000008U -/*Output Inversion Enable (for DDR4 RDIMM implementations only). DDR4 RDIMM implements the Output Inversion feature by default, - which means that the following address, bank address and bank group bits of B-side DRAMs are inverted: A3-A9, A11, A13, A17, - A0-BA1, BG0-BG1. Setting this bit ensures that, for mode register accesses generated by the uMCTL2 during the automatic initi - lization routine and enabling of a particular DDR4 feature, separate A-side and B-side mode register accesses are generated. - or B-side mode register accesses, these bits are inverted within the uMCTL2 to compensate for this RDIMM inversion. Note: Thi - has no effect on the address of any other memory accesses, or of software-driven mode register accesses. - 1 - Implement out - ut inversion for B-side DRAMs. - 0 - Do not implement output inversion for B-side DRAMs.*/ +/* +* Output Inversion Enable (for DDR4 RDIMM implementations only). DDR4 RDIM + * M implements the Output Inversion feature by default, which means that t + * he following address, bank address and bank group bits of B-side DRAMs a + * re inverted: A3-A9, A11, A13, A17, BA0-BA1, BG0-BG1. Setting this bit en + * sures that, for mode register accesses generated by the uMCTL2 during th + * e automatic initialization routine and enabling of a particular DDR4 fea + * ture, separate A-side and B-side mode register accesses are generated. F + * or B-side mode register accesses, these bits are inverted within the uMC + * TL2 to compensate for this RDIMM inversion. Note: This has no effect on + * the address of any other memory accesses, or of software-driven mode reg + * ister accesses. - 1 - Implement output inversion for B-side DRAMs. - 0 - + * Do not implement output inversion for B-side DRAMs. +*/ #undef DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_DEFVAL #undef DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_SHIFT #undef DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_MASK -#define DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_DEFVAL 0x00000000 -#define DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_SHIFT 2 -#define DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_MASK 0x00000004U +#define DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_DEFVAL 0x00000000 +#define DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_SHIFT 2 +#define DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_MASK 0x00000004U -/*Address Mirroring Enable (for multi-rank UDIMM implementations and multi-rank DDR4 RDIMM implementations). Some UDIMMs and DD - 4 RDIMMs implement address mirroring for odd ranks, which means that the following address, bank address and bank group bits - re swapped: (A3, A4), (A5, A6), (A7, A8), (BA0, BA1) and also (A11, A13), (BG0, BG1) for the DDR4. Setting this bit ensures t - at, for mode register accesses during the automatic initialization routine, these bits are swapped within the uMCTL2 to compe - sate for this UDIMM/RDIMM swapping. In addition to the automatic initialization routine, in case of DDR4 UDIMM/RDIMM, they ar - swapped during the automatic MRS access to enable/disable of a particular DDR4 feature. Note: This has no effect on the addr - ss of any other memory accesses, or of software-driven mode register accesses. This is not supported for mDDR, LPDDR2, LPDDR3 - or LPDDR4 SDRAMs. Note: In case of x16 DDR4 DIMMs, BG1 output of MRS for the odd ranks is same as BG0 because BG1 is invalid, - hence dimm_dis_bg_mirroring register must be set to 1. - 1 - For odd ranks, implement address mirroring for MRS commands to d - ring initialization and for any automatic DDR4 MRS commands (to be used if UDIMM/RDIMM implements address mirroring) - 0 - Do - not implement address mirroring*/ +/* +* Address Mirroring Enable (for multi-rank UDIMM implementations and multi + * -rank DDR4 RDIMM implementations). Some UDIMMs and DDR4 RDIMMs implement + * address mirroring for odd ranks, which means that the following address + * , bank address and bank group bits are swapped: (A3, A4), (A5, A6), (A7, + * A8), (BA0, BA1) and also (A11, A13), (BG0, BG1) for the DDR4. Setting t + * his bit ensures that, for mode register accesses during the automatic in + * itialization routine, these bits are swapped within the uMCTL2 to compen + * sate for this UDIMM/RDIMM swapping. In addition to the automatic initial + * ization routine, in case of DDR4 UDIMM/RDIMM, they are swapped during th + * e automatic MRS access to enable/disable of a particular DDR4 feature. N + * ote: This has no effect on the address of any other memory accesses, or + * of software-driven mode register accesses. This is not supported for mDD + * R, LPDDR2, LPDDR3 or LPDDR4 SDRAMs. Note: In case of x16 DDR4 DIMMs, BG1 + * output of MRS for the odd ranks is same as BG0 because BG1 is invalid, + * hence dimm_dis_bg_mirroring register must be set to 1. - 1 - For odd ran + * ks, implement address mirroring for MRS commands to during initializatio + * n and for any automatic DDR4 MRS commands (to be used if UDIMM/RDIMM imp + * lements address mirroring) - 0 - Do not implement address mirroring +*/ #undef DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_DEFVAL #undef DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_SHIFT #undef DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_MASK -#define DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_DEFVAL 0x00000000 -#define DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_SHIFT 1 -#define DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_MASK 0x00000002U +#define DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_DEFVAL 0x00000000 +#define DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_SHIFT 1 +#define DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_MASK 0x00000002U -/*Staggering enable for multi-rank accesses (for multi-rank UDIMM and RDIMM implementations only). This is not supported for mD - R, LPDDR2, LPDDR3 or LPDDR4 SDRAMs. Note: Even if this bit is set it does not take care of software driven MR commands (via M - CTRL0/MRCTRL1), where software is responsible to send them to seperate ranks as appropriate. - 1 - (DDR4) Send MRS commands t - each ranks seperately - 1 - (non-DDR4) Send all commands to even and odd ranks seperately - 0 - Do not stagger accesses*/ +/* +* Staggering enable for multi-rank accesses (for multi-rank UDIMM and RDIM + * M implementations only). This is not supported for mDDR, LPDDR2, LPDDR3 + * or LPDDR4 SDRAMs. Note: Even if this bit is set it does not take care of + * software driven MR commands (via MRCTRL0/MRCTRL1), where software is re + * sponsible to send them to seperate ranks as appropriate. - 1 - (DDR4) Se + * nd MRS commands to each ranks seperately - 1 - (non-DDR4) Send all comma + * nds to even and odd ranks seperately - 0 - Do not stagger accesses +*/ #undef DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_DEFVAL #undef DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_SHIFT #undef DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_MASK -#define DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_DEFVAL 0x00000000 -#define DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_SHIFT 0 -#define DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_MASK 0x00000001U +#define DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_DEFVAL 0x00000000 +#define DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_SHIFT 0 +#define DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_MASK 0x00000001U -/*Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecuti - e writes to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This value should c - nsider both PHY requirement and ODT requirement. - PHY requirement: tphy_wrcsgap + 1 (see PHY databook for value of tphy_wrcs - ap) If CRC feature is enabled, should be increased by 1. If write preamble is set to 2tCK(DDR4/LPDDR4 only), should be increa - ed by 1. If write postamble is set to 1.5tCK(LPDDR4 only), should be increased by 1. - ODT requirement: The value programmed - n this register takes care of the ODT switch off timing requirement when switching ranks during writes. For LPDDR4, the requi - ement is ODTLoff - ODTLon - BL/2 + 1 For configurations with MEMC_FREQ_RATIO=1, program this to the larger of PHY requirement - or ODT requirement. For configurations with MEMC_FREQ_RATIO=2, program this to the larger value divided by two and round it u - to the next integer.*/ +/* +* Only present for multi-rank configurations. Indicates the number of cloc + * ks of gap in data responses when performing consecutive writes to differ + * ent ranks. This is used to switch the delays in the PHY to match the ran + * k requirements. This value should consider both PHY requirement and ODT + * requirement. - PHY requirement: tphy_wrcsgap + 1 (see PHY databook for v + * alue of tphy_wrcsgap) If CRC feature is enabled, should be increased by + * 1. If write preamble is set to 2tCK(DDR4/LPDDR4 only), should be increas + * ed by 1. If write postamble is set to 1.5tCK(LPDDR4 only), should be inc + * reased by 1. - ODT requirement: The value programmed in this register ta + * kes care of the ODT switch off timing requirement when switching ranks d + * uring writes. For LPDDR4, the requirement is ODTLoff - ODTLon - BL/2 + 1 + * For configurations with MEMC_FREQ_RATIO=1, program this to the larger o + * f PHY requirement or ODT requirement. For configurations with MEMC_FREQ_ + * RATIO=2, program this to the larger value divided by two and round it up + * to the next integer. +*/ #undef DDRC_RANKCTL_DIFF_RANK_WR_GAP_DEFVAL #undef DDRC_RANKCTL_DIFF_RANK_WR_GAP_SHIFT #undef DDRC_RANKCTL_DIFF_RANK_WR_GAP_MASK -#define DDRC_RANKCTL_DIFF_RANK_WR_GAP_DEFVAL 0x0000066F -#define DDRC_RANKCTL_DIFF_RANK_WR_GAP_SHIFT 8 -#define DDRC_RANKCTL_DIFF_RANK_WR_GAP_MASK 0x00000F00U +#define DDRC_RANKCTL_DIFF_RANK_WR_GAP_DEFVAL 0x0000066F +#define DDRC_RANKCTL_DIFF_RANK_WR_GAP_SHIFT 8 +#define DDRC_RANKCTL_DIFF_RANK_WR_GAP_MASK 0x00000F00U -/*Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecuti - e reads to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This value should co - sider both PHY requirement and ODT requirement. - PHY requirement: tphy_rdcsgap + 1 (see PHY databook for value of tphy_rdcsg - p) If read preamble is set to 2tCK(DDR4/LPDDR4 only), should be increased by 1. If read postamble is set to 1.5tCK(LPDDR4 onl - ), should be increased by 1. - ODT requirement: The value programmed in this register takes care of the ODT switch off timing - requirement when switching ranks during reads. For configurations with MEMC_FREQ_RATIO=1, program this to the larger of PHY r - quirement or ODT requirement. For configurations with MEMC_FREQ_RATIO=2, program this to the larger value divided by two and - ound it up to the next integer.*/ +/* +* Only present for multi-rank configurations. Indicates the number of cloc + * ks of gap in data responses when performing consecutive reads to differe + * nt ranks. This is used to switch the delays in the PHY to match the rank + * requirements. This value should consider both PHY requirement and ODT r + * equirement. - PHY requirement: tphy_rdcsgap + 1 (see PHY databook for va + * lue of tphy_rdcsgap) If read preamble is set to 2tCK(DDR4/LPDDR4 only), + * should be increased by 1. If read postamble is set to 1.5tCK(LPDDR4 only + * ), should be increased by 1. - ODT requirement: The value programmed in + * this register takes care of the ODT switch off timing requirement when s + * witching ranks during reads. For configurations with MEMC_FREQ_RATIO=1, + * program this to the larger of PHY requirement or ODT requirement. For co + * nfigurations with MEMC_FREQ_RATIO=2, program this to the larger value di + * vided by two and round it up to the next integer. +*/ #undef DDRC_RANKCTL_DIFF_RANK_RD_GAP_DEFVAL #undef DDRC_RANKCTL_DIFF_RANK_RD_GAP_SHIFT #undef DDRC_RANKCTL_DIFF_RANK_RD_GAP_MASK -#define DDRC_RANKCTL_DIFF_RANK_RD_GAP_DEFVAL 0x0000066F -#define DDRC_RANKCTL_DIFF_RANK_RD_GAP_SHIFT 4 -#define DDRC_RANKCTL_DIFF_RANK_RD_GAP_MASK 0x000000F0U +#define DDRC_RANKCTL_DIFF_RANK_RD_GAP_DEFVAL 0x0000066F +#define DDRC_RANKCTL_DIFF_RANK_RD_GAP_SHIFT 4 +#define DDRC_RANKCTL_DIFF_RANK_RD_GAP_MASK 0x000000F0U -/*Only present for multi-rank configurations. Background: Reads to the same rank can be performed back-to-back. Reads to differ - nt ranks require additional gap dictated by the register RANKCTL.diff_rank_rd_gap. This is to avoid possible data bus content - on as well as to give PHY enough time to switch the delay when changing ranks. The uMCTL2 arbitrates for bus access on a cycl - -by-cycle basis; therefore after a read is scheduled, there are few clock cycles (determined by the value on RANKCTL.diff_ran - _rd_gap register) in which only reads from the same rank are eligible to be scheduled. This prevents reads from other ranks f - om having fair access to the data bus. This parameter represents the maximum number of reads that can be scheduled consecutiv - ly to the same rank. After this number is reached, a delay equal to RANKCTL.diff_rank_rd_gap is inserted by the scheduler to - llow all ranks a fair opportunity to be scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fair - ess. This feature can be DISABLED by setting this register to 0. When set to 0, the Controller will stay on the same rank as - ong as commands are available for it. Minimum programmable value is 0 (feature disabled) and maximum programmable value is 0x - . FOR PERFORMANCE ONLY.*/ +/* +* Only present for multi-rank configurations. Background: Reads to the sam + * e rank can be performed back-to-back. Reads to different ranks require a + * dditional gap dictated by the register RANKCTL.diff_rank_rd_gap. This is + * to avoid possible data bus contention as well as to give PHY enough tim + * e to switch the delay when changing ranks. The uMCTL2 arbitrates for bus + * access on a cycle-by-cycle basis; therefore after a read is scheduled, + * there are few clock cycles (determined by the value on RANKCTL.diff_rank + * _rd_gap register) in which only reads from the same rank are eligible to + * be scheduled. This prevents reads from other ranks from having fair acc + * ess to the data bus. This parameter represents the maximum number of rea + * ds that can be scheduled consecutively to the same rank. After this numb + * er is reached, a delay equal to RANKCTL.diff_rank_rd_gap is inserted by + * the scheduler to allow all ranks a fair opportunity to be scheduled. Hig + * her numbers increase bandwidth utilization, lower numbers increase fairn + * ess. This feature can be DISABLED by setting this register to 0. When se + * t to 0, the Controller will stay on the same rank as long as commands ar + * e available for it. Minimum programmable value is 0 (feature disabled) a + * nd maximum programmable value is 0xF. FOR PERFORMANCE ONLY. +*/ #undef DDRC_RANKCTL_MAX_RANK_RD_DEFVAL #undef DDRC_RANKCTL_MAX_RANK_RD_SHIFT #undef DDRC_RANKCTL_MAX_RANK_RD_MASK -#define DDRC_RANKCTL_MAX_RANK_RD_DEFVAL 0x0000066F -#define DDRC_RANKCTL_MAX_RANK_RD_SHIFT 0 -#define DDRC_RANKCTL_MAX_RANK_RD_MASK 0x0000000FU +#define DDRC_RANKCTL_MAX_RANK_RD_DEFVAL 0x0000066F +#define DDRC_RANKCTL_MAX_RANK_RD_SHIFT 0 +#define DDRC_RANKCTL_MAX_RANK_RD_MASK 0x0000000FU -/*Minimum time between write and precharge to same bank. Unit: Clocks Specifications: WL + BL/2 + tWR = approximately 8 cycles - 15 ns = 14 clocks @400MHz and less for lower frequencies where: - WL = write latency - BL = burst length. This must match th - value programmed in the BL bit of the mode register to the SDRAM. BST (burst terminate) is not supported at present. - tWR = - Write recovery time. This comes directly from the SDRAM specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 for this - arameter. For configurations with MEMC_FREQ_RATIO=2, 1T mode, divide the above value by 2. No rounding up. For configurations - with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, divide the above value by 2 and round it up to the next integer value.*/ +/* +* Minimum time between write and precharge to same bank. Unit: Clocks Spec + * ifications: WL + BL/2 + tWR = approximately 8 cycles + 15 ns = 14 clocks + * @400MHz and less for lower frequencies where: - WL = write latency - BL + * = burst length. This must match the value programmed in the BL bit of t + * he mode register to the SDRAM. BST (burst terminate) is not supported at + * present. - tWR = Write recovery time. This comes directly from the SDRA + * M specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 for this p + * arameter. For configurations with MEMC_FREQ_RATIO=2, 1T mode, divide the + * above value by 2. No rounding up. For configurations with MEMC_FREQ_RAT + * IO=2, 2T mode or LPDDR4 mode, divide the above value by 2 and round it u + * p to the next integer value. +*/ #undef DDRC_DRAMTMG0_WR2PRE_DEFVAL #undef DDRC_DRAMTMG0_WR2PRE_SHIFT #undef DDRC_DRAMTMG0_WR2PRE_MASK -#define DDRC_DRAMTMG0_WR2PRE_DEFVAL 0x0F101B0F -#define DDRC_DRAMTMG0_WR2PRE_SHIFT 24 -#define DDRC_DRAMTMG0_WR2PRE_MASK 0x7F000000U +#define DDRC_DRAMTMG0_WR2PRE_DEFVAL 0x0F101B0F +#define DDRC_DRAMTMG0_WR2PRE_SHIFT 24 +#define DDRC_DRAMTMG0_WR2PRE_MASK 0x7F000000U -/*tFAW Valid only when 8 or more banks(or banks x bank groups) are present. In 8-bank design, at most 4 banks must be activated - in a rolling window of tFAW cycles. For configurations with MEMC_FREQ_RATIO=2, program this to (tFAW/2) and round up to next - nteger value. In a 4-bank design, set this register to 0x1 independent of the MEMC_FREQ_RATIO configuration. Unit: Clocks*/ +/* +* tFAW Valid only when 8 or more banks(or banks x bank groups) are present + * . In 8-bank design, at most 4 banks must be activated in a rolling windo + * w of tFAW cycles. For configurations with MEMC_FREQ_RATIO=2, program thi + * s to (tFAW/2) and round up to next integer value. In a 4-bank design, se + * t this register to 0x1 independent of the MEMC_FREQ_RATIO configuration. + * Unit: Clocks +*/ #undef DDRC_DRAMTMG0_T_FAW_DEFVAL #undef DDRC_DRAMTMG0_T_FAW_SHIFT #undef DDRC_DRAMTMG0_T_FAW_MASK -#define DDRC_DRAMTMG0_T_FAW_DEFVAL 0x0F101B0F -#define DDRC_DRAMTMG0_T_FAW_SHIFT 16 -#define DDRC_DRAMTMG0_T_FAW_MASK 0x003F0000U +#define DDRC_DRAMTMG0_T_FAW_DEFVAL 0x0F101B0F +#define DDRC_DRAMTMG0_T_FAW_SHIFT 16 +#define DDRC_DRAMTMG0_T_FAW_MASK 0x003F0000U -/*tRAS(max): Maximum time between activate and precharge to same bank. This is the maximum time that a page can be kept open Mi - imum value of this register is 1. Zero is invalid. For configurations with MEMC_FREQ_RATIO=2, program this to (tRAS(max)-1)/2 - No rounding up. Unit: Multiples of 1024 clocks.*/ +/* +* tRAS(max): Maximum time between activate and precharge to same bank. Thi + * s is the maximum time that a page can be kept open Minimum value of this + * register is 1. Zero is invalid. For configurations with MEMC_FREQ_RATIO + * =2, program this to (tRAS(max)-1)/2. No rounding up. Unit: Multiples of + * 1024 clocks. +*/ #undef DDRC_DRAMTMG0_T_RAS_MAX_DEFVAL #undef DDRC_DRAMTMG0_T_RAS_MAX_SHIFT #undef DDRC_DRAMTMG0_T_RAS_MAX_MASK -#define DDRC_DRAMTMG0_T_RAS_MAX_DEFVAL 0x0F101B0F -#define DDRC_DRAMTMG0_T_RAS_MAX_SHIFT 8 -#define DDRC_DRAMTMG0_T_RAS_MAX_MASK 0x00007F00U +#define DDRC_DRAMTMG0_T_RAS_MAX_DEFVAL 0x0F101B0F +#define DDRC_DRAMTMG0_T_RAS_MAX_SHIFT 8 +#define DDRC_DRAMTMG0_T_RAS_MAX_MASK 0x00007F00U -/*tRAS(min): Minimum time between activate and precharge to the same bank. For configurations with MEMC_FREQ_RATIO=2, 1T mode, - rogram this to tRAS(min)/2. No rounding up. For configurations with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, program this t - (tRAS(min)/2) and round it up to the next integer value. Unit: Clocks*/ +/* +* tRAS(min): Minimum time between activate and precharge to the same bank. + * For configurations with MEMC_FREQ_RATIO=2, 1T mode, program this to tRA + * S(min)/2. No rounding up. For configurations with MEMC_FREQ_RATIO=2, 2T + * mode or LPDDR4 mode, program this to (tRAS(min)/2) and round it up to th + * e next integer value. Unit: Clocks +*/ #undef DDRC_DRAMTMG0_T_RAS_MIN_DEFVAL #undef DDRC_DRAMTMG0_T_RAS_MIN_SHIFT #undef DDRC_DRAMTMG0_T_RAS_MIN_MASK -#define DDRC_DRAMTMG0_T_RAS_MIN_DEFVAL 0x0F101B0F -#define DDRC_DRAMTMG0_T_RAS_MIN_SHIFT 0 -#define DDRC_DRAMTMG0_T_RAS_MIN_MASK 0x0000003FU +#define DDRC_DRAMTMG0_T_RAS_MIN_DEFVAL 0x0F101B0F +#define DDRC_DRAMTMG0_T_RAS_MIN_SHIFT 0 +#define DDRC_DRAMTMG0_T_RAS_MIN_MASK 0x0000003FU -/*tXP: Minimum time after power-down exit to any operation. For DDR3, this should be programmed to tXPDLL if slow powerdown exi - is selected in MR0[12]. If C/A parity for DDR4 is used, set to (tXP+PL) instead. For configurations with MEMC_FREQ_RATIO=2, - rogram this to (tXP/2) and round it up to the next integer value. Units: Clocks*/ +/* +* tXP: Minimum time after power-down exit to any operation. For DDR3, this + * should be programmed to tXPDLL if slow powerdown exit is selected in MR + * 0[12]. If C/A parity for DDR4 is used, set to (tXP+PL) instead. For conf + * igurations with MEMC_FREQ_RATIO=2, program this to (tXP/2) and round it + * up to the next integer value. Units: Clocks +*/ #undef DDRC_DRAMTMG1_T_XP_DEFVAL #undef DDRC_DRAMTMG1_T_XP_SHIFT #undef DDRC_DRAMTMG1_T_XP_MASK -#define DDRC_DRAMTMG1_T_XP_DEFVAL 0x00080414 -#define DDRC_DRAMTMG1_T_XP_SHIFT 16 -#define DDRC_DRAMTMG1_T_XP_MASK 0x001F0000U +#define DDRC_DRAMTMG1_T_XP_DEFVAL 0x00080414 +#define DDRC_DRAMTMG1_T_XP_SHIFT 16 +#define DDRC_DRAMTMG1_T_XP_MASK 0x001F0000U -/*tRTP: Minimum time from read to precharge of same bank. - DDR2: tAL + BL/2 + max(tRTP, 2) - 2 - DDR3: tAL + max (tRTP, 4) - D - R4: Max of following two equations: tAL + max (tRTP, 4) or, RL + BL/2 - tRP. - mDDR: BL/2 - LPDDR2: Depends on if it's LPDDR2 - S2 or LPDDR2-S4: LPDDR2-S2: BL/2 + tRTP - 1. LPDDR2-S4: BL/2 + max(tRTP,2) - 2. - LPDDR3: BL/2 + max(tRTP,4) - 4 - LPDDR4: BL - 2 + max(tRTP,8) - 8 For configurations with MEMC_FREQ_RATIO=2, 1T mode, divide the above value by 2. No rounding up. For conf - gurations with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, divide the above value by 2 and round it up to the next integer val - e. Unit: Clocks.*/ +/* +* tRTP: Minimum time from read to precharge of same bank. - DDR2: tAL + BL + * /2 + max(tRTP, 2) - 2 - DDR3: tAL + max (tRTP, 4) - DDR4: Max of followi + * ng two equations: tAL + max (tRTP, 4) or, RL + BL/2 - tRP. - mDDR: BL/2 + * - LPDDR2: Depends on if it's LPDDR2-S2 or LPDDR2-S4: LPDDR2-S2: BL/2 + t + * RTP - 1. LPDDR2-S4: BL/2 + max(tRTP,2) - 2. - LPDDR3: BL/2 + max(tRTP,4) + * - 4 - LPDDR4: BL/2 + max(tRTP,8) - 8 For configurations with MEMC_FREQ_ + * RATIO=2, 1T mode, divide the above value by 2. No rounding up. For confi + * gurations with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, divide the abo + * ve value by 2 and round it up to the next integer value. Unit: Clocks. +*/ #undef DDRC_DRAMTMG1_RD2PRE_DEFVAL #undef DDRC_DRAMTMG1_RD2PRE_SHIFT #undef DDRC_DRAMTMG1_RD2PRE_MASK -#define DDRC_DRAMTMG1_RD2PRE_DEFVAL 0x00080414 -#define DDRC_DRAMTMG1_RD2PRE_SHIFT 8 -#define DDRC_DRAMTMG1_RD2PRE_MASK 0x00001F00U +#define DDRC_DRAMTMG1_RD2PRE_DEFVAL 0x00080414 +#define DDRC_DRAMTMG1_RD2PRE_SHIFT 8 +#define DDRC_DRAMTMG1_RD2PRE_MASK 0x00001F00U -/*tRC: Minimum time between activates to same bank. For configurations with MEMC_FREQ_RATIO=2, program this to (tRC/2) and roun - up to next integer value. Unit: Clocks.*/ +/* +* tRC: Minimum time between activates to same bank. For configurations wit + * h MEMC_FREQ_RATIO=2, program this to (tRC/2) and round up to next intege + * r value. Unit: Clocks. +*/ #undef DDRC_DRAMTMG1_T_RC_DEFVAL #undef DDRC_DRAMTMG1_T_RC_SHIFT #undef DDRC_DRAMTMG1_T_RC_MASK -#define DDRC_DRAMTMG1_T_RC_DEFVAL 0x00080414 -#define DDRC_DRAMTMG1_T_RC_SHIFT 0 -#define DDRC_DRAMTMG1_T_RC_MASK 0x0000007FU +#define DDRC_DRAMTMG1_T_RC_DEFVAL 0x00080414 +#define DDRC_DRAMTMG1_T_RC_SHIFT 0 +#define DDRC_DRAMTMG1_T_RC_MASK 0x0000007FU -/*Set to WL Time from write command to write data on SDRAM interface. This must be set to WL. For mDDR, it should normally be s - t to 1. Note that, depending on the PHY, if using RDIMM, it may be necessary to use a value of WL + 1 to compensate for the e - tra cycle of latency through the RDIMM For configurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above - equation by 2, and round it up to next integer. This register field is not required for DDR2 and DDR3 (except if MEMC_TRAININ - is set), as the DFI read and write latencies defined in DFITMG0 and DFITMG1 are sufficient for those protocols Unit: clocks*/ +/* +* Set to WL Time from write command to write data on SDRAM interface. This + * must be set to WL. For mDDR, it should normally be set to 1. Note that, + * depending on the PHY, if using RDIMM, it may be necessary to use a valu + * e of WL + 1 to compensate for the extra cycle of latency through the RDI + * MM For configurations with MEMC_FREQ_RATIO=2, divide the value calculate + * d using the above equation by 2, and round it up to next integer. This r + * egister field is not required for DDR2 and DDR3 (except if MEMC_TRAINING + * is set), as the DFI read and write latencies defined in DFITMG0 and DFI + * TMG1 are sufficient for those protocols Unit: clocks +*/ #undef DDRC_DRAMTMG2_WRITE_LATENCY_DEFVAL #undef DDRC_DRAMTMG2_WRITE_LATENCY_SHIFT #undef DDRC_DRAMTMG2_WRITE_LATENCY_MASK -#define DDRC_DRAMTMG2_WRITE_LATENCY_DEFVAL 0x0305060D -#define DDRC_DRAMTMG2_WRITE_LATENCY_SHIFT 24 -#define DDRC_DRAMTMG2_WRITE_LATENCY_MASK 0x3F000000U +#define DDRC_DRAMTMG2_WRITE_LATENCY_DEFVAL 0x0305060D +#define DDRC_DRAMTMG2_WRITE_LATENCY_SHIFT 24 +#define DDRC_DRAMTMG2_WRITE_LATENCY_MASK 0x3F000000U -/*Set to RL Time from read command to read data on SDRAM interface. This must be set to RL. Note that, depending on the PHY, if - using RDIMM, it mat be necessary to use a value of RL + 1 to compensate for the extra cycle of latency through the RDIMM For - onfigurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next inte - er. This register field is not required for DDR2 and DDR3 (except if MEMC_TRAINING is set), as the DFI read and write latenci - s defined in DFITMG0 and DFITMG1 are sufficient for those protocols Unit: clocks*/ +/* +* Set to RL Time from read command to read data on SDRAM interface. This m + * ust be set to RL. Note that, depending on the PHY, if using RDIMM, it ma + * t be necessary to use a value of RL + 1 to compensate for the extra cycl + * e of latency through the RDIMM For configurations with MEMC_FREQ_RATIO=2 + * , divide the value calculated using the above equation by 2, and round i + * t up to next integer. This register field is not required for DDR2 and D + * DR3 (except if MEMC_TRAINING is set), as the DFI read and write latencie + * s defined in DFITMG0 and DFITMG1 are sufficient for those protocols Unit + * : clocks +*/ #undef DDRC_DRAMTMG2_READ_LATENCY_DEFVAL #undef DDRC_DRAMTMG2_READ_LATENCY_SHIFT #undef DDRC_DRAMTMG2_READ_LATENCY_MASK -#define DDRC_DRAMTMG2_READ_LATENCY_DEFVAL 0x0305060D -#define DDRC_DRAMTMG2_READ_LATENCY_SHIFT 16 -#define DDRC_DRAMTMG2_READ_LATENCY_MASK 0x003F0000U +#define DDRC_DRAMTMG2_READ_LATENCY_DEFVAL 0x0305060D +#define DDRC_DRAMTMG2_READ_LATENCY_SHIFT 16 +#define DDRC_DRAMTMG2_READ_LATENCY_MASK 0x003F0000U -/*DDR2/3/mDDR: RL + BL/2 + 2 - WL DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL LPDDR2/LPDDR3: RL + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL - PDDR4(DQ ODT is Disabled): RL + BL/2 + RU(tDQSCKmax/tCK) + WR_PREAMBLE + RD_POSTAMBLE - WL LPDDR4(DQ ODT is Enabled) : RL + B - /2 + RU(tDQSCKmax/tCK) + RD_POSTAMBLE - ODTLon - RU(tODTon(min)/tCK) Minimum time from read command to write command. Include - time for bus turnaround and all per-bank, per-rank, and global constraints. Unit: Clocks. Where: - WL = write latency - BL = - urst length. This must match the value programmed in the BL bit of the mode register to the SDRAM - RL = read latency = CAS l - tency - WR_PREAMBLE = write preamble. This is unique to DDR4 and LPDDR4. - RD_POSTAMBLE = read postamble. This is unique to L - DDR4. For LPDDR2/LPDDR3/LPDDR4, if derating is enabled (DERATEEN.derate_enable=1), derated tDQSCKmax should be used. For conf - gurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next integer.*/ +/* +* DDR2/3/mDDR: RL + BL/2 + 2 - WL DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL L + * PDDR2/LPDDR3: RL + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL LPDDR4(DQ ODT is Di + * sabled): RL + BL/2 + RU(tDQSCKmax/tCK) + WR_PREAMBLE + RD_POSTAMBLE - WL + * LPDDR4(DQ ODT is Enabled) : RL + BL/2 + RU(tDQSCKmax/tCK) + RD_POSTAMBL + * E - ODTLon - RU(tODTon(min)/tCK) Minimum time from read command to write + * command. Include time for bus turnaround and all per-bank, per-rank, an + * d global constraints. Unit: Clocks. Where: - WL = write latency - BL = b + * urst length. This must match the value programmed in the BL bit of the m + * ode register to the SDRAM - RL = read latency = CAS latency - WR_PREAMBL + * E = write preamble. This is unique to DDR4 and LPDDR4. - RD_POSTAMBLE = + * read postamble. This is unique to LPDDR4. For LPDDR2/LPDDR3/LPDDR4, if d + * erating is enabled (DERATEEN.derate_enable=1), derated tDQSCKmax should + * be used. For configurations with MEMC_FREQ_RATIO=2, divide the value cal + * culated using the above equation by 2, and round it up to next integer. +*/ #undef DDRC_DRAMTMG2_RD2WR_DEFVAL #undef DDRC_DRAMTMG2_RD2WR_SHIFT #undef DDRC_DRAMTMG2_RD2WR_MASK -#define DDRC_DRAMTMG2_RD2WR_DEFVAL 0x0305060D -#define DDRC_DRAMTMG2_RD2WR_SHIFT 8 -#define DDRC_DRAMTMG2_RD2WR_MASK 0x00003F00U +#define DDRC_DRAMTMG2_RD2WR_DEFVAL 0x0305060D +#define DDRC_DRAMTMG2_RD2WR_SHIFT 8 +#define DDRC_DRAMTMG2_RD2WR_MASK 0x00003F00U -/*DDR4: CWL + PL + BL/2 + tWTR_L Others: CWL + BL/2 + tWTR In DDR4, minimum time from write command to read command for same ba - k group. In others, minimum time from write command to read command. Includes time for bus turnaround, recovery times, and al - per-bank, per-rank, and global constraints. Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity latency - BL = burs - length. This must match the value programmed in the BL bit of the mode register to the SDRAM - tWTR_L = internal write to re - d command delay for same bank group. This comes directly from the SDRAM specification. - tWTR = internal write to read comman - delay. This comes directly from the SDRAM specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 operation. For configu - ations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next integer.*/ +/* +* DDR4: CWL + PL + BL/2 + tWTR_L Others: CWL + BL/2 + tWTR In DDR4, minimu + * m time from write command to read command for same bank group. In others + * , minimum time from write command to read command. Includes time for bus + * turnaround, recovery times, and all per-bank, per-rank, and global cons + * traints. Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity la + * tency - BL = burst length. This must match the value programmed in the B + * L bit of the mode register to the SDRAM - tWTR_L = internal write to rea + * d command delay for same bank group. This comes directly from the SDRAM + * specification. - tWTR = internal write to read command delay. This comes + * directly from the SDRAM specification. Add one extra cycle for LPDDR2/L + * PDDR3/LPDDR4 operation. For configurations with MEMC_FREQ_RATIO=2, divid + * e the value calculated using the above equation by 2, and round it up to + * next integer. +*/ #undef DDRC_DRAMTMG2_WR2RD_DEFVAL #undef DDRC_DRAMTMG2_WR2RD_SHIFT #undef DDRC_DRAMTMG2_WR2RD_MASK -#define DDRC_DRAMTMG2_WR2RD_DEFVAL 0x0305060D -#define DDRC_DRAMTMG2_WR2RD_SHIFT 0 -#define DDRC_DRAMTMG2_WR2RD_MASK 0x0000003FU +#define DDRC_DRAMTMG2_WR2RD_DEFVAL 0x0305060D +#define DDRC_DRAMTMG2_WR2RD_SHIFT 0 +#define DDRC_DRAMTMG2_WR2RD_MASK 0x0000003FU -/*Time to wait after a mode register write or read (MRW or MRR). Present only in designs configured to support LPDDR2, LPDDR3 o - LPDDR4. LPDDR2 typically requires value of 5. LPDDR3 typically requires value of 10. LPDDR4: Set this to the larger of tMRW - nd tMRWCKEL. For LPDDR2, this register is used for the time from a MRW/MRR to all other commands. For LDPDR3, this register i - used for the time from a MRW/MRR to a MRW/MRR.*/ +/* +* Time to wait after a mode register write or read (MRW or MRR). Present o + * nly in designs configured to support LPDDR2, LPDDR3 or LPDDR4. LPDDR2 ty + * pically requires value of 5. LPDDR3 typically requires value of 10. LPDD + * R4: Set this to the larger of tMRW and tMRWCKEL. For LPDDR2, this regist + * er is used for the time from a MRW/MRR to all other commands. For LDPDR3 + * , this register is used for the time from a MRW/MRR to a MRW/MRR. +*/ #undef DDRC_DRAMTMG3_T_MRW_DEFVAL #undef DDRC_DRAMTMG3_T_MRW_SHIFT #undef DDRC_DRAMTMG3_T_MRW_MASK -#define DDRC_DRAMTMG3_T_MRW_DEFVAL 0x0050400C -#define DDRC_DRAMTMG3_T_MRW_SHIFT 20 -#define DDRC_DRAMTMG3_T_MRW_MASK 0x3FF00000U +#define DDRC_DRAMTMG3_T_MRW_DEFVAL 0x0050400C +#define DDRC_DRAMTMG3_T_MRW_SHIFT 20 +#define DDRC_DRAMTMG3_T_MRW_MASK 0x3FF00000U -/*tMRD: Cycles to wait after a mode register write or read. Depending on the connected SDRAM, tMRD represents: DDR2/mDDR: Time - rom MRS to any command DDR3/4: Time from MRS to MRS command LPDDR2: not used LPDDR3/4: Time from MRS to non-MRS command For c - nfigurations with MEMC_FREQ_RATIO=2, program this to (tMRD/2) and round it up to the next integer value. If C/A parity for DD - 4 is used, set to tMRD_PAR(tMOD+PL) instead.*/ +/* +* tMRD: Cycles to wait after a mode register write or read. Depending on t + * he connected SDRAM, tMRD represents: DDR2/mDDR: Time from MRS to any com + * mand DDR3/4: Time from MRS to MRS command LPDDR2: not used LPDDR3/4: Tim + * e from MRS to non-MRS command For configurations with MEMC_FREQ_RATIO=2, + * program this to (tMRD/2) and round it up to the next integer value. If + * C/A parity for DDR4 is used, set to tMRD_PAR(tMOD+PL) instead. +*/ #undef DDRC_DRAMTMG3_T_MRD_DEFVAL #undef DDRC_DRAMTMG3_T_MRD_SHIFT #undef DDRC_DRAMTMG3_T_MRD_MASK -#define DDRC_DRAMTMG3_T_MRD_DEFVAL 0x0050400C -#define DDRC_DRAMTMG3_T_MRD_SHIFT 12 -#define DDRC_DRAMTMG3_T_MRD_MASK 0x0003F000U +#define DDRC_DRAMTMG3_T_MRD_DEFVAL 0x0050400C +#define DDRC_DRAMTMG3_T_MRD_SHIFT 12 +#define DDRC_DRAMTMG3_T_MRD_MASK 0x0003F000U -/*tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode command and following non-load mode command. If C/A pari - y for DDR4 is used, set to tMOD_PAR(tMOD+PL) instead. Set to tMOD if MEMC_FREQ_RATIO=1, or tMOD/2 (rounded up to next integer - if MEMC_FREQ_RATIO=2. Note that if using RDIMM, depending on the PHY, it may be necessary to use a value of tMOD + 1 or (tMO - + 1)/2 to compensate for the extra cycle of latency applied to mode register writes by the RDIMM chip.*/ +/* +* tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode com + * mand and following non-load mode command. If C/A parity for DDR4 is used + * , set to tMOD_PAR(tMOD+PL) instead. Set to tMOD if MEMC_FREQ_RATIO=1, or + * tMOD/2 (rounded up to next integer) if MEMC_FREQ_RATIO=2. Note that if + * using RDIMM, depending on the PHY, it may be necessary to use a value of + * tMOD + 1 or (tMOD + 1)/2 to compensate for the extra cycle of latency a + * pplied to mode register writes by the RDIMM chip. +*/ #undef DDRC_DRAMTMG3_T_MOD_DEFVAL #undef DDRC_DRAMTMG3_T_MOD_SHIFT #undef DDRC_DRAMTMG3_T_MOD_MASK -#define DDRC_DRAMTMG3_T_MOD_DEFVAL 0x0050400C -#define DDRC_DRAMTMG3_T_MOD_SHIFT 0 -#define DDRC_DRAMTMG3_T_MOD_MASK 0x000003FFU +#define DDRC_DRAMTMG3_T_MOD_DEFVAL 0x0050400C +#define DDRC_DRAMTMG3_T_MOD_SHIFT 0 +#define DDRC_DRAMTMG3_T_MOD_MASK 0x000003FFU -/*tRCD - tAL: Minimum time from activate to read or write command to same bank. For configurations with MEMC_FREQ_RATIO=2, prog - am this to ((tRCD - tAL)/2) and round it up to the next integer value. Minimum value allowed for this register is 1, which im - lies minimum (tRCD - tAL) value to be 2 in configurations with MEMC_FREQ_RATIO=2. Unit: Clocks.*/ +/* +* tRCD - tAL: Minimum time from activate to read or write command to same + * bank. For configurations with MEMC_FREQ_RATIO=2, program this to ((tRCD + * - tAL)/2) and round it up to the next integer value. Minimum value allow + * ed for this register is 1, which implies minimum (tRCD - tAL) value to b + * e 2 in configurations with MEMC_FREQ_RATIO=2. Unit: Clocks. +*/ #undef DDRC_DRAMTMG4_T_RCD_DEFVAL #undef DDRC_DRAMTMG4_T_RCD_SHIFT #undef DDRC_DRAMTMG4_T_RCD_MASK -#define DDRC_DRAMTMG4_T_RCD_DEFVAL 0x05040405 -#define DDRC_DRAMTMG4_T_RCD_SHIFT 24 -#define DDRC_DRAMTMG4_T_RCD_MASK 0x1F000000U +#define DDRC_DRAMTMG4_T_RCD_DEFVAL 0x05040405 +#define DDRC_DRAMTMG4_T_RCD_SHIFT 24 +#define DDRC_DRAMTMG4_T_RCD_MASK 0x1F000000U -/*DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank group. Others: tCCD: This is the minimum - time between two reads or two writes. For configurations with MEMC_FREQ_RATIO=2, program this to (tCCD_L/2 or tCCD/2) and rou - d it up to the next integer value. Unit: clocks.*/ +/* +* DDR4: tCCD_L: This is the minimum time between two reads or two writes f + * or same bank group. Others: tCCD: This is the minimum time between two r + * eads or two writes. For configurations with MEMC_FREQ_RATIO=2, program t + * his to (tCCD_L/2 or tCCD/2) and round it up to the next integer value. U + * nit: clocks. +*/ #undef DDRC_DRAMTMG4_T_CCD_DEFVAL #undef DDRC_DRAMTMG4_T_CCD_SHIFT #undef DDRC_DRAMTMG4_T_CCD_MASK -#define DDRC_DRAMTMG4_T_CCD_DEFVAL 0x05040405 -#define DDRC_DRAMTMG4_T_CCD_SHIFT 16 -#define DDRC_DRAMTMG4_T_CCD_MASK 0x000F0000U +#define DDRC_DRAMTMG4_T_CCD_DEFVAL 0x05040405 +#define DDRC_DRAMTMG4_T_CCD_SHIFT 16 +#define DDRC_DRAMTMG4_T_CCD_MASK 0x000F0000U -/*DDR4: tRRD_L: Minimum time between activates from bank 'a' to bank 'b' for same bank group. Others: tRRD: Minimum time betwee - activates from bank 'a' to bank 'b'For configurations with MEMC_FREQ_RATIO=2, program this to (tRRD_L/2 or tRRD/2) and round - it up to the next integer value. Unit: Clocks.*/ +/* +* DDR4: tRRD_L: Minimum time between activates from bank 'a' to bank 'b' f + * or same bank group. Others: tRRD: Minimum time between activates from ba + * nk 'a' to bank 'b'For configurations with MEMC_FREQ_RATIO=2, program thi + * s to (tRRD_L/2 or tRRD/2) and round it up to the next integer value. Uni + * t: Clocks. +*/ #undef DDRC_DRAMTMG4_T_RRD_DEFVAL #undef DDRC_DRAMTMG4_T_RRD_SHIFT #undef DDRC_DRAMTMG4_T_RRD_MASK -#define DDRC_DRAMTMG4_T_RRD_DEFVAL 0x05040405 -#define DDRC_DRAMTMG4_T_RRD_SHIFT 8 -#define DDRC_DRAMTMG4_T_RRD_MASK 0x00000F00U +#define DDRC_DRAMTMG4_T_RRD_DEFVAL 0x05040405 +#define DDRC_DRAMTMG4_T_RRD_SHIFT 8 +#define DDRC_DRAMTMG4_T_RRD_MASK 0x00000F00U -/*tRP: Minimum time from precharge to activate of same bank. For MEMC_FREQ_RATIO=1 configurations, t_rp should be set to RoundU - (tRP/tCK). For MEMC_FREQ_RATIO=2 configurations, t_rp should be set to RoundDown(RoundUp(tRP/tCK)/2) + 1. For MEMC_FREQ_RATIO - 2 configurations in LPDDR4, t_rp should be set to RoundUp(RoundUp(tRP/tCK)/2). Unit: Clocks.*/ +/* +* tRP: Minimum time from precharge to activate of same bank. For MEMC_FREQ + * _RATIO=1 configurations, t_rp should be set to RoundUp(tRP/tCK). For MEM + * C_FREQ_RATIO=2 configurations, t_rp should be set to RoundDown(RoundUp(t + * RP/tCK)/2) + 1. For MEMC_FREQ_RATIO=2 configurations in LPDDR4, t_rp sho + * uld be set to RoundUp(RoundUp(tRP/tCK)/2). Unit: Clocks. +*/ #undef DDRC_DRAMTMG4_T_RP_DEFVAL #undef DDRC_DRAMTMG4_T_RP_SHIFT #undef DDRC_DRAMTMG4_T_RP_MASK -#define DDRC_DRAMTMG4_T_RP_DEFVAL 0x05040405 -#define DDRC_DRAMTMG4_T_RP_SHIFT 0 -#define DDRC_DRAMTMG4_T_RP_MASK 0x0000001FU +#define DDRC_DRAMTMG4_T_RP_DEFVAL 0x05040405 +#define DDRC_DRAMTMG4_T_RP_SHIFT 0 +#define DDRC_DRAMTMG4_T_RP_MASK 0x0000001FU -/*This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stab - e time before SRX. Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEH - DDR2: 1 - DDR3: tCKSRX - DDR4: - tCKSRX For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it up to next in - eger.*/ +/* +* This is the time before Self Refresh Exit that CK is maintained as a val + * id clock before issuing SRX. Specifies the clock stable time before SRX. + * Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCK + * EH - DDR2: 1 - DDR3: tCKSRX - DDR4: tCKSRX For configurations with MEMC_ + * FREQ_RATIO=2, program this to recommended value divided by two and round + * it up to next integer. +*/ #undef DDRC_DRAMTMG5_T_CKSRX_DEFVAL #undef DDRC_DRAMTMG5_T_CKSRX_SHIFT #undef DDRC_DRAMTMG5_T_CKSRX_MASK -#define DDRC_DRAMTMG5_T_CKSRX_DEFVAL 0x05050403 -#define DDRC_DRAMTMG5_T_CKSRX_SHIFT 24 -#define DDRC_DRAMTMG5_T_CKSRX_MASK 0x0F000000U +#define DDRC_DRAMTMG5_T_CKSRX_DEFVAL 0x05050403 +#define DDRC_DRAMTMG5_T_CKSRX_SHIFT 24 +#define DDRC_DRAMTMG5_T_CKSRX_MASK 0x0F000000U -/*This is the time after Self Refresh Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay afte - SRE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL - DDR2: 1 - DDR3: max (10 ns, 5 tCK) - DDR4: - ax (10 ns, 5 tCK) For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it up - to next integer.*/ +/* +* This is the time after Self Refresh Down Entry that CK is maintained as + * a valid clock. Specifies the clock disable delay after SRE. Recommended + * settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL - DDR2: 1 + * - DDR3: max (10 ns, 5 tCK) - DDR4: max (10 ns, 5 tCK) For configurations + * with MEMC_FREQ_RATIO=2, program this to recommended value divided by tw + * o and round it up to next integer. +*/ #undef DDRC_DRAMTMG5_T_CKSRE_DEFVAL #undef DDRC_DRAMTMG5_T_CKSRE_SHIFT #undef DDRC_DRAMTMG5_T_CKSRE_MASK -#define DDRC_DRAMTMG5_T_CKSRE_DEFVAL 0x05050403 -#define DDRC_DRAMTMG5_T_CKSRE_SHIFT 16 -#define DDRC_DRAMTMG5_T_CKSRE_MASK 0x000F0000U +#define DDRC_DRAMTMG5_T_CKSRE_DEFVAL 0x05050403 +#define DDRC_DRAMTMG5_T_CKSRE_SHIFT 16 +#define DDRC_DRAMTMG5_T_CKSRE_MASK 0x000F0000U -/*Minimum CKE low width for Self refresh or Self refresh power down entry to exit timing in memory clock cycles. Recommended se - tings: - mDDR: tRFC - LPDDR2: tCKESR - LPDDR3: tCKESR - LPDDR4: max(tCKELPD, tSR) - DDR2: tCKE - DDR3: tCKE + 1 - DDR4: tCKE - 1 For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it up to next intege - .*/ +/* +* Minimum CKE low width for Self refresh or Self refresh power down entry + * to exit timing in memory clock cycles. Recommended settings: - mDDR: tRF + * C - LPDDR2: tCKESR - LPDDR3: tCKESR - LPDDR4: max(tCKELPD, tSR) - DDR2: + * tCKE - DDR3: tCKE + 1 - DDR4: tCKE + 1 For configurations with MEMC_FREQ + * _RATIO=2, program this to recommended value divided by two and round it + * up to next integer. +*/ #undef DDRC_DRAMTMG5_T_CKESR_DEFVAL #undef DDRC_DRAMTMG5_T_CKESR_SHIFT #undef DDRC_DRAMTMG5_T_CKESR_MASK -#define DDRC_DRAMTMG5_T_CKESR_DEFVAL 0x05050403 -#define DDRC_DRAMTMG5_T_CKESR_SHIFT 8 -#define DDRC_DRAMTMG5_T_CKESR_MASK 0x00003F00U +#define DDRC_DRAMTMG5_T_CKESR_DEFVAL 0x05050403 +#define DDRC_DRAMTMG5_T_CKESR_SHIFT 8 +#define DDRC_DRAMTMG5_T_CKESR_MASK 0x00003F00U -/*Minimum number of cycles of CKE HIGH/LOW during power-down and self refresh. - LPDDR2/LPDDR3 mode: Set this to the larger of - CKE or tCKESR - LPDDR4 mode: Set this to the larger of tCKE, tCKELPD or tSR. - Non-LPDDR2/non-LPDDR3/non-LPDDR4 designs: Set - his to tCKE value. For configurations with MEMC_FREQ_RATIO=2, program this to (value described above)/2 and round it up to th - next integer value. Unit: Clocks.*/ +/* +* Minimum number of cycles of CKE HIGH/LOW during power-down and self refr + * esh. - LPDDR2/LPDDR3 mode: Set this to the larger of tCKE or tCKESR - LP + * DDR4 mode: Set this to the larger of tCKE, tCKELPD or tSR. - Non-LPDDR2/ + * non-LPDDR3/non-LPDDR4 designs: Set this to tCKE value. For configuration + * s with MEMC_FREQ_RATIO=2, program this to (value described above)/2 and + * round it up to the next integer value. Unit: Clocks. +*/ #undef DDRC_DRAMTMG5_T_CKE_DEFVAL #undef DDRC_DRAMTMG5_T_CKE_SHIFT #undef DDRC_DRAMTMG5_T_CKE_MASK -#define DDRC_DRAMTMG5_T_CKE_DEFVAL 0x05050403 -#define DDRC_DRAMTMG5_T_CKE_SHIFT 0 -#define DDRC_DRAMTMG5_T_CKE_MASK 0x0000001FU +#define DDRC_DRAMTMG5_T_CKE_DEFVAL 0x05050403 +#define DDRC_DRAMTMG5_T_CKE_SHIFT 0 +#define DDRC_DRAMTMG5_T_CKE_MASK 0x0000001FU -/*This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after - PDE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 For configurations with MEMC_FREQ_RATIO=2, program this to recom - ended value divided by two and round it up to next integer. This is only present for designs supporting mDDR or LPDDR2/LPDDR3 - devices.*/ +/* +* This is the time after Deep Power Down Entry that CK is maintained as a + * valid clock. Specifies the clock disable delay after DPDE. Recommended s + * ettings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 For configurations with MEMC_ + * FREQ_RATIO=2, program this to recommended value divided by two and round + * it up to next integer. This is only present for designs supporting mDDR + * or LPDDR2/LPDDR3 devices. +*/ #undef DDRC_DRAMTMG6_T_CKDPDE_DEFVAL #undef DDRC_DRAMTMG6_T_CKDPDE_SHIFT #undef DDRC_DRAMTMG6_T_CKDPDE_MASK -#define DDRC_DRAMTMG6_T_CKDPDE_DEFVAL 0x02020005 -#define DDRC_DRAMTMG6_T_CKDPDE_SHIFT 24 -#define DDRC_DRAMTMG6_T_CKDPDE_MASK 0x0F000000U +#define DDRC_DRAMTMG6_T_CKDPDE_DEFVAL 0x02020005 +#define DDRC_DRAMTMG6_T_CKDPDE_SHIFT 24 +#define DDRC_DRAMTMG6_T_CKDPDE_MASK 0x0F000000U -/*This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock - table time before DPDX. Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 For configurations with MEMC_FREQ_RATIO=2, pr - gram this to recommended value divided by two and round it up to next integer. This is only present for designs supporting mD - R or LPDDR2 devices.*/ +/* +* This is the time before Deep Power Down Exit that CK is maintained as a + * valid clock before issuing DPDX. Specifies the clock stable time before + * DPDX. Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 For config + * urations with MEMC_FREQ_RATIO=2, program this to recommended value divid + * ed by two and round it up to next integer. This is only present for desi + * gns supporting mDDR or LPDDR2 devices. +*/ #undef DDRC_DRAMTMG6_T_CKDPDX_DEFVAL #undef DDRC_DRAMTMG6_T_CKDPDX_SHIFT #undef DDRC_DRAMTMG6_T_CKDPDX_MASK -#define DDRC_DRAMTMG6_T_CKDPDX_DEFVAL 0x02020005 -#define DDRC_DRAMTMG6_T_CKDPDX_SHIFT 16 -#define DDRC_DRAMTMG6_T_CKDPDX_MASK 0x000F0000U +#define DDRC_DRAMTMG6_T_CKDPDX_DEFVAL 0x02020005 +#define DDRC_DRAMTMG6_T_CKDPDX_SHIFT 16 +#define DDRC_DRAMTMG6_T_CKDPDX_MASK 0x000F0000U -/*This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing Clock Stop Exit. Specifies the - lock stable time before next command after Clock Stop Exit. Recommended settings: - mDDR: 1 - LPDDR2: tXP + 2 - LPDDR3: tXP + - 2 - LPDDR4: tXP + 2 For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it - p to next integer. This is only present for designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices.*/ +/* +* This is the time before Clock Stop Exit that CK is maintained as a valid + * clock before issuing Clock Stop Exit. Specifies the clock stable time b + * efore next command after Clock Stop Exit. Recommended settings: - mDDR: + * 1 - LPDDR2: tXP + 2 - LPDDR3: tXP + 2 - LPDDR4: tXP + 2 For configuratio + * ns with MEMC_FREQ_RATIO=2, program this to recommended value divided by + * two and round it up to next integer. This is only present for designs su + * pporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices. +*/ #undef DDRC_DRAMTMG6_T_CKCSX_DEFVAL #undef DDRC_DRAMTMG6_T_CKCSX_SHIFT #undef DDRC_DRAMTMG6_T_CKCSX_MASK -#define DDRC_DRAMTMG6_T_CKCSX_DEFVAL 0x02020005 -#define DDRC_DRAMTMG6_T_CKCSX_SHIFT 0 -#define DDRC_DRAMTMG6_T_CKCSX_MASK 0x0000000FU +#define DDRC_DRAMTMG6_T_CKCSX_DEFVAL 0x02020005 +#define DDRC_DRAMTMG6_T_CKCSX_SHIFT 0 +#define DDRC_DRAMTMG6_T_CKCSX_MASK 0x0000000FU -/*This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. - ecommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL For configurations with MEMC_FREQ_RATIO=2, program t - is to recommended value divided by two and round it up to next integer. This is only present for designs supporting mDDR or L - DDR2/LPDDR3/LPDDR4 devices.*/ +/* +* This is the time after Power Down Entry that CK is maintained as a valid + * clock. Specifies the clock disable delay after PDE. Recommended setting + * s: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL For configuration + * s with MEMC_FREQ_RATIO=2, program this to recommended value divided by t + * wo and round it up to next integer. This is only present for designs sup + * porting mDDR or LPDDR2/LPDDR3/LPDDR4 devices. +*/ #undef DDRC_DRAMTMG7_T_CKPDE_DEFVAL #undef DDRC_DRAMTMG7_T_CKPDE_SHIFT #undef DDRC_DRAMTMG7_T_CKPDE_MASK -#define DDRC_DRAMTMG7_T_CKPDE_DEFVAL 0x00000202 -#define DDRC_DRAMTMG7_T_CKPDE_SHIFT 8 -#define DDRC_DRAMTMG7_T_CKPDE_MASK 0x00000F00U +#define DDRC_DRAMTMG7_T_CKPDE_DEFVAL 0x00000202 +#define DDRC_DRAMTMG7_T_CKPDE_SHIFT 8 +#define DDRC_DRAMTMG7_T_CKPDE_MASK 0x00000F00U -/*This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable - time before PDX. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: 2 For configurations with MEMC_FREQ_RATIO= - , program this to recommended value divided by two and round it up to next integer. This is only present for designs supporti - g mDDR or LPDDR2/LPDDR3/LPDDR4 devices.*/ +/* +* This is the time before Power Down Exit that CK is maintained as a valid + * clock before issuing PDX. Specifies the clock stable time before PDX. R + * ecommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: 2 For c + * onfigurations with MEMC_FREQ_RATIO=2, program this to recommended value + * divided by two and round it up to next integer. This is only present for + * designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices. +*/ #undef DDRC_DRAMTMG7_T_CKPDX_DEFVAL #undef DDRC_DRAMTMG7_T_CKPDX_SHIFT #undef DDRC_DRAMTMG7_T_CKPDX_MASK -#define DDRC_DRAMTMG7_T_CKPDX_DEFVAL 0x00000202 -#define DDRC_DRAMTMG7_T_CKPDX_SHIFT 0 -#define DDRC_DRAMTMG7_T_CKPDX_MASK 0x0000000FU +#define DDRC_DRAMTMG7_T_CKPDX_DEFVAL 0x00000202 +#define DDRC_DRAMTMG7_T_CKPDX_SHIFT 0 +#define DDRC_DRAMTMG7_T_CKPDX_MASK 0x0000000FU -/*tXS_FAST: Exit Self Refresh to ZQCL, ZQCS and MRS (only CL, WR, RTP and Geardown mode). For configurations with MEMC_FREQ_RAT - O=2, program this to the above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: Thi - is applicable to only ZQCL/ZQCS commands. Note: Ensure this is less than or equal to t_xs_x32.*/ +/* +* tXS_FAST: Exit Self Refresh to ZQCL, ZQCS and MRS (only CL, WR, RTP and + * Geardown mode). For configurations with MEMC_FREQ_RATIO=2, program this + * to the above value divided by 2 and round up to next integer value. Unit + * : Multiples of 32 clocks. Note: This is applicable to only ZQCL/ZQCS com + * mands. Note: Ensure this is less than or equal to t_xs_x32. +*/ #undef DDRC_DRAMTMG8_T_XS_FAST_X32_DEFVAL #undef DDRC_DRAMTMG8_T_XS_FAST_X32_SHIFT #undef DDRC_DRAMTMG8_T_XS_FAST_X32_MASK -#define DDRC_DRAMTMG8_T_XS_FAST_X32_DEFVAL 0x03034405 -#define DDRC_DRAMTMG8_T_XS_FAST_X32_SHIFT 24 -#define DDRC_DRAMTMG8_T_XS_FAST_X32_MASK 0x7F000000U +#define DDRC_DRAMTMG8_T_XS_FAST_X32_DEFVAL 0x03034405 +#define DDRC_DRAMTMG8_T_XS_FAST_X32_SHIFT 24 +#define DDRC_DRAMTMG8_T_XS_FAST_X32_MASK 0x7F000000U -/*tXS_ABORT: Exit Self Refresh to commands not requiring a locked DLL in Self Refresh Abort. For configurations with MEMC_FREQ_ - ATIO=2, program this to the above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: - nsure this is less than or equal to t_xs_x32.*/ +/* +* tXS_ABORT: Exit Self Refresh to commands not requiring a locked DLL in S + * elf Refresh Abort. For configurations with MEMC_FREQ_RATIO=2, program th + * is to the above value divided by 2 and round up to next integer value. U + * nit: Multiples of 32 clocks. Note: Ensure this is less than or equal to + * t_xs_x32. +*/ #undef DDRC_DRAMTMG8_T_XS_ABORT_X32_DEFVAL #undef DDRC_DRAMTMG8_T_XS_ABORT_X32_SHIFT #undef DDRC_DRAMTMG8_T_XS_ABORT_X32_MASK -#define DDRC_DRAMTMG8_T_XS_ABORT_X32_DEFVAL 0x03034405 -#define DDRC_DRAMTMG8_T_XS_ABORT_X32_SHIFT 16 -#define DDRC_DRAMTMG8_T_XS_ABORT_X32_MASK 0x007F0000U +#define DDRC_DRAMTMG8_T_XS_ABORT_X32_DEFVAL 0x03034405 +#define DDRC_DRAMTMG8_T_XS_ABORT_X32_SHIFT 16 +#define DDRC_DRAMTMG8_T_XS_ABORT_X32_MASK 0x007F0000U -/*tXSDLL: Exit Self Refresh to commands requiring a locked DLL. For configurations with MEMC_FREQ_RATIO=2, program this to the - bove value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: Used only for DDR2, DDR3 and - DR4 SDRAMs.*/ +/* +* tXSDLL: Exit Self Refresh to commands requiring a locked DLL. For config + * urations with MEMC_FREQ_RATIO=2, program this to the above value divided + * by 2 and round up to next integer value. Unit: Multiples of 32 clocks. + * Note: Used only for DDR2, DDR3 and DDR4 SDRAMs. +*/ #undef DDRC_DRAMTMG8_T_XS_DLL_X32_DEFVAL #undef DDRC_DRAMTMG8_T_XS_DLL_X32_SHIFT #undef DDRC_DRAMTMG8_T_XS_DLL_X32_MASK -#define DDRC_DRAMTMG8_T_XS_DLL_X32_DEFVAL 0x03034405 -#define DDRC_DRAMTMG8_T_XS_DLL_X32_SHIFT 8 -#define DDRC_DRAMTMG8_T_XS_DLL_X32_MASK 0x00007F00U +#define DDRC_DRAMTMG8_T_XS_DLL_X32_DEFVAL 0x03034405 +#define DDRC_DRAMTMG8_T_XS_DLL_X32_SHIFT 8 +#define DDRC_DRAMTMG8_T_XS_DLL_X32_MASK 0x00007F00U -/*tXS: Exit Self Refresh to commands not requiring a locked DLL. For configurations with MEMC_FREQ_RATIO=2, program this to the - above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: Used only for DDR2, DDR3 and - DDR4 SDRAMs.*/ +/* +* tXS: Exit Self Refresh to commands not requiring a locked DLL. For confi + * gurations with MEMC_FREQ_RATIO=2, program this to the above value divide + * d by 2 and round up to next integer value. Unit: Multiples of 32 clocks. + * Note: Used only for DDR2, DDR3 and DDR4 SDRAMs. +*/ #undef DDRC_DRAMTMG8_T_XS_X32_DEFVAL #undef DDRC_DRAMTMG8_T_XS_X32_SHIFT #undef DDRC_DRAMTMG8_T_XS_X32_MASK -#define DDRC_DRAMTMG8_T_XS_X32_DEFVAL 0x03034405 -#define DDRC_DRAMTMG8_T_XS_X32_SHIFT 0 -#define DDRC_DRAMTMG8_T_XS_X32_MASK 0x0000007FU +#define DDRC_DRAMTMG8_T_XS_X32_DEFVAL 0x03034405 +#define DDRC_DRAMTMG8_T_XS_X32_SHIFT 0 +#define DDRC_DRAMTMG8_T_XS_X32_MASK 0x0000007FU -/*DDR4 Write preamble mode - 0: 1tCK preamble - 1: 2tCK preamble Present only with MEMC_FREQ_RATIO=2*/ +/* +* DDR4 Write preamble mode - 0: 1tCK preamble - 1: 2tCK preamble Present o + * nly with MEMC_FREQ_RATIO=2 +*/ #undef DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_DEFVAL #undef DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_SHIFT #undef DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_MASK -#define DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_DEFVAL 0x0004040D -#define DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_SHIFT 30 -#define DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_MASK 0x40000000U +#define DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_DEFVAL 0x0004040D +#define DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_SHIFT 30 +#define DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_MASK 0x40000000U -/*tCCD_S: This is the minimum time between two reads or two writes for different bank group. For bank switching (from bank 'a' - o bank 'b'), the minimum time is this value + 1. For configurations with MEMC_FREQ_RATIO=2, program this to (tCCD_S/2) and ro - nd it up to the next integer value. Present only in designs configured to support DDR4. Unit: clocks.*/ +/* +* tCCD_S: This is the minimum time between two reads or two writes for dif + * ferent bank group. For bank switching (from bank 'a' to bank 'b'), the m + * inimum time is this value + 1. For configurations with MEMC_FREQ_RATIO=2 + * , program this to (tCCD_S/2) and round it up to the next integer value. + * Present only in designs configured to support DDR4. Unit: clocks. +*/ #undef DDRC_DRAMTMG9_T_CCD_S_DEFVAL #undef DDRC_DRAMTMG9_T_CCD_S_SHIFT #undef DDRC_DRAMTMG9_T_CCD_S_MASK -#define DDRC_DRAMTMG9_T_CCD_S_DEFVAL 0x0004040D -#define DDRC_DRAMTMG9_T_CCD_S_SHIFT 16 -#define DDRC_DRAMTMG9_T_CCD_S_MASK 0x00070000U +#define DDRC_DRAMTMG9_T_CCD_S_DEFVAL 0x0004040D +#define DDRC_DRAMTMG9_T_CCD_S_SHIFT 16 +#define DDRC_DRAMTMG9_T_CCD_S_MASK 0x00070000U -/*tRRD_S: Minimum time between activates from bank 'a' to bank 'b' for different bank group. For configurations with MEMC_FREQ_ - ATIO=2, program this to (tRRD_S/2) and round it up to the next integer value. Present only in designs configured to support D - R4. Unit: Clocks.*/ +/* +* tRRD_S: Minimum time between activates from bank 'a' to bank 'b' for dif + * ferent bank group. For configurations with MEMC_FREQ_RATIO=2, program th + * is to (tRRD_S/2) and round it up to the next integer value. Present only + * in designs configured to support DDR4. Unit: Clocks. +*/ #undef DDRC_DRAMTMG9_T_RRD_S_DEFVAL #undef DDRC_DRAMTMG9_T_RRD_S_SHIFT #undef DDRC_DRAMTMG9_T_RRD_S_MASK -#define DDRC_DRAMTMG9_T_RRD_S_DEFVAL 0x0004040D -#define DDRC_DRAMTMG9_T_RRD_S_SHIFT 8 -#define DDRC_DRAMTMG9_T_RRD_S_MASK 0x00000F00U +#define DDRC_DRAMTMG9_T_RRD_S_DEFVAL 0x0004040D +#define DDRC_DRAMTMG9_T_RRD_S_SHIFT 8 +#define DDRC_DRAMTMG9_T_RRD_S_MASK 0x00000F00U -/*CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command for different bank group. Includes time for bus turn - round, recovery times, and all per-bank, per-rank, and global constraints. Present only in designs configured to support DDR4 - Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity latency - BL = burst length. This must match the value programm - d in the BL bit of the mode register to the SDRAM - tWTR_S = internal write to read command delay for different bank group. T - is comes directly from the SDRAM specification. For configurations with MEMC_FREQ_RATIO=2, divide the value calculated using - he above equation by 2, and round it up to next integer.*/ +/* +* CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command + * for different bank group. Includes time for bus turnaround, recovery ti + * mes, and all per-bank, per-rank, and global constraints. Present only in + * designs configured to support DDR4. Unit: Clocks. Where: - CWL = CAS wr + * ite latency - PL = Parity latency - BL = burst length. This must match t + * he value programmed in the BL bit of the mode register to the SDRAM - tW + * TR_S = internal write to read command delay for different bank group. Th + * is comes directly from the SDRAM specification. For configurations with + * MEMC_FREQ_RATIO=2, divide the value calculated using the above equation + * by 2, and round it up to next integer. +*/ #undef DDRC_DRAMTMG9_WR2RD_S_DEFVAL #undef DDRC_DRAMTMG9_WR2RD_S_SHIFT #undef DDRC_DRAMTMG9_WR2RD_S_MASK -#define DDRC_DRAMTMG9_WR2RD_S_DEFVAL 0x0004040D -#define DDRC_DRAMTMG9_WR2RD_S_SHIFT 0 -#define DDRC_DRAMTMG9_WR2RD_S_MASK 0x0000003FU +#define DDRC_DRAMTMG9_WR2RD_S_DEFVAL 0x0004040D +#define DDRC_DRAMTMG9_WR2RD_S_SHIFT 0 +#define DDRC_DRAMTMG9_WR2RD_S_MASK 0x0000003FU -/*tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DLL. For configurations with MEMC_FREQ_RATIO=2, program - this to (tXMPDLL/2) and round it up to the next integer value. Present only in designs configured to support DDR4. Unit: Mult - ples of 32 clocks.*/ +/* +* tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DL + * L. For configurations with MEMC_FREQ_RATIO=2, program this to (tXMPDLL/2 + * ) and round it up to the next integer value. Present only in designs con + * figured to support DDR4. Unit: Multiples of 32 clocks. +*/ #undef DDRC_DRAMTMG11_POST_MPSM_GAP_X32_DEFVAL #undef DDRC_DRAMTMG11_POST_MPSM_GAP_X32_SHIFT #undef DDRC_DRAMTMG11_POST_MPSM_GAP_X32_MASK -#define DDRC_DRAMTMG11_POST_MPSM_GAP_X32_DEFVAL 0x440C021C -#define DDRC_DRAMTMG11_POST_MPSM_GAP_X32_SHIFT 24 -#define DDRC_DRAMTMG11_POST_MPSM_GAP_X32_MASK 0x7F000000U +#define DDRC_DRAMTMG11_POST_MPSM_GAP_X32_DEFVAL 0x440C021C +#define DDRC_DRAMTMG11_POST_MPSM_GAP_X32_SHIFT 24 +#define DDRC_DRAMTMG11_POST_MPSM_GAP_X32_MASK 0x7F000000U -/*tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge. For configurations with MEMC_FREQ_RATIO=2, program this t - RoundUp(tMPX_LH/2)+1. Present only in designs configured to support DDR4. Unit: clocks.*/ +/* +* tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge. For + * configurations with MEMC_FREQ_RATIO=2, program this to RoundUp(tMPX_LH/2 + * )+1. Present only in designs configured to support DDR4. Unit: clocks. +*/ #undef DDRC_DRAMTMG11_T_MPX_LH_DEFVAL #undef DDRC_DRAMTMG11_T_MPX_LH_SHIFT #undef DDRC_DRAMTMG11_T_MPX_LH_MASK -#define DDRC_DRAMTMG11_T_MPX_LH_DEFVAL 0x440C021C -#define DDRC_DRAMTMG11_T_MPX_LH_SHIFT 16 -#define DDRC_DRAMTMG11_T_MPX_LH_MASK 0x001F0000U +#define DDRC_DRAMTMG11_T_MPX_LH_DEFVAL 0x440C021C +#define DDRC_DRAMTMG11_T_MPX_LH_SHIFT 16 +#define DDRC_DRAMTMG11_T_MPX_LH_MASK 0x001F0000U -/*tMPX_S: Minimum time CS setup time to CKE. For configurations with MEMC_FREQ_RATIO=2, program this to (tMPX_S/2) and round it - up to the next integer value. Present only in designs configured to support DDR4. Unit: Clocks.*/ +/* +* tMPX_S: Minimum time CS setup time to CKE. For configurations with MEMC_ + * FREQ_RATIO=2, program this to (tMPX_S/2) and round it up to the next int + * eger value. Present only in designs configured to support DDR4. Unit: Cl + * ocks. +*/ #undef DDRC_DRAMTMG11_T_MPX_S_DEFVAL #undef DDRC_DRAMTMG11_T_MPX_S_SHIFT #undef DDRC_DRAMTMG11_T_MPX_S_MASK -#define DDRC_DRAMTMG11_T_MPX_S_DEFVAL 0x440C021C -#define DDRC_DRAMTMG11_T_MPX_S_SHIFT 8 -#define DDRC_DRAMTMG11_T_MPX_S_MASK 0x00000300U +#define DDRC_DRAMTMG11_T_MPX_S_DEFVAL 0x440C021C +#define DDRC_DRAMTMG11_T_MPX_S_SHIFT 8 +#define DDRC_DRAMTMG11_T_MPX_S_MASK 0x00000300U -/*tCKMPE: Minimum valid clock requirement after MPSM entry. Present only in designs configured to support DDR4. Unit: Clocks. F - r configurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next i - teger.*/ +/* +* tCKMPE: Minimum valid clock requirement after MPSM entry. Present only i + * n designs configured to support DDR4. Unit: Clocks. For configurations w + * ith MEMC_FREQ_RATIO=2, divide the value calculated using the above equat + * ion by 2, and round it up to next integer. +*/ #undef DDRC_DRAMTMG11_T_CKMPE_DEFVAL #undef DDRC_DRAMTMG11_T_CKMPE_SHIFT #undef DDRC_DRAMTMG11_T_CKMPE_MASK -#define DDRC_DRAMTMG11_T_CKMPE_DEFVAL 0x440C021C -#define DDRC_DRAMTMG11_T_CKMPE_SHIFT 0 -#define DDRC_DRAMTMG11_T_CKMPE_MASK 0x0000001FU +#define DDRC_DRAMTMG11_T_CKMPE_DEFVAL 0x440C021C +#define DDRC_DRAMTMG11_T_CKMPE_SHIFT 0 +#define DDRC_DRAMTMG11_T_CKMPE_MASK 0x0000001FU -/*tCMDCKE: Delay from valid command to CKE input LOW. Set this to the larger of tESCKE or tCMDCKE For configurations with MEMC_ - REQ_RATIO=2, program this to (max(tESCKE, tCMDCKE)/2) and round it up to next integer value.*/ +/* +* tCMDCKE: Delay from valid command to CKE input LOW. Set this to the larg + * er of tESCKE or tCMDCKE For configurations with MEMC_FREQ_RATIO=2, progr + * am this to (max(tESCKE, tCMDCKE)/2) and round it up to next integer valu + * e. +*/ #undef DDRC_DRAMTMG12_T_CMDCKE_DEFVAL #undef DDRC_DRAMTMG12_T_CMDCKE_SHIFT #undef DDRC_DRAMTMG12_T_CMDCKE_MASK -#define DDRC_DRAMTMG12_T_CMDCKE_DEFVAL 0x00020610 -#define DDRC_DRAMTMG12_T_CMDCKE_SHIFT 16 -#define DDRC_DRAMTMG12_T_CMDCKE_MASK 0x00030000U +#define DDRC_DRAMTMG12_T_CMDCKE_DEFVAL 0x00020610 +#define DDRC_DRAMTMG12_T_CMDCKE_SHIFT 16 +#define DDRC_DRAMTMG12_T_CMDCKE_MASK 0x00030000U -/*tCKEHCMD: Valid command requirement after CKE input HIGH. For configurations with MEMC_FREQ_RATIO=2, program this to (tCKEHCM - /2) and round it up to next integer value.*/ +/* +* tCKEHCMD: Valid command requirement after CKE input HIGH. For configurat + * ions with MEMC_FREQ_RATIO=2, program this to (tCKEHCMD/2) and round it u + * p to next integer value. +*/ #undef DDRC_DRAMTMG12_T_CKEHCMD_DEFVAL #undef DDRC_DRAMTMG12_T_CKEHCMD_SHIFT #undef DDRC_DRAMTMG12_T_CKEHCMD_MASK -#define DDRC_DRAMTMG12_T_CKEHCMD_DEFVAL 0x00020610 -#define DDRC_DRAMTMG12_T_CKEHCMD_SHIFT 8 -#define DDRC_DRAMTMG12_T_CKEHCMD_MASK 0x00000F00U +#define DDRC_DRAMTMG12_T_CKEHCMD_DEFVAL 0x00020610 +#define DDRC_DRAMTMG12_T_CKEHCMD_SHIFT 8 +#define DDRC_DRAMTMG12_T_CKEHCMD_MASK 0x00000F00U -/*tMRD_PDA: This is the Mode Register Set command cycle time in PDA mode. For configurations with MEMC_FREQ_RATIO=2, program th - s to (tMRD_PDA/2) and round it up to next integer value.*/ +/* +* tMRD_PDA: This is the Mode Register Set command cycle time in PDA mode. + * For configurations with MEMC_FREQ_RATIO=2, program this to (tMRD_PDA/2) + * and round it up to next integer value. +*/ #undef DDRC_DRAMTMG12_T_MRD_PDA_DEFVAL #undef DDRC_DRAMTMG12_T_MRD_PDA_SHIFT #undef DDRC_DRAMTMG12_T_MRD_PDA_MASK -#define DDRC_DRAMTMG12_T_MRD_PDA_DEFVAL 0x00020610 -#define DDRC_DRAMTMG12_T_MRD_PDA_SHIFT 0 -#define DDRC_DRAMTMG12_T_MRD_PDA_MASK 0x0000001FU +#define DDRC_DRAMTMG12_T_MRD_PDA_DEFVAL 0x00020610 +#define DDRC_DRAMTMG12_T_MRD_PDA_SHIFT 0 +#define DDRC_DRAMTMG12_T_MRD_PDA_MASK 0x0000001FU -/*- 1 - Disable uMCTL2 generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used instead to is - ue ZQ calibration request from APB module. - 0 - Internally generate ZQCS/MPC(ZQ calibration) commands based on ZQCTL1.t_zq_s - ort_interval_x1024. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.*/ +/* +* - 1 - Disable uMCTL2 generation of ZQCS/MPC(ZQ calibration) command. Reg + * ister DBGCMD.zq_calib_short can be used instead to issue ZQ calibration + * request from APB module. - 0 - Internally generate ZQCS/MPC(ZQ calibrati + * on) commands based on ZQCTL1.t_zq_short_interval_x1024. This is only pre + * sent for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. +*/ #undef DDRC_ZQCTL0_DIS_AUTO_ZQ_DEFVAL #undef DDRC_ZQCTL0_DIS_AUTO_ZQ_SHIFT #undef DDRC_ZQCTL0_DIS_AUTO_ZQ_MASK -#define DDRC_ZQCTL0_DIS_AUTO_ZQ_DEFVAL 0x02000040 -#define DDRC_ZQCTL0_DIS_AUTO_ZQ_SHIFT 31 -#define DDRC_ZQCTL0_DIS_AUTO_ZQ_MASK 0x80000000U +#define DDRC_ZQCTL0_DIS_AUTO_ZQ_DEFVAL 0x02000040 +#define DDRC_ZQCTL0_DIS_AUTO_ZQ_SHIFT 31 +#define DDRC_ZQCTL0_DIS_AUTO_ZQ_MASK 0x80000000U -/*- 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable when run in DDR3 - or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. - 0 - Enable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Power - own exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. This is only present for designs suppo - ting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.*/ +/* +* - 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refres + * h/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 + * or LPDDR3 or LPDDR4 mode. - 0 - Enable issuing of ZQCL/MPC(ZQ calibratio + * n) command at Self-Refresh/SR-Powerdown exit. Only applicable when run i + * n DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. This is only present + * for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. +*/ #undef DDRC_ZQCTL0_DIS_SRX_ZQCL_DEFVAL #undef DDRC_ZQCTL0_DIS_SRX_ZQCL_SHIFT #undef DDRC_ZQCTL0_DIS_SRX_ZQCL_MASK -#define DDRC_ZQCTL0_DIS_SRX_ZQCL_DEFVAL 0x02000040 -#define DDRC_ZQCTL0_DIS_SRX_ZQCL_SHIFT 30 -#define DDRC_ZQCTL0_DIS_SRX_ZQCL_MASK 0x40000000U +#define DDRC_ZQCTL0_DIS_SRX_ZQCL_DEFVAL 0x02000040 +#define DDRC_ZQCTL0_DIS_SRX_ZQCL_SHIFT 30 +#define DDRC_ZQCTL0_DIS_SRX_ZQCL_MASK 0x40000000U -/*- 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are sent to one r - nk at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to different ranks do not ov - rlap. - 0 - ZQ resistor is not shared. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.*/ +/* +* - 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQC + * L/ZQCS/MPC(ZQ calibration) commands are sent to one rank at a time with + * tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that co + * mmands to different ranks do not overlap. - 0 - ZQ resistor is not share + * d. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR + * 3/LPDDR4 devices. +*/ #undef DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_DEFVAL #undef DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_SHIFT #undef DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_MASK -#define DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_DEFVAL 0x02000040 -#define DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_SHIFT 29 -#define DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_MASK 0x20000000U +#define DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_DEFVAL 0x02000040 +#define DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_SHIFT 29 +#define DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_MASK 0x20000000U -/*- 1 - Disable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode. - 0 - Enable - ssuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode. This is only present for des - gns supporting DDR4 devices.*/ +/* +* - 1 - Disable issuing of ZQCL command at Maximum Power Saving Mode exit. + * Only applicable when run in DDR4 mode. - 0 - Enable issuing of ZQCL com + * mand at Maximum Power Saving Mode exit. Only applicable when run in DDR4 + * mode. This is only present for designs supporting DDR4 devices. +*/ #undef DDRC_ZQCTL0_DIS_MPSMX_ZQCL_DEFVAL #undef DDRC_ZQCTL0_DIS_MPSMX_ZQCL_SHIFT #undef DDRC_ZQCTL0_DIS_MPSMX_ZQCL_MASK -#define DDRC_ZQCTL0_DIS_MPSMX_ZQCL_DEFVAL 0x02000040 -#define DDRC_ZQCTL0_DIS_MPSMX_ZQCL_SHIFT 28 -#define DDRC_ZQCTL0_DIS_MPSMX_ZQCL_MASK 0x10000000U +#define DDRC_ZQCTL0_DIS_MPSMX_ZQCL_DEFVAL 0x02000040 +#define DDRC_ZQCTL0_DIS_MPSMX_ZQCL_SHIFT 28 +#define DDRC_ZQCTL0_DIS_MPSMX_ZQCL_MASK 0x10000000U -/*tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Number of cycles of NOP required after a ZQCL (ZQ calibrat - on long)/MPC(ZQ Start) command is issued to SDRAM. For configurations with MEMC_FREQ_RATIO=2: DDR3/DDR4: program this to tZQo - er/2 and round it up to the next integer value. LPDDR2/LPDDR3: program this to tZQCL/2 and round it up to the next integer va - ue. LPDDR4: program this to tZQCAL/2 and round it up to the next integer value. Unit: Clock cycles. This is only present for - esigns supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.*/ +/* +* tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Numbe + * r of cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ St + * art) command is issued to SDRAM. For configurations with MEMC_FREQ_RATIO + * =2: DDR3/DDR4: program this to tZQoper/2 and round it up to the next int + * eger value. LPDDR2/LPDDR3: program this to tZQCL/2 and round it up to th + * e next integer value. LPDDR4: program this to tZQCAL/2 and round it up t + * o the next integer value. Unit: Clock cycles. This is only present for d + * esigns supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. +*/ #undef DDRC_ZQCTL0_T_ZQ_LONG_NOP_DEFVAL #undef DDRC_ZQCTL0_T_ZQ_LONG_NOP_SHIFT #undef DDRC_ZQCTL0_T_ZQ_LONG_NOP_MASK -#define DDRC_ZQCTL0_T_ZQ_LONG_NOP_DEFVAL 0x02000040 -#define DDRC_ZQCTL0_T_ZQ_LONG_NOP_SHIFT 16 -#define DDRC_ZQCTL0_T_ZQ_LONG_NOP_MASK 0x07FF0000U +#define DDRC_ZQCTL0_T_ZQ_LONG_NOP_DEFVAL 0x02000040 +#define DDRC_ZQCTL0_T_ZQ_LONG_NOP_SHIFT 16 +#define DDRC_ZQCTL0_T_ZQ_LONG_NOP_MASK 0x07FF0000U -/*tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of cycles of NOP required after a ZQCS (ZQ calibration short)/MPC - ZQ Latch) command is issued to SDRAM. For configurations with MEMC_FREQ_RATIO=2, program this to tZQCS/2 and round it up to t - e next integer value. Unit: Clock cycles. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devic - s.*/ +/* +* tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of cycles of + * NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command + * is issued to SDRAM. For configurations with MEMC_FREQ_RATIO=2, program t + * his to tZQCS/2 and round it up to the next integer value. Unit: Clock cy + * cles. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LP + * DDR3/LPDDR4 devices. +*/ #undef DDRC_ZQCTL0_T_ZQ_SHORT_NOP_DEFVAL #undef DDRC_ZQCTL0_T_ZQ_SHORT_NOP_SHIFT #undef DDRC_ZQCTL0_T_ZQ_SHORT_NOP_MASK -#define DDRC_ZQCTL0_T_ZQ_SHORT_NOP_DEFVAL 0x02000040 -#define DDRC_ZQCTL0_T_ZQ_SHORT_NOP_SHIFT 0 -#define DDRC_ZQCTL0_T_ZQ_SHORT_NOP_MASK 0x000003FFU +#define DDRC_ZQCTL0_T_ZQ_SHORT_NOP_DEFVAL 0x02000040 +#define DDRC_ZQCTL0_T_ZQ_SHORT_NOP_SHIFT 0 +#define DDRC_ZQCTL0_T_ZQ_SHORT_NOP_MASK 0x000003FFU -/*tZQReset: Number of cycles of NOP required after a ZQReset (ZQ calibration Reset) command is issued to SDRAM. For configurati - ns with MEMC_FREQ_RATIO=2, program this to tZQReset/2 and round it up to the next integer value. Unit: Clock cycles. This is - nly present for designs supporting LPDDR2/LPDDR3/LPDDR4 devices.*/ +/* +* tZQReset: Number of cycles of NOP required after a ZQReset (ZQ calibrati + * on Reset) command is issued to SDRAM. For configurations with MEMC_FREQ_ + * RATIO=2, program this to tZQReset/2 and round it up to the next integer + * value. Unit: Clock cycles. This is only present for designs supporting L + * PDDR2/LPDDR3/LPDDR4 devices. +*/ #undef DDRC_ZQCTL1_T_ZQ_RESET_NOP_DEFVAL #undef DDRC_ZQCTL1_T_ZQ_RESET_NOP_SHIFT #undef DDRC_ZQCTL1_T_ZQ_RESET_NOP_MASK -#define DDRC_ZQCTL1_T_ZQ_RESET_NOP_DEFVAL 0x02000100 -#define DDRC_ZQCTL1_T_ZQ_RESET_NOP_SHIFT 20 -#define DDRC_ZQCTL1_T_ZQ_RESET_NOP_MASK 0x3FF00000U +#define DDRC_ZQCTL1_T_ZQ_RESET_NOP_DEFVAL 0x02000100 +#define DDRC_ZQCTL1_T_ZQ_RESET_NOP_SHIFT 20 +#define DDRC_ZQCTL1_T_ZQ_RESET_NOP_MASK 0x3FF00000U -/*Average interval to wait between automatically issuing ZQCS (ZQ calibration short)/MPC(ZQ calibration) commands to DDR3/DDR4/ - PDDR2/LPDDR3/LPDDR4 devices. Meaningless, if ZQCTL0.dis_auto_zq=1. Unit: 1024 clock cycles. This is only present for designs - upporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.*/ +/* +* Average interval to wait between automatically issuing ZQCS (ZQ calibrat + * ion short)/MPC(ZQ calibration) commands to DDR3/DDR4/LPDDR2/LPDDR3/LPDDR + * 4 devices. Meaningless, if ZQCTL0.dis_auto_zq=1. Unit: 1024 clock cycles + * . This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3 + * /LPDDR4 devices. +*/ #undef DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_DEFVAL #undef DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_SHIFT #undef DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_MASK -#define DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_DEFVAL 0x02000100 -#define DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_SHIFT 0 -#define DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_MASK 0x000FFFFFU +#define DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_DEFVAL 0x02000100 +#define DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_SHIFT 0 +#define DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_MASK 0x000FFFFFU -/*Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signa - s at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligne - , this timing parameter should be rounded up to the next integer value. Note that if using RDIMM, it is necessary to incremen - this parameter by RDIMM's extra cycle of latency in terms of DFI clock.*/ +/* +* Specifies the number of DFI clock cycles after an assertion or de-assert + * ion of the DFI control signals that the control signals at the PHY-DRAM + * interface reflect the assertion or de-assertion. If the DFI clock and th + * e memory clock are not phase-aligned, this timing parameter should be ro + * unded up to the next integer value. Note that if using RDIMM, it is nece + * ssary to increment this parameter by RDIMM's extra cycle of latency in t + * erms of DFI clock. +*/ #undef DDRC_DFITMG0_DFI_T_CTRL_DELAY_DEFVAL #undef DDRC_DFITMG0_DFI_T_CTRL_DELAY_SHIFT #undef DDRC_DFITMG0_DFI_T_CTRL_DELAY_MASK -#define DDRC_DFITMG0_DFI_T_CTRL_DELAY_DEFVAL 0x07020002 -#define DDRC_DFITMG0_DFI_T_CTRL_DELAY_SHIFT 24 -#define DDRC_DFITMG0_DFI_T_CTRL_DELAY_MASK 0x1F000000U +#define DDRC_DFITMG0_DFI_T_CTRL_DELAY_DEFVAL 0x07020002 +#define DDRC_DFITMG0_DFI_T_CTRL_DELAY_SHIFT 24 +#define DDRC_DFITMG0_DFI_T_CTRL_DELAY_MASK 0x1F000000U -/*Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR or SDR values Selects whether value in DFITM - 0.dfi_t_rddata_en is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles R - fer to PHY specification for correct value.*/ +/* +* Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated u + * sing HDR or SDR values Selects whether value in DFITMG0.dfi_t_rddata_en + * is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles + * - 1 in terms of SDR clock cycles Refer to PHY specification for correct + * value. +*/ #undef DDRC_DFITMG0_DFI_RDDATA_USE_SDR_DEFVAL #undef DDRC_DFITMG0_DFI_RDDATA_USE_SDR_SHIFT #undef DDRC_DFITMG0_DFI_RDDATA_USE_SDR_MASK -#define DDRC_DFITMG0_DFI_RDDATA_USE_SDR_DEFVAL 0x07020002 -#define DDRC_DFITMG0_DFI_RDDATA_USE_SDR_SHIFT 23 -#define DDRC_DFITMG0_DFI_RDDATA_USE_SDR_MASK 0x00800000U +#define DDRC_DFITMG0_DFI_RDDATA_USE_SDR_DEFVAL 0x07020002 +#define DDRC_DFITMG0_DFI_RDDATA_USE_SDR_SHIFT 23 +#define DDRC_DFITMG0_DFI_RDDATA_USE_SDR_MASK 0x00800000U -/*Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. Refer to PHY spe - ification for correct value. This corresponds to the DFI parameter trddata_en. Note that, depending on the PHY, if using RDIM - , it may be necessary to use the value (CL + 1) in the calculation of trddata_en. This is to compensate for the extra cycle o - latency through the RDIMM. Unit: Clocks*/ +/* +* Time from the assertion of a read command on the DFI interface to the as + * sertion of the dfi_rddata_en signal. Refer to PHY specification for corr + * ect value. This corresponds to the DFI parameter trddata_en. Note that, + * depending on the PHY, if using RDIMM, it may be necessary to use the val + * ue (CL + 1) in the calculation of trddata_en. This is to compensate for + * the extra cycle of latency through the RDIMM. Unit: Clocks +*/ #undef DDRC_DFITMG0_DFI_T_RDDATA_EN_DEFVAL #undef DDRC_DFITMG0_DFI_T_RDDATA_EN_SHIFT #undef DDRC_DFITMG0_DFI_T_RDDATA_EN_MASK -#define DDRC_DFITMG0_DFI_T_RDDATA_EN_DEFVAL 0x07020002 -#define DDRC_DFITMG0_DFI_T_RDDATA_EN_SHIFT 16 -#define DDRC_DFITMG0_DFI_T_RDDATA_EN_MASK 0x003F0000U +#define DDRC_DFITMG0_DFI_T_RDDATA_EN_DEFVAL 0x07020002 +#define DDRC_DFITMG0_DFI_T_RDDATA_EN_SHIFT 16 +#define DDRC_DFITMG0_DFI_T_RDDATA_EN_MASK 0x003F0000U -/*Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using HDR or SDR values Selects whether value in DFITMG - .dfi_tphy_wrlat is in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.dfi_tphy_wrdata is in terms of SDR or - HDR clock cycles - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles Refer to PHY specification for correct val - e.*/ +/* +* Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated us + * ing HDR or SDR values Selects whether value in DFITMG0.dfi_tphy_wrlat is + * in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.df + * i_tphy_wrdata is in terms of SDR or HDR clock cycles - 0 in terms of HDR + * clock cycles - 1 in terms of SDR clock cycles Refer to PHY specificatio + * n for correct value. +*/ #undef DDRC_DFITMG0_DFI_WRDATA_USE_SDR_DEFVAL #undef DDRC_DFITMG0_DFI_WRDATA_USE_SDR_SHIFT #undef DDRC_DFITMG0_DFI_WRDATA_USE_SDR_MASK -#define DDRC_DFITMG0_DFI_WRDATA_USE_SDR_DEFVAL 0x07020002 -#define DDRC_DFITMG0_DFI_WRDATA_USE_SDR_SHIFT 15 -#define DDRC_DFITMG0_DFI_WRDATA_USE_SDR_MASK 0x00008000U +#define DDRC_DFITMG0_DFI_WRDATA_USE_SDR_DEFVAL 0x07020002 +#define DDRC_DFITMG0_DFI_WRDATA_USE_SDR_SHIFT 15 +#define DDRC_DFITMG0_DFI_WRDATA_USE_SDR_MASK 0x00008000U -/*Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on th - dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. N - te, max supported value is 8. Unit: Clocks*/ +/* +* Specifies the number of clock cycles between when dfi_wrdata_en is asser + * ted to when the associated write data is driven on the dfi_wrdata signal + * . This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY + * specification for correct value. Note, max supported value is 8. Unit: + * Clocks +*/ #undef DDRC_DFITMG0_DFI_TPHY_WRDATA_DEFVAL #undef DDRC_DFITMG0_DFI_TPHY_WRDATA_SHIFT #undef DDRC_DFITMG0_DFI_TPHY_WRDATA_MASK -#define DDRC_DFITMG0_DFI_TPHY_WRDATA_DEFVAL 0x07020002 -#define DDRC_DFITMG0_DFI_TPHY_WRDATA_SHIFT 8 -#define DDRC_DFITMG0_DFI_TPHY_WRDATA_MASK 0x00003F00U +#define DDRC_DFITMG0_DFI_TPHY_WRDATA_DEFVAL 0x07020002 +#define DDRC_DFITMG0_DFI_TPHY_WRDATA_SHIFT 8 +#define DDRC_DFITMG0_DFI_TPHY_WRDATA_MASK 0x00003F00U -/*Write latency Number of clocks from the write command to write data enable (dfi_wrdata_en). This corresponds to the DFI timin - parameter tphy_wrlat. Refer to PHY specification for correct value.Note that, depending on the PHY, if using RDIMM, it may b - necessary to use the value (CL + 1) in the calculation of tphy_wrlat. This is to compensate for the extra cycle of latency t - rough the RDIMM.*/ +/* +* Write latency Number of clocks from the write command to write data enab + * le (dfi_wrdata_en). This corresponds to the DFI timing parameter tphy_wr + * lat. Refer to PHY specification for correct value.Note that, depending o + * n the PHY, if using RDIMM, it may be necessary to use the value (CL + 1) + * in the calculation of tphy_wrlat. This is to compensate for the extra c + * ycle of latency through the RDIMM. +*/ #undef DDRC_DFITMG0_DFI_TPHY_WRLAT_DEFVAL #undef DDRC_DFITMG0_DFI_TPHY_WRLAT_SHIFT #undef DDRC_DFITMG0_DFI_TPHY_WRLAT_MASK -#define DDRC_DFITMG0_DFI_TPHY_WRLAT_DEFVAL 0x07020002 -#define DDRC_DFITMG0_DFI_TPHY_WRLAT_SHIFT 0 -#define DDRC_DFITMG0_DFI_TPHY_WRLAT_MASK 0x0000003FU +#define DDRC_DFITMG0_DFI_TPHY_WRLAT_DEFVAL 0x07020002 +#define DDRC_DFITMG0_DFI_TPHY_WRLAT_SHIFT 0 +#define DDRC_DFITMG0_DFI_TPHY_WRLAT_MASK 0x0000003FU -/*Specifies the number of DFI PHY clocks between when the dfi_cs signal is asserted and when the associated command is driven. - his field is used for CAL mode, should be set to '0' or the value which matches the CAL mode register setting in the DRAM. If - the PHY can add the latency for CAL mode, this should be set to '0'. Valid Range: 0, 3, 4, 5, 6, and 8*/ +/* +* Specifies the number of DFI PHY clocks between when the dfi_cs signal is + * asserted and when the associated command is driven. This field is used + * for CAL mode, should be set to '0' or the value which matches the CAL mo + * de register setting in the DRAM. If the PHY can add the latency for CAL + * mode, this should be set to '0'. Valid Range: 0, 3, 4, 5, 6, and 8 +*/ #undef DDRC_DFITMG1_DFI_T_CMD_LAT_DEFVAL #undef DDRC_DFITMG1_DFI_T_CMD_LAT_SHIFT #undef DDRC_DFITMG1_DFI_T_CMD_LAT_MASK -#define DDRC_DFITMG1_DFI_T_CMD_LAT_DEFVAL 0x00000404 -#define DDRC_DFITMG1_DFI_T_CMD_LAT_SHIFT 28 -#define DDRC_DFITMG1_DFI_T_CMD_LAT_MASK 0xF0000000U +#define DDRC_DFITMG1_DFI_T_CMD_LAT_DEFVAL 0x00000404 +#define DDRC_DFITMG1_DFI_T_CMD_LAT_SHIFT 28 +#define DDRC_DFITMG1_DFI_T_CMD_LAT_MASK 0xF0000000U -/*Specifies the number of DFI PHY clocks between when the dfi_cs signal is asserted and when the associated dfi_parity_in signa - is driven.*/ +/* +* Specifies the number of DFI PHY clocks between when the dfi_cs signal is + * asserted and when the associated dfi_parity_in signal is driven. +*/ #undef DDRC_DFITMG1_DFI_T_PARIN_LAT_DEFVAL #undef DDRC_DFITMG1_DFI_T_PARIN_LAT_SHIFT #undef DDRC_DFITMG1_DFI_T_PARIN_LAT_MASK -#define DDRC_DFITMG1_DFI_T_PARIN_LAT_DEFVAL 0x00000404 -#define DDRC_DFITMG1_DFI_T_PARIN_LAT_SHIFT 24 -#define DDRC_DFITMG1_DFI_T_PARIN_LAT_MASK 0x03000000U +#define DDRC_DFITMG1_DFI_T_PARIN_LAT_DEFVAL 0x00000404 +#define DDRC_DFITMG1_DFI_T_PARIN_LAT_SHIFT 24 +#define DDRC_DFITMG1_DFI_T_PARIN_LAT_MASK 0x03000000U -/*Specifies the number of DFI clocks between when the dfi_wrdata_en signal is asserted and when the corresponding write data tr - nsfer is completed on the DRAM bus. This corresponds to the DFI timing parameter twrdata_delay. Refer to PHY specification fo - correct value. For DFI 3.0 PHY, set to twrdata_delay, a new timing parameter introduced in DFI 3.0. For DFI 2.1 PHY, set to - phy_wrdata + (delay of DFI write data to the DRAM). Value to be programmed is in terms of DFI clocks, not PHY clocks. In FREQ - RATIO=2, divide PHY's value by 2 and round up to next integer. If using DFITMG0.dfi_wrdata_use_sdr=1, add 1 to the value. Uni - : Clocks*/ +/* +* Specifies the number of DFI clocks between when the dfi_wrdata_en signal + * is asserted and when the corresponding write data transfer is completed + * on the DRAM bus. This corresponds to the DFI timing parameter twrdata_d + * elay. Refer to PHY specification for correct value. For DFI 3.0 PHY, set + * to twrdata_delay, a new timing parameter introduced in DFI 3.0. For DFI + * 2.1 PHY, set to tphy_wrdata + (delay of DFI write data to the DRAM). Va + * lue to be programmed is in terms of DFI clocks, not PHY clocks. In FREQ_ + * RATIO=2, divide PHY's value by 2 and round up to next integer. If using + * DFITMG0.dfi_wrdata_use_sdr=1, add 1 to the value. Unit: Clocks +*/ #undef DDRC_DFITMG1_DFI_T_WRDATA_DELAY_DEFVAL #undef DDRC_DFITMG1_DFI_T_WRDATA_DELAY_SHIFT #undef DDRC_DFITMG1_DFI_T_WRDATA_DELAY_MASK -#define DDRC_DFITMG1_DFI_T_WRDATA_DELAY_DEFVAL 0x00000404 -#define DDRC_DFITMG1_DFI_T_WRDATA_DELAY_SHIFT 16 -#define DDRC_DFITMG1_DFI_T_WRDATA_DELAY_MASK 0x001F0000U +#define DDRC_DFITMG1_DFI_T_WRDATA_DELAY_DEFVAL 0x00000404 +#define DDRC_DFITMG1_DFI_T_WRDATA_DELAY_SHIFT 16 +#define DDRC_DFITMG1_DFI_T_WRDATA_DELAY_MASK 0x001F0000U -/*Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to - he DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase - ligned, this timing parameter should be rounded up to the next integer value.*/ +/* +* Specifies the number of DFI clock cycles from the assertion of the dfi_d + * ram_clk_disable signal on the DFI until the clock to the DRAM memory dev + * ices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock + * and the memory clock are not phase aligned, this timing parameter should + * be rounded up to the next integer value. +*/ #undef DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_DEFVAL #undef DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_SHIFT #undef DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_MASK -#define DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_DEFVAL 0x00000404 -#define DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_SHIFT 8 -#define DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_MASK 0x00000F00U +#define DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_DEFVAL 0x00000404 +#define DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_SHIFT 8 +#define DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_MASK 0x00000F00U -/*Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first - alid rising edge of the clock to the DRAM memory devices, at the PHY-DRAM boundary. If the DFI clock and the memory clock are - not phase aligned, this timing parameter should be rounded up to the next integer value.*/ +/* +* Specifies the number of DFI clock cycles from the de-assertion of the df + * i_dram_clk_disable signal on the DFI until the first valid rising edge o + * f the clock to the DRAM memory devices, at the PHY-DRAM boundary. If the + * DFI clock and the memory clock are not phase aligned, this timing param + * eter should be rounded up to the next integer value. +*/ #undef DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_DEFVAL #undef DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_SHIFT #undef DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_MASK -#define DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_DEFVAL 0x00000404 -#define DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_SHIFT 0 -#define DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_MASK 0x0000000FU +#define DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_DEFVAL 0x00000404 +#define DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_SHIFT 0 +#define DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_MASK 0x0000000FU -/*Setting for DFI's tlp_resp time. Same value is used for both Power Down, Self Refresh, Deep Power Down and Maximum Power Savi - g modes. DFI 2.1 specification onwards, recommends using a fixed value of 7 always.*/ +/* +* Setting for DFI's tlp_resp time. Same value is used for both Power Down, + * Self Refresh, Deep Power Down and Maximum Power Saving modes. DFI 2.1 s + * pecification onwards, recommends using a fixed value of 7 always. +*/ #undef DDRC_DFILPCFG0_DFI_TLP_RESP_DEFVAL #undef DDRC_DFILPCFG0_DFI_TLP_RESP_SHIFT #undef DDRC_DFILPCFG0_DFI_TLP_RESP_MASK -#define DDRC_DFILPCFG0_DFI_TLP_RESP_DEFVAL 0x07000000 -#define DDRC_DFILPCFG0_DFI_TLP_RESP_SHIFT 24 -#define DDRC_DFILPCFG0_DFI_TLP_RESP_MASK 0x0F000000U +#define DDRC_DFILPCFG0_DFI_TLP_RESP_DEFVAL 0x07000000 +#define DDRC_DFILPCFG0_DFI_TLP_RESP_SHIFT 24 +#define DDRC_DFILPCFG0_DFI_TLP_RESP_MASK 0x0F000000U -/*Value to drive on dfi_lp_wakeup signal when Deep Power Down mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 - cycles - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles - 0x7 - - 2048 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0xD - - 31072 cycles - 0xE - 262144 cycles - 0xF - Unlimited This is only present for designs supporting mDDR or LPDDR2/LPDDR3 device - .*/ +/* +* Value to drive on dfi_lp_wakeup signal when Deep Power Down mode is ente + * red. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32 + * cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 5 + * 12 cycles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycles - + * 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 6553 + * 6 cycles - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited T + * his is only present for designs supporting mDDR or LPDDR2/LPDDR3 devices + * . +*/ #undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_DEFVAL #undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_SHIFT #undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_MASK -#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_DEFVAL 0x07000000 -#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_SHIFT 20 -#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_MASK 0x00F00000U +#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_DEFVAL 0x07000000 +#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_SHIFT 20 +#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_MASK 0x00F00000U -/*Enables DFI Low Power interface handshaking during Deep Power Down Entry/Exit. - 0 - Disabled - 1 - Enabled This is only pres - nt for designs supporting mDDR or LPDDR2/LPDDR3 devices.*/ +/* +* Enables DFI Low Power interface handshaking during Deep Power Down Entry + * /Exit. - 0 - Disabled - 1 - Enabled This is only present for designs sup + * porting mDDR or LPDDR2/LPDDR3 devices. +*/ #undef DDRC_DFILPCFG0_DFI_LP_EN_DPD_DEFVAL #undef DDRC_DFILPCFG0_DFI_LP_EN_DPD_SHIFT #undef DDRC_DFILPCFG0_DFI_LP_EN_DPD_MASK -#define DDRC_DFILPCFG0_DFI_LP_EN_DPD_DEFVAL 0x07000000 -#define DDRC_DFILPCFG0_DFI_LP_EN_DPD_SHIFT 16 -#define DDRC_DFILPCFG0_DFI_LP_EN_DPD_MASK 0x00010000U +#define DDRC_DFILPCFG0_DFI_LP_EN_DPD_DEFVAL 0x07000000 +#define DDRC_DFILPCFG0_DFI_LP_EN_DPD_SHIFT 16 +#define DDRC_DFILPCFG0_DFI_LP_EN_DPD_MASK 0x00010000U -/*Value to drive on dfi_lp_wakeup signal when Self Refresh mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cy - les - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles - 0x7 - - 048 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0xD - 131 - 72 cycles - 0xE - 262144 cycles - 0xF - Unlimited*/ +/* +* Value to drive on dfi_lp_wakeup signal when Self Refresh mode is entered + * . Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32 cyc + * les - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 + * cycles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycles - 0x9 + * - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 c + * ycles - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited +*/ #undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_DEFVAL #undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_SHIFT #undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_MASK -#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_DEFVAL 0x07000000 -#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_SHIFT 12 -#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_MASK 0x0000F000U +#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_DEFVAL 0x07000000 +#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_SHIFT 12 +#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_MASK 0x0000F000U -/*Enables DFI Low Power interface handshaking during Self Refresh Entry/Exit. - 0 - Disabled - 1 - Enabled*/ +/* +* Enables DFI Low Power interface handshaking during Self Refresh Entry/Ex + * it. - 0 - Disabled - 1 - Enabled +*/ #undef DDRC_DFILPCFG0_DFI_LP_EN_SR_DEFVAL #undef DDRC_DFILPCFG0_DFI_LP_EN_SR_SHIFT #undef DDRC_DFILPCFG0_DFI_LP_EN_SR_MASK -#define DDRC_DFILPCFG0_DFI_LP_EN_SR_DEFVAL 0x07000000 -#define DDRC_DFILPCFG0_DFI_LP_EN_SR_SHIFT 8 -#define DDRC_DFILPCFG0_DFI_LP_EN_SR_MASK 0x00000100U +#define DDRC_DFILPCFG0_DFI_LP_EN_SR_DEFVAL 0x07000000 +#define DDRC_DFILPCFG0_DFI_LP_EN_SR_SHIFT 8 +#define DDRC_DFILPCFG0_DFI_LP_EN_SR_MASK 0x00000100U -/*Value to drive on dfi_lp_wakeup signal when Power Down mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycl - s - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles - 0x7 - 20 - 8 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0xD - 13107 - cycles - 0xE - 262144 cycles - 0xF - Unlimited*/ +/* +* Value to drive on dfi_lp_wakeup signal when Power Down mode is entered. + * Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32 cycle + * s - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cy + * cles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycles - 0x9 - + * 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cyc + * les - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited +*/ #undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_DEFVAL #undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_SHIFT #undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_MASK -#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_DEFVAL 0x07000000 -#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_SHIFT 4 -#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_MASK 0x000000F0U +#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_DEFVAL 0x07000000 +#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_SHIFT 4 +#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_MASK 0x000000F0U -/*Enables DFI Low Power interface handshaking during Power Down Entry/Exit. - 0 - Disabled - 1 - Enabled*/ +/* +* Enables DFI Low Power interface handshaking during Power Down Entry/Exit + * . - 0 - Disabled - 1 - Enabled +*/ #undef DDRC_DFILPCFG0_DFI_LP_EN_PD_DEFVAL #undef DDRC_DFILPCFG0_DFI_LP_EN_PD_SHIFT #undef DDRC_DFILPCFG0_DFI_LP_EN_PD_MASK -#define DDRC_DFILPCFG0_DFI_LP_EN_PD_DEFVAL 0x07000000 -#define DDRC_DFILPCFG0_DFI_LP_EN_PD_SHIFT 0 -#define DDRC_DFILPCFG0_DFI_LP_EN_PD_MASK 0x00000001U +#define DDRC_DFILPCFG0_DFI_LP_EN_PD_DEFVAL 0x07000000 +#define DDRC_DFILPCFG0_DFI_LP_EN_PD_SHIFT 0 +#define DDRC_DFILPCFG0_DFI_LP_EN_PD_MASK 0x00000001U -/*Value to drive on dfi_lp_wakeup signal when Maximum Power Saving Mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - - 16 cycles - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0 - D - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited This is only present for designs supporting DDR4 devices.*/ +/* +* Value to drive on dfi_lp_wakeup signal when Maximum Power Saving Mode is + * entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 + * - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x + * 5 - 512 cycles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycl + * es - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - + * 65536 cycles - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimi + * ted This is only present for designs supporting DDR4 devices. +*/ #undef DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_DEFVAL #undef DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_SHIFT #undef DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_MASK -#define DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_DEFVAL 0x00000000 -#define DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_SHIFT 4 -#define DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_MASK 0x000000F0U +#define DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_DEFVAL 0x00000000 +#define DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_SHIFT 4 +#define DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_MASK 0x000000F0U -/*Enables DFI Low Power interface handshaking during Maximum Power Saving Mode Entry/Exit. - 0 - Disabled - 1 - Enabled This is - only present for designs supporting DDR4 devices.*/ +/* +* Enables DFI Low Power interface handshaking during Maximum Power Saving + * Mode Entry/Exit. - 0 - Disabled - 1 - Enabled This is only present for d + * esigns supporting DDR4 devices. +*/ #undef DDRC_DFILPCFG1_DFI_LP_EN_MPSM_DEFVAL #undef DDRC_DFILPCFG1_DFI_LP_EN_MPSM_SHIFT #undef DDRC_DFILPCFG1_DFI_LP_EN_MPSM_MASK -#define DDRC_DFILPCFG1_DFI_LP_EN_MPSM_DEFVAL 0x00000000 -#define DDRC_DFILPCFG1_DFI_LP_EN_MPSM_SHIFT 0 -#define DDRC_DFILPCFG1_DFI_LP_EN_MPSM_MASK 0x00000001U +#define DDRC_DFILPCFG1_DFI_LP_EN_MPSM_DEFVAL 0x00000000 +#define DDRC_DFILPCFG1_DFI_LP_EN_MPSM_SHIFT 0 +#define DDRC_DFILPCFG1_DFI_LP_EN_MPSM_MASK 0x00000001U -/*This is the minimum amount of time between uMCTL2 initiated DFI update requests (which is executed whenever the uMCTL2 is idl - ). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the fir - t read request when the uMCTL2 is idle. Unit: 1024 clocks*/ +/* +* When '1', disable the automatic dfi_ctrlupd_req generation by the uMCTL2 + * . The core must issue the dfi_ctrlupd_req signal using register reg_ddrc + * _ctrlupd. When '0', uMCTL2 issues dfi_ctrlupd_req periodically. +*/ +#undef DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_DEFVAL +#undef DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SHIFT +#undef DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_MASK +#define DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_DEFVAL 0x00400003 +#define DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SHIFT 31 +#define DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_MASK 0x80000000U + +/* +* When '1', disable the automatic dfi_ctrlupd_req generation by the uMCTL2 + * following a self-refresh exit. The core must issue the dfi_ctrlupd_req + * signal using register reg_ddrc_ctrlupd. When '0', uMCTL2 issues a dfi_ct + * rlupd_req after exiting self-refresh. +*/ +#undef DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_DEFVAL +#undef DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_SHIFT +#undef DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_MASK +#define DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_DEFVAL 0x00400003 +#define DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_SHIFT 30 +#define DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_MASK 0x40000000U + +/* +* Specifies the maximum number of clock cycles that the dfi_ctrlupd_req si + * gnal can assert. Lowest value to assign to this variable is 0x40. Unit: + * Clocks +*/ +#undef DDRC_DFIUPD0_DFI_T_CTRLUP_MAX_DEFVAL +#undef DDRC_DFIUPD0_DFI_T_CTRLUP_MAX_SHIFT +#undef DDRC_DFIUPD0_DFI_T_CTRLUP_MAX_MASK +#define DDRC_DFIUPD0_DFI_T_CTRLUP_MAX_DEFVAL 0x00400003 +#define DDRC_DFIUPD0_DFI_T_CTRLUP_MAX_SHIFT 16 +#define DDRC_DFIUPD0_DFI_T_CTRLUP_MAX_MASK 0x03FF0000U + +/* +* Specifies the minimum number of clock cycles that the dfi_ctrlupd_req si + * gnal must be asserted. The uMCTL2 expects the PHY to respond within this + * time. If the PHY does not respond, the uMCTL2 will de-assert dfi_ctrlup + * d_req after dfi_t_ctrlup_min + 2 cycles. Lowest value to assign to this + * variable is 0x3. Unit: Clocks +*/ +#undef DDRC_DFIUPD0_DFI_T_CTRLUP_MIN_DEFVAL +#undef DDRC_DFIUPD0_DFI_T_CTRLUP_MIN_SHIFT +#undef DDRC_DFIUPD0_DFI_T_CTRLUP_MIN_MASK +#define DDRC_DFIUPD0_DFI_T_CTRLUP_MIN_DEFVAL 0x00400003 +#define DDRC_DFIUPD0_DFI_T_CTRLUP_MIN_SHIFT 0 +#define DDRC_DFIUPD0_DFI_T_CTRLUP_MIN_MASK 0x000003FFU + +/* +* This is the minimum amount of time between uMCTL2 initiated DFI update r + * equests (which is executed whenever the uMCTL2 is idle). Set this number + * higher to reduce the frequency of update requests, which can have a sma + * ll impact on the latency of the first read request when the uMCTL2 is id + * le. Unit: 1024 clocks +*/ #undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_DEFVAL #undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_SHIFT #undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_MASK -#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_DEFVAL 0x00000000 -#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_SHIFT 16 -#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_MASK 0x00FF0000U +#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_DEFVAL 0x00000000 +#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_SHIFT 16 +#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_MASK 0x00FF0000U -/*This is the maximum amount of time between uMCTL2 initiated DFI update requests. This timer resets with each update request; - hen the timer expires dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd_ackx is received. PHY can use this - idle time to recalibrate the delay lines to the DLLs. The DFI controller update is also used to reset PHY FIFO pointers in ca - e of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. - Note: Value programmed for DFIUPD1.dfi_t_ctrlupd_interval_max_x1024 must be greater than DFIUPD1.dfi_t_ctrlupd_interval_min_x - 024. Unit: 1024 clocks*/ +/* +* This is the maximum amount of time between uMCTL2 initiated DFI update r + * equests. This timer resets with each update request; when the timer expi + * res dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd + * _ackx is received. PHY can use this idle time to recalibrate the delay l + * ines to the DLLs. The DFI controller update is also used to reset PHY FI + * FO pointers in case of data capture errors. Updates are required to main + * tain calibration over PVT, but frequent updates may impact performance. + * Note: Value programmed for DFIUPD1.dfi_t_ctrlupd_interval_max_x1024 must + * be greater than DFIUPD1.dfi_t_ctrlupd_interval_min_x1024. Unit: 1024 cl + * ocks +*/ #undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_DEFVAL #undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_SHIFT #undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_MASK -#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_DEFVAL 0x00000000 -#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_SHIFT 0 -#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_MASK 0x000000FFU +#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_DEFVAL 0x00000000 +#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_SHIFT 0 +#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_MASK 0x000000FFU -/*Defines polarity of dfi_wrdata_cs and dfi_rddata_cs signals. - 0: Signals are active low - 1: Signals are active high*/ +/* +* Defines polarity of dfi_wrdata_cs and dfi_rddata_cs signals. - 0: Signal + * s are active low - 1: Signals are active high +*/ #undef DDRC_DFIMISC_DFI_DATA_CS_POLARITY_DEFVAL #undef DDRC_DFIMISC_DFI_DATA_CS_POLARITY_SHIFT #undef DDRC_DFIMISC_DFI_DATA_CS_POLARITY_MASK -#define DDRC_DFIMISC_DFI_DATA_CS_POLARITY_DEFVAL 0x00000001 -#define DDRC_DFIMISC_DFI_DATA_CS_POLARITY_SHIFT 2 -#define DDRC_DFIMISC_DFI_DATA_CS_POLARITY_MASK 0x00000004U +#define DDRC_DFIMISC_DFI_DATA_CS_POLARITY_DEFVAL 0x00000001 +#define DDRC_DFIMISC_DFI_DATA_CS_POLARITY_SHIFT 2 +#define DDRC_DFIMISC_DFI_DATA_CS_POLARITY_MASK 0x00000004U -/*DBI implemented in DDRC or PHY. - 0 - DDRC implements DBI functionality. - 1 - PHY implements DBI functionality. Present only - in designs configured to support DDR4 and LPDDR4.*/ +/* +* DBI implemented in DDRC or PHY. - 0 - DDRC implements DBI functionality. + * - 1 - PHY implements DBI functionality. Present only in designs configu + * red to support DDR4 and LPDDR4. +*/ #undef DDRC_DFIMISC_PHY_DBI_MODE_DEFVAL #undef DDRC_DFIMISC_PHY_DBI_MODE_SHIFT #undef DDRC_DFIMISC_PHY_DBI_MODE_MASK -#define DDRC_DFIMISC_PHY_DBI_MODE_DEFVAL 0x00000001 -#define DDRC_DFIMISC_PHY_DBI_MODE_SHIFT 1 -#define DDRC_DFIMISC_PHY_DBI_MODE_MASK 0x00000002U +#define DDRC_DFIMISC_PHY_DBI_MODE_DEFVAL 0x00000001 +#define DDRC_DFIMISC_PHY_DBI_MODE_SHIFT 1 +#define DDRC_DFIMISC_PHY_DBI_MODE_MASK 0x00000002U -/*PHY initialization complete enable signal. When asserted the dfi_init_complete signal can be used to trigger SDRAM initialisa - ion*/ +/* +* PHY initialization complete enable signal. When asserted the dfi_init_co + * mplete signal can be used to trigger SDRAM initialisation +*/ #undef DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_DEFVAL #undef DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_SHIFT #undef DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_MASK -#define DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_DEFVAL 0x00000001 -#define DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_SHIFT 0 -#define DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_MASK 0x00000001U +#define DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_DEFVAL 0x00000001 +#define DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_SHIFT 0 +#define DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_MASK 0x00000001U -/*>Number of clocks between when a read command is sent on the DFI control interface and when the associated dfi_rddata_cs sign - l is asserted. This corresponds to the DFI timing parameter tphy_rdcslat. Refer to PHY specification for correct value.*/ +/* +* >Number of clocks between when a read command is sent on the DFI control + * interface and when the associated dfi_rddata_cs signal is asserted. Thi + * s corresponds to the DFI timing parameter tphy_rdcslat. Refer to PHY spe + * cification for correct value. +*/ #undef DDRC_DFITMG2_DFI_TPHY_RDCSLAT_DEFVAL #undef DDRC_DFITMG2_DFI_TPHY_RDCSLAT_SHIFT #undef DDRC_DFITMG2_DFI_TPHY_RDCSLAT_MASK -#define DDRC_DFITMG2_DFI_TPHY_RDCSLAT_DEFVAL 0x00000202 -#define DDRC_DFITMG2_DFI_TPHY_RDCSLAT_SHIFT 8 -#define DDRC_DFITMG2_DFI_TPHY_RDCSLAT_MASK 0x00003F00U +#define DDRC_DFITMG2_DFI_TPHY_RDCSLAT_DEFVAL 0x00000202 +#define DDRC_DFITMG2_DFI_TPHY_RDCSLAT_SHIFT 8 +#define DDRC_DFITMG2_DFI_TPHY_RDCSLAT_MASK 0x00003F00U -/*Number of clocks between when a write command is sent on the DFI control interface and when the associated dfi_wrdata_cs sign - l is asserted. This corresponds to the DFI timing parameter tphy_wrcslat. Refer to PHY specification for correct value.*/ +/* +* Number of clocks between when a write command is sent on the DFI control + * interface and when the associated dfi_wrdata_cs signal is asserted. Thi + * s corresponds to the DFI timing parameter tphy_wrcslat. Refer to PHY spe + * cification for correct value. +*/ #undef DDRC_DFITMG2_DFI_TPHY_WRCSLAT_DEFVAL #undef DDRC_DFITMG2_DFI_TPHY_WRCSLAT_SHIFT #undef DDRC_DFITMG2_DFI_TPHY_WRCSLAT_MASK -#define DDRC_DFITMG2_DFI_TPHY_WRCSLAT_DEFVAL 0x00000202 -#define DDRC_DFITMG2_DFI_TPHY_WRCSLAT_SHIFT 0 -#define DDRC_DFITMG2_DFI_TPHY_WRCSLAT_MASK 0x0000003FU +#define DDRC_DFITMG2_DFI_TPHY_WRCSLAT_DEFVAL 0x00000202 +#define DDRC_DFITMG2_DFI_TPHY_WRCSLAT_SHIFT 0 +#define DDRC_DFITMG2_DFI_TPHY_WRCSLAT_MASK 0x0000003FU -/*Read DBI enable signal in DDRC. - 0 - Read DBI is disabled. - 1 - Read DBI is enabled. This signal must be set the same value - as DRAM's mode register. - DDR4: MR5 bit A12. When x4 devices are used, this signal must be set to 0. - LPDDR4: MR3[6]*/ +/* +* Read DBI enable signal in DDRC. - 0 - Read DBI is disabled. - 1 - Read D + * BI is enabled. This signal must be set the same value as DRAM's mode reg + * ister. - DDR4: MR5 bit A12. When x4 devices are used, this signal must b + * e set to 0. - LPDDR4: MR3[6] +*/ #undef DDRC_DBICTL_RD_DBI_EN_DEFVAL #undef DDRC_DBICTL_RD_DBI_EN_SHIFT #undef DDRC_DBICTL_RD_DBI_EN_MASK -#define DDRC_DBICTL_RD_DBI_EN_DEFVAL 0x00000001 -#define DDRC_DBICTL_RD_DBI_EN_SHIFT 2 -#define DDRC_DBICTL_RD_DBI_EN_MASK 0x00000004U +#define DDRC_DBICTL_RD_DBI_EN_DEFVAL 0x00000001 +#define DDRC_DBICTL_RD_DBI_EN_SHIFT 2 +#define DDRC_DBICTL_RD_DBI_EN_MASK 0x00000004U -/*Write DBI enable signal in DDRC. - 0 - Write DBI is disabled. - 1 - Write DBI is enabled. This signal must be set the same va - ue as DRAM's mode register. - DDR4: MR5 bit A11. When x4 devices are used, this signal must be set to 0. - LPDDR4: MR3[7]*/ +/* +* Write DBI enable signal in DDRC. - 0 - Write DBI is disabled. - 1 - Writ + * e DBI is enabled. This signal must be set the same value as DRAM's mode + * register. - DDR4: MR5 bit A11. When x4 devices are used, this signal mus + * t be set to 0. - LPDDR4: MR3[7] +*/ #undef DDRC_DBICTL_WR_DBI_EN_DEFVAL #undef DDRC_DBICTL_WR_DBI_EN_SHIFT #undef DDRC_DBICTL_WR_DBI_EN_MASK -#define DDRC_DBICTL_WR_DBI_EN_DEFVAL 0x00000001 -#define DDRC_DBICTL_WR_DBI_EN_SHIFT 1 -#define DDRC_DBICTL_WR_DBI_EN_MASK 0x00000002U +#define DDRC_DBICTL_WR_DBI_EN_DEFVAL 0x00000001 +#define DDRC_DBICTL_WR_DBI_EN_SHIFT 1 +#define DDRC_DBICTL_WR_DBI_EN_MASK 0x00000002U -/*DM enable signal in DDRC. - 0 - DM is disabled. - 1 - DM is enabled. This signal must be set the same logical value as DRAM's - mode register. - DDR4: Set this to same value as MR5 bit A10. When x4 devices are used, this signal must be set to 0. - LPDDR - : Set this to inverted value of MR13[5] which is opposite polarity from this signal*/ +/* +* DM enable signal in DDRC. - 0 - DM is disabled. - 1 - DM is enabled. Thi + * s signal must be set the same logical value as DRAM's mode register. - D + * DR4: Set this to same value as MR5 bit A10. When x4 devices are used, th + * is signal must be set to 0. - LPDDR4: Set this to inverted value of MR13 + * [5] which is opposite polarity from this signal +*/ #undef DDRC_DBICTL_DM_EN_DEFVAL #undef DDRC_DBICTL_DM_EN_SHIFT #undef DDRC_DBICTL_DM_EN_MASK -#define DDRC_DBICTL_DM_EN_DEFVAL 0x00000001 -#define DDRC_DBICTL_DM_EN_SHIFT 0 -#define DDRC_DBICTL_DM_EN_MASK 0x00000001U +#define DDRC_DBICTL_DM_EN_DEFVAL 0x00000001 +#define DDRC_DBICTL_DM_EN_SHIFT 0 +#define DDRC_DBICTL_DM_EN_MASK 0x00000001U -/*Selects the HIF address bit used as rank address bit 0. Valid Range: 0 to 27, and 31 Internal Base: 6 The selected HIF addres - bit is determined by adding the internal base to the value of this field. If set to 31, rank address bit 0 is set to 0.*/ +/* +* Selects the HIF address bit used as rank address bit 0. Valid Range: 0 t + * o 27, and 31 Internal Base: 6 The selected HIF address bit is determined + * by adding the internal base to the value of this field. If set to 31, r + * ank address bit 0 is set to 0. +*/ #undef DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_DEFVAL #undef DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_SHIFT #undef DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_MASK -#define DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_DEFVAL -#define DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_SHIFT 0 -#define DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_MASK 0x0000001FU +#define DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_DEFVAL +#define DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_SHIFT 0 +#define DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_MASK 0x0000001FU -/*Selects the HIF address bit used as bank address bit 2. Valid Range: 0 to 29 and 31 Internal Base: 4 The selected HIF address - bit is determined by adding the internal base to the value of this field. If set to 31, bank address bit 2 is set to 0.*/ +/* +* Selects the HIF address bit used as bank address bit 2. Valid Range: 0 t + * o 29 and 31 Internal Base: 4 The selected HIF address bit is determined + * by adding the internal base to the value of this field. If set to 31, ba + * nk address bit 2 is set to 0. +*/ #undef DDRC_ADDRMAP1_ADDRMAP_BANK_B2_DEFVAL #undef DDRC_ADDRMAP1_ADDRMAP_BANK_B2_SHIFT #undef DDRC_ADDRMAP1_ADDRMAP_BANK_B2_MASK -#define DDRC_ADDRMAP1_ADDRMAP_BANK_B2_DEFVAL 0x00000000 -#define DDRC_ADDRMAP1_ADDRMAP_BANK_B2_SHIFT 16 -#define DDRC_ADDRMAP1_ADDRMAP_BANK_B2_MASK 0x001F0000U +#define DDRC_ADDRMAP1_ADDRMAP_BANK_B2_DEFVAL 0x00000000 +#define DDRC_ADDRMAP1_ADDRMAP_BANK_B2_SHIFT 16 +#define DDRC_ADDRMAP1_ADDRMAP_BANK_B2_MASK 0x001F0000U -/*Selects the HIF address bits used as bank address bit 1. Valid Range: 0 to 30 Internal Base: 3 The selected HIF address bit f - r each of the bank address bits is determined by adding the internal base to the value of this field.*/ +/* +* Selects the HIF address bits used as bank address bit 1. Valid Range: 0 + * to 30 Internal Base: 3 The selected HIF address bit for each of the bank + * address bits is determined by adding the internal base to the value of + * this field. +*/ #undef DDRC_ADDRMAP1_ADDRMAP_BANK_B1_DEFVAL #undef DDRC_ADDRMAP1_ADDRMAP_BANK_B1_SHIFT #undef DDRC_ADDRMAP1_ADDRMAP_BANK_B1_MASK -#define DDRC_ADDRMAP1_ADDRMAP_BANK_B1_DEFVAL 0x00000000 -#define DDRC_ADDRMAP1_ADDRMAP_BANK_B1_SHIFT 8 -#define DDRC_ADDRMAP1_ADDRMAP_BANK_B1_MASK 0x00001F00U +#define DDRC_ADDRMAP1_ADDRMAP_BANK_B1_DEFVAL 0x00000000 +#define DDRC_ADDRMAP1_ADDRMAP_BANK_B1_SHIFT 8 +#define DDRC_ADDRMAP1_ADDRMAP_BANK_B1_MASK 0x00001F00U -/*Selects the HIF address bits used as bank address bit 0. Valid Range: 0 to 30 Internal Base: 2 The selected HIF address bit f - r each of the bank address bits is determined by adding the internal base to the value of this field.*/ +/* +* Selects the HIF address bits used as bank address bit 0. Valid Range: 0 + * to 30 Internal Base: 2 The selected HIF address bit for each of the bank + * address bits is determined by adding the internal base to the value of + * this field. +*/ #undef DDRC_ADDRMAP1_ADDRMAP_BANK_B0_DEFVAL #undef DDRC_ADDRMAP1_ADDRMAP_BANK_B0_SHIFT #undef DDRC_ADDRMAP1_ADDRMAP_BANK_B0_MASK -#define DDRC_ADDRMAP1_ADDRMAP_BANK_B0_DEFVAL 0x00000000 -#define DDRC_ADDRMAP1_ADDRMAP_BANK_B0_SHIFT 0 -#define DDRC_ADDRMAP1_ADDRMAP_BANK_B0_MASK 0x0000001FU +#define DDRC_ADDRMAP1_ADDRMAP_BANK_B0_DEFVAL 0x00000000 +#define DDRC_ADDRMAP1_ADDRMAP_BANK_B0_SHIFT 0 +#define DDRC_ADDRMAP1_ADDRMAP_BANK_B0_MASK 0x0000001FU -/*- Full bus width mode: Selects the HIF address bit used as column address bit 5. - Half bus width mode: Selects the HIF addre - s bit used as column address bit 6. - Quarter bus width mode: Selects the HIF address bit used as column address bit 7 . Vali - Range: 0 to 7, and 15 Internal Base: 5 The selected HIF address bit is determined by adding the internal base to the value o - this field. If set to 15, this column address bit is set to 0.*/ +/* +* - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 5. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 6. - Quarter bus width mode: Selects the HIF address bit + * used as column address bit 7 . Valid Range: 0 to 7, and 15 Internal Base + * : 5 The selected HIF address bit is determined by adding the internal ba + * se to the value of this field. If set to 15, this column address bit is + * set to 0. +*/ #undef DDRC_ADDRMAP2_ADDRMAP_COL_B5_DEFVAL #undef DDRC_ADDRMAP2_ADDRMAP_COL_B5_SHIFT #undef DDRC_ADDRMAP2_ADDRMAP_COL_B5_MASK -#define DDRC_ADDRMAP2_ADDRMAP_COL_B5_DEFVAL 0x00000000 -#define DDRC_ADDRMAP2_ADDRMAP_COL_B5_SHIFT 24 -#define DDRC_ADDRMAP2_ADDRMAP_COL_B5_MASK 0x0F000000U +#define DDRC_ADDRMAP2_ADDRMAP_COL_B5_DEFVAL 0x00000000 +#define DDRC_ADDRMAP2_ADDRMAP_COL_B5_SHIFT 24 +#define DDRC_ADDRMAP2_ADDRMAP_COL_B5_MASK 0x0F000000U -/*- Full bus width mode: Selects the HIF address bit used as column address bit 4. - Half bus width mode: Selects the HIF addre - s bit used as column address bit 5. - Quarter bus width mode: Selects the HIF address bit used as column address bit 6. Valid - Range: 0 to 7, and 15 Internal Base: 4 The selected HIF address bit is determined by adding the internal base to the value of - this field. If set to 15, this column address bit is set to 0.*/ +/* +* - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 4. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 5. - Quarter bus width mode: Selects the HIF address bit + * used as column address bit 6. Valid Range: 0 to 7, and 15 Internal Base: + * 4 The selected HIF address bit is determined by adding the internal bas + * e to the value of this field. If set to 15, this column address bit is s + * et to 0. +*/ #undef DDRC_ADDRMAP2_ADDRMAP_COL_B4_DEFVAL #undef DDRC_ADDRMAP2_ADDRMAP_COL_B4_SHIFT #undef DDRC_ADDRMAP2_ADDRMAP_COL_B4_MASK -#define DDRC_ADDRMAP2_ADDRMAP_COL_B4_DEFVAL 0x00000000 -#define DDRC_ADDRMAP2_ADDRMAP_COL_B4_SHIFT 16 -#define DDRC_ADDRMAP2_ADDRMAP_COL_B4_MASK 0x000F0000U +#define DDRC_ADDRMAP2_ADDRMAP_COL_B4_DEFVAL 0x00000000 +#define DDRC_ADDRMAP2_ADDRMAP_COL_B4_SHIFT 16 +#define DDRC_ADDRMAP2_ADDRMAP_COL_B4_MASK 0x000F0000U -/*- Full bus width mode: Selects the HIF address bit used as column address bit 3. - Half bus width mode: Selects the HIF addre - s bit used as column address bit 4. - Quarter bus width mode: Selects the HIF address bit used as column address bit 5. Valid - Range: 0 to 7 Internal Base: 3 The selected HIF address bit is determined by adding the internal base to the value of this fi - ld. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=16, it is required to program this to 0, hence register does not exist i - this case.*/ +/* +* - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 3. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 4. - Quarter bus width mode: Selects the HIF address bit + * used as column address bit 5. Valid Range: 0 to 7 Internal Base: 3 The s + * elected HIF address bit is determined by adding the internal base to the + * value of this field. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=1 + * 6, it is required to program this to 0, hence register does not exist in + * this case. +*/ #undef DDRC_ADDRMAP2_ADDRMAP_COL_B3_DEFVAL #undef DDRC_ADDRMAP2_ADDRMAP_COL_B3_SHIFT #undef DDRC_ADDRMAP2_ADDRMAP_COL_B3_MASK -#define DDRC_ADDRMAP2_ADDRMAP_COL_B3_DEFVAL 0x00000000 -#define DDRC_ADDRMAP2_ADDRMAP_COL_B3_SHIFT 8 -#define DDRC_ADDRMAP2_ADDRMAP_COL_B3_MASK 0x00000F00U +#define DDRC_ADDRMAP2_ADDRMAP_COL_B3_DEFVAL 0x00000000 +#define DDRC_ADDRMAP2_ADDRMAP_COL_B3_SHIFT 8 +#define DDRC_ADDRMAP2_ADDRMAP_COL_B3_MASK 0x00000F00U -/*- Full bus width mode: Selects the HIF address bit used as column address bit 2. - Half bus width mode: Selects the HIF addre - s bit used as column address bit 3. - Quarter bus width mode: Selects the HIF address bit used as column address bit 4. Valid - Range: 0 to 7 Internal Base: 2 The selected HIF address bit is determined by adding the internal base to the value of this fi - ld. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=8 or 16, it is required to program this to 0.*/ +/* +* - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 2. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 3. - Quarter bus width mode: Selects the HIF address bit + * used as column address bit 4. Valid Range: 0 to 7 Internal Base: 2 The s + * elected HIF address bit is determined by adding the internal base to the + * value of this field. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=8 + * or 16, it is required to program this to 0. +*/ #undef DDRC_ADDRMAP2_ADDRMAP_COL_B2_DEFVAL #undef DDRC_ADDRMAP2_ADDRMAP_COL_B2_SHIFT #undef DDRC_ADDRMAP2_ADDRMAP_COL_B2_MASK -#define DDRC_ADDRMAP2_ADDRMAP_COL_B2_DEFVAL 0x00000000 -#define DDRC_ADDRMAP2_ADDRMAP_COL_B2_SHIFT 0 -#define DDRC_ADDRMAP2_ADDRMAP_COL_B2_MASK 0x0000000FU +#define DDRC_ADDRMAP2_ADDRMAP_COL_B2_DEFVAL 0x00000000 +#define DDRC_ADDRMAP2_ADDRMAP_COL_B2_SHIFT 0 +#define DDRC_ADDRMAP2_ADDRMAP_COL_B2_MASK 0x0000000FU -/*- Full bus width mode: Selects the HIF address bit used as column address bit 9. - Half bus width mode: Selects the HIF addre - s bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). - Quarter bus width mode: Selects the HIF address bit used as - column address bit 13 (11 in LPDDR2/LPDDR3 mode). Valid Range: 0 to 7, and 15 Internal Base: 9 The selected HIF address bit i - determined by adding the internal base to the value of this field. If set to 15, this column address bit is set to 0. Note: - er JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source addr - ss bit can be mapped to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus an - hence column bit 10 is used.*/ +/* +* - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 9. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 11 (10 in LPDDR2/LPDDR3 mode). - Quarter bus width mode: + * Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/ + * LPDDR3 mode). Valid Range: 0 to 7, and 15 Internal Base: 9 The selected + * HIF address bit is determined by adding the internal base to the value o + * f this field. If set to 15, this column address bit is set to 0. Note: P + * er JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved fo + * r indicating auto-precharge, and hence no source address bit can be mapp + * ed to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit + * for auto-precharge in the CA bus and hence column bit 10 is used. +*/ #undef DDRC_ADDRMAP3_ADDRMAP_COL_B9_DEFVAL #undef DDRC_ADDRMAP3_ADDRMAP_COL_B9_SHIFT #undef DDRC_ADDRMAP3_ADDRMAP_COL_B9_MASK -#define DDRC_ADDRMAP3_ADDRMAP_COL_B9_DEFVAL 0x00000000 -#define DDRC_ADDRMAP3_ADDRMAP_COL_B9_SHIFT 24 -#define DDRC_ADDRMAP3_ADDRMAP_COL_B9_MASK 0x0F000000U +#define DDRC_ADDRMAP3_ADDRMAP_COL_B9_DEFVAL 0x00000000 +#define DDRC_ADDRMAP3_ADDRMAP_COL_B9_SHIFT 24 +#define DDRC_ADDRMAP3_ADDRMAP_COL_B9_MASK 0x0F000000U -/*- Full bus width mode: Selects the HIF address bit used as column address bit 8. - Half bus width mode: Selects the HIF addre - s bit used as column address bit 9. - Quarter bus width mode: Selects the HIF address bit used as column address bit 11 (10 i - LPDDR2/LPDDR3 mode). Valid Range: 0 to 7, and 15 Internal Base: 8 The selected HIF address bit is determined by adding the i - ternal base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specif - cation, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to col - mn address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and hence column bit 10 is use - .*/ +/* +* - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 8. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 9. - Quarter bus width mode: Selects the HIF address bit + * used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). Valid Range: 0 + * to 7, and 15 Internal Base: 8 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specifi + * cation, column address bit 10 is reserved for indicating auto-precharge, + * and hence no source address bit can be mapped to column address bit 10. + * In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA + * bus and hence column bit 10 is used. +*/ #undef DDRC_ADDRMAP3_ADDRMAP_COL_B8_DEFVAL #undef DDRC_ADDRMAP3_ADDRMAP_COL_B8_SHIFT #undef DDRC_ADDRMAP3_ADDRMAP_COL_B8_MASK -#define DDRC_ADDRMAP3_ADDRMAP_COL_B8_DEFVAL 0x00000000 -#define DDRC_ADDRMAP3_ADDRMAP_COL_B8_SHIFT 16 -#define DDRC_ADDRMAP3_ADDRMAP_COL_B8_MASK 0x000F0000U +#define DDRC_ADDRMAP3_ADDRMAP_COL_B8_DEFVAL 0x00000000 +#define DDRC_ADDRMAP3_ADDRMAP_COL_B8_SHIFT 16 +#define DDRC_ADDRMAP3_ADDRMAP_COL_B8_MASK 0x000F0000U -/*- Full bus width mode: Selects the HIF address bit used as column address bit 7. - Half bus width mode: Selects the HIF addre - s bit used as column address bit 8. - Quarter bus width mode: Selects the HIF address bit used as column address bit 9. Valid - Range: 0 to 7, and 15 Internal Base: 7 The selected HIF address bit is determined by adding the internal base to the value of - this field. If set to 15, this column address bit is set to 0.*/ +/* +* - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 7. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 8. - Quarter bus width mode: Selects the HIF address bit + * used as column address bit 9. Valid Range: 0 to 7, and 15 Internal Base: + * 7 The selected HIF address bit is determined by adding the internal bas + * e to the value of this field. If set to 15, this column address bit is s + * et to 0. +*/ #undef DDRC_ADDRMAP3_ADDRMAP_COL_B7_DEFVAL #undef DDRC_ADDRMAP3_ADDRMAP_COL_B7_SHIFT #undef DDRC_ADDRMAP3_ADDRMAP_COL_B7_MASK -#define DDRC_ADDRMAP3_ADDRMAP_COL_B7_DEFVAL 0x00000000 -#define DDRC_ADDRMAP3_ADDRMAP_COL_B7_SHIFT 8 -#define DDRC_ADDRMAP3_ADDRMAP_COL_B7_MASK 0x00000F00U +#define DDRC_ADDRMAP3_ADDRMAP_COL_B7_DEFVAL 0x00000000 +#define DDRC_ADDRMAP3_ADDRMAP_COL_B7_SHIFT 8 +#define DDRC_ADDRMAP3_ADDRMAP_COL_B7_MASK 0x00000F00U -/*- Full bus width mode: Selects the HIF address bit used as column address bit 6. - Half bus width mode: Selects the HIF addre - s bit used as column address bit 7. - Quarter bus width mode: Selects the HIF address bit used as column address bit 8. Valid - Range: 0 to 7, and 15 Internal Base: 6 The selected HIF address bit is determined by adding the internal base to the value of - this field. If set to 15, this column address bit is set to 0.*/ +/* +* - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 6. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 7. - Quarter bus width mode: Selects the HIF address bit + * used as column address bit 8. Valid Range: 0 to 7, and 15 Internal Base: + * 6 The selected HIF address bit is determined by adding the internal bas + * e to the value of this field. If set to 15, this column address bit is s + * et to 0. +*/ #undef DDRC_ADDRMAP3_ADDRMAP_COL_B6_DEFVAL #undef DDRC_ADDRMAP3_ADDRMAP_COL_B6_SHIFT #undef DDRC_ADDRMAP3_ADDRMAP_COL_B6_MASK -#define DDRC_ADDRMAP3_ADDRMAP_COL_B6_DEFVAL 0x00000000 -#define DDRC_ADDRMAP3_ADDRMAP_COL_B6_SHIFT 0 -#define DDRC_ADDRMAP3_ADDRMAP_COL_B6_MASK 0x0000000FU +#define DDRC_ADDRMAP3_ADDRMAP_COL_B6_DEFVAL 0x00000000 +#define DDRC_ADDRMAP3_ADDRMAP_COL_B6_SHIFT 0 +#define DDRC_ADDRMAP3_ADDRMAP_COL_B6_MASK 0x0000000FU -/*- Full bus width mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode). - Half bus width - mode: Unused. To make it unused, this should be tied to 4'hF. - Quarter bus width mode: Unused. To make it unused, this must - e tied to 4'hF. Valid Range: 0 to 7, and 15 Internal Base: 11 The selected HIF address bit is determined by adding the intern - l base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specificati - n, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column a - dress bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and hence column bit 10 is used.*/ +/* +* - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 13 (11 in LPDDR2/LPDDR3 mode). - Half bus width mode: Unused. To m + * ake it unused, this should be tied to 4'hF. - Quarter bus width mode: Un + * used. To make it unused, this must be tied to 4'hF. Valid Range: 0 to 7, + * and 15 Internal Base: 11 The selected HIF address bit is determined by + * adding the internal base to the value of this field. If set to 15, this + * column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specificatio + * n, column address bit 10 is reserved for indicating auto-precharge, and + * hence no source address bit can be mapped to column address bit 10. In L + * PDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus + * and hence column bit 10 is used. +*/ #undef DDRC_ADDRMAP4_ADDRMAP_COL_B11_DEFVAL #undef DDRC_ADDRMAP4_ADDRMAP_COL_B11_SHIFT #undef DDRC_ADDRMAP4_ADDRMAP_COL_B11_MASK -#define DDRC_ADDRMAP4_ADDRMAP_COL_B11_DEFVAL 0x00000000 -#define DDRC_ADDRMAP4_ADDRMAP_COL_B11_SHIFT 8 -#define DDRC_ADDRMAP4_ADDRMAP_COL_B11_MASK 0x00000F00U +#define DDRC_ADDRMAP4_ADDRMAP_COL_B11_DEFVAL 0x00000000 +#define DDRC_ADDRMAP4_ADDRMAP_COL_B11_SHIFT 8 +#define DDRC_ADDRMAP4_ADDRMAP_COL_B11_MASK 0x00000F00U -/*- Full bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). - Half bus width - mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode). - Quarter bus width mode: UNUSED. - To make it unused, this must be tied to 4'hF. Valid Range: 0 to 7, and 15 Internal Base: 10 The selected HIF address bit is d - termined by adding the internal base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per - JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source address - bit can be mapped to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and h - nce column bit 10 is used.*/ +/* +* - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 11 (10 in LPDDR2/LPDDR3 mode). - Half bus width mode: Selects the + * HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode) + * . - Quarter bus width mode: UNUSED. To make it unused, this must be tied + * to 4'hF. Valid Range: 0 to 7, and 15 Internal Base: 10 The selected HIF + * address bit is determined by adding the internal base to the value of t + * his field. If set to 15, this column address bit is set to 0. Note: Per + * JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for i + * ndicating auto-precharge, and hence no source address bit can be mapped + * to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for + * auto-precharge in the CA bus and hence column bit 10 is used. +*/ #undef DDRC_ADDRMAP4_ADDRMAP_COL_B10_DEFVAL #undef DDRC_ADDRMAP4_ADDRMAP_COL_B10_SHIFT #undef DDRC_ADDRMAP4_ADDRMAP_COL_B10_MASK -#define DDRC_ADDRMAP4_ADDRMAP_COL_B10_DEFVAL 0x00000000 -#define DDRC_ADDRMAP4_ADDRMAP_COL_B10_SHIFT 0 -#define DDRC_ADDRMAP4_ADDRMAP_COL_B10_MASK 0x0000000FU +#define DDRC_ADDRMAP4_ADDRMAP_COL_B10_DEFVAL 0x00000000 +#define DDRC_ADDRMAP4_ADDRMAP_COL_B10_SHIFT 0 +#define DDRC_ADDRMAP4_ADDRMAP_COL_B10_MASK 0x0000000FU -/*Selects the HIF address bit used as row address bit 11. Valid Range: 0 to 11, and 15 Internal Base: 17 The selected HIF addre - s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 11 is set to 0.*/ +/* +* Selects the HIF address bit used as row address bit 11. Valid Range: 0 t + * o 11, and 15 Internal Base: 17 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * row address bit 11 is set to 0. +*/ #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B11_DEFVAL #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B11_SHIFT #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B11_MASK -#define DDRC_ADDRMAP5_ADDRMAP_ROW_B11_DEFVAL 0x00000000 -#define DDRC_ADDRMAP5_ADDRMAP_ROW_B11_SHIFT 24 -#define DDRC_ADDRMAP5_ADDRMAP_ROW_B11_MASK 0x0F000000U +#define DDRC_ADDRMAP5_ADDRMAP_ROW_B11_DEFVAL 0x00000000 +#define DDRC_ADDRMAP5_ADDRMAP_ROW_B11_SHIFT 24 +#define DDRC_ADDRMAP5_ADDRMAP_ROW_B11_MASK 0x0F000000U -/*Selects the HIF address bits used as row address bits 2 to 10. Valid Range: 0 to 11, and 15 Internal Base: 8 (for row address - bit 2), 9 (for row address bit 3), 10 (for row address bit 4) etc increasing to 16 (for row address bit 10) The selected HIF - ddress bit for each of the row address bits is determined by adding the internal base to the value of this field. When value - 5 is used the values of row address bits 2 to 10 are defined by registers ADDRMAP9, ADDRMAP10, ADDRMAP11.*/ +/* +* Selects the HIF address bits used as row address bits 2 to 10. Valid Ran + * ge: 0 to 11, and 15 Internal Base: 8 (for row address bit 2), 9 (for row + * address bit 3), 10 (for row address bit 4) etc increasing to 16 (for ro + * w address bit 10) The selected HIF address bit for each of the row addre + * ss bits is determined by adding the internal base to the value of this f + * ield. When value 15 is used the values of row address bits 2 to 10 are d + * efined by registers ADDRMAP9, ADDRMAP10, ADDRMAP11. +*/ #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_DEFVAL #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_SHIFT #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_MASK -#define DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_DEFVAL 0x00000000 -#define DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_SHIFT 16 -#define DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_MASK 0x000F0000U +#define DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_DEFVAL 0x00000000 +#define DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_SHIFT 16 +#define DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_MASK 0x000F0000U -/*Selects the HIF address bits used as row address bit 1. Valid Range: 0 to 11 Internal Base: 7 The selected HIF address bit fo - each of the row address bits is determined by adding the internal base to the value of this field.*/ +/* +* Selects the HIF address bits used as row address bit 1. Valid Range: 0 t + * o 11 Internal Base: 7 The selected HIF address bit for each of the row a + * ddress bits is determined by adding the internal base to the value of th + * is field. +*/ #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B1_DEFVAL #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B1_SHIFT #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B1_MASK -#define DDRC_ADDRMAP5_ADDRMAP_ROW_B1_DEFVAL 0x00000000 -#define DDRC_ADDRMAP5_ADDRMAP_ROW_B1_SHIFT 8 -#define DDRC_ADDRMAP5_ADDRMAP_ROW_B1_MASK 0x00000F00U +#define DDRC_ADDRMAP5_ADDRMAP_ROW_B1_DEFVAL 0x00000000 +#define DDRC_ADDRMAP5_ADDRMAP_ROW_B1_SHIFT 8 +#define DDRC_ADDRMAP5_ADDRMAP_ROW_B1_MASK 0x00000F00U -/*Selects the HIF address bits used as row address bit 0. Valid Range: 0 to 11 Internal Base: 6 The selected HIF address bit fo - each of the row address bits is determined by adding the internal base to the value of this field.*/ +/* +* Selects the HIF address bits used as row address bit 0. Valid Range: 0 t + * o 11 Internal Base: 6 The selected HIF address bit for each of the row a + * ddress bits is determined by adding the internal base to the value of th + * is field. +*/ #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B0_DEFVAL #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B0_SHIFT #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B0_MASK -#define DDRC_ADDRMAP5_ADDRMAP_ROW_B0_DEFVAL 0x00000000 -#define DDRC_ADDRMAP5_ADDRMAP_ROW_B0_SHIFT 0 -#define DDRC_ADDRMAP5_ADDRMAP_ROW_B0_MASK 0x0000000FU +#define DDRC_ADDRMAP5_ADDRMAP_ROW_B0_DEFVAL 0x00000000 +#define DDRC_ADDRMAP5_ADDRMAP_ROW_B0_SHIFT 0 +#define DDRC_ADDRMAP5_ADDRMAP_ROW_B0_MASK 0x0000000FU -/*Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use. - 1 - LPDDR3 SDRAM 6Gb/12Gb device in use. Every address - having row[14:13]==2'b11 is considered as invalid - 0 - non-LPDDR3 6Gb/12Gb device in use. All addresses are valid Present on - y in designs configured to support LPDDR3.*/ +/* +* Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use. - 1 + * - LPDDR3 SDRAM 6Gb/12Gb device in use. Every address having row[14:13]= + * =2'b11 is considered as invalid - 0 - non-LPDDR3 6Gb/12Gb device in use. + * All addresses are valid Present only in designs configured to support L + * PDDR3. +*/ #undef DDRC_ADDRMAP6_LPDDR3_6GB_12GB_DEFVAL #undef DDRC_ADDRMAP6_LPDDR3_6GB_12GB_SHIFT #undef DDRC_ADDRMAP6_LPDDR3_6GB_12GB_MASK -#define DDRC_ADDRMAP6_LPDDR3_6GB_12GB_DEFVAL 0x00000000 -#define DDRC_ADDRMAP6_LPDDR3_6GB_12GB_SHIFT 31 -#define DDRC_ADDRMAP6_LPDDR3_6GB_12GB_MASK 0x80000000U +#define DDRC_ADDRMAP6_LPDDR3_6GB_12GB_DEFVAL 0x00000000 +#define DDRC_ADDRMAP6_LPDDR3_6GB_12GB_SHIFT 31 +#define DDRC_ADDRMAP6_LPDDR3_6GB_12GB_MASK 0x80000000U -/*Selects the HIF address bit used as row address bit 15. Valid Range: 0 to 11, and 15 Internal Base: 21 The selected HIF addre - s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 15 is set to 0.*/ +/* +* Selects the HIF address bit used as row address bit 15. Valid Range: 0 t + * o 11, and 15 Internal Base: 21 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * row address bit 15 is set to 0. +*/ #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B15_DEFVAL #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B15_SHIFT #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B15_MASK -#define DDRC_ADDRMAP6_ADDRMAP_ROW_B15_DEFVAL 0x00000000 -#define DDRC_ADDRMAP6_ADDRMAP_ROW_B15_SHIFT 24 -#define DDRC_ADDRMAP6_ADDRMAP_ROW_B15_MASK 0x0F000000U +#define DDRC_ADDRMAP6_ADDRMAP_ROW_B15_DEFVAL 0x00000000 +#define DDRC_ADDRMAP6_ADDRMAP_ROW_B15_SHIFT 24 +#define DDRC_ADDRMAP6_ADDRMAP_ROW_B15_MASK 0x0F000000U -/*Selects the HIF address bit used as row address bit 14. Valid Range: 0 to 11, and 15 Internal Base: 20 The selected HIF addre - s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 14 is set to 0.*/ +/* +* Selects the HIF address bit used as row address bit 14. Valid Range: 0 t + * o 11, and 15 Internal Base: 20 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * row address bit 14 is set to 0. +*/ #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B14_DEFVAL #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B14_SHIFT #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B14_MASK -#define DDRC_ADDRMAP6_ADDRMAP_ROW_B14_DEFVAL 0x00000000 -#define DDRC_ADDRMAP6_ADDRMAP_ROW_B14_SHIFT 16 -#define DDRC_ADDRMAP6_ADDRMAP_ROW_B14_MASK 0x000F0000U +#define DDRC_ADDRMAP6_ADDRMAP_ROW_B14_DEFVAL 0x00000000 +#define DDRC_ADDRMAP6_ADDRMAP_ROW_B14_SHIFT 16 +#define DDRC_ADDRMAP6_ADDRMAP_ROW_B14_MASK 0x000F0000U -/*Selects the HIF address bit used as row address bit 13. Valid Range: 0 to 11, and 15 Internal Base: 19 The selected HIF addre - s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 13 is set to 0.*/ +/* +* Selects the HIF address bit used as row address bit 13. Valid Range: 0 t + * o 11, and 15 Internal Base: 19 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * row address bit 13 is set to 0. +*/ #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B13_DEFVAL #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B13_SHIFT #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B13_MASK -#define DDRC_ADDRMAP6_ADDRMAP_ROW_B13_DEFVAL 0x00000000 -#define DDRC_ADDRMAP6_ADDRMAP_ROW_B13_SHIFT 8 -#define DDRC_ADDRMAP6_ADDRMAP_ROW_B13_MASK 0x00000F00U +#define DDRC_ADDRMAP6_ADDRMAP_ROW_B13_DEFVAL 0x00000000 +#define DDRC_ADDRMAP6_ADDRMAP_ROW_B13_SHIFT 8 +#define DDRC_ADDRMAP6_ADDRMAP_ROW_B13_MASK 0x00000F00U -/*Selects the HIF address bit used as row address bit 12. Valid Range: 0 to 11, and 15 Internal Base: 18 The selected HIF addre - s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 12 is set to 0.*/ +/* +* Selects the HIF address bit used as row address bit 12. Valid Range: 0 t + * o 11, and 15 Internal Base: 18 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * row address bit 12 is set to 0. +*/ #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B12_DEFVAL #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B12_SHIFT #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B12_MASK -#define DDRC_ADDRMAP6_ADDRMAP_ROW_B12_DEFVAL 0x00000000 -#define DDRC_ADDRMAP6_ADDRMAP_ROW_B12_SHIFT 0 -#define DDRC_ADDRMAP6_ADDRMAP_ROW_B12_MASK 0x0000000FU +#define DDRC_ADDRMAP6_ADDRMAP_ROW_B12_DEFVAL 0x00000000 +#define DDRC_ADDRMAP6_ADDRMAP_ROW_B12_SHIFT 0 +#define DDRC_ADDRMAP6_ADDRMAP_ROW_B12_MASK 0x0000000FU -/*Selects the HIF address bit used as row address bit 17. Valid Range: 0 to 10, and 15 Internal Base: 23 The selected HIF addre - s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 17 is set to 0.*/ +/* +* Selects the HIF address bit used as row address bit 17. Valid Range: 0 t + * o 10, and 15 Internal Base: 23 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * row address bit 17 is set to 0. +*/ #undef DDRC_ADDRMAP7_ADDRMAP_ROW_B17_DEFVAL #undef DDRC_ADDRMAP7_ADDRMAP_ROW_B17_SHIFT #undef DDRC_ADDRMAP7_ADDRMAP_ROW_B17_MASK -#define DDRC_ADDRMAP7_ADDRMAP_ROW_B17_DEFVAL 0x00000000 -#define DDRC_ADDRMAP7_ADDRMAP_ROW_B17_SHIFT 8 -#define DDRC_ADDRMAP7_ADDRMAP_ROW_B17_MASK 0x00000F00U +#define DDRC_ADDRMAP7_ADDRMAP_ROW_B17_DEFVAL 0x00000000 +#define DDRC_ADDRMAP7_ADDRMAP_ROW_B17_SHIFT 8 +#define DDRC_ADDRMAP7_ADDRMAP_ROW_B17_MASK 0x00000F00U -/*Selects the HIF address bit used as row address bit 16. Valid Range: 0 to 11, and 15 Internal Base: 22 The selected HIF addre - s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 16 is set to 0.*/ +/* +* Selects the HIF address bit used as row address bit 16. Valid Range: 0 t + * o 11, and 15 Internal Base: 22 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * row address bit 16 is set to 0. +*/ #undef DDRC_ADDRMAP7_ADDRMAP_ROW_B16_DEFVAL #undef DDRC_ADDRMAP7_ADDRMAP_ROW_B16_SHIFT #undef DDRC_ADDRMAP7_ADDRMAP_ROW_B16_MASK -#define DDRC_ADDRMAP7_ADDRMAP_ROW_B16_DEFVAL 0x00000000 -#define DDRC_ADDRMAP7_ADDRMAP_ROW_B16_SHIFT 0 -#define DDRC_ADDRMAP7_ADDRMAP_ROW_B16_MASK 0x0000000FU +#define DDRC_ADDRMAP7_ADDRMAP_ROW_B16_DEFVAL 0x00000000 +#define DDRC_ADDRMAP7_ADDRMAP_ROW_B16_SHIFT 0 +#define DDRC_ADDRMAP7_ADDRMAP_ROW_B16_MASK 0x0000000FU -/*Selects the HIF address bits used as bank group address bit 1. Valid Range: 0 to 30, and 31 Internal Base: 3 The selected HIF - address bit for each of the bank group address bits is determined by adding the internal base to the value of this field. If - et to 31, bank group address bit 1 is set to 0.*/ +/* +* Selects the HIF address bits used as bank group address bit 1. Valid Ran + * ge: 0 to 30, and 31 Internal Base: 3 The selected HIF address bit for ea + * ch of the bank group address bits is determined by adding the internal b + * ase to the value of this field. If set to 31, bank group address bit 1 i + * s set to 0. +*/ #undef DDRC_ADDRMAP8_ADDRMAP_BG_B1_DEFVAL #undef DDRC_ADDRMAP8_ADDRMAP_BG_B1_SHIFT #undef DDRC_ADDRMAP8_ADDRMAP_BG_B1_MASK -#define DDRC_ADDRMAP8_ADDRMAP_BG_B1_DEFVAL 0x00000000 -#define DDRC_ADDRMAP8_ADDRMAP_BG_B1_SHIFT 8 -#define DDRC_ADDRMAP8_ADDRMAP_BG_B1_MASK 0x00001F00U +#define DDRC_ADDRMAP8_ADDRMAP_BG_B1_DEFVAL 0x00000000 +#define DDRC_ADDRMAP8_ADDRMAP_BG_B1_SHIFT 8 +#define DDRC_ADDRMAP8_ADDRMAP_BG_B1_MASK 0x00001F00U -/*Selects the HIF address bits used as bank group address bit 0. Valid Range: 0 to 30 Internal Base: 2 The selected HIF address - bit for each of the bank group address bits is determined by adding the internal base to the value of this field.*/ +/* +* Selects the HIF address bits used as bank group address bit 0. Valid Ran + * ge: 0 to 30 Internal Base: 2 The selected HIF address bit for each of th + * e bank group address bits is determined by adding the internal base to t + * he value of this field. +*/ #undef DDRC_ADDRMAP8_ADDRMAP_BG_B0_DEFVAL #undef DDRC_ADDRMAP8_ADDRMAP_BG_B0_SHIFT #undef DDRC_ADDRMAP8_ADDRMAP_BG_B0_MASK -#define DDRC_ADDRMAP8_ADDRMAP_BG_B0_DEFVAL 0x00000000 -#define DDRC_ADDRMAP8_ADDRMAP_BG_B0_SHIFT 0 -#define DDRC_ADDRMAP8_ADDRMAP_BG_B0_MASK 0x0000001FU +#define DDRC_ADDRMAP8_ADDRMAP_BG_B0_DEFVAL 0x00000000 +#define DDRC_ADDRMAP8_ADDRMAP_BG_B0_SHIFT 0 +#define DDRC_ADDRMAP8_ADDRMAP_BG_B0_MASK 0x0000001FU -/*Selects the HIF address bits used as row address bit 5. Valid Range: 0 to 11 Internal Base: 11 The selected HIF address bit f - r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u - ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/ +/* +* Selects the HIF address bits used as row address bit 5. Valid Range: 0 t + * o 11 Internal Base: 11 The selected HIF address bit for each of the row + * address bits is determined by adding the internal base to the value of t + * his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + * _10 is set to value 15. +*/ #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B5_DEFVAL #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B5_SHIFT #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B5_MASK -#define DDRC_ADDRMAP9_ADDRMAP_ROW_B5_DEFVAL 0x00000000 -#define DDRC_ADDRMAP9_ADDRMAP_ROW_B5_SHIFT 24 -#define DDRC_ADDRMAP9_ADDRMAP_ROW_B5_MASK 0x0F000000U +#define DDRC_ADDRMAP9_ADDRMAP_ROW_B5_DEFVAL 0x00000000 +#define DDRC_ADDRMAP9_ADDRMAP_ROW_B5_SHIFT 24 +#define DDRC_ADDRMAP9_ADDRMAP_ROW_B5_MASK 0x0F000000U -/*Selects the HIF address bits used as row address bit 4. Valid Range: 0 to 11 Internal Base: 10 The selected HIF address bit f - r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u - ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/ +/* +* Selects the HIF address bits used as row address bit 4. Valid Range: 0 t + * o 11 Internal Base: 10 The selected HIF address bit for each of the row + * address bits is determined by adding the internal base to the value of t + * his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + * _10 is set to value 15. +*/ #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B4_DEFVAL #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B4_SHIFT #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B4_MASK -#define DDRC_ADDRMAP9_ADDRMAP_ROW_B4_DEFVAL 0x00000000 -#define DDRC_ADDRMAP9_ADDRMAP_ROW_B4_SHIFT 16 -#define DDRC_ADDRMAP9_ADDRMAP_ROW_B4_MASK 0x000F0000U +#define DDRC_ADDRMAP9_ADDRMAP_ROW_B4_DEFVAL 0x00000000 +#define DDRC_ADDRMAP9_ADDRMAP_ROW_B4_SHIFT 16 +#define DDRC_ADDRMAP9_ADDRMAP_ROW_B4_MASK 0x000F0000U -/*Selects the HIF address bits used as row address bit 3. Valid Range: 0 to 11 Internal Base: 9 The selected HIF address bit fo - each of the row address bits is determined by adding the internal base to the value of this field. This register field is us - d only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/ +/* +* Selects the HIF address bits used as row address bit 3. Valid Range: 0 t + * o 11 Internal Base: 9 The selected HIF address bit for each of the row a + * ddress bits is determined by adding the internal base to the value of th + * is field. This register field is used only when ADDRMAP5.addrmap_row_b2_ + * 10 is set to value 15. +*/ #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B3_DEFVAL #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B3_SHIFT #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B3_MASK -#define DDRC_ADDRMAP9_ADDRMAP_ROW_B3_DEFVAL 0x00000000 -#define DDRC_ADDRMAP9_ADDRMAP_ROW_B3_SHIFT 8 -#define DDRC_ADDRMAP9_ADDRMAP_ROW_B3_MASK 0x00000F00U +#define DDRC_ADDRMAP9_ADDRMAP_ROW_B3_DEFVAL 0x00000000 +#define DDRC_ADDRMAP9_ADDRMAP_ROW_B3_SHIFT 8 +#define DDRC_ADDRMAP9_ADDRMAP_ROW_B3_MASK 0x00000F00U -/*Selects the HIF address bits used as row address bit 2. Valid Range: 0 to 11 Internal Base: 8 The selected HIF address bit fo - each of the row address bits is determined by adding the internal base to the value of this field. This register field is us - d only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/ +/* +* Selects the HIF address bits used as row address bit 2. Valid Range: 0 t + * o 11 Internal Base: 8 The selected HIF address bit for each of the row a + * ddress bits is determined by adding the internal base to the value of th + * is field. This register field is used only when ADDRMAP5.addrmap_row_b2_ + * 10 is set to value 15. +*/ #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B2_DEFVAL #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B2_SHIFT #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B2_MASK -#define DDRC_ADDRMAP9_ADDRMAP_ROW_B2_DEFVAL 0x00000000 -#define DDRC_ADDRMAP9_ADDRMAP_ROW_B2_SHIFT 0 -#define DDRC_ADDRMAP9_ADDRMAP_ROW_B2_MASK 0x0000000FU +#define DDRC_ADDRMAP9_ADDRMAP_ROW_B2_DEFVAL 0x00000000 +#define DDRC_ADDRMAP9_ADDRMAP_ROW_B2_SHIFT 0 +#define DDRC_ADDRMAP9_ADDRMAP_ROW_B2_MASK 0x0000000FU -/*Selects the HIF address bits used as row address bit 9. Valid Range: 0 to 11 Internal Base: 15 The selected HIF address bit f - r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u - ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/ +/* +* Selects the HIF address bits used as row address bit 9. Valid Range: 0 t + * o 11 Internal Base: 15 The selected HIF address bit for each of the row + * address bits is determined by adding the internal base to the value of t + * his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + * _10 is set to value 15. +*/ #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B9_DEFVAL #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B9_SHIFT #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B9_MASK -#define DDRC_ADDRMAP10_ADDRMAP_ROW_B9_DEFVAL 0x00000000 -#define DDRC_ADDRMAP10_ADDRMAP_ROW_B9_SHIFT 24 -#define DDRC_ADDRMAP10_ADDRMAP_ROW_B9_MASK 0x0F000000U +#define DDRC_ADDRMAP10_ADDRMAP_ROW_B9_DEFVAL 0x00000000 +#define DDRC_ADDRMAP10_ADDRMAP_ROW_B9_SHIFT 24 +#define DDRC_ADDRMAP10_ADDRMAP_ROW_B9_MASK 0x0F000000U -/*Selects the HIF address bits used as row address bit 8. Valid Range: 0 to 11 Internal Base: 14 The selected HIF address bit f - r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u - ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/ +/* +* Selects the HIF address bits used as row address bit 8. Valid Range: 0 t + * o 11 Internal Base: 14 The selected HIF address bit for each of the row + * address bits is determined by adding the internal base to the value of t + * his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + * _10 is set to value 15. +*/ #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B8_DEFVAL #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B8_SHIFT #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B8_MASK -#define DDRC_ADDRMAP10_ADDRMAP_ROW_B8_DEFVAL 0x00000000 -#define DDRC_ADDRMAP10_ADDRMAP_ROW_B8_SHIFT 16 -#define DDRC_ADDRMAP10_ADDRMAP_ROW_B8_MASK 0x000F0000U +#define DDRC_ADDRMAP10_ADDRMAP_ROW_B8_DEFVAL 0x00000000 +#define DDRC_ADDRMAP10_ADDRMAP_ROW_B8_SHIFT 16 +#define DDRC_ADDRMAP10_ADDRMAP_ROW_B8_MASK 0x000F0000U -/*Selects the HIF address bits used as row address bit 7. Valid Range: 0 to 11 Internal Base: 13 The selected HIF address bit f - r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u - ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/ +/* +* Selects the HIF address bits used as row address bit 7. Valid Range: 0 t + * o 11 Internal Base: 13 The selected HIF address bit for each of the row + * address bits is determined by adding the internal base to the value of t + * his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + * _10 is set to value 15. +*/ #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B7_DEFVAL #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B7_SHIFT #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B7_MASK -#define DDRC_ADDRMAP10_ADDRMAP_ROW_B7_DEFVAL 0x00000000 -#define DDRC_ADDRMAP10_ADDRMAP_ROW_B7_SHIFT 8 -#define DDRC_ADDRMAP10_ADDRMAP_ROW_B7_MASK 0x00000F00U +#define DDRC_ADDRMAP10_ADDRMAP_ROW_B7_DEFVAL 0x00000000 +#define DDRC_ADDRMAP10_ADDRMAP_ROW_B7_SHIFT 8 +#define DDRC_ADDRMAP10_ADDRMAP_ROW_B7_MASK 0x00000F00U -/*Selects the HIF address bits used as row address bit 6. Valid Range: 0 to 11 Internal Base: 12 The selected HIF address bit f - r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u - ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/ +/* +* Selects the HIF address bits used as row address bit 6. Valid Range: 0 t + * o 11 Internal Base: 12 The selected HIF address bit for each of the row + * address bits is determined by adding the internal base to the value of t + * his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + * _10 is set to value 15. +*/ #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B6_DEFVAL #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B6_SHIFT #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B6_MASK -#define DDRC_ADDRMAP10_ADDRMAP_ROW_B6_DEFVAL 0x00000000 -#define DDRC_ADDRMAP10_ADDRMAP_ROW_B6_SHIFT 0 -#define DDRC_ADDRMAP10_ADDRMAP_ROW_B6_MASK 0x0000000FU +#define DDRC_ADDRMAP10_ADDRMAP_ROW_B6_DEFVAL 0x00000000 +#define DDRC_ADDRMAP10_ADDRMAP_ROW_B6_SHIFT 0 +#define DDRC_ADDRMAP10_ADDRMAP_ROW_B6_MASK 0x0000000FU -/*Selects the HIF address bits used as row address bit 10. Valid Range: 0 to 11 Internal Base: 16 The selected HIF address bit - or each of the row address bits is determined by adding the internal base to the value of this field. This register field is - sed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/ +/* +* Selects the HIF address bits used as row address bit 10. Valid Range: 0 + * to 11 Internal Base: 16 The selected HIF address bit for each of the row + * address bits is determined by adding the internal base to the value of + * this field. This register field is used only when ADDRMAP5.addrmap_row_b + * 2_10 is set to value 15. +*/ #undef DDRC_ADDRMAP11_ADDRMAP_ROW_B10_DEFVAL #undef DDRC_ADDRMAP11_ADDRMAP_ROW_B10_SHIFT #undef DDRC_ADDRMAP11_ADDRMAP_ROW_B10_MASK -#define DDRC_ADDRMAP11_ADDRMAP_ROW_B10_DEFVAL -#define DDRC_ADDRMAP11_ADDRMAP_ROW_B10_SHIFT 0 -#define DDRC_ADDRMAP11_ADDRMAP_ROW_B10_MASK 0x0000000FU +#define DDRC_ADDRMAP11_ADDRMAP_ROW_B10_DEFVAL +#define DDRC_ADDRMAP11_ADDRMAP_ROW_B10_SHIFT 0 +#define DDRC_ADDRMAP11_ADDRMAP_ROW_B10_MASK 0x0000000FU -/*Cycles to hold ODT for a write command. The minimum supported value is 2. Recommended values: DDR2: - BL8: 0x5 (DDR2-400/533/ - 67), 0x6 (DDR2-800), 0x7 (DDR2-1066) - BL4: 0x3 (DDR2-400/533/667), 0x4 (DDR2-800), 0x5 (DDR2-1066) DDR3: - BL8: 0x6 DDR4: - - L8: 5 + WR_PREAMBLE + CRC_MODE WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) CRC_MODE = 0 (not CRC mode), 1 - CRC mode) LPDDR3: - BL8: 7 + RU(tODTon(max)/tCK)*/ +/* +* Cycles to hold ODT for a write command. The minimum supported value is 2 + * . Recommended values: DDR2: - BL8: 0x5 (DDR2-400/533/667), 0x6 (DDR2-800 + * ), 0x7 (DDR2-1066) - BL4: 0x3 (DDR2-400/533/667), 0x4 (DDR2-800), 0x5 (D + * DR2-1066) DDR3: - BL8: 0x6 DDR4: - BL8: 5 + WR_PREAMBLE + CRC_MODE WR_PR + * EAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) CRC_MODE = 0 ( + * not CRC mode), 1 (CRC mode) LPDDR3: - BL8: 7 + RU(tODTon(max)/tCK) +*/ #undef DDRC_ODTCFG_WR_ODT_HOLD_DEFVAL #undef DDRC_ODTCFG_WR_ODT_HOLD_SHIFT #undef DDRC_ODTCFG_WR_ODT_HOLD_MASK -#define DDRC_ODTCFG_WR_ODT_HOLD_DEFVAL 0x04000400 -#define DDRC_ODTCFG_WR_ODT_HOLD_SHIFT 24 -#define DDRC_ODTCFG_WR_ODT_HOLD_MASK 0x0F000000U +#define DDRC_ODTCFG_WR_ODT_HOLD_DEFVAL 0x04000400 +#define DDRC_ODTCFG_WR_ODT_HOLD_SHIFT 24 +#define DDRC_ODTCFG_WR_ODT_HOLD_MASK 0x0F000000U -/*The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting must - remain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: - CWL + AL - 3 (DDR2-400/533/ - 67), CWL + AL - 4 (DDR2-800), CWL + AL - 5 (DDR2-1066) If (CWL + AL - 3 < 0), uMCTL2 does not support ODT for write operation - DDR3: - 0x0 DDR4: - DFITMG1.dfi_t_cmd_lat (to adjust for CAL mode) LPDDR3: - WL - 1 - RU(tODTon(max)/tCK))*/ +/* +* The delay, in clock cycles, from issuing a write command to setting ODT + * values associated with that command. ODT setting must remain constant fo + * r the entire time that DQS is driven by the uMCTL2. Recommended values: + * DDR2: - CWL + AL - 3 (DDR2-400/533/667), CWL + AL - 4 (DDR2-800), CWL + + * AL - 5 (DDR2-1066) If (CWL + AL - 3 < 0), uMCTL2 does not support ODT fo + * r write operation. DDR3: - 0x0 DDR4: - DFITMG1.dfi_t_cmd_lat (to adjust + * for CAL mode) LPDDR3: - WL - 1 - RU(tODTon(max)/tCK)) +*/ #undef DDRC_ODTCFG_WR_ODT_DELAY_DEFVAL #undef DDRC_ODTCFG_WR_ODT_DELAY_SHIFT #undef DDRC_ODTCFG_WR_ODT_DELAY_MASK -#define DDRC_ODTCFG_WR_ODT_DELAY_DEFVAL 0x04000400 -#define DDRC_ODTCFG_WR_ODT_DELAY_SHIFT 16 -#define DDRC_ODTCFG_WR_ODT_DELAY_MASK 0x001F0000U +#define DDRC_ODTCFG_WR_ODT_DELAY_DEFVAL 0x04000400 +#define DDRC_ODTCFG_WR_ODT_DELAY_SHIFT 16 +#define DDRC_ODTCFG_WR_ODT_DELAY_MASK 0x001F0000U -/*Cycles to hold ODT for a read command. The minimum supported value is 2. Recommended values: DDR2: - BL8: 0x6 (not DDR2-1066) - 0x7 (DDR2-1066) - BL4: 0x4 (not DDR2-1066), 0x5 (DDR2-1066) DDR3: - BL8 - 0x6 DDR4: - BL8: 5 + RD_PREAMBLE RD_PREAMBLE = 1 ( - tCK write preamble), 2 (2tCK write preamble) LPDDR3: - BL8: 5 + RU(tDQSCK(max)/tCK) - RD(tDQSCK(min)/tCK) + RU(tODTon(max)/tC - )*/ +/* +* Cycles to hold ODT for a read command. The minimum supported value is 2. + * Recommended values: DDR2: - BL8: 0x6 (not DDR2-1066), 0x7 (DDR2-1066) - + * BL4: 0x4 (not DDR2-1066), 0x5 (DDR2-1066) DDR3: - BL8 - 0x6 DDR4: - BL8 + * : 5 + RD_PREAMBLE RD_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write p + * reamble) LPDDR3: - BL8: 5 + RU(tDQSCK(max)/tCK) - RD(tDQSCK(min)/tCK) + + * RU(tODTon(max)/tCK) +*/ #undef DDRC_ODTCFG_RD_ODT_HOLD_DEFVAL #undef DDRC_ODTCFG_RD_ODT_HOLD_SHIFT #undef DDRC_ODTCFG_RD_ODT_HOLD_MASK -#define DDRC_ODTCFG_RD_ODT_HOLD_DEFVAL 0x04000400 -#define DDRC_ODTCFG_RD_ODT_HOLD_SHIFT 8 -#define DDRC_ODTCFG_RD_ODT_HOLD_MASK 0x00000F00U +#define DDRC_ODTCFG_RD_ODT_HOLD_DEFVAL 0x04000400 +#define DDRC_ODTCFG_RD_ODT_HOLD_SHIFT 8 +#define DDRC_ODTCFG_RD_ODT_HOLD_MASK 0x00000F00U -/*The delay, in clock cycles, from issuing a read command to setting ODT values associated with that command. ODT setting must - emain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: - CL + AL - 4 (not DDR2-1066), - CL + AL - 5 (DDR2-1066) If (CL + AL - 4 < 0), uMCTL2 does not support ODT for read operation. DDR3: - CL - CWL DDR4: - CL - C - L - RD_PREAMBLE + WR_PREAMBLE + DFITMG1.dfi_t_cmd_lat (to adjust for CAL mode) WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK - write preamble) RD_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) If (CL - CWL - RD_PREAMBLE + WR_PREAMBLE) < 0, - uMCTL2 does not support ODT for read operation. LPDDR3: - RL + RD(tDQSCK(min)/tCK) - 1 - RU(tODTon(max)/tCK)*/ +/* +* The delay, in clock cycles, from issuing a read command to setting ODT v + * alues associated with that command. ODT setting must remain constant for + * the entire time that DQS is driven by the uMCTL2. Recommended values: D + * DR2: - CL + AL - 4 (not DDR2-1066), CL + AL - 5 (DDR2-1066) If (CL + AL + * - 4 < 0), uMCTL2 does not support ODT for read operation. DDR3: - CL - C + * WL DDR4: - CL - CWL - RD_PREAMBLE + WR_PREAMBLE + DFITMG1.dfi_t_cmd_lat + * (to adjust for CAL mode) WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK + * write preamble) RD_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write pre + * amble) If (CL - CWL - RD_PREAMBLE + WR_PREAMBLE) < 0, uMCTL2 does not su + * pport ODT for read operation. LPDDR3: - RL + RD(tDQSCK(min)/tCK) - 1 - R + * U(tODTon(max)/tCK) +*/ #undef DDRC_ODTCFG_RD_ODT_DELAY_DEFVAL #undef DDRC_ODTCFG_RD_ODT_DELAY_SHIFT #undef DDRC_ODTCFG_RD_ODT_DELAY_MASK -#define DDRC_ODTCFG_RD_ODT_DELAY_DEFVAL 0x04000400 -#define DDRC_ODTCFG_RD_ODT_DELAY_SHIFT 2 -#define DDRC_ODTCFG_RD_ODT_DELAY_MASK 0x0000007CU +#define DDRC_ODTCFG_RD_ODT_DELAY_DEFVAL 0x04000400 +#define DDRC_ODTCFG_RD_ODT_DELAY_SHIFT 2 +#define DDRC_ODTCFG_RD_ODT_DELAY_MASK 0x0000007CU -/*Indicates which remote ODTs must be turned on during a read from rank 1. Each rank has a remote ODT (in the SDRAM) which can - e turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB - etc. For each rank, set its bit to 1 to enable its ODT. Present only in configurations that have 2 or more ranks*/ +/* +* Indicates which remote ODTs must be turned on during a read from rank 1. + * Each rank has a remote ODT (in the SDRAM) which can be turned on by set + * ting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 i + * s controlled by bit next to the LSB, etc. For each rank, set its bit to + * 1 to enable its ODT. Present only in configurations that have 2 or more + * ranks +*/ #undef DDRC_ODTMAP_RANK1_RD_ODT_DEFVAL #undef DDRC_ODTMAP_RANK1_RD_ODT_SHIFT #undef DDRC_ODTMAP_RANK1_RD_ODT_MASK -#define DDRC_ODTMAP_RANK1_RD_ODT_DEFVAL 0x00002211 -#define DDRC_ODTMAP_RANK1_RD_ODT_SHIFT 12 -#define DDRC_ODTMAP_RANK1_RD_ODT_MASK 0x00003000U +#define DDRC_ODTMAP_RANK1_RD_ODT_DEFVAL 0x00002211 +#define DDRC_ODTMAP_RANK1_RD_ODT_SHIFT 12 +#define DDRC_ODTMAP_RANK1_RD_ODT_MASK 0x00003000U -/*Indicates which remote ODTs must be turned on during a write to rank 1. Each rank has a remote ODT (in the SDRAM) which can b - turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB, - etc. For each rank, set its bit to 1 to enable its ODT. Present only in configurations that have 2 or more ranks*/ +/* +* Indicates which remote ODTs must be turned on during a write to rank 1. + * Each rank has a remote ODT (in the SDRAM) which can be turned on by sett + * ing the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is + * controlled by bit next to the LSB, etc. For each rank, set its bit to 1 + * to enable its ODT. Present only in configurations that have 2 or more r + * anks +*/ #undef DDRC_ODTMAP_RANK1_WR_ODT_DEFVAL #undef DDRC_ODTMAP_RANK1_WR_ODT_SHIFT #undef DDRC_ODTMAP_RANK1_WR_ODT_MASK -#define DDRC_ODTMAP_RANK1_WR_ODT_DEFVAL 0x00002211 -#define DDRC_ODTMAP_RANK1_WR_ODT_SHIFT 8 -#define DDRC_ODTMAP_RANK1_WR_ODT_MASK 0x00000300U +#define DDRC_ODTMAP_RANK1_WR_ODT_DEFVAL 0x00002211 +#define DDRC_ODTMAP_RANK1_WR_ODT_SHIFT 8 +#define DDRC_ODTMAP_RANK1_WR_ODT_MASK 0x00000300U -/*Indicates which remote ODTs must be turned on during a read from rank 0. Each rank has a remote ODT (in the SDRAM) which can - e turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB - etc. For each rank, set its bit to 1 to enable its ODT.*/ +/* +* Indicates which remote ODTs must be turned on during a read from rank 0. + * Each rank has a remote ODT (in the SDRAM) which can be turned on by set + * ting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 i + * s controlled by bit next to the LSB, etc. For each rank, set its bit to + * 1 to enable its ODT. +*/ #undef DDRC_ODTMAP_RANK0_RD_ODT_DEFVAL #undef DDRC_ODTMAP_RANK0_RD_ODT_SHIFT #undef DDRC_ODTMAP_RANK0_RD_ODT_MASK -#define DDRC_ODTMAP_RANK0_RD_ODT_DEFVAL 0x00002211 -#define DDRC_ODTMAP_RANK0_RD_ODT_SHIFT 4 -#define DDRC_ODTMAP_RANK0_RD_ODT_MASK 0x00000030U +#define DDRC_ODTMAP_RANK0_RD_ODT_DEFVAL 0x00002211 +#define DDRC_ODTMAP_RANK0_RD_ODT_SHIFT 4 +#define DDRC_ODTMAP_RANK0_RD_ODT_MASK 0x00000030U -/*Indicates which remote ODTs must be turned on during a write to rank 0. Each rank has a remote ODT (in the SDRAM) which can b - turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB, - etc. For each rank, set its bit to 1 to enable its ODT.*/ +/* +* Indicates which remote ODTs must be turned on during a write to rank 0. + * Each rank has a remote ODT (in the SDRAM) which can be turned on by sett + * ing the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is + * controlled by bit next to the LSB, etc. For each rank, set its bit to 1 + * to enable its ODT. +*/ #undef DDRC_ODTMAP_RANK0_WR_ODT_DEFVAL #undef DDRC_ODTMAP_RANK0_WR_ODT_SHIFT #undef DDRC_ODTMAP_RANK0_WR_ODT_MASK -#define DDRC_ODTMAP_RANK0_WR_ODT_DEFVAL 0x00002211 -#define DDRC_ODTMAP_RANK0_WR_ODT_SHIFT 0 -#define DDRC_ODTMAP_RANK0_WR_ODT_MASK 0x00000003U +#define DDRC_ODTMAP_RANK0_WR_ODT_DEFVAL 0x00002211 +#define DDRC_ODTMAP_RANK0_WR_ODT_SHIFT 0 +#define DDRC_ODTMAP_RANK0_WR_ODT_MASK 0x00000003U -/*When the preferred transaction store is empty for these many clock cycles, switch to the alternate transaction store if it is - non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write t - ansaction store is the alternative store. When prefer write over read is set this is reversed. 0x0 is a legal value for this - egister. When set to 0x0, the transaction store switching will happen immediately when the switching conditions become true. - OR PERFORMANCE ONLY*/ +/* +* When the preferred transaction store is empty for these many clock cycle + * s, switch to the alternate transaction store if it is non-empty. The rea + * d transaction store (both high and low priority) is the default preferre + * d transaction store and the write transaction store is the alternative s + * tore. When prefer write over read is set this is reversed. 0x0 is a lega + * l value for this register. When set to 0x0, the transaction store switch + * ing will happen immediately when the switching conditions become true. F + * OR PERFORMANCE ONLY +*/ #undef DDRC_SCHED_RDWR_IDLE_GAP_DEFVAL #undef DDRC_SCHED_RDWR_IDLE_GAP_SHIFT #undef DDRC_SCHED_RDWR_IDLE_GAP_MASK -#define DDRC_SCHED_RDWR_IDLE_GAP_DEFVAL 0x00002005 -#define DDRC_SCHED_RDWR_IDLE_GAP_SHIFT 24 -#define DDRC_SCHED_RDWR_IDLE_GAP_MASK 0x7F000000U +#define DDRC_SCHED_RDWR_IDLE_GAP_DEFVAL 0x00002005 +#define DDRC_SCHED_RDWR_IDLE_GAP_SHIFT 24 +#define DDRC_SCHED_RDWR_IDLE_GAP_MASK 0x7F000000U -/*UNUSED*/ +/* +* UNUSED +*/ #undef DDRC_SCHED_GO2CRITICAL_HYSTERESIS_DEFVAL #undef DDRC_SCHED_GO2CRITICAL_HYSTERESIS_SHIFT #undef DDRC_SCHED_GO2CRITICAL_HYSTERESIS_MASK -#define DDRC_SCHED_GO2CRITICAL_HYSTERESIS_DEFVAL 0x00002005 -#define DDRC_SCHED_GO2CRITICAL_HYSTERESIS_SHIFT 16 -#define DDRC_SCHED_GO2CRITICAL_HYSTERESIS_MASK 0x00FF0000U +#define DDRC_SCHED_GO2CRITICAL_HYSTERESIS_DEFVAL 0x00002005 +#define DDRC_SCHED_GO2CRITICAL_HYSTERESIS_SHIFT 16 +#define DDRC_SCHED_GO2CRITICAL_HYSTERESIS_MASK 0x00FF0000U -/*Number of entries in the low priority transaction store is this value + 1. (MEMC_NO_OF_ENTRY - (SCHED.lpr_num_entries + 1)) i - the number of entries available for the high priority transaction store. Setting this to maximum value allocates all entries - to low priority transaction store. Setting this to 0 allocates 1 entry to low priority transaction store and the rest to high - priority transaction store. Note: In ECC configurations, the numbers of write and low priority read credits issued is one les - than in the non-ECC case. One entry each is reserved in the write and low-priority read CAMs for storing the RMW requests ar - sing out of single bit error correction RMW operation.*/ +/* +* Number of entries in the low priority transaction store is this value + + * 1. (MEMC_NO_OF_ENTRY - (SCHED.lpr_num_entries + 1)) is the number of ent + * ries available for the high priority transaction store. Setting this to + * maximum value allocates all entries to low priority transaction store. S + * etting this to 0 allocates 1 entry to low priority transaction store and + * the rest to high priority transaction store. Note: In ECC configuration + * s, the numbers of write and low priority read credits issued is one less + * than in the non-ECC case. One entry each is reserved in the write and l + * ow-priority read CAMs for storing the RMW requests arising out of single + * bit error correction RMW operation. +*/ #undef DDRC_SCHED_LPR_NUM_ENTRIES_DEFVAL #undef DDRC_SCHED_LPR_NUM_ENTRIES_SHIFT #undef DDRC_SCHED_LPR_NUM_ENTRIES_MASK -#define DDRC_SCHED_LPR_NUM_ENTRIES_DEFVAL 0x00002005 -#define DDRC_SCHED_LPR_NUM_ENTRIES_SHIFT 8 -#define DDRC_SCHED_LPR_NUM_ENTRIES_MASK 0x00003F00U +#define DDRC_SCHED_LPR_NUM_ENTRIES_DEFVAL 0x00002005 +#define DDRC_SCHED_LPR_NUM_ENTRIES_SHIFT 8 +#define DDRC_SCHED_LPR_NUM_ENTRIES_MASK 0x00003F00U -/*If true, bank is kept open only while there are page hit transactions available in the CAM to that bank. The last read or wri - e command in the CAM with a bank and page hit will be executed with auto-precharge if SCHED1.pageclose_timer=0. Even if this - egister set to 1 and SCHED1.pageclose_timer is set to 0, explicit precharge (and not auto-precharge) may be issued in some ca - es where there is a mode switch between Write and Read or between LPR and HPR. The Read and Write commands that are executed - s part of the ECC scrub requests are also executed without auto-precharge. If false, the bank remains open until there is a n - ed to close it (to open a different page, or for page timeout or refresh timeout) - also known as open page policy. The open - age policy can be overridden by setting the per-command-autopre bit on the HIF interface (hif_cmd_autopre). The pageclose fea - ure provids a midway between Open and Close page policies. FOR PERFORMANCE ONLY.*/ +/* +* If true, bank is kept open only while there are page hit transactions av + * ailable in the CAM to that bank. The last read or write command in the C + * AM with a bank and page hit will be executed with auto-precharge if SCHE + * D1.pageclose_timer=0. Even if this register set to 1 and SCHED1.pageclos + * e_timer is set to 0, explicit precharge (and not auto-precharge) may be + * issued in some cases where there is a mode switch between Write and Read + * or between LPR and HPR. The Read and Write commands that are executed a + * s part of the ECC scrub requests are also executed without auto-precharg + * e. If false, the bank remains open until there is a need to close it (to + * open a different page, or for page timeout or refresh timeout) - also k + * nown as open page policy. The open page policy can be overridden by sett + * ing the per-command-autopre bit on the HIF interface (hif_cmd_autopre). + * The pageclose feature provids a midway between Open and Close page polic + * ies. FOR PERFORMANCE ONLY. +*/ #undef DDRC_SCHED_PAGECLOSE_DEFVAL #undef DDRC_SCHED_PAGECLOSE_SHIFT #undef DDRC_SCHED_PAGECLOSE_MASK -#define DDRC_SCHED_PAGECLOSE_DEFVAL 0x00002005 -#define DDRC_SCHED_PAGECLOSE_SHIFT 2 -#define DDRC_SCHED_PAGECLOSE_MASK 0x00000004U +#define DDRC_SCHED_PAGECLOSE_DEFVAL 0x00002005 +#define DDRC_SCHED_PAGECLOSE_SHIFT 2 +#define DDRC_SCHED_PAGECLOSE_MASK 0x00000004U -/*If set then the bank selector prefers writes over reads. FOR DEBUG ONLY.*/ +/* +* If set then the bank selector prefers writes over reads. FOR DEBUG ONLY. +*/ #undef DDRC_SCHED_PREFER_WRITE_DEFVAL #undef DDRC_SCHED_PREFER_WRITE_SHIFT #undef DDRC_SCHED_PREFER_WRITE_MASK -#define DDRC_SCHED_PREFER_WRITE_DEFVAL 0x00002005 -#define DDRC_SCHED_PREFER_WRITE_SHIFT 1 -#define DDRC_SCHED_PREFER_WRITE_MASK 0x00000002U +#define DDRC_SCHED_PREFER_WRITE_DEFVAL 0x00002005 +#define DDRC_SCHED_PREFER_WRITE_SHIFT 1 +#define DDRC_SCHED_PREFER_WRITE_MASK 0x00000002U -/*Active low signal. When asserted ('0'), all incoming transactions are forced to low priority. This implies that all High Prio - ity Read (HPR) and Variable Priority Read commands (VPR) will be treated as Low Priority Read (LPR) commands. On the write si - e, all Variable Priority Write (VPW) commands will be treated as Normal Priority Write (NPW) commands. Forcing the incoming t - ansactions to low priority implicitly turns off Bypass path for read commands. FOR PERFORMANCE ONLY.*/ +/* +* Active low signal. When asserted ('0'), all incoming transactions are fo + * rced to low priority. This implies that all High Priority Read (HPR) and + * Variable Priority Read commands (VPR) will be treated as Low Priority R + * ead (LPR) commands. On the write side, all Variable Priority Write (VPW) + * commands will be treated as Normal Priority Write (NPW) commands. Forci + * ng the incoming transactions to low priority implicitly turns off Bypass + * path for read commands. FOR PERFORMANCE ONLY. +*/ #undef DDRC_SCHED_FORCE_LOW_PRI_N_DEFVAL #undef DDRC_SCHED_FORCE_LOW_PRI_N_SHIFT #undef DDRC_SCHED_FORCE_LOW_PRI_N_MASK -#define DDRC_SCHED_FORCE_LOW_PRI_N_DEFVAL 0x00002005 -#define DDRC_SCHED_FORCE_LOW_PRI_N_SHIFT 0 -#define DDRC_SCHED_FORCE_LOW_PRI_N_MASK 0x00000001U +#define DDRC_SCHED_FORCE_LOW_PRI_N_DEFVAL 0x00002005 +#define DDRC_SCHED_FORCE_LOW_PRI_N_SHIFT 0 +#define DDRC_SCHED_FORCE_LOW_PRI_N_MASK 0x00000001U -/*Number of transactions that are serviced once the LPR queue goes critical is the smaller of: - (a) This number - (b) Number o - transactions available. Unit: Transaction. FOR PERFORMANCE ONLY.*/ +/* +* Number of transactions that are serviced once the LPR queue goes critica + * l is the smaller of: - (a) This number - (b) Number of transactions avai + * lable. Unit: Transaction. FOR PERFORMANCE ONLY. +*/ #undef DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_DEFVAL #undef DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_SHIFT #undef DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_MASK -#define DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_DEFVAL 0x0F00007F -#define DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_SHIFT 24 -#define DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_MASK 0xFF000000U +#define DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_DEFVAL 0x0F00007F +#define DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_SHIFT 24 +#define DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_MASK 0xFF000000U -/*Number of clocks that the LPR queue can be starved before it goes critical. The minimum valid functional value for this regis - er is 0x1. Programming it to 0x0 will disable the starvation functionality; during normal operation, this function should not - be disabled as it will cause excessive latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY.*/ +/* +* Number of clocks that the LPR queue can be starved before it goes critic + * al. The minimum valid functional value for this register is 0x1. Program + * ming it to 0x0 will disable the starvation functionality; during normal + * operation, this function should not be disabled as it will cause excessi + * ve latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY. +*/ #undef DDRC_PERFLPR1_LPR_MAX_STARVE_DEFVAL #undef DDRC_PERFLPR1_LPR_MAX_STARVE_SHIFT #undef DDRC_PERFLPR1_LPR_MAX_STARVE_MASK -#define DDRC_PERFLPR1_LPR_MAX_STARVE_DEFVAL 0x0F00007F -#define DDRC_PERFLPR1_LPR_MAX_STARVE_SHIFT 0 -#define DDRC_PERFLPR1_LPR_MAX_STARVE_MASK 0x0000FFFFU +#define DDRC_PERFLPR1_LPR_MAX_STARVE_DEFVAL 0x0F00007F +#define DDRC_PERFLPR1_LPR_MAX_STARVE_SHIFT 0 +#define DDRC_PERFLPR1_LPR_MAX_STARVE_MASK 0x0000FFFFU -/*Number of transactions that are serviced once the WR queue goes critical is the smaller of: - (a) This number - (b) Number of - transactions available. Unit: Transaction. FOR PERFORMANCE ONLY.*/ +/* +* Number of transactions that are serviced once the WR queue goes critical + * is the smaller of: - (a) This number - (b) Number of transactions avail + * able. Unit: Transaction. FOR PERFORMANCE ONLY. +*/ #undef DDRC_PERFWR1_W_XACT_RUN_LENGTH_DEFVAL #undef DDRC_PERFWR1_W_XACT_RUN_LENGTH_SHIFT #undef DDRC_PERFWR1_W_XACT_RUN_LENGTH_MASK -#define DDRC_PERFWR1_W_XACT_RUN_LENGTH_DEFVAL 0x0F00007F -#define DDRC_PERFWR1_W_XACT_RUN_LENGTH_SHIFT 24 -#define DDRC_PERFWR1_W_XACT_RUN_LENGTH_MASK 0xFF000000U +#define DDRC_PERFWR1_W_XACT_RUN_LENGTH_DEFVAL 0x0F00007F +#define DDRC_PERFWR1_W_XACT_RUN_LENGTH_SHIFT 24 +#define DDRC_PERFWR1_W_XACT_RUN_LENGTH_MASK 0xFF000000U -/*Number of clocks that the WR queue can be starved before it goes critical. The minimum valid functional value for this regist - r is 0x1. Programming it to 0x0 will disable the starvation functionality; during normal operation, this function should not - e disabled as it will cause excessive latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY.*/ +/* +* Number of clocks that the WR queue can be starved before it goes critica + * l. The minimum valid functional value for this register is 0x1. Programm + * ing it to 0x0 will disable the starvation functionality; during normal o + * peration, this function should not be disabled as it will cause excessiv + * e latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY. +*/ #undef DDRC_PERFWR1_W_MAX_STARVE_DEFVAL #undef DDRC_PERFWR1_W_MAX_STARVE_SHIFT #undef DDRC_PERFWR1_W_MAX_STARVE_MASK -#define DDRC_PERFWR1_W_MAX_STARVE_DEFVAL 0x0F00007F -#define DDRC_PERFWR1_W_MAX_STARVE_SHIFT 0 -#define DDRC_PERFWR1_W_MAX_STARVE_MASK 0x0000FFFFU +#define DDRC_PERFWR1_W_MAX_STARVE_DEFVAL 0x0F00007F +#define DDRC_PERFWR1_W_MAX_STARVE_SHIFT 0 +#define DDRC_PERFWR1_W_MAX_STARVE_MASK 0x0000FFFFU -/*All even ranks have the same DQ mapping controled by DQMAP0-4 register as rank 0. This register provides DQ swap function for - all odd ranks to support CRC feature. rank based DQ swapping is: swap bit 0 with 1, swap bit 2 with 3, swap bit 4 with 5 and - wap bit 6 with 7. 1: Disable rank based DQ swapping 0: Enable rank based DQ swapping Present only in designs configured to su - port DDR4.*/ +/* +* DQ nibble map for DQ bits [12-15] Present only in designs configured to + * support DDR4. +*/ +#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_12_15_DEFVAL +#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_12_15_SHIFT +#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_12_15_MASK +#define DDRC_DQMAP0_DQ_NIBBLE_MAP_12_15_DEFVAL 0x00000000 +#define DDRC_DQMAP0_DQ_NIBBLE_MAP_12_15_SHIFT 24 +#define DDRC_DQMAP0_DQ_NIBBLE_MAP_12_15_MASK 0xFF000000U + +/* +* DQ nibble map for DQ bits [8-11] Present only in designs configured to s + * upport DDR4. +*/ +#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_8_11_DEFVAL +#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_8_11_SHIFT +#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_8_11_MASK +#define DDRC_DQMAP0_DQ_NIBBLE_MAP_8_11_DEFVAL 0x00000000 +#define DDRC_DQMAP0_DQ_NIBBLE_MAP_8_11_SHIFT 16 +#define DDRC_DQMAP0_DQ_NIBBLE_MAP_8_11_MASK 0x00FF0000U + +/* +* DQ nibble map for DQ bits [4-7] Present only in designs configured to su + * pport DDR4. +*/ +#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_4_7_DEFVAL +#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_4_7_SHIFT +#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_4_7_MASK +#define DDRC_DQMAP0_DQ_NIBBLE_MAP_4_7_DEFVAL 0x00000000 +#define DDRC_DQMAP0_DQ_NIBBLE_MAP_4_7_SHIFT 8 +#define DDRC_DQMAP0_DQ_NIBBLE_MAP_4_7_MASK 0x0000FF00U + +/* +* DQ nibble map for DQ bits [0-3] Present only in designs configured to su + * pport DDR4. +*/ +#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_0_3_DEFVAL +#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_0_3_SHIFT +#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_0_3_MASK +#define DDRC_DQMAP0_DQ_NIBBLE_MAP_0_3_DEFVAL 0x00000000 +#define DDRC_DQMAP0_DQ_NIBBLE_MAP_0_3_SHIFT 0 +#define DDRC_DQMAP0_DQ_NIBBLE_MAP_0_3_MASK 0x000000FFU + +/* +* DQ nibble map for DQ bits [28-31] Present only in designs configured to + * support DDR4. +*/ +#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_28_31_DEFVAL +#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_28_31_SHIFT +#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_28_31_MASK +#define DDRC_DQMAP1_DQ_NIBBLE_MAP_28_31_DEFVAL 0x00000000 +#define DDRC_DQMAP1_DQ_NIBBLE_MAP_28_31_SHIFT 24 +#define DDRC_DQMAP1_DQ_NIBBLE_MAP_28_31_MASK 0xFF000000U + +/* +* DQ nibble map for DQ bits [24-27] Present only in designs configured to + * support DDR4. +*/ +#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_24_27_DEFVAL +#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_24_27_SHIFT +#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_24_27_MASK +#define DDRC_DQMAP1_DQ_NIBBLE_MAP_24_27_DEFVAL 0x00000000 +#define DDRC_DQMAP1_DQ_NIBBLE_MAP_24_27_SHIFT 16 +#define DDRC_DQMAP1_DQ_NIBBLE_MAP_24_27_MASK 0x00FF0000U + +/* +* DQ nibble map for DQ bits [20-23] Present only in designs configured to + * support DDR4. +*/ +#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_20_23_DEFVAL +#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_20_23_SHIFT +#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_20_23_MASK +#define DDRC_DQMAP1_DQ_NIBBLE_MAP_20_23_DEFVAL 0x00000000 +#define DDRC_DQMAP1_DQ_NIBBLE_MAP_20_23_SHIFT 8 +#define DDRC_DQMAP1_DQ_NIBBLE_MAP_20_23_MASK 0x0000FF00U + +/* +* DQ nibble map for DQ bits [16-19] Present only in designs configured to + * support DDR4. +*/ +#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_16_19_DEFVAL +#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_16_19_SHIFT +#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_16_19_MASK +#define DDRC_DQMAP1_DQ_NIBBLE_MAP_16_19_DEFVAL 0x00000000 +#define DDRC_DQMAP1_DQ_NIBBLE_MAP_16_19_SHIFT 0 +#define DDRC_DQMAP1_DQ_NIBBLE_MAP_16_19_MASK 0x000000FFU + +/* +* DQ nibble map for DQ bits [44-47] Present only in designs configured to + * support DDR4. +*/ +#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_44_47_DEFVAL +#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_44_47_SHIFT +#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_44_47_MASK +#define DDRC_DQMAP2_DQ_NIBBLE_MAP_44_47_DEFVAL 0x00000000 +#define DDRC_DQMAP2_DQ_NIBBLE_MAP_44_47_SHIFT 24 +#define DDRC_DQMAP2_DQ_NIBBLE_MAP_44_47_MASK 0xFF000000U + +/* +* DQ nibble map for DQ bits [40-43] Present only in designs configured to + * support DDR4. +*/ +#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_40_43_DEFVAL +#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_40_43_SHIFT +#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_40_43_MASK +#define DDRC_DQMAP2_DQ_NIBBLE_MAP_40_43_DEFVAL 0x00000000 +#define DDRC_DQMAP2_DQ_NIBBLE_MAP_40_43_SHIFT 16 +#define DDRC_DQMAP2_DQ_NIBBLE_MAP_40_43_MASK 0x00FF0000U + +/* +* DQ nibble map for DQ bits [36-39] Present only in designs configured to + * support DDR4. +*/ +#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_36_39_DEFVAL +#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_36_39_SHIFT +#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_36_39_MASK +#define DDRC_DQMAP2_DQ_NIBBLE_MAP_36_39_DEFVAL 0x00000000 +#define DDRC_DQMAP2_DQ_NIBBLE_MAP_36_39_SHIFT 8 +#define DDRC_DQMAP2_DQ_NIBBLE_MAP_36_39_MASK 0x0000FF00U + +/* +* DQ nibble map for DQ bits [32-35] Present only in designs configured to + * support DDR4. +*/ +#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_32_35_DEFVAL +#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_32_35_SHIFT +#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_32_35_MASK +#define DDRC_DQMAP2_DQ_NIBBLE_MAP_32_35_DEFVAL 0x00000000 +#define DDRC_DQMAP2_DQ_NIBBLE_MAP_32_35_SHIFT 0 +#define DDRC_DQMAP2_DQ_NIBBLE_MAP_32_35_MASK 0x000000FFU + +/* +* DQ nibble map for DQ bits [60-63] Present only in designs configured to + * support DDR4. +*/ +#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_60_63_DEFVAL +#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_60_63_SHIFT +#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_60_63_MASK +#define DDRC_DQMAP3_DQ_NIBBLE_MAP_60_63_DEFVAL 0x00000000 +#define DDRC_DQMAP3_DQ_NIBBLE_MAP_60_63_SHIFT 24 +#define DDRC_DQMAP3_DQ_NIBBLE_MAP_60_63_MASK 0xFF000000U + +/* +* DQ nibble map for DQ bits [56-59] Present only in designs configured to + * support DDR4. +*/ +#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_56_59_DEFVAL +#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_56_59_SHIFT +#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_56_59_MASK +#define DDRC_DQMAP3_DQ_NIBBLE_MAP_56_59_DEFVAL 0x00000000 +#define DDRC_DQMAP3_DQ_NIBBLE_MAP_56_59_SHIFT 16 +#define DDRC_DQMAP3_DQ_NIBBLE_MAP_56_59_MASK 0x00FF0000U + +/* +* DQ nibble map for DQ bits [52-55] Present only in designs configured to + * support DDR4. +*/ +#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_52_55_DEFVAL +#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_52_55_SHIFT +#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_52_55_MASK +#define DDRC_DQMAP3_DQ_NIBBLE_MAP_52_55_DEFVAL 0x00000000 +#define DDRC_DQMAP3_DQ_NIBBLE_MAP_52_55_SHIFT 8 +#define DDRC_DQMAP3_DQ_NIBBLE_MAP_52_55_MASK 0x0000FF00U + +/* +* DQ nibble map for DQ bits [48-51] Present only in designs configured to + * support DDR4. +*/ +#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_48_51_DEFVAL +#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_48_51_SHIFT +#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_48_51_MASK +#define DDRC_DQMAP3_DQ_NIBBLE_MAP_48_51_DEFVAL 0x00000000 +#define DDRC_DQMAP3_DQ_NIBBLE_MAP_48_51_SHIFT 0 +#define DDRC_DQMAP3_DQ_NIBBLE_MAP_48_51_MASK 0x000000FFU + +/* +* DQ nibble map for DIMM ECC check bits [4-7] Present only in designs conf + * igured to support DDR4. +*/ +#undef DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_4_7_DEFVAL +#undef DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_4_7_SHIFT +#undef DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_4_7_MASK +#define DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_4_7_DEFVAL 0x00000000 +#define DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_4_7_SHIFT 8 +#define DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_4_7_MASK 0x0000FF00U + +/* +* DQ nibble map for DIMM ECC check bits [0-3] Present only in designs conf + * igured to support DDR4. +*/ +#undef DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_0_3_DEFVAL +#undef DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_0_3_SHIFT +#undef DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_0_3_MASK +#define DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_0_3_DEFVAL 0x00000000 +#define DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_0_3_SHIFT 0 +#define DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_0_3_MASK 0x000000FFU + +/* +* All even ranks have the same DQ mapping controled by DQMAP0-4 register a + * s rank 0. This register provides DQ swap function for all odd ranks to s + * upport CRC feature. rank based DQ swapping is: swap bit 0 with 1, swap b + * it 2 with 3, swap bit 4 with 5 and swap bit 6 with 7. 1: Disable rank ba + * sed DQ swapping 0: Enable rank based DQ swapping Present only in designs + * configured to support DDR4. +*/ #undef DDRC_DQMAP5_DIS_DQ_RANK_SWAP_DEFVAL #undef DDRC_DQMAP5_DIS_DQ_RANK_SWAP_SHIFT #undef DDRC_DQMAP5_DIS_DQ_RANK_SWAP_MASK -#define DDRC_DQMAP5_DIS_DQ_RANK_SWAP_DEFVAL -#define DDRC_DQMAP5_DIS_DQ_RANK_SWAP_SHIFT 0 -#define DDRC_DQMAP5_DIS_DQ_RANK_SWAP_MASK 0x00000001U +#define DDRC_DQMAP5_DIS_DQ_RANK_SWAP_DEFVAL +#define DDRC_DQMAP5_DIS_DQ_RANK_SWAP_SHIFT 0 +#define DDRC_DQMAP5_DIS_DQ_RANK_SWAP_MASK 0x00000001U -/*When this is set to '0', auto-precharge is disabled for the flushed command in a collision case. Collision cases are write fo - lowed by read to same address, read followed by write to same address, or write followed by write to same address with DBG0.d - s_wc bit = 1 (where same address comparisons exclude the two address bits representing critical word). FOR DEBUG ONLY.*/ +/* +* When this is set to '0', auto-precharge is disabled for the flushed comm + * and in a collision case. Collision cases are write followed by read to s + * ame address, read followed by write to same address, or write followed b + * y write to same address with DBG0.dis_wc bit = 1 (where same address com + * parisons exclude the two address bits representing critical word). FOR D + * EBUG ONLY. +*/ #undef DDRC_DBG0_DIS_COLLISION_PAGE_OPT_DEFVAL #undef DDRC_DBG0_DIS_COLLISION_PAGE_OPT_SHIFT #undef DDRC_DBG0_DIS_COLLISION_PAGE_OPT_MASK -#define DDRC_DBG0_DIS_COLLISION_PAGE_OPT_DEFVAL 0x00000000 -#define DDRC_DBG0_DIS_COLLISION_PAGE_OPT_SHIFT 4 -#define DDRC_DBG0_DIS_COLLISION_PAGE_OPT_MASK 0x00000010U +#define DDRC_DBG0_DIS_COLLISION_PAGE_OPT_DEFVAL 0x00000000 +#define DDRC_DBG0_DIS_COLLISION_PAGE_OPT_SHIFT 4 +#define DDRC_DBG0_DIS_COLLISION_PAGE_OPT_MASK 0x00000010U -/*When 1, disable write combine. FOR DEBUG ONLY*/ +/* +* When 1, disable write combine. FOR DEBUG ONLY +*/ #undef DDRC_DBG0_DIS_WC_DEFVAL #undef DDRC_DBG0_DIS_WC_SHIFT #undef DDRC_DBG0_DIS_WC_MASK -#define DDRC_DBG0_DIS_WC_DEFVAL 0x00000000 -#define DDRC_DBG0_DIS_WC_SHIFT 0 -#define DDRC_DBG0_DIS_WC_MASK 0x00000001U +#define DDRC_DBG0_DIS_WC_DEFVAL 0x00000000 +#define DDRC_DBG0_DIS_WC_SHIFT 0 +#define DDRC_DBG0_DIS_WC_MASK 0x00000001U -/*Setting this register bit to 1 allows refresh and ZQCS commands to be triggered from hardware via the IOs ext_*. If set to 1, - the fields DBGCMD.zq_calib_short and DBGCMD.rank*_refresh have no function, and are ignored by the uMCTL2 logic. Setting this - register bit to 0 allows refresh and ZQCS to be triggered from software, via the fields DBGCMD.zq_calib_short and DBGCMD.rank - _refresh. If set to 0, the hardware pins ext_* have no function, and are ignored by the uMCTL2 logic. This register is static - and may only be changed when the DDRC reset signal, core_ddrc_rstn, is asserted (0).*/ +/* +* Setting this register bit to 1 allows refresh and ZQCS commands to be tr + * iggered from hardware via the IOs ext_*. If set to 1, the fields DBGCMD. + * zq_calib_short and DBGCMD.rank*_refresh have no function, and are ignore + * d by the uMCTL2 logic. Setting this register bit to 0 allows refresh and + * ZQCS to be triggered from software, via the fields DBGCMD.zq_calib_shor + * t and DBGCMD.rank*_refresh. If set to 0, the hardware pins ext_* have no + * function, and are ignored by the uMCTL2 logic. This register is static, + * and may only be changed when the DDRC reset signal, core_ddrc_rstn, is + * asserted (0). +*/ #undef DDRC_DBGCMD_HW_REF_ZQ_EN_DEFVAL #undef DDRC_DBGCMD_HW_REF_ZQ_EN_SHIFT #undef DDRC_DBGCMD_HW_REF_ZQ_EN_MASK -#define DDRC_DBGCMD_HW_REF_ZQ_EN_DEFVAL 0x00000000 -#define DDRC_DBGCMD_HW_REF_ZQ_EN_SHIFT 31 -#define DDRC_DBGCMD_HW_REF_ZQ_EN_MASK 0x80000000U +#define DDRC_DBGCMD_HW_REF_ZQ_EN_DEFVAL 0x00000000 +#define DDRC_DBGCMD_HW_REF_ZQ_EN_SHIFT 31 +#define DDRC_DBGCMD_HW_REF_ZQ_EN_MASK 0x80000000U -/*Setting this register bit to 1 indicates to the uMCTL2 to issue a dfi_ctrlupd_req to the PHY. When this request is stored in - he uMCTL2, the bit is automatically cleared. This operation must only be performed when DFIUPD0.dis_auto_ctrlupd=1.*/ +/* +* Setting this register bit to 1 indicates to the uMCTL2 to issue a dfi_ct + * rlupd_req to the PHY. When this request is stored in the uMCTL2, the bit + * is automatically cleared. This operation must only be performed when DF + * IUPD0.dis_auto_ctrlupd=1. +*/ #undef DDRC_DBGCMD_CTRLUPD_DEFVAL #undef DDRC_DBGCMD_CTRLUPD_SHIFT #undef DDRC_DBGCMD_CTRLUPD_MASK -#define DDRC_DBGCMD_CTRLUPD_DEFVAL 0x00000000 -#define DDRC_DBGCMD_CTRLUPD_SHIFT 5 -#define DDRC_DBGCMD_CTRLUPD_MASK 0x00000020U +#define DDRC_DBGCMD_CTRLUPD_DEFVAL 0x00000000 +#define DDRC_DBGCMD_CTRLUPD_SHIFT 5 +#define DDRC_DBGCMD_CTRLUPD_MASK 0x00000020U -/*Setting this register bit to 1 indicates to the uMCTL2 to issue a ZQCS (ZQ calibration short)/MPC(ZQ calibration) command to - he SDRAM. When this request is stored in the uMCTL2, the bit is automatically cleared. This operation can be performed only w - en ZQCTL0.dis_auto_zq=1. It is recommended NOT to set this register bit if in Init operating mode. This register bit is ignor - d when in Self-Refresh(except LPDDR4) and SR-Powerdown(LPDDR4) and Deep power-down operating modes and Maximum Power Saving M - de.*/ +/* +* Setting this register bit to 1 indicates to the uMCTL2 to issue a ZQCS ( + * ZQ calibration short)/MPC(ZQ calibration) command to the SDRAM. When thi + * s request is stored in the uMCTL2, the bit is automatically cleared. Thi + * s operation can be performed only when ZQCTL0.dis_auto_zq=1. It is recom + * mended NOT to set this register bit if in Init operating mode. This regi + * ster bit is ignored when in Self-Refresh(except LPDDR4) and SR-Powerdown + * (LPDDR4) and Deep power-down operating modes and Maximum Power Saving Mo + * de. +*/ #undef DDRC_DBGCMD_ZQ_CALIB_SHORT_DEFVAL #undef DDRC_DBGCMD_ZQ_CALIB_SHORT_SHIFT #undef DDRC_DBGCMD_ZQ_CALIB_SHORT_MASK -#define DDRC_DBGCMD_ZQ_CALIB_SHORT_DEFVAL 0x00000000 -#define DDRC_DBGCMD_ZQ_CALIB_SHORT_SHIFT 4 -#define DDRC_DBGCMD_ZQ_CALIB_SHORT_MASK 0x00000010U +#define DDRC_DBGCMD_ZQ_CALIB_SHORT_DEFVAL 0x00000000 +#define DDRC_DBGCMD_ZQ_CALIB_SHORT_SHIFT 4 +#define DDRC_DBGCMD_ZQ_CALIB_SHORT_MASK 0x00000010U -/*Setting this register bit to 1 indicates to the uMCTL2 to issue a refresh to rank 1. Writing to this bit causes DBGSTAT.rank1 - refresh_busy to be set. When DBGSTAT.rank1_refresh_busy is cleared, the command has been stored in uMCTL2. This operation can - be performed only when RFSHCTL3.dis_auto_refresh=1. It is recommended NOT to set this register bit if in Init or Deep power-d - wn operating modes or Maximum Power Saving Mode.*/ +/* +* Setting this register bit to 1 indicates to the uMCTL2 to issue a refres + * h to rank 1. Writing to this bit causes DBGSTAT.rank1_refresh_busy to be + * set. When DBGSTAT.rank1_refresh_busy is cleared, the command has been s + * tored in uMCTL2. This operation can be performed only when RFSHCTL3.dis_ + * auto_refresh=1. It is recommended NOT to set this register bit if in Ini + * t or Deep power-down operating modes or Maximum Power Saving Mode. +*/ #undef DDRC_DBGCMD_RANK1_REFRESH_DEFVAL #undef DDRC_DBGCMD_RANK1_REFRESH_SHIFT #undef DDRC_DBGCMD_RANK1_REFRESH_MASK -#define DDRC_DBGCMD_RANK1_REFRESH_DEFVAL 0x00000000 -#define DDRC_DBGCMD_RANK1_REFRESH_SHIFT 1 -#define DDRC_DBGCMD_RANK1_REFRESH_MASK 0x00000002U +#define DDRC_DBGCMD_RANK1_REFRESH_DEFVAL 0x00000000 +#define DDRC_DBGCMD_RANK1_REFRESH_SHIFT 1 +#define DDRC_DBGCMD_RANK1_REFRESH_MASK 0x00000002U -/*Setting this register bit to 1 indicates to the uMCTL2 to issue a refresh to rank 0. Writing to this bit causes DBGSTAT.rank0 - refresh_busy to be set. When DBGSTAT.rank0_refresh_busy is cleared, the command has been stored in uMCTL2. This operation can - be performed only when RFSHCTL3.dis_auto_refresh=1. It is recommended NOT to set this register bit if in Init or Deep power-d - wn operating modes or Maximum Power Saving Mode.*/ +/* +* Setting this register bit to 1 indicates to the uMCTL2 to issue a refres + * h to rank 0. Writing to this bit causes DBGSTAT.rank0_refresh_busy to be + * set. When DBGSTAT.rank0_refresh_busy is cleared, the command has been s + * tored in uMCTL2. This operation can be performed only when RFSHCTL3.dis_ + * auto_refresh=1. It is recommended NOT to set this register bit if in Ini + * t or Deep power-down operating modes or Maximum Power Saving Mode. +*/ #undef DDRC_DBGCMD_RANK0_REFRESH_DEFVAL #undef DDRC_DBGCMD_RANK0_REFRESH_SHIFT #undef DDRC_DBGCMD_RANK0_REFRESH_MASK -#define DDRC_DBGCMD_RANK0_REFRESH_DEFVAL 0x00000000 -#define DDRC_DBGCMD_RANK0_REFRESH_SHIFT 0 -#define DDRC_DBGCMD_RANK0_REFRESH_MASK 0x00000001U +#define DDRC_DBGCMD_RANK0_REFRESH_DEFVAL 0x00000000 +#define DDRC_DBGCMD_RANK0_REFRESH_SHIFT 0 +#define DDRC_DBGCMD_RANK0_REFRESH_MASK 0x00000001U -/*Enable quasi-dynamic register programming outside reset. Program register to 0 to enable quasi-dynamic programming. Set back - egister to 1 once programming is done.*/ +/* +* Enable quasi-dynamic register programming outside reset. Program registe + * r to 0 to enable quasi-dynamic programming. Set back register to 1 once + * programming is done. +*/ #undef DDRC_SWCTL_SW_DONE_DEFVAL #undef DDRC_SWCTL_SW_DONE_SHIFT #undef DDRC_SWCTL_SW_DONE_MASK -#define DDRC_SWCTL_SW_DONE_DEFVAL -#define DDRC_SWCTL_SW_DONE_SHIFT 0 -#define DDRC_SWCTL_SW_DONE_MASK 0x00000001U +#define DDRC_SWCTL_SW_DONE_DEFVAL +#define DDRC_SWCTL_SW_DONE_SHIFT 0 +#define DDRC_SWCTL_SW_DONE_MASK 0x00000001U -/*Burst length expansion mode. By default (i.e. bl_exp_mode==0) XPI expands every AXI burst into multiple HIF commands, using t - e memory burst length as a unit. If set to 1, then XPI will use half of the memory burst length as a unit. This applies to bo - h reads and writes. When MSTR.data_bus_width==00, setting bl_exp_mode to 1 has no effect. This can be used in cases where Par - ial Writes is enabled (UMCTL2_PARTIAL_WR=1) and DBG0.dis_wc=1, in order to avoid or minimize t_ccd_l penalty in DDR4 and t_cc - _mw penalty in LPDDR4. Note that if DBICTL.reg_ddrc_dm_en=0, functionality is not supported in the following cases: - UMCTL2_ - ARTIAL_WR=0 - UMCTL2_PARTIAL_WR=1, MSTR.reg_ddrc_data_bus_width=01, MEMC_BURST_LENGTH=8 and MSTR.reg_ddrc_burst_rdwr=1000 (LP - DR4 only) - UMCTL2_PARTIAL_WR=1, MSTR.reg_ddrc_data_bus_width=01, MEMC_BURST_LENGTH=4 and MSTR.reg_ddrc_burst_rdwr=0100 (DDR4 - only), with either MSTR.reg_ddrc_burstchop=0 or CRCPARCTL1.reg_ddrc_crc_enable=1 Functionality is also not supported if Share - -AC is enabled*/ +/* +* Burst length expansion mode. By default (i.e. bl_exp_mode==0) XPI expand + * s every AXI burst into multiple HIF commands, using the memory burst len + * gth as a unit. If set to 1, then XPI will use half of the memory burst l + * ength as a unit. This applies to both reads and writes. When MSTR.data_b + * us_width==00, setting bl_exp_mode to 1 has no effect. This can be used i + * n cases where Partial Writes is enabled (UMCTL2_PARTIAL_WR=1) and DBG0.d + * is_wc=1, in order to avoid or minimize t_ccd_l penalty in DDR4 and t_ccd + * _mw penalty in LPDDR4. Note that if DBICTL.reg_ddrc_dm_en=0, functionali + * ty is not supported in the following cases: - UMCTL2_PARTIAL_WR=0 - UMCT + * L2_PARTIAL_WR=1, MSTR.reg_ddrc_data_bus_width=01, MEMC_BURST_LENGTH=8 an + * d MSTR.reg_ddrc_burst_rdwr=1000 (LPDDR4 only) - UMCTL2_PARTIAL_WR=1, MST + * R.reg_ddrc_data_bus_width=01, MEMC_BURST_LENGTH=4 and MSTR.reg_ddrc_burs + * t_rdwr=0100 (DDR4 only), with either MSTR.reg_ddrc_burstchop=0 or CRCPAR + * CTL1.reg_ddrc_crc_enable=1 Functionality is also not supported if Shared + * -AC is enabled +*/ #undef DDRC_PCCFG_BL_EXP_MODE_DEFVAL #undef DDRC_PCCFG_BL_EXP_MODE_SHIFT #undef DDRC_PCCFG_BL_EXP_MODE_MASK -#define DDRC_PCCFG_BL_EXP_MODE_DEFVAL 0x00000000 -#define DDRC_PCCFG_BL_EXP_MODE_SHIFT 8 -#define DDRC_PCCFG_BL_EXP_MODE_MASK 0x00000100U +#define DDRC_PCCFG_BL_EXP_MODE_DEFVAL 0x00000000 +#define DDRC_PCCFG_BL_EXP_MODE_SHIFT 8 +#define DDRC_PCCFG_BL_EXP_MODE_MASK 0x00000100U -/*Page match four limit. If set to 1, limits the number of consecutive same page DDRC transactions that can be granted by the P - rt Arbiter to four when Page Match feature is enabled. If set to 0, there is no limit imposed on number of consecutive same p - ge DDRC transactions.*/ +/* +* Page match four limit. If set to 1, limits the number of consecutive sam + * e page DDRC transactions that can be granted by the Port Arbiter to four + * when Page Match feature is enabled. If set to 0, there is no limit impo + * sed on number of consecutive same page DDRC transactions. +*/ #undef DDRC_PCCFG_PAGEMATCH_LIMIT_DEFVAL #undef DDRC_PCCFG_PAGEMATCH_LIMIT_SHIFT #undef DDRC_PCCFG_PAGEMATCH_LIMIT_MASK -#define DDRC_PCCFG_PAGEMATCH_LIMIT_DEFVAL 0x00000000 -#define DDRC_PCCFG_PAGEMATCH_LIMIT_SHIFT 4 -#define DDRC_PCCFG_PAGEMATCH_LIMIT_MASK 0x00000010U +#define DDRC_PCCFG_PAGEMATCH_LIMIT_DEFVAL 0x00000000 +#define DDRC_PCCFG_PAGEMATCH_LIMIT_SHIFT 4 +#define DDRC_PCCFG_PAGEMATCH_LIMIT_MASK 0x00000010U -/*If set to 1 (enabled), sets co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals going to DDRC based - n urgent input (awurgent, arurgent) coming from AXI master. If set to 0 (disabled), co_gs_go2critical_wr and co_gs_go2critica - _lpr/co_gs_go2critical_hpr signals at DDRC are driven to 1b'0.*/ +/* +* If set to 1 (enabled), sets co_gs_go2critical_wr and co_gs_go2critical_l + * pr/co_gs_go2critical_hpr signals going to DDRC based on urgent input (aw + * urgent, arurgent) coming from AXI master. If set to 0 (disabled), co_gs_ + * go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals a + * t DDRC are driven to 1b'0. +*/ #undef DDRC_PCCFG_GO2CRITICAL_EN_DEFVAL #undef DDRC_PCCFG_GO2CRITICAL_EN_SHIFT #undef DDRC_PCCFG_GO2CRITICAL_EN_MASK -#define DDRC_PCCFG_GO2CRITICAL_EN_DEFVAL 0x00000000 -#define DDRC_PCCFG_GO2CRITICAL_EN_SHIFT 0 -#define DDRC_PCCFG_GO2CRITICAL_EN_MASK 0x00000001U +#define DDRC_PCCFG_GO2CRITICAL_EN_DEFVAL 0x00000000 +#define DDRC_PCCFG_GO2CRITICAL_EN_SHIFT 0 +#define DDRC_PCCFG_GO2CRITICAL_EN_MASK 0x00000001U -/*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register.*/ +/* +* If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. +*/ #undef DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_DEFVAL #undef DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_SHIFT #undef DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_MASK -#define DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_DEFVAL 0x00000000 -#define DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_SHIFT 14 -#define DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_MASK 0x00004000U +#define DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_SHIFT 14 +#define DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_MASK 0x00004000U -/*If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG. - o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add - ess handshaking (it is not associated with any particular command).*/ +/* +* If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + * bled and arurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + * urgent signal can be asserted anytime and as long as required which is i + * ndependent of address handshaking (it is not associated with any particu + * lar command). +*/ #undef DDRC_PCFGR_0_RD_PORT_URGENT_EN_DEFVAL #undef DDRC_PCFGR_0_RD_PORT_URGENT_EN_SHIFT #undef DDRC_PCFGR_0_RD_PORT_URGENT_EN_MASK -#define DDRC_PCFGR_0_RD_PORT_URGENT_EN_DEFVAL 0x00000000 -#define DDRC_PCFGR_0_RD_PORT_URGENT_EN_SHIFT 13 -#define DDRC_PCFGR_0_RD_PORT_URGENT_EN_MASK 0x00002000U +#define DDRC_PCFGR_0_RD_PORT_URGENT_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_0_RD_PORT_URGENT_EN_SHIFT 13 +#define DDRC_PCFGR_0_RD_PORT_URGENT_EN_MASK 0x00002000U -/*If set to 1, enables aging function for the read channel of the port.*/ +/* +* If set to 1, enables aging function for the read channel of the port. +*/ #undef DDRC_PCFGR_0_RD_PORT_AGING_EN_DEFVAL #undef DDRC_PCFGR_0_RD_PORT_AGING_EN_SHIFT #undef DDRC_PCFGR_0_RD_PORT_AGING_EN_MASK -#define DDRC_PCFGR_0_RD_PORT_AGING_EN_DEFVAL 0x00000000 -#define DDRC_PCFGR_0_RD_PORT_AGING_EN_SHIFT 12 -#define DDRC_PCFGR_0_RD_PORT_AGING_EN_MASK 0x00001000U +#define DDRC_PCFGR_0_RD_PORT_AGING_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_0_RD_PORT_AGING_EN_SHIFT 12 +#define DDRC_PCFGR_0_RD_PORT_AGING_EN_MASK 0x00001000U -/*Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g - ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority - will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre - ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the - aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st - ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w - ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D - RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: - he two LSBs of this register field are tied internally to 2'b00.*/ +/* +* Determines the initial load value of read aging counters. These counters + * will be parallel loaded after reset, or after each grant to the corresp + * onding port. The aging counters down-count every clock cycle where the p + * ort is requesting but not granted. The higher significant 5-bits of the + * read aging counter sets the priority of the read channel of a given port + * . Port's priority will increase as the higher significant 5-bits of the + * counter starts to decrease. When the aging counter becomes 0, the corres + * ponding port channel will have the highest priority level (timeout condi + * tion - Priority0). For multi-port configurations, the aging counters can + * not be used to set port priorities when external dynamic priority inputs + * (arqos) are enabled (timeout is still applicable). For single port conf + * igurations, the aging counters are only used when they timeout (become 0 + * ) to force read-write direction switching. In this case, external dynami + * c priority input, arqos (for reads only) can still be used to set the DD + * RC read priority (2 priority levels: low priority read - LPR, high prior + * ity read - HPR) on a command by command basis. Note: The two LSBs of thi + * s register field are tied internally to 2'b00. +*/ #undef DDRC_PCFGR_0_RD_PORT_PRIORITY_DEFVAL #undef DDRC_PCFGR_0_RD_PORT_PRIORITY_SHIFT #undef DDRC_PCFGR_0_RD_PORT_PRIORITY_MASK -#define DDRC_PCFGR_0_RD_PORT_PRIORITY_DEFVAL 0x00000000 -#define DDRC_PCFGR_0_RD_PORT_PRIORITY_SHIFT 0 -#define DDRC_PCFGR_0_RD_PORT_PRIORITY_MASK 0x000003FFU +#define DDRC_PCFGR_0_RD_PORT_PRIORITY_DEFVAL 0x00000000 +#define DDRC_PCFGR_0_RD_PORT_PRIORITY_SHIFT 0 +#define DDRC_PCFGR_0_RD_PORT_PRIORITY_MASK 0x000003FFU -/*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register.*/ +/* +* If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. +*/ #undef DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_DEFVAL #undef DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_SHIFT #undef DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_MASK -#define DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_DEFVAL 0x00004000 -#define DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_SHIFT 14 -#define DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_MASK 0x00004000U +#define DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_SHIFT 14 +#define DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_MASK 0x00004000U -/*If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register - Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is - not associated with any particular command).*/ +/* +* If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + * bled and awurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + * serted anytime and as long as required which is independent of address h + * andshaking (it is not associated with any particular command). +*/ #undef DDRC_PCFGW_0_WR_PORT_URGENT_EN_DEFVAL #undef DDRC_PCFGW_0_WR_PORT_URGENT_EN_SHIFT #undef DDRC_PCFGW_0_WR_PORT_URGENT_EN_MASK -#define DDRC_PCFGW_0_WR_PORT_URGENT_EN_DEFVAL 0x00004000 -#define DDRC_PCFGW_0_WR_PORT_URGENT_EN_SHIFT 13 -#define DDRC_PCFGW_0_WR_PORT_URGENT_EN_MASK 0x00002000U +#define DDRC_PCFGW_0_WR_PORT_URGENT_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_0_WR_PORT_URGENT_EN_SHIFT 13 +#define DDRC_PCFGW_0_WR_PORT_URGENT_EN_MASK 0x00002000U -/*If set to 1, enables aging function for the write channel of the port.*/ +/* +* If set to 1, enables aging function for the write channel of the port. +*/ #undef DDRC_PCFGW_0_WR_PORT_AGING_EN_DEFVAL #undef DDRC_PCFGW_0_WR_PORT_AGING_EN_SHIFT #undef DDRC_PCFGW_0_WR_PORT_AGING_EN_MASK -#define DDRC_PCFGW_0_WR_PORT_AGING_EN_DEFVAL 0x00004000 -#define DDRC_PCFGW_0_WR_PORT_AGING_EN_SHIFT 12 -#define DDRC_PCFGW_0_WR_PORT_AGING_EN_MASK 0x00001000U +#define DDRC_PCFGW_0_WR_PORT_AGING_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_0_WR_PORT_AGING_EN_SHIFT 12 +#define DDRC_PCFGW_0_WR_PORT_AGING_EN_MASK 0x00001000U -/*Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each - rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port - s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0 - the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno - be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For - ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch - ng. Note: The two LSBs of this register field are tied internally to 2'b00.*/ +/* +* Determines the initial load value of write aging counters. These counter + * s will be parallel loaded after reset, or after each grant to the corres + * ponding port. The aging counters down-count every clock cycle where the + * port is requesting but not granted. The higher significant 5-bits of the + * write aging counter sets the initial priority of the write channel of a + * given port. Port's priority will increase as the higher significant 5-b + * its of the counter starts to decrease. When the aging counter becomes 0, + * the corresponding port channel will have the highest priority level. Fo + * r multi-port configurations, the aging counters cannot be used to set po + * rt priorities when external dynamic priority inputs (awqos) are enabled + * (timeout is still applicable). For single port configurations, the aging + * counters are only used when they timeout (become 0) to force read-write + * direction switching. Note: The two LSBs of this register field are tied + * internally to 2'b00. +*/ #undef DDRC_PCFGW_0_WR_PORT_PRIORITY_DEFVAL #undef DDRC_PCFGW_0_WR_PORT_PRIORITY_SHIFT #undef DDRC_PCFGW_0_WR_PORT_PRIORITY_MASK -#define DDRC_PCFGW_0_WR_PORT_PRIORITY_DEFVAL 0x00004000 -#define DDRC_PCFGW_0_WR_PORT_PRIORITY_SHIFT 0 -#define DDRC_PCFGW_0_WR_PORT_PRIORITY_MASK 0x000003FFU +#define DDRC_PCFGW_0_WR_PORT_PRIORITY_DEFVAL 0x00004000 +#define DDRC_PCFGW_0_WR_PORT_PRIORITY_SHIFT 0 +#define DDRC_PCFGW_0_WR_PORT_PRIORITY_MASK 0x000003FFU -/*Enables port n.*/ +/* +* Enables port n. +*/ #undef DDRC_PCTRL_0_PORT_EN_DEFVAL #undef DDRC_PCTRL_0_PORT_EN_SHIFT #undef DDRC_PCTRL_0_PORT_EN_MASK -#define DDRC_PCTRL_0_PORT_EN_DEFVAL -#define DDRC_PCTRL_0_PORT_EN_SHIFT 0 -#define DDRC_PCTRL_0_PORT_EN_MASK 0x00000001U +#define DDRC_PCTRL_0_PORT_EN_DEFVAL +#define DDRC_PCTRL_0_PORT_EN_SHIFT 0 +#define DDRC_PCTRL_0_PORT_EN_MASK 0x00000001U -/*This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf - gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is - disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/ +/* +* This bitfield indicates the traffic class of region 1. Valid values are: + * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + * maps to the blue address queue. In this case, valid values are 0: LPR a + * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. +*/ #undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_DEFVAL #undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_SHIFT #undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_MASK -#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_DEFVAL 0x00000000 -#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_SHIFT 20 -#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_MASK 0x00300000U +#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_DEFVAL 0x00000000 +#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_SHIFT 20 +#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_MASK 0x00300000U -/*This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi - urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i - disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/ +/* +* This bitfield indicates the traffic class of region 0. Valid values are: + * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + * maps to the blue address queue. In this case, valid values are: 0: LPR + * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. +*/ #undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_DEFVAL #undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_SHIFT #undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_MASK -#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_DEFVAL 0x00000000 -#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_SHIFT 16 -#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_MASK 0x00030000U +#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_DEFVAL 0x00000000 +#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_SHIFT 16 +#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_MASK 0x00030000U -/*Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d - al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio - ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc - values.*/ +/* +* Separation level1 indicating the end of region0 mapping; start of region + * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + * lues are used directly as port priorities, where the higher the value co + * rresponds to higher port priority. All of the map_level* registers must + * be set to distinct values. +*/ #undef DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_DEFVAL #undef DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_SHIFT #undef DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_MASK -#define DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_DEFVAL 0x00000000 -#define DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_SHIFT 0 -#define DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_MASK 0x0000000FU +#define DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_DEFVAL 0x00000000 +#define DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_SHIFT 0 +#define DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_MASK 0x0000000FU -/*Specifies the timeout value for transactions mapped to the red address queue.*/ +/* +* Specifies the timeout value for transactions mapped to the red address q + * ueue. +*/ #undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_DEFVAL #undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_SHIFT #undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_MASK -#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_DEFVAL 0x00000000 -#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_SHIFT 16 -#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_MASK 0x07FF0000U +#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_DEFVAL 0x00000000 +#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_SHIFT 16 +#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_MASK 0x07FF0000U -/*Specifies the timeout value for transactions mapped to the blue address queue.*/ +/* +* Specifies the timeout value for transactions mapped to the blue address + * queue. +*/ #undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_DEFVAL #undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_SHIFT #undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_MASK -#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_DEFVAL 0x00000000 -#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_SHIFT 0 -#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_MASK 0x000007FFU +#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_DEFVAL 0x00000000 +#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_SHIFT 0 +#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_MASK 0x000007FFU -/*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register.*/ +/* +* If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. +*/ #undef DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_DEFVAL #undef DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_SHIFT #undef DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_MASK -#define DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_DEFVAL 0x00000000 -#define DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_SHIFT 14 -#define DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_MASK 0x00004000U +#define DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_SHIFT 14 +#define DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_MASK 0x00004000U -/*If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG. - o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add - ess handshaking (it is not associated with any particular command).*/ +/* +* If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + * bled and arurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + * urgent signal can be asserted anytime and as long as required which is i + * ndependent of address handshaking (it is not associated with any particu + * lar command). +*/ #undef DDRC_PCFGR_1_RD_PORT_URGENT_EN_DEFVAL #undef DDRC_PCFGR_1_RD_PORT_URGENT_EN_SHIFT #undef DDRC_PCFGR_1_RD_PORT_URGENT_EN_MASK -#define DDRC_PCFGR_1_RD_PORT_URGENT_EN_DEFVAL 0x00000000 -#define DDRC_PCFGR_1_RD_PORT_URGENT_EN_SHIFT 13 -#define DDRC_PCFGR_1_RD_PORT_URGENT_EN_MASK 0x00002000U +#define DDRC_PCFGR_1_RD_PORT_URGENT_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_1_RD_PORT_URGENT_EN_SHIFT 13 +#define DDRC_PCFGR_1_RD_PORT_URGENT_EN_MASK 0x00002000U -/*If set to 1, enables aging function for the read channel of the port.*/ +/* +* If set to 1, enables aging function for the read channel of the port. +*/ #undef DDRC_PCFGR_1_RD_PORT_AGING_EN_DEFVAL #undef DDRC_PCFGR_1_RD_PORT_AGING_EN_SHIFT #undef DDRC_PCFGR_1_RD_PORT_AGING_EN_MASK -#define DDRC_PCFGR_1_RD_PORT_AGING_EN_DEFVAL 0x00000000 -#define DDRC_PCFGR_1_RD_PORT_AGING_EN_SHIFT 12 -#define DDRC_PCFGR_1_RD_PORT_AGING_EN_MASK 0x00001000U +#define DDRC_PCFGR_1_RD_PORT_AGING_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_1_RD_PORT_AGING_EN_SHIFT 12 +#define DDRC_PCFGR_1_RD_PORT_AGING_EN_MASK 0x00001000U -/*Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g - ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority - will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre - ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the - aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st - ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w - ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D - RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: - he two LSBs of this register field are tied internally to 2'b00.*/ +/* +* Determines the initial load value of read aging counters. These counters + * will be parallel loaded after reset, or after each grant to the corresp + * onding port. The aging counters down-count every clock cycle where the p + * ort is requesting but not granted. The higher significant 5-bits of the + * read aging counter sets the priority of the read channel of a given port + * . Port's priority will increase as the higher significant 5-bits of the + * counter starts to decrease. When the aging counter becomes 0, the corres + * ponding port channel will have the highest priority level (timeout condi + * tion - Priority0). For multi-port configurations, the aging counters can + * not be used to set port priorities when external dynamic priority inputs + * (arqos) are enabled (timeout is still applicable). For single port conf + * igurations, the aging counters are only used when they timeout (become 0 + * ) to force read-write direction switching. In this case, external dynami + * c priority input, arqos (for reads only) can still be used to set the DD + * RC read priority (2 priority levels: low priority read - LPR, high prior + * ity read - HPR) on a command by command basis. Note: The two LSBs of thi + * s register field are tied internally to 2'b00. +*/ #undef DDRC_PCFGR_1_RD_PORT_PRIORITY_DEFVAL #undef DDRC_PCFGR_1_RD_PORT_PRIORITY_SHIFT #undef DDRC_PCFGR_1_RD_PORT_PRIORITY_MASK -#define DDRC_PCFGR_1_RD_PORT_PRIORITY_DEFVAL 0x00000000 -#define DDRC_PCFGR_1_RD_PORT_PRIORITY_SHIFT 0 -#define DDRC_PCFGR_1_RD_PORT_PRIORITY_MASK 0x000003FFU +#define DDRC_PCFGR_1_RD_PORT_PRIORITY_DEFVAL 0x00000000 +#define DDRC_PCFGR_1_RD_PORT_PRIORITY_SHIFT 0 +#define DDRC_PCFGR_1_RD_PORT_PRIORITY_MASK 0x000003FFU -/*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register.*/ +/* +* If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. +*/ #undef DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_DEFVAL #undef DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_SHIFT #undef DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_MASK -#define DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_DEFVAL 0x00004000 -#define DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_SHIFT 14 -#define DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_MASK 0x00004000U +#define DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_SHIFT 14 +#define DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_MASK 0x00004000U -/*If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register - Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is - not associated with any particular command).*/ +/* +* If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + * bled and awurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + * serted anytime and as long as required which is independent of address h + * andshaking (it is not associated with any particular command). +*/ #undef DDRC_PCFGW_1_WR_PORT_URGENT_EN_DEFVAL #undef DDRC_PCFGW_1_WR_PORT_URGENT_EN_SHIFT #undef DDRC_PCFGW_1_WR_PORT_URGENT_EN_MASK -#define DDRC_PCFGW_1_WR_PORT_URGENT_EN_DEFVAL 0x00004000 -#define DDRC_PCFGW_1_WR_PORT_URGENT_EN_SHIFT 13 -#define DDRC_PCFGW_1_WR_PORT_URGENT_EN_MASK 0x00002000U +#define DDRC_PCFGW_1_WR_PORT_URGENT_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_1_WR_PORT_URGENT_EN_SHIFT 13 +#define DDRC_PCFGW_1_WR_PORT_URGENT_EN_MASK 0x00002000U -/*If set to 1, enables aging function for the write channel of the port.*/ +/* +* If set to 1, enables aging function for the write channel of the port. +*/ #undef DDRC_PCFGW_1_WR_PORT_AGING_EN_DEFVAL #undef DDRC_PCFGW_1_WR_PORT_AGING_EN_SHIFT #undef DDRC_PCFGW_1_WR_PORT_AGING_EN_MASK -#define DDRC_PCFGW_1_WR_PORT_AGING_EN_DEFVAL 0x00004000 -#define DDRC_PCFGW_1_WR_PORT_AGING_EN_SHIFT 12 -#define DDRC_PCFGW_1_WR_PORT_AGING_EN_MASK 0x00001000U +#define DDRC_PCFGW_1_WR_PORT_AGING_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_1_WR_PORT_AGING_EN_SHIFT 12 +#define DDRC_PCFGW_1_WR_PORT_AGING_EN_MASK 0x00001000U -/*Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each - rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port - s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0 - the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno - be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For - ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch - ng. Note: The two LSBs of this register field are tied internally to 2'b00.*/ +/* +* Determines the initial load value of write aging counters. These counter + * s will be parallel loaded after reset, or after each grant to the corres + * ponding port. The aging counters down-count every clock cycle where the + * port is requesting but not granted. The higher significant 5-bits of the + * write aging counter sets the initial priority of the write channel of a + * given port. Port's priority will increase as the higher significant 5-b + * its of the counter starts to decrease. When the aging counter becomes 0, + * the corresponding port channel will have the highest priority level. Fo + * r multi-port configurations, the aging counters cannot be used to set po + * rt priorities when external dynamic priority inputs (awqos) are enabled + * (timeout is still applicable). For single port configurations, the aging + * counters are only used when they timeout (become 0) to force read-write + * direction switching. Note: The two LSBs of this register field are tied + * internally to 2'b00. +*/ #undef DDRC_PCFGW_1_WR_PORT_PRIORITY_DEFVAL #undef DDRC_PCFGW_1_WR_PORT_PRIORITY_SHIFT #undef DDRC_PCFGW_1_WR_PORT_PRIORITY_MASK -#define DDRC_PCFGW_1_WR_PORT_PRIORITY_DEFVAL 0x00004000 -#define DDRC_PCFGW_1_WR_PORT_PRIORITY_SHIFT 0 -#define DDRC_PCFGW_1_WR_PORT_PRIORITY_MASK 0x000003FFU +#define DDRC_PCFGW_1_WR_PORT_PRIORITY_DEFVAL 0x00004000 +#define DDRC_PCFGW_1_WR_PORT_PRIORITY_SHIFT 0 +#define DDRC_PCFGW_1_WR_PORT_PRIORITY_MASK 0x000003FFU -/*Enables port n.*/ +/* +* Enables port n. +*/ #undef DDRC_PCTRL_1_PORT_EN_DEFVAL #undef DDRC_PCTRL_1_PORT_EN_SHIFT #undef DDRC_PCTRL_1_PORT_EN_MASK -#define DDRC_PCTRL_1_PORT_EN_DEFVAL -#define DDRC_PCTRL_1_PORT_EN_SHIFT 0 -#define DDRC_PCTRL_1_PORT_EN_MASK 0x00000001U +#define DDRC_PCTRL_1_PORT_EN_DEFVAL +#define DDRC_PCTRL_1_PORT_EN_SHIFT 0 +#define DDRC_PCTRL_1_PORT_EN_MASK 0x00000001U -/*This bitfield indicates the traffic class of region2. For dual address queue configurations, region2 maps to the red address - ueue. Valid values are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and traffic class of region2 - s set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/ +/* +* This bitfield indicates the traffic class of region2. For dual address q + * ueue configurations, region2 maps to the red address queue. Valid values + * are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN + * = 0) and traffic class of region2 is set to 1 (VPR), VPR traffic is ali + * ased to LPR traffic. +*/ #undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_DEFVAL #undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_SHIFT #undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_MASK -#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_DEFVAL 0x02000E00 -#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_SHIFT 24 -#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_MASK 0x03000000U +#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_DEFVAL 0x02000E00 +#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_SHIFT 24 +#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_MASK 0x03000000U -/*This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf - gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is - disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/ +/* +* This bitfield indicates the traffic class of region 1. Valid values are: + * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + * maps to the blue address queue. In this case, valid values are 0: LPR a + * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. +*/ #undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_DEFVAL #undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_SHIFT #undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_MASK -#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_DEFVAL 0x02000E00 -#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_SHIFT 20 -#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_MASK 0x00300000U +#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_DEFVAL 0x02000E00 +#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_SHIFT 20 +#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_MASK 0x00300000U -/*This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi - urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i - disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/ +/* +* This bitfield indicates the traffic class of region 0. Valid values are: + * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + * maps to the blue address queue. In this case, valid values are: 0: LPR + * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. +*/ #undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_DEFVAL #undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_SHIFT #undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_MASK -#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_DEFVAL 0x02000E00 -#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_SHIFT 16 -#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_MASK 0x00030000U +#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_DEFVAL 0x02000E00 +#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_SHIFT 16 +#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_MASK 0x00030000U -/*Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (le - el1 + 1) to 14 which corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note that for PA, arqos values are used - directly as port priorities, where the higher the value corresponds to higher port priority. All of the map_level* registers - ust be set to distinct values.*/ +/* +* Separation level2 indicating the end of region1 mapping; start of region + * 1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 whi + * ch corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note + * that for PA, arqos values are used directly as port priorities, where t + * he higher the value corresponds to higher port priority. All of the map_ + * level* registers must be set to distinct values. +*/ #undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_DEFVAL #undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_SHIFT #undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_MASK -#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_DEFVAL 0x02000E00 -#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_SHIFT 8 -#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_MASK 0x00000F00U +#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_DEFVAL 0x02000E00 +#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_SHIFT 8 +#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_MASK 0x00000F00U -/*Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d - al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio - ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc - values.*/ +/* +* Separation level1 indicating the end of region0 mapping; start of region + * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + * lues are used directly as port priorities, where the higher the value co + * rresponds to higher port priority. All of the map_level* registers must + * be set to distinct values. +*/ #undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_DEFVAL #undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_SHIFT #undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_MASK -#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_DEFVAL 0x02000E00 -#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_SHIFT 0 -#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_MASK 0x0000000FU +#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_DEFVAL 0x02000E00 +#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_SHIFT 0 +#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_MASK 0x0000000FU -/*Specifies the timeout value for transactions mapped to the red address queue.*/ +/* +* Specifies the timeout value for transactions mapped to the red address q + * ueue. +*/ #undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_DEFVAL #undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_SHIFT #undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_MASK -#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_DEFVAL 0x00000000 -#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_SHIFT 16 -#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_MASK 0x07FF0000U +#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_DEFVAL 0x00000000 +#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_SHIFT 16 +#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_MASK 0x07FF0000U -/*Specifies the timeout value for transactions mapped to the blue address queue.*/ +/* +* Specifies the timeout value for transactions mapped to the blue address + * queue. +*/ #undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_DEFVAL #undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_SHIFT #undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_MASK -#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_DEFVAL 0x00000000 -#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_SHIFT 0 -#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_MASK 0x000007FFU +#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_DEFVAL 0x00000000 +#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_SHIFT 0 +#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_MASK 0x000007FFU -/*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register.*/ +/* +* If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. +*/ #undef DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_DEFVAL #undef DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_SHIFT #undef DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_MASK -#define DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_DEFVAL 0x00000000 -#define DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_SHIFT 14 -#define DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_MASK 0x00004000U +#define DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_SHIFT 14 +#define DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_MASK 0x00004000U -/*If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG. - o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add - ess handshaking (it is not associated with any particular command).*/ +/* +* If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + * bled and arurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + * urgent signal can be asserted anytime and as long as required which is i + * ndependent of address handshaking (it is not associated with any particu + * lar command). +*/ #undef DDRC_PCFGR_2_RD_PORT_URGENT_EN_DEFVAL #undef DDRC_PCFGR_2_RD_PORT_URGENT_EN_SHIFT #undef DDRC_PCFGR_2_RD_PORT_URGENT_EN_MASK -#define DDRC_PCFGR_2_RD_PORT_URGENT_EN_DEFVAL 0x00000000 -#define DDRC_PCFGR_2_RD_PORT_URGENT_EN_SHIFT 13 -#define DDRC_PCFGR_2_RD_PORT_URGENT_EN_MASK 0x00002000U +#define DDRC_PCFGR_2_RD_PORT_URGENT_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_2_RD_PORT_URGENT_EN_SHIFT 13 +#define DDRC_PCFGR_2_RD_PORT_URGENT_EN_MASK 0x00002000U -/*If set to 1, enables aging function for the read channel of the port.*/ +/* +* If set to 1, enables aging function for the read channel of the port. +*/ #undef DDRC_PCFGR_2_RD_PORT_AGING_EN_DEFVAL #undef DDRC_PCFGR_2_RD_PORT_AGING_EN_SHIFT #undef DDRC_PCFGR_2_RD_PORT_AGING_EN_MASK -#define DDRC_PCFGR_2_RD_PORT_AGING_EN_DEFVAL 0x00000000 -#define DDRC_PCFGR_2_RD_PORT_AGING_EN_SHIFT 12 -#define DDRC_PCFGR_2_RD_PORT_AGING_EN_MASK 0x00001000U +#define DDRC_PCFGR_2_RD_PORT_AGING_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_2_RD_PORT_AGING_EN_SHIFT 12 +#define DDRC_PCFGR_2_RD_PORT_AGING_EN_MASK 0x00001000U -/*Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g - ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority - will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre - ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the - aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st - ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w - ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D - RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: - he two LSBs of this register field are tied internally to 2'b00.*/ +/* +* Determines the initial load value of read aging counters. These counters + * will be parallel loaded after reset, or after each grant to the corresp + * onding port. The aging counters down-count every clock cycle where the p + * ort is requesting but not granted. The higher significant 5-bits of the + * read aging counter sets the priority of the read channel of a given port + * . Port's priority will increase as the higher significant 5-bits of the + * counter starts to decrease. When the aging counter becomes 0, the corres + * ponding port channel will have the highest priority level (timeout condi + * tion - Priority0). For multi-port configurations, the aging counters can + * not be used to set port priorities when external dynamic priority inputs + * (arqos) are enabled (timeout is still applicable). For single port conf + * igurations, the aging counters are only used when they timeout (become 0 + * ) to force read-write direction switching. In this case, external dynami + * c priority input, arqos (for reads only) can still be used to set the DD + * RC read priority (2 priority levels: low priority read - LPR, high prior + * ity read - HPR) on a command by command basis. Note: The two LSBs of thi + * s register field are tied internally to 2'b00. +*/ #undef DDRC_PCFGR_2_RD_PORT_PRIORITY_DEFVAL #undef DDRC_PCFGR_2_RD_PORT_PRIORITY_SHIFT #undef DDRC_PCFGR_2_RD_PORT_PRIORITY_MASK -#define DDRC_PCFGR_2_RD_PORT_PRIORITY_DEFVAL 0x00000000 -#define DDRC_PCFGR_2_RD_PORT_PRIORITY_SHIFT 0 -#define DDRC_PCFGR_2_RD_PORT_PRIORITY_MASK 0x000003FFU +#define DDRC_PCFGR_2_RD_PORT_PRIORITY_DEFVAL 0x00000000 +#define DDRC_PCFGR_2_RD_PORT_PRIORITY_SHIFT 0 +#define DDRC_PCFGR_2_RD_PORT_PRIORITY_MASK 0x000003FFU -/*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register.*/ +/* +* If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. +*/ #undef DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_DEFVAL #undef DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_SHIFT #undef DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_MASK -#define DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_DEFVAL 0x00004000 -#define DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_SHIFT 14 -#define DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_MASK 0x00004000U +#define DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_SHIFT 14 +#define DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_MASK 0x00004000U -/*If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register - Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is - not associated with any particular command).*/ +/* +* If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + * bled and awurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + * serted anytime and as long as required which is independent of address h + * andshaking (it is not associated with any particular command). +*/ #undef DDRC_PCFGW_2_WR_PORT_URGENT_EN_DEFVAL #undef DDRC_PCFGW_2_WR_PORT_URGENT_EN_SHIFT #undef DDRC_PCFGW_2_WR_PORT_URGENT_EN_MASK -#define DDRC_PCFGW_2_WR_PORT_URGENT_EN_DEFVAL 0x00004000 -#define DDRC_PCFGW_2_WR_PORT_URGENT_EN_SHIFT 13 -#define DDRC_PCFGW_2_WR_PORT_URGENT_EN_MASK 0x00002000U +#define DDRC_PCFGW_2_WR_PORT_URGENT_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_2_WR_PORT_URGENT_EN_SHIFT 13 +#define DDRC_PCFGW_2_WR_PORT_URGENT_EN_MASK 0x00002000U -/*If set to 1, enables aging function for the write channel of the port.*/ +/* +* If set to 1, enables aging function for the write channel of the port. +*/ #undef DDRC_PCFGW_2_WR_PORT_AGING_EN_DEFVAL #undef DDRC_PCFGW_2_WR_PORT_AGING_EN_SHIFT #undef DDRC_PCFGW_2_WR_PORT_AGING_EN_MASK -#define DDRC_PCFGW_2_WR_PORT_AGING_EN_DEFVAL 0x00004000 -#define DDRC_PCFGW_2_WR_PORT_AGING_EN_SHIFT 12 -#define DDRC_PCFGW_2_WR_PORT_AGING_EN_MASK 0x00001000U +#define DDRC_PCFGW_2_WR_PORT_AGING_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_2_WR_PORT_AGING_EN_SHIFT 12 +#define DDRC_PCFGW_2_WR_PORT_AGING_EN_MASK 0x00001000U -/*Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each - rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port - s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0 - the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno - be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For - ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch - ng. Note: The two LSBs of this register field are tied internally to 2'b00.*/ +/* +* Determines the initial load value of write aging counters. These counter + * s will be parallel loaded after reset, or after each grant to the corres + * ponding port. The aging counters down-count every clock cycle where the + * port is requesting but not granted. The higher significant 5-bits of the + * write aging counter sets the initial priority of the write channel of a + * given port. Port's priority will increase as the higher significant 5-b + * its of the counter starts to decrease. When the aging counter becomes 0, + * the corresponding port channel will have the highest priority level. Fo + * r multi-port configurations, the aging counters cannot be used to set po + * rt priorities when external dynamic priority inputs (awqos) are enabled + * (timeout is still applicable). For single port configurations, the aging + * counters are only used when they timeout (become 0) to force read-write + * direction switching. Note: The two LSBs of this register field are tied + * internally to 2'b00. +*/ #undef DDRC_PCFGW_2_WR_PORT_PRIORITY_DEFVAL #undef DDRC_PCFGW_2_WR_PORT_PRIORITY_SHIFT #undef DDRC_PCFGW_2_WR_PORT_PRIORITY_MASK -#define DDRC_PCFGW_2_WR_PORT_PRIORITY_DEFVAL 0x00004000 -#define DDRC_PCFGW_2_WR_PORT_PRIORITY_SHIFT 0 -#define DDRC_PCFGW_2_WR_PORT_PRIORITY_MASK 0x000003FFU +#define DDRC_PCFGW_2_WR_PORT_PRIORITY_DEFVAL 0x00004000 +#define DDRC_PCFGW_2_WR_PORT_PRIORITY_SHIFT 0 +#define DDRC_PCFGW_2_WR_PORT_PRIORITY_MASK 0x000003FFU -/*Enables port n.*/ +/* +* Enables port n. +*/ #undef DDRC_PCTRL_2_PORT_EN_DEFVAL #undef DDRC_PCTRL_2_PORT_EN_SHIFT #undef DDRC_PCTRL_2_PORT_EN_MASK -#define DDRC_PCTRL_2_PORT_EN_DEFVAL -#define DDRC_PCTRL_2_PORT_EN_SHIFT 0 -#define DDRC_PCTRL_2_PORT_EN_MASK 0x00000001U +#define DDRC_PCTRL_2_PORT_EN_DEFVAL +#define DDRC_PCTRL_2_PORT_EN_SHIFT 0 +#define DDRC_PCTRL_2_PORT_EN_MASK 0x00000001U -/*This bitfield indicates the traffic class of region2. For dual address queue configurations, region2 maps to the red address - ueue. Valid values are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and traffic class of region2 - s set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/ +/* +* This bitfield indicates the traffic class of region2. For dual address q + * ueue configurations, region2 maps to the red address queue. Valid values + * are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN + * = 0) and traffic class of region2 is set to 1 (VPR), VPR traffic is ali + * ased to LPR traffic. +*/ #undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_DEFVAL #undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_SHIFT #undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_MASK -#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_DEFVAL 0x02000E00 -#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_SHIFT 24 -#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_MASK 0x03000000U +#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_DEFVAL 0x02000E00 +#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_SHIFT 24 +#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_MASK 0x03000000U -/*This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf - gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is - disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/ +/* +* This bitfield indicates the traffic class of region 1. Valid values are: + * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + * maps to the blue address queue. In this case, valid values are 0: LPR a + * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. +*/ #undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_DEFVAL #undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_SHIFT #undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_MASK -#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_DEFVAL 0x02000E00 -#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_SHIFT 20 -#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_MASK 0x00300000U +#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_DEFVAL 0x02000E00 +#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_SHIFT 20 +#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_MASK 0x00300000U -/*This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi - urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i - disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/ +/* +* This bitfield indicates the traffic class of region 0. Valid values are: + * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + * maps to the blue address queue. In this case, valid values are: 0: LPR + * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. +*/ #undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_DEFVAL #undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_SHIFT #undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_MASK -#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_DEFVAL 0x02000E00 -#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_SHIFT 16 -#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_MASK 0x00030000U +#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_DEFVAL 0x02000E00 +#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_SHIFT 16 +#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_MASK 0x00030000U -/*Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (le - el1 + 1) to 14 which corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note that for PA, arqos values are used - directly as port priorities, where the higher the value corresponds to higher port priority. All of the map_level* registers - ust be set to distinct values.*/ +/* +* Separation level2 indicating the end of region1 mapping; start of region + * 1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 whi + * ch corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note + * that for PA, arqos values are used directly as port priorities, where t + * he higher the value corresponds to higher port priority. All of the map_ + * level* registers must be set to distinct values. +*/ #undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_DEFVAL #undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_SHIFT #undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_MASK -#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_DEFVAL 0x02000E00 -#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_SHIFT 8 -#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_MASK 0x00000F00U +#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_DEFVAL 0x02000E00 +#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_SHIFT 8 +#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_MASK 0x00000F00U -/*Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d - al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio - ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc - values.*/ +/* +* Separation level1 indicating the end of region0 mapping; start of region + * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + * lues are used directly as port priorities, where the higher the value co + * rresponds to higher port priority. All of the map_level* registers must + * be set to distinct values. +*/ #undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_DEFVAL #undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_SHIFT #undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_MASK -#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_DEFVAL 0x02000E00 -#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_SHIFT 0 -#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_MASK 0x0000000FU +#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_DEFVAL 0x02000E00 +#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_SHIFT 0 +#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_MASK 0x0000000FU -/*Specifies the timeout value for transactions mapped to the red address queue.*/ +/* +* Specifies the timeout value for transactions mapped to the red address q + * ueue. +*/ #undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_DEFVAL #undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_SHIFT #undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_MASK -#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_DEFVAL 0x00000000 -#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_SHIFT 16 -#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_MASK 0x07FF0000U +#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_DEFVAL 0x00000000 +#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_SHIFT 16 +#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_MASK 0x07FF0000U -/*Specifies the timeout value for transactions mapped to the blue address queue.*/ +/* +* Specifies the timeout value for transactions mapped to the blue address + * queue. +*/ #undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_DEFVAL #undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_SHIFT #undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_MASK -#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_DEFVAL 0x00000000 -#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_SHIFT 0 -#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_MASK 0x000007FFU +#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_DEFVAL 0x00000000 +#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_SHIFT 0 +#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_MASK 0x000007FFU -/*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register.*/ +/* +* If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. +*/ #undef DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_DEFVAL #undef DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_SHIFT #undef DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_MASK -#define DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_DEFVAL 0x00000000 -#define DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_SHIFT 14 -#define DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_MASK 0x00004000U +#define DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_SHIFT 14 +#define DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_MASK 0x00004000U -/*If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG. - o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add - ess handshaking (it is not associated with any particular command).*/ +/* +* If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + * bled and arurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + * urgent signal can be asserted anytime and as long as required which is i + * ndependent of address handshaking (it is not associated with any particu + * lar command). +*/ #undef DDRC_PCFGR_3_RD_PORT_URGENT_EN_DEFVAL #undef DDRC_PCFGR_3_RD_PORT_URGENT_EN_SHIFT #undef DDRC_PCFGR_3_RD_PORT_URGENT_EN_MASK -#define DDRC_PCFGR_3_RD_PORT_URGENT_EN_DEFVAL 0x00000000 -#define DDRC_PCFGR_3_RD_PORT_URGENT_EN_SHIFT 13 -#define DDRC_PCFGR_3_RD_PORT_URGENT_EN_MASK 0x00002000U +#define DDRC_PCFGR_3_RD_PORT_URGENT_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_3_RD_PORT_URGENT_EN_SHIFT 13 +#define DDRC_PCFGR_3_RD_PORT_URGENT_EN_MASK 0x00002000U -/*If set to 1, enables aging function for the read channel of the port.*/ +/* +* If set to 1, enables aging function for the read channel of the port. +*/ #undef DDRC_PCFGR_3_RD_PORT_AGING_EN_DEFVAL #undef DDRC_PCFGR_3_RD_PORT_AGING_EN_SHIFT #undef DDRC_PCFGR_3_RD_PORT_AGING_EN_MASK -#define DDRC_PCFGR_3_RD_PORT_AGING_EN_DEFVAL 0x00000000 -#define DDRC_PCFGR_3_RD_PORT_AGING_EN_SHIFT 12 -#define DDRC_PCFGR_3_RD_PORT_AGING_EN_MASK 0x00001000U +#define DDRC_PCFGR_3_RD_PORT_AGING_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_3_RD_PORT_AGING_EN_SHIFT 12 +#define DDRC_PCFGR_3_RD_PORT_AGING_EN_MASK 0x00001000U -/*Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g - ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority - will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre - ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the - aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st - ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w - ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D - RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: - he two LSBs of this register field are tied internally to 2'b00.*/ +/* +* Determines the initial load value of read aging counters. These counters + * will be parallel loaded after reset, or after each grant to the corresp + * onding port. The aging counters down-count every clock cycle where the p + * ort is requesting but not granted. The higher significant 5-bits of the + * read aging counter sets the priority of the read channel of a given port + * . Port's priority will increase as the higher significant 5-bits of the + * counter starts to decrease. When the aging counter becomes 0, the corres + * ponding port channel will have the highest priority level (timeout condi + * tion - Priority0). For multi-port configurations, the aging counters can + * not be used to set port priorities when external dynamic priority inputs + * (arqos) are enabled (timeout is still applicable). For single port conf + * igurations, the aging counters are only used when they timeout (become 0 + * ) to force read-write direction switching. In this case, external dynami + * c priority input, arqos (for reads only) can still be used to set the DD + * RC read priority (2 priority levels: low priority read - LPR, high prior + * ity read - HPR) on a command by command basis. Note: The two LSBs of thi + * s register field are tied internally to 2'b00. +*/ #undef DDRC_PCFGR_3_RD_PORT_PRIORITY_DEFVAL #undef DDRC_PCFGR_3_RD_PORT_PRIORITY_SHIFT #undef DDRC_PCFGR_3_RD_PORT_PRIORITY_MASK -#define DDRC_PCFGR_3_RD_PORT_PRIORITY_DEFVAL 0x00000000 -#define DDRC_PCFGR_3_RD_PORT_PRIORITY_SHIFT 0 -#define DDRC_PCFGR_3_RD_PORT_PRIORITY_MASK 0x000003FFU +#define DDRC_PCFGR_3_RD_PORT_PRIORITY_DEFVAL 0x00000000 +#define DDRC_PCFGR_3_RD_PORT_PRIORITY_SHIFT 0 +#define DDRC_PCFGR_3_RD_PORT_PRIORITY_MASK 0x000003FFU -/*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register.*/ +/* +* If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. +*/ #undef DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_DEFVAL #undef DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_SHIFT #undef DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_MASK -#define DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_DEFVAL 0x00004000 -#define DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_SHIFT 14 -#define DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_MASK 0x00004000U +#define DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_SHIFT 14 +#define DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_MASK 0x00004000U -/*If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register - Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is - not associated with any particular command).*/ +/* +* If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + * bled and awurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + * serted anytime and as long as required which is independent of address h + * andshaking (it is not associated with any particular command). +*/ #undef DDRC_PCFGW_3_WR_PORT_URGENT_EN_DEFVAL #undef DDRC_PCFGW_3_WR_PORT_URGENT_EN_SHIFT #undef DDRC_PCFGW_3_WR_PORT_URGENT_EN_MASK -#define DDRC_PCFGW_3_WR_PORT_URGENT_EN_DEFVAL 0x00004000 -#define DDRC_PCFGW_3_WR_PORT_URGENT_EN_SHIFT 13 -#define DDRC_PCFGW_3_WR_PORT_URGENT_EN_MASK 0x00002000U +#define DDRC_PCFGW_3_WR_PORT_URGENT_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_3_WR_PORT_URGENT_EN_SHIFT 13 +#define DDRC_PCFGW_3_WR_PORT_URGENT_EN_MASK 0x00002000U -/*If set to 1, enables aging function for the write channel of the port.*/ +/* +* If set to 1, enables aging function for the write channel of the port. +*/ #undef DDRC_PCFGW_3_WR_PORT_AGING_EN_DEFVAL #undef DDRC_PCFGW_3_WR_PORT_AGING_EN_SHIFT #undef DDRC_PCFGW_3_WR_PORT_AGING_EN_MASK -#define DDRC_PCFGW_3_WR_PORT_AGING_EN_DEFVAL 0x00004000 -#define DDRC_PCFGW_3_WR_PORT_AGING_EN_SHIFT 12 -#define DDRC_PCFGW_3_WR_PORT_AGING_EN_MASK 0x00001000U +#define DDRC_PCFGW_3_WR_PORT_AGING_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_3_WR_PORT_AGING_EN_SHIFT 12 +#define DDRC_PCFGW_3_WR_PORT_AGING_EN_MASK 0x00001000U -/*Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each - rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port - s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0 - the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno - be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For - ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch - ng. Note: The two LSBs of this register field are tied internally to 2'b00.*/ +/* +* Determines the initial load value of write aging counters. These counter + * s will be parallel loaded after reset, or after each grant to the corres + * ponding port. The aging counters down-count every clock cycle where the + * port is requesting but not granted. The higher significant 5-bits of the + * write aging counter sets the initial priority of the write channel of a + * given port. Port's priority will increase as the higher significant 5-b + * its of the counter starts to decrease. When the aging counter becomes 0, + * the corresponding port channel will have the highest priority level. Fo + * r multi-port configurations, the aging counters cannot be used to set po + * rt priorities when external dynamic priority inputs (awqos) are enabled + * (timeout is still applicable). For single port configurations, the aging + * counters are only used when they timeout (become 0) to force read-write + * direction switching. Note: The two LSBs of this register field are tied + * internally to 2'b00. +*/ #undef DDRC_PCFGW_3_WR_PORT_PRIORITY_DEFVAL #undef DDRC_PCFGW_3_WR_PORT_PRIORITY_SHIFT #undef DDRC_PCFGW_3_WR_PORT_PRIORITY_MASK -#define DDRC_PCFGW_3_WR_PORT_PRIORITY_DEFVAL 0x00004000 -#define DDRC_PCFGW_3_WR_PORT_PRIORITY_SHIFT 0 -#define DDRC_PCFGW_3_WR_PORT_PRIORITY_MASK 0x000003FFU +#define DDRC_PCFGW_3_WR_PORT_PRIORITY_DEFVAL 0x00004000 +#define DDRC_PCFGW_3_WR_PORT_PRIORITY_SHIFT 0 +#define DDRC_PCFGW_3_WR_PORT_PRIORITY_MASK 0x000003FFU -/*Enables port n.*/ +/* +* Enables port n. +*/ #undef DDRC_PCTRL_3_PORT_EN_DEFVAL #undef DDRC_PCTRL_3_PORT_EN_SHIFT #undef DDRC_PCTRL_3_PORT_EN_MASK -#define DDRC_PCTRL_3_PORT_EN_DEFVAL -#define DDRC_PCTRL_3_PORT_EN_SHIFT 0 -#define DDRC_PCTRL_3_PORT_EN_MASK 0x00000001U +#define DDRC_PCTRL_3_PORT_EN_DEFVAL +#define DDRC_PCTRL_3_PORT_EN_SHIFT 0 +#define DDRC_PCTRL_3_PORT_EN_MASK 0x00000001U -/*This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf - gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is - disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/ +/* +* This bitfield indicates the traffic class of region 1. Valid values are: + * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + * maps to the blue address queue. In this case, valid values are 0: LPR a + * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. +*/ #undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_DEFVAL #undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_SHIFT #undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_MASK -#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_DEFVAL 0x00000000 -#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_SHIFT 20 -#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_MASK 0x00300000U +#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_DEFVAL 0x00000000 +#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_SHIFT 20 +#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_MASK 0x00300000U -/*This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi - urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i - disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/ +/* +* This bitfield indicates the traffic class of region 0. Valid values are: + * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + * maps to the blue address queue. In this case, valid values are: 0: LPR + * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. +*/ #undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_DEFVAL #undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_SHIFT #undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_MASK -#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_DEFVAL 0x00000000 -#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_SHIFT 16 -#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_MASK 0x00030000U +#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_DEFVAL 0x00000000 +#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_SHIFT 16 +#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_MASK 0x00030000U -/*Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d - al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio - ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc - values.*/ +/* +* Separation level1 indicating the end of region0 mapping; start of region + * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + * lues are used directly as port priorities, where the higher the value co + * rresponds to higher port priority. All of the map_level* registers must + * be set to distinct values. +*/ #undef DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_DEFVAL #undef DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_SHIFT #undef DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_MASK -#define DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_DEFVAL 0x00000000 -#define DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_SHIFT 0 -#define DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_MASK 0x0000000FU +#define DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_DEFVAL 0x00000000 +#define DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_SHIFT 0 +#define DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_MASK 0x0000000FU -/*Specifies the timeout value for transactions mapped to the red address queue.*/ +/* +* Specifies the timeout value for transactions mapped to the red address q + * ueue. +*/ #undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_DEFVAL #undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_SHIFT #undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_MASK -#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_DEFVAL 0x00000000 -#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_SHIFT 16 -#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_MASK 0x07FF0000U +#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_DEFVAL 0x00000000 +#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_SHIFT 16 +#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_MASK 0x07FF0000U -/*Specifies the timeout value for transactions mapped to the blue address queue.*/ +/* +* Specifies the timeout value for transactions mapped to the blue address + * queue. +*/ #undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_DEFVAL #undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_SHIFT #undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_MASK -#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_DEFVAL 0x00000000 -#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_SHIFT 0 -#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_MASK 0x000007FFU +#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_DEFVAL 0x00000000 +#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_SHIFT 0 +#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_MASK 0x000007FFU -/*This bitfield indicates the traffic class of region 1. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2 - VPW_EN = 0) and traffic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW traffic.*/ +/* +* This bitfield indicates the traffic class of region 1. Valid values are: + * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + * affic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW + * traffic. +*/ #undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_DEFVAL #undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_SHIFT #undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_MASK -#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_DEFVAL 0x00000000 -#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_SHIFT 20 -#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_MASK 0x00300000U +#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_DEFVAL 0x00000000 +#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_SHIFT 20 +#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_MASK 0x00300000U -/*This bitfield indicates the traffic class of region 0. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2 - VPW_EN = 0) and traffic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW traffic.*/ +/* +* This bitfield indicates the traffic class of region 0. Valid values are: + * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + * affic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW + * traffic. +*/ #undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_DEFVAL #undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_SHIFT #undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_MASK -#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_DEFVAL 0x00000000 -#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_SHIFT 16 -#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_MASK 0x00030000U +#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_DEFVAL 0x00000000 +#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_SHIFT 16 +#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_MASK 0x00030000U -/*Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 14 which c - rresponds to awqos. Note that for PA, awqos values are used directly as port priorities, where the higher the value correspon - s to higher port priority.*/ +/* +* Separation level indicating the end of region0 mapping; start of region0 + * is 0. Possible values for level1 are 0 to 14 which corresponds to awqos + * . Note that for PA, awqos values are used directly as port priorities, w + * here the higher the value corresponds to higher port priority. +*/ #undef DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_DEFVAL #undef DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_SHIFT #undef DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_MASK -#define DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_DEFVAL 0x00000000 -#define DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_SHIFT 0 -#define DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_MASK 0x0000000FU +#define DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_DEFVAL 0x00000000 +#define DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_SHIFT 0 +#define DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_MASK 0x0000000FU -/*Specifies the timeout value for write transactions.*/ +/* +* Specifies the timeout value for write transactions. +*/ #undef DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_DEFVAL #undef DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_SHIFT #undef DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_MASK -#define DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_DEFVAL -#define DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_SHIFT 0 -#define DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_MASK 0x000007FFU +#define DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_DEFVAL +#define DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_SHIFT 0 +#define DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_MASK 0x000007FFU -/*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register.*/ +/* +* If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. +*/ #undef DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_DEFVAL #undef DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_SHIFT #undef DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_MASK -#define DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_DEFVAL 0x00000000 -#define DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_SHIFT 14 -#define DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_MASK 0x00004000U +#define DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_SHIFT 14 +#define DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_MASK 0x00004000U -/*If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG. - o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add - ess handshaking (it is not associated with any particular command).*/ +/* +* If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + * bled and arurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + * urgent signal can be asserted anytime and as long as required which is i + * ndependent of address handshaking (it is not associated with any particu + * lar command). +*/ #undef DDRC_PCFGR_4_RD_PORT_URGENT_EN_DEFVAL #undef DDRC_PCFGR_4_RD_PORT_URGENT_EN_SHIFT #undef DDRC_PCFGR_4_RD_PORT_URGENT_EN_MASK -#define DDRC_PCFGR_4_RD_PORT_URGENT_EN_DEFVAL 0x00000000 -#define DDRC_PCFGR_4_RD_PORT_URGENT_EN_SHIFT 13 -#define DDRC_PCFGR_4_RD_PORT_URGENT_EN_MASK 0x00002000U +#define DDRC_PCFGR_4_RD_PORT_URGENT_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_4_RD_PORT_URGENT_EN_SHIFT 13 +#define DDRC_PCFGR_4_RD_PORT_URGENT_EN_MASK 0x00002000U -/*If set to 1, enables aging function for the read channel of the port.*/ +/* +* If set to 1, enables aging function for the read channel of the port. +*/ #undef DDRC_PCFGR_4_RD_PORT_AGING_EN_DEFVAL #undef DDRC_PCFGR_4_RD_PORT_AGING_EN_SHIFT #undef DDRC_PCFGR_4_RD_PORT_AGING_EN_MASK -#define DDRC_PCFGR_4_RD_PORT_AGING_EN_DEFVAL 0x00000000 -#define DDRC_PCFGR_4_RD_PORT_AGING_EN_SHIFT 12 -#define DDRC_PCFGR_4_RD_PORT_AGING_EN_MASK 0x00001000U +#define DDRC_PCFGR_4_RD_PORT_AGING_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_4_RD_PORT_AGING_EN_SHIFT 12 +#define DDRC_PCFGR_4_RD_PORT_AGING_EN_MASK 0x00001000U -/*Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g - ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority - will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre - ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the - aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st - ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w - ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D - RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: - he two LSBs of this register field are tied internally to 2'b00.*/ +/* +* Determines the initial load value of read aging counters. These counters + * will be parallel loaded after reset, or after each grant to the corresp + * onding port. The aging counters down-count every clock cycle where the p + * ort is requesting but not granted. The higher significant 5-bits of the + * read aging counter sets the priority of the read channel of a given port + * . Port's priority will increase as the higher significant 5-bits of the + * counter starts to decrease. When the aging counter becomes 0, the corres + * ponding port channel will have the highest priority level (timeout condi + * tion - Priority0). For multi-port configurations, the aging counters can + * not be used to set port priorities when external dynamic priority inputs + * (arqos) are enabled (timeout is still applicable). For single port conf + * igurations, the aging counters are only used when they timeout (become 0 + * ) to force read-write direction switching. In this case, external dynami + * c priority input, arqos (for reads only) can still be used to set the DD + * RC read priority (2 priority levels: low priority read - LPR, high prior + * ity read - HPR) on a command by command basis. Note: The two LSBs of thi + * s register field are tied internally to 2'b00. +*/ #undef DDRC_PCFGR_4_RD_PORT_PRIORITY_DEFVAL #undef DDRC_PCFGR_4_RD_PORT_PRIORITY_SHIFT #undef DDRC_PCFGR_4_RD_PORT_PRIORITY_MASK -#define DDRC_PCFGR_4_RD_PORT_PRIORITY_DEFVAL 0x00000000 -#define DDRC_PCFGR_4_RD_PORT_PRIORITY_SHIFT 0 -#define DDRC_PCFGR_4_RD_PORT_PRIORITY_MASK 0x000003FFU +#define DDRC_PCFGR_4_RD_PORT_PRIORITY_DEFVAL 0x00000000 +#define DDRC_PCFGR_4_RD_PORT_PRIORITY_SHIFT 0 +#define DDRC_PCFGR_4_RD_PORT_PRIORITY_MASK 0x000003FFU -/*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register.*/ +/* +* If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. +*/ #undef DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_DEFVAL #undef DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_SHIFT #undef DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_MASK -#define DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_DEFVAL 0x00004000 -#define DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_SHIFT 14 -#define DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_MASK 0x00004000U +#define DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_SHIFT 14 +#define DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_MASK 0x00004000U -/*If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register - Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is - not associated with any particular command).*/ +/* +* If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + * bled and awurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + * serted anytime and as long as required which is independent of address h + * andshaking (it is not associated with any particular command). +*/ #undef DDRC_PCFGW_4_WR_PORT_URGENT_EN_DEFVAL #undef DDRC_PCFGW_4_WR_PORT_URGENT_EN_SHIFT #undef DDRC_PCFGW_4_WR_PORT_URGENT_EN_MASK -#define DDRC_PCFGW_4_WR_PORT_URGENT_EN_DEFVAL 0x00004000 -#define DDRC_PCFGW_4_WR_PORT_URGENT_EN_SHIFT 13 -#define DDRC_PCFGW_4_WR_PORT_URGENT_EN_MASK 0x00002000U +#define DDRC_PCFGW_4_WR_PORT_URGENT_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_4_WR_PORT_URGENT_EN_SHIFT 13 +#define DDRC_PCFGW_4_WR_PORT_URGENT_EN_MASK 0x00002000U -/*If set to 1, enables aging function for the write channel of the port.*/ +/* +* If set to 1, enables aging function for the write channel of the port. +*/ #undef DDRC_PCFGW_4_WR_PORT_AGING_EN_DEFVAL #undef DDRC_PCFGW_4_WR_PORT_AGING_EN_SHIFT #undef DDRC_PCFGW_4_WR_PORT_AGING_EN_MASK -#define DDRC_PCFGW_4_WR_PORT_AGING_EN_DEFVAL 0x00004000 -#define DDRC_PCFGW_4_WR_PORT_AGING_EN_SHIFT 12 -#define DDRC_PCFGW_4_WR_PORT_AGING_EN_MASK 0x00001000U +#define DDRC_PCFGW_4_WR_PORT_AGING_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_4_WR_PORT_AGING_EN_SHIFT 12 +#define DDRC_PCFGW_4_WR_PORT_AGING_EN_MASK 0x00001000U -/*Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each - rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port - s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0 - the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno - be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For - ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch - ng. Note: The two LSBs of this register field are tied internally to 2'b00.*/ +/* +* Determines the initial load value of write aging counters. These counter + * s will be parallel loaded after reset, or after each grant to the corres + * ponding port. The aging counters down-count every clock cycle where the + * port is requesting but not granted. The higher significant 5-bits of the + * write aging counter sets the initial priority of the write channel of a + * given port. Port's priority will increase as the higher significant 5-b + * its of the counter starts to decrease. When the aging counter becomes 0, + * the corresponding port channel will have the highest priority level. Fo + * r multi-port configurations, the aging counters cannot be used to set po + * rt priorities when external dynamic priority inputs (awqos) are enabled + * (timeout is still applicable). For single port configurations, the aging + * counters are only used when they timeout (become 0) to force read-write + * direction switching. Note: The two LSBs of this register field are tied + * internally to 2'b00. +*/ #undef DDRC_PCFGW_4_WR_PORT_PRIORITY_DEFVAL #undef DDRC_PCFGW_4_WR_PORT_PRIORITY_SHIFT #undef DDRC_PCFGW_4_WR_PORT_PRIORITY_MASK -#define DDRC_PCFGW_4_WR_PORT_PRIORITY_DEFVAL 0x00004000 -#define DDRC_PCFGW_4_WR_PORT_PRIORITY_SHIFT 0 -#define DDRC_PCFGW_4_WR_PORT_PRIORITY_MASK 0x000003FFU +#define DDRC_PCFGW_4_WR_PORT_PRIORITY_DEFVAL 0x00004000 +#define DDRC_PCFGW_4_WR_PORT_PRIORITY_SHIFT 0 +#define DDRC_PCFGW_4_WR_PORT_PRIORITY_MASK 0x000003FFU -/*Enables port n.*/ +/* +* Enables port n. +*/ #undef DDRC_PCTRL_4_PORT_EN_DEFVAL #undef DDRC_PCTRL_4_PORT_EN_SHIFT #undef DDRC_PCTRL_4_PORT_EN_MASK -#define DDRC_PCTRL_4_PORT_EN_DEFVAL -#define DDRC_PCTRL_4_PORT_EN_SHIFT 0 -#define DDRC_PCTRL_4_PORT_EN_MASK 0x00000001U +#define DDRC_PCTRL_4_PORT_EN_DEFVAL +#define DDRC_PCTRL_4_PORT_EN_SHIFT 0 +#define DDRC_PCTRL_4_PORT_EN_MASK 0x00000001U -/*This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf - gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is - disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/ +/* +* This bitfield indicates the traffic class of region 1. Valid values are: + * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + * maps to the blue address queue. In this case, valid values are 0: LPR a + * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. +*/ #undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_DEFVAL #undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_SHIFT #undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_MASK -#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_DEFVAL 0x00000000 -#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_SHIFT 20 -#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_MASK 0x00300000U +#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_DEFVAL 0x00000000 +#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_SHIFT 20 +#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_MASK 0x00300000U -/*This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi - urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i - disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/ +/* +* This bitfield indicates the traffic class of region 0. Valid values are: + * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + * maps to the blue address queue. In this case, valid values are: 0: LPR + * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. +*/ #undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_DEFVAL #undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_SHIFT #undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_MASK -#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_DEFVAL 0x00000000 -#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_SHIFT 16 -#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_MASK 0x00030000U +#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_DEFVAL 0x00000000 +#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_SHIFT 16 +#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_MASK 0x00030000U -/*Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d - al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio - ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc - values.*/ +/* +* Separation level1 indicating the end of region0 mapping; start of region + * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + * lues are used directly as port priorities, where the higher the value co + * rresponds to higher port priority. All of the map_level* registers must + * be set to distinct values. +*/ #undef DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_DEFVAL #undef DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_SHIFT #undef DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_MASK -#define DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_DEFVAL 0x00000000 -#define DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_SHIFT 0 -#define DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_MASK 0x0000000FU +#define DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_DEFVAL 0x00000000 +#define DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_SHIFT 0 +#define DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_MASK 0x0000000FU -/*Specifies the timeout value for transactions mapped to the red address queue.*/ +/* +* Specifies the timeout value for transactions mapped to the red address q + * ueue. +*/ #undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_DEFVAL #undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_SHIFT #undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_MASK -#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_DEFVAL 0x00000000 -#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_SHIFT 16 -#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_MASK 0x07FF0000U +#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_DEFVAL 0x00000000 +#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_SHIFT 16 +#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_MASK 0x07FF0000U -/*Specifies the timeout value for transactions mapped to the blue address queue.*/ +/* +* Specifies the timeout value for transactions mapped to the blue address + * queue. +*/ #undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_DEFVAL #undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_SHIFT #undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_MASK -#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_DEFVAL 0x00000000 -#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_SHIFT 0 -#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_MASK 0x000007FFU +#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_DEFVAL 0x00000000 +#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_SHIFT 0 +#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_MASK 0x000007FFU -/*This bitfield indicates the traffic class of region 1. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2 - VPW_EN = 0) and traffic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW traffic.*/ +/* +* This bitfield indicates the traffic class of region 1. Valid values are: + * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + * affic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW + * traffic. +*/ #undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_DEFVAL #undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_SHIFT #undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_MASK -#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_DEFVAL 0x00000000 -#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_SHIFT 20 -#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_MASK 0x00300000U +#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_DEFVAL 0x00000000 +#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_SHIFT 20 +#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_MASK 0x00300000U -/*This bitfield indicates the traffic class of region 0. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2 - VPW_EN = 0) and traffic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW traffic.*/ +/* +* This bitfield indicates the traffic class of region 0. Valid values are: + * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + * affic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW + * traffic. +*/ #undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_DEFVAL #undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_SHIFT #undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_MASK -#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_DEFVAL 0x00000000 -#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_SHIFT 16 -#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_MASK 0x00030000U +#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_DEFVAL 0x00000000 +#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_SHIFT 16 +#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_MASK 0x00030000U -/*Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 14 which c - rresponds to awqos. Note that for PA, awqos values are used directly as port priorities, where the higher the value correspon - s to higher port priority.*/ +/* +* Separation level indicating the end of region0 mapping; start of region0 + * is 0. Possible values for level1 are 0 to 14 which corresponds to awqos + * . Note that for PA, awqos values are used directly as port priorities, w + * here the higher the value corresponds to higher port priority. +*/ #undef DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_DEFVAL #undef DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_SHIFT #undef DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_MASK -#define DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_DEFVAL 0x00000000 -#define DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_SHIFT 0 -#define DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_MASK 0x0000000FU +#define DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_DEFVAL 0x00000000 +#define DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_SHIFT 0 +#define DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_MASK 0x0000000FU -/*Specifies the timeout value for write transactions.*/ +/* +* Specifies the timeout value for write transactions. +*/ #undef DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_DEFVAL #undef DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_SHIFT #undef DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_MASK -#define DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_DEFVAL -#define DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_SHIFT 0 -#define DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_MASK 0x000007FFU +#define DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_DEFVAL +#define DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_SHIFT 0 +#define DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_MASK 0x000007FFU -/*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register.*/ +/* +* If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. +*/ #undef DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_DEFVAL #undef DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_SHIFT #undef DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_MASK -#define DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_DEFVAL 0x00000000 -#define DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_SHIFT 14 -#define DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_MASK 0x00004000U +#define DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_SHIFT 14 +#define DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_MASK 0x00004000U -/*If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG. - o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add - ess handshaking (it is not associated with any particular command).*/ +/* +* If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + * bled and arurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + * urgent signal can be asserted anytime and as long as required which is i + * ndependent of address handshaking (it is not associated with any particu + * lar command). +*/ #undef DDRC_PCFGR_5_RD_PORT_URGENT_EN_DEFVAL #undef DDRC_PCFGR_5_RD_PORT_URGENT_EN_SHIFT #undef DDRC_PCFGR_5_RD_PORT_URGENT_EN_MASK -#define DDRC_PCFGR_5_RD_PORT_URGENT_EN_DEFVAL 0x00000000 -#define DDRC_PCFGR_5_RD_PORT_URGENT_EN_SHIFT 13 -#define DDRC_PCFGR_5_RD_PORT_URGENT_EN_MASK 0x00002000U +#define DDRC_PCFGR_5_RD_PORT_URGENT_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_5_RD_PORT_URGENT_EN_SHIFT 13 +#define DDRC_PCFGR_5_RD_PORT_URGENT_EN_MASK 0x00002000U -/*If set to 1, enables aging function for the read channel of the port.*/ +/* +* If set to 1, enables aging function for the read channel of the port. +*/ #undef DDRC_PCFGR_5_RD_PORT_AGING_EN_DEFVAL #undef DDRC_PCFGR_5_RD_PORT_AGING_EN_SHIFT #undef DDRC_PCFGR_5_RD_PORT_AGING_EN_MASK -#define DDRC_PCFGR_5_RD_PORT_AGING_EN_DEFVAL 0x00000000 -#define DDRC_PCFGR_5_RD_PORT_AGING_EN_SHIFT 12 -#define DDRC_PCFGR_5_RD_PORT_AGING_EN_MASK 0x00001000U +#define DDRC_PCFGR_5_RD_PORT_AGING_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_5_RD_PORT_AGING_EN_SHIFT 12 +#define DDRC_PCFGR_5_RD_PORT_AGING_EN_MASK 0x00001000U -/*Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g - ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority - will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre - ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the - aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st - ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w - ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D - RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: - he two LSBs of this register field are tied internally to 2'b00.*/ +/* +* Determines the initial load value of read aging counters. These counters + * will be parallel loaded after reset, or after each grant to the corresp + * onding port. The aging counters down-count every clock cycle where the p + * ort is requesting but not granted. The higher significant 5-bits of the + * read aging counter sets the priority of the read channel of a given port + * . Port's priority will increase as the higher significant 5-bits of the + * counter starts to decrease. When the aging counter becomes 0, the corres + * ponding port channel will have the highest priority level (timeout condi + * tion - Priority0). For multi-port configurations, the aging counters can + * not be used to set port priorities when external dynamic priority inputs + * (arqos) are enabled (timeout is still applicable). For single port conf + * igurations, the aging counters are only used when they timeout (become 0 + * ) to force read-write direction switching. In this case, external dynami + * c priority input, arqos (for reads only) can still be used to set the DD + * RC read priority (2 priority levels: low priority read - LPR, high prior + * ity read - HPR) on a command by command basis. Note: The two LSBs of thi + * s register field are tied internally to 2'b00. +*/ #undef DDRC_PCFGR_5_RD_PORT_PRIORITY_DEFVAL #undef DDRC_PCFGR_5_RD_PORT_PRIORITY_SHIFT #undef DDRC_PCFGR_5_RD_PORT_PRIORITY_MASK -#define DDRC_PCFGR_5_RD_PORT_PRIORITY_DEFVAL 0x00000000 -#define DDRC_PCFGR_5_RD_PORT_PRIORITY_SHIFT 0 -#define DDRC_PCFGR_5_RD_PORT_PRIORITY_MASK 0x000003FFU +#define DDRC_PCFGR_5_RD_PORT_PRIORITY_DEFVAL 0x00000000 +#define DDRC_PCFGR_5_RD_PORT_PRIORITY_SHIFT 0 +#define DDRC_PCFGR_5_RD_PORT_PRIORITY_MASK 0x000003FFU -/*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register.*/ +/* +* If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. +*/ #undef DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_DEFVAL #undef DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_SHIFT #undef DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_MASK -#define DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_DEFVAL 0x00004000 -#define DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_SHIFT 14 -#define DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_MASK 0x00004000U +#define DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_SHIFT 14 +#define DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_MASK 0x00004000U -/*If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register - Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is - not associated with any particular command).*/ +/* +* If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + * bled and awurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + * serted anytime and as long as required which is independent of address h + * andshaking (it is not associated with any particular command). +*/ #undef DDRC_PCFGW_5_WR_PORT_URGENT_EN_DEFVAL #undef DDRC_PCFGW_5_WR_PORT_URGENT_EN_SHIFT #undef DDRC_PCFGW_5_WR_PORT_URGENT_EN_MASK -#define DDRC_PCFGW_5_WR_PORT_URGENT_EN_DEFVAL 0x00004000 -#define DDRC_PCFGW_5_WR_PORT_URGENT_EN_SHIFT 13 -#define DDRC_PCFGW_5_WR_PORT_URGENT_EN_MASK 0x00002000U +#define DDRC_PCFGW_5_WR_PORT_URGENT_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_5_WR_PORT_URGENT_EN_SHIFT 13 +#define DDRC_PCFGW_5_WR_PORT_URGENT_EN_MASK 0x00002000U -/*If set to 1, enables aging function for the write channel of the port.*/ +/* +* If set to 1, enables aging function for the write channel of the port. +*/ #undef DDRC_PCFGW_5_WR_PORT_AGING_EN_DEFVAL #undef DDRC_PCFGW_5_WR_PORT_AGING_EN_SHIFT #undef DDRC_PCFGW_5_WR_PORT_AGING_EN_MASK -#define DDRC_PCFGW_5_WR_PORT_AGING_EN_DEFVAL 0x00004000 -#define DDRC_PCFGW_5_WR_PORT_AGING_EN_SHIFT 12 -#define DDRC_PCFGW_5_WR_PORT_AGING_EN_MASK 0x00001000U +#define DDRC_PCFGW_5_WR_PORT_AGING_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_5_WR_PORT_AGING_EN_SHIFT 12 +#define DDRC_PCFGW_5_WR_PORT_AGING_EN_MASK 0x00001000U -/*Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each - rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port - s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0 - the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno - be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For - ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch - ng. Note: The two LSBs of this register field are tied internally to 2'b00.*/ +/* +* Determines the initial load value of write aging counters. These counter + * s will be parallel loaded after reset, or after each grant to the corres + * ponding port. The aging counters down-count every clock cycle where the + * port is requesting but not granted. The higher significant 5-bits of the + * write aging counter sets the initial priority of the write channel of a + * given port. Port's priority will increase as the higher significant 5-b + * its of the counter starts to decrease. When the aging counter becomes 0, + * the corresponding port channel will have the highest priority level. Fo + * r multi-port configurations, the aging counters cannot be used to set po + * rt priorities when external dynamic priority inputs (awqos) are enabled + * (timeout is still applicable). For single port configurations, the aging + * counters are only used when they timeout (become 0) to force read-write + * direction switching. Note: The two LSBs of this register field are tied + * internally to 2'b00. +*/ #undef DDRC_PCFGW_5_WR_PORT_PRIORITY_DEFVAL #undef DDRC_PCFGW_5_WR_PORT_PRIORITY_SHIFT #undef DDRC_PCFGW_5_WR_PORT_PRIORITY_MASK -#define DDRC_PCFGW_5_WR_PORT_PRIORITY_DEFVAL 0x00004000 -#define DDRC_PCFGW_5_WR_PORT_PRIORITY_SHIFT 0 -#define DDRC_PCFGW_5_WR_PORT_PRIORITY_MASK 0x000003FFU +#define DDRC_PCFGW_5_WR_PORT_PRIORITY_DEFVAL 0x00004000 +#define DDRC_PCFGW_5_WR_PORT_PRIORITY_SHIFT 0 +#define DDRC_PCFGW_5_WR_PORT_PRIORITY_MASK 0x000003FFU -/*Enables port n.*/ +/* +* Enables port n. +*/ #undef DDRC_PCTRL_5_PORT_EN_DEFVAL #undef DDRC_PCTRL_5_PORT_EN_SHIFT #undef DDRC_PCTRL_5_PORT_EN_MASK -#define DDRC_PCTRL_5_PORT_EN_DEFVAL -#define DDRC_PCTRL_5_PORT_EN_SHIFT 0 -#define DDRC_PCTRL_5_PORT_EN_MASK 0x00000001U +#define DDRC_PCTRL_5_PORT_EN_DEFVAL +#define DDRC_PCTRL_5_PORT_EN_SHIFT 0 +#define DDRC_PCTRL_5_PORT_EN_MASK 0x00000001U -/*This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf - gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is - disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/ +/* +* This bitfield indicates the traffic class of region 1. Valid values are: + * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + * maps to the blue address queue. In this case, valid values are 0: LPR a + * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. +*/ #undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_DEFVAL #undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_SHIFT #undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_MASK -#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_DEFVAL 0x00000000 -#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_SHIFT 20 -#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_MASK 0x00300000U +#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_DEFVAL 0x00000000 +#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_SHIFT 20 +#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_MASK 0x00300000U -/*This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi - urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i - disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/ +/* +* This bitfield indicates the traffic class of region 0. Valid values are: + * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + * maps to the blue address queue. In this case, valid values are: 0: LPR + * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. +*/ #undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_DEFVAL #undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_SHIFT #undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_MASK -#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_DEFVAL 0x00000000 -#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_SHIFT 16 -#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_MASK 0x00030000U +#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_DEFVAL 0x00000000 +#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_SHIFT 16 +#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_MASK 0x00030000U -/*Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d - al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio - ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc - values.*/ +/* +* Separation level1 indicating the end of region0 mapping; start of region + * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + * lues are used directly as port priorities, where the higher the value co + * rresponds to higher port priority. All of the map_level* registers must + * be set to distinct values. +*/ #undef DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_DEFVAL #undef DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_SHIFT #undef DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_MASK -#define DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_DEFVAL 0x00000000 -#define DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_SHIFT 0 -#define DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_MASK 0x0000000FU +#define DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_DEFVAL 0x00000000 +#define DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_SHIFT 0 +#define DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_MASK 0x0000000FU -/*Specifies the timeout value for transactions mapped to the red address queue.*/ +/* +* Specifies the timeout value for transactions mapped to the red address q + * ueue. +*/ #undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_DEFVAL #undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_SHIFT #undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_MASK -#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_DEFVAL 0x00000000 -#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_SHIFT 16 -#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_MASK 0x07FF0000U +#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_DEFVAL 0x00000000 +#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_SHIFT 16 +#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_MASK 0x07FF0000U -/*Specifies the timeout value for transactions mapped to the blue address queue.*/ +/* +* Specifies the timeout value for transactions mapped to the blue address + * queue. +*/ #undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_DEFVAL #undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_SHIFT #undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_MASK -#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_DEFVAL 0x00000000 -#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_SHIFT 0 -#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_MASK 0x000007FFU +#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_DEFVAL 0x00000000 +#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_SHIFT 0 +#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_MASK 0x000007FFU -/*This bitfield indicates the traffic class of region 1. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2 - VPW_EN = 0) and traffic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW traffic.*/ +/* +* This bitfield indicates the traffic class of region 1. Valid values are: + * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + * affic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW + * traffic. +*/ #undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_DEFVAL #undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_SHIFT #undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_MASK -#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_DEFVAL 0x00000000 -#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_SHIFT 20 -#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_MASK 0x00300000U +#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_DEFVAL 0x00000000 +#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_SHIFT 20 +#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_MASK 0x00300000U -/*This bitfield indicates the traffic class of region 0. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2 - VPW_EN = 0) and traffic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW traffic.*/ +/* +* This bitfield indicates the traffic class of region 0. Valid values are: + * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + * affic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW + * traffic. +*/ #undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_DEFVAL #undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_SHIFT #undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_MASK -#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_DEFVAL 0x00000000 -#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_SHIFT 16 -#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_MASK 0x00030000U +#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_DEFVAL 0x00000000 +#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_SHIFT 16 +#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_MASK 0x00030000U -/*Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 14 which c - rresponds to awqos. Note that for PA, awqos values are used directly as port priorities, where the higher the value correspon - s to higher port priority.*/ +/* +* Separation level indicating the end of region0 mapping; start of region0 + * is 0. Possible values for level1 are 0 to 14 which corresponds to awqos + * . Note that for PA, awqos values are used directly as port priorities, w + * here the higher the value corresponds to higher port priority. +*/ #undef DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_DEFVAL #undef DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_SHIFT #undef DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_MASK -#define DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_DEFVAL 0x00000000 -#define DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_SHIFT 0 -#define DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_MASK 0x0000000FU +#define DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_DEFVAL 0x00000000 +#define DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_SHIFT 0 +#define DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_MASK 0x0000000FU -/*Specifies the timeout value for write transactions.*/ +/* +* Specifies the timeout value for write transactions. +*/ #undef DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_DEFVAL #undef DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_SHIFT #undef DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_MASK -#define DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_DEFVAL -#define DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_SHIFT 0 -#define DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_MASK 0x000007FFU +#define DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_DEFVAL +#define DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_SHIFT 0 +#define DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_MASK 0x000007FFU -/*Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x] and araddr[UMCTL2_A_ADDRW-1:x] where x is determine - by the minimum block size parameter UMCTL2_SARMINSIZE: (x=log2(block size)).*/ +/* +* Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x + * ] and araddr[UMCTL2_A_ADDRW-1:x] where x is determined by the minimum bl + * ock size parameter UMCTL2_SARMINSIZE: (x=log2(block size)). +*/ #undef DDRC_SARBASE0_BASE_ADDR_DEFVAL #undef DDRC_SARBASE0_BASE_ADDR_SHIFT #undef DDRC_SARBASE0_BASE_ADDR_MASK -#define DDRC_SARBASE0_BASE_ADDR_DEFVAL -#define DDRC_SARBASE0_BASE_ADDR_SHIFT 0 -#define DDRC_SARBASE0_BASE_ADDR_MASK 0x000001FFU +#define DDRC_SARBASE0_BASE_ADDR_DEFVAL +#define DDRC_SARBASE0_BASE_ADDR_SHIFT 0 +#define DDRC_SARBASE0_BASE_ADDR_MASK 0x000001FFU -/*Number of blocks for address region n. This register determines the total size of the region in multiples of minimum block si - e as specified by the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded as number of blocks = nblocks + 1. - or example, if register is programmed to 0, region will have 1 block.*/ +/* +* Number of blocks for address region n. This register determines the tota + * l size of the region in multiples of minimum block size as specified by + * the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded + * as number of blocks = nblocks + 1. For example, if register is programme + * d to 0, region will have 1 block. +*/ #undef DDRC_SARSIZE0_NBLOCKS_DEFVAL #undef DDRC_SARSIZE0_NBLOCKS_SHIFT #undef DDRC_SARSIZE0_NBLOCKS_MASK -#define DDRC_SARSIZE0_NBLOCKS_DEFVAL -#define DDRC_SARSIZE0_NBLOCKS_SHIFT 0 -#define DDRC_SARSIZE0_NBLOCKS_MASK 0x000000FFU +#define DDRC_SARSIZE0_NBLOCKS_DEFVAL +#define DDRC_SARSIZE0_NBLOCKS_SHIFT 0 +#define DDRC_SARSIZE0_NBLOCKS_MASK 0x000000FFU -/*Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x] and araddr[UMCTL2_A_ADDRW-1:x] where x is determine - by the minimum block size parameter UMCTL2_SARMINSIZE: (x=log2(block size)).*/ +/* +* Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x + * ] and araddr[UMCTL2_A_ADDRW-1:x] where x is determined by the minimum bl + * ock size parameter UMCTL2_SARMINSIZE: (x=log2(block size)). +*/ #undef DDRC_SARBASE1_BASE_ADDR_DEFVAL #undef DDRC_SARBASE1_BASE_ADDR_SHIFT #undef DDRC_SARBASE1_BASE_ADDR_MASK -#define DDRC_SARBASE1_BASE_ADDR_DEFVAL -#define DDRC_SARBASE1_BASE_ADDR_SHIFT 0 -#define DDRC_SARBASE1_BASE_ADDR_MASK 0x000001FFU +#define DDRC_SARBASE1_BASE_ADDR_DEFVAL +#define DDRC_SARBASE1_BASE_ADDR_SHIFT 0 +#define DDRC_SARBASE1_BASE_ADDR_MASK 0x000001FFU -/*Number of blocks for address region n. This register determines the total size of the region in multiples of minimum block si - e as specified by the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded as number of blocks = nblocks + 1. - or example, if register is programmed to 0, region will have 1 block.*/ +/* +* Number of blocks for address region n. This register determines the tota + * l size of the region in multiples of minimum block size as specified by + * the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded + * as number of blocks = nblocks + 1. For example, if register is programme + * d to 0, region will have 1 block. +*/ #undef DDRC_SARSIZE1_NBLOCKS_DEFVAL #undef DDRC_SARSIZE1_NBLOCKS_SHIFT #undef DDRC_SARSIZE1_NBLOCKS_MASK -#define DDRC_SARSIZE1_NBLOCKS_DEFVAL -#define DDRC_SARSIZE1_NBLOCKS_SHIFT 0 -#define DDRC_SARSIZE1_NBLOCKS_MASK 0x000000FFU +#define DDRC_SARSIZE1_NBLOCKS_DEFVAL +#define DDRC_SARSIZE1_NBLOCKS_SHIFT 0 +#define DDRC_SARSIZE1_NBLOCKS_MASK 0x000000FFU -/*Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signa - s at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligne - , this timing parameter should be rounded up to the next integer value. Note that if using RDIMM, it is necessary to incremen - this parameter by RDIMM's extra cycle of latency in terms of DFI clock.*/ +/* +* Specifies the number of DFI clock cycles after an assertion or de-assert + * ion of the DFI control signals that the control signals at the PHY-DRAM + * interface reflect the assertion or de-assertion. If the DFI clock and th + * e memory clock are not phase-aligned, this timing parameter should be ro + * unded up to the next integer value. Note that if using RDIMM, it is nece + * ssary to increment this parameter by RDIMM's extra cycle of latency in t + * erms of DFI clock. +*/ #undef DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_DEFVAL #undef DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_SHIFT #undef DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_MASK -#define DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_DEFVAL 0x07020002 -#define DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_SHIFT 24 -#define DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_MASK 0x1F000000U +#define DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_DEFVAL 0x07020002 +#define DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_SHIFT 24 +#define DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_MASK 0x1F000000U -/*Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR or SDR values Selects whether value in DFITM - 0.dfi_t_rddata_en is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles R - fer to PHY specification for correct value.*/ +/* +* Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated u + * sing HDR or SDR values Selects whether value in DFITMG0.dfi_t_rddata_en + * is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles + * - 1 in terms of SDR clock cycles Refer to PHY specification for correct + * value. +*/ #undef DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_DEFVAL #undef DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_SHIFT #undef DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_MASK -#define DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_DEFVAL 0x07020002 -#define DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_SHIFT 23 -#define DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_MASK 0x00800000U +#define DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_DEFVAL 0x07020002 +#define DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_SHIFT 23 +#define DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_MASK 0x00800000U -/*Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. Refer to PHY spe - ification for correct value. This corresponds to the DFI parameter trddata_en. Note that, depending on the PHY, if using RDIM - , it may be necessary to use the value (CL + 1) in the calculation of trddata_en. This is to compensate for the extra cycle o - latency through the RDIMM. Unit: Clocks*/ +/* +* Time from the assertion of a read command on the DFI interface to the as + * sertion of the dfi_rddata_en signal. Refer to PHY specification for corr + * ect value. This corresponds to the DFI parameter trddata_en. Note that, + * depending on the PHY, if using RDIMM, it may be necessary to use the val + * ue (CL + 1) in the calculation of trddata_en. This is to compensate for + * the extra cycle of latency through the RDIMM. Unit: Clocks +*/ #undef DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_DEFVAL #undef DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_SHIFT #undef DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_MASK -#define DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_DEFVAL 0x07020002 -#define DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_SHIFT 16 -#define DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_MASK 0x003F0000U +#define DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_DEFVAL 0x07020002 +#define DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_SHIFT 16 +#define DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_MASK 0x003F0000U -/*Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using HDR or SDR values Selects whether value in DFITMG - .dfi_tphy_wrlat is in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.dfi_tphy_wrdata is in terms of SDR or - HDR clock cycles - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles Refer to PHY specification for correct val - e.*/ +/* +* Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated us + * ing HDR or SDR values Selects whether value in DFITMG0.dfi_tphy_wrlat is + * in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.df + * i_tphy_wrdata is in terms of SDR or HDR clock cycles - 0 in terms of HDR + * clock cycles - 1 in terms of SDR clock cycles Refer to PHY specificatio + * n for correct value. +*/ #undef DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_DEFVAL #undef DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_SHIFT #undef DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_MASK -#define DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_DEFVAL 0x07020002 -#define DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_SHIFT 15 -#define DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_MASK 0x00008000U +#define DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_DEFVAL 0x07020002 +#define DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_SHIFT 15 +#define DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_MASK 0x00008000U -/*Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on th - dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. N - te, max supported value is 8. Unit: Clocks*/ +/* +* Specifies the number of clock cycles between when dfi_wrdata_en is asser + * ted to when the associated write data is driven on the dfi_wrdata signal + * . This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY + * specification for correct value. Note, max supported value is 8. Unit: + * Clocks +*/ #undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_DEFVAL #undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_SHIFT #undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_MASK -#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_DEFVAL 0x07020002 -#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_SHIFT 8 -#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_MASK 0x00003F00U +#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_DEFVAL 0x07020002 +#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_SHIFT 8 +#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_MASK 0x00003F00U -/*Write latency Number of clocks from the write command to write data enable (dfi_wrdata_en). This corresponds to the DFI timin - parameter tphy_wrlat. Refer to PHY specification for correct value.Note that, depending on the PHY, if using RDIMM, it may b - necessary to use the value (CL + 1) in the calculation of tphy_wrlat. This is to compensate for the extra cycle of latency t - rough the RDIMM.*/ +/* +* Write latency Number of clocks from the write command to write data enab + * le (dfi_wrdata_en). This corresponds to the DFI timing parameter tphy_wr + * lat. Refer to PHY specification for correct value.Note that, depending o + * n the PHY, if using RDIMM, it may be necessary to use the value (CL + 1) + * in the calculation of tphy_wrlat. This is to compensate for the extra c + * ycle of latency through the RDIMM. +*/ #undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_DEFVAL #undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_SHIFT #undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_MASK -#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_DEFVAL 0x07020002 -#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_SHIFT 0 -#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_MASK 0x0000003FU +#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_DEFVAL 0x07020002 +#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_SHIFT 0 +#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_MASK 0x0000003FU -/*DDR block level reset inside of the DDR Sub System*/ +/* +* DDR block level reset inside of the DDR Sub System +*/ #undef CRF_APB_RST_DDR_SS_DDR_RESET_DEFVAL #undef CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT #undef CRF_APB_RST_DDR_SS_DDR_RESET_MASK -#define CRF_APB_RST_DDR_SS_DDR_RESET_DEFVAL 0x0000000F -#define CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT 3 -#define CRF_APB_RST_DDR_SS_DDR_RESET_MASK 0x00000008U +#define CRF_APB_RST_DDR_SS_DDR_RESET_DEFVAL 0x0000000F +#define CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT 3 +#define CRF_APB_RST_DDR_SS_DDR_RESET_MASK 0x00000008U -/*Address Copy*/ +/* +* APM block level reset inside of the DDR Sub System +*/ +#undef CRF_APB_RST_DDR_SS_APM_RESET_DEFVAL +#undef CRF_APB_RST_DDR_SS_APM_RESET_SHIFT +#undef CRF_APB_RST_DDR_SS_APM_RESET_MASK +#define CRF_APB_RST_DDR_SS_APM_RESET_DEFVAL 0x0000000F +#define CRF_APB_RST_DDR_SS_APM_RESET_SHIFT 2 +#define CRF_APB_RST_DDR_SS_APM_RESET_MASK 0x00000004U + +/* +* Address Copy +*/ #undef DDR_PHY_PGCR0_ADCP_DEFVAL #undef DDR_PHY_PGCR0_ADCP_SHIFT #undef DDR_PHY_PGCR0_ADCP_MASK -#define DDR_PHY_PGCR0_ADCP_DEFVAL 0x07001E00 -#define DDR_PHY_PGCR0_ADCP_SHIFT 31 -#define DDR_PHY_PGCR0_ADCP_MASK 0x80000000U +#define DDR_PHY_PGCR0_ADCP_DEFVAL 0x07001E00 +#define DDR_PHY_PGCR0_ADCP_SHIFT 31 +#define DDR_PHY_PGCR0_ADCP_MASK 0x80000000U -/*Reserved. Returns zeroes on reads.*/ +/* +* Reserved. Returns zeroes on reads. +*/ #undef DDR_PHY_PGCR0_RESERVED_30_27_DEFVAL #undef DDR_PHY_PGCR0_RESERVED_30_27_SHIFT #undef DDR_PHY_PGCR0_RESERVED_30_27_MASK -#define DDR_PHY_PGCR0_RESERVED_30_27_DEFVAL 0x07001E00 -#define DDR_PHY_PGCR0_RESERVED_30_27_SHIFT 27 -#define DDR_PHY_PGCR0_RESERVED_30_27_MASK 0x78000000U +#define DDR_PHY_PGCR0_RESERVED_30_27_DEFVAL 0x07001E00 +#define DDR_PHY_PGCR0_RESERVED_30_27_SHIFT 27 +#define DDR_PHY_PGCR0_RESERVED_30_27_MASK 0x78000000U -/*PHY FIFO Reset*/ +/* +* PHY FIFO Reset +*/ #undef DDR_PHY_PGCR0_PHYFRST_DEFVAL #undef DDR_PHY_PGCR0_PHYFRST_SHIFT #undef DDR_PHY_PGCR0_PHYFRST_MASK -#define DDR_PHY_PGCR0_PHYFRST_DEFVAL 0x07001E00 -#define DDR_PHY_PGCR0_PHYFRST_SHIFT 26 -#define DDR_PHY_PGCR0_PHYFRST_MASK 0x04000000U +#define DDR_PHY_PGCR0_PHYFRST_DEFVAL 0x07001E00 +#define DDR_PHY_PGCR0_PHYFRST_SHIFT 26 +#define DDR_PHY_PGCR0_PHYFRST_MASK 0x04000000U -/*Oscillator Mode Address/Command Delay Line Select*/ +/* +* Oscillator Mode Address/Command Delay Line Select +*/ #undef DDR_PHY_PGCR0_OSCACDL_DEFVAL #undef DDR_PHY_PGCR0_OSCACDL_SHIFT #undef DDR_PHY_PGCR0_OSCACDL_MASK -#define DDR_PHY_PGCR0_OSCACDL_DEFVAL 0x07001E00 -#define DDR_PHY_PGCR0_OSCACDL_SHIFT 24 -#define DDR_PHY_PGCR0_OSCACDL_MASK 0x03000000U +#define DDR_PHY_PGCR0_OSCACDL_DEFVAL 0x07001E00 +#define DDR_PHY_PGCR0_OSCACDL_SHIFT 24 +#define DDR_PHY_PGCR0_OSCACDL_MASK 0x03000000U -/*Reserved. Returns zeroes on reads.*/ +/* +* Reserved. Returns zeroes on reads. +*/ #undef DDR_PHY_PGCR0_RESERVED_23_19_DEFVAL #undef DDR_PHY_PGCR0_RESERVED_23_19_SHIFT #undef DDR_PHY_PGCR0_RESERVED_23_19_MASK -#define DDR_PHY_PGCR0_RESERVED_23_19_DEFVAL 0x07001E00 -#define DDR_PHY_PGCR0_RESERVED_23_19_SHIFT 19 -#define DDR_PHY_PGCR0_RESERVED_23_19_MASK 0x00F80000U +#define DDR_PHY_PGCR0_RESERVED_23_19_DEFVAL 0x07001E00 +#define DDR_PHY_PGCR0_RESERVED_23_19_SHIFT 19 +#define DDR_PHY_PGCR0_RESERVED_23_19_MASK 0x00F80000U -/*Digital Test Output Select*/ +/* +* Digital Test Output Select +*/ #undef DDR_PHY_PGCR0_DTOSEL_DEFVAL #undef DDR_PHY_PGCR0_DTOSEL_SHIFT #undef DDR_PHY_PGCR0_DTOSEL_MASK -#define DDR_PHY_PGCR0_DTOSEL_DEFVAL 0x07001E00 -#define DDR_PHY_PGCR0_DTOSEL_SHIFT 14 -#define DDR_PHY_PGCR0_DTOSEL_MASK 0x0007C000U +#define DDR_PHY_PGCR0_DTOSEL_DEFVAL 0x07001E00 +#define DDR_PHY_PGCR0_DTOSEL_SHIFT 14 +#define DDR_PHY_PGCR0_DTOSEL_MASK 0x0007C000U -/*Reserved. Returns zeroes on reads.*/ +/* +* Reserved. Returns zeroes on reads. +*/ #undef DDR_PHY_PGCR0_RESERVED_13_DEFVAL #undef DDR_PHY_PGCR0_RESERVED_13_SHIFT #undef DDR_PHY_PGCR0_RESERVED_13_MASK -#define DDR_PHY_PGCR0_RESERVED_13_DEFVAL 0x07001E00 -#define DDR_PHY_PGCR0_RESERVED_13_SHIFT 13 -#define DDR_PHY_PGCR0_RESERVED_13_MASK 0x00002000U +#define DDR_PHY_PGCR0_RESERVED_13_DEFVAL 0x07001E00 +#define DDR_PHY_PGCR0_RESERVED_13_SHIFT 13 +#define DDR_PHY_PGCR0_RESERVED_13_MASK 0x00002000U -/*Oscillator Mode Division*/ +/* +* Oscillator Mode Division +*/ #undef DDR_PHY_PGCR0_OSCDIV_DEFVAL #undef DDR_PHY_PGCR0_OSCDIV_SHIFT #undef DDR_PHY_PGCR0_OSCDIV_MASK -#define DDR_PHY_PGCR0_OSCDIV_DEFVAL 0x07001E00 -#define DDR_PHY_PGCR0_OSCDIV_SHIFT 9 -#define DDR_PHY_PGCR0_OSCDIV_MASK 0x00001E00U +#define DDR_PHY_PGCR0_OSCDIV_DEFVAL 0x07001E00 +#define DDR_PHY_PGCR0_OSCDIV_SHIFT 9 +#define DDR_PHY_PGCR0_OSCDIV_MASK 0x00001E00U -/*Oscillator Enable*/ +/* +* Oscillator Enable +*/ #undef DDR_PHY_PGCR0_OSCEN_DEFVAL #undef DDR_PHY_PGCR0_OSCEN_SHIFT #undef DDR_PHY_PGCR0_OSCEN_MASK -#define DDR_PHY_PGCR0_OSCEN_DEFVAL 0x07001E00 -#define DDR_PHY_PGCR0_OSCEN_SHIFT 8 -#define DDR_PHY_PGCR0_OSCEN_MASK 0x00000100U +#define DDR_PHY_PGCR0_OSCEN_DEFVAL 0x07001E00 +#define DDR_PHY_PGCR0_OSCEN_SHIFT 8 +#define DDR_PHY_PGCR0_OSCEN_MASK 0x00000100U -/*Reserved. Returns zeroes on reads.*/ +/* +* Reserved. Returns zeroes on reads. +*/ #undef DDR_PHY_PGCR0_RESERVED_7_0_DEFVAL #undef DDR_PHY_PGCR0_RESERVED_7_0_SHIFT #undef DDR_PHY_PGCR0_RESERVED_7_0_MASK -#define DDR_PHY_PGCR0_RESERVED_7_0_DEFVAL 0x07001E00 -#define DDR_PHY_PGCR0_RESERVED_7_0_SHIFT 0 -#define DDR_PHY_PGCR0_RESERVED_7_0_MASK 0x000000FFU +#define DDR_PHY_PGCR0_RESERVED_7_0_DEFVAL 0x07001E00 +#define DDR_PHY_PGCR0_RESERVED_7_0_SHIFT 0 +#define DDR_PHY_PGCR0_RESERVED_7_0_MASK 0x000000FFU -/*Clear Training Status Registers*/ +/* +* Clear Training Status Registers +*/ #undef DDR_PHY_PGCR2_CLRTSTAT_DEFVAL #undef DDR_PHY_PGCR2_CLRTSTAT_SHIFT #undef DDR_PHY_PGCR2_CLRTSTAT_MASK -#define DDR_PHY_PGCR2_CLRTSTAT_DEFVAL 0x00F12480 -#define DDR_PHY_PGCR2_CLRTSTAT_SHIFT 31 -#define DDR_PHY_PGCR2_CLRTSTAT_MASK 0x80000000U +#define DDR_PHY_PGCR2_CLRTSTAT_DEFVAL 0x00F12480 +#define DDR_PHY_PGCR2_CLRTSTAT_SHIFT 31 +#define DDR_PHY_PGCR2_CLRTSTAT_MASK 0x80000000U -/*Clear Impedance Calibration*/ +/* +* Clear Impedance Calibration +*/ #undef DDR_PHY_PGCR2_CLRZCAL_DEFVAL #undef DDR_PHY_PGCR2_CLRZCAL_SHIFT #undef DDR_PHY_PGCR2_CLRZCAL_MASK -#define DDR_PHY_PGCR2_CLRZCAL_DEFVAL 0x00F12480 -#define DDR_PHY_PGCR2_CLRZCAL_SHIFT 30 -#define DDR_PHY_PGCR2_CLRZCAL_MASK 0x40000000U +#define DDR_PHY_PGCR2_CLRZCAL_DEFVAL 0x00F12480 +#define DDR_PHY_PGCR2_CLRZCAL_SHIFT 30 +#define DDR_PHY_PGCR2_CLRZCAL_MASK 0x40000000U -/*Clear Parity Error*/ +/* +* Clear Parity Error +*/ #undef DDR_PHY_PGCR2_CLRPERR_DEFVAL #undef DDR_PHY_PGCR2_CLRPERR_SHIFT #undef DDR_PHY_PGCR2_CLRPERR_MASK -#define DDR_PHY_PGCR2_CLRPERR_DEFVAL 0x00F12480 -#define DDR_PHY_PGCR2_CLRPERR_SHIFT 29 -#define DDR_PHY_PGCR2_CLRPERR_MASK 0x20000000U +#define DDR_PHY_PGCR2_CLRPERR_DEFVAL 0x00F12480 +#define DDR_PHY_PGCR2_CLRPERR_SHIFT 29 +#define DDR_PHY_PGCR2_CLRPERR_MASK 0x20000000U -/*Initialization Complete Pin Configuration*/ +/* +* Initialization Complete Pin Configuration +*/ #undef DDR_PHY_PGCR2_ICPC_DEFVAL #undef DDR_PHY_PGCR2_ICPC_SHIFT #undef DDR_PHY_PGCR2_ICPC_MASK -#define DDR_PHY_PGCR2_ICPC_DEFVAL 0x00F12480 -#define DDR_PHY_PGCR2_ICPC_SHIFT 28 -#define DDR_PHY_PGCR2_ICPC_MASK 0x10000000U +#define DDR_PHY_PGCR2_ICPC_DEFVAL 0x00F12480 +#define DDR_PHY_PGCR2_ICPC_SHIFT 28 +#define DDR_PHY_PGCR2_ICPC_MASK 0x10000000U -/*Data Training PUB Mode Exit Timer*/ +/* +* Data Training PUB Mode Exit Timer +*/ #undef DDR_PHY_PGCR2_DTPMXTMR_DEFVAL #undef DDR_PHY_PGCR2_DTPMXTMR_SHIFT #undef DDR_PHY_PGCR2_DTPMXTMR_MASK -#define DDR_PHY_PGCR2_DTPMXTMR_DEFVAL 0x00F12480 -#define DDR_PHY_PGCR2_DTPMXTMR_SHIFT 20 -#define DDR_PHY_PGCR2_DTPMXTMR_MASK 0x0FF00000U +#define DDR_PHY_PGCR2_DTPMXTMR_DEFVAL 0x00F12480 +#define DDR_PHY_PGCR2_DTPMXTMR_SHIFT 20 +#define DDR_PHY_PGCR2_DTPMXTMR_MASK 0x0FF00000U -/*Initialization Bypass*/ +/* +* Initialization Bypass +*/ #undef DDR_PHY_PGCR2_INITFSMBYP_DEFVAL #undef DDR_PHY_PGCR2_INITFSMBYP_SHIFT #undef DDR_PHY_PGCR2_INITFSMBYP_MASK -#define DDR_PHY_PGCR2_INITFSMBYP_DEFVAL 0x00F12480 -#define DDR_PHY_PGCR2_INITFSMBYP_SHIFT 19 -#define DDR_PHY_PGCR2_INITFSMBYP_MASK 0x00080000U +#define DDR_PHY_PGCR2_INITFSMBYP_DEFVAL 0x00F12480 +#define DDR_PHY_PGCR2_INITFSMBYP_SHIFT 19 +#define DDR_PHY_PGCR2_INITFSMBYP_MASK 0x00080000U -/*PLL FSM Bypass*/ +/* +* PLL FSM Bypass +*/ #undef DDR_PHY_PGCR2_PLLFSMBYP_DEFVAL #undef DDR_PHY_PGCR2_PLLFSMBYP_SHIFT #undef DDR_PHY_PGCR2_PLLFSMBYP_MASK -#define DDR_PHY_PGCR2_PLLFSMBYP_DEFVAL 0x00F12480 -#define DDR_PHY_PGCR2_PLLFSMBYP_SHIFT 18 -#define DDR_PHY_PGCR2_PLLFSMBYP_MASK 0x00040000U +#define DDR_PHY_PGCR2_PLLFSMBYP_DEFVAL 0x00F12480 +#define DDR_PHY_PGCR2_PLLFSMBYP_SHIFT 18 +#define DDR_PHY_PGCR2_PLLFSMBYP_MASK 0x00040000U -/*Refresh Period*/ +/* +* Refresh Period +*/ #undef DDR_PHY_PGCR2_TREFPRD_DEFVAL #undef DDR_PHY_PGCR2_TREFPRD_SHIFT #undef DDR_PHY_PGCR2_TREFPRD_MASK -#define DDR_PHY_PGCR2_TREFPRD_DEFVAL 0x00F12480 -#define DDR_PHY_PGCR2_TREFPRD_SHIFT 0 -#define DDR_PHY_PGCR2_TREFPRD_MASK 0x0003FFFFU +#define DDR_PHY_PGCR2_TREFPRD_DEFVAL 0x00F12480 +#define DDR_PHY_PGCR2_TREFPRD_SHIFT 0 +#define DDR_PHY_PGCR2_TREFPRD_MASK 0x0003FFFFU -/*CKN Enable*/ +/* +* CKN Enable +*/ #undef DDR_PHY_PGCR3_CKNEN_DEFVAL #undef DDR_PHY_PGCR3_CKNEN_SHIFT #undef DDR_PHY_PGCR3_CKNEN_MASK -#define DDR_PHY_PGCR3_CKNEN_DEFVAL 0x55AA0080 -#define DDR_PHY_PGCR3_CKNEN_SHIFT 24 -#define DDR_PHY_PGCR3_CKNEN_MASK 0xFF000000U +#define DDR_PHY_PGCR3_CKNEN_DEFVAL 0x55AA0080 +#define DDR_PHY_PGCR3_CKNEN_SHIFT 24 +#define DDR_PHY_PGCR3_CKNEN_MASK 0xFF000000U -/*CK Enable*/ +/* +* CK Enable +*/ #undef DDR_PHY_PGCR3_CKEN_DEFVAL #undef DDR_PHY_PGCR3_CKEN_SHIFT #undef DDR_PHY_PGCR3_CKEN_MASK -#define DDR_PHY_PGCR3_CKEN_DEFVAL 0x55AA0080 -#define DDR_PHY_PGCR3_CKEN_SHIFT 16 -#define DDR_PHY_PGCR3_CKEN_MASK 0x00FF0000U +#define DDR_PHY_PGCR3_CKEN_DEFVAL 0x55AA0080 +#define DDR_PHY_PGCR3_CKEN_SHIFT 16 +#define DDR_PHY_PGCR3_CKEN_MASK 0x00FF0000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_PGCR3_RESERVED_15_DEFVAL #undef DDR_PHY_PGCR3_RESERVED_15_SHIFT #undef DDR_PHY_PGCR3_RESERVED_15_MASK -#define DDR_PHY_PGCR3_RESERVED_15_DEFVAL 0x55AA0080 -#define DDR_PHY_PGCR3_RESERVED_15_SHIFT 15 -#define DDR_PHY_PGCR3_RESERVED_15_MASK 0x00008000U +#define DDR_PHY_PGCR3_RESERVED_15_DEFVAL 0x55AA0080 +#define DDR_PHY_PGCR3_RESERVED_15_SHIFT 15 +#define DDR_PHY_PGCR3_RESERVED_15_MASK 0x00008000U -/*Enable Clock Gating for AC [0] ctl_rd_clk*/ +/* +* Enable Clock Gating for AC [0] ctl_rd_clk +*/ #undef DDR_PHY_PGCR3_GATEACRDCLK_DEFVAL #undef DDR_PHY_PGCR3_GATEACRDCLK_SHIFT #undef DDR_PHY_PGCR3_GATEACRDCLK_MASK -#define DDR_PHY_PGCR3_GATEACRDCLK_DEFVAL 0x55AA0080 -#define DDR_PHY_PGCR3_GATEACRDCLK_SHIFT 13 -#define DDR_PHY_PGCR3_GATEACRDCLK_MASK 0x00006000U +#define DDR_PHY_PGCR3_GATEACRDCLK_DEFVAL 0x55AA0080 +#define DDR_PHY_PGCR3_GATEACRDCLK_SHIFT 13 +#define DDR_PHY_PGCR3_GATEACRDCLK_MASK 0x00006000U -/*Enable Clock Gating for AC [0] ddr_clk*/ +/* +* Enable Clock Gating for AC [0] ddr_clk +*/ #undef DDR_PHY_PGCR3_GATEACDDRCLK_DEFVAL #undef DDR_PHY_PGCR3_GATEACDDRCLK_SHIFT #undef DDR_PHY_PGCR3_GATEACDDRCLK_MASK -#define DDR_PHY_PGCR3_GATEACDDRCLK_DEFVAL 0x55AA0080 -#define DDR_PHY_PGCR3_GATEACDDRCLK_SHIFT 11 -#define DDR_PHY_PGCR3_GATEACDDRCLK_MASK 0x00001800U +#define DDR_PHY_PGCR3_GATEACDDRCLK_DEFVAL 0x55AA0080 +#define DDR_PHY_PGCR3_GATEACDDRCLK_SHIFT 11 +#define DDR_PHY_PGCR3_GATEACDDRCLK_MASK 0x00001800U -/*Enable Clock Gating for AC [0] ctl_clk*/ +/* +* Enable Clock Gating for AC [0] ctl_clk +*/ #undef DDR_PHY_PGCR3_GATEACCTLCLK_DEFVAL #undef DDR_PHY_PGCR3_GATEACCTLCLK_SHIFT #undef DDR_PHY_PGCR3_GATEACCTLCLK_MASK -#define DDR_PHY_PGCR3_GATEACCTLCLK_DEFVAL 0x55AA0080 -#define DDR_PHY_PGCR3_GATEACCTLCLK_SHIFT 9 -#define DDR_PHY_PGCR3_GATEACCTLCLK_MASK 0x00000600U +#define DDR_PHY_PGCR3_GATEACCTLCLK_DEFVAL 0x55AA0080 +#define DDR_PHY_PGCR3_GATEACCTLCLK_SHIFT 9 +#define DDR_PHY_PGCR3_GATEACCTLCLK_MASK 0x00000600U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_PGCR3_RESERVED_8_DEFVAL #undef DDR_PHY_PGCR3_RESERVED_8_SHIFT #undef DDR_PHY_PGCR3_RESERVED_8_MASK -#define DDR_PHY_PGCR3_RESERVED_8_DEFVAL 0x55AA0080 -#define DDR_PHY_PGCR3_RESERVED_8_SHIFT 8 -#define DDR_PHY_PGCR3_RESERVED_8_MASK 0x00000100U +#define DDR_PHY_PGCR3_RESERVED_8_DEFVAL 0x55AA0080 +#define DDR_PHY_PGCR3_RESERVED_8_SHIFT 8 +#define DDR_PHY_PGCR3_RESERVED_8_MASK 0x00000100U -/*Controls DDL Bypass Modes*/ +/* +* Controls DDL Bypass Modes +*/ #undef DDR_PHY_PGCR3_DDLBYPMODE_DEFVAL #undef DDR_PHY_PGCR3_DDLBYPMODE_SHIFT #undef DDR_PHY_PGCR3_DDLBYPMODE_MASK -#define DDR_PHY_PGCR3_DDLBYPMODE_DEFVAL 0x55AA0080 -#define DDR_PHY_PGCR3_DDLBYPMODE_SHIFT 6 -#define DDR_PHY_PGCR3_DDLBYPMODE_MASK 0x000000C0U +#define DDR_PHY_PGCR3_DDLBYPMODE_DEFVAL 0x55AA0080 +#define DDR_PHY_PGCR3_DDLBYPMODE_SHIFT 6 +#define DDR_PHY_PGCR3_DDLBYPMODE_MASK 0x000000C0U -/*IO Loop-Back Select*/ +/* +* IO Loop-Back Select +*/ #undef DDR_PHY_PGCR3_IOLB_DEFVAL #undef DDR_PHY_PGCR3_IOLB_SHIFT #undef DDR_PHY_PGCR3_IOLB_MASK -#define DDR_PHY_PGCR3_IOLB_DEFVAL 0x55AA0080 -#define DDR_PHY_PGCR3_IOLB_SHIFT 5 -#define DDR_PHY_PGCR3_IOLB_MASK 0x00000020U +#define DDR_PHY_PGCR3_IOLB_DEFVAL 0x55AA0080 +#define DDR_PHY_PGCR3_IOLB_SHIFT 5 +#define DDR_PHY_PGCR3_IOLB_MASK 0x00000020U -/*AC Receive FIFO Read Mode*/ +/* +* AC Receive FIFO Read Mode +*/ #undef DDR_PHY_PGCR3_RDMODE_DEFVAL #undef DDR_PHY_PGCR3_RDMODE_SHIFT #undef DDR_PHY_PGCR3_RDMODE_MASK -#define DDR_PHY_PGCR3_RDMODE_DEFVAL 0x55AA0080 -#define DDR_PHY_PGCR3_RDMODE_SHIFT 3 -#define DDR_PHY_PGCR3_RDMODE_MASK 0x00000018U +#define DDR_PHY_PGCR3_RDMODE_DEFVAL 0x55AA0080 +#define DDR_PHY_PGCR3_RDMODE_SHIFT 3 +#define DDR_PHY_PGCR3_RDMODE_MASK 0x00000018U -/*Read FIFO Reset Disable*/ +/* +* Read FIFO Reset Disable +*/ #undef DDR_PHY_PGCR3_DISRST_DEFVAL #undef DDR_PHY_PGCR3_DISRST_SHIFT #undef DDR_PHY_PGCR3_DISRST_MASK -#define DDR_PHY_PGCR3_DISRST_DEFVAL 0x55AA0080 -#define DDR_PHY_PGCR3_DISRST_SHIFT 2 -#define DDR_PHY_PGCR3_DISRST_MASK 0x00000004U +#define DDR_PHY_PGCR3_DISRST_DEFVAL 0x55AA0080 +#define DDR_PHY_PGCR3_DISRST_SHIFT 2 +#define DDR_PHY_PGCR3_DISRST_MASK 0x00000004U -/*Clock Level when Clock Gating*/ +/* +* Clock Level when Clock Gating +*/ #undef DDR_PHY_PGCR3_CLKLEVEL_DEFVAL #undef DDR_PHY_PGCR3_CLKLEVEL_SHIFT #undef DDR_PHY_PGCR3_CLKLEVEL_MASK -#define DDR_PHY_PGCR3_CLKLEVEL_DEFVAL 0x55AA0080 -#define DDR_PHY_PGCR3_CLKLEVEL_SHIFT 0 -#define DDR_PHY_PGCR3_CLKLEVEL_MASK 0x00000003U +#define DDR_PHY_PGCR3_CLKLEVEL_DEFVAL 0x55AA0080 +#define DDR_PHY_PGCR3_CLKLEVEL_SHIFT 0 +#define DDR_PHY_PGCR3_CLKLEVEL_MASK 0x00000003U -/*Frequency B Ratio Term*/ +/* +* Frequency B Ratio Term +*/ #undef DDR_PHY_PGCR5_FRQBT_DEFVAL #undef DDR_PHY_PGCR5_FRQBT_SHIFT #undef DDR_PHY_PGCR5_FRQBT_MASK -#define DDR_PHY_PGCR5_FRQBT_DEFVAL 0x01010000 -#define DDR_PHY_PGCR5_FRQBT_SHIFT 24 -#define DDR_PHY_PGCR5_FRQBT_MASK 0xFF000000U +#define DDR_PHY_PGCR5_FRQBT_DEFVAL 0x01010000 +#define DDR_PHY_PGCR5_FRQBT_SHIFT 24 +#define DDR_PHY_PGCR5_FRQBT_MASK 0xFF000000U -/*Frequency A Ratio Term*/ +/* +* Frequency A Ratio Term +*/ #undef DDR_PHY_PGCR5_FRQAT_DEFVAL #undef DDR_PHY_PGCR5_FRQAT_SHIFT #undef DDR_PHY_PGCR5_FRQAT_MASK -#define DDR_PHY_PGCR5_FRQAT_DEFVAL 0x01010000 -#define DDR_PHY_PGCR5_FRQAT_SHIFT 16 -#define DDR_PHY_PGCR5_FRQAT_MASK 0x00FF0000U +#define DDR_PHY_PGCR5_FRQAT_DEFVAL 0x01010000 +#define DDR_PHY_PGCR5_FRQAT_SHIFT 16 +#define DDR_PHY_PGCR5_FRQAT_MASK 0x00FF0000U -/*DFI Disconnect Time Period*/ +/* +* DFI Disconnect Time Period +*/ #undef DDR_PHY_PGCR5_DISCNPERIOD_DEFVAL #undef DDR_PHY_PGCR5_DISCNPERIOD_SHIFT #undef DDR_PHY_PGCR5_DISCNPERIOD_MASK -#define DDR_PHY_PGCR5_DISCNPERIOD_DEFVAL 0x01010000 -#define DDR_PHY_PGCR5_DISCNPERIOD_SHIFT 8 -#define DDR_PHY_PGCR5_DISCNPERIOD_MASK 0x0000FF00U +#define DDR_PHY_PGCR5_DISCNPERIOD_DEFVAL 0x01010000 +#define DDR_PHY_PGCR5_DISCNPERIOD_SHIFT 8 +#define DDR_PHY_PGCR5_DISCNPERIOD_MASK 0x0000FF00U -/*Receiver bias core side control*/ +/* +* Receiver bias core side control +*/ #undef DDR_PHY_PGCR5_VREF_RBCTRL_DEFVAL #undef DDR_PHY_PGCR5_VREF_RBCTRL_SHIFT #undef DDR_PHY_PGCR5_VREF_RBCTRL_MASK -#define DDR_PHY_PGCR5_VREF_RBCTRL_DEFVAL 0x01010000 -#define DDR_PHY_PGCR5_VREF_RBCTRL_SHIFT 4 -#define DDR_PHY_PGCR5_VREF_RBCTRL_MASK 0x000000F0U +#define DDR_PHY_PGCR5_VREF_RBCTRL_DEFVAL 0x01010000 +#define DDR_PHY_PGCR5_VREF_RBCTRL_SHIFT 4 +#define DDR_PHY_PGCR5_VREF_RBCTRL_MASK 0x000000F0U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_PGCR5_RESERVED_3_DEFVAL #undef DDR_PHY_PGCR5_RESERVED_3_SHIFT #undef DDR_PHY_PGCR5_RESERVED_3_MASK -#define DDR_PHY_PGCR5_RESERVED_3_DEFVAL 0x01010000 -#define DDR_PHY_PGCR5_RESERVED_3_SHIFT 3 -#define DDR_PHY_PGCR5_RESERVED_3_MASK 0x00000008U +#define DDR_PHY_PGCR5_RESERVED_3_DEFVAL 0x01010000 +#define DDR_PHY_PGCR5_RESERVED_3_SHIFT 3 +#define DDR_PHY_PGCR5_RESERVED_3_MASK 0x00000008U -/*Internal VREF generator REFSEL ragne select*/ +/* +* Internal VREF generator REFSEL ragne select +*/ #undef DDR_PHY_PGCR5_DXREFISELRANGE_DEFVAL #undef DDR_PHY_PGCR5_DXREFISELRANGE_SHIFT #undef DDR_PHY_PGCR5_DXREFISELRANGE_MASK -#define DDR_PHY_PGCR5_DXREFISELRANGE_DEFVAL 0x01010000 -#define DDR_PHY_PGCR5_DXREFISELRANGE_SHIFT 2 -#define DDR_PHY_PGCR5_DXREFISELRANGE_MASK 0x00000004U +#define DDR_PHY_PGCR5_DXREFISELRANGE_DEFVAL 0x01010000 +#define DDR_PHY_PGCR5_DXREFISELRANGE_SHIFT 2 +#define DDR_PHY_PGCR5_DXREFISELRANGE_MASK 0x00000004U -/*DDL Page Read Write select*/ +/* +* DDL Page Read Write select +*/ #undef DDR_PHY_PGCR5_DDLPGACT_DEFVAL #undef DDR_PHY_PGCR5_DDLPGACT_SHIFT #undef DDR_PHY_PGCR5_DDLPGACT_MASK -#define DDR_PHY_PGCR5_DDLPGACT_DEFVAL 0x01010000 -#define DDR_PHY_PGCR5_DDLPGACT_SHIFT 1 -#define DDR_PHY_PGCR5_DDLPGACT_MASK 0x00000002U +#define DDR_PHY_PGCR5_DDLPGACT_DEFVAL 0x01010000 +#define DDR_PHY_PGCR5_DDLPGACT_SHIFT 1 +#define DDR_PHY_PGCR5_DDLPGACT_MASK 0x00000002U -/*DDL Page Read Write select*/ +/* +* DDL Page Read Write select +*/ #undef DDR_PHY_PGCR5_DDLPGRW_DEFVAL #undef DDR_PHY_PGCR5_DDLPGRW_SHIFT #undef DDR_PHY_PGCR5_DDLPGRW_MASK -#define DDR_PHY_PGCR5_DDLPGRW_DEFVAL 0x01010000 -#define DDR_PHY_PGCR5_DDLPGRW_SHIFT 0 -#define DDR_PHY_PGCR5_DDLPGRW_MASK 0x00000001U +#define DDR_PHY_PGCR5_DDLPGRW_DEFVAL 0x01010000 +#define DDR_PHY_PGCR5_DDLPGRW_SHIFT 0 +#define DDR_PHY_PGCR5_DDLPGRW_MASK 0x00000001U -/*PLL Power-Down Time*/ +/* +* PLL Power-Down Time +*/ #undef DDR_PHY_PTR0_TPLLPD_DEFVAL #undef DDR_PHY_PTR0_TPLLPD_SHIFT #undef DDR_PHY_PTR0_TPLLPD_MASK -#define DDR_PHY_PTR0_TPLLPD_DEFVAL 0x42C21590 -#define DDR_PHY_PTR0_TPLLPD_SHIFT 21 -#define DDR_PHY_PTR0_TPLLPD_MASK 0xFFE00000U +#define DDR_PHY_PTR0_TPLLPD_DEFVAL 0x42C21590 +#define DDR_PHY_PTR0_TPLLPD_SHIFT 21 +#define DDR_PHY_PTR0_TPLLPD_MASK 0xFFE00000U -/*PLL Gear Shift Time*/ +/* +* PLL Gear Shift Time +*/ #undef DDR_PHY_PTR0_TPLLGS_DEFVAL #undef DDR_PHY_PTR0_TPLLGS_SHIFT #undef DDR_PHY_PTR0_TPLLGS_MASK -#define DDR_PHY_PTR0_TPLLGS_DEFVAL 0x42C21590 -#define DDR_PHY_PTR0_TPLLGS_SHIFT 6 -#define DDR_PHY_PTR0_TPLLGS_MASK 0x001FFFC0U +#define DDR_PHY_PTR0_TPLLGS_DEFVAL 0x42C21590 +#define DDR_PHY_PTR0_TPLLGS_SHIFT 6 +#define DDR_PHY_PTR0_TPLLGS_MASK 0x001FFFC0U -/*PHY Reset Time*/ +/* +* PHY Reset Time +*/ #undef DDR_PHY_PTR0_TPHYRST_DEFVAL #undef DDR_PHY_PTR0_TPHYRST_SHIFT #undef DDR_PHY_PTR0_TPHYRST_MASK -#define DDR_PHY_PTR0_TPHYRST_DEFVAL 0x42C21590 -#define DDR_PHY_PTR0_TPHYRST_SHIFT 0 -#define DDR_PHY_PTR0_TPHYRST_MASK 0x0000003FU +#define DDR_PHY_PTR0_TPHYRST_DEFVAL 0x42C21590 +#define DDR_PHY_PTR0_TPHYRST_SHIFT 0 +#define DDR_PHY_PTR0_TPHYRST_MASK 0x0000003FU -/*PLL Lock Time*/ +/* +* PLL Lock Time +*/ #undef DDR_PHY_PTR1_TPLLLOCK_DEFVAL #undef DDR_PHY_PTR1_TPLLLOCK_SHIFT #undef DDR_PHY_PTR1_TPLLLOCK_MASK -#define DDR_PHY_PTR1_TPLLLOCK_DEFVAL 0xD05612C0 -#define DDR_PHY_PTR1_TPLLLOCK_SHIFT 16 -#define DDR_PHY_PTR1_TPLLLOCK_MASK 0xFFFF0000U +#define DDR_PHY_PTR1_TPLLLOCK_DEFVAL 0xD05612C0 +#define DDR_PHY_PTR1_TPLLLOCK_SHIFT 16 +#define DDR_PHY_PTR1_TPLLLOCK_MASK 0xFFFF0000U -/*Reserved. Returns zeroes on reads.*/ +/* +* Reserved. Returns zeroes on reads. +*/ #undef DDR_PHY_PTR1_RESERVED_15_13_DEFVAL #undef DDR_PHY_PTR1_RESERVED_15_13_SHIFT #undef DDR_PHY_PTR1_RESERVED_15_13_MASK -#define DDR_PHY_PTR1_RESERVED_15_13_DEFVAL 0xD05612C0 -#define DDR_PHY_PTR1_RESERVED_15_13_SHIFT 13 -#define DDR_PHY_PTR1_RESERVED_15_13_MASK 0x0000E000U +#define DDR_PHY_PTR1_RESERVED_15_13_DEFVAL 0xD05612C0 +#define DDR_PHY_PTR1_RESERVED_15_13_SHIFT 13 +#define DDR_PHY_PTR1_RESERVED_15_13_MASK 0x0000E000U -/*PLL Reset Time*/ +/* +* PLL Reset Time +*/ #undef DDR_PHY_PTR1_TPLLRST_DEFVAL #undef DDR_PHY_PTR1_TPLLRST_SHIFT #undef DDR_PHY_PTR1_TPLLRST_MASK -#define DDR_PHY_PTR1_TPLLRST_DEFVAL 0xD05612C0 -#define DDR_PHY_PTR1_TPLLRST_SHIFT 0 -#define DDR_PHY_PTR1_TPLLRST_MASK 0x00001FFFU +#define DDR_PHY_PTR1_TPLLRST_DEFVAL 0xD05612C0 +#define DDR_PHY_PTR1_TPLLRST_SHIFT 0 +#define DDR_PHY_PTR1_TPLLRST_MASK 0x00001FFFU -/*Reserved. Return zeroes on reads.*/ +/* +* PLL Bypass +*/ +#undef DDR_PHY_PLLCR0_PLLBYP_DEFVAL +#undef DDR_PHY_PLLCR0_PLLBYP_SHIFT +#undef DDR_PHY_PLLCR0_PLLBYP_MASK +#define DDR_PHY_PLLCR0_PLLBYP_DEFVAL 0x001C0000 +#define DDR_PHY_PLLCR0_PLLBYP_SHIFT 31 +#define DDR_PHY_PLLCR0_PLLBYP_MASK 0x80000000U + +/* +* PLL Reset +*/ +#undef DDR_PHY_PLLCR0_PLLRST_DEFVAL +#undef DDR_PHY_PLLCR0_PLLRST_SHIFT +#undef DDR_PHY_PLLCR0_PLLRST_MASK +#define DDR_PHY_PLLCR0_PLLRST_DEFVAL 0x001C0000 +#define DDR_PHY_PLLCR0_PLLRST_SHIFT 30 +#define DDR_PHY_PLLCR0_PLLRST_MASK 0x40000000U + +/* +* PLL Power Down +*/ +#undef DDR_PHY_PLLCR0_PLLPD_DEFVAL +#undef DDR_PHY_PLLCR0_PLLPD_SHIFT +#undef DDR_PHY_PLLCR0_PLLPD_MASK +#define DDR_PHY_PLLCR0_PLLPD_DEFVAL 0x001C0000 +#define DDR_PHY_PLLCR0_PLLPD_SHIFT 29 +#define DDR_PHY_PLLCR0_PLLPD_MASK 0x20000000U + +/* +* Reference Stop Mode +*/ +#undef DDR_PHY_PLLCR0_RSTOPM_DEFVAL +#undef DDR_PHY_PLLCR0_RSTOPM_SHIFT +#undef DDR_PHY_PLLCR0_RSTOPM_MASK +#define DDR_PHY_PLLCR0_RSTOPM_DEFVAL 0x001C0000 +#define DDR_PHY_PLLCR0_RSTOPM_SHIFT 28 +#define DDR_PHY_PLLCR0_RSTOPM_MASK 0x10000000U + +/* +* PLL Frequency Select +*/ +#undef DDR_PHY_PLLCR0_FRQSEL_DEFVAL +#undef DDR_PHY_PLLCR0_FRQSEL_SHIFT +#undef DDR_PHY_PLLCR0_FRQSEL_MASK +#define DDR_PHY_PLLCR0_FRQSEL_DEFVAL 0x001C0000 +#define DDR_PHY_PLLCR0_FRQSEL_SHIFT 24 +#define DDR_PHY_PLLCR0_FRQSEL_MASK 0x0F000000U + +/* +* Relock Mode +*/ +#undef DDR_PHY_PLLCR0_RLOCKM_DEFVAL +#undef DDR_PHY_PLLCR0_RLOCKM_SHIFT +#undef DDR_PHY_PLLCR0_RLOCKM_MASK +#define DDR_PHY_PLLCR0_RLOCKM_DEFVAL 0x001C0000 +#define DDR_PHY_PLLCR0_RLOCKM_SHIFT 23 +#define DDR_PHY_PLLCR0_RLOCKM_MASK 0x00800000U + +/* +* Charge Pump Proportional Current Control +*/ +#undef DDR_PHY_PLLCR0_CPPC_DEFVAL +#undef DDR_PHY_PLLCR0_CPPC_SHIFT +#undef DDR_PHY_PLLCR0_CPPC_MASK +#define DDR_PHY_PLLCR0_CPPC_DEFVAL 0x001C0000 +#define DDR_PHY_PLLCR0_CPPC_SHIFT 17 +#define DDR_PHY_PLLCR0_CPPC_MASK 0x007E0000U + +/* +* Charge Pump Integrating Current Control +*/ +#undef DDR_PHY_PLLCR0_CPIC_DEFVAL +#undef DDR_PHY_PLLCR0_CPIC_SHIFT +#undef DDR_PHY_PLLCR0_CPIC_MASK +#define DDR_PHY_PLLCR0_CPIC_DEFVAL 0x001C0000 +#define DDR_PHY_PLLCR0_CPIC_SHIFT 13 +#define DDR_PHY_PLLCR0_CPIC_MASK 0x0001E000U + +/* +* Gear Shift +*/ +#undef DDR_PHY_PLLCR0_GSHIFT_DEFVAL +#undef DDR_PHY_PLLCR0_GSHIFT_SHIFT +#undef DDR_PHY_PLLCR0_GSHIFT_MASK +#define DDR_PHY_PLLCR0_GSHIFT_DEFVAL 0x001C0000 +#define DDR_PHY_PLLCR0_GSHIFT_SHIFT 12 +#define DDR_PHY_PLLCR0_GSHIFT_MASK 0x00001000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_PLLCR0_RESERVED_11_9_DEFVAL +#undef DDR_PHY_PLLCR0_RESERVED_11_9_SHIFT +#undef DDR_PHY_PLLCR0_RESERVED_11_9_MASK +#define DDR_PHY_PLLCR0_RESERVED_11_9_DEFVAL 0x001C0000 +#define DDR_PHY_PLLCR0_RESERVED_11_9_SHIFT 9 +#define DDR_PHY_PLLCR0_RESERVED_11_9_MASK 0x00000E00U + +/* +* Analog Test Enable +*/ +#undef DDR_PHY_PLLCR0_ATOEN_DEFVAL +#undef DDR_PHY_PLLCR0_ATOEN_SHIFT +#undef DDR_PHY_PLLCR0_ATOEN_MASK +#define DDR_PHY_PLLCR0_ATOEN_DEFVAL 0x001C0000 +#define DDR_PHY_PLLCR0_ATOEN_SHIFT 8 +#define DDR_PHY_PLLCR0_ATOEN_MASK 0x00000100U + +/* +* Analog Test Control +*/ +#undef DDR_PHY_PLLCR0_ATC_DEFVAL +#undef DDR_PHY_PLLCR0_ATC_SHIFT +#undef DDR_PHY_PLLCR0_ATC_MASK +#define DDR_PHY_PLLCR0_ATC_DEFVAL 0x001C0000 +#define DDR_PHY_PLLCR0_ATC_SHIFT 4 +#define DDR_PHY_PLLCR0_ATC_MASK 0x000000F0U + +/* +* Digital Test Control +*/ +#undef DDR_PHY_PLLCR0_DTC_DEFVAL +#undef DDR_PHY_PLLCR0_DTC_SHIFT +#undef DDR_PHY_PLLCR0_DTC_MASK +#define DDR_PHY_PLLCR0_DTC_DEFVAL 0x001C0000 +#define DDR_PHY_PLLCR0_DTC_SHIFT 0 +#define DDR_PHY_PLLCR0_DTC_MASK 0x0000000FU + +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DSGCR_RESERVED_31_28_DEFVAL #undef DDR_PHY_DSGCR_RESERVED_31_28_SHIFT #undef DDR_PHY_DSGCR_RESERVED_31_28_MASK -#define DDR_PHY_DSGCR_RESERVED_31_28_DEFVAL 0x02A04101 -#define DDR_PHY_DSGCR_RESERVED_31_28_SHIFT 28 -#define DDR_PHY_DSGCR_RESERVED_31_28_MASK 0xF0000000U +#define DDR_PHY_DSGCR_RESERVED_31_28_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_RESERVED_31_28_SHIFT 28 +#define DDR_PHY_DSGCR_RESERVED_31_28_MASK 0xF0000000U -/*When RDBI enabled, this bit is used to select RDBI CL calculation, if it is 1b1, calculation will use RDBICL, otherwise use d - fault calculation.*/ +/* +* When RDBI enabled, this bit is used to select RDBI CL calculation, if it + * is 1b1, calculation will use RDBICL, otherwise use default calculation. +*/ #undef DDR_PHY_DSGCR_RDBICLSEL_DEFVAL #undef DDR_PHY_DSGCR_RDBICLSEL_SHIFT #undef DDR_PHY_DSGCR_RDBICLSEL_MASK -#define DDR_PHY_DSGCR_RDBICLSEL_DEFVAL 0x02A04101 -#define DDR_PHY_DSGCR_RDBICLSEL_SHIFT 27 -#define DDR_PHY_DSGCR_RDBICLSEL_MASK 0x08000000U +#define DDR_PHY_DSGCR_RDBICLSEL_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_RDBICLSEL_SHIFT 27 +#define DDR_PHY_DSGCR_RDBICLSEL_MASK 0x08000000U -/*When RDBI enabled, if RDBICLSEL is asserted, RDBI CL adjust using this value.*/ +/* +* When RDBI enabled, if RDBICLSEL is asserted, RDBI CL adjust using this v + * alue. +*/ #undef DDR_PHY_DSGCR_RDBICL_DEFVAL #undef DDR_PHY_DSGCR_RDBICL_SHIFT #undef DDR_PHY_DSGCR_RDBICL_MASK -#define DDR_PHY_DSGCR_RDBICL_DEFVAL 0x02A04101 -#define DDR_PHY_DSGCR_RDBICL_SHIFT 24 -#define DDR_PHY_DSGCR_RDBICL_MASK 0x07000000U +#define DDR_PHY_DSGCR_RDBICL_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_RDBICL_SHIFT 24 +#define DDR_PHY_DSGCR_RDBICL_MASK 0x07000000U -/*PHY Impedance Update Enable*/ +/* +* PHY Impedance Update Enable +*/ #undef DDR_PHY_DSGCR_PHYZUEN_DEFVAL #undef DDR_PHY_DSGCR_PHYZUEN_SHIFT #undef DDR_PHY_DSGCR_PHYZUEN_MASK -#define DDR_PHY_DSGCR_PHYZUEN_DEFVAL 0x02A04101 -#define DDR_PHY_DSGCR_PHYZUEN_SHIFT 23 -#define DDR_PHY_DSGCR_PHYZUEN_MASK 0x00800000U +#define DDR_PHY_DSGCR_PHYZUEN_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_PHYZUEN_SHIFT 23 +#define DDR_PHY_DSGCR_PHYZUEN_MASK 0x00800000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DSGCR_RESERVED_22_DEFVAL #undef DDR_PHY_DSGCR_RESERVED_22_SHIFT #undef DDR_PHY_DSGCR_RESERVED_22_MASK -#define DDR_PHY_DSGCR_RESERVED_22_DEFVAL 0x02A04101 -#define DDR_PHY_DSGCR_RESERVED_22_SHIFT 22 -#define DDR_PHY_DSGCR_RESERVED_22_MASK 0x00400000U +#define DDR_PHY_DSGCR_RESERVED_22_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_RESERVED_22_SHIFT 22 +#define DDR_PHY_DSGCR_RESERVED_22_MASK 0x00400000U -/*SDRAM Reset Output Enable*/ +/* +* SDRAM Reset Output Enable +*/ #undef DDR_PHY_DSGCR_RSTOE_DEFVAL #undef DDR_PHY_DSGCR_RSTOE_SHIFT #undef DDR_PHY_DSGCR_RSTOE_MASK -#define DDR_PHY_DSGCR_RSTOE_DEFVAL 0x02A04101 -#define DDR_PHY_DSGCR_RSTOE_SHIFT 21 -#define DDR_PHY_DSGCR_RSTOE_MASK 0x00200000U +#define DDR_PHY_DSGCR_RSTOE_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_RSTOE_SHIFT 21 +#define DDR_PHY_DSGCR_RSTOE_MASK 0x00200000U -/*Single Data Rate Mode*/ +/* +* Single Data Rate Mode +*/ #undef DDR_PHY_DSGCR_SDRMODE_DEFVAL #undef DDR_PHY_DSGCR_SDRMODE_SHIFT #undef DDR_PHY_DSGCR_SDRMODE_MASK -#define DDR_PHY_DSGCR_SDRMODE_DEFVAL 0x02A04101 -#define DDR_PHY_DSGCR_SDRMODE_SHIFT 19 -#define DDR_PHY_DSGCR_SDRMODE_MASK 0x00180000U +#define DDR_PHY_DSGCR_SDRMODE_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_SDRMODE_SHIFT 19 +#define DDR_PHY_DSGCR_SDRMODE_MASK 0x00180000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DSGCR_RESERVED_18_DEFVAL #undef DDR_PHY_DSGCR_RESERVED_18_SHIFT #undef DDR_PHY_DSGCR_RESERVED_18_MASK -#define DDR_PHY_DSGCR_RESERVED_18_DEFVAL 0x02A04101 -#define DDR_PHY_DSGCR_RESERVED_18_SHIFT 18 -#define DDR_PHY_DSGCR_RESERVED_18_MASK 0x00040000U +#define DDR_PHY_DSGCR_RESERVED_18_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_RESERVED_18_SHIFT 18 +#define DDR_PHY_DSGCR_RESERVED_18_MASK 0x00040000U -/*ATO Analog Test Enable*/ +/* +* ATO Analog Test Enable +*/ #undef DDR_PHY_DSGCR_ATOAE_DEFVAL #undef DDR_PHY_DSGCR_ATOAE_SHIFT #undef DDR_PHY_DSGCR_ATOAE_MASK -#define DDR_PHY_DSGCR_ATOAE_DEFVAL 0x02A04101 -#define DDR_PHY_DSGCR_ATOAE_SHIFT 17 -#define DDR_PHY_DSGCR_ATOAE_MASK 0x00020000U +#define DDR_PHY_DSGCR_ATOAE_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_ATOAE_SHIFT 17 +#define DDR_PHY_DSGCR_ATOAE_MASK 0x00020000U -/*DTO Output Enable*/ +/* +* DTO Output Enable +*/ #undef DDR_PHY_DSGCR_DTOOE_DEFVAL #undef DDR_PHY_DSGCR_DTOOE_SHIFT #undef DDR_PHY_DSGCR_DTOOE_MASK -#define DDR_PHY_DSGCR_DTOOE_DEFVAL 0x02A04101 -#define DDR_PHY_DSGCR_DTOOE_SHIFT 16 -#define DDR_PHY_DSGCR_DTOOE_MASK 0x00010000U +#define DDR_PHY_DSGCR_DTOOE_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_DTOOE_SHIFT 16 +#define DDR_PHY_DSGCR_DTOOE_MASK 0x00010000U -/*DTO I/O Mode*/ +/* +* DTO I/O Mode +*/ #undef DDR_PHY_DSGCR_DTOIOM_DEFVAL #undef DDR_PHY_DSGCR_DTOIOM_SHIFT #undef DDR_PHY_DSGCR_DTOIOM_MASK -#define DDR_PHY_DSGCR_DTOIOM_DEFVAL 0x02A04101 -#define DDR_PHY_DSGCR_DTOIOM_SHIFT 15 -#define DDR_PHY_DSGCR_DTOIOM_MASK 0x00008000U +#define DDR_PHY_DSGCR_DTOIOM_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_DTOIOM_SHIFT 15 +#define DDR_PHY_DSGCR_DTOIOM_MASK 0x00008000U -/*DTO Power Down Receiver*/ +/* +* DTO Power Down Receiver +*/ #undef DDR_PHY_DSGCR_DTOPDR_DEFVAL #undef DDR_PHY_DSGCR_DTOPDR_SHIFT #undef DDR_PHY_DSGCR_DTOPDR_MASK -#define DDR_PHY_DSGCR_DTOPDR_DEFVAL 0x02A04101 -#define DDR_PHY_DSGCR_DTOPDR_SHIFT 14 -#define DDR_PHY_DSGCR_DTOPDR_MASK 0x00004000U +#define DDR_PHY_DSGCR_DTOPDR_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_DTOPDR_SHIFT 14 +#define DDR_PHY_DSGCR_DTOPDR_MASK 0x00004000U -/*Reserved. Return zeroes on reads*/ +/* +* Reserved. Return zeroes on reads +*/ #undef DDR_PHY_DSGCR_RESERVED_13_DEFVAL #undef DDR_PHY_DSGCR_RESERVED_13_SHIFT #undef DDR_PHY_DSGCR_RESERVED_13_MASK -#define DDR_PHY_DSGCR_RESERVED_13_DEFVAL 0x02A04101 -#define DDR_PHY_DSGCR_RESERVED_13_SHIFT 13 -#define DDR_PHY_DSGCR_RESERVED_13_MASK 0x00002000U +#define DDR_PHY_DSGCR_RESERVED_13_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_RESERVED_13_SHIFT 13 +#define DDR_PHY_DSGCR_RESERVED_13_MASK 0x00002000U -/*DTO On-Die Termination*/ +/* +* DTO On-Die Termination +*/ #undef DDR_PHY_DSGCR_DTOODT_DEFVAL #undef DDR_PHY_DSGCR_DTOODT_SHIFT #undef DDR_PHY_DSGCR_DTOODT_MASK -#define DDR_PHY_DSGCR_DTOODT_DEFVAL 0x02A04101 -#define DDR_PHY_DSGCR_DTOODT_SHIFT 12 -#define DDR_PHY_DSGCR_DTOODT_MASK 0x00001000U +#define DDR_PHY_DSGCR_DTOODT_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_DTOODT_SHIFT 12 +#define DDR_PHY_DSGCR_DTOODT_MASK 0x00001000U -/*PHY Update Acknowledge Delay*/ +/* +* PHY Update Acknowledge Delay +*/ #undef DDR_PHY_DSGCR_PUAD_DEFVAL #undef DDR_PHY_DSGCR_PUAD_SHIFT #undef DDR_PHY_DSGCR_PUAD_MASK -#define DDR_PHY_DSGCR_PUAD_DEFVAL 0x02A04101 -#define DDR_PHY_DSGCR_PUAD_SHIFT 6 -#define DDR_PHY_DSGCR_PUAD_MASK 0x00000FC0U +#define DDR_PHY_DSGCR_PUAD_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_PUAD_SHIFT 6 +#define DDR_PHY_DSGCR_PUAD_MASK 0x00000FC0U -/*Controller Update Acknowledge Enable*/ +/* +* Controller Update Acknowledge Enable +*/ #undef DDR_PHY_DSGCR_CUAEN_DEFVAL #undef DDR_PHY_DSGCR_CUAEN_SHIFT #undef DDR_PHY_DSGCR_CUAEN_MASK -#define DDR_PHY_DSGCR_CUAEN_DEFVAL 0x02A04101 -#define DDR_PHY_DSGCR_CUAEN_SHIFT 5 -#define DDR_PHY_DSGCR_CUAEN_MASK 0x00000020U +#define DDR_PHY_DSGCR_CUAEN_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_CUAEN_SHIFT 5 +#define DDR_PHY_DSGCR_CUAEN_MASK 0x00000020U -/*Reserved. Return zeroes on reads*/ +/* +* Reserved. Return zeroes on reads +*/ #undef DDR_PHY_DSGCR_RESERVED_4_3_DEFVAL #undef DDR_PHY_DSGCR_RESERVED_4_3_SHIFT #undef DDR_PHY_DSGCR_RESERVED_4_3_MASK -#define DDR_PHY_DSGCR_RESERVED_4_3_DEFVAL 0x02A04101 -#define DDR_PHY_DSGCR_RESERVED_4_3_SHIFT 3 -#define DDR_PHY_DSGCR_RESERVED_4_3_MASK 0x00000018U +#define DDR_PHY_DSGCR_RESERVED_4_3_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_RESERVED_4_3_SHIFT 3 +#define DDR_PHY_DSGCR_RESERVED_4_3_MASK 0x00000018U -/*Controller Impedance Update Enable*/ +/* +* Controller Impedance Update Enable +*/ #undef DDR_PHY_DSGCR_CTLZUEN_DEFVAL #undef DDR_PHY_DSGCR_CTLZUEN_SHIFT #undef DDR_PHY_DSGCR_CTLZUEN_MASK -#define DDR_PHY_DSGCR_CTLZUEN_DEFVAL 0x02A04101 -#define DDR_PHY_DSGCR_CTLZUEN_SHIFT 2 -#define DDR_PHY_DSGCR_CTLZUEN_MASK 0x00000004U +#define DDR_PHY_DSGCR_CTLZUEN_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_CTLZUEN_SHIFT 2 +#define DDR_PHY_DSGCR_CTLZUEN_MASK 0x00000004U -/*Reserved. Return zeroes on reads*/ +/* +* Reserved. Return zeroes on reads +*/ #undef DDR_PHY_DSGCR_RESERVED_1_DEFVAL #undef DDR_PHY_DSGCR_RESERVED_1_SHIFT #undef DDR_PHY_DSGCR_RESERVED_1_MASK -#define DDR_PHY_DSGCR_RESERVED_1_DEFVAL 0x02A04101 -#define DDR_PHY_DSGCR_RESERVED_1_SHIFT 1 -#define DDR_PHY_DSGCR_RESERVED_1_MASK 0x00000002U +#define DDR_PHY_DSGCR_RESERVED_1_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_RESERVED_1_SHIFT 1 +#define DDR_PHY_DSGCR_RESERVED_1_MASK 0x00000002U -/*PHY Update Request Enable*/ +/* +* PHY Update Request Enable +*/ #undef DDR_PHY_DSGCR_PUREN_DEFVAL #undef DDR_PHY_DSGCR_PUREN_SHIFT #undef DDR_PHY_DSGCR_PUREN_MASK -#define DDR_PHY_DSGCR_PUREN_DEFVAL 0x02A04101 -#define DDR_PHY_DSGCR_PUREN_SHIFT 0 -#define DDR_PHY_DSGCR_PUREN_MASK 0x00000001U +#define DDR_PHY_DSGCR_PUREN_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_PUREN_SHIFT 0 +#define DDR_PHY_DSGCR_PUREN_MASK 0x00000001U -/*DDR4 Gear Down Timing.*/ +/* +* General Purpose Register 0 +*/ +#undef DDR_PHY_GPR0_GPR0_DEFVAL +#undef DDR_PHY_GPR0_GPR0_SHIFT +#undef DDR_PHY_GPR0_GPR0_MASK +#define DDR_PHY_GPR0_GPR0_DEFVAL +#define DDR_PHY_GPR0_GPR0_SHIFT 0 +#define DDR_PHY_GPR0_GPR0_MASK 0xFFFFFFFFU + +/* +* DDR4 Gear Down Timing. +*/ #undef DDR_PHY_DCR_GEARDN_DEFVAL #undef DDR_PHY_DCR_GEARDN_SHIFT #undef DDR_PHY_DCR_GEARDN_MASK -#define DDR_PHY_DCR_GEARDN_DEFVAL 0x0000040D -#define DDR_PHY_DCR_GEARDN_SHIFT 31 -#define DDR_PHY_DCR_GEARDN_MASK 0x80000000U +#define DDR_PHY_DCR_GEARDN_DEFVAL 0x0000040D +#define DDR_PHY_DCR_GEARDN_SHIFT 31 +#define DDR_PHY_DCR_GEARDN_MASK 0x80000000U -/*Un-used Bank Group*/ +/* +* Un-used Bank Group +*/ #undef DDR_PHY_DCR_UBG_DEFVAL #undef DDR_PHY_DCR_UBG_SHIFT #undef DDR_PHY_DCR_UBG_MASK -#define DDR_PHY_DCR_UBG_DEFVAL 0x0000040D -#define DDR_PHY_DCR_UBG_SHIFT 30 -#define DDR_PHY_DCR_UBG_MASK 0x40000000U +#define DDR_PHY_DCR_UBG_DEFVAL 0x0000040D +#define DDR_PHY_DCR_UBG_SHIFT 30 +#define DDR_PHY_DCR_UBG_MASK 0x40000000U -/*Un-buffered DIMM Address Mirroring*/ +/* +* Un-buffered DIMM Address Mirroring +*/ #undef DDR_PHY_DCR_UDIMM_DEFVAL #undef DDR_PHY_DCR_UDIMM_SHIFT #undef DDR_PHY_DCR_UDIMM_MASK -#define DDR_PHY_DCR_UDIMM_DEFVAL 0x0000040D -#define DDR_PHY_DCR_UDIMM_SHIFT 29 -#define DDR_PHY_DCR_UDIMM_MASK 0x20000000U +#define DDR_PHY_DCR_UDIMM_DEFVAL 0x0000040D +#define DDR_PHY_DCR_UDIMM_SHIFT 29 +#define DDR_PHY_DCR_UDIMM_MASK 0x20000000U -/*DDR 2T Timing*/ +/* +* DDR 2T Timing +*/ #undef DDR_PHY_DCR_DDR2T_DEFVAL #undef DDR_PHY_DCR_DDR2T_SHIFT #undef DDR_PHY_DCR_DDR2T_MASK -#define DDR_PHY_DCR_DDR2T_DEFVAL 0x0000040D -#define DDR_PHY_DCR_DDR2T_SHIFT 28 -#define DDR_PHY_DCR_DDR2T_MASK 0x10000000U +#define DDR_PHY_DCR_DDR2T_DEFVAL 0x0000040D +#define DDR_PHY_DCR_DDR2T_SHIFT 28 +#define DDR_PHY_DCR_DDR2T_MASK 0x10000000U -/*No Simultaneous Rank Access*/ +/* +* No Simultaneous Rank Access +*/ #undef DDR_PHY_DCR_NOSRA_DEFVAL #undef DDR_PHY_DCR_NOSRA_SHIFT #undef DDR_PHY_DCR_NOSRA_MASK -#define DDR_PHY_DCR_NOSRA_DEFVAL 0x0000040D -#define DDR_PHY_DCR_NOSRA_SHIFT 27 -#define DDR_PHY_DCR_NOSRA_MASK 0x08000000U +#define DDR_PHY_DCR_NOSRA_DEFVAL 0x0000040D +#define DDR_PHY_DCR_NOSRA_SHIFT 27 +#define DDR_PHY_DCR_NOSRA_MASK 0x08000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DCR_RESERVED_26_18_DEFVAL #undef DDR_PHY_DCR_RESERVED_26_18_SHIFT #undef DDR_PHY_DCR_RESERVED_26_18_MASK -#define DDR_PHY_DCR_RESERVED_26_18_DEFVAL 0x0000040D -#define DDR_PHY_DCR_RESERVED_26_18_SHIFT 18 -#define DDR_PHY_DCR_RESERVED_26_18_MASK 0x07FC0000U +#define DDR_PHY_DCR_RESERVED_26_18_DEFVAL 0x0000040D +#define DDR_PHY_DCR_RESERVED_26_18_SHIFT 18 +#define DDR_PHY_DCR_RESERVED_26_18_MASK 0x07FC0000U -/*Byte Mask*/ +/* +* Byte Mask +*/ #undef DDR_PHY_DCR_BYTEMASK_DEFVAL #undef DDR_PHY_DCR_BYTEMASK_SHIFT #undef DDR_PHY_DCR_BYTEMASK_MASK -#define DDR_PHY_DCR_BYTEMASK_DEFVAL 0x0000040D -#define DDR_PHY_DCR_BYTEMASK_SHIFT 10 -#define DDR_PHY_DCR_BYTEMASK_MASK 0x0003FC00U +#define DDR_PHY_DCR_BYTEMASK_DEFVAL 0x0000040D +#define DDR_PHY_DCR_BYTEMASK_SHIFT 10 +#define DDR_PHY_DCR_BYTEMASK_MASK 0x0003FC00U -/*DDR Type*/ +/* +* DDR Type +*/ #undef DDR_PHY_DCR_DDRTYPE_DEFVAL #undef DDR_PHY_DCR_DDRTYPE_SHIFT #undef DDR_PHY_DCR_DDRTYPE_MASK -#define DDR_PHY_DCR_DDRTYPE_DEFVAL 0x0000040D -#define DDR_PHY_DCR_DDRTYPE_SHIFT 8 -#define DDR_PHY_DCR_DDRTYPE_MASK 0x00000300U +#define DDR_PHY_DCR_DDRTYPE_DEFVAL 0x0000040D +#define DDR_PHY_DCR_DDRTYPE_SHIFT 8 +#define DDR_PHY_DCR_DDRTYPE_MASK 0x00000300U -/*Multi-Purpose Register (MPR) DQ (DDR3 Only)*/ +/* +* Multi-Purpose Register (MPR) DQ (DDR3 Only) +*/ #undef DDR_PHY_DCR_MPRDQ_DEFVAL #undef DDR_PHY_DCR_MPRDQ_SHIFT #undef DDR_PHY_DCR_MPRDQ_MASK -#define DDR_PHY_DCR_MPRDQ_DEFVAL 0x0000040D -#define DDR_PHY_DCR_MPRDQ_SHIFT 7 -#define DDR_PHY_DCR_MPRDQ_MASK 0x00000080U +#define DDR_PHY_DCR_MPRDQ_DEFVAL 0x0000040D +#define DDR_PHY_DCR_MPRDQ_SHIFT 7 +#define DDR_PHY_DCR_MPRDQ_MASK 0x00000080U -/*Primary DQ (DDR3 Only)*/ +/* +* Primary DQ (DDR3 Only) +*/ #undef DDR_PHY_DCR_PDQ_DEFVAL #undef DDR_PHY_DCR_PDQ_SHIFT #undef DDR_PHY_DCR_PDQ_MASK -#define DDR_PHY_DCR_PDQ_DEFVAL 0x0000040D -#define DDR_PHY_DCR_PDQ_SHIFT 4 -#define DDR_PHY_DCR_PDQ_MASK 0x00000070U +#define DDR_PHY_DCR_PDQ_DEFVAL 0x0000040D +#define DDR_PHY_DCR_PDQ_SHIFT 4 +#define DDR_PHY_DCR_PDQ_MASK 0x00000070U -/*DDR 8-Bank*/ +/* +* DDR 8-Bank +*/ #undef DDR_PHY_DCR_DDR8BNK_DEFVAL #undef DDR_PHY_DCR_DDR8BNK_SHIFT #undef DDR_PHY_DCR_DDR8BNK_MASK -#define DDR_PHY_DCR_DDR8BNK_DEFVAL 0x0000040D -#define DDR_PHY_DCR_DDR8BNK_SHIFT 3 -#define DDR_PHY_DCR_DDR8BNK_MASK 0x00000008U +#define DDR_PHY_DCR_DDR8BNK_DEFVAL 0x0000040D +#define DDR_PHY_DCR_DDR8BNK_SHIFT 3 +#define DDR_PHY_DCR_DDR8BNK_MASK 0x00000008U -/*DDR Mode*/ +/* +* DDR Mode +*/ #undef DDR_PHY_DCR_DDRMD_DEFVAL #undef DDR_PHY_DCR_DDRMD_SHIFT #undef DDR_PHY_DCR_DDRMD_MASK -#define DDR_PHY_DCR_DDRMD_DEFVAL 0x0000040D -#define DDR_PHY_DCR_DDRMD_SHIFT 0 -#define DDR_PHY_DCR_DDRMD_MASK 0x00000007U +#define DDR_PHY_DCR_DDRMD_DEFVAL 0x0000040D +#define DDR_PHY_DCR_DDRMD_SHIFT 0 +#define DDR_PHY_DCR_DDRMD_MASK 0x00000007U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR0_RESERVED_31_29_DEFVAL #undef DDR_PHY_DTPR0_RESERVED_31_29_SHIFT #undef DDR_PHY_DTPR0_RESERVED_31_29_MASK -#define DDR_PHY_DTPR0_RESERVED_31_29_DEFVAL 0x105A2D08 -#define DDR_PHY_DTPR0_RESERVED_31_29_SHIFT 29 -#define DDR_PHY_DTPR0_RESERVED_31_29_MASK 0xE0000000U +#define DDR_PHY_DTPR0_RESERVED_31_29_DEFVAL 0x105A2D08 +#define DDR_PHY_DTPR0_RESERVED_31_29_SHIFT 29 +#define DDR_PHY_DTPR0_RESERVED_31_29_MASK 0xE0000000U -/*Activate to activate command delay (different banks)*/ +/* +* Activate to activate command delay (different banks) +*/ #undef DDR_PHY_DTPR0_TRRD_DEFVAL #undef DDR_PHY_DTPR0_TRRD_SHIFT #undef DDR_PHY_DTPR0_TRRD_MASK -#define DDR_PHY_DTPR0_TRRD_DEFVAL 0x105A2D08 -#define DDR_PHY_DTPR0_TRRD_SHIFT 24 -#define DDR_PHY_DTPR0_TRRD_MASK 0x1F000000U +#define DDR_PHY_DTPR0_TRRD_DEFVAL 0x105A2D08 +#define DDR_PHY_DTPR0_TRRD_SHIFT 24 +#define DDR_PHY_DTPR0_TRRD_MASK 0x1F000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR0_RESERVED_23_DEFVAL #undef DDR_PHY_DTPR0_RESERVED_23_SHIFT #undef DDR_PHY_DTPR0_RESERVED_23_MASK -#define DDR_PHY_DTPR0_RESERVED_23_DEFVAL 0x105A2D08 -#define DDR_PHY_DTPR0_RESERVED_23_SHIFT 23 -#define DDR_PHY_DTPR0_RESERVED_23_MASK 0x00800000U +#define DDR_PHY_DTPR0_RESERVED_23_DEFVAL 0x105A2D08 +#define DDR_PHY_DTPR0_RESERVED_23_SHIFT 23 +#define DDR_PHY_DTPR0_RESERVED_23_MASK 0x00800000U -/*Activate to precharge command delay*/ +/* +* Activate to precharge command delay +*/ #undef DDR_PHY_DTPR0_TRAS_DEFVAL #undef DDR_PHY_DTPR0_TRAS_SHIFT #undef DDR_PHY_DTPR0_TRAS_MASK -#define DDR_PHY_DTPR0_TRAS_DEFVAL 0x105A2D08 -#define DDR_PHY_DTPR0_TRAS_SHIFT 16 -#define DDR_PHY_DTPR0_TRAS_MASK 0x007F0000U +#define DDR_PHY_DTPR0_TRAS_DEFVAL 0x105A2D08 +#define DDR_PHY_DTPR0_TRAS_SHIFT 16 +#define DDR_PHY_DTPR0_TRAS_MASK 0x007F0000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR0_RESERVED_15_DEFVAL #undef DDR_PHY_DTPR0_RESERVED_15_SHIFT #undef DDR_PHY_DTPR0_RESERVED_15_MASK -#define DDR_PHY_DTPR0_RESERVED_15_DEFVAL 0x105A2D08 -#define DDR_PHY_DTPR0_RESERVED_15_SHIFT 15 -#define DDR_PHY_DTPR0_RESERVED_15_MASK 0x00008000U +#define DDR_PHY_DTPR0_RESERVED_15_DEFVAL 0x105A2D08 +#define DDR_PHY_DTPR0_RESERVED_15_SHIFT 15 +#define DDR_PHY_DTPR0_RESERVED_15_MASK 0x00008000U -/*Precharge command period*/ +/* +* Precharge command period +*/ #undef DDR_PHY_DTPR0_TRP_DEFVAL #undef DDR_PHY_DTPR0_TRP_SHIFT #undef DDR_PHY_DTPR0_TRP_MASK -#define DDR_PHY_DTPR0_TRP_DEFVAL 0x105A2D08 -#define DDR_PHY_DTPR0_TRP_SHIFT 8 -#define DDR_PHY_DTPR0_TRP_MASK 0x00007F00U +#define DDR_PHY_DTPR0_TRP_DEFVAL 0x105A2D08 +#define DDR_PHY_DTPR0_TRP_SHIFT 8 +#define DDR_PHY_DTPR0_TRP_MASK 0x00007F00U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR0_RESERVED_7_5_DEFVAL #undef DDR_PHY_DTPR0_RESERVED_7_5_SHIFT #undef DDR_PHY_DTPR0_RESERVED_7_5_MASK -#define DDR_PHY_DTPR0_RESERVED_7_5_DEFVAL 0x105A2D08 -#define DDR_PHY_DTPR0_RESERVED_7_5_SHIFT 5 -#define DDR_PHY_DTPR0_RESERVED_7_5_MASK 0x000000E0U +#define DDR_PHY_DTPR0_RESERVED_7_5_DEFVAL 0x105A2D08 +#define DDR_PHY_DTPR0_RESERVED_7_5_SHIFT 5 +#define DDR_PHY_DTPR0_RESERVED_7_5_MASK 0x000000E0U -/*Internal read to precharge command delay*/ +/* +* Internal read to precharge command delay +*/ #undef DDR_PHY_DTPR0_TRTP_DEFVAL #undef DDR_PHY_DTPR0_TRTP_SHIFT #undef DDR_PHY_DTPR0_TRTP_MASK -#define DDR_PHY_DTPR0_TRTP_DEFVAL 0x105A2D08 -#define DDR_PHY_DTPR0_TRTP_SHIFT 0 -#define DDR_PHY_DTPR0_TRTP_MASK 0x0000001FU +#define DDR_PHY_DTPR0_TRTP_DEFVAL 0x105A2D08 +#define DDR_PHY_DTPR0_TRTP_SHIFT 0 +#define DDR_PHY_DTPR0_TRTP_MASK 0x0000001FU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR1_RESERVED_31_DEFVAL #undef DDR_PHY_DTPR1_RESERVED_31_SHIFT #undef DDR_PHY_DTPR1_RESERVED_31_MASK -#define DDR_PHY_DTPR1_RESERVED_31_DEFVAL 0x5656041E -#define DDR_PHY_DTPR1_RESERVED_31_SHIFT 31 -#define DDR_PHY_DTPR1_RESERVED_31_MASK 0x80000000U +#define DDR_PHY_DTPR1_RESERVED_31_DEFVAL 0x5656041E +#define DDR_PHY_DTPR1_RESERVED_31_SHIFT 31 +#define DDR_PHY_DTPR1_RESERVED_31_MASK 0x80000000U -/*Minimum delay from when write leveling mode is programmed to the first DQS/DQS# rising edge.*/ +/* +* Minimum delay from when write leveling mode is programmed to the first D + * QS/DQS# rising edge. +*/ #undef DDR_PHY_DTPR1_TWLMRD_DEFVAL #undef DDR_PHY_DTPR1_TWLMRD_SHIFT #undef DDR_PHY_DTPR1_TWLMRD_MASK -#define DDR_PHY_DTPR1_TWLMRD_DEFVAL 0x5656041E -#define DDR_PHY_DTPR1_TWLMRD_SHIFT 24 -#define DDR_PHY_DTPR1_TWLMRD_MASK 0x7F000000U +#define DDR_PHY_DTPR1_TWLMRD_DEFVAL 0x5656041E +#define DDR_PHY_DTPR1_TWLMRD_SHIFT 24 +#define DDR_PHY_DTPR1_TWLMRD_MASK 0x7F000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR1_RESERVED_23_DEFVAL #undef DDR_PHY_DTPR1_RESERVED_23_SHIFT #undef DDR_PHY_DTPR1_RESERVED_23_MASK -#define DDR_PHY_DTPR1_RESERVED_23_DEFVAL 0x5656041E -#define DDR_PHY_DTPR1_RESERVED_23_SHIFT 23 -#define DDR_PHY_DTPR1_RESERVED_23_MASK 0x00800000U +#define DDR_PHY_DTPR1_RESERVED_23_DEFVAL 0x5656041E +#define DDR_PHY_DTPR1_RESERVED_23_SHIFT 23 +#define DDR_PHY_DTPR1_RESERVED_23_MASK 0x00800000U -/*4-bank activate period*/ +/* +* 4-bank activate period +*/ #undef DDR_PHY_DTPR1_TFAW_DEFVAL #undef DDR_PHY_DTPR1_TFAW_SHIFT #undef DDR_PHY_DTPR1_TFAW_MASK -#define DDR_PHY_DTPR1_TFAW_DEFVAL 0x5656041E -#define DDR_PHY_DTPR1_TFAW_SHIFT 16 -#define DDR_PHY_DTPR1_TFAW_MASK 0x007F0000U +#define DDR_PHY_DTPR1_TFAW_DEFVAL 0x5656041E +#define DDR_PHY_DTPR1_TFAW_SHIFT 16 +#define DDR_PHY_DTPR1_TFAW_MASK 0x007F0000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR1_RESERVED_15_11_DEFVAL #undef DDR_PHY_DTPR1_RESERVED_15_11_SHIFT #undef DDR_PHY_DTPR1_RESERVED_15_11_MASK -#define DDR_PHY_DTPR1_RESERVED_15_11_DEFVAL 0x5656041E -#define DDR_PHY_DTPR1_RESERVED_15_11_SHIFT 11 -#define DDR_PHY_DTPR1_RESERVED_15_11_MASK 0x0000F800U +#define DDR_PHY_DTPR1_RESERVED_15_11_DEFVAL 0x5656041E +#define DDR_PHY_DTPR1_RESERVED_15_11_SHIFT 11 +#define DDR_PHY_DTPR1_RESERVED_15_11_MASK 0x0000F800U -/*Load mode update delay (DDR4 and DDR3 only)*/ +/* +* Load mode update delay (DDR4 and DDR3 only) +*/ #undef DDR_PHY_DTPR1_TMOD_DEFVAL #undef DDR_PHY_DTPR1_TMOD_SHIFT #undef DDR_PHY_DTPR1_TMOD_MASK -#define DDR_PHY_DTPR1_TMOD_DEFVAL 0x5656041E -#define DDR_PHY_DTPR1_TMOD_SHIFT 8 -#define DDR_PHY_DTPR1_TMOD_MASK 0x00000700U +#define DDR_PHY_DTPR1_TMOD_DEFVAL 0x5656041E +#define DDR_PHY_DTPR1_TMOD_SHIFT 8 +#define DDR_PHY_DTPR1_TMOD_MASK 0x00000700U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR1_RESERVED_7_5_DEFVAL #undef DDR_PHY_DTPR1_RESERVED_7_5_SHIFT #undef DDR_PHY_DTPR1_RESERVED_7_5_MASK -#define DDR_PHY_DTPR1_RESERVED_7_5_DEFVAL 0x5656041E -#define DDR_PHY_DTPR1_RESERVED_7_5_SHIFT 5 -#define DDR_PHY_DTPR1_RESERVED_7_5_MASK 0x000000E0U +#define DDR_PHY_DTPR1_RESERVED_7_5_DEFVAL 0x5656041E +#define DDR_PHY_DTPR1_RESERVED_7_5_SHIFT 5 +#define DDR_PHY_DTPR1_RESERVED_7_5_MASK 0x000000E0U -/*Load mode cycle time*/ +/* +* Load mode cycle time +*/ #undef DDR_PHY_DTPR1_TMRD_DEFVAL #undef DDR_PHY_DTPR1_TMRD_SHIFT #undef DDR_PHY_DTPR1_TMRD_MASK -#define DDR_PHY_DTPR1_TMRD_DEFVAL 0x5656041E -#define DDR_PHY_DTPR1_TMRD_SHIFT 0 -#define DDR_PHY_DTPR1_TMRD_MASK 0x0000001FU +#define DDR_PHY_DTPR1_TMRD_DEFVAL 0x5656041E +#define DDR_PHY_DTPR1_TMRD_SHIFT 0 +#define DDR_PHY_DTPR1_TMRD_MASK 0x0000001FU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR2_RESERVED_31_29_DEFVAL #undef DDR_PHY_DTPR2_RESERVED_31_29_SHIFT #undef DDR_PHY_DTPR2_RESERVED_31_29_MASK -#define DDR_PHY_DTPR2_RESERVED_31_29_DEFVAL 0x000B01D0 -#define DDR_PHY_DTPR2_RESERVED_31_29_SHIFT 29 -#define DDR_PHY_DTPR2_RESERVED_31_29_MASK 0xE0000000U +#define DDR_PHY_DTPR2_RESERVED_31_29_DEFVAL 0x000B01D0 +#define DDR_PHY_DTPR2_RESERVED_31_29_SHIFT 29 +#define DDR_PHY_DTPR2_RESERVED_31_29_MASK 0xE0000000U -/*Read to Write command delay. Valid values are*/ +/* +* Read to Write command delay. Valid values are +*/ #undef DDR_PHY_DTPR2_TRTW_DEFVAL #undef DDR_PHY_DTPR2_TRTW_SHIFT #undef DDR_PHY_DTPR2_TRTW_MASK -#define DDR_PHY_DTPR2_TRTW_DEFVAL 0x000B01D0 -#define DDR_PHY_DTPR2_TRTW_SHIFT 28 -#define DDR_PHY_DTPR2_TRTW_MASK 0x10000000U +#define DDR_PHY_DTPR2_TRTW_DEFVAL 0x000B01D0 +#define DDR_PHY_DTPR2_TRTW_SHIFT 28 +#define DDR_PHY_DTPR2_TRTW_MASK 0x10000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR2_RESERVED_27_25_DEFVAL #undef DDR_PHY_DTPR2_RESERVED_27_25_SHIFT #undef DDR_PHY_DTPR2_RESERVED_27_25_MASK -#define DDR_PHY_DTPR2_RESERVED_27_25_DEFVAL 0x000B01D0 -#define DDR_PHY_DTPR2_RESERVED_27_25_SHIFT 25 -#define DDR_PHY_DTPR2_RESERVED_27_25_MASK 0x0E000000U +#define DDR_PHY_DTPR2_RESERVED_27_25_DEFVAL 0x000B01D0 +#define DDR_PHY_DTPR2_RESERVED_27_25_SHIFT 25 +#define DDR_PHY_DTPR2_RESERVED_27_25_MASK 0x0E000000U -/*Read to ODT delay (DDR3 only)*/ +/* +* Read to ODT delay (DDR3 only) +*/ #undef DDR_PHY_DTPR2_TRTODT_DEFVAL #undef DDR_PHY_DTPR2_TRTODT_SHIFT #undef DDR_PHY_DTPR2_TRTODT_MASK -#define DDR_PHY_DTPR2_TRTODT_DEFVAL 0x000B01D0 -#define DDR_PHY_DTPR2_TRTODT_SHIFT 24 -#define DDR_PHY_DTPR2_TRTODT_MASK 0x01000000U +#define DDR_PHY_DTPR2_TRTODT_DEFVAL 0x000B01D0 +#define DDR_PHY_DTPR2_TRTODT_SHIFT 24 +#define DDR_PHY_DTPR2_TRTODT_MASK 0x01000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR2_RESERVED_23_20_DEFVAL #undef DDR_PHY_DTPR2_RESERVED_23_20_SHIFT #undef DDR_PHY_DTPR2_RESERVED_23_20_MASK -#define DDR_PHY_DTPR2_RESERVED_23_20_DEFVAL 0x000B01D0 -#define DDR_PHY_DTPR2_RESERVED_23_20_SHIFT 20 -#define DDR_PHY_DTPR2_RESERVED_23_20_MASK 0x00F00000U +#define DDR_PHY_DTPR2_RESERVED_23_20_DEFVAL 0x000B01D0 +#define DDR_PHY_DTPR2_RESERVED_23_20_SHIFT 20 +#define DDR_PHY_DTPR2_RESERVED_23_20_MASK 0x00F00000U -/*CKE minimum pulse width*/ +/* +* CKE minimum pulse width +*/ #undef DDR_PHY_DTPR2_TCKE_DEFVAL #undef DDR_PHY_DTPR2_TCKE_SHIFT #undef DDR_PHY_DTPR2_TCKE_MASK -#define DDR_PHY_DTPR2_TCKE_DEFVAL 0x000B01D0 -#define DDR_PHY_DTPR2_TCKE_SHIFT 16 -#define DDR_PHY_DTPR2_TCKE_MASK 0x000F0000U +#define DDR_PHY_DTPR2_TCKE_DEFVAL 0x000B01D0 +#define DDR_PHY_DTPR2_TCKE_SHIFT 16 +#define DDR_PHY_DTPR2_TCKE_MASK 0x000F0000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR2_RESERVED_15_10_DEFVAL #undef DDR_PHY_DTPR2_RESERVED_15_10_SHIFT #undef DDR_PHY_DTPR2_RESERVED_15_10_MASK -#define DDR_PHY_DTPR2_RESERVED_15_10_DEFVAL 0x000B01D0 -#define DDR_PHY_DTPR2_RESERVED_15_10_SHIFT 10 -#define DDR_PHY_DTPR2_RESERVED_15_10_MASK 0x0000FC00U +#define DDR_PHY_DTPR2_RESERVED_15_10_DEFVAL 0x000B01D0 +#define DDR_PHY_DTPR2_RESERVED_15_10_SHIFT 10 +#define DDR_PHY_DTPR2_RESERVED_15_10_MASK 0x0000FC00U -/*Self refresh exit delay*/ +/* +* Self refresh exit delay +*/ #undef DDR_PHY_DTPR2_TXS_DEFVAL #undef DDR_PHY_DTPR2_TXS_SHIFT #undef DDR_PHY_DTPR2_TXS_MASK -#define DDR_PHY_DTPR2_TXS_DEFVAL 0x000B01D0 -#define DDR_PHY_DTPR2_TXS_SHIFT 0 -#define DDR_PHY_DTPR2_TXS_MASK 0x000003FFU +#define DDR_PHY_DTPR2_TXS_DEFVAL 0x000B01D0 +#define DDR_PHY_DTPR2_TXS_SHIFT 0 +#define DDR_PHY_DTPR2_TXS_MASK 0x000003FFU -/*ODT turn-off delay extension*/ +/* +* ODT turn-off delay extension +*/ #undef DDR_PHY_DTPR3_TOFDX_DEFVAL #undef DDR_PHY_DTPR3_TOFDX_SHIFT #undef DDR_PHY_DTPR3_TOFDX_MASK -#define DDR_PHY_DTPR3_TOFDX_DEFVAL 0x02000804 -#define DDR_PHY_DTPR3_TOFDX_SHIFT 29 -#define DDR_PHY_DTPR3_TOFDX_MASK 0xE0000000U +#define DDR_PHY_DTPR3_TOFDX_DEFVAL 0x02000804 +#define DDR_PHY_DTPR3_TOFDX_SHIFT 29 +#define DDR_PHY_DTPR3_TOFDX_MASK 0xE0000000U -/*Read to read and write to write command delay*/ +/* +* Read to read and write to write command delay +*/ #undef DDR_PHY_DTPR3_TCCD_DEFVAL #undef DDR_PHY_DTPR3_TCCD_SHIFT #undef DDR_PHY_DTPR3_TCCD_MASK -#define DDR_PHY_DTPR3_TCCD_DEFVAL 0x02000804 -#define DDR_PHY_DTPR3_TCCD_SHIFT 26 -#define DDR_PHY_DTPR3_TCCD_MASK 0x1C000000U +#define DDR_PHY_DTPR3_TCCD_DEFVAL 0x02000804 +#define DDR_PHY_DTPR3_TCCD_SHIFT 26 +#define DDR_PHY_DTPR3_TCCD_MASK 0x1C000000U -/*DLL locking time*/ +/* +* DLL locking time +*/ #undef DDR_PHY_DTPR3_TDLLK_DEFVAL #undef DDR_PHY_DTPR3_TDLLK_SHIFT #undef DDR_PHY_DTPR3_TDLLK_MASK -#define DDR_PHY_DTPR3_TDLLK_DEFVAL 0x02000804 -#define DDR_PHY_DTPR3_TDLLK_SHIFT 16 -#define DDR_PHY_DTPR3_TDLLK_MASK 0x03FF0000U +#define DDR_PHY_DTPR3_TDLLK_DEFVAL 0x02000804 +#define DDR_PHY_DTPR3_TDLLK_SHIFT 16 +#define DDR_PHY_DTPR3_TDLLK_MASK 0x03FF0000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR3_RESERVED_15_12_DEFVAL #undef DDR_PHY_DTPR3_RESERVED_15_12_SHIFT #undef DDR_PHY_DTPR3_RESERVED_15_12_MASK -#define DDR_PHY_DTPR3_RESERVED_15_12_DEFVAL 0x02000804 -#define DDR_PHY_DTPR3_RESERVED_15_12_SHIFT 12 -#define DDR_PHY_DTPR3_RESERVED_15_12_MASK 0x0000F000U +#define DDR_PHY_DTPR3_RESERVED_15_12_DEFVAL 0x02000804 +#define DDR_PHY_DTPR3_RESERVED_15_12_SHIFT 12 +#define DDR_PHY_DTPR3_RESERVED_15_12_MASK 0x0000F000U -/*Maximum DQS output access time from CK/CK# (LPDDR2/3 only)*/ +/* +* Maximum DQS output access time from CK/CK# (LPDDR2/3 only) +*/ #undef DDR_PHY_DTPR3_TDQSCKMAX_DEFVAL #undef DDR_PHY_DTPR3_TDQSCKMAX_SHIFT #undef DDR_PHY_DTPR3_TDQSCKMAX_MASK -#define DDR_PHY_DTPR3_TDQSCKMAX_DEFVAL 0x02000804 -#define DDR_PHY_DTPR3_TDQSCKMAX_SHIFT 8 -#define DDR_PHY_DTPR3_TDQSCKMAX_MASK 0x00000F00U +#define DDR_PHY_DTPR3_TDQSCKMAX_DEFVAL 0x02000804 +#define DDR_PHY_DTPR3_TDQSCKMAX_SHIFT 8 +#define DDR_PHY_DTPR3_TDQSCKMAX_MASK 0x00000F00U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR3_RESERVED_7_3_DEFVAL #undef DDR_PHY_DTPR3_RESERVED_7_3_SHIFT #undef DDR_PHY_DTPR3_RESERVED_7_3_MASK -#define DDR_PHY_DTPR3_RESERVED_7_3_DEFVAL 0x02000804 -#define DDR_PHY_DTPR3_RESERVED_7_3_SHIFT 3 -#define DDR_PHY_DTPR3_RESERVED_7_3_MASK 0x000000F8U +#define DDR_PHY_DTPR3_RESERVED_7_3_DEFVAL 0x02000804 +#define DDR_PHY_DTPR3_RESERVED_7_3_SHIFT 3 +#define DDR_PHY_DTPR3_RESERVED_7_3_MASK 0x000000F8U -/*DQS output access time from CK/CK# (LPDDR2/3 only)*/ +/* +* DQS output access time from CK/CK# (LPDDR2/3 only) +*/ #undef DDR_PHY_DTPR3_TDQSCK_DEFVAL #undef DDR_PHY_DTPR3_TDQSCK_SHIFT #undef DDR_PHY_DTPR3_TDQSCK_MASK -#define DDR_PHY_DTPR3_TDQSCK_DEFVAL 0x02000804 -#define DDR_PHY_DTPR3_TDQSCK_SHIFT 0 -#define DDR_PHY_DTPR3_TDQSCK_MASK 0x00000007U +#define DDR_PHY_DTPR3_TDQSCK_DEFVAL 0x02000804 +#define DDR_PHY_DTPR3_TDQSCK_SHIFT 0 +#define DDR_PHY_DTPR3_TDQSCK_MASK 0x00000007U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR4_RESERVED_31_30_DEFVAL #undef DDR_PHY_DTPR4_RESERVED_31_30_SHIFT #undef DDR_PHY_DTPR4_RESERVED_31_30_MASK -#define DDR_PHY_DTPR4_RESERVED_31_30_DEFVAL 0x01C02B10 -#define DDR_PHY_DTPR4_RESERVED_31_30_SHIFT 30 -#define DDR_PHY_DTPR4_RESERVED_31_30_MASK 0xC0000000U +#define DDR_PHY_DTPR4_RESERVED_31_30_DEFVAL 0x01C02B10 +#define DDR_PHY_DTPR4_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DTPR4_RESERVED_31_30_MASK 0xC0000000U -/*ODT turn-on/turn-off delays (DDR2 only)*/ +/* +* ODT turn-on/turn-off delays (DDR2 only) +*/ #undef DDR_PHY_DTPR4_TAOND_TAOFD_DEFVAL #undef DDR_PHY_DTPR4_TAOND_TAOFD_SHIFT #undef DDR_PHY_DTPR4_TAOND_TAOFD_MASK -#define DDR_PHY_DTPR4_TAOND_TAOFD_DEFVAL 0x01C02B10 -#define DDR_PHY_DTPR4_TAOND_TAOFD_SHIFT 28 -#define DDR_PHY_DTPR4_TAOND_TAOFD_MASK 0x30000000U +#define DDR_PHY_DTPR4_TAOND_TAOFD_DEFVAL 0x01C02B10 +#define DDR_PHY_DTPR4_TAOND_TAOFD_SHIFT 28 +#define DDR_PHY_DTPR4_TAOND_TAOFD_MASK 0x30000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR4_RESERVED_27_26_DEFVAL #undef DDR_PHY_DTPR4_RESERVED_27_26_SHIFT #undef DDR_PHY_DTPR4_RESERVED_27_26_MASK -#define DDR_PHY_DTPR4_RESERVED_27_26_DEFVAL 0x01C02B10 -#define DDR_PHY_DTPR4_RESERVED_27_26_SHIFT 26 -#define DDR_PHY_DTPR4_RESERVED_27_26_MASK 0x0C000000U +#define DDR_PHY_DTPR4_RESERVED_27_26_DEFVAL 0x01C02B10 +#define DDR_PHY_DTPR4_RESERVED_27_26_SHIFT 26 +#define DDR_PHY_DTPR4_RESERVED_27_26_MASK 0x0C000000U -/*Refresh-to-Refresh*/ +/* +* Refresh-to-Refresh +*/ #undef DDR_PHY_DTPR4_TRFC_DEFVAL #undef DDR_PHY_DTPR4_TRFC_SHIFT #undef DDR_PHY_DTPR4_TRFC_MASK -#define DDR_PHY_DTPR4_TRFC_DEFVAL 0x01C02B10 -#define DDR_PHY_DTPR4_TRFC_SHIFT 16 -#define DDR_PHY_DTPR4_TRFC_MASK 0x03FF0000U +#define DDR_PHY_DTPR4_TRFC_DEFVAL 0x01C02B10 +#define DDR_PHY_DTPR4_TRFC_SHIFT 16 +#define DDR_PHY_DTPR4_TRFC_MASK 0x03FF0000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR4_RESERVED_15_14_DEFVAL #undef DDR_PHY_DTPR4_RESERVED_15_14_SHIFT #undef DDR_PHY_DTPR4_RESERVED_15_14_MASK -#define DDR_PHY_DTPR4_RESERVED_15_14_DEFVAL 0x01C02B10 -#define DDR_PHY_DTPR4_RESERVED_15_14_SHIFT 14 -#define DDR_PHY_DTPR4_RESERVED_15_14_MASK 0x0000C000U +#define DDR_PHY_DTPR4_RESERVED_15_14_DEFVAL 0x01C02B10 +#define DDR_PHY_DTPR4_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_DTPR4_RESERVED_15_14_MASK 0x0000C000U -/*Write leveling output delay*/ +/* +* Write leveling output delay +*/ #undef DDR_PHY_DTPR4_TWLO_DEFVAL #undef DDR_PHY_DTPR4_TWLO_SHIFT #undef DDR_PHY_DTPR4_TWLO_MASK -#define DDR_PHY_DTPR4_TWLO_DEFVAL 0x01C02B10 -#define DDR_PHY_DTPR4_TWLO_SHIFT 8 -#define DDR_PHY_DTPR4_TWLO_MASK 0x00003F00U +#define DDR_PHY_DTPR4_TWLO_DEFVAL 0x01C02B10 +#define DDR_PHY_DTPR4_TWLO_SHIFT 8 +#define DDR_PHY_DTPR4_TWLO_MASK 0x00003F00U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR4_RESERVED_7_5_DEFVAL #undef DDR_PHY_DTPR4_RESERVED_7_5_SHIFT #undef DDR_PHY_DTPR4_RESERVED_7_5_MASK -#define DDR_PHY_DTPR4_RESERVED_7_5_DEFVAL 0x01C02B10 -#define DDR_PHY_DTPR4_RESERVED_7_5_SHIFT 5 -#define DDR_PHY_DTPR4_RESERVED_7_5_MASK 0x000000E0U +#define DDR_PHY_DTPR4_RESERVED_7_5_DEFVAL 0x01C02B10 +#define DDR_PHY_DTPR4_RESERVED_7_5_SHIFT 5 +#define DDR_PHY_DTPR4_RESERVED_7_5_MASK 0x000000E0U -/*Power down exit delay*/ +/* +* Power down exit delay +*/ #undef DDR_PHY_DTPR4_TXP_DEFVAL #undef DDR_PHY_DTPR4_TXP_SHIFT #undef DDR_PHY_DTPR4_TXP_MASK -#define DDR_PHY_DTPR4_TXP_DEFVAL 0x01C02B10 -#define DDR_PHY_DTPR4_TXP_SHIFT 0 -#define DDR_PHY_DTPR4_TXP_MASK 0x0000001FU +#define DDR_PHY_DTPR4_TXP_DEFVAL 0x01C02B10 +#define DDR_PHY_DTPR4_TXP_SHIFT 0 +#define DDR_PHY_DTPR4_TXP_MASK 0x0000001FU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR5_RESERVED_31_24_DEFVAL #undef DDR_PHY_DTPR5_RESERVED_31_24_SHIFT #undef DDR_PHY_DTPR5_RESERVED_31_24_MASK -#define DDR_PHY_DTPR5_RESERVED_31_24_DEFVAL 0x00872716 -#define DDR_PHY_DTPR5_RESERVED_31_24_SHIFT 24 -#define DDR_PHY_DTPR5_RESERVED_31_24_MASK 0xFF000000U +#define DDR_PHY_DTPR5_RESERVED_31_24_DEFVAL 0x00872716 +#define DDR_PHY_DTPR5_RESERVED_31_24_SHIFT 24 +#define DDR_PHY_DTPR5_RESERVED_31_24_MASK 0xFF000000U -/*Activate to activate command delay (same bank)*/ +/* +* Activate to activate command delay (same bank) +*/ #undef DDR_PHY_DTPR5_TRC_DEFVAL #undef DDR_PHY_DTPR5_TRC_SHIFT #undef DDR_PHY_DTPR5_TRC_MASK -#define DDR_PHY_DTPR5_TRC_DEFVAL 0x00872716 -#define DDR_PHY_DTPR5_TRC_SHIFT 16 -#define DDR_PHY_DTPR5_TRC_MASK 0x00FF0000U +#define DDR_PHY_DTPR5_TRC_DEFVAL 0x00872716 +#define DDR_PHY_DTPR5_TRC_SHIFT 16 +#define DDR_PHY_DTPR5_TRC_MASK 0x00FF0000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR5_RESERVED_15_DEFVAL #undef DDR_PHY_DTPR5_RESERVED_15_SHIFT #undef DDR_PHY_DTPR5_RESERVED_15_MASK -#define DDR_PHY_DTPR5_RESERVED_15_DEFVAL 0x00872716 -#define DDR_PHY_DTPR5_RESERVED_15_SHIFT 15 -#define DDR_PHY_DTPR5_RESERVED_15_MASK 0x00008000U +#define DDR_PHY_DTPR5_RESERVED_15_DEFVAL 0x00872716 +#define DDR_PHY_DTPR5_RESERVED_15_SHIFT 15 +#define DDR_PHY_DTPR5_RESERVED_15_MASK 0x00008000U -/*Activate to read or write delay*/ +/* +* Activate to read or write delay +*/ #undef DDR_PHY_DTPR5_TRCD_DEFVAL #undef DDR_PHY_DTPR5_TRCD_SHIFT #undef DDR_PHY_DTPR5_TRCD_MASK -#define DDR_PHY_DTPR5_TRCD_DEFVAL 0x00872716 -#define DDR_PHY_DTPR5_TRCD_SHIFT 8 -#define DDR_PHY_DTPR5_TRCD_MASK 0x00007F00U +#define DDR_PHY_DTPR5_TRCD_DEFVAL 0x00872716 +#define DDR_PHY_DTPR5_TRCD_SHIFT 8 +#define DDR_PHY_DTPR5_TRCD_MASK 0x00007F00U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR5_RESERVED_7_5_DEFVAL #undef DDR_PHY_DTPR5_RESERVED_7_5_SHIFT #undef DDR_PHY_DTPR5_RESERVED_7_5_MASK -#define DDR_PHY_DTPR5_RESERVED_7_5_DEFVAL 0x00872716 -#define DDR_PHY_DTPR5_RESERVED_7_5_SHIFT 5 -#define DDR_PHY_DTPR5_RESERVED_7_5_MASK 0x000000E0U +#define DDR_PHY_DTPR5_RESERVED_7_5_DEFVAL 0x00872716 +#define DDR_PHY_DTPR5_RESERVED_7_5_SHIFT 5 +#define DDR_PHY_DTPR5_RESERVED_7_5_MASK 0x000000E0U -/*Internal write to read command delay*/ +/* +* Internal write to read command delay +*/ #undef DDR_PHY_DTPR5_TWTR_DEFVAL #undef DDR_PHY_DTPR5_TWTR_SHIFT #undef DDR_PHY_DTPR5_TWTR_MASK -#define DDR_PHY_DTPR5_TWTR_DEFVAL 0x00872716 -#define DDR_PHY_DTPR5_TWTR_SHIFT 0 -#define DDR_PHY_DTPR5_TWTR_MASK 0x0000001FU +#define DDR_PHY_DTPR5_TWTR_DEFVAL 0x00872716 +#define DDR_PHY_DTPR5_TWTR_SHIFT 0 +#define DDR_PHY_DTPR5_TWTR_MASK 0x0000001FU -/*PUB Write Latency Enable*/ +/* +* PUB Write Latency Enable +*/ #undef DDR_PHY_DTPR6_PUBWLEN_DEFVAL #undef DDR_PHY_DTPR6_PUBWLEN_SHIFT #undef DDR_PHY_DTPR6_PUBWLEN_MASK -#define DDR_PHY_DTPR6_PUBWLEN_DEFVAL 0x00000505 -#define DDR_PHY_DTPR6_PUBWLEN_SHIFT 31 -#define DDR_PHY_DTPR6_PUBWLEN_MASK 0x80000000U +#define DDR_PHY_DTPR6_PUBWLEN_DEFVAL 0x00000505 +#define DDR_PHY_DTPR6_PUBWLEN_SHIFT 31 +#define DDR_PHY_DTPR6_PUBWLEN_MASK 0x80000000U -/*PUB Read Latency Enable*/ +/* +* PUB Read Latency Enable +*/ #undef DDR_PHY_DTPR6_PUBRLEN_DEFVAL #undef DDR_PHY_DTPR6_PUBRLEN_SHIFT #undef DDR_PHY_DTPR6_PUBRLEN_MASK -#define DDR_PHY_DTPR6_PUBRLEN_DEFVAL 0x00000505 -#define DDR_PHY_DTPR6_PUBRLEN_SHIFT 30 -#define DDR_PHY_DTPR6_PUBRLEN_MASK 0x40000000U +#define DDR_PHY_DTPR6_PUBRLEN_DEFVAL 0x00000505 +#define DDR_PHY_DTPR6_PUBRLEN_SHIFT 30 +#define DDR_PHY_DTPR6_PUBRLEN_MASK 0x40000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR6_RESERVED_29_14_DEFVAL #undef DDR_PHY_DTPR6_RESERVED_29_14_SHIFT #undef DDR_PHY_DTPR6_RESERVED_29_14_MASK -#define DDR_PHY_DTPR6_RESERVED_29_14_DEFVAL 0x00000505 -#define DDR_PHY_DTPR6_RESERVED_29_14_SHIFT 14 -#define DDR_PHY_DTPR6_RESERVED_29_14_MASK 0x3FFFC000U +#define DDR_PHY_DTPR6_RESERVED_29_14_DEFVAL 0x00000505 +#define DDR_PHY_DTPR6_RESERVED_29_14_SHIFT 14 +#define DDR_PHY_DTPR6_RESERVED_29_14_MASK 0x3FFFC000U -/*Write Latency*/ +/* +* Write Latency +*/ #undef DDR_PHY_DTPR6_PUBWL_DEFVAL #undef DDR_PHY_DTPR6_PUBWL_SHIFT #undef DDR_PHY_DTPR6_PUBWL_MASK -#define DDR_PHY_DTPR6_PUBWL_DEFVAL 0x00000505 -#define DDR_PHY_DTPR6_PUBWL_SHIFT 8 -#define DDR_PHY_DTPR6_PUBWL_MASK 0x00003F00U +#define DDR_PHY_DTPR6_PUBWL_DEFVAL 0x00000505 +#define DDR_PHY_DTPR6_PUBWL_SHIFT 8 +#define DDR_PHY_DTPR6_PUBWL_MASK 0x00003F00U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR6_RESERVED_7_6_DEFVAL #undef DDR_PHY_DTPR6_RESERVED_7_6_SHIFT #undef DDR_PHY_DTPR6_RESERVED_7_6_MASK -#define DDR_PHY_DTPR6_RESERVED_7_6_DEFVAL 0x00000505 -#define DDR_PHY_DTPR6_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_DTPR6_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_DTPR6_RESERVED_7_6_DEFVAL 0x00000505 +#define DDR_PHY_DTPR6_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DTPR6_RESERVED_7_6_MASK 0x000000C0U -/*Read Latency*/ +/* +* Read Latency +*/ #undef DDR_PHY_DTPR6_PUBRL_DEFVAL #undef DDR_PHY_DTPR6_PUBRL_SHIFT #undef DDR_PHY_DTPR6_PUBRL_MASK -#define DDR_PHY_DTPR6_PUBRL_DEFVAL 0x00000505 -#define DDR_PHY_DTPR6_PUBRL_SHIFT 0 -#define DDR_PHY_DTPR6_PUBRL_MASK 0x0000003FU +#define DDR_PHY_DTPR6_PUBRL_DEFVAL 0x00000505 +#define DDR_PHY_DTPR6_PUBRL_SHIFT 0 +#define DDR_PHY_DTPR6_PUBRL_MASK 0x0000003FU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_RDIMMGCR0_RESERVED_31_DEFVAL #undef DDR_PHY_RDIMMGCR0_RESERVED_31_SHIFT #undef DDR_PHY_RDIMMGCR0_RESERVED_31_MASK -#define DDR_PHY_RDIMMGCR0_RESERVED_31_DEFVAL 0x08400020 -#define DDR_PHY_RDIMMGCR0_RESERVED_31_SHIFT 31 -#define DDR_PHY_RDIMMGCR0_RESERVED_31_MASK 0x80000000U +#define DDR_PHY_RDIMMGCR0_RESERVED_31_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_RESERVED_31_SHIFT 31 +#define DDR_PHY_RDIMMGCR0_RESERVED_31_MASK 0x80000000U -/*RDMIMM Quad CS Enable*/ +/* +* RDMIMM Quad CS Enable +*/ #undef DDR_PHY_RDIMMGCR0_QCSEN_DEFVAL #undef DDR_PHY_RDIMMGCR0_QCSEN_SHIFT #undef DDR_PHY_RDIMMGCR0_QCSEN_MASK -#define DDR_PHY_RDIMMGCR0_QCSEN_DEFVAL 0x08400020 -#define DDR_PHY_RDIMMGCR0_QCSEN_SHIFT 30 -#define DDR_PHY_RDIMMGCR0_QCSEN_MASK 0x40000000U +#define DDR_PHY_RDIMMGCR0_QCSEN_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_QCSEN_SHIFT 30 +#define DDR_PHY_RDIMMGCR0_QCSEN_MASK 0x40000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_RDIMMGCR0_RESERVED_29_28_DEFVAL #undef DDR_PHY_RDIMMGCR0_RESERVED_29_28_SHIFT #undef DDR_PHY_RDIMMGCR0_RESERVED_29_28_MASK -#define DDR_PHY_RDIMMGCR0_RESERVED_29_28_DEFVAL 0x08400020 -#define DDR_PHY_RDIMMGCR0_RESERVED_29_28_SHIFT 28 -#define DDR_PHY_RDIMMGCR0_RESERVED_29_28_MASK 0x30000000U +#define DDR_PHY_RDIMMGCR0_RESERVED_29_28_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_RESERVED_29_28_SHIFT 28 +#define DDR_PHY_RDIMMGCR0_RESERVED_29_28_MASK 0x30000000U -/*RDIMM Outputs I/O Mode*/ +/* +* RDIMM Outputs I/O Mode +*/ #undef DDR_PHY_RDIMMGCR0_RDIMMIOM_DEFVAL #undef DDR_PHY_RDIMMGCR0_RDIMMIOM_SHIFT #undef DDR_PHY_RDIMMGCR0_RDIMMIOM_MASK -#define DDR_PHY_RDIMMGCR0_RDIMMIOM_DEFVAL 0x08400020 -#define DDR_PHY_RDIMMGCR0_RDIMMIOM_SHIFT 27 -#define DDR_PHY_RDIMMGCR0_RDIMMIOM_MASK 0x08000000U +#define DDR_PHY_RDIMMGCR0_RDIMMIOM_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_RDIMMIOM_SHIFT 27 +#define DDR_PHY_RDIMMGCR0_RDIMMIOM_MASK 0x08000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_RDIMMGCR0_RESERVED_26_24_DEFVAL #undef DDR_PHY_RDIMMGCR0_RESERVED_26_24_SHIFT #undef DDR_PHY_RDIMMGCR0_RESERVED_26_24_MASK -#define DDR_PHY_RDIMMGCR0_RESERVED_26_24_DEFVAL 0x08400020 -#define DDR_PHY_RDIMMGCR0_RESERVED_26_24_SHIFT 24 -#define DDR_PHY_RDIMMGCR0_RESERVED_26_24_MASK 0x07000000U +#define DDR_PHY_RDIMMGCR0_RESERVED_26_24_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_RESERVED_26_24_SHIFT 24 +#define DDR_PHY_RDIMMGCR0_RESERVED_26_24_MASK 0x07000000U -/*ERROUT# Output Enable*/ +/* +* ERROUT# Output Enable +*/ #undef DDR_PHY_RDIMMGCR0_ERROUTOE_DEFVAL #undef DDR_PHY_RDIMMGCR0_ERROUTOE_SHIFT #undef DDR_PHY_RDIMMGCR0_ERROUTOE_MASK -#define DDR_PHY_RDIMMGCR0_ERROUTOE_DEFVAL 0x08400020 -#define DDR_PHY_RDIMMGCR0_ERROUTOE_SHIFT 23 -#define DDR_PHY_RDIMMGCR0_ERROUTOE_MASK 0x00800000U +#define DDR_PHY_RDIMMGCR0_ERROUTOE_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_ERROUTOE_SHIFT 23 +#define DDR_PHY_RDIMMGCR0_ERROUTOE_MASK 0x00800000U -/*ERROUT# I/O Mode*/ +/* +* ERROUT# I/O Mode +*/ #undef DDR_PHY_RDIMMGCR0_ERROUTIOM_DEFVAL #undef DDR_PHY_RDIMMGCR0_ERROUTIOM_SHIFT #undef DDR_PHY_RDIMMGCR0_ERROUTIOM_MASK -#define DDR_PHY_RDIMMGCR0_ERROUTIOM_DEFVAL 0x08400020 -#define DDR_PHY_RDIMMGCR0_ERROUTIOM_SHIFT 22 -#define DDR_PHY_RDIMMGCR0_ERROUTIOM_MASK 0x00400000U +#define DDR_PHY_RDIMMGCR0_ERROUTIOM_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_ERROUTIOM_SHIFT 22 +#define DDR_PHY_RDIMMGCR0_ERROUTIOM_MASK 0x00400000U -/*ERROUT# Power Down Receiver*/ +/* +* ERROUT# Power Down Receiver +*/ #undef DDR_PHY_RDIMMGCR0_ERROUTPDR_DEFVAL #undef DDR_PHY_RDIMMGCR0_ERROUTPDR_SHIFT #undef DDR_PHY_RDIMMGCR0_ERROUTPDR_MASK -#define DDR_PHY_RDIMMGCR0_ERROUTPDR_DEFVAL 0x08400020 -#define DDR_PHY_RDIMMGCR0_ERROUTPDR_SHIFT 21 -#define DDR_PHY_RDIMMGCR0_ERROUTPDR_MASK 0x00200000U +#define DDR_PHY_RDIMMGCR0_ERROUTPDR_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_ERROUTPDR_SHIFT 21 +#define DDR_PHY_RDIMMGCR0_ERROUTPDR_MASK 0x00200000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_RDIMMGCR0_RESERVED_20_DEFVAL #undef DDR_PHY_RDIMMGCR0_RESERVED_20_SHIFT #undef DDR_PHY_RDIMMGCR0_RESERVED_20_MASK -#define DDR_PHY_RDIMMGCR0_RESERVED_20_DEFVAL 0x08400020 -#define DDR_PHY_RDIMMGCR0_RESERVED_20_SHIFT 20 -#define DDR_PHY_RDIMMGCR0_RESERVED_20_MASK 0x00100000U +#define DDR_PHY_RDIMMGCR0_RESERVED_20_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_RESERVED_20_SHIFT 20 +#define DDR_PHY_RDIMMGCR0_RESERVED_20_MASK 0x00100000U -/*ERROUT# On-Die Termination*/ +/* +* ERROUT# On-Die Termination +*/ #undef DDR_PHY_RDIMMGCR0_ERROUTODT_DEFVAL #undef DDR_PHY_RDIMMGCR0_ERROUTODT_SHIFT #undef DDR_PHY_RDIMMGCR0_ERROUTODT_MASK -#define DDR_PHY_RDIMMGCR0_ERROUTODT_DEFVAL 0x08400020 -#define DDR_PHY_RDIMMGCR0_ERROUTODT_SHIFT 19 -#define DDR_PHY_RDIMMGCR0_ERROUTODT_MASK 0x00080000U +#define DDR_PHY_RDIMMGCR0_ERROUTODT_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_ERROUTODT_SHIFT 19 +#define DDR_PHY_RDIMMGCR0_ERROUTODT_MASK 0x00080000U -/*Load Reduced DIMM*/ +/* +* Load Reduced DIMM +*/ #undef DDR_PHY_RDIMMGCR0_LRDIMM_DEFVAL #undef DDR_PHY_RDIMMGCR0_LRDIMM_SHIFT #undef DDR_PHY_RDIMMGCR0_LRDIMM_MASK -#define DDR_PHY_RDIMMGCR0_LRDIMM_DEFVAL 0x08400020 -#define DDR_PHY_RDIMMGCR0_LRDIMM_SHIFT 18 -#define DDR_PHY_RDIMMGCR0_LRDIMM_MASK 0x00040000U +#define DDR_PHY_RDIMMGCR0_LRDIMM_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_LRDIMM_SHIFT 18 +#define DDR_PHY_RDIMMGCR0_LRDIMM_MASK 0x00040000U -/*PAR_IN I/O Mode*/ +/* +* PAR_IN I/O Mode +*/ #undef DDR_PHY_RDIMMGCR0_PARINIOM_DEFVAL #undef DDR_PHY_RDIMMGCR0_PARINIOM_SHIFT #undef DDR_PHY_RDIMMGCR0_PARINIOM_MASK -#define DDR_PHY_RDIMMGCR0_PARINIOM_DEFVAL 0x08400020 -#define DDR_PHY_RDIMMGCR0_PARINIOM_SHIFT 17 -#define DDR_PHY_RDIMMGCR0_PARINIOM_MASK 0x00020000U +#define DDR_PHY_RDIMMGCR0_PARINIOM_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_PARINIOM_SHIFT 17 +#define DDR_PHY_RDIMMGCR0_PARINIOM_MASK 0x00020000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_RDIMMGCR0_RESERVED_16_8_DEFVAL #undef DDR_PHY_RDIMMGCR0_RESERVED_16_8_SHIFT #undef DDR_PHY_RDIMMGCR0_RESERVED_16_8_MASK -#define DDR_PHY_RDIMMGCR0_RESERVED_16_8_DEFVAL 0x08400020 -#define DDR_PHY_RDIMMGCR0_RESERVED_16_8_SHIFT 8 -#define DDR_PHY_RDIMMGCR0_RESERVED_16_8_MASK 0x0001FF00U +#define DDR_PHY_RDIMMGCR0_RESERVED_16_8_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_RESERVED_16_8_SHIFT 8 +#define DDR_PHY_RDIMMGCR0_RESERVED_16_8_MASK 0x0001FF00U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_DEFVAL #undef DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_SHIFT #undef DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_MASK -#define DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_DEFVAL 0x08400020 -#define DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_SHIFT 6 -#define DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_MASK 0x000000C0U +#define DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_SHIFT 6 +#define DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_MASK 0x000000C0U -/*Rank Mirror Enable.*/ +/* +* Rank Mirror Enable. +*/ #undef DDR_PHY_RDIMMGCR0_RNKMRREN_DEFVAL #undef DDR_PHY_RDIMMGCR0_RNKMRREN_SHIFT #undef DDR_PHY_RDIMMGCR0_RNKMRREN_MASK -#define DDR_PHY_RDIMMGCR0_RNKMRREN_DEFVAL 0x08400020 -#define DDR_PHY_RDIMMGCR0_RNKMRREN_SHIFT 4 -#define DDR_PHY_RDIMMGCR0_RNKMRREN_MASK 0x00000030U +#define DDR_PHY_RDIMMGCR0_RNKMRREN_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_RNKMRREN_SHIFT 4 +#define DDR_PHY_RDIMMGCR0_RNKMRREN_MASK 0x00000030U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_RDIMMGCR0_RESERVED_3_DEFVAL #undef DDR_PHY_RDIMMGCR0_RESERVED_3_SHIFT #undef DDR_PHY_RDIMMGCR0_RESERVED_3_MASK -#define DDR_PHY_RDIMMGCR0_RESERVED_3_DEFVAL 0x08400020 -#define DDR_PHY_RDIMMGCR0_RESERVED_3_SHIFT 3 -#define DDR_PHY_RDIMMGCR0_RESERVED_3_MASK 0x00000008U +#define DDR_PHY_RDIMMGCR0_RESERVED_3_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_RESERVED_3_SHIFT 3 +#define DDR_PHY_RDIMMGCR0_RESERVED_3_MASK 0x00000008U -/*Stop on Parity Error*/ +/* +* Stop on Parity Error +*/ #undef DDR_PHY_RDIMMGCR0_SOPERR_DEFVAL #undef DDR_PHY_RDIMMGCR0_SOPERR_SHIFT #undef DDR_PHY_RDIMMGCR0_SOPERR_MASK -#define DDR_PHY_RDIMMGCR0_SOPERR_DEFVAL 0x08400020 -#define DDR_PHY_RDIMMGCR0_SOPERR_SHIFT 2 -#define DDR_PHY_RDIMMGCR0_SOPERR_MASK 0x00000004U +#define DDR_PHY_RDIMMGCR0_SOPERR_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_SOPERR_SHIFT 2 +#define DDR_PHY_RDIMMGCR0_SOPERR_MASK 0x00000004U -/*Parity Error No Registering*/ +/* +* Parity Error No Registering +*/ #undef DDR_PHY_RDIMMGCR0_ERRNOREG_DEFVAL #undef DDR_PHY_RDIMMGCR0_ERRNOREG_SHIFT #undef DDR_PHY_RDIMMGCR0_ERRNOREG_MASK -#define DDR_PHY_RDIMMGCR0_ERRNOREG_DEFVAL 0x08400020 -#define DDR_PHY_RDIMMGCR0_ERRNOREG_SHIFT 1 -#define DDR_PHY_RDIMMGCR0_ERRNOREG_MASK 0x00000002U +#define DDR_PHY_RDIMMGCR0_ERRNOREG_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_ERRNOREG_SHIFT 1 +#define DDR_PHY_RDIMMGCR0_ERRNOREG_MASK 0x00000002U -/*Registered DIMM*/ +/* +* Registered DIMM +*/ #undef DDR_PHY_RDIMMGCR0_RDIMM_DEFVAL #undef DDR_PHY_RDIMMGCR0_RDIMM_SHIFT #undef DDR_PHY_RDIMMGCR0_RDIMM_MASK -#define DDR_PHY_RDIMMGCR0_RDIMM_DEFVAL 0x08400020 -#define DDR_PHY_RDIMMGCR0_RDIMM_SHIFT 0 -#define DDR_PHY_RDIMMGCR0_RDIMM_MASK 0x00000001U +#define DDR_PHY_RDIMMGCR0_RDIMM_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_RDIMM_SHIFT 0 +#define DDR_PHY_RDIMMGCR0_RDIMM_MASK 0x00000001U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_RDIMMGCR1_RESERVED_31_29_DEFVAL #undef DDR_PHY_RDIMMGCR1_RESERVED_31_29_SHIFT #undef DDR_PHY_RDIMMGCR1_RESERVED_31_29_MASK -#define DDR_PHY_RDIMMGCR1_RESERVED_31_29_DEFVAL 0x00000C80 -#define DDR_PHY_RDIMMGCR1_RESERVED_31_29_SHIFT 29 -#define DDR_PHY_RDIMMGCR1_RESERVED_31_29_MASK 0xE0000000U +#define DDR_PHY_RDIMMGCR1_RESERVED_31_29_DEFVAL 0x00000C80 +#define DDR_PHY_RDIMMGCR1_RESERVED_31_29_SHIFT 29 +#define DDR_PHY_RDIMMGCR1_RESERVED_31_29_MASK 0xE0000000U -/*Address [17] B-side Inversion Disable*/ +/* +* Address [17] B-side Inversion Disable +*/ #undef DDR_PHY_RDIMMGCR1_A17BID_DEFVAL #undef DDR_PHY_RDIMMGCR1_A17BID_SHIFT #undef DDR_PHY_RDIMMGCR1_A17BID_MASK -#define DDR_PHY_RDIMMGCR1_A17BID_DEFVAL 0x00000C80 -#define DDR_PHY_RDIMMGCR1_A17BID_SHIFT 28 -#define DDR_PHY_RDIMMGCR1_A17BID_MASK 0x10000000U +#define DDR_PHY_RDIMMGCR1_A17BID_DEFVAL 0x00000C80 +#define DDR_PHY_RDIMMGCR1_A17BID_SHIFT 28 +#define DDR_PHY_RDIMMGCR1_A17BID_MASK 0x10000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_RDIMMGCR1_RESERVED_27_DEFVAL #undef DDR_PHY_RDIMMGCR1_RESERVED_27_SHIFT #undef DDR_PHY_RDIMMGCR1_RESERVED_27_MASK -#define DDR_PHY_RDIMMGCR1_RESERVED_27_DEFVAL 0x00000C80 -#define DDR_PHY_RDIMMGCR1_RESERVED_27_SHIFT 27 -#define DDR_PHY_RDIMMGCR1_RESERVED_27_MASK 0x08000000U +#define DDR_PHY_RDIMMGCR1_RESERVED_27_DEFVAL 0x00000C80 +#define DDR_PHY_RDIMMGCR1_RESERVED_27_SHIFT 27 +#define DDR_PHY_RDIMMGCR1_RESERVED_27_MASK 0x08000000U -/*Command word to command word programming delay*/ +/* +* Command word to command word programming delay +*/ #undef DDR_PHY_RDIMMGCR1_TBCMRD_L2_DEFVAL #undef DDR_PHY_RDIMMGCR1_TBCMRD_L2_SHIFT #undef DDR_PHY_RDIMMGCR1_TBCMRD_L2_MASK -#define DDR_PHY_RDIMMGCR1_TBCMRD_L2_DEFVAL 0x00000C80 -#define DDR_PHY_RDIMMGCR1_TBCMRD_L2_SHIFT 24 -#define DDR_PHY_RDIMMGCR1_TBCMRD_L2_MASK 0x07000000U +#define DDR_PHY_RDIMMGCR1_TBCMRD_L2_DEFVAL 0x00000C80 +#define DDR_PHY_RDIMMGCR1_TBCMRD_L2_SHIFT 24 +#define DDR_PHY_RDIMMGCR1_TBCMRD_L2_MASK 0x07000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_RDIMMGCR1_RESERVED_23_DEFVAL #undef DDR_PHY_RDIMMGCR1_RESERVED_23_SHIFT #undef DDR_PHY_RDIMMGCR1_RESERVED_23_MASK -#define DDR_PHY_RDIMMGCR1_RESERVED_23_DEFVAL 0x00000C80 -#define DDR_PHY_RDIMMGCR1_RESERVED_23_SHIFT 23 -#define DDR_PHY_RDIMMGCR1_RESERVED_23_MASK 0x00800000U +#define DDR_PHY_RDIMMGCR1_RESERVED_23_DEFVAL 0x00000C80 +#define DDR_PHY_RDIMMGCR1_RESERVED_23_SHIFT 23 +#define DDR_PHY_RDIMMGCR1_RESERVED_23_MASK 0x00800000U -/*Command word to command word programming delay*/ +/* +* Command word to command word programming delay +*/ #undef DDR_PHY_RDIMMGCR1_TBCMRD_L_DEFVAL #undef DDR_PHY_RDIMMGCR1_TBCMRD_L_SHIFT #undef DDR_PHY_RDIMMGCR1_TBCMRD_L_MASK -#define DDR_PHY_RDIMMGCR1_TBCMRD_L_DEFVAL 0x00000C80 -#define DDR_PHY_RDIMMGCR1_TBCMRD_L_SHIFT 20 -#define DDR_PHY_RDIMMGCR1_TBCMRD_L_MASK 0x00700000U +#define DDR_PHY_RDIMMGCR1_TBCMRD_L_DEFVAL 0x00000C80 +#define DDR_PHY_RDIMMGCR1_TBCMRD_L_SHIFT 20 +#define DDR_PHY_RDIMMGCR1_TBCMRD_L_MASK 0x00700000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_RDIMMGCR1_RESERVED_19_DEFVAL #undef DDR_PHY_RDIMMGCR1_RESERVED_19_SHIFT #undef DDR_PHY_RDIMMGCR1_RESERVED_19_MASK -#define DDR_PHY_RDIMMGCR1_RESERVED_19_DEFVAL 0x00000C80 -#define DDR_PHY_RDIMMGCR1_RESERVED_19_SHIFT 19 -#define DDR_PHY_RDIMMGCR1_RESERVED_19_MASK 0x00080000U +#define DDR_PHY_RDIMMGCR1_RESERVED_19_DEFVAL 0x00000C80 +#define DDR_PHY_RDIMMGCR1_RESERVED_19_SHIFT 19 +#define DDR_PHY_RDIMMGCR1_RESERVED_19_MASK 0x00080000U -/*Command word to command word programming delay*/ +/* +* Command word to command word programming delay +*/ #undef DDR_PHY_RDIMMGCR1_TBCMRD_DEFVAL #undef DDR_PHY_RDIMMGCR1_TBCMRD_SHIFT #undef DDR_PHY_RDIMMGCR1_TBCMRD_MASK -#define DDR_PHY_RDIMMGCR1_TBCMRD_DEFVAL 0x00000C80 -#define DDR_PHY_RDIMMGCR1_TBCMRD_SHIFT 16 -#define DDR_PHY_RDIMMGCR1_TBCMRD_MASK 0x00070000U +#define DDR_PHY_RDIMMGCR1_TBCMRD_DEFVAL 0x00000C80 +#define DDR_PHY_RDIMMGCR1_TBCMRD_SHIFT 16 +#define DDR_PHY_RDIMMGCR1_TBCMRD_MASK 0x00070000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_RDIMMGCR1_RESERVED_15_14_DEFVAL #undef DDR_PHY_RDIMMGCR1_RESERVED_15_14_SHIFT #undef DDR_PHY_RDIMMGCR1_RESERVED_15_14_MASK -#define DDR_PHY_RDIMMGCR1_RESERVED_15_14_DEFVAL 0x00000C80 -#define DDR_PHY_RDIMMGCR1_RESERVED_15_14_SHIFT 14 -#define DDR_PHY_RDIMMGCR1_RESERVED_15_14_MASK 0x0000C000U +#define DDR_PHY_RDIMMGCR1_RESERVED_15_14_DEFVAL 0x00000C80 +#define DDR_PHY_RDIMMGCR1_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_RDIMMGCR1_RESERVED_15_14_MASK 0x0000C000U -/*Stabilization time*/ +/* +* Stabilization time +*/ #undef DDR_PHY_RDIMMGCR1_TBCSTAB_DEFVAL #undef DDR_PHY_RDIMMGCR1_TBCSTAB_SHIFT #undef DDR_PHY_RDIMMGCR1_TBCSTAB_MASK -#define DDR_PHY_RDIMMGCR1_TBCSTAB_DEFVAL 0x00000C80 -#define DDR_PHY_RDIMMGCR1_TBCSTAB_SHIFT 0 -#define DDR_PHY_RDIMMGCR1_TBCSTAB_MASK 0x00003FFFU +#define DDR_PHY_RDIMMGCR1_TBCSTAB_DEFVAL 0x00000C80 +#define DDR_PHY_RDIMMGCR1_TBCSTAB_SHIFT 0 +#define DDR_PHY_RDIMMGCR1_TBCSTAB_MASK 0x00003FFFU -/*DDR4/DDR3 Control Word 7*/ +/* +* DDR4/DDR3 Control Word 7 +*/ #undef DDR_PHY_RDIMMCR0_RC7_DEFVAL #undef DDR_PHY_RDIMMCR0_RC7_SHIFT #undef DDR_PHY_RDIMMCR0_RC7_MASK -#define DDR_PHY_RDIMMCR0_RC7_DEFVAL 0x00000000 -#define DDR_PHY_RDIMMCR0_RC7_SHIFT 28 -#define DDR_PHY_RDIMMCR0_RC7_MASK 0xF0000000U +#define DDR_PHY_RDIMMCR0_RC7_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR0_RC7_SHIFT 28 +#define DDR_PHY_RDIMMCR0_RC7_MASK 0xF0000000U -/*DDR4 Control Word 6 (Comman space Control Word) / DDR3 Reserved*/ +/* +* DDR4 Control Word 6 (Comman space Control Word) / DDR3 Reserved +*/ #undef DDR_PHY_RDIMMCR0_RC6_DEFVAL #undef DDR_PHY_RDIMMCR0_RC6_SHIFT #undef DDR_PHY_RDIMMCR0_RC6_MASK -#define DDR_PHY_RDIMMCR0_RC6_DEFVAL 0x00000000 -#define DDR_PHY_RDIMMCR0_RC6_SHIFT 24 -#define DDR_PHY_RDIMMCR0_RC6_MASK 0x0F000000U +#define DDR_PHY_RDIMMCR0_RC6_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR0_RC6_SHIFT 24 +#define DDR_PHY_RDIMMCR0_RC6_MASK 0x0F000000U -/*DDR4/DDR3 Control Word 5 (CK Driver Characteristics Control Word)*/ +/* +* DDR4/DDR3 Control Word 5 (CK Driver Characteristics Control Word) +*/ #undef DDR_PHY_RDIMMCR0_RC5_DEFVAL #undef DDR_PHY_RDIMMCR0_RC5_SHIFT #undef DDR_PHY_RDIMMCR0_RC5_MASK -#define DDR_PHY_RDIMMCR0_RC5_DEFVAL 0x00000000 -#define DDR_PHY_RDIMMCR0_RC5_SHIFT 20 -#define DDR_PHY_RDIMMCR0_RC5_MASK 0x00F00000U +#define DDR_PHY_RDIMMCR0_RC5_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR0_RC5_SHIFT 20 +#define DDR_PHY_RDIMMCR0_RC5_MASK 0x00F00000U -/*DDR4 Control Word 4 (ODT and CKE Signals Driver Characteristics Control Word) / DDR3 Control Word 4 (Control Signals Driver C - aracteristics Control Word)*/ +/* +* DDR4 Control Word 4 (ODT and CKE Signals Driver Characteristics Control + * Word) / DDR3 Control Word 4 (Control Signals Driver Characteristics Cont + * rol Word) +*/ #undef DDR_PHY_RDIMMCR0_RC4_DEFVAL #undef DDR_PHY_RDIMMCR0_RC4_SHIFT #undef DDR_PHY_RDIMMCR0_RC4_MASK -#define DDR_PHY_RDIMMCR0_RC4_DEFVAL 0x00000000 -#define DDR_PHY_RDIMMCR0_RC4_SHIFT 16 -#define DDR_PHY_RDIMMCR0_RC4_MASK 0x000F0000U +#define DDR_PHY_RDIMMCR0_RC4_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR0_RC4_SHIFT 16 +#define DDR_PHY_RDIMMCR0_RC4_MASK 0x000F0000U -/*DDR4 Control Word 3 (CA and CS Signals Driver Characteristics Control Word) / DDR3 Control Word 3 (Command/Address Signals Dr - ver Characteristrics Control Word)*/ +/* +* DDR4 Control Word 3 (CA and CS Signals Driver Characteristics Control Wo + * rd) / DDR3 Control Word 3 (Command/Address Signals Driver Characteristri + * cs Control Word) +*/ #undef DDR_PHY_RDIMMCR0_RC3_DEFVAL #undef DDR_PHY_RDIMMCR0_RC3_SHIFT #undef DDR_PHY_RDIMMCR0_RC3_MASK -#define DDR_PHY_RDIMMCR0_RC3_DEFVAL 0x00000000 -#define DDR_PHY_RDIMMCR0_RC3_SHIFT 12 -#define DDR_PHY_RDIMMCR0_RC3_MASK 0x0000F000U +#define DDR_PHY_RDIMMCR0_RC3_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR0_RC3_SHIFT 12 +#define DDR_PHY_RDIMMCR0_RC3_MASK 0x0000F000U -/*DDR4 Control Word 2 (Timing and IBT Control Word) / DDR3 Control Word 2 (Timing Control Word)*/ +/* +* DDR4 Control Word 2 (Timing and IBT Control Word) / DDR3 Control Word 2 + * (Timing Control Word) +*/ #undef DDR_PHY_RDIMMCR0_RC2_DEFVAL #undef DDR_PHY_RDIMMCR0_RC2_SHIFT #undef DDR_PHY_RDIMMCR0_RC2_MASK -#define DDR_PHY_RDIMMCR0_RC2_DEFVAL 0x00000000 -#define DDR_PHY_RDIMMCR0_RC2_SHIFT 8 -#define DDR_PHY_RDIMMCR0_RC2_MASK 0x00000F00U +#define DDR_PHY_RDIMMCR0_RC2_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR0_RC2_SHIFT 8 +#define DDR_PHY_RDIMMCR0_RC2_MASK 0x00000F00U -/*DDR4/DDR3 Control Word 1 (Clock Driver Enable Control Word)*/ +/* +* DDR4/DDR3 Control Word 1 (Clock Driver Enable Control Word) +*/ #undef DDR_PHY_RDIMMCR0_RC1_DEFVAL #undef DDR_PHY_RDIMMCR0_RC1_SHIFT #undef DDR_PHY_RDIMMCR0_RC1_MASK -#define DDR_PHY_RDIMMCR0_RC1_DEFVAL 0x00000000 -#define DDR_PHY_RDIMMCR0_RC1_SHIFT 4 -#define DDR_PHY_RDIMMCR0_RC1_MASK 0x000000F0U +#define DDR_PHY_RDIMMCR0_RC1_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR0_RC1_SHIFT 4 +#define DDR_PHY_RDIMMCR0_RC1_MASK 0x000000F0U -/*DDR4/DDR3 Control Word 0 (Global Features Control Word)*/ +/* +* DDR4/DDR3 Control Word 0 (Global Features Control Word) +*/ #undef DDR_PHY_RDIMMCR0_RC0_DEFVAL #undef DDR_PHY_RDIMMCR0_RC0_SHIFT #undef DDR_PHY_RDIMMCR0_RC0_MASK -#define DDR_PHY_RDIMMCR0_RC0_DEFVAL 0x00000000 -#define DDR_PHY_RDIMMCR0_RC0_SHIFT 0 -#define DDR_PHY_RDIMMCR0_RC0_MASK 0x0000000FU +#define DDR_PHY_RDIMMCR0_RC0_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR0_RC0_SHIFT 0 +#define DDR_PHY_RDIMMCR0_RC0_MASK 0x0000000FU -/*Control Word 15*/ +/* +* Control Word 15 +*/ #undef DDR_PHY_RDIMMCR1_RC15_DEFVAL #undef DDR_PHY_RDIMMCR1_RC15_SHIFT #undef DDR_PHY_RDIMMCR1_RC15_MASK -#define DDR_PHY_RDIMMCR1_RC15_DEFVAL 0x00000000 -#define DDR_PHY_RDIMMCR1_RC15_SHIFT 28 -#define DDR_PHY_RDIMMCR1_RC15_MASK 0xF0000000U +#define DDR_PHY_RDIMMCR1_RC15_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR1_RC15_SHIFT 28 +#define DDR_PHY_RDIMMCR1_RC15_MASK 0xF0000000U -/*DDR4 Control Word 14 (Parity Control Word) / DDR3 Reserved*/ +/* +* DDR4 Control Word 14 (Parity Control Word) / DDR3 Reserved +*/ #undef DDR_PHY_RDIMMCR1_RC14_DEFVAL #undef DDR_PHY_RDIMMCR1_RC14_SHIFT #undef DDR_PHY_RDIMMCR1_RC14_MASK -#define DDR_PHY_RDIMMCR1_RC14_DEFVAL 0x00000000 -#define DDR_PHY_RDIMMCR1_RC14_SHIFT 24 -#define DDR_PHY_RDIMMCR1_RC14_MASK 0x0F000000U +#define DDR_PHY_RDIMMCR1_RC14_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR1_RC14_SHIFT 24 +#define DDR_PHY_RDIMMCR1_RC14_MASK 0x0F000000U -/*DDR4 Control Word 13 (DIMM Configuration Control Word) / DDR3 Reserved*/ +/* +* DDR4 Control Word 13 (DIMM Configuration Control Word) / DDR3 Reserved +*/ #undef DDR_PHY_RDIMMCR1_RC13_DEFVAL #undef DDR_PHY_RDIMMCR1_RC13_SHIFT #undef DDR_PHY_RDIMMCR1_RC13_MASK -#define DDR_PHY_RDIMMCR1_RC13_DEFVAL 0x00000000 -#define DDR_PHY_RDIMMCR1_RC13_SHIFT 20 -#define DDR_PHY_RDIMMCR1_RC13_MASK 0x00F00000U +#define DDR_PHY_RDIMMCR1_RC13_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR1_RC13_SHIFT 20 +#define DDR_PHY_RDIMMCR1_RC13_MASK 0x00F00000U -/*DDR4 Control Word 12 (Training Control Word) / DDR3 Reserved*/ +/* +* DDR4 Control Word 12 (Training Control Word) / DDR3 Reserved +*/ #undef DDR_PHY_RDIMMCR1_RC12_DEFVAL #undef DDR_PHY_RDIMMCR1_RC12_SHIFT #undef DDR_PHY_RDIMMCR1_RC12_MASK -#define DDR_PHY_RDIMMCR1_RC12_DEFVAL 0x00000000 -#define DDR_PHY_RDIMMCR1_RC12_SHIFT 16 -#define DDR_PHY_RDIMMCR1_RC12_MASK 0x000F0000U +#define DDR_PHY_RDIMMCR1_RC12_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR1_RC12_SHIFT 16 +#define DDR_PHY_RDIMMCR1_RC12_MASK 0x000F0000U -/*DDR4 Control Word 11 (Operating Voltage VDD and VREFCA Source Control Word) / DDR3 Control Word 11 (Operation Voltage VDD Con - rol Word)*/ +/* +* DDR4 Control Word 11 (Operating Voltage VDD and VREFCA Source Control Wo + * rd) / DDR3 Control Word 11 (Operation Voltage VDD Control Word) +*/ #undef DDR_PHY_RDIMMCR1_RC11_DEFVAL #undef DDR_PHY_RDIMMCR1_RC11_SHIFT #undef DDR_PHY_RDIMMCR1_RC11_MASK -#define DDR_PHY_RDIMMCR1_RC11_DEFVAL 0x00000000 -#define DDR_PHY_RDIMMCR1_RC11_SHIFT 12 -#define DDR_PHY_RDIMMCR1_RC11_MASK 0x0000F000U +#define DDR_PHY_RDIMMCR1_RC11_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR1_RC11_SHIFT 12 +#define DDR_PHY_RDIMMCR1_RC11_MASK 0x0000F000U -/*DDR4/DDR3 Control Word 10 (RDIMM Operating Speed Control Word)*/ +/* +* DDR4/DDR3 Control Word 10 (RDIMM Operating Speed Control Word) +*/ #undef DDR_PHY_RDIMMCR1_RC10_DEFVAL #undef DDR_PHY_RDIMMCR1_RC10_SHIFT #undef DDR_PHY_RDIMMCR1_RC10_MASK -#define DDR_PHY_RDIMMCR1_RC10_DEFVAL 0x00000000 -#define DDR_PHY_RDIMMCR1_RC10_SHIFT 8 -#define DDR_PHY_RDIMMCR1_RC10_MASK 0x00000F00U +#define DDR_PHY_RDIMMCR1_RC10_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR1_RC10_SHIFT 8 +#define DDR_PHY_RDIMMCR1_RC10_MASK 0x00000F00U -/*DDR4/DDR3 Control Word 9 (Power Saving Settings Control Word)*/ +/* +* DDR4/DDR3 Control Word 9 (Power Saving Settings Control Word) +*/ #undef DDR_PHY_RDIMMCR1_RC9_DEFVAL #undef DDR_PHY_RDIMMCR1_RC9_SHIFT #undef DDR_PHY_RDIMMCR1_RC9_MASK -#define DDR_PHY_RDIMMCR1_RC9_DEFVAL 0x00000000 -#define DDR_PHY_RDIMMCR1_RC9_SHIFT 4 -#define DDR_PHY_RDIMMCR1_RC9_MASK 0x000000F0U +#define DDR_PHY_RDIMMCR1_RC9_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR1_RC9_SHIFT 4 +#define DDR_PHY_RDIMMCR1_RC9_MASK 0x000000F0U -/*DDR4 Control Word 8 (Input/Output Configuration Control Word) / DDR3 Control Word 8 (Additional Input Bus Termination Setting - Control Word)*/ +/* +* DDR4 Control Word 8 (Input/Output Configuration Control Word) / DDR3 Con + * trol Word 8 (Additional Input Bus Termination Setting Control Word) +*/ #undef DDR_PHY_RDIMMCR1_RC8_DEFVAL #undef DDR_PHY_RDIMMCR1_RC8_SHIFT #undef DDR_PHY_RDIMMCR1_RC8_MASK -#define DDR_PHY_RDIMMCR1_RC8_DEFVAL 0x00000000 -#define DDR_PHY_RDIMMCR1_RC8_SHIFT 0 -#define DDR_PHY_RDIMMCR1_RC8_MASK 0x0000000FU +#define DDR_PHY_RDIMMCR1_RC8_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR1_RC8_SHIFT 0 +#define DDR_PHY_RDIMMCR1_RC8_MASK 0x0000000FU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_MR0_RESERVED_31_8_DEFVAL #undef DDR_PHY_MR0_RESERVED_31_8_SHIFT #undef DDR_PHY_MR0_RESERVED_31_8_MASK -#define DDR_PHY_MR0_RESERVED_31_8_DEFVAL 0x00000052 -#define DDR_PHY_MR0_RESERVED_31_8_SHIFT 8 -#define DDR_PHY_MR0_RESERVED_31_8_MASK 0xFFFFFF00U +#define DDR_PHY_MR0_RESERVED_31_8_DEFVAL 0x00000052 +#define DDR_PHY_MR0_RESERVED_31_8_SHIFT 8 +#define DDR_PHY_MR0_RESERVED_31_8_MASK 0xFFFFFF00U -/*CA Terminating Rank*/ +/* +* CA Terminating Rank +*/ #undef DDR_PHY_MR0_CATR_DEFVAL #undef DDR_PHY_MR0_CATR_SHIFT #undef DDR_PHY_MR0_CATR_MASK -#define DDR_PHY_MR0_CATR_DEFVAL 0x00000052 -#define DDR_PHY_MR0_CATR_SHIFT 7 -#define DDR_PHY_MR0_CATR_MASK 0x00000080U +#define DDR_PHY_MR0_CATR_DEFVAL 0x00000052 +#define DDR_PHY_MR0_CATR_SHIFT 7 +#define DDR_PHY_MR0_CATR_MASK 0x00000080U -/*Reserved. These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/ +/* +* Reserved. These are JEDEC reserved bits and are recommended by JEDEC to + * be programmed to 0x0. +*/ #undef DDR_PHY_MR0_RSVD_6_5_DEFVAL #undef DDR_PHY_MR0_RSVD_6_5_SHIFT #undef DDR_PHY_MR0_RSVD_6_5_MASK -#define DDR_PHY_MR0_RSVD_6_5_DEFVAL 0x00000052 -#define DDR_PHY_MR0_RSVD_6_5_SHIFT 5 -#define DDR_PHY_MR0_RSVD_6_5_MASK 0x00000060U +#define DDR_PHY_MR0_RSVD_6_5_DEFVAL 0x00000052 +#define DDR_PHY_MR0_RSVD_6_5_SHIFT 5 +#define DDR_PHY_MR0_RSVD_6_5_MASK 0x00000060U -/*Built-in Self-Test for RZQ*/ +/* +* Built-in Self-Test for RZQ +*/ #undef DDR_PHY_MR0_RZQI_DEFVAL #undef DDR_PHY_MR0_RZQI_SHIFT #undef DDR_PHY_MR0_RZQI_MASK -#define DDR_PHY_MR0_RZQI_DEFVAL 0x00000052 -#define DDR_PHY_MR0_RZQI_SHIFT 3 -#define DDR_PHY_MR0_RZQI_MASK 0x00000018U +#define DDR_PHY_MR0_RZQI_DEFVAL 0x00000052 +#define DDR_PHY_MR0_RZQI_SHIFT 3 +#define DDR_PHY_MR0_RZQI_MASK 0x00000018U -/*Reserved. These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/ +/* +* Reserved. These are JEDEC reserved bits and are recommended by JEDEC to + * be programmed to 0x0. +*/ #undef DDR_PHY_MR0_RSVD_2_0_DEFVAL #undef DDR_PHY_MR0_RSVD_2_0_SHIFT #undef DDR_PHY_MR0_RSVD_2_0_MASK -#define DDR_PHY_MR0_RSVD_2_0_DEFVAL 0x00000052 -#define DDR_PHY_MR0_RSVD_2_0_SHIFT 0 -#define DDR_PHY_MR0_RSVD_2_0_MASK 0x00000007U +#define DDR_PHY_MR0_RSVD_2_0_DEFVAL 0x00000052 +#define DDR_PHY_MR0_RSVD_2_0_SHIFT 0 +#define DDR_PHY_MR0_RSVD_2_0_MASK 0x00000007U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_MR1_RESERVED_31_8_DEFVAL #undef DDR_PHY_MR1_RESERVED_31_8_SHIFT #undef DDR_PHY_MR1_RESERVED_31_8_MASK -#define DDR_PHY_MR1_RESERVED_31_8_DEFVAL 0x00000004 -#define DDR_PHY_MR1_RESERVED_31_8_SHIFT 8 -#define DDR_PHY_MR1_RESERVED_31_8_MASK 0xFFFFFF00U +#define DDR_PHY_MR1_RESERVED_31_8_DEFVAL 0x00000004 +#define DDR_PHY_MR1_RESERVED_31_8_SHIFT 8 +#define DDR_PHY_MR1_RESERVED_31_8_MASK 0xFFFFFF00U -/*Read Postamble Length*/ +/* +* Read Postamble Length +*/ #undef DDR_PHY_MR1_RDPST_DEFVAL #undef DDR_PHY_MR1_RDPST_SHIFT #undef DDR_PHY_MR1_RDPST_MASK -#define DDR_PHY_MR1_RDPST_DEFVAL 0x00000004 -#define DDR_PHY_MR1_RDPST_SHIFT 7 -#define DDR_PHY_MR1_RDPST_MASK 0x00000080U +#define DDR_PHY_MR1_RDPST_DEFVAL 0x00000004 +#define DDR_PHY_MR1_RDPST_SHIFT 7 +#define DDR_PHY_MR1_RDPST_MASK 0x00000080U -/*Write-recovery for auto-precharge command*/ +/* +* Write-recovery for auto-precharge command +*/ #undef DDR_PHY_MR1_NWR_DEFVAL #undef DDR_PHY_MR1_NWR_SHIFT #undef DDR_PHY_MR1_NWR_MASK -#define DDR_PHY_MR1_NWR_DEFVAL 0x00000004 -#define DDR_PHY_MR1_NWR_SHIFT 4 -#define DDR_PHY_MR1_NWR_MASK 0x00000070U +#define DDR_PHY_MR1_NWR_DEFVAL 0x00000004 +#define DDR_PHY_MR1_NWR_SHIFT 4 +#define DDR_PHY_MR1_NWR_MASK 0x00000070U -/*Read Preamble Length*/ +/* +* Read Preamble Length +*/ #undef DDR_PHY_MR1_RDPRE_DEFVAL #undef DDR_PHY_MR1_RDPRE_SHIFT #undef DDR_PHY_MR1_RDPRE_MASK -#define DDR_PHY_MR1_RDPRE_DEFVAL 0x00000004 -#define DDR_PHY_MR1_RDPRE_SHIFT 3 -#define DDR_PHY_MR1_RDPRE_MASK 0x00000008U +#define DDR_PHY_MR1_RDPRE_DEFVAL 0x00000004 +#define DDR_PHY_MR1_RDPRE_SHIFT 3 +#define DDR_PHY_MR1_RDPRE_MASK 0x00000008U -/*Write Preamble Length*/ +/* +* Write Preamble Length +*/ #undef DDR_PHY_MR1_WRPRE_DEFVAL #undef DDR_PHY_MR1_WRPRE_SHIFT #undef DDR_PHY_MR1_WRPRE_MASK -#define DDR_PHY_MR1_WRPRE_DEFVAL 0x00000004 -#define DDR_PHY_MR1_WRPRE_SHIFT 2 -#define DDR_PHY_MR1_WRPRE_MASK 0x00000004U +#define DDR_PHY_MR1_WRPRE_DEFVAL 0x00000004 +#define DDR_PHY_MR1_WRPRE_SHIFT 2 +#define DDR_PHY_MR1_WRPRE_MASK 0x00000004U -/*Burst Length*/ +/* +* Burst Length +*/ #undef DDR_PHY_MR1_BL_DEFVAL #undef DDR_PHY_MR1_BL_SHIFT #undef DDR_PHY_MR1_BL_MASK -#define DDR_PHY_MR1_BL_DEFVAL 0x00000004 -#define DDR_PHY_MR1_BL_SHIFT 0 -#define DDR_PHY_MR1_BL_MASK 0x00000003U +#define DDR_PHY_MR1_BL_DEFVAL 0x00000004 +#define DDR_PHY_MR1_BL_SHIFT 0 +#define DDR_PHY_MR1_BL_MASK 0x00000003U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_MR2_RESERVED_31_8_DEFVAL #undef DDR_PHY_MR2_RESERVED_31_8_SHIFT #undef DDR_PHY_MR2_RESERVED_31_8_MASK -#define DDR_PHY_MR2_RESERVED_31_8_DEFVAL 0x00000000 -#define DDR_PHY_MR2_RESERVED_31_8_SHIFT 8 -#define DDR_PHY_MR2_RESERVED_31_8_MASK 0xFFFFFF00U +#define DDR_PHY_MR2_RESERVED_31_8_DEFVAL 0x00000000 +#define DDR_PHY_MR2_RESERVED_31_8_SHIFT 8 +#define DDR_PHY_MR2_RESERVED_31_8_MASK 0xFFFFFF00U -/*Write Leveling*/ +/* +* Write Leveling +*/ #undef DDR_PHY_MR2_WRL_DEFVAL #undef DDR_PHY_MR2_WRL_SHIFT #undef DDR_PHY_MR2_WRL_MASK -#define DDR_PHY_MR2_WRL_DEFVAL 0x00000000 -#define DDR_PHY_MR2_WRL_SHIFT 7 -#define DDR_PHY_MR2_WRL_MASK 0x00000080U +#define DDR_PHY_MR2_WRL_DEFVAL 0x00000000 +#define DDR_PHY_MR2_WRL_SHIFT 7 +#define DDR_PHY_MR2_WRL_MASK 0x00000080U -/*Write Latency Set*/ +/* +* Write Latency Set +*/ #undef DDR_PHY_MR2_WLS_DEFVAL #undef DDR_PHY_MR2_WLS_SHIFT #undef DDR_PHY_MR2_WLS_MASK -#define DDR_PHY_MR2_WLS_DEFVAL 0x00000000 -#define DDR_PHY_MR2_WLS_SHIFT 6 -#define DDR_PHY_MR2_WLS_MASK 0x00000040U +#define DDR_PHY_MR2_WLS_DEFVAL 0x00000000 +#define DDR_PHY_MR2_WLS_SHIFT 6 +#define DDR_PHY_MR2_WLS_MASK 0x00000040U -/*Write Latency*/ +/* +* Write Latency +*/ #undef DDR_PHY_MR2_WL_DEFVAL #undef DDR_PHY_MR2_WL_SHIFT #undef DDR_PHY_MR2_WL_MASK -#define DDR_PHY_MR2_WL_DEFVAL 0x00000000 -#define DDR_PHY_MR2_WL_SHIFT 3 -#define DDR_PHY_MR2_WL_MASK 0x00000038U +#define DDR_PHY_MR2_WL_DEFVAL 0x00000000 +#define DDR_PHY_MR2_WL_SHIFT 3 +#define DDR_PHY_MR2_WL_MASK 0x00000038U -/*Read Latency*/ +/* +* Read Latency +*/ #undef DDR_PHY_MR2_RL_DEFVAL #undef DDR_PHY_MR2_RL_SHIFT #undef DDR_PHY_MR2_RL_MASK -#define DDR_PHY_MR2_RL_DEFVAL 0x00000000 -#define DDR_PHY_MR2_RL_SHIFT 0 -#define DDR_PHY_MR2_RL_MASK 0x00000007U +#define DDR_PHY_MR2_RL_DEFVAL 0x00000000 +#define DDR_PHY_MR2_RL_SHIFT 0 +#define DDR_PHY_MR2_RL_MASK 0x00000007U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_MR3_RESERVED_31_8_DEFVAL #undef DDR_PHY_MR3_RESERVED_31_8_SHIFT #undef DDR_PHY_MR3_RESERVED_31_8_MASK -#define DDR_PHY_MR3_RESERVED_31_8_DEFVAL 0x00000031 -#define DDR_PHY_MR3_RESERVED_31_8_SHIFT 8 -#define DDR_PHY_MR3_RESERVED_31_8_MASK 0xFFFFFF00U +#define DDR_PHY_MR3_RESERVED_31_8_DEFVAL 0x00000031 +#define DDR_PHY_MR3_RESERVED_31_8_SHIFT 8 +#define DDR_PHY_MR3_RESERVED_31_8_MASK 0xFFFFFF00U -/*DBI-Write Enable*/ +/* +* DBI-Write Enable +*/ #undef DDR_PHY_MR3_DBIWR_DEFVAL #undef DDR_PHY_MR3_DBIWR_SHIFT #undef DDR_PHY_MR3_DBIWR_MASK -#define DDR_PHY_MR3_DBIWR_DEFVAL 0x00000031 -#define DDR_PHY_MR3_DBIWR_SHIFT 7 -#define DDR_PHY_MR3_DBIWR_MASK 0x00000080U +#define DDR_PHY_MR3_DBIWR_DEFVAL 0x00000031 +#define DDR_PHY_MR3_DBIWR_SHIFT 7 +#define DDR_PHY_MR3_DBIWR_MASK 0x00000080U -/*DBI-Read Enable*/ +/* +* DBI-Read Enable +*/ #undef DDR_PHY_MR3_DBIRD_DEFVAL #undef DDR_PHY_MR3_DBIRD_SHIFT #undef DDR_PHY_MR3_DBIRD_MASK -#define DDR_PHY_MR3_DBIRD_DEFVAL 0x00000031 -#define DDR_PHY_MR3_DBIRD_SHIFT 6 -#define DDR_PHY_MR3_DBIRD_MASK 0x00000040U +#define DDR_PHY_MR3_DBIRD_DEFVAL 0x00000031 +#define DDR_PHY_MR3_DBIRD_SHIFT 6 +#define DDR_PHY_MR3_DBIRD_MASK 0x00000040U -/*Pull-down Drive Strength*/ +/* +* Pull-down Drive Strength +*/ #undef DDR_PHY_MR3_PDDS_DEFVAL #undef DDR_PHY_MR3_PDDS_SHIFT #undef DDR_PHY_MR3_PDDS_MASK -#define DDR_PHY_MR3_PDDS_DEFVAL 0x00000031 -#define DDR_PHY_MR3_PDDS_SHIFT 3 -#define DDR_PHY_MR3_PDDS_MASK 0x00000038U +#define DDR_PHY_MR3_PDDS_DEFVAL 0x00000031 +#define DDR_PHY_MR3_PDDS_SHIFT 3 +#define DDR_PHY_MR3_PDDS_MASK 0x00000038U -/*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/ +/* +* These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. +*/ #undef DDR_PHY_MR3_RSVD_DEFVAL #undef DDR_PHY_MR3_RSVD_SHIFT #undef DDR_PHY_MR3_RSVD_MASK -#define DDR_PHY_MR3_RSVD_DEFVAL 0x00000031 -#define DDR_PHY_MR3_RSVD_SHIFT 2 -#define DDR_PHY_MR3_RSVD_MASK 0x00000004U +#define DDR_PHY_MR3_RSVD_DEFVAL 0x00000031 +#define DDR_PHY_MR3_RSVD_SHIFT 2 +#define DDR_PHY_MR3_RSVD_MASK 0x00000004U -/*Write Postamble Length*/ +/* +* Write Postamble Length +*/ #undef DDR_PHY_MR3_WRPST_DEFVAL #undef DDR_PHY_MR3_WRPST_SHIFT #undef DDR_PHY_MR3_WRPST_MASK -#define DDR_PHY_MR3_WRPST_DEFVAL 0x00000031 -#define DDR_PHY_MR3_WRPST_SHIFT 1 -#define DDR_PHY_MR3_WRPST_MASK 0x00000002U +#define DDR_PHY_MR3_WRPST_DEFVAL 0x00000031 +#define DDR_PHY_MR3_WRPST_SHIFT 1 +#define DDR_PHY_MR3_WRPST_MASK 0x00000002U -/*Pull-up Calibration Point*/ +/* +* Pull-up Calibration Point +*/ #undef DDR_PHY_MR3_PUCAL_DEFVAL #undef DDR_PHY_MR3_PUCAL_SHIFT #undef DDR_PHY_MR3_PUCAL_MASK -#define DDR_PHY_MR3_PUCAL_DEFVAL 0x00000031 -#define DDR_PHY_MR3_PUCAL_SHIFT 0 -#define DDR_PHY_MR3_PUCAL_MASK 0x00000001U +#define DDR_PHY_MR3_PUCAL_DEFVAL 0x00000031 +#define DDR_PHY_MR3_PUCAL_SHIFT 0 +#define DDR_PHY_MR3_PUCAL_MASK 0x00000001U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_MR4_RESERVED_31_16_DEFVAL #undef DDR_PHY_MR4_RESERVED_31_16_SHIFT #undef DDR_PHY_MR4_RESERVED_31_16_MASK -#define DDR_PHY_MR4_RESERVED_31_16_DEFVAL 0x00000000 -#define DDR_PHY_MR4_RESERVED_31_16_SHIFT 16 -#define DDR_PHY_MR4_RESERVED_31_16_MASK 0xFFFF0000U +#define DDR_PHY_MR4_RESERVED_31_16_DEFVAL 0x00000000 +#define DDR_PHY_MR4_RESERVED_31_16_SHIFT 16 +#define DDR_PHY_MR4_RESERVED_31_16_MASK 0xFFFF0000U -/*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/ +/* +* These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. +*/ #undef DDR_PHY_MR4_RSVD_15_13_DEFVAL #undef DDR_PHY_MR4_RSVD_15_13_SHIFT #undef DDR_PHY_MR4_RSVD_15_13_MASK -#define DDR_PHY_MR4_RSVD_15_13_DEFVAL 0x00000000 -#define DDR_PHY_MR4_RSVD_15_13_SHIFT 13 -#define DDR_PHY_MR4_RSVD_15_13_MASK 0x0000E000U +#define DDR_PHY_MR4_RSVD_15_13_DEFVAL 0x00000000 +#define DDR_PHY_MR4_RSVD_15_13_SHIFT 13 +#define DDR_PHY_MR4_RSVD_15_13_MASK 0x0000E000U -/*Write Preamble*/ +/* +* Write Preamble +*/ #undef DDR_PHY_MR4_WRP_DEFVAL #undef DDR_PHY_MR4_WRP_SHIFT #undef DDR_PHY_MR4_WRP_MASK -#define DDR_PHY_MR4_WRP_DEFVAL 0x00000000 -#define DDR_PHY_MR4_WRP_SHIFT 12 -#define DDR_PHY_MR4_WRP_MASK 0x00001000U +#define DDR_PHY_MR4_WRP_DEFVAL 0x00000000 +#define DDR_PHY_MR4_WRP_SHIFT 12 +#define DDR_PHY_MR4_WRP_MASK 0x00001000U -/*Read Preamble*/ +/* +* Read Preamble +*/ #undef DDR_PHY_MR4_RDP_DEFVAL #undef DDR_PHY_MR4_RDP_SHIFT #undef DDR_PHY_MR4_RDP_MASK -#define DDR_PHY_MR4_RDP_DEFVAL 0x00000000 -#define DDR_PHY_MR4_RDP_SHIFT 11 -#define DDR_PHY_MR4_RDP_MASK 0x00000800U +#define DDR_PHY_MR4_RDP_DEFVAL 0x00000000 +#define DDR_PHY_MR4_RDP_SHIFT 11 +#define DDR_PHY_MR4_RDP_MASK 0x00000800U -/*Read Preamble Training Mode*/ +/* +* Read Preamble Training Mode +*/ #undef DDR_PHY_MR4_RPTM_DEFVAL #undef DDR_PHY_MR4_RPTM_SHIFT #undef DDR_PHY_MR4_RPTM_MASK -#define DDR_PHY_MR4_RPTM_DEFVAL 0x00000000 -#define DDR_PHY_MR4_RPTM_SHIFT 10 -#define DDR_PHY_MR4_RPTM_MASK 0x00000400U +#define DDR_PHY_MR4_RPTM_DEFVAL 0x00000000 +#define DDR_PHY_MR4_RPTM_SHIFT 10 +#define DDR_PHY_MR4_RPTM_MASK 0x00000400U -/*Self Refresh Abort*/ +/* +* Self Refresh Abort +*/ #undef DDR_PHY_MR4_SRA_DEFVAL #undef DDR_PHY_MR4_SRA_SHIFT #undef DDR_PHY_MR4_SRA_MASK -#define DDR_PHY_MR4_SRA_DEFVAL 0x00000000 -#define DDR_PHY_MR4_SRA_SHIFT 9 -#define DDR_PHY_MR4_SRA_MASK 0x00000200U +#define DDR_PHY_MR4_SRA_DEFVAL 0x00000000 +#define DDR_PHY_MR4_SRA_SHIFT 9 +#define DDR_PHY_MR4_SRA_MASK 0x00000200U -/*CS to Command Latency Mode*/ +/* +* CS to Command Latency Mode +*/ #undef DDR_PHY_MR4_CS2CMDL_DEFVAL #undef DDR_PHY_MR4_CS2CMDL_SHIFT #undef DDR_PHY_MR4_CS2CMDL_MASK -#define DDR_PHY_MR4_CS2CMDL_DEFVAL 0x00000000 -#define DDR_PHY_MR4_CS2CMDL_SHIFT 6 -#define DDR_PHY_MR4_CS2CMDL_MASK 0x000001C0U +#define DDR_PHY_MR4_CS2CMDL_DEFVAL 0x00000000 +#define DDR_PHY_MR4_CS2CMDL_SHIFT 6 +#define DDR_PHY_MR4_CS2CMDL_MASK 0x000001C0U -/*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/ +/* +* These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. +*/ #undef DDR_PHY_MR4_RSVD1_DEFVAL #undef DDR_PHY_MR4_RSVD1_SHIFT #undef DDR_PHY_MR4_RSVD1_MASK -#define DDR_PHY_MR4_RSVD1_DEFVAL 0x00000000 -#define DDR_PHY_MR4_RSVD1_SHIFT 5 -#define DDR_PHY_MR4_RSVD1_MASK 0x00000020U +#define DDR_PHY_MR4_RSVD1_DEFVAL 0x00000000 +#define DDR_PHY_MR4_RSVD1_SHIFT 5 +#define DDR_PHY_MR4_RSVD1_MASK 0x00000020U -/*Internal VREF Monitor*/ +/* +* Internal VREF Monitor +*/ #undef DDR_PHY_MR4_IVM_DEFVAL #undef DDR_PHY_MR4_IVM_SHIFT #undef DDR_PHY_MR4_IVM_MASK -#define DDR_PHY_MR4_IVM_DEFVAL 0x00000000 -#define DDR_PHY_MR4_IVM_SHIFT 4 -#define DDR_PHY_MR4_IVM_MASK 0x00000010U +#define DDR_PHY_MR4_IVM_DEFVAL 0x00000000 +#define DDR_PHY_MR4_IVM_SHIFT 4 +#define DDR_PHY_MR4_IVM_MASK 0x00000010U -/*Temperature Controlled Refresh Mode*/ +/* +* Temperature Controlled Refresh Mode +*/ #undef DDR_PHY_MR4_TCRM_DEFVAL #undef DDR_PHY_MR4_TCRM_SHIFT #undef DDR_PHY_MR4_TCRM_MASK -#define DDR_PHY_MR4_TCRM_DEFVAL 0x00000000 -#define DDR_PHY_MR4_TCRM_SHIFT 3 -#define DDR_PHY_MR4_TCRM_MASK 0x00000008U +#define DDR_PHY_MR4_TCRM_DEFVAL 0x00000000 +#define DDR_PHY_MR4_TCRM_SHIFT 3 +#define DDR_PHY_MR4_TCRM_MASK 0x00000008U -/*Temperature Controlled Refresh Range*/ +/* +* Temperature Controlled Refresh Range +*/ #undef DDR_PHY_MR4_TCRR_DEFVAL #undef DDR_PHY_MR4_TCRR_SHIFT #undef DDR_PHY_MR4_TCRR_MASK -#define DDR_PHY_MR4_TCRR_DEFVAL 0x00000000 -#define DDR_PHY_MR4_TCRR_SHIFT 2 -#define DDR_PHY_MR4_TCRR_MASK 0x00000004U +#define DDR_PHY_MR4_TCRR_DEFVAL 0x00000000 +#define DDR_PHY_MR4_TCRR_SHIFT 2 +#define DDR_PHY_MR4_TCRR_MASK 0x00000004U -/*Maximum Power Down Mode*/ +/* +* Maximum Power Down Mode +*/ #undef DDR_PHY_MR4_MPDM_DEFVAL #undef DDR_PHY_MR4_MPDM_SHIFT #undef DDR_PHY_MR4_MPDM_MASK -#define DDR_PHY_MR4_MPDM_DEFVAL 0x00000000 -#define DDR_PHY_MR4_MPDM_SHIFT 1 -#define DDR_PHY_MR4_MPDM_MASK 0x00000002U +#define DDR_PHY_MR4_MPDM_DEFVAL 0x00000000 +#define DDR_PHY_MR4_MPDM_SHIFT 1 +#define DDR_PHY_MR4_MPDM_MASK 0x00000002U -/*This is a JEDEC reserved bit and is recommended by JEDEC to be programmed to 0x0.*/ +/* +* This is a JEDEC reserved bit and is recommended by JEDEC to be programme + * d to 0x0. +*/ #undef DDR_PHY_MR4_RSVD_0_DEFVAL #undef DDR_PHY_MR4_RSVD_0_SHIFT #undef DDR_PHY_MR4_RSVD_0_MASK -#define DDR_PHY_MR4_RSVD_0_DEFVAL 0x00000000 -#define DDR_PHY_MR4_RSVD_0_SHIFT 0 -#define DDR_PHY_MR4_RSVD_0_MASK 0x00000001U +#define DDR_PHY_MR4_RSVD_0_DEFVAL 0x00000000 +#define DDR_PHY_MR4_RSVD_0_SHIFT 0 +#define DDR_PHY_MR4_RSVD_0_MASK 0x00000001U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_MR5_RESERVED_31_16_DEFVAL #undef DDR_PHY_MR5_RESERVED_31_16_SHIFT #undef DDR_PHY_MR5_RESERVED_31_16_MASK -#define DDR_PHY_MR5_RESERVED_31_16_DEFVAL 0x00000000 -#define DDR_PHY_MR5_RESERVED_31_16_SHIFT 16 -#define DDR_PHY_MR5_RESERVED_31_16_MASK 0xFFFF0000U +#define DDR_PHY_MR5_RESERVED_31_16_DEFVAL 0x00000000 +#define DDR_PHY_MR5_RESERVED_31_16_SHIFT 16 +#define DDR_PHY_MR5_RESERVED_31_16_MASK 0xFFFF0000U -/*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/ +/* +* These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. +*/ #undef DDR_PHY_MR5_RSVD_DEFVAL #undef DDR_PHY_MR5_RSVD_SHIFT #undef DDR_PHY_MR5_RSVD_MASK -#define DDR_PHY_MR5_RSVD_DEFVAL 0x00000000 -#define DDR_PHY_MR5_RSVD_SHIFT 13 -#define DDR_PHY_MR5_RSVD_MASK 0x0000E000U +#define DDR_PHY_MR5_RSVD_DEFVAL 0x00000000 +#define DDR_PHY_MR5_RSVD_SHIFT 13 +#define DDR_PHY_MR5_RSVD_MASK 0x0000E000U -/*Read DBI*/ +/* +* Read DBI +*/ #undef DDR_PHY_MR5_RDBI_DEFVAL #undef DDR_PHY_MR5_RDBI_SHIFT #undef DDR_PHY_MR5_RDBI_MASK -#define DDR_PHY_MR5_RDBI_DEFVAL 0x00000000 -#define DDR_PHY_MR5_RDBI_SHIFT 12 -#define DDR_PHY_MR5_RDBI_MASK 0x00001000U +#define DDR_PHY_MR5_RDBI_DEFVAL 0x00000000 +#define DDR_PHY_MR5_RDBI_SHIFT 12 +#define DDR_PHY_MR5_RDBI_MASK 0x00001000U -/*Write DBI*/ +/* +* Write DBI +*/ #undef DDR_PHY_MR5_WDBI_DEFVAL #undef DDR_PHY_MR5_WDBI_SHIFT #undef DDR_PHY_MR5_WDBI_MASK -#define DDR_PHY_MR5_WDBI_DEFVAL 0x00000000 -#define DDR_PHY_MR5_WDBI_SHIFT 11 -#define DDR_PHY_MR5_WDBI_MASK 0x00000800U +#define DDR_PHY_MR5_WDBI_DEFVAL 0x00000000 +#define DDR_PHY_MR5_WDBI_SHIFT 11 +#define DDR_PHY_MR5_WDBI_MASK 0x00000800U -/*Data Mask*/ +/* +* Data Mask +*/ #undef DDR_PHY_MR5_DM_DEFVAL #undef DDR_PHY_MR5_DM_SHIFT #undef DDR_PHY_MR5_DM_MASK -#define DDR_PHY_MR5_DM_DEFVAL 0x00000000 -#define DDR_PHY_MR5_DM_SHIFT 10 -#define DDR_PHY_MR5_DM_MASK 0x00000400U +#define DDR_PHY_MR5_DM_DEFVAL 0x00000000 +#define DDR_PHY_MR5_DM_SHIFT 10 +#define DDR_PHY_MR5_DM_MASK 0x00000400U -/*CA Parity Persistent Error*/ +/* +* CA Parity Persistent Error +*/ #undef DDR_PHY_MR5_CAPPE_DEFVAL #undef DDR_PHY_MR5_CAPPE_SHIFT #undef DDR_PHY_MR5_CAPPE_MASK -#define DDR_PHY_MR5_CAPPE_DEFVAL 0x00000000 -#define DDR_PHY_MR5_CAPPE_SHIFT 9 -#define DDR_PHY_MR5_CAPPE_MASK 0x00000200U +#define DDR_PHY_MR5_CAPPE_DEFVAL 0x00000000 +#define DDR_PHY_MR5_CAPPE_SHIFT 9 +#define DDR_PHY_MR5_CAPPE_MASK 0x00000200U -/*RTT_PARK*/ +/* +* RTT_PARK +*/ #undef DDR_PHY_MR5_RTTPARK_DEFVAL #undef DDR_PHY_MR5_RTTPARK_SHIFT #undef DDR_PHY_MR5_RTTPARK_MASK -#define DDR_PHY_MR5_RTTPARK_DEFVAL 0x00000000 -#define DDR_PHY_MR5_RTTPARK_SHIFT 6 -#define DDR_PHY_MR5_RTTPARK_MASK 0x000001C0U +#define DDR_PHY_MR5_RTTPARK_DEFVAL 0x00000000 +#define DDR_PHY_MR5_RTTPARK_SHIFT 6 +#define DDR_PHY_MR5_RTTPARK_MASK 0x000001C0U -/*ODT Input Buffer during Power Down mode*/ +/* +* ODT Input Buffer during Power Down mode +*/ #undef DDR_PHY_MR5_ODTIBPD_DEFVAL #undef DDR_PHY_MR5_ODTIBPD_SHIFT #undef DDR_PHY_MR5_ODTIBPD_MASK -#define DDR_PHY_MR5_ODTIBPD_DEFVAL 0x00000000 -#define DDR_PHY_MR5_ODTIBPD_SHIFT 5 -#define DDR_PHY_MR5_ODTIBPD_MASK 0x00000020U +#define DDR_PHY_MR5_ODTIBPD_DEFVAL 0x00000000 +#define DDR_PHY_MR5_ODTIBPD_SHIFT 5 +#define DDR_PHY_MR5_ODTIBPD_MASK 0x00000020U -/*C/A Parity Error Status*/ +/* +* C/A Parity Error Status +*/ #undef DDR_PHY_MR5_CAPES_DEFVAL #undef DDR_PHY_MR5_CAPES_SHIFT #undef DDR_PHY_MR5_CAPES_MASK -#define DDR_PHY_MR5_CAPES_DEFVAL 0x00000000 -#define DDR_PHY_MR5_CAPES_SHIFT 4 -#define DDR_PHY_MR5_CAPES_MASK 0x00000010U +#define DDR_PHY_MR5_CAPES_DEFVAL 0x00000000 +#define DDR_PHY_MR5_CAPES_SHIFT 4 +#define DDR_PHY_MR5_CAPES_MASK 0x00000010U -/*CRC Error Clear*/ +/* +* CRC Error Clear +*/ #undef DDR_PHY_MR5_CRCEC_DEFVAL #undef DDR_PHY_MR5_CRCEC_SHIFT #undef DDR_PHY_MR5_CRCEC_MASK -#define DDR_PHY_MR5_CRCEC_DEFVAL 0x00000000 -#define DDR_PHY_MR5_CRCEC_SHIFT 3 -#define DDR_PHY_MR5_CRCEC_MASK 0x00000008U +#define DDR_PHY_MR5_CRCEC_DEFVAL 0x00000000 +#define DDR_PHY_MR5_CRCEC_SHIFT 3 +#define DDR_PHY_MR5_CRCEC_MASK 0x00000008U -/*C/A Parity Latency Mode*/ +/* +* C/A Parity Latency Mode +*/ #undef DDR_PHY_MR5_CAPM_DEFVAL #undef DDR_PHY_MR5_CAPM_SHIFT #undef DDR_PHY_MR5_CAPM_MASK -#define DDR_PHY_MR5_CAPM_DEFVAL 0x00000000 -#define DDR_PHY_MR5_CAPM_SHIFT 0 -#define DDR_PHY_MR5_CAPM_MASK 0x00000007U +#define DDR_PHY_MR5_CAPM_DEFVAL 0x00000000 +#define DDR_PHY_MR5_CAPM_SHIFT 0 +#define DDR_PHY_MR5_CAPM_MASK 0x00000007U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_MR6_RESERVED_31_16_DEFVAL #undef DDR_PHY_MR6_RESERVED_31_16_SHIFT #undef DDR_PHY_MR6_RESERVED_31_16_MASK -#define DDR_PHY_MR6_RESERVED_31_16_DEFVAL 0x00000000 -#define DDR_PHY_MR6_RESERVED_31_16_SHIFT 16 -#define DDR_PHY_MR6_RESERVED_31_16_MASK 0xFFFF0000U +#define DDR_PHY_MR6_RESERVED_31_16_DEFVAL 0x00000000 +#define DDR_PHY_MR6_RESERVED_31_16_SHIFT 16 +#define DDR_PHY_MR6_RESERVED_31_16_MASK 0xFFFF0000U -/*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/ +/* +* These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. +*/ #undef DDR_PHY_MR6_RSVD_15_13_DEFVAL #undef DDR_PHY_MR6_RSVD_15_13_SHIFT #undef DDR_PHY_MR6_RSVD_15_13_MASK -#define DDR_PHY_MR6_RSVD_15_13_DEFVAL 0x00000000 -#define DDR_PHY_MR6_RSVD_15_13_SHIFT 13 -#define DDR_PHY_MR6_RSVD_15_13_MASK 0x0000E000U +#define DDR_PHY_MR6_RSVD_15_13_DEFVAL 0x00000000 +#define DDR_PHY_MR6_RSVD_15_13_SHIFT 13 +#define DDR_PHY_MR6_RSVD_15_13_MASK 0x0000E000U -/*CAS_n to CAS_n command delay for same bank group (tCCD_L)*/ +/* +* CAS_n to CAS_n command delay for same bank group (tCCD_L) +*/ #undef DDR_PHY_MR6_TCCDL_DEFVAL #undef DDR_PHY_MR6_TCCDL_SHIFT #undef DDR_PHY_MR6_TCCDL_MASK -#define DDR_PHY_MR6_TCCDL_DEFVAL 0x00000000 -#define DDR_PHY_MR6_TCCDL_SHIFT 10 -#define DDR_PHY_MR6_TCCDL_MASK 0x00001C00U +#define DDR_PHY_MR6_TCCDL_DEFVAL 0x00000000 +#define DDR_PHY_MR6_TCCDL_SHIFT 10 +#define DDR_PHY_MR6_TCCDL_MASK 0x00001C00U -/*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/ +/* +* These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. +*/ #undef DDR_PHY_MR6_RSVD_9_8_DEFVAL #undef DDR_PHY_MR6_RSVD_9_8_SHIFT #undef DDR_PHY_MR6_RSVD_9_8_MASK -#define DDR_PHY_MR6_RSVD_9_8_DEFVAL 0x00000000 -#define DDR_PHY_MR6_RSVD_9_8_SHIFT 8 -#define DDR_PHY_MR6_RSVD_9_8_MASK 0x00000300U +#define DDR_PHY_MR6_RSVD_9_8_DEFVAL 0x00000000 +#define DDR_PHY_MR6_RSVD_9_8_SHIFT 8 +#define DDR_PHY_MR6_RSVD_9_8_MASK 0x00000300U -/*VrefDQ Training Enable*/ +/* +* VrefDQ Training Enable +*/ #undef DDR_PHY_MR6_VDDQTEN_DEFVAL #undef DDR_PHY_MR6_VDDQTEN_SHIFT #undef DDR_PHY_MR6_VDDQTEN_MASK -#define DDR_PHY_MR6_VDDQTEN_DEFVAL 0x00000000 -#define DDR_PHY_MR6_VDDQTEN_SHIFT 7 -#define DDR_PHY_MR6_VDDQTEN_MASK 0x00000080U +#define DDR_PHY_MR6_VDDQTEN_DEFVAL 0x00000000 +#define DDR_PHY_MR6_VDDQTEN_SHIFT 7 +#define DDR_PHY_MR6_VDDQTEN_MASK 0x00000080U -/*VrefDQ Training Range*/ +/* +* VrefDQ Training Range +*/ #undef DDR_PHY_MR6_VDQTRG_DEFVAL #undef DDR_PHY_MR6_VDQTRG_SHIFT #undef DDR_PHY_MR6_VDQTRG_MASK -#define DDR_PHY_MR6_VDQTRG_DEFVAL 0x00000000 -#define DDR_PHY_MR6_VDQTRG_SHIFT 6 -#define DDR_PHY_MR6_VDQTRG_MASK 0x00000040U +#define DDR_PHY_MR6_VDQTRG_DEFVAL 0x00000000 +#define DDR_PHY_MR6_VDQTRG_SHIFT 6 +#define DDR_PHY_MR6_VDQTRG_MASK 0x00000040U -/*VrefDQ Training Values*/ +/* +* VrefDQ Training Values +*/ #undef DDR_PHY_MR6_VDQTVAL_DEFVAL #undef DDR_PHY_MR6_VDQTVAL_SHIFT #undef DDR_PHY_MR6_VDQTVAL_MASK -#define DDR_PHY_MR6_VDQTVAL_DEFVAL 0x00000000 -#define DDR_PHY_MR6_VDQTVAL_SHIFT 0 -#define DDR_PHY_MR6_VDQTVAL_MASK 0x0000003FU +#define DDR_PHY_MR6_VDQTVAL_DEFVAL 0x00000000 +#define DDR_PHY_MR6_VDQTVAL_SHIFT 0 +#define DDR_PHY_MR6_VDQTVAL_MASK 0x0000003FU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_MR11_RESERVED_31_8_DEFVAL #undef DDR_PHY_MR11_RESERVED_31_8_SHIFT #undef DDR_PHY_MR11_RESERVED_31_8_MASK -#define DDR_PHY_MR11_RESERVED_31_8_DEFVAL 0x00000000 -#define DDR_PHY_MR11_RESERVED_31_8_SHIFT 8 -#define DDR_PHY_MR11_RESERVED_31_8_MASK 0xFFFFFF00U +#define DDR_PHY_MR11_RESERVED_31_8_DEFVAL 0x00000000 +#define DDR_PHY_MR11_RESERVED_31_8_SHIFT 8 +#define DDR_PHY_MR11_RESERVED_31_8_MASK 0xFFFFFF00U -/*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/ +/* +* These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. +*/ #undef DDR_PHY_MR11_RSVD_DEFVAL #undef DDR_PHY_MR11_RSVD_SHIFT #undef DDR_PHY_MR11_RSVD_MASK -#define DDR_PHY_MR11_RSVD_DEFVAL 0x00000000 -#define DDR_PHY_MR11_RSVD_SHIFT 3 -#define DDR_PHY_MR11_RSVD_MASK 0x000000F8U +#define DDR_PHY_MR11_RSVD_DEFVAL 0x00000000 +#define DDR_PHY_MR11_RSVD_SHIFT 3 +#define DDR_PHY_MR11_RSVD_MASK 0x000000F8U -/*Power Down Control*/ +/* +* Power Down Control +*/ #undef DDR_PHY_MR11_PDCTL_DEFVAL #undef DDR_PHY_MR11_PDCTL_SHIFT #undef DDR_PHY_MR11_PDCTL_MASK -#define DDR_PHY_MR11_PDCTL_DEFVAL 0x00000000 -#define DDR_PHY_MR11_PDCTL_SHIFT 2 -#define DDR_PHY_MR11_PDCTL_MASK 0x00000004U +#define DDR_PHY_MR11_PDCTL_DEFVAL 0x00000000 +#define DDR_PHY_MR11_PDCTL_SHIFT 2 +#define DDR_PHY_MR11_PDCTL_MASK 0x00000004U -/*DQ Bus Receiver On-Die-Termination*/ +/* +* DQ Bus Receiver On-Die-Termination +*/ #undef DDR_PHY_MR11_DQODT_DEFVAL #undef DDR_PHY_MR11_DQODT_SHIFT #undef DDR_PHY_MR11_DQODT_MASK -#define DDR_PHY_MR11_DQODT_DEFVAL 0x00000000 -#define DDR_PHY_MR11_DQODT_SHIFT 0 -#define DDR_PHY_MR11_DQODT_MASK 0x00000003U +#define DDR_PHY_MR11_DQODT_DEFVAL 0x00000000 +#define DDR_PHY_MR11_DQODT_SHIFT 0 +#define DDR_PHY_MR11_DQODT_MASK 0x00000003U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_MR12_RESERVED_31_8_DEFVAL #undef DDR_PHY_MR12_RESERVED_31_8_SHIFT #undef DDR_PHY_MR12_RESERVED_31_8_MASK -#define DDR_PHY_MR12_RESERVED_31_8_DEFVAL 0x0000004D -#define DDR_PHY_MR12_RESERVED_31_8_SHIFT 8 -#define DDR_PHY_MR12_RESERVED_31_8_MASK 0xFFFFFF00U +#define DDR_PHY_MR12_RESERVED_31_8_DEFVAL 0x0000004D +#define DDR_PHY_MR12_RESERVED_31_8_SHIFT 8 +#define DDR_PHY_MR12_RESERVED_31_8_MASK 0xFFFFFF00U -/*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/ +/* +* These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. +*/ #undef DDR_PHY_MR12_RSVD_DEFVAL #undef DDR_PHY_MR12_RSVD_SHIFT #undef DDR_PHY_MR12_RSVD_MASK -#define DDR_PHY_MR12_RSVD_DEFVAL 0x0000004D -#define DDR_PHY_MR12_RSVD_SHIFT 7 -#define DDR_PHY_MR12_RSVD_MASK 0x00000080U +#define DDR_PHY_MR12_RSVD_DEFVAL 0x0000004D +#define DDR_PHY_MR12_RSVD_SHIFT 7 +#define DDR_PHY_MR12_RSVD_MASK 0x00000080U -/*VREF_CA Range Select.*/ +/* +* VREF_CA Range Select. +*/ #undef DDR_PHY_MR12_VR_CA_DEFVAL #undef DDR_PHY_MR12_VR_CA_SHIFT #undef DDR_PHY_MR12_VR_CA_MASK -#define DDR_PHY_MR12_VR_CA_DEFVAL 0x0000004D -#define DDR_PHY_MR12_VR_CA_SHIFT 6 -#define DDR_PHY_MR12_VR_CA_MASK 0x00000040U +#define DDR_PHY_MR12_VR_CA_DEFVAL 0x0000004D +#define DDR_PHY_MR12_VR_CA_SHIFT 6 +#define DDR_PHY_MR12_VR_CA_MASK 0x00000040U -/*Controls the VREF(ca) levels for Frequency-Set-Point[1:0].*/ +/* +* Controls the VREF(ca) levels for Frequency-Set-Point[1:0]. +*/ #undef DDR_PHY_MR12_VREF_CA_DEFVAL #undef DDR_PHY_MR12_VREF_CA_SHIFT #undef DDR_PHY_MR12_VREF_CA_MASK -#define DDR_PHY_MR12_VREF_CA_DEFVAL 0x0000004D -#define DDR_PHY_MR12_VREF_CA_SHIFT 0 -#define DDR_PHY_MR12_VREF_CA_MASK 0x0000003FU +#define DDR_PHY_MR12_VREF_CA_DEFVAL 0x0000004D +#define DDR_PHY_MR12_VREF_CA_SHIFT 0 +#define DDR_PHY_MR12_VREF_CA_MASK 0x0000003FU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_MR13_RESERVED_31_8_DEFVAL #undef DDR_PHY_MR13_RESERVED_31_8_SHIFT #undef DDR_PHY_MR13_RESERVED_31_8_MASK -#define DDR_PHY_MR13_RESERVED_31_8_DEFVAL 0x00000000 -#define DDR_PHY_MR13_RESERVED_31_8_SHIFT 8 -#define DDR_PHY_MR13_RESERVED_31_8_MASK 0xFFFFFF00U +#define DDR_PHY_MR13_RESERVED_31_8_DEFVAL 0x00000000 +#define DDR_PHY_MR13_RESERVED_31_8_SHIFT 8 +#define DDR_PHY_MR13_RESERVED_31_8_MASK 0xFFFFFF00U -/*Frequency Set Point Operation Mode*/ +/* +* Frequency Set Point Operation Mode +*/ #undef DDR_PHY_MR13_FSPOP_DEFVAL #undef DDR_PHY_MR13_FSPOP_SHIFT #undef DDR_PHY_MR13_FSPOP_MASK -#define DDR_PHY_MR13_FSPOP_DEFVAL 0x00000000 -#define DDR_PHY_MR13_FSPOP_SHIFT 7 -#define DDR_PHY_MR13_FSPOP_MASK 0x00000080U +#define DDR_PHY_MR13_FSPOP_DEFVAL 0x00000000 +#define DDR_PHY_MR13_FSPOP_SHIFT 7 +#define DDR_PHY_MR13_FSPOP_MASK 0x00000080U -/*Frequency Set Point Write Enable*/ +/* +* Frequency Set Point Write Enable +*/ #undef DDR_PHY_MR13_FSPWR_DEFVAL #undef DDR_PHY_MR13_FSPWR_SHIFT #undef DDR_PHY_MR13_FSPWR_MASK -#define DDR_PHY_MR13_FSPWR_DEFVAL 0x00000000 -#define DDR_PHY_MR13_FSPWR_SHIFT 6 -#define DDR_PHY_MR13_FSPWR_MASK 0x00000040U +#define DDR_PHY_MR13_FSPWR_DEFVAL 0x00000000 +#define DDR_PHY_MR13_FSPWR_SHIFT 6 +#define DDR_PHY_MR13_FSPWR_MASK 0x00000040U -/*Data Mask Enable*/ +/* +* Data Mask Enable +*/ #undef DDR_PHY_MR13_DMD_DEFVAL #undef DDR_PHY_MR13_DMD_SHIFT #undef DDR_PHY_MR13_DMD_MASK -#define DDR_PHY_MR13_DMD_DEFVAL 0x00000000 -#define DDR_PHY_MR13_DMD_SHIFT 5 -#define DDR_PHY_MR13_DMD_MASK 0x00000020U +#define DDR_PHY_MR13_DMD_DEFVAL 0x00000000 +#define DDR_PHY_MR13_DMD_SHIFT 5 +#define DDR_PHY_MR13_DMD_MASK 0x00000020U -/*Refresh Rate Option*/ +/* +* Refresh Rate Option +*/ #undef DDR_PHY_MR13_RRO_DEFVAL #undef DDR_PHY_MR13_RRO_SHIFT #undef DDR_PHY_MR13_RRO_MASK -#define DDR_PHY_MR13_RRO_DEFVAL 0x00000000 -#define DDR_PHY_MR13_RRO_SHIFT 4 -#define DDR_PHY_MR13_RRO_MASK 0x00000010U +#define DDR_PHY_MR13_RRO_DEFVAL 0x00000000 +#define DDR_PHY_MR13_RRO_SHIFT 4 +#define DDR_PHY_MR13_RRO_MASK 0x00000010U -/*VREF Current Generator*/ +/* +* VREF Current Generator +*/ #undef DDR_PHY_MR13_VRCG_DEFVAL #undef DDR_PHY_MR13_VRCG_SHIFT #undef DDR_PHY_MR13_VRCG_MASK -#define DDR_PHY_MR13_VRCG_DEFVAL 0x00000000 -#define DDR_PHY_MR13_VRCG_SHIFT 3 -#define DDR_PHY_MR13_VRCG_MASK 0x00000008U +#define DDR_PHY_MR13_VRCG_DEFVAL 0x00000000 +#define DDR_PHY_MR13_VRCG_SHIFT 3 +#define DDR_PHY_MR13_VRCG_MASK 0x00000008U -/*VREF Output*/ +/* +* VREF Output +*/ #undef DDR_PHY_MR13_VRO_DEFVAL #undef DDR_PHY_MR13_VRO_SHIFT #undef DDR_PHY_MR13_VRO_MASK -#define DDR_PHY_MR13_VRO_DEFVAL 0x00000000 -#define DDR_PHY_MR13_VRO_SHIFT 2 -#define DDR_PHY_MR13_VRO_MASK 0x00000004U +#define DDR_PHY_MR13_VRO_DEFVAL 0x00000000 +#define DDR_PHY_MR13_VRO_SHIFT 2 +#define DDR_PHY_MR13_VRO_MASK 0x00000004U -/*Read Preamble Training Mode*/ +/* +* Read Preamble Training Mode +*/ #undef DDR_PHY_MR13_RPT_DEFVAL #undef DDR_PHY_MR13_RPT_SHIFT #undef DDR_PHY_MR13_RPT_MASK -#define DDR_PHY_MR13_RPT_DEFVAL 0x00000000 -#define DDR_PHY_MR13_RPT_SHIFT 1 -#define DDR_PHY_MR13_RPT_MASK 0x00000002U +#define DDR_PHY_MR13_RPT_DEFVAL 0x00000000 +#define DDR_PHY_MR13_RPT_SHIFT 1 +#define DDR_PHY_MR13_RPT_MASK 0x00000002U -/*Command Bus Training*/ +/* +* Command Bus Training +*/ #undef DDR_PHY_MR13_CBT_DEFVAL #undef DDR_PHY_MR13_CBT_SHIFT #undef DDR_PHY_MR13_CBT_MASK -#define DDR_PHY_MR13_CBT_DEFVAL 0x00000000 -#define DDR_PHY_MR13_CBT_SHIFT 0 -#define DDR_PHY_MR13_CBT_MASK 0x00000001U +#define DDR_PHY_MR13_CBT_DEFVAL 0x00000000 +#define DDR_PHY_MR13_CBT_SHIFT 0 +#define DDR_PHY_MR13_CBT_MASK 0x00000001U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_MR14_RESERVED_31_8_DEFVAL #undef DDR_PHY_MR14_RESERVED_31_8_SHIFT #undef DDR_PHY_MR14_RESERVED_31_8_MASK -#define DDR_PHY_MR14_RESERVED_31_8_DEFVAL 0x0000004D -#define DDR_PHY_MR14_RESERVED_31_8_SHIFT 8 -#define DDR_PHY_MR14_RESERVED_31_8_MASK 0xFFFFFF00U +#define DDR_PHY_MR14_RESERVED_31_8_DEFVAL 0x0000004D +#define DDR_PHY_MR14_RESERVED_31_8_SHIFT 8 +#define DDR_PHY_MR14_RESERVED_31_8_MASK 0xFFFFFF00U -/*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/ +/* +* These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. +*/ #undef DDR_PHY_MR14_RSVD_DEFVAL #undef DDR_PHY_MR14_RSVD_SHIFT #undef DDR_PHY_MR14_RSVD_MASK -#define DDR_PHY_MR14_RSVD_DEFVAL 0x0000004D -#define DDR_PHY_MR14_RSVD_SHIFT 7 -#define DDR_PHY_MR14_RSVD_MASK 0x00000080U +#define DDR_PHY_MR14_RSVD_DEFVAL 0x0000004D +#define DDR_PHY_MR14_RSVD_SHIFT 7 +#define DDR_PHY_MR14_RSVD_MASK 0x00000080U -/*VREFDQ Range Selects.*/ +/* +* VREFDQ Range Selects. +*/ #undef DDR_PHY_MR14_VR_DQ_DEFVAL #undef DDR_PHY_MR14_VR_DQ_SHIFT #undef DDR_PHY_MR14_VR_DQ_MASK -#define DDR_PHY_MR14_VR_DQ_DEFVAL 0x0000004D -#define DDR_PHY_MR14_VR_DQ_SHIFT 6 -#define DDR_PHY_MR14_VR_DQ_MASK 0x00000040U +#define DDR_PHY_MR14_VR_DQ_DEFVAL 0x0000004D +#define DDR_PHY_MR14_VR_DQ_SHIFT 6 +#define DDR_PHY_MR14_VR_DQ_MASK 0x00000040U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_MR14_VREF_DQ_DEFVAL #undef DDR_PHY_MR14_VREF_DQ_SHIFT #undef DDR_PHY_MR14_VREF_DQ_MASK -#define DDR_PHY_MR14_VREF_DQ_DEFVAL 0x0000004D -#define DDR_PHY_MR14_VREF_DQ_SHIFT 0 -#define DDR_PHY_MR14_VREF_DQ_MASK 0x0000003FU +#define DDR_PHY_MR14_VREF_DQ_DEFVAL 0x0000004D +#define DDR_PHY_MR14_VREF_DQ_SHIFT 0 +#define DDR_PHY_MR14_VREF_DQ_MASK 0x0000003FU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_MR22_RESERVED_31_8_DEFVAL #undef DDR_PHY_MR22_RESERVED_31_8_SHIFT #undef DDR_PHY_MR22_RESERVED_31_8_MASK -#define DDR_PHY_MR22_RESERVED_31_8_DEFVAL 0x00000000 -#define DDR_PHY_MR22_RESERVED_31_8_SHIFT 8 -#define DDR_PHY_MR22_RESERVED_31_8_MASK 0xFFFFFF00U +#define DDR_PHY_MR22_RESERVED_31_8_DEFVAL 0x00000000 +#define DDR_PHY_MR22_RESERVED_31_8_SHIFT 8 +#define DDR_PHY_MR22_RESERVED_31_8_MASK 0xFFFFFF00U -/*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/ +/* +* These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. +*/ #undef DDR_PHY_MR22_RSVD_DEFVAL #undef DDR_PHY_MR22_RSVD_SHIFT #undef DDR_PHY_MR22_RSVD_MASK -#define DDR_PHY_MR22_RSVD_DEFVAL 0x00000000 -#define DDR_PHY_MR22_RSVD_SHIFT 6 -#define DDR_PHY_MR22_RSVD_MASK 0x000000C0U +#define DDR_PHY_MR22_RSVD_DEFVAL 0x00000000 +#define DDR_PHY_MR22_RSVD_SHIFT 6 +#define DDR_PHY_MR22_RSVD_MASK 0x000000C0U -/*CA ODT termination disable.*/ +/* +* CA ODT termination disable. +*/ #undef DDR_PHY_MR22_ODTD_CA_DEFVAL #undef DDR_PHY_MR22_ODTD_CA_SHIFT #undef DDR_PHY_MR22_ODTD_CA_MASK -#define DDR_PHY_MR22_ODTD_CA_DEFVAL 0x00000000 -#define DDR_PHY_MR22_ODTD_CA_SHIFT 5 -#define DDR_PHY_MR22_ODTD_CA_MASK 0x00000020U +#define DDR_PHY_MR22_ODTD_CA_DEFVAL 0x00000000 +#define DDR_PHY_MR22_ODTD_CA_SHIFT 5 +#define DDR_PHY_MR22_ODTD_CA_MASK 0x00000020U -/*ODT CS override.*/ +/* +* ODT CS override. +*/ #undef DDR_PHY_MR22_ODTE_CS_DEFVAL #undef DDR_PHY_MR22_ODTE_CS_SHIFT #undef DDR_PHY_MR22_ODTE_CS_MASK -#define DDR_PHY_MR22_ODTE_CS_DEFVAL 0x00000000 -#define DDR_PHY_MR22_ODTE_CS_SHIFT 4 -#define DDR_PHY_MR22_ODTE_CS_MASK 0x00000010U +#define DDR_PHY_MR22_ODTE_CS_DEFVAL 0x00000000 +#define DDR_PHY_MR22_ODTE_CS_SHIFT 4 +#define DDR_PHY_MR22_ODTE_CS_MASK 0x00000010U -/*ODT CK override.*/ +/* +* ODT CK override. +*/ #undef DDR_PHY_MR22_ODTE_CK_DEFVAL #undef DDR_PHY_MR22_ODTE_CK_SHIFT #undef DDR_PHY_MR22_ODTE_CK_MASK -#define DDR_PHY_MR22_ODTE_CK_DEFVAL 0x00000000 -#define DDR_PHY_MR22_ODTE_CK_SHIFT 3 -#define DDR_PHY_MR22_ODTE_CK_MASK 0x00000008U +#define DDR_PHY_MR22_ODTE_CK_DEFVAL 0x00000000 +#define DDR_PHY_MR22_ODTE_CK_SHIFT 3 +#define DDR_PHY_MR22_ODTE_CK_MASK 0x00000008U -/*Controller ODT value for VOH calibration.*/ +/* +* Controller ODT value for VOH calibration. +*/ #undef DDR_PHY_MR22_CODT_DEFVAL #undef DDR_PHY_MR22_CODT_SHIFT #undef DDR_PHY_MR22_CODT_MASK -#define DDR_PHY_MR22_CODT_DEFVAL 0x00000000 -#define DDR_PHY_MR22_CODT_SHIFT 0 -#define DDR_PHY_MR22_CODT_MASK 0x00000007U +#define DDR_PHY_MR22_CODT_DEFVAL 0x00000000 +#define DDR_PHY_MR22_CODT_SHIFT 0 +#define DDR_PHY_MR22_CODT_MASK 0x00000007U -/*Refresh During Training*/ +/* +* Refresh During Training +*/ #undef DDR_PHY_DTCR0_RFSHDT_DEFVAL #undef DDR_PHY_DTCR0_RFSHDT_SHIFT #undef DDR_PHY_DTCR0_RFSHDT_MASK -#define DDR_PHY_DTCR0_RFSHDT_DEFVAL 0x800091C7 -#define DDR_PHY_DTCR0_RFSHDT_SHIFT 28 -#define DDR_PHY_DTCR0_RFSHDT_MASK 0xF0000000U +#define DDR_PHY_DTCR0_RFSHDT_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_RFSHDT_SHIFT 28 +#define DDR_PHY_DTCR0_RFSHDT_MASK 0xF0000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTCR0_RESERVED_27_26_DEFVAL #undef DDR_PHY_DTCR0_RESERVED_27_26_SHIFT #undef DDR_PHY_DTCR0_RESERVED_27_26_MASK -#define DDR_PHY_DTCR0_RESERVED_27_26_DEFVAL 0x800091C7 -#define DDR_PHY_DTCR0_RESERVED_27_26_SHIFT 26 -#define DDR_PHY_DTCR0_RESERVED_27_26_MASK 0x0C000000U +#define DDR_PHY_DTCR0_RESERVED_27_26_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_RESERVED_27_26_SHIFT 26 +#define DDR_PHY_DTCR0_RESERVED_27_26_MASK 0x0C000000U -/*Data Training Debug Rank Select*/ +/* +* Data Training Debug Rank Select +*/ #undef DDR_PHY_DTCR0_DTDRS_DEFVAL #undef DDR_PHY_DTCR0_DTDRS_SHIFT #undef DDR_PHY_DTCR0_DTDRS_MASK -#define DDR_PHY_DTCR0_DTDRS_DEFVAL 0x800091C7 -#define DDR_PHY_DTCR0_DTDRS_SHIFT 24 -#define DDR_PHY_DTCR0_DTDRS_MASK 0x03000000U +#define DDR_PHY_DTCR0_DTDRS_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_DTDRS_SHIFT 24 +#define DDR_PHY_DTCR0_DTDRS_MASK 0x03000000U -/*Data Training with Early/Extended Gate*/ +/* +* Data Training with Early/Extended Gate +*/ #undef DDR_PHY_DTCR0_DTEXG_DEFVAL #undef DDR_PHY_DTCR0_DTEXG_SHIFT #undef DDR_PHY_DTCR0_DTEXG_MASK -#define DDR_PHY_DTCR0_DTEXG_DEFVAL 0x800091C7 -#define DDR_PHY_DTCR0_DTEXG_SHIFT 23 -#define DDR_PHY_DTCR0_DTEXG_MASK 0x00800000U +#define DDR_PHY_DTCR0_DTEXG_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_DTEXG_SHIFT 23 +#define DDR_PHY_DTCR0_DTEXG_MASK 0x00800000U -/*Data Training Extended Write DQS*/ +/* +* Data Training Extended Write DQS +*/ #undef DDR_PHY_DTCR0_DTEXD_DEFVAL #undef DDR_PHY_DTCR0_DTEXD_SHIFT #undef DDR_PHY_DTCR0_DTEXD_MASK -#define DDR_PHY_DTCR0_DTEXD_DEFVAL 0x800091C7 -#define DDR_PHY_DTCR0_DTEXD_SHIFT 22 -#define DDR_PHY_DTCR0_DTEXD_MASK 0x00400000U +#define DDR_PHY_DTCR0_DTEXD_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_DTEXD_SHIFT 22 +#define DDR_PHY_DTCR0_DTEXD_MASK 0x00400000U -/*Data Training Debug Step*/ +/* +* Data Training Debug Step +*/ #undef DDR_PHY_DTCR0_DTDSTP_DEFVAL #undef DDR_PHY_DTCR0_DTDSTP_SHIFT #undef DDR_PHY_DTCR0_DTDSTP_MASK -#define DDR_PHY_DTCR0_DTDSTP_DEFVAL 0x800091C7 -#define DDR_PHY_DTCR0_DTDSTP_SHIFT 21 -#define DDR_PHY_DTCR0_DTDSTP_MASK 0x00200000U +#define DDR_PHY_DTCR0_DTDSTP_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_DTDSTP_SHIFT 21 +#define DDR_PHY_DTCR0_DTDSTP_MASK 0x00200000U -/*Data Training Debug Enable*/ +/* +* Data Training Debug Enable +*/ #undef DDR_PHY_DTCR0_DTDEN_DEFVAL #undef DDR_PHY_DTCR0_DTDEN_SHIFT #undef DDR_PHY_DTCR0_DTDEN_MASK -#define DDR_PHY_DTCR0_DTDEN_DEFVAL 0x800091C7 -#define DDR_PHY_DTCR0_DTDEN_SHIFT 20 -#define DDR_PHY_DTCR0_DTDEN_MASK 0x00100000U +#define DDR_PHY_DTCR0_DTDEN_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_DTDEN_SHIFT 20 +#define DDR_PHY_DTCR0_DTDEN_MASK 0x00100000U -/*Data Training Debug Byte Select*/ +/* +* Data Training Debug Byte Select +*/ #undef DDR_PHY_DTCR0_DTDBS_DEFVAL #undef DDR_PHY_DTCR0_DTDBS_SHIFT #undef DDR_PHY_DTCR0_DTDBS_MASK -#define DDR_PHY_DTCR0_DTDBS_DEFVAL 0x800091C7 -#define DDR_PHY_DTCR0_DTDBS_SHIFT 16 -#define DDR_PHY_DTCR0_DTDBS_MASK 0x000F0000U +#define DDR_PHY_DTCR0_DTDBS_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_DTDBS_SHIFT 16 +#define DDR_PHY_DTCR0_DTDBS_MASK 0x000F0000U -/*Data Training read DBI deskewing configuration*/ +/* +* Data Training read DBI deskewing configuration +*/ #undef DDR_PHY_DTCR0_DTRDBITR_DEFVAL #undef DDR_PHY_DTCR0_DTRDBITR_SHIFT #undef DDR_PHY_DTCR0_DTRDBITR_MASK -#define DDR_PHY_DTCR0_DTRDBITR_DEFVAL 0x800091C7 -#define DDR_PHY_DTCR0_DTRDBITR_SHIFT 14 -#define DDR_PHY_DTCR0_DTRDBITR_MASK 0x0000C000U +#define DDR_PHY_DTCR0_DTRDBITR_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_DTRDBITR_SHIFT 14 +#define DDR_PHY_DTCR0_DTRDBITR_MASK 0x0000C000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTCR0_RESERVED_13_DEFVAL #undef DDR_PHY_DTCR0_RESERVED_13_SHIFT #undef DDR_PHY_DTCR0_RESERVED_13_MASK -#define DDR_PHY_DTCR0_RESERVED_13_DEFVAL 0x800091C7 -#define DDR_PHY_DTCR0_RESERVED_13_SHIFT 13 -#define DDR_PHY_DTCR0_RESERVED_13_MASK 0x00002000U +#define DDR_PHY_DTCR0_RESERVED_13_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_RESERVED_13_SHIFT 13 +#define DDR_PHY_DTCR0_RESERVED_13_MASK 0x00002000U -/*Data Training Write Bit Deskew Data Mask*/ +/* +* Data Training Write Bit Deskew Data Mask +*/ #undef DDR_PHY_DTCR0_DTWBDDM_DEFVAL #undef DDR_PHY_DTCR0_DTWBDDM_SHIFT #undef DDR_PHY_DTCR0_DTWBDDM_MASK -#define DDR_PHY_DTCR0_DTWBDDM_DEFVAL 0x800091C7 -#define DDR_PHY_DTCR0_DTWBDDM_SHIFT 12 -#define DDR_PHY_DTCR0_DTWBDDM_MASK 0x00001000U +#define DDR_PHY_DTCR0_DTWBDDM_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_DTWBDDM_SHIFT 12 +#define DDR_PHY_DTCR0_DTWBDDM_MASK 0x00001000U -/*Refreshes Issued During Entry to Training*/ +/* +* Refreshes Issued During Entry to Training +*/ #undef DDR_PHY_DTCR0_RFSHEN_DEFVAL #undef DDR_PHY_DTCR0_RFSHEN_SHIFT #undef DDR_PHY_DTCR0_RFSHEN_MASK -#define DDR_PHY_DTCR0_RFSHEN_DEFVAL 0x800091C7 -#define DDR_PHY_DTCR0_RFSHEN_SHIFT 8 -#define DDR_PHY_DTCR0_RFSHEN_MASK 0x00000F00U +#define DDR_PHY_DTCR0_RFSHEN_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_RFSHEN_SHIFT 8 +#define DDR_PHY_DTCR0_RFSHEN_MASK 0x00000F00U -/*Data Training Compare Data*/ +/* +* Data Training Compare Data +*/ #undef DDR_PHY_DTCR0_DTCMPD_DEFVAL #undef DDR_PHY_DTCR0_DTCMPD_SHIFT #undef DDR_PHY_DTCR0_DTCMPD_MASK -#define DDR_PHY_DTCR0_DTCMPD_DEFVAL 0x800091C7 -#define DDR_PHY_DTCR0_DTCMPD_SHIFT 7 -#define DDR_PHY_DTCR0_DTCMPD_MASK 0x00000080U +#define DDR_PHY_DTCR0_DTCMPD_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_DTCMPD_SHIFT 7 +#define DDR_PHY_DTCR0_DTCMPD_MASK 0x00000080U -/*Data Training Using MPR*/ +/* +* Data Training Using MPR +*/ #undef DDR_PHY_DTCR0_DTMPR_DEFVAL #undef DDR_PHY_DTCR0_DTMPR_SHIFT #undef DDR_PHY_DTCR0_DTMPR_MASK -#define DDR_PHY_DTCR0_DTMPR_DEFVAL 0x800091C7 -#define DDR_PHY_DTCR0_DTMPR_SHIFT 6 -#define DDR_PHY_DTCR0_DTMPR_MASK 0x00000040U +#define DDR_PHY_DTCR0_DTMPR_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_DTMPR_SHIFT 6 +#define DDR_PHY_DTCR0_DTMPR_MASK 0x00000040U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTCR0_RESERVED_5_4_DEFVAL #undef DDR_PHY_DTCR0_RESERVED_5_4_SHIFT #undef DDR_PHY_DTCR0_RESERVED_5_4_MASK -#define DDR_PHY_DTCR0_RESERVED_5_4_DEFVAL 0x800091C7 -#define DDR_PHY_DTCR0_RESERVED_5_4_SHIFT 4 -#define DDR_PHY_DTCR0_RESERVED_5_4_MASK 0x00000030U +#define DDR_PHY_DTCR0_RESERVED_5_4_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_RESERVED_5_4_SHIFT 4 +#define DDR_PHY_DTCR0_RESERVED_5_4_MASK 0x00000030U -/*Data Training Repeat Number*/ +/* +* Data Training Repeat Number +*/ #undef DDR_PHY_DTCR0_DTRPTN_DEFVAL #undef DDR_PHY_DTCR0_DTRPTN_SHIFT #undef DDR_PHY_DTCR0_DTRPTN_MASK -#define DDR_PHY_DTCR0_DTRPTN_DEFVAL 0x800091C7 -#define DDR_PHY_DTCR0_DTRPTN_SHIFT 0 -#define DDR_PHY_DTCR0_DTRPTN_MASK 0x0000000FU +#define DDR_PHY_DTCR0_DTRPTN_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_DTRPTN_SHIFT 0 +#define DDR_PHY_DTCR0_DTRPTN_MASK 0x0000000FU -/*Rank Enable.*/ +/* +* Rank Enable. +*/ #undef DDR_PHY_DTCR1_RANKEN_RSVD_DEFVAL #undef DDR_PHY_DTCR1_RANKEN_RSVD_SHIFT #undef DDR_PHY_DTCR1_RANKEN_RSVD_MASK -#define DDR_PHY_DTCR1_RANKEN_RSVD_DEFVAL 0x00030237 -#define DDR_PHY_DTCR1_RANKEN_RSVD_SHIFT 18 -#define DDR_PHY_DTCR1_RANKEN_RSVD_MASK 0xFFFC0000U +#define DDR_PHY_DTCR1_RANKEN_RSVD_DEFVAL 0x00030237 +#define DDR_PHY_DTCR1_RANKEN_RSVD_SHIFT 18 +#define DDR_PHY_DTCR1_RANKEN_RSVD_MASK 0xFFFC0000U -/*Rank Enable.*/ +/* +* Rank Enable. +*/ #undef DDR_PHY_DTCR1_RANKEN_DEFVAL #undef DDR_PHY_DTCR1_RANKEN_SHIFT #undef DDR_PHY_DTCR1_RANKEN_MASK -#define DDR_PHY_DTCR1_RANKEN_DEFVAL 0x00030237 -#define DDR_PHY_DTCR1_RANKEN_SHIFT 16 -#define DDR_PHY_DTCR1_RANKEN_MASK 0x00030000U +#define DDR_PHY_DTCR1_RANKEN_DEFVAL 0x00030237 +#define DDR_PHY_DTCR1_RANKEN_SHIFT 16 +#define DDR_PHY_DTCR1_RANKEN_MASK 0x00030000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTCR1_RESERVED_15_14_DEFVAL #undef DDR_PHY_DTCR1_RESERVED_15_14_SHIFT #undef DDR_PHY_DTCR1_RESERVED_15_14_MASK -#define DDR_PHY_DTCR1_RESERVED_15_14_DEFVAL 0x00030237 -#define DDR_PHY_DTCR1_RESERVED_15_14_SHIFT 14 -#define DDR_PHY_DTCR1_RESERVED_15_14_MASK 0x0000C000U +#define DDR_PHY_DTCR1_RESERVED_15_14_DEFVAL 0x00030237 +#define DDR_PHY_DTCR1_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_DTCR1_RESERVED_15_14_MASK 0x0000C000U -/*Data Training Rank*/ +/* +* Data Training Rank +*/ #undef DDR_PHY_DTCR1_DTRANK_DEFVAL #undef DDR_PHY_DTCR1_DTRANK_SHIFT #undef DDR_PHY_DTCR1_DTRANK_MASK -#define DDR_PHY_DTCR1_DTRANK_DEFVAL 0x00030237 -#define DDR_PHY_DTCR1_DTRANK_SHIFT 12 -#define DDR_PHY_DTCR1_DTRANK_MASK 0x00003000U +#define DDR_PHY_DTCR1_DTRANK_DEFVAL 0x00030237 +#define DDR_PHY_DTCR1_DTRANK_SHIFT 12 +#define DDR_PHY_DTCR1_DTRANK_MASK 0x00003000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTCR1_RESERVED_11_DEFVAL #undef DDR_PHY_DTCR1_RESERVED_11_SHIFT #undef DDR_PHY_DTCR1_RESERVED_11_MASK -#define DDR_PHY_DTCR1_RESERVED_11_DEFVAL 0x00030237 -#define DDR_PHY_DTCR1_RESERVED_11_SHIFT 11 -#define DDR_PHY_DTCR1_RESERVED_11_MASK 0x00000800U +#define DDR_PHY_DTCR1_RESERVED_11_DEFVAL 0x00030237 +#define DDR_PHY_DTCR1_RESERVED_11_SHIFT 11 +#define DDR_PHY_DTCR1_RESERVED_11_MASK 0x00000800U -/*Read Leveling Gate Sampling Difference*/ +/* +* Read Leveling Gate Sampling Difference +*/ #undef DDR_PHY_DTCR1_RDLVLGDIFF_DEFVAL #undef DDR_PHY_DTCR1_RDLVLGDIFF_SHIFT #undef DDR_PHY_DTCR1_RDLVLGDIFF_MASK -#define DDR_PHY_DTCR1_RDLVLGDIFF_DEFVAL 0x00030237 -#define DDR_PHY_DTCR1_RDLVLGDIFF_SHIFT 8 -#define DDR_PHY_DTCR1_RDLVLGDIFF_MASK 0x00000700U +#define DDR_PHY_DTCR1_RDLVLGDIFF_DEFVAL 0x00030237 +#define DDR_PHY_DTCR1_RDLVLGDIFF_SHIFT 8 +#define DDR_PHY_DTCR1_RDLVLGDIFF_MASK 0x00000700U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTCR1_RESERVED_7_DEFVAL #undef DDR_PHY_DTCR1_RESERVED_7_SHIFT #undef DDR_PHY_DTCR1_RESERVED_7_MASK -#define DDR_PHY_DTCR1_RESERVED_7_DEFVAL 0x00030237 -#define DDR_PHY_DTCR1_RESERVED_7_SHIFT 7 -#define DDR_PHY_DTCR1_RESERVED_7_MASK 0x00000080U +#define DDR_PHY_DTCR1_RESERVED_7_DEFVAL 0x00030237 +#define DDR_PHY_DTCR1_RESERVED_7_SHIFT 7 +#define DDR_PHY_DTCR1_RESERVED_7_MASK 0x00000080U -/*Read Leveling Gate Shift*/ +/* +* Read Leveling Gate Shift +*/ #undef DDR_PHY_DTCR1_RDLVLGS_DEFVAL #undef DDR_PHY_DTCR1_RDLVLGS_SHIFT #undef DDR_PHY_DTCR1_RDLVLGS_MASK -#define DDR_PHY_DTCR1_RDLVLGS_DEFVAL 0x00030237 -#define DDR_PHY_DTCR1_RDLVLGS_SHIFT 4 -#define DDR_PHY_DTCR1_RDLVLGS_MASK 0x00000070U +#define DDR_PHY_DTCR1_RDLVLGS_DEFVAL 0x00030237 +#define DDR_PHY_DTCR1_RDLVLGS_SHIFT 4 +#define DDR_PHY_DTCR1_RDLVLGS_MASK 0x00000070U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTCR1_RESERVED_3_DEFVAL #undef DDR_PHY_DTCR1_RESERVED_3_SHIFT #undef DDR_PHY_DTCR1_RESERVED_3_MASK -#define DDR_PHY_DTCR1_RESERVED_3_DEFVAL 0x00030237 -#define DDR_PHY_DTCR1_RESERVED_3_SHIFT 3 -#define DDR_PHY_DTCR1_RESERVED_3_MASK 0x00000008U +#define DDR_PHY_DTCR1_RESERVED_3_DEFVAL 0x00030237 +#define DDR_PHY_DTCR1_RESERVED_3_SHIFT 3 +#define DDR_PHY_DTCR1_RESERVED_3_MASK 0x00000008U -/*Read Preamble Training enable*/ +/* +* Read Preamble Training enable +*/ #undef DDR_PHY_DTCR1_RDPRMVL_TRN_DEFVAL #undef DDR_PHY_DTCR1_RDPRMVL_TRN_SHIFT #undef DDR_PHY_DTCR1_RDPRMVL_TRN_MASK -#define DDR_PHY_DTCR1_RDPRMVL_TRN_DEFVAL 0x00030237 -#define DDR_PHY_DTCR1_RDPRMVL_TRN_SHIFT 2 -#define DDR_PHY_DTCR1_RDPRMVL_TRN_MASK 0x00000004U +#define DDR_PHY_DTCR1_RDPRMVL_TRN_DEFVAL 0x00030237 +#define DDR_PHY_DTCR1_RDPRMVL_TRN_SHIFT 2 +#define DDR_PHY_DTCR1_RDPRMVL_TRN_MASK 0x00000004U -/*Read Leveling Enable*/ +/* +* Read Leveling Enable +*/ #undef DDR_PHY_DTCR1_RDLVLEN_DEFVAL #undef DDR_PHY_DTCR1_RDLVLEN_SHIFT #undef DDR_PHY_DTCR1_RDLVLEN_MASK -#define DDR_PHY_DTCR1_RDLVLEN_DEFVAL 0x00030237 -#define DDR_PHY_DTCR1_RDLVLEN_SHIFT 1 -#define DDR_PHY_DTCR1_RDLVLEN_MASK 0x00000002U +#define DDR_PHY_DTCR1_RDLVLEN_DEFVAL 0x00030237 +#define DDR_PHY_DTCR1_RDLVLEN_SHIFT 1 +#define DDR_PHY_DTCR1_RDLVLEN_MASK 0x00000002U -/*Basic Gate Training Enable*/ +/* +* Basic Gate Training Enable +*/ #undef DDR_PHY_DTCR1_BSTEN_DEFVAL #undef DDR_PHY_DTCR1_BSTEN_SHIFT #undef DDR_PHY_DTCR1_BSTEN_MASK -#define DDR_PHY_DTCR1_BSTEN_DEFVAL 0x00030237 -#define DDR_PHY_DTCR1_BSTEN_SHIFT 0 -#define DDR_PHY_DTCR1_BSTEN_MASK 0x00000001U +#define DDR_PHY_DTCR1_BSTEN_DEFVAL 0x00030237 +#define DDR_PHY_DTCR1_BSTEN_SHIFT 0 +#define DDR_PHY_DTCR1_BSTEN_MASK 0x00000001U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_CATR0_RESERVED_31_21_DEFVAL #undef DDR_PHY_CATR0_RESERVED_31_21_SHIFT #undef DDR_PHY_CATR0_RESERVED_31_21_MASK -#define DDR_PHY_CATR0_RESERVED_31_21_DEFVAL 0x00141054 -#define DDR_PHY_CATR0_RESERVED_31_21_SHIFT 21 -#define DDR_PHY_CATR0_RESERVED_31_21_MASK 0xFFE00000U +#define DDR_PHY_CATR0_RESERVED_31_21_DEFVAL 0x00141054 +#define DDR_PHY_CATR0_RESERVED_31_21_SHIFT 21 +#define DDR_PHY_CATR0_RESERVED_31_21_MASK 0xFFE00000U -/*Minimum time (in terms of number of dram clocks) between two consectuve CA calibration command*/ +/* +* Minimum time (in terms of number of dram clocks) between two consectuve + * CA calibration command +*/ #undef DDR_PHY_CATR0_CACD_DEFVAL #undef DDR_PHY_CATR0_CACD_SHIFT #undef DDR_PHY_CATR0_CACD_MASK -#define DDR_PHY_CATR0_CACD_DEFVAL 0x00141054 -#define DDR_PHY_CATR0_CACD_SHIFT 16 -#define DDR_PHY_CATR0_CACD_MASK 0x001F0000U +#define DDR_PHY_CATR0_CACD_DEFVAL 0x00141054 +#define DDR_PHY_CATR0_CACD_SHIFT 16 +#define DDR_PHY_CATR0_CACD_MASK 0x001F0000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_CATR0_RESERVED_15_13_DEFVAL #undef DDR_PHY_CATR0_RESERVED_15_13_SHIFT #undef DDR_PHY_CATR0_RESERVED_15_13_MASK -#define DDR_PHY_CATR0_RESERVED_15_13_DEFVAL 0x00141054 -#define DDR_PHY_CATR0_RESERVED_15_13_SHIFT 13 -#define DDR_PHY_CATR0_RESERVED_15_13_MASK 0x0000E000U +#define DDR_PHY_CATR0_RESERVED_15_13_DEFVAL 0x00141054 +#define DDR_PHY_CATR0_RESERVED_15_13_SHIFT 13 +#define DDR_PHY_CATR0_RESERVED_15_13_MASK 0x0000E000U -/*Minimum time (in terms of number of dram clocks) PUB should wait before sampling the CA response after Calibration command ha - been sent to the memory*/ +/* +* Minimum time (in terms of number of dram clocks) PUB should wait before + * sampling the CA response after Calibration command has been sent to the + * memory +*/ #undef DDR_PHY_CATR0_CAADR_DEFVAL #undef DDR_PHY_CATR0_CAADR_SHIFT #undef DDR_PHY_CATR0_CAADR_MASK -#define DDR_PHY_CATR0_CAADR_DEFVAL 0x00141054 -#define DDR_PHY_CATR0_CAADR_SHIFT 8 -#define DDR_PHY_CATR0_CAADR_MASK 0x00001F00U +#define DDR_PHY_CATR0_CAADR_DEFVAL 0x00141054 +#define DDR_PHY_CATR0_CAADR_SHIFT 8 +#define DDR_PHY_CATR0_CAADR_MASK 0x00001F00U -/*CA_1 Response Byte Lane 1*/ +/* +* CA_1 Response Byte Lane 1 +*/ #undef DDR_PHY_CATR0_CA1BYTE1_DEFVAL #undef DDR_PHY_CATR0_CA1BYTE1_SHIFT #undef DDR_PHY_CATR0_CA1BYTE1_MASK -#define DDR_PHY_CATR0_CA1BYTE1_DEFVAL 0x00141054 -#define DDR_PHY_CATR0_CA1BYTE1_SHIFT 4 -#define DDR_PHY_CATR0_CA1BYTE1_MASK 0x000000F0U +#define DDR_PHY_CATR0_CA1BYTE1_DEFVAL 0x00141054 +#define DDR_PHY_CATR0_CA1BYTE1_SHIFT 4 +#define DDR_PHY_CATR0_CA1BYTE1_MASK 0x000000F0U -/*CA_1 Response Byte Lane 0*/ +/* +* CA_1 Response Byte Lane 0 +*/ #undef DDR_PHY_CATR0_CA1BYTE0_DEFVAL #undef DDR_PHY_CATR0_CA1BYTE0_SHIFT #undef DDR_PHY_CATR0_CA1BYTE0_MASK -#define DDR_PHY_CATR0_CA1BYTE0_DEFVAL 0x00141054 -#define DDR_PHY_CATR0_CA1BYTE0_SHIFT 0 -#define DDR_PHY_CATR0_CA1BYTE0_MASK 0x0000000FU +#define DDR_PHY_CATR0_CA1BYTE0_DEFVAL 0x00141054 +#define DDR_PHY_CATR0_CA1BYTE0_SHIFT 0 +#define DDR_PHY_CATR0_CA1BYTE0_MASK 0x0000000FU -/*LFSR seed for pseudo-random BIST patterns*/ +/* +* Number of delay taps by which the DQS gate LCDL will be updated when DQS + * drift is detected +*/ +#undef DDR_PHY_DQSDR0_DFTDLY_DEFVAL +#undef DDR_PHY_DQSDR0_DFTDLY_SHIFT +#undef DDR_PHY_DQSDR0_DFTDLY_MASK +#define DDR_PHY_DQSDR0_DFTDLY_DEFVAL 0x00088000 +#define DDR_PHY_DQSDR0_DFTDLY_SHIFT 28 +#define DDR_PHY_DQSDR0_DFTDLY_MASK 0xF0000000U + +/* +* Drift Impedance Update +*/ +#undef DDR_PHY_DQSDR0_DFTZQUP_DEFVAL +#undef DDR_PHY_DQSDR0_DFTZQUP_SHIFT +#undef DDR_PHY_DQSDR0_DFTZQUP_MASK +#define DDR_PHY_DQSDR0_DFTZQUP_DEFVAL 0x00088000 +#define DDR_PHY_DQSDR0_DFTZQUP_SHIFT 27 +#define DDR_PHY_DQSDR0_DFTZQUP_MASK 0x08000000U + +/* +* Drift DDL Update +*/ +#undef DDR_PHY_DQSDR0_DFTDDLUP_DEFVAL +#undef DDR_PHY_DQSDR0_DFTDDLUP_SHIFT +#undef DDR_PHY_DQSDR0_DFTDDLUP_MASK +#define DDR_PHY_DQSDR0_DFTDDLUP_DEFVAL 0x00088000 +#define DDR_PHY_DQSDR0_DFTDDLUP_SHIFT 26 +#define DDR_PHY_DQSDR0_DFTDDLUP_MASK 0x04000000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DQSDR0_RESERVED_25_22_DEFVAL +#undef DDR_PHY_DQSDR0_RESERVED_25_22_SHIFT +#undef DDR_PHY_DQSDR0_RESERVED_25_22_MASK +#define DDR_PHY_DQSDR0_RESERVED_25_22_DEFVAL 0x00088000 +#define DDR_PHY_DQSDR0_RESERVED_25_22_SHIFT 22 +#define DDR_PHY_DQSDR0_RESERVED_25_22_MASK 0x03C00000U + +/* +* Drift Read Spacing +*/ +#undef DDR_PHY_DQSDR0_DFTRDSPC_DEFVAL +#undef DDR_PHY_DQSDR0_DFTRDSPC_SHIFT +#undef DDR_PHY_DQSDR0_DFTRDSPC_MASK +#define DDR_PHY_DQSDR0_DFTRDSPC_DEFVAL 0x00088000 +#define DDR_PHY_DQSDR0_DFTRDSPC_SHIFT 20 +#define DDR_PHY_DQSDR0_DFTRDSPC_MASK 0x00300000U + +/* +* Drift Back-to-Back Reads +*/ +#undef DDR_PHY_DQSDR0_DFTB2BRD_DEFVAL +#undef DDR_PHY_DQSDR0_DFTB2BRD_SHIFT +#undef DDR_PHY_DQSDR0_DFTB2BRD_MASK +#define DDR_PHY_DQSDR0_DFTB2BRD_DEFVAL 0x00088000 +#define DDR_PHY_DQSDR0_DFTB2BRD_SHIFT 16 +#define DDR_PHY_DQSDR0_DFTB2BRD_MASK 0x000F0000U + +/* +* Drift Idle Reads +*/ +#undef DDR_PHY_DQSDR0_DFTIDLRD_DEFVAL +#undef DDR_PHY_DQSDR0_DFTIDLRD_SHIFT +#undef DDR_PHY_DQSDR0_DFTIDLRD_MASK +#define DDR_PHY_DQSDR0_DFTIDLRD_DEFVAL 0x00088000 +#define DDR_PHY_DQSDR0_DFTIDLRD_SHIFT 12 +#define DDR_PHY_DQSDR0_DFTIDLRD_MASK 0x0000F000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DQSDR0_RESERVED_11_8_DEFVAL +#undef DDR_PHY_DQSDR0_RESERVED_11_8_SHIFT +#undef DDR_PHY_DQSDR0_RESERVED_11_8_MASK +#define DDR_PHY_DQSDR0_RESERVED_11_8_DEFVAL 0x00088000 +#define DDR_PHY_DQSDR0_RESERVED_11_8_SHIFT 8 +#define DDR_PHY_DQSDR0_RESERVED_11_8_MASK 0x00000F00U + +/* +* Gate Pulse Enable +*/ +#undef DDR_PHY_DQSDR0_DFTGPULSE_DEFVAL +#undef DDR_PHY_DQSDR0_DFTGPULSE_SHIFT +#undef DDR_PHY_DQSDR0_DFTGPULSE_MASK +#define DDR_PHY_DQSDR0_DFTGPULSE_DEFVAL 0x00088000 +#define DDR_PHY_DQSDR0_DFTGPULSE_SHIFT 4 +#define DDR_PHY_DQSDR0_DFTGPULSE_MASK 0x000000F0U + +/* +* DQS Drift Update Mode +*/ +#undef DDR_PHY_DQSDR0_DFTUPMODE_DEFVAL +#undef DDR_PHY_DQSDR0_DFTUPMODE_SHIFT +#undef DDR_PHY_DQSDR0_DFTUPMODE_MASK +#define DDR_PHY_DQSDR0_DFTUPMODE_DEFVAL 0x00088000 +#define DDR_PHY_DQSDR0_DFTUPMODE_SHIFT 2 +#define DDR_PHY_DQSDR0_DFTUPMODE_MASK 0x0000000CU + +/* +* DQS Drift Detection Mode +*/ +#undef DDR_PHY_DQSDR0_DFTDTMODE_DEFVAL +#undef DDR_PHY_DQSDR0_DFTDTMODE_SHIFT +#undef DDR_PHY_DQSDR0_DFTDTMODE_MASK +#define DDR_PHY_DQSDR0_DFTDTMODE_DEFVAL 0x00088000 +#define DDR_PHY_DQSDR0_DFTDTMODE_SHIFT 1 +#define DDR_PHY_DQSDR0_DFTDTMODE_MASK 0x00000002U + +/* +* DQS Drift Detection Enable +*/ +#undef DDR_PHY_DQSDR0_DFTDTEN_DEFVAL +#undef DDR_PHY_DQSDR0_DFTDTEN_SHIFT +#undef DDR_PHY_DQSDR0_DFTDTEN_MASK +#define DDR_PHY_DQSDR0_DFTDTEN_DEFVAL 0x00088000 +#define DDR_PHY_DQSDR0_DFTDTEN_SHIFT 0 +#define DDR_PHY_DQSDR0_DFTDTEN_MASK 0x00000001U + +/* +* LFSR seed for pseudo-random BIST patterns +*/ #undef DDR_PHY_BISTLSR_SEED_DEFVAL #undef DDR_PHY_BISTLSR_SEED_SHIFT #undef DDR_PHY_BISTLSR_SEED_MASK -#define DDR_PHY_BISTLSR_SEED_DEFVAL -#define DDR_PHY_BISTLSR_SEED_SHIFT 0 -#define DDR_PHY_BISTLSR_SEED_MASK 0xFFFFFFFFU +#define DDR_PHY_BISTLSR_SEED_DEFVAL +#define DDR_PHY_BISTLSR_SEED_SHIFT 0 +#define DDR_PHY_BISTLSR_SEED_MASK 0xFFFFFFFFU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_RIOCR5_RESERVED_31_16_DEFVAL #undef DDR_PHY_RIOCR5_RESERVED_31_16_SHIFT #undef DDR_PHY_RIOCR5_RESERVED_31_16_MASK -#define DDR_PHY_RIOCR5_RESERVED_31_16_DEFVAL 0x00000005 -#define DDR_PHY_RIOCR5_RESERVED_31_16_SHIFT 16 -#define DDR_PHY_RIOCR5_RESERVED_31_16_MASK 0xFFFF0000U +#define DDR_PHY_RIOCR5_RESERVED_31_16_DEFVAL 0x00000005 +#define DDR_PHY_RIOCR5_RESERVED_31_16_SHIFT 16 +#define DDR_PHY_RIOCR5_RESERVED_31_16_MASK 0xFFFF0000U -/*Reserved. Return zeros on reads.*/ +/* +* Reserved. Return zeros on reads. +*/ #undef DDR_PHY_RIOCR5_ODTOEMODE_RSVD_DEFVAL #undef DDR_PHY_RIOCR5_ODTOEMODE_RSVD_SHIFT #undef DDR_PHY_RIOCR5_ODTOEMODE_RSVD_MASK -#define DDR_PHY_RIOCR5_ODTOEMODE_RSVD_DEFVAL 0x00000005 -#define DDR_PHY_RIOCR5_ODTOEMODE_RSVD_SHIFT 4 -#define DDR_PHY_RIOCR5_ODTOEMODE_RSVD_MASK 0x0000FFF0U +#define DDR_PHY_RIOCR5_ODTOEMODE_RSVD_DEFVAL 0x00000005 +#define DDR_PHY_RIOCR5_ODTOEMODE_RSVD_SHIFT 4 +#define DDR_PHY_RIOCR5_ODTOEMODE_RSVD_MASK 0x0000FFF0U -/*SDRAM On-die Termination Output Enable (OE) Mode Selection.*/ +/* +* SDRAM On-die Termination Output Enable (OE) Mode Selection. +*/ #undef DDR_PHY_RIOCR5_ODTOEMODE_DEFVAL #undef DDR_PHY_RIOCR5_ODTOEMODE_SHIFT #undef DDR_PHY_RIOCR5_ODTOEMODE_MASK -#define DDR_PHY_RIOCR5_ODTOEMODE_DEFVAL 0x00000005 -#define DDR_PHY_RIOCR5_ODTOEMODE_SHIFT 0 -#define DDR_PHY_RIOCR5_ODTOEMODE_MASK 0x0000000FU +#define DDR_PHY_RIOCR5_ODTOEMODE_DEFVAL 0x00000005 +#define DDR_PHY_RIOCR5_ODTOEMODE_SHIFT 0 +#define DDR_PHY_RIOCR5_ODTOEMODE_MASK 0x0000000FU -/*Address/Command Slew Rate (D3F I/O Only)*/ +/* +* Address/Command Slew Rate (D3F I/O Only) +*/ #undef DDR_PHY_ACIOCR0_ACSR_DEFVAL #undef DDR_PHY_ACIOCR0_ACSR_SHIFT #undef DDR_PHY_ACIOCR0_ACSR_MASK -#define DDR_PHY_ACIOCR0_ACSR_DEFVAL 0x30000000 -#define DDR_PHY_ACIOCR0_ACSR_SHIFT 30 -#define DDR_PHY_ACIOCR0_ACSR_MASK 0xC0000000U +#define DDR_PHY_ACIOCR0_ACSR_DEFVAL 0x30000000 +#define DDR_PHY_ACIOCR0_ACSR_SHIFT 30 +#define DDR_PHY_ACIOCR0_ACSR_MASK 0xC0000000U -/*SDRAM Reset I/O Mode*/ +/* +* SDRAM Reset I/O Mode +*/ #undef DDR_PHY_ACIOCR0_RSTIOM_DEFVAL #undef DDR_PHY_ACIOCR0_RSTIOM_SHIFT #undef DDR_PHY_ACIOCR0_RSTIOM_MASK -#define DDR_PHY_ACIOCR0_RSTIOM_DEFVAL 0x30000000 -#define DDR_PHY_ACIOCR0_RSTIOM_SHIFT 29 -#define DDR_PHY_ACIOCR0_RSTIOM_MASK 0x20000000U +#define DDR_PHY_ACIOCR0_RSTIOM_DEFVAL 0x30000000 +#define DDR_PHY_ACIOCR0_RSTIOM_SHIFT 29 +#define DDR_PHY_ACIOCR0_RSTIOM_MASK 0x20000000U -/*SDRAM Reset Power Down Receiver*/ +/* +* SDRAM Reset Power Down Receiver +*/ #undef DDR_PHY_ACIOCR0_RSTPDR_DEFVAL #undef DDR_PHY_ACIOCR0_RSTPDR_SHIFT #undef DDR_PHY_ACIOCR0_RSTPDR_MASK -#define DDR_PHY_ACIOCR0_RSTPDR_DEFVAL 0x30000000 -#define DDR_PHY_ACIOCR0_RSTPDR_SHIFT 28 -#define DDR_PHY_ACIOCR0_RSTPDR_MASK 0x10000000U +#define DDR_PHY_ACIOCR0_RSTPDR_DEFVAL 0x30000000 +#define DDR_PHY_ACIOCR0_RSTPDR_SHIFT 28 +#define DDR_PHY_ACIOCR0_RSTPDR_MASK 0x10000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACIOCR0_RESERVED_27_DEFVAL #undef DDR_PHY_ACIOCR0_RESERVED_27_SHIFT #undef DDR_PHY_ACIOCR0_RESERVED_27_MASK -#define DDR_PHY_ACIOCR0_RESERVED_27_DEFVAL 0x30000000 -#define DDR_PHY_ACIOCR0_RESERVED_27_SHIFT 27 -#define DDR_PHY_ACIOCR0_RESERVED_27_MASK 0x08000000U +#define DDR_PHY_ACIOCR0_RESERVED_27_DEFVAL 0x30000000 +#define DDR_PHY_ACIOCR0_RESERVED_27_SHIFT 27 +#define DDR_PHY_ACIOCR0_RESERVED_27_MASK 0x08000000U -/*SDRAM Reset On-Die Termination*/ +/* +* SDRAM Reset On-Die Termination +*/ #undef DDR_PHY_ACIOCR0_RSTODT_DEFVAL #undef DDR_PHY_ACIOCR0_RSTODT_SHIFT #undef DDR_PHY_ACIOCR0_RSTODT_MASK -#define DDR_PHY_ACIOCR0_RSTODT_DEFVAL 0x30000000 -#define DDR_PHY_ACIOCR0_RSTODT_SHIFT 26 -#define DDR_PHY_ACIOCR0_RSTODT_MASK 0x04000000U +#define DDR_PHY_ACIOCR0_RSTODT_DEFVAL 0x30000000 +#define DDR_PHY_ACIOCR0_RSTODT_SHIFT 26 +#define DDR_PHY_ACIOCR0_RSTODT_MASK 0x04000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACIOCR0_RESERVED_25_10_DEFVAL #undef DDR_PHY_ACIOCR0_RESERVED_25_10_SHIFT #undef DDR_PHY_ACIOCR0_RESERVED_25_10_MASK -#define DDR_PHY_ACIOCR0_RESERVED_25_10_DEFVAL 0x30000000 -#define DDR_PHY_ACIOCR0_RESERVED_25_10_SHIFT 10 -#define DDR_PHY_ACIOCR0_RESERVED_25_10_MASK 0x03FFFC00U +#define DDR_PHY_ACIOCR0_RESERVED_25_10_DEFVAL 0x30000000 +#define DDR_PHY_ACIOCR0_RESERVED_25_10_SHIFT 10 +#define DDR_PHY_ACIOCR0_RESERVED_25_10_MASK 0x03FFFC00U -/*CK Duty Cycle Correction*/ +/* +* CK Duty Cycle Correction +*/ #undef DDR_PHY_ACIOCR0_CKDCC_DEFVAL #undef DDR_PHY_ACIOCR0_CKDCC_SHIFT #undef DDR_PHY_ACIOCR0_CKDCC_MASK -#define DDR_PHY_ACIOCR0_CKDCC_DEFVAL 0x30000000 -#define DDR_PHY_ACIOCR0_CKDCC_SHIFT 6 -#define DDR_PHY_ACIOCR0_CKDCC_MASK 0x000003C0U +#define DDR_PHY_ACIOCR0_CKDCC_DEFVAL 0x30000000 +#define DDR_PHY_ACIOCR0_CKDCC_SHIFT 6 +#define DDR_PHY_ACIOCR0_CKDCC_MASK 0x000003C0U -/*AC Power Down Receiver Mode*/ +/* +* AC Power Down Receiver Mode +*/ #undef DDR_PHY_ACIOCR0_ACPDRMODE_DEFVAL #undef DDR_PHY_ACIOCR0_ACPDRMODE_SHIFT #undef DDR_PHY_ACIOCR0_ACPDRMODE_MASK -#define DDR_PHY_ACIOCR0_ACPDRMODE_DEFVAL 0x30000000 -#define DDR_PHY_ACIOCR0_ACPDRMODE_SHIFT 4 -#define DDR_PHY_ACIOCR0_ACPDRMODE_MASK 0x00000030U +#define DDR_PHY_ACIOCR0_ACPDRMODE_DEFVAL 0x30000000 +#define DDR_PHY_ACIOCR0_ACPDRMODE_SHIFT 4 +#define DDR_PHY_ACIOCR0_ACPDRMODE_MASK 0x00000030U -/*AC On-die Termination Mode*/ +/* +* AC On-die Termination Mode +*/ #undef DDR_PHY_ACIOCR0_ACODTMODE_DEFVAL #undef DDR_PHY_ACIOCR0_ACODTMODE_SHIFT #undef DDR_PHY_ACIOCR0_ACODTMODE_MASK -#define DDR_PHY_ACIOCR0_ACODTMODE_DEFVAL 0x30000000 -#define DDR_PHY_ACIOCR0_ACODTMODE_SHIFT 2 -#define DDR_PHY_ACIOCR0_ACODTMODE_MASK 0x0000000CU +#define DDR_PHY_ACIOCR0_ACODTMODE_DEFVAL 0x30000000 +#define DDR_PHY_ACIOCR0_ACODTMODE_SHIFT 2 +#define DDR_PHY_ACIOCR0_ACODTMODE_MASK 0x0000000CU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACIOCR0_RESERVED_1_DEFVAL #undef DDR_PHY_ACIOCR0_RESERVED_1_SHIFT #undef DDR_PHY_ACIOCR0_RESERVED_1_MASK -#define DDR_PHY_ACIOCR0_RESERVED_1_DEFVAL 0x30000000 -#define DDR_PHY_ACIOCR0_RESERVED_1_SHIFT 1 -#define DDR_PHY_ACIOCR0_RESERVED_1_MASK 0x00000002U +#define DDR_PHY_ACIOCR0_RESERVED_1_DEFVAL 0x30000000 +#define DDR_PHY_ACIOCR0_RESERVED_1_SHIFT 1 +#define DDR_PHY_ACIOCR0_RESERVED_1_MASK 0x00000002U -/*Control delayed or non-delayed clock to CS_N/ODT?CKE AC slices.*/ +/* +* Control delayed or non-delayed clock to CS_N/ODT?CKE AC slices. +*/ #undef DDR_PHY_ACIOCR0_ACRANKCLKSEL_DEFVAL #undef DDR_PHY_ACIOCR0_ACRANKCLKSEL_SHIFT #undef DDR_PHY_ACIOCR0_ACRANKCLKSEL_MASK -#define DDR_PHY_ACIOCR0_ACRANKCLKSEL_DEFVAL 0x30000000 -#define DDR_PHY_ACIOCR0_ACRANKCLKSEL_SHIFT 0 -#define DDR_PHY_ACIOCR0_ACRANKCLKSEL_MASK 0x00000001U +#define DDR_PHY_ACIOCR0_ACRANKCLKSEL_DEFVAL 0x30000000 +#define DDR_PHY_ACIOCR0_ACRANKCLKSEL_SHIFT 0 +#define DDR_PHY_ACIOCR0_ACRANKCLKSEL_MASK 0x00000001U -/*Clock gating for glue logic inside CLKGEN and glue logic inside CONTROL slice*/ +/* +* Clock gating for glue logic inside CLKGEN and glue logic inside CONTROL + * slice +*/ #undef DDR_PHY_ACIOCR2_CLKGENCLKGATE_DEFVAL #undef DDR_PHY_ACIOCR2_CLKGENCLKGATE_SHIFT #undef DDR_PHY_ACIOCR2_CLKGENCLKGATE_MASK -#define DDR_PHY_ACIOCR2_CLKGENCLKGATE_DEFVAL 0x00000000 -#define DDR_PHY_ACIOCR2_CLKGENCLKGATE_SHIFT 31 -#define DDR_PHY_ACIOCR2_CLKGENCLKGATE_MASK 0x80000000U +#define DDR_PHY_ACIOCR2_CLKGENCLKGATE_DEFVAL 0x00000000 +#define DDR_PHY_ACIOCR2_CLKGENCLKGATE_SHIFT 31 +#define DDR_PHY_ACIOCR2_CLKGENCLKGATE_MASK 0x80000000U -/*Clock gating for Output Enable D slices [0]*/ +/* +* Clock gating for Output Enable D slices [0] +*/ #undef DDR_PHY_ACIOCR2_ACOECLKGATE0_DEFVAL #undef DDR_PHY_ACIOCR2_ACOECLKGATE0_SHIFT #undef DDR_PHY_ACIOCR2_ACOECLKGATE0_MASK -#define DDR_PHY_ACIOCR2_ACOECLKGATE0_DEFVAL 0x00000000 -#define DDR_PHY_ACIOCR2_ACOECLKGATE0_SHIFT 30 -#define DDR_PHY_ACIOCR2_ACOECLKGATE0_MASK 0x40000000U +#define DDR_PHY_ACIOCR2_ACOECLKGATE0_DEFVAL 0x00000000 +#define DDR_PHY_ACIOCR2_ACOECLKGATE0_SHIFT 30 +#define DDR_PHY_ACIOCR2_ACOECLKGATE0_MASK 0x40000000U -/*Clock gating for Power Down Receiver D slices [0]*/ +/* +* Clock gating for Power Down Receiver D slices [0] +*/ #undef DDR_PHY_ACIOCR2_ACPDRCLKGATE0_DEFVAL #undef DDR_PHY_ACIOCR2_ACPDRCLKGATE0_SHIFT #undef DDR_PHY_ACIOCR2_ACPDRCLKGATE0_MASK -#define DDR_PHY_ACIOCR2_ACPDRCLKGATE0_DEFVAL 0x00000000 -#define DDR_PHY_ACIOCR2_ACPDRCLKGATE0_SHIFT 29 -#define DDR_PHY_ACIOCR2_ACPDRCLKGATE0_MASK 0x20000000U +#define DDR_PHY_ACIOCR2_ACPDRCLKGATE0_DEFVAL 0x00000000 +#define DDR_PHY_ACIOCR2_ACPDRCLKGATE0_SHIFT 29 +#define DDR_PHY_ACIOCR2_ACPDRCLKGATE0_MASK 0x20000000U -/*Clock gating for Termination Enable D slices [0]*/ +/* +* Clock gating for Termination Enable D slices [0] +*/ #undef DDR_PHY_ACIOCR2_ACTECLKGATE0_DEFVAL #undef DDR_PHY_ACIOCR2_ACTECLKGATE0_SHIFT #undef DDR_PHY_ACIOCR2_ACTECLKGATE0_MASK -#define DDR_PHY_ACIOCR2_ACTECLKGATE0_DEFVAL 0x00000000 -#define DDR_PHY_ACIOCR2_ACTECLKGATE0_SHIFT 28 -#define DDR_PHY_ACIOCR2_ACTECLKGATE0_MASK 0x10000000U +#define DDR_PHY_ACIOCR2_ACTECLKGATE0_DEFVAL 0x00000000 +#define DDR_PHY_ACIOCR2_ACTECLKGATE0_SHIFT 28 +#define DDR_PHY_ACIOCR2_ACTECLKGATE0_MASK 0x10000000U -/*Clock gating for CK# D slices [1:0]*/ +/* +* Clock gating for CK# D slices [1:0] +*/ #undef DDR_PHY_ACIOCR2_CKNCLKGATE0_DEFVAL #undef DDR_PHY_ACIOCR2_CKNCLKGATE0_SHIFT #undef DDR_PHY_ACIOCR2_CKNCLKGATE0_MASK -#define DDR_PHY_ACIOCR2_CKNCLKGATE0_DEFVAL 0x00000000 -#define DDR_PHY_ACIOCR2_CKNCLKGATE0_SHIFT 26 -#define DDR_PHY_ACIOCR2_CKNCLKGATE0_MASK 0x0C000000U +#define DDR_PHY_ACIOCR2_CKNCLKGATE0_DEFVAL 0x00000000 +#define DDR_PHY_ACIOCR2_CKNCLKGATE0_SHIFT 26 +#define DDR_PHY_ACIOCR2_CKNCLKGATE0_MASK 0x0C000000U -/*Clock gating for CK D slices [1:0]*/ +/* +* Clock gating for CK D slices [1:0] +*/ #undef DDR_PHY_ACIOCR2_CKCLKGATE0_DEFVAL #undef DDR_PHY_ACIOCR2_CKCLKGATE0_SHIFT #undef DDR_PHY_ACIOCR2_CKCLKGATE0_MASK -#define DDR_PHY_ACIOCR2_CKCLKGATE0_DEFVAL 0x00000000 -#define DDR_PHY_ACIOCR2_CKCLKGATE0_SHIFT 24 -#define DDR_PHY_ACIOCR2_CKCLKGATE0_MASK 0x03000000U +#define DDR_PHY_ACIOCR2_CKCLKGATE0_DEFVAL 0x00000000 +#define DDR_PHY_ACIOCR2_CKCLKGATE0_SHIFT 24 +#define DDR_PHY_ACIOCR2_CKCLKGATE0_MASK 0x03000000U -/*Clock gating for AC D slices [23:0]*/ +/* +* Clock gating for AC D slices [23:0] +*/ #undef DDR_PHY_ACIOCR2_ACCLKGATE0_DEFVAL #undef DDR_PHY_ACIOCR2_ACCLKGATE0_SHIFT #undef DDR_PHY_ACIOCR2_ACCLKGATE0_MASK -#define DDR_PHY_ACIOCR2_ACCLKGATE0_DEFVAL 0x00000000 -#define DDR_PHY_ACIOCR2_ACCLKGATE0_SHIFT 0 -#define DDR_PHY_ACIOCR2_ACCLKGATE0_MASK 0x00FFFFFFU +#define DDR_PHY_ACIOCR2_ACCLKGATE0_DEFVAL 0x00000000 +#define DDR_PHY_ACIOCR2_ACCLKGATE0_SHIFT 0 +#define DDR_PHY_ACIOCR2_ACCLKGATE0_MASK 0x00FFFFFFU -/*SDRAM Parity Output Enable (OE) Mode Selection*/ +/* +* SDRAM Parity Output Enable (OE) Mode Selection +*/ #undef DDR_PHY_ACIOCR3_PAROEMODE_DEFVAL #undef DDR_PHY_ACIOCR3_PAROEMODE_SHIFT #undef DDR_PHY_ACIOCR3_PAROEMODE_MASK -#define DDR_PHY_ACIOCR3_PAROEMODE_DEFVAL 0x00000005 -#define DDR_PHY_ACIOCR3_PAROEMODE_SHIFT 30 -#define DDR_PHY_ACIOCR3_PAROEMODE_MASK 0xC0000000U +#define DDR_PHY_ACIOCR3_PAROEMODE_DEFVAL 0x00000005 +#define DDR_PHY_ACIOCR3_PAROEMODE_SHIFT 30 +#define DDR_PHY_ACIOCR3_PAROEMODE_MASK 0xC0000000U -/*SDRAM Bank Group Output Enable (OE) Mode Selection*/ +/* +* SDRAM Bank Group Output Enable (OE) Mode Selection +*/ #undef DDR_PHY_ACIOCR3_BGOEMODE_DEFVAL #undef DDR_PHY_ACIOCR3_BGOEMODE_SHIFT #undef DDR_PHY_ACIOCR3_BGOEMODE_MASK -#define DDR_PHY_ACIOCR3_BGOEMODE_DEFVAL 0x00000005 -#define DDR_PHY_ACIOCR3_BGOEMODE_SHIFT 26 -#define DDR_PHY_ACIOCR3_BGOEMODE_MASK 0x3C000000U +#define DDR_PHY_ACIOCR3_BGOEMODE_DEFVAL 0x00000005 +#define DDR_PHY_ACIOCR3_BGOEMODE_SHIFT 26 +#define DDR_PHY_ACIOCR3_BGOEMODE_MASK 0x3C000000U -/*SDRAM Bank Address Output Enable (OE) Mode Selection*/ +/* +* SDRAM Bank Address Output Enable (OE) Mode Selection +*/ #undef DDR_PHY_ACIOCR3_BAOEMODE_DEFVAL #undef DDR_PHY_ACIOCR3_BAOEMODE_SHIFT #undef DDR_PHY_ACIOCR3_BAOEMODE_MASK -#define DDR_PHY_ACIOCR3_BAOEMODE_DEFVAL 0x00000005 -#define DDR_PHY_ACIOCR3_BAOEMODE_SHIFT 22 -#define DDR_PHY_ACIOCR3_BAOEMODE_MASK 0x03C00000U +#define DDR_PHY_ACIOCR3_BAOEMODE_DEFVAL 0x00000005 +#define DDR_PHY_ACIOCR3_BAOEMODE_SHIFT 22 +#define DDR_PHY_ACIOCR3_BAOEMODE_MASK 0x03C00000U -/*SDRAM A[17] Output Enable (OE) Mode Selection*/ +/* +* SDRAM A[17] Output Enable (OE) Mode Selection +*/ #undef DDR_PHY_ACIOCR3_A17OEMODE_DEFVAL #undef DDR_PHY_ACIOCR3_A17OEMODE_SHIFT #undef DDR_PHY_ACIOCR3_A17OEMODE_MASK -#define DDR_PHY_ACIOCR3_A17OEMODE_DEFVAL 0x00000005 -#define DDR_PHY_ACIOCR3_A17OEMODE_SHIFT 20 -#define DDR_PHY_ACIOCR3_A17OEMODE_MASK 0x00300000U +#define DDR_PHY_ACIOCR3_A17OEMODE_DEFVAL 0x00000005 +#define DDR_PHY_ACIOCR3_A17OEMODE_SHIFT 20 +#define DDR_PHY_ACIOCR3_A17OEMODE_MASK 0x00300000U -/*SDRAM A[16] / RAS_n Output Enable (OE) Mode Selection*/ +/* +* SDRAM A[16] / RAS_n Output Enable (OE) Mode Selection +*/ #undef DDR_PHY_ACIOCR3_A16OEMODE_DEFVAL #undef DDR_PHY_ACIOCR3_A16OEMODE_SHIFT #undef DDR_PHY_ACIOCR3_A16OEMODE_MASK -#define DDR_PHY_ACIOCR3_A16OEMODE_DEFVAL 0x00000005 -#define DDR_PHY_ACIOCR3_A16OEMODE_SHIFT 18 -#define DDR_PHY_ACIOCR3_A16OEMODE_MASK 0x000C0000U +#define DDR_PHY_ACIOCR3_A16OEMODE_DEFVAL 0x00000005 +#define DDR_PHY_ACIOCR3_A16OEMODE_SHIFT 18 +#define DDR_PHY_ACIOCR3_A16OEMODE_MASK 0x000C0000U -/*SDRAM ACT_n Output Enable (OE) Mode Selection (DDR4 only)*/ +/* +* SDRAM ACT_n Output Enable (OE) Mode Selection (DDR4 only) +*/ #undef DDR_PHY_ACIOCR3_ACTOEMODE_DEFVAL #undef DDR_PHY_ACIOCR3_ACTOEMODE_SHIFT #undef DDR_PHY_ACIOCR3_ACTOEMODE_MASK -#define DDR_PHY_ACIOCR3_ACTOEMODE_DEFVAL 0x00000005 -#define DDR_PHY_ACIOCR3_ACTOEMODE_SHIFT 16 -#define DDR_PHY_ACIOCR3_ACTOEMODE_MASK 0x00030000U +#define DDR_PHY_ACIOCR3_ACTOEMODE_DEFVAL 0x00000005 +#define DDR_PHY_ACIOCR3_ACTOEMODE_SHIFT 16 +#define DDR_PHY_ACIOCR3_ACTOEMODE_MASK 0x00030000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACIOCR3_RESERVED_15_8_DEFVAL #undef DDR_PHY_ACIOCR3_RESERVED_15_8_SHIFT #undef DDR_PHY_ACIOCR3_RESERVED_15_8_MASK -#define DDR_PHY_ACIOCR3_RESERVED_15_8_DEFVAL 0x00000005 -#define DDR_PHY_ACIOCR3_RESERVED_15_8_SHIFT 8 -#define DDR_PHY_ACIOCR3_RESERVED_15_8_MASK 0x0000FF00U +#define DDR_PHY_ACIOCR3_RESERVED_15_8_DEFVAL 0x00000005 +#define DDR_PHY_ACIOCR3_RESERVED_15_8_SHIFT 8 +#define DDR_PHY_ACIOCR3_RESERVED_15_8_MASK 0x0000FF00U -/*Reserved. Return zeros on reads.*/ +/* +* Reserved. Return zeros on reads. +*/ #undef DDR_PHY_ACIOCR3_CKOEMODE_RSVD_DEFVAL #undef DDR_PHY_ACIOCR3_CKOEMODE_RSVD_SHIFT #undef DDR_PHY_ACIOCR3_CKOEMODE_RSVD_MASK -#define DDR_PHY_ACIOCR3_CKOEMODE_RSVD_DEFVAL 0x00000005 -#define DDR_PHY_ACIOCR3_CKOEMODE_RSVD_SHIFT 4 -#define DDR_PHY_ACIOCR3_CKOEMODE_RSVD_MASK 0x000000F0U +#define DDR_PHY_ACIOCR3_CKOEMODE_RSVD_DEFVAL 0x00000005 +#define DDR_PHY_ACIOCR3_CKOEMODE_RSVD_SHIFT 4 +#define DDR_PHY_ACIOCR3_CKOEMODE_RSVD_MASK 0x000000F0U -/*SDRAM CK Output Enable (OE) Mode Selection.*/ +/* +* SDRAM CK Output Enable (OE) Mode Selection. +*/ #undef DDR_PHY_ACIOCR3_CKOEMODE_DEFVAL #undef DDR_PHY_ACIOCR3_CKOEMODE_SHIFT #undef DDR_PHY_ACIOCR3_CKOEMODE_MASK -#define DDR_PHY_ACIOCR3_CKOEMODE_DEFVAL 0x00000005 -#define DDR_PHY_ACIOCR3_CKOEMODE_SHIFT 0 -#define DDR_PHY_ACIOCR3_CKOEMODE_MASK 0x0000000FU +#define DDR_PHY_ACIOCR3_CKOEMODE_DEFVAL 0x00000005 +#define DDR_PHY_ACIOCR3_CKOEMODE_SHIFT 0 +#define DDR_PHY_ACIOCR3_CKOEMODE_MASK 0x0000000FU -/*Clock gating for AC LB slices and loopback read valid slices*/ +/* +* Clock gating for AC LB slices and loopback read valid slices +*/ #undef DDR_PHY_ACIOCR4_LBCLKGATE_DEFVAL #undef DDR_PHY_ACIOCR4_LBCLKGATE_SHIFT #undef DDR_PHY_ACIOCR4_LBCLKGATE_MASK -#define DDR_PHY_ACIOCR4_LBCLKGATE_DEFVAL 0x00000000 -#define DDR_PHY_ACIOCR4_LBCLKGATE_SHIFT 31 -#define DDR_PHY_ACIOCR4_LBCLKGATE_MASK 0x80000000U +#define DDR_PHY_ACIOCR4_LBCLKGATE_DEFVAL 0x00000000 +#define DDR_PHY_ACIOCR4_LBCLKGATE_SHIFT 31 +#define DDR_PHY_ACIOCR4_LBCLKGATE_MASK 0x80000000U -/*Clock gating for Output Enable D slices [1]*/ +/* +* Clock gating for Output Enable D slices [1] +*/ #undef DDR_PHY_ACIOCR4_ACOECLKGATE1_DEFVAL #undef DDR_PHY_ACIOCR4_ACOECLKGATE1_SHIFT #undef DDR_PHY_ACIOCR4_ACOECLKGATE1_MASK -#define DDR_PHY_ACIOCR4_ACOECLKGATE1_DEFVAL 0x00000000 -#define DDR_PHY_ACIOCR4_ACOECLKGATE1_SHIFT 30 -#define DDR_PHY_ACIOCR4_ACOECLKGATE1_MASK 0x40000000U +#define DDR_PHY_ACIOCR4_ACOECLKGATE1_DEFVAL 0x00000000 +#define DDR_PHY_ACIOCR4_ACOECLKGATE1_SHIFT 30 +#define DDR_PHY_ACIOCR4_ACOECLKGATE1_MASK 0x40000000U -/*Clock gating for Power Down Receiver D slices [1]*/ +/* +* Clock gating for Power Down Receiver D slices [1] +*/ #undef DDR_PHY_ACIOCR4_ACPDRCLKGATE1_DEFVAL #undef DDR_PHY_ACIOCR4_ACPDRCLKGATE1_SHIFT #undef DDR_PHY_ACIOCR4_ACPDRCLKGATE1_MASK -#define DDR_PHY_ACIOCR4_ACPDRCLKGATE1_DEFVAL 0x00000000 -#define DDR_PHY_ACIOCR4_ACPDRCLKGATE1_SHIFT 29 -#define DDR_PHY_ACIOCR4_ACPDRCLKGATE1_MASK 0x20000000U +#define DDR_PHY_ACIOCR4_ACPDRCLKGATE1_DEFVAL 0x00000000 +#define DDR_PHY_ACIOCR4_ACPDRCLKGATE1_SHIFT 29 +#define DDR_PHY_ACIOCR4_ACPDRCLKGATE1_MASK 0x20000000U -/*Clock gating for Termination Enable D slices [1]*/ +/* +* Clock gating for Termination Enable D slices [1] +*/ #undef DDR_PHY_ACIOCR4_ACTECLKGATE1_DEFVAL #undef DDR_PHY_ACIOCR4_ACTECLKGATE1_SHIFT #undef DDR_PHY_ACIOCR4_ACTECLKGATE1_MASK -#define DDR_PHY_ACIOCR4_ACTECLKGATE1_DEFVAL 0x00000000 -#define DDR_PHY_ACIOCR4_ACTECLKGATE1_SHIFT 28 -#define DDR_PHY_ACIOCR4_ACTECLKGATE1_MASK 0x10000000U +#define DDR_PHY_ACIOCR4_ACTECLKGATE1_DEFVAL 0x00000000 +#define DDR_PHY_ACIOCR4_ACTECLKGATE1_SHIFT 28 +#define DDR_PHY_ACIOCR4_ACTECLKGATE1_MASK 0x10000000U -/*Clock gating for CK# D slices [3:2]*/ +/* +* Clock gating for CK# D slices [3:2] +*/ #undef DDR_PHY_ACIOCR4_CKNCLKGATE1_DEFVAL #undef DDR_PHY_ACIOCR4_CKNCLKGATE1_SHIFT #undef DDR_PHY_ACIOCR4_CKNCLKGATE1_MASK -#define DDR_PHY_ACIOCR4_CKNCLKGATE1_DEFVAL 0x00000000 -#define DDR_PHY_ACIOCR4_CKNCLKGATE1_SHIFT 26 -#define DDR_PHY_ACIOCR4_CKNCLKGATE1_MASK 0x0C000000U +#define DDR_PHY_ACIOCR4_CKNCLKGATE1_DEFVAL 0x00000000 +#define DDR_PHY_ACIOCR4_CKNCLKGATE1_SHIFT 26 +#define DDR_PHY_ACIOCR4_CKNCLKGATE1_MASK 0x0C000000U -/*Clock gating for CK D slices [3:2]*/ +/* +* Clock gating for CK D slices [3:2] +*/ #undef DDR_PHY_ACIOCR4_CKCLKGATE1_DEFVAL #undef DDR_PHY_ACIOCR4_CKCLKGATE1_SHIFT #undef DDR_PHY_ACIOCR4_CKCLKGATE1_MASK -#define DDR_PHY_ACIOCR4_CKCLKGATE1_DEFVAL 0x00000000 -#define DDR_PHY_ACIOCR4_CKCLKGATE1_SHIFT 24 -#define DDR_PHY_ACIOCR4_CKCLKGATE1_MASK 0x03000000U +#define DDR_PHY_ACIOCR4_CKCLKGATE1_DEFVAL 0x00000000 +#define DDR_PHY_ACIOCR4_CKCLKGATE1_SHIFT 24 +#define DDR_PHY_ACIOCR4_CKCLKGATE1_MASK 0x03000000U -/*Clock gating for AC D slices [47:24]*/ +/* +* Clock gating for AC D slices [47:24] +*/ #undef DDR_PHY_ACIOCR4_ACCLKGATE1_DEFVAL #undef DDR_PHY_ACIOCR4_ACCLKGATE1_SHIFT #undef DDR_PHY_ACIOCR4_ACCLKGATE1_MASK -#define DDR_PHY_ACIOCR4_ACCLKGATE1_DEFVAL 0x00000000 -#define DDR_PHY_ACIOCR4_ACCLKGATE1_SHIFT 0 -#define DDR_PHY_ACIOCR4_ACCLKGATE1_MASK 0x00FFFFFFU +#define DDR_PHY_ACIOCR4_ACCLKGATE1_DEFVAL 0x00000000 +#define DDR_PHY_ACIOCR4_ACCLKGATE1_SHIFT 0 +#define DDR_PHY_ACIOCR4_ACCLKGATE1_MASK 0x00FFFFFFU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_IOVCR0_RESERVED_31_29_DEFVAL #undef DDR_PHY_IOVCR0_RESERVED_31_29_SHIFT #undef DDR_PHY_IOVCR0_RESERVED_31_29_MASK -#define DDR_PHY_IOVCR0_RESERVED_31_29_DEFVAL 0x0F000000 -#define DDR_PHY_IOVCR0_RESERVED_31_29_SHIFT 29 -#define DDR_PHY_IOVCR0_RESERVED_31_29_MASK 0xE0000000U +#define DDR_PHY_IOVCR0_RESERVED_31_29_DEFVAL 0x0F000000 +#define DDR_PHY_IOVCR0_RESERVED_31_29_SHIFT 29 +#define DDR_PHY_IOVCR0_RESERVED_31_29_MASK 0xE0000000U -/*Address/command lane VREF Pad Enable*/ +/* +* Address/command lane VREF Pad Enable +*/ #undef DDR_PHY_IOVCR0_ACREFPEN_DEFVAL #undef DDR_PHY_IOVCR0_ACREFPEN_SHIFT #undef DDR_PHY_IOVCR0_ACREFPEN_MASK -#define DDR_PHY_IOVCR0_ACREFPEN_DEFVAL 0x0F000000 -#define DDR_PHY_IOVCR0_ACREFPEN_SHIFT 28 -#define DDR_PHY_IOVCR0_ACREFPEN_MASK 0x10000000U +#define DDR_PHY_IOVCR0_ACREFPEN_DEFVAL 0x0F000000 +#define DDR_PHY_IOVCR0_ACREFPEN_SHIFT 28 +#define DDR_PHY_IOVCR0_ACREFPEN_MASK 0x10000000U -/*Address/command lane Internal VREF Enable*/ +/* +* Address/command lane Internal VREF Enable +*/ #undef DDR_PHY_IOVCR0_ACREFEEN_DEFVAL #undef DDR_PHY_IOVCR0_ACREFEEN_SHIFT #undef DDR_PHY_IOVCR0_ACREFEEN_MASK -#define DDR_PHY_IOVCR0_ACREFEEN_DEFVAL 0x0F000000 -#define DDR_PHY_IOVCR0_ACREFEEN_SHIFT 26 -#define DDR_PHY_IOVCR0_ACREFEEN_MASK 0x0C000000U +#define DDR_PHY_IOVCR0_ACREFEEN_DEFVAL 0x0F000000 +#define DDR_PHY_IOVCR0_ACREFEEN_SHIFT 26 +#define DDR_PHY_IOVCR0_ACREFEEN_MASK 0x0C000000U -/*Address/command lane Single-End VREF Enable*/ +/* +* Address/command lane Single-End VREF Enable +*/ #undef DDR_PHY_IOVCR0_ACREFSEN_DEFVAL #undef DDR_PHY_IOVCR0_ACREFSEN_SHIFT #undef DDR_PHY_IOVCR0_ACREFSEN_MASK -#define DDR_PHY_IOVCR0_ACREFSEN_DEFVAL 0x0F000000 -#define DDR_PHY_IOVCR0_ACREFSEN_SHIFT 25 -#define DDR_PHY_IOVCR0_ACREFSEN_MASK 0x02000000U +#define DDR_PHY_IOVCR0_ACREFSEN_DEFVAL 0x0F000000 +#define DDR_PHY_IOVCR0_ACREFSEN_SHIFT 25 +#define DDR_PHY_IOVCR0_ACREFSEN_MASK 0x02000000U -/*Address/command lane Internal VREF Enable*/ +/* +* Address/command lane Internal VREF Enable +*/ #undef DDR_PHY_IOVCR0_ACREFIEN_DEFVAL #undef DDR_PHY_IOVCR0_ACREFIEN_SHIFT #undef DDR_PHY_IOVCR0_ACREFIEN_MASK -#define DDR_PHY_IOVCR0_ACREFIEN_DEFVAL 0x0F000000 -#define DDR_PHY_IOVCR0_ACREFIEN_SHIFT 24 -#define DDR_PHY_IOVCR0_ACREFIEN_MASK 0x01000000U +#define DDR_PHY_IOVCR0_ACREFIEN_DEFVAL 0x0F000000 +#define DDR_PHY_IOVCR0_ACREFIEN_SHIFT 24 +#define DDR_PHY_IOVCR0_ACREFIEN_MASK 0x01000000U -/*External VREF generato REFSEL range select*/ +/* +* External VREF generato REFSEL range select +*/ #undef DDR_PHY_IOVCR0_ACREFESELRANGE_DEFVAL #undef DDR_PHY_IOVCR0_ACREFESELRANGE_SHIFT #undef DDR_PHY_IOVCR0_ACREFESELRANGE_MASK -#define DDR_PHY_IOVCR0_ACREFESELRANGE_DEFVAL 0x0F000000 -#define DDR_PHY_IOVCR0_ACREFESELRANGE_SHIFT 23 -#define DDR_PHY_IOVCR0_ACREFESELRANGE_MASK 0x00800000U +#define DDR_PHY_IOVCR0_ACREFESELRANGE_DEFVAL 0x0F000000 +#define DDR_PHY_IOVCR0_ACREFESELRANGE_SHIFT 23 +#define DDR_PHY_IOVCR0_ACREFESELRANGE_MASK 0x00800000U -/*Address/command lane External VREF Select*/ +/* +* Address/command lane External VREF Select +*/ #undef DDR_PHY_IOVCR0_ACREFESEL_DEFVAL #undef DDR_PHY_IOVCR0_ACREFESEL_SHIFT #undef DDR_PHY_IOVCR0_ACREFESEL_MASK -#define DDR_PHY_IOVCR0_ACREFESEL_DEFVAL 0x0F000000 -#define DDR_PHY_IOVCR0_ACREFESEL_SHIFT 16 -#define DDR_PHY_IOVCR0_ACREFESEL_MASK 0x007F0000U +#define DDR_PHY_IOVCR0_ACREFESEL_DEFVAL 0x0F000000 +#define DDR_PHY_IOVCR0_ACREFESEL_SHIFT 16 +#define DDR_PHY_IOVCR0_ACREFESEL_MASK 0x007F0000U -/*Single ended VREF generator REFSEL range select*/ +/* +* Single ended VREF generator REFSEL range select +*/ #undef DDR_PHY_IOVCR0_ACREFSSELRANGE_DEFVAL #undef DDR_PHY_IOVCR0_ACREFSSELRANGE_SHIFT #undef DDR_PHY_IOVCR0_ACREFSSELRANGE_MASK -#define DDR_PHY_IOVCR0_ACREFSSELRANGE_DEFVAL 0x0F000000 -#define DDR_PHY_IOVCR0_ACREFSSELRANGE_SHIFT 15 -#define DDR_PHY_IOVCR0_ACREFSSELRANGE_MASK 0x00008000U +#define DDR_PHY_IOVCR0_ACREFSSELRANGE_DEFVAL 0x0F000000 +#define DDR_PHY_IOVCR0_ACREFSSELRANGE_SHIFT 15 +#define DDR_PHY_IOVCR0_ACREFSSELRANGE_MASK 0x00008000U -/*Address/command lane Single-End VREF Select*/ +/* +* Address/command lane Single-End VREF Select +*/ #undef DDR_PHY_IOVCR0_ACREFSSEL_DEFVAL #undef DDR_PHY_IOVCR0_ACREFSSEL_SHIFT #undef DDR_PHY_IOVCR0_ACREFSSEL_MASK -#define DDR_PHY_IOVCR0_ACREFSSEL_DEFVAL 0x0F000000 -#define DDR_PHY_IOVCR0_ACREFSSEL_SHIFT 8 -#define DDR_PHY_IOVCR0_ACREFSSEL_MASK 0x00007F00U +#define DDR_PHY_IOVCR0_ACREFSSEL_DEFVAL 0x0F000000 +#define DDR_PHY_IOVCR0_ACREFSSEL_SHIFT 8 +#define DDR_PHY_IOVCR0_ACREFSSEL_MASK 0x00007F00U -/*Internal VREF generator REFSEL ragne select*/ +/* +* Internal VREF generator REFSEL ragne select +*/ #undef DDR_PHY_IOVCR0_ACVREFISELRANGE_DEFVAL #undef DDR_PHY_IOVCR0_ACVREFISELRANGE_SHIFT #undef DDR_PHY_IOVCR0_ACVREFISELRANGE_MASK -#define DDR_PHY_IOVCR0_ACVREFISELRANGE_DEFVAL 0x0F000000 -#define DDR_PHY_IOVCR0_ACVREFISELRANGE_SHIFT 7 -#define DDR_PHY_IOVCR0_ACVREFISELRANGE_MASK 0x00000080U +#define DDR_PHY_IOVCR0_ACVREFISELRANGE_DEFVAL 0x0F000000 +#define DDR_PHY_IOVCR0_ACVREFISELRANGE_SHIFT 7 +#define DDR_PHY_IOVCR0_ACVREFISELRANGE_MASK 0x00000080U -/*REFSEL Control for internal AC IOs*/ +/* +* REFSEL Control for internal AC IOs +*/ #undef DDR_PHY_IOVCR0_ACVREFISEL_DEFVAL #undef DDR_PHY_IOVCR0_ACVREFISEL_SHIFT #undef DDR_PHY_IOVCR0_ACVREFISEL_MASK -#define DDR_PHY_IOVCR0_ACVREFISEL_DEFVAL 0x0F000000 -#define DDR_PHY_IOVCR0_ACVREFISEL_SHIFT 0 -#define DDR_PHY_IOVCR0_ACVREFISEL_MASK 0x0000007FU +#define DDR_PHY_IOVCR0_ACVREFISEL_DEFVAL 0x0F000000 +#define DDR_PHY_IOVCR0_ACVREFISEL_SHIFT 0 +#define DDR_PHY_IOVCR0_ACVREFISEL_MASK 0x0000007FU -/*Number of ctl_clk required to meet (> 150ns) timing requirements during DRAM DQ VREF training*/ +/* +* Number of ctl_clk required to meet (> 150ns) timing requirements during + * DRAM DQ VREF training +*/ #undef DDR_PHY_VTCR0_TVREF_DEFVAL #undef DDR_PHY_VTCR0_TVREF_SHIFT #undef DDR_PHY_VTCR0_TVREF_MASK -#define DDR_PHY_VTCR0_TVREF_DEFVAL 0x70032019 -#define DDR_PHY_VTCR0_TVREF_SHIFT 29 -#define DDR_PHY_VTCR0_TVREF_MASK 0xE0000000U +#define DDR_PHY_VTCR0_TVREF_DEFVAL 0x70032019 +#define DDR_PHY_VTCR0_TVREF_SHIFT 29 +#define DDR_PHY_VTCR0_TVREF_MASK 0xE0000000U -/*DRM DQ VREF training Enable*/ +/* +* DRM DQ VREF training Enable +*/ #undef DDR_PHY_VTCR0_DVEN_DEFVAL #undef DDR_PHY_VTCR0_DVEN_SHIFT #undef DDR_PHY_VTCR0_DVEN_MASK -#define DDR_PHY_VTCR0_DVEN_DEFVAL 0x70032019 -#define DDR_PHY_VTCR0_DVEN_SHIFT 28 -#define DDR_PHY_VTCR0_DVEN_MASK 0x10000000U +#define DDR_PHY_VTCR0_DVEN_DEFVAL 0x70032019 +#define DDR_PHY_VTCR0_DVEN_SHIFT 28 +#define DDR_PHY_VTCR0_DVEN_MASK 0x10000000U -/*Per Device Addressability Enable*/ +/* +* Per Device Addressability Enable +*/ #undef DDR_PHY_VTCR0_PDAEN_DEFVAL #undef DDR_PHY_VTCR0_PDAEN_SHIFT #undef DDR_PHY_VTCR0_PDAEN_MASK -#define DDR_PHY_VTCR0_PDAEN_DEFVAL 0x70032019 -#define DDR_PHY_VTCR0_PDAEN_SHIFT 27 -#define DDR_PHY_VTCR0_PDAEN_MASK 0x08000000U +#define DDR_PHY_VTCR0_PDAEN_DEFVAL 0x70032019 +#define DDR_PHY_VTCR0_PDAEN_SHIFT 27 +#define DDR_PHY_VTCR0_PDAEN_MASK 0x08000000U -/*Reserved. Returns zeroes on reads.*/ +/* +* Reserved. Returns zeroes on reads. +*/ #undef DDR_PHY_VTCR0_RESERVED_26_DEFVAL #undef DDR_PHY_VTCR0_RESERVED_26_SHIFT #undef DDR_PHY_VTCR0_RESERVED_26_MASK -#define DDR_PHY_VTCR0_RESERVED_26_DEFVAL 0x70032019 -#define DDR_PHY_VTCR0_RESERVED_26_SHIFT 26 -#define DDR_PHY_VTCR0_RESERVED_26_MASK 0x04000000U +#define DDR_PHY_VTCR0_RESERVED_26_DEFVAL 0x70032019 +#define DDR_PHY_VTCR0_RESERVED_26_SHIFT 26 +#define DDR_PHY_VTCR0_RESERVED_26_MASK 0x04000000U -/*VREF Word Count*/ +/* +* VREF Word Count +*/ #undef DDR_PHY_VTCR0_VWCR_DEFVAL #undef DDR_PHY_VTCR0_VWCR_SHIFT #undef DDR_PHY_VTCR0_VWCR_MASK -#define DDR_PHY_VTCR0_VWCR_DEFVAL 0x70032019 -#define DDR_PHY_VTCR0_VWCR_SHIFT 22 -#define DDR_PHY_VTCR0_VWCR_MASK 0x03C00000U +#define DDR_PHY_VTCR0_VWCR_DEFVAL 0x70032019 +#define DDR_PHY_VTCR0_VWCR_SHIFT 22 +#define DDR_PHY_VTCR0_VWCR_MASK 0x03C00000U -/*DRAM DQ VREF step size used during DRAM VREF training*/ +/* +* DRAM DQ VREF step size used during DRAM VREF training +*/ #undef DDR_PHY_VTCR0_DVSS_DEFVAL #undef DDR_PHY_VTCR0_DVSS_SHIFT #undef DDR_PHY_VTCR0_DVSS_MASK -#define DDR_PHY_VTCR0_DVSS_DEFVAL 0x70032019 -#define DDR_PHY_VTCR0_DVSS_SHIFT 18 -#define DDR_PHY_VTCR0_DVSS_MASK 0x003C0000U +#define DDR_PHY_VTCR0_DVSS_DEFVAL 0x70032019 +#define DDR_PHY_VTCR0_DVSS_SHIFT 18 +#define DDR_PHY_VTCR0_DVSS_MASK 0x003C0000U -/*Maximum VREF limit value used during DRAM VREF training*/ +/* +* Maximum VREF limit value used during DRAM VREF training +*/ #undef DDR_PHY_VTCR0_DVMAX_DEFVAL #undef DDR_PHY_VTCR0_DVMAX_SHIFT #undef DDR_PHY_VTCR0_DVMAX_MASK -#define DDR_PHY_VTCR0_DVMAX_DEFVAL 0x70032019 -#define DDR_PHY_VTCR0_DVMAX_SHIFT 12 -#define DDR_PHY_VTCR0_DVMAX_MASK 0x0003F000U +#define DDR_PHY_VTCR0_DVMAX_DEFVAL 0x70032019 +#define DDR_PHY_VTCR0_DVMAX_SHIFT 12 +#define DDR_PHY_VTCR0_DVMAX_MASK 0x0003F000U -/*Minimum VREF limit value used during DRAM VREF training*/ +/* +* Minimum VREF limit value used during DRAM VREF training +*/ #undef DDR_PHY_VTCR0_DVMIN_DEFVAL #undef DDR_PHY_VTCR0_DVMIN_SHIFT #undef DDR_PHY_VTCR0_DVMIN_MASK -#define DDR_PHY_VTCR0_DVMIN_DEFVAL 0x70032019 -#define DDR_PHY_VTCR0_DVMIN_SHIFT 6 -#define DDR_PHY_VTCR0_DVMIN_MASK 0x00000FC0U +#define DDR_PHY_VTCR0_DVMIN_DEFVAL 0x70032019 +#define DDR_PHY_VTCR0_DVMIN_SHIFT 6 +#define DDR_PHY_VTCR0_DVMIN_MASK 0x00000FC0U -/*Initial DRAM DQ VREF value used during DRAM VREF training*/ +/* +* Initial DRAM DQ VREF value used during DRAM VREF training +*/ #undef DDR_PHY_VTCR0_DVINIT_DEFVAL #undef DDR_PHY_VTCR0_DVINIT_SHIFT #undef DDR_PHY_VTCR0_DVINIT_MASK -#define DDR_PHY_VTCR0_DVINIT_DEFVAL 0x70032019 -#define DDR_PHY_VTCR0_DVINIT_SHIFT 0 -#define DDR_PHY_VTCR0_DVINIT_MASK 0x0000003FU +#define DDR_PHY_VTCR0_DVINIT_DEFVAL 0x70032019 +#define DDR_PHY_VTCR0_DVINIT_SHIFT 0 +#define DDR_PHY_VTCR0_DVINIT_MASK 0x0000003FU -/*Host VREF step size used during VREF training. The register value of N indicates step size of (N+1)*/ +/* +* Host VREF step size used during VREF training. The register value of N i + * ndicates step size of (N+1) +*/ #undef DDR_PHY_VTCR1_HVSS_DEFVAL #undef DDR_PHY_VTCR1_HVSS_SHIFT #undef DDR_PHY_VTCR1_HVSS_MASK -#define DDR_PHY_VTCR1_HVSS_DEFVAL 0x07F00072 -#define DDR_PHY_VTCR1_HVSS_SHIFT 28 -#define DDR_PHY_VTCR1_HVSS_MASK 0xF0000000U +#define DDR_PHY_VTCR1_HVSS_DEFVAL 0x07F00072 +#define DDR_PHY_VTCR1_HVSS_SHIFT 28 +#define DDR_PHY_VTCR1_HVSS_MASK 0xF0000000U -/*Reserved. Returns zeroes on reads.*/ +/* +* Reserved. Returns zeroes on reads. +*/ #undef DDR_PHY_VTCR1_RESERVED_27_DEFVAL #undef DDR_PHY_VTCR1_RESERVED_27_SHIFT #undef DDR_PHY_VTCR1_RESERVED_27_MASK -#define DDR_PHY_VTCR1_RESERVED_27_DEFVAL 0x07F00072 -#define DDR_PHY_VTCR1_RESERVED_27_SHIFT 27 -#define DDR_PHY_VTCR1_RESERVED_27_MASK 0x08000000U +#define DDR_PHY_VTCR1_RESERVED_27_DEFVAL 0x07F00072 +#define DDR_PHY_VTCR1_RESERVED_27_SHIFT 27 +#define DDR_PHY_VTCR1_RESERVED_27_MASK 0x08000000U -/*Maximum VREF limit value used during DRAM VREF training.*/ +/* +* Maximum VREF limit value used during DRAM VREF training. +*/ #undef DDR_PHY_VTCR1_HVMAX_DEFVAL #undef DDR_PHY_VTCR1_HVMAX_SHIFT #undef DDR_PHY_VTCR1_HVMAX_MASK -#define DDR_PHY_VTCR1_HVMAX_DEFVAL 0x07F00072 -#define DDR_PHY_VTCR1_HVMAX_SHIFT 20 -#define DDR_PHY_VTCR1_HVMAX_MASK 0x07F00000U +#define DDR_PHY_VTCR1_HVMAX_DEFVAL 0x07F00072 +#define DDR_PHY_VTCR1_HVMAX_SHIFT 20 +#define DDR_PHY_VTCR1_HVMAX_MASK 0x07F00000U -/*Reserved. Returns zeroes on reads.*/ +/* +* Reserved. Returns zeroes on reads. +*/ #undef DDR_PHY_VTCR1_RESERVED_19_DEFVAL #undef DDR_PHY_VTCR1_RESERVED_19_SHIFT #undef DDR_PHY_VTCR1_RESERVED_19_MASK -#define DDR_PHY_VTCR1_RESERVED_19_DEFVAL 0x07F00072 -#define DDR_PHY_VTCR1_RESERVED_19_SHIFT 19 -#define DDR_PHY_VTCR1_RESERVED_19_MASK 0x00080000U +#define DDR_PHY_VTCR1_RESERVED_19_DEFVAL 0x07F00072 +#define DDR_PHY_VTCR1_RESERVED_19_SHIFT 19 +#define DDR_PHY_VTCR1_RESERVED_19_MASK 0x00080000U -/*Minimum VREF limit value used during DRAM VREF training.*/ +/* +* Minimum VREF limit value used during DRAM VREF training. +*/ #undef DDR_PHY_VTCR1_HVMIN_DEFVAL #undef DDR_PHY_VTCR1_HVMIN_SHIFT #undef DDR_PHY_VTCR1_HVMIN_MASK -#define DDR_PHY_VTCR1_HVMIN_DEFVAL 0x07F00072 -#define DDR_PHY_VTCR1_HVMIN_SHIFT 12 -#define DDR_PHY_VTCR1_HVMIN_MASK 0x0007F000U +#define DDR_PHY_VTCR1_HVMIN_DEFVAL 0x07F00072 +#define DDR_PHY_VTCR1_HVMIN_SHIFT 12 +#define DDR_PHY_VTCR1_HVMIN_MASK 0x0007F000U -/*Reserved. Returns zeroes on reads.*/ +/* +* Reserved. Returns zeroes on reads. +*/ #undef DDR_PHY_VTCR1_RESERVED_11_DEFVAL #undef DDR_PHY_VTCR1_RESERVED_11_SHIFT #undef DDR_PHY_VTCR1_RESERVED_11_MASK -#define DDR_PHY_VTCR1_RESERVED_11_DEFVAL 0x07F00072 -#define DDR_PHY_VTCR1_RESERVED_11_SHIFT 11 -#define DDR_PHY_VTCR1_RESERVED_11_MASK 0x00000800U +#define DDR_PHY_VTCR1_RESERVED_11_DEFVAL 0x07F00072 +#define DDR_PHY_VTCR1_RESERVED_11_SHIFT 11 +#define DDR_PHY_VTCR1_RESERVED_11_MASK 0x00000800U -/*Static Host Vref Rank Value*/ +/* +* Static Host Vref Rank Value +*/ #undef DDR_PHY_VTCR1_SHRNK_DEFVAL #undef DDR_PHY_VTCR1_SHRNK_SHIFT #undef DDR_PHY_VTCR1_SHRNK_MASK -#define DDR_PHY_VTCR1_SHRNK_DEFVAL 0x07F00072 -#define DDR_PHY_VTCR1_SHRNK_SHIFT 9 -#define DDR_PHY_VTCR1_SHRNK_MASK 0x00000600U +#define DDR_PHY_VTCR1_SHRNK_DEFVAL 0x07F00072 +#define DDR_PHY_VTCR1_SHRNK_SHIFT 9 +#define DDR_PHY_VTCR1_SHRNK_MASK 0x00000600U -/*Static Host Vref Rank Enable*/ +/* +* Static Host Vref Rank Enable +*/ #undef DDR_PHY_VTCR1_SHREN_DEFVAL #undef DDR_PHY_VTCR1_SHREN_SHIFT #undef DDR_PHY_VTCR1_SHREN_MASK -#define DDR_PHY_VTCR1_SHREN_DEFVAL 0x07F00072 -#define DDR_PHY_VTCR1_SHREN_SHIFT 8 -#define DDR_PHY_VTCR1_SHREN_MASK 0x00000100U +#define DDR_PHY_VTCR1_SHREN_DEFVAL 0x07F00072 +#define DDR_PHY_VTCR1_SHREN_SHIFT 8 +#define DDR_PHY_VTCR1_SHREN_MASK 0x00000100U -/*Number of ctl_clk required to meet (> 200ns) VREF Settling timing requirements during Host IO VREF training*/ +/* +* Number of ctl_clk required to meet (> 200ns) VREF Settling timing requir + * ements during Host IO VREF training +*/ #undef DDR_PHY_VTCR1_TVREFIO_DEFVAL #undef DDR_PHY_VTCR1_TVREFIO_SHIFT #undef DDR_PHY_VTCR1_TVREFIO_MASK -#define DDR_PHY_VTCR1_TVREFIO_DEFVAL 0x07F00072 -#define DDR_PHY_VTCR1_TVREFIO_SHIFT 5 -#define DDR_PHY_VTCR1_TVREFIO_MASK 0x000000E0U +#define DDR_PHY_VTCR1_TVREFIO_DEFVAL 0x07F00072 +#define DDR_PHY_VTCR1_TVREFIO_SHIFT 5 +#define DDR_PHY_VTCR1_TVREFIO_MASK 0x000000E0U -/*Eye LCDL Offset value for VREF training*/ +/* +* Eye LCDL Offset value for VREF training +*/ #undef DDR_PHY_VTCR1_EOFF_DEFVAL #undef DDR_PHY_VTCR1_EOFF_SHIFT #undef DDR_PHY_VTCR1_EOFF_MASK -#define DDR_PHY_VTCR1_EOFF_DEFVAL 0x07F00072 -#define DDR_PHY_VTCR1_EOFF_SHIFT 3 -#define DDR_PHY_VTCR1_EOFF_MASK 0x00000018U +#define DDR_PHY_VTCR1_EOFF_DEFVAL 0x07F00072 +#define DDR_PHY_VTCR1_EOFF_SHIFT 3 +#define DDR_PHY_VTCR1_EOFF_MASK 0x00000018U -/*Number of LCDL Eye points for which VREF training is repeated*/ +/* +* Number of LCDL Eye points for which VREF training is repeated +*/ #undef DDR_PHY_VTCR1_ENUM_DEFVAL #undef DDR_PHY_VTCR1_ENUM_SHIFT #undef DDR_PHY_VTCR1_ENUM_MASK -#define DDR_PHY_VTCR1_ENUM_DEFVAL 0x07F00072 -#define DDR_PHY_VTCR1_ENUM_SHIFT 2 -#define DDR_PHY_VTCR1_ENUM_MASK 0x00000004U +#define DDR_PHY_VTCR1_ENUM_DEFVAL 0x07F00072 +#define DDR_PHY_VTCR1_ENUM_SHIFT 2 +#define DDR_PHY_VTCR1_ENUM_MASK 0x00000004U -/*HOST (IO) internal VREF training Enable*/ +/* +* HOST (IO) internal VREF training Enable +*/ #undef DDR_PHY_VTCR1_HVEN_DEFVAL #undef DDR_PHY_VTCR1_HVEN_SHIFT #undef DDR_PHY_VTCR1_HVEN_MASK -#define DDR_PHY_VTCR1_HVEN_DEFVAL 0x07F00072 -#define DDR_PHY_VTCR1_HVEN_SHIFT 1 -#define DDR_PHY_VTCR1_HVEN_MASK 0x00000002U +#define DDR_PHY_VTCR1_HVEN_DEFVAL 0x07F00072 +#define DDR_PHY_VTCR1_HVEN_SHIFT 1 +#define DDR_PHY_VTCR1_HVEN_MASK 0x00000002U -/*Host IO Type Control*/ +/* +* Host IO Type Control +*/ #undef DDR_PHY_VTCR1_HVIO_DEFVAL #undef DDR_PHY_VTCR1_HVIO_SHIFT #undef DDR_PHY_VTCR1_HVIO_MASK -#define DDR_PHY_VTCR1_HVIO_DEFVAL 0x07F00072 -#define DDR_PHY_VTCR1_HVIO_SHIFT 0 -#define DDR_PHY_VTCR1_HVIO_MASK 0x00000001U +#define DDR_PHY_VTCR1_HVIO_DEFVAL 0x07F00072 +#define DDR_PHY_VTCR1_HVIO_SHIFT 0 +#define DDR_PHY_VTCR1_HVIO_MASK 0x00000001U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR1_RESERVED_31_30_DEFVAL #undef DDR_PHY_ACBDLR1_RESERVED_31_30_SHIFT #undef DDR_PHY_ACBDLR1_RESERVED_31_30_MASK -#define DDR_PHY_ACBDLR1_RESERVED_31_30_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR1_RESERVED_31_30_SHIFT 30 -#define DDR_PHY_ACBDLR1_RESERVED_31_30_MASK 0xC0000000U +#define DDR_PHY_ACBDLR1_RESERVED_31_30_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR1_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_ACBDLR1_RESERVED_31_30_MASK 0xC0000000U -/*Delay select for the BDL on Parity.*/ +/* +* Delay select for the BDL on Parity. +*/ #undef DDR_PHY_ACBDLR1_PARBD_DEFVAL #undef DDR_PHY_ACBDLR1_PARBD_SHIFT #undef DDR_PHY_ACBDLR1_PARBD_MASK -#define DDR_PHY_ACBDLR1_PARBD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR1_PARBD_SHIFT 24 -#define DDR_PHY_ACBDLR1_PARBD_MASK 0x3F000000U +#define DDR_PHY_ACBDLR1_PARBD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR1_PARBD_SHIFT 24 +#define DDR_PHY_ACBDLR1_PARBD_MASK 0x3F000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR1_RESERVED_23_22_DEFVAL #undef DDR_PHY_ACBDLR1_RESERVED_23_22_SHIFT #undef DDR_PHY_ACBDLR1_RESERVED_23_22_MASK -#define DDR_PHY_ACBDLR1_RESERVED_23_22_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR1_RESERVED_23_22_SHIFT 22 -#define DDR_PHY_ACBDLR1_RESERVED_23_22_MASK 0x00C00000U +#define DDR_PHY_ACBDLR1_RESERVED_23_22_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR1_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_ACBDLR1_RESERVED_23_22_MASK 0x00C00000U -/*Delay select for the BDL on Address A[16]. In DDR3 mode this pin is connected to WE.*/ +/* +* Delay select for the BDL on Address A[16]. In DDR3 mode this pin is conn + * ected to WE. +*/ #undef DDR_PHY_ACBDLR1_A16BD_DEFVAL #undef DDR_PHY_ACBDLR1_A16BD_SHIFT #undef DDR_PHY_ACBDLR1_A16BD_MASK -#define DDR_PHY_ACBDLR1_A16BD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR1_A16BD_SHIFT 16 -#define DDR_PHY_ACBDLR1_A16BD_MASK 0x003F0000U +#define DDR_PHY_ACBDLR1_A16BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR1_A16BD_SHIFT 16 +#define DDR_PHY_ACBDLR1_A16BD_MASK 0x003F0000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR1_RESERVED_15_14_DEFVAL #undef DDR_PHY_ACBDLR1_RESERVED_15_14_SHIFT #undef DDR_PHY_ACBDLR1_RESERVED_15_14_MASK -#define DDR_PHY_ACBDLR1_RESERVED_15_14_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR1_RESERVED_15_14_SHIFT 14 -#define DDR_PHY_ACBDLR1_RESERVED_15_14_MASK 0x0000C000U +#define DDR_PHY_ACBDLR1_RESERVED_15_14_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR1_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_ACBDLR1_RESERVED_15_14_MASK 0x0000C000U -/*Delay select for the BDL on Address A[17]. When not in DDR4 modemode this pin is connected to CAS.*/ +/* +* Delay select for the BDL on Address A[17]. When not in DDR4 modemode thi + * s pin is connected to CAS. +*/ #undef DDR_PHY_ACBDLR1_A17BD_DEFVAL #undef DDR_PHY_ACBDLR1_A17BD_SHIFT #undef DDR_PHY_ACBDLR1_A17BD_MASK -#define DDR_PHY_ACBDLR1_A17BD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR1_A17BD_SHIFT 8 -#define DDR_PHY_ACBDLR1_A17BD_MASK 0x00003F00U +#define DDR_PHY_ACBDLR1_A17BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR1_A17BD_SHIFT 8 +#define DDR_PHY_ACBDLR1_A17BD_MASK 0x00003F00U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR1_RESERVED_7_6_DEFVAL #undef DDR_PHY_ACBDLR1_RESERVED_7_6_SHIFT #undef DDR_PHY_ACBDLR1_RESERVED_7_6_MASK -#define DDR_PHY_ACBDLR1_RESERVED_7_6_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR1_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_ACBDLR1_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_ACBDLR1_RESERVED_7_6_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR1_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_ACBDLR1_RESERVED_7_6_MASK 0x000000C0U -/*Delay select for the BDL on ACTN.*/ +/* +* Delay select for the BDL on ACTN. +*/ #undef DDR_PHY_ACBDLR1_ACTBD_DEFVAL #undef DDR_PHY_ACBDLR1_ACTBD_SHIFT #undef DDR_PHY_ACBDLR1_ACTBD_MASK -#define DDR_PHY_ACBDLR1_ACTBD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR1_ACTBD_SHIFT 0 -#define DDR_PHY_ACBDLR1_ACTBD_MASK 0x0000003FU +#define DDR_PHY_ACBDLR1_ACTBD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR1_ACTBD_SHIFT 0 +#define DDR_PHY_ACBDLR1_ACTBD_MASK 0x0000003FU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR2_RESERVED_31_30_DEFVAL #undef DDR_PHY_ACBDLR2_RESERVED_31_30_SHIFT #undef DDR_PHY_ACBDLR2_RESERVED_31_30_MASK -#define DDR_PHY_ACBDLR2_RESERVED_31_30_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR2_RESERVED_31_30_SHIFT 30 -#define DDR_PHY_ACBDLR2_RESERVED_31_30_MASK 0xC0000000U +#define DDR_PHY_ACBDLR2_RESERVED_31_30_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR2_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_ACBDLR2_RESERVED_31_30_MASK 0xC0000000U -/*Delay select for the BDL on BG[1].*/ +/* +* Delay select for the BDL on BG[1]. +*/ #undef DDR_PHY_ACBDLR2_BG1BD_DEFVAL #undef DDR_PHY_ACBDLR2_BG1BD_SHIFT #undef DDR_PHY_ACBDLR2_BG1BD_MASK -#define DDR_PHY_ACBDLR2_BG1BD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR2_BG1BD_SHIFT 24 -#define DDR_PHY_ACBDLR2_BG1BD_MASK 0x3F000000U +#define DDR_PHY_ACBDLR2_BG1BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR2_BG1BD_SHIFT 24 +#define DDR_PHY_ACBDLR2_BG1BD_MASK 0x3F000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR2_RESERVED_23_22_DEFVAL #undef DDR_PHY_ACBDLR2_RESERVED_23_22_SHIFT #undef DDR_PHY_ACBDLR2_RESERVED_23_22_MASK -#define DDR_PHY_ACBDLR2_RESERVED_23_22_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR2_RESERVED_23_22_SHIFT 22 -#define DDR_PHY_ACBDLR2_RESERVED_23_22_MASK 0x00C00000U +#define DDR_PHY_ACBDLR2_RESERVED_23_22_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR2_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_ACBDLR2_RESERVED_23_22_MASK 0x00C00000U -/*Delay select for the BDL on BG[0].*/ +/* +* Delay select for the BDL on BG[0]. +*/ #undef DDR_PHY_ACBDLR2_BG0BD_DEFVAL #undef DDR_PHY_ACBDLR2_BG0BD_SHIFT #undef DDR_PHY_ACBDLR2_BG0BD_MASK -#define DDR_PHY_ACBDLR2_BG0BD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR2_BG0BD_SHIFT 16 -#define DDR_PHY_ACBDLR2_BG0BD_MASK 0x003F0000U +#define DDR_PHY_ACBDLR2_BG0BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR2_BG0BD_SHIFT 16 +#define DDR_PHY_ACBDLR2_BG0BD_MASK 0x003F0000U -/*Reser.ved Return zeroes on reads.*/ +/* +* Reser.ved Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR2_RESERVED_15_14_DEFVAL #undef DDR_PHY_ACBDLR2_RESERVED_15_14_SHIFT #undef DDR_PHY_ACBDLR2_RESERVED_15_14_MASK -#define DDR_PHY_ACBDLR2_RESERVED_15_14_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR2_RESERVED_15_14_SHIFT 14 -#define DDR_PHY_ACBDLR2_RESERVED_15_14_MASK 0x0000C000U +#define DDR_PHY_ACBDLR2_RESERVED_15_14_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR2_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_ACBDLR2_RESERVED_15_14_MASK 0x0000C000U -/*Delay select for the BDL on BA[1].*/ +/* +* Delay select for the BDL on BA[1]. +*/ #undef DDR_PHY_ACBDLR2_BA1BD_DEFVAL #undef DDR_PHY_ACBDLR2_BA1BD_SHIFT #undef DDR_PHY_ACBDLR2_BA1BD_MASK -#define DDR_PHY_ACBDLR2_BA1BD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR2_BA1BD_SHIFT 8 -#define DDR_PHY_ACBDLR2_BA1BD_MASK 0x00003F00U +#define DDR_PHY_ACBDLR2_BA1BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR2_BA1BD_SHIFT 8 +#define DDR_PHY_ACBDLR2_BA1BD_MASK 0x00003F00U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR2_RESERVED_7_6_DEFVAL #undef DDR_PHY_ACBDLR2_RESERVED_7_6_SHIFT #undef DDR_PHY_ACBDLR2_RESERVED_7_6_MASK -#define DDR_PHY_ACBDLR2_RESERVED_7_6_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR2_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_ACBDLR2_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_ACBDLR2_RESERVED_7_6_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR2_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_ACBDLR2_RESERVED_7_6_MASK 0x000000C0U -/*Delay select for the BDL on BA[0].*/ +/* +* Delay select for the BDL on BA[0]. +*/ #undef DDR_PHY_ACBDLR2_BA0BD_DEFVAL #undef DDR_PHY_ACBDLR2_BA0BD_SHIFT #undef DDR_PHY_ACBDLR2_BA0BD_MASK -#define DDR_PHY_ACBDLR2_BA0BD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR2_BA0BD_SHIFT 0 -#define DDR_PHY_ACBDLR2_BA0BD_MASK 0x0000003FU +#define DDR_PHY_ACBDLR2_BA0BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR2_BA0BD_SHIFT 0 +#define DDR_PHY_ACBDLR2_BA0BD_MASK 0x0000003FU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR6_RESERVED_31_30_DEFVAL #undef DDR_PHY_ACBDLR6_RESERVED_31_30_SHIFT #undef DDR_PHY_ACBDLR6_RESERVED_31_30_MASK -#define DDR_PHY_ACBDLR6_RESERVED_31_30_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR6_RESERVED_31_30_SHIFT 30 -#define DDR_PHY_ACBDLR6_RESERVED_31_30_MASK 0xC0000000U +#define DDR_PHY_ACBDLR6_RESERVED_31_30_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR6_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_ACBDLR6_RESERVED_31_30_MASK 0xC0000000U -/*Delay select for the BDL on Address A[3].*/ +/* +* Delay select for the BDL on Address A[3]. +*/ #undef DDR_PHY_ACBDLR6_A03BD_DEFVAL #undef DDR_PHY_ACBDLR6_A03BD_SHIFT #undef DDR_PHY_ACBDLR6_A03BD_MASK -#define DDR_PHY_ACBDLR6_A03BD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR6_A03BD_SHIFT 24 -#define DDR_PHY_ACBDLR6_A03BD_MASK 0x3F000000U +#define DDR_PHY_ACBDLR6_A03BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR6_A03BD_SHIFT 24 +#define DDR_PHY_ACBDLR6_A03BD_MASK 0x3F000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR6_RESERVED_23_22_DEFVAL #undef DDR_PHY_ACBDLR6_RESERVED_23_22_SHIFT #undef DDR_PHY_ACBDLR6_RESERVED_23_22_MASK -#define DDR_PHY_ACBDLR6_RESERVED_23_22_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR6_RESERVED_23_22_SHIFT 22 -#define DDR_PHY_ACBDLR6_RESERVED_23_22_MASK 0x00C00000U +#define DDR_PHY_ACBDLR6_RESERVED_23_22_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR6_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_ACBDLR6_RESERVED_23_22_MASK 0x00C00000U -/*Delay select for the BDL on Address A[2].*/ +/* +* Delay select for the BDL on Address A[2]. +*/ #undef DDR_PHY_ACBDLR6_A02BD_DEFVAL #undef DDR_PHY_ACBDLR6_A02BD_SHIFT #undef DDR_PHY_ACBDLR6_A02BD_MASK -#define DDR_PHY_ACBDLR6_A02BD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR6_A02BD_SHIFT 16 -#define DDR_PHY_ACBDLR6_A02BD_MASK 0x003F0000U +#define DDR_PHY_ACBDLR6_A02BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR6_A02BD_SHIFT 16 +#define DDR_PHY_ACBDLR6_A02BD_MASK 0x003F0000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR6_RESERVED_15_14_DEFVAL #undef DDR_PHY_ACBDLR6_RESERVED_15_14_SHIFT #undef DDR_PHY_ACBDLR6_RESERVED_15_14_MASK -#define DDR_PHY_ACBDLR6_RESERVED_15_14_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR6_RESERVED_15_14_SHIFT 14 -#define DDR_PHY_ACBDLR6_RESERVED_15_14_MASK 0x0000C000U +#define DDR_PHY_ACBDLR6_RESERVED_15_14_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR6_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_ACBDLR6_RESERVED_15_14_MASK 0x0000C000U -/*Delay select for the BDL on Address A[1].*/ +/* +* Delay select for the BDL on Address A[1]. +*/ #undef DDR_PHY_ACBDLR6_A01BD_DEFVAL #undef DDR_PHY_ACBDLR6_A01BD_SHIFT #undef DDR_PHY_ACBDLR6_A01BD_MASK -#define DDR_PHY_ACBDLR6_A01BD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR6_A01BD_SHIFT 8 -#define DDR_PHY_ACBDLR6_A01BD_MASK 0x00003F00U +#define DDR_PHY_ACBDLR6_A01BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR6_A01BD_SHIFT 8 +#define DDR_PHY_ACBDLR6_A01BD_MASK 0x00003F00U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR6_RESERVED_7_6_DEFVAL #undef DDR_PHY_ACBDLR6_RESERVED_7_6_SHIFT #undef DDR_PHY_ACBDLR6_RESERVED_7_6_MASK -#define DDR_PHY_ACBDLR6_RESERVED_7_6_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR6_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_ACBDLR6_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_ACBDLR6_RESERVED_7_6_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR6_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_ACBDLR6_RESERVED_7_6_MASK 0x000000C0U -/*Delay select for the BDL on Address A[0].*/ +/* +* Delay select for the BDL on Address A[0]. +*/ #undef DDR_PHY_ACBDLR6_A00BD_DEFVAL #undef DDR_PHY_ACBDLR6_A00BD_SHIFT #undef DDR_PHY_ACBDLR6_A00BD_MASK -#define DDR_PHY_ACBDLR6_A00BD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR6_A00BD_SHIFT 0 -#define DDR_PHY_ACBDLR6_A00BD_MASK 0x0000003FU +#define DDR_PHY_ACBDLR6_A00BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR6_A00BD_SHIFT 0 +#define DDR_PHY_ACBDLR6_A00BD_MASK 0x0000003FU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR7_RESERVED_31_30_DEFVAL #undef DDR_PHY_ACBDLR7_RESERVED_31_30_SHIFT #undef DDR_PHY_ACBDLR7_RESERVED_31_30_MASK -#define DDR_PHY_ACBDLR7_RESERVED_31_30_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR7_RESERVED_31_30_SHIFT 30 -#define DDR_PHY_ACBDLR7_RESERVED_31_30_MASK 0xC0000000U +#define DDR_PHY_ACBDLR7_RESERVED_31_30_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR7_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_ACBDLR7_RESERVED_31_30_MASK 0xC0000000U -/*Delay select for the BDL on Address A[7].*/ +/* +* Delay select for the BDL on Address A[7]. +*/ #undef DDR_PHY_ACBDLR7_A07BD_DEFVAL #undef DDR_PHY_ACBDLR7_A07BD_SHIFT #undef DDR_PHY_ACBDLR7_A07BD_MASK -#define DDR_PHY_ACBDLR7_A07BD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR7_A07BD_SHIFT 24 -#define DDR_PHY_ACBDLR7_A07BD_MASK 0x3F000000U +#define DDR_PHY_ACBDLR7_A07BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR7_A07BD_SHIFT 24 +#define DDR_PHY_ACBDLR7_A07BD_MASK 0x3F000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR7_RESERVED_23_22_DEFVAL #undef DDR_PHY_ACBDLR7_RESERVED_23_22_SHIFT #undef DDR_PHY_ACBDLR7_RESERVED_23_22_MASK -#define DDR_PHY_ACBDLR7_RESERVED_23_22_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR7_RESERVED_23_22_SHIFT 22 -#define DDR_PHY_ACBDLR7_RESERVED_23_22_MASK 0x00C00000U +#define DDR_PHY_ACBDLR7_RESERVED_23_22_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR7_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_ACBDLR7_RESERVED_23_22_MASK 0x00C00000U -/*Delay select for the BDL on Address A[6].*/ +/* +* Delay select for the BDL on Address A[6]. +*/ #undef DDR_PHY_ACBDLR7_A06BD_DEFVAL #undef DDR_PHY_ACBDLR7_A06BD_SHIFT #undef DDR_PHY_ACBDLR7_A06BD_MASK -#define DDR_PHY_ACBDLR7_A06BD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR7_A06BD_SHIFT 16 -#define DDR_PHY_ACBDLR7_A06BD_MASK 0x003F0000U +#define DDR_PHY_ACBDLR7_A06BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR7_A06BD_SHIFT 16 +#define DDR_PHY_ACBDLR7_A06BD_MASK 0x003F0000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR7_RESERVED_15_14_DEFVAL #undef DDR_PHY_ACBDLR7_RESERVED_15_14_SHIFT #undef DDR_PHY_ACBDLR7_RESERVED_15_14_MASK -#define DDR_PHY_ACBDLR7_RESERVED_15_14_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR7_RESERVED_15_14_SHIFT 14 -#define DDR_PHY_ACBDLR7_RESERVED_15_14_MASK 0x0000C000U +#define DDR_PHY_ACBDLR7_RESERVED_15_14_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR7_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_ACBDLR7_RESERVED_15_14_MASK 0x0000C000U -/*Delay select for the BDL on Address A[5].*/ +/* +* Delay select for the BDL on Address A[5]. +*/ #undef DDR_PHY_ACBDLR7_A05BD_DEFVAL #undef DDR_PHY_ACBDLR7_A05BD_SHIFT #undef DDR_PHY_ACBDLR7_A05BD_MASK -#define DDR_PHY_ACBDLR7_A05BD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR7_A05BD_SHIFT 8 -#define DDR_PHY_ACBDLR7_A05BD_MASK 0x00003F00U +#define DDR_PHY_ACBDLR7_A05BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR7_A05BD_SHIFT 8 +#define DDR_PHY_ACBDLR7_A05BD_MASK 0x00003F00U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR7_RESERVED_7_6_DEFVAL #undef DDR_PHY_ACBDLR7_RESERVED_7_6_SHIFT #undef DDR_PHY_ACBDLR7_RESERVED_7_6_MASK -#define DDR_PHY_ACBDLR7_RESERVED_7_6_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR7_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_ACBDLR7_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_ACBDLR7_RESERVED_7_6_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR7_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_ACBDLR7_RESERVED_7_6_MASK 0x000000C0U -/*Delay select for the BDL on Address A[4].*/ +/* +* Delay select for the BDL on Address A[4]. +*/ #undef DDR_PHY_ACBDLR7_A04BD_DEFVAL #undef DDR_PHY_ACBDLR7_A04BD_SHIFT #undef DDR_PHY_ACBDLR7_A04BD_MASK -#define DDR_PHY_ACBDLR7_A04BD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR7_A04BD_SHIFT 0 -#define DDR_PHY_ACBDLR7_A04BD_MASK 0x0000003FU +#define DDR_PHY_ACBDLR7_A04BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR7_A04BD_SHIFT 0 +#define DDR_PHY_ACBDLR7_A04BD_MASK 0x0000003FU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR8_RESERVED_31_30_DEFVAL #undef DDR_PHY_ACBDLR8_RESERVED_31_30_SHIFT #undef DDR_PHY_ACBDLR8_RESERVED_31_30_MASK -#define DDR_PHY_ACBDLR8_RESERVED_31_30_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR8_RESERVED_31_30_SHIFT 30 -#define DDR_PHY_ACBDLR8_RESERVED_31_30_MASK 0xC0000000U +#define DDR_PHY_ACBDLR8_RESERVED_31_30_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR8_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_ACBDLR8_RESERVED_31_30_MASK 0xC0000000U -/*Delay select for the BDL on Address A[11].*/ +/* +* Delay select for the BDL on Address A[11]. +*/ #undef DDR_PHY_ACBDLR8_A11BD_DEFVAL #undef DDR_PHY_ACBDLR8_A11BD_SHIFT #undef DDR_PHY_ACBDLR8_A11BD_MASK -#define DDR_PHY_ACBDLR8_A11BD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR8_A11BD_SHIFT 24 -#define DDR_PHY_ACBDLR8_A11BD_MASK 0x3F000000U +#define DDR_PHY_ACBDLR8_A11BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR8_A11BD_SHIFT 24 +#define DDR_PHY_ACBDLR8_A11BD_MASK 0x3F000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR8_RESERVED_23_22_DEFVAL #undef DDR_PHY_ACBDLR8_RESERVED_23_22_SHIFT #undef DDR_PHY_ACBDLR8_RESERVED_23_22_MASK -#define DDR_PHY_ACBDLR8_RESERVED_23_22_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR8_RESERVED_23_22_SHIFT 22 -#define DDR_PHY_ACBDLR8_RESERVED_23_22_MASK 0x00C00000U +#define DDR_PHY_ACBDLR8_RESERVED_23_22_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR8_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_ACBDLR8_RESERVED_23_22_MASK 0x00C00000U -/*Delay select for the BDL on Address A[10].*/ +/* +* Delay select for the BDL on Address A[10]. +*/ #undef DDR_PHY_ACBDLR8_A10BD_DEFVAL #undef DDR_PHY_ACBDLR8_A10BD_SHIFT #undef DDR_PHY_ACBDLR8_A10BD_MASK -#define DDR_PHY_ACBDLR8_A10BD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR8_A10BD_SHIFT 16 -#define DDR_PHY_ACBDLR8_A10BD_MASK 0x003F0000U +#define DDR_PHY_ACBDLR8_A10BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR8_A10BD_SHIFT 16 +#define DDR_PHY_ACBDLR8_A10BD_MASK 0x003F0000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR8_RESERVED_15_14_DEFVAL #undef DDR_PHY_ACBDLR8_RESERVED_15_14_SHIFT #undef DDR_PHY_ACBDLR8_RESERVED_15_14_MASK -#define DDR_PHY_ACBDLR8_RESERVED_15_14_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR8_RESERVED_15_14_SHIFT 14 -#define DDR_PHY_ACBDLR8_RESERVED_15_14_MASK 0x0000C000U +#define DDR_PHY_ACBDLR8_RESERVED_15_14_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR8_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_ACBDLR8_RESERVED_15_14_MASK 0x0000C000U -/*Delay select for the BDL on Address A[9].*/ +/* +* Delay select for the BDL on Address A[9]. +*/ #undef DDR_PHY_ACBDLR8_A09BD_DEFVAL #undef DDR_PHY_ACBDLR8_A09BD_SHIFT #undef DDR_PHY_ACBDLR8_A09BD_MASK -#define DDR_PHY_ACBDLR8_A09BD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR8_A09BD_SHIFT 8 -#define DDR_PHY_ACBDLR8_A09BD_MASK 0x00003F00U +#define DDR_PHY_ACBDLR8_A09BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR8_A09BD_SHIFT 8 +#define DDR_PHY_ACBDLR8_A09BD_MASK 0x00003F00U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR8_RESERVED_7_6_DEFVAL #undef DDR_PHY_ACBDLR8_RESERVED_7_6_SHIFT #undef DDR_PHY_ACBDLR8_RESERVED_7_6_MASK -#define DDR_PHY_ACBDLR8_RESERVED_7_6_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR8_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_ACBDLR8_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_ACBDLR8_RESERVED_7_6_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR8_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_ACBDLR8_RESERVED_7_6_MASK 0x000000C0U -/*Delay select for the BDL on Address A[8].*/ +/* +* Delay select for the BDL on Address A[8]. +*/ #undef DDR_PHY_ACBDLR8_A08BD_DEFVAL #undef DDR_PHY_ACBDLR8_A08BD_SHIFT #undef DDR_PHY_ACBDLR8_A08BD_MASK -#define DDR_PHY_ACBDLR8_A08BD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR8_A08BD_SHIFT 0 -#define DDR_PHY_ACBDLR8_A08BD_MASK 0x0000003FU +#define DDR_PHY_ACBDLR8_A08BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR8_A08BD_SHIFT 0 +#define DDR_PHY_ACBDLR8_A08BD_MASK 0x0000003FU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR9_RESERVED_31_30_DEFVAL #undef DDR_PHY_ACBDLR9_RESERVED_31_30_SHIFT #undef DDR_PHY_ACBDLR9_RESERVED_31_30_MASK -#define DDR_PHY_ACBDLR9_RESERVED_31_30_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR9_RESERVED_31_30_SHIFT 30 -#define DDR_PHY_ACBDLR9_RESERVED_31_30_MASK 0xC0000000U +#define DDR_PHY_ACBDLR9_RESERVED_31_30_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR9_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_ACBDLR9_RESERVED_31_30_MASK 0xC0000000U -/*Delay select for the BDL on Address A[15].*/ +/* +* Delay select for the BDL on Address A[15]. +*/ #undef DDR_PHY_ACBDLR9_A15BD_DEFVAL #undef DDR_PHY_ACBDLR9_A15BD_SHIFT #undef DDR_PHY_ACBDLR9_A15BD_MASK -#define DDR_PHY_ACBDLR9_A15BD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR9_A15BD_SHIFT 24 -#define DDR_PHY_ACBDLR9_A15BD_MASK 0x3F000000U +#define DDR_PHY_ACBDLR9_A15BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR9_A15BD_SHIFT 24 +#define DDR_PHY_ACBDLR9_A15BD_MASK 0x3F000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR9_RESERVED_23_22_DEFVAL #undef DDR_PHY_ACBDLR9_RESERVED_23_22_SHIFT #undef DDR_PHY_ACBDLR9_RESERVED_23_22_MASK -#define DDR_PHY_ACBDLR9_RESERVED_23_22_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR9_RESERVED_23_22_SHIFT 22 -#define DDR_PHY_ACBDLR9_RESERVED_23_22_MASK 0x00C00000U +#define DDR_PHY_ACBDLR9_RESERVED_23_22_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR9_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_ACBDLR9_RESERVED_23_22_MASK 0x00C00000U -/*Delay select for the BDL on Address A[14].*/ +/* +* Delay select for the BDL on Address A[14]. +*/ #undef DDR_PHY_ACBDLR9_A14BD_DEFVAL #undef DDR_PHY_ACBDLR9_A14BD_SHIFT #undef DDR_PHY_ACBDLR9_A14BD_MASK -#define DDR_PHY_ACBDLR9_A14BD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR9_A14BD_SHIFT 16 -#define DDR_PHY_ACBDLR9_A14BD_MASK 0x003F0000U +#define DDR_PHY_ACBDLR9_A14BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR9_A14BD_SHIFT 16 +#define DDR_PHY_ACBDLR9_A14BD_MASK 0x003F0000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR9_RESERVED_15_14_DEFVAL #undef DDR_PHY_ACBDLR9_RESERVED_15_14_SHIFT #undef DDR_PHY_ACBDLR9_RESERVED_15_14_MASK -#define DDR_PHY_ACBDLR9_RESERVED_15_14_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR9_RESERVED_15_14_SHIFT 14 -#define DDR_PHY_ACBDLR9_RESERVED_15_14_MASK 0x0000C000U +#define DDR_PHY_ACBDLR9_RESERVED_15_14_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR9_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_ACBDLR9_RESERVED_15_14_MASK 0x0000C000U -/*Delay select for the BDL on Address A[13].*/ +/* +* Delay select for the BDL on Address A[13]. +*/ #undef DDR_PHY_ACBDLR9_A13BD_DEFVAL #undef DDR_PHY_ACBDLR9_A13BD_SHIFT #undef DDR_PHY_ACBDLR9_A13BD_MASK -#define DDR_PHY_ACBDLR9_A13BD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR9_A13BD_SHIFT 8 -#define DDR_PHY_ACBDLR9_A13BD_MASK 0x00003F00U +#define DDR_PHY_ACBDLR9_A13BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR9_A13BD_SHIFT 8 +#define DDR_PHY_ACBDLR9_A13BD_MASK 0x00003F00U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR9_RESERVED_7_6_DEFVAL #undef DDR_PHY_ACBDLR9_RESERVED_7_6_SHIFT #undef DDR_PHY_ACBDLR9_RESERVED_7_6_MASK -#define DDR_PHY_ACBDLR9_RESERVED_7_6_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR9_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_ACBDLR9_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_ACBDLR9_RESERVED_7_6_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR9_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_ACBDLR9_RESERVED_7_6_MASK 0x000000C0U -/*Delay select for the BDL on Address A[12].*/ +/* +* Delay select for the BDL on Address A[12]. +*/ #undef DDR_PHY_ACBDLR9_A12BD_DEFVAL #undef DDR_PHY_ACBDLR9_A12BD_SHIFT #undef DDR_PHY_ACBDLR9_A12BD_MASK -#define DDR_PHY_ACBDLR9_A12BD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR9_A12BD_SHIFT 0 -#define DDR_PHY_ACBDLR9_A12BD_MASK 0x0000003FU +#define DDR_PHY_ACBDLR9_A12BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR9_A12BD_SHIFT 0 +#define DDR_PHY_ACBDLR9_A12BD_MASK 0x0000003FU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ZQCR_RESERVED_31_26_DEFVAL #undef DDR_PHY_ZQCR_RESERVED_31_26_SHIFT #undef DDR_PHY_ZQCR_RESERVED_31_26_MASK -#define DDR_PHY_ZQCR_RESERVED_31_26_DEFVAL 0x008A2858 -#define DDR_PHY_ZQCR_RESERVED_31_26_SHIFT 26 -#define DDR_PHY_ZQCR_RESERVED_31_26_MASK 0xFC000000U +#define DDR_PHY_ZQCR_RESERVED_31_26_DEFVAL 0x008A2858 +#define DDR_PHY_ZQCR_RESERVED_31_26_SHIFT 26 +#define DDR_PHY_ZQCR_RESERVED_31_26_MASK 0xFC000000U -/*ZQ VREF Range*/ +/* +* ZQ VREF Range +*/ #undef DDR_PHY_ZQCR_ZQREFISELRANGE_DEFVAL #undef DDR_PHY_ZQCR_ZQREFISELRANGE_SHIFT #undef DDR_PHY_ZQCR_ZQREFISELRANGE_MASK -#define DDR_PHY_ZQCR_ZQREFISELRANGE_DEFVAL 0x008A2858 -#define DDR_PHY_ZQCR_ZQREFISELRANGE_SHIFT 25 -#define DDR_PHY_ZQCR_ZQREFISELRANGE_MASK 0x02000000U +#define DDR_PHY_ZQCR_ZQREFISELRANGE_DEFVAL 0x008A2858 +#define DDR_PHY_ZQCR_ZQREFISELRANGE_SHIFT 25 +#define DDR_PHY_ZQCR_ZQREFISELRANGE_MASK 0x02000000U -/*Programmable Wait for Frequency B*/ +/* +* Programmable Wait for Frequency B +*/ #undef DDR_PHY_ZQCR_PGWAIT_FRQB_DEFVAL #undef DDR_PHY_ZQCR_PGWAIT_FRQB_SHIFT #undef DDR_PHY_ZQCR_PGWAIT_FRQB_MASK -#define DDR_PHY_ZQCR_PGWAIT_FRQB_DEFVAL 0x008A2858 -#define DDR_PHY_ZQCR_PGWAIT_FRQB_SHIFT 19 -#define DDR_PHY_ZQCR_PGWAIT_FRQB_MASK 0x01F80000U +#define DDR_PHY_ZQCR_PGWAIT_FRQB_DEFVAL 0x008A2858 +#define DDR_PHY_ZQCR_PGWAIT_FRQB_SHIFT 19 +#define DDR_PHY_ZQCR_PGWAIT_FRQB_MASK 0x01F80000U -/*Programmable Wait for Frequency A*/ +/* +* Programmable Wait for Frequency A +*/ #undef DDR_PHY_ZQCR_PGWAIT_FRQA_DEFVAL #undef DDR_PHY_ZQCR_PGWAIT_FRQA_SHIFT #undef DDR_PHY_ZQCR_PGWAIT_FRQA_MASK -#define DDR_PHY_ZQCR_PGWAIT_FRQA_DEFVAL 0x008A2858 -#define DDR_PHY_ZQCR_PGWAIT_FRQA_SHIFT 13 -#define DDR_PHY_ZQCR_PGWAIT_FRQA_MASK 0x0007E000U +#define DDR_PHY_ZQCR_PGWAIT_FRQA_DEFVAL 0x008A2858 +#define DDR_PHY_ZQCR_PGWAIT_FRQA_SHIFT 13 +#define DDR_PHY_ZQCR_PGWAIT_FRQA_MASK 0x0007E000U -/*ZQ VREF Pad Enable*/ +/* +* ZQ VREF Pad Enable +*/ #undef DDR_PHY_ZQCR_ZQREFPEN_DEFVAL #undef DDR_PHY_ZQCR_ZQREFPEN_SHIFT #undef DDR_PHY_ZQCR_ZQREFPEN_MASK -#define DDR_PHY_ZQCR_ZQREFPEN_DEFVAL 0x008A2858 -#define DDR_PHY_ZQCR_ZQREFPEN_SHIFT 12 -#define DDR_PHY_ZQCR_ZQREFPEN_MASK 0x00001000U +#define DDR_PHY_ZQCR_ZQREFPEN_DEFVAL 0x008A2858 +#define DDR_PHY_ZQCR_ZQREFPEN_SHIFT 12 +#define DDR_PHY_ZQCR_ZQREFPEN_MASK 0x00001000U -/*ZQ Internal VREF Enable*/ +/* +* ZQ Internal VREF Enable +*/ #undef DDR_PHY_ZQCR_ZQREFIEN_DEFVAL #undef DDR_PHY_ZQCR_ZQREFIEN_SHIFT #undef DDR_PHY_ZQCR_ZQREFIEN_MASK -#define DDR_PHY_ZQCR_ZQREFIEN_DEFVAL 0x008A2858 -#define DDR_PHY_ZQCR_ZQREFIEN_SHIFT 11 -#define DDR_PHY_ZQCR_ZQREFIEN_MASK 0x00000800U +#define DDR_PHY_ZQCR_ZQREFIEN_DEFVAL 0x008A2858 +#define DDR_PHY_ZQCR_ZQREFIEN_SHIFT 11 +#define DDR_PHY_ZQCR_ZQREFIEN_MASK 0x00000800U -/*Choice of termination mode*/ +/* +* Choice of termination mode +*/ #undef DDR_PHY_ZQCR_ODT_MODE_DEFVAL #undef DDR_PHY_ZQCR_ODT_MODE_SHIFT #undef DDR_PHY_ZQCR_ODT_MODE_MASK -#define DDR_PHY_ZQCR_ODT_MODE_DEFVAL 0x008A2858 -#define DDR_PHY_ZQCR_ODT_MODE_SHIFT 9 -#define DDR_PHY_ZQCR_ODT_MODE_MASK 0x00000600U +#define DDR_PHY_ZQCR_ODT_MODE_DEFVAL 0x008A2858 +#define DDR_PHY_ZQCR_ODT_MODE_SHIFT 9 +#define DDR_PHY_ZQCR_ODT_MODE_MASK 0x00000600U -/*Force ZCAL VT update*/ +/* +* Force ZCAL VT update +*/ #undef DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_DEFVAL #undef DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_SHIFT #undef DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_MASK -#define DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_DEFVAL 0x008A2858 -#define DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_SHIFT 8 -#define DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_MASK 0x00000100U +#define DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_DEFVAL 0x008A2858 +#define DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_SHIFT 8 +#define DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_MASK 0x00000100U -/*IO VT Drift Limit*/ +/* +* IO VT Drift Limit +*/ #undef DDR_PHY_ZQCR_IODLMT_DEFVAL #undef DDR_PHY_ZQCR_IODLMT_SHIFT #undef DDR_PHY_ZQCR_IODLMT_MASK -#define DDR_PHY_ZQCR_IODLMT_DEFVAL 0x008A2858 -#define DDR_PHY_ZQCR_IODLMT_SHIFT 5 -#define DDR_PHY_ZQCR_IODLMT_MASK 0x000000E0U +#define DDR_PHY_ZQCR_IODLMT_DEFVAL 0x008A2858 +#define DDR_PHY_ZQCR_IODLMT_SHIFT 5 +#define DDR_PHY_ZQCR_IODLMT_MASK 0x000000E0U -/*Averaging algorithm enable, if set, enables averaging algorithm*/ +/* +* Averaging algorithm enable, if set, enables averaging algorithm +*/ #undef DDR_PHY_ZQCR_AVGEN_DEFVAL #undef DDR_PHY_ZQCR_AVGEN_SHIFT #undef DDR_PHY_ZQCR_AVGEN_MASK -#define DDR_PHY_ZQCR_AVGEN_DEFVAL 0x008A2858 -#define DDR_PHY_ZQCR_AVGEN_SHIFT 4 -#define DDR_PHY_ZQCR_AVGEN_MASK 0x00000010U +#define DDR_PHY_ZQCR_AVGEN_DEFVAL 0x008A2858 +#define DDR_PHY_ZQCR_AVGEN_SHIFT 4 +#define DDR_PHY_ZQCR_AVGEN_MASK 0x00000010U -/*Maximum number of averaging rounds to be used by averaging algorithm*/ +/* +* Maximum number of averaging rounds to be used by averaging algorithm +*/ #undef DDR_PHY_ZQCR_AVGMAX_DEFVAL #undef DDR_PHY_ZQCR_AVGMAX_SHIFT #undef DDR_PHY_ZQCR_AVGMAX_MASK -#define DDR_PHY_ZQCR_AVGMAX_DEFVAL 0x008A2858 -#define DDR_PHY_ZQCR_AVGMAX_SHIFT 2 -#define DDR_PHY_ZQCR_AVGMAX_MASK 0x0000000CU +#define DDR_PHY_ZQCR_AVGMAX_DEFVAL 0x008A2858 +#define DDR_PHY_ZQCR_AVGMAX_SHIFT 2 +#define DDR_PHY_ZQCR_AVGMAX_MASK 0x0000000CU -/*ZQ Calibration Type*/ +/* +* ZQ Calibration Type +*/ #undef DDR_PHY_ZQCR_ZCALT_DEFVAL #undef DDR_PHY_ZQCR_ZCALT_SHIFT #undef DDR_PHY_ZQCR_ZCALT_MASK -#define DDR_PHY_ZQCR_ZCALT_DEFVAL 0x008A2858 -#define DDR_PHY_ZQCR_ZCALT_SHIFT 1 -#define DDR_PHY_ZQCR_ZCALT_MASK 0x00000002U +#define DDR_PHY_ZQCR_ZCALT_DEFVAL 0x008A2858 +#define DDR_PHY_ZQCR_ZCALT_SHIFT 1 +#define DDR_PHY_ZQCR_ZCALT_MASK 0x00000002U -/*ZQ Power Down*/ +/* +* ZQ Power Down +*/ #undef DDR_PHY_ZQCR_ZQPD_DEFVAL #undef DDR_PHY_ZQCR_ZQPD_SHIFT #undef DDR_PHY_ZQCR_ZQPD_MASK -#define DDR_PHY_ZQCR_ZQPD_DEFVAL 0x008A2858 -#define DDR_PHY_ZQCR_ZQPD_SHIFT 0 -#define DDR_PHY_ZQCR_ZQPD_MASK 0x00000001U +#define DDR_PHY_ZQCR_ZQPD_DEFVAL 0x008A2858 +#define DDR_PHY_ZQCR_ZQPD_SHIFT 0 +#define DDR_PHY_ZQCR_ZQPD_MASK 0x00000001U -/*Pull-down drive strength ZCTRL over-ride enable*/ +/* +* Pull-down drive strength ZCTRL over-ride enable +*/ #undef DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_DEFVAL #undef DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_SHIFT #undef DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_MASK -#define DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_DEFVAL 0x000077BB -#define DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_SHIFT 31 -#define DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_MASK 0x80000000U +#define DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_DEFVAL 0x000077BB +#define DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_SHIFT 31 +#define DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_MASK 0x80000000U -/*Pull-up drive strength ZCTRL over-ride enable*/ +/* +* Pull-up drive strength ZCTRL over-ride enable +*/ #undef DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_DEFVAL #undef DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_SHIFT #undef DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_MASK -#define DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_DEFVAL 0x000077BB -#define DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_SHIFT 30 -#define DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_MASK 0x40000000U +#define DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_DEFVAL 0x000077BB +#define DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_SHIFT 30 +#define DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_MASK 0x40000000U -/*Pull-down termination ZCTRL over-ride enable*/ +/* +* Pull-down termination ZCTRL over-ride enable +*/ #undef DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_DEFVAL #undef DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_SHIFT #undef DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_MASK -#define DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_DEFVAL 0x000077BB -#define DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_SHIFT 29 -#define DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_MASK 0x20000000U +#define DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_DEFVAL 0x000077BB +#define DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_SHIFT 29 +#define DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_MASK 0x20000000U -/*Pull-up termination ZCTRL over-ride enable*/ +/* +* Pull-up termination ZCTRL over-ride enable +*/ #undef DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_DEFVAL #undef DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_SHIFT #undef DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_MASK -#define DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_DEFVAL 0x000077BB -#define DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_SHIFT 28 -#define DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_MASK 0x10000000U +#define DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_DEFVAL 0x000077BB +#define DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_SHIFT 28 +#define DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_MASK 0x10000000U -/*Calibration segment bypass*/ +/* +* Calibration segment bypass +*/ #undef DDR_PHY_ZQ0PR0_ZSEGBYP_DEFVAL #undef DDR_PHY_ZQ0PR0_ZSEGBYP_SHIFT #undef DDR_PHY_ZQ0PR0_ZSEGBYP_MASK -#define DDR_PHY_ZQ0PR0_ZSEGBYP_DEFVAL 0x000077BB -#define DDR_PHY_ZQ0PR0_ZSEGBYP_SHIFT 27 -#define DDR_PHY_ZQ0PR0_ZSEGBYP_MASK 0x08000000U +#define DDR_PHY_ZQ0PR0_ZSEGBYP_DEFVAL 0x000077BB +#define DDR_PHY_ZQ0PR0_ZSEGBYP_SHIFT 27 +#define DDR_PHY_ZQ0PR0_ZSEGBYP_MASK 0x08000000U -/*VREF latch mode controls the mode in which the ZLE pin of the PVREF cell is driven by the PUB*/ +/* +* VREF latch mode controls the mode in which the ZLE pin of the PVREF cell + * is driven by the PUB +*/ #undef DDR_PHY_ZQ0PR0_ZLE_MODE_DEFVAL #undef DDR_PHY_ZQ0PR0_ZLE_MODE_SHIFT #undef DDR_PHY_ZQ0PR0_ZLE_MODE_MASK -#define DDR_PHY_ZQ0PR0_ZLE_MODE_DEFVAL 0x000077BB -#define DDR_PHY_ZQ0PR0_ZLE_MODE_SHIFT 25 -#define DDR_PHY_ZQ0PR0_ZLE_MODE_MASK 0x06000000U +#define DDR_PHY_ZQ0PR0_ZLE_MODE_DEFVAL 0x000077BB +#define DDR_PHY_ZQ0PR0_ZLE_MODE_SHIFT 25 +#define DDR_PHY_ZQ0PR0_ZLE_MODE_MASK 0x06000000U -/*Termination adjustment*/ +/* +* Termination adjustment +*/ #undef DDR_PHY_ZQ0PR0_ODT_ADJUST_DEFVAL #undef DDR_PHY_ZQ0PR0_ODT_ADJUST_SHIFT #undef DDR_PHY_ZQ0PR0_ODT_ADJUST_MASK -#define DDR_PHY_ZQ0PR0_ODT_ADJUST_DEFVAL 0x000077BB -#define DDR_PHY_ZQ0PR0_ODT_ADJUST_SHIFT 22 -#define DDR_PHY_ZQ0PR0_ODT_ADJUST_MASK 0x01C00000U +#define DDR_PHY_ZQ0PR0_ODT_ADJUST_DEFVAL 0x000077BB +#define DDR_PHY_ZQ0PR0_ODT_ADJUST_SHIFT 22 +#define DDR_PHY_ZQ0PR0_ODT_ADJUST_MASK 0x01C00000U -/*Pulldown drive strength adjustment*/ +/* +* Pulldown drive strength adjustment +*/ #undef DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_DEFVAL #undef DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_SHIFT #undef DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_MASK -#define DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_DEFVAL 0x000077BB -#define DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_SHIFT 19 -#define DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_MASK 0x00380000U +#define DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_DEFVAL 0x000077BB +#define DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_SHIFT 19 +#define DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_MASK 0x00380000U -/*Pullup drive strength adjustment*/ +/* +* Pullup drive strength adjustment +*/ #undef DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_DEFVAL #undef DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_SHIFT #undef DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_MASK -#define DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_DEFVAL 0x000077BB -#define DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_SHIFT 16 -#define DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_MASK 0x00070000U +#define DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_DEFVAL 0x000077BB +#define DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_SHIFT 16 +#define DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_MASK 0x00070000U -/*DRAM Impedance Divide Ratio*/ +/* +* DRAM Impedance Divide Ratio +*/ #undef DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_DEFVAL #undef DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_SHIFT #undef DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_MASK -#define DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_DEFVAL 0x000077BB -#define DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_SHIFT 12 -#define DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_MASK 0x0000F000U +#define DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_DEFVAL 0x000077BB +#define DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_SHIFT 12 +#define DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_MASK 0x0000F000U -/*HOST Impedance Divide Ratio*/ +/* +* HOST Impedance Divide Ratio +*/ #undef DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_DEFVAL #undef DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_SHIFT #undef DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_MASK -#define DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_DEFVAL 0x000077BB -#define DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_SHIFT 8 -#define DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_MASK 0x00000F00U +#define DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_DEFVAL 0x000077BB +#define DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_SHIFT 8 +#define DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_MASK 0x00000F00U -/*Impedance Divide Ratio (pulldown drive calibration during asymmetric drive strength calibration)*/ +/* +* Impedance Divide Ratio (pulldown drive calibration during asymmetric dri + * ve strength calibration) +*/ #undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_DEFVAL #undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_SHIFT #undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_MASK -#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_DEFVAL 0x000077BB -#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_SHIFT 4 -#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_MASK 0x000000F0U +#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_DEFVAL 0x000077BB +#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_SHIFT 4 +#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_MASK 0x000000F0U -/*Impedance Divide Ratio (pullup drive calibration during asymmetric drive strength calibration)*/ +/* +* Impedance Divide Ratio (pullup drive calibration during asymmetric drive + * strength calibration) +*/ #undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_DEFVAL #undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_SHIFT #undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_MASK -#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_DEFVAL 0x000077BB -#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_SHIFT 0 -#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_MASK 0x0000000FU +#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_DEFVAL 0x000077BB +#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_SHIFT 0 +#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_MASK 0x0000000FU -/*Reserved. Return zeros on reads.*/ +/* +* Reserved. Return zeros on reads. +*/ #undef DDR_PHY_ZQ0OR0_RESERVED_31_26_DEFVAL #undef DDR_PHY_ZQ0OR0_RESERVED_31_26_SHIFT #undef DDR_PHY_ZQ0OR0_RESERVED_31_26_MASK -#define DDR_PHY_ZQ0OR0_RESERVED_31_26_DEFVAL 0x00000000 -#define DDR_PHY_ZQ0OR0_RESERVED_31_26_SHIFT 26 -#define DDR_PHY_ZQ0OR0_RESERVED_31_26_MASK 0xFC000000U +#define DDR_PHY_ZQ0OR0_RESERVED_31_26_DEFVAL 0x00000000 +#define DDR_PHY_ZQ0OR0_RESERVED_31_26_SHIFT 26 +#define DDR_PHY_ZQ0OR0_RESERVED_31_26_MASK 0xFC000000U -/*Override value for the pull-up output impedance*/ +/* +* Override value for the pull-up output impedance +*/ #undef DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_DEFVAL #undef DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_SHIFT #undef DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_MASK -#define DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_DEFVAL 0x00000000 -#define DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_SHIFT 16 -#define DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_MASK 0x03FF0000U +#define DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_DEFVAL 0x00000000 +#define DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_SHIFT 16 +#define DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_MASK 0x03FF0000U -/*Reserved. Return zeros on reads.*/ +/* +* Reserved. Return zeros on reads. +*/ #undef DDR_PHY_ZQ0OR0_RESERVED_15_10_DEFVAL #undef DDR_PHY_ZQ0OR0_RESERVED_15_10_SHIFT #undef DDR_PHY_ZQ0OR0_RESERVED_15_10_MASK -#define DDR_PHY_ZQ0OR0_RESERVED_15_10_DEFVAL 0x00000000 -#define DDR_PHY_ZQ0OR0_RESERVED_15_10_SHIFT 10 -#define DDR_PHY_ZQ0OR0_RESERVED_15_10_MASK 0x0000FC00U +#define DDR_PHY_ZQ0OR0_RESERVED_15_10_DEFVAL 0x00000000 +#define DDR_PHY_ZQ0OR0_RESERVED_15_10_SHIFT 10 +#define DDR_PHY_ZQ0OR0_RESERVED_15_10_MASK 0x0000FC00U -/*Override value for the pull-down output impedance*/ +/* +* Override value for the pull-down output impedance +*/ #undef DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_DEFVAL #undef DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_SHIFT #undef DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_MASK -#define DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_DEFVAL 0x00000000 -#define DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_SHIFT 0 -#define DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_MASK 0x000003FFU +#define DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_DEFVAL 0x00000000 +#define DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_SHIFT 0 +#define DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_MASK 0x000003FFU -/*Reserved. Return zeros on reads.*/ +/* +* Reserved. Return zeros on reads. +*/ #undef DDR_PHY_ZQ0OR1_RESERVED_31_26_DEFVAL #undef DDR_PHY_ZQ0OR1_RESERVED_31_26_SHIFT #undef DDR_PHY_ZQ0OR1_RESERVED_31_26_MASK -#define DDR_PHY_ZQ0OR1_RESERVED_31_26_DEFVAL 0x00000000 -#define DDR_PHY_ZQ0OR1_RESERVED_31_26_SHIFT 26 -#define DDR_PHY_ZQ0OR1_RESERVED_31_26_MASK 0xFC000000U +#define DDR_PHY_ZQ0OR1_RESERVED_31_26_DEFVAL 0x00000000 +#define DDR_PHY_ZQ0OR1_RESERVED_31_26_SHIFT 26 +#define DDR_PHY_ZQ0OR1_RESERVED_31_26_MASK 0xFC000000U -/*Override value for the pull-up termination*/ +/* +* Override value for the pull-up termination +*/ #undef DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_DEFVAL #undef DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_SHIFT #undef DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_MASK -#define DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_DEFVAL 0x00000000 -#define DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_SHIFT 16 -#define DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_MASK 0x03FF0000U +#define DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_DEFVAL 0x00000000 +#define DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_SHIFT 16 +#define DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_MASK 0x03FF0000U -/*Reserved. Return zeros on reads.*/ +/* +* Reserved. Return zeros on reads. +*/ #undef DDR_PHY_ZQ0OR1_RESERVED_15_10_DEFVAL #undef DDR_PHY_ZQ0OR1_RESERVED_15_10_SHIFT #undef DDR_PHY_ZQ0OR1_RESERVED_15_10_MASK -#define DDR_PHY_ZQ0OR1_RESERVED_15_10_DEFVAL 0x00000000 -#define DDR_PHY_ZQ0OR1_RESERVED_15_10_SHIFT 10 -#define DDR_PHY_ZQ0OR1_RESERVED_15_10_MASK 0x0000FC00U +#define DDR_PHY_ZQ0OR1_RESERVED_15_10_DEFVAL 0x00000000 +#define DDR_PHY_ZQ0OR1_RESERVED_15_10_SHIFT 10 +#define DDR_PHY_ZQ0OR1_RESERVED_15_10_MASK 0x0000FC00U -/*Override value for the pull-down termination*/ +/* +* Override value for the pull-down termination +*/ #undef DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_DEFVAL #undef DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_SHIFT #undef DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_MASK -#define DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_DEFVAL 0x00000000 -#define DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_SHIFT 0 -#define DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_MASK 0x000003FFU +#define DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_DEFVAL 0x00000000 +#define DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_SHIFT 0 +#define DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_MASK 0x000003FFU -/*Pull-down drive strength ZCTRL over-ride enable*/ +/* +* Pull-down drive strength ZCTRL over-ride enable +*/ #undef DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_DEFVAL #undef DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_SHIFT #undef DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_MASK -#define DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_DEFVAL 0x000077BB -#define DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_SHIFT 31 -#define DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_MASK 0x80000000U +#define DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_DEFVAL 0x000077BB +#define DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_SHIFT 31 +#define DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_MASK 0x80000000U -/*Pull-up drive strength ZCTRL over-ride enable*/ +/* +* Pull-up drive strength ZCTRL over-ride enable +*/ #undef DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_DEFVAL #undef DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_SHIFT #undef DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_MASK -#define DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_DEFVAL 0x000077BB -#define DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_SHIFT 30 -#define DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_MASK 0x40000000U +#define DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_DEFVAL 0x000077BB +#define DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_SHIFT 30 +#define DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_MASK 0x40000000U -/*Pull-down termination ZCTRL over-ride enable*/ +/* +* Pull-down termination ZCTRL over-ride enable +*/ #undef DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_DEFVAL #undef DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_SHIFT #undef DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_MASK -#define DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_DEFVAL 0x000077BB -#define DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_SHIFT 29 -#define DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_MASK 0x20000000U +#define DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_DEFVAL 0x000077BB +#define DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_SHIFT 29 +#define DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_MASK 0x20000000U -/*Pull-up termination ZCTRL over-ride enable*/ +/* +* Pull-up termination ZCTRL over-ride enable +*/ #undef DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_DEFVAL #undef DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_SHIFT #undef DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_MASK -#define DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_DEFVAL 0x000077BB -#define DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_SHIFT 28 -#define DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_MASK 0x10000000U +#define DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_DEFVAL 0x000077BB +#define DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_SHIFT 28 +#define DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_MASK 0x10000000U -/*Calibration segment bypass*/ +/* +* Calibration segment bypass +*/ #undef DDR_PHY_ZQ1PR0_ZSEGBYP_DEFVAL #undef DDR_PHY_ZQ1PR0_ZSEGBYP_SHIFT #undef DDR_PHY_ZQ1PR0_ZSEGBYP_MASK -#define DDR_PHY_ZQ1PR0_ZSEGBYP_DEFVAL 0x000077BB -#define DDR_PHY_ZQ1PR0_ZSEGBYP_SHIFT 27 -#define DDR_PHY_ZQ1PR0_ZSEGBYP_MASK 0x08000000U +#define DDR_PHY_ZQ1PR0_ZSEGBYP_DEFVAL 0x000077BB +#define DDR_PHY_ZQ1PR0_ZSEGBYP_SHIFT 27 +#define DDR_PHY_ZQ1PR0_ZSEGBYP_MASK 0x08000000U -/*VREF latch mode controls the mode in which the ZLE pin of the PVREF cell is driven by the PUB*/ +/* +* VREF latch mode controls the mode in which the ZLE pin of the PVREF cell + * is driven by the PUB +*/ #undef DDR_PHY_ZQ1PR0_ZLE_MODE_DEFVAL #undef DDR_PHY_ZQ1PR0_ZLE_MODE_SHIFT #undef DDR_PHY_ZQ1PR0_ZLE_MODE_MASK -#define DDR_PHY_ZQ1PR0_ZLE_MODE_DEFVAL 0x000077BB -#define DDR_PHY_ZQ1PR0_ZLE_MODE_SHIFT 25 -#define DDR_PHY_ZQ1PR0_ZLE_MODE_MASK 0x06000000U +#define DDR_PHY_ZQ1PR0_ZLE_MODE_DEFVAL 0x000077BB +#define DDR_PHY_ZQ1PR0_ZLE_MODE_SHIFT 25 +#define DDR_PHY_ZQ1PR0_ZLE_MODE_MASK 0x06000000U -/*Termination adjustment*/ +/* +* Termination adjustment +*/ #undef DDR_PHY_ZQ1PR0_ODT_ADJUST_DEFVAL #undef DDR_PHY_ZQ1PR0_ODT_ADJUST_SHIFT #undef DDR_PHY_ZQ1PR0_ODT_ADJUST_MASK -#define DDR_PHY_ZQ1PR0_ODT_ADJUST_DEFVAL 0x000077BB -#define DDR_PHY_ZQ1PR0_ODT_ADJUST_SHIFT 22 -#define DDR_PHY_ZQ1PR0_ODT_ADJUST_MASK 0x01C00000U +#define DDR_PHY_ZQ1PR0_ODT_ADJUST_DEFVAL 0x000077BB +#define DDR_PHY_ZQ1PR0_ODT_ADJUST_SHIFT 22 +#define DDR_PHY_ZQ1PR0_ODT_ADJUST_MASK 0x01C00000U -/*Pulldown drive strength adjustment*/ +/* +* Pulldown drive strength adjustment +*/ #undef DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_DEFVAL #undef DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_SHIFT #undef DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_MASK -#define DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_DEFVAL 0x000077BB -#define DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_SHIFT 19 -#define DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_MASK 0x00380000U +#define DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_DEFVAL 0x000077BB +#define DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_SHIFT 19 +#define DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_MASK 0x00380000U -/*Pullup drive strength adjustment*/ +/* +* Pullup drive strength adjustment +*/ #undef DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_DEFVAL #undef DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_SHIFT #undef DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_MASK -#define DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_DEFVAL 0x000077BB -#define DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_SHIFT 16 -#define DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_MASK 0x00070000U +#define DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_DEFVAL 0x000077BB +#define DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_SHIFT 16 +#define DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_MASK 0x00070000U -/*DRAM Impedance Divide Ratio*/ +/* +* DRAM Impedance Divide Ratio +*/ #undef DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_DEFVAL #undef DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_SHIFT #undef DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_MASK -#define DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_DEFVAL 0x000077BB -#define DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_SHIFT 12 -#define DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_MASK 0x0000F000U +#define DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_DEFVAL 0x000077BB +#define DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_SHIFT 12 +#define DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_MASK 0x0000F000U -/*HOST Impedance Divide Ratio*/ +/* +* HOST Impedance Divide Ratio +*/ #undef DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_DEFVAL #undef DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_SHIFT #undef DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_MASK -#define DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_DEFVAL 0x000077BB -#define DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_SHIFT 8 -#define DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_MASK 0x00000F00U +#define DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_DEFVAL 0x000077BB +#define DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_SHIFT 8 +#define DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_MASK 0x00000F00U -/*Impedance Divide Ratio (pulldown drive calibration during asymmetric drive strength calibration)*/ +/* +* Impedance Divide Ratio (pulldown drive calibration during asymmetric dri + * ve strength calibration) +*/ #undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_DEFVAL #undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_SHIFT #undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_MASK -#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_DEFVAL 0x000077BB -#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_SHIFT 4 -#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_MASK 0x000000F0U +#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_DEFVAL 0x000077BB +#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_SHIFT 4 +#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_MASK 0x000000F0U -/*Impedance Divide Ratio (pullup drive calibration during asymmetric drive strength calibration)*/ +/* +* Impedance Divide Ratio (pullup drive calibration during asymmetric drive + * strength calibration) +*/ #undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_DEFVAL #undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_SHIFT #undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_MASK -#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_DEFVAL 0x000077BB -#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_SHIFT 0 -#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_MASK 0x0000000FU +#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_DEFVAL 0x000077BB +#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_SHIFT 0 +#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_MASK 0x0000000FU -/*Calibration Bypass*/ +/* +* Calibration Bypass +*/ #undef DDR_PHY_DX0GCR0_CALBYP_DEFVAL #undef DDR_PHY_DX0GCR0_CALBYP_SHIFT #undef DDR_PHY_DX0GCR0_CALBYP_MASK -#define DDR_PHY_DX0GCR0_CALBYP_DEFVAL 0x40200204 -#define DDR_PHY_DX0GCR0_CALBYP_SHIFT 31 -#define DDR_PHY_DX0GCR0_CALBYP_MASK 0x80000000U +#define DDR_PHY_DX0GCR0_CALBYP_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_CALBYP_SHIFT 31 +#define DDR_PHY_DX0GCR0_CALBYP_MASK 0x80000000U -/*Master Delay Line Enable*/ +/* +* Master Delay Line Enable +*/ #undef DDR_PHY_DX0GCR0_MDLEN_DEFVAL #undef DDR_PHY_DX0GCR0_MDLEN_SHIFT #undef DDR_PHY_DX0GCR0_MDLEN_MASK -#define DDR_PHY_DX0GCR0_MDLEN_DEFVAL 0x40200204 -#define DDR_PHY_DX0GCR0_MDLEN_SHIFT 30 -#define DDR_PHY_DX0GCR0_MDLEN_MASK 0x40000000U +#define DDR_PHY_DX0GCR0_MDLEN_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_MDLEN_SHIFT 30 +#define DDR_PHY_DX0GCR0_MDLEN_MASK 0x40000000U -/*Configurable ODT(TE) Phase Shift*/ +/* +* Configurable ODT(TE) Phase Shift +*/ #undef DDR_PHY_DX0GCR0_CODTSHFT_DEFVAL #undef DDR_PHY_DX0GCR0_CODTSHFT_SHIFT #undef DDR_PHY_DX0GCR0_CODTSHFT_MASK -#define DDR_PHY_DX0GCR0_CODTSHFT_DEFVAL 0x40200204 -#define DDR_PHY_DX0GCR0_CODTSHFT_SHIFT 28 -#define DDR_PHY_DX0GCR0_CODTSHFT_MASK 0x30000000U +#define DDR_PHY_DX0GCR0_CODTSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_CODTSHFT_SHIFT 28 +#define DDR_PHY_DX0GCR0_CODTSHFT_MASK 0x30000000U -/*DQS Duty Cycle Correction*/ +/* +* DQS Duty Cycle Correction +*/ #undef DDR_PHY_DX0GCR0_DQSDCC_DEFVAL #undef DDR_PHY_DX0GCR0_DQSDCC_SHIFT #undef DDR_PHY_DX0GCR0_DQSDCC_MASK -#define DDR_PHY_DX0GCR0_DQSDCC_DEFVAL 0x40200204 -#define DDR_PHY_DX0GCR0_DQSDCC_SHIFT 24 -#define DDR_PHY_DX0GCR0_DQSDCC_MASK 0x0F000000U +#define DDR_PHY_DX0GCR0_DQSDCC_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_DQSDCC_SHIFT 24 +#define DDR_PHY_DX0GCR0_DQSDCC_MASK 0x0F000000U -/*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/ +/* +* Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY +*/ #undef DDR_PHY_DX0GCR0_RDDLY_DEFVAL #undef DDR_PHY_DX0GCR0_RDDLY_SHIFT #undef DDR_PHY_DX0GCR0_RDDLY_MASK -#define DDR_PHY_DX0GCR0_RDDLY_DEFVAL 0x40200204 -#define DDR_PHY_DX0GCR0_RDDLY_SHIFT 20 -#define DDR_PHY_DX0GCR0_RDDLY_MASK 0x00F00000U +#define DDR_PHY_DX0GCR0_RDDLY_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_RDDLY_SHIFT 20 +#define DDR_PHY_DX0GCR0_RDDLY_MASK 0x00F00000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX0GCR0_RESERVED_19_14_DEFVAL #undef DDR_PHY_DX0GCR0_RESERVED_19_14_SHIFT #undef DDR_PHY_DX0GCR0_RESERVED_19_14_MASK -#define DDR_PHY_DX0GCR0_RESERVED_19_14_DEFVAL 0x40200204 -#define DDR_PHY_DX0GCR0_RESERVED_19_14_SHIFT 14 -#define DDR_PHY_DX0GCR0_RESERVED_19_14_MASK 0x000FC000U +#define DDR_PHY_DX0GCR0_RESERVED_19_14_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_RESERVED_19_14_SHIFT 14 +#define DDR_PHY_DX0GCR0_RESERVED_19_14_MASK 0x000FC000U -/*DQSNSE Power Down Receiver*/ +/* +* DQSNSE Power Down Receiver +*/ #undef DDR_PHY_DX0GCR0_DQSNSEPDR_DEFVAL #undef DDR_PHY_DX0GCR0_DQSNSEPDR_SHIFT #undef DDR_PHY_DX0GCR0_DQSNSEPDR_MASK -#define DDR_PHY_DX0GCR0_DQSNSEPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX0GCR0_DQSNSEPDR_SHIFT 13 -#define DDR_PHY_DX0GCR0_DQSNSEPDR_MASK 0x00002000U +#define DDR_PHY_DX0GCR0_DQSNSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_DQSNSEPDR_SHIFT 13 +#define DDR_PHY_DX0GCR0_DQSNSEPDR_MASK 0x00002000U -/*DQSSE Power Down Receiver*/ +/* +* DQSSE Power Down Receiver +*/ #undef DDR_PHY_DX0GCR0_DQSSEPDR_DEFVAL #undef DDR_PHY_DX0GCR0_DQSSEPDR_SHIFT #undef DDR_PHY_DX0GCR0_DQSSEPDR_MASK -#define DDR_PHY_DX0GCR0_DQSSEPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX0GCR0_DQSSEPDR_SHIFT 12 -#define DDR_PHY_DX0GCR0_DQSSEPDR_MASK 0x00001000U +#define DDR_PHY_DX0GCR0_DQSSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_DQSSEPDR_SHIFT 12 +#define DDR_PHY_DX0GCR0_DQSSEPDR_MASK 0x00001000U -/*RTT On Additive Latency*/ +/* +* RTT On Additive Latency +*/ #undef DDR_PHY_DX0GCR0_RTTOAL_DEFVAL #undef DDR_PHY_DX0GCR0_RTTOAL_SHIFT #undef DDR_PHY_DX0GCR0_RTTOAL_MASK -#define DDR_PHY_DX0GCR0_RTTOAL_DEFVAL 0x40200204 -#define DDR_PHY_DX0GCR0_RTTOAL_SHIFT 11 -#define DDR_PHY_DX0GCR0_RTTOAL_MASK 0x00000800U +#define DDR_PHY_DX0GCR0_RTTOAL_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_RTTOAL_SHIFT 11 +#define DDR_PHY_DX0GCR0_RTTOAL_MASK 0x00000800U -/*RTT Output Hold*/ +/* +* RTT Output Hold +*/ #undef DDR_PHY_DX0GCR0_RTTOH_DEFVAL #undef DDR_PHY_DX0GCR0_RTTOH_SHIFT #undef DDR_PHY_DX0GCR0_RTTOH_MASK -#define DDR_PHY_DX0GCR0_RTTOH_DEFVAL 0x40200204 -#define DDR_PHY_DX0GCR0_RTTOH_SHIFT 9 -#define DDR_PHY_DX0GCR0_RTTOH_MASK 0x00000600U +#define DDR_PHY_DX0GCR0_RTTOH_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_RTTOH_SHIFT 9 +#define DDR_PHY_DX0GCR0_RTTOH_MASK 0x00000600U -/*Configurable PDR Phase Shift*/ +/* +* Configurable PDR Phase Shift +*/ #undef DDR_PHY_DX0GCR0_CPDRSHFT_DEFVAL #undef DDR_PHY_DX0GCR0_CPDRSHFT_SHIFT #undef DDR_PHY_DX0GCR0_CPDRSHFT_MASK -#define DDR_PHY_DX0GCR0_CPDRSHFT_DEFVAL 0x40200204 -#define DDR_PHY_DX0GCR0_CPDRSHFT_SHIFT 7 -#define DDR_PHY_DX0GCR0_CPDRSHFT_MASK 0x00000180U +#define DDR_PHY_DX0GCR0_CPDRSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_CPDRSHFT_SHIFT 7 +#define DDR_PHY_DX0GCR0_CPDRSHFT_MASK 0x00000180U -/*DQSR Power Down*/ +/* +* DQSR Power Down +*/ #undef DDR_PHY_DX0GCR0_DQSRPD_DEFVAL #undef DDR_PHY_DX0GCR0_DQSRPD_SHIFT #undef DDR_PHY_DX0GCR0_DQSRPD_MASK -#define DDR_PHY_DX0GCR0_DQSRPD_DEFVAL 0x40200204 -#define DDR_PHY_DX0GCR0_DQSRPD_SHIFT 6 -#define DDR_PHY_DX0GCR0_DQSRPD_MASK 0x00000040U +#define DDR_PHY_DX0GCR0_DQSRPD_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_DQSRPD_SHIFT 6 +#define DDR_PHY_DX0GCR0_DQSRPD_MASK 0x00000040U -/*DQSG Power Down Receiver*/ +/* +* DQSG Power Down Receiver +*/ #undef DDR_PHY_DX0GCR0_DQSGPDR_DEFVAL #undef DDR_PHY_DX0GCR0_DQSGPDR_SHIFT #undef DDR_PHY_DX0GCR0_DQSGPDR_MASK -#define DDR_PHY_DX0GCR0_DQSGPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX0GCR0_DQSGPDR_SHIFT 5 -#define DDR_PHY_DX0GCR0_DQSGPDR_MASK 0x00000020U +#define DDR_PHY_DX0GCR0_DQSGPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_DQSGPDR_SHIFT 5 +#define DDR_PHY_DX0GCR0_DQSGPDR_MASK 0x00000020U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX0GCR0_RESERVED_4_DEFVAL #undef DDR_PHY_DX0GCR0_RESERVED_4_SHIFT #undef DDR_PHY_DX0GCR0_RESERVED_4_MASK -#define DDR_PHY_DX0GCR0_RESERVED_4_DEFVAL 0x40200204 -#define DDR_PHY_DX0GCR0_RESERVED_4_SHIFT 4 -#define DDR_PHY_DX0GCR0_RESERVED_4_MASK 0x00000010U +#define DDR_PHY_DX0GCR0_RESERVED_4_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_RESERVED_4_SHIFT 4 +#define DDR_PHY_DX0GCR0_RESERVED_4_MASK 0x00000010U -/*DQSG On-Die Termination*/ +/* +* DQSG On-Die Termination +*/ #undef DDR_PHY_DX0GCR0_DQSGODT_DEFVAL #undef DDR_PHY_DX0GCR0_DQSGODT_SHIFT #undef DDR_PHY_DX0GCR0_DQSGODT_MASK -#define DDR_PHY_DX0GCR0_DQSGODT_DEFVAL 0x40200204 -#define DDR_PHY_DX0GCR0_DQSGODT_SHIFT 3 -#define DDR_PHY_DX0GCR0_DQSGODT_MASK 0x00000008U +#define DDR_PHY_DX0GCR0_DQSGODT_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_DQSGODT_SHIFT 3 +#define DDR_PHY_DX0GCR0_DQSGODT_MASK 0x00000008U -/*DQSG Output Enable*/ +/* +* DQSG Output Enable +*/ #undef DDR_PHY_DX0GCR0_DQSGOE_DEFVAL #undef DDR_PHY_DX0GCR0_DQSGOE_SHIFT #undef DDR_PHY_DX0GCR0_DQSGOE_MASK -#define DDR_PHY_DX0GCR0_DQSGOE_DEFVAL 0x40200204 -#define DDR_PHY_DX0GCR0_DQSGOE_SHIFT 2 -#define DDR_PHY_DX0GCR0_DQSGOE_MASK 0x00000004U +#define DDR_PHY_DX0GCR0_DQSGOE_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_DQSGOE_SHIFT 2 +#define DDR_PHY_DX0GCR0_DQSGOE_MASK 0x00000004U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX0GCR0_RESERVED_1_0_DEFVAL #undef DDR_PHY_DX0GCR0_RESERVED_1_0_SHIFT #undef DDR_PHY_DX0GCR0_RESERVED_1_0_MASK -#define DDR_PHY_DX0GCR0_RESERVED_1_0_DEFVAL 0x40200204 -#define DDR_PHY_DX0GCR0_RESERVED_1_0_SHIFT 0 -#define DDR_PHY_DX0GCR0_RESERVED_1_0_MASK 0x00000003U +#define DDR_PHY_DX0GCR0_RESERVED_1_0_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_RESERVED_1_0_SHIFT 0 +#define DDR_PHY_DX0GCR0_RESERVED_1_0_MASK 0x00000003U -/*Byte lane VREF IOM (Used only by D4MU IOs)*/ +/* +* Byte lane VREF IOM (Used only by D4MU IOs) +*/ #undef DDR_PHY_DX0GCR4_RESERVED_31_29_DEFVAL #undef DDR_PHY_DX0GCR4_RESERVED_31_29_SHIFT #undef DDR_PHY_DX0GCR4_RESERVED_31_29_MASK -#define DDR_PHY_DX0GCR4_RESERVED_31_29_DEFVAL 0x0E00003C -#define DDR_PHY_DX0GCR4_RESERVED_31_29_SHIFT 29 -#define DDR_PHY_DX0GCR4_RESERVED_31_29_MASK 0xE0000000U +#define DDR_PHY_DX0GCR4_RESERVED_31_29_DEFVAL 0x0E00003C +#define DDR_PHY_DX0GCR4_RESERVED_31_29_SHIFT 29 +#define DDR_PHY_DX0GCR4_RESERVED_31_29_MASK 0xE0000000U -/*Byte Lane VREF Pad Enable*/ +/* +* Byte Lane VREF Pad Enable +*/ #undef DDR_PHY_DX0GCR4_DXREFPEN_DEFVAL #undef DDR_PHY_DX0GCR4_DXREFPEN_SHIFT #undef DDR_PHY_DX0GCR4_DXREFPEN_MASK -#define DDR_PHY_DX0GCR4_DXREFPEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX0GCR4_DXREFPEN_SHIFT 28 -#define DDR_PHY_DX0GCR4_DXREFPEN_MASK 0x10000000U +#define DDR_PHY_DX0GCR4_DXREFPEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX0GCR4_DXREFPEN_SHIFT 28 +#define DDR_PHY_DX0GCR4_DXREFPEN_MASK 0x10000000U -/*Byte Lane Internal VREF Enable*/ +/* +* Byte Lane Internal VREF Enable +*/ #undef DDR_PHY_DX0GCR4_DXREFEEN_DEFVAL #undef DDR_PHY_DX0GCR4_DXREFEEN_SHIFT #undef DDR_PHY_DX0GCR4_DXREFEEN_MASK -#define DDR_PHY_DX0GCR4_DXREFEEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX0GCR4_DXREFEEN_SHIFT 26 -#define DDR_PHY_DX0GCR4_DXREFEEN_MASK 0x0C000000U +#define DDR_PHY_DX0GCR4_DXREFEEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX0GCR4_DXREFEEN_SHIFT 26 +#define DDR_PHY_DX0GCR4_DXREFEEN_MASK 0x0C000000U -/*Byte Lane Single-End VREF Enable*/ +/* +* Byte Lane Single-End VREF Enable +*/ #undef DDR_PHY_DX0GCR4_DXREFSEN_DEFVAL #undef DDR_PHY_DX0GCR4_DXREFSEN_SHIFT #undef DDR_PHY_DX0GCR4_DXREFSEN_MASK -#define DDR_PHY_DX0GCR4_DXREFSEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX0GCR4_DXREFSEN_SHIFT 25 -#define DDR_PHY_DX0GCR4_DXREFSEN_MASK 0x02000000U +#define DDR_PHY_DX0GCR4_DXREFSEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX0GCR4_DXREFSEN_SHIFT 25 +#define DDR_PHY_DX0GCR4_DXREFSEN_MASK 0x02000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX0GCR4_RESERVED_24_DEFVAL #undef DDR_PHY_DX0GCR4_RESERVED_24_SHIFT #undef DDR_PHY_DX0GCR4_RESERVED_24_MASK -#define DDR_PHY_DX0GCR4_RESERVED_24_DEFVAL 0x0E00003C -#define DDR_PHY_DX0GCR4_RESERVED_24_SHIFT 24 -#define DDR_PHY_DX0GCR4_RESERVED_24_MASK 0x01000000U +#define DDR_PHY_DX0GCR4_RESERVED_24_DEFVAL 0x0E00003C +#define DDR_PHY_DX0GCR4_RESERVED_24_SHIFT 24 +#define DDR_PHY_DX0GCR4_RESERVED_24_MASK 0x01000000U -/*External VREF generator REFSEL range select*/ +/* +* External VREF generator REFSEL range select +*/ #undef DDR_PHY_DX0GCR4_DXREFESELRANGE_DEFVAL #undef DDR_PHY_DX0GCR4_DXREFESELRANGE_SHIFT #undef DDR_PHY_DX0GCR4_DXREFESELRANGE_MASK -#define DDR_PHY_DX0GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C -#define DDR_PHY_DX0GCR4_DXREFESELRANGE_SHIFT 23 -#define DDR_PHY_DX0GCR4_DXREFESELRANGE_MASK 0x00800000U +#define DDR_PHY_DX0GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX0GCR4_DXREFESELRANGE_SHIFT 23 +#define DDR_PHY_DX0GCR4_DXREFESELRANGE_MASK 0x00800000U -/*Byte Lane External VREF Select*/ +/* +* Byte Lane External VREF Select +*/ #undef DDR_PHY_DX0GCR4_DXREFESEL_DEFVAL #undef DDR_PHY_DX0GCR4_DXREFESEL_SHIFT #undef DDR_PHY_DX0GCR4_DXREFESEL_MASK -#define DDR_PHY_DX0GCR4_DXREFESEL_DEFVAL 0x0E00003C -#define DDR_PHY_DX0GCR4_DXREFESEL_SHIFT 16 -#define DDR_PHY_DX0GCR4_DXREFESEL_MASK 0x007F0000U +#define DDR_PHY_DX0GCR4_DXREFESEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX0GCR4_DXREFESEL_SHIFT 16 +#define DDR_PHY_DX0GCR4_DXREFESEL_MASK 0x007F0000U -/*Single ended VREF generator REFSEL range select*/ +/* +* Single ended VREF generator REFSEL range select +*/ #undef DDR_PHY_DX0GCR4_DXREFSSELRANGE_DEFVAL #undef DDR_PHY_DX0GCR4_DXREFSSELRANGE_SHIFT #undef DDR_PHY_DX0GCR4_DXREFSSELRANGE_MASK -#define DDR_PHY_DX0GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C -#define DDR_PHY_DX0GCR4_DXREFSSELRANGE_SHIFT 15 -#define DDR_PHY_DX0GCR4_DXREFSSELRANGE_MASK 0x00008000U +#define DDR_PHY_DX0GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX0GCR4_DXREFSSELRANGE_SHIFT 15 +#define DDR_PHY_DX0GCR4_DXREFSSELRANGE_MASK 0x00008000U -/*Byte Lane Single-End VREF Select*/ +/* +* Byte Lane Single-End VREF Select +*/ #undef DDR_PHY_DX0GCR4_DXREFSSEL_DEFVAL #undef DDR_PHY_DX0GCR4_DXREFSSEL_SHIFT #undef DDR_PHY_DX0GCR4_DXREFSSEL_MASK -#define DDR_PHY_DX0GCR4_DXREFSSEL_DEFVAL 0x0E00003C -#define DDR_PHY_DX0GCR4_DXREFSSEL_SHIFT 8 -#define DDR_PHY_DX0GCR4_DXREFSSEL_MASK 0x00007F00U +#define DDR_PHY_DX0GCR4_DXREFSSEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX0GCR4_DXREFSSEL_SHIFT 8 +#define DDR_PHY_DX0GCR4_DXREFSSEL_MASK 0x00007F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX0GCR4_RESERVED_7_6_DEFVAL #undef DDR_PHY_DX0GCR4_RESERVED_7_6_SHIFT #undef DDR_PHY_DX0GCR4_RESERVED_7_6_MASK -#define DDR_PHY_DX0GCR4_RESERVED_7_6_DEFVAL 0x0E00003C -#define DDR_PHY_DX0GCR4_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_DX0GCR4_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_DX0GCR4_RESERVED_7_6_DEFVAL 0x0E00003C +#define DDR_PHY_DX0GCR4_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX0GCR4_RESERVED_7_6_MASK 0x000000C0U -/*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/ +/* +* VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. +*/ #undef DDR_PHY_DX0GCR4_DXREFIEN_DEFVAL #undef DDR_PHY_DX0GCR4_DXREFIEN_SHIFT #undef DDR_PHY_DX0GCR4_DXREFIEN_MASK -#define DDR_PHY_DX0GCR4_DXREFIEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX0GCR4_DXREFIEN_SHIFT 2 -#define DDR_PHY_DX0GCR4_DXREFIEN_MASK 0x0000003CU +#define DDR_PHY_DX0GCR4_DXREFIEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX0GCR4_DXREFIEN_SHIFT 2 +#define DDR_PHY_DX0GCR4_DXREFIEN_MASK 0x0000003CU -/*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/ +/* +* VRMON control for DQ IO (Single Ended) buffers of a byte lane. +*/ #undef DDR_PHY_DX0GCR4_DXREFIMON_DEFVAL #undef DDR_PHY_DX0GCR4_DXREFIMON_SHIFT #undef DDR_PHY_DX0GCR4_DXREFIMON_MASK -#define DDR_PHY_DX0GCR4_DXREFIMON_DEFVAL 0x0E00003C -#define DDR_PHY_DX0GCR4_DXREFIMON_SHIFT 0 -#define DDR_PHY_DX0GCR4_DXREFIMON_MASK 0x00000003U +#define DDR_PHY_DX0GCR4_DXREFIMON_DEFVAL 0x0E00003C +#define DDR_PHY_DX0GCR4_DXREFIMON_SHIFT 0 +#define DDR_PHY_DX0GCR4_DXREFIMON_MASK 0x00000003U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX0GCR5_RESERVED_31_DEFVAL #undef DDR_PHY_DX0GCR5_RESERVED_31_SHIFT #undef DDR_PHY_DX0GCR5_RESERVED_31_MASK -#define DDR_PHY_DX0GCR5_RESERVED_31_DEFVAL 0x09090909 -#define DDR_PHY_DX0GCR5_RESERVED_31_SHIFT 31 -#define DDR_PHY_DX0GCR5_RESERVED_31_MASK 0x80000000U +#define DDR_PHY_DX0GCR5_RESERVED_31_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR5_RESERVED_31_SHIFT 31 +#define DDR_PHY_DX0GCR5_RESERVED_31_MASK 0x80000000U -/*Byte Lane internal VREF Select for Rank 3*/ +/* +* Byte Lane internal VREF Select for Rank 3 +*/ #undef DDR_PHY_DX0GCR5_DXREFISELR3_DEFVAL #undef DDR_PHY_DX0GCR5_DXREFISELR3_SHIFT #undef DDR_PHY_DX0GCR5_DXREFISELR3_MASK -#define DDR_PHY_DX0GCR5_DXREFISELR3_DEFVAL 0x09090909 -#define DDR_PHY_DX0GCR5_DXREFISELR3_SHIFT 24 -#define DDR_PHY_DX0GCR5_DXREFISELR3_MASK 0x7F000000U +#define DDR_PHY_DX0GCR5_DXREFISELR3_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR5_DXREFISELR3_SHIFT 24 +#define DDR_PHY_DX0GCR5_DXREFISELR3_MASK 0x7F000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX0GCR5_RESERVED_23_DEFVAL #undef DDR_PHY_DX0GCR5_RESERVED_23_SHIFT #undef DDR_PHY_DX0GCR5_RESERVED_23_MASK -#define DDR_PHY_DX0GCR5_RESERVED_23_DEFVAL 0x09090909 -#define DDR_PHY_DX0GCR5_RESERVED_23_SHIFT 23 -#define DDR_PHY_DX0GCR5_RESERVED_23_MASK 0x00800000U +#define DDR_PHY_DX0GCR5_RESERVED_23_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR5_RESERVED_23_SHIFT 23 +#define DDR_PHY_DX0GCR5_RESERVED_23_MASK 0x00800000U -/*Byte Lane internal VREF Select for Rank 2*/ +/* +* Byte Lane internal VREF Select for Rank 2 +*/ #undef DDR_PHY_DX0GCR5_DXREFISELR2_DEFVAL #undef DDR_PHY_DX0GCR5_DXREFISELR2_SHIFT #undef DDR_PHY_DX0GCR5_DXREFISELR2_MASK -#define DDR_PHY_DX0GCR5_DXREFISELR2_DEFVAL 0x09090909 -#define DDR_PHY_DX0GCR5_DXREFISELR2_SHIFT 16 -#define DDR_PHY_DX0GCR5_DXREFISELR2_MASK 0x007F0000U +#define DDR_PHY_DX0GCR5_DXREFISELR2_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR5_DXREFISELR2_SHIFT 16 +#define DDR_PHY_DX0GCR5_DXREFISELR2_MASK 0x007F0000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX0GCR5_RESERVED_15_DEFVAL #undef DDR_PHY_DX0GCR5_RESERVED_15_SHIFT #undef DDR_PHY_DX0GCR5_RESERVED_15_MASK -#define DDR_PHY_DX0GCR5_RESERVED_15_DEFVAL 0x09090909 -#define DDR_PHY_DX0GCR5_RESERVED_15_SHIFT 15 -#define DDR_PHY_DX0GCR5_RESERVED_15_MASK 0x00008000U +#define DDR_PHY_DX0GCR5_RESERVED_15_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR5_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX0GCR5_RESERVED_15_MASK 0x00008000U -/*Byte Lane internal VREF Select for Rank 1*/ +/* +* Byte Lane internal VREF Select for Rank 1 +*/ #undef DDR_PHY_DX0GCR5_DXREFISELR1_DEFVAL #undef DDR_PHY_DX0GCR5_DXREFISELR1_SHIFT #undef DDR_PHY_DX0GCR5_DXREFISELR1_MASK -#define DDR_PHY_DX0GCR5_DXREFISELR1_DEFVAL 0x09090909 -#define DDR_PHY_DX0GCR5_DXREFISELR1_SHIFT 8 -#define DDR_PHY_DX0GCR5_DXREFISELR1_MASK 0x00007F00U +#define DDR_PHY_DX0GCR5_DXREFISELR1_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR5_DXREFISELR1_SHIFT 8 +#define DDR_PHY_DX0GCR5_DXREFISELR1_MASK 0x00007F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX0GCR5_RESERVED_7_DEFVAL #undef DDR_PHY_DX0GCR5_RESERVED_7_SHIFT #undef DDR_PHY_DX0GCR5_RESERVED_7_MASK -#define DDR_PHY_DX0GCR5_RESERVED_7_DEFVAL 0x09090909 -#define DDR_PHY_DX0GCR5_RESERVED_7_SHIFT 7 -#define DDR_PHY_DX0GCR5_RESERVED_7_MASK 0x00000080U +#define DDR_PHY_DX0GCR5_RESERVED_7_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR5_RESERVED_7_SHIFT 7 +#define DDR_PHY_DX0GCR5_RESERVED_7_MASK 0x00000080U -/*Byte Lane internal VREF Select for Rank 0*/ +/* +* Byte Lane internal VREF Select for Rank 0 +*/ #undef DDR_PHY_DX0GCR5_DXREFISELR0_DEFVAL #undef DDR_PHY_DX0GCR5_DXREFISELR0_SHIFT #undef DDR_PHY_DX0GCR5_DXREFISELR0_MASK -#define DDR_PHY_DX0GCR5_DXREFISELR0_DEFVAL 0x09090909 -#define DDR_PHY_DX0GCR5_DXREFISELR0_SHIFT 0 -#define DDR_PHY_DX0GCR5_DXREFISELR0_MASK 0x0000007FU +#define DDR_PHY_DX0GCR5_DXREFISELR0_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR5_DXREFISELR0_SHIFT 0 +#define DDR_PHY_DX0GCR5_DXREFISELR0_MASK 0x0000007FU -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX0GCR6_RESERVED_31_30_DEFVAL #undef DDR_PHY_DX0GCR6_RESERVED_31_30_SHIFT #undef DDR_PHY_DX0GCR6_RESERVED_31_30_MASK -#define DDR_PHY_DX0GCR6_RESERVED_31_30_DEFVAL 0x09090909 -#define DDR_PHY_DX0GCR6_RESERVED_31_30_SHIFT 30 -#define DDR_PHY_DX0GCR6_RESERVED_31_30_MASK 0xC0000000U +#define DDR_PHY_DX0GCR6_RESERVED_31_30_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR6_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX0GCR6_RESERVED_31_30_MASK 0xC0000000U -/*DRAM DQ VREF Select for Rank3*/ +/* +* DRAM DQ VREF Select for Rank3 +*/ #undef DDR_PHY_DX0GCR6_DXDQVREFR3_DEFVAL #undef DDR_PHY_DX0GCR6_DXDQVREFR3_SHIFT #undef DDR_PHY_DX0GCR6_DXDQVREFR3_MASK -#define DDR_PHY_DX0GCR6_DXDQVREFR3_DEFVAL 0x09090909 -#define DDR_PHY_DX0GCR6_DXDQVREFR3_SHIFT 24 -#define DDR_PHY_DX0GCR6_DXDQVREFR3_MASK 0x3F000000U +#define DDR_PHY_DX0GCR6_DXDQVREFR3_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR6_DXDQVREFR3_SHIFT 24 +#define DDR_PHY_DX0GCR6_DXDQVREFR3_MASK 0x3F000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX0GCR6_RESERVED_23_22_DEFVAL #undef DDR_PHY_DX0GCR6_RESERVED_23_22_SHIFT #undef DDR_PHY_DX0GCR6_RESERVED_23_22_MASK -#define DDR_PHY_DX0GCR6_RESERVED_23_22_DEFVAL 0x09090909 -#define DDR_PHY_DX0GCR6_RESERVED_23_22_SHIFT 22 -#define DDR_PHY_DX0GCR6_RESERVED_23_22_MASK 0x00C00000U +#define DDR_PHY_DX0GCR6_RESERVED_23_22_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR6_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX0GCR6_RESERVED_23_22_MASK 0x00C00000U -/*DRAM DQ VREF Select for Rank2*/ +/* +* DRAM DQ VREF Select for Rank2 +*/ #undef DDR_PHY_DX0GCR6_DXDQVREFR2_DEFVAL #undef DDR_PHY_DX0GCR6_DXDQVREFR2_SHIFT #undef DDR_PHY_DX0GCR6_DXDQVREFR2_MASK -#define DDR_PHY_DX0GCR6_DXDQVREFR2_DEFVAL 0x09090909 -#define DDR_PHY_DX0GCR6_DXDQVREFR2_SHIFT 16 -#define DDR_PHY_DX0GCR6_DXDQVREFR2_MASK 0x003F0000U +#define DDR_PHY_DX0GCR6_DXDQVREFR2_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR6_DXDQVREFR2_SHIFT 16 +#define DDR_PHY_DX0GCR6_DXDQVREFR2_MASK 0x003F0000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX0GCR6_RESERVED_15_14_DEFVAL #undef DDR_PHY_DX0GCR6_RESERVED_15_14_SHIFT #undef DDR_PHY_DX0GCR6_RESERVED_15_14_MASK -#define DDR_PHY_DX0GCR6_RESERVED_15_14_DEFVAL 0x09090909 -#define DDR_PHY_DX0GCR6_RESERVED_15_14_SHIFT 14 -#define DDR_PHY_DX0GCR6_RESERVED_15_14_MASK 0x0000C000U +#define DDR_PHY_DX0GCR6_RESERVED_15_14_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR6_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_DX0GCR6_RESERVED_15_14_MASK 0x0000C000U -/*DRAM DQ VREF Select for Rank1*/ +/* +* DRAM DQ VREF Select for Rank1 +*/ #undef DDR_PHY_DX0GCR6_DXDQVREFR1_DEFVAL #undef DDR_PHY_DX0GCR6_DXDQVREFR1_SHIFT #undef DDR_PHY_DX0GCR6_DXDQVREFR1_MASK -#define DDR_PHY_DX0GCR6_DXDQVREFR1_DEFVAL 0x09090909 -#define DDR_PHY_DX0GCR6_DXDQVREFR1_SHIFT 8 -#define DDR_PHY_DX0GCR6_DXDQVREFR1_MASK 0x00003F00U +#define DDR_PHY_DX0GCR6_DXDQVREFR1_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR6_DXDQVREFR1_SHIFT 8 +#define DDR_PHY_DX0GCR6_DXDQVREFR1_MASK 0x00003F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX0GCR6_RESERVED_7_6_DEFVAL #undef DDR_PHY_DX0GCR6_RESERVED_7_6_SHIFT #undef DDR_PHY_DX0GCR6_RESERVED_7_6_MASK -#define DDR_PHY_DX0GCR6_RESERVED_7_6_DEFVAL 0x09090909 -#define DDR_PHY_DX0GCR6_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_DX0GCR6_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_DX0GCR6_RESERVED_7_6_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR6_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX0GCR6_RESERVED_7_6_MASK 0x000000C0U -/*DRAM DQ VREF Select for Rank0*/ +/* +* DRAM DQ VREF Select for Rank0 +*/ #undef DDR_PHY_DX0GCR6_DXDQVREFR0_DEFVAL #undef DDR_PHY_DX0GCR6_DXDQVREFR0_SHIFT #undef DDR_PHY_DX0GCR6_DXDQVREFR0_MASK -#define DDR_PHY_DX0GCR6_DXDQVREFR0_DEFVAL 0x09090909 -#define DDR_PHY_DX0GCR6_DXDQVREFR0_SHIFT 0 -#define DDR_PHY_DX0GCR6_DXDQVREFR0_MASK 0x0000003FU +#define DDR_PHY_DX0GCR6_DXDQVREFR0_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR6_DXDQVREFR0_SHIFT 0 +#define DDR_PHY_DX0GCR6_DXDQVREFR0_MASK 0x0000003FU -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX0LCDLR2_RESERVED_31_25_DEFVAL -#undef DDR_PHY_DX0LCDLR2_RESERVED_31_25_SHIFT -#undef DDR_PHY_DX0LCDLR2_RESERVED_31_25_MASK -#define DDR_PHY_DX0LCDLR2_RESERVED_31_25_DEFVAL 0x00000000 -#define DDR_PHY_DX0LCDLR2_RESERVED_31_25_SHIFT 25 -#define DDR_PHY_DX0LCDLR2_RESERVED_31_25_MASK 0xFE000000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX0LCDLR2_RESERVED_24_16_DEFVAL -#undef DDR_PHY_DX0LCDLR2_RESERVED_24_16_SHIFT -#undef DDR_PHY_DX0LCDLR2_RESERVED_24_16_MASK -#define DDR_PHY_DX0LCDLR2_RESERVED_24_16_DEFVAL 0x00000000 -#define DDR_PHY_DX0LCDLR2_RESERVED_24_16_SHIFT 16 -#define DDR_PHY_DX0LCDLR2_RESERVED_24_16_MASK 0x01FF0000U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX0LCDLR2_RESERVED_15_9_DEFVAL -#undef DDR_PHY_DX0LCDLR2_RESERVED_15_9_SHIFT -#undef DDR_PHY_DX0LCDLR2_RESERVED_15_9_MASK -#define DDR_PHY_DX0LCDLR2_RESERVED_15_9_DEFVAL 0x00000000 -#define DDR_PHY_DX0LCDLR2_RESERVED_15_9_SHIFT 9 -#define DDR_PHY_DX0LCDLR2_RESERVED_15_9_MASK 0x0000FE00U - -/*Read DQS Gating Delay*/ -#undef DDR_PHY_DX0LCDLR2_DQSGD_DEFVAL -#undef DDR_PHY_DX0LCDLR2_DQSGD_SHIFT -#undef DDR_PHY_DX0LCDLR2_DQSGD_MASK -#define DDR_PHY_DX0LCDLR2_DQSGD_DEFVAL 0x00000000 -#define DDR_PHY_DX0LCDLR2_DQSGD_SHIFT 0 -#define DDR_PHY_DX0LCDLR2_DQSGD_MASK 0x000001FFU - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX0GTR0_RESERVED_31_24_DEFVAL -#undef DDR_PHY_DX0GTR0_RESERVED_31_24_SHIFT -#undef DDR_PHY_DX0GTR0_RESERVED_31_24_MASK -#define DDR_PHY_DX0GTR0_RESERVED_31_24_DEFVAL 0x00020000 -#define DDR_PHY_DX0GTR0_RESERVED_31_24_SHIFT 27 -#define DDR_PHY_DX0GTR0_RESERVED_31_24_MASK 0xF8000000U - -/*DQ Write Path Latency Pipeline*/ -#undef DDR_PHY_DX0GTR0_WDQSL_DEFVAL -#undef DDR_PHY_DX0GTR0_WDQSL_SHIFT -#undef DDR_PHY_DX0GTR0_WDQSL_MASK -#define DDR_PHY_DX0GTR0_WDQSL_DEFVAL 0x00020000 -#define DDR_PHY_DX0GTR0_WDQSL_SHIFT 24 -#define DDR_PHY_DX0GTR0_WDQSL_MASK 0x07000000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX0GTR0_RESERVED_23_20_DEFVAL -#undef DDR_PHY_DX0GTR0_RESERVED_23_20_SHIFT -#undef DDR_PHY_DX0GTR0_RESERVED_23_20_MASK -#define DDR_PHY_DX0GTR0_RESERVED_23_20_DEFVAL 0x00020000 -#define DDR_PHY_DX0GTR0_RESERVED_23_20_SHIFT 20 -#define DDR_PHY_DX0GTR0_RESERVED_23_20_MASK 0x00F00000U - -/*Write Leveling System Latency*/ -#undef DDR_PHY_DX0GTR0_WLSL_DEFVAL -#undef DDR_PHY_DX0GTR0_WLSL_SHIFT -#undef DDR_PHY_DX0GTR0_WLSL_MASK -#define DDR_PHY_DX0GTR0_WLSL_DEFVAL 0x00020000 -#define DDR_PHY_DX0GTR0_WLSL_SHIFT 16 -#define DDR_PHY_DX0GTR0_WLSL_MASK 0x000F0000U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX0GTR0_RESERVED_15_13_DEFVAL -#undef DDR_PHY_DX0GTR0_RESERVED_15_13_SHIFT -#undef DDR_PHY_DX0GTR0_RESERVED_15_13_MASK -#define DDR_PHY_DX0GTR0_RESERVED_15_13_DEFVAL 0x00020000 -#define DDR_PHY_DX0GTR0_RESERVED_15_13_SHIFT 13 -#define DDR_PHY_DX0GTR0_RESERVED_15_13_MASK 0x0000E000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX0GTR0_RESERVED_12_8_DEFVAL -#undef DDR_PHY_DX0GTR0_RESERVED_12_8_SHIFT -#undef DDR_PHY_DX0GTR0_RESERVED_12_8_MASK -#define DDR_PHY_DX0GTR0_RESERVED_12_8_DEFVAL 0x00020000 -#define DDR_PHY_DX0GTR0_RESERVED_12_8_SHIFT 8 -#define DDR_PHY_DX0GTR0_RESERVED_12_8_MASK 0x00001F00U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX0GTR0_RESERVED_7_5_DEFVAL -#undef DDR_PHY_DX0GTR0_RESERVED_7_5_SHIFT -#undef DDR_PHY_DX0GTR0_RESERVED_7_5_MASK -#define DDR_PHY_DX0GTR0_RESERVED_7_5_DEFVAL 0x00020000 -#define DDR_PHY_DX0GTR0_RESERVED_7_5_SHIFT 5 -#define DDR_PHY_DX0GTR0_RESERVED_7_5_MASK 0x000000E0U - -/*DQS Gating System Latency*/ -#undef DDR_PHY_DX0GTR0_DGSL_DEFVAL -#undef DDR_PHY_DX0GTR0_DGSL_SHIFT -#undef DDR_PHY_DX0GTR0_DGSL_MASK -#define DDR_PHY_DX0GTR0_DGSL_DEFVAL 0x00020000 -#define DDR_PHY_DX0GTR0_DGSL_SHIFT 0 -#define DDR_PHY_DX0GTR0_DGSL_MASK 0x0000001FU - -/*Calibration Bypass*/ +/* +* Calibration Bypass +*/ #undef DDR_PHY_DX1GCR0_CALBYP_DEFVAL #undef DDR_PHY_DX1GCR0_CALBYP_SHIFT #undef DDR_PHY_DX1GCR0_CALBYP_MASK -#define DDR_PHY_DX1GCR0_CALBYP_DEFVAL 0x40200204 -#define DDR_PHY_DX1GCR0_CALBYP_SHIFT 31 -#define DDR_PHY_DX1GCR0_CALBYP_MASK 0x80000000U +#define DDR_PHY_DX1GCR0_CALBYP_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_CALBYP_SHIFT 31 +#define DDR_PHY_DX1GCR0_CALBYP_MASK 0x80000000U -/*Master Delay Line Enable*/ +/* +* Master Delay Line Enable +*/ #undef DDR_PHY_DX1GCR0_MDLEN_DEFVAL #undef DDR_PHY_DX1GCR0_MDLEN_SHIFT #undef DDR_PHY_DX1GCR0_MDLEN_MASK -#define DDR_PHY_DX1GCR0_MDLEN_DEFVAL 0x40200204 -#define DDR_PHY_DX1GCR0_MDLEN_SHIFT 30 -#define DDR_PHY_DX1GCR0_MDLEN_MASK 0x40000000U +#define DDR_PHY_DX1GCR0_MDLEN_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_MDLEN_SHIFT 30 +#define DDR_PHY_DX1GCR0_MDLEN_MASK 0x40000000U -/*Configurable ODT(TE) Phase Shift*/ +/* +* Configurable ODT(TE) Phase Shift +*/ #undef DDR_PHY_DX1GCR0_CODTSHFT_DEFVAL #undef DDR_PHY_DX1GCR0_CODTSHFT_SHIFT #undef DDR_PHY_DX1GCR0_CODTSHFT_MASK -#define DDR_PHY_DX1GCR0_CODTSHFT_DEFVAL 0x40200204 -#define DDR_PHY_DX1GCR0_CODTSHFT_SHIFT 28 -#define DDR_PHY_DX1GCR0_CODTSHFT_MASK 0x30000000U +#define DDR_PHY_DX1GCR0_CODTSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_CODTSHFT_SHIFT 28 +#define DDR_PHY_DX1GCR0_CODTSHFT_MASK 0x30000000U -/*DQS Duty Cycle Correction*/ +/* +* DQS Duty Cycle Correction +*/ #undef DDR_PHY_DX1GCR0_DQSDCC_DEFVAL #undef DDR_PHY_DX1GCR0_DQSDCC_SHIFT #undef DDR_PHY_DX1GCR0_DQSDCC_MASK -#define DDR_PHY_DX1GCR0_DQSDCC_DEFVAL 0x40200204 -#define DDR_PHY_DX1GCR0_DQSDCC_SHIFT 24 -#define DDR_PHY_DX1GCR0_DQSDCC_MASK 0x0F000000U +#define DDR_PHY_DX1GCR0_DQSDCC_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_DQSDCC_SHIFT 24 +#define DDR_PHY_DX1GCR0_DQSDCC_MASK 0x0F000000U -/*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/ +/* +* Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY +*/ #undef DDR_PHY_DX1GCR0_RDDLY_DEFVAL #undef DDR_PHY_DX1GCR0_RDDLY_SHIFT #undef DDR_PHY_DX1GCR0_RDDLY_MASK -#define DDR_PHY_DX1GCR0_RDDLY_DEFVAL 0x40200204 -#define DDR_PHY_DX1GCR0_RDDLY_SHIFT 20 -#define DDR_PHY_DX1GCR0_RDDLY_MASK 0x00F00000U +#define DDR_PHY_DX1GCR0_RDDLY_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_RDDLY_SHIFT 20 +#define DDR_PHY_DX1GCR0_RDDLY_MASK 0x00F00000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX1GCR0_RESERVED_19_14_DEFVAL #undef DDR_PHY_DX1GCR0_RESERVED_19_14_SHIFT #undef DDR_PHY_DX1GCR0_RESERVED_19_14_MASK -#define DDR_PHY_DX1GCR0_RESERVED_19_14_DEFVAL 0x40200204 -#define DDR_PHY_DX1GCR0_RESERVED_19_14_SHIFT 14 -#define DDR_PHY_DX1GCR0_RESERVED_19_14_MASK 0x000FC000U +#define DDR_PHY_DX1GCR0_RESERVED_19_14_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_RESERVED_19_14_SHIFT 14 +#define DDR_PHY_DX1GCR0_RESERVED_19_14_MASK 0x000FC000U -/*DQSNSE Power Down Receiver*/ +/* +* DQSNSE Power Down Receiver +*/ #undef DDR_PHY_DX1GCR0_DQSNSEPDR_DEFVAL #undef DDR_PHY_DX1GCR0_DQSNSEPDR_SHIFT #undef DDR_PHY_DX1GCR0_DQSNSEPDR_MASK -#define DDR_PHY_DX1GCR0_DQSNSEPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX1GCR0_DQSNSEPDR_SHIFT 13 -#define DDR_PHY_DX1GCR0_DQSNSEPDR_MASK 0x00002000U +#define DDR_PHY_DX1GCR0_DQSNSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_DQSNSEPDR_SHIFT 13 +#define DDR_PHY_DX1GCR0_DQSNSEPDR_MASK 0x00002000U -/*DQSSE Power Down Receiver*/ +/* +* DQSSE Power Down Receiver +*/ #undef DDR_PHY_DX1GCR0_DQSSEPDR_DEFVAL #undef DDR_PHY_DX1GCR0_DQSSEPDR_SHIFT #undef DDR_PHY_DX1GCR0_DQSSEPDR_MASK -#define DDR_PHY_DX1GCR0_DQSSEPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX1GCR0_DQSSEPDR_SHIFT 12 -#define DDR_PHY_DX1GCR0_DQSSEPDR_MASK 0x00001000U +#define DDR_PHY_DX1GCR0_DQSSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_DQSSEPDR_SHIFT 12 +#define DDR_PHY_DX1GCR0_DQSSEPDR_MASK 0x00001000U -/*RTT On Additive Latency*/ +/* +* RTT On Additive Latency +*/ #undef DDR_PHY_DX1GCR0_RTTOAL_DEFVAL #undef DDR_PHY_DX1GCR0_RTTOAL_SHIFT #undef DDR_PHY_DX1GCR0_RTTOAL_MASK -#define DDR_PHY_DX1GCR0_RTTOAL_DEFVAL 0x40200204 -#define DDR_PHY_DX1GCR0_RTTOAL_SHIFT 11 -#define DDR_PHY_DX1GCR0_RTTOAL_MASK 0x00000800U +#define DDR_PHY_DX1GCR0_RTTOAL_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_RTTOAL_SHIFT 11 +#define DDR_PHY_DX1GCR0_RTTOAL_MASK 0x00000800U -/*RTT Output Hold*/ +/* +* RTT Output Hold +*/ #undef DDR_PHY_DX1GCR0_RTTOH_DEFVAL #undef DDR_PHY_DX1GCR0_RTTOH_SHIFT #undef DDR_PHY_DX1GCR0_RTTOH_MASK -#define DDR_PHY_DX1GCR0_RTTOH_DEFVAL 0x40200204 -#define DDR_PHY_DX1GCR0_RTTOH_SHIFT 9 -#define DDR_PHY_DX1GCR0_RTTOH_MASK 0x00000600U +#define DDR_PHY_DX1GCR0_RTTOH_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_RTTOH_SHIFT 9 +#define DDR_PHY_DX1GCR0_RTTOH_MASK 0x00000600U -/*Configurable PDR Phase Shift*/ +/* +* Configurable PDR Phase Shift +*/ #undef DDR_PHY_DX1GCR0_CPDRSHFT_DEFVAL #undef DDR_PHY_DX1GCR0_CPDRSHFT_SHIFT #undef DDR_PHY_DX1GCR0_CPDRSHFT_MASK -#define DDR_PHY_DX1GCR0_CPDRSHFT_DEFVAL 0x40200204 -#define DDR_PHY_DX1GCR0_CPDRSHFT_SHIFT 7 -#define DDR_PHY_DX1GCR0_CPDRSHFT_MASK 0x00000180U +#define DDR_PHY_DX1GCR0_CPDRSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_CPDRSHFT_SHIFT 7 +#define DDR_PHY_DX1GCR0_CPDRSHFT_MASK 0x00000180U -/*DQSR Power Down*/ +/* +* DQSR Power Down +*/ #undef DDR_PHY_DX1GCR0_DQSRPD_DEFVAL #undef DDR_PHY_DX1GCR0_DQSRPD_SHIFT #undef DDR_PHY_DX1GCR0_DQSRPD_MASK -#define DDR_PHY_DX1GCR0_DQSRPD_DEFVAL 0x40200204 -#define DDR_PHY_DX1GCR0_DQSRPD_SHIFT 6 -#define DDR_PHY_DX1GCR0_DQSRPD_MASK 0x00000040U +#define DDR_PHY_DX1GCR0_DQSRPD_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_DQSRPD_SHIFT 6 +#define DDR_PHY_DX1GCR0_DQSRPD_MASK 0x00000040U -/*DQSG Power Down Receiver*/ +/* +* DQSG Power Down Receiver +*/ #undef DDR_PHY_DX1GCR0_DQSGPDR_DEFVAL #undef DDR_PHY_DX1GCR0_DQSGPDR_SHIFT #undef DDR_PHY_DX1GCR0_DQSGPDR_MASK -#define DDR_PHY_DX1GCR0_DQSGPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX1GCR0_DQSGPDR_SHIFT 5 -#define DDR_PHY_DX1GCR0_DQSGPDR_MASK 0x00000020U +#define DDR_PHY_DX1GCR0_DQSGPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_DQSGPDR_SHIFT 5 +#define DDR_PHY_DX1GCR0_DQSGPDR_MASK 0x00000020U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX1GCR0_RESERVED_4_DEFVAL #undef DDR_PHY_DX1GCR0_RESERVED_4_SHIFT #undef DDR_PHY_DX1GCR0_RESERVED_4_MASK -#define DDR_PHY_DX1GCR0_RESERVED_4_DEFVAL 0x40200204 -#define DDR_PHY_DX1GCR0_RESERVED_4_SHIFT 4 -#define DDR_PHY_DX1GCR0_RESERVED_4_MASK 0x00000010U +#define DDR_PHY_DX1GCR0_RESERVED_4_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_RESERVED_4_SHIFT 4 +#define DDR_PHY_DX1GCR0_RESERVED_4_MASK 0x00000010U -/*DQSG On-Die Termination*/ +/* +* DQSG On-Die Termination +*/ #undef DDR_PHY_DX1GCR0_DQSGODT_DEFVAL #undef DDR_PHY_DX1GCR0_DQSGODT_SHIFT #undef DDR_PHY_DX1GCR0_DQSGODT_MASK -#define DDR_PHY_DX1GCR0_DQSGODT_DEFVAL 0x40200204 -#define DDR_PHY_DX1GCR0_DQSGODT_SHIFT 3 -#define DDR_PHY_DX1GCR0_DQSGODT_MASK 0x00000008U +#define DDR_PHY_DX1GCR0_DQSGODT_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_DQSGODT_SHIFT 3 +#define DDR_PHY_DX1GCR0_DQSGODT_MASK 0x00000008U -/*DQSG Output Enable*/ +/* +* DQSG Output Enable +*/ #undef DDR_PHY_DX1GCR0_DQSGOE_DEFVAL #undef DDR_PHY_DX1GCR0_DQSGOE_SHIFT #undef DDR_PHY_DX1GCR0_DQSGOE_MASK -#define DDR_PHY_DX1GCR0_DQSGOE_DEFVAL 0x40200204 -#define DDR_PHY_DX1GCR0_DQSGOE_SHIFT 2 -#define DDR_PHY_DX1GCR0_DQSGOE_MASK 0x00000004U +#define DDR_PHY_DX1GCR0_DQSGOE_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_DQSGOE_SHIFT 2 +#define DDR_PHY_DX1GCR0_DQSGOE_MASK 0x00000004U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX1GCR0_RESERVED_1_0_DEFVAL #undef DDR_PHY_DX1GCR0_RESERVED_1_0_SHIFT #undef DDR_PHY_DX1GCR0_RESERVED_1_0_MASK -#define DDR_PHY_DX1GCR0_RESERVED_1_0_DEFVAL 0x40200204 -#define DDR_PHY_DX1GCR0_RESERVED_1_0_SHIFT 0 -#define DDR_PHY_DX1GCR0_RESERVED_1_0_MASK 0x00000003U +#define DDR_PHY_DX1GCR0_RESERVED_1_0_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_RESERVED_1_0_SHIFT 0 +#define DDR_PHY_DX1GCR0_RESERVED_1_0_MASK 0x00000003U -/*Byte lane VREF IOM (Used only by D4MU IOs)*/ +/* +* Byte lane VREF IOM (Used only by D4MU IOs) +*/ #undef DDR_PHY_DX1GCR4_RESERVED_31_29_DEFVAL #undef DDR_PHY_DX1GCR4_RESERVED_31_29_SHIFT #undef DDR_PHY_DX1GCR4_RESERVED_31_29_MASK -#define DDR_PHY_DX1GCR4_RESERVED_31_29_DEFVAL 0x0E00003C -#define DDR_PHY_DX1GCR4_RESERVED_31_29_SHIFT 29 -#define DDR_PHY_DX1GCR4_RESERVED_31_29_MASK 0xE0000000U +#define DDR_PHY_DX1GCR4_RESERVED_31_29_DEFVAL 0x0E00003C +#define DDR_PHY_DX1GCR4_RESERVED_31_29_SHIFT 29 +#define DDR_PHY_DX1GCR4_RESERVED_31_29_MASK 0xE0000000U -/*Byte Lane VREF Pad Enable*/ +/* +* Byte Lane VREF Pad Enable +*/ #undef DDR_PHY_DX1GCR4_DXREFPEN_DEFVAL #undef DDR_PHY_DX1GCR4_DXREFPEN_SHIFT #undef DDR_PHY_DX1GCR4_DXREFPEN_MASK -#define DDR_PHY_DX1GCR4_DXREFPEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX1GCR4_DXREFPEN_SHIFT 28 -#define DDR_PHY_DX1GCR4_DXREFPEN_MASK 0x10000000U +#define DDR_PHY_DX1GCR4_DXREFPEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX1GCR4_DXREFPEN_SHIFT 28 +#define DDR_PHY_DX1GCR4_DXREFPEN_MASK 0x10000000U -/*Byte Lane Internal VREF Enable*/ +/* +* Byte Lane Internal VREF Enable +*/ #undef DDR_PHY_DX1GCR4_DXREFEEN_DEFVAL #undef DDR_PHY_DX1GCR4_DXREFEEN_SHIFT #undef DDR_PHY_DX1GCR4_DXREFEEN_MASK -#define DDR_PHY_DX1GCR4_DXREFEEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX1GCR4_DXREFEEN_SHIFT 26 -#define DDR_PHY_DX1GCR4_DXREFEEN_MASK 0x0C000000U +#define DDR_PHY_DX1GCR4_DXREFEEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX1GCR4_DXREFEEN_SHIFT 26 +#define DDR_PHY_DX1GCR4_DXREFEEN_MASK 0x0C000000U -/*Byte Lane Single-End VREF Enable*/ +/* +* Byte Lane Single-End VREF Enable +*/ #undef DDR_PHY_DX1GCR4_DXREFSEN_DEFVAL #undef DDR_PHY_DX1GCR4_DXREFSEN_SHIFT #undef DDR_PHY_DX1GCR4_DXREFSEN_MASK -#define DDR_PHY_DX1GCR4_DXREFSEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX1GCR4_DXREFSEN_SHIFT 25 -#define DDR_PHY_DX1GCR4_DXREFSEN_MASK 0x02000000U +#define DDR_PHY_DX1GCR4_DXREFSEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX1GCR4_DXREFSEN_SHIFT 25 +#define DDR_PHY_DX1GCR4_DXREFSEN_MASK 0x02000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX1GCR4_RESERVED_24_DEFVAL #undef DDR_PHY_DX1GCR4_RESERVED_24_SHIFT #undef DDR_PHY_DX1GCR4_RESERVED_24_MASK -#define DDR_PHY_DX1GCR4_RESERVED_24_DEFVAL 0x0E00003C -#define DDR_PHY_DX1GCR4_RESERVED_24_SHIFT 24 -#define DDR_PHY_DX1GCR4_RESERVED_24_MASK 0x01000000U +#define DDR_PHY_DX1GCR4_RESERVED_24_DEFVAL 0x0E00003C +#define DDR_PHY_DX1GCR4_RESERVED_24_SHIFT 24 +#define DDR_PHY_DX1GCR4_RESERVED_24_MASK 0x01000000U -/*External VREF generator REFSEL range select*/ +/* +* External VREF generator REFSEL range select +*/ #undef DDR_PHY_DX1GCR4_DXREFESELRANGE_DEFVAL #undef DDR_PHY_DX1GCR4_DXREFESELRANGE_SHIFT #undef DDR_PHY_DX1GCR4_DXREFESELRANGE_MASK -#define DDR_PHY_DX1GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C -#define DDR_PHY_DX1GCR4_DXREFESELRANGE_SHIFT 23 -#define DDR_PHY_DX1GCR4_DXREFESELRANGE_MASK 0x00800000U +#define DDR_PHY_DX1GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX1GCR4_DXREFESELRANGE_SHIFT 23 +#define DDR_PHY_DX1GCR4_DXREFESELRANGE_MASK 0x00800000U -/*Byte Lane External VREF Select*/ +/* +* Byte Lane External VREF Select +*/ #undef DDR_PHY_DX1GCR4_DXREFESEL_DEFVAL #undef DDR_PHY_DX1GCR4_DXREFESEL_SHIFT #undef DDR_PHY_DX1GCR4_DXREFESEL_MASK -#define DDR_PHY_DX1GCR4_DXREFESEL_DEFVAL 0x0E00003C -#define DDR_PHY_DX1GCR4_DXREFESEL_SHIFT 16 -#define DDR_PHY_DX1GCR4_DXREFESEL_MASK 0x007F0000U +#define DDR_PHY_DX1GCR4_DXREFESEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX1GCR4_DXREFESEL_SHIFT 16 +#define DDR_PHY_DX1GCR4_DXREFESEL_MASK 0x007F0000U -/*Single ended VREF generator REFSEL range select*/ +/* +* Single ended VREF generator REFSEL range select +*/ #undef DDR_PHY_DX1GCR4_DXREFSSELRANGE_DEFVAL #undef DDR_PHY_DX1GCR4_DXREFSSELRANGE_SHIFT #undef DDR_PHY_DX1GCR4_DXREFSSELRANGE_MASK -#define DDR_PHY_DX1GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C -#define DDR_PHY_DX1GCR4_DXREFSSELRANGE_SHIFT 15 -#define DDR_PHY_DX1GCR4_DXREFSSELRANGE_MASK 0x00008000U +#define DDR_PHY_DX1GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX1GCR4_DXREFSSELRANGE_SHIFT 15 +#define DDR_PHY_DX1GCR4_DXREFSSELRANGE_MASK 0x00008000U -/*Byte Lane Single-End VREF Select*/ +/* +* Byte Lane Single-End VREF Select +*/ #undef DDR_PHY_DX1GCR4_DXREFSSEL_DEFVAL #undef DDR_PHY_DX1GCR4_DXREFSSEL_SHIFT #undef DDR_PHY_DX1GCR4_DXREFSSEL_MASK -#define DDR_PHY_DX1GCR4_DXREFSSEL_DEFVAL 0x0E00003C -#define DDR_PHY_DX1GCR4_DXREFSSEL_SHIFT 8 -#define DDR_PHY_DX1GCR4_DXREFSSEL_MASK 0x00007F00U +#define DDR_PHY_DX1GCR4_DXREFSSEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX1GCR4_DXREFSSEL_SHIFT 8 +#define DDR_PHY_DX1GCR4_DXREFSSEL_MASK 0x00007F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX1GCR4_RESERVED_7_6_DEFVAL #undef DDR_PHY_DX1GCR4_RESERVED_7_6_SHIFT #undef DDR_PHY_DX1GCR4_RESERVED_7_6_MASK -#define DDR_PHY_DX1GCR4_RESERVED_7_6_DEFVAL 0x0E00003C -#define DDR_PHY_DX1GCR4_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_DX1GCR4_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_DX1GCR4_RESERVED_7_6_DEFVAL 0x0E00003C +#define DDR_PHY_DX1GCR4_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX1GCR4_RESERVED_7_6_MASK 0x000000C0U -/*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/ +/* +* VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. +*/ #undef DDR_PHY_DX1GCR4_DXREFIEN_DEFVAL #undef DDR_PHY_DX1GCR4_DXREFIEN_SHIFT #undef DDR_PHY_DX1GCR4_DXREFIEN_MASK -#define DDR_PHY_DX1GCR4_DXREFIEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX1GCR4_DXREFIEN_SHIFT 2 -#define DDR_PHY_DX1GCR4_DXREFIEN_MASK 0x0000003CU +#define DDR_PHY_DX1GCR4_DXREFIEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX1GCR4_DXREFIEN_SHIFT 2 +#define DDR_PHY_DX1GCR4_DXREFIEN_MASK 0x0000003CU -/*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/ +/* +* VRMON control for DQ IO (Single Ended) buffers of a byte lane. +*/ #undef DDR_PHY_DX1GCR4_DXREFIMON_DEFVAL #undef DDR_PHY_DX1GCR4_DXREFIMON_SHIFT #undef DDR_PHY_DX1GCR4_DXREFIMON_MASK -#define DDR_PHY_DX1GCR4_DXREFIMON_DEFVAL 0x0E00003C -#define DDR_PHY_DX1GCR4_DXREFIMON_SHIFT 0 -#define DDR_PHY_DX1GCR4_DXREFIMON_MASK 0x00000003U +#define DDR_PHY_DX1GCR4_DXREFIMON_DEFVAL 0x0E00003C +#define DDR_PHY_DX1GCR4_DXREFIMON_SHIFT 0 +#define DDR_PHY_DX1GCR4_DXREFIMON_MASK 0x00000003U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX1GCR5_RESERVED_31_DEFVAL #undef DDR_PHY_DX1GCR5_RESERVED_31_SHIFT #undef DDR_PHY_DX1GCR5_RESERVED_31_MASK -#define DDR_PHY_DX1GCR5_RESERVED_31_DEFVAL 0x09090909 -#define DDR_PHY_DX1GCR5_RESERVED_31_SHIFT 31 -#define DDR_PHY_DX1GCR5_RESERVED_31_MASK 0x80000000U +#define DDR_PHY_DX1GCR5_RESERVED_31_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR5_RESERVED_31_SHIFT 31 +#define DDR_PHY_DX1GCR5_RESERVED_31_MASK 0x80000000U -/*Byte Lane internal VREF Select for Rank 3*/ +/* +* Byte Lane internal VREF Select for Rank 3 +*/ #undef DDR_PHY_DX1GCR5_DXREFISELR3_DEFVAL #undef DDR_PHY_DX1GCR5_DXREFISELR3_SHIFT #undef DDR_PHY_DX1GCR5_DXREFISELR3_MASK -#define DDR_PHY_DX1GCR5_DXREFISELR3_DEFVAL 0x09090909 -#define DDR_PHY_DX1GCR5_DXREFISELR3_SHIFT 24 -#define DDR_PHY_DX1GCR5_DXREFISELR3_MASK 0x7F000000U +#define DDR_PHY_DX1GCR5_DXREFISELR3_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR5_DXREFISELR3_SHIFT 24 +#define DDR_PHY_DX1GCR5_DXREFISELR3_MASK 0x7F000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX1GCR5_RESERVED_23_DEFVAL #undef DDR_PHY_DX1GCR5_RESERVED_23_SHIFT #undef DDR_PHY_DX1GCR5_RESERVED_23_MASK -#define DDR_PHY_DX1GCR5_RESERVED_23_DEFVAL 0x09090909 -#define DDR_PHY_DX1GCR5_RESERVED_23_SHIFT 23 -#define DDR_PHY_DX1GCR5_RESERVED_23_MASK 0x00800000U +#define DDR_PHY_DX1GCR5_RESERVED_23_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR5_RESERVED_23_SHIFT 23 +#define DDR_PHY_DX1GCR5_RESERVED_23_MASK 0x00800000U -/*Byte Lane internal VREF Select for Rank 2*/ +/* +* Byte Lane internal VREF Select for Rank 2 +*/ #undef DDR_PHY_DX1GCR5_DXREFISELR2_DEFVAL #undef DDR_PHY_DX1GCR5_DXREFISELR2_SHIFT #undef DDR_PHY_DX1GCR5_DXREFISELR2_MASK -#define DDR_PHY_DX1GCR5_DXREFISELR2_DEFVAL 0x09090909 -#define DDR_PHY_DX1GCR5_DXREFISELR2_SHIFT 16 -#define DDR_PHY_DX1GCR5_DXREFISELR2_MASK 0x007F0000U +#define DDR_PHY_DX1GCR5_DXREFISELR2_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR5_DXREFISELR2_SHIFT 16 +#define DDR_PHY_DX1GCR5_DXREFISELR2_MASK 0x007F0000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX1GCR5_RESERVED_15_DEFVAL #undef DDR_PHY_DX1GCR5_RESERVED_15_SHIFT #undef DDR_PHY_DX1GCR5_RESERVED_15_MASK -#define DDR_PHY_DX1GCR5_RESERVED_15_DEFVAL 0x09090909 -#define DDR_PHY_DX1GCR5_RESERVED_15_SHIFT 15 -#define DDR_PHY_DX1GCR5_RESERVED_15_MASK 0x00008000U +#define DDR_PHY_DX1GCR5_RESERVED_15_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR5_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX1GCR5_RESERVED_15_MASK 0x00008000U -/*Byte Lane internal VREF Select for Rank 1*/ +/* +* Byte Lane internal VREF Select for Rank 1 +*/ #undef DDR_PHY_DX1GCR5_DXREFISELR1_DEFVAL #undef DDR_PHY_DX1GCR5_DXREFISELR1_SHIFT #undef DDR_PHY_DX1GCR5_DXREFISELR1_MASK -#define DDR_PHY_DX1GCR5_DXREFISELR1_DEFVAL 0x09090909 -#define DDR_PHY_DX1GCR5_DXREFISELR1_SHIFT 8 -#define DDR_PHY_DX1GCR5_DXREFISELR1_MASK 0x00007F00U +#define DDR_PHY_DX1GCR5_DXREFISELR1_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR5_DXREFISELR1_SHIFT 8 +#define DDR_PHY_DX1GCR5_DXREFISELR1_MASK 0x00007F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX1GCR5_RESERVED_7_DEFVAL #undef DDR_PHY_DX1GCR5_RESERVED_7_SHIFT #undef DDR_PHY_DX1GCR5_RESERVED_7_MASK -#define DDR_PHY_DX1GCR5_RESERVED_7_DEFVAL 0x09090909 -#define DDR_PHY_DX1GCR5_RESERVED_7_SHIFT 7 -#define DDR_PHY_DX1GCR5_RESERVED_7_MASK 0x00000080U +#define DDR_PHY_DX1GCR5_RESERVED_7_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR5_RESERVED_7_SHIFT 7 +#define DDR_PHY_DX1GCR5_RESERVED_7_MASK 0x00000080U -/*Byte Lane internal VREF Select for Rank 0*/ +/* +* Byte Lane internal VREF Select for Rank 0 +*/ #undef DDR_PHY_DX1GCR5_DXREFISELR0_DEFVAL #undef DDR_PHY_DX1GCR5_DXREFISELR0_SHIFT #undef DDR_PHY_DX1GCR5_DXREFISELR0_MASK -#define DDR_PHY_DX1GCR5_DXREFISELR0_DEFVAL 0x09090909 -#define DDR_PHY_DX1GCR5_DXREFISELR0_SHIFT 0 -#define DDR_PHY_DX1GCR5_DXREFISELR0_MASK 0x0000007FU +#define DDR_PHY_DX1GCR5_DXREFISELR0_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR5_DXREFISELR0_SHIFT 0 +#define DDR_PHY_DX1GCR5_DXREFISELR0_MASK 0x0000007FU -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX1GCR6_RESERVED_31_30_DEFVAL #undef DDR_PHY_DX1GCR6_RESERVED_31_30_SHIFT #undef DDR_PHY_DX1GCR6_RESERVED_31_30_MASK -#define DDR_PHY_DX1GCR6_RESERVED_31_30_DEFVAL 0x09090909 -#define DDR_PHY_DX1GCR6_RESERVED_31_30_SHIFT 30 -#define DDR_PHY_DX1GCR6_RESERVED_31_30_MASK 0xC0000000U +#define DDR_PHY_DX1GCR6_RESERVED_31_30_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR6_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX1GCR6_RESERVED_31_30_MASK 0xC0000000U -/*DRAM DQ VREF Select for Rank3*/ +/* +* DRAM DQ VREF Select for Rank3 +*/ #undef DDR_PHY_DX1GCR6_DXDQVREFR3_DEFVAL #undef DDR_PHY_DX1GCR6_DXDQVREFR3_SHIFT #undef DDR_PHY_DX1GCR6_DXDQVREFR3_MASK -#define DDR_PHY_DX1GCR6_DXDQVREFR3_DEFVAL 0x09090909 -#define DDR_PHY_DX1GCR6_DXDQVREFR3_SHIFT 24 -#define DDR_PHY_DX1GCR6_DXDQVREFR3_MASK 0x3F000000U +#define DDR_PHY_DX1GCR6_DXDQVREFR3_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR6_DXDQVREFR3_SHIFT 24 +#define DDR_PHY_DX1GCR6_DXDQVREFR3_MASK 0x3F000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX1GCR6_RESERVED_23_22_DEFVAL #undef DDR_PHY_DX1GCR6_RESERVED_23_22_SHIFT #undef DDR_PHY_DX1GCR6_RESERVED_23_22_MASK -#define DDR_PHY_DX1GCR6_RESERVED_23_22_DEFVAL 0x09090909 -#define DDR_PHY_DX1GCR6_RESERVED_23_22_SHIFT 22 -#define DDR_PHY_DX1GCR6_RESERVED_23_22_MASK 0x00C00000U +#define DDR_PHY_DX1GCR6_RESERVED_23_22_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR6_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX1GCR6_RESERVED_23_22_MASK 0x00C00000U -/*DRAM DQ VREF Select for Rank2*/ +/* +* DRAM DQ VREF Select for Rank2 +*/ #undef DDR_PHY_DX1GCR6_DXDQVREFR2_DEFVAL #undef DDR_PHY_DX1GCR6_DXDQVREFR2_SHIFT #undef DDR_PHY_DX1GCR6_DXDQVREFR2_MASK -#define DDR_PHY_DX1GCR6_DXDQVREFR2_DEFVAL 0x09090909 -#define DDR_PHY_DX1GCR6_DXDQVREFR2_SHIFT 16 -#define DDR_PHY_DX1GCR6_DXDQVREFR2_MASK 0x003F0000U +#define DDR_PHY_DX1GCR6_DXDQVREFR2_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR6_DXDQVREFR2_SHIFT 16 +#define DDR_PHY_DX1GCR6_DXDQVREFR2_MASK 0x003F0000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX1GCR6_RESERVED_15_14_DEFVAL #undef DDR_PHY_DX1GCR6_RESERVED_15_14_SHIFT #undef DDR_PHY_DX1GCR6_RESERVED_15_14_MASK -#define DDR_PHY_DX1GCR6_RESERVED_15_14_DEFVAL 0x09090909 -#define DDR_PHY_DX1GCR6_RESERVED_15_14_SHIFT 14 -#define DDR_PHY_DX1GCR6_RESERVED_15_14_MASK 0x0000C000U +#define DDR_PHY_DX1GCR6_RESERVED_15_14_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR6_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_DX1GCR6_RESERVED_15_14_MASK 0x0000C000U -/*DRAM DQ VREF Select for Rank1*/ +/* +* DRAM DQ VREF Select for Rank1 +*/ #undef DDR_PHY_DX1GCR6_DXDQVREFR1_DEFVAL #undef DDR_PHY_DX1GCR6_DXDQVREFR1_SHIFT #undef DDR_PHY_DX1GCR6_DXDQVREFR1_MASK -#define DDR_PHY_DX1GCR6_DXDQVREFR1_DEFVAL 0x09090909 -#define DDR_PHY_DX1GCR6_DXDQVREFR1_SHIFT 8 -#define DDR_PHY_DX1GCR6_DXDQVREFR1_MASK 0x00003F00U +#define DDR_PHY_DX1GCR6_DXDQVREFR1_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR6_DXDQVREFR1_SHIFT 8 +#define DDR_PHY_DX1GCR6_DXDQVREFR1_MASK 0x00003F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX1GCR6_RESERVED_7_6_DEFVAL #undef DDR_PHY_DX1GCR6_RESERVED_7_6_SHIFT #undef DDR_PHY_DX1GCR6_RESERVED_7_6_MASK -#define DDR_PHY_DX1GCR6_RESERVED_7_6_DEFVAL 0x09090909 -#define DDR_PHY_DX1GCR6_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_DX1GCR6_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_DX1GCR6_RESERVED_7_6_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR6_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX1GCR6_RESERVED_7_6_MASK 0x000000C0U -/*DRAM DQ VREF Select for Rank0*/ +/* +* DRAM DQ VREF Select for Rank0 +*/ #undef DDR_PHY_DX1GCR6_DXDQVREFR0_DEFVAL #undef DDR_PHY_DX1GCR6_DXDQVREFR0_SHIFT #undef DDR_PHY_DX1GCR6_DXDQVREFR0_MASK -#define DDR_PHY_DX1GCR6_DXDQVREFR0_DEFVAL 0x09090909 -#define DDR_PHY_DX1GCR6_DXDQVREFR0_SHIFT 0 -#define DDR_PHY_DX1GCR6_DXDQVREFR0_MASK 0x0000003FU +#define DDR_PHY_DX1GCR6_DXDQVREFR0_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR6_DXDQVREFR0_SHIFT 0 +#define DDR_PHY_DX1GCR6_DXDQVREFR0_MASK 0x0000003FU -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX1LCDLR2_RESERVED_31_25_DEFVAL -#undef DDR_PHY_DX1LCDLR2_RESERVED_31_25_SHIFT -#undef DDR_PHY_DX1LCDLR2_RESERVED_31_25_MASK -#define DDR_PHY_DX1LCDLR2_RESERVED_31_25_DEFVAL 0x00000000 -#define DDR_PHY_DX1LCDLR2_RESERVED_31_25_SHIFT 25 -#define DDR_PHY_DX1LCDLR2_RESERVED_31_25_MASK 0xFE000000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX1LCDLR2_RESERVED_24_16_DEFVAL -#undef DDR_PHY_DX1LCDLR2_RESERVED_24_16_SHIFT -#undef DDR_PHY_DX1LCDLR2_RESERVED_24_16_MASK -#define DDR_PHY_DX1LCDLR2_RESERVED_24_16_DEFVAL 0x00000000 -#define DDR_PHY_DX1LCDLR2_RESERVED_24_16_SHIFT 16 -#define DDR_PHY_DX1LCDLR2_RESERVED_24_16_MASK 0x01FF0000U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX1LCDLR2_RESERVED_15_9_DEFVAL -#undef DDR_PHY_DX1LCDLR2_RESERVED_15_9_SHIFT -#undef DDR_PHY_DX1LCDLR2_RESERVED_15_9_MASK -#define DDR_PHY_DX1LCDLR2_RESERVED_15_9_DEFVAL 0x00000000 -#define DDR_PHY_DX1LCDLR2_RESERVED_15_9_SHIFT 9 -#define DDR_PHY_DX1LCDLR2_RESERVED_15_9_MASK 0x0000FE00U - -/*Read DQS Gating Delay*/ -#undef DDR_PHY_DX1LCDLR2_DQSGD_DEFVAL -#undef DDR_PHY_DX1LCDLR2_DQSGD_SHIFT -#undef DDR_PHY_DX1LCDLR2_DQSGD_MASK -#define DDR_PHY_DX1LCDLR2_DQSGD_DEFVAL 0x00000000 -#define DDR_PHY_DX1LCDLR2_DQSGD_SHIFT 0 -#define DDR_PHY_DX1LCDLR2_DQSGD_MASK 0x000001FFU - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX1GTR0_RESERVED_31_24_DEFVAL -#undef DDR_PHY_DX1GTR0_RESERVED_31_24_SHIFT -#undef DDR_PHY_DX1GTR0_RESERVED_31_24_MASK -#define DDR_PHY_DX1GTR0_RESERVED_31_24_DEFVAL 0x00020000 -#define DDR_PHY_DX1GTR0_RESERVED_31_24_SHIFT 27 -#define DDR_PHY_DX1GTR0_RESERVED_31_24_MASK 0xF8000000U - -/*DQ Write Path Latency Pipeline*/ -#undef DDR_PHY_DX1GTR0_WDQSL_DEFVAL -#undef DDR_PHY_DX1GTR0_WDQSL_SHIFT -#undef DDR_PHY_DX1GTR0_WDQSL_MASK -#define DDR_PHY_DX1GTR0_WDQSL_DEFVAL 0x00020000 -#define DDR_PHY_DX1GTR0_WDQSL_SHIFT 24 -#define DDR_PHY_DX1GTR0_WDQSL_MASK 0x07000000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX1GTR0_RESERVED_23_20_DEFVAL -#undef DDR_PHY_DX1GTR0_RESERVED_23_20_SHIFT -#undef DDR_PHY_DX1GTR0_RESERVED_23_20_MASK -#define DDR_PHY_DX1GTR0_RESERVED_23_20_DEFVAL 0x00020000 -#define DDR_PHY_DX1GTR0_RESERVED_23_20_SHIFT 20 -#define DDR_PHY_DX1GTR0_RESERVED_23_20_MASK 0x00F00000U - -/*Write Leveling System Latency*/ -#undef DDR_PHY_DX1GTR0_WLSL_DEFVAL -#undef DDR_PHY_DX1GTR0_WLSL_SHIFT -#undef DDR_PHY_DX1GTR0_WLSL_MASK -#define DDR_PHY_DX1GTR0_WLSL_DEFVAL 0x00020000 -#define DDR_PHY_DX1GTR0_WLSL_SHIFT 16 -#define DDR_PHY_DX1GTR0_WLSL_MASK 0x000F0000U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX1GTR0_RESERVED_15_13_DEFVAL -#undef DDR_PHY_DX1GTR0_RESERVED_15_13_SHIFT -#undef DDR_PHY_DX1GTR0_RESERVED_15_13_MASK -#define DDR_PHY_DX1GTR0_RESERVED_15_13_DEFVAL 0x00020000 -#define DDR_PHY_DX1GTR0_RESERVED_15_13_SHIFT 13 -#define DDR_PHY_DX1GTR0_RESERVED_15_13_MASK 0x0000E000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX1GTR0_RESERVED_12_8_DEFVAL -#undef DDR_PHY_DX1GTR0_RESERVED_12_8_SHIFT -#undef DDR_PHY_DX1GTR0_RESERVED_12_8_MASK -#define DDR_PHY_DX1GTR0_RESERVED_12_8_DEFVAL 0x00020000 -#define DDR_PHY_DX1GTR0_RESERVED_12_8_SHIFT 8 -#define DDR_PHY_DX1GTR0_RESERVED_12_8_MASK 0x00001F00U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX1GTR0_RESERVED_7_5_DEFVAL -#undef DDR_PHY_DX1GTR0_RESERVED_7_5_SHIFT -#undef DDR_PHY_DX1GTR0_RESERVED_7_5_MASK -#define DDR_PHY_DX1GTR0_RESERVED_7_5_DEFVAL 0x00020000 -#define DDR_PHY_DX1GTR0_RESERVED_7_5_SHIFT 5 -#define DDR_PHY_DX1GTR0_RESERVED_7_5_MASK 0x000000E0U - -/*DQS Gating System Latency*/ -#undef DDR_PHY_DX1GTR0_DGSL_DEFVAL -#undef DDR_PHY_DX1GTR0_DGSL_SHIFT -#undef DDR_PHY_DX1GTR0_DGSL_MASK -#define DDR_PHY_DX1GTR0_DGSL_DEFVAL 0x00020000 -#define DDR_PHY_DX1GTR0_DGSL_SHIFT 0 -#define DDR_PHY_DX1GTR0_DGSL_MASK 0x0000001FU - -/*Calibration Bypass*/ +/* +* Calibration Bypass +*/ #undef DDR_PHY_DX2GCR0_CALBYP_DEFVAL #undef DDR_PHY_DX2GCR0_CALBYP_SHIFT #undef DDR_PHY_DX2GCR0_CALBYP_MASK -#define DDR_PHY_DX2GCR0_CALBYP_DEFVAL 0x40200204 -#define DDR_PHY_DX2GCR0_CALBYP_SHIFT 31 -#define DDR_PHY_DX2GCR0_CALBYP_MASK 0x80000000U +#define DDR_PHY_DX2GCR0_CALBYP_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_CALBYP_SHIFT 31 +#define DDR_PHY_DX2GCR0_CALBYP_MASK 0x80000000U -/*Master Delay Line Enable*/ +/* +* Master Delay Line Enable +*/ #undef DDR_PHY_DX2GCR0_MDLEN_DEFVAL #undef DDR_PHY_DX2GCR0_MDLEN_SHIFT #undef DDR_PHY_DX2GCR0_MDLEN_MASK -#define DDR_PHY_DX2GCR0_MDLEN_DEFVAL 0x40200204 -#define DDR_PHY_DX2GCR0_MDLEN_SHIFT 30 -#define DDR_PHY_DX2GCR0_MDLEN_MASK 0x40000000U +#define DDR_PHY_DX2GCR0_MDLEN_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_MDLEN_SHIFT 30 +#define DDR_PHY_DX2GCR0_MDLEN_MASK 0x40000000U -/*Configurable ODT(TE) Phase Shift*/ +/* +* Configurable ODT(TE) Phase Shift +*/ #undef DDR_PHY_DX2GCR0_CODTSHFT_DEFVAL #undef DDR_PHY_DX2GCR0_CODTSHFT_SHIFT #undef DDR_PHY_DX2GCR0_CODTSHFT_MASK -#define DDR_PHY_DX2GCR0_CODTSHFT_DEFVAL 0x40200204 -#define DDR_PHY_DX2GCR0_CODTSHFT_SHIFT 28 -#define DDR_PHY_DX2GCR0_CODTSHFT_MASK 0x30000000U +#define DDR_PHY_DX2GCR0_CODTSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_CODTSHFT_SHIFT 28 +#define DDR_PHY_DX2GCR0_CODTSHFT_MASK 0x30000000U -/*DQS Duty Cycle Correction*/ +/* +* DQS Duty Cycle Correction +*/ #undef DDR_PHY_DX2GCR0_DQSDCC_DEFVAL #undef DDR_PHY_DX2GCR0_DQSDCC_SHIFT #undef DDR_PHY_DX2GCR0_DQSDCC_MASK -#define DDR_PHY_DX2GCR0_DQSDCC_DEFVAL 0x40200204 -#define DDR_PHY_DX2GCR0_DQSDCC_SHIFT 24 -#define DDR_PHY_DX2GCR0_DQSDCC_MASK 0x0F000000U +#define DDR_PHY_DX2GCR0_DQSDCC_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_DQSDCC_SHIFT 24 +#define DDR_PHY_DX2GCR0_DQSDCC_MASK 0x0F000000U -/*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/ +/* +* Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY +*/ #undef DDR_PHY_DX2GCR0_RDDLY_DEFVAL #undef DDR_PHY_DX2GCR0_RDDLY_SHIFT #undef DDR_PHY_DX2GCR0_RDDLY_MASK -#define DDR_PHY_DX2GCR0_RDDLY_DEFVAL 0x40200204 -#define DDR_PHY_DX2GCR0_RDDLY_SHIFT 20 -#define DDR_PHY_DX2GCR0_RDDLY_MASK 0x00F00000U +#define DDR_PHY_DX2GCR0_RDDLY_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_RDDLY_SHIFT 20 +#define DDR_PHY_DX2GCR0_RDDLY_MASK 0x00F00000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX2GCR0_RESERVED_19_14_DEFVAL #undef DDR_PHY_DX2GCR0_RESERVED_19_14_SHIFT #undef DDR_PHY_DX2GCR0_RESERVED_19_14_MASK -#define DDR_PHY_DX2GCR0_RESERVED_19_14_DEFVAL 0x40200204 -#define DDR_PHY_DX2GCR0_RESERVED_19_14_SHIFT 14 -#define DDR_PHY_DX2GCR0_RESERVED_19_14_MASK 0x000FC000U +#define DDR_PHY_DX2GCR0_RESERVED_19_14_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_RESERVED_19_14_SHIFT 14 +#define DDR_PHY_DX2GCR0_RESERVED_19_14_MASK 0x000FC000U -/*DQSNSE Power Down Receiver*/ +/* +* DQSNSE Power Down Receiver +*/ #undef DDR_PHY_DX2GCR0_DQSNSEPDR_DEFVAL #undef DDR_PHY_DX2GCR0_DQSNSEPDR_SHIFT #undef DDR_PHY_DX2GCR0_DQSNSEPDR_MASK -#define DDR_PHY_DX2GCR0_DQSNSEPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX2GCR0_DQSNSEPDR_SHIFT 13 -#define DDR_PHY_DX2GCR0_DQSNSEPDR_MASK 0x00002000U +#define DDR_PHY_DX2GCR0_DQSNSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_DQSNSEPDR_SHIFT 13 +#define DDR_PHY_DX2GCR0_DQSNSEPDR_MASK 0x00002000U -/*DQSSE Power Down Receiver*/ +/* +* DQSSE Power Down Receiver +*/ #undef DDR_PHY_DX2GCR0_DQSSEPDR_DEFVAL #undef DDR_PHY_DX2GCR0_DQSSEPDR_SHIFT #undef DDR_PHY_DX2GCR0_DQSSEPDR_MASK -#define DDR_PHY_DX2GCR0_DQSSEPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX2GCR0_DQSSEPDR_SHIFT 12 -#define DDR_PHY_DX2GCR0_DQSSEPDR_MASK 0x00001000U +#define DDR_PHY_DX2GCR0_DQSSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_DQSSEPDR_SHIFT 12 +#define DDR_PHY_DX2GCR0_DQSSEPDR_MASK 0x00001000U -/*RTT On Additive Latency*/ +/* +* RTT On Additive Latency +*/ #undef DDR_PHY_DX2GCR0_RTTOAL_DEFVAL #undef DDR_PHY_DX2GCR0_RTTOAL_SHIFT #undef DDR_PHY_DX2GCR0_RTTOAL_MASK -#define DDR_PHY_DX2GCR0_RTTOAL_DEFVAL 0x40200204 -#define DDR_PHY_DX2GCR0_RTTOAL_SHIFT 11 -#define DDR_PHY_DX2GCR0_RTTOAL_MASK 0x00000800U +#define DDR_PHY_DX2GCR0_RTTOAL_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_RTTOAL_SHIFT 11 +#define DDR_PHY_DX2GCR0_RTTOAL_MASK 0x00000800U -/*RTT Output Hold*/ +/* +* RTT Output Hold +*/ #undef DDR_PHY_DX2GCR0_RTTOH_DEFVAL #undef DDR_PHY_DX2GCR0_RTTOH_SHIFT #undef DDR_PHY_DX2GCR0_RTTOH_MASK -#define DDR_PHY_DX2GCR0_RTTOH_DEFVAL 0x40200204 -#define DDR_PHY_DX2GCR0_RTTOH_SHIFT 9 -#define DDR_PHY_DX2GCR0_RTTOH_MASK 0x00000600U +#define DDR_PHY_DX2GCR0_RTTOH_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_RTTOH_SHIFT 9 +#define DDR_PHY_DX2GCR0_RTTOH_MASK 0x00000600U -/*Configurable PDR Phase Shift*/ +/* +* Configurable PDR Phase Shift +*/ #undef DDR_PHY_DX2GCR0_CPDRSHFT_DEFVAL #undef DDR_PHY_DX2GCR0_CPDRSHFT_SHIFT #undef DDR_PHY_DX2GCR0_CPDRSHFT_MASK -#define DDR_PHY_DX2GCR0_CPDRSHFT_DEFVAL 0x40200204 -#define DDR_PHY_DX2GCR0_CPDRSHFT_SHIFT 7 -#define DDR_PHY_DX2GCR0_CPDRSHFT_MASK 0x00000180U +#define DDR_PHY_DX2GCR0_CPDRSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_CPDRSHFT_SHIFT 7 +#define DDR_PHY_DX2GCR0_CPDRSHFT_MASK 0x00000180U -/*DQSR Power Down*/ +/* +* DQSR Power Down +*/ #undef DDR_PHY_DX2GCR0_DQSRPD_DEFVAL #undef DDR_PHY_DX2GCR0_DQSRPD_SHIFT #undef DDR_PHY_DX2GCR0_DQSRPD_MASK -#define DDR_PHY_DX2GCR0_DQSRPD_DEFVAL 0x40200204 -#define DDR_PHY_DX2GCR0_DQSRPD_SHIFT 6 -#define DDR_PHY_DX2GCR0_DQSRPD_MASK 0x00000040U +#define DDR_PHY_DX2GCR0_DQSRPD_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_DQSRPD_SHIFT 6 +#define DDR_PHY_DX2GCR0_DQSRPD_MASK 0x00000040U -/*DQSG Power Down Receiver*/ +/* +* DQSG Power Down Receiver +*/ #undef DDR_PHY_DX2GCR0_DQSGPDR_DEFVAL #undef DDR_PHY_DX2GCR0_DQSGPDR_SHIFT #undef DDR_PHY_DX2GCR0_DQSGPDR_MASK -#define DDR_PHY_DX2GCR0_DQSGPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX2GCR0_DQSGPDR_SHIFT 5 -#define DDR_PHY_DX2GCR0_DQSGPDR_MASK 0x00000020U +#define DDR_PHY_DX2GCR0_DQSGPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_DQSGPDR_SHIFT 5 +#define DDR_PHY_DX2GCR0_DQSGPDR_MASK 0x00000020U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX2GCR0_RESERVED_4_DEFVAL #undef DDR_PHY_DX2GCR0_RESERVED_4_SHIFT #undef DDR_PHY_DX2GCR0_RESERVED_4_MASK -#define DDR_PHY_DX2GCR0_RESERVED_4_DEFVAL 0x40200204 -#define DDR_PHY_DX2GCR0_RESERVED_4_SHIFT 4 -#define DDR_PHY_DX2GCR0_RESERVED_4_MASK 0x00000010U +#define DDR_PHY_DX2GCR0_RESERVED_4_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_RESERVED_4_SHIFT 4 +#define DDR_PHY_DX2GCR0_RESERVED_4_MASK 0x00000010U -/*DQSG On-Die Termination*/ +/* +* DQSG On-Die Termination +*/ #undef DDR_PHY_DX2GCR0_DQSGODT_DEFVAL #undef DDR_PHY_DX2GCR0_DQSGODT_SHIFT #undef DDR_PHY_DX2GCR0_DQSGODT_MASK -#define DDR_PHY_DX2GCR0_DQSGODT_DEFVAL 0x40200204 -#define DDR_PHY_DX2GCR0_DQSGODT_SHIFT 3 -#define DDR_PHY_DX2GCR0_DQSGODT_MASK 0x00000008U +#define DDR_PHY_DX2GCR0_DQSGODT_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_DQSGODT_SHIFT 3 +#define DDR_PHY_DX2GCR0_DQSGODT_MASK 0x00000008U -/*DQSG Output Enable*/ +/* +* DQSG Output Enable +*/ #undef DDR_PHY_DX2GCR0_DQSGOE_DEFVAL #undef DDR_PHY_DX2GCR0_DQSGOE_SHIFT #undef DDR_PHY_DX2GCR0_DQSGOE_MASK -#define DDR_PHY_DX2GCR0_DQSGOE_DEFVAL 0x40200204 -#define DDR_PHY_DX2GCR0_DQSGOE_SHIFT 2 -#define DDR_PHY_DX2GCR0_DQSGOE_MASK 0x00000004U +#define DDR_PHY_DX2GCR0_DQSGOE_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_DQSGOE_SHIFT 2 +#define DDR_PHY_DX2GCR0_DQSGOE_MASK 0x00000004U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX2GCR0_RESERVED_1_0_DEFVAL #undef DDR_PHY_DX2GCR0_RESERVED_1_0_SHIFT #undef DDR_PHY_DX2GCR0_RESERVED_1_0_MASK -#define DDR_PHY_DX2GCR0_RESERVED_1_0_DEFVAL 0x40200204 -#define DDR_PHY_DX2GCR0_RESERVED_1_0_SHIFT 0 -#define DDR_PHY_DX2GCR0_RESERVED_1_0_MASK 0x00000003U +#define DDR_PHY_DX2GCR0_RESERVED_1_0_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_RESERVED_1_0_SHIFT 0 +#define DDR_PHY_DX2GCR0_RESERVED_1_0_MASK 0x00000003U -/*Enables the PDR mode for DQ[7:0]*/ +/* +* Enables the PDR mode for DQ[7:0] +*/ #undef DDR_PHY_DX2GCR1_DXPDRMODE_DEFVAL #undef DDR_PHY_DX2GCR1_DXPDRMODE_SHIFT #undef DDR_PHY_DX2GCR1_DXPDRMODE_MASK -#define DDR_PHY_DX2GCR1_DXPDRMODE_DEFVAL 0x00007FFF -#define DDR_PHY_DX2GCR1_DXPDRMODE_SHIFT 16 -#define DDR_PHY_DX2GCR1_DXPDRMODE_MASK 0xFFFF0000U +#define DDR_PHY_DX2GCR1_DXPDRMODE_DEFVAL 0x00007FFF +#define DDR_PHY_DX2GCR1_DXPDRMODE_SHIFT 16 +#define DDR_PHY_DX2GCR1_DXPDRMODE_MASK 0xFFFF0000U -/*Reserved. Returns zeroes on reads.*/ +/* +* Reserved. Returns zeroes on reads. +*/ #undef DDR_PHY_DX2GCR1_RESERVED_15_DEFVAL #undef DDR_PHY_DX2GCR1_RESERVED_15_SHIFT #undef DDR_PHY_DX2GCR1_RESERVED_15_MASK -#define DDR_PHY_DX2GCR1_RESERVED_15_DEFVAL 0x00007FFF -#define DDR_PHY_DX2GCR1_RESERVED_15_SHIFT 15 -#define DDR_PHY_DX2GCR1_RESERVED_15_MASK 0x00008000U +#define DDR_PHY_DX2GCR1_RESERVED_15_DEFVAL 0x00007FFF +#define DDR_PHY_DX2GCR1_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX2GCR1_RESERVED_15_MASK 0x00008000U -/*Select the delayed or non-delayed read data strobe #*/ +/* +* Select the delayed or non-delayed read data strobe # +*/ #undef DDR_PHY_DX2GCR1_QSNSEL_DEFVAL #undef DDR_PHY_DX2GCR1_QSNSEL_SHIFT #undef DDR_PHY_DX2GCR1_QSNSEL_MASK -#define DDR_PHY_DX2GCR1_QSNSEL_DEFVAL 0x00007FFF -#define DDR_PHY_DX2GCR1_QSNSEL_SHIFT 14 -#define DDR_PHY_DX2GCR1_QSNSEL_MASK 0x00004000U +#define DDR_PHY_DX2GCR1_QSNSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX2GCR1_QSNSEL_SHIFT 14 +#define DDR_PHY_DX2GCR1_QSNSEL_MASK 0x00004000U -/*Select the delayed or non-delayed read data strobe*/ +/* +* Select the delayed or non-delayed read data strobe +*/ #undef DDR_PHY_DX2GCR1_QSSEL_DEFVAL #undef DDR_PHY_DX2GCR1_QSSEL_SHIFT #undef DDR_PHY_DX2GCR1_QSSEL_MASK -#define DDR_PHY_DX2GCR1_QSSEL_DEFVAL 0x00007FFF -#define DDR_PHY_DX2GCR1_QSSEL_SHIFT 13 -#define DDR_PHY_DX2GCR1_QSSEL_MASK 0x00002000U +#define DDR_PHY_DX2GCR1_QSSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX2GCR1_QSSEL_SHIFT 13 +#define DDR_PHY_DX2GCR1_QSSEL_MASK 0x00002000U -/*Enables Read Data Strobe in a byte lane*/ +/* +* Enables Read Data Strobe in a byte lane +*/ #undef DDR_PHY_DX2GCR1_OEEN_DEFVAL #undef DDR_PHY_DX2GCR1_OEEN_SHIFT #undef DDR_PHY_DX2GCR1_OEEN_MASK -#define DDR_PHY_DX2GCR1_OEEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX2GCR1_OEEN_SHIFT 12 -#define DDR_PHY_DX2GCR1_OEEN_MASK 0x00001000U +#define DDR_PHY_DX2GCR1_OEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX2GCR1_OEEN_SHIFT 12 +#define DDR_PHY_DX2GCR1_OEEN_MASK 0x00001000U -/*Enables PDR in a byte lane*/ +/* +* Enables PDR in a byte lane +*/ #undef DDR_PHY_DX2GCR1_PDREN_DEFVAL #undef DDR_PHY_DX2GCR1_PDREN_SHIFT #undef DDR_PHY_DX2GCR1_PDREN_MASK -#define DDR_PHY_DX2GCR1_PDREN_DEFVAL 0x00007FFF -#define DDR_PHY_DX2GCR1_PDREN_SHIFT 11 -#define DDR_PHY_DX2GCR1_PDREN_MASK 0x00000800U +#define DDR_PHY_DX2GCR1_PDREN_DEFVAL 0x00007FFF +#define DDR_PHY_DX2GCR1_PDREN_SHIFT 11 +#define DDR_PHY_DX2GCR1_PDREN_MASK 0x00000800U -/*Enables ODT/TE in a byte lane*/ +/* +* Enables ODT/TE in a byte lane +*/ #undef DDR_PHY_DX2GCR1_TEEN_DEFVAL #undef DDR_PHY_DX2GCR1_TEEN_SHIFT #undef DDR_PHY_DX2GCR1_TEEN_MASK -#define DDR_PHY_DX2GCR1_TEEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX2GCR1_TEEN_SHIFT 10 -#define DDR_PHY_DX2GCR1_TEEN_MASK 0x00000400U +#define DDR_PHY_DX2GCR1_TEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX2GCR1_TEEN_SHIFT 10 +#define DDR_PHY_DX2GCR1_TEEN_MASK 0x00000400U -/*Enables Write Data strobe in a byte lane*/ +/* +* Enables Write Data strobe in a byte lane +*/ #undef DDR_PHY_DX2GCR1_DSEN_DEFVAL #undef DDR_PHY_DX2GCR1_DSEN_SHIFT #undef DDR_PHY_DX2GCR1_DSEN_MASK -#define DDR_PHY_DX2GCR1_DSEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX2GCR1_DSEN_SHIFT 9 -#define DDR_PHY_DX2GCR1_DSEN_MASK 0x00000200U +#define DDR_PHY_DX2GCR1_DSEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX2GCR1_DSEN_SHIFT 9 +#define DDR_PHY_DX2GCR1_DSEN_MASK 0x00000200U -/*Enables DM pin in a byte lane*/ +/* +* Enables DM pin in a byte lane +*/ #undef DDR_PHY_DX2GCR1_DMEN_DEFVAL #undef DDR_PHY_DX2GCR1_DMEN_SHIFT #undef DDR_PHY_DX2GCR1_DMEN_MASK -#define DDR_PHY_DX2GCR1_DMEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX2GCR1_DMEN_SHIFT 8 -#define DDR_PHY_DX2GCR1_DMEN_MASK 0x00000100U +#define DDR_PHY_DX2GCR1_DMEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX2GCR1_DMEN_SHIFT 8 +#define DDR_PHY_DX2GCR1_DMEN_MASK 0x00000100U -/*Enables DQ corresponding to each bit in a byte*/ +/* +* Enables DQ corresponding to each bit in a byte +*/ #undef DDR_PHY_DX2GCR1_DQEN_DEFVAL #undef DDR_PHY_DX2GCR1_DQEN_SHIFT #undef DDR_PHY_DX2GCR1_DQEN_MASK -#define DDR_PHY_DX2GCR1_DQEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX2GCR1_DQEN_SHIFT 0 -#define DDR_PHY_DX2GCR1_DQEN_MASK 0x000000FFU +#define DDR_PHY_DX2GCR1_DQEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX2GCR1_DQEN_SHIFT 0 +#define DDR_PHY_DX2GCR1_DQEN_MASK 0x000000FFU -/*Byte lane VREF IOM (Used only by D4MU IOs)*/ +/* +* Byte lane VREF IOM (Used only by D4MU IOs) +*/ #undef DDR_PHY_DX2GCR4_RESERVED_31_29_DEFVAL #undef DDR_PHY_DX2GCR4_RESERVED_31_29_SHIFT #undef DDR_PHY_DX2GCR4_RESERVED_31_29_MASK -#define DDR_PHY_DX2GCR4_RESERVED_31_29_DEFVAL 0x0E00003C -#define DDR_PHY_DX2GCR4_RESERVED_31_29_SHIFT 29 -#define DDR_PHY_DX2GCR4_RESERVED_31_29_MASK 0xE0000000U +#define DDR_PHY_DX2GCR4_RESERVED_31_29_DEFVAL 0x0E00003C +#define DDR_PHY_DX2GCR4_RESERVED_31_29_SHIFT 29 +#define DDR_PHY_DX2GCR4_RESERVED_31_29_MASK 0xE0000000U -/*Byte Lane VREF Pad Enable*/ +/* +* Byte Lane VREF Pad Enable +*/ #undef DDR_PHY_DX2GCR4_DXREFPEN_DEFVAL #undef DDR_PHY_DX2GCR4_DXREFPEN_SHIFT #undef DDR_PHY_DX2GCR4_DXREFPEN_MASK -#define DDR_PHY_DX2GCR4_DXREFPEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX2GCR4_DXREFPEN_SHIFT 28 -#define DDR_PHY_DX2GCR4_DXREFPEN_MASK 0x10000000U +#define DDR_PHY_DX2GCR4_DXREFPEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX2GCR4_DXREFPEN_SHIFT 28 +#define DDR_PHY_DX2GCR4_DXREFPEN_MASK 0x10000000U -/*Byte Lane Internal VREF Enable*/ +/* +* Byte Lane Internal VREF Enable +*/ #undef DDR_PHY_DX2GCR4_DXREFEEN_DEFVAL #undef DDR_PHY_DX2GCR4_DXREFEEN_SHIFT #undef DDR_PHY_DX2GCR4_DXREFEEN_MASK -#define DDR_PHY_DX2GCR4_DXREFEEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX2GCR4_DXREFEEN_SHIFT 26 -#define DDR_PHY_DX2GCR4_DXREFEEN_MASK 0x0C000000U +#define DDR_PHY_DX2GCR4_DXREFEEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX2GCR4_DXREFEEN_SHIFT 26 +#define DDR_PHY_DX2GCR4_DXREFEEN_MASK 0x0C000000U -/*Byte Lane Single-End VREF Enable*/ +/* +* Byte Lane Single-End VREF Enable +*/ #undef DDR_PHY_DX2GCR4_DXREFSEN_DEFVAL #undef DDR_PHY_DX2GCR4_DXREFSEN_SHIFT #undef DDR_PHY_DX2GCR4_DXREFSEN_MASK -#define DDR_PHY_DX2GCR4_DXREFSEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX2GCR4_DXREFSEN_SHIFT 25 -#define DDR_PHY_DX2GCR4_DXREFSEN_MASK 0x02000000U +#define DDR_PHY_DX2GCR4_DXREFSEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX2GCR4_DXREFSEN_SHIFT 25 +#define DDR_PHY_DX2GCR4_DXREFSEN_MASK 0x02000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX2GCR4_RESERVED_24_DEFVAL #undef DDR_PHY_DX2GCR4_RESERVED_24_SHIFT #undef DDR_PHY_DX2GCR4_RESERVED_24_MASK -#define DDR_PHY_DX2GCR4_RESERVED_24_DEFVAL 0x0E00003C -#define DDR_PHY_DX2GCR4_RESERVED_24_SHIFT 24 -#define DDR_PHY_DX2GCR4_RESERVED_24_MASK 0x01000000U +#define DDR_PHY_DX2GCR4_RESERVED_24_DEFVAL 0x0E00003C +#define DDR_PHY_DX2GCR4_RESERVED_24_SHIFT 24 +#define DDR_PHY_DX2GCR4_RESERVED_24_MASK 0x01000000U -/*External VREF generator REFSEL range select*/ +/* +* External VREF generator REFSEL range select +*/ #undef DDR_PHY_DX2GCR4_DXREFESELRANGE_DEFVAL #undef DDR_PHY_DX2GCR4_DXREFESELRANGE_SHIFT #undef DDR_PHY_DX2GCR4_DXREFESELRANGE_MASK -#define DDR_PHY_DX2GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C -#define DDR_PHY_DX2GCR4_DXREFESELRANGE_SHIFT 23 -#define DDR_PHY_DX2GCR4_DXREFESELRANGE_MASK 0x00800000U +#define DDR_PHY_DX2GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX2GCR4_DXREFESELRANGE_SHIFT 23 +#define DDR_PHY_DX2GCR4_DXREFESELRANGE_MASK 0x00800000U -/*Byte Lane External VREF Select*/ +/* +* Byte Lane External VREF Select +*/ #undef DDR_PHY_DX2GCR4_DXREFESEL_DEFVAL #undef DDR_PHY_DX2GCR4_DXREFESEL_SHIFT #undef DDR_PHY_DX2GCR4_DXREFESEL_MASK -#define DDR_PHY_DX2GCR4_DXREFESEL_DEFVAL 0x0E00003C -#define DDR_PHY_DX2GCR4_DXREFESEL_SHIFT 16 -#define DDR_PHY_DX2GCR4_DXREFESEL_MASK 0x007F0000U +#define DDR_PHY_DX2GCR4_DXREFESEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX2GCR4_DXREFESEL_SHIFT 16 +#define DDR_PHY_DX2GCR4_DXREFESEL_MASK 0x007F0000U -/*Single ended VREF generator REFSEL range select*/ +/* +* Single ended VREF generator REFSEL range select +*/ #undef DDR_PHY_DX2GCR4_DXREFSSELRANGE_DEFVAL #undef DDR_PHY_DX2GCR4_DXREFSSELRANGE_SHIFT #undef DDR_PHY_DX2GCR4_DXREFSSELRANGE_MASK -#define DDR_PHY_DX2GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C -#define DDR_PHY_DX2GCR4_DXREFSSELRANGE_SHIFT 15 -#define DDR_PHY_DX2GCR4_DXREFSSELRANGE_MASK 0x00008000U +#define DDR_PHY_DX2GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX2GCR4_DXREFSSELRANGE_SHIFT 15 +#define DDR_PHY_DX2GCR4_DXREFSSELRANGE_MASK 0x00008000U -/*Byte Lane Single-End VREF Select*/ +/* +* Byte Lane Single-End VREF Select +*/ #undef DDR_PHY_DX2GCR4_DXREFSSEL_DEFVAL #undef DDR_PHY_DX2GCR4_DXREFSSEL_SHIFT #undef DDR_PHY_DX2GCR4_DXREFSSEL_MASK -#define DDR_PHY_DX2GCR4_DXREFSSEL_DEFVAL 0x0E00003C -#define DDR_PHY_DX2GCR4_DXREFSSEL_SHIFT 8 -#define DDR_PHY_DX2GCR4_DXREFSSEL_MASK 0x00007F00U +#define DDR_PHY_DX2GCR4_DXREFSSEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX2GCR4_DXREFSSEL_SHIFT 8 +#define DDR_PHY_DX2GCR4_DXREFSSEL_MASK 0x00007F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX2GCR4_RESERVED_7_6_DEFVAL #undef DDR_PHY_DX2GCR4_RESERVED_7_6_SHIFT #undef DDR_PHY_DX2GCR4_RESERVED_7_6_MASK -#define DDR_PHY_DX2GCR4_RESERVED_7_6_DEFVAL 0x0E00003C -#define DDR_PHY_DX2GCR4_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_DX2GCR4_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_DX2GCR4_RESERVED_7_6_DEFVAL 0x0E00003C +#define DDR_PHY_DX2GCR4_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX2GCR4_RESERVED_7_6_MASK 0x000000C0U -/*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/ +/* +* VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. +*/ #undef DDR_PHY_DX2GCR4_DXREFIEN_DEFVAL #undef DDR_PHY_DX2GCR4_DXREFIEN_SHIFT #undef DDR_PHY_DX2GCR4_DXREFIEN_MASK -#define DDR_PHY_DX2GCR4_DXREFIEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX2GCR4_DXREFIEN_SHIFT 2 -#define DDR_PHY_DX2GCR4_DXREFIEN_MASK 0x0000003CU +#define DDR_PHY_DX2GCR4_DXREFIEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX2GCR4_DXREFIEN_SHIFT 2 +#define DDR_PHY_DX2GCR4_DXREFIEN_MASK 0x0000003CU -/*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/ +/* +* VRMON control for DQ IO (Single Ended) buffers of a byte lane. +*/ #undef DDR_PHY_DX2GCR4_DXREFIMON_DEFVAL #undef DDR_PHY_DX2GCR4_DXREFIMON_SHIFT #undef DDR_PHY_DX2GCR4_DXREFIMON_MASK -#define DDR_PHY_DX2GCR4_DXREFIMON_DEFVAL 0x0E00003C -#define DDR_PHY_DX2GCR4_DXREFIMON_SHIFT 0 -#define DDR_PHY_DX2GCR4_DXREFIMON_MASK 0x00000003U +#define DDR_PHY_DX2GCR4_DXREFIMON_DEFVAL 0x0E00003C +#define DDR_PHY_DX2GCR4_DXREFIMON_SHIFT 0 +#define DDR_PHY_DX2GCR4_DXREFIMON_MASK 0x00000003U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX2GCR5_RESERVED_31_DEFVAL #undef DDR_PHY_DX2GCR5_RESERVED_31_SHIFT #undef DDR_PHY_DX2GCR5_RESERVED_31_MASK -#define DDR_PHY_DX2GCR5_RESERVED_31_DEFVAL 0x09090909 -#define DDR_PHY_DX2GCR5_RESERVED_31_SHIFT 31 -#define DDR_PHY_DX2GCR5_RESERVED_31_MASK 0x80000000U +#define DDR_PHY_DX2GCR5_RESERVED_31_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR5_RESERVED_31_SHIFT 31 +#define DDR_PHY_DX2GCR5_RESERVED_31_MASK 0x80000000U -/*Byte Lane internal VREF Select for Rank 3*/ +/* +* Byte Lane internal VREF Select for Rank 3 +*/ #undef DDR_PHY_DX2GCR5_DXREFISELR3_DEFVAL #undef DDR_PHY_DX2GCR5_DXREFISELR3_SHIFT #undef DDR_PHY_DX2GCR5_DXREFISELR3_MASK -#define DDR_PHY_DX2GCR5_DXREFISELR3_DEFVAL 0x09090909 -#define DDR_PHY_DX2GCR5_DXREFISELR3_SHIFT 24 -#define DDR_PHY_DX2GCR5_DXREFISELR3_MASK 0x7F000000U +#define DDR_PHY_DX2GCR5_DXREFISELR3_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR5_DXREFISELR3_SHIFT 24 +#define DDR_PHY_DX2GCR5_DXREFISELR3_MASK 0x7F000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX2GCR5_RESERVED_23_DEFVAL #undef DDR_PHY_DX2GCR5_RESERVED_23_SHIFT #undef DDR_PHY_DX2GCR5_RESERVED_23_MASK -#define DDR_PHY_DX2GCR5_RESERVED_23_DEFVAL 0x09090909 -#define DDR_PHY_DX2GCR5_RESERVED_23_SHIFT 23 -#define DDR_PHY_DX2GCR5_RESERVED_23_MASK 0x00800000U +#define DDR_PHY_DX2GCR5_RESERVED_23_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR5_RESERVED_23_SHIFT 23 +#define DDR_PHY_DX2GCR5_RESERVED_23_MASK 0x00800000U -/*Byte Lane internal VREF Select for Rank 2*/ +/* +* Byte Lane internal VREF Select for Rank 2 +*/ #undef DDR_PHY_DX2GCR5_DXREFISELR2_DEFVAL #undef DDR_PHY_DX2GCR5_DXREFISELR2_SHIFT #undef DDR_PHY_DX2GCR5_DXREFISELR2_MASK -#define DDR_PHY_DX2GCR5_DXREFISELR2_DEFVAL 0x09090909 -#define DDR_PHY_DX2GCR5_DXREFISELR2_SHIFT 16 -#define DDR_PHY_DX2GCR5_DXREFISELR2_MASK 0x007F0000U +#define DDR_PHY_DX2GCR5_DXREFISELR2_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR5_DXREFISELR2_SHIFT 16 +#define DDR_PHY_DX2GCR5_DXREFISELR2_MASK 0x007F0000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX2GCR5_RESERVED_15_DEFVAL #undef DDR_PHY_DX2GCR5_RESERVED_15_SHIFT #undef DDR_PHY_DX2GCR5_RESERVED_15_MASK -#define DDR_PHY_DX2GCR5_RESERVED_15_DEFVAL 0x09090909 -#define DDR_PHY_DX2GCR5_RESERVED_15_SHIFT 15 -#define DDR_PHY_DX2GCR5_RESERVED_15_MASK 0x00008000U +#define DDR_PHY_DX2GCR5_RESERVED_15_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR5_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX2GCR5_RESERVED_15_MASK 0x00008000U -/*Byte Lane internal VREF Select for Rank 1*/ +/* +* Byte Lane internal VREF Select for Rank 1 +*/ #undef DDR_PHY_DX2GCR5_DXREFISELR1_DEFVAL #undef DDR_PHY_DX2GCR5_DXREFISELR1_SHIFT #undef DDR_PHY_DX2GCR5_DXREFISELR1_MASK -#define DDR_PHY_DX2GCR5_DXREFISELR1_DEFVAL 0x09090909 -#define DDR_PHY_DX2GCR5_DXREFISELR1_SHIFT 8 -#define DDR_PHY_DX2GCR5_DXREFISELR1_MASK 0x00007F00U +#define DDR_PHY_DX2GCR5_DXREFISELR1_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR5_DXREFISELR1_SHIFT 8 +#define DDR_PHY_DX2GCR5_DXREFISELR1_MASK 0x00007F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX2GCR5_RESERVED_7_DEFVAL #undef DDR_PHY_DX2GCR5_RESERVED_7_SHIFT #undef DDR_PHY_DX2GCR5_RESERVED_7_MASK -#define DDR_PHY_DX2GCR5_RESERVED_7_DEFVAL 0x09090909 -#define DDR_PHY_DX2GCR5_RESERVED_7_SHIFT 7 -#define DDR_PHY_DX2GCR5_RESERVED_7_MASK 0x00000080U +#define DDR_PHY_DX2GCR5_RESERVED_7_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR5_RESERVED_7_SHIFT 7 +#define DDR_PHY_DX2GCR5_RESERVED_7_MASK 0x00000080U -/*Byte Lane internal VREF Select for Rank 0*/ +/* +* Byte Lane internal VREF Select for Rank 0 +*/ #undef DDR_PHY_DX2GCR5_DXREFISELR0_DEFVAL #undef DDR_PHY_DX2GCR5_DXREFISELR0_SHIFT #undef DDR_PHY_DX2GCR5_DXREFISELR0_MASK -#define DDR_PHY_DX2GCR5_DXREFISELR0_DEFVAL 0x09090909 -#define DDR_PHY_DX2GCR5_DXREFISELR0_SHIFT 0 -#define DDR_PHY_DX2GCR5_DXREFISELR0_MASK 0x0000007FU +#define DDR_PHY_DX2GCR5_DXREFISELR0_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR5_DXREFISELR0_SHIFT 0 +#define DDR_PHY_DX2GCR5_DXREFISELR0_MASK 0x0000007FU -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX2GCR6_RESERVED_31_30_DEFVAL #undef DDR_PHY_DX2GCR6_RESERVED_31_30_SHIFT #undef DDR_PHY_DX2GCR6_RESERVED_31_30_MASK -#define DDR_PHY_DX2GCR6_RESERVED_31_30_DEFVAL 0x09090909 -#define DDR_PHY_DX2GCR6_RESERVED_31_30_SHIFT 30 -#define DDR_PHY_DX2GCR6_RESERVED_31_30_MASK 0xC0000000U +#define DDR_PHY_DX2GCR6_RESERVED_31_30_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR6_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX2GCR6_RESERVED_31_30_MASK 0xC0000000U -/*DRAM DQ VREF Select for Rank3*/ +/* +* DRAM DQ VREF Select for Rank3 +*/ #undef DDR_PHY_DX2GCR6_DXDQVREFR3_DEFVAL #undef DDR_PHY_DX2GCR6_DXDQVREFR3_SHIFT #undef DDR_PHY_DX2GCR6_DXDQVREFR3_MASK -#define DDR_PHY_DX2GCR6_DXDQVREFR3_DEFVAL 0x09090909 -#define DDR_PHY_DX2GCR6_DXDQVREFR3_SHIFT 24 -#define DDR_PHY_DX2GCR6_DXDQVREFR3_MASK 0x3F000000U +#define DDR_PHY_DX2GCR6_DXDQVREFR3_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR6_DXDQVREFR3_SHIFT 24 +#define DDR_PHY_DX2GCR6_DXDQVREFR3_MASK 0x3F000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX2GCR6_RESERVED_23_22_DEFVAL #undef DDR_PHY_DX2GCR6_RESERVED_23_22_SHIFT #undef DDR_PHY_DX2GCR6_RESERVED_23_22_MASK -#define DDR_PHY_DX2GCR6_RESERVED_23_22_DEFVAL 0x09090909 -#define DDR_PHY_DX2GCR6_RESERVED_23_22_SHIFT 22 -#define DDR_PHY_DX2GCR6_RESERVED_23_22_MASK 0x00C00000U +#define DDR_PHY_DX2GCR6_RESERVED_23_22_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR6_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX2GCR6_RESERVED_23_22_MASK 0x00C00000U -/*DRAM DQ VREF Select for Rank2*/ +/* +* DRAM DQ VREF Select for Rank2 +*/ #undef DDR_PHY_DX2GCR6_DXDQVREFR2_DEFVAL #undef DDR_PHY_DX2GCR6_DXDQVREFR2_SHIFT #undef DDR_PHY_DX2GCR6_DXDQVREFR2_MASK -#define DDR_PHY_DX2GCR6_DXDQVREFR2_DEFVAL 0x09090909 -#define DDR_PHY_DX2GCR6_DXDQVREFR2_SHIFT 16 -#define DDR_PHY_DX2GCR6_DXDQVREFR2_MASK 0x003F0000U +#define DDR_PHY_DX2GCR6_DXDQVREFR2_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR6_DXDQVREFR2_SHIFT 16 +#define DDR_PHY_DX2GCR6_DXDQVREFR2_MASK 0x003F0000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX2GCR6_RESERVED_15_14_DEFVAL #undef DDR_PHY_DX2GCR6_RESERVED_15_14_SHIFT #undef DDR_PHY_DX2GCR6_RESERVED_15_14_MASK -#define DDR_PHY_DX2GCR6_RESERVED_15_14_DEFVAL 0x09090909 -#define DDR_PHY_DX2GCR6_RESERVED_15_14_SHIFT 14 -#define DDR_PHY_DX2GCR6_RESERVED_15_14_MASK 0x0000C000U +#define DDR_PHY_DX2GCR6_RESERVED_15_14_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR6_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_DX2GCR6_RESERVED_15_14_MASK 0x0000C000U -/*DRAM DQ VREF Select for Rank1*/ +/* +* DRAM DQ VREF Select for Rank1 +*/ #undef DDR_PHY_DX2GCR6_DXDQVREFR1_DEFVAL #undef DDR_PHY_DX2GCR6_DXDQVREFR1_SHIFT #undef DDR_PHY_DX2GCR6_DXDQVREFR1_MASK -#define DDR_PHY_DX2GCR6_DXDQVREFR1_DEFVAL 0x09090909 -#define DDR_PHY_DX2GCR6_DXDQVREFR1_SHIFT 8 -#define DDR_PHY_DX2GCR6_DXDQVREFR1_MASK 0x00003F00U +#define DDR_PHY_DX2GCR6_DXDQVREFR1_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR6_DXDQVREFR1_SHIFT 8 +#define DDR_PHY_DX2GCR6_DXDQVREFR1_MASK 0x00003F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX2GCR6_RESERVED_7_6_DEFVAL #undef DDR_PHY_DX2GCR6_RESERVED_7_6_SHIFT #undef DDR_PHY_DX2GCR6_RESERVED_7_6_MASK -#define DDR_PHY_DX2GCR6_RESERVED_7_6_DEFVAL 0x09090909 -#define DDR_PHY_DX2GCR6_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_DX2GCR6_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_DX2GCR6_RESERVED_7_6_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR6_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX2GCR6_RESERVED_7_6_MASK 0x000000C0U -/*DRAM DQ VREF Select for Rank0*/ +/* +* DRAM DQ VREF Select for Rank0 +*/ #undef DDR_PHY_DX2GCR6_DXDQVREFR0_DEFVAL #undef DDR_PHY_DX2GCR6_DXDQVREFR0_SHIFT #undef DDR_PHY_DX2GCR6_DXDQVREFR0_MASK -#define DDR_PHY_DX2GCR6_DXDQVREFR0_DEFVAL 0x09090909 -#define DDR_PHY_DX2GCR6_DXDQVREFR0_SHIFT 0 -#define DDR_PHY_DX2GCR6_DXDQVREFR0_MASK 0x0000003FU +#define DDR_PHY_DX2GCR6_DXDQVREFR0_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR6_DXDQVREFR0_SHIFT 0 +#define DDR_PHY_DX2GCR6_DXDQVREFR0_MASK 0x0000003FU -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX2LCDLR2_RESERVED_31_25_DEFVAL -#undef DDR_PHY_DX2LCDLR2_RESERVED_31_25_SHIFT -#undef DDR_PHY_DX2LCDLR2_RESERVED_31_25_MASK -#define DDR_PHY_DX2LCDLR2_RESERVED_31_25_DEFVAL 0x00000000 -#define DDR_PHY_DX2LCDLR2_RESERVED_31_25_SHIFT 25 -#define DDR_PHY_DX2LCDLR2_RESERVED_31_25_MASK 0xFE000000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX2LCDLR2_RESERVED_24_16_DEFVAL -#undef DDR_PHY_DX2LCDLR2_RESERVED_24_16_SHIFT -#undef DDR_PHY_DX2LCDLR2_RESERVED_24_16_MASK -#define DDR_PHY_DX2LCDLR2_RESERVED_24_16_DEFVAL 0x00000000 -#define DDR_PHY_DX2LCDLR2_RESERVED_24_16_SHIFT 16 -#define DDR_PHY_DX2LCDLR2_RESERVED_24_16_MASK 0x01FF0000U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX2LCDLR2_RESERVED_15_9_DEFVAL -#undef DDR_PHY_DX2LCDLR2_RESERVED_15_9_SHIFT -#undef DDR_PHY_DX2LCDLR2_RESERVED_15_9_MASK -#define DDR_PHY_DX2LCDLR2_RESERVED_15_9_DEFVAL 0x00000000 -#define DDR_PHY_DX2LCDLR2_RESERVED_15_9_SHIFT 9 -#define DDR_PHY_DX2LCDLR2_RESERVED_15_9_MASK 0x0000FE00U - -/*Read DQS Gating Delay*/ -#undef DDR_PHY_DX2LCDLR2_DQSGD_DEFVAL -#undef DDR_PHY_DX2LCDLR2_DQSGD_SHIFT -#undef DDR_PHY_DX2LCDLR2_DQSGD_MASK -#define DDR_PHY_DX2LCDLR2_DQSGD_DEFVAL 0x00000000 -#define DDR_PHY_DX2LCDLR2_DQSGD_SHIFT 0 -#define DDR_PHY_DX2LCDLR2_DQSGD_MASK 0x000001FFU - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX2GTR0_RESERVED_31_24_DEFVAL -#undef DDR_PHY_DX2GTR0_RESERVED_31_24_SHIFT -#undef DDR_PHY_DX2GTR0_RESERVED_31_24_MASK -#define DDR_PHY_DX2GTR0_RESERVED_31_24_DEFVAL 0x00020000 -#define DDR_PHY_DX2GTR0_RESERVED_31_24_SHIFT 27 -#define DDR_PHY_DX2GTR0_RESERVED_31_24_MASK 0xF8000000U - -/*DQ Write Path Latency Pipeline*/ -#undef DDR_PHY_DX2GTR0_WDQSL_DEFVAL -#undef DDR_PHY_DX2GTR0_WDQSL_SHIFT -#undef DDR_PHY_DX2GTR0_WDQSL_MASK -#define DDR_PHY_DX2GTR0_WDQSL_DEFVAL 0x00020000 -#define DDR_PHY_DX2GTR0_WDQSL_SHIFT 24 -#define DDR_PHY_DX2GTR0_WDQSL_MASK 0x07000000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX2GTR0_RESERVED_23_20_DEFVAL -#undef DDR_PHY_DX2GTR0_RESERVED_23_20_SHIFT -#undef DDR_PHY_DX2GTR0_RESERVED_23_20_MASK -#define DDR_PHY_DX2GTR0_RESERVED_23_20_DEFVAL 0x00020000 -#define DDR_PHY_DX2GTR0_RESERVED_23_20_SHIFT 20 -#define DDR_PHY_DX2GTR0_RESERVED_23_20_MASK 0x00F00000U - -/*Write Leveling System Latency*/ -#undef DDR_PHY_DX2GTR0_WLSL_DEFVAL -#undef DDR_PHY_DX2GTR0_WLSL_SHIFT -#undef DDR_PHY_DX2GTR0_WLSL_MASK -#define DDR_PHY_DX2GTR0_WLSL_DEFVAL 0x00020000 -#define DDR_PHY_DX2GTR0_WLSL_SHIFT 16 -#define DDR_PHY_DX2GTR0_WLSL_MASK 0x000F0000U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX2GTR0_RESERVED_15_13_DEFVAL -#undef DDR_PHY_DX2GTR0_RESERVED_15_13_SHIFT -#undef DDR_PHY_DX2GTR0_RESERVED_15_13_MASK -#define DDR_PHY_DX2GTR0_RESERVED_15_13_DEFVAL 0x00020000 -#define DDR_PHY_DX2GTR0_RESERVED_15_13_SHIFT 13 -#define DDR_PHY_DX2GTR0_RESERVED_15_13_MASK 0x0000E000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX2GTR0_RESERVED_12_8_DEFVAL -#undef DDR_PHY_DX2GTR0_RESERVED_12_8_SHIFT -#undef DDR_PHY_DX2GTR0_RESERVED_12_8_MASK -#define DDR_PHY_DX2GTR0_RESERVED_12_8_DEFVAL 0x00020000 -#define DDR_PHY_DX2GTR0_RESERVED_12_8_SHIFT 8 -#define DDR_PHY_DX2GTR0_RESERVED_12_8_MASK 0x00001F00U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX2GTR0_RESERVED_7_5_DEFVAL -#undef DDR_PHY_DX2GTR0_RESERVED_7_5_SHIFT -#undef DDR_PHY_DX2GTR0_RESERVED_7_5_MASK -#define DDR_PHY_DX2GTR0_RESERVED_7_5_DEFVAL 0x00020000 -#define DDR_PHY_DX2GTR0_RESERVED_7_5_SHIFT 5 -#define DDR_PHY_DX2GTR0_RESERVED_7_5_MASK 0x000000E0U - -/*DQS Gating System Latency*/ -#undef DDR_PHY_DX2GTR0_DGSL_DEFVAL -#undef DDR_PHY_DX2GTR0_DGSL_SHIFT -#undef DDR_PHY_DX2GTR0_DGSL_MASK -#define DDR_PHY_DX2GTR0_DGSL_DEFVAL 0x00020000 -#define DDR_PHY_DX2GTR0_DGSL_SHIFT 0 -#define DDR_PHY_DX2GTR0_DGSL_MASK 0x0000001FU - -/*Calibration Bypass*/ +/* +* Calibration Bypass +*/ #undef DDR_PHY_DX3GCR0_CALBYP_DEFVAL #undef DDR_PHY_DX3GCR0_CALBYP_SHIFT #undef DDR_PHY_DX3GCR0_CALBYP_MASK -#define DDR_PHY_DX3GCR0_CALBYP_DEFVAL 0x40200204 -#define DDR_PHY_DX3GCR0_CALBYP_SHIFT 31 -#define DDR_PHY_DX3GCR0_CALBYP_MASK 0x80000000U +#define DDR_PHY_DX3GCR0_CALBYP_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_CALBYP_SHIFT 31 +#define DDR_PHY_DX3GCR0_CALBYP_MASK 0x80000000U -/*Master Delay Line Enable*/ +/* +* Master Delay Line Enable +*/ #undef DDR_PHY_DX3GCR0_MDLEN_DEFVAL #undef DDR_PHY_DX3GCR0_MDLEN_SHIFT #undef DDR_PHY_DX3GCR0_MDLEN_MASK -#define DDR_PHY_DX3GCR0_MDLEN_DEFVAL 0x40200204 -#define DDR_PHY_DX3GCR0_MDLEN_SHIFT 30 -#define DDR_PHY_DX3GCR0_MDLEN_MASK 0x40000000U +#define DDR_PHY_DX3GCR0_MDLEN_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_MDLEN_SHIFT 30 +#define DDR_PHY_DX3GCR0_MDLEN_MASK 0x40000000U -/*Configurable ODT(TE) Phase Shift*/ +/* +* Configurable ODT(TE) Phase Shift +*/ #undef DDR_PHY_DX3GCR0_CODTSHFT_DEFVAL #undef DDR_PHY_DX3GCR0_CODTSHFT_SHIFT #undef DDR_PHY_DX3GCR0_CODTSHFT_MASK -#define DDR_PHY_DX3GCR0_CODTSHFT_DEFVAL 0x40200204 -#define DDR_PHY_DX3GCR0_CODTSHFT_SHIFT 28 -#define DDR_PHY_DX3GCR0_CODTSHFT_MASK 0x30000000U +#define DDR_PHY_DX3GCR0_CODTSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_CODTSHFT_SHIFT 28 +#define DDR_PHY_DX3GCR0_CODTSHFT_MASK 0x30000000U -/*DQS Duty Cycle Correction*/ +/* +* DQS Duty Cycle Correction +*/ #undef DDR_PHY_DX3GCR0_DQSDCC_DEFVAL #undef DDR_PHY_DX3GCR0_DQSDCC_SHIFT #undef DDR_PHY_DX3GCR0_DQSDCC_MASK -#define DDR_PHY_DX3GCR0_DQSDCC_DEFVAL 0x40200204 -#define DDR_PHY_DX3GCR0_DQSDCC_SHIFT 24 -#define DDR_PHY_DX3GCR0_DQSDCC_MASK 0x0F000000U +#define DDR_PHY_DX3GCR0_DQSDCC_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_DQSDCC_SHIFT 24 +#define DDR_PHY_DX3GCR0_DQSDCC_MASK 0x0F000000U -/*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/ +/* +* Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY +*/ #undef DDR_PHY_DX3GCR0_RDDLY_DEFVAL #undef DDR_PHY_DX3GCR0_RDDLY_SHIFT #undef DDR_PHY_DX3GCR0_RDDLY_MASK -#define DDR_PHY_DX3GCR0_RDDLY_DEFVAL 0x40200204 -#define DDR_PHY_DX3GCR0_RDDLY_SHIFT 20 -#define DDR_PHY_DX3GCR0_RDDLY_MASK 0x00F00000U +#define DDR_PHY_DX3GCR0_RDDLY_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_RDDLY_SHIFT 20 +#define DDR_PHY_DX3GCR0_RDDLY_MASK 0x00F00000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX3GCR0_RESERVED_19_14_DEFVAL #undef DDR_PHY_DX3GCR0_RESERVED_19_14_SHIFT #undef DDR_PHY_DX3GCR0_RESERVED_19_14_MASK -#define DDR_PHY_DX3GCR0_RESERVED_19_14_DEFVAL 0x40200204 -#define DDR_PHY_DX3GCR0_RESERVED_19_14_SHIFT 14 -#define DDR_PHY_DX3GCR0_RESERVED_19_14_MASK 0x000FC000U +#define DDR_PHY_DX3GCR0_RESERVED_19_14_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_RESERVED_19_14_SHIFT 14 +#define DDR_PHY_DX3GCR0_RESERVED_19_14_MASK 0x000FC000U -/*DQSNSE Power Down Receiver*/ +/* +* DQSNSE Power Down Receiver +*/ #undef DDR_PHY_DX3GCR0_DQSNSEPDR_DEFVAL #undef DDR_PHY_DX3GCR0_DQSNSEPDR_SHIFT #undef DDR_PHY_DX3GCR0_DQSNSEPDR_MASK -#define DDR_PHY_DX3GCR0_DQSNSEPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX3GCR0_DQSNSEPDR_SHIFT 13 -#define DDR_PHY_DX3GCR0_DQSNSEPDR_MASK 0x00002000U +#define DDR_PHY_DX3GCR0_DQSNSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_DQSNSEPDR_SHIFT 13 +#define DDR_PHY_DX3GCR0_DQSNSEPDR_MASK 0x00002000U -/*DQSSE Power Down Receiver*/ +/* +* DQSSE Power Down Receiver +*/ #undef DDR_PHY_DX3GCR0_DQSSEPDR_DEFVAL #undef DDR_PHY_DX3GCR0_DQSSEPDR_SHIFT #undef DDR_PHY_DX3GCR0_DQSSEPDR_MASK -#define DDR_PHY_DX3GCR0_DQSSEPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX3GCR0_DQSSEPDR_SHIFT 12 -#define DDR_PHY_DX3GCR0_DQSSEPDR_MASK 0x00001000U +#define DDR_PHY_DX3GCR0_DQSSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_DQSSEPDR_SHIFT 12 +#define DDR_PHY_DX3GCR0_DQSSEPDR_MASK 0x00001000U -/*RTT On Additive Latency*/ +/* +* RTT On Additive Latency +*/ #undef DDR_PHY_DX3GCR0_RTTOAL_DEFVAL #undef DDR_PHY_DX3GCR0_RTTOAL_SHIFT #undef DDR_PHY_DX3GCR0_RTTOAL_MASK -#define DDR_PHY_DX3GCR0_RTTOAL_DEFVAL 0x40200204 -#define DDR_PHY_DX3GCR0_RTTOAL_SHIFT 11 -#define DDR_PHY_DX3GCR0_RTTOAL_MASK 0x00000800U +#define DDR_PHY_DX3GCR0_RTTOAL_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_RTTOAL_SHIFT 11 +#define DDR_PHY_DX3GCR0_RTTOAL_MASK 0x00000800U -/*RTT Output Hold*/ +/* +* RTT Output Hold +*/ #undef DDR_PHY_DX3GCR0_RTTOH_DEFVAL #undef DDR_PHY_DX3GCR0_RTTOH_SHIFT #undef DDR_PHY_DX3GCR0_RTTOH_MASK -#define DDR_PHY_DX3GCR0_RTTOH_DEFVAL 0x40200204 -#define DDR_PHY_DX3GCR0_RTTOH_SHIFT 9 -#define DDR_PHY_DX3GCR0_RTTOH_MASK 0x00000600U +#define DDR_PHY_DX3GCR0_RTTOH_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_RTTOH_SHIFT 9 +#define DDR_PHY_DX3GCR0_RTTOH_MASK 0x00000600U -/*Configurable PDR Phase Shift*/ +/* +* Configurable PDR Phase Shift +*/ #undef DDR_PHY_DX3GCR0_CPDRSHFT_DEFVAL #undef DDR_PHY_DX3GCR0_CPDRSHFT_SHIFT #undef DDR_PHY_DX3GCR0_CPDRSHFT_MASK -#define DDR_PHY_DX3GCR0_CPDRSHFT_DEFVAL 0x40200204 -#define DDR_PHY_DX3GCR0_CPDRSHFT_SHIFT 7 -#define DDR_PHY_DX3GCR0_CPDRSHFT_MASK 0x00000180U +#define DDR_PHY_DX3GCR0_CPDRSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_CPDRSHFT_SHIFT 7 +#define DDR_PHY_DX3GCR0_CPDRSHFT_MASK 0x00000180U -/*DQSR Power Down*/ +/* +* DQSR Power Down +*/ #undef DDR_PHY_DX3GCR0_DQSRPD_DEFVAL #undef DDR_PHY_DX3GCR0_DQSRPD_SHIFT #undef DDR_PHY_DX3GCR0_DQSRPD_MASK -#define DDR_PHY_DX3GCR0_DQSRPD_DEFVAL 0x40200204 -#define DDR_PHY_DX3GCR0_DQSRPD_SHIFT 6 -#define DDR_PHY_DX3GCR0_DQSRPD_MASK 0x00000040U +#define DDR_PHY_DX3GCR0_DQSRPD_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_DQSRPD_SHIFT 6 +#define DDR_PHY_DX3GCR0_DQSRPD_MASK 0x00000040U -/*DQSG Power Down Receiver*/ +/* +* DQSG Power Down Receiver +*/ #undef DDR_PHY_DX3GCR0_DQSGPDR_DEFVAL #undef DDR_PHY_DX3GCR0_DQSGPDR_SHIFT #undef DDR_PHY_DX3GCR0_DQSGPDR_MASK -#define DDR_PHY_DX3GCR0_DQSGPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX3GCR0_DQSGPDR_SHIFT 5 -#define DDR_PHY_DX3GCR0_DQSGPDR_MASK 0x00000020U +#define DDR_PHY_DX3GCR0_DQSGPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_DQSGPDR_SHIFT 5 +#define DDR_PHY_DX3GCR0_DQSGPDR_MASK 0x00000020U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX3GCR0_RESERVED_4_DEFVAL #undef DDR_PHY_DX3GCR0_RESERVED_4_SHIFT #undef DDR_PHY_DX3GCR0_RESERVED_4_MASK -#define DDR_PHY_DX3GCR0_RESERVED_4_DEFVAL 0x40200204 -#define DDR_PHY_DX3GCR0_RESERVED_4_SHIFT 4 -#define DDR_PHY_DX3GCR0_RESERVED_4_MASK 0x00000010U +#define DDR_PHY_DX3GCR0_RESERVED_4_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_RESERVED_4_SHIFT 4 +#define DDR_PHY_DX3GCR0_RESERVED_4_MASK 0x00000010U -/*DQSG On-Die Termination*/ +/* +* DQSG On-Die Termination +*/ #undef DDR_PHY_DX3GCR0_DQSGODT_DEFVAL #undef DDR_PHY_DX3GCR0_DQSGODT_SHIFT #undef DDR_PHY_DX3GCR0_DQSGODT_MASK -#define DDR_PHY_DX3GCR0_DQSGODT_DEFVAL 0x40200204 -#define DDR_PHY_DX3GCR0_DQSGODT_SHIFT 3 -#define DDR_PHY_DX3GCR0_DQSGODT_MASK 0x00000008U +#define DDR_PHY_DX3GCR0_DQSGODT_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_DQSGODT_SHIFT 3 +#define DDR_PHY_DX3GCR0_DQSGODT_MASK 0x00000008U -/*DQSG Output Enable*/ +/* +* DQSG Output Enable +*/ #undef DDR_PHY_DX3GCR0_DQSGOE_DEFVAL #undef DDR_PHY_DX3GCR0_DQSGOE_SHIFT #undef DDR_PHY_DX3GCR0_DQSGOE_MASK -#define DDR_PHY_DX3GCR0_DQSGOE_DEFVAL 0x40200204 -#define DDR_PHY_DX3GCR0_DQSGOE_SHIFT 2 -#define DDR_PHY_DX3GCR0_DQSGOE_MASK 0x00000004U +#define DDR_PHY_DX3GCR0_DQSGOE_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_DQSGOE_SHIFT 2 +#define DDR_PHY_DX3GCR0_DQSGOE_MASK 0x00000004U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX3GCR0_RESERVED_1_0_DEFVAL #undef DDR_PHY_DX3GCR0_RESERVED_1_0_SHIFT #undef DDR_PHY_DX3GCR0_RESERVED_1_0_MASK -#define DDR_PHY_DX3GCR0_RESERVED_1_0_DEFVAL 0x40200204 -#define DDR_PHY_DX3GCR0_RESERVED_1_0_SHIFT 0 -#define DDR_PHY_DX3GCR0_RESERVED_1_0_MASK 0x00000003U +#define DDR_PHY_DX3GCR0_RESERVED_1_0_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_RESERVED_1_0_SHIFT 0 +#define DDR_PHY_DX3GCR0_RESERVED_1_0_MASK 0x00000003U -/*Enables the PDR mode for DQ[7:0]*/ +/* +* Enables the PDR mode for DQ[7:0] +*/ #undef DDR_PHY_DX3GCR1_DXPDRMODE_DEFVAL #undef DDR_PHY_DX3GCR1_DXPDRMODE_SHIFT #undef DDR_PHY_DX3GCR1_DXPDRMODE_MASK -#define DDR_PHY_DX3GCR1_DXPDRMODE_DEFVAL 0x00007FFF -#define DDR_PHY_DX3GCR1_DXPDRMODE_SHIFT 16 -#define DDR_PHY_DX3GCR1_DXPDRMODE_MASK 0xFFFF0000U +#define DDR_PHY_DX3GCR1_DXPDRMODE_DEFVAL 0x00007FFF +#define DDR_PHY_DX3GCR1_DXPDRMODE_SHIFT 16 +#define DDR_PHY_DX3GCR1_DXPDRMODE_MASK 0xFFFF0000U -/*Reserved. Returns zeroes on reads.*/ +/* +* Reserved. Returns zeroes on reads. +*/ #undef DDR_PHY_DX3GCR1_RESERVED_15_DEFVAL #undef DDR_PHY_DX3GCR1_RESERVED_15_SHIFT #undef DDR_PHY_DX3GCR1_RESERVED_15_MASK -#define DDR_PHY_DX3GCR1_RESERVED_15_DEFVAL 0x00007FFF -#define DDR_PHY_DX3GCR1_RESERVED_15_SHIFT 15 -#define DDR_PHY_DX3GCR1_RESERVED_15_MASK 0x00008000U +#define DDR_PHY_DX3GCR1_RESERVED_15_DEFVAL 0x00007FFF +#define DDR_PHY_DX3GCR1_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX3GCR1_RESERVED_15_MASK 0x00008000U -/*Select the delayed or non-delayed read data strobe #*/ +/* +* Select the delayed or non-delayed read data strobe # +*/ #undef DDR_PHY_DX3GCR1_QSNSEL_DEFVAL #undef DDR_PHY_DX3GCR1_QSNSEL_SHIFT #undef DDR_PHY_DX3GCR1_QSNSEL_MASK -#define DDR_PHY_DX3GCR1_QSNSEL_DEFVAL 0x00007FFF -#define DDR_PHY_DX3GCR1_QSNSEL_SHIFT 14 -#define DDR_PHY_DX3GCR1_QSNSEL_MASK 0x00004000U +#define DDR_PHY_DX3GCR1_QSNSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX3GCR1_QSNSEL_SHIFT 14 +#define DDR_PHY_DX3GCR1_QSNSEL_MASK 0x00004000U -/*Select the delayed or non-delayed read data strobe*/ +/* +* Select the delayed or non-delayed read data strobe +*/ #undef DDR_PHY_DX3GCR1_QSSEL_DEFVAL #undef DDR_PHY_DX3GCR1_QSSEL_SHIFT #undef DDR_PHY_DX3GCR1_QSSEL_MASK -#define DDR_PHY_DX3GCR1_QSSEL_DEFVAL 0x00007FFF -#define DDR_PHY_DX3GCR1_QSSEL_SHIFT 13 -#define DDR_PHY_DX3GCR1_QSSEL_MASK 0x00002000U +#define DDR_PHY_DX3GCR1_QSSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX3GCR1_QSSEL_SHIFT 13 +#define DDR_PHY_DX3GCR1_QSSEL_MASK 0x00002000U -/*Enables Read Data Strobe in a byte lane*/ +/* +* Enables Read Data Strobe in a byte lane +*/ #undef DDR_PHY_DX3GCR1_OEEN_DEFVAL #undef DDR_PHY_DX3GCR1_OEEN_SHIFT #undef DDR_PHY_DX3GCR1_OEEN_MASK -#define DDR_PHY_DX3GCR1_OEEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX3GCR1_OEEN_SHIFT 12 -#define DDR_PHY_DX3GCR1_OEEN_MASK 0x00001000U +#define DDR_PHY_DX3GCR1_OEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX3GCR1_OEEN_SHIFT 12 +#define DDR_PHY_DX3GCR1_OEEN_MASK 0x00001000U -/*Enables PDR in a byte lane*/ +/* +* Enables PDR in a byte lane +*/ #undef DDR_PHY_DX3GCR1_PDREN_DEFVAL #undef DDR_PHY_DX3GCR1_PDREN_SHIFT #undef DDR_PHY_DX3GCR1_PDREN_MASK -#define DDR_PHY_DX3GCR1_PDREN_DEFVAL 0x00007FFF -#define DDR_PHY_DX3GCR1_PDREN_SHIFT 11 -#define DDR_PHY_DX3GCR1_PDREN_MASK 0x00000800U +#define DDR_PHY_DX3GCR1_PDREN_DEFVAL 0x00007FFF +#define DDR_PHY_DX3GCR1_PDREN_SHIFT 11 +#define DDR_PHY_DX3GCR1_PDREN_MASK 0x00000800U -/*Enables ODT/TE in a byte lane*/ +/* +* Enables ODT/TE in a byte lane +*/ #undef DDR_PHY_DX3GCR1_TEEN_DEFVAL #undef DDR_PHY_DX3GCR1_TEEN_SHIFT #undef DDR_PHY_DX3GCR1_TEEN_MASK -#define DDR_PHY_DX3GCR1_TEEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX3GCR1_TEEN_SHIFT 10 -#define DDR_PHY_DX3GCR1_TEEN_MASK 0x00000400U +#define DDR_PHY_DX3GCR1_TEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX3GCR1_TEEN_SHIFT 10 +#define DDR_PHY_DX3GCR1_TEEN_MASK 0x00000400U -/*Enables Write Data strobe in a byte lane*/ +/* +* Enables Write Data strobe in a byte lane +*/ #undef DDR_PHY_DX3GCR1_DSEN_DEFVAL #undef DDR_PHY_DX3GCR1_DSEN_SHIFT #undef DDR_PHY_DX3GCR1_DSEN_MASK -#define DDR_PHY_DX3GCR1_DSEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX3GCR1_DSEN_SHIFT 9 -#define DDR_PHY_DX3GCR1_DSEN_MASK 0x00000200U +#define DDR_PHY_DX3GCR1_DSEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX3GCR1_DSEN_SHIFT 9 +#define DDR_PHY_DX3GCR1_DSEN_MASK 0x00000200U -/*Enables DM pin in a byte lane*/ +/* +* Enables DM pin in a byte lane +*/ #undef DDR_PHY_DX3GCR1_DMEN_DEFVAL #undef DDR_PHY_DX3GCR1_DMEN_SHIFT #undef DDR_PHY_DX3GCR1_DMEN_MASK -#define DDR_PHY_DX3GCR1_DMEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX3GCR1_DMEN_SHIFT 8 -#define DDR_PHY_DX3GCR1_DMEN_MASK 0x00000100U +#define DDR_PHY_DX3GCR1_DMEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX3GCR1_DMEN_SHIFT 8 +#define DDR_PHY_DX3GCR1_DMEN_MASK 0x00000100U -/*Enables DQ corresponding to each bit in a byte*/ +/* +* Enables DQ corresponding to each bit in a byte +*/ #undef DDR_PHY_DX3GCR1_DQEN_DEFVAL #undef DDR_PHY_DX3GCR1_DQEN_SHIFT #undef DDR_PHY_DX3GCR1_DQEN_MASK -#define DDR_PHY_DX3GCR1_DQEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX3GCR1_DQEN_SHIFT 0 -#define DDR_PHY_DX3GCR1_DQEN_MASK 0x000000FFU +#define DDR_PHY_DX3GCR1_DQEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX3GCR1_DQEN_SHIFT 0 +#define DDR_PHY_DX3GCR1_DQEN_MASK 0x000000FFU -/*Byte lane VREF IOM (Used only by D4MU IOs)*/ +/* +* Byte lane VREF IOM (Used only by D4MU IOs) +*/ #undef DDR_PHY_DX3GCR4_RESERVED_31_29_DEFVAL #undef DDR_PHY_DX3GCR4_RESERVED_31_29_SHIFT #undef DDR_PHY_DX3GCR4_RESERVED_31_29_MASK -#define DDR_PHY_DX3GCR4_RESERVED_31_29_DEFVAL 0x0E00003C -#define DDR_PHY_DX3GCR4_RESERVED_31_29_SHIFT 29 -#define DDR_PHY_DX3GCR4_RESERVED_31_29_MASK 0xE0000000U +#define DDR_PHY_DX3GCR4_RESERVED_31_29_DEFVAL 0x0E00003C +#define DDR_PHY_DX3GCR4_RESERVED_31_29_SHIFT 29 +#define DDR_PHY_DX3GCR4_RESERVED_31_29_MASK 0xE0000000U -/*Byte Lane VREF Pad Enable*/ +/* +* Byte Lane VREF Pad Enable +*/ #undef DDR_PHY_DX3GCR4_DXREFPEN_DEFVAL #undef DDR_PHY_DX3GCR4_DXREFPEN_SHIFT #undef DDR_PHY_DX3GCR4_DXREFPEN_MASK -#define DDR_PHY_DX3GCR4_DXREFPEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX3GCR4_DXREFPEN_SHIFT 28 -#define DDR_PHY_DX3GCR4_DXREFPEN_MASK 0x10000000U +#define DDR_PHY_DX3GCR4_DXREFPEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX3GCR4_DXREFPEN_SHIFT 28 +#define DDR_PHY_DX3GCR4_DXREFPEN_MASK 0x10000000U -/*Byte Lane Internal VREF Enable*/ +/* +* Byte Lane Internal VREF Enable +*/ #undef DDR_PHY_DX3GCR4_DXREFEEN_DEFVAL #undef DDR_PHY_DX3GCR4_DXREFEEN_SHIFT #undef DDR_PHY_DX3GCR4_DXREFEEN_MASK -#define DDR_PHY_DX3GCR4_DXREFEEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX3GCR4_DXREFEEN_SHIFT 26 -#define DDR_PHY_DX3GCR4_DXREFEEN_MASK 0x0C000000U +#define DDR_PHY_DX3GCR4_DXREFEEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX3GCR4_DXREFEEN_SHIFT 26 +#define DDR_PHY_DX3GCR4_DXREFEEN_MASK 0x0C000000U -/*Byte Lane Single-End VREF Enable*/ +/* +* Byte Lane Single-End VREF Enable +*/ #undef DDR_PHY_DX3GCR4_DXREFSEN_DEFVAL #undef DDR_PHY_DX3GCR4_DXREFSEN_SHIFT #undef DDR_PHY_DX3GCR4_DXREFSEN_MASK -#define DDR_PHY_DX3GCR4_DXREFSEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX3GCR4_DXREFSEN_SHIFT 25 -#define DDR_PHY_DX3GCR4_DXREFSEN_MASK 0x02000000U +#define DDR_PHY_DX3GCR4_DXREFSEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX3GCR4_DXREFSEN_SHIFT 25 +#define DDR_PHY_DX3GCR4_DXREFSEN_MASK 0x02000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX3GCR4_RESERVED_24_DEFVAL #undef DDR_PHY_DX3GCR4_RESERVED_24_SHIFT #undef DDR_PHY_DX3GCR4_RESERVED_24_MASK -#define DDR_PHY_DX3GCR4_RESERVED_24_DEFVAL 0x0E00003C -#define DDR_PHY_DX3GCR4_RESERVED_24_SHIFT 24 -#define DDR_PHY_DX3GCR4_RESERVED_24_MASK 0x01000000U +#define DDR_PHY_DX3GCR4_RESERVED_24_DEFVAL 0x0E00003C +#define DDR_PHY_DX3GCR4_RESERVED_24_SHIFT 24 +#define DDR_PHY_DX3GCR4_RESERVED_24_MASK 0x01000000U -/*External VREF generator REFSEL range select*/ +/* +* External VREF generator REFSEL range select +*/ #undef DDR_PHY_DX3GCR4_DXREFESELRANGE_DEFVAL #undef DDR_PHY_DX3GCR4_DXREFESELRANGE_SHIFT #undef DDR_PHY_DX3GCR4_DXREFESELRANGE_MASK -#define DDR_PHY_DX3GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C -#define DDR_PHY_DX3GCR4_DXREFESELRANGE_SHIFT 23 -#define DDR_PHY_DX3GCR4_DXREFESELRANGE_MASK 0x00800000U +#define DDR_PHY_DX3GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX3GCR4_DXREFESELRANGE_SHIFT 23 +#define DDR_PHY_DX3GCR4_DXREFESELRANGE_MASK 0x00800000U -/*Byte Lane External VREF Select*/ +/* +* Byte Lane External VREF Select +*/ #undef DDR_PHY_DX3GCR4_DXREFESEL_DEFVAL #undef DDR_PHY_DX3GCR4_DXREFESEL_SHIFT #undef DDR_PHY_DX3GCR4_DXREFESEL_MASK -#define DDR_PHY_DX3GCR4_DXREFESEL_DEFVAL 0x0E00003C -#define DDR_PHY_DX3GCR4_DXREFESEL_SHIFT 16 -#define DDR_PHY_DX3GCR4_DXREFESEL_MASK 0x007F0000U +#define DDR_PHY_DX3GCR4_DXREFESEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX3GCR4_DXREFESEL_SHIFT 16 +#define DDR_PHY_DX3GCR4_DXREFESEL_MASK 0x007F0000U -/*Single ended VREF generator REFSEL range select*/ +/* +* Single ended VREF generator REFSEL range select +*/ #undef DDR_PHY_DX3GCR4_DXREFSSELRANGE_DEFVAL #undef DDR_PHY_DX3GCR4_DXREFSSELRANGE_SHIFT #undef DDR_PHY_DX3GCR4_DXREFSSELRANGE_MASK -#define DDR_PHY_DX3GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C -#define DDR_PHY_DX3GCR4_DXREFSSELRANGE_SHIFT 15 -#define DDR_PHY_DX3GCR4_DXREFSSELRANGE_MASK 0x00008000U +#define DDR_PHY_DX3GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX3GCR4_DXREFSSELRANGE_SHIFT 15 +#define DDR_PHY_DX3GCR4_DXREFSSELRANGE_MASK 0x00008000U -/*Byte Lane Single-End VREF Select*/ +/* +* Byte Lane Single-End VREF Select +*/ #undef DDR_PHY_DX3GCR4_DXREFSSEL_DEFVAL #undef DDR_PHY_DX3GCR4_DXREFSSEL_SHIFT #undef DDR_PHY_DX3GCR4_DXREFSSEL_MASK -#define DDR_PHY_DX3GCR4_DXREFSSEL_DEFVAL 0x0E00003C -#define DDR_PHY_DX3GCR4_DXREFSSEL_SHIFT 8 -#define DDR_PHY_DX3GCR4_DXREFSSEL_MASK 0x00007F00U +#define DDR_PHY_DX3GCR4_DXREFSSEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX3GCR4_DXREFSSEL_SHIFT 8 +#define DDR_PHY_DX3GCR4_DXREFSSEL_MASK 0x00007F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX3GCR4_RESERVED_7_6_DEFVAL #undef DDR_PHY_DX3GCR4_RESERVED_7_6_SHIFT #undef DDR_PHY_DX3GCR4_RESERVED_7_6_MASK -#define DDR_PHY_DX3GCR4_RESERVED_7_6_DEFVAL 0x0E00003C -#define DDR_PHY_DX3GCR4_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_DX3GCR4_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_DX3GCR4_RESERVED_7_6_DEFVAL 0x0E00003C +#define DDR_PHY_DX3GCR4_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX3GCR4_RESERVED_7_6_MASK 0x000000C0U -/*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/ +/* +* VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. +*/ #undef DDR_PHY_DX3GCR4_DXREFIEN_DEFVAL #undef DDR_PHY_DX3GCR4_DXREFIEN_SHIFT #undef DDR_PHY_DX3GCR4_DXREFIEN_MASK -#define DDR_PHY_DX3GCR4_DXREFIEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX3GCR4_DXREFIEN_SHIFT 2 -#define DDR_PHY_DX3GCR4_DXREFIEN_MASK 0x0000003CU +#define DDR_PHY_DX3GCR4_DXREFIEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX3GCR4_DXREFIEN_SHIFT 2 +#define DDR_PHY_DX3GCR4_DXREFIEN_MASK 0x0000003CU -/*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/ +/* +* VRMON control for DQ IO (Single Ended) buffers of a byte lane. +*/ #undef DDR_PHY_DX3GCR4_DXREFIMON_DEFVAL #undef DDR_PHY_DX3GCR4_DXREFIMON_SHIFT #undef DDR_PHY_DX3GCR4_DXREFIMON_MASK -#define DDR_PHY_DX3GCR4_DXREFIMON_DEFVAL 0x0E00003C -#define DDR_PHY_DX3GCR4_DXREFIMON_SHIFT 0 -#define DDR_PHY_DX3GCR4_DXREFIMON_MASK 0x00000003U +#define DDR_PHY_DX3GCR4_DXREFIMON_DEFVAL 0x0E00003C +#define DDR_PHY_DX3GCR4_DXREFIMON_SHIFT 0 +#define DDR_PHY_DX3GCR4_DXREFIMON_MASK 0x00000003U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX3GCR5_RESERVED_31_DEFVAL #undef DDR_PHY_DX3GCR5_RESERVED_31_SHIFT #undef DDR_PHY_DX3GCR5_RESERVED_31_MASK -#define DDR_PHY_DX3GCR5_RESERVED_31_DEFVAL 0x09090909 -#define DDR_PHY_DX3GCR5_RESERVED_31_SHIFT 31 -#define DDR_PHY_DX3GCR5_RESERVED_31_MASK 0x80000000U +#define DDR_PHY_DX3GCR5_RESERVED_31_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR5_RESERVED_31_SHIFT 31 +#define DDR_PHY_DX3GCR5_RESERVED_31_MASK 0x80000000U -/*Byte Lane internal VREF Select for Rank 3*/ +/* +* Byte Lane internal VREF Select for Rank 3 +*/ #undef DDR_PHY_DX3GCR5_DXREFISELR3_DEFVAL #undef DDR_PHY_DX3GCR5_DXREFISELR3_SHIFT #undef DDR_PHY_DX3GCR5_DXREFISELR3_MASK -#define DDR_PHY_DX3GCR5_DXREFISELR3_DEFVAL 0x09090909 -#define DDR_PHY_DX3GCR5_DXREFISELR3_SHIFT 24 -#define DDR_PHY_DX3GCR5_DXREFISELR3_MASK 0x7F000000U +#define DDR_PHY_DX3GCR5_DXREFISELR3_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR5_DXREFISELR3_SHIFT 24 +#define DDR_PHY_DX3GCR5_DXREFISELR3_MASK 0x7F000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX3GCR5_RESERVED_23_DEFVAL #undef DDR_PHY_DX3GCR5_RESERVED_23_SHIFT #undef DDR_PHY_DX3GCR5_RESERVED_23_MASK -#define DDR_PHY_DX3GCR5_RESERVED_23_DEFVAL 0x09090909 -#define DDR_PHY_DX3GCR5_RESERVED_23_SHIFT 23 -#define DDR_PHY_DX3GCR5_RESERVED_23_MASK 0x00800000U +#define DDR_PHY_DX3GCR5_RESERVED_23_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR5_RESERVED_23_SHIFT 23 +#define DDR_PHY_DX3GCR5_RESERVED_23_MASK 0x00800000U -/*Byte Lane internal VREF Select for Rank 2*/ +/* +* Byte Lane internal VREF Select for Rank 2 +*/ #undef DDR_PHY_DX3GCR5_DXREFISELR2_DEFVAL #undef DDR_PHY_DX3GCR5_DXREFISELR2_SHIFT #undef DDR_PHY_DX3GCR5_DXREFISELR2_MASK -#define DDR_PHY_DX3GCR5_DXREFISELR2_DEFVAL 0x09090909 -#define DDR_PHY_DX3GCR5_DXREFISELR2_SHIFT 16 -#define DDR_PHY_DX3GCR5_DXREFISELR2_MASK 0x007F0000U +#define DDR_PHY_DX3GCR5_DXREFISELR2_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR5_DXREFISELR2_SHIFT 16 +#define DDR_PHY_DX3GCR5_DXREFISELR2_MASK 0x007F0000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX3GCR5_RESERVED_15_DEFVAL #undef DDR_PHY_DX3GCR5_RESERVED_15_SHIFT #undef DDR_PHY_DX3GCR5_RESERVED_15_MASK -#define DDR_PHY_DX3GCR5_RESERVED_15_DEFVAL 0x09090909 -#define DDR_PHY_DX3GCR5_RESERVED_15_SHIFT 15 -#define DDR_PHY_DX3GCR5_RESERVED_15_MASK 0x00008000U +#define DDR_PHY_DX3GCR5_RESERVED_15_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR5_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX3GCR5_RESERVED_15_MASK 0x00008000U -/*Byte Lane internal VREF Select for Rank 1*/ +/* +* Byte Lane internal VREF Select for Rank 1 +*/ #undef DDR_PHY_DX3GCR5_DXREFISELR1_DEFVAL #undef DDR_PHY_DX3GCR5_DXREFISELR1_SHIFT #undef DDR_PHY_DX3GCR5_DXREFISELR1_MASK -#define DDR_PHY_DX3GCR5_DXREFISELR1_DEFVAL 0x09090909 -#define DDR_PHY_DX3GCR5_DXREFISELR1_SHIFT 8 -#define DDR_PHY_DX3GCR5_DXREFISELR1_MASK 0x00007F00U +#define DDR_PHY_DX3GCR5_DXREFISELR1_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR5_DXREFISELR1_SHIFT 8 +#define DDR_PHY_DX3GCR5_DXREFISELR1_MASK 0x00007F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX3GCR5_RESERVED_7_DEFVAL #undef DDR_PHY_DX3GCR5_RESERVED_7_SHIFT #undef DDR_PHY_DX3GCR5_RESERVED_7_MASK -#define DDR_PHY_DX3GCR5_RESERVED_7_DEFVAL 0x09090909 -#define DDR_PHY_DX3GCR5_RESERVED_7_SHIFT 7 -#define DDR_PHY_DX3GCR5_RESERVED_7_MASK 0x00000080U +#define DDR_PHY_DX3GCR5_RESERVED_7_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR5_RESERVED_7_SHIFT 7 +#define DDR_PHY_DX3GCR5_RESERVED_7_MASK 0x00000080U -/*Byte Lane internal VREF Select for Rank 0*/ +/* +* Byte Lane internal VREF Select for Rank 0 +*/ #undef DDR_PHY_DX3GCR5_DXREFISELR0_DEFVAL #undef DDR_PHY_DX3GCR5_DXREFISELR0_SHIFT #undef DDR_PHY_DX3GCR5_DXREFISELR0_MASK -#define DDR_PHY_DX3GCR5_DXREFISELR0_DEFVAL 0x09090909 -#define DDR_PHY_DX3GCR5_DXREFISELR0_SHIFT 0 -#define DDR_PHY_DX3GCR5_DXREFISELR0_MASK 0x0000007FU +#define DDR_PHY_DX3GCR5_DXREFISELR0_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR5_DXREFISELR0_SHIFT 0 +#define DDR_PHY_DX3GCR5_DXREFISELR0_MASK 0x0000007FU -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX3GCR6_RESERVED_31_30_DEFVAL #undef DDR_PHY_DX3GCR6_RESERVED_31_30_SHIFT #undef DDR_PHY_DX3GCR6_RESERVED_31_30_MASK -#define DDR_PHY_DX3GCR6_RESERVED_31_30_DEFVAL 0x09090909 -#define DDR_PHY_DX3GCR6_RESERVED_31_30_SHIFT 30 -#define DDR_PHY_DX3GCR6_RESERVED_31_30_MASK 0xC0000000U +#define DDR_PHY_DX3GCR6_RESERVED_31_30_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR6_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX3GCR6_RESERVED_31_30_MASK 0xC0000000U -/*DRAM DQ VREF Select for Rank3*/ +/* +* DRAM DQ VREF Select for Rank3 +*/ #undef DDR_PHY_DX3GCR6_DXDQVREFR3_DEFVAL #undef DDR_PHY_DX3GCR6_DXDQVREFR3_SHIFT #undef DDR_PHY_DX3GCR6_DXDQVREFR3_MASK -#define DDR_PHY_DX3GCR6_DXDQVREFR3_DEFVAL 0x09090909 -#define DDR_PHY_DX3GCR6_DXDQVREFR3_SHIFT 24 -#define DDR_PHY_DX3GCR6_DXDQVREFR3_MASK 0x3F000000U +#define DDR_PHY_DX3GCR6_DXDQVREFR3_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR6_DXDQVREFR3_SHIFT 24 +#define DDR_PHY_DX3GCR6_DXDQVREFR3_MASK 0x3F000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX3GCR6_RESERVED_23_22_DEFVAL #undef DDR_PHY_DX3GCR6_RESERVED_23_22_SHIFT #undef DDR_PHY_DX3GCR6_RESERVED_23_22_MASK -#define DDR_PHY_DX3GCR6_RESERVED_23_22_DEFVAL 0x09090909 -#define DDR_PHY_DX3GCR6_RESERVED_23_22_SHIFT 22 -#define DDR_PHY_DX3GCR6_RESERVED_23_22_MASK 0x00C00000U +#define DDR_PHY_DX3GCR6_RESERVED_23_22_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR6_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX3GCR6_RESERVED_23_22_MASK 0x00C00000U -/*DRAM DQ VREF Select for Rank2*/ +/* +* DRAM DQ VREF Select for Rank2 +*/ #undef DDR_PHY_DX3GCR6_DXDQVREFR2_DEFVAL #undef DDR_PHY_DX3GCR6_DXDQVREFR2_SHIFT #undef DDR_PHY_DX3GCR6_DXDQVREFR2_MASK -#define DDR_PHY_DX3GCR6_DXDQVREFR2_DEFVAL 0x09090909 -#define DDR_PHY_DX3GCR6_DXDQVREFR2_SHIFT 16 -#define DDR_PHY_DX3GCR6_DXDQVREFR2_MASK 0x003F0000U +#define DDR_PHY_DX3GCR6_DXDQVREFR2_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR6_DXDQVREFR2_SHIFT 16 +#define DDR_PHY_DX3GCR6_DXDQVREFR2_MASK 0x003F0000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX3GCR6_RESERVED_15_14_DEFVAL #undef DDR_PHY_DX3GCR6_RESERVED_15_14_SHIFT #undef DDR_PHY_DX3GCR6_RESERVED_15_14_MASK -#define DDR_PHY_DX3GCR6_RESERVED_15_14_DEFVAL 0x09090909 -#define DDR_PHY_DX3GCR6_RESERVED_15_14_SHIFT 14 -#define DDR_PHY_DX3GCR6_RESERVED_15_14_MASK 0x0000C000U +#define DDR_PHY_DX3GCR6_RESERVED_15_14_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR6_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_DX3GCR6_RESERVED_15_14_MASK 0x0000C000U -/*DRAM DQ VREF Select for Rank1*/ +/* +* DRAM DQ VREF Select for Rank1 +*/ #undef DDR_PHY_DX3GCR6_DXDQVREFR1_DEFVAL #undef DDR_PHY_DX3GCR6_DXDQVREFR1_SHIFT #undef DDR_PHY_DX3GCR6_DXDQVREFR1_MASK -#define DDR_PHY_DX3GCR6_DXDQVREFR1_DEFVAL 0x09090909 -#define DDR_PHY_DX3GCR6_DXDQVREFR1_SHIFT 8 -#define DDR_PHY_DX3GCR6_DXDQVREFR1_MASK 0x00003F00U +#define DDR_PHY_DX3GCR6_DXDQVREFR1_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR6_DXDQVREFR1_SHIFT 8 +#define DDR_PHY_DX3GCR6_DXDQVREFR1_MASK 0x00003F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX3GCR6_RESERVED_7_6_DEFVAL #undef DDR_PHY_DX3GCR6_RESERVED_7_6_SHIFT #undef DDR_PHY_DX3GCR6_RESERVED_7_6_MASK -#define DDR_PHY_DX3GCR6_RESERVED_7_6_DEFVAL 0x09090909 -#define DDR_PHY_DX3GCR6_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_DX3GCR6_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_DX3GCR6_RESERVED_7_6_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR6_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX3GCR6_RESERVED_7_6_MASK 0x000000C0U -/*DRAM DQ VREF Select for Rank0*/ +/* +* DRAM DQ VREF Select for Rank0 +*/ #undef DDR_PHY_DX3GCR6_DXDQVREFR0_DEFVAL #undef DDR_PHY_DX3GCR6_DXDQVREFR0_SHIFT #undef DDR_PHY_DX3GCR6_DXDQVREFR0_MASK -#define DDR_PHY_DX3GCR6_DXDQVREFR0_DEFVAL 0x09090909 -#define DDR_PHY_DX3GCR6_DXDQVREFR0_SHIFT 0 -#define DDR_PHY_DX3GCR6_DXDQVREFR0_MASK 0x0000003FU +#define DDR_PHY_DX3GCR6_DXDQVREFR0_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR6_DXDQVREFR0_SHIFT 0 +#define DDR_PHY_DX3GCR6_DXDQVREFR0_MASK 0x0000003FU -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX3LCDLR2_RESERVED_31_25_DEFVAL -#undef DDR_PHY_DX3LCDLR2_RESERVED_31_25_SHIFT -#undef DDR_PHY_DX3LCDLR2_RESERVED_31_25_MASK -#define DDR_PHY_DX3LCDLR2_RESERVED_31_25_DEFVAL 0x00000000 -#define DDR_PHY_DX3LCDLR2_RESERVED_31_25_SHIFT 25 -#define DDR_PHY_DX3LCDLR2_RESERVED_31_25_MASK 0xFE000000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX3LCDLR2_RESERVED_24_16_DEFVAL -#undef DDR_PHY_DX3LCDLR2_RESERVED_24_16_SHIFT -#undef DDR_PHY_DX3LCDLR2_RESERVED_24_16_MASK -#define DDR_PHY_DX3LCDLR2_RESERVED_24_16_DEFVAL 0x00000000 -#define DDR_PHY_DX3LCDLR2_RESERVED_24_16_SHIFT 16 -#define DDR_PHY_DX3LCDLR2_RESERVED_24_16_MASK 0x01FF0000U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX3LCDLR2_RESERVED_15_9_DEFVAL -#undef DDR_PHY_DX3LCDLR2_RESERVED_15_9_SHIFT -#undef DDR_PHY_DX3LCDLR2_RESERVED_15_9_MASK -#define DDR_PHY_DX3LCDLR2_RESERVED_15_9_DEFVAL 0x00000000 -#define DDR_PHY_DX3LCDLR2_RESERVED_15_9_SHIFT 9 -#define DDR_PHY_DX3LCDLR2_RESERVED_15_9_MASK 0x0000FE00U - -/*Read DQS Gating Delay*/ -#undef DDR_PHY_DX3LCDLR2_DQSGD_DEFVAL -#undef DDR_PHY_DX3LCDLR2_DQSGD_SHIFT -#undef DDR_PHY_DX3LCDLR2_DQSGD_MASK -#define DDR_PHY_DX3LCDLR2_DQSGD_DEFVAL 0x00000000 -#define DDR_PHY_DX3LCDLR2_DQSGD_SHIFT 0 -#define DDR_PHY_DX3LCDLR2_DQSGD_MASK 0x000001FFU - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX3GTR0_RESERVED_31_24_DEFVAL -#undef DDR_PHY_DX3GTR0_RESERVED_31_24_SHIFT -#undef DDR_PHY_DX3GTR0_RESERVED_31_24_MASK -#define DDR_PHY_DX3GTR0_RESERVED_31_24_DEFVAL 0x00020000 -#define DDR_PHY_DX3GTR0_RESERVED_31_24_SHIFT 27 -#define DDR_PHY_DX3GTR0_RESERVED_31_24_MASK 0xF8000000U - -/*DQ Write Path Latency Pipeline*/ -#undef DDR_PHY_DX3GTR0_WDQSL_DEFVAL -#undef DDR_PHY_DX3GTR0_WDQSL_SHIFT -#undef DDR_PHY_DX3GTR0_WDQSL_MASK -#define DDR_PHY_DX3GTR0_WDQSL_DEFVAL 0x00020000 -#define DDR_PHY_DX3GTR0_WDQSL_SHIFT 24 -#define DDR_PHY_DX3GTR0_WDQSL_MASK 0x07000000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX3GTR0_RESERVED_23_20_DEFVAL -#undef DDR_PHY_DX3GTR0_RESERVED_23_20_SHIFT -#undef DDR_PHY_DX3GTR0_RESERVED_23_20_MASK -#define DDR_PHY_DX3GTR0_RESERVED_23_20_DEFVAL 0x00020000 -#define DDR_PHY_DX3GTR0_RESERVED_23_20_SHIFT 20 -#define DDR_PHY_DX3GTR0_RESERVED_23_20_MASK 0x00F00000U - -/*Write Leveling System Latency*/ -#undef DDR_PHY_DX3GTR0_WLSL_DEFVAL -#undef DDR_PHY_DX3GTR0_WLSL_SHIFT -#undef DDR_PHY_DX3GTR0_WLSL_MASK -#define DDR_PHY_DX3GTR0_WLSL_DEFVAL 0x00020000 -#define DDR_PHY_DX3GTR0_WLSL_SHIFT 16 -#define DDR_PHY_DX3GTR0_WLSL_MASK 0x000F0000U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX3GTR0_RESERVED_15_13_DEFVAL -#undef DDR_PHY_DX3GTR0_RESERVED_15_13_SHIFT -#undef DDR_PHY_DX3GTR0_RESERVED_15_13_MASK -#define DDR_PHY_DX3GTR0_RESERVED_15_13_DEFVAL 0x00020000 -#define DDR_PHY_DX3GTR0_RESERVED_15_13_SHIFT 13 -#define DDR_PHY_DX3GTR0_RESERVED_15_13_MASK 0x0000E000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX3GTR0_RESERVED_12_8_DEFVAL -#undef DDR_PHY_DX3GTR0_RESERVED_12_8_SHIFT -#undef DDR_PHY_DX3GTR0_RESERVED_12_8_MASK -#define DDR_PHY_DX3GTR0_RESERVED_12_8_DEFVAL 0x00020000 -#define DDR_PHY_DX3GTR0_RESERVED_12_8_SHIFT 8 -#define DDR_PHY_DX3GTR0_RESERVED_12_8_MASK 0x00001F00U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX3GTR0_RESERVED_7_5_DEFVAL -#undef DDR_PHY_DX3GTR0_RESERVED_7_5_SHIFT -#undef DDR_PHY_DX3GTR0_RESERVED_7_5_MASK -#define DDR_PHY_DX3GTR0_RESERVED_7_5_DEFVAL 0x00020000 -#define DDR_PHY_DX3GTR0_RESERVED_7_5_SHIFT 5 -#define DDR_PHY_DX3GTR0_RESERVED_7_5_MASK 0x000000E0U - -/*DQS Gating System Latency*/ -#undef DDR_PHY_DX3GTR0_DGSL_DEFVAL -#undef DDR_PHY_DX3GTR0_DGSL_SHIFT -#undef DDR_PHY_DX3GTR0_DGSL_MASK -#define DDR_PHY_DX3GTR0_DGSL_DEFVAL 0x00020000 -#define DDR_PHY_DX3GTR0_DGSL_SHIFT 0 -#define DDR_PHY_DX3GTR0_DGSL_MASK 0x0000001FU - -/*Calibration Bypass*/ +/* +* Calibration Bypass +*/ #undef DDR_PHY_DX4GCR0_CALBYP_DEFVAL #undef DDR_PHY_DX4GCR0_CALBYP_SHIFT #undef DDR_PHY_DX4GCR0_CALBYP_MASK -#define DDR_PHY_DX4GCR0_CALBYP_DEFVAL 0x40200204 -#define DDR_PHY_DX4GCR0_CALBYP_SHIFT 31 -#define DDR_PHY_DX4GCR0_CALBYP_MASK 0x80000000U +#define DDR_PHY_DX4GCR0_CALBYP_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_CALBYP_SHIFT 31 +#define DDR_PHY_DX4GCR0_CALBYP_MASK 0x80000000U -/*Master Delay Line Enable*/ +/* +* Master Delay Line Enable +*/ #undef DDR_PHY_DX4GCR0_MDLEN_DEFVAL #undef DDR_PHY_DX4GCR0_MDLEN_SHIFT #undef DDR_PHY_DX4GCR0_MDLEN_MASK -#define DDR_PHY_DX4GCR0_MDLEN_DEFVAL 0x40200204 -#define DDR_PHY_DX4GCR0_MDLEN_SHIFT 30 -#define DDR_PHY_DX4GCR0_MDLEN_MASK 0x40000000U +#define DDR_PHY_DX4GCR0_MDLEN_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_MDLEN_SHIFT 30 +#define DDR_PHY_DX4GCR0_MDLEN_MASK 0x40000000U -/*Configurable ODT(TE) Phase Shift*/ +/* +* Configurable ODT(TE) Phase Shift +*/ #undef DDR_PHY_DX4GCR0_CODTSHFT_DEFVAL #undef DDR_PHY_DX4GCR0_CODTSHFT_SHIFT #undef DDR_PHY_DX4GCR0_CODTSHFT_MASK -#define DDR_PHY_DX4GCR0_CODTSHFT_DEFVAL 0x40200204 -#define DDR_PHY_DX4GCR0_CODTSHFT_SHIFT 28 -#define DDR_PHY_DX4GCR0_CODTSHFT_MASK 0x30000000U +#define DDR_PHY_DX4GCR0_CODTSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_CODTSHFT_SHIFT 28 +#define DDR_PHY_DX4GCR0_CODTSHFT_MASK 0x30000000U -/*DQS Duty Cycle Correction*/ +/* +* DQS Duty Cycle Correction +*/ #undef DDR_PHY_DX4GCR0_DQSDCC_DEFVAL #undef DDR_PHY_DX4GCR0_DQSDCC_SHIFT #undef DDR_PHY_DX4GCR0_DQSDCC_MASK -#define DDR_PHY_DX4GCR0_DQSDCC_DEFVAL 0x40200204 -#define DDR_PHY_DX4GCR0_DQSDCC_SHIFT 24 -#define DDR_PHY_DX4GCR0_DQSDCC_MASK 0x0F000000U +#define DDR_PHY_DX4GCR0_DQSDCC_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_DQSDCC_SHIFT 24 +#define DDR_PHY_DX4GCR0_DQSDCC_MASK 0x0F000000U -/*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/ +/* +* Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY +*/ #undef DDR_PHY_DX4GCR0_RDDLY_DEFVAL #undef DDR_PHY_DX4GCR0_RDDLY_SHIFT #undef DDR_PHY_DX4GCR0_RDDLY_MASK -#define DDR_PHY_DX4GCR0_RDDLY_DEFVAL 0x40200204 -#define DDR_PHY_DX4GCR0_RDDLY_SHIFT 20 -#define DDR_PHY_DX4GCR0_RDDLY_MASK 0x00F00000U +#define DDR_PHY_DX4GCR0_RDDLY_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_RDDLY_SHIFT 20 +#define DDR_PHY_DX4GCR0_RDDLY_MASK 0x00F00000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX4GCR0_RESERVED_19_14_DEFVAL #undef DDR_PHY_DX4GCR0_RESERVED_19_14_SHIFT #undef DDR_PHY_DX4GCR0_RESERVED_19_14_MASK -#define DDR_PHY_DX4GCR0_RESERVED_19_14_DEFVAL 0x40200204 -#define DDR_PHY_DX4GCR0_RESERVED_19_14_SHIFT 14 -#define DDR_PHY_DX4GCR0_RESERVED_19_14_MASK 0x000FC000U +#define DDR_PHY_DX4GCR0_RESERVED_19_14_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_RESERVED_19_14_SHIFT 14 +#define DDR_PHY_DX4GCR0_RESERVED_19_14_MASK 0x000FC000U -/*DQSNSE Power Down Receiver*/ +/* +* DQSNSE Power Down Receiver +*/ #undef DDR_PHY_DX4GCR0_DQSNSEPDR_DEFVAL #undef DDR_PHY_DX4GCR0_DQSNSEPDR_SHIFT #undef DDR_PHY_DX4GCR0_DQSNSEPDR_MASK -#define DDR_PHY_DX4GCR0_DQSNSEPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX4GCR0_DQSNSEPDR_SHIFT 13 -#define DDR_PHY_DX4GCR0_DQSNSEPDR_MASK 0x00002000U +#define DDR_PHY_DX4GCR0_DQSNSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_DQSNSEPDR_SHIFT 13 +#define DDR_PHY_DX4GCR0_DQSNSEPDR_MASK 0x00002000U -/*DQSSE Power Down Receiver*/ +/* +* DQSSE Power Down Receiver +*/ #undef DDR_PHY_DX4GCR0_DQSSEPDR_DEFVAL #undef DDR_PHY_DX4GCR0_DQSSEPDR_SHIFT #undef DDR_PHY_DX4GCR0_DQSSEPDR_MASK -#define DDR_PHY_DX4GCR0_DQSSEPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX4GCR0_DQSSEPDR_SHIFT 12 -#define DDR_PHY_DX4GCR0_DQSSEPDR_MASK 0x00001000U +#define DDR_PHY_DX4GCR0_DQSSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_DQSSEPDR_SHIFT 12 +#define DDR_PHY_DX4GCR0_DQSSEPDR_MASK 0x00001000U -/*RTT On Additive Latency*/ +/* +* RTT On Additive Latency +*/ #undef DDR_PHY_DX4GCR0_RTTOAL_DEFVAL #undef DDR_PHY_DX4GCR0_RTTOAL_SHIFT #undef DDR_PHY_DX4GCR0_RTTOAL_MASK -#define DDR_PHY_DX4GCR0_RTTOAL_DEFVAL 0x40200204 -#define DDR_PHY_DX4GCR0_RTTOAL_SHIFT 11 -#define DDR_PHY_DX4GCR0_RTTOAL_MASK 0x00000800U +#define DDR_PHY_DX4GCR0_RTTOAL_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_RTTOAL_SHIFT 11 +#define DDR_PHY_DX4GCR0_RTTOAL_MASK 0x00000800U -/*RTT Output Hold*/ +/* +* RTT Output Hold +*/ #undef DDR_PHY_DX4GCR0_RTTOH_DEFVAL #undef DDR_PHY_DX4GCR0_RTTOH_SHIFT #undef DDR_PHY_DX4GCR0_RTTOH_MASK -#define DDR_PHY_DX4GCR0_RTTOH_DEFVAL 0x40200204 -#define DDR_PHY_DX4GCR0_RTTOH_SHIFT 9 -#define DDR_PHY_DX4GCR0_RTTOH_MASK 0x00000600U +#define DDR_PHY_DX4GCR0_RTTOH_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_RTTOH_SHIFT 9 +#define DDR_PHY_DX4GCR0_RTTOH_MASK 0x00000600U -/*Configurable PDR Phase Shift*/ +/* +* Configurable PDR Phase Shift +*/ #undef DDR_PHY_DX4GCR0_CPDRSHFT_DEFVAL #undef DDR_PHY_DX4GCR0_CPDRSHFT_SHIFT #undef DDR_PHY_DX4GCR0_CPDRSHFT_MASK -#define DDR_PHY_DX4GCR0_CPDRSHFT_DEFVAL 0x40200204 -#define DDR_PHY_DX4GCR0_CPDRSHFT_SHIFT 7 -#define DDR_PHY_DX4GCR0_CPDRSHFT_MASK 0x00000180U +#define DDR_PHY_DX4GCR0_CPDRSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_CPDRSHFT_SHIFT 7 +#define DDR_PHY_DX4GCR0_CPDRSHFT_MASK 0x00000180U -/*DQSR Power Down*/ +/* +* DQSR Power Down +*/ #undef DDR_PHY_DX4GCR0_DQSRPD_DEFVAL #undef DDR_PHY_DX4GCR0_DQSRPD_SHIFT #undef DDR_PHY_DX4GCR0_DQSRPD_MASK -#define DDR_PHY_DX4GCR0_DQSRPD_DEFVAL 0x40200204 -#define DDR_PHY_DX4GCR0_DQSRPD_SHIFT 6 -#define DDR_PHY_DX4GCR0_DQSRPD_MASK 0x00000040U +#define DDR_PHY_DX4GCR0_DQSRPD_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_DQSRPD_SHIFT 6 +#define DDR_PHY_DX4GCR0_DQSRPD_MASK 0x00000040U -/*DQSG Power Down Receiver*/ +/* +* DQSG Power Down Receiver +*/ #undef DDR_PHY_DX4GCR0_DQSGPDR_DEFVAL #undef DDR_PHY_DX4GCR0_DQSGPDR_SHIFT #undef DDR_PHY_DX4GCR0_DQSGPDR_MASK -#define DDR_PHY_DX4GCR0_DQSGPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX4GCR0_DQSGPDR_SHIFT 5 -#define DDR_PHY_DX4GCR0_DQSGPDR_MASK 0x00000020U +#define DDR_PHY_DX4GCR0_DQSGPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_DQSGPDR_SHIFT 5 +#define DDR_PHY_DX4GCR0_DQSGPDR_MASK 0x00000020U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX4GCR0_RESERVED_4_DEFVAL #undef DDR_PHY_DX4GCR0_RESERVED_4_SHIFT #undef DDR_PHY_DX4GCR0_RESERVED_4_MASK -#define DDR_PHY_DX4GCR0_RESERVED_4_DEFVAL 0x40200204 -#define DDR_PHY_DX4GCR0_RESERVED_4_SHIFT 4 -#define DDR_PHY_DX4GCR0_RESERVED_4_MASK 0x00000010U +#define DDR_PHY_DX4GCR0_RESERVED_4_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_RESERVED_4_SHIFT 4 +#define DDR_PHY_DX4GCR0_RESERVED_4_MASK 0x00000010U -/*DQSG On-Die Termination*/ +/* +* DQSG On-Die Termination +*/ #undef DDR_PHY_DX4GCR0_DQSGODT_DEFVAL #undef DDR_PHY_DX4GCR0_DQSGODT_SHIFT #undef DDR_PHY_DX4GCR0_DQSGODT_MASK -#define DDR_PHY_DX4GCR0_DQSGODT_DEFVAL 0x40200204 -#define DDR_PHY_DX4GCR0_DQSGODT_SHIFT 3 -#define DDR_PHY_DX4GCR0_DQSGODT_MASK 0x00000008U +#define DDR_PHY_DX4GCR0_DQSGODT_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_DQSGODT_SHIFT 3 +#define DDR_PHY_DX4GCR0_DQSGODT_MASK 0x00000008U -/*DQSG Output Enable*/ +/* +* DQSG Output Enable +*/ #undef DDR_PHY_DX4GCR0_DQSGOE_DEFVAL #undef DDR_PHY_DX4GCR0_DQSGOE_SHIFT #undef DDR_PHY_DX4GCR0_DQSGOE_MASK -#define DDR_PHY_DX4GCR0_DQSGOE_DEFVAL 0x40200204 -#define DDR_PHY_DX4GCR0_DQSGOE_SHIFT 2 -#define DDR_PHY_DX4GCR0_DQSGOE_MASK 0x00000004U +#define DDR_PHY_DX4GCR0_DQSGOE_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_DQSGOE_SHIFT 2 +#define DDR_PHY_DX4GCR0_DQSGOE_MASK 0x00000004U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX4GCR0_RESERVED_1_0_DEFVAL #undef DDR_PHY_DX4GCR0_RESERVED_1_0_SHIFT #undef DDR_PHY_DX4GCR0_RESERVED_1_0_MASK -#define DDR_PHY_DX4GCR0_RESERVED_1_0_DEFVAL 0x40200204 -#define DDR_PHY_DX4GCR0_RESERVED_1_0_SHIFT 0 -#define DDR_PHY_DX4GCR0_RESERVED_1_0_MASK 0x00000003U +#define DDR_PHY_DX4GCR0_RESERVED_1_0_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_RESERVED_1_0_SHIFT 0 +#define DDR_PHY_DX4GCR0_RESERVED_1_0_MASK 0x00000003U -/*Enables the PDR mode for DQ[7:0]*/ +/* +* Enables the PDR mode for DQ[7:0] +*/ #undef DDR_PHY_DX4GCR1_DXPDRMODE_DEFVAL #undef DDR_PHY_DX4GCR1_DXPDRMODE_SHIFT #undef DDR_PHY_DX4GCR1_DXPDRMODE_MASK -#define DDR_PHY_DX4GCR1_DXPDRMODE_DEFVAL 0x00007FFF -#define DDR_PHY_DX4GCR1_DXPDRMODE_SHIFT 16 -#define DDR_PHY_DX4GCR1_DXPDRMODE_MASK 0xFFFF0000U +#define DDR_PHY_DX4GCR1_DXPDRMODE_DEFVAL 0x00007FFF +#define DDR_PHY_DX4GCR1_DXPDRMODE_SHIFT 16 +#define DDR_PHY_DX4GCR1_DXPDRMODE_MASK 0xFFFF0000U -/*Reserved. Returns zeroes on reads.*/ +/* +* Reserved. Returns zeroes on reads. +*/ #undef DDR_PHY_DX4GCR1_RESERVED_15_DEFVAL #undef DDR_PHY_DX4GCR1_RESERVED_15_SHIFT #undef DDR_PHY_DX4GCR1_RESERVED_15_MASK -#define DDR_PHY_DX4GCR1_RESERVED_15_DEFVAL 0x00007FFF -#define DDR_PHY_DX4GCR1_RESERVED_15_SHIFT 15 -#define DDR_PHY_DX4GCR1_RESERVED_15_MASK 0x00008000U +#define DDR_PHY_DX4GCR1_RESERVED_15_DEFVAL 0x00007FFF +#define DDR_PHY_DX4GCR1_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX4GCR1_RESERVED_15_MASK 0x00008000U -/*Select the delayed or non-delayed read data strobe #*/ +/* +* Select the delayed or non-delayed read data strobe # +*/ #undef DDR_PHY_DX4GCR1_QSNSEL_DEFVAL #undef DDR_PHY_DX4GCR1_QSNSEL_SHIFT #undef DDR_PHY_DX4GCR1_QSNSEL_MASK -#define DDR_PHY_DX4GCR1_QSNSEL_DEFVAL 0x00007FFF -#define DDR_PHY_DX4GCR1_QSNSEL_SHIFT 14 -#define DDR_PHY_DX4GCR1_QSNSEL_MASK 0x00004000U +#define DDR_PHY_DX4GCR1_QSNSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX4GCR1_QSNSEL_SHIFT 14 +#define DDR_PHY_DX4GCR1_QSNSEL_MASK 0x00004000U -/*Select the delayed or non-delayed read data strobe*/ +/* +* Select the delayed or non-delayed read data strobe +*/ #undef DDR_PHY_DX4GCR1_QSSEL_DEFVAL #undef DDR_PHY_DX4GCR1_QSSEL_SHIFT #undef DDR_PHY_DX4GCR1_QSSEL_MASK -#define DDR_PHY_DX4GCR1_QSSEL_DEFVAL 0x00007FFF -#define DDR_PHY_DX4GCR1_QSSEL_SHIFT 13 -#define DDR_PHY_DX4GCR1_QSSEL_MASK 0x00002000U +#define DDR_PHY_DX4GCR1_QSSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX4GCR1_QSSEL_SHIFT 13 +#define DDR_PHY_DX4GCR1_QSSEL_MASK 0x00002000U -/*Enables Read Data Strobe in a byte lane*/ +/* +* Enables Read Data Strobe in a byte lane +*/ #undef DDR_PHY_DX4GCR1_OEEN_DEFVAL #undef DDR_PHY_DX4GCR1_OEEN_SHIFT #undef DDR_PHY_DX4GCR1_OEEN_MASK -#define DDR_PHY_DX4GCR1_OEEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX4GCR1_OEEN_SHIFT 12 -#define DDR_PHY_DX4GCR1_OEEN_MASK 0x00001000U +#define DDR_PHY_DX4GCR1_OEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX4GCR1_OEEN_SHIFT 12 +#define DDR_PHY_DX4GCR1_OEEN_MASK 0x00001000U -/*Enables PDR in a byte lane*/ +/* +* Enables PDR in a byte lane +*/ #undef DDR_PHY_DX4GCR1_PDREN_DEFVAL #undef DDR_PHY_DX4GCR1_PDREN_SHIFT #undef DDR_PHY_DX4GCR1_PDREN_MASK -#define DDR_PHY_DX4GCR1_PDREN_DEFVAL 0x00007FFF -#define DDR_PHY_DX4GCR1_PDREN_SHIFT 11 -#define DDR_PHY_DX4GCR1_PDREN_MASK 0x00000800U +#define DDR_PHY_DX4GCR1_PDREN_DEFVAL 0x00007FFF +#define DDR_PHY_DX4GCR1_PDREN_SHIFT 11 +#define DDR_PHY_DX4GCR1_PDREN_MASK 0x00000800U -/*Enables ODT/TE in a byte lane*/ +/* +* Enables ODT/TE in a byte lane +*/ #undef DDR_PHY_DX4GCR1_TEEN_DEFVAL #undef DDR_PHY_DX4GCR1_TEEN_SHIFT #undef DDR_PHY_DX4GCR1_TEEN_MASK -#define DDR_PHY_DX4GCR1_TEEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX4GCR1_TEEN_SHIFT 10 -#define DDR_PHY_DX4GCR1_TEEN_MASK 0x00000400U +#define DDR_PHY_DX4GCR1_TEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX4GCR1_TEEN_SHIFT 10 +#define DDR_PHY_DX4GCR1_TEEN_MASK 0x00000400U -/*Enables Write Data strobe in a byte lane*/ +/* +* Enables Write Data strobe in a byte lane +*/ #undef DDR_PHY_DX4GCR1_DSEN_DEFVAL #undef DDR_PHY_DX4GCR1_DSEN_SHIFT #undef DDR_PHY_DX4GCR1_DSEN_MASK -#define DDR_PHY_DX4GCR1_DSEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX4GCR1_DSEN_SHIFT 9 -#define DDR_PHY_DX4GCR1_DSEN_MASK 0x00000200U +#define DDR_PHY_DX4GCR1_DSEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX4GCR1_DSEN_SHIFT 9 +#define DDR_PHY_DX4GCR1_DSEN_MASK 0x00000200U -/*Enables DM pin in a byte lane*/ +/* +* Enables DM pin in a byte lane +*/ #undef DDR_PHY_DX4GCR1_DMEN_DEFVAL #undef DDR_PHY_DX4GCR1_DMEN_SHIFT #undef DDR_PHY_DX4GCR1_DMEN_MASK -#define DDR_PHY_DX4GCR1_DMEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX4GCR1_DMEN_SHIFT 8 -#define DDR_PHY_DX4GCR1_DMEN_MASK 0x00000100U +#define DDR_PHY_DX4GCR1_DMEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX4GCR1_DMEN_SHIFT 8 +#define DDR_PHY_DX4GCR1_DMEN_MASK 0x00000100U -/*Enables DQ corresponding to each bit in a byte*/ +/* +* Enables DQ corresponding to each bit in a byte +*/ #undef DDR_PHY_DX4GCR1_DQEN_DEFVAL #undef DDR_PHY_DX4GCR1_DQEN_SHIFT #undef DDR_PHY_DX4GCR1_DQEN_MASK -#define DDR_PHY_DX4GCR1_DQEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX4GCR1_DQEN_SHIFT 0 -#define DDR_PHY_DX4GCR1_DQEN_MASK 0x000000FFU +#define DDR_PHY_DX4GCR1_DQEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX4GCR1_DQEN_SHIFT 0 +#define DDR_PHY_DX4GCR1_DQEN_MASK 0x000000FFU -/*Byte lane VREF IOM (Used only by D4MU IOs)*/ +/* +* Byte lane VREF IOM (Used only by D4MU IOs) +*/ #undef DDR_PHY_DX4GCR4_RESERVED_31_29_DEFVAL #undef DDR_PHY_DX4GCR4_RESERVED_31_29_SHIFT #undef DDR_PHY_DX4GCR4_RESERVED_31_29_MASK -#define DDR_PHY_DX4GCR4_RESERVED_31_29_DEFVAL 0x0E00003C -#define DDR_PHY_DX4GCR4_RESERVED_31_29_SHIFT 29 -#define DDR_PHY_DX4GCR4_RESERVED_31_29_MASK 0xE0000000U +#define DDR_PHY_DX4GCR4_RESERVED_31_29_DEFVAL 0x0E00003C +#define DDR_PHY_DX4GCR4_RESERVED_31_29_SHIFT 29 +#define DDR_PHY_DX4GCR4_RESERVED_31_29_MASK 0xE0000000U -/*Byte Lane VREF Pad Enable*/ +/* +* Byte Lane VREF Pad Enable +*/ #undef DDR_PHY_DX4GCR4_DXREFPEN_DEFVAL #undef DDR_PHY_DX4GCR4_DXREFPEN_SHIFT #undef DDR_PHY_DX4GCR4_DXREFPEN_MASK -#define DDR_PHY_DX4GCR4_DXREFPEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX4GCR4_DXREFPEN_SHIFT 28 -#define DDR_PHY_DX4GCR4_DXREFPEN_MASK 0x10000000U +#define DDR_PHY_DX4GCR4_DXREFPEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX4GCR4_DXREFPEN_SHIFT 28 +#define DDR_PHY_DX4GCR4_DXREFPEN_MASK 0x10000000U -/*Byte Lane Internal VREF Enable*/ +/* +* Byte Lane Internal VREF Enable +*/ #undef DDR_PHY_DX4GCR4_DXREFEEN_DEFVAL #undef DDR_PHY_DX4GCR4_DXREFEEN_SHIFT #undef DDR_PHY_DX4GCR4_DXREFEEN_MASK -#define DDR_PHY_DX4GCR4_DXREFEEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX4GCR4_DXREFEEN_SHIFT 26 -#define DDR_PHY_DX4GCR4_DXREFEEN_MASK 0x0C000000U +#define DDR_PHY_DX4GCR4_DXREFEEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX4GCR4_DXREFEEN_SHIFT 26 +#define DDR_PHY_DX4GCR4_DXREFEEN_MASK 0x0C000000U -/*Byte Lane Single-End VREF Enable*/ +/* +* Byte Lane Single-End VREF Enable +*/ #undef DDR_PHY_DX4GCR4_DXREFSEN_DEFVAL #undef DDR_PHY_DX4GCR4_DXREFSEN_SHIFT #undef DDR_PHY_DX4GCR4_DXREFSEN_MASK -#define DDR_PHY_DX4GCR4_DXREFSEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX4GCR4_DXREFSEN_SHIFT 25 -#define DDR_PHY_DX4GCR4_DXREFSEN_MASK 0x02000000U +#define DDR_PHY_DX4GCR4_DXREFSEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX4GCR4_DXREFSEN_SHIFT 25 +#define DDR_PHY_DX4GCR4_DXREFSEN_MASK 0x02000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX4GCR4_RESERVED_24_DEFVAL #undef DDR_PHY_DX4GCR4_RESERVED_24_SHIFT #undef DDR_PHY_DX4GCR4_RESERVED_24_MASK -#define DDR_PHY_DX4GCR4_RESERVED_24_DEFVAL 0x0E00003C -#define DDR_PHY_DX4GCR4_RESERVED_24_SHIFT 24 -#define DDR_PHY_DX4GCR4_RESERVED_24_MASK 0x01000000U +#define DDR_PHY_DX4GCR4_RESERVED_24_DEFVAL 0x0E00003C +#define DDR_PHY_DX4GCR4_RESERVED_24_SHIFT 24 +#define DDR_PHY_DX4GCR4_RESERVED_24_MASK 0x01000000U -/*External VREF generator REFSEL range select*/ +/* +* External VREF generator REFSEL range select +*/ #undef DDR_PHY_DX4GCR4_DXREFESELRANGE_DEFVAL #undef DDR_PHY_DX4GCR4_DXREFESELRANGE_SHIFT #undef DDR_PHY_DX4GCR4_DXREFESELRANGE_MASK -#define DDR_PHY_DX4GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C -#define DDR_PHY_DX4GCR4_DXREFESELRANGE_SHIFT 23 -#define DDR_PHY_DX4GCR4_DXREFESELRANGE_MASK 0x00800000U +#define DDR_PHY_DX4GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX4GCR4_DXREFESELRANGE_SHIFT 23 +#define DDR_PHY_DX4GCR4_DXREFESELRANGE_MASK 0x00800000U -/*Byte Lane External VREF Select*/ +/* +* Byte Lane External VREF Select +*/ #undef DDR_PHY_DX4GCR4_DXREFESEL_DEFVAL #undef DDR_PHY_DX4GCR4_DXREFESEL_SHIFT #undef DDR_PHY_DX4GCR4_DXREFESEL_MASK -#define DDR_PHY_DX4GCR4_DXREFESEL_DEFVAL 0x0E00003C -#define DDR_PHY_DX4GCR4_DXREFESEL_SHIFT 16 -#define DDR_PHY_DX4GCR4_DXREFESEL_MASK 0x007F0000U +#define DDR_PHY_DX4GCR4_DXREFESEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX4GCR4_DXREFESEL_SHIFT 16 +#define DDR_PHY_DX4GCR4_DXREFESEL_MASK 0x007F0000U -/*Single ended VREF generator REFSEL range select*/ +/* +* Single ended VREF generator REFSEL range select +*/ #undef DDR_PHY_DX4GCR4_DXREFSSELRANGE_DEFVAL #undef DDR_PHY_DX4GCR4_DXREFSSELRANGE_SHIFT #undef DDR_PHY_DX4GCR4_DXREFSSELRANGE_MASK -#define DDR_PHY_DX4GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C -#define DDR_PHY_DX4GCR4_DXREFSSELRANGE_SHIFT 15 -#define DDR_PHY_DX4GCR4_DXREFSSELRANGE_MASK 0x00008000U +#define DDR_PHY_DX4GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX4GCR4_DXREFSSELRANGE_SHIFT 15 +#define DDR_PHY_DX4GCR4_DXREFSSELRANGE_MASK 0x00008000U -/*Byte Lane Single-End VREF Select*/ +/* +* Byte Lane Single-End VREF Select +*/ #undef DDR_PHY_DX4GCR4_DXREFSSEL_DEFVAL #undef DDR_PHY_DX4GCR4_DXREFSSEL_SHIFT #undef DDR_PHY_DX4GCR4_DXREFSSEL_MASK -#define DDR_PHY_DX4GCR4_DXREFSSEL_DEFVAL 0x0E00003C -#define DDR_PHY_DX4GCR4_DXREFSSEL_SHIFT 8 -#define DDR_PHY_DX4GCR4_DXREFSSEL_MASK 0x00007F00U +#define DDR_PHY_DX4GCR4_DXREFSSEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX4GCR4_DXREFSSEL_SHIFT 8 +#define DDR_PHY_DX4GCR4_DXREFSSEL_MASK 0x00007F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX4GCR4_RESERVED_7_6_DEFVAL #undef DDR_PHY_DX4GCR4_RESERVED_7_6_SHIFT #undef DDR_PHY_DX4GCR4_RESERVED_7_6_MASK -#define DDR_PHY_DX4GCR4_RESERVED_7_6_DEFVAL 0x0E00003C -#define DDR_PHY_DX4GCR4_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_DX4GCR4_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_DX4GCR4_RESERVED_7_6_DEFVAL 0x0E00003C +#define DDR_PHY_DX4GCR4_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX4GCR4_RESERVED_7_6_MASK 0x000000C0U -/*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/ +/* +* VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. +*/ #undef DDR_PHY_DX4GCR4_DXREFIEN_DEFVAL #undef DDR_PHY_DX4GCR4_DXREFIEN_SHIFT #undef DDR_PHY_DX4GCR4_DXREFIEN_MASK -#define DDR_PHY_DX4GCR4_DXREFIEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX4GCR4_DXREFIEN_SHIFT 2 -#define DDR_PHY_DX4GCR4_DXREFIEN_MASK 0x0000003CU +#define DDR_PHY_DX4GCR4_DXREFIEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX4GCR4_DXREFIEN_SHIFT 2 +#define DDR_PHY_DX4GCR4_DXREFIEN_MASK 0x0000003CU -/*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/ +/* +* VRMON control for DQ IO (Single Ended) buffers of a byte lane. +*/ #undef DDR_PHY_DX4GCR4_DXREFIMON_DEFVAL #undef DDR_PHY_DX4GCR4_DXREFIMON_SHIFT #undef DDR_PHY_DX4GCR4_DXREFIMON_MASK -#define DDR_PHY_DX4GCR4_DXREFIMON_DEFVAL 0x0E00003C -#define DDR_PHY_DX4GCR4_DXREFIMON_SHIFT 0 -#define DDR_PHY_DX4GCR4_DXREFIMON_MASK 0x00000003U +#define DDR_PHY_DX4GCR4_DXREFIMON_DEFVAL 0x0E00003C +#define DDR_PHY_DX4GCR4_DXREFIMON_SHIFT 0 +#define DDR_PHY_DX4GCR4_DXREFIMON_MASK 0x00000003U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX4GCR5_RESERVED_31_DEFVAL #undef DDR_PHY_DX4GCR5_RESERVED_31_SHIFT #undef DDR_PHY_DX4GCR5_RESERVED_31_MASK -#define DDR_PHY_DX4GCR5_RESERVED_31_DEFVAL 0x09090909 -#define DDR_PHY_DX4GCR5_RESERVED_31_SHIFT 31 -#define DDR_PHY_DX4GCR5_RESERVED_31_MASK 0x80000000U +#define DDR_PHY_DX4GCR5_RESERVED_31_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR5_RESERVED_31_SHIFT 31 +#define DDR_PHY_DX4GCR5_RESERVED_31_MASK 0x80000000U -/*Byte Lane internal VREF Select for Rank 3*/ +/* +* Byte Lane internal VREF Select for Rank 3 +*/ #undef DDR_PHY_DX4GCR5_DXREFISELR3_DEFVAL #undef DDR_PHY_DX4GCR5_DXREFISELR3_SHIFT #undef DDR_PHY_DX4GCR5_DXREFISELR3_MASK -#define DDR_PHY_DX4GCR5_DXREFISELR3_DEFVAL 0x09090909 -#define DDR_PHY_DX4GCR5_DXREFISELR3_SHIFT 24 -#define DDR_PHY_DX4GCR5_DXREFISELR3_MASK 0x7F000000U +#define DDR_PHY_DX4GCR5_DXREFISELR3_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR5_DXREFISELR3_SHIFT 24 +#define DDR_PHY_DX4GCR5_DXREFISELR3_MASK 0x7F000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX4GCR5_RESERVED_23_DEFVAL #undef DDR_PHY_DX4GCR5_RESERVED_23_SHIFT #undef DDR_PHY_DX4GCR5_RESERVED_23_MASK -#define DDR_PHY_DX4GCR5_RESERVED_23_DEFVAL 0x09090909 -#define DDR_PHY_DX4GCR5_RESERVED_23_SHIFT 23 -#define DDR_PHY_DX4GCR5_RESERVED_23_MASK 0x00800000U +#define DDR_PHY_DX4GCR5_RESERVED_23_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR5_RESERVED_23_SHIFT 23 +#define DDR_PHY_DX4GCR5_RESERVED_23_MASK 0x00800000U -/*Byte Lane internal VREF Select for Rank 2*/ +/* +* Byte Lane internal VREF Select for Rank 2 +*/ #undef DDR_PHY_DX4GCR5_DXREFISELR2_DEFVAL #undef DDR_PHY_DX4GCR5_DXREFISELR2_SHIFT #undef DDR_PHY_DX4GCR5_DXREFISELR2_MASK -#define DDR_PHY_DX4GCR5_DXREFISELR2_DEFVAL 0x09090909 -#define DDR_PHY_DX4GCR5_DXREFISELR2_SHIFT 16 -#define DDR_PHY_DX4GCR5_DXREFISELR2_MASK 0x007F0000U +#define DDR_PHY_DX4GCR5_DXREFISELR2_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR5_DXREFISELR2_SHIFT 16 +#define DDR_PHY_DX4GCR5_DXREFISELR2_MASK 0x007F0000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX4GCR5_RESERVED_15_DEFVAL #undef DDR_PHY_DX4GCR5_RESERVED_15_SHIFT #undef DDR_PHY_DX4GCR5_RESERVED_15_MASK -#define DDR_PHY_DX4GCR5_RESERVED_15_DEFVAL 0x09090909 -#define DDR_PHY_DX4GCR5_RESERVED_15_SHIFT 15 -#define DDR_PHY_DX4GCR5_RESERVED_15_MASK 0x00008000U +#define DDR_PHY_DX4GCR5_RESERVED_15_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR5_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX4GCR5_RESERVED_15_MASK 0x00008000U -/*Byte Lane internal VREF Select for Rank 1*/ +/* +* Byte Lane internal VREF Select for Rank 1 +*/ #undef DDR_PHY_DX4GCR5_DXREFISELR1_DEFVAL #undef DDR_PHY_DX4GCR5_DXREFISELR1_SHIFT #undef DDR_PHY_DX4GCR5_DXREFISELR1_MASK -#define DDR_PHY_DX4GCR5_DXREFISELR1_DEFVAL 0x09090909 -#define DDR_PHY_DX4GCR5_DXREFISELR1_SHIFT 8 -#define DDR_PHY_DX4GCR5_DXREFISELR1_MASK 0x00007F00U +#define DDR_PHY_DX4GCR5_DXREFISELR1_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR5_DXREFISELR1_SHIFT 8 +#define DDR_PHY_DX4GCR5_DXREFISELR1_MASK 0x00007F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX4GCR5_RESERVED_7_DEFVAL #undef DDR_PHY_DX4GCR5_RESERVED_7_SHIFT #undef DDR_PHY_DX4GCR5_RESERVED_7_MASK -#define DDR_PHY_DX4GCR5_RESERVED_7_DEFVAL 0x09090909 -#define DDR_PHY_DX4GCR5_RESERVED_7_SHIFT 7 -#define DDR_PHY_DX4GCR5_RESERVED_7_MASK 0x00000080U +#define DDR_PHY_DX4GCR5_RESERVED_7_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR5_RESERVED_7_SHIFT 7 +#define DDR_PHY_DX4GCR5_RESERVED_7_MASK 0x00000080U -/*Byte Lane internal VREF Select for Rank 0*/ +/* +* Byte Lane internal VREF Select for Rank 0 +*/ #undef DDR_PHY_DX4GCR5_DXREFISELR0_DEFVAL #undef DDR_PHY_DX4GCR5_DXREFISELR0_SHIFT #undef DDR_PHY_DX4GCR5_DXREFISELR0_MASK -#define DDR_PHY_DX4GCR5_DXREFISELR0_DEFVAL 0x09090909 -#define DDR_PHY_DX4GCR5_DXREFISELR0_SHIFT 0 -#define DDR_PHY_DX4GCR5_DXREFISELR0_MASK 0x0000007FU +#define DDR_PHY_DX4GCR5_DXREFISELR0_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR5_DXREFISELR0_SHIFT 0 +#define DDR_PHY_DX4GCR5_DXREFISELR0_MASK 0x0000007FU -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX4GCR6_RESERVED_31_30_DEFVAL #undef DDR_PHY_DX4GCR6_RESERVED_31_30_SHIFT #undef DDR_PHY_DX4GCR6_RESERVED_31_30_MASK -#define DDR_PHY_DX4GCR6_RESERVED_31_30_DEFVAL 0x09090909 -#define DDR_PHY_DX4GCR6_RESERVED_31_30_SHIFT 30 -#define DDR_PHY_DX4GCR6_RESERVED_31_30_MASK 0xC0000000U +#define DDR_PHY_DX4GCR6_RESERVED_31_30_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR6_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX4GCR6_RESERVED_31_30_MASK 0xC0000000U -/*DRAM DQ VREF Select for Rank3*/ +/* +* DRAM DQ VREF Select for Rank3 +*/ #undef DDR_PHY_DX4GCR6_DXDQVREFR3_DEFVAL #undef DDR_PHY_DX4GCR6_DXDQVREFR3_SHIFT #undef DDR_PHY_DX4GCR6_DXDQVREFR3_MASK -#define DDR_PHY_DX4GCR6_DXDQVREFR3_DEFVAL 0x09090909 -#define DDR_PHY_DX4GCR6_DXDQVREFR3_SHIFT 24 -#define DDR_PHY_DX4GCR6_DXDQVREFR3_MASK 0x3F000000U +#define DDR_PHY_DX4GCR6_DXDQVREFR3_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR6_DXDQVREFR3_SHIFT 24 +#define DDR_PHY_DX4GCR6_DXDQVREFR3_MASK 0x3F000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX4GCR6_RESERVED_23_22_DEFVAL #undef DDR_PHY_DX4GCR6_RESERVED_23_22_SHIFT #undef DDR_PHY_DX4GCR6_RESERVED_23_22_MASK -#define DDR_PHY_DX4GCR6_RESERVED_23_22_DEFVAL 0x09090909 -#define DDR_PHY_DX4GCR6_RESERVED_23_22_SHIFT 22 -#define DDR_PHY_DX4GCR6_RESERVED_23_22_MASK 0x00C00000U +#define DDR_PHY_DX4GCR6_RESERVED_23_22_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR6_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX4GCR6_RESERVED_23_22_MASK 0x00C00000U -/*DRAM DQ VREF Select for Rank2*/ +/* +* DRAM DQ VREF Select for Rank2 +*/ #undef DDR_PHY_DX4GCR6_DXDQVREFR2_DEFVAL #undef DDR_PHY_DX4GCR6_DXDQVREFR2_SHIFT #undef DDR_PHY_DX4GCR6_DXDQVREFR2_MASK -#define DDR_PHY_DX4GCR6_DXDQVREFR2_DEFVAL 0x09090909 -#define DDR_PHY_DX4GCR6_DXDQVREFR2_SHIFT 16 -#define DDR_PHY_DX4GCR6_DXDQVREFR2_MASK 0x003F0000U +#define DDR_PHY_DX4GCR6_DXDQVREFR2_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR6_DXDQVREFR2_SHIFT 16 +#define DDR_PHY_DX4GCR6_DXDQVREFR2_MASK 0x003F0000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX4GCR6_RESERVED_15_14_DEFVAL #undef DDR_PHY_DX4GCR6_RESERVED_15_14_SHIFT #undef DDR_PHY_DX4GCR6_RESERVED_15_14_MASK -#define DDR_PHY_DX4GCR6_RESERVED_15_14_DEFVAL 0x09090909 -#define DDR_PHY_DX4GCR6_RESERVED_15_14_SHIFT 14 -#define DDR_PHY_DX4GCR6_RESERVED_15_14_MASK 0x0000C000U +#define DDR_PHY_DX4GCR6_RESERVED_15_14_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR6_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_DX4GCR6_RESERVED_15_14_MASK 0x0000C000U -/*DRAM DQ VREF Select for Rank1*/ +/* +* DRAM DQ VREF Select for Rank1 +*/ #undef DDR_PHY_DX4GCR6_DXDQVREFR1_DEFVAL #undef DDR_PHY_DX4GCR6_DXDQVREFR1_SHIFT #undef DDR_PHY_DX4GCR6_DXDQVREFR1_MASK -#define DDR_PHY_DX4GCR6_DXDQVREFR1_DEFVAL 0x09090909 -#define DDR_PHY_DX4GCR6_DXDQVREFR1_SHIFT 8 -#define DDR_PHY_DX4GCR6_DXDQVREFR1_MASK 0x00003F00U +#define DDR_PHY_DX4GCR6_DXDQVREFR1_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR6_DXDQVREFR1_SHIFT 8 +#define DDR_PHY_DX4GCR6_DXDQVREFR1_MASK 0x00003F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX4GCR6_RESERVED_7_6_DEFVAL #undef DDR_PHY_DX4GCR6_RESERVED_7_6_SHIFT #undef DDR_PHY_DX4GCR6_RESERVED_7_6_MASK -#define DDR_PHY_DX4GCR6_RESERVED_7_6_DEFVAL 0x09090909 -#define DDR_PHY_DX4GCR6_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_DX4GCR6_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_DX4GCR6_RESERVED_7_6_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR6_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX4GCR6_RESERVED_7_6_MASK 0x000000C0U -/*DRAM DQ VREF Select for Rank0*/ +/* +* DRAM DQ VREF Select for Rank0 +*/ #undef DDR_PHY_DX4GCR6_DXDQVREFR0_DEFVAL #undef DDR_PHY_DX4GCR6_DXDQVREFR0_SHIFT #undef DDR_PHY_DX4GCR6_DXDQVREFR0_MASK -#define DDR_PHY_DX4GCR6_DXDQVREFR0_DEFVAL 0x09090909 -#define DDR_PHY_DX4GCR6_DXDQVREFR0_SHIFT 0 -#define DDR_PHY_DX4GCR6_DXDQVREFR0_MASK 0x0000003FU +#define DDR_PHY_DX4GCR6_DXDQVREFR0_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR6_DXDQVREFR0_SHIFT 0 +#define DDR_PHY_DX4GCR6_DXDQVREFR0_MASK 0x0000003FU -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX4LCDLR2_RESERVED_31_25_DEFVAL -#undef DDR_PHY_DX4LCDLR2_RESERVED_31_25_SHIFT -#undef DDR_PHY_DX4LCDLR2_RESERVED_31_25_MASK -#define DDR_PHY_DX4LCDLR2_RESERVED_31_25_DEFVAL 0x00000000 -#define DDR_PHY_DX4LCDLR2_RESERVED_31_25_SHIFT 25 -#define DDR_PHY_DX4LCDLR2_RESERVED_31_25_MASK 0xFE000000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX4LCDLR2_RESERVED_24_16_DEFVAL -#undef DDR_PHY_DX4LCDLR2_RESERVED_24_16_SHIFT -#undef DDR_PHY_DX4LCDLR2_RESERVED_24_16_MASK -#define DDR_PHY_DX4LCDLR2_RESERVED_24_16_DEFVAL 0x00000000 -#define DDR_PHY_DX4LCDLR2_RESERVED_24_16_SHIFT 16 -#define DDR_PHY_DX4LCDLR2_RESERVED_24_16_MASK 0x01FF0000U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX4LCDLR2_RESERVED_15_9_DEFVAL -#undef DDR_PHY_DX4LCDLR2_RESERVED_15_9_SHIFT -#undef DDR_PHY_DX4LCDLR2_RESERVED_15_9_MASK -#define DDR_PHY_DX4LCDLR2_RESERVED_15_9_DEFVAL 0x00000000 -#define DDR_PHY_DX4LCDLR2_RESERVED_15_9_SHIFT 9 -#define DDR_PHY_DX4LCDLR2_RESERVED_15_9_MASK 0x0000FE00U - -/*Read DQS Gating Delay*/ -#undef DDR_PHY_DX4LCDLR2_DQSGD_DEFVAL -#undef DDR_PHY_DX4LCDLR2_DQSGD_SHIFT -#undef DDR_PHY_DX4LCDLR2_DQSGD_MASK -#define DDR_PHY_DX4LCDLR2_DQSGD_DEFVAL 0x00000000 -#define DDR_PHY_DX4LCDLR2_DQSGD_SHIFT 0 -#define DDR_PHY_DX4LCDLR2_DQSGD_MASK 0x000001FFU - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX4GTR0_RESERVED_31_24_DEFVAL -#undef DDR_PHY_DX4GTR0_RESERVED_31_24_SHIFT -#undef DDR_PHY_DX4GTR0_RESERVED_31_24_MASK -#define DDR_PHY_DX4GTR0_RESERVED_31_24_DEFVAL 0x00020000 -#define DDR_PHY_DX4GTR0_RESERVED_31_24_SHIFT 27 -#define DDR_PHY_DX4GTR0_RESERVED_31_24_MASK 0xF8000000U - -/*DQ Write Path Latency Pipeline*/ -#undef DDR_PHY_DX4GTR0_WDQSL_DEFVAL -#undef DDR_PHY_DX4GTR0_WDQSL_SHIFT -#undef DDR_PHY_DX4GTR0_WDQSL_MASK -#define DDR_PHY_DX4GTR0_WDQSL_DEFVAL 0x00020000 -#define DDR_PHY_DX4GTR0_WDQSL_SHIFT 24 -#define DDR_PHY_DX4GTR0_WDQSL_MASK 0x07000000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX4GTR0_RESERVED_23_20_DEFVAL -#undef DDR_PHY_DX4GTR0_RESERVED_23_20_SHIFT -#undef DDR_PHY_DX4GTR0_RESERVED_23_20_MASK -#define DDR_PHY_DX4GTR0_RESERVED_23_20_DEFVAL 0x00020000 -#define DDR_PHY_DX4GTR0_RESERVED_23_20_SHIFT 20 -#define DDR_PHY_DX4GTR0_RESERVED_23_20_MASK 0x00F00000U - -/*Write Leveling System Latency*/ -#undef DDR_PHY_DX4GTR0_WLSL_DEFVAL -#undef DDR_PHY_DX4GTR0_WLSL_SHIFT -#undef DDR_PHY_DX4GTR0_WLSL_MASK -#define DDR_PHY_DX4GTR0_WLSL_DEFVAL 0x00020000 -#define DDR_PHY_DX4GTR0_WLSL_SHIFT 16 -#define DDR_PHY_DX4GTR0_WLSL_MASK 0x000F0000U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX4GTR0_RESERVED_15_13_DEFVAL -#undef DDR_PHY_DX4GTR0_RESERVED_15_13_SHIFT -#undef DDR_PHY_DX4GTR0_RESERVED_15_13_MASK -#define DDR_PHY_DX4GTR0_RESERVED_15_13_DEFVAL 0x00020000 -#define DDR_PHY_DX4GTR0_RESERVED_15_13_SHIFT 13 -#define DDR_PHY_DX4GTR0_RESERVED_15_13_MASK 0x0000E000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX4GTR0_RESERVED_12_8_DEFVAL -#undef DDR_PHY_DX4GTR0_RESERVED_12_8_SHIFT -#undef DDR_PHY_DX4GTR0_RESERVED_12_8_MASK -#define DDR_PHY_DX4GTR0_RESERVED_12_8_DEFVAL 0x00020000 -#define DDR_PHY_DX4GTR0_RESERVED_12_8_SHIFT 8 -#define DDR_PHY_DX4GTR0_RESERVED_12_8_MASK 0x00001F00U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX4GTR0_RESERVED_7_5_DEFVAL -#undef DDR_PHY_DX4GTR0_RESERVED_7_5_SHIFT -#undef DDR_PHY_DX4GTR0_RESERVED_7_5_MASK -#define DDR_PHY_DX4GTR0_RESERVED_7_5_DEFVAL 0x00020000 -#define DDR_PHY_DX4GTR0_RESERVED_7_5_SHIFT 5 -#define DDR_PHY_DX4GTR0_RESERVED_7_5_MASK 0x000000E0U - -/*DQS Gating System Latency*/ -#undef DDR_PHY_DX4GTR0_DGSL_DEFVAL -#undef DDR_PHY_DX4GTR0_DGSL_SHIFT -#undef DDR_PHY_DX4GTR0_DGSL_MASK -#define DDR_PHY_DX4GTR0_DGSL_DEFVAL 0x00020000 -#define DDR_PHY_DX4GTR0_DGSL_SHIFT 0 -#define DDR_PHY_DX4GTR0_DGSL_MASK 0x0000001FU - -/*Calibration Bypass*/ +/* +* Calibration Bypass +*/ #undef DDR_PHY_DX5GCR0_CALBYP_DEFVAL #undef DDR_PHY_DX5GCR0_CALBYP_SHIFT #undef DDR_PHY_DX5GCR0_CALBYP_MASK -#define DDR_PHY_DX5GCR0_CALBYP_DEFVAL 0x40200204 -#define DDR_PHY_DX5GCR0_CALBYP_SHIFT 31 -#define DDR_PHY_DX5GCR0_CALBYP_MASK 0x80000000U +#define DDR_PHY_DX5GCR0_CALBYP_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_CALBYP_SHIFT 31 +#define DDR_PHY_DX5GCR0_CALBYP_MASK 0x80000000U -/*Master Delay Line Enable*/ +/* +* Master Delay Line Enable +*/ #undef DDR_PHY_DX5GCR0_MDLEN_DEFVAL #undef DDR_PHY_DX5GCR0_MDLEN_SHIFT #undef DDR_PHY_DX5GCR0_MDLEN_MASK -#define DDR_PHY_DX5GCR0_MDLEN_DEFVAL 0x40200204 -#define DDR_PHY_DX5GCR0_MDLEN_SHIFT 30 -#define DDR_PHY_DX5GCR0_MDLEN_MASK 0x40000000U +#define DDR_PHY_DX5GCR0_MDLEN_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_MDLEN_SHIFT 30 +#define DDR_PHY_DX5GCR0_MDLEN_MASK 0x40000000U -/*Configurable ODT(TE) Phase Shift*/ +/* +* Configurable ODT(TE) Phase Shift +*/ #undef DDR_PHY_DX5GCR0_CODTSHFT_DEFVAL #undef DDR_PHY_DX5GCR0_CODTSHFT_SHIFT #undef DDR_PHY_DX5GCR0_CODTSHFT_MASK -#define DDR_PHY_DX5GCR0_CODTSHFT_DEFVAL 0x40200204 -#define DDR_PHY_DX5GCR0_CODTSHFT_SHIFT 28 -#define DDR_PHY_DX5GCR0_CODTSHFT_MASK 0x30000000U +#define DDR_PHY_DX5GCR0_CODTSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_CODTSHFT_SHIFT 28 +#define DDR_PHY_DX5GCR0_CODTSHFT_MASK 0x30000000U -/*DQS Duty Cycle Correction*/ +/* +* DQS Duty Cycle Correction +*/ #undef DDR_PHY_DX5GCR0_DQSDCC_DEFVAL #undef DDR_PHY_DX5GCR0_DQSDCC_SHIFT #undef DDR_PHY_DX5GCR0_DQSDCC_MASK -#define DDR_PHY_DX5GCR0_DQSDCC_DEFVAL 0x40200204 -#define DDR_PHY_DX5GCR0_DQSDCC_SHIFT 24 -#define DDR_PHY_DX5GCR0_DQSDCC_MASK 0x0F000000U +#define DDR_PHY_DX5GCR0_DQSDCC_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_DQSDCC_SHIFT 24 +#define DDR_PHY_DX5GCR0_DQSDCC_MASK 0x0F000000U -/*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/ +/* +* Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY +*/ #undef DDR_PHY_DX5GCR0_RDDLY_DEFVAL #undef DDR_PHY_DX5GCR0_RDDLY_SHIFT #undef DDR_PHY_DX5GCR0_RDDLY_MASK -#define DDR_PHY_DX5GCR0_RDDLY_DEFVAL 0x40200204 -#define DDR_PHY_DX5GCR0_RDDLY_SHIFT 20 -#define DDR_PHY_DX5GCR0_RDDLY_MASK 0x00F00000U +#define DDR_PHY_DX5GCR0_RDDLY_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_RDDLY_SHIFT 20 +#define DDR_PHY_DX5GCR0_RDDLY_MASK 0x00F00000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX5GCR0_RESERVED_19_14_DEFVAL #undef DDR_PHY_DX5GCR0_RESERVED_19_14_SHIFT #undef DDR_PHY_DX5GCR0_RESERVED_19_14_MASK -#define DDR_PHY_DX5GCR0_RESERVED_19_14_DEFVAL 0x40200204 -#define DDR_PHY_DX5GCR0_RESERVED_19_14_SHIFT 14 -#define DDR_PHY_DX5GCR0_RESERVED_19_14_MASK 0x000FC000U +#define DDR_PHY_DX5GCR0_RESERVED_19_14_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_RESERVED_19_14_SHIFT 14 +#define DDR_PHY_DX5GCR0_RESERVED_19_14_MASK 0x000FC000U -/*DQSNSE Power Down Receiver*/ +/* +* DQSNSE Power Down Receiver +*/ #undef DDR_PHY_DX5GCR0_DQSNSEPDR_DEFVAL #undef DDR_PHY_DX5GCR0_DQSNSEPDR_SHIFT #undef DDR_PHY_DX5GCR0_DQSNSEPDR_MASK -#define DDR_PHY_DX5GCR0_DQSNSEPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX5GCR0_DQSNSEPDR_SHIFT 13 -#define DDR_PHY_DX5GCR0_DQSNSEPDR_MASK 0x00002000U +#define DDR_PHY_DX5GCR0_DQSNSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_DQSNSEPDR_SHIFT 13 +#define DDR_PHY_DX5GCR0_DQSNSEPDR_MASK 0x00002000U -/*DQSSE Power Down Receiver*/ +/* +* DQSSE Power Down Receiver +*/ #undef DDR_PHY_DX5GCR0_DQSSEPDR_DEFVAL #undef DDR_PHY_DX5GCR0_DQSSEPDR_SHIFT #undef DDR_PHY_DX5GCR0_DQSSEPDR_MASK -#define DDR_PHY_DX5GCR0_DQSSEPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX5GCR0_DQSSEPDR_SHIFT 12 -#define DDR_PHY_DX5GCR0_DQSSEPDR_MASK 0x00001000U +#define DDR_PHY_DX5GCR0_DQSSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_DQSSEPDR_SHIFT 12 +#define DDR_PHY_DX5GCR0_DQSSEPDR_MASK 0x00001000U -/*RTT On Additive Latency*/ +/* +* RTT On Additive Latency +*/ #undef DDR_PHY_DX5GCR0_RTTOAL_DEFVAL #undef DDR_PHY_DX5GCR0_RTTOAL_SHIFT #undef DDR_PHY_DX5GCR0_RTTOAL_MASK -#define DDR_PHY_DX5GCR0_RTTOAL_DEFVAL 0x40200204 -#define DDR_PHY_DX5GCR0_RTTOAL_SHIFT 11 -#define DDR_PHY_DX5GCR0_RTTOAL_MASK 0x00000800U +#define DDR_PHY_DX5GCR0_RTTOAL_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_RTTOAL_SHIFT 11 +#define DDR_PHY_DX5GCR0_RTTOAL_MASK 0x00000800U -/*RTT Output Hold*/ +/* +* RTT Output Hold +*/ #undef DDR_PHY_DX5GCR0_RTTOH_DEFVAL #undef DDR_PHY_DX5GCR0_RTTOH_SHIFT #undef DDR_PHY_DX5GCR0_RTTOH_MASK -#define DDR_PHY_DX5GCR0_RTTOH_DEFVAL 0x40200204 -#define DDR_PHY_DX5GCR0_RTTOH_SHIFT 9 -#define DDR_PHY_DX5GCR0_RTTOH_MASK 0x00000600U +#define DDR_PHY_DX5GCR0_RTTOH_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_RTTOH_SHIFT 9 +#define DDR_PHY_DX5GCR0_RTTOH_MASK 0x00000600U -/*Configurable PDR Phase Shift*/ +/* +* Configurable PDR Phase Shift +*/ #undef DDR_PHY_DX5GCR0_CPDRSHFT_DEFVAL #undef DDR_PHY_DX5GCR0_CPDRSHFT_SHIFT #undef DDR_PHY_DX5GCR0_CPDRSHFT_MASK -#define DDR_PHY_DX5GCR0_CPDRSHFT_DEFVAL 0x40200204 -#define DDR_PHY_DX5GCR0_CPDRSHFT_SHIFT 7 -#define DDR_PHY_DX5GCR0_CPDRSHFT_MASK 0x00000180U +#define DDR_PHY_DX5GCR0_CPDRSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_CPDRSHFT_SHIFT 7 +#define DDR_PHY_DX5GCR0_CPDRSHFT_MASK 0x00000180U -/*DQSR Power Down*/ +/* +* DQSR Power Down +*/ #undef DDR_PHY_DX5GCR0_DQSRPD_DEFVAL #undef DDR_PHY_DX5GCR0_DQSRPD_SHIFT #undef DDR_PHY_DX5GCR0_DQSRPD_MASK -#define DDR_PHY_DX5GCR0_DQSRPD_DEFVAL 0x40200204 -#define DDR_PHY_DX5GCR0_DQSRPD_SHIFT 6 -#define DDR_PHY_DX5GCR0_DQSRPD_MASK 0x00000040U +#define DDR_PHY_DX5GCR0_DQSRPD_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_DQSRPD_SHIFT 6 +#define DDR_PHY_DX5GCR0_DQSRPD_MASK 0x00000040U -/*DQSG Power Down Receiver*/ +/* +* DQSG Power Down Receiver +*/ #undef DDR_PHY_DX5GCR0_DQSGPDR_DEFVAL #undef DDR_PHY_DX5GCR0_DQSGPDR_SHIFT #undef DDR_PHY_DX5GCR0_DQSGPDR_MASK -#define DDR_PHY_DX5GCR0_DQSGPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX5GCR0_DQSGPDR_SHIFT 5 -#define DDR_PHY_DX5GCR0_DQSGPDR_MASK 0x00000020U +#define DDR_PHY_DX5GCR0_DQSGPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_DQSGPDR_SHIFT 5 +#define DDR_PHY_DX5GCR0_DQSGPDR_MASK 0x00000020U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX5GCR0_RESERVED_4_DEFVAL #undef DDR_PHY_DX5GCR0_RESERVED_4_SHIFT #undef DDR_PHY_DX5GCR0_RESERVED_4_MASK -#define DDR_PHY_DX5GCR0_RESERVED_4_DEFVAL 0x40200204 -#define DDR_PHY_DX5GCR0_RESERVED_4_SHIFT 4 -#define DDR_PHY_DX5GCR0_RESERVED_4_MASK 0x00000010U +#define DDR_PHY_DX5GCR0_RESERVED_4_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_RESERVED_4_SHIFT 4 +#define DDR_PHY_DX5GCR0_RESERVED_4_MASK 0x00000010U -/*DQSG On-Die Termination*/ +/* +* DQSG On-Die Termination +*/ #undef DDR_PHY_DX5GCR0_DQSGODT_DEFVAL #undef DDR_PHY_DX5GCR0_DQSGODT_SHIFT #undef DDR_PHY_DX5GCR0_DQSGODT_MASK -#define DDR_PHY_DX5GCR0_DQSGODT_DEFVAL 0x40200204 -#define DDR_PHY_DX5GCR0_DQSGODT_SHIFT 3 -#define DDR_PHY_DX5GCR0_DQSGODT_MASK 0x00000008U +#define DDR_PHY_DX5GCR0_DQSGODT_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_DQSGODT_SHIFT 3 +#define DDR_PHY_DX5GCR0_DQSGODT_MASK 0x00000008U -/*DQSG Output Enable*/ +/* +* DQSG Output Enable +*/ #undef DDR_PHY_DX5GCR0_DQSGOE_DEFVAL #undef DDR_PHY_DX5GCR0_DQSGOE_SHIFT #undef DDR_PHY_DX5GCR0_DQSGOE_MASK -#define DDR_PHY_DX5GCR0_DQSGOE_DEFVAL 0x40200204 -#define DDR_PHY_DX5GCR0_DQSGOE_SHIFT 2 -#define DDR_PHY_DX5GCR0_DQSGOE_MASK 0x00000004U +#define DDR_PHY_DX5GCR0_DQSGOE_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_DQSGOE_SHIFT 2 +#define DDR_PHY_DX5GCR0_DQSGOE_MASK 0x00000004U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX5GCR0_RESERVED_1_0_DEFVAL #undef DDR_PHY_DX5GCR0_RESERVED_1_0_SHIFT #undef DDR_PHY_DX5GCR0_RESERVED_1_0_MASK -#define DDR_PHY_DX5GCR0_RESERVED_1_0_DEFVAL 0x40200204 -#define DDR_PHY_DX5GCR0_RESERVED_1_0_SHIFT 0 -#define DDR_PHY_DX5GCR0_RESERVED_1_0_MASK 0x00000003U +#define DDR_PHY_DX5GCR0_RESERVED_1_0_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_RESERVED_1_0_SHIFT 0 +#define DDR_PHY_DX5GCR0_RESERVED_1_0_MASK 0x00000003U -/*Enables the PDR mode for DQ[7:0]*/ +/* +* Enables the PDR mode for DQ[7:0] +*/ #undef DDR_PHY_DX5GCR1_DXPDRMODE_DEFVAL #undef DDR_PHY_DX5GCR1_DXPDRMODE_SHIFT #undef DDR_PHY_DX5GCR1_DXPDRMODE_MASK -#define DDR_PHY_DX5GCR1_DXPDRMODE_DEFVAL 0x00007FFF -#define DDR_PHY_DX5GCR1_DXPDRMODE_SHIFT 16 -#define DDR_PHY_DX5GCR1_DXPDRMODE_MASK 0xFFFF0000U +#define DDR_PHY_DX5GCR1_DXPDRMODE_DEFVAL 0x00007FFF +#define DDR_PHY_DX5GCR1_DXPDRMODE_SHIFT 16 +#define DDR_PHY_DX5GCR1_DXPDRMODE_MASK 0xFFFF0000U -/*Reserved. Returns zeroes on reads.*/ +/* +* Reserved. Returns zeroes on reads. +*/ #undef DDR_PHY_DX5GCR1_RESERVED_15_DEFVAL #undef DDR_PHY_DX5GCR1_RESERVED_15_SHIFT #undef DDR_PHY_DX5GCR1_RESERVED_15_MASK -#define DDR_PHY_DX5GCR1_RESERVED_15_DEFVAL 0x00007FFF -#define DDR_PHY_DX5GCR1_RESERVED_15_SHIFT 15 -#define DDR_PHY_DX5GCR1_RESERVED_15_MASK 0x00008000U +#define DDR_PHY_DX5GCR1_RESERVED_15_DEFVAL 0x00007FFF +#define DDR_PHY_DX5GCR1_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX5GCR1_RESERVED_15_MASK 0x00008000U -/*Select the delayed or non-delayed read data strobe #*/ +/* +* Select the delayed or non-delayed read data strobe # +*/ #undef DDR_PHY_DX5GCR1_QSNSEL_DEFVAL #undef DDR_PHY_DX5GCR1_QSNSEL_SHIFT #undef DDR_PHY_DX5GCR1_QSNSEL_MASK -#define DDR_PHY_DX5GCR1_QSNSEL_DEFVAL 0x00007FFF -#define DDR_PHY_DX5GCR1_QSNSEL_SHIFT 14 -#define DDR_PHY_DX5GCR1_QSNSEL_MASK 0x00004000U +#define DDR_PHY_DX5GCR1_QSNSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX5GCR1_QSNSEL_SHIFT 14 +#define DDR_PHY_DX5GCR1_QSNSEL_MASK 0x00004000U -/*Select the delayed or non-delayed read data strobe*/ +/* +* Select the delayed or non-delayed read data strobe +*/ #undef DDR_PHY_DX5GCR1_QSSEL_DEFVAL #undef DDR_PHY_DX5GCR1_QSSEL_SHIFT #undef DDR_PHY_DX5GCR1_QSSEL_MASK -#define DDR_PHY_DX5GCR1_QSSEL_DEFVAL 0x00007FFF -#define DDR_PHY_DX5GCR1_QSSEL_SHIFT 13 -#define DDR_PHY_DX5GCR1_QSSEL_MASK 0x00002000U +#define DDR_PHY_DX5GCR1_QSSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX5GCR1_QSSEL_SHIFT 13 +#define DDR_PHY_DX5GCR1_QSSEL_MASK 0x00002000U -/*Enables Read Data Strobe in a byte lane*/ +/* +* Enables Read Data Strobe in a byte lane +*/ #undef DDR_PHY_DX5GCR1_OEEN_DEFVAL #undef DDR_PHY_DX5GCR1_OEEN_SHIFT #undef DDR_PHY_DX5GCR1_OEEN_MASK -#define DDR_PHY_DX5GCR1_OEEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX5GCR1_OEEN_SHIFT 12 -#define DDR_PHY_DX5GCR1_OEEN_MASK 0x00001000U +#define DDR_PHY_DX5GCR1_OEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX5GCR1_OEEN_SHIFT 12 +#define DDR_PHY_DX5GCR1_OEEN_MASK 0x00001000U -/*Enables PDR in a byte lane*/ +/* +* Enables PDR in a byte lane +*/ #undef DDR_PHY_DX5GCR1_PDREN_DEFVAL #undef DDR_PHY_DX5GCR1_PDREN_SHIFT #undef DDR_PHY_DX5GCR1_PDREN_MASK -#define DDR_PHY_DX5GCR1_PDREN_DEFVAL 0x00007FFF -#define DDR_PHY_DX5GCR1_PDREN_SHIFT 11 -#define DDR_PHY_DX5GCR1_PDREN_MASK 0x00000800U +#define DDR_PHY_DX5GCR1_PDREN_DEFVAL 0x00007FFF +#define DDR_PHY_DX5GCR1_PDREN_SHIFT 11 +#define DDR_PHY_DX5GCR1_PDREN_MASK 0x00000800U -/*Enables ODT/TE in a byte lane*/ +/* +* Enables ODT/TE in a byte lane +*/ #undef DDR_PHY_DX5GCR1_TEEN_DEFVAL #undef DDR_PHY_DX5GCR1_TEEN_SHIFT #undef DDR_PHY_DX5GCR1_TEEN_MASK -#define DDR_PHY_DX5GCR1_TEEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX5GCR1_TEEN_SHIFT 10 -#define DDR_PHY_DX5GCR1_TEEN_MASK 0x00000400U +#define DDR_PHY_DX5GCR1_TEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX5GCR1_TEEN_SHIFT 10 +#define DDR_PHY_DX5GCR1_TEEN_MASK 0x00000400U -/*Enables Write Data strobe in a byte lane*/ +/* +* Enables Write Data strobe in a byte lane +*/ #undef DDR_PHY_DX5GCR1_DSEN_DEFVAL #undef DDR_PHY_DX5GCR1_DSEN_SHIFT #undef DDR_PHY_DX5GCR1_DSEN_MASK -#define DDR_PHY_DX5GCR1_DSEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX5GCR1_DSEN_SHIFT 9 -#define DDR_PHY_DX5GCR1_DSEN_MASK 0x00000200U +#define DDR_PHY_DX5GCR1_DSEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX5GCR1_DSEN_SHIFT 9 +#define DDR_PHY_DX5GCR1_DSEN_MASK 0x00000200U -/*Enables DM pin in a byte lane*/ +/* +* Enables DM pin in a byte lane +*/ #undef DDR_PHY_DX5GCR1_DMEN_DEFVAL #undef DDR_PHY_DX5GCR1_DMEN_SHIFT #undef DDR_PHY_DX5GCR1_DMEN_MASK -#define DDR_PHY_DX5GCR1_DMEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX5GCR1_DMEN_SHIFT 8 -#define DDR_PHY_DX5GCR1_DMEN_MASK 0x00000100U +#define DDR_PHY_DX5GCR1_DMEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX5GCR1_DMEN_SHIFT 8 +#define DDR_PHY_DX5GCR1_DMEN_MASK 0x00000100U -/*Enables DQ corresponding to each bit in a byte*/ +/* +* Enables DQ corresponding to each bit in a byte +*/ #undef DDR_PHY_DX5GCR1_DQEN_DEFVAL #undef DDR_PHY_DX5GCR1_DQEN_SHIFT #undef DDR_PHY_DX5GCR1_DQEN_MASK -#define DDR_PHY_DX5GCR1_DQEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX5GCR1_DQEN_SHIFT 0 -#define DDR_PHY_DX5GCR1_DQEN_MASK 0x000000FFU +#define DDR_PHY_DX5GCR1_DQEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX5GCR1_DQEN_SHIFT 0 +#define DDR_PHY_DX5GCR1_DQEN_MASK 0x000000FFU -/*Byte lane VREF IOM (Used only by D4MU IOs)*/ +/* +* Byte lane VREF IOM (Used only by D4MU IOs) +*/ #undef DDR_PHY_DX5GCR4_RESERVED_31_29_DEFVAL #undef DDR_PHY_DX5GCR4_RESERVED_31_29_SHIFT #undef DDR_PHY_DX5GCR4_RESERVED_31_29_MASK -#define DDR_PHY_DX5GCR4_RESERVED_31_29_DEFVAL 0x0E00003C -#define DDR_PHY_DX5GCR4_RESERVED_31_29_SHIFT 29 -#define DDR_PHY_DX5GCR4_RESERVED_31_29_MASK 0xE0000000U +#define DDR_PHY_DX5GCR4_RESERVED_31_29_DEFVAL 0x0E00003C +#define DDR_PHY_DX5GCR4_RESERVED_31_29_SHIFT 29 +#define DDR_PHY_DX5GCR4_RESERVED_31_29_MASK 0xE0000000U -/*Byte Lane VREF Pad Enable*/ +/* +* Byte Lane VREF Pad Enable +*/ #undef DDR_PHY_DX5GCR4_DXREFPEN_DEFVAL #undef DDR_PHY_DX5GCR4_DXREFPEN_SHIFT #undef DDR_PHY_DX5GCR4_DXREFPEN_MASK -#define DDR_PHY_DX5GCR4_DXREFPEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX5GCR4_DXREFPEN_SHIFT 28 -#define DDR_PHY_DX5GCR4_DXREFPEN_MASK 0x10000000U +#define DDR_PHY_DX5GCR4_DXREFPEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX5GCR4_DXREFPEN_SHIFT 28 +#define DDR_PHY_DX5GCR4_DXREFPEN_MASK 0x10000000U -/*Byte Lane Internal VREF Enable*/ +/* +* Byte Lane Internal VREF Enable +*/ #undef DDR_PHY_DX5GCR4_DXREFEEN_DEFVAL #undef DDR_PHY_DX5GCR4_DXREFEEN_SHIFT #undef DDR_PHY_DX5GCR4_DXREFEEN_MASK -#define DDR_PHY_DX5GCR4_DXREFEEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX5GCR4_DXREFEEN_SHIFT 26 -#define DDR_PHY_DX5GCR4_DXREFEEN_MASK 0x0C000000U +#define DDR_PHY_DX5GCR4_DXREFEEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX5GCR4_DXREFEEN_SHIFT 26 +#define DDR_PHY_DX5GCR4_DXREFEEN_MASK 0x0C000000U -/*Byte Lane Single-End VREF Enable*/ +/* +* Byte Lane Single-End VREF Enable +*/ #undef DDR_PHY_DX5GCR4_DXREFSEN_DEFVAL #undef DDR_PHY_DX5GCR4_DXREFSEN_SHIFT #undef DDR_PHY_DX5GCR4_DXREFSEN_MASK -#define DDR_PHY_DX5GCR4_DXREFSEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX5GCR4_DXREFSEN_SHIFT 25 -#define DDR_PHY_DX5GCR4_DXREFSEN_MASK 0x02000000U +#define DDR_PHY_DX5GCR4_DXREFSEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX5GCR4_DXREFSEN_SHIFT 25 +#define DDR_PHY_DX5GCR4_DXREFSEN_MASK 0x02000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX5GCR4_RESERVED_24_DEFVAL #undef DDR_PHY_DX5GCR4_RESERVED_24_SHIFT #undef DDR_PHY_DX5GCR4_RESERVED_24_MASK -#define DDR_PHY_DX5GCR4_RESERVED_24_DEFVAL 0x0E00003C -#define DDR_PHY_DX5GCR4_RESERVED_24_SHIFT 24 -#define DDR_PHY_DX5GCR4_RESERVED_24_MASK 0x01000000U +#define DDR_PHY_DX5GCR4_RESERVED_24_DEFVAL 0x0E00003C +#define DDR_PHY_DX5GCR4_RESERVED_24_SHIFT 24 +#define DDR_PHY_DX5GCR4_RESERVED_24_MASK 0x01000000U -/*External VREF generator REFSEL range select*/ +/* +* External VREF generator REFSEL range select +*/ #undef DDR_PHY_DX5GCR4_DXREFESELRANGE_DEFVAL #undef DDR_PHY_DX5GCR4_DXREFESELRANGE_SHIFT #undef DDR_PHY_DX5GCR4_DXREFESELRANGE_MASK -#define DDR_PHY_DX5GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C -#define DDR_PHY_DX5GCR4_DXREFESELRANGE_SHIFT 23 -#define DDR_PHY_DX5GCR4_DXREFESELRANGE_MASK 0x00800000U +#define DDR_PHY_DX5GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX5GCR4_DXREFESELRANGE_SHIFT 23 +#define DDR_PHY_DX5GCR4_DXREFESELRANGE_MASK 0x00800000U -/*Byte Lane External VREF Select*/ +/* +* Byte Lane External VREF Select +*/ #undef DDR_PHY_DX5GCR4_DXREFESEL_DEFVAL #undef DDR_PHY_DX5GCR4_DXREFESEL_SHIFT #undef DDR_PHY_DX5GCR4_DXREFESEL_MASK -#define DDR_PHY_DX5GCR4_DXREFESEL_DEFVAL 0x0E00003C -#define DDR_PHY_DX5GCR4_DXREFESEL_SHIFT 16 -#define DDR_PHY_DX5GCR4_DXREFESEL_MASK 0x007F0000U +#define DDR_PHY_DX5GCR4_DXREFESEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX5GCR4_DXREFESEL_SHIFT 16 +#define DDR_PHY_DX5GCR4_DXREFESEL_MASK 0x007F0000U -/*Single ended VREF generator REFSEL range select*/ +/* +* Single ended VREF generator REFSEL range select +*/ #undef DDR_PHY_DX5GCR4_DXREFSSELRANGE_DEFVAL #undef DDR_PHY_DX5GCR4_DXREFSSELRANGE_SHIFT #undef DDR_PHY_DX5GCR4_DXREFSSELRANGE_MASK -#define DDR_PHY_DX5GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C -#define DDR_PHY_DX5GCR4_DXREFSSELRANGE_SHIFT 15 -#define DDR_PHY_DX5GCR4_DXREFSSELRANGE_MASK 0x00008000U +#define DDR_PHY_DX5GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX5GCR4_DXREFSSELRANGE_SHIFT 15 +#define DDR_PHY_DX5GCR4_DXREFSSELRANGE_MASK 0x00008000U -/*Byte Lane Single-End VREF Select*/ +/* +* Byte Lane Single-End VREF Select +*/ #undef DDR_PHY_DX5GCR4_DXREFSSEL_DEFVAL #undef DDR_PHY_DX5GCR4_DXREFSSEL_SHIFT #undef DDR_PHY_DX5GCR4_DXREFSSEL_MASK -#define DDR_PHY_DX5GCR4_DXREFSSEL_DEFVAL 0x0E00003C -#define DDR_PHY_DX5GCR4_DXREFSSEL_SHIFT 8 -#define DDR_PHY_DX5GCR4_DXREFSSEL_MASK 0x00007F00U +#define DDR_PHY_DX5GCR4_DXREFSSEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX5GCR4_DXREFSSEL_SHIFT 8 +#define DDR_PHY_DX5GCR4_DXREFSSEL_MASK 0x00007F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX5GCR4_RESERVED_7_6_DEFVAL #undef DDR_PHY_DX5GCR4_RESERVED_7_6_SHIFT #undef DDR_PHY_DX5GCR4_RESERVED_7_6_MASK -#define DDR_PHY_DX5GCR4_RESERVED_7_6_DEFVAL 0x0E00003C -#define DDR_PHY_DX5GCR4_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_DX5GCR4_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_DX5GCR4_RESERVED_7_6_DEFVAL 0x0E00003C +#define DDR_PHY_DX5GCR4_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX5GCR4_RESERVED_7_6_MASK 0x000000C0U -/*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/ +/* +* VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. +*/ #undef DDR_PHY_DX5GCR4_DXREFIEN_DEFVAL #undef DDR_PHY_DX5GCR4_DXREFIEN_SHIFT #undef DDR_PHY_DX5GCR4_DXREFIEN_MASK -#define DDR_PHY_DX5GCR4_DXREFIEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX5GCR4_DXREFIEN_SHIFT 2 -#define DDR_PHY_DX5GCR4_DXREFIEN_MASK 0x0000003CU +#define DDR_PHY_DX5GCR4_DXREFIEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX5GCR4_DXREFIEN_SHIFT 2 +#define DDR_PHY_DX5GCR4_DXREFIEN_MASK 0x0000003CU -/*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/ +/* +* VRMON control for DQ IO (Single Ended) buffers of a byte lane. +*/ #undef DDR_PHY_DX5GCR4_DXREFIMON_DEFVAL #undef DDR_PHY_DX5GCR4_DXREFIMON_SHIFT #undef DDR_PHY_DX5GCR4_DXREFIMON_MASK -#define DDR_PHY_DX5GCR4_DXREFIMON_DEFVAL 0x0E00003C -#define DDR_PHY_DX5GCR4_DXREFIMON_SHIFT 0 -#define DDR_PHY_DX5GCR4_DXREFIMON_MASK 0x00000003U +#define DDR_PHY_DX5GCR4_DXREFIMON_DEFVAL 0x0E00003C +#define DDR_PHY_DX5GCR4_DXREFIMON_SHIFT 0 +#define DDR_PHY_DX5GCR4_DXREFIMON_MASK 0x00000003U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX5GCR5_RESERVED_31_DEFVAL #undef DDR_PHY_DX5GCR5_RESERVED_31_SHIFT #undef DDR_PHY_DX5GCR5_RESERVED_31_MASK -#define DDR_PHY_DX5GCR5_RESERVED_31_DEFVAL 0x09090909 -#define DDR_PHY_DX5GCR5_RESERVED_31_SHIFT 31 -#define DDR_PHY_DX5GCR5_RESERVED_31_MASK 0x80000000U +#define DDR_PHY_DX5GCR5_RESERVED_31_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR5_RESERVED_31_SHIFT 31 +#define DDR_PHY_DX5GCR5_RESERVED_31_MASK 0x80000000U -/*Byte Lane internal VREF Select for Rank 3*/ +/* +* Byte Lane internal VREF Select for Rank 3 +*/ #undef DDR_PHY_DX5GCR5_DXREFISELR3_DEFVAL #undef DDR_PHY_DX5GCR5_DXREFISELR3_SHIFT #undef DDR_PHY_DX5GCR5_DXREFISELR3_MASK -#define DDR_PHY_DX5GCR5_DXREFISELR3_DEFVAL 0x09090909 -#define DDR_PHY_DX5GCR5_DXREFISELR3_SHIFT 24 -#define DDR_PHY_DX5GCR5_DXREFISELR3_MASK 0x7F000000U +#define DDR_PHY_DX5GCR5_DXREFISELR3_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR5_DXREFISELR3_SHIFT 24 +#define DDR_PHY_DX5GCR5_DXREFISELR3_MASK 0x7F000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX5GCR5_RESERVED_23_DEFVAL #undef DDR_PHY_DX5GCR5_RESERVED_23_SHIFT #undef DDR_PHY_DX5GCR5_RESERVED_23_MASK -#define DDR_PHY_DX5GCR5_RESERVED_23_DEFVAL 0x09090909 -#define DDR_PHY_DX5GCR5_RESERVED_23_SHIFT 23 -#define DDR_PHY_DX5GCR5_RESERVED_23_MASK 0x00800000U +#define DDR_PHY_DX5GCR5_RESERVED_23_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR5_RESERVED_23_SHIFT 23 +#define DDR_PHY_DX5GCR5_RESERVED_23_MASK 0x00800000U -/*Byte Lane internal VREF Select for Rank 2*/ +/* +* Byte Lane internal VREF Select for Rank 2 +*/ #undef DDR_PHY_DX5GCR5_DXREFISELR2_DEFVAL #undef DDR_PHY_DX5GCR5_DXREFISELR2_SHIFT #undef DDR_PHY_DX5GCR5_DXREFISELR2_MASK -#define DDR_PHY_DX5GCR5_DXREFISELR2_DEFVAL 0x09090909 -#define DDR_PHY_DX5GCR5_DXREFISELR2_SHIFT 16 -#define DDR_PHY_DX5GCR5_DXREFISELR2_MASK 0x007F0000U +#define DDR_PHY_DX5GCR5_DXREFISELR2_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR5_DXREFISELR2_SHIFT 16 +#define DDR_PHY_DX5GCR5_DXREFISELR2_MASK 0x007F0000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX5GCR5_RESERVED_15_DEFVAL #undef DDR_PHY_DX5GCR5_RESERVED_15_SHIFT #undef DDR_PHY_DX5GCR5_RESERVED_15_MASK -#define DDR_PHY_DX5GCR5_RESERVED_15_DEFVAL 0x09090909 -#define DDR_PHY_DX5GCR5_RESERVED_15_SHIFT 15 -#define DDR_PHY_DX5GCR5_RESERVED_15_MASK 0x00008000U +#define DDR_PHY_DX5GCR5_RESERVED_15_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR5_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX5GCR5_RESERVED_15_MASK 0x00008000U -/*Byte Lane internal VREF Select for Rank 1*/ +/* +* Byte Lane internal VREF Select for Rank 1 +*/ #undef DDR_PHY_DX5GCR5_DXREFISELR1_DEFVAL #undef DDR_PHY_DX5GCR5_DXREFISELR1_SHIFT #undef DDR_PHY_DX5GCR5_DXREFISELR1_MASK -#define DDR_PHY_DX5GCR5_DXREFISELR1_DEFVAL 0x09090909 -#define DDR_PHY_DX5GCR5_DXREFISELR1_SHIFT 8 -#define DDR_PHY_DX5GCR5_DXREFISELR1_MASK 0x00007F00U +#define DDR_PHY_DX5GCR5_DXREFISELR1_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR5_DXREFISELR1_SHIFT 8 +#define DDR_PHY_DX5GCR5_DXREFISELR1_MASK 0x00007F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX5GCR5_RESERVED_7_DEFVAL #undef DDR_PHY_DX5GCR5_RESERVED_7_SHIFT #undef DDR_PHY_DX5GCR5_RESERVED_7_MASK -#define DDR_PHY_DX5GCR5_RESERVED_7_DEFVAL 0x09090909 -#define DDR_PHY_DX5GCR5_RESERVED_7_SHIFT 7 -#define DDR_PHY_DX5GCR5_RESERVED_7_MASK 0x00000080U +#define DDR_PHY_DX5GCR5_RESERVED_7_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR5_RESERVED_7_SHIFT 7 +#define DDR_PHY_DX5GCR5_RESERVED_7_MASK 0x00000080U -/*Byte Lane internal VREF Select for Rank 0*/ +/* +* Byte Lane internal VREF Select for Rank 0 +*/ #undef DDR_PHY_DX5GCR5_DXREFISELR0_DEFVAL #undef DDR_PHY_DX5GCR5_DXREFISELR0_SHIFT #undef DDR_PHY_DX5GCR5_DXREFISELR0_MASK -#define DDR_PHY_DX5GCR5_DXREFISELR0_DEFVAL 0x09090909 -#define DDR_PHY_DX5GCR5_DXREFISELR0_SHIFT 0 -#define DDR_PHY_DX5GCR5_DXREFISELR0_MASK 0x0000007FU +#define DDR_PHY_DX5GCR5_DXREFISELR0_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR5_DXREFISELR0_SHIFT 0 +#define DDR_PHY_DX5GCR5_DXREFISELR0_MASK 0x0000007FU -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX5GCR6_RESERVED_31_30_DEFVAL #undef DDR_PHY_DX5GCR6_RESERVED_31_30_SHIFT #undef DDR_PHY_DX5GCR6_RESERVED_31_30_MASK -#define DDR_PHY_DX5GCR6_RESERVED_31_30_DEFVAL 0x09090909 -#define DDR_PHY_DX5GCR6_RESERVED_31_30_SHIFT 30 -#define DDR_PHY_DX5GCR6_RESERVED_31_30_MASK 0xC0000000U +#define DDR_PHY_DX5GCR6_RESERVED_31_30_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR6_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX5GCR6_RESERVED_31_30_MASK 0xC0000000U -/*DRAM DQ VREF Select for Rank3*/ +/* +* DRAM DQ VREF Select for Rank3 +*/ #undef DDR_PHY_DX5GCR6_DXDQVREFR3_DEFVAL #undef DDR_PHY_DX5GCR6_DXDQVREFR3_SHIFT #undef DDR_PHY_DX5GCR6_DXDQVREFR3_MASK -#define DDR_PHY_DX5GCR6_DXDQVREFR3_DEFVAL 0x09090909 -#define DDR_PHY_DX5GCR6_DXDQVREFR3_SHIFT 24 -#define DDR_PHY_DX5GCR6_DXDQVREFR3_MASK 0x3F000000U +#define DDR_PHY_DX5GCR6_DXDQVREFR3_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR6_DXDQVREFR3_SHIFT 24 +#define DDR_PHY_DX5GCR6_DXDQVREFR3_MASK 0x3F000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX5GCR6_RESERVED_23_22_DEFVAL #undef DDR_PHY_DX5GCR6_RESERVED_23_22_SHIFT #undef DDR_PHY_DX5GCR6_RESERVED_23_22_MASK -#define DDR_PHY_DX5GCR6_RESERVED_23_22_DEFVAL 0x09090909 -#define DDR_PHY_DX5GCR6_RESERVED_23_22_SHIFT 22 -#define DDR_PHY_DX5GCR6_RESERVED_23_22_MASK 0x00C00000U +#define DDR_PHY_DX5GCR6_RESERVED_23_22_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR6_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX5GCR6_RESERVED_23_22_MASK 0x00C00000U -/*DRAM DQ VREF Select for Rank2*/ +/* +* DRAM DQ VREF Select for Rank2 +*/ #undef DDR_PHY_DX5GCR6_DXDQVREFR2_DEFVAL #undef DDR_PHY_DX5GCR6_DXDQVREFR2_SHIFT #undef DDR_PHY_DX5GCR6_DXDQVREFR2_MASK -#define DDR_PHY_DX5GCR6_DXDQVREFR2_DEFVAL 0x09090909 -#define DDR_PHY_DX5GCR6_DXDQVREFR2_SHIFT 16 -#define DDR_PHY_DX5GCR6_DXDQVREFR2_MASK 0x003F0000U +#define DDR_PHY_DX5GCR6_DXDQVREFR2_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR6_DXDQVREFR2_SHIFT 16 +#define DDR_PHY_DX5GCR6_DXDQVREFR2_MASK 0x003F0000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX5GCR6_RESERVED_15_14_DEFVAL #undef DDR_PHY_DX5GCR6_RESERVED_15_14_SHIFT #undef DDR_PHY_DX5GCR6_RESERVED_15_14_MASK -#define DDR_PHY_DX5GCR6_RESERVED_15_14_DEFVAL 0x09090909 -#define DDR_PHY_DX5GCR6_RESERVED_15_14_SHIFT 14 -#define DDR_PHY_DX5GCR6_RESERVED_15_14_MASK 0x0000C000U +#define DDR_PHY_DX5GCR6_RESERVED_15_14_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR6_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_DX5GCR6_RESERVED_15_14_MASK 0x0000C000U -/*DRAM DQ VREF Select for Rank1*/ +/* +* DRAM DQ VREF Select for Rank1 +*/ #undef DDR_PHY_DX5GCR6_DXDQVREFR1_DEFVAL #undef DDR_PHY_DX5GCR6_DXDQVREFR1_SHIFT #undef DDR_PHY_DX5GCR6_DXDQVREFR1_MASK -#define DDR_PHY_DX5GCR6_DXDQVREFR1_DEFVAL 0x09090909 -#define DDR_PHY_DX5GCR6_DXDQVREFR1_SHIFT 8 -#define DDR_PHY_DX5GCR6_DXDQVREFR1_MASK 0x00003F00U +#define DDR_PHY_DX5GCR6_DXDQVREFR1_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR6_DXDQVREFR1_SHIFT 8 +#define DDR_PHY_DX5GCR6_DXDQVREFR1_MASK 0x00003F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX5GCR6_RESERVED_7_6_DEFVAL #undef DDR_PHY_DX5GCR6_RESERVED_7_6_SHIFT #undef DDR_PHY_DX5GCR6_RESERVED_7_6_MASK -#define DDR_PHY_DX5GCR6_RESERVED_7_6_DEFVAL 0x09090909 -#define DDR_PHY_DX5GCR6_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_DX5GCR6_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_DX5GCR6_RESERVED_7_6_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR6_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX5GCR6_RESERVED_7_6_MASK 0x000000C0U -/*DRAM DQ VREF Select for Rank0*/ +/* +* DRAM DQ VREF Select for Rank0 +*/ #undef DDR_PHY_DX5GCR6_DXDQVREFR0_DEFVAL #undef DDR_PHY_DX5GCR6_DXDQVREFR0_SHIFT #undef DDR_PHY_DX5GCR6_DXDQVREFR0_MASK -#define DDR_PHY_DX5GCR6_DXDQVREFR0_DEFVAL 0x09090909 -#define DDR_PHY_DX5GCR6_DXDQVREFR0_SHIFT 0 -#define DDR_PHY_DX5GCR6_DXDQVREFR0_MASK 0x0000003FU +#define DDR_PHY_DX5GCR6_DXDQVREFR0_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR6_DXDQVREFR0_SHIFT 0 +#define DDR_PHY_DX5GCR6_DXDQVREFR0_MASK 0x0000003FU -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX5LCDLR2_RESERVED_31_25_DEFVAL -#undef DDR_PHY_DX5LCDLR2_RESERVED_31_25_SHIFT -#undef DDR_PHY_DX5LCDLR2_RESERVED_31_25_MASK -#define DDR_PHY_DX5LCDLR2_RESERVED_31_25_DEFVAL 0x00000000 -#define DDR_PHY_DX5LCDLR2_RESERVED_31_25_SHIFT 25 -#define DDR_PHY_DX5LCDLR2_RESERVED_31_25_MASK 0xFE000000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX5LCDLR2_RESERVED_24_16_DEFVAL -#undef DDR_PHY_DX5LCDLR2_RESERVED_24_16_SHIFT -#undef DDR_PHY_DX5LCDLR2_RESERVED_24_16_MASK -#define DDR_PHY_DX5LCDLR2_RESERVED_24_16_DEFVAL 0x00000000 -#define DDR_PHY_DX5LCDLR2_RESERVED_24_16_SHIFT 16 -#define DDR_PHY_DX5LCDLR2_RESERVED_24_16_MASK 0x01FF0000U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX5LCDLR2_RESERVED_15_9_DEFVAL -#undef DDR_PHY_DX5LCDLR2_RESERVED_15_9_SHIFT -#undef DDR_PHY_DX5LCDLR2_RESERVED_15_9_MASK -#define DDR_PHY_DX5LCDLR2_RESERVED_15_9_DEFVAL 0x00000000 -#define DDR_PHY_DX5LCDLR2_RESERVED_15_9_SHIFT 9 -#define DDR_PHY_DX5LCDLR2_RESERVED_15_9_MASK 0x0000FE00U - -/*Read DQS Gating Delay*/ -#undef DDR_PHY_DX5LCDLR2_DQSGD_DEFVAL -#undef DDR_PHY_DX5LCDLR2_DQSGD_SHIFT -#undef DDR_PHY_DX5LCDLR2_DQSGD_MASK -#define DDR_PHY_DX5LCDLR2_DQSGD_DEFVAL 0x00000000 -#define DDR_PHY_DX5LCDLR2_DQSGD_SHIFT 0 -#define DDR_PHY_DX5LCDLR2_DQSGD_MASK 0x000001FFU - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX5GTR0_RESERVED_31_24_DEFVAL -#undef DDR_PHY_DX5GTR0_RESERVED_31_24_SHIFT -#undef DDR_PHY_DX5GTR0_RESERVED_31_24_MASK -#define DDR_PHY_DX5GTR0_RESERVED_31_24_DEFVAL 0x00020000 -#define DDR_PHY_DX5GTR0_RESERVED_31_24_SHIFT 27 -#define DDR_PHY_DX5GTR0_RESERVED_31_24_MASK 0xF8000000U - -/*DQ Write Path Latency Pipeline*/ -#undef DDR_PHY_DX5GTR0_WDQSL_DEFVAL -#undef DDR_PHY_DX5GTR0_WDQSL_SHIFT -#undef DDR_PHY_DX5GTR0_WDQSL_MASK -#define DDR_PHY_DX5GTR0_WDQSL_DEFVAL 0x00020000 -#define DDR_PHY_DX5GTR0_WDQSL_SHIFT 24 -#define DDR_PHY_DX5GTR0_WDQSL_MASK 0x07000000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX5GTR0_RESERVED_23_20_DEFVAL -#undef DDR_PHY_DX5GTR0_RESERVED_23_20_SHIFT -#undef DDR_PHY_DX5GTR0_RESERVED_23_20_MASK -#define DDR_PHY_DX5GTR0_RESERVED_23_20_DEFVAL 0x00020000 -#define DDR_PHY_DX5GTR0_RESERVED_23_20_SHIFT 20 -#define DDR_PHY_DX5GTR0_RESERVED_23_20_MASK 0x00F00000U - -/*Write Leveling System Latency*/ -#undef DDR_PHY_DX5GTR0_WLSL_DEFVAL -#undef DDR_PHY_DX5GTR0_WLSL_SHIFT -#undef DDR_PHY_DX5GTR0_WLSL_MASK -#define DDR_PHY_DX5GTR0_WLSL_DEFVAL 0x00020000 -#define DDR_PHY_DX5GTR0_WLSL_SHIFT 16 -#define DDR_PHY_DX5GTR0_WLSL_MASK 0x000F0000U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX5GTR0_RESERVED_15_13_DEFVAL -#undef DDR_PHY_DX5GTR0_RESERVED_15_13_SHIFT -#undef DDR_PHY_DX5GTR0_RESERVED_15_13_MASK -#define DDR_PHY_DX5GTR0_RESERVED_15_13_DEFVAL 0x00020000 -#define DDR_PHY_DX5GTR0_RESERVED_15_13_SHIFT 13 -#define DDR_PHY_DX5GTR0_RESERVED_15_13_MASK 0x0000E000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX5GTR0_RESERVED_12_8_DEFVAL -#undef DDR_PHY_DX5GTR0_RESERVED_12_8_SHIFT -#undef DDR_PHY_DX5GTR0_RESERVED_12_8_MASK -#define DDR_PHY_DX5GTR0_RESERVED_12_8_DEFVAL 0x00020000 -#define DDR_PHY_DX5GTR0_RESERVED_12_8_SHIFT 8 -#define DDR_PHY_DX5GTR0_RESERVED_12_8_MASK 0x00001F00U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX5GTR0_RESERVED_7_5_DEFVAL -#undef DDR_PHY_DX5GTR0_RESERVED_7_5_SHIFT -#undef DDR_PHY_DX5GTR0_RESERVED_7_5_MASK -#define DDR_PHY_DX5GTR0_RESERVED_7_5_DEFVAL 0x00020000 -#define DDR_PHY_DX5GTR0_RESERVED_7_5_SHIFT 5 -#define DDR_PHY_DX5GTR0_RESERVED_7_5_MASK 0x000000E0U - -/*DQS Gating System Latency*/ -#undef DDR_PHY_DX5GTR0_DGSL_DEFVAL -#undef DDR_PHY_DX5GTR0_DGSL_SHIFT -#undef DDR_PHY_DX5GTR0_DGSL_MASK -#define DDR_PHY_DX5GTR0_DGSL_DEFVAL 0x00020000 -#define DDR_PHY_DX5GTR0_DGSL_SHIFT 0 -#define DDR_PHY_DX5GTR0_DGSL_MASK 0x0000001FU - -/*Calibration Bypass*/ +/* +* Calibration Bypass +*/ #undef DDR_PHY_DX6GCR0_CALBYP_DEFVAL #undef DDR_PHY_DX6GCR0_CALBYP_SHIFT #undef DDR_PHY_DX6GCR0_CALBYP_MASK -#define DDR_PHY_DX6GCR0_CALBYP_DEFVAL 0x40200204 -#define DDR_PHY_DX6GCR0_CALBYP_SHIFT 31 -#define DDR_PHY_DX6GCR0_CALBYP_MASK 0x80000000U +#define DDR_PHY_DX6GCR0_CALBYP_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_CALBYP_SHIFT 31 +#define DDR_PHY_DX6GCR0_CALBYP_MASK 0x80000000U -/*Master Delay Line Enable*/ +/* +* Master Delay Line Enable +*/ #undef DDR_PHY_DX6GCR0_MDLEN_DEFVAL #undef DDR_PHY_DX6GCR0_MDLEN_SHIFT #undef DDR_PHY_DX6GCR0_MDLEN_MASK -#define DDR_PHY_DX6GCR0_MDLEN_DEFVAL 0x40200204 -#define DDR_PHY_DX6GCR0_MDLEN_SHIFT 30 -#define DDR_PHY_DX6GCR0_MDLEN_MASK 0x40000000U +#define DDR_PHY_DX6GCR0_MDLEN_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_MDLEN_SHIFT 30 +#define DDR_PHY_DX6GCR0_MDLEN_MASK 0x40000000U -/*Configurable ODT(TE) Phase Shift*/ +/* +* Configurable ODT(TE) Phase Shift +*/ #undef DDR_PHY_DX6GCR0_CODTSHFT_DEFVAL #undef DDR_PHY_DX6GCR0_CODTSHFT_SHIFT #undef DDR_PHY_DX6GCR0_CODTSHFT_MASK -#define DDR_PHY_DX6GCR0_CODTSHFT_DEFVAL 0x40200204 -#define DDR_PHY_DX6GCR0_CODTSHFT_SHIFT 28 -#define DDR_PHY_DX6GCR0_CODTSHFT_MASK 0x30000000U +#define DDR_PHY_DX6GCR0_CODTSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_CODTSHFT_SHIFT 28 +#define DDR_PHY_DX6GCR0_CODTSHFT_MASK 0x30000000U -/*DQS Duty Cycle Correction*/ +/* +* DQS Duty Cycle Correction +*/ #undef DDR_PHY_DX6GCR0_DQSDCC_DEFVAL #undef DDR_PHY_DX6GCR0_DQSDCC_SHIFT #undef DDR_PHY_DX6GCR0_DQSDCC_MASK -#define DDR_PHY_DX6GCR0_DQSDCC_DEFVAL 0x40200204 -#define DDR_PHY_DX6GCR0_DQSDCC_SHIFT 24 -#define DDR_PHY_DX6GCR0_DQSDCC_MASK 0x0F000000U +#define DDR_PHY_DX6GCR0_DQSDCC_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_DQSDCC_SHIFT 24 +#define DDR_PHY_DX6GCR0_DQSDCC_MASK 0x0F000000U -/*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/ +/* +* Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY +*/ #undef DDR_PHY_DX6GCR0_RDDLY_DEFVAL #undef DDR_PHY_DX6GCR0_RDDLY_SHIFT #undef DDR_PHY_DX6GCR0_RDDLY_MASK -#define DDR_PHY_DX6GCR0_RDDLY_DEFVAL 0x40200204 -#define DDR_PHY_DX6GCR0_RDDLY_SHIFT 20 -#define DDR_PHY_DX6GCR0_RDDLY_MASK 0x00F00000U +#define DDR_PHY_DX6GCR0_RDDLY_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_RDDLY_SHIFT 20 +#define DDR_PHY_DX6GCR0_RDDLY_MASK 0x00F00000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX6GCR0_RESERVED_19_14_DEFVAL #undef DDR_PHY_DX6GCR0_RESERVED_19_14_SHIFT #undef DDR_PHY_DX6GCR0_RESERVED_19_14_MASK -#define DDR_PHY_DX6GCR0_RESERVED_19_14_DEFVAL 0x40200204 -#define DDR_PHY_DX6GCR0_RESERVED_19_14_SHIFT 14 -#define DDR_PHY_DX6GCR0_RESERVED_19_14_MASK 0x000FC000U +#define DDR_PHY_DX6GCR0_RESERVED_19_14_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_RESERVED_19_14_SHIFT 14 +#define DDR_PHY_DX6GCR0_RESERVED_19_14_MASK 0x000FC000U -/*DQSNSE Power Down Receiver*/ +/* +* DQSNSE Power Down Receiver +*/ #undef DDR_PHY_DX6GCR0_DQSNSEPDR_DEFVAL #undef DDR_PHY_DX6GCR0_DQSNSEPDR_SHIFT #undef DDR_PHY_DX6GCR0_DQSNSEPDR_MASK -#define DDR_PHY_DX6GCR0_DQSNSEPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX6GCR0_DQSNSEPDR_SHIFT 13 -#define DDR_PHY_DX6GCR0_DQSNSEPDR_MASK 0x00002000U +#define DDR_PHY_DX6GCR0_DQSNSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_DQSNSEPDR_SHIFT 13 +#define DDR_PHY_DX6GCR0_DQSNSEPDR_MASK 0x00002000U -/*DQSSE Power Down Receiver*/ +/* +* DQSSE Power Down Receiver +*/ #undef DDR_PHY_DX6GCR0_DQSSEPDR_DEFVAL #undef DDR_PHY_DX6GCR0_DQSSEPDR_SHIFT #undef DDR_PHY_DX6GCR0_DQSSEPDR_MASK -#define DDR_PHY_DX6GCR0_DQSSEPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX6GCR0_DQSSEPDR_SHIFT 12 -#define DDR_PHY_DX6GCR0_DQSSEPDR_MASK 0x00001000U +#define DDR_PHY_DX6GCR0_DQSSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_DQSSEPDR_SHIFT 12 +#define DDR_PHY_DX6GCR0_DQSSEPDR_MASK 0x00001000U -/*RTT On Additive Latency*/ +/* +* RTT On Additive Latency +*/ #undef DDR_PHY_DX6GCR0_RTTOAL_DEFVAL #undef DDR_PHY_DX6GCR0_RTTOAL_SHIFT #undef DDR_PHY_DX6GCR0_RTTOAL_MASK -#define DDR_PHY_DX6GCR0_RTTOAL_DEFVAL 0x40200204 -#define DDR_PHY_DX6GCR0_RTTOAL_SHIFT 11 -#define DDR_PHY_DX6GCR0_RTTOAL_MASK 0x00000800U +#define DDR_PHY_DX6GCR0_RTTOAL_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_RTTOAL_SHIFT 11 +#define DDR_PHY_DX6GCR0_RTTOAL_MASK 0x00000800U -/*RTT Output Hold*/ +/* +* RTT Output Hold +*/ #undef DDR_PHY_DX6GCR0_RTTOH_DEFVAL #undef DDR_PHY_DX6GCR0_RTTOH_SHIFT #undef DDR_PHY_DX6GCR0_RTTOH_MASK -#define DDR_PHY_DX6GCR0_RTTOH_DEFVAL 0x40200204 -#define DDR_PHY_DX6GCR0_RTTOH_SHIFT 9 -#define DDR_PHY_DX6GCR0_RTTOH_MASK 0x00000600U +#define DDR_PHY_DX6GCR0_RTTOH_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_RTTOH_SHIFT 9 +#define DDR_PHY_DX6GCR0_RTTOH_MASK 0x00000600U -/*Configurable PDR Phase Shift*/ +/* +* Configurable PDR Phase Shift +*/ #undef DDR_PHY_DX6GCR0_CPDRSHFT_DEFVAL #undef DDR_PHY_DX6GCR0_CPDRSHFT_SHIFT #undef DDR_PHY_DX6GCR0_CPDRSHFT_MASK -#define DDR_PHY_DX6GCR0_CPDRSHFT_DEFVAL 0x40200204 -#define DDR_PHY_DX6GCR0_CPDRSHFT_SHIFT 7 -#define DDR_PHY_DX6GCR0_CPDRSHFT_MASK 0x00000180U +#define DDR_PHY_DX6GCR0_CPDRSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_CPDRSHFT_SHIFT 7 +#define DDR_PHY_DX6GCR0_CPDRSHFT_MASK 0x00000180U -/*DQSR Power Down*/ +/* +* DQSR Power Down +*/ #undef DDR_PHY_DX6GCR0_DQSRPD_DEFVAL #undef DDR_PHY_DX6GCR0_DQSRPD_SHIFT #undef DDR_PHY_DX6GCR0_DQSRPD_MASK -#define DDR_PHY_DX6GCR0_DQSRPD_DEFVAL 0x40200204 -#define DDR_PHY_DX6GCR0_DQSRPD_SHIFT 6 -#define DDR_PHY_DX6GCR0_DQSRPD_MASK 0x00000040U +#define DDR_PHY_DX6GCR0_DQSRPD_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_DQSRPD_SHIFT 6 +#define DDR_PHY_DX6GCR0_DQSRPD_MASK 0x00000040U -/*DQSG Power Down Receiver*/ +/* +* DQSG Power Down Receiver +*/ #undef DDR_PHY_DX6GCR0_DQSGPDR_DEFVAL #undef DDR_PHY_DX6GCR0_DQSGPDR_SHIFT #undef DDR_PHY_DX6GCR0_DQSGPDR_MASK -#define DDR_PHY_DX6GCR0_DQSGPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX6GCR0_DQSGPDR_SHIFT 5 -#define DDR_PHY_DX6GCR0_DQSGPDR_MASK 0x00000020U +#define DDR_PHY_DX6GCR0_DQSGPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_DQSGPDR_SHIFT 5 +#define DDR_PHY_DX6GCR0_DQSGPDR_MASK 0x00000020U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX6GCR0_RESERVED_4_DEFVAL #undef DDR_PHY_DX6GCR0_RESERVED_4_SHIFT #undef DDR_PHY_DX6GCR0_RESERVED_4_MASK -#define DDR_PHY_DX6GCR0_RESERVED_4_DEFVAL 0x40200204 -#define DDR_PHY_DX6GCR0_RESERVED_4_SHIFT 4 -#define DDR_PHY_DX6GCR0_RESERVED_4_MASK 0x00000010U +#define DDR_PHY_DX6GCR0_RESERVED_4_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_RESERVED_4_SHIFT 4 +#define DDR_PHY_DX6GCR0_RESERVED_4_MASK 0x00000010U -/*DQSG On-Die Termination*/ +/* +* DQSG On-Die Termination +*/ #undef DDR_PHY_DX6GCR0_DQSGODT_DEFVAL #undef DDR_PHY_DX6GCR0_DQSGODT_SHIFT #undef DDR_PHY_DX6GCR0_DQSGODT_MASK -#define DDR_PHY_DX6GCR0_DQSGODT_DEFVAL 0x40200204 -#define DDR_PHY_DX6GCR0_DQSGODT_SHIFT 3 -#define DDR_PHY_DX6GCR0_DQSGODT_MASK 0x00000008U +#define DDR_PHY_DX6GCR0_DQSGODT_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_DQSGODT_SHIFT 3 +#define DDR_PHY_DX6GCR0_DQSGODT_MASK 0x00000008U -/*DQSG Output Enable*/ +/* +* DQSG Output Enable +*/ #undef DDR_PHY_DX6GCR0_DQSGOE_DEFVAL #undef DDR_PHY_DX6GCR0_DQSGOE_SHIFT #undef DDR_PHY_DX6GCR0_DQSGOE_MASK -#define DDR_PHY_DX6GCR0_DQSGOE_DEFVAL 0x40200204 -#define DDR_PHY_DX6GCR0_DQSGOE_SHIFT 2 -#define DDR_PHY_DX6GCR0_DQSGOE_MASK 0x00000004U +#define DDR_PHY_DX6GCR0_DQSGOE_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_DQSGOE_SHIFT 2 +#define DDR_PHY_DX6GCR0_DQSGOE_MASK 0x00000004U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX6GCR0_RESERVED_1_0_DEFVAL #undef DDR_PHY_DX6GCR0_RESERVED_1_0_SHIFT #undef DDR_PHY_DX6GCR0_RESERVED_1_0_MASK -#define DDR_PHY_DX6GCR0_RESERVED_1_0_DEFVAL 0x40200204 -#define DDR_PHY_DX6GCR0_RESERVED_1_0_SHIFT 0 -#define DDR_PHY_DX6GCR0_RESERVED_1_0_MASK 0x00000003U +#define DDR_PHY_DX6GCR0_RESERVED_1_0_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_RESERVED_1_0_SHIFT 0 +#define DDR_PHY_DX6GCR0_RESERVED_1_0_MASK 0x00000003U -/*Enables the PDR mode for DQ[7:0]*/ +/* +* Enables the PDR mode for DQ[7:0] +*/ #undef DDR_PHY_DX6GCR1_DXPDRMODE_DEFVAL #undef DDR_PHY_DX6GCR1_DXPDRMODE_SHIFT #undef DDR_PHY_DX6GCR1_DXPDRMODE_MASK -#define DDR_PHY_DX6GCR1_DXPDRMODE_DEFVAL 0x00007FFF -#define DDR_PHY_DX6GCR1_DXPDRMODE_SHIFT 16 -#define DDR_PHY_DX6GCR1_DXPDRMODE_MASK 0xFFFF0000U +#define DDR_PHY_DX6GCR1_DXPDRMODE_DEFVAL 0x00007FFF +#define DDR_PHY_DX6GCR1_DXPDRMODE_SHIFT 16 +#define DDR_PHY_DX6GCR1_DXPDRMODE_MASK 0xFFFF0000U -/*Reserved. Returns zeroes on reads.*/ +/* +* Reserved. Returns zeroes on reads. +*/ #undef DDR_PHY_DX6GCR1_RESERVED_15_DEFVAL #undef DDR_PHY_DX6GCR1_RESERVED_15_SHIFT #undef DDR_PHY_DX6GCR1_RESERVED_15_MASK -#define DDR_PHY_DX6GCR1_RESERVED_15_DEFVAL 0x00007FFF -#define DDR_PHY_DX6GCR1_RESERVED_15_SHIFT 15 -#define DDR_PHY_DX6GCR1_RESERVED_15_MASK 0x00008000U +#define DDR_PHY_DX6GCR1_RESERVED_15_DEFVAL 0x00007FFF +#define DDR_PHY_DX6GCR1_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX6GCR1_RESERVED_15_MASK 0x00008000U -/*Select the delayed or non-delayed read data strobe #*/ +/* +* Select the delayed or non-delayed read data strobe # +*/ #undef DDR_PHY_DX6GCR1_QSNSEL_DEFVAL #undef DDR_PHY_DX6GCR1_QSNSEL_SHIFT #undef DDR_PHY_DX6GCR1_QSNSEL_MASK -#define DDR_PHY_DX6GCR1_QSNSEL_DEFVAL 0x00007FFF -#define DDR_PHY_DX6GCR1_QSNSEL_SHIFT 14 -#define DDR_PHY_DX6GCR1_QSNSEL_MASK 0x00004000U +#define DDR_PHY_DX6GCR1_QSNSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX6GCR1_QSNSEL_SHIFT 14 +#define DDR_PHY_DX6GCR1_QSNSEL_MASK 0x00004000U -/*Select the delayed or non-delayed read data strobe*/ +/* +* Select the delayed or non-delayed read data strobe +*/ #undef DDR_PHY_DX6GCR1_QSSEL_DEFVAL #undef DDR_PHY_DX6GCR1_QSSEL_SHIFT #undef DDR_PHY_DX6GCR1_QSSEL_MASK -#define DDR_PHY_DX6GCR1_QSSEL_DEFVAL 0x00007FFF -#define DDR_PHY_DX6GCR1_QSSEL_SHIFT 13 -#define DDR_PHY_DX6GCR1_QSSEL_MASK 0x00002000U +#define DDR_PHY_DX6GCR1_QSSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX6GCR1_QSSEL_SHIFT 13 +#define DDR_PHY_DX6GCR1_QSSEL_MASK 0x00002000U -/*Enables Read Data Strobe in a byte lane*/ +/* +* Enables Read Data Strobe in a byte lane +*/ #undef DDR_PHY_DX6GCR1_OEEN_DEFVAL #undef DDR_PHY_DX6GCR1_OEEN_SHIFT #undef DDR_PHY_DX6GCR1_OEEN_MASK -#define DDR_PHY_DX6GCR1_OEEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX6GCR1_OEEN_SHIFT 12 -#define DDR_PHY_DX6GCR1_OEEN_MASK 0x00001000U +#define DDR_PHY_DX6GCR1_OEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX6GCR1_OEEN_SHIFT 12 +#define DDR_PHY_DX6GCR1_OEEN_MASK 0x00001000U -/*Enables PDR in a byte lane*/ +/* +* Enables PDR in a byte lane +*/ #undef DDR_PHY_DX6GCR1_PDREN_DEFVAL #undef DDR_PHY_DX6GCR1_PDREN_SHIFT #undef DDR_PHY_DX6GCR1_PDREN_MASK -#define DDR_PHY_DX6GCR1_PDREN_DEFVAL 0x00007FFF -#define DDR_PHY_DX6GCR1_PDREN_SHIFT 11 -#define DDR_PHY_DX6GCR1_PDREN_MASK 0x00000800U +#define DDR_PHY_DX6GCR1_PDREN_DEFVAL 0x00007FFF +#define DDR_PHY_DX6GCR1_PDREN_SHIFT 11 +#define DDR_PHY_DX6GCR1_PDREN_MASK 0x00000800U -/*Enables ODT/TE in a byte lane*/ +/* +* Enables ODT/TE in a byte lane +*/ #undef DDR_PHY_DX6GCR1_TEEN_DEFVAL #undef DDR_PHY_DX6GCR1_TEEN_SHIFT #undef DDR_PHY_DX6GCR1_TEEN_MASK -#define DDR_PHY_DX6GCR1_TEEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX6GCR1_TEEN_SHIFT 10 -#define DDR_PHY_DX6GCR1_TEEN_MASK 0x00000400U +#define DDR_PHY_DX6GCR1_TEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX6GCR1_TEEN_SHIFT 10 +#define DDR_PHY_DX6GCR1_TEEN_MASK 0x00000400U -/*Enables Write Data strobe in a byte lane*/ +/* +* Enables Write Data strobe in a byte lane +*/ #undef DDR_PHY_DX6GCR1_DSEN_DEFVAL #undef DDR_PHY_DX6GCR1_DSEN_SHIFT #undef DDR_PHY_DX6GCR1_DSEN_MASK -#define DDR_PHY_DX6GCR1_DSEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX6GCR1_DSEN_SHIFT 9 -#define DDR_PHY_DX6GCR1_DSEN_MASK 0x00000200U +#define DDR_PHY_DX6GCR1_DSEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX6GCR1_DSEN_SHIFT 9 +#define DDR_PHY_DX6GCR1_DSEN_MASK 0x00000200U -/*Enables DM pin in a byte lane*/ +/* +* Enables DM pin in a byte lane +*/ #undef DDR_PHY_DX6GCR1_DMEN_DEFVAL #undef DDR_PHY_DX6GCR1_DMEN_SHIFT #undef DDR_PHY_DX6GCR1_DMEN_MASK -#define DDR_PHY_DX6GCR1_DMEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX6GCR1_DMEN_SHIFT 8 -#define DDR_PHY_DX6GCR1_DMEN_MASK 0x00000100U +#define DDR_PHY_DX6GCR1_DMEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX6GCR1_DMEN_SHIFT 8 +#define DDR_PHY_DX6GCR1_DMEN_MASK 0x00000100U -/*Enables DQ corresponding to each bit in a byte*/ +/* +* Enables DQ corresponding to each bit in a byte +*/ #undef DDR_PHY_DX6GCR1_DQEN_DEFVAL #undef DDR_PHY_DX6GCR1_DQEN_SHIFT #undef DDR_PHY_DX6GCR1_DQEN_MASK -#define DDR_PHY_DX6GCR1_DQEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX6GCR1_DQEN_SHIFT 0 -#define DDR_PHY_DX6GCR1_DQEN_MASK 0x000000FFU +#define DDR_PHY_DX6GCR1_DQEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX6GCR1_DQEN_SHIFT 0 +#define DDR_PHY_DX6GCR1_DQEN_MASK 0x000000FFU -/*Byte lane VREF IOM (Used only by D4MU IOs)*/ +/* +* Byte lane VREF IOM (Used only by D4MU IOs) +*/ #undef DDR_PHY_DX6GCR4_RESERVED_31_29_DEFVAL #undef DDR_PHY_DX6GCR4_RESERVED_31_29_SHIFT #undef DDR_PHY_DX6GCR4_RESERVED_31_29_MASK -#define DDR_PHY_DX6GCR4_RESERVED_31_29_DEFVAL 0x0E00003C -#define DDR_PHY_DX6GCR4_RESERVED_31_29_SHIFT 29 -#define DDR_PHY_DX6GCR4_RESERVED_31_29_MASK 0xE0000000U +#define DDR_PHY_DX6GCR4_RESERVED_31_29_DEFVAL 0x0E00003C +#define DDR_PHY_DX6GCR4_RESERVED_31_29_SHIFT 29 +#define DDR_PHY_DX6GCR4_RESERVED_31_29_MASK 0xE0000000U -/*Byte Lane VREF Pad Enable*/ +/* +* Byte Lane VREF Pad Enable +*/ #undef DDR_PHY_DX6GCR4_DXREFPEN_DEFVAL #undef DDR_PHY_DX6GCR4_DXREFPEN_SHIFT #undef DDR_PHY_DX6GCR4_DXREFPEN_MASK -#define DDR_PHY_DX6GCR4_DXREFPEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX6GCR4_DXREFPEN_SHIFT 28 -#define DDR_PHY_DX6GCR4_DXREFPEN_MASK 0x10000000U +#define DDR_PHY_DX6GCR4_DXREFPEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX6GCR4_DXREFPEN_SHIFT 28 +#define DDR_PHY_DX6GCR4_DXREFPEN_MASK 0x10000000U -/*Byte Lane Internal VREF Enable*/ +/* +* Byte Lane Internal VREF Enable +*/ #undef DDR_PHY_DX6GCR4_DXREFEEN_DEFVAL #undef DDR_PHY_DX6GCR4_DXREFEEN_SHIFT #undef DDR_PHY_DX6GCR4_DXREFEEN_MASK -#define DDR_PHY_DX6GCR4_DXREFEEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX6GCR4_DXREFEEN_SHIFT 26 -#define DDR_PHY_DX6GCR4_DXREFEEN_MASK 0x0C000000U +#define DDR_PHY_DX6GCR4_DXREFEEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX6GCR4_DXREFEEN_SHIFT 26 +#define DDR_PHY_DX6GCR4_DXREFEEN_MASK 0x0C000000U -/*Byte Lane Single-End VREF Enable*/ +/* +* Byte Lane Single-End VREF Enable +*/ #undef DDR_PHY_DX6GCR4_DXREFSEN_DEFVAL #undef DDR_PHY_DX6GCR4_DXREFSEN_SHIFT #undef DDR_PHY_DX6GCR4_DXREFSEN_MASK -#define DDR_PHY_DX6GCR4_DXREFSEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX6GCR4_DXREFSEN_SHIFT 25 -#define DDR_PHY_DX6GCR4_DXREFSEN_MASK 0x02000000U +#define DDR_PHY_DX6GCR4_DXREFSEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX6GCR4_DXREFSEN_SHIFT 25 +#define DDR_PHY_DX6GCR4_DXREFSEN_MASK 0x02000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX6GCR4_RESERVED_24_DEFVAL #undef DDR_PHY_DX6GCR4_RESERVED_24_SHIFT #undef DDR_PHY_DX6GCR4_RESERVED_24_MASK -#define DDR_PHY_DX6GCR4_RESERVED_24_DEFVAL 0x0E00003C -#define DDR_PHY_DX6GCR4_RESERVED_24_SHIFT 24 -#define DDR_PHY_DX6GCR4_RESERVED_24_MASK 0x01000000U +#define DDR_PHY_DX6GCR4_RESERVED_24_DEFVAL 0x0E00003C +#define DDR_PHY_DX6GCR4_RESERVED_24_SHIFT 24 +#define DDR_PHY_DX6GCR4_RESERVED_24_MASK 0x01000000U -/*External VREF generator REFSEL range select*/ +/* +* External VREF generator REFSEL range select +*/ #undef DDR_PHY_DX6GCR4_DXREFESELRANGE_DEFVAL #undef DDR_PHY_DX6GCR4_DXREFESELRANGE_SHIFT #undef DDR_PHY_DX6GCR4_DXREFESELRANGE_MASK -#define DDR_PHY_DX6GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C -#define DDR_PHY_DX6GCR4_DXREFESELRANGE_SHIFT 23 -#define DDR_PHY_DX6GCR4_DXREFESELRANGE_MASK 0x00800000U +#define DDR_PHY_DX6GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX6GCR4_DXREFESELRANGE_SHIFT 23 +#define DDR_PHY_DX6GCR4_DXREFESELRANGE_MASK 0x00800000U -/*Byte Lane External VREF Select*/ +/* +* Byte Lane External VREF Select +*/ #undef DDR_PHY_DX6GCR4_DXREFESEL_DEFVAL #undef DDR_PHY_DX6GCR4_DXREFESEL_SHIFT #undef DDR_PHY_DX6GCR4_DXREFESEL_MASK -#define DDR_PHY_DX6GCR4_DXREFESEL_DEFVAL 0x0E00003C -#define DDR_PHY_DX6GCR4_DXREFESEL_SHIFT 16 -#define DDR_PHY_DX6GCR4_DXREFESEL_MASK 0x007F0000U +#define DDR_PHY_DX6GCR4_DXREFESEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX6GCR4_DXREFESEL_SHIFT 16 +#define DDR_PHY_DX6GCR4_DXREFESEL_MASK 0x007F0000U -/*Single ended VREF generator REFSEL range select*/ +/* +* Single ended VREF generator REFSEL range select +*/ #undef DDR_PHY_DX6GCR4_DXREFSSELRANGE_DEFVAL #undef DDR_PHY_DX6GCR4_DXREFSSELRANGE_SHIFT #undef DDR_PHY_DX6GCR4_DXREFSSELRANGE_MASK -#define DDR_PHY_DX6GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C -#define DDR_PHY_DX6GCR4_DXREFSSELRANGE_SHIFT 15 -#define DDR_PHY_DX6GCR4_DXREFSSELRANGE_MASK 0x00008000U +#define DDR_PHY_DX6GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX6GCR4_DXREFSSELRANGE_SHIFT 15 +#define DDR_PHY_DX6GCR4_DXREFSSELRANGE_MASK 0x00008000U -/*Byte Lane Single-End VREF Select*/ +/* +* Byte Lane Single-End VREF Select +*/ #undef DDR_PHY_DX6GCR4_DXREFSSEL_DEFVAL #undef DDR_PHY_DX6GCR4_DXREFSSEL_SHIFT #undef DDR_PHY_DX6GCR4_DXREFSSEL_MASK -#define DDR_PHY_DX6GCR4_DXREFSSEL_DEFVAL 0x0E00003C -#define DDR_PHY_DX6GCR4_DXREFSSEL_SHIFT 8 -#define DDR_PHY_DX6GCR4_DXREFSSEL_MASK 0x00007F00U +#define DDR_PHY_DX6GCR4_DXREFSSEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX6GCR4_DXREFSSEL_SHIFT 8 +#define DDR_PHY_DX6GCR4_DXREFSSEL_MASK 0x00007F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX6GCR4_RESERVED_7_6_DEFVAL #undef DDR_PHY_DX6GCR4_RESERVED_7_6_SHIFT #undef DDR_PHY_DX6GCR4_RESERVED_7_6_MASK -#define DDR_PHY_DX6GCR4_RESERVED_7_6_DEFVAL 0x0E00003C -#define DDR_PHY_DX6GCR4_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_DX6GCR4_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_DX6GCR4_RESERVED_7_6_DEFVAL 0x0E00003C +#define DDR_PHY_DX6GCR4_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX6GCR4_RESERVED_7_6_MASK 0x000000C0U -/*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/ +/* +* VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. +*/ #undef DDR_PHY_DX6GCR4_DXREFIEN_DEFVAL #undef DDR_PHY_DX6GCR4_DXREFIEN_SHIFT #undef DDR_PHY_DX6GCR4_DXREFIEN_MASK -#define DDR_PHY_DX6GCR4_DXREFIEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX6GCR4_DXREFIEN_SHIFT 2 -#define DDR_PHY_DX6GCR4_DXREFIEN_MASK 0x0000003CU +#define DDR_PHY_DX6GCR4_DXREFIEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX6GCR4_DXREFIEN_SHIFT 2 +#define DDR_PHY_DX6GCR4_DXREFIEN_MASK 0x0000003CU -/*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/ +/* +* VRMON control for DQ IO (Single Ended) buffers of a byte lane. +*/ #undef DDR_PHY_DX6GCR4_DXREFIMON_DEFVAL #undef DDR_PHY_DX6GCR4_DXREFIMON_SHIFT #undef DDR_PHY_DX6GCR4_DXREFIMON_MASK -#define DDR_PHY_DX6GCR4_DXREFIMON_DEFVAL 0x0E00003C -#define DDR_PHY_DX6GCR4_DXREFIMON_SHIFT 0 -#define DDR_PHY_DX6GCR4_DXREFIMON_MASK 0x00000003U +#define DDR_PHY_DX6GCR4_DXREFIMON_DEFVAL 0x0E00003C +#define DDR_PHY_DX6GCR4_DXREFIMON_SHIFT 0 +#define DDR_PHY_DX6GCR4_DXREFIMON_MASK 0x00000003U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX6GCR5_RESERVED_31_DEFVAL #undef DDR_PHY_DX6GCR5_RESERVED_31_SHIFT #undef DDR_PHY_DX6GCR5_RESERVED_31_MASK -#define DDR_PHY_DX6GCR5_RESERVED_31_DEFVAL 0x09090909 -#define DDR_PHY_DX6GCR5_RESERVED_31_SHIFT 31 -#define DDR_PHY_DX6GCR5_RESERVED_31_MASK 0x80000000U +#define DDR_PHY_DX6GCR5_RESERVED_31_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR5_RESERVED_31_SHIFT 31 +#define DDR_PHY_DX6GCR5_RESERVED_31_MASK 0x80000000U -/*Byte Lane internal VREF Select for Rank 3*/ +/* +* Byte Lane internal VREF Select for Rank 3 +*/ #undef DDR_PHY_DX6GCR5_DXREFISELR3_DEFVAL #undef DDR_PHY_DX6GCR5_DXREFISELR3_SHIFT #undef DDR_PHY_DX6GCR5_DXREFISELR3_MASK -#define DDR_PHY_DX6GCR5_DXREFISELR3_DEFVAL 0x09090909 -#define DDR_PHY_DX6GCR5_DXREFISELR3_SHIFT 24 -#define DDR_PHY_DX6GCR5_DXREFISELR3_MASK 0x7F000000U +#define DDR_PHY_DX6GCR5_DXREFISELR3_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR5_DXREFISELR3_SHIFT 24 +#define DDR_PHY_DX6GCR5_DXREFISELR3_MASK 0x7F000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX6GCR5_RESERVED_23_DEFVAL #undef DDR_PHY_DX6GCR5_RESERVED_23_SHIFT #undef DDR_PHY_DX6GCR5_RESERVED_23_MASK -#define DDR_PHY_DX6GCR5_RESERVED_23_DEFVAL 0x09090909 -#define DDR_PHY_DX6GCR5_RESERVED_23_SHIFT 23 -#define DDR_PHY_DX6GCR5_RESERVED_23_MASK 0x00800000U +#define DDR_PHY_DX6GCR5_RESERVED_23_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR5_RESERVED_23_SHIFT 23 +#define DDR_PHY_DX6GCR5_RESERVED_23_MASK 0x00800000U -/*Byte Lane internal VREF Select for Rank 2*/ +/* +* Byte Lane internal VREF Select for Rank 2 +*/ #undef DDR_PHY_DX6GCR5_DXREFISELR2_DEFVAL #undef DDR_PHY_DX6GCR5_DXREFISELR2_SHIFT #undef DDR_PHY_DX6GCR5_DXREFISELR2_MASK -#define DDR_PHY_DX6GCR5_DXREFISELR2_DEFVAL 0x09090909 -#define DDR_PHY_DX6GCR5_DXREFISELR2_SHIFT 16 -#define DDR_PHY_DX6GCR5_DXREFISELR2_MASK 0x007F0000U +#define DDR_PHY_DX6GCR5_DXREFISELR2_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR5_DXREFISELR2_SHIFT 16 +#define DDR_PHY_DX6GCR5_DXREFISELR2_MASK 0x007F0000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX6GCR5_RESERVED_15_DEFVAL #undef DDR_PHY_DX6GCR5_RESERVED_15_SHIFT #undef DDR_PHY_DX6GCR5_RESERVED_15_MASK -#define DDR_PHY_DX6GCR5_RESERVED_15_DEFVAL 0x09090909 -#define DDR_PHY_DX6GCR5_RESERVED_15_SHIFT 15 -#define DDR_PHY_DX6GCR5_RESERVED_15_MASK 0x00008000U +#define DDR_PHY_DX6GCR5_RESERVED_15_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR5_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX6GCR5_RESERVED_15_MASK 0x00008000U -/*Byte Lane internal VREF Select for Rank 1*/ +/* +* Byte Lane internal VREF Select for Rank 1 +*/ #undef DDR_PHY_DX6GCR5_DXREFISELR1_DEFVAL #undef DDR_PHY_DX6GCR5_DXREFISELR1_SHIFT #undef DDR_PHY_DX6GCR5_DXREFISELR1_MASK -#define DDR_PHY_DX6GCR5_DXREFISELR1_DEFVAL 0x09090909 -#define DDR_PHY_DX6GCR5_DXREFISELR1_SHIFT 8 -#define DDR_PHY_DX6GCR5_DXREFISELR1_MASK 0x00007F00U +#define DDR_PHY_DX6GCR5_DXREFISELR1_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR5_DXREFISELR1_SHIFT 8 +#define DDR_PHY_DX6GCR5_DXREFISELR1_MASK 0x00007F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX6GCR5_RESERVED_7_DEFVAL #undef DDR_PHY_DX6GCR5_RESERVED_7_SHIFT #undef DDR_PHY_DX6GCR5_RESERVED_7_MASK -#define DDR_PHY_DX6GCR5_RESERVED_7_DEFVAL 0x09090909 -#define DDR_PHY_DX6GCR5_RESERVED_7_SHIFT 7 -#define DDR_PHY_DX6GCR5_RESERVED_7_MASK 0x00000080U +#define DDR_PHY_DX6GCR5_RESERVED_7_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR5_RESERVED_7_SHIFT 7 +#define DDR_PHY_DX6GCR5_RESERVED_7_MASK 0x00000080U -/*Byte Lane internal VREF Select for Rank 0*/ +/* +* Byte Lane internal VREF Select for Rank 0 +*/ #undef DDR_PHY_DX6GCR5_DXREFISELR0_DEFVAL #undef DDR_PHY_DX6GCR5_DXREFISELR0_SHIFT #undef DDR_PHY_DX6GCR5_DXREFISELR0_MASK -#define DDR_PHY_DX6GCR5_DXREFISELR0_DEFVAL 0x09090909 -#define DDR_PHY_DX6GCR5_DXREFISELR0_SHIFT 0 -#define DDR_PHY_DX6GCR5_DXREFISELR0_MASK 0x0000007FU +#define DDR_PHY_DX6GCR5_DXREFISELR0_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR5_DXREFISELR0_SHIFT 0 +#define DDR_PHY_DX6GCR5_DXREFISELR0_MASK 0x0000007FU -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX6GCR6_RESERVED_31_30_DEFVAL #undef DDR_PHY_DX6GCR6_RESERVED_31_30_SHIFT #undef DDR_PHY_DX6GCR6_RESERVED_31_30_MASK -#define DDR_PHY_DX6GCR6_RESERVED_31_30_DEFVAL 0x09090909 -#define DDR_PHY_DX6GCR6_RESERVED_31_30_SHIFT 30 -#define DDR_PHY_DX6GCR6_RESERVED_31_30_MASK 0xC0000000U +#define DDR_PHY_DX6GCR6_RESERVED_31_30_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR6_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX6GCR6_RESERVED_31_30_MASK 0xC0000000U -/*DRAM DQ VREF Select for Rank3*/ +/* +* DRAM DQ VREF Select for Rank3 +*/ #undef DDR_PHY_DX6GCR6_DXDQVREFR3_DEFVAL #undef DDR_PHY_DX6GCR6_DXDQVREFR3_SHIFT #undef DDR_PHY_DX6GCR6_DXDQVREFR3_MASK -#define DDR_PHY_DX6GCR6_DXDQVREFR3_DEFVAL 0x09090909 -#define DDR_PHY_DX6GCR6_DXDQVREFR3_SHIFT 24 -#define DDR_PHY_DX6GCR6_DXDQVREFR3_MASK 0x3F000000U +#define DDR_PHY_DX6GCR6_DXDQVREFR3_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR6_DXDQVREFR3_SHIFT 24 +#define DDR_PHY_DX6GCR6_DXDQVREFR3_MASK 0x3F000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX6GCR6_RESERVED_23_22_DEFVAL #undef DDR_PHY_DX6GCR6_RESERVED_23_22_SHIFT #undef DDR_PHY_DX6GCR6_RESERVED_23_22_MASK -#define DDR_PHY_DX6GCR6_RESERVED_23_22_DEFVAL 0x09090909 -#define DDR_PHY_DX6GCR6_RESERVED_23_22_SHIFT 22 -#define DDR_PHY_DX6GCR6_RESERVED_23_22_MASK 0x00C00000U +#define DDR_PHY_DX6GCR6_RESERVED_23_22_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR6_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX6GCR6_RESERVED_23_22_MASK 0x00C00000U -/*DRAM DQ VREF Select for Rank2*/ +/* +* DRAM DQ VREF Select for Rank2 +*/ #undef DDR_PHY_DX6GCR6_DXDQVREFR2_DEFVAL #undef DDR_PHY_DX6GCR6_DXDQVREFR2_SHIFT #undef DDR_PHY_DX6GCR6_DXDQVREFR2_MASK -#define DDR_PHY_DX6GCR6_DXDQVREFR2_DEFVAL 0x09090909 -#define DDR_PHY_DX6GCR6_DXDQVREFR2_SHIFT 16 -#define DDR_PHY_DX6GCR6_DXDQVREFR2_MASK 0x003F0000U +#define DDR_PHY_DX6GCR6_DXDQVREFR2_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR6_DXDQVREFR2_SHIFT 16 +#define DDR_PHY_DX6GCR6_DXDQVREFR2_MASK 0x003F0000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX6GCR6_RESERVED_15_14_DEFVAL #undef DDR_PHY_DX6GCR6_RESERVED_15_14_SHIFT #undef DDR_PHY_DX6GCR6_RESERVED_15_14_MASK -#define DDR_PHY_DX6GCR6_RESERVED_15_14_DEFVAL 0x09090909 -#define DDR_PHY_DX6GCR6_RESERVED_15_14_SHIFT 14 -#define DDR_PHY_DX6GCR6_RESERVED_15_14_MASK 0x0000C000U +#define DDR_PHY_DX6GCR6_RESERVED_15_14_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR6_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_DX6GCR6_RESERVED_15_14_MASK 0x0000C000U -/*DRAM DQ VREF Select for Rank1*/ +/* +* DRAM DQ VREF Select for Rank1 +*/ #undef DDR_PHY_DX6GCR6_DXDQVREFR1_DEFVAL #undef DDR_PHY_DX6GCR6_DXDQVREFR1_SHIFT #undef DDR_PHY_DX6GCR6_DXDQVREFR1_MASK -#define DDR_PHY_DX6GCR6_DXDQVREFR1_DEFVAL 0x09090909 -#define DDR_PHY_DX6GCR6_DXDQVREFR1_SHIFT 8 -#define DDR_PHY_DX6GCR6_DXDQVREFR1_MASK 0x00003F00U +#define DDR_PHY_DX6GCR6_DXDQVREFR1_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR6_DXDQVREFR1_SHIFT 8 +#define DDR_PHY_DX6GCR6_DXDQVREFR1_MASK 0x00003F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX6GCR6_RESERVED_7_6_DEFVAL #undef DDR_PHY_DX6GCR6_RESERVED_7_6_SHIFT #undef DDR_PHY_DX6GCR6_RESERVED_7_6_MASK -#define DDR_PHY_DX6GCR6_RESERVED_7_6_DEFVAL 0x09090909 -#define DDR_PHY_DX6GCR6_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_DX6GCR6_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_DX6GCR6_RESERVED_7_6_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR6_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX6GCR6_RESERVED_7_6_MASK 0x000000C0U -/*DRAM DQ VREF Select for Rank0*/ +/* +* DRAM DQ VREF Select for Rank0 +*/ #undef DDR_PHY_DX6GCR6_DXDQVREFR0_DEFVAL #undef DDR_PHY_DX6GCR6_DXDQVREFR0_SHIFT #undef DDR_PHY_DX6GCR6_DXDQVREFR0_MASK -#define DDR_PHY_DX6GCR6_DXDQVREFR0_DEFVAL 0x09090909 -#define DDR_PHY_DX6GCR6_DXDQVREFR0_SHIFT 0 -#define DDR_PHY_DX6GCR6_DXDQVREFR0_MASK 0x0000003FU +#define DDR_PHY_DX6GCR6_DXDQVREFR0_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR6_DXDQVREFR0_SHIFT 0 +#define DDR_PHY_DX6GCR6_DXDQVREFR0_MASK 0x0000003FU -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX6LCDLR2_RESERVED_31_25_DEFVAL -#undef DDR_PHY_DX6LCDLR2_RESERVED_31_25_SHIFT -#undef DDR_PHY_DX6LCDLR2_RESERVED_31_25_MASK -#define DDR_PHY_DX6LCDLR2_RESERVED_31_25_DEFVAL 0x00000000 -#define DDR_PHY_DX6LCDLR2_RESERVED_31_25_SHIFT 25 -#define DDR_PHY_DX6LCDLR2_RESERVED_31_25_MASK 0xFE000000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX6LCDLR2_RESERVED_24_16_DEFVAL -#undef DDR_PHY_DX6LCDLR2_RESERVED_24_16_SHIFT -#undef DDR_PHY_DX6LCDLR2_RESERVED_24_16_MASK -#define DDR_PHY_DX6LCDLR2_RESERVED_24_16_DEFVAL 0x00000000 -#define DDR_PHY_DX6LCDLR2_RESERVED_24_16_SHIFT 16 -#define DDR_PHY_DX6LCDLR2_RESERVED_24_16_MASK 0x01FF0000U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX6LCDLR2_RESERVED_15_9_DEFVAL -#undef DDR_PHY_DX6LCDLR2_RESERVED_15_9_SHIFT -#undef DDR_PHY_DX6LCDLR2_RESERVED_15_9_MASK -#define DDR_PHY_DX6LCDLR2_RESERVED_15_9_DEFVAL 0x00000000 -#define DDR_PHY_DX6LCDLR2_RESERVED_15_9_SHIFT 9 -#define DDR_PHY_DX6LCDLR2_RESERVED_15_9_MASK 0x0000FE00U - -/*Read DQS Gating Delay*/ -#undef DDR_PHY_DX6LCDLR2_DQSGD_DEFVAL -#undef DDR_PHY_DX6LCDLR2_DQSGD_SHIFT -#undef DDR_PHY_DX6LCDLR2_DQSGD_MASK -#define DDR_PHY_DX6LCDLR2_DQSGD_DEFVAL 0x00000000 -#define DDR_PHY_DX6LCDLR2_DQSGD_SHIFT 0 -#define DDR_PHY_DX6LCDLR2_DQSGD_MASK 0x000001FFU - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX6GTR0_RESERVED_31_24_DEFVAL -#undef DDR_PHY_DX6GTR0_RESERVED_31_24_SHIFT -#undef DDR_PHY_DX6GTR0_RESERVED_31_24_MASK -#define DDR_PHY_DX6GTR0_RESERVED_31_24_DEFVAL 0x00020000 -#define DDR_PHY_DX6GTR0_RESERVED_31_24_SHIFT 27 -#define DDR_PHY_DX6GTR0_RESERVED_31_24_MASK 0xF8000000U - -/*DQ Write Path Latency Pipeline*/ -#undef DDR_PHY_DX6GTR0_WDQSL_DEFVAL -#undef DDR_PHY_DX6GTR0_WDQSL_SHIFT -#undef DDR_PHY_DX6GTR0_WDQSL_MASK -#define DDR_PHY_DX6GTR0_WDQSL_DEFVAL 0x00020000 -#define DDR_PHY_DX6GTR0_WDQSL_SHIFT 24 -#define DDR_PHY_DX6GTR0_WDQSL_MASK 0x07000000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX6GTR0_RESERVED_23_20_DEFVAL -#undef DDR_PHY_DX6GTR0_RESERVED_23_20_SHIFT -#undef DDR_PHY_DX6GTR0_RESERVED_23_20_MASK -#define DDR_PHY_DX6GTR0_RESERVED_23_20_DEFVAL 0x00020000 -#define DDR_PHY_DX6GTR0_RESERVED_23_20_SHIFT 20 -#define DDR_PHY_DX6GTR0_RESERVED_23_20_MASK 0x00F00000U - -/*Write Leveling System Latency*/ -#undef DDR_PHY_DX6GTR0_WLSL_DEFVAL -#undef DDR_PHY_DX6GTR0_WLSL_SHIFT -#undef DDR_PHY_DX6GTR0_WLSL_MASK -#define DDR_PHY_DX6GTR0_WLSL_DEFVAL 0x00020000 -#define DDR_PHY_DX6GTR0_WLSL_SHIFT 16 -#define DDR_PHY_DX6GTR0_WLSL_MASK 0x000F0000U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX6GTR0_RESERVED_15_13_DEFVAL -#undef DDR_PHY_DX6GTR0_RESERVED_15_13_SHIFT -#undef DDR_PHY_DX6GTR0_RESERVED_15_13_MASK -#define DDR_PHY_DX6GTR0_RESERVED_15_13_DEFVAL 0x00020000 -#define DDR_PHY_DX6GTR0_RESERVED_15_13_SHIFT 13 -#define DDR_PHY_DX6GTR0_RESERVED_15_13_MASK 0x0000E000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX6GTR0_RESERVED_12_8_DEFVAL -#undef DDR_PHY_DX6GTR0_RESERVED_12_8_SHIFT -#undef DDR_PHY_DX6GTR0_RESERVED_12_8_MASK -#define DDR_PHY_DX6GTR0_RESERVED_12_8_DEFVAL 0x00020000 -#define DDR_PHY_DX6GTR0_RESERVED_12_8_SHIFT 8 -#define DDR_PHY_DX6GTR0_RESERVED_12_8_MASK 0x00001F00U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX6GTR0_RESERVED_7_5_DEFVAL -#undef DDR_PHY_DX6GTR0_RESERVED_7_5_SHIFT -#undef DDR_PHY_DX6GTR0_RESERVED_7_5_MASK -#define DDR_PHY_DX6GTR0_RESERVED_7_5_DEFVAL 0x00020000 -#define DDR_PHY_DX6GTR0_RESERVED_7_5_SHIFT 5 -#define DDR_PHY_DX6GTR0_RESERVED_7_5_MASK 0x000000E0U - -/*DQS Gating System Latency*/ -#undef DDR_PHY_DX6GTR0_DGSL_DEFVAL -#undef DDR_PHY_DX6GTR0_DGSL_SHIFT -#undef DDR_PHY_DX6GTR0_DGSL_MASK -#define DDR_PHY_DX6GTR0_DGSL_DEFVAL 0x00020000 -#define DDR_PHY_DX6GTR0_DGSL_SHIFT 0 -#define DDR_PHY_DX6GTR0_DGSL_MASK 0x0000001FU - -/*Calibration Bypass*/ +/* +* Calibration Bypass +*/ #undef DDR_PHY_DX7GCR0_CALBYP_DEFVAL #undef DDR_PHY_DX7GCR0_CALBYP_SHIFT #undef DDR_PHY_DX7GCR0_CALBYP_MASK -#define DDR_PHY_DX7GCR0_CALBYP_DEFVAL 0x40200204 -#define DDR_PHY_DX7GCR0_CALBYP_SHIFT 31 -#define DDR_PHY_DX7GCR0_CALBYP_MASK 0x80000000U +#define DDR_PHY_DX7GCR0_CALBYP_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_CALBYP_SHIFT 31 +#define DDR_PHY_DX7GCR0_CALBYP_MASK 0x80000000U -/*Master Delay Line Enable*/ +/* +* Master Delay Line Enable +*/ #undef DDR_PHY_DX7GCR0_MDLEN_DEFVAL #undef DDR_PHY_DX7GCR0_MDLEN_SHIFT #undef DDR_PHY_DX7GCR0_MDLEN_MASK -#define DDR_PHY_DX7GCR0_MDLEN_DEFVAL 0x40200204 -#define DDR_PHY_DX7GCR0_MDLEN_SHIFT 30 -#define DDR_PHY_DX7GCR0_MDLEN_MASK 0x40000000U +#define DDR_PHY_DX7GCR0_MDLEN_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_MDLEN_SHIFT 30 +#define DDR_PHY_DX7GCR0_MDLEN_MASK 0x40000000U -/*Configurable ODT(TE) Phase Shift*/ +/* +* Configurable ODT(TE) Phase Shift +*/ #undef DDR_PHY_DX7GCR0_CODTSHFT_DEFVAL #undef DDR_PHY_DX7GCR0_CODTSHFT_SHIFT #undef DDR_PHY_DX7GCR0_CODTSHFT_MASK -#define DDR_PHY_DX7GCR0_CODTSHFT_DEFVAL 0x40200204 -#define DDR_PHY_DX7GCR0_CODTSHFT_SHIFT 28 -#define DDR_PHY_DX7GCR0_CODTSHFT_MASK 0x30000000U +#define DDR_PHY_DX7GCR0_CODTSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_CODTSHFT_SHIFT 28 +#define DDR_PHY_DX7GCR0_CODTSHFT_MASK 0x30000000U -/*DQS Duty Cycle Correction*/ +/* +* DQS Duty Cycle Correction +*/ #undef DDR_PHY_DX7GCR0_DQSDCC_DEFVAL #undef DDR_PHY_DX7GCR0_DQSDCC_SHIFT #undef DDR_PHY_DX7GCR0_DQSDCC_MASK -#define DDR_PHY_DX7GCR0_DQSDCC_DEFVAL 0x40200204 -#define DDR_PHY_DX7GCR0_DQSDCC_SHIFT 24 -#define DDR_PHY_DX7GCR0_DQSDCC_MASK 0x0F000000U +#define DDR_PHY_DX7GCR0_DQSDCC_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_DQSDCC_SHIFT 24 +#define DDR_PHY_DX7GCR0_DQSDCC_MASK 0x0F000000U -/*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/ +/* +* Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY +*/ #undef DDR_PHY_DX7GCR0_RDDLY_DEFVAL #undef DDR_PHY_DX7GCR0_RDDLY_SHIFT #undef DDR_PHY_DX7GCR0_RDDLY_MASK -#define DDR_PHY_DX7GCR0_RDDLY_DEFVAL 0x40200204 -#define DDR_PHY_DX7GCR0_RDDLY_SHIFT 20 -#define DDR_PHY_DX7GCR0_RDDLY_MASK 0x00F00000U +#define DDR_PHY_DX7GCR0_RDDLY_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_RDDLY_SHIFT 20 +#define DDR_PHY_DX7GCR0_RDDLY_MASK 0x00F00000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX7GCR0_RESERVED_19_14_DEFVAL #undef DDR_PHY_DX7GCR0_RESERVED_19_14_SHIFT #undef DDR_PHY_DX7GCR0_RESERVED_19_14_MASK -#define DDR_PHY_DX7GCR0_RESERVED_19_14_DEFVAL 0x40200204 -#define DDR_PHY_DX7GCR0_RESERVED_19_14_SHIFT 14 -#define DDR_PHY_DX7GCR0_RESERVED_19_14_MASK 0x000FC000U +#define DDR_PHY_DX7GCR0_RESERVED_19_14_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_RESERVED_19_14_SHIFT 14 +#define DDR_PHY_DX7GCR0_RESERVED_19_14_MASK 0x000FC000U -/*DQSNSE Power Down Receiver*/ +/* +* DQSNSE Power Down Receiver +*/ #undef DDR_PHY_DX7GCR0_DQSNSEPDR_DEFVAL #undef DDR_PHY_DX7GCR0_DQSNSEPDR_SHIFT #undef DDR_PHY_DX7GCR0_DQSNSEPDR_MASK -#define DDR_PHY_DX7GCR0_DQSNSEPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX7GCR0_DQSNSEPDR_SHIFT 13 -#define DDR_PHY_DX7GCR0_DQSNSEPDR_MASK 0x00002000U +#define DDR_PHY_DX7GCR0_DQSNSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_DQSNSEPDR_SHIFT 13 +#define DDR_PHY_DX7GCR0_DQSNSEPDR_MASK 0x00002000U -/*DQSSE Power Down Receiver*/ +/* +* DQSSE Power Down Receiver +*/ #undef DDR_PHY_DX7GCR0_DQSSEPDR_DEFVAL #undef DDR_PHY_DX7GCR0_DQSSEPDR_SHIFT #undef DDR_PHY_DX7GCR0_DQSSEPDR_MASK -#define DDR_PHY_DX7GCR0_DQSSEPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX7GCR0_DQSSEPDR_SHIFT 12 -#define DDR_PHY_DX7GCR0_DQSSEPDR_MASK 0x00001000U +#define DDR_PHY_DX7GCR0_DQSSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_DQSSEPDR_SHIFT 12 +#define DDR_PHY_DX7GCR0_DQSSEPDR_MASK 0x00001000U -/*RTT On Additive Latency*/ +/* +* RTT On Additive Latency +*/ #undef DDR_PHY_DX7GCR0_RTTOAL_DEFVAL #undef DDR_PHY_DX7GCR0_RTTOAL_SHIFT #undef DDR_PHY_DX7GCR0_RTTOAL_MASK -#define DDR_PHY_DX7GCR0_RTTOAL_DEFVAL 0x40200204 -#define DDR_PHY_DX7GCR0_RTTOAL_SHIFT 11 -#define DDR_PHY_DX7GCR0_RTTOAL_MASK 0x00000800U +#define DDR_PHY_DX7GCR0_RTTOAL_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_RTTOAL_SHIFT 11 +#define DDR_PHY_DX7GCR0_RTTOAL_MASK 0x00000800U -/*RTT Output Hold*/ +/* +* RTT Output Hold +*/ #undef DDR_PHY_DX7GCR0_RTTOH_DEFVAL #undef DDR_PHY_DX7GCR0_RTTOH_SHIFT #undef DDR_PHY_DX7GCR0_RTTOH_MASK -#define DDR_PHY_DX7GCR0_RTTOH_DEFVAL 0x40200204 -#define DDR_PHY_DX7GCR0_RTTOH_SHIFT 9 -#define DDR_PHY_DX7GCR0_RTTOH_MASK 0x00000600U +#define DDR_PHY_DX7GCR0_RTTOH_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_RTTOH_SHIFT 9 +#define DDR_PHY_DX7GCR0_RTTOH_MASK 0x00000600U -/*Configurable PDR Phase Shift*/ +/* +* Configurable PDR Phase Shift +*/ #undef DDR_PHY_DX7GCR0_CPDRSHFT_DEFVAL #undef DDR_PHY_DX7GCR0_CPDRSHFT_SHIFT #undef DDR_PHY_DX7GCR0_CPDRSHFT_MASK -#define DDR_PHY_DX7GCR0_CPDRSHFT_DEFVAL 0x40200204 -#define DDR_PHY_DX7GCR0_CPDRSHFT_SHIFT 7 -#define DDR_PHY_DX7GCR0_CPDRSHFT_MASK 0x00000180U +#define DDR_PHY_DX7GCR0_CPDRSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_CPDRSHFT_SHIFT 7 +#define DDR_PHY_DX7GCR0_CPDRSHFT_MASK 0x00000180U -/*DQSR Power Down*/ +/* +* DQSR Power Down +*/ #undef DDR_PHY_DX7GCR0_DQSRPD_DEFVAL #undef DDR_PHY_DX7GCR0_DQSRPD_SHIFT #undef DDR_PHY_DX7GCR0_DQSRPD_MASK -#define DDR_PHY_DX7GCR0_DQSRPD_DEFVAL 0x40200204 -#define DDR_PHY_DX7GCR0_DQSRPD_SHIFT 6 -#define DDR_PHY_DX7GCR0_DQSRPD_MASK 0x00000040U +#define DDR_PHY_DX7GCR0_DQSRPD_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_DQSRPD_SHIFT 6 +#define DDR_PHY_DX7GCR0_DQSRPD_MASK 0x00000040U -/*DQSG Power Down Receiver*/ +/* +* DQSG Power Down Receiver +*/ #undef DDR_PHY_DX7GCR0_DQSGPDR_DEFVAL #undef DDR_PHY_DX7GCR0_DQSGPDR_SHIFT #undef DDR_PHY_DX7GCR0_DQSGPDR_MASK -#define DDR_PHY_DX7GCR0_DQSGPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX7GCR0_DQSGPDR_SHIFT 5 -#define DDR_PHY_DX7GCR0_DQSGPDR_MASK 0x00000020U +#define DDR_PHY_DX7GCR0_DQSGPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_DQSGPDR_SHIFT 5 +#define DDR_PHY_DX7GCR0_DQSGPDR_MASK 0x00000020U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX7GCR0_RESERVED_4_DEFVAL #undef DDR_PHY_DX7GCR0_RESERVED_4_SHIFT #undef DDR_PHY_DX7GCR0_RESERVED_4_MASK -#define DDR_PHY_DX7GCR0_RESERVED_4_DEFVAL 0x40200204 -#define DDR_PHY_DX7GCR0_RESERVED_4_SHIFT 4 -#define DDR_PHY_DX7GCR0_RESERVED_4_MASK 0x00000010U +#define DDR_PHY_DX7GCR0_RESERVED_4_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_RESERVED_4_SHIFT 4 +#define DDR_PHY_DX7GCR0_RESERVED_4_MASK 0x00000010U -/*DQSG On-Die Termination*/ +/* +* DQSG On-Die Termination +*/ #undef DDR_PHY_DX7GCR0_DQSGODT_DEFVAL #undef DDR_PHY_DX7GCR0_DQSGODT_SHIFT #undef DDR_PHY_DX7GCR0_DQSGODT_MASK -#define DDR_PHY_DX7GCR0_DQSGODT_DEFVAL 0x40200204 -#define DDR_PHY_DX7GCR0_DQSGODT_SHIFT 3 -#define DDR_PHY_DX7GCR0_DQSGODT_MASK 0x00000008U +#define DDR_PHY_DX7GCR0_DQSGODT_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_DQSGODT_SHIFT 3 +#define DDR_PHY_DX7GCR0_DQSGODT_MASK 0x00000008U -/*DQSG Output Enable*/ +/* +* DQSG Output Enable +*/ #undef DDR_PHY_DX7GCR0_DQSGOE_DEFVAL #undef DDR_PHY_DX7GCR0_DQSGOE_SHIFT #undef DDR_PHY_DX7GCR0_DQSGOE_MASK -#define DDR_PHY_DX7GCR0_DQSGOE_DEFVAL 0x40200204 -#define DDR_PHY_DX7GCR0_DQSGOE_SHIFT 2 -#define DDR_PHY_DX7GCR0_DQSGOE_MASK 0x00000004U +#define DDR_PHY_DX7GCR0_DQSGOE_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_DQSGOE_SHIFT 2 +#define DDR_PHY_DX7GCR0_DQSGOE_MASK 0x00000004U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX7GCR0_RESERVED_1_0_DEFVAL #undef DDR_PHY_DX7GCR0_RESERVED_1_0_SHIFT #undef DDR_PHY_DX7GCR0_RESERVED_1_0_MASK -#define DDR_PHY_DX7GCR0_RESERVED_1_0_DEFVAL 0x40200204 -#define DDR_PHY_DX7GCR0_RESERVED_1_0_SHIFT 0 -#define DDR_PHY_DX7GCR0_RESERVED_1_0_MASK 0x00000003U +#define DDR_PHY_DX7GCR0_RESERVED_1_0_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_RESERVED_1_0_SHIFT 0 +#define DDR_PHY_DX7GCR0_RESERVED_1_0_MASK 0x00000003U -/*Enables the PDR mode for DQ[7:0]*/ +/* +* Enables the PDR mode for DQ[7:0] +*/ #undef DDR_PHY_DX7GCR1_DXPDRMODE_DEFVAL #undef DDR_PHY_DX7GCR1_DXPDRMODE_SHIFT #undef DDR_PHY_DX7GCR1_DXPDRMODE_MASK -#define DDR_PHY_DX7GCR1_DXPDRMODE_DEFVAL 0x00007FFF -#define DDR_PHY_DX7GCR1_DXPDRMODE_SHIFT 16 -#define DDR_PHY_DX7GCR1_DXPDRMODE_MASK 0xFFFF0000U +#define DDR_PHY_DX7GCR1_DXPDRMODE_DEFVAL 0x00007FFF +#define DDR_PHY_DX7GCR1_DXPDRMODE_SHIFT 16 +#define DDR_PHY_DX7GCR1_DXPDRMODE_MASK 0xFFFF0000U -/*Reserved. Returns zeroes on reads.*/ +/* +* Reserved. Returns zeroes on reads. +*/ #undef DDR_PHY_DX7GCR1_RESERVED_15_DEFVAL #undef DDR_PHY_DX7GCR1_RESERVED_15_SHIFT #undef DDR_PHY_DX7GCR1_RESERVED_15_MASK -#define DDR_PHY_DX7GCR1_RESERVED_15_DEFVAL 0x00007FFF -#define DDR_PHY_DX7GCR1_RESERVED_15_SHIFT 15 -#define DDR_PHY_DX7GCR1_RESERVED_15_MASK 0x00008000U +#define DDR_PHY_DX7GCR1_RESERVED_15_DEFVAL 0x00007FFF +#define DDR_PHY_DX7GCR1_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX7GCR1_RESERVED_15_MASK 0x00008000U -/*Select the delayed or non-delayed read data strobe #*/ +/* +* Select the delayed or non-delayed read data strobe # +*/ #undef DDR_PHY_DX7GCR1_QSNSEL_DEFVAL #undef DDR_PHY_DX7GCR1_QSNSEL_SHIFT #undef DDR_PHY_DX7GCR1_QSNSEL_MASK -#define DDR_PHY_DX7GCR1_QSNSEL_DEFVAL 0x00007FFF -#define DDR_PHY_DX7GCR1_QSNSEL_SHIFT 14 -#define DDR_PHY_DX7GCR1_QSNSEL_MASK 0x00004000U +#define DDR_PHY_DX7GCR1_QSNSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX7GCR1_QSNSEL_SHIFT 14 +#define DDR_PHY_DX7GCR1_QSNSEL_MASK 0x00004000U -/*Select the delayed or non-delayed read data strobe*/ +/* +* Select the delayed or non-delayed read data strobe +*/ #undef DDR_PHY_DX7GCR1_QSSEL_DEFVAL #undef DDR_PHY_DX7GCR1_QSSEL_SHIFT #undef DDR_PHY_DX7GCR1_QSSEL_MASK -#define DDR_PHY_DX7GCR1_QSSEL_DEFVAL 0x00007FFF -#define DDR_PHY_DX7GCR1_QSSEL_SHIFT 13 -#define DDR_PHY_DX7GCR1_QSSEL_MASK 0x00002000U +#define DDR_PHY_DX7GCR1_QSSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX7GCR1_QSSEL_SHIFT 13 +#define DDR_PHY_DX7GCR1_QSSEL_MASK 0x00002000U -/*Enables Read Data Strobe in a byte lane*/ +/* +* Enables Read Data Strobe in a byte lane +*/ #undef DDR_PHY_DX7GCR1_OEEN_DEFVAL #undef DDR_PHY_DX7GCR1_OEEN_SHIFT #undef DDR_PHY_DX7GCR1_OEEN_MASK -#define DDR_PHY_DX7GCR1_OEEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX7GCR1_OEEN_SHIFT 12 -#define DDR_PHY_DX7GCR1_OEEN_MASK 0x00001000U +#define DDR_PHY_DX7GCR1_OEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX7GCR1_OEEN_SHIFT 12 +#define DDR_PHY_DX7GCR1_OEEN_MASK 0x00001000U -/*Enables PDR in a byte lane*/ +/* +* Enables PDR in a byte lane +*/ #undef DDR_PHY_DX7GCR1_PDREN_DEFVAL #undef DDR_PHY_DX7GCR1_PDREN_SHIFT #undef DDR_PHY_DX7GCR1_PDREN_MASK -#define DDR_PHY_DX7GCR1_PDREN_DEFVAL 0x00007FFF -#define DDR_PHY_DX7GCR1_PDREN_SHIFT 11 -#define DDR_PHY_DX7GCR1_PDREN_MASK 0x00000800U +#define DDR_PHY_DX7GCR1_PDREN_DEFVAL 0x00007FFF +#define DDR_PHY_DX7GCR1_PDREN_SHIFT 11 +#define DDR_PHY_DX7GCR1_PDREN_MASK 0x00000800U -/*Enables ODT/TE in a byte lane*/ +/* +* Enables ODT/TE in a byte lane +*/ #undef DDR_PHY_DX7GCR1_TEEN_DEFVAL #undef DDR_PHY_DX7GCR1_TEEN_SHIFT #undef DDR_PHY_DX7GCR1_TEEN_MASK -#define DDR_PHY_DX7GCR1_TEEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX7GCR1_TEEN_SHIFT 10 -#define DDR_PHY_DX7GCR1_TEEN_MASK 0x00000400U +#define DDR_PHY_DX7GCR1_TEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX7GCR1_TEEN_SHIFT 10 +#define DDR_PHY_DX7GCR1_TEEN_MASK 0x00000400U -/*Enables Write Data strobe in a byte lane*/ +/* +* Enables Write Data strobe in a byte lane +*/ #undef DDR_PHY_DX7GCR1_DSEN_DEFVAL #undef DDR_PHY_DX7GCR1_DSEN_SHIFT #undef DDR_PHY_DX7GCR1_DSEN_MASK -#define DDR_PHY_DX7GCR1_DSEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX7GCR1_DSEN_SHIFT 9 -#define DDR_PHY_DX7GCR1_DSEN_MASK 0x00000200U +#define DDR_PHY_DX7GCR1_DSEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX7GCR1_DSEN_SHIFT 9 +#define DDR_PHY_DX7GCR1_DSEN_MASK 0x00000200U -/*Enables DM pin in a byte lane*/ +/* +* Enables DM pin in a byte lane +*/ #undef DDR_PHY_DX7GCR1_DMEN_DEFVAL #undef DDR_PHY_DX7GCR1_DMEN_SHIFT #undef DDR_PHY_DX7GCR1_DMEN_MASK -#define DDR_PHY_DX7GCR1_DMEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX7GCR1_DMEN_SHIFT 8 -#define DDR_PHY_DX7GCR1_DMEN_MASK 0x00000100U +#define DDR_PHY_DX7GCR1_DMEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX7GCR1_DMEN_SHIFT 8 +#define DDR_PHY_DX7GCR1_DMEN_MASK 0x00000100U -/*Enables DQ corresponding to each bit in a byte*/ +/* +* Enables DQ corresponding to each bit in a byte +*/ #undef DDR_PHY_DX7GCR1_DQEN_DEFVAL #undef DDR_PHY_DX7GCR1_DQEN_SHIFT #undef DDR_PHY_DX7GCR1_DQEN_MASK -#define DDR_PHY_DX7GCR1_DQEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX7GCR1_DQEN_SHIFT 0 -#define DDR_PHY_DX7GCR1_DQEN_MASK 0x000000FFU +#define DDR_PHY_DX7GCR1_DQEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX7GCR1_DQEN_SHIFT 0 +#define DDR_PHY_DX7GCR1_DQEN_MASK 0x000000FFU -/*Byte lane VREF IOM (Used only by D4MU IOs)*/ +/* +* Byte lane VREF IOM (Used only by D4MU IOs) +*/ #undef DDR_PHY_DX7GCR4_RESERVED_31_29_DEFVAL #undef DDR_PHY_DX7GCR4_RESERVED_31_29_SHIFT #undef DDR_PHY_DX7GCR4_RESERVED_31_29_MASK -#define DDR_PHY_DX7GCR4_RESERVED_31_29_DEFVAL 0x0E00003C -#define DDR_PHY_DX7GCR4_RESERVED_31_29_SHIFT 29 -#define DDR_PHY_DX7GCR4_RESERVED_31_29_MASK 0xE0000000U +#define DDR_PHY_DX7GCR4_RESERVED_31_29_DEFVAL 0x0E00003C +#define DDR_PHY_DX7GCR4_RESERVED_31_29_SHIFT 29 +#define DDR_PHY_DX7GCR4_RESERVED_31_29_MASK 0xE0000000U -/*Byte Lane VREF Pad Enable*/ +/* +* Byte Lane VREF Pad Enable +*/ #undef DDR_PHY_DX7GCR4_DXREFPEN_DEFVAL #undef DDR_PHY_DX7GCR4_DXREFPEN_SHIFT #undef DDR_PHY_DX7GCR4_DXREFPEN_MASK -#define DDR_PHY_DX7GCR4_DXREFPEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX7GCR4_DXREFPEN_SHIFT 28 -#define DDR_PHY_DX7GCR4_DXREFPEN_MASK 0x10000000U +#define DDR_PHY_DX7GCR4_DXREFPEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX7GCR4_DXREFPEN_SHIFT 28 +#define DDR_PHY_DX7GCR4_DXREFPEN_MASK 0x10000000U -/*Byte Lane Internal VREF Enable*/ +/* +* Byte Lane Internal VREF Enable +*/ #undef DDR_PHY_DX7GCR4_DXREFEEN_DEFVAL #undef DDR_PHY_DX7GCR4_DXREFEEN_SHIFT #undef DDR_PHY_DX7GCR4_DXREFEEN_MASK -#define DDR_PHY_DX7GCR4_DXREFEEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX7GCR4_DXREFEEN_SHIFT 26 -#define DDR_PHY_DX7GCR4_DXREFEEN_MASK 0x0C000000U +#define DDR_PHY_DX7GCR4_DXREFEEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX7GCR4_DXREFEEN_SHIFT 26 +#define DDR_PHY_DX7GCR4_DXREFEEN_MASK 0x0C000000U -/*Byte Lane Single-End VREF Enable*/ +/* +* Byte Lane Single-End VREF Enable +*/ #undef DDR_PHY_DX7GCR4_DXREFSEN_DEFVAL #undef DDR_PHY_DX7GCR4_DXREFSEN_SHIFT #undef DDR_PHY_DX7GCR4_DXREFSEN_MASK -#define DDR_PHY_DX7GCR4_DXREFSEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX7GCR4_DXREFSEN_SHIFT 25 -#define DDR_PHY_DX7GCR4_DXREFSEN_MASK 0x02000000U +#define DDR_PHY_DX7GCR4_DXREFSEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX7GCR4_DXREFSEN_SHIFT 25 +#define DDR_PHY_DX7GCR4_DXREFSEN_MASK 0x02000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX7GCR4_RESERVED_24_DEFVAL #undef DDR_PHY_DX7GCR4_RESERVED_24_SHIFT #undef DDR_PHY_DX7GCR4_RESERVED_24_MASK -#define DDR_PHY_DX7GCR4_RESERVED_24_DEFVAL 0x0E00003C -#define DDR_PHY_DX7GCR4_RESERVED_24_SHIFT 24 -#define DDR_PHY_DX7GCR4_RESERVED_24_MASK 0x01000000U +#define DDR_PHY_DX7GCR4_RESERVED_24_DEFVAL 0x0E00003C +#define DDR_PHY_DX7GCR4_RESERVED_24_SHIFT 24 +#define DDR_PHY_DX7GCR4_RESERVED_24_MASK 0x01000000U -/*External VREF generator REFSEL range select*/ +/* +* External VREF generator REFSEL range select +*/ #undef DDR_PHY_DX7GCR4_DXREFESELRANGE_DEFVAL #undef DDR_PHY_DX7GCR4_DXREFESELRANGE_SHIFT #undef DDR_PHY_DX7GCR4_DXREFESELRANGE_MASK -#define DDR_PHY_DX7GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C -#define DDR_PHY_DX7GCR4_DXREFESELRANGE_SHIFT 23 -#define DDR_PHY_DX7GCR4_DXREFESELRANGE_MASK 0x00800000U +#define DDR_PHY_DX7GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX7GCR4_DXREFESELRANGE_SHIFT 23 +#define DDR_PHY_DX7GCR4_DXREFESELRANGE_MASK 0x00800000U -/*Byte Lane External VREF Select*/ +/* +* Byte Lane External VREF Select +*/ #undef DDR_PHY_DX7GCR4_DXREFESEL_DEFVAL #undef DDR_PHY_DX7GCR4_DXREFESEL_SHIFT #undef DDR_PHY_DX7GCR4_DXREFESEL_MASK -#define DDR_PHY_DX7GCR4_DXREFESEL_DEFVAL 0x0E00003C -#define DDR_PHY_DX7GCR4_DXREFESEL_SHIFT 16 -#define DDR_PHY_DX7GCR4_DXREFESEL_MASK 0x007F0000U +#define DDR_PHY_DX7GCR4_DXREFESEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX7GCR4_DXREFESEL_SHIFT 16 +#define DDR_PHY_DX7GCR4_DXREFESEL_MASK 0x007F0000U -/*Single ended VREF generator REFSEL range select*/ +/* +* Single ended VREF generator REFSEL range select +*/ #undef DDR_PHY_DX7GCR4_DXREFSSELRANGE_DEFVAL #undef DDR_PHY_DX7GCR4_DXREFSSELRANGE_SHIFT #undef DDR_PHY_DX7GCR4_DXREFSSELRANGE_MASK -#define DDR_PHY_DX7GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C -#define DDR_PHY_DX7GCR4_DXREFSSELRANGE_SHIFT 15 -#define DDR_PHY_DX7GCR4_DXREFSSELRANGE_MASK 0x00008000U +#define DDR_PHY_DX7GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX7GCR4_DXREFSSELRANGE_SHIFT 15 +#define DDR_PHY_DX7GCR4_DXREFSSELRANGE_MASK 0x00008000U -/*Byte Lane Single-End VREF Select*/ +/* +* Byte Lane Single-End VREF Select +*/ #undef DDR_PHY_DX7GCR4_DXREFSSEL_DEFVAL #undef DDR_PHY_DX7GCR4_DXREFSSEL_SHIFT #undef DDR_PHY_DX7GCR4_DXREFSSEL_MASK -#define DDR_PHY_DX7GCR4_DXREFSSEL_DEFVAL 0x0E00003C -#define DDR_PHY_DX7GCR4_DXREFSSEL_SHIFT 8 -#define DDR_PHY_DX7GCR4_DXREFSSEL_MASK 0x00007F00U +#define DDR_PHY_DX7GCR4_DXREFSSEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX7GCR4_DXREFSSEL_SHIFT 8 +#define DDR_PHY_DX7GCR4_DXREFSSEL_MASK 0x00007F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX7GCR4_RESERVED_7_6_DEFVAL #undef DDR_PHY_DX7GCR4_RESERVED_7_6_SHIFT #undef DDR_PHY_DX7GCR4_RESERVED_7_6_MASK -#define DDR_PHY_DX7GCR4_RESERVED_7_6_DEFVAL 0x0E00003C -#define DDR_PHY_DX7GCR4_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_DX7GCR4_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_DX7GCR4_RESERVED_7_6_DEFVAL 0x0E00003C +#define DDR_PHY_DX7GCR4_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX7GCR4_RESERVED_7_6_MASK 0x000000C0U -/*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/ +/* +* VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. +*/ #undef DDR_PHY_DX7GCR4_DXREFIEN_DEFVAL #undef DDR_PHY_DX7GCR4_DXREFIEN_SHIFT #undef DDR_PHY_DX7GCR4_DXREFIEN_MASK -#define DDR_PHY_DX7GCR4_DXREFIEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX7GCR4_DXREFIEN_SHIFT 2 -#define DDR_PHY_DX7GCR4_DXREFIEN_MASK 0x0000003CU +#define DDR_PHY_DX7GCR4_DXREFIEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX7GCR4_DXREFIEN_SHIFT 2 +#define DDR_PHY_DX7GCR4_DXREFIEN_MASK 0x0000003CU -/*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/ +/* +* VRMON control for DQ IO (Single Ended) buffers of a byte lane. +*/ #undef DDR_PHY_DX7GCR4_DXREFIMON_DEFVAL #undef DDR_PHY_DX7GCR4_DXREFIMON_SHIFT #undef DDR_PHY_DX7GCR4_DXREFIMON_MASK -#define DDR_PHY_DX7GCR4_DXREFIMON_DEFVAL 0x0E00003C -#define DDR_PHY_DX7GCR4_DXREFIMON_SHIFT 0 -#define DDR_PHY_DX7GCR4_DXREFIMON_MASK 0x00000003U +#define DDR_PHY_DX7GCR4_DXREFIMON_DEFVAL 0x0E00003C +#define DDR_PHY_DX7GCR4_DXREFIMON_SHIFT 0 +#define DDR_PHY_DX7GCR4_DXREFIMON_MASK 0x00000003U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX7GCR5_RESERVED_31_DEFVAL #undef DDR_PHY_DX7GCR5_RESERVED_31_SHIFT #undef DDR_PHY_DX7GCR5_RESERVED_31_MASK -#define DDR_PHY_DX7GCR5_RESERVED_31_DEFVAL 0x09090909 -#define DDR_PHY_DX7GCR5_RESERVED_31_SHIFT 31 -#define DDR_PHY_DX7GCR5_RESERVED_31_MASK 0x80000000U +#define DDR_PHY_DX7GCR5_RESERVED_31_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR5_RESERVED_31_SHIFT 31 +#define DDR_PHY_DX7GCR5_RESERVED_31_MASK 0x80000000U -/*Byte Lane internal VREF Select for Rank 3*/ +/* +* Byte Lane internal VREF Select for Rank 3 +*/ #undef DDR_PHY_DX7GCR5_DXREFISELR3_DEFVAL #undef DDR_PHY_DX7GCR5_DXREFISELR3_SHIFT #undef DDR_PHY_DX7GCR5_DXREFISELR3_MASK -#define DDR_PHY_DX7GCR5_DXREFISELR3_DEFVAL 0x09090909 -#define DDR_PHY_DX7GCR5_DXREFISELR3_SHIFT 24 -#define DDR_PHY_DX7GCR5_DXREFISELR3_MASK 0x7F000000U +#define DDR_PHY_DX7GCR5_DXREFISELR3_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR5_DXREFISELR3_SHIFT 24 +#define DDR_PHY_DX7GCR5_DXREFISELR3_MASK 0x7F000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX7GCR5_RESERVED_23_DEFVAL #undef DDR_PHY_DX7GCR5_RESERVED_23_SHIFT #undef DDR_PHY_DX7GCR5_RESERVED_23_MASK -#define DDR_PHY_DX7GCR5_RESERVED_23_DEFVAL 0x09090909 -#define DDR_PHY_DX7GCR5_RESERVED_23_SHIFT 23 -#define DDR_PHY_DX7GCR5_RESERVED_23_MASK 0x00800000U +#define DDR_PHY_DX7GCR5_RESERVED_23_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR5_RESERVED_23_SHIFT 23 +#define DDR_PHY_DX7GCR5_RESERVED_23_MASK 0x00800000U -/*Byte Lane internal VREF Select for Rank 2*/ +/* +* Byte Lane internal VREF Select for Rank 2 +*/ #undef DDR_PHY_DX7GCR5_DXREFISELR2_DEFVAL #undef DDR_PHY_DX7GCR5_DXREFISELR2_SHIFT #undef DDR_PHY_DX7GCR5_DXREFISELR2_MASK -#define DDR_PHY_DX7GCR5_DXREFISELR2_DEFVAL 0x09090909 -#define DDR_PHY_DX7GCR5_DXREFISELR2_SHIFT 16 -#define DDR_PHY_DX7GCR5_DXREFISELR2_MASK 0x007F0000U +#define DDR_PHY_DX7GCR5_DXREFISELR2_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR5_DXREFISELR2_SHIFT 16 +#define DDR_PHY_DX7GCR5_DXREFISELR2_MASK 0x007F0000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX7GCR5_RESERVED_15_DEFVAL #undef DDR_PHY_DX7GCR5_RESERVED_15_SHIFT #undef DDR_PHY_DX7GCR5_RESERVED_15_MASK -#define DDR_PHY_DX7GCR5_RESERVED_15_DEFVAL 0x09090909 -#define DDR_PHY_DX7GCR5_RESERVED_15_SHIFT 15 -#define DDR_PHY_DX7GCR5_RESERVED_15_MASK 0x00008000U +#define DDR_PHY_DX7GCR5_RESERVED_15_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR5_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX7GCR5_RESERVED_15_MASK 0x00008000U -/*Byte Lane internal VREF Select for Rank 1*/ +/* +* Byte Lane internal VREF Select for Rank 1 +*/ #undef DDR_PHY_DX7GCR5_DXREFISELR1_DEFVAL #undef DDR_PHY_DX7GCR5_DXREFISELR1_SHIFT #undef DDR_PHY_DX7GCR5_DXREFISELR1_MASK -#define DDR_PHY_DX7GCR5_DXREFISELR1_DEFVAL 0x09090909 -#define DDR_PHY_DX7GCR5_DXREFISELR1_SHIFT 8 -#define DDR_PHY_DX7GCR5_DXREFISELR1_MASK 0x00007F00U +#define DDR_PHY_DX7GCR5_DXREFISELR1_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR5_DXREFISELR1_SHIFT 8 +#define DDR_PHY_DX7GCR5_DXREFISELR1_MASK 0x00007F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX7GCR5_RESERVED_7_DEFVAL #undef DDR_PHY_DX7GCR5_RESERVED_7_SHIFT #undef DDR_PHY_DX7GCR5_RESERVED_7_MASK -#define DDR_PHY_DX7GCR5_RESERVED_7_DEFVAL 0x09090909 -#define DDR_PHY_DX7GCR5_RESERVED_7_SHIFT 7 -#define DDR_PHY_DX7GCR5_RESERVED_7_MASK 0x00000080U +#define DDR_PHY_DX7GCR5_RESERVED_7_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR5_RESERVED_7_SHIFT 7 +#define DDR_PHY_DX7GCR5_RESERVED_7_MASK 0x00000080U -/*Byte Lane internal VREF Select for Rank 0*/ +/* +* Byte Lane internal VREF Select for Rank 0 +*/ #undef DDR_PHY_DX7GCR5_DXREFISELR0_DEFVAL #undef DDR_PHY_DX7GCR5_DXREFISELR0_SHIFT #undef DDR_PHY_DX7GCR5_DXREFISELR0_MASK -#define DDR_PHY_DX7GCR5_DXREFISELR0_DEFVAL 0x09090909 -#define DDR_PHY_DX7GCR5_DXREFISELR0_SHIFT 0 -#define DDR_PHY_DX7GCR5_DXREFISELR0_MASK 0x0000007FU +#define DDR_PHY_DX7GCR5_DXREFISELR0_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR5_DXREFISELR0_SHIFT 0 +#define DDR_PHY_DX7GCR5_DXREFISELR0_MASK 0x0000007FU -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX7GCR6_RESERVED_31_30_DEFVAL #undef DDR_PHY_DX7GCR6_RESERVED_31_30_SHIFT #undef DDR_PHY_DX7GCR6_RESERVED_31_30_MASK -#define DDR_PHY_DX7GCR6_RESERVED_31_30_DEFVAL 0x09090909 -#define DDR_PHY_DX7GCR6_RESERVED_31_30_SHIFT 30 -#define DDR_PHY_DX7GCR6_RESERVED_31_30_MASK 0xC0000000U +#define DDR_PHY_DX7GCR6_RESERVED_31_30_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR6_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX7GCR6_RESERVED_31_30_MASK 0xC0000000U -/*DRAM DQ VREF Select for Rank3*/ +/* +* DRAM DQ VREF Select for Rank3 +*/ #undef DDR_PHY_DX7GCR6_DXDQVREFR3_DEFVAL #undef DDR_PHY_DX7GCR6_DXDQVREFR3_SHIFT #undef DDR_PHY_DX7GCR6_DXDQVREFR3_MASK -#define DDR_PHY_DX7GCR6_DXDQVREFR3_DEFVAL 0x09090909 -#define DDR_PHY_DX7GCR6_DXDQVREFR3_SHIFT 24 -#define DDR_PHY_DX7GCR6_DXDQVREFR3_MASK 0x3F000000U +#define DDR_PHY_DX7GCR6_DXDQVREFR3_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR6_DXDQVREFR3_SHIFT 24 +#define DDR_PHY_DX7GCR6_DXDQVREFR3_MASK 0x3F000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX7GCR6_RESERVED_23_22_DEFVAL #undef DDR_PHY_DX7GCR6_RESERVED_23_22_SHIFT #undef DDR_PHY_DX7GCR6_RESERVED_23_22_MASK -#define DDR_PHY_DX7GCR6_RESERVED_23_22_DEFVAL 0x09090909 -#define DDR_PHY_DX7GCR6_RESERVED_23_22_SHIFT 22 -#define DDR_PHY_DX7GCR6_RESERVED_23_22_MASK 0x00C00000U +#define DDR_PHY_DX7GCR6_RESERVED_23_22_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR6_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX7GCR6_RESERVED_23_22_MASK 0x00C00000U -/*DRAM DQ VREF Select for Rank2*/ +/* +* DRAM DQ VREF Select for Rank2 +*/ #undef DDR_PHY_DX7GCR6_DXDQVREFR2_DEFVAL #undef DDR_PHY_DX7GCR6_DXDQVREFR2_SHIFT #undef DDR_PHY_DX7GCR6_DXDQVREFR2_MASK -#define DDR_PHY_DX7GCR6_DXDQVREFR2_DEFVAL 0x09090909 -#define DDR_PHY_DX7GCR6_DXDQVREFR2_SHIFT 16 -#define DDR_PHY_DX7GCR6_DXDQVREFR2_MASK 0x003F0000U +#define DDR_PHY_DX7GCR6_DXDQVREFR2_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR6_DXDQVREFR2_SHIFT 16 +#define DDR_PHY_DX7GCR6_DXDQVREFR2_MASK 0x003F0000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX7GCR6_RESERVED_15_14_DEFVAL #undef DDR_PHY_DX7GCR6_RESERVED_15_14_SHIFT #undef DDR_PHY_DX7GCR6_RESERVED_15_14_MASK -#define DDR_PHY_DX7GCR6_RESERVED_15_14_DEFVAL 0x09090909 -#define DDR_PHY_DX7GCR6_RESERVED_15_14_SHIFT 14 -#define DDR_PHY_DX7GCR6_RESERVED_15_14_MASK 0x0000C000U +#define DDR_PHY_DX7GCR6_RESERVED_15_14_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR6_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_DX7GCR6_RESERVED_15_14_MASK 0x0000C000U -/*DRAM DQ VREF Select for Rank1*/ +/* +* DRAM DQ VREF Select for Rank1 +*/ #undef DDR_PHY_DX7GCR6_DXDQVREFR1_DEFVAL #undef DDR_PHY_DX7GCR6_DXDQVREFR1_SHIFT #undef DDR_PHY_DX7GCR6_DXDQVREFR1_MASK -#define DDR_PHY_DX7GCR6_DXDQVREFR1_DEFVAL 0x09090909 -#define DDR_PHY_DX7GCR6_DXDQVREFR1_SHIFT 8 -#define DDR_PHY_DX7GCR6_DXDQVREFR1_MASK 0x00003F00U +#define DDR_PHY_DX7GCR6_DXDQVREFR1_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR6_DXDQVREFR1_SHIFT 8 +#define DDR_PHY_DX7GCR6_DXDQVREFR1_MASK 0x00003F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX7GCR6_RESERVED_7_6_DEFVAL #undef DDR_PHY_DX7GCR6_RESERVED_7_6_SHIFT #undef DDR_PHY_DX7GCR6_RESERVED_7_6_MASK -#define DDR_PHY_DX7GCR6_RESERVED_7_6_DEFVAL 0x09090909 -#define DDR_PHY_DX7GCR6_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_DX7GCR6_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_DX7GCR6_RESERVED_7_6_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR6_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX7GCR6_RESERVED_7_6_MASK 0x000000C0U -/*DRAM DQ VREF Select for Rank0*/ +/* +* DRAM DQ VREF Select for Rank0 +*/ #undef DDR_PHY_DX7GCR6_DXDQVREFR0_DEFVAL #undef DDR_PHY_DX7GCR6_DXDQVREFR0_SHIFT #undef DDR_PHY_DX7GCR6_DXDQVREFR0_MASK -#define DDR_PHY_DX7GCR6_DXDQVREFR0_DEFVAL 0x09090909 -#define DDR_PHY_DX7GCR6_DXDQVREFR0_SHIFT 0 -#define DDR_PHY_DX7GCR6_DXDQVREFR0_MASK 0x0000003FU +#define DDR_PHY_DX7GCR6_DXDQVREFR0_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR6_DXDQVREFR0_SHIFT 0 +#define DDR_PHY_DX7GCR6_DXDQVREFR0_MASK 0x0000003FU -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX7LCDLR2_RESERVED_31_25_DEFVAL -#undef DDR_PHY_DX7LCDLR2_RESERVED_31_25_SHIFT -#undef DDR_PHY_DX7LCDLR2_RESERVED_31_25_MASK -#define DDR_PHY_DX7LCDLR2_RESERVED_31_25_DEFVAL 0x00000000 -#define DDR_PHY_DX7LCDLR2_RESERVED_31_25_SHIFT 25 -#define DDR_PHY_DX7LCDLR2_RESERVED_31_25_MASK 0xFE000000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX7LCDLR2_RESERVED_24_16_DEFVAL -#undef DDR_PHY_DX7LCDLR2_RESERVED_24_16_SHIFT -#undef DDR_PHY_DX7LCDLR2_RESERVED_24_16_MASK -#define DDR_PHY_DX7LCDLR2_RESERVED_24_16_DEFVAL 0x00000000 -#define DDR_PHY_DX7LCDLR2_RESERVED_24_16_SHIFT 16 -#define DDR_PHY_DX7LCDLR2_RESERVED_24_16_MASK 0x01FF0000U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX7LCDLR2_RESERVED_15_9_DEFVAL -#undef DDR_PHY_DX7LCDLR2_RESERVED_15_9_SHIFT -#undef DDR_PHY_DX7LCDLR2_RESERVED_15_9_MASK -#define DDR_PHY_DX7LCDLR2_RESERVED_15_9_DEFVAL 0x00000000 -#define DDR_PHY_DX7LCDLR2_RESERVED_15_9_SHIFT 9 -#define DDR_PHY_DX7LCDLR2_RESERVED_15_9_MASK 0x0000FE00U - -/*Read DQS Gating Delay*/ -#undef DDR_PHY_DX7LCDLR2_DQSGD_DEFVAL -#undef DDR_PHY_DX7LCDLR2_DQSGD_SHIFT -#undef DDR_PHY_DX7LCDLR2_DQSGD_MASK -#define DDR_PHY_DX7LCDLR2_DQSGD_DEFVAL 0x00000000 -#define DDR_PHY_DX7LCDLR2_DQSGD_SHIFT 0 -#define DDR_PHY_DX7LCDLR2_DQSGD_MASK 0x000001FFU - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX7GTR0_RESERVED_31_24_DEFVAL -#undef DDR_PHY_DX7GTR0_RESERVED_31_24_SHIFT -#undef DDR_PHY_DX7GTR0_RESERVED_31_24_MASK -#define DDR_PHY_DX7GTR0_RESERVED_31_24_DEFVAL 0x00020000 -#define DDR_PHY_DX7GTR0_RESERVED_31_24_SHIFT 27 -#define DDR_PHY_DX7GTR0_RESERVED_31_24_MASK 0xF8000000U - -/*DQ Write Path Latency Pipeline*/ -#undef DDR_PHY_DX7GTR0_WDQSL_DEFVAL -#undef DDR_PHY_DX7GTR0_WDQSL_SHIFT -#undef DDR_PHY_DX7GTR0_WDQSL_MASK -#define DDR_PHY_DX7GTR0_WDQSL_DEFVAL 0x00020000 -#define DDR_PHY_DX7GTR0_WDQSL_SHIFT 24 -#define DDR_PHY_DX7GTR0_WDQSL_MASK 0x07000000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX7GTR0_RESERVED_23_20_DEFVAL -#undef DDR_PHY_DX7GTR0_RESERVED_23_20_SHIFT -#undef DDR_PHY_DX7GTR0_RESERVED_23_20_MASK -#define DDR_PHY_DX7GTR0_RESERVED_23_20_DEFVAL 0x00020000 -#define DDR_PHY_DX7GTR0_RESERVED_23_20_SHIFT 20 -#define DDR_PHY_DX7GTR0_RESERVED_23_20_MASK 0x00F00000U - -/*Write Leveling System Latency*/ -#undef DDR_PHY_DX7GTR0_WLSL_DEFVAL -#undef DDR_PHY_DX7GTR0_WLSL_SHIFT -#undef DDR_PHY_DX7GTR0_WLSL_MASK -#define DDR_PHY_DX7GTR0_WLSL_DEFVAL 0x00020000 -#define DDR_PHY_DX7GTR0_WLSL_SHIFT 16 -#define DDR_PHY_DX7GTR0_WLSL_MASK 0x000F0000U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX7GTR0_RESERVED_15_13_DEFVAL -#undef DDR_PHY_DX7GTR0_RESERVED_15_13_SHIFT -#undef DDR_PHY_DX7GTR0_RESERVED_15_13_MASK -#define DDR_PHY_DX7GTR0_RESERVED_15_13_DEFVAL 0x00020000 -#define DDR_PHY_DX7GTR0_RESERVED_15_13_SHIFT 13 -#define DDR_PHY_DX7GTR0_RESERVED_15_13_MASK 0x0000E000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX7GTR0_RESERVED_12_8_DEFVAL -#undef DDR_PHY_DX7GTR0_RESERVED_12_8_SHIFT -#undef DDR_PHY_DX7GTR0_RESERVED_12_8_MASK -#define DDR_PHY_DX7GTR0_RESERVED_12_8_DEFVAL 0x00020000 -#define DDR_PHY_DX7GTR0_RESERVED_12_8_SHIFT 8 -#define DDR_PHY_DX7GTR0_RESERVED_12_8_MASK 0x00001F00U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX7GTR0_RESERVED_7_5_DEFVAL -#undef DDR_PHY_DX7GTR0_RESERVED_7_5_SHIFT -#undef DDR_PHY_DX7GTR0_RESERVED_7_5_MASK -#define DDR_PHY_DX7GTR0_RESERVED_7_5_DEFVAL 0x00020000 -#define DDR_PHY_DX7GTR0_RESERVED_7_5_SHIFT 5 -#define DDR_PHY_DX7GTR0_RESERVED_7_5_MASK 0x000000E0U - -/*DQS Gating System Latency*/ -#undef DDR_PHY_DX7GTR0_DGSL_DEFVAL -#undef DDR_PHY_DX7GTR0_DGSL_SHIFT -#undef DDR_PHY_DX7GTR0_DGSL_MASK -#define DDR_PHY_DX7GTR0_DGSL_DEFVAL 0x00020000 -#define DDR_PHY_DX7GTR0_DGSL_SHIFT 0 -#define DDR_PHY_DX7GTR0_DGSL_MASK 0x0000001FU - -/*Calibration Bypass*/ +/* +* Calibration Bypass +*/ #undef DDR_PHY_DX8GCR0_CALBYP_DEFVAL #undef DDR_PHY_DX8GCR0_CALBYP_SHIFT #undef DDR_PHY_DX8GCR0_CALBYP_MASK -#define DDR_PHY_DX8GCR0_CALBYP_DEFVAL 0x40200204 -#define DDR_PHY_DX8GCR0_CALBYP_SHIFT 31 -#define DDR_PHY_DX8GCR0_CALBYP_MASK 0x80000000U +#define DDR_PHY_DX8GCR0_CALBYP_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_CALBYP_SHIFT 31 +#define DDR_PHY_DX8GCR0_CALBYP_MASK 0x80000000U -/*Master Delay Line Enable*/ +/* +* Master Delay Line Enable +*/ #undef DDR_PHY_DX8GCR0_MDLEN_DEFVAL #undef DDR_PHY_DX8GCR0_MDLEN_SHIFT #undef DDR_PHY_DX8GCR0_MDLEN_MASK -#define DDR_PHY_DX8GCR0_MDLEN_DEFVAL 0x40200204 -#define DDR_PHY_DX8GCR0_MDLEN_SHIFT 30 -#define DDR_PHY_DX8GCR0_MDLEN_MASK 0x40000000U +#define DDR_PHY_DX8GCR0_MDLEN_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_MDLEN_SHIFT 30 +#define DDR_PHY_DX8GCR0_MDLEN_MASK 0x40000000U -/*Configurable ODT(TE) Phase Shift*/ +/* +* Configurable ODT(TE) Phase Shift +*/ #undef DDR_PHY_DX8GCR0_CODTSHFT_DEFVAL #undef DDR_PHY_DX8GCR0_CODTSHFT_SHIFT #undef DDR_PHY_DX8GCR0_CODTSHFT_MASK -#define DDR_PHY_DX8GCR0_CODTSHFT_DEFVAL 0x40200204 -#define DDR_PHY_DX8GCR0_CODTSHFT_SHIFT 28 -#define DDR_PHY_DX8GCR0_CODTSHFT_MASK 0x30000000U +#define DDR_PHY_DX8GCR0_CODTSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_CODTSHFT_SHIFT 28 +#define DDR_PHY_DX8GCR0_CODTSHFT_MASK 0x30000000U -/*DQS Duty Cycle Correction*/ +/* +* DQS Duty Cycle Correction +*/ #undef DDR_PHY_DX8GCR0_DQSDCC_DEFVAL #undef DDR_PHY_DX8GCR0_DQSDCC_SHIFT #undef DDR_PHY_DX8GCR0_DQSDCC_MASK -#define DDR_PHY_DX8GCR0_DQSDCC_DEFVAL 0x40200204 -#define DDR_PHY_DX8GCR0_DQSDCC_SHIFT 24 -#define DDR_PHY_DX8GCR0_DQSDCC_MASK 0x0F000000U +#define DDR_PHY_DX8GCR0_DQSDCC_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_DQSDCC_SHIFT 24 +#define DDR_PHY_DX8GCR0_DQSDCC_MASK 0x0F000000U -/*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/ +/* +* Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY +*/ #undef DDR_PHY_DX8GCR0_RDDLY_DEFVAL #undef DDR_PHY_DX8GCR0_RDDLY_SHIFT #undef DDR_PHY_DX8GCR0_RDDLY_MASK -#define DDR_PHY_DX8GCR0_RDDLY_DEFVAL 0x40200204 -#define DDR_PHY_DX8GCR0_RDDLY_SHIFT 20 -#define DDR_PHY_DX8GCR0_RDDLY_MASK 0x00F00000U +#define DDR_PHY_DX8GCR0_RDDLY_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_RDDLY_SHIFT 20 +#define DDR_PHY_DX8GCR0_RDDLY_MASK 0x00F00000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8GCR0_RESERVED_19_14_DEFVAL #undef DDR_PHY_DX8GCR0_RESERVED_19_14_SHIFT #undef DDR_PHY_DX8GCR0_RESERVED_19_14_MASK -#define DDR_PHY_DX8GCR0_RESERVED_19_14_DEFVAL 0x40200204 -#define DDR_PHY_DX8GCR0_RESERVED_19_14_SHIFT 14 -#define DDR_PHY_DX8GCR0_RESERVED_19_14_MASK 0x000FC000U +#define DDR_PHY_DX8GCR0_RESERVED_19_14_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_RESERVED_19_14_SHIFT 14 +#define DDR_PHY_DX8GCR0_RESERVED_19_14_MASK 0x000FC000U -/*DQSNSE Power Down Receiver*/ +/* +* DQSNSE Power Down Receiver +*/ #undef DDR_PHY_DX8GCR0_DQSNSEPDR_DEFVAL #undef DDR_PHY_DX8GCR0_DQSNSEPDR_SHIFT #undef DDR_PHY_DX8GCR0_DQSNSEPDR_MASK -#define DDR_PHY_DX8GCR0_DQSNSEPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX8GCR0_DQSNSEPDR_SHIFT 13 -#define DDR_PHY_DX8GCR0_DQSNSEPDR_MASK 0x00002000U +#define DDR_PHY_DX8GCR0_DQSNSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_DQSNSEPDR_SHIFT 13 +#define DDR_PHY_DX8GCR0_DQSNSEPDR_MASK 0x00002000U -/*DQSSE Power Down Receiver*/ +/* +* DQSSE Power Down Receiver +*/ #undef DDR_PHY_DX8GCR0_DQSSEPDR_DEFVAL #undef DDR_PHY_DX8GCR0_DQSSEPDR_SHIFT #undef DDR_PHY_DX8GCR0_DQSSEPDR_MASK -#define DDR_PHY_DX8GCR0_DQSSEPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX8GCR0_DQSSEPDR_SHIFT 12 -#define DDR_PHY_DX8GCR0_DQSSEPDR_MASK 0x00001000U +#define DDR_PHY_DX8GCR0_DQSSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_DQSSEPDR_SHIFT 12 +#define DDR_PHY_DX8GCR0_DQSSEPDR_MASK 0x00001000U -/*RTT On Additive Latency*/ +/* +* RTT On Additive Latency +*/ #undef DDR_PHY_DX8GCR0_RTTOAL_DEFVAL #undef DDR_PHY_DX8GCR0_RTTOAL_SHIFT #undef DDR_PHY_DX8GCR0_RTTOAL_MASK -#define DDR_PHY_DX8GCR0_RTTOAL_DEFVAL 0x40200204 -#define DDR_PHY_DX8GCR0_RTTOAL_SHIFT 11 -#define DDR_PHY_DX8GCR0_RTTOAL_MASK 0x00000800U +#define DDR_PHY_DX8GCR0_RTTOAL_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_RTTOAL_SHIFT 11 +#define DDR_PHY_DX8GCR0_RTTOAL_MASK 0x00000800U -/*RTT Output Hold*/ +/* +* RTT Output Hold +*/ #undef DDR_PHY_DX8GCR0_RTTOH_DEFVAL #undef DDR_PHY_DX8GCR0_RTTOH_SHIFT #undef DDR_PHY_DX8GCR0_RTTOH_MASK -#define DDR_PHY_DX8GCR0_RTTOH_DEFVAL 0x40200204 -#define DDR_PHY_DX8GCR0_RTTOH_SHIFT 9 -#define DDR_PHY_DX8GCR0_RTTOH_MASK 0x00000600U +#define DDR_PHY_DX8GCR0_RTTOH_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_RTTOH_SHIFT 9 +#define DDR_PHY_DX8GCR0_RTTOH_MASK 0x00000600U -/*Configurable PDR Phase Shift*/ +/* +* Configurable PDR Phase Shift +*/ #undef DDR_PHY_DX8GCR0_CPDRSHFT_DEFVAL #undef DDR_PHY_DX8GCR0_CPDRSHFT_SHIFT #undef DDR_PHY_DX8GCR0_CPDRSHFT_MASK -#define DDR_PHY_DX8GCR0_CPDRSHFT_DEFVAL 0x40200204 -#define DDR_PHY_DX8GCR0_CPDRSHFT_SHIFT 7 -#define DDR_PHY_DX8GCR0_CPDRSHFT_MASK 0x00000180U +#define DDR_PHY_DX8GCR0_CPDRSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_CPDRSHFT_SHIFT 7 +#define DDR_PHY_DX8GCR0_CPDRSHFT_MASK 0x00000180U -/*DQSR Power Down*/ +/* +* DQSR Power Down +*/ #undef DDR_PHY_DX8GCR0_DQSRPD_DEFVAL #undef DDR_PHY_DX8GCR0_DQSRPD_SHIFT #undef DDR_PHY_DX8GCR0_DQSRPD_MASK -#define DDR_PHY_DX8GCR0_DQSRPD_DEFVAL 0x40200204 -#define DDR_PHY_DX8GCR0_DQSRPD_SHIFT 6 -#define DDR_PHY_DX8GCR0_DQSRPD_MASK 0x00000040U +#define DDR_PHY_DX8GCR0_DQSRPD_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_DQSRPD_SHIFT 6 +#define DDR_PHY_DX8GCR0_DQSRPD_MASK 0x00000040U -/*DQSG Power Down Receiver*/ +/* +* DQSG Power Down Receiver +*/ #undef DDR_PHY_DX8GCR0_DQSGPDR_DEFVAL #undef DDR_PHY_DX8GCR0_DQSGPDR_SHIFT #undef DDR_PHY_DX8GCR0_DQSGPDR_MASK -#define DDR_PHY_DX8GCR0_DQSGPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX8GCR0_DQSGPDR_SHIFT 5 -#define DDR_PHY_DX8GCR0_DQSGPDR_MASK 0x00000020U +#define DDR_PHY_DX8GCR0_DQSGPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_DQSGPDR_SHIFT 5 +#define DDR_PHY_DX8GCR0_DQSGPDR_MASK 0x00000020U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8GCR0_RESERVED_4_DEFVAL #undef DDR_PHY_DX8GCR0_RESERVED_4_SHIFT #undef DDR_PHY_DX8GCR0_RESERVED_4_MASK -#define DDR_PHY_DX8GCR0_RESERVED_4_DEFVAL 0x40200204 -#define DDR_PHY_DX8GCR0_RESERVED_4_SHIFT 4 -#define DDR_PHY_DX8GCR0_RESERVED_4_MASK 0x00000010U +#define DDR_PHY_DX8GCR0_RESERVED_4_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_RESERVED_4_SHIFT 4 +#define DDR_PHY_DX8GCR0_RESERVED_4_MASK 0x00000010U -/*DQSG On-Die Termination*/ +/* +* DQSG On-Die Termination +*/ #undef DDR_PHY_DX8GCR0_DQSGODT_DEFVAL #undef DDR_PHY_DX8GCR0_DQSGODT_SHIFT #undef DDR_PHY_DX8GCR0_DQSGODT_MASK -#define DDR_PHY_DX8GCR0_DQSGODT_DEFVAL 0x40200204 -#define DDR_PHY_DX8GCR0_DQSGODT_SHIFT 3 -#define DDR_PHY_DX8GCR0_DQSGODT_MASK 0x00000008U +#define DDR_PHY_DX8GCR0_DQSGODT_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_DQSGODT_SHIFT 3 +#define DDR_PHY_DX8GCR0_DQSGODT_MASK 0x00000008U -/*DQSG Output Enable*/ +/* +* DQSG Output Enable +*/ #undef DDR_PHY_DX8GCR0_DQSGOE_DEFVAL #undef DDR_PHY_DX8GCR0_DQSGOE_SHIFT #undef DDR_PHY_DX8GCR0_DQSGOE_MASK -#define DDR_PHY_DX8GCR0_DQSGOE_DEFVAL 0x40200204 -#define DDR_PHY_DX8GCR0_DQSGOE_SHIFT 2 -#define DDR_PHY_DX8GCR0_DQSGOE_MASK 0x00000004U +#define DDR_PHY_DX8GCR0_DQSGOE_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_DQSGOE_SHIFT 2 +#define DDR_PHY_DX8GCR0_DQSGOE_MASK 0x00000004U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8GCR0_RESERVED_1_0_DEFVAL #undef DDR_PHY_DX8GCR0_RESERVED_1_0_SHIFT #undef DDR_PHY_DX8GCR0_RESERVED_1_0_MASK -#define DDR_PHY_DX8GCR0_RESERVED_1_0_DEFVAL 0x40200204 -#define DDR_PHY_DX8GCR0_RESERVED_1_0_SHIFT 0 -#define DDR_PHY_DX8GCR0_RESERVED_1_0_MASK 0x00000003U +#define DDR_PHY_DX8GCR0_RESERVED_1_0_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_RESERVED_1_0_SHIFT 0 +#define DDR_PHY_DX8GCR0_RESERVED_1_0_MASK 0x00000003U -/*Enables the PDR mode for DQ[7:0]*/ +/* +* Enables the PDR mode for DQ[7:0] +*/ #undef DDR_PHY_DX8GCR1_DXPDRMODE_DEFVAL #undef DDR_PHY_DX8GCR1_DXPDRMODE_SHIFT #undef DDR_PHY_DX8GCR1_DXPDRMODE_MASK -#define DDR_PHY_DX8GCR1_DXPDRMODE_DEFVAL 0x00007FFF -#define DDR_PHY_DX8GCR1_DXPDRMODE_SHIFT 16 -#define DDR_PHY_DX8GCR1_DXPDRMODE_MASK 0xFFFF0000U +#define DDR_PHY_DX8GCR1_DXPDRMODE_DEFVAL 0x00007FFF +#define DDR_PHY_DX8GCR1_DXPDRMODE_SHIFT 16 +#define DDR_PHY_DX8GCR1_DXPDRMODE_MASK 0xFFFF0000U -/*Reserved. Returns zeroes on reads.*/ +/* +* Reserved. Returns zeroes on reads. +*/ #undef DDR_PHY_DX8GCR1_RESERVED_15_DEFVAL #undef DDR_PHY_DX8GCR1_RESERVED_15_SHIFT #undef DDR_PHY_DX8GCR1_RESERVED_15_MASK -#define DDR_PHY_DX8GCR1_RESERVED_15_DEFVAL 0x00007FFF -#define DDR_PHY_DX8GCR1_RESERVED_15_SHIFT 15 -#define DDR_PHY_DX8GCR1_RESERVED_15_MASK 0x00008000U +#define DDR_PHY_DX8GCR1_RESERVED_15_DEFVAL 0x00007FFF +#define DDR_PHY_DX8GCR1_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX8GCR1_RESERVED_15_MASK 0x00008000U -/*Select the delayed or non-delayed read data strobe #*/ +/* +* Select the delayed or non-delayed read data strobe # +*/ #undef DDR_PHY_DX8GCR1_QSNSEL_DEFVAL #undef DDR_PHY_DX8GCR1_QSNSEL_SHIFT #undef DDR_PHY_DX8GCR1_QSNSEL_MASK -#define DDR_PHY_DX8GCR1_QSNSEL_DEFVAL 0x00007FFF -#define DDR_PHY_DX8GCR1_QSNSEL_SHIFT 14 -#define DDR_PHY_DX8GCR1_QSNSEL_MASK 0x00004000U +#define DDR_PHY_DX8GCR1_QSNSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX8GCR1_QSNSEL_SHIFT 14 +#define DDR_PHY_DX8GCR1_QSNSEL_MASK 0x00004000U -/*Select the delayed or non-delayed read data strobe*/ +/* +* Select the delayed or non-delayed read data strobe +*/ #undef DDR_PHY_DX8GCR1_QSSEL_DEFVAL #undef DDR_PHY_DX8GCR1_QSSEL_SHIFT #undef DDR_PHY_DX8GCR1_QSSEL_MASK -#define DDR_PHY_DX8GCR1_QSSEL_DEFVAL 0x00007FFF -#define DDR_PHY_DX8GCR1_QSSEL_SHIFT 13 -#define DDR_PHY_DX8GCR1_QSSEL_MASK 0x00002000U +#define DDR_PHY_DX8GCR1_QSSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX8GCR1_QSSEL_SHIFT 13 +#define DDR_PHY_DX8GCR1_QSSEL_MASK 0x00002000U -/*Enables Read Data Strobe in a byte lane*/ +/* +* Enables Read Data Strobe in a byte lane +*/ #undef DDR_PHY_DX8GCR1_OEEN_DEFVAL #undef DDR_PHY_DX8GCR1_OEEN_SHIFT #undef DDR_PHY_DX8GCR1_OEEN_MASK -#define DDR_PHY_DX8GCR1_OEEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX8GCR1_OEEN_SHIFT 12 -#define DDR_PHY_DX8GCR1_OEEN_MASK 0x00001000U +#define DDR_PHY_DX8GCR1_OEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX8GCR1_OEEN_SHIFT 12 +#define DDR_PHY_DX8GCR1_OEEN_MASK 0x00001000U -/*Enables PDR in a byte lane*/ +/* +* Enables PDR in a byte lane +*/ #undef DDR_PHY_DX8GCR1_PDREN_DEFVAL #undef DDR_PHY_DX8GCR1_PDREN_SHIFT #undef DDR_PHY_DX8GCR1_PDREN_MASK -#define DDR_PHY_DX8GCR1_PDREN_DEFVAL 0x00007FFF -#define DDR_PHY_DX8GCR1_PDREN_SHIFT 11 -#define DDR_PHY_DX8GCR1_PDREN_MASK 0x00000800U +#define DDR_PHY_DX8GCR1_PDREN_DEFVAL 0x00007FFF +#define DDR_PHY_DX8GCR1_PDREN_SHIFT 11 +#define DDR_PHY_DX8GCR1_PDREN_MASK 0x00000800U -/*Enables ODT/TE in a byte lane*/ +/* +* Enables ODT/TE in a byte lane +*/ #undef DDR_PHY_DX8GCR1_TEEN_DEFVAL #undef DDR_PHY_DX8GCR1_TEEN_SHIFT #undef DDR_PHY_DX8GCR1_TEEN_MASK -#define DDR_PHY_DX8GCR1_TEEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX8GCR1_TEEN_SHIFT 10 -#define DDR_PHY_DX8GCR1_TEEN_MASK 0x00000400U +#define DDR_PHY_DX8GCR1_TEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX8GCR1_TEEN_SHIFT 10 +#define DDR_PHY_DX8GCR1_TEEN_MASK 0x00000400U -/*Enables Write Data strobe in a byte lane*/ +/* +* Enables Write Data strobe in a byte lane +*/ #undef DDR_PHY_DX8GCR1_DSEN_DEFVAL #undef DDR_PHY_DX8GCR1_DSEN_SHIFT #undef DDR_PHY_DX8GCR1_DSEN_MASK -#define DDR_PHY_DX8GCR1_DSEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX8GCR1_DSEN_SHIFT 9 -#define DDR_PHY_DX8GCR1_DSEN_MASK 0x00000200U +#define DDR_PHY_DX8GCR1_DSEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX8GCR1_DSEN_SHIFT 9 +#define DDR_PHY_DX8GCR1_DSEN_MASK 0x00000200U -/*Enables DM pin in a byte lane*/ +/* +* Enables DM pin in a byte lane +*/ #undef DDR_PHY_DX8GCR1_DMEN_DEFVAL #undef DDR_PHY_DX8GCR1_DMEN_SHIFT #undef DDR_PHY_DX8GCR1_DMEN_MASK -#define DDR_PHY_DX8GCR1_DMEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX8GCR1_DMEN_SHIFT 8 -#define DDR_PHY_DX8GCR1_DMEN_MASK 0x00000100U +#define DDR_PHY_DX8GCR1_DMEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX8GCR1_DMEN_SHIFT 8 +#define DDR_PHY_DX8GCR1_DMEN_MASK 0x00000100U -/*Enables DQ corresponding to each bit in a byte*/ +/* +* Enables DQ corresponding to each bit in a byte +*/ #undef DDR_PHY_DX8GCR1_DQEN_DEFVAL #undef DDR_PHY_DX8GCR1_DQEN_SHIFT #undef DDR_PHY_DX8GCR1_DQEN_MASK -#define DDR_PHY_DX8GCR1_DQEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX8GCR1_DQEN_SHIFT 0 -#define DDR_PHY_DX8GCR1_DQEN_MASK 0x000000FFU +#define DDR_PHY_DX8GCR1_DQEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX8GCR1_DQEN_SHIFT 0 +#define DDR_PHY_DX8GCR1_DQEN_MASK 0x000000FFU -/*Byte lane VREF IOM (Used only by D4MU IOs)*/ +/* +* Byte lane VREF IOM (Used only by D4MU IOs) +*/ #undef DDR_PHY_DX8GCR4_RESERVED_31_29_DEFVAL #undef DDR_PHY_DX8GCR4_RESERVED_31_29_SHIFT #undef DDR_PHY_DX8GCR4_RESERVED_31_29_MASK -#define DDR_PHY_DX8GCR4_RESERVED_31_29_DEFVAL 0x0E00003C -#define DDR_PHY_DX8GCR4_RESERVED_31_29_SHIFT 29 -#define DDR_PHY_DX8GCR4_RESERVED_31_29_MASK 0xE0000000U +#define DDR_PHY_DX8GCR4_RESERVED_31_29_DEFVAL 0x0E00003C +#define DDR_PHY_DX8GCR4_RESERVED_31_29_SHIFT 29 +#define DDR_PHY_DX8GCR4_RESERVED_31_29_MASK 0xE0000000U -/*Byte Lane VREF Pad Enable*/ +/* +* Byte Lane VREF Pad Enable +*/ #undef DDR_PHY_DX8GCR4_DXREFPEN_DEFVAL #undef DDR_PHY_DX8GCR4_DXREFPEN_SHIFT #undef DDR_PHY_DX8GCR4_DXREFPEN_MASK -#define DDR_PHY_DX8GCR4_DXREFPEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX8GCR4_DXREFPEN_SHIFT 28 -#define DDR_PHY_DX8GCR4_DXREFPEN_MASK 0x10000000U +#define DDR_PHY_DX8GCR4_DXREFPEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX8GCR4_DXREFPEN_SHIFT 28 +#define DDR_PHY_DX8GCR4_DXREFPEN_MASK 0x10000000U -/*Byte Lane Internal VREF Enable*/ +/* +* Byte Lane Internal VREF Enable +*/ #undef DDR_PHY_DX8GCR4_DXREFEEN_DEFVAL #undef DDR_PHY_DX8GCR4_DXREFEEN_SHIFT #undef DDR_PHY_DX8GCR4_DXREFEEN_MASK -#define DDR_PHY_DX8GCR4_DXREFEEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX8GCR4_DXREFEEN_SHIFT 26 -#define DDR_PHY_DX8GCR4_DXREFEEN_MASK 0x0C000000U +#define DDR_PHY_DX8GCR4_DXREFEEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX8GCR4_DXREFEEN_SHIFT 26 +#define DDR_PHY_DX8GCR4_DXREFEEN_MASK 0x0C000000U -/*Byte Lane Single-End VREF Enable*/ +/* +* Byte Lane Single-End VREF Enable +*/ #undef DDR_PHY_DX8GCR4_DXREFSEN_DEFVAL #undef DDR_PHY_DX8GCR4_DXREFSEN_SHIFT #undef DDR_PHY_DX8GCR4_DXREFSEN_MASK -#define DDR_PHY_DX8GCR4_DXREFSEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX8GCR4_DXREFSEN_SHIFT 25 -#define DDR_PHY_DX8GCR4_DXREFSEN_MASK 0x02000000U +#define DDR_PHY_DX8GCR4_DXREFSEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX8GCR4_DXREFSEN_SHIFT 25 +#define DDR_PHY_DX8GCR4_DXREFSEN_MASK 0x02000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX8GCR4_RESERVED_24_DEFVAL #undef DDR_PHY_DX8GCR4_RESERVED_24_SHIFT #undef DDR_PHY_DX8GCR4_RESERVED_24_MASK -#define DDR_PHY_DX8GCR4_RESERVED_24_DEFVAL 0x0E00003C -#define DDR_PHY_DX8GCR4_RESERVED_24_SHIFT 24 -#define DDR_PHY_DX8GCR4_RESERVED_24_MASK 0x01000000U +#define DDR_PHY_DX8GCR4_RESERVED_24_DEFVAL 0x0E00003C +#define DDR_PHY_DX8GCR4_RESERVED_24_SHIFT 24 +#define DDR_PHY_DX8GCR4_RESERVED_24_MASK 0x01000000U -/*External VREF generator REFSEL range select*/ +/* +* External VREF generator REFSEL range select +*/ #undef DDR_PHY_DX8GCR4_DXREFESELRANGE_DEFVAL #undef DDR_PHY_DX8GCR4_DXREFESELRANGE_SHIFT #undef DDR_PHY_DX8GCR4_DXREFESELRANGE_MASK -#define DDR_PHY_DX8GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C -#define DDR_PHY_DX8GCR4_DXREFESELRANGE_SHIFT 23 -#define DDR_PHY_DX8GCR4_DXREFESELRANGE_MASK 0x00800000U +#define DDR_PHY_DX8GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX8GCR4_DXREFESELRANGE_SHIFT 23 +#define DDR_PHY_DX8GCR4_DXREFESELRANGE_MASK 0x00800000U -/*Byte Lane External VREF Select*/ +/* +* Byte Lane External VREF Select +*/ #undef DDR_PHY_DX8GCR4_DXREFESEL_DEFVAL #undef DDR_PHY_DX8GCR4_DXREFESEL_SHIFT #undef DDR_PHY_DX8GCR4_DXREFESEL_MASK -#define DDR_PHY_DX8GCR4_DXREFESEL_DEFVAL 0x0E00003C -#define DDR_PHY_DX8GCR4_DXREFESEL_SHIFT 16 -#define DDR_PHY_DX8GCR4_DXREFESEL_MASK 0x007F0000U +#define DDR_PHY_DX8GCR4_DXREFESEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX8GCR4_DXREFESEL_SHIFT 16 +#define DDR_PHY_DX8GCR4_DXREFESEL_MASK 0x007F0000U -/*Single ended VREF generator REFSEL range select*/ +/* +* Single ended VREF generator REFSEL range select +*/ #undef DDR_PHY_DX8GCR4_DXREFSSELRANGE_DEFVAL #undef DDR_PHY_DX8GCR4_DXREFSSELRANGE_SHIFT #undef DDR_PHY_DX8GCR4_DXREFSSELRANGE_MASK -#define DDR_PHY_DX8GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C -#define DDR_PHY_DX8GCR4_DXREFSSELRANGE_SHIFT 15 -#define DDR_PHY_DX8GCR4_DXREFSSELRANGE_MASK 0x00008000U +#define DDR_PHY_DX8GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX8GCR4_DXREFSSELRANGE_SHIFT 15 +#define DDR_PHY_DX8GCR4_DXREFSSELRANGE_MASK 0x00008000U -/*Byte Lane Single-End VREF Select*/ +/* +* Byte Lane Single-End VREF Select +*/ #undef DDR_PHY_DX8GCR4_DXREFSSEL_DEFVAL #undef DDR_PHY_DX8GCR4_DXREFSSEL_SHIFT #undef DDR_PHY_DX8GCR4_DXREFSSEL_MASK -#define DDR_PHY_DX8GCR4_DXREFSSEL_DEFVAL 0x0E00003C -#define DDR_PHY_DX8GCR4_DXREFSSEL_SHIFT 8 -#define DDR_PHY_DX8GCR4_DXREFSSEL_MASK 0x00007F00U +#define DDR_PHY_DX8GCR4_DXREFSSEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX8GCR4_DXREFSSEL_SHIFT 8 +#define DDR_PHY_DX8GCR4_DXREFSSEL_MASK 0x00007F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX8GCR4_RESERVED_7_6_DEFVAL #undef DDR_PHY_DX8GCR4_RESERVED_7_6_SHIFT #undef DDR_PHY_DX8GCR4_RESERVED_7_6_MASK -#define DDR_PHY_DX8GCR4_RESERVED_7_6_DEFVAL 0x0E00003C -#define DDR_PHY_DX8GCR4_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_DX8GCR4_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_DX8GCR4_RESERVED_7_6_DEFVAL 0x0E00003C +#define DDR_PHY_DX8GCR4_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX8GCR4_RESERVED_7_6_MASK 0x000000C0U -/*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/ +/* +* VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. +*/ #undef DDR_PHY_DX8GCR4_DXREFIEN_DEFVAL #undef DDR_PHY_DX8GCR4_DXREFIEN_SHIFT #undef DDR_PHY_DX8GCR4_DXREFIEN_MASK -#define DDR_PHY_DX8GCR4_DXREFIEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX8GCR4_DXREFIEN_SHIFT 2 -#define DDR_PHY_DX8GCR4_DXREFIEN_MASK 0x0000003CU +#define DDR_PHY_DX8GCR4_DXREFIEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX8GCR4_DXREFIEN_SHIFT 2 +#define DDR_PHY_DX8GCR4_DXREFIEN_MASK 0x0000003CU -/*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/ +/* +* VRMON control for DQ IO (Single Ended) buffers of a byte lane. +*/ #undef DDR_PHY_DX8GCR4_DXREFIMON_DEFVAL #undef DDR_PHY_DX8GCR4_DXREFIMON_SHIFT #undef DDR_PHY_DX8GCR4_DXREFIMON_MASK -#define DDR_PHY_DX8GCR4_DXREFIMON_DEFVAL 0x0E00003C -#define DDR_PHY_DX8GCR4_DXREFIMON_SHIFT 0 -#define DDR_PHY_DX8GCR4_DXREFIMON_MASK 0x00000003U +#define DDR_PHY_DX8GCR4_DXREFIMON_DEFVAL 0x0E00003C +#define DDR_PHY_DX8GCR4_DXREFIMON_SHIFT 0 +#define DDR_PHY_DX8GCR4_DXREFIMON_MASK 0x00000003U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX8GCR5_RESERVED_31_DEFVAL #undef DDR_PHY_DX8GCR5_RESERVED_31_SHIFT #undef DDR_PHY_DX8GCR5_RESERVED_31_MASK -#define DDR_PHY_DX8GCR5_RESERVED_31_DEFVAL 0x09090909 -#define DDR_PHY_DX8GCR5_RESERVED_31_SHIFT 31 -#define DDR_PHY_DX8GCR5_RESERVED_31_MASK 0x80000000U +#define DDR_PHY_DX8GCR5_RESERVED_31_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR5_RESERVED_31_SHIFT 31 +#define DDR_PHY_DX8GCR5_RESERVED_31_MASK 0x80000000U -/*Byte Lane internal VREF Select for Rank 3*/ +/* +* Byte Lane internal VREF Select for Rank 3 +*/ #undef DDR_PHY_DX8GCR5_DXREFISELR3_DEFVAL #undef DDR_PHY_DX8GCR5_DXREFISELR3_SHIFT #undef DDR_PHY_DX8GCR5_DXREFISELR3_MASK -#define DDR_PHY_DX8GCR5_DXREFISELR3_DEFVAL 0x09090909 -#define DDR_PHY_DX8GCR5_DXREFISELR3_SHIFT 24 -#define DDR_PHY_DX8GCR5_DXREFISELR3_MASK 0x7F000000U +#define DDR_PHY_DX8GCR5_DXREFISELR3_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR5_DXREFISELR3_SHIFT 24 +#define DDR_PHY_DX8GCR5_DXREFISELR3_MASK 0x7F000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX8GCR5_RESERVED_23_DEFVAL #undef DDR_PHY_DX8GCR5_RESERVED_23_SHIFT #undef DDR_PHY_DX8GCR5_RESERVED_23_MASK -#define DDR_PHY_DX8GCR5_RESERVED_23_DEFVAL 0x09090909 -#define DDR_PHY_DX8GCR5_RESERVED_23_SHIFT 23 -#define DDR_PHY_DX8GCR5_RESERVED_23_MASK 0x00800000U +#define DDR_PHY_DX8GCR5_RESERVED_23_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR5_RESERVED_23_SHIFT 23 +#define DDR_PHY_DX8GCR5_RESERVED_23_MASK 0x00800000U -/*Byte Lane internal VREF Select for Rank 2*/ +/* +* Byte Lane internal VREF Select for Rank 2 +*/ #undef DDR_PHY_DX8GCR5_DXREFISELR2_DEFVAL #undef DDR_PHY_DX8GCR5_DXREFISELR2_SHIFT #undef DDR_PHY_DX8GCR5_DXREFISELR2_MASK -#define DDR_PHY_DX8GCR5_DXREFISELR2_DEFVAL 0x09090909 -#define DDR_PHY_DX8GCR5_DXREFISELR2_SHIFT 16 -#define DDR_PHY_DX8GCR5_DXREFISELR2_MASK 0x007F0000U +#define DDR_PHY_DX8GCR5_DXREFISELR2_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR5_DXREFISELR2_SHIFT 16 +#define DDR_PHY_DX8GCR5_DXREFISELR2_MASK 0x007F0000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX8GCR5_RESERVED_15_DEFVAL #undef DDR_PHY_DX8GCR5_RESERVED_15_SHIFT #undef DDR_PHY_DX8GCR5_RESERVED_15_MASK -#define DDR_PHY_DX8GCR5_RESERVED_15_DEFVAL 0x09090909 -#define DDR_PHY_DX8GCR5_RESERVED_15_SHIFT 15 -#define DDR_PHY_DX8GCR5_RESERVED_15_MASK 0x00008000U +#define DDR_PHY_DX8GCR5_RESERVED_15_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR5_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX8GCR5_RESERVED_15_MASK 0x00008000U -/*Byte Lane internal VREF Select for Rank 1*/ +/* +* Byte Lane internal VREF Select for Rank 1 +*/ #undef DDR_PHY_DX8GCR5_DXREFISELR1_DEFVAL #undef DDR_PHY_DX8GCR5_DXREFISELR1_SHIFT #undef DDR_PHY_DX8GCR5_DXREFISELR1_MASK -#define DDR_PHY_DX8GCR5_DXREFISELR1_DEFVAL 0x09090909 -#define DDR_PHY_DX8GCR5_DXREFISELR1_SHIFT 8 -#define DDR_PHY_DX8GCR5_DXREFISELR1_MASK 0x00007F00U +#define DDR_PHY_DX8GCR5_DXREFISELR1_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR5_DXREFISELR1_SHIFT 8 +#define DDR_PHY_DX8GCR5_DXREFISELR1_MASK 0x00007F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX8GCR5_RESERVED_7_DEFVAL #undef DDR_PHY_DX8GCR5_RESERVED_7_SHIFT #undef DDR_PHY_DX8GCR5_RESERVED_7_MASK -#define DDR_PHY_DX8GCR5_RESERVED_7_DEFVAL 0x09090909 -#define DDR_PHY_DX8GCR5_RESERVED_7_SHIFT 7 -#define DDR_PHY_DX8GCR5_RESERVED_7_MASK 0x00000080U +#define DDR_PHY_DX8GCR5_RESERVED_7_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR5_RESERVED_7_SHIFT 7 +#define DDR_PHY_DX8GCR5_RESERVED_7_MASK 0x00000080U -/*Byte Lane internal VREF Select for Rank 0*/ +/* +* Byte Lane internal VREF Select for Rank 0 +*/ #undef DDR_PHY_DX8GCR5_DXREFISELR0_DEFVAL #undef DDR_PHY_DX8GCR5_DXREFISELR0_SHIFT #undef DDR_PHY_DX8GCR5_DXREFISELR0_MASK -#define DDR_PHY_DX8GCR5_DXREFISELR0_DEFVAL 0x09090909 -#define DDR_PHY_DX8GCR5_DXREFISELR0_SHIFT 0 -#define DDR_PHY_DX8GCR5_DXREFISELR0_MASK 0x0000007FU +#define DDR_PHY_DX8GCR5_DXREFISELR0_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR5_DXREFISELR0_SHIFT 0 +#define DDR_PHY_DX8GCR5_DXREFISELR0_MASK 0x0000007FU -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX8GCR6_RESERVED_31_30_DEFVAL #undef DDR_PHY_DX8GCR6_RESERVED_31_30_SHIFT #undef DDR_PHY_DX8GCR6_RESERVED_31_30_MASK -#define DDR_PHY_DX8GCR6_RESERVED_31_30_DEFVAL 0x09090909 -#define DDR_PHY_DX8GCR6_RESERVED_31_30_SHIFT 30 -#define DDR_PHY_DX8GCR6_RESERVED_31_30_MASK 0xC0000000U +#define DDR_PHY_DX8GCR6_RESERVED_31_30_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR6_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX8GCR6_RESERVED_31_30_MASK 0xC0000000U -/*DRAM DQ VREF Select for Rank3*/ +/* +* DRAM DQ VREF Select for Rank3 +*/ #undef DDR_PHY_DX8GCR6_DXDQVREFR3_DEFVAL #undef DDR_PHY_DX8GCR6_DXDQVREFR3_SHIFT #undef DDR_PHY_DX8GCR6_DXDQVREFR3_MASK -#define DDR_PHY_DX8GCR6_DXDQVREFR3_DEFVAL 0x09090909 -#define DDR_PHY_DX8GCR6_DXDQVREFR3_SHIFT 24 -#define DDR_PHY_DX8GCR6_DXDQVREFR3_MASK 0x3F000000U +#define DDR_PHY_DX8GCR6_DXDQVREFR3_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR6_DXDQVREFR3_SHIFT 24 +#define DDR_PHY_DX8GCR6_DXDQVREFR3_MASK 0x3F000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX8GCR6_RESERVED_23_22_DEFVAL #undef DDR_PHY_DX8GCR6_RESERVED_23_22_SHIFT #undef DDR_PHY_DX8GCR6_RESERVED_23_22_MASK -#define DDR_PHY_DX8GCR6_RESERVED_23_22_DEFVAL 0x09090909 -#define DDR_PHY_DX8GCR6_RESERVED_23_22_SHIFT 22 -#define DDR_PHY_DX8GCR6_RESERVED_23_22_MASK 0x00C00000U +#define DDR_PHY_DX8GCR6_RESERVED_23_22_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR6_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX8GCR6_RESERVED_23_22_MASK 0x00C00000U -/*DRAM DQ VREF Select for Rank2*/ +/* +* DRAM DQ VREF Select for Rank2 +*/ #undef DDR_PHY_DX8GCR6_DXDQVREFR2_DEFVAL #undef DDR_PHY_DX8GCR6_DXDQVREFR2_SHIFT #undef DDR_PHY_DX8GCR6_DXDQVREFR2_MASK -#define DDR_PHY_DX8GCR6_DXDQVREFR2_DEFVAL 0x09090909 -#define DDR_PHY_DX8GCR6_DXDQVREFR2_SHIFT 16 -#define DDR_PHY_DX8GCR6_DXDQVREFR2_MASK 0x003F0000U +#define DDR_PHY_DX8GCR6_DXDQVREFR2_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR6_DXDQVREFR2_SHIFT 16 +#define DDR_PHY_DX8GCR6_DXDQVREFR2_MASK 0x003F0000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX8GCR6_RESERVED_15_14_DEFVAL #undef DDR_PHY_DX8GCR6_RESERVED_15_14_SHIFT #undef DDR_PHY_DX8GCR6_RESERVED_15_14_MASK -#define DDR_PHY_DX8GCR6_RESERVED_15_14_DEFVAL 0x09090909 -#define DDR_PHY_DX8GCR6_RESERVED_15_14_SHIFT 14 -#define DDR_PHY_DX8GCR6_RESERVED_15_14_MASK 0x0000C000U +#define DDR_PHY_DX8GCR6_RESERVED_15_14_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR6_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_DX8GCR6_RESERVED_15_14_MASK 0x0000C000U -/*DRAM DQ VREF Select for Rank1*/ +/* +* DRAM DQ VREF Select for Rank1 +*/ #undef DDR_PHY_DX8GCR6_DXDQVREFR1_DEFVAL #undef DDR_PHY_DX8GCR6_DXDQVREFR1_SHIFT #undef DDR_PHY_DX8GCR6_DXDQVREFR1_MASK -#define DDR_PHY_DX8GCR6_DXDQVREFR1_DEFVAL 0x09090909 -#define DDR_PHY_DX8GCR6_DXDQVREFR1_SHIFT 8 -#define DDR_PHY_DX8GCR6_DXDQVREFR1_MASK 0x00003F00U +#define DDR_PHY_DX8GCR6_DXDQVREFR1_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR6_DXDQVREFR1_SHIFT 8 +#define DDR_PHY_DX8GCR6_DXDQVREFR1_MASK 0x00003F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX8GCR6_RESERVED_7_6_DEFVAL #undef DDR_PHY_DX8GCR6_RESERVED_7_6_SHIFT #undef DDR_PHY_DX8GCR6_RESERVED_7_6_MASK -#define DDR_PHY_DX8GCR6_RESERVED_7_6_DEFVAL 0x09090909 -#define DDR_PHY_DX8GCR6_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_DX8GCR6_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_DX8GCR6_RESERVED_7_6_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR6_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX8GCR6_RESERVED_7_6_MASK 0x000000C0U -/*DRAM DQ VREF Select for Rank0*/ +/* +* DRAM DQ VREF Select for Rank0 +*/ #undef DDR_PHY_DX8GCR6_DXDQVREFR0_DEFVAL #undef DDR_PHY_DX8GCR6_DXDQVREFR0_SHIFT #undef DDR_PHY_DX8GCR6_DXDQVREFR0_MASK -#define DDR_PHY_DX8GCR6_DXDQVREFR0_DEFVAL 0x09090909 -#define DDR_PHY_DX8GCR6_DXDQVREFR0_SHIFT 0 -#define DDR_PHY_DX8GCR6_DXDQVREFR0_MASK 0x0000003FU +#define DDR_PHY_DX8GCR6_DXDQVREFR0_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR6_DXDQVREFR0_SHIFT 0 +#define DDR_PHY_DX8GCR6_DXDQVREFR0_MASK 0x0000003FU -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX8LCDLR2_RESERVED_31_25_DEFVAL -#undef DDR_PHY_DX8LCDLR2_RESERVED_31_25_SHIFT -#undef DDR_PHY_DX8LCDLR2_RESERVED_31_25_MASK -#define DDR_PHY_DX8LCDLR2_RESERVED_31_25_DEFVAL 0x00000000 -#define DDR_PHY_DX8LCDLR2_RESERVED_31_25_SHIFT 25 -#define DDR_PHY_DX8LCDLR2_RESERVED_31_25_MASK 0xFE000000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX8LCDLR2_RESERVED_24_16_DEFVAL -#undef DDR_PHY_DX8LCDLR2_RESERVED_24_16_SHIFT -#undef DDR_PHY_DX8LCDLR2_RESERVED_24_16_MASK -#define DDR_PHY_DX8LCDLR2_RESERVED_24_16_DEFVAL 0x00000000 -#define DDR_PHY_DX8LCDLR2_RESERVED_24_16_SHIFT 16 -#define DDR_PHY_DX8LCDLR2_RESERVED_24_16_MASK 0x01FF0000U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX8LCDLR2_RESERVED_15_9_DEFVAL -#undef DDR_PHY_DX8LCDLR2_RESERVED_15_9_SHIFT -#undef DDR_PHY_DX8LCDLR2_RESERVED_15_9_MASK -#define DDR_PHY_DX8LCDLR2_RESERVED_15_9_DEFVAL 0x00000000 -#define DDR_PHY_DX8LCDLR2_RESERVED_15_9_SHIFT 9 -#define DDR_PHY_DX8LCDLR2_RESERVED_15_9_MASK 0x0000FE00U - -/*Read DQS Gating Delay*/ -#undef DDR_PHY_DX8LCDLR2_DQSGD_DEFVAL -#undef DDR_PHY_DX8LCDLR2_DQSGD_SHIFT -#undef DDR_PHY_DX8LCDLR2_DQSGD_MASK -#define DDR_PHY_DX8LCDLR2_DQSGD_DEFVAL 0x00000000 -#define DDR_PHY_DX8LCDLR2_DQSGD_SHIFT 0 -#define DDR_PHY_DX8LCDLR2_DQSGD_MASK 0x000001FFU - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX8GTR0_RESERVED_31_24_DEFVAL -#undef DDR_PHY_DX8GTR0_RESERVED_31_24_SHIFT -#undef DDR_PHY_DX8GTR0_RESERVED_31_24_MASK -#define DDR_PHY_DX8GTR0_RESERVED_31_24_DEFVAL 0x00020000 -#define DDR_PHY_DX8GTR0_RESERVED_31_24_SHIFT 27 -#define DDR_PHY_DX8GTR0_RESERVED_31_24_MASK 0xF8000000U - -/*DQ Write Path Latency Pipeline*/ -#undef DDR_PHY_DX8GTR0_WDQSL_DEFVAL -#undef DDR_PHY_DX8GTR0_WDQSL_SHIFT -#undef DDR_PHY_DX8GTR0_WDQSL_MASK -#define DDR_PHY_DX8GTR0_WDQSL_DEFVAL 0x00020000 -#define DDR_PHY_DX8GTR0_WDQSL_SHIFT 24 -#define DDR_PHY_DX8GTR0_WDQSL_MASK 0x07000000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX8GTR0_RESERVED_23_20_DEFVAL -#undef DDR_PHY_DX8GTR0_RESERVED_23_20_SHIFT -#undef DDR_PHY_DX8GTR0_RESERVED_23_20_MASK -#define DDR_PHY_DX8GTR0_RESERVED_23_20_DEFVAL 0x00020000 -#define DDR_PHY_DX8GTR0_RESERVED_23_20_SHIFT 20 -#define DDR_PHY_DX8GTR0_RESERVED_23_20_MASK 0x00F00000U - -/*Write Leveling System Latency*/ -#undef DDR_PHY_DX8GTR0_WLSL_DEFVAL -#undef DDR_PHY_DX8GTR0_WLSL_SHIFT -#undef DDR_PHY_DX8GTR0_WLSL_MASK -#define DDR_PHY_DX8GTR0_WLSL_DEFVAL 0x00020000 -#define DDR_PHY_DX8GTR0_WLSL_SHIFT 16 -#define DDR_PHY_DX8GTR0_WLSL_MASK 0x000F0000U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX8GTR0_RESERVED_15_13_DEFVAL -#undef DDR_PHY_DX8GTR0_RESERVED_15_13_SHIFT -#undef DDR_PHY_DX8GTR0_RESERVED_15_13_MASK -#define DDR_PHY_DX8GTR0_RESERVED_15_13_DEFVAL 0x00020000 -#define DDR_PHY_DX8GTR0_RESERVED_15_13_SHIFT 13 -#define DDR_PHY_DX8GTR0_RESERVED_15_13_MASK 0x0000E000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX8GTR0_RESERVED_12_8_DEFVAL -#undef DDR_PHY_DX8GTR0_RESERVED_12_8_SHIFT -#undef DDR_PHY_DX8GTR0_RESERVED_12_8_MASK -#define DDR_PHY_DX8GTR0_RESERVED_12_8_DEFVAL 0x00020000 -#define DDR_PHY_DX8GTR0_RESERVED_12_8_SHIFT 8 -#define DDR_PHY_DX8GTR0_RESERVED_12_8_MASK 0x00001F00U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX8GTR0_RESERVED_7_5_DEFVAL -#undef DDR_PHY_DX8GTR0_RESERVED_7_5_SHIFT -#undef DDR_PHY_DX8GTR0_RESERVED_7_5_MASK -#define DDR_PHY_DX8GTR0_RESERVED_7_5_DEFVAL 0x00020000 -#define DDR_PHY_DX8GTR0_RESERVED_7_5_SHIFT 5 -#define DDR_PHY_DX8GTR0_RESERVED_7_5_MASK 0x000000E0U - -/*DQS Gating System Latency*/ -#undef DDR_PHY_DX8GTR0_DGSL_DEFVAL -#undef DDR_PHY_DX8GTR0_DGSL_SHIFT -#undef DDR_PHY_DX8GTR0_DGSL_MASK -#define DDR_PHY_DX8GTR0_DGSL_DEFVAL 0x00020000 -#define DDR_PHY_DX8GTR0_DGSL_SHIFT 0 -#define DDR_PHY_DX8GTR0_DGSL_MASK 0x0000001FU - -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL0OSC_RESERVED_31_30_DEFVAL #undef DDR_PHY_DX8SL0OSC_RESERVED_31_30_SHIFT #undef DDR_PHY_DX8SL0OSC_RESERVED_31_30_MASK -#define DDR_PHY_DX8SL0OSC_RESERVED_31_30_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL0OSC_RESERVED_31_30_SHIFT 30 -#define DDR_PHY_DX8SL0OSC_RESERVED_31_30_MASK 0xC0000000U +#define DDR_PHY_DX8SL0OSC_RESERVED_31_30_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX8SL0OSC_RESERVED_31_30_MASK 0xC0000000U -/*Enable Clock Gating for DX ddr_clk*/ +/* +* Enable Clock Gating for DX ddr_clk +*/ #undef DDR_PHY_DX8SL0OSC_GATEDXRDCLK_DEFVAL #undef DDR_PHY_DX8SL0OSC_GATEDXRDCLK_SHIFT #undef DDR_PHY_DX8SL0OSC_GATEDXRDCLK_MASK -#define DDR_PHY_DX8SL0OSC_GATEDXRDCLK_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL0OSC_GATEDXRDCLK_SHIFT 28 -#define DDR_PHY_DX8SL0OSC_GATEDXRDCLK_MASK 0x30000000U +#define DDR_PHY_DX8SL0OSC_GATEDXRDCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_GATEDXRDCLK_SHIFT 28 +#define DDR_PHY_DX8SL0OSC_GATEDXRDCLK_MASK 0x30000000U -/*Enable Clock Gating for DX ctl_rd_clk*/ +/* +* Enable Clock Gating for DX ctl_rd_clk +*/ #undef DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_DEFVAL #undef DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_SHIFT #undef DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_MASK -#define DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_SHIFT 26 -#define DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_MASK 0x0C000000U +#define DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_SHIFT 26 +#define DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_MASK 0x0C000000U -/*Enable Clock Gating for DX ctl_clk*/ +/* +* Enable Clock Gating for DX ctl_clk +*/ #undef DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_DEFVAL #undef DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_SHIFT #undef DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_MASK -#define DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_SHIFT 24 -#define DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_MASK 0x03000000U +#define DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_SHIFT 24 +#define DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_MASK 0x03000000U -/*Selects the level to which clocks will be stalled when clock gating is enabled.*/ +/* +* Selects the level to which clocks will be stalled when clock gating is e + * nabled. +*/ #undef DDR_PHY_DX8SL0OSC_CLKLEVEL_DEFVAL #undef DDR_PHY_DX8SL0OSC_CLKLEVEL_SHIFT #undef DDR_PHY_DX8SL0OSC_CLKLEVEL_MASK -#define DDR_PHY_DX8SL0OSC_CLKLEVEL_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL0OSC_CLKLEVEL_SHIFT 22 -#define DDR_PHY_DX8SL0OSC_CLKLEVEL_MASK 0x00C00000U +#define DDR_PHY_DX8SL0OSC_CLKLEVEL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_CLKLEVEL_SHIFT 22 +#define DDR_PHY_DX8SL0OSC_CLKLEVEL_MASK 0x00C00000U -/*Loopback Mode*/ +/* +* Loopback Mode +*/ #undef DDR_PHY_DX8SL0OSC_LBMODE_DEFVAL #undef DDR_PHY_DX8SL0OSC_LBMODE_SHIFT #undef DDR_PHY_DX8SL0OSC_LBMODE_MASK -#define DDR_PHY_DX8SL0OSC_LBMODE_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL0OSC_LBMODE_SHIFT 21 -#define DDR_PHY_DX8SL0OSC_LBMODE_MASK 0x00200000U +#define DDR_PHY_DX8SL0OSC_LBMODE_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_LBMODE_SHIFT 21 +#define DDR_PHY_DX8SL0OSC_LBMODE_MASK 0x00200000U -/*Load GSDQS LCDL with 2x the calibrated GSDQSPRD value*/ +/* +* Load GSDQS LCDL with 2x the calibrated GSDQSPRD value +*/ #undef DDR_PHY_DX8SL0OSC_LBGSDQS_DEFVAL #undef DDR_PHY_DX8SL0OSC_LBGSDQS_SHIFT #undef DDR_PHY_DX8SL0OSC_LBGSDQS_MASK -#define DDR_PHY_DX8SL0OSC_LBGSDQS_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL0OSC_LBGSDQS_SHIFT 20 -#define DDR_PHY_DX8SL0OSC_LBGSDQS_MASK 0x00100000U +#define DDR_PHY_DX8SL0OSC_LBGSDQS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_LBGSDQS_SHIFT 20 +#define DDR_PHY_DX8SL0OSC_LBGSDQS_MASK 0x00100000U -/*Loopback DQS Gating*/ +/* +* Loopback DQS Gating +*/ #undef DDR_PHY_DX8SL0OSC_LBGDQS_DEFVAL #undef DDR_PHY_DX8SL0OSC_LBGDQS_SHIFT #undef DDR_PHY_DX8SL0OSC_LBGDQS_MASK -#define DDR_PHY_DX8SL0OSC_LBGDQS_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL0OSC_LBGDQS_SHIFT 18 -#define DDR_PHY_DX8SL0OSC_LBGDQS_MASK 0x000C0000U +#define DDR_PHY_DX8SL0OSC_LBGDQS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_LBGDQS_SHIFT 18 +#define DDR_PHY_DX8SL0OSC_LBGDQS_MASK 0x000C0000U -/*Loopback DQS Shift*/ +/* +* Loopback DQS Shift +*/ #undef DDR_PHY_DX8SL0OSC_LBDQSS_DEFVAL #undef DDR_PHY_DX8SL0OSC_LBDQSS_SHIFT #undef DDR_PHY_DX8SL0OSC_LBDQSS_MASK -#define DDR_PHY_DX8SL0OSC_LBDQSS_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL0OSC_LBDQSS_SHIFT 17 -#define DDR_PHY_DX8SL0OSC_LBDQSS_MASK 0x00020000U +#define DDR_PHY_DX8SL0OSC_LBDQSS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_LBDQSS_SHIFT 17 +#define DDR_PHY_DX8SL0OSC_LBDQSS_MASK 0x00020000U -/*PHY High-Speed Reset*/ +/* +* PHY High-Speed Reset +*/ #undef DDR_PHY_DX8SL0OSC_PHYHRST_DEFVAL #undef DDR_PHY_DX8SL0OSC_PHYHRST_SHIFT #undef DDR_PHY_DX8SL0OSC_PHYHRST_MASK -#define DDR_PHY_DX8SL0OSC_PHYHRST_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL0OSC_PHYHRST_SHIFT 16 -#define DDR_PHY_DX8SL0OSC_PHYHRST_MASK 0x00010000U +#define DDR_PHY_DX8SL0OSC_PHYHRST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_PHYHRST_SHIFT 16 +#define DDR_PHY_DX8SL0OSC_PHYHRST_MASK 0x00010000U -/*PHY FIFO Reset*/ +/* +* PHY FIFO Reset +*/ #undef DDR_PHY_DX8SL0OSC_PHYFRST_DEFVAL #undef DDR_PHY_DX8SL0OSC_PHYFRST_SHIFT #undef DDR_PHY_DX8SL0OSC_PHYFRST_MASK -#define DDR_PHY_DX8SL0OSC_PHYFRST_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL0OSC_PHYFRST_SHIFT 15 -#define DDR_PHY_DX8SL0OSC_PHYFRST_MASK 0x00008000U +#define DDR_PHY_DX8SL0OSC_PHYFRST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_PHYFRST_SHIFT 15 +#define DDR_PHY_DX8SL0OSC_PHYFRST_MASK 0x00008000U -/*Delay Line Test Start*/ +/* +* Delay Line Test Start +*/ #undef DDR_PHY_DX8SL0OSC_DLTST_DEFVAL #undef DDR_PHY_DX8SL0OSC_DLTST_SHIFT #undef DDR_PHY_DX8SL0OSC_DLTST_MASK -#define DDR_PHY_DX8SL0OSC_DLTST_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL0OSC_DLTST_SHIFT 14 -#define DDR_PHY_DX8SL0OSC_DLTST_MASK 0x00004000U +#define DDR_PHY_DX8SL0OSC_DLTST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_DLTST_SHIFT 14 +#define DDR_PHY_DX8SL0OSC_DLTST_MASK 0x00004000U -/*Delay Line Test Mode*/ +/* +* Delay Line Test Mode +*/ #undef DDR_PHY_DX8SL0OSC_DLTMODE_DEFVAL #undef DDR_PHY_DX8SL0OSC_DLTMODE_SHIFT #undef DDR_PHY_DX8SL0OSC_DLTMODE_MASK -#define DDR_PHY_DX8SL0OSC_DLTMODE_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL0OSC_DLTMODE_SHIFT 13 -#define DDR_PHY_DX8SL0OSC_DLTMODE_MASK 0x00002000U +#define DDR_PHY_DX8SL0OSC_DLTMODE_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_DLTMODE_SHIFT 13 +#define DDR_PHY_DX8SL0OSC_DLTMODE_MASK 0x00002000U -/*Reserved. Caution, do not write to this register field.*/ +/* +* Reserved. Caution, do not write to this register field. +*/ #undef DDR_PHY_DX8SL0OSC_RESERVED_12_11_DEFVAL #undef DDR_PHY_DX8SL0OSC_RESERVED_12_11_SHIFT #undef DDR_PHY_DX8SL0OSC_RESERVED_12_11_MASK -#define DDR_PHY_DX8SL0OSC_RESERVED_12_11_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL0OSC_RESERVED_12_11_SHIFT 11 -#define DDR_PHY_DX8SL0OSC_RESERVED_12_11_MASK 0x00001800U +#define DDR_PHY_DX8SL0OSC_RESERVED_12_11_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_RESERVED_12_11_SHIFT 11 +#define DDR_PHY_DX8SL0OSC_RESERVED_12_11_MASK 0x00001800U -/*Oscillator Mode Write-Data Delay Line Select*/ +/* +* Oscillator Mode Write-Data Delay Line Select +*/ #undef DDR_PHY_DX8SL0OSC_OSCWDDL_DEFVAL #undef DDR_PHY_DX8SL0OSC_OSCWDDL_SHIFT #undef DDR_PHY_DX8SL0OSC_OSCWDDL_MASK -#define DDR_PHY_DX8SL0OSC_OSCWDDL_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL0OSC_OSCWDDL_SHIFT 9 -#define DDR_PHY_DX8SL0OSC_OSCWDDL_MASK 0x00000600U +#define DDR_PHY_DX8SL0OSC_OSCWDDL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_OSCWDDL_SHIFT 9 +#define DDR_PHY_DX8SL0OSC_OSCWDDL_MASK 0x00000600U -/*Reserved. Caution, do not write to this register field.*/ +/* +* Reserved. Caution, do not write to this register field. +*/ #undef DDR_PHY_DX8SL0OSC_RESERVED_8_7_DEFVAL #undef DDR_PHY_DX8SL0OSC_RESERVED_8_7_SHIFT #undef DDR_PHY_DX8SL0OSC_RESERVED_8_7_MASK -#define DDR_PHY_DX8SL0OSC_RESERVED_8_7_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL0OSC_RESERVED_8_7_SHIFT 7 -#define DDR_PHY_DX8SL0OSC_RESERVED_8_7_MASK 0x00000180U +#define DDR_PHY_DX8SL0OSC_RESERVED_8_7_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_RESERVED_8_7_SHIFT 7 +#define DDR_PHY_DX8SL0OSC_RESERVED_8_7_MASK 0x00000180U -/*Oscillator Mode Write-Leveling Delay Line Select*/ +/* +* Oscillator Mode Write-Leveling Delay Line Select +*/ #undef DDR_PHY_DX8SL0OSC_OSCWDL_DEFVAL #undef DDR_PHY_DX8SL0OSC_OSCWDL_SHIFT #undef DDR_PHY_DX8SL0OSC_OSCWDL_MASK -#define DDR_PHY_DX8SL0OSC_OSCWDL_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL0OSC_OSCWDL_SHIFT 5 -#define DDR_PHY_DX8SL0OSC_OSCWDL_MASK 0x00000060U +#define DDR_PHY_DX8SL0OSC_OSCWDL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_OSCWDL_SHIFT 5 +#define DDR_PHY_DX8SL0OSC_OSCWDL_MASK 0x00000060U -/*Oscillator Mode Division*/ +/* +* Oscillator Mode Division +*/ #undef DDR_PHY_DX8SL0OSC_OSCDIV_DEFVAL #undef DDR_PHY_DX8SL0OSC_OSCDIV_SHIFT #undef DDR_PHY_DX8SL0OSC_OSCDIV_MASK -#define DDR_PHY_DX8SL0OSC_OSCDIV_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL0OSC_OSCDIV_SHIFT 1 -#define DDR_PHY_DX8SL0OSC_OSCDIV_MASK 0x0000001EU +#define DDR_PHY_DX8SL0OSC_OSCDIV_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_OSCDIV_SHIFT 1 +#define DDR_PHY_DX8SL0OSC_OSCDIV_MASK 0x0000001EU -/*Oscillator Enable*/ +/* +* Oscillator Enable +*/ #undef DDR_PHY_DX8SL0OSC_OSCEN_DEFVAL #undef DDR_PHY_DX8SL0OSC_OSCEN_SHIFT #undef DDR_PHY_DX8SL0OSC_OSCEN_MASK -#define DDR_PHY_DX8SL0OSC_OSCEN_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL0OSC_OSCEN_SHIFT 0 -#define DDR_PHY_DX8SL0OSC_OSCEN_MASK 0x00000001U +#define DDR_PHY_DX8SL0OSC_OSCEN_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_OSCEN_SHIFT 0 +#define DDR_PHY_DX8SL0OSC_OSCEN_MASK 0x00000001U -/*Reserved. Return zeroes on reads.*/ +/* +* PLL Bypass +*/ +#undef DDR_PHY_DX8SL0PLLCR0_PLLBYP_DEFVAL +#undef DDR_PHY_DX8SL0PLLCR0_PLLBYP_SHIFT +#undef DDR_PHY_DX8SL0PLLCR0_PLLBYP_MASK +#define DDR_PHY_DX8SL0PLLCR0_PLLBYP_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL0PLLCR0_PLLBYP_SHIFT 31 +#define DDR_PHY_DX8SL0PLLCR0_PLLBYP_MASK 0x80000000U + +/* +* PLL Reset +*/ +#undef DDR_PHY_DX8SL0PLLCR0_PLLRST_DEFVAL +#undef DDR_PHY_DX8SL0PLLCR0_PLLRST_SHIFT +#undef DDR_PHY_DX8SL0PLLCR0_PLLRST_MASK +#define DDR_PHY_DX8SL0PLLCR0_PLLRST_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL0PLLCR0_PLLRST_SHIFT 30 +#define DDR_PHY_DX8SL0PLLCR0_PLLRST_MASK 0x40000000U + +/* +* PLL Power Down +*/ +#undef DDR_PHY_DX8SL0PLLCR0_PLLPD_DEFVAL +#undef DDR_PHY_DX8SL0PLLCR0_PLLPD_SHIFT +#undef DDR_PHY_DX8SL0PLLCR0_PLLPD_MASK +#define DDR_PHY_DX8SL0PLLCR0_PLLPD_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL0PLLCR0_PLLPD_SHIFT 29 +#define DDR_PHY_DX8SL0PLLCR0_PLLPD_MASK 0x20000000U + +/* +* Reference Stop Mode +*/ +#undef DDR_PHY_DX8SL0PLLCR0_RSTOPM_DEFVAL +#undef DDR_PHY_DX8SL0PLLCR0_RSTOPM_SHIFT +#undef DDR_PHY_DX8SL0PLLCR0_RSTOPM_MASK +#define DDR_PHY_DX8SL0PLLCR0_RSTOPM_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL0PLLCR0_RSTOPM_SHIFT 28 +#define DDR_PHY_DX8SL0PLLCR0_RSTOPM_MASK 0x10000000U + +/* +* PLL Frequency Select +*/ +#undef DDR_PHY_DX8SL0PLLCR0_FRQSEL_DEFVAL +#undef DDR_PHY_DX8SL0PLLCR0_FRQSEL_SHIFT +#undef DDR_PHY_DX8SL0PLLCR0_FRQSEL_MASK +#define DDR_PHY_DX8SL0PLLCR0_FRQSEL_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL0PLLCR0_FRQSEL_SHIFT 24 +#define DDR_PHY_DX8SL0PLLCR0_FRQSEL_MASK 0x0F000000U + +/* +* Relock Mode +*/ +#undef DDR_PHY_DX8SL0PLLCR0_RLOCKM_DEFVAL +#undef DDR_PHY_DX8SL0PLLCR0_RLOCKM_SHIFT +#undef DDR_PHY_DX8SL0PLLCR0_RLOCKM_MASK +#define DDR_PHY_DX8SL0PLLCR0_RLOCKM_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL0PLLCR0_RLOCKM_SHIFT 23 +#define DDR_PHY_DX8SL0PLLCR0_RLOCKM_MASK 0x00800000U + +/* +* Charge Pump Proportional Current Control +*/ +#undef DDR_PHY_DX8SL0PLLCR0_CPPC_DEFVAL +#undef DDR_PHY_DX8SL0PLLCR0_CPPC_SHIFT +#undef DDR_PHY_DX8SL0PLLCR0_CPPC_MASK +#define DDR_PHY_DX8SL0PLLCR0_CPPC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL0PLLCR0_CPPC_SHIFT 17 +#define DDR_PHY_DX8SL0PLLCR0_CPPC_MASK 0x007E0000U + +/* +* Charge Pump Integrating Current Control +*/ +#undef DDR_PHY_DX8SL0PLLCR0_CPIC_DEFVAL +#undef DDR_PHY_DX8SL0PLLCR0_CPIC_SHIFT +#undef DDR_PHY_DX8SL0PLLCR0_CPIC_MASK +#define DDR_PHY_DX8SL0PLLCR0_CPIC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL0PLLCR0_CPIC_SHIFT 13 +#define DDR_PHY_DX8SL0PLLCR0_CPIC_MASK 0x0001E000U + +/* +* Gear Shift +*/ +#undef DDR_PHY_DX8SL0PLLCR0_GSHIFT_DEFVAL +#undef DDR_PHY_DX8SL0PLLCR0_GSHIFT_SHIFT +#undef DDR_PHY_DX8SL0PLLCR0_GSHIFT_MASK +#define DDR_PHY_DX8SL0PLLCR0_GSHIFT_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL0PLLCR0_GSHIFT_SHIFT 12 +#define DDR_PHY_DX8SL0PLLCR0_GSHIFT_MASK 0x00001000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL0PLLCR0_RESERVED_11_9_DEFVAL +#undef DDR_PHY_DX8SL0PLLCR0_RESERVED_11_9_SHIFT +#undef DDR_PHY_DX8SL0PLLCR0_RESERVED_11_9_MASK +#define DDR_PHY_DX8SL0PLLCR0_RESERVED_11_9_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL0PLLCR0_RESERVED_11_9_SHIFT 9 +#define DDR_PHY_DX8SL0PLLCR0_RESERVED_11_9_MASK 0x00000E00U + +/* +* Analog Test Enable (ATOEN) +*/ +#undef DDR_PHY_DX8SL0PLLCR0_ATOEN_DEFVAL +#undef DDR_PHY_DX8SL0PLLCR0_ATOEN_SHIFT +#undef DDR_PHY_DX8SL0PLLCR0_ATOEN_MASK +#define DDR_PHY_DX8SL0PLLCR0_ATOEN_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL0PLLCR0_ATOEN_SHIFT 8 +#define DDR_PHY_DX8SL0PLLCR0_ATOEN_MASK 0x00000100U + +/* +* Analog Test Control +*/ +#undef DDR_PHY_DX8SL0PLLCR0_ATC_DEFVAL +#undef DDR_PHY_DX8SL0PLLCR0_ATC_SHIFT +#undef DDR_PHY_DX8SL0PLLCR0_ATC_MASK +#define DDR_PHY_DX8SL0PLLCR0_ATC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL0PLLCR0_ATC_SHIFT 4 +#define DDR_PHY_DX8SL0PLLCR0_ATC_MASK 0x000000F0U + +/* +* Digital Test Control +*/ +#undef DDR_PHY_DX8SL0PLLCR0_DTC_DEFVAL +#undef DDR_PHY_DX8SL0PLLCR0_DTC_SHIFT +#undef DDR_PHY_DX8SL0PLLCR0_DTC_MASK +#define DDR_PHY_DX8SL0PLLCR0_DTC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL0PLLCR0_DTC_SHIFT 0 +#define DDR_PHY_DX8SL0PLLCR0_DTC_MASK 0x0000000FU + +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_DEFVAL #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_SHIFT #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_MASK -#define DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_SHIFT 25 -#define DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_MASK 0xFE000000U +#define DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_SHIFT 25 +#define DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_MASK 0xFE000000U -/*Read Path Rise-to-Rise Mode*/ +/* +* Read Path Rise-to-Rise Mode +*/ #undef DDR_PHY_DX8SL0DQSCTL_RRRMODE_DEFVAL #undef DDR_PHY_DX8SL0DQSCTL_RRRMODE_SHIFT #undef DDR_PHY_DX8SL0DQSCTL_RRRMODE_MASK -#define DDR_PHY_DX8SL0DQSCTL_RRRMODE_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL0DQSCTL_RRRMODE_SHIFT 24 -#define DDR_PHY_DX8SL0DQSCTL_RRRMODE_MASK 0x01000000U +#define DDR_PHY_DX8SL0DQSCTL_RRRMODE_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL0DQSCTL_RRRMODE_SHIFT 24 +#define DDR_PHY_DX8SL0DQSCTL_RRRMODE_MASK 0x01000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_DEFVAL #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_SHIFT #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_MASK -#define DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_SHIFT 22 -#define DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_MASK 0x00C00000U +#define DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_MASK 0x00C00000U -/*Write Path Rise-to-Rise Mode*/ +/* +* Write Path Rise-to-Rise Mode +*/ #undef DDR_PHY_DX8SL0DQSCTL_WRRMODE_DEFVAL #undef DDR_PHY_DX8SL0DQSCTL_WRRMODE_SHIFT #undef DDR_PHY_DX8SL0DQSCTL_WRRMODE_MASK -#define DDR_PHY_DX8SL0DQSCTL_WRRMODE_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL0DQSCTL_WRRMODE_SHIFT 21 -#define DDR_PHY_DX8SL0DQSCTL_WRRMODE_MASK 0x00200000U +#define DDR_PHY_DX8SL0DQSCTL_WRRMODE_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL0DQSCTL_WRRMODE_SHIFT 21 +#define DDR_PHY_DX8SL0DQSCTL_WRRMODE_MASK 0x00200000U -/*DQS Gate Extension*/ +/* +* DQS Gate Extension +*/ #undef DDR_PHY_DX8SL0DQSCTL_DQSGX_DEFVAL #undef DDR_PHY_DX8SL0DQSCTL_DQSGX_SHIFT #undef DDR_PHY_DX8SL0DQSCTL_DQSGX_MASK -#define DDR_PHY_DX8SL0DQSCTL_DQSGX_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL0DQSCTL_DQSGX_SHIFT 19 -#define DDR_PHY_DX8SL0DQSCTL_DQSGX_MASK 0x00180000U +#define DDR_PHY_DX8SL0DQSCTL_DQSGX_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL0DQSCTL_DQSGX_SHIFT 19 +#define DDR_PHY_DX8SL0DQSCTL_DQSGX_MASK 0x00180000U -/*Low Power PLL Power Down*/ +/* +* Low Power PLL Power Down +*/ #undef DDR_PHY_DX8SL0DQSCTL_LPPLLPD_DEFVAL #undef DDR_PHY_DX8SL0DQSCTL_LPPLLPD_SHIFT #undef DDR_PHY_DX8SL0DQSCTL_LPPLLPD_MASK -#define DDR_PHY_DX8SL0DQSCTL_LPPLLPD_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL0DQSCTL_LPPLLPD_SHIFT 18 -#define DDR_PHY_DX8SL0DQSCTL_LPPLLPD_MASK 0x00040000U +#define DDR_PHY_DX8SL0DQSCTL_LPPLLPD_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL0DQSCTL_LPPLLPD_SHIFT 18 +#define DDR_PHY_DX8SL0DQSCTL_LPPLLPD_MASK 0x00040000U -/*Low Power I/O Power Down*/ +/* +* Low Power I/O Power Down +*/ #undef DDR_PHY_DX8SL0DQSCTL_LPIOPD_DEFVAL #undef DDR_PHY_DX8SL0DQSCTL_LPIOPD_SHIFT #undef DDR_PHY_DX8SL0DQSCTL_LPIOPD_MASK -#define DDR_PHY_DX8SL0DQSCTL_LPIOPD_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL0DQSCTL_LPIOPD_SHIFT 17 -#define DDR_PHY_DX8SL0DQSCTL_LPIOPD_MASK 0x00020000U +#define DDR_PHY_DX8SL0DQSCTL_LPIOPD_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL0DQSCTL_LPIOPD_SHIFT 17 +#define DDR_PHY_DX8SL0DQSCTL_LPIOPD_MASK 0x00020000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_DEFVAL #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_SHIFT #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_MASK -#define DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_SHIFT 15 -#define DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_MASK 0x00018000U +#define DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_SHIFT 15 +#define DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_MASK 0x00018000U -/*QS Counter Enable*/ +/* +* QS Counter Enable +*/ #undef DDR_PHY_DX8SL0DQSCTL_QSCNTEN_DEFVAL #undef DDR_PHY_DX8SL0DQSCTL_QSCNTEN_SHIFT #undef DDR_PHY_DX8SL0DQSCTL_QSCNTEN_MASK -#define DDR_PHY_DX8SL0DQSCTL_QSCNTEN_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL0DQSCTL_QSCNTEN_SHIFT 14 -#define DDR_PHY_DX8SL0DQSCTL_QSCNTEN_MASK 0x00004000U +#define DDR_PHY_DX8SL0DQSCTL_QSCNTEN_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL0DQSCTL_QSCNTEN_SHIFT 14 +#define DDR_PHY_DX8SL0DQSCTL_QSCNTEN_MASK 0x00004000U -/*Unused DQ I/O Mode*/ +/* +* Unused DQ I/O Mode +*/ #undef DDR_PHY_DX8SL0DQSCTL_UDQIOM_DEFVAL #undef DDR_PHY_DX8SL0DQSCTL_UDQIOM_SHIFT #undef DDR_PHY_DX8SL0DQSCTL_UDQIOM_MASK -#define DDR_PHY_DX8SL0DQSCTL_UDQIOM_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL0DQSCTL_UDQIOM_SHIFT 13 -#define DDR_PHY_DX8SL0DQSCTL_UDQIOM_MASK 0x00002000U +#define DDR_PHY_DX8SL0DQSCTL_UDQIOM_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL0DQSCTL_UDQIOM_SHIFT 13 +#define DDR_PHY_DX8SL0DQSCTL_UDQIOM_MASK 0x00002000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_DEFVAL #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_SHIFT #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_MASK -#define DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_SHIFT 10 -#define DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_MASK 0x00001C00U +#define DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_SHIFT 10 +#define DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_MASK 0x00001C00U -/*Data Slew Rate*/ +/* +* Data Slew Rate +*/ #undef DDR_PHY_DX8SL0DQSCTL_DXSR_DEFVAL #undef DDR_PHY_DX8SL0DQSCTL_DXSR_SHIFT #undef DDR_PHY_DX8SL0DQSCTL_DXSR_MASK -#define DDR_PHY_DX8SL0DQSCTL_DXSR_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL0DQSCTL_DXSR_SHIFT 8 -#define DDR_PHY_DX8SL0DQSCTL_DXSR_MASK 0x00000300U +#define DDR_PHY_DX8SL0DQSCTL_DXSR_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL0DQSCTL_DXSR_SHIFT 8 +#define DDR_PHY_DX8SL0DQSCTL_DXSR_MASK 0x00000300U -/*DQS_N Resistor*/ +/* +* DQS_N Resistor +*/ #undef DDR_PHY_DX8SL0DQSCTL_DQSNRES_DEFVAL #undef DDR_PHY_DX8SL0DQSCTL_DQSNRES_SHIFT #undef DDR_PHY_DX8SL0DQSCTL_DQSNRES_MASK -#define DDR_PHY_DX8SL0DQSCTL_DQSNRES_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL0DQSCTL_DQSNRES_SHIFT 4 -#define DDR_PHY_DX8SL0DQSCTL_DQSNRES_MASK 0x000000F0U +#define DDR_PHY_DX8SL0DQSCTL_DQSNRES_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL0DQSCTL_DQSNRES_SHIFT 4 +#define DDR_PHY_DX8SL0DQSCTL_DQSNRES_MASK 0x000000F0U -/*DQS Resistor*/ +/* +* DQS Resistor +*/ #undef DDR_PHY_DX8SL0DQSCTL_DQSRES_DEFVAL #undef DDR_PHY_DX8SL0DQSCTL_DQSRES_SHIFT #undef DDR_PHY_DX8SL0DQSCTL_DQSRES_MASK -#define DDR_PHY_DX8SL0DQSCTL_DQSRES_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL0DQSCTL_DQSRES_SHIFT 0 -#define DDR_PHY_DX8SL0DQSCTL_DQSRES_MASK 0x0000000FU +#define DDR_PHY_DX8SL0DQSCTL_DQSRES_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL0DQSCTL_DQSRES_SHIFT 0 +#define DDR_PHY_DX8SL0DQSCTL_DQSRES_MASK 0x0000000FU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_DEFVAL #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_SHIFT #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_MASK -#define DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_SHIFT 24 -#define DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_MASK 0xFF000000U +#define DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_SHIFT 24 +#define DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_MASK 0xFF000000U -/*Configurable Read Data Enable*/ +/* +* Configurable Read Data Enable +*/ #undef DDR_PHY_DX8SL0DXCTL2_CRDEN_DEFVAL #undef DDR_PHY_DX8SL0DXCTL2_CRDEN_SHIFT #undef DDR_PHY_DX8SL0DXCTL2_CRDEN_MASK -#define DDR_PHY_DX8SL0DXCTL2_CRDEN_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL0DXCTL2_CRDEN_SHIFT 23 -#define DDR_PHY_DX8SL0DXCTL2_CRDEN_MASK 0x00800000U +#define DDR_PHY_DX8SL0DXCTL2_CRDEN_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_CRDEN_SHIFT 23 +#define DDR_PHY_DX8SL0DXCTL2_CRDEN_MASK 0x00800000U -/*OX Extension during Post-amble*/ +/* +* OX Extension during Post-amble +*/ #undef DDR_PHY_DX8SL0DXCTL2_POSOEX_DEFVAL #undef DDR_PHY_DX8SL0DXCTL2_POSOEX_SHIFT #undef DDR_PHY_DX8SL0DXCTL2_POSOEX_MASK -#define DDR_PHY_DX8SL0DXCTL2_POSOEX_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL0DXCTL2_POSOEX_SHIFT 20 -#define DDR_PHY_DX8SL0DXCTL2_POSOEX_MASK 0x00700000U +#define DDR_PHY_DX8SL0DXCTL2_POSOEX_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_POSOEX_SHIFT 20 +#define DDR_PHY_DX8SL0DXCTL2_POSOEX_MASK 0x00700000U -/*OE Extension during Pre-amble*/ +/* +* OE Extension during Pre-amble +*/ #undef DDR_PHY_DX8SL0DXCTL2_PREOEX_DEFVAL #undef DDR_PHY_DX8SL0DXCTL2_PREOEX_SHIFT #undef DDR_PHY_DX8SL0DXCTL2_PREOEX_MASK -#define DDR_PHY_DX8SL0DXCTL2_PREOEX_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL0DXCTL2_PREOEX_SHIFT 18 -#define DDR_PHY_DX8SL0DXCTL2_PREOEX_MASK 0x000C0000U +#define DDR_PHY_DX8SL0DXCTL2_PREOEX_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_PREOEX_SHIFT 18 +#define DDR_PHY_DX8SL0DXCTL2_PREOEX_MASK 0x000C0000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_17_DEFVAL #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_17_SHIFT #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_17_MASK -#define DDR_PHY_DX8SL0DXCTL2_RESERVED_17_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL0DXCTL2_RESERVED_17_SHIFT 17 -#define DDR_PHY_DX8SL0DXCTL2_RESERVED_17_MASK 0x00020000U +#define DDR_PHY_DX8SL0DXCTL2_RESERVED_17_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_RESERVED_17_SHIFT 17 +#define DDR_PHY_DX8SL0DXCTL2_RESERVED_17_MASK 0x00020000U -/*I/O Assisted Gate Select*/ +/* +* I/O Assisted Gate Select +*/ #undef DDR_PHY_DX8SL0DXCTL2_IOAG_DEFVAL #undef DDR_PHY_DX8SL0DXCTL2_IOAG_SHIFT #undef DDR_PHY_DX8SL0DXCTL2_IOAG_MASK -#define DDR_PHY_DX8SL0DXCTL2_IOAG_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL0DXCTL2_IOAG_SHIFT 16 -#define DDR_PHY_DX8SL0DXCTL2_IOAG_MASK 0x00010000U +#define DDR_PHY_DX8SL0DXCTL2_IOAG_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_IOAG_SHIFT 16 +#define DDR_PHY_DX8SL0DXCTL2_IOAG_MASK 0x00010000U -/*I/O Loopback Select*/ +/* +* I/O Loopback Select +*/ #undef DDR_PHY_DX8SL0DXCTL2_IOLB_DEFVAL #undef DDR_PHY_DX8SL0DXCTL2_IOLB_SHIFT #undef DDR_PHY_DX8SL0DXCTL2_IOLB_MASK -#define DDR_PHY_DX8SL0DXCTL2_IOLB_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL0DXCTL2_IOLB_SHIFT 15 -#define DDR_PHY_DX8SL0DXCTL2_IOLB_MASK 0x00008000U +#define DDR_PHY_DX8SL0DXCTL2_IOLB_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_IOLB_SHIFT 15 +#define DDR_PHY_DX8SL0DXCTL2_IOLB_MASK 0x00008000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_DEFVAL #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_SHIFT #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_MASK -#define DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_SHIFT 13 -#define DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_MASK 0x00006000U +#define DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_SHIFT 13 +#define DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_MASK 0x00006000U -/*Low Power Wakeup Threshold*/ +/* +* Low Power Wakeup Threshold +*/ #undef DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_DEFVAL #undef DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_SHIFT #undef DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_MASK -#define DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_SHIFT 9 -#define DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_MASK 0x00001E00U +#define DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_SHIFT 9 +#define DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_MASK 0x00001E00U -/*Read Data Bus Inversion Enable*/ +/* +* Read Data Bus Inversion Enable +*/ #undef DDR_PHY_DX8SL0DXCTL2_RDBI_DEFVAL #undef DDR_PHY_DX8SL0DXCTL2_RDBI_SHIFT #undef DDR_PHY_DX8SL0DXCTL2_RDBI_MASK -#define DDR_PHY_DX8SL0DXCTL2_RDBI_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL0DXCTL2_RDBI_SHIFT 8 -#define DDR_PHY_DX8SL0DXCTL2_RDBI_MASK 0x00000100U +#define DDR_PHY_DX8SL0DXCTL2_RDBI_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_RDBI_SHIFT 8 +#define DDR_PHY_DX8SL0DXCTL2_RDBI_MASK 0x00000100U -/*Write Data Bus Inversion Enable*/ +/* +* Write Data Bus Inversion Enable +*/ #undef DDR_PHY_DX8SL0DXCTL2_WDBI_DEFVAL #undef DDR_PHY_DX8SL0DXCTL2_WDBI_SHIFT #undef DDR_PHY_DX8SL0DXCTL2_WDBI_MASK -#define DDR_PHY_DX8SL0DXCTL2_WDBI_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL0DXCTL2_WDBI_SHIFT 7 -#define DDR_PHY_DX8SL0DXCTL2_WDBI_MASK 0x00000080U +#define DDR_PHY_DX8SL0DXCTL2_WDBI_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_WDBI_SHIFT 7 +#define DDR_PHY_DX8SL0DXCTL2_WDBI_MASK 0x00000080U -/*PUB Read FIFO Bypass*/ +/* +* PUB Read FIFO Bypass +*/ #undef DDR_PHY_DX8SL0DXCTL2_PRFBYP_DEFVAL #undef DDR_PHY_DX8SL0DXCTL2_PRFBYP_SHIFT #undef DDR_PHY_DX8SL0DXCTL2_PRFBYP_MASK -#define DDR_PHY_DX8SL0DXCTL2_PRFBYP_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL0DXCTL2_PRFBYP_SHIFT 6 -#define DDR_PHY_DX8SL0DXCTL2_PRFBYP_MASK 0x00000040U +#define DDR_PHY_DX8SL0DXCTL2_PRFBYP_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_PRFBYP_SHIFT 6 +#define DDR_PHY_DX8SL0DXCTL2_PRFBYP_MASK 0x00000040U -/*DATX8 Receive FIFO Read Mode*/ +/* +* DATX8 Receive FIFO Read Mode +*/ #undef DDR_PHY_DX8SL0DXCTL2_RDMODE_DEFVAL #undef DDR_PHY_DX8SL0DXCTL2_RDMODE_SHIFT #undef DDR_PHY_DX8SL0DXCTL2_RDMODE_MASK -#define DDR_PHY_DX8SL0DXCTL2_RDMODE_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL0DXCTL2_RDMODE_SHIFT 4 -#define DDR_PHY_DX8SL0DXCTL2_RDMODE_MASK 0x00000030U +#define DDR_PHY_DX8SL0DXCTL2_RDMODE_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_RDMODE_SHIFT 4 +#define DDR_PHY_DX8SL0DXCTL2_RDMODE_MASK 0x00000030U -/*Disables the Read FIFO Reset*/ +/* +* Disables the Read FIFO Reset +*/ #undef DDR_PHY_DX8SL0DXCTL2_DISRST_DEFVAL #undef DDR_PHY_DX8SL0DXCTL2_DISRST_SHIFT #undef DDR_PHY_DX8SL0DXCTL2_DISRST_MASK -#define DDR_PHY_DX8SL0DXCTL2_DISRST_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL0DXCTL2_DISRST_SHIFT 3 -#define DDR_PHY_DX8SL0DXCTL2_DISRST_MASK 0x00000008U +#define DDR_PHY_DX8SL0DXCTL2_DISRST_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_DISRST_SHIFT 3 +#define DDR_PHY_DX8SL0DXCTL2_DISRST_MASK 0x00000008U -/*Read DQS Gate I/O Loopback*/ +/* +* Read DQS Gate I/O Loopback +*/ #undef DDR_PHY_DX8SL0DXCTL2_DQSGLB_DEFVAL #undef DDR_PHY_DX8SL0DXCTL2_DQSGLB_SHIFT #undef DDR_PHY_DX8SL0DXCTL2_DQSGLB_MASK -#define DDR_PHY_DX8SL0DXCTL2_DQSGLB_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL0DXCTL2_DQSGLB_SHIFT 1 -#define DDR_PHY_DX8SL0DXCTL2_DQSGLB_MASK 0x00000006U +#define DDR_PHY_DX8SL0DXCTL2_DQSGLB_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_DQSGLB_SHIFT 1 +#define DDR_PHY_DX8SL0DXCTL2_DQSGLB_MASK 0x00000006U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_0_DEFVAL #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_0_SHIFT #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_0_MASK -#define DDR_PHY_DX8SL0DXCTL2_RESERVED_0_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL0DXCTL2_RESERVED_0_SHIFT 0 -#define DDR_PHY_DX8SL0DXCTL2_RESERVED_0_MASK 0x00000001U +#define DDR_PHY_DX8SL0DXCTL2_RESERVED_0_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_RESERVED_0_SHIFT 0 +#define DDR_PHY_DX8SL0DXCTL2_RESERVED_0_MASK 0x00000001U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL0IOCR_RESERVED_31_DEFVAL #undef DDR_PHY_DX8SL0IOCR_RESERVED_31_SHIFT #undef DDR_PHY_DX8SL0IOCR_RESERVED_31_MASK -#define DDR_PHY_DX8SL0IOCR_RESERVED_31_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL0IOCR_RESERVED_31_SHIFT 31 -#define DDR_PHY_DX8SL0IOCR_RESERVED_31_MASK 0x80000000U +#define DDR_PHY_DX8SL0IOCR_RESERVED_31_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL0IOCR_RESERVED_31_SHIFT 31 +#define DDR_PHY_DX8SL0IOCR_RESERVED_31_MASK 0x80000000U -/*PVREF_DAC REFSEL range select*/ +/* +* PVREF_DAC REFSEL range select +*/ #undef DDR_PHY_DX8SL0IOCR_DXDACRANGE_DEFVAL #undef DDR_PHY_DX8SL0IOCR_DXDACRANGE_SHIFT #undef DDR_PHY_DX8SL0IOCR_DXDACRANGE_MASK -#define DDR_PHY_DX8SL0IOCR_DXDACRANGE_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL0IOCR_DXDACRANGE_SHIFT 28 -#define DDR_PHY_DX8SL0IOCR_DXDACRANGE_MASK 0x70000000U +#define DDR_PHY_DX8SL0IOCR_DXDACRANGE_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL0IOCR_DXDACRANGE_SHIFT 28 +#define DDR_PHY_DX8SL0IOCR_DXDACRANGE_MASK 0x70000000U -/*IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring*/ +/* +* IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring +*/ #undef DDR_PHY_DX8SL0IOCR_DXVREFIOM_DEFVAL #undef DDR_PHY_DX8SL0IOCR_DXVREFIOM_SHIFT #undef DDR_PHY_DX8SL0IOCR_DXVREFIOM_MASK -#define DDR_PHY_DX8SL0IOCR_DXVREFIOM_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL0IOCR_DXVREFIOM_SHIFT 25 -#define DDR_PHY_DX8SL0IOCR_DXVREFIOM_MASK 0x0E000000U +#define DDR_PHY_DX8SL0IOCR_DXVREFIOM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL0IOCR_DXVREFIOM_SHIFT 25 +#define DDR_PHY_DX8SL0IOCR_DXVREFIOM_MASK 0x0E000000U -/*DX IO Mode*/ +/* +* DX IO Mode +*/ #undef DDR_PHY_DX8SL0IOCR_DXIOM_DEFVAL #undef DDR_PHY_DX8SL0IOCR_DXIOM_SHIFT #undef DDR_PHY_DX8SL0IOCR_DXIOM_MASK -#define DDR_PHY_DX8SL0IOCR_DXIOM_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL0IOCR_DXIOM_SHIFT 22 -#define DDR_PHY_DX8SL0IOCR_DXIOM_MASK 0x01C00000U +#define DDR_PHY_DX8SL0IOCR_DXIOM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL0IOCR_DXIOM_SHIFT 22 +#define DDR_PHY_DX8SL0IOCR_DXIOM_MASK 0x01C00000U -/*DX IO Transmitter Mode*/ +/* +* DX IO Transmitter Mode +*/ #undef DDR_PHY_DX8SL0IOCR_DXTXM_DEFVAL #undef DDR_PHY_DX8SL0IOCR_DXTXM_SHIFT #undef DDR_PHY_DX8SL0IOCR_DXTXM_MASK -#define DDR_PHY_DX8SL0IOCR_DXTXM_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL0IOCR_DXTXM_SHIFT 11 -#define DDR_PHY_DX8SL0IOCR_DXTXM_MASK 0x003FF800U +#define DDR_PHY_DX8SL0IOCR_DXTXM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL0IOCR_DXTXM_SHIFT 11 +#define DDR_PHY_DX8SL0IOCR_DXTXM_MASK 0x003FF800U -/*DX IO Receiver Mode*/ +/* +* DX IO Receiver Mode +*/ #undef DDR_PHY_DX8SL0IOCR_DXRXM_DEFVAL #undef DDR_PHY_DX8SL0IOCR_DXRXM_SHIFT #undef DDR_PHY_DX8SL0IOCR_DXRXM_MASK -#define DDR_PHY_DX8SL0IOCR_DXRXM_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL0IOCR_DXRXM_SHIFT 0 -#define DDR_PHY_DX8SL0IOCR_DXRXM_MASK 0x000007FFU +#define DDR_PHY_DX8SL0IOCR_DXRXM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL0IOCR_DXRXM_SHIFT 0 +#define DDR_PHY_DX8SL0IOCR_DXRXM_MASK 0x000007FFU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL1OSC_RESERVED_31_30_DEFVAL #undef DDR_PHY_DX8SL1OSC_RESERVED_31_30_SHIFT #undef DDR_PHY_DX8SL1OSC_RESERVED_31_30_MASK -#define DDR_PHY_DX8SL1OSC_RESERVED_31_30_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL1OSC_RESERVED_31_30_SHIFT 30 -#define DDR_PHY_DX8SL1OSC_RESERVED_31_30_MASK 0xC0000000U +#define DDR_PHY_DX8SL1OSC_RESERVED_31_30_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX8SL1OSC_RESERVED_31_30_MASK 0xC0000000U -/*Enable Clock Gating for DX ddr_clk*/ +/* +* Enable Clock Gating for DX ddr_clk +*/ #undef DDR_PHY_DX8SL1OSC_GATEDXRDCLK_DEFVAL #undef DDR_PHY_DX8SL1OSC_GATEDXRDCLK_SHIFT #undef DDR_PHY_DX8SL1OSC_GATEDXRDCLK_MASK -#define DDR_PHY_DX8SL1OSC_GATEDXRDCLK_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL1OSC_GATEDXRDCLK_SHIFT 28 -#define DDR_PHY_DX8SL1OSC_GATEDXRDCLK_MASK 0x30000000U +#define DDR_PHY_DX8SL1OSC_GATEDXRDCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_GATEDXRDCLK_SHIFT 28 +#define DDR_PHY_DX8SL1OSC_GATEDXRDCLK_MASK 0x30000000U -/*Enable Clock Gating for DX ctl_rd_clk*/ +/* +* Enable Clock Gating for DX ctl_rd_clk +*/ #undef DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_DEFVAL #undef DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_SHIFT #undef DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_MASK -#define DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_SHIFT 26 -#define DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_MASK 0x0C000000U +#define DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_SHIFT 26 +#define DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_MASK 0x0C000000U -/*Enable Clock Gating for DX ctl_clk*/ +/* +* Enable Clock Gating for DX ctl_clk +*/ #undef DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_DEFVAL #undef DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_SHIFT #undef DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_MASK -#define DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_SHIFT 24 -#define DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_MASK 0x03000000U +#define DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_SHIFT 24 +#define DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_MASK 0x03000000U -/*Selects the level to which clocks will be stalled when clock gating is enabled.*/ +/* +* Selects the level to which clocks will be stalled when clock gating is e + * nabled. +*/ #undef DDR_PHY_DX8SL1OSC_CLKLEVEL_DEFVAL #undef DDR_PHY_DX8SL1OSC_CLKLEVEL_SHIFT #undef DDR_PHY_DX8SL1OSC_CLKLEVEL_MASK -#define DDR_PHY_DX8SL1OSC_CLKLEVEL_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL1OSC_CLKLEVEL_SHIFT 22 -#define DDR_PHY_DX8SL1OSC_CLKLEVEL_MASK 0x00C00000U +#define DDR_PHY_DX8SL1OSC_CLKLEVEL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_CLKLEVEL_SHIFT 22 +#define DDR_PHY_DX8SL1OSC_CLKLEVEL_MASK 0x00C00000U -/*Loopback Mode*/ +/* +* Loopback Mode +*/ #undef DDR_PHY_DX8SL1OSC_LBMODE_DEFVAL #undef DDR_PHY_DX8SL1OSC_LBMODE_SHIFT #undef DDR_PHY_DX8SL1OSC_LBMODE_MASK -#define DDR_PHY_DX8SL1OSC_LBMODE_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL1OSC_LBMODE_SHIFT 21 -#define DDR_PHY_DX8SL1OSC_LBMODE_MASK 0x00200000U +#define DDR_PHY_DX8SL1OSC_LBMODE_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_LBMODE_SHIFT 21 +#define DDR_PHY_DX8SL1OSC_LBMODE_MASK 0x00200000U -/*Load GSDQS LCDL with 2x the calibrated GSDQSPRD value*/ +/* +* Load GSDQS LCDL with 2x the calibrated GSDQSPRD value +*/ #undef DDR_PHY_DX8SL1OSC_LBGSDQS_DEFVAL #undef DDR_PHY_DX8SL1OSC_LBGSDQS_SHIFT #undef DDR_PHY_DX8SL1OSC_LBGSDQS_MASK -#define DDR_PHY_DX8SL1OSC_LBGSDQS_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL1OSC_LBGSDQS_SHIFT 20 -#define DDR_PHY_DX8SL1OSC_LBGSDQS_MASK 0x00100000U +#define DDR_PHY_DX8SL1OSC_LBGSDQS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_LBGSDQS_SHIFT 20 +#define DDR_PHY_DX8SL1OSC_LBGSDQS_MASK 0x00100000U -/*Loopback DQS Gating*/ +/* +* Loopback DQS Gating +*/ #undef DDR_PHY_DX8SL1OSC_LBGDQS_DEFVAL #undef DDR_PHY_DX8SL1OSC_LBGDQS_SHIFT #undef DDR_PHY_DX8SL1OSC_LBGDQS_MASK -#define DDR_PHY_DX8SL1OSC_LBGDQS_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL1OSC_LBGDQS_SHIFT 18 -#define DDR_PHY_DX8SL1OSC_LBGDQS_MASK 0x000C0000U +#define DDR_PHY_DX8SL1OSC_LBGDQS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_LBGDQS_SHIFT 18 +#define DDR_PHY_DX8SL1OSC_LBGDQS_MASK 0x000C0000U -/*Loopback DQS Shift*/ +/* +* Loopback DQS Shift +*/ #undef DDR_PHY_DX8SL1OSC_LBDQSS_DEFVAL #undef DDR_PHY_DX8SL1OSC_LBDQSS_SHIFT #undef DDR_PHY_DX8SL1OSC_LBDQSS_MASK -#define DDR_PHY_DX8SL1OSC_LBDQSS_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL1OSC_LBDQSS_SHIFT 17 -#define DDR_PHY_DX8SL1OSC_LBDQSS_MASK 0x00020000U +#define DDR_PHY_DX8SL1OSC_LBDQSS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_LBDQSS_SHIFT 17 +#define DDR_PHY_DX8SL1OSC_LBDQSS_MASK 0x00020000U -/*PHY High-Speed Reset*/ +/* +* PHY High-Speed Reset +*/ #undef DDR_PHY_DX8SL1OSC_PHYHRST_DEFVAL #undef DDR_PHY_DX8SL1OSC_PHYHRST_SHIFT #undef DDR_PHY_DX8SL1OSC_PHYHRST_MASK -#define DDR_PHY_DX8SL1OSC_PHYHRST_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL1OSC_PHYHRST_SHIFT 16 -#define DDR_PHY_DX8SL1OSC_PHYHRST_MASK 0x00010000U +#define DDR_PHY_DX8SL1OSC_PHYHRST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_PHYHRST_SHIFT 16 +#define DDR_PHY_DX8SL1OSC_PHYHRST_MASK 0x00010000U -/*PHY FIFO Reset*/ +/* +* PHY FIFO Reset +*/ #undef DDR_PHY_DX8SL1OSC_PHYFRST_DEFVAL #undef DDR_PHY_DX8SL1OSC_PHYFRST_SHIFT #undef DDR_PHY_DX8SL1OSC_PHYFRST_MASK -#define DDR_PHY_DX8SL1OSC_PHYFRST_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL1OSC_PHYFRST_SHIFT 15 -#define DDR_PHY_DX8SL1OSC_PHYFRST_MASK 0x00008000U +#define DDR_PHY_DX8SL1OSC_PHYFRST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_PHYFRST_SHIFT 15 +#define DDR_PHY_DX8SL1OSC_PHYFRST_MASK 0x00008000U -/*Delay Line Test Start*/ +/* +* Delay Line Test Start +*/ #undef DDR_PHY_DX8SL1OSC_DLTST_DEFVAL #undef DDR_PHY_DX8SL1OSC_DLTST_SHIFT #undef DDR_PHY_DX8SL1OSC_DLTST_MASK -#define DDR_PHY_DX8SL1OSC_DLTST_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL1OSC_DLTST_SHIFT 14 -#define DDR_PHY_DX8SL1OSC_DLTST_MASK 0x00004000U +#define DDR_PHY_DX8SL1OSC_DLTST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_DLTST_SHIFT 14 +#define DDR_PHY_DX8SL1OSC_DLTST_MASK 0x00004000U -/*Delay Line Test Mode*/ +/* +* Delay Line Test Mode +*/ #undef DDR_PHY_DX8SL1OSC_DLTMODE_DEFVAL #undef DDR_PHY_DX8SL1OSC_DLTMODE_SHIFT #undef DDR_PHY_DX8SL1OSC_DLTMODE_MASK -#define DDR_PHY_DX8SL1OSC_DLTMODE_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL1OSC_DLTMODE_SHIFT 13 -#define DDR_PHY_DX8SL1OSC_DLTMODE_MASK 0x00002000U +#define DDR_PHY_DX8SL1OSC_DLTMODE_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_DLTMODE_SHIFT 13 +#define DDR_PHY_DX8SL1OSC_DLTMODE_MASK 0x00002000U -/*Reserved. Caution, do not write to this register field.*/ +/* +* Reserved. Caution, do not write to this register field. +*/ #undef DDR_PHY_DX8SL1OSC_RESERVED_12_11_DEFVAL #undef DDR_PHY_DX8SL1OSC_RESERVED_12_11_SHIFT #undef DDR_PHY_DX8SL1OSC_RESERVED_12_11_MASK -#define DDR_PHY_DX8SL1OSC_RESERVED_12_11_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL1OSC_RESERVED_12_11_SHIFT 11 -#define DDR_PHY_DX8SL1OSC_RESERVED_12_11_MASK 0x00001800U +#define DDR_PHY_DX8SL1OSC_RESERVED_12_11_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_RESERVED_12_11_SHIFT 11 +#define DDR_PHY_DX8SL1OSC_RESERVED_12_11_MASK 0x00001800U -/*Oscillator Mode Write-Data Delay Line Select*/ +/* +* Oscillator Mode Write-Data Delay Line Select +*/ #undef DDR_PHY_DX8SL1OSC_OSCWDDL_DEFVAL #undef DDR_PHY_DX8SL1OSC_OSCWDDL_SHIFT #undef DDR_PHY_DX8SL1OSC_OSCWDDL_MASK -#define DDR_PHY_DX8SL1OSC_OSCWDDL_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL1OSC_OSCWDDL_SHIFT 9 -#define DDR_PHY_DX8SL1OSC_OSCWDDL_MASK 0x00000600U +#define DDR_PHY_DX8SL1OSC_OSCWDDL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_OSCWDDL_SHIFT 9 +#define DDR_PHY_DX8SL1OSC_OSCWDDL_MASK 0x00000600U -/*Reserved. Caution, do not write to this register field.*/ +/* +* Reserved. Caution, do not write to this register field. +*/ #undef DDR_PHY_DX8SL1OSC_RESERVED_8_7_DEFVAL #undef DDR_PHY_DX8SL1OSC_RESERVED_8_7_SHIFT #undef DDR_PHY_DX8SL1OSC_RESERVED_8_7_MASK -#define DDR_PHY_DX8SL1OSC_RESERVED_8_7_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL1OSC_RESERVED_8_7_SHIFT 7 -#define DDR_PHY_DX8SL1OSC_RESERVED_8_7_MASK 0x00000180U +#define DDR_PHY_DX8SL1OSC_RESERVED_8_7_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_RESERVED_8_7_SHIFT 7 +#define DDR_PHY_DX8SL1OSC_RESERVED_8_7_MASK 0x00000180U -/*Oscillator Mode Write-Leveling Delay Line Select*/ +/* +* Oscillator Mode Write-Leveling Delay Line Select +*/ #undef DDR_PHY_DX8SL1OSC_OSCWDL_DEFVAL #undef DDR_PHY_DX8SL1OSC_OSCWDL_SHIFT #undef DDR_PHY_DX8SL1OSC_OSCWDL_MASK -#define DDR_PHY_DX8SL1OSC_OSCWDL_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL1OSC_OSCWDL_SHIFT 5 -#define DDR_PHY_DX8SL1OSC_OSCWDL_MASK 0x00000060U +#define DDR_PHY_DX8SL1OSC_OSCWDL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_OSCWDL_SHIFT 5 +#define DDR_PHY_DX8SL1OSC_OSCWDL_MASK 0x00000060U -/*Oscillator Mode Division*/ +/* +* Oscillator Mode Division +*/ #undef DDR_PHY_DX8SL1OSC_OSCDIV_DEFVAL #undef DDR_PHY_DX8SL1OSC_OSCDIV_SHIFT #undef DDR_PHY_DX8SL1OSC_OSCDIV_MASK -#define DDR_PHY_DX8SL1OSC_OSCDIV_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL1OSC_OSCDIV_SHIFT 1 -#define DDR_PHY_DX8SL1OSC_OSCDIV_MASK 0x0000001EU +#define DDR_PHY_DX8SL1OSC_OSCDIV_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_OSCDIV_SHIFT 1 +#define DDR_PHY_DX8SL1OSC_OSCDIV_MASK 0x0000001EU -/*Oscillator Enable*/ +/* +* Oscillator Enable +*/ #undef DDR_PHY_DX8SL1OSC_OSCEN_DEFVAL #undef DDR_PHY_DX8SL1OSC_OSCEN_SHIFT #undef DDR_PHY_DX8SL1OSC_OSCEN_MASK -#define DDR_PHY_DX8SL1OSC_OSCEN_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL1OSC_OSCEN_SHIFT 0 -#define DDR_PHY_DX8SL1OSC_OSCEN_MASK 0x00000001U +#define DDR_PHY_DX8SL1OSC_OSCEN_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_OSCEN_SHIFT 0 +#define DDR_PHY_DX8SL1OSC_OSCEN_MASK 0x00000001U -/*Reserved. Return zeroes on reads.*/ +/* +* PLL Bypass +*/ +#undef DDR_PHY_DX8SL1PLLCR0_PLLBYP_DEFVAL +#undef DDR_PHY_DX8SL1PLLCR0_PLLBYP_SHIFT +#undef DDR_PHY_DX8SL1PLLCR0_PLLBYP_MASK +#define DDR_PHY_DX8SL1PLLCR0_PLLBYP_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL1PLLCR0_PLLBYP_SHIFT 31 +#define DDR_PHY_DX8SL1PLLCR0_PLLBYP_MASK 0x80000000U + +/* +* PLL Reset +*/ +#undef DDR_PHY_DX8SL1PLLCR0_PLLRST_DEFVAL +#undef DDR_PHY_DX8SL1PLLCR0_PLLRST_SHIFT +#undef DDR_PHY_DX8SL1PLLCR0_PLLRST_MASK +#define DDR_PHY_DX8SL1PLLCR0_PLLRST_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL1PLLCR0_PLLRST_SHIFT 30 +#define DDR_PHY_DX8SL1PLLCR0_PLLRST_MASK 0x40000000U + +/* +* PLL Power Down +*/ +#undef DDR_PHY_DX8SL1PLLCR0_PLLPD_DEFVAL +#undef DDR_PHY_DX8SL1PLLCR0_PLLPD_SHIFT +#undef DDR_PHY_DX8SL1PLLCR0_PLLPD_MASK +#define DDR_PHY_DX8SL1PLLCR0_PLLPD_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL1PLLCR0_PLLPD_SHIFT 29 +#define DDR_PHY_DX8SL1PLLCR0_PLLPD_MASK 0x20000000U + +/* +* Reference Stop Mode +*/ +#undef DDR_PHY_DX8SL1PLLCR0_RSTOPM_DEFVAL +#undef DDR_PHY_DX8SL1PLLCR0_RSTOPM_SHIFT +#undef DDR_PHY_DX8SL1PLLCR0_RSTOPM_MASK +#define DDR_PHY_DX8SL1PLLCR0_RSTOPM_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL1PLLCR0_RSTOPM_SHIFT 28 +#define DDR_PHY_DX8SL1PLLCR0_RSTOPM_MASK 0x10000000U + +/* +* PLL Frequency Select +*/ +#undef DDR_PHY_DX8SL1PLLCR0_FRQSEL_DEFVAL +#undef DDR_PHY_DX8SL1PLLCR0_FRQSEL_SHIFT +#undef DDR_PHY_DX8SL1PLLCR0_FRQSEL_MASK +#define DDR_PHY_DX8SL1PLLCR0_FRQSEL_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL1PLLCR0_FRQSEL_SHIFT 24 +#define DDR_PHY_DX8SL1PLLCR0_FRQSEL_MASK 0x0F000000U + +/* +* Relock Mode +*/ +#undef DDR_PHY_DX8SL1PLLCR0_RLOCKM_DEFVAL +#undef DDR_PHY_DX8SL1PLLCR0_RLOCKM_SHIFT +#undef DDR_PHY_DX8SL1PLLCR0_RLOCKM_MASK +#define DDR_PHY_DX8SL1PLLCR0_RLOCKM_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL1PLLCR0_RLOCKM_SHIFT 23 +#define DDR_PHY_DX8SL1PLLCR0_RLOCKM_MASK 0x00800000U + +/* +* Charge Pump Proportional Current Control +*/ +#undef DDR_PHY_DX8SL1PLLCR0_CPPC_DEFVAL +#undef DDR_PHY_DX8SL1PLLCR0_CPPC_SHIFT +#undef DDR_PHY_DX8SL1PLLCR0_CPPC_MASK +#define DDR_PHY_DX8SL1PLLCR0_CPPC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL1PLLCR0_CPPC_SHIFT 17 +#define DDR_PHY_DX8SL1PLLCR0_CPPC_MASK 0x007E0000U + +/* +* Charge Pump Integrating Current Control +*/ +#undef DDR_PHY_DX8SL1PLLCR0_CPIC_DEFVAL +#undef DDR_PHY_DX8SL1PLLCR0_CPIC_SHIFT +#undef DDR_PHY_DX8SL1PLLCR0_CPIC_MASK +#define DDR_PHY_DX8SL1PLLCR0_CPIC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL1PLLCR0_CPIC_SHIFT 13 +#define DDR_PHY_DX8SL1PLLCR0_CPIC_MASK 0x0001E000U + +/* +* Gear Shift +*/ +#undef DDR_PHY_DX8SL1PLLCR0_GSHIFT_DEFVAL +#undef DDR_PHY_DX8SL1PLLCR0_GSHIFT_SHIFT +#undef DDR_PHY_DX8SL1PLLCR0_GSHIFT_MASK +#define DDR_PHY_DX8SL1PLLCR0_GSHIFT_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL1PLLCR0_GSHIFT_SHIFT 12 +#define DDR_PHY_DX8SL1PLLCR0_GSHIFT_MASK 0x00001000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL1PLLCR0_RESERVED_11_9_DEFVAL +#undef DDR_PHY_DX8SL1PLLCR0_RESERVED_11_9_SHIFT +#undef DDR_PHY_DX8SL1PLLCR0_RESERVED_11_9_MASK +#define DDR_PHY_DX8SL1PLLCR0_RESERVED_11_9_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL1PLLCR0_RESERVED_11_9_SHIFT 9 +#define DDR_PHY_DX8SL1PLLCR0_RESERVED_11_9_MASK 0x00000E00U + +/* +* Analog Test Enable (ATOEN) +*/ +#undef DDR_PHY_DX8SL1PLLCR0_ATOEN_DEFVAL +#undef DDR_PHY_DX8SL1PLLCR0_ATOEN_SHIFT +#undef DDR_PHY_DX8SL1PLLCR0_ATOEN_MASK +#define DDR_PHY_DX8SL1PLLCR0_ATOEN_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL1PLLCR0_ATOEN_SHIFT 8 +#define DDR_PHY_DX8SL1PLLCR0_ATOEN_MASK 0x00000100U + +/* +* Analog Test Control +*/ +#undef DDR_PHY_DX8SL1PLLCR0_ATC_DEFVAL +#undef DDR_PHY_DX8SL1PLLCR0_ATC_SHIFT +#undef DDR_PHY_DX8SL1PLLCR0_ATC_MASK +#define DDR_PHY_DX8SL1PLLCR0_ATC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL1PLLCR0_ATC_SHIFT 4 +#define DDR_PHY_DX8SL1PLLCR0_ATC_MASK 0x000000F0U + +/* +* Digital Test Control +*/ +#undef DDR_PHY_DX8SL1PLLCR0_DTC_DEFVAL +#undef DDR_PHY_DX8SL1PLLCR0_DTC_SHIFT +#undef DDR_PHY_DX8SL1PLLCR0_DTC_MASK +#define DDR_PHY_DX8SL1PLLCR0_DTC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL1PLLCR0_DTC_SHIFT 0 +#define DDR_PHY_DX8SL1PLLCR0_DTC_MASK 0x0000000FU + +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_DEFVAL #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_SHIFT #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_MASK -#define DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_SHIFT 25 -#define DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_MASK 0xFE000000U +#define DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_SHIFT 25 +#define DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_MASK 0xFE000000U -/*Read Path Rise-to-Rise Mode*/ +/* +* Read Path Rise-to-Rise Mode +*/ #undef DDR_PHY_DX8SL1DQSCTL_RRRMODE_DEFVAL #undef DDR_PHY_DX8SL1DQSCTL_RRRMODE_SHIFT #undef DDR_PHY_DX8SL1DQSCTL_RRRMODE_MASK -#define DDR_PHY_DX8SL1DQSCTL_RRRMODE_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL1DQSCTL_RRRMODE_SHIFT 24 -#define DDR_PHY_DX8SL1DQSCTL_RRRMODE_MASK 0x01000000U +#define DDR_PHY_DX8SL1DQSCTL_RRRMODE_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL1DQSCTL_RRRMODE_SHIFT 24 +#define DDR_PHY_DX8SL1DQSCTL_RRRMODE_MASK 0x01000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_DEFVAL #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_SHIFT #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_MASK -#define DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_SHIFT 22 -#define DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_MASK 0x00C00000U +#define DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_MASK 0x00C00000U -/*Write Path Rise-to-Rise Mode*/ +/* +* Write Path Rise-to-Rise Mode +*/ #undef DDR_PHY_DX8SL1DQSCTL_WRRMODE_DEFVAL #undef DDR_PHY_DX8SL1DQSCTL_WRRMODE_SHIFT #undef DDR_PHY_DX8SL1DQSCTL_WRRMODE_MASK -#define DDR_PHY_DX8SL1DQSCTL_WRRMODE_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL1DQSCTL_WRRMODE_SHIFT 21 -#define DDR_PHY_DX8SL1DQSCTL_WRRMODE_MASK 0x00200000U +#define DDR_PHY_DX8SL1DQSCTL_WRRMODE_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL1DQSCTL_WRRMODE_SHIFT 21 +#define DDR_PHY_DX8SL1DQSCTL_WRRMODE_MASK 0x00200000U -/*DQS Gate Extension*/ +/* +* DQS Gate Extension +*/ #undef DDR_PHY_DX8SL1DQSCTL_DQSGX_DEFVAL #undef DDR_PHY_DX8SL1DQSCTL_DQSGX_SHIFT #undef DDR_PHY_DX8SL1DQSCTL_DQSGX_MASK -#define DDR_PHY_DX8SL1DQSCTL_DQSGX_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL1DQSCTL_DQSGX_SHIFT 19 -#define DDR_PHY_DX8SL1DQSCTL_DQSGX_MASK 0x00180000U +#define DDR_PHY_DX8SL1DQSCTL_DQSGX_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL1DQSCTL_DQSGX_SHIFT 19 +#define DDR_PHY_DX8SL1DQSCTL_DQSGX_MASK 0x00180000U -/*Low Power PLL Power Down*/ +/* +* Low Power PLL Power Down +*/ #undef DDR_PHY_DX8SL1DQSCTL_LPPLLPD_DEFVAL #undef DDR_PHY_DX8SL1DQSCTL_LPPLLPD_SHIFT #undef DDR_PHY_DX8SL1DQSCTL_LPPLLPD_MASK -#define DDR_PHY_DX8SL1DQSCTL_LPPLLPD_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL1DQSCTL_LPPLLPD_SHIFT 18 -#define DDR_PHY_DX8SL1DQSCTL_LPPLLPD_MASK 0x00040000U +#define DDR_PHY_DX8SL1DQSCTL_LPPLLPD_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL1DQSCTL_LPPLLPD_SHIFT 18 +#define DDR_PHY_DX8SL1DQSCTL_LPPLLPD_MASK 0x00040000U -/*Low Power I/O Power Down*/ +/* +* Low Power I/O Power Down +*/ #undef DDR_PHY_DX8SL1DQSCTL_LPIOPD_DEFVAL #undef DDR_PHY_DX8SL1DQSCTL_LPIOPD_SHIFT #undef DDR_PHY_DX8SL1DQSCTL_LPIOPD_MASK -#define DDR_PHY_DX8SL1DQSCTL_LPIOPD_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL1DQSCTL_LPIOPD_SHIFT 17 -#define DDR_PHY_DX8SL1DQSCTL_LPIOPD_MASK 0x00020000U +#define DDR_PHY_DX8SL1DQSCTL_LPIOPD_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL1DQSCTL_LPIOPD_SHIFT 17 +#define DDR_PHY_DX8SL1DQSCTL_LPIOPD_MASK 0x00020000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_DEFVAL #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_SHIFT #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_MASK -#define DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_SHIFT 15 -#define DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_MASK 0x00018000U +#define DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_SHIFT 15 +#define DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_MASK 0x00018000U -/*QS Counter Enable*/ +/* +* QS Counter Enable +*/ #undef DDR_PHY_DX8SL1DQSCTL_QSCNTEN_DEFVAL #undef DDR_PHY_DX8SL1DQSCTL_QSCNTEN_SHIFT #undef DDR_PHY_DX8SL1DQSCTL_QSCNTEN_MASK -#define DDR_PHY_DX8SL1DQSCTL_QSCNTEN_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL1DQSCTL_QSCNTEN_SHIFT 14 -#define DDR_PHY_DX8SL1DQSCTL_QSCNTEN_MASK 0x00004000U +#define DDR_PHY_DX8SL1DQSCTL_QSCNTEN_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL1DQSCTL_QSCNTEN_SHIFT 14 +#define DDR_PHY_DX8SL1DQSCTL_QSCNTEN_MASK 0x00004000U -/*Unused DQ I/O Mode*/ +/* +* Unused DQ I/O Mode +*/ #undef DDR_PHY_DX8SL1DQSCTL_UDQIOM_DEFVAL #undef DDR_PHY_DX8SL1DQSCTL_UDQIOM_SHIFT #undef DDR_PHY_DX8SL1DQSCTL_UDQIOM_MASK -#define DDR_PHY_DX8SL1DQSCTL_UDQIOM_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL1DQSCTL_UDQIOM_SHIFT 13 -#define DDR_PHY_DX8SL1DQSCTL_UDQIOM_MASK 0x00002000U +#define DDR_PHY_DX8SL1DQSCTL_UDQIOM_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL1DQSCTL_UDQIOM_SHIFT 13 +#define DDR_PHY_DX8SL1DQSCTL_UDQIOM_MASK 0x00002000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_DEFVAL #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_SHIFT #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_MASK -#define DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_SHIFT 10 -#define DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_MASK 0x00001C00U +#define DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_SHIFT 10 +#define DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_MASK 0x00001C00U -/*Data Slew Rate*/ +/* +* Data Slew Rate +*/ #undef DDR_PHY_DX8SL1DQSCTL_DXSR_DEFVAL #undef DDR_PHY_DX8SL1DQSCTL_DXSR_SHIFT #undef DDR_PHY_DX8SL1DQSCTL_DXSR_MASK -#define DDR_PHY_DX8SL1DQSCTL_DXSR_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL1DQSCTL_DXSR_SHIFT 8 -#define DDR_PHY_DX8SL1DQSCTL_DXSR_MASK 0x00000300U +#define DDR_PHY_DX8SL1DQSCTL_DXSR_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL1DQSCTL_DXSR_SHIFT 8 +#define DDR_PHY_DX8SL1DQSCTL_DXSR_MASK 0x00000300U -/*DQS_N Resistor*/ +/* +* DQS_N Resistor +*/ #undef DDR_PHY_DX8SL1DQSCTL_DQSNRES_DEFVAL #undef DDR_PHY_DX8SL1DQSCTL_DQSNRES_SHIFT #undef DDR_PHY_DX8SL1DQSCTL_DQSNRES_MASK -#define DDR_PHY_DX8SL1DQSCTL_DQSNRES_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL1DQSCTL_DQSNRES_SHIFT 4 -#define DDR_PHY_DX8SL1DQSCTL_DQSNRES_MASK 0x000000F0U +#define DDR_PHY_DX8SL1DQSCTL_DQSNRES_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL1DQSCTL_DQSNRES_SHIFT 4 +#define DDR_PHY_DX8SL1DQSCTL_DQSNRES_MASK 0x000000F0U -/*DQS Resistor*/ +/* +* DQS Resistor +*/ #undef DDR_PHY_DX8SL1DQSCTL_DQSRES_DEFVAL #undef DDR_PHY_DX8SL1DQSCTL_DQSRES_SHIFT #undef DDR_PHY_DX8SL1DQSCTL_DQSRES_MASK -#define DDR_PHY_DX8SL1DQSCTL_DQSRES_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL1DQSCTL_DQSRES_SHIFT 0 -#define DDR_PHY_DX8SL1DQSCTL_DQSRES_MASK 0x0000000FU +#define DDR_PHY_DX8SL1DQSCTL_DQSRES_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL1DQSCTL_DQSRES_SHIFT 0 +#define DDR_PHY_DX8SL1DQSCTL_DQSRES_MASK 0x0000000FU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_DEFVAL #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_SHIFT #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_MASK -#define DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_SHIFT 24 -#define DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_MASK 0xFF000000U +#define DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_SHIFT 24 +#define DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_MASK 0xFF000000U -/*Configurable Read Data Enable*/ +/* +* Configurable Read Data Enable +*/ #undef DDR_PHY_DX8SL1DXCTL2_CRDEN_DEFVAL #undef DDR_PHY_DX8SL1DXCTL2_CRDEN_SHIFT #undef DDR_PHY_DX8SL1DXCTL2_CRDEN_MASK -#define DDR_PHY_DX8SL1DXCTL2_CRDEN_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL1DXCTL2_CRDEN_SHIFT 23 -#define DDR_PHY_DX8SL1DXCTL2_CRDEN_MASK 0x00800000U +#define DDR_PHY_DX8SL1DXCTL2_CRDEN_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_CRDEN_SHIFT 23 +#define DDR_PHY_DX8SL1DXCTL2_CRDEN_MASK 0x00800000U -/*OX Extension during Post-amble*/ +/* +* OX Extension during Post-amble +*/ #undef DDR_PHY_DX8SL1DXCTL2_POSOEX_DEFVAL #undef DDR_PHY_DX8SL1DXCTL2_POSOEX_SHIFT #undef DDR_PHY_DX8SL1DXCTL2_POSOEX_MASK -#define DDR_PHY_DX8SL1DXCTL2_POSOEX_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL1DXCTL2_POSOEX_SHIFT 20 -#define DDR_PHY_DX8SL1DXCTL2_POSOEX_MASK 0x00700000U +#define DDR_PHY_DX8SL1DXCTL2_POSOEX_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_POSOEX_SHIFT 20 +#define DDR_PHY_DX8SL1DXCTL2_POSOEX_MASK 0x00700000U -/*OE Extension during Pre-amble*/ +/* +* OE Extension during Pre-amble +*/ #undef DDR_PHY_DX8SL1DXCTL2_PREOEX_DEFVAL #undef DDR_PHY_DX8SL1DXCTL2_PREOEX_SHIFT #undef DDR_PHY_DX8SL1DXCTL2_PREOEX_MASK -#define DDR_PHY_DX8SL1DXCTL2_PREOEX_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL1DXCTL2_PREOEX_SHIFT 18 -#define DDR_PHY_DX8SL1DXCTL2_PREOEX_MASK 0x000C0000U +#define DDR_PHY_DX8SL1DXCTL2_PREOEX_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_PREOEX_SHIFT 18 +#define DDR_PHY_DX8SL1DXCTL2_PREOEX_MASK 0x000C0000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_17_DEFVAL #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_17_SHIFT #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_17_MASK -#define DDR_PHY_DX8SL1DXCTL2_RESERVED_17_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL1DXCTL2_RESERVED_17_SHIFT 17 -#define DDR_PHY_DX8SL1DXCTL2_RESERVED_17_MASK 0x00020000U +#define DDR_PHY_DX8SL1DXCTL2_RESERVED_17_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_RESERVED_17_SHIFT 17 +#define DDR_PHY_DX8SL1DXCTL2_RESERVED_17_MASK 0x00020000U -/*I/O Assisted Gate Select*/ +/* +* I/O Assisted Gate Select +*/ #undef DDR_PHY_DX8SL1DXCTL2_IOAG_DEFVAL #undef DDR_PHY_DX8SL1DXCTL2_IOAG_SHIFT #undef DDR_PHY_DX8SL1DXCTL2_IOAG_MASK -#define DDR_PHY_DX8SL1DXCTL2_IOAG_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL1DXCTL2_IOAG_SHIFT 16 -#define DDR_PHY_DX8SL1DXCTL2_IOAG_MASK 0x00010000U +#define DDR_PHY_DX8SL1DXCTL2_IOAG_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_IOAG_SHIFT 16 +#define DDR_PHY_DX8SL1DXCTL2_IOAG_MASK 0x00010000U -/*I/O Loopback Select*/ +/* +* I/O Loopback Select +*/ #undef DDR_PHY_DX8SL1DXCTL2_IOLB_DEFVAL #undef DDR_PHY_DX8SL1DXCTL2_IOLB_SHIFT #undef DDR_PHY_DX8SL1DXCTL2_IOLB_MASK -#define DDR_PHY_DX8SL1DXCTL2_IOLB_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL1DXCTL2_IOLB_SHIFT 15 -#define DDR_PHY_DX8SL1DXCTL2_IOLB_MASK 0x00008000U +#define DDR_PHY_DX8SL1DXCTL2_IOLB_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_IOLB_SHIFT 15 +#define DDR_PHY_DX8SL1DXCTL2_IOLB_MASK 0x00008000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_DEFVAL #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_SHIFT #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_MASK -#define DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_SHIFT 13 -#define DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_MASK 0x00006000U +#define DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_SHIFT 13 +#define DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_MASK 0x00006000U -/*Low Power Wakeup Threshold*/ +/* +* Low Power Wakeup Threshold +*/ #undef DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_DEFVAL #undef DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_SHIFT #undef DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_MASK -#define DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_SHIFT 9 -#define DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_MASK 0x00001E00U +#define DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_SHIFT 9 +#define DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_MASK 0x00001E00U -/*Read Data Bus Inversion Enable*/ +/* +* Read Data Bus Inversion Enable +*/ #undef DDR_PHY_DX8SL1DXCTL2_RDBI_DEFVAL #undef DDR_PHY_DX8SL1DXCTL2_RDBI_SHIFT #undef DDR_PHY_DX8SL1DXCTL2_RDBI_MASK -#define DDR_PHY_DX8SL1DXCTL2_RDBI_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL1DXCTL2_RDBI_SHIFT 8 -#define DDR_PHY_DX8SL1DXCTL2_RDBI_MASK 0x00000100U +#define DDR_PHY_DX8SL1DXCTL2_RDBI_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_RDBI_SHIFT 8 +#define DDR_PHY_DX8SL1DXCTL2_RDBI_MASK 0x00000100U -/*Write Data Bus Inversion Enable*/ +/* +* Write Data Bus Inversion Enable +*/ #undef DDR_PHY_DX8SL1DXCTL2_WDBI_DEFVAL #undef DDR_PHY_DX8SL1DXCTL2_WDBI_SHIFT #undef DDR_PHY_DX8SL1DXCTL2_WDBI_MASK -#define DDR_PHY_DX8SL1DXCTL2_WDBI_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL1DXCTL2_WDBI_SHIFT 7 -#define DDR_PHY_DX8SL1DXCTL2_WDBI_MASK 0x00000080U +#define DDR_PHY_DX8SL1DXCTL2_WDBI_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_WDBI_SHIFT 7 +#define DDR_PHY_DX8SL1DXCTL2_WDBI_MASK 0x00000080U -/*PUB Read FIFO Bypass*/ +/* +* PUB Read FIFO Bypass +*/ #undef DDR_PHY_DX8SL1DXCTL2_PRFBYP_DEFVAL #undef DDR_PHY_DX8SL1DXCTL2_PRFBYP_SHIFT #undef DDR_PHY_DX8SL1DXCTL2_PRFBYP_MASK -#define DDR_PHY_DX8SL1DXCTL2_PRFBYP_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL1DXCTL2_PRFBYP_SHIFT 6 -#define DDR_PHY_DX8SL1DXCTL2_PRFBYP_MASK 0x00000040U +#define DDR_PHY_DX8SL1DXCTL2_PRFBYP_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_PRFBYP_SHIFT 6 +#define DDR_PHY_DX8SL1DXCTL2_PRFBYP_MASK 0x00000040U -/*DATX8 Receive FIFO Read Mode*/ +/* +* DATX8 Receive FIFO Read Mode +*/ #undef DDR_PHY_DX8SL1DXCTL2_RDMODE_DEFVAL #undef DDR_PHY_DX8SL1DXCTL2_RDMODE_SHIFT #undef DDR_PHY_DX8SL1DXCTL2_RDMODE_MASK -#define DDR_PHY_DX8SL1DXCTL2_RDMODE_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL1DXCTL2_RDMODE_SHIFT 4 -#define DDR_PHY_DX8SL1DXCTL2_RDMODE_MASK 0x00000030U +#define DDR_PHY_DX8SL1DXCTL2_RDMODE_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_RDMODE_SHIFT 4 +#define DDR_PHY_DX8SL1DXCTL2_RDMODE_MASK 0x00000030U -/*Disables the Read FIFO Reset*/ +/* +* Disables the Read FIFO Reset +*/ #undef DDR_PHY_DX8SL1DXCTL2_DISRST_DEFVAL #undef DDR_PHY_DX8SL1DXCTL2_DISRST_SHIFT #undef DDR_PHY_DX8SL1DXCTL2_DISRST_MASK -#define DDR_PHY_DX8SL1DXCTL2_DISRST_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL1DXCTL2_DISRST_SHIFT 3 -#define DDR_PHY_DX8SL1DXCTL2_DISRST_MASK 0x00000008U +#define DDR_PHY_DX8SL1DXCTL2_DISRST_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_DISRST_SHIFT 3 +#define DDR_PHY_DX8SL1DXCTL2_DISRST_MASK 0x00000008U -/*Read DQS Gate I/O Loopback*/ +/* +* Read DQS Gate I/O Loopback +*/ #undef DDR_PHY_DX8SL1DXCTL2_DQSGLB_DEFVAL #undef DDR_PHY_DX8SL1DXCTL2_DQSGLB_SHIFT #undef DDR_PHY_DX8SL1DXCTL2_DQSGLB_MASK -#define DDR_PHY_DX8SL1DXCTL2_DQSGLB_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL1DXCTL2_DQSGLB_SHIFT 1 -#define DDR_PHY_DX8SL1DXCTL2_DQSGLB_MASK 0x00000006U +#define DDR_PHY_DX8SL1DXCTL2_DQSGLB_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_DQSGLB_SHIFT 1 +#define DDR_PHY_DX8SL1DXCTL2_DQSGLB_MASK 0x00000006U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_0_DEFVAL #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_0_SHIFT #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_0_MASK -#define DDR_PHY_DX8SL1DXCTL2_RESERVED_0_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL1DXCTL2_RESERVED_0_SHIFT 0 -#define DDR_PHY_DX8SL1DXCTL2_RESERVED_0_MASK 0x00000001U +#define DDR_PHY_DX8SL1DXCTL2_RESERVED_0_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_RESERVED_0_SHIFT 0 +#define DDR_PHY_DX8SL1DXCTL2_RESERVED_0_MASK 0x00000001U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL1IOCR_RESERVED_31_DEFVAL #undef DDR_PHY_DX8SL1IOCR_RESERVED_31_SHIFT #undef DDR_PHY_DX8SL1IOCR_RESERVED_31_MASK -#define DDR_PHY_DX8SL1IOCR_RESERVED_31_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL1IOCR_RESERVED_31_SHIFT 31 -#define DDR_PHY_DX8SL1IOCR_RESERVED_31_MASK 0x80000000U +#define DDR_PHY_DX8SL1IOCR_RESERVED_31_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL1IOCR_RESERVED_31_SHIFT 31 +#define DDR_PHY_DX8SL1IOCR_RESERVED_31_MASK 0x80000000U -/*PVREF_DAC REFSEL range select*/ +/* +* PVREF_DAC REFSEL range select +*/ #undef DDR_PHY_DX8SL1IOCR_DXDACRANGE_DEFVAL #undef DDR_PHY_DX8SL1IOCR_DXDACRANGE_SHIFT #undef DDR_PHY_DX8SL1IOCR_DXDACRANGE_MASK -#define DDR_PHY_DX8SL1IOCR_DXDACRANGE_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL1IOCR_DXDACRANGE_SHIFT 28 -#define DDR_PHY_DX8SL1IOCR_DXDACRANGE_MASK 0x70000000U +#define DDR_PHY_DX8SL1IOCR_DXDACRANGE_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL1IOCR_DXDACRANGE_SHIFT 28 +#define DDR_PHY_DX8SL1IOCR_DXDACRANGE_MASK 0x70000000U -/*IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring*/ +/* +* IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring +*/ #undef DDR_PHY_DX8SL1IOCR_DXVREFIOM_DEFVAL #undef DDR_PHY_DX8SL1IOCR_DXVREFIOM_SHIFT #undef DDR_PHY_DX8SL1IOCR_DXVREFIOM_MASK -#define DDR_PHY_DX8SL1IOCR_DXVREFIOM_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL1IOCR_DXVREFIOM_SHIFT 25 -#define DDR_PHY_DX8SL1IOCR_DXVREFIOM_MASK 0x0E000000U +#define DDR_PHY_DX8SL1IOCR_DXVREFIOM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL1IOCR_DXVREFIOM_SHIFT 25 +#define DDR_PHY_DX8SL1IOCR_DXVREFIOM_MASK 0x0E000000U -/*DX IO Mode*/ +/* +* DX IO Mode +*/ #undef DDR_PHY_DX8SL1IOCR_DXIOM_DEFVAL #undef DDR_PHY_DX8SL1IOCR_DXIOM_SHIFT #undef DDR_PHY_DX8SL1IOCR_DXIOM_MASK -#define DDR_PHY_DX8SL1IOCR_DXIOM_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL1IOCR_DXIOM_SHIFT 22 -#define DDR_PHY_DX8SL1IOCR_DXIOM_MASK 0x01C00000U +#define DDR_PHY_DX8SL1IOCR_DXIOM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL1IOCR_DXIOM_SHIFT 22 +#define DDR_PHY_DX8SL1IOCR_DXIOM_MASK 0x01C00000U -/*DX IO Transmitter Mode*/ +/* +* DX IO Transmitter Mode +*/ #undef DDR_PHY_DX8SL1IOCR_DXTXM_DEFVAL #undef DDR_PHY_DX8SL1IOCR_DXTXM_SHIFT #undef DDR_PHY_DX8SL1IOCR_DXTXM_MASK -#define DDR_PHY_DX8SL1IOCR_DXTXM_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL1IOCR_DXTXM_SHIFT 11 -#define DDR_PHY_DX8SL1IOCR_DXTXM_MASK 0x003FF800U +#define DDR_PHY_DX8SL1IOCR_DXTXM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL1IOCR_DXTXM_SHIFT 11 +#define DDR_PHY_DX8SL1IOCR_DXTXM_MASK 0x003FF800U -/*DX IO Receiver Mode*/ +/* +* DX IO Receiver Mode +*/ #undef DDR_PHY_DX8SL1IOCR_DXRXM_DEFVAL #undef DDR_PHY_DX8SL1IOCR_DXRXM_SHIFT #undef DDR_PHY_DX8SL1IOCR_DXRXM_MASK -#define DDR_PHY_DX8SL1IOCR_DXRXM_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL1IOCR_DXRXM_SHIFT 0 -#define DDR_PHY_DX8SL1IOCR_DXRXM_MASK 0x000007FFU +#define DDR_PHY_DX8SL1IOCR_DXRXM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL1IOCR_DXRXM_SHIFT 0 +#define DDR_PHY_DX8SL1IOCR_DXRXM_MASK 0x000007FFU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL2OSC_RESERVED_31_30_DEFVAL #undef DDR_PHY_DX8SL2OSC_RESERVED_31_30_SHIFT #undef DDR_PHY_DX8SL2OSC_RESERVED_31_30_MASK -#define DDR_PHY_DX8SL2OSC_RESERVED_31_30_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL2OSC_RESERVED_31_30_SHIFT 30 -#define DDR_PHY_DX8SL2OSC_RESERVED_31_30_MASK 0xC0000000U +#define DDR_PHY_DX8SL2OSC_RESERVED_31_30_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX8SL2OSC_RESERVED_31_30_MASK 0xC0000000U -/*Enable Clock Gating for DX ddr_clk*/ +/* +* Enable Clock Gating for DX ddr_clk +*/ #undef DDR_PHY_DX8SL2OSC_GATEDXRDCLK_DEFVAL #undef DDR_PHY_DX8SL2OSC_GATEDXRDCLK_SHIFT #undef DDR_PHY_DX8SL2OSC_GATEDXRDCLK_MASK -#define DDR_PHY_DX8SL2OSC_GATEDXRDCLK_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL2OSC_GATEDXRDCLK_SHIFT 28 -#define DDR_PHY_DX8SL2OSC_GATEDXRDCLK_MASK 0x30000000U +#define DDR_PHY_DX8SL2OSC_GATEDXRDCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_GATEDXRDCLK_SHIFT 28 +#define DDR_PHY_DX8SL2OSC_GATEDXRDCLK_MASK 0x30000000U -/*Enable Clock Gating for DX ctl_rd_clk*/ +/* +* Enable Clock Gating for DX ctl_rd_clk +*/ #undef DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_DEFVAL #undef DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_SHIFT #undef DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_MASK -#define DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_SHIFT 26 -#define DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_MASK 0x0C000000U +#define DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_SHIFT 26 +#define DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_MASK 0x0C000000U -/*Enable Clock Gating for DX ctl_clk*/ +/* +* Enable Clock Gating for DX ctl_clk +*/ #undef DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_DEFVAL #undef DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_SHIFT #undef DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_MASK -#define DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_SHIFT 24 -#define DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_MASK 0x03000000U +#define DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_SHIFT 24 +#define DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_MASK 0x03000000U -/*Selects the level to which clocks will be stalled when clock gating is enabled.*/ +/* +* Selects the level to which clocks will be stalled when clock gating is e + * nabled. +*/ #undef DDR_PHY_DX8SL2OSC_CLKLEVEL_DEFVAL #undef DDR_PHY_DX8SL2OSC_CLKLEVEL_SHIFT #undef DDR_PHY_DX8SL2OSC_CLKLEVEL_MASK -#define DDR_PHY_DX8SL2OSC_CLKLEVEL_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL2OSC_CLKLEVEL_SHIFT 22 -#define DDR_PHY_DX8SL2OSC_CLKLEVEL_MASK 0x00C00000U +#define DDR_PHY_DX8SL2OSC_CLKLEVEL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_CLKLEVEL_SHIFT 22 +#define DDR_PHY_DX8SL2OSC_CLKLEVEL_MASK 0x00C00000U -/*Loopback Mode*/ +/* +* Loopback Mode +*/ #undef DDR_PHY_DX8SL2OSC_LBMODE_DEFVAL #undef DDR_PHY_DX8SL2OSC_LBMODE_SHIFT #undef DDR_PHY_DX8SL2OSC_LBMODE_MASK -#define DDR_PHY_DX8SL2OSC_LBMODE_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL2OSC_LBMODE_SHIFT 21 -#define DDR_PHY_DX8SL2OSC_LBMODE_MASK 0x00200000U +#define DDR_PHY_DX8SL2OSC_LBMODE_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_LBMODE_SHIFT 21 +#define DDR_PHY_DX8SL2OSC_LBMODE_MASK 0x00200000U -/*Load GSDQS LCDL with 2x the calibrated GSDQSPRD value*/ +/* +* Load GSDQS LCDL with 2x the calibrated GSDQSPRD value +*/ #undef DDR_PHY_DX8SL2OSC_LBGSDQS_DEFVAL #undef DDR_PHY_DX8SL2OSC_LBGSDQS_SHIFT #undef DDR_PHY_DX8SL2OSC_LBGSDQS_MASK -#define DDR_PHY_DX8SL2OSC_LBGSDQS_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL2OSC_LBGSDQS_SHIFT 20 -#define DDR_PHY_DX8SL2OSC_LBGSDQS_MASK 0x00100000U +#define DDR_PHY_DX8SL2OSC_LBGSDQS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_LBGSDQS_SHIFT 20 +#define DDR_PHY_DX8SL2OSC_LBGSDQS_MASK 0x00100000U -/*Loopback DQS Gating*/ +/* +* Loopback DQS Gating +*/ #undef DDR_PHY_DX8SL2OSC_LBGDQS_DEFVAL #undef DDR_PHY_DX8SL2OSC_LBGDQS_SHIFT #undef DDR_PHY_DX8SL2OSC_LBGDQS_MASK -#define DDR_PHY_DX8SL2OSC_LBGDQS_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL2OSC_LBGDQS_SHIFT 18 -#define DDR_PHY_DX8SL2OSC_LBGDQS_MASK 0x000C0000U +#define DDR_PHY_DX8SL2OSC_LBGDQS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_LBGDQS_SHIFT 18 +#define DDR_PHY_DX8SL2OSC_LBGDQS_MASK 0x000C0000U -/*Loopback DQS Shift*/ +/* +* Loopback DQS Shift +*/ #undef DDR_PHY_DX8SL2OSC_LBDQSS_DEFVAL #undef DDR_PHY_DX8SL2OSC_LBDQSS_SHIFT #undef DDR_PHY_DX8SL2OSC_LBDQSS_MASK -#define DDR_PHY_DX8SL2OSC_LBDQSS_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL2OSC_LBDQSS_SHIFT 17 -#define DDR_PHY_DX8SL2OSC_LBDQSS_MASK 0x00020000U +#define DDR_PHY_DX8SL2OSC_LBDQSS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_LBDQSS_SHIFT 17 +#define DDR_PHY_DX8SL2OSC_LBDQSS_MASK 0x00020000U -/*PHY High-Speed Reset*/ +/* +* PHY High-Speed Reset +*/ #undef DDR_PHY_DX8SL2OSC_PHYHRST_DEFVAL #undef DDR_PHY_DX8SL2OSC_PHYHRST_SHIFT #undef DDR_PHY_DX8SL2OSC_PHYHRST_MASK -#define DDR_PHY_DX8SL2OSC_PHYHRST_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL2OSC_PHYHRST_SHIFT 16 -#define DDR_PHY_DX8SL2OSC_PHYHRST_MASK 0x00010000U +#define DDR_PHY_DX8SL2OSC_PHYHRST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_PHYHRST_SHIFT 16 +#define DDR_PHY_DX8SL2OSC_PHYHRST_MASK 0x00010000U -/*PHY FIFO Reset*/ +/* +* PHY FIFO Reset +*/ #undef DDR_PHY_DX8SL2OSC_PHYFRST_DEFVAL #undef DDR_PHY_DX8SL2OSC_PHYFRST_SHIFT #undef DDR_PHY_DX8SL2OSC_PHYFRST_MASK -#define DDR_PHY_DX8SL2OSC_PHYFRST_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL2OSC_PHYFRST_SHIFT 15 -#define DDR_PHY_DX8SL2OSC_PHYFRST_MASK 0x00008000U +#define DDR_PHY_DX8SL2OSC_PHYFRST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_PHYFRST_SHIFT 15 +#define DDR_PHY_DX8SL2OSC_PHYFRST_MASK 0x00008000U -/*Delay Line Test Start*/ +/* +* Delay Line Test Start +*/ #undef DDR_PHY_DX8SL2OSC_DLTST_DEFVAL #undef DDR_PHY_DX8SL2OSC_DLTST_SHIFT #undef DDR_PHY_DX8SL2OSC_DLTST_MASK -#define DDR_PHY_DX8SL2OSC_DLTST_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL2OSC_DLTST_SHIFT 14 -#define DDR_PHY_DX8SL2OSC_DLTST_MASK 0x00004000U +#define DDR_PHY_DX8SL2OSC_DLTST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_DLTST_SHIFT 14 +#define DDR_PHY_DX8SL2OSC_DLTST_MASK 0x00004000U -/*Delay Line Test Mode*/ +/* +* Delay Line Test Mode +*/ #undef DDR_PHY_DX8SL2OSC_DLTMODE_DEFVAL #undef DDR_PHY_DX8SL2OSC_DLTMODE_SHIFT #undef DDR_PHY_DX8SL2OSC_DLTMODE_MASK -#define DDR_PHY_DX8SL2OSC_DLTMODE_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL2OSC_DLTMODE_SHIFT 13 -#define DDR_PHY_DX8SL2OSC_DLTMODE_MASK 0x00002000U +#define DDR_PHY_DX8SL2OSC_DLTMODE_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_DLTMODE_SHIFT 13 +#define DDR_PHY_DX8SL2OSC_DLTMODE_MASK 0x00002000U -/*Reserved. Caution, do not write to this register field.*/ +/* +* Reserved. Caution, do not write to this register field. +*/ #undef DDR_PHY_DX8SL2OSC_RESERVED_12_11_DEFVAL #undef DDR_PHY_DX8SL2OSC_RESERVED_12_11_SHIFT #undef DDR_PHY_DX8SL2OSC_RESERVED_12_11_MASK -#define DDR_PHY_DX8SL2OSC_RESERVED_12_11_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL2OSC_RESERVED_12_11_SHIFT 11 -#define DDR_PHY_DX8SL2OSC_RESERVED_12_11_MASK 0x00001800U +#define DDR_PHY_DX8SL2OSC_RESERVED_12_11_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_RESERVED_12_11_SHIFT 11 +#define DDR_PHY_DX8SL2OSC_RESERVED_12_11_MASK 0x00001800U -/*Oscillator Mode Write-Data Delay Line Select*/ +/* +* Oscillator Mode Write-Data Delay Line Select +*/ #undef DDR_PHY_DX8SL2OSC_OSCWDDL_DEFVAL #undef DDR_PHY_DX8SL2OSC_OSCWDDL_SHIFT #undef DDR_PHY_DX8SL2OSC_OSCWDDL_MASK -#define DDR_PHY_DX8SL2OSC_OSCWDDL_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL2OSC_OSCWDDL_SHIFT 9 -#define DDR_PHY_DX8SL2OSC_OSCWDDL_MASK 0x00000600U +#define DDR_PHY_DX8SL2OSC_OSCWDDL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_OSCWDDL_SHIFT 9 +#define DDR_PHY_DX8SL2OSC_OSCWDDL_MASK 0x00000600U -/*Reserved. Caution, do not write to this register field.*/ +/* +* Reserved. Caution, do not write to this register field. +*/ #undef DDR_PHY_DX8SL2OSC_RESERVED_8_7_DEFVAL #undef DDR_PHY_DX8SL2OSC_RESERVED_8_7_SHIFT #undef DDR_PHY_DX8SL2OSC_RESERVED_8_7_MASK -#define DDR_PHY_DX8SL2OSC_RESERVED_8_7_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL2OSC_RESERVED_8_7_SHIFT 7 -#define DDR_PHY_DX8SL2OSC_RESERVED_8_7_MASK 0x00000180U +#define DDR_PHY_DX8SL2OSC_RESERVED_8_7_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_RESERVED_8_7_SHIFT 7 +#define DDR_PHY_DX8SL2OSC_RESERVED_8_7_MASK 0x00000180U -/*Oscillator Mode Write-Leveling Delay Line Select*/ +/* +* Oscillator Mode Write-Leveling Delay Line Select +*/ #undef DDR_PHY_DX8SL2OSC_OSCWDL_DEFVAL #undef DDR_PHY_DX8SL2OSC_OSCWDL_SHIFT #undef DDR_PHY_DX8SL2OSC_OSCWDL_MASK -#define DDR_PHY_DX8SL2OSC_OSCWDL_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL2OSC_OSCWDL_SHIFT 5 -#define DDR_PHY_DX8SL2OSC_OSCWDL_MASK 0x00000060U +#define DDR_PHY_DX8SL2OSC_OSCWDL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_OSCWDL_SHIFT 5 +#define DDR_PHY_DX8SL2OSC_OSCWDL_MASK 0x00000060U -/*Oscillator Mode Division*/ +/* +* Oscillator Mode Division +*/ #undef DDR_PHY_DX8SL2OSC_OSCDIV_DEFVAL #undef DDR_PHY_DX8SL2OSC_OSCDIV_SHIFT #undef DDR_PHY_DX8SL2OSC_OSCDIV_MASK -#define DDR_PHY_DX8SL2OSC_OSCDIV_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL2OSC_OSCDIV_SHIFT 1 -#define DDR_PHY_DX8SL2OSC_OSCDIV_MASK 0x0000001EU +#define DDR_PHY_DX8SL2OSC_OSCDIV_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_OSCDIV_SHIFT 1 +#define DDR_PHY_DX8SL2OSC_OSCDIV_MASK 0x0000001EU -/*Oscillator Enable*/ +/* +* Oscillator Enable +*/ #undef DDR_PHY_DX8SL2OSC_OSCEN_DEFVAL #undef DDR_PHY_DX8SL2OSC_OSCEN_SHIFT #undef DDR_PHY_DX8SL2OSC_OSCEN_MASK -#define DDR_PHY_DX8SL2OSC_OSCEN_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL2OSC_OSCEN_SHIFT 0 -#define DDR_PHY_DX8SL2OSC_OSCEN_MASK 0x00000001U +#define DDR_PHY_DX8SL2OSC_OSCEN_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_OSCEN_SHIFT 0 +#define DDR_PHY_DX8SL2OSC_OSCEN_MASK 0x00000001U -/*Reserved. Return zeroes on reads.*/ +/* +* PLL Bypass +*/ +#undef DDR_PHY_DX8SL2PLLCR0_PLLBYP_DEFVAL +#undef DDR_PHY_DX8SL2PLLCR0_PLLBYP_SHIFT +#undef DDR_PHY_DX8SL2PLLCR0_PLLBYP_MASK +#define DDR_PHY_DX8SL2PLLCR0_PLLBYP_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL2PLLCR0_PLLBYP_SHIFT 31 +#define DDR_PHY_DX8SL2PLLCR0_PLLBYP_MASK 0x80000000U + +/* +* PLL Reset +*/ +#undef DDR_PHY_DX8SL2PLLCR0_PLLRST_DEFVAL +#undef DDR_PHY_DX8SL2PLLCR0_PLLRST_SHIFT +#undef DDR_PHY_DX8SL2PLLCR0_PLLRST_MASK +#define DDR_PHY_DX8SL2PLLCR0_PLLRST_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL2PLLCR0_PLLRST_SHIFT 30 +#define DDR_PHY_DX8SL2PLLCR0_PLLRST_MASK 0x40000000U + +/* +* PLL Power Down +*/ +#undef DDR_PHY_DX8SL2PLLCR0_PLLPD_DEFVAL +#undef DDR_PHY_DX8SL2PLLCR0_PLLPD_SHIFT +#undef DDR_PHY_DX8SL2PLLCR0_PLLPD_MASK +#define DDR_PHY_DX8SL2PLLCR0_PLLPD_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL2PLLCR0_PLLPD_SHIFT 29 +#define DDR_PHY_DX8SL2PLLCR0_PLLPD_MASK 0x20000000U + +/* +* Reference Stop Mode +*/ +#undef DDR_PHY_DX8SL2PLLCR0_RSTOPM_DEFVAL +#undef DDR_PHY_DX8SL2PLLCR0_RSTOPM_SHIFT +#undef DDR_PHY_DX8SL2PLLCR0_RSTOPM_MASK +#define DDR_PHY_DX8SL2PLLCR0_RSTOPM_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL2PLLCR0_RSTOPM_SHIFT 28 +#define DDR_PHY_DX8SL2PLLCR0_RSTOPM_MASK 0x10000000U + +/* +* PLL Frequency Select +*/ +#undef DDR_PHY_DX8SL2PLLCR0_FRQSEL_DEFVAL +#undef DDR_PHY_DX8SL2PLLCR0_FRQSEL_SHIFT +#undef DDR_PHY_DX8SL2PLLCR0_FRQSEL_MASK +#define DDR_PHY_DX8SL2PLLCR0_FRQSEL_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL2PLLCR0_FRQSEL_SHIFT 24 +#define DDR_PHY_DX8SL2PLLCR0_FRQSEL_MASK 0x0F000000U + +/* +* Relock Mode +*/ +#undef DDR_PHY_DX8SL2PLLCR0_RLOCKM_DEFVAL +#undef DDR_PHY_DX8SL2PLLCR0_RLOCKM_SHIFT +#undef DDR_PHY_DX8SL2PLLCR0_RLOCKM_MASK +#define DDR_PHY_DX8SL2PLLCR0_RLOCKM_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL2PLLCR0_RLOCKM_SHIFT 23 +#define DDR_PHY_DX8SL2PLLCR0_RLOCKM_MASK 0x00800000U + +/* +* Charge Pump Proportional Current Control +*/ +#undef DDR_PHY_DX8SL2PLLCR0_CPPC_DEFVAL +#undef DDR_PHY_DX8SL2PLLCR0_CPPC_SHIFT +#undef DDR_PHY_DX8SL2PLLCR0_CPPC_MASK +#define DDR_PHY_DX8SL2PLLCR0_CPPC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL2PLLCR0_CPPC_SHIFT 17 +#define DDR_PHY_DX8SL2PLLCR0_CPPC_MASK 0x007E0000U + +/* +* Charge Pump Integrating Current Control +*/ +#undef DDR_PHY_DX8SL2PLLCR0_CPIC_DEFVAL +#undef DDR_PHY_DX8SL2PLLCR0_CPIC_SHIFT +#undef DDR_PHY_DX8SL2PLLCR0_CPIC_MASK +#define DDR_PHY_DX8SL2PLLCR0_CPIC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL2PLLCR0_CPIC_SHIFT 13 +#define DDR_PHY_DX8SL2PLLCR0_CPIC_MASK 0x0001E000U + +/* +* Gear Shift +*/ +#undef DDR_PHY_DX8SL2PLLCR0_GSHIFT_DEFVAL +#undef DDR_PHY_DX8SL2PLLCR0_GSHIFT_SHIFT +#undef DDR_PHY_DX8SL2PLLCR0_GSHIFT_MASK +#define DDR_PHY_DX8SL2PLLCR0_GSHIFT_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL2PLLCR0_GSHIFT_SHIFT 12 +#define DDR_PHY_DX8SL2PLLCR0_GSHIFT_MASK 0x00001000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL2PLLCR0_RESERVED_11_9_DEFVAL +#undef DDR_PHY_DX8SL2PLLCR0_RESERVED_11_9_SHIFT +#undef DDR_PHY_DX8SL2PLLCR0_RESERVED_11_9_MASK +#define DDR_PHY_DX8SL2PLLCR0_RESERVED_11_9_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL2PLLCR0_RESERVED_11_9_SHIFT 9 +#define DDR_PHY_DX8SL2PLLCR0_RESERVED_11_9_MASK 0x00000E00U + +/* +* Analog Test Enable (ATOEN) +*/ +#undef DDR_PHY_DX8SL2PLLCR0_ATOEN_DEFVAL +#undef DDR_PHY_DX8SL2PLLCR0_ATOEN_SHIFT +#undef DDR_PHY_DX8SL2PLLCR0_ATOEN_MASK +#define DDR_PHY_DX8SL2PLLCR0_ATOEN_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL2PLLCR0_ATOEN_SHIFT 8 +#define DDR_PHY_DX8SL2PLLCR0_ATOEN_MASK 0x00000100U + +/* +* Analog Test Control +*/ +#undef DDR_PHY_DX8SL2PLLCR0_ATC_DEFVAL +#undef DDR_PHY_DX8SL2PLLCR0_ATC_SHIFT +#undef DDR_PHY_DX8SL2PLLCR0_ATC_MASK +#define DDR_PHY_DX8SL2PLLCR0_ATC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL2PLLCR0_ATC_SHIFT 4 +#define DDR_PHY_DX8SL2PLLCR0_ATC_MASK 0x000000F0U + +/* +* Digital Test Control +*/ +#undef DDR_PHY_DX8SL2PLLCR0_DTC_DEFVAL +#undef DDR_PHY_DX8SL2PLLCR0_DTC_SHIFT +#undef DDR_PHY_DX8SL2PLLCR0_DTC_MASK +#define DDR_PHY_DX8SL2PLLCR0_DTC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL2PLLCR0_DTC_SHIFT 0 +#define DDR_PHY_DX8SL2PLLCR0_DTC_MASK 0x0000000FU + +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_DEFVAL #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_SHIFT #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_MASK -#define DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_SHIFT 25 -#define DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_MASK 0xFE000000U +#define DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_SHIFT 25 +#define DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_MASK 0xFE000000U -/*Read Path Rise-to-Rise Mode*/ +/* +* Read Path Rise-to-Rise Mode +*/ #undef DDR_PHY_DX8SL2DQSCTL_RRRMODE_DEFVAL #undef DDR_PHY_DX8SL2DQSCTL_RRRMODE_SHIFT #undef DDR_PHY_DX8SL2DQSCTL_RRRMODE_MASK -#define DDR_PHY_DX8SL2DQSCTL_RRRMODE_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL2DQSCTL_RRRMODE_SHIFT 24 -#define DDR_PHY_DX8SL2DQSCTL_RRRMODE_MASK 0x01000000U +#define DDR_PHY_DX8SL2DQSCTL_RRRMODE_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL2DQSCTL_RRRMODE_SHIFT 24 +#define DDR_PHY_DX8SL2DQSCTL_RRRMODE_MASK 0x01000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_DEFVAL #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_SHIFT #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_MASK -#define DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_SHIFT 22 -#define DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_MASK 0x00C00000U +#define DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_MASK 0x00C00000U -/*Write Path Rise-to-Rise Mode*/ +/* +* Write Path Rise-to-Rise Mode +*/ #undef DDR_PHY_DX8SL2DQSCTL_WRRMODE_DEFVAL #undef DDR_PHY_DX8SL2DQSCTL_WRRMODE_SHIFT #undef DDR_PHY_DX8SL2DQSCTL_WRRMODE_MASK -#define DDR_PHY_DX8SL2DQSCTL_WRRMODE_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL2DQSCTL_WRRMODE_SHIFT 21 -#define DDR_PHY_DX8SL2DQSCTL_WRRMODE_MASK 0x00200000U +#define DDR_PHY_DX8SL2DQSCTL_WRRMODE_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL2DQSCTL_WRRMODE_SHIFT 21 +#define DDR_PHY_DX8SL2DQSCTL_WRRMODE_MASK 0x00200000U -/*DQS Gate Extension*/ +/* +* DQS Gate Extension +*/ #undef DDR_PHY_DX8SL2DQSCTL_DQSGX_DEFVAL #undef DDR_PHY_DX8SL2DQSCTL_DQSGX_SHIFT #undef DDR_PHY_DX8SL2DQSCTL_DQSGX_MASK -#define DDR_PHY_DX8SL2DQSCTL_DQSGX_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL2DQSCTL_DQSGX_SHIFT 19 -#define DDR_PHY_DX8SL2DQSCTL_DQSGX_MASK 0x00180000U +#define DDR_PHY_DX8SL2DQSCTL_DQSGX_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL2DQSCTL_DQSGX_SHIFT 19 +#define DDR_PHY_DX8SL2DQSCTL_DQSGX_MASK 0x00180000U -/*Low Power PLL Power Down*/ +/* +* Low Power PLL Power Down +*/ #undef DDR_PHY_DX8SL2DQSCTL_LPPLLPD_DEFVAL #undef DDR_PHY_DX8SL2DQSCTL_LPPLLPD_SHIFT #undef DDR_PHY_DX8SL2DQSCTL_LPPLLPD_MASK -#define DDR_PHY_DX8SL2DQSCTL_LPPLLPD_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL2DQSCTL_LPPLLPD_SHIFT 18 -#define DDR_PHY_DX8SL2DQSCTL_LPPLLPD_MASK 0x00040000U +#define DDR_PHY_DX8SL2DQSCTL_LPPLLPD_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL2DQSCTL_LPPLLPD_SHIFT 18 +#define DDR_PHY_DX8SL2DQSCTL_LPPLLPD_MASK 0x00040000U -/*Low Power I/O Power Down*/ +/* +* Low Power I/O Power Down +*/ #undef DDR_PHY_DX8SL2DQSCTL_LPIOPD_DEFVAL #undef DDR_PHY_DX8SL2DQSCTL_LPIOPD_SHIFT #undef DDR_PHY_DX8SL2DQSCTL_LPIOPD_MASK -#define DDR_PHY_DX8SL2DQSCTL_LPIOPD_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL2DQSCTL_LPIOPD_SHIFT 17 -#define DDR_PHY_DX8SL2DQSCTL_LPIOPD_MASK 0x00020000U +#define DDR_PHY_DX8SL2DQSCTL_LPIOPD_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL2DQSCTL_LPIOPD_SHIFT 17 +#define DDR_PHY_DX8SL2DQSCTL_LPIOPD_MASK 0x00020000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_DEFVAL #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_SHIFT #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_MASK -#define DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_SHIFT 15 -#define DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_MASK 0x00018000U +#define DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_SHIFT 15 +#define DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_MASK 0x00018000U -/*QS Counter Enable*/ +/* +* QS Counter Enable +*/ #undef DDR_PHY_DX8SL2DQSCTL_QSCNTEN_DEFVAL #undef DDR_PHY_DX8SL2DQSCTL_QSCNTEN_SHIFT #undef DDR_PHY_DX8SL2DQSCTL_QSCNTEN_MASK -#define DDR_PHY_DX8SL2DQSCTL_QSCNTEN_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL2DQSCTL_QSCNTEN_SHIFT 14 -#define DDR_PHY_DX8SL2DQSCTL_QSCNTEN_MASK 0x00004000U +#define DDR_PHY_DX8SL2DQSCTL_QSCNTEN_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL2DQSCTL_QSCNTEN_SHIFT 14 +#define DDR_PHY_DX8SL2DQSCTL_QSCNTEN_MASK 0x00004000U -/*Unused DQ I/O Mode*/ +/* +* Unused DQ I/O Mode +*/ #undef DDR_PHY_DX8SL2DQSCTL_UDQIOM_DEFVAL #undef DDR_PHY_DX8SL2DQSCTL_UDQIOM_SHIFT #undef DDR_PHY_DX8SL2DQSCTL_UDQIOM_MASK -#define DDR_PHY_DX8SL2DQSCTL_UDQIOM_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL2DQSCTL_UDQIOM_SHIFT 13 -#define DDR_PHY_DX8SL2DQSCTL_UDQIOM_MASK 0x00002000U +#define DDR_PHY_DX8SL2DQSCTL_UDQIOM_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL2DQSCTL_UDQIOM_SHIFT 13 +#define DDR_PHY_DX8SL2DQSCTL_UDQIOM_MASK 0x00002000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_DEFVAL #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_SHIFT #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_MASK -#define DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_SHIFT 10 -#define DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_MASK 0x00001C00U +#define DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_SHIFT 10 +#define DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_MASK 0x00001C00U -/*Data Slew Rate*/ +/* +* Data Slew Rate +*/ #undef DDR_PHY_DX8SL2DQSCTL_DXSR_DEFVAL #undef DDR_PHY_DX8SL2DQSCTL_DXSR_SHIFT #undef DDR_PHY_DX8SL2DQSCTL_DXSR_MASK -#define DDR_PHY_DX8SL2DQSCTL_DXSR_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL2DQSCTL_DXSR_SHIFT 8 -#define DDR_PHY_DX8SL2DQSCTL_DXSR_MASK 0x00000300U +#define DDR_PHY_DX8SL2DQSCTL_DXSR_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL2DQSCTL_DXSR_SHIFT 8 +#define DDR_PHY_DX8SL2DQSCTL_DXSR_MASK 0x00000300U -/*DQS_N Resistor*/ +/* +* DQS_N Resistor +*/ #undef DDR_PHY_DX8SL2DQSCTL_DQSNRES_DEFVAL #undef DDR_PHY_DX8SL2DQSCTL_DQSNRES_SHIFT #undef DDR_PHY_DX8SL2DQSCTL_DQSNRES_MASK -#define DDR_PHY_DX8SL2DQSCTL_DQSNRES_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL2DQSCTL_DQSNRES_SHIFT 4 -#define DDR_PHY_DX8SL2DQSCTL_DQSNRES_MASK 0x000000F0U +#define DDR_PHY_DX8SL2DQSCTL_DQSNRES_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL2DQSCTL_DQSNRES_SHIFT 4 +#define DDR_PHY_DX8SL2DQSCTL_DQSNRES_MASK 0x000000F0U -/*DQS Resistor*/ +/* +* DQS Resistor +*/ #undef DDR_PHY_DX8SL2DQSCTL_DQSRES_DEFVAL #undef DDR_PHY_DX8SL2DQSCTL_DQSRES_SHIFT #undef DDR_PHY_DX8SL2DQSCTL_DQSRES_MASK -#define DDR_PHY_DX8SL2DQSCTL_DQSRES_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL2DQSCTL_DQSRES_SHIFT 0 -#define DDR_PHY_DX8SL2DQSCTL_DQSRES_MASK 0x0000000FU +#define DDR_PHY_DX8SL2DQSCTL_DQSRES_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL2DQSCTL_DQSRES_SHIFT 0 +#define DDR_PHY_DX8SL2DQSCTL_DQSRES_MASK 0x0000000FU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_DEFVAL #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_SHIFT #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_MASK -#define DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_SHIFT 24 -#define DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_MASK 0xFF000000U +#define DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_SHIFT 24 +#define DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_MASK 0xFF000000U -/*Configurable Read Data Enable*/ +/* +* Configurable Read Data Enable +*/ #undef DDR_PHY_DX8SL2DXCTL2_CRDEN_DEFVAL #undef DDR_PHY_DX8SL2DXCTL2_CRDEN_SHIFT #undef DDR_PHY_DX8SL2DXCTL2_CRDEN_MASK -#define DDR_PHY_DX8SL2DXCTL2_CRDEN_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL2DXCTL2_CRDEN_SHIFT 23 -#define DDR_PHY_DX8SL2DXCTL2_CRDEN_MASK 0x00800000U +#define DDR_PHY_DX8SL2DXCTL2_CRDEN_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_CRDEN_SHIFT 23 +#define DDR_PHY_DX8SL2DXCTL2_CRDEN_MASK 0x00800000U -/*OX Extension during Post-amble*/ +/* +* OX Extension during Post-amble +*/ #undef DDR_PHY_DX8SL2DXCTL2_POSOEX_DEFVAL #undef DDR_PHY_DX8SL2DXCTL2_POSOEX_SHIFT #undef DDR_PHY_DX8SL2DXCTL2_POSOEX_MASK -#define DDR_PHY_DX8SL2DXCTL2_POSOEX_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL2DXCTL2_POSOEX_SHIFT 20 -#define DDR_PHY_DX8SL2DXCTL2_POSOEX_MASK 0x00700000U +#define DDR_PHY_DX8SL2DXCTL2_POSOEX_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_POSOEX_SHIFT 20 +#define DDR_PHY_DX8SL2DXCTL2_POSOEX_MASK 0x00700000U -/*OE Extension during Pre-amble*/ +/* +* OE Extension during Pre-amble +*/ #undef DDR_PHY_DX8SL2DXCTL2_PREOEX_DEFVAL #undef DDR_PHY_DX8SL2DXCTL2_PREOEX_SHIFT #undef DDR_PHY_DX8SL2DXCTL2_PREOEX_MASK -#define DDR_PHY_DX8SL2DXCTL2_PREOEX_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL2DXCTL2_PREOEX_SHIFT 18 -#define DDR_PHY_DX8SL2DXCTL2_PREOEX_MASK 0x000C0000U +#define DDR_PHY_DX8SL2DXCTL2_PREOEX_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_PREOEX_SHIFT 18 +#define DDR_PHY_DX8SL2DXCTL2_PREOEX_MASK 0x000C0000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_17_DEFVAL #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_17_SHIFT #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_17_MASK -#define DDR_PHY_DX8SL2DXCTL2_RESERVED_17_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL2DXCTL2_RESERVED_17_SHIFT 17 -#define DDR_PHY_DX8SL2DXCTL2_RESERVED_17_MASK 0x00020000U +#define DDR_PHY_DX8SL2DXCTL2_RESERVED_17_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_RESERVED_17_SHIFT 17 +#define DDR_PHY_DX8SL2DXCTL2_RESERVED_17_MASK 0x00020000U -/*I/O Assisted Gate Select*/ +/* +* I/O Assisted Gate Select +*/ #undef DDR_PHY_DX8SL2DXCTL2_IOAG_DEFVAL #undef DDR_PHY_DX8SL2DXCTL2_IOAG_SHIFT #undef DDR_PHY_DX8SL2DXCTL2_IOAG_MASK -#define DDR_PHY_DX8SL2DXCTL2_IOAG_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL2DXCTL2_IOAG_SHIFT 16 -#define DDR_PHY_DX8SL2DXCTL2_IOAG_MASK 0x00010000U +#define DDR_PHY_DX8SL2DXCTL2_IOAG_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_IOAG_SHIFT 16 +#define DDR_PHY_DX8SL2DXCTL2_IOAG_MASK 0x00010000U -/*I/O Loopback Select*/ +/* +* I/O Loopback Select +*/ #undef DDR_PHY_DX8SL2DXCTL2_IOLB_DEFVAL #undef DDR_PHY_DX8SL2DXCTL2_IOLB_SHIFT #undef DDR_PHY_DX8SL2DXCTL2_IOLB_MASK -#define DDR_PHY_DX8SL2DXCTL2_IOLB_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL2DXCTL2_IOLB_SHIFT 15 -#define DDR_PHY_DX8SL2DXCTL2_IOLB_MASK 0x00008000U +#define DDR_PHY_DX8SL2DXCTL2_IOLB_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_IOLB_SHIFT 15 +#define DDR_PHY_DX8SL2DXCTL2_IOLB_MASK 0x00008000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_DEFVAL #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_SHIFT #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_MASK -#define DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_SHIFT 13 -#define DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_MASK 0x00006000U +#define DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_SHIFT 13 +#define DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_MASK 0x00006000U -/*Low Power Wakeup Threshold*/ +/* +* Low Power Wakeup Threshold +*/ #undef DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_DEFVAL #undef DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_SHIFT #undef DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_MASK -#define DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_SHIFT 9 -#define DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_MASK 0x00001E00U +#define DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_SHIFT 9 +#define DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_MASK 0x00001E00U -/*Read Data Bus Inversion Enable*/ +/* +* Read Data Bus Inversion Enable +*/ #undef DDR_PHY_DX8SL2DXCTL2_RDBI_DEFVAL #undef DDR_PHY_DX8SL2DXCTL2_RDBI_SHIFT #undef DDR_PHY_DX8SL2DXCTL2_RDBI_MASK -#define DDR_PHY_DX8SL2DXCTL2_RDBI_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL2DXCTL2_RDBI_SHIFT 8 -#define DDR_PHY_DX8SL2DXCTL2_RDBI_MASK 0x00000100U +#define DDR_PHY_DX8SL2DXCTL2_RDBI_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_RDBI_SHIFT 8 +#define DDR_PHY_DX8SL2DXCTL2_RDBI_MASK 0x00000100U -/*Write Data Bus Inversion Enable*/ +/* +* Write Data Bus Inversion Enable +*/ #undef DDR_PHY_DX8SL2DXCTL2_WDBI_DEFVAL #undef DDR_PHY_DX8SL2DXCTL2_WDBI_SHIFT #undef DDR_PHY_DX8SL2DXCTL2_WDBI_MASK -#define DDR_PHY_DX8SL2DXCTL2_WDBI_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL2DXCTL2_WDBI_SHIFT 7 -#define DDR_PHY_DX8SL2DXCTL2_WDBI_MASK 0x00000080U +#define DDR_PHY_DX8SL2DXCTL2_WDBI_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_WDBI_SHIFT 7 +#define DDR_PHY_DX8SL2DXCTL2_WDBI_MASK 0x00000080U -/*PUB Read FIFO Bypass*/ +/* +* PUB Read FIFO Bypass +*/ #undef DDR_PHY_DX8SL2DXCTL2_PRFBYP_DEFVAL #undef DDR_PHY_DX8SL2DXCTL2_PRFBYP_SHIFT #undef DDR_PHY_DX8SL2DXCTL2_PRFBYP_MASK -#define DDR_PHY_DX8SL2DXCTL2_PRFBYP_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL2DXCTL2_PRFBYP_SHIFT 6 -#define DDR_PHY_DX8SL2DXCTL2_PRFBYP_MASK 0x00000040U +#define DDR_PHY_DX8SL2DXCTL2_PRFBYP_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_PRFBYP_SHIFT 6 +#define DDR_PHY_DX8SL2DXCTL2_PRFBYP_MASK 0x00000040U -/*DATX8 Receive FIFO Read Mode*/ +/* +* DATX8 Receive FIFO Read Mode +*/ #undef DDR_PHY_DX8SL2DXCTL2_RDMODE_DEFVAL #undef DDR_PHY_DX8SL2DXCTL2_RDMODE_SHIFT #undef DDR_PHY_DX8SL2DXCTL2_RDMODE_MASK -#define DDR_PHY_DX8SL2DXCTL2_RDMODE_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL2DXCTL2_RDMODE_SHIFT 4 -#define DDR_PHY_DX8SL2DXCTL2_RDMODE_MASK 0x00000030U +#define DDR_PHY_DX8SL2DXCTL2_RDMODE_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_RDMODE_SHIFT 4 +#define DDR_PHY_DX8SL2DXCTL2_RDMODE_MASK 0x00000030U -/*Disables the Read FIFO Reset*/ +/* +* Disables the Read FIFO Reset +*/ #undef DDR_PHY_DX8SL2DXCTL2_DISRST_DEFVAL #undef DDR_PHY_DX8SL2DXCTL2_DISRST_SHIFT #undef DDR_PHY_DX8SL2DXCTL2_DISRST_MASK -#define DDR_PHY_DX8SL2DXCTL2_DISRST_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL2DXCTL2_DISRST_SHIFT 3 -#define DDR_PHY_DX8SL2DXCTL2_DISRST_MASK 0x00000008U +#define DDR_PHY_DX8SL2DXCTL2_DISRST_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_DISRST_SHIFT 3 +#define DDR_PHY_DX8SL2DXCTL2_DISRST_MASK 0x00000008U -/*Read DQS Gate I/O Loopback*/ +/* +* Read DQS Gate I/O Loopback +*/ #undef DDR_PHY_DX8SL2DXCTL2_DQSGLB_DEFVAL #undef DDR_PHY_DX8SL2DXCTL2_DQSGLB_SHIFT #undef DDR_PHY_DX8SL2DXCTL2_DQSGLB_MASK -#define DDR_PHY_DX8SL2DXCTL2_DQSGLB_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL2DXCTL2_DQSGLB_SHIFT 1 -#define DDR_PHY_DX8SL2DXCTL2_DQSGLB_MASK 0x00000006U +#define DDR_PHY_DX8SL2DXCTL2_DQSGLB_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_DQSGLB_SHIFT 1 +#define DDR_PHY_DX8SL2DXCTL2_DQSGLB_MASK 0x00000006U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_0_DEFVAL #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_0_SHIFT #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_0_MASK -#define DDR_PHY_DX8SL2DXCTL2_RESERVED_0_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL2DXCTL2_RESERVED_0_SHIFT 0 -#define DDR_PHY_DX8SL2DXCTL2_RESERVED_0_MASK 0x00000001U +#define DDR_PHY_DX8SL2DXCTL2_RESERVED_0_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_RESERVED_0_SHIFT 0 +#define DDR_PHY_DX8SL2DXCTL2_RESERVED_0_MASK 0x00000001U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL2IOCR_RESERVED_31_DEFVAL #undef DDR_PHY_DX8SL2IOCR_RESERVED_31_SHIFT #undef DDR_PHY_DX8SL2IOCR_RESERVED_31_MASK -#define DDR_PHY_DX8SL2IOCR_RESERVED_31_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL2IOCR_RESERVED_31_SHIFT 31 -#define DDR_PHY_DX8SL2IOCR_RESERVED_31_MASK 0x80000000U +#define DDR_PHY_DX8SL2IOCR_RESERVED_31_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL2IOCR_RESERVED_31_SHIFT 31 +#define DDR_PHY_DX8SL2IOCR_RESERVED_31_MASK 0x80000000U -/*PVREF_DAC REFSEL range select*/ +/* +* PVREF_DAC REFSEL range select +*/ #undef DDR_PHY_DX8SL2IOCR_DXDACRANGE_DEFVAL #undef DDR_PHY_DX8SL2IOCR_DXDACRANGE_SHIFT #undef DDR_PHY_DX8SL2IOCR_DXDACRANGE_MASK -#define DDR_PHY_DX8SL2IOCR_DXDACRANGE_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL2IOCR_DXDACRANGE_SHIFT 28 -#define DDR_PHY_DX8SL2IOCR_DXDACRANGE_MASK 0x70000000U +#define DDR_PHY_DX8SL2IOCR_DXDACRANGE_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL2IOCR_DXDACRANGE_SHIFT 28 +#define DDR_PHY_DX8SL2IOCR_DXDACRANGE_MASK 0x70000000U -/*IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring*/ +/* +* IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring +*/ #undef DDR_PHY_DX8SL2IOCR_DXVREFIOM_DEFVAL #undef DDR_PHY_DX8SL2IOCR_DXVREFIOM_SHIFT #undef DDR_PHY_DX8SL2IOCR_DXVREFIOM_MASK -#define DDR_PHY_DX8SL2IOCR_DXVREFIOM_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL2IOCR_DXVREFIOM_SHIFT 25 -#define DDR_PHY_DX8SL2IOCR_DXVREFIOM_MASK 0x0E000000U +#define DDR_PHY_DX8SL2IOCR_DXVREFIOM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL2IOCR_DXVREFIOM_SHIFT 25 +#define DDR_PHY_DX8SL2IOCR_DXVREFIOM_MASK 0x0E000000U -/*DX IO Mode*/ +/* +* DX IO Mode +*/ #undef DDR_PHY_DX8SL2IOCR_DXIOM_DEFVAL #undef DDR_PHY_DX8SL2IOCR_DXIOM_SHIFT #undef DDR_PHY_DX8SL2IOCR_DXIOM_MASK -#define DDR_PHY_DX8SL2IOCR_DXIOM_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL2IOCR_DXIOM_SHIFT 22 -#define DDR_PHY_DX8SL2IOCR_DXIOM_MASK 0x01C00000U +#define DDR_PHY_DX8SL2IOCR_DXIOM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL2IOCR_DXIOM_SHIFT 22 +#define DDR_PHY_DX8SL2IOCR_DXIOM_MASK 0x01C00000U -/*DX IO Transmitter Mode*/ +/* +* DX IO Transmitter Mode +*/ #undef DDR_PHY_DX8SL2IOCR_DXTXM_DEFVAL #undef DDR_PHY_DX8SL2IOCR_DXTXM_SHIFT #undef DDR_PHY_DX8SL2IOCR_DXTXM_MASK -#define DDR_PHY_DX8SL2IOCR_DXTXM_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL2IOCR_DXTXM_SHIFT 11 -#define DDR_PHY_DX8SL2IOCR_DXTXM_MASK 0x003FF800U +#define DDR_PHY_DX8SL2IOCR_DXTXM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL2IOCR_DXTXM_SHIFT 11 +#define DDR_PHY_DX8SL2IOCR_DXTXM_MASK 0x003FF800U -/*DX IO Receiver Mode*/ +/* +* DX IO Receiver Mode +*/ #undef DDR_PHY_DX8SL2IOCR_DXRXM_DEFVAL #undef DDR_PHY_DX8SL2IOCR_DXRXM_SHIFT #undef DDR_PHY_DX8SL2IOCR_DXRXM_MASK -#define DDR_PHY_DX8SL2IOCR_DXRXM_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL2IOCR_DXRXM_SHIFT 0 -#define DDR_PHY_DX8SL2IOCR_DXRXM_MASK 0x000007FFU +#define DDR_PHY_DX8SL2IOCR_DXRXM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL2IOCR_DXRXM_SHIFT 0 +#define DDR_PHY_DX8SL2IOCR_DXRXM_MASK 0x000007FFU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL3OSC_RESERVED_31_30_DEFVAL #undef DDR_PHY_DX8SL3OSC_RESERVED_31_30_SHIFT #undef DDR_PHY_DX8SL3OSC_RESERVED_31_30_MASK -#define DDR_PHY_DX8SL3OSC_RESERVED_31_30_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL3OSC_RESERVED_31_30_SHIFT 30 -#define DDR_PHY_DX8SL3OSC_RESERVED_31_30_MASK 0xC0000000U +#define DDR_PHY_DX8SL3OSC_RESERVED_31_30_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX8SL3OSC_RESERVED_31_30_MASK 0xC0000000U -/*Enable Clock Gating for DX ddr_clk*/ +/* +* Enable Clock Gating for DX ddr_clk +*/ #undef DDR_PHY_DX8SL3OSC_GATEDXRDCLK_DEFVAL #undef DDR_PHY_DX8SL3OSC_GATEDXRDCLK_SHIFT #undef DDR_PHY_DX8SL3OSC_GATEDXRDCLK_MASK -#define DDR_PHY_DX8SL3OSC_GATEDXRDCLK_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL3OSC_GATEDXRDCLK_SHIFT 28 -#define DDR_PHY_DX8SL3OSC_GATEDXRDCLK_MASK 0x30000000U +#define DDR_PHY_DX8SL3OSC_GATEDXRDCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_GATEDXRDCLK_SHIFT 28 +#define DDR_PHY_DX8SL3OSC_GATEDXRDCLK_MASK 0x30000000U -/*Enable Clock Gating for DX ctl_rd_clk*/ +/* +* Enable Clock Gating for DX ctl_rd_clk +*/ #undef DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_DEFVAL #undef DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_SHIFT #undef DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_MASK -#define DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_SHIFT 26 -#define DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_MASK 0x0C000000U +#define DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_SHIFT 26 +#define DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_MASK 0x0C000000U -/*Enable Clock Gating for DX ctl_clk*/ +/* +* Enable Clock Gating for DX ctl_clk +*/ #undef DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_DEFVAL #undef DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_SHIFT #undef DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_MASK -#define DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_SHIFT 24 -#define DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_MASK 0x03000000U +#define DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_SHIFT 24 +#define DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_MASK 0x03000000U -/*Selects the level to which clocks will be stalled when clock gating is enabled.*/ +/* +* Selects the level to which clocks will be stalled when clock gating is e + * nabled. +*/ #undef DDR_PHY_DX8SL3OSC_CLKLEVEL_DEFVAL #undef DDR_PHY_DX8SL3OSC_CLKLEVEL_SHIFT #undef DDR_PHY_DX8SL3OSC_CLKLEVEL_MASK -#define DDR_PHY_DX8SL3OSC_CLKLEVEL_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL3OSC_CLKLEVEL_SHIFT 22 -#define DDR_PHY_DX8SL3OSC_CLKLEVEL_MASK 0x00C00000U +#define DDR_PHY_DX8SL3OSC_CLKLEVEL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_CLKLEVEL_SHIFT 22 +#define DDR_PHY_DX8SL3OSC_CLKLEVEL_MASK 0x00C00000U -/*Loopback Mode*/ +/* +* Loopback Mode +*/ #undef DDR_PHY_DX8SL3OSC_LBMODE_DEFVAL #undef DDR_PHY_DX8SL3OSC_LBMODE_SHIFT #undef DDR_PHY_DX8SL3OSC_LBMODE_MASK -#define DDR_PHY_DX8SL3OSC_LBMODE_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL3OSC_LBMODE_SHIFT 21 -#define DDR_PHY_DX8SL3OSC_LBMODE_MASK 0x00200000U +#define DDR_PHY_DX8SL3OSC_LBMODE_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_LBMODE_SHIFT 21 +#define DDR_PHY_DX8SL3OSC_LBMODE_MASK 0x00200000U -/*Load GSDQS LCDL with 2x the calibrated GSDQSPRD value*/ +/* +* Load GSDQS LCDL with 2x the calibrated GSDQSPRD value +*/ #undef DDR_PHY_DX8SL3OSC_LBGSDQS_DEFVAL #undef DDR_PHY_DX8SL3OSC_LBGSDQS_SHIFT #undef DDR_PHY_DX8SL3OSC_LBGSDQS_MASK -#define DDR_PHY_DX8SL3OSC_LBGSDQS_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL3OSC_LBGSDQS_SHIFT 20 -#define DDR_PHY_DX8SL3OSC_LBGSDQS_MASK 0x00100000U +#define DDR_PHY_DX8SL3OSC_LBGSDQS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_LBGSDQS_SHIFT 20 +#define DDR_PHY_DX8SL3OSC_LBGSDQS_MASK 0x00100000U -/*Loopback DQS Gating*/ +/* +* Loopback DQS Gating +*/ #undef DDR_PHY_DX8SL3OSC_LBGDQS_DEFVAL #undef DDR_PHY_DX8SL3OSC_LBGDQS_SHIFT #undef DDR_PHY_DX8SL3OSC_LBGDQS_MASK -#define DDR_PHY_DX8SL3OSC_LBGDQS_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL3OSC_LBGDQS_SHIFT 18 -#define DDR_PHY_DX8SL3OSC_LBGDQS_MASK 0x000C0000U +#define DDR_PHY_DX8SL3OSC_LBGDQS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_LBGDQS_SHIFT 18 +#define DDR_PHY_DX8SL3OSC_LBGDQS_MASK 0x000C0000U -/*Loopback DQS Shift*/ +/* +* Loopback DQS Shift +*/ #undef DDR_PHY_DX8SL3OSC_LBDQSS_DEFVAL #undef DDR_PHY_DX8SL3OSC_LBDQSS_SHIFT #undef DDR_PHY_DX8SL3OSC_LBDQSS_MASK -#define DDR_PHY_DX8SL3OSC_LBDQSS_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL3OSC_LBDQSS_SHIFT 17 -#define DDR_PHY_DX8SL3OSC_LBDQSS_MASK 0x00020000U +#define DDR_PHY_DX8SL3OSC_LBDQSS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_LBDQSS_SHIFT 17 +#define DDR_PHY_DX8SL3OSC_LBDQSS_MASK 0x00020000U -/*PHY High-Speed Reset*/ +/* +* PHY High-Speed Reset +*/ #undef DDR_PHY_DX8SL3OSC_PHYHRST_DEFVAL #undef DDR_PHY_DX8SL3OSC_PHYHRST_SHIFT #undef DDR_PHY_DX8SL3OSC_PHYHRST_MASK -#define DDR_PHY_DX8SL3OSC_PHYHRST_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL3OSC_PHYHRST_SHIFT 16 -#define DDR_PHY_DX8SL3OSC_PHYHRST_MASK 0x00010000U +#define DDR_PHY_DX8SL3OSC_PHYHRST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_PHYHRST_SHIFT 16 +#define DDR_PHY_DX8SL3OSC_PHYHRST_MASK 0x00010000U -/*PHY FIFO Reset*/ +/* +* PHY FIFO Reset +*/ #undef DDR_PHY_DX8SL3OSC_PHYFRST_DEFVAL #undef DDR_PHY_DX8SL3OSC_PHYFRST_SHIFT #undef DDR_PHY_DX8SL3OSC_PHYFRST_MASK -#define DDR_PHY_DX8SL3OSC_PHYFRST_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL3OSC_PHYFRST_SHIFT 15 -#define DDR_PHY_DX8SL3OSC_PHYFRST_MASK 0x00008000U +#define DDR_PHY_DX8SL3OSC_PHYFRST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_PHYFRST_SHIFT 15 +#define DDR_PHY_DX8SL3OSC_PHYFRST_MASK 0x00008000U -/*Delay Line Test Start*/ +/* +* Delay Line Test Start +*/ #undef DDR_PHY_DX8SL3OSC_DLTST_DEFVAL #undef DDR_PHY_DX8SL3OSC_DLTST_SHIFT #undef DDR_PHY_DX8SL3OSC_DLTST_MASK -#define DDR_PHY_DX8SL3OSC_DLTST_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL3OSC_DLTST_SHIFT 14 -#define DDR_PHY_DX8SL3OSC_DLTST_MASK 0x00004000U +#define DDR_PHY_DX8SL3OSC_DLTST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_DLTST_SHIFT 14 +#define DDR_PHY_DX8SL3OSC_DLTST_MASK 0x00004000U -/*Delay Line Test Mode*/ +/* +* Delay Line Test Mode +*/ #undef DDR_PHY_DX8SL3OSC_DLTMODE_DEFVAL #undef DDR_PHY_DX8SL3OSC_DLTMODE_SHIFT #undef DDR_PHY_DX8SL3OSC_DLTMODE_MASK -#define DDR_PHY_DX8SL3OSC_DLTMODE_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL3OSC_DLTMODE_SHIFT 13 -#define DDR_PHY_DX8SL3OSC_DLTMODE_MASK 0x00002000U +#define DDR_PHY_DX8SL3OSC_DLTMODE_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_DLTMODE_SHIFT 13 +#define DDR_PHY_DX8SL3OSC_DLTMODE_MASK 0x00002000U -/*Reserved. Caution, do not write to this register field.*/ +/* +* Reserved. Caution, do not write to this register field. +*/ #undef DDR_PHY_DX8SL3OSC_RESERVED_12_11_DEFVAL #undef DDR_PHY_DX8SL3OSC_RESERVED_12_11_SHIFT #undef DDR_PHY_DX8SL3OSC_RESERVED_12_11_MASK -#define DDR_PHY_DX8SL3OSC_RESERVED_12_11_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL3OSC_RESERVED_12_11_SHIFT 11 -#define DDR_PHY_DX8SL3OSC_RESERVED_12_11_MASK 0x00001800U +#define DDR_PHY_DX8SL3OSC_RESERVED_12_11_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_RESERVED_12_11_SHIFT 11 +#define DDR_PHY_DX8SL3OSC_RESERVED_12_11_MASK 0x00001800U -/*Oscillator Mode Write-Data Delay Line Select*/ +/* +* Oscillator Mode Write-Data Delay Line Select +*/ #undef DDR_PHY_DX8SL3OSC_OSCWDDL_DEFVAL #undef DDR_PHY_DX8SL3OSC_OSCWDDL_SHIFT #undef DDR_PHY_DX8SL3OSC_OSCWDDL_MASK -#define DDR_PHY_DX8SL3OSC_OSCWDDL_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL3OSC_OSCWDDL_SHIFT 9 -#define DDR_PHY_DX8SL3OSC_OSCWDDL_MASK 0x00000600U +#define DDR_PHY_DX8SL3OSC_OSCWDDL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_OSCWDDL_SHIFT 9 +#define DDR_PHY_DX8SL3OSC_OSCWDDL_MASK 0x00000600U -/*Reserved. Caution, do not write to this register field.*/ +/* +* Reserved. Caution, do not write to this register field. +*/ #undef DDR_PHY_DX8SL3OSC_RESERVED_8_7_DEFVAL #undef DDR_PHY_DX8SL3OSC_RESERVED_8_7_SHIFT #undef DDR_PHY_DX8SL3OSC_RESERVED_8_7_MASK -#define DDR_PHY_DX8SL3OSC_RESERVED_8_7_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL3OSC_RESERVED_8_7_SHIFT 7 -#define DDR_PHY_DX8SL3OSC_RESERVED_8_7_MASK 0x00000180U +#define DDR_PHY_DX8SL3OSC_RESERVED_8_7_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_RESERVED_8_7_SHIFT 7 +#define DDR_PHY_DX8SL3OSC_RESERVED_8_7_MASK 0x00000180U -/*Oscillator Mode Write-Leveling Delay Line Select*/ +/* +* Oscillator Mode Write-Leveling Delay Line Select +*/ #undef DDR_PHY_DX8SL3OSC_OSCWDL_DEFVAL #undef DDR_PHY_DX8SL3OSC_OSCWDL_SHIFT #undef DDR_PHY_DX8SL3OSC_OSCWDL_MASK -#define DDR_PHY_DX8SL3OSC_OSCWDL_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL3OSC_OSCWDL_SHIFT 5 -#define DDR_PHY_DX8SL3OSC_OSCWDL_MASK 0x00000060U +#define DDR_PHY_DX8SL3OSC_OSCWDL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_OSCWDL_SHIFT 5 +#define DDR_PHY_DX8SL3OSC_OSCWDL_MASK 0x00000060U -/*Oscillator Mode Division*/ +/* +* Oscillator Mode Division +*/ #undef DDR_PHY_DX8SL3OSC_OSCDIV_DEFVAL #undef DDR_PHY_DX8SL3OSC_OSCDIV_SHIFT #undef DDR_PHY_DX8SL3OSC_OSCDIV_MASK -#define DDR_PHY_DX8SL3OSC_OSCDIV_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL3OSC_OSCDIV_SHIFT 1 -#define DDR_PHY_DX8SL3OSC_OSCDIV_MASK 0x0000001EU +#define DDR_PHY_DX8SL3OSC_OSCDIV_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_OSCDIV_SHIFT 1 +#define DDR_PHY_DX8SL3OSC_OSCDIV_MASK 0x0000001EU -/*Oscillator Enable*/ +/* +* Oscillator Enable +*/ #undef DDR_PHY_DX8SL3OSC_OSCEN_DEFVAL #undef DDR_PHY_DX8SL3OSC_OSCEN_SHIFT #undef DDR_PHY_DX8SL3OSC_OSCEN_MASK -#define DDR_PHY_DX8SL3OSC_OSCEN_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL3OSC_OSCEN_SHIFT 0 -#define DDR_PHY_DX8SL3OSC_OSCEN_MASK 0x00000001U +#define DDR_PHY_DX8SL3OSC_OSCEN_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_OSCEN_SHIFT 0 +#define DDR_PHY_DX8SL3OSC_OSCEN_MASK 0x00000001U -/*Reserved. Return zeroes on reads.*/ +/* +* PLL Bypass +*/ +#undef DDR_PHY_DX8SL3PLLCR0_PLLBYP_DEFVAL +#undef DDR_PHY_DX8SL3PLLCR0_PLLBYP_SHIFT +#undef DDR_PHY_DX8SL3PLLCR0_PLLBYP_MASK +#define DDR_PHY_DX8SL3PLLCR0_PLLBYP_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL3PLLCR0_PLLBYP_SHIFT 31 +#define DDR_PHY_DX8SL3PLLCR0_PLLBYP_MASK 0x80000000U + +/* +* PLL Reset +*/ +#undef DDR_PHY_DX8SL3PLLCR0_PLLRST_DEFVAL +#undef DDR_PHY_DX8SL3PLLCR0_PLLRST_SHIFT +#undef DDR_PHY_DX8SL3PLLCR0_PLLRST_MASK +#define DDR_PHY_DX8SL3PLLCR0_PLLRST_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL3PLLCR0_PLLRST_SHIFT 30 +#define DDR_PHY_DX8SL3PLLCR0_PLLRST_MASK 0x40000000U + +/* +* PLL Power Down +*/ +#undef DDR_PHY_DX8SL3PLLCR0_PLLPD_DEFVAL +#undef DDR_PHY_DX8SL3PLLCR0_PLLPD_SHIFT +#undef DDR_PHY_DX8SL3PLLCR0_PLLPD_MASK +#define DDR_PHY_DX8SL3PLLCR0_PLLPD_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL3PLLCR0_PLLPD_SHIFT 29 +#define DDR_PHY_DX8SL3PLLCR0_PLLPD_MASK 0x20000000U + +/* +* Reference Stop Mode +*/ +#undef DDR_PHY_DX8SL3PLLCR0_RSTOPM_DEFVAL +#undef DDR_PHY_DX8SL3PLLCR0_RSTOPM_SHIFT +#undef DDR_PHY_DX8SL3PLLCR0_RSTOPM_MASK +#define DDR_PHY_DX8SL3PLLCR0_RSTOPM_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL3PLLCR0_RSTOPM_SHIFT 28 +#define DDR_PHY_DX8SL3PLLCR0_RSTOPM_MASK 0x10000000U + +/* +* PLL Frequency Select +*/ +#undef DDR_PHY_DX8SL3PLLCR0_FRQSEL_DEFVAL +#undef DDR_PHY_DX8SL3PLLCR0_FRQSEL_SHIFT +#undef DDR_PHY_DX8SL3PLLCR0_FRQSEL_MASK +#define DDR_PHY_DX8SL3PLLCR0_FRQSEL_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL3PLLCR0_FRQSEL_SHIFT 24 +#define DDR_PHY_DX8SL3PLLCR0_FRQSEL_MASK 0x0F000000U + +/* +* Relock Mode +*/ +#undef DDR_PHY_DX8SL3PLLCR0_RLOCKM_DEFVAL +#undef DDR_PHY_DX8SL3PLLCR0_RLOCKM_SHIFT +#undef DDR_PHY_DX8SL3PLLCR0_RLOCKM_MASK +#define DDR_PHY_DX8SL3PLLCR0_RLOCKM_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL3PLLCR0_RLOCKM_SHIFT 23 +#define DDR_PHY_DX8SL3PLLCR0_RLOCKM_MASK 0x00800000U + +/* +* Charge Pump Proportional Current Control +*/ +#undef DDR_PHY_DX8SL3PLLCR0_CPPC_DEFVAL +#undef DDR_PHY_DX8SL3PLLCR0_CPPC_SHIFT +#undef DDR_PHY_DX8SL3PLLCR0_CPPC_MASK +#define DDR_PHY_DX8SL3PLLCR0_CPPC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL3PLLCR0_CPPC_SHIFT 17 +#define DDR_PHY_DX8SL3PLLCR0_CPPC_MASK 0x007E0000U + +/* +* Charge Pump Integrating Current Control +*/ +#undef DDR_PHY_DX8SL3PLLCR0_CPIC_DEFVAL +#undef DDR_PHY_DX8SL3PLLCR0_CPIC_SHIFT +#undef DDR_PHY_DX8SL3PLLCR0_CPIC_MASK +#define DDR_PHY_DX8SL3PLLCR0_CPIC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL3PLLCR0_CPIC_SHIFT 13 +#define DDR_PHY_DX8SL3PLLCR0_CPIC_MASK 0x0001E000U + +/* +* Gear Shift +*/ +#undef DDR_PHY_DX8SL3PLLCR0_GSHIFT_DEFVAL +#undef DDR_PHY_DX8SL3PLLCR0_GSHIFT_SHIFT +#undef DDR_PHY_DX8SL3PLLCR0_GSHIFT_MASK +#define DDR_PHY_DX8SL3PLLCR0_GSHIFT_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL3PLLCR0_GSHIFT_SHIFT 12 +#define DDR_PHY_DX8SL3PLLCR0_GSHIFT_MASK 0x00001000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL3PLLCR0_RESERVED_11_9_DEFVAL +#undef DDR_PHY_DX8SL3PLLCR0_RESERVED_11_9_SHIFT +#undef DDR_PHY_DX8SL3PLLCR0_RESERVED_11_9_MASK +#define DDR_PHY_DX8SL3PLLCR0_RESERVED_11_9_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL3PLLCR0_RESERVED_11_9_SHIFT 9 +#define DDR_PHY_DX8SL3PLLCR0_RESERVED_11_9_MASK 0x00000E00U + +/* +* Analog Test Enable (ATOEN) +*/ +#undef DDR_PHY_DX8SL3PLLCR0_ATOEN_DEFVAL +#undef DDR_PHY_DX8SL3PLLCR0_ATOEN_SHIFT +#undef DDR_PHY_DX8SL3PLLCR0_ATOEN_MASK +#define DDR_PHY_DX8SL3PLLCR0_ATOEN_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL3PLLCR0_ATOEN_SHIFT 8 +#define DDR_PHY_DX8SL3PLLCR0_ATOEN_MASK 0x00000100U + +/* +* Analog Test Control +*/ +#undef DDR_PHY_DX8SL3PLLCR0_ATC_DEFVAL +#undef DDR_PHY_DX8SL3PLLCR0_ATC_SHIFT +#undef DDR_PHY_DX8SL3PLLCR0_ATC_MASK +#define DDR_PHY_DX8SL3PLLCR0_ATC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL3PLLCR0_ATC_SHIFT 4 +#define DDR_PHY_DX8SL3PLLCR0_ATC_MASK 0x000000F0U + +/* +* Digital Test Control +*/ +#undef DDR_PHY_DX8SL3PLLCR0_DTC_DEFVAL +#undef DDR_PHY_DX8SL3PLLCR0_DTC_SHIFT +#undef DDR_PHY_DX8SL3PLLCR0_DTC_MASK +#define DDR_PHY_DX8SL3PLLCR0_DTC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL3PLLCR0_DTC_SHIFT 0 +#define DDR_PHY_DX8SL3PLLCR0_DTC_MASK 0x0000000FU + +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_DEFVAL #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_SHIFT #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_MASK -#define DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_SHIFT 25 -#define DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_MASK 0xFE000000U +#define DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_SHIFT 25 +#define DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_MASK 0xFE000000U -/*Read Path Rise-to-Rise Mode*/ +/* +* Read Path Rise-to-Rise Mode +*/ #undef DDR_PHY_DX8SL3DQSCTL_RRRMODE_DEFVAL #undef DDR_PHY_DX8SL3DQSCTL_RRRMODE_SHIFT #undef DDR_PHY_DX8SL3DQSCTL_RRRMODE_MASK -#define DDR_PHY_DX8SL3DQSCTL_RRRMODE_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL3DQSCTL_RRRMODE_SHIFT 24 -#define DDR_PHY_DX8SL3DQSCTL_RRRMODE_MASK 0x01000000U +#define DDR_PHY_DX8SL3DQSCTL_RRRMODE_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL3DQSCTL_RRRMODE_SHIFT 24 +#define DDR_PHY_DX8SL3DQSCTL_RRRMODE_MASK 0x01000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_DEFVAL #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_SHIFT #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_MASK -#define DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_SHIFT 22 -#define DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_MASK 0x00C00000U +#define DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_MASK 0x00C00000U -/*Write Path Rise-to-Rise Mode*/ +/* +* Write Path Rise-to-Rise Mode +*/ #undef DDR_PHY_DX8SL3DQSCTL_WRRMODE_DEFVAL #undef DDR_PHY_DX8SL3DQSCTL_WRRMODE_SHIFT #undef DDR_PHY_DX8SL3DQSCTL_WRRMODE_MASK -#define DDR_PHY_DX8SL3DQSCTL_WRRMODE_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL3DQSCTL_WRRMODE_SHIFT 21 -#define DDR_PHY_DX8SL3DQSCTL_WRRMODE_MASK 0x00200000U +#define DDR_PHY_DX8SL3DQSCTL_WRRMODE_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL3DQSCTL_WRRMODE_SHIFT 21 +#define DDR_PHY_DX8SL3DQSCTL_WRRMODE_MASK 0x00200000U -/*DQS Gate Extension*/ +/* +* DQS Gate Extension +*/ #undef DDR_PHY_DX8SL3DQSCTL_DQSGX_DEFVAL #undef DDR_PHY_DX8SL3DQSCTL_DQSGX_SHIFT #undef DDR_PHY_DX8SL3DQSCTL_DQSGX_MASK -#define DDR_PHY_DX8SL3DQSCTL_DQSGX_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL3DQSCTL_DQSGX_SHIFT 19 -#define DDR_PHY_DX8SL3DQSCTL_DQSGX_MASK 0x00180000U +#define DDR_PHY_DX8SL3DQSCTL_DQSGX_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL3DQSCTL_DQSGX_SHIFT 19 +#define DDR_PHY_DX8SL3DQSCTL_DQSGX_MASK 0x00180000U -/*Low Power PLL Power Down*/ +/* +* Low Power PLL Power Down +*/ #undef DDR_PHY_DX8SL3DQSCTL_LPPLLPD_DEFVAL #undef DDR_PHY_DX8SL3DQSCTL_LPPLLPD_SHIFT #undef DDR_PHY_DX8SL3DQSCTL_LPPLLPD_MASK -#define DDR_PHY_DX8SL3DQSCTL_LPPLLPD_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL3DQSCTL_LPPLLPD_SHIFT 18 -#define DDR_PHY_DX8SL3DQSCTL_LPPLLPD_MASK 0x00040000U +#define DDR_PHY_DX8SL3DQSCTL_LPPLLPD_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL3DQSCTL_LPPLLPD_SHIFT 18 +#define DDR_PHY_DX8SL3DQSCTL_LPPLLPD_MASK 0x00040000U -/*Low Power I/O Power Down*/ +/* +* Low Power I/O Power Down +*/ #undef DDR_PHY_DX8SL3DQSCTL_LPIOPD_DEFVAL #undef DDR_PHY_DX8SL3DQSCTL_LPIOPD_SHIFT #undef DDR_PHY_DX8SL3DQSCTL_LPIOPD_MASK -#define DDR_PHY_DX8SL3DQSCTL_LPIOPD_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL3DQSCTL_LPIOPD_SHIFT 17 -#define DDR_PHY_DX8SL3DQSCTL_LPIOPD_MASK 0x00020000U +#define DDR_PHY_DX8SL3DQSCTL_LPIOPD_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL3DQSCTL_LPIOPD_SHIFT 17 +#define DDR_PHY_DX8SL3DQSCTL_LPIOPD_MASK 0x00020000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_DEFVAL #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_SHIFT #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_MASK -#define DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_SHIFT 15 -#define DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_MASK 0x00018000U +#define DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_SHIFT 15 +#define DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_MASK 0x00018000U -/*QS Counter Enable*/ +/* +* QS Counter Enable +*/ #undef DDR_PHY_DX8SL3DQSCTL_QSCNTEN_DEFVAL #undef DDR_PHY_DX8SL3DQSCTL_QSCNTEN_SHIFT #undef DDR_PHY_DX8SL3DQSCTL_QSCNTEN_MASK -#define DDR_PHY_DX8SL3DQSCTL_QSCNTEN_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL3DQSCTL_QSCNTEN_SHIFT 14 -#define DDR_PHY_DX8SL3DQSCTL_QSCNTEN_MASK 0x00004000U +#define DDR_PHY_DX8SL3DQSCTL_QSCNTEN_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL3DQSCTL_QSCNTEN_SHIFT 14 +#define DDR_PHY_DX8SL3DQSCTL_QSCNTEN_MASK 0x00004000U -/*Unused DQ I/O Mode*/ +/* +* Unused DQ I/O Mode +*/ #undef DDR_PHY_DX8SL3DQSCTL_UDQIOM_DEFVAL #undef DDR_PHY_DX8SL3DQSCTL_UDQIOM_SHIFT #undef DDR_PHY_DX8SL3DQSCTL_UDQIOM_MASK -#define DDR_PHY_DX8SL3DQSCTL_UDQIOM_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL3DQSCTL_UDQIOM_SHIFT 13 -#define DDR_PHY_DX8SL3DQSCTL_UDQIOM_MASK 0x00002000U +#define DDR_PHY_DX8SL3DQSCTL_UDQIOM_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL3DQSCTL_UDQIOM_SHIFT 13 +#define DDR_PHY_DX8SL3DQSCTL_UDQIOM_MASK 0x00002000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_DEFVAL #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_SHIFT #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_MASK -#define DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_SHIFT 10 -#define DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_MASK 0x00001C00U +#define DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_SHIFT 10 +#define DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_MASK 0x00001C00U -/*Data Slew Rate*/ +/* +* Data Slew Rate +*/ #undef DDR_PHY_DX8SL3DQSCTL_DXSR_DEFVAL #undef DDR_PHY_DX8SL3DQSCTL_DXSR_SHIFT #undef DDR_PHY_DX8SL3DQSCTL_DXSR_MASK -#define DDR_PHY_DX8SL3DQSCTL_DXSR_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL3DQSCTL_DXSR_SHIFT 8 -#define DDR_PHY_DX8SL3DQSCTL_DXSR_MASK 0x00000300U +#define DDR_PHY_DX8SL3DQSCTL_DXSR_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL3DQSCTL_DXSR_SHIFT 8 +#define DDR_PHY_DX8SL3DQSCTL_DXSR_MASK 0x00000300U -/*DQS_N Resistor*/ +/* +* DQS_N Resistor +*/ #undef DDR_PHY_DX8SL3DQSCTL_DQSNRES_DEFVAL #undef DDR_PHY_DX8SL3DQSCTL_DQSNRES_SHIFT #undef DDR_PHY_DX8SL3DQSCTL_DQSNRES_MASK -#define DDR_PHY_DX8SL3DQSCTL_DQSNRES_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL3DQSCTL_DQSNRES_SHIFT 4 -#define DDR_PHY_DX8SL3DQSCTL_DQSNRES_MASK 0x000000F0U +#define DDR_PHY_DX8SL3DQSCTL_DQSNRES_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL3DQSCTL_DQSNRES_SHIFT 4 +#define DDR_PHY_DX8SL3DQSCTL_DQSNRES_MASK 0x000000F0U -/*DQS Resistor*/ +/* +* DQS Resistor +*/ #undef DDR_PHY_DX8SL3DQSCTL_DQSRES_DEFVAL #undef DDR_PHY_DX8SL3DQSCTL_DQSRES_SHIFT #undef DDR_PHY_DX8SL3DQSCTL_DQSRES_MASK -#define DDR_PHY_DX8SL3DQSCTL_DQSRES_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL3DQSCTL_DQSRES_SHIFT 0 -#define DDR_PHY_DX8SL3DQSCTL_DQSRES_MASK 0x0000000FU +#define DDR_PHY_DX8SL3DQSCTL_DQSRES_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL3DQSCTL_DQSRES_SHIFT 0 +#define DDR_PHY_DX8SL3DQSCTL_DQSRES_MASK 0x0000000FU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_DEFVAL #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_SHIFT #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_MASK -#define DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_SHIFT 24 -#define DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_MASK 0xFF000000U +#define DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_SHIFT 24 +#define DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_MASK 0xFF000000U -/*Configurable Read Data Enable*/ +/* +* Configurable Read Data Enable +*/ #undef DDR_PHY_DX8SL3DXCTL2_CRDEN_DEFVAL #undef DDR_PHY_DX8SL3DXCTL2_CRDEN_SHIFT #undef DDR_PHY_DX8SL3DXCTL2_CRDEN_MASK -#define DDR_PHY_DX8SL3DXCTL2_CRDEN_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL3DXCTL2_CRDEN_SHIFT 23 -#define DDR_PHY_DX8SL3DXCTL2_CRDEN_MASK 0x00800000U +#define DDR_PHY_DX8SL3DXCTL2_CRDEN_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_CRDEN_SHIFT 23 +#define DDR_PHY_DX8SL3DXCTL2_CRDEN_MASK 0x00800000U -/*OX Extension during Post-amble*/ +/* +* OX Extension during Post-amble +*/ #undef DDR_PHY_DX8SL3DXCTL2_POSOEX_DEFVAL #undef DDR_PHY_DX8SL3DXCTL2_POSOEX_SHIFT #undef DDR_PHY_DX8SL3DXCTL2_POSOEX_MASK -#define DDR_PHY_DX8SL3DXCTL2_POSOEX_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL3DXCTL2_POSOEX_SHIFT 20 -#define DDR_PHY_DX8SL3DXCTL2_POSOEX_MASK 0x00700000U +#define DDR_PHY_DX8SL3DXCTL2_POSOEX_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_POSOEX_SHIFT 20 +#define DDR_PHY_DX8SL3DXCTL2_POSOEX_MASK 0x00700000U -/*OE Extension during Pre-amble*/ +/* +* OE Extension during Pre-amble +*/ #undef DDR_PHY_DX8SL3DXCTL2_PREOEX_DEFVAL #undef DDR_PHY_DX8SL3DXCTL2_PREOEX_SHIFT #undef DDR_PHY_DX8SL3DXCTL2_PREOEX_MASK -#define DDR_PHY_DX8SL3DXCTL2_PREOEX_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL3DXCTL2_PREOEX_SHIFT 18 -#define DDR_PHY_DX8SL3DXCTL2_PREOEX_MASK 0x000C0000U +#define DDR_PHY_DX8SL3DXCTL2_PREOEX_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_PREOEX_SHIFT 18 +#define DDR_PHY_DX8SL3DXCTL2_PREOEX_MASK 0x000C0000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_17_DEFVAL #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_17_SHIFT #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_17_MASK -#define DDR_PHY_DX8SL3DXCTL2_RESERVED_17_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL3DXCTL2_RESERVED_17_SHIFT 17 -#define DDR_PHY_DX8SL3DXCTL2_RESERVED_17_MASK 0x00020000U +#define DDR_PHY_DX8SL3DXCTL2_RESERVED_17_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_RESERVED_17_SHIFT 17 +#define DDR_PHY_DX8SL3DXCTL2_RESERVED_17_MASK 0x00020000U -/*I/O Assisted Gate Select*/ +/* +* I/O Assisted Gate Select +*/ #undef DDR_PHY_DX8SL3DXCTL2_IOAG_DEFVAL #undef DDR_PHY_DX8SL3DXCTL2_IOAG_SHIFT #undef DDR_PHY_DX8SL3DXCTL2_IOAG_MASK -#define DDR_PHY_DX8SL3DXCTL2_IOAG_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL3DXCTL2_IOAG_SHIFT 16 -#define DDR_PHY_DX8SL3DXCTL2_IOAG_MASK 0x00010000U +#define DDR_PHY_DX8SL3DXCTL2_IOAG_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_IOAG_SHIFT 16 +#define DDR_PHY_DX8SL3DXCTL2_IOAG_MASK 0x00010000U -/*I/O Loopback Select*/ +/* +* I/O Loopback Select +*/ #undef DDR_PHY_DX8SL3DXCTL2_IOLB_DEFVAL #undef DDR_PHY_DX8SL3DXCTL2_IOLB_SHIFT #undef DDR_PHY_DX8SL3DXCTL2_IOLB_MASK -#define DDR_PHY_DX8SL3DXCTL2_IOLB_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL3DXCTL2_IOLB_SHIFT 15 -#define DDR_PHY_DX8SL3DXCTL2_IOLB_MASK 0x00008000U +#define DDR_PHY_DX8SL3DXCTL2_IOLB_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_IOLB_SHIFT 15 +#define DDR_PHY_DX8SL3DXCTL2_IOLB_MASK 0x00008000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_DEFVAL #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_SHIFT #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_MASK -#define DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_SHIFT 13 -#define DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_MASK 0x00006000U +#define DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_SHIFT 13 +#define DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_MASK 0x00006000U -/*Low Power Wakeup Threshold*/ +/* +* Low Power Wakeup Threshold +*/ #undef DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_DEFVAL #undef DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_SHIFT #undef DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_MASK -#define DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_SHIFT 9 -#define DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_MASK 0x00001E00U +#define DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_SHIFT 9 +#define DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_MASK 0x00001E00U -/*Read Data Bus Inversion Enable*/ +/* +* Read Data Bus Inversion Enable +*/ #undef DDR_PHY_DX8SL3DXCTL2_RDBI_DEFVAL #undef DDR_PHY_DX8SL3DXCTL2_RDBI_SHIFT #undef DDR_PHY_DX8SL3DXCTL2_RDBI_MASK -#define DDR_PHY_DX8SL3DXCTL2_RDBI_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL3DXCTL2_RDBI_SHIFT 8 -#define DDR_PHY_DX8SL3DXCTL2_RDBI_MASK 0x00000100U +#define DDR_PHY_DX8SL3DXCTL2_RDBI_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_RDBI_SHIFT 8 +#define DDR_PHY_DX8SL3DXCTL2_RDBI_MASK 0x00000100U -/*Write Data Bus Inversion Enable*/ +/* +* Write Data Bus Inversion Enable +*/ #undef DDR_PHY_DX8SL3DXCTL2_WDBI_DEFVAL #undef DDR_PHY_DX8SL3DXCTL2_WDBI_SHIFT #undef DDR_PHY_DX8SL3DXCTL2_WDBI_MASK -#define DDR_PHY_DX8SL3DXCTL2_WDBI_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL3DXCTL2_WDBI_SHIFT 7 -#define DDR_PHY_DX8SL3DXCTL2_WDBI_MASK 0x00000080U +#define DDR_PHY_DX8SL3DXCTL2_WDBI_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_WDBI_SHIFT 7 +#define DDR_PHY_DX8SL3DXCTL2_WDBI_MASK 0x00000080U -/*PUB Read FIFO Bypass*/ +/* +* PUB Read FIFO Bypass +*/ #undef DDR_PHY_DX8SL3DXCTL2_PRFBYP_DEFVAL #undef DDR_PHY_DX8SL3DXCTL2_PRFBYP_SHIFT #undef DDR_PHY_DX8SL3DXCTL2_PRFBYP_MASK -#define DDR_PHY_DX8SL3DXCTL2_PRFBYP_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL3DXCTL2_PRFBYP_SHIFT 6 -#define DDR_PHY_DX8SL3DXCTL2_PRFBYP_MASK 0x00000040U +#define DDR_PHY_DX8SL3DXCTL2_PRFBYP_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_PRFBYP_SHIFT 6 +#define DDR_PHY_DX8SL3DXCTL2_PRFBYP_MASK 0x00000040U -/*DATX8 Receive FIFO Read Mode*/ +/* +* DATX8 Receive FIFO Read Mode +*/ #undef DDR_PHY_DX8SL3DXCTL2_RDMODE_DEFVAL #undef DDR_PHY_DX8SL3DXCTL2_RDMODE_SHIFT #undef DDR_PHY_DX8SL3DXCTL2_RDMODE_MASK -#define DDR_PHY_DX8SL3DXCTL2_RDMODE_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL3DXCTL2_RDMODE_SHIFT 4 -#define DDR_PHY_DX8SL3DXCTL2_RDMODE_MASK 0x00000030U +#define DDR_PHY_DX8SL3DXCTL2_RDMODE_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_RDMODE_SHIFT 4 +#define DDR_PHY_DX8SL3DXCTL2_RDMODE_MASK 0x00000030U -/*Disables the Read FIFO Reset*/ +/* +* Disables the Read FIFO Reset +*/ #undef DDR_PHY_DX8SL3DXCTL2_DISRST_DEFVAL #undef DDR_PHY_DX8SL3DXCTL2_DISRST_SHIFT #undef DDR_PHY_DX8SL3DXCTL2_DISRST_MASK -#define DDR_PHY_DX8SL3DXCTL2_DISRST_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL3DXCTL2_DISRST_SHIFT 3 -#define DDR_PHY_DX8SL3DXCTL2_DISRST_MASK 0x00000008U +#define DDR_PHY_DX8SL3DXCTL2_DISRST_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_DISRST_SHIFT 3 +#define DDR_PHY_DX8SL3DXCTL2_DISRST_MASK 0x00000008U -/*Read DQS Gate I/O Loopback*/ +/* +* Read DQS Gate I/O Loopback +*/ #undef DDR_PHY_DX8SL3DXCTL2_DQSGLB_DEFVAL #undef DDR_PHY_DX8SL3DXCTL2_DQSGLB_SHIFT #undef DDR_PHY_DX8SL3DXCTL2_DQSGLB_MASK -#define DDR_PHY_DX8SL3DXCTL2_DQSGLB_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL3DXCTL2_DQSGLB_SHIFT 1 -#define DDR_PHY_DX8SL3DXCTL2_DQSGLB_MASK 0x00000006U +#define DDR_PHY_DX8SL3DXCTL2_DQSGLB_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_DQSGLB_SHIFT 1 +#define DDR_PHY_DX8SL3DXCTL2_DQSGLB_MASK 0x00000006U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_0_DEFVAL #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_0_SHIFT #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_0_MASK -#define DDR_PHY_DX8SL3DXCTL2_RESERVED_0_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL3DXCTL2_RESERVED_0_SHIFT 0 -#define DDR_PHY_DX8SL3DXCTL2_RESERVED_0_MASK 0x00000001U +#define DDR_PHY_DX8SL3DXCTL2_RESERVED_0_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_RESERVED_0_SHIFT 0 +#define DDR_PHY_DX8SL3DXCTL2_RESERVED_0_MASK 0x00000001U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL3IOCR_RESERVED_31_DEFVAL #undef DDR_PHY_DX8SL3IOCR_RESERVED_31_SHIFT #undef DDR_PHY_DX8SL3IOCR_RESERVED_31_MASK -#define DDR_PHY_DX8SL3IOCR_RESERVED_31_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL3IOCR_RESERVED_31_SHIFT 31 -#define DDR_PHY_DX8SL3IOCR_RESERVED_31_MASK 0x80000000U +#define DDR_PHY_DX8SL3IOCR_RESERVED_31_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL3IOCR_RESERVED_31_SHIFT 31 +#define DDR_PHY_DX8SL3IOCR_RESERVED_31_MASK 0x80000000U -/*PVREF_DAC REFSEL range select*/ +/* +* PVREF_DAC REFSEL range select +*/ #undef DDR_PHY_DX8SL3IOCR_DXDACRANGE_DEFVAL #undef DDR_PHY_DX8SL3IOCR_DXDACRANGE_SHIFT #undef DDR_PHY_DX8SL3IOCR_DXDACRANGE_MASK -#define DDR_PHY_DX8SL3IOCR_DXDACRANGE_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL3IOCR_DXDACRANGE_SHIFT 28 -#define DDR_PHY_DX8SL3IOCR_DXDACRANGE_MASK 0x70000000U +#define DDR_PHY_DX8SL3IOCR_DXDACRANGE_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL3IOCR_DXDACRANGE_SHIFT 28 +#define DDR_PHY_DX8SL3IOCR_DXDACRANGE_MASK 0x70000000U -/*IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring*/ +/* +* IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring +*/ #undef DDR_PHY_DX8SL3IOCR_DXVREFIOM_DEFVAL #undef DDR_PHY_DX8SL3IOCR_DXVREFIOM_SHIFT #undef DDR_PHY_DX8SL3IOCR_DXVREFIOM_MASK -#define DDR_PHY_DX8SL3IOCR_DXVREFIOM_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL3IOCR_DXVREFIOM_SHIFT 25 -#define DDR_PHY_DX8SL3IOCR_DXVREFIOM_MASK 0x0E000000U +#define DDR_PHY_DX8SL3IOCR_DXVREFIOM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL3IOCR_DXVREFIOM_SHIFT 25 +#define DDR_PHY_DX8SL3IOCR_DXVREFIOM_MASK 0x0E000000U -/*DX IO Mode*/ +/* +* DX IO Mode +*/ #undef DDR_PHY_DX8SL3IOCR_DXIOM_DEFVAL #undef DDR_PHY_DX8SL3IOCR_DXIOM_SHIFT #undef DDR_PHY_DX8SL3IOCR_DXIOM_MASK -#define DDR_PHY_DX8SL3IOCR_DXIOM_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL3IOCR_DXIOM_SHIFT 22 -#define DDR_PHY_DX8SL3IOCR_DXIOM_MASK 0x01C00000U +#define DDR_PHY_DX8SL3IOCR_DXIOM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL3IOCR_DXIOM_SHIFT 22 +#define DDR_PHY_DX8SL3IOCR_DXIOM_MASK 0x01C00000U -/*DX IO Transmitter Mode*/ +/* +* DX IO Transmitter Mode +*/ #undef DDR_PHY_DX8SL3IOCR_DXTXM_DEFVAL #undef DDR_PHY_DX8SL3IOCR_DXTXM_SHIFT #undef DDR_PHY_DX8SL3IOCR_DXTXM_MASK -#define DDR_PHY_DX8SL3IOCR_DXTXM_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL3IOCR_DXTXM_SHIFT 11 -#define DDR_PHY_DX8SL3IOCR_DXTXM_MASK 0x003FF800U +#define DDR_PHY_DX8SL3IOCR_DXTXM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL3IOCR_DXTXM_SHIFT 11 +#define DDR_PHY_DX8SL3IOCR_DXTXM_MASK 0x003FF800U -/*DX IO Receiver Mode*/ +/* +* DX IO Receiver Mode +*/ #undef DDR_PHY_DX8SL3IOCR_DXRXM_DEFVAL #undef DDR_PHY_DX8SL3IOCR_DXRXM_SHIFT #undef DDR_PHY_DX8SL3IOCR_DXRXM_MASK -#define DDR_PHY_DX8SL3IOCR_DXRXM_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL3IOCR_DXRXM_SHIFT 0 -#define DDR_PHY_DX8SL3IOCR_DXRXM_MASK 0x000007FFU +#define DDR_PHY_DX8SL3IOCR_DXRXM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL3IOCR_DXRXM_SHIFT 0 +#define DDR_PHY_DX8SL3IOCR_DXRXM_MASK 0x000007FFU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL4OSC_RESERVED_31_30_DEFVAL #undef DDR_PHY_DX8SL4OSC_RESERVED_31_30_SHIFT #undef DDR_PHY_DX8SL4OSC_RESERVED_31_30_MASK -#define DDR_PHY_DX8SL4OSC_RESERVED_31_30_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL4OSC_RESERVED_31_30_SHIFT 30 -#define DDR_PHY_DX8SL4OSC_RESERVED_31_30_MASK 0xC0000000U +#define DDR_PHY_DX8SL4OSC_RESERVED_31_30_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX8SL4OSC_RESERVED_31_30_MASK 0xC0000000U -/*Enable Clock Gating for DX ddr_clk*/ +/* +* Enable Clock Gating for DX ddr_clk +*/ #undef DDR_PHY_DX8SL4OSC_GATEDXRDCLK_DEFVAL #undef DDR_PHY_DX8SL4OSC_GATEDXRDCLK_SHIFT #undef DDR_PHY_DX8SL4OSC_GATEDXRDCLK_MASK -#define DDR_PHY_DX8SL4OSC_GATEDXRDCLK_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL4OSC_GATEDXRDCLK_SHIFT 28 -#define DDR_PHY_DX8SL4OSC_GATEDXRDCLK_MASK 0x30000000U +#define DDR_PHY_DX8SL4OSC_GATEDXRDCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_GATEDXRDCLK_SHIFT 28 +#define DDR_PHY_DX8SL4OSC_GATEDXRDCLK_MASK 0x30000000U -/*Enable Clock Gating for DX ctl_rd_clk*/ +/* +* Enable Clock Gating for DX ctl_rd_clk +*/ #undef DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_DEFVAL #undef DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_SHIFT #undef DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_MASK -#define DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_SHIFT 26 -#define DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_MASK 0x0C000000U +#define DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_SHIFT 26 +#define DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_MASK 0x0C000000U -/*Enable Clock Gating for DX ctl_clk*/ +/* +* Enable Clock Gating for DX ctl_clk +*/ #undef DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_DEFVAL #undef DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_SHIFT #undef DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_MASK -#define DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_SHIFT 24 -#define DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_MASK 0x03000000U +#define DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_SHIFT 24 +#define DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_MASK 0x03000000U -/*Selects the level to which clocks will be stalled when clock gating is enabled.*/ +/* +* Selects the level to which clocks will be stalled when clock gating is e + * nabled. +*/ #undef DDR_PHY_DX8SL4OSC_CLKLEVEL_DEFVAL #undef DDR_PHY_DX8SL4OSC_CLKLEVEL_SHIFT #undef DDR_PHY_DX8SL4OSC_CLKLEVEL_MASK -#define DDR_PHY_DX8SL4OSC_CLKLEVEL_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL4OSC_CLKLEVEL_SHIFT 22 -#define DDR_PHY_DX8SL4OSC_CLKLEVEL_MASK 0x00C00000U +#define DDR_PHY_DX8SL4OSC_CLKLEVEL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_CLKLEVEL_SHIFT 22 +#define DDR_PHY_DX8SL4OSC_CLKLEVEL_MASK 0x00C00000U -/*Loopback Mode*/ +/* +* Loopback Mode +*/ #undef DDR_PHY_DX8SL4OSC_LBMODE_DEFVAL #undef DDR_PHY_DX8SL4OSC_LBMODE_SHIFT #undef DDR_PHY_DX8SL4OSC_LBMODE_MASK -#define DDR_PHY_DX8SL4OSC_LBMODE_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL4OSC_LBMODE_SHIFT 21 -#define DDR_PHY_DX8SL4OSC_LBMODE_MASK 0x00200000U +#define DDR_PHY_DX8SL4OSC_LBMODE_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_LBMODE_SHIFT 21 +#define DDR_PHY_DX8SL4OSC_LBMODE_MASK 0x00200000U -/*Load GSDQS LCDL with 2x the calibrated GSDQSPRD value*/ +/* +* Load GSDQS LCDL with 2x the calibrated GSDQSPRD value +*/ #undef DDR_PHY_DX8SL4OSC_LBGSDQS_DEFVAL #undef DDR_PHY_DX8SL4OSC_LBGSDQS_SHIFT #undef DDR_PHY_DX8SL4OSC_LBGSDQS_MASK -#define DDR_PHY_DX8SL4OSC_LBGSDQS_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL4OSC_LBGSDQS_SHIFT 20 -#define DDR_PHY_DX8SL4OSC_LBGSDQS_MASK 0x00100000U +#define DDR_PHY_DX8SL4OSC_LBGSDQS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_LBGSDQS_SHIFT 20 +#define DDR_PHY_DX8SL4OSC_LBGSDQS_MASK 0x00100000U -/*Loopback DQS Gating*/ +/* +* Loopback DQS Gating +*/ #undef DDR_PHY_DX8SL4OSC_LBGDQS_DEFVAL #undef DDR_PHY_DX8SL4OSC_LBGDQS_SHIFT #undef DDR_PHY_DX8SL4OSC_LBGDQS_MASK -#define DDR_PHY_DX8SL4OSC_LBGDQS_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL4OSC_LBGDQS_SHIFT 18 -#define DDR_PHY_DX8SL4OSC_LBGDQS_MASK 0x000C0000U +#define DDR_PHY_DX8SL4OSC_LBGDQS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_LBGDQS_SHIFT 18 +#define DDR_PHY_DX8SL4OSC_LBGDQS_MASK 0x000C0000U -/*Loopback DQS Shift*/ +/* +* Loopback DQS Shift +*/ #undef DDR_PHY_DX8SL4OSC_LBDQSS_DEFVAL #undef DDR_PHY_DX8SL4OSC_LBDQSS_SHIFT #undef DDR_PHY_DX8SL4OSC_LBDQSS_MASK -#define DDR_PHY_DX8SL4OSC_LBDQSS_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL4OSC_LBDQSS_SHIFT 17 -#define DDR_PHY_DX8SL4OSC_LBDQSS_MASK 0x00020000U +#define DDR_PHY_DX8SL4OSC_LBDQSS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_LBDQSS_SHIFT 17 +#define DDR_PHY_DX8SL4OSC_LBDQSS_MASK 0x00020000U -/*PHY High-Speed Reset*/ +/* +* PHY High-Speed Reset +*/ #undef DDR_PHY_DX8SL4OSC_PHYHRST_DEFVAL #undef DDR_PHY_DX8SL4OSC_PHYHRST_SHIFT #undef DDR_PHY_DX8SL4OSC_PHYHRST_MASK -#define DDR_PHY_DX8SL4OSC_PHYHRST_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL4OSC_PHYHRST_SHIFT 16 -#define DDR_PHY_DX8SL4OSC_PHYHRST_MASK 0x00010000U +#define DDR_PHY_DX8SL4OSC_PHYHRST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_PHYHRST_SHIFT 16 +#define DDR_PHY_DX8SL4OSC_PHYHRST_MASK 0x00010000U -/*PHY FIFO Reset*/ +/* +* PHY FIFO Reset +*/ #undef DDR_PHY_DX8SL4OSC_PHYFRST_DEFVAL #undef DDR_PHY_DX8SL4OSC_PHYFRST_SHIFT #undef DDR_PHY_DX8SL4OSC_PHYFRST_MASK -#define DDR_PHY_DX8SL4OSC_PHYFRST_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL4OSC_PHYFRST_SHIFT 15 -#define DDR_PHY_DX8SL4OSC_PHYFRST_MASK 0x00008000U +#define DDR_PHY_DX8SL4OSC_PHYFRST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_PHYFRST_SHIFT 15 +#define DDR_PHY_DX8SL4OSC_PHYFRST_MASK 0x00008000U -/*Delay Line Test Start*/ +/* +* Delay Line Test Start +*/ #undef DDR_PHY_DX8SL4OSC_DLTST_DEFVAL #undef DDR_PHY_DX8SL4OSC_DLTST_SHIFT #undef DDR_PHY_DX8SL4OSC_DLTST_MASK -#define DDR_PHY_DX8SL4OSC_DLTST_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL4OSC_DLTST_SHIFT 14 -#define DDR_PHY_DX8SL4OSC_DLTST_MASK 0x00004000U +#define DDR_PHY_DX8SL4OSC_DLTST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_DLTST_SHIFT 14 +#define DDR_PHY_DX8SL4OSC_DLTST_MASK 0x00004000U -/*Delay Line Test Mode*/ +/* +* Delay Line Test Mode +*/ #undef DDR_PHY_DX8SL4OSC_DLTMODE_DEFVAL #undef DDR_PHY_DX8SL4OSC_DLTMODE_SHIFT #undef DDR_PHY_DX8SL4OSC_DLTMODE_MASK -#define DDR_PHY_DX8SL4OSC_DLTMODE_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL4OSC_DLTMODE_SHIFT 13 -#define DDR_PHY_DX8SL4OSC_DLTMODE_MASK 0x00002000U +#define DDR_PHY_DX8SL4OSC_DLTMODE_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_DLTMODE_SHIFT 13 +#define DDR_PHY_DX8SL4OSC_DLTMODE_MASK 0x00002000U -/*Reserved. Caution, do not write to this register field.*/ +/* +* Reserved. Caution, do not write to this register field. +*/ #undef DDR_PHY_DX8SL4OSC_RESERVED_12_11_DEFVAL #undef DDR_PHY_DX8SL4OSC_RESERVED_12_11_SHIFT #undef DDR_PHY_DX8SL4OSC_RESERVED_12_11_MASK -#define DDR_PHY_DX8SL4OSC_RESERVED_12_11_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL4OSC_RESERVED_12_11_SHIFT 11 -#define DDR_PHY_DX8SL4OSC_RESERVED_12_11_MASK 0x00001800U +#define DDR_PHY_DX8SL4OSC_RESERVED_12_11_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_RESERVED_12_11_SHIFT 11 +#define DDR_PHY_DX8SL4OSC_RESERVED_12_11_MASK 0x00001800U -/*Oscillator Mode Write-Data Delay Line Select*/ +/* +* Oscillator Mode Write-Data Delay Line Select +*/ #undef DDR_PHY_DX8SL4OSC_OSCWDDL_DEFVAL #undef DDR_PHY_DX8SL4OSC_OSCWDDL_SHIFT #undef DDR_PHY_DX8SL4OSC_OSCWDDL_MASK -#define DDR_PHY_DX8SL4OSC_OSCWDDL_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL4OSC_OSCWDDL_SHIFT 9 -#define DDR_PHY_DX8SL4OSC_OSCWDDL_MASK 0x00000600U +#define DDR_PHY_DX8SL4OSC_OSCWDDL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_OSCWDDL_SHIFT 9 +#define DDR_PHY_DX8SL4OSC_OSCWDDL_MASK 0x00000600U -/*Reserved. Caution, do not write to this register field.*/ +/* +* Reserved. Caution, do not write to this register field. +*/ #undef DDR_PHY_DX8SL4OSC_RESERVED_8_7_DEFVAL #undef DDR_PHY_DX8SL4OSC_RESERVED_8_7_SHIFT #undef DDR_PHY_DX8SL4OSC_RESERVED_8_7_MASK -#define DDR_PHY_DX8SL4OSC_RESERVED_8_7_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL4OSC_RESERVED_8_7_SHIFT 7 -#define DDR_PHY_DX8SL4OSC_RESERVED_8_7_MASK 0x00000180U +#define DDR_PHY_DX8SL4OSC_RESERVED_8_7_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_RESERVED_8_7_SHIFT 7 +#define DDR_PHY_DX8SL4OSC_RESERVED_8_7_MASK 0x00000180U -/*Oscillator Mode Write-Leveling Delay Line Select*/ +/* +* Oscillator Mode Write-Leveling Delay Line Select +*/ #undef DDR_PHY_DX8SL4OSC_OSCWDL_DEFVAL #undef DDR_PHY_DX8SL4OSC_OSCWDL_SHIFT #undef DDR_PHY_DX8SL4OSC_OSCWDL_MASK -#define DDR_PHY_DX8SL4OSC_OSCWDL_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL4OSC_OSCWDL_SHIFT 5 -#define DDR_PHY_DX8SL4OSC_OSCWDL_MASK 0x00000060U +#define DDR_PHY_DX8SL4OSC_OSCWDL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_OSCWDL_SHIFT 5 +#define DDR_PHY_DX8SL4OSC_OSCWDL_MASK 0x00000060U -/*Oscillator Mode Division*/ +/* +* Oscillator Mode Division +*/ #undef DDR_PHY_DX8SL4OSC_OSCDIV_DEFVAL #undef DDR_PHY_DX8SL4OSC_OSCDIV_SHIFT #undef DDR_PHY_DX8SL4OSC_OSCDIV_MASK -#define DDR_PHY_DX8SL4OSC_OSCDIV_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL4OSC_OSCDIV_SHIFT 1 -#define DDR_PHY_DX8SL4OSC_OSCDIV_MASK 0x0000001EU +#define DDR_PHY_DX8SL4OSC_OSCDIV_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_OSCDIV_SHIFT 1 +#define DDR_PHY_DX8SL4OSC_OSCDIV_MASK 0x0000001EU -/*Oscillator Enable*/ +/* +* Oscillator Enable +*/ #undef DDR_PHY_DX8SL4OSC_OSCEN_DEFVAL #undef DDR_PHY_DX8SL4OSC_OSCEN_SHIFT #undef DDR_PHY_DX8SL4OSC_OSCEN_MASK -#define DDR_PHY_DX8SL4OSC_OSCEN_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL4OSC_OSCEN_SHIFT 0 -#define DDR_PHY_DX8SL4OSC_OSCEN_MASK 0x00000001U +#define DDR_PHY_DX8SL4OSC_OSCEN_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_OSCEN_SHIFT 0 +#define DDR_PHY_DX8SL4OSC_OSCEN_MASK 0x00000001U -/*Reserved. Return zeroes on reads.*/ +/* +* PLL Bypass +*/ +#undef DDR_PHY_DX8SL4PLLCR0_PLLBYP_DEFVAL +#undef DDR_PHY_DX8SL4PLLCR0_PLLBYP_SHIFT +#undef DDR_PHY_DX8SL4PLLCR0_PLLBYP_MASK +#define DDR_PHY_DX8SL4PLLCR0_PLLBYP_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL4PLLCR0_PLLBYP_SHIFT 31 +#define DDR_PHY_DX8SL4PLLCR0_PLLBYP_MASK 0x80000000U + +/* +* PLL Reset +*/ +#undef DDR_PHY_DX8SL4PLLCR0_PLLRST_DEFVAL +#undef DDR_PHY_DX8SL4PLLCR0_PLLRST_SHIFT +#undef DDR_PHY_DX8SL4PLLCR0_PLLRST_MASK +#define DDR_PHY_DX8SL4PLLCR0_PLLRST_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL4PLLCR0_PLLRST_SHIFT 30 +#define DDR_PHY_DX8SL4PLLCR0_PLLRST_MASK 0x40000000U + +/* +* PLL Power Down +*/ +#undef DDR_PHY_DX8SL4PLLCR0_PLLPD_DEFVAL +#undef DDR_PHY_DX8SL4PLLCR0_PLLPD_SHIFT +#undef DDR_PHY_DX8SL4PLLCR0_PLLPD_MASK +#define DDR_PHY_DX8SL4PLLCR0_PLLPD_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL4PLLCR0_PLLPD_SHIFT 29 +#define DDR_PHY_DX8SL4PLLCR0_PLLPD_MASK 0x20000000U + +/* +* Reference Stop Mode +*/ +#undef DDR_PHY_DX8SL4PLLCR0_RSTOPM_DEFVAL +#undef DDR_PHY_DX8SL4PLLCR0_RSTOPM_SHIFT +#undef DDR_PHY_DX8SL4PLLCR0_RSTOPM_MASK +#define DDR_PHY_DX8SL4PLLCR0_RSTOPM_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL4PLLCR0_RSTOPM_SHIFT 28 +#define DDR_PHY_DX8SL4PLLCR0_RSTOPM_MASK 0x10000000U + +/* +* PLL Frequency Select +*/ +#undef DDR_PHY_DX8SL4PLLCR0_FRQSEL_DEFVAL +#undef DDR_PHY_DX8SL4PLLCR0_FRQSEL_SHIFT +#undef DDR_PHY_DX8SL4PLLCR0_FRQSEL_MASK +#define DDR_PHY_DX8SL4PLLCR0_FRQSEL_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL4PLLCR0_FRQSEL_SHIFT 24 +#define DDR_PHY_DX8SL4PLLCR0_FRQSEL_MASK 0x0F000000U + +/* +* Relock Mode +*/ +#undef DDR_PHY_DX8SL4PLLCR0_RLOCKM_DEFVAL +#undef DDR_PHY_DX8SL4PLLCR0_RLOCKM_SHIFT +#undef DDR_PHY_DX8SL4PLLCR0_RLOCKM_MASK +#define DDR_PHY_DX8SL4PLLCR0_RLOCKM_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL4PLLCR0_RLOCKM_SHIFT 23 +#define DDR_PHY_DX8SL4PLLCR0_RLOCKM_MASK 0x00800000U + +/* +* Charge Pump Proportional Current Control +*/ +#undef DDR_PHY_DX8SL4PLLCR0_CPPC_DEFVAL +#undef DDR_PHY_DX8SL4PLLCR0_CPPC_SHIFT +#undef DDR_PHY_DX8SL4PLLCR0_CPPC_MASK +#define DDR_PHY_DX8SL4PLLCR0_CPPC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL4PLLCR0_CPPC_SHIFT 17 +#define DDR_PHY_DX8SL4PLLCR0_CPPC_MASK 0x007E0000U + +/* +* Charge Pump Integrating Current Control +*/ +#undef DDR_PHY_DX8SL4PLLCR0_CPIC_DEFVAL +#undef DDR_PHY_DX8SL4PLLCR0_CPIC_SHIFT +#undef DDR_PHY_DX8SL4PLLCR0_CPIC_MASK +#define DDR_PHY_DX8SL4PLLCR0_CPIC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL4PLLCR0_CPIC_SHIFT 13 +#define DDR_PHY_DX8SL4PLLCR0_CPIC_MASK 0x0001E000U + +/* +* Gear Shift +*/ +#undef DDR_PHY_DX8SL4PLLCR0_GSHIFT_DEFVAL +#undef DDR_PHY_DX8SL4PLLCR0_GSHIFT_SHIFT +#undef DDR_PHY_DX8SL4PLLCR0_GSHIFT_MASK +#define DDR_PHY_DX8SL4PLLCR0_GSHIFT_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL4PLLCR0_GSHIFT_SHIFT 12 +#define DDR_PHY_DX8SL4PLLCR0_GSHIFT_MASK 0x00001000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL4PLLCR0_RESERVED_11_9_DEFVAL +#undef DDR_PHY_DX8SL4PLLCR0_RESERVED_11_9_SHIFT +#undef DDR_PHY_DX8SL4PLLCR0_RESERVED_11_9_MASK +#define DDR_PHY_DX8SL4PLLCR0_RESERVED_11_9_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL4PLLCR0_RESERVED_11_9_SHIFT 9 +#define DDR_PHY_DX8SL4PLLCR0_RESERVED_11_9_MASK 0x00000E00U + +/* +* Analog Test Enable (ATOEN) +*/ +#undef DDR_PHY_DX8SL4PLLCR0_ATOEN_DEFVAL +#undef DDR_PHY_DX8SL4PLLCR0_ATOEN_SHIFT +#undef DDR_PHY_DX8SL4PLLCR0_ATOEN_MASK +#define DDR_PHY_DX8SL4PLLCR0_ATOEN_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL4PLLCR0_ATOEN_SHIFT 8 +#define DDR_PHY_DX8SL4PLLCR0_ATOEN_MASK 0x00000100U + +/* +* Analog Test Control +*/ +#undef DDR_PHY_DX8SL4PLLCR0_ATC_DEFVAL +#undef DDR_PHY_DX8SL4PLLCR0_ATC_SHIFT +#undef DDR_PHY_DX8SL4PLLCR0_ATC_MASK +#define DDR_PHY_DX8SL4PLLCR0_ATC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL4PLLCR0_ATC_SHIFT 4 +#define DDR_PHY_DX8SL4PLLCR0_ATC_MASK 0x000000F0U + +/* +* Digital Test Control +*/ +#undef DDR_PHY_DX8SL4PLLCR0_DTC_DEFVAL +#undef DDR_PHY_DX8SL4PLLCR0_DTC_SHIFT +#undef DDR_PHY_DX8SL4PLLCR0_DTC_MASK +#define DDR_PHY_DX8SL4PLLCR0_DTC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL4PLLCR0_DTC_SHIFT 0 +#define DDR_PHY_DX8SL4PLLCR0_DTC_MASK 0x0000000FU + +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_DEFVAL #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_SHIFT #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_MASK -#define DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_SHIFT 25 -#define DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_MASK 0xFE000000U +#define DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_SHIFT 25 +#define DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_MASK 0xFE000000U -/*Read Path Rise-to-Rise Mode*/ +/* +* Read Path Rise-to-Rise Mode +*/ #undef DDR_PHY_DX8SL4DQSCTL_RRRMODE_DEFVAL #undef DDR_PHY_DX8SL4DQSCTL_RRRMODE_SHIFT #undef DDR_PHY_DX8SL4DQSCTL_RRRMODE_MASK -#define DDR_PHY_DX8SL4DQSCTL_RRRMODE_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL4DQSCTL_RRRMODE_SHIFT 24 -#define DDR_PHY_DX8SL4DQSCTL_RRRMODE_MASK 0x01000000U +#define DDR_PHY_DX8SL4DQSCTL_RRRMODE_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL4DQSCTL_RRRMODE_SHIFT 24 +#define DDR_PHY_DX8SL4DQSCTL_RRRMODE_MASK 0x01000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_DEFVAL #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_SHIFT #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_MASK -#define DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_SHIFT 22 -#define DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_MASK 0x00C00000U +#define DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_MASK 0x00C00000U -/*Write Path Rise-to-Rise Mode*/ +/* +* Write Path Rise-to-Rise Mode +*/ #undef DDR_PHY_DX8SL4DQSCTL_WRRMODE_DEFVAL #undef DDR_PHY_DX8SL4DQSCTL_WRRMODE_SHIFT #undef DDR_PHY_DX8SL4DQSCTL_WRRMODE_MASK -#define DDR_PHY_DX8SL4DQSCTL_WRRMODE_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL4DQSCTL_WRRMODE_SHIFT 21 -#define DDR_PHY_DX8SL4DQSCTL_WRRMODE_MASK 0x00200000U +#define DDR_PHY_DX8SL4DQSCTL_WRRMODE_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL4DQSCTL_WRRMODE_SHIFT 21 +#define DDR_PHY_DX8SL4DQSCTL_WRRMODE_MASK 0x00200000U -/*DQS Gate Extension*/ +/* +* DQS Gate Extension +*/ #undef DDR_PHY_DX8SL4DQSCTL_DQSGX_DEFVAL #undef DDR_PHY_DX8SL4DQSCTL_DQSGX_SHIFT #undef DDR_PHY_DX8SL4DQSCTL_DQSGX_MASK -#define DDR_PHY_DX8SL4DQSCTL_DQSGX_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL4DQSCTL_DQSGX_SHIFT 19 -#define DDR_PHY_DX8SL4DQSCTL_DQSGX_MASK 0x00180000U +#define DDR_PHY_DX8SL4DQSCTL_DQSGX_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL4DQSCTL_DQSGX_SHIFT 19 +#define DDR_PHY_DX8SL4DQSCTL_DQSGX_MASK 0x00180000U -/*Low Power PLL Power Down*/ +/* +* Low Power PLL Power Down +*/ #undef DDR_PHY_DX8SL4DQSCTL_LPPLLPD_DEFVAL #undef DDR_PHY_DX8SL4DQSCTL_LPPLLPD_SHIFT #undef DDR_PHY_DX8SL4DQSCTL_LPPLLPD_MASK -#define DDR_PHY_DX8SL4DQSCTL_LPPLLPD_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL4DQSCTL_LPPLLPD_SHIFT 18 -#define DDR_PHY_DX8SL4DQSCTL_LPPLLPD_MASK 0x00040000U +#define DDR_PHY_DX8SL4DQSCTL_LPPLLPD_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL4DQSCTL_LPPLLPD_SHIFT 18 +#define DDR_PHY_DX8SL4DQSCTL_LPPLLPD_MASK 0x00040000U -/*Low Power I/O Power Down*/ +/* +* Low Power I/O Power Down +*/ #undef DDR_PHY_DX8SL4DQSCTL_LPIOPD_DEFVAL #undef DDR_PHY_DX8SL4DQSCTL_LPIOPD_SHIFT #undef DDR_PHY_DX8SL4DQSCTL_LPIOPD_MASK -#define DDR_PHY_DX8SL4DQSCTL_LPIOPD_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL4DQSCTL_LPIOPD_SHIFT 17 -#define DDR_PHY_DX8SL4DQSCTL_LPIOPD_MASK 0x00020000U +#define DDR_PHY_DX8SL4DQSCTL_LPIOPD_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL4DQSCTL_LPIOPD_SHIFT 17 +#define DDR_PHY_DX8SL4DQSCTL_LPIOPD_MASK 0x00020000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_DEFVAL #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_SHIFT #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_MASK -#define DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_SHIFT 15 -#define DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_MASK 0x00018000U +#define DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_SHIFT 15 +#define DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_MASK 0x00018000U -/*QS Counter Enable*/ +/* +* QS Counter Enable +*/ #undef DDR_PHY_DX8SL4DQSCTL_QSCNTEN_DEFVAL #undef DDR_PHY_DX8SL4DQSCTL_QSCNTEN_SHIFT #undef DDR_PHY_DX8SL4DQSCTL_QSCNTEN_MASK -#define DDR_PHY_DX8SL4DQSCTL_QSCNTEN_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL4DQSCTL_QSCNTEN_SHIFT 14 -#define DDR_PHY_DX8SL4DQSCTL_QSCNTEN_MASK 0x00004000U +#define DDR_PHY_DX8SL4DQSCTL_QSCNTEN_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL4DQSCTL_QSCNTEN_SHIFT 14 +#define DDR_PHY_DX8SL4DQSCTL_QSCNTEN_MASK 0x00004000U -/*Unused DQ I/O Mode*/ +/* +* Unused DQ I/O Mode +*/ #undef DDR_PHY_DX8SL4DQSCTL_UDQIOM_DEFVAL #undef DDR_PHY_DX8SL4DQSCTL_UDQIOM_SHIFT #undef DDR_PHY_DX8SL4DQSCTL_UDQIOM_MASK -#define DDR_PHY_DX8SL4DQSCTL_UDQIOM_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL4DQSCTL_UDQIOM_SHIFT 13 -#define DDR_PHY_DX8SL4DQSCTL_UDQIOM_MASK 0x00002000U +#define DDR_PHY_DX8SL4DQSCTL_UDQIOM_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL4DQSCTL_UDQIOM_SHIFT 13 +#define DDR_PHY_DX8SL4DQSCTL_UDQIOM_MASK 0x00002000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_DEFVAL #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_SHIFT #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_MASK -#define DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_SHIFT 10 -#define DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_MASK 0x00001C00U +#define DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_SHIFT 10 +#define DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_MASK 0x00001C00U -/*Data Slew Rate*/ +/* +* Data Slew Rate +*/ #undef DDR_PHY_DX8SL4DQSCTL_DXSR_DEFVAL #undef DDR_PHY_DX8SL4DQSCTL_DXSR_SHIFT #undef DDR_PHY_DX8SL4DQSCTL_DXSR_MASK -#define DDR_PHY_DX8SL4DQSCTL_DXSR_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL4DQSCTL_DXSR_SHIFT 8 -#define DDR_PHY_DX8SL4DQSCTL_DXSR_MASK 0x00000300U +#define DDR_PHY_DX8SL4DQSCTL_DXSR_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL4DQSCTL_DXSR_SHIFT 8 +#define DDR_PHY_DX8SL4DQSCTL_DXSR_MASK 0x00000300U -/*DQS_N Resistor*/ +/* +* DQS_N Resistor +*/ #undef DDR_PHY_DX8SL4DQSCTL_DQSNRES_DEFVAL #undef DDR_PHY_DX8SL4DQSCTL_DQSNRES_SHIFT #undef DDR_PHY_DX8SL4DQSCTL_DQSNRES_MASK -#define DDR_PHY_DX8SL4DQSCTL_DQSNRES_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL4DQSCTL_DQSNRES_SHIFT 4 -#define DDR_PHY_DX8SL4DQSCTL_DQSNRES_MASK 0x000000F0U +#define DDR_PHY_DX8SL4DQSCTL_DQSNRES_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL4DQSCTL_DQSNRES_SHIFT 4 +#define DDR_PHY_DX8SL4DQSCTL_DQSNRES_MASK 0x000000F0U -/*DQS Resistor*/ +/* +* DQS Resistor +*/ #undef DDR_PHY_DX8SL4DQSCTL_DQSRES_DEFVAL #undef DDR_PHY_DX8SL4DQSCTL_DQSRES_SHIFT #undef DDR_PHY_DX8SL4DQSCTL_DQSRES_MASK -#define DDR_PHY_DX8SL4DQSCTL_DQSRES_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL4DQSCTL_DQSRES_SHIFT 0 -#define DDR_PHY_DX8SL4DQSCTL_DQSRES_MASK 0x0000000FU +#define DDR_PHY_DX8SL4DQSCTL_DQSRES_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL4DQSCTL_DQSRES_SHIFT 0 +#define DDR_PHY_DX8SL4DQSCTL_DQSRES_MASK 0x0000000FU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_DEFVAL #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_SHIFT #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_MASK -#define DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_SHIFT 24 -#define DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_MASK 0xFF000000U +#define DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_SHIFT 24 +#define DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_MASK 0xFF000000U -/*Configurable Read Data Enable*/ +/* +* Configurable Read Data Enable +*/ #undef DDR_PHY_DX8SL4DXCTL2_CRDEN_DEFVAL #undef DDR_PHY_DX8SL4DXCTL2_CRDEN_SHIFT #undef DDR_PHY_DX8SL4DXCTL2_CRDEN_MASK -#define DDR_PHY_DX8SL4DXCTL2_CRDEN_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL4DXCTL2_CRDEN_SHIFT 23 -#define DDR_PHY_DX8SL4DXCTL2_CRDEN_MASK 0x00800000U +#define DDR_PHY_DX8SL4DXCTL2_CRDEN_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_CRDEN_SHIFT 23 +#define DDR_PHY_DX8SL4DXCTL2_CRDEN_MASK 0x00800000U -/*OX Extension during Post-amble*/ +/* +* OX Extension during Post-amble +*/ #undef DDR_PHY_DX8SL4DXCTL2_POSOEX_DEFVAL #undef DDR_PHY_DX8SL4DXCTL2_POSOEX_SHIFT #undef DDR_PHY_DX8SL4DXCTL2_POSOEX_MASK -#define DDR_PHY_DX8SL4DXCTL2_POSOEX_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL4DXCTL2_POSOEX_SHIFT 20 -#define DDR_PHY_DX8SL4DXCTL2_POSOEX_MASK 0x00700000U +#define DDR_PHY_DX8SL4DXCTL2_POSOEX_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_POSOEX_SHIFT 20 +#define DDR_PHY_DX8SL4DXCTL2_POSOEX_MASK 0x00700000U -/*OE Extension during Pre-amble*/ +/* +* OE Extension during Pre-amble +*/ #undef DDR_PHY_DX8SL4DXCTL2_PREOEX_DEFVAL #undef DDR_PHY_DX8SL4DXCTL2_PREOEX_SHIFT #undef DDR_PHY_DX8SL4DXCTL2_PREOEX_MASK -#define DDR_PHY_DX8SL4DXCTL2_PREOEX_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL4DXCTL2_PREOEX_SHIFT 18 -#define DDR_PHY_DX8SL4DXCTL2_PREOEX_MASK 0x000C0000U +#define DDR_PHY_DX8SL4DXCTL2_PREOEX_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_PREOEX_SHIFT 18 +#define DDR_PHY_DX8SL4DXCTL2_PREOEX_MASK 0x000C0000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_17_DEFVAL #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_17_SHIFT #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_17_MASK -#define DDR_PHY_DX8SL4DXCTL2_RESERVED_17_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL4DXCTL2_RESERVED_17_SHIFT 17 -#define DDR_PHY_DX8SL4DXCTL2_RESERVED_17_MASK 0x00020000U +#define DDR_PHY_DX8SL4DXCTL2_RESERVED_17_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_RESERVED_17_SHIFT 17 +#define DDR_PHY_DX8SL4DXCTL2_RESERVED_17_MASK 0x00020000U -/*I/O Assisted Gate Select*/ +/* +* I/O Assisted Gate Select +*/ #undef DDR_PHY_DX8SL4DXCTL2_IOAG_DEFVAL #undef DDR_PHY_DX8SL4DXCTL2_IOAG_SHIFT #undef DDR_PHY_DX8SL4DXCTL2_IOAG_MASK -#define DDR_PHY_DX8SL4DXCTL2_IOAG_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL4DXCTL2_IOAG_SHIFT 16 -#define DDR_PHY_DX8SL4DXCTL2_IOAG_MASK 0x00010000U +#define DDR_PHY_DX8SL4DXCTL2_IOAG_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_IOAG_SHIFT 16 +#define DDR_PHY_DX8SL4DXCTL2_IOAG_MASK 0x00010000U -/*I/O Loopback Select*/ +/* +* I/O Loopback Select +*/ #undef DDR_PHY_DX8SL4DXCTL2_IOLB_DEFVAL #undef DDR_PHY_DX8SL4DXCTL2_IOLB_SHIFT #undef DDR_PHY_DX8SL4DXCTL2_IOLB_MASK -#define DDR_PHY_DX8SL4DXCTL2_IOLB_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL4DXCTL2_IOLB_SHIFT 15 -#define DDR_PHY_DX8SL4DXCTL2_IOLB_MASK 0x00008000U +#define DDR_PHY_DX8SL4DXCTL2_IOLB_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_IOLB_SHIFT 15 +#define DDR_PHY_DX8SL4DXCTL2_IOLB_MASK 0x00008000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_DEFVAL #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_SHIFT #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_MASK -#define DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_SHIFT 13 -#define DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_MASK 0x00006000U +#define DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_SHIFT 13 +#define DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_MASK 0x00006000U -/*Low Power Wakeup Threshold*/ +/* +* Low Power Wakeup Threshold +*/ #undef DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_DEFVAL #undef DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_SHIFT #undef DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_MASK -#define DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_SHIFT 9 -#define DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_MASK 0x00001E00U +#define DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_SHIFT 9 +#define DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_MASK 0x00001E00U -/*Read Data Bus Inversion Enable*/ +/* +* Read Data Bus Inversion Enable +*/ #undef DDR_PHY_DX8SL4DXCTL2_RDBI_DEFVAL #undef DDR_PHY_DX8SL4DXCTL2_RDBI_SHIFT #undef DDR_PHY_DX8SL4DXCTL2_RDBI_MASK -#define DDR_PHY_DX8SL4DXCTL2_RDBI_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL4DXCTL2_RDBI_SHIFT 8 -#define DDR_PHY_DX8SL4DXCTL2_RDBI_MASK 0x00000100U +#define DDR_PHY_DX8SL4DXCTL2_RDBI_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_RDBI_SHIFT 8 +#define DDR_PHY_DX8SL4DXCTL2_RDBI_MASK 0x00000100U -/*Write Data Bus Inversion Enable*/ +/* +* Write Data Bus Inversion Enable +*/ #undef DDR_PHY_DX8SL4DXCTL2_WDBI_DEFVAL #undef DDR_PHY_DX8SL4DXCTL2_WDBI_SHIFT #undef DDR_PHY_DX8SL4DXCTL2_WDBI_MASK -#define DDR_PHY_DX8SL4DXCTL2_WDBI_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL4DXCTL2_WDBI_SHIFT 7 -#define DDR_PHY_DX8SL4DXCTL2_WDBI_MASK 0x00000080U +#define DDR_PHY_DX8SL4DXCTL2_WDBI_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_WDBI_SHIFT 7 +#define DDR_PHY_DX8SL4DXCTL2_WDBI_MASK 0x00000080U -/*PUB Read FIFO Bypass*/ +/* +* PUB Read FIFO Bypass +*/ #undef DDR_PHY_DX8SL4DXCTL2_PRFBYP_DEFVAL #undef DDR_PHY_DX8SL4DXCTL2_PRFBYP_SHIFT #undef DDR_PHY_DX8SL4DXCTL2_PRFBYP_MASK -#define DDR_PHY_DX8SL4DXCTL2_PRFBYP_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL4DXCTL2_PRFBYP_SHIFT 6 -#define DDR_PHY_DX8SL4DXCTL2_PRFBYP_MASK 0x00000040U +#define DDR_PHY_DX8SL4DXCTL2_PRFBYP_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_PRFBYP_SHIFT 6 +#define DDR_PHY_DX8SL4DXCTL2_PRFBYP_MASK 0x00000040U -/*DATX8 Receive FIFO Read Mode*/ +/* +* DATX8 Receive FIFO Read Mode +*/ #undef DDR_PHY_DX8SL4DXCTL2_RDMODE_DEFVAL #undef DDR_PHY_DX8SL4DXCTL2_RDMODE_SHIFT #undef DDR_PHY_DX8SL4DXCTL2_RDMODE_MASK -#define DDR_PHY_DX8SL4DXCTL2_RDMODE_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL4DXCTL2_RDMODE_SHIFT 4 -#define DDR_PHY_DX8SL4DXCTL2_RDMODE_MASK 0x00000030U +#define DDR_PHY_DX8SL4DXCTL2_RDMODE_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_RDMODE_SHIFT 4 +#define DDR_PHY_DX8SL4DXCTL2_RDMODE_MASK 0x00000030U -/*Disables the Read FIFO Reset*/ +/* +* Disables the Read FIFO Reset +*/ #undef DDR_PHY_DX8SL4DXCTL2_DISRST_DEFVAL #undef DDR_PHY_DX8SL4DXCTL2_DISRST_SHIFT #undef DDR_PHY_DX8SL4DXCTL2_DISRST_MASK -#define DDR_PHY_DX8SL4DXCTL2_DISRST_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL4DXCTL2_DISRST_SHIFT 3 -#define DDR_PHY_DX8SL4DXCTL2_DISRST_MASK 0x00000008U +#define DDR_PHY_DX8SL4DXCTL2_DISRST_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_DISRST_SHIFT 3 +#define DDR_PHY_DX8SL4DXCTL2_DISRST_MASK 0x00000008U -/*Read DQS Gate I/O Loopback*/ +/* +* Read DQS Gate I/O Loopback +*/ #undef DDR_PHY_DX8SL4DXCTL2_DQSGLB_DEFVAL #undef DDR_PHY_DX8SL4DXCTL2_DQSGLB_SHIFT #undef DDR_PHY_DX8SL4DXCTL2_DQSGLB_MASK -#define DDR_PHY_DX8SL4DXCTL2_DQSGLB_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL4DXCTL2_DQSGLB_SHIFT 1 -#define DDR_PHY_DX8SL4DXCTL2_DQSGLB_MASK 0x00000006U +#define DDR_PHY_DX8SL4DXCTL2_DQSGLB_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_DQSGLB_SHIFT 1 +#define DDR_PHY_DX8SL4DXCTL2_DQSGLB_MASK 0x00000006U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_0_DEFVAL #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_0_SHIFT #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_0_MASK -#define DDR_PHY_DX8SL4DXCTL2_RESERVED_0_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL4DXCTL2_RESERVED_0_SHIFT 0 -#define DDR_PHY_DX8SL4DXCTL2_RESERVED_0_MASK 0x00000001U +#define DDR_PHY_DX8SL4DXCTL2_RESERVED_0_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_RESERVED_0_SHIFT 0 +#define DDR_PHY_DX8SL4DXCTL2_RESERVED_0_MASK 0x00000001U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL4IOCR_RESERVED_31_DEFVAL #undef DDR_PHY_DX8SL4IOCR_RESERVED_31_SHIFT #undef DDR_PHY_DX8SL4IOCR_RESERVED_31_MASK -#define DDR_PHY_DX8SL4IOCR_RESERVED_31_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL4IOCR_RESERVED_31_SHIFT 31 -#define DDR_PHY_DX8SL4IOCR_RESERVED_31_MASK 0x80000000U +#define DDR_PHY_DX8SL4IOCR_RESERVED_31_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL4IOCR_RESERVED_31_SHIFT 31 +#define DDR_PHY_DX8SL4IOCR_RESERVED_31_MASK 0x80000000U -/*PVREF_DAC REFSEL range select*/ +/* +* PVREF_DAC REFSEL range select +*/ #undef DDR_PHY_DX8SL4IOCR_DXDACRANGE_DEFVAL #undef DDR_PHY_DX8SL4IOCR_DXDACRANGE_SHIFT #undef DDR_PHY_DX8SL4IOCR_DXDACRANGE_MASK -#define DDR_PHY_DX8SL4IOCR_DXDACRANGE_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL4IOCR_DXDACRANGE_SHIFT 28 -#define DDR_PHY_DX8SL4IOCR_DXDACRANGE_MASK 0x70000000U +#define DDR_PHY_DX8SL4IOCR_DXDACRANGE_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL4IOCR_DXDACRANGE_SHIFT 28 +#define DDR_PHY_DX8SL4IOCR_DXDACRANGE_MASK 0x70000000U -/*IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring*/ +/* +* IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring +*/ #undef DDR_PHY_DX8SL4IOCR_DXVREFIOM_DEFVAL #undef DDR_PHY_DX8SL4IOCR_DXVREFIOM_SHIFT #undef DDR_PHY_DX8SL4IOCR_DXVREFIOM_MASK -#define DDR_PHY_DX8SL4IOCR_DXVREFIOM_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL4IOCR_DXVREFIOM_SHIFT 25 -#define DDR_PHY_DX8SL4IOCR_DXVREFIOM_MASK 0x0E000000U +#define DDR_PHY_DX8SL4IOCR_DXVREFIOM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL4IOCR_DXVREFIOM_SHIFT 25 +#define DDR_PHY_DX8SL4IOCR_DXVREFIOM_MASK 0x0E000000U -/*DX IO Mode*/ +/* +* DX IO Mode +*/ #undef DDR_PHY_DX8SL4IOCR_DXIOM_DEFVAL #undef DDR_PHY_DX8SL4IOCR_DXIOM_SHIFT #undef DDR_PHY_DX8SL4IOCR_DXIOM_MASK -#define DDR_PHY_DX8SL4IOCR_DXIOM_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL4IOCR_DXIOM_SHIFT 22 -#define DDR_PHY_DX8SL4IOCR_DXIOM_MASK 0x01C00000U +#define DDR_PHY_DX8SL4IOCR_DXIOM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL4IOCR_DXIOM_SHIFT 22 +#define DDR_PHY_DX8SL4IOCR_DXIOM_MASK 0x01C00000U -/*DX IO Transmitter Mode*/ +/* +* DX IO Transmitter Mode +*/ #undef DDR_PHY_DX8SL4IOCR_DXTXM_DEFVAL #undef DDR_PHY_DX8SL4IOCR_DXTXM_SHIFT #undef DDR_PHY_DX8SL4IOCR_DXTXM_MASK -#define DDR_PHY_DX8SL4IOCR_DXTXM_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL4IOCR_DXTXM_SHIFT 11 -#define DDR_PHY_DX8SL4IOCR_DXTXM_MASK 0x003FF800U +#define DDR_PHY_DX8SL4IOCR_DXTXM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL4IOCR_DXTXM_SHIFT 11 +#define DDR_PHY_DX8SL4IOCR_DXTXM_MASK 0x003FF800U -/*DX IO Receiver Mode*/ +/* +* DX IO Receiver Mode +*/ #undef DDR_PHY_DX8SL4IOCR_DXRXM_DEFVAL #undef DDR_PHY_DX8SL4IOCR_DXRXM_SHIFT #undef DDR_PHY_DX8SL4IOCR_DXRXM_MASK -#define DDR_PHY_DX8SL4IOCR_DXRXM_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL4IOCR_DXRXM_SHIFT 0 -#define DDR_PHY_DX8SL4IOCR_DXRXM_MASK 0x000007FFU +#define DDR_PHY_DX8SL4IOCR_DXRXM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL4IOCR_DXRXM_SHIFT 0 +#define DDR_PHY_DX8SL4IOCR_DXRXM_MASK 0x000007FFU -/*Reserved. Return zeroes on reads.*/ +/* +* PLL Bypass +*/ +#undef DDR_PHY_DX8SLBPLLCR0_PLLBYP_DEFVAL +#undef DDR_PHY_DX8SLBPLLCR0_PLLBYP_SHIFT +#undef DDR_PHY_DX8SLBPLLCR0_PLLBYP_MASK +#define DDR_PHY_DX8SLBPLLCR0_PLLBYP_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBPLLCR0_PLLBYP_SHIFT 31 +#define DDR_PHY_DX8SLBPLLCR0_PLLBYP_MASK 0x80000000U + +/* +* PLL Reset +*/ +#undef DDR_PHY_DX8SLBPLLCR0_PLLRST_DEFVAL +#undef DDR_PHY_DX8SLBPLLCR0_PLLRST_SHIFT +#undef DDR_PHY_DX8SLBPLLCR0_PLLRST_MASK +#define DDR_PHY_DX8SLBPLLCR0_PLLRST_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBPLLCR0_PLLRST_SHIFT 30 +#define DDR_PHY_DX8SLBPLLCR0_PLLRST_MASK 0x40000000U + +/* +* PLL Power Down +*/ +#undef DDR_PHY_DX8SLBPLLCR0_PLLPD_DEFVAL +#undef DDR_PHY_DX8SLBPLLCR0_PLLPD_SHIFT +#undef DDR_PHY_DX8SLBPLLCR0_PLLPD_MASK +#define DDR_PHY_DX8SLBPLLCR0_PLLPD_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBPLLCR0_PLLPD_SHIFT 29 +#define DDR_PHY_DX8SLBPLLCR0_PLLPD_MASK 0x20000000U + +/* +* Reference Stop Mode +*/ +#undef DDR_PHY_DX8SLBPLLCR0_RSTOPM_DEFVAL +#undef DDR_PHY_DX8SLBPLLCR0_RSTOPM_SHIFT +#undef DDR_PHY_DX8SLBPLLCR0_RSTOPM_MASK +#define DDR_PHY_DX8SLBPLLCR0_RSTOPM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBPLLCR0_RSTOPM_SHIFT 28 +#define DDR_PHY_DX8SLBPLLCR0_RSTOPM_MASK 0x10000000U + +/* +* PLL Frequency Select +*/ +#undef DDR_PHY_DX8SLBPLLCR0_FRQSEL_DEFVAL +#undef DDR_PHY_DX8SLBPLLCR0_FRQSEL_SHIFT +#undef DDR_PHY_DX8SLBPLLCR0_FRQSEL_MASK +#define DDR_PHY_DX8SLBPLLCR0_FRQSEL_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBPLLCR0_FRQSEL_SHIFT 24 +#define DDR_PHY_DX8SLBPLLCR0_FRQSEL_MASK 0x0F000000U + +/* +* Relock Mode +*/ +#undef DDR_PHY_DX8SLBPLLCR0_RLOCKM_DEFVAL +#undef DDR_PHY_DX8SLBPLLCR0_RLOCKM_SHIFT +#undef DDR_PHY_DX8SLBPLLCR0_RLOCKM_MASK +#define DDR_PHY_DX8SLBPLLCR0_RLOCKM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBPLLCR0_RLOCKM_SHIFT 23 +#define DDR_PHY_DX8SLBPLLCR0_RLOCKM_MASK 0x00800000U + +/* +* Charge Pump Proportional Current Control +*/ +#undef DDR_PHY_DX8SLBPLLCR0_CPPC_DEFVAL +#undef DDR_PHY_DX8SLBPLLCR0_CPPC_SHIFT +#undef DDR_PHY_DX8SLBPLLCR0_CPPC_MASK +#define DDR_PHY_DX8SLBPLLCR0_CPPC_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBPLLCR0_CPPC_SHIFT 17 +#define DDR_PHY_DX8SLBPLLCR0_CPPC_MASK 0x007E0000U + +/* +* Charge Pump Integrating Current Control +*/ +#undef DDR_PHY_DX8SLBPLLCR0_CPIC_DEFVAL +#undef DDR_PHY_DX8SLBPLLCR0_CPIC_SHIFT +#undef DDR_PHY_DX8SLBPLLCR0_CPIC_MASK +#define DDR_PHY_DX8SLBPLLCR0_CPIC_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBPLLCR0_CPIC_SHIFT 13 +#define DDR_PHY_DX8SLBPLLCR0_CPIC_MASK 0x0001E000U + +/* +* Gear Shift +*/ +#undef DDR_PHY_DX8SLBPLLCR0_GSHIFT_DEFVAL +#undef DDR_PHY_DX8SLBPLLCR0_GSHIFT_SHIFT +#undef DDR_PHY_DX8SLBPLLCR0_GSHIFT_MASK +#define DDR_PHY_DX8SLBPLLCR0_GSHIFT_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBPLLCR0_GSHIFT_SHIFT 12 +#define DDR_PHY_DX8SLBPLLCR0_GSHIFT_MASK 0x00001000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SLBPLLCR0_RESERVED_11_9_DEFVAL +#undef DDR_PHY_DX8SLBPLLCR0_RESERVED_11_9_SHIFT +#undef DDR_PHY_DX8SLBPLLCR0_RESERVED_11_9_MASK +#define DDR_PHY_DX8SLBPLLCR0_RESERVED_11_9_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBPLLCR0_RESERVED_11_9_SHIFT 9 +#define DDR_PHY_DX8SLBPLLCR0_RESERVED_11_9_MASK 0x00000E00U + +/* +* Analog Test Enable (ATOEN) +*/ +#undef DDR_PHY_DX8SLBPLLCR0_ATOEN_DEFVAL +#undef DDR_PHY_DX8SLBPLLCR0_ATOEN_SHIFT +#undef DDR_PHY_DX8SLBPLLCR0_ATOEN_MASK +#define DDR_PHY_DX8SLBPLLCR0_ATOEN_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBPLLCR0_ATOEN_SHIFT 8 +#define DDR_PHY_DX8SLBPLLCR0_ATOEN_MASK 0x00000100U + +/* +* Analog Test Control +*/ +#undef DDR_PHY_DX8SLBPLLCR0_ATC_DEFVAL +#undef DDR_PHY_DX8SLBPLLCR0_ATC_SHIFT +#undef DDR_PHY_DX8SLBPLLCR0_ATC_MASK +#define DDR_PHY_DX8SLBPLLCR0_ATC_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBPLLCR0_ATC_SHIFT 4 +#define DDR_PHY_DX8SLBPLLCR0_ATC_MASK 0x000000F0U + +/* +* Digital Test Control +*/ +#undef DDR_PHY_DX8SLBPLLCR0_DTC_DEFVAL +#undef DDR_PHY_DX8SLBPLLCR0_DTC_SHIFT +#undef DDR_PHY_DX8SLBPLLCR0_DTC_MASK +#define DDR_PHY_DX8SLBPLLCR0_DTC_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBPLLCR0_DTC_SHIFT 0 +#define DDR_PHY_DX8SLBPLLCR0_DTC_MASK 0x0000000FU + +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_DEFVAL #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_SHIFT #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_MASK -#define DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_DEFVAL 0x00000000 -#define DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_SHIFT 25 -#define DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_MASK 0xFE000000U +#define DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_SHIFT 25 +#define DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_MASK 0xFE000000U -/*Read Path Rise-to-Rise Mode*/ +/* +* Read Path Rise-to-Rise Mode +*/ #undef DDR_PHY_DX8SLBDQSCTL_RRRMODE_DEFVAL #undef DDR_PHY_DX8SLBDQSCTL_RRRMODE_SHIFT #undef DDR_PHY_DX8SLBDQSCTL_RRRMODE_MASK -#define DDR_PHY_DX8SLBDQSCTL_RRRMODE_DEFVAL 0x00000000 -#define DDR_PHY_DX8SLBDQSCTL_RRRMODE_SHIFT 24 -#define DDR_PHY_DX8SLBDQSCTL_RRRMODE_MASK 0x01000000U +#define DDR_PHY_DX8SLBDQSCTL_RRRMODE_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBDQSCTL_RRRMODE_SHIFT 24 +#define DDR_PHY_DX8SLBDQSCTL_RRRMODE_MASK 0x01000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_DEFVAL #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_SHIFT #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_MASK -#define DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_DEFVAL 0x00000000 -#define DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_SHIFT 22 -#define DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_MASK 0x00C00000U +#define DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_MASK 0x00C00000U -/*Write Path Rise-to-Rise Mode*/ +/* +* Write Path Rise-to-Rise Mode +*/ #undef DDR_PHY_DX8SLBDQSCTL_WRRMODE_DEFVAL #undef DDR_PHY_DX8SLBDQSCTL_WRRMODE_SHIFT #undef DDR_PHY_DX8SLBDQSCTL_WRRMODE_MASK -#define DDR_PHY_DX8SLBDQSCTL_WRRMODE_DEFVAL 0x00000000 -#define DDR_PHY_DX8SLBDQSCTL_WRRMODE_SHIFT 21 -#define DDR_PHY_DX8SLBDQSCTL_WRRMODE_MASK 0x00200000U +#define DDR_PHY_DX8SLBDQSCTL_WRRMODE_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBDQSCTL_WRRMODE_SHIFT 21 +#define DDR_PHY_DX8SLBDQSCTL_WRRMODE_MASK 0x00200000U -/*DQS Gate Extension*/ +/* +* DQS Gate Extension +*/ #undef DDR_PHY_DX8SLBDQSCTL_DQSGX_DEFVAL #undef DDR_PHY_DX8SLBDQSCTL_DQSGX_SHIFT #undef DDR_PHY_DX8SLBDQSCTL_DQSGX_MASK -#define DDR_PHY_DX8SLBDQSCTL_DQSGX_DEFVAL 0x00000000 -#define DDR_PHY_DX8SLBDQSCTL_DQSGX_SHIFT 19 -#define DDR_PHY_DX8SLBDQSCTL_DQSGX_MASK 0x00180000U +#define DDR_PHY_DX8SLBDQSCTL_DQSGX_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBDQSCTL_DQSGX_SHIFT 19 +#define DDR_PHY_DX8SLBDQSCTL_DQSGX_MASK 0x00180000U -/*Low Power PLL Power Down*/ +/* +* Low Power PLL Power Down +*/ #undef DDR_PHY_DX8SLBDQSCTL_LPPLLPD_DEFVAL #undef DDR_PHY_DX8SLBDQSCTL_LPPLLPD_SHIFT #undef DDR_PHY_DX8SLBDQSCTL_LPPLLPD_MASK -#define DDR_PHY_DX8SLBDQSCTL_LPPLLPD_DEFVAL 0x00000000 -#define DDR_PHY_DX8SLBDQSCTL_LPPLLPD_SHIFT 18 -#define DDR_PHY_DX8SLBDQSCTL_LPPLLPD_MASK 0x00040000U +#define DDR_PHY_DX8SLBDQSCTL_LPPLLPD_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBDQSCTL_LPPLLPD_SHIFT 18 +#define DDR_PHY_DX8SLBDQSCTL_LPPLLPD_MASK 0x00040000U -/*Low Power I/O Power Down*/ +/* +* Low Power I/O Power Down +*/ #undef DDR_PHY_DX8SLBDQSCTL_LPIOPD_DEFVAL #undef DDR_PHY_DX8SLBDQSCTL_LPIOPD_SHIFT #undef DDR_PHY_DX8SLBDQSCTL_LPIOPD_MASK -#define DDR_PHY_DX8SLBDQSCTL_LPIOPD_DEFVAL 0x00000000 -#define DDR_PHY_DX8SLBDQSCTL_LPIOPD_SHIFT 17 -#define DDR_PHY_DX8SLBDQSCTL_LPIOPD_MASK 0x00020000U +#define DDR_PHY_DX8SLBDQSCTL_LPIOPD_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBDQSCTL_LPIOPD_SHIFT 17 +#define DDR_PHY_DX8SLBDQSCTL_LPIOPD_MASK 0x00020000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_DEFVAL #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_SHIFT #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_MASK -#define DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_DEFVAL 0x00000000 -#define DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_SHIFT 15 -#define DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_MASK 0x00018000U +#define DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_SHIFT 15 +#define DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_MASK 0x00018000U -/*QS Counter Enable*/ +/* +* QS Counter Enable +*/ #undef DDR_PHY_DX8SLBDQSCTL_QSCNTEN_DEFVAL #undef DDR_PHY_DX8SLBDQSCTL_QSCNTEN_SHIFT #undef DDR_PHY_DX8SLBDQSCTL_QSCNTEN_MASK -#define DDR_PHY_DX8SLBDQSCTL_QSCNTEN_DEFVAL 0x00000000 -#define DDR_PHY_DX8SLBDQSCTL_QSCNTEN_SHIFT 14 -#define DDR_PHY_DX8SLBDQSCTL_QSCNTEN_MASK 0x00004000U +#define DDR_PHY_DX8SLBDQSCTL_QSCNTEN_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBDQSCTL_QSCNTEN_SHIFT 14 +#define DDR_PHY_DX8SLBDQSCTL_QSCNTEN_MASK 0x00004000U -/*Unused DQ I/O Mode*/ +/* +* Unused DQ I/O Mode +*/ #undef DDR_PHY_DX8SLBDQSCTL_UDQIOM_DEFVAL #undef DDR_PHY_DX8SLBDQSCTL_UDQIOM_SHIFT #undef DDR_PHY_DX8SLBDQSCTL_UDQIOM_MASK -#define DDR_PHY_DX8SLBDQSCTL_UDQIOM_DEFVAL 0x00000000 -#define DDR_PHY_DX8SLBDQSCTL_UDQIOM_SHIFT 13 -#define DDR_PHY_DX8SLBDQSCTL_UDQIOM_MASK 0x00002000U +#define DDR_PHY_DX8SLBDQSCTL_UDQIOM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBDQSCTL_UDQIOM_SHIFT 13 +#define DDR_PHY_DX8SLBDQSCTL_UDQIOM_MASK 0x00002000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_DEFVAL #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_SHIFT #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_MASK -#define DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_DEFVAL 0x00000000 -#define DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_SHIFT 10 -#define DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_MASK 0x00001C00U +#define DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_SHIFT 10 +#define DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_MASK 0x00001C00U -/*Data Slew Rate*/ +/* +* Data Slew Rate +*/ #undef DDR_PHY_DX8SLBDQSCTL_DXSR_DEFVAL #undef DDR_PHY_DX8SLBDQSCTL_DXSR_SHIFT #undef DDR_PHY_DX8SLBDQSCTL_DXSR_MASK -#define DDR_PHY_DX8SLBDQSCTL_DXSR_DEFVAL 0x00000000 -#define DDR_PHY_DX8SLBDQSCTL_DXSR_SHIFT 8 -#define DDR_PHY_DX8SLBDQSCTL_DXSR_MASK 0x00000300U +#define DDR_PHY_DX8SLBDQSCTL_DXSR_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBDQSCTL_DXSR_SHIFT 8 +#define DDR_PHY_DX8SLBDQSCTL_DXSR_MASK 0x00000300U -/*DQS# Resistor*/ +/* +* DQS# Resistor +*/ #undef DDR_PHY_DX8SLBDQSCTL_DQSNRES_DEFVAL #undef DDR_PHY_DX8SLBDQSCTL_DQSNRES_SHIFT #undef DDR_PHY_DX8SLBDQSCTL_DQSNRES_MASK -#define DDR_PHY_DX8SLBDQSCTL_DQSNRES_DEFVAL 0x00000000 -#define DDR_PHY_DX8SLBDQSCTL_DQSNRES_SHIFT 4 -#define DDR_PHY_DX8SLBDQSCTL_DQSNRES_MASK 0x000000F0U +#define DDR_PHY_DX8SLBDQSCTL_DQSNRES_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBDQSCTL_DQSNRES_SHIFT 4 +#define DDR_PHY_DX8SLBDQSCTL_DQSNRES_MASK 0x000000F0U -/*DQS Resistor*/ +/* +* DQS Resistor +*/ #undef DDR_PHY_DX8SLBDQSCTL_DQSRES_DEFVAL #undef DDR_PHY_DX8SLBDQSCTL_DQSRES_SHIFT #undef DDR_PHY_DX8SLBDQSCTL_DQSRES_MASK -#define DDR_PHY_DX8SLBDQSCTL_DQSRES_DEFVAL 0x00000000 -#define DDR_PHY_DX8SLBDQSCTL_DQSRES_SHIFT 0 -#define DDR_PHY_DX8SLBDQSCTL_DQSRES_MASK 0x0000000FU - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_PIR_RESERVED_31_DEFVAL -#undef DDR_PHY_PIR_RESERVED_31_SHIFT -#undef DDR_PHY_PIR_RESERVED_31_MASK -#define DDR_PHY_PIR_RESERVED_31_DEFVAL 0x00000000 -#define DDR_PHY_PIR_RESERVED_31_SHIFT 31 -#define DDR_PHY_PIR_RESERVED_31_MASK 0x80000000U - -/*Impedance Calibration Bypass*/ -#undef DDR_PHY_PIR_ZCALBYP_DEFVAL -#undef DDR_PHY_PIR_ZCALBYP_SHIFT -#undef DDR_PHY_PIR_ZCALBYP_MASK -#define DDR_PHY_PIR_ZCALBYP_DEFVAL 0x00000000 -#define DDR_PHY_PIR_ZCALBYP_SHIFT 30 -#define DDR_PHY_PIR_ZCALBYP_MASK 0x40000000U - -/*Digital Delay Line (DDL) Calibration Pause*/ -#undef DDR_PHY_PIR_DCALPSE_DEFVAL -#undef DDR_PHY_PIR_DCALPSE_SHIFT -#undef DDR_PHY_PIR_DCALPSE_MASK -#define DDR_PHY_PIR_DCALPSE_DEFVAL 0x00000000 -#define DDR_PHY_PIR_DCALPSE_SHIFT 29 -#define DDR_PHY_PIR_DCALPSE_MASK 0x20000000U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_PIR_RESERVED_28_21_DEFVAL -#undef DDR_PHY_PIR_RESERVED_28_21_SHIFT -#undef DDR_PHY_PIR_RESERVED_28_21_MASK -#define DDR_PHY_PIR_RESERVED_28_21_DEFVAL 0x00000000 -#define DDR_PHY_PIR_RESERVED_28_21_SHIFT 21 -#define DDR_PHY_PIR_RESERVED_28_21_MASK 0x1FE00000U - -/*Write DQS2DQ Training*/ -#undef DDR_PHY_PIR_DQS2DQ_DEFVAL -#undef DDR_PHY_PIR_DQS2DQ_SHIFT -#undef DDR_PHY_PIR_DQS2DQ_MASK -#define DDR_PHY_PIR_DQS2DQ_DEFVAL 0x00000000 -#define DDR_PHY_PIR_DQS2DQ_SHIFT 20 -#define DDR_PHY_PIR_DQS2DQ_MASK 0x00100000U - -/*RDIMM Initialization*/ -#undef DDR_PHY_PIR_RDIMMINIT_DEFVAL -#undef DDR_PHY_PIR_RDIMMINIT_SHIFT -#undef DDR_PHY_PIR_RDIMMINIT_MASK -#define DDR_PHY_PIR_RDIMMINIT_DEFVAL 0x00000000 -#define DDR_PHY_PIR_RDIMMINIT_SHIFT 19 -#define DDR_PHY_PIR_RDIMMINIT_MASK 0x00080000U - -/*Controller DRAM Initialization*/ -#undef DDR_PHY_PIR_CTLDINIT_DEFVAL -#undef DDR_PHY_PIR_CTLDINIT_SHIFT -#undef DDR_PHY_PIR_CTLDINIT_MASK -#define DDR_PHY_PIR_CTLDINIT_DEFVAL 0x00000000 -#define DDR_PHY_PIR_CTLDINIT_SHIFT 18 -#define DDR_PHY_PIR_CTLDINIT_MASK 0x00040000U - -/*VREF Training*/ -#undef DDR_PHY_PIR_VREF_DEFVAL -#undef DDR_PHY_PIR_VREF_SHIFT -#undef DDR_PHY_PIR_VREF_MASK -#define DDR_PHY_PIR_VREF_DEFVAL 0x00000000 -#define DDR_PHY_PIR_VREF_SHIFT 17 -#define DDR_PHY_PIR_VREF_MASK 0x00020000U - -/*Static Read Training*/ -#undef DDR_PHY_PIR_SRD_DEFVAL -#undef DDR_PHY_PIR_SRD_SHIFT -#undef DDR_PHY_PIR_SRD_MASK -#define DDR_PHY_PIR_SRD_DEFVAL 0x00000000 -#define DDR_PHY_PIR_SRD_SHIFT 16 -#define DDR_PHY_PIR_SRD_MASK 0x00010000U - -/*Write Data Eye Training*/ -#undef DDR_PHY_PIR_WREYE_DEFVAL -#undef DDR_PHY_PIR_WREYE_SHIFT -#undef DDR_PHY_PIR_WREYE_MASK -#define DDR_PHY_PIR_WREYE_DEFVAL 0x00000000 -#define DDR_PHY_PIR_WREYE_SHIFT 15 -#define DDR_PHY_PIR_WREYE_MASK 0x00008000U - -/*Read Data Eye Training*/ -#undef DDR_PHY_PIR_RDEYE_DEFVAL -#undef DDR_PHY_PIR_RDEYE_SHIFT -#undef DDR_PHY_PIR_RDEYE_MASK -#define DDR_PHY_PIR_RDEYE_DEFVAL 0x00000000 -#define DDR_PHY_PIR_RDEYE_SHIFT 14 -#define DDR_PHY_PIR_RDEYE_MASK 0x00004000U - -/*Write Data Bit Deskew*/ -#undef DDR_PHY_PIR_WRDSKW_DEFVAL -#undef DDR_PHY_PIR_WRDSKW_SHIFT -#undef DDR_PHY_PIR_WRDSKW_MASK -#define DDR_PHY_PIR_WRDSKW_DEFVAL 0x00000000 -#define DDR_PHY_PIR_WRDSKW_SHIFT 13 -#define DDR_PHY_PIR_WRDSKW_MASK 0x00002000U - -/*Read Data Bit Deskew*/ -#undef DDR_PHY_PIR_RDDSKW_DEFVAL -#undef DDR_PHY_PIR_RDDSKW_SHIFT -#undef DDR_PHY_PIR_RDDSKW_MASK -#define DDR_PHY_PIR_RDDSKW_DEFVAL 0x00000000 -#define DDR_PHY_PIR_RDDSKW_SHIFT 12 -#define DDR_PHY_PIR_RDDSKW_MASK 0x00001000U - -/*Write Leveling Adjust*/ -#undef DDR_PHY_PIR_WLADJ_DEFVAL -#undef DDR_PHY_PIR_WLADJ_SHIFT -#undef DDR_PHY_PIR_WLADJ_MASK -#define DDR_PHY_PIR_WLADJ_DEFVAL 0x00000000 -#define DDR_PHY_PIR_WLADJ_SHIFT 11 -#define DDR_PHY_PIR_WLADJ_MASK 0x00000800U - -/*Read DQS Gate Training*/ -#undef DDR_PHY_PIR_QSGATE_DEFVAL -#undef DDR_PHY_PIR_QSGATE_SHIFT -#undef DDR_PHY_PIR_QSGATE_MASK -#define DDR_PHY_PIR_QSGATE_DEFVAL 0x00000000 -#define DDR_PHY_PIR_QSGATE_SHIFT 10 -#define DDR_PHY_PIR_QSGATE_MASK 0x00000400U - -/*Write Leveling*/ -#undef DDR_PHY_PIR_WL_DEFVAL -#undef DDR_PHY_PIR_WL_SHIFT -#undef DDR_PHY_PIR_WL_MASK -#define DDR_PHY_PIR_WL_DEFVAL 0x00000000 -#define DDR_PHY_PIR_WL_SHIFT 9 -#define DDR_PHY_PIR_WL_MASK 0x00000200U - -/*DRAM Initialization*/ -#undef DDR_PHY_PIR_DRAMINIT_DEFVAL -#undef DDR_PHY_PIR_DRAMINIT_SHIFT -#undef DDR_PHY_PIR_DRAMINIT_MASK -#define DDR_PHY_PIR_DRAMINIT_DEFVAL 0x00000000 -#define DDR_PHY_PIR_DRAMINIT_SHIFT 8 -#define DDR_PHY_PIR_DRAMINIT_MASK 0x00000100U - -/*DRAM Reset (DDR3/DDR4/LPDDR4 Only)*/ -#undef DDR_PHY_PIR_DRAMRST_DEFVAL -#undef DDR_PHY_PIR_DRAMRST_SHIFT -#undef DDR_PHY_PIR_DRAMRST_MASK -#define DDR_PHY_PIR_DRAMRST_DEFVAL 0x00000000 -#define DDR_PHY_PIR_DRAMRST_SHIFT 7 -#define DDR_PHY_PIR_DRAMRST_MASK 0x00000080U - -/*PHY Reset*/ -#undef DDR_PHY_PIR_PHYRST_DEFVAL -#undef DDR_PHY_PIR_PHYRST_SHIFT -#undef DDR_PHY_PIR_PHYRST_MASK -#define DDR_PHY_PIR_PHYRST_DEFVAL 0x00000000 -#define DDR_PHY_PIR_PHYRST_SHIFT 6 -#define DDR_PHY_PIR_PHYRST_MASK 0x00000040U - -/*Digital Delay Line (DDL) Calibration*/ -#undef DDR_PHY_PIR_DCAL_DEFVAL -#undef DDR_PHY_PIR_DCAL_SHIFT -#undef DDR_PHY_PIR_DCAL_MASK -#define DDR_PHY_PIR_DCAL_DEFVAL 0x00000000 -#define DDR_PHY_PIR_DCAL_SHIFT 5 -#define DDR_PHY_PIR_DCAL_MASK 0x00000020U - -/*PLL Initialiazation*/ -#undef DDR_PHY_PIR_PLLINIT_DEFVAL -#undef DDR_PHY_PIR_PLLINIT_SHIFT -#undef DDR_PHY_PIR_PLLINIT_MASK -#define DDR_PHY_PIR_PLLINIT_DEFVAL 0x00000000 -#define DDR_PHY_PIR_PLLINIT_SHIFT 4 -#define DDR_PHY_PIR_PLLINIT_MASK 0x00000010U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_PIR_RESERVED_3_DEFVAL -#undef DDR_PHY_PIR_RESERVED_3_SHIFT -#undef DDR_PHY_PIR_RESERVED_3_MASK -#define DDR_PHY_PIR_RESERVED_3_DEFVAL 0x00000000 -#define DDR_PHY_PIR_RESERVED_3_SHIFT 3 -#define DDR_PHY_PIR_RESERVED_3_MASK 0x00000008U - -/*CA Training*/ -#undef DDR_PHY_PIR_CA_DEFVAL -#undef DDR_PHY_PIR_CA_SHIFT -#undef DDR_PHY_PIR_CA_MASK -#define DDR_PHY_PIR_CA_DEFVAL 0x00000000 -#define DDR_PHY_PIR_CA_SHIFT 2 -#define DDR_PHY_PIR_CA_MASK 0x00000004U - -/*Impedance Calibration*/ -#undef DDR_PHY_PIR_ZCAL_DEFVAL -#undef DDR_PHY_PIR_ZCAL_SHIFT -#undef DDR_PHY_PIR_ZCAL_MASK -#define DDR_PHY_PIR_ZCAL_DEFVAL 0x00000000 -#define DDR_PHY_PIR_ZCAL_SHIFT 1 -#define DDR_PHY_PIR_ZCAL_MASK 0x00000002U - -/*Initialization Trigger*/ -#undef DDR_PHY_PIR_INIT_DEFVAL -#undef DDR_PHY_PIR_INIT_SHIFT -#undef DDR_PHY_PIR_INIT_MASK -#define DDR_PHY_PIR_INIT_DEFVAL 0x00000000 -#define DDR_PHY_PIR_INIT_SHIFT 0 -#define DDR_PHY_PIR_INIT_MASK 0x00000001U +#define DDR_PHY_DX8SLBDQSCTL_DQSRES_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBDQSCTL_DQSRES_SHIFT 0 +#define DDR_PHY_DX8SLBDQSCTL_DQSRES_MASK 0x0000000FU #undef IOU_SLCR_MIO_PIN_0_OFFSET #define IOU_SLCR_MIO_PIN_0_OFFSET 0XFF180000 #undef IOU_SLCR_MIO_PIN_1_OFFSET @@ -17120,7308 +21593,9482 @@ #undef IOU_SLCR_MIO_LOOPBACK_OFFSET #define IOU_SLCR_MIO_LOOPBACK_OFFSET 0XFF180200 -/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out- (QSPI Clock)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out- + * (QSPI Clock) +*/ #undef IOU_SLCR_MIO_PIN_0_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_0_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_0_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_0_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_0_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_0_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_0_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_0_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_0_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_0_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_0_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_0_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_0_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_0_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_0_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_0_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_0_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_0_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[0]- (Test Scan Port) = test_scan, Outp - t, test_scan_out[0]- (Test Scan Port) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[0]- (Test Scan Port) = test_scan, Output, test_scan_out[0 + * ]- (Test Scan Port) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_0_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_0_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_0_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_0_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_0_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_0_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_0_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_0_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_0_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[0]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[0]- (GPIO bank 0) 1= can - , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa - ) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Cloc - ) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_ - lk- (Trace Port Clock)*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[0]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[0]- (GPIO bank 0) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG + * TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sc + * lk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Out + * put, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_c + * lk- (Trace Port Clock) +*/ #undef IOU_SLCR_MIO_PIN_0_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_0_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_0_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_0_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_0_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_0_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_0_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_0_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_0_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (QSPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Data - us)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (Q + * SPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Databus) +*/ #undef IOU_SLCR_MIO_PIN_1_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_1_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_1_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_1_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_1_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_1_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_1_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_1_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_1_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_1_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_1_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_1_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_1_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_1_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_1_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_1_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_1_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_1_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[1]- (Test Scan Port) = test_scan, Outp - t, test_scan_out[1]- (Test Scan Port) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[1]- (Test Scan Port) = test_scan, Output, test_scan_out[1 + * ]- (Test Scan Port) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_1_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_1_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_1_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_1_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_1_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_1_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_1_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_1_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_1_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[1]- (GPIO bank 0) 1= can - , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal - 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_o - t- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control - Signal)*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[1]- (GPIO bank 0) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG + * TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc3, Ou + * tput, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART + * receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control + * Signal) +*/ #undef IOU_SLCR_MIO_PIN_1_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_1_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_1_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_1_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_1_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_1_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_1_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_1_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_1_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI + * Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus) +*/ #undef IOU_SLCR_MIO_PIN_2_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_2_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_2_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_2_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_2_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_2_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_2_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_2_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_2_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_2_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_2_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_2_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_2_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_2_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_2_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_2_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_2_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_2_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[2]- (Test Scan Port) = test_scan, Outp - t, test_scan_out[2]- (Test Scan Port) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[2]- (Test Scan Port) = test_scan, Output, test_scan_out[2 + * ]- (Test Scan Port) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_2_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_2_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_2_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_2_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_2_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_2_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_2_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_2_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_2_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[2]- (GPIO bank 0) 1= can - , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal - 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc2, Input, ttc2_clk_in - (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[0]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[2]- (GPIO bank 0) 1= can0, Input, can0_phy_ + * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + * , Output, i2c0_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTAG + * TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc2, I + * nput, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver se + * rial input) 7= trace, Output, tracedq[0]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_2_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_2_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_2_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_2_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_2_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_2_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_2_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_2_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_2_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI + * Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus) +*/ #undef IOU_SLCR_MIO_PIN_3_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_3_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_3_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_3_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_3_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_3_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_3_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_3_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_3_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_3_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_3_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_3_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_3_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_3_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_3_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_3_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_3_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_3_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[3]- (Test Scan Port) = test_scan, Outp - t, test_scan_out[3]- (Test Scan Port) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[3]- (Test Scan Port) = test_scan, Output, test_scan_out[3 + * ]- (Test Scan Port) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_3_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_3_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_3_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_3_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_3_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_3_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_3_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_3_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_3_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[3]- (GPIO bank 0) 1= can - , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa - ) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0 - - (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial - output) 7= trace, Output, tracedq[1]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[3]- (GPIO bank 0) 1= can0, Output, can0_phy + * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + * 0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG + * TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output + * , spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- + * (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial + * output) 7= trace, Output, tracedq[1]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_3_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_3_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_3_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_3_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_3_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_3_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_3_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_3_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_3_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- (QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Data - us)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- ( + * QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Databus) +*/ #undef IOU_SLCR_MIO_PIN_4_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_4_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_4_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_4_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_4_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_4_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_4_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_4_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_4_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_4_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_4_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_4_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_4_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_4_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_4_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_4_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_4_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_4_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[4]- (Test Scan Port) = test_scan, Outp - t, test_scan_out[4]- (Test Scan Port) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[4]- (Test Scan Port) = test_scan, Output, test_scan_out[4 + * ]- (Test Scan Port) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_4_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_4_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_4_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_4_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_4_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_4_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_4_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_4_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_4_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[4]- (GPIO bank 0) 1= can - , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa - ) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_s - - (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, - utput, tracedq[2]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[4]- (GPIO bank 0) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Wa + * tch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi + * 0, Output, spi0_so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Cloc + * k) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, O + * utput, tracedq[2]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_4_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_4_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_4_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_4_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_4_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_4_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_4_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_4_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_4_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out- (QSPI Slave Select)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out- + * (QSPI Slave Select) +*/ #undef IOU_SLCR_MIO_PIN_5_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_5_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_5_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_5_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_5_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_5_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_5_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_5_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_5_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_5_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_5_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_5_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_5_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_5_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_5_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_5_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_5_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_5_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[5]- (Test Scan Port) = test_scan, Outp - t, test_scan_out[5]- (Test Scan Port) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[5]- (Test Scan Port) = test_scan, Output, test_scan_out[5 + * ]- (Test Scan Port) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_5_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_5_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_5_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_5_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_5_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_5_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_5_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_5_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_5_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[5]- (GPIO bank 0) 1= can - , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal - 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi0 - si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7 - trace, Output, tracedq[3]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[5]- (GPIO bank 0) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (W + * atch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= + * spi0, Input, spi0_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC + * Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= + * trace, Output, tracedq[3]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_5_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_5_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_5_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_5_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_5_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_5_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_5_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_5_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_5_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_clk_for_lpbk- (QSPI Clock to be fed-back)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_clk_for_l + * pbk- (QSPI Clock to be fed-back) +*/ #undef IOU_SLCR_MIO_PIN_6_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_6_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_6_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_6_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_6_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_6_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_6_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_6_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_6_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_6_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_6_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_6_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_6_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_6_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_6_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_6_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_6_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_6_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[6]- (Test Scan Port) = test_scan, Outp - t, test_scan_out[6]- (Test Scan Port) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[6]- (Test Scan Port) = test_scan, Output, test_scan_out[6 + * ]- (Test Scan Port) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_6_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_6_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_6_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_6_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_6_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_6_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_6_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_6_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_6_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[6]- (GPIO bank 0) 1= can - , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal - 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1 - sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, - Output, tracedq[4]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[6]- (GPIO bank 0) 1= can0, Input, can0_phy_ + * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + * , Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Wat + * ch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= s + * pi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TT + * C Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, + * Output, tracedq[4]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_6_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_6_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_6_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_6_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_6_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_6_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_6_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_6_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_6_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out_upper- (QSPI Slave Select upper)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out_ + * upper- (QSPI Slave Select upper) +*/ #undef IOU_SLCR_MIO_PIN_7_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_7_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_7_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_7_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_7_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_7_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_7_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_7_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_7_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_7_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_7_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_7_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_7_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_7_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_7_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_7_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_7_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_7_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[7]- (Test Scan Port) = test_scan, Outp - t, test_scan_out[7]- (Test Scan Port) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[7]- (Test Scan Port) = test_scan, Output, test_scan_out[7 + * ]- (Test Scan Port) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_7_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_7_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_7_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_7_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_7_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_7_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_7_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_7_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_7_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[7]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[7]- (GPIO bank 0) 1= can - , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa - ) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= - tc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, - racedq[5]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[7]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[7]- (GPIO bank 0) 1= can0, Output, can0_phy + * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + * 0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- ( + * Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Ma + * ster Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua + * 0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, t + * racedq[5]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_7_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_7_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_7_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_7_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_7_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_7_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_7_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_7_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_7_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[0]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe - [0]- (QSPI Upper Databus)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[0 + * ]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[0]- (QSPI Upper D + * atabus) +*/ #undef IOU_SLCR_MIO_PIN_8_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_8_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_8_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_8_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_8_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_8_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_8_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_8_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_8_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_8_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_8_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_8_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_8_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_8_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_8_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_8_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_8_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_8_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[8]- (Test Scan Port) = test_scan, Outp - t, test_scan_out[8]- (Test Scan Port) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[8]- (Test Scan Port) = test_scan, Output, test_scan_out[8 + * ]- (Test Scan Port) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_8_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_8_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_8_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_8_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_8_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_8_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_8_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_8_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_8_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[8]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[8]- (GPIO bank 0) 1= can - , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa - ) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc - , Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Tr - ce Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[8]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[8]- (GPIO bank 0) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Wa + * tch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Maste + * r Selects) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_ + * txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Tra + * ce Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_8_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_8_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_8_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_8_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_8_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_8_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_8_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_8_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_8_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[1]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe - [1]- (QSPI Upper Databus)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[1 + * ]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[1]- (QSPI Upper D + * atabus) +*/ #undef IOU_SLCR_MIO_PIN_9_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_9_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_9_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_9_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_9_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_9_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_9_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_9_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_9_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NAND chip enable)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NA + * ND chip enable) +*/ #undef IOU_SLCR_MIO_PIN_9_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_9_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_9_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_9_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_9_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_9_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_9_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_9_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_9_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[9]- (Test Scan Port) = test_scan, Outp - t, test_scan_out[9]- (Test Scan Port) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[9]- (Test Scan Port) = test_scan, Output, test_scan_out[9 + * ]- (Test Scan Port) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_9_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_9_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_9_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_9_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_9_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_9_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_9_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_9_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_9_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[9]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[9]- (GPIO bank 0) 1= can - , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal - 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, - utput, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (U - RT receiver serial input) 7= trace, Output, tracedq[7]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[9]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[9]- (GPIO bank 0) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (W + * atch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master S + * elects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc3, + * Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UA + * RT receiver serial input) 7= trace, Output, tracedq[7]- (Trace Port Data + * bus) +*/ #undef IOU_SLCR_MIO_PIN_9_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_9_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_9_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_9_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_9_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_9_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_9_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_9_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_9_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[2]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe - [2]- (QSPI Upper Databus)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[2 + * ]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[2]- (QSPI Upper D + * atabus) +*/ #undef IOU_SLCR_MIO_PIN_10_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_10_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_10_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_10_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_10_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_10_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_10_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_10_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_10_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (NAND Ready/Busy)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (N + * AND Ready/Busy) +*/ #undef IOU_SLCR_MIO_PIN_10_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_10_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_10_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_10_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_10_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_10_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_10_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_10_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_10_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[10]- (Test Scan Port) = test_scan, Out - ut, test_scan_out[10]- (Test Scan Port) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[10]- (Test Scan Port) = test_scan, Output, test_scan_out[ + * 10]- (Test Scan Port) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_10_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_10_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_10_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_10_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_10_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_10_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_10_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_10_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_10_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[10]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[10]- (GPIO bank 0) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_ - o- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outp - t, tracedq[8]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[10]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[10]- (GPIO bank 0) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= sp + * i1, Output, spi1_so- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clo + * ck) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outpu + * t, tracedq[8]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_10_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_10_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_10_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_10_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_10_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_10_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_10_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_10_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_10_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[3]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe - [3]- (QSPI Upper Databus)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[3 + * ]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[3]- (QSPI Upper D + * atabus) +*/ #undef IOU_SLCR_MIO_PIN_11_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_11_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_11_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_11_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_11_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_11_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_11_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_11_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_11_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (NAND Ready/Busy)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (N + * AND Ready/Busy) +*/ #undef IOU_SLCR_MIO_PIN_11_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_11_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_11_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_11_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_11_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_11_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_11_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_11_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_11_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[11]- (Test Scan Port) = test_scan, Out - ut, test_scan_out[11]- (Test Scan Port) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[11]- (Test Scan Port) = test_scan, Output, test_scan_out[ + * 11]- (Test Scan Port) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_11_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_11_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_11_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_11_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_11_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_11_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_11_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_11_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_11_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s - i1_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o - tput) 7= trace, Output, tracedq[9]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) + * 4= spi1, Input, spi1_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- ( + * TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial ou + * tput) 7= trace, Output, tracedq[9]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_11_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_11_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_11_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_11_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_11_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_11_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_11_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_11_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_11_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out_upper- (QSPI Upper Clock)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out_ + * upper- (QSPI Upper Clock) +*/ #undef IOU_SLCR_MIO_PIN_12_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_12_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_12_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_12_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_12_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_12_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_12_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_12_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_12_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NAND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe - */ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NA + * ND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe) +*/ #undef IOU_SLCR_MIO_PIN_12_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_12_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_12_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_12_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_12_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_12_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_12_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_12_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_12_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[12]- (Test Scan Port) = test_scan, Out - ut, test_scan_out[12]- (Test Scan Port) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[12]- (Test Scan Port) = test_scan, Output, test_scan_out[ + * 12]- (Test Scan Port) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_12_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_12_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_12_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_12_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_12_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_12_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_12_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_12_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_12_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[12]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[12]- (GPIO bank 0) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Cl - ck) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trac - dq[10]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[12]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[12]- (GPIO bank 0) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJT + * AG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_ + * sclk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, O + * utput, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace + * dq[10]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_12_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_12_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_12_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_12_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_12_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_12_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_12_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_12_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_12_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_13_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_13_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_13_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_13_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_13_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_13_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_13_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_13_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_13_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[0]- (NAND chip enable)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[0]- (NA + * ND chip enable) +*/ #undef IOU_SLCR_MIO_PIN_13_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_13_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_13_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_13_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_13_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_13_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_13_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_13_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_13_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8 - bit Data bus) 2= test_scan, Input, test_scan_in[13]- (Test Scan Port) = test_scan, Output, test_scan_out[13]- (Test Scan Port - 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[13]- (Test Scan Port) = test_scan, Output, + * test_scan_out[13]- (Test Scan Port) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_13_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_13_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_13_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_13_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_13_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_13_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_13_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_13_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_13_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[13]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[13]- (GPIO bank 0) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave - out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq[11]- (Trace Port Dat - bus)*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[13]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[13]- (GPIO bank 0) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTA + * G TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, + * Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UAR + * T receiver serial input) 7= trace, Output, tracedq[11]- (Trace Port Data + * bus) +*/ #undef IOU_SLCR_MIO_PIN_13_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_13_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_13_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_13_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_13_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_13_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_13_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_13_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_13_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_14_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_14_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_14_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_14_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_14_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_14_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_14_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_14_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_14_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_cle- (NAND Command Latch Enable)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_cle- (NAND + * Command Latch Enable) +*/ #undef IOU_SLCR_MIO_PIN_14_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_14_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_14_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_14_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_14_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_14_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_14_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_14_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_14_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8 - bit Data bus) 2= test_scan, Input, test_scan_in[14]- (Test Scan Port) = test_scan, Output, test_scan_out[14]- (Test Scan Port - 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[14]- (Test Scan Port) = test_scan, Output, + * test_scan_out[14]- (Test Scan Port) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_14_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_14_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_14_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_14_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_14_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_14_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_14_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_14_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_14_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, Input, ttc0_clk_ - n- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJT + * AG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, + * Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver + * serial input) 7= trace, Output, tracedq[12]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_14_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_14_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_14_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_14_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_14_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_14_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_14_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_14_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_14_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_15_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_15_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_15_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_15_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_15_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_15_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_15_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_15_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_15_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ale- (NAND Address Latch Enable)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ale- (NAND + * Address Latch Enable) +*/ #undef IOU_SLCR_MIO_PIN_15_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_15_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_15_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_15_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_15_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_15_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_15_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_15_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_15_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8 - bit Data bus) 2= test_scan, Input, test_scan_in[15]- (Test Scan Port) = test_scan, Output, test_scan_out[15]- (Test Scan Port - 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[15]- (Test Scan Port) = test_scan, Output, + * test_scan_out[15]- (Test Scan Port) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_15_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_15_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_15_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_15_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_15_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_15_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_15_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_15_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_15_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[15]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[15]- (GPIO bank 0) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out - 0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter seri - l output) 7= trace, Output, tracedq[13]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[15]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[15]- (GPIO bank 0) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJT + * AG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Outp + * ut, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_ou + * t- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter seria + * l output) 7= trace, Output, tracedq[13]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_15_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_15_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_15_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_15_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_15_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_15_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_15_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_15_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_15_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_16_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_16_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_16_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_16_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_16_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_16_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_16_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_16_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_16_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[0]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[0]- (NAND - ata Bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[0]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[0]- (NAND Data Bus) +*/ #undef IOU_SLCR_MIO_PIN_16_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_16_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_16_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_16_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_16_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_16_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_16_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_16_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_16_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8 - bit Data bus) 2= test_scan, Input, test_scan_in[16]- (Test Scan Port) = test_scan, Output, test_scan_out[16]- (Test Scan Port - 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[16]- (Test Scan Port) = test_scan, Output, + * test_scan_out[16]- (Test Scan Port) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_16_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_16_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_16_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_16_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_16_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_16_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_16_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_16_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_16_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[16]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[16]- (GPIO bank 0) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0 - so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace - Output, tracedq[14]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[16]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[16]- (GPIO bank 0) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= s + * pi0, Output, spi0_so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Cl + * ock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, + * Output, tracedq[14]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_16_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_16_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_16_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_16_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_16_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_16_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_16_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_16_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_16_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_17_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_17_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_17_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_17_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_17_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_17_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_17_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_17_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_17_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[1]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[1]- (NAND - ata Bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[1]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[1]- (NAND Data Bus) +*/ #undef IOU_SLCR_MIO_PIN_17_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_17_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_17_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_17_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_17_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_17_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_17_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_17_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_17_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8 - bit Data bus) 2= test_scan, Input, test_scan_in[17]- (Test Scan Port) = test_scan, Output, test_scan_out[17]- (Test Scan Port - 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[17]- (Test Scan Port) = test_scan, Output, + * test_scan_out[17]- (Test Scan Port) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_17_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_17_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_17_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_17_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_17_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_17_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_17_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_17_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_17_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[17]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[17]- (GPIO bank 0) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, sp - 0_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) - 7= trace, Output, tracedq[15]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[17]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[17]- (GPIO bank 0) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4 + * = spi0, Input, spi0_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (T + * TC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) + * 7= trace, Output, tracedq[15]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_17_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_17_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_17_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_17_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_17_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_17_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_17_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_17_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_17_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_18_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_18_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_18_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_18_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_18_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_18_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_18_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_18_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_18_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[2]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[2]- (NAND - ata Bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[2]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[2]- (NAND Data Bus) +*/ #undef IOU_SLCR_MIO_PIN_18_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_18_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_18_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_18_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_18_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_18_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_18_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_18_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_18_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8 - bit Data bus) 2= test_scan, Input, test_scan_in[18]- (Test Scan Port) = test_scan, Output, test_scan_out[18]- (Test Scan Port - 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[18]- (Test Scan Port) = test_scan, Output, + * test_scan_out[18]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU + * Ext Tamper) +*/ #undef IOU_SLCR_MIO_PIN_18_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_18_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_18_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_18_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_18_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_18_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_18_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_18_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_18_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[18]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[18]- (GPIO bank 0) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_ - o- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[18]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[18]- (GPIO bank 0) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= sp + * i1, Output, spi1_so- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clo + * ck) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used +*/ #undef IOU_SLCR_MIO_PIN_18_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_18_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_18_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_18_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_18_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_18_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_18_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_18_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_18_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_19_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_19_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_19_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_19_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_19_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_19_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_19_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_19_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_19_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[3]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[3]- (NAND - ata Bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[3]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[3]- (NAND Data Bus) +*/ #undef IOU_SLCR_MIO_PIN_19_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_19_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_19_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_19_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_19_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_19_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_19_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_19_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_19_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8 - bit Data bus) 2= test_scan, Input, test_scan_in[19]- (Test Scan Port) = test_scan, Output, test_scan_out[19]- (Test Scan Port - 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[19]- (Test Scan Port) = test_scan, Output, + * test_scan_out[19]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU + * Ext Tamper) +*/ #undef IOU_SLCR_MIO_PIN_19_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_19_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_19_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_19_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_19_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_19_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_19_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_19_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_19_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[19]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[19]- (GPIO bank 0) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5 - ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[19]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[19]- (GPIO bank 0) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI + * Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= + * ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used +*/ #undef IOU_SLCR_MIO_PIN_19_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_19_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_19_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_19_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_19_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_19_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_19_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_19_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_19_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_20_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_20_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_20_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_20_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_20_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_20_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_20_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_20_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_20_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[4]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[4]- (NAND - ata Bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[4]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[4]- (NAND Data Bus) +*/ #undef IOU_SLCR_MIO_PIN_20_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_20_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_20_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_20_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_20_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_20_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_20_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_20_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_20_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8 - bit Data bus) 2= test_scan, Input, test_scan_in[20]- (Test Scan Port) = test_scan, Output, test_scan_out[20]- (Test Scan Port - 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[20]- (Test Scan Port) = test_scan, Output, + * test_scan_out[20]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU + * Ext Tamper) +*/ #undef IOU_SLCR_MIO_PIN_20_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_20_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_20_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_20_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_20_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_20_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_20_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_20_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_20_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[20]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[20]- (GPIO bank 0) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= t - c1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Used*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[20]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[20]- (GPIO bank 0) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Mas + * ter Selects) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua + * 1_txd- (UART transmitter serial output) 7= Not Used +*/ #undef IOU_SLCR_MIO_PIN_20_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_20_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_20_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_20_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_20_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_20_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_20_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_20_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_20_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_21_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_21_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_21_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_21_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_21_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_21_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_21_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_21_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_21_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[5]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[5]- (NAND - ata Bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[5]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[5]- (NAND Data Bus) +*/ #undef IOU_SLCR_MIO_PIN_21_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_21_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_21_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_21_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_21_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_21_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_21_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_21_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_21_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Comman - Indicator) 2= test_scan, Input, test_scan_in[21]- (Test Scan Port) = test_scan, Output, test_scan_out[21]- (Test Scan Port) - = csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Com + * mand Indicator) = sd0, Output, sdio0_cmd_out- (Command Indicator) 2= tes + * t_scan, Input, test_scan_in[21]- (Test Scan Port) = test_scan, Output, t + * est_scan_out[21]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU E + * xt Tamper) +*/ #undef IOU_SLCR_MIO_PIN_21_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_21_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_21_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_21_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_21_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_21_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_21_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_21_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_21_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[21]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[21]- (GPIO bank 0) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1 - Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- - UART receiver serial input) 7= Not Used*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[21]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[21]- (GPIO bank 0) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master + * Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc + * 1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- ( + * UART receiver serial input) 7= Not Used +*/ #undef IOU_SLCR_MIO_PIN_21_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_21_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_21_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_21_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_21_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_21_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_21_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_21_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_21_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_22_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_22_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_22_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_22_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_22_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_22_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_22_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_22_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_22_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_we_b- (NAND Write Enable)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_we_b- (NAN + * D Write Enable) +*/ #undef IOU_SLCR_MIO_PIN_22_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_22_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_22_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_22_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_22_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_22_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_22_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_22_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_22_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= test_scan, Input, test_scan_in[22]- - (Test Scan Port) = test_scan, Output, test_scan_out[22]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- + * (SDSDIO clock) 2= test_scan, Input, test_scan_in[22]- (Test Scan Port) = + * test_scan, Output, test_scan_out[22]- (Test Scan Port) 3= csu, Input, c + * su_ext_tamper- (CSU Ext Tamper) +*/ #undef IOU_SLCR_MIO_PIN_22_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_22_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_22_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_22_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_22_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_22_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_22_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_22_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_22_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[22]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[22]- (GPIO bank 0) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, sp - 1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not - sed*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[22]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[22]- (GPIO bank 0) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= + * spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- ( + * TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not U + * sed +*/ #undef IOU_SLCR_MIO_PIN_22_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_22_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_22_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_22_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_22_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_22_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_22_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_22_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_22_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_23_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_23_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_23_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_23_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_23_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_23_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_23_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_23_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_23_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[6]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[6]- (NAND - ata Bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[6]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[6]- (NAND Data Bus) +*/ #undef IOU_SLCR_MIO_PIN_23_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_23_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_23_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_23_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_23_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_23_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_23_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_23_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_23_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= test_scan, Input, test_scan_in - 23]- (Test Scan Port) = test_scan, Output, test_scan_out[23]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper - */ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- + * (SD card bus power) 2= test_scan, Input, test_scan_in[23]- (Test Scan Po + * rt) = test_scan, Output, test_scan_out[23]- (Test Scan Port) 3= csu, Inp + * ut, csu_ext_tamper- (CSU Ext Tamper) +*/ #undef IOU_SLCR_MIO_PIN_23_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_23_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_23_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_23_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_23_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_23_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_23_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_23_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_23_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[23]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[23]- (GPIO bank 0) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s - i1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o - tput) 7= Not Used*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[23]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[23]- (GPIO bank 0) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) + * 4= spi1, Input, spi1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- ( + * TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial ou + * tput) 7= Not Used +*/ #undef IOU_SLCR_MIO_PIN_23_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_23_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_23_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_23_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_23_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_23_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_23_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_23_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_23_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_24_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_24_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_24_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_24_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_24_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_24_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_24_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_24_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_24_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[7]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[7]- (NAND - ata Bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[7]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[7]- (NAND Data Bus) +*/ #undef IOU_SLCR_MIO_PIN_24_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_24_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_24_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_24_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_24_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_24_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_24_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_24_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_24_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= test_scan, Input, test - scan_in[24]- (Test Scan Port) = test_scan, Output, test_scan_out[24]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ex - Tamper)*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD + * card detect from connector) 2= test_scan, Input, test_scan_in[24]- (Test + * Scan Port) = test_scan, Output, test_scan_out[24]- (Test Scan Port) 3= + * csu, Input, csu_ext_tamper- (CSU Ext Tamper) +*/ #undef IOU_SLCR_MIO_PIN_24_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_24_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_24_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_24_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_24_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_24_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_24_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_24_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_24_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[24]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[24]- (GPIO bank 0) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= Not Used 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, - Output, ua1_txd- (UART transmitter serial output) 7= Not Used*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[24]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[24]- (GPIO bank 0) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= Not Used 5= ttc3, Input, ttc3_clk_in- (T + * TC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= N + * ot Used +*/ #undef IOU_SLCR_MIO_PIN_24_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_24_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_24_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_24_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_24_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_24_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_24_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_24_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_24_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_25_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_25_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_25_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_25_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_25_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_25_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_25_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_25_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_25_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_re_n- (NAND Read Enable)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_re_n- (NAN + * D Read Enable) +*/ #undef IOU_SLCR_MIO_PIN_25_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_25_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_25_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_25_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_25_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_25_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_25_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_25_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_25_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= test_scan, Input, - test_scan_in[25]- (Test Scan Port) = test_scan, Output, test_scan_out[25]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (C - U Ext Tamper)*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD ca + * rd write protect from connector) 2= test_scan, Input, test_scan_in[25]- + * (Test Scan Port) = test_scan, Output, test_scan_out[25]- (Test Scan Port + * ) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper) +*/ #undef IOU_SLCR_MIO_PIN_25_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_25_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_25_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_25_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_25_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_25_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_25_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_25_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_25_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[25]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[25]- (GPIO bank 0) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= Not Used 5= ttc3, Output, ttc3_wave_out- (TTC Waveform - lock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[25]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[25]- (GPIO bank 0) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= Not Used 5= ttc3, Output, ttc3_wave_ou + * t- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial in + * put) 7= Not Used +*/ #undef IOU_SLCR_MIO_PIN_25_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_25_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_25_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_25_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_25_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_25_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_25_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_25_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_25_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_clk- (TX RGMII clock)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ + * clk- (TX RGMII clock) +*/ #undef IOU_SLCR_MIO_PIN_26_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_26_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_26_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_26_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_26_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_26_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_26_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_26_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_26_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NAND chip enable)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NA + * ND chip enable) +*/ #undef IOU_SLCR_MIO_PIN_26_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_26_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_26_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_26_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_26_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_26_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_26_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_26_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_26_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[0]- (PMU GPI) 2= test_scan, Input, test_scan_in[26]- (Test Sc - n Port) = test_scan, Output, test_scan_out[26]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[0]- (PMU + * GPI) 2= test_scan, Input, test_scan_in[26]- (Test Scan Port) = test_sca + * n, Output, test_scan_out[26]- (Test Scan Port) 3= csu, Input, csu_ext_ta + * mper- (CSU Ext Tamper) +*/ #undef IOU_SLCR_MIO_PIN_26_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_26_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_26_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_26_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_26_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_26_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_26_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_26_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_26_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[0]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[0]- (GPIO bank 1) 1= can - , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal - 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Clock - 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- - Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[0]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[0]- (GPIO bank 1) 1= can0, Input, can0_phy_ + * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + * , Output, i2c0_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG + * TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_scl + * k_out- (SPI Clock) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Inpu + * t, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- ( + * Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_26_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_26_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_26_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_26_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_26_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_26_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_26_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_26_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_26_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[0]- (TX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd + * [0]- (TX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_27_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_27_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_27_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_27_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_27_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_27_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_27_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_27_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_27_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (NAND Ready/Busy)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (N + * AND Ready/Busy) +*/ #undef IOU_SLCR_MIO_PIN_27_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_27_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_27_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_27_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_27_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_27_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_27_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_27_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_27_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[1]- (PMU GPI) 2= test_scan, Input, test_scan_in[27]- (Test Sc - n Port) = test_scan, Output, test_scan_out[27]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Outp - t, dp_aux_data_out- (Dp Aux Data)*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[1]- (PMU + * GPI) 2= test_scan, Input, test_scan_in[27]- (Test Scan Port) = test_sca + * n, Output, test_scan_out[27]- (Test Scan Port) 3= dpaux, Input, dp_aux_d + * ata_in- (Dp Aux Data) = dpaux, Output, dp_aux_data_out- (Dp Aux Data) +*/ #undef IOU_SLCR_MIO_PIN_27_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_27_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_27_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_27_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_27_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_27_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_27_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_27_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_27_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[1]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[1]- (GPIO bank 1) 1= can - , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa - ) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_ - ut- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port - atabus)*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[1]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[1]- (GPIO bank 1) 1= can0, Output, can0_phy + * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + * 0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG + * TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc2, O + * utput, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UAR + * T transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port D + * atabus) +*/ #undef IOU_SLCR_MIO_PIN_27_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_27_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_27_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_27_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_27_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_27_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_27_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_27_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_27_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[1]- (TX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd + * [1]- (TX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_28_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_28_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_28_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_28_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_28_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_28_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_28_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_28_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_28_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (NAND Ready/Busy)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (N + * AND Ready/Busy) +*/ #undef IOU_SLCR_MIO_PIN_28_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_28_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_28_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_28_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_28_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_28_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_28_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_28_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_28_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[2]- (PMU GPI) 2= test_scan, Input, test_scan_in[28]- (Test Sc - n Port) = test_scan, Output, test_scan_out[28]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[2]- (PMU + * GPI) 2= test_scan, Input, test_scan_in[28]- (Test Scan Port) = test_sca + * n, Output, test_scan_out[28]- (Test Scan Port) 3= dpaux, Input, dp_hot_p + * lug_detect- (Dp Aux Hot Plug) +*/ #undef IOU_SLCR_MIO_PIN_28_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_28_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_28_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_28_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_28_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_28_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_28_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_28_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_28_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[2]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[2]- (GPIO bank 1) 1= can - , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa - ) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc1, Input, ttc1_clk_i - - (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[2]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[2]- (GPIO bank 1) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTA + * G TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc1, + * Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitt + * er serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_28_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_28_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_28_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_28_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_28_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_28_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_28_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_28_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_28_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[2]- (TX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd + * [2]- (TX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_29_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_29_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_29_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_29_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_29_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_29_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_29_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_29_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_29_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + * PCIE Reset signal) +*/ #undef IOU_SLCR_MIO_PIN_29_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_29_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_29_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_29_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_29_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_29_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_29_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_29_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_29_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[3]- (PMU GPI) 2= test_scan, Input, test_scan_in[29]- (Test Sc - n Port) = test_scan, Output, test_scan_out[29]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Outp - t, dp_aux_data_out- (Dp Aux Data)*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[3]- (PMU + * GPI) 2= test_scan, Input, test_scan_in[29]- (Test Scan Port) = test_sca + * n, Output, test_scan_out[29]- (Test Scan Port) 3= dpaux, Input, dp_aux_d + * ata_in- (Dp Aux Data) = dpaux, Output, dp_aux_data_out- (Dp Aux Data) +*/ #undef IOU_SLCR_MIO_PIN_29_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_29_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_29_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_29_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_29_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_29_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_29_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_29_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_29_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[3]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[3]- (GPIO bank 1) 1= can - , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal - 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0] - (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial inpu - ) 7= trace, Output, tracedq[7]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[3]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[3]- (GPIO bank 1) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG + * TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, + * spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- + * (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input + * ) 7= trace, Output, tracedq[7]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_29_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_29_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_29_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_29_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_29_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_29_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_29_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_29_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_29_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[3]- (TX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd + * [3]- (TX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_30_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_30_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_30_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_30_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_30_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_30_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_30_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_30_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_30_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + * PCIE Reset signal) +*/ #undef IOU_SLCR_MIO_PIN_30_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_30_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_30_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_30_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_30_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_30_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_30_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_30_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_30_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[4]- (PMU GPI) 2= test_scan, Input, test_scan_in[30]- (Test Sc - n Port) = test_scan, Output, test_scan_out[30]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[4]- (PMU + * GPI) 2= test_scan, Input, test_scan_in[30]- (Test Scan Port) = test_sca + * n, Output, test_scan_out[30]- (Test Scan Port) 3= dpaux, Input, dp_hot_p + * lug_detect- (Dp Aux Hot Plug) +*/ #undef IOU_SLCR_MIO_PIN_30_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_30_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_30_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_30_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_30_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_30_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_30_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_30_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_30_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[4]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[4]- (GPIO bank 1) 1= can - , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal - 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_so - (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output - tracedq[8]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[4]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[4]- (GPIO bank 1) 1= can0, Input, can0_phy_ + * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + * , Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Wat + * ch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0 + * , Output, spi0_so- (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clock + * ) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, + * tracedq[8]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_30_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_30_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_30_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_30_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_30_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_30_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_30_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_30_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_30_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ctl- (TX RGMII control)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ + * ctl- (TX RGMII control) +*/ #undef IOU_SLCR_MIO_PIN_31_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_31_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_31_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_31_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_31_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_31_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_31_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_31_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_31_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + * PCIE Reset signal) +*/ #undef IOU_SLCR_MIO_PIN_31_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_31_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_31_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_31_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_31_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_31_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_31_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_31_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_31_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[5]- (PMU GPI) 2= test_scan, Input, test_scan_in[31]- (Test Sc - n Port) = test_scan, Output, test_scan_out[31]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[5]- (PMU + * GPI) 2= test_scan, Input, test_scan_in[31]- (Test Scan Port) = test_sca + * n, Output, test_scan_out[31]- (Test Scan Port) 3= csu, Input, csu_ext_ta + * mper- (CSU Ext Tamper) +*/ #undef IOU_SLCR_MIO_PIN_31_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_31_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_31_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_31_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_31_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_31_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_31_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_31_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_31_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[5]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[5]- (GPIO bank 1) 1= can - , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa - ) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi - _si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial out - ut) 7= trace, Output, tracedq[9]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[5]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[5]- (GPIO bank 1) 1= can0, Output, can0_phy + * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + * 0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- ( + * Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= + * spi0, Input, spi0_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TT + * C Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial outp + * ut) 7= trace, Output, tracedq[9]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_31_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_31_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_31_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_31_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_31_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_31_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_31_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_31_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_31_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_clk- (RX RGMII clock)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_c + * lk- (RX RGMII clock) +*/ #undef IOU_SLCR_MIO_PIN_32_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_32_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_32_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_32_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_32_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_32_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_32_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_32_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_32_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NAND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe - */ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NA + * ND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe) +*/ #undef IOU_SLCR_MIO_PIN_32_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_32_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_32_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_32_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_32_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_32_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_32_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_32_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_32_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[0]- (PMU GPI) 2= test_scan, Input, test_scan_in[32]- (Test S - an Port) = test_scan, Output, test_scan_out[32]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[0]- (PM + * U GPI) 2= test_scan, Input, test_scan_in[32]- (Test Scan Port) = test_sc + * an, Output, test_scan_out[32]- (Test Scan Port) 3= csu, Input, csu_ext_t + * amper- (CSU Ext Tamper) +*/ #undef IOU_SLCR_MIO_PIN_32_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_32_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_32_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_32_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_32_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_32_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_32_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_32_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_32_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[6]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[6]- (GPIO bank 1) 1= can - , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa - ) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi - _sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= - race, Output, tracedq[10]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[6]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[6]- (GPIO bank 1) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Wa + * tch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= + * spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (T + * TC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= t + * race, Output, tracedq[10]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_32_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_32_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_32_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_32_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_32_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_32_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_32_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_32_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_32_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[0]- (RX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[ + * 0]- (RX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_33_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_33_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_33_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_33_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_33_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_33_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_33_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_33_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_33_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + * PCIE Reset signal) +*/ #undef IOU_SLCR_MIO_PIN_33_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_33_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_33_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_33_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_33_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_33_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_33_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_33_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_33_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[1]- (PMU GPI) 2= test_scan, Input, test_scan_in[33]- (Test S - an Port) = test_scan, Output, test_scan_out[33]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[1]- (PM + * U GPI) 2= test_scan, Input, test_scan_in[33]- (Test Scan Port) = test_sc + * an, Output, test_scan_out[33]- (Test Scan Port) 3= csu, Input, csu_ext_t + * amper- (CSU Ext Tamper) +*/ #undef IOU_SLCR_MIO_PIN_33_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_33_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_33_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_33_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_33_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_33_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_33_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_33_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_33_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[7]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[7]- (GPIO bank 1) 1= can - , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal - 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= t - c3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, traced - [11]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[7]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[7]- (GPIO bank 1) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (W + * atch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Mas + * ter Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1 + * , Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq + * [11]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_33_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_33_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_33_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_33_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_33_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_33_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_33_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_33_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_33_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[1]- (RX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[ + * 1]- (RX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_34_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_34_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_34_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_34_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_34_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_34_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_34_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_34_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_34_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + * PCIE Reset signal) +*/ #undef IOU_SLCR_MIO_PIN_34_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_34_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_34_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_34_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_34_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_34_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_34_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_34_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_34_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[2]- (PMU GPI) 2= test_scan, Input, test_scan_in[34]- (Test S - an Port) = test_scan, Output, test_scan_out[34]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Out - ut, dp_aux_data_out- (Dp Aux Data)*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[2]- (PM + * U GPI) 2= test_scan, Input, test_scan_in[34]- (Test Scan Port) = test_sc + * an, Output, test_scan_out[34]- (Test Scan Port) 3= dpaux, Input, dp_aux_ + * data_in- (Dp Aux Data) = dpaux, Output, dp_aux_data_out- (Dp Aux Data) +*/ #undef IOU_SLCR_MIO_PIN_34_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_34_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_34_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_34_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_34_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_34_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_34_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_34_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_34_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[8]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[8]- (GPIO bank 1) 1= can - , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal - 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc2 - Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace P - rt Databus)*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[8]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[8]- (GPIO bank 1) 1= can0, Input, can0_phy_ + * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + * , Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Wat + * ch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master + * Selects) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rx + * d- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace Po + * rt Databus) +*/ #undef IOU_SLCR_MIO_PIN_34_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_34_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_34_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_34_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_34_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_34_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_34_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_34_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_34_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[2]- (RX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[ + * 2]- (RX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_35_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_35_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_35_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_35_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_35_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_35_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_35_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_35_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_35_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + * PCIE Reset signal) +*/ #undef IOU_SLCR_MIO_PIN_35_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_35_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_35_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_35_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_35_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_35_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_35_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_35_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_35_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[3]- (PMU GPI) 2= test_scan, Input, test_scan_in[35]- (Test S - an Port) = test_scan, Output, test_scan_out[35]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[3]- (PM + * U GPI) 2= test_scan, Input, test_scan_in[35]- (Test Scan Port) = test_sc + * an, Output, test_scan_out[35]- (Test Scan Port) 3= dpaux, Input, dp_hot_ + * plug_detect- (Dp Aux Hot Plug) +*/ #undef IOU_SLCR_MIO_PIN_35_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_35_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_35_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_35_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_35_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_35_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_35_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_35_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_35_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[9]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[9]- (GPIO bank 1) 1= can - , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa - ) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, - Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- - UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[9]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[9]- (GPIO bank 1) 1= can0, Output, can0_phy + * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + * 0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- ( + * Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master + * Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc2 + * , Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- ( + * UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace Po + * rt Databus) +*/ #undef IOU_SLCR_MIO_PIN_35_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_35_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_35_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_35_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_35_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_35_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_35_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_35_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_35_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[3]- (RX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[ + * 3]- (RX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_36_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_36_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_36_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_36_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_36_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_36_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_36_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_36_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_36_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + * PCIE Reset signal) +*/ #undef IOU_SLCR_MIO_PIN_36_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_36_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_36_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_36_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_36_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_36_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_36_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_36_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_36_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[4]- (PMU GPI) 2= test_scan, Input, test_scan_in[36]- (Test S - an Port) = test_scan, Output, test_scan_out[36]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Out - ut, dp_aux_data_out- (Dp Aux Data)*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[4]- (PM + * U GPI) 2= test_scan, Input, test_scan_in[36]- (Test Scan Port) = test_sc + * an, Output, test_scan_out[36]- (Test Scan Port) 3= dpaux, Input, dp_aux_ + * data_in- (Dp Aux Data) = dpaux, Output, dp_aux_data_out- (Dp Aux Data) +*/ #undef IOU_SLCR_MIO_PIN_36_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_36_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_36_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_36_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_36_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_36_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_36_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_36_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_36_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[10]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[10]- (GPIO bank 1) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1 - so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace - Output, tracedq[14]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[10]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[10]- (GPIO bank 1) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= s + * pi1, Output, spi1_so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Cl + * ock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, + * Output, tracedq[14]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_36_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_36_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_36_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_36_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_36_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_36_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_36_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_36_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_36_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_ctl- (RX RGMII control )*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_c + * tl- (RX RGMII control ) +*/ #undef IOU_SLCR_MIO_PIN_37_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_37_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_37_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_37_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_37_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_37_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_37_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_37_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_37_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + * PCIE Reset signal) +*/ #undef IOU_SLCR_MIO_PIN_37_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_37_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_37_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_37_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_37_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_37_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_37_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_37_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_37_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[5]- (PMU GPI) 2= test_scan, Input, test_scan_in[37]- (Test S - an Port) = test_scan, Output, test_scan_out[37]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[5]- (PM + * U GPI) 2= test_scan, Input, test_scan_in[37]- (Test Scan Port) = test_sc + * an, Output, test_scan_out[37]- (Test Scan Port) 3= dpaux, Input, dp_hot_ + * plug_detect- (Dp Aux Hot Plug) +*/ #undef IOU_SLCR_MIO_PIN_37_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_37_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_37_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_37_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_37_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_37_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_37_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_37_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_37_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[11]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[11]- (GPIO bank 1) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, sp - 1_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) - 7= trace, Output, tracedq[15]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[11]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[11]- (GPIO bank 1) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4 + * = spi1, Input, spi1_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (T + * TC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) + * 7= trace, Output, tracedq[15]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_37_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_37_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_37_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_37_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_37_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_37_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_37_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_37_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_37_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_clk- (TX RGMII clock)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ + * clk- (TX RGMII clock) +*/ #undef IOU_SLCR_MIO_PIN_38_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_38_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_38_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_38_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_38_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_38_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_38_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_38_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_38_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_38_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_38_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_38_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_38_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_38_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_38_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_38_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_38_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_38_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= Not Used 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- + * (SDSDIO clock) 2= Not Used 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_38_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_38_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_38_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_38_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_38_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_38_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_38_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_38_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_38_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[12]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[12]- (GPIO bank 1) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Clo - k) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, trace_clk- - (Trace Port Clock)*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[12]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[12]- (GPIO bank 1) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTA + * G TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_s + * clk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, In + * put, ua0_rxd- (UART receiver serial input) 7= trace, Output, trace_clk- + * (Trace Port Clock) +*/ #undef IOU_SLCR_MIO_PIN_38_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_38_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_38_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_38_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_38_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_38_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_38_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_38_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_38_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[0]- (TX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd + * [0]- (TX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_39_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_39_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_39_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_39_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_39_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_39_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_39_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_39_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_39_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_39_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_39_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_39_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_39_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_39_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_39_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_39_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_39_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_39_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= sd1, Input, sd1_data_i - [4]- (8-bit Data bus) = sd1, Output, sdio1_data_out[4]- (8-bit Data bus) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD + * card detect from connector) 2= sd1, Input, sd1_data_in[4]- (8-bit Data b + * us) = sd1, Output, sdio1_data_out[4]- (8-bit Data bus) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_39_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_39_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_39_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_39_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_39_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_39_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_39_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_39_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_39_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[13]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[13]- (GPIO bank 1) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc0, Output, ttc0_wav - _out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, trace_ctl- (Trace Port - Control Signal)*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[13]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[13]- (GPIO bank 1) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJT + * AG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc0, + * Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (U + * ART transmitter serial output) 7= trace, Output, trace_ctl- (Trace Port + * Control Signal) +*/ #undef IOU_SLCR_MIO_PIN_39_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_39_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_39_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_39_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_39_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_39_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_39_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_39_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_39_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[1]- (TX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd + * [1]- (TX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_40_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_40_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_40_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_40_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_40_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_40_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_40_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_40_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_40_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_40_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_40_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_40_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_40_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_40_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_40_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_40_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_40_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_40_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Comman - Indicator) 2= sd1, Input, sd1_data_in[5]- (8-bit Data bus) = sd1, Output, sdio1_data_out[5]- (8-bit Data bus) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Com + * mand Indicator) = sd0, Output, sdio0_cmd_out- (Command Indicator) 2= sd1 + * , Input, sd1_data_in[5]- (8-bit Data bus) = sd1, Output, sdio1_data_out[ + * 5]- (8-bit Data bus) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_40_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_40_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_40_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_40_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_40_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_40_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_40_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_40_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_40_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[14]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[14]- (GPIO bank 1) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc3, Input, ttc3_clk - in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[0]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[14]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[14]- (GPIO bank 1) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJ + * TAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc3 + * , Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmi + * tter serial output) 7= trace, Output, tracedq[0]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_40_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_40_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_40_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_40_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_40_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_40_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_40_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_40_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_40_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[2]- (TX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd + * [2]- (TX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_41_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_41_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_41_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_41_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_41_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_41_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_41_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_41_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_41_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_41_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_41_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_41_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_41_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_41_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_41_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_41_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_41_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_41_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8 - bit Data bus) 2= sd1, Input, sd1_data_in[6]- (8-bit Data bus) = sd1, Output, sdio1_data_out[6]- (8-bit Data bus) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[6]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[6]- (8-bit Data bus) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_41_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_41_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_41_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_41_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_41_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_41_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_41_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_41_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_41_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[15]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[15]- (GPIO bank 1) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[ - ]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial in - ut) 7= trace, Output, tracedq[1]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[15]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[15]- (GPIO bank 1) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTA + * G TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Outpu + * t, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out + * - (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial inp + * ut) 7= trace, Output, tracedq[1]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_41_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_41_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_41_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_41_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_41_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_41_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_41_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_41_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_41_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[3]- (TX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd + * [3]- (TX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_42_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_42_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_42_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_42_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_42_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_42_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_42_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_42_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_42_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_42_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_42_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_42_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_42_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_42_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_42_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_42_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_42_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_42_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8 - bit Data bus) 2= sd1, Input, sd1_data_in[7]- (8-bit Data bus) = sd1, Output, sdio1_data_out[7]- (8-bit Data bus) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[7]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[7]- (8-bit Data bus) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_42_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_42_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_42_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_42_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_42_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_42_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_42_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_42_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_42_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_ - o- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outp - t, tracedq[2]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= sp + * i0, Output, spi0_so- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clo + * ck) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outpu + * t, tracedq[2]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_42_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_42_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_42_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_42_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_42_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_42_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_42_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_42_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_42_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ctl- (TX RGMII control)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ + * ctl- (TX RGMII control) +*/ #undef IOU_SLCR_MIO_PIN_43_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_43_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_43_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_43_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_43_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_43_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_43_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_43_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_43_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_43_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_43_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_43_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_43_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_43_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_43_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_43_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_43_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_43_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8 - bit Data bus) 2= sd1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8-bit Data bus) 2= s + * d1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_43_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_43_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_43_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_43_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_43_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_43_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_43_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_43_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_43_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, s - i0_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o - tput) 7= trace, Output, tracedq[3]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) + * 4= spi0, Input, spi0_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- ( + * TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial ou + * tput) 7= trace, Output, tracedq[3]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_43_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_43_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_43_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_43_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_43_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_43_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_43_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_43_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_43_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_clk- (RX RGMII clock)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_c + * lk- (RX RGMII clock) +*/ #undef IOU_SLCR_MIO_PIN_44_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_44_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_44_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_44_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_44_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_44_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_44_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_44_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_44_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_44_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_44_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_44_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_44_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_44_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_44_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_44_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_44_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_44_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8 - bit Data bus) 2= sd1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8-bit Data bus) 2= s + * d1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_44_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_44_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_44_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_44_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_44_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_44_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_44_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_44_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_44_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[18]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[18]- (GPIO bank 1) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, s - i1_sclk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7 - Not Used*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[18]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[18]- (GPIO bank 1) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4 + * = spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- + * (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= + * Not Used +*/ #undef IOU_SLCR_MIO_PIN_44_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_44_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_44_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_44_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_44_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_44_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_44_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_44_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_44_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[0]- (RX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[ + * 0]- (RX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_45_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_45_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_45_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_45_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_45_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_45_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_45_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_45_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_45_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_45_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_45_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_45_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_45_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_45_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_45_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_45_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_45_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_45_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8 - bit Data bus) 2= sd1, Input, sdio1_cd_n- (SD card detect from connector) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8-bit Data bus) 2= s + * d1, Input, sdio1_cd_n- (SD card detect from connector) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_45_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_45_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_45_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_45_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_45_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_45_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_45_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_45_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_45_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[19]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[19]- (GPIO bank 1) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= - ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[19]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[19]- (GPIO bank 1) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI M + * aster Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= u + * a1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used +*/ #undef IOU_SLCR_MIO_PIN_45_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_45_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_45_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_45_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_45_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_45_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_45_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_45_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_45_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[1]- (RX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[ + * 1]- (RX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_46_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_46_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_46_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_46_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_46_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_46_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_46_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_46_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_46_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_46_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_46_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_46_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_46_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_46_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_46_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_46_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_46_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_46_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8 - bit Data bus) 2= sd1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_out[0]- (8-bit Data bus) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[0]- (8-bit Data bus) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_46_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_46_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_46_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_46_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_46_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_46_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_46_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_46_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_46_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= tt - 0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Mast + * er Selects) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_ + * rxd- (UART receiver serial input) 7= Not Used +*/ #undef IOU_SLCR_MIO_PIN_46_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_46_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_46_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_46_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_46_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_46_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_46_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_46_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_46_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[2]- (RX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[ + * 2]- (RX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_47_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_47_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_47_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_47_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_47_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_47_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_47_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_47_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_47_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_47_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_47_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_47_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_47_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_47_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_47_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_47_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_47_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_47_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8 - bit Data bus) 2= sd1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_out[1]- (8-bit Data bus) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[1]- (8-bit Data bus) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_47_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_47_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_47_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_47_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_47_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_47_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_47_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_47_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_47_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi - , Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd - (UART transmitter serial output) 7= Not Used*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Maste + * r Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= tt + * c0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- + * (UART transmitter serial output) 7= Not Used +*/ #undef IOU_SLCR_MIO_PIN_47_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_47_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_47_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_47_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_47_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_47_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_47_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_47_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_47_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[3]- (RX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[ + * 3]- (RX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_48_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_48_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_48_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_48_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_48_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_48_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_48_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_48_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_48_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_48_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_48_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_48_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_48_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_48_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_48_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_48_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_48_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_48_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8 - bit Data bus) 2= sd1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_out[2]- (8-bit Data bus) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[2]- (8-bit Data bus) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_48_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_48_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_48_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_48_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_48_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_48_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_48_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_48_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_48_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[22]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[22]- (GPIO bank 1) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1 - so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not U - ed*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[22]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[22]- (GPIO bank 1) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= s + * pi1, Output, spi1_so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Cl + * ock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Us + * ed +*/ #undef IOU_SLCR_MIO_PIN_48_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_48_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_48_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_48_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_48_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_48_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_48_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_48_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_48_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_ctl- (RX RGMII control )*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_c + * tl- (RX RGMII control ) +*/ #undef IOU_SLCR_MIO_PIN_49_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_49_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_49_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_49_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_49_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_49_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_49_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_49_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_49_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_49_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_49_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_49_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_49_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_49_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_49_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_49_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_49_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_49_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= sd1, Input, sd1_data_in[3]- (8 - bit Data bus) = sd1, Output, sdio1_data_out[3]- (8-bit Data bus) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- + * (SD card bus power) 2= sd1, Input, sd1_data_in[3]- (8-bit Data bus) = sd + * 1, Output, sdio1_data_out[3]- (8-bit Data bus) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_49_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_49_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_49_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_49_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_49_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_49_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_49_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_49_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_49_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[23]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[23]- (GPIO bank 1) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, sp - 1_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) - 7= Not Used*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[23]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[23]- (GPIO bank 1) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4 + * = spi1, Input, spi1_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (T + * TC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) + * 7= Not Used +*/ #undef IOU_SLCR_MIO_PIN_49_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_49_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_49_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_49_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_49_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_49_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_49_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_49_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_49_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- (TSU clock)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- + * (TSU clock) +*/ #undef IOU_SLCR_MIO_PIN_50_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_50_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_50_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_50_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_50_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_50_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_50_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_50_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_50_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_50_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_50_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_50_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_50_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_50_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_50_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_50_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_50_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_50_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= sd1, Input, sd1_c - d_in- (Command Indicator) = sd1, Output, sdio1_cmd_out- (Command Indicator) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD ca + * rd write protect from connector) 2= sd1, Input, sd1_cmd_in- (Command Ind + * icator) = sd1, Output, sdio1_cmd_out- (Command Indicator) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_50_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_50_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_50_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_50_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_50_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_50_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_50_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_50_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_50_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[24]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[24]- (GPIO bank 1) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= ttc2, Input, ttc2 - clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[24]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[24]- (GPIO bank 1) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= + * ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART rece + * iver serial input) 7= Not Used +*/ #undef IOU_SLCR_MIO_PIN_50_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_50_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_50_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_50_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_50_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_50_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_50_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_50_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_50_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- (TSU clock)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- + * (TSU clock) +*/ #undef IOU_SLCR_MIO_PIN_51_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_51_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_51_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_51_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_51_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_51_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_51_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_51_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_51_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_51_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_51_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_51_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_51_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_51_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_51_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_51_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_51_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_51_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Output, sdio1_clk_out- (SDSDIO clock) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Output, sdi + * o1_clk_out- (SDSDIO clock) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_51_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_51_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_51_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_51_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_51_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_51_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_51_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_51_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_51_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[25]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[25]- (GPIO bank 1) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= mdio1, Input, gem1_mdio_in- (MDIO Data) 4= mdio1, Outp - t, gem1_mdio_out- (MDIO Data) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter - serial output) 7= Not Used*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[25]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[25]- (GPIO bank 1) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= mdio1, Input, gem1_mdio_in- (MDIO Dat + * a) 4= mdio1, Output, gem1_mdio_out- (MDIO Data) 5= ttc2, Output, ttc2_wa + * ve_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter + * serial output) 7= Not Used +*/ #undef IOU_SLCR_MIO_PIN_51_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_51_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_51_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_51_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_51_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_51_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_51_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_51_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_51_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_clk- (TX RGMII clock)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_ + * clk- (TX RGMII clock) +*/ #undef IOU_SLCR_MIO_PIN_52_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_52_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_52_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_52_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_52_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_52_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_52_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_52_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_52_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_clk_in- (ULPI Clock)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_clk_i + * n- (ULPI Clock) +*/ #undef IOU_SLCR_MIO_PIN_52_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_52_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_52_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_52_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_52_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_52_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_52_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_52_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_52_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used +*/ #undef IOU_SLCR_MIO_PIN_52_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_52_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_52_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_52_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_52_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_52_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_52_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_52_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_52_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[0]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[0]- (GPIO bank 2) 1= can - , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa - ) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Cloc - ) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_ - lk- (Trace Port Clock)*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[0]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[0]- (GPIO bank 2) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG + * TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sc + * lk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Out + * put, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_c + * lk- (Trace Port Clock) +*/ #undef IOU_SLCR_MIO_PIN_52_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_52_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_52_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_52_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_52_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_52_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_52_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_52_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_52_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[0]- (TX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd + * [0]- (TX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_53_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_53_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_53_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_53_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_53_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_53_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_53_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_53_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_53_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_dir- (Data bus direction control)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_dir- + * (Data bus direction control) +*/ #undef IOU_SLCR_MIO_PIN_53_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_53_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_53_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_53_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_53_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_53_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_53_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_53_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_53_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used +*/ #undef IOU_SLCR_MIO_PIN_53_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_53_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_53_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_53_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_53_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_53_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_53_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_53_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_53_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[1]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[1]- (GPIO bank 2) 1= can - , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal - 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_o - t- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control - Signal)*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[1]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[1]- (GPIO bank 2) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG + * TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Ou + * tput, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART + * receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control + * Signal) +*/ #undef IOU_SLCR_MIO_PIN_53_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_53_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_53_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_53_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_53_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_53_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_53_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_53_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_53_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[1]- (TX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd + * [1]- (TX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_54_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_54_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_54_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_54_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_54_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_54_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_54_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_54_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_54_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[2]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_ - ata[2]- (ULPI data bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[2]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[2]- (ULPI data + * bus) +*/ #undef IOU_SLCR_MIO_PIN_54_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_54_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_54_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_54_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_54_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_54_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_54_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_54_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_54_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used +*/ #undef IOU_SLCR_MIO_PIN_54_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_54_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_54_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_54_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_54_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_54_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_54_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_54_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_54_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[2]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[2]- (GPIO bank 2) 1= can - , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal - 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, Input, ttc0_clk_in - (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[0]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[2]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[2]- (GPIO bank 2) 1= can0, Input, can0_phy_ + * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + * , Output, i2c0_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTAG + * TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, I + * nput, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver se + * rial input) 7= trace, Output, tracedq[0]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_54_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_54_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_54_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_54_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_54_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_54_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_54_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_54_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_54_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[2]- (TX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd + * [2]- (TX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_55_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_55_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_55_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_55_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_55_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_55_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_55_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_55_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_55_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_nxt- (Data flow control signal from the PHY)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_nxt- + * (Data flow control signal from the PHY) +*/ #undef IOU_SLCR_MIO_PIN_55_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_55_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_55_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_55_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_55_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_55_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_55_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_55_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_55_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used +*/ #undef IOU_SLCR_MIO_PIN_55_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_55_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_55_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_55_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_55_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_55_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_55_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_55_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_55_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[3]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[3]- (GPIO bank 2) 1= can - , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa - ) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0 - - (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial - output) 7= trace, Output, tracedq[1]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[3]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[3]- (GPIO bank 2) 1= can0, Output, can0_phy + * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + * 0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG + * TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output + * , spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- + * (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial + * output) 7= trace, Output, tracedq[1]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_55_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_55_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_55_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_55_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_55_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_55_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_55_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_55_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_55_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[3]- (TX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd + * [3]- (TX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_56_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_56_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_56_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_56_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_56_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_56_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_56_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_56_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_56_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[0]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_ - ata[0]- (ULPI data bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[0]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[0]- (ULPI data + * bus) +*/ #undef IOU_SLCR_MIO_PIN_56_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_56_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_56_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_56_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_56_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_56_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_56_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_56_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_56_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used +*/ #undef IOU_SLCR_MIO_PIN_56_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_56_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_56_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_56_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_56_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_56_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_56_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_56_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_56_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[4]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[4]- (GPIO bank 2) 1= can - , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa - ) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_s - - (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, - utput, tracedq[2]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[4]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[4]- (GPIO bank 2) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Wa + * tch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi + * 0, Output, spi0_so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Cloc + * k) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, O + * utput, tracedq[2]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_56_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_56_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_56_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_56_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_56_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_56_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_56_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_56_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_56_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_ctl- (TX RGMII control)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_ + * ctl- (TX RGMII control) +*/ #undef IOU_SLCR_MIO_PIN_57_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_57_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_57_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_57_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_57_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_57_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_57_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_57_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_57_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[1]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_ - ata[1]- (ULPI data bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[1]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[1]- (ULPI data + * bus) +*/ #undef IOU_SLCR_MIO_PIN_57_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_57_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_57_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_57_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_57_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_57_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_57_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_57_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_57_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used +*/ #undef IOU_SLCR_MIO_PIN_57_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_57_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_57_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_57_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_57_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_57_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_57_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_57_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_57_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[5]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[5]- (GPIO bank 2) 1= can - , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal - 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi0 - si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7 - trace, Output, tracedq[3]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[5]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[5]- (GPIO bank 2) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (W + * atch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= + * spi0, Input, spi0_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC + * Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= + * trace, Output, tracedq[3]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_57_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_57_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_57_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_57_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_57_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_57_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_57_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_57_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_57_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_clk- (RX RGMII clock)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_c + * lk- (RX RGMII clock) +*/ #undef IOU_SLCR_MIO_PIN_58_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_58_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_58_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_58_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_58_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_58_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_58_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_58_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_58_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Output, usb0_ulpi_stp- (Asserted to end or interrupt transfers)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Output, usb0_ulpi_stp- + * (Asserted to end or interrupt transfers) +*/ #undef IOU_SLCR_MIO_PIN_58_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_58_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_58_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_58_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_58_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_58_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_58_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_58_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_58_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used +*/ #undef IOU_SLCR_MIO_PIN_58_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_58_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_58_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_58_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_58_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_58_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_58_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_58_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_58_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[6]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[6]- (GPIO bank 2) 1= can - , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal - 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1_sclk_out- (SPI Clock - 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- - Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[6]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[6]- (GPIO bank 2) 1= can0, Input, can0_phy_ + * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + * , Output, i2c0_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG + * TCK) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1_scl + * k_out- (SPI Clock) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Inpu + * t, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- ( + * Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_58_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_58_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_58_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_58_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_58_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_58_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_58_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_58_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_58_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[0]- (RX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[ + * 0]- (RX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_59_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_59_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_59_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_59_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_59_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_59_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_59_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_59_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_59_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[3]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_ - ata[3]- (ULPI data bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[3]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[3]- (ULPI data + * bus) +*/ #undef IOU_SLCR_MIO_PIN_59_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_59_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_59_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_59_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_59_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_59_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_59_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_59_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_59_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used +*/ #undef IOU_SLCR_MIO_PIN_59_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_59_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_59_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_59_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_59_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_59_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_59_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_59_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_59_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[7]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[7]- (GPIO bank 2) 1= can - , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa - ) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_ - ut- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port - atabus)*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[7]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[7]- (GPIO bank 2) 1= can0, Output, can0_phy + * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + * 0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG + * TDI) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= ttc2, O + * utput, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UAR + * T transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port D + * atabus) +*/ #undef IOU_SLCR_MIO_PIN_59_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_59_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_59_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_59_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_59_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_59_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_59_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_59_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_59_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[1]- (RX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[ + * 1]- (RX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_60_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_60_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_60_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_60_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_60_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_60_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_60_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_60_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_60_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[4]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_ - ata[4]- (ULPI data bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[4]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[4]- (ULPI data + * bus) +*/ #undef IOU_SLCR_MIO_PIN_60_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_60_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_60_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_60_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_60_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_60_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_60_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_60_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_60_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used +*/ #undef IOU_SLCR_MIO_PIN_60_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_60_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_60_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_60_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_60_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_60_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_60_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_60_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_60_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[8]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[8]- (GPIO bank 2) 1= can - , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa - ) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc1, Input, ttc1_clk_i - - (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[8]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[8]- (GPIO bank 2) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTA + * G TDO) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc1, + * Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitt + * er serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_60_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_60_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_60_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_60_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_60_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_60_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_60_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_60_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_60_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[2]- (RX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[ + * 2]- (RX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_61_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_61_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_61_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_61_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_61_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_61_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_61_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_61_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_61_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[5]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_ - ata[5]- (ULPI data bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[5]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[5]- (ULPI data + * bus) +*/ #undef IOU_SLCR_MIO_PIN_61_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_61_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_61_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_61_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_61_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_61_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_61_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_61_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_61_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used +*/ #undef IOU_SLCR_MIO_PIN_61_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_61_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_61_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_61_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_61_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_61_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_61_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_61_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_61_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[9]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[9]- (GPIO bank 2) 1= can - , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal - 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, Output, spi1_n_ss_out[0] - (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial inpu - ) 7= trace, Output, tracedq[7]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[9]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[9]- (GPIO bank 2) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG + * TMS) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, Output, + * spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- + * (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input + * ) 7= trace, Output, tracedq[7]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_61_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_61_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_61_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_61_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_61_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_61_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_61_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_61_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_61_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[3]- (RX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[ + * 3]- (RX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_62_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_62_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_62_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_62_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_62_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_62_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_62_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_62_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_62_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[6]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_ - ata[6]- (ULPI data bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[6]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[6]- (ULPI data + * bus) +*/ #undef IOU_SLCR_MIO_PIN_62_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_62_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_62_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_62_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_62_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_62_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_62_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_62_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_62_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used +*/ #undef IOU_SLCR_MIO_PIN_62_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_62_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_62_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_62_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_62_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_62_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_62_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_62_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_62_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[10]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[10]- (GPIO bank 2) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_ - o- (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outp - t, tracedq[8]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[10]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[10]- (GPIO bank 2) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= sp + * i1, Output, spi1_so- (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clo + * ck) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outpu + * t, tracedq[8]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_62_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_62_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_62_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_62_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_62_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_62_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_62_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_62_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_62_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_ctl- (RX RGMII control )*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_c + * tl- (RX RGMII control ) +*/ #undef IOU_SLCR_MIO_PIN_63_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_63_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_63_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_63_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_63_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_63_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_63_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_63_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_63_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[7]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_ - ata[7]- (ULPI data bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[7]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[7]- (ULPI data + * bus) +*/ #undef IOU_SLCR_MIO_PIN_63_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_63_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_63_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_63_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_63_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_63_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_63_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_63_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_63_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used +*/ #undef IOU_SLCR_MIO_PIN_63_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_63_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_63_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_63_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_63_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_63_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_63_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_63_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_63_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[11]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[11]- (GPIO bank 2) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s - i1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o - tput) 7= trace, Output, tracedq[9]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[11]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[11]- (GPIO bank 2) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) + * 4= spi1, Input, spi1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- ( + * TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial ou + * tput) 7= trace, Output, tracedq[9]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_63_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_63_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_63_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_63_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_63_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_63_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_63_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_63_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_63_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_clk- (TX RGMII clock)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_ + * clk- (TX RGMII clock) +*/ #undef IOU_SLCR_MIO_PIN_64_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_64_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_64_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_64_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_64_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_64_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_64_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_64_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_64_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_clk_in- (ULPI Clock)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_clk_i + * n- (ULPI Clock) +*/ #undef IOU_SLCR_MIO_PIN_64_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_64_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_64_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_64_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_64_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_64_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_64_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_64_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_64_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= Not Used 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- + * (SDSDIO clock) 2= Not Used 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_64_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_64_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_64_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_64_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_64_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_64_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_64_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_64_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_64_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[12]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[12]- (GPIO bank 2) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, s - i0_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7 - trace, Output, tracedq[10]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[12]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[12]- (GPIO bank 2) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4 + * = spi0, Output, spi0_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- + * (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= + * trace, Output, tracedq[10]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_64_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_64_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_64_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_64_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_64_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_64_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_64_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_64_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_64_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[0]- (TX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd + * [0]- (TX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_65_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_65_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_65_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_65_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_65_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_65_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_65_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_65_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_65_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_dir- (Data bus direction control)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_dir- + * (Data bus direction control) +*/ #undef IOU_SLCR_MIO_PIN_65_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_65_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_65_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_65_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_65_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_65_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_65_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_65_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_65_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= Not Used 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD + * card detect from connector) 2= Not Used 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_65_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_65_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_65_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_65_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_65_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_65_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_65_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_65_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_65_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[13]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[13]- (GPIO bank 2) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= - ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trac - dq[11]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[13]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[13]- (GPIO bank 2) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi0, Output, spi0_n_ss_out[2]- (SPI M + * aster Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= u + * a1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trace + * dq[11]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_65_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_65_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_65_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_65_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_65_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_65_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_65_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_65_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_65_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[1]- (TX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd + * [1]- (TX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_66_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_66_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_66_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_66_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_66_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_66_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_66_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_66_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_66_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[2]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_ - ata[2]- (ULPI data bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[2]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[2]- (ULPI data + * bus) +*/ #undef IOU_SLCR_MIO_PIN_66_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_66_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_66_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_66_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_66_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_66_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_66_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_66_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_66_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Comman - Indicator) 2= Not Used 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Com + * mand Indicator) = sd0, Output, sdio0_cmd_out- (Command Indicator) 2= Not + * Used 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_66_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_66_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_66_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_66_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_66_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_66_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_66_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_66_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_66_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[14]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[14]- (GPIO bank 2) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= tt - 2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace - Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[14]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[14]- (GPIO bank 2) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Mast + * er Selects) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_ + * rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace + * Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_66_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_66_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_66_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_66_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_66_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_66_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_66_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_66_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_66_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[2]- (TX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd + * [2]- (TX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_67_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_67_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_67_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_67_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_67_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_67_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_67_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_67_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_67_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_nxt- (Data flow control signal from the PHY)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_nxt- + * (Data flow control signal from the PHY) +*/ #undef IOU_SLCR_MIO_PIN_67_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_67_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_67_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_67_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_67_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_67_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_67_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_67_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_67_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8 - bit Data bus) 2= Not Used 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8-bit Data bus) 2= N + * ot Used 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_67_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_67_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_67_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_67_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_67_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_67_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_67_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_67_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_67_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[15]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[15]- (GPIO bank 2) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi - , Output, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd - (UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[15]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[15]- (GPIO bank 2) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi0, Input, spi0_n_ss_in- (SPI Maste + * r Selects) 4= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 5= tt + * c2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- + * (UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace + * Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_67_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_67_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_67_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_67_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_67_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_67_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_67_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_67_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_67_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[3]- (TX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd + * [3]- (TX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_68_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_68_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_68_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_68_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_68_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_68_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_68_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_68_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_68_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[0]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_ - ata[0]- (ULPI data bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[0]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[0]- (ULPI data + * bus) +*/ #undef IOU_SLCR_MIO_PIN_68_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_68_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_68_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_68_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_68_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_68_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_68_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_68_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_68_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8 - bit Data bus) 2= Not Used 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8-bit Data bus) 2= N + * ot Used 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_68_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_68_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_68_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_68_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_68_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_68_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_68_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_68_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_68_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[16]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[16]- (GPIO bank 2) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0 - so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace - Output, tracedq[14]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[16]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[16]- (GPIO bank 2) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= s + * pi0, Output, spi0_so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Cl + * ock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, + * Output, tracedq[14]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_68_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_68_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_68_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_68_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_68_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_68_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_68_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_68_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_68_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_ctl- (TX RGMII control)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_ + * ctl- (TX RGMII control) +*/ #undef IOU_SLCR_MIO_PIN_69_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_69_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_69_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_69_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_69_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_69_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_69_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_69_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_69_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[1]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_ - ata[1]- (ULPI data bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[1]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[1]- (ULPI data + * bus) +*/ #undef IOU_SLCR_MIO_PIN_69_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_69_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_69_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_69_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_69_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_69_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_69_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_69_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_69_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8 - bit Data bus) 2= sd1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8-bit Data bus) 2= s + * d1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_69_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_69_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_69_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_69_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_69_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_69_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_69_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_69_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_69_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[17]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[17]- (GPIO bank 2) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, sp - 0_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) - 7= trace, Output, tracedq[15]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[17]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[17]- (GPIO bank 2) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4 + * = spi0, Input, spi0_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (T + * TC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) + * 7= trace, Output, tracedq[15]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_69_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_69_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_69_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_69_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_69_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_69_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_69_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_69_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_69_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_clk- (RX RGMII clock)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_c + * lk- (RX RGMII clock) +*/ #undef IOU_SLCR_MIO_PIN_70_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_70_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_70_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_70_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_70_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_70_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_70_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_70_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_70_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Output, usb1_ulpi_stp- (Asserted to end or interrupt transfers)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Output, usb1_ulpi_stp- + * (Asserted to end or interrupt transfers) +*/ #undef IOU_SLCR_MIO_PIN_70_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_70_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_70_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_70_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_70_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_70_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_70_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_70_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_70_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8 - bit Data bus) 2= sd1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8-bit Data bus) 2= s + * d1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_70_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_70_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_70_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_70_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_70_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_70_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_70_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_70_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_70_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[18]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[18]- (GPIO bank 2) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, sp - 1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not - sed*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[18]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[18]- (GPIO bank 2) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= + * spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- ( + * TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not U + * sed +*/ #undef IOU_SLCR_MIO_PIN_70_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_70_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_70_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_70_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_70_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_70_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_70_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_70_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_70_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[0]- (RX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[ + * 0]- (RX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_71_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_71_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_71_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_71_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_71_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_71_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_71_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_71_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_71_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[3]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_ - ata[3]- (ULPI data bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[3]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[3]- (ULPI data + * bus) +*/ #undef IOU_SLCR_MIO_PIN_71_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_71_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_71_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_71_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_71_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_71_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_71_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_71_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_71_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8 - bit Data bus) 2= sd1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_out[0]- (8-bit Data bus) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[0]- (8-bit Data bus) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_71_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_71_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_71_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_71_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_71_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_71_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_71_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_71_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_71_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[19]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[19]- (GPIO bank 2) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5 - ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[19]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[19]- (GPIO bank 2) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI + * Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= + * ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used +*/ #undef IOU_SLCR_MIO_PIN_71_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_71_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_71_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_71_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_71_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_71_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_71_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_71_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_71_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[1]- (RX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[ + * 1]- (RX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_72_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_72_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_72_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_72_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_72_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_72_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_72_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_72_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_72_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[4]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_ - ata[4]- (ULPI data bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[4]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[4]- (ULPI data + * bus) +*/ #undef IOU_SLCR_MIO_PIN_72_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_72_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_72_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_72_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_72_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_72_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_72_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_72_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_72_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8 - bit Data bus) 2= sd1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_out[1]- (8-bit Data bus) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[1]- (8-bit Data bus) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_72_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_72_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_72_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_72_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_72_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_72_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_72_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_72_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_72_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[20]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[20]- (GPIO bank 2) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= N - t Used 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Used*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[20]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[20]- (GPIO bank 2) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Mas + * ter Selects) 5= Not Used 6= ua1, Output, ua1_txd- (UART transmitter seri + * al output) 7= Not Used +*/ #undef IOU_SLCR_MIO_PIN_72_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_72_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_72_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_72_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_72_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_72_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_72_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_72_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_72_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[2]- (RX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[ + * 2]- (RX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_73_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_73_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_73_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_73_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_73_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_73_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_73_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_73_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_73_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_ - ata[5]- (ULPI data bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[5]- (ULPI data + * bus) +*/ #undef IOU_SLCR_MIO_PIN_73_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_73_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_73_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_73_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_73_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_73_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_73_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_73_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_73_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8 - bit Data bus) 2= sd1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_out[2]- (8-bit Data bus) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[2]- (8-bit Data bus) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_73_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_73_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_73_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_73_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_73_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_73_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_73_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_73_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_73_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[21]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[21]- (GPIO bank 2) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1 - Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= Not Used 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[21]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[21]- (GPIO bank 2) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master + * Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= Not + * Used 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used +*/ #undef IOU_SLCR_MIO_PIN_73_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_73_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_73_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_73_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_73_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_73_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_73_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_73_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_73_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[3]- (RX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[ + * 3]- (RX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_74_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_74_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_74_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_74_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_74_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_74_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_74_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_74_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_74_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[6]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_ - ata[6]- (ULPI data bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[6]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[6]- (ULPI data + * bus) +*/ #undef IOU_SLCR_MIO_PIN_74_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_74_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_74_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_74_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_74_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_74_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_74_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_74_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_74_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8 - bit Data bus) 2= sd1, Input, sd1_data_in[3]- (8-bit Data bus) = sd1, Output, sdio1_data_out[3]- (8-bit Data bus) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[3]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[3]- (8-bit Data bus) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_74_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_74_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_74_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_74_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_74_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_74_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_74_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_74_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_74_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[22]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[22]- (GPIO bank 2) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_ - o- (MISO signal) 5= Not Used 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[22]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[22]- (GPIO bank 2) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= sp + * i1, Output, spi1_so- (MISO signal) 5= Not Used 6= ua0, Input, ua0_rxd- ( + * UART receiver serial input) 7= Not Used +*/ #undef IOU_SLCR_MIO_PIN_74_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_74_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_74_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_74_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_74_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_74_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_74_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_74_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_74_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_ctl- (RX RGMII control )*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_c + * tl- (RX RGMII control ) +*/ #undef IOU_SLCR_MIO_PIN_75_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_75_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_75_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_75_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_75_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_75_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_75_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_75_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_75_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[7]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_ - ata[7]- (ULPI data bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[7]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[7]- (ULPI data + * bus) +*/ #undef IOU_SLCR_MIO_PIN_75_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_75_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_75_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_75_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_75_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_75_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_75_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_75_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_75_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= sd1, Input, sd1_cmd_in- (Comma - d Indicator) = sd1, Output, sdio1_cmd_out- (Command Indicator) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- + * (SD card bus power) 2= sd1, Input, sd1_cmd_in- (Command Indicator) = sd1 + * , Output, sdio1_cmd_out- (Command Indicator) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_75_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_75_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_75_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_75_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_75_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_75_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_75_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_75_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_75_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[23]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[23]- (GPIO bank 2) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s - i1_si- (MOSI signal) 5= Not Used 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[23]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[23]- (GPIO bank 2) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) + * 4= spi1, Input, spi1_si- (MOSI signal) 5= Not Used 6= ua0, Output, ua0_t + * xd- (UART transmitter serial output) 7= Not Used +*/ #undef IOU_SLCR_MIO_PIN_75_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_75_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_75_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_75_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_75_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_75_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_75_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_75_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_75_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_76_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_76_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_76_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_76_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_76_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_76_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_76_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_76_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_76_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_76_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_76_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_76_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_76_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_76_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_76_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_76_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_76_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_76_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= sd1, Output, sdio - _clk_out- (SDSDIO clock) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD ca + * rd write protect from connector) 2= sd1, Output, sdio1_clk_out- (SDSDIO + * clock) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_76_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_76_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_76_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_76_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_76_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_76_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_76_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_76_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_76_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[24]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[24]- (GPIO bank 2) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= mdio0, Output, gem0_mdc- (MDIO Clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= mdio2, Output, gem2_mdc- (MDIO Clock - 6= mdio3, Output, gem3_mdc- (MDIO Clock) 7= Not Used*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[24]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[24]- (GPIO bank 2) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= mdio0, Output, gem0_mdc- (MDI + * O Clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= mdio2, Output, gem2 + * _mdc- (MDIO Clock) 6= mdio3, Output, gem3_mdc- (MDIO Clock) 7= Not Used +*/ #undef IOU_SLCR_MIO_PIN_76_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_76_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_76_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_76_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_76_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_76_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_76_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_76_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_76_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_77_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_77_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_77_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_77_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_77_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_77_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_77_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_77_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_77_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_77_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_77_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_77_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_77_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_77_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_77_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_77_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_77_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_77_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Input, sdio1_cd_n- (SD card detect from connector) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Input, sdio + * 1_cd_n- (SD card detect from connector) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_77_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_77_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_77_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_77_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_77_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_77_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_77_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_77_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_77_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[25]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[25]- (GPIO bank 2) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= mdio0, Input, gem0_mdio_in- (MDIO Data) 3= mdio0, Output, gem0_mdio_out- (MDIO Data) 4= mdio1, Input, gem1_mdio_in- (MD - O Data) 4= mdio1, Output, gem1_mdio_out- (MDIO Data) 5= mdio2, Input, gem2_mdio_in- (MDIO Data) 5= mdio2, Output, gem2_mdio_o - t- (MDIO Data) 6= mdio3, Input, gem3_mdio_in- (MDIO Data) 6= mdio3, Output, gem3_mdio_out- (MDIO Data) 7= Not Used*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[25]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[25]- (GPIO bank 2) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= mdio0, Input, gem0_mdio_in- (M + * DIO Data) 3= mdio0, Output, gem0_mdio_out- (MDIO Data) 4= mdio1, Input, + * gem1_mdio_in- (MDIO Data) 4= mdio1, Output, gem1_mdio_out- (MDIO Data) 5 + * = mdio2, Input, gem2_mdio_in- (MDIO Data) 5= mdio2, Output, gem2_mdio_ou + * t- (MDIO Data) 6= mdio3, Input, gem3_mdio_in- (MDIO Data) 6= mdio3, Outp + * ut, gem3_mdio_out- (MDIO Data) 7= Not Used +*/ #undef IOU_SLCR_MIO_PIN_77_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_77_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_77_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_77_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_77_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_77_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_77_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_77_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_77_L3_SEL_MASK 0x000000E0U -/*Master Tri-state Enable for pin 0, active high*/ +/* +* Master Tri-state Enable for pin 0, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_SHIFT 0 -#define IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_MASK 0x00000001U +#define IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_SHIFT 0 +#define IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_MASK 0x00000001U -/*Master Tri-state Enable for pin 1, active high*/ +/* +* Master Tri-state Enable for pin 1, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_SHIFT 1 -#define IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_MASK 0x00000002U +#define IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_SHIFT 1 +#define IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_MASK 0x00000002U -/*Master Tri-state Enable for pin 2, active high*/ +/* +* Master Tri-state Enable for pin 2, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_SHIFT 2 -#define IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_MASK 0x00000004U +#define IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_SHIFT 2 +#define IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_MASK 0x00000004U -/*Master Tri-state Enable for pin 3, active high*/ +/* +* Master Tri-state Enable for pin 3, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_SHIFT 3 -#define IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_MASK 0x00000008U +#define IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_SHIFT 3 +#define IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_MASK 0x00000008U -/*Master Tri-state Enable for pin 4, active high*/ +/* +* Master Tri-state Enable for pin 4, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_SHIFT 4 -#define IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_MASK 0x00000010U +#define IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_SHIFT 4 +#define IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_MASK 0x00000010U -/*Master Tri-state Enable for pin 5, active high*/ +/* +* Master Tri-state Enable for pin 5, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_SHIFT 5 -#define IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_MASK 0x00000020U +#define IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_SHIFT 5 +#define IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_MASK 0x00000020U -/*Master Tri-state Enable for pin 6, active high*/ +/* +* Master Tri-state Enable for pin 6, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_SHIFT 6 -#define IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_MASK 0x00000040U +#define IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_SHIFT 6 +#define IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_MASK 0x00000040U -/*Master Tri-state Enable for pin 7, active high*/ +/* +* Master Tri-state Enable for pin 7, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_SHIFT 7 -#define IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_MASK 0x00000080U +#define IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_SHIFT 7 +#define IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_MASK 0x00000080U -/*Master Tri-state Enable for pin 8, active high*/ +/* +* Master Tri-state Enable for pin 8, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_SHIFT 8 -#define IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_MASK 0x00000100U +#define IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_SHIFT 8 +#define IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_MASK 0x00000100U -/*Master Tri-state Enable for pin 9, active high*/ +/* +* Master Tri-state Enable for pin 9, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_SHIFT 9 -#define IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_MASK 0x00000200U +#define IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_SHIFT 9 +#define IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_MASK 0x00000200U -/*Master Tri-state Enable for pin 10, active high*/ +/* +* Master Tri-state Enable for pin 10, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_SHIFT 10 -#define IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_MASK 0x00000400U +#define IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_SHIFT 10 +#define IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_MASK 0x00000400U -/*Master Tri-state Enable for pin 11, active high*/ +/* +* Master Tri-state Enable for pin 11, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_SHIFT 11 -#define IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_MASK 0x00000800U +#define IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_SHIFT 11 +#define IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_MASK 0x00000800U -/*Master Tri-state Enable for pin 12, active high*/ +/* +* Master Tri-state Enable for pin 12, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_SHIFT 12 -#define IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_MASK 0x00001000U +#define IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_SHIFT 12 +#define IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_MASK 0x00001000U -/*Master Tri-state Enable for pin 13, active high*/ +/* +* Master Tri-state Enable for pin 13, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_SHIFT 13 -#define IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_MASK 0x00002000U +#define IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_SHIFT 13 +#define IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_MASK 0x00002000U -/*Master Tri-state Enable for pin 14, active high*/ +/* +* Master Tri-state Enable for pin 14, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_SHIFT 14 -#define IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_MASK 0x00004000U +#define IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_SHIFT 14 +#define IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_MASK 0x00004000U -/*Master Tri-state Enable for pin 15, active high*/ +/* +* Master Tri-state Enable for pin 15, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_SHIFT 15 -#define IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_MASK 0x00008000U +#define IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_SHIFT 15 +#define IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_MASK 0x00008000U -/*Master Tri-state Enable for pin 16, active high*/ +/* +* Master Tri-state Enable for pin 16, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_SHIFT 16 -#define IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_MASK 0x00010000U +#define IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_SHIFT 16 +#define IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_MASK 0x00010000U -/*Master Tri-state Enable for pin 17, active high*/ +/* +* Master Tri-state Enable for pin 17, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_SHIFT 17 -#define IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_MASK 0x00020000U +#define IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_SHIFT 17 +#define IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_MASK 0x00020000U -/*Master Tri-state Enable for pin 18, active high*/ +/* +* Master Tri-state Enable for pin 18, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_SHIFT 18 -#define IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_MASK 0x00040000U +#define IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_SHIFT 18 +#define IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_MASK 0x00040000U -/*Master Tri-state Enable for pin 19, active high*/ +/* +* Master Tri-state Enable for pin 19, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_SHIFT 19 -#define IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_MASK 0x00080000U +#define IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_SHIFT 19 +#define IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_MASK 0x00080000U -/*Master Tri-state Enable for pin 20, active high*/ +/* +* Master Tri-state Enable for pin 20, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_SHIFT 20 -#define IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_MASK 0x00100000U +#define IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_SHIFT 20 +#define IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_MASK 0x00100000U -/*Master Tri-state Enable for pin 21, active high*/ +/* +* Master Tri-state Enable for pin 21, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_SHIFT 21 -#define IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_MASK 0x00200000U +#define IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_SHIFT 21 +#define IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_MASK 0x00200000U -/*Master Tri-state Enable for pin 22, active high*/ +/* +* Master Tri-state Enable for pin 22, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_SHIFT 22 -#define IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_MASK 0x00400000U +#define IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_SHIFT 22 +#define IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_MASK 0x00400000U -/*Master Tri-state Enable for pin 23, active high*/ +/* +* Master Tri-state Enable for pin 23, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_SHIFT 23 -#define IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_MASK 0x00800000U +#define IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_SHIFT 23 +#define IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_MASK 0x00800000U -/*Master Tri-state Enable for pin 24, active high*/ +/* +* Master Tri-state Enable for pin 24, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_SHIFT 24 -#define IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_MASK 0x01000000U +#define IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_SHIFT 24 +#define IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_MASK 0x01000000U -/*Master Tri-state Enable for pin 25, active high*/ +/* +* Master Tri-state Enable for pin 25, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_SHIFT 25 -#define IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_MASK 0x02000000U +#define IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_SHIFT 25 +#define IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_MASK 0x02000000U -/*Master Tri-state Enable for pin 26, active high*/ +/* +* Master Tri-state Enable for pin 26, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_SHIFT 26 -#define IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_MASK 0x04000000U +#define IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_SHIFT 26 +#define IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_MASK 0x04000000U -/*Master Tri-state Enable for pin 27, active high*/ +/* +* Master Tri-state Enable for pin 27, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_SHIFT 27 -#define IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_MASK 0x08000000U +#define IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_SHIFT 27 +#define IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_MASK 0x08000000U -/*Master Tri-state Enable for pin 28, active high*/ +/* +* Master Tri-state Enable for pin 28, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_SHIFT 28 -#define IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_MASK 0x10000000U +#define IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_SHIFT 28 +#define IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_MASK 0x10000000U -/*Master Tri-state Enable for pin 29, active high*/ +/* +* Master Tri-state Enable for pin 29, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_SHIFT 29 -#define IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_MASK 0x20000000U +#define IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_SHIFT 29 +#define IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_MASK 0x20000000U -/*Master Tri-state Enable for pin 30, active high*/ +/* +* Master Tri-state Enable for pin 30, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_SHIFT 30 -#define IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_MASK 0x40000000U +#define IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_SHIFT 30 +#define IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_MASK 0x40000000U -/*Master Tri-state Enable for pin 31, active high*/ +/* +* Master Tri-state Enable for pin 31, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_SHIFT 31 -#define IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_MASK 0x80000000U +#define IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_SHIFT 31 +#define IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_MASK 0x80000000U -/*Master Tri-state Enable for pin 32, active high*/ +/* +* Master Tri-state Enable for pin 32, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_SHIFT 0 -#define IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_MASK 0x00000001U +#define IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_SHIFT 0 +#define IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_MASK 0x00000001U -/*Master Tri-state Enable for pin 33, active high*/ +/* +* Master Tri-state Enable for pin 33, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_SHIFT 1 -#define IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_MASK 0x00000002U +#define IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_SHIFT 1 +#define IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_MASK 0x00000002U -/*Master Tri-state Enable for pin 34, active high*/ +/* +* Master Tri-state Enable for pin 34, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_SHIFT 2 -#define IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_MASK 0x00000004U +#define IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_SHIFT 2 +#define IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_MASK 0x00000004U -/*Master Tri-state Enable for pin 35, active high*/ +/* +* Master Tri-state Enable for pin 35, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_SHIFT 3 -#define IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_MASK 0x00000008U +#define IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_SHIFT 3 +#define IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_MASK 0x00000008U -/*Master Tri-state Enable for pin 36, active high*/ +/* +* Master Tri-state Enable for pin 36, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_SHIFT 4 -#define IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_MASK 0x00000010U +#define IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_SHIFT 4 +#define IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_MASK 0x00000010U -/*Master Tri-state Enable for pin 37, active high*/ +/* +* Master Tri-state Enable for pin 37, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_SHIFT 5 -#define IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_MASK 0x00000020U +#define IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_SHIFT 5 +#define IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_MASK 0x00000020U -/*Master Tri-state Enable for pin 38, active high*/ +/* +* Master Tri-state Enable for pin 38, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_SHIFT 6 -#define IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_MASK 0x00000040U +#define IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_SHIFT 6 +#define IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_MASK 0x00000040U -/*Master Tri-state Enable for pin 39, active high*/ +/* +* Master Tri-state Enable for pin 39, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_SHIFT 7 -#define IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_MASK 0x00000080U +#define IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_SHIFT 7 +#define IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_MASK 0x00000080U -/*Master Tri-state Enable for pin 40, active high*/ +/* +* Master Tri-state Enable for pin 40, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_SHIFT 8 -#define IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_MASK 0x00000100U +#define IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_SHIFT 8 +#define IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_MASK 0x00000100U -/*Master Tri-state Enable for pin 41, active high*/ +/* +* Master Tri-state Enable for pin 41, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_SHIFT 9 -#define IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_MASK 0x00000200U +#define IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_SHIFT 9 +#define IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_MASK 0x00000200U -/*Master Tri-state Enable for pin 42, active high*/ +/* +* Master Tri-state Enable for pin 42, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_SHIFT 10 -#define IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_MASK 0x00000400U +#define IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_SHIFT 10 +#define IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_MASK 0x00000400U -/*Master Tri-state Enable for pin 43, active high*/ +/* +* Master Tri-state Enable for pin 43, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_SHIFT 11 -#define IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_MASK 0x00000800U +#define IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_SHIFT 11 +#define IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_MASK 0x00000800U -/*Master Tri-state Enable for pin 44, active high*/ +/* +* Master Tri-state Enable for pin 44, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_SHIFT 12 -#define IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_MASK 0x00001000U +#define IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_SHIFT 12 +#define IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_MASK 0x00001000U -/*Master Tri-state Enable for pin 45, active high*/ +/* +* Master Tri-state Enable for pin 45, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_SHIFT 13 -#define IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_MASK 0x00002000U +#define IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_SHIFT 13 +#define IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_MASK 0x00002000U -/*Master Tri-state Enable for pin 46, active high*/ +/* +* Master Tri-state Enable for pin 46, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_SHIFT 14 -#define IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_MASK 0x00004000U +#define IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_SHIFT 14 +#define IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_MASK 0x00004000U -/*Master Tri-state Enable for pin 47, active high*/ +/* +* Master Tri-state Enable for pin 47, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_SHIFT 15 -#define IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_MASK 0x00008000U +#define IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_SHIFT 15 +#define IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_MASK 0x00008000U -/*Master Tri-state Enable for pin 48, active high*/ +/* +* Master Tri-state Enable for pin 48, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_SHIFT 16 -#define IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_MASK 0x00010000U +#define IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_SHIFT 16 +#define IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_MASK 0x00010000U -/*Master Tri-state Enable for pin 49, active high*/ +/* +* Master Tri-state Enable for pin 49, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_SHIFT 17 -#define IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_MASK 0x00020000U +#define IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_SHIFT 17 +#define IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_MASK 0x00020000U -/*Master Tri-state Enable for pin 50, active high*/ +/* +* Master Tri-state Enable for pin 50, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_SHIFT 18 -#define IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_MASK 0x00040000U +#define IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_SHIFT 18 +#define IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_MASK 0x00040000U -/*Master Tri-state Enable for pin 51, active high*/ +/* +* Master Tri-state Enable for pin 51, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_SHIFT 19 -#define IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_MASK 0x00080000U +#define IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_SHIFT 19 +#define IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_MASK 0x00080000U -/*Master Tri-state Enable for pin 52, active high*/ +/* +* Master Tri-state Enable for pin 52, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_SHIFT 20 -#define IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_MASK 0x00100000U +#define IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_SHIFT 20 +#define IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_MASK 0x00100000U -/*Master Tri-state Enable for pin 53, active high*/ +/* +* Master Tri-state Enable for pin 53, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_SHIFT 21 -#define IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_MASK 0x00200000U +#define IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_SHIFT 21 +#define IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_MASK 0x00200000U -/*Master Tri-state Enable for pin 54, active high*/ +/* +* Master Tri-state Enable for pin 54, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_SHIFT 22 -#define IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_MASK 0x00400000U +#define IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_SHIFT 22 +#define IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_MASK 0x00400000U -/*Master Tri-state Enable for pin 55, active high*/ +/* +* Master Tri-state Enable for pin 55, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_SHIFT 23 -#define IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_MASK 0x00800000U +#define IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_SHIFT 23 +#define IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_MASK 0x00800000U -/*Master Tri-state Enable for pin 56, active high*/ +/* +* Master Tri-state Enable for pin 56, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_SHIFT 24 -#define IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_MASK 0x01000000U +#define IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_SHIFT 24 +#define IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_MASK 0x01000000U -/*Master Tri-state Enable for pin 57, active high*/ +/* +* Master Tri-state Enable for pin 57, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_SHIFT 25 -#define IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_MASK 0x02000000U +#define IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_SHIFT 25 +#define IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_MASK 0x02000000U -/*Master Tri-state Enable for pin 58, active high*/ +/* +* Master Tri-state Enable for pin 58, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_SHIFT 26 -#define IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_MASK 0x04000000U +#define IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_SHIFT 26 +#define IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_MASK 0x04000000U -/*Master Tri-state Enable for pin 59, active high*/ +/* +* Master Tri-state Enable for pin 59, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_SHIFT 27 -#define IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_MASK 0x08000000U +#define IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_SHIFT 27 +#define IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_MASK 0x08000000U -/*Master Tri-state Enable for pin 60, active high*/ +/* +* Master Tri-state Enable for pin 60, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_SHIFT 28 -#define IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_MASK 0x10000000U +#define IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_SHIFT 28 +#define IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_MASK 0x10000000U -/*Master Tri-state Enable for pin 61, active high*/ +/* +* Master Tri-state Enable for pin 61, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_SHIFT 29 -#define IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_MASK 0x20000000U +#define IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_SHIFT 29 +#define IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_MASK 0x20000000U -/*Master Tri-state Enable for pin 62, active high*/ +/* +* Master Tri-state Enable for pin 62, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_SHIFT 30 -#define IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_MASK 0x40000000U +#define IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_SHIFT 30 +#define IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_MASK 0x40000000U -/*Master Tri-state Enable for pin 63, active high*/ +/* +* Master Tri-state Enable for pin 63, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_SHIFT 31 -#define IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_MASK 0x80000000U +#define IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_SHIFT 31 +#define IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_MASK 0x80000000U -/*Master Tri-state Enable for pin 64, active high*/ +/* +* Master Tri-state Enable for pin 64, active high +*/ #undef IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_DEFVAL 0x00003FFF -#define IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_SHIFT 0 -#define IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_MASK 0x00000001U +#define IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_DEFVAL 0x00003FFF +#define IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_SHIFT 0 +#define IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_MASK 0x00000001U -/*Master Tri-state Enable for pin 65, active high*/ +/* +* Master Tri-state Enable for pin 65, active high +*/ #undef IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_DEFVAL 0x00003FFF -#define IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_SHIFT 1 -#define IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_MASK 0x00000002U +#define IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_DEFVAL 0x00003FFF +#define IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_SHIFT 1 +#define IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_MASK 0x00000002U -/*Master Tri-state Enable for pin 66, active high*/ +/* +* Master Tri-state Enable for pin 66, active high +*/ #undef IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_DEFVAL 0x00003FFF -#define IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_SHIFT 2 -#define IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_MASK 0x00000004U +#define IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_DEFVAL 0x00003FFF +#define IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_SHIFT 2 +#define IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_MASK 0x00000004U -/*Master Tri-state Enable for pin 67, active high*/ +/* +* Master Tri-state Enable for pin 67, active high +*/ #undef IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_DEFVAL 0x00003FFF -#define IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_SHIFT 3 -#define IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_MASK 0x00000008U +#define IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_DEFVAL 0x00003FFF +#define IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_SHIFT 3 +#define IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_MASK 0x00000008U -/*Master Tri-state Enable for pin 68, active high*/ +/* +* Master Tri-state Enable for pin 68, active high +*/ #undef IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_DEFVAL 0x00003FFF -#define IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_SHIFT 4 -#define IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_MASK 0x00000010U +#define IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_DEFVAL 0x00003FFF +#define IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_SHIFT 4 +#define IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_MASK 0x00000010U -/*Master Tri-state Enable for pin 69, active high*/ +/* +* Master Tri-state Enable for pin 69, active high +*/ #undef IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_DEFVAL 0x00003FFF -#define IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_SHIFT 5 -#define IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_MASK 0x00000020U +#define IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_DEFVAL 0x00003FFF +#define IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_SHIFT 5 +#define IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_MASK 0x00000020U -/*Master Tri-state Enable for pin 70, active high*/ +/* +* Master Tri-state Enable for pin 70, active high +*/ #undef IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_DEFVAL 0x00003FFF -#define IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_SHIFT 6 -#define IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_MASK 0x00000040U +#define IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_DEFVAL 0x00003FFF +#define IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_SHIFT 6 +#define IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_MASK 0x00000040U -/*Master Tri-state Enable for pin 71, active high*/ +/* +* Master Tri-state Enable for pin 71, active high +*/ #undef IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_DEFVAL 0x00003FFF -#define IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_SHIFT 7 -#define IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_MASK 0x00000080U +#define IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_DEFVAL 0x00003FFF +#define IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_SHIFT 7 +#define IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_MASK 0x00000080U -/*Master Tri-state Enable for pin 72, active high*/ +/* +* Master Tri-state Enable for pin 72, active high +*/ #undef IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_DEFVAL 0x00003FFF -#define IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_SHIFT 8 -#define IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_MASK 0x00000100U +#define IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_DEFVAL 0x00003FFF +#define IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_SHIFT 8 +#define IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_MASK 0x00000100U -/*Master Tri-state Enable for pin 73, active high*/ +/* +* Master Tri-state Enable for pin 73, active high +*/ #undef IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_DEFVAL 0x00003FFF -#define IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_SHIFT 9 -#define IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_MASK 0x00000200U +#define IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_DEFVAL 0x00003FFF +#define IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_SHIFT 9 +#define IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_MASK 0x00000200U -/*Master Tri-state Enable for pin 74, active high*/ +/* +* Master Tri-state Enable for pin 74, active high +*/ #undef IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_DEFVAL 0x00003FFF -#define IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_SHIFT 10 -#define IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_MASK 0x00000400U +#define IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_DEFVAL 0x00003FFF +#define IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_SHIFT 10 +#define IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_MASK 0x00000400U -/*Master Tri-state Enable for pin 75, active high*/ +/* +* Master Tri-state Enable for pin 75, active high +*/ #undef IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_DEFVAL 0x00003FFF -#define IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_SHIFT 11 -#define IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_MASK 0x00000800U +#define IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_DEFVAL 0x00003FFF +#define IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_SHIFT 11 +#define IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_MASK 0x00000800U -/*Master Tri-state Enable for pin 76, active high*/ +/* +* Master Tri-state Enable for pin 76, active high +*/ #undef IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_DEFVAL 0x00003FFF -#define IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_SHIFT 12 -#define IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_MASK 0x00001000U +#define IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_DEFVAL 0x00003FFF +#define IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_SHIFT 12 +#define IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_MASK 0x00001000U -/*Master Tri-state Enable for pin 77, active high*/ +/* +* Master Tri-state Enable for pin 77, active high +*/ #undef IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_DEFVAL 0x00003FFF -#define IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_SHIFT 13 -#define IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_MASK 0x00002000U +#define IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_DEFVAL 0x00003FFF +#define IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_SHIFT 13 +#define IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_MASK 0x00002000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_SHIFT 0 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_MASK 0x00000001U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_MASK 0x00000001U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_SHIFT 1 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_MASK 0x00000002U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_MASK 0x00000002U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_SHIFT 2 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_MASK 0x00000004U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_MASK 0x00000004U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_SHIFT 3 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_MASK 0x00000008U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_MASK 0x00000008U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_SHIFT 4 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_MASK 0x00000010U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_MASK 0x00000010U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_SHIFT 5 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_MASK 0x00000020U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_MASK 0x00000020U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_SHIFT 6 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_MASK 0x00000040U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_MASK 0x00000040U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_SHIFT 7 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_MASK 0x00000080U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_MASK 0x00000080U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_SHIFT 8 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_MASK 0x00000100U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_MASK 0x00000100U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_SHIFT 9 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_MASK 0x00000200U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_MASK 0x00000200U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_SHIFT 10 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_MASK 0x00000400U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_MASK 0x00000400U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_SHIFT 11 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_MASK 0x00000800U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_MASK 0x00000800U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_SHIFT 12 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_MASK 0x00001000U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_MASK 0x00001000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_SHIFT 13 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_MASK 0x00002000U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_MASK 0x00002000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_SHIFT 14 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_MASK 0x00004000U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_MASK 0x00004000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_SHIFT 15 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_MASK 0x00008000U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_MASK 0x00008000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_SHIFT 16 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_MASK 0x00010000U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_MASK 0x00010000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_SHIFT 17 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_MASK 0x00020000U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_MASK 0x00020000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_SHIFT 18 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_MASK 0x00040000U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_MASK 0x00040000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_SHIFT 19 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_MASK 0x00080000U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_MASK 0x00080000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_SHIFT 20 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_MASK 0x00100000U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_MASK 0x00100000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_SHIFT 21 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_MASK 0x00200000U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_MASK 0x00200000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_SHIFT 22 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_MASK 0x00400000U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_MASK 0x00400000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_SHIFT 23 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_MASK 0x00800000U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_MASK 0x00800000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_SHIFT 24 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_MASK 0x01000000U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_MASK 0x01000000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_SHIFT 25 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_MASK 0x02000000U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_MASK 0x02000000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_SHIFT 0 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_MASK 0x00000001U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_MASK 0x00000001U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_SHIFT 1 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_MASK 0x00000002U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_MASK 0x00000002U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_SHIFT 2 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_MASK 0x00000004U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_MASK 0x00000004U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_SHIFT 3 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_MASK 0x00000008U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_MASK 0x00000008U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_SHIFT 4 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_MASK 0x00000010U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_MASK 0x00000010U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_SHIFT 5 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_MASK 0x00000020U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_MASK 0x00000020U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_SHIFT 6 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_MASK 0x00000040U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_MASK 0x00000040U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_SHIFT 7 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_MASK 0x00000080U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_MASK 0x00000080U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_SHIFT 8 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_MASK 0x00000100U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_MASK 0x00000100U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_SHIFT 9 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_MASK 0x00000200U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_MASK 0x00000200U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_SHIFT 10 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_MASK 0x00000400U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_MASK 0x00000400U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_SHIFT 11 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_MASK 0x00000800U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_MASK 0x00000800U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_SHIFT 12 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_MASK 0x00001000U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_MASK 0x00001000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_SHIFT 13 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_MASK 0x00002000U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_MASK 0x00002000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_SHIFT 14 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_MASK 0x00004000U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_MASK 0x00004000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_SHIFT 15 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_MASK 0x00008000U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_MASK 0x00008000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_SHIFT 16 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_MASK 0x00010000U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_MASK 0x00010000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_SHIFT 17 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_MASK 0x00020000U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_MASK 0x00020000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_SHIFT 18 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_MASK 0x00040000U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_MASK 0x00040000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_SHIFT 19 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_MASK 0x00080000U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_MASK 0x00080000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_SHIFT 20 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_MASK 0x00100000U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_MASK 0x00100000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_SHIFT 21 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_MASK 0x00200000U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_MASK 0x00200000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_SHIFT 22 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_MASK 0x00400000U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_MASK 0x00400000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_SHIFT 23 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_MASK 0x00800000U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_MASK 0x00800000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_SHIFT 24 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_MASK 0x01000000U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_MASK 0x01000000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_SHIFT 25 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_MASK 0x02000000U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_MASK 0x02000000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT 0 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK 0x00000001U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK 0x00000001U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT 1 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK 0x00000002U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK 0x00000002U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT 2 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK 0x00000004U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK 0x00000004U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT 3 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK 0x00000008U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK 0x00000008U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT 4 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK 0x00000010U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK 0x00000010U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT 5 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK 0x00000020U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK 0x00000020U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT 6 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK 0x00000040U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK 0x00000040U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT 7 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK 0x00000080U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK 0x00000080U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT 8 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK 0x00000100U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK 0x00000100U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT 9 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK 0x00000200U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK 0x00000200U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT 10 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK 0x00000400U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK 0x00000400U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT 11 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK 0x00000800U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK 0x00000800U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT 12 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK 0x00001000U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK 0x00001000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT 13 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK 0x00002000U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK 0x00002000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT 14 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK 0x00004000U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK 0x00004000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT 15 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK 0x00008000U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK 0x00008000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT 16 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK 0x00010000U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK 0x00010000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT 17 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK 0x00020000U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK 0x00020000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT 18 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK 0x00040000U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK 0x00040000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT 19 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK 0x00080000U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK 0x00080000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT 20 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK 0x00100000U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK 0x00100000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT 21 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK 0x00200000U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK 0x00200000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT 22 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK 0x00400000U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK 0x00400000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT 23 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK 0x00800000U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK 0x00800000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT 24 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK 0x01000000U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK 0x01000000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT 25 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK 0x02000000U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK 0x02000000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT 0 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK 0x00000001U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK 0x00000001U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT 1 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK 0x00000002U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK 0x00000002U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT 2 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK 0x00000004U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK 0x00000004U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT 3 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK 0x00000008U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK 0x00000008U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT 4 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK 0x00000010U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK 0x00000010U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT 5 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK 0x00000020U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK 0x00000020U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT 6 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK 0x00000040U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK 0x00000040U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT 7 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK 0x00000080U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK 0x00000080U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT 8 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK 0x00000100U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK 0x00000100U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT 9 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK 0x00000200U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK 0x00000200U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT 10 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK 0x00000400U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK 0x00000400U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT 11 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK 0x00000800U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK 0x00000800U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT 12 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK 0x00001000U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK 0x00001000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT 13 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK 0x00002000U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK 0x00002000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT 14 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK 0x00004000U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK 0x00004000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT 15 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK 0x00008000U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK 0x00008000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT 16 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK 0x00010000U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK 0x00010000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT 17 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK 0x00020000U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK 0x00020000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT 18 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK 0x00040000U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK 0x00040000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT 19 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK 0x00080000U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK 0x00080000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT 20 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK 0x00100000U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK 0x00100000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT 21 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK 0x00200000U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK 0x00200000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT 22 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK 0x00400000U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK 0x00400000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT 23 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK 0x00800000U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK 0x00800000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT 24 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK 0x01000000U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK 0x01000000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT 25 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK 0x02000000U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK 0x02000000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_SHIFT 0 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_MASK 0x00000001U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_MASK 0x00000001U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_SHIFT 1 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_MASK 0x00000002U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_MASK 0x00000002U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_SHIFT 2 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_MASK 0x00000004U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_MASK 0x00000004U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_SHIFT 3 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_MASK 0x00000008U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_MASK 0x00000008U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_SHIFT 4 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_MASK 0x00000010U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_MASK 0x00000010U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_SHIFT 5 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_MASK 0x00000020U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_MASK 0x00000020U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_SHIFT 6 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_MASK 0x00000040U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_MASK 0x00000040U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_SHIFT 7 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_MASK 0x00000080U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_MASK 0x00000080U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_SHIFT 8 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_MASK 0x00000100U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_MASK 0x00000100U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_SHIFT 9 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_MASK 0x00000200U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_MASK 0x00000200U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_SHIFT 10 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_MASK 0x00000400U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_MASK 0x00000400U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_SHIFT 11 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_MASK 0x00000800U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_MASK 0x00000800U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_SHIFT 12 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_MASK 0x00001000U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_MASK 0x00001000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_SHIFT 13 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_MASK 0x00002000U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_MASK 0x00002000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_SHIFT 14 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_MASK 0x00004000U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_MASK 0x00004000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_SHIFT 15 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_MASK 0x00008000U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_MASK 0x00008000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_SHIFT 16 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_MASK 0x00010000U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_MASK 0x00010000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_SHIFT 17 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_MASK 0x00020000U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_MASK 0x00020000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_SHIFT 18 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_MASK 0x00040000U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_MASK 0x00040000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_SHIFT 19 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_MASK 0x00080000U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_MASK 0x00080000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_SHIFT 20 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_MASK 0x00100000U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_MASK 0x00100000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_SHIFT 21 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_MASK 0x00200000U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_MASK 0x00200000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_SHIFT 22 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_MASK 0x00400000U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_MASK 0x00400000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_SHIFT 23 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_MASK 0x00800000U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_MASK 0x00800000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_SHIFT 24 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_MASK 0x01000000U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_MASK 0x01000000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_SHIFT 25 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_MASK 0x02000000U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_MASK 0x02000000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT 0 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK 0x00000001U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK 0x00000001U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT 1 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK 0x00000002U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK 0x00000002U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT 2 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK 0x00000004U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK 0x00000004U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT 3 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK 0x00000008U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK 0x00000008U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT 4 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK 0x00000010U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK 0x00000010U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT 5 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK 0x00000020U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK 0x00000020U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT 6 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK 0x00000040U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK 0x00000040U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT 7 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK 0x00000080U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK 0x00000080U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT 8 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK 0x00000100U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK 0x00000100U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT 9 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK 0x00000200U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK 0x00000200U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT 10 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK 0x00000400U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK 0x00000400U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT 11 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK 0x00000800U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK 0x00000800U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT 12 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK 0x00001000U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK 0x00001000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT 13 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK 0x00002000U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK 0x00002000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT 14 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK 0x00004000U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK 0x00004000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT 15 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK 0x00008000U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK 0x00008000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT 16 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK 0x00010000U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK 0x00010000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT 17 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK 0x00020000U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK 0x00020000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT 18 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK 0x00040000U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK 0x00040000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT 19 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK 0x00080000U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK 0x00080000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT 20 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK 0x00100000U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK 0x00100000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT 21 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK 0x00200000U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK 0x00200000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT 22 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK 0x00400000U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK 0x00400000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT 23 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK 0x00800000U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK 0x00800000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT 24 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK 0x01000000U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK 0x01000000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT 25 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK 0x02000000U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK 0x02000000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_SHIFT 0 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_MASK 0x00000001U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_MASK 0x00000001U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_SHIFT 1 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_MASK 0x00000002U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_MASK 0x00000002U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_SHIFT 2 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_MASK 0x00000004U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_MASK 0x00000004U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_SHIFT 3 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_MASK 0x00000008U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_MASK 0x00000008U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_SHIFT 4 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_MASK 0x00000010U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_MASK 0x00000010U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_SHIFT 5 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_MASK 0x00000020U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_MASK 0x00000020U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_SHIFT 6 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_MASK 0x00000040U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_MASK 0x00000040U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_SHIFT 7 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_MASK 0x00000080U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_MASK 0x00000080U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_SHIFT 8 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_MASK 0x00000100U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_MASK 0x00000100U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_SHIFT 9 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_MASK 0x00000200U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_MASK 0x00000200U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_SHIFT 10 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_MASK 0x00000400U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_MASK 0x00000400U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_SHIFT 11 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_MASK 0x00000800U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_MASK 0x00000800U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_SHIFT 12 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_MASK 0x00001000U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_MASK 0x00001000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_SHIFT 13 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_MASK 0x00002000U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_MASK 0x00002000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_SHIFT 14 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_MASK 0x00004000U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_MASK 0x00004000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_SHIFT 15 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_MASK 0x00008000U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_MASK 0x00008000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_SHIFT 16 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_MASK 0x00010000U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_MASK 0x00010000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_SHIFT 17 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_MASK 0x00020000U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_MASK 0x00020000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_SHIFT 18 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_MASK 0x00040000U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_MASK 0x00040000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_SHIFT 19 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_MASK 0x00080000U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_MASK 0x00080000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_SHIFT 20 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_MASK 0x00100000U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_MASK 0x00100000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_SHIFT 21 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_MASK 0x00200000U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_MASK 0x00200000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_SHIFT 22 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_MASK 0x00400000U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_MASK 0x00400000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_SHIFT 23 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_MASK 0x00800000U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_MASK 0x00800000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_SHIFT 24 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_MASK 0x01000000U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_MASK 0x01000000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_SHIFT 25 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_MASK 0x02000000U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_MASK 0x02000000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_SHIFT 0 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_MASK 0x00000001U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_MASK 0x00000001U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_SHIFT 1 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_MASK 0x00000002U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_MASK 0x00000002U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_SHIFT 2 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_MASK 0x00000004U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_MASK 0x00000004U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_SHIFT 3 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_MASK 0x00000008U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_MASK 0x00000008U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_SHIFT 4 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_MASK 0x00000010U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_MASK 0x00000010U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_SHIFT 5 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_MASK 0x00000020U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_MASK 0x00000020U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_SHIFT 6 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_MASK 0x00000040U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_MASK 0x00000040U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_SHIFT 7 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_MASK 0x00000080U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_MASK 0x00000080U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_SHIFT 8 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_MASK 0x00000100U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_MASK 0x00000100U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_SHIFT 9 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_MASK 0x00000200U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_MASK 0x00000200U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_SHIFT 10 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_MASK 0x00000400U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_MASK 0x00000400U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_SHIFT 11 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_MASK 0x00000800U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_MASK 0x00000800U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_SHIFT 12 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_MASK 0x00001000U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_MASK 0x00001000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_SHIFT 13 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_MASK 0x00002000U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_MASK 0x00002000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_SHIFT 14 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_MASK 0x00004000U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_MASK 0x00004000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_SHIFT 15 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_MASK 0x00008000U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_MASK 0x00008000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_SHIFT 16 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_MASK 0x00010000U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_MASK 0x00010000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_SHIFT 17 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_MASK 0x00020000U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_MASK 0x00020000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_SHIFT 18 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_MASK 0x00040000U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_MASK 0x00040000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_SHIFT 19 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_MASK 0x00080000U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_MASK 0x00080000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_SHIFT 20 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_MASK 0x00100000U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_MASK 0x00100000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_SHIFT 21 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_MASK 0x00200000U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_MASK 0x00200000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_SHIFT 22 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_MASK 0x00400000U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_MASK 0x00400000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_SHIFT 23 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_MASK 0x00800000U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_MASK 0x00800000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_SHIFT 24 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_MASK 0x01000000U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_MASK 0x01000000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_SHIFT 25 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_MASK 0x02000000U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_MASK 0x02000000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT 0 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK 0x00000001U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK 0x00000001U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT 1 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK 0x00000002U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK 0x00000002U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT 2 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK 0x00000004U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK 0x00000004U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT 3 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK 0x00000008U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK 0x00000008U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT 4 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK 0x00000010U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK 0x00000010U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT 5 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK 0x00000020U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK 0x00000020U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT 6 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK 0x00000040U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK 0x00000040U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT 7 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK 0x00000080U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK 0x00000080U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT 8 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK 0x00000100U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK 0x00000100U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT 9 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK 0x00000200U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK 0x00000200U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT 10 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK 0x00000400U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK 0x00000400U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT 11 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK 0x00000800U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK 0x00000800U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT 12 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK 0x00001000U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK 0x00001000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT 13 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK 0x00002000U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK 0x00002000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT 14 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK 0x00004000U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK 0x00004000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT 15 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK 0x00008000U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK 0x00008000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT 16 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK 0x00010000U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK 0x00010000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT 17 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK 0x00020000U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK 0x00020000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT 18 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK 0x00040000U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK 0x00040000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT 19 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK 0x00080000U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK 0x00080000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT 20 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK 0x00100000U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK 0x00100000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT 21 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK 0x00200000U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK 0x00200000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT 22 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK 0x00400000U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK 0x00400000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT 23 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK 0x00800000U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK 0x00800000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT 24 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK 0x01000000U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK 0x01000000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT 25 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK 0x02000000U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK 0x02000000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT 0 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK 0x00000001U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK 0x00000001U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT 1 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK 0x00000002U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK 0x00000002U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT 2 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK 0x00000004U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK 0x00000004U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT 3 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK 0x00000008U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK 0x00000008U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT 4 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK 0x00000010U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK 0x00000010U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT 5 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK 0x00000020U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK 0x00000020U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT 6 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK 0x00000040U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK 0x00000040U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT 7 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK 0x00000080U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK 0x00000080U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT 8 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK 0x00000100U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK 0x00000100U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT 9 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK 0x00000200U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK 0x00000200U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT 10 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK 0x00000400U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK 0x00000400U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT 11 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK 0x00000800U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK 0x00000800U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT 12 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK 0x00001000U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK 0x00001000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT 13 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK 0x00002000U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK 0x00002000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT 14 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK 0x00004000U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK 0x00004000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT 15 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK 0x00008000U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK 0x00008000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT 16 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK 0x00010000U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK 0x00010000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT 17 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK 0x00020000U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK 0x00020000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT 18 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK 0x00040000U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK 0x00040000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT 19 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK 0x00080000U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK 0x00080000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT 20 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK 0x00100000U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK 0x00100000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT 21 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK 0x00200000U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK 0x00200000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT 22 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK 0x00400000U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK 0x00400000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT 23 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK 0x00800000U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK 0x00800000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT 24 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK 0x01000000U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK 0x01000000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT 25 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK 0x02000000U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK 0x02000000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_SHIFT 12 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_MASK 0x00001000U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_SHIFT 12 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_MASK 0x00001000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_SHIFT 13 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_MASK 0x00002000U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_SHIFT 13 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_MASK 0x00002000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_SHIFT 14 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_MASK 0x00004000U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_SHIFT 14 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_MASK 0x00004000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_SHIFT 15 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_MASK 0x00008000U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_SHIFT 15 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_MASK 0x00008000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_SHIFT 16 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_MASK 0x00010000U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_SHIFT 16 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_MASK 0x00010000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_SHIFT 17 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_MASK 0x00020000U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_SHIFT 17 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_MASK 0x00020000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_SHIFT 18 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_MASK 0x00040000U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_SHIFT 18 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_MASK 0x00040000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_SHIFT 19 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_MASK 0x00080000U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_SHIFT 19 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_MASK 0x00080000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_SHIFT 20 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_MASK 0x00100000U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_SHIFT 20 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_MASK 0x00100000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_SHIFT 21 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_MASK 0x00200000U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_SHIFT 21 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_MASK 0x00200000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_SHIFT 22 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_MASK 0x00400000U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_SHIFT 22 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_MASK 0x00400000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_SHIFT 23 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_MASK 0x00800000U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_SHIFT 23 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_MASK 0x00800000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_SHIFT 24 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_MASK 0x01000000U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_SHIFT 24 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_MASK 0x01000000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_SHIFT 25 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_MASK 0x02000000U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_SHIFT 25 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_MASK 0x02000000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_SHIFT 0 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_MASK 0x00000001U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_SHIFT 0 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_MASK 0x00000001U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_SHIFT 1 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_MASK 0x00000002U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_SHIFT 1 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_MASK 0x00000002U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_SHIFT 2 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_MASK 0x00000004U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_SHIFT 2 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_MASK 0x00000004U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_SHIFT 3 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_MASK 0x00000008U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_SHIFT 3 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_MASK 0x00000008U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_SHIFT 4 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_MASK 0x00000010U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_SHIFT 4 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_MASK 0x00000010U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_SHIFT 5 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_MASK 0x00000020U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_SHIFT 5 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_MASK 0x00000020U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_SHIFT 6 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_MASK 0x00000040U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_SHIFT 6 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_MASK 0x00000040U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_SHIFT 7 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_MASK 0x00000080U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_SHIFT 7 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_MASK 0x00000080U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_SHIFT 8 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_MASK 0x00000100U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_SHIFT 8 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_MASK 0x00000100U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_SHIFT 9 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_MASK 0x00000200U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_SHIFT 9 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_MASK 0x00000200U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_SHIFT 10 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_MASK 0x00000400U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_SHIFT 10 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_MASK 0x00000400U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_SHIFT 11 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_MASK 0x00000800U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_SHIFT 11 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_MASK 0x00000800U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT 0 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK 0x00000001U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK 0x00000001U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT 1 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK 0x00000002U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK 0x00000002U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT 2 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK 0x00000004U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK 0x00000004U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT 3 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK 0x00000008U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK 0x00000008U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT 4 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK 0x00000010U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK 0x00000010U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT 5 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK 0x00000020U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK 0x00000020U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT 6 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK 0x00000040U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK 0x00000040U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT 7 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK 0x00000080U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK 0x00000080U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT 8 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK 0x00000100U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK 0x00000100U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT 9 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK 0x00000200U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK 0x00000200U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT 10 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK 0x00000400U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK 0x00000400U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT 11 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK 0x00000800U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK 0x00000800U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT 12 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK 0x00001000U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK 0x00001000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT 13 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK 0x00002000U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK 0x00002000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT 14 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK 0x00004000U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK 0x00004000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT 15 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK 0x00008000U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK 0x00008000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT 16 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK 0x00010000U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK 0x00010000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT 17 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK 0x00020000U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK 0x00020000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT 18 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK 0x00040000U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK 0x00040000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT 19 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK 0x00080000U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK 0x00080000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT 20 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK 0x00100000U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK 0x00100000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT 21 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK 0x00200000U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK 0x00200000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT 22 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK 0x00400000U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK 0x00400000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT 23 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK 0x00800000U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK 0x00800000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT 24 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK 0x01000000U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK 0x01000000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT 25 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK 0x02000000U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK 0x02000000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_SHIFT 0 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_MASK 0x00000001U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_MASK 0x00000001U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_SHIFT 1 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_MASK 0x00000002U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_MASK 0x00000002U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_SHIFT 2 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_MASK 0x00000004U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_MASK 0x00000004U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_SHIFT 3 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_MASK 0x00000008U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_MASK 0x00000008U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_SHIFT 4 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_MASK 0x00000010U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_MASK 0x00000010U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_SHIFT 5 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_MASK 0x00000020U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_MASK 0x00000020U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_SHIFT 6 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_MASK 0x00000040U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_MASK 0x00000040U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_SHIFT 7 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_MASK 0x00000080U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_MASK 0x00000080U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_SHIFT 8 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_MASK 0x00000100U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_MASK 0x00000100U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_SHIFT 9 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_MASK 0x00000200U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_MASK 0x00000200U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_SHIFT 10 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_MASK 0x00000400U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_MASK 0x00000400U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_SHIFT 11 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_MASK 0x00000800U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_MASK 0x00000800U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_SHIFT 12 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_MASK 0x00001000U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_MASK 0x00001000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_SHIFT 13 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_MASK 0x00002000U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_MASK 0x00002000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_SHIFT 14 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_MASK 0x00004000U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_MASK 0x00004000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_SHIFT 15 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_MASK 0x00008000U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_MASK 0x00008000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_SHIFT 16 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_MASK 0x00010000U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_MASK 0x00010000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_SHIFT 17 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_MASK 0x00020000U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_MASK 0x00020000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_SHIFT 18 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_MASK 0x00040000U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_MASK 0x00040000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_SHIFT 19 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_MASK 0x00080000U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_MASK 0x00080000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_SHIFT 20 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_MASK 0x00100000U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_MASK 0x00100000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_SHIFT 21 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_MASK 0x00200000U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_MASK 0x00200000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_SHIFT 22 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_MASK 0x00400000U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_MASK 0x00400000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_SHIFT 23 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_MASK 0x00800000U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_MASK 0x00800000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_SHIFT 24 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_MASK 0x01000000U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_MASK 0x01000000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_SHIFT 25 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_MASK 0x02000000U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_MASK 0x02000000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_SHIFT 0 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_MASK 0x00000001U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_MASK 0x00000001U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_SHIFT 1 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_MASK 0x00000002U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_MASK 0x00000002U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_SHIFT 2 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_MASK 0x00000004U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_MASK 0x00000004U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_SHIFT 3 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_MASK 0x00000008U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_MASK 0x00000008U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_SHIFT 4 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_MASK 0x00000010U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_MASK 0x00000010U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_SHIFT 5 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_MASK 0x00000020U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_MASK 0x00000020U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_SHIFT 6 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_MASK 0x00000040U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_MASK 0x00000040U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_SHIFT 7 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_MASK 0x00000080U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_MASK 0x00000080U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_SHIFT 8 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_MASK 0x00000100U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_MASK 0x00000100U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_SHIFT 9 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_MASK 0x00000200U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_MASK 0x00000200U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_SHIFT 10 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_MASK 0x00000400U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_MASK 0x00000400U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_SHIFT 11 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_MASK 0x00000800U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_MASK 0x00000800U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_SHIFT 12 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_MASK 0x00001000U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_MASK 0x00001000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_SHIFT 13 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_MASK 0x00002000U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_MASK 0x00002000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_SHIFT 14 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_MASK 0x00004000U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_MASK 0x00004000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_SHIFT 15 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_MASK 0x00008000U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_MASK 0x00008000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_SHIFT 16 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_MASK 0x00010000U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_MASK 0x00010000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_SHIFT 17 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_MASK 0x00020000U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_MASK 0x00020000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_SHIFT 18 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_MASK 0x00040000U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_MASK 0x00040000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_SHIFT 19 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_MASK 0x00080000U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_MASK 0x00080000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_SHIFT 20 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_MASK 0x00100000U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_MASK 0x00100000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_SHIFT 21 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_MASK 0x00200000U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_MASK 0x00200000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_SHIFT 22 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_MASK 0x00400000U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_MASK 0x00400000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_SHIFT 23 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_MASK 0x00800000U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_MASK 0x00800000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_SHIFT 24 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_MASK 0x01000000U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_MASK 0x01000000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_SHIFT 25 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_MASK 0x02000000U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_MASK 0x02000000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT 0 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK 0x00000001U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK 0x00000001U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT 1 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK 0x00000002U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK 0x00000002U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT 2 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK 0x00000004U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK 0x00000004U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT 3 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK 0x00000008U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK 0x00000008U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT 4 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK 0x00000010U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK 0x00000010U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT 5 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK 0x00000020U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK 0x00000020U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT 6 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK 0x00000040U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK 0x00000040U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT 7 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK 0x00000080U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK 0x00000080U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT 8 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK 0x00000100U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK 0x00000100U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT 9 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK 0x00000200U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK 0x00000200U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT 10 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK 0x00000400U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK 0x00000400U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT 11 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK 0x00000800U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK 0x00000800U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT 12 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK 0x00001000U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK 0x00001000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT 13 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK 0x00002000U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK 0x00002000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT 14 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK 0x00004000U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK 0x00004000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT 15 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK 0x00008000U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK 0x00008000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT 16 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK 0x00010000U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK 0x00010000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT 17 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK 0x00020000U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK 0x00020000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT 18 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK 0x00040000U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK 0x00040000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT 19 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK 0x00080000U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK 0x00080000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT 20 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK 0x00100000U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK 0x00100000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT 21 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK 0x00200000U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK 0x00200000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT 22 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK 0x00400000U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK 0x00400000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT 23 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK 0x00800000U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK 0x00800000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT 24 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK 0x01000000U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK 0x01000000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT 25 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK 0x02000000U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK 0x02000000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT 0 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK 0x00000001U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK 0x00000001U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT 1 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK 0x00000002U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK 0x00000002U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT 2 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK 0x00000004U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK 0x00000004U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT 3 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK 0x00000008U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK 0x00000008U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT 4 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK 0x00000010U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK 0x00000010U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT 5 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK 0x00000020U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK 0x00000020U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT 6 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK 0x00000040U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK 0x00000040U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT 7 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK 0x00000080U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK 0x00000080U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT 8 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK 0x00000100U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK 0x00000100U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT 9 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK 0x00000200U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK 0x00000200U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT 10 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK 0x00000400U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK 0x00000400U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT 11 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK 0x00000800U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK 0x00000800U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT 12 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK 0x00001000U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK 0x00001000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT 13 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK 0x00002000U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK 0x00002000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT 14 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK 0x00004000U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK 0x00004000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT 15 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK 0x00008000U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK 0x00008000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT 16 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK 0x00010000U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK 0x00010000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT 17 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK 0x00020000U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK 0x00020000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT 18 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK 0x00040000U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK 0x00040000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT 19 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK 0x00080000U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK 0x00080000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT 20 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK 0x00100000U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK 0x00100000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT 21 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK 0x00200000U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK 0x00200000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT 22 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK 0x00400000U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK 0x00400000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT 23 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK 0x00800000U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK 0x00800000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT 24 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK 0x01000000U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK 0x01000000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT 25 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK 0x02000000U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK 0x02000000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_SHIFT 0 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_MASK 0x00000001U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_MASK 0x00000001U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_SHIFT 1 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_MASK 0x00000002U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_MASK 0x00000002U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_SHIFT 2 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_MASK 0x00000004U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_MASK 0x00000004U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_SHIFT 3 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_MASK 0x00000008U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_MASK 0x00000008U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_SHIFT 4 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_MASK 0x00000010U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_MASK 0x00000010U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_SHIFT 5 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_MASK 0x00000020U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_MASK 0x00000020U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_SHIFT 6 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_MASK 0x00000040U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_MASK 0x00000040U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_SHIFT 7 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_MASK 0x00000080U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_MASK 0x00000080U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_SHIFT 8 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_MASK 0x00000100U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_MASK 0x00000100U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_SHIFT 9 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_MASK 0x00000200U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_MASK 0x00000200U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_SHIFT 10 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_MASK 0x00000400U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_MASK 0x00000400U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_SHIFT 11 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_MASK 0x00000800U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_MASK 0x00000800U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_SHIFT 12 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_MASK 0x00001000U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_MASK 0x00001000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_SHIFT 13 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_MASK 0x00002000U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_MASK 0x00002000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_SHIFT 14 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_MASK 0x00004000U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_MASK 0x00004000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_SHIFT 15 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_MASK 0x00008000U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_MASK 0x00008000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_SHIFT 16 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_MASK 0x00010000U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_MASK 0x00010000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_SHIFT 17 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_MASK 0x00020000U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_MASK 0x00020000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_SHIFT 18 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_MASK 0x00040000U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_MASK 0x00040000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_SHIFT 19 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_MASK 0x00080000U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_MASK 0x00080000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_SHIFT 20 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_MASK 0x00100000U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_MASK 0x00100000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_SHIFT 21 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_MASK 0x00200000U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_MASK 0x00200000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_SHIFT 22 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_MASK 0x00400000U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_MASK 0x00400000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_SHIFT 23 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_MASK 0x00800000U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_MASK 0x00800000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_SHIFT 24 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_MASK 0x01000000U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_MASK 0x01000000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_SHIFT 25 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_MASK 0x02000000U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_MASK 0x02000000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT 0 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK 0x00000001U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK 0x00000001U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT 1 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK 0x00000002U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK 0x00000002U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT 2 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK 0x00000004U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK 0x00000004U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT 3 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK 0x00000008U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK 0x00000008U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT 4 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK 0x00000010U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK 0x00000010U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT 5 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK 0x00000020U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK 0x00000020U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT 6 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK 0x00000040U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK 0x00000040U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT 7 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK 0x00000080U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK 0x00000080U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT 8 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK 0x00000100U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK 0x00000100U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT 9 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK 0x00000200U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK 0x00000200U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT 10 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK 0x00000400U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK 0x00000400U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT 11 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK 0x00000800U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK 0x00000800U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT 12 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK 0x00001000U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK 0x00001000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT 13 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK 0x00002000U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK 0x00002000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT 14 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK 0x00004000U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK 0x00004000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT 15 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK 0x00008000U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK 0x00008000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT 16 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK 0x00010000U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK 0x00010000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT 17 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK 0x00020000U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK 0x00020000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT 18 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK 0x00040000U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK 0x00040000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT 19 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK 0x00080000U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK 0x00080000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT 20 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK 0x00100000U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK 0x00100000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT 21 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK 0x00200000U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK 0x00200000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT 22 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK 0x00400000U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK 0x00400000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT 23 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK 0x00800000U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK 0x00800000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT 24 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK 0x01000000U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK 0x01000000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT 25 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK 0x02000000U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK 0x02000000U -/*I2C Loopback Control. 0 = Connect I2C inputs according to MIO mapping. 1 = Loop I2C 0 outputs to I2C 1 inputs, and I2C 1 outp - ts to I2C 0 inputs.*/ +/* +* I2C Loopback Control. 0 = Connect I2C inputs according to MIO mapping. 1 + * = Loop I2C 0 outputs to I2C 1 inputs, and I2C 1 outputs to I2C 0 inputs + * . +*/ #undef IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_DEFVAL #undef IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_SHIFT #undef IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_MASK -#define IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_SHIFT 3 -#define IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_MASK 0x00000008U +#define IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_SHIFT 3 +#define IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_MASK 0x00000008U -/*CAN Loopback Control. 0 = Connect CAN inputs according to MIO mapping. 1 = Loop CAN 0 Tx to CAN 1 Rx, and CAN 1 Tx to CAN 0 R - .*/ +/* +* CAN Loopback Control. 0 = Connect CAN inputs according to MIO mapping. 1 + * = Loop CAN 0 Tx to CAN 1 Rx, and CAN 1 Tx to CAN 0 Rx. +*/ #undef IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_DEFVAL #undef IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_SHIFT #undef IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_MASK -#define IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_SHIFT 2 -#define IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_MASK 0x00000004U +#define IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_SHIFT 2 +#define IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_MASK 0x00000004U -/*UART Loopback Control. 0 = Connect UART inputs according to MIO mapping. 1 = Loop UART 0 outputs to UART 1 inputs, and UART 1 - outputs to UART 0 inputs. RXD/TXD cross-connected. RTS/CTS cross-connected. DSR, DTR, DCD and RI not used.*/ +/* +* UART Loopback Control. 0 = Connect UART inputs according to MIO mapping. + * 1 = Loop UART 0 outputs to UART 1 inputs, and UART 1 outputs to UART 0 + * inputs. RXD/TXD cross-connected. RTS/CTS cross-connected. DSR, DTR, DCD + * and RI not used. +*/ #undef IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_DEFVAL #undef IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_SHIFT #undef IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_MASK -#define IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_SHIFT 1 -#define IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_MASK 0x00000002U +#define IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_SHIFT 1 +#define IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_MASK 0x00000002U -/*SPI Loopback Control. 0 = Connect SPI inputs according to MIO mapping. 1 = Loop SPI 0 outputs to SPI 1 inputs, and SPI 1 outp - ts to SPI 0 inputs. The other SPI core will appear on the LS Slave Select.*/ +/* +* SPI Loopback Control. 0 = Connect SPI inputs according to MIO mapping. 1 + * = Loop SPI 0 outputs to SPI 1 inputs, and SPI 1 outputs to SPI 0 inputs + * . The other SPI core will appear on the LS Slave Select. +*/ #undef IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_DEFVAL #undef IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_SHIFT #undef IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_MASK -#define IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_SHIFT 0 -#define IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_MASK 0x00000001U +#define IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_SHIFT 0 +#define IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_MASK 0x00000001U +#undef CRF_APB_RST_FPD_TOP_OFFSET +#define CRF_APB_RST_FPD_TOP_OFFSET 0XFD1A0100 #undef CRL_APB_RST_LPD_IOU2_OFFSET #define CRL_APB_RST_LPD_IOU2_OFFSET 0XFF5E0238 +#undef CRL_APB_RST_LPD_TOP_OFFSET +#define CRL_APB_RST_LPD_TOP_OFFSET 0XFF5E023C #undef CRL_APB_RST_LPD_IOU0_OFFSET #define CRL_APB_RST_LPD_IOU0_OFFSET 0XFF5E0230 #undef CRL_APB_RST_LPD_IOU2_OFFSET @@ -24430,8 +31077,10 @@ #define IOU_SLCR_IOU_TAPDLY_BYPASS_OFFSET 0XFF180390 #undef CRL_APB_RST_LPD_TOP_OFFSET #define CRL_APB_RST_LPD_TOP_OFFSET 0XFF5E023C -#undef CRF_APB_RST_FPD_TOP_OFFSET -#define CRF_APB_RST_FPD_TOP_OFFSET 0XFD1A0100 +#undef USB3_0_FPD_POWER_PRSNT_OFFSET +#define USB3_0_FPD_POWER_PRSNT_OFFSET 0XFF9D0080 +#undef USB3_0_FPD_PIPE_CLK_OFFSET +#define USB3_0_FPD_PIPE_CLK_OFFSET 0XFF9D007C #undef CRL_APB_RST_LPD_IOU2_OFFSET #define CRL_APB_RST_LPD_IOU2_OFFSET 0XFF5E0238 #undef IOU_SLCR_CTRL_REG_SD_OFFSET @@ -24440,6 +31089,8 @@ #define IOU_SLCR_SD_CONFIG_REG2_OFFSET 0XFF180320 #undef IOU_SLCR_SD_CONFIG_REG1_OFFSET #define IOU_SLCR_SD_CONFIG_REG1_OFFSET 0XFF18031C +#undef IOU_SLCR_SD_DLL_CTRL_OFFSET +#define IOU_SLCR_SD_DLL_CTRL_OFFSET 0XFF180358 #undef IOU_SLCR_SD_CONFIG_REG3_OFFSET #define IOU_SLCR_SD_CONFIG_REG3_OFFSET 0XFF180324 #undef CRL_APB_RST_LPD_IOU2_OFFSET @@ -24468,6 +31119,8 @@ #define UART1_CONTROL_REG0_OFFSET 0XFF010000 #undef UART1_MODE_REG0_OFFSET #define UART1_MODE_REG0_OFFSET 0XFF010004 +#undef CRL_APB_RST_LPD_IOU2_OFFSET +#define CRL_APB_RST_LPD_IOU2_OFFSET 0XFF5E0238 #undef LPD_SLCR_SECURE_SLCR_ADMA_OFFSET #define LPD_SLCR_SECURE_SLCR_ADMA_OFFSET 0XFF4B0024 #undef CSU_TAMPER_STATUS_OFFSET @@ -24480,782 +31133,1656 @@ #define IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_OFFSET 0XFF260020 #undef IOU_SCNTRS_COUNTER_CONTROL_REGISTER_OFFSET #define IOU_SCNTRS_COUNTER_CONTROL_REGISTER_OFFSET 0XFF260000 +#undef GPIO_DIRM_1_OFFSET +#define GPIO_DIRM_1_OFFSET 0XFF0A0244 +#undef GPIO_OEN_1_OFFSET +#define GPIO_OEN_1_OFFSET 0XFF0A0248 +#undef GPIO_MASK_DATA_1_LSW_OFFSET +#define GPIO_MASK_DATA_1_LSW_OFFSET 0XFF0A0008 +#undef GPIO_MASK_DATA_1_LSW_OFFSET +#define GPIO_MASK_DATA_1_LSW_OFFSET 0XFF0A0008 -/*Block level reset*/ -#undef CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_DEFVAL -#undef CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_SHIFT -#undef CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_MASK -#define CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_DEFVAL 0x0017FFFF -#define CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_SHIFT 20 -#define CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_MASK 0x00100000U - -/*GEM 3 reset*/ -#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL -#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT -#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK -#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL 0x0000000F -#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT 3 -#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK 0x00000008U - -/*Block level reset*/ -#undef CRL_APB_RST_LPD_IOU2_QSPI_RESET_DEFVAL -#undef CRL_APB_RST_LPD_IOU2_QSPI_RESET_SHIFT -#undef CRL_APB_RST_LPD_IOU2_QSPI_RESET_MASK -#define CRL_APB_RST_LPD_IOU2_QSPI_RESET_DEFVAL 0x0017FFFF -#define CRL_APB_RST_LPD_IOU2_QSPI_RESET_SHIFT 0 -#define CRL_APB_RST_LPD_IOU2_QSPI_RESET_MASK 0x00000001U - -/*0: Do not by pass the tap delays on the Rx clock signal of LQSPI 1: Bypass the Tap delay on the Rx clock signal of LQSPI*/ -#undef IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_DEFVAL -#undef IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_SHIFT -#undef IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_MASK -#define IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_DEFVAL 0x00000007 -#define IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_SHIFT 2 -#define IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_MASK 0x00000004U - -/*USB 0 reset for control registers*/ -#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL -#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT -#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK -#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL 0x00188FDF -#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT 10 -#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK 0x00000400U - -/*USB 0 sleep circuit reset*/ -#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL -#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT -#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK -#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL 0x00188FDF -#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT 8 -#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK 0x00000100U - -/*USB 0 reset*/ -#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL -#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT -#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK -#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL 0x00188FDF -#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT 6 -#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK 0x00000040U - -/*PCIE config reset*/ +/* +* PCIE config reset +*/ #undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL #undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT #undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK -#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL 0x000F9FFE -#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT 19 -#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK 0x00080000U +#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT 19 +#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK 0x00080000U -/*PCIE control block level reset*/ +/* +* PCIE control block level reset +*/ #undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL #undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT #undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK -#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL 0x000F9FFE -#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT 17 -#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK 0x00020000U +#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT 17 +#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK 0x00020000U -/*PCIE bridge block level reset (AXI interface)*/ +/* +* PCIE bridge block level reset (AXI interface) +*/ #undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL #undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT #undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK -#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL 0x000F9FFE -#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT 18 -#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK 0x00040000U +#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT 18 +#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK 0x00040000U -/*Display Port block level reset (includes DPDMA)*/ +/* +* Display Port block level reset (includes DPDMA) +*/ #undef CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL #undef CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT #undef CRF_APB_RST_FPD_TOP_DP_RESET_MASK -#define CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL 0x000F9FFE -#define CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT 16 -#define CRF_APB_RST_FPD_TOP_DP_RESET_MASK 0x00010000U +#define CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT 16 +#define CRF_APB_RST_FPD_TOP_DP_RESET_MASK 0x00010000U -/*FPD WDT reset*/ +/* +* FPD WDT reset +*/ #undef CRF_APB_RST_FPD_TOP_SWDT_RESET_DEFVAL #undef CRF_APB_RST_FPD_TOP_SWDT_RESET_SHIFT #undef CRF_APB_RST_FPD_TOP_SWDT_RESET_MASK -#define CRF_APB_RST_FPD_TOP_SWDT_RESET_DEFVAL 0x000F9FFE -#define CRF_APB_RST_FPD_TOP_SWDT_RESET_SHIFT 15 -#define CRF_APB_RST_FPD_TOP_SWDT_RESET_MASK 0x00008000U +#define CRF_APB_RST_FPD_TOP_SWDT_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_SWDT_RESET_SHIFT 15 +#define CRF_APB_RST_FPD_TOP_SWDT_RESET_MASK 0x00008000U -/*GDMA block level reset*/ +/* +* GDMA block level reset +*/ #undef CRF_APB_RST_FPD_TOP_GDMA_RESET_DEFVAL #undef CRF_APB_RST_FPD_TOP_GDMA_RESET_SHIFT #undef CRF_APB_RST_FPD_TOP_GDMA_RESET_MASK -#define CRF_APB_RST_FPD_TOP_GDMA_RESET_DEFVAL 0x000F9FFE -#define CRF_APB_RST_FPD_TOP_GDMA_RESET_SHIFT 6 -#define CRF_APB_RST_FPD_TOP_GDMA_RESET_MASK 0x00000040U +#define CRF_APB_RST_FPD_TOP_GDMA_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_GDMA_RESET_SHIFT 6 +#define CRF_APB_RST_FPD_TOP_GDMA_RESET_MASK 0x00000040U -/*Pixel Processor (submodule of GPU) block level reset*/ +/* +* Pixel Processor (submodule of GPU) block level reset +*/ #undef CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_DEFVAL #undef CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_SHIFT #undef CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_MASK -#define CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_DEFVAL 0x000F9FFE -#define CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_SHIFT 4 -#define CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_MASK 0x00000010U +#define CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_SHIFT 4 +#define CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_MASK 0x00000010U -/*Pixel Processor (submodule of GPU) block level reset*/ +/* +* Pixel Processor (submodule of GPU) block level reset +*/ #undef CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_DEFVAL #undef CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_SHIFT #undef CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_MASK -#define CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_DEFVAL 0x000F9FFE -#define CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_SHIFT 5 -#define CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_MASK 0x00000020U +#define CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_SHIFT 5 +#define CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_MASK 0x00000020U -/*GPU block level reset*/ +/* +* GPU block level reset +*/ #undef CRF_APB_RST_FPD_TOP_GPU_RESET_DEFVAL #undef CRF_APB_RST_FPD_TOP_GPU_RESET_SHIFT #undef CRF_APB_RST_FPD_TOP_GPU_RESET_MASK -#define CRF_APB_RST_FPD_TOP_GPU_RESET_DEFVAL 0x000F9FFE -#define CRF_APB_RST_FPD_TOP_GPU_RESET_SHIFT 3 -#define CRF_APB_RST_FPD_TOP_GPU_RESET_MASK 0x00000008U +#define CRF_APB_RST_FPD_TOP_GPU_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_GPU_RESET_SHIFT 3 +#define CRF_APB_RST_FPD_TOP_GPU_RESET_MASK 0x00000008U -/*GT block level reset*/ +/* +* GT block level reset +*/ #undef CRF_APB_RST_FPD_TOP_GT_RESET_DEFVAL #undef CRF_APB_RST_FPD_TOP_GT_RESET_SHIFT #undef CRF_APB_RST_FPD_TOP_GT_RESET_MASK -#define CRF_APB_RST_FPD_TOP_GT_RESET_DEFVAL 0x000F9FFE -#define CRF_APB_RST_FPD_TOP_GT_RESET_SHIFT 2 -#define CRF_APB_RST_FPD_TOP_GT_RESET_MASK 0x00000004U +#define CRF_APB_RST_FPD_TOP_GT_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_GT_RESET_SHIFT 2 +#define CRF_APB_RST_FPD_TOP_GT_RESET_MASK 0x00000004U -/*Sata block level reset*/ +/* +* Sata block level reset +*/ #undef CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL #undef CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT #undef CRF_APB_RST_FPD_TOP_SATA_RESET_MASK -#define CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL 0x000F9FFE -#define CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT 1 -#define CRF_APB_RST_FPD_TOP_SATA_RESET_MASK 0x00000002U +#define CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT 1 +#define CRF_APB_RST_FPD_TOP_SATA_RESET_MASK 0x00000002U -/*Block level reset*/ +/* +* Block level reset +*/ +#undef CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_DEFVAL +#undef CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_SHIFT +#undef CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_MASK +#define CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_SHIFT 20 +#define CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_MASK 0x00100000U + +/* +* Block level reset +*/ +#undef CRL_APB_RST_LPD_IOU2_IOU_CC_RESET_DEFVAL +#undef CRL_APB_RST_LPD_IOU2_IOU_CC_RESET_SHIFT +#undef CRL_APB_RST_LPD_IOU2_IOU_CC_RESET_MASK +#define CRL_APB_RST_LPD_IOU2_IOU_CC_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_IOU_CC_RESET_SHIFT 19 +#define CRL_APB_RST_LPD_IOU2_IOU_CC_RESET_MASK 0x00080000U + +/* +* Block level reset +*/ +#undef CRL_APB_RST_LPD_IOU2_ADMA_RESET_DEFVAL +#undef CRL_APB_RST_LPD_IOU2_ADMA_RESET_SHIFT +#undef CRL_APB_RST_LPD_IOU2_ADMA_RESET_MASK +#define CRL_APB_RST_LPD_IOU2_ADMA_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_ADMA_RESET_SHIFT 17 +#define CRL_APB_RST_LPD_IOU2_ADMA_RESET_MASK 0x00020000U + +/* +* Reset entire full power domain. +*/ +#undef CRL_APB_RST_LPD_TOP_FPD_RESET_DEFVAL +#undef CRL_APB_RST_LPD_TOP_FPD_RESET_SHIFT +#undef CRL_APB_RST_LPD_TOP_FPD_RESET_MASK +#define CRL_APB_RST_LPD_TOP_FPD_RESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_FPD_RESET_SHIFT 23 +#define CRL_APB_RST_LPD_TOP_FPD_RESET_MASK 0x00800000U + +/* +* LPD SWDT +*/ +#undef CRL_APB_RST_LPD_TOP_LPD_SWDT_RESET_DEFVAL +#undef CRL_APB_RST_LPD_TOP_LPD_SWDT_RESET_SHIFT +#undef CRL_APB_RST_LPD_TOP_LPD_SWDT_RESET_MASK +#define CRL_APB_RST_LPD_TOP_LPD_SWDT_RESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_LPD_SWDT_RESET_SHIFT 20 +#define CRL_APB_RST_LPD_TOP_LPD_SWDT_RESET_MASK 0x00100000U + +/* +* Sysmonitor reset +*/ +#undef CRL_APB_RST_LPD_TOP_SYSMON_RESET_DEFVAL +#undef CRL_APB_RST_LPD_TOP_SYSMON_RESET_SHIFT +#undef CRL_APB_RST_LPD_TOP_SYSMON_RESET_MASK +#define CRL_APB_RST_LPD_TOP_SYSMON_RESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_SYSMON_RESET_SHIFT 17 +#define CRL_APB_RST_LPD_TOP_SYSMON_RESET_MASK 0x00020000U + +/* +* Real Time Clock reset +*/ +#undef CRL_APB_RST_LPD_TOP_RTC_RESET_DEFVAL +#undef CRL_APB_RST_LPD_TOP_RTC_RESET_SHIFT +#undef CRL_APB_RST_LPD_TOP_RTC_RESET_MASK +#define CRL_APB_RST_LPD_TOP_RTC_RESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_RTC_RESET_SHIFT 16 +#define CRL_APB_RST_LPD_TOP_RTC_RESET_MASK 0x00010000U + +/* +* APM reset +*/ +#undef CRL_APB_RST_LPD_TOP_APM_RESET_DEFVAL +#undef CRL_APB_RST_LPD_TOP_APM_RESET_SHIFT +#undef CRL_APB_RST_LPD_TOP_APM_RESET_MASK +#define CRL_APB_RST_LPD_TOP_APM_RESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_APM_RESET_SHIFT 15 +#define CRL_APB_RST_LPD_TOP_APM_RESET_MASK 0x00008000U + +/* +* IPI reset +*/ +#undef CRL_APB_RST_LPD_TOP_IPI_RESET_DEFVAL +#undef CRL_APB_RST_LPD_TOP_IPI_RESET_SHIFT +#undef CRL_APB_RST_LPD_TOP_IPI_RESET_MASK +#define CRL_APB_RST_LPD_TOP_IPI_RESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_IPI_RESET_SHIFT 14 +#define CRL_APB_RST_LPD_TOP_IPI_RESET_MASK 0x00004000U + +/* +* reset entire RPU power island +*/ +#undef CRL_APB_RST_LPD_TOP_RPU_PGE_RESET_DEFVAL +#undef CRL_APB_RST_LPD_TOP_RPU_PGE_RESET_SHIFT +#undef CRL_APB_RST_LPD_TOP_RPU_PGE_RESET_MASK +#define CRL_APB_RST_LPD_TOP_RPU_PGE_RESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_RPU_PGE_RESET_SHIFT 4 +#define CRL_APB_RST_LPD_TOP_RPU_PGE_RESET_MASK 0x00000010U + +/* +* reset ocm +*/ +#undef CRL_APB_RST_LPD_TOP_OCM_RESET_DEFVAL +#undef CRL_APB_RST_LPD_TOP_OCM_RESET_SHIFT +#undef CRL_APB_RST_LPD_TOP_OCM_RESET_MASK +#define CRL_APB_RST_LPD_TOP_OCM_RESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_OCM_RESET_SHIFT 3 +#define CRL_APB_RST_LPD_TOP_OCM_RESET_MASK 0x00000008U + +/* +* GEM 3 reset +*/ +#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL +#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT +#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK +#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL 0x0000000F +#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT 3 +#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK 0x00000008U + +/* +* Block level reset +*/ +#undef CRL_APB_RST_LPD_IOU2_QSPI_RESET_DEFVAL +#undef CRL_APB_RST_LPD_IOU2_QSPI_RESET_SHIFT +#undef CRL_APB_RST_LPD_IOU2_QSPI_RESET_MASK +#define CRL_APB_RST_LPD_IOU2_QSPI_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_QSPI_RESET_SHIFT 0 +#define CRL_APB_RST_LPD_IOU2_QSPI_RESET_MASK 0x00000001U + +/* +* 0: Do not by pass the tap delays on the Rx clock signal of LQSPI 1: Bypa + * ss the Tap delay on the Rx clock signal of LQSPI +*/ +#undef IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_DEFVAL +#undef IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_SHIFT +#undef IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_MASK +#define IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_DEFVAL 0x00000007 +#define IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_SHIFT 2 +#define IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_MASK 0x00000004U + +/* +* USB 0 reset for control registers +*/ +#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL +#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT +#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK +#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT 10 +#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK 0x00000400U + +/* +* USB 0 sleep circuit reset +*/ +#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL +#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT +#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK +#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT 8 +#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK 0x00000100U + +/* +* USB 0 reset +*/ +#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL +#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT +#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK +#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT 6 +#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK 0x00000040U + +/* +* This bit is used to choose between PIPE power present and 1'b1 +*/ +#undef USB3_0_FPD_POWER_PRSNT_OPTION_DEFVAL +#undef USB3_0_FPD_POWER_PRSNT_OPTION_SHIFT +#undef USB3_0_FPD_POWER_PRSNT_OPTION_MASK +#define USB3_0_FPD_POWER_PRSNT_OPTION_DEFVAL +#define USB3_0_FPD_POWER_PRSNT_OPTION_SHIFT 0 +#define USB3_0_FPD_POWER_PRSNT_OPTION_MASK 0x00000001U + +/* +* This bit is used to choose between PIPE clock coming from SerDes and the + * suspend clk +*/ +#undef USB3_0_FPD_PIPE_CLK_OPTION_DEFVAL +#undef USB3_0_FPD_PIPE_CLK_OPTION_SHIFT +#undef USB3_0_FPD_PIPE_CLK_OPTION_MASK +#define USB3_0_FPD_PIPE_CLK_OPTION_DEFVAL +#define USB3_0_FPD_PIPE_CLK_OPTION_SHIFT 0 +#define USB3_0_FPD_PIPE_CLK_OPTION_MASK 0x00000001U + +/* +* Block level reset +*/ #undef CRL_APB_RST_LPD_IOU2_SDIO1_RESET_DEFVAL #undef CRL_APB_RST_LPD_IOU2_SDIO1_RESET_SHIFT #undef CRL_APB_RST_LPD_IOU2_SDIO1_RESET_MASK -#define CRL_APB_RST_LPD_IOU2_SDIO1_RESET_DEFVAL 0x0017FFFF -#define CRL_APB_RST_LPD_IOU2_SDIO1_RESET_SHIFT 6 -#define CRL_APB_RST_LPD_IOU2_SDIO1_RESET_MASK 0x00000040U +#define CRL_APB_RST_LPD_IOU2_SDIO1_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_SDIO1_RESET_SHIFT 6 +#define CRL_APB_RST_LPD_IOU2_SDIO1_RESET_MASK 0x00000040U -/*SD or eMMC selection on SDIO1 0: SD enabled 1: eMMC enabled*/ +/* +* SD or eMMC selection on SDIO1 0: SD enabled 1: eMMC enabled +*/ #undef IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_DEFVAL #undef IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_SHIFT #undef IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_MASK -#define IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_SHIFT 15 -#define IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_MASK 0x00008000U +#define IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_SHIFT 15 +#define IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_MASK 0x00008000U -/*Should be set based on the final product usage 00 - Removable SCard Slot 01 - Embedded Slot for One Device 10 - Shared Bus Sl - t 11 - Reserved*/ +/* +* Should be set based on the final product usage 00 - Removable SCard Slot + * 01 - Embedded Slot for One Device 10 - Shared Bus Slot 11 - Reserved +*/ #undef IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_DEFVAL #undef IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_SHIFT #undef IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_MASK -#define IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_DEFVAL 0x0FFC0FFC -#define IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_SHIFT 28 -#define IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_MASK 0x30000000U +#define IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_DEFVAL 0x0FFC0FFC +#define IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_SHIFT 28 +#define IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_MASK 0x30000000U -/*1.8V Support 1: 1.8V supported 0: 1.8V not supported support*/ +/* +* 1.8V Support 1: 1.8V supported 0: 1.8V not supported support +*/ #undef IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_DEFVAL #undef IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_SHIFT #undef IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_MASK -#define IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_DEFVAL 0x0FFC0FFC -#define IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_SHIFT 25 -#define IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_MASK 0x02000000U +#define IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_DEFVAL 0x0FFC0FFC +#define IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_SHIFT 25 +#define IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_MASK 0x02000000U -/*3.0V Support 1: 3.0V supported 0: 3.0V not supported support*/ +/* +* 3.0V Support 1: 3.0V supported 0: 3.0V not supported support +*/ #undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_DEFVAL #undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_SHIFT #undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_MASK -#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_DEFVAL 0x0FFC0FFC -#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_SHIFT 24 -#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_MASK 0x01000000U +#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_DEFVAL 0x0FFC0FFC +#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_SHIFT 24 +#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_MASK 0x01000000U -/*3.3V Support 1: 3.3V supported 0: 3.3V not supported support*/ +/* +* 3.3V Support 1: 3.3V supported 0: 3.3V not supported support +*/ #undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_DEFVAL #undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_SHIFT #undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_MASK -#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_DEFVAL 0x0FFC0FFC -#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_SHIFT 23 -#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_MASK 0x00800000U +#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_DEFVAL 0x0FFC0FFC +#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_SHIFT 23 +#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_MASK 0x00800000U -/*Base Clock Frequency for SD Clock. This is the frequency of the xin_clk.*/ +/* +* Base Clock Frequency for SD Clock. This is the frequency of the xin_clk. +*/ #undef IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_DEFVAL #undef IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_SHIFT #undef IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_MASK -#define IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_DEFVAL 0x32403240 -#define IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_SHIFT 23 -#define IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_MASK 0x7F800000U +#define IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_DEFVAL 0x32403240 +#define IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_SHIFT 23 +#define IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_MASK 0x7F800000U -/*This is the Timer Count for Re-Tuning Timer for Re-Tuning Mode 1 to 3. Setting to 4'b0 disables Re-Tuning Timer. 0h - Get inf - rmation via other source 1h = 1 seconds 2h = 2 seconds 3h = 4 seconds 4h = 8 seconds -- n = 2(n-1) seconds -- Bh = 1024 secon - s Fh - Ch = Reserved*/ +/* +* Configures the Number of Taps (Phases) of the rxclk_in that is supported + * . +*/ +#undef IOU_SLCR_SD_CONFIG_REG1_SD1_TUNIGCOUNT_DEFVAL +#undef IOU_SLCR_SD_CONFIG_REG1_SD1_TUNIGCOUNT_SHIFT +#undef IOU_SLCR_SD_CONFIG_REG1_SD1_TUNIGCOUNT_MASK +#define IOU_SLCR_SD_CONFIG_REG1_SD1_TUNIGCOUNT_DEFVAL 0x32403240 +#define IOU_SLCR_SD_CONFIG_REG1_SD1_TUNIGCOUNT_SHIFT 17 +#define IOU_SLCR_SD_CONFIG_REG1_SD1_TUNIGCOUNT_MASK 0x007E0000U + +/* +* Reserved. +*/ +#undef IOU_SLCR_SD_DLL_CTRL_RESERVED_DEFVAL +#undef IOU_SLCR_SD_DLL_CTRL_RESERVED_SHIFT +#undef IOU_SLCR_SD_DLL_CTRL_RESERVED_MASK +#define IOU_SLCR_SD_DLL_CTRL_RESERVED_DEFVAL 0x00080008 +#define IOU_SLCR_SD_DLL_CTRL_RESERVED_SHIFT 3 +#define IOU_SLCR_SD_DLL_CTRL_RESERVED_MASK 0x00000008U + +/* +* This is the Timer Count for Re-Tuning Timer for Re-Tuning Mode 1 to 3. S + * etting to 4'b0 disables Re-Tuning Timer. 0h - Get information via other + * source 1h = 1 seconds 2h = 2 seconds 3h = 4 seconds 4h = 8 seconds -- n + * = 2(n-1) seconds -- Bh = 1024 seconds Fh - Ch = Reserved +*/ #undef IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_DEFVAL #undef IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_SHIFT #undef IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_MASK -#define IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_DEFVAL 0x06070607 -#define IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_SHIFT 22 -#define IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_MASK 0x03C00000U +#define IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_DEFVAL 0x06070607 +#define IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_SHIFT 22 +#define IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_MASK 0x03C00000U -/*Block level reset*/ +/* +* Block level reset +*/ #undef CRL_APB_RST_LPD_IOU2_CAN1_RESET_DEFVAL #undef CRL_APB_RST_LPD_IOU2_CAN1_RESET_SHIFT #undef CRL_APB_RST_LPD_IOU2_CAN1_RESET_MASK -#define CRL_APB_RST_LPD_IOU2_CAN1_RESET_DEFVAL 0x0017FFFF -#define CRL_APB_RST_LPD_IOU2_CAN1_RESET_SHIFT 8 -#define CRL_APB_RST_LPD_IOU2_CAN1_RESET_MASK 0x00000100U +#define CRL_APB_RST_LPD_IOU2_CAN1_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_CAN1_RESET_SHIFT 8 +#define CRL_APB_RST_LPD_IOU2_CAN1_RESET_MASK 0x00000100U -/*Block level reset*/ +/* +* Block level reset +*/ #undef CRL_APB_RST_LPD_IOU2_I2C0_RESET_DEFVAL #undef CRL_APB_RST_LPD_IOU2_I2C0_RESET_SHIFT #undef CRL_APB_RST_LPD_IOU2_I2C0_RESET_MASK -#define CRL_APB_RST_LPD_IOU2_I2C0_RESET_DEFVAL 0x0017FFFF -#define CRL_APB_RST_LPD_IOU2_I2C0_RESET_SHIFT 9 -#define CRL_APB_RST_LPD_IOU2_I2C0_RESET_MASK 0x00000200U +#define CRL_APB_RST_LPD_IOU2_I2C0_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_I2C0_RESET_SHIFT 9 +#define CRL_APB_RST_LPD_IOU2_I2C0_RESET_MASK 0x00000200U -/*Block level reset*/ +/* +* Block level reset +*/ #undef CRL_APB_RST_LPD_IOU2_I2C1_RESET_DEFVAL #undef CRL_APB_RST_LPD_IOU2_I2C1_RESET_SHIFT #undef CRL_APB_RST_LPD_IOU2_I2C1_RESET_MASK -#define CRL_APB_RST_LPD_IOU2_I2C1_RESET_DEFVAL 0x0017FFFF -#define CRL_APB_RST_LPD_IOU2_I2C1_RESET_SHIFT 10 -#define CRL_APB_RST_LPD_IOU2_I2C1_RESET_MASK 0x00000400U +#define CRL_APB_RST_LPD_IOU2_I2C1_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_I2C1_RESET_SHIFT 10 +#define CRL_APB_RST_LPD_IOU2_I2C1_RESET_MASK 0x00000400U -/*Block level reset*/ +/* +* Block level reset +*/ #undef CRL_APB_RST_LPD_IOU2_SWDT_RESET_DEFVAL #undef CRL_APB_RST_LPD_IOU2_SWDT_RESET_SHIFT #undef CRL_APB_RST_LPD_IOU2_SWDT_RESET_MASK -#define CRL_APB_RST_LPD_IOU2_SWDT_RESET_DEFVAL 0x0017FFFF -#define CRL_APB_RST_LPD_IOU2_SWDT_RESET_SHIFT 15 -#define CRL_APB_RST_LPD_IOU2_SWDT_RESET_MASK 0x00008000U +#define CRL_APB_RST_LPD_IOU2_SWDT_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_SWDT_RESET_SHIFT 15 +#define CRL_APB_RST_LPD_IOU2_SWDT_RESET_MASK 0x00008000U -/*Block level reset*/ +/* +* Block level reset +*/ #undef CRL_APB_RST_LPD_IOU2_TTC0_RESET_DEFVAL #undef CRL_APB_RST_LPD_IOU2_TTC0_RESET_SHIFT #undef CRL_APB_RST_LPD_IOU2_TTC0_RESET_MASK -#define CRL_APB_RST_LPD_IOU2_TTC0_RESET_DEFVAL 0x0017FFFF -#define CRL_APB_RST_LPD_IOU2_TTC0_RESET_SHIFT 11 -#define CRL_APB_RST_LPD_IOU2_TTC0_RESET_MASK 0x00000800U +#define CRL_APB_RST_LPD_IOU2_TTC0_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_TTC0_RESET_SHIFT 11 +#define CRL_APB_RST_LPD_IOU2_TTC0_RESET_MASK 0x00000800U -/*Block level reset*/ +/* +* Block level reset +*/ #undef CRL_APB_RST_LPD_IOU2_TTC1_RESET_DEFVAL #undef CRL_APB_RST_LPD_IOU2_TTC1_RESET_SHIFT #undef CRL_APB_RST_LPD_IOU2_TTC1_RESET_MASK -#define CRL_APB_RST_LPD_IOU2_TTC1_RESET_DEFVAL 0x0017FFFF -#define CRL_APB_RST_LPD_IOU2_TTC1_RESET_SHIFT 12 -#define CRL_APB_RST_LPD_IOU2_TTC1_RESET_MASK 0x00001000U +#define CRL_APB_RST_LPD_IOU2_TTC1_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_TTC1_RESET_SHIFT 12 +#define CRL_APB_RST_LPD_IOU2_TTC1_RESET_MASK 0x00001000U -/*Block level reset*/ +/* +* Block level reset +*/ #undef CRL_APB_RST_LPD_IOU2_TTC2_RESET_DEFVAL #undef CRL_APB_RST_LPD_IOU2_TTC2_RESET_SHIFT #undef CRL_APB_RST_LPD_IOU2_TTC2_RESET_MASK -#define CRL_APB_RST_LPD_IOU2_TTC2_RESET_DEFVAL 0x0017FFFF -#define CRL_APB_RST_LPD_IOU2_TTC2_RESET_SHIFT 13 -#define CRL_APB_RST_LPD_IOU2_TTC2_RESET_MASK 0x00002000U +#define CRL_APB_RST_LPD_IOU2_TTC2_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_TTC2_RESET_SHIFT 13 +#define CRL_APB_RST_LPD_IOU2_TTC2_RESET_MASK 0x00002000U -/*Block level reset*/ +/* +* Block level reset +*/ #undef CRL_APB_RST_LPD_IOU2_TTC3_RESET_DEFVAL #undef CRL_APB_RST_LPD_IOU2_TTC3_RESET_SHIFT #undef CRL_APB_RST_LPD_IOU2_TTC3_RESET_MASK -#define CRL_APB_RST_LPD_IOU2_TTC3_RESET_DEFVAL 0x0017FFFF -#define CRL_APB_RST_LPD_IOU2_TTC3_RESET_SHIFT 14 -#define CRL_APB_RST_LPD_IOU2_TTC3_RESET_MASK 0x00004000U +#define CRL_APB_RST_LPD_IOU2_TTC3_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_TTC3_RESET_SHIFT 14 +#define CRL_APB_RST_LPD_IOU2_TTC3_RESET_MASK 0x00004000U -/*Block level reset*/ +/* +* Block level reset +*/ #undef CRL_APB_RST_LPD_IOU2_UART0_RESET_DEFVAL #undef CRL_APB_RST_LPD_IOU2_UART0_RESET_SHIFT #undef CRL_APB_RST_LPD_IOU2_UART0_RESET_MASK -#define CRL_APB_RST_LPD_IOU2_UART0_RESET_DEFVAL 0x0017FFFF -#define CRL_APB_RST_LPD_IOU2_UART0_RESET_SHIFT 1 -#define CRL_APB_RST_LPD_IOU2_UART0_RESET_MASK 0x00000002U +#define CRL_APB_RST_LPD_IOU2_UART0_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_UART0_RESET_SHIFT 1 +#define CRL_APB_RST_LPD_IOU2_UART0_RESET_MASK 0x00000002U -/*Block level reset*/ +/* +* Block level reset +*/ #undef CRL_APB_RST_LPD_IOU2_UART1_RESET_DEFVAL #undef CRL_APB_RST_LPD_IOU2_UART1_RESET_SHIFT #undef CRL_APB_RST_LPD_IOU2_UART1_RESET_MASK -#define CRL_APB_RST_LPD_IOU2_UART1_RESET_DEFVAL 0x0017FFFF -#define CRL_APB_RST_LPD_IOU2_UART1_RESET_SHIFT 2 -#define CRL_APB_RST_LPD_IOU2_UART1_RESET_MASK 0x00000004U +#define CRL_APB_RST_LPD_IOU2_UART1_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_UART1_RESET_SHIFT 2 +#define CRL_APB_RST_LPD_IOU2_UART1_RESET_MASK 0x00000004U -/*Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate*/ +/* +* Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate +*/ #undef UART0_BAUD_RATE_DIVIDER_REG0_BDIV_DEFVAL #undef UART0_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT #undef UART0_BAUD_RATE_DIVIDER_REG0_BDIV_MASK -#define UART0_BAUD_RATE_DIVIDER_REG0_BDIV_DEFVAL 0x0000000F -#define UART0_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT 0 -#define UART0_BAUD_RATE_DIVIDER_REG0_BDIV_MASK 0x000000FFU +#define UART0_BAUD_RATE_DIVIDER_REG0_BDIV_DEFVAL 0x0000000F +#define UART0_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT 0 +#define UART0_BAUD_RATE_DIVIDER_REG0_BDIV_MASK 0x000000FFU -/*Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample*/ +/* +* Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor + * bypass (baud_sample = sel_clk) 2 - 65535: baud_sample +*/ #undef UART0_BAUD_RATE_GEN_REG0_CD_DEFVAL #undef UART0_BAUD_RATE_GEN_REG0_CD_SHIFT #undef UART0_BAUD_RATE_GEN_REG0_CD_MASK -#define UART0_BAUD_RATE_GEN_REG0_CD_DEFVAL 0x0000028B -#define UART0_BAUD_RATE_GEN_REG0_CD_SHIFT 0 -#define UART0_BAUD_RATE_GEN_REG0_CD_MASK 0x0000FFFFU +#define UART0_BAUD_RATE_GEN_REG0_CD_DEFVAL 0x0000028B +#define UART0_BAUD_RATE_GEN_REG0_CD_SHIFT 0 +#define UART0_BAUD_RATE_GEN_REG0_CD_MASK 0x0000FFFFU -/*Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a - high level during 12 bit periods. It can be set regardless of the value of STTBRK.*/ +/* +* Stop transmitter break: 0: no affect 1: stop transmission of the break a + * fter a minimum of one character length and transmit a high level during + * 12 bit periods. It can be set regardless of the value of STTBRK. +*/ #undef UART0_CONTROL_REG0_STPBRK_DEFVAL #undef UART0_CONTROL_REG0_STPBRK_SHIFT #undef UART0_CONTROL_REG0_STPBRK_MASK -#define UART0_CONTROL_REG0_STPBRK_DEFVAL 0x00000128 -#define UART0_CONTROL_REG0_STPBRK_SHIFT 8 -#define UART0_CONTROL_REG0_STPBRK_MASK 0x00000100U +#define UART0_CONTROL_REG0_STPBRK_DEFVAL 0x00000128 +#define UART0_CONTROL_REG0_STPBRK_SHIFT 8 +#define UART0_CONTROL_REG0_STPBRK_MASK 0x00000100U -/*Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the - transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high.*/ +/* +* Start transmitter break: 0: no affect 1: start to transmit a break after + * the characters currently present in the FIFO and the transmit shift reg + * ister have been transmitted. It can only be set if STPBRK (Stop transmit + * ter break) is not high. +*/ #undef UART0_CONTROL_REG0_STTBRK_DEFVAL #undef UART0_CONTROL_REG0_STTBRK_SHIFT #undef UART0_CONTROL_REG0_STTBRK_MASK -#define UART0_CONTROL_REG0_STTBRK_DEFVAL 0x00000128 -#define UART0_CONTROL_REG0_STTBRK_SHIFT 7 -#define UART0_CONTROL_REG0_STTBRK_MASK 0x00000080U +#define UART0_CONTROL_REG0_STTBRK_DEFVAL 0x00000128 +#define UART0_CONTROL_REG0_STTBRK_SHIFT 7 +#define UART0_CONTROL_REG0_STTBRK_MASK 0x00000080U -/*Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has co - pleted.*/ +/* +* Restart receiver timeout counter: 1: receiver timeout counter is restart + * ed. This bit is self clearing once the restart has completed. +*/ #undef UART0_CONTROL_REG0_RSTTO_DEFVAL #undef UART0_CONTROL_REG0_RSTTO_SHIFT #undef UART0_CONTROL_REG0_RSTTO_MASK -#define UART0_CONTROL_REG0_RSTTO_DEFVAL 0x00000128 -#define UART0_CONTROL_REG0_RSTTO_SHIFT 6 -#define UART0_CONTROL_REG0_RSTTO_MASK 0x00000040U +#define UART0_CONTROL_REG0_RSTTO_DEFVAL 0x00000128 +#define UART0_CONTROL_REG0_RSTTO_SHIFT 6 +#define UART0_CONTROL_REG0_RSTTO_MASK 0x00000040U -/*Transmit disable: 0: enable transmitter 1: disable transmitter*/ +/* +* Transmit disable: 0: enable transmitter 1: disable transmitter +*/ #undef UART0_CONTROL_REG0_TXDIS_DEFVAL #undef UART0_CONTROL_REG0_TXDIS_SHIFT #undef UART0_CONTROL_REG0_TXDIS_MASK -#define UART0_CONTROL_REG0_TXDIS_DEFVAL 0x00000128 -#define UART0_CONTROL_REG0_TXDIS_SHIFT 5 -#define UART0_CONTROL_REG0_TXDIS_MASK 0x00000020U +#define UART0_CONTROL_REG0_TXDIS_DEFVAL 0x00000128 +#define UART0_CONTROL_REG0_TXDIS_SHIFT 5 +#define UART0_CONTROL_REG0_TXDIS_MASK 0x00000020U -/*Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0.*/ +/* +* Transmit enable: 0: disable transmitter 1: enable transmitter, provided + * the TXDIS field is set to 0. +*/ #undef UART0_CONTROL_REG0_TXEN_DEFVAL #undef UART0_CONTROL_REG0_TXEN_SHIFT #undef UART0_CONTROL_REG0_TXEN_MASK -#define UART0_CONTROL_REG0_TXEN_DEFVAL 0x00000128 -#define UART0_CONTROL_REG0_TXEN_SHIFT 4 -#define UART0_CONTROL_REG0_TXEN_MASK 0x00000010U +#define UART0_CONTROL_REG0_TXEN_DEFVAL 0x00000128 +#define UART0_CONTROL_REG0_TXEN_SHIFT 4 +#define UART0_CONTROL_REG0_TXEN_MASK 0x00000010U -/*Receive disable: 0: enable 1: disable, regardless of the value of RXEN*/ +/* +* Receive disable: 0: enable 1: disable, regardless of the value of RXEN +*/ #undef UART0_CONTROL_REG0_RXDIS_DEFVAL #undef UART0_CONTROL_REG0_RXDIS_SHIFT #undef UART0_CONTROL_REG0_RXDIS_MASK -#define UART0_CONTROL_REG0_RXDIS_DEFVAL 0x00000128 -#define UART0_CONTROL_REG0_RXDIS_SHIFT 3 -#define UART0_CONTROL_REG0_RXDIS_MASK 0x00000008U +#define UART0_CONTROL_REG0_RXDIS_DEFVAL 0x00000128 +#define UART0_CONTROL_REG0_RXDIS_SHIFT 3 +#define UART0_CONTROL_REG0_RXDIS_MASK 0x00000008U -/*Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero.*/ +/* +* Receive enable: 0: disable 1: enable When set to one, the receiver logic + * is enabled, provided the RXDIS field is set to zero. +*/ #undef UART0_CONTROL_REG0_RXEN_DEFVAL #undef UART0_CONTROL_REG0_RXEN_SHIFT #undef UART0_CONTROL_REG0_RXEN_MASK -#define UART0_CONTROL_REG0_RXEN_DEFVAL 0x00000128 -#define UART0_CONTROL_REG0_RXEN_SHIFT 2 -#define UART0_CONTROL_REG0_RXEN_MASK 0x00000004U +#define UART0_CONTROL_REG0_RXEN_DEFVAL 0x00000128 +#define UART0_CONTROL_REG0_RXEN_SHIFT 2 +#define UART0_CONTROL_REG0_RXEN_MASK 0x00000004U -/*Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded Thi - bit is self clearing once the reset has completed.*/ +/* +* Software reset for Tx data path: 0: no affect 1: transmitter logic is re + * set and all pending transmitter data is discarded This bit is self clear + * ing once the reset has completed. +*/ #undef UART0_CONTROL_REG0_TXRES_DEFVAL #undef UART0_CONTROL_REG0_TXRES_SHIFT #undef UART0_CONTROL_REG0_TXRES_MASK -#define UART0_CONTROL_REG0_TXRES_DEFVAL 0x00000128 -#define UART0_CONTROL_REG0_TXRES_SHIFT 1 -#define UART0_CONTROL_REG0_TXRES_MASK 0x00000002U +#define UART0_CONTROL_REG0_TXRES_DEFVAL 0x00000128 +#define UART0_CONTROL_REG0_TXRES_SHIFT 1 +#define UART0_CONTROL_REG0_TXRES_MASK 0x00000002U -/*Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit - is self clearing once the reset has completed.*/ +/* +* Software reset for Rx data path: 0: no affect 1: receiver logic is reset + * and all pending receiver data is discarded. This bit is self clearing o + * nce the reset has completed. +*/ #undef UART0_CONTROL_REG0_RXRES_DEFVAL #undef UART0_CONTROL_REG0_RXRES_SHIFT #undef UART0_CONTROL_REG0_RXRES_MASK -#define UART0_CONTROL_REG0_RXRES_DEFVAL 0x00000128 -#define UART0_CONTROL_REG0_RXRES_SHIFT 0 -#define UART0_CONTROL_REG0_RXRES_MASK 0x00000001U +#define UART0_CONTROL_REG0_RXRES_DEFVAL 0x00000128 +#define UART0_CONTROL_REG0_RXRES_SHIFT 0 +#define UART0_CONTROL_REG0_RXRES_MASK 0x00000001U -/*Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback*/ +/* +* Channel mode: Defines the mode of operation of the UART. 00: normal 01: + * automatic echo 10: local loopback 11: remote loopback +*/ #undef UART0_MODE_REG0_CHMODE_DEFVAL #undef UART0_MODE_REG0_CHMODE_SHIFT #undef UART0_MODE_REG0_CHMODE_MASK -#define UART0_MODE_REG0_CHMODE_DEFVAL 0x00000000 -#define UART0_MODE_REG0_CHMODE_SHIFT 8 -#define UART0_MODE_REG0_CHMODE_MASK 0x00000300U +#define UART0_MODE_REG0_CHMODE_DEFVAL 0x00000000 +#define UART0_MODE_REG0_CHMODE_SHIFT 8 +#define UART0_MODE_REG0_CHMODE_MASK 0x00000300U -/*Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5 - stop bits 10: 2 stop bits 11: reserved*/ +/* +* Number of stop bits: Defines the number of stop bits to detect on receiv + * e and to generate on transmit. 00: 1 stop bit 01: 1.5 stop bits 10: 2 st + * op bits 11: reserved +*/ #undef UART0_MODE_REG0_NBSTOP_DEFVAL #undef UART0_MODE_REG0_NBSTOP_SHIFT #undef UART0_MODE_REG0_NBSTOP_MASK -#define UART0_MODE_REG0_NBSTOP_DEFVAL 0x00000000 -#define UART0_MODE_REG0_NBSTOP_SHIFT 6 -#define UART0_MODE_REG0_NBSTOP_MASK 0x000000C0U +#define UART0_MODE_REG0_NBSTOP_DEFVAL 0x00000000 +#define UART0_MODE_REG0_NBSTOP_SHIFT 6 +#define UART0_MODE_REG0_NBSTOP_MASK 0x000000C0U -/*Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity - 01: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity*/ +/* +* Parity type select: Defines the expected parity to check on receive and + * the parity to generate on transmit. 000: even parity 001: odd parity 010 + * : forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no pari + * ty +*/ #undef UART0_MODE_REG0_PAR_DEFVAL #undef UART0_MODE_REG0_PAR_SHIFT #undef UART0_MODE_REG0_PAR_MASK -#define UART0_MODE_REG0_PAR_DEFVAL 0x00000000 -#define UART0_MODE_REG0_PAR_SHIFT 3 -#define UART0_MODE_REG0_PAR_MASK 0x00000038U +#define UART0_MODE_REG0_PAR_DEFVAL 0x00000000 +#define UART0_MODE_REG0_PAR_SHIFT 3 +#define UART0_MODE_REG0_PAR_MASK 0x00000038U -/*Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits*/ +/* +* Character length select: Defines the number of bits in each character. 1 + * 1: 6 bits 10: 7 bits 0x: 8 bits +*/ #undef UART0_MODE_REG0_CHRL_DEFVAL #undef UART0_MODE_REG0_CHRL_SHIFT #undef UART0_MODE_REG0_CHRL_MASK -#define UART0_MODE_REG0_CHRL_DEFVAL 0x00000000 -#define UART0_MODE_REG0_CHRL_SHIFT 1 -#define UART0_MODE_REG0_CHRL_MASK 0x00000006U +#define UART0_MODE_REG0_CHRL_DEFVAL 0x00000000 +#define UART0_MODE_REG0_CHRL_SHIFT 1 +#define UART0_MODE_REG0_CHRL_MASK 0x00000006U -/*Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock - source is uart_ref_clk 1: clock source is uart_ref_clk/8*/ +/* +* Clock source select: This field defines whether a pre-scalar of 8 is app + * lied to the baud rate generator input clock. 0: clock source is uart_ref + * _clk 1: clock source is uart_ref_clk/8 +*/ #undef UART0_MODE_REG0_CLKS_DEFVAL #undef UART0_MODE_REG0_CLKS_SHIFT #undef UART0_MODE_REG0_CLKS_MASK -#define UART0_MODE_REG0_CLKS_DEFVAL 0x00000000 -#define UART0_MODE_REG0_CLKS_SHIFT 0 -#define UART0_MODE_REG0_CLKS_MASK 0x00000001U +#define UART0_MODE_REG0_CLKS_DEFVAL 0x00000000 +#define UART0_MODE_REG0_CLKS_SHIFT 0 +#define UART0_MODE_REG0_CLKS_MASK 0x00000001U -/*Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate*/ +/* +* Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate +*/ #undef UART1_BAUD_RATE_DIVIDER_REG0_BDIV_DEFVAL #undef UART1_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT #undef UART1_BAUD_RATE_DIVIDER_REG0_BDIV_MASK -#define UART1_BAUD_RATE_DIVIDER_REG0_BDIV_DEFVAL 0x0000000F -#define UART1_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT 0 -#define UART1_BAUD_RATE_DIVIDER_REG0_BDIV_MASK 0x000000FFU +#define UART1_BAUD_RATE_DIVIDER_REG0_BDIV_DEFVAL 0x0000000F +#define UART1_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT 0 +#define UART1_BAUD_RATE_DIVIDER_REG0_BDIV_MASK 0x000000FFU -/*Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample*/ +/* +* Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor + * bypass (baud_sample = sel_clk) 2 - 65535: baud_sample +*/ #undef UART1_BAUD_RATE_GEN_REG0_CD_DEFVAL #undef UART1_BAUD_RATE_GEN_REG0_CD_SHIFT #undef UART1_BAUD_RATE_GEN_REG0_CD_MASK -#define UART1_BAUD_RATE_GEN_REG0_CD_DEFVAL 0x0000028B -#define UART1_BAUD_RATE_GEN_REG0_CD_SHIFT 0 -#define UART1_BAUD_RATE_GEN_REG0_CD_MASK 0x0000FFFFU +#define UART1_BAUD_RATE_GEN_REG0_CD_DEFVAL 0x0000028B +#define UART1_BAUD_RATE_GEN_REG0_CD_SHIFT 0 +#define UART1_BAUD_RATE_GEN_REG0_CD_MASK 0x0000FFFFU -/*Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a - high level during 12 bit periods. It can be set regardless of the value of STTBRK.*/ +/* +* Stop transmitter break: 0: no affect 1: stop transmission of the break a + * fter a minimum of one character length and transmit a high level during + * 12 bit periods. It can be set regardless of the value of STTBRK. +*/ #undef UART1_CONTROL_REG0_STPBRK_DEFVAL #undef UART1_CONTROL_REG0_STPBRK_SHIFT #undef UART1_CONTROL_REG0_STPBRK_MASK -#define UART1_CONTROL_REG0_STPBRK_DEFVAL 0x00000128 -#define UART1_CONTROL_REG0_STPBRK_SHIFT 8 -#define UART1_CONTROL_REG0_STPBRK_MASK 0x00000100U +#define UART1_CONTROL_REG0_STPBRK_DEFVAL 0x00000128 +#define UART1_CONTROL_REG0_STPBRK_SHIFT 8 +#define UART1_CONTROL_REG0_STPBRK_MASK 0x00000100U -/*Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the - transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high.*/ +/* +* Start transmitter break: 0: no affect 1: start to transmit a break after + * the characters currently present in the FIFO and the transmit shift reg + * ister have been transmitted. It can only be set if STPBRK (Stop transmit + * ter break) is not high. +*/ #undef UART1_CONTROL_REG0_STTBRK_DEFVAL #undef UART1_CONTROL_REG0_STTBRK_SHIFT #undef UART1_CONTROL_REG0_STTBRK_MASK -#define UART1_CONTROL_REG0_STTBRK_DEFVAL 0x00000128 -#define UART1_CONTROL_REG0_STTBRK_SHIFT 7 -#define UART1_CONTROL_REG0_STTBRK_MASK 0x00000080U +#define UART1_CONTROL_REG0_STTBRK_DEFVAL 0x00000128 +#define UART1_CONTROL_REG0_STTBRK_SHIFT 7 +#define UART1_CONTROL_REG0_STTBRK_MASK 0x00000080U -/*Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has co - pleted.*/ +/* +* Restart receiver timeout counter: 1: receiver timeout counter is restart + * ed. This bit is self clearing once the restart has completed. +*/ #undef UART1_CONTROL_REG0_RSTTO_DEFVAL #undef UART1_CONTROL_REG0_RSTTO_SHIFT #undef UART1_CONTROL_REG0_RSTTO_MASK -#define UART1_CONTROL_REG0_RSTTO_DEFVAL 0x00000128 -#define UART1_CONTROL_REG0_RSTTO_SHIFT 6 -#define UART1_CONTROL_REG0_RSTTO_MASK 0x00000040U +#define UART1_CONTROL_REG0_RSTTO_DEFVAL 0x00000128 +#define UART1_CONTROL_REG0_RSTTO_SHIFT 6 +#define UART1_CONTROL_REG0_RSTTO_MASK 0x00000040U -/*Transmit disable: 0: enable transmitter 1: disable transmitter*/ +/* +* Transmit disable: 0: enable transmitter 1: disable transmitter +*/ #undef UART1_CONTROL_REG0_TXDIS_DEFVAL #undef UART1_CONTROL_REG0_TXDIS_SHIFT #undef UART1_CONTROL_REG0_TXDIS_MASK -#define UART1_CONTROL_REG0_TXDIS_DEFVAL 0x00000128 -#define UART1_CONTROL_REG0_TXDIS_SHIFT 5 -#define UART1_CONTROL_REG0_TXDIS_MASK 0x00000020U +#define UART1_CONTROL_REG0_TXDIS_DEFVAL 0x00000128 +#define UART1_CONTROL_REG0_TXDIS_SHIFT 5 +#define UART1_CONTROL_REG0_TXDIS_MASK 0x00000020U -/*Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0.*/ +/* +* Transmit enable: 0: disable transmitter 1: enable transmitter, provided + * the TXDIS field is set to 0. +*/ #undef UART1_CONTROL_REG0_TXEN_DEFVAL #undef UART1_CONTROL_REG0_TXEN_SHIFT #undef UART1_CONTROL_REG0_TXEN_MASK -#define UART1_CONTROL_REG0_TXEN_DEFVAL 0x00000128 -#define UART1_CONTROL_REG0_TXEN_SHIFT 4 -#define UART1_CONTROL_REG0_TXEN_MASK 0x00000010U +#define UART1_CONTROL_REG0_TXEN_DEFVAL 0x00000128 +#define UART1_CONTROL_REG0_TXEN_SHIFT 4 +#define UART1_CONTROL_REG0_TXEN_MASK 0x00000010U -/*Receive disable: 0: enable 1: disable, regardless of the value of RXEN*/ +/* +* Receive disable: 0: enable 1: disable, regardless of the value of RXEN +*/ #undef UART1_CONTROL_REG0_RXDIS_DEFVAL #undef UART1_CONTROL_REG0_RXDIS_SHIFT #undef UART1_CONTROL_REG0_RXDIS_MASK -#define UART1_CONTROL_REG0_RXDIS_DEFVAL 0x00000128 -#define UART1_CONTROL_REG0_RXDIS_SHIFT 3 -#define UART1_CONTROL_REG0_RXDIS_MASK 0x00000008U +#define UART1_CONTROL_REG0_RXDIS_DEFVAL 0x00000128 +#define UART1_CONTROL_REG0_RXDIS_SHIFT 3 +#define UART1_CONTROL_REG0_RXDIS_MASK 0x00000008U -/*Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero.*/ +/* +* Receive enable: 0: disable 1: enable When set to one, the receiver logic + * is enabled, provided the RXDIS field is set to zero. +*/ #undef UART1_CONTROL_REG0_RXEN_DEFVAL #undef UART1_CONTROL_REG0_RXEN_SHIFT #undef UART1_CONTROL_REG0_RXEN_MASK -#define UART1_CONTROL_REG0_RXEN_DEFVAL 0x00000128 -#define UART1_CONTROL_REG0_RXEN_SHIFT 2 -#define UART1_CONTROL_REG0_RXEN_MASK 0x00000004U +#define UART1_CONTROL_REG0_RXEN_DEFVAL 0x00000128 +#define UART1_CONTROL_REG0_RXEN_SHIFT 2 +#define UART1_CONTROL_REG0_RXEN_MASK 0x00000004U -/*Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded Thi - bit is self clearing once the reset has completed.*/ +/* +* Software reset for Tx data path: 0: no affect 1: transmitter logic is re + * set and all pending transmitter data is discarded This bit is self clear + * ing once the reset has completed. +*/ #undef UART1_CONTROL_REG0_TXRES_DEFVAL #undef UART1_CONTROL_REG0_TXRES_SHIFT #undef UART1_CONTROL_REG0_TXRES_MASK -#define UART1_CONTROL_REG0_TXRES_DEFVAL 0x00000128 -#define UART1_CONTROL_REG0_TXRES_SHIFT 1 -#define UART1_CONTROL_REG0_TXRES_MASK 0x00000002U +#define UART1_CONTROL_REG0_TXRES_DEFVAL 0x00000128 +#define UART1_CONTROL_REG0_TXRES_SHIFT 1 +#define UART1_CONTROL_REG0_TXRES_MASK 0x00000002U -/*Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit - is self clearing once the reset has completed.*/ +/* +* Software reset for Rx data path: 0: no affect 1: receiver logic is reset + * and all pending receiver data is discarded. This bit is self clearing o + * nce the reset has completed. +*/ #undef UART1_CONTROL_REG0_RXRES_DEFVAL #undef UART1_CONTROL_REG0_RXRES_SHIFT #undef UART1_CONTROL_REG0_RXRES_MASK -#define UART1_CONTROL_REG0_RXRES_DEFVAL 0x00000128 -#define UART1_CONTROL_REG0_RXRES_SHIFT 0 -#define UART1_CONTROL_REG0_RXRES_MASK 0x00000001U +#define UART1_CONTROL_REG0_RXRES_DEFVAL 0x00000128 +#define UART1_CONTROL_REG0_RXRES_SHIFT 0 +#define UART1_CONTROL_REG0_RXRES_MASK 0x00000001U -/*Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback*/ +/* +* Channel mode: Defines the mode of operation of the UART. 00: normal 01: + * automatic echo 10: local loopback 11: remote loopback +*/ #undef UART1_MODE_REG0_CHMODE_DEFVAL #undef UART1_MODE_REG0_CHMODE_SHIFT #undef UART1_MODE_REG0_CHMODE_MASK -#define UART1_MODE_REG0_CHMODE_DEFVAL 0x00000000 -#define UART1_MODE_REG0_CHMODE_SHIFT 8 -#define UART1_MODE_REG0_CHMODE_MASK 0x00000300U +#define UART1_MODE_REG0_CHMODE_DEFVAL 0x00000000 +#define UART1_MODE_REG0_CHMODE_SHIFT 8 +#define UART1_MODE_REG0_CHMODE_MASK 0x00000300U -/*Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5 - stop bits 10: 2 stop bits 11: reserved*/ +/* +* Number of stop bits: Defines the number of stop bits to detect on receiv + * e and to generate on transmit. 00: 1 stop bit 01: 1.5 stop bits 10: 2 st + * op bits 11: reserved +*/ #undef UART1_MODE_REG0_NBSTOP_DEFVAL #undef UART1_MODE_REG0_NBSTOP_SHIFT #undef UART1_MODE_REG0_NBSTOP_MASK -#define UART1_MODE_REG0_NBSTOP_DEFVAL 0x00000000 -#define UART1_MODE_REG0_NBSTOP_SHIFT 6 -#define UART1_MODE_REG0_NBSTOP_MASK 0x000000C0U +#define UART1_MODE_REG0_NBSTOP_DEFVAL 0x00000000 +#define UART1_MODE_REG0_NBSTOP_SHIFT 6 +#define UART1_MODE_REG0_NBSTOP_MASK 0x000000C0U -/*Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity - 01: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity*/ +/* +* Parity type select: Defines the expected parity to check on receive and + * the parity to generate on transmit. 000: even parity 001: odd parity 010 + * : forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no pari + * ty +*/ #undef UART1_MODE_REG0_PAR_DEFVAL #undef UART1_MODE_REG0_PAR_SHIFT #undef UART1_MODE_REG0_PAR_MASK -#define UART1_MODE_REG0_PAR_DEFVAL 0x00000000 -#define UART1_MODE_REG0_PAR_SHIFT 3 -#define UART1_MODE_REG0_PAR_MASK 0x00000038U +#define UART1_MODE_REG0_PAR_DEFVAL 0x00000000 +#define UART1_MODE_REG0_PAR_SHIFT 3 +#define UART1_MODE_REG0_PAR_MASK 0x00000038U -/*Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits*/ +/* +* Character length select: Defines the number of bits in each character. 1 + * 1: 6 bits 10: 7 bits 0x: 8 bits +*/ #undef UART1_MODE_REG0_CHRL_DEFVAL #undef UART1_MODE_REG0_CHRL_SHIFT #undef UART1_MODE_REG0_CHRL_MASK -#define UART1_MODE_REG0_CHRL_DEFVAL 0x00000000 -#define UART1_MODE_REG0_CHRL_SHIFT 1 -#define UART1_MODE_REG0_CHRL_MASK 0x00000006U +#define UART1_MODE_REG0_CHRL_DEFVAL 0x00000000 +#define UART1_MODE_REG0_CHRL_SHIFT 1 +#define UART1_MODE_REG0_CHRL_MASK 0x00000006U -/*Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock - source is uart_ref_clk 1: clock source is uart_ref_clk/8*/ +/* +* Clock source select: This field defines whether a pre-scalar of 8 is app + * lied to the baud rate generator input clock. 0: clock source is uart_ref + * _clk 1: clock source is uart_ref_clk/8 +*/ #undef UART1_MODE_REG0_CLKS_DEFVAL #undef UART1_MODE_REG0_CLKS_SHIFT #undef UART1_MODE_REG0_CLKS_MASK -#define UART1_MODE_REG0_CLKS_DEFVAL 0x00000000 -#define UART1_MODE_REG0_CLKS_SHIFT 0 -#define UART1_MODE_REG0_CLKS_MASK 0x00000001U +#define UART1_MODE_REG0_CLKS_DEFVAL 0x00000000 +#define UART1_MODE_REG0_CLKS_SHIFT 0 +#define UART1_MODE_REG0_CLKS_MASK 0x00000001U -/*TrustZone Classification for ADMA*/ +/* +* Block level reset +*/ +#undef CRL_APB_RST_LPD_IOU2_GPIO_RESET_DEFVAL +#undef CRL_APB_RST_LPD_IOU2_GPIO_RESET_SHIFT +#undef CRL_APB_RST_LPD_IOU2_GPIO_RESET_MASK +#define CRL_APB_RST_LPD_IOU2_GPIO_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_GPIO_RESET_SHIFT 18 +#define CRL_APB_RST_LPD_IOU2_GPIO_RESET_MASK 0x00040000U + +/* +* TrustZone Classification for ADMA +*/ #undef LPD_SLCR_SECURE_SLCR_ADMA_TZ_DEFVAL #undef LPD_SLCR_SECURE_SLCR_ADMA_TZ_SHIFT #undef LPD_SLCR_SECURE_SLCR_ADMA_TZ_MASK -#define LPD_SLCR_SECURE_SLCR_ADMA_TZ_DEFVAL -#define LPD_SLCR_SECURE_SLCR_ADMA_TZ_SHIFT 0 -#define LPD_SLCR_SECURE_SLCR_ADMA_TZ_MASK 0x000000FFU +#define LPD_SLCR_SECURE_SLCR_ADMA_TZ_DEFVAL +#define LPD_SLCR_SECURE_SLCR_ADMA_TZ_SHIFT 0 +#define LPD_SLCR_SECURE_SLCR_ADMA_TZ_MASK 0x000000FFU -/*CSU regsiter*/ +/* +* CSU regsiter +*/ #undef CSU_TAMPER_STATUS_TAMPER_0_DEFVAL #undef CSU_TAMPER_STATUS_TAMPER_0_SHIFT #undef CSU_TAMPER_STATUS_TAMPER_0_MASK -#define CSU_TAMPER_STATUS_TAMPER_0_DEFVAL 0x00000000 -#define CSU_TAMPER_STATUS_TAMPER_0_SHIFT 0 -#define CSU_TAMPER_STATUS_TAMPER_0_MASK 0x00000001U +#define CSU_TAMPER_STATUS_TAMPER_0_DEFVAL 0x00000000 +#define CSU_TAMPER_STATUS_TAMPER_0_SHIFT 0 +#define CSU_TAMPER_STATUS_TAMPER_0_MASK 0x00000001U -/*External MIO*/ +/* +* External MIO +*/ #undef CSU_TAMPER_STATUS_TAMPER_1_DEFVAL #undef CSU_TAMPER_STATUS_TAMPER_1_SHIFT #undef CSU_TAMPER_STATUS_TAMPER_1_MASK -#define CSU_TAMPER_STATUS_TAMPER_1_DEFVAL 0x00000000 -#define CSU_TAMPER_STATUS_TAMPER_1_SHIFT 1 -#define CSU_TAMPER_STATUS_TAMPER_1_MASK 0x00000002U +#define CSU_TAMPER_STATUS_TAMPER_1_DEFVAL 0x00000000 +#define CSU_TAMPER_STATUS_TAMPER_1_SHIFT 1 +#define CSU_TAMPER_STATUS_TAMPER_1_MASK 0x00000002U -/*JTAG toggle detect*/ +/* +* JTAG toggle detect +*/ #undef CSU_TAMPER_STATUS_TAMPER_2_DEFVAL #undef CSU_TAMPER_STATUS_TAMPER_2_SHIFT #undef CSU_TAMPER_STATUS_TAMPER_2_MASK -#define CSU_TAMPER_STATUS_TAMPER_2_DEFVAL 0x00000000 -#define CSU_TAMPER_STATUS_TAMPER_2_SHIFT 2 -#define CSU_TAMPER_STATUS_TAMPER_2_MASK 0x00000004U +#define CSU_TAMPER_STATUS_TAMPER_2_DEFVAL 0x00000000 +#define CSU_TAMPER_STATUS_TAMPER_2_SHIFT 2 +#define CSU_TAMPER_STATUS_TAMPER_2_MASK 0x00000004U -/*PL SEU error*/ +/* +* PL SEU error +*/ #undef CSU_TAMPER_STATUS_TAMPER_3_DEFVAL #undef CSU_TAMPER_STATUS_TAMPER_3_SHIFT #undef CSU_TAMPER_STATUS_TAMPER_3_MASK -#define CSU_TAMPER_STATUS_TAMPER_3_DEFVAL 0x00000000 -#define CSU_TAMPER_STATUS_TAMPER_3_SHIFT 3 -#define CSU_TAMPER_STATUS_TAMPER_3_MASK 0x00000008U +#define CSU_TAMPER_STATUS_TAMPER_3_DEFVAL 0x00000000 +#define CSU_TAMPER_STATUS_TAMPER_3_SHIFT 3 +#define CSU_TAMPER_STATUS_TAMPER_3_MASK 0x00000008U -/*AMS over temperature alarm for LPD*/ +/* +* AMS over temperature alarm for LPD +*/ #undef CSU_TAMPER_STATUS_TAMPER_4_DEFVAL #undef CSU_TAMPER_STATUS_TAMPER_4_SHIFT #undef CSU_TAMPER_STATUS_TAMPER_4_MASK -#define CSU_TAMPER_STATUS_TAMPER_4_DEFVAL 0x00000000 -#define CSU_TAMPER_STATUS_TAMPER_4_SHIFT 4 -#define CSU_TAMPER_STATUS_TAMPER_4_MASK 0x00000010U +#define CSU_TAMPER_STATUS_TAMPER_4_DEFVAL 0x00000000 +#define CSU_TAMPER_STATUS_TAMPER_4_SHIFT 4 +#define CSU_TAMPER_STATUS_TAMPER_4_MASK 0x00000010U -/*AMS over temperature alarm for APU*/ +/* +* AMS over temperature alarm for APU +*/ #undef CSU_TAMPER_STATUS_TAMPER_5_DEFVAL #undef CSU_TAMPER_STATUS_TAMPER_5_SHIFT #undef CSU_TAMPER_STATUS_TAMPER_5_MASK -#define CSU_TAMPER_STATUS_TAMPER_5_DEFVAL 0x00000000 -#define CSU_TAMPER_STATUS_TAMPER_5_SHIFT 5 -#define CSU_TAMPER_STATUS_TAMPER_5_MASK 0x00000020U +#define CSU_TAMPER_STATUS_TAMPER_5_DEFVAL 0x00000000 +#define CSU_TAMPER_STATUS_TAMPER_5_SHIFT 5 +#define CSU_TAMPER_STATUS_TAMPER_5_MASK 0x00000020U -/*AMS voltage alarm for VCCPINT_FPD*/ +/* +* AMS voltage alarm for VCCPINT_FPD +*/ #undef CSU_TAMPER_STATUS_TAMPER_6_DEFVAL #undef CSU_TAMPER_STATUS_TAMPER_6_SHIFT #undef CSU_TAMPER_STATUS_TAMPER_6_MASK -#define CSU_TAMPER_STATUS_TAMPER_6_DEFVAL 0x00000000 -#define CSU_TAMPER_STATUS_TAMPER_6_SHIFT 6 -#define CSU_TAMPER_STATUS_TAMPER_6_MASK 0x00000040U +#define CSU_TAMPER_STATUS_TAMPER_6_DEFVAL 0x00000000 +#define CSU_TAMPER_STATUS_TAMPER_6_SHIFT 6 +#define CSU_TAMPER_STATUS_TAMPER_6_MASK 0x00000040U -/*AMS voltage alarm for VCCPINT_LPD*/ +/* +* AMS voltage alarm for VCCPINT_LPD +*/ #undef CSU_TAMPER_STATUS_TAMPER_7_DEFVAL #undef CSU_TAMPER_STATUS_TAMPER_7_SHIFT #undef CSU_TAMPER_STATUS_TAMPER_7_MASK -#define CSU_TAMPER_STATUS_TAMPER_7_DEFVAL 0x00000000 -#define CSU_TAMPER_STATUS_TAMPER_7_SHIFT 7 -#define CSU_TAMPER_STATUS_TAMPER_7_MASK 0x00000080U +#define CSU_TAMPER_STATUS_TAMPER_7_DEFVAL 0x00000000 +#define CSU_TAMPER_STATUS_TAMPER_7_SHIFT 7 +#define CSU_TAMPER_STATUS_TAMPER_7_MASK 0x00000080U -/*AMS voltage alarm for VCCPAUX*/ +/* +* AMS voltage alarm for VCCPAUX +*/ #undef CSU_TAMPER_STATUS_TAMPER_8_DEFVAL #undef CSU_TAMPER_STATUS_TAMPER_8_SHIFT #undef CSU_TAMPER_STATUS_TAMPER_8_MASK -#define CSU_TAMPER_STATUS_TAMPER_8_DEFVAL 0x00000000 -#define CSU_TAMPER_STATUS_TAMPER_8_SHIFT 8 -#define CSU_TAMPER_STATUS_TAMPER_8_MASK 0x00000100U +#define CSU_TAMPER_STATUS_TAMPER_8_DEFVAL 0x00000000 +#define CSU_TAMPER_STATUS_TAMPER_8_SHIFT 8 +#define CSU_TAMPER_STATUS_TAMPER_8_MASK 0x00000100U -/*AMS voltage alarm for DDRPHY*/ +/* +* AMS voltage alarm for DDRPHY +*/ #undef CSU_TAMPER_STATUS_TAMPER_9_DEFVAL #undef CSU_TAMPER_STATUS_TAMPER_9_SHIFT #undef CSU_TAMPER_STATUS_TAMPER_9_MASK -#define CSU_TAMPER_STATUS_TAMPER_9_DEFVAL 0x00000000 -#define CSU_TAMPER_STATUS_TAMPER_9_SHIFT 9 -#define CSU_TAMPER_STATUS_TAMPER_9_MASK 0x00000200U +#define CSU_TAMPER_STATUS_TAMPER_9_DEFVAL 0x00000000 +#define CSU_TAMPER_STATUS_TAMPER_9_SHIFT 9 +#define CSU_TAMPER_STATUS_TAMPER_9_MASK 0x00000200U -/*AMS voltage alarm for PSIO bank 0/1/2*/ +/* +* AMS voltage alarm for PSIO bank 0/1/2 +*/ #undef CSU_TAMPER_STATUS_TAMPER_10_DEFVAL #undef CSU_TAMPER_STATUS_TAMPER_10_SHIFT #undef CSU_TAMPER_STATUS_TAMPER_10_MASK -#define CSU_TAMPER_STATUS_TAMPER_10_DEFVAL 0x00000000 -#define CSU_TAMPER_STATUS_TAMPER_10_SHIFT 10 -#define CSU_TAMPER_STATUS_TAMPER_10_MASK 0x00000400U +#define CSU_TAMPER_STATUS_TAMPER_10_DEFVAL 0x00000000 +#define CSU_TAMPER_STATUS_TAMPER_10_SHIFT 10 +#define CSU_TAMPER_STATUS_TAMPER_10_MASK 0x00000400U -/*AMS voltage alarm for PSIO bank 3 (dedicated pins)*/ +/* +* AMS voltage alarm for PSIO bank 3 (dedicated pins) +*/ #undef CSU_TAMPER_STATUS_TAMPER_11_DEFVAL #undef CSU_TAMPER_STATUS_TAMPER_11_SHIFT #undef CSU_TAMPER_STATUS_TAMPER_11_MASK -#define CSU_TAMPER_STATUS_TAMPER_11_DEFVAL 0x00000000 -#define CSU_TAMPER_STATUS_TAMPER_11_SHIFT 11 -#define CSU_TAMPER_STATUS_TAMPER_11_MASK 0x00000800U +#define CSU_TAMPER_STATUS_TAMPER_11_DEFVAL 0x00000000 +#define CSU_TAMPER_STATUS_TAMPER_11_SHIFT 11 +#define CSU_TAMPER_STATUS_TAMPER_11_MASK 0x00000800U -/*AMS voltaage alarm for GT*/ +/* +* AMS voltaage alarm for GT +*/ #undef CSU_TAMPER_STATUS_TAMPER_12_DEFVAL #undef CSU_TAMPER_STATUS_TAMPER_12_SHIFT #undef CSU_TAMPER_STATUS_TAMPER_12_MASK -#define CSU_TAMPER_STATUS_TAMPER_12_DEFVAL 0x00000000 -#define CSU_TAMPER_STATUS_TAMPER_12_SHIFT 12 -#define CSU_TAMPER_STATUS_TAMPER_12_MASK 0x00001000U +#define CSU_TAMPER_STATUS_TAMPER_12_DEFVAL 0x00000000 +#define CSU_TAMPER_STATUS_TAMPER_12_SHIFT 12 +#define CSU_TAMPER_STATUS_TAMPER_12_MASK 0x00001000U -/*Set ACE outgoing AWQOS value*/ +/* +* Set ACE outgoing AWQOS value +*/ #undef APU_ACE_CTRL_AWQOS_DEFVAL #undef APU_ACE_CTRL_AWQOS_SHIFT #undef APU_ACE_CTRL_AWQOS_MASK -#define APU_ACE_CTRL_AWQOS_DEFVAL 0x000F000F -#define APU_ACE_CTRL_AWQOS_SHIFT 16 -#define APU_ACE_CTRL_AWQOS_MASK 0x000F0000U +#define APU_ACE_CTRL_AWQOS_DEFVAL 0x000F000F +#define APU_ACE_CTRL_AWQOS_SHIFT 16 +#define APU_ACE_CTRL_AWQOS_MASK 0x000F0000U -/*Set ACE outgoing ARQOS value*/ +/* +* Set ACE outgoing ARQOS value +*/ #undef APU_ACE_CTRL_ARQOS_DEFVAL #undef APU_ACE_CTRL_ARQOS_SHIFT #undef APU_ACE_CTRL_ARQOS_MASK -#define APU_ACE_CTRL_ARQOS_DEFVAL 0x000F000F -#define APU_ACE_CTRL_ARQOS_SHIFT 0 -#define APU_ACE_CTRL_ARQOS_MASK 0x0000000FU +#define APU_ACE_CTRL_ARQOS_DEFVAL 0x000F000F +#define APU_ACE_CTRL_ARQOS_SHIFT 0 +#define APU_ACE_CTRL_ARQOS_MASK 0x0000000FU -/*Enables the RTC. By writing a 0 to this bit, RTC will be powered off and the only module that potentially draws current from - he battery will be BBRAM. The value read through this bit does not necessarily reflect whether RTC is enabled or not. It is e - pected that RTC is enabled every time it is being configured. If RTC is not used in the design, FSBL will disable it by writi - g a 0 to this bit.*/ +/* +* Enables the RTC. By writing a 0 to this bit, RTC will be powered off and + * the only module that potentially draws current from the battery will be + * BBRAM. The value read through this bit does not necessarily reflect whe + * ther RTC is enabled or not. It is expected that RTC is enabled every tim + * e it is being configured. If RTC is not used in the design, FSBL will di + * sable it by writing a 0 to this bit. +*/ #undef RTC_CONTROL_BATTERY_DISABLE_DEFVAL #undef RTC_CONTROL_BATTERY_DISABLE_SHIFT #undef RTC_CONTROL_BATTERY_DISABLE_MASK -#define RTC_CONTROL_BATTERY_DISABLE_DEFVAL 0x01000000 -#define RTC_CONTROL_BATTERY_DISABLE_SHIFT 31 -#define RTC_CONTROL_BATTERY_DISABLE_MASK 0x80000000U +#define RTC_CONTROL_BATTERY_DISABLE_DEFVAL 0x01000000 +#define RTC_CONTROL_BATTERY_DISABLE_SHIFT 31 +#define RTC_CONTROL_BATTERY_DISABLE_MASK 0x80000000U -/*Frequency in number of ticks per second. Valid range from 10 MHz to 100 MHz.*/ +/* +* Frequency in number of ticks per second. Valid range from 10 MHz to 100 + * MHz. +*/ #undef IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_DEFVAL #undef IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_SHIFT #undef IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_MASK -#define IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_DEFVAL -#define IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_SHIFT 0 -#define IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_MASK 0xFFFFFFFFU +#define IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_DEFVAL +#define IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_SHIFT 0 +#define IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_MASK 0xFFFFFFFFU -/*Enable 0: The counter is disabled and not incrementing. 1: The counter is enabled and is incrementing.*/ +/* +* Enable 0: The counter is disabled and not incrementing. 1: The counter i + * s enabled and is incrementing. +*/ #undef IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_DEFVAL #undef IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_SHIFT #undef IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_MASK -#define IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_DEFVAL 0x00000000 -#define IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_SHIFT 0 -#define IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_MASK 0x00000001U -#undef LPD_XPPU_CFG_IEN_OFFSET -#define LPD_XPPU_CFG_IEN_OFFSET 0XFF980018 +#define IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_DEFVAL 0x00000000 +#define IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_SHIFT 0 +#define IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_MASK 0x00000001U -/*See Interuppt Status Register for details*/ -#undef LPD_XPPU_CFG_IEN_APER_PARITY_DEFVAL -#undef LPD_XPPU_CFG_IEN_APER_PARITY_SHIFT -#undef LPD_XPPU_CFG_IEN_APER_PARITY_MASK -#define LPD_XPPU_CFG_IEN_APER_PARITY_DEFVAL 0x00000000 -#define LPD_XPPU_CFG_IEN_APER_PARITY_SHIFT 7 -#define LPD_XPPU_CFG_IEN_APER_PARITY_MASK 0x00000080U +/* +* Operation is the same as DIRM_0[DIRECTION_0] +*/ +#undef GPIO_DIRM_1_DIRECTION_1_DEFVAL +#undef GPIO_DIRM_1_DIRECTION_1_SHIFT +#undef GPIO_DIRM_1_DIRECTION_1_MASK +#define GPIO_DIRM_1_DIRECTION_1_DEFVAL 0x00000000 +#define GPIO_DIRM_1_DIRECTION_1_SHIFT 0 +#define GPIO_DIRM_1_DIRECTION_1_MASK 0x03FFFFFFU -/*See Interuppt Status Register for details*/ -#undef LPD_XPPU_CFG_IEN_APER_TZ_DEFVAL -#undef LPD_XPPU_CFG_IEN_APER_TZ_SHIFT -#undef LPD_XPPU_CFG_IEN_APER_TZ_MASK -#define LPD_XPPU_CFG_IEN_APER_TZ_DEFVAL 0x00000000 -#define LPD_XPPU_CFG_IEN_APER_TZ_SHIFT 6 -#define LPD_XPPU_CFG_IEN_APER_TZ_MASK 0x00000040U +/* +* Operation is the same as OEN_0[OP_ENABLE_0] +*/ +#undef GPIO_OEN_1_OP_ENABLE_1_DEFVAL +#undef GPIO_OEN_1_OP_ENABLE_1_SHIFT +#undef GPIO_OEN_1_OP_ENABLE_1_MASK +#define GPIO_OEN_1_OP_ENABLE_1_DEFVAL 0x00000000 +#define GPIO_OEN_1_OP_ENABLE_1_SHIFT 0 +#define GPIO_OEN_1_OP_ENABLE_1_MASK 0x03FFFFFFU -/*See Interuppt Status Register for details*/ -#undef LPD_XPPU_CFG_IEN_APER_PERM_DEFVAL -#undef LPD_XPPU_CFG_IEN_APER_PERM_SHIFT -#undef LPD_XPPU_CFG_IEN_APER_PERM_MASK -#define LPD_XPPU_CFG_IEN_APER_PERM_DEFVAL 0x00000000 -#define LPD_XPPU_CFG_IEN_APER_PERM_SHIFT 5 -#define LPD_XPPU_CFG_IEN_APER_PERM_MASK 0x00000020U +/* +* Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW] +*/ +#undef GPIO_MASK_DATA_1_LSW_MASK_1_LSW_DEFVAL +#undef GPIO_MASK_DATA_1_LSW_MASK_1_LSW_SHIFT +#undef GPIO_MASK_DATA_1_LSW_MASK_1_LSW_MASK +#define GPIO_MASK_DATA_1_LSW_MASK_1_LSW_DEFVAL 0x00000000 +#define GPIO_MASK_DATA_1_LSW_MASK_1_LSW_SHIFT 16 +#define GPIO_MASK_DATA_1_LSW_MASK_1_LSW_MASK 0xFFFF0000U -/*See Interuppt Status Register for details*/ -#undef LPD_XPPU_CFG_IEN_MID_PARITY_DEFVAL -#undef LPD_XPPU_CFG_IEN_MID_PARITY_SHIFT -#undef LPD_XPPU_CFG_IEN_MID_PARITY_MASK -#define LPD_XPPU_CFG_IEN_MID_PARITY_DEFVAL 0x00000000 -#define LPD_XPPU_CFG_IEN_MID_PARITY_SHIFT 3 -#define LPD_XPPU_CFG_IEN_MID_PARITY_MASK 0x00000008U +/* +* Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW] +*/ +#undef GPIO_MASK_DATA_1_LSW_DATA_1_LSW_DEFVAL +#undef GPIO_MASK_DATA_1_LSW_DATA_1_LSW_SHIFT +#undef GPIO_MASK_DATA_1_LSW_DATA_1_LSW_MASK +#define GPIO_MASK_DATA_1_LSW_DATA_1_LSW_DEFVAL 0x00000000 +#define GPIO_MASK_DATA_1_LSW_DATA_1_LSW_SHIFT 0 +#define GPIO_MASK_DATA_1_LSW_DATA_1_LSW_MASK 0x0000FFFFU -/*See Interuppt Status Register for details*/ -#undef LPD_XPPU_CFG_IEN_MID_RO_DEFVAL -#undef LPD_XPPU_CFG_IEN_MID_RO_SHIFT -#undef LPD_XPPU_CFG_IEN_MID_RO_MASK -#define LPD_XPPU_CFG_IEN_MID_RO_DEFVAL 0x00000000 -#define LPD_XPPU_CFG_IEN_MID_RO_SHIFT 2 -#define LPD_XPPU_CFG_IEN_MID_RO_MASK 0x00000004U +/* +* Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW] +*/ +#undef GPIO_MASK_DATA_1_LSW_MASK_1_LSW_DEFVAL +#undef GPIO_MASK_DATA_1_LSW_MASK_1_LSW_SHIFT +#undef GPIO_MASK_DATA_1_LSW_MASK_1_LSW_MASK +#define GPIO_MASK_DATA_1_LSW_MASK_1_LSW_DEFVAL 0x00000000 +#define GPIO_MASK_DATA_1_LSW_MASK_1_LSW_SHIFT 16 +#define GPIO_MASK_DATA_1_LSW_MASK_1_LSW_MASK 0xFFFF0000U -/*See Interuppt Status Register for details*/ -#undef LPD_XPPU_CFG_IEN_MID_MISS_DEFVAL -#undef LPD_XPPU_CFG_IEN_MID_MISS_SHIFT -#undef LPD_XPPU_CFG_IEN_MID_MISS_MASK -#define LPD_XPPU_CFG_IEN_MID_MISS_DEFVAL 0x00000000 -#define LPD_XPPU_CFG_IEN_MID_MISS_SHIFT 1 -#define LPD_XPPU_CFG_IEN_MID_MISS_MASK 0x00000002U +/* +* Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW] +*/ +#undef GPIO_MASK_DATA_1_LSW_DATA_1_LSW_DEFVAL +#undef GPIO_MASK_DATA_1_LSW_DATA_1_LSW_SHIFT +#undef GPIO_MASK_DATA_1_LSW_DATA_1_LSW_MASK +#define GPIO_MASK_DATA_1_LSW_DATA_1_LSW_DEFVAL 0x00000000 +#define GPIO_MASK_DATA_1_LSW_DATA_1_LSW_SHIFT 0 +#define GPIO_MASK_DATA_1_LSW_DATA_1_LSW_MASK 0x0000FFFFU +#undef FPD_SLCR_SECURE_SLCR_DPDMA_OFFSET +#define FPD_SLCR_SECURE_SLCR_DPDMA_OFFSET 0XFD690040 +#undef FPD_SLCR_SECURE_SLCR_PCIE_OFFSET +#define FPD_SLCR_SECURE_SLCR_PCIE_OFFSET 0XFD690030 +#undef LPD_SLCR_SECURE_SLCR_USB_OFFSET +#define LPD_SLCR_SECURE_SLCR_USB_OFFSET 0XFF4B0034 +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_OFFSET +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_OFFSET 0XFF240004 +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET 0XFF240000 +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_OFFSET +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_OFFSET 0XFF240004 +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET 0XFF240000 +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET 0XFF240000 +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_OFFSET +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_OFFSET 0XFF240004 +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET 0XFF240000 +#undef LPD_SLCR_SECURE_SLCR_ADMA_OFFSET +#define LPD_SLCR_SECURE_SLCR_ADMA_OFFSET 0XFF4B0024 +#undef FPD_SLCR_SECURE_SLCR_GDMA_OFFSET +#define FPD_SLCR_SECURE_SLCR_GDMA_OFFSET 0XFD690050 -/*See Interuppt Status Register for details*/ -#undef LPD_XPPU_CFG_IEN_INV_APB_DEFVAL -#undef LPD_XPPU_CFG_IEN_INV_APB_SHIFT -#undef LPD_XPPU_CFG_IEN_INV_APB_MASK -#define LPD_XPPU_CFG_IEN_INV_APB_DEFVAL 0x00000000 -#define LPD_XPPU_CFG_IEN_INV_APB_SHIFT 0 -#define LPD_XPPU_CFG_IEN_INV_APB_MASK 0x00000001U +/* +* TrustZone classification for DisplayPort DMA +*/ +#undef FPD_SLCR_SECURE_SLCR_DPDMA_TZ_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_DPDMA_TZ_SHIFT +#undef FPD_SLCR_SECURE_SLCR_DPDMA_TZ_MASK +#define FPD_SLCR_SECURE_SLCR_DPDMA_TZ_DEFVAL 0x00000001 +#define FPD_SLCR_SECURE_SLCR_DPDMA_TZ_SHIFT 0 +#define FPD_SLCR_SECURE_SLCR_DPDMA_TZ_MASK 0x00000001U + +/* +* TrustZone classification for DMA Channel 0 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_0_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_0_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_0_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_0_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_0_SHIFT 21 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_0_MASK 0x00200000U + +/* +* TrustZone classification for DMA Channel 1 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_1_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_1_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_1_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_1_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_1_SHIFT 22 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_1_MASK 0x00400000U + +/* +* TrustZone classification for DMA Channel 2 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_2_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_2_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_2_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_2_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_2_SHIFT 23 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_2_MASK 0x00800000U + +/* +* TrustZone classification for DMA Channel 3 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_3_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_3_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_3_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_3_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_3_SHIFT 24 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_3_MASK 0x01000000U + +/* +* TrustZone classification for Ingress Address Translation 0 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_0_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_0_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_0_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_0_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_0_SHIFT 13 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_0_MASK 0x00002000U + +/* +* TrustZone classification for Ingress Address Translation 1 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_1_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_1_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_1_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_1_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_1_SHIFT 14 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_1_MASK 0x00004000U + +/* +* TrustZone classification for Ingress Address Translation 2 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_2_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_2_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_2_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_2_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_2_SHIFT 15 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_2_MASK 0x00008000U + +/* +* TrustZone classification for Ingress Address Translation 3 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_3_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_3_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_3_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_3_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_3_SHIFT 16 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_3_MASK 0x00010000U + +/* +* TrustZone classification for Ingress Address Translation 4 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_4_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_4_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_4_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_4_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_4_SHIFT 17 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_4_MASK 0x00020000U + +/* +* TrustZone classification for Ingress Address Translation 5 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_5_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_5_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_5_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_5_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_5_SHIFT 18 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_5_MASK 0x00040000U + +/* +* TrustZone classification for Ingress Address Translation 6 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_6_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_6_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_6_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_6_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_6_SHIFT 19 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_6_MASK 0x00080000U + +/* +* TrustZone classification for Ingress Address Translation 7 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_7_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_7_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_7_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_7_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_7_SHIFT 20 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_7_MASK 0x00100000U + +/* +* TrustZone classification for Egress Address Translation 0 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_0_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_0_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_0_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_0_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_0_SHIFT 5 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_0_MASK 0x00000020U + +/* +* TrustZone classification for Egress Address Translation 1 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_1_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_1_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_1_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_1_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_1_SHIFT 6 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_1_MASK 0x00000040U + +/* +* TrustZone classification for Egress Address Translation 2 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_2_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_2_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_2_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_2_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_2_SHIFT 7 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_2_MASK 0x00000080U + +/* +* TrustZone classification for Egress Address Translation 3 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_3_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_3_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_3_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_3_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_3_SHIFT 8 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_3_MASK 0x00000100U + +/* +* TrustZone classification for Egress Address Translation 4 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_4_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_4_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_4_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_4_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_4_SHIFT 9 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_4_MASK 0x00000200U + +/* +* TrustZone classification for Egress Address Translation 5 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_5_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_5_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_5_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_5_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_5_SHIFT 10 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_5_MASK 0x00000400U + +/* +* TrustZone classification for Egress Address Translation 6 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_6_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_6_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_6_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_6_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_6_SHIFT 11 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_6_MASK 0x00000800U + +/* +* TrustZone classification for Egress Address Translation 7 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_7_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_7_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_7_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_7_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_7_SHIFT 12 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_7_MASK 0x00001000U + +/* +* TrustZone classification for DMA Registers +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_REGS_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_REGS_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_REGS_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_REGS_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_REGS_SHIFT 4 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_REGS_MASK 0x00000010U + +/* +* TrustZone classification for MSIx Table +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_TABLE_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_TABLE_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_TABLE_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_TABLE_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_TABLE_SHIFT 2 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_TABLE_MASK 0x00000004U + +/* +* TrustZone classification for MSIx PBA +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_PBA_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_PBA_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_PBA_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_PBA_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_PBA_SHIFT 3 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_PBA_MASK 0x00000008U + +/* +* TrustZone classification for ECAM +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_ECAM_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_ECAM_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_ECAM_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_ECAM_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_ECAM_SHIFT 1 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_ECAM_MASK 0x00000002U + +/* +* TrustZone classification for Bridge Common Registers +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_BRIDGE_REGS_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_BRIDGE_REGS_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_BRIDGE_REGS_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_BRIDGE_REGS_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_BRIDGE_REGS_SHIFT 0 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_BRIDGE_REGS_MASK 0x00000001U + +/* +* TrustZone Classification for USB3_0 +*/ +#undef LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_0_DEFVAL +#undef LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_0_SHIFT +#undef LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_0_MASK +#define LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_0_DEFVAL 0x00000003 +#define LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_0_SHIFT 0 +#define LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_0_MASK 0x00000001U + +/* +* TrustZone Classification for USB3_1 +*/ +#undef LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_1_DEFVAL +#undef LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_1_SHIFT +#undef LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_1_MASK +#define LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_1_DEFVAL 0x00000003 +#define LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_1_SHIFT 1 +#define LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_1_MASK 0x00000002U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD0_AXI_ARPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD0_AXI_ARPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD0_AXI_ARPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD0_AXI_ARPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD0_AXI_ARPROT_SHIFT 16 +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD0_AXI_ARPROT_MASK 0x00070000U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD1_AXI_ARPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD1_AXI_ARPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD1_AXI_ARPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD1_AXI_ARPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD1_AXI_ARPROT_SHIFT 19 +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD1_AXI_ARPROT_MASK 0x00380000U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD0_AXI_AWPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD0_AXI_AWPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD0_AXI_AWPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD0_AXI_AWPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD0_AXI_AWPROT_SHIFT 16 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD0_AXI_AWPROT_MASK 0x00070000U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD1_AXI_AWPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD1_AXI_AWPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD1_AXI_AWPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD1_AXI_AWPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD1_AXI_AWPROT_SHIFT 19 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD1_AXI_AWPROT_MASK 0x00380000U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM0_AXI_ARPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM0_AXI_ARPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM0_AXI_ARPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM0_AXI_ARPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM0_AXI_ARPROT_SHIFT 0 +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM0_AXI_ARPROT_MASK 0x00000007U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM1_AXI_ARPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM1_AXI_ARPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM1_AXI_ARPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM1_AXI_ARPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM1_AXI_ARPROT_SHIFT 3 +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM1_AXI_ARPROT_MASK 0x00000038U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM2_AXI_ARPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM2_AXI_ARPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM2_AXI_ARPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM2_AXI_ARPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM2_AXI_ARPROT_SHIFT 6 +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM2_AXI_ARPROT_MASK 0x000001C0U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM3_AXI_ARPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM3_AXI_ARPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM3_AXI_ARPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM3_AXI_ARPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM3_AXI_ARPROT_SHIFT 9 +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM3_AXI_ARPROT_MASK 0x00000E00U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM0_AXI_AWPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM0_AXI_AWPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM0_AXI_AWPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM0_AXI_AWPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM0_AXI_AWPROT_SHIFT 0 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM0_AXI_AWPROT_MASK 0x00000007U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM1_AXI_AWPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM1_AXI_AWPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM1_AXI_AWPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM1_AXI_AWPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM1_AXI_AWPROT_SHIFT 3 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM1_AXI_AWPROT_MASK 0x00000038U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM2_AXI_AWPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM2_AXI_AWPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM2_AXI_AWPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM2_AXI_AWPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM2_AXI_AWPROT_SHIFT 6 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM2_AXI_AWPROT_MASK 0x000001C0U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM3_AXI_AWPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM3_AXI_AWPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM3_AXI_AWPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM3_AXI_AWPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM3_AXI_AWPROT_SHIFT 9 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM3_AXI_AWPROT_MASK 0x00000E00U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_QSPI_AXI_AWPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_QSPI_AXI_AWPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_QSPI_AXI_AWPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_QSPI_AXI_AWPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_QSPI_AXI_AWPROT_SHIFT 25 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_QSPI_AXI_AWPROT_MASK 0x0E000000U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_NAND_AXI_ARPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_NAND_AXI_ARPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_NAND_AXI_ARPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_NAND_AXI_ARPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_NAND_AXI_ARPROT_SHIFT 22 +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_NAND_AXI_ARPROT_MASK 0x01C00000U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_NAND_AXI_AWPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_NAND_AXI_AWPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_NAND_AXI_AWPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_NAND_AXI_AWPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_NAND_AXI_AWPROT_SHIFT 22 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_NAND_AXI_AWPROT_MASK 0x01C00000U + +/* +* TrustZone Classification for ADMA +*/ +#undef LPD_SLCR_SECURE_SLCR_ADMA_TZ_DEFVAL +#undef LPD_SLCR_SECURE_SLCR_ADMA_TZ_SHIFT +#undef LPD_SLCR_SECURE_SLCR_ADMA_TZ_MASK +#define LPD_SLCR_SECURE_SLCR_ADMA_TZ_DEFVAL +#define LPD_SLCR_SECURE_SLCR_ADMA_TZ_SHIFT 0 +#define LPD_SLCR_SECURE_SLCR_ADMA_TZ_MASK 0x000000FFU + +/* +* TrustZone Classification for GDMA +*/ +#undef FPD_SLCR_SECURE_SLCR_GDMA_TZ_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_GDMA_TZ_SHIFT +#undef FPD_SLCR_SECURE_SLCR_GDMA_TZ_MASK +#define FPD_SLCR_SECURE_SLCR_GDMA_TZ_DEFVAL +#define FPD_SLCR_SECURE_SLCR_GDMA_TZ_SHIFT 0 +#define FPD_SLCR_SECURE_SLCR_GDMA_TZ_MASK 0x000000FFU #undef SERDES_PLL_REF_SEL0_OFFSET #define SERDES_PLL_REF_SEL0_OFFSET 0XFD410000 #undef SERDES_PLL_REF_SEL1_OFFSET @@ -25320,8 +32847,6 @@ #define SERDES_L3_TM_DIG_6_OFFSET 0XFD40D06C #undef SERDES_L3_TX_DIG_TM_61_OFFSET #define SERDES_L3_TX_DIG_TM_61_OFFSET 0XFD40C0F4 -#undef SERDES_L3_TXPMA_ST_0_OFFSET -#define SERDES_L3_TXPMA_ST_0_OFFSET 0XFD40CB00 #undef SERDES_L0_TM_AUX_0_OFFSET #define SERDES_L0_TM_AUX_0_OFFSET 0XFD4010CC #undef SERDES_L2_TM_AUX_0_OFFSET @@ -25360,6 +32885,10 @@ #define SERDES_L0_TM_E_ILL8_OFFSET 0XFD401940 #undef SERDES_L0_TM_E_ILL9_OFFSET #define SERDES_L0_TM_E_ILL9_OFFSET 0XFD401944 +#undef SERDES_L0_TM_ILL13_OFFSET +#define SERDES_L0_TM_ILL13_OFFSET 0XFD401994 +#undef SERDES_L1_TM_ILL13_OFFSET +#define SERDES_L1_TM_ILL13_OFFSET 0XFD405994 #undef SERDES_L2_TM_MISC2_OFFSET #define SERDES_L2_TM_MISC2_OFFSET 0XFD40989C #undef SERDES_L2_TM_IQ_ILL1_OFFSET @@ -25386,6 +32915,8 @@ #define SERDES_L2_TM_E_ILL8_OFFSET 0XFD409940 #undef SERDES_L2_TM_E_ILL9_OFFSET #define SERDES_L2_TM_E_ILL9_OFFSET 0XFD409944 +#undef SERDES_L2_TM_ILL13_OFFSET +#define SERDES_L2_TM_ILL13_OFFSET 0XFD409994 #undef SERDES_L3_TM_MISC2_OFFSET #define SERDES_L3_TM_MISC2_OFFSET 0XFD40D89C #undef SERDES_L3_TM_IQ_ILL1_OFFSET @@ -25414,10 +32945,16 @@ #define SERDES_L3_TM_E_ILL8_OFFSET 0XFD40D940 #undef SERDES_L3_TM_E_ILL9_OFFSET #define SERDES_L3_TM_E_ILL9_OFFSET 0XFD40D944 -#undef SERDES_L0_TM_DIG_21_OFFSET -#define SERDES_L0_TM_DIG_21_OFFSET 0XFD4010A8 +#undef SERDES_L3_TM_ILL13_OFFSET +#define SERDES_L3_TM_ILL13_OFFSET 0XFD40D994 #undef SERDES_L0_TM_DIG_10_OFFSET #define SERDES_L0_TM_DIG_10_OFFSET 0XFD40107C +#undef SERDES_L1_TM_DIG_10_OFFSET +#define SERDES_L1_TM_DIG_10_OFFSET 0XFD40507C +#undef SERDES_L2_TM_DIG_10_OFFSET +#define SERDES_L2_TM_DIG_10_OFFSET 0XFD40907C +#undef SERDES_L3_TM_DIG_10_OFFSET +#define SERDES_L3_TM_DIG_10_OFFSET 0XFD40D07C #undef SERDES_L0_TM_RST_DLY_OFFSET #define SERDES_L0_TM_RST_DLY_OFFSET 0XFD4019A4 #undef SERDES_L0_TM_ANA_BYP_15_OFFSET @@ -25442,6 +32979,24 @@ #define SERDES_L3_TM_ANA_BYP_15_OFFSET 0XFD40D038 #undef SERDES_L3_TM_ANA_BYP_12_OFFSET #define SERDES_L3_TM_ANA_BYP_12_OFFSET 0XFD40D02C +#undef SERDES_L0_TM_MISC3_OFFSET +#define SERDES_L0_TM_MISC3_OFFSET 0XFD4019AC +#undef SERDES_L1_TM_MISC3_OFFSET +#define SERDES_L1_TM_MISC3_OFFSET 0XFD4059AC +#undef SERDES_L2_TM_MISC3_OFFSET +#define SERDES_L2_TM_MISC3_OFFSET 0XFD4099AC +#undef SERDES_L3_TM_MISC3_OFFSET +#define SERDES_L3_TM_MISC3_OFFSET 0XFD40D9AC +#undef SERDES_L0_TM_EQ11_OFFSET +#define SERDES_L0_TM_EQ11_OFFSET 0XFD401978 +#undef SERDES_L1_TM_EQ11_OFFSET +#define SERDES_L1_TM_EQ11_OFFSET 0XFD405978 +#undef SERDES_L2_TM_EQ11_OFFSET +#define SERDES_L2_TM_EQ11_OFFSET 0XFD409978 +#undef SERDES_L3_TM_EQ11_OFFSET +#define SERDES_L3_TM_EQ11_OFFSET 0XFD40D978 +#undef SIOU_ECO_0_OFFSET +#define SIOU_ECO_0_OFFSET 0XFD3D001C #undef SERDES_ICM_CFG0_OFFSET #define SERDES_ICM_CFG0_OFFSET 0XFD410010 #undef SERDES_ICM_CFG1_OFFSET @@ -25467,1055 +33022,1511 @@ #undef SERDES_L3_TX_ANA_TM_18_OFFSET #define SERDES_L3_TX_ANA_TM_18_OFFSET 0XFD40C048 -/*PLL0 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - - 4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135 - Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved*/ +/* +* PLL0 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 1 + * 2MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 24MHz, 0x8 - 26MHz, + * 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE + * - 108MHz, 0xF - 125MHz, 0x10 - 135MHz, 0x11 - 150 MHz. 0x12 to 0x1F - R + * eserved +*/ #undef SERDES_PLL_REF_SEL0_PLLREFSEL0_DEFVAL #undef SERDES_PLL_REF_SEL0_PLLREFSEL0_SHIFT #undef SERDES_PLL_REF_SEL0_PLLREFSEL0_MASK -#define SERDES_PLL_REF_SEL0_PLLREFSEL0_DEFVAL 0x0000000D -#define SERDES_PLL_REF_SEL0_PLLREFSEL0_SHIFT 0 -#define SERDES_PLL_REF_SEL0_PLLREFSEL0_MASK 0x0000001FU +#define SERDES_PLL_REF_SEL0_PLLREFSEL0_DEFVAL 0x0000000D +#define SERDES_PLL_REF_SEL0_PLLREFSEL0_SHIFT 0 +#define SERDES_PLL_REF_SEL0_PLLREFSEL0_MASK 0x0000001FU -/*PLL1 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - - 4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135 - Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved*/ +/* +* PLL1 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 1 + * 2MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 24MHz, 0x8 - 26MHz, + * 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE + * - 108MHz, 0xF - 125MHz, 0x10 - 135MHz, 0x11 - 150 MHz. 0x12 to 0x1F - R + * eserved +*/ #undef SERDES_PLL_REF_SEL1_PLLREFSEL1_DEFVAL #undef SERDES_PLL_REF_SEL1_PLLREFSEL1_SHIFT #undef SERDES_PLL_REF_SEL1_PLLREFSEL1_MASK -#define SERDES_PLL_REF_SEL1_PLLREFSEL1_DEFVAL 0x00000008 -#define SERDES_PLL_REF_SEL1_PLLREFSEL1_SHIFT 0 -#define SERDES_PLL_REF_SEL1_PLLREFSEL1_MASK 0x0000001FU +#define SERDES_PLL_REF_SEL1_PLLREFSEL1_DEFVAL 0x00000008 +#define SERDES_PLL_REF_SEL1_PLLREFSEL1_SHIFT 0 +#define SERDES_PLL_REF_SEL1_PLLREFSEL1_MASK 0x0000001FU -/*PLL2 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - - 4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135 - Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved*/ +/* +* PLL2 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 1 + * 2MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 24MHz, 0x8 - 26MHz, + * 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE + * - 108MHz, 0xF - 125MHz, 0x10 - 135MHz, 0x11 - 150 MHz. 0x12 to 0x1F - R + * eserved +*/ #undef SERDES_PLL_REF_SEL2_PLLREFSEL2_DEFVAL #undef SERDES_PLL_REF_SEL2_PLLREFSEL2_SHIFT #undef SERDES_PLL_REF_SEL2_PLLREFSEL2_MASK -#define SERDES_PLL_REF_SEL2_PLLREFSEL2_DEFVAL 0x0000000F -#define SERDES_PLL_REF_SEL2_PLLREFSEL2_SHIFT 0 -#define SERDES_PLL_REF_SEL2_PLLREFSEL2_MASK 0x0000001FU +#define SERDES_PLL_REF_SEL2_PLLREFSEL2_DEFVAL 0x0000000F +#define SERDES_PLL_REF_SEL2_PLLREFSEL2_SHIFT 0 +#define SERDES_PLL_REF_SEL2_PLLREFSEL2_MASK 0x0000001FU -/*PLL3 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - - 4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135 - Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved*/ +/* +* PLL3 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 1 + * 2MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 24MHz, 0x8 - 26MHz, + * 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE + * - 108MHz, 0xF - 125MHz, 0x10 - 135MHz, 0x11 - 150 MHz. 0x12 to 0x1F - R + * eserved +*/ #undef SERDES_PLL_REF_SEL3_PLLREFSEL3_DEFVAL #undef SERDES_PLL_REF_SEL3_PLLREFSEL3_SHIFT #undef SERDES_PLL_REF_SEL3_PLLREFSEL3_MASK -#define SERDES_PLL_REF_SEL3_PLLREFSEL3_DEFVAL 0x0000000E -#define SERDES_PLL_REF_SEL3_PLLREFSEL3_SHIFT 0 -#define SERDES_PLL_REF_SEL3_PLLREFSEL3_MASK 0x0000001FU +#define SERDES_PLL_REF_SEL3_PLLREFSEL3_DEFVAL 0x0000000E +#define SERDES_PLL_REF_SEL3_PLLREFSEL3_SHIFT 0 +#define SERDES_PLL_REF_SEL3_PLLREFSEL3_MASK 0x0000001FU -/*Sel of lane 0 ref clock local mux. Set to 1 to select lane 0 slicer output. Set to 0 to select lane0 ref clock mux output.*/ +/* +* Sel of lane 0 ref clock local mux. Set to 1 to select lane 0 slicer outp + * ut. Set to 0 to select lane0 ref clock mux output. +*/ #undef SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_DEFVAL #undef SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_SHIFT #undef SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_MASK -#define SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_DEFVAL 0x00000080 -#define SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_SHIFT 7 -#define SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_MASK 0x00000080U +#define SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_DEFVAL 0x00000080 +#define SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_SHIFT 7 +#define SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_MASK 0x00000080U -/*Sel of lane 1 ref clock local mux. Set to 1 to select lane 1 slicer output. Set to 0 to select lane1 ref clock mux output.*/ +/* +* Sel of lane 1 ref clock local mux. Set to 1 to select lane 1 slicer outp + * ut. Set to 0 to select lane1 ref clock mux output. +*/ #undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_DEFVAL #undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_SHIFT #undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_MASK -#define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_DEFVAL 0x00000080 -#define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_SHIFT 7 -#define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_MASK 0x00000080U +#define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_DEFVAL 0x00000080 +#define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_SHIFT 7 +#define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_MASK 0x00000080U -/*Bit 3 of lane 1 ref clock mux one hot sel. Set to 1 to select lane 3 slicer output from ref clock network*/ +/* +* Bit 3 of lane 1 ref clock mux one hot sel. Set to 1 to select lane 3 sli + * cer output from ref clock network +*/ #undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_DEFVAL #undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_SHIFT #undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_MASK -#define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_DEFVAL 0x00000080 -#define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_SHIFT 3 -#define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_MASK 0x00000008U +#define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_DEFVAL 0x00000080 +#define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_SHIFT 3 +#define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_MASK 0x00000008U -/*Sel of lane 2 ref clock local mux. Set to 1 to select lane 1 slicer output. Set to 0 to select lane2 ref clock mux output.*/ +/* +* Sel of lane 2 ref clock local mux. Set to 1 to select lane 1 slicer outp + * ut. Set to 0 to select lane2 ref clock mux output. +*/ #undef SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_DEFVAL #undef SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_SHIFT #undef SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_MASK -#define SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_DEFVAL 0x00000080 -#define SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_SHIFT 7 -#define SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_MASK 0x00000080U +#define SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_DEFVAL 0x00000080 +#define SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_SHIFT 7 +#define SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_MASK 0x00000080U -/*Sel of lane 3 ref clock local mux. Set to 1 to select lane 3 slicer output. Set to 0 to select lane3 ref clock mux output.*/ +/* +* Sel of lane 3 ref clock local mux. Set to 1 to select lane 3 slicer outp + * ut. Set to 0 to select lane3 ref clock mux output. +*/ #undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_DEFVAL #undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_SHIFT #undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_MASK -#define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_DEFVAL 0x00000080 -#define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_SHIFT 7 -#define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_MASK 0x00000080U +#define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_DEFVAL 0x00000080 +#define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_SHIFT 7 +#define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_MASK 0x00000080U -/*Bit 1 of lane 3 ref clock mux one hot sel. Set to 1 to select lane 1 slicer output from ref clock network*/ +/* +* Bit 1 of lane 3 ref clock mux one hot sel. Set to 1 to select lane 1 sli + * cer output from ref clock network +*/ #undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_DEFVAL #undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_SHIFT #undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_MASK -#define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_DEFVAL 0x00000080 -#define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_SHIFT 1 -#define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_MASK 0x00000002U +#define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_DEFVAL 0x00000080 +#define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_SHIFT 1 +#define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_MASK 0x00000002U -/*Enable/Disable coarse code satureation limiting logic*/ +/* +* Enable/Disable coarse code satureation limiting logic +*/ #undef SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_DEFVAL #undef SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_SHIFT #undef SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_MASK -#define SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_DEFVAL 0x00000000 -#define SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_SHIFT 4 -#define SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_MASK 0x00000010U +#define SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_DEFVAL 0x00000000 +#define SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_SHIFT 4 +#define SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_MASK 0x00000010U -/*Spread Spectrum No of Steps [7:0]*/ +/* +* Spread Spectrum No of Steps [7:0] +*/ #undef SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL #undef SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT #undef SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK -#define SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL 0x00000000 -#define SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT 0 -#define SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK 0x000000FFU +#define SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL 0x00000000 +#define SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT 0 +#define SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK 0x000000FFU -/*Spread Spectrum No of Steps [10:8]*/ +/* +* Spread Spectrum No of Steps [10:8] +*/ #undef SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL #undef SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT #undef SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK -#define SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL 0x00000000 -#define SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT 0 -#define SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK 0x00000007U +#define SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL 0x00000000 +#define SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT 0 +#define SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK 0x00000007U -/*Spread Spectrum No of Steps [7:0]*/ +/* +* Spread Spectrum No of Steps [7:0] +*/ #undef SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL #undef SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT #undef SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK -#define SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL 0x00000000 -#define SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT 0 -#define SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK 0x000000FFU +#define SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL 0x00000000 +#define SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT 0 +#define SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK 0x000000FFU -/*Spread Spectrum No of Steps [10:8]*/ +/* +* Spread Spectrum No of Steps [10:8] +*/ #undef SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL #undef SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT #undef SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK -#define SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL 0x00000000 -#define SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT 0 -#define SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK 0x00000007U +#define SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL 0x00000000 +#define SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT 0 +#define SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK 0x00000007U -/*Spread Spectrum No of Steps [7:0]*/ +/* +* Spread Spectrum No of Steps [7:0] +*/ #undef SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL #undef SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT #undef SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK -#define SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL 0x00000000 -#define SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT 0 -#define SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK 0x000000FFU +#define SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL 0x00000000 +#define SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT 0 +#define SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK 0x000000FFU -/*Spread Spectrum No of Steps [10:8]*/ +/* +* Spread Spectrum No of Steps [10:8] +*/ #undef SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL #undef SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT #undef SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK -#define SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL 0x00000000 -#define SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT 0 -#define SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK 0x00000007U +#define SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL 0x00000000 +#define SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT 0 +#define SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK 0x00000007U -/*Step Size for Spread Spectrum [7:0]*/ +/* +* Step Size for Spread Spectrum [7:0] +*/ #undef SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL #undef SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT #undef SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK -#define SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL 0x00000000 -#define SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT 0 -#define SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK 0x000000FFU +#define SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL 0x00000000 +#define SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT 0 +#define SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK 0x000000FFU -/*Step Size for Spread Spectrum [15:8]*/ +/* +* Step Size for Spread Spectrum [15:8] +*/ #undef SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL #undef SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT #undef SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK -#define SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL 0x00000000 -#define SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT 0 -#define SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK 0x000000FFU +#define SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL 0x00000000 +#define SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT 0 +#define SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK 0x000000FFU -/*Step Size for Spread Spectrum [23:16]*/ +/* +* Step Size for Spread Spectrum [23:16] +*/ #undef SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL #undef SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT #undef SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK -#define SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL 0x00000000 -#define SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT 0 -#define SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK 0x000000FFU +#define SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL 0x00000000 +#define SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT 0 +#define SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK 0x000000FFU -/*Step Size for Spread Spectrum [25:24]*/ +/* +* Step Size for Spread Spectrum [25:24] +*/ #undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL #undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT #undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK -#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL 0x00000000 -#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT 0 -#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK 0x00000003U +#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL 0x00000000 +#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT 0 +#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK 0x00000003U -/*Enable/Disable test mode force on SS step size*/ +/* +* Enable/Disable test mode force on SS step size +*/ #undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL #undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT #undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK -#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL 0x00000000 -#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT 4 -#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK 0x00000010U +#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL 0x00000000 +#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT 4 +#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK 0x00000010U -/*Enable/Disable test mode force on SS no of steps*/ +/* +* Enable/Disable test mode force on SS no of steps +*/ #undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL #undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT #undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK -#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL 0x00000000 -#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT 5 -#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK 0x00000020U +#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL 0x00000000 +#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT 5 +#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK 0x00000020U -/*Step Size for Spread Spectrum [7:0]*/ +/* +* Step Size for Spread Spectrum [7:0] +*/ #undef SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL #undef SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT #undef SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK -#define SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL 0x00000000 -#define SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT 0 -#define SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK 0x000000FFU +#define SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL 0x00000000 +#define SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT 0 +#define SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK 0x000000FFU -/*Step Size for Spread Spectrum [15:8]*/ +/* +* Step Size for Spread Spectrum [15:8] +*/ #undef SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL #undef SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT #undef SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK -#define SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL 0x00000000 -#define SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT 0 -#define SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK 0x000000FFU +#define SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL 0x00000000 +#define SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT 0 +#define SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK 0x000000FFU -/*Step Size for Spread Spectrum [23:16]*/ +/* +* Step Size for Spread Spectrum [23:16] +*/ #undef SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL #undef SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT #undef SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK -#define SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL 0x00000000 -#define SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT 0 -#define SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK 0x000000FFU +#define SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL 0x00000000 +#define SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT 0 +#define SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK 0x000000FFU -/*Step Size for Spread Spectrum [25:24]*/ +/* +* Step Size for Spread Spectrum [25:24] +*/ #undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL #undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT #undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK -#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL 0x00000000 -#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT 0 -#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK 0x00000003U +#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL 0x00000000 +#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT 0 +#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK 0x00000003U -/*Enable/Disable test mode force on SS step size*/ +/* +* Enable/Disable test mode force on SS step size +*/ #undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL #undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT #undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK -#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL 0x00000000 -#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT 4 -#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK 0x00000010U +#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL 0x00000000 +#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT 4 +#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK 0x00000010U -/*Enable/Disable test mode force on SS no of steps*/ +/* +* Enable/Disable test mode force on SS no of steps +*/ #undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL #undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT #undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK -#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL 0x00000000 -#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT 5 -#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK 0x00000020U +#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL 0x00000000 +#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT 5 +#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK 0x00000020U -/*Step Size for Spread Spectrum [7:0]*/ +/* +* Step Size for Spread Spectrum [7:0] +*/ #undef SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL #undef SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT #undef SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK -#define SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL 0x00000000 -#define SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT 0 -#define SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK 0x000000FFU +#define SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL 0x00000000 +#define SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT 0 +#define SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK 0x000000FFU -/*Step Size for Spread Spectrum [15:8]*/ +/* +* Step Size for Spread Spectrum [15:8] +*/ #undef SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL #undef SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT #undef SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK -#define SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL 0x00000000 -#define SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT 0 -#define SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK 0x000000FFU +#define SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL 0x00000000 +#define SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT 0 +#define SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK 0x000000FFU -/*Step Size for Spread Spectrum [23:16]*/ +/* +* Step Size for Spread Spectrum [23:16] +*/ #undef SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL #undef SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT #undef SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK -#define SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL 0x00000000 -#define SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT 0 -#define SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK 0x000000FFU +#define SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL 0x00000000 +#define SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT 0 +#define SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK 0x000000FFU -/*Step Size for Spread Spectrum [25:24]*/ +/* +* Step Size for Spread Spectrum [25:24] +*/ #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK -#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL 0x00000000 -#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT 0 -#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK 0x00000003U +#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL 0x00000000 +#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT 0 +#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK 0x00000003U -/*Enable/Disable test mode force on SS step size*/ +/* +* Enable/Disable test mode force on SS step size +*/ #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK -#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL 0x00000000 -#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT 4 -#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK 0x00000010U +#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL 0x00000000 +#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT 4 +#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK 0x00000010U -/*Enable/Disable test mode force on SS no of steps*/ +/* +* Enable/Disable test mode force on SS no of steps +*/ #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK -#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL 0x00000000 -#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT 5 -#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK 0x00000020U +#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL 0x00000000 +#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT 5 +#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK 0x00000020U -/*Enable test mode forcing on enable Spread Spectrum*/ +/* +* Enable test mode forcing on enable Spread Spectrum +*/ #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_DEFVAL #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_SHIFT #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_MASK -#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_DEFVAL 0x00000000 -#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_SHIFT 7 -#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_MASK 0x00000080U +#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_DEFVAL 0x00000000 +#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_SHIFT 7 +#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_MASK 0x00000080U -/*Bypass Descrambler*/ +/* +* Bypass Descrambler +*/ #undef SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_DEFVAL #undef SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_SHIFT #undef SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_MASK -#define SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_DEFVAL 0x00000000 -#define SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_SHIFT 1 -#define SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_MASK 0x00000002U +#define SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_DEFVAL 0x00000000 +#define SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_SHIFT 1 +#define SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_MASK 0x00000002U -/*Enable Bypass for <1> TM_DIG_CTRL_6*/ +/* +* Enable Bypass for <1> TM_DIG_CTRL_6 +*/ #undef SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_DEFVAL #undef SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_SHIFT #undef SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_MASK -#define SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_DEFVAL 0x00000000 -#define SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_SHIFT 0 -#define SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_MASK 0x00000001U +#define SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_DEFVAL 0x00000000 +#define SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_SHIFT 0 +#define SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_MASK 0x00000001U -/*Bypass scrambler signal*/ +/* +* Bypass scrambler signal +*/ #undef SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_DEFVAL #undef SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_SHIFT #undef SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_MASK -#define SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_DEFVAL 0x00000000 -#define SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_SHIFT 1 -#define SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_MASK 0x00000002U +#define SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_DEFVAL 0x00000000 +#define SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_SHIFT 1 +#define SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_MASK 0x00000002U -/*Enable/disable scrambler bypass signal*/ +/* +* Enable/disable scrambler bypass signal +*/ #undef SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_DEFVAL #undef SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_SHIFT #undef SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_MASK -#define SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_DEFVAL 0x00000000 -#define SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_SHIFT 0 -#define SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_MASK 0x00000001U +#define SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_DEFVAL 0x00000000 +#define SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_SHIFT 0 +#define SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_MASK 0x00000001U -/*Enable test mode force on fractional mode enable*/ +/* +* Enable test mode force on fractional mode enable +*/ #undef SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_DEFVAL #undef SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_SHIFT #undef SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_MASK -#define SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_DEFVAL 0x00000000 -#define SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_SHIFT 6 -#define SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_MASK 0x00000040U +#define SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_DEFVAL 0x00000000 +#define SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_SHIFT 6 +#define SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_MASK 0x00000040U -/*Bypass 8b10b decoder*/ +/* +* Bypass 8b10b decoder +*/ #undef SERDES_L3_TM_DIG_6_BYPASS_DECODER_DEFVAL #undef SERDES_L3_TM_DIG_6_BYPASS_DECODER_SHIFT #undef SERDES_L3_TM_DIG_6_BYPASS_DECODER_MASK -#define SERDES_L3_TM_DIG_6_BYPASS_DECODER_DEFVAL 0x00000000 -#define SERDES_L3_TM_DIG_6_BYPASS_DECODER_SHIFT 3 -#define SERDES_L3_TM_DIG_6_BYPASS_DECODER_MASK 0x00000008U +#define SERDES_L3_TM_DIG_6_BYPASS_DECODER_DEFVAL 0x00000000 +#define SERDES_L3_TM_DIG_6_BYPASS_DECODER_SHIFT 3 +#define SERDES_L3_TM_DIG_6_BYPASS_DECODER_MASK 0x00000008U -/*Enable Bypass for <3> TM_DIG_CTRL_6*/ +/* +* Enable Bypass for <3> TM_DIG_CTRL_6 +*/ #undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_DEFVAL #undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_SHIFT #undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_MASK -#define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_DEFVAL 0x00000000 -#define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_SHIFT 2 -#define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_MASK 0x00000004U +#define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_DEFVAL 0x00000000 +#define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_SHIFT 2 +#define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_MASK 0x00000004U -/*Bypass Descrambler*/ +/* +* Bypass Descrambler +*/ #undef SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_DEFVAL #undef SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_SHIFT #undef SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_MASK -#define SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_DEFVAL 0x00000000 -#define SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_SHIFT 1 -#define SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_MASK 0x00000002U +#define SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_DEFVAL 0x00000000 +#define SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_SHIFT 1 +#define SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_MASK 0x00000002U -/*Enable Bypass for <1> TM_DIG_CTRL_6*/ +/* +* Enable Bypass for <1> TM_DIG_CTRL_6 +*/ #undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_DEFVAL #undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_SHIFT #undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_MASK -#define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_DEFVAL 0x00000000 -#define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_SHIFT 0 -#define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_MASK 0x00000001U +#define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_DEFVAL 0x00000000 +#define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_SHIFT 0 +#define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_MASK 0x00000001U -/*Enable/disable encoder bypass signal*/ +/* +* Enable/disable encoder bypass signal +*/ #undef SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_DEFVAL #undef SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_SHIFT #undef SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_MASK -#define SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_DEFVAL 0x00000000 -#define SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_SHIFT 3 -#define SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_MASK 0x00000008U +#define SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_DEFVAL 0x00000000 +#define SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_SHIFT 3 +#define SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_MASK 0x00000008U -/*Bypass scrambler signal*/ +/* +* Bypass scrambler signal +*/ #undef SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_DEFVAL #undef SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_SHIFT #undef SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_MASK -#define SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_DEFVAL 0x00000000 -#define SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_SHIFT 1 -#define SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_MASK 0x00000002U +#define SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_DEFVAL 0x00000000 +#define SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_SHIFT 1 +#define SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_MASK 0x00000002U -/*Enable/disable scrambler bypass signal*/ +/* +* Enable/disable scrambler bypass signal +*/ #undef SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_DEFVAL #undef SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_SHIFT #undef SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_MASK -#define SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_DEFVAL 0x00000000 -#define SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_SHIFT 0 -#define SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_MASK 0x00000001U +#define SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_DEFVAL 0x00000000 +#define SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_SHIFT 0 +#define SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_MASK 0x00000001U -/*PHY Mode: 4'b000 - PCIe, 4'b001 - USB3, 4'b0010 - SATA, 4'b0100 - SGMII, 4'b0101 - DP, 4'b1000 - MPHY*/ -#undef SERDES_L3_TXPMA_ST_0_TX_PHY_MODE_DEFVAL -#undef SERDES_L3_TXPMA_ST_0_TX_PHY_MODE_SHIFT -#undef SERDES_L3_TXPMA_ST_0_TX_PHY_MODE_MASK -#define SERDES_L3_TXPMA_ST_0_TX_PHY_MODE_DEFVAL 0x00000001 -#define SERDES_L3_TXPMA_ST_0_TX_PHY_MODE_SHIFT 4 -#define SERDES_L3_TXPMA_ST_0_TX_PHY_MODE_MASK 0x000000F0U - -/*Spare- not used*/ +/* +* Spare- not used +*/ #undef SERDES_L0_TM_AUX_0_BIT_2_DEFVAL #undef SERDES_L0_TM_AUX_0_BIT_2_SHIFT #undef SERDES_L0_TM_AUX_0_BIT_2_MASK -#define SERDES_L0_TM_AUX_0_BIT_2_DEFVAL 0x00000000 -#define SERDES_L0_TM_AUX_0_BIT_2_SHIFT 5 -#define SERDES_L0_TM_AUX_0_BIT_2_MASK 0x00000020U +#define SERDES_L0_TM_AUX_0_BIT_2_DEFVAL 0x00000000 +#define SERDES_L0_TM_AUX_0_BIT_2_SHIFT 5 +#define SERDES_L0_TM_AUX_0_BIT_2_MASK 0x00000020U -/*Spare- not used*/ +/* +* Spare- not used +*/ #undef SERDES_L2_TM_AUX_0_BIT_2_DEFVAL #undef SERDES_L2_TM_AUX_0_BIT_2_SHIFT #undef SERDES_L2_TM_AUX_0_BIT_2_MASK -#define SERDES_L2_TM_AUX_0_BIT_2_DEFVAL 0x00000000 -#define SERDES_L2_TM_AUX_0_BIT_2_SHIFT 5 -#define SERDES_L2_TM_AUX_0_BIT_2_MASK 0x00000020U +#define SERDES_L2_TM_AUX_0_BIT_2_DEFVAL 0x00000000 +#define SERDES_L2_TM_AUX_0_BIT_2_SHIFT 5 +#define SERDES_L2_TM_AUX_0_BIT_2_MASK 0x00000020U -/*Enable Eye Surf*/ +/* +* Enable Eye Surf +*/ #undef SERDES_L0_TM_DIG_8_EYESURF_ENABLE_DEFVAL #undef SERDES_L0_TM_DIG_8_EYESURF_ENABLE_SHIFT #undef SERDES_L0_TM_DIG_8_EYESURF_ENABLE_MASK -#define SERDES_L0_TM_DIG_8_EYESURF_ENABLE_DEFVAL 0x00000000 -#define SERDES_L0_TM_DIG_8_EYESURF_ENABLE_SHIFT 4 -#define SERDES_L0_TM_DIG_8_EYESURF_ENABLE_MASK 0x00000010U +#define SERDES_L0_TM_DIG_8_EYESURF_ENABLE_DEFVAL 0x00000000 +#define SERDES_L0_TM_DIG_8_EYESURF_ENABLE_SHIFT 4 +#define SERDES_L0_TM_DIG_8_EYESURF_ENABLE_MASK 0x00000010U -/*Enable Eye Surf*/ +/* +* Enable Eye Surf +*/ #undef SERDES_L1_TM_DIG_8_EYESURF_ENABLE_DEFVAL #undef SERDES_L1_TM_DIG_8_EYESURF_ENABLE_SHIFT #undef SERDES_L1_TM_DIG_8_EYESURF_ENABLE_MASK -#define SERDES_L1_TM_DIG_8_EYESURF_ENABLE_DEFVAL 0x00000000 -#define SERDES_L1_TM_DIG_8_EYESURF_ENABLE_SHIFT 4 -#define SERDES_L1_TM_DIG_8_EYESURF_ENABLE_MASK 0x00000010U +#define SERDES_L1_TM_DIG_8_EYESURF_ENABLE_DEFVAL 0x00000000 +#define SERDES_L1_TM_DIG_8_EYESURF_ENABLE_SHIFT 4 +#define SERDES_L1_TM_DIG_8_EYESURF_ENABLE_MASK 0x00000010U -/*Enable Eye Surf*/ +/* +* Enable Eye Surf +*/ #undef SERDES_L2_TM_DIG_8_EYESURF_ENABLE_DEFVAL #undef SERDES_L2_TM_DIG_8_EYESURF_ENABLE_SHIFT #undef SERDES_L2_TM_DIG_8_EYESURF_ENABLE_MASK -#define SERDES_L2_TM_DIG_8_EYESURF_ENABLE_DEFVAL 0x00000000 -#define SERDES_L2_TM_DIG_8_EYESURF_ENABLE_SHIFT 4 -#define SERDES_L2_TM_DIG_8_EYESURF_ENABLE_MASK 0x00000010U +#define SERDES_L2_TM_DIG_8_EYESURF_ENABLE_DEFVAL 0x00000000 +#define SERDES_L2_TM_DIG_8_EYESURF_ENABLE_SHIFT 4 +#define SERDES_L2_TM_DIG_8_EYESURF_ENABLE_MASK 0x00000010U -/*Enable Eye Surf*/ +/* +* Enable Eye Surf +*/ #undef SERDES_L3_TM_DIG_8_EYESURF_ENABLE_DEFVAL #undef SERDES_L3_TM_DIG_8_EYESURF_ENABLE_SHIFT #undef SERDES_L3_TM_DIG_8_EYESURF_ENABLE_MASK -#define SERDES_L3_TM_DIG_8_EYESURF_ENABLE_DEFVAL 0x00000000 -#define SERDES_L3_TM_DIG_8_EYESURF_ENABLE_SHIFT 4 -#define SERDES_L3_TM_DIG_8_EYESURF_ENABLE_MASK 0x00000010U +#define SERDES_L3_TM_DIG_8_EYESURF_ENABLE_DEFVAL 0x00000000 +#define SERDES_L3_TM_DIG_8_EYESURF_ENABLE_SHIFT 4 +#define SERDES_L3_TM_DIG_8_EYESURF_ENABLE_MASK 0x00000010U -/*ILL calib counts BYPASSED with calcode bits*/ +/* +* ILL calib counts BYPASSED with calcode bits +*/ #undef SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL #undef SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT #undef SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK -#define SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL 0x00000000 -#define SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT 7 -#define SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK 0x00000080U +#define SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL 0x00000000 +#define SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT 7 +#define SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK 0x00000080U -/*IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS*/ +/* +* IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , + * USB3 : SS +*/ #undef SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL #undef SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT #undef SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK -#define SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL 0x00000000 -#define SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT 0 -#define SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK 0x000000FFU +#define SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL 0x00000000 +#define SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT 0 +#define SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK 0x000000FFU -/*IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2*/ +/* +* IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 +*/ #undef SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL #undef SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT #undef SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK -#define SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL 0x00000000 -#define SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT 0 -#define SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK 0x000000FFU +#define SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL 0x00000000 +#define SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT 0 +#define SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK 0x000000FFU -/*G1A pll ctr bypass value*/ +/* +* G1A pll ctr bypass value +*/ #undef SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL #undef SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT #undef SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK -#define SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL 0x00000000 -#define SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT 0 -#define SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK 0x000000FFU +#define SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL 0x00000000 +#define SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT 0 +#define SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK 0x000000FFU -/*E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS*/ +/* +* E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , U + * SB3 : SS +*/ #undef SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL #undef SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT #undef SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK -#define SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL 0x00000000 -#define SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT 0 -#define SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK 0x000000FFU +#define SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL 0x00000000 +#define SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT 0 +#define SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK 0x000000FFU -/*E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2*/ +/* +* E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 +*/ #undef SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL #undef SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT #undef SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK -#define SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL 0x00000000 -#define SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT 0 -#define SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK 0x000000FFU +#define SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL 0x00000000 +#define SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT 0 +#define SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK 0x000000FFU -/*IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3*/ +/* +* IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 +*/ #undef SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL #undef SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT #undef SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK -#define SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL 0x00000000 -#define SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT 0 -#define SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK 0x000000FFU +#define SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL 0x00000000 +#define SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT 0 +#define SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK 0x000000FFU -/*E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3*/ +/* +* E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 +*/ #undef SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL #undef SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT #undef SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK -#define SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL 0x00000000 -#define SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT 0 -#define SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK 0x000000FFU +#define SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL 0x00000000 +#define SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT 0 +#define SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK 0x000000FFU -/*ILL calibration code change wait time*/ +/* +* ILL calibration code change wait time +*/ #undef SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL #undef SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT #undef SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_MASK -#define SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL 0x00000002 -#define SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT 0 -#define SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_MASK 0x000000FFU +#define SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL 0x00000002 +#define SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT 0 +#define SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_MASK 0x000000FFU -/*IQ ILL polytrim bypass value*/ +/* +* IQ ILL polytrim bypass value +*/ #undef SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL #undef SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT #undef SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK -#define SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL 0x00000000 -#define SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT 0 -#define SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK 0x000000FFU +#define SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL 0x00000000 +#define SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT 0 +#define SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK 0x000000FFU -/*bypass IQ polytrim*/ +/* +* bypass IQ polytrim +*/ #undef SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL #undef SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT #undef SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK -#define SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL 0x00000000 -#define SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT 0 -#define SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK 0x00000001U +#define SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL 0x00000000 +#define SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT 0 +#define SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK 0x00000001U -/*E ILL polytrim bypass value*/ +/* +* E ILL polytrim bypass value +*/ #undef SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL #undef SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT #undef SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK -#define SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL 0x00000000 -#define SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT 0 -#define SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK 0x000000FFU +#define SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL 0x00000000 +#define SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT 0 +#define SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK 0x000000FFU -/*bypass E polytrim*/ +/* +* bypass E polytrim +*/ #undef SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL #undef SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT #undef SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK -#define SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL 0x00000000 -#define SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT 0 -#define SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK 0x00000001U +#define SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL 0x00000000 +#define SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT 0 +#define SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK 0x00000001U -/*ILL calib counts BYPASSED with calcode bits*/ +/* +* ILL cal idle val refcnt +*/ +#undef SERDES_L0_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_DEFVAL +#undef SERDES_L0_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_SHIFT +#undef SERDES_L0_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_MASK +#define SERDES_L0_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_DEFVAL 0x00000001 +#define SERDES_L0_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_SHIFT 0 +#define SERDES_L0_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_MASK 0x00000007U + +/* +* ILL cal idle val refcnt +*/ +#undef SERDES_L1_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_DEFVAL +#undef SERDES_L1_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_SHIFT +#undef SERDES_L1_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_MASK +#define SERDES_L1_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_DEFVAL 0x00000001 +#define SERDES_L1_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_SHIFT 0 +#define SERDES_L1_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_MASK 0x00000007U + +/* +* ILL calib counts BYPASSED with calcode bits +*/ #undef SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL #undef SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT #undef SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK -#define SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL 0x00000000 -#define SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT 7 -#define SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK 0x00000080U +#define SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL 0x00000000 +#define SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT 7 +#define SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK 0x00000080U -/*IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS*/ +/* +* IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , + * USB3 : SS +*/ #undef SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL #undef SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT #undef SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK -#define SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL 0x00000000 -#define SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT 0 -#define SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK 0x000000FFU +#define SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL 0x00000000 +#define SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT 0 +#define SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK 0x000000FFU -/*IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2*/ +/* +* IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 +*/ #undef SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL #undef SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT #undef SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK -#define SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL 0x00000000 -#define SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT 0 -#define SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK 0x000000FFU +#define SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL 0x00000000 +#define SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT 0 +#define SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK 0x000000FFU -/*G1A pll ctr bypass value*/ +/* +* G1A pll ctr bypass value +*/ #undef SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL #undef SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT #undef SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK -#define SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL 0x00000000 -#define SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT 0 -#define SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK 0x000000FFU +#define SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL 0x00000000 +#define SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT 0 +#define SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK 0x000000FFU -/*E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS*/ +/* +* E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , U + * SB3 : SS +*/ #undef SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL #undef SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT #undef SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK -#define SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL 0x00000000 -#define SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT 0 -#define SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK 0x000000FFU +#define SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL 0x00000000 +#define SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT 0 +#define SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK 0x000000FFU -/*E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2*/ +/* +* E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 +*/ #undef SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL #undef SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT #undef SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK -#define SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL 0x00000000 -#define SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT 0 -#define SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK 0x000000FFU +#define SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL 0x00000000 +#define SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT 0 +#define SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK 0x000000FFU -/*IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3*/ +/* +* IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 +*/ #undef SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL #undef SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT #undef SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK -#define SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL 0x00000000 -#define SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT 0 -#define SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK 0x000000FFU +#define SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL 0x00000000 +#define SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT 0 +#define SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK 0x000000FFU -/*E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3*/ +/* +* E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 +*/ #undef SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL #undef SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT #undef SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK -#define SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL 0x00000000 -#define SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT 0 -#define SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK 0x000000FFU +#define SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL 0x00000000 +#define SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT 0 +#define SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK 0x000000FFU -/*ILL calibration code change wait time*/ +/* +* ILL calibration code change wait time +*/ #undef SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL #undef SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT #undef SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_MASK -#define SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL 0x00000002 -#define SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT 0 -#define SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_MASK 0x000000FFU +#define SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL 0x00000002 +#define SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT 0 +#define SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_MASK 0x000000FFU -/*IQ ILL polytrim bypass value*/ +/* +* IQ ILL polytrim bypass value +*/ #undef SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL #undef SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT #undef SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK -#define SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL 0x00000000 -#define SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT 0 -#define SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK 0x000000FFU +#define SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL 0x00000000 +#define SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT 0 +#define SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK 0x000000FFU -/*bypass IQ polytrim*/ +/* +* bypass IQ polytrim +*/ #undef SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL #undef SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT #undef SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK -#define SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL 0x00000000 -#define SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT 0 -#define SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK 0x00000001U +#define SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL 0x00000000 +#define SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT 0 +#define SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK 0x00000001U -/*E ILL polytrim bypass value*/ +/* +* E ILL polytrim bypass value +*/ #undef SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL #undef SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT #undef SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK -#define SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL 0x00000000 -#define SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT 0 -#define SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK 0x000000FFU +#define SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL 0x00000000 +#define SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT 0 +#define SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK 0x000000FFU -/*bypass E polytrim*/ +/* +* bypass E polytrim +*/ #undef SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL #undef SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT #undef SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK -#define SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL 0x00000000 -#define SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT 0 -#define SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK 0x00000001U +#define SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL 0x00000000 +#define SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT 0 +#define SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK 0x00000001U -/*ILL calib counts BYPASSED with calcode bits*/ +/* +* ILL cal idle val refcnt +*/ +#undef SERDES_L2_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_DEFVAL +#undef SERDES_L2_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_SHIFT +#undef SERDES_L2_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_MASK +#define SERDES_L2_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_DEFVAL 0x00000001 +#define SERDES_L2_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_SHIFT 0 +#define SERDES_L2_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_MASK 0x00000007U + +/* +* ILL calib counts BYPASSED with calcode bits +*/ #undef SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL #undef SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT #undef SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK -#define SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL 0x00000000 -#define SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT 7 -#define SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK 0x00000080U +#define SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL 0x00000000 +#define SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT 7 +#define SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK 0x00000080U -/*IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS*/ +/* +* IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , + * USB3 : SS +*/ #undef SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL #undef SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT #undef SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK -#define SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL 0x00000000 -#define SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT 0 -#define SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK 0x000000FFU +#define SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL 0x00000000 +#define SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT 0 +#define SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK 0x000000FFU -/*IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2*/ +/* +* IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 +*/ #undef SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL #undef SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT #undef SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK -#define SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL 0x00000000 -#define SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT 0 -#define SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK 0x000000FFU +#define SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL 0x00000000 +#define SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT 0 +#define SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK 0x000000FFU -/*G1A pll ctr bypass value*/ +/* +* G1A pll ctr bypass value +*/ #undef SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL #undef SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT #undef SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK -#define SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL 0x00000000 -#define SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT 0 -#define SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK 0x000000FFU +#define SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL 0x00000000 +#define SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT 0 +#define SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK 0x000000FFU -/*E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS*/ +/* +* E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , U + * SB3 : SS +*/ #undef SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL #undef SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT #undef SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK -#define SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL 0x00000000 -#define SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT 0 -#define SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK 0x000000FFU +#define SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL 0x00000000 +#define SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT 0 +#define SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK 0x000000FFU -/*E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2*/ +/* +* E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 +*/ #undef SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL #undef SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT #undef SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK -#define SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL 0x00000000 -#define SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT 0 -#define SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK 0x000000FFU +#define SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL 0x00000000 +#define SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT 0 +#define SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK 0x000000FFU -/*G2A_PCIe1 PLL ctr bypass value*/ +/* +* G2A_PCIe1 PLL ctr bypass value +*/ #undef SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_DEFVAL #undef SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_SHIFT #undef SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_MASK -#define SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_DEFVAL 0x00000000 -#define SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_SHIFT 4 -#define SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_MASK 0x000000F0U +#define SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_DEFVAL 0x00000000 +#define SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_SHIFT 4 +#define SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_MASK 0x000000F0U -/*IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3*/ +/* +* IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 +*/ #undef SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL #undef SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT #undef SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK -#define SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL 0x00000000 -#define SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT 0 -#define SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK 0x000000FFU +#define SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL 0x00000000 +#define SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT 0 +#define SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK 0x000000FFU -/*E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3*/ +/* +* E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 +*/ #undef SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL #undef SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT #undef SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK -#define SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL 0x00000000 -#define SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT 0 -#define SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK 0x000000FFU +#define SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL 0x00000000 +#define SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT 0 +#define SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK 0x000000FFU -/*ILL calibration code change wait time*/ +/* +* ILL calibration code change wait time +*/ #undef SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL #undef SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT #undef SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_MASK -#define SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL 0x00000002 -#define SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT 0 -#define SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_MASK 0x000000FFU +#define SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL 0x00000002 +#define SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT 0 +#define SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_MASK 0x000000FFU -/*IQ ILL polytrim bypass value*/ +/* +* IQ ILL polytrim bypass value +*/ #undef SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL #undef SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT #undef SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK -#define SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL 0x00000000 -#define SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT 0 -#define SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK 0x000000FFU +#define SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL 0x00000000 +#define SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT 0 +#define SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK 0x000000FFU -/*bypass IQ polytrim*/ +/* +* bypass IQ polytrim +*/ #undef SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL #undef SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT #undef SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK -#define SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL 0x00000000 -#define SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT 0 -#define SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK 0x00000001U +#define SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL 0x00000000 +#define SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT 0 +#define SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK 0x00000001U -/*E ILL polytrim bypass value*/ +/* +* E ILL polytrim bypass value +*/ #undef SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL #undef SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT #undef SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK -#define SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL 0x00000000 -#define SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT 0 -#define SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK 0x000000FFU +#define SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL 0x00000000 +#define SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT 0 +#define SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK 0x000000FFU -/*bypass E polytrim*/ +/* +* bypass E polytrim +*/ #undef SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL #undef SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT #undef SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK -#define SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL 0x00000000 -#define SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT 0 -#define SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK 0x00000001U +#define SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL 0x00000000 +#define SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT 0 +#define SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK 0x00000001U -/*pre lock comma count threshold. 2'b 00 : 3, 2'b 01 : 5, 2'b 10 : 10, 2'b 11 : 20*/ -#undef SERDES_L0_TM_DIG_21_COMMA_PRE_LOCK_THRESH_DEFVAL -#undef SERDES_L0_TM_DIG_21_COMMA_PRE_LOCK_THRESH_SHIFT -#undef SERDES_L0_TM_DIG_21_COMMA_PRE_LOCK_THRESH_MASK -#define SERDES_L0_TM_DIG_21_COMMA_PRE_LOCK_THRESH_DEFVAL 0x00000000 -#define SERDES_L0_TM_DIG_21_COMMA_PRE_LOCK_THRESH_SHIFT 0 -#define SERDES_L0_TM_DIG_21_COMMA_PRE_LOCK_THRESH_MASK 0x00000003U +/* +* ILL cal idle val refcnt +*/ +#undef SERDES_L3_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_DEFVAL +#undef SERDES_L3_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_SHIFT +#undef SERDES_L3_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_MASK +#define SERDES_L3_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_DEFVAL 0x00000001 +#define SERDES_L3_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_SHIFT 0 +#define SERDES_L3_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_MASK 0x00000007U -/*CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001*/ +/* +* CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001 +*/ #undef SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL #undef SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT #undef SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK -#define SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL 0x00000001 -#define SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT 0 -#define SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK 0x0000000FU +#define SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL 0x00000001 +#define SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT 0 +#define SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK 0x0000000FU -/*Delay apb reset by specified amount*/ +/* +* CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001 +*/ +#undef SERDES_L1_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL +#undef SERDES_L1_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT +#undef SERDES_L1_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK +#define SERDES_L1_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL 0x00000001 +#define SERDES_L1_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT 0 +#define SERDES_L1_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK 0x0000000FU + +/* +* CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001 +*/ +#undef SERDES_L2_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL +#undef SERDES_L2_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT +#undef SERDES_L2_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK +#define SERDES_L2_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL 0x00000001 +#define SERDES_L2_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT 0 +#define SERDES_L2_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK 0x0000000FU + +/* +* CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001 +*/ +#undef SERDES_L3_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL +#undef SERDES_L3_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT +#undef SERDES_L3_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK +#define SERDES_L3_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL 0x00000001 +#define SERDES_L3_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT 0 +#define SERDES_L3_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK 0x0000000FU + +/* +* Delay apb reset by specified amount +*/ #undef SERDES_L0_TM_RST_DLY_APB_RST_DLY_DEFVAL #undef SERDES_L0_TM_RST_DLY_APB_RST_DLY_SHIFT #undef SERDES_L0_TM_RST_DLY_APB_RST_DLY_MASK -#define SERDES_L0_TM_RST_DLY_APB_RST_DLY_DEFVAL 0x00000000 -#define SERDES_L0_TM_RST_DLY_APB_RST_DLY_SHIFT 0 -#define SERDES_L0_TM_RST_DLY_APB_RST_DLY_MASK 0x000000FFU +#define SERDES_L0_TM_RST_DLY_APB_RST_DLY_DEFVAL 0x00000000 +#define SERDES_L0_TM_RST_DLY_APB_RST_DLY_SHIFT 0 +#define SERDES_L0_TM_RST_DLY_APB_RST_DLY_MASK 0x000000FFU -/*Enable Bypass for <7> of TM_ANA_BYPS_15*/ +/* +* Enable Bypass for <7> of TM_ANA_BYPS_15 +*/ #undef SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL #undef SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT #undef SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK -#define SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL 0x00000000 -#define SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT 6 -#define SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK 0x00000040U +#define SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL 0x00000000 +#define SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT 6 +#define SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK 0x00000040U -/*Enable Bypass for <7> of TM_ANA_BYPS_12*/ +/* +* Enable Bypass for <7> of TM_ANA_BYPS_12 +*/ #undef SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL #undef SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT #undef SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK -#define SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL 0x00000000 -#define SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT 6 -#define SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK 0x00000040U +#define SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL 0x00000000 +#define SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT 6 +#define SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK 0x00000040U -/*Delay apb reset by specified amount*/ +/* +* Delay apb reset by specified amount +*/ #undef SERDES_L1_TM_RST_DLY_APB_RST_DLY_DEFVAL #undef SERDES_L1_TM_RST_DLY_APB_RST_DLY_SHIFT #undef SERDES_L1_TM_RST_DLY_APB_RST_DLY_MASK -#define SERDES_L1_TM_RST_DLY_APB_RST_DLY_DEFVAL 0x00000000 -#define SERDES_L1_TM_RST_DLY_APB_RST_DLY_SHIFT 0 -#define SERDES_L1_TM_RST_DLY_APB_RST_DLY_MASK 0x000000FFU +#define SERDES_L1_TM_RST_DLY_APB_RST_DLY_DEFVAL 0x00000000 +#define SERDES_L1_TM_RST_DLY_APB_RST_DLY_SHIFT 0 +#define SERDES_L1_TM_RST_DLY_APB_RST_DLY_MASK 0x000000FFU -/*Enable Bypass for <7> of TM_ANA_BYPS_15*/ +/* +* Enable Bypass for <7> of TM_ANA_BYPS_15 +*/ #undef SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL #undef SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT #undef SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK -#define SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL 0x00000000 -#define SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT 6 -#define SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK 0x00000040U +#define SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL 0x00000000 +#define SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT 6 +#define SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK 0x00000040U -/*Enable Bypass for <7> of TM_ANA_BYPS_12*/ +/* +* Enable Bypass for <7> of TM_ANA_BYPS_12 +*/ #undef SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL #undef SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT #undef SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK -#define SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL 0x00000000 -#define SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT 6 -#define SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK 0x00000040U +#define SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL 0x00000000 +#define SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT 6 +#define SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK 0x00000040U -/*Delay apb reset by specified amount*/ +/* +* Delay apb reset by specified amount +*/ #undef SERDES_L2_TM_RST_DLY_APB_RST_DLY_DEFVAL #undef SERDES_L2_TM_RST_DLY_APB_RST_DLY_SHIFT #undef SERDES_L2_TM_RST_DLY_APB_RST_DLY_MASK -#define SERDES_L2_TM_RST_DLY_APB_RST_DLY_DEFVAL 0x00000000 -#define SERDES_L2_TM_RST_DLY_APB_RST_DLY_SHIFT 0 -#define SERDES_L2_TM_RST_DLY_APB_RST_DLY_MASK 0x000000FFU +#define SERDES_L2_TM_RST_DLY_APB_RST_DLY_DEFVAL 0x00000000 +#define SERDES_L2_TM_RST_DLY_APB_RST_DLY_SHIFT 0 +#define SERDES_L2_TM_RST_DLY_APB_RST_DLY_MASK 0x000000FFU -/*Enable Bypass for <7> of TM_ANA_BYPS_15*/ +/* +* Enable Bypass for <7> of TM_ANA_BYPS_15 +*/ #undef SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL #undef SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT #undef SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK -#define SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL 0x00000000 -#define SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT 6 -#define SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK 0x00000040U +#define SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL 0x00000000 +#define SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT 6 +#define SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK 0x00000040U -/*Enable Bypass for <7> of TM_ANA_BYPS_12*/ +/* +* Enable Bypass for <7> of TM_ANA_BYPS_12 +*/ #undef SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL #undef SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT #undef SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK -#define SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL 0x00000000 -#define SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT 6 -#define SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK 0x00000040U +#define SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL 0x00000000 +#define SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT 6 +#define SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK 0x00000040U -/*Delay apb reset by specified amount*/ +/* +* Delay apb reset by specified amount +*/ #undef SERDES_L3_TM_RST_DLY_APB_RST_DLY_DEFVAL #undef SERDES_L3_TM_RST_DLY_APB_RST_DLY_SHIFT #undef SERDES_L3_TM_RST_DLY_APB_RST_DLY_MASK -#define SERDES_L3_TM_RST_DLY_APB_RST_DLY_DEFVAL 0x00000000 -#define SERDES_L3_TM_RST_DLY_APB_RST_DLY_SHIFT 0 -#define SERDES_L3_TM_RST_DLY_APB_RST_DLY_MASK 0x000000FFU +#define SERDES_L3_TM_RST_DLY_APB_RST_DLY_DEFVAL 0x00000000 +#define SERDES_L3_TM_RST_DLY_APB_RST_DLY_SHIFT 0 +#define SERDES_L3_TM_RST_DLY_APB_RST_DLY_MASK 0x000000FFU -/*Enable Bypass for <7> of TM_ANA_BYPS_15*/ +/* +* Enable Bypass for <7> of TM_ANA_BYPS_15 +*/ #undef SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL #undef SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT #undef SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK -#define SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL 0x00000000 -#define SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT 6 -#define SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK 0x00000040U +#define SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL 0x00000000 +#define SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT 6 +#define SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK 0x00000040U -/*Enable Bypass for <7> of TM_ANA_BYPS_12*/ +/* +* Enable Bypass for <7> of TM_ANA_BYPS_12 +*/ #undef SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL #undef SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT #undef SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK -#define SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL 0x00000000 -#define SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT 6 -#define SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK 0x00000040U +#define SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL 0x00000000 +#define SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT 6 +#define SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK 0x00000040U -/*Controls UPHY Lane 0 protocol configuration. 0 - PowerDown, 1 - PCIe .0, 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII0, 6 - Unuse - , 7 - Unused*/ +/* +* CDR fast phase lock control +*/ +#undef SERDES_L0_TM_MISC3_CDR_EN_FPL_DEFVAL +#undef SERDES_L0_TM_MISC3_CDR_EN_FPL_SHIFT +#undef SERDES_L0_TM_MISC3_CDR_EN_FPL_MASK +#define SERDES_L0_TM_MISC3_CDR_EN_FPL_DEFVAL 0x00000003 +#define SERDES_L0_TM_MISC3_CDR_EN_FPL_SHIFT 1 +#define SERDES_L0_TM_MISC3_CDR_EN_FPL_MASK 0x00000002U + +/* +* CDR fast frequency lock control +*/ +#undef SERDES_L0_TM_MISC3_CDR_EN_FFL_DEFVAL +#undef SERDES_L0_TM_MISC3_CDR_EN_FFL_SHIFT +#undef SERDES_L0_TM_MISC3_CDR_EN_FFL_MASK +#define SERDES_L0_TM_MISC3_CDR_EN_FFL_DEFVAL 0x00000003 +#define SERDES_L0_TM_MISC3_CDR_EN_FFL_SHIFT 0 +#define SERDES_L0_TM_MISC3_CDR_EN_FFL_MASK 0x00000001U + +/* +* CDR fast phase lock control +*/ +#undef SERDES_L1_TM_MISC3_CDR_EN_FPL_DEFVAL +#undef SERDES_L1_TM_MISC3_CDR_EN_FPL_SHIFT +#undef SERDES_L1_TM_MISC3_CDR_EN_FPL_MASK +#define SERDES_L1_TM_MISC3_CDR_EN_FPL_DEFVAL 0x00000003 +#define SERDES_L1_TM_MISC3_CDR_EN_FPL_SHIFT 1 +#define SERDES_L1_TM_MISC3_CDR_EN_FPL_MASK 0x00000002U + +/* +* CDR fast frequency lock control +*/ +#undef SERDES_L1_TM_MISC3_CDR_EN_FFL_DEFVAL +#undef SERDES_L1_TM_MISC3_CDR_EN_FFL_SHIFT +#undef SERDES_L1_TM_MISC3_CDR_EN_FFL_MASK +#define SERDES_L1_TM_MISC3_CDR_EN_FFL_DEFVAL 0x00000003 +#define SERDES_L1_TM_MISC3_CDR_EN_FFL_SHIFT 0 +#define SERDES_L1_TM_MISC3_CDR_EN_FFL_MASK 0x00000001U + +/* +* CDR fast phase lock control +*/ +#undef SERDES_L2_TM_MISC3_CDR_EN_FPL_DEFVAL +#undef SERDES_L2_TM_MISC3_CDR_EN_FPL_SHIFT +#undef SERDES_L2_TM_MISC3_CDR_EN_FPL_MASK +#define SERDES_L2_TM_MISC3_CDR_EN_FPL_DEFVAL 0x00000003 +#define SERDES_L2_TM_MISC3_CDR_EN_FPL_SHIFT 1 +#define SERDES_L2_TM_MISC3_CDR_EN_FPL_MASK 0x00000002U + +/* +* CDR fast frequency lock control +*/ +#undef SERDES_L2_TM_MISC3_CDR_EN_FFL_DEFVAL +#undef SERDES_L2_TM_MISC3_CDR_EN_FFL_SHIFT +#undef SERDES_L2_TM_MISC3_CDR_EN_FFL_MASK +#define SERDES_L2_TM_MISC3_CDR_EN_FFL_DEFVAL 0x00000003 +#define SERDES_L2_TM_MISC3_CDR_EN_FFL_SHIFT 0 +#define SERDES_L2_TM_MISC3_CDR_EN_FFL_MASK 0x00000001U + +/* +* CDR fast phase lock control +*/ +#undef SERDES_L3_TM_MISC3_CDR_EN_FPL_DEFVAL +#undef SERDES_L3_TM_MISC3_CDR_EN_FPL_SHIFT +#undef SERDES_L3_TM_MISC3_CDR_EN_FPL_MASK +#define SERDES_L3_TM_MISC3_CDR_EN_FPL_DEFVAL 0x00000003 +#define SERDES_L3_TM_MISC3_CDR_EN_FPL_SHIFT 1 +#define SERDES_L3_TM_MISC3_CDR_EN_FPL_MASK 0x00000002U + +/* +* CDR fast frequency lock control +*/ +#undef SERDES_L3_TM_MISC3_CDR_EN_FFL_DEFVAL +#undef SERDES_L3_TM_MISC3_CDR_EN_FFL_SHIFT +#undef SERDES_L3_TM_MISC3_CDR_EN_FFL_MASK +#define SERDES_L3_TM_MISC3_CDR_EN_FFL_DEFVAL 0x00000003 +#define SERDES_L3_TM_MISC3_CDR_EN_FFL_SHIFT 0 +#define SERDES_L3_TM_MISC3_CDR_EN_FFL_MASK 0x00000001U + +/* +* Force EQ offset correction algo off if not forced on +*/ +#undef SERDES_L0_TM_EQ11_FORCE_EQ_OFFS_OFF_DEFVAL +#undef SERDES_L0_TM_EQ11_FORCE_EQ_OFFS_OFF_SHIFT +#undef SERDES_L0_TM_EQ11_FORCE_EQ_OFFS_OFF_MASK +#define SERDES_L0_TM_EQ11_FORCE_EQ_OFFS_OFF_DEFVAL 0x00000000 +#define SERDES_L0_TM_EQ11_FORCE_EQ_OFFS_OFF_SHIFT 4 +#define SERDES_L0_TM_EQ11_FORCE_EQ_OFFS_OFF_MASK 0x00000010U + +/* +* Force EQ offset correction algo off if not forced on +*/ +#undef SERDES_L1_TM_EQ11_FORCE_EQ_OFFS_OFF_DEFVAL +#undef SERDES_L1_TM_EQ11_FORCE_EQ_OFFS_OFF_SHIFT +#undef SERDES_L1_TM_EQ11_FORCE_EQ_OFFS_OFF_MASK +#define SERDES_L1_TM_EQ11_FORCE_EQ_OFFS_OFF_DEFVAL 0x00000000 +#define SERDES_L1_TM_EQ11_FORCE_EQ_OFFS_OFF_SHIFT 4 +#define SERDES_L1_TM_EQ11_FORCE_EQ_OFFS_OFF_MASK 0x00000010U + +/* +* Force EQ offset correction algo off if not forced on +*/ +#undef SERDES_L2_TM_EQ11_FORCE_EQ_OFFS_OFF_DEFVAL +#undef SERDES_L2_TM_EQ11_FORCE_EQ_OFFS_OFF_SHIFT +#undef SERDES_L2_TM_EQ11_FORCE_EQ_OFFS_OFF_MASK +#define SERDES_L2_TM_EQ11_FORCE_EQ_OFFS_OFF_DEFVAL 0x00000000 +#define SERDES_L2_TM_EQ11_FORCE_EQ_OFFS_OFF_SHIFT 4 +#define SERDES_L2_TM_EQ11_FORCE_EQ_OFFS_OFF_MASK 0x00000010U + +/* +* Force EQ offset correction algo off if not forced on +*/ +#undef SERDES_L3_TM_EQ11_FORCE_EQ_OFFS_OFF_DEFVAL +#undef SERDES_L3_TM_EQ11_FORCE_EQ_OFFS_OFF_SHIFT +#undef SERDES_L3_TM_EQ11_FORCE_EQ_OFFS_OFF_MASK +#define SERDES_L3_TM_EQ11_FORCE_EQ_OFFS_OFF_DEFVAL 0x00000000 +#define SERDES_L3_TM_EQ11_FORCE_EQ_OFFS_OFF_SHIFT 4 +#define SERDES_L3_TM_EQ11_FORCE_EQ_OFFS_OFF_MASK 0x00000010U + +/* +* For future use +*/ +#undef SIOU_ECO_0_FIELD_DEFVAL +#undef SIOU_ECO_0_FIELD_SHIFT +#undef SIOU_ECO_0_FIELD_MASK +#define SIOU_ECO_0_FIELD_DEFVAL +#define SIOU_ECO_0_FIELD_SHIFT 0 +#define SIOU_ECO_0_FIELD_MASK 0xFFFFFFFFU + +/* +* Controls UPHY Lane 0 protocol configuration. 0 - PowerDown, 1 - PCIe .0, + * 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII0, 6 - Unused, 7 - Unused +*/ #undef SERDES_ICM_CFG0_L0_ICM_CFG_DEFVAL #undef SERDES_ICM_CFG0_L0_ICM_CFG_SHIFT #undef SERDES_ICM_CFG0_L0_ICM_CFG_MASK -#define SERDES_ICM_CFG0_L0_ICM_CFG_DEFVAL 0x00000000 -#define SERDES_ICM_CFG0_L0_ICM_CFG_SHIFT 0 -#define SERDES_ICM_CFG0_L0_ICM_CFG_MASK 0x00000007U +#define SERDES_ICM_CFG0_L0_ICM_CFG_DEFVAL 0x00000000 +#define SERDES_ICM_CFG0_L0_ICM_CFG_SHIFT 0 +#define SERDES_ICM_CFG0_L0_ICM_CFG_MASK 0x00000007U -/*Controls UPHY Lane 1 protocol configuration. 0 - PowerDown, 1 - PCIe.1, 2 - Sata1, 3 - USB0, 4 - DP.0, 5 - SGMII1, 6 - Unused - 7 - Unused*/ +/* +* Controls UPHY Lane 1 protocol configuration. 0 - PowerDown, 1 - PCIe.1, + * 2 - Sata1, 3 - USB0, 4 - DP.0, 5 - SGMII1, 6 - Unused, 7 - Unused +*/ #undef SERDES_ICM_CFG0_L1_ICM_CFG_DEFVAL #undef SERDES_ICM_CFG0_L1_ICM_CFG_SHIFT #undef SERDES_ICM_CFG0_L1_ICM_CFG_MASK -#define SERDES_ICM_CFG0_L1_ICM_CFG_DEFVAL 0x00000000 -#define SERDES_ICM_CFG0_L1_ICM_CFG_SHIFT 4 -#define SERDES_ICM_CFG0_L1_ICM_CFG_MASK 0x00000070U +#define SERDES_ICM_CFG0_L1_ICM_CFG_DEFVAL 0x00000000 +#define SERDES_ICM_CFG0_L1_ICM_CFG_SHIFT 4 +#define SERDES_ICM_CFG0_L1_ICM_CFG_MASK 0x00000070U -/*Controls UPHY Lane 2 protocol configuration. 0 - PowerDown, 1 - PCIe.1, 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII2, 6 - Unused - 7 - Unused*/ +/* +* Controls UPHY Lane 2 protocol configuration. 0 - PowerDown, 1 - PCIe.1, + * 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII2, 6 - Unused, 7 - Unused +*/ #undef SERDES_ICM_CFG1_L2_ICM_CFG_DEFVAL #undef SERDES_ICM_CFG1_L2_ICM_CFG_SHIFT #undef SERDES_ICM_CFG1_L2_ICM_CFG_MASK -#define SERDES_ICM_CFG1_L2_ICM_CFG_DEFVAL 0x00000000 -#define SERDES_ICM_CFG1_L2_ICM_CFG_SHIFT 0 -#define SERDES_ICM_CFG1_L2_ICM_CFG_MASK 0x00000007U +#define SERDES_ICM_CFG1_L2_ICM_CFG_DEFVAL 0x00000000 +#define SERDES_ICM_CFG1_L2_ICM_CFG_SHIFT 0 +#define SERDES_ICM_CFG1_L2_ICM_CFG_MASK 0x00000007U -/*Controls UPHY Lane 3 protocol configuration. 0 - PowerDown, 1 - PCIe.3, 2 - Sata1, 3 - USB1, 4 - DP.0, 5 - SGMII3, 6 - Unused - 7 - Unused*/ +/* +* Controls UPHY Lane 3 protocol configuration. 0 - PowerDown, 1 - PCIe.3, + * 2 - Sata1, 3 - USB1, 4 - DP.0, 5 - SGMII3, 6 - Unused, 7 - Unused +*/ #undef SERDES_ICM_CFG1_L3_ICM_CFG_DEFVAL #undef SERDES_ICM_CFG1_L3_ICM_CFG_SHIFT #undef SERDES_ICM_CFG1_L3_ICM_CFG_MASK -#define SERDES_ICM_CFG1_L3_ICM_CFG_DEFVAL 0x00000000 -#define SERDES_ICM_CFG1_L3_ICM_CFG_SHIFT 4 -#define SERDES_ICM_CFG1_L3_ICM_CFG_MASK 0x00000070U +#define SERDES_ICM_CFG1_L3_ICM_CFG_DEFVAL 0x00000000 +#define SERDES_ICM_CFG1_L3_ICM_CFG_SHIFT 4 +#define SERDES_ICM_CFG1_L3_ICM_CFG_MASK 0x00000070U -/*Enable/disable DP post2 path*/ +/* +* Enable/disable DP post2 path +*/ #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_DEFVAL #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_SHIFT #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_MASK -#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_DEFVAL 0x00000000 -#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_SHIFT 5 -#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_MASK 0x00000020U +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_DEFVAL 0x00000000 +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_SHIFT 5 +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_MASK 0x00000020U -/*Override enable/disable of DP post2 path*/ +/* +* Override enable/disable of DP post2 path +*/ #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_DEFVAL #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_SHIFT #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_MASK -#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_DEFVAL 0x00000000 -#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_SHIFT 4 -#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_MASK 0x00000010U +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_DEFVAL 0x00000000 +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_SHIFT 4 +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_MASK 0x00000010U -/*Override enable/disable of DP post1 path*/ +/* +* Override enable/disable of DP post1 path +*/ #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_DEFVAL #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_SHIFT #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_MASK -#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_DEFVAL 0x00000000 -#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_SHIFT 2 -#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_MASK 0x00000004U +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_DEFVAL 0x00000000 +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_SHIFT 2 +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_MASK 0x00000004U -/*Enable/disable DP main path*/ +/* +* Enable/disable DP main path +*/ #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_DEFVAL #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_SHIFT #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_MASK -#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_DEFVAL 0x00000000 -#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_SHIFT 1 -#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_MASK 0x00000002U +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_DEFVAL 0x00000000 +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_SHIFT 1 +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_MASK 0x00000002U -/*Override enable/disable of DP main path*/ +/* +* Override enable/disable of DP main path +*/ #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_DEFVAL #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_SHIFT #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_MASK -#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_DEFVAL 0x00000000 -#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_SHIFT 0 -#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_MASK 0x00000001U +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_DEFVAL 0x00000000 +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_SHIFT 0 +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_MASK 0x00000001U -/*Test register force for enabling/disablign TX deemphasis bits <17:0>*/ +/* +* Test register force for enabling/disablign TX deemphasis bits <17:0> +*/ #undef SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_DEFVAL #undef SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT #undef SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK -#define SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_DEFVAL 0x00000000 -#define SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT 0 -#define SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK 0x00000001U +#define SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_DEFVAL 0x00000000 +#define SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT 0 +#define SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK 0x00000001U -/*Test register force for enabling/disablign TX deemphasis bits <17:0>*/ +/* +* Test register force for enabling/disablign TX deemphasis bits <17:0> +*/ #undef SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_DEFVAL #undef SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT #undef SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK -#define SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_DEFVAL 0x00000000 -#define SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT 0 -#define SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK 0x00000001U +#define SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_DEFVAL 0x00000000 +#define SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT 0 +#define SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK 0x00000001U -/*FPHL FSM accumulate cycles*/ +/* +* FPHL FSM accumulate cycles +*/ #undef SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_DEFVAL #undef SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_SHIFT #undef SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_MASK -#define SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_DEFVAL 0x00000000 -#define SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_SHIFT 5 -#define SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_MASK 0x000000E0U +#define SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_DEFVAL 0x00000000 +#define SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_SHIFT 5 +#define SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_MASK 0x000000E0U -/*FFL Phase0 int gain aka 2ol SD update rate*/ +/* +* FFL Phase0 int gain aka 2ol SD update rate +*/ #undef SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_DEFVAL #undef SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_SHIFT #undef SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_MASK -#define SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_DEFVAL 0x00000000 -#define SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_SHIFT 0 -#define SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_MASK 0x0000001FU +#define SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_DEFVAL 0x00000000 +#define SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_SHIFT 0 +#define SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_MASK 0x0000001FU -/*FFL Phase0 prop gain aka 1ol SD update rate*/ +/* +* FFL Phase0 prop gain aka 1ol SD update rate +*/ #undef SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_DEFVAL #undef SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_SHIFT #undef SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_MASK -#define SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_DEFVAL 0x00000000 -#define SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_SHIFT 0 -#define SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_MASK 0x0000001FU +#define SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_DEFVAL 0x00000000 +#define SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_SHIFT 0 +#define SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_MASK 0x0000001FU -/*EQ stg 2 controls BYPASSED*/ +/* +* EQ stg 2 controls BYPASSED +*/ #undef SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_DEFVAL #undef SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_SHIFT #undef SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_MASK -#define SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_DEFVAL 0x00000000 -#define SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_SHIFT 5 -#define SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_MASK 0x00000020U +#define SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_DEFVAL 0x00000000 +#define SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_SHIFT 5 +#define SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_MASK 0x00000020U -/*EQ STG2 RL PROG*/ +/* +* EQ STG2 RL PROG +*/ #undef SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_DEFVAL #undef SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_SHIFT #undef SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_MASK -#define SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_DEFVAL 0x00000000 -#define SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_SHIFT 0 -#define SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_MASK 0x00000003U +#define SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_DEFVAL 0x00000000 +#define SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_SHIFT 0 +#define SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_MASK 0x00000003U -/*EQ stg 2 preamp mode val*/ +/* +* EQ stg 2 preamp mode val +*/ #undef SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_DEFVAL #undef SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_SHIFT #undef SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_MASK -#define SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_DEFVAL 0x00000000 -#define SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_SHIFT 2 -#define SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_MASK 0x00000004U +#define SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_DEFVAL 0x00000000 +#define SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_SHIFT 2 +#define SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_MASK 0x00000004U -/*Margining factor value*/ +/* +* Margining factor value +*/ #undef SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_DEFVAL #undef SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_SHIFT #undef SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_MASK -#define SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_DEFVAL 0x00000000 -#define SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_SHIFT 0 -#define SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_MASK 0x0000001FU +#define SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_DEFVAL 0x00000000 +#define SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_SHIFT 0 +#define SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_MASK 0x0000001FU -/*pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-emphasis, Others: reserved*/ +/* +* pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-em + * phasis, Others: reserved +*/ #undef SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_DEFVAL #undef SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT #undef SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK -#define SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_DEFVAL 0x00000002 -#define SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT 0 -#define SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK 0x000000FFU +#define SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_DEFVAL 0x00000002 +#define SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT 0 +#define SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK 0x000000FFU -/*pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-emphasis, Others: reserved*/ +/* +* pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-em + * phasis, Others: reserved +*/ #undef SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_DEFVAL #undef SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT #undef SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK -#define SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_DEFVAL 0x00000002 -#define SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT 0 -#define SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK 0x000000FFU +#define SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_DEFVAL 0x00000002 +#define SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT 0 +#define SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK 0x000000FFU #undef CRL_APB_RST_LPD_TOP_OFFSET #define CRL_APB_RST_LPD_TOP_OFFSET 0XFF5E023C -#undef USB3_0_FPD_POWER_PRSNT_OFFSET -#define USB3_0_FPD_POWER_PRSNT_OFFSET 0XFF9D0080 -#undef USB3_0_FPD_PIPE_CLK_OFFSET -#define USB3_0_FPD_PIPE_CLK_OFFSET 0XFF9D007C #undef CRL_APB_RST_LPD_TOP_OFFSET #define CRL_APB_RST_LPD_TOP_OFFSET 0XFF5E023C #undef CRL_APB_RST_LPD_IOU0_OFFSET @@ -26536,6 +34547,10 @@ #define USB3_0_XHCI_GUSB2PHYCFG_OFFSET 0XFE20C200 #undef USB3_0_XHCI_GFLADJ_OFFSET #define USB3_0_XHCI_GFLADJ_OFFSET 0XFE20C630 +#undef USB3_0_XHCI_GUCTL1_OFFSET +#define USB3_0_XHCI_GUCTL1_OFFSET 0XFE20C11C +#undef USB3_0_XHCI_GUCTL_OFFSET +#define USB3_0_XHCI_GUCTL_OFFSET 0XFE20C12C #undef PCIE_ATTRIB_ATTR_25_OFFSET #define PCIE_ATTRIB_ATTR_25_OFFSET 0XFD480064 #undef PCIE_ATTRIB_ATTR_7_OFFSET @@ -26626,6 +34641,8 @@ #define PCIE_ATTRIB_ATTR_35_OFFSET 0XFD48008C #undef CRF_APB_RST_FPD_TOP_OFFSET #define CRF_APB_RST_FPD_TOP_OFFSET 0XFD1A0100 +#undef GPIO_MASK_DATA_1_LSW_OFFSET +#define GPIO_MASK_DATA_1_LSW_OFFSET 0XFF0A0008 #undef SATA_AHCI_VENDOR_PP2C_OFFSET #define SATA_AHCI_VENDOR_PP2C_OFFSET 0XFD0C00AC #undef SATA_AHCI_VENDOR_PP3C_OFFSET @@ -26635,1015 +34652,1462 @@ #undef SATA_AHCI_VENDOR_PP5C_OFFSET #define SATA_AHCI_VENDOR_PP5C_OFFSET 0XFD0C00B8 -/*USB 0 reset for control registers*/ +/* +* USB 0 reset for control registers +*/ #undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL #undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT #undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK -#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL 0x00188FDF -#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT 10 -#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK 0x00000400U +#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT 10 +#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK 0x00000400U -/*This bit is used to choose between PIPE power present and 1'b1*/ -#undef USB3_0_FPD_POWER_PRSNT_OPTION_DEFVAL -#undef USB3_0_FPD_POWER_PRSNT_OPTION_SHIFT -#undef USB3_0_FPD_POWER_PRSNT_OPTION_MASK -#define USB3_0_FPD_POWER_PRSNT_OPTION_DEFVAL -#define USB3_0_FPD_POWER_PRSNT_OPTION_SHIFT 0 -#define USB3_0_FPD_POWER_PRSNT_OPTION_MASK 0x00000001U - -/*This bit is used to choose between PIPE clock coming from SerDes and the suspend clk*/ -#undef USB3_0_FPD_PIPE_CLK_OPTION_DEFVAL -#undef USB3_0_FPD_PIPE_CLK_OPTION_SHIFT -#undef USB3_0_FPD_PIPE_CLK_OPTION_MASK -#define USB3_0_FPD_PIPE_CLK_OPTION_DEFVAL -#define USB3_0_FPD_PIPE_CLK_OPTION_SHIFT 0 -#define USB3_0_FPD_PIPE_CLK_OPTION_MASK 0x00000001U - -/*USB 0 sleep circuit reset*/ +/* +* USB 0 sleep circuit reset +*/ #undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL #undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT #undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK -#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL 0x00188FDF -#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT 8 -#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK 0x00000100U +#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT 8 +#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK 0x00000100U -/*USB 0 reset*/ +/* +* USB 0 reset +*/ #undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL #undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT #undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK -#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL 0x00188FDF -#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT 6 -#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK 0x00000040U +#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT 6 +#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK 0x00000040U -/*GEM 3 reset*/ +/* +* GEM 3 reset +*/ #undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL #undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT #undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK -#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL 0x0000000F -#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT 3 -#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK 0x00000008U +#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL 0x0000000F +#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT 3 +#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK 0x00000008U -/*Sata PM clock control select*/ +/* +* Sata PM clock control select +*/ #undef SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_DEFVAL #undef SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_SHIFT #undef SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_MASK -#define SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_DEFVAL -#define SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_SHIFT 0 -#define SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_MASK 0x00000003U +#define SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_DEFVAL +#define SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_SHIFT 0 +#define SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_MASK 0x00000003U -/*Sata block level reset*/ +/* +* Sata block level reset +*/ #undef CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL #undef CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT #undef CRF_APB_RST_FPD_TOP_SATA_RESET_MASK -#define CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL 0x000F9FFE -#define CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT 1 -#define CRF_APB_RST_FPD_TOP_SATA_RESET_MASK 0x00000002U +#define CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT 1 +#define CRF_APB_RST_FPD_TOP_SATA_RESET_MASK 0x00000002U -/*PCIE config reset*/ +/* +* PCIE config reset +*/ #undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL #undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT #undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK -#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL 0x000F9FFE -#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT 19 -#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK 0x00080000U +#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT 19 +#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK 0x00080000U -/*PCIE bridge block level reset (AXI interface)*/ +/* +* PCIE bridge block level reset (AXI interface) +*/ #undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL #undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT #undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK -#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL 0x000F9FFE -#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT 18 -#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK 0x00040000U +#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT 18 +#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK 0x00040000U -/*Display Port block level reset (includes DPDMA)*/ +/* +* Display Port block level reset (includes DPDMA) +*/ #undef CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL #undef CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT #undef CRF_APB_RST_FPD_TOP_DP_RESET_MASK -#define CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL 0x000F9FFE -#define CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT 16 -#define CRF_APB_RST_FPD_TOP_DP_RESET_MASK 0x00010000U +#define CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT 16 +#define CRF_APB_RST_FPD_TOP_DP_RESET_MASK 0x00010000U -/*Set to '1' to hold the GT in reset. Clear to release.*/ +/* +* Set to '1' to hold the GT in reset. Clear to release. +*/ #undef DP_DP_PHY_RESET_GT_RESET_DEFVAL #undef DP_DP_PHY_RESET_GT_RESET_SHIFT #undef DP_DP_PHY_RESET_GT_RESET_MASK -#define DP_DP_PHY_RESET_GT_RESET_DEFVAL 0x00010003 -#define DP_DP_PHY_RESET_GT_RESET_SHIFT 1 -#define DP_DP_PHY_RESET_GT_RESET_MASK 0x00000002U +#define DP_DP_PHY_RESET_GT_RESET_DEFVAL 0x00010003 +#define DP_DP_PHY_RESET_GT_RESET_SHIFT 1 +#define DP_DP_PHY_RESET_GT_RESET_MASK 0x00000002U -/*Two bits per lane. When set to 11, moves the GT to power down mode. When set to 00, GT will be in active state. bits [1:0] - - ane0 Bits [3:2] - lane 1*/ +/* +* Two bits per lane. When set to 11, moves the GT to power down mode. When + * set to 00, GT will be in active state. bits [1:0] - lane0 Bits [3:2] - + * lane 1 +*/ #undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_DEFVAL #undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT #undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK -#define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_DEFVAL 0x00000000 -#define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT 0 -#define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK 0x0000000FU +#define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_DEFVAL 0x00000000 +#define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT 0 +#define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK 0x0000000FU -/*USB 2.0 Turnaround Time (USBTrdTim) Sets the turnaround time in PHY clocks. Specifies the response time for a MAC request to - he Packet FIFO Controller (PFC) to fetch data from the DFIFO (SPRAM). The following are the required values for the minimum S - C bus frequency of 60 MHz. USB turnaround time is a critical certification criteria when using long cables and five hub level - . The required values for this field: - 4'h5: When the MAC interface is 16-bit UTMI+. - 4'h9: When the MAC interface is 8-bit - UTMI+/ULPI. If SoC bus clock is less than 60 MHz, and USB turnaround time is not critical, this field can be set to a larger - alue. Note: This field is valid only in device mode.*/ +/* +* USB 2.0 Turnaround Time (USBTrdTim) Sets the turnaround time in PHY cloc + * ks. Specifies the response time for a MAC request to the Packet FIFO Con + * troller (PFC) to fetch data from the DFIFO (SPRAM). The following are th + * e required values for the minimum SoC bus frequency of 60 MHz. USB turna + * round time is a critical certification criteria when using long cables a + * nd five hub levels. The required values for this field: - 4'h5: When the + * MAC interface is 16-bit UTMI+. - 4'h9: When the MAC interface is 8-bit + * UTMI+/ULPI. If SoC bus clock is less than 60 MHz, and USB turnaround tim + * e is not critical, this field can be set to a larger value. Note: This f + * ield is valid only in device mode. +*/ #undef USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_DEFVAL #undef USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_SHIFT #undef USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_MASK -#define USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_DEFVAL 0x00000000 -#define USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_SHIFT 10 -#define USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_MASK 0x00003C00U +#define USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_DEFVAL 0x00000000 +#define USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_SHIFT 10 +#define USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_MASK 0x00003C00U -/*Transceiver Delay: Enables a delay between the assertion of the UTMI/ULPI Transceiver Select signal (for HS) and the assertio - of the TxValid signal during a HS Chirp. When this bit is set to 1, a delay (of approximately 2.5 us) is introduced from the - time when the Transceiver Select is set to 2'b00 (HS) to the time the TxValid is driven to 0 for sending the chirp-K. This de - ay is required for some UTMI/ULPI PHYs. Note: - If you enable the hibernation feature when the device core comes out of power - off, you must re-initialize this bit with the appropriate value because the core does not save and restore this bit value dur - ng hibernation. - This bit is valid only in device mode.*/ +/* +* Transceiver Delay: Enables a delay between the assertion of the UTMI/ULP + * I Transceiver Select signal (for HS) and the assertion of the TxValid si + * gnal during a HS Chirp. When this bit is set to 1, a delay (of approxima + * tely 2.5 us) is introduced from the time when the Transceiver Select is + * set to 2'b00 (HS) to the time the TxValid is driven to 0 for sending the + * chirp-K. This delay is required for some UTMI/ULPI PHYs. Note: - If you + * enable the hibernation feature when the device core comes out of power- + * off, you must re-initialize this bit with the appropriate value because + * the core does not save and restore this bit value during hibernation. - + * This bit is valid only in device mode. +*/ #undef USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_DEFVAL #undef USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_SHIFT #undef USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_MASK -#define USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_DEFVAL 0x00000000 -#define USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_SHIFT 9 -#define USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_MASK 0x00000200U +#define USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_DEFVAL 0x00000000 +#define USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_SHIFT 9 +#define USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_MASK 0x00000200U -/*Enable utmi_sleep_n and utmi_l1_suspend_n (EnblSlpM) The application uses this bit to control utmi_sleep_n and utmi_l1_suspen - _n assertion to the PHY in the L1 state. - 1'b0: utmi_sleep_n and utmi_l1_suspend_n assertion from the core is not transferre - to the external PHY. - 1'b1: utmi_sleep_n and utmi_l1_suspend_n assertion from the core is transferred to the external PHY. - ote: This bit must be set high for Port0 if PHY is used. Note: In Device mode - Before issuing any device endpoint command wh - n operating in 2.0 speeds, disable this bit and enable it after the command completes. Without disabling this bit, if a comma - d is issued when the device is in L1 state and if mac2_clk (utmi_clk/ulpi_clk) is gated off, the command will not get complet - d.*/ +/* +* Enable utmi_sleep_n and utmi_l1_suspend_n (EnblSlpM) The application use + * s this bit to control utmi_sleep_n and utmi_l1_suspend_n assertion to th + * e PHY in the L1 state. - 1'b0: utmi_sleep_n and utmi_l1_suspend_n assert + * ion from the core is not transferred to the external PHY. - 1'b1: utmi_s + * leep_n and utmi_l1_suspend_n assertion from the core is transferred to t + * he external PHY. Note: This bit must be set high for Port0 if PHY is use + * d. Note: In Device mode - Before issuing any device endpoint command whe + * n operating in 2.0 speeds, disable this bit and enable it after the comm + * and completes. Without disabling this bit, if a command is issued when t + * he device is in L1 state and if mac2_clk (utmi_clk/ulpi_clk) is gated of + * f, the command will not get completed. +*/ #undef USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_DEFVAL #undef USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_SHIFT #undef USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_MASK -#define USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_DEFVAL 0x00000000 -#define USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_SHIFT 8 -#define USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_MASK 0x00000100U +#define USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_DEFVAL 0x00000000 +#define USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_SHIFT 8 +#define USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_MASK 0x00000100U -/*USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial Transceiver Select The application uses this bit to select a high-speed P - Y or a full-speed transceiver. - 1'b0: USB 2.0 high-speed UTMI+ or ULPI PHY. This bit is always 0, with Write Only access. - - 'b1: USB 1.1 full-speed serial transceiver. This bit is always 1, with Write Only access. If both interface types are selecte - in coreConsultant (that is, parameters' values are not zero), the application uses this bit to select the active interface i - active, with Read-Write bit access. Note: USB 1.1 full-serial transceiver is not supported. This bit always reads as 1'b0.*/ +/* +* USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial Transceiver Select T + * he application uses this bit to select a high-speed PHY or a full-speed + * transceiver. - 1'b0: USB 2.0 high-speed UTMI+ or ULPI PHY. This bit is a + * lways 0, with Write Only access. - 1'b1: USB 1.1 full-speed serial trans + * ceiver. This bit is always 1, with Write Only access. If both interface + * types are selected in coreConsultant (that is, parameters' values are no + * t zero), the application uses this bit to select the active interface is + * active, with Read-Write bit access. Note: USB 1.1 full-serial transceiv + * er is not supported. This bit always reads as 1'b0. +*/ #undef USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_DEFVAL #undef USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_SHIFT #undef USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_MASK -#define USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_DEFVAL 0x00000000 -#define USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_SHIFT 7 -#define USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_MASK 0x00000080U +#define USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_DEFVAL 0x00000000 +#define USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_SHIFT 7 +#define USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_MASK 0x00000080U -/*Full-Speed Serial Interface Select (FSIntf) The application uses this bit to select a unidirectional or bidirectional USB 1.1 - full-speed serial transceiver interface. - 1'b0: 6-pin unidirectional full-speed serial interface. This bit is set to 0 with - ead Only access. - 1'b1: 3-pin bidirectional full-speed serial interface. This bit is set to 0 with Read Only access. Note: U - B 1.1 full-speed serial interface is not supported. This bit always reads as 1'b0.*/ +/* +* Suspend USB2.0 HS/FS/LS PHY (SusPHY) When set, USB2.0 PHY enters Suspend + * mode if Suspend conditions are valid. For DRD/OTG configurations, it is + * recommended that this bit is set to 0 during coreConsultant configurati + * on. If it is set to 1, then the application must clear this bit after po + * wer-on reset. Application needs to set it to 1 after the core initializa + * tion completes. For all other configurations, this bit can be set to 1 d + * uring core configuration. Note: - In host mode, on reset, this bit is se + * t to 1. Software can override this bit after reset. - In device mode, be + * fore issuing any device endpoint command when operating in 2.0 speeds, d + * isable this bit and enable it after the command completes. If you issue + * a command without disabling this bit when the device is in L2 state and + * if mac2_clk (utmi_clk/ulpi_clk) is gated off, the command will not get c + * ompleted. +*/ +#undef USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_DEFVAL +#undef USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_SHIFT +#undef USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_MASK +#define USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_DEFVAL 0x00000000 +#define USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_SHIFT 6 +#define USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_MASK 0x00000040U + +/* +* Full-Speed Serial Interface Select (FSIntf) The application uses this bi + * t to select a unidirectional or bidirectional USB 1.1 full-speed serial + * transceiver interface. - 1'b0: 6-pin unidirectional full-speed serial in + * terface. This bit is set to 0 with Read Only access. - 1'b1: 3-pin bidir + * ectional full-speed serial interface. This bit is set to 0 with Read Onl + * y access. Note: USB 1.1 full-speed serial interface is not supported. Th + * is bit always reads as 1'b0. +*/ #undef USB3_0_XHCI_GUSB2PHYCFG_FSINTF_DEFVAL #undef USB3_0_XHCI_GUSB2PHYCFG_FSINTF_SHIFT #undef USB3_0_XHCI_GUSB2PHYCFG_FSINTF_MASK -#define USB3_0_XHCI_GUSB2PHYCFG_FSINTF_DEFVAL 0x00000000 -#define USB3_0_XHCI_GUSB2PHYCFG_FSINTF_SHIFT 5 -#define USB3_0_XHCI_GUSB2PHYCFG_FSINTF_MASK 0x00000020U +#define USB3_0_XHCI_GUSB2PHYCFG_FSINTF_DEFVAL 0x00000000 +#define USB3_0_XHCI_GUSB2PHYCFG_FSINTF_SHIFT 5 +#define USB3_0_XHCI_GUSB2PHYCFG_FSINTF_MASK 0x00000020U -/*ULPI or UTMI+ Select (ULPI_UTMI_Sel) The application uses this bit to select a UTMI+ or ULPI Interface. - 1'b0: UTMI+ Interfa - e - 1'b1: ULPI Interface This bit is writable only if UTMI+ and ULPI is specified for High-Speed PHY Interface(s) in coreCons - ltant configuration (DWC_USB3_HSPHY_INTERFACE = 3). Otherwise, this bit is read-only and the value depends on the interface s - lected through DWC_USB3_HSPHY_INTERFACE.*/ +/* +* ULPI or UTMI+ Select (ULPI_UTMI_Sel) The application uses this bit to se + * lect a UTMI+ or ULPI Interface. - 1'b0: UTMI+ Interface - 1'b1: ULPI Int + * erface This bit is writable only if UTMI+ and ULPI is specified for High + * -Speed PHY Interface(s) in coreConsultant configuration (DWC_USB3_HSPHY_ + * INTERFACE = 3). Otherwise, this bit is read-only and the value depends o + * n the interface selected through DWC_USB3_HSPHY_INTERFACE. +*/ #undef USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_DEFVAL #undef USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_SHIFT #undef USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_MASK -#define USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_DEFVAL 0x00000000 -#define USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_SHIFT 4 -#define USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_MASK 0x00000010U +#define USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_DEFVAL 0x00000000 +#define USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_SHIFT 4 +#define USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_MASK 0x00000010U -/*PHY Interface (PHYIf) If UTMI+ is selected, the application uses this bit to configure the core to support a UTMI+ PHY with a - 8- or 16-bit interface. - 1'b0: 8 bits - 1'b1: 16 bits ULPI Mode: 1'b0 Note: - All the enabled 2.0 ports must have the same - lock frequency as Port0 clock frequency (utmi_clk[0]). - The UTMI 8-bit and 16-bit modes cannot be used together for differen - ports at the same time (that is, all the ports must be in 8-bit mode, or all of them must be in 16-bit mode, at a time). - I - any of the USB 2.0 ports is selected as ULPI port for operation, then all the USB 2.0 ports must be operating at 60 MHz.*/ +/* +* PHY Interface (PHYIf) If UTMI+ is selected, the application uses this bi + * t to configure the core to support a UTMI+ PHY with an 8- or 16-bit inte + * rface. - 1'b0: 8 bits - 1'b1: 16 bits ULPI Mode: 1'b0 Note: - All the en + * abled 2.0 ports must have the same clock frequency as Port0 clock freque + * ncy (utmi_clk[0]). - The UTMI 8-bit and 16-bit modes cannot be used toge + * ther for different ports at the same time (that is, all the ports must b + * e in 8-bit mode, or all of them must be in 16-bit mode, at a time). - If + * any of the USB 2.0 ports is selected as ULPI port for operation, then a + * ll the USB 2.0 ports must be operating at 60 MHz. +*/ #undef USB3_0_XHCI_GUSB2PHYCFG_PHYIF_DEFVAL #undef USB3_0_XHCI_GUSB2PHYCFG_PHYIF_SHIFT #undef USB3_0_XHCI_GUSB2PHYCFG_PHYIF_MASK -#define USB3_0_XHCI_GUSB2PHYCFG_PHYIF_DEFVAL 0x00000000 -#define USB3_0_XHCI_GUSB2PHYCFG_PHYIF_SHIFT 3 -#define USB3_0_XHCI_GUSB2PHYCFG_PHYIF_MASK 0x00000008U +#define USB3_0_XHCI_GUSB2PHYCFG_PHYIF_DEFVAL 0x00000000 +#define USB3_0_XHCI_GUSB2PHYCFG_PHYIF_SHIFT 3 +#define USB3_0_XHCI_GUSB2PHYCFG_PHYIF_MASK 0x00000008U -/*HS/FS Timeout Calibration (TOutCal) The number of PHY clocks, as indicated by the application in this field, is multiplied by - a bit-time factor; this factor is added to the high-speed/full-speed interpacket timeout duration in the core to account for - dditional delays introduced by the PHY. This may be required, since the delay introduced by the PHY in generating the linesta - e condition may vary among PHYs. The USB standard timeout value for high-speed operation is 736 to 816 (inclusive) bit times. - The USB standard timeout value for full-speed operation is 16 to 18 (inclusive) bit times. The application must program this - ield based on the speed of connection. The number of bit times added per PHY clock are: High-speed operation: - One 30-MHz PH - clock = 16 bit times - One 60-MHz PHY clock = 8 bit times Full-speed operation: - One 30-MHz PHY clock = 0.4 bit times - One - 60-MHz PHY clock = 0.2 bit times - One 48-MHz PHY clock = 0.25 bit times*/ +/* +* HS/FS Timeout Calibration (TOutCal) The number of PHY clocks, as indicat + * ed by the application in this field, is multiplied by a bit-time factor; + * this factor is added to the high-speed/full-speed interpacket timeout d + * uration in the core to account for additional delays introduced by the P + * HY. This may be required, since the delay introduced by the PHY in gener + * ating the linestate condition may vary among PHYs. The USB standard time + * out value for high-speed operation is 736 to 816 (inclusive) bit times. + * The USB standard timeout value for full-speed operation is 16 to 18 (inc + * lusive) bit times. The application must program this field based on the + * speed of connection. The number of bit times added per PHY clock are: Hi + * gh-speed operation: - One 30-MHz PHY clock = 16 bit times - One 60-MHz P + * HY clock = 8 bit times Full-speed operation: - One 30-MHz PHY clock = 0. + * 4 bit times - One 60-MHz PHY clock = 0.2 bit times - One 48-MHz PHY cloc + * k = 0.25 bit times +*/ #undef USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_DEFVAL #undef USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_SHIFT #undef USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_MASK -#define USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_DEFVAL 0x00000000 -#define USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_SHIFT 0 -#define USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_MASK 0x00000007U +#define USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_DEFVAL 0x00000000 +#define USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_SHIFT 0 +#define USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_MASK 0x00000007U -/*This field indicates the frame length adjustment to be applied when SOF/ITP counter is running on the ref_clk. This register - alue is used to adjust the ITP interval when GCTL[SOFITPSYNC] is set to '1'; SOF and ITP interval when GLADJ.GFLADJ_REFCLK_LP - _SEL is set to '1'. This field must be programmed to a non-zero value only if GFLADJ_REFCLK_LPM_SEL is set to '1' or GCTL.SOF - TPSYNC is set to '1'. The value is derived as follows: FLADJ_REF_CLK_FLADJ=((125000/ref_clk_period_integer)-(125000/ref_clk_p - riod)) * ref_clk_period where - the ref_clk_period_integer is the integer value of the ref_clk period got by truncating the d - cimal (fractional) value that is programmed in the GUCTL.REF_CLK_PERIOD field. - the ref_clk_period is the ref_clk period inc - uding the fractional value. Examples: If the ref_clk is 24 MHz then - GUCTL.REF_CLK_PERIOD = 41 - GFLADJ.GLADJ_REFCLK_FLADJ = - ((125000/41)-(125000/41.6666))*41.6666 = 2032 (ignoring the fractional value) If the ref_clk is 48 MHz then - GUCTL.REF_CLK_P - RIOD = 20 - GFLADJ.GLADJ_REFCLK_FLADJ = ((125000/20)-(125000/20.8333))*20.8333 = 5208 (ignoring the fractional value)*/ +/* +* ULPI External VBUS Drive (ULPIExtVbusDrv) Selects supply source to drive + * 5V on VBUS, in the ULPI PHY. - 1'b0: PHY drives VBUS with internal char + * ge pump (default). - 1'b1: PHY drives VBUS with an external supply. (Onl + * y when RTL parameter DWC_USB3_HSPHY_INTERFACE = 2 or 3) +*/ +#undef USB3_0_XHCI_GUSB2PHYCFG_ULPIEXTVBUSDRV_DEFVAL +#undef USB3_0_XHCI_GUSB2PHYCFG_ULPIEXTVBUSDRV_SHIFT +#undef USB3_0_XHCI_GUSB2PHYCFG_ULPIEXTVBUSDRV_MASK +#define USB3_0_XHCI_GUSB2PHYCFG_ULPIEXTVBUSDRV_DEFVAL 0x00000000 +#define USB3_0_XHCI_GUSB2PHYCFG_ULPIEXTVBUSDRV_SHIFT 17 +#define USB3_0_XHCI_GUSB2PHYCFG_ULPIEXTVBUSDRV_MASK 0x00020000U + +/* +* This field indicates the frame length adjustment to be applied when SOF/ + * ITP counter is running on the ref_clk. This register value is used to ad + * just the ITP interval when GCTL[SOFITPSYNC] is set to '1'; SOF and ITP i + * nterval when GLADJ.GFLADJ_REFCLK_LPM_SEL is set to '1'. This field must + * be programmed to a non-zero value only if GFLADJ_REFCLK_LPM_SEL is set t + * o '1' or GCTL.SOFITPSYNC is set to '1'. The value is derived as follows: + * FLADJ_REF_CLK_FLADJ=((125000/ref_clk_period_integer)-(125000/ref_clk_pe + * riod)) * ref_clk_period where - the ref_clk_period_integer is the intege + * r value of the ref_clk period got by truncating the decimal (fractional) + * value that is programmed in the GUCTL.REF_CLK_PERIOD field. - the ref_c + * lk_period is the ref_clk period including the fractional value. Examples + * : If the ref_clk is 24 MHz then - GUCTL.REF_CLK_PERIOD = 41 - GFLADJ.GLA + * DJ_REFCLK_FLADJ = ((125000/41)-(125000/41.6666))*41.6666 = 2032 (ignorin + * g the fractional value) If the ref_clk is 48 MHz then - GUCTL.REF_CLK_PE + * RIOD = 20 - GFLADJ.GLADJ_REFCLK_FLADJ = ((125000/20)-(125000/20.8333))*2 + * 0.8333 = 5208 (ignoring the fractional value) +*/ #undef USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_DEFVAL #undef USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_SHIFT #undef USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_MASK -#define USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_DEFVAL 0x00000000 -#define USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_SHIFT 8 -#define USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_MASK 0x003FFF00U +#define USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_DEFVAL 0x00000000 +#define USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_SHIFT 8 +#define USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_MASK 0x003FFF00U -/*If TRUE Completion Timeout Disable is supported. This is required to be TRUE for Endpoint and either setting allowed for Root - ports. Drives Device Capability 2 [4]; EP=0x0001; RP=0x0001*/ +/* +* When this bit is set to '0', termsel, xcvrsel will become 0 during end o + * f resume while the opmode will become 0 once controller completes end of + * resume and enters U0 state (2 separate commandswill be issued). When th + * is bit is set to '1', all the termsel, xcvrsel, opmode becomes 0 during + * end of resume itself (only 1 command will be issued) +*/ +#undef USB3_0_XHCI_GUCTL1_RESUME_TERMSEL_XCVRSEL_UNIFY_DEFVAL +#undef USB3_0_XHCI_GUCTL1_RESUME_TERMSEL_XCVRSEL_UNIFY_SHIFT +#undef USB3_0_XHCI_GUCTL1_RESUME_TERMSEL_XCVRSEL_UNIFY_MASK +#define USB3_0_XHCI_GUCTL1_RESUME_TERMSEL_XCVRSEL_UNIFY_DEFVAL 0x00000000 +#define USB3_0_XHCI_GUCTL1_RESUME_TERMSEL_XCVRSEL_UNIFY_SHIFT 10 +#define USB3_0_XHCI_GUCTL1_RESUME_TERMSEL_XCVRSEL_UNIFY_MASK 0x00000400U + +/* +* Reserved +*/ +#undef USB3_0_XHCI_GUCTL1_RESERVED_9_DEFVAL +#undef USB3_0_XHCI_GUCTL1_RESERVED_9_SHIFT +#undef USB3_0_XHCI_GUCTL1_RESERVED_9_MASK +#define USB3_0_XHCI_GUCTL1_RESERVED_9_DEFVAL 0x00000000 +#define USB3_0_XHCI_GUCTL1_RESERVED_9_SHIFT 9 +#define USB3_0_XHCI_GUCTL1_RESERVED_9_MASK 0x00000200U + +/* +* Host IN Auto Retry (USBHstInAutoRetryEn) When set, this field enables th + * e Auto Retry feature. For IN transfers (non-isochronous) that encounter + * data packets with CRC errors or internal overrun scenarios, the auto ret + * ry feature causes the Host core to reply to the device with a non-termin + * ating retry ACK (that is, an ACK transaction packet with Retry = 1 and N + * umP != 0). If the Auto Retry feature is disabled (default), the core wil + * l respond with a terminating retry ACK (that is, an ACK transaction pack + * et with Retry = 1 and NumP = 0). - 1'b0: Auto Retry Disabled - 1'b1: Aut + * o Retry Enabled Note: This bit is also applicable to the device mode. +*/ +#undef USB3_0_XHCI_GUCTL_USBHSTINAUTORETRYEN_DEFVAL +#undef USB3_0_XHCI_GUCTL_USBHSTINAUTORETRYEN_SHIFT +#undef USB3_0_XHCI_GUCTL_USBHSTINAUTORETRYEN_MASK +#define USB3_0_XHCI_GUCTL_USBHSTINAUTORETRYEN_DEFVAL 0x00000000 +#define USB3_0_XHCI_GUCTL_USBHSTINAUTORETRYEN_SHIFT 14 +#define USB3_0_XHCI_GUCTL_USBHSTINAUTORETRYEN_MASK 0x00004000U + +/* +* If TRUE Completion Timeout Disable is supported. This is required to be + * TRUE for Endpoint and either setting allowed for Root ports. Drives Devi + * ce Capability 2 [4]; EP=0x0001; RP=0x0001 +*/ #undef PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_DEFVAL #undef PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_SHIFT #undef PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_MASK -#define PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_DEFVAL 0x00000905 -#define PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_SHIFT 9 -#define PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_MASK 0x00000200U +#define PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_DEFVAL 0x00000905 +#define PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_SHIFT 9 +#define PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_MASK 0x00000200U -/*Specifies mask/settings for Base Address Register (BAR) 0. If BAR is not to be implemented, set to 32'h00000000. Bits are def - ned as follows: Memory Space BAR [0] = Mem Space Indicator (set to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = - Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory a - erture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR1,BAR0\'7d to 1. IO Space BAR 0] = IO Space Indicator - set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o apert - re size in bytes.; EP=0x0004; RP=0x0000*/ +/* +* Specifies mask/settings for Base Address Register (BAR) 0. If BAR is not + * to be implemented, set to 32'h00000000. Bits are defined as follows: Me + * mory Space BAR [0] = Mem Space Indicator (set to 0) [2:1] = Type field ( + * 10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask + * for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to 1, w + * here 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63: + * n bits of \'7bBAR1,BAR0\'7d to 1. IO Space BAR 0] = IO Space Indicator ( + * set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of B + * AR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; + * EP=0x0004; RP=0x0000 +*/ #undef PCIE_ATTRIB_ATTR_7_ATTR_BAR0_DEFVAL #undef PCIE_ATTRIB_ATTR_7_ATTR_BAR0_SHIFT #undef PCIE_ATTRIB_ATTR_7_ATTR_BAR0_MASK -#define PCIE_ATTRIB_ATTR_7_ATTR_BAR0_DEFVAL -#define PCIE_ATTRIB_ATTR_7_ATTR_BAR0_SHIFT 0 -#define PCIE_ATTRIB_ATTR_7_ATTR_BAR0_MASK 0x0000FFFFU +#define PCIE_ATTRIB_ATTR_7_ATTR_BAR0_DEFVAL +#define PCIE_ATTRIB_ATTR_7_ATTR_BAR0_SHIFT 0 +#define PCIE_ATTRIB_ATTR_7_ATTR_BAR0_MASK 0x0000FFFFU -/*Specifies mask/settings for Base Address Register (BAR) 0. If BAR is not to be implemented, set to 32'h00000000. Bits are def - ned as follows: Memory Space BAR [0] = Mem Space Indicator (set to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = - Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory a - erture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR1,BAR0\'7d to 1. IO Space BAR 0] = IO Space Indicator - set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o apert - re size in bytes.; EP=0xFFF0; RP=0x0000*/ +/* +* Specifies mask/settings for Base Address Register (BAR) 0. If BAR is not + * to be implemented, set to 32'h00000000. Bits are defined as follows: Me + * mory Space BAR [0] = Mem Space Indicator (set to 0) [2:1] = Type field ( + * 10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask + * for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to 1, w + * here 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63: + * n bits of \'7bBAR1,BAR0\'7d to 1. IO Space BAR 0] = IO Space Indicator ( + * set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of B + * AR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; + * EP=0xFFF0; RP=0x0000 +*/ #undef PCIE_ATTRIB_ATTR_8_ATTR_BAR0_DEFVAL #undef PCIE_ATTRIB_ATTR_8_ATTR_BAR0_SHIFT #undef PCIE_ATTRIB_ATTR_8_ATTR_BAR0_MASK -#define PCIE_ATTRIB_ATTR_8_ATTR_BAR0_DEFVAL -#define PCIE_ATTRIB_ATTR_8_ATTR_BAR0_SHIFT 0 -#define PCIE_ATTRIB_ATTR_8_ATTR_BAR0_MASK 0x0000FFFFU +#define PCIE_ATTRIB_ATTR_8_ATTR_BAR0_DEFVAL +#define PCIE_ATTRIB_ATTR_8_ATTR_BAR0_SHIFT 0 +#define PCIE_ATTRIB_ATTR_8_ATTR_BAR0_MASK 0x0000FFFFU -/*Specifies mask/settings for Base Address Register (BAR) 1 if BAR0 is a 32-bit BAR, or the upper bits of \'7bBAR1,BAR0\'7d if - AR0 is a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR0 description if this functions as the uppe - bits of a 64-bit BAR. Bits are defined as follows: Memory Space BAR (not upper bits of BAR0) [0] = Mem Space Indicator (set - o 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if - 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of - '7bBAR2,BAR1\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable b - ts of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000*/ +/* +* Specifies mask/settings for Base Address Register (BAR) 1 if BAR0 is a 3 + * 2-bit BAR, or the upper bits of \'7bBAR1,BAR0\'7d if BAR0 is a 64-bit BA + * R. If BAR is not to be implemented, set to 32'h00000000. See BAR0 descri + * ption if this functions as the upper bits of a 64-bit BAR. Bits are defi + * ned as follows: Memory Space BAR (not upper bits of BAR0) [0] = Mem Spac + * e Indicator (set to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) + * [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if + * 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size + * in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR2,BAR1\'7d t + * o 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set + * to 0) [31:2] = Mask for writable bits of BAR; set uppermost 31:n bits t + * o 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000 +*/ #undef PCIE_ATTRIB_ATTR_9_ATTR_BAR1_DEFVAL #undef PCIE_ATTRIB_ATTR_9_ATTR_BAR1_SHIFT #undef PCIE_ATTRIB_ATTR_9_ATTR_BAR1_MASK -#define PCIE_ATTRIB_ATTR_9_ATTR_BAR1_DEFVAL -#define PCIE_ATTRIB_ATTR_9_ATTR_BAR1_SHIFT 0 -#define PCIE_ATTRIB_ATTR_9_ATTR_BAR1_MASK 0x0000FFFFU +#define PCIE_ATTRIB_ATTR_9_ATTR_BAR1_DEFVAL +#define PCIE_ATTRIB_ATTR_9_ATTR_BAR1_SHIFT 0 +#define PCIE_ATTRIB_ATTR_9_ATTR_BAR1_MASK 0x0000FFFFU -/*Specifies mask/settings for Base Address Register (BAR) 1 if BAR0 is a 32-bit BAR, or the upper bits of \'7bBAR1,BAR0\'7d if - AR0 is a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR0 description if this functions as the uppe - bits of a 64-bit BAR. Bits are defined as follows: Memory Space BAR (not upper bits of BAR0) [0] = Mem Space Indicator (set - o 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if - 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of - '7bBAR2,BAR1\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable b - ts of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000*/ +/* +* Specifies mask/settings for Base Address Register (BAR) 1 if BAR0 is a 3 + * 2-bit BAR, or the upper bits of \'7bBAR1,BAR0\'7d if BAR0 is a 64-bit BA + * R. If BAR is not to be implemented, set to 32'h00000000. See BAR0 descri + * ption if this functions as the upper bits of a 64-bit BAR. Bits are defi + * ned as follows: Memory Space BAR (not upper bits of BAR0) [0] = Mem Spac + * e Indicator (set to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) + * [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if + * 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size + * in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR2,BAR1\'7d t + * o 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set + * to 0) [31:2] = Mask for writable bits of BAR; set uppermost 31:n bits t + * o 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000 +*/ #undef PCIE_ATTRIB_ATTR_10_ATTR_BAR1_DEFVAL #undef PCIE_ATTRIB_ATTR_10_ATTR_BAR1_SHIFT #undef PCIE_ATTRIB_ATTR_10_ATTR_BAR1_MASK -#define PCIE_ATTRIB_ATTR_10_ATTR_BAR1_DEFVAL -#define PCIE_ATTRIB_ATTR_10_ATTR_BAR1_SHIFT 0 -#define PCIE_ATTRIB_ATTR_10_ATTR_BAR1_MASK 0x0000FFFFU +#define PCIE_ATTRIB_ATTR_10_ATTR_BAR1_DEFVAL +#define PCIE_ATTRIB_ATTR_10_ATTR_BAR1_SHIFT 0 +#define PCIE_ATTRIB_ATTR_10_ATTR_BAR1_MASK 0x0000FFFFU -/*For an endpoint, specifies mask/settings for Base Address Register (BAR) 2 if BAR1 is a 32-bit BAR, or the upper bits of \'7b - AR2,BAR1\'7d if BAR1 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR1 descri - tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to 00FF_FFFF. For an endpoin - , bits are defined as follows: Memory Space BAR (not upper bits of BAR1) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi - ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe - most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR3,BAR2\'7d to - . IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper - ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0x0004; RP=0xFFFF*/ +/* +* For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 2 if BAR1 is a 32-bit BAR, or the upper bits of \'7bBAR2,BAR1\'7d if BA + * R1 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR1 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root: This must be set to 00FF_FFF + * F. For an endpoint, bits are defined as follows: Memory Space BAR (not u + * pper bits of BAR1) [0] = Mem Space Indicator (set to 0) [2:1] = Type fie + * ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = M + * ask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to + * 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost + * 63:n bits of \'7bBAR3,BAR2\'7d to 1. IO Space BAR 0] = IO Space Indicat + * or (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits + * of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in byt + * es.; EP=0x0004; RP=0xFFFF +*/ #undef PCIE_ATTRIB_ATTR_11_ATTR_BAR2_DEFVAL #undef PCIE_ATTRIB_ATTR_11_ATTR_BAR2_SHIFT #undef PCIE_ATTRIB_ATTR_11_ATTR_BAR2_MASK -#define PCIE_ATTRIB_ATTR_11_ATTR_BAR2_DEFVAL -#define PCIE_ATTRIB_ATTR_11_ATTR_BAR2_SHIFT 0 -#define PCIE_ATTRIB_ATTR_11_ATTR_BAR2_MASK 0x0000FFFFU +#define PCIE_ATTRIB_ATTR_11_ATTR_BAR2_DEFVAL +#define PCIE_ATTRIB_ATTR_11_ATTR_BAR2_SHIFT 0 +#define PCIE_ATTRIB_ATTR_11_ATTR_BAR2_MASK 0x0000FFFFU -/*For an endpoint, specifies mask/settings for Base Address Register (BAR) 2 if BAR1 is a 32-bit BAR, or the upper bits of \'7b - AR2,BAR1\'7d if BAR1 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR1 descri - tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to 00FF_FFFF. For an endpoin - , bits are defined as follows: Memory Space BAR (not upper bits of BAR1) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi - ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe - most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR3,BAR2\'7d to - . IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper - ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFF0; RP=0x00FF*/ +/* +* For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 2 if BAR1 is a 32-bit BAR, or the upper bits of \'7bBAR2,BAR1\'7d if BA + * R1 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR1 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root: This must be set to 00FF_FFF + * F. For an endpoint, bits are defined as follows: Memory Space BAR (not u + * pper bits of BAR1) [0] = Mem Space Indicator (set to 0) [2:1] = Type fie + * ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = M + * ask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to + * 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost + * 63:n bits of \'7bBAR3,BAR2\'7d to 1. IO Space BAR 0] = IO Space Indicat + * or (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits + * of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in byt + * es.; EP=0xFFF0; RP=0x00FF +*/ #undef PCIE_ATTRIB_ATTR_12_ATTR_BAR2_DEFVAL #undef PCIE_ATTRIB_ATTR_12_ATTR_BAR2_SHIFT #undef PCIE_ATTRIB_ATTR_12_ATTR_BAR2_MASK -#define PCIE_ATTRIB_ATTR_12_ATTR_BAR2_DEFVAL -#define PCIE_ATTRIB_ATTR_12_ATTR_BAR2_SHIFT 0 -#define PCIE_ATTRIB_ATTR_12_ATTR_BAR2_MASK 0x0000FFFFU +#define PCIE_ATTRIB_ATTR_12_ATTR_BAR2_DEFVAL +#define PCIE_ATTRIB_ATTR_12_ATTR_BAR2_SHIFT 0 +#define PCIE_ATTRIB_ATTR_12_ATTR_BAR2_MASK 0x0000FFFFU -/*For an endpoint, specifies mask/settings for Base Address Register (BAR) 3 if BAR2 is a 32-bit BAR, or the upper bits of \'7b - AR3,BAR2\'7d if BAR2 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR2 descri - tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: FFFF_0000 = IO Limit/Bas - Registers not implemented FFFF_F0F0 = IO Limit/Base Registers use 16-bit decode FFFF_F1F1 = IO Limit/Base Registers use 32-b - t decode For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of BAR2) [0] = Mem Space Indicator (s - t to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; - if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits - f \'7bBAR4,BAR3\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writabl - bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000*/ +/* +* For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 3 if BAR2 is a 32-bit BAR, or the upper bits of \'7bBAR3,BAR2\'7d if BA + * R2 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR2 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root, this must be set to: FFFF_00 + * 00 = IO Limit/Base Registers not implemented FFFF_F0F0 = IO Limit/Base R + * egisters use 16-bit decode FFFF_F1F1 = IO Limit/Base Registers use 32-bi + * t decode For an endpoint, bits are defined as follows: Memory Space BAR + * (not upper bits of BAR2) [0] = Mem Space Indicator (set to 0) [2:1] = Ty + * pe field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31: + * 4] = Mask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bi + * ts to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set upp + * ermost 63:n bits of \'7bBAR4,BAR3\'7d to 1. IO Space BAR 0] = IO Space I + * ndicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable + * bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size + * in bytes.; EP=0xFFFF; RP=0x0000 +*/ #undef PCIE_ATTRIB_ATTR_13_ATTR_BAR3_DEFVAL #undef PCIE_ATTRIB_ATTR_13_ATTR_BAR3_SHIFT #undef PCIE_ATTRIB_ATTR_13_ATTR_BAR3_MASK -#define PCIE_ATTRIB_ATTR_13_ATTR_BAR3_DEFVAL -#define PCIE_ATTRIB_ATTR_13_ATTR_BAR3_SHIFT 0 -#define PCIE_ATTRIB_ATTR_13_ATTR_BAR3_MASK 0x0000FFFFU +#define PCIE_ATTRIB_ATTR_13_ATTR_BAR3_DEFVAL +#define PCIE_ATTRIB_ATTR_13_ATTR_BAR3_SHIFT 0 +#define PCIE_ATTRIB_ATTR_13_ATTR_BAR3_MASK 0x0000FFFFU -/*For an endpoint, specifies mask/settings for Base Address Register (BAR) 3 if BAR2 is a 32-bit BAR, or the upper bits of \'7b - AR3,BAR2\'7d if BAR2 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR2 descri - tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: FFFF_0000 = IO Limit/Bas - Registers not implemented FFFF_F0F0 = IO Limit/Base Registers use 16-bit decode FFFF_F1F1 = IO Limit/Base Registers use 32-b - t decode For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of BAR2) [0] = Mem Space Indicator (s - t to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; - if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits - f \'7bBAR4,BAR3\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writabl - bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0xFFFF*/ +/* +* For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 3 if BAR2 is a 32-bit BAR, or the upper bits of \'7bBAR3,BAR2\'7d if BA + * R2 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR2 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root, this must be set to: FFFF_00 + * 00 = IO Limit/Base Registers not implemented FFFF_F0F0 = IO Limit/Base R + * egisters use 16-bit decode FFFF_F1F1 = IO Limit/Base Registers use 32-bi + * t decode For an endpoint, bits are defined as follows: Memory Space BAR + * (not upper bits of BAR2) [0] = Mem Space Indicator (set to 0) [2:1] = Ty + * pe field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31: + * 4] = Mask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bi + * ts to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set upp + * ermost 63:n bits of \'7bBAR4,BAR3\'7d to 1. IO Space BAR 0] = IO Space I + * ndicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable + * bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size + * in bytes.; EP=0xFFFF; RP=0xFFFF +*/ #undef PCIE_ATTRIB_ATTR_14_ATTR_BAR3_DEFVAL #undef PCIE_ATTRIB_ATTR_14_ATTR_BAR3_SHIFT #undef PCIE_ATTRIB_ATTR_14_ATTR_BAR3_MASK -#define PCIE_ATTRIB_ATTR_14_ATTR_BAR3_DEFVAL -#define PCIE_ATTRIB_ATTR_14_ATTR_BAR3_SHIFT 0 -#define PCIE_ATTRIB_ATTR_14_ATTR_BAR3_MASK 0x0000FFFFU +#define PCIE_ATTRIB_ATTR_14_ATTR_BAR3_DEFVAL +#define PCIE_ATTRIB_ATTR_14_ATTR_BAR3_SHIFT 0 +#define PCIE_ATTRIB_ATTR_14_ATTR_BAR3_MASK 0x0000FFFFU -/*For an endpoint, specifies mask/settings for Base Address Register (BAR) 4 if BAR3 is a 32-bit BAR, or the upper bits of \'7b - AR4,BAR3\'7d if BAR3 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR3 descri - tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to FFF0_FFF0. For an endpoin - , bits are defined as follows: Memory Space BAR (not upper bits of BAR3) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi - ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe - most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR5,BAR4\'7d to - . IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper - ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0x0004; RP=0xFFF0*/ +/* +* For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 4 if BAR3 is a 32-bit BAR, or the upper bits of \'7bBAR4,BAR3\'7d if BA + * R3 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR3 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root: This must be set to FFF0_FFF + * 0. For an endpoint, bits are defined as follows: Memory Space BAR (not u + * pper bits of BAR3) [0] = Mem Space Indicator (set to 0) [2:1] = Type fie + * ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = M + * ask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to + * 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost + * 63:n bits of \'7bBAR5,BAR4\'7d to 1. IO Space BAR 0] = IO Space Indicat + * or (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits + * of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in byt + * es.; EP=0x0004; RP=0xFFF0 +*/ #undef PCIE_ATTRIB_ATTR_15_ATTR_BAR4_DEFVAL #undef PCIE_ATTRIB_ATTR_15_ATTR_BAR4_SHIFT #undef PCIE_ATTRIB_ATTR_15_ATTR_BAR4_MASK -#define PCIE_ATTRIB_ATTR_15_ATTR_BAR4_DEFVAL -#define PCIE_ATTRIB_ATTR_15_ATTR_BAR4_SHIFT 0 -#define PCIE_ATTRIB_ATTR_15_ATTR_BAR4_MASK 0x0000FFFFU +#define PCIE_ATTRIB_ATTR_15_ATTR_BAR4_DEFVAL +#define PCIE_ATTRIB_ATTR_15_ATTR_BAR4_SHIFT 0 +#define PCIE_ATTRIB_ATTR_15_ATTR_BAR4_MASK 0x0000FFFFU -/*For an endpoint, specifies mask/settings for Base Address Register (BAR) 4 if BAR3 is a 32-bit BAR, or the upper bits of \'7b - AR4,BAR3\'7d if BAR3 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR3 descri - tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to FFF0_FFF0. For an endpoin - , bits are defined as follows: Memory Space BAR (not upper bits of BAR3) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi - ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe - most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR5,BAR4\'7d to - . IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper - ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFF0; RP=0xFFF0*/ +/* +* For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 4 if BAR3 is a 32-bit BAR, or the upper bits of \'7bBAR4,BAR3\'7d if BA + * R3 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR3 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root: This must be set to FFF0_FFF + * 0. For an endpoint, bits are defined as follows: Memory Space BAR (not u + * pper bits of BAR3) [0] = Mem Space Indicator (set to 0) [2:1] = Type fie + * ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = M + * ask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to + * 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost + * 63:n bits of \'7bBAR5,BAR4\'7d to 1. IO Space BAR 0] = IO Space Indicat + * or (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits + * of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in byt + * es.; EP=0xFFF0; RP=0xFFF0 +*/ #undef PCIE_ATTRIB_ATTR_16_ATTR_BAR4_DEFVAL #undef PCIE_ATTRIB_ATTR_16_ATTR_BAR4_SHIFT #undef PCIE_ATTRIB_ATTR_16_ATTR_BAR4_MASK -#define PCIE_ATTRIB_ATTR_16_ATTR_BAR4_DEFVAL -#define PCIE_ATTRIB_ATTR_16_ATTR_BAR4_SHIFT 0 -#define PCIE_ATTRIB_ATTR_16_ATTR_BAR4_MASK 0x0000FFFFU +#define PCIE_ATTRIB_ATTR_16_ATTR_BAR4_DEFVAL +#define PCIE_ATTRIB_ATTR_16_ATTR_BAR4_SHIFT 0 +#define PCIE_ATTRIB_ATTR_16_ATTR_BAR4_MASK 0x0000FFFFU -/*For an endpoint, specifies mask/settings for Base Address Register (BAR) 5 if BAR4 is a 32-bit BAR, or the upper bits of \'7b - AR5,BAR4\'7d if BAR4 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR4 descri - tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: 0000_0000 = Prefetchable - Memory Limit/Base Registers not implemented FFF0_FFF0 = 32-bit Prefetchable Memory Limit/Base implemented FFF1_FFF1 = 64-bit - refetchable Memory Limit/Base implemented For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of B - R4) [0] = Mem Space Indicator (set to 0) [2:1] = Type field (00 for 32-bit; BAR5 cannot be lower part of a 64-bit BAR) [3] = - refetchable (0 or 1) [31:4] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=memory aperture size in - ytes. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set u - permost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0xFFF1*/ +/* +* For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 5 if BAR4 is a 32-bit BAR, or the upper bits of \'7bBAR5,BAR4\'7d if BA + * R4 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR4 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root, this must be set to: 0000_00 + * 00 = Prefetchable Memory Limit/Base Registers not implemented FFF0_FFF0 + * = 32-bit Prefetchable Memory Limit/Base implemented FFF1_FFF1 = 64-bit P + * refetchable Memory Limit/Base implemented For an endpoint, bits are defi + * ned as follows: Memory Space BAR (not upper bits of BAR4) [0] = Mem Spac + * e Indicator (set to 0) [2:1] = Type field (00 for 32-bit; BAR5 cannot be + * lower part of a 64-bit BAR) [3] = Prefetchable (0 or 1) [31:4] = Mask f + * or writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=memory + * aperture size in bytes. IO Space BAR 0] = IO Space Indicator (set to 1) + * [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set up + * permost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF + * ; RP=0xFFF1 +*/ #undef PCIE_ATTRIB_ATTR_17_ATTR_BAR5_DEFVAL #undef PCIE_ATTRIB_ATTR_17_ATTR_BAR5_SHIFT #undef PCIE_ATTRIB_ATTR_17_ATTR_BAR5_MASK -#define PCIE_ATTRIB_ATTR_17_ATTR_BAR5_DEFVAL -#define PCIE_ATTRIB_ATTR_17_ATTR_BAR5_SHIFT 0 -#define PCIE_ATTRIB_ATTR_17_ATTR_BAR5_MASK 0x0000FFFFU +#define PCIE_ATTRIB_ATTR_17_ATTR_BAR5_DEFVAL +#define PCIE_ATTRIB_ATTR_17_ATTR_BAR5_SHIFT 0 +#define PCIE_ATTRIB_ATTR_17_ATTR_BAR5_MASK 0x0000FFFFU -/*For an endpoint, specifies mask/settings for Base Address Register (BAR) 5 if BAR4 is a 32-bit BAR, or the upper bits of \'7b - AR5,BAR4\'7d if BAR4 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR4 descri - tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: 0000_0000 = Prefetchable - Memory Limit/Base Registers not implemented FFF0_FFF0 = 32-bit Prefetchable Memory Limit/Base implemented FFF1_FFF1 = 64-bit - refetchable Memory Limit/Base implemented For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of B - R4) [0] = Mem Space Indicator (set to 0) [2:1] = Type field (00 for 32-bit; BAR5 cannot be lower part of a 64-bit BAR) [3] = - refetchable (0 or 1) [31:4] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=memory aperture size in - ytes. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set u - permost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0xFFF1*/ +/* +* For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 5 if BAR4 is a 32-bit BAR, or the upper bits of \'7bBAR5,BAR4\'7d if BA + * R4 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR4 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root, this must be set to: 0000_00 + * 00 = Prefetchable Memory Limit/Base Registers not implemented FFF0_FFF0 + * = 32-bit Prefetchable Memory Limit/Base implemented FFF1_FFF1 = 64-bit P + * refetchable Memory Limit/Base implemented For an endpoint, bits are defi + * ned as follows: Memory Space BAR (not upper bits of BAR4) [0] = Mem Spac + * e Indicator (set to 0) [2:1] = Type field (00 for 32-bit; BAR5 cannot be + * lower part of a 64-bit BAR) [3] = Prefetchable (0 or 1) [31:4] = Mask f + * or writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=memory + * aperture size in bytes. IO Space BAR 0] = IO Space Indicator (set to 1) + * [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set up + * permost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF + * ; RP=0xFFF1 +*/ #undef PCIE_ATTRIB_ATTR_18_ATTR_BAR5_DEFVAL #undef PCIE_ATTRIB_ATTR_18_ATTR_BAR5_SHIFT #undef PCIE_ATTRIB_ATTR_18_ATTR_BAR5_MASK -#define PCIE_ATTRIB_ATTR_18_ATTR_BAR5_DEFVAL -#define PCIE_ATTRIB_ATTR_18_ATTR_BAR5_SHIFT 0 -#define PCIE_ATTRIB_ATTR_18_ATTR_BAR5_MASK 0x0000FFFFU +#define PCIE_ATTRIB_ATTR_18_ATTR_BAR5_DEFVAL +#define PCIE_ATTRIB_ATTR_18_ATTR_BAR5_SHIFT 0 +#define PCIE_ATTRIB_ATTR_18_ATTR_BAR5_MASK 0x0000FFFFU -/*Specifies maximum payload supported. Valid settings are: 0- 128 bytes, 1- 256 bytes, 2- 512 bytes, 3- 1024 bytes. Transferred - to the Device Capabilities register. The values: 4-2048 bytes, 5- 4096 bytes are not supported; EP=0x0001; RP=0x0001*/ +/* +* Specifies maximum payload supported. Valid settings are: 0- 128 bytes, 1 + * - 256 bytes, 2- 512 bytes, 3- 1024 bytes. Transferred to the Device Capa + * bilities register. The values: 4-2048 bytes, 5- 4096 bytes are not suppo + * rted; EP=0x0001; RP=0x0001 +*/ #undef PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_DEFVAL #undef PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_SHIFT #undef PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_MASK -#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_DEFVAL 0x00002138 -#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_SHIFT 8 -#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_MASK 0x00000700U +#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_DEFVAL 0x00002138 +#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_SHIFT 8 +#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_MASK 0x00000700U -/*Endpoint L1 Acceptable Latency. Records the latency that the endpoint can withstand on transitions from L1 state to L0 (if L1 - state supported). Valid settings are: 0h less than 1us, 1h 1 to 2us, 2h 2 to 4us, 3h 4 to 8us, 4h 8 to 16us, 5h 16 to 32us, 6 - 32 to 64us, 7h more than 64us. For Endpoints only. Must be 0h for other devices.; EP=0x0007; RP=0x0000*/ +/* +* Endpoint L1 Acceptable Latency. Records the latency that the endpoint ca + * n withstand on transitions from L1 state to L0 (if L1 state supported). + * Valid settings are: 0h less than 1us, 1h 1 to 2us, 2h 2 to 4us, 3h 4 to + * 8us, 4h 8 to 16us, 5h 16 to 32us, 6h 32 to 64us, 7h more than 64us. For + * Endpoints only. Must be 0h for other devices.; EP=0x0007; RP=0x0000 +*/ #undef PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_DEFVAL #undef PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_SHIFT #undef PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_MASK -#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_DEFVAL 0x00002138 -#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_SHIFT 3 -#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_MASK 0x00000038U +#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_DEFVAL 0x00002138 +#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_SHIFT 3 +#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_MASK 0x00000038U -/*Identifies the type of device/port as follows: 0000b PCI Express Endpoint device, 0001b Legacy PCI Express Endpoint device, 0 - 00b Root Port of PCI Express Root Complex, 0101b Upstream Port of PCI Express Switch, 0110b Downstream Port of PCI Express Sw - tch, 0111b PCIE Express to PCI/PCI-X Bridge, 1000b PCI/PCI-X to PCI Express Bridge. Transferred to PCI Express Capabilities r - gister. Must be consistent with IS_SWITCH and UPSTREAM_FACING settings.; EP=0x0000; RP=0x0004*/ +/* +* Identifies the type of device/port as follows: 0000b PCI Express Endpoin + * t device, 0001b Legacy PCI Express Endpoint device, 0100b Root Port of P + * CI Express Root Complex, 0101b Upstream Port of PCI Express Switch, 0110 + * b Downstream Port of PCI Express Switch, 0111b PCIE Express to PCI/PCI-X + * Bridge, 1000b PCI/PCI-X to PCI Express Bridge. Transferred to PCI Expre + * ss Capabilities register. Must be consistent with IS_SWITCH and UPSTREAM + * _FACING settings.; EP=0x0000; RP=0x0004 +*/ #undef PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_DEFVAL #undef PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_SHIFT #undef PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_MASK -#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_DEFVAL 0x00009C02 -#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_SHIFT 4 -#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_MASK 0x000000F0U +#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_DEFVAL 0x00009C02 +#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_SHIFT 4 +#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_MASK 0x000000F0U -/*PCIe Capability's Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capab - lity.; EP=0x009C; RP=0x0000*/ +/* +* PCIe Capability's Next Capability Offset pointer to the next item in the + * capabilities list, or 00h if this is the final capability.; EP=0x009C; + * RP=0x0000 +*/ #undef PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_DEFVAL #undef PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_SHIFT #undef PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_MASK -#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_DEFVAL 0x00009C02 -#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_SHIFT 8 -#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_MASK 0x0000FF00U +#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_DEFVAL 0x00009C02 +#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_SHIFT 8 +#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_MASK 0x0000FF00U -/*Number of credits that should be advertised for Completion data received on Virtual Channel 0. The bytes advertised must be l - ss than or equal to the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0172; RP=0x00CD*/ +/* +* Number of credits that should be advertised for Completion data received + * on Virtual Channel 0. The bytes advertised must be less than or equal t + * o the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0172; RP=0x00CD +*/ #undef PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_DEFVAL #undef PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_SHIFT #undef PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_MASK -#define PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_DEFVAL -#define PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_SHIFT 0 -#define PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_MASK 0x000007FFU +#define PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_DEFVAL +#define PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_SHIFT 0 +#define PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_MASK 0x000007FFU -/*Number of credits that should be advertised for Completion headers received on Virtual Channel 0. The sum of the posted, non - osted, and completion header credits must be <= 80; EP=0x0048; RP=0x0024*/ +/* +* Number of credits that should be advertised for Completion headers recei + * ved on Virtual Channel 0. The sum of the posted, non posted, and complet + * ion header credits must be <= 80; EP=0x0048; RP=0x0024 +*/ #undef PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_DEFVAL #undef PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_SHIFT #undef PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_MASK -#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_DEFVAL 0x00000248 -#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_SHIFT 0 -#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_MASK 0x0000007FU +#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_DEFVAL 0x00000248 +#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_SHIFT 0 +#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_MASK 0x0000007FU -/*Number of credits that should be advertised for Non-Posted headers received on Virtual Channel 0. The number of non posted da - a credits advertised by the block is equal to the number of non posted header credits. The sum of the posted, non posted, and - completion header credits must be <= 80; EP=0x0004; RP=0x000C*/ +/* +* Number of credits that should be advertised for Non-Posted headers recei + * ved on Virtual Channel 0. The number of non posted data credits advertis + * ed by the block is equal to the number of non posted header credits. The + * sum of the posted, non posted, and completion header credits must be <= + * 80; EP=0x0004; RP=0x000C +*/ #undef PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_DEFVAL #undef PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_SHIFT #undef PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_MASK -#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_DEFVAL 0x00000248 -#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_SHIFT 7 -#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_MASK 0x00003F80U +#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_DEFVAL 0x00000248 +#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_SHIFT 7 +#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_MASK 0x00003F80U -/*Number of credits that should be advertised for Non-Posted data received on Virtual Channel 0. The number of non posted data - redits advertised by the block is equal to two times the number of non posted header credits if atomic operations are support - d or is equal to the number of non posted header credits if atomic operations are not supported. The bytes advertised must be - less than or equal to the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0008; RP=0x0018*/ +/* +* Number of credits that should be advertised for Non-Posted data received + * on Virtual Channel 0. The number of non posted data credits advertised + * by the block is equal to two times the number of non posted header credi + * ts if atomic operations are supported or is equal to the number of non p + * osted header credits if atomic operations are not supported. The bytes a + * dvertised must be less than or equal to the bram bytes available. See VC + * 0_RX_RAM_LIMIT; EP=0x0008; RP=0x0018 +*/ #undef PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_DEFVAL #undef PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_SHIFT #undef PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_MASK -#define PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_DEFVAL -#define PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_SHIFT 0 -#define PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_MASK 0x000007FFU +#define PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_DEFVAL +#define PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_SHIFT 0 +#define PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_MASK 0x000007FFU -/*Number of credits that should be advertised for Posted data received on Virtual Channel 0. The bytes advertised must be less - han or equal to the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0020; RP=0x00B5*/ +/* +* Number of credits that should be advertised for Posted data received on + * Virtual Channel 0. The bytes advertised must be less than or equal to th + * e bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0020; RP=0x00B5 +*/ #undef PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_DEFVAL #undef PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_SHIFT #undef PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_MASK -#define PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_DEFVAL -#define PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_SHIFT 0 -#define PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_MASK 0x000007FFU +#define PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_DEFVAL +#define PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_SHIFT 0 +#define PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_MASK 0x000007FFU -/*Not currently in use. Invert ECRC generated by block when trn_tecrc_gen_n and trn_terrfwd_n are asserted.; EP=0x0000; RP=0x00 - 0*/ +/* +* Not currently in use. Invert ECRC generated by block when trn_tecrc_gen_ + * n and trn_terrfwd_n are asserted.; EP=0x0000; RP=0x0000 +*/ #undef PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_DEFVAL #undef PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_SHIFT #undef PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_MASK -#define PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_DEFVAL 0x00007E04 -#define PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_SHIFT 15 -#define PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_MASK 0x00008000U +#define PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_DEFVAL 0x00007E04 +#define PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_SHIFT 15 +#define PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_MASK 0x00008000U -/*Enables td bit clear and ECRC trim on received TLP's FALSE == don't trim TRUE == trim.; EP=0x0001; RP=0x0001*/ +/* +* Enables td bit clear and ECRC trim on received TLP's FALSE == don't trim + * TRUE == trim.; EP=0x0001; RP=0x0001 +*/ #undef PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_DEFVAL #undef PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_SHIFT #undef PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_MASK -#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_DEFVAL 0x00007E04 -#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_SHIFT 14 -#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_MASK 0x00004000U +#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_DEFVAL 0x00007E04 +#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_SHIFT 14 +#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_MASK 0x00004000U -/*Enables ECRC check on received TLP's 0 == don't check 1 == always check 3 == check if enabled by ECRC check enable bit of AER - cap structure; EP=0x0003; RP=0x0003*/ +/* +* Enables ECRC check on received TLP's 0 == don't check 1 == always check + * 3 == check if enabled by ECRC check enable bit of AER cap structure; EP= + * 0x0003; RP=0x0003 +*/ #undef PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_DEFVAL #undef PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_SHIFT #undef PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_MASK -#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_DEFVAL 0x00007E04 -#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_SHIFT 12 -#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_MASK 0x00003000U +#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_DEFVAL 0x00007E04 +#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_SHIFT 12 +#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_MASK 0x00003000U -/*Index of last packet buffer used by TX TLM (i.e. number of buffers - 1). Calculated from max payload size supported and the n - mber of brams configured for transmit; EP=0x001C; RP=0x001C*/ +/* +* Index of last packet buffer used by TX TLM (i.e. number of buffers - 1). + * Calculated from max payload size supported and the number of brams conf + * igured for transmit; EP=0x001C; RP=0x001C +*/ #undef PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_DEFVAL #undef PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_SHIFT #undef PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_MASK -#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_DEFVAL 0x00007E04 -#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_SHIFT 7 -#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_MASK 0x00000F80U +#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_DEFVAL 0x00007E04 +#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_SHIFT 7 +#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_MASK 0x00000F80U -/*Number of credits that should be advertised for Posted headers received on Virtual Channel 0. The sum of the posted, non post - d, and completion header credits must be <= 80; EP=0x0004; RP=0x0020*/ +/* +* Number of credits that should be advertised for Posted headers received + * on Virtual Channel 0. The sum of the posted, non posted, and completion + * header credits must be <= 80; EP=0x0004; RP=0x0020 +*/ #undef PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_DEFVAL #undef PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_SHIFT #undef PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_MASK -#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_DEFVAL 0x00007E04 -#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_SHIFT 0 -#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_MASK 0x0000007FU +#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_DEFVAL 0x00007E04 +#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_SHIFT 0 +#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_MASK 0x0000007FU -/*Specifies values to be transferred to Header Type register. Bit 7 should be set to '0' indicating single-function device. Bit - 0 identifies header as Type 0 or Type 1, with '0' indicating a Type 0 header.; EP=0x0000; RP=0x0001*/ +/* +* Specifies values to be transferred to Header Type register. Bit 7 should + * be set to '0' indicating single-function device. Bit 0 identifies heade + * r as Type 0 or Type 1, with '0' indicating a Type 0 header.; EP=0x0000; + * RP=0x0001 +*/ #undef PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_DEFVAL #undef PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_SHIFT #undef PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_MASK -#define PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_DEFVAL 0x00000100 -#define PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_SHIFT 0 -#define PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_MASK 0x000000FFU +#define PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_DEFVAL 0x00000100 +#define PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_SHIFT 0 +#define PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_MASK 0x000000FFU -/*PM Capability's Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capabil - ty.; EP=0x0048; RP=0x0060*/ +/* +* PM Capability's Next Capability Offset pointer to the next item in the c + * apabilities list, or 00h if this is the final capability.; EP=0x0048; RP + * =0x0060 +*/ #undef PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_DEFVAL #undef PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_SHIFT #undef PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_MASK -#define PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_DEFVAL 0x00003D48 -#define PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_SHIFT 0 -#define PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_MASK 0x000000FFU +#define PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_DEFVAL 0x00003D48 +#define PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_SHIFT 0 +#define PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_MASK 0x000000FFU -/*MSI Per-Vector Masking Capable. The value is transferred to the MSI Control Register[8]. When set, adds Mask and Pending Dwor - to Cap structure; EP=0x0000; RP=0x0000*/ +/* +* MSI Per-Vector Masking Capable. The value is transferred to the MSI Cont + * rol Register[8]. When set, adds Mask and Pending Dword to Cap structure; + * EP=0x0000; RP=0x0000 +*/ #undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_DEFVAL #undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_SHIFT #undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_MASK -#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_DEFVAL 0x00000160 -#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_SHIFT 9 -#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_MASK 0x00000200U +#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_DEFVAL 0x00000160 +#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_SHIFT 9 +#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_MASK 0x00000200U -/*Indicates that the MSI structures exists. If this is FALSE, then the MSI structure cannot be accessed via either the link or - he management port.; EP=0x0001; RP=0x0000*/ +/* +* Indicates that the MSI structures exists. If this is FALSE, then the MSI + * structure cannot be accessed via either the link or the management port + * .; EP=0x0001; RP=0x0000 +*/ #undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_DEFVAL #undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_SHIFT #undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_MASK -#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_DEFVAL 0x00000160 -#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_SHIFT 8 -#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_MASK 0x00000100U +#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_DEFVAL 0x00000160 +#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_SHIFT 8 +#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_MASK 0x00000100U -/*MSI Capability's Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capabi - ity.; EP=0x0060; RP=0x0000*/ +/* +* MSI Capability's Next Capability Offset pointer to the next item in the + * capabilities list, or 00h if this is the final capability.; EP=0x0060; R + * P=0x0000 +*/ #undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_DEFVAL #undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_SHIFT #undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_MASK -#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_DEFVAL 0x00000160 -#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_SHIFT 0 -#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_MASK 0x000000FFU +#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_DEFVAL 0x00000160 +#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_SHIFT 0 +#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_MASK 0x000000FFU -/*Indicates that the MSI structures exists. If this is FALSE, then the MSI structure cannot be accessed via either the link or - he management port.; EP=0x0001; RP=0x0000*/ +/* +* Indicates that the MSI structures exists. If this is FALSE, then the MSI + * structure cannot be accessed via either the link or the management port + * .; EP=0x0001; RP=0x0000 +*/ #undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_DEFVAL #undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_SHIFT #undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_MASK -#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_DEFVAL 0x00000160 -#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_SHIFT 8 -#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_MASK 0x00000100U +#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_DEFVAL 0x00000160 +#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_SHIFT 8 +#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_MASK 0x00000100U -/*Maximum Link Width. Valid settings are: 000001b x1, 000010b x2, 000100b x4, 001000b x8.; EP=0x0004; RP=0x0004*/ +/* +* Maximum Link Width. Valid settings are: 000001b x1, 000010b x2, 000100b + * x4, 001000b x8.; EP=0x0004; RP=0x0004 +*/ #undef PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_DEFVAL #undef PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_SHIFT #undef PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_MASK -#define PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_DEFVAL 0x00000104 -#define PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_SHIFT 0 -#define PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_MASK 0x0000003FU +#define PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_DEFVAL 0x00000104 +#define PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_SHIFT 0 +#define PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_MASK 0x0000003FU -/*Used by LTSSM to set Maximum Link Width. Valid settings are: 000001b [x1], 000010b [x2], 000100b [x4], 001000b [x8].; EP=0x00 - 4; RP=0x0004*/ +/* +* Used by LTSSM to set Maximum Link Width. Valid settings are: 000001b [x1 + * ], 000010b [x2], 000100b [x4], 001000b [x8].; EP=0x0004; RP=0x0004 +*/ #undef PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_DEFVAL #undef PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_SHIFT #undef PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_MASK -#define PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_DEFVAL 0x00000104 -#define PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_SHIFT 6 -#define PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_MASK 0x00000FC0U +#define PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_DEFVAL 0x00000104 +#define PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_SHIFT 6 +#define PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_MASK 0x00000FC0U -/*TRUE specifies upstream-facing port. FALSE specifies downstream-facing port.; EP=0x0001; RP=0x0000*/ +/* +* TRUE specifies upstream-facing port. FALSE specifies downstream-facing p + * ort.; EP=0x0001; RP=0x0000 +*/ #undef PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_DEFVAL #undef PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_SHIFT #undef PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_MASK -#define PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_DEFVAL 0x000000F0 -#define PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_SHIFT 6 -#define PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_MASK 0x00000040U +#define PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_DEFVAL 0x000000F0 +#define PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_SHIFT 6 +#define PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_MASK 0x00000040U -/*Enable the routing of message TLPs to the user through the TRN RX interface. A bit value of 1 enables routing of the message - LP to the user. Messages are always decoded by the message decoder. Bit 0 - ERR COR, Bit 1 - ERR NONFATAL, Bit 2 - ERR FATAL, - Bit 3 - INTA Bit 4 - INTB, Bit 5 - INTC, Bit 6 - INTD, Bit 7 PM_PME, Bit 8 - PME_TO_ACK, Bit 9 - unlock, Bit 10 PME_Turn_Off; - EP=0x0000; RP=0x07FF*/ +/* +* Enable the routing of message TLPs to the user through the TRN RX interf + * ace. A bit value of 1 enables routing of the message TLP to the user. Me + * ssages are always decoded by the message decoder. Bit 0 - ERR COR, Bit 1 + * - ERR NONFATAL, Bit 2 - ERR FATAL, Bit 3 - INTA Bit 4 - INTB, Bit 5 - I + * NTC, Bit 6 - INTD, Bit 7 PM_PME, Bit 8 - PME_TO_ACK, Bit 9 - unlock, Bit + * 10 PME_Turn_Off; EP=0x0000; RP=0x07FF +*/ #undef PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_DEFVAL #undef PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_SHIFT #undef PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_MASK -#define PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_DEFVAL 0x00000000 -#define PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_SHIFT 5 -#define PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_MASK 0x0000FFE0U +#define PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_DEFVAL 0x00000000 +#define PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_SHIFT 5 +#define PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_MASK 0x0000FFE0U -/*Disable BAR filtering. Does not change the behavior of the bar hit outputs; EP=0x0000; RP=0x0001*/ +/* +* Disable BAR filtering. Does not change the behavior of the bar hit outpu + * ts; EP=0x0000; RP=0x0001 +*/ #undef PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_DEFVAL #undef PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_SHIFT #undef PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_MASK -#define PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_DEFVAL 0x00000000 -#define PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_SHIFT 1 -#define PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_MASK 0x00000002U +#define PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_DEFVAL 0x00000000 +#define PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_SHIFT 1 +#define PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_MASK 0x00000002U -/*Link Bandwidth notification capability. Indicates support for the link bandwidth notification status and interrupt mechanism. - Required for Root.; EP=0x0000; RP=0x0001*/ +/* +* Link Bandwidth notification capability. Indicates support for the link b + * andwidth notification status and interrupt mechanism. Required for Root. + * ; EP=0x0000; RP=0x0001 +*/ #undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_DEFVAL #undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_SHIFT #undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_MASK -#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_DEFVAL 0x000009FF -#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_SHIFT 9 -#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_MASK 0x00000200U +#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_DEFVAL 0x000009FF +#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_SHIFT 9 +#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_MASK 0x00000200U -/*Sets the ASPM Optionality Compliance bit, to comply with the 2.1 ASPM Optionality ECN. Transferred to the Link Capabilities r - gister.; EP=0x0001; RP=0x0001*/ +/* +* Sets the ASPM Optionality Compliance bit, to comply with the 2.1 ASPM Op + * tionality ECN. Transferred to the Link Capabilities register.; EP=0x0001 + * ; RP=0x0001 +*/ #undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_DEFVAL #undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_SHIFT #undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_MASK -#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_DEFVAL 0x000009FF -#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_SHIFT 14 -#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_MASK 0x00004000U +#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_DEFVAL 0x000009FF +#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_SHIFT 14 +#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_MASK 0x00004000U -/*Enables the Replay Timer to use the user-defined LL_REPLAY_TIMEOUT value (or combined with the built-in value, depending on L - _REPLAY_TIMEOUT_FUNC). If FALSE, the built-in value is used.; EP=0x0000; RP=0x0000*/ +/* +* Enables the Replay Timer to use the user-defined LL_REPLAY_TIMEOUT value + * (or combined with the built-in value, depending on LL_REPLAY_TIMEOUT_FU + * NC). If FALSE, the built-in value is used.; EP=0x0000; RP=0x0000 +*/ #undef PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_DEFVAL #undef PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_SHIFT #undef PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_MASK -#define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_DEFVAL 0x00000000 -#define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_SHIFT 15 -#define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_MASK 0x00008000U +#define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_DEFVAL 0x00000000 +#define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_SHIFT 15 +#define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_MASK 0x00008000U -/*Sets a user-defined timeout for the Replay Timer to force cause the retransmission of unacknowledged TLPs; refer to LL_REPLAY - TIMEOUT_EN and LL_REPLAY_TIMEOUT_FUNC to see how this value is used. The unit for this attribute is in symbol times, which is - 4ns at GEN1 speeds and 2ns at GEN2.; EP=0x0000; RP=0x0000*/ +/* +* Sets a user-defined timeout for the Replay Timer to force cause the retr + * ansmission of unacknowledged TLPs; refer to LL_REPLAY_TIMEOUT_EN and LL_ + * REPLAY_TIMEOUT_FUNC to see how this value is used. The unit for this att + * ribute is in symbol times, which is 4ns at GEN1 speeds and 2ns at GEN2.; + * EP=0x0000; RP=0x0000 +*/ #undef PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_DEFVAL #undef PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_SHIFT #undef PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_MASK -#define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_DEFVAL 0x00000000 -#define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_SHIFT 0 -#define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_MASK 0x00007FFFU +#define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_DEFVAL 0x00000000 +#define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_SHIFT 0 +#define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_MASK 0x00007FFFU -/*Device ID for the the PCIe Cap Structure Device ID field*/ +/* +* Device ID for the the PCIe Cap Structure Device ID field +*/ #undef PCIE_ATTRIB_ID_CFG_DEV_ID_DEFVAL #undef PCIE_ATTRIB_ID_CFG_DEV_ID_SHIFT #undef PCIE_ATTRIB_ID_CFG_DEV_ID_MASK -#define PCIE_ATTRIB_ID_CFG_DEV_ID_DEFVAL 0x10EE7024 -#define PCIE_ATTRIB_ID_CFG_DEV_ID_SHIFT 0 -#define PCIE_ATTRIB_ID_CFG_DEV_ID_MASK 0x0000FFFFU +#define PCIE_ATTRIB_ID_CFG_DEV_ID_DEFVAL 0x10EE7024 +#define PCIE_ATTRIB_ID_CFG_DEV_ID_SHIFT 0 +#define PCIE_ATTRIB_ID_CFG_DEV_ID_MASK 0x0000FFFFU -/*Vendor ID for the PCIe Cap Structure Vendor ID field*/ +/* +* Vendor ID for the PCIe Cap Structure Vendor ID field +*/ #undef PCIE_ATTRIB_ID_CFG_VEND_ID_DEFVAL #undef PCIE_ATTRIB_ID_CFG_VEND_ID_SHIFT #undef PCIE_ATTRIB_ID_CFG_VEND_ID_MASK -#define PCIE_ATTRIB_ID_CFG_VEND_ID_DEFVAL 0x10EE7024 -#define PCIE_ATTRIB_ID_CFG_VEND_ID_SHIFT 16 -#define PCIE_ATTRIB_ID_CFG_VEND_ID_MASK 0xFFFF0000U +#define PCIE_ATTRIB_ID_CFG_VEND_ID_DEFVAL 0x10EE7024 +#define PCIE_ATTRIB_ID_CFG_VEND_ID_SHIFT 16 +#define PCIE_ATTRIB_ID_CFG_VEND_ID_MASK 0xFFFF0000U -/*Subsystem ID for the the PCIe Cap Structure Subsystem ID field*/ +/* +* Subsystem ID for the the PCIe Cap Structure Subsystem ID field +*/ #undef PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_DEFVAL #undef PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_SHIFT #undef PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_MASK -#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_DEFVAL 0x10EE0007 -#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_SHIFT 0 -#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_MASK 0x0000FFFFU +#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_DEFVAL 0x10EE0007 +#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_SHIFT 0 +#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_MASK 0x0000FFFFU -/*Subsystem Vendor ID for the PCIe Cap Structure Subsystem Vendor ID field*/ +/* +* Subsystem Vendor ID for the PCIe Cap Structure Subsystem Vendor ID field +*/ #undef PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_DEFVAL #undef PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_SHIFT #undef PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_MASK -#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_DEFVAL 0x10EE0007 -#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_SHIFT 16 -#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_MASK 0xFFFF0000U +#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_DEFVAL 0x10EE0007 +#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_SHIFT 16 +#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_MASK 0xFFFF0000U -/*Revision ID for the the PCIe Cap Structure*/ +/* +* Revision ID for the the PCIe Cap Structure +*/ #undef PCIE_ATTRIB_REV_ID_CFG_REV_ID_DEFVAL #undef PCIE_ATTRIB_REV_ID_CFG_REV_ID_SHIFT #undef PCIE_ATTRIB_REV_ID_CFG_REV_ID_MASK -#define PCIE_ATTRIB_REV_ID_CFG_REV_ID_DEFVAL -#define PCIE_ATTRIB_REV_ID_CFG_REV_ID_SHIFT 0 -#define PCIE_ATTRIB_REV_ID_CFG_REV_ID_MASK 0x000000FFU +#define PCIE_ATTRIB_REV_ID_CFG_REV_ID_DEFVAL +#define PCIE_ATTRIB_REV_ID_CFG_REV_ID_SHIFT 0 +#define PCIE_ATTRIB_REV_ID_CFG_REV_ID_MASK 0x000000FFU -/*Code identifying basic function, subclass and applicable programming interface. Transferred to the Class Code register.; EP=0 - 8000; RP=0x8000*/ +/* +* Code identifying basic function, subclass and applicable programming int + * erface. Transferred to the Class Code register.; EP=0x8000; RP=0x8000 +*/ #undef PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_DEFVAL #undef PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_SHIFT #undef PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_MASK -#define PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_DEFVAL -#define PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_SHIFT 0 -#define PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_MASK 0x0000FFFFU +#define PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_DEFVAL +#define PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_SHIFT 0 +#define PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_MASK 0x0000FFFFU -/*Code identifying basic function, subclass and applicable programming interface. Transferred to the Class Code register.; EP=0 - 0005; RP=0x0006*/ +/* +* Code identifying basic function, subclass and applicable programming int + * erface. Transferred to the Class Code register.; EP=0x0005; RP=0x0006 +*/ #undef PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_DEFVAL #undef PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_SHIFT #undef PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_MASK -#define PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_DEFVAL 0x00000905 -#define PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_SHIFT 0 -#define PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_MASK 0x000000FFU +#define PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_DEFVAL 0x00000905 +#define PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_SHIFT 0 +#define PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_MASK 0x000000FFU -/*INTX Interrupt Generation Capable. If FALSE, this will cause Command[10] to be hardwired to 0.; EP=0x0001; RP=0x0001*/ +/* +* INTX Interrupt Generation Capable. If FALSE, this will cause Command[10] + * to be hardwired to 0.; EP=0x0001; RP=0x0001 +*/ #undef PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_DEFVAL #undef PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_SHIFT #undef PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_MASK -#define PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_DEFVAL 0x00000905 -#define PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_SHIFT 8 -#define PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_MASK 0x00000100U +#define PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_DEFVAL 0x00000905 +#define PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_SHIFT 8 +#define PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_MASK 0x00000100U -/*Indicates that the AER structures exists. If this is FALSE, then the AER structure cannot be accessed via either the link or - he management port, and AER will be considered to not be present for error management tasks (such as what types of error mess - ges are sent if an error is detected).; EP=0x0001; RP=0x0001*/ +/* +* Indicates that the AER structures exists. If this is FALSE, then the AER + * structure cannot be accessed via either the link or the management port + * , and AER will be considered to not be present for error management task + * s (such as what types of error messages are sent if an error is detected + * ).; EP=0x0001; RP=0x0001 +*/ #undef PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_DEFVAL #undef PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_SHIFT #undef PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_MASK -#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_DEFVAL 0x00001000 -#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_SHIFT 12 -#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_MASK 0x00001000U +#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_DEFVAL 0x00001000 +#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_SHIFT 12 +#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_MASK 0x00001000U -/*Indicates that the AER structures exists. If this is FALSE, then the AER structure cannot be accessed via either the link or - he management port, and AER will be considered to not be present for error management tasks (such as what types of error mess - ges are sent if an error is detected).; EP=0x0001; RP=0x0001*/ +/* +* Indicates that the AER structures exists. If this is FALSE, then the AER + * structure cannot be accessed via either the link or the management port + * , and AER will be considered to not be present for error management task + * s (such as what types of error messages are sent if an error is detected + * ).; EP=0x0001; RP=0x0001 +*/ #undef PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_DEFVAL #undef PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_SHIFT #undef PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_MASK -#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_DEFVAL 0x00001000 -#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_SHIFT 12 -#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_MASK 0x00001000U +#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_DEFVAL 0x00001000 +#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_SHIFT 12 +#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_MASK 0x00001000U -/*VSEC's Next Capability Offset pointer to the next item in the capabilities list, or 000h if this is the final capability.; EP - 0x0140; RP=0x0140*/ +/* +* VSEC's Next Capability Offset pointer to the next item in the capabiliti + * es list, or 000h if this is the final capability.; EP=0x0140; RP=0x0140 +*/ #undef PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_DEFVAL #undef PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_SHIFT #undef PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_MASK -#define PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_DEFVAL 0x00002281 -#define PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_SHIFT 1 -#define PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_MASK 0x00001FFEU +#define PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_DEFVAL 0x00002281 +#define PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_SHIFT 1 +#define PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_MASK 0x00001FFEU -/*CRS SW Visibility. Indicates RC can return CRS to SW. Transferred to the Root Capabilities register.; EP=0x0000; RP=0x0000*/ +/* +* CRS SW Visibility. Indicates RC can return CRS to SW. Transferred to the + * Root Capabilities register.; EP=0x0000; RP=0x0000 +*/ #undef PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_DEFVAL #undef PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_SHIFT #undef PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_MASK -#define PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_DEFVAL 0x00000000 -#define PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_SHIFT 5 -#define PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_MASK 0x00000020U +#define PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_DEFVAL 0x00000000 +#define PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_SHIFT 5 +#define PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_MASK 0x00000020U -/*Indicates that the MSIX structures exists. If this is FALSE, then the MSIX structure cannot be accessed via either the link o - the management port.; EP=0x0001; RP=0x0000*/ +/* +* Indicates that the MSIX structures exists. If this is FALSE, then the MS + * IX structure cannot be accessed via either the link or the management po + * rt.; EP=0x0001; RP=0x0000 +*/ #undef PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_DEFVAL #undef PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_SHIFT #undef PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_MASK -#define PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_DEFVAL 0x00000100 -#define PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_SHIFT 8 -#define PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_MASK 0x00000100U +#define PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_DEFVAL 0x00000100 +#define PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_SHIFT 8 +#define PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_MASK 0x00000100U -/*MSI-X Table Size. This value is transferred to the MSI-X Message Control[10:0] field. Set to 0 if MSI-X is not enabled. Note - hat the core does not implement the table; that must be implemented in user logic.; EP=0x0003; RP=0x0000*/ +/* +* MSI-X Table Size. This value is transferred to the MSI-X Message Control + * [10:0] field. Set to 0 if MSI-X is not enabled. Note that the core does + * not implement the table; that must be implemented in user logic.; EP=0x0 + * 003; RP=0x0000 +*/ #undef PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_DEFVAL #undef PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_SHIFT #undef PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_MASK -#define PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_DEFVAL -#define PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_SHIFT 0 -#define PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_MASK 0x000007FFU +#define PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_DEFVAL +#define PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_SHIFT 0 +#define PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_MASK 0x000007FFU -/*MSI-X Table Offset. This value is transferred to the MSI-X Table Offset field. Set to 0 if MSI-X is not enabled.; EP=0x0001; - P=0x0000*/ +/* +* MSI-X Table Offset. This value is transferred to the MSI-X Table Offset + * field. Set to 0 if MSI-X is not enabled.; EP=0x0001; RP=0x0000 +*/ #undef PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_DEFVAL #undef PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_SHIFT #undef PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_MASK -#define PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_DEFVAL -#define PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_SHIFT 0 -#define PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_MASK 0x0000FFFFU +#define PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_DEFVAL +#define PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_SHIFT 0 +#define PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_MASK 0x0000FFFFU -/*MSI-X Table Offset. This value is transferred to the MSI-X Table Offset field. Set to 0 if MSI-X is not enabled.; EP=0x0000; - P=0x0000*/ +/* +* MSI-X Table Offset. This value is transferred to the MSI-X Table Offset + * field. Set to 0 if MSI-X is not enabled.; EP=0x0000; RP=0x0000 +*/ #undef PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_DEFVAL #undef PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_SHIFT #undef PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_MASK -#define PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_DEFVAL -#define PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_SHIFT 0 -#define PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_MASK 0x00001FFFU +#define PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_DEFVAL +#define PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_SHIFT 0 +#define PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_MASK 0x00001FFFU -/*MSI-X Pending Bit Array Offset This value is transferred to the MSI-X PBA Offset field. Set to 0 if MSI-X is not enabled.; EP - 0x0001; RP=0x0000*/ +/* +* MSI-X Pending Bit Array Offset This value is transferred to the MSI-X PB + * A Offset field. Set to 0 if MSI-X is not enabled.; EP=0x0001; RP=0x0000 +*/ #undef PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_DEFVAL #undef PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_SHIFT #undef PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_MASK -#define PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_DEFVAL -#define PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_SHIFT 0 -#define PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_MASK 0x0000FFFFU +#define PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_DEFVAL +#define PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_SHIFT 0 +#define PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_MASK 0x0000FFFFU -/*MSI-X Pending Bit Array Offset This value is transferred to the MSI-X PBA Offset field. Set to 0 if MSI-X is not enabled.; EP - 0x1000; RP=0x0000*/ +/* +* MSI-X Pending Bit Array Offset This value is transferred to the MSI-X PB + * A Offset field. Set to 0 if MSI-X is not enabled.; EP=0x1000; RP=0x0000 +*/ #undef PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_DEFVAL #undef PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_SHIFT #undef PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_MASK -#define PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_DEFVAL 0x00008000 -#define PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_SHIFT 3 -#define PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_MASK 0x0000FFF8U +#define PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_DEFVAL 0x00008000 +#define PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_SHIFT 3 +#define PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_MASK 0x0000FFF8U -/*DT837748 Enable*/ +/* +* DT837748 Enable +*/ #undef PCIE_ATTRIB_CB_CB1_DEFVAL #undef PCIE_ATTRIB_CB_CB1_SHIFT #undef PCIE_ATTRIB_CB_CB1_MASK -#define PCIE_ATTRIB_CB_CB1_DEFVAL 0x00000001 -#define PCIE_ATTRIB_CB_CB1_SHIFT 1 -#define PCIE_ATTRIB_CB_CB1_MASK 0x00000002U +#define PCIE_ATTRIB_CB_CB1_DEFVAL 0x00000001 +#define PCIE_ATTRIB_CB_CB1_SHIFT 1 +#define PCIE_ATTRIB_CB_CB1_MASK 0x00000002U -/*Active State PM Support. Indicates the level of active state power management supported by the selected PCI Express Link, enc - ded as follows: 0 Reserved, 1 L0s entry supported, 2 Reserved, 3 L0s and L1 entry supported.; EP=0x0001; RP=0x0001*/ +/* +* Active State PM Support. Indicates the level of active state power manag + * ement supported by the selected PCI Express Link, encoded as follows: 0 + * Reserved, 1 L0s entry supported, 2 Reserved, 3 L0s and L1 entry supporte + * d.; EP=0x0001; RP=0x0001 +*/ #undef PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_DEFVAL #undef PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_SHIFT #undef PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_MASK -#define PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_DEFVAL 0x00001FFD -#define PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_SHIFT 12 -#define PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_MASK 0x00003000U +#define PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_DEFVAL 0x00001FFD +#define PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_SHIFT 12 +#define PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_MASK 0x00003000U -/*PCIE control block level reset*/ +/* +* PCIE control block level reset +*/ #undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL #undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT #undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK -#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL 0x000F9FFE -#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT 17 -#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK 0x00020000U +#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT 17 +#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK 0x00020000U -/*Status Read value of PLL Lock*/ +/* +* Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW] +*/ +#undef GPIO_MASK_DATA_1_LSW_MASK_1_LSW_DEFVAL +#undef GPIO_MASK_DATA_1_LSW_MASK_1_LSW_SHIFT +#undef GPIO_MASK_DATA_1_LSW_MASK_1_LSW_MASK +#define GPIO_MASK_DATA_1_LSW_MASK_1_LSW_DEFVAL 0x00000000 +#define GPIO_MASK_DATA_1_LSW_MASK_1_LSW_SHIFT 16 +#define GPIO_MASK_DATA_1_LSW_MASK_1_LSW_MASK 0xFFFF0000U + +/* +* Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW] +*/ +#undef GPIO_MASK_DATA_1_LSW_DATA_1_LSW_DEFVAL +#undef GPIO_MASK_DATA_1_LSW_DATA_1_LSW_SHIFT +#undef GPIO_MASK_DATA_1_LSW_DATA_1_LSW_MASK +#define GPIO_MASK_DATA_1_LSW_DATA_1_LSW_DEFVAL 0x00000000 +#define GPIO_MASK_DATA_1_LSW_DATA_1_LSW_SHIFT 0 +#define GPIO_MASK_DATA_1_LSW_DATA_1_LSW_MASK 0x0000FFFFU + +/* +* Status Read value of PLL Lock +*/ #undef SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL #undef SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT #undef SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK -#define SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL 0x00000001 -#define SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT 4 -#define SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK 0x00000010U +#define SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL 0x00000001 +#define SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT 4 +#define SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK 0x00000010U #define SERDES_L0_PLL_STATUS_READ_1_OFFSET 0XFD4023E4 -/*Status Read value of PLL Lock*/ +/* +* Status Read value of PLL Lock +*/ #undef SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL #undef SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT #undef SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK -#define SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL 0x00000001 -#define SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT 4 -#define SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK 0x00000010U +#define SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL 0x00000001 +#define SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT 4 +#define SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK 0x00000010U #define SERDES_L1_PLL_STATUS_READ_1_OFFSET 0XFD4063E4 -/*Status Read value of PLL Lock*/ +/* +* Status Read value of PLL Lock +*/ #undef SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL #undef SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT #undef SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK -#define SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL 0x00000001 -#define SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT 4 -#define SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK 0x00000010U +#define SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL 0x00000001 +#define SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT 4 +#define SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK 0x00000010U #define SERDES_L2_PLL_STATUS_READ_1_OFFSET 0XFD40A3E4 -/*Status Read value of PLL Lock*/ +/* +* Status Read value of PLL Lock +*/ #undef SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL #undef SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT #undef SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK -#define SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL 0x00000001 -#define SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT 4 -#define SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK 0x00000010U +#define SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL 0x00000001 +#define SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT 4 +#define SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK 0x00000010U #define SERDES_L3_PLL_STATUS_READ_1_OFFSET 0XFD40E3E4 -/*CIBGMN: COMINIT Burst Gap Minimum.*/ +/* +* CIBGMN: COMINIT Burst Gap Minimum. +*/ #undef SATA_AHCI_VENDOR_PP2C_CIBGMN_DEFVAL #undef SATA_AHCI_VENDOR_PP2C_CIBGMN_SHIFT #undef SATA_AHCI_VENDOR_PP2C_CIBGMN_MASK -#define SATA_AHCI_VENDOR_PP2C_CIBGMN_DEFVAL 0x28184D1B -#define SATA_AHCI_VENDOR_PP2C_CIBGMN_SHIFT 0 -#define SATA_AHCI_VENDOR_PP2C_CIBGMN_MASK 0x000000FFU +#define SATA_AHCI_VENDOR_PP2C_CIBGMN_DEFVAL 0x28184D1B +#define SATA_AHCI_VENDOR_PP2C_CIBGMN_SHIFT 0 +#define SATA_AHCI_VENDOR_PP2C_CIBGMN_MASK 0x000000FFU -/*CIBGMX: COMINIT Burst Gap Maximum.*/ +/* +* CIBGMX: COMINIT Burst Gap Maximum. +*/ #undef SATA_AHCI_VENDOR_PP2C_CIBGMX_DEFVAL #undef SATA_AHCI_VENDOR_PP2C_CIBGMX_SHIFT #undef SATA_AHCI_VENDOR_PP2C_CIBGMX_MASK -#define SATA_AHCI_VENDOR_PP2C_CIBGMX_DEFVAL 0x28184D1B -#define SATA_AHCI_VENDOR_PP2C_CIBGMX_SHIFT 8 -#define SATA_AHCI_VENDOR_PP2C_CIBGMX_MASK 0x0000FF00U +#define SATA_AHCI_VENDOR_PP2C_CIBGMX_DEFVAL 0x28184D1B +#define SATA_AHCI_VENDOR_PP2C_CIBGMX_SHIFT 8 +#define SATA_AHCI_VENDOR_PP2C_CIBGMX_MASK 0x0000FF00U -/*CIBGN: COMINIT Burst Gap Nominal.*/ +/* +* CIBGN: COMINIT Burst Gap Nominal. +*/ #undef SATA_AHCI_VENDOR_PP2C_CIBGN_DEFVAL #undef SATA_AHCI_VENDOR_PP2C_CIBGN_SHIFT #undef SATA_AHCI_VENDOR_PP2C_CIBGN_MASK -#define SATA_AHCI_VENDOR_PP2C_CIBGN_DEFVAL 0x28184D1B -#define SATA_AHCI_VENDOR_PP2C_CIBGN_SHIFT 16 -#define SATA_AHCI_VENDOR_PP2C_CIBGN_MASK 0x00FF0000U +#define SATA_AHCI_VENDOR_PP2C_CIBGN_DEFVAL 0x28184D1B +#define SATA_AHCI_VENDOR_PP2C_CIBGN_SHIFT 16 +#define SATA_AHCI_VENDOR_PP2C_CIBGN_MASK 0x00FF0000U -/*CINMP: COMINIT Negate Minimum Period.*/ +/* +* CINMP: COMINIT Negate Minimum Period. +*/ #undef SATA_AHCI_VENDOR_PP2C_CINMP_DEFVAL #undef SATA_AHCI_VENDOR_PP2C_CINMP_SHIFT #undef SATA_AHCI_VENDOR_PP2C_CINMP_MASK -#define SATA_AHCI_VENDOR_PP2C_CINMP_DEFVAL 0x28184D1B -#define SATA_AHCI_VENDOR_PP2C_CINMP_SHIFT 24 -#define SATA_AHCI_VENDOR_PP2C_CINMP_MASK 0xFF000000U +#define SATA_AHCI_VENDOR_PP2C_CINMP_DEFVAL 0x28184D1B +#define SATA_AHCI_VENDOR_PP2C_CINMP_SHIFT 24 +#define SATA_AHCI_VENDOR_PP2C_CINMP_MASK 0xFF000000U -/*CWBGMN: COMWAKE Burst Gap Minimum.*/ +/* +* CWBGMN: COMWAKE Burst Gap Minimum. +*/ #undef SATA_AHCI_VENDOR_PP3C_CWBGMN_DEFVAL #undef SATA_AHCI_VENDOR_PP3C_CWBGMN_SHIFT #undef SATA_AHCI_VENDOR_PP3C_CWBGMN_MASK -#define SATA_AHCI_VENDOR_PP3C_CWBGMN_DEFVAL 0x0E081906 -#define SATA_AHCI_VENDOR_PP3C_CWBGMN_SHIFT 0 -#define SATA_AHCI_VENDOR_PP3C_CWBGMN_MASK 0x000000FFU +#define SATA_AHCI_VENDOR_PP3C_CWBGMN_DEFVAL 0x0E081906 +#define SATA_AHCI_VENDOR_PP3C_CWBGMN_SHIFT 0 +#define SATA_AHCI_VENDOR_PP3C_CWBGMN_MASK 0x000000FFU -/*CWBGMX: COMWAKE Burst Gap Maximum.*/ +/* +* CWBGMX: COMWAKE Burst Gap Maximum. +*/ #undef SATA_AHCI_VENDOR_PP3C_CWBGMX_DEFVAL #undef SATA_AHCI_VENDOR_PP3C_CWBGMX_SHIFT #undef SATA_AHCI_VENDOR_PP3C_CWBGMX_MASK -#define SATA_AHCI_VENDOR_PP3C_CWBGMX_DEFVAL 0x0E081906 -#define SATA_AHCI_VENDOR_PP3C_CWBGMX_SHIFT 8 -#define SATA_AHCI_VENDOR_PP3C_CWBGMX_MASK 0x0000FF00U +#define SATA_AHCI_VENDOR_PP3C_CWBGMX_DEFVAL 0x0E081906 +#define SATA_AHCI_VENDOR_PP3C_CWBGMX_SHIFT 8 +#define SATA_AHCI_VENDOR_PP3C_CWBGMX_MASK 0x0000FF00U -/*CWBGN: COMWAKE Burst Gap Nominal.*/ +/* +* CWBGN: COMWAKE Burst Gap Nominal. +*/ #undef SATA_AHCI_VENDOR_PP3C_CWBGN_DEFVAL #undef SATA_AHCI_VENDOR_PP3C_CWBGN_SHIFT #undef SATA_AHCI_VENDOR_PP3C_CWBGN_MASK -#define SATA_AHCI_VENDOR_PP3C_CWBGN_DEFVAL 0x0E081906 -#define SATA_AHCI_VENDOR_PP3C_CWBGN_SHIFT 16 -#define SATA_AHCI_VENDOR_PP3C_CWBGN_MASK 0x00FF0000U +#define SATA_AHCI_VENDOR_PP3C_CWBGN_DEFVAL 0x0E081906 +#define SATA_AHCI_VENDOR_PP3C_CWBGN_SHIFT 16 +#define SATA_AHCI_VENDOR_PP3C_CWBGN_MASK 0x00FF0000U -/*CWNMP: COMWAKE Negate Minimum Period.*/ +/* +* CWNMP: COMWAKE Negate Minimum Period. +*/ #undef SATA_AHCI_VENDOR_PP3C_CWNMP_DEFVAL #undef SATA_AHCI_VENDOR_PP3C_CWNMP_SHIFT #undef SATA_AHCI_VENDOR_PP3C_CWNMP_MASK -#define SATA_AHCI_VENDOR_PP3C_CWNMP_DEFVAL 0x0E081906 -#define SATA_AHCI_VENDOR_PP3C_CWNMP_SHIFT 24 -#define SATA_AHCI_VENDOR_PP3C_CWNMP_MASK 0xFF000000U +#define SATA_AHCI_VENDOR_PP3C_CWNMP_DEFVAL 0x0E081906 +#define SATA_AHCI_VENDOR_PP3C_CWNMP_SHIFT 24 +#define SATA_AHCI_VENDOR_PP3C_CWNMP_MASK 0xFF000000U -/*BMX: COM Burst Maximum.*/ +/* +* BMX: COM Burst Maximum. +*/ #undef SATA_AHCI_VENDOR_PP4C_BMX_DEFVAL #undef SATA_AHCI_VENDOR_PP4C_BMX_SHIFT #undef SATA_AHCI_VENDOR_PP4C_BMX_MASK -#define SATA_AHCI_VENDOR_PP4C_BMX_DEFVAL 0x064A0813 -#define SATA_AHCI_VENDOR_PP4C_BMX_SHIFT 0 -#define SATA_AHCI_VENDOR_PP4C_BMX_MASK 0x000000FFU +#define SATA_AHCI_VENDOR_PP4C_BMX_DEFVAL 0x064A0813 +#define SATA_AHCI_VENDOR_PP4C_BMX_SHIFT 0 +#define SATA_AHCI_VENDOR_PP4C_BMX_MASK 0x000000FFU -/*BNM: COM Burst Nominal.*/ +/* +* BNM: COM Burst Nominal. +*/ #undef SATA_AHCI_VENDOR_PP4C_BNM_DEFVAL #undef SATA_AHCI_VENDOR_PP4C_BNM_SHIFT #undef SATA_AHCI_VENDOR_PP4C_BNM_MASK -#define SATA_AHCI_VENDOR_PP4C_BNM_DEFVAL 0x064A0813 -#define SATA_AHCI_VENDOR_PP4C_BNM_SHIFT 8 -#define SATA_AHCI_VENDOR_PP4C_BNM_MASK 0x0000FF00U +#define SATA_AHCI_VENDOR_PP4C_BNM_DEFVAL 0x064A0813 +#define SATA_AHCI_VENDOR_PP4C_BNM_SHIFT 8 +#define SATA_AHCI_VENDOR_PP4C_BNM_MASK 0x0000FF00U -/*SFD: Signal Failure Detection, if the signal detection de-asserts for a time greater than this then the OOB detector will det - rmine this is a line idle and cause the PhyInit state machine to exit the Phy Ready State. A value of zero disables the Signa - Failure Detector. The value is based on the OOB Detector Clock typically (PMCLK Clock Period) * SFD giving a nominal time of - 500ns based on a 150MHz PMCLK.*/ +/* +* SFD: Signal Failure Detection, if the signal detection de-asserts for a + * time greater than this then the OOB detector will determine this is a li + * ne idle and cause the PhyInit state machine to exit the Phy Ready State. + * A value of zero disables the Signal Failure Detector. The value is base + * d on the OOB Detector Clock typically (PMCLK Clock Period) * SFD giving + * a nominal time of 500ns based on a 150MHz PMCLK. +*/ #undef SATA_AHCI_VENDOR_PP4C_SFD_DEFVAL #undef SATA_AHCI_VENDOR_PP4C_SFD_SHIFT #undef SATA_AHCI_VENDOR_PP4C_SFD_MASK -#define SATA_AHCI_VENDOR_PP4C_SFD_DEFVAL 0x064A0813 -#define SATA_AHCI_VENDOR_PP4C_SFD_SHIFT 16 -#define SATA_AHCI_VENDOR_PP4C_SFD_MASK 0x00FF0000U +#define SATA_AHCI_VENDOR_PP4C_SFD_DEFVAL 0x064A0813 +#define SATA_AHCI_VENDOR_PP4C_SFD_SHIFT 16 +#define SATA_AHCI_VENDOR_PP4C_SFD_MASK 0x00FF0000U -/*PTST: Partial to Slumber timer value, specific delay the controller should apply while in partial before entering slumber. Th - value is bases on the system clock divided by 128, total delay = (Sys Clock Period) * PTST * 128*/ +/* +* PTST: Partial to Slumber timer value, specific delay the controller shou + * ld apply while in partial before entering slumber. The value is bases on + * the system clock divided by 128, total delay = (Sys Clock Period) * PTS + * T * 128 +*/ #undef SATA_AHCI_VENDOR_PP4C_PTST_DEFVAL #undef SATA_AHCI_VENDOR_PP4C_PTST_SHIFT #undef SATA_AHCI_VENDOR_PP4C_PTST_MASK -#define SATA_AHCI_VENDOR_PP4C_PTST_DEFVAL 0x064A0813 -#define SATA_AHCI_VENDOR_PP4C_PTST_SHIFT 24 -#define SATA_AHCI_VENDOR_PP4C_PTST_MASK 0xFF000000U +#define SATA_AHCI_VENDOR_PP4C_PTST_DEFVAL 0x064A0813 +#define SATA_AHCI_VENDOR_PP4C_PTST_SHIFT 24 +#define SATA_AHCI_VENDOR_PP4C_PTST_MASK 0xFF000000U -/*RIT: Retry Interval Timer. The calculated value divided by two, the lower digit of precision is not needed.*/ +/* +* RIT: Retry Interval Timer. The calculated value divided by two, the lowe + * r digit of precision is not needed. +*/ #undef SATA_AHCI_VENDOR_PP5C_RIT_DEFVAL #undef SATA_AHCI_VENDOR_PP5C_RIT_SHIFT #undef SATA_AHCI_VENDOR_PP5C_RIT_MASK -#define SATA_AHCI_VENDOR_PP5C_RIT_DEFVAL 0x3FFC96A4 -#define SATA_AHCI_VENDOR_PP5C_RIT_SHIFT 0 -#define SATA_AHCI_VENDOR_PP5C_RIT_MASK 0x000FFFFFU +#define SATA_AHCI_VENDOR_PP5C_RIT_DEFVAL 0x3FFC96A4 +#define SATA_AHCI_VENDOR_PP5C_RIT_SHIFT 0 +#define SATA_AHCI_VENDOR_PP5C_RIT_MASK 0x000FFFFFU -/*RCT: Rate Change Timer, a value based on the 54.2us for which a SATA device will transmit at a fixed rate ALIGNp after OOB ha - completed, for a fast SERDES it is suggested that this value be 54.2us / 4*/ +/* +* RCT: Rate Change Timer, a value based on the 54.2us for which a SATA dev + * ice will transmit at a fixed rate ALIGNp after OOB has completed, for a + * fast SERDES it is suggested that this value be 54.2us / 4 +*/ #undef SATA_AHCI_VENDOR_PP5C_RCT_DEFVAL #undef SATA_AHCI_VENDOR_PP5C_RCT_SHIFT #undef SATA_AHCI_VENDOR_PP5C_RCT_MASK -#define SATA_AHCI_VENDOR_PP5C_RCT_DEFVAL 0x3FFC96A4 -#define SATA_AHCI_VENDOR_PP5C_RCT_SHIFT 20 -#define SATA_AHCI_VENDOR_PP5C_RCT_MASK 0xFFF00000U +#define SATA_AHCI_VENDOR_PP5C_RCT_DEFVAL 0x3FFC96A4 +#define SATA_AHCI_VENDOR_PP5C_RCT_SHIFT 20 +#define SATA_AHCI_VENDOR_PP5C_RCT_MASK 0xFFF00000U #undef CRL_APB_RST_LPD_TOP_OFFSET #define CRL_APB_RST_LPD_TOP_OFFSET 0XFF5E023C #undef CRL_APB_RST_LPD_IOU0_OFFSET @@ -27659,123 +36123,252 @@ #undef CRF_APB_RST_FPD_TOP_OFFSET #define CRF_APB_RST_FPD_TOP_OFFSET 0XFD1A0100 -/*USB 0 reset for control registers*/ +/* +* USB 0 reset for control registers +*/ #undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL #undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT #undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK -#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL 0x00188FDF -#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT 10 -#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK 0x00000400U +#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT 10 +#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK 0x00000400U -/*USB 0 sleep circuit reset*/ +/* +* USB 0 sleep circuit reset +*/ #undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL #undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT #undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK -#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL 0x00188FDF -#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT 8 -#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK 0x00000100U +#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT 8 +#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK 0x00000100U -/*USB 0 reset*/ +/* +* USB 0 reset +*/ #undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL #undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT #undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK -#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL 0x00188FDF -#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT 6 -#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK 0x00000040U +#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT 6 +#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK 0x00000040U -/*GEM 3 reset*/ +/* +* GEM 3 reset +*/ #undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL #undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT #undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK -#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL 0x0000000F -#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT 3 -#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK 0x00000008U +#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL 0x0000000F +#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT 3 +#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK 0x00000008U -/*Sata block level reset*/ +/* +* Sata block level reset +*/ #undef CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL #undef CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT #undef CRF_APB_RST_FPD_TOP_SATA_RESET_MASK -#define CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL 0x000F9FFE -#define CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT 1 -#define CRF_APB_RST_FPD_TOP_SATA_RESET_MASK 0x00000002U +#define CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT 1 +#define CRF_APB_RST_FPD_TOP_SATA_RESET_MASK 0x00000002U -/*PCIE config reset*/ +/* +* PCIE config reset +*/ #undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL #undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT #undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK -#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL 0x000F9FFE -#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT 19 -#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK 0x00080000U +#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT 19 +#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK 0x00080000U -/*PCIE control block level reset*/ +/* +* PCIE control block level reset +*/ #undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL #undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT #undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK -#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL 0x000F9FFE -#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT 17 -#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK 0x00020000U +#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT 17 +#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK 0x00020000U -/*PCIE bridge block level reset (AXI interface)*/ +/* +* PCIE bridge block level reset (AXI interface) +*/ #undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL #undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT #undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK -#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL 0x000F9FFE -#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT 18 -#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK 0x00040000U +#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT 18 +#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK 0x00040000U -/*Two bits per lane. When set to 11, moves the GT to power down mode. When set to 00, GT will be in active state. bits [1:0] - - ane0 Bits [3:2] - lane 1*/ +/* +* Two bits per lane. When set to 11, moves the GT to power down mode. When + * set to 00, GT will be in active state. bits [1:0] - lane0 Bits [3:2] - + * lane 1 +*/ #undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_DEFVAL #undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT #undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK -#define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_DEFVAL 0x00000000 -#define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT 0 -#define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK 0x0000000FU +#define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_DEFVAL 0x00000000 +#define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT 0 +#define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK 0x0000000FU -/*Set to '1' to hold the GT in reset. Clear to release.*/ +/* +* Set to '1' to hold the GT in reset. Clear to release. +*/ #undef DP_DP_PHY_RESET_GT_RESET_DEFVAL #undef DP_DP_PHY_RESET_GT_RESET_SHIFT #undef DP_DP_PHY_RESET_GT_RESET_MASK -#define DP_DP_PHY_RESET_GT_RESET_DEFVAL 0x00010003 -#define DP_DP_PHY_RESET_GT_RESET_SHIFT 1 -#define DP_DP_PHY_RESET_GT_RESET_MASK 0x00000002U +#define DP_DP_PHY_RESET_GT_RESET_DEFVAL 0x00010003 +#define DP_DP_PHY_RESET_GT_RESET_SHIFT 1 +#define DP_DP_PHY_RESET_GT_RESET_MASK 0x00000002U -/*Display Port block level reset (includes DPDMA)*/ +/* +* Display Port block level reset (includes DPDMA) +*/ #undef CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL #undef CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT #undef CRF_APB_RST_FPD_TOP_DP_RESET_MASK -#define CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL 0x000F9FFE -#define CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT 16 -#define CRF_APB_RST_FPD_TOP_DP_RESET_MASK 0x00010000U +#define CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT 16 +#define CRF_APB_RST_FPD_TOP_DP_RESET_MASK 0x00010000U #undef PMU_GLOBAL_REQ_PWRUP_INT_EN_OFFSET #define PMU_GLOBAL_REQ_PWRUP_INT_EN_OFFSET 0XFFD80118 #undef PMU_GLOBAL_REQ_PWRUP_TRIG_OFFSET #define PMU_GLOBAL_REQ_PWRUP_TRIG_OFFSET 0XFFD80120 -/*Power-up Request Interrupt Enable for PL*/ +/* +* Power-up Request Interrupt Enable for PL +*/ #undef PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_DEFVAL #undef PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_SHIFT #undef PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_MASK -#define PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_DEFVAL 0x00000000 -#define PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_SHIFT 23 -#define PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_MASK 0x00800000U +#define PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_DEFVAL 0x00000000 +#define PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_SHIFT 23 +#define PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_MASK 0x00800000U -/*Power-up Request Trigger for PL*/ +/* +* Power-up Request Trigger for PL +*/ #undef PMU_GLOBAL_REQ_PWRUP_TRIG_PL_DEFVAL #undef PMU_GLOBAL_REQ_PWRUP_TRIG_PL_SHIFT #undef PMU_GLOBAL_REQ_PWRUP_TRIG_PL_MASK -#define PMU_GLOBAL_REQ_PWRUP_TRIG_PL_DEFVAL 0x00000000 -#define PMU_GLOBAL_REQ_PWRUP_TRIG_PL_SHIFT 23 -#define PMU_GLOBAL_REQ_PWRUP_TRIG_PL_MASK 0x00800000U +#define PMU_GLOBAL_REQ_PWRUP_TRIG_PL_DEFVAL 0x00000000 +#define PMU_GLOBAL_REQ_PWRUP_TRIG_PL_SHIFT 23 +#define PMU_GLOBAL_REQ_PWRUP_TRIG_PL_MASK 0x00800000U -/*Power-up Request Status for PL*/ +/* +* Power-up Request Status for PL +*/ #undef PMU_GLOBAL_REQ_PWRUP_STATUS_PL_DEFVAL #undef PMU_GLOBAL_REQ_PWRUP_STATUS_PL_SHIFT #undef PMU_GLOBAL_REQ_PWRUP_STATUS_PL_MASK -#define PMU_GLOBAL_REQ_PWRUP_STATUS_PL_DEFVAL 0x00000000 -#define PMU_GLOBAL_REQ_PWRUP_STATUS_PL_SHIFT 23 -#define PMU_GLOBAL_REQ_PWRUP_STATUS_PL_MASK 0x00800000U +#define PMU_GLOBAL_REQ_PWRUP_STATUS_PL_DEFVAL 0x00000000 +#define PMU_GLOBAL_REQ_PWRUP_STATUS_PL_SHIFT 23 +#define PMU_GLOBAL_REQ_PWRUP_STATUS_PL_MASK 0x00800000U #define PMU_GLOBAL_REQ_PWRUP_STATUS_OFFSET 0XFFD80110 +#undef CRF_APB_RST_FPD_TOP_OFFSET +#define CRF_APB_RST_FPD_TOP_OFFSET 0XFD1A0100 +#undef CRL_APB_RST_LPD_TOP_OFFSET +#define CRL_APB_RST_LPD_TOP_OFFSET 0XFF5E023C +#undef FPD_SLCR_AFI_FS_OFFSET +#define FPD_SLCR_AFI_FS_OFFSET 0XFD615000 + +/* +* AF_FM0 block level reset +*/ +#undef CRF_APB_RST_FPD_TOP_AFI_FM0_RESET_DEFVAL +#undef CRF_APB_RST_FPD_TOP_AFI_FM0_RESET_SHIFT +#undef CRF_APB_RST_FPD_TOP_AFI_FM0_RESET_MASK +#define CRF_APB_RST_FPD_TOP_AFI_FM0_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_AFI_FM0_RESET_SHIFT 7 +#define CRF_APB_RST_FPD_TOP_AFI_FM0_RESET_MASK 0x00000080U + +/* +* AF_FM1 block level reset +*/ +#undef CRF_APB_RST_FPD_TOP_AFI_FM1_RESET_DEFVAL +#undef CRF_APB_RST_FPD_TOP_AFI_FM1_RESET_SHIFT +#undef CRF_APB_RST_FPD_TOP_AFI_FM1_RESET_MASK +#define CRF_APB_RST_FPD_TOP_AFI_FM1_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_AFI_FM1_RESET_SHIFT 8 +#define CRF_APB_RST_FPD_TOP_AFI_FM1_RESET_MASK 0x00000100U + +/* +* AF_FM2 block level reset +*/ +#undef CRF_APB_RST_FPD_TOP_AFI_FM2_RESET_DEFVAL +#undef CRF_APB_RST_FPD_TOP_AFI_FM2_RESET_SHIFT +#undef CRF_APB_RST_FPD_TOP_AFI_FM2_RESET_MASK +#define CRF_APB_RST_FPD_TOP_AFI_FM2_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_AFI_FM2_RESET_SHIFT 9 +#define CRF_APB_RST_FPD_TOP_AFI_FM2_RESET_MASK 0x00000200U + +/* +* AF_FM3 block level reset +*/ +#undef CRF_APB_RST_FPD_TOP_AFI_FM3_RESET_DEFVAL +#undef CRF_APB_RST_FPD_TOP_AFI_FM3_RESET_SHIFT +#undef CRF_APB_RST_FPD_TOP_AFI_FM3_RESET_MASK +#define CRF_APB_RST_FPD_TOP_AFI_FM3_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_AFI_FM3_RESET_SHIFT 10 +#define CRF_APB_RST_FPD_TOP_AFI_FM3_RESET_MASK 0x00000400U + +/* +* AF_FM4 block level reset +*/ +#undef CRF_APB_RST_FPD_TOP_AFI_FM4_RESET_DEFVAL +#undef CRF_APB_RST_FPD_TOP_AFI_FM4_RESET_SHIFT +#undef CRF_APB_RST_FPD_TOP_AFI_FM4_RESET_MASK +#define CRF_APB_RST_FPD_TOP_AFI_FM4_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_AFI_FM4_RESET_SHIFT 11 +#define CRF_APB_RST_FPD_TOP_AFI_FM4_RESET_MASK 0x00000800U + +/* +* AF_FM5 block level reset +*/ +#undef CRF_APB_RST_FPD_TOP_AFI_FM5_RESET_DEFVAL +#undef CRF_APB_RST_FPD_TOP_AFI_FM5_RESET_SHIFT +#undef CRF_APB_RST_FPD_TOP_AFI_FM5_RESET_MASK +#define CRF_APB_RST_FPD_TOP_AFI_FM5_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_AFI_FM5_RESET_SHIFT 12 +#define CRF_APB_RST_FPD_TOP_AFI_FM5_RESET_MASK 0x00001000U + +/* +* AFI FM 6 +*/ +#undef CRL_APB_RST_LPD_TOP_AFI_FM6_RESET_DEFVAL +#undef CRL_APB_RST_LPD_TOP_AFI_FM6_RESET_SHIFT +#undef CRL_APB_RST_LPD_TOP_AFI_FM6_RESET_MASK +#define CRL_APB_RST_LPD_TOP_AFI_FM6_RESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_AFI_FM6_RESET_SHIFT 19 +#define CRL_APB_RST_LPD_TOP_AFI_FM6_RESET_MASK 0x00080000U + +/* +* Select the 32/64/128-bit data width selection for the Slave 0 00: 32-bit + * AXI data width (default) 01: 64-bit AXI data width 10: 128-bit AXI data + * width 11: reserved +*/ +#undef FPD_SLCR_AFI_FS_DW_SS0_SEL_DEFVAL +#undef FPD_SLCR_AFI_FS_DW_SS0_SEL_SHIFT +#undef FPD_SLCR_AFI_FS_DW_SS0_SEL_MASK +#define FPD_SLCR_AFI_FS_DW_SS0_SEL_DEFVAL 0x00000A00 +#define FPD_SLCR_AFI_FS_DW_SS0_SEL_SHIFT 8 +#define FPD_SLCR_AFI_FS_DW_SS0_SEL_MASK 0x00000300U + +/* +* Select the 32/64/128-bit data width selection for the Slave 1 00: 32-bit + * AXI data width (default) 01: 64-bit AXI data width 10: 128-bit AXI data + * width 11: reserved +*/ +#undef FPD_SLCR_AFI_FS_DW_SS1_SEL_DEFVAL +#undef FPD_SLCR_AFI_FS_DW_SS1_SEL_SHIFT +#undef FPD_SLCR_AFI_FS_DW_SS1_SEL_MASK +#define FPD_SLCR_AFI_FS_DW_SS1_SEL_DEFVAL 0x00000A00 +#define FPD_SLCR_AFI_FS_DW_SS1_SEL_SHIFT 10 +#define FPD_SLCR_AFI_FS_DW_SS1_SEL_MASK 0x00000C00U #undef GPIO_MASK_DATA_5_MSW_OFFSET #define GPIO_MASK_DATA_5_MSW_OFFSET 0XFF0A002C #undef GPIO_DIRM_5_OFFSET @@ -27789,53 +36382,65 @@ #undef GPIO_DATA_5_OFFSET #define GPIO_DATA_5_OFFSET 0XFF0A0054 -/*Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW]*/ +/* +* Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW] +*/ #undef GPIO_MASK_DATA_5_MSW_MASK_5_MSW_DEFVAL #undef GPIO_MASK_DATA_5_MSW_MASK_5_MSW_SHIFT #undef GPIO_MASK_DATA_5_MSW_MASK_5_MSW_MASK -#define GPIO_MASK_DATA_5_MSW_MASK_5_MSW_DEFVAL 0x00000000 -#define GPIO_MASK_DATA_5_MSW_MASK_5_MSW_SHIFT 16 -#define GPIO_MASK_DATA_5_MSW_MASK_5_MSW_MASK 0xFFFF0000U +#define GPIO_MASK_DATA_5_MSW_MASK_5_MSW_DEFVAL 0x00000000 +#define GPIO_MASK_DATA_5_MSW_MASK_5_MSW_SHIFT 16 +#define GPIO_MASK_DATA_5_MSW_MASK_5_MSW_MASK 0xFFFF0000U -/*Operation is the same as DIRM_0[DIRECTION_0]*/ +/* +* Operation is the same as DIRM_0[DIRECTION_0] +*/ #undef GPIO_DIRM_5_DIRECTION_5_DEFVAL #undef GPIO_DIRM_5_DIRECTION_5_SHIFT #undef GPIO_DIRM_5_DIRECTION_5_MASK -#define GPIO_DIRM_5_DIRECTION_5_DEFVAL -#define GPIO_DIRM_5_DIRECTION_5_SHIFT 0 -#define GPIO_DIRM_5_DIRECTION_5_MASK 0xFFFFFFFFU +#define GPIO_DIRM_5_DIRECTION_5_DEFVAL +#define GPIO_DIRM_5_DIRECTION_5_SHIFT 0 +#define GPIO_DIRM_5_DIRECTION_5_MASK 0xFFFFFFFFU -/*Operation is the same as OEN_0[OP_ENABLE_0]*/ +/* +* Operation is the same as OEN_0[OP_ENABLE_0] +*/ #undef GPIO_OEN_5_OP_ENABLE_5_DEFVAL #undef GPIO_OEN_5_OP_ENABLE_5_SHIFT #undef GPIO_OEN_5_OP_ENABLE_5_MASK -#define GPIO_OEN_5_OP_ENABLE_5_DEFVAL -#define GPIO_OEN_5_OP_ENABLE_5_SHIFT 0 -#define GPIO_OEN_5_OP_ENABLE_5_MASK 0xFFFFFFFFU +#define GPIO_OEN_5_OP_ENABLE_5_DEFVAL +#define GPIO_OEN_5_OP_ENABLE_5_SHIFT 0 +#define GPIO_OEN_5_OP_ENABLE_5_MASK 0xFFFFFFFFU -/*Output Data*/ +/* +* Output Data +*/ #undef GPIO_DATA_5_DATA_5_DEFVAL #undef GPIO_DATA_5_DATA_5_SHIFT #undef GPIO_DATA_5_DATA_5_MASK -#define GPIO_DATA_5_DATA_5_DEFVAL -#define GPIO_DATA_5_DATA_5_SHIFT 0 -#define GPIO_DATA_5_DATA_5_MASK 0xFFFFFFFFU +#define GPIO_DATA_5_DATA_5_DEFVAL +#define GPIO_DATA_5_DATA_5_SHIFT 0 +#define GPIO_DATA_5_DATA_5_MASK 0xFFFFFFFFU -/*Output Data*/ +/* +* Output Data +*/ #undef GPIO_DATA_5_DATA_5_DEFVAL #undef GPIO_DATA_5_DATA_5_SHIFT #undef GPIO_DATA_5_DATA_5_MASK -#define GPIO_DATA_5_DATA_5_DEFVAL -#define GPIO_DATA_5_DATA_5_SHIFT 0 -#define GPIO_DATA_5_DATA_5_MASK 0xFFFFFFFFU +#define GPIO_DATA_5_DATA_5_DEFVAL +#define GPIO_DATA_5_DATA_5_SHIFT 0 +#define GPIO_DATA_5_DATA_5_MASK 0xFFFFFFFFU -/*Output Data*/ +/* +* Output Data +*/ #undef GPIO_DATA_5_DATA_5_DEFVAL #undef GPIO_DATA_5_DATA_5_SHIFT #undef GPIO_DATA_5_DATA_5_MASK -#define GPIO_DATA_5_DATA_5_DEFVAL -#define GPIO_DATA_5_DATA_5_SHIFT 0 -#define GPIO_DATA_5_DATA_5_MASK 0xFFFFFFFFU +#define GPIO_DATA_5_DATA_5_DEFVAL +#define GPIO_DATA_5_DATA_5_SHIFT 0 +#define GPIO_DATA_5_DATA_5_MASK 0xFFFFFFFFU #ifdef __cplusplus extern "C" { #endif @@ -27848,6 +36453,7 @@ extern "C" { int psu_ddr_protection(); int psu_lpd_protection(); int psu_protection_lock(); + unsigned long psu_ddr_qos_init_data(void); unsigned long psu_apply_master_tz(); #ifdef __cplusplus } diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/system.hdf b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/system.hdf index 01f637605..8502f0d4b 100644 Binary files a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/system.hdf and b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/system.hdf differ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/.project b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/.project index d5d0e78c2..5dcf587a9 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/.project +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/.project @@ -57,7 +57,7 @@ - 1461592609781 + 1525142482332 src/FreeRTOS_Source 5 @@ -66,7 +66,7 @@ - 1461592609791 + 1525142482336 src/FreeRTOS_Source 5 @@ -75,7 +75,7 @@ - 1461592609811 + 1525142482342 src/FreeRTOS_Source 5 @@ -84,7 +84,7 @@ - 1461592609821 + 1525142482346 src/FreeRTOS_Source 5 @@ -93,7 +93,7 @@ - 1461592609921 + 1525142482352 src/FreeRTOS_Source 5 @@ -102,7 +102,7 @@ - 1461592609921 + 1525142482356 src/FreeRTOS_Source 5 @@ -111,7 +111,7 @@ - 1461592609931 + 1525142482360 src/FreeRTOS_Source 9 @@ -120,7 +120,7 @@ - 1461592609941 + 1525142482364 src/FreeRTOS_Source 9 @@ -128,6 +128,15 @@ 1.0-name-matches-false-false-portable + + 1525142482368 + src/FreeRTOS_Source + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-stream_buffer.c + + 1461592643370 src/FreeRTOS_Source/portable diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/FreeRTOSConfig.h index 5f417f026..12b5f4af8 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/FreeRTOSConfig.h @@ -127,6 +127,7 @@ to exclude the API function. */ #define INCLUDE_xTaskAbortDelay 1 #define INCLUDE_xTaskGetTaskHandle 1 #define INCLUDE_xTaskGetHandle 1 +#define INCLUDE_xSemaphoreGetMutexHolder 1 /* This demo makes use of one or more example stats formatting functions. These format the raw data provided by the uxTaskGetSystemState() function in to human diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwipopts.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwipopts.h index 82f31f8d9..bcfe0f8b8 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwipopts.h +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo/src/lwipopts.h @@ -309,4 +309,7 @@ a lot of data that needs to be copied, this should be set high. */ #define LWIP_NETIF_STATUS_CALLBACK 1 +/* Prevent conflict with struct timeval from compiler's library. */ +#define LWIP_TIMEVAL_PRIVATE 0 + #endif /* __LWIPOPTS_H__ */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/.cproject b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/.cproject index ed7e1b590..b4f281cf8 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/.cproject +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/.cproject @@ -1,8 +1,8 @@ - - + + diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/.project b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/.project index 4ff920168..07b59e59a 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/.project +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/.project @@ -1,7 +1,7 @@ RTOSDemo_bsp - Created by SDK v2016.1 + Created by SDK v2018.1 diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/Makefile b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/Makefile index 368665eb9..db5fc27bd 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/Makefile +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/Makefile @@ -16,16 +16,20 @@ include: $(addsuffix /make.include,$(SUBDIRS)) libs: $(addsuffix /make.libs,$(SUBDIRS)) +clean: $(addsuffix /make.clean,$(SUBDIRS)) + $(PROCESSOR)/lib/libxil.a: $(PROCESSOR)/lib/libxil_init.a cp -f $< $@ %/make.include: $(if $(wildcard $(PROCESSOR)/lib/libxil_init.a),$(PROCESSOR)/lib/libxil.a,) @echo "Running Make include in $(subst /make.include,,$@)" - $(MAKE) -C $(subst /make.include,,$@) -s include "SHELL=$(SHELL)" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles" + $(MAKE) -C $(subst /make.include,,$@) -s include "SHELL=$(SHELL)" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra" %/make.libs: include @echo "Running Make libs in $(subst /make.libs,,$@)" - $(MAKE) -C $(subst /make.libs,,$@) -s libs "SHELL=$(SHELL)" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles" + $(MAKE) -C $(subst /make.libs,,$@) -s libs "SHELL=$(SHELL)" "COMPILER=arm-none-eabi-gcc" "ARCHIVER=arm-none-eabi-ar" "COMPILER_FLAGS= -O2 -c" "EXTRA_COMPILER_FLAGS=-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra" +%/make.clean: + $(MAKE) -C $(subst /make.clean,,$@) -s clean clean: rm -f ${PROCESSOR}/lib/libxil.a diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xparameters.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xparameters.h index 06f110000..cfa88870e 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xparameters.h +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/include/xparameters.h @@ -1,5 +1,8 @@ +#ifndef XPARAMETERS_H /* prevent circular inclusions */ +#define XPARAMETERS_H /* by using protection macros */ + /* Definition for CPU ID */ -#define XPAR_CPU_ID 0 +#define XPAR_CPU_ID 0U /* Definitions for peripheral PS7_CORTEXA9_0 */ #define XPAR_PS7_CORTEXA9_0_CPU_CLK_FREQ_HZ 666666687 @@ -20,6 +23,14 @@ /******************************************************************/ +/* Platform specific definitions */ +#define PLATFORM_ZYNQ + +/* Definitions for sleep timer configuration */ +#define XSLEEP_TIMER_IS_DEFAULT_TIMER + + +/******************************************************************/ /* Definitions for driver CANPS */ #define XPAR_XCANPS_NUM_INSTANCES 1 @@ -50,20 +61,20 @@ /******************************************************************/ /* Definitions for driver DEVCFG */ -#define XPAR_XDCFG_NUM_INSTANCES 1 +#define XPAR_XDCFG_NUM_INSTANCES 1U /* Definitions for peripheral PS7_DEV_CFG_0 */ -#define XPAR_PS7_DEV_CFG_0_DEVICE_ID 0 -#define XPAR_PS7_DEV_CFG_0_BASEADDR 0xF8007000 -#define XPAR_PS7_DEV_CFG_0_HIGHADDR 0xF80070FF +#define XPAR_PS7_DEV_CFG_0_DEVICE_ID 0U +#define XPAR_PS7_DEV_CFG_0_BASEADDR 0xF8007000U +#define XPAR_PS7_DEV_CFG_0_HIGHADDR 0xF80070FFU /******************************************************************/ /* Canonical definitions for peripheral PS7_DEV_CFG_0 */ #define XPAR_XDCFG_0_DEVICE_ID XPAR_PS7_DEV_CFG_0_DEVICE_ID -#define XPAR_XDCFG_0_BASEADDR 0xF8007000 -#define XPAR_XDCFG_0_HIGHADDR 0xF80070FF +#define XPAR_XDCFG_0_BASEADDR 0xF8007000U +#define XPAR_XDCFG_0_HIGHADDR 0xF80070FFU /******************************************************************/ @@ -112,10 +123,12 @@ #define XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV1 5 #define XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV0 8 #define XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV1 50 +#define XPAR_PS7_ETHERNET_0_ENET_TSU_CLK_FREQ_HZ 0 /******************************************************************/ +#define XPAR_PS7_ETHERNET_0_IS_CACHE_COHERENT 0 /* Canonical definitions for peripheral PS7_ETHERNET_0 */ #define XPAR_XEMACPS_0_DEVICE_ID XPAR_PS7_ETHERNET_0_DEVICE_ID #define XPAR_XEMACPS_0_BASEADDR 0xE000B000 @@ -127,6 +140,7 @@ #define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV1 5 #define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV0 8 #define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV1 50 +#define XPAR_XEMACPS_0_ENET_TSU_CLK_FREQ_HZ 0 /******************************************************************/ @@ -275,6 +289,7 @@ #define XPAR_PS7_QSPI_0_HIGHADDR 0xE000DFFF #define XPAR_PS7_QSPI_0_QSPI_CLK_FREQ_HZ 200000000 #define XPAR_PS7_QSPI_0_QSPI_MODE 0 +#define XPAR_PS7_QSPI_0_QSPI_BUS_WIDTH 2 /******************************************************************/ @@ -285,27 +300,28 @@ #define XPAR_XQSPIPS_0_HIGHADDR 0xE000DFFF #define XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ 200000000 #define XPAR_XQSPIPS_0_QSPI_MODE 0 +#define XPAR_XQSPIPS_0_QSPI_BUS_WIDTH 2 /******************************************************************/ /* Definitions for driver SCUGIC */ -#define XPAR_XSCUGIC_NUM_INSTANCES 1 +#define XPAR_XSCUGIC_NUM_INSTANCES 1U /* Definitions for peripheral PS7_SCUGIC_0 */ -#define XPAR_PS7_SCUGIC_0_DEVICE_ID 0 -#define XPAR_PS7_SCUGIC_0_BASEADDR 0xF8F00100 -#define XPAR_PS7_SCUGIC_0_HIGHADDR 0xF8F001FF -#define XPAR_PS7_SCUGIC_0_DIST_BASEADDR 0xF8F01000 +#define XPAR_PS7_SCUGIC_0_DEVICE_ID 0U +#define XPAR_PS7_SCUGIC_0_BASEADDR 0xF8F00100U +#define XPAR_PS7_SCUGIC_0_HIGHADDR 0xF8F001FFU +#define XPAR_PS7_SCUGIC_0_DIST_BASEADDR 0xF8F01000U /******************************************************************/ /* Canonical definitions for peripheral PS7_SCUGIC_0 */ -#define XPAR_SCUGIC_0_DEVICE_ID 0 -#define XPAR_SCUGIC_0_CPU_BASEADDR 0xF8F00100 -#define XPAR_SCUGIC_0_CPU_HIGHADDR 0xF8F001FF -#define XPAR_SCUGIC_0_DIST_BASEADDR 0xF8F01000 +#define XPAR_SCUGIC_0_DEVICE_ID 0U +#define XPAR_SCUGIC_0_CPU_BASEADDR 0xF8F00100U +#define XPAR_SCUGIC_0_CPU_HIGHADDR 0xF8F001FFU +#define XPAR_SCUGIC_0_DIST_BASEADDR 0xF8F01000U /******************************************************************/ @@ -358,10 +374,14 @@ #define XPAR_PS7_SD_0_SDIO_CLK_FREQ_HZ 50000000 #define XPAR_PS7_SD_0_HAS_CD 1 #define XPAR_PS7_SD_0_HAS_WP 1 +#define XPAR_PS7_SD_0_BUS_WIDTH 0 +#define XPAR_PS7_SD_0_MIO_BANK 0 +#define XPAR_PS7_SD_0_HAS_EMIO 0 /******************************************************************/ +#define XPAR_PS7_SD_0_IS_CACHE_COHERENT 0 /* Canonical definitions for peripheral PS7_SD_0 */ #define XPAR_XSDPS_0_DEVICE_ID XPAR_PS7_SD_0_DEVICE_ID #define XPAR_XSDPS_0_BASEADDR 0xE0100000 @@ -369,45 +389,48 @@ #define XPAR_XSDPS_0_SDIO_CLK_FREQ_HZ 50000000 #define XPAR_XSDPS_0_HAS_CD 1 #define XPAR_XSDPS_0_HAS_WP 1 +#define XPAR_XSDPS_0_BUS_WIDTH 0 +#define XPAR_XSDPS_0_MIO_BANK 0 +#define XPAR_XSDPS_0_HAS_EMIO 0 /******************************************************************/ /* Definitions for driver TTCPS */ -#define XPAR_XTTCPS_NUM_INSTANCES 3 +#define XPAR_XTTCPS_NUM_INSTANCES 3U /* Definitions for peripheral PS7_TTC_0 */ -#define XPAR_PS7_TTC_0_DEVICE_ID 0 -#define XPAR_PS7_TTC_0_BASEADDR 0XF8001000 -#define XPAR_PS7_TTC_0_TTC_CLK_FREQ_HZ 111111115 -#define XPAR_PS7_TTC_0_TTC_CLK_CLKSRC 0 -#define XPAR_PS7_TTC_1_DEVICE_ID 1 -#define XPAR_PS7_TTC_1_BASEADDR 0XF8001004 -#define XPAR_PS7_TTC_1_TTC_CLK_FREQ_HZ 111111115 -#define XPAR_PS7_TTC_1_TTC_CLK_CLKSRC 0 -#define XPAR_PS7_TTC_2_DEVICE_ID 2 -#define XPAR_PS7_TTC_2_BASEADDR 0XF8001008 -#define XPAR_PS7_TTC_2_TTC_CLK_FREQ_HZ 111111115 -#define XPAR_PS7_TTC_2_TTC_CLK_CLKSRC 0 +#define XPAR_PS7_TTC_0_DEVICE_ID 0U +#define XPAR_PS7_TTC_0_BASEADDR 0XF8001000U +#define XPAR_PS7_TTC_0_TTC_CLK_FREQ_HZ 111111115U +#define XPAR_PS7_TTC_0_TTC_CLK_CLKSRC 0U +#define XPAR_PS7_TTC_1_DEVICE_ID 1U +#define XPAR_PS7_TTC_1_BASEADDR 0XF8001004U +#define XPAR_PS7_TTC_1_TTC_CLK_FREQ_HZ 111111115U +#define XPAR_PS7_TTC_1_TTC_CLK_CLKSRC 0U +#define XPAR_PS7_TTC_2_DEVICE_ID 2U +#define XPAR_PS7_TTC_2_BASEADDR 0XF8001008U +#define XPAR_PS7_TTC_2_TTC_CLK_FREQ_HZ 111111115U +#define XPAR_PS7_TTC_2_TTC_CLK_CLKSRC 0U /******************************************************************/ /* Canonical definitions for peripheral PS7_TTC_0 */ #define XPAR_XTTCPS_0_DEVICE_ID XPAR_PS7_TTC_0_DEVICE_ID -#define XPAR_XTTCPS_0_BASEADDR 0xF8001000 -#define XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ 111111115 -#define XPAR_XTTCPS_0_TTC_CLK_CLKSRC 0 +#define XPAR_XTTCPS_0_BASEADDR 0xF8001000U +#define XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ 111111115U +#define XPAR_XTTCPS_0_TTC_CLK_CLKSRC 0U #define XPAR_XTTCPS_1_DEVICE_ID XPAR_PS7_TTC_1_DEVICE_ID -#define XPAR_XTTCPS_1_BASEADDR 0xF8001004 -#define XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ 111111115 -#define XPAR_XTTCPS_1_TTC_CLK_CLKSRC 0 +#define XPAR_XTTCPS_1_BASEADDR 0xF8001004U +#define XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ 111111115U +#define XPAR_XTTCPS_1_TTC_CLK_CLKSRC 0U #define XPAR_XTTCPS_2_DEVICE_ID XPAR_PS7_TTC_2_DEVICE_ID -#define XPAR_XTTCPS_2_BASEADDR 0xF8001008 -#define XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ 111111115 -#define XPAR_XTTCPS_2_TTC_CLK_CLKSRC 0 +#define XPAR_XTTCPS_2_BASEADDR 0xF8001008U +#define XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ 111111115U +#define XPAR_XTTCPS_2_TTC_CLK_CLKSRC 0U /******************************************************************/ @@ -473,3 +496,4 @@ /******************************************************************/ +#endif /* end of protection macro */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/canps_v3_1/src/Makefile b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/canps_v3_2/src/Makefile similarity index 100% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/canps_v3_1/src/Makefile rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/canps_v3_2/src/Makefile diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/canps_v3_1/src/xcanps.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/canps_v3_2/src/xcanps.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/canps_v3_1/src/xcanps.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/canps_v3_2/src/xcanps.c index 243b3a81b..f852de4e6 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/canps_v3_1/src/xcanps.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/canps_v3_2/src/xcanps.c @@ -33,7 +33,7 @@ /** * * @file xcanps.c -* @addtogroup canps_v3_0 +* @addtogroup canps_v3_2 * @{ * * Functions in this file are the minimum required functions for the XCanPs diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/canps_v3_1/src/xcanps.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/canps_v3_2/src/xcanps.h similarity index 99% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/canps_v3_1/src/xcanps.h rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/canps_v3_2/src/xcanps.h index b180e37ec..9feb45eea 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/canps_v3_1/src/xcanps.h +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/canps_v3_2/src/xcanps.h @@ -33,7 +33,7 @@ /** * * @file xcanps.h -* @addtogroup canps_v3_0 +* @addtogroup canps_v3_2 * @{ * @details * @@ -204,6 +204,8 @@ * Data mismatch while sending data less than 8 bytes. * 3.1 nsk 12/21/15 Updated XCanPs_IntrHandler in xcanps_intr.c to handle * error interrupts correctly. CR#925615 +* ms 03/17/17 Added readme.txt file in examples folder for doxygen +* generation. * * ******************************************************************************/ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/canps_v3_1/src/xcanps_g.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/canps_v3_2/src/xcanps_g.c similarity index 91% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/canps_v3_1/src/xcanps_g.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/canps_v3_2/src/xcanps_g.c index ba95a60f4..bd2b19708 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/canps_v3_1/src/xcanps_g.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/canps_v3_2/src/xcanps_g.c @@ -5,7 +5,7 @@ * Version: * DO NOT EDIT. * -* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.* +* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.* *Permission is hereby granted, free of charge, to any person obtaining a copy *of this software and associated documentation files (the Software), to deal *in the Software without restriction, including without limitation the rights @@ -44,7 +44,7 @@ * The configuration table for devices */ -XCanPs_Config XCanPs_ConfigTable[] = +XCanPs_Config XCanPs_ConfigTable[XPAR_XCANPS_NUM_INSTANCES] = { { XPAR_PS7_CAN_0_DEVICE_ID, diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/canps_v3_1/src/xcanps_hw.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/canps_v3_2/src/xcanps_hw.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/canps_v3_1/src/xcanps_hw.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/canps_v3_2/src/xcanps_hw.c index bbb96120a..7ca2f81eb 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/canps_v3_1/src/xcanps_hw.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/canps_v3_2/src/xcanps_hw.c @@ -33,7 +33,7 @@ /** * * @file xcanps_hw.c -* @addtogroup canps_v3_0 +* @addtogroup canps_v3_2 * @{ * * This file contains the implementation of the canps interface reset sequence diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/canps_v3_1/src/xcanps_hw.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/canps_v3_2/src/xcanps_hw.h similarity index 99% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/canps_v3_1/src/xcanps_hw.h rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/canps_v3_2/src/xcanps_hw.h index 9fe681aaf..30ec68ab9 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/canps_v3_1/src/xcanps_hw.h +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/canps_v3_2/src/xcanps_hw.h @@ -33,7 +33,7 @@ /** * * @file xcanps_hw.h -* @addtogroup canps_v3_0 +* @addtogroup canps_v3_2 * @{ * * This header file contains the identifiers and basic driver functions (or diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/canps_v3_1/src/xcanps_intr.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/canps_v3_2/src/xcanps_intr.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/canps_v3_1/src/xcanps_intr.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/canps_v3_2/src/xcanps_intr.c index f6721ca75..715b35eb2 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/canps_v3_1/src/xcanps_intr.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/canps_v3_2/src/xcanps_intr.c @@ -33,7 +33,7 @@ /** * * @file xcanps_intr.c -* @addtogroup canps_v3_0 +* @addtogroup canps_v3_2 * @{ * * This file contains functions related to CAN interrupt handling. diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/canps_v3_1/src/xcanps_selftest.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/canps_v3_2/src/xcanps_selftest.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/canps_v3_1/src/xcanps_selftest.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/canps_v3_2/src/xcanps_selftest.c index 8bc77d7f4..26c9fcb68 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/canps_v3_1/src/xcanps_selftest.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/canps_v3_2/src/xcanps_selftest.c @@ -33,7 +33,7 @@ /** * * @file xcanps_selftest.c -* @addtogroup canps_v3_0 +* @addtogroup canps_v3_2 * @{ * * This file contains a diagnostic self-test function for the XCanPs driver. @@ -166,7 +166,7 @@ s32 XCanPs_SelfTest(XCanPs *InstancePtr) for (Index = 0U; Index < 8U; Index++) { if(*FramePtr != 0U) { *FramePtr = (u8)Index; - *FramePtr++; + FramePtr++; } } diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/canps_v3_1/src/xcanps_sinit.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/canps_v3_2/src/xcanps_sinit.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/canps_v3_1/src/xcanps_sinit.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/canps_v3_2/src/xcanps_sinit.c index 230c429b3..5321669d7 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/canps_v3_1/src/xcanps_sinit.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/canps_v3_2/src/xcanps_sinit.c @@ -33,7 +33,7 @@ /** * * @file xcanps_sinit.c -* @addtogroup canps_v3_0 +* @addtogroup canps_v3_2 * @{ * * This file contains the implementation of the XCanPs driver's static diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_2/src/Makefile b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src/Makefile similarity index 100% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_2/src/Makefile rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src/Makefile diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/coresightps_dcc_v1_3/src/xcoresightpsdcc.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src/xcoresightpsdcc.c similarity index 98% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/coresightps_dcc_v1_3/src/xcoresightpsdcc.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src/xcoresightpsdcc.c index 4bad57094..fca26ca2e 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/coresightps_dcc_v1_3/src/xcoresightpsdcc.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src/xcoresightpsdcc.c @@ -33,7 +33,7 @@ /** * * @file xcoresightpsdcc.c -* @addtogroup coresightps_dcc_v1_1 +* @addtogroup coresightps_dcc_v1_4 * @{ * * Functions in this file are the minimum required functions for the @@ -132,7 +132,7 @@ void XCoresightPs_DccSendByte(u32 BaseAddress, u8 Data) ******************************************************************************/ u8 XCoresightPs_DccRecvByte(u32 BaseAddress) { - u8 Data; + u8 Data = 0U; (void) BaseAddress; while (!(XCoresightPs_DccGetStatus() & XCORESIGHTPS_DCC_STATUS_RX)) @@ -169,7 +169,7 @@ u8 XCoresightPs_DccRecvByte(u32 BaseAddress) ******************************************************************************/ static INLINE u32 XCoresightPs_DccGetStatus(void) { - u32 Status; + u32 Status = 0U; #ifdef __aarch64__ asm volatile ("mrs %0, mdccsr_el0" : "=r" (Status)); diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/coresightps_dcc_v1_3/src/xcoresightpsdcc.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src/xcoresightpsdcc.h similarity index 98% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/coresightps_dcc_v1_3/src/xcoresightpsdcc.h rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src/xcoresightpsdcc.h index a732b235d..67959e327 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/coresightps_dcc_v1_3/src/xcoresightpsdcc.h +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_4/src/xcoresightpsdcc.h @@ -33,7 +33,7 @@ /** * * @file xcoresightpsdcc.h -* @addtogroup coresightps_dcc_v1_1 +* @addtogroup coresightps_dcc_v1_4 * @{ * @details * diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_2/src/Makefile b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_6/src/Makefile similarity index 78% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_2/src/Makefile rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_6/src/Makefile index 77363c67c..7ea505c10 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_2/src/Makefile +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_6/src/Makefile @@ -10,7 +10,7 @@ INCLUDEDIR=../../../include INCLUDES=-I${INCLUDEDIR} OUTS = *.o - +OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c))) LIBSOURCES=*.c INCLUDEFILES=*.h @@ -21,3 +21,5 @@ libs: include: ${CP} $(INCLUDEFILES) $(INCLUDEDIR) +clean: + rm -rf ${OBJECTS} diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_2/src/xcpu_cortexa9.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_6/src/xcpu_cortexa9.h similarity index 86% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_2/src/xcpu_cortexa9.h rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_6/src/xcpu_cortexa9.h index 4d441e53e..95c8ba536 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_2/src/xcpu_cortexa9.h +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_6/src/xcpu_cortexa9.h @@ -33,11 +33,16 @@ /** * * @file xcpu_cortexa9.h -* @addtogroup cpu_cortexa9_v2_1 +* @addtogroup cpu_cortexa9_v2_5 * @{ * @details * * dummy file +* MODIFICATION HISTORY: * +* Ver Who Date Changes +* ----- ---- -------- --------------------------------------------------------- +* 2.5 ms 04/18/17 Modified tcl file to add suffix U for XPAR_CPU_ID +* parameter of cpu_cortexa9 in xparameters.h ******************************************************************************/ /** @} */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/ddrps_v1_0/src/xddrps.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/ddrps_v1_0/src/xddrps.h index fe7adb066..c8804d2ed 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/ddrps_v1_0/src/xddrps.h +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/ddrps_v1_0/src/xddrps.h @@ -18,8 +18,8 @@ * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_4/src/Makefile b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/Makefile similarity index 100% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_4/src/Makefile rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/Makefile diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_4/src/xdevcfg.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_4/src/xdevcfg.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg.c index dcb80303d..e9447e7e3 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_4/src/xdevcfg.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg.c @@ -33,7 +33,7 @@ /** * * @file xdevcfg.c -* @addtogroup devcfg_v3_3 +* @addtogroup devcfg_v3_5 * @{ * * This file contains the implementation of the interface functions for XDcfg diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_4/src/xdevcfg.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg.h similarity index 96% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_4/src/xdevcfg.h rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg.h index 144c9e1f9..b9a0111d6 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_4/src/xdevcfg.h +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg.h @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -33,7 +33,7 @@ /** * * @file xdevcfg.h -* @addtogroup devcfg_v3_3 +* @addtogroup devcfg_v3_5 * @{ * @details * @@ -152,7 +152,13 @@ * configuration registers from the PL region. * xdevcfg_reg_readback_example.c * 3.3 sk 04/06/15 Modified XDcfg_ReadMultiBootConfig Macro CR# 851335. -* +* ms 03/17/17 Added readme.txt file in examples folder for doxygen +* generation. +* ms 04/10/17 Modified filename tag in interrupt and polled examples +* to include them in doxygen examples. +* 3.5 ms 04/18/17 Modified tcl file to add suffix U for all macros +* definitions of devcfg in xparameters.h +* ms 08/07/17 Fixed compilation warnings in xdevcfg_sinit.c * * ******************************************************************************/ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_4/src/xdevcfg_g.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_g.c similarity index 94% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_4/src/xdevcfg_g.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_g.c index 5e02d6dcd..e96911d51 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_4/src/xdevcfg_g.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_g.c @@ -5,7 +5,7 @@ * Version: * DO NOT EDIT. * -* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.* +* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.* *Permission is hereby granted, free of charge, to any person obtaining a copy *of this software and associated documentation files (the Software), to deal *in the Software without restriction, including without limitation the rights diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_4/src/xdevcfg_hw.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_hw.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_4/src/xdevcfg_hw.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_hw.c index 8a3095de3..bcb238f06 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_4/src/xdevcfg_hw.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_hw.c @@ -33,7 +33,7 @@ /** * * @file xdevcfg_hw.c -* @addtogroup devcfg_v3_3 +* @addtogroup devcfg_v3_5 * @{ * * This file contains the implementation of the interface reset functionality diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_4/src/xdevcfg_hw.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_hw.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_4/src/xdevcfg_hw.h rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_hw.h diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_4/src/xdevcfg_intr.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_intr.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_4/src/xdevcfg_intr.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_intr.c index 55bbde2f0..b41b7ea37 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_4/src/xdevcfg_intr.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_intr.c @@ -33,7 +33,7 @@ /** * * @file xdevcfg_intr.c -* @addtogroup devcfg_v3_3 +* @addtogroup devcfg_v3_5 * @{ * * Contains the implementation of interrupt related functions of the XDcfg diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_4/src/xdevcfg_selftest.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_selftest.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_4/src/xdevcfg_selftest.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_selftest.c index 7159782e1..40cf1de6a 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_4/src/xdevcfg_selftest.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_selftest.c @@ -33,7 +33,7 @@ /** * * @file xdevcfg_selftest.c -* @addtogroup devcfg_v3_3 +* @addtogroup devcfg_v3_5 * @{ * * Contains diagnostic self-test functions for the XDcfg driver. diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_4/src/xdevcfg_sinit.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_sinit.c similarity index 93% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_4/src/xdevcfg_sinit.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_sinit.c index d0d0e6d99..bbc96a0c6 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_4/src/xdevcfg_sinit.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_5/src/xdevcfg_sinit.c @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -33,7 +33,7 @@ /** * * @file xdevcfg_sinit.c -* @addtogroup devcfg_v3_3 +* @addtogroup devcfg_v3_5 * @{ * * This file contains method for static initialization (compile-time) of the @@ -45,6 +45,7 @@ * Ver Who Date Changes * ----- --- -------- --------------------------------------------- * 1.00a hvm 02/07/11 First release +* 3.5 ms 08/07/17 Fixed compilation warnings. * * ******************************************************************************/ @@ -79,9 +80,9 @@ XDcfg_Config *XDcfg_LookupConfig(u16 DeviceId) { extern XDcfg_Config XDcfg_ConfigTable[]; XDcfg_Config *CfgPtr = NULL; - int Index; + u32 Index; - for (Index = 0; Index < XPAR_XDCFG_NUM_INSTANCES; Index++) { + for (Index = 0U; Index < XPAR_XDCFG_NUM_INSTANCES; Index++) { if (XDcfg_ConfigTable[Index].DeviceId == DeviceId) { CfgPtr = &XDcfg_ConfigTable[Index]; break; diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_1/src/Makefile b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/Makefile similarity index 100% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_1/src/Makefile rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/Makefile diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_1/src/xdmaps.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps.c similarity index 97% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_1/src/xdmaps.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps.c index 1b6174256..9db769284 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_1/src/xdmaps.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps.c @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved. +* Copyright (C) 2009 - 2016 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -33,7 +33,7 @@ /** * * @file xdmaps.c -* @addtogroup dmaps_v2_1 +* @addtogroup dmaps_v2_3 * @{ * * This file contains the implementation of the interface functions for XDmaPs @@ -67,6 +67,9 @@ * the IARCC compiler around PDBG, it is better to remove it. * Users can always use xil_printfs if they want to debug. * 2.01 kpc 08/23/14 Fixed the IAR compiler reported errors +* 2.2 mus 12/08/16 Remove definition of INLINE macro to avoid re-definition, +* since it is being defined in xil_io.h +* 2.3 kpc 14/10/16 Fixed the compiler error when optimization O0 is used. * * *****************************************************************************/ @@ -93,11 +96,6 @@ /**************************** Type Definitions ******************************/ -#ifdef __ICCARM__ -#define INLINE -#else -#define INLINE __inline -#endif /***************** Macros (Inline Functions) Definitions ********************/ @@ -418,7 +416,7 @@ int XDmaPs_SetFaultHandler(XDmaPs *InstPtr, * @note None. * *****************************************************************************/ -INLINE int XDmaPs_Instr_DMAEND(char *DmaProg) +static INLINE int XDmaPs_Instr_DMAEND(char *DmaProg) { /* * DMAEND encoding: @@ -430,7 +428,7 @@ INLINE int XDmaPs_Instr_DMAEND(char *DmaProg) return 1; } -INLINE void XDmaPs_Memcpy4(char *Dst, char *Src) +static INLINE void XDmaPs_Memcpy4(char *Dst, char *Src) { *Dst = *Src; *(Dst + 1) = *(Src + 1); @@ -461,7 +459,7 @@ INLINE void XDmaPs_Memcpy4(char *Dst, char *Src) * @note None * *****************************************************************************/ -INLINE int XDmaPs_Instr_DMAGO(char *DmaProg, unsigned int Cn, +static INLINE int XDmaPs_Instr_DMAGO(char *DmaProg, unsigned int Cn, u32 Imm, unsigned int Ns) { /* @@ -497,7 +495,7 @@ INLINE int XDmaPs_Instr_DMAGO(char *DmaProg, unsigned int Cn, * @note None. * *****************************************************************************/ -INLINE int XDmaPs_Instr_DMALD(char *DmaProg) +static INLINE int XDmaPs_Instr_DMALD(char *DmaProg) { /* * DMALD encoding @@ -528,7 +526,7 @@ INLINE int XDmaPs_Instr_DMALD(char *DmaProg) * @note None. * *****************************************************************************/ -INLINE int XDmaPs_Instr_DMALP(char *DmaProg, unsigned Lc, +static INLINE int XDmaPs_Instr_DMALP(char *DmaProg, unsigned Lc, unsigned LoopIterations) { /* @@ -558,7 +556,7 @@ INLINE int XDmaPs_Instr_DMALP(char *DmaProg, unsigned Lc, * @note None. * *****************************************************************************/ -INLINE int XDmaPs_Instr_DMALPEND(char *DmaProg, char *BodyStart, unsigned Lc) +static INLINE int XDmaPs_Instr_DMALPEND(char *DmaProg, char *BodyStart, unsigned Lc) { /* * DMALPEND encoding @@ -599,7 +597,7 @@ INLINE int XDmaPs_Instr_DMALPEND(char *DmaProg, char *BodyStart, unsigned Lc) * @note None. * *****************************************************************************/ -INLINE int XDmaPs_Instr_DMAMOV(char *DmaProg, unsigned Rd, u32 Imm) +static INLINE int XDmaPs_Instr_DMAMOV(char *DmaProg, unsigned Rd, u32 Imm) { /* * DMAMOV encoding @@ -632,7 +630,7 @@ INLINE int XDmaPs_Instr_DMAMOV(char *DmaProg, unsigned Rd, u32 Imm) * @note None. * *****************************************************************************/ -INLINE int XDmaPs_Instr_DMANOP(char *DmaProg) +static INLINE int XDmaPs_Instr_DMANOP(char *DmaProg) { /* * DMANOP encoding @@ -657,7 +655,7 @@ INLINE int XDmaPs_Instr_DMANOP(char *DmaProg) * @note None. * *****************************************************************************/ -INLINE int XDmaPs_Instr_DMARMB(char *DmaProg) +static INLINE int XDmaPs_Instr_DMARMB(char *DmaProg) { /* * DMARMB encoding @@ -683,7 +681,7 @@ INLINE int XDmaPs_Instr_DMARMB(char *DmaProg) * @note None. * *****************************************************************************/ -INLINE int XDmaPs_Instr_DMASEV(char *DmaProg, unsigned int EventNumber) +static INLINE int XDmaPs_Instr_DMASEV(char *DmaProg, unsigned int EventNumber) { /* * DMASEV encoding @@ -711,7 +709,7 @@ INLINE int XDmaPs_Instr_DMASEV(char *DmaProg, unsigned int EventNumber) * @note None. * *****************************************************************************/ -INLINE int XDmaPs_Instr_DMAST(char *DmaProg) +static INLINE int XDmaPs_Instr_DMAST(char *DmaProg) { /* * DMAST encoding @@ -740,7 +738,7 @@ INLINE int XDmaPs_Instr_DMAST(char *DmaProg) * @note None. * *****************************************************************************/ -INLINE int XDmaPs_Instr_DMAWMB(char *DmaProg) +static INLINE int XDmaPs_Instr_DMAWMB(char *DmaProg) { /* * DMAWMB encoding @@ -764,7 +762,7 @@ INLINE int XDmaPs_Instr_DMAWMB(char *DmaProg) * @note None. * *****************************************************************************/ -INLINE unsigned XDmaPs_ToEndianSwapSizeBits(unsigned int EndianSwapSize) +static INLINE unsigned XDmaPs_ToEndianSwapSizeBits(unsigned int EndianSwapSize) { switch (EndianSwapSize) { case 0: @@ -797,7 +795,7 @@ INLINE unsigned XDmaPs_ToEndianSwapSizeBits(unsigned int EndianSwapSize) * @note None. * *****************************************************************************/ -INLINE unsigned XDmaPs_ToBurstSizeBits(unsigned BurstSize) +static INLINE unsigned XDmaPs_ToBurstSizeBits(unsigned BurstSize) { switch (BurstSize) { case 1: diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_1/src/xdmaps.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps.h similarity index 86% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_1/src/xdmaps.h rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps.h index cc415c811..5a0c1a28e 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_1/src/xdmaps.h +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps.h @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved. +* Copyright (C) 2009 - 2016 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -33,7 +33,7 @@ /** * * @file xdmaps.h -* @addtogroup dmaps_v2_1 +* @addtogroup dmaps_v2_3 * @{ * @details * @@ -75,6 +75,14 @@ * Users can always use xil_printfs if they want to debug. * 2.0 adk 10/12/13 Updated as per the New Tcl API's * 2.01 kpc 08/23/14 Fixed the IAR compiler reported errors +* 2.2 mus 08/12/16 Declared all inline functions in xdmaps.c as extern, to avoid +* linker error for IAR compiler +* 2.3 ms 01/23/17 Modified xil_printf statement in main function for all +* examples to ensure that "Successfully ran" and "Failed" +* strings are available in all examples. This is a fix +* for CR-965028. +* ms 03/17/17 Added readme.txt file in examples folder for doxygen +* generation. * * *****************************************************************************/ @@ -281,6 +289,29 @@ int XDmaPs_SetFaultHandler(XDmaPs *InstPtr, void XDmaPs_Print_DmaProg(XDmaPs_Cmd *Cmd); +/** + * To avoid linking error,Declare all inline functions as extern for + * IAR compiler + */ +#ifdef __ICCARM__ +extern INLINE int XDmaPs_Instr_DMAEND(char *DmaProg); +extern INLINE void XDmaPs_Memcpy4(char *Dst, char *Src); +extern INLINE int XDmaPs_Instr_DMAGO(char *DmaProg, unsigned int Cn, + u32 Imm, unsigned int Ns); +extern INLINE int XDmaPs_Instr_DMALD(char *DmaProg); +extern INLINE int XDmaPs_Instr_DMALP(char *DmaProg, unsigned Lc, + unsigned LoopIterations); +extern INLINE int XDmaPs_Instr_DMALPEND(char *DmaProg, char *BodyStart, unsigned Lc); +extern INLINE int XDmaPs_Instr_DMAMOV(char *DmaProg, unsigned Rd, u32 Imm); +extern INLINE int XDmaPs_Instr_DMANOP(char *DmaProg); +extern INLINE int XDmaPs_Instr_DMARMB(char *DmaProg); +extern INLINE int XDmaPs_Instr_DMASEV(char *DmaProg, unsigned int EventNumber); +extern INLINE int XDmaPs_Instr_DMAST(char *DmaProg); +extern INLINE int XDmaPs_Instr_DMAWMB(char *DmaProg); +extern INLINE unsigned XDmaPs_ToEndianSwapSizeBits(unsigned int EndianSwapSize); +extern INLINE unsigned XDmaPs_ToBurstSizeBits(unsigned BurstSize); +#endif + /** * Driver done interrupt service routines for the channels. * We need this done ISR mainly because the driver needs to release the diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_1/src/xdmaps_g.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_g.c similarity index 91% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_1/src/xdmaps_g.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_g.c index 3529895f9..bab15561f 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_1/src/xdmaps_g.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_g.c @@ -5,7 +5,7 @@ * Version: * DO NOT EDIT. * -* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.* +* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.* *Permission is hereby granted, free of charge, to any person obtaining a copy *of this software and associated documentation files (the Software), to deal *in the Software without restriction, including without limitation the rights @@ -44,7 +44,7 @@ * The configuration table for devices */ -XDmaPs_Config XDmaPs_ConfigTable[] = +XDmaPs_Config XDmaPs_ConfigTable[XPAR_XDMAPS_NUM_INSTANCES] = { { XPAR_PS7_DMA_NS_DEVICE_ID, diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_1/src/xdmaps_hw.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_hw.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_1/src/xdmaps_hw.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_hw.c index 9fc3dd898..4c0cfbfd2 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_1/src/xdmaps_hw.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_hw.c @@ -33,7 +33,7 @@ /** * * @file xdmaps_hw.c -* @addtogroup dmaps_v2_1 +* @addtogroup dmaps_v2_3 * @{ * * This file contains the implementation of the interface reset functionality diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_1/src/xdmaps_hw.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_hw.h similarity index 99% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_1/src/xdmaps_hw.h rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_hw.h index 1186107ac..628f1ec4f 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_1/src/xdmaps_hw.h +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_hw.h @@ -33,7 +33,7 @@ /** * * @file xdmaps_hw.h -* @addtogroup dmaps_v2_1 +* @addtogroup dmaps_v2_3 * @{ * * This header file contains the hardware interface of an XDmaPs device. diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_1/src/xdmaps_selftest.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_selftest.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_1/src/xdmaps_selftest.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_selftest.c index eae0846b5..daebd9903 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_1/src/xdmaps_selftest.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_selftest.c @@ -33,7 +33,7 @@ /** * * @file xdmaps_selftest.c -* @addtogroup dmaps_v2_1 +* @addtogroup dmaps_v2_3 * @{ * * This file contains the self-test functions for the XDmaPs driver. diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_1/src/xdmaps_sinit.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_sinit.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_1/src/xdmaps_sinit.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_sinit.c index 20866cf57..b92ee5311 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_1/src/xdmaps_sinit.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_3/src/xdmaps_sinit.c @@ -33,7 +33,7 @@ /** * * @file xdmaps_sinit.c -* @addtogroup dmaps_v2_1 +* @addtogroup dmaps_v2_3 * @{ * * The implementation of the XDmaPs driver's static initialzation diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v3_2/src/Makefile b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/Makefile similarity index 100% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v3_2/src/Makefile rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/Makefile diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_3/src/xemacps.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps.c similarity index 98% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_3/src/xemacps.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps.c index 26df03c3d..c013c4946 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_3/src/xemacps.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps.c @@ -33,7 +33,7 @@ /** * * @file xemacps.c -* @addtogroup emacps_v3_1 +* @addtogroup emacps_v3_7 * @{ * * The XEmacPs driver. Functions in this file are the minimum required functions @@ -52,6 +52,8 @@ * Disable extended mode. Perform all 64 bit changes under * check for arch64. * 3.1 hk 08/10/15 Update upper 32 bit tx and rx queue ptr registers +* 3.5 hk 08/14/17 Update cache coherency information of the interface in +* its config structure. * * ******************************************************************************/ @@ -107,6 +109,7 @@ LONG XEmacPs_CfgInitialize(XEmacPs *InstancePtr, XEmacPs_Config * CfgPtr, /* Set device base address and ID */ InstancePtr->Config.DeviceId = CfgPtr->DeviceId; InstancePtr->Config.BaseAddress = EffectiveAddress; + InstancePtr->Config.IsCacheCoherent = CfgPtr->IsCacheCoherent; /* Set callbacks to an initial stub routine */ InstancePtr->SendHandler = ((XEmacPs_Handler)((void*)XEmacPs_StubHandler)); diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v3_2/src/xemacps.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps.h similarity index 97% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v3_2/src/xemacps.h rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps.h index f12092bec..6d4b15b24 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v3_2/src/xemacps.h +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps.h @@ -33,7 +33,7 @@ /** * * @file xemacps.h -* @addtogroup emacps_v3_1 +* @addtogroup emacps_v3_7 * @{ * @details * @@ -316,6 +316,21 @@ * there is no error. CR# 869403 * 08/10/15 Update upper 32 bit tx and rx queue ptr registers. * 3.2 hk 02/22/16 Added SGMII support for Zynq Ultrascale+ MPSoC. + * 3.4 ms 01/23/17 Modified xil_printf statement in main function for all + * examples to ensure that "Successfully ran" and "Failed" + * strings are available in all examples. This is a fix + * for CR-965028. + * ms 03/17/17 Modified text file in examples folder for doxygen + * generation. + * ms 04/05/17 Added tabspace for return statements in functions of + * xemacps_ieee1588_example.c for proper documentation + * while generating doxygen. + * 3.5 hk 08/14/17 Update cache coherency information of the interface in + * its config structure. + * 3.6 rb 09/08/17 HwCnt variable (in XEmacPs_BdRing structure) is + * changed to volatile. + * Add API XEmacPs_BdRingPtrReset() to reset pointers + * * * ****************************************************************************/ @@ -513,6 +528,8 @@ typedef void (*XEmacPs_ErrHandler) (void *CallBackRef, u8 Direction, typedef struct { u16 DeviceId; /**< Unique ID of device */ UINTPTR BaseAddress;/**< Physical base address of IPIF registers */ + u8 IsCacheCoherent; /**< Applicable only to A53 in EL1 mode; + * describes whether Cache Coherent or not */ } XEmacPs_Config; diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_3/src/xemacps_bd.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_bd.h similarity index 99% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_3/src/xemacps_bd.h rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_bd.h index 52c5f7e7e..83f9a87fc 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_3/src/xemacps_bd.h +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_bd.h @@ -33,7 +33,7 @@ /** * * @file xemacps_bd.h -* @addtogroup emacps_v3_1 +* @addtogroup emacps_v3_7 * @{ * * This header provides operations to manage buffer descriptors in support diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_bdring.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_bdring.c similarity index 97% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_bdring.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_bdring.c index d837e1df1..3536873dc 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_bdring.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_bdring.c @@ -33,7 +33,7 @@ /** * * @file xemacps_bdring.c -* @addtogroup emacps_v3_1 +* @addtogroup emacps_v3_7 * @{ * * This file implements buffer descriptor ring related functions. @@ -57,6 +57,8 @@ * from uncached area. Fix for CR #663885. * 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp architecture. * 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance. +* 3.6 rb 09/08/17 Add XEmacPs_BdRingPtrReset() API to reset BD ring +* pointers * * ******************************************************************************/ @@ -505,7 +507,7 @@ LONG XEmacPs_BdRingUnAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd, XEmacPs_Bd * BdSetPtr) { LONG Status; - (void *)BdSetPtr; + (void) BdSetPtr; Xil_AssertNonvoid(RingPtr != NULL); Xil_AssertNonvoid(BdSetPtr != NULL); @@ -1072,4 +1074,29 @@ static void XEmacPs_BdSetTxWrap(UINTPTR BdPtr) *TempPtr = DataValueTx; } } + +/*****************************************************************************/ +/** + * Reset BD ring head and tail pointers. + * + * @param RingPtr is the instance to be worked on. + * @param VirtAddr is the virtual base address of the user memory region. + * + * @note + * Should be called after XEmacPs_Stop() + * + * @note + * C-style signature: + * void XEmacPs_BdRingPtrReset(XEmacPs_BdRing * RingPtr, void *virtaddrloc) + * + *****************************************************************************/ +void XEmacPs_BdRingPtrReset(XEmacPs_BdRing * RingPtr, void *virtaddrloc) +{ + RingPtr->FreeHead = virtaddrloc; + RingPtr->PreHead = virtaddrloc; + RingPtr->HwHead = virtaddrloc; + RingPtr->HwTail = virtaddrloc; + RingPtr->PostHead = virtaddrloc; +} + /** @} */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v3_2/src/xemacps_bdring.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_bdring.h similarity index 97% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v3_2/src/xemacps_bdring.h rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_bdring.h index de78cf28f..b89e89885 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v3_2/src/xemacps_bdring.h +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_bdring.h @@ -33,7 +33,7 @@ /** * * @file xemacps_bdring.h -* @addtogroup emacps_v3_1 +* @addtogroup emacps_v3_7 * @{ * * The Xiline EmacPs Buffer Descriptor ring driver. This is part of EmacPs @@ -47,6 +47,8 @@ * 1.00a wsy 01/10/10 First release * 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp architecture. * 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance. +* 3.6 rb 09/08/17 HwCnt variable (in XEmacPs_BdRing structure) is +* changed to volatile. * * * @@ -81,7 +83,7 @@ typedef struct { XEmacPs_Bd *BdaRestart; /**< BDA to load when channel is started */ - u32 HwCnt; /**< Number of BDs in work group */ + volatile u32 HwCnt; /**< Number of BDs in work group */ u32 PreCnt; /**< Number of BDs in pre-work group */ u32 FreeCnt; /**< Number of allocatable BDs in the free group */ u32 PostCnt; /**< Number of BDs in post-work group */ @@ -228,6 +230,7 @@ u32 XEmacPs_BdRingFromHwRx(XEmacPs_BdRing * RingPtr, u32 BdLimit, XEmacPs_Bd ** BdSetPtr); LONG XEmacPs_BdRingCheck(XEmacPs_BdRing * RingPtr, u8 Direction); +void XEmacPs_BdRingPtrReset(XEmacPs_BdRing * RingPtr, void *virtaddrloc); #ifdef __cplusplus } diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v3_2/src/xemacps_control.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_control.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v3_2/src/xemacps_control.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_control.c index f52451a8c..8217a4521 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v3_2/src/xemacps_control.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_control.c @@ -33,7 +33,7 @@ /** * * @file xemacps_control.c -* @addtogroup emacps_v3_1 +* @addtogroup emacps_v3_7 * @{ * * Functions in this file implement general purpose command and control related diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v3_2/src/xemacps_g.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_g.c similarity index 87% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v3_2/src/xemacps_g.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_g.c index 201e23d8f..2554f27ba 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v3_2/src/xemacps_g.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_g.c @@ -5,7 +5,7 @@ * Version: * DO NOT EDIT. * -* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.* +* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.* *Permission is hereby granted, free of charge, to any person obtaining a copy *of this software and associated documentation files (the Software), to deal *in the Software without restriction, including without limitation the rights @@ -44,11 +44,12 @@ * The configuration table for devices */ -XEmacPs_Config XEmacPs_ConfigTable[] = +XEmacPs_Config XEmacPs_ConfigTable[XPAR_XEMACPS_NUM_INSTANCES] = { { XPAR_PS7_ETHERNET_0_DEVICE_ID, - XPAR_PS7_ETHERNET_0_BASEADDR + XPAR_PS7_ETHERNET_0_BASEADDR, + XPAR_PS7_ETHERNET_0_IS_CACHE_COHERENT } }; diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v3_2/src/xemacps_hw.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_hw.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v3_2/src/xemacps_hw.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_hw.c index daba38397..00e79a58d 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v3_2/src/xemacps_hw.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_hw.c @@ -33,7 +33,7 @@ /** * * @file xemacps_hw.c -* @addtogroup emacps_v3_1 +* @addtogroup emacps_v3_7 * @{ * * This file contains the implementation of the ethernet interface reset sequence diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_3/src/xemacps_hw.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_hw.h similarity index 99% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_3/src/xemacps_hw.h rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_hw.h index 953cc6265..e535470c2 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_3/src/xemacps_hw.h +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_hw.h @@ -33,7 +33,7 @@ /** * * @file xemacps_hw.h -* @addtogroup emacps_v3_1 +* @addtogroup emacps_v3_7 * @{ * * This header file contains identifiers and low-level driver functions (or diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_3/src/xemacps_intr.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_intr.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_3/src/xemacps_intr.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_intr.c index 59636c4ef..9c355a163 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_3/src/xemacps_intr.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_intr.c @@ -33,7 +33,7 @@ /** * * @file xemacps_intr.c -* @addtogroup emacps_v3_1 +* @addtogroup emacps_v3_7 * @{ * * Functions in this file implement general purpose interrupt processing related diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v3_2/src/xemacps_sinit.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_sinit.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v3_2/src/xemacps_sinit.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_sinit.c index 1bc5b3b19..e2d2078af 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v3_2/src/xemacps_sinit.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v3_7/src/xemacps_sinit.c @@ -33,7 +33,7 @@ /** * * @file xemacps_sinit.c -* @addtogroup emacps_v3_1 +* @addtogroup emacps_v3_7 * @{ * * This file contains lookup method by device ID when success, it returns diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_1/src/Makefile b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/Makefile similarity index 100% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_1/src/Makefile rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/Makefile diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_1/src/xgpiops.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_1/src/xgpiops.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops.c index 90eedb87d..7b6fe2e46 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_1/src/xgpiops.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops.c @@ -33,7 +33,7 @@ /** * * @file xgpiops.c -* @addtogroup gpiops_v3_1 +* @addtogroup gpiops_v3_3 * @{ * * The XGpioPs driver. Functions in this file are the minimum required functions diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_1/src/xgpiops.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops.h similarity index 94% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_1/src/xgpiops.h rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops.h index 102615572..fda562d91 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_1/src/xgpiops.h +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops.h @@ -1,3 +1,4 @@ + /****************************************************************************** * * Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. @@ -33,7 +34,7 @@ /** * * @file xgpiops.h -* @addtogroup gpiops_v3_1 +* @addtogroup gpiops_v3_3 * @{ * @details * @@ -97,7 +98,15 @@ * passed to APIs. CR# 822636 * 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance. * 3.1 kvn 04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980. -* +* ms 03/17/17 Added readme.txt file in examples folder for doxygen +* generation. +* ms 04/05/17 Added tabspace for return statements in functions of +* gpiops examples for proper documentation while +* generating doxygen. +* 3.3 ms 04/17/17 Added notes about gpio input and output pin description +* for zcu102 and zc702 boards in polled and interrupt +* example, configured Interrupt pin to input pin for +* proper functioning of interrupt example. * * ******************************************************************************/ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_1/src/xgpiops_g.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_g.c similarity index 90% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_1/src/xgpiops_g.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_g.c index eac708037..76e6947a8 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_1/src/xgpiops_g.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_g.c @@ -5,7 +5,7 @@ * Version: * DO NOT EDIT. * -* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.* +* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.* *Permission is hereby granted, free of charge, to any person obtaining a copy *of this software and associated documentation files (the Software), to deal *in the Software without restriction, including without limitation the rights @@ -44,7 +44,7 @@ * The configuration table for devices */ -XGpioPs_Config XGpioPs_ConfigTable[] = +XGpioPs_Config XGpioPs_ConfigTable[XPAR_XGPIOPS_NUM_INSTANCES] = { { XPAR_PS7_GPIO_0_DEVICE_ID, diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_1/src/xgpiops_hw.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_hw.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_1/src/xgpiops_hw.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_hw.c index d7a5e00f0..8961c4287 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_1/src/xgpiops_hw.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_hw.c @@ -33,7 +33,7 @@ /** * * @file xgpiops_hw.c -* @addtogroup gpiops_v3_1 +* @addtogroup gpiops_v3_3 * @{ * * This file contains low level GPIO functions. diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_1/src/xgpiops_hw.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_hw.h similarity index 99% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_1/src/xgpiops_hw.h rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_hw.h index 81e8d6a9f..ff0190675 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_1/src/xgpiops_hw.h +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_hw.h @@ -33,7 +33,7 @@ /** * * @file xgpiops_hw.h -* @addtogroup gpiops_v3_1 +* @addtogroup gpiops_v3_3 * @{ * * This header file contains the identifiers and basic driver functions (or diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_1/src/xgpiops_intr.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_intr.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_1/src/xgpiops_intr.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_intr.c index c07381be6..a8b0a5626 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_1/src/xgpiops_intr.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_intr.c @@ -33,7 +33,7 @@ /** * * @file xgpiops_intr.c -* @addtogroup gpiops_v3_1 +* @addtogroup gpiops_v3_3 * @{ * * This file contains functions related to GPIO interrupt handling. @@ -722,7 +722,7 @@ void XGpioPs_IntrHandler(XGpioPs *InstancePtr) ******************************************************************************/ void StubHandler(void *CallBackRef, u32 Bank, u32 Status) { - (void*) CallBackRef; + (void) CallBackRef; (void) Bank; (void) Status; diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_1/src/xgpiops_selftest.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_selftest.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_1/src/xgpiops_selftest.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_selftest.c index da1973a2d..378524c14 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_1/src/xgpiops_selftest.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_selftest.c @@ -33,7 +33,7 @@ /** * * @file xgpiops_selftest.c -* @addtogroup gpiops_v3_1 +* @addtogroup gpiops_v3_3 * @{ * * This file contains a diagnostic self-test function for the XGpioPs driver. diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_1/src/xgpiops_sinit.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_sinit.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_1/src/xgpiops_sinit.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_sinit.c index 2ca008373..4cc0c390f 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_1/src/xgpiops_sinit.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_3/src/xgpiops_sinit.c @@ -33,7 +33,7 @@ /** * * @file xgpiops_sinit.c -* @addtogroup gpiops_v3_1 +* @addtogroup gpiops_v3_3 * @{ * * This file contains the implementation of the XGpioPs driver's static diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v3_1/src/Makefile b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v3_6/src/Makefile similarity index 100% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v3_1/src/Makefile rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v3_6/src/Makefile diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v3_6/src/xiicps.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v3_6/src/xiicps.c index 1c6819152..4f2b592e7 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v3_6/src/xiicps.c @@ -33,7 +33,7 @@ /** * * @file xiicps.c -* @addtogroup iicps_v3_0 +* @addtogroup iicps_v3_5 * @{ * * Contains implementation of required functions for the XIicPs driver. diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_4/src/xiicps.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v3_6/src/xiicps.h similarity index 99% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_4/src/xiicps.h rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v3_6/src/xiicps.h index b26193486..cc837a14c 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_4/src/xiicps.h +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v3_6/src/xiicps.h @@ -33,7 +33,7 @@ /** * * @file xiicps.h -* @addtogroup iicps_v3_0 +* @addtogroup iicps_v3_5 * @{ * @details * @@ -184,6 +184,8 @@ * 02/18/15 Implemented larger data transfer using repeated start * in Zynq UltraScale MP. * 3.3 kvn 05/05/16 Modified latest code for MISRA-C:2012 Compliance. +* ms 03/17/17 Added readme.txt file in examples folder for doxygen +* generation. * * * diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v3_1/src/xiicps_g.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v3_6/src/xiicps_g.c similarity index 91% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v3_1/src/xiicps_g.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v3_6/src/xiicps_g.c index 1f5d00c45..64ac64811 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v3_1/src/xiicps_g.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v3_6/src/xiicps_g.c @@ -5,7 +5,7 @@ * Version: * DO NOT EDIT. * -* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.* +* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.* *Permission is hereby granted, free of charge, to any person obtaining a copy *of this software and associated documentation files (the Software), to deal *in the Software without restriction, including without limitation the rights @@ -44,7 +44,7 @@ * The configuration table for devices */ -XIicPs_Config XIicPs_ConfigTable[] = +XIicPs_Config XIicPs_ConfigTable[XPAR_XIICPS_NUM_INSTANCES] = { { XPAR_PS7_I2C_0_DEVICE_ID, diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_hw.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v3_6/src/xiicps_hw.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_hw.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v3_6/src/xiicps_hw.c index a1dba8e62..2d85e1436 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_hw.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v3_6/src/xiicps_hw.c @@ -33,7 +33,7 @@ /** * * @file xiicps_hw.c -* @addtogroup iicps_v3_0 +* @addtogroup iicps_v3_5 * @{ * * Contains implementation of required functions for providing the reset sequence diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_hw.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v3_6/src/xiicps_hw.h similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_hw.h rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v3_6/src/xiicps_hw.h index 3b00cf8b1..d1eee82f2 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_hw.h +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v3_6/src/xiicps_hw.h @@ -33,7 +33,7 @@ /** * * @file xiicps_hw.h -* @addtogroup iicps_v3_0 +* @addtogroup iicps_v3_5 * @{ * * This header file contains the hardware definition for an IIC device. diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_intr.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v3_6/src/xiicps_intr.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_intr.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v3_6/src/xiicps_intr.c index 5231049c7..7f385918f 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_intr.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v3_6/src/xiicps_intr.c @@ -33,7 +33,7 @@ /** * * @file xiicps_intr.c -* @addtogroup iicps_v3_0 +* @addtogroup iicps_v3_5 * @{ * * Contains functions of the XIicPs driver for interrupt-driven transfers. diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_master.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v3_6/src/xiicps_master.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_master.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v3_6/src/xiicps_master.c index 7824d86b6..faa852826 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_master.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v3_6/src/xiicps_master.c @@ -33,7 +33,7 @@ /** * * @file xiicps_master.c -* @addtogroup iicps_v3_0 +* @addtogroup iicps_v3_5 * @{ * * Handles master mode transfers. @@ -63,7 +63,8 @@ * 02/18/15 Implemented larger data transfer using repeated start * in Zynq UltraScale MP. * 3.3 kvn 05/05/16 Modified latest code for MISRA-C:2012 Compliance. -* +* 3.6 ask 09/03/18 In XIicPs_MasterRecvPolled, set transfer size register +* before slave address. Fix for CR996440. * * ******************************************************************************/ @@ -424,7 +425,6 @@ s32 XIicPs_MasterRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr, IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET); XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg); - XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, SlaveAddr); /* * Set up the transfer size register so the slave knows how much @@ -440,6 +440,9 @@ s32 XIicPs_MasterRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr, ByteCountVar); } + + XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, SlaveAddr); + /* * Intrs keeps all the error-related interrupts. */ @@ -632,6 +635,11 @@ void XIicPs_DisableSlaveMonitor(XIicPs *InstancePtr) XIicPs_ReadReg(BaseAddr, XIICPS_CR_OFFSET) & (~XIICPS_CR_SLVMON_MASK)); + /* + * wait for slv monitor control bit to be clear + */ + while (XIicPs_ReadReg(BaseAddr, XIICPS_CR_OFFSET) + & XIICPS_CR_SLVMON_MASK); /* * Clear interrupt flag for slave monitor interrupt. */ diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_options.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v3_6/src/xiicps_options.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_options.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v3_6/src/xiicps_options.c index 1ebd78673..c9237dbb0 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_options.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v3_6/src/xiicps_options.c @@ -33,7 +33,7 @@ /** * * @file xiicps_options.c -* @addtogroup iicps_v3_0 +* @addtogroup iicps_v3_5 * @{ * * Contains functions for the configuration of the XIccPs driver. diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_4/src/xiicps_selftest.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v3_6/src/xiicps_selftest.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_4/src/xiicps_selftest.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v3_6/src/xiicps_selftest.c index dd57a1a51..31e02b56f 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_4/src/xiicps_selftest.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v3_6/src/xiicps_selftest.c @@ -33,7 +33,7 @@ /** * * @file xiicps_selftest.c -* @addtogroup iicps_v3_0 +* @addtogroup iicps_v3_5 * @{ * * This component contains the implementation of selftest functions for the diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_sinit.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v3_6/src/xiicps_sinit.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_sinit.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v3_6/src/xiicps_sinit.c index 7d7dadaa8..d8fbc4cd5 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_sinit.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v3_6/src/xiicps_sinit.c @@ -33,7 +33,7 @@ /** * * @file xiicps_sinit.c -* @addtogroup iicps_v3_0 +* @addtogroup iicps_v3_5 * @{ * * The implementation of the XIicPs component's static initialization diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_4/src/xiicps_slave.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v3_6/src/xiicps_slave.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_4/src/xiicps_slave.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v3_6/src/xiicps_slave.c index fef640b77..adc40a435 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/iicps_v3_4/src/xiicps_slave.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v3_6/src/xiicps_slave.c @@ -32,7 +32,7 @@ /*****************************************************************************/ /** * @file xiicps_slave.c -* @addtogroup iicps_v3_0 +* @addtogroup iicps_v3_5 * @{ * * Handles slave transfers diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/qspips_v3_3/src/Makefile b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/Makefile similarity index 100% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/qspips_v3_3/src/Makefile rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/Makefile diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/qspips_v3_3/src/xqspips.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/qspips_v3_3/src/xqspips.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips.c index 086b9887e..c33322c73 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/qspips_v3_3/src/xqspips.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips.c @@ -33,7 +33,7 @@ /** * * @file xqspips.c -* @addtogroup qspips_v3_2 +* @addtogroup qspips_v3_4 * @{ * * Contains implements the interface functions of the XQspiPs driver. diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/qspips_v3_3/src/xqspips.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips.h similarity index 98% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/qspips_v3_3/src/xqspips.h rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips.h index c97e5fa27..139ce4d38 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/qspips_v3_3/src/xqspips.h +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips.h @@ -33,7 +33,7 @@ /** * * @file xqspips.h -* @addtogroup qspips_v3_2 +* @addtogroup qspips_v3_4 * @{ * @details * @@ -273,6 +273,14 @@ * when thresholds are used. * 3.3 sk 11/07/15 Modified the API prototypes according to MISRAC standards * to remove compilation warnings. CR# 868893. +* ms 03/17/17 Added readme.txt file in examples folder for doxygen +* generation. +* ms 04/05/17 Modified Comment lines in functions of qspips +* examples to recognize it as documentation block +* and modified filename tag in +* xqspips_dual_flash_stack_lqspi_example.c to include it in +* doxygen examples. +* 3.4 nsk 31/07/17 Added QSPI_BUS_WIDTH parameter in xparameters.h file * * * diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/qspips_v3_3/src/xqspips_g.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_g.c similarity index 91% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/qspips_v3_3/src/xqspips_g.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_g.c index d9453c49c..d739e6218 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/qspips_v3_3/src/xqspips_g.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_g.c @@ -5,7 +5,7 @@ * Version: * DO NOT EDIT. * -* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.* +* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.* *Permission is hereby granted, free of charge, to any person obtaining a copy *of this software and associated documentation files (the Software), to deal *in the Software without restriction, including without limitation the rights @@ -44,7 +44,7 @@ * The configuration table for devices */ -XQspiPs_Config XQspiPs_ConfigTable[] = +XQspiPs_Config XQspiPs_ConfigTable[XPAR_XQSPIPS_NUM_INSTANCES] = { { XPAR_PS7_QSPI_0_DEVICE_ID, diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/qspips_v3_3/src/xqspips_hw.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_hw.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/qspips_v3_3/src/xqspips_hw.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_hw.c index 47cf6d4c9..1817b0780 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/qspips_v3_3/src/xqspips_hw.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_hw.c @@ -33,7 +33,7 @@ /** * * @file xqspips_hw.c -* @addtogroup qspips_v3_2 +* @addtogroup qspips_v3_4 * @{ * * Contains low level functions, primarily reset related. diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/qspips_v3_3/src/xqspips_hw.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_hw.h similarity index 99% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/qspips_v3_3/src/xqspips_hw.h rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_hw.h index 404afed94..96c867ad3 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/qspips_v3_3/src/xqspips_hw.h +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_hw.h @@ -33,7 +33,7 @@ /** * * @file xqspips_hw.h -* @addtogroup qspips_v3_2 +* @addtogroup qspips_v3_4 * @{ * * This header file contains the identifiers and basic HW access driver diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/qspips_v3_3/src/xqspips_options.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_options.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/qspips_v3_3/src/xqspips_options.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_options.c index 911391ccd..1cd43f48c 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/qspips_v3_3/src/xqspips_options.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_options.c @@ -33,7 +33,7 @@ /** * * @file xqspips_options.c -* @addtogroup qspips_v3_2 +* @addtogroup qspips_v3_4 * @{ * * Contains functions for the configuration of the XQspiPs driver component. diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/qspips_v3_3/src/xqspips_selftest.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_selftest.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/qspips_v3_3/src/xqspips_selftest.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_selftest.c index 309b36e2b..4c44cdff2 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/qspips_v3_3/src/xqspips_selftest.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_selftest.c @@ -33,7 +33,7 @@ /** * * @file xqspips_selftest.c -* @addtogroup qspips_v3_2 +* @addtogroup qspips_v3_4 * @{ * * This file contains the implementation of selftest function for the QSPI diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/qspips_v3_3/src/xqspips_sinit.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_sinit.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/qspips_v3_3/src/xqspips_sinit.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_sinit.c index be154be99..929ecd832 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/qspips_v3_3/src/xqspips_sinit.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/qspips_v3_4/src/xqspips_sinit.c @@ -33,7 +33,7 @@ /** * * @file xqspips_sinit.c -* @addtogroup qspips_v3_2 +* @addtogroup qspips_v3_4 * @{ * * The implementation of the XQspiPs component's static initialization diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scugic_v3_2/src/Makefile b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/Makefile similarity index 100% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scugic_v3_2/src/Makefile rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/Makefile diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/scugic_v3_5/src/xscugic.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic.c similarity index 82% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/scugic_v3_5/src/xscugic.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic.c index bf7ac12e8..f6afc0e5a 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/scugic_v3_5/src/xscugic.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic.c @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2010 - 2016 Xilinx, Inc. All rights reserved. +* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -33,7 +33,7 @@ /** * * @file xscugic.c -* @addtogroup scugic_v3_1 +* @addtogroup scugic_v3_8 * @{ * * Contains required functions for the XScuGic driver for the Interrupt @@ -107,7 +107,17 @@ * and properly mask interrupt target processor value to modify * interrupt target processor register for a given interrupt ID * and cpu ID -* +* 3.6 pkp 20/01/17 Added new API XScuGic_Stop to Disable distributor and +* interrupts in case they are being used only by current cpu. +* It also removes current cpu from interrupt target registers +* for all interrupts. +* kvn 02/17/17 Add support for changing GIC CPU master at run time. +* kvn 02/28/17 Make the CpuId as static variable and Added new +* XScugiC_GetCpuId to access CpuId. +* 3.9 mus 02/21/18 Added new API's XScuGic_UnmapAllInterruptsFromCpu and +* XScuGic_InterruptUnmapFromCpu, These API's can be used +* by applications to unmap specific/all interrupts from +* target CPU. It fixes CR#992490. * * * @@ -127,6 +137,7 @@ /***************** Macros (Inline Functions) Definitions *********************/ /************************** Variable Definitions *****************************/ +static u32 CpuId = XPAR_CPU_ID; /**< CPU Core identifier */ /************************** Function Prototypes ******************************/ @@ -254,7 +265,7 @@ static void DistributorInit(XScuGic *InstancePtr, u32 CpuID) #endif RegValue = XScuGic_DistReadReg(InstancePtr, XSCUGIC_DIST_EN_OFFSET); - if (!(RegValue & XSCUGIC_EN_INT_MASK)) { + if ((RegValue & XSCUGIC_EN_INT_MASK) == 0U) { Xil_AssertVoid(InstancePtr != NULL); DoDistributorInit(InstancePtr, CpuID); return; @@ -353,7 +364,7 @@ s32 XScuGic_CfgInitialize(XScuGic *InstancePtr, u32 EffectiveAddr) { u32 Int_Id; - u32 Cpu_Id = (u32)XPAR_CPU_ID + (u32)1; + u32 Cpu_Id = CpuId + (u32)1; (void) EffectiveAddr; Xil_AssertNonvoid(InstancePtr != NULL); @@ -392,7 +403,7 @@ s32 XScuGic_CfgInitialize(XScuGic *InstancePtr, InstancePtr->Config->HandlerTable[Int_Id].CallBackRef = InstancePtr; } - + XScuGic_Stop(InstancePtr); DistributorInit(InstancePtr, Cpu_Id); CPUInitialize(InstancePtr); @@ -827,4 +838,183 @@ void XScuGic_InterruptMaptoCpu(XScuGic *InstancePtr, u8 Cpu_Id, u32 Int_Id) XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id), RegValue); } +/****************************************************************************/ +/** +* Unmaps specific SPI interrupt from the target CPU +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param Cpu_Id is a CPU number from which the interrupt has to be +* unmapped +* @param Int_Id is the IRQ source number to modify +* +* @return None. +* +* @note None +* +*****************************************************************************/ +void XScuGic_InterruptUnmapFromCpu(XScuGic *InstancePtr, u8 Cpu_Id, u32 Int_Id) +{ + u32 RegValue; + u8 BitPos; + + Xil_AssertVoid(InstancePtr != NULL); + + RegValue = XScuGic_DistReadReg(InstancePtr, + XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id)); + + /* + * Identify bit position corresponding to Int_Id and Cpu_Id, + * in interrupt target register and clear it + */ + BitPos = ((Int_Id % 4U) * 8U) + Cpu_Id; + RegValue &= (~ ( 1U << BitPos )); + XScuGic_DistWriteReg(InstancePtr, + XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id), + RegValue); +} +/****************************************************************************/ +/** +* Unmaps all SPI interrupts from the target CPU +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param Cpu_Id is a CPU number from which the interrupts has to be +* unmapped +* +* @return None. +* +* @note None +* +*****************************************************************************/ +void XScuGic_UnmapAllInterruptsFromCpu(XScuGic *InstancePtr, u8 Cpu_Id) +{ + u32 Int_Id; + u32 Target_Cpu; + u32 LocalCpuID = (1U << Cpu_Id); + + Xil_AssertVoid(InstancePtr != NULL); + + LocalCpuID |= LocalCpuID << 8U; + LocalCpuID |= LocalCpuID << 16U; + + for (Int_Id = 32U; Int_Id * @@ -322,6 +344,11 @@ void XScuGic_GetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id, void XScuGic_SetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id, u8 Priority, u8 Trigger); void XScuGic_InterruptMaptoCpu(XScuGic *InstancePtr, u8 Cpu_Id, u32 Int_Id); +void XScuGic_InterruptUnmapFromCpu(XScuGic *InstancePtr, u8 Cpu_Id, u32 Int_Id); +void XScuGic_UnmapAllInterruptsFromCpu(XScuGic *InstancePtr, u8 Cpu_Id); +void XScuGic_Stop(XScuGic *InstancePtr); +void XScuGic_SetCpuID(u32 CpuCoreId); +u32 XScuGic_GetCpuID(void); /* * Initialization functions in xscugic_sinit.c */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scugic_v3_2/src/xscugic_g.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic_g.c similarity index 87% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scugic_v3_2/src/xscugic_g.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic_g.c index 50888df78..6765fd57e 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scugic_v3_2/src/xscugic_g.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic_g.c @@ -5,7 +5,7 @@ * Version: * DO NOT EDIT. * -* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.* +* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.* *Permission is hereby granted, free of charge, to any person obtaining a copy *of this software and associated documentation files (the Software), to deal *in the Software without restriction, including without limitation the rights @@ -44,12 +44,13 @@ * The configuration table for devices */ -XScuGic_Config XScuGic_ConfigTable[] = +XScuGic_Config XScuGic_ConfigTable[XPAR_XSCUGIC_NUM_INSTANCES] = { { XPAR_PS7_SCUGIC_0_DEVICE_ID, XPAR_PS7_SCUGIC_0_BASEADDR, - XPAR_PS7_SCUGIC_0_DIST_BASEADDR + XPAR_PS7_SCUGIC_0_DIST_BASEADDR, + {{0}} /**< Initialize the HandlerTable to 0 */ } }; diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/scugic_v3_5/src/xscugic_hw.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic_hw.c similarity index 88% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/scugic_v3_5/src/xscugic_hw.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic_hw.c index 626779720..6604e3a55 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/scugic_v3_5/src/xscugic_hw.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic_hw.c @@ -33,7 +33,7 @@ /** * * @file xscugic_hw.c -* @addtogroup scugic_v3_1 +* @addtogroup scugic_v3_8 * @{ * * This file contains low-level driver functions that can be used to access the @@ -62,6 +62,13 @@ * XScuGic_SetPriTrigTypeByDistAddr and * XScuGic_GetPriTrigTypeByDistAddr here from xscugic.c * 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance. +* 3.6 kvn 02/17/17 Add support for changing GIC CPU master at run time. +* kvn 02/28/17 Make the CpuId as static variable and Added new +* XScugiC_GetCpuId to access CpuId. +* 3.9 mus 02/21/18 Added new API's XScuGic_InterruptUnmapFromCpuByDistAddr +* and XScuGic_UnmapAllInterruptsFromCpuByDistAddr, These +* API's can be used by applications to unmap specific/all +* interrupts from target CPU. It fixes CR#992490. * * * @@ -90,6 +97,7 @@ static XScuGic_Config *LookupConfigByBaseAddress(u32 CpuBaseAddress); /************************** Variable Definitions *****************************/ extern XScuGic_Config XScuGic_ConfigTable[XPAR_XSCUGIC_NUM_INSTANCES]; +extern u32 CpuId; /*****************************************************************************/ /** @@ -274,7 +282,7 @@ static void CPUInit(XScuGic_Config *Config) s32 XScuGic_DeviceInitialize(u32 DeviceId) { XScuGic_Config *Config; - u32 Cpu_Id = (u32)XPAR_CPU_ID + (u32)1; + u32 Cpu_Id = XScuGic_GetCpuID() + (u32)1; Config = &XScuGic_ConfigTable[(u32 )DeviceId]; @@ -567,4 +575,75 @@ void XScuGic_GetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id, *Trigger = (u8)(RegValue & XSCUGIC_INT_CFG_MASK); } + +/****************************************************************************/ +/** +* Unmaps specific SPI interrupt from the target CPU +* +* @param DistBaseAddress is the device base address +* @param Cpu_Id is a CPU number from which the interrupt has to be +* unmapped +* @param Int_Id is the IRQ source number to modify +* +* @return None. +* +* @note None +* +*****************************************************************************/ +void XScuGic_InterruptUnmapFromCpuByDistAddr(u32 DistBaseAddress, + u8 Cpu_Id, u32 Int_Id) +{ + u32 RegValue; + u8 BitPos; + + Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS); + + RegValue = XScuGic_ReadReg(DistBaseAddress, + XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id)); + + /* + * Identify bit position corresponding to Int_Id and Cpu_Id, + * in interrupt target register and clear it + */ + BitPos = ((Int_Id % 4U) * 8U) + Cpu_Id; + RegValue &= (~ ( 1U << BitPos )); + XScuGic_WriteReg(DistBaseAddress, + XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id), RegValue); +} + +/****************************************************************************/ +/** +* Unmaps all SPI interrupts from the target CPU +* +* @param DistBaseAddress is the device base address +* @param Cpu_Id is a CPU number from which the interrupts has to be +* unmapped +* +* @return None. +* +* @note None +* +*****************************************************************************/ +void XScuGic_UnmapAllInterruptsFromCpuByDistAddr(u32 DistBaseAddress, + u8 Cpu_Id) +{ + u32 Int_Id; + u32 Target_Cpu; + u32 LocalCpuID = (1U << Cpu_Id); + + LocalCpuID |= LocalCpuID << 8U; + LocalCpuID |= LocalCpuID << 16U; + + for (Int_Id = 32U; Int_Id * ******************************************************************************/ @@ -633,6 +637,10 @@ void XScuGic_SetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id, u8 Priority, u8 Trigger); void XScuGic_GetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id, u8 *Priority, u8 *Trigger); +void XScuGic_InterruptUnmapFromCpuByDistAddr(u32 DistBaseAddress, + u8 Cpu_Id, u32 Int_Id); +void XScuGic_UnmapAllInterruptsFromCpuByDistAddr(u32 DistBaseAddress, + u8 Cpu_Id); /************************** Variable Definitions *****************************/ #ifdef __cplusplus } diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/xscugic_intr.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic_intr.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/xscugic_intr.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic_intr.c index d05a51c5e..d82a60b9e 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/xscugic_intr.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic_intr.c @@ -33,7 +33,7 @@ /** * * @file xscugic_intr.c -* @addtogroup scugic_v3_1 +* @addtogroup scugic_v3_8 * @{ * * This file contains the interrupt processing for the driver for the Xilinx diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scugic_v3_2/src/xscugic_selftest.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic_selftest.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scugic_v3_2/src/xscugic_selftest.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic_selftest.c index 47620d644..7b1028f9f 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scugic_v3_2/src/xscugic_selftest.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic_selftest.c @@ -33,7 +33,7 @@ /** * * @file xscugic_selftest.c -* @addtogroup scugic_v3_1 +* @addtogroup scugic_v3_8 * @{ * * Contains diagnostic self-test functions for the XScuGic driver. diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/scugic_v3_5/src/xscugic_sinit.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic_sinit.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/scugic_v3_5/src/xscugic_sinit.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic_sinit.c index d30390ab8..842f31812 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/scugic_v3_5/src/xscugic_sinit.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scugic_v3_9/src/xscugic_sinit.c @@ -33,7 +33,7 @@ /** * * @file xscugic_sinit.c -* @addtogroup scugic_v3_1 +* @addtogroup scugic_v3_8 * @{ * * Contains static init functions for the XScuGic driver for the Interrupt diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer.h index 5a35f6210..ea4ba79de 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer.h +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer.h @@ -103,6 +103,8 @@ * the xstatus.h of the standalone BSP during the * libgen. * 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance. +* ms 03/17/17 Added readme.txt file in examples folder for doxygen +* generation. * * ******************************************************************************/ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_g.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_g.c index 8126d2402..6ccfa915b 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_g.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_1/src/xscutimer_g.c @@ -5,7 +5,7 @@ * Version: * DO NOT EDIT. * -* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.* +* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.* *Permission is hereby granted, free of charge, to any person obtaining a copy *of this software and associated documentation files (the Software), to deal *in the Software without restriction, including without limitation the rights @@ -44,7 +44,7 @@ * The configuration table for devices */ -XScuTimer_Config XScuTimer_ConfigTable[] = +XScuTimer_Config XScuTimer_ConfigTable[XPAR_XSCUTIMER_NUM_INSTANCES] = { { XPAR_PS7_SCUTIMER_0_DEVICE_ID, diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt.c index 8e9788551..cd9e15d2c 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt.c @@ -1,4 +1,3 @@ -/* $Id: xscuwdt.c,v 1.1.2.1 2011/01/20 04:04:40 sadanan Exp $ */ /****************************************************************************** * * Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt.h index 5d3b92bae..372bbc343 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt.h +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt.h @@ -125,6 +125,8 @@ * the xstatus.h of the standalone BSP during the * libgen. * 2.1 sk 02/26/15 Modified the code for MISRA-C:2012 compliance. +* ms 03/17/17 Added readme.txt file in examples folder for doxygen +* generation. * * ******************************************************************************/ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_g.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_g.c index 9824a3647..5d6307d34 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_g.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_1/src/xscuwdt_g.c @@ -5,7 +5,7 @@ * Version: * DO NOT EDIT. * -* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.* +* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.* *Permission is hereby granted, free of charge, to any person obtaining a copy *of this software and associated documentation files (the Software), to deal *in the Software without restriction, including without limitation the rights @@ -44,7 +44,7 @@ * The configuration table for devices */ -XScuWdt_Config XScuWdt_ConfigTable[] = +XScuWdt_Config XScuWdt_ConfigTable[XPAR_XSCUWDT_NUM_INSTANCES] = { { XPAR_PS7_SCUWDT_0_DEVICE_ID, diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/sdps_v2_7/src/Makefile b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/sdps_v3_4/src/Makefile similarity index 100% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/sdps_v2_7/src/Makefile rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/sdps_v3_4/src/Makefile diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_1/src/xsdps.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/sdps_v3_4/src/xsdps.c similarity index 81% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_1/src/xsdps.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/sdps_v3_4/src/xsdps.c index ac3f9469e..65f1b2237 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_1/src/xsdps.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/sdps_v3_4/src/xsdps.c @@ -33,7 +33,7 @@ /** * * @file xsdps.c -* @addtogroup sdps_v2_5 +* @addtogroup sdps_v3_4 * @{ * * Contains the interface functions of the XSdPs driver. @@ -74,6 +74,22 @@ * sk 10/13/16 Reduced the delay during power cycle to 1ms as per spec * sk 10/19/16 Used emmc_hwreset pin to reset eMMC. * sk 11/07/16 Enable Rst_n bit in ext_csd reg if not enabled. +* 3.2 sk 11/30/16 Modified the voltage switching sequence as per spec. +* sk 02/01/17 Added HSD and DDR mode support for eMMC. +* vns 02/09/17 Added ARMA53_32 support for ZynqMP CR#968397 +* sk 03/20/17 Add support for EL1 non-secure mode. +* 3.3 mn 05/17/17 Add support for 64bit DMA addressing +* mn 07/17/17 Add support for running SD at 200MHz +* mn 07/26/17 Fixed compilation warnings +* mn 08/07/17 Modify driver to support 64-bit DMA in arm64 only +* mn 08/17/17 Added CCI support for A53 and disabled data cache +* operations when it is enabled. +* mn 08/22/17 Updated for Word Access System support +* mn 09/06/17 Resolved compilation errors with IAR toolchain +* mn 09/26/17 Added UHS_MODE_ENABLE macro to enable UHS mode +* 3.4 mn 10/17/17 Use different commands for single and multi block +* transfers +* mn 03/02/18 Move UHS macro check to SD card initialization routine * * ******************************************************************************/ @@ -90,21 +106,23 @@ #define XSDPS_CMD1_HIGH_VOL 0x00FF8000U #define XSDPS_CMD1_DUAL_VOL 0x00FF8010U #define HIGH_SPEED_SUPPORT 0x2U +#define UHS_SDR50_SUPPORT 0x4U #define WIDTH_4_BIT_SUPPORT 0x4U #define SD_CLK_25_MHZ 25000000U #define SD_CLK_19_MHZ 19000000U #define SD_CLK_26_MHZ 26000000U #define EXT_CSD_DEVICE_TYPE_BYTE 196U -#define EXT_CSD_SEC_COUNT 212U +#define EXT_CSD_SEC_COUNT_BYTE1 212U +#define EXT_CSD_SEC_COUNT_BYTE2 213U +#define EXT_CSD_SEC_COUNT_BYTE3 214U +#define EXT_CSD_SEC_COUNT_BYTE4 215U #define EXT_CSD_DEVICE_TYPE_HIGH_SPEED 0x2U #define EXT_CSD_DEVICE_TYPE_DDR_1V8_HIGH_SPEED 0x4U #define EXT_CSD_DEVICE_TYPE_DDR_1V2_HIGH_SPEED 0x8U #define EXT_CSD_DEVICE_TYPE_SDR_1V8_HS200 0x10U #define EXT_CSD_DEVICE_TYPE_SDR_1V2_HS200 0x20U #define CSD_SPEC_VER_3 0x3U - -/* Note: Remove this once fixed */ -#define UHS_BROKEN +#define SCR_SPEC_VER_3 0x80U /**************************** Type Definitions *******************************/ @@ -116,10 +134,9 @@ s32 XSdPs_CmdTransfer(XSdPs *InstancePtr, u32 Cmd, u32 Arg, u32 BlkCnt); void XSdPs_SetupADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff); extern s32 XSdPs_Uhs_ModeInit(XSdPs *InstancePtr, u8 Mode); static s32 XSdPs_IdentifyCard(XSdPs *InstancePtr); -#ifndef UHS_BROKEN static s32 XSdPs_Switch_Voltage(XSdPs *InstancePtr); -#endif +u16 TransferMode; /*****************************************************************************/ /** * @@ -172,6 +189,7 @@ s32 XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr, InstancePtr->Config.BusWidth = ConfigPtr->BusWidth; InstancePtr->Config.BankNumber = ConfigPtr->BankNumber; InstancePtr->Config.HasEMIO = ConfigPtr->HasEMIO; + InstancePtr->Config.IsCacheCoherent = ConfigPtr->IsCacheCoherent; InstancePtr->SectorCount = 0; InstancePtr->Mode = XSDPS_DEFAULT_SPEED_MODE; InstancePtr->Config_TapDelay = NULL; @@ -250,10 +268,18 @@ s32 XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr, XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, XSDPS_POWER_CTRL_OFFSET, PowerLevel | XSDPS_PC_BUS_PWR_MASK); + +#ifdef __aarch64__ /* Enable ADMA2 in 64bit mode. */ + XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, + XSDPS_HOST_CTRL1_OFFSET, + XSDPS_HC_DMA_ADMA2_64_MASK); +#else + /* Enable ADMA2 in 32bit mode. */ XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL1_OFFSET, XSDPS_HC_DMA_ADMA2_32_MASK); +#endif /* Enable all interrupt status except card interrupt initially */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, @@ -274,10 +300,8 @@ s32 XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr, * Transfer mode register - default value * DMA enabled, block count enabled, data direction card to host(read) */ - XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, - XSDPS_XFER_MODE_OFFSET, - XSDPS_TM_DMA_EN_MASK | XSDPS_TM_BLK_CNT_EN_MASK | - XSDPS_TM_DAT_DIR_SEL_MASK); + TransferMode = XSDPS_TM_DMA_EN_MASK | XSDPS_TM_BLK_CNT_EN_MASK | + XSDPS_TM_DAT_DIR_SEL_MASK; /* Set block size to 512 by default */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, @@ -328,6 +352,10 @@ s32 XSdPs_SdCardInitialize(XSdPs *InstancePtr) Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); +#ifndef UHS_MODE_ENABLE + InstancePtr->Config.BusWidth = XSDPS_WIDTH_4; +#endif + if ((InstancePtr->HC_Version != XSDPS_HC_SPEC_V3) || ((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK) != XSDPS_CAPS_EMB_SLOT)) { @@ -395,9 +423,17 @@ s32 XSdPs_SdCardInitialize(XSdPs *InstancePtr) goto RETURN_PATH; } - Arg = XSDPS_ACMD41_HCS | XSDPS_ACMD41_3V3 | (0x1FFU << 15U); - if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) { - Arg |= XSDPS_OCR_S18; + Arg = XSDPS_ACMD41_HCS | XSDPS_ACMD41_3V3 | (0x1FFU << 15U); + /* + * There is no support to switch to 1.8V and use UHS mode on + * 1.0 silicon + */ + if ((InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) && +#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) || (PSU_PMU) + (XGetPSVersion_Info() > XPS_VERSION_1) && +#endif + (InstancePtr->Config.BusWidth == XSDPS_WIDTH_8)) { + Arg |= XSDPS_OCR_S18; } /* 0x40300000 - Host High Capacity support & 3.3V window */ @@ -419,18 +455,14 @@ s32 XSdPs_SdCardInitialize(XSdPs *InstancePtr) InstancePtr->HCS = 1U; } - /* There is no support to switch to 1.8V and use UHS mode on 1.0 silicon */ -#ifndef UHS_BROKEN - if ((RespOCR & XSDPS_OCR_S18) != 0U) { + if ((RespOCR & XSDPS_OCR_S18) != 0U) { InstancePtr->Switch1v8 = 1U; Status = XSdPs_Switch_Voltage(InstancePtr); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } - } -#endif /* CMD2 for Card ID */ Status = XSdPs_CmdTransfer(InstancePtr, CMD2, 0U, 0U); @@ -528,12 +560,13 @@ s32 XSdPs_CardInitialize(XSdPs *InstancePtr) { #ifdef __ICCARM__ #pragma data_alignment = 32 -static u8 ExtCsd[512]; + static u8 ExtCsd[512]; + u8 SCR[8] = { 0U }; #pragma data_alignment = 4 #else -static u8 ExtCsd[512] __attribute__ ((aligned(32))); + static u8 ExtCsd[512] __attribute__ ((aligned(32))); + u8 SCR[8] __attribute__ ((aligned(32))) = { 0U }; #endif - u8 SCR[8] = { 0U }; u8 ReadBuff[64] = { 0U }; s32 Status; u32 Arg; @@ -641,9 +674,68 @@ static u8 ExtCsd[512] __attribute__ ((aligned(32))); goto RETURN_PATH; } -#if defined (ARMR5) || defined (__aarch64__) - if ((InstancePtr->Switch1v8 != 0U) && - (InstancePtr->BusWidth == XSDPS_4_BIT_WIDTH)) { + if (((SCR[2] & SCR_SPEC_VER_3) != 0U) && + (ReadBuff[13] >= UHS_SDR50_SUPPORT) && + (InstancePtr->Config.BusWidth == XSDPS_WIDTH_8) && +#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) || (PSU_PMU) + (XGetPSVersion_Info() > XPS_VERSION_1) && +#endif + (InstancePtr->Switch1v8 == 0U)) { + u16 CtrlReg, ClockReg; + + /* Stop the clock */ + CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_CLK_CTRL_OFFSET); + CtrlReg &= ~(XSDPS_CC_SD_CLK_EN_MASK | XSDPS_CC_INT_CLK_EN_MASK); + XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_CLK_CTRL_OFFSET, + CtrlReg); + + /* Enabling 1.8V in controller */ + CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_HOST_CTRL2_OFFSET); + CtrlReg |= XSDPS_HC2_1V8_EN_MASK; + XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL2_OFFSET, + CtrlReg); + + /* Wait minimum 5mSec */ + (void)usleep(5000U); + + /* Check for 1.8V signal enable bit is cleared by Host */ + CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_HOST_CTRL2_OFFSET); + if ((CtrlReg & XSDPS_HC2_1V8_EN_MASK) == 0U) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + + /* Wait for internal clock to stabilize */ + ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_CLK_CTRL_OFFSET); + XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, + XSDPS_CLK_CTRL_OFFSET, + ClockReg | XSDPS_CC_INT_CLK_EN_MASK); + ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_CLK_CTRL_OFFSET); + while((ClockReg & XSDPS_CC_INT_CLK_STABLE_MASK) == 0U) { + ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_CLK_CTRL_OFFSET); + } + + /* Enable SD clock */ + ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_CLK_CTRL_OFFSET); + XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, + XSDPS_CLK_CTRL_OFFSET, + ClockReg | XSDPS_CC_SD_CLK_EN_MASK); + + /* Wait for 1mSec */ + (void)usleep(1000U); + + InstancePtr->Switch1v8 = 1U; + } + +#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) + if (InstancePtr->Switch1v8 != 0U) { /* Identify the UHS mode supported by card */ XSdPs_Identify_UhsMode(InstancePtr, ReadBuff); @@ -663,9 +755,10 @@ static u8 ExtCsd[512] __attribute__ ((aligned(32))); */ if (SCR[0] != 0U) { /* Check for high speed support */ - if ((ReadBuff[13] & HIGH_SPEED_SUPPORT) != 0U) { + if (((ReadBuff[13] & HIGH_SPEED_SUPPORT) != 0U) && + (InstancePtr->BusWidth >= XSDPS_4_BIT_WIDTH)) { InstancePtr->Mode = XSDPS_HIGH_SPEED_MODE; -#if defined (ARMR5) || defined (__aarch64__) +#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) InstancePtr->Config_TapDelay = XSdPs_hsd_sdr25_tapdelay; #endif Status = XSdPs_Change_BusSpeed(InstancePtr); @@ -675,7 +768,7 @@ static u8 ExtCsd[512] __attribute__ ((aligned(32))); } } } -#if defined (ARMR5) || defined (__aarch64__) +#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) } #endif @@ -695,10 +788,14 @@ static u8 ExtCsd[512] __attribute__ ((aligned(32))); goto RETURN_PATH; } - InstancePtr->SectorCount = *(u32 *)&ExtCsd[EXT_CSD_SEC_COUNT]; + InstancePtr->SectorCount = ((u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE4]) << 24; + InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE3] << 16; + InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE2] << 8; + InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE1]; - if ((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] & - EXT_CSD_DEVICE_TYPE_HIGH_SPEED) != 0U) { + if (((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] & + EXT_CSD_DEVICE_TYPE_HIGH_SPEED) != 0U) && + (InstancePtr->BusWidth >= XSDPS_4_BIT_WIDTH)) { InstancePtr->Mode = XSDPS_HIGH_SPEED_MODE; Status = XSdPs_Change_BusSpeed(InstancePtr); if (Status != XST_SUCCESS) { @@ -732,15 +829,39 @@ static u8 ExtCsd[512] __attribute__ ((aligned(32))); goto RETURN_PATH; } - InstancePtr->SectorCount = *(u32 *)&ExtCsd[EXT_CSD_SEC_COUNT]; + InstancePtr->SectorCount = ((u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE4]) << 24; + InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE3] << 16; + InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE2] << 8; + InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE1]; - if ((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] & + /* Check for card supported speed */ + if (((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] & (EXT_CSD_DEVICE_TYPE_SDR_1V8_HS200 | - EXT_CSD_DEVICE_TYPE_SDR_1V2_HS200)) != 0U) { + EXT_CSD_DEVICE_TYPE_SDR_1V2_HS200)) != 0U) && + (InstancePtr->BusWidth >= XSDPS_4_BIT_WIDTH)) { InstancePtr->Mode = XSDPS_HS200_MODE; -#if defined (ARMR5) || defined (__aarch64__) +#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) InstancePtr->Config_TapDelay = XSdPs_sdr104_hs200_tapdelay; #endif + } else if (((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] & + (EXT_CSD_DEVICE_TYPE_DDR_1V8_HIGH_SPEED | + EXT_CSD_DEVICE_TYPE_DDR_1V2_HIGH_SPEED)) != 0U) && + (InstancePtr->BusWidth >= XSDPS_4_BIT_WIDTH)) { + InstancePtr->Mode = XSDPS_DDR52_MODE; +#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) + InstancePtr->Config_TapDelay = XSdPs_ddr50_tapdelay; +#endif + } else if (((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] & + EXT_CSD_DEVICE_TYPE_HIGH_SPEED) != 0U) && + (InstancePtr->BusWidth >= XSDPS_4_BIT_WIDTH)) { + InstancePtr->Mode = XSDPS_HIGH_SPEED_MODE; +#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) + InstancePtr->Config_TapDelay = XSdPs_hsd_sdr25_tapdelay; +#endif + } else + InstancePtr->Mode = XSDPS_DEFAULT_SPEED_MODE; + + if (InstancePtr->Mode != XSDPS_DEFAULT_SPEED_MODE) { Status = XSdPs_Change_BusSpeed(InstancePtr); if (Status != XST_SUCCESS) { Status = XST_FAILURE; @@ -753,9 +874,27 @@ static u8 ExtCsd[512] __attribute__ ((aligned(32))); goto RETURN_PATH; } - if (ExtCsd[EXT_CSD_HS_TIMING_BYTE] != EXT_CSD_HS_TIMING_HS200) { - Status = XST_FAILURE; - goto RETURN_PATH; + if (InstancePtr->Mode == XSDPS_HS200_MODE) { + if (ExtCsd[EXT_CSD_HS_TIMING_BYTE] != EXT_CSD_HS_TIMING_HS200) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + } + + if ((InstancePtr->Mode == XSDPS_HIGH_SPEED_MODE) || + InstancePtr->Mode == XSDPS_DDR52_MODE) { + if (ExtCsd[EXT_CSD_HS_TIMING_BYTE] != EXT_CSD_HS_TIMING_HIGH) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + + if (InstancePtr->Mode == XSDPS_DDR52_MODE) { + Status = XSdPs_Change_BusWidth(InstancePtr); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + } } } @@ -769,11 +908,13 @@ static u8 ExtCsd[512] __attribute__ ((aligned(32))); } } } - - Status = XSdPs_SetBlkSize(InstancePtr, XSDPS_BLK_SIZE_512_MASK); - if (Status != XST_SUCCESS) { - Status = XST_FAILURE; - goto RETURN_PATH; + if ((InstancePtr->Mode != XSDPS_DDR52_MODE) || + (InstancePtr->CardType == XSDPS_CARD_SD)) { + Status = XSdPs_SetBlkSize(InstancePtr, XSDPS_BLK_SIZE_512_MASK); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } } RETURN_PATH: @@ -839,7 +980,6 @@ RETURN_PATH: return Status; } -#ifndef UHS_BROKEN /*****************************************************************************/ /** * @@ -853,7 +993,7 @@ static s32 XSdPs_Switch_Voltage(XSdPs *InstancePtr) { s32 Status; u16 CtrlReg; - u32 ReadReg; + u32 ReadReg, ClockReg; /* Send switch voltage command */ Status = XSdPs_CmdTransfer(InstancePtr, CMD11, 0U, 0U); @@ -877,9 +1017,6 @@ static s32 XSdPs_Switch_Voltage(XSdPs *InstancePtr) XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_CLK_CTRL_OFFSET, CtrlReg); - /* Wait minimum 5mSec */ - (void)usleep(5000U); - /* Enabling 1.8V in controller */ CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL2_OFFSET); @@ -887,13 +1024,40 @@ static s32 XSdPs_Switch_Voltage(XSdPs *InstancePtr) XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL2_OFFSET, CtrlReg); - /* Start clock */ - Status = XSdPs_Change_ClkFreq(InstancePtr, XSDPS_CLK_400_KHZ); - if (Status != XST_SUCCESS) { + /* Wait minimum 5mSec */ + (void)usleep(5000U); + + /* Check for 1.8V signal enable bit is cleared by Host */ + CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_HOST_CTRL2_OFFSET); + if ((CtrlReg & XSDPS_HC2_1V8_EN_MASK) == 0U) { Status = XST_FAILURE; goto RETURN_PATH; } + /* Wait for internal clock to stabilize */ + ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_CLK_CTRL_OFFSET); + XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, + XSDPS_CLK_CTRL_OFFSET, + ClockReg | XSDPS_CC_INT_CLK_EN_MASK); + ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_CLK_CTRL_OFFSET); + while((ClockReg & XSDPS_CC_INT_CLK_STABLE_MASK) == 0U) { + ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_CLK_CTRL_OFFSET); + } + + /* Enable SD clock */ + ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_CLK_CTRL_OFFSET); + XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, + XSDPS_CLK_CTRL_OFFSET, + ClockReg | XSDPS_CC_SD_CLK_EN_MASK); + + /* Wait for 1mSec */ + (void)usleep(1000U); + /* Wait for CMD and DATA line to go high */ ReadReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_PRES_STATE_OFFSET); @@ -906,7 +1070,6 @@ static s32 XSdPs_Switch_Voltage(XSdPs *InstancePtr) RETURN_PATH: return Status; } -#endif /*****************************************************************************/ /** @@ -986,8 +1149,8 @@ s32 XSdPs_CmdTransfer(XSdPs *InstancePtr, u32 Cmd, u32 Arg, u32 BlkCnt) } } - XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_CMD_OFFSET, - (u16)CommandReg); + XSdPs_WriteReg(InstancePtr->Config.BaseAddress, XSDPS_XFER_MODE_OFFSET, + (CommandReg << 16) | TransferMode); /* Polling for response for now */ do { @@ -1178,20 +1341,32 @@ s32 XSdPs_ReadPolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff) } XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, Buff); + if (InstancePtr->Config.IsCacheCoherent == 0) { + Xil_DCacheInvalidateRange((INTPTR)Buff, + BlkCnt * XSDPS_BLK_SIZE_512_MASK); + } - XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, - XSDPS_XFER_MODE_OFFSET, - XSDPS_TM_AUTO_CMD12_EN_MASK | + if (BlkCnt == 1U) { + TransferMode = XSDPS_TM_BLK_CNT_EN_MASK | + XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK; + + /* Send single block read command */ + Status = XSdPs_CmdTransfer(InstancePtr, CMD17, Arg, BlkCnt); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + } else { + TransferMode = XSDPS_TM_AUTO_CMD12_EN_MASK | XSDPS_TM_BLK_CNT_EN_MASK | XSDPS_TM_DAT_DIR_SEL_MASK | - XSDPS_TM_DMA_EN_MASK | XSDPS_TM_MUL_SIN_BLK_SEL_MASK); + XSDPS_TM_DMA_EN_MASK | XSDPS_TM_MUL_SIN_BLK_SEL_MASK; - Xil_DCacheInvalidateRange((INTPTR)Buff, BlkCnt * XSDPS_BLK_SIZE_512_MASK); - - /* Send block read command */ - Status = XSdPs_CmdTransfer(InstancePtr, CMD18, Arg, BlkCnt); - if (Status != XST_SUCCESS) { - Status = XST_FAILURE; - goto RETURN_PATH; + /* Send multiple blocks read command */ + Status = XSdPs_CmdTransfer(InstancePtr, CMD18, Arg, BlkCnt); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } } /* Check for transfer complete */ @@ -1269,19 +1444,31 @@ s32 XSdPs_WritePolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, const u8 *Buff) } XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, Buff); - Xil_DCacheFlushRange((INTPTR)Buff, BlkCnt * XSDPS_BLK_SIZE_512_MASK); + if (InstancePtr->Config.IsCacheCoherent == 0) { + Xil_DCacheFlushRange((INTPTR)Buff, + BlkCnt * XSDPS_BLK_SIZE_512_MASK); + } - XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, - XSDPS_XFER_MODE_OFFSET, - XSDPS_TM_AUTO_CMD12_EN_MASK | + if (BlkCnt == 1U) { + TransferMode = XSDPS_TM_BLK_CNT_EN_MASK | XSDPS_TM_DMA_EN_MASK; + + /* Send single block write command */ + Status = XSdPs_CmdTransfer(InstancePtr, CMD24, Arg, BlkCnt); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + } else { + TransferMode = XSDPS_TM_AUTO_CMD12_EN_MASK | XSDPS_TM_BLK_CNT_EN_MASK | - XSDPS_TM_MUL_SIN_BLK_SEL_MASK | XSDPS_TM_DMA_EN_MASK); + XSDPS_TM_MUL_SIN_BLK_SEL_MASK | XSDPS_TM_DMA_EN_MASK; - /* Send block write command */ - Status = XSdPs_CmdTransfer(InstancePtr, CMD25, Arg, BlkCnt); - if (Status != XST_SUCCESS) { - Status = XST_FAILURE; - goto RETURN_PATH; + /* Send multiple blocks write command */ + Status = XSdPs_CmdTransfer(InstancePtr, CMD25, Arg, BlkCnt); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } } /* @@ -1383,8 +1570,13 @@ void XSdPs_SetupADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff) } for (DescNum = 0U; DescNum < (TotalDescLines-1); DescNum++) { +#ifdef __aarch64__ + InstancePtr->Adma2_DescrTbl[DescNum].Address = + (u64)((UINTPTR)Buff + (DescNum*XSDPS_DESC_MAX_LENGTH)); +#else InstancePtr->Adma2_DescrTbl[DescNum].Address = (u32)((UINTPTR)Buff + (DescNum*XSDPS_DESC_MAX_LENGTH)); +#endif InstancePtr->Adma2_DescrTbl[DescNum].Attribute = XSDPS_DESC_TRAN | XSDPS_DESC_VALID; /* This will write '0' to length field which indicates 65536 */ @@ -1392,8 +1584,13 @@ void XSdPs_SetupADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff) (u16)XSDPS_DESC_MAX_LENGTH; } +#ifdef __aarch64__ + InstancePtr->Adma2_DescrTbl[TotalDescLines-1].Address = + (u64)((UINTPTR)Buff + (DescNum*XSDPS_DESC_MAX_LENGTH)); +#else InstancePtr->Adma2_DescrTbl[TotalDescLines-1].Address = (u32)((UINTPTR)Buff + (DescNum*XSDPS_DESC_MAX_LENGTH)); +#endif InstancePtr->Adma2_DescrTbl[TotalDescLines-1].Attribute = XSDPS_DESC_TRAN | XSDPS_DESC_END | XSDPS_DESC_VALID; @@ -1401,13 +1598,18 @@ void XSdPs_SetupADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff) InstancePtr->Adma2_DescrTbl[TotalDescLines-1].Length = (u16)((BlkCnt*BlkSize) - (DescNum*XSDPS_DESC_MAX_LENGTH)); +#ifdef __aarch64__ + XSdPs_WriteReg(InstancePtr->Config.BaseAddress, XSDPS_ADMA_SAR_EXT_OFFSET, + (u32)(((u64)&(InstancePtr->Adma2_DescrTbl[0]))>>32)); +#endif XSdPs_WriteReg(InstancePtr->Config.BaseAddress, XSDPS_ADMA_SAR_OFFSET, (u32)(UINTPTR)&(InstancePtr->Adma2_DescrTbl[0])); - Xil_DCacheFlushRange((INTPTR)&(InstancePtr->Adma2_DescrTbl[0]), + if (InstancePtr->Config.IsCacheCoherent == 0) { + Xil_DCacheFlushRange((INTPTR)&(InstancePtr->Adma2_DescrTbl[0]), sizeof(XSdPs_Adma2Descriptor) * 32U); - + } } /*****************************************************************************/ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sdps_v3_1/src/xsdps.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/sdps_v3_4/src/xsdps.h similarity index 90% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sdps_v3_1/src/xsdps.h rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/sdps_v3_4/src/xsdps.h index 46fe545d9..3f9ffd202 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sdps_v3_1/src/xsdps.h +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/sdps_v3_4/src/xsdps.h @@ -33,7 +33,7 @@ /** * * @file xsdps.h -* @addtogroup sdps_v2_5 +* @addtogroup sdps_v3_4 * @{ * @details * @@ -139,6 +139,16 @@ * sk 10/19/16 Used emmc_hwreset pin to reset eMMC. * sk 11/07/16 Enable Rst_n bit in ext_csd reg if not enabled. * sk 11/16/16 Issue DLL reset at 31 iteration to load new zero value. +* 3.2 sk 11/30/16 Modified the voltage switching sequence as per spec. +* sk 02/01/17 Added HSD and DDR mode support for eMMC. +* sk 02/01/17 Consider bus width parameter from design for switching +* vns 02/09/17 Added ARMA53_32 support for ZynqMP CR#968397 +* sk 03/20/17 Add support for EL1 non-secure mode. +* 3.3 mn 05/17/17 Add support for 64bit DMA addressing +* mn 08/07/17 Modify driver to support 64-bit DMA in arm64 only +* mn 08/17/17 Enabled CCI support for A53 by adding cache coherency +* information. +* mn 09/06/17 Resolved compilation errors with IAR toolchain * * * @@ -156,6 +166,7 @@ extern "C" { #include "xil_cache.h" #include "xstatus.h" #include "xsdps_hw.h" +#include "xplatform_info.h" #include /************************** Constant Definitions *****************************/ @@ -179,14 +190,25 @@ typedef struct { u32 BusWidth; /**< Bus Width */ u32 BankNumber; /**< MIO Bank selection for SD */ u32 HasEMIO; /**< If SD is connected to EMIO */ + u8 IsCacheCoherent; /**< If SD is Cache Coherent or not */ } XSdPs_Config; /* ADMA2 descriptor table */ typedef struct { u16 Attribute; /**< Attributes of descriptor */ u16 Length; /**< Length of current dma transfer */ +#ifdef __aarch64__ + u64 Address; /**< Address of current dma transfer */ +#else u32 Address; /**< Address of current dma transfer */ +#endif +#ifdef __ICCARM__ +#pragma data_alignment = 32 } XSdPs_Adma2Descriptor; +#pragma data_alignment = 4 +#else +} __attribute__((__packed__))XSdPs_Adma2Descriptor; +#endif /** * The XSdPs driver instance data. The user is required to allocate a @@ -243,8 +265,9 @@ s32 XSdPs_MmcCardInitialize(XSdPs *InstancePtr); s32 XSdPs_CardInitialize(XSdPs *InstancePtr); s32 XSdPs_Get_Mmc_ExtCsd(XSdPs *InstancePtr, u8 *ReadBuff); s32 XSdPs_Set_Mmc_ExtCsd(XSdPs *InstancePtr, u32 Arg); -#if defined (ARMR5) || defined (__aarch64__) +#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) void XSdPs_Identify_UhsMode(XSdPs *InstancePtr, u8 *ReadBuff); +void XSdPs_ddr50_tapdelay(u32 Bank, u32 DeviceId, u32 CardType); void XSdPs_hsd_sdr25_tapdelay(u32 Bank, u32 DeviceId, u32 CardType); void XSdPs_sdr104_hs200_tapdelay(u32 Bank, u32 DeviceId, u32 CardType); #endif diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/sdps_v2_7/src/xsdps_g.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/sdps_v3_4/src/xsdps_g.c similarity index 85% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/sdps_v2_7/src/xsdps_g.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/sdps_v3_4/src/xsdps_g.c index caab9c3f1..c427bed19 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/sdps_v2_7/src/xsdps_g.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/sdps_v3_4/src/xsdps_g.c @@ -5,7 +5,7 @@ * Version: * DO NOT EDIT. * -* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.* +* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.* *Permission is hereby granted, free of charge, to any person obtaining a copy *of this software and associated documentation files (the Software), to deal *in the Software without restriction, including without limitation the rights @@ -44,14 +44,18 @@ * The configuration table for devices */ -XSdPs_Config XSdPs_ConfigTable[] = +XSdPs_Config XSdPs_ConfigTable[XPAR_XSDPS_NUM_INSTANCES] = { { XPAR_PS7_SD_0_DEVICE_ID, XPAR_PS7_SD_0_BASEADDR, XPAR_PS7_SD_0_SDIO_CLK_FREQ_HZ, XPAR_PS7_SD_0_HAS_CD, - XPAR_PS7_SD_0_HAS_WP + XPAR_PS7_SD_0_HAS_WP, + XPAR_PS7_SD_0_BUS_WIDTH, + XPAR_PS7_SD_0_MIO_BANK, + XPAR_PS7_SD_0_HAS_EMIO, + XPAR_PS7_SD_0_IS_CACHE_COHERENT } }; diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sdps_v3_1/src/xsdps_hw.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/sdps_v3_4/src/xsdps_hw.h similarity index 95% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sdps_v3_1/src/xsdps_hw.h rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/sdps_v3_4/src/xsdps_hw.h index 2c5d712d2..8d190efa0 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sdps_v3_1/src/xsdps_hw.h +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/sdps_v3_4/src/xsdps_hw.h @@ -33,7 +33,7 @@ /** * * @file xsdps_hw.h -* @addtogroup sdps_v2_5 +* @addtogroup sdps_v3_4 * @{ * * This header file contains the identifiers and basic HW access driver @@ -56,6 +56,11 @@ * sk 07/16/16 Added Tap delays accordingly to different SD/eMMC * operating modes. * 3.1 sk 11/07/16 Enable Rst_n bit in ext_csd reg if not enabled. +* 3.2 sk 03/20/17 Add support for EL1 non-secure mode. +* 3.3 mn 08/22/17 Updated for Word Access System support +* mn 09/06/17 Added support for ARMCC toolchain +* 3.4 mn 01/22/18 Separated out SDR104 and HS200 clock defines +* * * ******************************************************************************/ @@ -953,6 +958,7 @@ extern "C" { #define XSDPS_HIGH_SPEED_MODE 0x5U #define XSDPS_DEFAULT_SPEED_MODE 0x6U #define XSDPS_HS200_MODE 0x7U +#define XSDPS_DDR52_MODE 0x4U #define XSDPS_SWITCH_CMD_BLKCNT 1U #define XSDPS_SWITCH_CMD_BLKSIZE 64U #define XSDPS_SWITCH_CMD_HS_GET 0x00FFFFF0U @@ -993,7 +999,16 @@ extern "C" { #define XSDPS_SD_SDR50_MAX_CLK 100000000U #define XSDPS_SD_DDR50_MAX_CLK 50000000U #define XSDPS_SD_SDR104_MAX_CLK 208000000U +/* + * XSDPS_SD_INPUT_MAX_CLK is set to 175000000 in order to keep it smaller + * than the clock value coming from the core. This value is kept to safely + * switch to SDR104 mode if the SD card supports it. + */ +#define XSDPS_SD_INPUT_MAX_CLK 175000000U + #define XSDPS_MMC_HS200_MAX_CLK 200000000U +#define XSDPS_MMC_HSD_MAX_CLK 52000000U +#define XSDPS_MMC_DDR_MAX_CLK 52000000U #define XSDPS_CARD_STATE_IDLE 0U #define XSDPS_CARD_STATE_RDY 1U @@ -1010,7 +1025,15 @@ extern "C" { #define XSDPS_SLOT_REM 0U #define XSDPS_SLOT_EMB 1U -#if defined (ARMR5) || defined (__aarch64__) +#define XSDPS_WIDTH_8 8U +#define XSDPS_WIDTH_4 4U + + +#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) +#define SD0_ITAPDLY_SEL_MASK 0x000000FFU +#define SD0_OTAPDLY_SEL_MASK 0x0000003FU +#define SD1_ITAPDLY_SEL_MASK 0x00FF0000U +#define SD1_OTAPDLY_SEL_MASK 0x003F0000U #define SD_DLL_CTRL 0x00000358U #define SD_ITAPDLY 0x00000314U #define SD_OTAPDLY 0x00000318U @@ -1151,8 +1174,18 @@ extern "C" { * u16 XSdPs_ReadReg(u32 BaseAddress. int RegOffset) * ******************************************************************************/ -#define XSdPs_ReadReg16(BaseAddress, RegOffset) \ - XSdPs_In16((BaseAddress) + (RegOffset)) +static INLINE u16 XSdPs_ReadReg16(u32 BaseAddress, u8 RegOffset) +{ +#if defined (__MICROBLAZE__) + u32 Reg; + BaseAddress += RegOffset & 0xFC; + Reg = XSdPs_In32(BaseAddress); + Reg >>= ((RegOffset & 0x3)*8); + return (u16)Reg; +#else + return XSdPs_In16((BaseAddress) + (RegOffset)); +#endif +} /***************************************************************************/ /** @@ -1170,8 +1203,20 @@ extern "C" { * u16 RegisterValue) * ******************************************************************************/ -#define XSdPs_WriteReg16(BaseAddress, RegOffset, RegisterValue) \ - XSdPs_Out16((BaseAddress) + (RegOffset), (RegisterValue)) + +static INLINE void XSdPs_WriteReg16(u32 BaseAddress, u8 RegOffset, u16 RegisterValue) +{ +#if defined (__MICROBLAZE__) + u32 Reg; + BaseAddress += RegOffset & 0xFC; + Reg = XSdPs_In32(BaseAddress); + Reg &= ~(0xFFFF<<((RegOffset & 0x3)*8)); + Reg |= RegisterValue <<((RegOffset & 0x3)*8); + XSdPs_Out32(BaseAddress, Reg); +#else + XSdPs_Out16((BaseAddress) + (RegOffset), (RegisterValue)); +#endif +} /****************************************************************************/ /** @@ -1187,9 +1232,18 @@ extern "C" { * u8 XSdPs_ReadReg(u32 BaseAddress. int RegOffset) * ******************************************************************************/ -#define XSdPs_ReadReg8(BaseAddress, RegOffset) \ - XSdPs_In8((BaseAddress) + (RegOffset)) - +static INLINE u8 XSdPs_ReadReg8(u32 BaseAddress, u8 RegOffset) +{ +#if defined (__MICROBLAZE__) + u32 Reg; + BaseAddress += RegOffset & 0xFC; + Reg = XSdPs_In32(BaseAddress); + Reg >>= ((RegOffset & 0x3)*8); + return (u8)Reg; +#else + return XSdPs_In8((BaseAddress) + (RegOffset)); +#endif +} /***************************************************************************/ /** * Write to a register. @@ -1206,9 +1260,19 @@ extern "C" { * u8 RegisterValue) * ******************************************************************************/ -#define XSdPs_WriteReg8(BaseAddress, RegOffset, RegisterValue) \ - XSdPs_Out8((BaseAddress) + (RegOffset), (RegisterValue)) - +static INLINE void XSdPs_WriteReg8(u32 BaseAddress, u8 RegOffset, u8 RegisterValue) +{ +#if defined (__MICROBLAZE__) + u32 Reg; + BaseAddress += RegOffset & 0xFC; + Reg = XSdPs_In32(BaseAddress); + Reg &= ~(0xFF<<((RegOffset & 0x3)*8)); + Reg |= RegisterValue <<((RegOffset & 0x3)*8); + XSdPs_Out32(BaseAddress, Reg); +#else + XSdPs_Out8((BaseAddress) + (RegOffset), (RegisterValue)); +#endif +} /***************************************************************************/ /** * Macro to get present status register diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sdps_v3_1/src/xsdps_options.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/sdps_v3_4/src/xsdps_options.c similarity index 77% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sdps_v3_1/src/xsdps_options.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/sdps_v3_4/src/xsdps_options.c index 7dbc772f3..bcd7c689b 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sdps_v3_1/src/xsdps_options.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/sdps_v3_4/src/xsdps_options.c @@ -33,7 +33,7 @@ /** * * @file xsdps_options.c -* @addtogroup sdps_v2_5 +* @addtogroup sdps_v3_4 * @{ * * Contains API's for changing the various options in host and card. @@ -63,6 +63,18 @@ * 3.1 mi 09/07/16 Removed compilation warnings with extra compiler flags. * sk 11/07/16 Enable Rst_n bit in ext_csd reg if not enabled. * sk 11/16/16 Issue DLL reset at 31 iteration to load new zero value. +* 3.2 sk 02/01/17 Added HSD and DDR mode support for eMMC. +* sk 02/01/17 Consider bus width parameter from design for switching +* vns 02/09/17 Added ARMA53_32 support for ZynqMP CR#968397 +* vns 03/13/17 Fixed MISRAC mandatory violation +* sk 03/20/17 Add support for EL1 non-secure mode. +* 3.3 mn 07/25/17 Removed SD0_OTAPDLYENA and SD1_OTAPDLYENA bits +* mn 08/07/17 Properly set OTAPDLY value by clearing previous bit +* settings +* mn 08/17/17 Added CCI support for A53 and disabled data cache +* operations when it is enabled. +* mn 08/22/17 Updated for Word Access System support +* 3.4 mn 01/22/18 Separated out SDR104 and HS200 clock defines * * * @@ -71,7 +83,9 @@ /***************************** Include Files *********************************/ #include "xsdps.h" #include "sleep.h" - +#if defined (__aarch64__) +#include "xil_smc.h" +#endif /************************** Constant Definitions *****************************/ #define UHS_SDR12_SUPPORT 0x1U #define UHS_SDR25_SUPPORT 0x2U @@ -86,14 +100,14 @@ s32 XSdPs_CmdTransfer(XSdPs *InstancePtr, u32 Cmd, u32 Arg, u32 BlkCnt); void XSdPs_SetupADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff); static s32 XSdPs_Execute_Tuning(XSdPs *InstancePtr); -#if defined (ARMR5) || defined (__aarch64__) +#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) s32 XSdPs_Uhs_ModeInit(XSdPs *InstancePtr, u8 Mode); static void XSdPs_sdr50_tapdelay(u32 Bank, u32 DeviceId, u32 CardType); -static void XSdPs_ddr50_tapdelay(u32 Bank, u32 DeviceId, u32 CardType); void XSdPs_SetTapDelay(XSdPs *InstancePtr); static void XSdPs_DllReset(XSdPs *InstancePtr); #endif +extern u16 TransferMode; /*****************************************************************************/ /** * Update Block size for read/write operations. @@ -193,11 +207,11 @@ s32 XSdPs_Get_BusWidth(XSdPs *InstancePtr, u8 *SCR) XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, SCR); - XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, - XSDPS_XFER_MODE_OFFSET, - XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK); + TransferMode = XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK; - Xil_DCacheInvalidateRange((INTPTR)SCR, 8); + if (InstancePtr->Config.IsCacheCoherent == 0) { + Xil_DCacheInvalidateRange((INTPTR)SCR, 8); + } Status = XSdPs_CmdTransfer(InstancePtr, ACMD51, 0U, BlkCnt); if (Status != XST_SUCCESS) { @@ -261,6 +275,16 @@ s32 XSdPs_Change_BusWidth(XSdPs *InstancePtr) Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + /* + * check for bus width for 3.0 controller and return if + * bus width is <4 + */ + if ((InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) && + (InstancePtr->Config.BusWidth < XSDPS_WIDTH_4)) { + Status = XST_SUCCESS; + goto RETURN_PATH; + } + if (InstancePtr->CardType == XSDPS_CARD_SD) { Status = XSdPs_CmdTransfer(InstancePtr, CMD55, InstancePtr->RelCardAddr, @@ -282,7 +306,8 @@ s32 XSdPs_Change_BusWidth(XSdPs *InstancePtr) } else { if ((InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) - && (InstancePtr->CardType == XSDPS_CHIP_EMMC)) { + && (InstancePtr->CardType == XSDPS_CHIP_EMMC) && + (InstancePtr->Config.BusWidth == XSDPS_WIDTH_8)) { /* in case of eMMC data width 8-bit */ InstancePtr->BusWidth = XSDPS_8_BIT_WIDTH; } else { @@ -290,9 +315,15 @@ s32 XSdPs_Change_BusWidth(XSdPs *InstancePtr) } if (InstancePtr->BusWidth == XSDPS_8_BIT_WIDTH) { - Arg = XSDPS_MMC_8_BIT_BUS_ARG; + if (InstancePtr->Mode == XSDPS_DDR52_MODE) + Arg = XSDPS_MMC_DDR_8_BIT_BUS_ARG; + else + Arg = XSDPS_MMC_8_BIT_BUS_ARG; } else { - Arg = XSDPS_MMC_4_BIT_BUS_ARG; + if (InstancePtr->Mode == XSDPS_DDR52_MODE) + Arg = XSDPS_MMC_DDR_4_BIT_BUS_ARG; + else + Arg = XSDPS_MMC_4_BIT_BUS_ARG; } Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 0U); @@ -336,6 +367,15 @@ s32 XSdPs_Change_BusWidth(XSdPs *InstancePtr) XSDPS_HOST_CTRL1_OFFSET, (u8)StatusReg); + if (InstancePtr->Mode == XSDPS_DDR52_MODE) { + StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_HOST_CTRL2_OFFSET); + StatusReg &= (u16)(~XSDPS_HC2_UHS_MODE_MASK); + StatusReg |= InstancePtr->Mode; + XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, + XSDPS_HOST_CTRL2_OFFSET, StatusReg); + } + Status = (s32)XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_RESP0_OFFSET); @@ -387,13 +427,13 @@ s32 XSdPs_Get_BusSpeed(XSdPs *InstancePtr, u8 *ReadBuff) XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff); - XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, - XSDPS_XFER_MODE_OFFSET, - XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK); + TransferMode = XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK; Arg = XSDPS_SWITCH_CMD_HS_GET; - Xil_DCacheInvalidateRange((INTPTR)ReadBuff, 64); + if (InstancePtr->Config.IsCacheCoherent == 0) { + Xil_DCacheInvalidateRange((INTPTR)ReadBuff, 64); + } Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 1U); if (Status != XST_SUCCESS) { @@ -454,7 +494,7 @@ s32 XSdPs_Change_BusSpeed(XSdPs *InstancePtr) u32 Arg; u16 BlkCnt; u16 BlkSize; - u8 ReadBuff[64]; + u8 ReadBuff[64] = {0U}; Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); @@ -469,11 +509,11 @@ s32 XSdPs_Change_BusSpeed(XSdPs *InstancePtr) XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff); - Xil_DCacheFlushRange((INTPTR)ReadBuff, 64); + if (InstancePtr->Config.IsCacheCoherent == 0) { + Xil_DCacheFlushRange((INTPTR)ReadBuff, 64); + } - XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, - XSDPS_XFER_MODE_OFFSET, - XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK); + TransferMode = XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK; Arg = XSDPS_SWITCH_CMD_HS_SET; @@ -553,7 +593,16 @@ s32 XSdPs_Change_BusSpeed(XSdPs *InstancePtr) goto RETURN_PATH; } } else { - Arg = XSDPS_MMC_HS200_ARG; + if (InstancePtr->Mode == XSDPS_HS200_MODE) { + Arg = XSDPS_MMC_HS200_ARG; + InstancePtr->BusSpeed = XSDPS_MMC_HS200_MAX_CLK; + } else if (InstancePtr->Mode == XSDPS_DDR52_MODE) { + Arg = XSDPS_MMC_HIGH_SPEED_ARG; + InstancePtr->BusSpeed = XSDPS_MMC_DDR_MAX_CLK; + } else { + Arg = XSDPS_MMC_HIGH_SPEED_ARG; + InstancePtr->BusSpeed = XSDPS_MMC_HSD_MAX_CLK; + } Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 0U); if (Status != XST_SUCCESS) { @@ -585,18 +634,18 @@ s32 XSdPs_Change_BusSpeed(XSdPs *InstancePtr) XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK); - /* Change the clock frequency to 200 MHz */ - InstancePtr->BusSpeed = XSDPS_MMC_HS200_MAX_CLK; - Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } - Status = XSdPs_Execute_Tuning(InstancePtr); - if (Status != XST_SUCCESS) { - Status = XST_FAILURE; - goto RETURN_PATH; + + if (InstancePtr->Mode == XSDPS_HS200_MODE) { + Status = XSdPs_Execute_Tuning(InstancePtr); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } } } @@ -654,7 +703,7 @@ s32 XSdPs_Change_ClkFreq(XSdPs *InstancePtr, u32 SelFreq) XSDPS_CLK_CTRL_OFFSET, ClockReg); if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) { -#if defined (ARMR5) || defined (__aarch64__) +#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) if ((InstancePtr->Mode != XSDPS_DEFAULT_SPEED_MODE) && (InstancePtr->Mode != XSDPS_UHS_SPEED_MODE_SDR12)) /* Program the Tap delays */ @@ -823,12 +872,11 @@ s32 XSdPs_Get_Mmc_ExtCsd(XSdPs *InstancePtr, u8 *ReadBuff) XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff); - Xil_DCacheInvalidateRange((INTPTR)ReadBuff, 512U); - - XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, - XSDPS_XFER_MODE_OFFSET, - XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK); + if (InstancePtr->Config.IsCacheCoherent == 0) { + Xil_DCacheInvalidateRange((INTPTR)ReadBuff, 512U); + } + TransferMode = XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK; /* Send SEND_EXT_CSD command */ Status = XSdPs_CmdTransfer(InstancePtr, CMD8, Arg, 1U); @@ -927,7 +975,7 @@ s32 XSdPs_Set_Mmc_ExtCsd(XSdPs *InstancePtr, u32 Arg) } -#if defined (ARMR5) || defined (__aarch64__) +#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) /*****************************************************************************/ /** * @@ -950,7 +998,7 @@ void XSdPs_Identify_UhsMode(XSdPs *InstancePtr, u8 *ReadBuff) Xil_AssertVoid(InstancePtr != NULL); if (((ReadBuff[13] & UHS_SDR104_SUPPORT) != 0U) && - (InstancePtr->Config.InputClockHz >= XSDPS_MMC_HS200_MAX_CLK)) { + (InstancePtr->Config.InputClockHz >= XSDPS_SD_INPUT_MAX_CLK)) { InstancePtr->Mode = XSDPS_UHS_SPEED_MODE_SDR104; InstancePtr->Config_TapDelay = XSdPs_sdr104_hs200_tapdelay; } @@ -997,7 +1045,7 @@ s32 XSdPs_Uhs_ModeInit(XSdPs *InstancePtr, u8 Mode) u32 Arg; u16 BlkCnt; u16 BlkSize; - u8 ReadBuff[64]; + u8 ReadBuff[64] = {0U}; Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); @@ -1013,10 +1061,11 @@ s32 XSdPs_Uhs_ModeInit(XSdPs *InstancePtr, u8 Mode) XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff); - Xil_DCacheFlushRange((INTPTR)ReadBuff, 64); + if (InstancePtr->Config.IsCacheCoherent == 0) { + Xil_DCacheFlushRange((INTPTR)ReadBuff, 64); + } - XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_XFER_MODE_OFFSET, - XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK); + TransferMode = XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK; switch (Mode) { case 0U: @@ -1125,8 +1174,7 @@ static s32 XSdPs_Execute_Tuning(XSdPs *InstancePtr) XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_BLK_SIZE_OFFSET, BlkSize); - XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_XFER_MODE_OFFSET, - XSDPS_TM_DAT_DIR_SEL_MASK); + TransferMode = XSDPS_TM_DAT_DIR_SEL_MASK; CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL2_OFFSET); @@ -1141,7 +1189,7 @@ static s32 XSdPs_Execute_Tuning(XSdPs *InstancePtr) /* Wait for ~60 clock cycles to reset the tap values */ (void)usleep(1U); -#if defined (ARMR5) || defined (__aarch64__) +#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) /* Issue DLL Reset to load new SDHC tuned tap values */ XSdPs_DllReset(InstancePtr); #endif @@ -1165,7 +1213,7 @@ static s32 XSdPs_Execute_Tuning(XSdPs *InstancePtr) } if (TuningCount == 31) { -#if defined (ARMR5) || defined (__aarch64__) +#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) /* Issue DLL Reset to load new SDHC tuned tap values */ XSdPs_DllReset(InstancePtr); #endif @@ -1181,7 +1229,7 @@ static s32 XSdPs_Execute_Tuning(XSdPs *InstancePtr) /* Wait for ~12 clock cycles to synchronize the new tap values */ (void)usleep(1U); -#if defined (ARMR5) || defined (__aarch64__) +#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) /* Issue DLL Reset to load new SDHC tuned tap values */ XSdPs_DllReset(InstancePtr); #endif @@ -1192,7 +1240,7 @@ static s32 XSdPs_Execute_Tuning(XSdPs *InstancePtr) } -#if defined (ARMR5) || defined (__aarch64__) +#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) /*****************************************************************************/ /** * @@ -1213,25 +1261,48 @@ void XSdPs_sdr104_hs200_tapdelay(u32 Bank, u32 DeviceId, u32 CardType) #ifdef XPAR_PSU_SD_0_DEVICE_ID if (DeviceId == 0U) { +#if EL1_NONSECURE && defined (__aarch64__) + (void)TapDelay; + if (Bank == 2) + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_OTAPDLY) | ((u64)SD0_OTAPDLY_SEL_MASK << 32), + (u64)SD0_OTAPDLYSEL_HS200_B2, 0, 0, 0, 0, 0); + else + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_OTAPDLY) | ((u64)SD0_OTAPDLY_SEL_MASK << 32), + (u64)SD0_OTAPDLYSEL_HS200_B0, 0, 0, 0, 0, 0); +#else /* Program the OTAPDLY */ TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY); - TapDelay |= SD0_OTAPDLYENA; - XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay); + TapDelay &= ~SD0_OTAPDLY_SEL_MASK; if (Bank == 2) TapDelay |= SD0_OTAPDLYSEL_HS200_B2; else TapDelay |= SD0_OTAPDLYSEL_HS200_B0; XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay); +#endif } else { #endif + (void) DeviceId; +#if EL1_NONSECURE && defined (__aarch64__) + (void)TapDelay; + if (Bank == 2) + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_OTAPDLY) | ((u64)SD1_OTAPDLY_SEL_MASK << 32), + (u64)SD1_OTAPDLYSEL_HS200_B2, 0, 0, 0, 0, 0); + else + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_OTAPDLY) | ((u64)SD1_OTAPDLY_SEL_MASK << 32), + (u64)SD1_OTAPDLYSEL_HS200_B0, 0, 0, 0, 0, 0); +#else TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY); - TapDelay |= SD1_OTAPDLYENA; - XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay); + TapDelay &= ~SD1_OTAPDLY_SEL_MASK; if (Bank == 2) TapDelay |= SD1_OTAPDLYSEL_HS200_B2; else TapDelay |= SD1_OTAPDLYSEL_HS200_B0; XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay); +#endif #ifdef XPAR_PSU_SD_0_DEVICE_ID } #endif @@ -1258,19 +1329,32 @@ void XSdPs_sdr50_tapdelay(u32 Bank, u32 DeviceId, u32 CardType) #ifdef XPAR_PSU_SD_0_DEVICE_ID if (DeviceId == 0U) { +#if EL1_NONSECURE && defined (__aarch64__) + (void)TapDelay; + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_OTAPDLY) | + ((u64)SD0_OTAPDLY_SEL_MASK << 32), (u64)SD0_OTAPDLYSEL_SD50, + 0, 0, 0, 0, 0); +#else /* Program the OTAPDLY */ TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY); - TapDelay |= SD0_OTAPDLYENA; - XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay); + TapDelay &= ~SD0_OTAPDLY_SEL_MASK; TapDelay |= SD0_OTAPDLYSEL_SD50; XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay); +#endif } else { #endif + (void) DeviceId; +#if EL1_NONSECURE && defined (__aarch64__) + (void)TapDelay; + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_OTAPDLY) | + ((u64)SD1_OTAPDLY_SEL_MASK << 32), (u64)SD1_OTAPDLYSEL_SD50, + 0, 0, 0, 0, 0); +#else TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY); - TapDelay |= SD1_OTAPDLYENA; - XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay); + TapDelay &= ~SD1_OTAPDLY_SEL_MASK; TapDelay |= SD1_OTAPDLYSEL_SD50; XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay); +#endif #ifdef XPAR_PSU_SD_0_DEVICE_ID } #endif @@ -1296,6 +1380,33 @@ void XSdPs_ddr50_tapdelay(u32 Bank, u32 DeviceId, u32 CardType) #ifdef XPAR_PSU_SD_0_DEVICE_ID if (DeviceId == 0U) { +#if EL1_NONSECURE && defined (__aarch64__) + (void)TapDelay; + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) | + ((u64)SD0_ITAPCHGWIN << 32), (u64)SD0_ITAPCHGWIN, + 0, 0, 0, 0, 0); + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) | + ((u64)SD0_ITAPDLYENA << 32), (u64)SD0_ITAPDLYENA, + 0, 0, 0, 0, 0); + if (CardType== XSDPS_CARD_SD) + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_ITAPDLY) | ((u64)SD0_ITAPDLY_SEL_MASK << 32), + (u64)SD0_ITAPDLYSEL_SD_DDR50, 0, 0, 0, 0, 0); + else + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_ITAPDLY) | ((u64)SD0_ITAPDLY_SEL_MASK << 32), + (u64)SD0_ITAPDLYSEL_EMMC_DDR50, 0, 0, 0, 0, 0); + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) | + ((u64)SD0_ITAPCHGWIN << 32), (u64)0x0, 0, 0, 0, 0, 0); + if (CardType == XSDPS_CARD_SD) + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_OTAPDLY) | ((u64)SD0_OTAPDLY_SEL_MASK << 32), + (u64)SD0_OTAPDLYSEL_SD_DDR50, 0, 0, 0, 0, 0); + else + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_OTAPDLY) | ((u64)SD0_OTAPDLY_SEL_MASK << 32), + (u64)SD0_OTAPDLYSEL_EMMC_DDR50, 0, 0, 0, 0, 0); +#else TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY); TapDelay |= SD0_ITAPCHGWIN; XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay); @@ -1311,15 +1422,44 @@ void XSdPs_ddr50_tapdelay(u32 Bank, u32 DeviceId, u32 CardType) XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay); /* Program the OTAPDLY */ TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY); - TapDelay |= SD0_OTAPDLYENA; - XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay); + TapDelay &= ~SD0_OTAPDLY_SEL_MASK; if (CardType == XSDPS_CARD_SD) TapDelay |= SD0_OTAPDLYSEL_SD_DDR50; else TapDelay |= SD0_OTAPDLYSEL_EMMC_DDR50; XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay); +#endif } else { #endif + (void) DeviceId; +#if EL1_NONSECURE && defined (__aarch64__) + (void)TapDelay; + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) | + ((u64)SD1_ITAPCHGWIN << 32), (u64)SD1_ITAPCHGWIN, + 0, 0, 0, 0, 0); + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) | + ((u64)SD1_ITAPDLYENA << 32), (u64)SD1_ITAPDLYENA, + 0, 0, 0, 0, 0); + if (CardType== XSDPS_CARD_SD) + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_ITAPDLY) | ((u64)SD1_ITAPDLY_SEL_MASK << 32), + (u64)SD1_ITAPDLYSEL_SD_DDR50, 0, 0, 0, 0, 0); + else + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_ITAPDLY) | ((u64)SD1_ITAPDLY_SEL_MASK << 32), + (u64)SD1_ITAPDLYSEL_EMMC_DDR50, 0, 0, 0, 0, 0); + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_ITAPDLY) | ((u64)SD1_ITAPCHGWIN << 32), + (u64)0x0, 0, 0, 0, 0, 0); + if (CardType == XSDPS_CARD_SD) + Xil_Smc(MMIO_WRITE_SMC_FID,(u64)(XPS_SYS_CTRL_BASEADDR + + SD_OTAPDLY) | ((u64)SD1_OTAPDLY_SEL_MASK << 32), + (u64)SD1_OTAPDLYSEL_SD_DDR50, 0, 0, 0, 0, 0); + else + Xil_Smc(MMIO_WRITE_SMC_FID,(u64)(XPS_SYS_CTRL_BASEADDR + + SD_OTAPDLY) | ((u64)SD1_OTAPDLY_SEL_MASK << 32), + (u64)SD1_OTAPDLYSEL_EMMC_DDR50, 0, 0, 0, 0, 0); +#else TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY); TapDelay |= SD1_ITAPCHGWIN; XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay); @@ -1335,13 +1475,13 @@ void XSdPs_ddr50_tapdelay(u32 Bank, u32 DeviceId, u32 CardType) XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay); /* Program the OTAPDLY */ TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY); - TapDelay |= SD1_OTAPDLYENA; - XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay); + TapDelay &= ~SD1_OTAPDLY_SEL_MASK; if (CardType == XSDPS_CARD_SD) TapDelay |= SD1_OTAPDLYSEL_SD_DDR50; else TapDelay |= SD1_OTAPDLYSEL_EMMC_DDR50; XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay); +#endif #ifdef XPAR_PSU_SD_0_DEVICE_ID } #endif @@ -1367,6 +1507,28 @@ void XSdPs_hsd_sdr25_tapdelay(u32 Bank, u32 DeviceId, u32 CardType) #ifdef XPAR_PSU_SD_0_DEVICE_ID if (DeviceId == 0U) { +#if EL1_NONSECURE && defined (__aarch64__) + (void)TapDelay; + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) | + ((u64)SD0_ITAPCHGWIN << 32), (u64)SD0_ITAPCHGWIN, + 0, 0, 0, 0, 0); + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) | + ((u64)SD0_ITAPDLYENA << 32), (u64)SD0_ITAPDLYENA, + 0, 0, 0, 0, 0); + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) | + ((u64)SD0_ITAPDLY_SEL_MASK << 32), (u64)SD0_ITAPDLYSEL_HSD, + 0, 0, 0, 0, 0); + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) | + ((u64)SD0_ITAPCHGWIN << 32), (u64)0x0, 0, 0, 0, 0, 0); + if (CardType == XSDPS_CARD_SD) + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_OTAPDLY) | ((u64)SD0_OTAPDLY_SEL_MASK << 32), + (u64)SD0_OTAPDLYSEL_SD_HSD, 0, 0, 0, 0, 0); + else + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_OTAPDLY) | ((u64)SD0_OTAPDLY_SEL_MASK << 32), + (u64)SD0_OTAPDLYSEL_EMMC_HSD, 0, 0, 0, 0, 0); +#else TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY); TapDelay |= SD0_ITAPCHGWIN; XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay); @@ -1379,15 +1541,38 @@ void XSdPs_hsd_sdr25_tapdelay(u32 Bank, u32 DeviceId, u32 CardType) XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay); /* Program the OTAPDLY */ TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY); - TapDelay |= SD0_OTAPDLYENA; - XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay); + TapDelay &= ~SD0_OTAPDLY_SEL_MASK; if (CardType == XSDPS_CARD_SD) TapDelay |= SD0_OTAPDLYSEL_SD_HSD; else TapDelay |= SD0_OTAPDLYSEL_EMMC_HSD; XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay); +#endif } else { #endif + (void) DeviceId; +#if EL1_NONSECURE && defined (__aarch64__) + (void)TapDelay; + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) | + ((u64)SD1_ITAPCHGWIN << 32), (u64)SD1_ITAPCHGWIN, + 0, 0, 0, 0, 0); + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) | + ((u64)SD1_ITAPDLYENA << 32), (u64)SD1_ITAPDLYENA, + 0, 0, 0, 0, 0); + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) | + ((u64)SD1_ITAPDLY_SEL_MASK << 32), (u64)SD1_ITAPDLYSEL_HSD, + 0, 0, 0, 0, 0); + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) | + ((u64)SD1_ITAPCHGWIN << 32), (u64)0x0, 0, 0, 0, 0, 0); + if (CardType == XSDPS_CARD_SD) + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_OTAPDLY) | ((u64)SD1_OTAPDLY_SEL_MASK << 32), + (u64)SD1_OTAPDLYSEL_SD_HSD, 0, 0, 0, 0, 0); + else + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_OTAPDLY) | ((u64)SD1_OTAPDLY_SEL_MASK << 32), + (u64)SD1_OTAPDLYSEL_EMMC_HSD, 0, 0, 0, 0, 0); +#else TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY); TapDelay |= SD1_ITAPCHGWIN; XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay); @@ -1400,13 +1585,13 @@ void XSdPs_hsd_sdr25_tapdelay(u32 Bank, u32 DeviceId, u32 CardType) XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay); /* Program the OTAPDLY */ TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY); - TapDelay |= SD1_OTAPDLYENA; - XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay); + TapDelay &= ~SD1_OTAPDLY_SEL_MASK; if (CardType == XSDPS_CARD_SD) TapDelay |= SD1_OTAPDLYSEL_SD_HSD; else TapDelay |= SD1_OTAPDLYSEL_EMMC_HSD; XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay); +#endif #ifdef XPAR_PSU_SD_0_DEVICE_ID } #endif @@ -1434,20 +1619,48 @@ void XSdPs_SetTapDelay(XSdPs *InstancePtr) CardType = InstancePtr->CardType ; #ifdef XPAR_PSU_SD_0_DEVICE_ID if (DeviceId == 0U) { +#if EL1_NONSECURE && defined (__aarch64__) + (void)DllCtrl; + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_DLL_CTRL) | ((u64)SD0_DLL_RST << 32), + (u64)SD0_DLL_RST, 0, 0, 0, 0, 0); +#else DllCtrl = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL); DllCtrl |= SD0_DLL_RST; XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl); +#endif InstancePtr->Config_TapDelay(BankNum, DeviceId, CardType); +#if EL1_NONSECURE && defined (__aarch64__) + (void)DllCtrl; + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_DLL_CTRL) | ((u64)SD0_DLL_RST << 32), + (u64)0x0, 0, 0, 0, 0, 0); +#else DllCtrl &= ~SD0_DLL_RST; XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl); +#endif } else { #endif +#if EL1_NONSECURE && defined (__aarch64__) + (void)DllCtrl; + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_DLL_CTRL) | ((u64)SD1_DLL_RST << 32), + (u64)SD1_DLL_RST, 0, 0, 0, 0, 0); +#else DllCtrl = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL); DllCtrl |= SD1_DLL_RST; XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl); +#endif InstancePtr->Config_TapDelay(BankNum, DeviceId, CardType); +#if EL1_NONSECURE && defined (__aarch64__) + (void)DllCtrl; + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_DLL_CTRL) | ((u64)SD1_DLL_RST << 32), + (u64)0x0, 0, 0, 0, 0, 0); +#else DllCtrl &= ~SD1_DLL_RST; XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl); +#endif #ifdef XPAR_PSU_SD_0_DEVICE_ID } #endif @@ -1480,11 +1693,26 @@ static void XSdPs_DllReset(XSdPs *InstancePtr) /* Issue DLL Reset to load zero tap values */ DllCtrl = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL); if (InstancePtr->Config.DeviceId == 0U) { +#if EL1_NONSECURE && defined (__aarch64__) + (void)DllCtrl; + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_DLL_CTRL) | ((u64)SD0_DLL_RST << 32), + (u64)SD0_DLL_RST, 0, 0, 0, 0, 0); +#else DllCtrl |= SD0_DLL_RST; + XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl); +#endif } else { +#if EL1_NONSECURE && defined (__aarch64__) + (void)DllCtrl; + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_DLL_CTRL) | ((u64)SD1_DLL_RST << 32), + (u64)SD1_DLL_RST, 0, 0, 0, 0, 0); +#else DllCtrl |= SD1_DLL_RST; + XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl); +#endif } - XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl); /* Wait for 2 micro seconds */ (void)usleep(2U); @@ -1492,11 +1720,26 @@ static void XSdPs_DllReset(XSdPs *InstancePtr) /* Release the DLL out of reset */ DllCtrl = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL); if (InstancePtr->Config.DeviceId == 0U) { +#if EL1_NONSECURE && defined (__aarch64__) + (void)DllCtrl; + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_DLL_CTRL) | ((u64)SD0_DLL_RST << 32), + (u64)0x0, 0, 0, 0, 0, 0); +#else DllCtrl &= ~SD0_DLL_RST; + XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl); +#endif } else { +#if EL1_NONSECURE && defined (__aarch64__) + (void)DllCtrl; + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_DLL_CTRL) | ((u64)SD1_DLL_RST << 32), + (u64)0x0, 0, 0, 0, 0, 0); +#else DllCtrl &= ~SD1_DLL_RST; + XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl); +#endif } - XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl); /* Wait for internal clock to stabilize */ ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sdps_v3_1/src/xsdps_sinit.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/sdps_v3_4/src/xsdps_sinit.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sdps_v3_1/src/xsdps_sinit.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/sdps_v3_4/src/xsdps_sinit.c index e0936b308..b49a0064c 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sdps_v3_1/src/xsdps_sinit.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/sdps_v3_4/src/xsdps_sinit.c @@ -33,7 +33,7 @@ /** * * @file xsdps_sinit.c -* @addtogroup sdps_v2_5 +* @addtogroup sdps_v3_4 * @{ * * The implementation of the XSdPs component's static initialization diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/sleep.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/sleep.h deleted file mode 100644 index 9d0f0ffbf..000000000 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/sleep.h +++ /dev/null @@ -1,49 +0,0 @@ -/****************************************************************************** -* -* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved. -* -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: -* -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. -* -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. -* -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. -* -******************************************************************************/ - -#ifndef SLEEP_H -#define SLEEP_H - -#include "xil_types.h" - -#ifdef __cplusplus -extern "C" { -#endif - -s32 usleep(u32 useconds); -s32 sleep(u32 seconds); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xil_io.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xil_io.c deleted file mode 100644 index de77d6817..000000000 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xil_io.c +++ /dev/null @@ -1,344 +0,0 @@ -/****************************************************************************** -* -* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved. -* -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: -* -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. -* -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. -* -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xil_io.c -* -* Contains I/O functions for memory-mapped or non-memory-mapped I/O -* architectures. These functions encapsulate Cortex A9 architecture-specific -* I/O requirements. -* -* @note -* -* This file contains architecture-dependent code. -* -* 
-* MODIFICATION HISTORY:
-*
-* Ver   Who      Date     Changes
-* ----- -------- -------- -----------------------------------------------
-* 1.00a ecm/sdm  10/24/09 First release
-* 3.06a sgd      05/15/12 Pointer volatile used for the all read functions
-* 3.07a sgd      08/17/12 Removed barriers (SYNCHRONIZE_IO) calls.
-* 3.09a sgd      02/05/13 Comments cleanup
-*
-******************************************************************************/ - - -/***************************** Include Files *********************************/ -#include "xil_io.h" -#include "xil_types.h" -#include "xil_assert.h" -#include "xpseudo_asm.h" -#include "xreg_cortexa9.h" - -/************************** Constant Definitions *****************************/ - -/**************************** Type Definitions *******************************/ - -/***************** Macros (Inline Functions) Definitions *********************/ - -/************************** Function Prototypes ******************************/ - -/*****************************************************************************/ -/** -* -* Performs an input operation for an 8-bit memory location by reading from the -* specified address and returning the Value read from that address. -* -* @param Addr contains the address to perform the input operation -* at. -* -* @return The Value read from the specified input address. -* -* @note None. -* -******************************************************************************/ -u8 Xil_In8(INTPTR Addr) -{ - return *(volatile u8 *) Addr; -} - -/*****************************************************************************/ -/** -* -* Performs an input operation for a 16-bit memory location by reading from the -* specified address and returning the Value read from that address. -* -* @param Addr contains the address to perform the input operation -* at. -* -* @return The Value read from the specified input address. -* -* @note None. -* -******************************************************************************/ -u16 Xil_In16(INTPTR Addr) -{ - return *(volatile u16 *) Addr; -} - -/*****************************************************************************/ -/** -* -* Performs an input operation for a 32-bit memory location by reading from the -* specified address and returning the Value read from that address. -* -* @param Addr contains the address to perform the input operation -* at. -* -* @return The Value read from the specified input address. -* -* @note None. -* -******************************************************************************/ -u32 Xil_In32(UINTPTR Addr) -{ - return *(volatile u32 *) Addr; -} - -/*****************************************************************************/ -/** -* -* Performs an output operation for an 8-bit memory location by writing the -* specified Value to the the specified address. -* -* @param Addr contains the address to perform the output operation -* at. -* @param Value contains the Value to be output at the specified address. -* -* @return None. -* -* @note None. -* -******************************************************************************/ -void Xil_Out8(INTPTR Addr, u8 Value) -{ - volatile u8 *LocalAddr = (u8 *)Addr; - *LocalAddr = Value; -} - -/*****************************************************************************/ -/** -* -* Performs an output operation for a 16-bit memory location by writing the -* specified Value to the the specified address. -* -* @param Addr contains the address to perform the output operation -* at. -* @param Value contains the Value to be output at the specified address. -* -* @return None. -* -* @note None. -* -******************************************************************************/ -void Xil_Out16(INTPTR Addr, u16 Value) -{ - volatile u16 *LocalAddr = (u16 *)Addr; - *LocalAddr = Value; -} - -/*****************************************************************************/ -/** -* -* Performs an output operation for a 32-bit memory location by writing the -* specified Value to the the specified address. -* -* @param Addr contains the address to perform the output operation -* at. -* @param Value contains the Value to be output at the specified address. -* -* @return None. -* -* @note None. -* -******************************************************************************/ -void Xil_Out32(UINTPTR Addr, u32 Value) -{ - volatile u32 *LocalAddr = (u32 *)Addr; - *LocalAddr = Value; -} - -/*****************************************************************************/ -/** -* -* Performs an input operation for a 16-bit memory location by reading from the -* specified address and returning the byte-swapped Value read from that -* address. -* -* @param Addr contains the address to perform the input operation -* at. -* -* @return The byte-swapped Value read from the specified input address. -* -* @note None. -* -******************************************************************************/ -u16 Xil_In16BE(INTPTR Addr) -{ - u16 temp; - u16 result; - - temp = Xil_In16(Addr); - - result = Xil_EndianSwap16(temp); - - return result; -} - -/*****************************************************************************/ -/** -* -* Performs an input operation for a 32-bit memory location by reading from the -* specified address and returning the byte-swapped Value read from that -* address. -* -* @param Addr contains the address to perform the input operation -* at. -* -* @return The byte-swapped Value read from the specified input address. -* -* @note None. -* -******************************************************************************/ -u32 Xil_In32BE(INTPTR Addr) -{ - u32 temp; - u32 result; - - temp = Xil_In32(Addr); - - result = Xil_EndianSwap32(temp); - - return result; -} - -/*****************************************************************************/ -/** -* -* Performs an output operation for a 16-bit memory location by writing the -* specified Value to the the specified address. The Value is byte-swapped -* before being written. -* -* @param Addr contains the address to perform the output operation -* at. -* @param Value contains the Value to be output at the specified address. -* -* @return None. -* -* @note None. -* -******************************************************************************/ -void Xil_Out16BE(INTPTR Addr, u16 Value) -{ - u16 temp; - - temp = Xil_EndianSwap16(Value); - - Xil_Out16(Addr, temp); -} - -/*****************************************************************************/ -/** -* -* Performs an output operation for a 32-bit memory location by writing the -* specified Value to the the specified address. The Value is byte-swapped -* before being written. -* -* @param Addr contains the address to perform the output operation -* at. -* @param Value contains the Value to be output at the specified address. -* -* @return None. -* -* @note None. -* -******************************************************************************/ -void Xil_Out32BE(INTPTR Addr, u32 Value) -{ - u32 temp; - - temp = Xil_EndianSwap32(Value); - - Xil_Out32(Addr, temp); -} - -/*****************************************************************************/ -/** -* -* Perform a 16-bit endian converion. -* -* @param Data contains the value to be converted. -* -* @return converted value. -* -* @note None. -* -******************************************************************************/ -u16 Xil_EndianSwap16(u16 Data) -{ - return (u16) (((Data & 0xFF00U) >> 8U) | ((Data & 0x00FFU) << 8U)); -} - -/*****************************************************************************/ -/** -* -* Perform a 32-bit endian converion. -* -* @param Data contains the value to be converted. -* -* @return converted value. -* -* @note None. -* -******************************************************************************/ -u32 Xil_EndianSwap32(u32 Data) -{ - u16 LoWord; - u16 HiWord; - - /* get each of the half words from the 32 bit word */ - - LoWord = (u16) (Data & 0x0000FFFFU); - HiWord = (u16) ((Data & 0xFFFF0000U) >> 16U); - - /* byte swap each of the 16 bit half words */ - - LoWord = (((LoWord & 0xFF00U) >> 8U) | ((LoWord & 0x00FFU) << 8U)); - HiWord = (((HiWord & 0xFF00U) >> 8U) | ((HiWord & 0x00FFU) << 8U)); - - /* swap the half words before returning the value */ - - return ((((u32)LoWord) << (u32)16U) | (u32)HiWord); -} diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xil_io.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xil_io.h deleted file mode 100644 index 9d4f3b3ee..000000000 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xil_io.h +++ /dev/null @@ -1,246 +0,0 @@ -/****************************************************************************** -* -* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved. -* -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: -* -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. -* -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. -* -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xil_io.h -* -* This file contains the interface for the general IO component, which -* encapsulates the Input/Output functions for processors that do not -* require any special I/O handling. -* -* -* 
-* MODIFICATION HISTORY:
-*
-* Ver   Who      Date     Changes
-* ----- -------- -------- -----------------------------------------------
-* 1.00a ecm/sdm  10/24/09 First release
-* 1.00a sdm      07/21/10 Added Xil_Htonl/s, Xil_Ntohl/s
-* 3.07a asa	     08/31/12 Added xil_printf.h include
-* 3.08a sgd	     11/05/12 Reverted SYNC macros definitions
-*
-******************************************************************************/ - -#ifndef XIL_IO_H /* prevent circular inclusions */ -#define XIL_IO_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************** Include Files *********************************/ - -#include "xil_types.h" -#include "xpseudo_asm.h" -#include "xil_printf.h" - -/************************** Constant Definitions *****************************/ - -/**************************** Type Definitions *******************************/ - -/***************** Macros (Inline Functions) Definitions *********************/ - -#if defined __GNUC__ -# define SYNCHRONIZE_IO dmb() -# define INST_SYNC isb() -# define DATA_SYNC dsb() -#else -# define SYNCHRONIZE_IO -# define INST_SYNC -# define DATA_SYNC -#endif /* __GNUC__ */ - -/*****************************************************************************/ -/** -* -* Perform an big-endian input operation for a 16-bit memory location -* by reading from the specified address and returning the Value read from -* that address. -* -* @param Addr contains the address to perform the input operation at. -* -* @return The Value read from the specified input address with the -* proper endianness. The return Value has the same endianness -* as that of the processor, i.e. if the processor is -* little-engian, the return Value is the byte-swapped Value read -* from the address. -* -* @note None. -* -******************************************************************************/ -#define Xil_In16LE(Addr) Xil_In16((Addr)) - -/*****************************************************************************/ -/** -* -* Perform a big-endian input operation for a 32-bit memory location -* by reading from the specified address and returning the Value read from -* that address. -* -* @param Addr contains the address to perform the input operation at. -* -* @return The Value read from the specified input address with the -* proper endianness. The return Value has the same endianness -* as that of the processor, i.e. if the processor is -* little-engian, the return Value is the byte-swapped Value read -* from the address. -* -* -* @note None. -* -******************************************************************************/ -#define Xil_In32LE(Addr) Xil_In32((Addr)) - -/*****************************************************************************/ -/** -* -* Perform a big-endian output operation for a 16-bit memory location -* by writing the specified Value to the specified address. -* -* @param Addr contains the address to perform the output operation at. -* @param Value contains the Value to be output at the specified address. -* The Value has the same endianness as that of the processor. -* If the processor is little-endian, the byte-swapped Value is -* written to the address. -* -* -* @return None -* -* @note None. -* -******************************************************************************/ -#define Xil_Out16LE(Addr, Value) Xil_Out16((Addr), (Value)) - -/*****************************************************************************/ -/** -* -* Perform a big-endian output operation for a 32-bit memory location -* by writing the specified Value to the specified address. -* -* @param Addr contains the address to perform the output operation at. -* @param Value contains the Value to be output at the specified address. -* The Value has the same endianness as that of the processor. -* If the processor is little-endian, the byte-swapped Value is -* written to the address. -* -* @return None -* -* @note None. -* -******************************************************************************/ -#define Xil_Out32LE(Addr, Value) Xil_Out32((Addr), (Value)) - -/*****************************************************************************/ -/** -* -* Convert a 32-bit number from host byte order to network byte order. -* -* @param Data the 32-bit number to be converted. -* -* @return The converted 32-bit number in network byte order. -* -* @note None. -* -******************************************************************************/ -#define Xil_Htonl(Data) Xil_EndianSwap32((Data)) - -/*****************************************************************************/ -/** -* -* Convert a 16-bit number from host byte order to network byte order. -* -* @param Data the 16-bit number to be converted. -* -* @return The converted 16-bit number in network byte order. -* -* @note None. -* -******************************************************************************/ -#define Xil_Htons(Data) Xil_EndianSwap16((Data)) - -/*****************************************************************************/ -/** -* -* Convert a 32-bit number from network byte order to host byte order. -* -* @param Data the 32-bit number to be converted. -* -* @return The converted 32-bit number in host byte order. -* -* @note None. -* -******************************************************************************/ -#define Xil_Ntohl(Data) Xil_EndianSwap32((Data)) - -/*****************************************************************************/ -/** -* -* Convert a 16-bit number from network byte order to host byte order. -* -* @param Data the 16-bit number to be converted. -* -* @return The converted 16-bit number in host byte order. -* -* @note None. -* -******************************************************************************/ -#define Xil_Ntohs(Data) Xil_EndianSwap16((Data)) - -/************************** Function Prototypes ******************************/ - -/* The following functions allow the software to be transportable across - * processors which may use memory mapped I/O or I/O which is mapped into a - * seperate address space. - */ -u8 Xil_In8(INTPTR Addr); -u16 Xil_In16(INTPTR Addr); -u32 Xil_In32(UINTPTR Addr); - -void Xil_Out8(INTPTR Addr, u8 Value); -void Xil_Out16(INTPTR Addr, u16 Value); -void Xil_Out32(UINTPTR Addr, u32 Value); - - -u16 Xil_In16BE(INTPTR Addr); -u32 Xil_In32BE(INTPTR Addr); -void Xil_Out16BE(INTPTR Addr, u16 Value); -void Xil_Out32BE(INTPTR Addr, u32 Value); - -u16 Xil_EndianSwap16(u16 Data); -u32 Xil_EndianSwap32(u32 Data); - -#ifdef __cplusplus -} -#endif - -#endif /* end of protection macro */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xstatus.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xstatus.h deleted file mode 100644 index 3c8670cb3..000000000 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xstatus.h +++ /dev/null @@ -1,430 +0,0 @@ -/****************************************************************************** -* -* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved. -* -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: -* -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. -* -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. -* -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xstatus.h -* -* This file contains Xilinx software status codes. Status codes have their -* own data type called int. These codes are used throughout the Xilinx -* device drivers. -* -******************************************************************************/ - -#ifndef XSTATUS_H /* prevent circular inclusions */ -#define XSTATUS_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************** Include Files *********************************/ - -#include "xil_types.h" -#include "xil_assert.h" - -/************************** Constant Definitions *****************************/ - -/*********************** Common statuses 0 - 500 *****************************/ - -#define XST_SUCCESS 0L -#define XST_FAILURE 1L -#define XST_DEVICE_NOT_FOUND 2L -#define XST_DEVICE_BLOCK_NOT_FOUND 3L -#define XST_INVALID_VERSION 4L -#define XST_DEVICE_IS_STARTED 5L -#define XST_DEVICE_IS_STOPPED 6L -#define XST_FIFO_ERROR 7L /* an error occurred during an - operation with a FIFO such as - an underrun or overrun, this - error requires the device to - be reset */ -#define XST_RESET_ERROR 8L /* an error occurred which requires - the device to be reset */ -#define XST_DMA_ERROR 9L /* a DMA error occurred, this error - typically requires the device - using the DMA to be reset */ -#define XST_NOT_POLLED 10L /* the device is not configured for - polled mode operation */ -#define XST_FIFO_NO_ROOM 11L /* a FIFO did not have room to put - the specified data into */ -#define XST_BUFFER_TOO_SMALL 12L /* the buffer is not large enough - to hold the expected data */ -#define XST_NO_DATA 13L /* there was no data available */ -#define XST_REGISTER_ERROR 14L /* a register did not contain the - expected value */ -#define XST_INVALID_PARAM 15L /* an invalid parameter was passed - into the function */ -#define XST_NOT_SGDMA 16L /* the device is not configured for - scatter-gather DMA operation */ -#define XST_LOOPBACK_ERROR 17L /* a loopback test failed */ -#define XST_NO_CALLBACK 18L /* a callback has not yet been - registered */ -#define XST_NO_FEATURE 19L /* device is not configured with - the requested feature */ -#define XST_NOT_INTERRUPT 20L /* device is not configured for - interrupt mode operation */ -#define XST_DEVICE_BUSY 21L /* device is busy */ -#define XST_ERROR_COUNT_MAX 22L /* the error counters of a device - have maxed out */ -#define XST_IS_STARTED 23L /* used when part of device is - already started i.e. - sub channel */ -#define XST_IS_STOPPED 24L /* used when part of device is - already stopped i.e. - sub channel */ -#define XST_DATA_LOST 26L /* driver defined error */ -#define XST_RECV_ERROR 27L /* generic receive error */ -#define XST_SEND_ERROR 28L /* generic transmit error */ -#define XST_NOT_ENABLED 29L /* a requested service is not - available because it has not - been enabled */ - -/***************** Utility Component statuses 401 - 500 *********************/ - -#define XST_MEMTEST_FAILED 401L /* memory test failed */ - - -/***************** Common Components statuses 501 - 1000 *********************/ - -/********************* Packet Fifo statuses 501 - 510 ************************/ - -#define XST_PFIFO_LACK_OF_DATA 501L /* not enough data in FIFO */ -#define XST_PFIFO_NO_ROOM 502L /* not enough room in FIFO */ -#define XST_PFIFO_BAD_REG_VALUE 503L /* self test, a register value - was invalid after reset */ -#define XST_PFIFO_ERROR 504L /* generic packet FIFO error */ -#define XST_PFIFO_DEADLOCK 505L /* packet FIFO is reporting - * empty and full simultaneously - */ - -/************************** DMA statuses 511 - 530 ***************************/ - -#define XST_DMA_TRANSFER_ERROR 511L /* self test, DMA transfer - failed */ -#define XST_DMA_RESET_REGISTER_ERROR 512L /* self test, a register value - was invalid after reset */ -#define XST_DMA_SG_LIST_EMPTY 513L /* scatter gather list contains - no buffer descriptors ready - to be processed */ -#define XST_DMA_SG_IS_STARTED 514L /* scatter gather not stopped */ -#define XST_DMA_SG_IS_STOPPED 515L /* scatter gather not running */ -#define XST_DMA_SG_LIST_FULL 517L /* all the buffer desciptors of - the scatter gather list are - being used */ -#define XST_DMA_SG_BD_LOCKED 518L /* the scatter gather buffer - descriptor which is to be - copied over in the scatter - list is locked */ -#define XST_DMA_SG_NOTHING_TO_COMMIT 519L /* no buffer descriptors have been - put into the scatter gather - list to be commited */ -#define XST_DMA_SG_COUNT_EXCEEDED 521L /* the packet count threshold - specified was larger than the - total # of buffer descriptors - in the scatter gather list */ -#define XST_DMA_SG_LIST_EXISTS 522L /* the scatter gather list has - already been created */ -#define XST_DMA_SG_NO_LIST 523L /* no scatter gather list has - been created */ -#define XST_DMA_SG_BD_NOT_COMMITTED 524L /* the buffer descriptor which was - being started was not committed - to the list */ -#define XST_DMA_SG_NO_DATA 525L /* the buffer descriptor to start - has already been used by the - hardware so it can't be reused - */ -#define XST_DMA_SG_LIST_ERROR 526L /* general purpose list access - error */ -#define XST_DMA_BD_ERROR 527L /* general buffer descriptor - error */ - -/************************** IPIF statuses 531 - 550 ***************************/ - -#define XST_IPIF_REG_WIDTH_ERROR 531L /* an invalid register width - was passed into the function */ -#define XST_IPIF_RESET_REGISTER_ERROR 532L /* the value of a register at - reset was not valid */ -#define XST_IPIF_DEVICE_STATUS_ERROR 533L /* a write to the device interrupt - status register did not read - back correctly */ -#define XST_IPIF_DEVICE_ACK_ERROR 534L /* the device interrupt status - register did not reset when - acked */ -#define XST_IPIF_DEVICE_ENABLE_ERROR 535L /* the device interrupt enable - register was not updated when - other registers changed */ -#define XST_IPIF_IP_STATUS_ERROR 536L /* a write to the IP interrupt - status register did not read - back correctly */ -#define XST_IPIF_IP_ACK_ERROR 537L /* the IP interrupt status register - did not reset when acked */ -#define XST_IPIF_IP_ENABLE_ERROR 538L /* IP interrupt enable register was - not updated correctly when other - registers changed */ -#define XST_IPIF_DEVICE_PENDING_ERROR 539L /* The device interrupt pending - register did not indicate the - expected value */ -#define XST_IPIF_DEVICE_ID_ERROR 540L /* The device interrupt ID register - did not indicate the expected - value */ -#define XST_IPIF_ERROR 541L /* generic ipif error */ - -/****************** Device specific statuses 1001 - 4095 *********************/ - -/********************* Ethernet statuses 1001 - 1050 *************************/ - -#define XST_EMAC_MEMORY_SIZE_ERROR 1001L /* Memory space is not big enough - * to hold the minimum number of - * buffers or descriptors */ -#define XST_EMAC_MEMORY_ALLOC_ERROR 1002L /* Memory allocation failed */ -#define XST_EMAC_MII_READ_ERROR 1003L /* MII read error */ -#define XST_EMAC_MII_BUSY 1004L /* An MII operation is in progress */ -#define XST_EMAC_OUT_OF_BUFFERS 1005L /* Driver is out of buffers */ -#define XST_EMAC_PARSE_ERROR 1006L /* Invalid driver init string */ -#define XST_EMAC_COLLISION_ERROR 1007L /* Excess deferral or late - * collision on polled send */ - -/*********************** UART statuses 1051 - 1075 ***************************/ -#define XST_UART - -#define XST_UART_INIT_ERROR 1051L -#define XST_UART_START_ERROR 1052L -#define XST_UART_CONFIG_ERROR 1053L -#define XST_UART_TEST_FAIL 1054L -#define XST_UART_BAUD_ERROR 1055L -#define XST_UART_BAUD_RANGE 1056L - - -/************************ IIC statuses 1076 - 1100 ***************************/ - -#define XST_IIC_SELFTEST_FAILED 1076 /* self test failed */ -#define XST_IIC_BUS_BUSY 1077 /* bus found busy */ -#define XST_IIC_GENERAL_CALL_ADDRESS 1078 /* mastersend attempted with */ - /* general call address */ -#define XST_IIC_STAND_REG_RESET_ERROR 1079 /* A non parameterizable reg */ - /* value after reset not valid */ -#define XST_IIC_TX_FIFO_REG_RESET_ERROR 1080 /* Tx fifo included in design */ - /* value after reset not valid */ -#define XST_IIC_RX_FIFO_REG_RESET_ERROR 1081 /* Rx fifo included in design */ - /* value after reset not valid */ -#define XST_IIC_TBA_REG_RESET_ERROR 1082 /* 10 bit addr incl in design */ - /* value after reset not valid */ -#define XST_IIC_CR_READBACK_ERROR 1083 /* Read of the control register */ - /* didn't return value written */ -#define XST_IIC_DTR_READBACK_ERROR 1084 /* Read of the data Tx reg */ - /* didn't return value written */ -#define XST_IIC_DRR_READBACK_ERROR 1085 /* Read of the data Receive reg */ - /* didn't return value written */ -#define XST_IIC_ADR_READBACK_ERROR 1086 /* Read of the data Tx reg */ - /* didn't return value written */ -#define XST_IIC_TBA_READBACK_ERROR 1087 /* Read of the 10 bit addr reg */ - /* didn't return written value */ -#define XST_IIC_NOT_SLAVE 1088 /* The device isn't a slave */ - -/*********************** ATMC statuses 1101 - 1125 ***************************/ - -#define XST_ATMC_ERROR_COUNT_MAX 1101L /* the error counters in the ATM - controller hit the max value - which requires the statistics - to be cleared */ - -/*********************** Flash statuses 1126 - 1150 **************************/ - -#define XST_FLASH_BUSY 1126L /* Flash is erasing or programming - */ -#define XST_FLASH_READY 1127L /* Flash is ready for commands */ -#define XST_FLASH_ERROR 1128L /* Flash had detected an internal - error. Use XFlash_DeviceControl - to retrieve device specific codes - */ -#define XST_FLASH_ERASE_SUSPENDED 1129L /* Flash is in suspended erase state - */ -#define XST_FLASH_WRITE_SUSPENDED 1130L /* Flash is in suspended write state - */ -#define XST_FLASH_PART_NOT_SUPPORTED 1131L /* Flash type not supported by - driver */ -#define XST_FLASH_NOT_SUPPORTED 1132L /* Operation not supported */ -#define XST_FLASH_TOO_MANY_REGIONS 1133L /* Too many erase regions */ -#define XST_FLASH_TIMEOUT_ERROR 1134L /* Programming or erase operation - aborted due to a timeout */ -#define XST_FLASH_ADDRESS_ERROR 1135L /* Accessed flash outside its - addressible range */ -#define XST_FLASH_ALIGNMENT_ERROR 1136L /* Write alignment error */ -#define XST_FLASH_BLOCKING_CALL_ERROR 1137L /* Couldn't return immediately from - write/erase function with - XFL_NON_BLOCKING_WRITE/ERASE - option cleared */ -#define XST_FLASH_CFI_QUERY_ERROR 1138L /* Failed to query the device */ - -/*********************** SPI statuses 1151 - 1175 ****************************/ - -#define XST_SPI_MODE_FAULT 1151 /* master was selected as slave */ -#define XST_SPI_TRANSFER_DONE 1152 /* data transfer is complete */ -#define XST_SPI_TRANSMIT_UNDERRUN 1153 /* slave underruns transmit register */ -#define XST_SPI_RECEIVE_OVERRUN 1154 /* device overruns receive register */ -#define XST_SPI_NO_SLAVE 1155 /* no slave has been selected yet */ -#define XST_SPI_TOO_MANY_SLAVES 1156 /* more than one slave is being - * selected */ -#define XST_SPI_NOT_MASTER 1157 /* operation is valid only as master */ -#define XST_SPI_SLAVE_ONLY 1158 /* device is configured as slave-only - */ -#define XST_SPI_SLAVE_MODE_FAULT 1159 /* slave was selected while disabled */ -#define XST_SPI_SLAVE_MODE 1160 /* device has been addressed as slave */ -#define XST_SPI_RECEIVE_NOT_EMPTY 1161 /* device received data in slave mode */ - -#define XST_SPI_COMMAND_ERROR 1162 /* unrecognised command - qspi only */ - -/********************** OPB Arbiter statuses 1176 - 1200 *********************/ - -#define XST_OPBARB_INVALID_PRIORITY 1176 /* the priority registers have either - * one master assigned to two or more - * priorities, or one master not - * assigned to any priority - */ -#define XST_OPBARB_NOT_SUSPENDED 1177 /* an attempt was made to modify the - * priority levels without first - * suspending the use of priority - * levels - */ -#define XST_OPBARB_PARK_NOT_ENABLED 1178 /* bus parking by id was enabled but - * bus parking was not enabled - */ -#define XST_OPBARB_NOT_FIXED_PRIORITY 1179 /* the arbiter must be in fixed - * priority mode to allow the - * priorities to be changed - */ - -/************************ Intc statuses 1201 - 1225 **************************/ - -#define XST_INTC_FAIL_SELFTEST 1201 /* self test failed */ -#define XST_INTC_CONNECT_ERROR 1202 /* interrupt already in use */ - -/********************** TmrCtr statuses 1226 - 1250 **************************/ - -#define XST_TMRCTR_TIMER_FAILED 1226 /* self test failed */ - -/********************** WdtTb statuses 1251 - 1275 ***************************/ - -#define XST_WDTTB_TIMER_FAILED 1251L - -/********************** PlbArb statuses 1276 - 1300 **************************/ - -#define XST_PLBARB_FAIL_SELFTEST 1276L - -/********************** Plb2Opb statuses 1301 - 1325 *************************/ - -#define XST_PLB2OPB_FAIL_SELFTEST 1301L - -/********************** Opb2Plb statuses 1326 - 1350 *************************/ - -#define XST_OPB2PLB_FAIL_SELFTEST 1326L - -/********************** SysAce statuses 1351 - 1360 **************************/ - -#define XST_SYSACE_NO_LOCK 1351L /* No MPU lock has been granted */ - -/********************** PCI Bridge statuses 1361 - 1375 **********************/ - -#define XST_PCI_INVALID_ADDRESS 1361L - -/********************** FlexRay constants 1400 - 1409 *************************/ - -#define XST_FR_TX_ERROR 1400 -#define XST_FR_TX_BUSY 1401 -#define XST_FR_BUF_LOCKED 1402 -#define XST_FR_NO_BUF 1403 - -/****************** USB constants 1410 - 1420 *******************************/ - -#define XST_USB_ALREADY_CONFIGURED 1410 -#define XST_USB_BUF_ALIGN_ERROR 1411 -#define XST_USB_NO_DESC_AVAILABLE 1412 -#define XST_USB_BUF_TOO_BIG 1413 -#define XST_USB_NO_BUF 1414 - -/****************** HWICAP constants 1421 - 1429 *****************************/ - -#define XST_HWICAP_WRITE_DONE 1421 - - -/****************** AXI VDMA constants 1430 - 1440 *****************************/ - -#define XST_VDMA_MISMATCH_ERROR 1430 - -/*********************** NAND Flash statuses 1441 - 1459 *********************/ - -#define XST_NAND_BUSY 1441L /* Flash is erasing or - * programming - */ -#define XST_NAND_READY 1442L /* Flash is ready for commands - */ -#define XST_NAND_ERROR 1443L /* Flash had detected an - * internal error. - */ -#define XST_NAND_PART_NOT_SUPPORTED 1444L /* Flash type not supported by - * driver - */ -#define XST_NAND_OPT_NOT_SUPPORTED 1445L /* Operation not supported - */ -#define XST_NAND_TIMEOUT_ERROR 1446L /* Programming or erase - * operation aborted due to a - * timeout - */ -#define XST_NAND_ADDRESS_ERROR 1447L /* Accessed flash outside its - * addressible range - */ -#define XST_NAND_ALIGNMENT_ERROR 1448L /* Write alignment error - */ -#define XST_NAND_PARAM_PAGE_ERROR 1449L /* Failed to read parameter - * page of the device - */ -#define XST_NAND_CACHE_ERROR 1450L /* Flash page buffer error - */ - -#define XST_NAND_WRITE_PROTECTED 1451L /* Flash is write protected - */ - -/**************************** Type Definitions *******************************/ - -typedef s32 XStatus; - -/***************** Macros (Inline Functions) Definitions *********************/ - - -/************************** Function Prototypes ******************************/ - -#ifdef __cplusplus -} -#endif - -#endif /* end of protection macro */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/Makefile b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/Makefile similarity index 91% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/Makefile rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/Makefile index 1536e1d85..8c079ab32 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/Makefile +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/Makefile @@ -43,10 +43,15 @@ CC_FLAGS = $(subst -pg, -DPROFILING, $(COMPILER_FLAGS)) ECC_FLAGS = $(subst -pg, -DPROFILING, $(EXTRA_COMPILER_FLAGS)) ifeq (($(notdir $(CC))) , arm-xilinx-eabi-gcc) +#ECC_FLAGS += -nostartfiles\ +# -march=armv7-a \ +# -mfloat-abi=soft \ +# -mfpu=neon ECC_FLAGS += -nostartfiles\ -march=armv7-a \ -mfloat-abi=soft \ - -mfpu=neon + -mfpu=neongoat + endif ifeq (($(notdir $(CC))) , arm-none-eabi-gcc) @@ -58,7 +63,8 @@ INCLUDEDIR=../../../include INCLUDES=-I./. -I${INCLUDEDIR} OUTS = *.o - +OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c))) +ASSEMBLY_OBJECTS = $(addsuffix .o, $(basename $(wildcard *.S))) INCLUDEFILES=*.h libs: $(LIBS) @@ -81,5 +87,6 @@ profile_includes: $(MAKE) -C profile COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(CC)" ARCHIVER="$(AR)" include clean: - rm -rf ${OUTS} + rm -rf ${OBJECTS} + rm -rf ${ASSEMBLY_OBJECTS} $(MAKE) -C profile COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(CC)" ARCHIVER="$(AR)" clean diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/_exit.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/_exit.c similarity index 100% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/_exit.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/_exit.c diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/_open.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/_open.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/_open.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/_open.c index 9b5a23adf..a108b7716 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/_open.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/_open.c @@ -45,7 +45,7 @@ extern "C" { */ __attribute__((weak)) s32 _open(const char8 *buf, s32 flags, s32 mode) { - (void *)buf; + (void)buf; (void)flags; (void)mode; errno = EIO; diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/_sbrk.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/_sbrk.c similarity index 95% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/_sbrk.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/_sbrk.c index 2a069ec06..967bdfc5b 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/_sbrk.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/_sbrk.c @@ -54,15 +54,10 @@ __attribute__((weak)) caddr_t _sbrk ( s32 incr ) } prev_heap = heap; + if (((heap + incr) <= HeapEndPtr) && (prev_heap != NULL)) { heap += incr; - - if (heap > HeapEndPtr){ - Status = (caddr_t) -1; - } - else if (prev_heap != NULL) { Status = (caddr_t) ((void *)prev_heap); - } - else { + } else { Status = (caddr_t) -1; } diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/abort.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/abort.c similarity index 100% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/abort.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/abort.c diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/asm_vectors.S b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/asm_vectors.S similarity index 100% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/asm_vectors.S rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/asm_vectors.S diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/boot.S b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/boot.S similarity index 84% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/boot.S rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/boot.S index 4dafca8b1..5dfe5c2e7 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/boot.S +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/boot.S @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* Copyright (C) 2010 - 2016 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -33,7 +33,25 @@ /** * @file boot.S * -* This file contains the initial startup code for the Cortex A9 processor +* @addtogroup a9_boot_code Cortex A9 Processor Boot Code +* @{ +*

boot.S

+* The boot code performs minimum configuration which is required for an +* application to run starting from processor's reset state. Below is a +* sequence illustrating what all configuration is performed before control +* reaches to main function. +* +* 1. Program vector table base for exception handling +* 2. Invalidate instruction cache, data cache and TLBs +* 3. Program stack pointer for various modes (IRQ, FIQ, supervisor, undefine, +* abort, system) +* 4. Configure MMU with short descriptor translation table format and program +* base address of translation table +* 5. Enable data cache, instruction cache and MMU +* 6. Enable Floating point unit +* 7. Transfer control to _start which clears BSS sections, initializes +* global timer and runs global constructor before jumping to main +* application * * 
 * MODIFICATION HISTORY:
@@ -62,6 +80,12 @@
 *			 bit in ACTLR. L2Cache invalidation and enabling of L2Cache
 *			 is done later.
 * 5.4   asa     12/6/15  Added code to initialize SPSR for all relevant modes.
+* 6.0   mus     08/04/16 Added code to detect zynq-7000 base silicon configuration and
+*                        attempt to enable dual core behavior on single cpu zynq-7000s
+*                        devices is prevented from corrupting system behavior.
+* 6.0   mus     08/24/16 Check CPU core before putting cpu1 to reset for single core
+*                        zynq-7000s devices
+*
 *
* * @note @@ -102,6 +126,8 @@ .set SLCRlockReg, (PSS_SLCR_BASE_ADDR + 0x04) /*(PSS_SLCR_BASE_ADDR + XPSS_SLCR_LOCK_OFFSET)*/ .set SLCRUnlockReg, (PSS_SLCR_BASE_ADDR + 0x08) /*(PSS_SLCR_BASE_ADDR + XPSS_SLCR_UNLOCK_OFFSET)*/ .set SLCRL2cRamReg, (PSS_SLCR_BASE_ADDR + 0xA1C) /*(PSS_SLCR_BASE_ADDR + XPSS_SLCR_L2C_RAM_OFFSET)*/ +.set SLCRCPURSTReg, (0xF8000000 + 0x244) /*(XPS_SYS_CTRL_BASEADDR + A9_CPU_RST_CTRL_OFFSET)*/ +.set EFUSEStaus, (0xF800D000 + 0x10) /*(XPS_EFUSE_BASEADDR + EFUSE_STATUS_OFFSET)*/ /* workaround for simulation not working when L1 D and I caches,MMU and L2 cache enabled - DT568997 */ .if SIM_MODE == 1 @@ -143,23 +169,50 @@ _prestart: _boot: #if XPAR_CPU_ID==0 -/* only allow cpu0 through */ + /* only allow cpu0 through */ mrc p15,0,r1,c0,c0,5 and r1, r1, #0xf - cmp r1, #0 - beq OKToRun -EndlessLoop0: - wfe + cmp r1, #0 + beq CheckEFUSE + EndlessLoop0: + wfe b EndlessLoop0 +CheckEFUSE: + ldr r0,=EFUSEStaus + ldr r1,[r0] /* Read eFuse setting */ + ands r1,r1,#0x80 /* Check whether device is having single core */ + beq OKToRun + + /* single core device, reset cpu1 */ + ldr r0,=SLCRUnlockReg /* Load SLCR base address base + unlock register */ + ldr r1,=SLCRUnlockKey /* set unlock key */ + str r1, [r0] /* Unlock SLCR */ + + ldr r0,=SLCRCPURSTReg + ldr r1,[r0] /* Read CPU Software Reset Control register */ + orr r1,r1,#0x22 + str r1,[r0] /* Reset CPU1 */ + + ldr r0,=SLCRlockReg /* Load SLCR base address base + lock register */ + ldr r1,=SLCRlockKey /* set lock key */ + str r1, [r0] /* lock SLCR */ + #elif XPAR_CPU_ID==1 -/* only allow cpu1 through */ - mrc p15,0,r1,c0,c0,5 - and r1, r1, #0xf - cmp r1, #1 - beq OKToRun -EndlessLoop1: - wfe + /* only allow cpu1 through */ + mrc p15,0,r1,c0,c0,5 + and r1, r1, #0xf + cmp r1, #1 + beq CheckEFUSE1 + b EndlessLoop1 + +CheckEFUSE1: + ldr r0,=EFUSEStaus + ldr r1,[r0] /* Read eFuse setting */ + ands r1,r1,#0x80 /* Check whether device is having single core */ + beq OKToRun + EndlessLoop1: + wfe b EndlessLoop1 #endif @@ -438,3 +491,6 @@ finished: bx lr .end +/** +* @} End of "addtogroup a9_boot_code". +*/ \ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/bspconfig.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/bspconfig.h similarity index 87% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/bspconfig.h rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/bspconfig.h index 8671e3fbe..9427ad054 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/bspconfig.h +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/bspconfig.h @@ -5,7 +5,7 @@ * Version: * DO NOT EDIT. * -* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.* +* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.* *Permission is hereby granted, free of charge, to any person obtaining a copy *of this software and associated documentation files (the Software), to deal *in the Software without restriction, including without limitation the rights @@ -37,4 +37,9 @@ * *******************************************************************/ +#ifndef BSPCONFIG_H /* prevent circular inclusions */ +#define BSPCONFIG_H /* by using protection macros */ + #define MICROBLAZE_PVR_NONE + +#endif /*end of __BSPCONFIG_H_*/ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/changelog.txt b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/changelog.txt similarity index 71% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/changelog.txt rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/changelog.txt index f663af134..64144403a 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/changelog.txt +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/changelog.txt @@ -399,4 +399,141 @@ * ::hsi::utils::handle_stdin and ::hsi::utils::handle_stdout are taken as a base for * these APIs and modifications are done on top of it to handle stdout/stdin * parameters for design which doesnt have UART.It fixes CR#953681 + * 6.1 nsk 11/07/16 Added two new files xil_mem.c and xil_mem.h for xil_memcpy + * 6.2 pkp 12/14/16 Updated cortexa53/64bit/translation_table.S for upper ps DDR. The 0x800000000 - + * 0xFFFFFFFFF range is marked normal memory for the DDR size defined in hdf + * and rest of the memory in that 32GB region is marked as reserved to avoid + * any speculative access + * 6.2 pkp 12/23/16 Added support for floating point operation to Cortex-A53 64bit mode. It modified + * asm_vectors.S to implement lazy floating point context saving i.e. floating point + * access is enabled if there is any floating point operation, it is disabled by + * default. Also FPU is initally disabled for IRQ and none of the floating point + * registers are saved during normal context saving. If IRQ handler does not require + * floating point operation, the floating point registers are untouched and no need + * for saving/restoring. If IRQ handler uses any floating point operation, then floating + * point registers are saved and FPU is enabled for IRQ handler. Then floating point + * registers are restored back after servicing IRQ during normal context restoring. + * 6.2 mus 01/01/17 Updated makefiles of R5 and a53 64 bit/32 bit processors to fix error in clean + * target.It fixes the CR#966900 + * 6.2 pkp 01/22/17 Added support for EL1 non-secure execution and Hypervisor Baremetal for Cortex-A53 + * 64bit Mode. If Hypervisor_guest is selected as true in BSP settings, BSP will be built + * for EL1 Non-secure, else BSP will be built for EL3. By default hypervisor_guest is + * as false i.e. default bsp is EL3. + * 6.2 pkp 01/24/17 Updated cortexa53/64bit/boot.S to clear FPUStatus variable to make sure that it + * contains initial status of FPU i.e. disabled. In case of a warm restart execution + * when bss sections are not cleared, it may contain previously updated value which + * does not hold true once processor resumes. This fixes CR#966826. + * 6.2 asa 01/31/17 The existing Xil_DCacheDisable API first flushes the + * D caches and then disables it. The problem with that is, + * potentially there will be a small window after the cache + * flush operation and before the we disable D caches where + * we might have valid data in cache lines. In such a + * scenario disabling the D cache can lead to unknown behavior. + * The ideal solution to this is to use assembly code for + * the complete API and avoid any memory accesses. But with + * that we will end up having a huge amount on assembly code + * which is not maintainable. Changes are done to use a mix + * of assembly and C code. All local variables are put in + * registers. Also function calls are avoided in the API to + * avoid using stack memory. + * 6.2 mus 02/13/17 A53 CPU cache system can pre-fetch catch lines.So there are + * scenarios when an invalidated cache line can get pre fetched to cache. + * If that happens, the coherency between cache and memory is lost + * resulting in lost data. To avoid this kind of issue either + * user has to use dsb() or disable pre-fetching for L1 cache + * or else reduce maximum number of outstanding data prefetches allowed. + * Using dsb() while comparing data costing more performance compared to + * disabling pre-fetching/reducing maximum number of outstanding data + * prefetches for L1 Cache.The new api Xil_ConfigureL1Prefetch is added + * to disable pre-fetching/configure maximum number of outstanding data + * prefetches allowed in L1 cache system.This fixes CR#967864. + * 6.2 pkp 02/16/17 Added xil_smc.c file to provide a C wrapper for smc calling which can be + * used by cortex-A53 64bit EL1 Non-secure application. + * 6.2 kvn 03/03/17 Added support thumb mode + * 6.2 mus 03/13/17 Fixed MISRA C mandatory standard violations in ARM cortexr5 and cortexa53 BSP. + * It fixes CR#970543 + * 6.2 asa 03/16/17 Fix for CR#970859. For Mcroblaze BSP, when we enable intrusive + * profiling we see a crash. That is because the the tcl uses invalid + * HSI command. This change fixes it. + * 6.2 mus 03/22/17 Updated standalone tcl to generate xparameter XPAR_FPD_IS_CACHE_COHERENT, if + * any FPD peripheral is configured to use CCI.It fixes CR#972638 + * 6.3 mus 03/20/17 Updated cortex-r5 BSP, to add hard floating point support. + * 6.3 mus 04/17/17 Updated Cortex-a53 32 bit BSP boot code to fix bug in + * the HW coherency enablement. It fixes the CR#973287 + * 6.3 mus 04/20/17 Updated Cortex-A53 64 bit BSP boot code, to remove redundant write to the + * L2CTLR_EL1 register. It fixes the CR#974698 + * 6.4 mus 06/08/17 Updated arm/common/xil_exception.c to fix warnings in C level exception handlers + * of ARM 32 bit processor's. + * 6.4 mus 06/14/17 Updated cortexa53/64bit/gcc/asm_vectors.S to fix bug in IRQInterruptHandler code + * snippet, which checks for the FPEN bit of CPACR_EL1 register. + * 6.4 ms 05/23/17 Added PSU_PMU macro in xplatform_info.c, xparameters.h to support + * XGetPSVersion_Info function for PMUFW. + * ms 06/13/17 Added PSU_PMU macro in xplatform_info.c to support XGetPlatform_Info + * function for PMUFW. + * 6.4 mus 07/05/17 Updated Xil_In32BE function in xil_io.h to fix bug.It fixes CR#979740. + * 6.4 mus 07/25/17 Updated a53 32 bit boot code and vectors to support hard floating point + * operations.Now,VFP is being enabled in FPEXC register, through boot code + * and FPU registers are being saved/restored when irq/fiq vector is invoked. + * 6.4 adk 08/01/17 Updated standalone tcl to generate xparameter XPAR_PL_IS_CACHE_COHERENT, + * if h/w design configured with HPC port. + * 6.4 mus 08/10/17 Updated a53 64 bit translation table to mark memory as a outer shareable for + * EL1 NS execution. This change has been done to support CCI enabled IP's. + * 6.4 mus 08/11/17 Updated a53 64 bit boot code to implement ARM erratum 855873.This fixes + * CR#982209. + * 6.4 asa 08/16/17 Made several changes in the R5 MPU handling logic. Added new APIs to + * make RPU MPU handling user-friendly. This also fixes the CR-981028. + * 6.4 mus 08/17/17 Updated XGet_Zynq_UltraMp_Platform_info and XGetPSVersion_Info APIs to read + * version register through SMC call, over EL1 NS mode. This change has been done to + * support these APIs over EL1 NS mode. + * 6.5 mus 10/20/17 Updated standalone.tcl to fix bug in mb_can_handle_exceptions_in_delay_slots proc, + * it fixes CR#987464. + * 6.6 mus 12/07/17 Updated cortexa9/xil_errata.h and cortexa9/xil_cache.c to remove Errata 753970. + * It fixes CR#989132. + * srm 10/18/17 Updated all the sleep routines in a9,a53,R5,microblaze. Now the sleep routines + * will use the timer specified by the user to provide delay. A9 and A53 can use + * Global timer or TTC. R5 can use TTC or the machine cycles. Microblaze can use + * machine cycles or Axi timer. Updated standalone.tcl and standalone.mld files + * to support the sleep configuration Added new API's for the Axi timer in + * microblaze and TTC in ARM. Added two new files, xil_sleeptimer.c and + * xil_sleeptimer.h in ARM for the common sleep routines and 1 new file, + * xil_sleepcommon.c in Standalone-common for sleep/usleep API's. + * 6.6 hk 12/15/17 Export platform macros to bspconfig.h based on the processor. + * 6.6 asa 1/16/18 Ensure C stack information for A9 are flushed out from L1 D cache + * or L2 cache only when the respective caches are enabled. This fixes CR-922023. + * 6.6 mus 01/19/18 Updated asm_vectors.S and boot.S in Cortexa53 64 bit BSP, to add isb + * after writing to cpacr_el1/cptr_el3 registers. It would ensure + * disabling/enabling of floating-point unit, before any subsequent + * instruction. + * 6.6 mus 01/30/18 Updated hypervisor enabled Cortexa53 64 bit BSP, to add xen PV console + * support. Now, xil_printf would use PV console instead of UART in case of + * hypervisor enabled BSP. + * 6.6 mus 02/02/18 Updated get_connected_if proc in standalone tcl to detect the HPC port + * configured with smart interconnect.It fixes CR#990318. + * 6.6 srm 02/10/18 Updated csu_wdt interrupt to the correct value. Fixes CR#992229 + * 6.6 asa 02/12/18 Fix for heap handling for ARM platforms. CR#993932. + * 6.6 mus 02/19/18 Updated standalone.tcl to fix bug in handle_profile_opbtimer proc, + * CR#995014. + * 6.6 mus 02/23/18 Presently Cortex R5 BSP boot code is disabling the debug logic in +* non-JTAG boot mode, when processor is in lockstep configuration. +* This behavior is restricting application debugging in non-JTAG boot +* mode. To get rid of this restriction, added new mld parameter +* "lockstep_mode_debug", to enable/disable debug logic from BSP +* settings. Now, debug logic can be enabled through BSP settings, +* by modifying value of parameter "lockstep_mode_debug" as "true". +* It fixes CR#993896. + * 6.6.mus 02/27/18 Updated Xil_DCacheInvalidateRange and +* Xil_ICacheInvalidateRange APIs in Cortexa53 64 bit BSP, to fix bug +* in handling upper DDR addresses.It fixes CR#995581. +* 6.6 mus 03/12/18 Updated makefile of Cortexa53 32bit BSP to add includes_ps directory +* in the list of include paths. This change allows applications/BSP +* files to include .h files in include_ps directory. +* 6.6 mus 03/16/18 By default CPUACTLR_EL1 is accessible only from EL3, it +* results into abort if accessed from EL1 non secure privilege +* level. Updated Xil_ConfigureL1Prefetch function in Cortexa53 64 bit BSP +* to avoid CPUACTLR_EL1 access from privile levels other than EL3. +* 6.6 mus 03/16/18 Updated hypervisor enabled BSP to use PV console, based on the +* XEN_USE_PV_CONSOLE flag. By deafault hypervisor enabled BSP would +* use UART console, PV console can be enabled by appending + "-DXEN_USE_PV_CONSOLE" to the BSP extra compiler flags. + * *****************************************************************************************/ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/close.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/close.c similarity index 100% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/close.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/close.c diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/config.make b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/config.make similarity index 100% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/config.make rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/config.make diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/cpu_init.S b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/cpu_init.S similarity index 100% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/cpu_init.S rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/cpu_init.S diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/errno.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/errno.c similarity index 100% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/errno.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/errno.c diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/fcntl.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/fcntl.c similarity index 100% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/fcntl.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/fcntl.c diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/fstat.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/fstat.c similarity index 100% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/fstat.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/fstat.c diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/getpid.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/getpid.c similarity index 100% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/getpid.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/getpid.c diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/inbyte.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/inbyte.c similarity index 100% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/inbyte.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/inbyte.c diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/isatty.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/isatty.c similarity index 100% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/isatty.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/isatty.c diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/kill.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/kill.c similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/kill.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/kill.c diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/lseek.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/lseek.c similarity index 100% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/lseek.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/lseek.c diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/open.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/open.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/open.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/open.c index 4b51839fd..85e9ce402 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/open.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/open.c @@ -44,7 +44,7 @@ extern "C" { */ __attribute__((weak)) s32 open(char8 *buf, s32 flags, s32 mode) { - (void *)buf; + (void)buf; (void)flags; (void)mode; errno = EIO; diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/outbyte.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/outbyte.c similarity index 100% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/outbyte.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/outbyte.c diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/print.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/print.c similarity index 90% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/print.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/print.c index 74d70ee4a..da7e768d0 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/print.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/print.c @@ -21,6 +21,9 @@ void print(const char8 *ptr) { +#if HYP_GUEST && EL1_NONSECURE && XEN_USE_PV_CONSOLE + XPVXenConsole_Write(ptr); +#else #ifdef STDOUT_BASEADDRESS while (*ptr != (char8)0) { outbyte (*ptr); @@ -29,4 +32,5 @@ void print(const char8 *ptr) #else (void)ptr; #endif +#endif } diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/profile/Makefile b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/profile/Makefile similarity index 100% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/profile/Makefile rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/profile/Makefile diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/profile/_profile_clean.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/profile/_profile_clean.c similarity index 100% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/profile/_profile_clean.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/profile/_profile_clean.c diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/profile/_profile_init.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/profile/_profile_init.c similarity index 100% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/profile/_profile_init.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/profile/_profile_init.c diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/profile/_profile_timer_hw.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/profile/_profile_timer_hw.c similarity index 100% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/profile/_profile_timer_hw.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/profile/_profile_timer_hw.c diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/profile/_profile_timer_hw.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/profile/_profile_timer_hw.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/profile/_profile_timer_hw.h rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/profile/_profile_timer_hw.h diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/profile/dummy.S b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/profile/dummy.S similarity index 100% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/profile/dummy.S rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/profile/dummy.S diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/profile/mblaze_nt_types.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/profile/mblaze_nt_types.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/profile/mblaze_nt_types.h rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/profile/mblaze_nt_types.h diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/profile/profile.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/profile/profile.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/profile/profile.h rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/profile/profile.h diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/profile/profile_cg.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/profile/profile_cg.c similarity index 100% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/profile/profile_cg.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/profile/profile_cg.c diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/profile/profile_config.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/profile/profile_config.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/profile/profile_config.h rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/profile/profile_config.h diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/profile/profile_hist.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/profile/profile_hist.c similarity index 100% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/profile/profile_hist.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/profile/profile_hist.c diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/profile/profile_mcount_arm.S b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/profile/profile_mcount_arm.S similarity index 100% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/profile/profile_mcount_arm.S rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/profile/profile_mcount_arm.S diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/profile/profile_mcount_mb.S b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/profile/profile_mcount_mb.S similarity index 100% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/profile/profile_mcount_mb.S rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/profile/profile_mcount_mb.S diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/profile/profile_mcount_ppc.S b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/profile/profile_mcount_ppc.S similarity index 100% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/profile/profile_mcount_ppc.S rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/profile/profile_mcount_ppc.S diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/putnum.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/putnum.c similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/putnum.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/putnum.c diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/read.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/read.c similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/read.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/read.c diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/sbrk.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/sbrk.c similarity index 94% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/sbrk.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/sbrk.c index 64d5156af..87a753d49 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/sbrk.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/sbrk.c @@ -51,12 +51,8 @@ __attribute__((weak)) char8 *sbrk (s32 nbytes) static char8 *heap_ptr = HeapBase; base = heap_ptr; - if(heap_ptr != NULL) { + if((heap_ptr != NULL) && (heap_ptr + nbytes <= (char8 *)&HeapLimit + 1)) { heap_ptr += nbytes; - } - -/* if (heap_ptr <= ((char8 *)&_heap_end + 1)) */ - if (heap_ptr <= ((char8 *)&HeapLimit + 1)) { return base; } else { errno = ENOMEM; diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/sleep.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/sleep.c similarity index 78% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/sleep.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/sleep.c index fe4707af3..f85743b47 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/sleep.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/sleep.c @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved. +* Copyright (C) 2009 - 2017 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -42,7 +42,12 @@ * Ver Who Date Changes * ----- -------- -------- ----------------------------------------------- * 1.00a ecm/sdm 11/11/09 First release -* 3.07a sgd 07/05/12 Updated sleep function to make use Global Timer +* 3.07a sgd 07/05/12 Updated sleep function to make use Global +* 6.0 asa 08/15/16 Updated the sleep signature. Fix for CR#956899. +* 6.6 srm 10/18/17 Updated sleep routines to support user configurable +* implementation. Now sleep routines will use Timer +* specified by the user (i.e. Global timer/TTC timer) +* * * ******************************************************************************/ @@ -52,6 +57,10 @@ #include "xtime_l.h" #include "xparameters.h" +#if defined (SLEEP_TIMER_BASEADDR) +#include "xil_sleeptimer.h" +#endif + /*****************************************************************************/ /* * @@ -64,16 +73,20 @@ * @note None. * ****************************************************************************/ -s32 sleep(u32 seconds) +unsigned sleep_A9(unsigned int seconds) { - XTime tEnd, tCur; +#if defined (SLEEP_TIMER_BASEADDR) + Xil_SleepTTCCommon(seconds, COUNTS_PER_SECOND); +#else + XTime tEnd, tCur; - XTime_GetTime(&tCur); - tEnd = tCur + (((XTime) seconds) * COUNTS_PER_SECOND); - do - { - XTime_GetTime(&tCur); - } while (tCur < tEnd); + XTime_GetTime(&tCur); + tEnd = tCur + (((XTime) seconds) * COUNTS_PER_SECOND); + do + { + XTime_GetTime(&tCur); + } while (tCur < tEnd); +#endif return 0; } diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/sleep.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/sleep.h new file mode 100644 index 000000000..f53b2d8c8 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/sleep.h @@ -0,0 +1,119 @@ +/****************************************************************************** +* +* Copyright (C) 2014 - 2017 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +/*****************************************************************************/ +/** +* @file sleep.h +* +* This header file contains ARM Cortex A53,A9,R5,Microblaze specific sleep +* related APIs. +* +* 
+* MODIFICATION HISTORY :
+*
+* Ver   Who  Date	 Changes
+* ----- ---- -------- -------------------------------------------------------
+* 6.6   srm  11/02/17 Added processor specific sleep rountines
+*								 function prototypes.
+*
+*
+* +******************************************************************************/ + +#ifndef SLEEP_H +#define SLEEP_H + +#include "xil_types.h" +#include "xil_io.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/*****************************************************************************/ +/** +* +* This macro polls an address periodically until a condition is met or till the +* timeout occurs. +* The minimum timeout for calling this macro is 100us. If the timeout is less +* than 100us, it still waits for 100us. Also the unit for the timeout is 100us. +* If the timeout is not a multiple of 100us, it waits for a timeout of +* the next usec value which is a multiple of 100us. +* +* @param IO_func - accessor function to read the register contents. +* Depends on the register width. +* @param ADDR - Address to be polled +* @param VALUE - variable to read the value +* @param COND - Condition to checked (usually involves VALUE) +* @param TIMEOUT_US - timeout in micro seconds +* +* @return 0 - when the condition is met +* -1 - when the condition is not met till the timeout period +* +* @note none +* +*****************************************************************************/ +#define Xil_poll_timeout(IO_func, ADDR, VALUE, COND, TIMEOUT_US) \ + ( { \ + u64 timeout = TIMEOUT_US/100; \ + if(TIMEOUT_US%100!=0) \ + timeout++; \ + for(;;) { \ + VALUE = IO_func(ADDR); \ + if(COND) \ + break; \ + else { \ + usleep(100); \ + timeout--; \ + if(timeout==0) \ + break; \ + } \ + } \ + (timeout>0) ? 0 : -1; \ + } ) + +void usleep(unsigned long useconds); +void sleep(unsigned int seconds); +int usleep_R5(unsigned long useconds); +unsigned sleep_R5(unsigned int seconds); +int usleep_MB(unsigned long useconds); +unsigned sleep_MB(unsigned int seconds); +int usleep_A53(unsigned long useconds); +unsigned sleep_A53(unsigned int seconds); +int usleep_A9(unsigned long useconds); +unsigned sleep_A9(unsigned int seconds); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/smc.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/smc.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/smc.h rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/smc.h diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/translation_table.S b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/translation_table.S similarity index 72% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/translation_table.S rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/translation_table.S index 6aeca4cf9..ade44de2b 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/translation_table.S +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/translation_table.S @@ -33,8 +33,42 @@ /** * @file translation_table.s * -* This file contains the initialization for the MMU table in RAM -* needed by the Cortex A9 processor +* @addtogroup a9_boot_code +* @{ +*

translation_table.S

+* translation_table.S contains a static page table required by MMU for +* cortex-A9. This translation table is flat mapped (input address = output +* address) with default memory attributes defined for zynq architecture. It +* utilizes short descriptor translation table format with each section defining +* 1MB of memory. +* +* The overview of translation table memory attributes is described below. +* +*| | Memory Range | Definition in Translation Table | +*|-----------------------|-------------------------|-----------------------------------| +*| DDR | 0x00000000 - 0x3FFFFFFF | Normal write-back Cacheable | +*| PL | 0x40000000 - 0xBFFFFFFF | Strongly Ordered | +*| Reserved | 0xC0000000 - 0xDFFFFFFF | Unassigned | +*| Memory mapped devices | 0xE0000000 - 0xE02FFFFF | Device Memory | +*| Reserved | 0xE0300000 - 0xE0FFFFFF | Unassigned | +*| NAND, NOR | 0xE1000000 - 0xE3FFFFFF | Device memory | +*| SRAM | 0xE4000000 - 0xE5FFFFFF | Normal write-back Cacheable | +*| Reserved | 0xE6000000 - 0xF7FFFFFF | Unassigned | +*| AMBA APB Peripherals | 0xF8000000 - 0xF8FFFFFF | Device Memory | +*| Reserved | 0xF9000000 - 0xFBFFFFFF | Unassigned | +*| Linear QSPI - XIP | 0xFC000000 - 0xFDFFFFFF | Normal write-through cacheable | +*| Reserved | 0xFE000000 - 0xFFEFFFFF | Unassigned | +*| OCM | 0xFFF00000 - 0xFFFFFFFF | Normal inner write-back cacheable | +* +* @note +* +* For region 0x00000000 - 0x3FFFFFFF, a system where DDR is less than 1GB, +* region after DDR and before PL is marked as undefined/reserved in translation +* table. In 0xF8000000 - 0xF8FFFFFF, 0xF8000C00 - 0xF8000FFF, 0xF8010000 - +* 0xF88FFFFF and 0xF8F03000 to 0xF8FFFFFF are reserved but due to granual size +* of 1MB, it is not possible to define separate regions for them. For region +* 0xFFF00000 - 0xFFFFFFFF, 0xFFF00000 to 0xFFFB0000 is reserved but due to 1MB +* granual size, it is not possible to define separate region for it * * 
 * MODIFICATION HISTORY:
@@ -54,11 +88,9 @@
 * 5.2	pkp  06/08/2015 put a check for XPAR_PS7_DDR_0_S_AXI_BASEADDR to confirm
 *			if DDR is present or not and accordingly generate the
 *			translation table
+* 6.1	pkp  07/11/2016 Corrected comments for memory attributes
 *
* -* @note -* -* None. * ******************************************************************************/ #include "xparameters.h" @@ -101,12 +133,12 @@ MMUTable: .rept 0x0400 /* 0x40000000 - 0x7fffffff (FPGA slave0) */ -.word SECT + 0xc02 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */ +.word SECT + 0xc02 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b0 */ .set SECT, SECT+0x100000 .endr .rept 0x0400 /* 0x80000000 - 0xbfffffff (FPGA slave1) */ -.word SECT + 0xc02 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b1 */ +.word SECT + 0xc02 /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b0, B=b0 */ .set SECT, SECT+0x100000 .endr @@ -166,7 +198,7 @@ MMUTable: .endr .rept 0x0020 /* 0xfc000000 - 0xfdffffff (Linear QSPI - XIP) */ -.word SECT + 0xc0a /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b1, B=b1 */ +.word SECT + 0xc0a /* S=b0 TEX=b000 AP=b11, Domain=b0, C=b1, B=b0 */ .set SECT, SECT+0x100000 .endr @@ -179,10 +211,13 @@ MMUTable: /* 0xfff00000 to 0xfffb0000 is reserved but due to granual size of 1MB, it is not possible to define separate region for it -/* 0xfff00000 - 0xffffffff + 0xfff00000 - 0xffffffff 256K OCM when mapped to high address space inner-cacheable */ .word SECT + 0x4c0e /* S=b0 TEX=b100 AP=b11, Domain=b0, C=b1, B=b1 */ .set SECT, SECT+0x100000 .end +/** +* @} End of "addtogroup a9_boot_code". +*/ \ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/unlink.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/unlink.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/unlink.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/unlink.c index 84e44a47c..d0cc6807b 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/unlink.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/unlink.c @@ -44,7 +44,7 @@ extern "C" { */ __attribute__((weak)) sint32 unlink(char8 *path) { - (void *)path; + (void) path; errno = EIO; return (-1); } diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/usleep.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/usleep.c similarity index 81% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/usleep.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/usleep.c index a4b23f2f3..65eea28cf 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/usleep.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/usleep.c @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved. +* Copyright (C) 2009 - 2017 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -47,6 +47,10 @@ * 4.2 pkp 08/04/14 Removed unimplemented nanosleep routine as it is not * possible to generate timer in nanosecond due to * limited cpu frequency +* 6.0 asa 08/15/16 Updated the usleep signature. Fix for CR#956899. +* 6.6 srm 10/18/17 Updated sleep routines to support user configurable +* implementation. Now sleep routines will use Timer +* specified by the user (i.e. Global timer/TTC timer) * * ******************************************************************************/ @@ -59,8 +63,17 @@ #include "xpseudo_asm.h" #include "xreg_cortexa9.h" +#if defined (SLEEP_TIMER_BASEADDR) +#include "xil_sleeptimer.h" +#endif + +/**************************** Constant Definitions ************************/ +#if defined (SLEEP_TIMER_BASEADDR) +#define COUNTS_PER_USECOND (SLEEP_TIMER_FREQUENCY / 1000000) +#else /* Global Timer is always clocked at half of the CPU frequency */ #define COUNTS_PER_USECOND (XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ / (2U*1000000U)) +#endif /*****************************************************************************/ /** @@ -75,8 +88,11 @@ * @note None. * ****************************************************************************/ -s32 usleep(u32 useconds) +int usleep_A9(unsigned long useconds) { +#if defined (SLEEP_TIMER_BASEADDR) + Xil_SleepTTCCommon(useconds, COUNTS_PER_USECOND); +#else XTime tEnd, tCur; XTime_GetTime(&tCur); @@ -85,6 +101,7 @@ s32 usleep(u32 useconds) { XTime_GetTime(&tCur); } while (tCur < tEnd); +#endif return 0; } diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/vectors.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/vectors.c similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/vectors.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/vectors.c diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/vectors.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/vectors.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/vectors.h rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/vectors.h diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/write.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/write.c similarity index 93% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/write.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/write.c index aaa879e73..9389f610a 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/write.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/write.c @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved. +* Copyright (C) 2009 - 2018 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -82,6 +82,14 @@ write (sint32 fd, char8* buf, sint32 nbytes) __attribute__((weak)) sint32 _write (sint32 fd, char8* buf, sint32 nbytes) { +#if HYP_GUEST && EL1_NONSECURE && XEN_USE_PV_CONSOLE + sint32 length; + + (void)fd; + (void)nbytes; + length = XPVXenConsole_Write(buf); + return length; +#else #ifdef STDOUT_BASEADDRESS s32 i; char8* LocalBuf = buf; @@ -108,5 +116,6 @@ _write (sint32 fd, char8* buf, sint32 nbytes) (void)nbytes; return 0; #endif +#endif } #endif diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xbasic_types.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xbasic_types.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xbasic_types.h rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xbasic_types.h diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xdebug.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xdebug.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xdebug.h rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xdebug.h diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xenv.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xenv.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xenv.h rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xenv.h diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xenv_standalone.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xenv_standalone.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xenv_standalone.h rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xenv_standalone.h diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xil-crt0.S b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil-crt0.S similarity index 91% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xil-crt0.S rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil-crt0.S index 64175fef9..6beb6fd15 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xil-crt0.S +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil-crt0.S @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved. +* Copyright (C) 2009 - 2017 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -48,6 +48,9 @@ * initialization of uart smc nor and sram * 5.3 pkp 10/07/15 Added support for OpenAMP by not initializing global * timer when USE_AMP flag is defined +* 6.6 srm 10/18/17 Added timer configuration using XTime_StartTTCTimer API. +* Now the TTC instance as specified by the user will be +* started. * * * @note @@ -55,6 +58,7 @@ * None. * ******************************************************************************/ +#include "bspconfig.h" .file "xil-crt0.S" .section ".got2","aw" @@ -113,6 +117,11 @@ _start: mov r0, #0x0 mov r1, #0x0 + /* Reset and start Triple Timer Counter */ + #if defined SLEEP_TIMER_BASEADDR + bl XTime_StartTTCTimer + #endif + #if USE_AMP != 1 bl XTime_SetTime #endif diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_assert.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_assert.c similarity index 83% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_assert.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_assert.c index 3087fe80f..59b3c1c98 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_assert.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_assert.c @@ -82,12 +82,13 @@ static Xil_AssertCallback Xil_AssertCallbackRoutine = NULL; /*****************************************************************************/ /** * -* Implement assert. Currently, it calls a user-defined callback function -* if one has been set. Then, it potentially enters an infinite loop depending -* on the value of the Xil_AssertWait variable. +* @brief Implement assert. Currently, it calls a user-defined callback +* function if one has been set. Then, it potentially enters an +* infinite loop depending on the value of the Xil_AssertWait +* variable. * -* @param file is the name of the filename of the source -* @param line is the linenumber within File +* @param file: filename of the source +* @param line: linenumber within File * * @return None. * @@ -111,10 +112,10 @@ void Xil_Assert(const char8 *File, s32 Line) /*****************************************************************************/ /** * -* Set up a callback function to be invoked when an assert occurs. If there -* was already a callback installed, then it is replaced. +* @brief Set up a callback function to be invoked when an assert occurs. +* If a callback is already installed, then it will be replaced. * -* @param routine is the callback to be invoked when an assert is taken +* @param routine: callback to be invoked when an assert is taken * * @return None. * @@ -129,11 +130,11 @@ void Xil_AssertSetCallback(Xil_AssertCallback Routine) /*****************************************************************************/ /** * -* Null handler function. This follows the XInterruptHandler signature for -* interrupt handlers. It can be used to assign a null handler (a stub) to an -* interrupt controller vector table. +* @brief Null handler function. This follows the XInterruptHandler +* signature for interrupt handlers. It can be used to assign a null +* handler (a stub) to an interrupt controller vector table. * -* @param NullParameter is an arbitrary void pointer and not used. +* @param NullParameter: arbitrary void pointer and not used. * * @return None. * @@ -142,5 +143,5 @@ void Xil_AssertSetCallback(Xil_AssertCallback Routine) ******************************************************************************/ void XNullHandler(void *NullParameter) { - (void *) NullParameter; + (void) NullParameter; } diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_assert.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_assert.h similarity index 77% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_assert.h rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_assert.h index 1e3c17b50..add4124e2 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_assert.h +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_assert.h @@ -34,8 +34,15 @@ * * @file xil_assert.h * -* This file contains assert related functions. +* @addtogroup common_assert_apis Assert APIs and Macros * +* The xil_assert.h file contains assert related functions and macros. +* Assert APIs/Macros specifies that a application program satisfies certain +* conditions at particular points in its execution. These function can be +* used by application programs to ensure that, application code is satisfying +* certain conditions. +* +* @{ * 
 * MODIFICATION HISTORY:
 *
@@ -83,18 +90,17 @@ typedef void (*Xil_AssertCallback) (const char8 *File, s32 Line);
 
 /*****************************************************************************/
 /**
-* This assert macro is to be used for functions that do not return anything
-* (void). This in conjunction with the Xil_AssertWait boolean can be used to
-* accomodate tests so that asserts which fail allow execution to continue.
+* @brief    This assert macro is to be used for void functions. This in
+*           conjunction with the Xil_AssertWait boolean can be used to
+*           accomodate tests so that asserts which fail allow execution to
+*           continue.
 *
-* @param    Expression is the expression to evaluate. If it evaluates to
+* @param    Expression: expression to be evaluated. If it evaluates to
 *           false, the assert occurs.
 *
 * @return   Returns void unless the Xil_AssertWait variable is true, in which
 *           case no return is made and an infinite loop is entered.
 *
-* @note     None.
-*
 ******************************************************************************/
 #define Xil_AssertVoid(Expression)                \
 {                                                  \
@@ -109,17 +115,16 @@ typedef void (*Xil_AssertCallback) (const char8 *File, s32 Line);
 
 /*****************************************************************************/
 /**
-* This assert macro is to be used for functions that do return a value. This in
-* conjunction with the Xil_AssertWait boolean can be used to accomodate tests
-* so that asserts which fail allow execution to continue.
+* @brief    This assert macro is to be used for functions that do return a
+*           value. This in conjunction with the Xil_AssertWait boolean can be
+*           used to accomodate tests so that asserts which fail allow execution
+*           to continue.
 *
-* @param    Expression is the expression to evaluate. If it evaluates to false,
+* @param    Expression: expression to be evaluated. If it evaluates to false,
 *           the assert occurs.
 *
 * @return   Returns 0 unless the Xil_AssertWait variable is true, in which
-* 	    case no return is made and an infinite loop is entered.
-*
-* @note     None.
+* 	        case no return is made and an infinite loop is entered.
 *
 ******************************************************************************/
 #define Xil_AssertNonvoid(Expression)             \
@@ -135,14 +140,11 @@ typedef void (*Xil_AssertCallback) (const char8 *File, s32 Line);
 
 /*****************************************************************************/
 /**
-* Always assert. This assert macro is to be used for functions that do not
-* return anything (void). Use for instances where an assert should always
-* occur.
+* @brief     Always assert. This assert macro is to be used for void functions.
+*            Use for instances where an assert should always occur.
 *
-* @return Returns void unless the Xil_AssertWait variable is true, in which
-*	  case no return is made and an infinite loop is entered.
-*
-* @note   None.
+* @return    Returns void unless the Xil_AssertWait variable is true, in which
+*	         case no return is made and an infinite loop is entered.
 *
 ******************************************************************************/
 #define Xil_AssertVoidAlways()                   \
@@ -154,13 +156,12 @@ typedef void (*Xil_AssertCallback) (const char8 *File, s32 Line);
 
 /*****************************************************************************/
 /**
-* Always assert. This assert macro is to be used for functions that do return
-* a value. Use for instances where an assert should always occur.
+* @brief   Always assert. This assert macro is to be used for functions that
+*          do return a value. Use for instances where an assert should always
+*          occur.
 *
 * @return Returns void unless the Xil_AssertWait variable is true, in which
-*	  case no return is made and an infinite loop is entered.
-*
-* @note   None.
+*	      case no return is made and an infinite loop is entered.
 *
 ******************************************************************************/
 #define Xil_AssertNonvoidAlways()                \
@@ -189,3 +190,6 @@ void Xil_AssertSetCallback(Xil_AssertCallback Routine);
 #endif
 
 #endif	/* end of protection macro */
+/**
+* @} End of "addtogroup common_assert_apis".
+*/
\ No newline at end of file
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xil_cache.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_cache.c
similarity index 72%
rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xil_cache.c
rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_cache.c
index 217767e34..259c3b1f1 100644
--- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xil_cache.c
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_cache.c
@@ -92,6 +92,12 @@
 * 5.03	 pkp 10/07/15 L2 Cache functionalities are avoided for the OpenAMP slave
 *					  application(when USE_AMP flag is defined for BSP) as master CPU
 *					  would be utilizing L2 cache for its operation
+* 6.6    mus 12/07/17 Errata 753970 is not applicable for the PL130 cache controller
+*                     version r0p2, which is present in zynq. So,removed the handling
+*                     related to same.It fixes CR#989132.
+* 6.6    asa 16/01/18 Changes made in Xil_L1DCacheInvalidate and Xil_L2CacheInvalidate
+*					  routines to ensure the stack data flushed only when the respective
+*					  caches are enabled. This fixes CR-992023.
 *
 *
* @@ -162,16 +168,12 @@ static inline void Xil_L2CacheSync(void) static void Xil_L2CacheSync(void) #endif { -#ifdef CONFIG_PL310_ERRATA_753970 - Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_DUMMY_CACHE_SYNC_OFFSET, 0x0U); -#else Xil_Out32(XPS_L2CC_BASEADDR + XPS_L2CC_CACHE_SYNC_OFFSET, 0x0U); -#endif } #endif -/**************************************************************************** -* -* Enable the Data cache. +/****************************************************************************/ +/** +* @brief Enable the Data cache. * * @param None. * @@ -188,9 +190,9 @@ void Xil_DCacheEnable(void) #endif } -/**************************************************************************** -* -* Disable the Data cache. +/****************************************************************************/ +/** +* @brief Disable the Data cache. * * @param None. * @@ -207,9 +209,9 @@ void Xil_DCacheDisable(void) Xil_L1DCacheDisable(); } -/**************************************************************************** -* -* Invalidate the entire Data cache. +/****************************************************************************/ +/** +* @brief Invalidate the entire Data cache. * * @param None. * @@ -232,15 +234,15 @@ void Xil_DCacheInvalidate(void) mtcpsr(currmask); } -/**************************************************************************** +/*****************************************************************************/ +/** +* @brief Invalidate a Data cache line. If the byte specified by the address +* (adr) is cached by the Data cache, the cacheline containing that +* byte is invalidated. If the cacheline is modified (dirty), the +* modified contents are lost and are NOT written to the system memory +* before the line is invalidated. * -* Invalidate a Data cache line. If the byte specified by the address (adr) -* is cached by the Data cache, the cacheline containing that byte is -* invalidated. If the cacheline is modified (dirty), the modified contents -* are lost and are NOT written to system memory before the line is -* invalidated. -* -* @param Address to be flushed. +* @param adr: 32bit address of the data to be flushed. * * @return None. * @@ -261,61 +263,67 @@ void Xil_DCacheInvalidateLine(u32 adr) mtcpsr(currmask); } -/**************************************************************************** + +/*****************************************************************************/ +/** +* @brief Invalidate the Data cache for the given address range. +* If the bytes specified by the address range are cached by the Data +* cache, the cachelines containing those bytes are invalidated. If +* the cachelines are modified (dirty), the modified contents are lost +* and NOT written to the system memory before the lines are +* invalidated. * -* Invalidate the Data cache for the given address range. -* If the bytes specified by the address (adr) are cached by the Data cache, -* the cacheline containing that byte is invalidated. If the cacheline -* is modified (dirty), the modified contents are lost and are NOT -* written to system memory before the line is invalidated. +* In this function, if start address or end address is not aligned to +* cache-line, particular cache-line containing unaligned start or end +* address is flush first and then invalidated the others as +* invalidating the same unaligned cache line may result into loss of +* data. This issue raises few possibilities. * -* In this function, if start address or end address is not aligned to cache-line, -* particular cache-line containing unaligned start or end address is flush first -* and then invalidated the others as invalidating the same unaligned cache line -* may result into loss of data. This issue raises few possibilities. +* If the address to be invalidated is not cache-line aligned, the +* following choices are available: +* 1. Invalidate the cache line when required and do not bother much +* for the side effects. Though it sounds good, it can result in +* hard-to-debug issues. The problem is, if some other variable are +* allocated in the same cache line and had been recently updated +* (in cache), the invalidation would result in loss of data. +* 2. Flush the cache line first. This will ensure that if any other +* variable present in the same cache line and updated recently are +* flushed out to memory. Then it can safely be invalidated. Again it +* sounds good, but this can result in issues. For example, when the +* invalidation happens in a typical ISR (after a DMA transfer has +* updated the memory), then flushing the cache line means, loosing +* data that were updated recently before the ISR got invoked. +* +* Linux prefers the second one. To have uniform implementation +* (across standalone and Linux), the second option is implemented. +* This being the case, follwoing needs to be taken care of: +* 1. Whenever possible, the addresses must be cache line aligned. +* Please nore that, not just start address, even the end address must +* be cache line aligned. If that is taken care of, this will always +* work. +* 2. Avoid situations where invalidation has to be done after the +* data is updated by peripheral/DMA directly into the memory. It is +* not tough to achieve (may be a bit risky). The common use case to +* do invalidation is when a DMA happens. Generally for such use +* cases, buffers can be allocated first and then start the DMA. The +* practice that needs to be followed here is, immediately after +* buffer allocation and before starting the DMA, do the invalidation. +* With this approach, invalidation need not to be done after the DMA +* transfer is over. +* +* This is going to always work if done carefully. +* However, the concern is, there is no guarantee that invalidate has +* not needed to be done after DMA is complete. For example, because +* of some reasons if the first cache line or last cache line +* (assuming the buffer in question comprises of multiple cache lines) +* are brought into cache (between the time it is invalidated and DMA +* completes) because of some speculative prefetching or reading data +* for a variable present in the same cache line, then we will have to +* invalidate the cache after DMA is complete. * * -* If the address to be invalidated is not cache-line aligned, the -* following choices are available: -* 1) Invalidate the cache line when required and do not bother much for the -* side effects. Though it sounds good, it can result in hard-to-debug issues. -* The problem is, if some other variable are allocated in the -* same cache line and had been recently updated (in cache), the invalidation -* would result in loss of data. -* -* 2) Flush the cache line first. This will ensure that if any other variable -* present in the same cache line and updated recently are flushed out to memory. -* Then it can safely be invalidated. Again it sounds good, but this can result -* in issues. For example, when the invalidation happens -* in a typical ISR (after a DMA transfer has updated the memory), then flushing -* the cache line means, loosing data that were updated recently before the ISR -* got invoked. -* -* Linux prefers the second one. To have uniform implementation (across standalone -* and Linux), the second option is implemented. -* This being the case, follwoing needs to be taken care of: -* 1) Whenever possible, the addresses must be cache line aligned. Please nore that, -* not just start address, even the end address must be cache line aligned. If that -* is taken care of, this will always work. -* 2) Avoid situations where invalidation has to be done after the data is updated by -* peripheral/DMA directly into the memory. It is not tough to achieve (may be a bit -* risky). The common use case to do invalidation is when a DMA happens. Generally -* for such use cases, buffers can be allocated first and then start the DMA. The -* practice that needs to be followed here is, immediately after buffer allocation -* and before starting the DMA, do the invalidation. With this approach, invalidation -* need not to be done after the DMA transfer is over. -* -* This is going to always work if done carefully. -* However, the concern is, there is no guarantee that invalidate has not needed to be -* done after DMA is complete. For example, because of some reasons if the first cache -* line or last cache line (assuming the buffer in question comprises of multiple cache -* lines) are brought into cache (between the time it is invalidated and DMA completes) -* because of some speculative prefetching or reading data for a variable present -* in the same cache line, then we will have to invalidate the cache after DMA is complete. -* -* -* @param Start address of range to be invalidated. -* @param Length of range to be invalidated in bytes. +* @param adr: 32bit start address of the range to be invalidated. +* @param len: Length of the range to be invalidated in bytes. * * @return None. * @@ -392,9 +400,9 @@ void Xil_DCacheInvalidateRange(INTPTR adr, u32 len) mtcpsr(currmask); } -/**************************************************************************** -* -* Flush the entire Data cache. +/****************************************************************************/ +/** +* @brief Flush the entire Data cache. * * @param None. * @@ -416,15 +424,16 @@ void Xil_DCacheFlush(void) mtcpsr(currmask); } -/**************************************************************************** + +/****************************************************************************/ +/** +* @brief Flush a Data cache line. If the byte specified by the address (adr) +* is cached by the Data cache, the cacheline containing that byte is +* invalidated. If the cacheline is modified (dirty), the entire +* contents of the cacheline are written to system memory before the +* line is invalidated. * -* Flush a Data cache line. If the byte specified by the address (adr) -* is cached by the Data cache, the cacheline containing that byte is -* invalidated. If the cacheline is modified (dirty), the entire -* contents of the cacheline are written to system memory before the -* line is invalidated. -* -* @param Address to be flushed. +* @param adr: 32bit address of the data to be flushed. * * @return None. * @@ -451,15 +460,16 @@ void Xil_DCacheFlushLine(u32 adr) mtcpsr(currmask); } -/**************************************************************************** -* Flush the Data cache for the given address range. -* If the bytes specified by the address (adr) are cached by the Data cache, -* the cacheline containing that byte is invalidated. If the cacheline -* is modified (dirty), the written to system memory first before the -* before the line is invalidated. +/****************************************************************************/ +/** +* @brief Flush the Data cache for the given address range. +* If the bytes specified by the address range are cached by the +* data cache, the cachelines containing those bytes are invalidated. +* If the cachelines are modified (dirty), they are written to the +* system memory before the lines are invalidated. * -* @param Start address of range to be flushed. -* @param Length of range to be flushed in bytes. +* @param adr: 32bit start address of the range to be flushed. +* @param len: Length of the range to be flushed in bytes. * * @return None. * @@ -506,15 +516,15 @@ void Xil_DCacheFlushRange(INTPTR adr, u32 len) dsb(); mtcpsr(currmask); } -/**************************************************************************** +/****************************************************************************/ +/** +* @brief Store a Data cache line. If the byte specified by the address (adr) +* is cached by the Data cache and the cacheline is modified (dirty), +* the entire contents of the cacheline are written to system memory. +* After the store completes, the cacheline is marked as unmodified +* (not dirty). * -* Store a Data cache line. If the byte specified by the address (adr) -* is cached by the Data cache and the cacheline is modified (dirty), -* the entire contents of the cacheline are written to system memory. -* After the store completes, the cacheline is marked as unmodified -* (not dirty). -* -* @param Address to be stored. +* @param adr: 32bit address of the data to be stored. * * @return None. * @@ -535,9 +545,9 @@ void Xil_DCacheStoreLine(u32 adr) mtcpsr(currmask); } -/**************************************************************************** -* -* Enable the instruction cache. +/***************************************************************************/ +/** +* @brief Enable the instruction cache. * * @param None. * @@ -554,9 +564,9 @@ void Xil_ICacheEnable(void) #endif } -/**************************************************************************** -* -* Disable the instruction cache. +/***************************************************************************/ +/** +* @brief Disable the instruction cache. * * @param None. * @@ -573,9 +583,10 @@ void Xil_ICacheDisable(void) Xil_L1ICacheDisable(); } -/**************************************************************************** -* -* Invalidate the entire instruction cache. + +/****************************************************************************/ +/** +* @brief Invalidate the entire instruction cache. * * @param None. * @@ -598,13 +609,13 @@ void Xil_ICacheInvalidate(void) mtcpsr(currmask); } -/**************************************************************************** +/****************************************************************************/ +/** +* @brief Invalidate an instruction cache line. If the instruction specified +* by the address is cached by the instruction cache, the cacheline +* containing that instruction is invalidated. * -* Invalidate an instruction cache line. If the instruction specified by the -* parameter adr is cached by the instruction cache, the cacheline containing -* that instruction is invalidated. -* -* @param None. +* @param adr: 32bit address of the instruction to be invalidated. * * @return None. * @@ -624,16 +635,15 @@ void Xil_ICacheInvalidateLine(u32 adr) mtcpsr(currmask); } -/**************************************************************************** +/****************************************************************************/ +/** +* @brief Invalidate the instruction cache for the given address range. +* If the instructions specified by the address range are cached by +* the instrunction cache, the cachelines containing those +* instructions are invalidated. * -* Invalidate the instruction cache for the given address range. -* If the bytes specified by the address (adr) are cached by the Data cache, -* the cacheline containing that byte is invalidated. If the cacheline -* is modified (dirty), the modified contents are lost and are NOT -* written to system memory before the line is invalidated. -* -* @param Start address of range to be invalidated. -* @param Length of range to be invalidated in bytes. +* @param adr: 32bit start address of the range to be invalidated. +* @param len: Length of the range to be invalidated in bytes. * * @return None. * @@ -687,9 +697,9 @@ void Xil_ICacheInvalidateRange(INTPTR adr, u32 len) mtcpsr(currmask); } -/**************************************************************************** -* -* Enable the level 1 Data cache. +/****************************************************************************/ +/** +* @brief Enable the level 1 Data cache. * * @param None. * @@ -724,9 +734,9 @@ void Xil_L1DCacheEnable(void) mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); } -/**************************************************************************** -* -* Disable the level 1 Data cache. +/***************************************************************************/ +/** +* @brief Disable the level 1 Data cache. * * @param None. * @@ -757,17 +767,17 @@ void Xil_L1DCacheDisable(void) mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); } -/**************************************************************************** -* -* Invalidate the level 1 Data cache. +/****************************************************************************/ +/** +* @brief Invalidate the level 1 Data cache. * * @param None. * * @return None. * * @note In Cortex A9, there is no cp instruction for invalidating -* the whole D-cache. This function invalidates each line by -* set/way. +* the whole D-cache. This function invalidates each line by +* set/way. * ****************************************************************************/ void Xil_L1DCacheInvalidate(void) @@ -779,6 +789,7 @@ void Xil_L1DCacheInvalidate(void) #ifdef __GNUC__ u32 stack_start,stack_end,stack_size; + register u32 CtrlReg; #endif currmask = mfcpsr(); @@ -789,8 +800,15 @@ void Xil_L1DCacheInvalidate(void) stack_start = (u32)&__undef_stack; stack_size=stack_start-stack_end; - /*Flush stack memory to save return address*/ - Xil_DCacheFlushRange(stack_end, stack_size); + /* Check for the cache status. If cache is enabled, then only + * flush stack memory to save return address. If cache is disabled, + * dont flush anything as it might result in flushing stale date into + * memory which is undesirable. + * */ + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); + if ((CtrlReg & (XREG_CP15_CONTROL_C_BIT)) != 0U) { + Xil_DCacheFlushRange(stack_end, stack_size); + } #endif /* Select cache level 0 and D cache in CSSR */ @@ -847,15 +865,15 @@ void Xil_L1DCacheInvalidate(void) mtcpsr(currmask); } -/**************************************************************************** +/****************************************************************************/ +/** +* @brief Invalidate a level 1 Data cache line. If the byte specified by the +* address (Addr) is cached by the Data cache, the cacheline +* containing that byte is invalidated. If the cacheline is modified +* (dirty), the modified contents are lost and are NOT written to +* system memory before the line is invalidated. * -* Invalidate a level 1 Data cache line. If the byte specified by the address -* (Addr) is cached by the Data cache, the cacheline containing that byte is -* invalidated. If the cacheline is modified (dirty), the modified contents -* are lost and are NOT written to system memory before the line is -* invalidated. -* -* @param Address to be flushed. +* @param adr: 32bit address of the data to be invalidated. * * @return None. * @@ -871,16 +889,16 @@ void Xil_L1DCacheInvalidateLine(u32 adr) dsb(); } -/**************************************************************************** +/****************************************************************************/ +/** +* @brief Invalidate the level 1 Data cache for the given address range. +* If the bytes specified by the address range are cached by the Data +* cache, the cachelines containing those bytes are invalidated. If the +* cachelines are modified (dirty), the modified contents are lost and +* NOT written to the system memory before the lines are invalidated. * -* Invalidate the level 1 Data cache for the given address range. -* If the bytes specified by the address (adr) are cached by the Data cache, -* the cacheline containing that byte is invalidated. If the cacheline -* is modified (dirty), the modified contents are lost and are NOT -* written to system memory before the line is invalidated. -* -* @param Start address of range to be invalidated. -* @param Length of range to be invalidated in bytes. +* @param adr: 32bit start address of the range to be invalidated. +* @param len: Length of the range to be invalidated in bytes. * * @return None. * @@ -925,16 +943,16 @@ void Xil_L1DCacheInvalidateRange(u32 adr, u32 len) mtcpsr(currmask); } -/**************************************************************************** -* -* Flush the level 1 Data cache. +/****************************************************************************/ +/** +* @brief Flush the level 1 Data cache. * * @param None. * * @return None. * * @note In Cortex A9, there is no cp instruction for flushing -* the whole D-cache. Need to flush each line. +* the whole D-cache. Need to flush each line. * ****************************************************************************/ void Xil_L1DCacheFlush(void) @@ -1003,15 +1021,15 @@ void Xil_L1DCacheFlush(void) mtcpsr(currmask); } -/**************************************************************************** +/****************************************************************************/ +/** +* @brief Flush a level 1 Data cache line. If the byte specified by the +* address (adr) is cached by the Data cache, the cacheline containing +* that byte is invalidated. If the cacheline is modified (dirty), the +* entire contents of the cacheline are written to system memory +* before the line is invalidated. * -* Flush a level 1 Data cache line. If the byte specified by the address (adr) -* is cached by the Data cache, the cacheline containing that byte is -* invalidated. If the cacheline is modified (dirty), the entire -* contents of the cacheline are written to system memory before the -* line is invalidated. -* -* @param Address to be flushed. +* @param adr: 32bit address of the data to be flushed. * * @return None. * @@ -1027,15 +1045,16 @@ void Xil_L1DCacheFlushLine(u32 adr) dsb(); } -/**************************************************************************** -* Flush the level 1 Data cache for the given address range. -* If the bytes specified by the address (adr) are cached by the Data cache, -* the cacheline containing that byte is invalidated. If the cacheline -* is modified (dirty), the written to system memory first before the -* before the line is invalidated. +/****************************************************************************/ +/** +* @brief Flush the level 1 Data cache for the given address range. +* If the bytes specified by the address range are cached by the Data +* cache, the cacheline containing those bytes are invalidated. If the +* cachelines are modified (dirty), they are written to system memory +* before the lines are invalidated. * -* @param Start address of range to be flushed. -* @param Length of range to be flushed in bytes. +* @param adr: 32bit start address of the range to be flushed. +* @param len: Length of the range to be flushed in bytes. * * @return None. * @@ -1080,13 +1099,13 @@ void Xil_L1DCacheFlushRange(u32 adr, u32 len) mtcpsr(currmask); } -/**************************************************************************** -* -* Store a level 1 Data cache line. If the byte specified by the address (adr) -* is cached by the Data cache and the cacheline is modified (dirty), -* the entire contents of the cacheline are written to system memory. -* After the store completes, the cacheline is marked as unmodified -* (not dirty). +/****************************************************************************/ +/** +* @brief Store a level 1 Data cache line. If the byte specified by the +* address (adr) is cached by the Data cache and the cacheline is +* modified (dirty), the entire contents of the cacheline are written +* to system memory. After the store completes, the cacheline is +* marked as unmodified (not dirty). * * @param Address to be stored. * @@ -1104,9 +1123,10 @@ void Xil_L1DCacheStoreLine(u32 adr) dsb(); } -/**************************************************************************** -* -* Enable the level 1 instruction cache. + +/****************************************************************************/ +/** +* @brief Enable the level 1 instruction cache. * * @param None. * @@ -1141,9 +1161,9 @@ void Xil_L1ICacheEnable(void) mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); } -/**************************************************************************** -* -* Disable level 1 the instruction cache. +/****************************************************************************/ +/** +* @brief Disable level 1 the instruction cache. * * @param None. * @@ -1175,9 +1195,9 @@ void Xil_L1ICacheDisable(void) mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); } -/**************************************************************************** -* -* Invalidate the entire level 1 instruction cache. +/****************************************************************************/ +/** +* @brief Invalidate the entire level 1 instruction cache. * * @param None. * @@ -1196,13 +1216,13 @@ void Xil_L1ICacheInvalidate(void) dsb(); } -/**************************************************************************** +/****************************************************************************/ +/** +* @brief Invalidate a level 1 instruction cache line. If the instruction +* specified by the address is cached by the instruction cache, the +* cacheline containing that instruction is invalidated. * -* Invalidate a level 1 instruction cache line. If the instruction specified by -* the parameter adr is cached by the instruction cache, the cacheline containing -* that instruction is invalidated. -* -* @param None. +* @param adr: 32bit address of the instruction to be invalidated. * * @return None. * @@ -1218,16 +1238,15 @@ void Xil_L1ICacheInvalidateLine(u32 adr) dsb(); } -/**************************************************************************** +/****************************************************************************/ +/** +* @brief Invalidate the level 1 instruction cache for the given address +* range. If the instrucions specified by the address range are cached +* by the instruction cache, the cacheline containing those bytes are +* invalidated. * -* Invalidate the level 1 instruction cache for the given address range. -* If the bytes specified by the address (adr) are cached by the Data cache, -* the cacheline containing that byte is invalidated. If the cacheline -* is modified (dirty), the modified contents are lost and are NOT -* written to system memory before the line is invalidated. -* -* @param Start address of range to be invalidated. -* @param Length of range to be invalidated in bytes. +* @param adr: 32bit start address of the range to be invalidated. +* @param len: Length of the range to be invalidated in bytes. * * @return None. * @@ -1273,9 +1292,9 @@ void Xil_L1ICacheInvalidateRange(u32 adr, u32 len) } #ifndef USE_AMP -/**************************************************************************** -* -* Enable the L2 cache. +/****************************************************************************/ +/** +* @brief Enable the L2 cache. * * @param None. * @@ -1323,9 +1342,9 @@ void Xil_L2CacheEnable(void) } } -/**************************************************************************** -* -* Disable the L2 cache. +/****************************************************************************/ +/** +* @brief Disable the L2 cache. * * @param None. * @@ -1355,31 +1374,37 @@ void Xil_L2CacheDisable(void) } } -/**************************************************************************** +/*****************************************************************************/ +/** +* @brief Invalidate the entire level 2 cache. * -* Invalidate the L2 cache. If the byte specified by the address (adr) -* is cached by the Data cache, the cacheline containing that byte is -* invalidated. If the cacheline is modified (dirty), the modified contents -* are lost and are NOT written to system memory before the line is -* invalidated. -* -* @param Address to be flushed. +* @param None. * * @return None. * -* @note The bottom 4 bits are set to 0, forced by architecture. +* @note None. * ****************************************************************************/ void Xil_L2CacheInvalidate(void) { #ifdef __GNUC__ u32 stack_start,stack_end,stack_size; + register u32 L2CCReg; stack_end = (u32)&_stack_end; stack_start = (u32)&__undef_stack; stack_size=stack_start-stack_end; + /* Check for the cache status. If cache is enabled, then only + * flush stack memory to save return address. If cache is disabled, + * dont flush anything as it might result in flushing stale date into + * memory which is undesirable. + */ + L2CCReg = Xil_In32(XPS_L2CC_BASEADDR + XPS_L2CC_CNTRL_OFFSET); + if ((L2CCReg & 0x01U) != 0U) { /*Flush stack memory to save return address*/ - Xil_DCacheFlushRange(stack_end, stack_size); + Xil_DCacheFlushRange(stack_end, stack_size); + } + #endif u32 ResultDCache; /* Invalidate the caches */ @@ -1399,15 +1424,15 @@ void Xil_L2CacheInvalidate(void) dsb(); } -/**************************************************************************** +/*****************************************************************************/ +/** +* @brief Invalidate a level 2 cache line. If the byte specified by the +* address (adr) is cached by the Data cache, the cacheline containing +* that byte is invalidated. If the cacheline is modified (dirty), +* the modified contents are lost and are NOT written to system memory +* before the line is invalidated. * -* Invalidate a level 2 cache line. If the byte specified by the address (adr) -* is cached by the Data cache, the cacheline containing that byte is -* invalidated. If the cacheline is modified (dirty), the modified contents -* are lost and are NOT written to system memory before the line is -* invalidated. -* -* @param Address to be flushed. +* @param adr: 32bit address of the data/instruction to be invalidated. * * @return None. * @@ -1421,16 +1446,16 @@ void Xil_L2CacheInvalidateLine(u32 adr) dsb(); } -/**************************************************************************** +/****************************************************************************/ +/** +* @brief Invalidate the level 2 cache for the given address range. +* If the bytes specified by the address range are cached by the L2 +* cache, the cacheline containing those bytes are invalidated. If the +* cachelines are modified (dirty), the modified contents are lost and +* are NOT written to system memory before the lines are invalidated. * -* Invalidate the level 2 cache for the given address range. -* If the bytes specified by the address (adr) are cached by the Data cache, -* the cacheline containing that byte is invalidated. If the cacheline -* is modified (dirty), the modified contents are lost and are NOT -* written to system memory before the line is invalidated. -* -* @param Start address of range to be invalidated. -* @param Length of range to be invalidated in bytes. +* @param adr: 32bit start address of the range to be invalidated. +* @param len: Length of the range to be invalidated in bytes. * * @return None. * @@ -1475,24 +1500,19 @@ void Xil_L2CacheInvalidateRange(u32 adr, u32 len) mtcpsr(currmask); } -/**************************************************************************** +/****************************************************************************/ +/** +* @brief Flush the entire level 2 cache. * -* Flush the L2 cache. If the byte specified by the address (adr) -* is cached by the Data cache, the cacheline containing that byte is -* invalidated. If the cacheline is modified (dirty), the entire -* contents of the cacheline are written to system memory before the -* line is invalidated. -* -* @param Address to be flushed. +* @param None. * * @return None. * -* @note The bottom 4 bits are set to 0, forced by architecture. +* @note None. * ****************************************************************************/ void Xil_L2CacheFlush(void) { - u16 L2CCReg; u32 ResultL2Cache; /* Flush the caches */ @@ -1518,15 +1538,15 @@ void Xil_L2CacheFlush(void) dsb(); } -/**************************************************************************** +/****************************************************************************/ +/** +* @brief Flush a level 2 cache line. If the byte specified by the address +* (adr) is cached by the L2 cache, the cacheline containing that +* byte is invalidated. If the cacheline is modified (dirty), the +* entire contents of the cacheline are written to system memory +* before the line is invalidated. * -* Flush a level 2 cache line. If the byte specified by the address (adr) -* is cached by the Data cache, the cacheline containing that byte is -* invalidated. If the cacheline is modified (dirty), the entire -* contents of the cacheline are written to system memory before the -* line is invalidated. -* -* @param Address to be flushed. +* @param adr: 32bit address of the data/instruction to be flushed. * * @return None. * @@ -1545,15 +1565,16 @@ void Xil_L2CacheFlushLine(u32 adr) dsb(); } -/**************************************************************************** -* Flush the level 2 cache for the given address range. -* If the bytes specified by the address (adr) are cached by the Data cache, -* the cacheline containing that byte is invalidated. If the cacheline -* is modified (dirty), the written to system memory first before the -* before the line is invalidated. +/****************************************************************************/ +/** +* @brief Flush the level 2 cache for the given address range. +* If the bytes specified by the address range are cached by the L2 +* cache, the cacheline containing those bytes are invalidated. If the +* cachelines are modified (dirty), they are written to the system +* memory before the lines are invalidated. * -* @param Start address of range to be flushed. -* @param Length of range to be flushed in bytes. +* @param adr: 32bit start address of the range to be flushed. +* @param len: Length of the range to be flushed in bytes. * * @return None. * @@ -1596,15 +1617,15 @@ void Xil_L2CacheFlushRange(u32 adr, u32 len) mtcpsr(currmask); } -/**************************************************************************** +/****************************************************************************/ +/** +* @brief Store a level 2 cache line. If the byte specified by the address +* (adr) is cached by the L2 cache and the cacheline is modified +* (dirty), the entire contents of the cacheline are written to +* system memory. After the store completes, the cacheline is marked +* as unmodified (not dirty). * -* Store a level 2 cache line. If the byte specified by the address (adr) -* is cached by the Data cache and the cacheline is modified (dirty), -* the entire contents of the cacheline are written to system memory. -* After the store completes, the cacheline is marked as unmodified -* (not dirty). -* -* @param Address to be stored. +* @param adr: 32bit address of the data/instruction to be stored. * * @return None. * @@ -1617,4 +1638,4 @@ void Xil_L2CacheStoreLine(u32 adr) /* synchronize the processor */ dsb(); } -#endif \ No newline at end of file +#endif diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xil_cache.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_cache.h similarity index 91% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xil_cache.h rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_cache.h index 2d9e7fff1..b6614d5f9 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xil_cache.h +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_cache.h @@ -34,7 +34,14 @@ * * @file xil_cache.h * -* Contains required functions for the ARM cache functionality +* @addtogroup a9_cache_apis Cortex A9 Processor Cache Functions +* +* Cache functions provide access to cache related operations such as flush +* and invalidate for instruction and data caches. It gives option to perform +* the cache operations on a single cacheline, a range of memory and an entire +* cache. +* +* @{ * * 
 * MODIFICATION HISTORY:
@@ -109,3 +116,6 @@ void Xil_ICacheInvalidateRange(INTPTR adr, u32 len);
 #endif
 
 #endif
+/**
+* @} End of "addtogroup a9_cache_apis".
+*/
\ No newline at end of file
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xil_cache_l.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_cache_l.h
similarity index 97%
rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xil_cache_l.h
rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_cache_l.h
index b291896aa..fa92c6b1c 100644
--- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xil_cache_l.h
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_cache_l.h
@@ -38,6 +38,8 @@
 * used by xcache.c. This functionality is being made available here for
 * more sophisticated users.
 *
+* @addtogroup a9_cache_apis
+* @{
 * 
 * MODIFICATION HISTORY:
 *
@@ -93,3 +95,6 @@ void Xil_L2CacheStoreLine(u32 adr);
 #endif
 
 #endif
+/**
+* @} End of "addtogroup a9_cache_apis".
+*/
\ No newline at end of file
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xil_cache_vxworks.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_cache_vxworks.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xil_cache_vxworks.h
rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_cache_vxworks.h
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xil_errata.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_errata.h
similarity index 77%
rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xil_errata.h
rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_errata.h
index c3870869d..490aebeab 100644
--- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xil_errata.h
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_errata.h
@@ -34,8 +34,17 @@
 *
 * @file xil_errata.h
 *
-* This header file contains Cortex A9 and PL310 Errata definitions.
+* @addtogroup a9_errata Cortex A9 Processor and pl310 Errata Support
+* @{
+* Various ARM errata are handled in the standalone BSP. The implementation for
+* errata handling follows ARM guidelines and is based on the open source Linux
+* support for these errata.
 *
+* @note
+* The errata handling is enabled by default. To disable handling of all the
+* errata globally, un-define the macro ENABLE_ARM_ERRATA in xil_errata.h. To
+* disable errata on a per-erratum basis, un-define relevant macros in
+* xil_errata.h.
 *
 * 
 * MODIFICATION HISTORY:
@@ -43,38 +52,45 @@
 * Ver   Who  Date     Changes
 * ----- ---- -------- -----------------------------------------------
 * 1.00a srt  04/18/13 First release
+* 6.6   mus  12/07/17 Removed errata 753970, It fixes CR#989132.
 * 

 *
 ******************************************************************************/
 #ifndef XIL_ERRATA_H
 #define XIL_ERRATA_H
 
+/**
+ * @name errata_definitions
+ *
+ * The errata conditions handled in the standalone BSP are listed below
+ * @{
+ */
+
 #define ENABLE_ARM_ERRATA 1
 
 #ifdef ENABLE_ARM_ERRATA
-/* Cortex A9 ARM Errata */
 
-/*
+/**
  *  Errata No: 	 742230
  *  Description: DMB operation may be faulty
  */
 #define CONFIG_ARM_ERRATA_742230 1
 
-/*
+/**
  *  Errata No: 	 743622
  *  Description: Faulty hazard checking in the Store Buffer may lead
- *	         to data corruption.
+ *	         	 to data corruption.
  */
 #define CONFIG_ARM_ERRATA_743622 1
 
-/*
+/**
  *  Errata No: 	 775420
  *  Description: A data cache maintenance operation which aborts,
- *		 might lead to deadlock
+ *		 		 might lead to deadlock
  */
 #define CONFIG_ARM_ERRATA_775420 1
 
-/*
+/**
  *  Errata No: 	 794073
  *  Description: Speculative instruction fetches with MMU disabled
  *               might not comply with architectural requirements
@@ -82,28 +98,26 @@
 #define CONFIG_ARM_ERRATA_794073 1
 
 
-/* PL310 L2 Cache Errata */
+/** PL310 L2 Cache Errata */
 
-/*
+/**
  *  Errata No: 	 588369
  *  Description: Clean & Invalidate maintenance operations do not
- *	   	 invalidate clean lines
+ *	   	 		 invalidate clean lines
  */
 #define CONFIG_PL310_ERRATA_588369 1
 
-/*
+/**
  *  Errata No: 	 727915
  *  Description: Background Clean and Invalidate by Way operation
  *		 can cause data corruption
  */
 #define CONFIG_PL310_ERRATA_727915 1
 
-/*
- *  Errata No: 	 753970
- *  Description: Cache sync operation may be faulty
- */
-#define CONFIG_PL310_ERRATA_753970 1
-
+/*@}*/
 #endif  /* ENABLE_ARM_ERRATA */
 
 #endif  /* XIL_ERRATA_H */
+/**
+* @} End of "addtogroup a9_errata".
+*/
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_exception.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_exception.c
similarity index 85%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_exception.c
rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_exception.c
index 66f722d92..4a2f2cfdf 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_exception.c
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_exception.c
@@ -46,6 +46,8 @@
 * 6.0   mus      27/07/16 Consolidated exceptions for a53,a9 and r5
 *                         processors and added Xil_UndefinedExceptionHandler
 *                         for a53 32 bit and r5 as well.
+* 6.4   mus      08/06/17 Updated debug prints to replace %x with the %lx, to
+*                         fix the warnings.
 * 

 *
 *****************************************************************************/
@@ -122,19 +124,19 @@ u32 UndefinedExceptionAddr;   /* Address of instruction causing Undefined
 *****************************************************************************/
 static void Xil_ExceptionNullHandler(void *Data)
 {
-	(void *)Data;
+	(void) Data;
 DieLoop: goto DieLoop;
 }
 
 /****************************************************************************/
 /**
-* The function is a common API used to initialize exception handlers across all
-* processors supported. For ARM CortexA53,R5,A9, the exception handlers are being
-* initialized statically and hence this function does not do anything.
-* However, it is still present to avoid any compilation issues in case an
-* application uses this API and also to take care of backward compatibility
-* issues (in earlier versions of BSPs, this API was being used to initialize
-* exception handlers).
+* @brief	The function is a common API used to initialize exception handlers
+*			across all supported arm processors. For ARM Cortex-A53, Cortex-R5,
+*			and Cortex-A9, the exception handlers are being initialized
+*			statically and this function does not do anything.
+* 			However, it is still present to take care of backward compatibility
+*			issues (in earlier versions of BSPs, this API was being used to
+*			initialize exception handlers).
 *
 * @param	None.
 *
@@ -150,18 +152,15 @@ void Xil_ExceptionInit(void)
 
 /*****************************************************************************/
 /**
-*
-* Makes the connection between the Id of the exception source and the
-* associated Handler that is to run when the exception is recognized. The
-* argument provided in this call as the Data is used as the argument
-* for the Handler when it is called.
+* @brief	Register a handler for a specific exception. This handler is being
+*			called when the processor encounters the specified exception.
 *
 * @param	exception_id contains the ID of the exception source and should
-*		be in the range of 0 to XIL_EXCEPTION_ID_LAST.
-		See xil_exception_l.h for further information.
+*			be in the range of 0 to XIL_EXCEPTION_ID_LAST.
+*			See xil_exception.h for further information.
 * @param	Handler to the Handler for that exception.
 * @param	Data is a reference to Data that will be passed to the
-*		Handler when it gets called.
+*			Handler when it gets called.
 *
 * @return	None.
 *
@@ -179,13 +178,13 @@ void Xil_ExceptionRegisterHandler(u32 Exception_id,
 /*****************************************************************************/
 /**
 *
-* Removes the Handler for a specific exception Id. The stub Handler is then
-* registered for this exception Id.
+* @brief	Removes the Handler for a specific exception Id. The stub Handler
+*			is then registered for this exception Id.
 *
 * @param	exception_id contains the ID of the exception source and should
-*		be in the range of 0 to XIL_EXCEPTION_ID_LAST.
-*		See xil_exception_l.h for further information.
-
+*			be in the range of 0 to XIL_EXCEPTION_ID_LAST.
+*			See xil_exception.h for further information.
+*
 * @return	None.
 *
 * @note		None.
@@ -214,6 +213,7 @@ void Xil_ExceptionRemoveHandler(u32 Exception_id)
 ****************************************************************************/
 
 void Xil_SyncAbortHandler(void *CallBackRef){
+	(void) CallBackRef;
 	xdbg_printf(XDBG_DEBUG_ERROR, "Synchronous abort \n");
 	while(1) {
 		;
@@ -234,6 +234,7 @@ void Xil_SyncAbortHandler(void *CallBackRef){
 *
 ****************************************************************************/
 void Xil_SErrorAbortHandler(void *CallBackRef){
+	(void) CallBackRef;
 	xdbg_printf(XDBG_DEBUG_ERROR, "Synchronous abort \n");
 	while(1) {
 		;
@@ -241,7 +242,7 @@ void Xil_SErrorAbortHandler(void *CallBackRef){
 }
 #else
 /*****************************************************************************/
-/**
+/*
 *
 * Default Data abort handler which prints data fault status register through
 * which information about data fault can be acquired
@@ -255,6 +256,7 @@ void Xil_SErrorAbortHandler(void *CallBackRef){
 ****************************************************************************/
 
 void Xil_DataAbortHandler(void *CallBackRef){
+	(void) CallBackRef;
 #ifdef DEBUG
 	u32 FaultStatus;
 
@@ -267,8 +269,8 @@ void Xil_DataAbortHandler(void *CallBackRef){
 	        { volatile register u32 Reg __asm(XREG_CP15_DATA_FAULT_STATUS);
 	        FaultStatus = Reg; }
 	    #endif
-	xdbg_printf(XDBG_DEBUG_GENERAL, "Data abort with Data Fault Status Register  %x\n",FaultStatus);
-	xdbg_printf(XDBG_DEBUG_GENERAL, "Address of Instrcution causing Data abort %x\n",DataAbortAddr);
+	xdbg_printf(XDBG_DEBUG_GENERAL, "Data abort with Data Fault Status Register  %lx\n",FaultStatus);
+	xdbg_printf(XDBG_DEBUG_GENERAL, "Address of Instruction causing Data abort %lx\n",DataAbortAddr);
 #endif
 	while(1) {
 		;
@@ -276,7 +278,7 @@ void Xil_DataAbortHandler(void *CallBackRef){
 }
 
 /*****************************************************************************/
-/**
+/*
 *
 * Default Prefetch abort handler which prints prefetch fault status register through
 * which information about instruction prefetch fault can be acquired
@@ -289,6 +291,7 @@ void Xil_DataAbortHandler(void *CallBackRef){
 *
 ****************************************************************************/
 void Xil_PrefetchAbortHandler(void *CallBackRef){
+	(void) CallBackRef;
 #ifdef DEBUG
 	u32 FaultStatus;
 
@@ -301,15 +304,15 @@ void Xil_PrefetchAbortHandler(void *CallBackRef){
 			{ volatile register u32 Reg __asm(XREG_CP15_INST_FAULT_STATUS);
 			FaultStatus = Reg; }
 		#endif
-	xdbg_printf(XDBG_DEBUG_GENERAL, "Prefetch abort with Instruction Fault Status Register  %x\n",FaultStatus);
-	xdbg_printf(XDBG_DEBUG_GENERAL, "Address of Instrcution causing Prefetch abort %x\n",PrefetchAbortAddr);
+	xdbg_printf(XDBG_DEBUG_GENERAL, "Prefetch abort with Instruction Fault Status Register  %lx\n",FaultStatus);
+	xdbg_printf(XDBG_DEBUG_GENERAL, "Address of Instruction causing Prefetch abort %lx\n",PrefetchAbortAddr);
 #endif
 	while(1) {
 		;
 	}
 }
 /*****************************************************************************/
-/**
+/*
 *
 * Default undefined exception handler which prints address of the undefined
 * instruction if debug prints are enabled
@@ -322,8 +325,8 @@ void Xil_PrefetchAbortHandler(void *CallBackRef){
 *
 ****************************************************************************/
 void Xil_UndefinedExceptionHandler(void *CallBackRef){
-
-	xdbg_printf(XDBG_DEBUG_GENERAL, "Address of the undefined instruction %x\n",UndefinedExceptionAddr);
+	(void) CallBackRef;
+	xdbg_printf(XDBG_DEBUG_GENERAL, "Address of the undefined instruction %lx\n",UndefinedExceptionAddr);
 	while(1) {
 		;
 	}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_exception.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_exception.h
similarity index 90%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_exception.h
rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_exception.h
index 434ef2a6a..ad4822205 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_exception.h
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_exception.h
@@ -38,6 +38,12 @@
 * For exception related functions that can be used across all Xilinx supported
 * processors, please use xil_exception.h.
 *
+* @addtogroup arm_exception_apis ARM Processor Exception Handling
+* @{
+* ARM processors specific exception related APIs for cortex A53,A9 and R5 can
+* utilized for enabling/disabling IRQ, registering/removing handler for
+* exceptions or initializing exception vector table with null handler.
+*
 * 
 * MODIFICATION HISTORY:
 *
@@ -102,14 +108,14 @@ typedef void (*Xil_InterruptHandler)(void *data);
 
 /****************************************************************************/
 /**
-* Enable Exceptions.
+* @brief	Enable Exceptions.
 *
-* @param	Mask for exceptions to be enabled.
+* @param	Mask: Value for enabling the exceptions.
 *
 * @return	None.
 *
 * @note		If bit is 0, exception is enabled.
-*		C-Style signature: void Xil_ExceptionEnableMask(Mask)
+*			C-Style signature: void Xil_ExceptionEnableMask(Mask)
 *
 ******************************************************************************/
 #if defined (__GNUC__) || defined (__ICCARM__)
@@ -124,7 +130,7 @@ typedef void (*Xil_InterruptHandler)(void *data);
 #endif
 /****************************************************************************/
 /**
-* Enable the IRQ exception.
+* @brief	Enable the IRQ exception.
 *
 * @return   None.
 *
@@ -136,14 +142,14 @@ typedef void (*Xil_InterruptHandler)(void *data);
 
 /****************************************************************************/
 /**
-* Disable Exceptions.
+* @brief	Disable Exceptions.
 *
-* @param	Mask for exceptions to be enabled.
+* @param	Mask: Value for disabling the exceptions.
 *
 * @return	None.
 *
 * @note		If bit is 1, exception is disabled.
-*		C-Style signature: Xil_ExceptionDisableMask(Mask)
+*			C-Style signature: Xil_ExceptionDisableMask(Mask)
 *
 ******************************************************************************/
 #if defined (__GNUC__) || defined (__ICCARM__)
@@ -171,7 +177,8 @@ typedef void (*Xil_InterruptHandler)(void *data);
 #if !defined (__aarch64__) && !defined (ARMA53_32)
 /****************************************************************************/
 /**
-* Enable nested interrupts by clearing the I and F bits it CPSR
+* @brief	Enable nested interrupts by clearing the I and F bits in CPSR. This
+* 			API is defined for cortex-a9 and cortex-r5.
 *
 * @return   None.
 *
@@ -197,7 +204,8 @@ typedef void (*Xil_InterruptHandler)(void *data);
 
 /****************************************************************************/
 /**
-* Disable the nested interrupts by setting the I and F bits.
+* @brief	Disable the nested interrupts by setting the I and F bits. This API
+*			is defined for cortex-a9 and cortex-r5.
 *
 * @return   None.
 *
@@ -243,3 +251,6 @@ extern void Xil_UndefinedExceptionHandler(void *CallBackRef);
 #endif /* __cplusplus */
 
 #endif /* XIL_EXCEPTION_H */
+/**
+* @} End of "addtogroup arm_exception_apis".
+*/
\ No newline at end of file
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xil_hal.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_hal.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xil_hal.h
rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_hal.h
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_io.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_io.c
similarity index 90%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_io.c
rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_io.c
index 31de05581..90bfc81dc 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_io.c
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_io.c
@@ -35,8 +35,7 @@
 * @file xil_io.c
 *
 * Contains I/O functions for memory-mapped or non-memory-mapped I/O
-* architectures.  These functions encapsulate Cortex A53 architecture-specific
-* I/O requirements.
+* architectures.
 *
 * @note
 *
@@ -60,13 +59,11 @@
 /*****************************************************************************/
 /**
 *
-* Perform a 16-bit endian converion.
+* @brief    Perform a 16-bit endian converion.
 *
-* @param	Data contains the value to be converted.
+* @param	Data: 16 bit value to be converted
 *
-* @return	converted value.
-*
-* @note		None.
+* @return	16 bit Data with converted endianess
 *
 ******************************************************************************/
 u16 Xil_EndianSwap16(u16 Data)
@@ -77,13 +74,11 @@ u16 Xil_EndianSwap16(u16 Data)
 /*****************************************************************************/
 /**
 *
-* Perform a 32-bit endian converion.
+* @brief    Perform a 32-bit endian converion.
 *
-* @param	Data contains the value to be converted.
+* @param	Data: 32 bit value to be converted
 *
-* @return	converted value.
-*
-* @note		None.
+* @return	32 bit data with converted endianess
 *
 ******************************************************************************/
 u32 Xil_EndianSwap32(u32 Data)
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_io.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_io.h
similarity index 74%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_io.h
rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_io.h
index 06d89dcc3..9c5aa43c7 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_io.h
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_io.h
@@ -34,11 +34,13 @@
 *
 * @file xil_io.h
 *
-* This file contains the interface for the general IO component, which
-* encapsulates the Input/Output functions for processors that do not
+* @addtogroup common_io_interfacing_apis Register IO interfacing APIs
+*
+* The xil_io.h file contains the interface for the general I/O component, which
+* encapsulates the Input/Output functions for the processors that do not
 * require any special I/O handling.
 *
-*
+* @{
 * 
 * MODIFICATION HISTORY:
 *
@@ -71,6 +73,9 @@ extern "C" {
 /************************** Function Prototypes ******************************/
 u16 Xil_EndianSwap16(u16 Data);
 u32 Xil_EndianSwap32(u32 Data);
+#ifdef ENABLE_SAFETY
+extern u32 XStl_RegUpdate(u32 RegAddr, u32 RegVal);
+#endif
 
 /***************** Macros (Inline Functions) Definitions *********************/
 #if defined __GNUC__
@@ -99,15 +104,14 @@ u32 Xil_EndianSwap32(u32 Data);
 /*****************************************************************************/
 /**
 *
-* Performs an input operation for an 8-bit memory location by reading from the
-* specified address and returning the Value read from that address.
+* @brief    Performs an input operation for a memory location by reading
+*           from the specified address and returning the 8 bit Value read from
+*            that address.
 *
-* @param	Addr contains the address to perform the input operation
-*		at.
+* @param	Addr: contains the address to perform the input operation
 *
-* @return	The Value read from the specified input address.
-*
-* @note		None.
+* @return	The 8 bit Value read from the specified input address.
+
 *
 ******************************************************************************/
 static INLINE u8 Xil_In8(UINTPTR Addr)
@@ -118,15 +122,13 @@ static INLINE u8 Xil_In8(UINTPTR Addr)
 /*****************************************************************************/
 /**
 *
-* Performs an input operation for a 16-bit memory location by reading from the
-* specified address and returning the Value read from that address.
+* @brief    Performs an input operation for a memory location by reading from
+*           the specified address and returning the 16 bit Value read from that
+*           address.
 *
-* @param	Addr contains the address to perform the input operation
-*		at.
+* @param	Addr: contains the address to perform the input operation
 *
-* @return	The Value read from the specified input address.
-*
-* @note		None.
+* @return	The 16 bit Value read from the specified input address.
 *
 ******************************************************************************/
 static INLINE u16 Xil_In16(UINTPTR Addr)
@@ -137,15 +139,13 @@ static INLINE u16 Xil_In16(UINTPTR Addr)
 /*****************************************************************************/
 /**
 *
-* Performs an input operation for a 32-bit memory location by reading from the
-* specified address and returning the Value read from that address.
+* @brief    Performs an input operation for a memory location by
+*           reading from the specified address and returning the 32 bit Value
+*           read  from that address.
 *
-* @param	Addr contains the address to perform the input operation
-*		at.
+* @param	Addr: contains the address to perform the input operation
 *
-* @return	The Value read from the specified input address.
-*
-* @note		None.
+* @return	The 32 bit Value read from the specified input address.
 *
 ******************************************************************************/
 static INLINE u32 Xil_In32(UINTPTR Addr)
@@ -156,16 +156,13 @@ static INLINE u32 Xil_In32(UINTPTR Addr)
 /*****************************************************************************/
 /**
 *
-* Performs an input operation for a 64-bit memory location by reading the
-* specified Value to the the specified address.
+* @brief     Performs an input operation for a memory location by reading the
+*            64 bit Value read  from that address.
 *
-* @param	OutAddress contains the address to perform the output operation
-*		at.
-* @param	Value contains the Value to be output at the specified address.
 *
-* @return	None.
+* @param	Addr: contains the address to perform the input operation
 *
-* @note		None.
+* @return	The 64 bit Value read from the specified input address.
 *
 ******************************************************************************/
 static INLINE u64 Xil_In64(UINTPTR Addr)
@@ -176,17 +173,15 @@ static INLINE u64 Xil_In64(UINTPTR Addr)
 /*****************************************************************************/
 /**
 *
-* Performs an output operation for an 8-bit memory location by writing the
-* specified Value to the the specified address.
+* @brief    Performs an output operation for an memory location by
+*           writing the 8 bit Value to the the specified address.
 *
-* @param	Addr contains the address to perform the output operation
-*		at.
-* @param	Value contains the Value to be output at the specified address.
+* @param	Addr: contains the address to perform the output operation
+* @param	Value: contains the 8 bit Value to be written at the specified
+*           address.
 *
 * @return	None.
 *
-* @note		None.
-*
 ******************************************************************************/
 static INLINE void Xil_Out8(UINTPTR Addr, u8 Value)
 {
@@ -197,17 +192,14 @@ static INLINE void Xil_Out8(UINTPTR Addr, u8 Value)
 /*****************************************************************************/
 /**
 *
-* Performs an output operation for a 16-bit memory location by writing the
-* specified Value to the the specified address.
+* @brief    Performs an output operation for a memory location by writing the
+*            16 bit Value to the the specified address.
 *
 * @param	Addr contains the address to perform the output operation
-*		at.
-* @param	Value contains the Value to be output at the specified address.
+* @param	Value contains the Value to be written at the specified address.
 *
 * @return	None.
 *
-* @note		None.
-*
 ******************************************************************************/
 static INLINE void Xil_Out16(UINTPTR Addr, u16 Value)
 {
@@ -218,38 +210,37 @@ static INLINE void Xil_Out16(UINTPTR Addr, u16 Value)
 /*****************************************************************************/
 /**
 *
-* Performs an output operation for a 32-bit memory location by writing the
-* specified Value to the the specified address.
+* @brief    Performs an output operation for a memory location by writing the
+*           32 bit Value to the the specified address.
 *
 * @param	Addr contains the address to perform the output operation
-*		at.
-* @param	Value contains the Value to be output at the specified address.
+* @param	Value contains the 32 bit Value to be written at the specified
+*           address.
 *
 * @return	None.
 *
-* @note		None.
-*
 ******************************************************************************/
 static INLINE void Xil_Out32(UINTPTR Addr, u32 Value)
 {
+#ifndef ENABLE_SAFETY
 	volatile u32 *LocalAddr = (volatile u32 *)Addr;
 	*LocalAddr = Value;
+#else
+	XStl_RegUpdate(Addr, Value);
+#endif
 }
 
 /*****************************************************************************/
 /**
 *
-* Performs an output operation for a 64-bit memory location by writing the
-* specified Value to the the specified address.
+* @brief    Performs an output operation for a memory location by writing the
+*           64 bit Value to the the specified address.
 *
 * @param	Addr contains the address to perform the output operation
-*		at.
-* @param	Value contains the Value to be output at the specified address.
+* @param	Value contains 64 bit Value to be written at the specified address.
 *
 * @return	None.
 *
-* @note		None.
-*
 ******************************************************************************/
 static INLINE void Xil_Out64(UINTPTR Addr, u64 Value)
 {
@@ -312,7 +303,7 @@ static INLINE u32 Xil_In32LE(UINTPTR Addr)
 static INLINE u32 Xil_In32BE(UINTPTR Addr)
 #endif
 {
-	u16 value = Xil_In32(Addr);
+	u32 value = Xil_In32(Addr);
 	return Xil_EndianSwap32(value);
 }
 
@@ -349,3 +340,6 @@ static INLINE void Xil_Out32BE(UINTPTR Addr, u32 Value)
 #endif
 
 #endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_io_interfacing_apis".
+*/
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xil_macroback.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_macroback.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xil_macroback.h
rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_macroback.h
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_mem.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_mem.c
new file mode 100644
index 000000000..0929a6878
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_mem.c
@@ -0,0 +1,83 @@
+/******************************************************************************/
+/**
+* Copyright (C) 2015 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+* @file xil_mem.c
+*
+* This file contains xil mem copy function to use in case of word aligned
+* data copies.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 6.1   nsk      11/07/16 First release.
+*
+* 

+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+
+/***************** Inline Functions Definitions ********************/
+/*****************************************************************************/
+/**
+* @brief       This  function copies memory from once location to other.
+*
+* @param       dst: pointer pointing to destination memory
+*
+* @param       src: pointer pointing to source memory
+*
+* @param       cnt: 32 bit length of bytes to be copied
+*
+*****************************************************************************/
+void Xil_MemCpy(void* dst, const void* src, u32 cnt)
+{
+	char *d = (char*)(void *)dst;
+	const char *s = src;
+
+	while (cnt >= sizeof (int)) {
+		*(int*)d = *(int*)s;
+		d += sizeof (int);
+		s += sizeof (int);
+		cnt -= sizeof (int);
+	}
+	while ((cnt) > 0U){
+		*d = *s;
+		d += 1U;
+		s += 1U;
+		cnt -= 1U;
+	}
+}
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_mem.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_mem.h
new file mode 100644
index 000000000..a2d5e6681
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_mem.h
@@ -0,0 +1,59 @@
+/******************************************************************************/
+/**
+* Copyright (C) 2015 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+* @file xil_mem.h
+*
+* @addtogroup common_mem_operation_api Customized APIs for Memory Operations
+*
+* The xil_mem.h file contains prototype for functions related
+* to memory operations. These APIs are applicable for all processors supported
+* by Xilinx.
+*
+* @{
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 6.1   nsk      11/07/16 First release.
+*
+* 

+*
+*****************************************************************************/
+
+/************************** Function Prototypes *****************************/
+
+void Xil_MemCpy(void* dst, const void* src, u32 cnt);
+/**
+* @} End of "addtogroup common_mem_operation_api".
+*/
\ No newline at end of file
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xil_misc_psreset_api.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_misc_psreset_api.c
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xil_misc_psreset_api.c
rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_misc_psreset_api.c
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xil_misc_psreset_api.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_misc_psreset_api.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xil_misc_psreset_api.h
rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_misc_psreset_api.h
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xil_mmu.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_mmu.c
similarity index 85%
rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xil_mmu.c
rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_mmu.c
index 6f743bd2b..1f58d906b 100644
--- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xil_mmu.c
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_mmu.c
@@ -83,18 +83,21 @@ extern u32 MMUTable;
 
 /************************** Function Prototypes ******************************/
 
-/*****************************************************************************
+/*****************************************************************************/
+/**
+* @brief	This function sets the memory attributes for a section covering 1MB
+*			of memory in the translation table.
 *
-* Set the memory attributes for a section, in the translation table. Each
-* section covers 1MB of memory.
+* @param	Addr: 32-bit address for which memory attributes need to be set.
+* @param	attrib: Attribute for the given memory region. xil_mmu.h contains
+*			definitions of commonly used memory attributes which can be
+*			utilized for this function.
 *
-* @param	Addr is the address for which attributes are to be set.
-* @param	attrib specifies the attributes for that memory region.
 *
 * @return	None.
 *
-* @note		The MMU and D-cache need not be disabled before changing an
-*		translation table attribute.
+* @note		The MMU or D-cache does not need to be disabled before changing a
+*			translation table entry.
 *
 ******************************************************************************/
 void Xil_SetTlbAttributes(INTPTR Addr, u32 attrib)
@@ -119,9 +122,10 @@ void Xil_SetTlbAttributes(INTPTR Addr, u32 attrib)
     isb(); /* synchronize context on this processor */
 }
 
-/*****************************************************************************
-*
-* Invalidate the caches, enable MMU and D Caches for Cortex A9 processor.
+/*****************************************************************************/
+/**
+* @brief	Enable MMU for cortex A9 processor. This function invalidates the
+*			instruction and data caches, and then enables MMU.
 *
 * @param	None.
 * @return	None.
@@ -148,16 +152,18 @@ void Xil_EnableMMU(void)
 	isb();
 }
 
-/*****************************************************************************
-*
-* Disable MMU for Cortex A9 processors. This function invalidates the TLBs,
-* Branch Predictor Array and flushed the D Caches before disabling
-* the MMU and D cache.
+/*****************************************************************************/
+/**
+* @brief	Disable MMU for Cortex A9 processors. This function invalidates
+*			the TLBs, Branch Predictor Array and flushed the D Caches before
+*			disabling the MMU.
 *
 * @param	None.
 *
 * @return	None.
 *
+* @note		When the MMU is disabled, all the memory accesses are treated as
+*			strongly ordered.
 ******************************************************************************/
 void Xil_DisableMMU(void)
 {
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xil_mmu.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_mmu.h
similarity index 93%
rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xil_mmu.h
rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_mmu.h
index a41fae3cf..dd14b63b7 100644
--- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xil_mmu.h
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_mmu.h
@@ -33,7 +33,12 @@
 /**
 * @file xil_mmu.h
 *
+* @addtogroup a9_mmu_apis Cortex A9 Processor MMU Functions
 *
+* MMU functions equip users to enable MMU, disable MMU and modify default
+* memory attributes of MMU table as per the need.
+*
+* @{
 *
 * 
 * MODIFICATION HISTORY:
@@ -46,9 +51,6 @@
 * 5.4	pkp	 23/11/15 Added attribute definitions for Xil_SetTlbAttributes API
 * 

 *
-* @note
-*
-* None.
 *
 ******************************************************************************/
 
@@ -101,3 +103,6 @@ void Xil_DisableMMU(void);
 #endif /* __cplusplus */
 
 #endif /* XIL_MMU_H */
+/**
+* @} End of "addtogroup a9_mmu_apis".
+*/
\ No newline at end of file
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_printf.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_printf.c
similarity index 98%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_printf.c
rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_printf.c
index 9dffed148..dc0897f0d 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_printf.c
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_printf.c
@@ -75,8 +75,8 @@ static void outs(const charptr lp, struct params_s *par)
 		(par->num2)--;
 #ifdef STDOUT_BASEADDRESS
         outbyte(*LocalPtr);
-		LocalPtr += 1;
 #endif
+		LocalPtr += 1;
 }
 
     /* Pad on right if needed                        */
@@ -135,8 +135,8 @@ static void outnum( const s32 n, const s32 base, struct params_s *par)
     while (&outbuf[i] >= outbuf) {
 #ifdef STDOUT_BASEADDRESS
 	outbyte( outbuf[i] );
-		i--;
 #endif
+		i--;
 }
     padding( par->left_flag, par);
 }
@@ -239,6 +239,11 @@ static s32 getnum( charptr* linep)
 
 /* void esp_printf( const func_ptr f_ptr,
    const charptr ctrl1, ...) */
+#if HYP_GUEST && EL1_NONSECURE && XEN_USE_PV_CONSOLE
+void xil_printf( const char8 *ctrl1, ...){
+	XPVXenConsole_Printf(ctrl1);
+}
+#else
 void xil_printf( const char8 *ctrl1, ...)
 {
 	s32 Check;
@@ -262,8 +267,8 @@ void xil_printf( const char8 *ctrl1, ...)
         if (*ctrl != '%') {
 #ifdef STDOUT_BASEADDRESS
             outbyte(*ctrl);
-			ctrl += 1;
 #endif
+			ctrl += 1;
             continue;
         }
 
@@ -434,5 +439,5 @@ void xil_printf( const char8 *ctrl1, ...)
     }
     va_end( argp);
 }
-
+#endif
 /*---------------------------------------------------*/
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xil_printf.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_printf.h
similarity index 91%
rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xil_printf.h
rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_printf.h
index 2be5c5734..016ae3b2f 100644
--- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xil_printf.h
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_printf.h
@@ -10,6 +10,10 @@ extern "C" {
 #include 
 #include "xil_types.h"
 #include "xparameters.h"
+#include "bspconfig.h"
+#if HYP_GUEST && EL1_NONSECURE && XEN_USE_PV_CONSOLE
+#include "xen_console.h"
+#endif
 
 /*----------------------------------------------------*/
 /* Use the following parameter passing structure to   */
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_sleepcommon.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_sleepcommon.c
new file mode 100644
index 000000000..972a310a8
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_sleepcommon.c
@@ -0,0 +1,106 @@
+/******************************************************************************
+*
+* Copyright (C) 2017 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+*@file xil_sleepcommon.c
+*
+* This file contains the sleep API's
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 6.6 	srm  	 11/02/17 First release
+* 

+******************************************************************************/
+
+
+/***************************** Include Files *********************************/
+#include "xil_io.h"
+#include "sleep.h"
+
+/****************************  Constant Definitions  *************************/
+
+
+/*****************************************************************************/
+/**
+*
+* This API gives delay in sec
+*
+* @param            seconds - delay time in seconds
+*
+* @return           none
+*
+* @note             none
+*
+*****************************************************************************/
+ void sleep(unsigned int seconds)
+ {
+#if defined (ARMR5)
+	sleep_R5(seconds);
+#elif defined (__aarch64__) || defined (ARMA53_32)
+	sleep_A53(seconds);
+#elif defined (__MICROBLAZE__)
+	sleep_MB(seconds);
+#else
+	sleep_A9(seconds);
+#endif
+
+ }
+
+/****************************************************************************/
+/**
+*
+* This API gives delay in usec
+*
+* @param            useconds - delay time in useconds
+*
+* @return           none
+*
+* @note             none
+*
+*****************************************************************************/
+ void usleep(unsigned long useconds)
+ {
+#if defined (ARMR5)
+	usleep_R5(useconds);
+#elif defined (__aarch64__) || defined (ARMA53_32)
+	usleep_A53(useconds);
+#elif defined (__MICROBLAZE__)
+	usleep_MB(useconds);
+#else
+	usleep_A9(useconds);
+#endif
+
+ }
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_sleeptimer.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_sleeptimer.c
new file mode 100644
index 000000000..477260676
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_sleeptimer.c
@@ -0,0 +1,161 @@
+/******************************************************************************
+*
+* Copyright (C) 2017 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+/*****************************************************************************/
+/**
+*
+* @file xil_sleeptimer.c
+*
+* This file provides the common helper routines for the sleep API's
+*
+* 
+* MODIFICATION HISTORY :
+*
+* Ver   Who  Date	 Changes
+* ----- ---- -------- -------------------------------------------------------
+* 6.6	srm  10/18/17 First Release.
+*
+* 

+*****************************************************************************/
+
+/****************************  Include Files  ********************************/
+
+#include "xil_io.h"
+#include "xil_sleeptimer.h"
+#include "xtime_l.h"
+
+/****************************  Constant Definitions  *************************/
+
+
+/* Function definitions are applicable only when TTC3 is present*/
+#if defined (SLEEP_TIMER_BASEADDR)
+/****************************************************************************/
+/**
+*
+* This is a helper function used by sleep/usleep APIs to
+* have delay in sec/usec
+*
+* @param            delay - delay time in seconds/micro seconds
+*
+* @param            frequency - Number of counts per second/micro second
+*
+* @return           none
+*
+* @note             none
+*
+*****************************************************************************/
+void Xil_SleepTTCCommon(u32 delay, u64 frequency)
+{
+	INTPTR tEnd = 0U;
+	INTPTR tCur = 0U;
+	XCntrVal TimeHighVal = 0U;
+	XCntrVal TimeLowVal1 = 0U;
+	XCntrVal TimeLowVal2 = 0U;
+
+	TimeLowVal1 = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR +
+			XSLEEP_TIMER_TTC_COUNT_VALUE_OFFSET);
+	tEnd = (INTPTR)TimeLowVal1 + ((INTPTR)(delay) * frequency);
+	do
+	{
+		TimeLowVal2 = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR +
+				                  XSLEEP_TIMER_TTC_COUNT_VALUE_OFFSET);
+		if (TimeLowVal2 < TimeLowVal1) {
+			TimeHighVal++;
+		}
+		TimeLowVal1 = TimeLowVal2;
+		tCur = (((INTPTR) TimeHighVal) << XSLEEP_TIMER_REG_SHIFT) |
+								(INTPTR)TimeLowVal2;
+	}while (tCur < tEnd);
+}
+
+
+/*****************************************************************************/
+/**
+*
+* This API starts the Triple Timer Counter
+*
+* @param            none
+*
+* @return           none
+*
+* @note             none
+*
+*****************************************************************************/
+void XTime_StartTTCTimer()
+{
+	u32 TimerPrescalar;
+	u32 TimerCntrl;
+
+#if (defined (__aarch64__) && EL3==1) || defined (ARMR5) || defined (ARMA53_32)
+	u32 LpdRst;
+
+	LpdRst = XSleep_ReadCounterVal(RST_LPD_IOU2);
+
+	/* check if the timer is reset */
+	if (((LpdRst & (RST_LPD_IOU2_TTC_BASE_RESET_MASK <<
+					       XSLEEP_TTC_INSTANCE)) != 0 )) {
+		LpdRst = LpdRst & (~(RST_LPD_IOU2_TTC_BASE_RESET_MASK <<
+							XSLEEP_TTC_INSTANCE));
+		Xil_Out32(RST_LPD_IOU2, LpdRst);
+	} else {
+#endif
+		TimerCntrl = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR +
+					XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET);
+		/* check if Timer is disabled */
+		if ((TimerCntrl & XSLEEP_TIMER_TTC_CNT_CNTRL_DIS_MASK) == 0) {
+		    TimerPrescalar = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR +
+					       XSLEEP_TIMER_TTC_CLK_CNTRL_OFFSET);
+		/* check if Timer is configured with proper functionalty for sleep */
+		   if ((TimerPrescalar & XSLEEP_TIMER_TTC_CLK_CNTRL_PS_EN_MASK) == 0)
+						return;
+		}
+#if (defined (__aarch64__) && EL3==1) || defined (ARMR5) || defined (ARMA53_32)
+	}
+#endif
+	/* Disable the timer to configure */
+	TimerCntrl = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR +
+					XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET);
+	TimerCntrl = TimerCntrl | XSLEEP_TIMER_TTC_CNT_CNTRL_DIS_MASK;
+	Xil_Out32(SLEEP_TIMER_BASEADDR + XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET,
+			                 TimerCntrl);
+	/* Disable the prescalar */
+	TimerPrescalar = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR +
+			XSLEEP_TIMER_TTC_CLK_CNTRL_OFFSET);
+	TimerPrescalar = TimerPrescalar & (~XSLEEP_TIMER_TTC_CLK_CNTRL_PS_EN_MASK);
+	Xil_Out32(SLEEP_TIMER_BASEADDR + XSLEEP_TIMER_TTC_CLK_CNTRL_OFFSET,
+								TimerPrescalar);
+	/* Enable the Timer */
+	TimerCntrl = TimerCntrl & (~XSLEEP_TIMER_TTC_CNT_CNTRL_DIS_MASK);
+	Xil_Out32(SLEEP_TIMER_BASEADDR + XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET,
+								TimerCntrl);
+}
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_sleeptimer.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_sleeptimer.h
new file mode 100644
index 000000000..4bfac0ac4
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_sleeptimer.h
@@ -0,0 +1,116 @@
+/******************************************************************************
+*
+* Copyright (C) 2017 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_sleeptimer.h
+*
+* This header file contains ARM Cortex A53,A9,R5 specific sleep related APIs.
+* For sleep related functions that can be used across all Xilinx supported
+* processors, please use xil_sleeptimer.h.
+*
+*
+* 
+* MODIFICATION HISTORY :
+*
+* Ver   Who  Date	 Changes
+* ----- ---- -------- -------------------------------------------------------
+* 6.6	srm  10/18/17 First Release.
+*
+* 

+*****************************************************************************/
+
+#ifndef XIL_SLEEPTIMER_H		/* prevent circular inclusions */
+#define XIL_SLEEPTIMER_H		/* by using protection macros */
+/****************************  Include Files  ********************************/
+
+#include "xil_io.h"
+#include "xparameters.h"
+#include "bspconfig.h"
+
+/************************** Constant Definitions *****************************/
+
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32)
+#define XSLEEP_TIMER_REG_SHIFT  32U
+#define XSleep_ReadCounterVal   Xil_In32
+#define XCntrVal 			    u32
+#else
+#define XSLEEP_TIMER_REG_SHIFT  16U
+#define XSleep_ReadCounterVal   Xil_In16
+#define XCntrVal 			    u16
+#endif
+
+#if defined(ARMR5) || (defined (__aarch64__) && EL3==1) || defined (ARMA53_32)
+#define RST_LPD_IOU2 					    0xFF5E0238U
+#define RST_LPD_IOU2_TTC_BASE_RESET_MASK 	0x00000800U
+#endif
+
+#if defined (SLEEP_TIMER_BASEADDR)
+/** @name Register Map
+*
+* Register offsets from the base address of the TTC device
+*
+* @{
+*/
+ #define XSLEEP_TIMER_TTC_CLK_CNTRL_OFFSET		0x00000000U
+					     /**< Clock Control Register */
+ #define XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET		0x0000000CU
+	                                     /**< Counter Control Register*/
+ #define XSLEEP_TIMER_TTC_COUNT_VALUE_OFFSET	0x00000018U
+					     /**< Current Counter Value */
+/* @} */
+/** @name Clock Control Register
+* Clock Control Register definitions of TTC
+* @{
+*/
+ #define XSLEEP_TIMER_TTC_CLK_CNTRL_PS_EN_MASK		0x00000001U
+						   /**< Prescale enable */
+/* @} */
+/** @name Counter Control Register
+* Counter Control Register definitions of TTC
+* @{
+*/
+#define XSLEEP_TIMER_TTC_CNT_CNTRL_DIS_MASK		0x00000001U
+						/**< Disable the counter */
+#define XSLEEP_TIMER_TTC_CNT_CNTRL_RST_MASK		0x00000010U
+						  /**< Reset counter */
+/* @} */
+
+/**************************** Type Definitions *******************************/
+
+/************************** Function Prototypes ******************************/
+
+void Xil_SleepTTCCommon(u32 delay, u64 frequency);
+void XTime_StartTTCTimer();
+
+#endif
+#endif /* XIL_SLEEPTIMER_H */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_testcache.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_testcache.c
similarity index 83%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_testcache.c
rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_testcache.c
index a2c4b0bbf..157ad0836 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_testcache.c
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_testcache.c
@@ -47,7 +47,6 @@
 * 

 *
 * @note
-*
 * This file contain functions that all operate on HAL.
 *
 ******************************************************************************/
@@ -74,17 +73,21 @@ static INTPTR Data[DATA_LENGTH] __attribute__ ((aligned(64)));
 static INTPTR Data[DATA_LENGTH] __attribute__ ((aligned(32)));
 #endif
 
+
+/*****************************************************************************/
 /**
-* Perform DCache range related API test such as Xil_DCacheFlushRange and
-* Xil_DCacheInvalidateRange. This test function writes a constant value
-* to the Data array, flushes the range, writes a new value, then invalidates
-* the corresponding range.
+*
+* @brief    Perform DCache range related API test such as Xil_DCacheFlushRange
+*           and Xil_DCacheInvalidateRange. This test function writes a constant
+*           value to the Data array, flushes the range, writes a new value, then
+*           invalidates the corresponding range.
+* @param	None
 *
 * @return
+*      - -1 is returned for a failure
+*      - 0 is returned for a pass
 *
-*     - 0 is returned for a pass
-*     - -1 is returned for a failure
-*/
+*****************************************************************************/
 s32 Xil_TestDCacheRange(void)
 {
 	s32 Index;
@@ -204,16 +207,17 @@ s32 Xil_TestDCacheRange(void)
 
 }
 
+/*****************************************************************************/
 /**
-* Perform DCache all related API test such as Xil_DCacheFlush and
-* Xil_DCacheInvalidate. This test function writes a constant value
-* to the Data array, flushes the DCache, writes a new value, then invalidates
-* the DCache.
+* @brief    Perform DCache all related API test such as Xil_DCacheFlush and
+*           Xil_DCacheInvalidate. This test function writes a constant value
+*           to the Data array, flushes the DCache, writes a new value,
+*           then invalidates the DCache.
 *
 * @return
-*     - 0 is returned for a pass
-*     - -1 is returned for a failure
-*/
+*          - 0 is returned for a pass
+*          - -1 is returned for a failure
+*****************************************************************************/
 s32 Xil_TestDCacheAll(void)
 {
 	s32 Index;
@@ -328,15 +332,15 @@ s32 Xil_TestDCacheAll(void)
 	return Status;
 }
 
-
+/*****************************************************************************/
 /**
-* Perform Xil_ICacheInvalidateRange() on a few function pointers.
+* @brief   Perform Xil_ICacheInvalidateRange() on a few function pointers.
 *
 * @return
-*
 *     - 0 is returned for a pass
+* @note
 *     The function will hang if it fails.
-*/
+*****************************************************************************/
 s32 Xil_TestICacheRange(void)
 {
 
@@ -349,14 +353,15 @@ s32 Xil_TestICacheRange(void)
 	return 0;
 }
 
+/*****************************************************************************/
 /**
-* Perform Xil_ICacheInvalidate().
+* @brief     Perform Xil_ICacheInvalidate() on a few function pointers.
 *
 * @return
-*
-*     - 0 is returned for a pass
-*     The function will hang if it fails.
-*/
+*           - 0 is returned for a pass
+* @note
+* The function will hang if it fails.
+*****************************************************************************/
 s32 Xil_TestICacheAll(void)
 {
 	Xil_ICacheInvalidate();
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xil_testcache.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_testcache.h
similarity index 92%
rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xil_testcache.h
rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_testcache.h
index b3c416cd0..c35e9a463 100644
--- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xil_testcache.h
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_testcache.h
@@ -34,11 +34,16 @@
 *
 * @file xil_testcache.h
 *
-* This file contains utility functions to test cache.
+* @addtogroup common_test_utils
+* 
Cache test 

+* The xil_testcache.h file contains utility functions to test cache.
 *
+* @{
+* 
 * Ver    Who    Date    Changes
 * ----- ---- -------- -----------------------------------------------
 * 1.00a hbm  07/29/09 First release
+* 

 *
 ******************************************************************************/
 
@@ -61,3 +66,6 @@ extern s32 Xil_TestICacheAll(void);
 #endif
 
 #endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_test_utils".
+*/
\ No newline at end of file
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_testio.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_testio.c
similarity index 70%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_testio.c
rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_testio.c
index a68d7652f..e6a36807b 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_testio.c
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_testio.c
@@ -32,7 +32,7 @@
 /*****************************************************************************/
 /**
 *
-* @file xil_testmemend.c
+* @file xil_testio.c
 *
 * Contains the memory test utility functions.
 *
@@ -95,18 +95,17 @@ static u32 Swap32(u32 Data)
 /*****************************************************************************/
 /**
 *
-* Perform a destructive 8-bit wide register IO test where the register is
-* accessed using Xil_Out8 and Xil_In8, and comparing the reading and writing
-* values.
+* @brief    Perform a destructive 8-bit wide register IO test where the
+*           register is accessed using Xil_Out8 and Xil_In8, and comparing
+*           the written values by reading them back.
 *
-* @param	Addr is a pointer to the region of memory to be tested.
-* @param	Length is the Length of the block.
-* @param	Value is the constant used for writting the memory.
+* @param	Addr: a pointer to the region of memory to be tested.
+* @param	Length: Length of the block.
+* @param	Value: constant used for writting the memory.
 *
 * @return
-*
-* - -1 is returned for a failure
-* - 0 is returned for a pass
+*           - -1 is returned for a failure
+*           - 0 is returned for a pass
 *
 *****************************************************************************/
 
@@ -133,24 +132,24 @@ s32 Xil_TestIO8(u8 *Addr, s32 Length, u8 Value)
 /*****************************************************************************/
 /**
 *
-* Perform a destructive 16-bit wide register IO test. Each location is tested
-* by sequentially writing a 16-bit wide register, reading the register, and
-* comparing value. This function tests three kinds of register IO functions,
-* normal register IO, little-endian register IO, and big-endian register IO.
-* When testing little/big-endian IO, the function performs the following
-* sequence, Xil_Out16LE/Xil_Out16BE, Xil_In16, Compare In-Out values,
-* Xil_Out16, Xil_In16LE/Xil_In16BE, Compare In-Out values. Whether to swap the
-* read-in value before comparing is controlled by the 5th argument.
+* @brief   Perform a destructive 16-bit wide register IO test. Each location
+*          is tested by sequentially writing a 16-bit wide register, reading
+*          the register, and comparing value. This function tests three kinds
+*          of register IO functions, normal register IO, little-endian register
+*          IO, and big-endian register IO. When testing little/big-endian IO,
+*          the function performs the following sequence, Xil_Out16LE/Xil_Out16BE,
+*          Xil_In16, Compare In-Out values, Xil_Out16, Xil_In16LE/Xil_In16BE,
+*          Compare In-Out values. Whether to swap the read-in value before
+*          comparing is controlled by the 5th argument.
 *
-* @param	Addr is a pointer to the region of memory to be tested.
-* @param	Length is the Length of the block.
-* @param	Value is the constant used for writting the memory.
-* @param	Kind is the test kind. Acceptable values are:
-*		XIL_TESTIO_DEFAULT, XIL_TESTIO_LE, XIL_TESTIO_BE.
-* @param	Swap indicates whether to byte swap the read-in value.
+* @param	Addr: a pointer to the region of memory to be tested.
+* @param	Length: Length of the block.
+* @param	Value: constant used for writting the memory.
+* @param	Kind: Type of test. Acceptable values are:
+*		    XIL_TESTIO_DEFAULT, XIL_TESTIO_LE, XIL_TESTIO_BE.
+* @param	Swap: indicates whether to byte swap the read-in value.
 *
 * @return
-*
 * - -1 is returned for a failure
 * - 0 is returned for a pass
 *
@@ -219,26 +218,25 @@ s32 Xil_TestIO16(u16 *Addr, s32 Length, u16 Value, s32 Kind, s32 Swap)
 /*****************************************************************************/
 /**
 *
-* Perform a destructive 32-bit wide register IO test. Each location is tested
-* by sequentially writing a 32-bit wide regsiter, reading the register, and
-* comparing value. This function tests three kinds of register IO functions,
-* normal register IO, little-endian register IO, and big-endian register IO.
-* When testing little/big-endian IO, the function perform the following
-* sequence, Xil_Out32LE/Xil_Out32BE, Xil_In32, Compare,
-* Xil_Out32, Xil_In32LE/Xil_In32BE, Compare. Whether to swap the read-in value
-* before comparing is controlled by the 5th argument.
-*
-* @param	Addr is a pointer to the region of memory to be tested.
-* @param	Length is the Length of the block.
-* @param	Value is the constant used for writting the memory.
-* @param	Kind is the test kind. Acceptable values are:
-*		XIL_TESTIO_DEFAULT, XIL_TESTIO_LE, XIL_TESTIO_BE.
-* @param	Swap indicates whether to byte swap the read-in value.
+* @brief    Perform a destructive 32-bit wide register IO test. Each location
+*           is tested by sequentially writing a 32-bit wide regsiter, reading
+*           the register, and comparing value. This function tests three kinds
+*           of register IO functions, normal register IO, little-endian register IO,
+*           and big-endian register IO. When testing little/big-endian IO,
+*           the function perform the following sequence, Xil_Out32LE/
+*           Xil_Out32BE, Xil_In32, Compare, Xil_Out32, Xil_In32LE/Xil_In32BE, Compare.
+*           Whether to swap the read-in value *before comparing is controlled
+*           by the 5th argument.
+* @param	Addr: a pointer to the region of memory to be tested.
+* @param	Length: Length of the block.
+* @param	Value: constant used for writting the memory.
+* @param	Kind: type of test. Acceptable values are:
+*		    XIL_TESTIO_DEFAULT, XIL_TESTIO_LE, XIL_TESTIO_BE.
+* @param	Swap: indicates whether to byte swap the read-in value.
 *
 * @return
-*
-* - -1 is returned for a failure
-* - 0 is returned for a pass
+*           - -1 is returned for a failure
+*           - 0 is returned for a pass
 *
 *****************************************************************************/
 s32 Xil_TestIO32(u32 *Addr, s32 Length, u32 Value, s32 Kind, s32 Swap)
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xil_testio.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_testio.h
similarity index 93%
rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xil_testio.h
rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_testio.h
index fba0c1060..ad68ead64 100644
--- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xil_testio.h
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_testio.h
@@ -32,19 +32,19 @@
 /*****************************************************************************/
 /**
 *
-* @file xil_testmemend.h
+* @file xil_testio.h
 *
-* This file contains utility functions to teach endian related memory
+* @addtogroup common_test_utils Test Utilities
+* 
I/O test 

+* The xil_testio.h file contains utility functions to test endian related memory
 * IO functions.
 *
-* Memory test description
-*
 * A subset of the memory tests can be selected or all of the tests can be run
 * in order. If there is an error detected by a subtest, the test stops and the
 * failure code is returned. Further tests are not run even if all of the tests
 * are selected.
 *
-*
+* @{
 * 
 * MODIFICATION HISTORY:
 *
@@ -89,3 +89,6 @@ extern s32 Xil_TestIO32(u32 *Addr, s32 Length, u32 Value, s32 Kind, s32 Swap);
 #endif
 
 #endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_test_utils".
+*/
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_testmem.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_testmem.c
similarity index 92%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_testmem.c
rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_testmem.c
index 19a3b6608..87426d17a 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_testmem.c
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_testmem.c
@@ -66,22 +66,20 @@ static u32 RotateRight(u32 Input, u8 Width);
 /*****************************************************************************/
 /**
 *
-* Perform a destructive 32-bit wide memory test.
+* @brief    Perform a destructive 32-bit wide memory test.
 *
-* @param    Addr is a pointer to the region of memory to be tested.
-* @param    Words is the length of the block.
-* @param    Pattern is the constant used for the constant pattern test, if 0,
+* @param    Addr: pointer to the region of memory to be tested.
+* @param    Words: length of the block.
+* @param    Pattern: constant used for the constant pattern test, if 0,
 *           0xDEADBEEF is used.
-* @param    Subtest is the test selected. See xil_testmem.h for possible
-*	    values.
+* @param    Subtest: test type selected. See xil_testmem.h for possible
+*	        values.
 *
 * @return
-*
-* - 0 is returned for a pass
-* - -1 is returned for a failure
+*           - 0 is returned for a pass
+*           - 1 is returned for a failure
 *
 * @note
-*
 * Used for spaces where the address range of the region is smaller than
 * the data width. If the memory range is greater than 2 ** Width,
 * the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
@@ -315,22 +313,21 @@ End_Label:
 /*****************************************************************************/
 /**
 *
-* Perform a destructive 16-bit wide memory test.
+* @brief    Perform a destructive 16-bit wide memory test.
 *
-* @param    Addr is a pointer to the region of memory to be tested.
-* @param    Words is the length of the block.
-* @param    Pattern is the constant used for the constant Pattern test, if 0,
+* @param    Addr: pointer to the region of memory to be tested.
+* @param    Words: length of the block.
+* @param    Pattern: constant used for the constant Pattern test, if 0,
 *           0xDEADBEEF is used.
-* @param    Subtest is the test selected. See xil_testmem.h for possible
-*	    values.
+* @param    Subtest: type of test selected. See xil_testmem.h for possible
+*	        values.
 *
 * @return
 *
-* - -1 is returned for a failure
-* - 0 is returned for a pass
+*           - -1 is returned for a failure
+*           - 0 is returned for a pass
 *
 * @note
-*
 * Used for spaces where the address range of the region is smaller than
 * the data width. If the memory range is greater than 2 ** Width,
 * the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
@@ -549,22 +546,20 @@ End_Label:
 /*****************************************************************************/
 /**
 *
-* Perform a destructive 8-bit wide memory test.
+* @brief    Perform a destructive 8-bit wide memory test.
 *
-* @param    Addr is a pointer to the region of memory to be tested.
-* @param    Words is the length of the block.
-* @param    Pattern is the constant used for the constant pattern test, if 0,
+* @param    Addr: pointer to the region of memory to be tested.
+* @param    Words: length of the block.
+* @param    Pattern: constant used for the constant pattern test, if 0,
 *           0xDEADBEEF is used.
-* @param    Subtest is the test selected. See xil_testmem.h for possible
-*	    values.
+* @param    Subtest: type of test selected. See xil_testmem.h for possible
+*	        values.
 *
 * @return
-*
-* - -1 is returned for a failure
-* - 0 is returned for a pass
+*           - -1 is returned for a failure
+*           - 0 is returned for a pass
 *
 * @note
-*
 * Used for spaces where the address range of the region is smaller than
 * the data width. If the memory range is greater than 2 ** Width,
 * the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
@@ -777,18 +772,14 @@ End_Label:
 /*****************************************************************************/
 /**
 *
-* Rotates the provided value to the left one bit position
+* @brief   Rotates the provided value to the left one bit position
 *
 * @param    Input is value to be rotated to the left
 * @param    Width is the number of bits in the input data
 *
 * @return
+*           The resulting unsigned long value of the rotate left
 *
-* The resulting unsigned long value of the rotate left
-*
-* @note
-*
-* None.
 *
 *****************************************************************************/
 static u32 RotateLeft(u32 Input, u8 Width)
@@ -831,18 +822,13 @@ static u32 RotateLeft(u32 Input, u8 Width)
 /*****************************************************************************/
 /**
 *
-* Rotates the provided value to the right one bit position
+* @brief    Rotates the provided value to the right one bit position
 *
-* @param    Input is value to be rotated to the right
-* @param    Width is the number of bits in the input data
+* @param    Input: value to be rotated to the right
+* @param    Width: number of bits in the input data
 *
 * @return
-*
-* The resulting u32 value of the rotate right
-*
-* @note
-*
-* None.
+*           The resulting u32 value of the rotate right
 *
 *****************************************************************************/
 static u32 RotateRight(u32 Input, u8 Width)
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xil_testmem.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_testmem.h
similarity index 79%
rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xil_testmem.h
rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_testmem.h
index 4cbfd878b..c20472822 100644
--- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xil_testmem.h
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_testmem.h
@@ -33,64 +33,57 @@
 /**
 *
 * @file xil_testmem.h
+* @addtogroup common_test_utils
 *
-* This file contains utility functions to test memory.
-*
-* Memory test description
+* 
Memory test

 *
+* The xil_testmem.h file contains utility functions to test memory.
 * A subset of the memory tests can be selected or all of the tests can be run
 * in order. If there is an error detected by a subtest, the test stops and the
 * failure code is returned. Further tests are not run even if all of the tests
 * are selected.
+* Following list describes the supported memory tests:
 *
-* Subtest descriptions:
-* 
-* XIL_TESTMEM_ALLMEMTESTS:
-*       Runs all of the following tests
+*  - XIL_TESTMEM_ALLMEMTESTS: This test runs all of the subtests.
 *
-* XIL_TESTMEM_INCREMENT:
-*       Incrementing Value Test.
-*       This test starts at 'XIL_TESTMEM_INIT_VALUE' and uses the
-*	incrementing value as the test value for memory.
+*  - XIL_TESTMEM_INCREMENT: This test
+* starts at 'XIL_TESTMEM_INIT_VALUE' and uses the incrementing value as the
+* test value for memory.
 *
-* XIL_TESTMEM_WALKONES:
-*       Walking Ones Test.
-*       This test uses a walking '1' as the test value for memory.
-*       location 1 = 0x00000001
-*       location 2 = 0x00000002
-*       ...
+*  - XIL_TESTMEM_WALKONES: Also known as the Walking ones test. This test
+* uses a walking '1' as the test value for memory.
+* @code
+*          location 1 = 0x00000001
+*          location 2 = 0x00000002
+*          ...
+* @endcode
 *
-* XIL_TESTMEM_WALKZEROS:
-*       Walking Zero's Test.
-*       This test uses the inverse value of the walking ones test
-*       as the test value for memory.
+*  - XIL_TESTMEM_WALKZEROS: Also known as the Walking zero's test.
+* This test uses the inverse value of the walking ones test
+* as the test value for memory.
+* @code
 *       location 1 = 0xFFFFFFFE
 *       location 2 = 0xFFFFFFFD
 *       ...
+*@endcode
 *
-* XIL_TESTMEM_INVERSEADDR:
-*       Inverse Address Test.
-*       This test uses the inverse of the address of the location under test
-*       as the test value for memory.
+*  - XIL_TESTMEM_INVERSEADDR: Also known as the inverse address test.
+* This test uses the inverse of the address of the location under test
+* as the test value for memory.
 *
-* XIL_TESTMEM_FIXEDPATTERN:
-*       Fixed Pattern Test.
-*       This test uses the provided patters as the test value for memory.
-*       If zero is provided as the pattern the test uses '0xDEADBEEF".
-* 

-*
-* WARNING
+*  - XIL_TESTMEM_FIXEDPATTERN: Also known as the fixed pattern test.
+* This test uses the provided patters as the test value for memory.
+* If zero is provided as the pattern the test uses '0xDEADBEEF".
 *
+* @warning
 * The tests are DESTRUCTIVE. Run before any initialized memory spaces
 * have been set up.
-*
 * The address provided to the memory tests is not checked for
 * validity except for the NULL case. It is possible to provide a code-space
 * pointer for this test to start with and ultimately destroy executable code
 * causing random failures.
 *
 * @note
-*
 * Used for spaces where the address range of the region is smaller than
 * the data width. If the memory range is greater than 2 ** width,
 * the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
@@ -160,3 +153,6 @@ extern s32 Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest);
 #endif
 
 #endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_test_utils".
+*/
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xil_types.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_types.h
similarity index 76%
rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xil_types.h
rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_types.h
index e8b78b7c6..8143aff1e 100644
--- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xil_types.h
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xil_types.h
@@ -34,9 +34,11 @@
 *
 * @file xil_types.h
 *
-* This file contains basic types for Xilinx software IP.
-
+* @addtogroup common_types Basic Data types for Xilinx® Software IP
 *
+* The xil_types.h file contains basic types for Xilinx software IP. These data types
+* are applicable for all processors supported by Xilinx.
+* @{
 * 
 * MODIFICATION HISTORY:
 *
@@ -71,22 +73,28 @@
 #define NULL		0U
 #endif
 
-#define XIL_COMPONENT_IS_READY     0x11111111U  /**< component has been initialized */
-#define XIL_COMPONENT_IS_STARTED   0x22222222U  /**< component has been started */
+#define XIL_COMPONENT_IS_READY     0x11111111U  /**< In device drivers, This macro will be
+                                                 assigend to "IsReady" member of driver
+												 instance to indicate that driver
+												 instance is initialized and ready to use. */
+#define XIL_COMPONENT_IS_STARTED   0x22222222U  /**< In device drivers, This macro will be assigend to
+                                                 "IsStarted" member of driver instance
+												 to indicate that driver instance is
+												 started and it can be enabled. */
 
-/** @name New types
+/* @name New types
  * New simple types.
  * @{
  */
 #ifndef __KERNEL__
 #ifndef XBASIC_TYPES_H
-/**
+/*
  * guarded against xbasic_types.h.
  */
 typedef uint8_t u8;
 typedef uint16_t u16;
 typedef uint32_t u32;
-
+/** @}*/
 #define __XUINT64__
 typedef struct
 {
@@ -97,36 +105,32 @@ typedef struct
 
 /*****************************************************************************/
 /**
-* Return the most significant half of the 64 bit data type.
+* @brief    Return the most significant half of the 64 bit data type.
 *
 * @param    x is the 64 bit word.
 *
 * @return   The upper 32 bits of the 64 bit word.
 *
-* @note     None.
-*
 ******************************************************************************/
 #define XUINT64_MSW(x) ((x).Upper)
 
 /*****************************************************************************/
 /**
-* Return the least significant half of the 64 bit data type.
+* @brief    Return the least significant half of the 64 bit data type.
 *
 * @param    x is the 64 bit word.
 *
 * @return   The lower 32 bits of the 64 bit word.
 *
-* @note     None.
-*
 ******************************************************************************/
 #define XUINT64_LSW(x) ((x).Lower)
 
 #endif /* XBASIC_TYPES_H */
 
-/**
+/*
  * xbasic_types.h does not typedef s* or u64
  */
-
+/** @{ */
 typedef char char8;
 typedef int8_t s8;
 typedef int16_t s16;
@@ -138,7 +142,7 @@ typedef int sint32;
 typedef intptr_t INTPTR;
 typedef uintptr_t UINTPTR;
 typedef ptrdiff_t PTRDIFF;
-
+/** @}*/
 #if !defined(LONG) || !defined(ULONG)
 typedef long LONG;
 typedef unsigned long ULONG;
@@ -151,7 +155,7 @@ typedef unsigned long ULONG;
 #include 
 #endif
 
-
+/** @{ */
 /**
  * This data type defines an interrupt handler for a device.
  * The argument points to the instance of the component
@@ -165,22 +169,24 @@ typedef void (*XInterruptHandler) (void *InstancePtr);
 typedef void (*XExceptionHandler) (void *InstancePtr);
 
 /**
- * UPPER_32_BITS - return bits 32-63 of a number
- * @n: the number we're accessing
+ * @brief  Returns 32-63 bits of a number.
+ * @param  n : Number being accessed.
+ * @return Bits 32-63 of number.
  *
- * A basic shift-right of a 64- or 32-bit quantity.  Use this to suppress
- * the "right shift count >= width of type" warning when that quantity is
- * 32-bits.
+ * @note    A basic shift-right of a 64- or 32-bit quantity.
+ *          Use this to suppress the "right shift count >= width of type"
+ *          warning when that quantity is 32-bits.
  */
 #define UPPER_32_BITS(n) ((u32)(((n) >> 16) >> 16))
 
 /**
- * LOWER_32_BITS - return bits 0-31 of a number
- * @n: the number we're accessing
+ * @brief  Returns 0-31 bits of a number
+ * @param  n : Number being accessed.
+ * @return Bits 0-31 of number
  */
 #define LOWER_32_BITS(n) ((u32)(n))
 
-/*@}*/
+
 
 
 /************************** Constant Definitions *****************************/
@@ -198,3 +204,6 @@ typedef void (*XExceptionHandler) (void *InstancePtr);
 #endif
 
 #endif	/* end of protection macro */
+/**
+* @} End of "addtogroup common_types".
+*/
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xl2cc.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xl2cc.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xl2cc.h
rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xl2cc.h
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xl2cc_counter.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xl2cc_counter.c
similarity index 86%
rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xl2cc_counter.c
rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xl2cc_counter.c
index c9993950a..d6b88cb39 100644
--- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xl2cc_counter.c
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xl2cc_counter.c
@@ -74,16 +74,16 @@ void XL2cc_EventCtrReset(void);
 /****************************************************************************/
 /**
 *
-* This function initializes the event counters in L2 Cache controller with a
-* set of event codes specified by the user.
+* @brief	This function initializes the event counters in L2 Cache controller
+*			with a set of event codes specified by the user.
 *
-* @param	Event0 is the event code for counter 0.
-* @param	Event1 is the event code for counter 1.
-*		Use the event codes defined by XL2CC_* in xl2cc_counter.h.
+* @param	Event0: Event code for counter 0.
+* @param	Event1: Event code for counter 1.
 *
 * @return	None.
 *
-* @note		None.
+* @note		The definitions for event codes XL2CC_* can be found in
+*			xl2cc_counter.h.
 *
 *****************************************************************************/
 void XL2cc_EventCtrInit(s32 Event0, s32 Event1)
@@ -99,10 +99,11 @@ void XL2cc_EventCtrInit(s32 Event0, s32 Event1)
 	XL2cc_EventCtrReset();
 }
 
+
 /****************************************************************************/
 /**
 *
-* This function starts the event counters in L2 Cache controller.
+* @brief	This function starts the event counters in L2 Cache controller.
 *
 * @param	None.
 *
@@ -125,13 +126,13 @@ void XL2cc_EventCtrStart(void)
 /****************************************************************************/
 /**
 *
-* This function disables the event counters in L2 Cache controller, saves the
-* counter values and resets the counters.
+* @brief	This function disables the event counters in L2 Cache controller,
+*			saves the counter values and resets the counters.
 *
-* @param	EveCtr0 is an output parameter which is used to return the value
-*		in event counter 0.
-*		EveCtr1 is an output parameter which is used to return the value
-*		in event counter 1.
+* @param	EveCtr0: Output parameter which is used to return the value
+*			in event counter 0.
+*			EveCtr1: Output parameter which is used to return the value
+*			in event counter 1.
 *
 * @return	None.
 *
@@ -153,7 +154,7 @@ void XL2cc_EventCtrStop(u32 *EveCtr0, u32 *EveCtr1)
 /****************************************************************************/
 /**
 *
-* This function resets the event counters in L2 Cache controller.
+* @brief	This function resets the event counters in L2 Cache controller.
 *
 * @param	None.
 *
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xl2cc_counter.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xl2cc_counter.h
similarity index 87%
rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xl2cc_counter.h
rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xl2cc_counter.h
index e1557acfc..8d0a61f07 100644
--- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xl2cc_counter.h
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xl2cc_counter.h
@@ -34,15 +34,17 @@
 *
 * @file xl2cc_counter.h
 *
-* This header file contains APIs for configuring and controlling the event
-* counters in PL310 L2 cache controller.
-* PL310 has 2 event counters which can be used to count a variety of events
-* like DRHIT, DRREQ, DWHIT, DWREQ, etc. This file defines configurations,
-* where value configures the event counters to count a set of events.
+* @addtogroup l2_event_counter_apis PL310 L2 Event Counters Functions
 *
-* XL2cc_EventCtrInit API can be used to select a set of events and
-* XL2cc_EventCtrStart configures the event counters and starts the counters.
-* XL2cc_EventCtrStop diables the event counters and returns the counter values.
+* xl2cc_counter.h contains APIs for configuring and controlling the event
+* counters in PL310 L2 cache controller.
+* PL310 has two event counters which can be used to count variety of events
+* like DRHIT, DRREQ, DWHIT, DWREQ, etc. xl2cc_counter.h contains definitions
+* for different configurations which can be used for the event counters to
+* count a set of events.
+*
+*
+* @{
 *
 * 
 * MODIFICATION HISTORY:
@@ -106,3 +108,6 @@ void XL2cc_EventCtrStop(u32 *EveCtr0, u32 *EveCtr1);
 #endif /* __cplusplus */
 
 #endif /* L2CCCOUNTER_H */
+/**
+* @} End of "addtogroup l2_event_counter_apis".
+*/
\ No newline at end of file
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xparameters_ps.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xparameters_ps.h
similarity index 98%
rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xparameters_ps.h
rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xparameters_ps.h
index ea0d2bcde..0fa77710d 100644
--- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xparameters_ps.h
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xparameters_ps.h
@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2010 - 2017 Xilinx, Inc.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
@@ -45,6 +45,8 @@
 * 3.04a sdm     02/02/12 Removed some of the defines as they are being generated through
 *                        driver tcl
 * 5.0	pkp		01/16/15 Added interrupt ID definition of ttc for TEST APP
+* 6.6   srm     10/18/17 Added ARMA9 macro to identify CortexA9
+*
 * 

 *
 * @note
@@ -60,6 +62,9 @@
 extern "C" {
 #endif
 
+/****************************  Include Files  *******************************/
+
+
 /************************** Constant Definitions *****************************/
 
 /*
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xplatform_info.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xplatform_info.c
similarity index 73%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xplatform_info.c
rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xplatform_info.c
index 9d4560a98..2c08e5f2e 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xplatform_info.c
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xplatform_info.c
@@ -45,6 +45,13 @@
 * 5.04  pkp  01/12/16 Added platform information support for Cortex-A53 32bit
 *					  mode
 * 6.00  mus  17/08/16 Removed unused variable from XGetPlatform_Info
+* 6.4   ms   05/23/17 Added PSU_PMU macro to support XGetPSVersion_Info
+*                     function for PMUFW.
+*       ms   06/13/17 Added PSU_PMU macro to provide support of
+*                     XGetPlatform_Info function for PMUFW.
+*       mus  08/17/17 Add EL1 NS mode support for
+*                     XGet_Zynq_UltraMp_Platform_info and XGetPSVersion_Info
+*                     APIs.
 * 

 *
 ******************************************************************************/
@@ -54,7 +61,10 @@
 #include "xil_types.h"
 #include "xil_io.h"
 #include "xplatform_info.h"
-
+#if defined (__aarch64__)
+#include "bspconfig.h"
+#include "xil_smc.h"
+#endif
 /************************** Constant Definitions *****************************/
 
 /**************************** Type Definitions *******************************/
@@ -69,19 +79,17 @@
 /*****************************************************************************/
 /**
 *
-* This API is used to provide information about platform
+* @brief    This API is used to provide information about platform
 *
 * @param    None.
 *
 * @return   The information about platform defined in xplatform_info.h
 *
-* @note     None.
-*
 ******************************************************************************/
 u32 XGetPlatform_Info()
 {
 
-#if defined (ARMR5) || (__aarch64__) || (ARMA53_32)
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) || (PSU_PMU)
 	return XPLAT_ZYNQ_ULTRA_MP;
 #elif (__microblaze__)
 	return XPLAT_MICROBLAZE;
@@ -93,43 +101,61 @@ u32 XGetPlatform_Info()
 /*****************************************************************************/
 /**
 *
-* This API is used to provide information about zynq ultrascale MP platform
+* @brief    This API is used to provide information about zynq ultrascale MP platform
 *
 * @param    None.
 *
 * @return   The information about zynq ultrascale MP platform defined in
 *			xplatform_info.h
 *
-* @note     None.
-*
 ******************************************************************************/
 #if defined (ARMR5) || (__aarch64__) || (ARMA53_32)
 u32 XGet_Zynq_UltraMp_Platform_info()
 {
+#if EL1_NONSECURE
+	XSmc_OutVar reg;
+    /*
+	 * This SMC call will return,
+     *  idcode - upper 32 bits of reg.Arg0
+     *  version - lower 32 bits of reg.Arg1
+	 */
+	reg = Xil_Smc(GET_CHIPID_SMC_FID,0,0, 0, 0, 0, 0, 0);
+	return (u32)((reg.Arg1 >> XPLAT_INFO_SHIFT) & XPLAT_INFO_MASK);
+#else
 	u32 reg;
 	reg = ((Xil_In32(XPAR_CSU_BASEADDR + XPAR_CSU_VER_OFFSET) >> 12U )& XPLAT_INFO_MASK);
 	return reg;
+#endif
 }
 #endif
 
 /*****************************************************************************/
 /**
 *
-* This API is used to provide information about PS Silicon version
+* @brief    This API is used to provide information about PS Silicon version
 *
 * @param    None.
 *
 * @return   The information about PS Silicon version.
 *
-* @note     None.
-*
 ******************************************************************************/
-#if defined (ARMR5) || (__aarch64__) || (ARMA53_32)
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) || (PSU_PMU)
 u32 XGetPSVersion_Info()
 {
+#if EL1_NONSECURE
+        /*
+         * This SMC call will return,
+         *  idcode - upper 32 bits of reg.Arg0
+         *  version - lower 32 bits of reg.Arg1
+         */
+        XSmc_OutVar reg;
+        reg = Xil_Smc(GET_CHIPID_SMC_FID,0,0, 0, 0, 0, 0, 0);
+        return (u32)(reg.Arg1 &  XPS_VERSION_INFO_MASK);
+#else
 	u32 reg;
 	reg = (Xil_In32(XPAR_CSU_BASEADDR + XPAR_CSU_VER_OFFSET)
 			& XPS_VERSION_INFO_MASK);
 	return reg;
+#endif
 }
 #endif
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xplatform_info.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xplatform_info.h
similarity index 80%
rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xplatform_info.h
rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xplatform_info.h
index 7028a83af..0582222bc 100644
--- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xplatform_info.h
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xplatform_info.h
@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2014 - 2015 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2014 - 2017 Xilinx, Inc.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
@@ -34,7 +34,21 @@
 *
 * @file xplatform_info.h
 *
-* This file contains definitions for various platforms available
+* @addtogroup common_platform_info APIs to Get Platform Information
+*
+* The xplatform_info.h file contains definitions for various available Xilinx®
+* platforms. Also, it contains prototype of APIs, which can be used to get the
+* platform information.
+*
+* @{
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date    Changes
+* ----- ---- --------- -------------------------------------------------------
+* 6.4    ms   05/23/17 Added PSU_PMU macro to support XGetPSVersion_Info
+*                      function for PMUFW.
+* 

 *
 ******************************************************************************/
 
@@ -65,6 +79,7 @@ extern "C" {
 #define XPS_VERSION_2 0x1
 
 #define XPLAT_INFO_MASK (0xF)
+#define XPLAT_INFO_SHIFT (0xC)
 #define XPS_VERSION_INFO_MASK (0xF)
 
 /**************************** Type Definitions *******************************/
@@ -74,7 +89,7 @@ extern "C" {
 
 u32 XGetPlatform_Info();
 
-#if defined (ARMR5) || (__aarch64__) || (ARMA53_32)
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) || (PSU_PMU)
 u32 XGetPSVersion_Info();
 #endif
 
@@ -89,3 +104,6 @@ u32 XGet_Zynq_UltraMp_Platform_info();
 #endif
 
 #endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_platform_info".
+*/
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xpm_counter.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xpm_counter.c
similarity index 90%
rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xpm_counter.c
rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xpm_counter.c
index 75c9b4943..d0765b600 100644
--- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xpm_counter.c
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xpm_counter.c
@@ -75,7 +75,7 @@ void Xpm_ResetEventCounters (void);
 /****************************************************************************/
 /**
 *
-* This function disables the Cortex A9 event counters.
+* @brief	This function disables the Cortex A9 event counters.
 *
 * @param	None.
 *
@@ -93,7 +93,7 @@ void Xpm_DisableEventCounters(void)
 /****************************************************************************/
 /**
 *
-* This function enables the Cortex A9 event counters.
+* @brief	This function enables the Cortex A9 event counters.
 *
 * @param	None.
 *
@@ -111,7 +111,7 @@ void Xpm_EnableEventCounters(void)
 /****************************************************************************/
 /**
 *
-* This function resets the Cortex A9 event counters.
+* @brief	This function resets the Cortex A9 event counters.
 *
 * @param	None.
 *
@@ -138,13 +138,13 @@ void Xpm_ResetEventCounters(void)
 
 /****************************************************************************/
 /**
+* @brief	This function configures the Cortex A9 event counters controller,
+*			with the event codes, in a configuration selected by the user and
+*			enables the counters.
 *
-* This function configures the Cortex A9 event counters controller, with the
-* event codes, in a configuration selected by the user and enables the counters.
-*
-* @param	PmcrCfg is configuration value based on which the event counters
-*		are configured.
-*		Use XPM_CNTRCFG* values defined in xpm_counter.h.
+* @param	PmcrCfg: Configuration value based on which the event counters
+*			are configured. XPM_CNTRCFG* values defined in xpm_counter.h can
+*			be utilized for setting configuration.
 *
 * @return	None.
 *
@@ -264,11 +264,12 @@ void Xpm_SetEvents(s32 PmcrCfg)
 /****************************************************************************/
 /**
 *
-* This function disables the event counters and returns the counter values.
+* @brief	This function disables the event counters and returns the counter
+*			values.
 *
-* @param	PmCtrValue is a pointer to an array of type u32 PmCtrValue[6].
-*		It is an output parameter which is used to return the PM
-*		counter values.
+* @param	PmCtrValue: Pointer to an array of type u32 PmCtrValue[6].
+*			It is an output parameter which is used to return the PM
+*			counter values.
 *
 * @return	None.
 *
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xpm_counter.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xpm_counter.h
similarity index 96%
rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xpm_counter.h
rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xpm_counter.h
index af7fac9ea..45f091982 100644
--- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xpm_counter.h
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xpm_counter.h
@@ -34,21 +34,22 @@
 *
 * @file xpm_counter.h
 *
-* This header file contains APIs for configuring and controlling the Cortex-A9
-* Performance Monitor Events.
-* Cortex-A9 Performance Monitor has 6 event counters which can be used to
-* count a variety of events described in Coretx-A9 TRM. This file defines
-* configurations, where value configures the event counters to count a
-* set of events.
+* @addtogroup a9_event_counter_apis Cortex A9 Event Counters Functions
 *
-* Xpm_SetEvents can be used to set the event counters to count a set of events
-* and Xpm_GetEventCounters can be used to read the counter values.
+* Cortex A9 event counter functions can be utilized to configure and control
+* the Cortex-A9 performance monitor events.
+*
+* Cortex-A9 performance monitor has six event counters which can be used to
+* count a variety of events described in Coretx-A9 TRM. xpm_counter.h defines
+* configurations XPM_CNTRCFGx which can be used to program the event counters
+* to count a set of events.
 *
 * @note
-*
-* This file doesn't handle the Cortex-A9 cycle counter, as the cycle counter is
+* It doesn't handle the Cortex-A9 cycle counter, as the cycle counter is
 * being used for time keeping.
 *
+* @{
+*
 * 
 * MODIFICATION HISTORY:
 *
@@ -569,3 +570,6 @@ void Xpm_GetEventCounters(u32 *PmCtrValue);
 #endif
 
 #endif
+/**
+* @} End of "addtogroup a9_event_counter_apis".
+*/
\ No newline at end of file
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xpseudo_asm.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xpseudo_asm.h
similarity index 75%
rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xpseudo_asm.h
rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xpseudo_asm.h
index 29298617c..4ad9e5d73 100644
--- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xpseudo_asm.h
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xpseudo_asm.h
@@ -34,8 +34,21 @@
 *
 * @file xpseudo_asm.h
 *
-* This header file contains macros for using inline assembler code.
+* @addtogroup a9_specific Cortex A9 Processor Specific Include Files
 *
+* The xpseudo_asm.h includes xreg_cortexa9.h and xpseudo_asm_gcc.h.
+*
+* The xreg_cortexa9.h file contains definitions for inline assembler code.
+* It provides inline definitions for Cortex A9 GPRs, SPRs, MPE registers,
+* co-processor registers and Debug registers.
+*
+* The xpseudo_asm_gcc.h contains the definitions for the most often used inline
+* assembler instructions, available as macros. These can be very useful for
+* tasks such as setting or getting special purpose registers, synchronization,
+* or cache manipulation etc. These inline assembler instructions can be used
+* from drivers and user applications written in C.
+*
+* @{
 * 
 * MODIFICATION HISTORY:
 *
@@ -59,3 +72,6 @@
 #endif
 
 #endif /* XPSEUDO_ASM_H */
+/**
+* @} End of "addtogroup a9_specific".
+*/
\ No newline at end of file
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xpseudo_asm_gcc.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xpseudo_asm_gcc.h
similarity index 97%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xpseudo_asm_gcc.h
rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xpseudo_asm_gcc.h
index b475c90e7..1b6726394 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xpseudo_asm_gcc.h
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xpseudo_asm_gcc.h
@@ -71,7 +71,7 @@ extern "C" {
 
 #if defined (__aarch64__)
 /* pseudo assembler instructions */
-#define mfcpsr()	({u32 rval; \
+#define mfcpsr()	({u32 rval = 0U; \
 			   asm volatile("mrs %0,  DAIF" : "=r" (rval));\
 			  rval;\
 			 })
@@ -123,7 +123,7 @@ extern "C" {
 #else
 
 /* pseudo assembler instructions */
-#define mfcpsr()	({u32 rval; \
+#define mfcpsr()	({u32 rval = 0U; \
 			  __asm__ __volatile__(\
 			    "mrs	%0, cpsr\n"\
 			    : "=r" (rval)\
@@ -215,7 +215,7 @@ extern "C" {
 #define mtcptlbi(reg)	__asm__ __volatile__("tlbi " #reg)
 #define mtcpat(reg,val)	__asm__ __volatile__("at " #reg ",%0"  : : "r" (val))
 /* CP15 operations */
-#define mfcp(reg)	({u64 rval;\
+#define mfcp(reg)	({u64 rval = 0U;\
 			__asm__ __volatile__("mrs	%0, " #reg : "=r" (rval));\
 			rval;\
 			})
@@ -229,7 +229,7 @@ extern "C" {
 			 : : "r" (v)\
 			);
 
-#define mfcp(rn)	({u32 rval; \
+#define mfcp(rn)	({u32 rval = 0U; \
 			 __asm__ __volatile__(\
 			   "mrc " rn "\n"\
 			   : "=r" (rval)\
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xreg_cortexa9.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xreg_cortexa9.h
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xreg_cortexa9.h
rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xreg_cortexa9.h
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xstatus.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xstatus.h
new file mode 100644
index 000000000..993747588
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xstatus.h
@@ -0,0 +1,535 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xstatus.h
+*
+* @addtogroup common_status_codes Xilinx® software status codes
+*
+* The xstatus.h file contains the Xilinx® software status codes.These codes are
+* used throughout the Xilinx device drivers.
+*
+* @{
+******************************************************************************/
+
+#ifndef XSTATUS_H		/* prevent circular inclusions */
+#define XSTATUS_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+
+/************************** Constant Definitions *****************************/
+
+/*********************** Common statuses 0 - 500 *****************************/
+/**
+@name Common Status Codes for All Device Drivers
+@{
+*/
+#define XST_SUCCESS                     0L
+#define XST_FAILURE                     1L
+#define XST_DEVICE_NOT_FOUND            2L
+#define XST_DEVICE_BLOCK_NOT_FOUND      3L
+#define XST_INVALID_VERSION             4L
+#define XST_DEVICE_IS_STARTED           5L
+#define XST_DEVICE_IS_STOPPED           6L
+#define XST_FIFO_ERROR                  7L	/*!< An error occurred during an
+						   operation with a FIFO such as
+						   an underrun or overrun, this
+						   error requires the device to
+						   be reset */
+#define XST_RESET_ERROR                 8L	/*!< An error occurred which requires
+						   the device to be reset */
+#define XST_DMA_ERROR                   9L	/*!< A DMA error occurred, this error
+						   typically requires the device
+						   using the DMA to be reset */
+#define XST_NOT_POLLED                  10L	/*!< The device is not configured for
+						   polled mode operation */
+#define XST_FIFO_NO_ROOM                11L	/*!< A FIFO did not have room to put
+						   the specified data into */
+#define XST_BUFFER_TOO_SMALL            12L	/*!< The buffer is not large enough
+						   to hold the expected data */
+#define XST_NO_DATA                     13L	/*!< There was no data available */
+#define XST_REGISTER_ERROR              14L	/*!< A register did not contain the
+						   expected value */
+#define XST_INVALID_PARAM               15L	/*!< An invalid parameter was passed
+						   into the function */
+#define XST_NOT_SGDMA                   16L	/*!< The device is not configured for
+						   scatter-gather DMA operation */
+#define XST_LOOPBACK_ERROR              17L	/*!< A loopback test failed */
+#define XST_NO_CALLBACK                 18L	/*!< A callback has not yet been
+						   registered */
+#define XST_NO_FEATURE                  19L	/*!< Device is not configured with
+						   the requested feature */
+#define XST_NOT_INTERRUPT               20L	/*!< Device is not configured for
+						   interrupt mode operation */
+#define XST_DEVICE_BUSY                 21L	/*!< Device is busy */
+#define XST_ERROR_COUNT_MAX             22L	/*!< The error counters of a device
+						   have maxed out */
+#define XST_IS_STARTED                  23L	/*!< Used when part of device is
+						   already started i.e.
+						   sub channel */
+#define XST_IS_STOPPED                  24L	/*!< Used when part of device is
+						   already stopped i.e.
+						   sub channel */
+#define XST_DATA_LOST                   26L	/*!< Driver defined error */
+#define XST_RECV_ERROR                  27L	/*!< Generic receive error */
+#define XST_SEND_ERROR                  28L	/*!< Generic transmit error */
+#define XST_NOT_ENABLED                 29L	/*!< A requested service is not
+						   available because it has not
+						   been enabled */
+/** @} */
+/***************** Utility Component statuses 401 - 500  *********************/
+/**
+@name Utility Component Status Codes 401 - 500
+@{
+*/
+#define XST_MEMTEST_FAILED              401L	/*!< Memory test failed */
+
+/** @} */
+/***************** Common Components statuses 501 - 1000 *********************/
+/**
+@name Packet Fifo Status Codes 501 - 510
+@{
+*/
+/********************* Packet Fifo statuses 501 - 510 ************************/
+
+#define XST_PFIFO_LACK_OF_DATA          501L	/*!< Not enough data in FIFO   */
+#define XST_PFIFO_NO_ROOM               502L	/*!< Not enough room in FIFO   */
+#define XST_PFIFO_BAD_REG_VALUE         503L	/*!< Self test, a register value
+						   was invalid after reset */
+#define XST_PFIFO_ERROR                 504L	/*!< Generic packet FIFO error */
+#define XST_PFIFO_DEADLOCK              505L	/*!< Packet FIFO is reporting
+						 * empty and full simultaneously
+						 */
+/** @} */
+/**
+@name DMA Status Codes 511 - 530
+@{
+*/
+/************************** DMA statuses 511 - 530 ***************************/
+
+#define XST_DMA_TRANSFER_ERROR          511L	/*!< Self test, DMA transfer
+						   failed */
+#define XST_DMA_RESET_REGISTER_ERROR    512L	/*!< Self test, a register value
+						   was invalid after reset */
+#define XST_DMA_SG_LIST_EMPTY           513L	/*!< Scatter gather list contains
+						   no buffer descriptors ready
+						   to be processed */
+#define XST_DMA_SG_IS_STARTED           514L	/*!< Scatter gather not stopped */
+#define XST_DMA_SG_IS_STOPPED           515L	/*!< Scatter gather not running */
+#define XST_DMA_SG_LIST_FULL            517L	/*!< All the buffer desciptors of
+						   the scatter gather list are
+						   being used */
+#define XST_DMA_SG_BD_LOCKED            518L	/*!< The scatter gather buffer
+						   descriptor which is to be
+						   copied over in the scatter
+						   list is locked */
+#define XST_DMA_SG_NOTHING_TO_COMMIT    519L	/*!< No buffer descriptors have been
+						   put into the scatter gather
+						   list to be commited */
+#define XST_DMA_SG_COUNT_EXCEEDED       521L	/*!< The packet count threshold
+						   specified was larger than the
+						   total # of buffer descriptors
+						   in the scatter gather list */
+#define XST_DMA_SG_LIST_EXISTS          522L	/*!< The scatter gather list has
+						   already been created */
+#define XST_DMA_SG_NO_LIST              523L	/*!< No scatter gather list has
+						   been created */
+#define XST_DMA_SG_BD_NOT_COMMITTED     524L	/*!< The buffer descriptor which was
+						   being started was not committed
+						   to the list */
+#define XST_DMA_SG_NO_DATA              525L	/*!< The buffer descriptor to start
+						   has already been used by the
+						   hardware so it can't be reused
+						 */
+#define XST_DMA_SG_LIST_ERROR           526L	/*!< General purpose list access
+						   error */
+#define XST_DMA_BD_ERROR                527L	/*!< General buffer descriptor
+						   error */
+/** @} */
+/**
+@name IPIF Status Codes Codes 531 - 550
+@{
+*/
+/************************** IPIF statuses 531 - 550 ***************************/
+
+#define XST_IPIF_REG_WIDTH_ERROR        531L	/*!< An invalid register width
+						   was passed into the function */
+#define XST_IPIF_RESET_REGISTER_ERROR   532L	/*!< The value of a register at
+						   reset was not valid */
+#define XST_IPIF_DEVICE_STATUS_ERROR    533L	/*!< A write to the device interrupt
+						   status register did not read
+						   back correctly */
+#define XST_IPIF_DEVICE_ACK_ERROR       534L	/*!< The device interrupt status
+						   register did not reset when
+						   acked */
+#define XST_IPIF_DEVICE_ENABLE_ERROR    535L	/*!< The device interrupt enable
+						   register was not updated when
+						   other registers changed */
+#define XST_IPIF_IP_STATUS_ERROR        536L	/*!< A write to the IP interrupt
+						   status register did not read
+						   back correctly */
+#define XST_IPIF_IP_ACK_ERROR           537L	/*!< The IP interrupt status register
+						   did not reset when acked */
+#define XST_IPIF_IP_ENABLE_ERROR        538L	/*!< IP interrupt enable register was
+						   not updated correctly when other
+						   registers changed */
+#define XST_IPIF_DEVICE_PENDING_ERROR   539L	/*!< The device interrupt pending
+						   register did not indicate the
+						   expected value */
+#define XST_IPIF_DEVICE_ID_ERROR        540L	/*!< The device interrupt ID register
+						   did not indicate the expected
+						   value */
+#define XST_IPIF_ERROR                  541L	/*!< Generic ipif error */
+/** @} */
+
+/****************** Device specific statuses 1001 - 4095 *********************/
+/**
+@name Ethernet Status Codes 1001 - 1050
+@{
+*/
+/********************* Ethernet statuses 1001 - 1050 *************************/
+
+#define XST_EMAC_MEMORY_SIZE_ERROR  1001L	/*!< Memory space is not big enough
+						 * to hold the minimum number of
+						 * buffers or descriptors */
+#define XST_EMAC_MEMORY_ALLOC_ERROR 1002L	/*!< Memory allocation failed */
+#define XST_EMAC_MII_READ_ERROR     1003L	/*!< MII read error */
+#define XST_EMAC_MII_BUSY           1004L	/*!< An MII operation is in progress */
+#define XST_EMAC_OUT_OF_BUFFERS     1005L	/*!< Driver is out of buffers */
+#define XST_EMAC_PARSE_ERROR        1006L	/*!< Invalid driver init string */
+#define XST_EMAC_COLLISION_ERROR    1007L	/*!< Excess deferral or late
+						 * collision on polled send */
+/** @} */
+/**
+@name UART Status Codes 1051 - 1075
+@{
+*/
+/*********************** UART statuses 1051 - 1075 ***************************/
+#define XST_UART
+
+#define XST_UART_INIT_ERROR         1051L
+#define XST_UART_START_ERROR        1052L
+#define XST_UART_CONFIG_ERROR       1053L
+#define XST_UART_TEST_FAIL          1054L
+#define XST_UART_BAUD_ERROR         1055L
+#define XST_UART_BAUD_RANGE         1056L
+
+/** @} */
+/**
+@name IIC Status Codes 1076 - 1100
+@{
+*/
+/************************ IIC statuses 1076 - 1100 ***************************/
+
+#define XST_IIC_SELFTEST_FAILED         1076	/*!< self test failed            */
+#define XST_IIC_BUS_BUSY                1077	/*!< bus found busy              */
+#define XST_IIC_GENERAL_CALL_ADDRESS    1078	/*!< mastersend attempted with   */
+					     /* general call address        */
+#define XST_IIC_STAND_REG_RESET_ERROR   1079	/*!< A non parameterizable reg   */
+					     /* value after reset not valid */
+#define XST_IIC_TX_FIFO_REG_RESET_ERROR 1080	/*!< Tx fifo included in design  */
+					     /* value after reset not valid */
+#define XST_IIC_RX_FIFO_REG_RESET_ERROR 1081	/*!< Rx fifo included in design  */
+					     /* value after reset not valid */
+#define XST_IIC_TBA_REG_RESET_ERROR     1082	/*!< 10 bit addr incl in design  */
+					     /* value after reset not valid */
+#define XST_IIC_CR_READBACK_ERROR       1083	/*!< Read of the control register */
+					     /* didn't return value written */
+#define XST_IIC_DTR_READBACK_ERROR      1084	/*!< Read of the data Tx reg     */
+					     /* didn't return value written */
+#define XST_IIC_DRR_READBACK_ERROR      1085	/*!< Read of the data Receive reg */
+					     /* didn't return value written */
+#define XST_IIC_ADR_READBACK_ERROR      1086	/*!< Read of the data Tx reg     */
+					     /* didn't return value written */
+#define XST_IIC_TBA_READBACK_ERROR      1087	/*!< Read of the 10 bit addr reg */
+					     /* didn't return written value */
+#define XST_IIC_NOT_SLAVE               1088	/*!< The device isn't a slave    */
+/** @} */
+/**
+@name ATMC Status Codes 1101 - 1125
+@{
+*/
+/*********************** ATMC statuses 1101 - 1125 ***************************/
+
+#define XST_ATMC_ERROR_COUNT_MAX    1101L	/*!< the error counters in the ATM
+						   controller hit the max value
+						   which requires the statistics
+						   to be cleared */
+/** @} */
+/**
+@name Flash Status Codes 1126 - 1150
+@{
+*/
+/*********************** Flash statuses 1126 - 1150 **************************/
+
+#define XST_FLASH_BUSY                1126L	/*!< Flash is erasing or programming
+						 */
+#define XST_FLASH_READY               1127L	/*!< Flash is ready for commands */
+#define XST_FLASH_ERROR               1128L	/*!< Flash had detected an internal
+						   error. Use XFlash_DeviceControl
+						   to retrieve device specific codes
+						 */
+#define XST_FLASH_ERASE_SUSPENDED     1129L	/*!< Flash is in suspended erase state
+						 */
+#define XST_FLASH_WRITE_SUSPENDED     1130L	/*!< Flash is in suspended write state
+						 */
+#define XST_FLASH_PART_NOT_SUPPORTED  1131L	/*!< Flash type not supported by
+						   driver */
+#define XST_FLASH_NOT_SUPPORTED       1132L	/*!< Operation not supported */
+#define XST_FLASH_TOO_MANY_REGIONS    1133L	/*!< Too many erase regions */
+#define XST_FLASH_TIMEOUT_ERROR       1134L	/*!< Programming or erase operation
+						   aborted due to a timeout */
+#define XST_FLASH_ADDRESS_ERROR       1135L	/*!< Accessed flash outside its
+						   addressible range */
+#define XST_FLASH_ALIGNMENT_ERROR     1136L	/*!< Write alignment error */
+#define XST_FLASH_BLOCKING_CALL_ERROR 1137L	/*!< Couldn't return immediately from
+						   write/erase function with
+						   XFL_NON_BLOCKING_WRITE/ERASE
+						   option cleared */
+#define XST_FLASH_CFI_QUERY_ERROR     1138L	/*!< Failed to query the device */
+/** @} */
+/**
+@name SPI Status Codes 1151 - 1175
+@{
+*/
+/*********************** SPI statuses 1151 - 1175 ****************************/
+
+#define XST_SPI_MODE_FAULT          1151	/*!< master was selected as slave */
+#define XST_SPI_TRANSFER_DONE       1152	/*!< data transfer is complete */
+#define XST_SPI_TRANSMIT_UNDERRUN   1153	/*!< slave underruns transmit register */
+#define XST_SPI_RECEIVE_OVERRUN     1154	/*!< device overruns receive register */
+#define XST_SPI_NO_SLAVE            1155	/*!< no slave has been selected yet */
+#define XST_SPI_TOO_MANY_SLAVES     1156	/*!< more than one slave is being
+						 * selected */
+#define XST_SPI_NOT_MASTER          1157	/*!< operation is valid only as master */
+#define XST_SPI_SLAVE_ONLY          1158	/*!< device is configured as slave-only
+						 */
+#define XST_SPI_SLAVE_MODE_FAULT    1159	/*!< slave was selected while disabled */
+#define XST_SPI_SLAVE_MODE          1160	/*!< device has been addressed as slave */
+#define XST_SPI_RECEIVE_NOT_EMPTY   1161	/*!< device received data in slave mode */
+
+#define XST_SPI_COMMAND_ERROR       1162	/*!< unrecognised command - qspi only */
+#define XST_SPI_POLL_DONE           1163        /*!< controller completed polling the
+						   device for status */
+/** @} */
+/**
+@name OPB Arbiter Status Codes 1176 - 1200
+@{
+*/
+/********************** OPB Arbiter statuses 1176 - 1200 *********************/
+
+#define XST_OPBARB_INVALID_PRIORITY  1176	/*!< the priority registers have either
+						 * one master assigned to two or more
+						 * priorities, or one master not
+						 * assigned to any priority
+						 */
+#define XST_OPBARB_NOT_SUSPENDED     1177	/*!< an attempt was made to modify the
+						 * priority levels without first
+						 * suspending the use of priority
+						 * levels
+						 */
+#define XST_OPBARB_PARK_NOT_ENABLED  1178	/*!< bus parking by id was enabled but
+						 * bus parking was not enabled
+						 */
+#define XST_OPBARB_NOT_FIXED_PRIORITY 1179	/*!< the arbiter must be in fixed
+						 * priority mode to allow the
+						 * priorities to be changed
+						 */
+/** @} */
+/**
+@name INTC Status Codes 1201 - 1225
+@{
+*/
+/************************ Intc statuses 1201 - 1225 **************************/
+
+#define XST_INTC_FAIL_SELFTEST      1201	/*!< self test failed */
+#define XST_INTC_CONNECT_ERROR      1202	/*!< interrupt already in use */
+/** @} */
+/**
+@name TmrCtr Status Codes 1226 - 1250
+@{
+*/
+/********************** TmrCtr statuses 1226 - 1250 **************************/
+
+#define XST_TMRCTR_TIMER_FAILED     1226	/*!< self test failed */
+/** @} */
+/**
+@name WdtTb Status Codes 1251 - 1275
+@{
+*/
+/********************** WdtTb statuses 1251 - 1275 ***************************/
+
+#define XST_WDTTB_TIMER_FAILED      1251L
+/** @} */
+/**
+@name PlbArb status Codes 1276 - 1300
+@{
+*/
+/********************** PlbArb statuses 1276 - 1300 **************************/
+
+#define XST_PLBARB_FAIL_SELFTEST    1276L
+/** @} */
+/**
+@name Plb2Opb Status Codes 1301 - 1325
+@{
+*/
+/********************** Plb2Opb statuses 1301 - 1325 *************************/
+
+#define XST_PLB2OPB_FAIL_SELFTEST   1301L
+/** @} */
+/**
+@name Opb2Plb Status 1326 - 1350
+@{
+*/
+/********************** Opb2Plb statuses 1326 - 1350 *************************/
+
+#define XST_OPB2PLB_FAIL_SELFTEST   1326L
+/** @} */
+/**
+@name SysAce Status Codes 1351 - 1360
+@{
+*/
+/********************** SysAce statuses 1351 - 1360 **************************/
+
+#define XST_SYSACE_NO_LOCK          1351L	/*!< No MPU lock has been granted */
+/** @} */
+/**
+@name PCI Bridge Status Codes 1361 - 1375
+@{
+*/
+/********************** PCI Bridge statuses 1361 - 1375 **********************/
+
+#define XST_PCI_INVALID_ADDRESS     1361L
+/** @} */
+/**
+@name FlexRay Constants 1400 - 1409
+@{
+*/
+/********************** FlexRay constants 1400 - 1409 *************************/
+
+#define XST_FR_TX_ERROR			1400
+#define XST_FR_TX_BUSY			1401
+#define XST_FR_BUF_LOCKED		1402
+#define XST_FR_NO_BUF			1403
+/** @} */
+/**
+@name USB constants 1410 - 1420
+@{
+*/
+/****************** USB constants 1410 - 1420  *******************************/
+
+#define XST_USB_ALREADY_CONFIGURED	1410
+#define XST_USB_BUF_ALIGN_ERROR		1411
+#define XST_USB_NO_DESC_AVAILABLE	1412
+#define XST_USB_BUF_TOO_BIG		1413
+#define XST_USB_NO_BUF			1414
+/** @} */
+/**
+@name HWICAP constants 1421 - 1429
+@{
+*/
+/****************** HWICAP constants 1421 - 1429  *****************************/
+
+#define XST_HWICAP_WRITE_DONE		1421
+
+/** @} */
+/**
+@name AXI VDMA constants 1430 - 1440
+@{
+*/
+/****************** AXI VDMA constants 1430 - 1440  *****************************/
+
+#define XST_VDMA_MISMATCH_ERROR		1430
+/** @} */
+/**
+@name NAND Flash Status Codes 1441 - 1459
+@{
+*/
+/*********************** NAND Flash statuses 1441 - 1459  *********************/
+
+#define XST_NAND_BUSY			1441L	/*!< Flash is erasing or
+						 * programming
+						 */
+#define XST_NAND_READY			1442L	/*!< Flash is ready for commands
+						 */
+#define XST_NAND_ERROR			1443L	/*!< Flash had detected an
+						 * internal error.
+						 */
+#define XST_NAND_PART_NOT_SUPPORTED	1444L	/*!< Flash type not supported by
+						 * driver
+						 */
+#define XST_NAND_OPT_NOT_SUPPORTED	1445L	/*!< Operation not supported
+						 */
+#define XST_NAND_TIMEOUT_ERROR		1446L	/*!< Programming or erase
+						 * operation aborted due to a
+						 * timeout
+						 */
+#define XST_NAND_ADDRESS_ERROR		1447L	/*!< Accessed flash outside its
+						 * addressible range
+						 */
+#define XST_NAND_ALIGNMENT_ERROR	1448L	/*!< Write alignment error
+						 */
+#define XST_NAND_PARAM_PAGE_ERROR	1449L	/*!< Failed to read parameter
+						 * page of the device
+						 */
+#define XST_NAND_CACHE_ERROR		1450L	/*!< Flash page buffer error
+						 */
+
+#define XST_NAND_WRITE_PROTECTED	1451L	/*!< Flash is write protected
+						 */
+/** @} */
+
+/**************************** Type Definitions *******************************/
+
+typedef s32 XStatus;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_status_codes".
+*/
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xtime_l.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xtime_l.c
similarity index 88%
rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xtime_l.c
rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xtime_l.c
index d24f41d1a..e81643f90 100644
--- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xtime_l.c
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xtime_l.c
@@ -66,16 +66,18 @@
 
 /************************** Function Prototypes ******************************/
 
-/****************************************************************************
+/****************************************************************************/
+/**
+* @brief	Set the time in the Global Timer Counter Register.
 *
-* Set the time in the Global Timer Counter Register.
-*
-* @param	Value to be written to the Global Timer Counter Register.
+* @param	Xtime_Global: 64-bit Value to be written to the Global Timer
+*			Counter Register.
 *
 * @return	None.
 *
-* @note		In multiprocessor environment reference time will reset/lost for
-*		all processors, when this function called by any one processor.
+* @note		When this function is called by any one processor in a multi-
+*			processor environment, reference time will reset/lost for all
+*			processors.
 *
 ****************************************************************************/
 void XTime_SetTime(XTime Xtime_Global)
@@ -92,11 +94,12 @@ void XTime_SetTime(XTime Xtime_Global)
 	Xil_Out32((u32)GLOBAL_TMR_BASEADDR + (u32)GTIMER_CONTROL_OFFSET, (u32)0x1);
 }
 
-/****************************************************************************
+/****************************************************************************/
+/**
+* @brief	Get the time from the Global Timer Counter Register.
 *
-* Get the time from the Global Timer Counter Register.
-*
-* @param	Pointer to the location to be updated with the time.
+* @param	Xtime_Global: Pointer to the 64-bit location which will be
+*			updated with the current timer value.
 *
 * @return	None.
 *
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xtime_l.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xtime_l.h
similarity index 83%
rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xtime_l.h
rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xtime_l.h
index e5f43b846..9b872b6cb 100644
--- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xtime_l.h
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v6_6/src/xtime_l.h
@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2009 - 2017 Xilinx, Inc.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
@@ -32,7 +32,13 @@
 /*****************************************************************************/
 /**
 * @file xtime_l.h
+* @addtogroup a9_time_apis Cortex A9 Time Functions
 *
+* xtime_l.h provides access to the 64-bit Global Counter in the PMU. This
+* counter increases by one at every two processor cycles. These functions can
+* be used to get/set time in the global timer.
+*
+* @{
 * 
 * MODIFICATION HISTORY:
 *
@@ -42,10 +48,10 @@
 * 3.06a sgd    05/15/12 Upadted get/set time functions to make use Global Timer
 * 3.06a asa    06/17/12 Reverted back the changes to make use Global Timer.
 * 3.07a sgd    07/05/12 Upadted get/set time functions to make use Global Timer
+* 6.6   srm    10/23/17 Updated the macros to support user configurable sleep
+*						implementation
 * 

 *
-* @note		None.
-*
 ******************************************************************************/
 
 #ifndef XTIME_H /* prevent circular inclusions */
@@ -72,9 +78,16 @@ typedef u64 XTime;
 #define GTIMER_COUNTER_UPPER_OFFSET       0x04U
 #define GTIMER_CONTROL_OFFSET             0x08U
 
-
+#if defined (SLEEP_TIMER_BASEADDR)
+#define COUNTS_PER_SECOND          (SLEEP_TIMER_FREQUENCY)
+#else
 /* Global Timer is always clocked at half of the CPU frequency */
 #define COUNTS_PER_SECOND          (XPAR_CPU_CORTEXA9_CORE_CLOCK_FREQ_HZ /2)
+#endif
+
+#if defined (XSLEEP_TIMER_IS_DEFAULT_TIMER)
+#pragma message ("For the sleep routines, Global timer is being used")
+#endif
 /************************** Variable Definitions *****************************/
 
 /************************** Function Prototypes ******************************/
@@ -87,3 +100,6 @@ void XTime_GetTime(XTime *Xtime_Global);
 #endif /* __cplusplus */
 
 #endif /* XTIME_H */
+/**
+* @} End of "addtogroup a9_time_apis".
+*/
\ No newline at end of file
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_1/src/Makefile b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_5/src/Makefile
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_1/src/Makefile
rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_5/src/Makefile
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_2/src/xttcps.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_5/src/xttcps.c
similarity index 95%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_2/src/xttcps.c
rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_5/src/xttcps.c
index 394262868..b2382f1b2 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_2/src/xttcps.c
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_5/src/xttcps.c
@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2010 - 2017 Xilinx, Inc.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
@@ -33,7 +33,7 @@
 /**
 *
 * @file xttcps.c
-* @addtogroup ttcps_v3_0
+* @addtogroup ttcps_v3_5
 * @{
 *
 * This file contains the implementation of the XTtcPs driver. This driver
@@ -52,7 +52,10 @@
 *						to stop the timer before configuring
 * 3.2   mus    10/28/16 Modified XTtcPs_CalcIntervalFromFreq to calculate
 *                       32 bit interval count for zynq ultrascale+mpsoc
-*
+* 3.5   srm    10/06/17 Updated XTtcPs_GetMatchValue and XTtcPs_SetMatchValue
+*                       APIs to use correct match register width for zynq
+*                       (i.e. 16 bit) and zynq ultrascale+mpsoc (i.e. 32 bit).
+*                       It fixes CR# 986617
 * 

 *
 ******************************************************************************/
@@ -196,7 +199,7 @@ s32 XTtcPs_CfgInitialize(XTtcPs *InstancePtr, XTtcPs_Config *ConfigPtr,
 * @note		None
 *
 ****************************************************************************/
-void XTtcPs_SetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex, u16 Value)
+void XTtcPs_SetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex, XMatchRegValue Value)
 {
 	/*
 	 * Assert to validate input arguments.
@@ -222,12 +225,12 @@ void XTtcPs_SetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex, u16 Value)
 * @param	MatchIndex is the index to the match register to be set.
 *		Valid values are 0, 1, or 2.
 *
-* @return	None
+* @return	The match register value
 *
 * @note		None
 *
 ****************************************************************************/
-u16 XTtcPs_GetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex)
+XMatchRegValue XTtcPs_GetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex)
 {
 	u32 MatchReg;
 
@@ -241,7 +244,7 @@ u16 XTtcPs_GetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex)
 	MatchReg = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress,
 			    XTtcPs_Match_N_Offset(MatchIndex));
 
-	return (u16) MatchReg;
+	return (XMatchRegValue) MatchReg;
 }
 
 /*****************************************************************************/
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_5/src/xttcps.h
similarity index 93%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps.h
rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_5/src/xttcps.h
index be266d9b3..b7b4e1950 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps.h
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_5/src/xttcps.h
@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2010 - 2017 Xilinx, Inc.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
@@ -33,7 +33,7 @@
 /**
 *
 * @file xttcps.h
-* @addtogroup ttcps_v3_0
+* @addtogroup ttcps_v3_5
 * @{
 * @details
 *
@@ -93,6 +93,16 @@
 *			modified for MISRA-C:2012 compliance.
 * 3.2   mus    10/28/16 Modified XTtcPs_GetCounterValue and XTtcPs_SetInterval
 *                       macros to return 32 bit values for zynq ultrascale+mpsoc
+*       ms   01/23/17 Modified xil_printf statement in main function for all
+*                     examples to ensure that "Successfully ran" and "Failed"
+*                     strings are available in all examples. This is a fix
+*                     for CR-965028.
+*       ms   03/17/17 Added readme.txt file in examples folder for doxygen
+*                     generation.
+* 3.4   ms   04/18/17 Modified tcl file to add suffix U for all macros
+*                     definitions of ttcps in xparameters.h
+* 3.5   srm  10/06/17 Added new typedef XMatchRegValue for match register width
+*
 * 

 *
 ******************************************************************************/
@@ -110,12 +120,7 @@ extern "C" {
 #include "xstatus.h"
 
 /************************** Constant Definitions *****************************/
-/*
- * Flag for a9 processor
- */
- #if !defined (ARMR5) && !defined (__aarch64__) && !defined (ARMA53_32)
- #define ARMA9
- #endif
+
 
 /*
  * Maximum Value for interval counter
@@ -165,12 +170,14 @@ typedef struct {
 } XTtcPs;
 
 /**
- * This typedef contains interval count
+ * This typedef contains interval count and Match register value
  */
 #if defined(ARMA9)
 typedef u16 XInterval;
+typedef u16 XMatchRegValue;
 #else
 typedef u32 XInterval;
+typedef u32 XMatchRegValue;
 #endif
 /***************** Macros (Inline Functions) Definitions *********************/
 
@@ -279,7 +286,7 @@ typedef u32 XInterval;
 * @return	None
 *
 * @note		C-style signature:
-*		void XTtcPs_SetInterval(XTtcPs *InstancePtr, u16 Value)
+*		void XTtcPs_SetInterval(XTtcPs *InstancePtr, XInterval Value)
 *
 ****************************************************************************/
 #define XTtcPs_SetInterval(InstancePtr, Value)	\
@@ -432,8 +439,8 @@ XTtcPs_Config *XTtcPs_LookupConfig(u16 DeviceId);
 s32 XTtcPs_CfgInitialize(XTtcPs *InstancePtr,
          XTtcPs_Config * ConfigPtr, u32 EffectiveAddr);
 
-void XTtcPs_SetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex, u16 Value);
-u16 XTtcPs_GetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex);
+void XTtcPs_SetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex, XMatchRegValue Value);
+XMatchRegValue XTtcPs_GetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex);
 
 void XTtcPs_SetPrescaler(XTtcPs *InstancePtr, u8 PrescalerValue);
 u8 XTtcPs_GetPrescaler(XTtcPs *InstancePtr);
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_1/src/xttcps_g.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_5/src/xttcps_g.c
similarity index 94%
rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_1/src/xttcps_g.c
rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_5/src/xttcps_g.c
index 2729f41f5..f88e5efbb 100644
--- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_1/src/xttcps_g.c
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_5/src/xttcps_g.c
@@ -5,7 +5,7 @@
 * Version: 
 * DO NOT EDIT.
 *
-* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.*
+* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
 *Permission is hereby granted, free of charge, to any person obtaining a copy
 *of this software and associated documentation files (the Software), to deal
 *in the Software without restriction, including without limitation the rights
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps_hw.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_5/src/xttcps_hw.h
similarity index 90%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps_hw.h
rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_5/src/xttcps_hw.h
index af78bcd67..b1fa545bd 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps_hw.h
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_5/src/xttcps_hw.h
@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2010 - 2017 Xilinx, Inc.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
@@ -33,7 +33,7 @@
 /**
 *
 * @file xttcps_hw.h
-* @addtogroup ttcps_v3_0
+* @addtogroup ttcps_v3_5
 * @{
 *
 * This file defines the hardware interface to one of the three timer counters
@@ -47,7 +47,10 @@
 * ----- ------ -------- -------------------------------------------------
 * 1.00a drg/jz 01/21/10 First release
 * 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
-*
+* 3.5   srm    10/06/17 Updated XTTCPS_COUNT_VALUE_MASK,
+*                       XTTCPS_INTERVAL_VAL_MASK, XTTCPS_MATCH_MASK macros to
+*                       mask 16 bit values for zynq and 32 bit values for
+*                       zynq ultrascale+mpsoc "
 * 

 *
 ******************************************************************************/
@@ -66,6 +69,12 @@ extern "C" {
 #include "xil_io.h"
 
 /************************** Constant Definitions *****************************/
+/*
+ * Flag for a9 processor
+ */
+ #if !defined (ARMR5) && !defined (__aarch64__) && !defined (ARMA53_32)
+ #define ARMA9
+ #endif
 
 /** @name Register Map
  *
@@ -114,7 +123,11 @@ extern "C" {
  * Current Counter Value Register definitions
  * @{
  */
+#if defined(ARMA9)
 #define XTTCPS_COUNT_VALUE_MASK		0x0000FFFFU /**< 16-bit counter value */
+#else
+#define XTTCPS_COUNT_VALUE_MASK		0xFFFFFFFFU /**< 32-bit counter value */
+#endif
 /* @} */
 
 /** @name Interval Value Register
@@ -122,7 +135,11 @@ extern "C" {
  * down to.
  * @{
  */
+#if defined(ARMA9)
 #define XTTCPS_INTERVAL_VAL_MASK	0x0000FFFFU /**< 16-bit Interval value*/
+#else
+#define XTTCPS_INTERVAL_VAL_MASK	0xFFFFFFFFU /**< 32-bit Interval value*/
+#endif
 /* @} */
 
 /** @name Match Registers
@@ -130,7 +147,11 @@ extern "C" {
  * registers.
  * @{
  */
+#if defined(ARMA9)
 #define XTTCPS_MATCH_MASK		0x0000FFFFU /**< 16-bit Match value */
+#else
+#define XTTCPS_MATCH_MASK		0xFFFFFFFFU /**< 32-bit Match value */
+#endif
 #define XTTCPS_NUM_MATCH_REG			 3U /**< Num of Match reg */
 /* @} */
 
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps_options.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_5/src/xttcps_options.c
similarity index 99%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps_options.c
rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_5/src/xttcps_options.c
index 532b235c5..01dd9efb3 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps_options.c
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_5/src/xttcps_options.c
@@ -33,7 +33,7 @@
 /**
 *
 * @file xttcps_options.c
-* @addtogroup ttcps_v3_0
+* @addtogroup ttcps_v3_5
 * @{
 *
 * This file contains functions to get or set option features for the device.
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps_selftest.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_5/src/xttcps_selftest.c
similarity index 99%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps_selftest.c
rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_5/src/xttcps_selftest.c
index 4923df667..b1dd7d0a2 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps_selftest.c
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_5/src/xttcps_selftest.c
@@ -33,7 +33,7 @@
 /**
 *
 * @file xttcps_selftest.c
-* @addtogroup ttcps_v3_0
+* @addtogroup ttcps_v3_5
 * @{
 *
 * This file contains the implementation of self test function for the
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_1/src/xttcps_sinit.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_5/src/xttcps_sinit.c
similarity index 99%
rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_1/src/xttcps_sinit.c
rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_5/src/xttcps_sinit.c
index ef3c6ea6b..4684c8a9c 100644
--- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_1/src/xttcps_sinit.c
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_5/src/xttcps_sinit.c
@@ -33,7 +33,7 @@
 /**
 *
 * @file xttcps_sinit.c
-* @addtogroup ttcps_v3_0
+* @addtogroup ttcps_v3_5
 * @{
 *
 * The implementation of the XTtcPs driver's static initialization functionality.
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v3_1/src/Makefile b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/Makefile
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v3_1/src/Makefile
rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/Makefile
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps.c
similarity index 99%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps.c
rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps.c
index a338d1f09..c33ec5481 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps.c
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps.c
@@ -33,7 +33,7 @@
 /**
 *
 * @file xuartps.c
-* @addtogroup uartps_v3_1
+* @addtogroup uartps_v3_5
 * @{
 *
 * This file contains the implementation of the interface functions for XUartPs
@@ -49,6 +49,7 @@
 *                       baud rate. CR# 804281.
 * 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
 * 3.1	kvn    04/10/15 Modified code for latest RTL changes.
+* 3.5	NK     09/26/17 Fix the RX Buffer Overflow issue.
 * 

 *
 *****************************************************************************/
@@ -463,7 +464,7 @@ u32 XUartPs_ReceiveBuffer(XUartPs *InstancePtr)
 	 * Loop until there is no more data in RX FIFO or the specified
 	 * number of bytes has been received
 	 */
-	while((ReceivedCount <= InstancePtr->ReceiveBuffer.RemainingBytes)&&
+	while((ReceivedCount < InstancePtr->ReceiveBuffer.RemainingBytes)&&
 		(((CsrRegister & XUARTPS_SR_RXEMPTY) == (u32)0))){
 
 		if (InstancePtr->is_rxbs_error) {
@@ -635,7 +636,7 @@ s32 XUartPs_SetBaudRate(XUartPs *InstancePtr, u32 BaudRate)
 static void XUartPs_StubHandler(void *CallBackRef, u32 Event,
 				 u32 ByteCount)
 {
-	(void *) CallBackRef;
+	(void) CallBackRef;
 	(void) Event;
 	(void) ByteCount;
 	/* Assert occurs always since this is a stub and should never be called */
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_3/src/xuartps.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps.h
similarity index 96%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_3/src/xuartps.h
rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps.h
index d915917bb..33758c23b 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_3/src/xuartps.h
+++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps.h
@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2010 - 2017 Xilinx, Inc.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
@@ -33,7 +33,7 @@
 /**
 *
 * @file xuartps.h
-* @addtogroup uartps_v3_1
+* @addtogroup uartps_v3_5
 * @{
 * @details
 *
@@ -162,6 +162,14 @@
 * 3.1   adk   14/03/16  Include interrupt examples in the peripheral test when
 *			uart is connected to a valid interrupt controller CR#946803.
 * 3.2   rk     07/20/16 Modified the logic for transmission break bit set
+* 3.4   ms     01/23/17 Added xil_printf statement in main function for all
+*                       examples to ensure that "Successfully ran" and "Failed"
+*                       strings are available in all examples. This is a fix
+*                       for CR-965028.
+*       ms     03/17/17 Added readme.txt file in examples folder for doxygen
+*                       generation.
+* 3.6   ms     02/16/18 Updates the flow control mode offset value in modem
+*                       control register.
 *
 *
* diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v3_1/src/xuartps_g.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_g.c similarity index 91% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v3_1/src/xuartps_g.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_g.c index d0ed617c4..295662046 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v3_1/src/xuartps_g.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_g.c @@ -5,7 +5,7 @@ * Version: * DO NOT EDIT. * -* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.* +* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.* *Permission is hereby granted, free of charge, to any person obtaining a copy *of this software and associated documentation files (the Software), to deal *in the Software without restriction, including without limitation the rights @@ -44,7 +44,7 @@ * The configuration table for devices */ -XUartPs_Config XUartPs_ConfigTable[] = +XUartPs_Config XUartPs_ConfigTable[XPAR_XUARTPS_NUM_INSTANCES] = { { XPAR_PS7_UART_1_DEVICE_ID, diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_3/src/xuartps_hw.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_hw.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_3/src/xuartps_hw.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_hw.c index 299dd35ae..724c3cb40 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_3/src/xuartps_hw.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_hw.c @@ -33,7 +33,7 @@ /** * * @file xuartps_hw.c -* @addtogroup uartps_v3_1 +* @addtogroup uartps_v3_5 * @{ * * diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_hw.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_hw.h similarity index 98% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_hw.h rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_hw.h index 9f5f0b700..9a2bc4305 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/xuartps_hw.h +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_hw.h @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -33,7 +33,7 @@ /** * * @file xuartps_hw.h -* @addtogroup uartps_v3_1 +* @addtogroup uartps_v3_5 * @{ * * This header file contains the hardware interface of an XUartPs device. @@ -55,6 +55,8 @@ * constant definitions. * 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance. * 3.1 kvn 04/10/15 Modified code for latest RTL changes. +* 3.6 ms 02/16/18 Updates flow control mode offset value in +* modem control register. * * * @@ -256,7 +258,7 @@ extern "C" { * * @{ */ -#define XUARTPS_MODEMCR_FCM 0x00000010U /**< Flow control mode */ +#define XUARTPS_MODEMCR_FCM 0x00000020U /**< Flow control mode */ #define XUARTPS_MODEMCR_RTS 0x00000002U /**< Request to send */ #define XUARTPS_MODEMCR_DTR 0x00000001U /**< Data terminal ready */ /* @} */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_3/src/xuartps_intr.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_intr.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_3/src/xuartps_intr.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_intr.c index 3068ee795..dff02fd63 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_3/src/xuartps_intr.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_intr.c @@ -33,7 +33,7 @@ /** * * @file xuartps_intr.c -* @addtogroup uartps_v3_1 +* @addtogroup uartps_v3_5 * @{ * * This file contains the functions for interrupt handling diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_3/src/xuartps_options.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_options.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_3/src/xuartps_options.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_options.c index 9a699afa1..5d8d3017c 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_3/src/xuartps_options.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_options.c @@ -33,7 +33,7 @@ /** * * @file xuartps_options.c -* @addtogroup uartps_v3_1 +* @addtogroup uartps_v3_5 * @{ * * The implementation of the options functions for the XUartPs driver. diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v3_1/src/xuartps_selftest.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_selftest.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v3_1/src/xuartps_selftest.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_selftest.c index a1a7dd366..de58201a1 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v3_1/src/xuartps_selftest.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_selftest.c @@ -33,7 +33,7 @@ /** * * @file xuartps_selftest.c -* @addtogroup uartps_v3_1 +* @addtogroup uartps_v3_5 * @{ * * This file contains the self-test functions for the XUartPs driver. diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_3/src/xuartps_sinit.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_sinit.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_3/src/xuartps_sinit.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_sinit.c index 8dc87dae3..22e2f7a83 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_3/src/xuartps_sinit.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v3_6/src/xuartps_sinit.c @@ -33,7 +33,7 @@ /** * * @file xuartps_sinit.c -* @addtogroup uartps_v3_1 +* @addtogroup uartps_v3_5 * @{ * * The implementation of the XUartPs driver's static initialzation diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_3/src/Makefile b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/Makefile similarity index 100% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_3/src/Makefile rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/Makefile diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_3/src/xusbps.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_3/src/xusbps.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps.c index 897c09497..b76c94a46 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_3/src/xusbps.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps.c @@ -32,7 +32,7 @@ /******************************************************************************/ /** * @file xusbps.c -* @addtogroup usbps_v2_2 +* @addtogroup usbps_v2_4 * @{ * * The XUsbPs driver. Functions in this file are the minimum required diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_3/src/xusbps.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps.h similarity index 98% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_3/src/xusbps.h rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps.h index 4b5d0d47d..b5c472ef9 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_3/src/xusbps.h +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps.h @@ -33,7 +33,7 @@ /** * * @file xusbps.h -* @addtogroup usbps_v2_2 +* @addtogroup usbps_v2_4 * @{ * @details * @@ -182,6 +182,11 @@ * 2.3 kpc 02/19/14 Fixed CR#873972, CR#873974. Corrected the logic for proper * moving of dTD Head/Tail Pointers. Invalidate the cache * after buffer receive in Endpoint Buffer Handler. + * 2.4 sg 04/26/16 Fixed CR#949693, Corrected the logic for EP flush + * ms 03/17/17 Added readme.txt file in examples folder for doxygen + * generation. + * ms 04/10/17 Modified filename tag to include the file in doxygen + * examples. * * ******************************************************************************/ @@ -801,8 +806,8 @@ typedef struct { ******************************************************************************/ #define XUsbPs_EpFlush(InstancePtr, EpNum, Dir) \ XUsbPs_SetBits(InstancePtr, XUSBPS_EPFLUSH_OFFSET, \ - EpNum << ((Dir) & XUSBPS_EP_DIRECTION_OUT ? \ - XUSBPS_EPFLUSH_RX_SHIFT:XUSBPS_EPFLUSH_TX_SHIFT)) \ + 1 << (EpNum + ((Dir) & XUSBPS_EP_DIRECTION_OUT ? \ + XUSBPS_EPFLUSH_RX_SHIFT:XUSBPS_EPFLUSH_TX_SHIFT))) \ /*****************************************************************************/ /** diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_3/src/xusbps_endpoint.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_endpoint.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_3/src/xusbps_endpoint.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_endpoint.c index f93c4b800..7b16d22b5 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_3/src/xusbps_endpoint.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_endpoint.c @@ -32,7 +32,7 @@ /******************************************************************************/ /** * @file xusbps_endpoint.c -* @addtogroup usbps_v2_2 +* @addtogroup usbps_v2_4 * @{ * * Endpoint specific function implementations. diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_3/src/xusbps_endpoint.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_endpoint.h similarity index 99% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_3/src/xusbps_endpoint.h rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_endpoint.h index b8b9ad685..1cb0cfcd3 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_3/src/xusbps_endpoint.h +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_endpoint.h @@ -33,7 +33,7 @@ /** * * @file xusbps_endpoint.h -* @addtogroup usbps_v2_2 +* @addtogroup usbps_v2_4 * @{ * * This is an internal file containung the definitions for endpoints. It is diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_3/src/xusbps_g.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_g.c similarity index 91% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_3/src/xusbps_g.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_g.c index a2486d88e..9f20ba868 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_3/src/xusbps_g.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_g.c @@ -5,7 +5,7 @@ * Version: * DO NOT EDIT. * -* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.* +* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.* *Permission is hereby granted, free of charge, to any person obtaining a copy *of this software and associated documentation files (the Software), to deal *in the Software without restriction, including without limitation the rights @@ -44,7 +44,7 @@ * The configuration table for devices */ -XUsbPs_Config XUsbPs_ConfigTable[] = +XUsbPs_Config XUsbPs_ConfigTable[XPAR_XUSBPS_NUM_INSTANCES] = { { XPAR_PS7_USB_0_DEVICE_ID, diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_3/src/xusbps_hw.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_hw.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_3/src/xusbps_hw.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_hw.c index 105ad9321..04963b288 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_3/src/xusbps_hw.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_hw.c @@ -33,7 +33,7 @@ /** * * @file xusbps_hw.c -* @addtogroup usbps_v2_2 +* @addtogroup usbps_v2_4 * @{ * * The implementation of the XUsbPs interface reset functionality diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_3/src/xusbps_hw.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_hw.h similarity index 99% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_3/src/xusbps_hw.h rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_hw.h index 792fbdde5..69f3ebffb 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_3/src/xusbps_hw.h +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_hw.h @@ -33,7 +33,7 @@ /** * * @file xusbps_hw.h -* @addtogroup usbps_v2_2 +* @addtogroup usbps_v2_4 * @{ * * This header file contains identifiers and low-level driver functions (or diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_3/src/xusbps_intr.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_intr.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_3/src/xusbps_intr.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_intr.c index 94fd3dee6..83463bdfe 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_3/src/xusbps_intr.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_intr.c @@ -32,7 +32,7 @@ /******************************************************************************/ /** * @file xusbps_intr.c -* @addtogroup usbps_v2_2 +* @addtogroup usbps_v2_4 * @{ * * This file contains the functions that are related to interrupt processing diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_3/src/xusbps_sinit.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_sinit.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_3/src/xusbps_sinit.c rename to FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_sinit.c index 1da441db5..a2070a76e 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_3/src/xusbps_sinit.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/usbps_v2_4/src/xusbps_sinit.c @@ -33,7 +33,7 @@ /** * * @file xusbps_sinit.c -* @addtogroup usbps_v2_2 +* @addtogroup usbps_v2_4 * @{ * * The implementation of the XUsbPs driver's static initialzation diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps.h b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps.h index 489a1ee86..549bfff29 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps.h +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps.h @@ -170,7 +170,15 @@ * xadcps.c to fix CR #807563. * 2.2 bss 04/27/14 Modified to use correct Device Config base address in * xadcps.c (CR#854437). -* +* ms 01/23/17 Added xil_printf statement in main function for all +* examples to ensure that "Successfully ran" and "Failed" +* strings are available in all examples. This is a fix +* for CR-965028. +* ms 03/17/17 Added readme.txt file in examples folder for doxygen +* generation. +* ms 04/05/17 Modified Comment lines in functions of xadcps +* examples to recognize it as documentation block +* for doxygen generation. * * * diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_g.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_g.c index 4668ee8c5..22757f39b 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_g.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_2/src/xadcps_g.c @@ -5,7 +5,7 @@ * Version: * DO NOT EDIT. * -* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.* +* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.* *Permission is hereby granted, free of charge, to any person obtaining a copy *of this software and associated documentation files (the Software), to deal *in the Software without restriction, including without limitation the rights @@ -44,7 +44,7 @@ * The configuration table for devices */ -XAdcPs_Config XAdcPs_ConfigTable[] = +XAdcPs_Config XAdcPs_ConfigTable[XPAR_XADCPS_NUM_INSTANCES] = { { XPAR_PS7_XADC_0_DEVICE_ID, diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/system.mss b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/system.mss index f5e391f05..9708c1c47 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/system.mss +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/system.mss @@ -4,7 +4,7 @@ BEGIN OS PARAMETER OS_NAME = standalone - PARAMETER OS_VER = 5.4 + PARAMETER OS_VER = 6.6 PARAMETER PROC_INSTANCE = ps7_cortexa9_0 PARAMETER stdin = ps7_uart_1 PARAMETER stdout = ps7_uart_1 @@ -13,7 +13,7 @@ END BEGIN PROCESSOR PARAMETER DRIVER_NAME = cpu_cortexa9 - PARAMETER DRIVER_VER = 2.2 + PARAMETER DRIVER_VER = 2.6 PARAMETER HW_INSTANCE = ps7_cortexa9_0 END @@ -44,13 +44,13 @@ END BEGIN DRIVER PARAMETER DRIVER_NAME = canps - PARAMETER DRIVER_VER = 3.1 + PARAMETER DRIVER_VER = 3.2 PARAMETER HW_INSTANCE = ps7_can_0 END BEGIN DRIVER PARAMETER DRIVER_NAME = coresightps_dcc - PARAMETER DRIVER_VER = 1.2 + PARAMETER DRIVER_VER = 1.4 PARAMETER HW_INSTANCE = ps7_coresight_comp_0 END @@ -68,25 +68,25 @@ END BEGIN DRIVER PARAMETER DRIVER_NAME = devcfg - PARAMETER DRIVER_VER = 3.4 + PARAMETER DRIVER_VER = 3.5 PARAMETER HW_INSTANCE = ps7_dev_cfg_0 END BEGIN DRIVER PARAMETER DRIVER_NAME = dmaps - PARAMETER DRIVER_VER = 2.1 + PARAMETER DRIVER_VER = 2.3 PARAMETER HW_INSTANCE = ps7_dma_ns END BEGIN DRIVER PARAMETER DRIVER_NAME = dmaps - PARAMETER DRIVER_VER = 2.1 + PARAMETER DRIVER_VER = 2.3 PARAMETER HW_INSTANCE = ps7_dma_s END BEGIN DRIVER PARAMETER DRIVER_NAME = emacps - PARAMETER DRIVER_VER = 3.2 + PARAMETER DRIVER_VER = 3.7 PARAMETER HW_INSTANCE = ps7_ethernet_0 END @@ -98,7 +98,7 @@ END BEGIN DRIVER PARAMETER DRIVER_NAME = gpiops - PARAMETER DRIVER_VER = 3.1 + PARAMETER DRIVER_VER = 3.3 PARAMETER HW_INSTANCE = ps7_gpio_0 END @@ -110,7 +110,7 @@ END BEGIN DRIVER PARAMETER DRIVER_NAME = iicps - PARAMETER DRIVER_VER = 3.1 + PARAMETER DRIVER_VER = 3.6 PARAMETER HW_INSTANCE = ps7_i2c_0 END @@ -152,7 +152,7 @@ END BEGIN DRIVER PARAMETER DRIVER_NAME = qspips - PARAMETER DRIVER_VER = 3.3 + PARAMETER DRIVER_VER = 3.4 PARAMETER HW_INSTANCE = ps7_qspi_0 END @@ -182,7 +182,7 @@ END BEGIN DRIVER PARAMETER DRIVER_NAME = scugic - PARAMETER DRIVER_VER = 3.2 + PARAMETER DRIVER_VER = 3.9 PARAMETER HW_INSTANCE = ps7_scugic_0 END @@ -200,7 +200,7 @@ END BEGIN DRIVER PARAMETER DRIVER_NAME = sdps - PARAMETER DRIVER_VER = 2.7 + PARAMETER DRIVER_VER = 3.4 PARAMETER HW_INSTANCE = ps7_sd_0 END @@ -212,19 +212,19 @@ END BEGIN DRIVER PARAMETER DRIVER_NAME = ttcps - PARAMETER DRIVER_VER = 3.1 + PARAMETER DRIVER_VER = 3.5 PARAMETER HW_INSTANCE = ps7_ttc_0 END BEGIN DRIVER PARAMETER DRIVER_NAME = uartps - PARAMETER DRIVER_VER = 3.1 + PARAMETER DRIVER_VER = 3.6 PARAMETER HW_INSTANCE = ps7_uart_1 END BEGIN DRIVER PARAMETER DRIVER_NAME = usbps - PARAMETER DRIVER_VER = 2.3 + PARAMETER DRIVER_VER = 2.4 PARAMETER HW_INSTANCE = ps7_usb_0 END diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/ZC702_hw_platform/ps7_init.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/ZC702_hw_platform/ps7_init.c index 29450b5f7..a06e30659 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/ZC702_hw_platform/ps7_init.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/ZC702_hw_platform/ps7_init.c @@ -400,39 +400,6 @@ unsigned long ps7_clock_init_data_3_0[] = { // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U // .. .. EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00400500U), - // .. .. SRCSEL = 0x0 - // .. .. ==> 0XF8000180[5:4] = 0x00000000U - // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. DIVISOR0 = 0x1 - // .. .. ==> 0XF8000180[13:8] = 0x00000001U - // .. .. ==> MASK : 0x00003F00U VAL : 0x00000100U - // .. .. DIVISOR1 = 0x1 - // .. .. ==> 0XF8000180[25:20] = 0x00000001U - // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. .. - EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100100U), - // .. .. SRCSEL = 0x0 - // .. .. ==> 0XF8000190[5:4] = 0x00000000U - // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. DIVISOR0 = 0x1 - // .. .. ==> 0XF8000190[13:8] = 0x00000001U - // .. .. ==> MASK : 0x00003F00U VAL : 0x00000100U - // .. .. DIVISOR1 = 0x1 - // .. .. ==> 0XF8000190[25:20] = 0x00000001U - // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. .. - EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00100100U), - // .. .. SRCSEL = 0x0 - // .. .. ==> 0XF80001A0[5:4] = 0x00000000U - // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. DIVISOR0 = 0x1 - // .. .. ==> 0XF80001A0[13:8] = 0x00000001U - // .. .. ==> MASK : 0x00003F00U VAL : 0x00000100U - // .. .. DIVISOR1 = 0x1 - // .. .. ==> 0XF80001A0[25:20] = 0x00000001U - // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. .. - EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00100100U), // .. .. CLK_621_TRUE = 0x1 // .. .. ==> 0XF80001C4[0:0] = 0x00000001U // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U @@ -1040,16 +1007,6 @@ unsigned long ps7_ddr_init_data_3_0[] = { // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U // .. .. EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), - // .. .. START: RESET ECC ERROR - // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 - // .. .. ==> 0XF80060C4[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. Clear_Correctable_DRAM_ECC_error = 1 - // .. .. ==> 0XF80060C4[1:1] = 0x00000001U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. - EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U), - // .. .. FINISH: RESET ECC ERROR // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 // .. .. ==> 0XF80060C4[0:0] = 0x00000000U // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U @@ -4654,39 +4611,6 @@ unsigned long ps7_clock_init_data_2_0[] = { // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U // .. .. EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00400500U), - // .. .. SRCSEL = 0x0 - // .. .. ==> 0XF8000180[5:4] = 0x00000000U - // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. DIVISOR0 = 0x1 - // .. .. ==> 0XF8000180[13:8] = 0x00000001U - // .. .. ==> MASK : 0x00003F00U VAL : 0x00000100U - // .. .. DIVISOR1 = 0x1 - // .. .. ==> 0XF8000180[25:20] = 0x00000001U - // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. .. - EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100100U), - // .. .. SRCSEL = 0x0 - // .. .. ==> 0XF8000190[5:4] = 0x00000000U - // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. DIVISOR0 = 0x1 - // .. .. ==> 0XF8000190[13:8] = 0x00000001U - // .. .. ==> MASK : 0x00003F00U VAL : 0x00000100U - // .. .. DIVISOR1 = 0x1 - // .. .. ==> 0XF8000190[25:20] = 0x00000001U - // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. .. - EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00100100U), - // .. .. SRCSEL = 0x0 - // .. .. ==> 0XF80001A0[5:4] = 0x00000000U - // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. DIVISOR0 = 0x1 - // .. .. ==> 0XF80001A0[13:8] = 0x00000001U - // .. .. ==> MASK : 0x00003F00U VAL : 0x00000100U - // .. .. DIVISOR1 = 0x1 - // .. .. ==> 0XF80001A0[25:20] = 0x00000001U - // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. .. - EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00100100U), // .. .. CLK_621_TRUE = 0x1 // .. .. ==> 0XF80001C4[0:0] = 0x00000001U // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U @@ -5368,16 +5292,6 @@ unsigned long ps7_ddr_init_data_2_0[] = { // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U // .. .. EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), - // .. .. START: RESET ECC ERROR - // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 - // .. .. ==> 0XF80060C4[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. Clear_Correctable_DRAM_ECC_error = 1 - // .. .. ==> 0XF80060C4[1:1] = 0x00000001U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. - EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U), - // .. .. FINISH: RESET ECC ERROR // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 // .. .. ==> 0XF80060C4[0:0] = 0x00000000U // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U @@ -9067,39 +8981,6 @@ unsigned long ps7_clock_init_data_1_0[] = { // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U // .. .. EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00400500U), - // .. .. SRCSEL = 0x0 - // .. .. ==> 0XF8000180[5:4] = 0x00000000U - // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. DIVISOR0 = 0x1 - // .. .. ==> 0XF8000180[13:8] = 0x00000001U - // .. .. ==> MASK : 0x00003F00U VAL : 0x00000100U - // .. .. DIVISOR1 = 0x1 - // .. .. ==> 0XF8000180[25:20] = 0x00000001U - // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. .. - EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100100U), - // .. .. SRCSEL = 0x0 - // .. .. ==> 0XF8000190[5:4] = 0x00000000U - // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. DIVISOR0 = 0x1 - // .. .. ==> 0XF8000190[13:8] = 0x00000001U - // .. .. ==> MASK : 0x00003F00U VAL : 0x00000100U - // .. .. DIVISOR1 = 0x1 - // .. .. ==> 0XF8000190[25:20] = 0x00000001U - // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. .. - EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00100100U), - // .. .. SRCSEL = 0x0 - // .. .. ==> 0XF80001A0[5:4] = 0x00000000U - // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. DIVISOR0 = 0x1 - // .. .. ==> 0XF80001A0[13:8] = 0x00000001U - // .. .. ==> MASK : 0x00003F00U VAL : 0x00000100U - // .. .. DIVISOR1 = 0x1 - // .. .. ==> 0XF80001A0[25:20] = 0x00000001U - // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. .. - EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00100100U), // .. .. CLK_621_TRUE = 0x1 // .. .. ==> 0XF80001C4[0:0] = 0x00000001U // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U @@ -9744,16 +9625,6 @@ unsigned long ps7_ddr_init_data_1_0[] = { // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U // .. .. EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), - // .. .. START: RESET ECC ERROR - // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 - // .. .. ==> 0XF80060C4[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. Clear_Correctable_DRAM_ECC_error = 1 - // .. .. ==> 0XF80060C4[1:1] = 0x00000001U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. - EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U), - // .. .. FINISH: RESET ECC ERROR // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 // .. .. ==> 0XF80060C4[0:0] = 0x00000000U // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U @@ -13229,6 +13100,7 @@ ps7_debug() return PS7_INIT_SUCCESS; } + int ps7_init() { @@ -13236,7 +13108,7 @@ ps7_init() unsigned long si_ver = ps7GetSiliconVersion (); int ret; //int pcw_ver = 0; - + if (si_ver == PCW_SILICON_VERSION_1) { ps7_mio_init_data = ps7_mio_init_data_1_0; ps7_pll_init_data = ps7_pll_init_data_1_0; diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/ZC702_hw_platform/ps7_init.html b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/ZC702_hw_platform/ps7_init.html index fa76c4919..ecd91ec0b 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/ZC702_hw_platform/ps7_init.html +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/ZC702_hw_platform/ps7_init.html @@ -5734,72 +5734,6 @@ FPGA0_CLK_CTRL - -FPGA1_CLK_CTRL - - - -0XF8000180 - - -32 - - -RW - - -0x000000 - - -PL Clock 1 Output control - - - - - -FPGA2_CLK_CTRL - - - -0XF8000190 - - -32 - - -RW - - -0x000000 - - -PL Clock 2 output control - - - - - -FPGA3_CLK_CTRL - - - -0XF80001A0 - - -32 - - -RW - - -0x000000 - - -PL Clock 3 output control - - - - CLK_621_TRUE @@ -7568,447 +7502,6 @@ SLCR_LOCK

-

Register ( slcr )FPGA1_CLK_CTRL

- - - - - - - - - - - - - - - - - -
-Register Name - -Address - -Width - -Type - -Reset Value - -Description -
-FPGA1_CLK_CTRL - -0XF8000180 - -32 - -rw - -0x00000000 - --- -
-

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-Field Name - -Bits - -Mask - -Value - -Shifted Value - -Description -
-SRCSEL - -5:4 - -30 - -0 - -0 - -Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. -
-DIVISOR0 - -13:8 - -3f00 - -1 - -100 - -Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. -
-DIVISOR1 - -25:20 - -3f00000 - -1 - -100000 - -Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide -
-FPGA1_CLK_CTRL@0XF8000180 - -31:0 - -3f03f30 - - - -100100 - -PL Clock 1 Output control -
-

-

Register ( slcr )FPGA2_CLK_CTRL

- - - - - - - - - - - - - - - - - -
-Register Name - -Address - -Width - -Type - -Reset Value - -Description -
-FPGA2_CLK_CTRL - -0XF8000190 - -32 - -rw - -0x00000000 - --- -
-

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-Field Name - -Bits - -Mask - -Value - -Shifted Value - -Description -
-SRCSEL - -5:4 - -30 - -0 - -0 - -Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. -
-DIVISOR0 - -13:8 - -3f00 - -1 - -100 - -Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. -
-DIVISOR1 - -25:20 - -3f00000 - -1 - -100000 - -Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide -
-FPGA2_CLK_CTRL@0XF8000190 - -31:0 - -3f03f30 - - - -100100 - -PL Clock 2 output control -
-

-

Register ( slcr )FPGA3_CLK_CTRL

- - - - - - - - - - - - - - - - - -
-Register Name - -Address - -Width - -Type - -Reset Value - -Description -
-FPGA3_CLK_CTRL - -0XF80001A0 - -32 - -rw - -0x00000000 - --- -
-

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-Field Name - -Bits - -Mask - -Value - -Shifted Value - -Description -
-SRCSEL - -5:4 - -30 - -0 - -0 - -Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. -
-DIVISOR0 - -13:8 - -3f00 - -1 - -100 - -Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. -
-DIVISOR1 - -25:20 - -3f00000 - -1 - -100000 - -Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide -
-FPGA3_CLK_CTRL@0XF80001A0 - -31:0 - -3f03f30 - - - -100100 - -PL Clock 3 output control -
-

Register ( slcr )CLK_621_TRUE

@@ -9468,28 +8961,6 @@ CHE_ECC_CONTROL_REG_OFFSET - - - - - - - -
- -CHE_ECC_CONTROL_REG_OFFSET - - -0XF80060C4 - -32 - -RW - -0x000000 - -ECC error clear -
CHE_CORR_ECC_LOG_REG_OFFSET @@ -16502,134 +15973,6 @@ ddrc_ctrl

-

RESET ECC ERROR

-

Register ( slcr )CHE_ECC_CONTROL_REG_OFFSET

- - - - - - - - - - - - - - - - - -
-Register Name - -Address - -Width - -Type - -Reset Value - -Description -
-CHE_ECC_CONTROL_REG_OFFSET - -0XF80060C4 - -32 - -rw - -0x00000000 - --- -
-

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-Field Name - -Bits - -Mask - -Value - -Shifted Value - -Description -
-Clear_Uncorrectable_DRAM_ECC_error - -0:0 - -1 - -1 - -1 - -Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters. -
-Clear_Correctable_DRAM_ECC_error - -1:1 - -2 - -1 - -2 - -Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters. -
-CHE_ECC_CONTROL_REG_OFFSET@0XF80060C4 - -31:0 - -3 - - - -3 - -ECC error clear -
-

Register ( slcr )CHE_ECC_CONTROL_REG_OFFSET

@@ -53700,72 +53043,6 @@ FPGA0_CLK_CTRL - - - - - - - - - - - - - - - - - - - - - - - -
- -FPGA1_CLK_CTRL - - -0XF8000180 - -32 - -RW - -0x000000 - -PL Clock 1 Output control -
- -FPGA2_CLK_CTRL - - -0XF8000190 - -32 - -RW - -0x000000 - -PL Clock 2 output control -
- -FPGA3_CLK_CTRL - - -0XF80001A0 - -32 - -RW - -0x000000 - -PL Clock 3 output control -
CLK_621_TRUE @@ -55534,447 +54811,6 @@ SLCR_LOCK

-

Register ( slcr )FPGA1_CLK_CTRL

- - - - - - - - - - - - - - - - - -
-Register Name - -Address - -Width - -Type - -Reset Value - -Description -
-FPGA1_CLK_CTRL - -0XF8000180 - -32 - -rw - -0x00000000 - --- -
-

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-Field Name - -Bits - -Mask - -Value - -Shifted Value - -Description -
-SRCSEL - -5:4 - -30 - -0 - -0 - -Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. -
-DIVISOR0 - -13:8 - -3f00 - -1 - -100 - -Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. -
-DIVISOR1 - -25:20 - -3f00000 - -1 - -100000 - -Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide -
-FPGA1_CLK_CTRL@0XF8000180 - -31:0 - -3f03f30 - - - -100100 - -PL Clock 1 Output control -
-

-

Register ( slcr )FPGA2_CLK_CTRL

- - - - - - - - - - - - - - - - - -
-Register Name - -Address - -Width - -Type - -Reset Value - -Description -
-FPGA2_CLK_CTRL - -0XF8000190 - -32 - -rw - -0x00000000 - --- -
-

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-Field Name - -Bits - -Mask - -Value - -Shifted Value - -Description -
-SRCSEL - -5:4 - -30 - -0 - -0 - -Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. -
-DIVISOR0 - -13:8 - -3f00 - -1 - -100 - -Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. -
-DIVISOR1 - -25:20 - -3f00000 - -1 - -100000 - -Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide -
-FPGA2_CLK_CTRL@0XF8000190 - -31:0 - -3f03f30 - - - -100100 - -PL Clock 2 output control -
-

-

Register ( slcr )FPGA3_CLK_CTRL

- - - - - - - - - - - - - - - - - -
-Register Name - -Address - -Width - -Type - -Reset Value - -Description -
-FPGA3_CLK_CTRL - -0XF80001A0 - -32 - -rw - -0x00000000 - --- -
-

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-Field Name - -Bits - -Mask - -Value - -Shifted Value - -Description -
-SRCSEL - -5:4 - -30 - -0 - -0 - -Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. -
-DIVISOR0 - -13:8 - -3f00 - -1 - -100 - -Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. -
-DIVISOR1 - -25:20 - -3f00000 - -1 - -100000 - -Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide -
-FPGA3_CLK_CTRL@0XF80001A0 - -31:0 - -3f03f30 - - - -100100 - -PL Clock 3 output control -
-

Register ( slcr )CLK_621_TRUE

@@ -57456,28 +56292,6 @@ CHE_ECC_CONTROL_REG_OFFSET - - - - - - - -
- -CHE_ECC_CONTROL_REG_OFFSET - - -0XF80060C4 - -32 - -RW - -0x000000 - -ECC error clear -
CHE_CORR_ECC_LOG_REG_OFFSET @@ -65057,134 +63871,6 @@ ddrc_ctrl

-

RESET ECC ERROR

-

Register ( slcr )CHE_ECC_CONTROL_REG_OFFSET

- - - - - - - - - - - - - - - - - -
-Register Name - -Address - -Width - -Type - -Reset Value - -Description -
-CHE_ECC_CONTROL_REG_OFFSET - -0XF80060C4 - -32 - -rw - -0x00000000 - --- -
-

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-Field Name - -Bits - -Mask - -Value - -Shifted Value - -Description -
-Clear_Uncorrectable_DRAM_ECC_error - -0:0 - -1 - -1 - -1 - -Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters. -
-Clear_Correctable_DRAM_ECC_error - -1:1 - -2 - -1 - -2 - -Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters. -
-CHE_ECC_CONTROL_REG_OFFSET@0XF80060C4 - -31:0 - -3 - - - -3 - -ECC error clear -
-

Register ( slcr )CHE_ECC_CONTROL_REG_OFFSET

@@ -102834,72 +101520,6 @@ FPGA0_CLK_CTRL - - - - - - - - - - - - - - - - - - - - - - - -
- -FPGA1_CLK_CTRL - - -0XF8000180 - -32 - -RW - -0x000000 - -FPGA 1 Output Clock Control -
- -FPGA2_CLK_CTRL - - -0XF8000190 - -32 - -RW - -0x000000 - -FPGA 2 Output Clock Control -
- -FPGA3_CLK_CTRL - - -0XF80001A0 - -32 - -RW - -0x000000 - -FPGA 3 Output Clock Control -
CLK_621_TRUE @@ -104668,447 +103288,6 @@ SLCR_LOCK

-

Register ( slcr )FPGA1_CLK_CTRL

- - - - - - - - - - - - - - - - - -
-Register Name - -Address - -Width - -Type - -Reset Value - -Description -
-FPGA1_CLK_CTRL - -0XF8000180 - -32 - -rw - -0x00000000 - --- -
-

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-Field Name - -Bits - -Mask - -Value - -Shifted Value - -Description -
-SRCSEL - -5:4 - -30 - -0 - -0 - -Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. -
-DIVISOR0 - -13:8 - -3f00 - -1 - -100 - -Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider -
-DIVISOR1 - -25:20 - -3f00000 - -1 - -100000 - -Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider -
-FPGA1_CLK_CTRL@0XF8000180 - -31:0 - -3f03f30 - - - -100100 - -FPGA 1 Output Clock Control -
-

-

Register ( slcr )FPGA2_CLK_CTRL

- - - - - - - - - - - - - - - - - -
-Register Name - -Address - -Width - -Type - -Reset Value - -Description -
-FPGA2_CLK_CTRL - -0XF8000190 - -32 - -rw - -0x00000000 - --- -
-

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-Field Name - -Bits - -Mask - -Value - -Shifted Value - -Description -
-SRCSEL - -5:4 - -30 - -0 - -0 - -Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. -
-DIVISOR0 - -13:8 - -3f00 - -1 - -100 - -Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider -
-DIVISOR1 - -25:20 - -3f00000 - -1 - -100000 - -Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider -
-FPGA2_CLK_CTRL@0XF8000190 - -31:0 - -3f03f30 - - - -100100 - -FPGA 2 Output Clock Control -
-

-

Register ( slcr )FPGA3_CLK_CTRL

- - - - - - - - - - - - - - - - - -
-Register Name - -Address - -Width - -Type - -Reset Value - -Description -
-FPGA3_CLK_CTRL - -0XF80001A0 - -32 - -rw - -0x00000000 - --- -
-

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-Field Name - -Bits - -Mask - -Value - -Shifted Value - -Description -
-SRCSEL - -5:4 - -30 - -0 - -0 - -Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. -
-DIVISOR0 - -13:8 - -3f00 - -1 - -100 - -Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider -
-DIVISOR1 - -25:20 - -3f00000 - -1 - -100000 - -Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider -
-FPGA3_CLK_CTRL@0XF80001A0 - -31:0 - -3f03f30 - - - -100100 - -FPGA 3 Output Clock Control -
-

Register ( slcr )CLK_621_TRUE

@@ -106546,28 +104725,6 @@ CHE_ECC_CONTROL_REG_OFFSET - - - - - - - -
- -CHE_ECC_CONTROL_REG_OFFSET - - -0XF80060C4 - -32 - -RW - -0x000000 - -ECC error clear register -
CHE_CORR_ECC_LOG_REG_OFFSET @@ -113753,134 +111910,6 @@ ddrc_ctrl

-

RESET ECC ERROR

-

Register ( slcr )CHE_ECC_CONTROL_REG_OFFSET

- - - - - - - - - - - - - - - - - -
-Register Name - -Address - -Width - -Type - -Reset Value - -Description -
-CHE_ECC_CONTROL_REG_OFFSET - -0XF80060C4 - -32 - -rw - -0x00000000 - --- -
-

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-Field Name - -Bits - -Mask - -Value - -Shifted Value - -Description -
-Clear_Uncorrectable_DRAM_ECC_error - -0:0 - -1 - -1 - -1 - -Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters. -
-Clear_Correctable_DRAM_ECC_error - -1:1 - -2 - -1 - -2 - -Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters. -
-CHE_ECC_CONTROL_REG_OFFSET@0XF80060C4 - -31:0 - -3 - - - -3 - -ECC error clear register -
-

Register ( slcr )CHE_ECC_CONTROL_REG_OFFSET

diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/ZC702_hw_platform/ps7_init.tcl b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/ZC702_hw_platform/ps7_init.tcl index 057dca0b3..05a88d2a8 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/ZC702_hw_platform/ps7_init.tcl +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/ZC702_hw_platform/ps7_init.tcl @@ -37,9 +37,6 @@ proc ps7_clock_init_data_3_0 {} { mask_write 0XF8000160 0x007F007F 0x00000000 mask_write 0XF8000168 0x00003F31 0x00000501 mask_write 0XF8000170 0x03F03F30 0x00400500 - mask_write 0XF8000180 0x03F03F30 0x00100100 - mask_write 0XF8000190 0x03F03F30 0x00100100 - mask_write 0XF80001A0 0x03F03F30 0x00100100 mask_write 0XF80001C4 0x00000001 0x00000001 mask_write 0XF800012C 0x01FFCCCD 0x01ED044D mask_write 0XF8000004 0x0000FFFF 0x0000767B @@ -79,7 +76,6 @@ proc ps7_ddr_init_data_3_0 {} { mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF mask_write 0XF80060B4 0x00000200 0x00000200 mask_write 0XF80060B8 0x01FFFFFF 0x00200066 - mask_write 0XF80060C4 0x00000003 0x00000003 mask_write 0XF80060C4 0x00000003 0x00000000 mask_write 0XF80060C8 0x000000FF 0x00000000 mask_write 0XF80060DC 0x00000001 0x00000000 @@ -289,9 +285,6 @@ proc ps7_clock_init_data_2_0 {} { mask_write 0XF8000160 0x007F007F 0x00000000 mask_write 0XF8000168 0x00003F31 0x00000501 mask_write 0XF8000170 0x03F03F30 0x00400500 - mask_write 0XF8000180 0x03F03F30 0x00100100 - mask_write 0XF8000190 0x03F03F30 0x00100100 - mask_write 0XF80001A0 0x03F03F30 0x00100100 mask_write 0XF80001C4 0x00000001 0x00000001 mask_write 0XF800012C 0x01FFCCCD 0x01ED044D mask_write 0XF8000004 0x0000FFFF 0x0000767B @@ -332,7 +325,6 @@ proc ps7_ddr_init_data_2_0 {} { mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF mask_write 0XF80060B4 0x000007FF 0x00000200 mask_write 0XF80060B8 0x01FFFFFF 0x00200066 - mask_write 0XF80060C4 0x00000003 0x00000003 mask_write 0XF80060C4 0x00000003 0x00000000 mask_write 0XF80060C8 0x000000FF 0x00000000 mask_write 0XF80060DC 0x00000001 0x00000000 @@ -542,9 +534,6 @@ proc ps7_clock_init_data_1_0 {} { mask_write 0XF8000160 0x007F007F 0x00000000 mask_write 0XF8000168 0x00003F31 0x00000501 mask_write 0XF8000170 0x03F03F30 0x00400500 - mask_write 0XF8000180 0x03F03F30 0x00100100 - mask_write 0XF8000190 0x03F03F30 0x00100100 - mask_write 0XF80001A0 0x03F03F30 0x00100100 mask_write 0XF80001C4 0x00000001 0x00000001 mask_write 0XF800012C 0x01FFCCCD 0x01ED044D mask_write 0XF8000004 0x0000FFFF 0x0000767B @@ -583,7 +572,6 @@ proc ps7_ddr_init_data_1_0 {} { mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF mask_write 0XF80060B4 0x000007FF 0x00000200 mask_write 0XF80060B8 0x01FFFFFF 0x00200066 - mask_write 0XF80060C4 0x00000003 0x00000003 mask_write 0XF80060C4 0x00000003 0x00000000 mask_write 0XF80060C8 0x000000FF 0x00000000 mask_write 0XF80060DC 0x00000001 0x00000000 @@ -825,13 +813,11 @@ proc ps7_debug {} { ps7_debug_3_0 } } - proc ps7_init {} { variable PCW_SILICON_VER_1_0 variable PCW_SILICON_VER_2_0 variable PCW_SILICON_VER_3_0 set sil_ver [ps_version] - if { $sil_ver == $PCW_SILICON_VER_1_0} { ps7_mio_init_data_1_0 ps7_pll_init_data_1_0 diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/ZC702_hw_platform/ps7_init_gpl.c b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/ZC702_hw_platform/ps7_init_gpl.c index 0a07f4f50..2000dd46f 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/ZC702_hw_platform/ps7_init_gpl.c +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/ZC702_hw_platform/ps7_init_gpl.c @@ -391,39 +391,6 @@ unsigned long ps7_clock_init_data_3_0[] = { // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U // .. .. EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00400500U), - // .. .. SRCSEL = 0x0 - // .. .. ==> 0XF8000180[5:4] = 0x00000000U - // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. DIVISOR0 = 0x1 - // .. .. ==> 0XF8000180[13:8] = 0x00000001U - // .. .. ==> MASK : 0x00003F00U VAL : 0x00000100U - // .. .. DIVISOR1 = 0x1 - // .. .. ==> 0XF8000180[25:20] = 0x00000001U - // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. .. - EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100100U), - // .. .. SRCSEL = 0x0 - // .. .. ==> 0XF8000190[5:4] = 0x00000000U - // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. DIVISOR0 = 0x1 - // .. .. ==> 0XF8000190[13:8] = 0x00000001U - // .. .. ==> MASK : 0x00003F00U VAL : 0x00000100U - // .. .. DIVISOR1 = 0x1 - // .. .. ==> 0XF8000190[25:20] = 0x00000001U - // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. .. - EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00100100U), - // .. .. SRCSEL = 0x0 - // .. .. ==> 0XF80001A0[5:4] = 0x00000000U - // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. DIVISOR0 = 0x1 - // .. .. ==> 0XF80001A0[13:8] = 0x00000001U - // .. .. ==> MASK : 0x00003F00U VAL : 0x00000100U - // .. .. DIVISOR1 = 0x1 - // .. .. ==> 0XF80001A0[25:20] = 0x00000001U - // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. .. - EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00100100U), // .. .. CLK_621_TRUE = 0x1 // .. .. ==> 0XF80001C4[0:0] = 0x00000001U // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U @@ -1031,16 +998,6 @@ unsigned long ps7_ddr_init_data_3_0[] = { // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U // .. .. EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), - // .. .. START: RESET ECC ERROR - // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 - // .. .. ==> 0XF80060C4[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. Clear_Correctable_DRAM_ECC_error = 1 - // .. .. ==> 0XF80060C4[1:1] = 0x00000001U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. - EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U), - // .. .. FINISH: RESET ECC ERROR // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 // .. .. ==> 0XF80060C4[0:0] = 0x00000000U // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U @@ -4645,39 +4602,6 @@ unsigned long ps7_clock_init_data_2_0[] = { // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U // .. .. EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00400500U), - // .. .. SRCSEL = 0x0 - // .. .. ==> 0XF8000180[5:4] = 0x00000000U - // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. DIVISOR0 = 0x1 - // .. .. ==> 0XF8000180[13:8] = 0x00000001U - // .. .. ==> MASK : 0x00003F00U VAL : 0x00000100U - // .. .. DIVISOR1 = 0x1 - // .. .. ==> 0XF8000180[25:20] = 0x00000001U - // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. .. - EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100100U), - // .. .. SRCSEL = 0x0 - // .. .. ==> 0XF8000190[5:4] = 0x00000000U - // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. DIVISOR0 = 0x1 - // .. .. ==> 0XF8000190[13:8] = 0x00000001U - // .. .. ==> MASK : 0x00003F00U VAL : 0x00000100U - // .. .. DIVISOR1 = 0x1 - // .. .. ==> 0XF8000190[25:20] = 0x00000001U - // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. .. - EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00100100U), - // .. .. SRCSEL = 0x0 - // .. .. ==> 0XF80001A0[5:4] = 0x00000000U - // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. DIVISOR0 = 0x1 - // .. .. ==> 0XF80001A0[13:8] = 0x00000001U - // .. .. ==> MASK : 0x00003F00U VAL : 0x00000100U - // .. .. DIVISOR1 = 0x1 - // .. .. ==> 0XF80001A0[25:20] = 0x00000001U - // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. .. - EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00100100U), // .. .. CLK_621_TRUE = 0x1 // .. .. ==> 0XF80001C4[0:0] = 0x00000001U // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U @@ -5359,16 +5283,6 @@ unsigned long ps7_ddr_init_data_2_0[] = { // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U // .. .. EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), - // .. .. START: RESET ECC ERROR - // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 - // .. .. ==> 0XF80060C4[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. Clear_Correctable_DRAM_ECC_error = 1 - // .. .. ==> 0XF80060C4[1:1] = 0x00000001U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. - EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U), - // .. .. FINISH: RESET ECC ERROR // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 // .. .. ==> 0XF80060C4[0:0] = 0x00000000U // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U @@ -9058,39 +8972,6 @@ unsigned long ps7_clock_init_data_1_0[] = { // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U // .. .. EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00400500U), - // .. .. SRCSEL = 0x0 - // .. .. ==> 0XF8000180[5:4] = 0x00000000U - // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. DIVISOR0 = 0x1 - // .. .. ==> 0XF8000180[13:8] = 0x00000001U - // .. .. ==> MASK : 0x00003F00U VAL : 0x00000100U - // .. .. DIVISOR1 = 0x1 - // .. .. ==> 0XF8000180[25:20] = 0x00000001U - // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. .. - EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00100100U), - // .. .. SRCSEL = 0x0 - // .. .. ==> 0XF8000190[5:4] = 0x00000000U - // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. DIVISOR0 = 0x1 - // .. .. ==> 0XF8000190[13:8] = 0x00000001U - // .. .. ==> MASK : 0x00003F00U VAL : 0x00000100U - // .. .. DIVISOR1 = 0x1 - // .. .. ==> 0XF8000190[25:20] = 0x00000001U - // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. .. - EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00100100U), - // .. .. SRCSEL = 0x0 - // .. .. ==> 0XF80001A0[5:4] = 0x00000000U - // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U - // .. .. DIVISOR0 = 0x1 - // .. .. ==> 0XF80001A0[13:8] = 0x00000001U - // .. .. ==> MASK : 0x00003F00U VAL : 0x00000100U - // .. .. DIVISOR1 = 0x1 - // .. .. ==> 0XF80001A0[25:20] = 0x00000001U - // .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U - // .. .. - EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00100100U), // .. .. CLK_621_TRUE = 0x1 // .. .. ==> 0XF80001C4[0:0] = 0x00000001U // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U @@ -9735,16 +9616,6 @@ unsigned long ps7_ddr_init_data_1_0[] = { // .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U // .. .. EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU ,0x00200066U), - // .. .. START: RESET ECC ERROR - // .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 - // .. .. ==> 0XF80060C4[0:0] = 0x00000001U - // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. .. Clear_Correctable_DRAM_ECC_error = 1 - // .. .. ==> 0XF80060C4[1:1] = 0x00000001U - // .. .. ==> MASK : 0x00000002U VAL : 0x00000002U - // .. .. - EMIT_MASKWRITE(0XF80060C4, 0x00000003U ,0x00000003U), - // .. .. FINISH: RESET ECC ERROR // .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 // .. .. ==> 0XF80060C4[0:0] = 0x00000000U // .. .. ==> MASK : 0x00000001U VAL : 0x00000000U @@ -13220,6 +13091,7 @@ ps7_debug() return PS7_INIT_SUCCESS; } + int ps7_init() { @@ -13227,7 +13099,7 @@ ps7_init() unsigned long si_ver = ps7GetSiliconVersion (); int ret; //int pcw_ver = 0; - + if (si_ver == PCW_SILICON_VERSION_1) { ps7_mio_init_data = ps7_mio_init_data_1_0; ps7_pll_init_data = ps7_pll_init_data_1_0; diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/ZC702_hw_platform/system.hdf b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/ZC702_hw_platform/system.hdf index 82ed8788f..b4e47c295 100644 Binary files a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/ZC702_hw_platform/system.hdf and b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/ZC702_hw_platform/system.hdf differ diff --git a/FreeRTOS/Demo/CORTEX_MPU_Simulator_Keil_GCC/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_MPU_Simulator_Keil_GCC/FreeRTOSConfig.h index cdee232d7..d74c384e0 100644 --- a/FreeRTOS/Demo/CORTEX_MPU_Simulator_Keil_GCC/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_MPU_Simulator_Keil_GCC/FreeRTOSConfig.h @@ -120,7 +120,7 @@ to exclude the API function. */ /* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */ #define configPRIO_BITS __NVIC_PRIO_BITS #else - #define configPRIO_BITS 8 /* 15 priority levels */ + #define configPRIO_BITS 4 /* 15 priority levels */ #endif /* The lowest interrupt priority that can be used in a call to a "set priority" diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5/.cproject b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5/.cproject index e67ed8330..de9ad404c 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5/.cproject +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5/.cproject @@ -18,18 +18,18 @@ - + - - - - - - - - - @@ -82,77 +88,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5/.project b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5/.project index 19cf84fa4..99270506b 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5/.project +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5/.project @@ -42,7 +42,7 @@ - 1462455164616 + 1525195743708 src/FreeRTOS_Source 5 @@ -51,7 +51,7 @@ - 1462455164616 + 1525195743711 src/FreeRTOS_Source 5 @@ -60,7 +60,7 @@ - 1462455164726 + 1525195743715 src/FreeRTOS_Source 5 @@ -69,7 +69,7 @@ - 1462455164766 + 1525195743718 src/FreeRTOS_Source 5 @@ -78,7 +78,7 @@ - 1462455164786 + 1525195743721 src/FreeRTOS_Source 5 @@ -86,6 +86,15 @@ 1.0-name-matches-false-false-timers.c + + 1525195743725 + src/FreeRTOS_Source + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-stream_buffer.c + + 1462455201203 src/FreeRTOS_Source/portable diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5/src/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5/src/FreeRTOSConfig.h index 7fc52c077..6bca21bad 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5/src/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5/src/FreeRTOSConfig.h @@ -120,6 +120,7 @@ to exclude the API function. */ #define INCLUDE_eTaskGetState 1 #define INCLUDE_xTaskAbortDelay 1 #define INCLUDE_xTaskGetHandle 1 +#define INCLUDE_xSemaphoreGetMutexHolder 1 /* This demo makes use of one or more example stats formatting functions. These format the raw data provided by the uxTaskGetSystemState() function in to human diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/.cproject b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/.cproject index 805e98fca..fc930db6c 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/.cproject +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/.cproject @@ -1,8 +1,8 @@ - - + + diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/.project b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/.project index ed0ff0ff0..7960aa322 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/.project +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/.project @@ -1,7 +1,7 @@ RTOSDemo_R5_bsp - Created by SDK v2016.4 + Created by SDK v2018.1 diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/Makefile index 071f646d1..610ec1a4e 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/Makefile +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/Makefile @@ -16,16 +16,20 @@ include: $(addsuffix /make.include,$(SUBDIRS)) libs: $(addsuffix /make.libs,$(SUBDIRS)) +clean: $(addsuffix /make.clean,$(SUBDIRS)) + $(PROCESSOR)/lib/libxil.a: $(PROCESSOR)/lib/libxil_init.a cp -f $< $@ %/make.include: $(if $(wildcard $(PROCESSOR)/lib/libxil_init.a),$(PROCESSOR)/lib/libxil.a,) @echo "Running Make include in $(subst /make.include,,$@)" - $(MAKE) -C $(subst /make.include,,$@) -s include "SHELL=$(SHELL)" "COMPILER=armr5-none-eabi-gcc" "ARCHIVER=armr5-none-eabi-ar" "COMPILER_FLAGS= -O2 -c -mcpu=cortex-r5" "EXTRA_COMPILER_FLAGS=-g -DARMR5" + $(MAKE) -C $(subst /make.include,,$@) -s include "SHELL=$(SHELL)" "COMPILER=armr5-none-eabi-gcc" "ARCHIVER=armr5-none-eabi-ar" "COMPILER_FLAGS= -O2 -c -mcpu=cortex-r5" "EXTRA_COMPILER_FLAGS=-g -DARMR5 -Wall -Wextra -mfloat-abi=hard -mfpu=vfpv3-d16" %/make.libs: include @echo "Running Make libs in $(subst /make.libs,,$@)" - $(MAKE) -C $(subst /make.libs,,$@) -s libs "SHELL=$(SHELL)" "COMPILER=armr5-none-eabi-gcc" "ARCHIVER=armr5-none-eabi-ar" "COMPILER_FLAGS= -O2 -c -mcpu=cortex-r5" "EXTRA_COMPILER_FLAGS=-g -DARMR5" + $(MAKE) -C $(subst /make.libs,,$@) -s libs "SHELL=$(SHELL)" "COMPILER=armr5-none-eabi-gcc" "ARCHIVER=armr5-none-eabi-ar" "COMPILER_FLAGS= -O2 -c -mcpu=cortex-r5" "EXTRA_COMPILER_FLAGS=-g -DARMR5 -Wall -Wextra -mfloat-abi=hard -mfpu=vfpv3-d16" +%/make.clean: + $(MAKE) -C $(subst /make.clean,,$@) -s clean clean: rm -f ${PROCESSOR}/lib/libxil.a diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/include/xparameters.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/include/xparameters.h index c85fe0a27..38c98f940 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/include/xparameters.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/include/xparameters.h @@ -1,20 +1,23 @@ +#ifndef XPARAMETERS_H /* prevent circular inclusions */ +#define XPARAMETERS_H /* by using protection macros */ + /* Definition for CPU ID */ -#define XPAR_CPU_ID 0 +#define XPAR_CPU_ID 0U /* Definitions for peripheral PSU_CORTEXR5_0 */ -#define XPAR_PSU_CORTEXR5_0_CPU_CLK_FREQ_HZ 499994995 +#define XPAR_PSU_CORTEXR5_0_CPU_CLK_FREQ_HZ 499950000 /******************************************************************/ /* Canonical definitions for peripheral PSU_CORTEXR5_0 */ -#define XPAR_CPU_CORTEXR5_0_CPU_CLK_FREQ_HZ 499994995 +#define XPAR_CPU_CORTEXR5_0_CPU_CLK_FREQ_HZ 499950000 /******************************************************************/ /* Definition for PSS REF CLK FREQUENCY */ -#define XPAR_PSU_PSS_REF_CLK_FREQ_HZ 33333000U +#define XPAR_PSU_PSS_REF_CLK_FREQ_HZ 33330000U #include "xparameters_ps.h" @@ -22,15 +25,9 @@ /******************************************************************/ -/* - * Definitions of PSU_TTC_3 counter 0 base address and frequency used - * by sleep and usleep APIs - */ - -#define SLEEP_TIMER_BASEADDR 0xFF140000 -#define SLEEP_TIMER_FREQUENCY 100000000 - -/******************************************************************/ + /*Definitions for peripheral PSU_R5_DDR_1 */ +#define XPAR_PSU_R5_DDR_1_S_AXI_BASEADDR 0x0 +#define XPAR_PSU_R5_DDR_1_S_AXI_HIGHADDR 0x7fffffff /* Number of Fabric Resets */ @@ -39,192 +36,225 @@ #define STDIN_BASEADDRESS 0xFF000000 #define STDOUT_BASEADDRESS 0xFF000000 +/******************************************************************/ + +/* Platform specific definitions */ +#define PLATFORM_ZYNQMP + +/* Definitions for debug logic configuration in lockstep mode */ +#define LOCKSTEP_MODE_DEBUG 0U + +/* Definitions for sleep timer configuration */ +#define SLEEP_TIMER_BASEADDR XPAR_PSU_TTC_9_BASEADDR +#define SLEEP_TIMER_FREQUENCY XPAR_PSU_TTC_9_TTC_CLK_FREQ_HZ +#define XSLEEP_TTC_INSTANCE 3 +#define XSLEEP_TIMER_IS_DEFAULT_TIMER + + +/******************************************************************/ +/* Definitions for driver AVBUF */ +#define XPAR_XAVBUF_NUM_INSTANCES 1 + +/* Definitions for peripheral PSU_DP */ +#define XPAR_PSU_DP_DEVICE_ID 0 +#define XPAR_PSU_DP_BASEADDR 0xFD4A0000 +#define XPAR_PSU_DP_HIGHADDR 0xFD4AFFFF + + +/******************************************************************/ + +/* Canonical definitions for peripheral PSU_DP */ +#define XPAR_XAVBUF_0_DEVICE_ID XPAR_PSU_DP_DEVICE_ID +#define XPAR_XAVBUF_0_BASEADDR 0xFD4A0000 +#define XPAR_XAVBUF_0_HIGHADDR 0xFD4AFFFF + + /******************************************************************/ /* Definitions for driver AXIPMON */ -#define XPAR_XAXIPMON_NUM_INSTANCES 4 +#define XPAR_XAXIPMON_NUM_INSTANCES 4U /* Definitions for peripheral PSU_APM_0 */ -#define XPAR_PSU_APM_0_DEVICE_ID 0 -#define XPAR_PSU_APM_0_BASEADDR 0xFD0B0000 -#define XPAR_PSU_APM_0_HIGHADDR 0xFD0BFFFF -#define XPAR_PSU_APM_0_GLOBAL_COUNT_WIDTH 32 -#define XPAR_PSU_APM_0_METRICS_SAMPLE_COUNT_WIDTH 32 -#define XPAR_PSU_APM_0_ENABLE_EVENT_COUNT 1 -#define XPAR_PSU_APM_0_NUM_MONITOR_SLOTS 6 -#define XPAR_PSU_APM_0_NUM_OF_COUNTERS 10 -#define XPAR_PSU_APM_0_HAVE_SAMPLED_METRIC_CNT 1 -#define XPAR_PSU_APM_0_ENABLE_EVENT_LOG 0 -#define XPAR_PSU_APM_0_FIFO_AXIS_DEPTH 32 -#define XPAR_PSU_APM_0_FIFO_AXIS_TDATA_WIDTH 56 -#define XPAR_PSU_APM_0_FIFO_AXIS_TID_WIDTH 1 -#define XPAR_PSU_APM_0_METRIC_COUNT_SCALE 1 -#define XPAR_PSU_APM_0_ENABLE_ADVANCED 1 -#define XPAR_PSU_APM_0_ENABLE_PROFILE 0 -#define XPAR_PSU_APM_0_ENABLE_TRACE 0 -#define XPAR_PSU_APM_0_S_AXI4_BASEADDR 0x00000000 -#define XPAR_PSU_APM_0_S_AXI4_HIGHADDR 0x00000000 -#define XPAR_PSU_APM_0_ENABLE_32BIT_FILTER_ID 1 +#define XPAR_PSU_APM_0_DEVICE_ID 0U +#define XPAR_PSU_APM_0_BASEADDR 0xFD0B0000U +#define XPAR_PSU_APM_0_HIGHADDR 0xFD0BFFFFU +#define XPAR_PSU_APM_0_GLOBAL_COUNT_WIDTH 32U +#define XPAR_PSU_APM_0_METRICS_SAMPLE_COUNT_WIDTH 32U +#define XPAR_PSU_APM_0_ENABLE_EVENT_COUNT 1U +#define XPAR_PSU_APM_0_NUM_MONITOR_SLOTS 6U +#define XPAR_PSU_APM_0_NUM_OF_COUNTERS 10U +#define XPAR_PSU_APM_0_HAVE_SAMPLED_METRIC_CNT 1U +#define XPAR_PSU_APM_0_ENABLE_EVENT_LOG 0U +#define XPAR_PSU_APM_0_FIFO_AXIS_DEPTH 32U +#define XPAR_PSU_APM_0_FIFO_AXIS_TDATA_WIDTH 56U +#define XPAR_PSU_APM_0_FIFO_AXIS_TID_WIDTH 1U +#define XPAR_PSU_APM_0_METRIC_COUNT_SCALE 1U +#define XPAR_PSU_APM_0_ENABLE_ADVANCED 1U +#define XPAR_PSU_APM_0_ENABLE_PROFILE 0U +#define XPAR_PSU_APM_0_ENABLE_TRACE 0U +#define XPAR_PSU_APM_0_S_AXI4_BASEADDR 0x00000000U +#define XPAR_PSU_APM_0_S_AXI4_HIGHADDR 0x00000000U +#define XPAR_PSU_APM_0_ENABLE_32BIT_FILTER_ID 1U /* Definitions for peripheral PSU_APM_1 */ -#define XPAR_PSU_APM_1_DEVICE_ID 1 -#define XPAR_PSU_APM_1_BASEADDR 0xFFA00000 -#define XPAR_PSU_APM_1_HIGHADDR 0xFFA0FFFF -#define XPAR_PSU_APM_1_GLOBAL_COUNT_WIDTH 32 -#define XPAR_PSU_APM_1_METRICS_SAMPLE_COUNT_WIDTH 32 -#define XPAR_PSU_APM_1_ENABLE_EVENT_COUNT 1 -#define XPAR_PSU_APM_1_NUM_MONITOR_SLOTS 1 -#define XPAR_PSU_APM_1_NUM_OF_COUNTERS 3 -#define XPAR_PSU_APM_1_HAVE_SAMPLED_METRIC_CNT 1 -#define XPAR_PSU_APM_1_ENABLE_EVENT_LOG 0 -#define XPAR_PSU_APM_1_FIFO_AXIS_DEPTH 32 -#define XPAR_PSU_APM_1_FIFO_AXIS_TDATA_WIDTH 56 -#define XPAR_PSU_APM_1_FIFO_AXIS_TID_WIDTH 1 -#define XPAR_PSU_APM_1_METRIC_COUNT_SCALE 1 -#define XPAR_PSU_APM_1_ENABLE_ADVANCED 1 -#define XPAR_PSU_APM_1_ENABLE_PROFILE 0 -#define XPAR_PSU_APM_1_ENABLE_TRACE 0 -#define XPAR_PSU_APM_1_S_AXI4_BASEADDR 0x00000000 -#define XPAR_PSU_APM_1_S_AXI4_HIGHADDR 0x00000000 -#define XPAR_PSU_APM_1_ENABLE_32BIT_FILTER_ID 1 +#define XPAR_PSU_APM_1_DEVICE_ID 1U +#define XPAR_PSU_APM_1_BASEADDR 0xFFA00000U +#define XPAR_PSU_APM_1_HIGHADDR 0xFFA0FFFFU +#define XPAR_PSU_APM_1_GLOBAL_COUNT_WIDTH 32U +#define XPAR_PSU_APM_1_METRICS_SAMPLE_COUNT_WIDTH 32U +#define XPAR_PSU_APM_1_ENABLE_EVENT_COUNT 1U +#define XPAR_PSU_APM_1_NUM_MONITOR_SLOTS 1U +#define XPAR_PSU_APM_1_NUM_OF_COUNTERS 3U +#define XPAR_PSU_APM_1_HAVE_SAMPLED_METRIC_CNT 1U +#define XPAR_PSU_APM_1_ENABLE_EVENT_LOG 0U +#define XPAR_PSU_APM_1_FIFO_AXIS_DEPTH 32U +#define XPAR_PSU_APM_1_FIFO_AXIS_TDATA_WIDTH 56U +#define XPAR_PSU_APM_1_FIFO_AXIS_TID_WIDTH 1U +#define XPAR_PSU_APM_1_METRIC_COUNT_SCALE 1U +#define XPAR_PSU_APM_1_ENABLE_ADVANCED 1U +#define XPAR_PSU_APM_1_ENABLE_PROFILE 0U +#define XPAR_PSU_APM_1_ENABLE_TRACE 0U +#define XPAR_PSU_APM_1_S_AXI4_BASEADDR 0x00000000U +#define XPAR_PSU_APM_1_S_AXI4_HIGHADDR 0x00000000U +#define XPAR_PSU_APM_1_ENABLE_32BIT_FILTER_ID 1U /* Definitions for peripheral PSU_APM_2 */ -#define XPAR_PSU_APM_2_DEVICE_ID 2 -#define XPAR_PSU_APM_2_BASEADDR 0xFFA10000 -#define XPAR_PSU_APM_2_HIGHADDR 0xFFA1FFFF -#define XPAR_PSU_APM_2_GLOBAL_COUNT_WIDTH 32 -#define XPAR_PSU_APM_2_METRICS_SAMPLE_COUNT_WIDTH 32 -#define XPAR_PSU_APM_2_ENABLE_EVENT_COUNT 1 -#define XPAR_PSU_APM_2_NUM_MONITOR_SLOTS 1 -#define XPAR_PSU_APM_2_NUM_OF_COUNTERS 3 -#define XPAR_PSU_APM_2_HAVE_SAMPLED_METRIC_CNT 1 -#define XPAR_PSU_APM_2_ENABLE_EVENT_LOG 0 -#define XPAR_PSU_APM_2_FIFO_AXIS_DEPTH 32 -#define XPAR_PSU_APM_2_FIFO_AXIS_TDATA_WIDTH 56 -#define XPAR_PSU_APM_2_FIFO_AXIS_TID_WIDTH 1 -#define XPAR_PSU_APM_2_METRIC_COUNT_SCALE 1 -#define XPAR_PSU_APM_2_ENABLE_ADVANCED 1 -#define XPAR_PSU_APM_2_ENABLE_PROFILE 0 -#define XPAR_PSU_APM_2_ENABLE_TRACE 0 -#define XPAR_PSU_APM_2_S_AXI4_BASEADDR 0x00000000 -#define XPAR_PSU_APM_2_S_AXI4_HIGHADDR 0x00000000 -#define XPAR_PSU_APM_2_ENABLE_32BIT_FILTER_ID 1 +#define XPAR_PSU_APM_2_DEVICE_ID 2U +#define XPAR_PSU_APM_2_BASEADDR 0xFFA10000U +#define XPAR_PSU_APM_2_HIGHADDR 0xFFA1FFFFU +#define XPAR_PSU_APM_2_GLOBAL_COUNT_WIDTH 32U +#define XPAR_PSU_APM_2_METRICS_SAMPLE_COUNT_WIDTH 32U +#define XPAR_PSU_APM_2_ENABLE_EVENT_COUNT 1U +#define XPAR_PSU_APM_2_NUM_MONITOR_SLOTS 1U +#define XPAR_PSU_APM_2_NUM_OF_COUNTERS 3U +#define XPAR_PSU_APM_2_HAVE_SAMPLED_METRIC_CNT 1U +#define XPAR_PSU_APM_2_ENABLE_EVENT_LOG 0U +#define XPAR_PSU_APM_2_FIFO_AXIS_DEPTH 32U +#define XPAR_PSU_APM_2_FIFO_AXIS_TDATA_WIDTH 56U +#define XPAR_PSU_APM_2_FIFO_AXIS_TID_WIDTH 1U +#define XPAR_PSU_APM_2_METRIC_COUNT_SCALE 1U +#define XPAR_PSU_APM_2_ENABLE_ADVANCED 1U +#define XPAR_PSU_APM_2_ENABLE_PROFILE 0U +#define XPAR_PSU_APM_2_ENABLE_TRACE 0U +#define XPAR_PSU_APM_2_S_AXI4_BASEADDR 0x00000000U +#define XPAR_PSU_APM_2_S_AXI4_HIGHADDR 0x00000000U +#define XPAR_PSU_APM_2_ENABLE_32BIT_FILTER_ID 1U /* Definitions for peripheral PSU_APM_5 */ -#define XPAR_PSU_APM_5_DEVICE_ID 3 -#define XPAR_PSU_APM_5_BASEADDR 0xFD490000 -#define XPAR_PSU_APM_5_HIGHADDR 0xFD49FFFF -#define XPAR_PSU_APM_5_GLOBAL_COUNT_WIDTH 32 -#define XPAR_PSU_APM_5_METRICS_SAMPLE_COUNT_WIDTH 32 -#define XPAR_PSU_APM_5_ENABLE_EVENT_COUNT 1 -#define XPAR_PSU_APM_5_NUM_MONITOR_SLOTS 1 -#define XPAR_PSU_APM_5_NUM_OF_COUNTERS 3 -#define XPAR_PSU_APM_5_HAVE_SAMPLED_METRIC_CNT 1 -#define XPAR_PSU_APM_5_ENABLE_EVENT_LOG 0 -#define XPAR_PSU_APM_5_FIFO_AXIS_DEPTH 32 -#define XPAR_PSU_APM_5_FIFO_AXIS_TDATA_WIDTH 56 -#define XPAR_PSU_APM_5_FIFO_AXIS_TID_WIDTH 1 -#define XPAR_PSU_APM_5_METRIC_COUNT_SCALE 1 -#define XPAR_PSU_APM_5_ENABLE_ADVANCED 1 -#define XPAR_PSU_APM_5_ENABLE_PROFILE 0 -#define XPAR_PSU_APM_5_ENABLE_TRACE 0 -#define XPAR_PSU_APM_5_S_AXI4_BASEADDR 0x00000000 -#define XPAR_PSU_APM_5_S_AXI4_HIGHADDR 0x00000000 -#define XPAR_PSU_APM_5_ENABLE_32BIT_FILTER_ID 1 +#define XPAR_PSU_APM_5_DEVICE_ID 3U +#define XPAR_PSU_APM_5_BASEADDR 0xFD490000U +#define XPAR_PSU_APM_5_HIGHADDR 0xFD49FFFFU +#define XPAR_PSU_APM_5_GLOBAL_COUNT_WIDTH 32U +#define XPAR_PSU_APM_5_METRICS_SAMPLE_COUNT_WIDTH 32U +#define XPAR_PSU_APM_5_ENABLE_EVENT_COUNT 1U +#define XPAR_PSU_APM_5_NUM_MONITOR_SLOTS 1U +#define XPAR_PSU_APM_5_NUM_OF_COUNTERS 3U +#define XPAR_PSU_APM_5_HAVE_SAMPLED_METRIC_CNT 1U +#define XPAR_PSU_APM_5_ENABLE_EVENT_LOG 0U +#define XPAR_PSU_APM_5_FIFO_AXIS_DEPTH 32U +#define XPAR_PSU_APM_5_FIFO_AXIS_TDATA_WIDTH 56U +#define XPAR_PSU_APM_5_FIFO_AXIS_TID_WIDTH 1U +#define XPAR_PSU_APM_5_METRIC_COUNT_SCALE 1U +#define XPAR_PSU_APM_5_ENABLE_ADVANCED 1U +#define XPAR_PSU_APM_5_ENABLE_PROFILE 0U +#define XPAR_PSU_APM_5_ENABLE_TRACE 0U +#define XPAR_PSU_APM_5_S_AXI4_BASEADDR 0x00000000U +#define XPAR_PSU_APM_5_S_AXI4_HIGHADDR 0x00000000U +#define XPAR_PSU_APM_5_ENABLE_32BIT_FILTER_ID 1U /******************************************************************/ /* Canonical definitions for peripheral PSU_APM_0 */ #define XPAR_AXIPMON_0_DEVICE_ID XPAR_PSU_APM_0_DEVICE_ID -#define XPAR_AXIPMON_0_BASEADDR 0xFD0B0000 -#define XPAR_AXIPMON_0_HIGHADDR 0xFD0BFFFF -#define XPAR_AXIPMON_0_GLOBAL_COUNT_WIDTH 32 -#define XPAR_AXIPMON_0_METRICS_SAMPLE_COUNT_WIDTH 32 -#define XPAR_AXIPMON_0_ENABLE_EVENT_COUNT 1 -#define XPAR_AXIPMON_0_NUM_MONITOR_SLOTS 6 -#define XPAR_AXIPMON_0_NUM_OF_COUNTERS 10 -#define XPAR_AXIPMON_0_HAVE_SAMPLED_METRIC_CNT 1 -#define XPAR_AXIPMON_0_ENABLE_EVENT_LOG 0 -#define XPAR_AXIPMON_0_FIFO_AXIS_DEPTH 32 -#define XPAR_AXIPMON_0_FIFO_AXIS_TDATA_WIDTH 56 -#define XPAR_AXIPMON_0_FIFO_AXIS_TID_WIDTH 1 -#define XPAR_AXIPMON_0_METRIC_COUNT_SCALE 1 -#define XPAR_AXIPMON_0_ENABLE_ADVANCED 1 -#define XPAR_AXIPMON_0_ENABLE_PROFILE 0 -#define XPAR_AXIPMON_0_ENABLE_TRACE 0 -#define XPAR_AXIPMON_0_S_AXI4_BASEADDR 0x00000000 -#define XPAR_AXIPMON_0_S_AXI4_HIGHADDR 0x00000000 -#define XPAR_AXIPMON_0_ENABLE_32BIT_FILTER_ID 1 +#define XPAR_AXIPMON_0_BASEADDR 0xFD0B0000U +#define XPAR_AXIPMON_0_HIGHADDR 0xFD0BFFFFU +#define XPAR_AXIPMON_0_GLOBAL_COUNT_WIDTH 32U +#define XPAR_AXIPMON_0_METRICS_SAMPLE_COUNT_WIDTH 32U +#define XPAR_AXIPMON_0_ENABLE_EVENT_COUNT 1U +#define XPAR_AXIPMON_0_NUM_MONITOR_SLOTS 6U +#define XPAR_AXIPMON_0_NUM_OF_COUNTERS 10U +#define XPAR_AXIPMON_0_HAVE_SAMPLED_METRIC_CNT 1U +#define XPAR_AXIPMON_0_ENABLE_EVENT_LOG 0U +#define XPAR_AXIPMON_0_FIFO_AXIS_DEPTH 32U +#define XPAR_AXIPMON_0_FIFO_AXIS_TDATA_WIDTH 56U +#define XPAR_AXIPMON_0_FIFO_AXIS_TID_WIDTH 1U +#define XPAR_AXIPMON_0_METRIC_COUNT_SCALE 1U +#define XPAR_AXIPMON_0_ENABLE_ADVANCED 1U +#define XPAR_AXIPMON_0_ENABLE_PROFILE 0U +#define XPAR_AXIPMON_0_ENABLE_TRACE 0U +#define XPAR_AXIPMON_0_S_AXI4_BASEADDR 0x00000000U +#define XPAR_AXIPMON_0_S_AXI4_HIGHADDR 0x00000000U +#define XPAR_AXIPMON_0_ENABLE_32BIT_FILTER_ID 1U /* Canonical definitions for peripheral PSU_APM_1 */ #define XPAR_AXIPMON_1_DEVICE_ID XPAR_PSU_APM_1_DEVICE_ID -#define XPAR_AXIPMON_1_BASEADDR 0xFFA00000 -#define XPAR_AXIPMON_1_HIGHADDR 0xFFA0FFFF -#define XPAR_AXIPMON_1_GLOBAL_COUNT_WIDTH 32 -#define XPAR_AXIPMON_1_METRICS_SAMPLE_COUNT_WIDTH 32 -#define XPAR_AXIPMON_1_ENABLE_EVENT_COUNT 1 -#define XPAR_AXIPMON_1_NUM_MONITOR_SLOTS 1 -#define XPAR_AXIPMON_1_NUM_OF_COUNTERS 3 -#define XPAR_AXIPMON_1_HAVE_SAMPLED_METRIC_CNT 1 -#define XPAR_AXIPMON_1_ENABLE_EVENT_LOG 0 -#define XPAR_AXIPMON_1_FIFO_AXIS_DEPTH 32 -#define XPAR_AXIPMON_1_FIFO_AXIS_TDATA_WIDTH 56 -#define XPAR_AXIPMON_1_FIFO_AXIS_TID_WIDTH 1 -#define XPAR_AXIPMON_1_METRIC_COUNT_SCALE 1 -#define XPAR_AXIPMON_1_ENABLE_ADVANCED 1 -#define XPAR_AXIPMON_1_ENABLE_PROFILE 0 -#define XPAR_AXIPMON_1_ENABLE_TRACE 0 -#define XPAR_AXIPMON_1_S_AXI4_BASEADDR 0x00000000 -#define XPAR_AXIPMON_1_S_AXI4_HIGHADDR 0x00000000 -#define XPAR_AXIPMON_1_ENABLE_32BIT_FILTER_ID 1 +#define XPAR_AXIPMON_1_BASEADDR 0xFFA00000U +#define XPAR_AXIPMON_1_HIGHADDR 0xFFA0FFFFU +#define XPAR_AXIPMON_1_GLOBAL_COUNT_WIDTH 32U +#define XPAR_AXIPMON_1_METRICS_SAMPLE_COUNT_WIDTH 32U +#define XPAR_AXIPMON_1_ENABLE_EVENT_COUNT 1U +#define XPAR_AXIPMON_1_NUM_MONITOR_SLOTS 1U +#define XPAR_AXIPMON_1_NUM_OF_COUNTERS 3U +#define XPAR_AXIPMON_1_HAVE_SAMPLED_METRIC_CNT 1U +#define XPAR_AXIPMON_1_ENABLE_EVENT_LOG 0U +#define XPAR_AXIPMON_1_FIFO_AXIS_DEPTH 32U +#define XPAR_AXIPMON_1_FIFO_AXIS_TDATA_WIDTH 56U +#define XPAR_AXIPMON_1_FIFO_AXIS_TID_WIDTH 1U +#define XPAR_AXIPMON_1_METRIC_COUNT_SCALE 1U +#define XPAR_AXIPMON_1_ENABLE_ADVANCED 1U +#define XPAR_AXIPMON_1_ENABLE_PROFILE 0U +#define XPAR_AXIPMON_1_ENABLE_TRACE 0U +#define XPAR_AXIPMON_1_S_AXI4_BASEADDR 0x00000000U +#define XPAR_AXIPMON_1_S_AXI4_HIGHADDR 0x00000000U +#define XPAR_AXIPMON_1_ENABLE_32BIT_FILTER_ID 1U /* Canonical definitions for peripheral PSU_APM_2 */ #define XPAR_AXIPMON_2_DEVICE_ID XPAR_PSU_APM_2_DEVICE_ID -#define XPAR_AXIPMON_2_BASEADDR 0xFFA10000 -#define XPAR_AXIPMON_2_HIGHADDR 0xFFA1FFFF -#define XPAR_AXIPMON_2_GLOBAL_COUNT_WIDTH 32 -#define XPAR_AXIPMON_2_METRICS_SAMPLE_COUNT_WIDTH 32 -#define XPAR_AXIPMON_2_ENABLE_EVENT_COUNT 1 -#define XPAR_AXIPMON_2_NUM_MONITOR_SLOTS 1 -#define XPAR_AXIPMON_2_NUM_OF_COUNTERS 3 -#define XPAR_AXIPMON_2_HAVE_SAMPLED_METRIC_CNT 1 -#define XPAR_AXIPMON_2_ENABLE_EVENT_LOG 0 -#define XPAR_AXIPMON_2_FIFO_AXIS_DEPTH 32 -#define XPAR_AXIPMON_2_FIFO_AXIS_TDATA_WIDTH 56 -#define XPAR_AXIPMON_2_FIFO_AXIS_TID_WIDTH 1 -#define XPAR_AXIPMON_2_METRIC_COUNT_SCALE 1 -#define XPAR_AXIPMON_2_ENABLE_ADVANCED 1 -#define XPAR_AXIPMON_2_ENABLE_PROFILE 0 -#define XPAR_AXIPMON_2_ENABLE_TRACE 0 -#define XPAR_AXIPMON_2_S_AXI4_BASEADDR 0x00000000 -#define XPAR_AXIPMON_2_S_AXI4_HIGHADDR 0x00000000 -#define XPAR_AXIPMON_2_ENABLE_32BIT_FILTER_ID 1 +#define XPAR_AXIPMON_2_BASEADDR 0xFFA10000U +#define XPAR_AXIPMON_2_HIGHADDR 0xFFA1FFFFU +#define XPAR_AXIPMON_2_GLOBAL_COUNT_WIDTH 32U +#define XPAR_AXIPMON_2_METRICS_SAMPLE_COUNT_WIDTH 32U +#define XPAR_AXIPMON_2_ENABLE_EVENT_COUNT 1U +#define XPAR_AXIPMON_2_NUM_MONITOR_SLOTS 1U +#define XPAR_AXIPMON_2_NUM_OF_COUNTERS 3U +#define XPAR_AXIPMON_2_HAVE_SAMPLED_METRIC_CNT 1U +#define XPAR_AXIPMON_2_ENABLE_EVENT_LOG 0U +#define XPAR_AXIPMON_2_FIFO_AXIS_DEPTH 32U +#define XPAR_AXIPMON_2_FIFO_AXIS_TDATA_WIDTH 56U +#define XPAR_AXIPMON_2_FIFO_AXIS_TID_WIDTH 1U +#define XPAR_AXIPMON_2_METRIC_COUNT_SCALE 1U +#define XPAR_AXIPMON_2_ENABLE_ADVANCED 1U +#define XPAR_AXIPMON_2_ENABLE_PROFILE 0U +#define XPAR_AXIPMON_2_ENABLE_TRACE 0U +#define XPAR_AXIPMON_2_S_AXI4_BASEADDR 0x00000000U +#define XPAR_AXIPMON_2_S_AXI4_HIGHADDR 0x00000000U +#define XPAR_AXIPMON_2_ENABLE_32BIT_FILTER_ID 1U /* Canonical definitions for peripheral PSU_APM_5 */ #define XPAR_AXIPMON_3_DEVICE_ID XPAR_PSU_APM_5_DEVICE_ID -#define XPAR_AXIPMON_3_BASEADDR 0xFD490000 -#define XPAR_AXIPMON_3_HIGHADDR 0xFD49FFFF -#define XPAR_AXIPMON_3_GLOBAL_COUNT_WIDTH 32 -#define XPAR_AXIPMON_3_METRICS_SAMPLE_COUNT_WIDTH 32 -#define XPAR_AXIPMON_3_ENABLE_EVENT_COUNT 1 -#define XPAR_AXIPMON_3_NUM_MONITOR_SLOTS 1 -#define XPAR_AXIPMON_3_NUM_OF_COUNTERS 3 -#define XPAR_AXIPMON_3_HAVE_SAMPLED_METRIC_CNT 1 -#define XPAR_AXIPMON_3_ENABLE_EVENT_LOG 0 -#define XPAR_AXIPMON_3_FIFO_AXIS_DEPTH 32 -#define XPAR_AXIPMON_3_FIFO_AXIS_TDATA_WIDTH 56 -#define XPAR_AXIPMON_3_FIFO_AXIS_TID_WIDTH 1 -#define XPAR_AXIPMON_3_METRIC_COUNT_SCALE 1 -#define XPAR_AXIPMON_3_ENABLE_ADVANCED 1 -#define XPAR_AXIPMON_3_ENABLE_PROFILE 0 -#define XPAR_AXIPMON_3_ENABLE_TRACE 0 -#define XPAR_AXIPMON_3_S_AXI4_BASEADDR 0x00000000 -#define XPAR_AXIPMON_3_S_AXI4_HIGHADDR 0x00000000 -#define XPAR_AXIPMON_3_ENABLE_32BIT_FILTER_ID 1 +#define XPAR_AXIPMON_3_BASEADDR 0xFD490000U +#define XPAR_AXIPMON_3_HIGHADDR 0xFD49FFFFU +#define XPAR_AXIPMON_3_GLOBAL_COUNT_WIDTH 32U +#define XPAR_AXIPMON_3_METRICS_SAMPLE_COUNT_WIDTH 32U +#define XPAR_AXIPMON_3_ENABLE_EVENT_COUNT 1U +#define XPAR_AXIPMON_3_NUM_MONITOR_SLOTS 1U +#define XPAR_AXIPMON_3_NUM_OF_COUNTERS 3U +#define XPAR_AXIPMON_3_HAVE_SAMPLED_METRIC_CNT 1U +#define XPAR_AXIPMON_3_ENABLE_EVENT_LOG 0U +#define XPAR_AXIPMON_3_FIFO_AXIS_DEPTH 32U +#define XPAR_AXIPMON_3_FIFO_AXIS_TDATA_WIDTH 56U +#define XPAR_AXIPMON_3_FIFO_AXIS_TID_WIDTH 1U +#define XPAR_AXIPMON_3_METRIC_COUNT_SCALE 1U +#define XPAR_AXIPMON_3_ENABLE_ADVANCED 1U +#define XPAR_AXIPMON_3_ENABLE_PROFILE 0U +#define XPAR_AXIPMON_3_ENABLE_TRACE 0U +#define XPAR_AXIPMON_3_S_AXI4_BASEADDR 0x00000000U +#define XPAR_AXIPMON_3_S_AXI4_HIGHADDR 0x00000000U +#define XPAR_AXIPMON_3_ENABLE_32BIT_FILTER_ID 1U /******************************************************************/ @@ -236,7 +266,7 @@ #define XPAR_PSU_CAN_1_DEVICE_ID 0 #define XPAR_PSU_CAN_1_BASEADDR 0xFF070000 #define XPAR_PSU_CAN_1_HIGHADDR 0xFF07FFFF -#define XPAR_PSU_CAN_1_CAN_CLK_FREQ_HZ 99998999 +#define XPAR_PSU_CAN_1_CAN_CLK_FREQ_HZ 99990000 /******************************************************************/ @@ -245,7 +275,7 @@ #define XPAR_XCANPS_0_DEVICE_ID XPAR_PSU_CAN_1_DEVICE_ID #define XPAR_XCANPS_0_BASEADDR 0xFF070000 #define XPAR_XCANPS_0_HIGHADDR 0xFF07FFFF -#define XPAR_XCANPS_0_CAN_CLK_FREQ_HZ 99998999 +#define XPAR_XCANPS_0_CAN_CLK_FREQ_HZ 99990000 /******************************************************************/ @@ -279,7 +309,7 @@ #define XPAR_PSU_DDRC_0_BASEADDR 0xFD070000 #define XPAR_PSU_DDRC_0_HIGHADDR 0xFD070FFF #define XPAR_PSU_DDRC_0_HAS_ECC 0 -#define XPAR_PSU_DDRC_0_DDRC_CLK_FREQ_HZ 533328002 +#define XPAR_PSU_DDRC_0_DDRC_CLK_FREQ_HZ 533280000 /******************************************************************/ @@ -288,7 +318,26 @@ #define XPAR_DDRCPSU_0_DEVICE_ID XPAR_PSU_DDRC_0_DEVICE_ID #define XPAR_DDRCPSU_0_BASEADDR 0xFD070000 #define XPAR_DDRCPSU_0_HIGHADDR 0xFD070FFF -#define XPAR_DDRCPSU_0_DDRC_CLK_FREQ_HZ 533328002 +#define XPAR_DDRCPSU_0_DDRC_CLK_FREQ_HZ 533280000 + + +/******************************************************************/ + +/* Definitions for driver DPDMA */ +#define XPAR_XDPDMA_NUM_INSTANCES 1 + +/* Definitions for peripheral PSU_DPDMA */ +#define XPAR_PSU_DPDMA_DEVICE_ID 0 +#define XPAR_PSU_DPDMA_BASEADDR 0xFD4C0000 +#define XPAR_PSU_DPDMA_HIGHADDR 0xFD4CFFFF + + +/******************************************************************/ + +/* Canonical definitions for peripheral PSU_DPDMA */ +#define XPAR_XDPDMA_0_DEVICE_ID XPAR_PSU_DPDMA_DEVICE_ID +#define XPAR_XDPDMA_0_BASEADDR 0xFD4C0000 +#define XPAR_XDPDMA_0_HIGHADDR 0xFD4CFFFF /******************************************************************/ @@ -300,28 +349,31 @@ #define XPAR_PSU_ETHERNET_3_DEVICE_ID 0 #define XPAR_PSU_ETHERNET_3_BASEADDR 0xFF0E0000 #define XPAR_PSU_ETHERNET_3_HIGHADDR 0xFF0EFFFF -#define XPAR_PSU_ETHERNET_3_ENET_CLK_FREQ_HZ 124998749 +#define XPAR_PSU_ETHERNET_3_ENET_CLK_FREQ_HZ 124987500 #define XPAR_PSU_ETHERNET_3_ENET_SLCR_1000MBPS_DIV0 12 #define XPAR_PSU_ETHERNET_3_ENET_SLCR_1000MBPS_DIV1 1 #define XPAR_PSU_ETHERNET_3_ENET_SLCR_100MBPS_DIV0 60 #define XPAR_PSU_ETHERNET_3_ENET_SLCR_100MBPS_DIV1 1 #define XPAR_PSU_ETHERNET_3_ENET_SLCR_10MBPS_DIV0 60 #define XPAR_PSU_ETHERNET_3_ENET_SLCR_10MBPS_DIV1 10 +#define XPAR_PSU_ETHERNET_3_ENET_TSU_CLK_FREQ_HZ 249975000 /******************************************************************/ +#define XPAR_PSU_ETHERNET_3_IS_CACHE_COHERENT 0 /* Canonical definitions for peripheral PSU_ETHERNET_3 */ #define XPAR_XEMACPS_0_DEVICE_ID XPAR_PSU_ETHERNET_3_DEVICE_ID #define XPAR_XEMACPS_0_BASEADDR 0xFF0E0000 #define XPAR_XEMACPS_0_HIGHADDR 0xFF0EFFFF -#define XPAR_XEMACPS_0_ENET_CLK_FREQ_HZ 124998749 +#define XPAR_XEMACPS_0_ENET_CLK_FREQ_HZ 124987500 #define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV0 12 #define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV1 1 #define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV0 60 #define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV1 1 #define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV0 60 #define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV1 10 +#define XPAR_XEMACPS_0_ENET_TSU_CLK_FREQ_HZ 249975000 /******************************************************************/ @@ -377,16 +429,16 @@ #define XPAR_PSU_CCI_REG_S_AXI_HIGHADDR 0xFD5EFFFF -/* Definitions for peripheral PSU_CRF_APB */ -#define XPAR_PSU_CRF_APB_S_AXI_BASEADDR 0xFD1A0000 -#define XPAR_PSU_CRF_APB_S_AXI_HIGHADDR 0xFD2DFFFF - - /* Definitions for peripheral PSU_CRL_APB */ #define XPAR_PSU_CRL_APB_S_AXI_BASEADDR 0xFF5E0000 #define XPAR_PSU_CRL_APB_S_AXI_HIGHADDR 0xFF85FFFF +/* Definitions for peripheral PSU_CTRL_IPI */ +#define XPAR_PSU_CTRL_IPI_S_AXI_BASEADDR 0xFF380000 +#define XPAR_PSU_CTRL_IPI_S_AXI_HIGHADDR 0xFF3FFFFF + + /* Definitions for peripheral PSU_DDR_PHY */ #define XPAR_PSU_DDR_PHY_S_AXI_BASEADDR 0xFD080000 #define XPAR_PSU_DDR_PHY_S_AXI_HIGHADDR 0xFD08FFFF @@ -427,16 +479,6 @@ #define XPAR_PSU_DDR_XMPU5_CFG_S_AXI_HIGHADDR 0xFD05FFFF -/* Definitions for peripheral PSU_DP */ -#define XPAR_PSU_DP_S_AXI_BASEADDR 0xFD4A0000 -#define XPAR_PSU_DP_S_AXI_HIGHADDR 0xFD4AFFFF - - -/* Definitions for peripheral PSU_DPDMA */ -#define XPAR_PSU_DPDMA_S_AXI_BASEADDR 0xFD4C0000 -#define XPAR_PSU_DPDMA_S_AXI_HIGHADDR 0xFD4CFFFF - - /* Definitions for peripheral PSU_EFUSE */ #define XPAR_PSU_EFUSE_S_AXI_BASEADDR 0xFFCC0000 #define XPAR_PSU_EFUSE_S_AXI_HIGHADDR 0xFFCCFFFF @@ -517,6 +559,11 @@ #define XPAR_PSU_MBISTJTAG_S_AXI_HIGHADDR 0xFFCFFFFF +/* Definitions for peripheral PSU_MESSAGE_BUFFERS */ +#define XPAR_PSU_MESSAGE_BUFFERS_S_AXI_BASEADDR 0xFF990000 +#define XPAR_PSU_MESSAGE_BUFFERS_S_AXI_HIGHADDR 0xFF99FFFF + + /* Definitions for peripheral PSU_OCM */ #define XPAR_PSU_OCM_S_AXI_BASEADDR 0xFF960000 #define XPAR_PSU_OCM_S_AXI_HIGHADDR 0xFF96FFFF @@ -524,7 +571,7 @@ /* Definitions for peripheral PSU_OCM_RAM_0 */ #define XPAR_PSU_OCM_RAM_0_S_AXI_BASEADDR 0xFFFC0000 -#define XPAR_PSU_OCM_RAM_0_S_AXI_HIGHADDR 0xFFFEFFFF +#define XPAR_PSU_OCM_RAM_0_S_AXI_HIGHADDR 0xFFFFFFFF /* Definitions for peripheral PSU_OCM_XMPU_CFG */ @@ -547,6 +594,16 @@ #define XPAR_PSU_PCIE_DMA_S_AXI_HIGHADDR 0xFD0FFFFF +/* Definitions for peripheral PSU_PCIE_HIGH1 */ +#define XPAR_PSU_PCIE_HIGH1_S_AXI_BASEADDR 0x600000000 +#define XPAR_PSU_PCIE_HIGH1_S_AXI_HIGHADDR 0x7FFFFFFFF + + +/* Definitions for peripheral PSU_PCIE_HIGH2 */ +#define XPAR_PSU_PCIE_HIGH2_S_AXI_BASEADDR 0x8000000000 +#define XPAR_PSU_PCIE_HIGH2_S_AXI_HIGHADDR 0xBFFFFFFFFF + + /* Definitions for peripheral PSU_PCIE_LOW */ #define XPAR_PSU_PCIE_LOW_S_AXI_BASEADDR 0xE0000000 #define XPAR_PSU_PCIE_LOW_S_AXI_HIGHADDR 0xEFFFFFFF @@ -557,11 +614,6 @@ #define XPAR_PSU_PMU_GLOBAL_0_S_AXI_HIGHADDR 0xFFDBFFFF -/* Definitions for peripheral PSU_PMU_IOMODULE */ -#define XPAR_PSU_PMU_IOMODULE_S_AXI_BASEADDR 0xFFD40000 -#define XPAR_PSU_PMU_IOMODULE_S_AXI_HIGHADDR 0xFFD5FFFF - - /* Definitions for peripheral PSU_QSPI_LINEAR_0 */ #define XPAR_PSU_QSPI_LINEAR_0_S_AXI_BASEADDR 0xC0000000 #define XPAR_PSU_QSPI_LINEAR_0_S_AXI_HIGHADDR 0xDFFFFFFF @@ -579,7 +631,7 @@ /* Definitions for peripheral PSU_R5_DDR_0 */ #define XPAR_PSU_R5_DDR_0_S_AXI_BASEADDR 0x00100000 -#define XPAR_PSU_R5_DDR_0_S_AXI_HIGHADDR 0xFFFFFFFF +#define XPAR_PSU_R5_DDR_0_S_AXI_HIGHADDR 0x7FFFFFFF /* Definitions for peripheral PSU_R5_TCM_RAM_0 */ @@ -622,6 +674,11 @@ #define XPAR_PSU_SMMU_REG_S_AXI_HIGHADDR 0xFD5FFFFF +/* Definitions for peripheral PSU_USB_0 */ +#define XPAR_PSU_USB_0_S_AXI_BASEADDR 0xFF9D0000 +#define XPAR_PSU_USB_0_S_AXI_HIGHADDR 0xFF9DFFFF + + /******************************************************************/ /* Definitions for driver GPIOPS */ @@ -650,14 +707,14 @@ #define XPAR_PSU_I2C_0_DEVICE_ID 0 #define XPAR_PSU_I2C_0_BASEADDR 0xFF020000 #define XPAR_PSU_I2C_0_HIGHADDR 0xFF02FFFF -#define XPAR_PSU_I2C_0_I2C_CLK_FREQ_HZ 99998999 +#define XPAR_PSU_I2C_0_I2C_CLK_FREQ_HZ 99990000 /* Definitions for peripheral PSU_I2C_1 */ #define XPAR_PSU_I2C_1_DEVICE_ID 1 #define XPAR_PSU_I2C_1_BASEADDR 0xFF030000 #define XPAR_PSU_I2C_1_HIGHADDR 0xFF03FFFF -#define XPAR_PSU_I2C_1_I2C_CLK_FREQ_HZ 99998999 +#define XPAR_PSU_I2C_1_I2C_CLK_FREQ_HZ 99990000 /******************************************************************/ @@ -666,25 +723,25 @@ #define XPAR_XIICPS_0_DEVICE_ID XPAR_PSU_I2C_0_DEVICE_ID #define XPAR_XIICPS_0_BASEADDR 0xFF020000 #define XPAR_XIICPS_0_HIGHADDR 0xFF02FFFF -#define XPAR_XIICPS_0_I2C_CLK_FREQ_HZ 99998999 +#define XPAR_XIICPS_0_I2C_CLK_FREQ_HZ 99990000 /* Canonical definitions for peripheral PSU_I2C_1 */ #define XPAR_XIICPS_1_DEVICE_ID XPAR_PSU_I2C_1_DEVICE_ID #define XPAR_XIICPS_1_BASEADDR 0xFF030000 #define XPAR_XIICPS_1_HIGHADDR 0xFF03FFFF -#define XPAR_XIICPS_1_I2C_CLK_FREQ_HZ 99998999 +#define XPAR_XIICPS_1_I2C_CLK_FREQ_HZ 99990000 /******************************************************************/ -#define XPAR_XIPIPSU_NUM_INSTANCES 1 +#define XPAR_XIPIPSU_NUM_INSTANCES 1U /* Parameter definitions for peripheral psu_ipi_1 */ -#define XPAR_PSU_IPI_1_DEVICE_ID 0 -#define XPAR_PSU_IPI_1_BASE_ADDRESS 0xFF310000 -#define XPAR_PSU_IPI_1_BIT_MASK 0x00000100 -#define XPAR_PSU_IPI_1_BUFFER_INDEX 0 -#define XPAR_PSU_IPI_1_INT_ID 65 +#define XPAR_PSU_IPI_1_DEVICE_ID 0U +#define XPAR_PSU_IPI_1_BASE_ADDRESS 0xFF310000U +#define XPAR_PSU_IPI_1_BIT_MASK 0x00000100U +#define XPAR_PSU_IPI_1_BUFFER_INDEX 0U +#define XPAR_PSU_IPI_1_INT_ID 65U /* Canonical definitions for peripheral psu_ipi_1 */ #define XPAR_XIPIPSU_0_DEVICE_ID XPAR_PSU_IPI_1_DEVICE_ID @@ -693,58 +750,50 @@ #define XPAR_XIPIPSU_0_BUFFER_INDEX XPAR_PSU_IPI_1_BUFFER_INDEX #define XPAR_XIPIPSU_0_INT_ID XPAR_PSU_IPI_1_INT_ID -#define XPAR_XIPIPSU_NUM_TARGETS 11 +#define XPAR_XIPIPSU_NUM_TARGETS 7U -#define XPAR_PSU_IPI_0_BIT_MASK 0x00000001 -#define XPAR_PSU_IPI_0_BUFFER_INDEX 2 -#define XPAR_PSU_IPI_1_BIT_MASK 0x00000100 -#define XPAR_PSU_IPI_1_BUFFER_INDEX 0 -#define XPAR_PSU_IPI_2_BIT_MASK 0x00000200 -#define XPAR_PSU_IPI_2_BUFFER_INDEX 1 -#define XPAR_PSU_IPI_3_BIT_MASK 0x00010000 -#define XPAR_PSU_IPI_3_BUFFER_INDEX 7 -#define XPAR_PSU_IPI_4_BIT_MASK 0x00020000 -#define XPAR_PSU_IPI_4_BUFFER_INDEX 7 -#define XPAR_PSU_IPI_5_BIT_MASK 0x00040000 -#define XPAR_PSU_IPI_5_BUFFER_INDEX 7 -#define XPAR_PSU_IPI_6_BIT_MASK 0x00080000 -#define XPAR_PSU_IPI_6_BUFFER_INDEX 7 -#define XPAR_PSU_IPI_7_BIT_MASK 0x01000000 -#define XPAR_PSU_IPI_7_BUFFER_INDEX 3 -#define XPAR_PSU_IPI_8_BIT_MASK 0x02000000 -#define XPAR_PSU_IPI_8_BUFFER_INDEX 4 -#define XPAR_PSU_IPI_9_BIT_MASK 0x04000000 -#define XPAR_PSU_IPI_9_BUFFER_INDEX 5 -#define XPAR_PSU_IPI_10_BIT_MASK 0x08000000 -#define XPAR_PSU_IPI_10_BUFFER_INDEX 6 +#define XPAR_PSU_IPI_0_BIT_MASK 0x00000001U +#define XPAR_PSU_IPI_0_BUFFER_INDEX 2U +#define XPAR_PSU_IPI_1_BIT_MASK 0x00000100U +#define XPAR_PSU_IPI_1_BUFFER_INDEX 0U +#define XPAR_PSU_IPI_2_BIT_MASK 0x00000200U +#define XPAR_PSU_IPI_2_BUFFER_INDEX 1U +#define XPAR_PSU_IPI_3_BIT_MASK 0x00010000U +#define XPAR_PSU_IPI_3_BUFFER_INDEX 7U +#define XPAR_PSU_IPI_4_BIT_MASK 0x00020000U +#define XPAR_PSU_IPI_4_BUFFER_INDEX 7U +#define XPAR_PSU_IPI_5_BIT_MASK 0x00040000U +#define XPAR_PSU_IPI_5_BUFFER_INDEX 7U +#define XPAR_PSU_IPI_6_BIT_MASK 0x00080000U +#define XPAR_PSU_IPI_6_BUFFER_INDEX 7U /* Target List for referring to processor IPI Targets */ #define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH0_MASK XPAR_PSU_IPI_0_BIT_MASK -#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH0_INDEX 0 +#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH0_INDEX 0U #define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH0_MASK XPAR_PSU_IPI_0_BIT_MASK -#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH0_INDEX 0 +#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH0_INDEX 0U #define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH0_MASK XPAR_PSU_IPI_0_BIT_MASK -#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH0_INDEX 0 +#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH0_INDEX 0U #define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH0_MASK XPAR_PSU_IPI_0_BIT_MASK -#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH0_INDEX 0 +#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH0_INDEX 0U #define XPAR_XIPIPS_TARGET_PSU_CORTEXR5_0_CH0_MASK XPAR_PSU_IPI_1_BIT_MASK -#define XPAR_XIPIPS_TARGET_PSU_CORTEXR5_0_CH0_INDEX 1 +#define XPAR_XIPIPS_TARGET_PSU_CORTEXR5_0_CH0_INDEX 1U #define XPAR_XIPIPS_TARGET_PSU_CORTEXR5_1_CH0_MASK XPAR_PSU_IPI_2_BIT_MASK -#define XPAR_XIPIPS_TARGET_PSU_CORTEXR5_1_CH0_INDEX 2 +#define XPAR_XIPIPS_TARGET_PSU_CORTEXR5_1_CH0_INDEX 2U #define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH0_MASK XPAR_PSU_IPI_3_BIT_MASK -#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH0_INDEX 3 +#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH0_INDEX 3U #define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH1_MASK XPAR_PSU_IPI_4_BIT_MASK -#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH1_INDEX 4 +#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH1_INDEX 4U #define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH2_MASK XPAR_PSU_IPI_5_BIT_MASK -#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH2_INDEX 5 +#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH2_INDEX 5U #define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH3_MASK XPAR_PSU_IPI_6_BIT_MASK -#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH3_INDEX 6 +#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH3_INDEX 6U /* Definitions for driver QSPIPSU */ #define XPAR_XQSPIPSU_NUM_INSTANCES 1 @@ -753,22 +802,31 @@ #define XPAR_PSU_QSPI_0_DEVICE_ID 0 #define XPAR_PSU_QSPI_0_BASEADDR 0xFF0F0000 #define XPAR_PSU_QSPI_0_HIGHADDR 0xFF0FFFFF -#define XPAR_PSU_QSPI_0_QSPI_CLK_FREQ_HZ 124998749 +#define XPAR_PSU_QSPI_0_QSPI_CLK_FREQ_HZ 124987500 #define XPAR_PSU_QSPI_0_QSPI_MODE 2 #define XPAR_PSU_QSPI_0_QSPI_BUS_WIDTH 2 /******************************************************************/ +#define XPAR_PSU_QSPI_0_IS_CACHE_COHERENT 0 /* Canonical definitions for peripheral PSU_QSPI_0 */ #define XPAR_XQSPIPSU_0_DEVICE_ID XPAR_PSU_QSPI_0_DEVICE_ID #define XPAR_XQSPIPSU_0_BASEADDR 0xFF0F0000 #define XPAR_XQSPIPSU_0_HIGHADDR 0xFF0FFFFF -#define XPAR_XQSPIPSU_0_QSPI_CLK_FREQ_HZ 124998749 +#define XPAR_XQSPIPSU_0_QSPI_CLK_FREQ_HZ 124987500 #define XPAR_XQSPIPSU_0_QSPI_MODE 2 #define XPAR_XQSPIPSU_0_QSPI_BUS_WIDTH 2 +/******************************************************************/ + +/* Definitions for driver RESETPS */ +#define XPAR_XRESETPS_NUM_INSTANCES 1U +/* Definitions for peripheral RESETPS */ +#define XPAR_XRESETPS_DEVICE_ID 0 +#define XPAR_XRESETPS_BASEADDR 0xFFFFFFFFU + /******************************************************************/ /* Definitions for driver RTCPSU */ @@ -791,22 +849,22 @@ /******************************************************************/ /* Definitions for driver SCUGIC */ -#define XPAR_XSCUGIC_NUM_INSTANCES 1 +#define XPAR_XSCUGIC_NUM_INSTANCES 1U /* Definitions for peripheral PSU_RCPU_GIC */ -#define XPAR_PSU_RCPU_GIC_DEVICE_ID 0 -#define XPAR_PSU_RCPU_GIC_BASEADDR 0xF9001000 -#define XPAR_PSU_RCPU_GIC_HIGHADDR 0xF9001FFF -#define XPAR_PSU_RCPU_GIC_DIST_BASEADDR 0xF9000000 +#define XPAR_PSU_RCPU_GIC_DEVICE_ID 0U +#define XPAR_PSU_RCPU_GIC_BASEADDR 0xF9001000U +#define XPAR_PSU_RCPU_GIC_HIGHADDR 0xF9001FFFU +#define XPAR_PSU_RCPU_GIC_DIST_BASEADDR 0xF9000000U /******************************************************************/ /* Canonical definitions for peripheral PSU_RCPU_GIC */ -#define XPAR_SCUGIC_0_DEVICE_ID 0 -#define XPAR_SCUGIC_0_CPU_BASEADDR 0xF9001000 -#define XPAR_SCUGIC_0_CPU_HIGHADDR 0xF9001FFF -#define XPAR_SCUGIC_0_DIST_BASEADDR 0xF9000000 +#define XPAR_SCUGIC_0_DEVICE_ID 0U +#define XPAR_SCUGIC_0_CPU_BASEADDR 0xF9001000U +#define XPAR_SCUGIC_0_CPU_HIGHADDR 0xF9001FFFU +#define XPAR_SCUGIC_0_DIST_BASEADDR 0xF9000000U /******************************************************************/ @@ -818,24 +876,25 @@ #define XPAR_PSU_SD_1_DEVICE_ID 0 #define XPAR_PSU_SD_1_BASEADDR 0xFF170000 #define XPAR_PSU_SD_1_HIGHADDR 0xFF17FFFF -#define XPAR_PSU_SD_1_SDIO_CLK_FREQ_HZ 199998006 +#define XPAR_PSU_SD_1_SDIO_CLK_FREQ_HZ 187481250 #define XPAR_PSU_SD_1_HAS_CD 1 #define XPAR_PSU_SD_1_HAS_WP 1 -#define XPAR_PSU_SD_1_BUS_WIDTH 4 +#define XPAR_PSU_SD_1_BUS_WIDTH 8 #define XPAR_PSU_SD_1_MIO_BANK 1 #define XPAR_PSU_SD_1_HAS_EMIO 0 /******************************************************************/ +#define XPAR_PSU_SD_1_IS_CACHE_COHERENT 0 /* Canonical definitions for peripheral PSU_SD_1 */ #define XPAR_XSDPS_0_DEVICE_ID XPAR_PSU_SD_1_DEVICE_ID #define XPAR_XSDPS_0_BASEADDR 0xFF170000 #define XPAR_XSDPS_0_HIGHADDR 0xFF17FFFF -#define XPAR_XSDPS_0_SDIO_CLK_FREQ_HZ 199998006 +#define XPAR_XSDPS_0_SDIO_CLK_FREQ_HZ 187481250 #define XPAR_XSDPS_0_HAS_CD 1 #define XPAR_XSDPS_0_HAS_WP 1 -#define XPAR_XSDPS_0_BUS_WIDTH 4 +#define XPAR_XSDPS_0_BUS_WIDTH 8 #define XPAR_XSDPS_0_MIO_BANK 1 #define XPAR_XSDPS_0_HAS_EMIO 0 @@ -853,6 +912,7 @@ /******************************************************************/ +#define XPAR_PSU_AMS_REF_FREQMHZ 49.995 /* Canonical definitions for peripheral PSU_AMS */ #define XPAR_XSYSMONPSU_0_DEVICE_ID XPAR_PSU_AMS_DEVICE_ID #define XPAR_XSYSMONPSU_0_BASEADDR 0xFFA50000 @@ -862,133 +922,133 @@ /******************************************************************/ /* Definitions for driver TTCPS */ -#define XPAR_XTTCPS_NUM_INSTANCES 12 +#define XPAR_XTTCPS_NUM_INSTANCES 12U /* Definitions for peripheral PSU_TTC_0 */ -#define XPAR_PSU_TTC_0_DEVICE_ID 0 -#define XPAR_PSU_TTC_0_BASEADDR 0XFF110000 -#define XPAR_PSU_TTC_0_TTC_CLK_FREQ_HZ 100000000 -#define XPAR_PSU_TTC_0_TTC_CLK_CLKSRC 0 -#define XPAR_PSU_TTC_1_DEVICE_ID 1 -#define XPAR_PSU_TTC_1_BASEADDR 0XFF110004 -#define XPAR_PSU_TTC_1_TTC_CLK_FREQ_HZ 100000000 -#define XPAR_PSU_TTC_1_TTC_CLK_CLKSRC 0 -#define XPAR_PSU_TTC_2_DEVICE_ID 2 -#define XPAR_PSU_TTC_2_BASEADDR 0XFF110008 -#define XPAR_PSU_TTC_2_TTC_CLK_FREQ_HZ 100000000 -#define XPAR_PSU_TTC_2_TTC_CLK_CLKSRC 0 +#define XPAR_PSU_TTC_0_DEVICE_ID 0U +#define XPAR_PSU_TTC_0_BASEADDR 0XFF110000U +#define XPAR_PSU_TTC_0_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_PSU_TTC_0_TTC_CLK_CLKSRC 0U +#define XPAR_PSU_TTC_1_DEVICE_ID 1U +#define XPAR_PSU_TTC_1_BASEADDR 0XFF110004U +#define XPAR_PSU_TTC_1_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_PSU_TTC_1_TTC_CLK_CLKSRC 0U +#define XPAR_PSU_TTC_2_DEVICE_ID 2U +#define XPAR_PSU_TTC_2_BASEADDR 0XFF110008U +#define XPAR_PSU_TTC_2_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_PSU_TTC_2_TTC_CLK_CLKSRC 0U /* Definitions for peripheral PSU_TTC_1 */ -#define XPAR_PSU_TTC_3_DEVICE_ID 3 -#define XPAR_PSU_TTC_3_BASEADDR 0XFF120000 -#define XPAR_PSU_TTC_3_TTC_CLK_FREQ_HZ 100000000 -#define XPAR_PSU_TTC_3_TTC_CLK_CLKSRC 0 -#define XPAR_PSU_TTC_4_DEVICE_ID 4 -#define XPAR_PSU_TTC_4_BASEADDR 0XFF120004 -#define XPAR_PSU_TTC_4_TTC_CLK_FREQ_HZ 100000000 -#define XPAR_PSU_TTC_4_TTC_CLK_CLKSRC 0 -#define XPAR_PSU_TTC_5_DEVICE_ID 5 -#define XPAR_PSU_TTC_5_BASEADDR 0XFF120008 -#define XPAR_PSU_TTC_5_TTC_CLK_FREQ_HZ 100000000 -#define XPAR_PSU_TTC_5_TTC_CLK_CLKSRC 0 +#define XPAR_PSU_TTC_3_DEVICE_ID 3U +#define XPAR_PSU_TTC_3_BASEADDR 0XFF120000U +#define XPAR_PSU_TTC_3_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_PSU_TTC_3_TTC_CLK_CLKSRC 0U +#define XPAR_PSU_TTC_4_DEVICE_ID 4U +#define XPAR_PSU_TTC_4_BASEADDR 0XFF120004U +#define XPAR_PSU_TTC_4_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_PSU_TTC_4_TTC_CLK_CLKSRC 0U +#define XPAR_PSU_TTC_5_DEVICE_ID 5U +#define XPAR_PSU_TTC_5_BASEADDR 0XFF120008U +#define XPAR_PSU_TTC_5_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_PSU_TTC_5_TTC_CLK_CLKSRC 0U /* Definitions for peripheral PSU_TTC_2 */ -#define XPAR_PSU_TTC_6_DEVICE_ID 6 -#define XPAR_PSU_TTC_6_BASEADDR 0XFF130000 -#define XPAR_PSU_TTC_6_TTC_CLK_FREQ_HZ 100000000 -#define XPAR_PSU_TTC_6_TTC_CLK_CLKSRC 0 -#define XPAR_PSU_TTC_7_DEVICE_ID 7 -#define XPAR_PSU_TTC_7_BASEADDR 0XFF130004 -#define XPAR_PSU_TTC_7_TTC_CLK_FREQ_HZ 100000000 -#define XPAR_PSU_TTC_7_TTC_CLK_CLKSRC 0 -#define XPAR_PSU_TTC_8_DEVICE_ID 8 -#define XPAR_PSU_TTC_8_BASEADDR 0XFF130008 -#define XPAR_PSU_TTC_8_TTC_CLK_FREQ_HZ 100000000 -#define XPAR_PSU_TTC_8_TTC_CLK_CLKSRC 0 +#define XPAR_PSU_TTC_6_DEVICE_ID 6U +#define XPAR_PSU_TTC_6_BASEADDR 0XFF130000U +#define XPAR_PSU_TTC_6_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_PSU_TTC_6_TTC_CLK_CLKSRC 0U +#define XPAR_PSU_TTC_7_DEVICE_ID 7U +#define XPAR_PSU_TTC_7_BASEADDR 0XFF130004U +#define XPAR_PSU_TTC_7_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_PSU_TTC_7_TTC_CLK_CLKSRC 0U +#define XPAR_PSU_TTC_8_DEVICE_ID 8U +#define XPAR_PSU_TTC_8_BASEADDR 0XFF130008U +#define XPAR_PSU_TTC_8_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_PSU_TTC_8_TTC_CLK_CLKSRC 0U /* Definitions for peripheral PSU_TTC_3 */ -#define XPAR_PSU_TTC_9_DEVICE_ID 9 -#define XPAR_PSU_TTC_9_BASEADDR 0XFF140000 -#define XPAR_PSU_TTC_9_TTC_CLK_FREQ_HZ 100000000 -#define XPAR_PSU_TTC_9_TTC_CLK_CLKSRC 0 -#define XPAR_PSU_TTC_10_DEVICE_ID 10 -#define XPAR_PSU_TTC_10_BASEADDR 0XFF140004 -#define XPAR_PSU_TTC_10_TTC_CLK_FREQ_HZ 100000000 -#define XPAR_PSU_TTC_10_TTC_CLK_CLKSRC 0 -#define XPAR_PSU_TTC_11_DEVICE_ID 11 -#define XPAR_PSU_TTC_11_BASEADDR 0XFF140008 -#define XPAR_PSU_TTC_11_TTC_CLK_FREQ_HZ 100000000 -#define XPAR_PSU_TTC_11_TTC_CLK_CLKSRC 0 +#define XPAR_PSU_TTC_9_DEVICE_ID 9U +#define XPAR_PSU_TTC_9_BASEADDR 0XFF140000U +#define XPAR_PSU_TTC_9_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_PSU_TTC_9_TTC_CLK_CLKSRC 0U +#define XPAR_PSU_TTC_10_DEVICE_ID 10U +#define XPAR_PSU_TTC_10_BASEADDR 0XFF140004U +#define XPAR_PSU_TTC_10_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_PSU_TTC_10_TTC_CLK_CLKSRC 0U +#define XPAR_PSU_TTC_11_DEVICE_ID 11U +#define XPAR_PSU_TTC_11_BASEADDR 0XFF140008U +#define XPAR_PSU_TTC_11_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_PSU_TTC_11_TTC_CLK_CLKSRC 0U /******************************************************************/ /* Canonical definitions for peripheral PSU_TTC_0 */ #define XPAR_XTTCPS_0_DEVICE_ID XPAR_PSU_TTC_0_DEVICE_ID -#define XPAR_XTTCPS_0_BASEADDR 0xFF110000 -#define XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ 100000000 -#define XPAR_XTTCPS_0_TTC_CLK_CLKSRC 0 +#define XPAR_XTTCPS_0_BASEADDR 0xFF110000U +#define XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_XTTCPS_0_TTC_CLK_CLKSRC 0U #define XPAR_XTTCPS_1_DEVICE_ID XPAR_PSU_TTC_1_DEVICE_ID -#define XPAR_XTTCPS_1_BASEADDR 0xFF110004 -#define XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ 100000000 -#define XPAR_XTTCPS_1_TTC_CLK_CLKSRC 0 +#define XPAR_XTTCPS_1_BASEADDR 0xFF110004U +#define XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_XTTCPS_1_TTC_CLK_CLKSRC 0U #define XPAR_XTTCPS_2_DEVICE_ID XPAR_PSU_TTC_2_DEVICE_ID -#define XPAR_XTTCPS_2_BASEADDR 0xFF110008 -#define XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ 100000000 -#define XPAR_XTTCPS_2_TTC_CLK_CLKSRC 0 +#define XPAR_XTTCPS_2_BASEADDR 0xFF110008U +#define XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_XTTCPS_2_TTC_CLK_CLKSRC 0U /* Canonical definitions for peripheral PSU_TTC_1 */ #define XPAR_XTTCPS_3_DEVICE_ID XPAR_PSU_TTC_3_DEVICE_ID -#define XPAR_XTTCPS_3_BASEADDR 0xFF120000 -#define XPAR_XTTCPS_3_TTC_CLK_FREQ_HZ 100000000 -#define XPAR_XTTCPS_3_TTC_CLK_CLKSRC 0 +#define XPAR_XTTCPS_3_BASEADDR 0xFF120000U +#define XPAR_XTTCPS_3_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_XTTCPS_3_TTC_CLK_CLKSRC 0U #define XPAR_XTTCPS_4_DEVICE_ID XPAR_PSU_TTC_4_DEVICE_ID -#define XPAR_XTTCPS_4_BASEADDR 0xFF120004 -#define XPAR_XTTCPS_4_TTC_CLK_FREQ_HZ 100000000 -#define XPAR_XTTCPS_4_TTC_CLK_CLKSRC 0 +#define XPAR_XTTCPS_4_BASEADDR 0xFF120004U +#define XPAR_XTTCPS_4_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_XTTCPS_4_TTC_CLK_CLKSRC 0U #define XPAR_XTTCPS_5_DEVICE_ID XPAR_PSU_TTC_5_DEVICE_ID -#define XPAR_XTTCPS_5_BASEADDR 0xFF120008 -#define XPAR_XTTCPS_5_TTC_CLK_FREQ_HZ 100000000 -#define XPAR_XTTCPS_5_TTC_CLK_CLKSRC 0 +#define XPAR_XTTCPS_5_BASEADDR 0xFF120008U +#define XPAR_XTTCPS_5_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_XTTCPS_5_TTC_CLK_CLKSRC 0U /* Canonical definitions for peripheral PSU_TTC_2 */ #define XPAR_XTTCPS_6_DEVICE_ID XPAR_PSU_TTC_6_DEVICE_ID -#define XPAR_XTTCPS_6_BASEADDR 0xFF130000 -#define XPAR_XTTCPS_6_TTC_CLK_FREQ_HZ 100000000 -#define XPAR_XTTCPS_6_TTC_CLK_CLKSRC 0 +#define XPAR_XTTCPS_6_BASEADDR 0xFF130000U +#define XPAR_XTTCPS_6_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_XTTCPS_6_TTC_CLK_CLKSRC 0U #define XPAR_XTTCPS_7_DEVICE_ID XPAR_PSU_TTC_7_DEVICE_ID -#define XPAR_XTTCPS_7_BASEADDR 0xFF130004 -#define XPAR_XTTCPS_7_TTC_CLK_FREQ_HZ 100000000 -#define XPAR_XTTCPS_7_TTC_CLK_CLKSRC 0 +#define XPAR_XTTCPS_7_BASEADDR 0xFF130004U +#define XPAR_XTTCPS_7_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_XTTCPS_7_TTC_CLK_CLKSRC 0U #define XPAR_XTTCPS_8_DEVICE_ID XPAR_PSU_TTC_8_DEVICE_ID -#define XPAR_XTTCPS_8_BASEADDR 0xFF130008 -#define XPAR_XTTCPS_8_TTC_CLK_FREQ_HZ 100000000 -#define XPAR_XTTCPS_8_TTC_CLK_CLKSRC 0 +#define XPAR_XTTCPS_8_BASEADDR 0xFF130008U +#define XPAR_XTTCPS_8_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_XTTCPS_8_TTC_CLK_CLKSRC 0U /* Canonical definitions for peripheral PSU_TTC_3 */ #define XPAR_XTTCPS_9_DEVICE_ID XPAR_PSU_TTC_9_DEVICE_ID -#define XPAR_XTTCPS_9_BASEADDR 0xFF140000 -#define XPAR_XTTCPS_9_TTC_CLK_FREQ_HZ 100000000 -#define XPAR_XTTCPS_9_TTC_CLK_CLKSRC 0 +#define XPAR_XTTCPS_9_BASEADDR 0xFF140000U +#define XPAR_XTTCPS_9_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_XTTCPS_9_TTC_CLK_CLKSRC 0U #define XPAR_XTTCPS_10_DEVICE_ID XPAR_PSU_TTC_10_DEVICE_ID -#define XPAR_XTTCPS_10_BASEADDR 0xFF140004 -#define XPAR_XTTCPS_10_TTC_CLK_FREQ_HZ 100000000 -#define XPAR_XTTCPS_10_TTC_CLK_CLKSRC 0 +#define XPAR_XTTCPS_10_BASEADDR 0xFF140004U +#define XPAR_XTTCPS_10_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_XTTCPS_10_TTC_CLK_CLKSRC 0U #define XPAR_XTTCPS_11_DEVICE_ID XPAR_PSU_TTC_11_DEVICE_ID -#define XPAR_XTTCPS_11_BASEADDR 0xFF140008 -#define XPAR_XTTCPS_11_TTC_CLK_FREQ_HZ 100000000 -#define XPAR_XTTCPS_11_TTC_CLK_CLKSRC 0 +#define XPAR_XTTCPS_11_BASEADDR 0xFF140008U +#define XPAR_XTTCPS_11_TTC_CLK_FREQ_HZ 100000000U +#define XPAR_XTTCPS_11_TTC_CLK_CLKSRC 0U /******************************************************************/ @@ -1000,7 +1060,7 @@ #define XPAR_PSU_UART_0_DEVICE_ID 0 #define XPAR_PSU_UART_0_BASEADDR 0xFF000000 #define XPAR_PSU_UART_0_HIGHADDR 0xFF00FFFF -#define XPAR_PSU_UART_0_UART_CLK_FREQ_HZ 99998999 +#define XPAR_PSU_UART_0_UART_CLK_FREQ_HZ 99990000 #define XPAR_PSU_UART_0_HAS_MODEM 0 @@ -1008,7 +1068,7 @@ #define XPAR_PSU_UART_1_DEVICE_ID 1 #define XPAR_PSU_UART_1_BASEADDR 0xFF010000 #define XPAR_PSU_UART_1_HIGHADDR 0xFF01FFFF -#define XPAR_PSU_UART_1_UART_CLK_FREQ_HZ 99998999 +#define XPAR_PSU_UART_1_UART_CLK_FREQ_HZ 99990000 #define XPAR_PSU_UART_1_HAS_MODEM 0 @@ -1018,14 +1078,14 @@ #define XPAR_XUARTPS_0_DEVICE_ID XPAR_PSU_UART_0_DEVICE_ID #define XPAR_XUARTPS_0_BASEADDR 0xFF000000 #define XPAR_XUARTPS_0_HIGHADDR 0xFF00FFFF -#define XPAR_XUARTPS_0_UART_CLK_FREQ_HZ 99998999 +#define XPAR_XUARTPS_0_UART_CLK_FREQ_HZ 99990000 #define XPAR_XUARTPS_0_HAS_MODEM 0 /* Canonical definitions for peripheral PSU_UART_1 */ #define XPAR_XUARTPS_1_DEVICE_ID XPAR_PSU_UART_1_DEVICE_ID #define XPAR_XUARTPS_1_BASEADDR 0xFF010000 #define XPAR_XUARTPS_1_HIGHADDR 0xFF01FFFF -#define XPAR_XUARTPS_1_UART_CLK_FREQ_HZ 99998999 +#define XPAR_XUARTPS_1_UART_CLK_FREQ_HZ 99990000 #define XPAR_XUARTPS_1_HAS_MODEM 0 @@ -1034,16 +1094,17 @@ /* Definitions for driver USBPSU */ #define XPAR_XUSBPSU_NUM_INSTANCES 1 -/* Definitions for peripheral PSU_USB_0 */ -#define XPAR_PSU_USB_0_DEVICE_ID 0 -#define XPAR_PSU_USB_0_BASEADDR 0xFE200000 -#define XPAR_PSU_USB_0_HIGHADDR 0xFE20FFFF +/* Definitions for peripheral PSU_USB_XHCI_0 */ +#define XPAR_PSU_USB_XHCI_0_DEVICE_ID 0 +#define XPAR_PSU_USB_XHCI_0_BASEADDR 0xFE200000 +#define XPAR_PSU_USB_XHCI_0_HIGHADDR 0xFE20FFFF /******************************************************************/ -/* Canonical definitions for peripheral PSU_USB_0 */ -#define XPAR_XUSBPSU_0_DEVICE_ID XPAR_PSU_USB_0_DEVICE_ID +#define XPAR_PSU_USB_XHCI_0_IS_CACHE_COHERENT 0 +/* Canonical definitions for peripheral PSU_USB_XHCI_0 */ +#define XPAR_XUSBPSU_0_DEVICE_ID XPAR_PSU_USB_XHCI_0_DEVICE_ID #define XPAR_XUSBPSU_0_BASEADDR 0xFE200000 #define XPAR_XUSBPSU_0_HIGHADDR 0xFE20FFFF @@ -1051,35 +1112,48 @@ /******************************************************************/ /* Definitions for driver WDTPS */ -#define XPAR_XWDTPS_NUM_INSTANCES 2 +#define XPAR_XWDTPS_NUM_INSTANCES 3 + +/* Definitions for peripheral PSU_CSU_WDT */ +#define XPAR_PSU_CSU_WDT_DEVICE_ID 0 +#define XPAR_PSU_CSU_WDT_BASEADDR 0xFFCB0000 +#define XPAR_PSU_CSU_WDT_HIGHADDR 0xFFCBFFFF +#define XPAR_PSU_CSU_WDT_WDT_CLK_FREQ_HZ 100000000 + /* Definitions for peripheral PSU_WDT_0 */ -#define XPAR_PSU_WDT_0_DEVICE_ID 0 +#define XPAR_PSU_WDT_0_DEVICE_ID 1 #define XPAR_PSU_WDT_0_BASEADDR 0xFF150000 #define XPAR_PSU_WDT_0_HIGHADDR 0xFF15FFFF -#define XPAR_PSU_WDT_0_WDT_CLK_FREQ_HZ 99999001 +#define XPAR_PSU_WDT_0_WDT_CLK_FREQ_HZ 99989998 /* Definitions for peripheral PSU_WDT_1 */ -#define XPAR_PSU_WDT_1_DEVICE_ID 1 +#define XPAR_PSU_WDT_1_DEVICE_ID 2 #define XPAR_PSU_WDT_1_BASEADDR 0xFD4D0000 #define XPAR_PSU_WDT_1_HIGHADDR 0xFD4DFFFF -#define XPAR_PSU_WDT_1_WDT_CLK_FREQ_HZ 99999001 +#define XPAR_PSU_WDT_1_WDT_CLK_FREQ_HZ 99989998 /******************************************************************/ +/* Canonical definitions for peripheral PSU_CSU_WDT */ +#define XPAR_XWDTPS_0_DEVICE_ID XPAR_PSU_CSU_WDT_DEVICE_ID +#define XPAR_XWDTPS_0_BASEADDR 0xFFCB0000 +#define XPAR_XWDTPS_0_HIGHADDR 0xFFCBFFFF +#define XPAR_XWDTPS_0_WDT_CLK_FREQ_HZ 100000000 + /* Canonical definitions for peripheral PSU_WDT_0 */ -#define XPAR_XWDTPS_0_DEVICE_ID XPAR_PSU_WDT_0_DEVICE_ID -#define XPAR_XWDTPS_0_BASEADDR 0xFF150000 -#define XPAR_XWDTPS_0_HIGHADDR 0xFF15FFFF -#define XPAR_XWDTPS_0_WDT_CLK_FREQ_HZ 99999001 +#define XPAR_XWDTPS_1_DEVICE_ID XPAR_PSU_WDT_0_DEVICE_ID +#define XPAR_XWDTPS_1_BASEADDR 0xFF150000 +#define XPAR_XWDTPS_1_HIGHADDR 0xFF15FFFF +#define XPAR_XWDTPS_1_WDT_CLK_FREQ_HZ 99989998 /* Canonical definitions for peripheral PSU_WDT_1 */ -#define XPAR_XWDTPS_1_DEVICE_ID XPAR_PSU_WDT_1_DEVICE_ID -#define XPAR_XWDTPS_1_BASEADDR 0xFD4D0000 -#define XPAR_XWDTPS_1_HIGHADDR 0xFD4DFFFF -#define XPAR_XWDTPS_1_WDT_CLK_FREQ_HZ 99999001 +#define XPAR_XWDTPS_2_DEVICE_ID XPAR_PSU_WDT_1_DEVICE_ID +#define XPAR_XWDTPS_2_BASEADDR 0xFD4D0000 +#define XPAR_XWDTPS_2_HIGHADDR 0xFD4DFFFF +#define XPAR_XWDTPS_2_WDT_CLK_FREQ_HZ 99989998 /******************************************************************/ @@ -1217,6 +1291,22 @@ /******************************************************************/ +#define XPAR_PSU_ADMA_0_IS_CACHE_COHERENT 0 +#define XPAR_PSU_ADMA_1_IS_CACHE_COHERENT 0 +#define XPAR_PSU_ADMA_2_IS_CACHE_COHERENT 0 +#define XPAR_PSU_ADMA_3_IS_CACHE_COHERENT 0 +#define XPAR_PSU_ADMA_4_IS_CACHE_COHERENT 0 +#define XPAR_PSU_ADMA_5_IS_CACHE_COHERENT 0 +#define XPAR_PSU_ADMA_6_IS_CACHE_COHERENT 0 +#define XPAR_PSU_ADMA_7_IS_CACHE_COHERENT 0 +#define XPAR_PSU_GDMA_0_IS_CACHE_COHERENT 0 +#define XPAR_PSU_GDMA_1_IS_CACHE_COHERENT 0 +#define XPAR_PSU_GDMA_2_IS_CACHE_COHERENT 0 +#define XPAR_PSU_GDMA_3_IS_CACHE_COHERENT 0 +#define XPAR_PSU_GDMA_4_IS_CACHE_COHERENT 0 +#define XPAR_PSU_GDMA_5_IS_CACHE_COHERENT 0 +#define XPAR_PSU_GDMA_6_IS_CACHE_COHERENT 0 +#define XPAR_PSU_GDMA_7_IS_CACHE_COHERENT 0 /* Canonical definitions for peripheral PSU_ADMA_0 */ #define XPAR_XZDMA_0_DEVICE_ID XPAR_PSU_ADMA_0_DEVICE_ID #define XPAR_XZDMA_0_BASEADDR 0xFFA80000 @@ -1332,3 +1422,4 @@ /******************************************************************/ +#endif /* end of protection macro */ diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/avbuf_v2_1/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/avbuf_v2_1/src/Makefile new file mode 100644 index 000000000..2a2195c4d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/avbuf_v2_1/src/Makefile @@ -0,0 +1,40 @@ +COMPILER= +ARCHIVER= +CP=cp +COMPILER_FLAGS= +EXTRA_COMPILER_FLAGS= +LIB=libxil.a + +CC_FLAGS = $(COMPILER_FLAGS) +ECC_FLAGS = $(EXTRA_COMPILER_FLAGS) + +RELEASEDIR=../../../lib +INCLUDEDIR=../../../include +INCLUDES=-I./. -I${INCLUDEDIR} + +OUTS = *.o + +LIBSOURCES:=*.c +INCLUDEFILES:=*.h + +OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c))) + +libs: banner avbuf_libs clean + +%.o: %.c + ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $< + +banner: + echo "Compiling avbuf" + +avbuf_libs: ${OBJECTS} + $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS} + +.PHONY: include +include: avbuf_includes + +avbuf_includes: + ${CP} ${INCLUDEFILES} ${INCLUDEDIR} + +clean: + rm -rf ${OBJECTS} diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/avbuf_v2_1/src/xavbuf.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/avbuf_v2_1/src/xavbuf.c new file mode 100644 index 000000000..34e841ff5 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/avbuf_v2_1/src/xavbuf.c @@ -0,0 +1,1092 @@ +/******************************************************************************* + * + * Copyright (C) 2017 Xilinx, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * Use of the Software is limited solely to applications: + * (a) running on a Xilinx device, or + * (b) that interact with a Xilinx device through a bus or interconnect. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of the Xilinx shall not be used + * in advertising or otherwise to promote the sale, use or other dealings in + * this Software without prior written authorization from Xilinx. + * +*******************************************************************************/ +/******************************************************************************/ +/** + * + * @file xavbuf.c + * + * This file implements all the functions related to the Video Pipeline of the + * DisplayPort Subsystem. See xavbuf.h for the detailed description of the + * driver. + * + * @note None. + * + * 
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -----------------------------------------------
+ * 1.0   aad  06/24/17 Initial release.
+ * 2.0   aad  10/08/17 Some APIs to use enums instead of Macros.
+ *		       Some bug fixes.
+ *
+ * +*******************************************************************************/ +/******************************* Include Files ********************************/ +#include "xavbuf.h" +#include "xstatus.h" + +/**************************** Constant Definitions ****************************/ +const XAVBuf_VideoAttribute XAVBuf_SupportedFormats[XAVBUF_NUM_SUPPORTED]; + +/******************************************************************************/ +/** + * This function sets the scaling factors depending on the source video stream. + * + * @param InstancePtr is a pointer to the XAVBuf instance. + * @param RegOffset is the register offset of the SF0 register from the + * DP BaseAddress. + * @param Scaling Factors is a pointer to the scaling factors needed for + * scaling colors to 12 BPC. + * + * @return None. + * + * @note None. + * +*******************************************************************************/ +static void XAVBuf_SetScalingFactors(XAVBuf *InstancePtr, u32 RegOffset, + u32 *ScalingFactors) +{ + u32 Index = 0; + for (Index = 0; Index < 3; Index++) { + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, + RegOffset + (Index * 4), ScalingFactors[Index]); + } + +} + +/******************************************************************************/ +/** + * This function sets the Layer Control for Video and Graphics layers. + * + * @param InstancePtr is a pointer to the XAVBuf instance. + * @param RegOffset is the register offset of Video Layer or Graphics + * Layer from the base address + * @param Video is a pointer to the XAVBuf_VideoAttribute struct which + * has been configured for the particular layer + * + * @return None. + * + * @note None. + * +*******************************************************************************/ +static void XAVBuf_SetLayerControl(XAVBuf *InstancePtr, u32 RegOffset, + XAVBuf_VideoAttribute *Video) +{ + u32 RegVal = 0; + + RegVal = (Video->IsRGB << + XAVBUF_V_BLEND_LAYER0_CONTROL_RGB_MODE_SHIFT) | + Video->SamplingEn; + + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, RegOffset, RegVal); +} + +/******************************************************************************/ +/** + * This function applies Attributes for Live source(Video/Graphics). + * + * @param InstancePtr is an pointer to the XAVBuf Instance. + * @param RegConfig is a register offset for Video or Graphics config + * register + * @param Video is a pointer to the attributes of the video to be applied + * + * @return None. + * + * @note Live source can be live Video or Live Graphics. +******************************************************************************/ +static void XAVBuf_SetLiveVideoAttributes(XAVBuf *InstancePtr, u32 RegConfig, + XAVBuf_VideoAttribute *Video) +{ + u32 RegVal = 0; + + RegVal |= Video->Value << XAVBUF_BUF_LIVE_VID_CFG_FORMAT_SHIFT; + RegVal |= Video->BPP/6 - 3; + RegVal |= Video->Swap << XAVBUF_BUF_LIVE_VID_CFG_CB_FIRST_SHIFT; + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, RegConfig, RegVal); +} + +/******************************************************************************/ +/** + * This function applies Attributes for Non - Live source(Video/Graphics). + * + * @param InstancePtr is an pointer to the XAVBuf Instance. + * @param VideoSrc is the source of the Non-Live Video + * @param Video is a pointer to the attributes of the video to be applied + * + * @return None. + * + * @note Non Live source can be Non Live Video or Non Live Graphics. +******************************************************************************/ +static void XAVBuf_SetNonLiveVideoAttributes(XAVBuf *InstancePtr, u32 VideoSrc, + XAVBuf_VideoAttribute *Video) +{ + u32 RegVal = 0; + + RegVal = XAVBuf_ReadReg(InstancePtr->Config.BaseAddr, + XAVBUF_BUF_FORMAT); + if(VideoSrc == XAVBUF_VIDSTREAM1_NONLIVE) { + RegVal &= ~XAVBUF_BUF_FORMAT_NL_VID_FORMAT_MASK; + RegVal |= Video->Value; + } + else if (VideoSrc == XAVBUF_VIDSTREAM2_NONLIVE_GFX) { + RegVal &= ~XAVBUF_BUF_FORMAT_NL_GRAPHX_FORMAT_MASK; + RegVal |= (Video->Value) << + XAVBUF_BUF_FORMAT_NL_GRAPHX_FORMAT_SHIFT; + } + + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, XAVBUF_BUF_FORMAT, + RegVal); +} + +/******************************************************************************/ +/** + * This function programs the coeffitients for Color Space Conversion. + * + * @param InstancePtr is an pointer to the XAVBuf Instance. + * @param RegOffset is a register offset for Video or Graphics config + * register + * @param Video is a pointer to the XAVBuf_Attribute structure + * + * @return None. + * + * @note None. +******************************************************************************/ +static void XAVBuf_InConvertToRGB(XAVBuf *InstancePtr, u32 RegOffset, + XAVBuf_VideoAttribute *Video) +{ + u16 Index; + u16 *CSCMatrix; + u16 *OffsetMatrix; + + /* SDTV Coefficients */ + u16 CSCCoeffs[] = { 0x1000, 0x0000, 0x166F, + 0x1000, 0x7A7F, 0x7493, + 0x1000, 0x1C5A, 0x0000 }; + u16 CSCOffset[] = { 0x0000, 0x1800, 0x1800 }; + u16 RGBCoeffs[] = { 0x1000, 0x0000, 0x0000, + 0x0000, 0x1000, 0x0000, + 0x0000, 0x0000, 0x1000 }; + u16 RGBOffset[] = { 0x0000, 0x0000, 0x0000 }; + if(Video->IsRGB) { + CSCMatrix = RGBCoeffs; + OffsetMatrix = RGBOffset; + } + else { + CSCMatrix = CSCCoeffs; + OffsetMatrix = CSCOffset; + } + /* Program Colorspace conversion coefficients */ + for (Index = 9; Index < 12; Index++) { + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, + RegOffset + (Index * 4), + OffsetMatrix[Index - 9]); + } + + /* Program Colorspace conversion matrix */ + for (Index = 0; Index < 9; Index++) { + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, + RegOffset + (Index * 4), CSCMatrix[Index]); + } + +} + +/******************************************************************************/ +/** + * This function converts the Blender output to the desired output format. + * + * @param InstancePtr is an pointer to the XAVBuf Instance. + * @param RegConfig is a register offset for Video or Graphics config + * register + * @param Video is a pointer to the XAVBuf_Attribute structure + * + * @return None. + * + * @note None. +******************************************************************************/ +static void XAVBuf_InConvertToOutputFormat(XAVBuf *InstancePtr, + XAVBuf_VideoAttribute *Video) + +{ u32 Index = 0; + u32 RegOffset = XAVBUF_V_BLEND_RGB2YCBCR_COEFF0; + u32 ColorOffset = XAVBUF_V_BLEND_LUMA_OUTCSC_OFFSET; + u8 Value = Video->Value; + u16 *MatrixCoeff; + u16 *MatrixOffset; + + /* SDTV Coeffitients */ + u16 CSCCoeffs[] = { 0x04C8, 0x0964, 0x01D3, + 0x7D4C, 0x7AB4, 0x0800, + 0x0800, 0x7945, 0x7EB5 }; + u16 CSCOffset[] = { 0x0000, 0x800, 0x800 }; + u16 RGBCoeffs[] = { 0x1000, 0x0000, 0x0000, + 0x0000, 0x1000, 0x0000, + 0x0000, 0x0000, 0x1000 }; + u16 RGBOffset[] = { 0x0000, 0x0000, 0x0000 }; + + + if(Value) { + MatrixCoeff = CSCCoeffs; + MatrixOffset = CSCOffset; + + } + else { + MatrixCoeff = RGBCoeffs; + MatrixOffset = RGBOffset; + } + + for (Index = 0; Index < 9; Index++) { + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, + RegOffset + (Index * 4), MatrixCoeff[Index]); + } + for (Index = 0; Index < 3; Index++) { + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, + ColorOffset + (Index * 4), + (MatrixOffset[Index] << + XAVBUF_V_BLEND_LUMA_IN1CSC_OFFSET_POST_OFFSET_SHIFT)); + } +} +/******************************************************************************/ +/** + * This function configures the Video Pipeline for the selected source + * + * @param InstancePtr is an pointer to the XAVBuf Instance. + * @param VideoSrc is a parameter which indicates which Video Source + * selected + * + * @return None. + * + * @note None. +******************************************************************************/ +static int XAVBuf_ConfigureVideo(XAVBuf *InstancePtr, u8 VideoSrc) +{ + + u32 RegConfig = 0; + u32 ScalingOffset = 0; + u32 LayerOffset = 0; + u32 CSCOffset = 0; + XAVBuf_VideoAttribute *Video = NULL; + u32 *ScalingFactors = NULL; + + Xil_AssertNonvoid(InstancePtr != NULL); + switch(VideoSrc) { + case XAVBUF_VIDSTREAM1_LIVE: + RegConfig = XAVBUF_BUF_LIVE_VID_CFG; + ScalingOffset = XAVBUF_BUF_LIVE_VID_COMP0_SF; + LayerOffset = XAVBUF_V_BLEND_LAYER0_CONTROL; + CSCOffset = XAVBUF_V_BLEND_IN1CSC_COEFF0; + Video = InstancePtr->AVMode.LiveVideo; + ScalingFactors = Video->SF; + + /* Set the Video Attributes */ + XAVBuf_SetLiveVideoAttributes(InstancePtr, RegConfig, + Video); + break; + + case XAVBUF_VIDSTREAM2_LIVE_GFX: + RegConfig = XAVBUF_BUF_LIVE_GFX_CFG; + ScalingOffset = XAVBUF_BUF_LIVE_GFX_COMP0_SF; + LayerOffset = XAVBUF_V_BLEND_LAYER1_CONTROL; + CSCOffset = XAVBUF_V_BLEND_IN2CSC_COEFF0; + Video = InstancePtr->AVMode.LiveGraphics; + ScalingFactors = Video->SF; + + /* Set the Video Attributes */ + XAVBuf_SetLiveVideoAttributes(InstancePtr, RegConfig, + Video); + break; + + case XAVBUF_VIDSTREAM1_NONLIVE: + RegConfig = XAVBUF_BUF_LIVE_GFX_CFG; + ScalingOffset = XAVBUF_BUF_VID_COMP0_SCALE_FACTOR; + LayerOffset = XAVBUF_V_BLEND_LAYER0_CONTROL; + CSCOffset = XAVBUF_V_BLEND_IN1CSC_COEFF0; + Video = InstancePtr->AVMode.NonLiveVideo; + ScalingFactors = Video->SF; + + /* Set the Video Attributes */ + XAVBuf_SetNonLiveVideoAttributes(InstancePtr, VideoSrc, + Video); + break; + + case XAVBUF_VIDSTREAM2_NONLIVE_GFX: + RegConfig = XAVBUF_BUF_LIVE_GFX_CFG; + ScalingOffset = XAVBUF_BUF_GRAPHICS_COMP0_SCALE_FACTOR; + LayerOffset = XAVBUF_V_BLEND_LAYER1_CONTROL; + CSCOffset = XAVBUF_V_BLEND_IN2CSC_COEFF0; + Video = InstancePtr->AVMode.NonLiveGraphics; + ScalingFactors = Video->SF; + + /* Set the Video Attributes */ + XAVBuf_SetNonLiveVideoAttributes(InstancePtr, VideoSrc, + Video); + break; + case XAVBUF_VIDSTREAM1_TPG: + RegConfig |= 1 << + XAVBUF_V_BLEND_LAYER0_CONTROL_RGB_MODE_SHIFT; + RegConfig |= 1 << + XAVBUF_V_BLEND_LAYER0_CONTROL_BYPASS_SHIFT; + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, + XAVBUF_V_BLEND_LAYER0_CONTROL, + RegConfig); + break; + default: + return XST_FAILURE; + } + /* Setting the scaling factors */ + XAVBuf_SetScalingFactors(InstancePtr, ScalingOffset, ScalingFactors); + /* Layer Control */ + XAVBuf_SetLayerControl(InstancePtr, LayerOffset, Video); + /* Colorspace conversion */ + XAVBuf_InConvertToRGB(InstancePtr, CSCOffset, Video); + return XST_SUCCESS; +} + +/******************************************************************************/ +/** + * This function intializes the configuration for the AVBuf Instance. + * + * @param InstancePtr is a pointer to the XAVBuf instance. + * @param BaseAddr sets the base address of the AVBuf instance + * @param Deviceid is the id of the device from the design. + * + * @return None. + * + * @note Base address and DeviceId is same as the DP Core driver. + * +*******************************************************************************/ +void XAVBuf_CfgInitialize(XAVBuf *InstancePtr, u32 BaseAddr, u16 DeviceId) +{ + Xil_AssertVoid(InstancePtr != NULL); + + InstancePtr->Config.DeviceId = DeviceId; + InstancePtr->Config.BaseAddr = BaseAddr; +} + +/******************************************************************************/ +/** + * This function initializes all the data structures of the XAVBuf Instance. + * + * @param InstancePtr is a pointer to the XAVBuf instance. + * + * @return None. + * + * @note None. + * +*******************************************************************************/ +void XAVBuf_Initialize(XAVBuf *InstancePtr) +{ + Xil_AssertVoid(InstancePtr != NULL); + + InstancePtr->AVMode.NonLiveVideo = NULL; + InstancePtr->AVMode.LiveVideo = NULL; + InstancePtr->AVMode.LiveGraphics = NULL; + InstancePtr->AVMode.NonLiveGraphics = NULL; + InstancePtr->AVMode.VideoSrc = XAVBUF_VIDSTREAM1_NONE; + InstancePtr->AVMode.GraphicsSrc = XAVBUF_VIDSTREAM2_NONE; + InstancePtr->AVMode.Audio = NULL; + InstancePtr->AVMode.GraphicsAudio = NULL; + InstancePtr->AVMode.AudioSrc1 = XAVBUF_AUDSTREAM1_NO_AUDIO; + InstancePtr->AVMode.AudioSrc2 = XAVBUF_AUDSTREAM2_NO_AUDIO; + + InstancePtr->Blender.GlobalAlphaEn = 0; + InstancePtr->Blender.Alpha = 0; + InstancePtr->Blender.OutputVideo = NULL; + + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, XAVBUF_AUD_SOFT_RST, 0); +} + +/******************************************************************************/ +/** + * This function selects the source for the Video and Graphics streams that are + * passed on to the blender block. + * + * @param InstancePtr is a pointer to the XAVBuf instance. + * @param VidStream selects the stream coming from the video sources + * @param GfxStream selects the stream coming from the graphics sources + * + * @return None. + * + * @note None. + * +*******************************************************************************/ +void XAVBuf_InputVideoSelect(XAVBuf *InstancePtr, XAVBuf_VideoStream VidStream, + XAVBuf_GfxStream GfxStream) +{ + + + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid((VidStream != XAVBUF_VIDSTREAM1_LIVE) | + (VidStream != XAVBUF_VIDSTREAM1_NONLIVE) | + (VidStream != XAVBUF_VIDSTREAM1_TPG) | + (VidStream != XAVBUF_VIDSTREAM1_NONE)); + Xil_AssertVoid((GfxStream != XAVBUF_VIDSTREAM2_DISABLEGFX) | + (GfxStream != XAVBUF_VIDSTREAM2_NONLIVE_GFX) | + (GfxStream != XAVBUF_VIDSTREAM2_LIVE_GFX) | + (GfxStream != XAVBUF_VIDSTREAM2_NONE)); + + InstancePtr->AVMode.VideoSrc = VidStream; + InstancePtr->AVMode.GraphicsSrc = GfxStream; + u32 RegVal; + RegVal = XAVBuf_ReadReg(InstancePtr->Config.BaseAddr, + XAVBUF_BUF_OUTPUT_AUD_VID_SELECT); + RegVal &= ~(XAVBUF_BUF_OUTPUT_AUD_VID_SELECT_VID_STREAM2_SEL_MASK | + XAVBUF_BUF_OUTPUT_AUD_VID_SELECT_VID_STREAM1_SEL_MASK); + RegVal |= VidStream | GfxStream; + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, + XAVBUF_BUF_OUTPUT_AUD_VID_SELECT, RegVal); +} + +/******************************************************************************/ +/** + * This function sets the video format for the non-live video + * + * @param InstancePtr is a pointer to the XAVBuf instance. + * @param Format is the enum for the non-live video format + * + * @return XST_SUCCESS if the correct format has been set. + * XST_FAILURE if the format is invalid. + * + * @note None. +*******************************************************************************/ +int XAVBuf_SetInputNonLiveVideoFormat(XAVBuf *InstancePtr, + XAVBuf_VideoFormat Format) +{ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid((Format >= CbY0CrY1) | (Format <= YV16Ci2_420_10BPC)); + + InstancePtr->AVMode.NonLiveVideo = + XAVBuf_GetNLiveVideoAttribute(Format); + if(InstancePtr->AVMode.NonLiveVideo == NULL) + return XST_FAILURE; + + return XST_SUCCESS; +} + +/******************************************************************************/ +/** + * This function sets the graphics format for the non-live video + * + * @param InstancePtr is a pointer to the XAVBuf instance. + * @param Format is the enum for the non-live video format + * + * @return XST_SUCCESS if the correct format has been set. + * XST_FAILURE if the format is invalid. + * + * @note None. +*******************************************************************************/ +int XAVBuf_SetInputNonLiveGraphicsFormat(XAVBuf *InstancePtr, + XAVBuf_VideoFormat Format) +{ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid((Format >= RGBA8888) |( Format <= YOnly)); + + InstancePtr->AVMode.NonLiveGraphics = + XAVBuf_GetNLGraphicsAttribute(Format); + if(InstancePtr->AVMode.NonLiveGraphics == NULL) + return XST_FAILURE; + + return XST_SUCCESS; +} + +/******************************************************************************/ +/** + * This function sets the video format for the live video + * + * @param InstancePtr is a pointer to the XAVBuf instance. + * @param Format is the enum for the non-live video format + * + * @return XST_SUCCESS if the correct format has been set. + * XST_FAILURE if the format is invalid. + * + * @note None. +*******************************************************************************/ +int XAVBuf_SetInputLiveVideoFormat(XAVBuf *InstancePtr, + XAVBuf_VideoFormat Format) +{ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid((Format >= RGB_6BPC) | (Format <= YOnly_12BPC)); + + InstancePtr->AVMode.LiveVideo = XAVBuf_GetLiveVideoAttribute(Format); + if(InstancePtr->AVMode.LiveVideo == NULL) + return XST_FAILURE; + + return XST_SUCCESS; +} + +/******************************************************************************/ +/** + * This function sets the graphics format for the live video + * + * @param InstancePtr is a pointer to the XAVBuf instance. + * @param Format is the enum for the non-live video format + * + * @return XST_SUCCESS if the correct format has been set. + * XST_FAILURE if the format is invalid. + * + * @note None. +*******************************************************************************/ +int XAVBuf_SetInputLiveGraphicsFormat(XAVBuf *InstancePtr, + XAVBuf_VideoFormat Format) +{ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid((Format >= RGB_6BPC) | (Format <= YOnly_12BPC)); + + InstancePtr->AVMode.LiveGraphics = + XAVBuf_GetLiveVideoAttribute(Format); + if(InstancePtr->AVMode.LiveGraphics == NULL) + return XST_FAILURE; + + return XST_SUCCESS; +} + +/******************************************************************************/ +/** + * This function sets the Output Video Format + * + * @param InstancePtr is a pointer to the XAVBuf instance. + * @param Format is the enum for the non-live video format + * + * @return XST_SUCCESS if the correct format has been set. + * XST_FAILURE if the format is invalid. + * + * @note None. +*******************************************************************************/ +int XAVBuf_SetOutputVideoFormat(XAVBuf *InstancePtr, XAVBuf_VideoFormat Format) +{ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid((Format >= RGB_6BPC) | (Format <= YOnly_12BPC)); + + InstancePtr->Blender.OutputVideo = + XAVBuf_GetLiveVideoAttribute(Format); + if(InstancePtr->Blender.OutputVideo == NULL) + return XST_FAILURE; + else + return XST_SUCCESS; +} + +/******************************************************************************/ +/** + * This function sets the Audio and Video Clock Source and the video timing + * source. + * + * @param InstancePtr is a pointer to the XAVBuf instance. + * @param VideoClk selects the Video Clock Source + * @param AudioClk selects the Audio Clock Source + * + * @return None. + * + * @note System uses PL Clock for Video when Live source is in use. + * +*******************************************************************************/ +void XAVBuf_SetAudioVideoClkSrc(XAVBuf *InstancePtr, u8 VideoClk, u8 AudioClk) +{ + + u32 RegVal = 0; + + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid((VideoClk != XAVBUF_PS_CLK) | + (VideoClk!= XAVBUF_PL_CLK)); + Xil_AssertVoid((AudioClk != XAVBUF_PS_CLK) | + (AudioClk!= XAVBUF_PL_CLK)); + + if((InstancePtr->AVMode.VideoSrc != XAVBUF_VIDSTREAM1_LIVE) && + (InstancePtr->AVMode.GraphicsSrc != XAVBUF_VIDSTREAM2_LIVE_GFX)) { + RegVal = 1 << + XAVBUF_BUF_AUD_VID_CLK_SOURCE_VID_TIMING_SRC_SHIFT; + } + else if((InstancePtr->AVMode.VideoSrc == XAVBUF_VIDSTREAM1_LIVE) || + (InstancePtr->AVMode.GraphicsSrc == + XAVBUF_VIDSTREAM2_LIVE_GFX)) { + VideoClk = XAVBUF_PL_CLK; + } + + RegVal |= (VideoClk << + XAVBUF_BUF_AUD_VID_CLK_SOURCE_VID_CLK_SRC_SHIFT) | + (AudioClk << + XAVBUF_BUF_AUD_VID_CLK_SOURCE_AUD_CLK_SRC_SHIFT); + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, + XAVBUF_BUF_AUD_VID_CLK_SOURCE, RegVal); + /*Soft Reset VideoPipeline when changing the clock source*/ + XAVBuf_SoftReset(InstancePtr); +} + +/******************************************************************************/ +/** + * This function applies a soft reset to the Audio Video pipeline. + * + * @param InstancePtr is a pointer to the XAVBuf instance. + * + * @return None. + * + * @note None. + * +*******************************************************************************/ +void XAVBuf_SoftReset(XAVBuf *InstancePtr) +{ + Xil_AssertVoid(InstancePtr != NULL); + + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, XAVBUF_BUF_SRST_REG, + XAVBUF_BUF_SRST_REG_VID_RST_MASK); + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, XAVBUF_BUF_SRST_REG, 0); +} + +/******************************************************************************/ +/** + * This function looks up if the video format is valid or not for the non-live + * video datapath and returns a pointer to the attributes of the video. + * + * @param Format takes in the video format for which attributes are being + * requested. + * + * @return A pointer to the structure XAVBuf_VideoAttribute if the video + * format is valid, else returns NULL. + * @note None. +*******************************************************************************/ +XAVBuf_VideoAttribute *XAVBuf_GetLiveVideoAttribute(XAVBuf_VideoFormat Format) +{ + u8 Index = 0; + XAVBuf_VideoAttribute *VideoAttribute; + Xil_AssertNonvoid((Format >= RGB_6BPC) | (Format <= YOnly_12BPC)); + + for (Index = RGB_6BPC; Index <= YOnly_12BPC; Index++) { + VideoAttribute = (XAVBuf_VideoAttribute *) + &XAVBuf_SupportedFormats[Index]; + if(Format == VideoAttribute->VideoFormat) { + return VideoAttribute; + } + } + return NULL; +} + +/******************************************************************************/ +/** + * This function looks up if the video format is valid or not and returns a + * pointer to the attributes of the video. + * + * @param Format takes in the video format for which attributes are being + * requested. + * + * @return A pointer to the structure XAVBuf_VideoAttribute if the video + * format is valid, else returns NULL. + * @note None. +*******************************************************************************/ +XAVBuf_VideoAttribute *XAVBuf_GetNLiveVideoAttribute(XAVBuf_VideoFormat Format) +{ + u8 Index = 0; + XAVBuf_VideoAttribute *VideoAttribute; + + Xil_AssertNonvoid((Format >= CbY0CrY1) | (Format <= YV16Ci2_420_10BPC)); + + for (Index = CbY0CrY1; Index <= YV16Ci2_420_10BPC; Index++) { + VideoAttribute = (XAVBuf_VideoAttribute *) + &XAVBuf_SupportedFormats[Index]; + if(Format == VideoAttribute->VideoFormat) { + return VideoAttribute; + } + } + return NULL; +} + +/******************************************************************************/ +/** + * This function looks up if the video format is valid or not and returns a + * pointer to the attributes of the video. + * + * @param Format takes in the video format for which attributes are being + * requested. + * + * @return A pointer to the structure XAVBuf_VideoAttribute if the video + * format is valid, else returns NULL. + * @note None. +*******************************************************************************/ +XAVBuf_VideoAttribute *XAVBuf_GetNLGraphicsAttribute(XAVBuf_VideoFormat Format) +{ + u32 Index = 0; + XAVBuf_VideoAttribute *VideoAttribute; + + Xil_AssertNonvoid((Format >= RGBA8888) | (Format <= YOnly)); + + for(Index = RGBA8888; Index <= YOnly; Index++) { + VideoAttribute = (XAVBuf_VideoAttribute *) + &XAVBuf_SupportedFormats[Index]; + if(Format == VideoAttribute->VideoFormat) { + return VideoAttribute; + } + } + return NULL; +} + +/******************************************************************************/ +/** + * This function configures the Video Pipeline + * + * @param InstancePtr is an pointer to the XAVBuf Instance. + * + * @return None. + * + * @note None. +******************************************************************************/ +void XAVBuf_ConfigureVideoPipeline(XAVBuf *InstancePtr) +{ + Xil_AssertVoid(InstancePtr != NULL); + + XAVBuf_ConfigureVideo(InstancePtr, InstancePtr->AVMode.VideoSrc); +} + +/******************************************************************************/ +/** + * This function configures the Graphics Pipeline + * + * @param InstancePtr is an pointer to the XAVBuf Instance. + * + * @return None. + * + * @note None. +******************************************************************************/ +void XAVBuf_ConfigureGraphicsPipeline(XAVBuf *InstancePtr) +{ + Xil_AssertVoid(InstancePtr != NULL); + XAVBuf_ConfigureVideo(InstancePtr, InstancePtr->AVMode.GraphicsSrc); +} + +/******************************************************************************/ +/** + * This function sets the blender background color + * + * @param InstancePtr is an pointer to the XAVBuf Instance. + * @param Color is a pointer to the structure XAVBuf_BlenderBgClr + * + * @return None. + * + * @note None. +******************************************************************************/ +void XAVBuf_BlendSetBgColor(XAVBuf *InstancePtr, XAVBuf_BlenderBgClr *Color) +{ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(Color != NULL); + + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, XAVBUF_V_BLEND_BG_CLR_0, + Color->RCr); + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, XAVBUF_V_BLEND_BG_CLR_1, + Color->GY); + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, XAVBUF_V_BLEND_BG_CLR_2, + Color->BCb); +} + +/******************************************************************************/ +/** + * This function enables or disables global alpha + * + * @param InstancePtr is an pointer to the XAVBuf Instance. + * @param Enable sets a software flag for global alpha + * @param Alpha sets the value for the global alpha blending + * + * @return None. + * + * @note GlobalAlphaEn = 1, enables the global alpha. + * GlobalAlphaEn = 0, disables the global alpha. + * Alpha = 0, passes stream2 + * Alpha = 255, passes stream1 +******************************************************************************/ +void XAVBuf_SetBlenderAlpha(XAVBuf *InstancePtr, u8 Alpha, u8 Enable) +{ + u32 RegVal; + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid((Enable !=0) | (Enable != 1)); + + InstancePtr->Blender.GlobalAlphaEn = Enable; + InstancePtr->Blender.Alpha = Alpha; + + RegVal = Enable; + RegVal |= Alpha << XAVBUF_V_BLEND_SET_GLOBAL_ALPHA_REG_VALUE_SHIFT; + + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, + XAVBUF_V_BLEND_SET_GLOBAL_ALPHA_REG, RegVal); +} + +/******************************************************************************/ +/** + * This function configures the Output of the Video Pipeline + * + * @param InstancePtr is an pointer to the XAVBuf Instance. + * @param OutputVideo is a pointer to the XAVBuf_VideoAttribute. + * + * @return None. + * + * @note None. +******************************************************************************/ +void XAVBuf_ConfigureOutputVideo(XAVBuf *InstancePtr) +{ + u32 RegVal = 0; + XAVBuf_VideoAttribute *OutputVideo = InstancePtr->Blender.OutputVideo; + + RegVal |= OutputVideo->SamplingEn << + XAVBUF_V_BLEND_OUTPUT_VID_FORMAT_EN_DOWNSAMPLE_SHIFT; + RegVal |= OutputVideo->Value; + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, + XAVBUF_V_BLEND_OUTPUT_VID_FORMAT, RegVal); + + XAVBuf_InConvertToOutputFormat(InstancePtr, OutputVideo); +} + +/******************************************************************************/ +/** + * This function selects the source for audio streams corresponding to the + * Video and Graphics streams that are passed on to the blender + * + * @param InstancePtr is a pointer to the XAVBuf instance. + * @param AudStream1 selects the audio stream source corresponding to + * the video source selected + * @param AudStream2 selects the audio stream source corresponding to + * the graphics source selected. + * + * @return None. + * + * @note None. + * +*******************************************************************************/ +void XAVBuf_InputAudioSelect(XAVBuf *InstancePtr, XAVBuf_AudioStream1 AudStream1, + XAVBuf_AudioStream2 AudStream2) +{ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid((AudStream1 != XAVBUF_AUDSTREAM1_NONLIVE) | + (AudStream1 != XAVBUF_AUDSTREAM1_LIVE) | + (AudStream1 != XAVBUF_AUDSTREAM1_TPG)); + Xil_AssertVoid((AudStream2 != XAVBUF_AUDSTREAM2_NO_AUDIO) | + (AudStream2 != XAVBUF_AUDSTREAM2_AUDIOGFX)); + + u32 RegVal; + RegVal = XAVBuf_ReadReg(InstancePtr->Config.BaseAddr, + XAVBUF_BUF_OUTPUT_AUD_VID_SELECT); + RegVal &= ~(XAVBUF_BUF_OUTPUT_AUD_VID_SELECT_AUD_STREAM2_SEL_MASK | + XAVBUF_BUF_OUTPUT_AUD_VID_SELECT_AUD_STREAM1_SEL_MASK); + RegVal |= AudStream1 | AudStream2; + + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, + XAVBUF_BUF_OUTPUT_AUD_VID_SELECT, RegVal); +} + +/******************************************************************************/ +/** + * This function sets up the scaling factor for Audio Mixer Volume Control. + * + * @param InstancePtr is a pointer to the XAVBuf instance. + * @param Channel0Volume is the volume to be set for Audio from Channel0 + * @param Channel1Volume is the volume to be set for Audio from Channel1 + * + * + * @return None. + * + * @note None. + * +*******************************************************************************/ +void XAVBuf_AudioMixerVolumeControl(XAVBuf *InstancePtr, u8 Channel0Volume, + u8 Channel1Volume) +{ + u32 Val; + Xil_AssertVoid(InstancePtr != NULL); + Val = Channel1Volume << + XAVBUF_AUD_MIXER_VOLUME_CONTROL_VOL_CTRL_CH1_SHIFT; + Val |= Channel0Volume; + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, + XAVBUF_AUD_MIXER_VOLUME_CONTROL, Val); +} + +/******************************************************************************/ +/** + * This function resets the Audio Pipe. + * + * @param InstancePtr is a pointer to the XAVBuf Instance. + * + * @returns None. + * + * @note Needed when non-live audio is disabled. + * + * + ******************************************************************************/ +void XAVBuf_AudioSoftReset(XAVBuf *InstancePtr) +{ + u32 RegVal = 0; + Xil_AssertVoid(InstancePtr != NULL); + RegVal = XAVBuf_ReadReg(InstancePtr->Config.BaseAddr, + XAVBUF_AUD_SOFT_RST); + RegVal |= XAVBUF_AUD_SOFT_RST_AUD_SRST_MASK; + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, XAVBUF_AUD_SOFT_RST, + RegVal); + RegVal &= ~XAVBUF_AUD_SOFT_RST_AUD_SRST_MASK; + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, XAVBUF_AUD_SOFT_RST, 0); + +} + +/******************************************************************************/ +/** + * This function enables End of Line Reset for reduced blanking resolutions. + * + * @param InstancePtr is a pointer to the XAVBuf Instance. + * @param Disable is to be set while using Reduced Blanking Resolutions. + * + * @returns None. + * + * @note None. + * + ******************************************************************************/ +void XABuf_LineResetDisable(XAVBuf *InstancePtr, u8 Disable) +{ + u32 RegVal = 0; + Xil_AssertVoid(InstancePtr != NULL); + RegVal = XAVBuf_ReadReg(InstancePtr->Config.BaseAddr, + XAVBUF_AUD_SOFT_RST); + if(Disable) + RegVal |= XAVBUF_AUD_SOFT_RST_LINE_RST_DISABLE_MASK; + else + RegVal &= ~XAVBUF_AUD_SOFT_RST_LINE_RST_DISABLE_MASK; + + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, XAVBUF_AUD_SOFT_RST, + RegVal); +} + +/******************************************************************************/ +/** + * This function enables the video channel interface between the DPDMA and the + * AVBuf + * + * @param InstancePtr is a pointer to the XAVBuf Instance. + * @param Enable sets the corresponding buffers. + * + * @returns None. + * + * @note None. + * + ******************************************************************************/ +void XAVBuf_EnableVideoBuffers(XAVBuf *InstancePtr, u8 Enable) +{ + u8 Index; + u32 RegVal = 0; + u8 NumPlanes = InstancePtr->AVMode.NonLiveVideo->Mode; + + RegVal = (0xF << XAVBUF_CHBUF0_BURST_LEN_SHIFT) | + (XAVBUF_CHBUF0_FLUSH_MASK); + + for (Index = 0; Index <= NumPlanes; Index++) { + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, + XAVBUF_CHBUF0 + (Index * 4), RegVal); + } + if(Enable) { + RegVal = (0xF << XAVBUF_CHBUF0_BURST_LEN_SHIFT) | + XAVBUF_CHBUF0_EN_MASK; + for (Index = 0; Index <= NumPlanes; Index++) { + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, + XAVBUF_CHBUF0 + (Index * 4), RegVal); + } + } +} +/******************************************************************************/ +/** + * This function enables the graphics interface between the DPDMA and the AVBuf. + * + * @param InstancePtr is a pointer to the XAVBuf Instance. + * @param Enable sets the corresponding buffers. + * + * @returns None. + * + * @note None. + * + ******************************************************************************/ +void XAVBuf_EnableGraphicsBuffers(XAVBuf *InstancePtr, u8 Enable) +{ + u32 RegVal = 0; + + RegVal = (0xF << XAVBUF_CHBUF3_BURST_LEN_SHIFT) | + XAVBUF_CHBUF3_FLUSH_MASK; + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, XAVBUF_CHBUF3, RegVal); + if(Enable) { + RegVal = (0xF << XAVBUF_CHBUF3_BURST_LEN_SHIFT) | + XAVBUF_CHBUF0_EN_MASK; + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, XAVBUF_CHBUF3, + RegVal); + } +} + +/******************************************************************************/ +/** + * This function enables the audio interface between the DPDMA and the AVBuf + * + * @param InstancePtr is a pointer to the XAVBuf Instance. + * @param Enable sets the corresponding buffers. + * + * @returns None. + * + * @note None. + * + ******************************************************************************/ +void XAVBuf_EnableAudio0Buffers(XAVBuf *InstancePtr, u8 Enable) +{ + u32 RegVal = 0; + + RegVal = (0x3 << XAVBUF_CHBUF4_BURST_LEN_SHIFT) | + XAVBUF_CHBUF4_FLUSH_MASK; + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, XAVBUF_CHBUF4, RegVal); + if(Enable) { + RegVal = (0x3 << XAVBUF_CHBUF4_BURST_LEN_SHIFT) | + XAVBUF_CHBUF4_EN_MASK; + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, XAVBUF_CHBUF4, + RegVal); + } +} + +/******************************************************************************/ +/** + * This function enables the audio interface between the DPDMA and the AVBuf + * + * @param InstancePtr is a pointer to the XAVBuf Instance. + * @param Enable sets the corresponding buffers. + * + * @returns None. + * + * @note None. + * + ******************************************************************************/ +void XAVBuf_EnableAudio1Buffers(XAVBuf *InstancePtr, u8 Enable) +{ + u32 RegVal = 0; + + RegVal = (0x3 << XAVBUF_CHBUF5_BURST_LEN_SHIFT) | + XAVBUF_CHBUF5_FLUSH_MASK; + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, XAVBUF_CHBUF5, RegVal); + if(Enable) { + RegVal = (0x3 << XAVBUF_CHBUF5_BURST_LEN_SHIFT) | + XAVBUF_CHBUF5_EN_MASK; + XAVBuf_WriteReg(InstancePtr->Config.BaseAddr, XAVBUF_CHBUF5, + RegVal); + } +} diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/avbuf_v2_1/src/xavbuf.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/avbuf_v2_1/src/xavbuf.h new file mode 100644 index 000000000..386bfbaa9 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/avbuf_v2_1/src/xavbuf.h @@ -0,0 +1,302 @@ +/******************************************************************************* + * + * Copyright (C) 2017 Xilinx, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * Use of the Software is limited solely to applications: + * (a) running on a Xilinx device, or + * (b) that interact with a Xilinx device through a bus or interconnect. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of the Xilinx shall not be used + * in advertising or otherwise to promote the sale, use or other dealings in + * this Software without prior written authorization from Xilinx. + * +*******************************************************************************/ +/******************************************************************************/ +/** + * + * @file xavbuf.h + * + * This file implements all the functions related to the Video Pipeline of the + * DisplayPort Subsystem. + * + * Features supported by this driver + * - Live Video and Graphics input. + * - Non-Live Video Graphics input. + * - Output Formats Supported - RGB, YUV444, YUV4222. + * + * + * 
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -----------------------------------------------
+ * 1.0   aad  06/24/17 Initial release.
+ * 2.0   aad  10/07/17 Added Enums for Video and Audio sources.
+ *
+ * +*******************************************************************************/ +#ifndef XAVBUF_H_ +/* Prevent circular inclusions by using protection macros. */ +#define XAVBUF_H_ + + +/******************************* Include Files ********************************/ +#include "xavbuf_hw.h" +#include "sleep.h" +/****************************** Type Definitions ******************************/ +/** + * This typedef describes all the Video Formats supported by the driver + */ +typedef enum { + //Non-Live Video Formats + CbY0CrY1, + CrY0CbY1, + Y0CrY1Cb, + Y0CbY1Cr, + YV16, + YV24, + YV16Ci, + MONOCHROME, + YV16Ci2, + YUV444, + RGB888, + RGBA8880, + RGB888_10BPC, + YUV444_10BPC, + YV16Ci2_10BPC, + YV16Ci_10BPC, + YV16_10BPC, + YV24_10BPC, + MONOCHROME_10BPC, + YV16_420, + YV16Ci_420, + YV16Ci2_420, + YV16_420_10BPC, + YV16Ci_420_10BPC, + YV16Ci2_420_10BPC, + + // Non-Live Graphics formats + RGBA8888, + ABGR8888, + RGB888_GFX, + BGR888, + RGBA5551, + RGBA4444, + RGB565, + BPP8, + BPP4, + BPP2, + BPP1, + YUV422, + YOnly, + + //Live Input/Output Video/Graphics Formats + RGB_6BPC, + RGB_8BPC, + RGB_10BPC, + RGB_12BPC, + YCbCr444_6BPC, + YCbCr444_8BPC, + YCbCr444_10BPC, + YCbCr444_12BPC, + YCbCr422_8BPC, + YCbCr422_10BPC, + YCbCr422_12BPC, + YOnly_8BPC, + YOnly_10BPC, + YOnly_12BPC, +} XAVBuf_VideoFormat; + +/** + * This data structure describes video planes. + */ +typedef enum { + Interleaved, + SemiPlanar, + Planar +} XAVBuf_VideoModes; + +/** + * This typedef describes the video source list + */ +typedef enum { + XAVBUF_VIDSTREAM1_LIVE, + XAVBUF_VIDSTREAM1_NONLIVE, + XAVBUF_VIDSTREAM1_TPG, + XAVBUF_VIDSTREAM1_NONE, +} XAVBuf_VideoStream; + +/** + * This typedef describes the graphics source list + */ +typedef enum { + XAVBUF_VIDSTREAM2_DISABLEGFX = 0x0, + XAVBUF_VIDSTREAM2_NONLIVE_GFX = 0x4, + XAVBUF_VIDSTREAM2_LIVE_GFX = 0x8, + XAVBUF_VIDSTREAM2_NONE = 0xC0, +} XAVBuf_GfxStream; + +/** + * This typedef describes the audio stream 1 source list + */ +typedef enum { + XAVBUF_AUDSTREAM1_LIVE = 0x00, + XAVBUF_AUDSTREAM1_NONLIVE = 0x10, + XAVBUF_AUDSTREAM1_TPG = 0x20, + XAVBUF_AUDSTREAM1_NO_AUDIO = 0x30, +} XAVBuf_AudioStream1; + +/** + * This typedef describes the audio stream 2 source list + */ +typedef enum { + XAVBUF_AUDSTREAM2_NO_AUDIO = 0X00, + XAVBUF_AUDSTREAM2_AUDIOGFX = 0X40, +} XAVBuf_AudioStream2; + +/** + * This typedef describes the attributes associated with the video formats. + */ +typedef struct { + XAVBuf_VideoFormat VideoFormat; + u8 Value; + XAVBuf_VideoModes Mode; + u32 SF[3]; + u8 SamplingEn; + u8 IsRGB; + u8 Swap; + u8 BPP; +} XAVBuf_VideoAttribute; + +/** + * This typedef stores the attributes of an audio stream + */ +typedef struct { + u32 Volume; + u8 SwapLR; +} XAVBuf_AudioAttribute; + +/** + * This typedef stores the data associated with the Audio Video input modes. + */ +typedef struct { + XAVBuf_VideoAttribute *NonLiveVideo, *NonLiveGraphics; + XAVBuf_VideoAttribute *LiveVideo, *LiveGraphics; + XAVBuf_AudioAttribute *Audio, *GraphicsAudio; + XAVBuf_VideoStream VideoSrc; + XAVBuf_GfxStream GraphicsSrc; + XAVBuf_AudioStream1 AudioSrc1; + XAVBuf_AudioStream2 AudioSrc2; + u8 AudioClk, VideoClk; +} XAVBuf_AVModes; + +/** + * This structure stores the background color information. + */ +typedef struct { + u16 RCr; + u16 GY; + u16 BCb; +} XAVBuf_BlenderBgClr; + +/** + * This typedef stores the AVBuf Configuration information. + */ +typedef struct { + u16 DeviceId; + u32 BaseAddr; +} XAVBuf_Config; + +/** + * This typedef stores all the attributes associated to the Blender block of the + * DisplayPort Subsystem + */ +typedef struct { + u8 GlobalAlphaEn; + u8 Alpha; + XAVBuf_VideoAttribute *OutputVideo; +} XAVBuf_Blender; + +/** + * The XAVBuf driver instance data. The user is required to allocate a variable + * of this type for every XAVBUF instance in the system. A pointer to this type + * is then passed to the driver API functions + */ +typedef struct { + XAVBuf_Config Config; + XAVBuf_AVModes AVMode; + XAVBuf_Blender Blender; +} XAVBuf; + + +/**************************** Function Prototypes *****************************/ + +/* xavbuf.c: Setup and initialization functions. */ +void XAVBuf_CfgInitialize(XAVBuf *InstancePtr, u32 BaseAddr, u16 DeviceId); + +/* xavbuf.c: Functions to setup the Input Video and Audio sources */ +void XAVBuf_InputVideoSelect(XAVBuf *InstancePtr, XAVBuf_VideoStream VidStream, + XAVBuf_GfxStream GfxStream); +void XAVBuf_InputAudioSelect(XAVBuf *InstancePtr, XAVBuf_AudioStream1 AudStream, + XAVBuf_AudioStream2 AudioStream2); + +/* xavbuf.c: Functions to setup the Video Format attributes */ +int XAVBuf_SetInputNonLiveVideoFormat(XAVBuf *InstancePtr, + XAVBuf_VideoFormat Format); +int XAVBuf_SetInputNonLiveGraphicsFormat(XAVBuf *InstancePtr, + XAVBuf_VideoFormat Format); +int XAVBuf_SetInputLiveVideoFormat(XAVBuf *InstancePtr, + XAVBuf_VideoFormat Format); +int XAVBuf_SetInputLiveGraphicsFormat(XAVBuf *InstancePtr, + XAVBuf_VideoFormat Format); +int XAVBuf_SetOutputVideoFormat(XAVBuf *InstancePtr, XAVBuf_VideoFormat Format); +XAVBuf_VideoAttribute *XAVBuf_GetLiveVideoAttribute(XAVBuf_VideoFormat Format); +XAVBuf_VideoAttribute *XAVBuf_GetNLiveVideoAttribute(XAVBuf_VideoFormat Format); +XAVBuf_VideoAttribute *XAVBuf_GetNLGraphicsAttribute(XAVBuf_VideoFormat Format); + +/* xavbuf.c: Functions to setup the clock sources for video and audio */ +void XAVBuf_SetAudioVideoClkSrc(XAVBuf *InstancePtr, u8 VideoClk, u8 AudioClk); + +/* xavbuf.c: Functions that setup Video and Graphics pipeline depending on the + * sources and format selected. + */ +void XAVBuf_ConfigureVideoPipeline(XAVBuf *InstancePtr); +void XAVBuf_ConfigureGraphicsPipeline(XAVBuf *InstancePtr); + +/* Functions to setup Blender Properties */ +void XAVBuf_BlendSetBgColor(XAVBuf *InstancePtr, XAVBuf_BlenderBgClr *Color); +void XAVBuf_SetBlenderAlpha(XAVBuf *InstancePtr, u8 Alpha, u8 Enable); +void XAVBuf_SoftReset(XAVBuf *InstancePtr); +void XABuf_LineResetDisable(XAVBuf *InstancePtr, u8 Disable); +void XAVBuf_ConfigureOutputVideo(XAVBuf *InstancePtr); + +/* Audio Configuration functions */ +void XAVBuf_AudioSoftReset(XAVBuf *InstancePtr); +void XAVBuf_AudioMixerVolumeControl(XAVBuf *InstancePtr, u8 Channel0Volume, + u8 Channel1Volume); + +/* DPDMA Interface functions */ +void XAVBuf_EnableGraphicsBuffers(XAVBuf *InstancePtr, u8 Enable); +void XAVBuf_EnableVideoBuffers(XAVBuf *InstancePtr, u8 Enable); +void XAVBuf_EnableAudio0Buffers(XAVBuf *InstancePtr, u8 Enable); +void XAVBuf_EnableAudio1Buffers(XAVBuf *InstancePtr, u8 Enable); + +#endif //XAVBUF_H_ diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/avbuf_v2_1/src/xavbuf_clk.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/avbuf_v2_1/src/xavbuf_clk.c new file mode 100644 index 000000000..6ef5d7089 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/avbuf_v2_1/src/xavbuf_clk.c @@ -0,0 +1,561 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/******************************************************************************/ +/** + * + * @file xavbuf.c + * + * This header file contains PLL configuring functions. These Functions + * calculates and configures the PLL depending on desired frequency. + * + * @note None. + * + * 
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -----------------------------------------------
+ * 1.0   mh  06/24/17 Initial release.
+ * 2.1   tu  12/29/17 LPD and FPD offsets adjusted
+ *
+ * +*******************************************************************************/ +/******************************* Include Files ********************************/ +#include "xavbuf_clk.h" + +/**************************** Constant Definitions ****************************/ +/*Input Frequency for the PLL with precision upto two decimals*/ +#define XAVBUF_INPUT_REF_CLK 3333333333 + +/*Frequency of VCO before divider to meet jitter requirement*/ +#define XAVBUF_PLL_OUT_FREQ 1450000000 + +/* Precision of Input Ref Frequency for PLL*/ +#define XAVBUF_INPUT_FREQ_PRECISION 100 + +/* 16 bit fractional shift to get Integer */ +#define XAVBUF_PRECISION 16 +#define XAVBUF_SHIFT_DECIMAL (1 << XAVBUF_PRECISION) +#define XAVBUF_DECIMAL (XAVBUF_SHIFT_DECIMAL - 1) +#define XDPSSU_MAX_VIDEO_FREQ 300000000 + +#define XAVBUF_AUDIO_SAMPLES 512 +#define XAVBUF_AUDIO_SAMPLE_RATE_44_1 44100 +#define XAVBUF_AUDIO_SAMPLE_RATE_48_0 48000 +#define XAVBUF_EXTERNAL_DIVIDER 2 + +/* Register offsets for address manipulation */ +#define XAVBUF_REG_OFFSET 4 +#define XAVBUF_FPD_CTRL_OFFSET 12 +#define XAVBUF_LPD_CTRL_OFFSET 16 +#define MOD_3(a) ((a) % (3)) + +/*************************** Constant Variable Definitions ********************/ +/** + * This typedef enumerates capacitor resistor and lock values to be programmed. + */ +typedef struct{ + u16 cp; + u16 res; + u16 lfhf; + u16 lock_dly; + u16 lock_cnt; +}PllConfig; + +/* PLL fractional divide programming table*/ +static const PllConfig PllFracDivideTable[] = { + {3, 5, 3, 63, 1000}, + {3, 5, 3, 63, 1000}, + {3, 9, 3, 63, 1000}, + {3, 9, 3, 63, 1000}, + {3, 9, 3, 63, 1000}, + {3, 9, 3, 63, 1000}, + {3, 14, 3, 63, 1000}, + {3, 14, 3, 63, 1000}, + {3, 14, 3, 63, 1000}, + {3, 14, 3, 63, 1000}, + {3, 14, 3, 63, 1000}, + {3, 14, 3, 63, 1000}, + {3, 14, 3, 63, 1000}, + {3, 14, 3, 63, 975}, + {3, 14, 3, 63, 950}, + {3, 14, 3, 63, 925}, + {3, 1, 3, 63, 900}, + {3, 1, 3, 63, 875}, + {3, 1, 3, 63, 850}, + {3, 1, 3, 63, 850}, + {3, 1, 3, 63, 825}, + {3, 1, 3, 63, 800}, + {3, 1, 3, 63, 775}, + {3, 6, 3, 63, 775}, + {3, 6, 3, 63, 750}, + {3, 6, 3, 63, 725}, + {3, 6, 3, 63, 700}, + {3, 6, 3, 63, 700}, + {3, 6, 3, 63, 675}, + {3, 6, 3, 63, 675}, + {3, 6, 3, 63, 650}, + {3, 6, 3, 63, 650}, + {3, 6, 3, 63, 625}, + {3, 6, 3, 63, 625}, + {3, 6, 3, 63, 625}, + {3, 6, 3, 63, 600}, + {3, 6, 3, 63, 600}, + {3, 6, 3, 63, 600}, + {3, 6, 3, 63, 600}, + {3, 6, 3, 63, 600}, + {3, 10, 3, 63, 600}, + {3, 10, 3, 63, 600}, + {3, 10, 3, 63, 600}, + {3, 10, 3, 63, 600}, + {3, 10, 3, 63, 600}, + {3, 10, 3, 63, 600}, + {3, 10, 3, 63, 600}, + {3, 10, 3, 63, 600}, + {3, 10, 3, 63, 600}, + {3, 10, 3, 63, 600}, + {3, 10, 3, 63, 600}, + {3, 10, 3, 63, 600}, + {3, 10, 3, 63, 600}, + {3, 10, 3, 63, 600}, + {3, 10, 3, 63, 600}, + {3, 10, 3, 63, 600}, + {4, 6, 3, 63, 600}, + {4, 6, 3, 63, 600}, + {4, 6, 3, 63, 600}, + {4, 6, 3, 63, 600}, + {4, 6, 3, 63, 600}, + {4, 6, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600}, + {3, 12, 3, 63, 600} +}; + +/******************************************************************************/ +/** + * This function initializes the parameters required to configure PLL. + * + * @param PllInstancePtr is pointer to the XAVBuf_Pll instance. + * @param Pll is the PLL chosen to be configured. + * @param Pll is the PLL chosen to be configured. + * @param CrossDomain is the bool which is used to mention if the PLL + * outputs in other domain. + * @param ExtDividerCnt is number of external divider out of VCO. + * + * @return XST_SUCCESS if PLL is configured without an error. + * XST_FAILURE otherwise. + * + * @note In order to avoid floating point usage we have a 16bit + * fractional fixed point arithmetic implementation + * +*******************************************************************************/ +static void XAVBuf_PllInitialize(XAVBuf_Pll *PllInstancePtr, + u8 Pll, u8 CrossDomain , u8 ExtDividerCnt) +{ + /* Instantiate input frequency. */ + PllInstancePtr->InputRefClk = XAVBUF_Pss_Ref_Clk; + PllInstancePtr->RefClkFreqhz = XAVBUF_INPUT_REF_CLK; + /* Turn on internal Divider*/ + PllInstancePtr->Divider = 1; + PllInstancePtr->Pll = Pll; + PllInstancePtr->ExtDividerCnt = ExtDividerCnt; + + //Check if CrossDomain is requested + if(CrossDomain) + PllInstancePtr->DomainSwitchDiv = 6; + else + PllInstancePtr->DomainSwitchDiv = 1; + //Check where PLL falls + if (Pll>2){ + PllInstancePtr->Fpd = 0; + PllInstancePtr->BaseAddress = XAVBUF_CLK_LPD_BASEADDR; + PllInstancePtr->Offset = XAVBUF_LPD_CTRL_OFFSET; + } + else{ + PllInstancePtr->Fpd = 1; + PllInstancePtr->BaseAddress = XAVBUF_CLK_FPD_BASEADDR; + PllInstancePtr->Offset = XAVBUF_FPD_CTRL_OFFSET; + } + +} + +/******************************************************************************/ +/** + * This function calculates the parameters which are required to configure PLL + * depending upon the requested frequency. + * + * @param PllInstancePtr is pointer to the XAVBuf_Pll instance + * @param FreqHz is the requested frequency to DP in Hz + * + * @return XST_SUCCESS if parameters are calculated + * XST_FAILURE otherwise. + * + * @note In order to avoid floating point usage we have a 16bit + * fractional fixed point arithmetic implementation + * +*******************************************************************************/ +static int XAVBuf_PllCalcParameterValues(XAVBuf_Pll *PllInstancePtr, + u64 FreqHz) +{ + u64 ExtDivider, Vco, VcoIntFrac; + + /* Instantiate input frequency. */ + PllInstancePtr->InputRefClk = XAVBUF_Pss_Ref_Clk; + PllInstancePtr->RefClkFreqhz = XAVBUF_INPUT_REF_CLK ; + /* Turn on internal Divider*/ + PllInstancePtr->Divider = 1; + PllInstancePtr->DomainSwitchDiv = 1; + + /* Estimate the total divider. */ + ExtDivider = (XAVBUF_PLL_OUT_FREQ / FreqHz) / + PllInstancePtr->DomainSwitchDiv; + if(ExtDivider > 63 && PllInstancePtr->ExtDividerCnt == 2){ + PllInstancePtr->ExtDivider0 = 63; + PllInstancePtr->ExtDivider1 = ExtDivider / 63; + } + else if(ExtDivider < 63){ + PllInstancePtr->ExtDivider0 = ExtDivider; + PllInstancePtr->ExtDivider1 = 1; + } + else + return XST_FAILURE; + + Vco = FreqHz *(PllInstancePtr->ExtDivider1 * + PllInstancePtr->ExtDivider0 * 2) * + PllInstancePtr->DomainSwitchDiv; + /* Calculate integer and fractional part. */ + VcoIntFrac = (Vco * XAVBUF_INPUT_FREQ_PRECISION * + XAVBUF_SHIFT_DECIMAL) / + PllInstancePtr->RefClkFreqhz ; + PllInstancePtr->Fractional = VcoIntFrac & XAVBUF_DECIMAL; + PllInstancePtr->FracIntegerFBDIV = VcoIntFrac >> XAVBUF_PRECISION; + + return XST_SUCCESS; +} + +/******************************************************************************/ +/** + * This function will Read modify and write into corresponding registers. + * + * @param BaseAddress is the base address to which the value has to be + * written. + * @param RegOffset is the relative offset from Base address. + * @param Mask is used to select the number of bits to be modified. + * @param Shift is the number bits to be shifted from LSB. + * @param Data is the Data to be written. + * + * @return None. + * + * @note None. + * +*******************************************************************************/ +static void XAVBuf_ReadModifyWriteReg(u32 BaseAddress, u32 RegOffset, u32 Mask, + u32 Shift, u32 Data) +{ + u32 RegValue; + + RegValue = XAVBuf_ReadReg(BaseAddress, RegOffset); + RegValue = (RegValue & ~Mask) | (Data << Shift); + XAVBuf_WriteReg(BaseAddress, RegOffset, RegValue); +} + +/******************************************************************************/ +/** + * This function configures PLL. + * + * @param PllInstancePtr is pointer to the XAVBuf_Pll instance. + * + * @return XST_SUCCESS if PLL is configured without an error. + * XST_FAILURE otherwise. + * + * @note None. + * +*******************************************************************************/ +static int XAVBuf_ConfigurePll(XAVBuf_Pll *PllInstancePtr) +{ + u64 BaseAddress = PllInstancePtr->BaseAddress; + u64 timer = 0; + u32 RegPll = 0; + u8 Pll = PllInstancePtr->Pll; + + RegPll |= XAVBUF_ENABLE_BIT << XAVBUF_PLL_CTRL_BYPASS_SHIFT; + RegPll |= PllInstancePtr->FracIntegerFBDIV << + XAVBUF_PLL_CTRL_FBDIV_SHIFT; + RegPll |= PllInstancePtr->Divider << XAVBUF_PLL_CTRL_DIV2_SHIFT; + RegPll |= PllInstancePtr->InputRefClk << XAVBUF_PLL_CTRL_PRE_SRC_SHIFT; + XAVBuf_WriteReg(BaseAddress, XAVBUF_PLL_CTRL + (MOD_3(Pll) * + PllInstancePtr->Offset), RegPll); + RegPll = 0; + /* Set the values for lock dly, lock counter, capacitor and resistor. */ + RegPll |= + PllFracDivideTable[PllInstancePtr->FracIntegerFBDIV -25].cp + << XAVBUF_PLL_CFG_CP_SHIFT; + RegPll |= + PllFracDivideTable[PllInstancePtr->FracIntegerFBDIV -25].res + << XAVBUF_PLL_CFG_RES_SHIFT; + RegPll |= + PllFracDivideTable[PllInstancePtr->FracIntegerFBDIV -25].lfhf + << XAVBUF_PLL_CFG_LFHF_SHIFT; + RegPll |= + PllFracDivideTable[PllInstancePtr->FracIntegerFBDIV -25].lock_dly + << XAVBUF_PLL_CFG_LOCK_DLY_SHIFT; + RegPll |= + PllFracDivideTable[PllInstancePtr->FracIntegerFBDIV -25].lock_cnt + << XAVBUF_PLL_CFG_LOCK_CNT_SHIFT; + XAVBuf_WriteReg(BaseAddress, XAVBUF_PLL_CFG + (MOD_3(Pll) * + PllInstancePtr->Offset), RegPll); + /* Enable and set Fractional Data. */ + XAVBuf_WriteReg(BaseAddress, XAVBUF_PLL_FRAC_CFG + (MOD_3(Pll) * + PllInstancePtr->Offset), (1 << XAVBUF_PLL_FRAC_CFG_ENABLED_SHIFT) | + (PllInstancePtr->Fractional << + XAVBUF_PLL_FRAC_CFG_DATA_SHIFT)); + /* Assert reset to the PLL. */ + XAVBuf_ReadModifyWriteReg(BaseAddress, XAVBUF_PLL_CTRL + (MOD_3(Pll) * + PllInstancePtr->Offset), + XAVBUF_PLL_CTRL_RESET_MASK, XAVBUF_PLL_CTRL_RESET_SHIFT, + XAVBUF_ENABLE_BIT); + + /* Deassert reset to the PLL. */ + XAVBuf_ReadModifyWriteReg(BaseAddress, XAVBUF_PLL_CTRL + (MOD_3(Pll) * + PllInstancePtr->Offset), + XAVBUF_PLL_CTRL_RESET_MASK, XAVBUF_PLL_CTRL_RESET_SHIFT, + XAVBUF_DISABLE_BIT); + + while(!(XAVBuf_ReadReg(BaseAddress, XAVBUF_PLL_STATUS - + ((1 - PllInstancePtr->Fpd) * XAVBUF_REG_OFFSET)) & + (1 << MOD_3(Pll)))) + if(++timer > 1000) + return XST_FAILURE; + + /* Deassert Bypass. */ + XAVBuf_ReadModifyWriteReg(BaseAddress, XAVBUF_PLL_CTRL + (MOD_3(Pll) * + PllInstancePtr->Offset), + XAVBUF_PLL_CTRL_BYPASS_MASK, XAVBUF_PLL_CTRL_BYPASS_SHIFT, + XAVBUF_DISABLE_BIT); + + if(PllInstancePtr->DomainSwitchDiv != 1) + XAVBuf_ReadModifyWriteReg(BaseAddress, (XAVBUF_DOMAIN_SWITCH_CTRL + + (MOD_3(Pll) * XAVBUF_REG_OFFSET) - ((1 - PllInstancePtr->Fpd) + * XAVBUF_REG_OFFSET)), + XAVBUF_DOMAIN_SWITCH_DIVISOR0_MASK, + XAVBUF_DOMAIN_SWITCH_DIVISOR0_SHIFT, + PllInstancePtr->DomainSwitchDiv); + usleep(1); + + return XST_SUCCESS; + +} + +/******************************************************************************/ +/** + * This function configures Configures external divider. + * + * @param PllInstancePtr is pointer to the XAVBuf_Pll instance. + * + * @return None. + * + * @note None. + * +*******************************************************************************/ +static void XAVBuf_ConfigureExtDivider(XAVBuf_Pll *PllInstancePtr, + u64 BaseAddress, u32 Offset) +{ + XAVBuf_ReadModifyWriteReg(BaseAddress, Offset, + XAVBUF_VIDEO_REF_CTRL_CLKACT_MASK, + XAVBUF_VIDEO_REF_CTRL_CLKACT_SHIFT, XAVBUF_DISABLE_BIT); + XAVBuf_ReadModifyWriteReg(BaseAddress, Offset, + XAVBUF_VIDEO_REF_CTRL_DIVISOR1_MASK, + XAVBUF_VIDEO_REF_CTRL_DIVISOR1_SHIFT, + PllInstancePtr->ExtDivider1); + XAVBuf_ReadModifyWriteReg(BaseAddress, Offset, + XAVBUF_VIDEO_REF_CTRL_DIVISOR0_MASK, + XAVBUF_VIDEO_REF_CTRL_DIVISOR0_SHIFT, + PllInstancePtr->ExtDivider0); + XAVBuf_ReadModifyWriteReg(BaseAddress, Offset, + XAVBUF_VIDEO_REF_CTRL_CLKACT_MASK, + XAVBUF_VIDEO_REF_CTRL_CLKACT_SHIFT, XAVBUF_ENABLE_BIT); + XAVBuf_WriteReg(BaseAddress, Offset, 0x1011003); +} + +/******************************************************************************/ +/** + * This function calls API to calculate and configure PLL with desired frequency + * for Video. + * + * @param FreqHz is the desired frequency in Hz. + * + * @return XST_SUCCESS if PLL is configured without an error. + * XST_FAILURE otherwise. + * + * @note The Pll used is design specific. + * +*******************************************************************************/ +int XAVBuf_SetPixelClock(u64 FreqHz) +{ + u32 PllAssigned; + XAVBuf_Pll PllInstancePtr; + u8 Pll, CrossDomain, Flag; + + /*Verify Input Arguments*/ + Xil_AssertNonvoid(FreqHz < XDPSSU_MAX_VIDEO_FREQ); + + PllAssigned = XAVBuf_ReadReg(XAVBUF_CLK_FPD_BASEADDR, + XAVBUF_VIDEO_REF_CTRL) & XAVBUF_VIDEO_REF_CTRL_SRCSEL_MASK; + + switch (PllAssigned) { + case XAVBUF_VPLL_SRC_SEL: + Pll = VPLL; + CrossDomain = 0; + break; + case XAVBUF_DPLL_SRC_SEL: + Pll = DPLL; + CrossDomain = 0; + break; + case XAVBUF_RPLL_TO_FPD_SRC_SEL: + Pll = RPLL; + CrossDomain = 1; + break; + default: + return XST_FAILURE; + } + + /*Calculate configure PLL and External Divider*/ + XAVBuf_PllInitialize(&PllInstancePtr, Pll, CrossDomain, + XAVBUF_EXTERNAL_DIVIDER); + Flag = XAVBuf_PllCalcParameterValues(&PllInstancePtr, FreqHz); + if(Flag != 0) + return XST_FAILURE; + Flag = XAVBuf_ConfigurePll(&PllInstancePtr); + if(Flag != 0) + return XST_FAILURE; + XAVBuf_ConfigureExtDivider(&PllInstancePtr, XAVBUF_CLK_FPD_BASEADDR, + XAVBUF_VIDEO_REF_CTRL); + + return XST_SUCCESS; +} + +/******************************************************************************/ +/** + * This function calls API to calculate and configure PLL with desired + * frequency for Audio. + * + * @param FreqHz is the desired frequency in Hz. + * + * @return XST_SUCCESS if PLL is configured without an error. + * XST_FAILURE otherwise. + * + * @note The Pll used is design specific. + * +*******************************************************************************/ +int XAVBuf_SetAudioClock(u64 FreqHz) +{ + u32 Flag, PllAssigned; + u8 Pll, CrossDomain; + XAVBuf_Pll XAVBuf_RPllInstancePtr; + + /*Verify Input Arguments*/ + Flag = (FreqHz == (XAVBUF_AUDIO_SAMPLE_RATE_44_1 * + XAVBUF_AUDIO_SAMPLES)) || + (FreqHz == (XAVBUF_AUDIO_SAMPLE_RATE_48_0 * + XAVBUF_AUDIO_SAMPLES)); + Xil_AssertNonvoid(Flag); + + PllAssigned = XAVBuf_ReadReg(XAVBUF_CLK_FPD_BASEADDR, + XAVBUF_AUDIO_REF_CTRL) & + XAVBUF_AUDIO_REF_CTRL_SRCSEL_MASK; + + switch (PllAssigned) { + case XAVBUF_VPLL_SRC_SEL: + Pll = VPLL; + CrossDomain = 0; + break; + case XAVBUF_DPLL_SRC_SEL: + Pll = DPLL; + CrossDomain = 0; + break; + case XAVBUF_RPLL_TO_FPD_SRC_SEL: + Pll = RPLL; + CrossDomain = 1; + break; + default: + return XST_FAILURE; + } + + /*Calculate configure PLL and External Divider*/ + XAVBuf_PllInitialize(&XAVBuf_RPllInstancePtr, Pll, CrossDomain, + XAVBUF_EXTERNAL_DIVIDER); + Flag = XAVBuf_PllCalcParameterValues(&XAVBuf_RPllInstancePtr, FreqHz); + if(Flag != 0) + return XST_FAILURE; + Flag = XAVBuf_ConfigurePll(&XAVBuf_RPllInstancePtr); + if(Flag != 0) + return XST_FAILURE; + XAVBuf_ConfigureExtDivider(&XAVBuf_RPllInstancePtr, + XAVBUF_CLK_FPD_BASEADDR, XAVBUF_AUDIO_REF_CTRL); + + return XST_SUCCESS; +} diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/avbuf_v2_1/src/xavbuf_clk.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/avbuf_v2_1/src/xavbuf_clk.h new file mode 100644 index 000000000..91ca3b5ed --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/avbuf_v2_1/src/xavbuf_clk.h @@ -0,0 +1,97 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/******************************************************************************/ +/** + * + * @file xavbuf_clk.h + * + * This header file contains the identifiers and low-level driver functions (or + * macros) that can be used to configure PLL to generate required frequency. + * + * @note None. + * + * 
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -----------------------------------------------
+ * 1.0   mh  06/24/17 Initial release.
+ * 2.1   tu  12/29/17 LPD and FPD offsets adjusted
+ *
+ * +*******************************************************************************/ + +#ifndef XAVBUF_CLK_H_ +#define XAVBUF_CLK_H_ + +/******************************* Include Files ********************************/ +#include "xavbuf_hw.h" +#include "xstatus.h" +#include "sleep.h" + +/****************************** Type Definitions ******************************/ +/** + * This enum enumerates various PLL + */ +enum PLL{ + APLL = 0, + DPLL = 1, + VPLL = 2, + IOPLL = 3, + RPLL = 4 +}; + +/** + * This typedef enumerates various variables used to configure Pll + */ +typedef struct { + u64 BaseAddress; + u64 Fractional; + u64 RefClkFreqhz; + u32 Divider; + u8 Offset; + u8 ClkDividBy2; + u8 ExtDivider0; + u8 ExtDivider1; + u8 ExtDividerCnt; + u8 DomainSwitchDiv; + u8 FracIntegerFBDIV; + u8 IntegerFBDIV; + u8 InputRefClk; + u8 Fpd; + u8 Pll; +}XAVBuf_Pll; + +/**************************** Function Prototypes *****************************/ +int XAVBuf_SetPixelClock(u64 FreqHz); +int XAVBuf_SetAudioClock(u64 FreqHz); +#endif /* XAVBUF_CLK_H_ */ diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/avbuf_v2_1/src/xavbuf_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/avbuf_v2_1/src/xavbuf_g.c new file mode 100644 index 000000000..325e01b47 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/avbuf_v2_1/src/xavbuf_g.c @@ -0,0 +1,55 @@ + +/******************************************************************* +* +* CAUTION: This file is automatically generated by HSI. +* Version: +* DO NOT EDIT. +* +* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.* +*Permission is hereby granted, free of charge, to any person obtaining a copy +*of this software and associated documentation files (the Software), to deal +*in the Software without restriction, including without limitation the rights +*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +*copies of the Software, and to permit persons to whom the Software is +*furnished to do so, subject to the following conditions: +* +*The above copyright notice and this permission notice shall be included in +*all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +*(a) running on a Xilinx device, or +*(b) that interact with a Xilinx device through a bus or interconnect. +* +*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +* +*Except as contained in this notice, the name of the Xilinx shall not be used +*in advertising or otherwise to promote the sale, use or other dealings in +*this Software without prior written authorization from Xilinx. +* + +* +* Description: Driver configuration +* +*******************************************************************/ + +#include "xparameters.h" +#include "xavbuf.h" + +/* +* The configuration table for devices +*/ + +XAVBuf_Config XAVBuf_ConfigTable[XPAR_XAVBUF_NUM_INSTANCES] = +{ + { + XPAR_PSU_DP_DEVICE_ID, + XPAR_PSU_DP_BASEADDR + } +}; + + diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/avbuf_v2_1/src/xavbuf_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/avbuf_v2_1/src/xavbuf_hw.h new file mode 100644 index 000000000..3454fa071 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/avbuf_v2_1/src/xavbuf_hw.h @@ -0,0 +1,1675 @@ +/******************************************************************************* + * + * Copyright C 2014 Xilinx, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * Use of the Software is limited solely to applications: + * (a) running on a Xilinx device, or + * (b) that interact with a Xilinx device through a bus or interconnect. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of the Xilinx shall not be used + * in advertising or otherwise to promote the sale, use or other dealings in + * this Software without prior written authorization from Xilinx. + * +*******************************************************************************/ +/******************************************************************************/ +/** + * + * @file xavbuf_hw.h + * + * This header file contains macros that can be used to access the device + * + * @note None. + * + * 
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -----------------------------------------------
+ * 1.0	 aad 02/24/17	Initial Release
+ * 1.0   mh  06/24/17	Added Clock related register information
+ * 2.0   aad 10/07/17   Removed Macros related to Video and Audio Src
+ *
+ * +*******************************************************************************/ +#ifndef XAVBUF_HW_H_ +/* Prevent circular inclusions by using protection macros. */ +#define XAVBUF_HW_H_ + +#ifdef __cplusplus +extern "C" { +#endif +/***************************** Include Files **********************************/ + +#include "xil_io.h" +#include "xil_types.h" + +/************************** Constant Definitions ******************************/ + +/******************************************************************************/ +/** + * Address mapping for the DisplayPort TX core. + * +*******************************************************************************/ + +#define XAVBUF_BASEADDR 0xFD4A0000 +/** + * * Register: XAVBUF_V_BLEND_BG_CLR_0 + * */ +#define XAVBUF_V_BLEND_BG_CLR_0 0X0000A000 + +#define XAVBUF_V_BLEND_BG_CLR_0_CLR0_SHIFT 0 +#define XAVBUF_V_BLEND_BG_CLR_0_CLR0_WIDTH 12 +#define XAVBUF_V_BLEND_BG_CLR_0_CLR0_MASK 0X00000FFF + +/** + * * Register: XAVBUF_V_BLEND_BG_CLR_1 + * */ +#define XAVBUF_V_BLEND_BG_CLR_1 0X0000A004 + +#define XAVBUF_V_BLEND_BG_CLR_1_CLR1_SHIFT 0 +#define XAVBUF_V_BLEND_BG_CLR_1_CLR1_WIDTH 12 +#define XAVBUF_V_BLEND_BG_CLR_1_CLR1_MASK 0X00000FFF + +/** + * * Register: XAVBUF_V_BLEND_BG_CLR_2 + * */ +#define XAVBUF_V_BLEND_BG_CLR_2 0X0000A008 + +#define XAVBUF_V_BLEND_BG_CLR_2_CLR2_SHIFT 0 +#define XAVBUF_V_BLEND_BG_CLR_2_CLR2_WIDTH 12 +#define XAVBUF_V_BLEND_BG_CLR_2_CLR2_MASK 0X00000FFF + +/** + * * Register: XAVBUF_V_BLEND_SET_GLOBAL_ALPHA_REG + * */ +#define XAVBUF_V_BLEND_SET_GLOBAL_ALPHA_REG 0X0000A00C + +#define XAVBUF_V_BLEND_SET_GLOBAL_ALPHA_REG_VALUE_SHIFT 1 +#define XAVBUF_V_BLEND_SET_GLOBAL_ALPHA_REG_VALUE_WIDTH 8 +#define XAVBUF_V_BLEND_SET_GLOBAL_ALPHA_REG_VALUE_MASK 0X000001FE + +#define XAVBUF_V_BLEND_SET_GLOBAL_ALPHA_REG_EN_SHIFT 0 +#define XAVBUF_V_BLEND_SET_GLOBAL_ALPHA_REG_EN_WIDTH 1 +#define XAVBUF_V_BLEND_SET_GLOBAL_ALPHA_REG_EN_MASK 0X00000001 + +/** + * * Register: XAVBUF_V_BLEND_OUTPUT_VID_FORMAT + * */ +#define XAVBUF_V_BLEND_OUTPUT_VID_FORMAT 0X0000A014 + +#define XAVBUF_V_BLEND_OUTPUT_VID_FORMAT_EN_DOWNSAMPLE_SHIFT 4 +#define XAVBUF_V_BLEND_OUTPUT_VID_FORMAT_EN_DOWNSAMPLE_WIDTH 1 +#define XAVBUF_V_BLEND_OUTPUT_VID_FORMAT_EN_DOWNSAMPLE_MASK 0X00000010 + +#define XAVBUF_V_BLEND_OUTPUT_VID_FORMAT_VID_FORMAT_SHIFT 0 +#define XAVBUF_V_BLEND_OUTPUT_VID_FORMAT_VID_FORMAT_WIDTH 3 +#define XAVBUF_V_BLEND_OUTPUT_VID_FORMAT_VID_FORMAT_MASK 0X00000007 + +/** + * * Register: XAVBUF_V_BLEND_LAYER0_CONTROL + * */ +#define XAVBUF_V_BLEND_LAYER0_CONTROL 0X0000A018 + +#define XAVBUF_V_BLEND_LAYER0_CONTROL_BYPASS_SHIFT 8 +#define XAVBUF_V_BLEND_LAYER0_CONTROL_BYPASS_WIDTH 1 +#define XAVBUF_V_BLEND_LAYER0_CONTROL_BYPASS_MASK 0X00000100 + +#define XAVBUF_V_BLEND_LAYER0_CONTROL_RGB_MODE_SHIFT 1 +#define XAVBUF_V_BLEND_LAYER0_CONTROL_RGB_MODE_WIDTH 1 +#define XAVBUF_V_BLEND_LAYER0_CONTROL_RGB_MODE_MASK 0X00000002 + +#define XAVBUF_V_BLEND_LAYER0_CONTROL_EN_US_SHIFT 0 +#define XAVBUF_V_BLEND_LAYER0_CONTROL_EN_US_WIDTH 1 +#define XAVBUF_V_BLEND_LAYER0_CONTROL_EN_US_MASK 0X00000001 + +/** + * * Register: XAVBUF_V_BLEND_LAYER1_CONTROL + * */ +#define XAVBUF_V_BLEND_LAYER1_CONTROL 0X0000A01C + +#define XAVBUF_V_BLEND_LAYER1_CONTROL_BYPASS_SHIFT 8 +#define XAVBUF_V_BLEND_LAYER1_CONTROL_BYPASS_WIDTH 1 +#define XAVBUF_V_BLEND_LAYER1_CONTROL_BYPASS_MASK 0X00000100 + +#define XAVBUF_V_BLEND_LAYER1_CONTROL_RGB_MODE_SHIFT 1 +#define XAVBUF_V_BLEND_LAYER1_CONTROL_RGB_MODE_WIDTH 1 +#define XAVBUF_V_BLEND_LAYER1_CONTROL_RGB_MODE_MASK 0X00000002 + +#define XAVBUF_V_BLEND_LAYER1_CONTROL_EN_US_SHIFT 0 +#define XAVBUF_V_BLEND_LAYER1_CONTROL_EN_US_WIDTH 1 +#define XAVBUF_V_BLEND_LAYER1_CONTROL_EN_US_MASK 0X00000001 + +/** + * * Register: XAVBUF_V_BLEND_RGB2YCBCR_COEFF0 + * */ +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF0 0X0000A020 + +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF0_RGB2Y_C0_SHIFT 0 +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF0_RGB2Y_C0_WIDTH 15 +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF0_RGB2Y_C0_MASK 0X00007FFF + +/** + * * Register: XAVBUF_V_BLEND_RGB2YCBCR_COEFF1 + * */ +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF1 0X0000A024 + +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF1_RGB2Y_C1_SHIFT 0 +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF1_RGB2Y_C1_WIDTH 15 +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF1_RGB2Y_C1_MASK 0X00007FFF + +/** + * * Register: XAVBUF_V_BLEND_RGB2YCBCR_COEFF2 + * */ +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF2 0X0000A028 + +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF2_RGB2Y_C2_SHIFT 0 +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF2_RGB2Y_C2_WIDTH 15 +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF2_RGB2Y_C2_MASK 0X00007FFF + +/** + * * Register: XAVBUF_V_BLEND_RGB2YCBCR_COEFF3 + * */ +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF3 0X0000A02C + +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF3_RGB2Y_C3_SHIFT 0 +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF3_RGB2Y_C3_WIDTH 15 +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF3_RGB2Y_C3_MASK 0X00007FFF + +/** + * * Register: XAVBUF_V_BLEND_RGB2YCBCR_COEFF4 + * */ +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF4 0X0000A030 + +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF4_RGB2Y_C4_SHIFT 0 +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF4_RGB2Y_C4_WIDTH 15 +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF4_RGB2Y_C4_MASK 0X00007FFF + +/** + * * Register: XAVBUF_V_BLEND_RGB2YCBCR_COEFF5 + * */ +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF5 0X0000A034 + +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF5_RGB2Y_C5_SHIFT 0 +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF5_RGB2Y_C5_WIDTH 15 +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF5_RGB2Y_C5_MASK 0X00007FFF + +/** + * * Register: XAVBUF_V_BLEND_RGB2YCBCR_COEFF6 + * */ +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF6 0X0000A038 + +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF6_RGB2Y_C6_SHIFT 0 +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF6_RGB2Y_C6_WIDTH 15 +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF6_RGB2Y_C6_MASK 0X00007FFF + +/** + * * Register: XAVBUF_V_BLEND_RGB2YCBCR_COEFF7 + * */ +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF7 0X0000A03C + +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF7_RGB2Y_C7_SHIFT 0 +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF7_RGB2Y_C7_WIDTH 15 +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF7_RGB2Y_C7_MASK 0X00007FFF + +/** + * * Register: XAVBUF_V_BLEND_RGB2YCBCR_COEFF8 + * */ +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF8 0X0000A040 + +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF8_RGB2Y_C8_SHIFT 0 +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF8_RGB2Y_C8_WIDTH 15 +#define XAVBUF_V_BLEND_RGB2YCBCR_COEFF8_RGB2Y_C8_MASK 0X00007FFF + +/** + * * Register: XAVBUF_V_BLEND_IN1CSC_COEFF0 + * */ +#define XAVBUF_V_BLEND_IN1CSC_COEFF0 0X0000A044 + +#define XAVBUF_V_BLEND_IN1CSC_COEFF0_Y2R_C0_SHIFT 0 +#define XAVBUF_V_BLEND_IN1CSC_COEFF0_Y2R_C0_WIDTH 15 +#define XAVBUF_V_BLEND_IN1CSC_COEFF0_Y2R_C0_MASK 0X00007FFF + +/** + * * Register: XAVBUF_V_BLEND_IN1CSC_COEFF1 + * */ +#define XAVBUF_V_BLEND_IN1CSC_COEFF1 0X0000A048 + +#define XAVBUF_V_BLEND_IN1CSC_COEFF1_Y2R_C1_SHIFT 0 +#define XAVBUF_V_BLEND_IN1CSC_COEFF1_Y2R_C1_WIDTH 15 +#define XAVBUF_V_BLEND_IN1CSC_COEFF1_Y2R_C1_MASK 0X00007FFF + +/** + * * Register: XAVBUF_V_BLEND_IN1CSC_COEFF2 + * */ +#define XAVBUF_V_BLEND_IN1CSC_COEFF2 0X0000A04C + +#define XAVBUF_V_BLEND_IN1CSC_COEFF2_Y2R_C2_SHIFT 0 +#define XAVBUF_V_BLEND_IN1CSC_COEFF2_Y2R_C2_WIDTH 15 +#define XAVBUF_V_BLEND_IN1CSC_COEFF2_Y2R_C2_MASK 0X00007FFF + +/** + * * Register: XAVBUF_V_BLEND_IN1CSC_COEFF3 + * */ +#define XAVBUF_V_BLEND_IN1CSC_COEFF3 0X0000A050 + +#define XAVBUF_V_BLEND_IN1CSC_COEFF3_Y2R_C3_SHIFT 0 +#define XAVBUF_V_BLEND_IN1CSC_COEFF3_Y2R_C3_WIDTH 15 +#define XAVBUF_V_BLEND_IN1CSC_COEFF3_Y2R_C3_MASK 0X00007FFF + +/** + * * Register: XAVBUF_V_BLEND_IN1CSC_COEFF4 + * */ +#define XAVBUF_V_BLEND_IN1CSC_COEFF4 0X0000A054 + +#define XAVBUF_V_BLEND_IN1CSC_COEFF4_Y2R_C4_SHIFT 0 +#define XAVBUF_V_BLEND_IN1CSC_COEFF4_Y2R_C4_WIDTH 15 +#define XAVBUF_V_BLEND_IN1CSC_COEFF4_Y2R_C4_MASK 0X00007FFF + +/** + * * Register: XAVBUF_V_BLEND_IN1CSC_COEFF5 + * */ +#define XAVBUF_V_BLEND_IN1CSC_COEFF5 0X0000A058 + +#define XAVBUF_V_BLEND_IN1CSC_COEFF5_Y2R_C5_SHIFT 0 +#define XAVBUF_V_BLEND_IN1CSC_COEFF5_Y2R_C5_WIDTH 15 +#define XAVBUF_V_BLEND_IN1CSC_COEFF5_Y2R_C5_MASK 0X00007FFF + +/** + * * Register: XAVBUF_V_BLEND_IN1CSC_COEFF6 + * */ +#define XAVBUF_V_BLEND_IN1CSC_COEFF6 0X0000A05C + +#define XAVBUF_V_BLEND_IN1CSC_COEFF6_Y2R_C6_SHIFT 0 +#define XAVBUF_V_BLEND_IN1CSC_COEFF6_Y2R_C6_WIDTH 15 +#define XAVBUF_V_BLEND_IN1CSC_COEFF6_Y2R_C6_MASK 0X00007FFF + +/** + * * Register: XAVBUF_V_BLEND_IN1CSC_COEFF7 + * */ +#define XAVBUF_V_BLEND_IN1CSC_COEFF7 0X0000A060 + +#define XAVBUF_V_BLEND_IN1CSC_COEFF7_Y2R_C7_SHIFT 0 +#define XAVBUF_V_BLEND_IN1CSC_COEFF7_Y2R_C7_WIDTH 15 +#define XAVBUF_V_BLEND_IN1CSC_COEFF7_Y2R_C7_MASK 0X00007FFF + +/** + * * Register: XAVBUF_V_BLEND_IN1CSC_COEFF8 + * */ +#define XAVBUF_V_BLEND_IN1CSC_COEFF8 0X0000A064 + +#define XAVBUF_V_BLEND_IN1CSC_COEFF8_Y2R_C8_SHIFT 0 +#define XAVBUF_V_BLEND_IN1CSC_COEFF8_Y2R_C8_WIDTH 15 +#define XAVBUF_V_BLEND_IN1CSC_COEFF8_Y2R_C8_MASK 0X00007FFF + +/** + * * Register: XAVBUF_V_BLEND_LUMA_IN1CSC_OFFSET + * */ +#define XAVBUF_V_BLEND_LUMA_IN1CSC_OFFSET 0X0000A068 + +#define XAVBUF_V_BLEND_LUMA_IN1CSC_OFFSET_POST_OFFSET_SHIFT 16 +#define XAVBUF_V_BLEND_LUMA_IN1CSC_OFFSET_POST_OFFSET_WIDTH 13 +#define XAVBUF_V_BLEND_LUMA_IN1CSC_OFFSET_POST_OFFSET_MASK 0X1FFF0000 + +#define XAVBUF_V_BLEND_LUMA_IN1CSC_OFFSET_PRE_OFFSET_SHIFT 0 +#define XAVBUF_V_BLEND_LUMA_IN1CSC_OFFSET_PRE_OFFSET_WIDTH 13 +#define XAVBUF_V_BLEND_LUMA_IN1CSC_OFFSET_PRE_OFFSET_MASK 0X00001FFF + +/** + * * Register: XAVBUF_V_BLEND_CR_IN1CSC_OFFSET + * */ +#define XAVBUF_V_BLEND_CR_IN1CSC_OFFSET 0X0000A06C + +#define XAVBUF_V_BLEND_CR_IN1CSC_OFFSET_POST_OFFSET_SHIFT 16 +#define XAVBUF_V_BLEND_CR_IN1CSC_OFFSET_POST_OFFSET_WIDTH 13 +#define XAVBUF_V_BLEND_CR_IN1CSC_OFFSET_POST_OFFSET_MASK 0X1FFF0000 + +#define XAVBUF_V_BLEND_CR_IN1CSC_OFFSET_PRE_OFFSET_SHIFT 0 +#define XAVBUF_V_BLEND_CR_IN1CSC_OFFSET_PRE_OFFSET_WIDTH 13 +#define XAVBUF_V_BLEND_CR_IN1CSC_OFFSET_PRE_OFFSET_MASK 0X00001FFF + +/** + * * Register: XAVBUF_V_BLEND_CB_IN1CSC_OFFSET + * */ +#define XAVBUF_V_BLEND_CB_IN1CSC_OFFSET 0X0000A070 + +#define XAVBUF_V_BLEND_CB_IN1CSC_OFFSET_POST_OFFSET_SHIFT 16 +#define XAVBUF_V_BLEND_CB_IN1CSC_OFFSET_POST_OFFSET_WIDTH 13 +#define XAVBUF_V_BLEND_CB_IN1CSC_OFFSET_POST_OFFSET_MASK 0X1FFF0000 + +#define XAVBUF_V_BLEND_CB_IN1CSC_OFFSET_PRE_OFFSET_SHIFT 0 +#define XAVBUF_V_BLEND_CB_IN1CSC_OFFSET_PRE_OFFSET_WIDTH 13 +#define XAVBUF_V_BLEND_CB_IN1CSC_OFFSET_PRE_OFFSET_MASK 0X00001FFF + +/** + * * Register: XAVBUF_V_BLEND_LUMA_OUTCSC_OFFSET + * */ +#define XAVBUF_V_BLEND_LUMA_OUTCSC_OFFSET 0X0000A074 + +#define XAVBUF_V_BLEND_LUMA_OUTCSC_OFFSET_POST_OFFSET_SHIFT 16 +#define XAVBUF_V_BLEND_LUMA_OUTCSC_OFFSET_POST_OFFSET_WIDTH 13 +#define XAVBUF_V_BLEND_LUMA_OUTCSC_OFFSET_POST_OFFSET_MASK 0X1FFF0000 + +#define XAVBUF_V_BLEND_LUMA_OUTCSC_OFFSET_PRE_OFFSET_SHIFT 0 +#define XAVBUF_V_BLEND_LUMA_OUTCSC_OFFSET_PRE_OFFSET_WIDTH 13 +#define XAVBUF_V_BLEND_LUMA_OUTCSC_OFFSET_PRE_OFFSET_MASK 0X00001FFF + +/** + * * Register: XAVBUF_V_BLEND_CR_OUTCSC_OFFSET + * */ +#define XAVBUF_V_BLEND_CR_OUTCSC_OFFSET 0X0000A078 + +#define XAVBUF_V_BLEND_CR_OUTCSC_OFFSET_POST_OFFSET_SHIFT 16 +#define XAVBUF_V_BLEND_CR_OUTCSC_OFFSET_POST_OFFSET_WIDTH 13 +#define XAVBUF_V_BLEND_CR_OUTCSC_OFFSET_POST_OFFSET_MASK 0X1FFF0000 + +#define XAVBUF_V_BLEND_CR_OUTCSC_OFFSET_PRE_OFFSET_SHIFT 0 +#define XAVBUF_V_BLEND_CR_OUTCSC_OFFSET_PRE_OFFSET_WIDTH 13 +#define XAVBUF_V_BLEND_CR_OUTCSC_OFFSET_PRE_OFFSET_MASK 0X00001FFF + +/** + * * Register: XAVBUF_V_BLEND_CB_OUTCSC_OFFSET + * */ +#define XAVBUF_V_BLEND_CB_OUTCSC_OFFSET 0X0000A07C + +#define XAVBUF_V_BLEND_CB_OUTCSC_OFFSET_POST_OFFSET_SHIFT 16 +#define XAVBUF_V_BLEND_CB_OUTCSC_OFFSET_POST_OFFSET_WIDTH 13 +#define XAVBUF_V_BLEND_CB_OUTCSC_OFFSET_POST_OFFSET_MASK 0X1FFF0000 + +#define XAVBUF_V_BLEND_CB_OUTCSC_OFFSET_PRE_OFFSET_SHIFT 0 +#define XAVBUF_V_BLEND_CB_OUTCSC_OFFSET_PRE_OFFSET_WIDTH 13 +#define XAVBUF_V_BLEND_CB_OUTCSC_OFFSET_PRE_OFFSET_MASK 0X00001FFF + +/** + * * Register: XAVBUF_V_BLEND_IN2CSC_COEFF0 + * */ +#define XAVBUF_V_BLEND_IN2CSC_COEFF0 0X0000A080 + +#define XAVBUF_V_BLEND_IN2CSC_COEFF0_Y2R_C0_SHIFT 0 +#define XAVBUF_V_BLEND_IN2CSC_COEFF0_Y2R_C0_WIDTH 15 +#define XAVBUF_V_BLEND_IN2CSC_COEFF0_Y2R_C0_MASK 0X00007FFF + +/** + * * Register: XAVBUF_V_BLEND_IN2CSC_COEFF1 + * */ +#define XAVBUF_V_BLEND_IN2CSC_COEFF1 0X0000A084 + +#define XAVBUF_V_BLEND_IN2CSC_COEFF1_Y2R_C1_SHIFT 0 +#define XAVBUF_V_BLEND_IN2CSC_COEFF1_Y2R_C1_WIDTH 15 +#define XAVBUF_V_BLEND_IN2CSC_COEFF1_Y2R_C1_MASK 0X00007FFF + +/** + * * Register: XAVBUF_V_BLEND_IN2CSC_COEFF2 + * */ +#define XAVBUF_V_BLEND_IN2CSC_COEFF2 0X0000A088 + +#define XAVBUF_V_BLEND_IN2CSC_COEFF2_Y2R_C2_SHIFT 0 +#define XAVBUF_V_BLEND_IN2CSC_COEFF2_Y2R_C2_WIDTH 15 +#define XAVBUF_V_BLEND_IN2CSC_COEFF2_Y2R_C2_MASK 0X00007FFF + +/** + * * Register: XAVBUF_V_BLEND_IN2CSC_COEFF3 + * */ +#define XAVBUF_V_BLEND_IN2CSC_COEFF3 0X0000A08C + +#define XAVBUF_V_BLEND_IN2CSC_COEFF3_Y2R_C3_SHIFT 0 +#define XAVBUF_V_BLEND_IN2CSC_COEFF3_Y2R_C3_WIDTH 15 +#define XAVBUF_V_BLEND_IN2CSC_COEFF3_Y2R_C3_MASK 0X00007FFF + +/** + * * Register: XAVBUF_V_BLEND_IN2CSC_COEFF4 + * */ +#define XAVBUF_V_BLEND_IN2CSC_COEFF4 0X0000A090 + +#define XAVBUF_V_BLEND_IN2CSC_COEFF4_Y2R_C4_SHIFT 0 +#define XAVBUF_V_BLEND_IN2CSC_COEFF4_Y2R_C4_WIDTH 15 +#define XAVBUF_V_BLEND_IN2CSC_COEFF4_Y2R_C4_MASK 0X00007FFF + +/** + * * Register: XAVBUF_V_BLEND_IN2CSC_COEFF5 + * */ +#define XAVBUF_V_BLEND_IN2CSC_COEFF5 0X0000A094 + +#define XAVBUF_V_BLEND_IN2CSC_COEFF5_Y2R_C5_SHIFT 0 +#define XAVBUF_V_BLEND_IN2CSC_COEFF5_Y2R_C5_WIDTH 15 +#define XAVBUF_V_BLEND_IN2CSC_COEFF5_Y2R_C5_MASK 0X00007FFF + +/** + * * Register: XAVBUF_V_BLEND_IN2CSC_COEFF6 + * */ +#define XAVBUF_V_BLEND_IN2CSC_COEFF6 0X0000A098 + +#define XAVBUF_V_BLEND_IN2CSC_COEFF6_Y2R_C6_SHIFT 0 +#define XAVBUF_V_BLEND_IN2CSC_COEFF6_Y2R_C6_WIDTH 15 +#define XAVBUF_V_BLEND_IN2CSC_COEFF6_Y2R_C6_MASK 0X00007FFF + +/** + * * Register: XAVBUF_V_BLEND_IN2CSC_COEFF7 + * */ +#define XAVBUF_V_BLEND_IN2CSC_COEFF7 0X0000A09C + +#define XAVBUF_V_BLEND_IN2CSC_COEFF7_Y2R_C7_SHIFT 0 +#define XAVBUF_V_BLEND_IN2CSC_COEFF7_Y2R_C7_WIDTH 15 +#define XAVBUF_V_BLEND_IN2CSC_COEFF7_Y2R_C7_MASK 0X00007FFF + +/** + * * Register: XAVBUF_V_BLEND_IN2CSC_COEFF8 + * */ +#define XAVBUF_V_BLEND_IN2CSC_COEFF8 0X0000A0A0 + +#define XAVBUF_V_BLEND_IN2CSC_COEFF8_Y2R_C8_SHIFT 0 +#define XAVBUF_V_BLEND_IN2CSC_COEFF8_Y2R_C8_WIDTH 15 +#define XAVBUF_V_BLEND_IN2CSC_COEFF8_Y2R_C8_MASK 0X00007FFF + +/** + * * Register: XAVBUF_V_BLEND_LUMA_IN2CSC_OFFSET + * */ +#define XAVBUF_V_BLEND_LUMA_IN2CSC_OFFSET 0X0000A0A4 + +#define XAVBUF_V_BLEND_LUMA_IN2CSC_OFFSET_POST_OFFSET_SHIFT 16 +#define XAVBUF_V_BLEND_LUMA_IN2CSC_OFFSET_POST_OFFSET_WIDTH 13 +#define XAVBUF_V_BLEND_LUMA_IN2CSC_OFFSET_POST_OFFSET_MASK 0X1FFF0000 + +#define XAVBUF_V_BLEND_LUMA_IN2CSC_OFFSET_PRE_OFFSET_SHIFT 0 +#define XAVBUF_V_BLEND_LUMA_IN2CSC_OFFSET_PRE_OFFSET_WIDTH 13 +#define XAVBUF_V_BLEND_LUMA_IN2CSC_OFFSET_PRE_OFFSET_MASK 0X00001FFF + +/** + * * Register: XAVBUF_V_BLEND_CR_IN2CSC_OFFSET + * */ +#define XAVBUF_V_BLEND_CR_IN2CSC_OFFSET 0X0000A0A8 + +#define XAVBUF_V_BLEND_CR_IN2CSC_OFFSET_POST_OFFSET_SHIFT 16 +#define XAVBUF_V_BLEND_CR_IN2CSC_OFFSET_POST_OFFSET_WIDTH 13 +#define XAVBUF_V_BLEND_CR_IN2CSC_OFFSET_POST_OFFSET_MASK 0X1FFF0000 + +#define XAVBUF_V_BLEND_CR_IN2CSC_OFFSET_PRE_OFFSET_SHIFT 0 +#define XAVBUF_V_BLEND_CR_IN2CSC_OFFSET_PRE_OFFSET_WIDTH 13 +#define XAVBUF_V_BLEND_CR_IN2CSC_OFFSET_PRE_OFFSET_MASK 0X00001FFF + +/** + * * Register: XAVBUF_V_BLEND_CB_IN2CSC_OFFSET + * */ +#define XAVBUF_V_BLEND_CB_IN2CSC_OFFSET 0X0000A0AC + +#define XAVBUF_V_BLEND_CB_IN2CSC_OFFSET_POST_OFFSET_SHIFT 16 +#define XAVBUF_V_BLEND_CB_IN2CSC_OFFSET_POST_OFFSET_WIDTH 13 +#define XAVBUF_V_BLEND_CB_IN2CSC_OFFSET_POST_OFFSET_MASK 0X1FFF0000 + +#define XAVBUF_V_BLEND_CB_IN2CSC_OFFSET_PRE_OFFSET_SHIFT 0 +#define XAVBUF_V_BLEND_CB_IN2CSC_OFFSET_PRE_OFFSET_WIDTH 13 +#define XAVBUF_V_BLEND_CB_IN2CSC_OFFSET_PRE_OFFSET_MASK 0X00001FFF + +/** + * * Register: XAVBUF_V_BLEND_CHROMA_KEY_ENABLE + * */ +#define XAVBUF_V_BLEND_CHROMA_KEY_ENABLE 0X0000A1D0 + +#define XAVBUF_V_BLEND_CHROMA_KEY_ENABLE_M_SEL_SHIFT 1 +#define XAVBUF_V_BLEND_CHROMA_KEY_ENABLE_M_SEL_WIDTH 1 +#define XAVBUF_V_BLEND_CHROMA_KEY_ENABLE_M_SEL_MASK 0X00000002 + +#define XAVBUF_V_BLEND_CHROMA_KEY_ENABLE_EN_SHIFT 0 +#define XAVBUF_V_BLEND_CHROMA_KEY_ENABLE_EN_WIDTH 1 +#define XAVBUF_V_BLEND_CHROMA_KEY_ENABLE_EN_MASK 0X00000001 + +/** + * * Register: XAVBUF_V_BLEND_CHROMA_KEY_COMP1 + * */ +#define XAVBUF_V_BLEND_CHROMA_KEY_COMP1 0X0000A1D4 + +#define XAVBUF_V_BLEND_CHROMA_KEY_COMP1_MAX_SHIFT 16 +#define XAVBUF_V_BLEND_CHROMA_KEY_COMP1_MAX_WIDTH 12 +#define XAVBUF_V_BLEND_CHROMA_KEY_COMP1_MAX_MASK 0X0FFF0000 + +#define XAVBUF_V_BLEND_CHROMA_KEY_COMP1_MIN_SHIFT 0 +#define XAVBUF_V_BLEND_CHROMA_KEY_COMP1_MIN_WIDTH 12 +#define XAVBUF_V_BLEND_CHROMA_KEY_COMP1_MIN_MASK 0X00000FFF + +/** + * * Register: XAVBUF_V_BLEND_CHROMA_KEY_COMP2 + * */ +#define XAVBUF_V_BLEND_CHROMA_KEY_COMP2 0X0000A1D8 + +#define XAVBUF_V_BLEND_CHROMA_KEY_COMP2_MAX_SHIFT 16 +#define XAVBUF_V_BLEND_CHROMA_KEY_COMP2_MAX_WIDTH 12 +#define XAVBUF_V_BLEND_CHROMA_KEY_COMP2_MAX_MASK 0X0FFF0000 + +#define XAVBUF_V_BLEND_CHROMA_KEY_COMP2_MIN_SHIFT 0 +#define XAVBUF_V_BLEND_CHROMA_KEY_COMP2_MIN_WIDTH 12 +#define XAVBUF_V_BLEND_CHROMA_KEY_COMP2_MIN_MASK 0X00000FFF + +/** + * * Register: XAVBUF_V_BLEND_CHROMA_KEY_COMP3 + * */ +#define XAVBUF_V_BLEND_CHROMA_KEY_COMP3 0X0000A1DC + +#define XAVBUF_V_BLEND_CHROMA_KEY_COMP3_MAX_SHIFT 16 +#define XAVBUF_V_BLEND_CHROMA_KEY_COMP3_MAX_WIDTH 12 +#define XAVBUF_V_BLEND_CHROMA_KEY_COMP3_MAX_MASK 0X0FFF0000 + +#define XAVBUF_V_BLEND_CHROMA_KEY_COMP3_MIN_SHIFT 0 +#define XAVBUF_V_BLEND_CHROMA_KEY_COMP3_MIN_WIDTH 12 +#define XAVBUF_V_BLEND_CHROMA_KEY_COMP3_MIN_MASK 0X00000FFF + +/** + * * Register: XAVBUF_BUF_FORMAT + * */ +#define XAVBUF_BUF_FORMAT 0X0000B000 + +#define XAVBUF_BUF_FORMAT_NL_GRAPHX_FORMAT_SHIFT 8 +#define XAVBUF_BUF_FORMAT_NL_GRAPHX_FORMAT_WIDTH 4 +#define XAVBUF_BUF_FORMAT_NL_GRAPHX_FORMAT_MASK 0X00000F00 + +#define XAVBUF_BUF_FORMAT_NL_VID_FORMAT_SHIFT 0 +#define XAVBUF_BUF_FORMAT_NL_VID_FORMAT_WIDTH 5 +#define XAVBUF_BUF_FORMAT_NL_VID_FORMAT_MASK 0X0000001F + +/** + * * Register: XAVBUF_BUF_NON_LIVE_LATENCY + * */ +#define XAVBUF_BUF_NON_LIVE_LATENCY 0X0000B008 + +#define XAVBUF_BUF_NON_LIVE_LATENCY_NL_LATENCY_SHIFT 0 +#define XAVBUF_BUF_NON_LIVE_LATENCY_NL_LATENCY_WIDTH 10 +#define XAVBUF_BUF_NON_LIVE_LATENCY_NL_LATENCY_MASK 0X000003FF + +/** + * * Register: XAVBUF_CHBUF0 + * */ +#define XAVBUF_CHBUF0 0X0000B010 + +#define XAVBUF_CHBUF0_BURST_LEN_SHIFT 2 +#define XAVBUF_CHBUF0_BURST_LEN_WIDTH 5 +#define XAVBUF_CHBUF0_BURST_LEN_MASK 0X0000007C + +#define XAVBUF_CHBUF0_FLUSH_SHIFT 1 +#define XAVBUF_CHBUF0_FLUSH_WIDTH 1 +#define XAVBUF_CHBUF0_FLUSH_MASK 0X00000002 + +#define XAVBUF_CHBUF0_EN_SHIFT 0 +#define XAVBUF_CHBUF0_EN_WIDTH 1 +#define XAVBUF_CHBUF0_EN_MASK 0X00000001 + +/** + * * Register: XAVBUF_CHBUF1 + * */ +#define XAVBUF_CHBUF1 0X0000B014 + +#define XAVBUF_CHBUF1_BURST_LEN_SHIFT 2 +#define XAVBUF_CHBUF1_BURST_LEN_WIDTH 5 +#define XAVBUF_CHBUF1_BURST_LEN_MASK 0X0000007C + +#define XAVBUF_CHBUF1_FLUSH_SHIFT 1 +#define XAVBUF_CHBUF1_FLUSH_WIDTH 1 +#define XAVBUF_CHBUF1_FLUSH_MASK 0X00000002 + +#define XAVBUF_CHBUF1_EN_SHIFT 0 +#define XAVBUF_CHBUF1_EN_WIDTH 1 +#define XAVBUF_CHBUF1_EN_MASK 0X00000001 + +/** + * * Register: XAVBUF_CHBUF2 + * */ +#define XAVBUF_CHBUF2 0X0000B018 + +#define XAVBUF_CHBUF2_BURST_LEN_SHIFT 2 +#define XAVBUF_CHBUF2_BURST_LEN_WIDTH 5 +#define XAVBUF_CHBUF2_BURST_LEN_MASK 0X0000007C + +#define XAVBUF_CHBUF2_FLUSH_SHIFT 1 +#define XAVBUF_CHBUF2_FLUSH_WIDTH 1 +#define XAVBUF_CHBUF2_FLUSH_MASK 0X00000002 + +#define XAVBUF_CHBUF2_EN_SHIFT 0 +#define XAVBUF_CHBUF2_EN_WIDTH 1 +#define XAVBUF_CHBUF2_EN_MASK 0X00000001 + +/** + * * Register: XAVBUF_CHBUF3 + * */ +#define XAVBUF_CHBUF3 0X0000B01C + +#define XAVBUF_CHBUF3_BURST_LEN_SHIFT 2 +#define XAVBUF_CHBUF3_BURST_LEN_WIDTH 5 +#define XAVBUF_CHBUF3_BURST_LEN_MASK 0X0000007C + +#define XAVBUF_CHBUF3_FLUSH_SHIFT 1 +#define XAVBUF_CHBUF3_FLUSH_WIDTH 1 +#define XAVBUF_CHBUF3_FLUSH_MASK 0X00000002 + +#define XAVBUF_CHBUF3_EN_SHIFT 0 +#define XAVBUF_CHBUF3_EN_WIDTH 1 +#define XAVBUF_CHBUF3_EN_MASK 0X00000001 + +/** + * * Register: XAVBUF_CHBUF4 + * */ +#define XAVBUF_CHBUF4 0X0000B020 + +#define XAVBUF_CHBUF4_BURST_LEN_SHIFT 2 +#define XAVBUF_CHBUF4_BURST_LEN_WIDTH 5 +#define XAVBUF_CHBUF4_BURST_LEN_MASK 0X0000007C + +#define XAVBUF_CHBUF4_FLUSH_SHIFT 1 +#define XAVBUF_CHBUF4_FLUSH_WIDTH 1 +#define XAVBUF_CHBUF4_FLUSH_MASK 0X00000002 + +#define XAVBUF_CHBUF4_EN_SHIFT 0 +#define XAVBUF_CHBUF4_EN_WIDTH 1 +#define XAVBUF_CHBUF4_EN_MASK 0X00000001 + +/** + * * Register: XAVBUF_CHBUF5 + * */ +#define XAVBUF_CHBUF5 0X0000B024 + +#define XAVBUF_CHBUF5_BURST_LEN_SHIFT 2 +#define XAVBUF_CHBUF5_BURST_LEN_WIDTH 5 +#define XAVBUF_CHBUF5_BURST_LEN_MASK 0X0000007C + +#define XAVBUF_CHBUF5_FLUSH_SHIFT 1 +#define XAVBUF_CHBUF5_FLUSH_WIDTH 1 +#define XAVBUF_CHBUF5_FLUSH_MASK 0X00000002 + +#define XAVBUF_CHBUF5_EN_SHIFT 0 +#define XAVBUF_CHBUF5_EN_WIDTH 1 +#define XAVBUF_CHBUF5_EN_MASK 0X00000001 + +/** + * * Register: XAVBUF_BUF_STC_CONTROL + * */ +#define XAVBUF_BUF_STC_CONTROL 0X0000B02C + +#define XAVBUF_BUF_STC_CONTROL_EN_SHIFT 0 +#define XAVBUF_BUF_STC_CONTROL_EN_WIDTH 1 +#define XAVBUF_BUF_STC_CONTROL_EN_MASK 0X00000001 + +/** + * * Register: XAVBUF_BUF_STC_INIT_VALUE0 + * */ +#define XAVBUF_BUF_STC_INIT_VALUE0 0X0000B030 + +#define XAVBUF_BUF_STC_INIT_VALUE0_INIT_VALUE0_SHIFT 0 +#define XAVBUF_BUF_STC_INIT_VALUE0_INIT_VALUE0_WIDTH 32 +#define XAVBUF_BUF_STC_INIT_VALUE0_INIT_VALUE0_MASK 0XFFFFFFFF + +/** + * * Register: XAVBUF_BUF_STC_INIT_VALUE1 + * */ +#define XAVBUF_BUF_STC_INIT_VALUE1 0X0000B034 + +#define XAVBUF_BUF_STC_INIT_VALUE1_INIT_VALUE1_SHIFT 0 +#define XAVBUF_BUF_STC_INIT_VALUE1_INIT_VALUE1_WIDTH 10 +#define XAVBUF_BUF_STC_INIT_VALUE1_INIT_VALUE1_MASK 0X000003FF + +/** + * * Register: XAVBUF_BUF_STC_ADJ + * */ +#define XAVBUF_BUF_STC_ADJ 0X0000B038 + +#define XAVBUF_BUF_STC_ADJ_SIGN_SHIFT 31 +#define XAVBUF_BUF_STC_ADJ_SIGN_WIDTH 1 +#define XAVBUF_BUF_STC_ADJ_SIGN_MASK 0X80000000 + +#define XAVBUF_BUF_STC_ADJ_VALUE_SHIFT 0 +#define XAVBUF_BUF_STC_ADJ_VALUE_WIDTH 31 +#define XAVBUF_BUF_STC_ADJ_VALUE_MASK 0X7FFFFFFF + +/** + * * Register: XAVBUF_BUF_STC_VID_VSYNC_TS_REG0 + * */ +#define XAVBUF_BUF_STC_VID_VSYNC_TS_REG0 0X0000B03C + +#define XAVBUF_BUF_STC_VID_VSYNC_TS_REG0_VSYNC_TS0_SHIFT 0 +#define XAVBUF_BUF_STC_VID_VSYNC_TS_REG0_VSYNC_TS0_WIDTH 32 +#define XAVBUF_BUF_STC_VID_VSYNC_TS_REG0_VSYNC_TS0_MASK 0XFFFFFFFF + +/** + * * Register: XAVBUF_BUF_STC_VID_VSYNC_TS_REG1 + * */ +#define XAVBUF_BUF_STC_VID_VSYNC_TS_REG1 0X0000B040 + +#define XAVBUF_BUF_STC_VID_VSYNC_TS_REG1_VSYNC_TS1_SHIFT 0 +#define XAVBUF_BUF_STC_VID_VSYNC_TS_REG1_VSYNC_TS1_WIDTH 10 +#define XAVBUF_BUF_STC_VID_VSYNC_TS_REG1_VSYNC_TS1_MASK 0X000003FF + +/** + * * Register: XAVBUF_BUF_STC_EXT_VSYNC_TS_REG0 + * */ +#define XAVBUF_BUF_STC_EXT_VSYNC_TS_REG0 0X0000B044 + +#define XAVBUF_BUF_STC_EXT_VSYNC_TS_REG0_EXT_VSYNC_TS0_SHIFT 0 +#define XAVBUF_BUF_STC_EXT_VSYNC_TS_REG0_EXT_VSYNC_TS0_WIDTH 32 +#define XAVBUF_BUF_STC_EXT_VSYNC_TS_REG0_EXT_VSYNC_TS0_MASK 0XFFFFFFFF + +/** + * * Register: XAVBUF_BUF_STC_EXT_VSYNC_TS_REG1 + * */ +#define XAVBUF_BUF_STC_EXT_VSYNC_TS_REG1 0X0000B048 + +#define XAVBUF_BUF_STC_EXT_VSYNC_TS_REG1_EXT_VSYNC_TS1_SHIFT 0 +#define XAVBUF_BUF_STC_EXT_VSYNC_TS_REG1_EXT_VSYNC_TS1_WIDTH 10 +#define XAVBUF_BUF_STC_EXT_VSYNC_TS_REG1_EXT_VSYNC_TS1_MASK 0X000003FF + +/** + * * Register: XAVBUF_BUF_STC_CUSTOM_EVENT_TS_REG0 + * */ +#define XAVBUF_BUF_STC_CUSTOM_EVENT_TS_REG0 0X0000B04C + +#define XAVBUF_BUF_STC_CUSTOM_EVENT_TS_REG0_CUST_EVENT_TS0_SHIFT 0 +#define XAVBUF_BUF_STC_CUSTOM_EVENT_TS_REG0_CUST_EVENT_TS0_WIDTH 32 +#define XAVBUF_BUF_STC_CUSTOM_EVENT_TS_REG0_CUST_EVENT_TS0_MASK 0XFFFFFFFF + +/** + * * Register: XAVBUF_BUF_STC_CUSTOM_EVENT_TS_REG1 + * */ +#define XAVBUF_BUF_STC_CUSTOM_EVENT_TS_REG1 0X0000B050 + +#define XAVBUF_BUF_STC_CUSTOM_EVENT_TS_REG1_CUST_EVENT_TS1_SHIFT 0 +#define XAVBUF_BUF_STC_CUSTOM_EVENT_TS_REG1_CUST_EVENT_TS1_WIDTH 10 +#define XAVBUF_BUF_STC_CUSTOM_EVENT_TS_REG1_CUST_EVENT_TS1_MASK 0X000003FF + +/** + * * Register: XAVBUF_BUF_STC_CUSTOM_EVENT2_TS_REG0 + * */ +#define XAVBUF_BUF_STC_CUSTOM_EVENT2_TS_REG0 0X0000B054 + +#define XAVBUF_BUF_STC_CUSTOM_EVENT2_TS_REG0_CUST_EVENT2_TS0_SHIFT 0 +#define XAVBUF_BUF_STC_CUSTOM_EVENT2_TS_REG0_CUST_EVENT2_TS0_WIDTH 32 +#define XAVBUF_BUF_STC_CUSTOM_EVENT2_TS_REG0_CUST_EVENT2_TS0_MASK 0XFFFFFFFF + +/** + * * Register: XAVBUF_BUF_STC_CUSTOM_EVENT2_TS_REG1 + * */ +#define XAVBUF_BUF_STC_CUSTOM_EVENT2_TS_REG1 0X0000B058 + +#define XAVBUF_BUF_STC_CUSTOM_EVENT2_TS_REG1_CUST_EVENT2_TS1_SHIFT 0 +#define XAVBUF_BUF_STC_CUSTOM_EVENT2_TS_REG1_CUST_EVENT2_TS1_WIDTH 10 +#define XAVBUF_BUF_STC_CUSTOM_EVENT2_TS_REG1_CUST_EVENT2_TS1_MASK 0X000003FF + +/** + * * Register: XAVBUF_BUF_STC_SNAPSHOT0 + * */ +#define XAVBUF_BUF_STC_SNAPSHOT0 0X0000B060 + +#define XAVBUF_BUF_STC_SNAPSHOT0_STC0_SHIFT 0 +#define XAVBUF_BUF_STC_SNAPSHOT0_STC0_WIDTH 32 +#define XAVBUF_BUF_STC_SNAPSHOT0_STC0_MASK 0XFFFFFFFF + +/** + * * Register: XAVBUF_BUF_STC_SNAPSHOT1 + * */ +#define XAVBUF_BUF_STC_SNAPSHOT1 0X0000B064 + +#define XAVBUF_BUF_STC_SNAPSHOT1_STC1_SHIFT 0 +#define XAVBUF_BUF_STC_SNAPSHOT1_STC1_WIDTH 10 +#define XAVBUF_BUF_STC_SNAPSHOT1_STC1_MASK 0X000003FF + +/** + * * Register: XAVBUF_BUF_OUTPUT_AUD_VID_SELECT + * */ +#define XAVBUF_BUF_OUTPUT_AUD_VID_SELECT 0X0000B070 + +#define XAVBUF_BUF_OUTPUT_AUD_VID_SELECT_AUD_STREAM2_SEL_SHIFT 6 +#define XAVBUF_BUF_OUTPUT_AUD_VID_SELECT_AUD_STREAM2_SEL_WIDTH 1 +#define XAVBUF_BUF_OUTPUT_AUD_VID_SELECT_AUD_STREAM2_SEL_MASK 0X00000040 + +#define XAVBUF_BUF_OUTPUT_AUD_VID_SELECT_AUD_STREAM1_SEL_SHIFT 4 +#define XAVBUF_BUF_OUTPUT_AUD_VID_SELECT_AUD_STREAM1_SEL_WIDTH 2 +#define XAVBUF_BUF_OUTPUT_AUD_VID_SELECT_AUD_STREAM1_SEL_MASK 0X00000030 + +#define XAVBUF_BUF_OUTPUT_AUD_VID_SELECT_VID_STREAM2_SEL_SHIFT 2 +#define XAVBUF_BUF_OUTPUT_AUD_VID_SELECT_VID_STREAM2_SEL_WIDTH 2 +#define XAVBUF_BUF_OUTPUT_AUD_VID_SELECT_VID_STREAM2_SEL_MASK 0X0000000C + +#define XAVBUF_BUF_OUTPUT_AUD_VID_SELECT_VID_STREAM1_SEL_SHIFT 0 +#define XAVBUF_BUF_OUTPUT_AUD_VID_SELECT_VID_STREAM1_SEL_WIDTH 2 +#define XAVBUF_BUF_OUTPUT_AUD_VID_SELECT_VID_STREAM1_SEL_MASK 0X00000003 + +/** + * * Register: XAVBUF_BUF_HCOUNT_VCOUNT_INT0 + * */ +#define XAVBUF_BUF_HCOUNT_VCOUNT_INT0 0X0000B074 + +#define XAVBUF_BUF_HCOUNT_VCOUNT_INT0_HCOUNT_SHIFT 16 +#define XAVBUF_BUF_HCOUNT_VCOUNT_INT0_HCOUNT_WIDTH 14 +#define XAVBUF_BUF_HCOUNT_VCOUNT_INT0_HCOUNT_MASK 0X3FFF0000 + +#define XAVBUF_BUF_HCOUNT_VCOUNT_INT0_VCOUNT_SHIFT 0 +#define XAVBUF_BUF_HCOUNT_VCOUNT_INT0_VCOUNT_WIDTH 14 +#define XAVBUF_BUF_HCOUNT_VCOUNT_INT0_VCOUNT_MASK 0X00003FFF + +/** + * * Register: XAVBUF_BUF_HCOUNT_VCOUNT_INT1 + * */ +#define XAVBUF_BUF_HCOUNT_VCOUNT_INT1 0X0000B078 + +#define XAVBUF_BUF_HCOUNT_VCOUNT_INT1_HCOUNT_SHIFT 16 +#define XAVBUF_BUF_HCOUNT_VCOUNT_INT1_HCOUNT_WIDTH 14 +#define XAVBUF_BUF_HCOUNT_VCOUNT_INT1_HCOUNT_MASK 0X3FFF0000 + +#define XAVBUF_BUF_HCOUNT_VCOUNT_INT1_VCOUNT_SHIFT 0 +#define XAVBUF_BUF_HCOUNT_VCOUNT_INT1_VCOUNT_WIDTH 14 +#define XAVBUF_BUF_HCOUNT_VCOUNT_INT1_VCOUNT_MASK 0X00003FFF + +/** + * * Register: XAVBUF_BUF_DITHER_CFG + * */ +#define XAVBUF_BUF_DITHER_CFG 0X0000B07C + +#define XAVBUF_BUF_DITHER_CFG_TAP_MSB_SHIFT 10 +#define XAVBUF_BUF_DITHER_CFG_TAP_MSB_WIDTH 1 +#define XAVBUF_BUF_DITHER_CFG_TAP_MSB_MASK 0X00000400 + +#define XAVBUF_BUF_DITHER_CFG_DW_SEL_SHIFT 9 +#define XAVBUF_BUF_DITHER_CFG_DW_SEL_WIDTH 1 +#define XAVBUF_BUF_DITHER_CFG_DW_SEL_MASK 0X00000200 + +#define XAVBUF_BUF_DITHER_CFG_LD_SHIFT 8 +#define XAVBUF_BUF_DITHER_CFG_LD_WIDTH 1 +#define XAVBUF_BUF_DITHER_CFG_LD_MASK 0X00000100 + +#define XAVBUF_BUF_DITHER_CFG_TRUNC_PT_SHIFT 5 +#define XAVBUF_BUF_DITHER_CFG_TRUNC_PT_WIDTH 3 +#define XAVBUF_BUF_DITHER_CFG_TRUNC_PT_MASK 0X000000E0 + +#define XAVBUF_BUF_DITHER_CFG_MODE_SHIFT 3 +#define XAVBUF_BUF_DITHER_CFG_MODE_WIDTH 2 +#define XAVBUF_BUF_DITHER_CFG_MODE_MASK 0X00000018 + +#define XAVBUF_BUF_DITHER_CFG_SIZE_SHIFT 0 +#define XAVBUF_BUF_DITHER_CFG_SIZE_WIDTH 3 +#define XAVBUF_BUF_DITHER_CFG_SIZE_MASK 0X00000007 + +/** + * * Register: XAVBUF_DITHER_CFG_SEED0 + * */ +#define XAVBUF_DITHER_CFG_SEED0 0X0000B080 + +#define XAVBUF_DITHER_CFG_SEED0_COLR0_SHIFT 0 +#define XAVBUF_DITHER_CFG_SEED0_COLR0_WIDTH 16 +#define XAVBUF_DITHER_CFG_SEED0_COLR0_MASK 0X0000FFFF + +/** + * * Register: XAVBUF_DITHER_CFG_SEED1 + * */ +#define XAVBUF_DITHER_CFG_SEED1 0X0000B084 + +#define XAVBUF_DITHER_CFG_SEED1_COLR1_SHIFT 0 +#define XAVBUF_DITHER_CFG_SEED1_COLR1_WIDTH 16 +#define XAVBUF_DITHER_CFG_SEED1_COLR1_MASK 0X0000FFFF + +/** + * * Register: XAVBUF_DITHER_CFG_SEED2 + * */ +#define XAVBUF_DITHER_CFG_SEED2 0X0000B088 + +#define XAVBUF_DITHER_CFG_SEED2_COLR2_SHIFT 0 +#define XAVBUF_DITHER_CFG_SEED2_COLR2_WIDTH 16 +#define XAVBUF_DITHER_CFG_SEED2_COLR2_MASK 0X0000FFFF + +/** + * * Register: XAVBUF_DITHER_CFG_MAX + * */ +#define XAVBUF_DITHER_CFG_MAX 0X0000B08C + +#define XAVBUF_DITHER_CFG_MAX_COLR_MAX_SHIFT 0 +#define XAVBUF_DITHER_CFG_MAX_COLR_MAX_WIDTH 12 +#define XAVBUF_DITHER_CFG_MAX_COLR_MAX_MASK 0X00000FFF + +/** + * * Register: XAVBUF_DITHER_CFG_MIN + * */ +#define XAVBUF_DITHER_CFG_MIN 0X0000B090 + +#define XAVBUF_DITHER_CFG_MIN_COLR_MIN_SHIFT 0 +#define XAVBUF_DITHER_CFG_MIN_COLR_MIN_WIDTH 12 +#define XAVBUF_DITHER_CFG_MIN_COLR_MIN_MASK 0X00000FFF + +/** + * * Register: XAVBUF_PATTERN_GEN_SELECT + * */ +#define XAVBUF_PATTERN_GEN_SELECT 0X0000B100 + +#define XAVBUF_PATTERN_GEN_SELECT_OFFSET_EQ_SHIFT 8 +#define XAVBUF_PATTERN_GEN_SELECT_OFFSET_EQ_WIDTH 24 +#define XAVBUF_PATTERN_GEN_SELECT_OFFSET_EQ_MASK 0XFFFFFF00 + +#define XAVBUF_PATTERN_GEN_SELECT_AUD_RATE_SEL_SHIFT 0 +#define XAVBUF_PATTERN_GEN_SELECT_AUD_RATE_SEL_WIDTH 2 +#define XAVBUF_PATTERN_GEN_SELECT_AUD_RATE_SEL_MASK 0X00000003 + +/** + * * Register: XAVBUF_AUD_PATTERN_SELECT1 + * */ +#define XAVBUF_AUD_PATTERN_SELECT1 0X0000B104 + +#define XAVBUF_AUD_PATTERN_SELECT1_PATTERN_SHIFT 0 +#define XAVBUF_AUD_PATTERN_SELECT1_PATTERN_WIDTH 2 +#define XAVBUF_AUD_PATTERN_SELECT1_PATTERN_MASK 0X00000003 + +/** + * * Register: XAVBUF_AUD_PATTERN_SELECT2 + * */ +#define XAVBUF_AUD_PATTERN_SELECT2 0X0000B108 + +#define XAVBUF_AUD_PATTERN_SELECT2_PATTERN_SHIFT 0 +#define XAVBUF_AUD_PATTERN_SELECT2_PATTERN_WIDTH 2 +#define XAVBUF_AUD_PATTERN_SELECT2_PATTERN_MASK 0X00000003 + +/** + * * Register: XAVBUF_BUF_AUD_VID_CLK_SOURCE + * */ +#define XAVBUF_BUF_AUD_VID_CLK_SOURCE 0X0000B120 + +#define XAVBUF_BUF_AUD_VID_CLK_SOURCE_VID_TIMING_SRC_SHIFT 2 +#define XAVBUF_BUF_AUD_VID_CLK_SOURCE_VID_TIMING_SRC_WIDTH 1 +#define XAVBUF_BUF_AUD_VID_CLK_SOURCE_VID_TIMING_SRC_MASK 0X00000004 + +#define XAVBUF_BUF_AUD_VID_CLK_SOURCE_AUD_CLK_SRC_SHIFT 1 +#define XAVBUF_BUF_AUD_VID_CLK_SOURCE_AUD_CLK_SRC_WIDTH 1 +#define XAVBUF_BUF_AUD_VID_CLK_SOURCE_AUD_CLK_SRC_MASK 0X00000002 + +#define XAVBUF_BUF_AUD_VID_CLK_SOURCE_VID_CLK_SRC_SHIFT 0 +#define XAVBUF_BUF_AUD_VID_CLK_SOURCE_VID_CLK_SRC_WIDTH 1 +#define XAVBUF_BUF_AUD_VID_CLK_SOURCE_VID_CLK_SRC_MASK 0X00000001 + +/** + * * Register: XAVBUF_BUF_SRST_REG + * */ +#define XAVBUF_BUF_SRST_REG 0X0000B124 + +#define XAVBUF_BUF_SRST_REG_VID_RST_SHIFT 1 +#define XAVBUF_BUF_SRST_REG_VID_RST_WIDTH 1 +#define XAVBUF_BUF_SRST_REG_VID_RST_MASK 0X00000002 + +/** + * * Register: XAVBUF_BUF_AUD_RDY_INTERVAL + * */ +#define XAVBUF_BUF_AUD_RDY_INTERVAL 0X0000B128 + +#define XAVBUF_BUF_AUD_RDY_INTERVAL_CH1_INT_SHIFT 16 +#define XAVBUF_BUF_AUD_RDY_INTERVAL_CH1_INT_WIDTH 16 +#define XAVBUF_BUF_AUD_RDY_INTERVAL_CH1_INT_MASK 0XFFFF0000 + +#define XAVBUF_BUF_AUD_RDY_INTERVAL_CH0_INT_SHIFT 0 +#define XAVBUF_BUF_AUD_RDY_INTERVAL_CH0_INT_WIDTH 16 +#define XAVBUF_BUF_AUD_RDY_INTERVAL_CH0_INT_MASK 0X0000FFFF + +/** + * * Register: XAVBUF_BUF_AUD_CH_CFG + * */ +#define XAVBUF_BUF_AUD_CH_CFG 0X0000B12C + +#define XAVBUF_BUF_AUD_CH_CFG_AUD_CH_ID_SHIFT 0 +#define XAVBUF_BUF_AUD_CH_CFG_AUD_CH_ID_WIDTH 2 +#define XAVBUF_BUF_AUD_CH_CFG_AUD_CH_ID_MASK 0X00000003 + +/** + * * Register: XAVBUF_BUF_GRAPHICS_COMP0_SCALE_FACTOR + * */ +#define XAVBUF_BUF_GRAPHICS_COMP0_SCALE_FACTOR 0X0000B200 + +#define XAVBUF_BUF_GRAPHICS_COMP0_SCALE_FACTOR_GRAPHICS_SCALE_FACTOR0_SHIFT 0 +#define XAVBUF_BUF_GRAPHICS_COMP0_SCALE_FACTOR_GRAPHICS_SCALE_FACTOR0_WIDTH 17 +#define XAVBUF_BUF_GRAPHICS_COMP0_SCALE_FACTOR_GRAPHICS_SCALE_FACTOR0_MASK 0X0001FFFF + +/** + * * Register: XAVBUF_BUF_GRAPHICS_COMP1_SCALE_FACTOR + * */ +#define XAVBUF_BUF_GRAPHICS_COMP1_SCALE_FACTOR 0X0000B204 + +#define XAVBUF_BUF_GRAPHICS_COMP1_SCALE_FACTOR_GRAPHICS_SCALE_FACTOR1_SHIFT 0 +#define XAVBUF_BUF_GRAPHICS_COMP1_SCALE_FACTOR_GRAPHICS_SCALE_FACTOR1_WIDTH 17 +#define XAVBUF_BUF_GRAPHICS_COMP1_SCALE_FACTOR_GRAPHICS_SCALE_FACTOR1_MASK 0X0001FFFF + +/** + * * Register: XAVBUF_BUF_GRAPHICS_COMP2_SCALE_FACTOR + * */ +#define XAVBUF_BUF_GRAPHICS_COMP2_SCALE_FACTOR 0X0000B208 + +#define XAVBUF_BUF_GRAPHICS_COMP2_SCALE_FACTOR_GRAPHICS_SCALE_FACTOR2_SHIFT 0 +#define XAVBUF_BUF_GRAPHICS_COMP2_SCALE_FACTOR_GRAPHICS_SCALE_FACTOR2_WIDTH 17 +#define XAVBUF_BUF_GRAPHICS_COMP2_SCALE_FACTOR_GRAPHICS_SCALE_FACTOR2_MASK 0X0001FFFF + +/** + * * Register: XAVBUF_BUF_VID_COMP0_SCALE_FACTOR + * */ +#define XAVBUF_BUF_VID_COMP0_SCALE_FACTOR 0X0000B20C + +#define XAVBUF_BUF_VID_COMP0_SCALE_FACTOR_VID_SCA_FACT0_SHIFT 0 +#define XAVBUF_BUF_VID_COMP0_SCALE_FACTOR_VID_SCA_FACT0_WIDTH 17 +#define XAVBUF_BUF_VID_COMP0_SCALE_FACTOR_VID_SCA_FACT0_MASK 0X0001FFFF + +/** + * * Register: XAVBUF_BUF_VID_COMP1_SCALE_FACTOR + * */ +#define XAVBUF_BUF_VID_COMP1_SCALE_FACTOR 0X0000B210 + +#define XAVBUF_BUF_VID_COMP1_SCALE_FACTOR_VID_SCA_FACT1_SHIFT 0 +#define XAVBUF_BUF_VID_COMP1_SCALE_FACTOR_VID_SCA_FACT1_WIDTH 17 +#define XAVBUF_BUF_VID_COMP1_SCALE_FACTOR_VID_SCA_FACT1_MASK 0X0001FFFF + +/** + * * Register: XAVBUF_BUF_VID_COMP2_SCALE_FACTOR + * */ +#define XAVBUF_BUF_VID_COMP2_SCALE_FACTOR 0X0000B214 + +#define XAVBUF_BUF_VID_COMP2_SCALE_FACTOR_VID_SCA_FACT2_SHIFT 0 +#define XAVBUF_BUF_VID_COMP2_SCALE_FACTOR_VID_SCA_FACT2_WIDTH 17 +#define XAVBUF_BUF_VID_COMP2_SCALE_FACTOR_VID_SCA_FACT2_MASK 0X0001FFFF + +/** + * * Register: XAVBUF_BUF_LIVE_VID_COMP0_SF + * */ +#define XAVBUF_BUF_LIVE_VID_COMP0_SF 0X0000B218 + +#define XAVBUF_BUF_LIVE_VID_COMP0_SF_LIV_VID_SCA_FACT0_SHIFT 0 +#define XAVBUF_BUF_LIVE_VID_COMP0_SF_LIV_VID_SCA_FACT0_WIDTH 17 +#define XAVBUF_BUF_LIVE_VID_COMP0_SF_LIV_VID_SCA_FACT0_MASK 0X0001FFFF + +/** + * * Register: XAVBUF_BUF_LIVE_VID_COMP1_SF + * */ +#define XAVBUF_BUF_LIVE_VID_COMP1_SF 0X0000B21C + +#define XAVBUF_BUF_LIVE_VID_COMP1_SF_LIV_VID_SCA_FACT1_SHIFT 0 +#define XAVBUF_BUF_LIVE_VID_COMP1_SF_LIV_VID_SCA_FACT1_WIDTH 17 +#define XAVBUF_BUF_LIVE_VID_COMP1_SF_LIV_VID_SCA_FACT1_MASK 0X0001FFFF + +/** + * * Register: XAVBUF_BUF_LIVE_VID_COMP2_SF + * */ +#define XAVBUF_BUF_LIVE_VID_COMP2_SF 0X0000B220 + +#define XAVBUF_BUF_LIVE_VID_COMP2_SF_LIV_VID_SCA_FACT2_SHIFT 0 +#define XAVBUF_BUF_LIVE_VID_COMP2_SF_LIV_VID_SCA_FACT2_WIDTH 17 +#define XAVBUF_BUF_LIVE_VID_COMP2_SF_LIV_VID_SCA_FACT2_MASK 0X0001FFFF + +/** + * * Register: XAVBUF_BUF_LIVE_VID_CFG + * */ +#define XAVBUF_BUF_LIVE_VID_CFG 0X0000B224 + +#define XAVBUF_BUF_LIVE_VID_CFG_CB_FIRST_SHIFT 8 +#define XAVBUF_BUF_LIVE_VID_CFG_CB_FIRST_WIDTH 1 +#define XAVBUF_BUF_LIVE_VID_CFG_CB_FIRST_MASK 0X00000100 + +#define XAVBUF_BUF_LIVE_VID_CFG_FORMAT_SHIFT 4 +#define XAVBUF_BUF_LIVE_VID_CFG_FORMAT_WIDTH 2 +#define XAVBUF_BUF_LIVE_VID_CFG_FORMAT_MASK 0X00000030 + +#define XAVBUF_BUF_LIVE_VID_CFG_BPC_SHIFT 0 +#define XAVBUF_BUF_LIVE_VID_CFG_BPC_WIDTH 3 +#define XAVBUF_BUF_LIVE_VID_CFG_BPC_MASK 0X00000007 + +/** + * * Register: XAVBUF_BUF_LIVE_GFX_COMP0_SF + * */ +#define XAVBUF_BUF_LIVE_GFX_COMP0_SF 0X0000B228 + +#define XAVBUF_BUF_LIVE_GFX_COMP0_SF_LIV_VID_SCA_FACT0_SHIFT 0 +#define XAVBUF_BUF_LIVE_GFX_COMP0_SF_LIV_VID_SCA_FACT0_WIDTH 17 +#define XAVBUF_BUF_LIVE_GFX_COMP0_SF_LIV_VID_SCA_FACT0_MASK 0X0001FFFF + +/** + * * Register: XAVBUF_BUF_LIVE_GFX_COMP1_SF + * */ +#define XAVBUF_BUF_LIVE_GFX_COMP1_SF 0X0000B22C + +#define XAVBUF_BUF_LIVE_GFX_COMP1_SF_LIV_VID_SCA_FACT1_SHIFT 0 +#define XAVBUF_BUF_LIVE_GFX_COMP1_SF_LIV_VID_SCA_FACT1_WIDTH 17 +#define XAVBUF_BUF_LIVE_GFX_COMP1_SF_LIV_VID_SCA_FACT1_MASK 0X0001FFFF + +/** + * * Register: XAVBUF_BUF_LIVE_GFX_COMP2_SF + * */ +#define XAVBUF_BUF_LIVE_GFX_COMP2_SF 0X0000B230 + +#define XAVBUF_BUF_LIVE_GFX_COMP2_SF_LIV_VID_SCA_FACT2_SHIFT 0 +#define XAVBUF_BUF_LIVE_GFX_COMP2_SF_LIV_VID_SCA_FACT2_WIDTH 17 +#define XAVBUF_BUF_LIVE_GFX_COMP2_SF_LIV_VID_SCA_FACT2_MASK 0X0001FFFF + +/** + * * Register: XAVBUF_BUF_LIVE_GFX_CFG + * */ +#define XAVBUF_BUF_LIVE_GFX_CFG 0X0000B234 + +#define XAVBUF_BUF_LIVE_GFX_CFG_CB_FIRST_SHIFT 8 +#define XAVBUF_BUF_LIVE_GFX_CFG_CB_FIRST_WIDTH 1 +#define XAVBUF_BUF_LIVE_GFX_CFG_CB_FIRST_MASK 0X00000100 + +#define XAVBUF_BUF_LIVE_GFX_CFG_FORMAT_SHIFT 4 +#define XAVBUF_BUF_LIVE_GFX_CFG_FORMAT_WIDTH 2 +#define XAVBUF_BUF_LIVE_GFX_CFG_FORMAT_MASK 0X00000030 + +#define XAVBUF_BUF_LIVE_GFX_CFG_BPC_SHIFT 0 +#define XAVBUF_BUF_LIVE_GFX_CFG_BPC_WIDTH 3 +#define XAVBUF_BUF_LIVE_GFX_CFG_BPC_MASK 0X00000007 + +/** + * * Register: XAVBUF_AUD_MIXER_VOLUME_CONTROL + * */ +#define XAVBUF_AUD_MIXER_VOLUME_CONTROL 0X0000C000 + +#define XAVBUF_AUD_MIXER_VOLUME_CONTROL_VOL_CTRL_CH1_SHIFT 16 +#define XAVBUF_AUD_MIXER_VOLUME_CONTROL_VOL_CTRL_CH1_WIDTH 16 +#define XAVBUF_AUD_MIXER_VOLUME_CONTROL_VOL_CTRL_CH1_MASK 0XFFFF0000 + +#define XAVBUF_AUD_MIXER_VOLUME_CONTROL_VOL_CTRL_CH0_SHIFT 0 +#define XAVBUF_AUD_MIXER_VOLUME_CONTROL_VOL_CTRL_CH0_WIDTH 16 +#define XAVBUF_AUD_MIXER_VOLUME_CONTROL_VOL_CTRL_CH0_MASK 0X0000FFFF + +/** + * * Register: XAVBUF_AUD_MIXER_META_DATA + * */ +#define XAVBUF_AUD_MIXER_META_DATA 0X0000C004 + +#define XAVBUF_AUD_MIXER_META_DATA_AUD_META_DATA_SEL_SHIFT 0 +#define XAVBUF_AUD_MIXER_META_DATA_AUD_META_DATA_SEL_WIDTH 1 +#define XAVBUF_AUD_MIXER_META_DATA_AUD_META_DATA_SEL_MASK 0X00000001 + +/** + * * Register: XAVBUF_AUD_CH_STATUS_REG0 + * */ +#define XAVBUF_AUD_CH_STATUS_REG0 0X0000C008 + +#define XAVBUF_AUD_CH_STATUS_REG0_STATUS0_SHIFT 0 +#define XAVBUF_AUD_CH_STATUS_REG0_STATUS0_WIDTH 32 +#define XAVBUF_AUD_CH_STATUS_REG0_STATUS0_MASK 0XFFFFFFFF + +/** + * * Register: XAVBUF_AUD_CH_STATUS_REG1 + * */ +#define XAVBUF_AUD_CH_STATUS_REG1 0X0000C00C + +#define XAVBUF_AUD_CH_STATUS_REG1_STATUS1_SHIFT 0 +#define XAVBUF_AUD_CH_STATUS_REG1_STATUS1_WIDTH 32 +#define XAVBUF_AUD_CH_STATUS_REG1_STATUS1_MASK 0XFFFFFFFF + +/** + * * Register: XAVBUF_AUD_CH_STATUS_REG2 + * */ +#define XAVBUF_AUD_CH_STATUS_REG2 0X0000C010 + +#define XAVBUF_AUD_CH_STATUS_REG2_STATUS2_SHIFT 0 +#define XAVBUF_AUD_CH_STATUS_REG2_STATUS2_WIDTH 32 +#define XAVBUF_AUD_CH_STATUS_REG2_STATUS2_MASK 0XFFFFFFFF + +/** + * * Register: XAVBUF_AUD_CH_STATUS_REG3 + * */ +#define XAVBUF_AUD_CH_STATUS_REG3 0X0000C014 + +#define XAVBUF_AUD_CH_STATUS_REG3_STATUS3_SHIFT 0 +#define XAVBUF_AUD_CH_STATUS_REG3_STATUS3_WIDTH 32 +#define XAVBUF_AUD_CH_STATUS_REG3_STATUS3_MASK 0XFFFFFFFF + +/** + * * Register: XAVBUF_AUD_CH_STATUS_REG4 + * */ +#define XAVBUF_AUD_CH_STATUS_REG4 0X0000C018 + +#define XAVBUF_AUD_CH_STATUS_REG4_STATUS4_SHIFT 0 +#define XAVBUF_AUD_CH_STATUS_REG4_STATUS4_WIDTH 32 +#define XAVBUF_AUD_CH_STATUS_REG4_STATUS4_MASK 0XFFFFFFFF + +/** + * * Register: XAVBUF_AUD_CH_STATUS_REG5 + * */ +#define XAVBUF_AUD_CH_STATUS_REG5 0X0000C01C + +#define XAVBUF_AUD_CH_STATUS_REG5_STATUS5_SHIFT 0 +#define XAVBUF_AUD_CH_STATUS_REG5_STATUS5_WIDTH 32 +#define XAVBUF_AUD_CH_STATUS_REG5_STATUS5_MASK 0XFFFFFFFF + +/** + * * Register: XAVBUF_AUD_CH_A_DATA_REG0 + * */ +#define XAVBUF_AUD_CH_A_DATA_REG0 0X0000C020 + +#define XAVBUF_AUD_CH_A_DATA_REG0_USER_DATA0_SHIFT 0 +#define XAVBUF_AUD_CH_A_DATA_REG0_USER_DATA0_WIDTH 32 +#define XAVBUF_AUD_CH_A_DATA_REG0_USER_DATA0_MASK 0XFFFFFFFF + +/** + * * Register: XAVBUF_AUD_CH_A_DATA_REG1 + * */ +#define XAVBUF_AUD_CH_A_DATA_REG1 0X0000C024 + +#define XAVBUF_AUD_CH_A_DATA_REG1_USER_DATA1_SHIFT 0 +#define XAVBUF_AUD_CH_A_DATA_REG1_USER_DATA1_WIDTH 32 +#define XAVBUF_AUD_CH_A_DATA_REG1_USER_DATA1_MASK 0XFFFFFFFF + +/** + * * Register: XAVBUF_AUD_CH_A_DATA_REG2 + * */ +#define XAVBUF_AUD_CH_A_DATA_REG2 0X0000C028 + +#define XAVBUF_AUD_CH_A_DATA_REG2_USER_DATA2_SHIFT 0 +#define XAVBUF_AUD_CH_A_DATA_REG2_USER_DATA2_WIDTH 32 +#define XAVBUF_AUD_CH_A_DATA_REG2_USER_DATA2_MASK 0XFFFFFFFF + +/** + * * Register: XAVBUF_AUD_CH_A_DATA_REG3 + * */ +#define XAVBUF_AUD_CH_A_DATA_REG3 0X0000C02C + +#define XAVBUF_AUD_CH_A_DATA_REG3_USER_DATA3_SHIFT 0 +#define XAVBUF_AUD_CH_A_DATA_REG3_USER_DATA3_WIDTH 32 +#define XAVBUF_AUD_CH_A_DATA_REG3_USER_DATA3_MASK 0XFFFFFFFF + +/** + * * Register: XAVBUF_AUD_CH_A_DATA_REG4 + * */ +#define XAVBUF_AUD_CH_A_DATA_REG4 0X0000C030 + +#define XAVBUF_AUD_CH_A_DATA_REG4_USER_DATA4_SHIFT 0 +#define XAVBUF_AUD_CH_A_DATA_REG4_USER_DATA4_WIDTH 32 +#define XAVBUF_AUD_CH_A_DATA_REG4_USER_DATA4_MASK 0XFFFFFFFF + +/** + * * Register: XAVBUF_AUD_CH_A_DATA_REG5 + * */ +#define XAVBUF_AUD_CH_A_DATA_REG5 0X0000C034 + +#define XAVBUF_AUD_CH_A_DATA_REG5_USER_DATA5_SHIFT 0 +#define XAVBUF_AUD_CH_A_DATA_REG5_USER_DATA5_WIDTH 32 +#define XAVBUF_AUD_CH_A_DATA_REG5_USER_DATA5_MASK 0XFFFFFFFF + +/** + * * Register: XAVBUF_AUD_CH_B_DATA_REG0 + * */ +#define XAVBUF_AUD_CH_B_DATA_REG0 0X0000C038 + +#define XAVBUF_AUD_CH_B_DATA_REG0_USER_DATA0_SHIFT 0 +#define XAVBUF_AUD_CH_B_DATA_REG0_USER_DATA0_WIDTH 32 +#define XAVBUF_AUD_CH_B_DATA_REG0_USER_DATA0_MASK 0XFFFFFFFF + +/** + * * Register: XAVBUF_AUD_CH_B_DATA_REG1 + * */ +#define XAVBUF_AUD_CH_B_DATA_REG1 0X0000C03C + +#define XAVBUF_AUD_CH_B_DATA_REG1_USER_DATA1_SHIFT 0 +#define XAVBUF_AUD_CH_B_DATA_REG1_USER_DATA1_WIDTH 32 +#define XAVBUF_AUD_CH_B_DATA_REG1_USER_DATA1_MASK 0XFFFFFFFF + +/** + * * Register: XAVBUF_AUD_CH_B_DATA_REG2 + * */ +#define XAVBUF_AUD_CH_B_DATA_REG2 0X0000C040 + +#define XAVBUF_AUD_CH_B_DATA_REG2_USER_DATA2_SHIFT 0 +#define XAVBUF_AUD_CH_B_DATA_REG2_USER_DATA2_WIDTH 32 +#define XAVBUF_AUD_CH_B_DATA_REG2_USER_DATA2_MASK 0XFFFFFFFF + +/** + * * Register: XAVBUF_AUD_CH_B_DATA_REG3 + * */ +#define XAVBUF_AUD_CH_B_DATA_REG3 0X0000C044 + +#define XAVBUF_AUD_CH_B_DATA_REG3_USER_DATA3_SHIFT 0 +#define XAVBUF_AUD_CH_B_DATA_REG3_USER_DATA3_WIDTH 32 +#define XAVBUF_AUD_CH_B_DATA_REG3_USER_DATA3_MASK 0XFFFFFFFF + +/** + * * Register: XAVBUF_AUD_CH_B_DATA_REG4 + * */ +#define XAVBUF_AUD_CH_B_DATA_REG4 0X0000C048 + +#define XAVBUF_AUD_CH_B_DATA_REG4_USER_DATA4_SHIFT 0 +#define XAVBUF_AUD_CH_B_DATA_REG4_USER_DATA4_WIDTH 32 +#define XAVBUF_AUD_CH_B_DATA_REG4_USER_DATA4_MASK 0XFFFFFFFF + +/** + * * Register: XAVBUF_AUD_CH_B_DATA_REG5 + * */ +#define XAVBUF_AUD_CH_B_DATA_REG5 0X0000C04C + +#define XAVBUF_AUD_CH_B_DATA_REG5_USER_DATA5_SHIFT 0 +#define XAVBUF_AUD_CH_B_DATA_REG5_USER_DATA5_WIDTH 32 +#define XAVBUF_AUD_CH_B_DATA_REG5_USER_DATA5_MASK 0XFFFFFFFF + +/** + * * Register: XAVBUF_AUD_SOFT_RST + * */ +#define XAVBUF_AUD_SOFT_RST 0X0000CC00 + +#define XAVBUF_AUD_SOFT_RST_EXTRA_BS_CONTROL_SHIFT 2 +#define XAVBUF_AUD_SOFT_RST_EXTRA_BS_CONTROL_WIDTH 1 +#define XAVBUF_AUD_SOFT_RST_EXTRA_BS_CONTROL_MASK 0X00000004 + +#define XAVBUF_AUD_SOFT_RST_LINE_RST_DISABLE_SHIFT 1 +#define XAVBUF_AUD_SOFT_RST_LINE_RST_DISABLE_WIDTH 1 +#define XAVBUF_AUD_SOFT_RST_LINE_RST_DISABLE_MASK 0X00000002 + +#define XAVBUF_AUD_SOFT_RST_AUD_SRST_SHIFT 0 +#define XAVBUF_AUD_SOFT_RST_AUD_SRST_WIDTH 1 +#define XAVBUF_AUD_SOFT_RST_AUD_SRST_MASK 0X00000001 + +/** + * * Register: XAVBUF_PATGEN_CRC_R + * */ +#define XAVBUF_PATGEN_CRC_R 0X0000CC10 + +#define XAVBUF_PATGEN_CRC_R_CRC_R_SHIFT 0 +#define XAVBUF_PATGEN_CRC_R_CRC_R_WIDTH 16 +#define XAVBUF_PATGEN_CRC_R_CRC_R_MASK 0X0000FFFF + +/** + * * Register: XAVBUF_PATGEN_CRC_G + * */ +#define XAVBUF_PATGEN_CRC_G 0X0000CC14 + +#define XAVBUF_PATGEN_CRC_G_CRC_G_SHIFT 0 +#define XAVBUF_PATGEN_CRC_G_CRC_G_WIDTH 16 +#define XAVBUF_PATGEN_CRC_G_CRC_G_MASK 0X0000FFFF + +/** + * * Register: XAVBUF_PATGEN_CRC_B + * */ +#define XAVBUF_PATGEN_CRC_B 0X0000CC18 + +#define XAVBUF_PATGEN_CRC_B_CRC_B_SHIFT 0 +#define XAVBUF_PATGEN_CRC_B_CRC_B_WIDTH 16 +#define XAVBUF_PATGEN_CRC_B_CRC_B_MASK 0X0000FFFF + +#define XAVBUF_NUM_SUPPORTED 52 + +#define XAVBUF_BUF_4BIT_SF 0x11111 +#define XAVBUF_BUF_5BIT_SF 0x10842 +#define XAVBUF_BUF_6BIT_SF 0x10410 +#define XAVBUF_BUF_8BIT_SF 0x10101 +#define XAVBUF_BUF_10BIT_SF 0x10040 +#define XAVBUF_BUF_12BIT_SF 0x10000 + +#define XAVBUF_BUF_6BPC 0x000 +#define XAVBUF_BUF_8BPC 0x001 +#define XAVBUF_BUF_10BPC 0x010 +#define XAVBUF_BUF_12BPC 0x011 + +#define XAVBUF_CHBUF_V_BURST_LEN 0xF +#define XAVBUF_CHBUF_A_BURST_LEN 0x3 + +#define XAVBUF_PL_CLK 0x0 +#define XAVBUF_PS_CLK 0x1 + +#define XAVBUF_NUM_SUPPORTED_NLVID 25 +#define XAVBUF_NUM_SUPPORTED_NLGFX 14 +#define XAVBUF_NUM_SUPPORTED_LIVE 14 +#define XAVBUF_NUM_OUTPUT_FORMATS 14 + +/** + * Address mapping for PLL (CRF and CRL) + */ + +/* Base Address for CLOCK in FPD. */ +#define XAVBUF_CLK_FPD_BASEADDR 0XFD1A0000 + +/* Base Address for CLOCK in LPD. */ +#define XAVBUF_CLK_LPD_BASEADDR 0XFF5E0000 + +/** + * The following constants define values to manipulate + * the bits of the VPLL control register. + */ +#define XAVBUF_PLL_CTRL 0X00000020 + +#define XAVBUF_PLL_CTRL_POST_SRC_SHIFT 24 +#define XAVBUF_PLL_CTRL_POST_SRC_WIDTH 3 +#define XAVBUF_PLL_CTRL_POST_SRC_MASK 0X07000000 + +#define XAVBUF_PLL_CTRL_PRE_SRC_SHIFT 20 +#define XAVBUF_VPLL_CTRL_PRE_SRC_WIDTH 3 +#define XAVBUF_VPLL_CTRL_PRE_SRC_MASK 0X00700000 + +#define XAVBUF_PLL_CTRL_CLKOUTDIV_SHIFT 17 +#define XAVBUF_PLL_CTRL_CLKOUTDIV_WIDTH 1 +#define XAVBUF_PLL_CTRL_CLKOUTDIV_MASK 0X00020000 + +#define XAVBUF_PLL_CTRL_DIV2_SHIFT 16 +#define XAVBUF_PLL_CTRL_DIV2_WIDTH 1 +#define XAVBUF_PLL_CTRL_DIV2_MASK 0X00010000 + +#define XAVBUF_PLL_CTRL_FBDIV_SHIFT 8 +#define XAVBUF_PLL_CTRL_FBDIV_WIDTH 7 +#define XAVBUF_PLL_CTRL_FBDIV_MASK 0X00007F00 + +#define XAVBUF_PLL_CTRL_BYPASS_SHIFT 3 +#define XAVBUF_PLL_CTRL_BYPASS_WIDTH 1 +#define XAVBUF_PLL_CTRL_BYPASS_MASK 0X00000008 + +#define XAVBUF_PLL_CTRL_RESET_SHIFT 0 +#define XAVBUF_PLL_CTRL_RESET_WIDTH 1 +#define XAVBUF_PLL_CTRL_RESET_MASK 0X00000001 + +/** + * The following constants define values to manipulate + * the bits of the PLL config register. + */ +#define XAVBUF_PLL_CFG 0X00000024 + +#define XAVBUF_PLL_CFG_LOCK_DLY_SHIFT 25 +#define XAVBUF_PLL_CFG_LOCK_DLY_WIDTH 7 +#define XAVBUF_PLL_CFG_LOCK_DLY_MASK 0XFE000000 + +#define XAVBUF_PLL_CFG_LOCK_CNT_SHIFT 13 +#define XAVBUF_PLL_CFG_LOCK_CNT_WIDTH 10 +#define XAVBUF_PLL_CFG_LOCK_CNT_MASK 0X007FE000 + +#define XAVBUF_PLL_CFG_LFHF_SHIFT 10 +#define XAVBUF_PLL_CFG_LFHF_WIDTH 2 +#define XAVBUF_PLL_CFG_LFHF_MASK 0X00000C00 + +#define XAVBUF_PLL_CFG_CP_SHIFT 5 +#define XAVBUF_PLL_CFG_CP_WIDTH 4 +#define XAVBUF_PLL_CFG_CP_MASK 0X000001E0 + +#define XAVBUF_PLL_CFG_RES_SHIFT 0 +#define XAVBUF_PLL_CFG_RES_WIDTH 4 +#define XAVBUF_PLL_CFG_RES_MASK 0X0000000F + +/** + * The following constants define values to manipulate + * the bits of the VPLL fractional config register. + */ +#define XAVBUF_PLL_FRAC_CFG 0X00000028 + +#define XAVBUF_PLL_FRAC_CFG_ENABLED_SHIFT 31 +#define XAVBUF_PLL_FRAC_CFG_ENABLED_WIDTH 1 +#define XAVBUF_PLL_FRAC_CFG_ENABLED_MASK 0X80000000 + +#define XAVBUF_PLL_FRAC_CFG_SEED_SHIFT 22 +#define XAVBUF_PLL_FRAC_CFG_SEED_WIDTH 3 +#define XAVBUF_PLL_FRAC_CFG_SEED_MASK 0X01C00000 + +#define XAVBUF_PLL_FRAC_CFG_ALGRTHM_SHIFT 19 +#define XAVBUF_PLL_FRAC_CFG_ALGRTHM_WIDTH 1 +#define XAVBUF_PLL_FRAC_CFG_ALGRTHM_MASK 0X00080000 + +#define XAVBUF_PLL_FRAC_CFG_ORDER_SHIFT 18 +#define XAVBUF_PLL_FRAC_CFG_ORDER_WIDTH 1 +#define XAVBUF_PLL_FRAC_CFG_ORDER_MASK 0X00040000 + +#define XAVBUF_PLL_FRAC_CFG_DATA_SHIFT 0 +#define XAVBUF_PLL_FRAC_CFG_DATA_WIDTH 16 +#define XAVBUF_PLL_FRAC_CFG_DATA_MASK 0X0000FFFF + +/** + * The following constants define values to manipulate + * the bits of the PLL STATUS register. + */ +#define XAVBUF_PLL_STATUS 0X00000044 + +#define XAVBUF_PLL_STATUS_VPLL_STABLE_SHIFT 5 +#define XAVBUF_PLL_STATUS_VPLL_STABLE_WIDTH 1 +#define XAVBUF_PLL_STATUS_VPLL_STABLE_MASK 0X00000020 + +#define XAVBUF_PLL_STATUS_DPLL_STABLE_SHIFT 4 +#define XAVBUF_PLL_STATUS_DPLL_STABLE_WIDTH 1 +#define XAVBUF_PLL_STATUS_DPLL_STABLE_MASK 0X00000010 + +#define XAVBUF_PLL_STATUS_APLL_STABLE_SHIFT 3 +#define XAVBUF_PLL_STATUS_APLL_STABLE_WIDTH 1 +#define XAVBUF_PLL_STATUS_APLL_STABLE_MASK 0X00000008 + +#define XAVBUF_PLL_STATUS_VPLL_LOCK_SHIFT 2 +#define XAVBUF_PLL_STATUS_VPLL_LOCK_WIDTH 1 +#define XAVBUF_PLL_STATUS_VPLL_LOCK_MASK 0X00000004 + +#define XAVBUF_PLL_STATUS_DPLL_LOCK_SHIFT 1 +#define XAVBUF_PLL_STATUS_DPLL_LOCK_WIDTH 1 +#define XAVBUF_PLL_STATUS_DPLL_LOCK_MASK 0X00000002 + +#define XAVBUF_PLL_STATUS_APLL_LOCK_SHIFT 0 +#define XAVBUF_PLL_STATUS_APLL_LOCK_WIDTH 1 +#define XAVBUF_PLL_STATUS_APLL_LOCK_MASK 0X00000001 + +/** + * The following constants define values to manipulate + * the bits of the VIDEO reference control register. + */ +#define XAVBUF_VIDEO_REF_CTRL 0X00000070 + +#define XAVBUF_VIDEO_REF_CTRL_CLKACT_SHIFT 24 +#define XAVBUF_VIDEO_REF_CTRL_CLKACT_WIDTH 1 +#define XAVBUF_VIDEO_REF_CTRL_CLKACT_MASK 0X01000000 + +#define XAVBUF_VIDEO_REF_CTRL_DIVISOR1_SHIFT 16 +#define XAVBUF_VIDEO_REF_CTRL_DIVISOR1_WIDTH 6 +#define XAVBUF_VIDEO_REF_CTRL_DIVISOR1_MASK 0X003F0000 + +#define XAVBUF_VIDEO_REF_CTRL_DIVISOR0_SHIFT 8 +#define XAVBUF_VIDEO_REF_CTRL_DIVISOR0_WIDTH 6 +#define XAVBUF_VIDEO_REF_CTRL_DIVISOR0_MASK 0X00003F00 + +#define XAVBUF_VIDEO_REF_CTRL_SRCSEL_SHIFT 0 +#define XAVBUF_VIDEO_REF_CTRL_SRCSEL_WIDTH 3 +#define XAVBUF_VIDEO_REF_CTRL_SRCSEL_MASK 0X00000007 + +/** + * The following constants define values to manipulate + * the bits of the AUDIO reference control register. + */ +#define XAVBUF_AUDIO_REF_CTRL 0X00000074 + +#define XAVBUF_AUDIO_REF_CTRL_CLKACT_SHIFT 24 +#define XAVBUF_AUDIO_REF_CTRL_CLKACT_WIDTH 1 +#define XAVBUF_AUDIO_REF_CTRL_CLKACT_MASK 0X01000000 + +#define XAVBUF_AUDIO_REF_CTRL_DIVISOR1_SHIFT 16 +#define XAVBUF_AUDIO_REF_CTRL_DIVISOR1_WIDTH 6 +#define XAVBUF_AUDIO_REF_CTRL_DIVISOR1_MASK 0X003F0000 + +#define XAVBUF_AUDIO_REF_CTRL_DIVISOR0_SHIFT 8 +#define XAVBUF_AUDIO_REF_CTRL_DIVISOR0_WIDTH 6 +#define XAVBUF_AUDIO_REF_CTRL_DIVISOR0_MASK 0X00003F00 + +#define XAVBUF_AUDIO_REF_CTRL_SRCSEL_SHIFT 0 +#define XAVBUF_AUDIO_REF_CTRL_SRCSEL_WIDTH 3 +#define XAVBUF_AUDIO_REF_CTRL_SRCSEL_MASK 0X00000007 + +/** + * The following constants define values to manipulate + * the bits of the Domain Switch register. + * For eg. FPD to LPD. + */ +#define XAVBUF_DOMAIN_SWITCH_CTRL 0X00000044 + +#define XAVBUF_DOMAIN_SWITCH_DIVISOR0_SHIFT 8 +#define XAVBUF_DOMAIN_SWITCH_DIVISOR0_WIDTH 6 +#define XAVBUF_DOMAIN_SWITCH_DIVISOR0_MASK 0X00003F00 + +/** + * The following constants define values to Reference + * clock. + */ +#define XAVBUF_Pss_Ref_Clk 0 +#define XAVBUF_Video_Clk 4 +#define XAVBUF_Pss_alt_Ref_Clk 5 +#define XAVBUF_Aux_Ref_clk 6 +#define XAVBUF_Gt_Crx_Ref_Clk 7 + +/** + * The following constants define values to manipulate + * the bits of any register. + */ +#define XAVBUF_ENABLE_BIT 1 +#define XAVBUF_DISABLE_BIT 0 + +/** + * The following constants define values available + * PLL source to Audio and Video. + */ +#define XAVBUF_VPLL_SRC_SEL 0 +#define XAVBUF_DPLL_SRC_SEL 2 +#define XAVBUF_RPLL_TO_FPD_SRC_SEL 3 + +/******************* Macros (Inline Functions) Definitions ********************/ + +/** @name Register access macro definitions. + * @{ + */ +#define XAVBuf_In32 Xil_In32 +#define XAVBuf_Out32 Xil_Out32 +/* @} */ + +/******************************************************************************/ +/** + * This is a low-level function that reads from the specified register. + * + * @param BaseAddress is the base address of the device. + * @param RegOffset is the register offset to be read from. + * + * @return The 32-bit value of the specified register. + * + * @note C-style signature: + * u32 XAVBuf_ReadReg(u32 BaseAddress, u32 RegOffset) + * +*******************************************************************************/ +#define XAVBuf_ReadReg(BaseAddress, RegOffset) \ + XAVBuf_In32((BaseAddress) + (RegOffset)) + +/******************************************************************************/ +/** + * This is a low-level function that writes to the specified register. + * + * @param BaseAddress is the base address of the device. + * @param RegOffset is the register offset to write to. + * @param Data is the 32-bit data to write to the specified register. + * + * @return None. + * + * @note C-style signature: + * void XAVBuf_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data) + * +*******************************************************************************/ +#define XAVBuf_WriteReg(BaseAddress, RegOffset, Data) \ + XAVBuf_Out32((BaseAddress) + (RegOffset), (Data)) + + +#ifdef __cplusplus +} +#endif + + +#endif //XAVBUF_H_ diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/avbuf_v2_1/src/xavbuf_videoformats.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/avbuf_v2_1/src/xavbuf_videoformats.c new file mode 100644 index 000000000..4651cd8d4 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/avbuf_v2_1/src/xavbuf_videoformats.c @@ -0,0 +1,227 @@ +/******************************************************************************* + * + * Copyright (C) 2017 Xilinx, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * Use of the Software is limited solely to applications: + * (a) running on a Xilinx device, or + * (b) that interact with a Xilinx device through a bus or interconnect. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of the Xilinx shall not be used + * in advertising or otherwise to promote the sale, use or other dealings in + * this Software without prior written authorization from Xilinx. + * +*******************************************************************************/ +/******************************************************************************/ +/** + * + * @file xavbuf_videoformats.c + * @addtogroup xavbuf_v2_1 + * @{ + * + * Contains attributes of the video formats mapped to the hardware + * + * @note None. + * + * 
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -----------------------------------------------
+ * 1.0   aad  03/10/17 Initial release.
+ * 2.0   aad  02/22/18 Fixed scaling factors and bits per pixel
+ *
+ * +*******************************************************************************/ + +/******************************* Include Files ********************************/ + +#include "xavbuf.h" + + +/**************************** Variable Definitions ****************************/ +#ifdef __cplusplus +extern "C" +#endif + +const XAVBuf_VideoAttribute XAVBuf_SupportedFormats[XAVBUF_NUM_SUPPORTED] = +{ + /* Non - Live Video Formats */ + { CbY0CrY1, 0, Interleaved, + {XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF}, + TRUE, FALSE, FALSE, 16}, + { CrY0CbY1, 1, Interleaved, + {XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF}, + TRUE, FALSE, FALSE, 16}, + { Y0CrY1Cb, 2, Interleaved, + {XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF}, + TRUE, FALSE, FALSE, 16}, + { Y0CbY1Cr, 3, Interleaved, + {XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF}, + TRUE, FALSE, FALSE, 16}, + { YV16, 4, Planar, + {XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF}, + TRUE, FALSE, FALSE, 16}, + { YV24, 5, Planar, + {XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF}, + FALSE, FALSE, FALSE, 24}, + { YV16Ci, 6, SemiPlanar, + {XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF}, + TRUE, FALSE, FALSE, 16}, + { MONOCHROME, 7, Interleaved, + {XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF}, + TRUE, FALSE, FALSE, 8}, + { YV16Ci2, 8, SemiPlanar, + {XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF}, + TRUE, FALSE, TRUE, 16}, + { YUV444, 9, Interleaved, + {XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF}, + FALSE, FALSE, FALSE, 24}, + { RGB888, 10, Interleaved, + {XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF}, + FALSE, TRUE, FALSE, 24}, + { RGBA8880, 11, Interleaved, + {XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF}, + FALSE, TRUE, FALSE, 32}, + { RGB888_10BPC, 12, Interleaved, + {XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF}, + FALSE, TRUE, FALSE, 30}, + { YUV444_10BPC, 13, Interleaved, + {XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF}, + FALSE, FALSE, FALSE, 30}, + { YV16Ci2_10BPC, 14, SemiPlanar, + {XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF}, + TRUE, FALSE, TRUE, 20}, + { YV16Ci_10BPC, 15, SemiPlanar, + {XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF}, + TRUE, FALSE, FALSE, 20}, + { YV16_10BPC, 16, Planar, + {XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF}, + TRUE, FALSE, FALSE, 20}, + { YV24_10BPC, 17, Planar, + {XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF}, + FALSE, FALSE, FALSE, 30}, + { MONOCHROME_10BPC, 18, Interleaved, + {XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF}, + TRUE, FALSE, FALSE, 10}, + { YV16_420, 19, Planar, + {XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF}, + TRUE, FALSE, FALSE, 16}, + { YV16Ci_420, 20, SemiPlanar, + {XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF}, + TRUE, FALSE, FALSE, 16}, + { YV16Ci2_420, 21, SemiPlanar, + {XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF}, + TRUE, FALSE, TRUE, 16}, + { YV16_420_10BPC, 22, Planar, + {XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF}, + TRUE, FALSE, FALSE, 20}, + { YV16Ci_420_10BPC, 23, SemiPlanar, + {XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF}, + TRUE, FALSE, FALSE, 20}, + { YV16Ci2_420_10BPC, 24, SemiPlanar, + {XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF}, + TRUE, FALSE, TRUE, 20}, + + /* Non-Live Graphics formats */ + { RGBA8888, 0, Interleaved, + {XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF}, + FALSE, TRUE, FALSE, 32}, + { ABGR8888, 1, Interleaved, + {XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF}, + FALSE, TRUE, FALSE, 32}, + { RGB888_GFX, 2, Interleaved, + {XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF}, + FALSE, TRUE, FALSE, 24}, + { BGR888, 3, Interleaved, + {XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF}, + FALSE, TRUE, FALSE, 24}, + { RGBA5551, 4, Interleaved, + {XAVBUF_BUF_5BIT_SF, XAVBUF_BUF_5BIT_SF, XAVBUF_BUF_5BIT_SF}, + FALSE, TRUE, FALSE, 16}, + { RGBA4444, 5, Interleaved, + {XAVBUF_BUF_4BIT_SF, XAVBUF_BUF_4BIT_SF, XAVBUF_BUF_4BIT_SF}, + FALSE, TRUE, FALSE, 16}, + { RGB565, 6, Interleaved, + {XAVBUF_BUF_5BIT_SF, XAVBUF_BUF_6BIT_SF, XAVBUF_BUF_5BIT_SF}, + FALSE, TRUE, FALSE, 16}, + { BPP8, 7, Interleaved, + {XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF}, + FALSE, TRUE, FALSE, 8}, + { BPP4, 8, Interleaved, + {XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF}, + FALSE, TRUE, FALSE, 4}, + { BPP2, 9, Interleaved, + {XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF}, + FALSE, TRUE, FALSE, 2}, + { BPP1, 10, Interleaved, + {XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF}, + FALSE, TRUE, FALSE, 1}, + { YUV422, 11, Interleaved, + {XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF}, + FALSE, FALSE, FALSE, 24}, + + /* Video Formats for Live Video/Graphics input and output sources */ + { RGB_6BPC, 0, Interleaved, + {XAVBUF_BUF_6BIT_SF, XAVBUF_BUF_6BIT_SF, XAVBUF_BUF_6BIT_SF}, + FALSE, TRUE, FALSE, 18}, + { RGB_8BPC, 0, Interleaved, + {XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF}, + FALSE, TRUE, FALSE, 24}, + { RGB_10BPC, 0, Interleaved, + {XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF}, + FALSE, TRUE, FALSE, 30}, + { RGB_12BPC, 0, Interleaved, + {XAVBUF_BUF_12BIT_SF, XAVBUF_BUF_12BIT_SF, XAVBUF_BUF_12BIT_SF}, + FALSE, TRUE, FALSE, 36}, + { YCbCr444_6BPC, 1, Interleaved, + {XAVBUF_BUF_6BIT_SF, XAVBUF_BUF_6BIT_SF, XAVBUF_BUF_6BIT_SF}, + FALSE, FALSE, FALSE, 18}, + { YCbCr444_8BPC, 1, Interleaved, + {XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF}, + FALSE, FALSE, FALSE, 24}, + { YCbCr444_10BPC, 1, Interleaved, + {XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF}, + FALSE, FALSE, FALSE, 30}, + { YCbCr444_12BPC, 1, Interleaved, + {XAVBUF_BUF_12BIT_SF, XAVBUF_BUF_12BIT_SF, XAVBUF_BUF_12BIT_SF}, + FALSE, FALSE, FALSE, 36}, + { YCbCr422_8BPC, 2, Interleaved, + {XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF}, + TRUE, FALSE, FALSE, 24}, + { YCbCr422_10BPC, 2, Interleaved, + {XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF}, + TRUE, FALSE, FALSE, 30}, + { YCbCr422_12BPC, 2, Interleaved, + {XAVBUF_BUF_12BIT_SF, XAVBUF_BUF_12BIT_SF, XAVBUF_BUF_12BIT_SF}, + TRUE, FALSE, FALSE, 36}, + { YOnly_8BPC, 3, Interleaved, + {XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF, XAVBUF_BUF_8BIT_SF}, + TRUE, FALSE, FALSE, 24}, + { YOnly_10BPC, 3, Interleaved, + {XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF, XAVBUF_BUF_10BIT_SF}, + TRUE, FALSE, FALSE, 30}, + { YOnly_12BPC, 3, Interleaved, + {XAVBUF_BUF_12BIT_SF, XAVBUF_BUF_12BIT_SF, XAVBUF_BUF_12BIT_SF}, + TRUE, FALSE, FALSE, 36}, + +}; + +/** @} */ diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_5/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_5/src/Makefile deleted file mode 100644 index 926b20c4e..000000000 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_5/src/Makefile +++ /dev/null @@ -1,27 +0,0 @@ -COMPILER= -ARCHIVER= -CP=cp -COMPILER_FLAGS= -EXTRA_COMPILER_FLAGS= -LIB=libxil.a - -RELEASEDIR=../../../lib -INCLUDEDIR=../../../include -INCLUDES=-I./. -I${INCLUDEDIR} - -INCLUDEFILES=*.h -LIBSOURCES=*.c -OUTS = *.o - - -libs: - echo "Compiling axipmon" - $(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES) - $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS} - make clean - -include: - ${CP} ${INCLUDEFILES} ${INCLUDEDIR} - -clean: - rm -rf ${OUTS} diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_6/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_6/src/Makefile new file mode 100644 index 000000000..8c401268f --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_6/src/Makefile @@ -0,0 +1,40 @@ +COMPILER= +ARCHIVER= +CP=cp +COMPILER_FLAGS= +EXTRA_COMPILER_FLAGS= +LIB=libxil.a + +CC_FLAGS = $(COMPILER_FLAGS) +ECC_FLAGS = $(EXTRA_COMPILER_FLAGS) + +RELEASEDIR=../../../lib +INCLUDEDIR=../../../include +INCLUDES=-I./. -I${INCLUDEDIR} + +OUTS = *.o + +LIBSOURCES:=*.c +INCLUDEFILES:=*.h + +OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c))) + +libs: banner xaxipmon_libs clean + +%.o: %.c + ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $< + +banner: + echo "Compiling axipmon" + +xaxipmon_libs: ${OBJECTS} + $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS} + +.PHONY: include +include: xaxipmon_includes + +xaxipmon_includes: + ${CP} ${INCLUDEFILES} ${INCLUDEDIR} + +clean: + rm -rf ${OBJECTS} diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/axipmon_v6_5/src/xaxipmon.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_6/src/xaxipmon.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/axipmon_v6_5/src/xaxipmon.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_6/src/xaxipmon.c index fbb867839..fc5d99fd2 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/axipmon_v6_5/src/xaxipmon.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_6/src/xaxipmon.c @@ -33,7 +33,7 @@ /** * * @file xaxipmon.c -* @addtogroup axipmon_v6_3 +* @addtogroup axipmon_v6_6 * @{ * * This file contains the driver API functions that can be used to access diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_5/src/xaxipmon.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_6/src/xaxipmon.h similarity index 98% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_5/src/xaxipmon.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_6/src/xaxipmon.h index f8d4d6467..ea347e07c 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_5/src/xaxipmon.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_6/src/xaxipmon.h @@ -33,7 +33,7 @@ /** * * @file xaxipmon.h -* @addtogroup axipmon_v6_3 +* @addtogroup axipmon_v6_6 * @{ * @details * @@ -253,6 +253,14 @@ * 6.3 kvn 07/02/15 Modified code according to MISRA-C:2012 guidelines. * 6.4 sk 11/10/15 Used UINTPTR instead of u32 for Baseaddress CR# 867425. * Changed the prototype of XAxiPmon_CfgInitialize API. +* 6.5 ms 01/23/17 Modified xil_printf statement in main function for all +* examples to ensure that "Successfully ran" and "Failed" +* strings are available in all examples. This is a fix +* for CR-965028. +* ms 03/17/17 Added readme.txt file in examples folder for doxygen +* generation. +* 6.6 ms 04/18/17 Modified tcl file to add suffix U for all macro +* definitions of axipmon in xparameters.h * * *****************************************************************************/ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/axipmon_v6_5/src/xaxipmon_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_6/src/xaxipmon_g.c similarity index 94% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/axipmon_v6_5/src/xaxipmon_g.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_6/src/xaxipmon_g.c index 2bd473dd5..b54becbef 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/axipmon_v6_5/src/xaxipmon_g.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_6/src/xaxipmon_g.c @@ -5,7 +5,7 @@ * Version: * DO NOT EDIT. * -* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.* +* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.* *Permission is hereby granted, free of charge, to any person obtaining a copy *of this software and associated documentation files (the Software), to deal *in the Software without restriction, including without limitation the rights @@ -44,7 +44,7 @@ * The configuration table for devices */ -XAxiPmon_Config XAxiPmon_ConfigTable[] = +XAxiPmon_Config XAxiPmon_ConfigTable[XPAR_XAXIPMON_NUM_INSTANCES] = { { XPAR_PSU_APM_0_DEVICE_ID, diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_5/src/xaxipmon_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_6/src/xaxipmon_hw.h similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_5/src/xaxipmon_hw.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_6/src/xaxipmon_hw.h index 68ed57aaf..b5d20f57f 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_5/src/xaxipmon_hw.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_6/src/xaxipmon_hw.h @@ -33,7 +33,7 @@ /** * * @file xaxipmon_hw.h -* @addtogroup axipmon_v6_3 +* @addtogroup axipmon_v6_6 * @{ * * This header file contains identifiers and basic driver functions (or diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_5/src/xaxipmon_selftest.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_6/src/xaxipmon_selftest.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_5/src/xaxipmon_selftest.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_6/src/xaxipmon_selftest.c index df2a9da66..7a6679140 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_5/src/xaxipmon_selftest.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_6/src/xaxipmon_selftest.c @@ -33,7 +33,7 @@ /** * * @file xaxipmon_selftest.c -* @addtogroup axipmon_v6_3 +* @addtogroup axipmon_v6_6 * @{ * * This file contains a diagnostic self test function for the XAxiPmon driver. diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_5/src/xaxipmon_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_6/src/xaxipmon_sinit.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_5/src/xaxipmon_sinit.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_6/src/xaxipmon_sinit.c index 737d80b48..2494aea8c 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_5/src/xaxipmon_sinit.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_6/src/xaxipmon_sinit.c @@ -33,7 +33,7 @@ /** * * @file xaxipmon_sinit.c -* @addtogroup axipmon_v6_3 +* @addtogroup axipmon_v6_6 * @{ * * This file contains the implementation of the XAxiPmon driver's static diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps.c index 243b3a81b..f852de4e6 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps.c @@ -33,7 +33,7 @@ /** * * @file xcanps.c -* @addtogroup canps_v3_0 +* @addtogroup canps_v3_2 * @{ * * Functions in this file are the minimum required functions for the XCanPs diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps.h index b180e37ec..9feb45eea 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps.h @@ -33,7 +33,7 @@ /** * * @file xcanps.h -* @addtogroup canps_v3_0 +* @addtogroup canps_v3_2 * @{ * @details * @@ -204,6 +204,8 @@ * Data mismatch while sending data less than 8 bytes. * 3.1 nsk 12/21/15 Updated XCanPs_IntrHandler in xcanps_intr.c to handle * error interrupts correctly. CR#925615 +* ms 03/17/17 Added readme.txt file in examples folder for doxygen +* generation. * * ******************************************************************************/ diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps_g.c index 4063a44eb..0ed8cd17c 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps_g.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps_g.c @@ -5,7 +5,7 @@ * Version: * DO NOT EDIT. * -* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.* +* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.* *Permission is hereby granted, free of charge, to any person obtaining a copy *of this software and associated documentation files (the Software), to deal *in the Software without restriction, including without limitation the rights @@ -44,7 +44,7 @@ * The configuration table for devices */ -XCanPs_Config XCanPs_ConfigTable[] = +XCanPs_Config XCanPs_ConfigTable[XPAR_XCANPS_NUM_INSTANCES] = { { XPAR_PSU_CAN_1_DEVICE_ID, diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps_hw.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps_hw.c index bbb96120a..7ca2f81eb 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps_hw.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps_hw.c @@ -33,7 +33,7 @@ /** * * @file xcanps_hw.c -* @addtogroup canps_v3_0 +* @addtogroup canps_v3_2 * @{ * * This file contains the implementation of the canps interface reset sequence diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps_hw.h index 9fe681aaf..30ec68ab9 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps_hw.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps_hw.h @@ -33,7 +33,7 @@ /** * * @file xcanps_hw.h -* @addtogroup canps_v3_0 +* @addtogroup canps_v3_2 * @{ * * This header file contains the identifiers and basic driver functions (or diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps_intr.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps_intr.c index f6721ca75..715b35eb2 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps_intr.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps_intr.c @@ -33,7 +33,7 @@ /** * * @file xcanps_intr.c -* @addtogroup canps_v3_0 +* @addtogroup canps_v3_2 * @{ * * This file contains functions related to CAN interrupt handling. diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps_selftest.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps_selftest.c index 48a6f4031..26c9fcb68 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps_selftest.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps_selftest.c @@ -33,7 +33,7 @@ /** * * @file xcanps_selftest.c -* @addtogroup canps_v3_0 +* @addtogroup canps_v3_2 * @{ * * This file contains a diagnostic self-test function for the XCanPs driver. diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps_sinit.c index 230c429b3..5321669d7 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps_sinit.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_2/src/xcanps_sinit.c @@ -33,7 +33,7 @@ /** * * @file xcanps_sinit.c -* @addtogroup canps_v3_0 +* @addtogroup canps_v3_2 * @{ * * This file contains the implementation of the XCanPs driver's static diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/coresightps_dcc_v1_3/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/coresightps_dcc_v1_4/src/Makefile similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/coresightps_dcc_v1_3/src/Makefile rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/coresightps_dcc_v1_4/src/Makefile diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_2/src/xcoresightpsdcc.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/coresightps_dcc_v1_4/src/xcoresightpsdcc.c similarity index 92% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_2/src/xcoresightpsdcc.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/coresightps_dcc_v1_4/src/xcoresightpsdcc.c index e999f6f5d..fca26ca2e 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_2/src/xcoresightpsdcc.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/coresightps_dcc_v1_4/src/xcoresightpsdcc.c @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* Copyright (C) 2015-2016 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -33,7 +33,7 @@ /** * * @file xcoresightpsdcc.c -* @addtogroup coresightps_dcc_v1_1 +* @addtogroup coresightps_dcc_v1_4 * @{ * * Functions in this file are the minimum required functions for the @@ -51,12 +51,18 @@ * 1.1 kvn 06/12/15 Add support for Zynq Ultrascale+ MP. * kvn 08/18/15 Modified Makefile according to compiler changes. * 1.2 kvn 10/09/15 Add support for IAR Compiler. +* 1.3 asa 07/01/16 Made changes to ensure that the file does not compile +* for MB BSPs. Instead it throws up a warning. This +* fixes the CR#953056. * * * ******************************************************************************/ /***************************** Include Files *********************************/ +#ifdef __MICROBLAZE__ +#warning "The driver is supported only for ARM architecture" +#else #include #include @@ -126,7 +132,7 @@ void XCoresightPs_DccSendByte(u32 BaseAddress, u8 Data) ******************************************************************************/ u8 XCoresightPs_DccRecvByte(u32 BaseAddress) { - u8 Data; + u8 Data = 0U; (void) BaseAddress; while (!(XCoresightPs_DccGetStatus() & XCORESIGHTPS_DCC_STATUS_RX)) @@ -163,7 +169,7 @@ u8 XCoresightPs_DccRecvByte(u32 BaseAddress) ******************************************************************************/ static INLINE u32 XCoresightPs_DccGetStatus(void) { - u32 Status; + u32 Status = 0U; #ifdef __aarch64__ asm volatile ("mrs %0, mdccsr_el0" : "=r" (Status)); @@ -177,5 +183,6 @@ static INLINE u32 XCoresightPs_DccGetStatus(void) } #endif return Status; +#endif } /** @} */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_2/src/xcoresightpsdcc.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/coresightps_dcc_v1_4/src/xcoresightpsdcc.h similarity index 91% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_2/src/xcoresightpsdcc.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/coresightps_dcc_v1_4/src/xcoresightpsdcc.h index 6bab7ae09..67959e327 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_2/src/xcoresightpsdcc.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/coresightps_dcc_v1_4/src/xcoresightpsdcc.h @@ -33,7 +33,7 @@ /** * * @file xcoresightpsdcc.h -* @addtogroup coresightps_dcc_v1_1 +* @addtogroup coresightps_dcc_v1_4 * @{ * @details * @@ -55,16 +55,20 @@ * 1.00 kvn 02/14/15 First release * 1.1 kvn 06/12/15 Add support for Zynq Ultrascale+ MP. * kvn 08/18/15 Modified Makefile according to compiler changes. +* 1.3 asa 07/01/16 Made changes to ensure that the file does not compile +* for MB BSPs. Instead it throws up a warning. This +* fixes the CR#953056. * * * ******************************************************************************/ /***************************** Include Files *********************************/ - +#ifndef __MICROBLAZE__ #include void XCoresightPs_DccSendByte(u32 BaseAddress, u8 Data); u8 XCoresightPs_DccRecvByte(u32 BaseAddress); +#endif /** @} */ diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/cpu_cortexr5_v1_1/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/cpu_cortexr5_v1_4/src/Makefile similarity index 78% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/cpu_cortexr5_v1_1/src/Makefile rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/cpu_cortexr5_v1_4/src/Makefile index 648f83a29..747826397 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/cpu_cortexr5_v1_1/src/Makefile +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/cpu_cortexr5_v1_4/src/Makefile @@ -10,7 +10,7 @@ INCLUDEDIR=../../../include INCLUDES=-I${INCLUDEDIR} OUTS = *.o - +OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c))) LIBSOURCES=*.c INCLUDEFILES=*.h @@ -20,3 +20,6 @@ libs: .PHONY: include include: ${CP} $(INCLUDEFILES) $(INCLUDEDIR) + +clean: + rm -rf ${OBJECTS} diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/cpu_cortexr5_v1_1/src/xcpu_cortexr5.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/cpu_cortexr5_v1_4/src/xcpu_cortexr5.h similarity index 86% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/cpu_cortexr5_v1_1/src/xcpu_cortexr5.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/cpu_cortexr5_v1_4/src/xcpu_cortexr5.h index 7b21dcd21..108dc7ed7 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/cpu_cortexr5_v1_1/src/xcpu_cortexr5.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/cpu_cortexr5_v1_4/src/xcpu_cortexr5.h @@ -33,11 +33,16 @@ /** * * @file xcpu_cortexr5.h -* @addtogroup cpu_cortexr5_v1_1 +* @addtogroup cpu_cortexr5_v1_4 * @{ * @details * * dummy file +* MODIFICATION HISTORY: * +* Ver Who Date Changes +* ----- ---- -------- --------------------------------------------------------- +* 1.4 ms 04/18/17 Modified tcl file to add suffix U for XPAR_CPU_ID +* parameter of cpu_cortexr5 in xparameters.h ******************************************************************************/ /** @} */ diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_2/src/Makefile similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/Makefile rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_2/src/Makefile diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_1/src/xcsudma.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_2/src/xcsudma.c similarity index 90% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_1/src/xcsudma.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_2/src/xcsudma.c index 4ed4dd60b..9aa4beedb 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_1/src/xcsudma.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_2/src/xcsudma.c @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2014-2018 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -34,7 +34,7 @@ /** * * @file xcsudma.c -* @addtogroup csudma_v1_0 +* @addtogroup csudma_v1_2 * @{ * * This file contains the implementation of the interface functions for CSU_DMA @@ -188,6 +188,80 @@ void XCsuDma_Transfer(XCsuDma *InstancePtr, XCsuDma_Channel Channel, } } +/*****************************************************************************/ +/** +* +* This function sets the starting address and amount(size) of the data to be +* transfered from/to the memory through the AXI interface. +* This function is useful for pmu processor when it wishes to do +* a 64-bit DMA transfer. +* +* @param InstancePtr is a pointer to XCsuDma instance to be worked on. +* @param Channel represents the type of channel either it is Source or +* Destination. +* Source channel - XCSUDMA_SRC_CHANNEL +* Destination Channel - XCSUDMA_DST_CHANNEL +* @param AddrLow is a 32 bit variable which holds the starting lower address of +* data which needs to write into the memory(DST) (or read from +* the memory(SRC)). +* @param AddrHigh is a 32 bit variable which holds the higher address of data +* which needs to write into the memory(DST) (or read from +* the memroy(SRC)). +* @param Size is a 32 bit variable which represents the number of 4 byte +* words needs to be transfered from starting address. +* @param EnDataLast is to trigger an end of message. It will enable or +* disable data_inp_last signal to stream interface when current +* command is completed. It is applicable only to source channel +* and neglected for destination channel. +* - 1 - Asserts data_inp_last signal. +* - 0 - data_inp_last will not be asserted. +* +* @return None. +* +* @note Data_inp_last signal is asserted simultaneously with the +* data_inp_valid signal associated with the final 32-bit word +* transfer +* This API won't do flush/invalidation for the DMA buffer. +* It is recommened to call this API only through PMU processor. +* +******************************************************************************/ +void XCsuDma_64BitTransfer(XCsuDma *InstancePtr, XCsuDma_Channel Channel, + u32 AddrLow, u32 AddrHigh, u32 Size, u8 EnDataLast) +{ + /* Verify arguments */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid((Channel == (XCSUDMA_SRC_CHANNEL)) || + (Channel == (XCSUDMA_DST_CHANNEL))); + Xil_AssertVoid(Size <= (u32)(XCSUDMA_SIZE_MAX)); + Xil_AssertVoid(InstancePtr->IsReady == (u32)(XIL_COMPONENT_IS_READY)); + + + XCsuDma_WriteReg(InstancePtr->Config.BaseAddress, + ((u32)(XCSUDMA_ADDR_OFFSET) + + ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))), + (AddrLow & XCSUDMA_ADDR_MASK)); + + XCsuDma_WriteReg(InstancePtr->Config.BaseAddress, + ((u32)(XCSUDMA_ADDR_MSB_OFFSET) + + ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))), + (AddrHigh & XCSUDMA_MSB_ADDR_MASK)); + + if (EnDataLast == (u8)(XCSUDMA_LAST_WORD_MASK)) { + XCsuDma_WriteReg(InstancePtr->Config.BaseAddress, + ((u32)(XCSUDMA_SIZE_OFFSET) + + ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))), + ((Size << (u32)(XCSUDMA_SIZE_SHIFT)) | + (u32)(XCSUDMA_LAST_WORD_MASK))); + } + else { + XCsuDma_WriteReg(InstancePtr->Config.BaseAddress, + ((u32)(XCSUDMA_SIZE_OFFSET) + + ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))), + (Size << (u32)(XCSUDMA_SIZE_SHIFT))); + } +} + +/*****************************************************************************/ /*****************************************************************************/ /** * diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/xcsudma.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_2/src/xcsudma.h similarity index 95% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/xcsudma.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_2/src/xcsudma.h index 03a32c1ce..fc675a13c 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/xcsudma.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_2/src/xcsudma.h @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2014-2018 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -82,7 +82,7 @@ * to build and link only those parts of the driver that are necessary. * * @file xcsudma.h -* @addtogroup csudma_v1_0 +* @addtogroup csudma_v1_2 * @{ * @details * @@ -99,6 +99,13 @@ * 1.0 vnsld 22/10/14 First release * 1.1 adk 10/05/16 Fixed CR#951040 race condition in the recv path when * source and destination points to the same buffer. +* ms 03/17/17 Added readme.txt file in examples folder for doxygen +* generation. +* ms 04/10/17 Modified filename tag in xcsudma_selftest_example.c to +* include the file in doxygen examples. +* 1.2 adk 11/22/17 Added peripheral test app support for CSUDMA driver. +* adk 09/03/18 Added new API XCsuDma_64BitTransfer() useful for 64-bit +* dma transfers through PMU processor(CR#996201). * * ******************************************************************************/ @@ -373,6 +380,8 @@ s32 XCsuDma_CfgInitialize(XCsuDma *InstancePtr, XCsuDma_Config *CfgPtr, u32 EffectiveAddr); void XCsuDma_Transfer(XCsuDma *InstancePtr, XCsuDma_Channel Channel, UINTPTR Addr, u32 Size, u8 EnDataLast); +void XCsuDma_64BitTransfer(XCsuDma *InstancePtr, XCsuDma_Channel Channel, + u32 AddrLow, u32 AddrHigh, u32 Size, u8 EnDataLast); void XCsuDma_LoopBackTransfer(XCsuDma *InstancePtr, u64 SrcAddr, u64 DstAddr, u32 Size); u64 XCsuDma_GetAddr(XCsuDma *InstancePtr, XCsuDma_Channel Channel); diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_1/src/xcsudma_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_2/src/xcsudma_g.c similarity index 90% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_1/src/xcsudma_g.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_2/src/xcsudma_g.c index 09e7f739a..1c2317e8e 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_1/src/xcsudma_g.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_2/src/xcsudma_g.c @@ -5,7 +5,7 @@ * Version: * DO NOT EDIT. * -* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.* +* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.* *Permission is hereby granted, free of charge, to any person obtaining a copy *of this software and associated documentation files (the Software), to deal *in the Software without restriction, including without limitation the rights @@ -44,7 +44,7 @@ * The configuration table for devices */ -XCsuDma_Config XCsuDma_ConfigTable[] = +XCsuDma_Config XCsuDma_ConfigTable[XPAR_XCSUDMA_NUM_INSTANCES] = { { XPAR_PSU_CSUDMA_DEVICE_ID, diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_1/src/xcsudma_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_2/src/xcsudma_hw.h similarity index 99% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_1/src/xcsudma_hw.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_2/src/xcsudma_hw.h index 6b2c2cdb8..031c13458 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_1/src/xcsudma_hw.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_2/src/xcsudma_hw.h @@ -33,7 +33,7 @@ /** * * @file xcsudma_hw.h -* @addtogroup csudma_v1_0 +* @addtogroup csudma_v1_2 * @{ * * This header file contains identifiers and register-level driver functions (or diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_1/src/xcsudma_intr.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_2/src/xcsudma_intr.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_1/src/xcsudma_intr.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_2/src/xcsudma_intr.c index 9f37e4582..b45d6cf29 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_1/src/xcsudma_intr.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_2/src/xcsudma_intr.c @@ -34,7 +34,7 @@ /** * * @file xcsudma_intr.c -* @addtogroup csudma_v1_0 +* @addtogroup csudma_v1_2 * @{ * * This file contains interrupt related functions of Xilinx CSU_DMA core. diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_1/src/xcsudma_selftest.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_2/src/xcsudma_selftest.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_1/src/xcsudma_selftest.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_2/src/xcsudma_selftest.c index f61910fd4..00f35e145 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/csudma_v1_1/src/xcsudma_selftest.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_2/src/xcsudma_selftest.c @@ -34,7 +34,7 @@ /** * * @file xcsudma_selftest.c -* @addtogroup csudma_v1_0 +* @addtogroup csudma_v1_2 * @{ * * This file contains a diagnostic self-test function for the CSU_DMA driver. diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/xcsudma_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_2/src/xcsudma_sinit.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/xcsudma_sinit.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_2/src/xcsudma_sinit.c index 10e5c14f6..be962e298 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_1/src/xcsudma_sinit.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_2/src/xcsudma_sinit.c @@ -34,7 +34,7 @@ /** * * @file xcsudma_sinit.c -* @addtogroup csudma_v1_0 +* @addtogroup csudma_v1_2 * @{ * * This file contains static initialization methods for Xilinx CSU_DMA core. diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ddrcpsu_v1_1/src/xddrcpsu.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ddrcpsu_v1_1/src/xddrcpsu.h index 2640a9462..412f335e4 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ddrcpsu_v1_1/src/xddrcpsu.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ddrcpsu_v1_1/src/xddrcpsu.h @@ -18,15 +18,14 @@ * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * * Except as contained in this notice, the name of the Xilinx shall not be used * in advertising or otherwise to promote the sale, use or other dealings in - * in advertising or otherwise to promote the sale, use or other dealings in * this Software without prior written authorization from Xilinx. * *******************************************************************************/ @@ -34,7 +33,7 @@ /** * * @file xddcrpsu.h - * @addtogroup ddrcpsu_v1_0 + * @addtogroup ddrcpsu_v1_1 * @{ * @details * diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/dpdma_v1_0/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/dpdma_v1_0/src/Makefile new file mode 100644 index 000000000..f5944f9d2 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/dpdma_v1_0/src/Makefile @@ -0,0 +1,40 @@ +COMPILER= +ARCHIVER= +CP=cp +COMPILER_FLAGS= +EXTRA_COMPILER_FLAGS= +LIB=libxil.a + +CC_FLAGS = $(COMPILER_FLAGS) +ECC_FLAGS = $(EXTRA_COMPILER_FLAGS) + +RELEASEDIR=../../../lib +INCLUDEDIR=../../../include +INCLUDES=-I./. -I${INCLUDEDIR} + +OUTS = *.o + +LIBSOURCES:=*.c +INCLUDEFILES:=*.h + +OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c))) + +libs: banner dpdma_libs clean + +%.o: %.c + ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $< + +banner: + echo "Compiling dpdma" + +dpdma_libs: ${OBJECTS} + $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS} + +.PHONY: include +include: dpdma_includes + +dpdma_includes: + ${CP} ${INCLUDEFILES} ${INCLUDEDIR} + +clean: + rm -rf ${OBJECTS} diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/dpdma_v1_0/src/xdpdma.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/dpdma_v1_0/src/xdpdma.c new file mode 100644 index 000000000..92eaad2cd --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/dpdma_v1_0/src/xdpdma.c @@ -0,0 +1,966 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* + +*******************************************************************************/ +/*****************************************************************************/ +/** + * + * @file xdpdma.c + * + * This file contains the implementation of the interface functions of the + * XDpDma driver. Refer to xdpdma.h for detailed information. + * + * @note None. + * + * 
+ * MODIFICATION HISTORY:
+ *
+ * Ver	Who   Date     Changes
+ * ---- ----- -------- ----------------------------------------------------
+ * 1.0  aad   04/12/16 Initial release.
+ *
+ *****************************************************************************/
+
+/***************************** Include Files **********************************/
+#include "xdpdma.h"
+#include "xavbuf.h"
+
+/************************** Constant Definitions ******************************/
+#define XDPDMA_CH_OFFSET		0x100
+#define XDPDMA_WAIT_TIMEOUT		10000
+
+#define XDPDMA_AUDIO_ALIGNMENT		128
+
+#define XDPDMA_VIDEO_CHANNEL0		0
+#define XDPDMA_VIDEO_CHANNEL1		1
+#define XDPDMA_VIDEO_CHANNEL2		2
+#define XDPDMA_GRAPHICS_CHANNEL		3
+#define XDPDMA_AUDIO_CHANNEL0		4
+#define XDPDMA_AUDIO_CHANNEL1		5
+
+#define XDPDMA_DESC_PREAMBLE		0xA5
+#define XDPDMA_DESC_IGNR_DONE		0x400
+#define XDPDMA_DESC_UPDATE		0x200
+#define XDPDMA_DESC_COMP_INTR		0x100
+#define XDPDMA_DESC_LAST_FRAME		0x200000
+#define XDPDMA_DESC_DONE_SHIFT		31
+#define XDPDMA_QOS_MIN			4
+#define XDPDMA_QOS_MAX			11
+
+/*************************************************************************/
+/**
+ *
+ * This function returns the number of outstanding transactions on a given
+ * channel.
+ *
+ * @param    InstancePtr is a pointer to the driver instance.
+ * @param    ChannelNum is the channel number on which the operation is
+ *	     being carried out.
+ *
+ * @return   Number of pending transactions.
+ *
+ * @note     None.
+ *
+ * **************************************************************************/
+static int XDpDma_GetPendingTransaction(XDpDma *InstancePtr, u32 ChannelNum)
+{
+	u32 RegVal;
+	RegVal = XDpDma_ReadReg(InstancePtr->Config.BaseAddr,
+				XDPDMA_CH0_STATUS + 0x100 * ChannelNum);
+	return (RegVal & XDPDMA_CH_STATUS_OTRAN_CNT_MASK);
+}
+
+/*************************************************************************/
+/**
+ *
+ * This function waits until the outstanding transactions are completed.
+ *
+ * @param    InstancePtr is a pointer to the driver instance.
+ * @param    ChannelNum is the channel number on which the operation is
+ *	     being carried out.
+ *
+ * @return   XST_SUCCESS when all the pending transactions are complete
+ *	     before timeout.
+ *	     XST_FAILURE if timeout occurs before pending transactions are
+ *	     completed.
+ *
+ * @note     None.
+ *
+ * **************************************************************************/
+static int XDpDma_WaitPendingTransaction(XDpDma *InstancePtr, u8 ChannelNum)
+{
+	/* Verify arguments. */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(ChannelNum <= XDPDMA_AUDIO_CHANNEL1);
+
+	u32 Timeout = 0;
+	u32 Count;
+	do {
+		Count = XDpDma_GetPendingTransaction(InstancePtr, ChannelNum);
+		Timeout++;
+	} while((Timeout != XDPDMA_WAIT_TIMEOUT) && Count);
+
+	if(Timeout ==  XDPDMA_WAIT_TIMEOUT) {
+		return XST_FAILURE;
+	}
+
+	return XST_SUCCESS;
+}
+
+/*************************************************************************/
+/**
+ *
+ * This function controls the hardware channels of the DPDMA.
+ *
+ *
+ * @param    InstancePtr is a pointer to the driver instance.
+ * @param    ChannelNum is the physical channel number of the DPDMA.
+ * @param    ChannelState is an enum of type XDpDma_ChannelState.
+ *
+ * @return   XST_SUCCESS when the mentioned channel is enabled successfully.
+ *	     XST_FAILURE when the mentioned channel fails to be enabled.
+ *
+ * @note     None.
+ *
+ * **************************************************************************/
+static int XDpDma_ConfigChannelState(XDpDma *InstancePtr, u8 ChannelNum,
+				     XDpDma_ChannelState Enable)
+{
+	u32 Mask = 0;
+	u32 RegVal = 0;
+	u32 Status = 0;
+	/* Verify arguments. */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(ChannelNum <= XDPDMA_AUDIO_CHANNEL1);
+
+	Mask = XDPDMA_CH_CNTL_EN_MASK | XDPDMA_CH_CNTL_PAUSE_MASK;
+	switch(Enable) {
+		case XDPDMA_ENABLE:
+			RegVal = XDPDMA_CH_CNTL_EN_MASK;
+			break;
+		case XDPDMA_DISABLE:
+			XDpDma_ConfigChannelState(InstancePtr, ChannelNum,
+						  XDPDMA_PAUSE);
+			Status = XDpDma_WaitPendingTransaction(InstancePtr,
+							       ChannelNum);
+			if(Status == XST_FAILURE) {
+				return XST_FAILURE;
+			}
+
+			RegVal = XDPDMA_DISABLE;
+			Mask = XDPDMA_CH_CNTL_EN_MASK;
+			break;
+		case XDPDMA_IDLE:
+			Status = XDpDma_ConfigChannelState(InstancePtr,
+							   ChannelNum,
+							   XDPDMA_DISABLE);
+			if(Status == XST_FAILURE) {
+				return XST_FAILURE;
+			}
+
+			RegVal = 0;
+			break;
+		case XDPDMA_PAUSE:
+			RegVal = XDPDMA_PAUSE;
+			break;
+	}
+	XDpDma_ReadModifyWrite(InstancePtr->Config.BaseAddr,
+			       XDPDMA_CH0_CNTL + XDPDMA_CH_OFFSET * ChannelNum,
+			       RegVal, Mask);
+	return XST_SUCCESS;
+}
+
+/*************************************************************************/
+/**
+ *
+ * This function updates the descriptor that is not currently active on a
+ * Video/Graphics channel.
+ *
+ * @param    InstancePtr is a pointer to the driver instance.
+ * @param    Channel is a pointer to the channel on which the operation is
+ *	     to be carried out.
+ *
+ * @return   Descriptor for next operation.
+ *
+ * @note     None.
+ *
+ * **************************************************************************/
+static XDpDma_Descriptor *XDpDma_UpdateVideoDescriptor(XDpDma_Channel *Channel)
+{
+	if(Channel->Current == NULL) {
+		Channel->Current = &Channel->Descriptor0;
+	}
+	else if(Channel->Current == &Channel->Descriptor0) {
+		Channel->Current = &Channel->Descriptor1;
+	}
+	else if(Channel->Current == &Channel->Descriptor1) {
+		Channel->Current = &Channel->Descriptor0;
+	}
+	return Channel->Current;
+}
+
+/*************************************************************************/
+/**
+ * This function programs the address of the descriptor about to be active
+ *
+ * @param    InstancePtr is a pointer to the DPDMA instance.
+ * @param    Channel is an enum of the channel for which the descriptor
+ *	     address is to be set.
+ *
+ * @return   Descriptor for next operation.
+ *
+ * @note     None.
+ *
+ * **************************************************************************/
+static void XDpDma_SetDescriptorAddress(XDpDma *InstancePtr, u8 ChannelNum)
+{
+	u32 AddrOffset;
+	u32 AddrEOffset;
+	Xil_AssertVoid(ChannelNum <= XDPDMA_AUDIO_CHANNEL1);
+	AddrOffset = XDPDMA_CH0_DSCR_STRT_ADDR +
+					(XDPDMA_CH_OFFSET * ChannelNum);
+	AddrEOffset = XDPDMA_CH0_DSCR_STRT_ADDRE +
+					(XDPDMA_CH_OFFSET * ChannelNum);
+
+	XDpDma_Descriptor *Descriptor = NULL;
+	switch(ChannelNum) {
+	case XDPDMA_VIDEO_CHANNEL0:
+		Descriptor = InstancePtr->Video.Channel[ChannelNum].Current;
+		break;
+	case XDPDMA_VIDEO_CHANNEL1:
+		Descriptor = InstancePtr->Video.Channel[ChannelNum].Current;
+		break;
+	case XDPDMA_VIDEO_CHANNEL2:
+		Descriptor = InstancePtr->Video.Channel[ChannelNum].Current;
+		break;
+	case XDPDMA_GRAPHICS_CHANNEL:
+		Descriptor = InstancePtr->Gfx.Channel.Current;
+		break;
+	case XDPDMA_AUDIO_CHANNEL0:
+		Descriptor = InstancePtr->Audio[0].Current;
+		break;
+	case XDPDMA_AUDIO_CHANNEL1:
+		Descriptor = InstancePtr->Audio[1].Current;
+		break;
+	}
+
+	XDpDma_WriteReg(InstancePtr->Config.BaseAddr, AddrEOffset,
+			(INTPTR) Descriptor >> 32);
+	XDpDma_WriteReg(InstancePtr->Config.BaseAddr, AddrOffset,
+			(INTPTR) Descriptor);
+}
+
+/*************************************************************************/
+/**
+ *
+ * This functions sets the Audio Descriptor for Data Transfer.
+ *
+ * @param    CurrDesc is a pointer to the descriptor to be initialized
+ * @param    DataSize is the payload size of the buffer to be transferred
+ * @param    BuffAddr is the payload address
+ *
+ * @return   None.
+ *
+ * @note     None.
+ *
+ * **************************************************************************/
+static void XDpDma_SetupAudioDescriptor(XDpDma_Descriptor *CurrDesc,
+					u64 DataSize, u64 BuffAddr,
+					XDpDma_Descriptor *NextDesc)
+{
+	Xil_AssertVoid(CurrDesc != NULL);
+	Xil_AssertVoid(DataSize != 0);
+	Xil_AssertVoid(BuffAddr != 0);
+
+	if(NextDesc == NULL) {
+		CurrDesc->Control = XDPDMA_DESC_PREAMBLE |
+			XDPDMA_DESC_UPDATE | XDPDMA_DESC_IGNR_DONE |
+			XDPDMA_DESC_COMP_INTR;
+
+	}
+	else {
+		CurrDesc->Control = XDPDMA_DESC_PREAMBLE |
+			XDPDMA_DESC_UPDATE | XDPDMA_DESC_IGNR_DONE;
+	}
+	CurrDesc->DSCR_ID = 0;
+	CurrDesc->XFER_SIZE = DataSize;
+	CurrDesc->LINE_SIZE_STRIDE = 0;
+	CurrDesc->LSB_Timestamp = 0;
+	CurrDesc->MSB_Timestamp = 0;
+	CurrDesc->ADDR_EXT = ((BuffAddr >> XDPDMA_DESCRIPTOR_SRC_ADDR_WIDTH) <<
+			      XDPDMA_DESCRIPTOR_ADDR_EXT_SRC_ADDR_EXT_SHIFT) |
+			     ((INTPTR) NextDesc >>
+			      XDPDMA_DESCRIPTOR_NEXT_DESR_WIDTH);
+	CurrDesc->NEXT_DESR = (INTPTR) NextDesc;
+	CurrDesc->SRC_ADDR =  BuffAddr;
+}
+
+/*************************************************************************/
+/**
+ *
+ * This functions retrieves the configuration for this DPDMA driver and
+ * fills in the InstancePtr->Config structure.
+ *
+ * @param    InstancePtr is a pointer to the driver instance.
+ * @param    ConfigPtr is a pointer to the configuration structure that will
+ *           be used to copy the settings from.
+ *
+ * @return   None.
+ *
+ * @note     None.
+ *
+ * **************************************************************************/
+void XDpDma_CfgInitialize(XDpDma *InstancePtr, XDpDma_Config *CfgPtr)
+{
+	InstancePtr->Config.DeviceId = CfgPtr->DeviceId;
+	InstancePtr->Config.BaseAddr = CfgPtr->BaseAddr;
+
+	InstancePtr->Video.Channel[XDPDMA_VIDEO_CHANNEL0].Current = NULL;
+	InstancePtr->Video.Channel[XDPDMA_VIDEO_CHANNEL1].Current = NULL;
+	InstancePtr->Video.Channel[XDPDMA_VIDEO_CHANNEL2].Current = NULL;
+	InstancePtr->Video.TriggerStatus = XDPDMA_TRIGGER_DONE;
+	InstancePtr->Video.VideoInfo = NULL;
+	InstancePtr->Video.FrameBuffer[XDPDMA_VIDEO_CHANNEL0] = NULL;
+	InstancePtr->Video.FrameBuffer[XDPDMA_VIDEO_CHANNEL1] = NULL;
+	InstancePtr->Video.FrameBuffer[XDPDMA_VIDEO_CHANNEL2] = NULL;
+
+	InstancePtr->Gfx.Channel.Current = NULL;
+	InstancePtr->Gfx.TriggerStatus = XDPDMA_TRIGGER_DONE;
+	InstancePtr->Gfx.VideoInfo = NULL;
+	InstancePtr->Gfx.FrameBuffer = NULL;
+}
+
+/*************************************************************************/
+/**
+ *
+ * This functions controls the states in which a channel should go into.
+ *
+ * @param    InstancePtr is a pointer to the driver instance.
+ * @param    ChannelType is an enum of XDpDma_ChannelType.
+ * @param    ChannelState is an enum of type XDpDma_ChannelState.
+ *
+ * @return   XST_SUCCESS when the mentioned channel is enabled successfully.
+ *	     XST_FAILURE when the mentioned channel fails to be enabled.
+ *
+ * @note     None.
+ *
+ * **************************************************************************/
+int XDpDma_SetChannelState(XDpDma *InstancePtr, XDpDma_ChannelType Channel,
+					XDpDma_ChannelState ChannelState)
+{
+	u32 Index = 0;
+	u32 NumPlanes = 0;
+	u32 Status = 0;
+	/* Verify arguments. */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	switch(Channel) {
+	case VideoChan:
+		if(InstancePtr->Video.VideoInfo == NULL) {
+			return XST_FAILURE;
+		}
+		else {
+			NumPlanes = InstancePtr->Video.VideoInfo->Mode;
+			for(Index = 0; Index <= NumPlanes; Index++) {
+				Status = XDpDma_ConfigChannelState(InstancePtr,
+								Index,
+								ChannelState);
+				if(Status == XST_FAILURE) {
+					return XST_FAILURE;
+				}
+			}
+		}
+		break;
+	case GraphicsChan:
+		if(InstancePtr->Gfx.VideoInfo == NULL) {
+			return XST_FAILURE;
+		}
+		else {
+			return	XDpDma_ConfigChannelState(InstancePtr,
+					      XDPDMA_GRAPHICS_CHANNEL,
+					      ChannelState);
+		}
+		break;
+	case AudioChan0:
+		return	XDpDma_ConfigChannelState(InstancePtr,
+						  XDPDMA_AUDIO_CHANNEL0,
+						  ChannelState);
+		break;
+	case AudioChan1:
+		return XDpDma_ConfigChannelState(InstancePtr,
+						 XDPDMA_AUDIO_CHANNEL1,
+						 ChannelState);
+		break;
+	default:
+		return XST_FAILURE;
+		break;
+	}
+
+	return XST_SUCCESS;
+}
+
+/*************************************************************************/
+/**
+ *
+ * This function allocates DPDMA Video Channels depending on the number of
+ * planes in the video
+ *
+ * @param	InstancePtr is a pointer to the driver instance.
+ * @params	Format is the video format to be used for the DPDMA transfer
+ *
+ * @return	XST_SUCCESS, When the format is valid Video Format.
+ *		XST_FAILURE, When the format is not valid Video Format
+ *
+ * @note	None.
+ *
+ * **************************************************************************/
+int XDpDma_SetVideoFormat(XDpDma *InstancePtr, XAVBuf_VideoFormat Format)
+{
+	/* Verify arguments. */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	InstancePtr->Video.VideoInfo = XAVBuf_GetNLiveVideoAttribute(Format);
+	if(InstancePtr->Video.VideoInfo == NULL) {
+		return XST_FAILURE;
+	}
+
+	return XST_SUCCESS;
+}
+
+/*************************************************************************/
+/**
+ *
+ * This function allocates DPDMA Graphics Channels.
+ *
+ * @param	InstancePtr is a pointer to the driver instance.
+ * @params	Format is the video format to be used for the DPDMA transfer
+ *
+ * @return	XST_SUCCESS, When the format is a valid Graphics Format.
+ *		XST_FAILURE, When the format is not valid Graphics Format.
+ *
+ * @note	None.
+ *
+ * **************************************************************************/
+int XDpDma_SetGraphicsFormat(XDpDma *InstancePtr, XAVBuf_VideoFormat Format)
+{
+
+	/* Verify arguments. */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	InstancePtr->Gfx.VideoInfo = XAVBuf_GetNLGraphicsAttribute(Format);
+	if(InstancePtr->Gfx.VideoInfo == NULL) {
+		return XST_FAILURE;
+	}
+
+	return XST_SUCCESS;
+}
+
+/*************************************************************************/
+/**
+ *
+ * This function starts the operation on the a given channel
+ *
+ * @param    InstancePtr is a pointer to the driver instance.
+ * @param    QOS is the Quality of Service value to be selected.
+ *
+ * @return   None.
+ *
+ * @note     .
+ *
+ * **************************************************************************/
+void XDpDma_SetQOS(XDpDma *InstancePtr, u8 QOS)
+{
+	u8 Index;
+	u32 RegVal = 0;
+
+	Xil_AssertVoid(QOS >= XDPDMA_QOS_MIN && QOS <= XDPDMA_QOS_MAX);
+
+	RegVal = ((QOS << XDPDMA_CH_CNTL_QOS_DATA_RD_SHIFT) |
+		   (QOS << XDPDMA_CH_CNTL_QOS_DSCR_RD_SHIFT) |
+		   (QOS << XDPDMA_CH_CNTL_QOS_DSCR_WR_SHIFT));
+
+	u32 Mask = XDPDMA_CH_CNTL_QOS_DATA_RD_MASK |
+		XDPDMA_CH_CNTL_QOS_DSCR_RD_MASK |
+		XDPDMA_CH_CNTL_QOS_DSCR_WR_MASK;
+
+	for(Index = 0; Index <= XDPDMA_AUDIO_CHANNEL1; Index++) {
+		XDpDma_ReadModifyWrite(InstancePtr->Config.BaseAddr,
+				XDPDMA_CH0_CNTL + (XDPDMA_CH_OFFSET * Index),
+			        RegVal, Mask);
+	}
+
+}
+
+/*************************************************************************/
+/**
+ *
+ * This function Triggers DPDMA to start the transaction.
+ *
+ * @param	InstancePtr is a pointer to the XDpDma instance.
+ * @param	Channel is the XDpDma_ChannelType on which the transaction
+ *		is to be triggered.
+ *
+ * @return	XST_SUCCESS The channel has successfully been Triggered.
+ *		XST_FAILURE When the triggering Video and Graphics channel
+ *		without setting the Video Formats.
+ *
+ * @note	None.
+ *
+ * **************************************************************************/
+int XDpDma_Trigger(XDpDma *InstancePtr, XDpDma_ChannelType Channel)
+{
+	u32 Trigger = 0;
+	u8 Index = 0;
+	u8 NumPlanes = 0;
+	switch(Channel) {
+	case VideoChan:
+		if(InstancePtr->Video.VideoInfo == NULL) {
+			return XST_FAILURE;
+		}
+		else {
+			NumPlanes = InstancePtr->Video.VideoInfo->Mode;
+			for(Index = 0; Index <= NumPlanes; Index++) {
+				Trigger |= XDPDMA_GBL_TRG_CH0_MASK << Index;
+				InstancePtr->Video.TriggerStatus =
+					XDPDMA_TRIGGER_DONE;
+			}
+		}
+		break;
+	case GraphicsChan:
+		if(InstancePtr->Gfx.VideoInfo == NULL) {
+			return XST_FAILURE;
+		}
+		Trigger = XDPDMA_GBL_TRG_CH3_MASK;
+		InstancePtr->Gfx.TriggerStatus = XDPDMA_TRIGGER_DONE;
+		break;
+	case AudioChan0:
+		Trigger = XDPDMA_GBL_TRG_CH4_MASK;
+		InstancePtr->Audio[0].TriggerStatus = XDPDMA_TRIGGER_DONE;
+		break;
+	case AudioChan1:
+		Trigger = XDPDMA_GBL_TRG_CH5_MASK;
+		InstancePtr->Audio[1].TriggerStatus = XDPDMA_TRIGGER_DONE;
+		break;
+	}
+	XDpDma_WriteReg(InstancePtr->Config.BaseAddr, XDPDMA_GBL, Trigger);
+
+	return XST_SUCCESS;
+
+}
+
+/*************************************************************************/
+/**
+ *
+ * This function Retriggers DPDMA to fetch data from new descriptor.
+ *
+ * @param	InstancePtr is a pointer to the XDpDma instance.
+ * @param	Channel is the XDpDma_ChannelType on which the transaction
+ *		is to be retriggered.
+ *
+ * @return	XST_SUCCESS The channel has successfully been Triggered.
+ *		XST_FAILURE When the triggering Video and Graphics channel
+ *		without setting the Video Formats.
+ *
+ * @note	None.
+ *
+ * **************************************************************************/
+int XDpDma_ReTrigger(XDpDma *InstancePtr, XDpDma_ChannelType Channel)
+{
+	u32 Trigger = 0;
+	u8 NumPlanes;
+	u8 Index;
+	switch(Channel) {
+	case VideoChan:
+		if(InstancePtr->Video.VideoInfo == NULL) {
+			return XST_FAILURE;
+		}
+		else {
+			NumPlanes = InstancePtr->Video.VideoInfo->Mode;
+			for(Index = 0; Index <= NumPlanes; Index++) {
+				Trigger |= XDPDMA_GBL_RTRG_CH0_MASK << Index;
+				InstancePtr->Video.TriggerStatus =
+					XDPDMA_RETRIGGER_DONE;
+			}
+		}
+		break;
+	case GraphicsChan:
+		if(InstancePtr->Gfx.VideoInfo == NULL) {
+			return XST_FAILURE;
+		}
+		Trigger = XDPDMA_GBL_RTRG_CH3_MASK;
+		InstancePtr->Gfx.TriggerStatus = XDPDMA_RETRIGGER_DONE;
+		break;
+	case AudioChan0:
+		Trigger = XDPDMA_GBL_RTRG_CH4_MASK;
+		InstancePtr->Audio[0].TriggerStatus = XDPDMA_RETRIGGER_DONE;
+		break;
+	case AudioChan1:
+		Trigger = XDPDMA_GBL_RTRG_CH5_MASK;
+		InstancePtr->Audio[1].TriggerStatus = XDPDMA_RETRIGGER_DONE;
+		break;
+	}
+	XDpDma_WriteReg(InstancePtr->Config.BaseAddr, XDPDMA_GBL, Trigger);
+
+	return XST_SUCCESS;
+}
+
+/*************************************************************************/
+/**
+ *
+ * This function intializes Video Descriptor for Video and Graphics channel
+ *
+ * @param    Channel is a pointer to the current Descriptor of Video or
+ *	     Graphics Channel.
+ * @param    FrameBuffer is a pointer to the Frame Buffer structure
+ *
+ * @return   None.
+ *
+ * @note     None.
+ *
+ * **************************************************************************/
+void XDpDma_InitVideoDescriptor(XDpDma_Descriptor *CurrDesc,
+				XDpDma_FrameBuffer *FrameBuffer)
+{
+	Xil_AssertVoid(CurrDesc != NULL);
+	Xil_AssertVoid(FrameBuffer != NULL);
+	Xil_AssertVoid((FrameBuffer->Stride) % XDPDMA_DESCRIPTOR_ALIGN == 0);
+	CurrDesc->Control = XDPDMA_DESC_PREAMBLE | XDPDMA_DESC_IGNR_DONE |
+			    XDPDMA_DESC_LAST_FRAME;
+	CurrDesc->DSCR_ID = 0;
+	CurrDesc->XFER_SIZE = FrameBuffer->Size;
+	CurrDesc->LINE_SIZE_STRIDE = ((FrameBuffer->Stride >> 4) <<
+				XDPDMA_DESCRIPTOR_LINE_SIZE_STRIDE_SHIFT) |
+				(FrameBuffer->LineSize);
+	CurrDesc->ADDR_EXT = (((FrameBuffer->Address >>
+				XDPDMA_DESCRIPTOR_SRC_ADDR_WIDTH) <<
+			       XDPDMA_DESCRIPTOR_ADDR_EXT_SRC_ADDR_EXT_SHIFT) |
+				((INTPTR) CurrDesc >>
+				 XDPDMA_DESCRIPTOR_NEXT_DESR_WIDTH));
+	CurrDesc->NEXT_DESR = (INTPTR) CurrDesc;
+	CurrDesc->SRC_ADDR = FrameBuffer->Address;
+}
+
+/*************************************************************************/
+/**
+ *
+ * This function intializes Descriptors for transactions on Audio Channel
+ *
+ * @param    Channel is a pointer to the XDpDma_AudioChannel instance
+ *
+ * @param    AudioBuffer is a pointer to the Audio Buffer structure
+ *
+ * @return   None.
+ *
+ * @note     None.
+ *
+ * **************************************************************************/
+void XDpDma_InitAudioDescriptor(XDpDma_AudioChannel *Channel,
+			       XDpDma_AudioBuffer *AudioBuffer)
+{
+	u32 Size;
+	u64 Address;
+	Xil_AssertVoid(Channel != NULL);
+	Xil_AssertVoid(AudioBuffer != NULL);
+	Xil_AssertVoid((AudioBuffer->Size) % XDPDMA_AUDIO_ALIGNMENT == 0);
+	Xil_AssertVoid((AudioBuffer->Address) % XDPDMA_AUDIO_ALIGNMENT == 0);
+
+	Size = AudioBuffer->Size / 4;
+	Address = AudioBuffer->Address;
+	if(Channel->Current == &Channel->Descriptor4) {
+		XDpDma_SetupAudioDescriptor(&Channel->Descriptor4, Size,
+					    Address,
+					    &Channel->Descriptor5);
+		XDpDma_SetupAudioDescriptor(&Channel->Descriptor5, Size,
+					    Address + Size,
+					    &Channel->Descriptor6);
+		XDpDma_SetupAudioDescriptor(&Channel->Descriptor6, Size,
+					    Address + (Size * 2),
+					    &Channel->Descriptor7);
+		XDpDma_SetupAudioDescriptor(&Channel->Descriptor7, Size,
+					    Address + (Size * 3), NULL);
+	}
+
+	else if(Channel->Current == &Channel->Descriptor0) {
+		XDpDma_SetupAudioDescriptor(&Channel->Descriptor0, Size,
+					    Address,
+					    &Channel->Descriptor1);
+		XDpDma_SetupAudioDescriptor(&Channel->Descriptor1, Size,
+					    Address + Size,
+					    &Channel->Descriptor2);
+		XDpDma_SetupAudioDescriptor(&Channel->Descriptor2, Size,
+					    Address + (Size * 2),
+					    &Channel->Descriptor3);
+		XDpDma_SetupAudioDescriptor(&Channel->Descriptor3, Size,
+					    Address + (Size * 3), NULL);
+
+	}
+}
+
+/*************************************************************************/
+/**
+ *
+ * This function sets the next Frame Buffers to be displayed on the Video
+ * Channel.
+ *
+ * @param    InstancePtr is pointer to the instance of DPDMA.
+ * @param    Plane0 is a pointer to the Frame Buffer structure.
+ * @param    Plane1 is a pointer to the Frame Buffer structure.
+ * @param    Plane2 is a pointer to the Frame Buffer structure.
+ *
+ * @return   None.
+ *
+ * @note     For interleaved mode use Plane0.
+ *	     For semi-planar mode use Plane0 and Plane1.
+ *	     For planar mode use Plane0, Plane1 and Plane2
+ *
+ * **************************************************************************/
+void  XDpDma_DisplayVideoFrameBuffer(XDpDma *InstancePtr,
+				     XDpDma_FrameBuffer *Plane0,
+				     XDpDma_FrameBuffer *Plane1,
+				     XDpDma_FrameBuffer *Plane2)
+{
+	u8 NumPlanes;
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->Video.VideoInfo != NULL);
+
+	NumPlanes = InstancePtr->Video.VideoInfo->Mode;
+
+	switch(NumPlanes) {
+		case XDPDMA_VIDEO_CHANNEL2:
+			Xil_AssertVoid(Plane2 != NULL);
+			InstancePtr->Video.FrameBuffer[XDPDMA_VIDEO_CHANNEL2] =
+				Plane2;
+		case XDPDMA_VIDEO_CHANNEL1:
+			Xil_AssertVoid(Plane1 != NULL);
+			InstancePtr->Video.FrameBuffer[XDPDMA_VIDEO_CHANNEL1] =
+				Plane1;
+		case XDPDMA_VIDEO_CHANNEL0:
+			Xil_AssertVoid(Plane0 != NULL);
+			InstancePtr->Video.FrameBuffer[XDPDMA_VIDEO_CHANNEL0] =
+				Plane0;
+			break;
+	}
+
+	if(InstancePtr->Video.Channel[XDPDMA_VIDEO_CHANNEL0].Current == NULL) {
+		InstancePtr->Video.TriggerStatus = XDPDMA_TRIGGER_EN;
+	}
+	else {
+		InstancePtr->Video.TriggerStatus = XDPDMA_RETRIGGER_EN;
+	}
+}
+
+/*************************************************************************/
+/**
+ *
+ * This function sets the next Frame Buffers to be displayed on the Graphics
+ * Channel.
+ *
+ * @param    InstancePtr is pointer to the instance of DPDMA.
+ * @param    Plane is a pointer to the Frame Buffer structure.
+ *
+ * @return   None.
+ *
+ * @note     None.
+ *
+ **************************************************************************/
+void XDpDma_DisplayGfxFrameBuffer(XDpDma *InstancePtr,
+				  XDpDma_FrameBuffer *Plane)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Plane != NULL);
+
+	InstancePtr->Gfx.FrameBuffer = Plane;
+
+	if(InstancePtr->Gfx.Channel.Current == NULL) {
+		InstancePtr->Gfx.TriggerStatus = XDPDMA_TRIGGER_EN;
+	}
+	else {
+		InstancePtr->Gfx.TriggerStatus = XDPDMA_RETRIGGER_EN;
+	}
+}
+/*************************************************************************/
+/**
+ *
+ * This function sets the next Audio Buffer to be played on Audio Channel 0
+ *
+ * @param    InstancePtr is pointer to the instance of DPDMA.
+ * @param    Buffer is a pointer to the attributes of the Audio information
+ *	     to be played.
+ * @param    ChannelNum selects between Audio Channel 0 and Audio Channel 1
+ *
+ * @return   XST_SUCCESS when the play audio request is successful.
+ *	     XST_FAILURE when the play audio request fails, user has to
+ *	     retry to play the audio.
+ *
+ * @note     The user has to schedule new audio buffer before half the audio
+ *	     information is consumed by DPDMA to have a seamless playback.
+ *
+ **************************************************************************/
+int XDpDma_PlayAudio(XDpDma *InstancePtr, XDpDma_AudioBuffer *Buffer,
+		      u8 ChannelNum)
+{
+	XDpDma_AudioChannel *Channel;
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(Buffer != NULL);
+	Xil_AssertNonvoid(Buffer->Size >= 512);
+	Xil_AssertNonvoid(Buffer->Size % 128 == 0);
+	Xil_AssertNonvoid(Buffer->Address % 128 == 0);
+
+	Channel = &InstancePtr->Audio[ChannelNum];
+	Channel->Buffer = Buffer;
+
+	if(Channel->Current == NULL) {
+		Channel->TriggerStatus = XDPDMA_TRIGGER_EN;
+		Channel->Current = &Channel->Descriptor0;
+		Channel->Used = 0;
+	}
+
+else if(Channel->Current == &Channel->Descriptor0) {
+		/* Check if descriptor chain can be updated */
+		if(Channel->Descriptor1.MSB_Timestamp >>
+		   XDPDMA_DESC_DONE_SHIFT) {
+			Channel->Current = NULL;
+			return XST_FAILURE;
+		}
+		else if(Channel->Descriptor7.MSB_Timestamp >>
+			XDPDMA_DESC_DONE_SHIFT || !(Channel->Used)) {
+			Channel->Descriptor3.Control = XDPDMA_DESC_PREAMBLE |
+				XDPDMA_DESC_UPDATE | XDPDMA_DESC_IGNR_DONE;
+			Channel->Descriptor3.NEXT_DESR =
+				(INTPTR) &Channel->Descriptor4;
+			Channel->Descriptor3.ADDR_EXT &=
+				~XDPDMA_DESCRIPTOR_ADDR_EXT_DSC_NXT_MASK;
+			Channel->Descriptor3.ADDR_EXT |=
+				(INTPTR) &Channel->Descriptor4 >> 32;
+			Channel->Current = &Channel->Descriptor4;
+			Channel->Used = 1;
+			XDpDma_InitAudioDescriptor(Channel, Buffer);
+		}
+		else {
+			return XST_FAILURE;
+		}
+	}
+
+	else if(Channel->Current == &Channel->Descriptor4)  {
+		/* Check if descriptor chain can be updated */
+		if(Channel->Descriptor5.MSB_Timestamp >>
+		   XDPDMA_DESC_DONE_SHIFT) {
+			Channel->Current = NULL;
+			return XST_FAILURE;
+		}
+		else if(Channel->Descriptor3.MSB_Timestamp >>
+			XDPDMA_DESC_DONE_SHIFT) {
+			Channel->Descriptor7.Control = XDPDMA_DESC_PREAMBLE |
+				XDPDMA_DESC_UPDATE | XDPDMA_DESC_IGNR_DONE;
+			Channel->Descriptor7.NEXT_DESR =
+				(INTPTR) &Channel->Descriptor0;
+			Channel->Descriptor7.ADDR_EXT &=
+				~XDPDMA_DESCRIPTOR_ADDR_EXT_DSC_NXT_MASK;
+			Channel->Descriptor7.ADDR_EXT |=
+				(INTPTR) &Channel->Descriptor0 >> 32;
+			Channel->Current = &Channel->Descriptor0;
+			XDpDma_InitAudioDescriptor(Channel, Buffer);
+		}
+		else {
+			return XST_FAILURE;
+		}
+	}
+
+	return XST_SUCCESS;
+
+}
+/*************************************************************************/
+/**
+ *
+ * This function sets the channel with the latest framebuffer and the
+ * available descriptor for transfer on the next Vsync.
+ *
+ * @param    InstancePtr is pointer to the instance of DPDMA.
+ * @param    Channel indicates which channels are being setup for transfer.
+ *
+ * @return   None.
+ *
+ * @note     None.
+ *
+ **************************************************************************/
+void XDpDma_SetupChannel(XDpDma *InstancePtr, XDpDma_ChannelType Channel)
+{
+	XDpDma_Channel *Chan;
+	XDpDma_AudioChannel *AudChan;
+	XDpDma_FrameBuffer *FB;
+	XDpDma_AudioBuffer *AudioBuffer;
+	u8 Index, NumPlanes;
+	Xil_AssertVoid(InstancePtr != NULL);
+
+	switch(Channel) {
+		case VideoChan:
+			Xil_AssertVoid(InstancePtr->Video.VideoInfo != NULL);
+			Xil_AssertVoid(InstancePtr->Video.FrameBuffer != NULL);
+			NumPlanes = InstancePtr->Video.VideoInfo->Mode;
+			for(Index = 0; Index <= NumPlanes; Index++) {
+				Chan = &InstancePtr->Video.Channel[Index];
+				FB = InstancePtr->Video.FrameBuffer[Index];
+				XDpDma_UpdateVideoDescriptor(Chan);
+				XDpDma_InitVideoDescriptor(Chan->Current, FB);
+				XDpDma_SetDescriptorAddress(InstancePtr,
+							    Index);
+			}
+			break;
+
+		case GraphicsChan:
+			Xil_AssertVoid(InstancePtr->Gfx.VideoInfo != NULL);
+			Xil_AssertVoid(InstancePtr->Gfx.FrameBuffer != NULL);
+			Chan = &InstancePtr->Gfx.Channel;
+			FB = InstancePtr->Gfx.FrameBuffer;
+			XDpDma_UpdateVideoDescriptor(Chan);
+			XDpDma_InitVideoDescriptor(Chan->Current, FB);
+			XDpDma_SetDescriptorAddress(InstancePtr,
+						    XDPDMA_GRAPHICS_CHANNEL);
+			break;
+
+		case AudioChan0:
+			Xil_AssertVoid(InstancePtr->Audio[0].Buffer != NULL);
+			AudChan = &InstancePtr->Audio[0];
+			AudioBuffer = InstancePtr->Audio[0].Buffer;
+			XDpDma_InitAudioDescriptor(AudChan, AudioBuffer);
+			XDpDma_SetDescriptorAddress(InstancePtr,
+						    XDPDMA_AUDIO_CHANNEL0);
+			break;
+		case AudioChan1:
+			Xil_AssertVoid(InstancePtr->Audio[1].Buffer != NULL);
+			AudChan = &InstancePtr->Audio[1];
+			AudioBuffer = InstancePtr->Audio[1].Buffer;
+			XDpDma_InitAudioDescriptor(AudChan, AudioBuffer);
+			XDpDma_SetDescriptorAddress(InstancePtr,
+						    XDPDMA_AUDIO_CHANNEL1);
+			break;
+	}
+}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/dpdma_v1_0/src/xdpdma.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/dpdma_v1_0/src/xdpdma.h
new file mode 100644
index 000000000..95315b058
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/dpdma_v1_0/src/xdpdma.h
@@ -0,0 +1,283 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2017 Xilinx, Inc. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * Use of the Software is limited solely to applications:
+ * (a) running on a Xilinx device, or
+ * (b) that interact with a Xilinx device through a bus or interconnect.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+ * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Except as contained in this notice, the name of the Xilinx shall not be used
+ * in advertising or otherwise to promote the sale, use or other dealings in
+ * this Software without prior written authorization from Xilinx.
+ *
+ ******************************************************************************/
+
+/*****************************************************************************/
+/**
+ *
+ * @file xdpdma.h
+ *
+ * This file defines the functions implemented by the DPDMA driver present
+ * in the Zynq Ultrascale MP.
+ *
+ * @note	None.
+ *
+ * 
+ * MODIFICATION HISTORY:
+ *
+ * Ver	Who   Date     Changes
+ * ---- ----- -------- ----------------------------------------------------
+ * 1.0  aad   04/12/16 Initial release.
+ *
+ *****************************************************************************/
+
+
+#ifndef XDPDMA_H_
+/* Prevent circular inclusions by using protection macros. */
+#define XDPDMA_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files **********************************/
+
+#include "xdpdma_hw.h"
+#include "xvidc.h"
+#include "xil_io.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xavbuf.h"
+/************************** Constant Definitions ******************************/
+
+/* Alignment for DPDMA Descriptor and Payload */
+#define XDPDMA_DESCRIPTOR_ALIGN 256
+/* DPDMA preamble field */
+#define XDPDMA_DESCRIPTOR_PREAMBLE 0xA5
+/**************************** Type Definitions ********************************/
+
+/**
+ *  This typedef describes the DPDMA descriptor structure and its internals
+ *  which will be used when fetching data from a nonlive path
+ */
+typedef struct {
+	u32 Control;			/**<	[7:0] Descriptor Preamble
+						[8] Enable completion Interrupt
+						[9] Enable descriptor update
+						[10] Ignore Done
+						[11] AXI burst type
+						[15:12] AXACHE
+						[17:16] AXPROT
+						[18] Descriptor mode
+						[19] Last Descriptor
+						[20] Enable CRC
+						[21] Last descriptor frame
+						[31:22] Reserved */
+	u32 DSCR_ID;			/**<	[15:0] Descriptor ID
+						[31:16] Reserved */
+	u32 XFER_SIZE;			/**<	Size of transfer in bytes */
+	u32 LINE_SIZE_STRIDE;		/**<	[17:0] Horizontal Resolution
+						[31:18] Stride */
+	u32 LSB_Timestamp;		/**<	LSB of the Timestamp */
+	u32 MSB_Timestamp;		/**<	MSB of the Timestamp */
+	u32 ADDR_EXT;			/**<	[15:0] Next descriptor
+						extenstion
+						[31:16] SRC address extemsion */
+	u32 NEXT_DESR;			/**<	Address of next descriptor */
+	u32 SRC_ADDR;			/**<	Source Address */
+	u32 ADDR_EXT_23;		/**<	[15:0] Address extension for SRC
+						Address2
+						[31:16] Address extension for
+						SRC Address 3 */
+	u32 ADDR_EXT_45;		/**<	[15:0] Address extension for SRC
+						Address4
+						[31:16] Address extension for
+						SRC Address 5 */
+	u32 SRC_ADDR2;			/**<	Source address of 2nd page */
+	u32 SRC_ADDR3;			/**<	Source address of 3rd page */
+	u32 SRC_ADDR4;			/**<	Source address of 4th page */
+	u32 SRC_ADDR5;			/**<	Source address of 5th page */
+	u32 CRC;			/**<	Reserved */
+
+} XDpDma_Descriptor __attribute__ ((aligned(XDPDMA_DESCRIPTOR_ALIGN)));
+
+/**
+ * This typedef contains configuration information for the DPDMA.
+ */
+typedef struct {
+	u16 DeviceId;			/**< Device ID */
+	u32 BaseAddr;			/**< Base Address */
+} XDpDma_Config;
+
+/**
+ * The following data structure enumerates the types of
+ * DPDMA channels
+ */
+typedef enum {
+	VideoChan,
+	GraphicsChan,
+	AudioChan0,
+	AudioChan1,
+} XDpDma_ChannelType;
+
+/**
+ * This typedef lists the channel status.
+ */
+typedef enum {
+	XDPDMA_DISABLE,
+	XDPDMA_ENABLE,
+	XDPDMA_IDLE,
+	XDPDMA_PAUSE
+} XDpDma_ChannelState;
+
+/**
+ * This typedef is the information needed to transfer video info.
+ */
+typedef struct {
+	u64 Address;
+	u32 Size;
+	u32 Stride;
+	u32 LineSize;
+} XDpDma_FrameBuffer;
+/**
+ * This typedef is the information needed to transfer audio info.
+ */
+typedef struct {
+	u64 Address;
+	u64 Size;
+} XDpDma_AudioBuffer;
+
+/**
+ * This typedef defines the Video/Graphics Channel attributes.
+ */
+typedef struct {
+	XDpDma_Descriptor Descriptor0;
+	XDpDma_Descriptor Descriptor1;
+	XDpDma_Descriptor *Current;
+} XDpDma_Channel;
+
+/**
+ * This typedef defines the Video Channel attributes.
+ */
+typedef struct {
+	XDpDma_Channel Channel[3];
+	u8 TriggerStatus;
+	u8 AVBufEn;
+	XAVBuf_VideoAttribute *VideoInfo;
+	XDpDma_FrameBuffer *FrameBuffer[3];
+} XDpDma_VideoChannel;
+
+/**
+ * This typedef defines the Graphics Channel attributes.
+ */
+typedef struct {
+	XDpDma_Channel Channel;
+	u8 TriggerStatus;
+	u8 AVBufEn;
+	XAVBuf_VideoAttribute *VideoInfo;
+	XDpDma_FrameBuffer *FrameBuffer;
+} XDpDma_GfxChannel;
+
+/**
+ * This typedef defines the Audio Channel attributes.
+ */
+typedef struct {
+	XDpDma_Descriptor Descriptor0, Descriptor1, Descriptor2;
+	XDpDma_Descriptor Descriptor3, Descriptor4, Descriptor5;
+	XDpDma_Descriptor Descriptor6, Descriptor7;
+	XDpDma_Descriptor *Current;
+	u8 TriggerStatus;
+	XDpDma_AudioBuffer *Buffer;
+	u8 Used;
+} XDpDma_AudioChannel;
+/*************************************************************************/
+/**
+ * This callback type represents the handler for a DPDMA VSync interrupt.
+ *
+ * @param	InstancePtr is a pointer to the XDpDma instance.
+ *
+ * @note	None.
+ *
+**************************************************************************/
+typedef void (*XDpDma_VSyncInterruptHandler)(void *InstancePtr);
+
+/*************************************************************************/
+/**
+ * This callback type represents the handler for a DPDMA Done interrupt.
+ *
+ * @param	InstancePtr is a pointer to the XDpDma instance.
+ *
+ * @note	None.
+ *
+**************************************************************************/
+typedef void (*XDpDma_DoneInterruptHandler)(void *InstancePtr);
+
+/**
+ * The XDpDma driver instance data representing the DPDMA operation.
+ */
+typedef struct {
+	XDpDma_Config Config;
+	XDpDma_VideoChannel Video;
+	XDpDma_GfxChannel Gfx;
+	XDpDma_AudioChannel Audio[2];
+	XVidC_VideoTiming *Timing;
+	u8 QOS;
+
+	XDpDma_VSyncInterruptHandler VSyncHandler;
+	void * VSyncInterruptHandler;
+
+	XDpDma_DoneInterruptHandler DoneHandler;
+	void * DoneInterruptHandler;
+
+} XDpDma;
+
+void XDpDma_CfgInitialize(XDpDma *InstancePtr, XDpDma_Config *CfgPtr);
+XDpDma_Config *XDpDma_LookupConfig(u16 DeviceId);
+int XDpDma_SetChannelState(XDpDma *InstancePtr, XDpDma_ChannelType Channel,
+					XDpDma_ChannelState ChannelState);
+void XDpDma_SetQOS(XDpDma *InstancePtr, u8 QOS);
+void XDpDma_SetupChannel(XDpDma *InstancePtr, XDpDma_ChannelType Channel);
+int XDpDma_SetVideoFormat(XDpDma *InstancePtr, XAVBuf_VideoFormat Format);
+int XDpDma_SetGraphicsFormat(XDpDma *InstancePtr, XAVBuf_VideoFormat Format);
+void XDpDma_SetVideoTiming(XDpDma *InstancePtr, XVidC_VideoTiming *Timing);
+int XDpDma_Trigger(XDpDma *InstancePtr, XDpDma_ChannelType Channel);
+int XDpDma_ReTrigger(XDpDma *InstancePtr, XDpDma_ChannelType Channel);
+void XDpDma_InterruptEnable(XDpDma *InstancePtr, u32 Mask);
+void XDpDma_InterruptHandler(XDpDma *InstancePtr);
+void XDpDma_VSyncHandler(XDpDma *InstancePtr);
+void XDpDma_DoneHandler(XDpDma *InstancePtr);
+void XDpDma_InitVideoDescriptor(XDpDma_Descriptor *CurrDesc,
+				XDpDma_FrameBuffer *FrameBuffer);
+void  XDpDma_DisplayVideoFrameBuffer(XDpDma *InstancePtr,
+				   XDpDma_FrameBuffer *Plane1,
+				   XDpDma_FrameBuffer *Plane2,
+				   XDpDma_FrameBuffer *Plane3);
+void XDpDma_DisplayGfxFrameBuffer(XDpDma *InstancePtr,
+				   XDpDma_FrameBuffer *Plane);
+void XDpDma_InitAudioDescriptor(XDpDma_AudioChannel *Channel,
+			       XDpDma_AudioBuffer *AudioBuffer);
+int XDpDma_PlayAudio(XDpDma *InstancePtr, XDpDma_AudioBuffer *Buffer,
+		      u8 ChannelNum);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _XDPDMA_H_ */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/dpdma_v1_0/src/xdpdma_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/dpdma_v1_0/src/xdpdma_g.c
new file mode 100644
index 000000000..5bedc6c8b
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/dpdma_v1_0/src/xdpdma_g.c
@@ -0,0 +1,55 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xdpdma.h"
+
+/*
+* The configuration table for devices
+*/
+
+XDpDma_Config XDpDma_ConfigTable[XPAR_XDPDMA_NUM_INSTANCES] =
+{
+	{
+		XPAR_PSU_DPDMA_DEVICE_ID,
+		XPAR_PSU_DPDMA_BASEADDR
+	}
+};
+
+
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/dpdma_v1_0/src/xdpdma_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/dpdma_v1_0/src/xdpdma_hw.h
new file mode 100644
index 000000000..14ebce221
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/dpdma_v1_0/src/xdpdma_hw.h
@@ -0,0 +1,1811 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * Use of the Software is limited solely to applications:
+ * (a) running on a Xilinx device, or
+ * (b) that interact with a Xilinx device through a bus or interconnect.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+ * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ *
+ * Except as contained in this notice, the name of the Xilinx shall not be used
+ * in advertising or otherwise to promote the sale, use or other dealings in
+ * this Software without prior written authorization from Xilinx.
+ *
+ ******************************************************************************/
+
+/*****************************************************************************/
+/**
+ *
+ * @file xdpdma_hw.h
+ *
+ * This header file contains identifiers and low-level driver functions (or
+ * macros) that can be used to access the device. High-level driver functions
+ * are defined in xdpdma.h
+ *
+ * @note	None.
+ *
+ * 
+ * MODIFICATION HISTORY:
+ *
+ * Ver	Who   Date     Changes
+ * ---- ----- -------- ----------------------------------------------------
+ * 1.0  aad   04/12/16 Initial release.
+ *
+ *****************************************************************************/
+
+
+#ifndef XDPDMAHW_H_
+/* Prevent circular inclusions by using protection macros. */
+#define XDPDMAHW_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files **********************************/
+
+#include "xil_io.h"
+
+/************************** Constant Definitions ******************************/
+
+/******************************************************************************/
+/**
+ * Address mapping for the DPDMA.
+ */
+/******************************************************************************/
+/** @name DPDMA registers
+ *  @{
+ */
+
+#define XDPDMA_BASEADDR					0XFD4C0000
+
+/**
+ * Register: XDPDMA_ERR_CTRL
+ */
+#define XDPDMA_ERR_CTRL					0X0000
+
+#define XDPDMA_ERR_CTRL_APB_ERR_RES_SHIFT		0
+#define XDPDMA_ERR_CTRL_APB_ERR_RES_WIDTH		1
+#define XDPDMA_ERR_CTRL_APB_ERR_RES_MASK		0X1
+
+/**
+ * Register: XDPDMA_ISR
+ */
+#define XDPDMA_ISR					0X0004
+
+#define XDPDMA_ISR_VSYNC_INT_SHIFT			27
+#define XDPDMA_ISR_VSYNC_INT_WIDTH			1
+#define XDPDMA_ISR_VSYNC_INT_MASK			0X08000000
+
+#define XDPDMA_ISR_AXI_RD_4K_CROSS_SHIFT		26
+#define XDPDMA_ISR_AXI_RD_4K_CROSS_WIDTH		1
+#define XDPDMA_ISR_AXI_RD_4K_CROSS_MASK			0X04000000
+
+#define XDPDMA_ISR_WR_DATA_FIFO_FULL_SHIFT		25
+#define XDPDMA_ISR_WR_DATA_FIFO_FULL_WIDTH		1
+#define XDPDMA_ISR_WR_DATA_FIFO_FULL_MASK		0X02000000
+
+#define XDPDMA_ISR_WR_CMD_FIFO_FULL_SHIFT		24
+#define XDPDMA_ISR_WR_CMD_FIFO_FULL_WIDTH		1
+#define XDPDMA_ISR_WR_CMD_FIFO_FULL_MASK		0X01000000
+
+#define XDPDMA_ISR_DSCR_ERR5_SHIFT			23
+#define XDPDMA_ISR_DSCR_ERR5_WIDTH			1
+#define XDPDMA_ISR_DSCR_ERR5_MASK			0X800000
+
+#define XDPDMA_ISR_DSCR_ERR4_SHIFT			22
+#define XDPDMA_ISR_DSCR_ERR4_WIDTH			1
+#define XDPDMA_ISR_DSCR_ERR4_MASK			0X400000
+
+#define XDPDMA_ISR_DSCR_ERR3_SHIFT			21
+#define XDPDMA_ISR_DSCR_ERR3_WIDTH			1
+#define XDPDMA_ISR_DSCR_ERR3_MASK			0X200000
+
+#define XDPDMA_ISR_DSCR_ERR2_SHIFT			20
+#define XDPDMA_ISR_DSCR_ERR2_WIDTH			1
+#define XDPDMA_ISR_DSCR_ERR2_MASK			0X100000
+
+#define XDPDMA_ISR_DSCR_ERR1_SHIFT			19
+#define XDPDMA_ISR_DSCR_ERR1_WIDTH			1
+#define XDPDMA_ISR_DSCR_ERR1_MASK			0X80000
+
+#define XDPDMA_ISR_DSCR_ERR0_SHIFT			18
+#define XDPDMA_ISR_DSCR_ERR0_WIDTH			1
+#define XDPDMA_ISR_DSCR_ERR0_MASK			0X40000
+
+#define XDPDMA_ISR_DATA_AXI_ERR5_SHIFT			17
+#define XDPDMA_ISR_DATA_AXI_ERR5_WIDTH			1
+#define XDPDMA_ISR_DATA_AXI_ERR5_MASK			0X20000
+
+#define XDPDMA_ISR_DATA_AXI_ERR4_SHIFT			16
+#define XDPDMA_ISR_DATA_AXI_ERR4_WIDTH			1
+#define XDPDMA_ISR_DATA_AXI_ERR4_MASK			0X10000
+
+#define XDPDMA_ISR_DATA_AXI_ERR3_SHIFT			15
+#define XDPDMA_ISR_DATA_AXI_ERR3_WIDTH			1
+#define XDPDMA_ISR_DATA_AXI_ERR3_MASK			0X8000
+
+#define XDPDMA_ISR_DATA_AXI_ERR2_SHIFT			14
+#define XDPDMA_ISR_DATA_AXI_ERR2_WIDTH			1
+#define XDPDMA_ISR_DATA_AXI_ERR2_MASK			0X4000
+
+#define XDPDMA_ISR_DATA_AXI_ERR1_SHIFT			13
+#define XDPDMA_ISR_DATA_AXI_ERR1_WIDTH			1
+#define XDPDMA_ISR_DATA_AXI_ERR1_MASK			0X2000
+
+#define XDPDMA_ISR_DATA_AXI_ERR0_SHIFT			12
+#define XDPDMA_ISR_DATA_AXI_ERR0_WIDTH			1
+#define XDPDMA_ISR_DATA_AXI_ERR0_MASK			0X1000
+
+#define XDPDMA_ISR_NO_OSTAND_TRAN5_SHIFT		11
+#define XDPDMA_ISR_NO_OSTAND_TRAN5_WIDTH		1
+#define XDPDMA_ISR_NO_OSTAND_TRAN5_MASK			0X0800
+
+#define XDPDMA_ISR_NO_OSTAND_TRAN4_SHIFT		10
+#define XDPDMA_ISR_NO_OSTAND_TRAN4_WIDTH		1
+#define XDPDMA_ISR_NO_OSTAND_TRAN4_MASK			0X0400
+
+#define XDPDMA_ISR_NO_OSTAND_TRAN3_SHIFT		9
+#define XDPDMA_ISR_NO_OSTAND_TRAN3_WIDTH		1
+#define XDPDMA_ISR_NO_OSTAND_TRAN3_MASK			0X0200
+
+#define XDPDMA_ISR_NO_OSTAND_TRAN2_SHIFT		8
+#define XDPDMA_ISR_NO_OSTAND_TRAN2_WIDTH		1
+#define XDPDMA_ISR_NO_OSTAND_TRAN2_MASK			0X0100
+
+#define XDPDMA_ISR_NO_OSTAND_TRAN1_SHIFT		7
+#define XDPDMA_ISR_NO_OSTAND_TRAN1_WIDTH		1
+#define XDPDMA_ISR_NO_OSTAND_TRAN1_MASK			0X80
+
+#define XDPDMA_ISR_NO_OSTAND_TRAN0_SHIFT		6
+#define XDPDMA_ISR_NO_OSTAND_TRAN0_WIDTH		1
+#define XDPDMA_ISR_NO_OSTAND_TRAN0_MASK			0X40
+
+#define XDPDMA_ISR_DSCR_DONE5_SHIFT			5
+#define XDPDMA_ISR_DSCR_DONE5_WIDTH			1
+#define XDPDMA_ISR_DSCR_DONE5_MASK			0X20
+
+#define XDPDMA_ISR_DSCR_DONE4_SHIFT			4
+#define XDPDMA_ISR_DSCR_DONE4_WIDTH			1
+#define XDPDMA_ISR_DSCR_DONE4_MASK			0X10
+
+#define XDPDMA_ISR_DSCR_DONE3_SHIFT			3
+#define XDPDMA_ISR_DSCR_DONE3_WIDTH			1
+#define XDPDMA_ISR_DSCR_DONE3_MASK			0X8
+
+#define XDPDMA_ISR_DSCR_DONE2_SHIFT			2
+#define XDPDMA_ISR_DSCR_DONE2_WIDTH			1
+#define XDPDMA_ISR_DSCR_DONE2_MASK			0X4
+
+#define XDPDMA_ISR_DSCR_DONE1_SHIFT			1
+#define XDPDMA_ISR_DSCR_DONE1_WIDTH			1
+#define XDPDMA_ISR_DSCR_DONE1_MASK			0X2
+
+#define XDPDMA_ISR_DSCR_DONE0_SHIFT			0
+#define XDPDMA_ISR_DSCR_DONE0_WIDTH			1
+#define XDPDMA_ISR_DSCR_DONE0_MASK			0X1
+
+/**
+ * Register: XDPDMA_IMR
+ */
+#define XDPDMA_IMR					0X0008
+
+#define XDPDMA_IMR_VSYNC_INT_SHIFT			27
+#define XDPDMA_IMR_VSYNC_INT_WIDTH			1
+#define XDPDMA_IMR_VSYNC_INT_MASK			0X08000000
+
+#define XDPDMA_IMR_AXI_RD_4K_CROSS_SHIFT		26
+#define XDPDMA_IMR_AXI_RD_4K_CROSS_WIDTH		1
+#define XDPDMA_IMR_AXI_RD_4K_CROSS_MASK			0X04000000
+
+#define XDPDMA_IMR_WR_DATA_FIFO_FULL_SHIFT		25
+#define XDPDMA_IMR_WR_DATA_FIFO_FULL_WIDTH		1
+#define XDPDMA_IMR_WR_DATA_FIFO_FULL_MASK		0X02000000
+
+#define XDPDMA_IMR_WR_CMD_FIFO_FULL_SHIFT		24
+#define XDPDMA_IMR_WR_CMD_FIFO_FULL_WIDTH		1
+#define XDPDMA_IMR_WR_CMD_FIFO_FULL_MASK		0X01000000
+
+#define XDPDMA_IMR_DSCR_ERR5_SHIFT			23
+#define XDPDMA_IMR_DSCR_ERR5_WIDTH			1
+#define XDPDMA_IMR_DSCR_ERR5_MASK			0X800000
+
+#define XDPDMA_IMR_DSCR_ERR4_SHIFT			22
+#define XDPDMA_IMR_DSCR_ERR4_WIDTH			1
+#define XDPDMA_IMR_DSCR_ERR4_MASK			0X400000
+
+#define XDPDMA_IMR_DSCR_ERR3_SHIFT			21
+#define XDPDMA_IMR_DSCR_ERR3_WIDTH			1
+#define XDPDMA_IMR_DSCR_ERR3_MASK			0X200000
+
+#define XDPDMA_IMR_DSCR_ERR2_SHIFT			20
+#define XDPDMA_IMR_DSCR_ERR2_WIDTH			1
+#define XDPDMA_IMR_DSCR_ERR2_MASK			0X100000
+
+#define XDPDMA_IMR_DSCR_ERR1_SHIFT			19
+#define XDPDMA_IMR_DSCR_ERR1_WIDTH			1
+#define XDPDMA_IMR_DSCR_ERR1_MASK			0X80000
+
+#define XDPDMA_IMR_DSCR_ERR0_SHIFT			18
+#define XDPDMA_IMR_DSCR_ERR0_WIDTH			1
+#define XDPDMA_IMR_DSCR_ERR0_MASK			0X40000
+
+#define XDPDMA_IMR_DATA_AXI_ERR5_SHIFT			17
+#define XDPDMA_IMR_DATA_AXI_ERR5_WIDTH			1
+#define XDPDMA_IMR_DATA_AXI_ERR5_MASK			0X20000
+
+#define XDPDMA_IMR_DATA_AXI_ERR4_SHIFT			16
+#define XDPDMA_IMR_DATA_AXI_ERR4_WIDTH			1
+#define XDPDMA_IMR_DATA_AXI_ERR4_MASK			0X10000
+
+#define XDPDMA_IMR_DATA_AXI_ERR3_SHIFT			15
+#define XDPDMA_IMR_DATA_AXI_ERR3_WIDTH			1
+#define XDPDMA_IMR_DATA_AXI_ERR3_MASK			0X8000
+
+#define XDPDMA_IMR_DATA_AXI_ERR2_SHIFT			14
+#define XDPDMA_IMR_DATA_AXI_ERR2_WIDTH			1
+#define XDPDMA_IMR_DATA_AXI_ERR2_MASK			0X4000
+
+#define XDPDMA_IMR_DATA_AXI_ERR1_SHIFT			13
+#define XDPDMA_IMR_DATA_AXI_ERR1_WIDTH			1
+#define XDPDMA_IMR_DATA_AXI_ERR1_MASK			0X2000
+
+#define XDPDMA_IMR_DATA_AXI_ERR0_SHIFT			12
+#define XDPDMA_IMR_DATA_AXI_ERR0_WIDTH			1
+#define XDPDMA_IMR_DATA_AXI_ERR0_MASK			0X1000
+
+#define XDPDMA_IMR_NO_OSTAND_TRAN5_SHIFT		11
+#define XDPDMA_IMR_NO_OSTAND_TRAN5_WIDTH		1
+#define XDPDMA_IMR_NO_OSTAND_TRAN5_MASK			0X0800
+
+#define XDPDMA_IMR_NO_OSTAND_TRAN4_SHIFT		10
+#define XDPDMA_IMR_NO_OSTAND_TRAN4_WIDTH		1
+#define XDPDMA_IMR_NO_OSTAND_TRAN4_MASK			0X0400
+
+#define XDPDMA_IMR_NO_OSTAND_TRAN3_SHIFT		9
+#define XDPDMA_IMR_NO_OSTAND_TRAN3_WIDTH		1
+#define XDPDMA_IMR_NO_OSTAND_TRAN3_MASK			0X0200
+
+#define XDPDMA_IMR_NO_OSTAND_TRAN2_SHIFT		8
+#define XDPDMA_IMR_NO_OSTAND_TRAN2_WIDTH		1
+#define XDPDMA_IMR_NO_OSTAND_TRAN2_MASK			0X0100
+
+#define XDPDMA_IMR_NO_OSTAND_TRAN1_SHIFT		7
+#define XDPDMA_IMR_NO_OSTAND_TRAN1_WIDTH		1
+#define XDPDMA_IMR_NO_OSTAND_TRAN1_MASK			0X80
+
+#define XDPDMA_IMR_NO_OSTAND_TRAN0_SHIFT		6
+#define XDPDMA_IMR_NO_OSTAND_TRAN0_WIDTH		1
+#define XDPDMA_IMR_NO_OSTAND_TRAN0_MASK			0X40
+
+#define XDPDMA_IMR_DSCR_DONE5_SHIFT			5
+#define XDPDMA_IMR_DSCR_DONE5_WIDTH			1
+#define XDPDMA_IMR_DSCR_DONE5_MASK			0X20
+
+#define XDPDMA_IMR_DSCR_DONE4_SHIFT			4
+#define XDPDMA_IMR_DSCR_DONE4_WIDTH			1
+#define XDPDMA_IMR_DSCR_DONE4_MASK			0X10
+
+#define XDPDMA_IMR_DSCR_DONE3_SHIFT			3
+#define XDPDMA_IMR_DSCR_DONE3_WIDTH			1
+#define XDPDMA_IMR_DSCR_DONE3_MASK			0X8
+
+#define XDPDMA_IMR_DSCR_DONE2_SHIFT			2
+#define XDPDMA_IMR_DSCR_DONE2_WIDTH			1
+#define XDPDMA_IMR_DSCR_DONE2_MASK			0X4
+
+#define XDPDMA_IMR_DSCR_DONE1_SHIFT			1
+#define XDPDMA_IMR_DSCR_DONE1_WIDTH			1
+#define XDPDMA_IMR_DSCR_DONE1_MASK			0X2
+
+#define XDPDMA_IMR_DSCR_DONE0_SHIFT			0
+#define XDPDMA_IMR_DSCR_DONE0_WIDTH			1
+#define XDPDMA_IMR_DSCR_DONE0_MASK			0X1
+
+/**
+ * Register: XDPDMA_IEN
+ */
+#define XDPDMA_IEN					0X000C
+
+#define XDPDMA_IEN_VSYNC_INT_SHIFT			27
+#define XDPDMA_IEN_VSYNC_INT_WIDTH			1
+#define XDPDMA_IEN_VSYNC_INT_MASK			0X08000000
+
+#define XDPDMA_IEN_AXI_RD_4K_CROSS_SHIFT		26
+#define XDPDMA_IEN_AXI_RD_4K_CROSS_WIDTH		1
+#define XDPDMA_IEN_AXI_RD_4K_CROSS_MASK			0X04000000
+
+#define XDPDMA_IEN_WR_DATA_FIFO_FULL_SHIFT		25
+#define XDPDMA_IEN_WR_DATA_FIFO_FULL_WIDTH		1
+#define XDPDMA_IEN_WR_DATA_FIFO_FULL_MASK		0X02000000
+
+#define XDPDMA_IEN_WR_CMD_FIFO_FULL_SHIFT		24
+#define XDPDMA_IEN_WR_CMD_FIFO_FULL_WIDTH		1
+#define XDPDMA_IEN_WR_CMD_FIFO_FULL_MASK		0X01000000
+
+#define XDPDMA_IEN_DSCR_ERR5_SHIFT			23
+#define XDPDMA_IEN_DSCR_ERR5_WIDTH			1
+#define XDPDMA_IEN_DSCR_ERR5_MASK			0X800000
+
+#define XDPDMA_IEN_DSCR_ERR4_SHIFT			22
+#define XDPDMA_IEN_DSCR_ERR4_WIDTH			1
+#define XDPDMA_IEN_DSCR_ERR4_MASK			0X400000
+
+#define XDPDMA_IEN_DSCR_ERR3_SHIFT			21
+#define XDPDMA_IEN_DSCR_ERR3_WIDTH			1
+#define XDPDMA_IEN_DSCR_ERR3_MASK			0X200000
+
+#define XDPDMA_IEN_DSCR_ERR2_SHIFT			20
+#define XDPDMA_IEN_DSCR_ERR2_WIDTH			1
+#define XDPDMA_IEN_DSCR_ERR2_MASK			0X100000
+
+#define XDPDMA_IEN_DSCR_ERR1_SHIFT			19
+#define XDPDMA_IEN_DSCR_ERR1_WIDTH			1
+#define XDPDMA_IEN_DSCR_ERR1_MASK			0X80000
+
+#define XDPDMA_IEN_DSCR_ERR0_SHIFT			18
+#define XDPDMA_IEN_DSCR_ERR0_WIDTH			1
+#define XDPDMA_IEN_DSCR_ERR0_MASK			0X40000
+
+#define XDPDMA_IEN_DATA_AXI_ERR5_SHIFT			17
+#define XDPDMA_IEN_DATA_AXI_ERR5_WIDTH			1
+#define XDPDMA_IEN_DATA_AXI_ERR5_MASK			0X20000
+
+#define XDPDMA_IEN_DATA_AXI_ERR4_SHIFT			16
+#define XDPDMA_IEN_DATA_AXI_ERR4_WIDTH			1
+#define XDPDMA_IEN_DATA_AXI_ERR4_MASK			0X10000
+
+#define XDPDMA_IEN_DATA_AXI_ERR3_SHIFT			15
+#define XDPDMA_IEN_DATA_AXI_ERR3_WIDTH			1
+#define XDPDMA_IEN_DATA_AXI_ERR3_MASK			0X8000
+
+#define XDPDMA_IEN_DATA_AXI_ERR2_SHIFT			14
+#define XDPDMA_IEN_DATA_AXI_ERR2_WIDTH			1
+#define XDPDMA_IEN_DATA_AXI_ERR2_MASK			0X4000
+
+#define XDPDMA_IEN_DATA_AXI_ERR1_SHIFT			13
+#define XDPDMA_IEN_DATA_AXI_ERR1_WIDTH			1
+#define XDPDMA_IEN_DATA_AXI_ERR1_MASK			0X2000
+
+#define XDPDMA_IEN_DATA_AXI_ERR0_SHIFT			12
+#define XDPDMA_IEN_DATA_AXI_ERR0_WIDTH			1
+#define XDPDMA_IEN_DATA_AXI_ERR0_MASK			0X1000
+
+#define XDPDMA_IEN_NO_OSTAND_TRAN5_SHIFT		11
+#define XDPDMA_IEN_NO_OSTAND_TRAN5_WIDTH		1
+#define XDPDMA_IEN_NO_OSTAND_TRAN5_MASK			0X0800
+
+#define XDPDMA_IEN_NO_OSTAND_TRAN4_SHIFT		10
+#define XDPDMA_IEN_NO_OSTAND_TRAN4_WIDTH		1
+#define XDPDMA_IEN_NO_OSTAND_TRAN4_MASK			0X0400
+
+#define XDPDMA_IEN_NO_OSTAND_TRAN3_SHIFT		9
+#define XDPDMA_IEN_NO_OSTAND_TRAN3_WIDTH		1
+#define XDPDMA_IEN_NO_OSTAND_TRAN3_MASK			0X0200
+
+#define XDPDMA_IEN_NO_OSTAND_TRAN2_SHIFT		8
+#define XDPDMA_IEN_NO_OSTAND_TRAN2_WIDTH		1
+#define XDPDMA_IEN_NO_OSTAND_TRAN2_MASK			0X0100
+
+#define XDPDMA_IEN_NO_OSTAND_TRAN1_SHIFT		7
+#define XDPDMA_IEN_NO_OSTAND_TRAN1_WIDTH		1
+#define XDPDMA_IEN_NO_OSTAND_TRAN1_MASK			0X80
+
+#define XDPDMA_IEN_NO_OSTAND_TRAN0_SHIFT		6
+#define XDPDMA_IEN_NO_OSTAND_TRAN0_WIDTH		1
+#define XDPDMA_IEN_NO_OSTAND_TRAN0_MASK			0X40
+
+#define XDPDMA_IEN_DSCR_DONE5_SHIFT			5
+#define XDPDMA_IEN_DSCR_DONE5_WIDTH			1
+#define XDPDMA_IEN_DSCR_DONE5_MASK			0X20
+
+#define XDPDMA_IEN_DSCR_DONE4_SHIFT			4
+#define XDPDMA_IEN_DSCR_DONE4_WIDTH			1
+#define XDPDMA_IEN_DSCR_DONE4_MASK			0X10
+
+#define XDPDMA_IEN_DSCR_DONE3_SHIFT			3
+#define XDPDMA_IEN_DSCR_DONE3_WIDTH			1
+#define XDPDMA_IEN_DSCR_DONE3_MASK			0X8
+
+#define XDPDMA_IEN_DSCR_DONE2_SHIFT			2
+#define XDPDMA_IEN_DSCR_DONE2_WIDTH			1
+#define XDPDMA_IEN_DSCR_DONE2_MASK			0X4
+
+#define XDPDMA_IEN_DSCR_DONE1_SHIFT			1
+#define XDPDMA_IEN_DSCR_DONE1_WIDTH			1
+#define XDPDMA_IEN_DSCR_DONE1_MASK			0X2
+
+#define XDPDMA_IEN_DSCR_DONE0_SHIFT			0
+#define XDPDMA_IEN_DSCR_DONE0_WIDTH			1
+#define XDPDMA_IEN_DSCR_DONE0_MASK			0X1
+
+/**
+ * Register: XDPDMA_IDS
+ */
+#define XDPDMA_IDS					0X0010
+
+#define XDPDMA_IDS_VSYNC_INT_SHIFT			27
+#define XDPDMA_IDS_VSYNC_INT_WIDTH			1
+#define XDPDMA_IDS_VSYNC_INT_MASK			0X08000000
+
+#define XDPDMA_IDS_AXI_RD_4K_CROSS_SHIFT		26
+#define XDPDMA_IDS_AXI_RD_4K_CROSS_WIDTH		1
+#define XDPDMA_IDS_AXI_RD_4K_CROSS_MASK		0X04000000
+
+#define XDPDMA_IDS_WR_DATA_FIFO_FULL_SHIFT		25
+#define XDPDMA_IDS_WR_DATA_FIFO_FULL_WIDTH		1
+#define XDPDMA_IDS_WR_DATA_FIFO_FULL_MASK		0X02000000
+
+#define XDPDMA_IDS_WR_CMD_FIFO_FULL_SHIFT		24
+#define XDPDMA_IDS_WR_CMD_FIFO_FULL_WIDTH		1
+#define XDPDMA_IDS_WR_CMD_FIFO_FULL_MASK		0X01000000
+
+#define XDPDMA_IDS_DSCR_ERR5_SHIFT			23
+#define XDPDMA_IDS_DSCR_ERR5_WIDTH			1
+#define XDPDMA_IDS_DSCR_ERR5_MASK			0X800000
+
+#define XDPDMA_IDS_DSCR_ERR4_SHIFT			22
+#define XDPDMA_IDS_DSCR_ERR4_WIDTH			1
+#define XDPDMA_IDS_DSCR_ERR4_MASK			0X400000
+
+#define XDPDMA_IDS_DSCR_ERR3_SHIFT			21
+#define XDPDMA_IDS_DSCR_ERR3_WIDTH			1
+#define XDPDMA_IDS_DSCR_ERR3_MASK			0X200000
+
+#define XDPDMA_IDS_DSCR_ERR2_SHIFT			20
+#define XDPDMA_IDS_DSCR_ERR2_WIDTH			1
+#define XDPDMA_IDS_DSCR_ERR2_MASK			0X100000
+
+#define XDPDMA_IDS_DSCR_ERR1_SHIFT			19
+#define XDPDMA_IDS_DSCR_ERR1_WIDTH			1
+#define XDPDMA_IDS_DSCR_ERR1_MASK			0X80000
+
+#define XDPDMA_IDS_DSCR_ERR0_SHIFT			18
+#define XDPDMA_IDS_DSCR_ERR0_WIDTH			1
+#define XDPDMA_IDS_DSCR_ERR0_MASK			0X40000
+
+#define XDPDMA_IDS_DATA_AXI_ERR5_SHIFT			17
+#define XDPDMA_IDS_DATA_AXI_ERR5_WIDTH			1
+#define XDPDMA_IDS_DATA_AXI_ERR5_MASK			0X20000
+
+#define XDPDMA_IDS_DATA_AXI_ERR4_SHIFT			16
+#define XDPDMA_IDS_DATA_AXI_ERR4_WIDTH			1
+#define XDPDMA_IDS_DATA_AXI_ERR4_MASK			0X10000
+
+#define XDPDMA_IDS_DATA_AXI_ERR3_SHIFT			15
+#define XDPDMA_IDS_DATA_AXI_ERR3_WIDTH			1
+#define XDPDMA_IDS_DATA_AXI_ERR3_MASK			0X8000
+
+#define XDPDMA_IDS_DATA_AXI_ERR2_SHIFT			14
+#define XDPDMA_IDS_DATA_AXI_ERR2_WIDTH			1
+#define XDPDMA_IDS_DATA_AXI_ERR2_MASK			0X4000
+
+#define XDPDMA_IDS_DATA_AXI_ERR1_SHIFT			13
+#define XDPDMA_IDS_DATA_AXI_ERR1_WIDTH			1
+#define XDPDMA_IDS_DATA_AXI_ERR1_MASK			0X2000
+
+#define XDPDMA_IDS_DATA_AXI_ERR0_SHIFT			12
+#define XDPDMA_IDS_DATA_AXI_ERR0_WIDTH			1
+#define XDPDMA_IDS_DATA_AXI_ERR0_MASK			0X1000
+
+#define XDPDMA_IDS_NO_OSTAND_TRAN5_SHIFT		11
+#define XDPDMA_IDS_NO_OSTAND_TRAN5_WIDTH		1
+#define XDPDMA_IDS_NO_OSTAND_TRAN5_MASK			0X0800
+
+#define XDPDMA_IDS_NO_OSTAND_TRAN4_SHIFT		10
+#define XDPDMA_IDS_NO_OSTAND_TRAN4_WIDTH		1
+#define XDPDMA_IDS_NO_OSTAND_TRAN4_MASK			0X0400
+
+#define XDPDMA_IDS_NO_OSTAND_TRAN3_SHIFT		9
+#define XDPDMA_IDS_NO_OSTAND_TRAN3_WIDTH		1
+#define XDPDMA_IDS_NO_OSTAND_TRAN3_MASK			0X0200
+
+#define XDPDMA_IDS_NO_OSTAND_TRAN2_SHIFT		8
+#define XDPDMA_IDS_NO_OSTAND_TRAN2_WIDTH		1
+#define XDPDMA_IDS_NO_OSTAND_TRAN2_MASK			0X0100
+
+#define XDPDMA_IDS_NO_OSTAND_TRAN1_SHIFT		7
+#define XDPDMA_IDS_NO_OSTAND_TRAN1_WIDTH		1
+#define XDPDMA_IDS_NO_OSTAND_TRAN1_MASK			0X80
+
+#define XDPDMA_IDS_NO_OSTAND_TRAN0_SHIFT		6
+#define XDPDMA_IDS_NO_OSTAND_TRAN0_WIDTH		1
+#define XDPDMA_IDS_NO_OSTAND_TRAN0_MASK			0X40
+
+#define XDPDMA_IDS_DSCR_DONE5_SHIFT			5
+#define XDPDMA_IDS_DSCR_DONE5_WIDTH			1
+#define XDPDMA_IDS_DSCR_DONE5_MASK			0X20
+
+#define XDPDMA_IDS_DSCR_DONE4_SHIFT			4
+#define XDPDMA_IDS_DSCR_DONE4_WIDTH			1
+#define XDPDMA_IDS_DSCR_DONE4_MASK			0X10
+
+#define XDPDMA_IDS_DSCR_DONE3_SHIFT			3
+#define XDPDMA_IDS_DSCR_DONE3_WIDTH			1
+#define XDPDMA_IDS_DSCR_DONE3_MASK			0X8
+
+#define XDPDMA_IDS_DSCR_DONE2_SHIFT			2
+#define XDPDMA_IDS_DSCR_DONE2_WIDTH			1
+#define XDPDMA_IDS_DSCR_DONE2_MASK			0X4
+
+#define XDPDMA_IDS_DSCR_DONE1_SHIFT			1
+#define XDPDMA_IDS_DSCR_DONE1_WIDTH			1
+#define XDPDMA_IDS_DSCR_DONE1_MASK			0X2
+
+#define XDPDMA_IDS_DSCR_DONE0_SHIFT			0
+#define XDPDMA_IDS_DSCR_DONE0_WIDTH			1
+#define XDPDMA_IDS_DSCR_DONE0_MASK			0X1
+
+/**
+ * Register: XDPDMA_EISR
+ */
+#define XDPDMA_EISR					0X0014
+
+#define XDPDMA_EISR_RD_CMD_FIFO_FULL_SHIFT		31
+#define XDPDMA_EISR_RD_CMD_FIFO_FULL_WIDTH		1
+#define XDPDMA_EISR_RD_CMD_FIFO_FULL_MASK		0X80000000
+
+#define XDPDMA_EISR_DSCR_DONE_ERR5_SHIFT		30
+#define XDPDMA_EISR_DSCR_DONE_ERR5_WIDTH		1
+#define XDPDMA_EISR_DSCR_DONE_ERR5_MASK			0X40000000
+
+#define XDPDMA_EISR_DSCR_DONE_ERR4_SHIFT		29
+#define XDPDMA_EISR_DSCR_DONE_ERR4_WIDTH		1
+#define XDPDMA_EISR_DSCR_DONE_ERR4_MASK			0X20000000
+
+#define XDPDMA_EISR_DSCR_DONE_ERR3_SHIFT		28
+#define XDPDMA_EISR_DSCR_DONE_ERR3_WIDTH		1
+#define XDPDMA_EISR_DSCR_DONE_ERR3_MASK			0X10000000
+
+#define XDPDMA_EISR_DSCR_DONE_ERR2_SHIFT		27
+#define XDPDMA_EISR_DSCR_DONE_ERR2_WIDTH		1
+#define XDPDMA_EISR_DSCR_DONE_ERR2_MASK			0X08000000
+
+#define XDPDMA_EISR_DSCR_DONE_ERR1_SHIFT		26
+#define XDPDMA_EISR_DSCR_DONE_ERR1_WIDTH		1
+#define XDPDMA_EISR_DSCR_DONE_ERR1_MASK			0X04000000
+
+#define XDPDMA_EISR_DSCR_DONE_ERR0_SHIFT		25
+#define XDPDMA_EISR_DSCR_DONE_ERR0_WIDTH		1
+#define XDPDMA_EISR_DSCR_DONE_ERR0_MASK			0X02000000
+
+#define XDPDMA_EISR_DSCR_WR_AXI_ERR5_SHIFT		24
+#define XDPDMA_EISR_DSCR_WR_AXI_ERR5_WIDTH		1
+#define XDPDMA_EISR_DSCR_WR_AXI_ERR5_MASK		0X01000000
+
+#define XDPDMA_EISR_DSCR_WR_AXI_ERR4_SHIFT		23
+#define XDPDMA_EISR_DSCR_WR_AXI_ERR4_WIDTH		1
+#define XDPDMA_EISR_DSCR_WR_AXI_ERR4_MASK		0X800000
+
+#define XDPDMA_EISR_DSCR_WR_AXI_ERR3_SHIFT		22
+#define XDPDMA_EISR_DSCR_WR_AXI_ERR3_WIDTH		1
+#define XDPDMA_EISR_DSCR_WR_AXI_ERR3_MASK		0X400000
+
+#define XDPDMA_EISR_DSCR_WR_AXI_ERR2_SHIFT		21
+#define XDPDMA_EISR_DSCR_WR_AXI_ERR2_WIDTH		1
+#define XDPDMA_EISR_DSCR_WR_AXI_ERR2_MASK		0X200000
+
+#define XDPDMA_EISR_DSCR_WR_AXI_ERR1_SHIFT		20
+#define XDPDMA_EISR_DSCR_WR_AXI_ERR1_WIDTH		1
+#define XDPDMA_EISR_DSCR_WR_AXI_ERR1_MASK		0X100000
+
+#define XDPDMA_EISR_DSCR_WR_AXI_ERR0_SHIFT		19
+#define XDPDMA_EISR_DSCR_WR_AXI_ERR0_WIDTH		1
+#define XDPDMA_EISR_DSCR_WR_AXI_ERR0_MASK		0X80000
+
+#define XDPDMA_EISR_DSCR_CRC_ERR5_SHIFT			18
+#define XDPDMA_EISR_DSCR_CRC_ERR5_WIDTH			1
+#define XDPDMA_EISR_DSCR_CRC_ERR5_MASK			0X40000
+
+#define XDPDMA_EISR_DSCR_CRC_ERR4_SHIFT			17
+#define XDPDMA_EISR_DSCR_CRC_ERR4_WIDTH			1
+#define XDPDMA_EISR_DSCR_CRC_ERR4_MASK			0X20000
+
+#define XDPDMA_EISR_DSCR_CRC_ERR3_SHIFT			16
+#define XDPDMA_EISR_DSCR_CRC_ERR3_WIDTH			1
+#define XDPDMA_EISR_DSCR_CRC_ERR3_MASK			0X10000
+
+#define XDPDMA_EISR_DSCR_CRC_ERR2_SHIFT			15
+#define XDPDMA_EISR_DSCR_CRC_ERR2_WIDTH			1
+#define XDPDMA_EISR_DSCR_CRC_ERR2_MASK			0X8000
+
+#define XDPDMA_EISR_DSCR_CRC_ERR1_SHIFT			14
+#define XDPDMA_EISR_DSCR_CRC_ERR1_WIDTH			1
+#define XDPDMA_EISR_DSCR_CRC_ERR1_MASK			0X4000
+
+#define XDPDMA_EISR_DSCR_CRC_ERR0_SHIFT			13
+#define XDPDMA_EISR_DSCR_CRC_ERR0_WIDTH			1
+#define XDPDMA_EISR_DSCR_CRC_ERR0_MASK			0X2000
+
+#define XDPDMA_EISR_DSCR_PRE_ERR5_SHIFT			12
+#define XDPDMA_EISR_DSCR_PRE_ERR5_WIDTH			1
+#define XDPDMA_EISR_DSCR_PRE_ERR5_MASK			0X1000
+
+#define XDPDMA_EISR_DSCR_PRE_ERR4_SHIFT			11
+#define XDPDMA_EISR_DSCR_PRE_ERR4_WIDTH			1
+#define XDPDMA_EISR_DSCR_PRE_ERR4_MASK			0X0800
+
+#define XDPDMA_EISR_DSCR_PRE_ERR3_SHIFT			10
+#define XDPDMA_EISR_DSCR_PRE_ERR3_WIDTH			1
+#define XDPDMA_EISR_DSCR_PRE_ERR3_MASK			0X0400
+
+#define XDPDMA_EISR_DSCR_PRE_ERR2_SHIFT			9
+#define XDPDMA_EISR_DSCR_PRE_ERR2_WIDTH			1
+#define XDPDMA_EISR_DSCR_PRE_ERR2_MASK			0X0200
+
+#define XDPDMA_EISR_DSCR_PRE_ERR1_SHIFT			8
+#define XDPDMA_EISR_DSCR_PRE_ERR1_WIDTH			1
+#define XDPDMA_EISR_DSCR_PRE_ERR1_MASK			0X0100
+
+#define XDPDMA_EISR_DSCR_PRE_ERR0_SHIFT			7
+#define XDPDMA_EISR_DSCR_PRE_ERR0_WIDTH			1
+#define XDPDMA_EISR_DSCR_PRE_ERR0_MASK			0X80
+
+#define XDPDMA_EISR_DSCR_RD_AXI_ERR5_SHIFT		6
+#define XDPDMA_EISR_DSCR_RD_AXI_ERR5_WIDTH		1
+#define XDPDMA_EISR_DSCR_RD_AXI_ERR5_MASK		0X40
+
+#define XDPDMA_EISR_DSCR_RD_AXI_ERR4_SHIFT		5
+#define XDPDMA_EISR_DSCR_RD_AXI_ERR4_WIDTH		1
+#define XDPDMA_EISR_DSCR_RD_AXI_ERR4_MASK		0X20
+
+#define XDPDMA_EISR_DSCR_RD_AXI_ERR3_SHIFT		4
+#define XDPDMA_EISR_DSCR_RD_AXI_ERR3_WIDTH		1
+#define XDPDMA_EISR_DSCR_RD_AXI_ERR3_MASK		0X10
+
+#define XDPDMA_EISR_DSCR_RD_AXI_ERR2_SHIFT		3
+#define XDPDMA_EISR_DSCR_RD_AXI_ERR2_WIDTH		1
+#define XDPDMA_EISR_DSCR_RD_AXI_ERR2_MASK		0X8
+
+#define XDPDMA_EISR_DSCR_RD_AXI_ERR1_SHIFT		2
+#define XDPDMA_EISR_DSCR_RD_AXI_ERR1_WIDTH		1
+#define XDPDMA_EISR_DSCR_RD_AXI_ERR1_MASK		0X4
+
+#define XDPDMA_EISR_DSCR_RD_AXI_ERR0_SHIFT		1
+#define XDPDMA_EISR_DSCR_RD_AXI_ERR0_WIDTH		1
+#define XDPDMA_EISR_DSCR_RD_AXI_ERR0_MASK		0X2
+
+#define XDPDMA_EISR_INV_APB_SHIFT			0
+#define XDPDMA_EISR_INV_APB_WIDTH			1
+#define XDPDMA_EISR_INV_APB_MASK			0X1
+
+/**
+ * Register: XDPDMA_EIMR
+ */
+#define XDPDMA_EIMR					0X0018
+
+#define XDPDMA_EIMR_RD_CMD_FIFO_FULL_SHIFT		31
+#define XDPDMA_EIMR_RD_CMD_FIFO_FULL_WIDTH		1
+#define XDPDMA_EIMR_RD_CMD_FIFO_FULL_MASK		0X80000000
+
+#define XDPDMA_EIMR_DSCR_DONE_ERR5_SHIFT		30
+#define XDPDMA_EIMR_DSCR_DONE_ERR5_WIDTH		1
+#define XDPDMA_EIMR_DSCR_DONE_ERR5_MASK			0X40000000
+
+#define XDPDMA_EIMR_DSCR_DONE_ERR4_SHIFT		29
+#define XDPDMA_EIMR_DSCR_DONE_ERR4_WIDTH		1
+#define XDPDMA_EIMR_DSCR_DONE_ERR4_MASK			0X20000000
+
+#define XDPDMA_EIMR_DSCR_DONE_ERR3_SHIFT		28
+#define XDPDMA_EIMR_DSCR_DONE_ERR3_WIDTH		1
+#define XDPDMA_EIMR_DSCR_DONE_ERR3_MASK			0X10000000
+
+#define XDPDMA_EIMR_DSCR_DONE_ERR2_SHIFT		27
+#define XDPDMA_EIMR_DSCR_DONE_ERR2_WIDTH		1
+#define XDPDMA_EIMR_DSCR_DONE_ERR2_MASK			0X08000000
+
+#define XDPDMA_EIMR_DSCR_DONE_ERR1_SHIFT		26
+#define XDPDMA_EIMR_DSCR_DONE_ERR1_WIDTH		1
+#define XDPDMA_EIMR_DSCR_DONE_ERR1_MASK			0X04000000
+
+#define XDPDMA_EIMR_DSCR_DONE_ERR0_SHIFT		25
+#define XDPDMA_EIMR_DSCR_DONE_ERR0_WIDTH		1
+#define XDPDMA_EIMR_DSCR_DONE_ERR0_MASK			0X02000000
+
+#define XDPDMA_EIMR_DSCR_WR_AXI_ERR5_SHIFT		24
+#define XDPDMA_EIMR_DSCR_WR_AXI_ERR5_WIDTH		1
+#define XDPDMA_EIMR_DSCR_WR_AXI_ERR5_MASK		0X01000000
+
+#define XDPDMA_EIMR_DSCR_WR_AXI_ERR4_SHIFT		23
+#define XDPDMA_EIMR_DSCR_WR_AXI_ERR4_WIDTH		1
+#define XDPDMA_EIMR_DSCR_WR_AXI_ERR4_MASK		0X800000
+
+#define XDPDMA_EIMR_DSCR_WR_AXI_ERR3_SHIFT		22
+#define XDPDMA_EIMR_DSCR_WR_AXI_ERR3_WIDTH		1
+#define XDPDMA_EIMR_DSCR_WR_AXI_ERR3_MASK		0X400000
+
+#define XDPDMA_EIMR_DSCR_WR_AXI_ERR2_SHIFT		21
+#define XDPDMA_EIMR_DSCR_WR_AXI_ERR2_WIDTH		1
+#define XDPDMA_EIMR_DSCR_WR_AXI_ERR2_MASK		0X200000
+
+#define XDPDMA_EIMR_DSCR_WR_AXI_ERR1_SHIFT		20
+#define XDPDMA_EIMR_DSCR_WR_AXI_ERR1_WIDTH		1
+#define XDPDMA_EIMR_DSCR_WR_AXI_ERR1_MASK		0X100000
+
+#define XDPDMA_EIMR_DSCR_WR_AXI_ERR0_SHIFT		19
+#define XDPDMA_EIMR_DSCR_WR_AXI_ERR0_WIDTH		1
+#define XDPDMA_EIMR_DSCR_WR_AXI_ERR0_MASK		0X80000
+
+#define XDPDMA_EIMR_DSCR_CRC_ERR5_SHIFT			18
+#define XDPDMA_EIMR_DSCR_CRC_ERR5_WIDTH			1
+#define XDPDMA_EIMR_DSCR_CRC_ERR5_MASK			0X40000
+
+#define XDPDMA_EIMR_DSCR_CRC_ERR4_SHIFT			17
+#define XDPDMA_EIMR_DSCR_CRC_ERR4_WIDTH			1
+#define XDPDMA_EIMR_DSCR_CRC_ERR4_MASK			0X20000
+
+#define XDPDMA_EIMR_DSCR_CRC_ERR3_SHIFT			16
+#define XDPDMA_EIMR_DSCR_CRC_ERR3_WIDTH			1
+#define XDPDMA_EIMR_DSCR_CRC_ERR3_MASK			0X10000
+
+#define XDPDMA_EIMR_DSCR_CRC_ERR2_SHIFT			15
+#define XDPDMA_EIMR_DSCR_CRC_ERR2_WIDTH			1
+#define XDPDMA_EIMR_DSCR_CRC_ERR2_MASK			0X8000
+
+#define XDPDMA_EIMR_DSCR_CRC_ERR1_SHIFT			14
+#define XDPDMA_EIMR_DSCR_CRC_ERR1_WIDTH			1
+#define XDPDMA_EIMR_DSCR_CRC_ERR1_MASK			0X4000
+
+#define XDPDMA_EIMR_DSCR_CRC_ERR0_SHIFT			13
+#define XDPDMA_EIMR_DSCR_CRC_ERR0_WIDTH			1
+#define XDPDMA_EIMR_DSCR_CRC_ERR0_MASK			0X2000
+
+#define XDPDMA_EIMR_DSCR_PRE_ERR5_SHIFT			12
+#define XDPDMA_EIMR_DSCR_PRE_ERR5_WIDTH			1
+#define XDPDMA_EIMR_DSCR_PRE_ERR5_MASK			0X1000
+
+#define XDPDMA_EIMR_DSCR_PRE_ERR4_SHIFT			11
+#define XDPDMA_EIMR_DSCR_PRE_ERR4_WIDTH			1
+#define XDPDMA_EIMR_DSCR_PRE_ERR4_MASK			0X0800
+
+#define XDPDMA_EIMR_DSCR_PRE_ERR3_SHIFT			10
+#define XDPDMA_EIMR_DSCR_PRE_ERR3_WIDTH			1
+#define XDPDMA_EIMR_DSCR_PRE_ERR3_MASK			0X0400
+
+#define XDPDMA_EIMR_DSCR_PRE_ERR2_SHIFT			9
+#define XDPDMA_EIMR_DSCR_PRE_ERR2_WIDTH			1
+#define XDPDMA_EIMR_DSCR_PRE_ERR2_MASK			0X0200
+
+#define XDPDMA_EIMR_DSCR_PRE_ERR1_SHIFT			8
+#define XDPDMA_EIMR_DSCR_PRE_ERR1_WIDTH			1
+#define XDPDMA_EIMR_DSCR_PRE_ERR1_MASK			0X0100
+
+#define XDPDMA_EIMR_DSCR_PRE_ERR0_SHIFT			7
+#define XDPDMA_EIMR_DSCR_PRE_ERR0_WIDTH			1
+#define XDPDMA_EIMR_DSCR_PRE_ERR0_MASK			0X80
+
+#define XDPDMA_EIMR_DSCR_RD_AXI_ERR5_SHIFT		6
+#define XDPDMA_EIMR_DSCR_RD_AXI_ERR5_WIDTH		1
+#define XDPDMA_EIMR_DSCR_RD_AXI_ERR5_MASK		0X40
+
+#define XDPDMA_EIMR_DSCR_RD_AXI_ERR4_SHIFT		5
+#define XDPDMA_EIMR_DSCR_RD_AXI_ERR4_WIDTH		1
+#define XDPDMA_EIMR_DSCR_RD_AXI_ERR4_MASK		0X20
+
+#define XDPDMA_EIMR_DSCR_RD_AXI_ERR3_SHIFT		4
+#define XDPDMA_EIMR_DSCR_RD_AXI_ERR3_WIDTH		1
+#define XDPDMA_EIMR_DSCR_RD_AXI_ERR3_MASK		0X10
+
+#define XDPDMA_EIMR_DSCR_RD_AXI_ERR2_SHIFT		3
+#define XDPDMA_EIMR_DSCR_RD_AXI_ERR2_WIDTH		1
+#define XDPDMA_EIMR_DSCR_RD_AXI_ERR2_MASK		0X8
+
+#define XDPDMA_EIMR_DSCR_RD_AXI_ERR1_SHIFT		2
+#define XDPDMA_EIMR_DSCR_RD_AXI_ERR1_WIDTH		1
+#define XDPDMA_EIMR_DSCR_RD_AXI_ERR1_MASK		0X4
+
+#define XDPDMA_EIMR_DSCR_RD_AXI_ERR0_SHIFT		1
+#define XDPDMA_EIMR_DSCR_RD_AXI_ERR0_WIDTH		1
+#define XDPDMA_EIMR_DSCR_RD_AXI_ERR0_MASK		0X2
+
+#define XDPDMA_EIMR_INV_APB_SHIFT			0
+#define XDPDMA_EIMR_INV_APB_WIDTH			1
+#define XDPDMA_EIMR_INV_APB_MASK			0X1
+
+/**
+ * Register: XDPDMA_EIEN
+ */
+#define XDPDMA_EIEN					0X001C
+
+#define XDPDMA_EIEN_RD_CMD_FIFO_FULL_SHIFT		31
+#define XDPDMA_EIEN_RD_CMD_FIFO_FULL_WIDTH		1
+#define XDPDMA_EIEN_RD_CMD_FIFO_FULL_MASK		0X80000000
+
+#define XDPDMA_EIEN_DSCR_DONE_ERR5_SHIFT		30
+#define XDPDMA_EIEN_DSCR_DONE_ERR5_WIDTH		1
+#define XDPDMA_EIEN_DSCR_DONE_ERR5_MASK			0X40000000
+
+#define XDPDMA_EIEN_DSCR_DONE_ERR4_SHIFT		29
+#define XDPDMA_EIEN_DSCR_DONE_ERR4_WIDTH		1
+#define XDPDMA_EIEN_DSCR_DONE_ERR4_MASK			0X20000000
+
+#define XDPDMA_EIEN_DSCR_DONE_ERR3_SHIFT		28
+#define XDPDMA_EIEN_DSCR_DONE_ERR3_WIDTH		1
+#define XDPDMA_EIEN_DSCR_DONE_ERR3_MASK			0X10000000
+
+#define XDPDMA_EIEN_DSCR_DONE_ERR2_SHIFT		27
+#define XDPDMA_EIEN_DSCR_DONE_ERR2_WIDTH		1
+#define XDPDMA_EIEN_DSCR_DONE_ERR2_MASK			0X08000000
+
+#define XDPDMA_EIEN_DSCR_DONE_ERR1_SHIFT		26
+#define XDPDMA_EIEN_DSCR_DONE_ERR1_WIDTH		1
+#define XDPDMA_EIEN_DSCR_DONE_ERR1_MASK			0X04000000
+
+#define XDPDMA_EIEN_DSCR_DONE_ERR0_SHIFT		25
+#define XDPDMA_EIEN_DSCR_DONE_ERR0_WIDTH		1
+#define XDPDMA_EIEN_DSCR_DONE_ERR0_MASK			0X02000000
+
+#define XDPDMA_EIEN_DSCR_WR_AXI_ERR5_SHIFT		24
+#define XDPDMA_EIEN_DSCR_WR_AXI_ERR5_WIDTH		1
+#define XDPDMA_EIEN_DSCR_WR_AXI_ERR5_MASK		0X01000000
+
+#define XDPDMA_EIEN_DSCR_WR_AXI_ERR4_SHIFT		23
+#define XDPDMA_EIEN_DSCR_WR_AXI_ERR4_WIDTH		1
+#define XDPDMA_EIEN_DSCR_WR_AXI_ERR4_MASK		0X800000
+
+#define XDPDMA_EIEN_DSCR_WR_AXI_ERR3_SHIFT		22
+#define XDPDMA_EIEN_DSCR_WR_AXI_ERR3_WIDTH		1
+#define XDPDMA_EIEN_DSCR_WR_AXI_ERR3_MASK		0X400000
+
+#define XDPDMA_EIEN_DSCR_WR_AXI_ERR2_SHIFT		21
+#define XDPDMA_EIEN_DSCR_WR_AXI_ERR2_WIDTH		1
+#define XDPDMA_EIEN_DSCR_WR_AXI_ERR2_MASK		0X200000
+
+#define XDPDMA_EIEN_DSCR_WR_AXI_ERR1_SHIFT		20
+#define XDPDMA_EIEN_DSCR_WR_AXI_ERR1_WIDTH		1
+#define XDPDMA_EIEN_DSCR_WR_AXI_ERR1_MASK		0X100000
+
+#define XDPDMA_EIEN_DSCR_WR_AXI_ERR0_SHIFT		19
+#define XDPDMA_EIEN_DSCR_WR_AXI_ERR0_WIDTH		1
+#define XDPDMA_EIEN_DSCR_WR_AXI_ERR0_MASK		0X80000
+
+#define XDPDMA_EIEN_DSCR_CRC_ERR5_SHIFT			18
+#define XDPDMA_EIEN_DSCR_CRC_ERR5_WIDTH			1
+#define XDPDMA_EIEN_DSCR_CRC_ERR5_MASK			0X40000
+
+#define XDPDMA_EIEN_DSCR_CRC_ERR4_SHIFT			17
+#define XDPDMA_EIEN_DSCR_CRC_ERR4_WIDTH			1
+#define XDPDMA_EIEN_DSCR_CRC_ERR4_MASK			0X20000
+
+#define XDPDMA_EIEN_DSCR_CRC_ERR3_SHIFT			16
+#define XDPDMA_EIEN_DSCR_CRC_ERR3_WIDTH			1
+#define XDPDMA_EIEN_DSCR_CRC_ERR3_MASK			0X10000
+
+#define XDPDMA_EIEN_DSCR_CRC_ERR2_SHIFT			15
+#define XDPDMA_EIEN_DSCR_CRC_ERR2_WIDTH			1
+#define XDPDMA_EIEN_DSCR_CRC_ERR2_MASK			0X8000
+
+#define XDPDMA_EIEN_DSCR_CRC_ERR1_SHIFT			14
+#define XDPDMA_EIEN_DSCR_CRC_ERR1_WIDTH			1
+#define XDPDMA_EIEN_DSCR_CRC_ERR1_MASK			0X4000
+
+#define XDPDMA_EIEN_DSCR_CRC_ERR0_SHIFT			13
+#define XDPDMA_EIEN_DSCR_CRC_ERR0_WIDTH			1
+#define XDPDMA_EIEN_DSCR_CRC_ERR0_MASK			0X2000
+
+#define XDPDMA_EIEN_DSCR_PRE_ERR5_SHIFT			12
+#define XDPDMA_EIEN_DSCR_PRE_ERR5_WIDTH			1
+#define XDPDMA_EIEN_DSCR_PRE_ERR5_MASK			0X1000
+
+#define XDPDMA_EIEN_DSCR_PRE_ERR4_SHIFT			11
+#define XDPDMA_EIEN_DSCR_PRE_ERR4_WIDTH			1
+#define XDPDMA_EIEN_DSCR_PRE_ERR4_MASK			0X0800
+
+#define XDPDMA_EIEN_DSCR_PRE_ERR3_SHIFT			10
+#define XDPDMA_EIEN_DSCR_PRE_ERR3_WIDTH			1
+#define XDPDMA_EIEN_DSCR_PRE_ERR3_MASK			0X0400
+
+#define XDPDMA_EIEN_DSCR_PRE_ERR2_SHIFT			9
+#define XDPDMA_EIEN_DSCR_PRE_ERR2_WIDTH			1
+#define XDPDMA_EIEN_DSCR_PRE_ERR2_MASK			0X0200
+
+#define XDPDMA_EIEN_DSCR_PRE_ERR1_SHIFT			8
+#define XDPDMA_EIEN_DSCR_PRE_ERR1_WIDTH			1
+#define XDPDMA_EIEN_DSCR_PRE_ERR1_MASK			0X0100
+
+#define XDPDMA_EIEN_DSCR_PRE_ERR0_SHIFT			7
+#define XDPDMA_EIEN_DSCR_PRE_ERR0_WIDTH			1
+#define XDPDMA_EIEN_DSCR_PRE_ERR0_MASK			0X80
+
+#define XDPDMA_EIEN_DSCR_RD_AXI_ERR5_SHIFT		6
+#define XDPDMA_EIEN_DSCR_RD_AXI_ERR5_WIDTH		1
+#define XDPDMA_EIEN_DSCR_RD_AXI_ERR5_MASK		0X40
+
+#define XDPDMA_EIEN_DSCR_RD_AXI_ERR4_SHIFT		5
+#define XDPDMA_EIEN_DSCR_RD_AXI_ERR4_WIDTH		1
+#define XDPDMA_EIEN_DSCR_RD_AXI_ERR4_MASK		0X20
+
+#define XDPDMA_EIEN_DSCR_RD_AXI_ERR3_SHIFT		4
+#define XDPDMA_EIEN_DSCR_RD_AXI_ERR3_WIDTH		1
+#define XDPDMA_EIEN_DSCR_RD_AXI_ERR3_MASK		0X10
+
+#define XDPDMA_EIEN_DSCR_RD_AXI_ERR2_SHIFT		3
+#define XDPDMA_EIEN_DSCR_RD_AXI_ERR2_WIDTH		1
+#define XDPDMA_EIEN_DSCR_RD_AXI_ERR2_MASK		0X8
+
+#define XDPDMA_EIEN_DSCR_RD_AXI_ERR1_SHIFT		2
+#define XDPDMA_EIEN_DSCR_RD_AXI_ERR1_WIDTH		1
+#define XDPDMA_EIEN_DSCR_RD_AXI_ERR1_MASK		0X4
+
+#define XDPDMA_EIEN_DSCR_RD_AXI_ERR0_SHIFT		1
+#define XDPDMA_EIEN_DSCR_RD_AXI_ERR0_WIDTH		1
+#define XDPDMA_EIEN_DSCR_RD_AXI_ERR0_MASK		0X2
+
+#define XDPDMA_EIEN_INV_APB_SHIFT			0
+#define XDPDMA_EIEN_INV_APB_WIDTH			1
+#define XDPDMA_EIEN_INV_APB_MASK			0X1
+
+/**
+ * Register: XDPDMA_EIDS
+ */
+#define XDPDMA_EIDS					0X0020
+
+#define XDPDMA_EIDS_RD_CMD_FIFO_FULL_SHIFT		31
+#define XDPDMA_EIDS_RD_CMD_FIFO_FULL_WIDTH		1
+#define XDPDMA_EIDS_RD_CMD_FIFO_FULL_MASK		0X80000000
+
+#define XDPDMA_EIDS_DSCR_DONE_ERR5_SHIFT		30
+#define XDPDMA_EIDS_DSCR_DONE_ERR5_WIDTH		1
+#define XDPDMA_EIDS_DSCR_DONE_ERR5_MASK			0X40000000
+
+#define XDPDMA_EIDS_DSCR_DONE_ERR4_SHIFT		29
+#define XDPDMA_EIDS_DSCR_DONE_ERR4_WIDTH		1
+#define XDPDMA_EIDS_DSCR_DONE_ERR4_MASK			0X20000000
+
+#define XDPDMA_EIDS_DSCR_DONE_ERR3_SHIFT		28
+#define XDPDMA_EIDS_DSCR_DONE_ERR3_WIDTH		1
+#define XDPDMA_EIDS_DSCR_DONE_ERR3_MASK			0X10000000
+
+#define XDPDMA_EIDS_DSCR_DONE_ERR2_SHIFT		27
+#define XDPDMA_EIDS_DSCR_DONE_ERR2_WIDTH		1
+#define XDPDMA_EIDS_DSCR_DONE_ERR2_MASK			0X08000000
+
+#define XDPDMA_EIDS_DSCR_DONE_ERR1_SHIFT		26
+#define XDPDMA_EIDS_DSCR_DONE_ERR1_WIDTH		1
+#define XDPDMA_EIDS_DSCR_DONE_ERR1_MASK			0X04000000
+
+#define XDPDMA_EIDS_DSCR_DONE_ERR0_SHIFT		25
+#define XDPDMA_EIDS_DSCR_DONE_ERR0_WIDTH		1
+#define XDPDMA_EIDS_DSCR_DONE_ERR0_MASK			0X02000000
+
+#define XDPDMA_EIDS_DSCR_WR_AXI_ERR5_SHIFT		24
+#define XDPDMA_EIDS_DSCR_WR_AXI_ERR5_WIDTH		1
+#define XDPDMA_EIDS_DSCR_WR_AXI_ERR5_MASK		0X01000000
+
+#define XDPDMA_EIDS_DSCR_WR_AXI_ERR4_SHIFT		23
+#define XDPDMA_EIDS_DSCR_WR_AXI_ERR4_WIDTH		1
+#define XDPDMA_EIDS_DSCR_WR_AXI_ERR4_MASK		0X800000
+
+#define XDPDMA_EIDS_DSCR_WR_AXI_ERR3_SHIFT		22
+#define XDPDMA_EIDS_DSCR_WR_AXI_ERR3_WIDTH		1
+#define XDPDMA_EIDS_DSCR_WR_AXI_ERR3_MASK		0X400000
+
+#define XDPDMA_EIDS_DSCR_WR_AXI_ERR2_SHIFT		21
+#define XDPDMA_EIDS_DSCR_WR_AXI_ERR2_WIDTH		1
+#define XDPDMA_EIDS_DSCR_WR_AXI_ERR2_MASK		0X200000
+
+#define XDPDMA_EIDS_DSCR_WR_AXI_ERR1_SHIFT		20
+#define XDPDMA_EIDS_DSCR_WR_AXI_ERR1_WIDTH		1
+#define XDPDMA_EIDS_DSCR_WR_AXI_ERR1_MASK		0X100000
+
+#define XDPDMA_EIDS_DSCR_WR_AXI_ERR0_SHIFT		19
+#define XDPDMA_EIDS_DSCR_WR_AXI_ERR0_WIDTH		1
+#define XDPDMA_EIDS_DSCR_WR_AXI_ERR0_MASK		0X80000
+
+#define XDPDMA_EIDS_DSCR_CRC_ERR5_SHIFT			18
+#define XDPDMA_EIDS_DSCR_CRC_ERR5_WIDTH			1
+#define XDPDMA_EIDS_DSCR_CRC_ERR5_MASK			0X40000
+
+#define XDPDMA_EIDS_DSCR_CRC_ERR4_SHIFT			17
+#define XDPDMA_EIDS_DSCR_CRC_ERR4_WIDTH			1
+#define XDPDMA_EIDS_DSCR_CRC_ERR4_MASK			0X20000
+
+#define XDPDMA_EIDS_DSCR_CRC_ERR3_SHIFT			16
+#define XDPDMA_EIDS_DSCR_CRC_ERR3_WIDTH			1
+#define XDPDMA_EIDS_DSCR_CRC_ERR3_MASK			0X10000
+
+#define XDPDMA_EIDS_DSCR_CRC_ERR2_SHIFT			15
+#define XDPDMA_EIDS_DSCR_CRC_ERR2_WIDTH			1
+#define XDPDMA_EIDS_DSCR_CRC_ERR2_MASK			0X8000
+
+#define XDPDMA_EIDS_DSCR_CRC_ERR1_SHIFT			14
+#define XDPDMA_EIDS_DSCR_CRC_ERR1_WIDTH			1
+#define XDPDMA_EIDS_DSCR_CRC_ERR1_MASK			0X4000
+
+#define XDPDMA_EIDS_DSCR_CRC_ERR0_SHIFT			13
+#define XDPDMA_EIDS_DSCR_CRC_ERR0_WIDTH			1
+#define XDPDMA_EIDS_DSCR_CRC_ERR0_MASK			0X2000
+
+#define XDPDMA_EIDS_DSCR_PRE_ERR5_SHIFT			12
+#define XDPDMA_EIDS_DSCR_PRE_ERR5_WIDTH			1
+#define XDPDMA_EIDS_DSCR_PRE_ERR5_MASK			0X1000
+
+#define XDPDMA_EIDS_DSCR_PRE_ERR4_SHIFT			11
+#define XDPDMA_EIDS_DSCR_PRE_ERR4_WIDTH			1
+#define XDPDMA_EIDS_DSCR_PRE_ERR4_MASK			0X0800
+
+#define XDPDMA_EIDS_DSCR_PRE_ERR3_SHIFT			10
+#define XDPDMA_EIDS_DSCR_PRE_ERR3_WIDTH			1
+#define XDPDMA_EIDS_DSCR_PRE_ERR3_MASK			0X0400
+
+#define XDPDMA_EIDS_DSCR_PRE_ERR2_SHIFT			9
+#define XDPDMA_EIDS_DSCR_PRE_ERR2_WIDTH			1
+#define XDPDMA_EIDS_DSCR_PRE_ERR2_MASK			0X0200
+
+#define XDPDMA_EIDS_DSCR_PRE_ERR1_SHIFT			8
+#define XDPDMA_EIDS_DSCR_PRE_ERR1_WIDTH			1
+#define XDPDMA_EIDS_DSCR_PRE_ERR1_MASK			0X0100
+
+#define XDPDMA_EIDS_DSCR_PRE_ERR0_SHIFT			7
+#define XDPDMA_EIDS_DSCR_PRE_ERR0_WIDTH			1
+#define XDPDMA_EIDS_DSCR_PRE_ERR0_MASK			0X80
+
+#define XDPDMA_EIDS_DSCR_RD_AXI_ERR5_SHIFT		6
+#define XDPDMA_EIDS_DSCR_RD_AXI_ERR5_WIDTH		1
+#define XDPDMA_EIDS_DSCR_RD_AXI_ERR5_MASK		0X40
+
+#define XDPDMA_EIDS_DSCR_RD_AXI_ERR4_SHIFT		5
+#define XDPDMA_EIDS_DSCR_RD_AXI_ERR4_WIDTH		1
+#define XDPDMA_EIDS_DSCR_RD_AXI_ERR4_MASK		0X20
+
+#define XDPDMA_EIDS_DSCR_RD_AXI_ERR3_SHIFT		4
+#define XDPDMA_EIDS_DSCR_RD_AXI_ERR3_WIDTH		1
+#define XDPDMA_EIDS_DSCR_RD_AXI_ERR3_MASK		0X10
+
+#define XDPDMA_EIDS_DSCR_RD_AXI_ERR2_SHIFT		3
+#define XDPDMA_EIDS_DSCR_RD_AXI_ERR2_WIDTH		1
+#define XDPDMA_EIDS_DSCR_RD_AXI_ERR2_MASK		0X8
+
+#define XDPDMA_EIDS_DSCR_RD_AXI_ERR1_SHIFT		2
+#define XDPDMA_EIDS_DSCR_RD_AXI_ERR1_WIDTH		1
+#define XDPDMA_EIDS_DSCR_RD_AXI_ERR1_MASK		0X4
+
+#define XDPDMA_EIDS_DSCR_RD_AXI_ERR0_SHIFT		1
+#define XDPDMA_EIDS_DSCR_RD_AXI_ERR0_WIDTH		1
+#define XDPDMA_EIDS_DSCR_RD_AXI_ERR0_MASK		0X2
+
+#define XDPDMA_EIDS_INV_APB_SHIFT			0
+#define XDPDMA_EIDS_INV_APB_WIDTH			1
+#define XDPDMA_EIDS_INV_APB_MASK			0X1
+
+/**
+ * Register: XDPDMA_CNTL
+ */
+#define XDPDMA_CNTL					0X0100
+
+/**
+ * Register: XDPDMA_GBL
+ */
+#define XDPDMA_GBL					0X0104
+
+#define XDPDMA_GBL_RTRG_CH5_SHIFT			11
+#define XDPDMA_GBL_RTRG_CH5_WIDTH			1
+#define XDPDMA_GBL_RTRG_CH5_MASK			0X0800
+
+#define XDPDMA_GBL_RTRG_CH4_SHIFT			10
+#define XDPDMA_GBL_RTRG_CH4_WIDTH			1
+#define XDPDMA_GBL_RTRG_CH4_MASK			0X0400
+
+#define XDPDMA_GBL_RTRG_CH3_SHIFT			9
+#define XDPDMA_GBL_RTRG_CH3_WIDTH			1
+#define XDPDMA_GBL_RTRG_CH3_MASK			0X0200
+
+#define XDPDMA_GBL_RTRG_CH2_SHIFT			8
+#define XDPDMA_GBL_RTRG_CH2_WIDTH			1
+#define XDPDMA_GBL_RTRG_CH2_MASK			0X0100
+
+#define XDPDMA_GBL_RTRG_CH1_SHIFT			7
+#define XDPDMA_GBL_RTRG_CH1_WIDTH			1
+#define XDPDMA_GBL_RTRG_CH1_MASK			0X80
+
+#define XDPDMA_GBL_RTRG_CH0_SHIFT			6
+#define XDPDMA_GBL_RTRG_CH0_WIDTH			1
+#define XDPDMA_GBL_RTRG_CH0_MASK			0X40
+
+#define XDPDMA_GBL_TRG_CH5_SHIFT			5
+#define XDPDMA_GBL_TRG_CH5_WIDTH			1
+#define XDPDMA_GBL_TRG_CH5_MASK				0X20
+
+#define XDPDMA_GBL_TRG_CH4_SHIFT			4
+#define XDPDMA_GBL_TRG_CH4_WIDTH			1
+#define XDPDMA_GBL_TRG_CH4_MASK				0X10
+
+#define XDPDMA_GBL_TRG_CH3_SHIFT			3
+#define XDPDMA_GBL_TRG_CH3_WIDTH			1
+#define XDPDMA_GBL_TRG_CH3_MASK				0X8
+
+#define XDPDMA_GBL_TRG_CH2_SHIFT			2
+#define XDPDMA_GBL_TRG_CH2_WIDTH			1
+#define XDPDMA_GBL_TRG_CH2_MASK				0X4
+
+#define XDPDMA_GBL_TRG_CH1_SHIFT			1
+#define XDPDMA_GBL_TRG_CH1_WIDTH			1
+#define XDPDMA_GBL_TRG_CH1_MASK				0X2
+
+#define XDPDMA_GBL_TRG_CH0_SHIFT			0
+#define XDPDMA_GBL_TRG_CH0_WIDTH			1
+#define XDPDMA_GBL_TRG_CH0_MASK				0X1
+
+/**
+ * Register: XDPDMA_CH0_DSCR_STRT_ADDRE
+ */
+#define XDPDMA_CH0_DSCR_STRT_ADDRE			0X0200
+
+/**
+ * Register: XDPDMA_CH0_DSCR_STRT_ADDR
+ */
+#define XDPDMA_CH0_DSCR_STRT_ADDR			0X0204
+
+/**
+ * Register: XDPDMA_CH0_DSCR_NEXT_ADDRE
+ */
+#define XDPDMA_CH0_DSCR_NEXT_ADDRE			0X0208
+
+/**
+ * Register: XDPDMA_CH0_DSCR_NEXT_ADDR
+ */
+#define XDPDMA_CH0_DSCR_NEXT_ADDR			0X020C
+
+/**
+ * Register: XDPDMA_CH0_PYLD_CUR_ADDRE
+ */
+#define XDPDMA_CH0_PYLD_CUR_ADDRE			0X0210
+
+/**
+ * Register: XDPDMA_CH0_PYLD_CUR_ADDR
+ */
+#define XDPDMA_CH0_PYLD_CUR_ADDR			0X0214
+
+/**
+ * Register: XDPDMA_CH0_CNTL
+ */
+#define XDPDMA_CH0_CNTL					0X0218
+
+#define XDPDMA_CNTL_QOS_VIDEO				0x11
+
+/**
+ * Register: XDPDMA_CH0_STATUS
+ */
+#define XDPDMA_CH0_STATUS				0X021C
+
+/**
+ * Register: XDPDMA_CH0_VDO
+ */
+#define XDPDMA_CH0_VDO					0X0220
+
+/**
+ * Register: XDPDMA_CH0_PYLD_SZ
+ */
+#define XDPDMA_CH0_PYLD_SZ				0X0224
+
+/**
+ * Register: XDPDMA_CH0_DSCR_ID
+ */
+#define XDPDMA_CH0_DSCR_ID				0X0228
+
+/**
+ * Register: XDPDMA_CH1_DSCR_STRT_ADDRE
+ */
+#define XDPDMA_CH1_DSCR_STRT_ADDRE			0X0300
+
+/**
+ * Register: XDPDMA_CH1_DSCR_STRT_ADDR
+ */
+#define XDPDMA_CH1_DSCR_STRT_ADDR			0X0304
+
+/**
+ * Register: XDPDMA_CH1_DSCR_NEXT_ADDRE
+ */
+#define XDPDMA_CH1_DSCR_NEXT_ADDRE			0X0308
+
+/**
+ * Register: XDPDMA_CH1_DSCR_NEXT_ADDR
+ */
+#define XDPDMA_CH1_DSCR_NEXT_ADDR			0X030C
+
+/**
+ * Register: XDPDMA_CH1_PYLD_CUR_ADDRE
+ */
+#define XDPDMA_CH1_PYLD_CUR_ADDRE			0X0310
+
+/**
+ * Register: XDPDMA_CH1_PYLD_CUR_ADDR
+ */
+#define XDPDMA_CH1_PYLD_CUR_ADDR			0X0314
+
+/**
+ * Register: XDPDMA_CH1_CNTL
+ */
+#define XDPDMA_CH1_CNTL					0X0318
+/**
+ * Register: XDPDMA_CH1_STATUS
+ */
+#define XDPDMA_CH1_STATUS				0X031C
+
+/**
+ * Register: XDPDMA_CH1_VDO
+ */
+#define XDPDMA_CH1_VDO					0X0320
+
+/**
+ * Register: XDPDMA_CH1_PYLD_SZ
+ */
+#define XDPDMA_CH1_PYLD_SZ				0X0324
+
+/**
+ * Register: XDPDMA_CH1_DSCR_ID
+ */
+#define XDPDMA_CH1_DSCR_ID				0X0328
+
+/**
+ * Register: XDPDMA_CH2_DSCR_STRT_ADDRE
+ */
+#define XDPDMA_CH2_DSCR_STRT_ADDRE			0X0400
+
+/**
+ * Register: XDPDMA_CH2_DSCR_STRT_ADDR
+ */
+#define XDPDMA_CH2_DSCR_STRT_ADDR			0X0404
+
+/**
+ * Register: XDPDMA_CH2_DSCR_NEXT_ADDRE
+ */
+#define XDPDMA_CH2_DSCR_NEXT_ADDRE			0X0408
+
+/**
+ * Register: XDPDMA_CH2_DSCR_NEXT_ADDR
+ */
+#define XDPDMA_CH2_DSCR_NEXT_ADDR			0X040C
+
+/**
+ * Register: XDPDMA_CH2_PYLD_CUR_ADDRE
+ */
+#define XDPDMA_CH2_PYLD_CUR_ADDRE			0X0410
+
+/**
+ * Register: XDPDMA_CH2_PYLD_CUR_ADDR
+ */
+#define XDPDMA_CH2_PYLD_CUR_ADDR			0X0414
+
+/**
+ * Register: XDPDMA_CH2_CNTL
+ */
+#define XDPDMA_CH2_CNTL					0X0418
+
+/**
+ * Register: XDPDMA_CH2_STATUS
+ */
+#define XDPDMA_CH2_STATUS				0X041C
+
+/**
+ * Register: XDPDMA_CH2_VDO
+ */
+#define XDPDMA_CH2_VDO					0X0420
+
+/**
+ * Register: XDPDMA_CH2_PYLD_SZ
+ */
+#define XDPDMA_CH2_PYLD_SZ				0X0424
+
+/**
+ * Register: XDPDMA_CH2_DSCR_ID
+ */
+#define XDPDMA_CH2_DSCR_ID				0X0428
+
+/**
+ * Register: XDPDMA_CH3_DSCR_STRT_ADDRE
+ */
+#define XDPDMA_CH3_DSCR_STRT_ADDRE			0X0500
+
+/**
+ * Register: XDPDMA_CH3_DSCR_STRT_ADDR
+ */
+#define XDPDMA_CH3_DSCR_STRT_ADDR			0X0504
+
+/**
+ * Register: XDPDMA_CH3_DSCR_NEXT_ADDRE
+ */
+#define XDPDMA_CH3_DSCR_NEXT_ADDRE			0X0508
+
+/**
+ * Register: XDPDMA_CH3_DSCR_NEXT_ADDR
+ */
+#define XDPDMA_CH3_DSCR_NEXT_ADDR			0X050C
+
+/**
+ * Register: XDPDMA_CH3_PYLD_CUR_ADDRE
+ */
+#define XDPDMA_CH3_PYLD_CUR_ADDRE			0X0510
+
+/**
+ * Register: XDPDMA_CH3_PYLD_CUR_ADDR
+ */
+#define XDPDMA_CH3_PYLD_CUR_ADDR			0X0514
+
+/**
+ * Register: XDPDMA_CH3_CNTL
+ */
+#define XDPDMA_CH3_CNTL					0X0518
+/**
+ * Register: XDPDMA_CH3_STATUS
+ */
+#define XDPDMA_CH3_STATUS				0X051C
+
+/**
+ * Register: XDPDMA_CH3_VDO
+ */
+#define XDPDMA_CH3_VDO					0X0520
+
+/**
+ * Register: XDPDMA_CH3_PYLD_SZ
+ */
+#define XDPDMA_CH3_PYLD_SZ				0X0524
+
+/**
+ * Register: XDPDMA_CH3_DSCR_ID
+ */
+#define XDPDMA_CH3_DSCR_ID				0X0528
+
+/**
+ * Register: XDPDMA_CH4_DSCR_STRT_ADDRE
+ */
+#define XDPDMA_CH4_DSCR_STRT_ADDRE			0X0600
+
+/**
+ * Register: XDPDMA_CH4_DSCR_STRT_ADDR
+ */
+#define XDPDMA_CH4_DSCR_STRT_ADDR			0X0604
+/**
+ * Register: XDPDMA_CH4_DSCR_NEXT_ADDRE
+ */
+#define XDPDMA_CH4_DSCR_NEXT_ADDRE			0X0608
+
+/**
+ * Register: XDPDMA_CH4_DSCR_NEXT_ADDR
+ */
+#define XDPDMA_CH4_DSCR_NEXT_ADDR			0X060C
+
+/**
+ * Register: XDPDMA_CH4_PYLD_CUR_ADDRE
+ */
+#define XDPDMA_CH4_PYLD_CUR_ADDRE			0X0610
+
+/**
+ * Register: XDPDMA_CH4_PYLD_CUR_ADDR
+ */
+#define XDPDMA_CH4_PYLD_CUR_ADDR			0X0614
+
+/**
+ * Register: XDPDMA_CH4_CNTL
+ */
+#define XDPDMA_CH4_CNTL					0X0618
+
+/**
+ * Register: XDPDMA_CH4_STATUS
+ */
+#define XDPDMA_CH4_STATUS				0X061C
+
+/**
+ * Register: XDPDMA_CH4_VDO
+ */
+#define XDPDMA_CH4_VDO					0X0620
+
+/**
+ * Register: XDPDMA_CH4_PYLD_SZ
+ */
+#define XDPDMA_CH4_PYLD_SZ				0X0624
+
+/**
+ * Register: XDPDMA_CH4_DSCR_ID
+ */
+#define XDPDMA_CH4_DSCR_ID				0X0628
+
+/**
+ * Register: XDPDMA_CH5_DSCR_STRT_ADDRE
+ */
+#define XDPDMA_CH5_DSCR_STRT_ADDRE			0X0700
+
+/**
+ * Register: XDPDMA_CH5_DSCR_STRT_ADDR
+ */
+#define XDPDMA_CH5_DSCR_STRT_ADDR			0X0704
+
+/**
+ * Register: XDPDMA_CH5_DSCR_NEXT_ADDRE
+ */
+#define XDPDMA_CH5_DSCR_NEXT_ADDRE			0X0708
+
+/**
+ * Register: XDPDMA_CH5_DSCR_NEXT_ADDR
+ */
+#define XDPDMA_CH5_DSCR_NEXT_ADDR			0X070C
+
+/**
+ * Register: XDPDMA_CH5_PYLD_CUR_ADDRE
+ */
+#define XDPDMA_CH5_PYLD_CUR_ADDRE			0X0710
+
+/**
+ * Register: XDPDMA_CH5_PYLD_CUR_ADDR
+ */
+#define XDPDMA_CH5_PYLD_CUR_ADDR			0X0714
+
+/**
+ * Register: XDPDMA_CH5_CNTL
+ */
+#define XDPDMA_CH5_CNTL					0X0718
+
+/**
+ * Register: XDPDMA_CH5_STATUS
+ */
+#define XDPDMA_CH5_STATUS				0X071C
+
+/**
+ * Register: XDPDMA_CH5_VDO
+ */
+#define XDPDMA_CH5_VDO					0X0720
+
+/**
+ * Register: XDPDMA_CH5_PYLD_SZ
+ */
+#define XDPDMA_CH5_PYLD_SZ				0X0724
+
+/**
+ * Register: XDPDMA_CH5_DSCR_ID
+ */
+#define XDPDMA_CH5_DSCR_ID				0X0728
+
+
+#define XDPDMA_CH_DSCR_STRT_ADDRE_MSB_SHIFT		0
+#define XDPDMA_CH_DSCR_STRT_ADDRE_MSB_WIDTH		16
+#define XDPDMA_CH_DSCR_STRT_ADDRE_MSB_MASK		0XFFFF
+
+
+#define XDPDMA_CH_DSCR_STRT_ADDR_LSB_SHIFT		0
+#define XDPDMA_CH_DSCR_STRT_ADDR_LSB_WIDTH		32
+#define XDPDMA_CH_DSCR_STRT_ADDR_LSB_MASK		0XFFFFFFFF
+
+
+#define XDPDMA_CH_DSCR_NEXT_ADDRE_MSB_SHIFT		0
+#define XDPDMA_CH_DSCR_NEXT_ADDRE_MSB_WIDTH		16
+#define XDPDMA_CH_DSCR_NEXT_ADDRE_MSB_MASK		0XFFFF
+
+
+#define XDPDMA_CH_DSCR_NEXT_ADDR_LSB_SHIFT		0
+#define XDPDMA_CH_DSCR_NEXT_ADDR_LSB_WIDTH		32
+#define XDPDMA_CH_DSCR_NEXT_ADDR_LSB_MASK		0XFFFFFFFF
+
+
+#define XDPDMA_CH_PYLD_CUR_ADDRE_MSB_SHIFT		0
+#define XDPDMA_CH_PYLD_CUR_ADDRE_MSB_WIDTH		16
+#define XDPDMA_CH_PYLD_CUR_ADDRE_MSB_MASK		0XFFFF
+
+#define XDPDMA_CH_PYLD_CUR_ADDR_LSB_SHIFT		0
+#define XDPDMA_CH_PYLD_CUR_ADDR_LSB_WIDTH		32
+#define XDPDMA_CH_PYLD_CUR_ADDR_LSB_MASK		0XFFFFFFFF
+
+#define XDPDMA_CH_CNTL_DSCR_AXCACHE_SHIFT		16
+#define XDPDMA_CH_CNTL_DSCR_AXCACHE_WIDTH		4
+#define XDPDMA_CH_CNTL_DSCR_AXCACHE_MASK		0XF0000
+
+#define XDPDMA_CH_CNTL_DSCR_AXPROT_SHIFT		14
+#define XDPDMA_CH_CNTL_DSCR_AXPROT_WIDTH		2
+#define XDPDMA_CH_CNTL_DSCR_AXPROT_MASK			0XC000
+
+#define XDPDMA_CH_CNTL_QOS_DATA_RD_SHIFT		10
+#define XDPDMA_CH_CNTL_QOS_DATA_RD_WIDTH		4
+#define XDPDMA_CH_CNTL_QOS_DATA_RD_MASK			0X3C00
+
+#define XDPDMA_CH_CNTL_QOS_DSCR_RD_SHIFT		6
+#define XDPDMA_CH_CNTL_QOS_DSCR_RD_WIDTH		4
+#define XDPDMA_CH_CNTL_QOS_DSCR_RD_MASK			0X03C0
+
+#define XDPDMA_CH_CNTL_QOS_DSCR_WR_SHIFT		2
+#define XDPDMA_CH_CNTL_QOS_DSCR_WR_WIDTH		4
+#define XDPDMA_CH_CNTL_QOS_DSCR_WR_MASK			0X3C
+
+#define XDPDMA_CH_CNTL_PAUSE_SHIFT			1
+#define XDPDMA_CH_CNTL_PAUSE_WIDTH			1
+#define XDPDMA_CH_CNTL_PAUSE_MASK			0X2
+
+#define XDPDMA_CH_CNTL_EN_SHIFT				0
+#define XDPDMA_CH_CNTL_EN_WIDTH				1
+#define XDPDMA_CH_CNTL_EN_MASK				0X1
+
+
+#define XDPDMA_CH_STATUS_OTRAN_CNT_SHIFT		21
+#define XDPDMA_CH_STATUS_OTRAN_CNT_WIDTH		4
+#define XDPDMA_CH_STATUS_OTRAN_CNT_MASK			0X01E00000
+
+#define XDPDMA_CH_STATUS_PREAMBLE_SHIFT			13
+#define XDPDMA_CH_STATUS_PREAMBLE_WIDTH			8
+#define XDPDMA_CH_STATUS_PREAMBLE_MASK			0X1FE000
+
+#define XDPDMA_CH_STATUS_EN_DSCR_INTR_SHIFT		12
+#define XDPDMA_CH_STATUS_EN_DSCR_INTR_WIDTH		1
+#define XDPDMA_CH_STATUS_EN_DSCR_INTR_MASK		0X1000
+
+#define XDPDMA_CH_STATUS_EN_DSCR_UP_SHIFT		11
+#define XDPDMA_CH_STATUS_EN_DSCR_UP_WIDTH		1
+#define XDPDMA_CH_STATUS_EN_DSCR_UP_MASK		0X0800
+
+#define XDPDMA_CH_STATUS_DSCR_DONE_SHIFT		10
+#define XDPDMA_CH_STATUS_DSCR_DONE_WIDTH		1
+#define XDPDMA_CH_STATUS_DSCR_DONE_MASK			0X0400
+
+#define XDPDMA_CH_STATUS_IGNR_DONE_SHIFT		9
+#define XDPDMA_CH_STATUS_IGNR_DONE_WIDTH		1
+#define XDPDMA_CH_STATUS_IGNR_DONE_MASK			0X0200
+
+#define XDPDMA_CH_STATUS_LDSCR_FRAME_SHIFT		8
+#define XDPDMA_CH_STATUS_LDSCR_FRAME_WIDTH		1
+#define XDPDMA_CH_STATUS_LDSCR_FRAME_MASK		0X0100
+
+#define XDPDMA_CH_STATUS_LAST_DSCR_SHIFT		7
+#define XDPDMA_CH_STATUS_LAST_DSCR_WIDTH		1
+#define XDPDMA_CH_STATUS_LAST_DSCR_MASK			0X80
+
+#define XDPDMA_CH_STATUS_EN_CRC_SHIFT			6
+#define XDPDMA_CH_STATUS_EN_CRC_WIDTH			1
+#define XDPDMA_CH_STATUS_EN_CRC_MASK			0X40
+
+#define XDPDMA_CH_STATUS_MODE_SHIFT			5
+#define XDPDMA_CH_STATUS_MODE_WIDTH			1
+#define XDPDMA_CH_STATUS_MODE_MASK			0X20
+
+#define XDPDMA_CH_STATUS_BURST_TYPE_SHIFT		4
+#define XDPDMA_CH_STATUS_BURST_TYPE_WIDTH		1
+#define XDPDMA_CH_STATUS_BURST_TYPE_MASK		0X10
+
+#define XDPDMA_CH_STATUS_BURST_LEN_SHIFT		0
+#define XDPDMA_CH_STATUS_BURST_LEN_WIDTH		4
+#define XDPDMA_CH_STATUS_BURST_LEN_MASK			0XF
+
+
+#define XDPDMA_CH_VDO_LINE_LENGTH_SHIFT			14
+#define XDPDMA_CH_VDO_LINE_LENGTH_WIDTH			18
+#define XDPDMA_CH_VDO_LINE_LENGTH_MASK			0XFFFFC000
+
+#define XDPDMA_CH_VDO_STRIDE_SHIFT			0
+#define XDPDMA_CH_VDO_STRIDE_WIDTH			14
+#define XDPDMA_CH_VDO_STRIDE_MASK			0X3FFF
+
+#define XDPDMA_CH_PYLD_SZ_BYTE_SHIFT			0
+#define XDPDMA_CH_PYLD_SZ_BYTE_WIDTH			32
+#define XDPDMA_CH_PYLD_SZ_BYTE_MASK			0XFFFFFFFF
+
+#define XDPDMA_CH_DSCR_ID_VAL_SHIFT			0
+#define XDPDMA_CH_DSCR_ID_VAL_WIDTH			16
+#define XDPDMA_CH_DSCR_ID_VAL_MASK			0XFFFF
+
+/**
+ * Register: XDPDMA_ECO
+ */
+#define XDPDMA_ECO					0X0FFC
+
+#define XDPDMA_ECO_VAL_SHIFT				0
+#define XDPDMA_ECO_VAL_WIDTH				32
+#define XDPDMA_ECO_VAL_MASK				0XFFFFFFFF
+
+/**
+ * DPDMA descriptor
+ */
+
+#define XDPDMA_DESCRIPTOR_CONTROL_PREAMBLE_SHIFT		0
+#define XDPDMA_DESCRIPTOR_CONTROL_PREAMBLE_WIDTH		8
+#define XDPDMA_DESCRIPTOR_CONTROL_PREAMBLE_MASK			0XFF
+
+#define XDPDMA_DESCRIPTOR_CONTROL_EN_COMP_INTR_SHIFT		8
+#define XDPDMA_DESCRIPTOR_CONTROL_EN_COMP_INTR_WIDTH		1
+#define XDPDMA_DESCRIPTOR_CONTROL_EN_COMP_INTR_MASK		0X0100
+
+#define XDPDMA_DESCRIPTOR_CONTROL_EN_DESC_UPDATE_SHIFT		9
+#define XDPDMA_DESCRIPTOR_CONTROL_EN_DESC_UPDATE_WIDTH		1
+#define XDPDMA_DESCRIPTOR_CONTROL_EN_DESC_UPDATE_MASK		0X0200
+
+#define XDPDMA_DESCRIPTOR_CONTROL_IGNORE_DONE_SHIFT		10
+#define XDPDMA_DESCRIPTOR_CONTROL_IGNORE_DONE_WIDTH		1
+#define XDPDMA_DESCRIPTOR_CONTROL_IGNORE_DONE_MASK		0X0400
+
+#define XDPDMA_DESCRIPTOR_CONTROL_AXI_BURST_TYPE_SHIFT		11
+#define XDPDMA_DESCRIPTOR_CONTROL_AXI_BURST_TYPE_WIDTH		1
+#define XDPDMA_DESCRIPTOR_CONTROL_AXI_BURST_TYPE_MASK		0X0800
+
+#define XDPDMA_DESCRIPTOR_CONTROL_AXACACHE_SHIFT		12
+#define XDPDMA_DESCRIPTOR_CONTROL_AXACACHE_WIDTH		4
+#define XDPDMA_DESCRIPTOR_CONTROL_AXACACHE_MASK			0XF000
+
+#define XDPDMA_DESCRIPTOR_CONTROL_AXPROT_SHIFT			16
+#define XDPDMA_DESCRIPTOR_CONTROL_AXPROT_WIDTH			2
+#define XDPDMA_DESCRIPTOR_CONTROL_AXPROT_MASK			0X30000
+
+#define XDPDMA_DESCRIPTOR_CONTROL_MODE_SHIFT			18
+#define XDPDMA_DESCRIPTOR_CONTROL_MODE_WIDTH			1
+#define XDPDMA_DESCRIPTOR_CONTROL_MODE_MASK			0X40000
+
+#define XDPDMA_DESCRIPTOR_CONTROL_LAST_DESC_SHIFT		19
+#define XDPDMA_DESCRIPTOR_CONTROL_LAST_DESC_WIDTH		1
+#define XDPDMA_DESCRIPTOR_CONTROL_LAST_DESC_MASK		0X80000
+
+#define XDPDMA_DESCRIPTOR_CONTROL_ENABLE_CRC_SHIFT		20
+#define XDPDMA_DESCRIPTOR_CONTROL_ENABLE_CRC_WIDTH		1
+#define XDPDMA_DESCRIPTOR_CONTROL_ENABLE_CRC_MASK		0x00100000
+
+#define XDPDMA_DESCRIPTOR_CONTROL_LAST_DESC_FRAME_SHIFT		21
+#define XDPDMA_DESCRIPTOR_CONTROL_LAST_DESC_FRAME_WIDTH		1
+#define XDPDMA_DESCRIPTOR_CONTROL_LAST_DESC_FRAME_MASK		0X200000
+
+#define XDPDMA_DESCRIPTOR_DSCR_ID_SHIFT				0
+#define XDPDMA_DESCRIPTOR_DSCR_ID_WIDTH				16
+#define XDPDMA_DESCRIPTOR_DSCR_ID_MASK				0XFFFF
+
+#define XDPDMA_DESCRIPTOR_XFER_SIZE_SHIFT			0
+#define XDPDMA_DESCRIPTOR_XFER_SIZE_WIDTH			32
+#define XDPDMA_DESCRIPTOR_XFER_SIZE_MASK			0x0000FFFF
+
+#define XDPDMA_DESCRIPTOR_LINE_SIZE_HZ_RES_SHIFT		0
+#define XDPDMA_DESCRIPTOR_LINE_SIZE_HZ_RES_WIDTH		18
+#define XDPDMA_DESCRIPTOR_LINE_SIZE_HZ_RES_MASK			0X3FFFF
+
+#define XDPDMA_DESCRIPTOR_LINE_SIZE_STRIDE_SHIFT		18
+#define XDPDMA_DESCRIPTOR_LINE_SIZE_STRIDE_WIDTH		14
+#define XDPDMA_DESCRIPTOR_LINE_SIZE_STRIDE_MASK			0XFFFC0000
+
+#define XDPDMA_DESCRIPTOR_TS_LSB_SHIFT				0
+#define XDPDMA_DESCRIPTOR_TS_LSB_WIDTH				32
+#define XDPDMA_DESCRIPTOR_TS_LSB_MASK				0XFFFFFFFF
+
+#define XDPDMA_DESCRIPTOR_TS_MSB_SHIFT				0
+#define XDPDMA_DESCRIPTOR_TS_MSB_WIDTH				32
+#define XDPDMA_DESCRIPTOR_TS_MSB_MASK				0XFFFFFFFF
+
+#define XDPDMA_DESCRIPTOR_TS_MSB_TS_SHIFT			0
+#define XDPDMA_DESCRIPTOR_TS_MSB_TS_WIDTH			9
+#define XDPDMA_DESCRIPTOR_TS_MSB_TS_MASK			0X01FF
+
+#define XDPDMA_DESCRIPTOR_TS_MSB_STATUS_SHIFT			31
+#define XDPDMA_DESCRIPTOR_TS_MSB_STATUS_WIDTH			1
+#define XDPDMA_DESCRIPTOR_TS_MSB_STATUS_MASK			0X80000000
+
+#define XDPDMA_DESCRIPTOR_ADDR_EXT_DSC_NXT_SHIFT		0
+#define XDPDMA_DESCRIPTOR_ADDR_EXT_DSC_NXT_WIDTH		16
+#define XDPDMA_DESCRIPTOR_ADDR_EXT_DSC_NXT_MASK			0XFFFF
+
+#define XDPDMA_DESCRIPTOR_ADDR_EXT_SRC_ADDR_EXT_SHIFT		16
+#define XDPDMA_DESCRIPTOR_ADDR_EXT_SRC_ADDR_EXT_WIDTH		16
+#define XDPDMA_DESCRIPTOR_ADDR_EXT_SRC_ADDR_EXT_MASK		0XFFFF0000
+
+#define XDPDMA_DESCRIPTOR_ADDR_EXT23_2_SHIFT			0
+#define XDPDMA_DESCRIPTOR_ADDR_EXT23_2_WIDTH			16
+#define XDPDMA_DESCRIPTOR_ADDR_EXT23_2_MASK			0XFFFF
+
+#define XDPDMA_DESCRIPTOR_ADDR_EXT23_3_SHIFT			16
+#define XDPDMA_DESCRIPTOR_ADDR_EXT23_3_WIDTH			16
+#define XDPDMA_DESCRIPTOR_ADDR_EXT23_3_MASK			0xFFFF0000
+
+#define XDPDMA_DESCRIPTOR_ADDR_EXT45_4_SHIFT			0
+#define XDPDMA_DESCRIPTOR_ADDR_EXT45_4_WIDTH			16
+#define XDPDMA_DESCRIPTOR_ADDR_EXT45_4_MASK			0XFFFF
+
+#define XDPDMA_DESCRIPTOR_ADDR_EXT45_5_SHIFT			16
+#define XDPDMA_DESCRIPTOR_ADDR_EXT45_5_WIDTH			16
+#define XDPDMA_DESCRIPTOR_ADDR_EXT45_5_MASK			0XFFFF0000
+
+#define XDPDMA_DESCRIPTOR_NEXT_DESR_SHIFT			0
+#define XDPDMA_DESCRIPTOR_NEXT_DESR_WIDTH			32
+#define XDPDMA_DESCRIPTOR_NEXT_DESR_MASK			0XFFFFFFFF
+
+#define XDPDMA_DESCRIPTOR_SRC_ADDR_SHIFT			0
+#define XDPDMA_DESCRIPTOR_SRC_ADDR_WIDTH			32
+#define XDPDMA_DESCRIPTOR_SRC_ADDR_MASK				0XFFFFFFFF
+
+#define XDPDMA_DESCRIPTOR_SRC_ADDR2_SHIFT			0
+#define XDPDMA_DESCRIPTOR_SRC_ADDR2_WIDTH			32
+#define XDPDMA_DESCRIPTOR_SRC_ADDR2_MASK			0XFFFFFFFF
+
+#define XDPDMA_DESCRIPTOR_SRC_ADDR3_SHIFT			0
+#define XDPDMA_DESCRIPTOR_SRC_ADDR3_WIDTH			32
+#define XDPDMA_DESCRIPTOR_SRC_ADDR3_MASK			0XFFFFFFFF
+
+#define XDPDMA_DESCRIPTOR_SRC_ADDR4_SHIFT			0
+#define XDPDMA_DESCRIPTOR_SRC_ADDR4_WIDTH			32
+#define XDPDMA_DESCRIPTOR_SRC_ADDR4_MASK			0XFFFFFFFF
+
+#define XDPDMA_DESCRIPTOR_SRC_ADDR5_SHIFT			0
+#define XDPDMA_DESCRIPTOR_SRC_ADDR5_WIDTH			32
+#define XDPDMA_DESCRIPTOR_SRC_ADDR5_MASK			0XFFFFFFFF
+
+#define XDPDMA_TRIGGER_EN					1
+#define XDPDMA_RETRIGGER_EN					2
+#define XDPDMA_TRIGGER_DONE					0
+#define XDPDMA_RETRIGGER_DONE					0
+/* @} */
+
+/******************* Macros (Inline Functions Definitions ********************/
+
+/** @name Register access macro definitions.
+  * @{
+  */
+#define XDpDma_In32 Xil_In32
+#define XDpDma_Out32 Xil_Out32
+/* @} */
+
+/******************************************************************************/
+/**
+ * This is a low-level function that reads from the specified register.
+ *
+ * @param	BaseAddress is the base address of the device.
+ * @param	RegOffset is the register offset to be read from.
+ *
+ * @return	The 32-bit value of the specified register.
+ *
+ * @note	C-style signature:
+ *		u32 XDpDma_ReadReg(u32 BaseAddress, u32 RegOffset
+ *
+*******************************************************************************/
+#define XDpDma_ReadReg(BaseAddress, RegOffset) \
+					XDpDma_In32((BaseAddress) + (RegOffset))
+
+/******************************************************************************/
+/**
+ * This is a low-level function that writes to the specified register.
+ *
+ * @param	BaseAddress is the base address of the device.
+ * @param	RegOffset is the register offset to write to.
+ * @param	Data is the 32-bit data to write to the specified register.
+ *
+ * @return	None.
+ *
+ * @note	C-style signature:
+ *		void XDpDma_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
+ *
+*******************************************************************************/
+#define XDpDma_WriteReg(BaseAddress, RegOffset, Data) \
+				XDpDma_Out32((BaseAddress) + (RegOffset), (Data))
+
+
+/******************************************************************************/
+/**
+ * This is a low-level function that writes to the specified register.
+ *
+ * @param	BaseAddress is the base address of the device.
+ * @param	RegOffset is the register offset to write to.
+ * @param	Data is the 32-bit data to write to the specified register.
+ * @param	Mask is the 32-bit field to which data is to be written
+ *
+ * @return	None.
+ *
+ * @note	C-style signature:
+ *		void XDpDma_ReadModifyWrite(u32 BaseAddress,
+ *							u32 RegOffset, u32 Data)
+ *
+*******************************************************************************/
+#define XDpDma_ReadModifyWrite(BaseAddress, RegOffset, Data, Mask) \
+				XDpDma_WriteReg((BaseAddress), (RegOffset), \
+				((XDpDma_ReadReg(BaseAddress, RegOffset) &  \
+				 ~(Mask)) | Data))
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* _XDPDMAHW_H_ */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/dpdma_v1_0/src/xdpdma_intr.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/dpdma_v1_0/src/xdpdma_intr.c
new file mode 100644
index 000000000..80b175db6
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/dpdma_v1_0/src/xdpdma_intr.c
@@ -0,0 +1,166 @@
+/*******************************************************************************
+ *
+ * Copyright (C) 2017 Xilinx, Inc.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * Use of the Software is limited solely to applications:
+ * (a) running on a Xilinx device, or
+ * (b) that interact with a Xilinx device through a bus or interconnect.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+ * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Except as contained in this notice, the name of the Xilinx shall not be used
+ * in advertising or otherwise to promote the sale, use or other dealings in
+ * this Software without prior written authorization from Xilinx.
+ *
+*******************************************************************************/
+/******************************************************************************/
+/**
+ *
+ * @file xdppsu_intr.c
+ *
+ * This file contains functions related to XDpPsu interrupt handling.
+ *
+ * @note	None.
+ *
+ * 
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -----------------------------------------------
+ * 1.0   aad  01/17/17 Initial release.
+ * 

+ *
+*******************************************************************************/
+
+/******************************* Include Files ********************************/
+#include "xdpdma.h"
+
+
+/*************************************************************************/
+/**
+ *
+ * This function enables the interrupts that are required.
+ *
+ * @param    InstancePtr is pointer to the instance of DPDMA
+ *
+ * @return   None.
+ *
+ * @note     None.
+ *
+ * **************************************************************************/
+void XDpDma_InterruptEnable(XDpDma *InstancePtr, u32 Mask)
+{
+	XDpDma_WriteReg(InstancePtr->Config.BaseAddr, XDPDMA_IEN, Mask);
+}
+
+/*************************************************************************/
+/**
+ *
+ * This function handles the interrupts generated by DPDMA
+ *
+ * @param    InstancePtr is pointer to the instance of the DPDMA
+ *
+ * @return   None.
+ *
+ * @note     None.
+ *
+ * **************************************************************************/
+void XDpDma_InterruptHandler(XDpDma *InstancePtr)
+{
+	u32 RegVal;
+	RegVal = XDpDma_ReadReg(InstancePtr->Config.BaseAddr,
+				XDPDMA_ISR);
+	if(RegVal & XDPDMA_ISR_VSYNC_INT_MASK) {
+		XDpDma_VSyncHandler(InstancePtr);
+	}
+
+	if(RegVal & XDPDMA_ISR_DSCR_DONE4_MASK) {
+		XDpDma_SetChannelState(InstancePtr, AudioChan0, XDPDMA_DISABLE);
+		InstancePtr->Audio[0].Current = NULL;
+		XDpDma_WriteReg(InstancePtr->Config.BaseAddr, XDPDMA_ISR,
+				XDPDMA_ISR_DSCR_DONE4_MASK);
+	}
+
+	if(RegVal & XDPDMA_ISR_DSCR_DONE5_MASK) {
+		XDpDma_SetChannelState(InstancePtr, AudioChan1, XDPDMA_DISABLE);
+		InstancePtr->Audio[1].Current = NULL;
+		XDpDma_WriteReg(InstancePtr->Config.BaseAddr, XDPDMA_ISR,
+				XDPDMA_ISR_DSCR_DONE5_MASK);
+	}
+}
+
+/*************************************************************************/
+/**
+ *
+ * This function handles frame new frames on VSync
+ *
+ * @param    InstancePtr is pointer to the instance of the driver.
+ *
+ * @return   None.
+ *
+ * @note     None.
+ *
+ * **************************************************************************/
+void XDpDma_VSyncHandler(XDpDma *InstancePtr)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+
+	/* Video Channel Trigger/Retrigger Handler */
+	if(InstancePtr->Video.TriggerStatus == XDPDMA_TRIGGER_EN) {
+		XDpDma_SetupChannel(InstancePtr, VideoChan);
+		XDpDma_SetChannelState(InstancePtr, VideoChan,
+				       XDPDMA_ENABLE);
+		XDpDma_Trigger(InstancePtr, VideoChan);
+	}
+	else if(InstancePtr->Video.TriggerStatus == XDPDMA_RETRIGGER_EN) {
+		XDpDma_SetupChannel(InstancePtr, VideoChan);
+		XDpDma_ReTrigger(InstancePtr, VideoChan);
+	}
+
+	/* Graphics Channel Trigger/Retrigger Handler */
+	if(InstancePtr->Gfx.TriggerStatus == XDPDMA_TRIGGER_EN) {
+		XDpDma_SetupChannel(InstancePtr, GraphicsChan);
+		XDpDma_SetChannelState(InstancePtr, GraphicsChan,
+				       XDPDMA_ENABLE);
+		XDpDma_Trigger(InstancePtr, GraphicsChan);
+	}
+	else if(InstancePtr->Gfx.TriggerStatus == XDPDMA_RETRIGGER_EN) {
+		XDpDma_SetupChannel(InstancePtr, GraphicsChan);
+		XDpDma_ReTrigger(InstancePtr, GraphicsChan);
+	}
+
+	/* Audio Channel 0 Trigger Handler */
+	if(InstancePtr->Audio[0].TriggerStatus == XDPDMA_TRIGGER_EN) {
+		XDpDma_SetupChannel(InstancePtr, AudioChan0);
+		XDpDma_SetChannelState(InstancePtr, AudioChan0,
+				       XDPDMA_ENABLE);
+		XDpDma_Trigger(InstancePtr, AudioChan0);
+	}
+
+	/* Audio Channel 1 Trigger Handler */
+	if(InstancePtr->Audio[1].TriggerStatus == XDPDMA_TRIGGER_EN) {
+		XDpDma_SetupChannel(InstancePtr, AudioChan1);
+		XDpDma_SetChannelState(InstancePtr, AudioChan1,
+				       XDPDMA_ENABLE);
+		XDpDma_Trigger(InstancePtr, AudioChan1);
+	}
+	/* Clear VSync Interrupt */
+	XDpDma_WriteReg(InstancePtr->Config.BaseAddr, XDPDMA_ISR,
+			XDPDMA_ISR_VSYNC_INT_MASK);
+}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/dpdma_v1_0/src/xdpdma_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/dpdma_v1_0/src/xdpdma_sinit.c
new file mode 100644
index 000000000..8f062681b
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/dpdma_v1_0/src/xdpdma_sinit.c
@@ -0,0 +1,96 @@
+/*******************************************************************************
+ *
+ * Copyright (C) 2017 Xilinx, Inc.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * Use of the Software is limited solely to applications:
+ * (a) running on a Xilinx device, or
+ * (b) that interact with a Xilinx device through a bus or interconnect.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+ * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Except as contained in this notice, the name of the Xilinx shall not be used
+ * in advertising or otherwise to promote the sale, use or other dealings in
+ * this Software without prior written authorization from Xilinx.
+ *
+*******************************************************************************/
+/******************************************************************************/
+/**
+ *
+ * @file xdpdma_sinit.c
+ * @addtogroup dpdma_v1_0
+ * @{
+ *
+ * This file contains static initialization methods for the XDpDma driver.
+ *
+ * @note	None.
+ *
+ * 
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -----------------------------------------------
+ * 1.0   aad  01/20/15 Initial release.
+ * 

+ *
+*******************************************************************************/
+
+/******************************* Include Files ********************************/
+
+#include "xdpdma.h"
+#include "xparameters.h"
+
+/*************************** Variable Declarations ****************************/
+
+/**
+ * A table of configuration structures containing the configuration information
+ * for each DisplayPort TX core in the system.
+ */
+extern XDpDma_Config XDpDma_ConfigTable[XPAR_XDPDMA_NUM_INSTANCES];
+
+/**************************** Function Definitions ****************************/
+
+/******************************************************************************/
+/**
+ * This function looks for the device configuration based on the unique device
+ * ID. The table XDpDma_ConfigTable[] contains the configuration information for
+ * each device in the system.
+ *
+ * @param	DeviceId is the unique device ID of the device being looked up.
+ *
+ * @return	A pointer to the configuration table entry corresponding to the
+ *		given device ID, or NULL if no match is found.
+ *
+ * @note	None.
+ *
+*******************************************************************************/
+XDpDma_Config *XDpDma_LookupConfig(u16 DeviceId)
+{
+	XDpDma_Config *CfgPtr;
+	u32 Index;
+
+	for (Index = 0; Index < XPAR_XDPDMA_NUM_INSTANCES; Index++) {
+		if (XDpDma_ConfigTable[Index].DeviceId == DeviceId) {
+			CfgPtr = &XDpDma_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return CfgPtr;
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_7/src/Makefile
similarity index 100%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/Makefile
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_7/src/Makefile
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_7/src/xemacps.c
similarity index 98%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps.c
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_7/src/xemacps.c
index 26df03c3d..c013c4946 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_7/src/xemacps.c
@@ -33,7 +33,7 @@
 /**
 *
 * @file xemacps.c
-* @addtogroup emacps_v3_1
+* @addtogroup emacps_v3_7
 * @{
 *
 * The XEmacPs driver. Functions in this file are the minimum required functions
@@ -52,6 +52,8 @@
 *                    Disable extended mode. Perform all 64 bit changes under
 *                    check for arch64.
 * 3.1  hk   08/10/15 Update upper 32 bit tx and rx queue ptr registers
+* 3.5  hk   08/14/17 Update cache coherency information of the interface in
+*                    its config structure.
 *
 * 

 ******************************************************************************/
@@ -107,6 +109,7 @@ LONG XEmacPs_CfgInitialize(XEmacPs *InstancePtr, XEmacPs_Config * CfgPtr,
 	/* Set device base address and ID */
 	InstancePtr->Config.DeviceId = CfgPtr->DeviceId;
 	InstancePtr->Config.BaseAddress = EffectiveAddress;
+	InstancePtr->Config.IsCacheCoherent = CfgPtr->IsCacheCoherent;
 
 	/* Set callbacks to an initial stub routine */
 	InstancePtr->SendHandler = ((XEmacPs_Handler)((void*)XEmacPs_StubHandler));
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_7/src/xemacps.h
similarity index 97%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps.h
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_7/src/xemacps.h
index f12092bec..6d4b15b24 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_7/src/xemacps.h
@@ -33,7 +33,7 @@
 /**
  *
  * @file xemacps.h
-* @addtogroup emacps_v3_1
+* @addtogroup emacps_v3_7
 * @{
 * @details
  *
@@ -316,6 +316,21 @@
  *                     there is no error. CR# 869403
  *            08/10/15 Update upper 32 bit tx and rx queue ptr registers.
  * 3.2   hk   02/22/16 Added SGMII support for Zynq Ultrascale+ MPSoC.
+ * 3.4   ms   01/23/17 Modified xil_printf statement in main function for all
+ *                     examples to ensure that "Successfully ran" and "Failed"
+ *                     strings are available in all examples. This is a fix
+ *                     for CR-965028.
+ *       ms   03/17/17 Modified text file in examples folder for doxygen
+ *                     generation.
+ *       ms   04/05/17 Added tabspace for return statements in functions of
+ *                     xemacps_ieee1588_example.c for proper documentation
+ *                     while generating doxygen.
+ * 3.5   hk   08/14/17 Update cache coherency information of the interface in
+ *                     its config structure.
+ * 3.6   rb   09/08/17 HwCnt variable (in XEmacPs_BdRing structure) is
+ *		       changed to volatile.
+ *		       Add API XEmacPs_BdRingPtrReset() to reset pointers
+ *
  * 

  *
  ****************************************************************************/
@@ -513,6 +528,8 @@ typedef void (*XEmacPs_ErrHandler) (void *CallBackRef, u8 Direction,
 typedef struct {
 	u16 DeviceId;	/**< Unique ID  of device */
 	UINTPTR BaseAddress;/**< Physical base address of IPIF registers */
+	u8 IsCacheCoherent; /**< Applicable only to A53 in EL1 mode;
+				* describes whether Cache Coherent or not */
 } XEmacPs_Config;
 
 
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_bd.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_7/src/xemacps_bd.h
similarity index 99%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_bd.h
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_7/src/xemacps_bd.h
index 52c5f7e7e..83f9a87fc 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_bd.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_7/src/xemacps_bd.h
@@ -33,7 +33,7 @@
 /**
  *
  * @file xemacps_bd.h
-* @addtogroup emacps_v3_1
+* @addtogroup emacps_v3_7
 * @{
  *
  * This header provides operations to manage buffer descriptors in support
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v3_2/src/xemacps_bdring.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_7/src/xemacps_bdring.c
similarity index 97%
rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v3_2/src/xemacps_bdring.c
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_7/src/xemacps_bdring.c
index d837e1df1..3536873dc 100644
--- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v3_2/src/xemacps_bdring.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_7/src/xemacps_bdring.c
@@ -33,7 +33,7 @@
 /**
 *
 * @file xemacps_bdring.c
-* @addtogroup emacps_v3_1
+* @addtogroup emacps_v3_7
 * @{
 *
 * This file implements buffer descriptor ring related functions.
@@ -57,6 +57,8 @@
 *		      from uncached area. Fix for CR #663885.
 * 2.1   srt  07/15/14 Add support for Zynq Ultrascale Mp architecture.
 * 3.0   kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.6   rb   09/08/17 Add XEmacPs_BdRingPtrReset() API to reset BD ring
+* 		      pointers
 *
 *
******************************************************************************/ @@ -505,7 +507,7 @@ LONG XEmacPs_BdRingUnAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd, XEmacPs_Bd * BdSetPtr) { LONG Status; - (void *)BdSetPtr; + (void) BdSetPtr; Xil_AssertNonvoid(RingPtr != NULL); Xil_AssertNonvoid(BdSetPtr != NULL); @@ -1072,4 +1074,29 @@ static void XEmacPs_BdSetTxWrap(UINTPTR BdPtr) *TempPtr = DataValueTx; } } + +/*****************************************************************************/ +/** + * Reset BD ring head and tail pointers. + * + * @param RingPtr is the instance to be worked on. + * @param VirtAddr is the virtual base address of the user memory region. + * + * @note + * Should be called after XEmacPs_Stop() + * + * @note + * C-style signature: + * void XEmacPs_BdRingPtrReset(XEmacPs_BdRing * RingPtr, void *virtaddrloc) + * + *****************************************************************************/ +void XEmacPs_BdRingPtrReset(XEmacPs_BdRing * RingPtr, void *virtaddrloc) +{ + RingPtr->FreeHead = virtaddrloc; + RingPtr->PreHead = virtaddrloc; + RingPtr->HwHead = virtaddrloc; + RingPtr->HwTail = virtaddrloc; + RingPtr->PostHead = virtaddrloc; +} + /** @} */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_3/src/xemacps_bdring.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_7/src/xemacps_bdring.h similarity index 97% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_3/src/xemacps_bdring.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_7/src/xemacps_bdring.h index de78cf28f..b89e89885 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_3/src/xemacps_bdring.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_7/src/xemacps_bdring.h @@ -33,7 +33,7 @@ /** * * @file xemacps_bdring.h -* @addtogroup emacps_v3_1 +* @addtogroup emacps_v3_7 * @{ * * The Xiline EmacPs Buffer Descriptor ring driver. This is part of EmacPs @@ -47,6 +47,8 @@ * 1.00a wsy 01/10/10 First release * 2.1 srt 07/15/14 Add support for Zynq Ultrascale Mp architecture. * 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance. +* 3.6 rb 09/08/17 HwCnt variable (in XEmacPs_BdRing structure) is +* changed to volatile. * * * @@ -81,7 +83,7 @@ typedef struct { XEmacPs_Bd *BdaRestart; /**< BDA to load when channel is started */ - u32 HwCnt; /**< Number of BDs in work group */ + volatile u32 HwCnt; /**< Number of BDs in work group */ u32 PreCnt; /**< Number of BDs in pre-work group */ u32 FreeCnt; /**< Number of allocatable BDs in the free group */ u32 PostCnt; /**< Number of BDs in post-work group */ @@ -228,6 +230,7 @@ u32 XEmacPs_BdRingFromHwRx(XEmacPs_BdRing * RingPtr, u32 BdLimit, XEmacPs_Bd ** BdSetPtr); LONG XEmacPs_BdRingCheck(XEmacPs_BdRing * RingPtr, u8 Direction); +void XEmacPs_BdRingPtrReset(XEmacPs_BdRing * RingPtr, void *virtaddrloc); #ifdef __cplusplus } diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_3/src/xemacps_control.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_7/src/xemacps_control.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_3/src/xemacps_control.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_7/src/xemacps_control.c index f52451a8c..8217a4521 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_3/src/xemacps_control.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_7/src/xemacps_control.c @@ -33,7 +33,7 @@ /** * * @file xemacps_control.c -* @addtogroup emacps_v3_1 +* @addtogroup emacps_v3_7 * @{ * * Functions in this file implement general purpose command and control related diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_7/src/xemacps_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_7/src/xemacps_g.c new file mode 100644 index 000000000..e58610f57 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_7/src/xemacps_g.c @@ -0,0 +1,56 @@ + +/******************************************************************* +* +* CAUTION: This file is automatically generated by HSI. +* Version: +* DO NOT EDIT. +* +* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.* +*Permission is hereby granted, free of charge, to any person obtaining a copy +*of this software and associated documentation files (the Software), to deal +*in the Software without restriction, including without limitation the rights +*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +*copies of the Software, and to permit persons to whom the Software is +*furnished to do so, subject to the following conditions: +* +*The above copyright notice and this permission notice shall be included in +*all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +*(a) running on a Xilinx device, or +*(b) that interact with a Xilinx device through a bus or interconnect. +* +*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +* +*Except as contained in this notice, the name of the Xilinx shall not be used +*in advertising or otherwise to promote the sale, use or other dealings in +*this Software without prior written authorization from Xilinx. +* + +* +* Description: Driver configuration +* +*******************************************************************/ + +#include "xparameters.h" +#include "xemacps.h" + +/* +* The configuration table for devices +*/ + +XEmacPs_Config XEmacPs_ConfigTable[XPAR_XEMACPS_NUM_INSTANCES] = +{ + { + XPAR_PSU_ETHERNET_3_DEVICE_ID, + XPAR_PSU_ETHERNET_3_BASEADDR, + XPAR_PSU_ETHERNET_3_IS_CACHE_COHERENT + } +}; + + diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_hw.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_7/src/xemacps_hw.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_hw.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_7/src/xemacps_hw.c index daba38397..00e79a58d 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_hw.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_7/src/xemacps_hw.c @@ -33,7 +33,7 @@ /** * * @file xemacps_hw.c -* @addtogroup emacps_v3_1 +* @addtogroup emacps_v3_7 * @{ * * This file contains the implementation of the ethernet interface reset sequence diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v3_2/src/xemacps_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_7/src/xemacps_hw.h similarity index 99% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v3_2/src/xemacps_hw.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_7/src/xemacps_hw.h index 953cc6265..e535470c2 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/emacps_v3_2/src/xemacps_hw.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_7/src/xemacps_hw.h @@ -33,7 +33,7 @@ /** * * @file xemacps_hw.h -* @addtogroup emacps_v3_1 +* @addtogroup emacps_v3_7 * @{ * * This header file contains identifiers and low-level driver functions (or diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_intr.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_7/src/xemacps_intr.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_intr.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_7/src/xemacps_intr.c index 59636c4ef..9c355a163 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_3/src/xemacps_intr.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_7/src/xemacps_intr.c @@ -33,7 +33,7 @@ /** * * @file xemacps_intr.c -* @addtogroup emacps_v3_1 +* @addtogroup emacps_v3_7 * @{ * * Functions in this file implement general purpose interrupt processing related diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_3/src/xemacps_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_7/src/xemacps_sinit.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_3/src/xemacps_sinit.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_7/src/xemacps_sinit.c index 1bc5b3b19..e2d2078af 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/emacps_v3_3/src/xemacps_sinit.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_7/src/xemacps_sinit.c @@ -33,7 +33,7 @@ /** * * @file xemacps_sinit.c -* @addtogroup emacps_v3_1 +* @addtogroup emacps_v3_7 * @{ * * This file contains lookup method by device ID when success, it returns diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_3/src/Makefile similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/Makefile rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_3/src/Makefile diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_1/src/xgpiops.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_3/src/xgpiops.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_1/src/xgpiops.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_3/src/xgpiops.c index 90eedb87d..7b6fe2e46 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_1/src/xgpiops.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_3/src/xgpiops.c @@ -33,7 +33,7 @@ /** * * @file xgpiops.c -* @addtogroup gpiops_v3_1 +* @addtogroup gpiops_v3_3 * @{ * * The XGpioPs driver. Functions in this file are the minimum required functions diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_1/src/xgpiops.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_3/src/xgpiops.h similarity index 94% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_1/src/xgpiops.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_3/src/xgpiops.h index 102615572..fda562d91 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_1/src/xgpiops.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_3/src/xgpiops.h @@ -1,3 +1,4 @@ + /****************************************************************************** * * Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. @@ -33,7 +34,7 @@ /** * * @file xgpiops.h -* @addtogroup gpiops_v3_1 +* @addtogroup gpiops_v3_3 * @{ * @details * @@ -97,7 +98,15 @@ * passed to APIs. CR# 822636 * 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance. * 3.1 kvn 04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980. -* +* ms 03/17/17 Added readme.txt file in examples folder for doxygen +* generation. +* ms 04/05/17 Added tabspace for return statements in functions of +* gpiops examples for proper documentation while +* generating doxygen. +* 3.3 ms 04/17/17 Added notes about gpio input and output pin description +* for zcu102 and zc702 boards in polled and interrupt +* example, configured Interrupt pin to input pin for +* proper functioning of interrupt example. * * ******************************************************************************/ diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_3/src/xgpiops_g.c similarity index 90% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops_g.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_3/src/xgpiops_g.c index 38a5b9355..a518a700e 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops_g.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_3/src/xgpiops_g.c @@ -5,7 +5,7 @@ * Version: * DO NOT EDIT. * -* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.* +* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.* *Permission is hereby granted, free of charge, to any person obtaining a copy *of this software and associated documentation files (the Software), to deal *in the Software without restriction, including without limitation the rights @@ -44,7 +44,7 @@ * The configuration table for devices */ -XGpioPs_Config XGpioPs_ConfigTable[] = +XGpioPs_Config XGpioPs_ConfigTable[XPAR_XGPIOPS_NUM_INSTANCES] = { { XPAR_PSU_GPIO_0_DEVICE_ID, diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_1/src/xgpiops_hw.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_3/src/xgpiops_hw.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_1/src/xgpiops_hw.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_3/src/xgpiops_hw.c index d7a5e00f0..8961c4287 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_1/src/xgpiops_hw.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_3/src/xgpiops_hw.c @@ -33,7 +33,7 @@ /** * * @file xgpiops_hw.c -* @addtogroup gpiops_v3_1 +* @addtogroup gpiops_v3_3 * @{ * * This file contains low level GPIO functions. diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_1/src/xgpiops_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_3/src/xgpiops_hw.h similarity index 99% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_1/src/xgpiops_hw.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_3/src/xgpiops_hw.h index 81e8d6a9f..ff0190675 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_1/src/xgpiops_hw.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_3/src/xgpiops_hw.h @@ -33,7 +33,7 @@ /** * * @file xgpiops_hw.h -* @addtogroup gpiops_v3_1 +* @addtogroup gpiops_v3_3 * @{ * * This header file contains the identifiers and basic driver functions (or diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops_intr.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_3/src/xgpiops_intr.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops_intr.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_3/src/xgpiops_intr.c index c07381be6..a8b0a5626 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops_intr.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_3/src/xgpiops_intr.c @@ -33,7 +33,7 @@ /** * * @file xgpiops_intr.c -* @addtogroup gpiops_v3_1 +* @addtogroup gpiops_v3_3 * @{ * * This file contains functions related to GPIO interrupt handling. @@ -722,7 +722,7 @@ void XGpioPs_IntrHandler(XGpioPs *InstancePtr) ******************************************************************************/ void StubHandler(void *CallBackRef, u32 Bank, u32 Status) { - (void*) CallBackRef; + (void) CallBackRef; (void) Bank; (void) Status; diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_1/src/xgpiops_selftest.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_3/src/xgpiops_selftest.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_1/src/xgpiops_selftest.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_3/src/xgpiops_selftest.c index da1973a2d..378524c14 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/gpiops_v3_1/src/xgpiops_selftest.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_3/src/xgpiops_selftest.c @@ -33,7 +33,7 @@ /** * * @file xgpiops_selftest.c -* @addtogroup gpiops_v3_1 +* @addtogroup gpiops_v3_3 * @{ * * This file contains a diagnostic self-test function for the XGpioPs driver. diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_1/src/xgpiops_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_3/src/xgpiops_sinit.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_1/src/xgpiops_sinit.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_3/src/xgpiops_sinit.c index 2ca008373..4cc0c390f 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_1/src/xgpiops_sinit.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_3/src/xgpiops_sinit.c @@ -33,7 +33,7 @@ /** * * @file xgpiops_sinit.c -* @addtogroup gpiops_v3_1 +* @addtogroup gpiops_v3_3 * @{ * * This file contains the implementation of the XGpioPs driver's static diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_6/src/Makefile similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/Makefile rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_6/src/Makefile diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v3_1/src/xiicps.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_6/src/xiicps.c similarity index 97% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v3_1/src/xiicps.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_6/src/xiicps.c index 812c2ecdc..4f2b592e7 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v3_1/src/xiicps.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_6/src/xiicps.c @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* Copyright (C) 2010 - 2016 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -33,7 +33,7 @@ /** * * @file xiicps.c -* @addtogroup iicps_v3_0 +* @addtogroup iicps_v3_5 * @{ * * Contains implementation of required functions for the XIicPs driver. @@ -54,6 +54,7 @@ * in XIicPs_Reset. * 12/06/14 Implemented Repeated start feature. * 01/31/15 Modified the code according to MISRAC 2012 Compliant. +* 3.3 kvn 05/05/16 Modified latest code for MISRA-C:2012 Compliance. * * * @@ -228,7 +229,7 @@ void XIicPs_Abort(XIicPs *InstancePtr) * Reset the settings in config register and clear the FIFOs. */ XIicPs_WriteReg(InstancePtr->Config.BaseAddress, XIICPS_CR_OFFSET, - XIICPS_CR_RESET_VALUE | XIICPS_CR_CLR_FIFO_MASK); + (u32)XIICPS_CR_RESET_VALUE | (u32)XIICPS_CR_CLR_FIFO_MASK); /* * Read, then write the interrupt status to make sure there are no @@ -242,7 +243,7 @@ void XIicPs_Abort(XIicPs *InstancePtr) /* * Restore the interrupt state. */ - IntrMaskReg = XIICPS_IXR_ALL_INTR_MASK & (~IntrMaskReg); + IntrMaskReg = (u32)XIICPS_IXR_ALL_INTR_MASK & (~IntrMaskReg); XIicPs_WriteReg(InstancePtr->Config.BaseAddress, XIICPS_IER_OFFSET, IntrMaskReg); diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v3_1/src/xiicps.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_6/src/xiicps.h similarity index 98% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v3_1/src/xiicps.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_6/src/xiicps.h index 73ad5dc64..cc837a14c 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v3_1/src/xiicps.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_6/src/xiicps.h @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* Copyright (C) 2010 - 2016 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -33,7 +33,7 @@ /** * * @file xiicps.h -* @addtogroup iicps_v3_0 +* @addtogroup iicps_v3_5 * @{ * @details * @@ -183,6 +183,9 @@ * 01/31/15 Modified the code according to MISRAC 2012 Compliant. * 02/18/15 Implemented larger data transfer using repeated start * in Zynq UltraScale MP. +* 3.3 kvn 05/05/16 Modified latest code for MISRA-C:2012 Compliance. +* ms 03/17/17 Added readme.txt file in examples folder for doxygen +* generation. * * * diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_6/src/xiicps_g.c similarity index 91% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_g.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_6/src/xiicps_g.c index f449e0ed6..1a469d08c 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_4/src/xiicps_g.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_6/src/xiicps_g.c @@ -5,7 +5,7 @@ * Version: * DO NOT EDIT. * -* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.* +* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.* *Permission is hereby granted, free of charge, to any person obtaining a copy *of this software and associated documentation files (the Software), to deal *in the Software without restriction, including without limitation the rights @@ -44,7 +44,7 @@ * The configuration table for devices */ -XIicPs_Config XIicPs_ConfigTable[] = +XIicPs_Config XIicPs_ConfigTable[XPAR_XIICPS_NUM_INSTANCES] = { { XPAR_PSU_I2C_0_DEVICE_ID, diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v3_1/src/xiicps_hw.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_6/src/xiicps_hw.c similarity index 98% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v3_1/src/xiicps_hw.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_6/src/xiicps_hw.c index 8b7a58fc6..2d85e1436 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v3_1/src/xiicps_hw.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_6/src/xiicps_hw.c @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2013 - 2015 Xilinx, Inc. All rights reserved. +* Copyright (C) 2013 - 2016 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -33,7 +33,7 @@ /** * * @file xiicps_hw.c -* @addtogroup iicps_v3_0 +* @addtogroup iicps_v3_5 * @{ * * Contains implementation of required functions for providing the reset sequence diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v3_1/src/xiicps_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_6/src/xiicps_hw.h similarity index 99% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v3_1/src/xiicps_hw.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_6/src/xiicps_hw.h index cec349928..d1eee82f2 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v3_1/src/xiicps_hw.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_6/src/xiicps_hw.h @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* Copyright (C) 2010 - 2016 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -33,7 +33,7 @@ /** * * @file xiicps_hw.h -* @addtogroup iicps_v3_0 +* @addtogroup iicps_v3_5 * @{ * * This header file contains the hardware definition for an IIC device. diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v3_1/src/xiicps_intr.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_6/src/xiicps_intr.c similarity index 97% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v3_1/src/xiicps_intr.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_6/src/xiicps_intr.c index de05b93b6..7f385918f 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v3_1/src/xiicps_intr.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_6/src/xiicps_intr.c @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* Copyright (C) 2010 - 2016 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -33,7 +33,7 @@ /** * * @file xiicps_intr.c -* @addtogroup iicps_v3_0 +* @addtogroup iicps_v3_5 * @{ * * Contains functions of the XIicPs driver for interrupt-driven transfers. diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v3_1/src/xiicps_master.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_6/src/xiicps_master.c similarity index 94% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v3_1/src/xiicps_master.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_6/src/xiicps_master.c index d49feecdf..faa852826 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v3_1/src/xiicps_master.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_6/src/xiicps_master.c @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* Copyright (C) 2010 - 2016 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -33,7 +33,7 @@ /** * * @file xiicps_master.c -* @addtogroup iicps_v3_0 +* @addtogroup iicps_v3_5 * @{ * * Handles master mode transfers. @@ -62,7 +62,9 @@ * 01/31/15 Modified the code according to MISRAC 2012 Compliant. * 02/18/15 Implemented larger data transfer using repeated start * in Zynq UltraScale MP. -* +* 3.3 kvn 05/05/16 Modified latest code for MISRA-C:2012 Compliance. +* 3.6 ask 09/03/18 In XIicPs_MasterRecvPolled, set transfer size register +* before slave address. Fix for CR996440. * * ******************************************************************************/ @@ -106,6 +108,7 @@ void XIicPs_MasterSend(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount, u16 SlaveAddr) { u32 BaseAddr; + u32 Platform = XGetPlatform_Info(); /* * Assert validates the input arguments. @@ -147,6 +150,16 @@ void XIicPs_MasterSend(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount, */ XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, (u32)SlaveAddr); + /* Clear the Hold bit in ZYNQ if receive byte count is less than + * the FIFO depth to get the completion interrupt properly. + */ + if ((ByteCount < XIICPS_FIFO_DEPTH) && (Platform == (u32)XPLAT_ZYNQ)) + { + XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET, + XIicPs_ReadReg(BaseAddr, (u32)XIICPS_CR_OFFSET) & + (u32)(~XIICPS_CR_HOLD_MASK)); + } + } /*****************************************************************************/ @@ -182,10 +195,8 @@ void XIicPs_MasterRecv(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount, BaseAddr = InstancePtr->Config.BaseAddress; InstancePtr->RecvBufferPtr = MsgPtr; InstancePtr->RecvByteCount = ByteCount; - InstancePtr->CurrByteCount = ByteCount; InstancePtr->SendBufferPtr = NULL; InstancePtr->IsSend = 0; - InstancePtr->UpdateTxSize = 0; if ((ByteCount > XIICPS_FIFO_DEPTH) || ((InstancePtr->IsRepeatedStart) !=0)) @@ -203,14 +214,16 @@ void XIicPs_MasterRecv(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount, * Setup the transfer size register so the slave knows how much * to send to us. */ - if (ByteCount > XIICPS_MAX_TRANSFER_SIZE) { + if (ByteCount > (s32)XIICPS_MAX_TRANSFER_SIZE) { XIicPs_WriteReg(BaseAddr, XIICPS_TRANS_SIZE_OFFSET, XIICPS_MAX_TRANSFER_SIZE); InstancePtr->CurrByteCount = (s32)XIICPS_MAX_TRANSFER_SIZE; InstancePtr->UpdateTxSize = 1; }else { + InstancePtr->CurrByteCount = ByteCount; XIicPs_WriteReg(BaseAddr, (u32)(XIICPS_TRANS_SIZE_OFFSET), (u32)ByteCount); + InstancePtr->UpdateTxSize = 0; } XIicPs_EnableInterrupts(BaseAddr, @@ -251,8 +264,7 @@ s32 XIicPs_MasterSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, u32 StatusReg; u32 BaseAddr; u32 Intrs; - u32 Value; - s32 Status; + _Bool Value; /* * Assert validates the input arguments. @@ -260,7 +272,7 @@ s32 XIicPs_MasterSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(MsgPtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY); - Xil_AssertNonvoid(XIICPS_ADDR_MASK >= SlaveAddr); + Xil_AssertNonvoid((u16)XIICPS_ADDR_MASK >= SlaveAddr); BaseAddr = InstancePtr->Config.BaseAddress; InstancePtr->SendBufferPtr = MsgPtr; @@ -302,7 +314,7 @@ s32 XIicPs_MasterSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, */ Value = ((InstancePtr->SendByteCount > (s32)0) && ((IntrStatusReg & Intrs) == (u32)0U)); - while (Value != (u32)0x00U) { + while (Value != FALSE) { StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET); /* @@ -374,14 +386,8 @@ s32 XIicPs_MasterRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr, u32 Intrs; u32 StatusReg; u32 BaseAddr; - s32 BytesToRecv; - s32 BytesToRead; - s32 TransSize; - s32 Tmp = 0; - u32 Status_Rcv; - u32 Status; s32 Result; - s32 IsHold = 0; + s32 IsHold; s32 UpdateTxSize = 0; s32 ByteCountVar = ByteCount; u32 Platform; @@ -407,6 +413,8 @@ s32 XIicPs_MasterRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr, XIicPs_ReadReg(BaseAddr, (u32)XIICPS_CR_OFFSET) | (u32)XIICPS_CR_HOLD_MASK); IsHold = 1; + } else { + IsHold = 0; } (void)XIicPs_SetupMaster(InstancePtr, RECVING_ROLE); @@ -417,13 +425,12 @@ s32 XIicPs_MasterRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr, IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET); XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg); - XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, SlaveAddr); /* * Set up the transfer size register so the slave knows how much * to send to us. */ - if (ByteCountVar > XIICPS_MAX_TRANSFER_SIZE) { + if (ByteCountVar > (s32)XIICPS_MAX_TRANSFER_SIZE) { XIicPs_WriteReg(BaseAddr, XIICPS_TRANS_SIZE_OFFSET, XIICPS_MAX_TRANSFER_SIZE); ByteCountVar = (s32)XIICPS_MAX_TRANSFER_SIZE; @@ -433,6 +440,9 @@ s32 XIicPs_MasterRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr, ByteCountVar); } + + XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, SlaveAddr); + /* * Intrs keeps all the error-related interrupts. */ @@ -460,18 +470,18 @@ s32 XIicPs_MasterRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr, XIicPs_RecvByte(InstancePtr); ByteCountVar --; - if (Platform == XPLAT_ZYNQ) { + if (Platform == (u32)XPLAT_ZYNQ) { if ((UpdateTxSize != 0) && - ((ByteCountVar == (XIICPS_FIFO_DEPTH + 1)) != 0U)) { + (ByteCountVar == (XIICPS_FIFO_DEPTH + 1))) { break; } } StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET); } - if (Platform == XPLAT_ZYNQ) { + if (Platform == (u32)XPLAT_ZYNQ) { if ((UpdateTxSize != 0) && - ((ByteCountVar == (XIICPS_FIFO_DEPTH + 1)) != 0U)) { + (ByteCountVar == (XIICPS_FIFO_DEPTH + 1))) { /* wait while fifo is full */ while (XIicPs_ReadReg(BaseAddr, XIICPS_TRANS_SIZE_OFFSET) != @@ -479,7 +489,7 @@ s32 XIicPs_MasterRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr, } if ((InstancePtr->RecvByteCount - XIICPS_FIFO_DEPTH) > - XIICPS_MAX_TRANSFER_SIZE) { + (s32)XIICPS_MAX_TRANSFER_SIZE) { XIicPs_WriteReg(BaseAddr, XIICPS_TRANS_SIZE_OFFSET, @@ -507,7 +517,7 @@ s32 XIicPs_MasterRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr, XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, SlaveAddr); if ((InstancePtr->RecvByteCount) > - XIICPS_MAX_TRANSFER_SIZE) { + (s32)XIICPS_MAX_TRANSFER_SIZE) { XIicPs_WriteReg(BaseAddr, XIICPS_TRANS_SIZE_OFFSET, @@ -625,6 +635,11 @@ void XIicPs_DisableSlaveMonitor(XIicPs *InstancePtr) XIicPs_ReadReg(BaseAddr, XIICPS_CR_OFFSET) & (~XIICPS_CR_SLVMON_MASK)); + /* + * wait for slv monitor control bit to be clear + */ + while (XIicPs_ReadReg(BaseAddr, XIICPS_CR_OFFSET) + & XIICPS_CR_SLVMON_MASK); /* * Clear interrupt flag for slave monitor interrupt. */ @@ -755,17 +770,17 @@ void XIicPs_MasterInterruptHandler(XIicPs *InstancePtr) XIicPs_RecvByte(InstancePtr); ByteCnt--; - if (Platform == XPLAT_ZYNQ) { + if (Platform == (u32)XPLAT_ZYNQ) { if ((InstancePtr->UpdateTxSize != 0) && - ((ByteCnt == (XIICPS_FIFO_DEPTH + 1)) != 0U)) { + (ByteCnt == (XIICPS_FIFO_DEPTH + 1))) { break; } } } - if (Platform == XPLAT_ZYNQ) { + if (Platform == (u32)XPLAT_ZYNQ) { if ((InstancePtr->UpdateTxSize != 0) && - ((ByteCnt == (XIICPS_FIFO_DEPTH + 1))!= 0U)) { + (ByteCnt == (XIICPS_FIFO_DEPTH + 1))) { /* wait while fifo is full */ while (XIicPs_ReadReg(BaseAddr, XIICPS_TRANS_SIZE_OFFSET) != @@ -773,7 +788,7 @@ void XIicPs_MasterInterruptHandler(XIicPs *InstancePtr) } if ((InstancePtr->RecvByteCount - XIICPS_FIFO_DEPTH) > - XIICPS_MAX_TRANSFER_SIZE) { + (s32)XIICPS_MAX_TRANSFER_SIZE) { XIicPs_WriteReg(BaseAddr, XIICPS_TRANS_SIZE_OFFSET, @@ -798,11 +813,11 @@ void XIicPs_MasterInterruptHandler(XIicPs *InstancePtr) IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET); XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg); - SlaveAddr = XIicPs_ReadReg(BaseAddr, (u32)XIICPS_ADDR_OFFSET); + SlaveAddr = (u16)XIicPs_ReadReg(BaseAddr, (u32)XIICPS_ADDR_OFFSET); XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, SlaveAddr); if ((InstancePtr->RecvByteCount) > - XIICPS_MAX_TRANSFER_SIZE) { + (s32)XIICPS_MAX_TRANSFER_SIZE) { XIicPs_WriteReg(BaseAddr, XIICPS_TRANS_SIZE_OFFSET, @@ -910,7 +925,6 @@ static s32 XIicPs_SetupMaster(XIicPs *InstancePtr, s32 Role) { u32 ControlReg; u32 BaseAddr; - u32 EnabledIntr = 0x0U; Xil_AssertNonvoid(InstancePtr != NULL); @@ -935,11 +949,9 @@ static s32 XIicPs_SetupMaster(XIicPs *InstancePtr, s32 Role) if (Role == RECVING_ROLE) { ControlReg |= (u32)XIICPS_CR_RD_WR_MASK; - EnabledIntr = (u32)XIICPS_IXR_DATA_MASK |(u32)XIICPS_IXR_RX_OVR_MASK; }else { ControlReg &= (u32)(~XIICPS_CR_RD_WR_MASK); } - EnabledIntr |= (u32)XIICPS_IXR_COMP_MASK | (u32)XIICPS_IXR_ARB_LOST_MASK; XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET, ControlReg); diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v3_1/src/xiicps_options.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_6/src/xiicps_options.c similarity index 97% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v3_1/src/xiicps_options.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_6/src/xiicps_options.c index 5d7427a48..c9237dbb0 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v3_1/src/xiicps_options.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_6/src/xiicps_options.c @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* Copyright (C) 2010 - 2016 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -33,7 +33,7 @@ /** * * @file xiicps_options.c -* @addtogroup iicps_v3_0 +* @addtogroup iicps_v3_5 * @{ * * Contains functions for the configuration of the XIccPs driver. @@ -55,6 +55,7 @@ * 2.3 sk 10/07/14 Repeated start feature removed. * 3.0 sk 12/06/14 Implemented Repeated start feature. * 01/31/15 Modified the code according to MISRAC 2012 Compliant. +* 3.3 kvn 05/05/16 Modified latest code for MISRA-C:2012 Compliance. * * * @@ -135,7 +136,7 @@ s32 XIicPs_SetOptions(XIicPs *InstancePtr, u32 Options) * The hold bit in CR will be written by driver when the next transfer * is initiated. */ - if ((OptionsVar & XIICPS_REP_START_OPTION) != 0U ) { + if ((OptionsVar & (u32)XIICPS_REP_START_OPTION) != (u32)0 ) { InstancePtr->IsRepeatedStart = 1; OptionsVar = OptionsVar & (~XIICPS_REP_START_OPTION); } @@ -349,8 +350,8 @@ s32 XIicPs_SetSClk(XIicPs *InstancePtr, u32 FsclHz) u32 ControlReg; u32 CalcDivA; u32 CalcDivB; - u32 BestDivA = 0; - u32 BestDivB = 0; + u32 BestDivA; + u32 BestDivB; u32 FsclHzVar = FsclHz; Xil_AssertNonvoid(InstancePtr != NULL); @@ -379,12 +380,12 @@ s32 XIicPs_SetSClk(XIicPs *InstancePtr, u32 FsclHz) * If frequency 100KHz is selected, 90KHz should be set. * This is due to a hardware limitation. */ - if(FsclHzVar > 384600U) { - FsclHzVar = 384600U; + if(FsclHzVar > (u32)384600U) { + FsclHzVar = (u32)384600U; } - if((FsclHzVar <= 100000U) && (FsclHzVar > 90000U)) { - FsclHzVar = 90000U; + if((FsclHzVar <= (u32)100000U) && (FsclHzVar > (u32)90000U)) { + FsclHzVar = (u32)90000U; } /* diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v3_1/src/xiicps_selftest.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_6/src/xiicps_selftest.c similarity index 98% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v3_1/src/xiicps_selftest.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_6/src/xiicps_selftest.c index 2d9e0e35e..31e02b56f 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v3_1/src/xiicps_selftest.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_6/src/xiicps_selftest.c @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* Copyright (C) 2010 - 2016 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -33,7 +33,7 @@ /** * * @file xiicps_selftest.c -* @addtogroup iicps_v3_0 +* @addtogroup iicps_v3_5 * @{ * * This component contains the implementation of selftest functions for the diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v3_1/src/xiicps_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_6/src/xiicps_sinit.c similarity index 97% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v3_1/src/xiicps_sinit.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_6/src/xiicps_sinit.c index 40ee7733e..d8fbc4cd5 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v3_1/src/xiicps_sinit.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_6/src/xiicps_sinit.c @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* Copyright (C) 2010 - 2016 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -33,7 +33,7 @@ /** * * @file xiicps_sinit.c -* @addtogroup iicps_v3_0 +* @addtogroup iicps_v3_5 * @{ * * The implementation of the XIicPs component's static initialization diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v3_1/src/xiicps_slave.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_6/src/xiicps_slave.c similarity index 96% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v3_1/src/xiicps_slave.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_6/src/xiicps_slave.c index 074b5ea2e..adc40a435 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/iicps_v3_1/src/xiicps_slave.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_6/src/xiicps_slave.c @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* Copyright (C) 2010 - 2016 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -32,7 +32,7 @@ /*****************************************************************************/ /** * @file xiicps_slave.c -* @addtogroup iicps_v3_0 +* @addtogroup iicps_v3_5 * @{ * * Handles slave transfers @@ -44,6 +44,7 @@ * 1.00a jz 01/30/10 First release * 1.04a kpc 08/30/13 Avoid buffer overwrite in SlaveRecvData function * 3.00 sk 01/31/15 Modified the code according to MISRAC 2012 Compliant. +* 3.3 kvn 05/05/16 Modified latest code for MISRA-C:2012 Compliance. * * * @@ -210,7 +211,8 @@ s32 XIicPs_SlaveSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount) s32 BytesToSend; s32 Error = 0; s32 Status = (s32)XST_SUCCESS; - u32 Value; + _Bool Value; + _Bool Result; /* * Assert validates the input arguments. @@ -227,8 +229,9 @@ s32 XIicPs_SlaveSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount) * Use RXRW bit in status register to wait master to start a read. */ StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET); - while (((StatusReg & XIICPS_SR_RXRW_MASK) == 0U) && - ((!Error) != 0)) { + Result = (((u32)(StatusReg & XIICPS_SR_RXRW_MASK) == (u32)0x0U) && + (Error == 0)); + while (Result != FALSE) { /* * If master tries to send us data, it is an error. @@ -238,6 +241,8 @@ s32 XIicPs_SlaveSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount) } StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET); + Result = (((u32)(StatusReg & XIICPS_SR_RXRW_MASK) == (u32)0x0U) && + (Error == 0)); } if (Error != 0) { @@ -255,8 +260,8 @@ s32 XIicPs_SlaveSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount) * there are no errors. */ Value = (InstancePtr->SendByteCount > (s32)0) && - ((!Error) != 0); - while (Value != (u32)0x00U) { + ((Error == 0)); + while (Value != FALSE) { /* * Find out how many can be sent. @@ -276,7 +281,7 @@ s32 XIicPs_SlaveSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount) * Wait for master to read the data out of fifo. */ while (((StatusReg & XIICPS_SR_TXDV_MASK) != (u32)0x00U) && - ((!Error) != 0)) { + (Error == 0)) { /* * If master terminates the transfer before all data is @@ -296,12 +301,12 @@ s32 XIicPs_SlaveSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount) StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET); } - Value = (InstancePtr->SendByteCount > (s32)0U) && - ((!Error) != 0); + Value = ((InstancePtr->SendByteCount > (s32)0) && + (Error == 0)); } } if (Error != 0) { - Status = (s32)XST_FAILURE; + Status = (s32)XST_FAILURE; } return Status; @@ -551,7 +556,7 @@ void XIicPs_SlaveInterruptHandler(XIicPs *InstancePtr) /* * Signal application if there are any events. */ - if (0U != StatusEvent) { + if ((u32)0U != StatusEvent) { InstancePtr->StatusHandler(InstancePtr->CallBackRef, StatusEvent); } diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_1/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_3/src/Makefile similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_1/src/Makefile rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_3/src/Makefile diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_1/src/xipipsu.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_3/src/xipipsu.c similarity index 87% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_1/src/xipipsu.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_3/src/xipipsu.c index 7c9d98ab0..06d9ced3c 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_1/src/xipipsu.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_3/src/xipipsu.c @@ -33,7 +33,7 @@ /** * * @file xipipsu.c -* @addtogroup ipipsu_v1_0 +* @addtogroup ipipsu_v2_3 * @{ * * This file contains the implementation of the interface functions for XIpiPsu @@ -48,6 +48,7 @@ * 2.0 mjr 01/22/16 Fixed response buffer address * calculation. CR# 932582. * 2.1 kvn 05/05/16 Modified code for MISRA-C:2012 Compliance +* 2.2 kvn 02/17/17 Add support for updating ConfigTable at run time * * *****************************************************************************/ @@ -56,6 +57,9 @@ #include "xipipsu.h" #include "xipipsu_hw.h" +/************************** Variable Definitions *****************************/ +extern XIpiPsu_Config XIpiPsu_ConfigTable[XPAR_XIPIPSU_NUM_INSTANCES]; + /****************************************************************************/ /** * Initialize the Instance pointer based on a given Config Pointer @@ -350,4 +354,39 @@ XStatus XIpiPsu_WriteMessage(XIpiPsu *InstancePtr, u32 DestCpuMask, u32 *MsgPtr, return Status; } + +/*****************************************************************************/ +/** +* +* Set up the device configuration based on the unique device ID. A table +* contains the configuration info for each device in the system. +* +* @param DeviceId contains the ID of the device to set up the +* configuration for. +* +* @return A pointer to the device configuration for the specified +* device ID. See xipipsu.h for the definition of +* XIpiPsu_Config. +* +* @note This is for safety use case where in this function has to +* be called before CfgInitialize. So that driver will be +* initialized with the provided configuration. For non-safe +* use cases, this is not needed. +* +******************************************************************************/ +void XIpiPsu_SetConfigTable(u32 DeviceId, XIpiPsu_Config *ConfigTblPtr) +{ + u32 Index; + + Xil_AssertVoid(ConfigTblPtr != NULL); + + for (Index = 0U; Index < XPAR_XIPIPSU_NUM_INSTANCES; Index++) { + if (XIpiPsu_ConfigTable[Index].DeviceId == DeviceId) { + XIpiPsu_ConfigTable[Index].BaseAddress = ConfigTblPtr->BaseAddress; + XIpiPsu_ConfigTable[Index].BitMask = ConfigTblPtr->BitMask; + XIpiPsu_ConfigTable[Index].BufferIndex = ConfigTblPtr->BufferIndex; + XIpiPsu_ConfigTable[Index].IntId = ConfigTblPtr->IntId; + } + } +} /** @} */ diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_1/src/xipipsu.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_3/src/xipipsu.h similarity index 92% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_1/src/xipipsu.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_3/src/xipipsu.h index 0253b9a68..83701f46e 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_1/src/xipipsu.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_3/src/xipipsu.h @@ -32,7 +32,7 @@ /*****************************************************************************/ /** * @file xipipsu.h -* @addtogroup ipipsu_v1_0 +* @addtogroup ipipsu_v2_3 * @{ * @details * @@ -76,7 +76,23 @@ * @note XIpiPsu_Reset can be used at startup to clear the status and * disable all sources * - */ + * 
+ * MODIFICATION HISTORY:
+ *
+ * Ver  Who Date     Changes
+ * ---- --- -------- --------------------------------------------------
+ * 2.2  ms  01/23/17 Modified xil_printf statement in main function for all
+ *                    examples to ensure that "Successfully ran" and "Failed"
+ *                    strings are available in all examples. This is a fix
+ *                    for CR-965028.
+ *  	kvn 02/17/17  Add support for updating ConfigTable at run time
+ *      ms  03/17/17  Added readme.txt file in examples folder for doxygen
+ *                    generation.
+ * 2.3  ms  04/11/17  Modified tcl file to add suffix U for all macro
+ *                    definitions of ipipsu in xparameters.h
+ *
+ * + *****************************************************************************/ /*****************************************************************************/ #ifndef XIPIPSU_H_ #define XIPIPSU_H_ @@ -276,6 +292,7 @@ XStatus XIpiPsu_ReadMessage(XIpiPsu *InstancePtr, u32 SrcCpuMask, u32 *MsgPtr, XStatus XIpiPsu_WriteMessage(XIpiPsu *InstancePtr, u32 DestCpuMask, u32 *MsgPtr, u32 MsgLength, u8 BufferType); +void XIpiPsu_SetConfigTable(u32 DeviceId, XIpiPsu_Config *ConfigTblPtr); #endif /* XIPIPSU_H_ */ /** @} */ diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_1/src/xipipsu_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_3/src/xipipsu_g.c similarity index 83% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_1/src/xipipsu_g.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_3/src/xipipsu_g.c index d40c925a9..f71017c2b 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_1/src/xipipsu_g.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_3/src/xipipsu_g.c @@ -5,7 +5,7 @@ * Version: * DO NOT EDIT. * -* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.* +* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.* *Permission is hereby granted, free of charge, to any person obtaining a copy *of this software and associated documentation files (the Software), to deal *in the Software without restriction, including without limitation the rights @@ -44,7 +44,7 @@ * The configuration table for devices */ -XIpiPsu_Config XIpiPsu_ConfigTable[] = +XIpiPsu_Config XIpiPsu_ConfigTable[XPAR_XIPIPSU_NUM_INSTANCES] = { { @@ -83,22 +83,6 @@ XIpiPsu_Config XIpiPsu_ConfigTable[] = { XPAR_PSU_IPI_6_BIT_MASK, XPAR_PSU_IPI_6_BUFFER_INDEX - }, - { - XPAR_PSU_IPI_7_BIT_MASK, - XPAR_PSU_IPI_7_BUFFER_INDEX - }, - { - XPAR_PSU_IPI_8_BIT_MASK, - XPAR_PSU_IPI_8_BUFFER_INDEX - }, - { - XPAR_PSU_IPI_9_BIT_MASK, - XPAR_PSU_IPI_9_BUFFER_INDEX - }, - { - XPAR_PSU_IPI_10_BIT_MASK, - XPAR_PSU_IPI_10_BUFFER_INDEX } } } diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_1/src/xipipsu_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_3/src/xipipsu_hw.h similarity index 95% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_1/src/xipipsu_hw.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_3/src/xipipsu_hw.h index b4c02b6e1..5a3202192 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_1/src/xipipsu_hw.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_3/src/xipipsu_hw.h @@ -32,7 +32,7 @@ /** * * @file xipipsu_hw.h -* @addtogroup ipipsu_v1_0 +* @addtogroup ipipsu_v2_3 * @{ * * This file contains macro definitions for low level HW related params @@ -62,8 +62,8 @@ #define XIPIPSU_BUFFER_OFFSET_TARGET (32U * 2U) #define XIPIPSU_BUFFER_OFFSET_RESPONSE (32U) -/* Max Number of IPI slots on the device */ -#define XIPIPSU_MAX_TARGETS 11 +/* Number of IPI slots enabled on the device */ +#define XIPIPSU_MAX_TARGETS XPAR_XIPIPSU_NUM_TARGETS /* Register Offsets for each member of IPI Register Set */ #define XIPIPSU_TRIG_OFFSET 0x00U diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ipipsu_v2_1/src/xipipsu_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_3/src/xipipsu_sinit.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ipipsu_v2_1/src/xipipsu_sinit.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_3/src/xipipsu_sinit.c index ae0900498..6f52a63e0 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ipipsu_v2_1/src/xipipsu_sinit.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_3/src/xipipsu_sinit.c @@ -32,7 +32,7 @@ /** * * @file xipipsu_sinit.c -* @addtogroup ipipsu_v1_0 +* @addtogroup ipipsu_v2_3 * @{ * * The implementation of the XIpiPsu component's static initialization diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_3/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_7/src/Makefile similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_3/src/Makefile rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_7/src/Makefile diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/qspipsu_v1_3/src/xqspipsu.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_7/src/xqspipsu.c similarity index 96% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/qspipsu_v1_3/src/xqspipsu.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_7/src/xqspipsu.c index 93fa53f75..60eee53ea 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/qspipsu_v1_3/src/xqspipsu.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_7/src/xqspipsu.c @@ -33,7 +33,7 @@ /** * * @file xqspipsu.c -* @addtogroup qspipsu_v1_0 +* @addtogroup qspipsu_v1_7 * @{ * * This file implements the functions required to use the QSPIPSU hardware to @@ -60,6 +60,10 @@ * 1.3 nsk 09/16/16 Update PollData and PollTimeout support for dual * parallel configurations, modified XQspiPsu_PollData() * and XQspiPsu_Create_PollConfigData() +* 1,5 nsk 08/14/17 Added CCI support +* 1.7 tjs 01/16/18 Removed the check for DMA MSB to be written. (CR#992560) +* 1.7 tjs 01/17/18 Added a support to toggle WP pin of the flash. +* 1.7 tjs 03/14/18 Added support in EL1 NS mode (CR#974882) * * * @@ -150,6 +154,7 @@ s32 XQspiPsu_CfgInitialize(XQspiPsu *InstancePtr, XQspiPsu_Config *ConfigPtr, InstancePtr->StatusHandler = StubStatusHandler; InstancePtr->Config.BusWidth = ConfigPtr->BusWidth; InstancePtr->Config.InputClockHz = ConfigPtr->InputClockHz; + InstancePtr->Config.IsCacheCoherent = ConfigPtr->IsCacheCoherent; /* Other instance variable initializations */ InstancePtr->SendBufferPtr = NULL; InstancePtr->RecvBufferPtr = NULL; @@ -928,7 +933,7 @@ void XQspiPsu_SetStatusHandler(XQspiPsu *InstancePtr, void *CallBackRef, static void StubStatusHandler(void *CallBackRef, u32 StatusEvent, u32 ByteCount) { - (void *) CallBackRef; + (void) CallBackRef; (void) StatusEvent; (void) ByteCount; @@ -1136,13 +1141,13 @@ static inline void XQspiPsu_SetupRxDma(XQspiPsu *InstancePtr, XQSPIPSU_QSPIDMA_DST_ADDR_OFFSET, (u32)AddrTemp); - AddrTemp = AddrTemp >> 32; - if ((AddrTemp & 0xFFFU) != FALSE) { - XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress, - XQSPIPSU_QSPIDMA_DST_ADDR_MSB_OFFSET, - (u32)AddrTemp & - XQSPIPSU_QSPIDMA_DST_ADDR_MSB_MASK); - } +#ifdef __aarch64__ + AddrTemp = (u64)((INTPTR)(Msg->RxBfrPtr) >> 32); + XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress, + XQSPIPSU_QSPIDMA_DST_ADDR_MSB_OFFSET, + (u32)AddrTemp & + XQSPIPSU_QSPIDMA_DST_ADDR_MSB_MASK); +#endif Remainder = InstancePtr->RxBytes % 4; DmaRxBytes = InstancePtr->RxBytes; @@ -1151,8 +1156,10 @@ static inline void XQspiPsu_SetupRxDma(XQspiPsu *InstancePtr, DmaRxBytes = InstancePtr->RxBytes - Remainder; Msg->ByteCount = (u32)DmaRxBytes; } - - Xil_DCacheInvalidateRange((INTPTR)InstancePtr->RecvBufferPtr, Msg->ByteCount); + if (InstancePtr->Config.IsCacheCoherent == 0) { + Xil_DCacheInvalidateRange((INTPTR)InstancePtr->RecvBufferPtr, + Msg->ByteCount); + } /* Write no. of words to DMA DST SIZE */ XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress, @@ -1511,4 +1518,37 @@ static inline u32 XQspiPsu_Create_PollConfigData(XQspiPsu *QspiPsuPtr, & XQSPIPSU_POLL_CFG_DATA_VALUE_MASK); return ConfigData; } + +/*****************************************************************************/ +/** +* @brief +* This API enables/ disables Write Protect pin on the flash parts. +* +* @param QspiPtr is a pointer to the QSPIPSU driver component to use. +* +* @return None +* +* @note By default WP pin as per the QSPI controller is driven High +* which means no write protection. Calling this function once +* will enable the protection. +* +******************************************************************************/ +void XQspiPsu_WriteProtectToggle(XQspiPsu *QspiPsuPtr, u32 Toggle) +{ + /* For Single and Stacked flash configuration with x1 or x2 mode*/ + if (QspiPsuPtr->Config.ConnectionMode == XQSPIPSU_CONNECTION_MODE_SINGLE) { + /* Enable */ + XQspiPsu_Enable(QspiPsuPtr); + + /* Select slave */ + XQspiPsu_GenFifoEntryCSAssert(QspiPsuPtr); + + XQspiPsu_WriteReg(QspiPsuPtr->Config.BaseAddress, XQSPIPSU_GPIO_OFFSET, + Toggle); + + } else if (QspiPsuPtr->Config.ConnectionMode == XQSPIPSU_CONNECTION_MODE_PARALLEL || + QspiPsuPtr->Config.ConnectionMode == XQSPIPSU_CONNECTION_MODE_STACKED) { + xil_printf("Dual Parallel/Stacked configuration is not supported by this API\r\n"); + } +} /** @} */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/qspipsu_v1_3/src/xqspipsu.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_7/src/xqspipsu.h similarity index 85% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/qspipsu_v1_3/src/xqspipsu.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_7/src/xqspipsu.h index 94801949c..b73b72293 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/qspipsu_v1_3/src/xqspipsu.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_7/src/xqspipsu.h @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2018 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -33,7 +33,7 @@ /** * * @file xqspipsu.h -* @addtogroup qspipsu_v1_0 +* @addtogroup qspipsu_v1_7 * @{ * @details * @@ -112,7 +112,33 @@ * configuration. Updated XQspiPsu_PollData() and * XQspiPsu_Create_PollConfigData() functions in xqspipsu.c * and also modified the polldata example -* +* ms 03/17/17 Added readme.txt file in examples folder for doxygen +* generation. +* ms 04/05/17 Modified Comment lines in functions of qspipsu +* examples to recognize it as documentation block +* and modified filename tag to include them in +* doxygen examples. +* 1.4 tjs 05/26/17 Added support for accessing upper DDR (0x800000000) +* while booting images from QSPI +* 1.5 tjs 08/08/17 Added index.html file for importing examples from system.mss +* 1.5 nsk 08/14/17 Added CCI support +* 1.5 tjs 09/14/17 Modified the checks for 4 byte addressing and commands. +* 1.6 tjs 10/16/17 Flow for accessing flash is made similar to u-boot and linux +* For CR-984966 +* 1.6 tjs 11/02/17 Resolved the compilation errors for ICCARM. CR-988625 +* 1.7 tjs 11/16/17 Removed the unsupported 4 Byte write and sector erase +* commands. +* 1.7 tjs 12/01/17 Added support for MT25QL02G Flash from Micron. CR-990642 +* 1.7 tjs 12/19/17 Added support for S25FL064L from Spansion. CR-990724 +* 1.7 tjs 01/11/18 Added support for MX66L1G45G flash from Macronix CR-992367 +* 1.7 tjs 01/16/18 Removed the check for DMA MSB to be written. (CR#992560) +* 1.7 tjs 01/17/18 Added support to toggle the WP pin of flash. (PR#2448) +* Added XQspiPsu_SetWP() in xqspipsu_options.c +* Added XQspiPsu_WriteProtectToggle() in xqspipsu.c and +* also added write protect example. +* 1.7 tjs 03/14/18 Added support in EL1 NS mode (CR#974882) +* 1.7 tjs 26/03/18 In dual parallel mode enable both CS when issuing Write +* enable command. CR-998478 * * ******************************************************************************/ @@ -175,6 +201,7 @@ typedef struct { u32 InputClockHz; /**< Input clock frequency */ u8 ConnectionMode; /**< Single, Stacked and Parallel mode */ u8 BusWidth; /**< Bus width available on board */ + u8 IsCacheCoherent; /**< Describes whether Cache Coherent or not */ } XQspiPsu_Config; /** @@ -259,6 +286,9 @@ typedef struct { #define XQSPIPSU_MSG_FLAG_TX 0x4U #define XQSPIPSU_MSG_FLAG_POLL 0x8U +/* GQSPI configuration to toggle WP of flash*/ +#define XQSPIPSU_SET_WP 1 + #define XQspiPsu_Select(InstancePtr, Mask) XQspiPsu_Out32(((InstancePtr)->Config.BaseAddress) + XQSPIPSU_SEL_OFFSET, Mask) #define XQspiPsu_Enable(InstancePtr) XQspiPsu_Out32(((InstancePtr)->Config.BaseAddress) + XQSPIPSU_EN_OFFSET, XQSPIPSU_EN_MASK) @@ -267,6 +297,7 @@ typedef struct { #define XQspiPsu_GetLqspiConfigReg(InstancePtr) XQspiPsu_In32((XQSPIPS_BASEADDR) + XQSPIPSU_LQSPI_CR_OFFSET) + /************************** Function Prototypes ******************************/ /* Initialization and reset */ @@ -292,6 +323,8 @@ s32 XQspiPsu_SetOptions(XQspiPsu *InstancePtr, u32 Options); s32 XQspiPsu_ClearOptions(XQspiPsu *InstancePtr, u32 Options); u32 XQspiPsu_GetOptions(XQspiPsu *InstancePtr); s32 XQspiPsu_SetReadMode(XQspiPsu *InstancePtr, u32 Mode); +void XQspiPsu_SetWP(XQspiPsu *InstancePtr, u8 Value); +void XQspiPsu_WriteProtectToggle(XQspiPsu *InstancePtr, u32 Toggle); #ifdef __cplusplus } diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_3/src/xqspipsu_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_7/src/xqspipsu_g.c similarity index 88% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_3/src/xqspipsu_g.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_7/src/xqspipsu_g.c index 969fa96b0..a6df4f5b8 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_3/src/xqspipsu_g.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_7/src/xqspipsu_g.c @@ -5,7 +5,7 @@ * Version: * DO NOT EDIT. * -* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.* +* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.* *Permission is hereby granted, free of charge, to any person obtaining a copy *of this software and associated documentation files (the Software), to deal *in the Software without restriction, including without limitation the rights @@ -44,14 +44,15 @@ * The configuration table for devices */ -XQspiPsu_Config XQspiPsu_ConfigTable[] = +XQspiPsu_Config XQspiPsu_ConfigTable[XPAR_XQSPIPSU_NUM_INSTANCES] = { { XPAR_PSU_QSPI_0_DEVICE_ID, XPAR_PSU_QSPI_0_BASEADDR, XPAR_PSU_QSPI_0_QSPI_CLK_FREQ_HZ, XPAR_PSU_QSPI_0_QSPI_MODE, - XPAR_PSU_QSPI_0_QSPI_BUS_WIDTH + XPAR_PSU_QSPI_0_QSPI_BUS_WIDTH, + XPAR_PSU_QSPI_0_IS_CACHE_COHERENT } }; diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/qspipsu_v1_3/src/xqspipsu_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_7/src/xqspipsu_hw.h similarity index 99% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/qspipsu_v1_3/src/xqspipsu_hw.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_7/src/xqspipsu_hw.h index 40314d6e1..a7e856310 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/qspipsu_v1_3/src/xqspipsu_hw.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_7/src/xqspipsu_hw.h @@ -33,7 +33,7 @@ /** * * @file xqspipsu_hw.h -* @addtogroup qspipsu_v1_0 +* @addtogroup qspipsu_v1_7 * @{ * * This file contains low level access funcitons using the base address @@ -49,6 +49,7 @@ * sk 04/24/15 Modified the code according to MISRAC-2012. * 1.2 nsk 07/01/16 Added LQSPI supported Masks * rk 07/15/16 Added support for TapDelays at different frequencies. +* 1.7 tjs 03/14/18 Added support in EL1 NS mode. * * * @@ -147,6 +148,7 @@ extern "C" { or quad I/O */ #define XQSPIPS_LQSPI_CR_INST_MASK 0x000000FF /**< Read instr code */ #define XQSPIPS_LQSPI_CR_RST_STATE 0x80000003 /**< Default LQSPI CR value */ +#define XQSPIPS_LQSPI_CR_4_BYTE_STATE 0x88000013 /**< Default 4 Byte LQSPI CR value */ #define XQSPIPS_LQSPI_CFG_RST_STATE 0x800238C1 /**< Default LQSPI CFG value */ /** * Register: XQSPIPSU_ISR @@ -828,6 +830,7 @@ extern "C" { #define IOU_TAPDLY_BYPASS_LQSPI_RX_SHIFT 0X02 #define IOU_TAPDLY_BYPASS_LQSPI_RX_WIDTH 0X01 #define IOU_TAPDLY_BYPASS_LQSPI_RX_MASK 0x00000004 +#define IOU_TAPDLY_RESET_STATE 0x7 /***************** Macros (Inline Functions) Definitions *********************/ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/qspipsu_v1_3/src/xqspipsu_options.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_7/src/xqspipsu_options.c similarity index 92% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/qspipsu_v1_3/src/xqspipsu_options.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_7/src/xqspipsu_options.c index 2c77a0881..e943e52ae 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/qspipsu_v1_3/src/xqspipsu_options.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_7/src/xqspipsu_options.c @@ -33,7 +33,7 @@ /** * * @file xqspipsu_options.c -* @addtogroup qspipsu_v1_0 +* @addtogroup qspipsu_v1_7 * @{ * * This file implements funcitons to configure the QSPIPSU component, @@ -51,6 +51,8 @@ * 1.2 nsk 07/01/16 Modified XQspiPsu_SetOptions() to support * LQSPI options and updated OptionsTable * rk 07/15/16 Added support for TapDelays at different frequencies. +* 1.7 tjs 01/17/18 Added support to toggle the WP pin of flash. (PR#2448) +* 1.7 tjs 03/14/18 Added support in EL1 NS mode. (CR#974882) * * * @@ -59,6 +61,9 @@ /***************************** Include Files *********************************/ #include "xqspipsu.h" +#if defined (__aarch64__) +#include "xil_smc.h" +#endif /************************** Constant Definitions *****************************/ @@ -179,7 +184,7 @@ s32 XQspiPsu_SetOptions(XQspiPsu *InstancePtr, u32 Options) ConfigReg = XQspiPsu_ReadReg(XQSPIPS_BASEADDR,XQSPIPSU_LQSPI_CR_OFFSET); if (QspiPsuOptions & XQSPIPSU_LQSPI_MODE_OPTION) { - XQspiPsu_WriteReg(XQSPIPS_BASEADDR,XQSPIPSU_LQSPI_CR_OFFSET,XQSPIPS_LQSPI_CR_RST_STATE); + XQspiPsu_WriteReg(XQSPIPS_BASEADDR,XQSPIPSU_LQSPI_CR_OFFSET,XQSPIPS_LQSPI_CR_4_BYTE_STATE); XQspiPsu_WriteReg(XQSPIPS_BASEADDR,XQSPIPSU_CFG_OFFSET,XQSPIPS_LQSPI_CFG_RST_STATE); /* Enable the QSPI controller */ XQspiPsu_WriteReg(XQSPIPS_BASEADDR,XQSPIPSU_EN_OFFSET,XQSPIPSU_EN_MASK); @@ -344,8 +349,15 @@ s32 XQspi_Set_TapDelay(XQspiPsu * InstancePtr,u32 TapdelayBypass, if (InstancePtr->IsBusy == TRUE) { Status = XST_DEVICE_BUSY; } else { +#if EL1_NONSECURE && defined (__aarch64__) + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + IOU_TAPDLY_BYPASS_OFFSET) | + ((u64)(0x4) << 32), + (u64)TapdelayBypass, 0, 0, 0, 0, 0); +#else XQspiPsu_WriteReg(XPS_SYS_CTRL_BASEADDR,IOU_TAPDLY_BYPASS_OFFSET, TapdelayBypass); +#endif XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPSU_LPBK_DLY_ADJ_OFFSET,LPBKDelay); XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress, @@ -380,8 +392,12 @@ static s32 XQspipsu_Calculate_Tapdelay(XQspiPsu *InstancePtr, u8 Prescaler) Divider = (1 << (Prescaler+1)); FreqDiv = (InstancePtr->Config.InputClockHz)/Divider; +#if EL1_NONSECURE && defined (__aarch64__) + Tapdelay = IOU_TAPDLY_RESET_STATE; +#else Tapdelay = XQspiPsu_ReadReg(XPS_SYS_CTRL_BASEADDR, - IOU_TAPDLY_BYPASS_OFFSET); + IOU_TAPDLY_BYPASS_OFFSET); +#endif Tapdelay = Tapdelay & (~IOU_TAPDLY_BYPASS_LQSPI_RX_MASK); @@ -618,4 +634,33 @@ s32 XQspiPsu_SetReadMode(XQspiPsu *InstancePtr, u32 Mode) #endif return Status; } + +/*****************************************************************************/ +/** +* +* This function sets the Write Protect and Hold options for the QSPIPSU device +* driver.The device must be idle rather than busy transferring data before +* setting Write Protect and Hold options. +* +* @param InstancePtr is a pointer to the XQspiPsu instance. +* @param Value of the WP_HOLD bit in configuration register +* +* @return None +* +* @note +* This function is not thread-safe. This function can only be used with single +* flash configuration and x1/x2 data mode. This function cannot be used with +* x4 data mode and dual parallel and stacked flash configuration. +* +******************************************************************************/ +void XQspiPsu_SetWP(XQspiPsu *InstancePtr, u8 Value) +{ + u32 ConfigReg; + + ConfigReg = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress, + XQSPIPSU_CFG_OFFSET); + ConfigReg |= Value << XQSPIPSU_CFG_WP_HOLD_SHIFT; + XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPSU_CFG_OFFSET, + ConfigReg); +} /** @} */ diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_3/src/xqspipsu_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_7/src/xqspipsu_sinit.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_3/src/xqspipsu_sinit.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_7/src/xqspipsu_sinit.c index 63aaed0bb..3869167d8 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_3/src/xqspipsu_sinit.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_7/src/xqspipsu_sinit.c @@ -33,7 +33,7 @@ /** * * @file xqspipsu_sinit.c -* @addtogroup qspipsu_v1_0 +* @addtogroup qspipsu_v1_7 * @{ * * The implementation of the XQspiPsu component's static initialization diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/resetps_v1_0/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/resetps_v1_0/src/Makefile new file mode 100644 index 000000000..67ab3d8a9 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/resetps_v1_0/src/Makefile @@ -0,0 +1,40 @@ +COMPILER= +ARCHIVER= +CP=cp +COMPILER_FLAGS= +EXTRA_COMPILER_FLAGS= +LIB=libxil.a + +CC_FLAGS = $(COMPILER_FLAGS) +ECC_FLAGS = $(EXTRA_COMPILER_FLAGS) + +RELEASEDIR=../../../lib +INCLUDEDIR=../../../include +INCLUDES=-I./. -I${INCLUDEDIR} + +OUTS = *.o + +LIBSOURCES:=*.c +INCLUDEFILES:=*.h + +OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c))) + +libs: banner resetps_libs clean + +%.o: %.c + ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $< + +banner: + echo "Compiling resetps" + +resetps_libs: ${OBJECTS} + $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS} + +.PHONY: include +include: resetps_includes + +resetps_includes: + ${CP} ${INCLUDEFILES} ${INCLUDEDIR} + +clean: + rm -rf ${OBJECTS} diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/resetps_v1_0/src/xresetps.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/resetps_v1_0/src/xresetps.c new file mode 100644 index 000000000..626ec54d7 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/resetps_v1_0/src/xresetps.c @@ -0,0 +1,1030 @@ +/****************************************************************************** +* +* Copyright (C) 2017 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xresetps.c +* @addtogroup xresetps_v1_0 +* @{ +* +* Contains the implementation of interface functions of the XResetPs driver. +* See xresetps.h for a description of the driver. +* +* 
+* MODIFICATION HISTORY:
+* Ver   Who    Date     Changes
+* ----- ------ -------- ---------------------------------------------
+* 1.00  cjp    09/05/17 First release
+*
+* +******************************************************************************/ + +/***************************** Include Files *********************************/ +#include "xresetps.h" +#include "xresetps_hw.h" +#include "xil_types.h" + +/************************** Constant Definitions *****************************/ +#define XRESETPS_RSTID_BASE (1000) +#define XRESETPS_REGADDR_INVALID (0xFFFFFFFFU) +#define XRESETPS_BM_INVALID (0xFFFFFFFFU) + +/**************************** Type Definitions *******************************/ +typedef struct { + const u32 SlcrregAddr; + const u32 SlcrregBitmask; + const u32 PwrStateBitmask; + const XResetPs_PulseTypes PulseType; + const u8 SupportedActions; +} XResetPs_Lookup; + +/************************** Variable Definitions *****************************/ +#if !EL1_NONSECURE +const static XResetPs_Lookup ResetMap[] = { + /* + * {Control Register, Control Bitmask, + * Power State Bitask, Pulse Type, + * Supported Actions}, + */ + {XRESETPS_CRF_APB_RST_FPD_TOP, PCIE_CFG_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_RST_FPD_TOP, PCIE_BRIDGE_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_RST_FPD_TOP, PCIE_CTRL_RESET_MASK, + PCIE_CTRL_PSCHK_MASK, XRESETPS_PT_DLY_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_RST_FPD_TOP, DP_RESET_MASK, + DP_PSCHK_MASK, XRESETPS_PT_DLY_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_RST_FPD_TOP, SWDT_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_RST_FPD_TOP, AFI_FM5_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_RST_FPD_TOP, AFI_FM4_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_RST_FPD_TOP, AFI_FM3_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_RST_FPD_TOP, AFI_FM2_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_RST_FPD_TOP, AFI_FM1_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_RST_FPD_TOP, AFI_FM0_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_RST_FPD_TOP, GDMA_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_RST_FPD_TOP, GPU_PP1_RESET_MASK, + GPU_PP1_PSCHK_MASK, XRESETPS_PT_DLY_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_RST_FPD_TOP, GPU_PP0_RESET_MASK, + GPU_PP0_PSCHK_MASK, XRESETPS_PT_DLY_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_RST_FPD_TOP, GPU_RESET_MASK, + GPU_PSCHK_MASK, XRESETPS_PT_DLY_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_RST_FPD_TOP, GT_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_RST_FPD_TOP, SATA_RESET_MASK, + SATA_PSCHK_MASK, XRESETPS_PT_DLY_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_RST_FPD_APU, ACPU3_PWRON_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_RST_FPD_APU, ACPU2_PWRON_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_RST_FPD_APU, ACPU1_PWRON_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_RST_FPD_APU, ACPU0_PWRON_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_RST_FPD_APU, APU_L2_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_RST_FPD_APU, ACPU3_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_RST_FPD_APU, ACPU2_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_RST_FPD_APU, ACPU1_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_RST_FPD_APU, ACPU0_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_RST_DDR_SS, DDR_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_RST_DDR_SS, DDR_APM_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RESET_CTRL, SOFT_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_IOU0, GEM0_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_IOU0, GEM1_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_IOU0, GEM2_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_IOU0, GEM3_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_IOU2, QSPI_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_IOU2, UART0_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_IOU2, UART1_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_IOU2, SPI0_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_IOU2, SPI1_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_IOU2, SDIO0_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_IOU2, SDIO1_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_IOU2, CAN0_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_IOU2, CAN1_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_IOU2, I2C0_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_IOU2, I2C1_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_IOU2, TTC0_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_IOU2, TTC1_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_IOU2, TTC2_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_IOU2, TTC3_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_IOU2, SWDT_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_IOU2, NAND_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_IOU2, ADMA_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_IOU2, GPIO_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_IOU2, IOU_CC_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_IOU2, TIMESTAMP_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_TOP, RPU_R50_RESET_MASK, + R50_PSCHK_MASK, XRESETPS_PT_DLY_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_TOP, RPU_R51_RESET_MASK, + R51_PSCHK_MASK, XRESETPS_PT_DLY_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_TOP, RPU_AMBA_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_TOP, OCM_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_TOP, RPU_PGE_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_TOP, USB0_CORERESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_TOP, USB1_CORERESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_TOP, USB0_HIBERRESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_TOP, USB1_HIBERRESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_TOP, USB0_APB_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_TOP, USB1_APB_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_TOP, IPI_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_TOP, APM_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_TOP, RTC_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_TOP, SYSMON_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_TOP, AFI_FM6_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_TOP, LPD_SWDT_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_TOP, FPD_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_DBG, RPU_DBG1_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_DBG, RPU_DBG0_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_DBG, DBG_LPD_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RST_LPD_DBG, DBG_FPD_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_APLL_CTRL, APLL_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_DPLL_CTRL, DPLL_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRF_APB_VPLL_CTRL, VPLL_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_IOPLL_CTRL, IOPLL_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_CRL_APB_RPLL_CTRL, RPLL_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_SUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL0_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL1_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL2_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL3_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL4_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL5_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL6_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL7_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL8_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL9_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL10_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL11_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL12_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL13_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL14_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL15_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL16_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL17_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL18_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL19_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL20_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL21_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL22_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL23_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL24_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL25_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL26_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL27_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL28_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL29_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL30_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_IOM_GPO3_CTRL, GPO3_PL31_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_GLB_RST_CTRL, RPU_LS_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_NOSUP)}, + {XRESETPS_PMU_GLB_RST_CTRL, PS_ONLY_RESET_MASK, + XRESETPS_BM_INVALID, XRESETPS_PT_NO_DLY_NO_PSCHK, + XRESETPS_SUPPORTED_ACT(XRESETPS_SUP, XRESETPS_SUP, XRESETPS_NOSUP)}, + /* All fields invalidated for PL since not supported */ + {XRESETPS_REGADDR_INVALID, XRESETPS_BM_INVALID, + XRESETPS_BM_INVALID, XRESETPS_PT_INVALID, + XRESETPS_SUPPORTED_ACT(XRESETPS_NOSUP, XRESETPS_NOSUP, XRESETPS_NOSUP)}, +}; +#endif + +/***************** Macros (Inline Functions) Definitions *********************/ + +/****************************************************************************/ +/** +* +* Initialize a specific reset controller instance/driver. This function +* must be called before other functions of the driver are called. +* +* @param InstancePtr is a pointer to the XResetPs instance. +* @param ConfigPtr is the config structure. +* @param EffectiveAddress is the base address for the device. It could be +* a virtual address if address translation is supported in the +* system, otherwise it is the physical address. +* +* @return +* - XST_SUCCESS if initialization was successful. +* +* @note None. +* +******************************************************************************/ +XStatus XResetPs_CfgInitialize(XResetPs *InstancePtr, + XResetPs_Config *ConfigPtr, u32 EffectiveAddress) +{ + /* Arguments validation */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(ConfigPtr != NULL); + + /* Copying instance */ + InstancePtr->Config.DeviceId = ConfigPtr->DeviceId; + InstancePtr->Config.BaseAddress = EffectiveAddress; + + return XST_SUCCESS; +} + +#if !EL1_NONSECURE +/****************************************************************************/ +/** +* +* Pulse Reset RPU. +* +* @param None. +* +* @return +* - XST_SUCCESS if successful else error code. +* +* @note The pulse reset sequence is referred from ug1085(v1.3) +* chapter-38. Few changes to the sequence are adpoted from PMUFW. +* +******************************************************************************/ +static XStatus XResetPs_PulseResetRpuLs(void) +{ + u32 TimeOut; + u32 RegValue; + + /* Block Cortex-R5 master interface */ + RegValue = XResetPs_ReadReg(XRESETPS_LPD_SCR_AXIISO_REQ_CTRL); + RegValue &= (~RPU_MASTER_ISO_MASK); + RegValue |= RPU_MASTER_ISO_MASK; + XResetPs_WriteReg(XRESETPS_LPD_SCR_AXIISO_REQ_CTRL, RegValue); + + /* Wait for acknowledgment from AIB until timeout */ + TimeOut = XRESETPS_AIB_PSPL_DELAY; + RegValue = XResetPs_ReadReg(XRESETPS_LPD_SCR_AXIISO_ACK_CTRL); + while ((TimeOut > 0U) && + ((RegValue & RPU_MASTER_ISO_MASK) != RPU_MASTER_ISO_MASK)) { + RegValue = XResetPs_ReadReg(XRESETPS_LPD_SCR_AXIISO_ACK_CTRL); + TimeOut--; + } + + if (TimeOut == 0U) { + /* + * @NOTE: + * AIB ack Timed Out. + * As per ug1085(v1.3), nothing is to be done on timeout, hence + * continuing with reset sequence. + */ + } + + /* Block Cortex-R5 slave interface */ + RegValue = XResetPs_ReadReg(XRESETPS_LPD_SCR_AXIISO_REQ_CTRL); + RegValue &= (~RPU_SLAVE_ISO_MASK); + RegValue |= RPU_SLAVE_ISO_MASK; + XResetPs_WriteReg(XRESETPS_LPD_SCR_AXIISO_REQ_CTRL, RegValue); + + /* Wait for acknowledgment from AIB until timeout */ + TimeOut = XRESETPS_AIB_PSPL_DELAY; + RegValue = XResetPs_ReadReg(XRESETPS_LPD_SCR_AXIISO_ACK_CTRL); + while ((TimeOut > 0U) && + ((RegValue & RPU_SLAVE_ISO_MASK) != RPU_SLAVE_ISO_MASK)) { + RegValue = XResetPs_ReadReg(XRESETPS_LPD_SCR_AXIISO_ACK_CTRL); + TimeOut--; + } + + if (TimeOut == 0U) { + /* + * @NOTE: + * AIB ack Timed Out. + * As per ug1085(v1.3), nothing is to be done on timeout, hence + * continuing with reset sequence. + */ + } + + /* Unblock Cortex-R5 master interface */ + RegValue = XResetPs_ReadReg(XRESETPS_LPD_SCR_AXIISO_REQ_CTRL); + RegValue &= (~RPU_MASTER_ISO_MASK); + XResetPs_WriteReg(XRESETPS_LPD_SCR_AXIISO_REQ_CTRL, RegValue); + + /* Initiate Cortex-R5 LockStep reset */ + RegValue = XResetPs_ReadReg(XRESETPS_PMU_GLB_RST_CTRL); + RegValue |= RPU_LS_RESET_MASK; + XResetPs_WriteReg(XRESETPS_PMU_GLB_RST_CTRL, RegValue); + + /* Wait */ + TimeOut = XRESETPS_RST_PROP_DELAY; + while (TimeOut > 0U) { + TimeOut--; + } + + /* Release Cortex-R5 from Reset */ + RegValue = XResetPs_ReadReg(XRESETPS_PMU_GLB_RST_CTRL); + RegValue &= (~RPU_LS_RESET_MASK); + XResetPs_WriteReg(XRESETPS_PMU_GLB_RST_CTRL, RegValue); + + /* Wait */ + TimeOut = XRESETPS_RST_PROP_DELAY; + while (TimeOut > 0U) { + TimeOut--; + } + + /* Unblock Cortex-R5 slave interface */ + RegValue = XResetPs_ReadReg(XRESETPS_LPD_SCR_AXIISO_REQ_CTRL); + RegValue &= (~RPU_SLAVE_ISO_MASK); + XResetPs_WriteReg(XRESETPS_LPD_SCR_AXIISO_REQ_CTRL, RegValue); + + return XST_SUCCESS; +} + +/****************************************************************************/ +/** +* +* Pulse Reset PS only. +* +* @param None. +* +* @return +* - XST_SUCCESS if successful else error code. +* +* @note The pulse reset sequence is referred from ug1085(v1.3) +* chapter-38. Few changes to the sequence are adpoted from PMUFW. +* +******************************************************************************/ +static XStatus XResetPs_PulseResetPsOnly(void) +{ + + u32 RegValue; + u32 TimeOut; + u8 ReconfirmAckCnt; + + /* TODO: Set PMU Error to indicate to PL */ + + /* Block FPD to PL and LPD to PL interfaces with AIB (in PS) */ + XResetPs_WriteReg(XRESETPS_PMU_GLB_AIB_CTRL, AIB_ISO_CTRL_MASK); + + /* + * @NOTE: Updated referring PMUFW + * There is a possibility of glitch in AIB ack signal to PMU, hence ack + * needs reconfirmation. + */ + /* Wait for AIB ack or Timeout */ + ReconfirmAckCnt = XRESETPS_AIB_PSPL_RECONFIRM_CNT; + do { + TimeOut = XRESETPS_AIB_PSPL_DELAY; + RegValue = XResetPs_ReadReg(XRESETPS_PMU_GLB_AIB_STATUS); + while ((TimeOut > 0U) && + ((RegValue & AIB_ISO_STATUS_MASK) != AIB_ISO_STATUS_MASK)) { + RegValue = + XResetPs_ReadReg(XRESETPS_PMU_GLB_AIB_STATUS); + TimeOut--; + } + + if (TimeOut == 0U) { + /* + * @NOTE: + * AIB ack Timed Out. + * As per ug1085(v1.3), nothing is to be done on + * timeout, hence continuing with reset sequence. + */ + ReconfirmAckCnt = 0U; + } else { + ReconfirmAckCnt--; + } + } + while (ReconfirmAckCnt > 0U); + + /* + * @NOTE: Updated referring PMUFW. + * Check if we are running Silicon version 1.0. If so, + * bypass the RPLL before initiating the reset. This is + * due to a bug in 1.0 Silicon wherein the PS hangs on a + * reset if the RPLL is in use. + */ + RegValue = XResetPs_ReadReg(XRESETPS_CSU_VERSION_REG); + if (XRESETPS_PLATFORM_PS_VER1 == (RegValue & PS_VERSION_MASK)) { + RegValue = XResetPs_ReadReg(XRESETPS_CRL_APB_RPLL_CTRL); + RegValue |= RPLL_BYPASS_MASK; + XResetPs_WriteReg(XRESETPS_CRL_APB_RPLL_CTRL, RegValue); + } + + /* Block the propagation of the PROG signal to the PL */ + RegValue = XResetPs_ReadReg(XRESETPS_PMU_GLB_PS_CTRL); + RegValue &= (~PROG_ENABLE_MASK); + XResetPs_WriteReg(XRESETPS_PMU_GLB_PS_CTRL, RegValue); + + RegValue = XResetPs_ReadReg(XRESETPS_PMU_GLB_PS_CTRL); + RegValue |= PROG_GATE_MASK; + XResetPs_WriteReg(XRESETPS_PMU_GLB_PS_CTRL, RegValue); + + /* Initiate PS-only reset */ + RegValue = XResetPs_ReadReg(XRESETPS_PMU_GLB_RST_CTRL); + RegValue |= PS_ONLY_RESET_MASK; + XResetPs_WriteReg(XRESETPS_PMU_GLB_RST_CTRL, RegValue); + + return XST_SUCCESS; +} + +/****************************************************************************/ +/** +* +* Pulse Reset FPD. +* +* @param None. +* +* @return +* - XST_SUCCESS if successful else error code. +* +* @note The pulse reset sequence is referred from ug1085(v1.3) +* chapter-38. Few changes to the sequence are adpoted from PMUFW. +* +******************************************************************************/ +static XStatus XResetPs_PulseResetFpd(void) +{ + u32 TimeOut; + u32 RegValue; + + /* Enable FPD to LPD isolations */ + RegValue = XResetPs_ReadReg(XRESETPS_LPD_SCR_AXIISO_REQ_CTRL); + RegValue &= (~FPD_TO_LPD_ISO_MASK); + RegValue |= FPD_TO_LPD_ISO_MASK; + XResetPs_WriteReg(XRESETPS_LPD_SCR_AXIISO_REQ_CTRL, RegValue); + + RegValue = XResetPs_ReadReg(XRESETPS_LPD_SLCR_APBISO_REQ_CTRL); + RegValue |= GPU_ISO_MASK; + XResetPs_WriteReg(XRESETPS_LPD_SLCR_APBISO_REQ_CTRL, RegValue); + + /* Enable LPD to FPD isolations */ + RegValue = XResetPs_ReadReg(XRESETPS_LPD_SCR_AXIISO_REQ_CTRL); + RegValue &= (~LPD_TO_FPD_ISO_MASK); + RegValue |= LPD_TO_FPD_ISO_MASK; + XResetPs_WriteReg(XRESETPS_LPD_SCR_AXIISO_REQ_CTRL, RegValue); + + /* + * Here we need to check for AIB ack, since nothing is done incase + * ack is not received, we are just waiting for specified timeout + * and continuing + */ + TimeOut = XRESETPS_AIB_ISO_DELAY; + while (TimeOut > 0U) { + TimeOut--; + } + + /* Initiate FPD reset */ + RegValue = XResetPs_ReadReg(XRESETPS_PMU_GLB_RST_CTRL); + RegValue |= FPD_APU_RESET_MASK; + XResetPs_WriteReg(XRESETPS_PMU_GLB_RST_CTRL, RegValue); + + /* Wait till reset propagates */ + TimeOut = XRESETPS_RST_PROP_DELAY; + while (TimeOut > 0U) { + TimeOut--; + } + + /* Disable FPD to LPD isolations */ + RegValue = XResetPs_ReadReg(XRESETPS_LPD_SCR_AXIISO_REQ_CTRL); + RegValue &= (~FPD_TO_LPD_ISO_MASK); + XResetPs_WriteReg(XRESETPS_LPD_SCR_AXIISO_REQ_CTRL, RegValue); + + RegValue = XResetPs_ReadReg(XRESETPS_LPD_SLCR_APBISO_REQ_CTRL); + RegValue &= (~GPU_ISO_MASK); + XResetPs_WriteReg(XRESETPS_LPD_SLCR_APBISO_REQ_CTRL, RegValue); + + /* Release from Reset and wait till it propagates */ + RegValue = XResetPs_ReadReg(XRESETPS_PMU_GLB_RST_CTRL); + RegValue &= (~FPD_APU_RESET_MASK); + XResetPs_WriteReg(XRESETPS_PMU_GLB_RST_CTRL, RegValue); + + /* Wait till reset propagates */ + TimeOut = XRESETPS_RST_PROP_DELAY; + while (TimeOut > 0U) { + TimeOut--; + } + + /* Disable LPD to FPD isolations */ + RegValue = XResetPs_ReadReg(XRESETPS_LPD_SCR_AXIISO_REQ_CTRL); + RegValue &= (~LPD_TO_FPD_ISO_MASK); + XResetPs_WriteReg(XRESETPS_LPD_SCR_AXIISO_REQ_CTRL, RegValue); + + return XST_SUCCESS; +} +#endif + +/****************************************************************************/ +/** +* +* Assert reset for specific peripheral based on reset ID. +* +* @param InstancePtr is a pointer to the XResetPs instance. +* @param ResetID is the ID of the peripheral. +* +* @return +* - XST_SUCCESS if reset assertion was successful. +* - Error Code otherwise. +* +* @note None. +* +******************************************************************************/ +XStatus XResetPs_ResetAssert(XResetPs *InstancePtr, + const XResetPs_RstId ResetID) +{ + /* Arguments validation */ + Xil_AssertNonvoid(InstancePtr != NULL); + if ((ResetID > XRESETPS_RSTID_END) || + (ResetID < XRESETPS_RSTID_START)) { + return XST_INVALID_PARAM; + } + +#if EL1_NONSECURE + /* Assert reset via PMUFW */ + u64 SmcArgs; + XSmc_OutVar out; + + SmcArgs = (u64)XRESETPS_RSTACT_ASSERT << 32; + SmcArgs |= ((u64)(ResetID + XRESETPS_RSTID_BASE)); + + out = Xil_Smc(PM_ASSERT_SMC_FID, SmcArgs, 0, 0, 0, 0, 0, 0); + + return ((u32)out.Arg0); +#else + u32 RegAddr; + u32 RegBitmask; + u32 RegValue; + + /* Ignoring Nodes that doesnot support assert */ + if (!XRESETPS_CHK_ASSERT_SUPPORT(ResetMap[ResetID].SupportedActions)) { + return XST_NO_FEATURE; + } + + RegAddr = ResetMap[ResetID].SlcrregAddr; + RegBitmask = ResetMap[ResetID].SlcrregBitmask; + + /* Enable bit to assert reset */ + RegValue = XResetPs_ReadReg(RegAddr); + RegValue |= RegBitmask; + XResetPs_WriteReg(RegAddr, RegValue); + + return XST_SUCCESS; +#endif +} + +/****************************************************************************/ +/** +* +* Deassert reset for specific peripheral based on reset ID. +* +* @param InstancePtr is a pointer to the XResetPs instance. +* @param ResetID is the ID of the peripheral. +* +* @return +* - XST_SUCCESS if reset deassertion was successful. +* - Error Code otherwise. +* +* @note None. +* +******************************************************************************/ +XStatus XResetPs_ResetDeassert(XResetPs *InstancePtr, + const XResetPs_RstId ResetID) +{ + /* Arguments validation */ + Xil_AssertNonvoid(InstancePtr != NULL); + if ((ResetID > XRESETPS_RSTID_END) || + (ResetID < XRESETPS_RSTID_START)) { + return XST_INVALID_PARAM; + } + +#if EL1_NONSECURE + /* Deassert reset via PMUFW */ + u64 SmcArgs; + XSmc_OutVar out; + + SmcArgs = (u64)XRESETPS_RSTACT_RELEASE << 32; + SmcArgs |= ((u64)(ResetID + XRESETPS_RSTID_BASE)); + + out = Xil_Smc(PM_ASSERT_SMC_FID, SmcArgs, 0, 0, 0, 0, 0, 0); + + return ((u32)out.Arg0); +#else + u32 RegAddr; + u32 RegBitmask; + u32 RegValue; + + /* Ignoring Nodes that does not support deassert */ + if (!XRESETPS_CHK_ASSERT_SUPPORT(ResetMap[ResetID].SupportedActions)) { + return XST_NO_FEATURE; + } + + RegAddr = ResetMap[ResetID].SlcrregAddr; + RegBitmask = ResetMap[ResetID].SlcrregBitmask; + + /* Disable bit to deassert reset */ + RegValue = XResetPs_ReadReg(RegAddr); + RegValue &= (~RegBitmask); + XResetPs_WriteReg(RegAddr, RegValue); + + return XST_SUCCESS; +#endif +} + +/****************************************************************************/ +/** +* +* Pulse reset for specific peripheral based on reset ID. +* +* @param InstancePtr is a pointer to the XResetPs instance. +* @param ResetID is the ID of the peripheral. +* +* @return +* - XST_SUCCESS if pulse reset was successful. +* - Error Code otherwise. +* +* @note None. +* +******************************************************************************/ +XStatus XResetPs_ResetPulse(XResetPs *InstancePtr, const XResetPs_RstId ResetID) +{ + /* Arguments validation */ + Xil_AssertNonvoid(InstancePtr != NULL); + if ((ResetID > XRESETPS_RSTID_END) || + (ResetID < XRESETPS_RSTID_START)) { + return XST_INVALID_PARAM; + } + +#if EL1_NONSECURE + /* Pulse reset via PMUFW */ + u64 SmcArgs; + XSmc_OutVar out; + + SmcArgs = (u64)XRESETPS_RSTACT_PULSE << 32; + SmcArgs |= ((u64)(ResetID + XRESETPS_RSTID_BASE)); + + out = Xil_Smc(PM_ASSERT_SMC_FID, SmcArgs, 0, 0, 0, 0, 0, 0); + + return ((u32)out.Arg0); +#else + u32 RegAddr; + u32 RegBitmask; + u32 RegValue; + u32 TimeOut; + + /* Ignoring Nodes that donot support pulse reset */ + if (!XRESETPS_CHK_PULSE_SUPPORT(ResetMap[ResetID].SupportedActions)) { + return XST_NO_FEATURE; + } + + /* Handling specific pulse resets */ + switch (ResetID) { + case XRESETPS_RSTID_FPD: + return XResetPs_PulseResetFpd(); + case XRESETPS_RSTID_RPU_LS: + return XResetPs_PulseResetRpuLs(); + case XRESETPS_RSTID_PS_ONLY: + return XResetPs_PulseResetPsOnly(); + default: + break; + } + + RegAddr = ResetMap[ResetID].SlcrregAddr; + RegBitmask = ResetMap[ResetID].SlcrregBitmask; + + /* Power state mask validation */ + if ((ResetMap[ResetID].PulseType == XRESETPS_PT_DLY_PSCHK) && + (ResetMap[ResetID].PwrStateBitmask != XRESETPS_BM_INVALID)) { + RegValue = XResetPs_ReadReg(XRESETPS_PMU_GLB_PWR_STATUS); + if (ResetMap[ResetID].PwrStateBitmask != + (RegValue && ResetMap[ResetID].PwrStateBitmask )) { + return XST_REGISTER_ERROR; + } + } + + /* Enable bit to assert reset */ + RegValue = XResetPs_ReadReg(RegAddr); + RegValue |= RegBitmask; + XResetPs_WriteReg(RegAddr, RegValue); + + /* Wait for assert propogation */ + if (ResetMap[ResetID].PulseType != XRESETPS_PT_NO_DLY_NO_PSCHK) { + TimeOut = XRESETPS_PULSE_PROP_DELAY; + while (TimeOut > 0U) { + TimeOut--; + } + } + + /* Disable bit to deassert reset */ + RegValue = XResetPs_ReadReg(RegAddr); + RegValue &= (~RegBitmask); + XResetPs_WriteReg(RegAddr, RegValue); + + /* Wait for release propogation */ + if (ResetMap[ResetID].PulseType != XRESETPS_PT_NO_DLY_NO_PSCHK) { + TimeOut = XRESETPS_PULSE_PROP_DELAY; + while (TimeOut > 0U) { + TimeOut--; + } + } + + return XST_SUCCESS; +#endif +} + +/****************************************************************************/ +/** +* +* Get reset status for specific peripheral based on reset ID. +* +* @param InstancePtr is a pointer to the XResetPs instance. +* @param ResetID is the ID of the peripheral. +* @param Status is the status of reset for ResetID. +* 1 if asserted and 0 if released +* +* @return +* - XST_SUCCESS if status fetched successful. +* - Error Code otherwise. +* +* @note None. +* +******************************************************************************/ +XStatus XResetPs_ResetStatus(XResetPs *InstancePtr, + const XResetPs_RstId ResetID, XResetPs_RstStatus *Status) +{ + /* Arguments validation */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(Status != NULL); + if ((ResetID > XRESETPS_RSTID_END) || + (ResetID < XRESETPS_RSTID_START)) { + return XST_INVALID_PARAM; + } + +#if EL1_NONSECURE + /* Get reset status via PMUFW */ + XSmc_OutVar out; + + out = Xil_Smc(PM_GETSTATUS_SMC_FID, + ((u64)(ResetID + XRESETPS_RSTID_BASE)), 0, 0, 0, 0, 0, 0); + *Status = ((u32)(out.Arg0 >> 32)); + + return ((u32)out.Arg0); +#else + u32 RegAddr; + u32 RegBitmask; + u32 RegValue; + + /* Ignoring Nodes that donot support reset status */ + if (!XRESETPS_CHK_STATUS_SUPPORT(ResetMap[ResetID].SupportedActions)) { + return XST_NO_FEATURE; + } + + /* + * @NOTE: + * This will always move to else part as GPO3 are ignored because + * XRESETPS_PMU_LCL_READ_CTRL is not accessible. + */ + /* GPO3PL have status address different from control address */ + if ((ResetID >= XRESETPS_RSTID_GPO3PL0) && + (ResetID <= XRESETPS_RSTID_GPO3PL31)) { + RegAddr = XRESETPS_PMU_LCL_READ_CTRL; + } else { + RegAddr = ResetMap[ResetID].SlcrregAddr; + } + + RegBitmask = ResetMap[ResetID].SlcrregBitmask; + + RegValue = XResetPs_ReadReg(RegAddr); + if ((RegValue & RegBitmask) == RegBitmask) { + *Status = XRESETPS_RESETASSERTED; + } else { + *Status = XRESETPS_RESETRELEASED; + } + + return XST_SUCCESS; +#endif +} + +/** @} */ diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/resetps_v1_0/src/xresetps.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/resetps_v1_0/src/xresetps.h new file mode 100644 index 000000000..f6a632b4e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/resetps_v1_0/src/xresetps.h @@ -0,0 +1,382 @@ +/****************************************************************************** +* +* Copyright (C) 2017 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xresetps.h +* @addtogroup xresetps_v1_0 +* @{ +* @details +* +* The Xilinx Reset Controller driver supports the following features: +* - Assert reset for specific peripheral. +* - Deassert reset for specific peripheral. +* - Pulse reset for specific peripheral. +* - Get reset status for specific peripheral. +* +* This driver is intended to be RTOS and processor independent. It works with +* physical addresses only. Any needs for dynamic memory management, threads +* or thread mutual exclusion, virtual memory, or cache control must be +* satisfied by the layer above this driver. +* +* 
+* MODIFICATION HISTORY:
+* Ver   Who    Date     Changes
+* ----- ------ -------- -----------------------------------------------
+* 1.00  cjp    09/05/17 First release
+*
+* +******************************************************************************/ +#ifndef XRESETPS_H /* prevent circular inclusions */ +#define XRESETPS_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ +#include "xil_types.h" +#include "xil_assert.h" +#include "xstatus.h" +#include "xresetps_hw.h" + +#if defined (__aarch64__) +#include "xil_smc.h" +#endif + +/************************** Constant Definitions *****************************/ +/* + * Constants for supported/Not supported reset actions + */ +#define XRESETPS_SUP 1 +#define XRESETPS_NOSUP 0 + +/**************************** Type Definitions *******************************/ +/** + * This typedef contains configuration information for the device. + */ +typedef struct { + u16 DeviceId; /**< Unique ID of device */ + u32 BaseAddress; /**< Base address of the device */ +} XResetPs_Config; + +/** + * The XResetPs driver instance data. The user is required to allocate a + * variable of this type for every reset controller device in the system. + * A pointer to a variable of this type is then passed to the driver API + * functions. + */ +typedef struct { + XResetPs_Config Config; /**< Hardware Configuration */ +} XResetPs; + +/** + * This typedef defines type of pulse reset to be executed for peripherals. + * 3 type of pulse reset are possible: + * 1. Pulse with no delay and no power state validation + * 2. Pulse with delay but no power state validation + * 3. Pulse with delay and power state validation + */ +typedef enum { + XRESETPS_PT_NO_DLY_NO_PSCHK, /**< No delay, no power state check */ + XRESETPS_PT_DLY_NO_PSCHK, /**< Delay, no power state check */ + XRESETPS_PT_DLY_PSCHK, /**< Delay, power state check */ + XRESETPS_PT_INVALID, /**< Invalid pulse type */ +} XResetPs_PulseTypes; + +/** + * This typedef defines reset actions on the peripherals. + */ +typedef enum { + XRESETPS_RSTACT_RELEASE, + XRESETPS_RSTACT_ASSERT, + XRESETPS_RSTACT_PULSE, +} XresetPs_ResetAction; + +/** + * This typedef defines resetIDs of peripherals maps to PMUFW resetIDs. This + * resetIDs are not offseted by 1000 and are relative. + */ +typedef enum { + XRESETPS_RSTID_START, + XRESETPS_RSTID_PCIE_CFG = XRESETPS_RSTID_START, + XRESETPS_RSTID_PCIE_BRIDGE, + XRESETPS_RSTID_PCIE_CTRL, + XRESETPS_RSTID_DP, + XRESETPS_RSTID_SWDT_CRF, + XRESETPS_RSTID_AFI_FM5, + XRESETPS_RSTID_AFI_FM4, + XRESETPS_RSTID_AFI_FM3, + XRESETPS_RSTID_AFI_FM2, + XRESETPS_RSTID_AFI_FM1, + XRESETPS_RSTID_AFI_FM0, + XRESETPS_RSTID_GDMA, + XRESETPS_RSTID_GPU_PP1, + XRESETPS_RSTID_GPU_PP0, + XRESETPS_RSTID_GPU, + XRESETPS_RSTID_GT, + XRESETPS_RSTID_SATA, + XRESETPS_RSTID_ACPU3_PWRON, + XRESETPS_RSTID_ACPU2_PWRON, + XRESETPS_RSTID_ACPU1_PWRON, + XRESETPS_RSTID_ACPU0_PWRON, + XRESETPS_RSTID_APU_L2, + XRESETPS_RSTID_ACPU3, + XRESETPS_RSTID_ACPU2, + XRESETPS_RSTID_ACPU1, + XRESETPS_RSTID_ACPU0, + XRESETPS_RSTID_DDR, + XRESETPS_RSTID_APM_FPD, + XRESETPS_RSTID_SOFT, + XRESETPS_RSTID_GEM0, + XRESETPS_RSTID_GEM1, + XRESETPS_RSTID_GEM2, + XRESETPS_RSTID_GEM3, + XRESETPS_RSTID_QSPI, + XRESETPS_RSTID_UART0, + XRESETPS_RSTID_UART1, + XRESETPS_RSTID_SPI0, + XRESETPS_RSTID_SPI1, + XRESETPS_RSTID_SDIO0, + XRESETPS_RSTID_SDIO1, + XRESETPS_RSTID_CAN0, + XRESETPS_RSTID_CAN1, + XRESETPS_RSTID_I2C0, + XRESETPS_RSTID_I2C1, + XRESETPS_RSTID_TTC0, + XRESETPS_RSTID_TTC1, + XRESETPS_RSTID_TTC2, + XRESETPS_RSTID_TTC3, + XRESETPS_RSTID_SWDT_CRL, + XRESETPS_RSTID_NAND, + XRESETPS_RSTID_ADMA, + XRESETPS_RSTID_GPIO, + XRESETPS_RSTID_IOU_CC, + XRESETPS_RSTID_TIMESTAMP, + XRESETPS_RSTID_RPU_R50, + XRESETPS_RSTID_RPU_R51, + XRESETPS_RSTID_RPU_AMBA, + XRESETPS_RSTID_OCM, + XRESETPS_RSTID_RPU_PGE, + XRESETPS_RSTID_USB0_CORERESET, + XRESETPS_RSTID_USB1_CORERESET, + XRESETPS_RSTID_USB0_HIBERRESET, + XRESETPS_RSTID_USB1_HIBERRESET, + XRESETPS_RSTID_USB0_APB, + XRESETPS_RSTID_USB1_APB, + XRESETPS_RSTID_IPI, + XRESETPS_RSTID_APM_LPD, + XRESETPS_RSTID_RTC, + XRESETPS_RSTID_SYSMON, + XRESETPS_RSTID_AFI_FM6, + XRESETPS_RSTID_LPD_SWDT, + XRESETPS_RSTID_FPD, + XRESETPS_RSTID_RPU_DBG1, + XRESETPS_RSTID_RPU_DBG0, + XRESETPS_RSTID_DBG_LPD, + XRESETPS_RSTID_DBG_FPD, + XRESETPS_RSTID_APLL, + XRESETPS_RSTID_DPLL, + XRESETPS_RSTID_VPLL, + XRESETPS_RSTID_IOPLL, + XRESETPS_RSTID_RPLL, + XRESETPS_RSTID_GPO3PL0, + XRESETPS_RSTID_GPO3PL1, + XRESETPS_RSTID_GPO3PL2, + XRESETPS_RSTID_GPO3PL3, + XRESETPS_RSTID_GPO3PL4, + XRESETPS_RSTID_GPO3PL5, + XRESETPS_RSTID_GPO3PL6, + XRESETPS_RSTID_GPO3PL7, + XRESETPS_RSTID_GPO3PL8, + XRESETPS_RSTID_GPO3PL9, + XRESETPS_RSTID_GPO3PL10, + XRESETPS_RSTID_GPO3PL11, + XRESETPS_RSTID_GPO3PL12, + XRESETPS_RSTID_GPO3PL13, + XRESETPS_RSTID_GPO3PL14, + XRESETPS_RSTID_GPO3PL15, + XRESETPS_RSTID_GPO3PL16, + XRESETPS_RSTID_GPO3PL17, + XRESETPS_RSTID_GPO3PL18, + XRESETPS_RSTID_GPO3PL19, + XRESETPS_RSTID_GPO3PL20, + XRESETPS_RSTID_GPO3PL21, + XRESETPS_RSTID_GPO3PL22, + XRESETPS_RSTID_GPO3PL23, + XRESETPS_RSTID_GPO3PL24, + XRESETPS_RSTID_GPO3PL25, + XRESETPS_RSTID_GPO3PL26, + XRESETPS_RSTID_GPO3PL27, + XRESETPS_RSTID_GPO3PL28, + XRESETPS_RSTID_GPO3PL29, + XRESETPS_RSTID_GPO3PL30, + XRESETPS_RSTID_GPO3PL31, + XRESETPS_RSTID_RPU_LS, + XRESETPS_RSTID_PS_ONLY, + XRESETPS_RSTID_PL, + XRESETPS_RSTID_END = XRESETPS_RSTID_PL, +} XResetPs_RstId; + +/** + * This typedef defines possible values for reset status of peripherals. + */ +typedef enum { + XRESETPS_RESETRELEASED, + XRESETPS_RESETASSERTED +} XResetPs_RstStatus; + +/***************** Macros (Inline Functions) Definitions *********************/ +/****************************************************************************/ +/** +* +* Set supported reset action. +* +* @param StatusSupport indicates if reset status check is supported +* @param PulseSupport indicates if pulse reset action is supported +* @param AssertSupport indicates if reset assert/deassert is supported +* +* @return Supported reset actions +* +* @note Here bit fields are used decide supported actions as defined +* below: +* BIT 1 - Assert/Deassert +* BIT 2 - Pulse +* BIT 3 - Reset status +* Bit set indicates corresponding action is supported and +* vice versa. +******************************************************************************/ +#define XRESETPS_SUPPORTED_ACT(ResetSupport, PulseSupport, AssertSupport) \ + ((ResetSupport << 2) | (PulseSupport << 1) | AssertSupport) + +/****************************************************************************/ +/** +* +* Check if assert/dessert reset is supported. +* +* @param Actions is supported reset actions +* +* @return 1 - Supported +* 0 - Not Supported +* +* @note None. +* +******************************************************************************/ +#define XRESETPS_CHK_ASSERT_SUPPORT(Actions) ((Actions & 0x1)) + +/****************************************************************************/ +/** +* +* Check if pulse reset is supported. +* +* @param Actions is supported reset actions +* +* @return 1 - Supported +* 0 - Not Supported +* +* @note None. +* +******************************************************************************/ +#define XRESETPS_CHK_PULSE_SUPPORT(Actions) ((Actions & 0x2) >> 1) + +/****************************************************************************/ +/** +* +* Check if Status check is supported. +* +* @param Actions is supported reset actions +* +* @return 1 - Supported +* 0 - Not Supported +* +* @note None. +* +******************************************************************************/ +#define XRESETPS_CHK_STATUS_SUPPORT(Actions) ((Actions & 0x4) >> 2) + +/****************************************************************************/ +/** +* +* Read the given register. +* +* @param RegAddress is the address of the register to read +* +* @return The 32-bit value of the register +* +* @note None. +* +******************************************************************************/ +#define XResetPs_ReadReg(RegAddress) \ + Xil_In32((u32)RegAddress) + +/****************************************************************************/ +/** +* +* Write the given register. +* +* @param RegAddress is the address of the register to write +* @param Data is the 32-bit value to write to the register +* +* @return None. +* +* @note None. +* +******************************************************************************/ +#define XResetPs_WriteReg(RegAddress, Data) \ + Xil_Out32((u32)RegAddress, (u32)Data) + +/************************** Function Prototypes ******************************/ + +/* + * Lookup configuration in xresetps_sinit.c. + */ +XResetPs_Config *XResetPs_LookupConfig(u16 DeviceId); + +/* + * Interface functions in xresetps.c + */ +XStatus XResetPs_CfgInitialize(XResetPs *InstancePtr, + XResetPs_Config *ConfigPtr, u32 EffectiveAddress); +XStatus XResetPs_ResetAssert(XResetPs *InstancePtr, + const XResetPs_RstId ResetID); +XStatus XResetPs_ResetDeassert(XResetPs *InstancePtr, + const XResetPs_RstId ResetID); +XStatus XResetPs_ResetPulse(XResetPs *InstancePtr, + const XResetPs_RstId ResetID); +XStatus XResetPs_ResetStatus(XResetPs *InstancePtr, + const XResetPs_RstId ResetID, XResetPs_RstStatus *Status); + +#ifdef __cplusplus +} +#endif +#endif /* end of protection macro */ +/** @} */ diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/resetps_v1_0/src/xresetps_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/resetps_v1_0/src/xresetps_g.c new file mode 100644 index 000000000..529215d65 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/resetps_v1_0/src/xresetps_g.c @@ -0,0 +1,53 @@ + +/******************************************************************* +* +* CAUTION: This file is automatically generated by HSI. +* Version: +* DO NOT EDIT. +* +* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.* +*Permission is hereby granted, free of charge, to any person obtaining a copy +*of this software and associated documentation files (the Software), to deal +*in the Software without restriction, including without limitation the rights +*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +*copies of the Software, and to permit persons to whom the Software is +*furnished to do so, subject to the following conditions: +* +*The above copyright notice and this permission notice shall be included in +*all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +*(a) running on a Xilinx device, or +*(b) that interact with a Xilinx device through a bus or interconnect. +* +*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +* +*Except as contained in this notice, the name of the Xilinx shall not be used +*in advertising or otherwise to promote the sale, use or other dealings in +*this Software without prior written authorization from Xilinx. +* + +* +* Description: Driver configuration +* +*******************************************************************/ + +#include "xparameters.h" +#include "xresetps.h" + +/* +* The configuration table for devices +*/ + +XResetPs_Config XResetPs_ConfigTable[XPAR_XRESETPS_NUM_INSTANCES] = +{ + { + XPAR_XRESETPS_DEVICE_ID, + XPAR_XRESETPS_BASEADDR, + } +}; diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/resetps_v1_0/src/xresetps_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/resetps_v1_0/src/xresetps_hw.h new file mode 100644 index 000000000..a97162d75 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/resetps_v1_0/src/xresetps_hw.h @@ -0,0 +1,327 @@ +/****************************************************************************** +* +* Copyright (C) 2017 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xresetps_hw.h +* @addtogroup xresetps_v1_0 +* @{ +* +* This file contains the hardware interface to the System Reset controller. +* +* 
+* MODIFICATION HISTORY:
+* Ver   Who    Date     Changes
+* ----- ------ -------- ---------------------------------------------
+* 1.00  cjp    09/05/17 First release
+*
+* +******************************************************************************/ +#ifndef XRESETPS_HW_H /* prevent circular inclusions */ +#define XRESETPS_HW_H /* by using protection macros */ + +/***************************** Include Files *********************************/ +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_io.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/************************** Constant Definitions *****************************/ +/* Register address defines */ +/* CRF_APB defines */ +#define XRESETPS_CRF_APB_BASE (0XFD1A0000U) +/* RST_FPD_TOP Address and mask definations */ +#define XRESETPS_CRF_APB_RST_FPD_TOP \ + ((XRESETPS_CRF_APB_BASE) + ((u32)0X00000100U)) +#define PCIE_CFG_RESET_MASK ((u32)0X00080000U) +#define PCIE_BRIDGE_RESET_MASK ((u32)0X00040000U) +#define PCIE_CTRL_RESET_MASK ((u32)0X00020000U) +#define DP_RESET_MASK ((u32)0X00010000U) +#define SWDT_RESET_MASK ((u32)0X00008000U) +#define AFI_FM5_RESET_MASK ((u32)0X00001000U) +#define AFI_FM4_RESET_MASK ((u32)0X00000800U) +#define AFI_FM3_RESET_MASK ((u32)0X00000400U) +#define AFI_FM2_RESET_MASK ((u32)0X00000200U) +#define AFI_FM1_RESET_MASK ((u32)0X00000100U) +#define AFI_FM0_RESET_MASK ((u32)0X00000080U) +#define GDMA_RESET_MASK ((u32)0X00000040U) +#define GPU_PP1_RESET_MASK ((u32)0X00000020U) +#define GPU_PP0_RESET_MASK ((u32)0X00000010U) +#define GPU_RESET_MASK ((u32)0X00000008U) +#define GT_RESET_MASK ((u32)0X00000004U) +#define SATA_RESET_MASK ((u32)0X00000002U) +/* RST_FPD_APU Address and mask definations */ +#define XRESETPS_CRF_APB_RST_FPD_APU \ + ((XRESETPS_CRF_APB_BASE) + ((u32)0X00000104U)) +#define ACPU3_PWRON_RESET_MASK ((u32)0X00002000U) +#define ACPU2_PWRON_RESET_MASK ((u32)0X00001000U) +#define ACPU1_PWRON_RESET_MASK ((u32)0X00000800U) +#define ACPU0_PWRON_RESET_MASK ((u32)0X00000400U) +#define APU_L2_RESET_MASK ((u32)0X00000100U) +#define ACPU3_RESET_MASK ((u32)0X00000008U) +#define ACPU2_RESET_MASK ((u32)0X00000004U) +#define ACPU1_RESET_MASK ((u32)0X00000002U) +#define ACPU0_RESET_MASK ((u32)0X00000001U) +/* RST_DDR_SS Address and mask definations */ +#define XRESETPS_CRF_APB_RST_DDR_SS \ + ((XRESETPS_CRF_APB_BASE) + ((u32)0X00000108U)) +#define DDR_RESET_MASK ((u32)0X00000008U) +#define DDR_APM_RESET_MASK ((u32)0X00000004U) +/* APLL_CTRL Address and mask definations */ +#define XRESETPS_CRF_APB_APLL_CTRL \ + ((XRESETPS_CRF_APB_BASE) + ((u32)0X00000020U)) +#define APLL_RESET_MASK ((u32)0X00000001U) +/* DPLL_CTRL Address and mask definations */ +#define XRESETPS_CRF_APB_DPLL_CTRL \ + ((XRESETPS_CRF_APB_BASE) + ((u32)0X0000002CU)) +#define DPLL_RESET_MASK ((u32)0X00000001U) +/* VPLL_CTRL Address and mask definations */ +#define XRESETPS_CRF_APB_VPLL_CTRL \ + ((XRESETPS_CRF_APB_BASE) + ((u32)0X00000038U)) +#define VPLL_RESET_MASK ((u32)0X00000001U) + +/* CRL_APB defines */ +#define XRESETPS_CRL_APB_BASE (0XFF5E0000U) +/* RESET_CTRL Address and mask definations */ +#define XRESETPS_CRL_APB_RESET_CTRL \ + ((XRESETPS_CRL_APB_BASE) + ((u32)0X00000218U)) +#define SOFT_RESET_MASK ((u32)0X00000010U) +/* RST_LPD_IOU0 Address and mask definations */ +#define XRESETPS_CRL_APB_RST_LPD_IOU0 \ + ((XRESETPS_CRL_APB_BASE) + ((u32)0X00000230U)) +#define GEM0_RESET_MASK ((u32)0X00000001U) +#define GEM1_RESET_MASK ((u32)0X00000002U) +#define GEM2_RESET_MASK ((u32)0X00000004U) +#define GEM3_RESET_MASK ((u32)0X00000008U) +/* RST_LPD_IOU2 Address and mask definations */ +#define XRESETPS_CRL_APB_RST_LPD_IOU2 \ + ((XRESETPS_CRL_APB_BASE) + ((u32)0X00000238U)) +#define QSPI_RESET_MASK ((u32)0X00000001U) +#define UART0_RESET_MASK ((u32)0X00000002U) +#define UART1_RESET_MASK ((u32)0X00000004U) +#define SPI0_RESET_MASK ((u32)0X00000008U) +#define SPI1_RESET_MASK ((u32)0X00000010U) +#define SDIO0_RESET_MASK ((u32)0X00000020U) +#define SDIO1_RESET_MASK ((u32)0X00000040U) +#define CAN0_RESET_MASK ((u32)0X00000080U) +#define CAN1_RESET_MASK ((u32)0X00000100U) +#define I2C0_RESET_MASK ((u32)0X00000200U) +#define I2C1_RESET_MASK ((u32)0X00000400U) +#define TTC0_RESET_MASK ((u32)0X00000800U) +#define TTC1_RESET_MASK ((u32)0X00001000U) +#define TTC2_RESET_MASK ((u32)0X00002000U) +#define TTC3_RESET_MASK ((u32)0X00004000U) +#define SWDT_RESET_MASK ((u32)0X00008000U) +#define NAND_RESET_MASK ((u32)0X00010000U) +#define ADMA_RESET_MASK ((u32)0X00020000U) +#define GPIO_RESET_MASK ((u32)0X00040000U) +#define IOU_CC_RESET_MASK ((u32)0X00080000U) +#define TIMESTAMP_RESET_MASK ((u32)0X00100000U) +/* RST_LPD_TOP Address and mask definations */ +#define XRESETPS_CRL_APB_RST_LPD_TOP \ + ((XRESETPS_CRL_APB_BASE) + ((u32)0X0000023CU)) +#define RPU_R50_RESET_MASK ((u32)0X00000001U) +#define RPU_R51_RESET_MASK ((u32)0X00000002U) +#define RPU_AMBA_RESET_MASK ((u32)0X00000004U) +#define OCM_RESET_MASK ((u32)0X00000008U) +#define RPU_PGE_RESET_MASK ((u32)0X00000010U) +#define USB0_CORERESET_MASK ((u32)0X00000040U) +#define USB1_CORERESET_MASK ((u32)0X00000080U) +#define USB0_HIBERRESET_MASK ((u32)0X00000100U) +#define USB1_HIBERRESET_MASK ((u32)0X00000200U) +#define USB0_APB_RESET_MASK ((u32)0X00000400U) +#define USB1_APB_RESET_MASK ((u32)0X00000800U) +#define IPI_RESET_MASK ((u32)0X00004000U) +#define APM_RESET_MASK ((u32)0X00008000U) +#define RTC_RESET_MASK ((u32)0X00010000U) +#define SYSMON_RESET_MASK ((u32)0X00020000U) +#define AFI_FM6_RESET_MASK ((u32)0X00080000U) +#define LPD_SWDT_RESET_MASK ((u32)0X00100000U) +#define FPD_RESET_MASK ((u32)0X00800000U) +/* RST_LPD_DBG Address and mask definations */ +#define XRESETPS_CRL_APB_RST_LPD_DBG \ + ((XRESETPS_CRL_APB_BASE) + ((u32)0X00000240U)) +#define RPU_DBG1_RESET_MASK ((u32)0X00000020U) +#define RPU_DBG0_RESET_MASK ((u32)0X00000010U) +#define DBG_LPD_RESET_MASK ((u32)0X00000002U) +#define DBG_FPD_RESET_MASK ((u32)0X00000001U) +/* IOPLL_CTRL Address and mask definations */ +#define XRESETPS_CRL_APB_IOPLL_CTRL \ + ((XRESETPS_CRL_APB_BASE) + ((u32)0X00000020U)) +#define IOPLL_RESET_MASK ((u32)0X00000001U) +/* RPLL_CTRL Address and mask definations */ +#define XRESETPS_CRL_APB_RPLL_CTRL \ + ((XRESETPS_CRL_APB_BASE) + ((u32)0X00000030U)) +#define RPLL_RESET_MASK ((u32)0X00000001U) +#define RPLL_BYPASS_MASK ((u32)0X00000008U) + +/* PMU_IOM defines */ +#define XRESETPS_PMU_IOM_BASE (0XFFD40000U) +/* PMU_IOM_GPO3 Address and mask definations */ +#define XRESETPS_PMU_IOM_GPO3_CTRL \ + ((XRESETPS_PMU_IOM_BASE) + ((u32)0X0000001CU)) +#define GPO3_PL0_RESET_MASK ((u32)0X00000001U) +#define GPO3_PL1_RESET_MASK ((u32)0X00000002U) +#define GPO3_PL2_RESET_MASK ((u32)0X00000004U) +#define GPO3_PL3_RESET_MASK ((u32)0X00000008U) +#define GPO3_PL4_RESET_MASK ((u32)0X00000010U) +#define GPO3_PL5_RESET_MASK ((u32)0X00000020U) +#define GPO3_PL6_RESET_MASK ((u32)0X00000040U) +#define GPO3_PL7_RESET_MASK ((u32)0X00000080U) +#define GPO3_PL8_RESET_MASK ((u32)0X00000100U) +#define GPO3_PL9_RESET_MASK ((u32)0X00000200U) +#define GPO3_PL10_RESET_MASK ((u32)0X00000400U) +#define GPO3_PL11_RESET_MASK ((u32)0X00000800U) +#define GPO3_PL12_RESET_MASK ((u32)0X00001000U) +#define GPO3_PL13_RESET_MASK ((u32)0X00002000U) +#define GPO3_PL14_RESET_MASK ((u32)0X00004000U) +#define GPO3_PL15_RESET_MASK ((u32)0X00008000U) +#define GPO3_PL16_RESET_MASK ((u32)0X00010000U) +#define GPO3_PL17_RESET_MASK ((u32)0X00020000U) +#define GPO3_PL18_RESET_MASK ((u32)0X00040000U) +#define GPO3_PL19_RESET_MASK ((u32)0X00080000U) +#define GPO3_PL20_RESET_MASK ((u32)0X00100000U) +#define GPO3_PL21_RESET_MASK ((u32)0X00200000U) +#define GPO3_PL22_RESET_MASK ((u32)0X00400000U) +#define GPO3_PL23_RESET_MASK ((u32)0X00800000U) +#define GPO3_PL24_RESET_MASK ((u32)0X01000000U) +#define GPO3_PL25_RESET_MASK ((u32)0X02000000U) +#define GPO3_PL26_RESET_MASK ((u32)0X04000000U) +#define GPO3_PL27_RESET_MASK ((u32)0X08000000U) +#define GPO3_PL28_RESET_MASK ((u32)0X10000000U) +#define GPO3_PL29_RESET_MASK ((u32)0X20000000U) +#define GPO3_PL30_RESET_MASK ((u32)0X40000000U) +#define GPO3_PL31_RESET_MASK ((u32)0X80000000U) + +/* PMU_LCL defines */ +#define XRESETPS_PMU_LCL_BASE (0XFFD60000U) +/* GPO Read control address */ +#define XRESETPS_PMU_LCL_READ_CTRL \ + ((XRESETPS_PMU_LCL_BASE) + ((u32)0X0000021CU)) + +/* PMU_GLB defines */ +#define XRESETPS_PMU_GLB_BASE (0XFFD80000U) +/* PMU_GLB_RST Address and mask definations */ +#define XRESETPS_PMU_GLB_RST_CTRL ((XRESETPS_PMU_GLB_BASE) + ((u32)0X00000608U)) +#define RPU_LS_RESET_MASK ((u32)0X00000100U) +#define FPD_APU_RESET_MASK ((u32)0X00000200U) +#define PS_ONLY_RESET_MASK ((u32)0X00000400U) +/* PMU_GLB_PS Address and mask definations */ +#define XRESETPS_PMU_GLB_PS_CTRL ((XRESETPS_PMU_GLB_BASE) + ((u32)0X00000004U)) +#define PROG_ENABLE_MASK ((u32)0X00000002U) +#define PROG_GATE_MASK ((u32)0X00000001U) +/* PMU_GLB_AIB Address and mask definations */ +#define XRESETPS_PMU_GLB_AIB_CTRL ((XRESETPS_PMU_GLB_BASE) + ((u32)0X00000600U)) +#define LPD_AFI_FM_ISO_MASK ((u32)0X00000001U) +#define LPD_AFI_FS_ISO_MASK ((u32)0X00000002U) +#define FPD_AFI_FM_ISO_MASK ((u32)0X00000004U) +#define FPD_AFI_FS_ISO_MASK ((u32)0X00000008U) +#define AIB_ISO_CTRL_MASK (LPD_AFI_FM_ISO_MASK | LPD_AFI_FS_ISO_MASK | \ + FPD_AFI_FM_ISO_MASK | FPD_AFI_FS_ISO_MASK) +/* PMU_GLB_AIB status Address and mask definations */ +#define XRESETPS_PMU_GLB_AIB_STATUS \ + ((XRESETPS_PMU_GLB_BASE) + ((u32)0X00000604U)) +#define AIB_ISO_STATUS_MASK (AIB_ISO_CTRL_MASK) +/* PMU_GLB_PWR status Address and mask definations */ +#define XRESETPS_PMU_GLB_PWR_STATUS \ + ((XRESETPS_PMU_GLB_BASE) + ((u32)0X00000100U)) +#define FPD_PSCHK_MASK ((u32)0x00400000U) +#define PCIE_CTRL_PSCHK_MASK (FPD_PSCHK_MASK) +#define DP_PSCHK_MASK (FPD_PSCHK_MASK) +#define SATA_PSCHK_MASK (FPD_PSCHK_MASK) +#define R50_PSCHK_MASK ((u32)0x00000400U) +#define R51_PSCHK_MASK ((u32)0x00000800U) +#define GPU_PP0_PSCHK_MASK (((u32)0x00000010U) | (FPD_PSCHK_MASK)) +#define GPU_PP1_PSCHK_MASK (((u32)0x00000020U) | (FPD_PSCHK_MASK)) +#define GPU_PSCHK_MASK ((GPU_PP0_PSCHK_MASK) | \ + (GPU_PP1_PSCHK_MASK) | (FPD_PSCHK_MASK)) + +/* LPD_SLCR defines */ +#define XRESETPS_LPD_SCR_BASE (0XFF410000U) +/* LPD_SCR_AXIISO_REQ and LPD_SCR_AXIISO_ACK Address and mask definations */ +#define XRESETPS_LPD_SCR_AXIISO_REQ_CTRL \ + ((XRESETPS_LPD_SCR_BASE) + ((u32)0X00003030U)) +#define XRESETPS_LPD_SCR_AXIISO_ACK_CTRL \ + ((XRESETPS_LPD_SCR_BASE) + ((u32)0X00003040U)) +#define RPU0_MASTER_ISO_MASK ((u32)0X00010000U) +#define RPU1_MASTER_ISO_MASK ((u32)0X00020000U) +#define RPU_MASTER_ISO_MASK (RPU0_MASTER_ISO_MASK | RPU1_MASTER_ISO_MASK) +#define RPU0_SLAVE_ISO_MASK ((u32)0X00040000U) +#define RPU1_SLAVE_ISO_MASK ((u32)0X00080000U) +#define RPU_SLAVE_ISO_MASK (RPU0_SLAVE_ISO_MASK | RPU1_SLAVE_ISO_MASK) +#define FPD_OCM_ISO_MASK ((u32)0X00000008U) +#define FPD_LPDIBS_ISO_MASK ((u32)0X00000004U) +#define AFIFS1_ISO_MASK ((u32)0X00000002U) +#define AFIFS0_ISO_MASK ((u32)0X00000001U) +#define FPD_TO_LPD_ISO_MASK (FPD_LPDIBS_ISO_MASK | FPD_OCM_ISO_MASK | \ + AFIFS0_ISO_MASK | AFIFS1_ISO_MASK) +#define LPD_DDR_ISO_MASK ((u32)0X08000000U) +#define FPD_MAIN_ISO_MASK ((u32)0X01000000U) +#define LPD_TO_FPD_ISO_MASK (LPD_DDR_ISO_MASK | FPD_MAIN_ISO_MASK) +/* LPD_SLCR_APBISO_REQ Address and mask definations */ +#define XRESETPS_LPD_SLCR_APBISO_REQ_CTRL \ + ((XRESETPS_LPD_SCR_BASE) + ((u32)0X00003048U)) +#define GPU_ISO_MASK ((u32)0X00000001U) + +/* CSU defines */ +#define XRESETPS_CSU_BASE (0xFFCA0000U) +#define XRESETPS_CSU_VERSION_REG ((XRESETPS_CSU_BASE) + ((u32)0x00000044U)) +#define XRESETPS_PLATFORM_PS_VER1 ((u32)0x00000000U) +#define PS_VERSION_MASK ((u32)0x0000000FU) + +/* Timeout delay defines */ +#define XRESETPS_RST_PROP_DELAY (0xFU) +#define XRESETPS_AIB_ISO_DELAY (0xFU) +#define XRESETPS_AIB_PSPL_DELAY (0xFU) +#define XRESETPS_PULSE_PROP_DELAY (0xFU) + +/* AIB ack reconfirmation count */ +#define XRESETPS_AIB_PSPL_RECONFIRM_CNT \ + (0x2U) + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ + + +/************************** Variable Definitions *****************************/ + +#ifdef __cplusplus +} +#endif +#endif /* end of protection macro */ +/** @} */ diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/resetps_v1_0/src/xresetps_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/resetps_v1_0/src/xresetps_sinit.c new file mode 100644 index 000000000..eebdc9d1c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/resetps_v1_0/src/xresetps_sinit.c @@ -0,0 +1,94 @@ +/****************************************************************************** +* +* Copyright (C) 2017 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xresetps_sinit.c +* @addtogroup xresetps_v1_0 +* @{ +* +* This file contains method for static initialization (compile-time) of the +* driver. +* +* 
+* MODIFICATION HISTORY:
+* Ver   Who    Date     Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00  cjp    09/05/17 First release
+*
+* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xresetps.h" +#include "xparameters.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + + +/***************** Macros (Inline Functions) Definitions *********************/ + +/*************************** Variable Definitions ****************************/ +extern XResetPs_Config XResetPs_ConfigTable[XPAR_XRESETPS_NUM_INSTANCES]; + +/************************** Function Prototypes ******************************/ + +/*****************************************************************************/ +/** +* Lookup the device configuration based on the unique device ID. The table +* contains the configuration info for each device in the system. +* +* @param DeviceId is the unique device ID of the device being looked up. +* +* @return A pointer to the configuration table entry corresponding to the +* given device ID, or NULL if no match is found. +* +* @note None. +* +******************************************************************************/ +XResetPs_Config *XResetPs_LookupConfig(u16 DeviceId) +{ + XResetPs_Config *CfgPtr = NULL; + u32 Index; + + for (Index = 0U; Index < (u32)XPAR_XRESETPS_NUM_INSTANCES; Index++) { + if (XResetPs_ConfigTable[Index].DeviceId == DeviceId) { + CfgPtr = &XResetPs_ConfigTable[Index]; + break; + } + } + return (XResetPs_Config *)CfgPtr; +} +/** @} */ diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_5/src/Makefile similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/Makefile rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_5/src/Makefile diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/rtcpsu_v1_3/src/xrtcpsu.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_5/src/xrtcpsu.c similarity index 96% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/rtcpsu_v1_3/src/xrtcpsu.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_5/src/xrtcpsu.c index c91f61279..c09d1e73c 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/rtcpsu_v1_3/src/xrtcpsu.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_5/src/xrtcpsu.c @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* Copyright (C) 2015 - 2017 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -18,8 +18,8 @@ * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. @@ -33,7 +33,7 @@ /** * * @file xrtcpsu.c -* @addtogroup rtcpsu_v1_0 +* @addtogroup rtcpsu_v1_5 * @{ * * Functions in this file are the minimum required functions for the XRtcPsu @@ -53,6 +53,8 @@ * 1.2 02/15/16 Corrected Calibration mask and Fractional * mask in CalculateCalibration API. * 1.3 vak 04/25/16 Corrected the RTC read and write time logic(cr#948833). +* 1.5 ms 08/27/17 Fixed compilation warnings. +* ms 08/29/17 Updated code as per source code style. * * ******************************************************************************/ @@ -166,7 +168,7 @@ s32 XRtcPsu_CfgInitialize(XRtcPsu *InstancePtr, XRtcPsu_Config *ConfigPtr, *****************************************************************************/ static void XRtcPsu_StubHandler(void *CallBackRef, u32 Event) { - (void *) CallBackRef; + (void) CallBackRef; (void) Event; /* Assert occurs always since this is a stub and should never be called */ Xil_AssertVoidAlways(); @@ -218,7 +220,9 @@ void XRtcPsu_SetTime(XRtcPsu *InstancePtr,u32 Time) *****************************************************************************/ u32 XRtcPsu_GetCurrentTime(XRtcPsu *InstancePtr) { - u32 Status, IntMask, CurrTime; + u32 Status; + u32 IntMask; + u32 CurrTime; IntMask = XRtcPsu_ReadReg(InstancePtr->RtcConfig.BaseAddr + XRTC_INT_MSK_OFFSET); @@ -294,9 +298,9 @@ void XRtcPsu_SetAlarm(XRtcPsu *InstancePtr, u32 Alarm, u32 Periodic) * format and saves it in the DT structure variable. It also reports the weekday. * * @param Seconds is the time value that has to be shown in DateTime -* format. +* format. * @param dt is the DateTime format variable that stores the translated -* time. +* time. * * @return None. * @@ -305,7 +309,10 @@ void XRtcPsu_SetAlarm(XRtcPsu *InstancePtr, u32 Alarm, u32 Periodic) *****************************************************************************/ void XRtcPsu_SecToDateTime(u32 Seconds, XRtcPsu_DT *dt) { - u32 CurrentTime, TempDays, Leap, DaysPerMonth; + u32 CurrentTime; + u32 TempDays; + u32 DaysPerMonth; + u32 Leap = 0U; CurrentTime = Seconds; dt->Sec = CurrentTime % 60U; @@ -364,7 +371,8 @@ void XRtcPsu_SecToDateTime(u32 Seconds, XRtcPsu_DT *dt) *****************************************************************************/ u32 XRtcPsu_DateTimeToSec(XRtcPsu_DT *dt) { - u32 i, Days; + u32 i; + u32 Days; u32 Seconds; Xil_AssertNonvoid(dt != NULL); @@ -414,8 +422,14 @@ u32 XRtcPsu_DateTimeToSec(XRtcPsu_DT *dt) void XRtcPsu_CalculateCalibration(XRtcPsu *InstancePtr,u32 TimeReal, u32 CrystalOscFreq) { - u32 ReadTime, SetTime; - u32 Cprev,Fprev,Cnew,Fnew,Xf,Calibration; + u32 ReadTime; + u32 SetTime; + u32 Cprev; + u32 Fprev; + u32 Cnew; + u32 Fnew; + u32 Calibration; + float Xf; Xil_AssertVoid(TimeReal != 0U); Xil_AssertVoid(CrystalOscFreq != 0U); diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/rtcpsu_v1_3/src/xrtcpsu.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_5/src/xrtcpsu.h similarity index 95% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/rtcpsu_v1_3/src/xrtcpsu.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_5/src/xrtcpsu.h index 164ddf64a..832047030 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/rtcpsu_v1_3/src/xrtcpsu.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_5/src/xrtcpsu.h @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* Copyright (C) 2015 - 2017 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -18,8 +18,8 @@ * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. @@ -32,7 +32,7 @@ /*****************************************************************************/ /** * @file xrtcpsu.h -* @addtogroup rtcpsu_v1_0 +* @addtogroup rtcpsu_v1_5 * @{ * @details * @@ -101,6 +101,14 @@ * 1.1 kvn 09/25/15 Modify control register to enable battery * switching when vcc_psaux is not available. * 1.3 vak 04/25/16 Corrected the RTC read and write time logic(cr#948833). +* 1.4 MNK 01/27/17 Corrected calibration and frequency macros based on +* rtc input oscillator frequency ( 32.768Khz). +* ms 03/17/17 Added readme.txt file in examples folder for doxygen +* generation. +* ms 04/10/17 Modified filename tag in examples to include them in +* doxygen examples. +* 1.5 ms 08/27/17 Fixed compilation warnings in xrtcpsu.c file. +* ms 08/29/17 Updated the code as per source code style. * * ******************************************************************************/ @@ -203,8 +211,8 @@ typedef struct { /***************** Macros (Inline Functions) Definitions *********************/ -#define XRTC_CALIBRATION_VALUE 0x00198231U -#define XRTC_TYPICAL_OSC_FREQ 33330U +#define XRTC_CALIBRATION_VALUE 0x8000U +#define XRTC_TYPICAL_OSC_FREQ 32768U /****************************************************************************/ /** diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_5/src/xrtcpsu_g.c similarity index 90% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu_g.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_5/src/xrtcpsu_g.c index 5913cd8d4..ef49025c7 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu_g.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_5/src/xrtcpsu_g.c @@ -5,7 +5,7 @@ * Version: * DO NOT EDIT. * -* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.* +* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.* *Permission is hereby granted, free of charge, to any person obtaining a copy *of this software and associated documentation files (the Software), to deal *in the Software without restriction, including without limitation the rights @@ -44,7 +44,7 @@ * The configuration table for devices */ -XRtcPsu_Config XRtcPsu_ConfigTable[] = +XRtcPsu_Config XRtcPsu_ConfigTable[XPAR_XRTCPSU_NUM_INSTANCES] = { { XPAR_PSU_RTC_DEVICE_ID, diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_5/src/xrtcpsu_hw.h similarity index 98% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu_hw.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_5/src/xrtcpsu_hw.h index 532ef7e3c..b535359eb 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu_hw.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_5/src/xrtcpsu_hw.h @@ -18,8 +18,8 @@ * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. @@ -33,7 +33,7 @@ /** * * @file xrtcpsu_hw.h -* @addtogroup rtcpsu_v1_0 +* @addtogroup rtcpsu_v1_5 * @{ * * This header file contains the identifiers and basic driver functions (or diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu_intr.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_5/src/xrtcpsu_intr.c similarity index 98% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu_intr.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_5/src/xrtcpsu_intr.c index 89d3cd990..1f5f831f7 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu_intr.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_5/src/xrtcpsu_intr.c @@ -18,8 +18,8 @@ * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. @@ -33,7 +33,7 @@ /** * * @file xrtcpsu_intr.c -* @addtogroup rtcpsu_v1_0 +* @addtogroup rtcpsu_v1_5 * @{ * * This file contains functions related to RTC interrupt handling. diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/rtcpsu_v1_3/src/xrtcpsu_selftest.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_5/src/xrtcpsu_selftest.c similarity index 97% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/rtcpsu_v1_3/src/xrtcpsu_selftest.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_5/src/xrtcpsu_selftest.c index 67c562c64..2678d8149 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/rtcpsu_v1_3/src/xrtcpsu_selftest.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_5/src/xrtcpsu_selftest.c @@ -18,8 +18,8 @@ * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. @@ -33,7 +33,7 @@ /** * * @file xrtcpsu_selftest.c -* @addtogroup rtcpsu_v1_0 +* @addtogroup rtcpsu_v1_5 * @{ * * This file contains the self-test functions for the XRtcPsu driver. diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_5/src/xrtcpsu_sinit.c similarity index 96% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu_sinit.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_5/src/xrtcpsu_sinit.c index d3a8b7dfc..32ea4e596 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_3/src/xrtcpsu_sinit.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_5/src/xrtcpsu_sinit.c @@ -18,8 +18,8 @@ * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. @@ -33,7 +33,7 @@ /** * * @file xrtcpsu_sinit.c -* @addtogroup rtcpsu_v1_0 +* @addtogroup rtcpsu_v1_5 * @{ * * This file contains the implementation of the XRtcPsu driver's static diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_9/src/Makefile similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/Makefile rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_9/src/Makefile diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scugic_v3_2/src/xscugic.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_9/src/xscugic.c similarity index 68% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scugic_v3_2/src/xscugic.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_9/src/xscugic.c index 1806274c7..f6afc0e5a 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scugic_v3_2/src/xscugic.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_9/src/xscugic.c @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* Copyright (C) 2010 - 2018 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -33,7 +33,7 @@ /** * * @file xscugic.c -* @addtogroup scugic_v3_1 +* @addtogroup scugic_v3_8 * @{ * * Contains required functions for the XScuGic driver for the Interrupt @@ -46,45 +46,78 @@ * ----- ---- -------- -------------------------------------------------------- * 1.00a drg 01/19/10 First release * 1.01a sdm 11/09/11 Changes are made in function XScuGic_CfgInitialize. Since -* "Config" entry is now made as pointer in the XScuGic -* structure, necessary changes are made. -* The HandlerTable can now be populated through the low -* level routine XScuGic_RegisterHandler added in this -* release. Hence necessary checks are added not to -* overwrite the HandlerTable entriesin function -* XScuGic_CfgInitialize. +* "Config" entry is now made as pointer in the XScuGic +* structure, necessary changes are made. +* The HandlerTable can now be populated through the low +* level routine XScuGic_RegisterHandler added in this +* release. Hence necessary checks are added not to +* overwrite the HandlerTable entriesin function +* XScuGic_CfgInitialize. * 1.03a srt 02/27/13 Added APIs -* - XScuGic_SetPriTrigTypeByDistAddr() -* - XScuGic_GetPriTrigTypeByDistAddr() -* Removed Offset calculation macros, defined in _hw.h -* (CR 702687) -* Added support to direct interrupts to the appropriate CPU. Earlier -* interrupts were directed to CPU1 (hard coded). Now depending -* upon the CPU selected by the user (xparameters.h), interrupts -* will be directed to the relevant CPU. This fixes CR 699688. +* - XScuGic_SetPriTrigTypeByDistAddr() +* - XScuGic_GetPriTrigTypeByDistAddr() +* Removed Offset calculation macros, defined in _hw.h +* (CR 702687) +* Added support to direct interrupts to the appropriate CPU. Earlier +* interrupts were directed to CPU1 (hard coded). Now depending +* upon the CPU selected by the user (xparameters.h), interrupts +* will be directed to the relevant CPU. This fixes CR 699688. * * 1.04a hk 05/04/13 Assigned EffectiveAddr to CpuBaseAddress in -* XScuGic_CfgInitialize. Fix for CR#704400 to remove warnings. -* Moved functions XScuGic_SetPriTrigTypeByDistAddr and -* XScuGic_GetPriTrigTypeByDistAddr to xscugic_hw.c. -* This is fix for CR#705621. +* XScuGic_CfgInitialize. Fix for CR#704400 to remove warnings. +* Moved functions XScuGic_SetPriTrigTypeByDistAddr and +* XScuGic_GetPriTrigTypeByDistAddr to xscugic_hw.c. +* This is fix for CR#705621. * 1.06a asa 16/11/13 Fix for CR#749178. Assignment for EffectiveAddr -* in function XScuGic_CfgInitialize is removed as it was -* a bug. +* in function XScuGic_CfgInitialize is removed as it was +* a bug. * 3.00 kvn 02/13/14 Modified code for MISRA-C:2012 compliance. * 3.01 pkp 06/19/15 Added XScuGic_InterruptMaptoCpu API for an interrupt -* target CPU mapping +* target CPU mapping * 3.02 pkp 11/09/15 Modified DistributorInit function for AMP case to add * the current cpu to interrupt processor targets registers * 3.2 asa 02/29/16 Modified DistributorInit function for Zynq AMP case. The -* distributor is left uninitialized for Zynq AMP. It is assumed -* that the distributor will be initialized by Linux master. However -* for CortexR5 case, the earlier code is left unchanged where the -* the interrupt processor target registers in the distributor is -* initialized with the corresponding CPU ID on which the application -* built over the scugic driver runs. -* These changes fix CR#937243. +* distributor is left uninitialized for Zynq AMP. It is assumed +* that the distributor will be initialized by Linux master. However +* for CortexR5 case, the earlier code is left unchanged where the +* the interrupt processor target registers in the distributor is +* initialized with the corresponding CPU ID on which the application +* built over the scugic driver runs. +* These changes fix CR#937243. +* 3.3 pkp 05/12/16 Modified XScuGic_InterruptMaptoCpu to write proper value +* to interrupt target register to fix CR#951848 * +* 3.4 asa 04/07/16 Created a new static function DoDistributorInit to simplify +* the flow and avoid code duplication. Changes are made for +* USE_AMP use case for R5. In a scenario (in R5 split mode) when +* one R5 is operating with A53 in open amp config and other +* R5 running baremetal app, the existing code +* had the potential to stop the whole AMP solution to work (if +* for some reason the R5 running the baremetal app tasked to +* initialize the Distributor hangs or crashes before initializing). +* Changes are made so that the R5 under AMP first checks if +* the distributor is enabled or not and if not, it does the +* standard Distributor initialization. +* This fixes the CR#952962. +* 3.4 mus 09/08/16 Added assert to avoid invalid access of GIC from CPUID 1 +* for single core zynq-7000s +* 3.5 mus 10/05/16 Modified DistributorInit function to avoid re-initialization of +* distributor,If it is already initialized by other CPU. +* 3.5 pkp 10/17/16 Modified XScuGic_InterruptMaptoCpu to correct the CPU Id value +* and properly mask interrupt target processor value to modify +* interrupt target processor register for a given interrupt ID +* and cpu ID +* 3.6 pkp 20/01/17 Added new API XScuGic_Stop to Disable distributor and +* interrupts in case they are being used only by current cpu. +* It also removes current cpu from interrupt target registers +* for all interrupts. +* kvn 02/17/17 Add support for changing GIC CPU master at run time. +* kvn 02/28/17 Make the CpuId as static variable and Added new +* XScugiC_GetCpuId to access CpuId. +* 3.9 mus 02/21/18 Added new API's XScuGic_UnmapAllInterruptsFromCpu and +* XScuGic_InterruptUnmapFromCpu, These API's can be used +* by applications to unmap specific/all interrupts from +* target CPU. It fixes CR#992490. * * * @@ -94,7 +127,6 @@ #include "xil_types.h" #include "xil_assert.h" #include "xscugic.h" -#include "xparameters.h" /************************** Constant Definitions *****************************/ @@ -105,6 +137,7 @@ /***************** Macros (Inline Functions) Definitions *********************/ /************************** Variable Definitions *****************************/ +static u32 CpuId = XPAR_CPU_ID; /**< CPU Core identifier */ /************************** Function Prototypes ******************************/ @@ -113,7 +146,7 @@ static void StubHandler(void *CallBackRef); /*****************************************************************************/ /** * -* DistributorInit initializes the distributor of the GIC. The +* DoDistributorInit initializes the distributor of the GIC. The * initialization entails: * * - Write the trigger mode, priority and target CPU @@ -128,35 +161,11 @@ static void StubHandler(void *CallBackRef); * @note None. * ******************************************************************************/ -static void DistributorInit(XScuGic *InstancePtr, u32 CpuID) +static void DoDistributorInit(XScuGic *InstancePtr, u32 CpuID) { u32 Int_Id; u32 LocalCpuID = CpuID; -#if USE_AMP==1 - #warning "Building GIC for AMP" -#ifdef ARMR5 - u32 RegValue; - - /* - * The overall distributor should not be initialized in AMP case where - * another CPU is taking care of it. - */ - LocalCpuID |= LocalCpuID << 8U; - LocalCpuID |= LocalCpuID << 16U; - for (Int_Id = 32U; Int_IdIsReady != XIL_COMPONENT_IS_READY) { - InstancePtr->IsReady = 0; + InstancePtr->IsReady = 0U; InstancePtr->Config = ConfigPtr; @@ -332,7 +403,7 @@ s32 XScuGic_CfgInitialize(XScuGic *InstancePtr, InstancePtr->Config->HandlerTable[Int_Id].CallBackRef = InstancePtr; } - + XScuGic_Stop(InstancePtr); DistributorInit(InstancePtr, Cpu_Id); CPUInitialize(InstancePtr); @@ -757,13 +828,193 @@ void XScuGic_InterruptMaptoCpu(XScuGic *InstancePtr, u8 Cpu_Id, u32 Int_Id) RegValue = XScuGic_DistReadReg(InstancePtr, XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id)); - Offset = (Int_Id & 0x3); + Offset = (Int_Id & 0x3U); + Cpu_Id = (0x1U << Cpu_Id); - RegValue = (RegValue | (~(0xFF << (Offset*8))) ); - RegValue |= ((Cpu_Id) << (Offset*8)); + RegValue = (RegValue & (~(0xFFU << (Offset*8U))) ); + RegValue |= ((Cpu_Id) << (Offset*8U)); XScuGic_DistWriteReg(InstancePtr, XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id), RegValue); } +/****************************************************************************/ +/** +* Unmaps specific SPI interrupt from the target CPU +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param Cpu_Id is a CPU number from which the interrupt has to be +* unmapped +* @param Int_Id is the IRQ source number to modify +* +* @return None. +* +* @note None +* +*****************************************************************************/ +void XScuGic_InterruptUnmapFromCpu(XScuGic *InstancePtr, u8 Cpu_Id, u32 Int_Id) +{ + u32 RegValue; + u8 BitPos; + + Xil_AssertVoid(InstancePtr != NULL); + + RegValue = XScuGic_DistReadReg(InstancePtr, + XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id)); + + /* + * Identify bit position corresponding to Int_Id and Cpu_Id, + * in interrupt target register and clear it + */ + BitPos = ((Int_Id % 4U) * 8U) + Cpu_Id; + RegValue &= (~ ( 1U << BitPos )); + XScuGic_DistWriteReg(InstancePtr, + XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id), + RegValue); +} +/****************************************************************************/ +/** +* Unmaps all SPI interrupts from the target CPU +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param Cpu_Id is a CPU number from which the interrupts has to be +* unmapped +* +* @return None. +* +* @note None +* +*****************************************************************************/ +void XScuGic_UnmapAllInterruptsFromCpu(XScuGic *InstancePtr, u8 Cpu_Id) +{ + u32 Int_Id; + u32 Target_Cpu; + u32 LocalCpuID = (1U << Cpu_Id); + + Xil_AssertVoid(InstancePtr != NULL); + + LocalCpuID |= LocalCpuID << 8U; + LocalCpuID |= LocalCpuID << 16U; + + for (Int_Id = 32U; Int_Id * ******************************************************************************/ @@ -166,7 +201,12 @@ extern "C" { /************************** Constant Definitions *****************************/ +#define EFUSE_STATUS_OFFSET 0x10 +#define EFUSE_STATUS_CPU_MASK 0x80 +#if !defined (ARMR5) && !defined (__aarch64__) && !defined (ARMA53_32) +#define ARMA9 +#endif /**************************** Type Definitions *******************************/ /* The following data type defines each entry in an interrupt vector table. @@ -304,6 +344,11 @@ void XScuGic_GetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id, void XScuGic_SetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id, u8 Priority, u8 Trigger); void XScuGic_InterruptMaptoCpu(XScuGic *InstancePtr, u8 Cpu_Id, u32 Int_Id); +void XScuGic_InterruptUnmapFromCpu(XScuGic *InstancePtr, u8 Cpu_Id, u32 Int_Id); +void XScuGic_UnmapAllInterruptsFromCpu(XScuGic *InstancePtr, u8 Cpu_Id); +void XScuGic_Stop(XScuGic *InstancePtr); +void XScuGic_SetCpuID(u32 CpuCoreId); +u32 XScuGic_GetCpuID(void); /* * Initialization functions in xscugic_sinit.c */ diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/xscugic_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_9/src/xscugic_g.c similarity index 87% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/xscugic_g.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_9/src/xscugic_g.c index 4bb186e5a..8bb1755ba 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_5/src/xscugic_g.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_9/src/xscugic_g.c @@ -5,7 +5,7 @@ * Version: * DO NOT EDIT. * -* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.* +* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.* *Permission is hereby granted, free of charge, to any person obtaining a copy *of this software and associated documentation files (the Software), to deal *in the Software without restriction, including without limitation the rights @@ -44,12 +44,13 @@ * The configuration table for devices */ -XScuGic_Config XScuGic_ConfigTable[] = +XScuGic_Config XScuGic_ConfigTable[XPAR_XSCUGIC_NUM_INSTANCES] = { { XPAR_PSU_RCPU_GIC_DEVICE_ID, XPAR_PSU_RCPU_GIC_BASEADDR, - XPAR_PSU_RCPU_GIC_DIST_BASEADDR + XPAR_PSU_RCPU_GIC_DIST_BASEADDR, + {{0}} /**< Initialize the HandlerTable to 0 */ } }; diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scugic_v3_2/src/xscugic_hw.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_9/src/xscugic_hw.c similarity index 88% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scugic_v3_2/src/xscugic_hw.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_9/src/xscugic_hw.c index 626779720..6604e3a55 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scugic_v3_2/src/xscugic_hw.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_9/src/xscugic_hw.c @@ -33,7 +33,7 @@ /** * * @file xscugic_hw.c -* @addtogroup scugic_v3_1 +* @addtogroup scugic_v3_8 * @{ * * This file contains low-level driver functions that can be used to access the @@ -62,6 +62,13 @@ * XScuGic_SetPriTrigTypeByDistAddr and * XScuGic_GetPriTrigTypeByDistAddr here from xscugic.c * 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance. +* 3.6 kvn 02/17/17 Add support for changing GIC CPU master at run time. +* kvn 02/28/17 Make the CpuId as static variable and Added new +* XScugiC_GetCpuId to access CpuId. +* 3.9 mus 02/21/18 Added new API's XScuGic_InterruptUnmapFromCpuByDistAddr +* and XScuGic_UnmapAllInterruptsFromCpuByDistAddr, These +* API's can be used by applications to unmap specific/all +* interrupts from target CPU. It fixes CR#992490. * * * @@ -90,6 +97,7 @@ static XScuGic_Config *LookupConfigByBaseAddress(u32 CpuBaseAddress); /************************** Variable Definitions *****************************/ extern XScuGic_Config XScuGic_ConfigTable[XPAR_XSCUGIC_NUM_INSTANCES]; +extern u32 CpuId; /*****************************************************************************/ /** @@ -274,7 +282,7 @@ static void CPUInit(XScuGic_Config *Config) s32 XScuGic_DeviceInitialize(u32 DeviceId) { XScuGic_Config *Config; - u32 Cpu_Id = (u32)XPAR_CPU_ID + (u32)1; + u32 Cpu_Id = XScuGic_GetCpuID() + (u32)1; Config = &XScuGic_ConfigTable[(u32 )DeviceId]; @@ -567,4 +575,75 @@ void XScuGic_GetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id, *Trigger = (u8)(RegValue & XSCUGIC_INT_CFG_MASK); } + +/****************************************************************************/ +/** +* Unmaps specific SPI interrupt from the target CPU +* +* @param DistBaseAddress is the device base address +* @param Cpu_Id is a CPU number from which the interrupt has to be +* unmapped +* @param Int_Id is the IRQ source number to modify +* +* @return None. +* +* @note None +* +*****************************************************************************/ +void XScuGic_InterruptUnmapFromCpuByDistAddr(u32 DistBaseAddress, + u8 Cpu_Id, u32 Int_Id) +{ + u32 RegValue; + u8 BitPos; + + Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS); + + RegValue = XScuGic_ReadReg(DistBaseAddress, + XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id)); + + /* + * Identify bit position corresponding to Int_Id and Cpu_Id, + * in interrupt target register and clear it + */ + BitPos = ((Int_Id % 4U) * 8U) + Cpu_Id; + RegValue &= (~ ( 1U << BitPos )); + XScuGic_WriteReg(DistBaseAddress, + XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id), RegValue); +} + +/****************************************************************************/ +/** +* Unmaps all SPI interrupts from the target CPU +* +* @param DistBaseAddress is the device base address +* @param Cpu_Id is a CPU number from which the interrupts has to be +* unmapped +* +* @return None. +* +* @note None +* +*****************************************************************************/ +void XScuGic_UnmapAllInterruptsFromCpuByDistAddr(u32 DistBaseAddress, + u8 Cpu_Id) +{ + u32 Int_Id; + u32 Target_Cpu; + u32 LocalCpuID = (1U << Cpu_Id); + + LocalCpuID |= LocalCpuID << 8U; + LocalCpuID |= LocalCpuID << 16U; + + for (Int_Id = 32U; Int_Id * ******************************************************************************/ @@ -633,6 +637,10 @@ void XScuGic_SetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id, u8 Priority, u8 Trigger); void XScuGic_GetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id, u8 *Priority, u8 *Trigger); +void XScuGic_InterruptUnmapFromCpuByDistAddr(u32 DistBaseAddress, + u8 Cpu_Id, u32 Int_Id); +void XScuGic_UnmapAllInterruptsFromCpuByDistAddr(u32 DistBaseAddress, + u8 Cpu_Id); /************************** Variable Definitions *****************************/ #ifdef __cplusplus } diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/scugic_v3_5/src/xscugic_intr.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_9/src/xscugic_intr.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/scugic_v3_5/src/xscugic_intr.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_9/src/xscugic_intr.c index d05a51c5e..d82a60b9e 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/scugic_v3_5/src/xscugic_intr.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_9/src/xscugic_intr.c @@ -33,7 +33,7 @@ /** * * @file xscugic_intr.c -* @addtogroup scugic_v3_1 +* @addtogroup scugic_v3_8 * @{ * * This file contains the interrupt processing for the driver for the Xilinx diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/scugic_v3_5/src/xscugic_selftest.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_9/src/xscugic_selftest.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/scugic_v3_5/src/xscugic_selftest.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_9/src/xscugic_selftest.c index 47620d644..7b1028f9f 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/scugic_v3_5/src/xscugic_selftest.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_9/src/xscugic_selftest.c @@ -33,7 +33,7 @@ /** * * @file xscugic_selftest.c -* @addtogroup scugic_v3_1 +* @addtogroup scugic_v3_8 * @{ * * Contains diagnostic self-test functions for the XScuGic driver. diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scugic_v3_2/src/xscugic_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_9/src/xscugic_sinit.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scugic_v3_2/src/xscugic_sinit.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_9/src/xscugic_sinit.c index d30390ab8..842f31812 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/scugic_v3_2/src/xscugic_sinit.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_9/src/xscugic_sinit.c @@ -33,7 +33,7 @@ /** * * @file xscugic_sinit.c -* @addtogroup scugic_v3_1 +* @addtogroup scugic_v3_8 * @{ * * Contains static init functions for the XScuGic driver for the Interrupt diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_1/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_4/src/Makefile similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_1/src/Makefile rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_4/src/Makefile diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/sdps_v2_7/src/xsdps.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_4/src/xsdps.c similarity index 73% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/sdps_v2_7/src/xsdps.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_4/src/xsdps.c index 6425a791b..65f1b2237 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/sdps_v2_7/src/xsdps.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_4/src/xsdps.c @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2013 - 2015 Xilinx, Inc. All rights reserved. +* Copyright (C) 2013 - 2016 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -33,7 +33,7 @@ /** * * @file xsdps.c -* @addtogroup sdps_v2_5 +* @addtogroup sdps_v3_4 * @{ * * Contains the interface functions of the XSdPs driver. @@ -64,28 +64,40 @@ * sk 12/10/15 Added support for MMC cards. * sk 02/16/16 Corrected the Tuning logic. * sk 03/01/16 Removed Bus Width check for eMMC. CR# 938311. +* 2.8 sk 05/03/16 Standard Speed for SD to 19MHz in ZynqMPSoC. CR#951024 +* 3.0 sk 06/09/16 Added support for mkfs to calculate sector count. +* sk 07/16/16 Added support for UHS modes. +* sk 07/07/16 Used usleep API for both arm and microblaze. +* sk 07/16/16 Added Tap delays accordingly to different SD/eMMC +* operating modes. +* 3.1 mi 09/07/16 Removed compilation warnings with extra compiler flags. +* sk 10/13/16 Reduced the delay during power cycle to 1ms as per spec +* sk 10/19/16 Used emmc_hwreset pin to reset eMMC. +* sk 11/07/16 Enable Rst_n bit in ext_csd reg if not enabled. +* 3.2 sk 11/30/16 Modified the voltage switching sequence as per spec. +* sk 02/01/17 Added HSD and DDR mode support for eMMC. +* vns 02/09/17 Added ARMA53_32 support for ZynqMP CR#968397 +* sk 03/20/17 Add support for EL1 non-secure mode. +* 3.3 mn 05/17/17 Add support for 64bit DMA addressing +* mn 07/17/17 Add support for running SD at 200MHz +* mn 07/26/17 Fixed compilation warnings +* mn 08/07/17 Modify driver to support 64-bit DMA in arm64 only +* mn 08/17/17 Added CCI support for A53 and disabled data cache +* operations when it is enabled. +* mn 08/22/17 Updated for Word Access System support +* mn 09/06/17 Resolved compilation errors with IAR toolchain +* mn 09/26/17 Added UHS_MODE_ENABLE macro to enable UHS mode +* 3.4 mn 10/17/17 Use different commands for single and multi block +* transfers +* mn 03/02/18 Move UHS macro check to SD card initialization routine * * ******************************************************************************/ /***************************** Include Files *********************************/ #include "xsdps.h" -/* - * The header sleep.h and API usleep() can only be used with an arm design. - * MB_Sleep() is used for microblaze design. - */ -#if defined (__arm__) || defined (__aarch64__) - #include "sleep.h" -#endif - -#ifdef __MICROBLAZE__ - -#include "microblaze_sleep.h" - -#endif - /************************** Constant Definitions *****************************/ #define XSDPS_CMD8_VOL_PATTERN 0x1AAU #define XSDPS_RESPOCR_READY 0x80000000U @@ -94,19 +106,23 @@ #define XSDPS_CMD1_HIGH_VOL 0x00FF8000U #define XSDPS_CMD1_DUAL_VOL 0x00FF8010U #define HIGH_SPEED_SUPPORT 0x2U +#define UHS_SDR50_SUPPORT 0x4U #define WIDTH_4_BIT_SUPPORT 0x4U #define SD_CLK_25_MHZ 25000000U +#define SD_CLK_19_MHZ 19000000U #define SD_CLK_26_MHZ 26000000U #define EXT_CSD_DEVICE_TYPE_BYTE 196U +#define EXT_CSD_SEC_COUNT_BYTE1 212U +#define EXT_CSD_SEC_COUNT_BYTE2 213U +#define EXT_CSD_SEC_COUNT_BYTE3 214U +#define EXT_CSD_SEC_COUNT_BYTE4 215U #define EXT_CSD_DEVICE_TYPE_HIGH_SPEED 0x2U #define EXT_CSD_DEVICE_TYPE_DDR_1V8_HIGH_SPEED 0x4U #define EXT_CSD_DEVICE_TYPE_DDR_1V2_HIGH_SPEED 0x8U #define EXT_CSD_DEVICE_TYPE_SDR_1V8_HS200 0x10U #define EXT_CSD_DEVICE_TYPE_SDR_1V2_HS200 0x20U #define CSD_SPEC_VER_3 0x3U - -/* Note: Remove this once fixed */ -#define UHS_BROKEN +#define SCR_SPEC_VER_3 0x80U /**************************** Type Definitions *******************************/ @@ -120,6 +136,7 @@ extern s32 XSdPs_Uhs_ModeInit(XSdPs *InstancePtr, u8 Mode); static s32 XSdPs_IdentifyCard(XSdPs *InstancePtr); static s32 XSdPs_Switch_Voltage(XSdPs *InstancePtr); +u16 TransferMode; /*****************************************************************************/ /** * @@ -163,28 +180,32 @@ s32 XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr, Xil_AssertNonvoid(ConfigPtr != NULL); /* Set some default values. */ + InstancePtr->Config.DeviceId = ConfigPtr->DeviceId; InstancePtr->Config.BaseAddress = EffectiveAddr; InstancePtr->Config.InputClockHz = ConfigPtr->InputClockHz; InstancePtr->IsReady = XIL_COMPONENT_IS_READY; InstancePtr->Config.CardDetect = ConfigPtr->CardDetect; InstancePtr->Config.WriteProtect = ConfigPtr->WriteProtect; + InstancePtr->Config.BusWidth = ConfigPtr->BusWidth; + InstancePtr->Config.BankNumber = ConfigPtr->BankNumber; + InstancePtr->Config.HasEMIO = ConfigPtr->HasEMIO; + InstancePtr->Config.IsCacheCoherent = ConfigPtr->IsCacheCoherent; + InstancePtr->SectorCount = 0; + InstancePtr->Mode = XSDPS_DEFAULT_SPEED_MODE; + InstancePtr->Config_TapDelay = NULL; - /* Disable bus power */ - XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, - XSDPS_POWER_CTRL_OFFSET, 0U); + /* Disable bus power and issue emmc hw reset */ + if ((XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_HOST_CTRL_VER_OFFSET) & XSDPS_HC_SPEC_VER_MASK) == + XSDPS_HC_SPEC_V3) + XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, + XSDPS_POWER_CTRL_OFFSET, XSDPS_PC_EMMC_HW_RST_MASK); + else + XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, + XSDPS_POWER_CTRL_OFFSET, 0x0); /* Delay to poweroff card */ -#if defined (__arm__) || defined (__aarch64__) - - (void)sleep(1U); - -#endif - -#ifdef __MICROBLAZE__ - - MB_Sleep(1000U); - -#endif + (void)usleep(1000U); /* "Software reset for all" is initiated */ XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, XSDPS_SW_RST_OFFSET, @@ -210,9 +231,21 @@ s32 XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr, XSDPS_CAPS_OFFSET); /* Select voltage and enable bus power. */ - XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, - XSDPS_POWER_CTRL_OFFSET, - XSDPS_PC_BUS_VSEL_3V3_MASK | XSDPS_PC_BUS_PWR_MASK); + if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) + XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, + XSDPS_POWER_CTRL_OFFSET, + (XSDPS_PC_BUS_VSEL_3V3_MASK | XSDPS_PC_BUS_PWR_MASK) & + ~XSDPS_PC_EMMC_HW_RST_MASK); + else + XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, + XSDPS_POWER_CTRL_OFFSET, + XSDPS_PC_BUS_VSEL_3V3_MASK | XSDPS_PC_BUS_PWR_MASK); + + /* Delay before issuing the command after emmc reset */ + if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) + if ((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK) == + XSDPS_CAPS_EMB_SLOT) + usleep(200); /* Change the clock frequency to 400 KHz */ Status = XSdPs_Change_ClkFreq(InstancePtr, XSDPS_CLK_400_KHZ); @@ -235,10 +268,18 @@ s32 XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr, XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, XSDPS_POWER_CTRL_OFFSET, PowerLevel | XSDPS_PC_BUS_PWR_MASK); + +#ifdef __aarch64__ /* Enable ADMA2 in 64bit mode. */ + XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, + XSDPS_HOST_CTRL1_OFFSET, + XSDPS_HC_DMA_ADMA2_64_MASK); +#else + /* Enable ADMA2 in 32bit mode. */ XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL1_OFFSET, XSDPS_HC_DMA_ADMA2_32_MASK); +#endif /* Enable all interrupt status except card interrupt initially */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, @@ -259,10 +300,8 @@ s32 XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr, * Transfer mode register - default value * DMA enabled, block count enabled, data direction card to host(read) */ - XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, - XSDPS_XFER_MODE_OFFSET, - XSDPS_TM_DMA_EN_MASK | XSDPS_TM_BLK_CNT_EN_MASK | - XSDPS_TM_DAT_DIR_SEL_MASK); + TransferMode = XSDPS_TM_DMA_EN_MASK | XSDPS_TM_BLK_CNT_EN_MASK | + XSDPS_TM_DAT_DIR_SEL_MASK; /* Set block size to 512 by default */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, @@ -308,10 +347,15 @@ s32 XSdPs_SdCardInitialize(XSdPs *InstancePtr) u32 CSD[4]; u32 Arg; u8 ReadReg; + u32 BlkLen, DeviceSize, Mult; Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); +#ifndef UHS_MODE_ENABLE + InstancePtr->Config.BusWidth = XSDPS_WIDTH_4; +#endif + if ((InstancePtr->HC_Version != XSDPS_HC_SPEC_V3) || ((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK) != XSDPS_CAPS_EMB_SLOT)) { @@ -379,9 +423,17 @@ s32 XSdPs_SdCardInitialize(XSdPs *InstancePtr) goto RETURN_PATH; } - Arg = XSDPS_ACMD41_HCS | XSDPS_ACMD41_3V3 | (0x1FFU << 15U); - if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) { - Arg |= XSDPS_OCR_S18; + Arg = XSDPS_ACMD41_HCS | XSDPS_ACMD41_3V3 | (0x1FFU << 15U); + /* + * There is no support to switch to 1.8V and use UHS mode on + * 1.0 silicon + */ + if ((InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) && +#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) || (PSU_PMU) + (XGetPSVersion_Info() > XPS_VERSION_1) && +#endif + (InstancePtr->Config.BusWidth == XSDPS_WIDTH_8)) { + Arg |= XSDPS_OCR_S18; } /* 0x40300000 - Host High Capacity support & 3.3V window */ @@ -403,18 +455,14 @@ s32 XSdPs_SdCardInitialize(XSdPs *InstancePtr) InstancePtr->HCS = 1U; } - /* There is no support to switch to 1.8V and use UHS mode on 1.0 silicon */ -#ifndef UHS_BROKEN - if ((RespOCR & XSDPS_OCR_S18) != 0U) { + if ((RespOCR & XSDPS_OCR_S18) != 0U) { InstancePtr->Switch1v8 = 1U; Status = XSdPs_Switch_Voltage(InstancePtr); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } - } -#endif /* CMD2 for Card ID */ Status = XSdPs_CmdTransfer(InstancePtr, CMD2, 0U, 0U); @@ -470,6 +518,19 @@ s32 XSdPs_SdCardInitialize(XSdPs *InstancePtr) CSD[3] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_RESP3_OFFSET); + if (((CSD[3] & CSD_STRUCT_MASK) >> 22U) == 0U) { + BlkLen = 1 << ((CSD[2] & READ_BLK_LEN_MASK) >> 8U); + Mult = 1 << (((CSD[1] & C_SIZE_MULT_MASK) >> 7U) + 2U); + DeviceSize = (CSD[1] & C_SIZE_LOWER_MASK) >> 22U; + DeviceSize |= (CSD[2] & C_SIZE_UPPER_MASK) << 10U; + DeviceSize = (DeviceSize + 1U) * Mult; + DeviceSize = DeviceSize * BlkLen; + InstancePtr->SectorCount = (DeviceSize/XSDPS_BLK_SIZE_512_MASK); + } else if (((CSD[3] & CSD_STRUCT_MASK) >> 22U) == 1U) { + InstancePtr->SectorCount = (((CSD[1] & CSD_V2_C_SIZE_MASK) >> 8U) + + 1U) * 1024U; + } + Status = XST_SUCCESS; RETURN_PATH: @@ -495,22 +556,20 @@ RETURN_PATH: * * ******************************************************************************/ -s32 XSdPs_CardInitialize(XSdPs *InstancePtr) { - u8 Tmp; - u32 Cnt; - u32 PresentStateReg; - u32 CtrlReg; - u32 CSD[4]; +s32 XSdPs_CardInitialize(XSdPs *InstancePtr) +{ #ifdef __ICCARM__ #pragma data_alignment = 32 -static u8 ExtCsd[512]; + static u8 ExtCsd[512]; + u8 SCR[8] = { 0U }; #pragma data_alignment = 4 #else -static u8 ExtCsd[512] __attribute__ ((aligned(32))); + static u8 ExtCsd[512] __attribute__ ((aligned(32))); + u8 SCR[8] __attribute__ ((aligned(32))) = { 0U }; #endif - u8 SCR[8] = { 0U }; u8 ReadBuff[64] = { 0U }; s32 Status; + u32 Arg; Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); @@ -547,7 +606,15 @@ static u8 ExtCsd[512] __attribute__ ((aligned(32))); } /* Change clock to default clock 25MHz */ - InstancePtr->BusSpeed = SD_CLK_25_MHZ; + /* + * SD default speed mode timing should be closed at 19 MHz. + * The reason for this is SD requires a voltage level shifter. + * This limitation applies to ZynqMPSoC. + */ + if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) + InstancePtr->BusSpeed = SD_CLK_19_MHZ; + else + InstancePtr->BusSpeed = SD_CLK_25_MHZ; Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed); if (Status != XST_SUCCESS) { Status = XST_FAILURE; @@ -601,33 +668,99 @@ static u8 ExtCsd[512] __attribute__ ((aligned(32))); } } - if ((InstancePtr->Switch1v8 != 0U) && - (InstancePtr->BusWidth == XSDPS_4_BIT_WIDTH)) { - /* Set UHS-I SDR104 mode */ - Status = XSdPs_Uhs_ModeInit(InstancePtr, - XSDPS_UHS_SPEED_MODE_SDR104); - if (Status != XST_SUCCESS) { + /* Get speed supported by device */ + Status = XSdPs_Get_BusSpeed(InstancePtr, ReadBuff); + if (Status != XST_SUCCESS) { + goto RETURN_PATH; + } + + if (((SCR[2] & SCR_SPEC_VER_3) != 0U) && + (ReadBuff[13] >= UHS_SDR50_SUPPORT) && + (InstancePtr->Config.BusWidth == XSDPS_WIDTH_8) && +#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) || (PSU_PMU) + (XGetPSVersion_Info() > XPS_VERSION_1) && +#endif + (InstancePtr->Switch1v8 == 0U)) { + u16 CtrlReg, ClockReg; + + /* Stop the clock */ + CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_CLK_CTRL_OFFSET); + CtrlReg &= ~(XSDPS_CC_SD_CLK_EN_MASK | XSDPS_CC_INT_CLK_EN_MASK); + XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_CLK_CTRL_OFFSET, + CtrlReg); + + /* Enabling 1.8V in controller */ + CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_HOST_CTRL2_OFFSET); + CtrlReg |= XSDPS_HC2_1V8_EN_MASK; + XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL2_OFFSET, + CtrlReg); + + /* Wait minimum 5mSec */ + (void)usleep(5000U); + + /* Check for 1.8V signal enable bit is cleared by Host */ + CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_HOST_CTRL2_OFFSET); + if ((CtrlReg & XSDPS_HC2_1V8_EN_MASK) == 0U) { Status = XST_FAILURE; goto RETURN_PATH; } - } else { + /* Wait for internal clock to stabilize */ + ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_CLK_CTRL_OFFSET); + XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, + XSDPS_CLK_CTRL_OFFSET, + ClockReg | XSDPS_CC_INT_CLK_EN_MASK); + ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_CLK_CTRL_OFFSET); + while((ClockReg & XSDPS_CC_INT_CLK_STABLE_MASK) == 0U) { + ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_CLK_CTRL_OFFSET); + } + /* Enable SD clock */ + ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_CLK_CTRL_OFFSET); + XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, + XSDPS_CLK_CTRL_OFFSET, + ClockReg | XSDPS_CC_SD_CLK_EN_MASK); + + /* Wait for 1mSec */ + (void)usleep(1000U); + + InstancePtr->Switch1v8 = 1U; + } + +#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) + if (InstancePtr->Switch1v8 != 0U) { + + /* Identify the UHS mode supported by card */ + XSdPs_Identify_UhsMode(InstancePtr, ReadBuff); + + /* Set UHS-I SDR104 mode */ + Status = XSdPs_Uhs_ModeInit(InstancePtr, InstancePtr->Mode); + if (Status != XST_SUCCESS) { + goto RETURN_PATH; + } + + } else { +#endif /* * card supports CMD6 when SD_SPEC field in SCR register * indicates that the Physical Layer Specification Version * is 1.10 or later. So for SD v1.0 cmd6 is not supported. */ if (SCR[0] != 0U) { - /* Get speed supported by device */ - Status = XSdPs_Get_BusSpeed(InstancePtr, ReadBuff); - if (Status != XST_SUCCESS) { - Status = XST_FAILURE; - goto RETURN_PATH; - } - /* Check for high speed support */ - if ((ReadBuff[13] & HIGH_SPEED_SUPPORT) != 0U) { + if (((ReadBuff[13] & HIGH_SPEED_SUPPORT) != 0U) && + (InstancePtr->BusWidth >= XSDPS_4_BIT_WIDTH)) { + InstancePtr->Mode = XSDPS_HIGH_SPEED_MODE; +#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) + InstancePtr->Config_TapDelay = XSdPs_hsd_sdr25_tapdelay; +#endif Status = XSdPs_Change_BusSpeed(InstancePtr); if (Status != XST_SUCCESS) { Status = XST_FAILURE; @@ -635,7 +768,9 @@ static u8 ExtCsd[512] __attribute__ ((aligned(32))); } } } +#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) } +#endif } else if (((InstancePtr->CardType == XSDPS_CARD_MMC) && (InstancePtr->Card_Version > CSD_SPEC_VER_3)) && @@ -653,8 +788,15 @@ static u8 ExtCsd[512] __attribute__ ((aligned(32))); goto RETURN_PATH; } - if ((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] & - EXT_CSD_DEVICE_TYPE_HIGH_SPEED) != 0U) { + InstancePtr->SectorCount = ((u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE4]) << 24; + InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE3] << 16; + InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE2] << 8; + InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE1]; + + if (((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] & + EXT_CSD_DEVICE_TYPE_HIGH_SPEED) != 0U) && + (InstancePtr->BusWidth >= XSDPS_4_BIT_WIDTH)) { + InstancePtr->Mode = XSDPS_HIGH_SPEED_MODE; Status = XSdPs_Change_BusSpeed(InstancePtr); if (Status != XST_SUCCESS) { Status = XST_FAILURE; @@ -687,9 +829,39 @@ static u8 ExtCsd[512] __attribute__ ((aligned(32))); goto RETURN_PATH; } - if ((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] & + InstancePtr->SectorCount = ((u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE4]) << 24; + InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE3] << 16; + InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE2] << 8; + InstancePtr->SectorCount |= (u32)ExtCsd[EXT_CSD_SEC_COUNT_BYTE1]; + + /* Check for card supported speed */ + if (((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] & (EXT_CSD_DEVICE_TYPE_SDR_1V8_HS200 | - EXT_CSD_DEVICE_TYPE_SDR_1V2_HS200)) != 0U) { + EXT_CSD_DEVICE_TYPE_SDR_1V2_HS200)) != 0U) && + (InstancePtr->BusWidth >= XSDPS_4_BIT_WIDTH)) { + InstancePtr->Mode = XSDPS_HS200_MODE; +#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) + InstancePtr->Config_TapDelay = XSdPs_sdr104_hs200_tapdelay; +#endif + } else if (((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] & + (EXT_CSD_DEVICE_TYPE_DDR_1V8_HIGH_SPEED | + EXT_CSD_DEVICE_TYPE_DDR_1V2_HIGH_SPEED)) != 0U) && + (InstancePtr->BusWidth >= XSDPS_4_BIT_WIDTH)) { + InstancePtr->Mode = XSDPS_DDR52_MODE; +#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) + InstancePtr->Config_TapDelay = XSdPs_ddr50_tapdelay; +#endif + } else if (((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] & + EXT_CSD_DEVICE_TYPE_HIGH_SPEED) != 0U) && + (InstancePtr->BusWidth >= XSDPS_4_BIT_WIDTH)) { + InstancePtr->Mode = XSDPS_HIGH_SPEED_MODE; +#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) + InstancePtr->Config_TapDelay = XSdPs_hsd_sdr25_tapdelay; +#endif + } else + InstancePtr->Mode = XSDPS_DEFAULT_SPEED_MODE; + + if (InstancePtr->Mode != XSDPS_DEFAULT_SPEED_MODE) { Status = XSdPs_Change_BusSpeed(InstancePtr); if (Status != XST_SUCCESS) { Status = XST_FAILURE; @@ -702,17 +874,47 @@ static u8 ExtCsd[512] __attribute__ ((aligned(32))); goto RETURN_PATH; } - if (ExtCsd[EXT_CSD_HS_TIMING_BYTE] != EXT_CSD_HS_TIMING_HS200) { + if (InstancePtr->Mode == XSDPS_HS200_MODE) { + if (ExtCsd[EXT_CSD_HS_TIMING_BYTE] != EXT_CSD_HS_TIMING_HS200) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + } + + if ((InstancePtr->Mode == XSDPS_HIGH_SPEED_MODE) || + InstancePtr->Mode == XSDPS_DDR52_MODE) { + if (ExtCsd[EXT_CSD_HS_TIMING_BYTE] != EXT_CSD_HS_TIMING_HIGH) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + + if (InstancePtr->Mode == XSDPS_DDR52_MODE) { + Status = XSdPs_Change_BusWidth(InstancePtr); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + } + } + } + + /* Enable Rst_n_Fun bit if it is disabled */ + if(ExtCsd[EXT_CSD_RST_N_FUN_BYTE] == EXT_CSD_RST_N_FUN_TEMP_DIS) { + Arg = XSDPS_MMC_RST_FUN_EN_ARG; + Status = XSdPs_Set_Mmc_ExtCsd(InstancePtr, Arg); + if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } } } - - Status = XSdPs_SetBlkSize(InstancePtr, XSDPS_BLK_SIZE_512_MASK); - if (Status != XST_SUCCESS) { - Status = XST_FAILURE; - goto RETURN_PATH; + if ((InstancePtr->Mode != XSDPS_DDR52_MODE) || + (InstancePtr->CardType == XSDPS_CARD_SD)) { + Status = XSdPs_SetBlkSize(InstancePtr, XSDPS_BLK_SIZE_512_MASK); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } } RETURN_PATH: @@ -731,26 +933,14 @@ RETURN_PATH: static s32 XSdPs_IdentifyCard(XSdPs *InstancePtr) { s32 Status; - u32 OperCondReg; u8 ReadReg; Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); /* 74 CLK delay after card is powered up, before the first command. */ -#if defined (__arm__) || defined (__aarch64__) - usleep(XSDPS_INIT_DELAY); -#endif - -#ifdef __MICROBLAZE__ - - /* 2 msec delay */ - MB_Sleep(2); - -#endif - /* CMD0 no response expected */ Status = XSdPs_CmdTransfer(InstancePtr, CMD0, 0U, 0U); if (Status != XST_SUCCESS) { @@ -803,7 +993,7 @@ static s32 XSdPs_Switch_Voltage(XSdPs *InstancePtr) { s32 Status; u16 CtrlReg; - u32 ReadReg; + u32 ReadReg, ClockReg; /* Send switch voltage command */ Status = XSdPs_CmdTransfer(InstancePtr, CMD11, 0U, 0U); @@ -827,19 +1017,6 @@ static s32 XSdPs_Switch_Voltage(XSdPs *InstancePtr) XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_CLK_CTRL_OFFSET, CtrlReg); - /* Wait minimum 5mSec */ -#if defined (__arm__) || defined (__aarch64__) - - (void)usleep(5000U); - -#endif - -#ifdef __MICROBLAZE__ - - MB_Sleep(5U); - -#endif - /* Enabling 1.8V in controller */ CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL2_OFFSET); @@ -847,13 +1024,40 @@ static s32 XSdPs_Switch_Voltage(XSdPs *InstancePtr) XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL2_OFFSET, CtrlReg); - /* Start clock */ - Status = XSdPs_Change_ClkFreq(InstancePtr, XSDPS_CLK_400_KHZ); - if (Status != XST_SUCCESS) { + /* Wait minimum 5mSec */ + (void)usleep(5000U); + + /* Check for 1.8V signal enable bit is cleared by Host */ + CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_HOST_CTRL2_OFFSET); + if ((CtrlReg & XSDPS_HC2_1V8_EN_MASK) == 0U) { Status = XST_FAILURE; goto RETURN_PATH; } + /* Wait for internal clock to stabilize */ + ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_CLK_CTRL_OFFSET); + XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, + XSDPS_CLK_CTRL_OFFSET, + ClockReg | XSDPS_CC_INT_CLK_EN_MASK); + ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_CLK_CTRL_OFFSET); + while((ClockReg & XSDPS_CC_INT_CLK_STABLE_MASK) == 0U) { + ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_CLK_CTRL_OFFSET); + } + + /* Enable SD clock */ + ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_CLK_CTRL_OFFSET); + XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, + XSDPS_CLK_CTRL_OFFSET, + ClockReg | XSDPS_CC_SD_CLK_EN_MASK); + + /* Wait for 1mSec */ + (void)usleep(1000U); + /* Wait for CMD and DATA line to go high */ ReadReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_PRES_STATE_OFFSET); @@ -945,8 +1149,8 @@ s32 XSdPs_CmdTransfer(XSdPs *InstancePtr, u32 Cmd, u32 Arg, u32 BlkCnt) } } - XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_CMD_OFFSET, - (u16)CommandReg); + XSdPs_WriteReg(InstancePtr->Config.BaseAddress, XSDPS_XFER_MODE_OFFSET, + (CommandReg << 16) | TransferMode); /* Polling for response for now */ do { @@ -1137,20 +1341,32 @@ s32 XSdPs_ReadPolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff) } XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, Buff); + if (InstancePtr->Config.IsCacheCoherent == 0) { + Xil_DCacheInvalidateRange((INTPTR)Buff, + BlkCnt * XSDPS_BLK_SIZE_512_MASK); + } - XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, - XSDPS_XFER_MODE_OFFSET, - XSDPS_TM_AUTO_CMD12_EN_MASK | + if (BlkCnt == 1U) { + TransferMode = XSDPS_TM_BLK_CNT_EN_MASK | + XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK; + + /* Send single block read command */ + Status = XSdPs_CmdTransfer(InstancePtr, CMD17, Arg, BlkCnt); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + } else { + TransferMode = XSDPS_TM_AUTO_CMD12_EN_MASK | XSDPS_TM_BLK_CNT_EN_MASK | XSDPS_TM_DAT_DIR_SEL_MASK | - XSDPS_TM_DMA_EN_MASK | XSDPS_TM_MUL_SIN_BLK_SEL_MASK); + XSDPS_TM_DMA_EN_MASK | XSDPS_TM_MUL_SIN_BLK_SEL_MASK; - Xil_DCacheInvalidateRange((INTPTR)Buff, BlkCnt * XSDPS_BLK_SIZE_512_MASK); - - /* Send block read command */ - Status = XSdPs_CmdTransfer(InstancePtr, CMD18, Arg, BlkCnt); - if (Status != XST_SUCCESS) { - Status = XST_FAILURE; - goto RETURN_PATH; + /* Send multiple blocks read command */ + Status = XSdPs_CmdTransfer(InstancePtr, CMD18, Arg, BlkCnt); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } } /* Check for transfer complete */ @@ -1228,19 +1444,31 @@ s32 XSdPs_WritePolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, const u8 *Buff) } XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, Buff); - Xil_DCacheFlushRange((INTPTR)Buff, BlkCnt * XSDPS_BLK_SIZE_512_MASK); + if (InstancePtr->Config.IsCacheCoherent == 0) { + Xil_DCacheFlushRange((INTPTR)Buff, + BlkCnt * XSDPS_BLK_SIZE_512_MASK); + } - XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, - XSDPS_XFER_MODE_OFFSET, - XSDPS_TM_AUTO_CMD12_EN_MASK | + if (BlkCnt == 1U) { + TransferMode = XSDPS_TM_BLK_CNT_EN_MASK | XSDPS_TM_DMA_EN_MASK; + + /* Send single block write command */ + Status = XSdPs_CmdTransfer(InstancePtr, CMD24, Arg, BlkCnt); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + } else { + TransferMode = XSDPS_TM_AUTO_CMD12_EN_MASK | XSDPS_TM_BLK_CNT_EN_MASK | - XSDPS_TM_MUL_SIN_BLK_SEL_MASK | XSDPS_TM_DMA_EN_MASK); + XSDPS_TM_MUL_SIN_BLK_SEL_MASK | XSDPS_TM_DMA_EN_MASK; - /* Send block write command */ - Status = XSdPs_CmdTransfer(InstancePtr, CMD25, Arg, BlkCnt); - if (Status != XST_SUCCESS) { - Status = XST_FAILURE; - goto RETURN_PATH; + /* Send multiple blocks write command */ + Status = XSdPs_CmdTransfer(InstancePtr, CMD25, Arg, BlkCnt); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } } /* @@ -1342,8 +1570,13 @@ void XSdPs_SetupADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff) } for (DescNum = 0U; DescNum < (TotalDescLines-1); DescNum++) { +#ifdef __aarch64__ + InstancePtr->Adma2_DescrTbl[DescNum].Address = + (u64)((UINTPTR)Buff + (DescNum*XSDPS_DESC_MAX_LENGTH)); +#else InstancePtr->Adma2_DescrTbl[DescNum].Address = (u32)((UINTPTR)Buff + (DescNum*XSDPS_DESC_MAX_LENGTH)); +#endif InstancePtr->Adma2_DescrTbl[DescNum].Attribute = XSDPS_DESC_TRAN | XSDPS_DESC_VALID; /* This will write '0' to length field which indicates 65536 */ @@ -1351,8 +1584,13 @@ void XSdPs_SetupADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff) (u16)XSDPS_DESC_MAX_LENGTH; } +#ifdef __aarch64__ + InstancePtr->Adma2_DescrTbl[TotalDescLines-1].Address = + (u64)((UINTPTR)Buff + (DescNum*XSDPS_DESC_MAX_LENGTH)); +#else InstancePtr->Adma2_DescrTbl[TotalDescLines-1].Address = (u32)((UINTPTR)Buff + (DescNum*XSDPS_DESC_MAX_LENGTH)); +#endif InstancePtr->Adma2_DescrTbl[TotalDescLines-1].Attribute = XSDPS_DESC_TRAN | XSDPS_DESC_END | XSDPS_DESC_VALID; @@ -1360,13 +1598,18 @@ void XSdPs_SetupADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff) InstancePtr->Adma2_DescrTbl[TotalDescLines-1].Length = (u16)((BlkCnt*BlkSize) - (DescNum*XSDPS_DESC_MAX_LENGTH)); +#ifdef __aarch64__ + XSdPs_WriteReg(InstancePtr->Config.BaseAddress, XSDPS_ADMA_SAR_EXT_OFFSET, + (u32)(((u64)&(InstancePtr->Adma2_DescrTbl[0]))>>32)); +#endif XSdPs_WriteReg(InstancePtr->Config.BaseAddress, XSDPS_ADMA_SAR_OFFSET, (u32)(UINTPTR)&(InstancePtr->Adma2_DescrTbl[0])); - Xil_DCacheFlushRange((INTPTR)&(InstancePtr->Adma2_DescrTbl[0]), + if (InstancePtr->Config.IsCacheCoherent == 0) { + Xil_DCacheFlushRange((INTPTR)&(InstancePtr->Adma2_DescrTbl[0]), sizeof(XSdPs_Adma2Descriptor) * 32U); - + } } /*****************************************************************************/ @@ -1398,6 +1641,7 @@ s32 XSdPs_MmcCardInitialize(XSdPs *InstancePtr) s32 Status; u32 RespOCR; u32 CSD[4]; + u32 BlkLen, DeviceSize, Mult; Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); @@ -1498,6 +1742,16 @@ s32 XSdPs_MmcCardInitialize(XSdPs *InstancePtr) InstancePtr->Card_Version = (CSD[3] & CSD_SPEC_VER_MASK) >>18U; + /* Calculating the memory capacity */ + BlkLen = 1 << ((CSD[2] & READ_BLK_LEN_MASK) >> 8U); + Mult = 1 << (((CSD[1] & C_SIZE_MULT_MASK) >> 7U) + 2U); + DeviceSize = (CSD[1] & C_SIZE_LOWER_MASK) >> 22U; + DeviceSize |= (CSD[2] & C_SIZE_UPPER_MASK) << 10U; + DeviceSize = (DeviceSize + 1U) * Mult; + DeviceSize = DeviceSize * BlkLen; + + InstancePtr->SectorCount = (DeviceSize/XSDPS_BLK_SIZE_512_MASK); + Status = XST_SUCCESS; RETURN_PATH: diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/sdps_v2_7/src/xsdps.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_4/src/xsdps.h similarity index 77% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/sdps_v2_7/src/xsdps.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_4/src/xsdps.h index 409653891..3f9ffd202 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/sdps_v2_7/src/xsdps.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_4/src/xsdps.h @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2013 - 2015 Xilinx, Inc. All rights reserved. +* Copyright (C) 2013 - 2016 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -33,7 +33,7 @@ /** * * @file xsdps.h -* @addtogroup sdps_v2_5 +* @addtogroup sdps_v3_4 * @{ * @details * @@ -125,6 +125,30 @@ * of SDR50, SDR104 and HS200. * sk 02/16/16 Corrected the Tuning logic. * sk 03/01/16 Removed Bus Width check for eMMC. CR# 938311. +* 2.8 sk 04/20/16 Added new workaround for auto tuning. +* 05/03/16 Standard Speed for SD to 19MHz in ZynqMPSoC. CR#951024 +* 3.0 sk 06/09/16 Added support for mkfs to calculate sector count. +* sk 07/16/16 Added support for UHS modes. +* sk 07/07/16 Used usleep API for both arm and microblaze. +* sk 07/16/16 Added Tap delays accordingly to different SD/eMMC +* operating modes. +* sk 08/13/16 Removed sleep.h from xsdps.h as a temporary fix for +* CR#956899. +* 3.1 mi 09/07/16 Removed compilation warnings with extra compiler flags. +* sk 10/13/16 Reduced the delay during power cycle to 1ms as per spec +* sk 10/19/16 Used emmc_hwreset pin to reset eMMC. +* sk 11/07/16 Enable Rst_n bit in ext_csd reg if not enabled. +* sk 11/16/16 Issue DLL reset at 31 iteration to load new zero value. +* 3.2 sk 11/30/16 Modified the voltage switching sequence as per spec. +* sk 02/01/17 Added HSD and DDR mode support for eMMC. +* sk 02/01/17 Consider bus width parameter from design for switching +* vns 02/09/17 Added ARMA53_32 support for ZynqMP CR#968397 +* sk 03/20/17 Add support for EL1 non-secure mode. +* 3.3 mn 05/17/17 Add support for 64bit DMA addressing +* mn 08/07/17 Modify driver to support 64-bit DMA in arm64 only +* mn 08/17/17 Enabled CCI support for A53 by adding cache coherency +* information. +* mn 09/06/17 Resolved compilation errors with IAR toolchain * * * @@ -142,6 +166,7 @@ extern "C" { #include "xil_cache.h" #include "xstatus.h" #include "xsdps_hw.h" +#include "xplatform_info.h" #include /************************** Constant Definitions *****************************/ @@ -150,6 +175,9 @@ extern "C" { #define MAX_TUNING_COUNT 40U /**< Maximum Tuning count */ /**************************** Type Definitions *******************************/ + +typedef void (*XSdPs_ConfigTap) (u32 Bank, u32 DeviceId, u32 CardType); + /** * This typedef contains configuration information for the device. */ @@ -159,14 +187,28 @@ typedef struct { u32 InputClockHz; /**< Input clock frequency */ u32 CardDetect; /**< Card Detect */ u32 WriteProtect; /**< Write Protect */ + u32 BusWidth; /**< Bus Width */ + u32 BankNumber; /**< MIO Bank selection for SD */ + u32 HasEMIO; /**< If SD is connected to EMIO */ + u8 IsCacheCoherent; /**< If SD is Cache Coherent or not */ } XSdPs_Config; /* ADMA2 descriptor table */ typedef struct { u16 Attribute; /**< Attributes of descriptor */ u16 Length; /**< Length of current dma transfer */ +#ifdef __aarch64__ + u64 Address; /**< Address of current dma transfer */ +#else u32 Address; /**< Address of current dma transfer */ +#endif +#ifdef __ICCARM__ +#pragma data_alignment = 32 } XSdPs_Adma2Descriptor; +#pragma data_alignment = 4 +#else +} __attribute__((__packed__))XSdPs_Adma2Descriptor; +#endif /** * The XSdPs driver instance data. The user is required to allocate a @@ -188,7 +230,10 @@ typedef struct { u32 CardID[4]; /**< Card ID Register */ u32 RelCardAddr; /**< Relative Card Address */ u32 CardSpecData[4]; /**< Card Specific Data Register */ + u32 SectorCount; /**< Sector Count */ u32 SdCardConfig; /**< Sd Card Configuration Register */ + u32 Mode; /**< Bus Speed Mode */ + XSdPs_ConfigTap Config_TapDelay; /**< Configuring the tap delays */ /**< ADMA Descriptors */ #ifdef __ICCARM__ #pragma data_alignment = 32 @@ -219,6 +264,13 @@ s32 XSdPs_Pullup(XSdPs *InstancePtr); s32 XSdPs_MmcCardInitialize(XSdPs *InstancePtr); s32 XSdPs_CardInitialize(XSdPs *InstancePtr); s32 XSdPs_Get_Mmc_ExtCsd(XSdPs *InstancePtr, u8 *ReadBuff); +s32 XSdPs_Set_Mmc_ExtCsd(XSdPs *InstancePtr, u32 Arg); +#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) +void XSdPs_Identify_UhsMode(XSdPs *InstancePtr, u8 *ReadBuff); +void XSdPs_ddr50_tapdelay(u32 Bank, u32 DeviceId, u32 CardType); +void XSdPs_hsd_sdr25_tapdelay(u32 Bank, u32 DeviceId, u32 CardType); +void XSdPs_sdr104_hs200_tapdelay(u32 Bank, u32 DeviceId, u32 CardType); +#endif #ifdef __cplusplus } diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_1/src/xsdps_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_4/src/xsdps_g.c similarity index 89% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_1/src/xsdps_g.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_4/src/xsdps_g.c index 72981b551..de9be71b8 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_1/src/xsdps_g.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_4/src/xsdps_g.c @@ -5,7 +5,7 @@ * Version: * DO NOT EDIT. * -* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.* +* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.* *Permission is hereby granted, free of charge, to any person obtaining a copy *of this software and associated documentation files (the Software), to deal *in the Software without restriction, including without limitation the rights @@ -44,7 +44,7 @@ * The configuration table for devices */ -XSdPs_Config XSdPs_ConfigTable[] = +XSdPs_Config XSdPs_ConfigTable[XPAR_XSDPS_NUM_INSTANCES] = { { XPAR_PSU_SD_1_DEVICE_ID, @@ -54,7 +54,8 @@ XSdPs_Config XSdPs_ConfigTable[] = XPAR_PSU_SD_1_HAS_WP, XPAR_PSU_SD_1_BUS_WIDTH, XPAR_PSU_SD_1_MIO_BANK, - XPAR_PSU_SD_1_HAS_EMIO + XPAR_PSU_SD_1_HAS_EMIO, + XPAR_PSU_SD_1_IS_CACHE_COHERENT } }; diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/sdps_v2_7/src/xsdps_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_4/src/xsdps_hw.h similarity index 90% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/sdps_v2_7/src/xsdps_hw.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_4/src/xsdps_hw.h index c797e8216..8d190efa0 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/sdps_v2_7/src/xsdps_hw.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_4/src/xsdps_hw.h @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2013 - 2015 Xilinx, Inc. All rights reserved. +* Copyright (C) 2013 - 2016 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -33,7 +33,7 @@ /** * * @file xsdps_hw.h -* @addtogroup sdps_v2_5 +* @addtogroup sdps_v3_4 * @{ * * This header file contains the identifiers and basic HW access driver @@ -50,6 +50,17 @@ * kvn 07/15/15 Modified the code according to MISRAC-2012. * 2.7 sk 12/10/15 Added support for MMC cards. * sk 03/02/16 Configured the Tap Delay values for eMMC HS200 mode. +* 2.8 sk 04/20/16 Added new workaround for auto tuning. +* 3.0 sk 06/09/16 Added support for mkfs to calculate sector count. +* sk 07/16/16 Added support for UHS modes. +* sk 07/16/16 Added Tap delays accordingly to different SD/eMMC +* operating modes. +* 3.1 sk 11/07/16 Enable Rst_n bit in ext_csd reg if not enabled. +* 3.2 sk 03/20/17 Add support for EL1 non-secure mode. +* 3.3 mn 08/22/17 Updated for Word Access System support +* mn 09/06/17 Added support for ARMCC toolchain +* 3.4 mn 01/22/18 Separated out SDR104 and HS200 clock defines +* * * ******************************************************************************/ @@ -796,6 +807,12 @@ extern "C" { #define XSDPS_CUR_LIM_800 3U #define CSD_SPEC_VER_MASK 0x3C0000U +#define READ_BLK_LEN_MASK 0x00000F00U +#define C_SIZE_MULT_MASK 0x00000380U +#define C_SIZE_LOWER_MASK 0xFFC00000U +#define C_SIZE_UPPER_MASK 0x00000003U +#define CSD_STRUCT_MASK 0x00C00000U +#define CSD_V2_C_SIZE_MASK 0x3FFFFF00U /* EXT_CSD field definitions */ #define XSDPS_EXT_CSD_SIZE 512U @@ -842,6 +859,10 @@ extern "C" { #define EXT_CSD_HS_TIMING_HIGH 1U /* Card is in high speed mode */ #define EXT_CSD_HS_TIMING_HS200 2U /* Card is in HS200 mode */ +#define EXT_CSD_RST_N_FUN_BYTE 162U +#define EXT_CSD_RST_N_FUN_TEMP_DIS 0U /* RST_n signal is temporarily disabled */ +#define EXT_CSD_RST_N_FUN_PERM_EN 1U /* RST_n signal is permanently enabled */ +#define EXT_CSD_RST_N_FUN_PERM_DIS 2U /* RST_n signal is permanently disabled */ #define XSDPS_EXT_CSD_CMD_SET 0U #define XSDPS_EXT_CSD_SET_BITS 1U @@ -880,6 +901,10 @@ extern "C" { | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \ | ((u32)EXT_CSD_BUS_WIDTH_DDR_8_BIT << 8)) +#define XSDPS_MMC_RST_FUN_EN_ARG (((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \ + | ((u32)EXT_CSD_RST_N_FUN_BYTE << 16) \ + | ((u32)EXT_CSD_RST_N_FUN_PERM_EN << 8)) + #define XSDPS_MMC_DELAY_FOR_SWITCH 1000U /* @} */ @@ -930,6 +955,10 @@ extern "C" { #define XSDPS_UHS_SPEED_MODE_SDR50 0x2U #define XSDPS_UHS_SPEED_MODE_SDR104 0x3U #define XSDPS_UHS_SPEED_MODE_DDR50 0x4U +#define XSDPS_HIGH_SPEED_MODE 0x5U +#define XSDPS_DEFAULT_SPEED_MODE 0x6U +#define XSDPS_HS200_MODE 0x7U +#define XSDPS_DDR52_MODE 0x4U #define XSDPS_SWITCH_CMD_BLKCNT 1U #define XSDPS_SWITCH_CMD_BLKSIZE 64U #define XSDPS_SWITCH_CMD_HS_GET 0x00FFFFF0U @@ -970,7 +999,16 @@ extern "C" { #define XSDPS_SD_SDR50_MAX_CLK 100000000U #define XSDPS_SD_DDR50_MAX_CLK 50000000U #define XSDPS_SD_SDR104_MAX_CLK 208000000U +/* + * XSDPS_SD_INPUT_MAX_CLK is set to 175000000 in order to keep it smaller + * than the clock value coming from the core. This value is kept to safely + * switch to SDR104 mode if the SD card supports it. + */ +#define XSDPS_SD_INPUT_MAX_CLK 175000000U + #define XSDPS_MMC_HS200_MAX_CLK 200000000U +#define XSDPS_MMC_HSD_MAX_CLK 52000000U +#define XSDPS_MMC_DDR_MAX_CLK 52000000U #define XSDPS_CARD_STATE_IDLE 0U #define XSDPS_CARD_STATE_RDY 1U @@ -987,15 +1025,51 @@ extern "C" { #define XSDPS_SLOT_REM 0U #define XSDPS_SLOT_EMB 1U -#if defined (__arm__) || defined (__aarch64__) -#define SD_DLL_CTRL 0x00000358U -#define SD_ITAPDLY 0x00000314U -#define SD_OTAPDLYSEL 0x00000318U -#define SD0_DLL_RST 0x00000004U -#define SD0_ITAPCHGWIN 0x00000200U -#define SD0_ITAPDLYENA 0x00000100U -#define SD0_OTAPDLYENA 0x00000040U -#define SD0_OTAPDLYSEL_HS200 0x00000003U +#define XSDPS_WIDTH_8 8U +#define XSDPS_WIDTH_4 4U + + +#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) +#define SD0_ITAPDLY_SEL_MASK 0x000000FFU +#define SD0_OTAPDLY_SEL_MASK 0x0000003FU +#define SD1_ITAPDLY_SEL_MASK 0x00FF0000U +#define SD1_OTAPDLY_SEL_MASK 0x003F0000U +#define SD_DLL_CTRL 0x00000358U +#define SD_ITAPDLY 0x00000314U +#define SD_OTAPDLY 0x00000318U +#define SD0_DLL_RST 0x00000004U +#define SD1_DLL_RST 0x00040000U +#define SD0_ITAPCHGWIN 0x00000200U +#define SD0_ITAPDLYENA 0x00000100U +#define SD0_OTAPDLYENA 0x00000040U +#define SD1_ITAPCHGWIN 0x02000000U +#define SD1_ITAPDLYENA 0x01000000U +#define SD1_OTAPDLYENA 0x00400000U + +#define SD0_OTAPDLYSEL_HS200_B0 0x00000003U +#define SD0_OTAPDLYSEL_HS200_B2 0x00000002U +#define SD0_ITAPDLYSEL_SD50 0x00000014U +#define SD0_OTAPDLYSEL_SD50 0x00000003U +#define SD0_ITAPDLYSEL_SD_DDR50 0x0000003DU +#define SD0_ITAPDLYSEL_EMMC_DDR50 0x00000012U +#define SD0_OTAPDLYSEL_SD_DDR50 0x00000004U +#define SD0_OTAPDLYSEL_EMMC_DDR50 0x00000006U +#define SD0_ITAPDLYSEL_HSD 0x00000015U +#define SD0_OTAPDLYSEL_SD_HSD 0x00000005U +#define SD0_OTAPDLYSEL_EMMC_HSD 0x00000006U + +#define SD1_OTAPDLYSEL_HS200_B0 0x00030000U +#define SD1_OTAPDLYSEL_HS200_B2 0x00020000U +#define SD1_ITAPDLYSEL_SD50 0x00140000U +#define SD1_OTAPDLYSEL_SD50 0x00030000U +#define SD1_ITAPDLYSEL_SD_DDR50 0x003D0000U +#define SD1_ITAPDLYSEL_EMMC_DDR50 0x00120000U +#define SD1_OTAPDLYSEL_SD_DDR50 0x00040000U +#define SD1_OTAPDLYSEL_EMMC_DDR50 0x00060000U +#define SD1_ITAPDLYSEL_HSD 0x00150000U +#define SD1_OTAPDLYSEL_SD_HSD 0x00050000U +#define SD1_OTAPDLYSEL_EMMC_HSD 0x00060000U + #endif /**************************** Type Definitions *******************************/ @@ -1100,8 +1174,18 @@ extern "C" { * u16 XSdPs_ReadReg(u32 BaseAddress. int RegOffset) * ******************************************************************************/ -#define XSdPs_ReadReg16(BaseAddress, RegOffset) \ - XSdPs_In16((BaseAddress) + (RegOffset)) +static INLINE u16 XSdPs_ReadReg16(u32 BaseAddress, u8 RegOffset) +{ +#if defined (__MICROBLAZE__) + u32 Reg; + BaseAddress += RegOffset & 0xFC; + Reg = XSdPs_In32(BaseAddress); + Reg >>= ((RegOffset & 0x3)*8); + return (u16)Reg; +#else + return XSdPs_In16((BaseAddress) + (RegOffset)); +#endif +} /***************************************************************************/ /** @@ -1119,8 +1203,20 @@ extern "C" { * u16 RegisterValue) * ******************************************************************************/ -#define XSdPs_WriteReg16(BaseAddress, RegOffset, RegisterValue) \ - XSdPs_Out16((BaseAddress) + (RegOffset), (RegisterValue)) + +static INLINE void XSdPs_WriteReg16(u32 BaseAddress, u8 RegOffset, u16 RegisterValue) +{ +#if defined (__MICROBLAZE__) + u32 Reg; + BaseAddress += RegOffset & 0xFC; + Reg = XSdPs_In32(BaseAddress); + Reg &= ~(0xFFFF<<((RegOffset & 0x3)*8)); + Reg |= RegisterValue <<((RegOffset & 0x3)*8); + XSdPs_Out32(BaseAddress, Reg); +#else + XSdPs_Out16((BaseAddress) + (RegOffset), (RegisterValue)); +#endif +} /****************************************************************************/ /** @@ -1136,9 +1232,18 @@ extern "C" { * u8 XSdPs_ReadReg(u32 BaseAddress. int RegOffset) * ******************************************************************************/ -#define XSdPs_ReadReg8(BaseAddress, RegOffset) \ - XSdPs_In8((BaseAddress) + (RegOffset)) - +static INLINE u8 XSdPs_ReadReg8(u32 BaseAddress, u8 RegOffset) +{ +#if defined (__MICROBLAZE__) + u32 Reg; + BaseAddress += RegOffset & 0xFC; + Reg = XSdPs_In32(BaseAddress); + Reg >>= ((RegOffset & 0x3)*8); + return (u8)Reg; +#else + return XSdPs_In8((BaseAddress) + (RegOffset)); +#endif +} /***************************************************************************/ /** * Write to a register. @@ -1155,9 +1260,19 @@ extern "C" { * u8 RegisterValue) * ******************************************************************************/ -#define XSdPs_WriteReg8(BaseAddress, RegOffset, RegisterValue) \ - XSdPs_Out8((BaseAddress) + (RegOffset), (RegisterValue)) - +static INLINE void XSdPs_WriteReg8(u32 BaseAddress, u8 RegOffset, u8 RegisterValue) +{ +#if defined (__MICROBLAZE__) + u32 Reg; + BaseAddress += RegOffset & 0xFC; + Reg = XSdPs_In32(BaseAddress); + Reg &= ~(0xFF<<((RegOffset & 0x3)*8)); + Reg |= RegisterValue <<((RegOffset & 0x3)*8); + XSdPs_Out32(BaseAddress, Reg); +#else + XSdPs_Out8((BaseAddress) + (RegOffset), (RegisterValue)); +#endif +} /***************************************************************************/ /** * Macro to get present status register diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/sdps_v2_7/src/xsdps_options.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_4/src/xsdps_options.c similarity index 52% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/sdps_v2_7/src/xsdps_options.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_4/src/xsdps_options.c index 8151eef1b..bcd7c689b 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/sdps_v2_7/src/xsdps_options.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_4/src/xsdps_options.c @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2013 - 2015 Xilinx, Inc. All rights reserved. +* Copyright (C) 2013 - 2016 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -33,7 +33,7 @@ /** * * @file xsdps_options.c -* @addtogroup sdps_v2_5 +* @addtogroup sdps_v3_4 * @{ * * Contains API's for changing the various options in host and card. @@ -55,6 +55,26 @@ * of SDR50, SDR104 and HS200. * sk 02/16/16 Corrected the Tuning logic. * sk 03/02/16 Configured the Tap Delay values for eMMC HS200 mode. +* 2.8 sk 04/20/16 Added new workaround for auto tuning. +* 3.0 sk 07/07/16 Used usleep API for both arm and microblaze. +* sk 07/16/16 Added support for UHS modes. +* sk 07/16/16 Added Tap delays accordingly to different SD/eMMC +* operating modes. +* 3.1 mi 09/07/16 Removed compilation warnings with extra compiler flags. +* sk 11/07/16 Enable Rst_n bit in ext_csd reg if not enabled. +* sk 11/16/16 Issue DLL reset at 31 iteration to load new zero value. +* 3.2 sk 02/01/17 Added HSD and DDR mode support for eMMC. +* sk 02/01/17 Consider bus width parameter from design for switching +* vns 02/09/17 Added ARMA53_32 support for ZynqMP CR#968397 +* vns 03/13/17 Fixed MISRAC mandatory violation +* sk 03/20/17 Add support for EL1 non-secure mode. +* 3.3 mn 07/25/17 Removed SD0_OTAPDLYENA and SD1_OTAPDLYENA bits +* mn 08/07/17 Properly set OTAPDLY value by clearing previous bit +* settings +* mn 08/17/17 Added CCI support for A53 and disabled data cache +* operations when it is enabled. +* mn 08/22/17 Updated for Word Access System support +* 3.4 mn 01/22/18 Separated out SDR104 and HS200 clock defines * * * @@ -62,24 +82,16 @@ /***************************** Include Files *********************************/ #include "xsdps.h" -/* - * The header sleep.h and API usleep() can only be used with an arm design. - * MB_Sleep() is used for microblaze design. - */ -#if defined (__arm__) || defined (__aarch64__) - #include "sleep.h" - +#if defined (__aarch64__) +#include "xil_smc.h" #endif - -#ifdef __MICROBLAZE__ - -#include "microblaze_sleep.h" - -#endif - /************************** Constant Definitions *****************************/ - +#define UHS_SDR12_SUPPORT 0x1U +#define UHS_SDR25_SUPPORT 0x2U +#define UHS_SDR50_SUPPORT 0x4U +#define UHS_SDR104_SUPPORT 0x8U +#define UHS_DDR50_SUPPORT 0x10U /**************************** Type Definitions *******************************/ /***************** Macros (Inline Functions) Definitions *********************/ @@ -87,13 +99,15 @@ /************************** Function Prototypes ******************************/ s32 XSdPs_CmdTransfer(XSdPs *InstancePtr, u32 Cmd, u32 Arg, u32 BlkCnt); void XSdPs_SetupADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff); -s32 XSdPs_Uhs_ModeInit(XSdPs *InstancePtr, u8 Mode); static s32 XSdPs_Execute_Tuning(XSdPs *InstancePtr); +#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) s32 XSdPs_Uhs_ModeInit(XSdPs *InstancePtr, u8 Mode); -#if defined (__arm__) || defined (__aarch64__) +static void XSdPs_sdr50_tapdelay(u32 Bank, u32 DeviceId, u32 CardType); void XSdPs_SetTapDelay(XSdPs *InstancePtr); +static void XSdPs_DllReset(XSdPs *InstancePtr); #endif +extern u16 TransferMode; /*****************************************************************************/ /** * Update Block size for read/write operations. @@ -193,11 +207,11 @@ s32 XSdPs_Get_BusWidth(XSdPs *InstancePtr, u8 *SCR) XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, SCR); - XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, - XSDPS_XFER_MODE_OFFSET, - XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK); + TransferMode = XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK; - Xil_DCacheInvalidateRange((INTPTR)SCR, 8); + if (InstancePtr->Config.IsCacheCoherent == 0) { + Xil_DCacheInvalidateRange((INTPTR)SCR, 8); + } Status = XSdPs_CmdTransfer(InstancePtr, ACMD51, 0U, BlkCnt); if (Status != XST_SUCCESS) { @@ -261,6 +275,16 @@ s32 XSdPs_Change_BusWidth(XSdPs *InstancePtr) Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + /* + * check for bus width for 3.0 controller and return if + * bus width is <4 + */ + if ((InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) && + (InstancePtr->Config.BusWidth < XSDPS_WIDTH_4)) { + Status = XST_SUCCESS; + goto RETURN_PATH; + } + if (InstancePtr->CardType == XSDPS_CARD_SD) { Status = XSdPs_CmdTransfer(InstancePtr, CMD55, InstancePtr->RelCardAddr, @@ -282,7 +306,8 @@ s32 XSdPs_Change_BusWidth(XSdPs *InstancePtr) } else { if ((InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) - && (InstancePtr->CardType == XSDPS_CHIP_EMMC)) { + && (InstancePtr->CardType == XSDPS_CHIP_EMMC) && + (InstancePtr->Config.BusWidth == XSDPS_WIDTH_8)) { /* in case of eMMC data width 8-bit */ InstancePtr->BusWidth = XSDPS_8_BIT_WIDTH; } else { @@ -290,9 +315,15 @@ s32 XSdPs_Change_BusWidth(XSdPs *InstancePtr) } if (InstancePtr->BusWidth == XSDPS_8_BIT_WIDTH) { - Arg = XSDPS_MMC_8_BIT_BUS_ARG; + if (InstancePtr->Mode == XSDPS_DDR52_MODE) + Arg = XSDPS_MMC_DDR_8_BIT_BUS_ARG; + else + Arg = XSDPS_MMC_8_BIT_BUS_ARG; } else { - Arg = XSDPS_MMC_4_BIT_BUS_ARG; + if (InstancePtr->Mode == XSDPS_DDR52_MODE) + Arg = XSDPS_MMC_DDR_4_BIT_BUS_ARG; + else + Arg = XSDPS_MMC_4_BIT_BUS_ARG; } Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 0U); @@ -320,19 +351,8 @@ s32 XSdPs_Change_BusWidth(XSdPs *InstancePtr) XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK); } -#if defined (__arm__) || defined (__aarch64__) - usleep(XSDPS_MMC_DELAY_FOR_SWITCH); -#endif - -#ifdef __MICROBLAZE__ - - /* 2 msec delay */ - MB_Sleep(2); - -#endif - StatusReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL1_OFFSET); @@ -347,6 +367,15 @@ s32 XSdPs_Change_BusWidth(XSdPs *InstancePtr) XSDPS_HOST_CTRL1_OFFSET, (u8)StatusReg); + if (InstancePtr->Mode == XSDPS_DDR52_MODE) { + StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_HOST_CTRL2_OFFSET); + StatusReg &= (u16)(~XSDPS_HC2_UHS_MODE_MASK); + StatusReg |= InstancePtr->Mode; + XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, + XSDPS_HOST_CTRL2_OFFSET, StatusReg); + } + Status = (s32)XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_RESP0_OFFSET); @@ -398,13 +427,13 @@ s32 XSdPs_Get_BusSpeed(XSdPs *InstancePtr, u8 *ReadBuff) XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff); - XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, - XSDPS_XFER_MODE_OFFSET, - XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK); + TransferMode = XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK; Arg = XSDPS_SWITCH_CMD_HS_GET; - Xil_DCacheInvalidateRange((INTPTR)ReadBuff, 64); + if (InstancePtr->Config.IsCacheCoherent == 0) { + Xil_DCacheInvalidateRange((INTPTR)ReadBuff, 64); + } Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 1U); if (Status != XST_SUCCESS) { @@ -463,10 +492,9 @@ s32 XSdPs_Change_BusSpeed(XSdPs *InstancePtr) s32 Status; u32 StatusReg; u32 Arg; - u32 ClockReg; u16 BlkCnt; u16 BlkSize; - u8 ReadBuff[64]; + u8 ReadBuff[64] = {0U}; Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); @@ -481,11 +509,11 @@ s32 XSdPs_Change_BusSpeed(XSdPs *InstancePtr) XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff); - Xil_DCacheFlushRange((INTPTR)ReadBuff, 64); + if (InstancePtr->Config.IsCacheCoherent == 0) { + Xil_DCacheFlushRange((INTPTR)ReadBuff, 64); + } - XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, - XSDPS_XFER_MODE_OFFSET, - XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK); + TransferMode = XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK; Arg = XSDPS_SWITCH_CMD_HS_SET; @@ -565,7 +593,16 @@ s32 XSdPs_Change_BusSpeed(XSdPs *InstancePtr) goto RETURN_PATH; } } else { - Arg = XSDPS_MMC_HS200_ARG; + if (InstancePtr->Mode == XSDPS_HS200_MODE) { + Arg = XSDPS_MMC_HS200_ARG; + InstancePtr->BusSpeed = XSDPS_MMC_HS200_MAX_CLK; + } else if (InstancePtr->Mode == XSDPS_DDR52_MODE) { + Arg = XSDPS_MMC_HIGH_SPEED_ARG; + InstancePtr->BusSpeed = XSDPS_MMC_DDR_MAX_CLK; + } else { + Arg = XSDPS_MMC_HIGH_SPEED_ARG; + InstancePtr->BusSpeed = XSDPS_MMC_HSD_MAX_CLK; + } Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 0U); if (Status != XST_SUCCESS) { @@ -597,38 +634,23 @@ s32 XSdPs_Change_BusSpeed(XSdPs *InstancePtr) XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK); - /* Change the clock frequency to 200 MHz */ - InstancePtr->BusSpeed = XSDPS_MMC_HS200_MAX_CLK; - Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } - Status = XSdPs_Execute_Tuning(InstancePtr); - if (Status != XST_SUCCESS) { - Status = XST_FAILURE; - goto RETURN_PATH; + + if (InstancePtr->Mode == XSDPS_HS200_MODE) { + Status = XSdPs_Execute_Tuning(InstancePtr); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } } -#if defined (__arm__) || defined (__aarch64__) - /* Program the Tap delays */ - XSdPs_SetTapDelay(InstancePtr); -#endif } -#if defined (__arm__) || defined (__aarch64__) - usleep(XSDPS_MMC_DELAY_FOR_SWITCH); -#endif - -#ifdef __MICROBLAZE__ - - /* 2 msec delay */ - MB_Sleep(2); - -#endif - StatusReg = (s32)XSdPs_ReadReg8(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL1_OFFSET); StatusReg |= XSDPS_HC_SPEED_MASK; @@ -667,7 +689,6 @@ s32 XSdPs_Change_ClkFreq(XSdPs *InstancePtr, u32 SelFreq) u16 DivCnt; u16 Divisor = 0U; u16 ExtDivisor; - u16 ClkLoopCnt; s32 Status; u16 ReadReg; @@ -682,6 +703,12 @@ s32 XSdPs_Change_ClkFreq(XSdPs *InstancePtr, u32 SelFreq) XSDPS_CLK_CTRL_OFFSET, ClockReg); if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) { +#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) + if ((InstancePtr->Mode != XSDPS_DEFAULT_SPEED_MODE) && + (InstancePtr->Mode != XSDPS_UHS_SPEED_MODE_SDR12)) + /* Program the Tap delays */ + XSdPs_SetTapDelay(InstancePtr); +#endif /* Calculate divisor */ for (DivCnt = 0x1U; DivCnt <= XSDPS_CC_EXT_MAX_DIV_CNT;DivCnt++) { if (((InstancePtr->Config.InputClockHz) / DivCnt) <= SelFreq) { @@ -845,12 +872,11 @@ s32 XSdPs_Get_Mmc_ExtCsd(XSdPs *InstancePtr, u8 *ReadBuff) XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff); - Xil_DCacheInvalidateRange((INTPTR)ReadBuff, 512U); - - XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, - XSDPS_XFER_MODE_OFFSET, - XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK); + if (InstancePtr->Config.IsCacheCoherent == 0) { + Xil_DCacheInvalidateRange((INTPTR)ReadBuff, 512U); + } + TransferMode = XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK; /* Send SEND_EXT_CSD command */ Status = XSdPs_CmdTransfer(InstancePtr, CMD8, Arg, 1U); @@ -890,6 +916,110 @@ s32 XSdPs_Get_Mmc_ExtCsd(XSdPs *InstancePtr, u8 *ReadBuff) } +/*****************************************************************************/ +/** +* +* API to write EXT_CSD register of eMMC. +* +* +* @param InstancePtr is a pointer to the XSdPs instance. +* @param Arg is the argument to be sent along with the command +* +* @return +* - XST_SUCCESS if successful. +* - XST_FAILURE if fail. +* +* @note None. +* +******************************************************************************/ +s32 XSdPs_Set_Mmc_ExtCsd(XSdPs *InstancePtr, u32 Arg) +{ + s32 Status; + u32 StatusReg; + + Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 0U); + if (Status != XST_SUCCESS) { + Status = XST_FAILURE; + goto RETURN_PATH; + } + + /* + * Check for transfer complete + */ + do { + StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_NORM_INTR_STS_OFFSET); + if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) { + /* + * Write to clear error bits + */ + XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, + XSDPS_ERR_INTR_STS_OFFSET, + XSDPS_ERROR_INTR_ALL_MASK); + Status = XST_FAILURE; + goto RETURN_PATH; + } + } while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U); + + /* Write to clear bit */ + XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, + XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK); + + Status = (s32)XSdPs_ReadReg(InstancePtr->Config.BaseAddress, + XSDPS_RESP0_OFFSET); + + Status = XST_SUCCESS; + + RETURN_PATH: + return Status; + +} + +#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) +/*****************************************************************************/ +/** +* +* API to Identify the supported UHS mode. This API will assign the +* corresponding tap delay API to the Config_TapDelay pointer based on the +* supported bus speed. +* +* +* @param InstancePtr is a pointer to the XSdPs instance. +* @param ReadBuff contains the response for CMD6 +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XSdPs_Identify_UhsMode(XSdPs *InstancePtr, u8 *ReadBuff) +{ + + Xil_AssertVoid(InstancePtr != NULL); + + if (((ReadBuff[13] & UHS_SDR104_SUPPORT) != 0U) && + (InstancePtr->Config.InputClockHz >= XSDPS_SD_INPUT_MAX_CLK)) { + InstancePtr->Mode = XSDPS_UHS_SPEED_MODE_SDR104; + InstancePtr->Config_TapDelay = XSdPs_sdr104_hs200_tapdelay; + } + else if (((ReadBuff[13] & UHS_SDR50_SUPPORT) != 0U) && + (InstancePtr->Config.InputClockHz >= XSDPS_SD_SDR50_MAX_CLK)) { + InstancePtr->Mode = XSDPS_UHS_SPEED_MODE_SDR50; + InstancePtr->Config_TapDelay = XSdPs_sdr50_tapdelay; + } + else if (((ReadBuff[13] & UHS_DDR50_SUPPORT) != 0U) && + (InstancePtr->Config.InputClockHz >= XSDPS_SD_DDR50_MAX_CLK)) { + InstancePtr->Mode = XSDPS_UHS_SPEED_MODE_DDR50; + InstancePtr->Config_TapDelay = XSdPs_ddr50_tapdelay; + } + else if (((ReadBuff[13] & UHS_SDR25_SUPPORT) != 0U) && + (InstancePtr->Config.InputClockHz >= XSDPS_SD_SDR25_MAX_CLK)) { + InstancePtr->Mode = XSDPS_UHS_SPEED_MODE_SDR25; + InstancePtr->Config_TapDelay = XSdPs_hsd_sdr25_tapdelay; + } + else + InstancePtr->Mode = XSDPS_UHS_SPEED_MODE_SDR12; +} /*****************************************************************************/ /** @@ -915,7 +1045,7 @@ s32 XSdPs_Uhs_ModeInit(XSdPs *InstancePtr, u8 Mode) u32 Arg; u16 BlkCnt; u16 BlkSize; - u8 ReadBuff[64]; + u8 ReadBuff[64] = {0U}; Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); @@ -931,10 +1061,11 @@ s32 XSdPs_Uhs_ModeInit(XSdPs *InstancePtr, u8 Mode) XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff); - Xil_DCacheFlushRange((INTPTR)ReadBuff, 64); + if (InstancePtr->Config.IsCacheCoherent == 0) { + Xil_DCacheFlushRange((INTPTR)ReadBuff, 64); + } - XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_XFER_MODE_OFFSET, - XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK); + TransferMode = XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK; switch (Mode) { case 0U: @@ -1008,7 +1139,7 @@ s32 XSdPs_Uhs_ModeInit(XSdPs *InstancePtr, u8 Mode) } if((Mode == XSDPS_UHS_SPEED_MODE_SDR104) || - (Mode == XSDPS_UHS_SPEED_MODE_DDR50)) { + (Mode == XSDPS_UHS_SPEED_MODE_SDR50)) { /* Send tuning pattern */ Status = XSdPs_Execute_Tuning(InstancePtr); if (Status != XST_SUCCESS) { @@ -1022,22 +1153,18 @@ s32 XSdPs_Uhs_ModeInit(XSdPs *InstancePtr, u8 Mode) RETURN_PATH: return Status; } +#endif static s32 XSdPs_Execute_Tuning(XSdPs *InstancePtr) { s32 Status; - u32 StatusReg; - u32 Arg; - u16 BlkCnt; u16 BlkSize; - s32 LoopCnt; u16 CtrlReg; u8 TuningCount; Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); - BlkCnt = XSDPS_TUNING_CMD_BLKCNT; BlkSize = XSDPS_TUNING_CMD_BLKSIZE; if(InstancePtr->BusWidth == XSDPS_8_BIT_WIDTH) { @@ -1047,8 +1174,7 @@ static s32 XSdPs_Execute_Tuning(XSdPs *InstancePtr) XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_BLK_SIZE_OFFSET, BlkSize); - XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_XFER_MODE_OFFSET, - XSDPS_TM_DAT_DIR_SEL_MASK); + TransferMode = XSDPS_TM_DAT_DIR_SEL_MASK; CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL2_OFFSET); @@ -1056,6 +1182,18 @@ static s32 XSdPs_Execute_Tuning(XSdPs *InstancePtr) XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL2_OFFSET, CtrlReg); + /* + * workaround which can work for 1.0/2.0 silicon for auto tuning. + * This can be revisited for 3.0 silicon if necessary. + */ + /* Wait for ~60 clock cycles to reset the tap values */ + (void)usleep(1U); + +#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) + /* Issue DLL Reset to load new SDHC tuned tap values */ + XSdPs_DllReset(InstancePtr); +#endif + for (TuningCount = 0U; TuningCount < MAX_TUNING_COUNT; TuningCount++) { if (InstancePtr->CardType == XSDPS_CARD_SD) { @@ -1073,6 +1211,13 @@ static s32 XSdPs_Execute_Tuning(XSdPs *InstancePtr) XSDPS_HOST_CTRL2_OFFSET) & XSDPS_HC2_EXEC_TNG_MASK) == 0U) { break; } + + if (TuningCount == 31) { +#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) + /* Issue DLL Reset to load new SDHC tuned tap values */ + XSdPs_DllReset(InstancePtr); +#endif + } } if ((XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, @@ -1081,25 +1226,13 @@ static s32 XSdPs_Execute_Tuning(XSdPs *InstancePtr) goto RETURN_PATH; } - /* - * As per controller erratum, program the "SDCLK Frequency - * Select" of clock control register with a value, say - * clock/2. Wait for the Internal clock stable and program - * the desired frequency. - */ - CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, - XSDPS_HOST_CTRL2_OFFSET); - if ((CtrlReg & XSDPS_HC2_SAMP_CLK_SEL_MASK) != 0U) { - Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed/2); - if (Status != XST_SUCCESS) { - goto RETURN_PATH ; - } - Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed); - if (Status != XST_SUCCESS) { - goto RETURN_PATH ; - } + /* Wait for ~12 clock cycles to synchronize the new tap values */ + (void)usleep(1U); - } +#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) + /* Issue DLL Reset to load new SDHC tuned tap values */ + XSdPs_DllReset(InstancePtr); +#endif Status = XST_SUCCESS; @@ -1107,7 +1240,363 @@ static s32 XSdPs_Execute_Tuning(XSdPs *InstancePtr) } -#if defined (__arm__) || defined (__aarch64__) +#if defined (ARMR5) || defined (__aarch64__) || defined (ARMA53_32) +/*****************************************************************************/ +/** +* +* API to set Tap Delay for SDR104 and HS200 modes +* +* +* @param InstancePtr is a pointer to the XSdPs instance. +* +* @return None +* +* @note None. +* +******************************************************************************/ +void XSdPs_sdr104_hs200_tapdelay(u32 Bank, u32 DeviceId, u32 CardType) +{ + u32 TapDelay; + (void) CardType; + +#ifdef XPAR_PSU_SD_0_DEVICE_ID + if (DeviceId == 0U) { +#if EL1_NONSECURE && defined (__aarch64__) + (void)TapDelay; + if (Bank == 2) + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_OTAPDLY) | ((u64)SD0_OTAPDLY_SEL_MASK << 32), + (u64)SD0_OTAPDLYSEL_HS200_B2, 0, 0, 0, 0, 0); + else + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_OTAPDLY) | ((u64)SD0_OTAPDLY_SEL_MASK << 32), + (u64)SD0_OTAPDLYSEL_HS200_B0, 0, 0, 0, 0, 0); +#else + /* Program the OTAPDLY */ + TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY); + TapDelay &= ~SD0_OTAPDLY_SEL_MASK; + if (Bank == 2) + TapDelay |= SD0_OTAPDLYSEL_HS200_B2; + else + TapDelay |= SD0_OTAPDLYSEL_HS200_B0; + XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay); +#endif + } else { +#endif + (void) DeviceId; +#if EL1_NONSECURE && defined (__aarch64__) + (void)TapDelay; + if (Bank == 2) + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_OTAPDLY) | ((u64)SD1_OTAPDLY_SEL_MASK << 32), + (u64)SD1_OTAPDLYSEL_HS200_B2, 0, 0, 0, 0, 0); + else + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_OTAPDLY) | ((u64)SD1_OTAPDLY_SEL_MASK << 32), + (u64)SD1_OTAPDLYSEL_HS200_B0, 0, 0, 0, 0, 0); +#else + TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY); + TapDelay &= ~SD1_OTAPDLY_SEL_MASK; + if (Bank == 2) + TapDelay |= SD1_OTAPDLYSEL_HS200_B2; + else + TapDelay |= SD1_OTAPDLYSEL_HS200_B0; + XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay); +#endif +#ifdef XPAR_PSU_SD_0_DEVICE_ID + } +#endif +} + +/*****************************************************************************/ +/** +* +* API to set Tap Delay for SDR50 mode +* +* +* @param InstancePtr is a pointer to the XSdPs instance. +* +* @return None +* +* @note None. +* +******************************************************************************/ +void XSdPs_sdr50_tapdelay(u32 Bank, u32 DeviceId, u32 CardType) +{ + u32 TapDelay; + (void) Bank; + (void) CardType; + +#ifdef XPAR_PSU_SD_0_DEVICE_ID + if (DeviceId == 0U) { +#if EL1_NONSECURE && defined (__aarch64__) + (void)TapDelay; + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_OTAPDLY) | + ((u64)SD0_OTAPDLY_SEL_MASK << 32), (u64)SD0_OTAPDLYSEL_SD50, + 0, 0, 0, 0, 0); +#else + /* Program the OTAPDLY */ + TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY); + TapDelay &= ~SD0_OTAPDLY_SEL_MASK; + TapDelay |= SD0_OTAPDLYSEL_SD50; + XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay); +#endif + } else { +#endif + (void) DeviceId; +#if EL1_NONSECURE && defined (__aarch64__) + (void)TapDelay; + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_OTAPDLY) | + ((u64)SD1_OTAPDLY_SEL_MASK << 32), (u64)SD1_OTAPDLYSEL_SD50, + 0, 0, 0, 0, 0); +#else + TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY); + TapDelay &= ~SD1_OTAPDLY_SEL_MASK; + TapDelay |= SD1_OTAPDLYSEL_SD50; + XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay); +#endif +#ifdef XPAR_PSU_SD_0_DEVICE_ID + } +#endif +} + +/*****************************************************************************/ +/** +* +* API to set Tap Delay for DDR50 mode +* +* +* @param InstancePtr is a pointer to the XSdPs instance. +* +* @return None +* +* @note None. +* +******************************************************************************/ +void XSdPs_ddr50_tapdelay(u32 Bank, u32 DeviceId, u32 CardType) +{ + u32 TapDelay; + (void) Bank; + +#ifdef XPAR_PSU_SD_0_DEVICE_ID + if (DeviceId == 0U) { +#if EL1_NONSECURE && defined (__aarch64__) + (void)TapDelay; + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) | + ((u64)SD0_ITAPCHGWIN << 32), (u64)SD0_ITAPCHGWIN, + 0, 0, 0, 0, 0); + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) | + ((u64)SD0_ITAPDLYENA << 32), (u64)SD0_ITAPDLYENA, + 0, 0, 0, 0, 0); + if (CardType== XSDPS_CARD_SD) + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_ITAPDLY) | ((u64)SD0_ITAPDLY_SEL_MASK << 32), + (u64)SD0_ITAPDLYSEL_SD_DDR50, 0, 0, 0, 0, 0); + else + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_ITAPDLY) | ((u64)SD0_ITAPDLY_SEL_MASK << 32), + (u64)SD0_ITAPDLYSEL_EMMC_DDR50, 0, 0, 0, 0, 0); + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) | + ((u64)SD0_ITAPCHGWIN << 32), (u64)0x0, 0, 0, 0, 0, 0); + if (CardType == XSDPS_CARD_SD) + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_OTAPDLY) | ((u64)SD0_OTAPDLY_SEL_MASK << 32), + (u64)SD0_OTAPDLYSEL_SD_DDR50, 0, 0, 0, 0, 0); + else + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_OTAPDLY) | ((u64)SD0_OTAPDLY_SEL_MASK << 32), + (u64)SD0_OTAPDLYSEL_EMMC_DDR50, 0, 0, 0, 0, 0); +#else + TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY); + TapDelay |= SD0_ITAPCHGWIN; + XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay); + /* Program the ITAPDLY */ + TapDelay |= SD0_ITAPDLYENA; + XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay); + if (CardType== XSDPS_CARD_SD) + TapDelay |= SD0_ITAPDLYSEL_SD_DDR50; + else + TapDelay |= SD0_ITAPDLYSEL_EMMC_DDR50; + XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay); + TapDelay &= ~SD0_ITAPCHGWIN; + XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay); + /* Program the OTAPDLY */ + TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY); + TapDelay &= ~SD0_OTAPDLY_SEL_MASK; + if (CardType == XSDPS_CARD_SD) + TapDelay |= SD0_OTAPDLYSEL_SD_DDR50; + else + TapDelay |= SD0_OTAPDLYSEL_EMMC_DDR50; + XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay); +#endif + } else { +#endif + (void) DeviceId; +#if EL1_NONSECURE && defined (__aarch64__) + (void)TapDelay; + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) | + ((u64)SD1_ITAPCHGWIN << 32), (u64)SD1_ITAPCHGWIN, + 0, 0, 0, 0, 0); + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) | + ((u64)SD1_ITAPDLYENA << 32), (u64)SD1_ITAPDLYENA, + 0, 0, 0, 0, 0); + if (CardType== XSDPS_CARD_SD) + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_ITAPDLY) | ((u64)SD1_ITAPDLY_SEL_MASK << 32), + (u64)SD1_ITAPDLYSEL_SD_DDR50, 0, 0, 0, 0, 0); + else + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_ITAPDLY) | ((u64)SD1_ITAPDLY_SEL_MASK << 32), + (u64)SD1_ITAPDLYSEL_EMMC_DDR50, 0, 0, 0, 0, 0); + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_ITAPDLY) | ((u64)SD1_ITAPCHGWIN << 32), + (u64)0x0, 0, 0, 0, 0, 0); + if (CardType == XSDPS_CARD_SD) + Xil_Smc(MMIO_WRITE_SMC_FID,(u64)(XPS_SYS_CTRL_BASEADDR + + SD_OTAPDLY) | ((u64)SD1_OTAPDLY_SEL_MASK << 32), + (u64)SD1_OTAPDLYSEL_SD_DDR50, 0, 0, 0, 0, 0); + else + Xil_Smc(MMIO_WRITE_SMC_FID,(u64)(XPS_SYS_CTRL_BASEADDR + + SD_OTAPDLY) | ((u64)SD1_OTAPDLY_SEL_MASK << 32), + (u64)SD1_OTAPDLYSEL_EMMC_DDR50, 0, 0, 0, 0, 0); +#else + TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY); + TapDelay |= SD1_ITAPCHGWIN; + XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay); + /* Program the ITAPDLY */ + TapDelay |= SD1_ITAPDLYENA; + XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay); + if (CardType == XSDPS_CARD_SD) + TapDelay |= SD1_ITAPDLYSEL_SD_DDR50; + else + TapDelay |= SD1_ITAPDLYSEL_EMMC_DDR50; + XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay); + TapDelay &= ~SD1_ITAPCHGWIN; + XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay); + /* Program the OTAPDLY */ + TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY); + TapDelay &= ~SD1_OTAPDLY_SEL_MASK; + if (CardType == XSDPS_CARD_SD) + TapDelay |= SD1_OTAPDLYSEL_SD_DDR50; + else + TapDelay |= SD1_OTAPDLYSEL_EMMC_DDR50; + XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay); +#endif +#ifdef XPAR_PSU_SD_0_DEVICE_ID + } +#endif +} + +/*****************************************************************************/ +/** +* +* API to set Tap Delay for HSD and SDR25 mode +* +* +* @param InstancePtr is a pointer to the XSdPs instance. +* +* @return None +* +* @note None. +* +******************************************************************************/ +void XSdPs_hsd_sdr25_tapdelay(u32 Bank, u32 DeviceId, u32 CardType) +{ + u32 TapDelay; + (void) Bank; + +#ifdef XPAR_PSU_SD_0_DEVICE_ID + if (DeviceId == 0U) { +#if EL1_NONSECURE && defined (__aarch64__) + (void)TapDelay; + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) | + ((u64)SD0_ITAPCHGWIN << 32), (u64)SD0_ITAPCHGWIN, + 0, 0, 0, 0, 0); + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) | + ((u64)SD0_ITAPDLYENA << 32), (u64)SD0_ITAPDLYENA, + 0, 0, 0, 0, 0); + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) | + ((u64)SD0_ITAPDLY_SEL_MASK << 32), (u64)SD0_ITAPDLYSEL_HSD, + 0, 0, 0, 0, 0); + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) | + ((u64)SD0_ITAPCHGWIN << 32), (u64)0x0, 0, 0, 0, 0, 0); + if (CardType == XSDPS_CARD_SD) + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_OTAPDLY) | ((u64)SD0_OTAPDLY_SEL_MASK << 32), + (u64)SD0_OTAPDLYSEL_SD_HSD, 0, 0, 0, 0, 0); + else + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_OTAPDLY) | ((u64)SD0_OTAPDLY_SEL_MASK << 32), + (u64)SD0_OTAPDLYSEL_EMMC_HSD, 0, 0, 0, 0, 0); +#else + TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY); + TapDelay |= SD0_ITAPCHGWIN; + XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay); + /* Program the ITAPDLY */ + TapDelay |= SD0_ITAPDLYENA; + XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay); + TapDelay |= SD0_ITAPDLYSEL_HSD; + XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay); + TapDelay &= ~SD0_ITAPCHGWIN; + XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay); + /* Program the OTAPDLY */ + TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY); + TapDelay &= ~SD0_OTAPDLY_SEL_MASK; + if (CardType == XSDPS_CARD_SD) + TapDelay |= SD0_OTAPDLYSEL_SD_HSD; + else + TapDelay |= SD0_OTAPDLYSEL_EMMC_HSD; + XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay); +#endif + } else { +#endif + (void) DeviceId; +#if EL1_NONSECURE && defined (__aarch64__) + (void)TapDelay; + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) | + ((u64)SD1_ITAPCHGWIN << 32), (u64)SD1_ITAPCHGWIN, + 0, 0, 0, 0, 0); + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) | + ((u64)SD1_ITAPDLYENA << 32), (u64)SD1_ITAPDLYENA, + 0, 0, 0, 0, 0); + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) | + ((u64)SD1_ITAPDLY_SEL_MASK << 32), (u64)SD1_ITAPDLYSEL_HSD, + 0, 0, 0, 0, 0); + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + SD_ITAPDLY) | + ((u64)SD1_ITAPCHGWIN << 32), (u64)0x0, 0, 0, 0, 0, 0); + if (CardType == XSDPS_CARD_SD) + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_OTAPDLY) | ((u64)SD1_OTAPDLY_SEL_MASK << 32), + (u64)SD1_OTAPDLYSEL_SD_HSD, 0, 0, 0, 0, 0); + else + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_OTAPDLY) | ((u64)SD1_OTAPDLY_SEL_MASK << 32), + (u64)SD1_OTAPDLYSEL_EMMC_HSD, 0, 0, 0, 0, 0); +#else + TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY); + TapDelay |= SD1_ITAPCHGWIN; + XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay); + /* Program the ITAPDLY */ + TapDelay |= SD1_ITAPDLYENA; + XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay); + TapDelay |= SD1_ITAPDLYSEL_HSD; + XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay); + TapDelay &= ~SD1_ITAPCHGWIN; + XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay); + /* Program the OTAPDLY */ + TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY); + TapDelay &= ~SD1_OTAPDLY_SEL_MASK; + if (CardType == XSDPS_CARD_SD) + TapDelay |= SD1_OTAPDLYSEL_SD_HSD; + else + TapDelay |= SD1_OTAPDLYSEL_EMMC_HSD; + XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLY, TapDelay); +#endif +#ifdef XPAR_PSU_SD_0_DEVICE_ID + } +#endif +} + /*****************************************************************************/ /** * @@ -1123,30 +1612,149 @@ static s32 XSdPs_Execute_Tuning(XSdPs *InstancePtr) ******************************************************************************/ void XSdPs_SetTapDelay(XSdPs *InstancePtr) { - u32 DllCtrl, TapDelay; - if (InstancePtr->Config.DeviceId == XPAR_XSDPS_0_DEVICE_ID) { + u32 DllCtrl, BankNum, DeviceId, CardType; + + BankNum = InstancePtr->Config.BankNumber; + DeviceId = InstancePtr->Config.DeviceId ; + CardType = InstancePtr->CardType ; +#ifdef XPAR_PSU_SD_0_DEVICE_ID + if (DeviceId == 0U) { +#if EL1_NONSECURE && defined (__aarch64__) + (void)DllCtrl; + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_DLL_CTRL) | ((u64)SD0_DLL_RST << 32), + (u64)SD0_DLL_RST, 0, 0, 0, 0, 0); +#else DllCtrl = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL); DllCtrl |= SD0_DLL_RST; XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl); - if(InstancePtr->BusSpeed == XSDPS_MMC_HS200_MAX_CLK) { - /* Program the ITAPDLY */ - TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY); - TapDelay |= SD0_ITAPCHGWIN; - XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay); - TapDelay |= SD0_ITAPDLYENA; - XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay); - TapDelay &= ~SD0_ITAPCHGWIN; - XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay); - /* Program the OTAPDLY */ - TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLYSEL); - TapDelay |= SD0_OTAPDLYENA; - XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLYSEL, TapDelay); - TapDelay |= SD0_OTAPDLYSEL_HS200; - XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLYSEL, TapDelay); - } +#endif + InstancePtr->Config_TapDelay(BankNum, DeviceId, CardType); +#if EL1_NONSECURE && defined (__aarch64__) + (void)DllCtrl; + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_DLL_CTRL) | ((u64)SD0_DLL_RST << 32), + (u64)0x0, 0, 0, 0, 0, 0); +#else DllCtrl &= ~SD0_DLL_RST; XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl); +#endif + } else { +#endif +#if EL1_NONSECURE && defined (__aarch64__) + (void)DllCtrl; + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_DLL_CTRL) | ((u64)SD1_DLL_RST << 32), + (u64)SD1_DLL_RST, 0, 0, 0, 0, 0); +#else + DllCtrl = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL); + DllCtrl |= SD1_DLL_RST; + XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl); +#endif + InstancePtr->Config_TapDelay(BankNum, DeviceId, CardType); +#if EL1_NONSECURE && defined (__aarch64__) + (void)DllCtrl; + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_DLL_CTRL) | ((u64)SD1_DLL_RST << 32), + (u64)0x0, 0, 0, 0, 0, 0); +#else + DllCtrl &= ~SD1_DLL_RST; + XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl); +#endif +#ifdef XPAR_PSU_SD_0_DEVICE_ID } +#endif +} + +/*****************************************************************************/ +/** +* +* API to reset the DLL +* +* +* @param InstancePtr is a pointer to the XSdPs instance. +* +* @return None +* +* @note None. +* +******************************************************************************/ +static void XSdPs_DllReset(XSdPs *InstancePtr) +{ + u32 ClockReg, DllCtrl; + + /* Disable clock */ + ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_CLK_CTRL_OFFSET); + ClockReg &= ~XSDPS_CC_SD_CLK_EN_MASK; + XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, + XSDPS_CLK_CTRL_OFFSET, ClockReg); + + /* Issue DLL Reset to load zero tap values */ + DllCtrl = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL); + if (InstancePtr->Config.DeviceId == 0U) { +#if EL1_NONSECURE && defined (__aarch64__) + (void)DllCtrl; + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_DLL_CTRL) | ((u64)SD0_DLL_RST << 32), + (u64)SD0_DLL_RST, 0, 0, 0, 0, 0); +#else + DllCtrl |= SD0_DLL_RST; + XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl); +#endif + } else { +#if EL1_NONSECURE && defined (__aarch64__) + (void)DllCtrl; + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_DLL_CTRL) | ((u64)SD1_DLL_RST << 32), + (u64)SD1_DLL_RST, 0, 0, 0, 0, 0); +#else + DllCtrl |= SD1_DLL_RST; + XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl); +#endif + } + + /* Wait for 2 micro seconds */ + (void)usleep(2U); + + /* Release the DLL out of reset */ + DllCtrl = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL); + if (InstancePtr->Config.DeviceId == 0U) { +#if EL1_NONSECURE && defined (__aarch64__) + (void)DllCtrl; + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_DLL_CTRL) | ((u64)SD0_DLL_RST << 32), + (u64)0x0, 0, 0, 0, 0, 0); +#else + DllCtrl &= ~SD0_DLL_RST; + XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl); +#endif + } else { +#if EL1_NONSECURE && defined (__aarch64__) + (void)DllCtrl; + Xil_Smc(MMIO_WRITE_SMC_FID, (u64)(XPS_SYS_CTRL_BASEADDR + + SD_DLL_CTRL) | ((u64)SD1_DLL_RST << 32), + (u64)0x0, 0, 0, 0, 0, 0); +#else + DllCtrl &= ~SD1_DLL_RST; + XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl); +#endif + } + + /* Wait for internal clock to stabilize */ + ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_CLK_CTRL_OFFSET); + while((ClockReg & XSDPS_CC_INT_CLK_STABLE_MASK) == 0U) { + ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_CLK_CTRL_OFFSET); + } + + /* Enable SD clock */ + ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, + XSDPS_CLK_CTRL_OFFSET); + XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, + XSDPS_CLK_CTRL_OFFSET, + ClockReg | XSDPS_CC_SD_CLK_EN_MASK); } #endif /** @} */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/sdps_v2_7/src/xsdps_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_4/src/xsdps_sinit.c similarity index 97% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/sdps_v2_7/src/xsdps_sinit.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_4/src/xsdps_sinit.c index 59657a7b3..b49a0064c 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/sdps_v2_7/src/xsdps_sinit.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v3_4/src/xsdps_sinit.c @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2013 - 2015 Xilinx, Inc. All rights reserved. +* Copyright (C) 2013 - 2016 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -33,7 +33,7 @@ /** * * @file xsdps_sinit.c -* @addtogroup sdps_v2_5 +* @addtogroup sdps_v3_4 * @{ * * The implementation of the XSdPs component's static initialization diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/sleep.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/sleep.h deleted file mode 100644 index 27add6605..000000000 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/sleep.h +++ /dev/null @@ -1,50 +0,0 @@ -/****************************************************************************** -* -* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved. -* -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: -* -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. -* -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. -* -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. -* -******************************************************************************/ - -#ifndef SLEEP_H -#define SLEEP_H - -#include "xil_types.h" -#include "xil_io.h" - -#ifdef __cplusplus -extern "C" { -#endif - -int usleep(unsigned long useconds); -unsigned sleep(unsigned int seconds); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_mpu.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_mpu.c deleted file mode 100644 index 7c028c515..000000000 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_mpu.c +++ /dev/null @@ -1,258 +0,0 @@ -/****************************************************************************** -* -* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved. -* -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: -* -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. -* -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. -* -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* @file xil_mpu.c -* -* This file provides APIs for enabling/disabling MPU and setting the memory -* attributes for sections, in the MPU translation table. -* -* 
-* MODIFICATION HISTORY:
-*
-* Ver   Who  Date     Changes
-* ----- ---- -------- ---------------------------------------------------
-* 5.00  pkp  02/10/14 Initial version
-*
-* -* @note -* -* None. -* -******************************************************************************/ - -/***************************** Include Files *********************************/ - -#include "xil_cache.h" -#include "xpseudo_asm.h" -#include "xil_types.h" -#include "xil_mpu.h" -#include "xdebug.h" -/***************** Macros (Inline Functions) Definitions *********************/ - -/**************************** Type Definitions *******************************/ - -/************************** Constant Definitions *****************************/ - -/************************** Variable Definitions *****************************/ - -static const struct { - u64 size; - unsigned int encoding; -}region_size[] = { - { 0x20, REGION_32B }, - { 0x40, REGION_64B }, - { 0x80, REGION_128B }, - { 0x100, REGION_256B }, - { 0x200, REGION_512B }, - { 0x400, REGION_1K }, - { 0x800, REGION_2K }, - { 0x1000, REGION_4K }, - { 0x2000, REGION_8K }, - { 0x4000, REGION_16K }, - { 0x8000, REGION_32K }, - { 0x10000, REGION_64K }, - { 0x20000, REGION_128K }, - { 0x40000, REGION_256K }, - { 0x80000, REGION_512K }, - { 0x100000, REGION_1M }, - { 0x200000, REGION_2M }, - { 0x400000, REGION_4M }, - { 0x800000, REGION_8M }, - { 0x1000000, REGION_16M }, - { 0x2000000, REGION_32M }, - { 0x4000000, REGION_64M }, - { 0x8000000, REGION_128M }, - { 0x10000000, REGION_256M }, - { 0x20000000, REGION_512M }, - { 0x40000000, REGION_1G }, - { 0x80000000, REGION_2G }, - { 0x100000000, REGION_4G }, -}; - -/************************** Function Prototypes ******************************/ - -/***************************************************************************** -* -* Set the memory attributes for a section of memory with starting address addr -* of the region size 1MB having attributes attrib -* -* @param addr is the address for which attributes are to be set. -* @param attrib specifies the attributes for that memory region. -* @return None. -* -* -******************************************************************************/ -void Xil_SetTlbAttributes(INTPTR addr, u32 attrib) -{ - INTPTR Localaddr = addr; - Localaddr &= (~(0xFFFFFU)); - /* Setting the MPU region with given attribute with 1MB size */ - Xil_SetMPURegion(Localaddr, 0x100000, attrib); -} - -/***************************************************************************** -* -* Set the memory attributes for a section of memory with starting address addr -* of the region size size and having attributes attrib -* -* @param addr is the address for which attributes are to be set. -* @param size is the size of the region. -* @param attrib specifies the attributes for that memory region. -* @return None. -* -* -******************************************************************************/ -void Xil_SetMPURegion(INTPTR addr, u64 size, u32 attrib) -{ - u32 Regionsize = 0; - INTPTR Localaddr = addr; - u32 NextAvailableMemRegion; - unsigned int i; - - Xil_DCacheFlush(); - Xil_ICacheInvalidate(); - NextAvailableMemRegion = mfcp(XREG_CP15_MPU_MEMORY_REG_NUMBER); - NextAvailableMemRegion++; - if (NextAvailableMemRegion > 16) { - xdbg_printf(DEBUG, "No regions available\r\n"); - return; - } - mtcp(XREG_CP15_MPU_MEMORY_REG_NUMBER,NextAvailableMemRegion); - isb(); - - /* Lookup the size. */ - for (i = 0; i < sizeof region_size / sizeof region_size[0]; i++) { - if (size <= region_size[i].size) { - Regionsize = region_size[i].encoding; - break; - } - } - - Localaddr &= ~(region_size[i].size - 1); - - Regionsize <<= 1; - Regionsize |= REGION_EN; - dsb(); - mtcp(XREG_CP15_MPU_REG_BASEADDR, Localaddr); /* Set base address of a region */ - mtcp(XREG_CP15_MPU_REG_ACCESS_CTRL, attrib); /* Set the control attribute */ - mtcp(XREG_CP15_MPU_REG_SIZE_EN, Regionsize); /* set the region size and enable it*/ - dsb(); - isb(); -} -/***************************************************************************** -* -* Enable MPU for Cortex R5 processor. This function invalidates I cache and -* flush the D Caches before enabling the MPU. -* -* -* @param None. -* @return None. -* -******************************************************************************/ -void Xil_EnableMPU(void) -{ - u32 CtrlReg, Reg; - s32 DCacheStatus=0, ICacheStatus=0; - /* enable caches only if they are disabled */ - CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); - if ((CtrlReg & XREG_CP15_CONTROL_C_BIT) != 0x00000000U) { - DCacheStatus=1; - } - if ((CtrlReg & XREG_CP15_CONTROL_I_BIT) != 0x00000000U) { - ICacheStatus=1; - } - - if(DCacheStatus != 0) { - Xil_DCacheDisable(); - } - if(ICacheStatus != 0){ - Xil_ICacheDisable(); - } - Reg = mfcp(XREG_CP15_SYS_CONTROL); - Reg |= 0x00000001U; - dsb(); - mtcp(XREG_CP15_SYS_CONTROL, Reg); - isb(); - /* enable caches only if they are disabled in routine*/ - if(DCacheStatus != 0) { - Xil_DCacheEnable(); - } - if(ICacheStatus != 0) { - Xil_ICacheEnable(); - } -} - -/***************************************************************************** -* -* Disable MPU for Cortex R5 processors. This function invalidates I cache and -* flush the D Caches before disabling the MPU. -* -* @param None. -* -* @return None. -* -******************************************************************************/ -void Xil_DisableMPU(void) -{ - u32 CtrlReg, Reg; - s32 DCacheStatus=0, ICacheStatus=0; - /* enable caches only if they are disabled */ - CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); - if ((CtrlReg & XREG_CP15_CONTROL_C_BIT) != 0x00000000U) { - DCacheStatus=1; - } - if ((CtrlReg & XREG_CP15_CONTROL_I_BIT) != 0x00000000U) { - ICacheStatus=1; - } - - if(DCacheStatus != 0) { - Xil_DCacheDisable(); - } - if(ICacheStatus != 0){ - Xil_ICacheDisable(); - } - - mtcp(XREG_CP15_INVAL_BRANCH_ARRAY, 0); - Reg = mfcp(XREG_CP15_SYS_CONTROL); - Reg &= ~(0x00000001U); - dsb(); - mtcp(XREG_CP15_SYS_CONTROL, Reg); - isb(); - /* enable caches only if they are disabled in routine*/ - if(DCacheStatus != 0) { - Xil_DCacheEnable(); - } - if(ICacheStatus != 0) { - Xil_ICacheEnable(); - } -} \ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xstatus.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xstatus.h deleted file mode 100644 index 4873e85eb..000000000 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xstatus.h +++ /dev/null @@ -1,432 +0,0 @@ -/****************************************************************************** -* -* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved. -* -* Permission is hereby granted, free of charge, to any person obtaining a copy -* of this software and associated documentation files (the "Software"), to deal -* in the Software without restriction, including without limitation the rights -* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -* copies of the Software, and to permit persons to whom the Software is -* furnished to do so, subject to the following conditions: -* -* The above copyright notice and this permission notice shall be included in -* all copies or substantial portions of the Software. -* -* Use of the Software is limited solely to applications: -* (a) running on a Xilinx device, or -* (b) that interact with a Xilinx device through a bus or interconnect. -* -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF -* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -* SOFTWARE. -* -* Except as contained in this notice, the name of the Xilinx shall not be used -* in advertising or otherwise to promote the sale, use or other dealings in -* this Software without prior written authorization from Xilinx. -* -******************************************************************************/ -/*****************************************************************************/ -/** -* -* @file xstatus.h -* -* This file contains Xilinx software status codes. Status codes have their -* own data type called int. These codes are used throughout the Xilinx -* device drivers. -* -******************************************************************************/ - -#ifndef XSTATUS_H /* prevent circular inclusions */ -#define XSTATUS_H /* by using protection macros */ - -#ifdef __cplusplus -extern "C" { -#endif - -/***************************** Include Files *********************************/ - -#include "xil_types.h" -#include "xil_assert.h" - -/************************** Constant Definitions *****************************/ - -/*********************** Common statuses 0 - 500 *****************************/ - -#define XST_SUCCESS 0L -#define XST_FAILURE 1L -#define XST_DEVICE_NOT_FOUND 2L -#define XST_DEVICE_BLOCK_NOT_FOUND 3L -#define XST_INVALID_VERSION 4L -#define XST_DEVICE_IS_STARTED 5L -#define XST_DEVICE_IS_STOPPED 6L -#define XST_FIFO_ERROR 7L /* an error occurred during an - operation with a FIFO such as - an underrun or overrun, this - error requires the device to - be reset */ -#define XST_RESET_ERROR 8L /* an error occurred which requires - the device to be reset */ -#define XST_DMA_ERROR 9L /* a DMA error occurred, this error - typically requires the device - using the DMA to be reset */ -#define XST_NOT_POLLED 10L /* the device is not configured for - polled mode operation */ -#define XST_FIFO_NO_ROOM 11L /* a FIFO did not have room to put - the specified data into */ -#define XST_BUFFER_TOO_SMALL 12L /* the buffer is not large enough - to hold the expected data */ -#define XST_NO_DATA 13L /* there was no data available */ -#define XST_REGISTER_ERROR 14L /* a register did not contain the - expected value */ -#define XST_INVALID_PARAM 15L /* an invalid parameter was passed - into the function */ -#define XST_NOT_SGDMA 16L /* the device is not configured for - scatter-gather DMA operation */ -#define XST_LOOPBACK_ERROR 17L /* a loopback test failed */ -#define XST_NO_CALLBACK 18L /* a callback has not yet been - registered */ -#define XST_NO_FEATURE 19L /* device is not configured with - the requested feature */ -#define XST_NOT_INTERRUPT 20L /* device is not configured for - interrupt mode operation */ -#define XST_DEVICE_BUSY 21L /* device is busy */ -#define XST_ERROR_COUNT_MAX 22L /* the error counters of a device - have maxed out */ -#define XST_IS_STARTED 23L /* used when part of device is - already started i.e. - sub channel */ -#define XST_IS_STOPPED 24L /* used when part of device is - already stopped i.e. - sub channel */ -#define XST_DATA_LOST 26L /* driver defined error */ -#define XST_RECV_ERROR 27L /* generic receive error */ -#define XST_SEND_ERROR 28L /* generic transmit error */ -#define XST_NOT_ENABLED 29L /* a requested service is not - available because it has not - been enabled */ - -/***************** Utility Component statuses 401 - 500 *********************/ - -#define XST_MEMTEST_FAILED 401L /* memory test failed */ - - -/***************** Common Components statuses 501 - 1000 *********************/ - -/********************* Packet Fifo statuses 501 - 510 ************************/ - -#define XST_PFIFO_LACK_OF_DATA 501L /* not enough data in FIFO */ -#define XST_PFIFO_NO_ROOM 502L /* not enough room in FIFO */ -#define XST_PFIFO_BAD_REG_VALUE 503L /* self test, a register value - was invalid after reset */ -#define XST_PFIFO_ERROR 504L /* generic packet FIFO error */ -#define XST_PFIFO_DEADLOCK 505L /* packet FIFO is reporting - * empty and full simultaneously - */ - -/************************** DMA statuses 511 - 530 ***************************/ - -#define XST_DMA_TRANSFER_ERROR 511L /* self test, DMA transfer - failed */ -#define XST_DMA_RESET_REGISTER_ERROR 512L /* self test, a register value - was invalid after reset */ -#define XST_DMA_SG_LIST_EMPTY 513L /* scatter gather list contains - no buffer descriptors ready - to be processed */ -#define XST_DMA_SG_IS_STARTED 514L /* scatter gather not stopped */ -#define XST_DMA_SG_IS_STOPPED 515L /* scatter gather not running */ -#define XST_DMA_SG_LIST_FULL 517L /* all the buffer desciptors of - the scatter gather list are - being used */ -#define XST_DMA_SG_BD_LOCKED 518L /* the scatter gather buffer - descriptor which is to be - copied over in the scatter - list is locked */ -#define XST_DMA_SG_NOTHING_TO_COMMIT 519L /* no buffer descriptors have been - put into the scatter gather - list to be commited */ -#define XST_DMA_SG_COUNT_EXCEEDED 521L /* the packet count threshold - specified was larger than the - total # of buffer descriptors - in the scatter gather list */ -#define XST_DMA_SG_LIST_EXISTS 522L /* the scatter gather list has - already been created */ -#define XST_DMA_SG_NO_LIST 523L /* no scatter gather list has - been created */ -#define XST_DMA_SG_BD_NOT_COMMITTED 524L /* the buffer descriptor which was - being started was not committed - to the list */ -#define XST_DMA_SG_NO_DATA 525L /* the buffer descriptor to start - has already been used by the - hardware so it can't be reused - */ -#define XST_DMA_SG_LIST_ERROR 526L /* general purpose list access - error */ -#define XST_DMA_BD_ERROR 527L /* general buffer descriptor - error */ - -/************************** IPIF statuses 531 - 550 ***************************/ - -#define XST_IPIF_REG_WIDTH_ERROR 531L /* an invalid register width - was passed into the function */ -#define XST_IPIF_RESET_REGISTER_ERROR 532L /* the value of a register at - reset was not valid */ -#define XST_IPIF_DEVICE_STATUS_ERROR 533L /* a write to the device interrupt - status register did not read - back correctly */ -#define XST_IPIF_DEVICE_ACK_ERROR 534L /* the device interrupt status - register did not reset when - acked */ -#define XST_IPIF_DEVICE_ENABLE_ERROR 535L /* the device interrupt enable - register was not updated when - other registers changed */ -#define XST_IPIF_IP_STATUS_ERROR 536L /* a write to the IP interrupt - status register did not read - back correctly */ -#define XST_IPIF_IP_ACK_ERROR 537L /* the IP interrupt status register - did not reset when acked */ -#define XST_IPIF_IP_ENABLE_ERROR 538L /* IP interrupt enable register was - not updated correctly when other - registers changed */ -#define XST_IPIF_DEVICE_PENDING_ERROR 539L /* The device interrupt pending - register did not indicate the - expected value */ -#define XST_IPIF_DEVICE_ID_ERROR 540L /* The device interrupt ID register - did not indicate the expected - value */ -#define XST_IPIF_ERROR 541L /* generic ipif error */ - -/****************** Device specific statuses 1001 - 4095 *********************/ - -/********************* Ethernet statuses 1001 - 1050 *************************/ - -#define XST_EMAC_MEMORY_SIZE_ERROR 1001L /* Memory space is not big enough - * to hold the minimum number of - * buffers or descriptors */ -#define XST_EMAC_MEMORY_ALLOC_ERROR 1002L /* Memory allocation failed */ -#define XST_EMAC_MII_READ_ERROR 1003L /* MII read error */ -#define XST_EMAC_MII_BUSY 1004L /* An MII operation is in progress */ -#define XST_EMAC_OUT_OF_BUFFERS 1005L /* Driver is out of buffers */ -#define XST_EMAC_PARSE_ERROR 1006L /* Invalid driver init string */ -#define XST_EMAC_COLLISION_ERROR 1007L /* Excess deferral or late - * collision on polled send */ - -/*********************** UART statuses 1051 - 1075 ***************************/ -#define XST_UART - -#define XST_UART_INIT_ERROR 1051L -#define XST_UART_START_ERROR 1052L -#define XST_UART_CONFIG_ERROR 1053L -#define XST_UART_TEST_FAIL 1054L -#define XST_UART_BAUD_ERROR 1055L -#define XST_UART_BAUD_RANGE 1056L - - -/************************ IIC statuses 1076 - 1100 ***************************/ - -#define XST_IIC_SELFTEST_FAILED 1076 /* self test failed */ -#define XST_IIC_BUS_BUSY 1077 /* bus found busy */ -#define XST_IIC_GENERAL_CALL_ADDRESS 1078 /* mastersend attempted with */ - /* general call address */ -#define XST_IIC_STAND_REG_RESET_ERROR 1079 /* A non parameterizable reg */ - /* value after reset not valid */ -#define XST_IIC_TX_FIFO_REG_RESET_ERROR 1080 /* Tx fifo included in design */ - /* value after reset not valid */ -#define XST_IIC_RX_FIFO_REG_RESET_ERROR 1081 /* Rx fifo included in design */ - /* value after reset not valid */ -#define XST_IIC_TBA_REG_RESET_ERROR 1082 /* 10 bit addr incl in design */ - /* value after reset not valid */ -#define XST_IIC_CR_READBACK_ERROR 1083 /* Read of the control register */ - /* didn't return value written */ -#define XST_IIC_DTR_READBACK_ERROR 1084 /* Read of the data Tx reg */ - /* didn't return value written */ -#define XST_IIC_DRR_READBACK_ERROR 1085 /* Read of the data Receive reg */ - /* didn't return value written */ -#define XST_IIC_ADR_READBACK_ERROR 1086 /* Read of the data Tx reg */ - /* didn't return value written */ -#define XST_IIC_TBA_READBACK_ERROR 1087 /* Read of the 10 bit addr reg */ - /* didn't return written value */ -#define XST_IIC_NOT_SLAVE 1088 /* The device isn't a slave */ - -/*********************** ATMC statuses 1101 - 1125 ***************************/ - -#define XST_ATMC_ERROR_COUNT_MAX 1101L /* the error counters in the ATM - controller hit the max value - which requires the statistics - to be cleared */ - -/*********************** Flash statuses 1126 - 1150 **************************/ - -#define XST_FLASH_BUSY 1126L /* Flash is erasing or programming - */ -#define XST_FLASH_READY 1127L /* Flash is ready for commands */ -#define XST_FLASH_ERROR 1128L /* Flash had detected an internal - error. Use XFlash_DeviceControl - to retrieve device specific codes - */ -#define XST_FLASH_ERASE_SUSPENDED 1129L /* Flash is in suspended erase state - */ -#define XST_FLASH_WRITE_SUSPENDED 1130L /* Flash is in suspended write state - */ -#define XST_FLASH_PART_NOT_SUPPORTED 1131L /* Flash type not supported by - driver */ -#define XST_FLASH_NOT_SUPPORTED 1132L /* Operation not supported */ -#define XST_FLASH_TOO_MANY_REGIONS 1133L /* Too many erase regions */ -#define XST_FLASH_TIMEOUT_ERROR 1134L /* Programming or erase operation - aborted due to a timeout */ -#define XST_FLASH_ADDRESS_ERROR 1135L /* Accessed flash outside its - addressible range */ -#define XST_FLASH_ALIGNMENT_ERROR 1136L /* Write alignment error */ -#define XST_FLASH_BLOCKING_CALL_ERROR 1137L /* Couldn't return immediately from - write/erase function with - XFL_NON_BLOCKING_WRITE/ERASE - option cleared */ -#define XST_FLASH_CFI_QUERY_ERROR 1138L /* Failed to query the device */ - -/*********************** SPI statuses 1151 - 1175 ****************************/ - -#define XST_SPI_MODE_FAULT 1151 /* master was selected as slave */ -#define XST_SPI_TRANSFER_DONE 1152 /* data transfer is complete */ -#define XST_SPI_TRANSMIT_UNDERRUN 1153 /* slave underruns transmit register */ -#define XST_SPI_RECEIVE_OVERRUN 1154 /* device overruns receive register */ -#define XST_SPI_NO_SLAVE 1155 /* no slave has been selected yet */ -#define XST_SPI_TOO_MANY_SLAVES 1156 /* more than one slave is being - * selected */ -#define XST_SPI_NOT_MASTER 1157 /* operation is valid only as master */ -#define XST_SPI_SLAVE_ONLY 1158 /* device is configured as slave-only - */ -#define XST_SPI_SLAVE_MODE_FAULT 1159 /* slave was selected while disabled */ -#define XST_SPI_SLAVE_MODE 1160 /* device has been addressed as slave */ -#define XST_SPI_RECEIVE_NOT_EMPTY 1161 /* device received data in slave mode */ - -#define XST_SPI_COMMAND_ERROR 1162 /* unrecognised command - qspi only */ -#define XST_SPI_POLL_DONE 1163 /* controller completed polling the - device for status */ - -/********************** OPB Arbiter statuses 1176 - 1200 *********************/ - -#define XST_OPBARB_INVALID_PRIORITY 1176 /* the priority registers have either - * one master assigned to two or more - * priorities, or one master not - * assigned to any priority - */ -#define XST_OPBARB_NOT_SUSPENDED 1177 /* an attempt was made to modify the - * priority levels without first - * suspending the use of priority - * levels - */ -#define XST_OPBARB_PARK_NOT_ENABLED 1178 /* bus parking by id was enabled but - * bus parking was not enabled - */ -#define XST_OPBARB_NOT_FIXED_PRIORITY 1179 /* the arbiter must be in fixed - * priority mode to allow the - * priorities to be changed - */ - -/************************ Intc statuses 1201 - 1225 **************************/ - -#define XST_INTC_FAIL_SELFTEST 1201 /* self test failed */ -#define XST_INTC_CONNECT_ERROR 1202 /* interrupt already in use */ - -/********************** TmrCtr statuses 1226 - 1250 **************************/ - -#define XST_TMRCTR_TIMER_FAILED 1226 /* self test failed */ - -/********************** WdtTb statuses 1251 - 1275 ***************************/ - -#define XST_WDTTB_TIMER_FAILED 1251L - -/********************** PlbArb statuses 1276 - 1300 **************************/ - -#define XST_PLBARB_FAIL_SELFTEST 1276L - -/********************** Plb2Opb statuses 1301 - 1325 *************************/ - -#define XST_PLB2OPB_FAIL_SELFTEST 1301L - -/********************** Opb2Plb statuses 1326 - 1350 *************************/ - -#define XST_OPB2PLB_FAIL_SELFTEST 1326L - -/********************** SysAce statuses 1351 - 1360 **************************/ - -#define XST_SYSACE_NO_LOCK 1351L /* No MPU lock has been granted */ - -/********************** PCI Bridge statuses 1361 - 1375 **********************/ - -#define XST_PCI_INVALID_ADDRESS 1361L - -/********************** FlexRay constants 1400 - 1409 *************************/ - -#define XST_FR_TX_ERROR 1400 -#define XST_FR_TX_BUSY 1401 -#define XST_FR_BUF_LOCKED 1402 -#define XST_FR_NO_BUF 1403 - -/****************** USB constants 1410 - 1420 *******************************/ - -#define XST_USB_ALREADY_CONFIGURED 1410 -#define XST_USB_BUF_ALIGN_ERROR 1411 -#define XST_USB_NO_DESC_AVAILABLE 1412 -#define XST_USB_BUF_TOO_BIG 1413 -#define XST_USB_NO_BUF 1414 - -/****************** HWICAP constants 1421 - 1429 *****************************/ - -#define XST_HWICAP_WRITE_DONE 1421 - - -/****************** AXI VDMA constants 1430 - 1440 *****************************/ - -#define XST_VDMA_MISMATCH_ERROR 1430 - -/*********************** NAND Flash statuses 1441 - 1459 *********************/ - -#define XST_NAND_BUSY 1441L /* Flash is erasing or - * programming - */ -#define XST_NAND_READY 1442L /* Flash is ready for commands - */ -#define XST_NAND_ERROR 1443L /* Flash had detected an - * internal error. - */ -#define XST_NAND_PART_NOT_SUPPORTED 1444L /* Flash type not supported by - * driver - */ -#define XST_NAND_OPT_NOT_SUPPORTED 1445L /* Operation not supported - */ -#define XST_NAND_TIMEOUT_ERROR 1446L /* Programming or erase - * operation aborted due to a - * timeout - */ -#define XST_NAND_ADDRESS_ERROR 1447L /* Accessed flash outside its - * addressible range - */ -#define XST_NAND_ALIGNMENT_ERROR 1448L /* Write alignment error - */ -#define XST_NAND_PARAM_PAGE_ERROR 1449L /* Failed to read parameter - * page of the device - */ -#define XST_NAND_CACHE_ERROR 1450L /* Flash page buffer error - */ - -#define XST_NAND_WRITE_PROTECTED 1451L /* Flash is write protected - */ - -/**************************** Type Definitions *******************************/ - -typedef s32 XStatus; - -/***************** Macros (Inline Functions) Definitions *********************/ - - -/************************** Function Prototypes ******************************/ - -#ifdef __cplusplus -} -#endif - -#endif /* end of protection macro */ diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/Makefile similarity index 83% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/Makefile rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/Makefile index ca8621a76..325e105c2 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/Makefile +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/Makefile @@ -42,17 +42,19 @@ CC_FLAGS = $(subst -pg, -DPROFILING, $(COMPILER_FLAGS)) ECC_FLAGS = $(subst -pg, -DPROFILING, $(EXTRA_COMPILER_FLAGS)) ifeq ($(notdir $(CC)), armr5-none-eabi-gcc) -ECC_FLAGS += -nostartfiles\ - -mfloat-abi=soft\ - -mfpu=vfpv3-d16 +ECC_FLAGS += -nostartfiles endif +ECC_FLAGS_NO_FLTO1 = $(subst -flto,,$(ECC_FLAGS)) +ECC_FLAGS_NO_FLTO = $(subst -ffat-lto-objects,,$(ECC_FLAGS_NO_FLTO1)) + RELEASEDIR=../../../lib INCLUDEDIR=../../../include INCLUDES=-I./. -I${INCLUDEDIR} OUTS = *.o - +OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c))) +ASSEMBLY_OBJECTS = $(addsuffix .o, $(basename $(wildcard *.S))) INCLUDEFILES=*.h INCLUDEFILES+=includes_ps/*.h @@ -60,7 +62,8 @@ libs: $(LIBS) standalone_libs: $(LIBSOURCES) echo "Compiling standalone R5" - $(CC) $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $^ + $(CC) $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $(filter-out _exit.c, $^) + $(CC) $(CC_FLAGS) $(ECC_FLAGS_NO_FLTO) $(INCLUDES) _exit.c $(AR) -r ${RELEASEDIR}/${LIB} ${OUTS} .PHONY: include @@ -70,5 +73,5 @@ standalone_includes: ${CP} ${INCLUDEFILES} ${INCLUDEDIR} clean: - rm -rf ${OUTS} - $(MAKE) -C COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(CC)" ARCHIVER="$(AR)" clean + rm -rf ${OBJECTS} + rm -rf ${ASSEMBLY_OBJECTS} diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/_exit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/_exit.c similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/_exit.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/_exit.c diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/_open.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/_open.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/_open.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/_open.c index 9b5a23adf..a108b7716 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/_open.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/_open.c @@ -45,7 +45,7 @@ extern "C" { */ __attribute__((weak)) s32 _open(const char8 *buf, s32 flags, s32 mode) { - (void *)buf; + (void)buf; (void)flags; (void)mode; errno = EIO; diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/_sbrk.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/_sbrk.c similarity index 95% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/_sbrk.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/_sbrk.c index 2a069ec06..967bdfc5b 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/_sbrk.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/_sbrk.c @@ -54,15 +54,10 @@ __attribute__((weak)) caddr_t _sbrk ( s32 incr ) } prev_heap = heap; + if (((heap + incr) <= HeapEndPtr) && (prev_heap != NULL)) { heap += incr; - - if (heap > HeapEndPtr){ - Status = (caddr_t) -1; - } - else if (prev_heap != NULL) { Status = (caddr_t) ((void *)prev_heap); - } - else { + } else { Status = (caddr_t) -1; } diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/abort.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/abort.c similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/abort.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/abort.c diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/asm_vectors.S b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/asm_vectors.S similarity index 93% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/asm_vectors.S rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/asm_vectors.S index 2c6f117eb..efdf629ef 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/asm_vectors.S +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/asm_vectors.S @@ -42,6 +42,7 @@ * ----- ------- -------- --------------------------------------------------- * 5.00 pkp 02/10/14 Initial version * 6.0 mus 27/07/16 Added UndefinedException handler +* 6.3 pkp 02/13/17 Added support for hard float * * * @note @@ -78,10 +79,25 @@ _vector_table: .text IRQHandler: /* IRQ vector handler */ stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code*/ +#ifndef __SOFTFP__ + + vpush {d0-d7} /* Store floating point registers */ + vmrs r1, FPSCR + push {r1} + vmrs r1, FPEXC + push {r1} +#endif bl IRQInterrupt /* IRQ vector */ +#ifndef __SOFTFP__ + + pop {r1} /* Restore floating point registers */ + vmsr FPEXC, r1 + pop {r1} + vmsr FPSCR, r1 + vpop {d0-d7} +#endif ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */ subs pc, lr, #4 /* adjust return */ - FIQHandler: /* FIQ vector handler */ stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */ FIQLoop: diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/boot.S b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/boot.S similarity index 85% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/boot.S rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/boot.S index 30b97cbfa..d9d2f1e22 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/boot.S +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/boot.S @@ -33,7 +33,26 @@ /** * @file boot.S * -* This file contains the initial startup code for the Cortex R5 processor +* @addtogroup r5_boot_code Cortex R5 Processor Boot Code +* @{ +*

boot.S

+* The boot code performs minimum configuration which is required for an +* application to run starting from processor's reset state. Below is a +* sequence illustrating what all configuration is performed before control +* reaches to main function. +* +* 1. Program vector table base for exception handling +* 2. Program stack pointer for various modes (IRQ, FIQ, supervisor, undefine, +* abort, system) +* 3. Disable instruction cache, data cache and MPU +* 4. Invalidate instruction and data cache +* 5. Configure MPU with short descriptor translation table format and program +* base address of translation table +* 6. Enable data cache, instruction cache and MPU +* 7. Enable Floating point unit +* 8. Transfer control to _start which clears BSS sections and jumping to main +* application +* * * 
 * MODIFICATION HISTORY:
@@ -52,12 +71,12 @@
 *		      to avoid intervention for lock-step mode
 * 5.05 pkp   04/11/16 Enable the comparators for non-JTAG boot mode for
 *		      lock-step to avoid putting debug logic to reset
+* 6.02 pkp   02/13/17 Added support for hard float
+* 6.6  mus   02/23/17 Enable/Disable the debug logic in non-JTAG boot mode(when
+*		      processor is in lockstep configuration), based
+*		      on the mld parameter "lockstep_mode_debug".
 *
* -* @note -* -* None. -* ******************************************************************************/ #include "xparameters.h" @@ -202,8 +221,10 @@ OKToRun: vmov d14,r1,r1 vmov d15,r1,r1 -/* restore previous value for fpu access */ +#ifdef __SOFTFP__ +/* Disable the FPU if SOFTFP is defined*/ vmsr FPEXC,r3 +#endif /* Disable MPU and caches */ mrc p15, 0, r0, c1, c0, 0 /* Read CP15 Control Register*/ @@ -218,12 +239,12 @@ OKToRun: orr r0, r0, #(0x1 << 17) /* Enable RSDIS bit 17 to disable the return stack */ orr r0, r0, #(0x1 << 16) /* Clear BP bit 15 and set BP bit 16:*/ bic r0, r0, #(0x1 << 15) /* Branch always not taken and history table updates disabled*/ - bic r0, r0, #(0x1 << 27) /* Disable B1TCM ECC check */ - bic r0, r0, #(0x1 << 26) /* Disable B0TCM ECC check */ - bic r0, r0, #(0x1 << 25) /* Disable ATCM ECC check */ - orr r0, r0, #(0x1 << 5) /* Enable ECC with no forced write through with [5:3]=b'101*/ + orr r0, r0, #(0x1 << 27) /* Enable B1TCM ECC check */ + orr r0, r0, #(0x1 << 26) /* Enable B0TCM ECC check */ + orr r0, r0, #(0x1 << 25) /* Enable ATCM ECC check */ + bic r0, r0, #(0x1 << 5) /* Generate abort on parity errors, with [5:3]=b 000*/ bic r0, r0, #(0x1 << 4) - orr r0, r0, #(0x1 << 3) + bic r0, r0, #(0x1 << 3) mcr p15, 0, r0, c1, c0, 1 /* Write ACTLR*/ dsb /* Complete all outstanding explicit memory operations*/ @@ -233,7 +254,7 @@ OKToRun: mcr p15, 0, r0, c7, c5, 0 /* invalidate icache */ mcr p15, 0, r0, c15, c5, 0 /* Invalidate entire data cache*/ isb - +#if LOCKSTEP_MODE_DEBUG == 0 /* enable fault log for lock step */ ldr r0,=RPU_GLBL_CNTL ldr r1, [r0] @@ -260,6 +281,7 @@ OKToRun: str r2, [r0] nop nop +#endif init: bl Init_MPU /* Initialize MPU */ @@ -306,3 +328,6 @@ init: .end +/** +* @} End of "addtogroup r5_boot_code". +*/ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/bspconfig.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/bspconfig.h similarity index 87% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/bspconfig.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/bspconfig.h index 8671e3fbe..9427ad054 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/bspconfig.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/bspconfig.h @@ -5,7 +5,7 @@ * Version: * DO NOT EDIT. * -* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.* +* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.* *Permission is hereby granted, free of charge, to any person obtaining a copy *of this software and associated documentation files (the Software), to deal *in the Software without restriction, including without limitation the rights @@ -37,4 +37,9 @@ * *******************************************************************/ +#ifndef BSPCONFIG_H /* prevent circular inclusions */ +#define BSPCONFIG_H /* by using protection macros */ + #define MICROBLAZE_PVR_NONE + +#endif /*end of __BSPCONFIG_H_*/ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/changelog.txt b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/changelog.txt similarity index 55% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/changelog.txt rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/changelog.txt index ad9c771e1..64144403a 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/changelog.txt +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/changelog.txt @@ -321,4 +321,219 @@ * the fault log to avoid intervention for lock-step mode and cortexr5/ * _exit.c to enable the dbg_lpd_reset once the fault log is disabled * to fix CR#947335 + * 5.5 pkp 04/11/16 Modified cortexr5/boot.S to enable comparators for non-JTAG bootmode + * in lock-step to avoid resetting the debug logic which restricts the + * access for debugger and removed enabling back of debug modules in + * cortexr5/_exit.c + * 5.5 pkp 04/13/16 Modified cortexa9/gcc/read.c to return correct number of bytes when + * read buffer is filled and removed the redundant NULL checking for + * buffer to simplify the code + * 5.5 pkp 04/13/16 Modified cortexa53/64bit/gcc/read.c and cortexa53/32bit/gcc/read.c + * to return correct number of bytes when read buffer is filled and + * removed the redundant NULL checking for buffer to simplify the code + * 5.5 pkp 04/13/16 Modified cortexr5/gcc/read.c to return correct number of bytes when + * read buffer is filled and removed the redundant NULL checking for + * buffer to simplify the code + * 5.5 pkp 04/13/16 Modified cortexa53/64bit/xpseudo_asm_gcc.h to add volatile to asm + * instruction macros to disable certain optimizations which may move + * code out of loops if optimizers believe that the code will always + * return the same result or discard asm statements if optimizers + * determine there is no need for the output variables + * 5.5 pkp 04/13/16 Modified cortexa53/64bit/xtime_l.c to add XTime_StartTimer which + * starts the timer if it is disabled and modified XTime_GetTime to + * enable the timer if it is not enabled. Also modified cortexa53/64bit/ + * sleep.c and cortexa53/64bit/usleep.c to enable the timer if it is + * disabled and read the counter value directly from register instead + * of using XTime_GetTime for optimization + * 5.5 pkp 04/13/16 Modified cortexa53/32bit/xtime_l.c to add XTime_StartTimer which + * starts the timer if it is disabled and modified XTime_GetTime to + * enable the timer if it is not enabled. Also modified cortexa53/32bit/ + * sleep.c and cortexa53/32bit/usleep.c to enable the timer if it is + * disabled and read the counter value directly from register instead + * of using XTime_GetTime for optimization + * 5.5 pkp 04/13/16 Modified cortexa53/32bit/xil_cache.c and cortexa53/64bit/xil_cache.c + * to update the Xil_DCacheInvalidate, Xil_DCacheInvalidateLine and + * Xil_DCacheInvalidateRange functions description for proper + * explaination to fix CR#949801 + * 5.5 asa 04/20/16 Added missing macros for hibernate and suspend in Microblaze BSP + * file mb_interface.h. This fixes the CR#949503. + * 5.5 asa 04/29/16 Fix for CR#951080. Updated cache APIs for HW designs where cache + * memory is not included for MicroBlaze. + * 5.5 pkp 05/06/16 Modified the cortexa9/xil_exception.h to update the macros + * Xil_EnableNestedInterrupts and Xil_DisableNestedInterrupts for fixing + * the issue of lr being corrupted to resolve CR#950468 + * 5.5 pkp 05/06/16 Modified the cortexr5/xil_exception.h to update the macros + * Xil_EnableNestedInterrupts and Xil_DisableNestedInterrupts for fixing + * the issue of lr being corrupted to resolve CR#950468 + * 6.0 kvn 05/31/16 Make Xil_AsserWait a global variable + * 6.0 pkp 06/27/16 Updated cortexr5/mpu.c to move the code related to Init_MPU to .boot + * section since it is part of boot process to fix CR#949555 + * hk 07/12/16 Correct masks for IOU SLCR GEM registers + * 6.0 pkp 07/25/16 Program the counter frequency in boot code for CortexA53 + * 6.0 asa 08/03/16 Updated sleep_common function in microblaze_sleep.c to improve the + * the accuracy of MB sleep functionality. This fixes the CR#954191. + * 6.0 mus 08/03/16 Restructured the BSP to avoid code duplication across all BSPs. + * Source code directories specific to ARM processor's are moved to src/arm + * directory(i.e. src/cortexa53,src/cortexa9 and src/cortexr5 moved to src/arm/cortexa53, + * src/arm/cortexa9 and src/arm/cortexr5 respectively).Files xil_printf.c,xil_printf.h, + * print.c,xil_io.c and xil_io.h are consolidated across all BSPs into common file each and + * consolidated files are kept at src/common directory.Files putnum.c,vectors.c,vectors.h, + * xil_exception.c and xil_exception.h are consolidated across all ARM BSPs + * into common file each and consolidated files are kept at src/arm/common directory. + * GCC source files related to file operations are consolidated and kept + * at src/arm/common/gcc directory. + * All io interfacing functions (i.e. All variants of xil_out, xil_in ) + * are made as static inline and implementation is kept in consolidated common/xil_io.h, + * xil_io.h must be included as a header file to access io interfacing functions. + * Added undefined exception handler for A53 32 bit and R5 processor + * 6.0 mus 08/11/16 Updated xtime_l.c in R5 BSP to remove implementation of XTime_SetTime API, since + * TTC counter value register is read only. + * 6.0 asa 08/15/16 Modified the signatures for functions sleep and usleep. This fixes + * the CR#956899. + * 6.0 mus 08/18/16 Defined ARMA53_32 flag in cortexa53/32bit/xparameters_ps.h and ARMR5 flag + * in cortexr5/xparameters_ps.h + * 6.0 mus 08/18/16 Added support for the the Zynq 7000s devices + * 6.0 mus 08/18/16 Removed unused variables from xil_printf.c and xplatform_info.c + * 6.0 mus 08/19/16 Modified xil_io.h to remove __LITTLE_ENDIAN__ flag check for all ARM processors + * 6.1 mus 11/03/16 Added APIs handle_stdin_parameter and handle_stdout_parameter in standalone tcl. + * ::hsi::utils::handle_stdin and ::hsi::utils::handle_stdout are taken as a base for + * these APIs and modifications are done on top of it to handle stdout/stdin + * parameters for design which doesnt have UART.It fixes CR#953681 + * 6.1 nsk 11/07/16 Added two new files xil_mem.c and xil_mem.h for xil_memcpy + * 6.2 pkp 12/14/16 Updated cortexa53/64bit/translation_table.S for upper ps DDR. The 0x800000000 - + * 0xFFFFFFFFF range is marked normal memory for the DDR size defined in hdf + * and rest of the memory in that 32GB region is marked as reserved to avoid + * any speculative access + * 6.2 pkp 12/23/16 Added support for floating point operation to Cortex-A53 64bit mode. It modified + * asm_vectors.S to implement lazy floating point context saving i.e. floating point + * access is enabled if there is any floating point operation, it is disabled by + * default. Also FPU is initally disabled for IRQ and none of the floating point + * registers are saved during normal context saving. If IRQ handler does not require + * floating point operation, the floating point registers are untouched and no need + * for saving/restoring. If IRQ handler uses any floating point operation, then floating + * point registers are saved and FPU is enabled for IRQ handler. Then floating point + * registers are restored back after servicing IRQ during normal context restoring. + * 6.2 mus 01/01/17 Updated makefiles of R5 and a53 64 bit/32 bit processors to fix error in clean + * target.It fixes the CR#966900 + * 6.2 pkp 01/22/17 Added support for EL1 non-secure execution and Hypervisor Baremetal for Cortex-A53 + * 64bit Mode. If Hypervisor_guest is selected as true in BSP settings, BSP will be built + * for EL1 Non-secure, else BSP will be built for EL3. By default hypervisor_guest is + * as false i.e. default bsp is EL3. + * 6.2 pkp 01/24/17 Updated cortexa53/64bit/boot.S to clear FPUStatus variable to make sure that it + * contains initial status of FPU i.e. disabled. In case of a warm restart execution + * when bss sections are not cleared, it may contain previously updated value which + * does not hold true once processor resumes. This fixes CR#966826. + * 6.2 asa 01/31/17 The existing Xil_DCacheDisable API first flushes the + * D caches and then disables it. The problem with that is, + * potentially there will be a small window after the cache + * flush operation and before the we disable D caches where + * we might have valid data in cache lines. In such a + * scenario disabling the D cache can lead to unknown behavior. + * The ideal solution to this is to use assembly code for + * the complete API and avoid any memory accesses. But with + * that we will end up having a huge amount on assembly code + * which is not maintainable. Changes are done to use a mix + * of assembly and C code. All local variables are put in + * registers. Also function calls are avoided in the API to + * avoid using stack memory. + * 6.2 mus 02/13/17 A53 CPU cache system can pre-fetch catch lines.So there are + * scenarios when an invalidated cache line can get pre fetched to cache. + * If that happens, the coherency between cache and memory is lost + * resulting in lost data. To avoid this kind of issue either + * user has to use dsb() or disable pre-fetching for L1 cache + * or else reduce maximum number of outstanding data prefetches allowed. + * Using dsb() while comparing data costing more performance compared to + * disabling pre-fetching/reducing maximum number of outstanding data + * prefetches for L1 Cache.The new api Xil_ConfigureL1Prefetch is added + * to disable pre-fetching/configure maximum number of outstanding data + * prefetches allowed in L1 cache system.This fixes CR#967864. + * 6.2 pkp 02/16/17 Added xil_smc.c file to provide a C wrapper for smc calling which can be + * used by cortex-A53 64bit EL1 Non-secure application. + * 6.2 kvn 03/03/17 Added support thumb mode + * 6.2 mus 03/13/17 Fixed MISRA C mandatory standard violations in ARM cortexr5 and cortexa53 BSP. + * It fixes CR#970543 + * 6.2 asa 03/16/17 Fix for CR#970859. For Mcroblaze BSP, when we enable intrusive + * profiling we see a crash. That is because the the tcl uses invalid + * HSI command. This change fixes it. + * 6.2 mus 03/22/17 Updated standalone tcl to generate xparameter XPAR_FPD_IS_CACHE_COHERENT, if + * any FPD peripheral is configured to use CCI.It fixes CR#972638 + * 6.3 mus 03/20/17 Updated cortex-r5 BSP, to add hard floating point support. + * 6.3 mus 04/17/17 Updated Cortex-a53 32 bit BSP boot code to fix bug in + * the HW coherency enablement. It fixes the CR#973287 + * 6.3 mus 04/20/17 Updated Cortex-A53 64 bit BSP boot code, to remove redundant write to the + * L2CTLR_EL1 register. It fixes the CR#974698 + * 6.4 mus 06/08/17 Updated arm/common/xil_exception.c to fix warnings in C level exception handlers + * of ARM 32 bit processor's. + * 6.4 mus 06/14/17 Updated cortexa53/64bit/gcc/asm_vectors.S to fix bug in IRQInterruptHandler code + * snippet, which checks for the FPEN bit of CPACR_EL1 register. + * 6.4 ms 05/23/17 Added PSU_PMU macro in xplatform_info.c, xparameters.h to support + * XGetPSVersion_Info function for PMUFW. + * ms 06/13/17 Added PSU_PMU macro in xplatform_info.c to support XGetPlatform_Info + * function for PMUFW. + * 6.4 mus 07/05/17 Updated Xil_In32BE function in xil_io.h to fix bug.It fixes CR#979740. + * 6.4 mus 07/25/17 Updated a53 32 bit boot code and vectors to support hard floating point + * operations.Now,VFP is being enabled in FPEXC register, through boot code + * and FPU registers are being saved/restored when irq/fiq vector is invoked. + * 6.4 adk 08/01/17 Updated standalone tcl to generate xparameter XPAR_PL_IS_CACHE_COHERENT, + * if h/w design configured with HPC port. + * 6.4 mus 08/10/17 Updated a53 64 bit translation table to mark memory as a outer shareable for + * EL1 NS execution. This change has been done to support CCI enabled IP's. + * 6.4 mus 08/11/17 Updated a53 64 bit boot code to implement ARM erratum 855873.This fixes + * CR#982209. + * 6.4 asa 08/16/17 Made several changes in the R5 MPU handling logic. Added new APIs to + * make RPU MPU handling user-friendly. This also fixes the CR-981028. + * 6.4 mus 08/17/17 Updated XGet_Zynq_UltraMp_Platform_info and XGetPSVersion_Info APIs to read + * version register through SMC call, over EL1 NS mode. This change has been done to + * support these APIs over EL1 NS mode. + * 6.5 mus 10/20/17 Updated standalone.tcl to fix bug in mb_can_handle_exceptions_in_delay_slots proc, + * it fixes CR#987464. + * 6.6 mus 12/07/17 Updated cortexa9/xil_errata.h and cortexa9/xil_cache.c to remove Errata 753970. + * It fixes CR#989132. + * srm 10/18/17 Updated all the sleep routines in a9,a53,R5,microblaze. Now the sleep routines + * will use the timer specified by the user to provide delay. A9 and A53 can use + * Global timer or TTC. R5 can use TTC or the machine cycles. Microblaze can use + * machine cycles or Axi timer. Updated standalone.tcl and standalone.mld files + * to support the sleep configuration Added new API's for the Axi timer in + * microblaze and TTC in ARM. Added two new files, xil_sleeptimer.c and + * xil_sleeptimer.h in ARM for the common sleep routines and 1 new file, + * xil_sleepcommon.c in Standalone-common for sleep/usleep API's. + * 6.6 hk 12/15/17 Export platform macros to bspconfig.h based on the processor. + * 6.6 asa 1/16/18 Ensure C stack information for A9 are flushed out from L1 D cache + * or L2 cache only when the respective caches are enabled. This fixes CR-922023. + * 6.6 mus 01/19/18 Updated asm_vectors.S and boot.S in Cortexa53 64 bit BSP, to add isb + * after writing to cpacr_el1/cptr_el3 registers. It would ensure + * disabling/enabling of floating-point unit, before any subsequent + * instruction. + * 6.6 mus 01/30/18 Updated hypervisor enabled Cortexa53 64 bit BSP, to add xen PV console + * support. Now, xil_printf would use PV console instead of UART in case of + * hypervisor enabled BSP. + * 6.6 mus 02/02/18 Updated get_connected_if proc in standalone tcl to detect the HPC port + * configured with smart interconnect.It fixes CR#990318. + * 6.6 srm 02/10/18 Updated csu_wdt interrupt to the correct value. Fixes CR#992229 + * 6.6 asa 02/12/18 Fix for heap handling for ARM platforms. CR#993932. + * 6.6 mus 02/19/18 Updated standalone.tcl to fix bug in handle_profile_opbtimer proc, + * CR#995014. + * 6.6 mus 02/23/18 Presently Cortex R5 BSP boot code is disabling the debug logic in +* non-JTAG boot mode, when processor is in lockstep configuration. +* This behavior is restricting application debugging in non-JTAG boot +* mode. To get rid of this restriction, added new mld parameter +* "lockstep_mode_debug", to enable/disable debug logic from BSP +* settings. Now, debug logic can be enabled through BSP settings, +* by modifying value of parameter "lockstep_mode_debug" as "true". +* It fixes CR#993896. + * 6.6.mus 02/27/18 Updated Xil_DCacheInvalidateRange and +* Xil_ICacheInvalidateRange APIs in Cortexa53 64 bit BSP, to fix bug +* in handling upper DDR addresses.It fixes CR#995581. +* 6.6 mus 03/12/18 Updated makefile of Cortexa53 32bit BSP to add includes_ps directory +* in the list of include paths. This change allows applications/BSP +* files to include .h files in include_ps directory. +* 6.6 mus 03/16/18 By default CPUACTLR_EL1 is accessible only from EL3, it +* results into abort if accessed from EL1 non secure privilege +* level. Updated Xil_ConfigureL1Prefetch function in Cortexa53 64 bit BSP +* to avoid CPUACTLR_EL1 access from privile levels other than EL3. +* 6.6 mus 03/16/18 Updated hypervisor enabled BSP to use PV console, based on the +* XEN_USE_PV_CONSOLE flag. By deafault hypervisor enabled BSP would +* use UART console, PV console can be enabled by appending + "-DXEN_USE_PV_CONSOLE" to the BSP extra compiler flags. + * *****************************************************************************************/ diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/close.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/close.c similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/close.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/close.c diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/config.make b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/config.make similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/config.make rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/config.make diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/cpu_init.S b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/cpu_init.S similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/cpu_init.S rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/cpu_init.S diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/errno.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/errno.c similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/errno.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/errno.c diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/fcntl.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/fcntl.c similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/fcntl.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/fcntl.c diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/fstat.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/fstat.c similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/fstat.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/fstat.c diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/getpid.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/getpid.c similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/getpid.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/getpid.c diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/inbyte.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/inbyte.c similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/inbyte.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/inbyte.c diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xddr_xmpu0_cfg.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/includes_ps/xddr_xmpu0_cfg.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xddr_xmpu0_cfg.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/includes_ps/xddr_xmpu0_cfg.h diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xddr_xmpu1_cfg.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/includes_ps/xddr_xmpu1_cfg.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xddr_xmpu1_cfg.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/includes_ps/xddr_xmpu1_cfg.h diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xddr_xmpu2_cfg.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/includes_ps/xddr_xmpu2_cfg.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xddr_xmpu2_cfg.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/includes_ps/xddr_xmpu2_cfg.h diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xddr_xmpu3_cfg.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/includes_ps/xddr_xmpu3_cfg.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xddr_xmpu3_cfg.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/includes_ps/xddr_xmpu3_cfg.h diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xddr_xmpu4_cfg.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/includes_ps/xddr_xmpu4_cfg.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xddr_xmpu4_cfg.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/includes_ps/xddr_xmpu4_cfg.h diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xddr_xmpu5_cfg.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/includes_ps/xddr_xmpu5_cfg.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xddr_xmpu5_cfg.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/includes_ps/xddr_xmpu5_cfg.h diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xfpd_slcr.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/includes_ps/xfpd_slcr.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xfpd_slcr.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/includes_ps/xfpd_slcr.h diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xfpd_slcr_secure.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/includes_ps/xfpd_slcr_secure.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xfpd_slcr_secure.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/includes_ps/xfpd_slcr_secure.h diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xfpd_xmpu_cfg.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/includes_ps/xfpd_xmpu_cfg.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xfpd_xmpu_cfg.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/includes_ps/xfpd_xmpu_cfg.h diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xfpd_xmpu_sink.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/includes_ps/xfpd_xmpu_sink.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xfpd_xmpu_sink.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/includes_ps/xfpd_xmpu_sink.h diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xiou_secure_slcr.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/includes_ps/xiou_secure_slcr.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xiou_secure_slcr.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/includes_ps/xiou_secure_slcr.h diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xiou_slcr.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/includes_ps/xiou_slcr.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xiou_slcr.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/includes_ps/xiou_slcr.h diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xlpd_slcr.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/includes_ps/xlpd_slcr.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xlpd_slcr.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/includes_ps/xlpd_slcr.h diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xlpd_slcr_secure.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/includes_ps/xlpd_slcr_secure.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xlpd_slcr_secure.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/includes_ps/xlpd_slcr_secure.h diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xlpd_xppu.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/includes_ps/xlpd_xppu.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xlpd_xppu.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/includes_ps/xlpd_xppu.h diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xlpd_xppu_sink.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/includes_ps/xlpd_xppu_sink.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xlpd_xppu_sink.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/includes_ps/xlpd_xppu_sink.h diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xocm_xmpu_cfg.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/includes_ps/xocm_xmpu_cfg.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/includes_ps/xocm_xmpu_cfg.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/includes_ps/xocm_xmpu_cfg.h diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/isatty.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/isatty.c similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/isatty.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/isatty.c diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/kill.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/kill.c similarity index 89% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/kill.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/kill.c index f70c2849b..fc2f89d6c 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/kill.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/kill.c @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved. +* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -35,7 +35,7 @@ #ifdef __cplusplus extern "C" { - __attribute__((weak)) s32 _kill(s32 pid, s32 sig); + __attribute__((weak)) int _kill(pid_t pid, int sig); } #endif @@ -43,7 +43,7 @@ extern "C" { * kill -- go out via exit... */ -__attribute__((weak)) s32 kill(s32 pid, s32 sig) +__attribute__((weak)) int kill(pid_t pid, int sig) { if(pid == 1) { _exit(sig); @@ -51,7 +51,7 @@ __attribute__((weak)) s32 kill(s32 pid, s32 sig) return 0; } -__attribute__((weak)) s32 _kill(s32 pid, s32 sig) +__attribute__((weak)) int _kill(pid_t pid, int sig) { if(pid == 1) { _exit(sig); diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/lseek.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/lseek.c similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/lseek.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/lseek.c diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/mpu.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/mpu.c similarity index 93% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/mpu.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/mpu.c index 55cdd4992..6d7054eca 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/mpu.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/mpu.c @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved. +* Copyright (C) 2014 - 2017 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -44,6 +44,7 @@ * 5.04 pkp 12/18/15 Updated MPU initialization as per the proper address map * 6.00 pkp 06/27/16 moving the Init_MPU code to .boot section since it is a * part of processor boot process +* 6.2 mus 01/27/17 Updated to support IAR compiler * * * @note @@ -102,10 +103,16 @@ static const struct { }; /************************** Function Prototypes ******************************/ +#if defined (__GNUC__) void Init_MPU(void) __attribute__((__section__(".boot"))); static void Xil_SetAttribute(u32 addr, u32 reg_size,s32 reg_num, u32 attrib) __attribute__((__section__(".boot"))); static void Xil_DisableMPURegions(void) __attribute__((__section__(".boot"))); - +#elif defined (__ICCARM__) +#pragma default_function_attributes = @ ".boot" +void Init_MPU(void); +static void Xil_SetAttribute(u32 addr, u32 reg_size,s32 reg_num, u32 attrib); +static void Xil_DisableMPURegions(void); +#endif /***************************************************************************** * * Initialize MPU for a given address map and Enabled the background Region in @@ -122,7 +129,7 @@ static void Xil_DisableMPURegions(void) __attribute__((__section__(".boot"))); void Init_MPU(void) { u32 Addr; - u32 RegSize; + u32 RegSize = 0U; u32 Attrib; u32 RegNum = 0, i; u64 size; @@ -270,11 +277,15 @@ static void Xil_SetAttribute(u32 addr, u32 reg_size,s32 reg_num, u32 attrib) ******************************************************************************/ static void Xil_DisableMPURegions(void) { - u32 Temp; - u32 Index; + u32 Temp = 0U; + u32 Index = 0U; for (Index = 0; Index <= 15; Index++) { mtcp(XREG_CP15_MPU_MEMORY_REG_NUMBER,Index); +#if defined (__GNUC__) Temp = mfcp(XREG_CP15_MPU_REG_SIZE_EN); +#elif defined (__ICCARM__) + mfcp(XREG_CP15_MPU_REG_SIZE_EN,Temp); +#endif Temp &= (~REGION_EN); dsb(); mtcp(XREG_CP15_MPU_REG_SIZE_EN,Temp); @@ -283,3 +294,7 @@ static void Xil_DisableMPURegions(void) } } + +#if defined (__ICCARM__) +#pragma default_function_attributes = +#endif diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/open.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/open.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/open.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/open.c index 4b51839fd..85e9ce402 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/open.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/open.c @@ -44,7 +44,7 @@ extern "C" { */ __attribute__((weak)) s32 open(char8 *buf, s32 flags, s32 mode) { - (void *)buf; + (void)buf; (void)flags; (void)mode; errno = EIO; diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/outbyte.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/outbyte.c similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/outbyte.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/outbyte.c diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/print.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/print.c similarity index 85% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/print.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/print.c index b966480a8..da7e768d0 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/print.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/print.c @@ -21,11 +21,16 @@ void print(const char8 *ptr) { +#if HYP_GUEST && EL1_NONSECURE && XEN_USE_PV_CONSOLE + XPVXenConsole_Write(ptr); +#else #ifdef STDOUT_BASEADDRESS - while (*ptr) { - outbyte (*ptr++); + while (*ptr != (char8)0) { + outbyte (*ptr); + ptr++; } #else (void)ptr; #endif +#endif } diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/putnum.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/putnum.c similarity index 96% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/putnum.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/putnum.c index 33c3a6c44..aaf9edee7 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/putnum.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/putnum.c @@ -37,7 +37,7 @@ void putnum(u32 num) ptr = buf; for (cnt = 7 ; cnt >= 0 ; cnt--) { - digit = ((num >> ((u16)cnt * 4U)) & 0xfU); + digit = (num >> (cnt * 4U)) & 0x0000000fU; if ((digit <= 9U) && (ptr != NULL)) { digit += (u32)'0'; diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/read.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/read.c similarity index 82% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/read.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/read.c index 1cad3272a..7f7b7d261 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/read.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/read.c @@ -51,25 +51,21 @@ read (s32 fd, char8* buf, s32 nbytes) { #ifdef STDIN_BASEADDRESS s32 i; + s32 numbytes = 0; char8* LocalBuf = buf; (void)fd; - for (i = 0; i < nbytes; i++) { - if(LocalBuf != NULL) { - LocalBuf += i; - } - if(LocalBuf != NULL) { - *LocalBuf = inbyte(); - if ((*LocalBuf == '\n' )|| (*LocalBuf == '\r')) { - break; + if(LocalBuf != NULL) { + for (i = 0; i < nbytes; i++) { + numbytes++; + *(LocalBuf + i) = inbyte(); + if ((*(LocalBuf + i) == '\n' )|| (*(LocalBuf + i) == '\r')) { + break; } } - if(LocalBuf != NULL) { - LocalBuf -= i; - } } - return (i + 1); + return numbytes; #else (void)fd; (void)buf; @@ -83,25 +79,21 @@ _read (s32 fd, char8* buf, s32 nbytes) { #ifdef STDIN_BASEADDRESS s32 i; + s32 numbytes = 0; char8* LocalBuf = buf; (void)fd; - for (i = 0; i < nbytes; i++) { - if(LocalBuf != NULL) { - LocalBuf += i; - } - if(LocalBuf != NULL) { - *LocalBuf = inbyte(); - if ((*LocalBuf == '\n' )|| (*LocalBuf == '\r')) { - break; + if(LocalBuf != NULL) { + for (i = 0; i < nbytes; i++) { + numbytes++; + *(LocalBuf + i) = inbyte(); + if ((*(LocalBuf + i) == '\n' )|| (*(LocalBuf + i) == '\r')) { + break; } } - if(LocalBuf != NULL) { - LocalBuf -= i; - } } - return (i + 1); + return numbytes; #else (void)fd; (void)buf; diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/sbrk.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/sbrk.c similarity index 94% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/sbrk.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/sbrk.c index 64d5156af..87a753d49 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/sbrk.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/sbrk.c @@ -51,12 +51,8 @@ __attribute__((weak)) char8 *sbrk (s32 nbytes) static char8 *heap_ptr = HeapBase; base = heap_ptr; - if(heap_ptr != NULL) { + if((heap_ptr != NULL) && (heap_ptr + nbytes <= (char8 *)&HeapLimit + 1)) { heap_ptr += nbytes; - } - -/* if (heap_ptr <= ((char8 *)&_heap_end + 1)) */ - if (heap_ptr <= ((char8 *)&HeapLimit + 1)) { return base; } else { errno = ENOMEM; diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/sleep.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/sleep.c similarity index 61% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/sleep.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/sleep.c index 74c7ec215..d5e56c526 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/sleep.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/sleep.c @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved. +* Copyright (C) 2014 - 2017 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -33,8 +33,9 @@ * * @file sleep.c * -* This function provides a second delay using the Global Timer register in -* the ARM Cortex R5 MP core. +* This function supports user configurable sleep implementation. +* This provides delay in seconds by using the Timer specified by +* the user in the ARM Cortex R5 MP core. * * 
 * MODIFICATION HISTORY:
@@ -50,6 +51,9 @@
 * 5.04	pkp		 03/11/16 Compare the counter value to previously read value
 *						  to detect the overflow for TTC3
 * 6.0   asa      08/15/16 Updated the sleep signature. Fix for CR#956899.
+* 6.6	srm      10/18/17 Updated sleep routines to support user configurable
+*			  implementation. Now sleep routines will use TTC
+*                         instance specified by user.
 *
* ******************************************************************************/ @@ -59,6 +63,10 @@ #include "xtime_l.h" #include "xparameters.h" +#if defined (SLEEP_TIMER_BASEADDR) +#include "xil_sleeptimer.h" +#endif + /*****************************************************************************/ /* * @@ -68,59 +76,45 @@ * * @return 0 always * -* @note The sleep API is implemented using TTC3 counter 0 timer if present. -* When TTC3 is absent, sleep is implemented using assembly -* instructions which is tested with instruction and data caches -* enabled and it gives proper delay. It may give more delay than -* exepcted when caches are disabled. If interrupt comes when sleep -* using assembly instruction is being executed, the delay may be -* greater than what is expected since once the interrupt is served -* count resumes from where it was interrupted unlike the case of TTC3 -* where counter keeps running while interrupt is being served. +* @note By default, sleep is implemented using TTC3. Although user is +* given an option to select other instances of TTC. When the user +* selects other instances of TTC, sleep is implemented by that +* specific TTC instance. If the user didn't select any other instance +* of TTC specifically and when TTC3 is absent, sleep is implemented +* using assembly instructions which is tested with instruction and +* data caches enabled and it gives proper delay. It may give more +* delay than exepcted when caches are disabled. If interrupt comes +* when sleep using assembly instruction is being executed, the delay +* may be greater than what is expected since once the interrupt is +* served count resumes from where it was interrupted unlike the case +* of TTC3 where counter keeps running while interrupt is being served. * ****************************************************************************/ -unsigned sleep(unsigned int seconds) +unsigned sleep_R5(unsigned int seconds) { -#ifdef SLEEP_TIMER_BASEADDR - u64 tEnd; - u64 tCur; - u32 TimeHighVal; - XTime TimeLowVal1; - XTime TimeLowVal2; - - TimeHighVal = 0; - - XTime_GetTime(&TimeLowVal1); - tEnd = (u64)TimeLowVal1 + (((u64) seconds) * COUNTS_PER_SECOND); - - do - { - - XTime_GetTime(&TimeLowVal2); - if (TimeLowVal2 < TimeLowVal1) { - TimeHighVal++; - } - - TimeLowVal1 = TimeLowVal2; - tCur = (((u64) TimeHighVal) << 32U) | (u64)TimeLowVal2; - - } while (tCur < tEnd); - - return 0; +#if defined (SLEEP_TIMER_BASEADDR) + Xil_SleepTTCCommon(seconds, COUNTS_PER_SECOND); #else +#if defined (__GNUC__) __asm__ __volatile__ ( - " push {r0,r1} \n\t" - " mov r0, %[sec] \n\t" - " 1: \n\t" - " mov r1, %[iter] \n\t" - " 2: \n\t" - " subs r1, r1, #0x1 \n\t" - " bne 2b \n\t" - " subs r0,r0,#0x1 \n\t" - " bne 1b \n\t" - " pop {r0,r1} \n\t" - :: [iter] "r" (ITERS_PER_SEC), [sec] "r" (seconds) - ); +#elif defined (__ICCARM__) + __asm volatile ( #endif + "push {r0,r1,r3} \n" + "mov r0, %[sec] \n" + "mov r1, %[iter] \n" + "1: \n" + "mov r3, r1\n" + "2: \n" + "subs r3, r3, #0x1 \n" + "bne 2b \n" + "subs r0, r0, #0x1 \n" + "bne 1b \n" + "pop {r0,r1,r3} \n" + ::[iter] "r" (ITERS_PER_SEC), [sec] "r" (seconds) + ); +#endif + +return 0; } diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/sleep.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/sleep.h new file mode 100644 index 000000000..f53b2d8c8 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/sleep.h @@ -0,0 +1,119 @@ +/****************************************************************************** +* +* Copyright (C) 2014 - 2017 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +/*****************************************************************************/ +/** +* @file sleep.h +* +* This header file contains ARM Cortex A53,A9,R5,Microblaze specific sleep +* related APIs. +* +* 
+* MODIFICATION HISTORY :
+*
+* Ver   Who  Date	 Changes
+* ----- ---- -------- -------------------------------------------------------
+* 6.6   srm  11/02/17 Added processor specific sleep rountines
+*								 function prototypes.
+*
+*
+* +******************************************************************************/ + +#ifndef SLEEP_H +#define SLEEP_H + +#include "xil_types.h" +#include "xil_io.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/*****************************************************************************/ +/** +* +* This macro polls an address periodically until a condition is met or till the +* timeout occurs. +* The minimum timeout for calling this macro is 100us. If the timeout is less +* than 100us, it still waits for 100us. Also the unit for the timeout is 100us. +* If the timeout is not a multiple of 100us, it waits for a timeout of +* the next usec value which is a multiple of 100us. +* +* @param IO_func - accessor function to read the register contents. +* Depends on the register width. +* @param ADDR - Address to be polled +* @param VALUE - variable to read the value +* @param COND - Condition to checked (usually involves VALUE) +* @param TIMEOUT_US - timeout in micro seconds +* +* @return 0 - when the condition is met +* -1 - when the condition is not met till the timeout period +* +* @note none +* +*****************************************************************************/ +#define Xil_poll_timeout(IO_func, ADDR, VALUE, COND, TIMEOUT_US) \ + ( { \ + u64 timeout = TIMEOUT_US/100; \ + if(TIMEOUT_US%100!=0) \ + timeout++; \ + for(;;) { \ + VALUE = IO_func(ADDR); \ + if(COND) \ + break; \ + else { \ + usleep(100); \ + timeout--; \ + if(timeout==0) \ + break; \ + } \ + } \ + (timeout>0) ? 0 : -1; \ + } ) + +void usleep(unsigned long useconds); +void sleep(unsigned int seconds); +int usleep_R5(unsigned long useconds); +unsigned sleep_R5(unsigned int seconds); +int usleep_MB(unsigned long useconds); +unsigned sleep_MB(unsigned int seconds); +int usleep_A53(unsigned long useconds); +unsigned sleep_A53(unsigned int seconds); +int usleep_A9(unsigned long useconds); +unsigned sleep_A9(unsigned int seconds); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/uart.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/uart.c similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/uart.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/uart.c diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/unlink.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/unlink.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/unlink.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/unlink.c index 84e44a47c..d0cc6807b 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/unlink.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/unlink.c @@ -44,7 +44,7 @@ extern "C" { */ __attribute__((weak)) sint32 unlink(char8 *path) { - (void *)path; + (void) path; errno = EIO; return (-1); } diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/usleep.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/usleep.c similarity index 62% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/usleep.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/usleep.c index ff01dfd73..a245f4f78 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/usleep.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/usleep.c @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved. +* Copyright (C) 2014 - 2017 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -34,7 +34,8 @@ * * @file usleep.c * -* This function provides a microsecond delay using the Global Timer register in +* This function supports user configurable sleep implementation. +* This provides a microsecond delay using the timer specified by the user in * the ARM Cortex R5 MP core. * * 
@@ -51,6 +52,10 @@
 * 5.04	pkp		 03/11/16 Compare the counter value to previously read value
 *						  to detect the overflow for TTC3
 * 6.0   asa      08/15/16 Updated the usleep signature. Fix for CR#956899.
+* 6.6	srm      10/18/17 Updated sleep routines to support user configurable
+*			  implementation. Now sleep routines will use TTC
+*                         instance specified by user.
+*
 *
* ******************************************************************************/ @@ -63,6 +68,10 @@ #include "xpseudo_asm.h" #include "xreg_cortexr5.h" +#if defined (SLEEP_TIMER_BASEADDR) +#include "xil_sleeptimer.h" +#endif + /*****************************************************************************/ /** * @@ -72,57 +81,45 @@ * * @return 0 always * -* @note The usleep API is implemented using TTC3 counter 0 timer if present -* When TTC3 is absent, usleep is implemented using assembly -* instructions which is tested with instruction and data caches -* enabled and it gives proper delay. It may give more delay than -* exepcted when caches are disabled. If interrupt comes when usleep -* using assembly instruction is being executed, the delay may be -* greater than what is expected since once the interrupt is served -* count resumes from where it was interrupted unlike the case of TTC3 -* where counter keeps running while interrupt is being served. +* @note By default, usleep is implemented using TTC3. Although user is +* given an option to select other instances of TTC. When the user +* selects other instances of TTC, usleep is implemented by that +* specific TTC instance. If the user didn't select any other instance +* of TTC specifically and when TTC3 is absent, usleep is implemented +* using assembly instructions which is tested with instruction and +* data caches enabled and it gives proper delay. It may give more +* delay than exepcted when caches are disabled. If interrupt comes +* when usleep using assembly instruction is being executed, the delay +* may be greater than what is expected since once the interrupt is +* served count resumes from where it was interrupted unlike the case +* of TTC3 where counter keeps running while interrupt is being served. * ****************************************************************************/ -int usleep(unsigned long useconds) +int usleep_R5(unsigned long useconds) { - -#ifdef SLEEP_TIMER_BASEADDR - u64 tEnd; - u64 tCur; - u32 TimeHighVal; - XTime TimeLowVal1; - XTime TimeLowVal2; - - TimeHighVal = 0; - - XTime_GetTime(&TimeLowVal1); - tEnd = (u64)TimeLowVal1 + (((u64) useconds) * COUNTS_PER_USECOND); - - do - { - XTime_GetTime(&TimeLowVal2); - if (TimeLowVal2 < TimeLowVal1) { - TimeHighVal++; - } - TimeLowVal1 = TimeLowVal2; - tCur = (((u64) TimeHighVal) << 32U) | (u64)TimeLowVal2; - } while (tCur < tEnd); - - return 0; +#if defined (SLEEP_TIMER_BASEADDR) + Xil_SleepTTCCommon(useconds, COUNTS_PER_USECOND); #else +#if defined (__GNUC__) __asm__ __volatile__ ( - " push {r0,r1} \n\t" - " mov r0, %[usec] \n\t" - " 1: \n\t" - " mov r1, %[iter] \n\t" - " 2: \n\t" - " subs r1, r1, #0x1 \n\t" - " bne 2b \n\t" - " subs r0,r0,#0x1 \n\t" - " bne 1b \n\t" - " pop {r0,r1} \n\t" - :: [iter] "r" (ITERS_PER_USEC), [usec] "r" (useconds) - ); +#elif defined (__ICCARM__) + __asm volatile ( #endif + "push {r0,r1,r3} \n" + "mov r0, %[usec] \n" + "mov r1, %[iter] \n" + "1: \n" + "mov r3, r1 \n" + "2: \n" + "subs r3, r3, #0x1\n" + "bne 2b \n" + "subs r0, r0, #0x1 \n" + "bne 1b \n" + "pop {r0,r1,r3} \n" + ::[iter] "r" (ITERS_PER_USEC), [usec] "r" (useconds) + ); +#endif + +return 0; } diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/vectors.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/vectors.c similarity index 81% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/vectors.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/vectors.c index 94a935d77..0a3616328 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/vectors.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/vectors.c @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved. +* Copyright (C) 2009 - 2016 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -41,6 +41,9 @@ * Ver Who Date Changes * ----- ---- -------- --------------------------------------------------- * 1.00a ecm 10/20/09 Initial version, moved over from bsp area +* 6.0 mus 27/07/16 Consolidated vectors for a53,a9 and r5 processor +* and added UndefinedException for a53 32 bit and r5 +* processor * * * @note @@ -70,25 +73,6 @@ extern XExc_VectorTableEntry XExc_VectorTable[]; /************************** Function Prototypes ******************************/ -/*****************************************************************************/ -/** -* -* This is the C level wrapper for the Undefined exception called from the -* vectors.s file. -* -* @param None. -* -* @return None. -* -* @note None. -* -******************************************************************************/ -void UndefinedException(void) -{ - XExc_VectorTable[XIL_EXCEPTION_ID_UNDEFINED_INT].Handler(XExc_VectorTable[ - XIL_EXCEPTION_ID_UNDEFINED_INT].Data); -} - /*****************************************************************************/ /** @@ -128,6 +112,26 @@ void IRQInterrupt(void) XIL_EXCEPTION_ID_IRQ_INT].Data); } +#if !defined (__aarch64__) +/*****************************************************************************/ +/** +* +* This is the C level wrapper for the Undefined exception called from the +* vectors.s file. +* +* @param None. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void UndefinedException(void) +{ + XExc_VectorTable[XIL_EXCEPTION_ID_UNDEFINED_INT].Handler(XExc_VectorTable[ + XIL_EXCEPTION_ID_UNDEFINED_INT].Data); +} + /*****************************************************************************/ /** * @@ -184,3 +188,44 @@ void PrefetchAbortInterrupt(void) XExc_VectorTable[XIL_EXCEPTION_ID_PREFETCH_ABORT_INT].Handler( XExc_VectorTable[XIL_EXCEPTION_ID_PREFETCH_ABORT_INT].Data); } +#else + +/*****************************************************************************/ +/** +* +* This is the C level wrapper for the Synchronous Interrupt called from the vectors.s +* file. +* +* @param None. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void SynchronousInterrupt(void) +{ + XExc_VectorTable[XIL_EXCEPTION_ID_SYNC_INT].Handler(XExc_VectorTable[ + XIL_EXCEPTION_ID_SYNC_INT].Data); +} + +/*****************************************************************************/ +/** +* +* This is the C level wrapper for the SError Interrupt called from the +* vectors.s file. +* +* @param None. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void SErrorInterrupt(void) +{ + XExc_VectorTable[XIL_EXCEPTION_ID_SERROR_ABORT_INT].Handler( + XExc_VectorTable[XIL_EXCEPTION_ID_SERROR_ABORT_INT].Data); +} + +#endif diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/vectors.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/vectors.h similarity index 92% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/vectors.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/vectors.h index 5c423b8f7..bb599b560 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/vectors.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/vectors.h @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved. +* Copyright (C) 2009 - 2016 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -41,6 +41,7 @@ * Ver Who Date Changes * ----- ---- -------- --------------------------------------------------- * 1.00a ecm 10/20/10 Initial version, moved over from bsp area +* 6.0 mus 07/27/16 Consolidated vectors for a9,a53 and r5 processors * * * @note @@ -67,13 +68,18 @@ extern "C" { /************************** Constant Definitions *****************************/ /************************** Function Prototypes ******************************/ -void UndefinedException(void); + void FIQInterrupt(void); void IRQInterrupt(void); +#if !defined (__aarch64__) void SWInterrupt(void); void DataAbortInterrupt(void); void PrefetchAbortInterrupt(void); - +void UndefinedException(void); +#else +void SynchronousInterrupt(void); +void SErrorInterrupt(void); +#endif #ifdef __cplusplus } diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/write.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/write.c similarity index 93% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/write.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/write.c index aaa879e73..9389f610a 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/write.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/write.c @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved. +* Copyright (C) 2009 - 2018 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -82,6 +82,14 @@ write (sint32 fd, char8* buf, sint32 nbytes) __attribute__((weak)) sint32 _write (sint32 fd, char8* buf, sint32 nbytes) { +#if HYP_GUEST && EL1_NONSECURE && XEN_USE_PV_CONSOLE + sint32 length; + + (void)fd; + (void)nbytes; + length = XPVXenConsole_Write(buf); + return length; +#else #ifdef STDOUT_BASEADDRESS s32 i; char8* LocalBuf = buf; @@ -108,5 +116,6 @@ _write (sint32 fd, char8* buf, sint32 nbytes) (void)nbytes; return 0; #endif +#endif } #endif diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xbasic_types.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xbasic_types.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xbasic_types.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xbasic_types.h diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xdebug.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xdebug.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xdebug.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xdebug.h diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xenv.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xenv.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xenv.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xenv.h diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xenv_standalone.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xenv_standalone.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xenv_standalone.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xenv_standalone.h diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil-crt0.S b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil-crt0.S similarity index 87% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil-crt0.S rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil-crt0.S index 6715a6ce5..5c4fe7465 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil-crt0.S +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil-crt0.S @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved. +* Copyright (C) 2014 - 2017 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -42,6 +42,12 @@ * 5.04 pkp 12/18/15 Initialized global constructor for C++ applications * 5.04 pkp 02/19/16 Added timer configuration using XTime_StartTimer API when * TTC3 is present +* 6.4 asa 08/16/17 Added call to Xil_InitializeExistingMPURegConfig to +* initialize the MPU configuration table with the MPU +* configurations already set in Init_Mpu function. +* 6.6 srm 10/18/17 Updated the timer configuration with XTime_StartTTCTimer. +* Now the timer instance as specified by the user will be +* started. * * * @note @@ -123,11 +129,11 @@ test_boot_status: /* set stack pointer */ ldr r13,.Lstack /* stack address */ - /* configure the timer if TTC3 is present */ + /* configure the timer if TTC is present */ #ifdef SLEEP_TIMER_BASEADDR - bl XTime_StartTimer + bl XTime_StartTTCTimer #endif - + bl Xil_InitializeExistingMPURegConfig /* Initialize MPU config */ /* run global constructors */ bl __libc_init_array diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xil_assert.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_assert.c similarity index 81% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xil_assert.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_assert.c index 42db07deb..59b3c1c98 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xil_assert.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_assert.c @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved. +* Copyright (C) 2009 - 2016 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -42,6 +42,7 @@ * Ver Who Date Changes * ----- ---- -------- ------------------------------------------------------- * 1.00a hbm 07/14/09 Initial release +* 6.0 kvn 05/31/16 Make Xil_AsserWait a global variable * * ******************************************************************************/ @@ -71,7 +72,7 @@ u32 Xil_AssertStatus; * such that it does not wait infinitely. Use the debugger to disable the * waiting during testing of asserts. */ -/*s32 Xil_AssertWait = 1*/ +s32 Xil_AssertWait = 1; /* The callback function to be invoked when an assert is taken */ static Xil_AssertCallback Xil_AssertCallbackRoutine = NULL; @@ -81,12 +82,13 @@ static Xil_AssertCallback Xil_AssertCallbackRoutine = NULL; /*****************************************************************************/ /** * -* Implement assert. Currently, it calls a user-defined callback function -* if one has been set. Then, it potentially enters an infinite loop depending -* on the value of the Xil_AssertWait variable. +* @brief Implement assert. Currently, it calls a user-defined callback +* function if one has been set. Then, it potentially enters an +* infinite loop depending on the value of the Xil_AssertWait +* variable. * -* @param file is the name of the filename of the source -* @param line is the linenumber within File +* @param file: filename of the source +* @param line: linenumber within File * * @return None. * @@ -95,7 +97,6 @@ static Xil_AssertCallback Xil_AssertCallbackRoutine = NULL; ******************************************************************************/ void Xil_Assert(const char8 *File, s32 Line) { - s32 Xil_AssertWait = 1; /* if the callback has been set then invoke it */ if (Xil_AssertCallbackRoutine != 0) { (*Xil_AssertCallbackRoutine)(File, Line); @@ -111,10 +112,10 @@ void Xil_Assert(const char8 *File, s32 Line) /*****************************************************************************/ /** * -* Set up a callback function to be invoked when an assert occurs. If there -* was already a callback installed, then it is replaced. +* @brief Set up a callback function to be invoked when an assert occurs. +* If a callback is already installed, then it will be replaced. * -* @param routine is the callback to be invoked when an assert is taken +* @param routine: callback to be invoked when an assert is taken * * @return None. * @@ -129,11 +130,11 @@ void Xil_AssertSetCallback(Xil_AssertCallback Routine) /*****************************************************************************/ /** * -* Null handler function. This follows the XInterruptHandler signature for -* interrupt handlers. It can be used to assign a null handler (a stub) to an -* interrupt controller vector table. +* @brief Null handler function. This follows the XInterruptHandler +* signature for interrupt handlers. It can be used to assign a null +* handler (a stub) to an interrupt controller vector table. * -* @param NullParameter is an arbitrary void pointer and not used. +* @param NullParameter: arbitrary void pointer and not used. * * @return None. * @@ -142,5 +143,5 @@ void Xil_AssertSetCallback(Xil_AssertCallback Routine) ******************************************************************************/ void XNullHandler(void *NullParameter) { - (void *) NullParameter; + (void) NullParameter; } diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xil_assert.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_assert.h similarity index 75% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xil_assert.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_assert.h index 7034bc9ad..add4124e2 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xil_assert.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_assert.h @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved. +* Copyright (C) 2009 - 2016 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -34,14 +34,22 @@ * * @file xil_assert.h * -* This file contains assert related functions. +* @addtogroup common_assert_apis Assert APIs and Macros * +* The xil_assert.h file contains assert related functions and macros. +* Assert APIs/Macros specifies that a application program satisfies certain +* conditions at particular points in its execution. These function can be +* used by application programs to ensure that, application code is satisfying +* certain conditions. +* +* @{ * 
 * MODIFICATION HISTORY:
 *
 * Ver   Who    Date   Changes
 * ----- ---- -------- -------------------------------------------------------
 * 1.00a hbm  07/14/09 First release
+* 6.0   kvn  05/31/16 Make Xil_AsserWait a global variable
 *
* ******************************************************************************/ @@ -66,6 +74,7 @@ extern "C" { #define XNULL NULL extern u32 Xil_AssertStatus; +extern s32 Xil_AssertWait; extern void Xil_Assert(const char8 *File, s32 Line); void XNullHandler(void *NullParameter); @@ -81,18 +90,17 @@ typedef void (*Xil_AssertCallback) (const char8 *File, s32 Line); /*****************************************************************************/ /** -* This assert macro is to be used for functions that do not return anything -* (void). This in conjunction with the Xil_AssertWait boolean can be used to -* accomodate tests so that asserts which fail allow execution to continue. +* @brief This assert macro is to be used for void functions. This in +* conjunction with the Xil_AssertWait boolean can be used to +* accomodate tests so that asserts which fail allow execution to +* continue. * -* @param Expression is the expression to evaluate. If it evaluates to +* @param Expression: expression to be evaluated. If it evaluates to * false, the assert occurs. * * @return Returns void unless the Xil_AssertWait variable is true, in which * case no return is made and an infinite loop is entered. * -* @note None. -* ******************************************************************************/ #define Xil_AssertVoid(Expression) \ { \ @@ -107,17 +115,16 @@ typedef void (*Xil_AssertCallback) (const char8 *File, s32 Line); /*****************************************************************************/ /** -* This assert macro is to be used for functions that do return a value. This in -* conjunction with the Xil_AssertWait boolean can be used to accomodate tests -* so that asserts which fail allow execution to continue. +* @brief This assert macro is to be used for functions that do return a +* value. This in conjunction with the Xil_AssertWait boolean can be +* used to accomodate tests so that asserts which fail allow execution +* to continue. * -* @param Expression is the expression to evaluate. If it evaluates to false, +* @param Expression: expression to be evaluated. If it evaluates to false, * the assert occurs. * * @return Returns 0 unless the Xil_AssertWait variable is true, in which -* case no return is made and an infinite loop is entered. -* -* @note None. +* case no return is made and an infinite loop is entered. * ******************************************************************************/ #define Xil_AssertNonvoid(Expression) \ @@ -133,14 +140,11 @@ typedef void (*Xil_AssertCallback) (const char8 *File, s32 Line); /*****************************************************************************/ /** -* Always assert. This assert macro is to be used for functions that do not -* return anything (void). Use for instances where an assert should always -* occur. +* @brief Always assert. This assert macro is to be used for void functions. +* Use for instances where an assert should always occur. * -* @return Returns void unless the Xil_AssertWait variable is true, in which -* case no return is made and an infinite loop is entered. -* -* @note None. +* @return Returns void unless the Xil_AssertWait variable is true, in which +* case no return is made and an infinite loop is entered. * ******************************************************************************/ #define Xil_AssertVoidAlways() \ @@ -152,13 +156,12 @@ typedef void (*Xil_AssertCallback) (const char8 *File, s32 Line); /*****************************************************************************/ /** -* Always assert. This assert macro is to be used for functions that do return -* a value. Use for instances where an assert should always occur. +* @brief Always assert. This assert macro is to be used for functions that +* do return a value. Use for instances where an assert should always +* occur. * * @return Returns void unless the Xil_AssertWait variable is true, in which -* case no return is made and an infinite loop is entered. -* -* @note None. +* case no return is made and an infinite loop is entered. * ******************************************************************************/ #define Xil_AssertNonvoidAlways() \ @@ -187,3 +190,6 @@ void Xil_AssertSetCallback(Xil_AssertCallback Routine); #endif #endif /* end of protection macro */ +/** +* @} End of "addtogroup common_assert_apis". +*/ \ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_cache.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_cache.c similarity index 74% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_cache.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_cache.c index 2ba080dff..3cd51ab6e 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_cache.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_cache.c @@ -42,6 +42,7 @@ * Ver Who Date Changes * ----- ---- -------- ----------------------------------------------- * 5.00 pkp 02/20/14 First release +* 6.2 mus 01/27/17 Updated to support IAR compiler * * ******************************************************************************/ @@ -60,16 +61,16 @@ #define IRQ_FIQ_MASK 0xC0 /* Mask IRQ and FIQ interrupts in cpsr */ - +#if defined (__GNUC__) extern s32 _stack_end; extern s32 __undef_stack; - +#endif /****************************************************************************/ /************************** Function Prototypes ******************************/ -/**************************************************************************** -* -* Enable the Data cache. +/****************************************************************************/ +/** +* @brief Enable the Data cache. * * @param None. * @@ -83,8 +84,11 @@ void Xil_DCacheEnable(void) register u32 CtrlReg; /* enable caches only if they are disabled */ +#if defined (__GNUC__) CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); - +#elif defined (__ICCARM__) + mfcp(XREG_CP15_SYS_CONTROL,CtrlReg); +#endif if ((CtrlReg & XREG_CP15_CONTROL_C_BIT)==0x00000000U) { /* invalidate the Data cache */ Xil_DCacheInvalidate(); @@ -96,9 +100,9 @@ void Xil_DCacheEnable(void) } } -/**************************************************************************** -* -* Disable the Data cache. +/****************************************************************************/ +/** +* @brief Disable the Data cache. * * @param None. * @@ -115,23 +119,25 @@ void Xil_DCacheDisable(void) Xil_DCacheFlush(); /* disable the Data cache */ +#if defined (__GNUC__) CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); +#elif defined (__ICCARM__) + mfcp(XREG_CP15_SYS_CONTROL,CtrlReg); +#endif CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT); mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); } -/**************************************************************************** -* -* Invalidate the entire Data cache. +/****************************************************************************/ +/** +* @brief Invalidate the entire Data cache. * * @param None. * * @return None. * -* @note None. -* ****************************************************************************/ void Xil_DCacheInvalidate(void) { @@ -141,14 +147,14 @@ void Xil_DCacheInvalidate(void) currmask = mfcpsr(); mtcpsr(currmask | IRQ_FIQ_MASK); - +#if defined (__GNUC__) stack_end = (u32 )&_stack_end; stack_start = (u32 )&__undef_stack; stack_size = stack_start-stack_end; /* Flush stack memory to save return address */ Xil_DCacheFlushRange(stack_end, stack_size); - +#endif mtcp(XREG_CP15_CACHE_SIZE_SEL, 0); /*invalidate all D cache*/ @@ -157,15 +163,16 @@ void Xil_DCacheInvalidate(void) mtcpsr(currmask); } -/**************************************************************************** +/****************************************************************************/ +/** +* @brief Invalidate a Data cache line. If the byte specified by the +* address (adr) is cached by the data cache, the cacheline +* containing that byte is invalidated.If the cacheline is modified +* (dirty), the modified contents are lost and are NOT written +* to system memory before the line is invalidated. * -* Invalidate a Data cache line. If the byte specified by the address (adr) -* is cached by the Data cache, the cacheline containing that byte is -* invalidated. If the cacheline is modified (dirty), the modified contents -* are lost and are NOT written to system memory before the line is -* invalidated. * -* @param Address to be flushed. +* @param adr: 32bit address of the data to be flushed. * * @return None. * @@ -188,21 +195,20 @@ void Xil_DCacheInvalidateLine(INTPTR adr) mtcpsr(currmask); } -/**************************************************************************** +/****************************************************************************/ +/** +* @brief Invalidate the Data cache for the given address range. +* If the bytes specified by the address (adr) are cached by the +* Data cache,the cacheline containing that byte is invalidated. +* If the cacheline is modified (dirty), the modified contents are +* lost and are NOT written to system memory before the line is +* invalidated. * -* Invalidate the Data cache for the given address range. -* If the bytes specified by the address (adr) are cached by the Data cache, -* the cacheline containing that byte is invalidated. If the cacheline -* is modified (dirty), the modified contents are lost and are NOT -* written to system memory before the line is invalidated. -* -* @param Start address of range to be invalidated. -* @param Length of range to be invalidated in bytes. +* @param adr: 32bit start address of the range to be invalidated. +* @param len: Length of range to be invalidated in bytes. * * @return None. * -* @note None. -* ****************************************************************************/ void Xil_DCacheInvalidateRange(INTPTR adr, u32 len) { @@ -245,16 +251,14 @@ void Xil_DCacheInvalidateRange(INTPTR adr, u32 len) mtcpsr(currmask); } -/**************************************************************************** -* -* Flush the entire Data cache. +/****************************************************************************/ +/** +* @brief Flush the entire Data cache. * * @param None. * * @return None. * -* @note None. -* ****************************************************************************/ void Xil_DCacheFlush(void) { @@ -269,8 +273,11 @@ void Xil_DCacheFlush(void) /* Select cache level 0 and D cache in CSSR */ mtcp(XREG_CP15_CACHE_SIZE_SEL, 0); +#if defined (__GNUC__) CsidReg = mfcp(XREG_CP15_CACHE_SIZE_ID); - +#elif defined (__ICCARM__) + mfcp(XREG_CP15_CACHE_SIZE_ID,CsidReg); +#endif /* Determine Cache Size */ CacheSize = (CsidReg >> 13U) & 0x000001FFU; @@ -310,15 +317,15 @@ void Xil_DCacheFlush(void) mtcpsr(currmask); } -/**************************************************************************** +/****************************************************************************/ +/** +* @brief Flush a Data cache line. If the byte specified by the address (adr) +* is cached by the Data cache, the cacheline containing that byte is +* invalidated. If the cacheline is modified (dirty), the entire +* contents of the cacheline are written to system memory before the +* line is invalidated. * -* Flush a Data cache line. If the byte specified by the address (adr) -* is cached by the Data cache, the cacheline containing that byte is -* invalidated. If the cacheline is modified (dirty), the entire -* contents of the cacheline are written to system memory before the -* line is invalidated. -* -* @param Address to be flushed. +* @param adr: 32bit address of the data to be flushed. * * @return None. * @@ -341,20 +348,19 @@ void Xil_DCacheFlushLine(INTPTR adr) mtcpsr(currmask); } -/**************************************************************************** -* Flush the Data cache for the given address range. -* If the bytes specified by the address (adr) are cached by the Data cache, -* the cacheline containing that byte is invalidated. If the cacheline -* is modified (dirty), the written to system memory first before the -* before the line is invalidated. +/****************************************************************************/ +/** +* @brief Flush the Data cache for the given address range. +* If the bytes specified by the address (adr) are cached by the +* Data cache, the cacheline containing those bytes is invalidated.If +* the cacheline is modified (dirty), the written to system memory +* before the lines are invalidated. * -* @param Start address of range to be flushed. -* @param Length of range to be flushed in bytes. +* @param adr: 32bit start address of the range to be flushed. +* @param len: Length of the range to be flushed in bytes * * @return None. * -* @note None. -* ****************************************************************************/ void Xil_DCacheFlushRange(INTPTR adr, u32 len) { @@ -383,15 +389,15 @@ void Xil_DCacheFlushRange(INTPTR adr, u32 len) dsb(); mtcpsr(currmask); } -/**************************************************************************** +/****************************************************************************/ +/** +* @brief Store a Data cache line. If the byte specified by the address +* (adr) is cached by the Data cache and the cacheline is modified +* (dirty), the entire contents of the cacheline are written to +* system memory.After the store completes, the cacheline is marked +* as unmodified (not dirty). * -* Store a Data cache line. If the byte specified by the address (adr) -* is cached by the Data cache and the cacheline is modified (dirty), -* the entire contents of the cacheline are written to system memory. -* After the store completes, the cacheline is marked as unmodified -* (not dirty). -* -* @param Address to be stored. +* @param adr: 32bit address of the data to be stored * * @return None. * @@ -415,25 +421,25 @@ void Xil_DCacheStoreLine(INTPTR adr) mtcpsr(currmask); } -/**************************************************************************** -* -* Enable the instruction cache. +/****************************************************************************/ +/** +* @brief Enable the instruction cache. * * @param None. * * @return None. * -* @note None. -* ****************************************************************************/ void Xil_ICacheEnable(void) { register u32 CtrlReg; /* enable caches only if they are disabled */ - +#if defined (__GNUC__) CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); - +#elif defined (__ICCARM__) + mfcp(XREG_CP15_SYS_CONTROL, CtrlReg); +#endif if ((CtrlReg & XREG_CP15_CONTROL_I_BIT)==0x00000000U) { /* invalidate the instruction cache */ mtcp(XREG_CP15_INVAL_IC_POU, 0); @@ -445,16 +451,14 @@ void Xil_ICacheEnable(void) } } -/**************************************************************************** -* -* Disable the instruction cache. +/****************************************************************************/ +/** +* @brief Disable the instruction cache. * * @param None. * * @return None. * -* @note None. -* ****************************************************************************/ void Xil_ICacheDisable(void) { @@ -466,24 +470,25 @@ void Xil_ICacheDisable(void) mtcp(XREG_CP15_INVAL_IC_POU, 0); /* disable the instruction cache */ - +#if defined (__GNUC__) CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); +#elif defined (__ICCARM__) + mfcp(XREG_CP15_SYS_CONTROL,CtrlReg); +#endif CtrlReg &= ~(XREG_CP15_CONTROL_I_BIT); mtcp(XREG_CP15_SYS_CONTROL, CtrlReg); } -/**************************************************************************** -* -* Invalidate the entire instruction cache. +/****************************************************************************/ +/** +* @brief Invalidate the entire instruction cache. * * @param None. * * @return None. * -* @note None. -* ****************************************************************************/ void Xil_ICacheInvalidate(void) { @@ -502,13 +507,13 @@ void Xil_ICacheInvalidate(void) mtcpsr(currmask); } -/**************************************************************************** +/****************************************************************************/ +/** +* @brief Invalidate an instruction cache line.If the instruction specified +* by the address is cached by the instruction cache, the +* cacheline containing that instruction is invalidated. * -* Invalidate an instruction cache line. If the instruction specified by the -* parameter adr is cached by the instruction cache, the cacheline containing -* that instruction is invalidated. -* -* @param None. +* @param adr: 32bit address of the instruction to be invalidated. * * @return None. * @@ -530,21 +535,20 @@ void Xil_ICacheInvalidateLine(INTPTR adr) mtcpsr(currmask); } -/**************************************************************************** +/****************************************************************************/ +/** +* @brief Invalidate the instruction cache for the given address range. +* If the bytes specified by the address (adr) are cached by the +* Data cache, the cacheline containing that byte is invalidated. +* If the cachelineis modified (dirty), the modified contents are +* lost and are NOT written to system memory before the line is +* invalidated. * -* Invalidate the instruction cache for the given address range. -* If the bytes specified by the address (adr) are cached by the Data cache, -* the cacheline containing that byte is invalidated. If the cacheline -* is modified (dirty), the modified contents are lost and are NOT -* written to system memory before the line is invalidated. -* -* @param Start address of range to be invalidated. -* @param Length of range to be invalidated in bytes. +* @param adr: 32bit start address of the range to be invalidated. +* @param len: Length of the range to be invalidated in bytes. * * @return None. * -* @note None. -* ****************************************************************************/ void Xil_ICacheInvalidateRange(INTPTR adr, u32 len) { diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_cache.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_cache.h similarity index 77% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_cache.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_cache.h index 581db3f16..ad1d10a7c 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_cache.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_cache.h @@ -34,14 +34,21 @@ * * @file xil_cache.h * -* Contains required functions for the ARM cache functionality +* @addtogroup r5_cache_apis Cortex R5 Processor Cache Functions * +* Cache functions provide access to cache related operations such as flush +* and invalidate for instruction and data caches. It gives option to perform +* the cache operations on a single cacheline, a range of memory and an entire +* cache. +* +* @{ * 
 * MODIFICATION HISTORY:
 *
 * Ver   Who  Date     Changes
 * ----- ---- -------- -----------------------------------------------
 * 5.00 	pkp  02/20/14 First release
+* 6.2   mus  01/27/17 Updated to support IAR compiler
 *
* ******************************************************************************/ @@ -54,6 +61,7 @@ extern "C" { #endif +#if defined (__GNUC__) #define asm_inval_dc_line_mva_poc(param) __asm__ __volatile__("mcr " \ XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (param)) @@ -65,6 +73,19 @@ extern "C" { #define asm_inval_ic_line_mva_pou(param) __asm__ __volatile__("mcr " \ XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (param)) +#elif defined (__ICCARM__) +#define asm_inval_dc_line_mva_poc(param) __asm volatile("mcr " \ + XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (param)) + +#define asm_clean_inval_dc_line_sw(param) __asm volatile("mcr " \ + XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (param)) + +#define asm_clean_inval_dc_line_mva_poc(param) __asm volatile("mcr " \ + XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (param)) + +#define asm_inval_ic_line_mva_pou(param) __asm volatile("mcr " \ + XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (param)) +#endif void Xil_DCacheEnable(void); void Xil_DCacheDisable(void); @@ -87,3 +108,6 @@ void Xil_ICacheInvalidateLine(INTPTR adr); #endif #endif +/** +* @} End of "addtogroup r5_cache_apis". +*/ \ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_cache_vxworks.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_cache_vxworks.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_cache_vxworks.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_cache_vxworks.h diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xil_exception.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_exception.c similarity index 63% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xil_exception.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_exception.c index 6171ea75d..4a2f2cfdf 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xil_exception.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_exception.c @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved. +* Copyright (C) 2015 - 2016 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -34,7 +34,7 @@ * * @file xil_exception.c * -* This file contains low-level driver functions for the Cortex A9 exception +* This file contains low-level driver functions for the Cortex A53,A9,R5 exception * Handler. * * 
@@ -42,18 +42,12 @@
 *
 * Ver   Who      Date     Changes
 * ----- -------- -------- -----------------------------------------------
-* 1.00a ecm/sdm  11/04/09 First release
-* 3.05a sdm		 02/02/12 Updated to resiter a null handler only if a handler
-*			  		      is not already registered
-* 4.2   pkp		 06/19/14 Added default exception handlers for data abort and
-*						  prefetch abort using handlers called
-*						  DataAbortHandler and PrefetchAbortHandler respectively
-*						  Both handlers are registers in vector table entries
-*						  using XExc_VectorTable
-* 5.1	pkp		 05/13/15 Added debugging message to print address of instruction
-*						  causing data abort and prefetch abort
-* 5.4	pkp		 12/03/15 Added handler for undefined exception to print the
-*						  address of instruction causing exception
+* 5.2	pkp  	 28/05/15 First release
+* 6.0   mus      27/07/16 Consolidated exceptions for a53,a9 and r5
+*                         processors and added Xil_UndefinedExceptionHandler
+*                         for a53 32 bit and r5 as well.
+* 6.4   mus      08/06/17 Updated debug prints to replace %x with the %lx, to
+*                         fix the warnings.
 *
* *****************************************************************************/ @@ -82,6 +76,17 @@ static void Xil_ExceptionNullHandler(void *Data); /* * Exception vector table to store handlers for each exception vector. */ +#if defined (__aarch64__) +XExc_VectorTableEntry XExc_VectorTable[XIL_EXCEPTION_ID_LAST + 1] = +{ + {Xil_ExceptionNullHandler, NULL}, + {Xil_SyncAbortHandler, NULL}, + {Xil_ExceptionNullHandler, NULL}, + {Xil_ExceptionNullHandler, NULL}, + {Xil_SErrorAbortHandler, NULL}, + +}; +#else XExc_VectorTableEntry XExc_VectorTable[XIL_EXCEPTION_ID_LAST + 1] = { {Xil_ExceptionNullHandler, NULL}, @@ -92,11 +97,13 @@ XExc_VectorTableEntry XExc_VectorTable[XIL_EXCEPTION_ID_LAST + 1] = {Xil_ExceptionNullHandler, NULL}, {Xil_ExceptionNullHandler, NULL}, }; - -u32 UndefinedExceptionAddr; /* Address of instruction causing Undefined - exception */ +#endif +#if !defined (__aarch64__) u32 DataAbortAddr; /* Address of instruction causing data abort */ u32 PrefetchAbortAddr; /* Address of instruction causing prefetch abort */ +u32 UndefinedExceptionAddr; /* Address of instruction causing Undefined + exception */ +#endif /*****************************************************************************/ @@ -117,19 +124,19 @@ u32 PrefetchAbortAddr; /* Address of instruction causing prefetch abort */ *****************************************************************************/ static void Xil_ExceptionNullHandler(void *Data) { - (void *)Data; + (void) Data; DieLoop: goto DieLoop; } /****************************************************************************/ /** -* The function is a common API used to initialize exception handlers across all -* processors supported. For ARM CortexA9, the exception handlers are being -* initialized statically and hence this function does not do anything. -* However, it is still present to avoid any compilation issues in case an -* application uses this API and also to take care of backward compatibility -* issues (in earlier versions of BSPs, this API was being used to initialize -* exception handlers). +* @brief The function is a common API used to initialize exception handlers +* across all supported arm processors. For ARM Cortex-A53, Cortex-R5, +* and Cortex-A9, the exception handlers are being initialized +* statically and this function does not do anything. +* However, it is still present to take care of backward compatibility +* issues (in earlier versions of BSPs, this API was being used to +* initialize exception handlers). * * @param None. * @@ -145,18 +152,15 @@ void Xil_ExceptionInit(void) /*****************************************************************************/ /** -* -* Makes the connection between the Id of the exception source and the -* associated Handler that is to run when the exception is recognized. The -* argument provided in this call as the Data is used as the argument -* for the Handler when it is called. +* @brief Register a handler for a specific exception. This handler is being +* called when the processor encounters the specified exception. * * @param exception_id contains the ID of the exception source and should -* be in the range of 0 to XIL_EXCEPTION_ID_LAST. - See xil_exception_l.h for further information. +* be in the range of 0 to XIL_EXCEPTION_ID_LAST. +* See xil_exception.h for further information. * @param Handler to the Handler for that exception. * @param Data is a reference to Data that will be passed to the -* Handler when it gets called. +* Handler when it gets called. * * @return None. * @@ -174,13 +178,13 @@ void Xil_ExceptionRegisterHandler(u32 Exception_id, /*****************************************************************************/ /** * -* Removes the Handler for a specific exception Id. The stub Handler is then -* registered for this exception Id. +* @brief Removes the Handler for a specific exception Id. The stub Handler +* is then registered for this exception Id. * * @param exception_id contains the ID of the exception source and should -* be in the range of 0 to XIL_EXCEPTION_ID_LAST. -* See xil_exception_l.h for further information. - +* be in the range of 0 to XIL_EXCEPTION_ID_LAST. +* See xil_exception.h for further information. +* * @return None. * * @note None. @@ -193,10 +197,53 @@ void Xil_ExceptionRemoveHandler(u32 Exception_id) NULL); } +#if defined (__aarch64__) +/*****************************************************************************/ +/** +* +* Default Synchronous abort handler which prints a debug message on console if +* Debug flag is enabled +* +* @param None +* +* @return None. +* +* @note None. +* +****************************************************************************/ + +void Xil_SyncAbortHandler(void *CallBackRef){ + (void) CallBackRef; + xdbg_printf(XDBG_DEBUG_ERROR, "Synchronous abort \n"); + while(1) { + ; + } +} /*****************************************************************************/ /** * +* Default SError abort handler which prints a debug message on console if +* Debug flag is enabled +* +* @param None +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void Xil_SErrorAbortHandler(void *CallBackRef){ + (void) CallBackRef; + xdbg_printf(XDBG_DEBUG_ERROR, "Synchronous abort \n"); + while(1) { + ; + } +} +#else +/*****************************************************************************/ +/* +* * Default Data abort handler which prints data fault status register through * which information about data fault can be acquired * @@ -209,24 +256,29 @@ void Xil_ExceptionRemoveHandler(u32 Exception_id) ****************************************************************************/ void Xil_DataAbortHandler(void *CallBackRef){ + (void) CallBackRef; +#ifdef DEBUG u32 FaultStatus; - #ifdef __GNUC__ - FaultStatus = mfcp(XREG_CP15_DATA_FAULT_STATUS); - #elif defined (__ICCARM__) - mfcp(XREG_CP15_DATA_FAULT_STATUS,FaultStatus); - #else - { volatile register u32 Reg __asm(XREG_CP15_DATA_FAULT_STATUS); - FaultStatus = Reg; } - #endif - xdbg_printf(XDBG_DEBUG_GENERAL, "Data abort with Data Fault Status Register %x\n",FaultStatus); - xdbg_printf(XDBG_DEBUG_GENERAL, "Address of Instrcution causing Data abort %x\n",DataAbortAddr); + + xdbg_printf(XDBG_DEBUG_ERROR, "Data abort \n"); + #ifdef __GNUC__ + FaultStatus = mfcp(XREG_CP15_DATA_FAULT_STATUS); + #elif defined (__ICCARM__) + mfcp(XREG_CP15_DATA_FAULT_STATUS,FaultStatus); + #else + { volatile register u32 Reg __asm(XREG_CP15_DATA_FAULT_STATUS); + FaultStatus = Reg; } + #endif + xdbg_printf(XDBG_DEBUG_GENERAL, "Data abort with Data Fault Status Register %lx\n",FaultStatus); + xdbg_printf(XDBG_DEBUG_GENERAL, "Address of Instruction causing Data abort %lx\n",DataAbortAddr); +#endif while(1) { ; } } /*****************************************************************************/ -/** +/* * * Default Prefetch abort handler which prints prefetch fault status register through * which information about instruction prefetch fault can be acquired @@ -239,24 +291,28 @@ void Xil_DataAbortHandler(void *CallBackRef){ * ****************************************************************************/ void Xil_PrefetchAbortHandler(void *CallBackRef){ + (void) CallBackRef; +#ifdef DEBUG u32 FaultStatus; - #ifdef __GNUC__ - FaultStatus = mfcp(XREG_CP15_INST_FAULT_STATUS); - #elif defined (__ICCARM__) - mfcp(XREG_CP15_INST_FAULT_STATUS,FaultStatus); - #else - { volatile register u32 Reg __asm(XREG_CP15_INST_FAULT_STATUS); - FaultStatus = Reg; } - #endif - xdbg_printf(XDBG_DEBUG_GENERAL, "Prefetch abort with Instruction Fault Status Register %x\n",FaultStatus); - xdbg_printf(XDBG_DEBUG_GENERAL, "Address of Instrcution causing Prefetch abort %x\n",PrefetchAbortAddr); + + xdbg_printf(XDBG_DEBUG_ERROR, "Prefetch abort \n"); + #ifdef __GNUC__ + FaultStatus = mfcp(XREG_CP15_INST_FAULT_STATUS); + #elif defined (__ICCARM__) + mfcp(XREG_CP15_INST_FAULT_STATUS,FaultStatus); + #else + { volatile register u32 Reg __asm(XREG_CP15_INST_FAULT_STATUS); + FaultStatus = Reg; } + #endif + xdbg_printf(XDBG_DEBUG_GENERAL, "Prefetch abort with Instruction Fault Status Register %lx\n",FaultStatus); + xdbg_printf(XDBG_DEBUG_GENERAL, "Address of Instruction causing Prefetch abort %lx\n",PrefetchAbortAddr); +#endif while(1) { ; } } - /*****************************************************************************/ -/** +/* * * Default undefined exception handler which prints address of the undefined * instruction if debug prints are enabled @@ -269,9 +325,10 @@ void Xil_PrefetchAbortHandler(void *CallBackRef){ * ****************************************************************************/ void Xil_UndefinedExceptionHandler(void *CallBackRef){ - - xdbg_printf(XDBG_DEBUG_GENERAL, "Address of the undefined instruction %x\n",UndefinedExceptionAddr); + (void) CallBackRef; + xdbg_printf(XDBG_DEBUG_GENERAL, "Address of the undefined instruction %lx\n",UndefinedExceptionAddr); while(1) { ; } -} \ No newline at end of file +} +#endif diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xil_exception.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_exception.h similarity index 80% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xil_exception.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_exception.h index db8641a25..ad4822205 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xil_exception.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_exception.h @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved. +* Copyright (C) 2015 - 2016 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -34,16 +34,23 @@ * * @file xil_exception.h * -* This header file contains ARM Cortex A9 specific exception related APIs. +* This header file contains ARM Cortex A53,A9,R5 specific exception related APIs. * For exception related functions that can be used across all Xilinx supported * processors, please use xil_exception.h. * +* @addtogroup arm_exception_apis ARM Processor Exception Handling +* @{ +* ARM processors specific exception related APIs for cortex A53,A9 and R5 can +* utilized for enabling/disabling IRQ, registering/removing handler for +* exceptions or initializing exception vector table with null handler. +* * 
 * MODIFICATION HISTORY:
 *
 * Ver   Who      Date     Changes
 * ----- -------- -------- -----------------------------------------------
-* 1.00a ecm/sdm  11/04/09 First release
+* 5.2	pkp  	 28/05/15 First release
+* 6.0   mus      27/07/16 Consolidated file for a53,a9 and r5 processors
 *
* ******************************************************************************/ @@ -67,6 +74,13 @@ extern "C" { #define XIL_EXCEPTION_ALL (XREG_CPSR_FIQ_ENABLE | XREG_CPSR_IRQ_ENABLE) #define XIL_EXCEPTION_ID_FIRST 0U +#if defined (__aarch64__) +#define XIL_EXCEPTION_ID_SYNC_INT 1U +#define XIL_EXCEPTION_ID_IRQ_INT 2U +#define XIL_EXCEPTION_ID_FIQ_INT 3U +#define XIL_EXCEPTION_ID_SERROR_ABORT_INT 4U +#define XIL_EXCEPTION_ID_LAST 5U +#else #define XIL_EXCEPTION_ID_RESET 0U #define XIL_EXCEPTION_ID_UNDEFINED_INT 1U #define XIL_EXCEPTION_ID_SWI_INT 2U @@ -75,6 +89,7 @@ extern "C" { #define XIL_EXCEPTION_ID_IRQ_INT 5U #define XIL_EXCEPTION_ID_FIQ_INT 6U #define XIL_EXCEPTION_ID_LAST 6U +#endif /* * XIL_EXCEPTION_ID_INT is defined for all Xilinx processors. @@ -93,20 +108,17 @@ typedef void (*Xil_InterruptHandler)(void *data); /****************************************************************************/ /** -* Enable Exceptions. +* @brief Enable Exceptions. * -* @param Mask for exceptions to be enabled. +* @param Mask: Value for enabling the exceptions. * * @return None. * * @note If bit is 0, exception is enabled. -* C-Style signature: void Xil_ExceptionEnableMask(Mask) +* C-Style signature: void Xil_ExceptionEnableMask(Mask) * ******************************************************************************/ -#ifdef __GNUC__ -#define Xil_ExceptionEnableMask(Mask) \ - mtcpsr(mfcpsr() & ~ ((Mask) & XIL_EXCEPTION_ALL)) -#elif defined (__ICCARM__) +#if defined (__GNUC__) || defined (__ICCARM__) #define Xil_ExceptionEnableMask(Mask) \ mtcpsr(mfcpsr() & ~ ((Mask) & XIL_EXCEPTION_ALL)) #else @@ -116,10 +128,9 @@ typedef void (*Xil_InterruptHandler)(void *data); mtcpsr((Reg) & (~((Mask) & XIL_EXCEPTION_ALL))); \ } #endif - /****************************************************************************/ /** -* Enable the IRQ exception. +* @brief Enable the IRQ exception. * * @return None. * @@ -127,26 +138,23 @@ typedef void (*Xil_InterruptHandler)(void *data); * ******************************************************************************/ #define Xil_ExceptionEnable() \ - Xil_ExceptionEnableMask((u32)XIL_EXCEPTION_IRQ) + Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ) /****************************************************************************/ /** -* Disable Exceptions. +* @brief Disable Exceptions. * -* @param Mask for exceptions to be enabled. +* @param Mask: Value for disabling the exceptions. * * @return None. * * @note If bit is 1, exception is disabled. -* C-Style signature: Xil_ExceptionDisableMask(Mask) +* C-Style signature: Xil_ExceptionDisableMask(Mask) * ******************************************************************************/ -#ifdef __GNUC__ +#if defined (__GNUC__) || defined (__ICCARM__) #define Xil_ExceptionDisableMask(Mask) \ mtcpsr(mfcpsr() | ((Mask) & XIL_EXCEPTION_ALL)) -#elif defined (__ICCARM__) -#define Xil_ExceptionDisableMask(Mask) \ - mtcpsr(mfcpsr() | (Mask & XIL_EXCEPTION_ALL)) #else #define Xil_ExceptionDisableMask(Mask) \ { \ @@ -154,7 +162,6 @@ typedef void (*Xil_InterruptHandler)(void *data); mtcpsr((Reg) | ((Mask) & XIL_EXCEPTION_ALL)); \ } #endif - /****************************************************************************/ /** * Disable the IRQ exception. @@ -167,9 +174,11 @@ typedef void (*Xil_InterruptHandler)(void *data); #define Xil_ExceptionDisable() \ Xil_ExceptionDisableMask(XIL_EXCEPTION_IRQ) +#if !defined (__aarch64__) && !defined (ARMA53_32) /****************************************************************************/ /** -* Enable nested interrupts by clearing the I and F bits it CPSR +* @brief Enable nested interrupts by clearing the I and F bits in CPSR. This +* API is defined for cortex-a9 and cortex-r5. * * @return None. * @@ -187,6 +196,7 @@ typedef void (*Xil_InterruptHandler)(void *data); * eventual crash (all the stack space getting consumed). ******************************************************************************/ #define Xil_EnableNestedInterrupts() \ + __asm__ __volatile__ ("stmfd sp!, {lr}"); \ __asm__ __volatile__ ("mrs lr, spsr"); \ __asm__ __volatile__ ("stmfd sp!, {lr}"); \ __asm__ __volatile__ ("msr cpsr_c, #0x1F"); \ @@ -194,7 +204,8 @@ typedef void (*Xil_InterruptHandler)(void *data); /****************************************************************************/ /** -* Disable the nested interrupts by setting the I and F bits. +* @brief Disable the nested interrupts by setting the I and F bits. This API +* is defined for cortex-a9 and cortex-r5. * * @return None. * @@ -211,8 +222,10 @@ typedef void (*Xil_InterruptHandler)(void *data); __asm__ __volatile__ ("ldmfd sp!, {lr}"); \ __asm__ __volatile__ ("msr cpsr_c, #0x92"); \ __asm__ __volatile__ ("ldmfd sp!, {lr}"); \ - __asm__ __volatile__ ("msr spsr_cxsf, lr"); + __asm__ __volatile__ ("msr spsr_cxsf, lr"); \ + __asm__ __volatile__ ("ldmfd sp!, {lr}"); \ +#endif /************************** Variable Definitions ****************************/ /************************** Function Prototypes *****************************/ @@ -224,12 +237,20 @@ extern void Xil_ExceptionRegisterHandler(u32 Exception_id, extern void Xil_ExceptionRemoveHandler(u32 Exception_id); extern void Xil_ExceptionInit(void); +#if defined (__aarch64__) +void Xil_SyncAbortHandler(void *CallBackRef); +void Xil_SErrorAbortHandler(void *CallBackRef); +#else extern void Xil_DataAbortHandler(void *CallBackRef); extern void Xil_PrefetchAbortHandler(void *CallBackRef); extern void Xil_UndefinedExceptionHandler(void *CallBackRef); +#endif #ifdef __cplusplus } #endif /* __cplusplus */ #endif /* XIL_EXCEPTION_H */ +/** +* @} End of "addtogroup arm_exception_apis". +*/ \ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_hal.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_hal.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_hal.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_hal.h diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_io.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_io.c new file mode 100644 index 000000000..90bfc81dc --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_io.c @@ -0,0 +1,102 @@ +/****************************************************************************** +* +* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_io.c +* +* Contains I/O functions for memory-mapped or non-memory-mapped I/O +* architectures. +* +* @note +* +* This file contains architecture-dependent code. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 	pkp  	 05/29/14 First release
+*
+******************************************************************************/ + + +/***************************** Include Files *********************************/ +#include "xil_io.h" +#include "xil_types.h" +#include "xil_assert.h" + +/*****************************************************************************/ +/** +* +* @brief Perform a 16-bit endian converion. +* +* @param Data: 16 bit value to be converted +* +* @return 16 bit Data with converted endianess +* +******************************************************************************/ +u16 Xil_EndianSwap16(u16 Data) +{ + return (u16) (((Data & 0xFF00U) >> 8U) | ((Data & 0x00FFU) << 8U)); +} + +/*****************************************************************************/ +/** +* +* @brief Perform a 32-bit endian converion. +* +* @param Data: 32 bit value to be converted +* +* @return 32 bit data with converted endianess +* +******************************************************************************/ +u32 Xil_EndianSwap32(u32 Data) +{ + u16 LoWord; + u16 HiWord; + + /* get each of the half words from the 32 bit word */ + + LoWord = (u16) (Data & 0x0000FFFFU); + HiWord = (u16) ((Data & 0xFFFF0000U) >> 16U); + + /* byte swap each of the 16 bit half words */ + + LoWord = (((LoWord & 0xFF00U) >> 8U) | ((LoWord & 0x00FFU) << 8U)); + HiWord = (((HiWord & 0xFF00U) >> 8U) | ((HiWord & 0x00FFU) << 8U)); + + /* swap the half words before returning the value */ + + return ((((u32)LoWord) << (u32)16U) | (u32)HiWord); +} diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_io.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_io.h new file mode 100644 index 000000000..9c5aa43c7 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_io.h @@ -0,0 +1,345 @@ +/****************************************************************************** +* +* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_io.h +* +* @addtogroup common_io_interfacing_apis Register IO interfacing APIs +* +* The xil_io.h file contains the interface for the general I/O component, which +* encapsulates the Input/Output functions for the processors that do not +* require any special I/O handling. +* +* @{ +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 	pkp  	 05/29/14 First release
+* 6.00  mus      08/19/16 Remove checking of __LITTLE_ENDIAN__ flag for
+*                         ARM processors
+*
+******************************************************************************/ + +#ifndef XIL_IO_H /* prevent circular inclusions */ +#define XIL_IO_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_printf.h" + +#if defined (__MICROBLAZE__) +#include "mb_interface.h" +#else +#include "xpseudo_asm.h" +#endif + +/************************** Function Prototypes ******************************/ +u16 Xil_EndianSwap16(u16 Data); +u32 Xil_EndianSwap32(u32 Data); +#ifdef ENABLE_SAFETY +extern u32 XStl_RegUpdate(u32 RegAddr, u32 RegVal); +#endif + +/***************** Macros (Inline Functions) Definitions *********************/ +#if defined __GNUC__ +#if defined (__MICROBLAZE__) +# define INST_SYNC mbar(0) +# define DATA_SYNC mbar(1) +# else +# define SYNCHRONIZE_IO dmb() +# define INST_SYNC isb() +# define DATA_SYNC dsb() +# endif +#else +# define SYNCHRONIZE_IO +# define INST_SYNC +# define DATA_SYNC +# define INST_SYNC +# define DATA_SYNC +#endif + +#if defined (__GNUC__) || defined (__ICCARM__) || defined (__MICROBLAZE__) +#define INLINE inline +#else +#define INLINE __inline +#endif + +/*****************************************************************************/ +/** +* +* @brief Performs an input operation for a memory location by reading +* from the specified address and returning the 8 bit Value read from +* that address. +* +* @param Addr: contains the address to perform the input operation +* +* @return The 8 bit Value read from the specified input address. + +* +******************************************************************************/ +static INLINE u8 Xil_In8(UINTPTR Addr) +{ + return *(volatile u8 *) Addr; +} + +/*****************************************************************************/ +/** +* +* @brief Performs an input operation for a memory location by reading from +* the specified address and returning the 16 bit Value read from that +* address. +* +* @param Addr: contains the address to perform the input operation +* +* @return The 16 bit Value read from the specified input address. +* +******************************************************************************/ +static INLINE u16 Xil_In16(UINTPTR Addr) +{ + return *(volatile u16 *) Addr; +} + +/*****************************************************************************/ +/** +* +* @brief Performs an input operation for a memory location by +* reading from the specified address and returning the 32 bit Value +* read from that address. +* +* @param Addr: contains the address to perform the input operation +* +* @return The 32 bit Value read from the specified input address. +* +******************************************************************************/ +static INLINE u32 Xil_In32(UINTPTR Addr) +{ + return *(volatile u32 *) Addr; +} + +/*****************************************************************************/ +/** +* +* @brief Performs an input operation for a memory location by reading the +* 64 bit Value read from that address. +* +* +* @param Addr: contains the address to perform the input operation +* +* @return The 64 bit Value read from the specified input address. +* +******************************************************************************/ +static INLINE u64 Xil_In64(UINTPTR Addr) +{ + return *(volatile u64 *) Addr; +} + +/*****************************************************************************/ +/** +* +* @brief Performs an output operation for an memory location by +* writing the 8 bit Value to the the specified address. +* +* @param Addr: contains the address to perform the output operation +* @param Value: contains the 8 bit Value to be written at the specified +* address. +* +* @return None. +* +******************************************************************************/ +static INLINE void Xil_Out8(UINTPTR Addr, u8 Value) +{ + volatile u8 *LocalAddr = (volatile u8 *)Addr; + *LocalAddr = Value; +} + +/*****************************************************************************/ +/** +* +* @brief Performs an output operation for a memory location by writing the +* 16 bit Value to the the specified address. +* +* @param Addr contains the address to perform the output operation +* @param Value contains the Value to be written at the specified address. +* +* @return None. +* +******************************************************************************/ +static INLINE void Xil_Out16(UINTPTR Addr, u16 Value) +{ + volatile u16 *LocalAddr = (volatile u16 *)Addr; + *LocalAddr = Value; +} + +/*****************************************************************************/ +/** +* +* @brief Performs an output operation for a memory location by writing the +* 32 bit Value to the the specified address. +* +* @param Addr contains the address to perform the output operation +* @param Value contains the 32 bit Value to be written at the specified +* address. +* +* @return None. +* +******************************************************************************/ +static INLINE void Xil_Out32(UINTPTR Addr, u32 Value) +{ +#ifndef ENABLE_SAFETY + volatile u32 *LocalAddr = (volatile u32 *)Addr; + *LocalAddr = Value; +#else + XStl_RegUpdate(Addr, Value); +#endif +} + +/*****************************************************************************/ +/** +* +* @brief Performs an output operation for a memory location by writing the +* 64 bit Value to the the specified address. +* +* @param Addr contains the address to perform the output operation +* @param Value contains 64 bit Value to be written at the specified address. +* +* @return None. +* +******************************************************************************/ +static INLINE void Xil_Out64(UINTPTR Addr, u64 Value) +{ + volatile u64 *LocalAddr = (volatile u64 *)Addr; + *LocalAddr = Value; +} + +#if defined (__MICROBLAZE__) +#ifdef __LITTLE_ENDIAN__ +# define Xil_In16LE Xil_In16 +# define Xil_In32LE Xil_In32 +# define Xil_Out16LE Xil_Out16 +# define Xil_Out32LE Xil_Out32 +# define Xil_Htons Xil_EndianSwap16 +# define Xil_Htonl Xil_EndianSwap32 +# define Xil_Ntohs Xil_EndianSwap16 +# define Xil_Ntohl Xil_EndianSwap32 +# else +# define Xil_In16BE Xil_In16 +# define Xil_In32BE Xil_In32 +# define Xil_Out16BE Xil_Out16 +# define Xil_Out32BE Xil_Out32 +# define Xil_Htons(Data) (Data) +# define Xil_Htonl(Data) (Data) +# define Xil_Ntohs(Data) (Data) +# define Xil_Ntohl(Data) (Data) +#endif +#else +# define Xil_In16LE Xil_In16 +# define Xil_In32LE Xil_In32 +# define Xil_Out16LE Xil_Out16 +# define Xil_Out32LE Xil_Out32 +# define Xil_Htons Xil_EndianSwap16 +# define Xil_Htonl Xil_EndianSwap32 +# define Xil_Ntohs Xil_EndianSwap16 +# define Xil_Ntohl Xil_EndianSwap32 +#endif + +#if defined (__MICROBLAZE__) +#ifdef __LITTLE_ENDIAN__ +static INLINE u16 Xil_In16BE(UINTPTR Addr) +#else +static INLINE u16 Xil_In16LE(UINTPTR Addr) +#endif +#else +static INLINE u16 Xil_In16BE(UINTPTR Addr) +#endif +{ + u16 value = Xil_In16(Addr); + return Xil_EndianSwap16(value); +} + +#if defined (__MICROBLAZE__) +#ifdef __LITTLE_ENDIAN__ +static INLINE u32 Xil_In32BE(UINTPTR Addr) +#else +static INLINE u32 Xil_In32LE(UINTPTR Addr) +#endif +#else +static INLINE u32 Xil_In32BE(UINTPTR Addr) +#endif +{ + u32 value = Xil_In32(Addr); + return Xil_EndianSwap32(value); +} + +#if defined (__MICROBLAZE__) +#ifdef __LITTLE_ENDIAN__ +static INLINE void Xil_Out16BE(UINTPTR Addr, u16 Value) +#else +static INLINE void Xil_Out16LE(UINTPTR Addr, u16 Value) +#endif +#else +static INLINE void Xil_Out16BE(UINTPTR Addr, u16 Value) +#endif +{ + Value = Xil_EndianSwap16(Value); + Xil_Out16(Addr, Value); +} + +#if defined (__MICROBLAZE__) +#ifdef __LITTLE_ENDIAN__ +static INLINE void Xil_Out32BE(UINTPTR Addr, u32 Value) +#else +static INLINE void Xil_Out32LE(UINTPTR Addr, u32 Value) +#endif +#else +static INLINE void Xil_Out32BE(UINTPTR Addr, u32 Value) +#endif +{ + Value = Xil_EndianSwap32(Value); + Xil_Out32(Addr, Value); +} + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** +* @} End of "addtogroup common_io_interfacing_apis". +*/ diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_macroback.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_macroback.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_macroback.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_macroback.h diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_mem.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_mem.c new file mode 100644 index 000000000..0929a6878 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_mem.c @@ -0,0 +1,83 @@ +/******************************************************************************/ +/** +* Copyright (C) 2015 - 2016 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* @file xil_mem.c +* +* This file contains xil mem copy function to use in case of word aligned +* data copies. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 6.1   nsk      11/07/16 First release.
+*
+*
+* +*****************************************************************************/ + +/***************************** Include Files ********************************/ + +#include "xil_types.h" + +/***************** Inline Functions Definitions ********************/ +/*****************************************************************************/ +/** +* @brief This function copies memory from once location to other. +* +* @param dst: pointer pointing to destination memory +* +* @param src: pointer pointing to source memory +* +* @param cnt: 32 bit length of bytes to be copied +* +*****************************************************************************/ +void Xil_MemCpy(void* dst, const void* src, u32 cnt) +{ + char *d = (char*)(void *)dst; + const char *s = src; + + while (cnt >= sizeof (int)) { + *(int*)d = *(int*)s; + d += sizeof (int); + s += sizeof (int); + cnt -= sizeof (int); + } + while ((cnt) > 0U){ + *d = *s; + d += 1U; + s += 1U; + cnt -= 1U; + } +} diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_mem.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_mem.h new file mode 100644 index 000000000..a2d5e6681 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_mem.h @@ -0,0 +1,59 @@ +/******************************************************************************/ +/** +* Copyright (C) 2015 - 2016 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* @file xil_mem.h +* +* @addtogroup common_mem_operation_api Customized APIs for Memory Operations +* +* The xil_mem.h file contains prototype for functions related +* to memory operations. These APIs are applicable for all processors supported +* by Xilinx. +* +* @{ +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 6.1   nsk      11/07/16 First release.
+*
+*
+* +*****************************************************************************/ + +/************************** Function Prototypes *****************************/ + +void Xil_MemCpy(void* dst, const void* src, u32 cnt); +/** +* @} End of "addtogroup common_mem_operation_api". +*/ \ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_mmu.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_mmu.h similarity index 97% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_mmu.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_mmu.h index 8e43e8227..28a7c781d 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_mmu.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_mmu.h @@ -18,8 +18,8 @@ * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_mpu.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_mpu.c new file mode 100644 index 000000000..7dd048fa6 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_mpu.c @@ -0,0 +1,579 @@ +/****************************************************************************** +* +* Copyright (C) 2014 - 2017 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file xil_mpu.c +* +* This file provides APIs for enabling/disabling MPU and setting the memory +* attributes for sections, in the MPU translation table. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 5.00  pkp  02/10/14 Initial version
+* 6.2   mus  01/27/17 Updated to support IAR compiler
+* 6.4   asa  08/16/17 Added many APIs for MPU access to make MPU usage
+* 					  user-friendly. The APIs added are: Xil_UpdateMPUConfig,
+* 					  Xil_GetMPUConfig, Xil_GetNumOfFreeRegions,
+* 					  Xil_GetNextMPURegion, Xil_DisableMPURegionByRegNum,
+* 					  Xil_GetMPUFreeRegMask, Xil_SetMPURegionByRegNum, and
+* 					  Xil_InitializeExistingMPURegConfig.
+* 					  Added a new array of structure of type XMpuConfig to
+* 					  represent the MPU configuration table.
+*
+* +* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xil_cache.h" +#include "xpseudo_asm.h" +#include "xil_types.h" +#include "xil_mpu.h" +#include "xdebug.h" +#include "xstatus.h" +/***************** Macros (Inline Functions) Definitions *********************/ + +/**************************** Type Definitions *******************************/ + +/************************** Constant Definitions *****************************/ + +/************************** Variable Definitions *****************************/ + +static const struct { + u64 size; + unsigned int encoding; +}region_size[] = { + { 0x20, REGION_32B }, + { 0x40, REGION_64B }, + { 0x80, REGION_128B }, + { 0x100, REGION_256B }, + { 0x200, REGION_512B }, + { 0x400, REGION_1K }, + { 0x800, REGION_2K }, + { 0x1000, REGION_4K }, + { 0x2000, REGION_8K }, + { 0x4000, REGION_16K }, + { 0x8000, REGION_32K }, + { 0x10000, REGION_64K }, + { 0x20000, REGION_128K }, + { 0x40000, REGION_256K }, + { 0x80000, REGION_512K }, + { 0x100000, REGION_1M }, + { 0x200000, REGION_2M }, + { 0x400000, REGION_4M }, + { 0x800000, REGION_8M }, + { 0x1000000, REGION_16M }, + { 0x2000000, REGION_32M }, + { 0x4000000, REGION_64M }, + { 0x8000000, REGION_128M }, + { 0x10000000, REGION_256M }, + { 0x20000000, REGION_512M }, + { 0x40000000, REGION_1G }, + { 0x80000000, REGION_2G }, + { 0x100000000, REGION_4G }, +}; + +XMpu_Config Mpu_Config; + +/************************** Function Prototypes ******************************/ +void Xil_InitializeExistingMPURegConfig(void); +/*****************************************************************************/ +/** +* @brief This function sets the memory attributes for a section covering +* 1MB, of memory in the translation table. +* +* @param Addr: 32-bit address for which memory attributes need to be set. +* @param attrib: Attribute for the given memory region. +* @return None. +* +* +******************************************************************************/ +void Xil_SetTlbAttributes(INTPTR addr, u32 attrib) +{ + INTPTR Localaddr = addr; + Localaddr &= (~(0xFFFFFU)); + /* Setting the MPU region with given attribute with 1MB size */ + Xil_SetMPURegion(Localaddr, 0x100000, attrib); +} + +/*****************************************************************************/ +/** +* @brief Set the memory attributes for a section of memory in the +* translation table. +* +* @param Addr: 32-bit address for which memory attributes need to be set.. +* @param size: size is the size of the region. +* @param attrib: Attribute for the given memory region. +* @return None. +* +* +******************************************************************************/ +u32 Xil_SetMPURegion(INTPTR addr, u64 size, u32 attrib) +{ + u32 Regionsize = 0; + INTPTR Localaddr = addr; + u32 NextAvailableMemRegion; + unsigned int i; + + NextAvailableMemRegion = Xil_GetNextMPURegion(); + if (NextAvailableMemRegion == 0xFF) { + xdbg_printf(DEBUG, "No regions available\r\n"); + return XST_FAILURE; + } + + Xil_DCacheFlush(); + Xil_ICacheInvalidate(); + + mtcp(XREG_CP15_MPU_MEMORY_REG_NUMBER,NextAvailableMemRegion); + isb(); + + /* Lookup the size. */ + for (i = 0; i < sizeof region_size / sizeof region_size[0]; i++) { + if (size <= region_size[i].size) { + Regionsize = region_size[i].encoding; + break; + } + } + + Localaddr &= ~(region_size[i].size - 1); + + Regionsize <<= 1; + Regionsize |= REGION_EN; + dsb(); + mtcp(XREG_CP15_MPU_REG_BASEADDR, Localaddr); /* Set base address of a region */ + mtcp(XREG_CP15_MPU_REG_ACCESS_CTRL, attrib); /* Set the control attribute */ + mtcp(XREG_CP15_MPU_REG_SIZE_EN, Regionsize); /* set the region size and enable it*/ + dsb(); + isb(); + Xil_UpdateMPUConfig(NextAvailableMemRegion, Localaddr, Regionsize, attrib); + return XST_SUCCESS; +} +/*****************************************************************************/ +/** +* @brief Enable MPU for Cortex R5 processor. This function invalidates I +* cache and flush the D Caches, and then enables the MPU. +* +* +* @param None. +* @return None. +* +******************************************************************************/ +void Xil_EnableMPU(void) +{ + u32 CtrlReg, Reg; + s32 DCacheStatus=0, ICacheStatus=0; + /* enable caches only if they are disabled */ +#if defined (__GNUC__) + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); +#elif defined (__ICCARM__) + mfcp(XREG_CP15_SYS_CONTROL,CtrlReg); +#endif + if ((CtrlReg & XREG_CP15_CONTROL_C_BIT) != 0x00000000U) { + DCacheStatus=1; + } + if ((CtrlReg & XREG_CP15_CONTROL_I_BIT) != 0x00000000U) { + ICacheStatus=1; + } + + if(DCacheStatus != 0) { + Xil_DCacheDisable(); + } + if(ICacheStatus != 0){ + Xil_ICacheDisable(); + } +#if defined (__GNUC__) + Reg = mfcp(XREG_CP15_SYS_CONTROL); +#elif defined (__ICCARM__) + mfcp(XREG_CP15_SYS_CONTROL,Reg); +#endif + Reg |= 0x00000001U; + dsb(); + mtcp(XREG_CP15_SYS_CONTROL, Reg); + isb(); + /* enable caches only if they are disabled in routine*/ + if(DCacheStatus != 0) { + Xil_DCacheEnable(); + } + if(ICacheStatus != 0) { + Xil_ICacheEnable(); + } +} + +/*****************************************************************************/ +/** +* @brief Disable MPU for Cortex R5 processors. This function invalidates I +* cache and flush the D Caches, and then disabes the MPU. +* +* @param None. +* +* @return None. +* +******************************************************************************/ +void Xil_DisableMPU(void) +{ + u32 CtrlReg, Reg; + s32 DCacheStatus=0, ICacheStatus=0; + /* enable caches only if they are disabled */ + +#if defined (__GNUC__) + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); +#elif defined (__ICCARM__) + mfcp(XREG_CP15_SYS_CONTROL,CtrlReg); +#endif + if ((CtrlReg & XREG_CP15_CONTROL_C_BIT) != 0x00000000U) { + DCacheStatus=1; + } + if ((CtrlReg & XREG_CP15_CONTROL_I_BIT) != 0x00000000U) { + ICacheStatus=1; + } + + if(DCacheStatus != 0) { + Xil_DCacheDisable(); + } + if(ICacheStatus != 0){ + Xil_ICacheDisable(); + } + + mtcp(XREG_CP15_INVAL_BRANCH_ARRAY, 0); +#if defined (__GNUC__) + Reg = mfcp(XREG_CP15_SYS_CONTROL); +#elif defined (__ICCARM__) + mfcp(XREG_CP15_SYS_CONTROL,Reg); +#endif + Reg &= ~(0x00000001U); + dsb(); + mtcp(XREG_CP15_SYS_CONTROL, Reg); + isb(); + /* enable caches only if they are disabled in routine*/ + if(DCacheStatus != 0) { + Xil_DCacheEnable(); + } + if(ICacheStatus != 0) { + Xil_ICacheEnable(); + } +} + +/*****************************************************************************/ +/** +* @brief Update the MPU configuration for the requested region number in +* the global MPU configuration table. +* +* @param reg_num: The requested region number to be updated information for. +* @param address: 32 bit address for start of the region. +* @param size: Requested size of the region. +* @param attrib: Attribute for the corresponding region. +* @return XST_FAILURE: When the requested region number if 16 or more. +* XST_SUCCESS: When the MPU configuration table is updated. +* +* +******************************************************************************/ +u32 Xil_UpdateMPUConfig(u32 reg_num, INTPTR address, u32 size, u32 attrib) +{ + u32 ReturnVal = XST_SUCCESS; + u32 Tempsize = size; + u32 Index; + + if (reg_num >= MAX_POSSIBLE_MPU_REGS) { + xdbg_printf(DEBUG, "Invalid region number\r\n"); + ReturnVal = XST_FAILURE; + goto exit; + } + + if (size & REGION_EN) { + Mpu_Config[reg_num].RegionStatus = MPU_REG_ENABLED; + Mpu_Config[reg_num].BaseAddress = address; + Tempsize &= (~REGION_EN); + Tempsize >>= 1; + /* Lookup the size. */ + for (Index = 0; Index < + sizeof region_size / sizeof region_size[0]; Index++) { + if (Tempsize <= region_size[Index].encoding) { + Mpu_Config[reg_num].Size = region_size[Index].size; + break; + } + } + Mpu_Config[reg_num].Attribute = attrib; + } else { + Mpu_Config[reg_num].RegionStatus = 0U; + Mpu_Config[reg_num].BaseAddress = 0U; + Mpu_Config[reg_num].Size = 0U; + Mpu_Config[reg_num].Attribute = 0U; + } + +exit: + return ReturnVal; +} + +/*****************************************************************************/ +/** +* @brief The MPU configuration table is passed to the caller. +* +* @param mpuconfig: This is of type XMpu_Config which is an array of +* 16 entries of type structure representing the MPU config table +* @return none +* +* +******************************************************************************/ +void Xil_GetMPUConfig (XMpu_Config mpuconfig) { + u32 Index = 0U; + + while (Index < MAX_POSSIBLE_MPU_REGS) { + mpuconfig[Index].RegionStatus = Mpu_Config[Index].RegionStatus; + mpuconfig[Index].BaseAddress = Mpu_Config[Index].BaseAddress; + mpuconfig[Index].Attribute = Mpu_Config[Index].Attribute; + mpuconfig[Index].Size = Mpu_Config[Index].Size; + Index++; + } +} + +/*****************************************************************************/ +/** +* @brief Returns the total number of free MPU regions available. +* +* @param none +* @return Number of free regions available to users +* +* +******************************************************************************/ +u32 Xil_GetNumOfFreeRegions (void) { + u32 Index = 0U; + int NumofFreeRegs = 0U; + + while (Index < MAX_POSSIBLE_MPU_REGS) { + if (MPU_REG_DISABLED == Mpu_Config[Index].RegionStatus) { + NumofFreeRegs++; + } + Index++; + } + return NumofFreeRegs; +} + +/*****************************************************************************/ +/** +* @brief Returns the total number of free MPU regions available in the form +* of a mask. A bit of 1 in the returned 16 bit value represents the +* corresponding region number to be available. +* For example, if this function returns 0xC0000, this would mean, the +* regions 14 and 15 are available to users. +* +* @param none +* @return The free region mask as a 16 bit value +* +* +******************************************************************************/ +u16 Xil_GetMPUFreeRegMask (void) { + u32 Index = 0U; + u16 FreeRegMask = 0U; + + while (Index < MAX_POSSIBLE_MPU_REGS) { + if (MPU_REG_DISABLED == Mpu_Config[Index].RegionStatus) { + FreeRegMask |= (1U << Index); + } + Index++; + } + return FreeRegMask; +} + +/*****************************************************************************/ +/** +* @brief Disables the corresponding region number as passed by the user. +* +* @param reg_num: The region number to be disabled +* @return XST_SUCCESS: If the region could be disabled successfully +* XST_FAILURE: If the requested region number is 16 or more. +* +* +******************************************************************************/ +u32 Xil_DisableMPURegionByRegNum (u32 reg_num) { + u32 Temp = 0U; + u32 ReturnVal = XST_FAILURE; + + if (reg_num >= 16U) { + xdbg_printf(DEBUG, "Invalid region number\r\n"); + goto exit1; + } + Xil_DCacheFlush(); + Xil_ICacheInvalidate(); + + mtcp(XREG_CP15_MPU_MEMORY_REG_NUMBER,reg_num); +#if defined (__GNUC__) + Temp = mfcp(XREG_CP15_MPU_REG_SIZE_EN); +#elif defined (__ICCARM__) + mfcp(XREG_CP15_MPU_REG_SIZE_EN,Temp); +#endif + Temp &= (~REGION_EN); + dsb(); + mtcp(XREG_CP15_MPU_REG_SIZE_EN,Temp); + dsb(); + isb(); + Xil_UpdateMPUConfig(reg_num, 0U, 0U, 0U); + ReturnVal = XST_SUCCESS; + +exit1: + return ReturnVal; +} + +/*****************************************************************************/ +/** +* @brief Enables the corresponding region number as passed by the user. +* +* @param reg_num: The region number to be enabled +* @param address: 32 bit address for start of the region. +* @param size: Requested size of the region. +* @param attrib: Attribute for the corresponding region. +* @return XST_SUCCESS: If the region could be created successfully +* XST_FAILURE: If the requested region number is 16 or more. +* +* +******************************************************************************/ +u32 Xil_SetMPURegionByRegNum (u32 reg_num, INTPTR addr, u64 size, u32 attrib) +{ + u32 ReturnVal = XST_SUCCESS; + INTPTR Localaddr = addr; + u32 Regionsize = 0; + u32 Index; + + if (reg_num >= 16U) { + xdbg_printf(DEBUG, "Invalid region number\r\n"); + ReturnVal = XST_FAILURE; + goto exit2; + } + + if (Mpu_Config[reg_num].RegionStatus == MPU_REG_ENABLED) { + xdbg_printf(DEBUG, "Region already enabled\r\n"); + ReturnVal = XST_FAILURE; + goto exit2; + } + + Xil_DCacheFlush(); + Xil_ICacheInvalidate(); + mtcp(XREG_CP15_MPU_MEMORY_REG_NUMBER,reg_num); + isb(); + + /* Lookup the size. */ + for (Index = 0; Index < + sizeof region_size / sizeof region_size[0]; Index++) { + if (size <= region_size[Index].size) { + Regionsize = region_size[Index].encoding; + break; + } + } + + Localaddr &= ~(region_size[Index].size - 1); + Regionsize <<= 1; + Regionsize |= REGION_EN; + dsb(); + mtcp(XREG_CP15_MPU_REG_BASEADDR, Localaddr); + mtcp(XREG_CP15_MPU_REG_ACCESS_CTRL, attrib); + mtcp(XREG_CP15_MPU_REG_SIZE_EN, Regionsize); + dsb(); + isb(); + Xil_UpdateMPUConfig(reg_num, Localaddr, Regionsize, attrib); +exit2: + return ReturnVal; + +} + +/*****************************************************************************/ +/** +* @brief Initializes the MPU configuration table that are setup in the +* R5 boot code in the Init_Mpu function called before C main. +* +* @param none +* @return none +* +* +******************************************************************************/ +void Xil_InitializeExistingMPURegConfig(void) +{ + u32 Index = 0U; + u32 Index1 = 0U; + u32 MPURegSize; + INTPTR MPURegBA; + u32 MPURegAttrib; + u32 Tempsize; + + while (Index < MAX_POSSIBLE_MPU_REGS) { + mtcp(XREG_CP15_MPU_MEMORY_REG_NUMBER,Index); +#if defined (__GNUC__) + MPURegSize = mfcp(XREG_CP15_MPU_REG_SIZE_EN); + MPURegBA = mfcp(XREG_CP15_MPU_REG_BASEADDR); + MPURegAttrib = mfcp(XREG_CP15_MPU_REG_ACCESS_CTRL); +#elif defined (__ICCARM__) + mfcp(XREG_CP15_MPU_REG_SIZE_EN,MPURegSize); + mfcp(XREG_CP15_MPU_REG_BASEADDR, MPURegBA); + mfcp(XREG_CP15_MPU_REG_ACCESS_CTRL, MPURegAttrib); +#endif + if (MPURegSize & REGION_EN) { + Mpu_Config[Index].RegionStatus = MPU_REG_ENABLED; + Mpu_Config[Index].BaseAddress = MPURegBA; + Mpu_Config[Index].Attribute = MPURegAttrib; + Tempsize = MPURegSize & (~REGION_EN); + Tempsize >>= 1; + for (Index1 = 0; Index1 < + (sizeof (region_size) / sizeof (region_size[0])); Index1++) { + if (Tempsize <= region_size[Index1].encoding) { + Mpu_Config[Index].Size = region_size[Index1].size; + break; + } + } + } + Index++; + } +} + +/*****************************************************************************/ +/** +* @brief Returns the next available free MPU region +* +* @param none +* @return The free MPU region available +* +* +******************************************************************************/ +u32 Xil_GetNextMPURegion(void) +{ + u32 Index = 0U; + u32 NextAvailableReg = 0xFF; + while (Index < MAX_POSSIBLE_MPU_REGS) { + if (Mpu_Config[Index].RegionStatus != MPU_REG_ENABLED) { + NextAvailableReg = Index; + break; + } + Index++; + } + return NextAvailableReg; +} diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_mpu.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_mpu.h new file mode 100644 index 000000000..95ffc66a7 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_mpu.h @@ -0,0 +1,134 @@ +/****************************************************************************** +* +* Copyright (C) 2014 - 2017 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file xil_mmu.h +* +* @addtogroup r5_mpu_apis Cortex R5 Processor MPU specific APIs +* +* MPU functions provides access to MPU operations such as enable MPU, disable +* MPU and set attribute for section of memory. +* Boot code invokes Init_MPU function to configure the MPU. A total of 10 MPU +* regions are allocated with another 6 being free for users. Overview of the +* memory attributes for different MPU regions is as given below, +* +*| | Memory Range | Attributes of MPURegion | +*|-----------------------|-------------------------|-----------------------------| +*| DDR | 0x00000000 - 0x7FFFFFFF | Normal write-back Cacheable | +*| PL | 0x80000000 - 0xBFFFFFFF | Strongly Ordered | +*| QSPI | 0xC0000000 - 0xDFFFFFFF | Device Memory | +*| PCIe | 0xE0000000 - 0xEFFFFFFF | Device Memory | +*| STM_CORESIGHT | 0xF8000000 - 0xF8FFFFFF | Device Memory | +*| RPU_R5_GIC | 0xF9000000 - 0xF90FFFFF | Device memory | +*| FPS | 0xFD000000 - 0xFDFFFFFF | Device Memory | +*| LPS | 0xFE000000 - 0xFFFFFFFF | Device Memory | +*| OCM | 0xFFFC0000 - 0xFFFFFFFF | Normal write-back Cacheable | +* +* +* @note +* For a system where DDR is less than 2GB, region after DDR and before PL is +* marked as undefined in translation table. Memory range 0xFE000000-0xFEFFFFFF is +* allocated for upper LPS slaves, where as memory region 0xFF000000-0xFFFFFFFF is +* allocated for lower LPS slaves. +* +* @{ +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 5.00  pkp  02/10/14 Initial version
+* 6.4   asa  08/16/17 Added many APIs for MPU access to make MPU usage
+* 					  user-friendly. The APIs added are: Xil_UpdateMPUConfig,
+* 					  Xil_GetMPUConfig, Xil_GetNumOfFreeRegions,
+* 					  Xil_GetNextMPURegion, Xil_DisableMPURegionByRegNum,
+* 					  Xil_GetMPUFreeRegMask, Xil_SetMPURegionByRegNum, and
+* 					  Xil_InitializeExistingMPURegConfig.
+* 					  Added a new array of structure of type XMpuConfig to
+* 					  represent the MPU configuration table.
+*
+* + +* +* +******************************************************************************/ + +#ifndef XIL_MPU_H +#define XIL_MPU_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ +#include "xil_types.h" +/***************************** Include Files *********************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ +#define MPU_REG_DISABLED 0U +#define MPU_REG_ENABLED 1U +#define MAX_POSSIBLE_MPU_REGS 16U +/**************************** Type Definitions *******************************/ +struct XMpuConfig{ + u32 RegionStatus; /* Enabled or disabled */ + INTPTR BaseAddress;/* MPU region base address */ + u64 Size; /* MPU region size address */ + u32 Attribute; /* MPU region size attribute */ +}; + +typedef struct XMpuConfig XMpu_Config[MAX_POSSIBLE_MPU_REGS]; + +extern XMpu_Config Mpu_Config; +/************************** Constant Definitions *****************************/ + +/************************** Variable Definitions *****************************/ + +/************************** Function Prototypes ******************************/ + +void Xil_SetTlbAttributes(INTPTR Addr, u32 attrib); +void Xil_EnableMPU(void); +void Xil_DisableMPU(void); +u32 Xil_SetMPURegion(INTPTR addr, u64 size, u32 attrib); +u32 Xil_UpdateMPUConfig(u32 reg_num, INTPTR address, u32 size, u32 attrib); +void Xil_GetMPUConfig (XMpu_Config mpuconfig); +u32 Xil_GetNumOfFreeRegions (void); +u32 Xil_GetNextMPURegion(void); +u32 Xil_DisableMPURegionByRegNum (u32 reg_num); +u16 Xil_GetMPUFreeRegMask (void); +u32 Xil_SetMPURegionByRegNum (u32 reg_num, INTPTR addr, u64 size, u32 attrib); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* XIL_MPU_H */ +/** +* @} End of "addtogroup r5_mpu_apis". +*/ \ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xil_printf.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_printf.c similarity index 80% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xil_printf.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_printf.c index 0f0db4fc9..dc0897f0d 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xil_printf.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_printf.c @@ -75,8 +75,8 @@ static void outs(const charptr lp, struct params_s *par) (par->num2)--; #ifdef STDOUT_BASEADDRESS outbyte(*LocalPtr); - LocalPtr += 1; #endif + LocalPtr += 1; } /* Pad on right if needed */ @@ -93,7 +93,6 @@ static void outs(const charptr lp, struct params_s *par) static void outnum( const s32 n, const s32 base, struct params_s *par) { - charptr cp; s32 negative; s32 i; char8 outbuf[32]; @@ -136,12 +135,66 @@ static void outnum( const s32 n, const s32 base, struct params_s *par) while (&outbuf[i] >= outbuf) { #ifdef STDOUT_BASEADDRESS outbyte( outbuf[i] ); - i--; #endif + i--; } padding( par->left_flag, par); } +/*---------------------------------------------------*/ +/* */ +/* This routine moves a 64-bit number to the output */ +/* buffer as directed by the padding and positioning */ +/* flags. */ +/* */ +#if defined (__aarch64__) +static void outnum1( const s64 n, const s32 base, params_t *par) +{ + s32 negative; + s32 i; + char8 outbuf[64]; + const char8 digits[] = "0123456789ABCDEF"; + u64 num; + for(i = 0; i<64; i++) { + outbuf[i] = '0'; + } + /* Check if number is negative */ + if ((par->unsigned_flag == 0) && (base == 10) && (n < 0L)) { + negative = 1; + num =(-(n)); + } + else{ + num = (n); + negative = 0; + } + + /* Build number (backwards) in outbuf */ + i = 0; + do { + outbuf[i] = digits[(num % base)]; + i++; + num /= base; + } while (num > 0); + + if (negative != 0) { + outbuf[i] = '-'; + i++; + } + + outbuf[i] = 0; + i--; + + /* Move the converted number to the buffer and */ + /* add in the padding where needed. */ + par->len = (s32)strlen(outbuf); + padding( !(par->left_flag), par); + while (&outbuf[i] >= outbuf) { + outbyte( outbuf[i] ); + i--; +} + padding( par->left_flag, par); +} +#endif /*---------------------------------------------------*/ /* */ /* This routine gets a number from the format */ @@ -186,10 +239,17 @@ static s32 getnum( charptr* linep) /* void esp_printf( const func_ptr f_ptr, const charptr ctrl1, ...) */ +#if HYP_GUEST && EL1_NONSECURE && XEN_USE_PV_CONSOLE +void xil_printf( const char8 *ctrl1, ...){ + XPVXenConsole_Printf(ctrl1); +} +#else void xil_printf( const char8 *ctrl1, ...) { s32 Check; +#if defined (__aarch64__) s32 long_flag; +#endif s32 dot_flag; params_t par; @@ -207,14 +267,16 @@ void xil_printf( const char8 *ctrl1, ...) if (*ctrl != '%') { #ifdef STDOUT_BASEADDRESS outbyte(*ctrl); - ctrl += 1; #endif + ctrl += 1; continue; } /* initialize all the flags for this format. */ dot_flag = 0; +#if defined (__aarch64__) long_flag = 0; +#endif par.unsigned_flag = 0; par.left_flag = 0; par.do_padding = 0; @@ -272,7 +334,9 @@ void xil_printf( const char8 *ctrl1, ...) break; case 'l': + #if defined (__aarch64__) long_flag = 1; + #endif Check = 0; break; @@ -281,19 +345,38 @@ void xil_printf( const char8 *ctrl1, ...) /* fall through */ case 'i': case 'd': - if ((long_flag != 0) || (ch == 'D')) { - outnum( va_arg(argp, s32), 10L, &par); + #if defined (__aarch64__) + if (long_flag != 0){ + outnum1((s64)va_arg(argp, s64), 10L, &par); } else { outnum( va_arg(argp, s32), 10L, &par); } + #else + outnum( va_arg(argp, s32), 10L, &par); + #endif Check = 1; break; case 'p': + #if defined (__aarch64__) + par.unsigned_flag = 1; + outnum1((s64)va_arg(argp, s64), 16L, &par); + Check = 1; + break; + #endif case 'X': case 'x': par.unsigned_flag = 1; + #if defined (__aarch64__) + if (long_flag != 0) { + outnum1((s64)va_arg(argp, s64), 16L, &par); + } + else { + outnum((s32)va_arg(argp, s32), 16L, &par); + } + #else outnum((s32)va_arg(argp, s32), 16L, &par); + #endif Check = 1; break; @@ -356,5 +439,5 @@ void xil_printf( const char8 *ctrl1, ...) } va_end( argp); } - +#endif /*---------------------------------------------------*/ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_printf.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_printf.h similarity index 91% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_printf.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_printf.h index 2be5c5734..016ae3b2f 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_printf.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_printf.h @@ -10,6 +10,10 @@ extern "C" { #include #include "xil_types.h" #include "xparameters.h" +#include "bspconfig.h" +#if HYP_GUEST && EL1_NONSECURE && XEN_USE_PV_CONSOLE +#include "xen_console.h" +#endif /*----------------------------------------------------*/ /* Use the following parameter passing structure to */ diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_sleepcommon.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_sleepcommon.c new file mode 100644 index 000000000..972a310a8 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_sleepcommon.c @@ -0,0 +1,106 @@ +/****************************************************************************** +* +* Copyright (C) 2017 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +*@file xil_sleepcommon.c +* +* This file contains the sleep API's +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 6.6 	srm  	 11/02/17 First release
+*
+******************************************************************************/ + + +/***************************** Include Files *********************************/ +#include "xil_io.h" +#include "sleep.h" + +/**************************** Constant Definitions *************************/ + + +/*****************************************************************************/ +/** +* +* This API gives delay in sec +* +* @param seconds - delay time in seconds +* +* @return none +* +* @note none +* +*****************************************************************************/ + void sleep(unsigned int seconds) + { +#if defined (ARMR5) + sleep_R5(seconds); +#elif defined (__aarch64__) || defined (ARMA53_32) + sleep_A53(seconds); +#elif defined (__MICROBLAZE__) + sleep_MB(seconds); +#else + sleep_A9(seconds); +#endif + + } + +/****************************************************************************/ +/** +* +* This API gives delay in usec +* +* @param useconds - delay time in useconds +* +* @return none +* +* @note none +* +*****************************************************************************/ + void usleep(unsigned long useconds) + { +#if defined (ARMR5) + usleep_R5(useconds); +#elif defined (__aarch64__) || defined (ARMA53_32) + usleep_A53(useconds); +#elif defined (__MICROBLAZE__) + usleep_MB(useconds); +#else + usleep_A9(useconds); +#endif + + } diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_sleeptimer.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_sleeptimer.c new file mode 100644 index 000000000..477260676 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_sleeptimer.c @@ -0,0 +1,161 @@ +/****************************************************************************** +* +* Copyright (C) 2017 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xil_sleeptimer.c +* +* This file provides the common helper routines for the sleep API's +* +* 
+* MODIFICATION HISTORY :
+*
+* Ver   Who  Date	 Changes
+* ----- ---- -------- -------------------------------------------------------
+* 6.6	srm  10/18/17 First Release.
+*
+*
+*****************************************************************************/ + +/**************************** Include Files ********************************/ + +#include "xil_io.h" +#include "xil_sleeptimer.h" +#include "xtime_l.h" + +/**************************** Constant Definitions *************************/ + + +/* Function definitions are applicable only when TTC3 is present*/ +#if defined (SLEEP_TIMER_BASEADDR) +/****************************************************************************/ +/** +* +* This is a helper function used by sleep/usleep APIs to +* have delay in sec/usec +* +* @param delay - delay time in seconds/micro seconds +* +* @param frequency - Number of counts per second/micro second +* +* @return none +* +* @note none +* +*****************************************************************************/ +void Xil_SleepTTCCommon(u32 delay, u64 frequency) +{ + INTPTR tEnd = 0U; + INTPTR tCur = 0U; + XCntrVal TimeHighVal = 0U; + XCntrVal TimeLowVal1 = 0U; + XCntrVal TimeLowVal2 = 0U; + + TimeLowVal1 = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR + + XSLEEP_TIMER_TTC_COUNT_VALUE_OFFSET); + tEnd = (INTPTR)TimeLowVal1 + ((INTPTR)(delay) * frequency); + do + { + TimeLowVal2 = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR + + XSLEEP_TIMER_TTC_COUNT_VALUE_OFFSET); + if (TimeLowVal2 < TimeLowVal1) { + TimeHighVal++; + } + TimeLowVal1 = TimeLowVal2; + tCur = (((INTPTR) TimeHighVal) << XSLEEP_TIMER_REG_SHIFT) | + (INTPTR)TimeLowVal2; + }while (tCur < tEnd); +} + + +/*****************************************************************************/ +/** +* +* This API starts the Triple Timer Counter +* +* @param none +* +* @return none +* +* @note none +* +*****************************************************************************/ +void XTime_StartTTCTimer() +{ + u32 TimerPrescalar; + u32 TimerCntrl; + +#if (defined (__aarch64__) && EL3==1) || defined (ARMR5) || defined (ARMA53_32) + u32 LpdRst; + + LpdRst = XSleep_ReadCounterVal(RST_LPD_IOU2); + + /* check if the timer is reset */ + if (((LpdRst & (RST_LPD_IOU2_TTC_BASE_RESET_MASK << + XSLEEP_TTC_INSTANCE)) != 0 )) { + LpdRst = LpdRst & (~(RST_LPD_IOU2_TTC_BASE_RESET_MASK << + XSLEEP_TTC_INSTANCE)); + Xil_Out32(RST_LPD_IOU2, LpdRst); + } else { +#endif + TimerCntrl = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR + + XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET); + /* check if Timer is disabled */ + if ((TimerCntrl & XSLEEP_TIMER_TTC_CNT_CNTRL_DIS_MASK) == 0) { + TimerPrescalar = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR + + XSLEEP_TIMER_TTC_CLK_CNTRL_OFFSET); + /* check if Timer is configured with proper functionalty for sleep */ + if ((TimerPrescalar & XSLEEP_TIMER_TTC_CLK_CNTRL_PS_EN_MASK) == 0) + return; + } +#if (defined (__aarch64__) && EL3==1) || defined (ARMR5) || defined (ARMA53_32) + } +#endif + /* Disable the timer to configure */ + TimerCntrl = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR + + XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET); + TimerCntrl = TimerCntrl | XSLEEP_TIMER_TTC_CNT_CNTRL_DIS_MASK; + Xil_Out32(SLEEP_TIMER_BASEADDR + XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET, + TimerCntrl); + /* Disable the prescalar */ + TimerPrescalar = XSleep_ReadCounterVal(SLEEP_TIMER_BASEADDR + + XSLEEP_TIMER_TTC_CLK_CNTRL_OFFSET); + TimerPrescalar = TimerPrescalar & (~XSLEEP_TIMER_TTC_CLK_CNTRL_PS_EN_MASK); + Xil_Out32(SLEEP_TIMER_BASEADDR + XSLEEP_TIMER_TTC_CLK_CNTRL_OFFSET, + TimerPrescalar); + /* Enable the Timer */ + TimerCntrl = TimerCntrl & (~XSLEEP_TIMER_TTC_CNT_CNTRL_DIS_MASK); + Xil_Out32(SLEEP_TIMER_BASEADDR + XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET, + TimerCntrl); +} +#endif diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_sleeptimer.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_sleeptimer.h new file mode 100644 index 000000000..4bfac0ac4 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_sleeptimer.h @@ -0,0 +1,116 @@ +/****************************************************************************** +* +* Copyright (C) 2017 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xil_sleeptimer.h +* +* This header file contains ARM Cortex A53,A9,R5 specific sleep related APIs. +* For sleep related functions that can be used across all Xilinx supported +* processors, please use xil_sleeptimer.h. +* +* +* 
+* MODIFICATION HISTORY :
+*
+* Ver   Who  Date	 Changes
+* ----- ---- -------- -------------------------------------------------------
+* 6.6	srm  10/18/17 First Release.
+*
+*
+*****************************************************************************/ + +#ifndef XIL_SLEEPTIMER_H /* prevent circular inclusions */ +#define XIL_SLEEPTIMER_H /* by using protection macros */ +/**************************** Include Files ********************************/ + +#include "xil_io.h" +#include "xparameters.h" +#include "bspconfig.h" + +/************************** Constant Definitions *****************************/ + +#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) +#define XSLEEP_TIMER_REG_SHIFT 32U +#define XSleep_ReadCounterVal Xil_In32 +#define XCntrVal u32 +#else +#define XSLEEP_TIMER_REG_SHIFT 16U +#define XSleep_ReadCounterVal Xil_In16 +#define XCntrVal u16 +#endif + +#if defined(ARMR5) || (defined (__aarch64__) && EL3==1) || defined (ARMA53_32) +#define RST_LPD_IOU2 0xFF5E0238U +#define RST_LPD_IOU2_TTC_BASE_RESET_MASK 0x00000800U +#endif + +#if defined (SLEEP_TIMER_BASEADDR) +/** @name Register Map +* +* Register offsets from the base address of the TTC device +* +* @{ +*/ + #define XSLEEP_TIMER_TTC_CLK_CNTRL_OFFSET 0x00000000U + /**< Clock Control Register */ + #define XSLEEP_TIMER_TTC_CNT_CNTRL_OFFSET 0x0000000CU + /**< Counter Control Register*/ + #define XSLEEP_TIMER_TTC_COUNT_VALUE_OFFSET 0x00000018U + /**< Current Counter Value */ +/* @} */ +/** @name Clock Control Register +* Clock Control Register definitions of TTC +* @{ +*/ + #define XSLEEP_TIMER_TTC_CLK_CNTRL_PS_EN_MASK 0x00000001U + /**< Prescale enable */ +/* @} */ +/** @name Counter Control Register +* Counter Control Register definitions of TTC +* @{ +*/ +#define XSLEEP_TIMER_TTC_CNT_CNTRL_DIS_MASK 0x00000001U + /**< Disable the counter */ +#define XSLEEP_TIMER_TTC_CNT_CNTRL_RST_MASK 0x00000010U + /**< Reset counter */ +/* @} */ + +/**************************** Type Definitions *******************************/ + +/************************** Function Prototypes ******************************/ + +void Xil_SleepTTCCommon(u32 delay, u64 frequency); +void XTime_StartTTCTimer(); + +#endif +#endif /* XIL_SLEEPTIMER_H */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xil_testcache.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_testcache.c similarity index 83% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xil_testcache.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_testcache.c index a2c4b0bbf..157ad0836 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xil_testcache.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_testcache.c @@ -47,7 +47,6 @@ * * * @note -* * This file contain functions that all operate on HAL. * ******************************************************************************/ @@ -74,17 +73,21 @@ static INTPTR Data[DATA_LENGTH] __attribute__ ((aligned(64))); static INTPTR Data[DATA_LENGTH] __attribute__ ((aligned(32))); #endif + +/*****************************************************************************/ /** -* Perform DCache range related API test such as Xil_DCacheFlushRange and -* Xil_DCacheInvalidateRange. This test function writes a constant value -* to the Data array, flushes the range, writes a new value, then invalidates -* the corresponding range. +* +* @brief Perform DCache range related API test such as Xil_DCacheFlushRange +* and Xil_DCacheInvalidateRange. This test function writes a constant +* value to the Data array, flushes the range, writes a new value, then +* invalidates the corresponding range. +* @param None * * @return +* - -1 is returned for a failure +* - 0 is returned for a pass * -* - 0 is returned for a pass -* - -1 is returned for a failure -*/ +*****************************************************************************/ s32 Xil_TestDCacheRange(void) { s32 Index; @@ -204,16 +207,17 @@ s32 Xil_TestDCacheRange(void) } +/*****************************************************************************/ /** -* Perform DCache all related API test such as Xil_DCacheFlush and -* Xil_DCacheInvalidate. This test function writes a constant value -* to the Data array, flushes the DCache, writes a new value, then invalidates -* the DCache. +* @brief Perform DCache all related API test such as Xil_DCacheFlush and +* Xil_DCacheInvalidate. This test function writes a constant value +* to the Data array, flushes the DCache, writes a new value, +* then invalidates the DCache. * * @return -* - 0 is returned for a pass -* - -1 is returned for a failure -*/ +* - 0 is returned for a pass +* - -1 is returned for a failure +*****************************************************************************/ s32 Xil_TestDCacheAll(void) { s32 Index; @@ -328,15 +332,15 @@ s32 Xil_TestDCacheAll(void) return Status; } - +/*****************************************************************************/ /** -* Perform Xil_ICacheInvalidateRange() on a few function pointers. +* @brief Perform Xil_ICacheInvalidateRange() on a few function pointers. * * @return -* * - 0 is returned for a pass +* @note * The function will hang if it fails. -*/ +*****************************************************************************/ s32 Xil_TestICacheRange(void) { @@ -349,14 +353,15 @@ s32 Xil_TestICacheRange(void) return 0; } +/*****************************************************************************/ /** -* Perform Xil_ICacheInvalidate(). +* @brief Perform Xil_ICacheInvalidate() on a few function pointers. * * @return -* -* - 0 is returned for a pass -* The function will hang if it fails. -*/ +* - 0 is returned for a pass +* @note +* The function will hang if it fails. +*****************************************************************************/ s32 Xil_TestICacheAll(void) { Xil_ICacheInvalidate(); diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_testcache.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_testcache.h similarity index 92% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_testcache.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_testcache.h index b3c416cd0..c35e9a463 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_testcache.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_testcache.h @@ -34,11 +34,16 @@ * * @file xil_testcache.h * -* This file contains utility functions to test cache. +* @addtogroup common_test_utils +*

Cache test

+* The xil_testcache.h file contains utility functions to test cache. * +* @{ +* 
 * Ver    Who    Date    Changes
 * ----- ---- -------- -----------------------------------------------
 * 1.00a hbm  07/29/09 First release
+*
* ******************************************************************************/ @@ -61,3 +66,6 @@ extern s32 Xil_TestICacheAll(void); #endif #endif /* end of protection macro */ +/** +* @} End of "addtogroup common_test_utils". +*/ \ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xil_testio.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_testio.c similarity index 70% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xil_testio.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_testio.c index a68d7652f..e6a36807b 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xil_testio.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_testio.c @@ -32,7 +32,7 @@ /*****************************************************************************/ /** * -* @file xil_testmemend.c +* @file xil_testio.c * * Contains the memory test utility functions. * @@ -95,18 +95,17 @@ static u32 Swap32(u32 Data) /*****************************************************************************/ /** * -* Perform a destructive 8-bit wide register IO test where the register is -* accessed using Xil_Out8 and Xil_In8, and comparing the reading and writing -* values. +* @brief Perform a destructive 8-bit wide register IO test where the +* register is accessed using Xil_Out8 and Xil_In8, and comparing +* the written values by reading them back. * -* @param Addr is a pointer to the region of memory to be tested. -* @param Length is the Length of the block. -* @param Value is the constant used for writting the memory. +* @param Addr: a pointer to the region of memory to be tested. +* @param Length: Length of the block. +* @param Value: constant used for writting the memory. * * @return -* -* - -1 is returned for a failure -* - 0 is returned for a pass +* - -1 is returned for a failure +* - 0 is returned for a pass * *****************************************************************************/ @@ -133,24 +132,24 @@ s32 Xil_TestIO8(u8 *Addr, s32 Length, u8 Value) /*****************************************************************************/ /** * -* Perform a destructive 16-bit wide register IO test. Each location is tested -* by sequentially writing a 16-bit wide register, reading the register, and -* comparing value. This function tests three kinds of register IO functions, -* normal register IO, little-endian register IO, and big-endian register IO. -* When testing little/big-endian IO, the function performs the following -* sequence, Xil_Out16LE/Xil_Out16BE, Xil_In16, Compare In-Out values, -* Xil_Out16, Xil_In16LE/Xil_In16BE, Compare In-Out values. Whether to swap the -* read-in value before comparing is controlled by the 5th argument. +* @brief Perform a destructive 16-bit wide register IO test. Each location +* is tested by sequentially writing a 16-bit wide register, reading +* the register, and comparing value. This function tests three kinds +* of register IO functions, normal register IO, little-endian register +* IO, and big-endian register IO. When testing little/big-endian IO, +* the function performs the following sequence, Xil_Out16LE/Xil_Out16BE, +* Xil_In16, Compare In-Out values, Xil_Out16, Xil_In16LE/Xil_In16BE, +* Compare In-Out values. Whether to swap the read-in value before +* comparing is controlled by the 5th argument. * -* @param Addr is a pointer to the region of memory to be tested. -* @param Length is the Length of the block. -* @param Value is the constant used for writting the memory. -* @param Kind is the test kind. Acceptable values are: -* XIL_TESTIO_DEFAULT, XIL_TESTIO_LE, XIL_TESTIO_BE. -* @param Swap indicates whether to byte swap the read-in value. +* @param Addr: a pointer to the region of memory to be tested. +* @param Length: Length of the block. +* @param Value: constant used for writting the memory. +* @param Kind: Type of test. Acceptable values are: +* XIL_TESTIO_DEFAULT, XIL_TESTIO_LE, XIL_TESTIO_BE. +* @param Swap: indicates whether to byte swap the read-in value. * * @return -* * - -1 is returned for a failure * - 0 is returned for a pass * @@ -219,26 +218,25 @@ s32 Xil_TestIO16(u16 *Addr, s32 Length, u16 Value, s32 Kind, s32 Swap) /*****************************************************************************/ /** * -* Perform a destructive 32-bit wide register IO test. Each location is tested -* by sequentially writing a 32-bit wide regsiter, reading the register, and -* comparing value. This function tests three kinds of register IO functions, -* normal register IO, little-endian register IO, and big-endian register IO. -* When testing little/big-endian IO, the function perform the following -* sequence, Xil_Out32LE/Xil_Out32BE, Xil_In32, Compare, -* Xil_Out32, Xil_In32LE/Xil_In32BE, Compare. Whether to swap the read-in value -* before comparing is controlled by the 5th argument. -* -* @param Addr is a pointer to the region of memory to be tested. -* @param Length is the Length of the block. -* @param Value is the constant used for writting the memory. -* @param Kind is the test kind. Acceptable values are: -* XIL_TESTIO_DEFAULT, XIL_TESTIO_LE, XIL_TESTIO_BE. -* @param Swap indicates whether to byte swap the read-in value. +* @brief Perform a destructive 32-bit wide register IO test. Each location +* is tested by sequentially writing a 32-bit wide regsiter, reading +* the register, and comparing value. This function tests three kinds +* of register IO functions, normal register IO, little-endian register IO, +* and big-endian register IO. When testing little/big-endian IO, +* the function perform the following sequence, Xil_Out32LE/ +* Xil_Out32BE, Xil_In32, Compare, Xil_Out32, Xil_In32LE/Xil_In32BE, Compare. +* Whether to swap the read-in value *before comparing is controlled +* by the 5th argument. +* @param Addr: a pointer to the region of memory to be tested. +* @param Length: Length of the block. +* @param Value: constant used for writting the memory. +* @param Kind: type of test. Acceptable values are: +* XIL_TESTIO_DEFAULT, XIL_TESTIO_LE, XIL_TESTIO_BE. +* @param Swap: indicates whether to byte swap the read-in value. * * @return -* -* - -1 is returned for a failure -* - 0 is returned for a pass +* - -1 is returned for a failure +* - 0 is returned for a pass * *****************************************************************************/ s32 Xil_TestIO32(u32 *Addr, s32 Length, u32 Value, s32 Kind, s32 Swap) diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_testio.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_testio.h similarity index 93% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_testio.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_testio.h index fba0c1060..ad68ead64 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_testio.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_testio.h @@ -32,19 +32,19 @@ /*****************************************************************************/ /** * -* @file xil_testmemend.h +* @file xil_testio.h * -* This file contains utility functions to teach endian related memory +* @addtogroup common_test_utils Test Utilities +*

I/O test

+* The xil_testio.h file contains utility functions to test endian related memory * IO functions. * -* Memory test description -* * A subset of the memory tests can be selected or all of the tests can be run * in order. If there is an error detected by a subtest, the test stops and the * failure code is returned. Further tests are not run even if all of the tests * are selected. * -* +* @{ * 
 * MODIFICATION HISTORY:
 *
@@ -89,3 +89,6 @@ extern s32 Xil_TestIO32(u32 *Addr, s32 Length, u32 Value, s32 Kind, s32 Swap);
 #endif
 
 #endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_test_utils".
+*/
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_testmem.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_testmem.c
similarity index 92%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_testmem.c
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_testmem.c
index 19a3b6608..87426d17a 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_testmem.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_testmem.c
@@ -66,22 +66,20 @@ static u32 RotateRight(u32 Input, u8 Width);
 /*****************************************************************************/
 /**
 *
-* Perform a destructive 32-bit wide memory test.
+* @brief    Perform a destructive 32-bit wide memory test.
 *
-* @param    Addr is a pointer to the region of memory to be tested.
-* @param    Words is the length of the block.
-* @param    Pattern is the constant used for the constant pattern test, if 0,
+* @param    Addr: pointer to the region of memory to be tested.
+* @param    Words: length of the block.
+* @param    Pattern: constant used for the constant pattern test, if 0,
 *           0xDEADBEEF is used.
-* @param    Subtest is the test selected. See xil_testmem.h for possible
-*	    values.
+* @param    Subtest: test type selected. See xil_testmem.h for possible
+*	        values.
 *
 * @return
-*
-* - 0 is returned for a pass
-* - -1 is returned for a failure
+*           - 0 is returned for a pass
+*           - 1 is returned for a failure
 *
 * @note
-*
 * Used for spaces where the address range of the region is smaller than
 * the data width. If the memory range is greater than 2 ** Width,
 * the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
@@ -315,22 +313,21 @@ End_Label:
 /*****************************************************************************/
 /**
 *
-* Perform a destructive 16-bit wide memory test.
+* @brief    Perform a destructive 16-bit wide memory test.
 *
-* @param    Addr is a pointer to the region of memory to be tested.
-* @param    Words is the length of the block.
-* @param    Pattern is the constant used for the constant Pattern test, if 0,
+* @param    Addr: pointer to the region of memory to be tested.
+* @param    Words: length of the block.
+* @param    Pattern: constant used for the constant Pattern test, if 0,
 *           0xDEADBEEF is used.
-* @param    Subtest is the test selected. See xil_testmem.h for possible
-*	    values.
+* @param    Subtest: type of test selected. See xil_testmem.h for possible
+*	        values.
 *
 * @return
 *
-* - -1 is returned for a failure
-* - 0 is returned for a pass
+*           - -1 is returned for a failure
+*           - 0 is returned for a pass
 *
 * @note
-*
 * Used for spaces where the address range of the region is smaller than
 * the data width. If the memory range is greater than 2 ** Width,
 * the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
@@ -549,22 +546,20 @@ End_Label:
 /*****************************************************************************/
 /**
 *
-* Perform a destructive 8-bit wide memory test.
+* @brief    Perform a destructive 8-bit wide memory test.
 *
-* @param    Addr is a pointer to the region of memory to be tested.
-* @param    Words is the length of the block.
-* @param    Pattern is the constant used for the constant pattern test, if 0,
+* @param    Addr: pointer to the region of memory to be tested.
+* @param    Words: length of the block.
+* @param    Pattern: constant used for the constant pattern test, if 0,
 *           0xDEADBEEF is used.
-* @param    Subtest is the test selected. See xil_testmem.h for possible
-*	    values.
+* @param    Subtest: type of test selected. See xil_testmem.h for possible
+*	        values.
 *
 * @return
-*
-* - -1 is returned for a failure
-* - 0 is returned for a pass
+*           - -1 is returned for a failure
+*           - 0 is returned for a pass
 *
 * @note
-*
 * Used for spaces where the address range of the region is smaller than
 * the data width. If the memory range is greater than 2 ** Width,
 * the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
@@ -777,18 +772,14 @@ End_Label:
 /*****************************************************************************/
 /**
 *
-* Rotates the provided value to the left one bit position
+* @brief   Rotates the provided value to the left one bit position
 *
 * @param    Input is value to be rotated to the left
 * @param    Width is the number of bits in the input data
 *
 * @return
+*           The resulting unsigned long value of the rotate left
 *
-* The resulting unsigned long value of the rotate left
-*
-* @note
-*
-* None.
 *
 *****************************************************************************/
 static u32 RotateLeft(u32 Input, u8 Width)
@@ -831,18 +822,13 @@ static u32 RotateLeft(u32 Input, u8 Width)
 /*****************************************************************************/
 /**
 *
-* Rotates the provided value to the right one bit position
+* @brief    Rotates the provided value to the right one bit position
 *
-* @param    Input is value to be rotated to the right
-* @param    Width is the number of bits in the input data
+* @param    Input: value to be rotated to the right
+* @param    Width: number of bits in the input data
 *
 * @return
-*
-* The resulting u32 value of the rotate right
-*
-* @note
-*
-* None.
+*           The resulting u32 value of the rotate right
 *
 *****************************************************************************/
 static u32 RotateRight(u32 Input, u8 Width)
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_testmem.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_testmem.h
similarity index 79%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_testmem.h
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_testmem.h
index 4cbfd878b..c20472822 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xil_testmem.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_testmem.h
@@ -33,64 +33,57 @@
 /**
 *
 * @file xil_testmem.h
+* @addtogroup common_test_utils
 *
-* This file contains utility functions to test memory.
-*
-* Memory test description
+* 
Memory test

 *
+* The xil_testmem.h file contains utility functions to test memory.
 * A subset of the memory tests can be selected or all of the tests can be run
 * in order. If there is an error detected by a subtest, the test stops and the
 * failure code is returned. Further tests are not run even if all of the tests
 * are selected.
+* Following list describes the supported memory tests:
 *
-* Subtest descriptions:
-* 
-* XIL_TESTMEM_ALLMEMTESTS:
-*       Runs all of the following tests
+*  - XIL_TESTMEM_ALLMEMTESTS: This test runs all of the subtests.
 *
-* XIL_TESTMEM_INCREMENT:
-*       Incrementing Value Test.
-*       This test starts at 'XIL_TESTMEM_INIT_VALUE' and uses the
-*	incrementing value as the test value for memory.
+*  - XIL_TESTMEM_INCREMENT: This test
+* starts at 'XIL_TESTMEM_INIT_VALUE' and uses the incrementing value as the
+* test value for memory.
 *
-* XIL_TESTMEM_WALKONES:
-*       Walking Ones Test.
-*       This test uses a walking '1' as the test value for memory.
-*       location 1 = 0x00000001
-*       location 2 = 0x00000002
-*       ...
+*  - XIL_TESTMEM_WALKONES: Also known as the Walking ones test. This test
+* uses a walking '1' as the test value for memory.
+* @code
+*          location 1 = 0x00000001
+*          location 2 = 0x00000002
+*          ...
+* @endcode
 *
-* XIL_TESTMEM_WALKZEROS:
-*       Walking Zero's Test.
-*       This test uses the inverse value of the walking ones test
-*       as the test value for memory.
+*  - XIL_TESTMEM_WALKZEROS: Also known as the Walking zero's test.
+* This test uses the inverse value of the walking ones test
+* as the test value for memory.
+* @code
 *       location 1 = 0xFFFFFFFE
 *       location 2 = 0xFFFFFFFD
 *       ...
+*@endcode
 *
-* XIL_TESTMEM_INVERSEADDR:
-*       Inverse Address Test.
-*       This test uses the inverse of the address of the location under test
-*       as the test value for memory.
+*  - XIL_TESTMEM_INVERSEADDR: Also known as the inverse address test.
+* This test uses the inverse of the address of the location under test
+* as the test value for memory.
 *
-* XIL_TESTMEM_FIXEDPATTERN:
-*       Fixed Pattern Test.
-*       This test uses the provided patters as the test value for memory.
-*       If zero is provided as the pattern the test uses '0xDEADBEEF".
-* 

-*
-* WARNING
+*  - XIL_TESTMEM_FIXEDPATTERN: Also known as the fixed pattern test.
+* This test uses the provided patters as the test value for memory.
+* If zero is provided as the pattern the test uses '0xDEADBEEF".
 *
+* @warning
 * The tests are DESTRUCTIVE. Run before any initialized memory spaces
 * have been set up.
-*
 * The address provided to the memory tests is not checked for
 * validity except for the NULL case. It is possible to provide a code-space
 * pointer for this test to start with and ultimately destroy executable code
 * causing random failures.
 *
 * @note
-*
 * Used for spaces where the address range of the region is smaller than
 * the data width. If the memory range is greater than 2 ** width,
 * the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
@@ -160,3 +153,6 @@ extern s32 Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest);
 #endif
 
 #endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_test_utils".
+*/
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_types.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_types.h
similarity index 76%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_types.h
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_types.h
index e8b78b7c6..8143aff1e 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xil_types.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xil_types.h
@@ -34,9 +34,11 @@
 *
 * @file xil_types.h
 *
-* This file contains basic types for Xilinx software IP.
-
+* @addtogroup common_types Basic Data types for Xilinx® Software IP
 *
+* The xil_types.h file contains basic types for Xilinx software IP. These data types
+* are applicable for all processors supported by Xilinx.
+* @{
 * 
 * MODIFICATION HISTORY:
 *
@@ -71,22 +73,28 @@
 #define NULL		0U
 #endif
 
-#define XIL_COMPONENT_IS_READY     0x11111111U  /**< component has been initialized */
-#define XIL_COMPONENT_IS_STARTED   0x22222222U  /**< component has been started */
+#define XIL_COMPONENT_IS_READY     0x11111111U  /**< In device drivers, This macro will be
+                                                 assigend to "IsReady" member of driver
+												 instance to indicate that driver
+												 instance is initialized and ready to use. */
+#define XIL_COMPONENT_IS_STARTED   0x22222222U  /**< In device drivers, This macro will be assigend to
+                                                 "IsStarted" member of driver instance
+												 to indicate that driver instance is
+												 started and it can be enabled. */
 
-/** @name New types
+/* @name New types
  * New simple types.
  * @{
  */
 #ifndef __KERNEL__
 #ifndef XBASIC_TYPES_H
-/**
+/*
  * guarded against xbasic_types.h.
  */
 typedef uint8_t u8;
 typedef uint16_t u16;
 typedef uint32_t u32;
-
+/** @}*/
 #define __XUINT64__
 typedef struct
 {
@@ -97,36 +105,32 @@ typedef struct
 
 /*****************************************************************************/
 /**
-* Return the most significant half of the 64 bit data type.
+* @brief    Return the most significant half of the 64 bit data type.
 *
 * @param    x is the 64 bit word.
 *
 * @return   The upper 32 bits of the 64 bit word.
 *
-* @note     None.
-*
 ******************************************************************************/
 #define XUINT64_MSW(x) ((x).Upper)
 
 /*****************************************************************************/
 /**
-* Return the least significant half of the 64 bit data type.
+* @brief    Return the least significant half of the 64 bit data type.
 *
 * @param    x is the 64 bit word.
 *
 * @return   The lower 32 bits of the 64 bit word.
 *
-* @note     None.
-*
 ******************************************************************************/
 #define XUINT64_LSW(x) ((x).Lower)
 
 #endif /* XBASIC_TYPES_H */
 
-/**
+/*
  * xbasic_types.h does not typedef s* or u64
  */
-
+/** @{ */
 typedef char char8;
 typedef int8_t s8;
 typedef int16_t s16;
@@ -138,7 +142,7 @@ typedef int sint32;
 typedef intptr_t INTPTR;
 typedef uintptr_t UINTPTR;
 typedef ptrdiff_t PTRDIFF;
-
+/** @}*/
 #if !defined(LONG) || !defined(ULONG)
 typedef long LONG;
 typedef unsigned long ULONG;
@@ -151,7 +155,7 @@ typedef unsigned long ULONG;
 #include 
 #endif
 
-
+/** @{ */
 /**
  * This data type defines an interrupt handler for a device.
  * The argument points to the instance of the component
@@ -165,22 +169,24 @@ typedef void (*XInterruptHandler) (void *InstancePtr);
 typedef void (*XExceptionHandler) (void *InstancePtr);
 
 /**
- * UPPER_32_BITS - return bits 32-63 of a number
- * @n: the number we're accessing
+ * @brief  Returns 32-63 bits of a number.
+ * @param  n : Number being accessed.
+ * @return Bits 32-63 of number.
  *
- * A basic shift-right of a 64- or 32-bit quantity.  Use this to suppress
- * the "right shift count >= width of type" warning when that quantity is
- * 32-bits.
+ * @note    A basic shift-right of a 64- or 32-bit quantity.
+ *          Use this to suppress the "right shift count >= width of type"
+ *          warning when that quantity is 32-bits.
  */
 #define UPPER_32_BITS(n) ((u32)(((n) >> 16) >> 16))
 
 /**
- * LOWER_32_BITS - return bits 0-31 of a number
- * @n: the number we're accessing
+ * @brief  Returns 0-31 bits of a number
+ * @param  n : Number being accessed.
+ * @return Bits 0-31 of number
  */
 #define LOWER_32_BITS(n) ((u32)(n))
 
-/*@}*/
+
 
 
 /************************** Constant Definitions *****************************/
@@ -198,3 +204,6 @@ typedef void (*XExceptionHandler) (void *InstancePtr);
 #endif
 
 #endif	/* end of protection macro */
+/**
+* @} End of "addtogroup common_types".
+*/
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xparameters_ps.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xparameters_ps.h
similarity index 88%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xparameters_ps.h
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xparameters_ps.h
index 2f527c90a..260c4d563 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xparameters_ps.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xparameters_ps.h
@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+* Copyright (C) 2014 - 2017 Xilinx, Inc. All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
@@ -33,9 +33,14 @@
 /**
 * @file xparameters_ps.h
 *
-* This file contains the address definitions for the hard peripherals
-* attached to the ARM Cortex R5 core.
+* @addtogroup r5_peripheral_definitions Cortex R5 peripheral definitions
 *
+* The xparameters_ps.h file contains the canonical definitions and constant
+* declarations for peripherals within hardblock, attached to the ARM Cortex R5
+* core. These definitions can be used by drivers or applications to access the
+* peripherals.
+*
+* @{
 * 
 * MODIFICATION HISTORY:
 *
@@ -45,10 +50,6 @@
 * 6.0   mus     08/18/16 Defined ARMR5 flag
 * 

 *
-* @note
-*
-* None.
-*
 ******************************************************************************/
 
 #ifndef XPARAMETERS_PS_H_
@@ -62,6 +63,8 @@
 extern "C" {
 #endif
 
+/***************************** Include Files *********************************/
+
 /************************** Constant Definitions *****************************/
 
 /*
@@ -94,8 +97,9 @@ extern "C" {
 #define XPAR_XSDIOPS_0_INTR		XPS_SDIO0_INT_ID
 #define XPAR_XQSPIPS_0_INTR		XPS_QSPI_INT_ID
 #define XPAR_XSDIOPS_1_INTR		XPS_SDIO1_INT_ID
-#define XPAR_XWDTPS_0_INTR		XPS_LPD_SWDT_INT_ID
-#define XPAR_XWDTPS_1_INTR		XPS_FPD_SWDT_INT_ID
+#define XPAR_XWDTPS_0_INTR		XPS_CSU_WDT_INT_ID
+#define XPAR_XWDTPS_1_INTR		XPS_LPD_SWDT_INT_ID
+#define XPAR_XWDTPS_2_INTR		XPS_FPD_SWDT_INT_ID
 #define XPAR_XDCFG_0_INTR		XPS_DVC_INT_ID
 #define XPAR_XTTCPS_0_INTR		XPS_TTC0_0_INT_ID
 #define XPAR_XTTCPS_1_INTR		XPS_TTC0_1_INT_ID
@@ -119,6 +123,15 @@ extern "C" {
 #define XPAR_XADMAPS_6_INTR 		XPS_ADMA_CH6_INT_ID
 #define XPAR_XADMAPS_7_INTR 		XPS_ADMA_CH7_INT_ID
 #define XPAR_XCSUDMA_INTR 		XPS_CSU_DMA_INT_ID
+#define XPAR_PSU_ADMA_0_INTR 		XPS_ADMA_CH0_INT_ID
+#define XPAR_PSU_ADMA_1_INTR 		XPS_ADMA_CH1_INT_ID
+#define XPAR_PSU_ADMA_2_INTR		XPS_ADMA_CH2_INT_ID
+#define XPAR_PSU_ADMA_3_INTR 		XPS_ADMA_CH3_INT_ID
+#define XPAR_PSU_ADMA_4_INTR		XPS_ADMA_CH4_INT_ID
+#define XPAR_PSU_ADMA_5_INTR 		XPS_ADMA_CH5_INT_ID
+#define XPAR_PSU_ADMA_6_INTR 		XPS_ADMA_CH6_INT_ID
+#define XPAR_PSU_ADMA_7_INTR 		XPS_ADMA_CH7_INT_ID
+#define XPAR_PSU_CSUDMA_INTR 		XPS_CSU_DMA_INT_ID
 #define XPAR_XMPU_LPD_INTR 		XPS_XMPU_LPD_INT_ID
 #define XPAR_XZDMAPS_0_INTR		XPS_ZDMA_CH0_INT_ID
 #define XPAR_XZDMAPS_1_INTR		XPS_ZDMA_CH1_INT_ID
@@ -128,6 +141,14 @@ extern "C" {
 #define XPAR_XZDMAPS_5_INTR 		XPS_ZDMA_CH5_INT_ID
 #define XPAR_XZDMAPS_6_INTR 		XPS_ZDMA_CH6_INT_ID
 #define XPAR_XZDMAPS_7_INTR 		XPS_ZDMA_CH7_INT_ID
+#define XPAR_PSU_GDMA_0_INTR		XPS_ZDMA_CH0_INT_ID
+#define XPAR_PSU_GDMA_1_INTR		XPS_ZDMA_CH1_INT_ID
+#define XPAR_PSU_GDMA_2_INTR 		XPS_ZDMA_CH2_INT_ID
+#define XPAR_PSU_GDMA_3_INTR 		XPS_ZDMA_CH3_INT_ID
+#define XPAR_PSU_GDMA_4_INTR		XPS_ZDMA_CH4_INT_ID
+#define XPAR_PSU_GDMA_5_INTR 		XPS_ZDMA_CH5_INT_ID
+#define XPAR_PSU_GDMA_6_INTR 		XPS_ZDMA_CH6_INT_ID
+#define XPAR_PSU_GDMA_7_INTR 		XPS_ZDMA_CH7_INT_ID
 #define XPAR_XMPU_FPD_INTR 		XPS_XMPU_FPD_INT_ID
 #define XPAR_XCCI_FPD_INTR 		XPS_FPD_CCI_INT_ID
 #define XPAR_XSMMU_FPD_INTR 		XPS_FPD_SMMU_INT_ID
@@ -194,6 +215,7 @@ extern "C" {
 #define	XPS_RTC_ALARM_INT_ID 	(26U + 32U)
 #define	XPS_RTC_SEC_INT_ID	 	(27U + 32U)
 #define XPS_LPD_SWDT_INT_ID		(52U + 32U)
+#define XPS_CSU_WDT_INT_ID	    (53U + 32U)
 #define XPS_FPD_SWDT_INT_ID		(113U + 32U)
 #define XPS_TTC0_0_INT_ID		(36U + 32U)
 #define XPS_TTC0_1_INT_ID		(37U + 32U)
@@ -282,6 +304,7 @@ extern "C" {
 #define XPAR_PSU_TTC_9_INTR			XPS_TTC3_0_INT_ID
 #define XPAR_PSU_TTC_10_INTR		XPS_TTC3_1_INT_ID
 #define XPAR_PSU_TTC_11_INTR		XPS_TTC3_2_INT_ID
+#define XPAR_PSU_AMS_INTR			XPS_AMS_INT_ID
 
 #define XPAR_XADCPS_NUM_INSTANCES 1U
 #define XPAR_XADCPS_0_DEVICE_ID   0U
@@ -318,3 +341,6 @@ extern "C" {
 #endif
 
 #endif /* protection macro */
+/**
+* @} End of "addtogroup r5_peripheral_definitions".
+*/
\ No newline at end of file
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xplatform_info.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xplatform_info.c
similarity index 72%
rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xplatform_info.c
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xplatform_info.c
index fea992e40..2c08e5f2e 100644
--- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xplatform_info.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xplatform_info.c
@@ -44,6 +44,14 @@
 * 5.00  pkp  12/15/14 Initial release
 * 5.04  pkp  01/12/16 Added platform information support for Cortex-A53 32bit
 *					  mode
+* 6.00  mus  17/08/16 Removed unused variable from XGetPlatform_Info
+* 6.4   ms   05/23/17 Added PSU_PMU macro to support XGetPSVersion_Info
+*                     function for PMUFW.
+*       ms   06/13/17 Added PSU_PMU macro to provide support of
+*                     XGetPlatform_Info function for PMUFW.
+*       mus  08/17/17 Add EL1 NS mode support for
+*                     XGet_Zynq_UltraMp_Platform_info and XGetPSVersion_Info
+*                     APIs.
 * 

 *
 ******************************************************************************/
@@ -51,8 +59,12 @@
 /***************************** Include Files *********************************/
 
 #include "xil_types.h"
+#include "xil_io.h"
 #include "xplatform_info.h"
-
+#if defined (__aarch64__)
+#include "bspconfig.h"
+#include "xil_smc.h"
+#endif
 /************************** Constant Definitions *****************************/
 
 /**************************** Type Definitions *******************************/
@@ -67,19 +79,17 @@
 /*****************************************************************************/
 /**
 *
-* This API is used to provide information about platform
+* @brief    This API is used to provide information about platform
 *
 * @param    None.
 *
 * @return   The information about platform defined in xplatform_info.h
 *
-* @note     None.
-*
 ******************************************************************************/
 u32 XGetPlatform_Info()
 {
-	u32 reg;
-#if defined (ARMR5) || (__aarch64__) || (ARMA53_32)
+
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) || (PSU_PMU)
 	return XPLAT_ZYNQ_ULTRA_MP;
 #elif (__microblaze__)
 	return XPLAT_MICROBLAZE;
@@ -91,43 +101,61 @@ u32 XGetPlatform_Info()
 /*****************************************************************************/
 /**
 *
-* This API is used to provide information about zynq ultrascale MP platform
+* @brief    This API is used to provide information about zynq ultrascale MP platform
 *
 * @param    None.
 *
 * @return   The information about zynq ultrascale MP platform defined in
 *			xplatform_info.h
 *
-* @note     None.
-*
 ******************************************************************************/
 #if defined (ARMR5) || (__aarch64__) || (ARMA53_32)
 u32 XGet_Zynq_UltraMp_Platform_info()
 {
+#if EL1_NONSECURE
+	XSmc_OutVar reg;
+    /*
+	 * This SMC call will return,
+     *  idcode - upper 32 bits of reg.Arg0
+     *  version - lower 32 bits of reg.Arg1
+	 */
+	reg = Xil_Smc(GET_CHIPID_SMC_FID,0,0, 0, 0, 0, 0, 0);
+	return (u32)((reg.Arg1 >> XPLAT_INFO_SHIFT) & XPLAT_INFO_MASK);
+#else
 	u32 reg;
 	reg = ((Xil_In32(XPAR_CSU_BASEADDR + XPAR_CSU_VER_OFFSET) >> 12U )& XPLAT_INFO_MASK);
 	return reg;
+#endif
 }
 #endif
 
 /*****************************************************************************/
 /**
 *
-* This API is used to provide information about PS Silicon version
+* @brief    This API is used to provide information about PS Silicon version
 *
 * @param    None.
 *
 * @return   The information about PS Silicon version.
 *
-* @note     None.
-*
 ******************************************************************************/
-#if defined (ARMR5) || (__aarch64__) || (ARMA53_32)
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) || (PSU_PMU)
 u32 XGetPSVersion_Info()
 {
+#if EL1_NONSECURE
+        /*
+         * This SMC call will return,
+         *  idcode - upper 32 bits of reg.Arg0
+         *  version - lower 32 bits of reg.Arg1
+         */
+        XSmc_OutVar reg;
+        reg = Xil_Smc(GET_CHIPID_SMC_FID,0,0, 0, 0, 0, 0, 0);
+        return (u32)(reg.Arg1 &  XPS_VERSION_INFO_MASK);
+#else
 	u32 reg;
 	reg = (Xil_In32(XPAR_CSU_BASEADDR + XPAR_CSU_VER_OFFSET)
 			& XPS_VERSION_INFO_MASK);
 	return reg;
+#endif
 }
 #endif
diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xplatform_info.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xplatform_info.h
similarity index 80%
rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xplatform_info.h
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xplatform_info.h
index 7028a83af..0582222bc 100644
--- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/standalone_v6_1/src/xplatform_info.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xplatform_info.h
@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2014 - 2015 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2014 - 2017 Xilinx, Inc.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
@@ -34,7 +34,21 @@
 *
 * @file xplatform_info.h
 *
-* This file contains definitions for various platforms available
+* @addtogroup common_platform_info APIs to Get Platform Information
+*
+* The xplatform_info.h file contains definitions for various available Xilinx®
+* platforms. Also, it contains prototype of APIs, which can be used to get the
+* platform information.
+*
+* @{
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date    Changes
+* ----- ---- --------- -------------------------------------------------------
+* 6.4    ms   05/23/17 Added PSU_PMU macro to support XGetPSVersion_Info
+*                      function for PMUFW.
+* 

 *
 ******************************************************************************/
 
@@ -65,6 +79,7 @@ extern "C" {
 #define XPS_VERSION_2 0x1
 
 #define XPLAT_INFO_MASK (0xF)
+#define XPLAT_INFO_SHIFT (0xC)
 #define XPS_VERSION_INFO_MASK (0xF)
 
 /**************************** Type Definitions *******************************/
@@ -74,7 +89,7 @@ extern "C" {
 
 u32 XGetPlatform_Info();
 
-#if defined (ARMR5) || (__aarch64__) || (ARMA53_32)
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32) || (PSU_PMU)
 u32 XGetPSVersion_Info();
 #endif
 
@@ -89,3 +104,6 @@ u32 XGet_Zynq_UltraMp_Platform_info();
 #endif
 
 #endif /* end of protection macro */
+/**
+* @} End of "addtogroup common_platform_info".
+*/
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xpm_counter.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xpm_counter.c
similarity index 87%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xpm_counter.c
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xpm_counter.c
index 0851408cc..e5b231e25 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xpm_counter.c
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xpm_counter.c
@@ -44,6 +44,7 @@
 * Ver   Who  Date     Changes
 * ----- ---- -------- -----------------------------------------------
 * 5.00  pkp  02/10/14 Initial version
+* 6.2   mus  01/27/17 Updated to support IAR compiler
 *
* ******************************************************************************/ @@ -75,14 +76,12 @@ void Xpm_ResetEventCounters (void); /****************************************************************************/ /** * -* This function disables the Cortex R5 event counters. +* @brief This function disables the Cortex R5 event counters. * * @param None. * * @return None. * -* @note None. -* *****************************************************************************/ void Xpm_DisableEventCounters(void) { @@ -93,14 +92,12 @@ void Xpm_DisableEventCounters(void) /****************************************************************************/ /** * -* This function enables the Cortex R5 event counters. +* @brief This function enables the Cortex R5 event counters. * * @param None. * * @return None. * -* @note None. -* *****************************************************************************/ void Xpm_EnableEventCounters(void) { @@ -111,14 +108,12 @@ void Xpm_EnableEventCounters(void) /****************************************************************************/ /** * -* This function resets the Cortex R5 event counters. +* @brief This function resets the Cortex R5 event counters. * * @param None. * * @return None. * -* @note None. -* *****************************************************************************/ void Xpm_ResetEventCounters(void) { @@ -126,6 +121,8 @@ void Xpm_ResetEventCounters(void) #ifdef __GNUC__ Reg = mfcp(XREG_CP15_PERF_MONITOR_CTRL); +#elif defined (__ICCARM__) + mfcp(XREG_CP15_PERF_MONITOR_CTRL, Reg); #else { register u32 C15Reg __asm(XREG_CP15_PERF_MONITOR_CTRL); Reg = C15Reg; } @@ -137,17 +134,16 @@ void Xpm_ResetEventCounters(void) /****************************************************************************/ /** * -* This function configures the Cortex R5 event counters controller, with the -* event codes, in a configuration selected by the user and enables the counters. +* @brief This function configures the Cortex R5 event counters controller, +* with the event codes, in a configuration selected by the user and +* enables the counters. * -* @param PmcrCfg is configuration value based on which the event counters -* are configured. -* Use XPM_CNTRCFG* values defined in xpm_counter.h. +* @param PmcrCfg: Configuration value based on which the event counters +* are configured.XPM_CNTRCFG* values defined in xpm_counter.h can +* be utilized for setting configuration * * @return None. * -* @note None. -* *****************************************************************************/ void Xpm_SetEvents(s32 PmcrCfg) { @@ -262,16 +258,15 @@ void Xpm_SetEvents(s32 PmcrCfg) /****************************************************************************/ /** * -* This function disables the event counters and returns the counter values. +* @brief This function disables the event counters and returns the counter +* values. * -* @param PmCtrValue is a pointer to an array of type u32 PmCtrValue[6]. -* It is an output parameter which is used to return the PM -* counter values. +* @param PmCtrValue: Pointer to an array of type u32 PmCtrValue[6]. +* It is an output parameter which is used to return the PM +* counter values. * * @return None. * -* @note None. -* *****************************************************************************/ void Xpm_GetEventCounters(u32 *PmCtrValue) { @@ -284,6 +279,8 @@ void Xpm_GetEventCounters(u32 *PmCtrValue) mtcp(XREG_CP15_EVENT_CNTR_SEL, Counter); #ifdef __GNUC__ PmCtrValue[Counter] = mfcp(XREG_CP15_PERF_MONITOR_COUNT); +#elif defined (__ICCARM__) + mfcp(XREG_CP15_PERF_MONITOR_COUNT, PmCtrValue[Counter]); #else { register u32 Cp15Reg __asm(XREG_CP15_PERF_MONITOR_COUNT); PmCtrValue[Counter] = Cp15Reg; } diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xpm_counter.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xpm_counter.h similarity index 97% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xpm_counter.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xpm_counter.h index 5679d4bb5..b24f4ae40 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xpm_counter.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xpm_counter.h @@ -34,21 +34,20 @@ * * @file xpm_counter.h * -* This header file contains APIs for configuring and controlling the Cortex-R5 -* Performance Monitor Events. -* Cortex-R5 Performance Monitor has 6 event counters which can be used to -* count a variety of events described in Coretx-R5 TRM. This file defines -* configurations, where value configures the event counters to count a -* set of events. +* @addtogroup r5_event_counter_apis Cortex R5 Event Counters Functions * -* Xpm_SetEvents can be used to set the event counters to count a set of events -* and Xpm_GetEventCounters can be used to read the counter values. +* Cortex R5 event counter functions can be utilized to configure and control +* the Cortex-R5 performance monitor events. +* Cortex-R5 Performance Monitor has 6 event counters which can be used to +* count a variety of events described in Coretx-R5 TRM. The xpm_counter.h file +* defines configurations XPM_CNTRCFGx which can be used to program the event +* counters to count a set of events. * * @note -* -* This file doesn't handle the Cortex-R5 cycle counter, as the cycle counter is +* It doesn't handle the Cortex-R5 cycle counter, as the cycle counter is * being used for time keeping. * +* @{ * 
 * MODIFICATION HISTORY:
 *
@@ -569,3 +568,6 @@ void Xpm_GetEventCounters(u32 *PmCtrValue);
 #endif
 
 #endif
+/**
+* @} End of "addtogroup r5_event_counter_apis".
+*/
\ No newline at end of file
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xpseudo_asm.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xpseudo_asm.h
similarity index 71%
rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xpseudo_asm.h
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xpseudo_asm.h
index aff19d5a9..4d587af3a 100644
--- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xpseudo_asm.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xpseudo_asm.h
@@ -34,14 +34,28 @@
 *
 * @file xpseudo_asm.h
 *
-* This header file contains macros for using inline assembler code.
+* @addtogroup r5_specific Cortex R5 Processor Specific Include Files
 *
+* The xpseudo_asm.h includes xreg_cortexr5.h and xpseudo_asm_gcc.h.
+*
+* The xreg_cortexr5.h file contains definitions for inline assembler code.
+* It provides inline definitions for Cortex R5 GPRs, SPRs,co-processor
+* registers and Debug register
+*
+* The xpseudo_asm_gcc.h contains the definitions for the most often used
+* inline assembler instructions, available as macros. These can be very
+* useful for tasks such as setting or getting special purpose registers,
+* synchronization,or cache manipulation. These inline assembler instructions
+* can be used from drivers and user applications written in C.
+*
+* @{
 * 
 * MODIFICATION HISTORY:
 *
 * Ver   Who  Date     Changes
 * ----- ---- -------- -----------------------------------------------
 * 5.00  pkp  02/10/14 Initial version
+* 6.2   mus  01/27/17 Updated to support IAR compiler
 * 

 *
 ******************************************************************************/
@@ -49,6 +63,12 @@
 #define XPSEUDO_ASM_H /* by using protection macros */
 
 #include "xreg_cortexr5.h"
+#if defined (__GNUC__)
 #include "xpseudo_asm_gcc.h"
-
+#elif defined (__ICCARM__)
+#include "xpseudo_asm_iccarm.h"
+#endif
 #endif /* XPSEUDO_ASM_H */
+/**
+* @} End of "addtogroup r5_specific".
+*/
\ No newline at end of file
diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xpseudo_asm_gcc.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xpseudo_asm_gcc.h
similarity index 70%
rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xpseudo_asm_gcc.h
rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xpseudo_asm_gcc.h
index 9b34a008e..1b6726394 100644
--- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/standalone_v5_4/src/xpseudo_asm_gcc.h
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xpseudo_asm_gcc.h
@@ -1,6 +1,6 @@
 /******************************************************************************
 *
-* Copyright (C) 2009 - 2015 Xilinx, Inc.  All rights reserved.
+* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
@@ -42,7 +42,8 @@
 *
 * Ver   Who      Date     Changes
 * ----- -------- -------- -----------------------------------------------
-* 1.00a ecm/sdm  10/28/09 First release
+* 5.00 	pkp		 05/21/14 First release
+* 6.0   mus      07/27/16 Consolidated file for a53,a9 and r5 processors
 *
* ******************************************************************************/ @@ -53,6 +54,7 @@ /***************************** Include Files ********************************/ #include "xil_types.h" + #ifdef __cplusplus extern "C" { #endif /* __cplusplus */ @@ -67,8 +69,61 @@ extern "C" { #define stringify(s) tostring(s) #define tostring(s) #s +#if defined (__aarch64__) /* pseudo assembler instructions */ -#define mfcpsr() ({u32 rval; \ +#define mfcpsr() ({u32 rval = 0U; \ + asm volatile("mrs %0, DAIF" : "=r" (rval));\ + rval;\ + }) + +#define mtcpsr(v) __asm__ __volatile__ ("msr DAIF, %0" : : "r" (v)) + +#define cpsiei() //__asm__ __volatile__("cpsie i\n") +#define cpsidi() //__asm__ __volatile__("cpsid i\n") + +#define cpsief() //__asm__ __volatile__("cpsie f\n") +#define cpsidf() //__asm__ __volatile__("cpsid f\n") + + + +#define mtgpr(rn, v) /*__asm__ __volatile__(\ + "mov r" stringify(rn) ", %0 \n"\ + : : "r" (v)\ + )*/ + +#define mfgpr(rn) /*({u32 rval; \ + __asm__ __volatile__(\ + "mov %0,r" stringify(rn) "\n"\ + : "=r" (rval)\ + );\ + rval;\ + })*/ + +/* memory synchronization operations */ + +/* Instruction Synchronization Barrier */ +#define isb() __asm__ __volatile__ ("isb sy") + +/* Data Synchronization Barrier */ +#define dsb() __asm__ __volatile__("dsb sy") + +/* Data Memory Barrier */ +#define dmb() __asm__ __volatile__("dmb sy") + + +/* Memory Operations */ +#define ldr(adr) ({u64 rval; \ + __asm__ __volatile__(\ + "ldr %0,[%1]"\ + : "=r" (rval) : "r" (adr)\ + );\ + rval;\ + }) + +#else + +/* pseudo assembler instructions */ +#define mfcpsr() ({u32 rval = 0U; \ __asm__ __volatile__(\ "mrs %0, cpsr\n"\ : "=r" (rval)\ @@ -123,6 +178,8 @@ extern "C" { rval;\ }) +#endif + #define ldrb(adr) ({u8 rval; \ __asm__ __volatile__(\ "ldrb %0,[%1]"\ @@ -150,19 +207,36 @@ extern "C" { rval;\ }) +#if defined (__aarch64__) +#define mtcpdc(reg,val) __asm__ __volatile__("dc " #reg ",%0" : : "r" (val)) +#define mtcpic(reg,val) __asm__ __volatile__("ic " #reg ",%0" : : "r" (val)) + +#define mtcpicall(reg) __asm__ __volatile__("ic " #reg) +#define mtcptlbi(reg) __asm__ __volatile__("tlbi " #reg) +#define mtcpat(reg,val) __asm__ __volatile__("at " #reg ",%0" : : "r" (val)) +/* CP15 operations */ +#define mfcp(reg) ({u64 rval = 0U;\ + __asm__ __volatile__("mrs %0, " #reg : "=r" (rval));\ + rval;\ + }) + +#define mtcp(reg,val) __asm__ __volatile__("msr " #reg ",%0" : : "r" (val)) + +#else /* CP15 operations */ #define mtcp(rn, v) __asm__ __volatile__(\ "mcr " rn "\n"\ : : "r" (v)\ ); -#define mfcp(rn) ({u32 rval; \ +#define mfcp(rn) ({u32 rval = 0U; \ __asm__ __volatile__(\ "mrc " rn "\n"\ : "=r" (rval)\ );\ rval;\ }) +#endif /************************** Variable Definitions ****************************/ diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xreg_cortexr5.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xreg_cortexr5.h similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xreg_cortexr5.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xreg_cortexr5.h diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xstatus.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xstatus.h new file mode 100644 index 000000000..993747588 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xstatus.h @@ -0,0 +1,535 @@ +/****************************************************************************** +* +* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xstatus.h +* +* @addtogroup common_status_codes Xilinx® software status codes +* +* The xstatus.h file contains the Xilinx® software status codes.These codes are +* used throughout the Xilinx device drivers. +* +* @{ +******************************************************************************/ + +#ifndef XSTATUS_H /* prevent circular inclusions */ +#define XSTATUS_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" + +/************************** Constant Definitions *****************************/ + +/*********************** Common statuses 0 - 500 *****************************/ +/** +@name Common Status Codes for All Device Drivers +@{ +*/ +#define XST_SUCCESS 0L +#define XST_FAILURE 1L +#define XST_DEVICE_NOT_FOUND 2L +#define XST_DEVICE_BLOCK_NOT_FOUND 3L +#define XST_INVALID_VERSION 4L +#define XST_DEVICE_IS_STARTED 5L +#define XST_DEVICE_IS_STOPPED 6L +#define XST_FIFO_ERROR 7L /*!< An error occurred during an + operation with a FIFO such as + an underrun or overrun, this + error requires the device to + be reset */ +#define XST_RESET_ERROR 8L /*!< An error occurred which requires + the device to be reset */ +#define XST_DMA_ERROR 9L /*!< A DMA error occurred, this error + typically requires the device + using the DMA to be reset */ +#define XST_NOT_POLLED 10L /*!< The device is not configured for + polled mode operation */ +#define XST_FIFO_NO_ROOM 11L /*!< A FIFO did not have room to put + the specified data into */ +#define XST_BUFFER_TOO_SMALL 12L /*!< The buffer is not large enough + to hold the expected data */ +#define XST_NO_DATA 13L /*!< There was no data available */ +#define XST_REGISTER_ERROR 14L /*!< A register did not contain the + expected value */ +#define XST_INVALID_PARAM 15L /*!< An invalid parameter was passed + into the function */ +#define XST_NOT_SGDMA 16L /*!< The device is not configured for + scatter-gather DMA operation */ +#define XST_LOOPBACK_ERROR 17L /*!< A loopback test failed */ +#define XST_NO_CALLBACK 18L /*!< A callback has not yet been + registered */ +#define XST_NO_FEATURE 19L /*!< Device is not configured with + the requested feature */ +#define XST_NOT_INTERRUPT 20L /*!< Device is not configured for + interrupt mode operation */ +#define XST_DEVICE_BUSY 21L /*!< Device is busy */ +#define XST_ERROR_COUNT_MAX 22L /*!< The error counters of a device + have maxed out */ +#define XST_IS_STARTED 23L /*!< Used when part of device is + already started i.e. + sub channel */ +#define XST_IS_STOPPED 24L /*!< Used when part of device is + already stopped i.e. + sub channel */ +#define XST_DATA_LOST 26L /*!< Driver defined error */ +#define XST_RECV_ERROR 27L /*!< Generic receive error */ +#define XST_SEND_ERROR 28L /*!< Generic transmit error */ +#define XST_NOT_ENABLED 29L /*!< A requested service is not + available because it has not + been enabled */ +/** @} */ +/***************** Utility Component statuses 401 - 500 *********************/ +/** +@name Utility Component Status Codes 401 - 500 +@{ +*/ +#define XST_MEMTEST_FAILED 401L /*!< Memory test failed */ + +/** @} */ +/***************** Common Components statuses 501 - 1000 *********************/ +/** +@name Packet Fifo Status Codes 501 - 510 +@{ +*/ +/********************* Packet Fifo statuses 501 - 510 ************************/ + +#define XST_PFIFO_LACK_OF_DATA 501L /*!< Not enough data in FIFO */ +#define XST_PFIFO_NO_ROOM 502L /*!< Not enough room in FIFO */ +#define XST_PFIFO_BAD_REG_VALUE 503L /*!< Self test, a register value + was invalid after reset */ +#define XST_PFIFO_ERROR 504L /*!< Generic packet FIFO error */ +#define XST_PFIFO_DEADLOCK 505L /*!< Packet FIFO is reporting + * empty and full simultaneously + */ +/** @} */ +/** +@name DMA Status Codes 511 - 530 +@{ +*/ +/************************** DMA statuses 511 - 530 ***************************/ + +#define XST_DMA_TRANSFER_ERROR 511L /*!< Self test, DMA transfer + failed */ +#define XST_DMA_RESET_REGISTER_ERROR 512L /*!< Self test, a register value + was invalid after reset */ +#define XST_DMA_SG_LIST_EMPTY 513L /*!< Scatter gather list contains + no buffer descriptors ready + to be processed */ +#define XST_DMA_SG_IS_STARTED 514L /*!< Scatter gather not stopped */ +#define XST_DMA_SG_IS_STOPPED 515L /*!< Scatter gather not running */ +#define XST_DMA_SG_LIST_FULL 517L /*!< All the buffer desciptors of + the scatter gather list are + being used */ +#define XST_DMA_SG_BD_LOCKED 518L /*!< The scatter gather buffer + descriptor which is to be + copied over in the scatter + list is locked */ +#define XST_DMA_SG_NOTHING_TO_COMMIT 519L /*!< No buffer descriptors have been + put into the scatter gather + list to be commited */ +#define XST_DMA_SG_COUNT_EXCEEDED 521L /*!< The packet count threshold + specified was larger than the + total # of buffer descriptors + in the scatter gather list */ +#define XST_DMA_SG_LIST_EXISTS 522L /*!< The scatter gather list has + already been created */ +#define XST_DMA_SG_NO_LIST 523L /*!< No scatter gather list has + been created */ +#define XST_DMA_SG_BD_NOT_COMMITTED 524L /*!< The buffer descriptor which was + being started was not committed + to the list */ +#define XST_DMA_SG_NO_DATA 525L /*!< The buffer descriptor to start + has already been used by the + hardware so it can't be reused + */ +#define XST_DMA_SG_LIST_ERROR 526L /*!< General purpose list access + error */ +#define XST_DMA_BD_ERROR 527L /*!< General buffer descriptor + error */ +/** @} */ +/** +@name IPIF Status Codes Codes 531 - 550 +@{ +*/ +/************************** IPIF statuses 531 - 550 ***************************/ + +#define XST_IPIF_REG_WIDTH_ERROR 531L /*!< An invalid register width + was passed into the function */ +#define XST_IPIF_RESET_REGISTER_ERROR 532L /*!< The value of a register at + reset was not valid */ +#define XST_IPIF_DEVICE_STATUS_ERROR 533L /*!< A write to the device interrupt + status register did not read + back correctly */ +#define XST_IPIF_DEVICE_ACK_ERROR 534L /*!< The device interrupt status + register did not reset when + acked */ +#define XST_IPIF_DEVICE_ENABLE_ERROR 535L /*!< The device interrupt enable + register was not updated when + other registers changed */ +#define XST_IPIF_IP_STATUS_ERROR 536L /*!< A write to the IP interrupt + status register did not read + back correctly */ +#define XST_IPIF_IP_ACK_ERROR 537L /*!< The IP interrupt status register + did not reset when acked */ +#define XST_IPIF_IP_ENABLE_ERROR 538L /*!< IP interrupt enable register was + not updated correctly when other + registers changed */ +#define XST_IPIF_DEVICE_PENDING_ERROR 539L /*!< The device interrupt pending + register did not indicate the + expected value */ +#define XST_IPIF_DEVICE_ID_ERROR 540L /*!< The device interrupt ID register + did not indicate the expected + value */ +#define XST_IPIF_ERROR 541L /*!< Generic ipif error */ +/** @} */ + +/****************** Device specific statuses 1001 - 4095 *********************/ +/** +@name Ethernet Status Codes 1001 - 1050 +@{ +*/ +/********************* Ethernet statuses 1001 - 1050 *************************/ + +#define XST_EMAC_MEMORY_SIZE_ERROR 1001L /*!< Memory space is not big enough + * to hold the minimum number of + * buffers or descriptors */ +#define XST_EMAC_MEMORY_ALLOC_ERROR 1002L /*!< Memory allocation failed */ +#define XST_EMAC_MII_READ_ERROR 1003L /*!< MII read error */ +#define XST_EMAC_MII_BUSY 1004L /*!< An MII operation is in progress */ +#define XST_EMAC_OUT_OF_BUFFERS 1005L /*!< Driver is out of buffers */ +#define XST_EMAC_PARSE_ERROR 1006L /*!< Invalid driver init string */ +#define XST_EMAC_COLLISION_ERROR 1007L /*!< Excess deferral or late + * collision on polled send */ +/** @} */ +/** +@name UART Status Codes 1051 - 1075 +@{ +*/ +/*********************** UART statuses 1051 - 1075 ***************************/ +#define XST_UART + +#define XST_UART_INIT_ERROR 1051L +#define XST_UART_START_ERROR 1052L +#define XST_UART_CONFIG_ERROR 1053L +#define XST_UART_TEST_FAIL 1054L +#define XST_UART_BAUD_ERROR 1055L +#define XST_UART_BAUD_RANGE 1056L + +/** @} */ +/** +@name IIC Status Codes 1076 - 1100 +@{ +*/ +/************************ IIC statuses 1076 - 1100 ***************************/ + +#define XST_IIC_SELFTEST_FAILED 1076 /*!< self test failed */ +#define XST_IIC_BUS_BUSY 1077 /*!< bus found busy */ +#define XST_IIC_GENERAL_CALL_ADDRESS 1078 /*!< mastersend attempted with */ + /* general call address */ +#define XST_IIC_STAND_REG_RESET_ERROR 1079 /*!< A non parameterizable reg */ + /* value after reset not valid */ +#define XST_IIC_TX_FIFO_REG_RESET_ERROR 1080 /*!< Tx fifo included in design */ + /* value after reset not valid */ +#define XST_IIC_RX_FIFO_REG_RESET_ERROR 1081 /*!< Rx fifo included in design */ + /* value after reset not valid */ +#define XST_IIC_TBA_REG_RESET_ERROR 1082 /*!< 10 bit addr incl in design */ + /* value after reset not valid */ +#define XST_IIC_CR_READBACK_ERROR 1083 /*!< Read of the control register */ + /* didn't return value written */ +#define XST_IIC_DTR_READBACK_ERROR 1084 /*!< Read of the data Tx reg */ + /* didn't return value written */ +#define XST_IIC_DRR_READBACK_ERROR 1085 /*!< Read of the data Receive reg */ + /* didn't return value written */ +#define XST_IIC_ADR_READBACK_ERROR 1086 /*!< Read of the data Tx reg */ + /* didn't return value written */ +#define XST_IIC_TBA_READBACK_ERROR 1087 /*!< Read of the 10 bit addr reg */ + /* didn't return written value */ +#define XST_IIC_NOT_SLAVE 1088 /*!< The device isn't a slave */ +/** @} */ +/** +@name ATMC Status Codes 1101 - 1125 +@{ +*/ +/*********************** ATMC statuses 1101 - 1125 ***************************/ + +#define XST_ATMC_ERROR_COUNT_MAX 1101L /*!< the error counters in the ATM + controller hit the max value + which requires the statistics + to be cleared */ +/** @} */ +/** +@name Flash Status Codes 1126 - 1150 +@{ +*/ +/*********************** Flash statuses 1126 - 1150 **************************/ + +#define XST_FLASH_BUSY 1126L /*!< Flash is erasing or programming + */ +#define XST_FLASH_READY 1127L /*!< Flash is ready for commands */ +#define XST_FLASH_ERROR 1128L /*!< Flash had detected an internal + error. Use XFlash_DeviceControl + to retrieve device specific codes + */ +#define XST_FLASH_ERASE_SUSPENDED 1129L /*!< Flash is in suspended erase state + */ +#define XST_FLASH_WRITE_SUSPENDED 1130L /*!< Flash is in suspended write state + */ +#define XST_FLASH_PART_NOT_SUPPORTED 1131L /*!< Flash type not supported by + driver */ +#define XST_FLASH_NOT_SUPPORTED 1132L /*!< Operation not supported */ +#define XST_FLASH_TOO_MANY_REGIONS 1133L /*!< Too many erase regions */ +#define XST_FLASH_TIMEOUT_ERROR 1134L /*!< Programming or erase operation + aborted due to a timeout */ +#define XST_FLASH_ADDRESS_ERROR 1135L /*!< Accessed flash outside its + addressible range */ +#define XST_FLASH_ALIGNMENT_ERROR 1136L /*!< Write alignment error */ +#define XST_FLASH_BLOCKING_CALL_ERROR 1137L /*!< Couldn't return immediately from + write/erase function with + XFL_NON_BLOCKING_WRITE/ERASE + option cleared */ +#define XST_FLASH_CFI_QUERY_ERROR 1138L /*!< Failed to query the device */ +/** @} */ +/** +@name SPI Status Codes 1151 - 1175 +@{ +*/ +/*********************** SPI statuses 1151 - 1175 ****************************/ + +#define XST_SPI_MODE_FAULT 1151 /*!< master was selected as slave */ +#define XST_SPI_TRANSFER_DONE 1152 /*!< data transfer is complete */ +#define XST_SPI_TRANSMIT_UNDERRUN 1153 /*!< slave underruns transmit register */ +#define XST_SPI_RECEIVE_OVERRUN 1154 /*!< device overruns receive register */ +#define XST_SPI_NO_SLAVE 1155 /*!< no slave has been selected yet */ +#define XST_SPI_TOO_MANY_SLAVES 1156 /*!< more than one slave is being + * selected */ +#define XST_SPI_NOT_MASTER 1157 /*!< operation is valid only as master */ +#define XST_SPI_SLAVE_ONLY 1158 /*!< device is configured as slave-only + */ +#define XST_SPI_SLAVE_MODE_FAULT 1159 /*!< slave was selected while disabled */ +#define XST_SPI_SLAVE_MODE 1160 /*!< device has been addressed as slave */ +#define XST_SPI_RECEIVE_NOT_EMPTY 1161 /*!< device received data in slave mode */ + +#define XST_SPI_COMMAND_ERROR 1162 /*!< unrecognised command - qspi only */ +#define XST_SPI_POLL_DONE 1163 /*!< controller completed polling the + device for status */ +/** @} */ +/** +@name OPB Arbiter Status Codes 1176 - 1200 +@{ +*/ +/********************** OPB Arbiter statuses 1176 - 1200 *********************/ + +#define XST_OPBARB_INVALID_PRIORITY 1176 /*!< the priority registers have either + * one master assigned to two or more + * priorities, or one master not + * assigned to any priority + */ +#define XST_OPBARB_NOT_SUSPENDED 1177 /*!< an attempt was made to modify the + * priority levels without first + * suspending the use of priority + * levels + */ +#define XST_OPBARB_PARK_NOT_ENABLED 1178 /*!< bus parking by id was enabled but + * bus parking was not enabled + */ +#define XST_OPBARB_NOT_FIXED_PRIORITY 1179 /*!< the arbiter must be in fixed + * priority mode to allow the + * priorities to be changed + */ +/** @} */ +/** +@name INTC Status Codes 1201 - 1225 +@{ +*/ +/************************ Intc statuses 1201 - 1225 **************************/ + +#define XST_INTC_FAIL_SELFTEST 1201 /*!< self test failed */ +#define XST_INTC_CONNECT_ERROR 1202 /*!< interrupt already in use */ +/** @} */ +/** +@name TmrCtr Status Codes 1226 - 1250 +@{ +*/ +/********************** TmrCtr statuses 1226 - 1250 **************************/ + +#define XST_TMRCTR_TIMER_FAILED 1226 /*!< self test failed */ +/** @} */ +/** +@name WdtTb Status Codes 1251 - 1275 +@{ +*/ +/********************** WdtTb statuses 1251 - 1275 ***************************/ + +#define XST_WDTTB_TIMER_FAILED 1251L +/** @} */ +/** +@name PlbArb status Codes 1276 - 1300 +@{ +*/ +/********************** PlbArb statuses 1276 - 1300 **************************/ + +#define XST_PLBARB_FAIL_SELFTEST 1276L +/** @} */ +/** +@name Plb2Opb Status Codes 1301 - 1325 +@{ +*/ +/********************** Plb2Opb statuses 1301 - 1325 *************************/ + +#define XST_PLB2OPB_FAIL_SELFTEST 1301L +/** @} */ +/** +@name Opb2Plb Status 1326 - 1350 +@{ +*/ +/********************** Opb2Plb statuses 1326 - 1350 *************************/ + +#define XST_OPB2PLB_FAIL_SELFTEST 1326L +/** @} */ +/** +@name SysAce Status Codes 1351 - 1360 +@{ +*/ +/********************** SysAce statuses 1351 - 1360 **************************/ + +#define XST_SYSACE_NO_LOCK 1351L /*!< No MPU lock has been granted */ +/** @} */ +/** +@name PCI Bridge Status Codes 1361 - 1375 +@{ +*/ +/********************** PCI Bridge statuses 1361 - 1375 **********************/ + +#define XST_PCI_INVALID_ADDRESS 1361L +/** @} */ +/** +@name FlexRay Constants 1400 - 1409 +@{ +*/ +/********************** FlexRay constants 1400 - 1409 *************************/ + +#define XST_FR_TX_ERROR 1400 +#define XST_FR_TX_BUSY 1401 +#define XST_FR_BUF_LOCKED 1402 +#define XST_FR_NO_BUF 1403 +/** @} */ +/** +@name USB constants 1410 - 1420 +@{ +*/ +/****************** USB constants 1410 - 1420 *******************************/ + +#define XST_USB_ALREADY_CONFIGURED 1410 +#define XST_USB_BUF_ALIGN_ERROR 1411 +#define XST_USB_NO_DESC_AVAILABLE 1412 +#define XST_USB_BUF_TOO_BIG 1413 +#define XST_USB_NO_BUF 1414 +/** @} */ +/** +@name HWICAP constants 1421 - 1429 +@{ +*/ +/****************** HWICAP constants 1421 - 1429 *****************************/ + +#define XST_HWICAP_WRITE_DONE 1421 + +/** @} */ +/** +@name AXI VDMA constants 1430 - 1440 +@{ +*/ +/****************** AXI VDMA constants 1430 - 1440 *****************************/ + +#define XST_VDMA_MISMATCH_ERROR 1430 +/** @} */ +/** +@name NAND Flash Status Codes 1441 - 1459 +@{ +*/ +/*********************** NAND Flash statuses 1441 - 1459 *********************/ + +#define XST_NAND_BUSY 1441L /*!< Flash is erasing or + * programming + */ +#define XST_NAND_READY 1442L /*!< Flash is ready for commands + */ +#define XST_NAND_ERROR 1443L /*!< Flash had detected an + * internal error. + */ +#define XST_NAND_PART_NOT_SUPPORTED 1444L /*!< Flash type not supported by + * driver + */ +#define XST_NAND_OPT_NOT_SUPPORTED 1445L /*!< Operation not supported + */ +#define XST_NAND_TIMEOUT_ERROR 1446L /*!< Programming or erase + * operation aborted due to a + * timeout + */ +#define XST_NAND_ADDRESS_ERROR 1447L /*!< Accessed flash outside its + * addressible range + */ +#define XST_NAND_ALIGNMENT_ERROR 1448L /*!< Write alignment error + */ +#define XST_NAND_PARAM_PAGE_ERROR 1449L /*!< Failed to read parameter + * page of the device + */ +#define XST_NAND_CACHE_ERROR 1450L /*!< Flash page buffer error + */ + +#define XST_NAND_WRITE_PROTECTED 1451L /*!< Flash is write protected + */ +/** @} */ + +/**************************** Type Definitions *******************************/ + +typedef s32 XStatus; + +/***************** Macros (Inline Functions) Definitions *********************/ + + +/************************** Function Prototypes ******************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** +* @} End of "addtogroup common_status_codes". +*/ diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xtime_l.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xtime_l.c similarity index 63% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xtime_l.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xtime_l.c index a9db4df7f..2eeb4128b 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xtime_l.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xtime_l.c @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved. +* Copyright (C) 2014 - 2017 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -54,6 +54,8 @@ * 5.04 pkp * 6.0 mus 08/11/16 Removed implementation of XTime_SetTime API, since * TTC counter value register is read only. +* 6.6 srm 10/18/17 Removed XTime_StartTimer API and made XTime_GetTime, +* XTime_SetTime applicable for all the instances of TTC * * * @@ -68,109 +70,59 @@ #include "xil_io.h" #include "xdebug.h" +#if defined SLEEP_TIMER_BASEADDR +#include "xil_sleeptimer.h" +#endif + /***************** Macros (Inline Functions) Definitions *********************/ /**************************** Type Definitions *******************************/ /************************** Constant Definitions *****************************/ -#define RST_LPD_IOU2 0xFF5E0238U -#define RST_LPD_IOU2_TTC3_RESET_MASK 0x00004000U + /************************** Variable Definitions *****************************/ /************************** Function Prototypes ******************************/ -/* Function definitions are applicable only when TTC3 is present*/ +/* Function definitions are applicable only when TTC is present*/ #ifdef SLEEP_TIMER_BASEADDR -/**************************************************************************** + +/****************************************************************************/ +/** +* @brief TTC Timer runs continuously and the time can not be set as +* desired. This API doesn't contain anything. It is defined to have +* uniformity across platforms. * -* Start the TTC timer. -* -* @param None. +* @param Xtime_Global: 32 bit value to be written to the timer counter +* register. * * @return None. * * @note In multiprocessor environment reference time will reset/lost for -* all processors, when this function called by any one processor. -* -****************************************************************************/ -void XTime_StartTimer(void) -{ - u32 LpdRst; - u32 TimerPrescalar; - u32 TimerCntrl; - - LpdRst = Xil_In32(RST_LPD_IOU2); - if ((LpdRst & RST_LPD_IOU2_TTC3_RESET_MASK) != 0 ) { - LpdRst = LpdRst & (~RST_LPD_IOU2_TTC3_RESET_MASK); - Xil_Out32(RST_LPD_IOU2, LpdRst); - - } else { - TimerCntrl = Xil_In32(SLEEP_TIMER_BASEADDR + - SLEEP_TIMER_CNTR_CNTRL_OFFSET); - /* check if Timer is disabled */ - if ((TimerCntrl & SLEEP_TIMER_COUNTER_CONTROL_DIS_MASK) == 0) { - TimerPrescalar = Xil_In32(SLEEP_TIMER_BASEADDR + - SLEEP_TIMER_CLK_CNTRL_OFFSET); - - /* check if Timer is configured with proper functionalty for sleep */ - if ((TimerPrescalar & SLEEP_TIMER_CLOCK_CONTROL_PS_EN_MASK) == 0) - return; - } - } - /* Disable the timer to configure */ - TimerCntrl = Xil_In32(SLEEP_TIMER_BASEADDR + - SLEEP_TIMER_CNTR_CNTRL_OFFSET); - TimerCntrl = TimerCntrl | SLEEP_TIMER_COUNTER_CONTROL_DIS_MASK; - Xil_Out32(SLEEP_TIMER_BASEADDR + SLEEP_TIMER_CNTR_CNTRL_OFFSET, - TimerCntrl); - - /* Disable the prescalar */ - TimerPrescalar = Xil_In32(SLEEP_TIMER_BASEADDR + - SLEEP_TIMER_CLK_CNTRL_OFFSET); - TimerPrescalar = TimerPrescalar & (~SLEEP_TIMER_CLOCK_CONTROL_PS_EN_MASK); - Xil_Out32(SLEEP_TIMER_BASEADDR + SLEEP_TIMER_CLK_CNTRL_OFFSET, - TimerPrescalar); - - /* Enable the Timer */ - TimerCntrl = SLEEP_TIMER_COUNTER_CONTROL_RST_MASK & - (~SLEEP_TIMER_COUNTER_CONTROL_DIS_MASK); - Xil_Out32(SLEEP_TIMER_BASEADDR + SLEEP_TIMER_CNTR_CNTRL_OFFSET, - TimerCntrl); - -} -/**************************************************************************** -* -* Set the time in the Timer Counter Register. -* -* @param Value to be written to the Timer Counter Register. -* -* @return None. -* -* @note In multiprocessor environment reference time will reset/lost for -* all processors, when this function called by any one processor. +* all processors, when this function called by any one processor. * ****************************************************************************/ void XTime_SetTime(XTime Xtime_Global) { + (void) Xtime_Global; /*Timer cannot be set to desired value, so the API is left unimplemented*/ xdbg_printf(XDBG_DEBUG_GENERAL, "XTime_SetTime:Timer cannot be set to desired value,so API is not implemented\n"); } -/**************************************************************************** +/****************************************************************************/ +/** +* @brief Get the time from the timer counter register. * -* Get the time from the Timer Counter Register. -* -* @param Pointer to the location to be updated with the time. +* @param Xtime_Global: Pointer to the 32 bit location to be updated with +* the time current value of timer counter register. * * @return None. * -* @note None. -* ****************************************************************************/ void XTime_GetTime(XTime *Xtime_Global) { *Xtime_Global = Xil_In32(SLEEP_TIMER_BASEADDR + - SLEEP_TIMER_CNTR_VAL_OFFSET); + XSLEEP_TIMER_TTC_COUNT_VALUE_OFFSET); } #endif diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xtime_l.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xtime_l.h similarity index 84% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xtime_l.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xtime_l.h index 36c416d5a..497466477 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_1/src/xtime_l.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v6_6/src/xtime_l.h @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved. +* Copyright (C) 2014 - 2017 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -33,6 +33,11 @@ /** * @file xtime_l.h * +* @addtogroup r5_time_apis Cortex R5 Time Functions +* The xtime_l.h provides access to 32-bit TTC timer counter. These functions +* can be used by applications to track the time. +* +* @{ * 
 * MODIFICATION HISTORY:
 *
@@ -42,10 +47,10 @@
 * 5.04  pkp	   02/19/16 Added timer configuration register offset definitions
 * 5.04	pkp	   03/11/16 Removed definitions for overflow interrupt register
 *						and mask
+* 6.6   srm    10/22/17 Added a warning message for the user configurable sleep
+*                       implementation when default timer is selected by the user
 *
* -* @note None. -* ******************************************************************************/ #ifndef XTIME_H /* prevent circular inclusions */ @@ -67,21 +72,16 @@ extern "C" { #define COUNTS_PER_SECOND SLEEP_TIMER_FREQUENCY #define COUNTS_PER_USECOND COUNTS_PER_SECOND/1000000 -/* Timer Register Offset*/ -#define SLEEP_TIMER_CLK_CNTRL_OFFSET 0x00000000U -#define SLEEP_TIMER_CNTR_CNTRL_OFFSET 0x0000000CU -#define SLEEP_TIMER_CNTR_VAL_OFFSET 0x00000018U - -/*Timer register values*/ -#define SLEEP_TIMER_COUNTER_CONTROL_DIS_MASK 0x00000001U -#define SLEEP_TIMER_CLOCK_CONTROL_PS_EN_MASK 0x00000001U -#define SLEEP_TIMER_COUNTER_CONTROL_RST_MASK 0x00000010U #else #define ITERS_PER_SEC (XPAR_CPU_CORTEXR5_0_CPU_CLK_FREQ_HZ / 4) #define ITERS_PER_USEC (XPAR_CPU_CORTEXR5_0_CPU_CLK_FREQ_HZ / 4000000) #define IRQ_FIQ_MASK 0xC0 /* Mask IRQ and FIQ interrupts in cpsr */ #endif +#if defined (XSLEEP_TIMER_IS_DEFAULT_TIMER) +#pragma message ("For the sleep routines, TTC3 is used if present else the assembly instructions are called") +#endif + /**************************** Type Definitions *******************************/ /* The following definitions are applicable only when TTC3 is present*/ @@ -97,3 +97,6 @@ void XTime_GetTime(XTime *Xtime_Global); #endif /* __cplusplus */ #endif /* XTIME_H */ +/** +* @} End of "@addtogroup r5_time_apis". +*/ diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_3/src/Makefile similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/Makefile rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_3/src/Makefile diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_3/src/xsysmonpsu.c similarity index 96% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_3/src/xsysmonpsu.c index b047a4599..4c2545c9e 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_3/src/xsysmonpsu.c @@ -18,8 +18,8 @@ * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. @@ -61,6 +61,9 @@ * XSysMonPsu_SetSeqAcqTime * and XSysMonPsu_GetSeqAcqTime to provide support for * set/get 64 bit value. +* 2.1 sk 03/03/16 Check for PL reset before doing PL Sysmon reset. +* 2.3 mn 12/13/17 Correct the AMS block channel numbers +* mn 03/08/18 Update Clock Divisor to the proper value * * * @@ -109,6 +112,7 @@ s32 XSysMonPsu_CfgInitialize(XSysMonPsu *InstancePtr, XSysMonPsu_Config *ConfigP { u32 PsSysmonControlStatus; u32 PlSysmonControlStatus; + u32 IntrStatus; /* Assert the input arguments. */ Xil_AssertNonvoid(InstancePtr != NULL); @@ -117,11 +121,14 @@ s32 XSysMonPsu_CfgInitialize(XSysMonPsu *InstancePtr, XSysMonPsu_Config *ConfigP /* Set the values read from the device config and the base address. */ InstancePtr->Config.DeviceId = ConfigPtr->DeviceId; InstancePtr->Config.BaseAddress = EffectiveAddr; - + InstancePtr->Config.InputClockMHz = ConfigPtr->InputClockMHz; /* Set all handlers to stub values, let user configure this data later. */ InstancePtr->Handler = XSysMonPsu_StubHandler; + XSysMonPsu_UpdateAdcClkDivisor(InstancePtr, XSYSMON_PS); + XSysMonPsu_UpdateAdcClkDivisor(InstancePtr, XSYSMON_PL); + /* Reset the device such that it is in a known state. */ XSysMonPsu_Reset(InstancePtr); @@ -147,6 +154,10 @@ s32 XSysMonPsu_CfgInitialize(XSysMonPsu *InstancePtr, XSysMonPsu_Config *ConfigP /* Indicate the instance is now ready to use, initialized without error */ InstancePtr->IsReady = XIL_COMPONENT_IS_READY; + /* Clear any bits set in the Interrupt Status Register. */ + IntrStatus = XSysMonPsu_IntrGetStatus(InstancePtr); + XSysMonPsu_IntrClear(InstancePtr, IntrStatus); + return XST_SUCCESS; } @@ -166,7 +177,7 @@ s32 XSysMonPsu_CfgInitialize(XSysMonPsu *InstancePtr, XSysMonPsu_Config *ConfigP *****************************************************************************/ static void XSysMonPsu_StubHandler(void *CallBackRef) { - (void *) CallBackRef; + (void) CallBackRef; /* Assert occurs always since this is a stub and should never be called */ Xil_AssertVoidAlways(); @@ -189,6 +200,7 @@ static void XSysMonPsu_StubHandler(void *CallBackRef) ******************************************************************************/ void XSysMonPsu_Reset(XSysMonPsu *InstancePtr) { + u8 IsPlReset; /* Assert the arguments. */ Xil_AssertVoid(InstancePtr != NULL); @@ -196,9 +208,14 @@ void XSysMonPsu_Reset(XSysMonPsu *InstancePtr) XSysmonPsu_WriteReg(InstancePtr->Config.BaseAddress + XPS_BA_OFFSET + XSYSMONPSU_VP_VN_OFFSET, XSYSMONPSU_VP_VN_MASK); - /* RESET the PL SYSMON */ - XSysmonPsu_WriteReg(InstancePtr->Config.BaseAddress + XPL_BA_OFFSET + - XSYSMONPSU_VP_VN_OFFSET, XSYSMONPSU_VP_VN_MASK); + /* Check for PL is under reset or not */ + IsPlReset = (XSysmonPsu_ReadReg(CSU_BASEADDR + PCAP_STATUS_OFFSET) & + PL_CFG_RESET_MASK) >> PL_CFG_RESET_SHIFT; + if (IsPlReset != 0U) { + /* RESET the PL SYSMON */ + XSysmonPsu_WriteReg(InstancePtr->Config.BaseAddress + XPL_BA_OFFSET + + XSYSMONPSU_VP_VN_OFFSET, XSYSMONPSU_VP_VN_MASK); + } } @@ -576,7 +593,9 @@ s32 XSysMonPsu_SetSingleChParams(XSysMonPsu *InstancePtr, u8 Channel, ((Channel >= XSM_CH_SUPPLY_CALIB) && (Channel <= XSM_CH_GAINERR_CALIB)) || ((Channel >= XSM_CH_SUPPLY4) && - (Channel <= XSM_CH_TEMP_REMTE))); + (Channel <= XSM_CH_TEMP_REMTE)) || + ((Channel >= XSM_CH_VCC_PSLL0) && + (Channel <= XSM_CH_RESERVE1))); Xil_AssertNonvoid((IncreaseAcqCycles == TRUE) || (IncreaseAcqCycles == FALSE)); Xil_AssertNonvoid((IsEventMode == TRUE) || (IsEventMode == FALSE)); @@ -1163,6 +1182,60 @@ u8 XSysMonPsu_GetAdcClkDivisor(XSysMonPsu *InstancePtr, u32 SysmonBlk) return (u8) (Divisor >> XSYSMONPSU_CFG_REG2_CLK_DVDR_SHIFT); } +u8 XSysMonPsu_UpdateAdcClkDivisor(XSysMonPsu *InstancePtr, u32 SysmonBlk) +{ + u16 Divisor; + u32 EffectiveBaseAddress; + u32 RegValue; + u32 InputFreq = InstancePtr->Config.InputClockMHz; + + /* Assert the arguments. */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL)); + + /* Calculate the effective baseaddress based on the Sysmon instance. */ + EffectiveBaseAddress = + XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress, + SysmonBlk); + + /* Read the divisor value from the Configuration Register 2. */ + Divisor = (u16) XSysmonPsu_ReadReg(EffectiveBaseAddress + + XSYSMONPSU_CFG_REG2_OFFSET); + Divisor = Divisor >> XSYSMONPSU_CFG_REG2_CLK_DVDR_SHIFT; + + while (1) { + if (!Divisor) { + if ((SysmonBlk == XSYSMON_PS) && + (InputFreq/8 >= 1) && (InputFreq/8 <= 26)) { + break; + } else if ((SysmonBlk == XSYSMON_PL) && + (InputFreq/2 >= 1) && (InputFreq/2 <= 26)) { + break; + } + } else if ((InputFreq/Divisor >= 1) && + (InputFreq/Divisor <= 26)) { + break; + } else { + Divisor += 1; + } + } + + /* + * Read the Configuration Register 2 and the clear the clock divisor + * bits. + */ + RegValue = XSysmonPsu_ReadReg(EffectiveBaseAddress + + XSYSMONPSU_CFG_REG2_OFFSET); + RegValue &= ~(XSYSMONPSU_CFG_REG2_CLK_DVDR_MASK); + + /* Write the divisor value into the Configuration Register 2. */ + RegValue |= ((u32)Divisor << XSYSMONPSU_CFG_REG2_CLK_DVDR_SHIFT) & + XSYSMONPSU_CFG_REG2_CLK_DVDR_MASK; + XSysmonPsu_WriteReg(EffectiveBaseAddress + XSYSMONPSU_CFG_REG2_OFFSET, + RegValue); + + return (u8)Divisor; +} /****************************************************************************/ /** * diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_3/src/xsysmonpsu.h similarity index 86% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_3/src/xsysmonpsu.h index ba090c5aa..8fcaa19fe 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_3/src/xsysmonpsu.h @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2016 Xilinx, Inc. All rights reserved. +* Copyright (C) 2016-2017 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -18,8 +18,8 @@ * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. @@ -163,6 +163,21 @@ * set/get 64 bit value. * Added constants XSM_CFR_ALM_SUPPLY*(8-31)_MASKs to * provide support for enabling extra PS alarams. +* 2.1 sk 03/03/16 Check for PL reset before doing PL Sysmon reset. +* ms 03/17/17 Added readme.txt file in examples folder for doxygen +* generation. +* ms 04/05/17 Modified Comment lines in functions of sysmonpsu +* examples to recognize it as documentation block +* for doxygen generation. +* 2.2 sk 04/14/17 Corrected temperature conversion formulas. +* 2.3 mn 12/11/17 Added missing closing bracket error when C++ is used +* mn 12/12/17 Added Conversion Support for voltages having Range of +* 1 Volt +* mn 12/13/17 Correct the AMS block channel numbers +* ms 12/15/17 Added peripheral test support. +* ms 01/04/18 Provided conditional checks for interrupt example +* in sysmonpsu_header.h +* mn 03/08/18 Update Clock Divisor to the proper value * * * @@ -211,22 +226,14 @@ extern "C" { #define XSM_CH_SUPPLY10 35U /**< SUPPLY10 PS_MGTRAVTT */ #define XSM_CH_VCCAMS 36U /**< VCCAMS */ #define XSM_CH_TEMP_REMTE 37U /**< Temperature Remote */ -#define XSM_CH_VCC_PSLL0 38U /**< VCC_PSLL0 */ -#define XSM_CH_VCC_PSLL1 39U /**< VCC_PSLL1 */ -#define XSM_CH_VCC_PSLL2 40U /**< VCC_PSLL2 */ -#define XSM_CH_VCC_PSLL3 41U /**< VCC_PSLL3 */ -#define XSM_CH_VCC_PSLL4 42U /**< VCC_PSLL4 */ -#define XSM_CH_VCC_PSBATT 43U /**< VCC_PSBATT */ -#define XSM_CH_VCCINT 44U /**< VCCINT */ -#define XSM_CH_VCCBRAM 45U /**< VCCBRAM */ -#define XSM_CH_VCCAUX 46U /**< VCCAUX */ -#define XSM_CH_VCC_PSDDRPLL 47U /**< VCC_PSDDRPLL */ -#define XSM_CH_DDRPHY_VREF 48U /**< DDRPHY_VREF */ -#define XSM_CH_DDRPHY_AT0 49U /**< DDRPHY_AT0 */ -#define XSM_CH_PSGT_AT0 50U /**< PSGT_AT0 */ -#define XSM_CH_PSGT_AT1 51U /**< PSGT_AT0 */ -#define XSM_CH_RESERVE0 52U /**< PSGT_AT0 */ -#define XSM_CH_RESERVE1 53U /**< PSGT_AT0 */ +#define XSM_CH_VCC_PSLL0 48U /**< VCC_PSLL0 */ +#define XSM_CH_VCC_PSLL3 51U /**< VCC_PSLL3 */ +#define XSM_CH_VCCINT 54U /**< VCCINT */ +#define XSM_CH_VCCBRAM 55U /**< VCCBRAM */ +#define XSM_CH_VCCAUX 56U /**< VCCAUX */ +#define XSM_CH_VCC_PSDDRPLL 57U /**< VCC_PSDDRPLL */ +#define XSM_CH_DDRPHY_VREF 58U /**< DDRPHY_VREF */ +#define XSM_CH_RESERVE1 63U /**< PSGT_AT0 */ /*@}*/ @@ -381,7 +388,8 @@ typedef void (*XSysMonPsu_Handler) (void *CallBackRef); */ typedef struct { u16 DeviceId; /**< Unique ID of device */ - u32 BaseAddress; /**< Register base address */ + u32 BaseAddress; /**< Register base address */ + u16 InputClockMHz; /**< Input clock frequency */ } XSysMonPsu_Config; /** @@ -425,7 +433,7 @@ typedef struct { * *****************************************************************************/ #define XSysMonPsu_RawToTemperature_OnChip(AdcData) \ - ((((float)(AdcData)/65536.0f)/0.00199451786f ) - 273.6777f) + ((((float)(AdcData)/65536.0f)/0.00196342531f ) - 280.2309f) /****************************************************************************/ /** @@ -442,12 +450,30 @@ typedef struct { * *****************************************************************************/ #define XSysMonPsu_RawToTemperature_ExternalRef(AdcData) \ - ((((float)(AdcData)/65536.0f)/0.00198842814f ) - 273.8195f) + ((((float)(AdcData)/65536.0f)/0.00197008621f ) - 279.4266f) /****************************************************************************/ /** * -* This macro converts System Monitor Raw Data to Voltage(volts). +* This macro converts System Monitor Raw Data to Voltage(volts) for VpVn +* supply. +* +* @param AdcData is the System Monitor ADC Raw Data. +* +* @return The Voltage in volts. +* +* @note C-Style signature: +* float XSysMon_VpVnRawToVoltage(u32 AdcData) +* +*****************************************************************************/ +#define XSysMonPsu_VpVnRawToVoltage(AdcData) \ + ((((float)(AdcData))* (1.0f))/65536.0f) + +/****************************************************************************/ +/** +* +* This macro converts System Monitor Raw Data to Voltage(volts) other than +* VCCO_PSIO supply. * * @param AdcData is the System Monitor ADC Raw Data. * @@ -460,6 +486,23 @@ typedef struct { #define XSysMonPsu_RawToVoltage(AdcData) \ ((((float)(AdcData))* (3.0f))/65536.0f) +/****************************************************************************/ +/** +* +* This macro converts System Monitor Raw Data to Voltage(volts) for +* VCCO_PSIO supply. +* +* @param AdcData is the System Monitor ADC Raw Data. +* +* @return The Voltage in volts. +* +* @note C-Style signature: +* float XSysMon_RawToVoltage(u32 AdcData) +* +*****************************************************************************/ +#define XSysMonPsu_VccopsioRawToVoltage(AdcData) \ + ((((float)(AdcData))* (6.0f))/65536.0f) + /****************************************************************************/ /** * @@ -476,7 +519,7 @@ typedef struct { * *****************************************************************************/ #define XSysMonPsu_TemperatureToRaw_OnChip(Temperature) \ - ((s32)(((Temperature) + 273.6777f)*65536.0f*0.00199451786f)) + ((s32)(((Temperature) + 280.2309f)*65536.0f*0.00196342531f)) /****************************************************************************/ /** @@ -494,12 +537,13 @@ typedef struct { * *****************************************************************************/ #define XSysMonPsu_TemperatureToRaw_ExternalRef(Temperature) \ - ((s32)(((Temperature) + 273.8195f)*65536.0f*0.00198842814f)) + ((s32)(((Temperature) + 279.4266f)*65536.0f*0.00197008621f)) /****************************************************************************/ /** * -* This macro converts Voltage in Volts to System Monitor Raw Data. +* This macro converts Voltage in Volts to System Monitor Raw Data other than +* VCCO_PSIO supply * * @param Voltage is the Voltage in volts to be converted to * System Monitor/ADC Raw Data. @@ -513,6 +557,24 @@ typedef struct { #define XSysMonPsu_VoltageToRaw(Voltage) \ ((s32)((Voltage)*65536.0f/3.0f)) +/****************************************************************************/ +/** +* +* This macro converts Voltage in Volts to System Monitor Raw Data for +* VCCO_PSIO supply +* +* @param Voltage is the Voltage in volts to be converted to +* System Monitor/ADC Raw Data. +* +* @return The System Monitor ADC Raw Data. +* +* @note C-Style signature: +* int XSysMon_VoltageToRaw(float Voltage) +* +*****************************************************************************/ +#define XSysMonPsu_VccopsioVoltageToRaw(Voltage) \ + ((s32)((Voltage)*65536.0f/6.0f)) + /****************************************************************************/ /** * @@ -574,6 +636,7 @@ void XSysMonPsu_SetExtenalMux(XSysMonPsu *InstancePtr, u8 Channel, u32 SysmonBlk u32 XSysMonPsu_GetExtenalMux(XSysMonPsu *InstancePtr, u32 SysmonBlk); void XSysMonPsu_SetAdcClkDivisor(XSysMonPsu *InstancePtr, u8 Divisor, u32 SysmonBlk); u8 XSysMonPsu_GetAdcClkDivisor(XSysMonPsu *InstancePtr, u32 SysmonBlk); +u8 XSysMonPsu_UpdateAdcClkDivisor(XSysMonPsu *InstancePtr, u32 SysmonBlk); s32 XSysMonPsu_SetSeqChEnables(XSysMonPsu *InstancePtr, u64 ChEnableMask, u32 SysmonBlk); u64 XSysMonPsu_GetSeqAvgEnables(XSysMonPsu *InstancePtr, u32 SysmonBlk); @@ -607,4 +670,8 @@ s32 XSysMonPsu_SelfTest(XSysMonPsu *InstancePtr); XSysMonPsu_Config *XSysMonPsu_LookupConfig(u16 DeviceId); +#ifdef __cplusplus +} +#endif + #endif /* XSYSMONPSU_H_ */ diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_3/src/xsysmonpsu_g.c similarity index 88% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_g.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_3/src/xsysmonpsu_g.c index b692531ad..34bd80b34 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_g.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_3/src/xsysmonpsu_g.c @@ -5,7 +5,7 @@ * Version: * DO NOT EDIT. * -* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.* +* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.* *Permission is hereby granted, free of charge, to any person obtaining a copy *of this software and associated documentation files (the Software), to deal *in the Software without restriction, including without limitation the rights @@ -44,11 +44,12 @@ * The configuration table for devices */ -XSysMonPsu_Config XSysMonPsu_ConfigTable[] = +XSysMonPsu_Config XSysMonPsu_ConfigTable[XPAR_XSYSMONPSU_NUM_INSTANCES] = { { XPAR_PSU_AMS_DEVICE_ID, - XPAR_PSU_AMS_BASEADDR + XPAR_PSU_AMS_BASEADDR, + XPAR_PSU_AMS_REF_FREQMHZ } }; diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_3/src/xsysmonpsu_hw.h similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_hw.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_3/src/xsysmonpsu_hw.h index 80266ebf9..20082773c 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_hw.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_3/src/xsysmonpsu_hw.h @@ -18,8 +18,8 @@ * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. @@ -46,6 +46,7 @@ * 1.0 kvn 12/15/15 First release * 2.0 vns 08/14/16 Added CFG_REG3, SEQ_INPUT_MODE2, SEQ_ACQ2, * SEQ_CH2 and SEQ_AVG2 offsets and bit masks +* 2.1 sk 03/03/16 Check for PL reset before doing PL Sysmon reset. * * * @@ -2281,6 +2282,11 @@ extern "C" { #define XSYSMONPSU_MIN_TEMP_REMTE_WIDTH 16U #define XSYSMONPSU_MIN_TEMP_REMTE_MASK 0x0000ffffU +#define CSU_BASEADDR 0xFFCA0000U +#define PCAP_STATUS_OFFSET 0x00003010U +#define PL_CFG_RESET_MASK 0x00000040U +#define PL_CFG_RESET_SHIFT 6U + /***************** Macros (Inline Functions) Definitions *********************/ /****************************************************************************/ diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_intr.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_3/src/xsysmonpsu_intr.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_intr.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_3/src/xsysmonpsu_intr.c index b178c2e11..12d921913 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_intr.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_3/src/xsysmonpsu_intr.c @@ -18,8 +18,8 @@ * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_selftest.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_3/src/xsysmonpsu_selftest.c similarity index 98% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_selftest.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_3/src/xsysmonpsu_selftest.c index 5b709be14..9b68b887e 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_selftest.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_3/src/xsysmonpsu_selftest.c @@ -18,8 +18,8 @@ * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_3/src/xsysmonpsu_sinit.c similarity index 97% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_sinit.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_3/src/xsysmonpsu_sinit.c index 34249a209..32e17ab59 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/sysmonpsu_v2_0/src/xsysmonpsu_sinit.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v2_3/src/xsysmonpsu_sinit.c @@ -18,8 +18,8 @@ * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_5/src/Makefile similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/Makefile rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_5/src/Makefile diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_1/src/xttcps.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_5/src/xttcps.c similarity index 93% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_1/src/xttcps.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_5/src/xttcps.c index 4534553f6..b2382f1b2 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_1/src/xttcps.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_5/src/xttcps.c @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -33,7 +33,7 @@ /** * * @file xttcps.c -* @addtogroup ttcps_v3_0 +* @addtogroup ttcps_v3_5 * @{ * * This file contains the implementation of the XTtcPs driver. This driver @@ -50,7 +50,12 @@ * 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance. * 3.01 pkp 01/30/16 Modified XTtcPs_CfgInitialize to add XTtcps_Stop * to stop the timer before configuring -* +* 3.2 mus 10/28/16 Modified XTtcPs_CalcIntervalFromFreq to calculate +* 32 bit interval count for zynq ultrascale+mpsoc +* 3.5 srm 10/06/17 Updated XTtcPs_GetMatchValue and XTtcPs_SetMatchValue +* APIs to use correct match register width for zynq +* (i.e. 16 bit) and zynq ultrascale+mpsoc (i.e. 32 bit). +* It fixes CR# 986617 * * ******************************************************************************/ @@ -194,7 +199,7 @@ s32 XTtcPs_CfgInitialize(XTtcPs *InstancePtr, XTtcPs_Config *ConfigPtr, * @note None * ****************************************************************************/ -void XTtcPs_SetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex, u16 Value) +void XTtcPs_SetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex, XMatchRegValue Value) { /* * Assert to validate input arguments. @@ -220,12 +225,12 @@ void XTtcPs_SetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex, u16 Value) * @param MatchIndex is the index to the match register to be set. * Valid values are 0, 1, or 2. * -* @return None +* @return The match register value * * @note None * ****************************************************************************/ -u16 XTtcPs_GetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex) +XMatchRegValue XTtcPs_GetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex) { u32 MatchReg; @@ -239,7 +244,7 @@ u16 XTtcPs_GetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex) MatchReg = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress, XTtcPs_Match_N_Offset(MatchIndex)); - return (u16) MatchReg; + return (XMatchRegValue) MatchReg; } /*****************************************************************************/ @@ -377,7 +382,7 @@ u8 XTtcPs_GetPrescaler(XTtcPs *InstancePtr) * ****************************************************************************/ void XTtcPs_CalcIntervalFromFreq(XTtcPs *InstancePtr, u32 Freq, - u16 *Interval, u8 *Prescaler) + XInterval *Interval, u8 *Prescaler) { u8 TmpPrescaler; u32 TempValue; @@ -396,7 +401,7 @@ void XTtcPs_CalcIntervalFromFreq(XTtcPs *InstancePtr, u32 Freq, * The frequency is too high, it is too close to the input * clock value. Use maximum values to signal caller. */ - *Interval = 0xFFFFU; + *Interval = XTTCPS_MAX_INTERVAL_COUNT; *Prescaler = 0xFFU; return; } @@ -408,7 +413,7 @@ void XTtcPs_CalcIntervalFromFreq(XTtcPs *InstancePtr, u32 Freq, /* * We do not need a prescaler, so set the values appropriately */ - *Interval = (u16)TempValue; + *Interval = (XInterval)TempValue; *Prescaler = XTTCPS_CLK_CNTRL_PS_DISABLE; return; } @@ -425,7 +430,7 @@ void XTtcPs_CalcIntervalFromFreq(XTtcPs *InstancePtr, u32 Freq, /* * Set the values appropriately */ - *Interval = (u16)TempValue; + *Interval = (XInterval)TempValue; *Prescaler = TmpPrescaler; return; } @@ -434,7 +439,7 @@ void XTtcPs_CalcIntervalFromFreq(XTtcPs *InstancePtr, u32 Freq, /* Can not find interval values that work for the given frequency. * Return maximum values to signal caller. */ - *Interval = 0XFFFFU; + *Interval = XTTCPS_MAX_INTERVAL_COUNT; *Prescaler = 0XFFU; return; } diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_1/src/xttcps.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_5/src/xttcps.h similarity index 84% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_1/src/xttcps.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_5/src/xttcps.h index 646d24db5..b7b4e1950 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/ttcps_v3_1/src/xttcps.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_5/src/xttcps.h @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -33,7 +33,7 @@ /** * * @file xttcps.h -* @addtogroup ttcps_v3_0 +* @addtogroup ttcps_v3_5 * @{ * @details * @@ -91,6 +91,18 @@ * 2.0 adk 12/10/13 Updated as per the New Tcl API's * 3.0 pkp 12/09/14 Added support for Zynq Ultrascale Mp.Also code * modified for MISRA-C:2012 compliance. +* 3.2 mus 10/28/16 Modified XTtcPs_GetCounterValue and XTtcPs_SetInterval +* macros to return 32 bit values for zynq ultrascale+mpsoc +* ms 01/23/17 Modified xil_printf statement in main function for all +* examples to ensure that "Successfully ran" and "Failed" +* strings are available in all examples. This is a fix +* for CR-965028. +* ms 03/17/17 Added readme.txt file in examples folder for doxygen +* generation. +* 3.4 ms 04/18/17 Modified tcl file to add suffix U for all macros +* definitions of ttcps in xparameters.h +* 3.5 srm 10/06/17 Added new typedef XMatchRegValue for match register width +* * * ******************************************************************************/ @@ -109,6 +121,16 @@ extern "C" { /************************** Constant Definitions *****************************/ + +/* + * Maximum Value for interval counter + */ + #if defined(ARMA9) + #define XTTCPS_MAX_INTERVAL_COUNT 0xFFFFU + #else + #define XTTCPS_MAX_INTERVAL_COUNT 0xFFFFFFFFU + #endif + /** @name Configuration options * * Options for the device. Each of the options is bit field, so more than one @@ -125,7 +147,6 @@ extern "C" { #define XTTCPS_OPTION_WAVE_DISABLE 0x00000020U /**< No waveform output */ #define XTTCPS_OPTION_WAVE_POLARITY 0x00000040U /**< Waveform polarity */ /*@}*/ - /**************************** Type Definitions *******************************/ /** @@ -148,7 +169,16 @@ typedef struct { u32 IsReady; /**< Device is initialized and ready */ } XTtcPs; - +/** + * This typedef contains interval count and Match register value + */ +#if defined(ARMA9) +typedef u16 XInterval; +typedef u16 XMatchRegValue; +#else +typedef u32 XInterval; +typedef u32 XMatchRegValue; +#endif /***************** Macros (Inline Functions) Definitions *********************/ /* @@ -223,14 +253,27 @@ typedef struct { * * @param InstancePtr is a pointer to the XTtcPs instance. * -* @return 16-bit counter value. +* @return zynq:16 bit counter value. +* zynq ultrascale+mpsoc:32 bit counter value. * * @note C-style signature: -* u16 XTtcPs_GetCounterValue(XTtcPs *InstancePtr) +* zynq: u16 XTtcPs_GetCounterValue(XTtcPs *InstancePtr) +* zynq ultrascale+mpsoc: u32 XTtcPs_GetCounterValue(XTtcPs *InstancePtr) * ****************************************************************************/ +#if defined(ARMA9) +/* + * ttc supports 16 bit counter for zynq + */ #define XTtcPs_GetCounterValue(InstancePtr) \ (u16)InstReadReg((InstancePtr), XTTCPS_COUNT_VALUE_OFFSET) +#else +/* + * ttc supports 32 bit counter for zynq ultrascale+mpsoc + */ +#define XTtcPs_GetCounterValue(InstancePtr) \ + InstReadReg((InstancePtr), XTTCPS_COUNT_VALUE_OFFSET) +#endif /*****************************************************************************/ /** @@ -243,7 +286,7 @@ typedef struct { * @return None * * @note C-style signature: -* void XTtcPs_SetInterval(XTtcPs *InstancePtr, u16 Value) +* void XTtcPs_SetInterval(XTtcPs *InstancePtr, XInterval Value) * ****************************************************************************/ #define XTtcPs_SetInterval(InstancePtr, Value) \ @@ -256,15 +299,27 @@ typedef struct { * * @param InstancePtr is a pointer to the XTtcPs instance. * -* @return 16-bit interval value +* @return zynq:16 bit interval value. +* zynq ultrascale+mpsoc:32 bit interval value. * * @note C-style signature: -* u16 XTtcPs_GetInterval(XTtcPs *InstancePtr) +* zynq: u16 XTtcPs_GetInterval(XTtcPs *InstancePtr) +* zynq ultrascale+mpsoc: u32 XTtcPs_GetInterval(XTtcPs *InstancePtr) * ****************************************************************************/ +#if defined(ARMA9) +/* + * ttc supports 16 bit interval counter for zynq + */ #define XTtcPs_GetInterval(InstancePtr) \ (u16)InstReadReg((InstancePtr), XTTCPS_INTERVAL_VAL_OFFSET) - +#else +/* + * ttc supports 32 bit interval counter for zynq ultrascale+mpsoc + */ +#define XTtcPs_GetInterval(InstancePtr) \ + InstReadReg((InstancePtr), XTTCPS_INTERVAL_VAL_OFFSET) +#endif /*****************************************************************************/ /** * @@ -384,14 +439,14 @@ XTtcPs_Config *XTtcPs_LookupConfig(u16 DeviceId); s32 XTtcPs_CfgInitialize(XTtcPs *InstancePtr, XTtcPs_Config * ConfigPtr, u32 EffectiveAddr); -void XTtcPs_SetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex, u16 Value); -u16 XTtcPs_GetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex); +void XTtcPs_SetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex, XMatchRegValue Value); +XMatchRegValue XTtcPs_GetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex); void XTtcPs_SetPrescaler(XTtcPs *InstancePtr, u8 PrescalerValue); u8 XTtcPs_GetPrescaler(XTtcPs *InstancePtr); void XTtcPs_CalcIntervalFromFreq(XTtcPs *InstancePtr, u32 Freq, - u16 *Interval, u8 *Prescaler); + XInterval *Interval, u8 *Prescaler); /* * Functions for options, in file xttcps_options.c diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_5/src/xttcps_g.c similarity index 94% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps_g.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_5/src/xttcps_g.c index 28d356092..571cb366a 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps_g.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_5/src/xttcps_g.c @@ -5,7 +5,7 @@ * Version: * DO NOT EDIT. * -* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.* +* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.* *Permission is hereby granted, free of charge, to any person obtaining a copy *of this software and associated documentation files (the Software), to deal *in the Software without restriction, including without limitation the rights diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_2/src/xttcps_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_5/src/xttcps_hw.h similarity index 90% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_2/src/xttcps_hw.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_5/src/xttcps_hw.h index af78bcd67..b1fa545bd 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_2/src/xttcps_hw.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_5/src/xttcps_hw.h @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -33,7 +33,7 @@ /** * * @file xttcps_hw.h -* @addtogroup ttcps_v3_0 +* @addtogroup ttcps_v3_5 * @{ * * This file defines the hardware interface to one of the three timer counters @@ -47,7 +47,10 @@ * ----- ------ -------- ------------------------------------------------- * 1.00a drg/jz 01/21/10 First release * 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance. -* +* 3.5 srm 10/06/17 Updated XTTCPS_COUNT_VALUE_MASK, +* XTTCPS_INTERVAL_VAL_MASK, XTTCPS_MATCH_MASK macros to +* mask 16 bit values for zynq and 32 bit values for +* zynq ultrascale+mpsoc " * * ******************************************************************************/ @@ -66,6 +69,12 @@ extern "C" { #include "xil_io.h" /************************** Constant Definitions *****************************/ +/* + * Flag for a9 processor + */ + #if !defined (ARMR5) && !defined (__aarch64__) && !defined (ARMA53_32) + #define ARMA9 + #endif /** @name Register Map * @@ -114,7 +123,11 @@ extern "C" { * Current Counter Value Register definitions * @{ */ +#if defined(ARMA9) #define XTTCPS_COUNT_VALUE_MASK 0x0000FFFFU /**< 16-bit counter value */ +#else +#define XTTCPS_COUNT_VALUE_MASK 0xFFFFFFFFU /**< 32-bit counter value */ +#endif /* @} */ /** @name Interval Value Register @@ -122,7 +135,11 @@ extern "C" { * down to. * @{ */ +#if defined(ARMA9) #define XTTCPS_INTERVAL_VAL_MASK 0x0000FFFFU /**< 16-bit Interval value*/ +#else +#define XTTCPS_INTERVAL_VAL_MASK 0xFFFFFFFFU /**< 32-bit Interval value*/ +#endif /* @} */ /** @name Match Registers @@ -130,7 +147,11 @@ extern "C" { * registers. * @{ */ +#if defined(ARMA9) #define XTTCPS_MATCH_MASK 0x0000FFFFU /**< 16-bit Match value */ +#else +#define XTTCPS_MATCH_MASK 0xFFFFFFFFU /**< 32-bit Match value */ +#endif #define XTTCPS_NUM_MATCH_REG 3U /**< Num of Match reg */ /* @} */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_2/src/xttcps_options.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_5/src/xttcps_options.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_2/src/xttcps_options.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_5/src/xttcps_options.c index 532b235c5..01dd9efb3 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_2/src/xttcps_options.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_5/src/xttcps_options.c @@ -33,7 +33,7 @@ /** * * @file xttcps_options.c -* @addtogroup ttcps_v3_0 +* @addtogroup ttcps_v3_5 * @{ * * This file contains functions to get or set option features for the device. diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_2/src/xttcps_selftest.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_5/src/xttcps_selftest.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_2/src/xttcps_selftest.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_5/src/xttcps_selftest.c index 4923df667..b1dd7d0a2 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/ttcps_v3_2/src/xttcps_selftest.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_5/src/xttcps_selftest.c @@ -33,7 +33,7 @@ /** * * @file xttcps_selftest.c -* @addtogroup ttcps_v3_0 +* @addtogroup ttcps_v3_5 * @{ * * This file contains the implementation of self test function for the diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_5/src/xttcps_sinit.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps_sinit.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_5/src/xttcps_sinit.c index ef3c6ea6b..4684c8a9c 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_2/src/xttcps_sinit.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_5/src/xttcps_sinit.c @@ -33,7 +33,7 @@ /** * * @file xttcps_sinit.c -* @addtogroup ttcps_v3_0 +* @addtogroup ttcps_v3_5 * @{ * * The implementation of the XTtcPs driver's static initialization functionality. diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_6/src/Makefile similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_3/src/Makefile rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_6/src/Makefile diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_3/src/xuartps.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_6/src/xuartps.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_3/src/xuartps.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_6/src/xuartps.c index a338d1f09..c33ec5481 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_3/src/xuartps.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_6/src/xuartps.c @@ -33,7 +33,7 @@ /** * * @file xuartps.c -* @addtogroup uartps_v3_1 +* @addtogroup uartps_v3_5 * @{ * * This file contains the implementation of the interface functions for XUartPs @@ -49,6 +49,7 @@ * baud rate. CR# 804281. * 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance. * 3.1 kvn 04/10/15 Modified code for latest RTL changes. +* 3.5 NK 09/26/17 Fix the RX Buffer Overflow issue. * * *****************************************************************************/ @@ -463,7 +464,7 @@ u32 XUartPs_ReceiveBuffer(XUartPs *InstancePtr) * Loop until there is no more data in RX FIFO or the specified * number of bytes has been received */ - while((ReceivedCount <= InstancePtr->ReceiveBuffer.RemainingBytes)&& + while((ReceivedCount < InstancePtr->ReceiveBuffer.RemainingBytes)&& (((CsrRegister & XUARTPS_SR_RXEMPTY) == (u32)0))){ if (InstancePtr->is_rxbs_error) { @@ -635,7 +636,7 @@ s32 XUartPs_SetBaudRate(XUartPs *InstancePtr, u32 BaudRate) static void XUartPs_StubHandler(void *CallBackRef, u32 Event, u32 ByteCount) { - (void *) CallBackRef; + (void) CallBackRef; (void) Event; (void) ByteCount; /* Assert occurs always since this is a stub and should never be called */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v3_1/src/xuartps.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_6/src/xuartps.h similarity index 96% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v3_1/src/xuartps.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_6/src/xuartps.h index 6bd42b21c..33758c23b 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v3_1/src/xuartps.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_6/src/xuartps.h @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -33,7 +33,7 @@ /** * * @file xuartps.h -* @addtogroup uartps_v3_1 +* @addtogroup uartps_v3_5 * @{ * @details * @@ -161,6 +161,15 @@ * platform variable in driver instance structure. * 3.1 adk 14/03/16 Include interrupt examples in the peripheral test when * uart is connected to a valid interrupt controller CR#946803. +* 3.2 rk 07/20/16 Modified the logic for transmission break bit set +* 3.4 ms 01/23/17 Added xil_printf statement in main function for all +* examples to ensure that "Successfully ran" and "Failed" +* strings are available in all examples. This is a fix +* for CR-965028. +* ms 03/17/17 Added readme.txt file in examples folder for doxygen +* generation. +* 3.6 ms 02/16/18 Updates the flow control mode offset value in modem +* control register. * * * diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_3/src/xuartps_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_6/src/xuartps_g.c similarity index 91% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_3/src/xuartps_g.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_6/src/xuartps_g.c index d4a8e5ab9..6abb20e4d 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_3/src/xuartps_g.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_6/src/xuartps_g.c @@ -5,7 +5,7 @@ * Version: * DO NOT EDIT. * -* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.* +* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.* *Permission is hereby granted, free of charge, to any person obtaining a copy *of this software and associated documentation files (the Software), to deal *in the Software without restriction, including without limitation the rights @@ -44,7 +44,7 @@ * The configuration table for devices */ -XUartPs_Config XUartPs_ConfigTable[] = +XUartPs_Config XUartPs_ConfigTable[XPAR_XUARTPS_NUM_INSTANCES] = { { XPAR_PSU_UART_0_DEVICE_ID, diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v3_1/src/xuartps_hw.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_6/src/xuartps_hw.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v3_1/src/xuartps_hw.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_6/src/xuartps_hw.c index 299dd35ae..724c3cb40 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v3_1/src/xuartps_hw.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_6/src/xuartps_hw.c @@ -33,7 +33,7 @@ /** * * @file xuartps_hw.c -* @addtogroup uartps_v3_1 +* @addtogroup uartps_v3_5 * @{ * * diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v3_1/src/xuartps_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_6/src/xuartps_hw.h similarity index 98% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v3_1/src/xuartps_hw.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_6/src/xuartps_hw.h index 9f5f0b700..9a2bc4305 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v3_1/src/xuartps_hw.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_6/src/xuartps_hw.h @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* Copyright (C) 2010 - 2017 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -33,7 +33,7 @@ /** * * @file xuartps_hw.h -* @addtogroup uartps_v3_1 +* @addtogroup uartps_v3_5 * @{ * * This header file contains the hardware interface of an XUartPs device. @@ -55,6 +55,8 @@ * constant definitions. * 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance. * 3.1 kvn 04/10/15 Modified code for latest RTL changes. +* 3.6 ms 02/16/18 Updates flow control mode offset value in +* modem control register. * * * @@ -256,7 +258,7 @@ extern "C" { * * @{ */ -#define XUARTPS_MODEMCR_FCM 0x00000010U /**< Flow control mode */ +#define XUARTPS_MODEMCR_FCM 0x00000020U /**< Flow control mode */ #define XUARTPS_MODEMCR_RTS 0x00000002U /**< Request to send */ #define XUARTPS_MODEMCR_DTR 0x00000001U /**< Data terminal ready */ /* @} */ diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v3_1/src/xuartps_intr.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_6/src/xuartps_intr.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v3_1/src/xuartps_intr.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_6/src/xuartps_intr.c index 849cb48db..dff02fd63 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v3_1/src/xuartps_intr.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_6/src/xuartps_intr.c @@ -33,7 +33,7 @@ /** * * @file xuartps_intr.c -* @addtogroup uartps_v3_1 +* @addtogroup uartps_v3_5 * @{ * * This file contains the functions for interrupt handling @@ -249,7 +249,7 @@ void XUartPs_InterruptHandler(XUartPs *InstancePtr) *****************************************************************************/ static void ReceiveErrorHandler(XUartPs *InstancePtr, u32 IsrStatus) { - u32 ByteStatusValue, EventData; + u32 EventData; u32 Event; InstancePtr->is_rxbs_error = 0; diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v3_1/src/xuartps_options.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_6/src/xuartps_options.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v3_1/src/xuartps_options.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_6/src/xuartps_options.c index 7051d07ec..5d8d3017c 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v3_1/src/xuartps_options.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_6/src/xuartps_options.c @@ -33,7 +33,7 @@ /** * * @file xuartps_options.c -* @addtogroup uartps_v3_1 +* @addtogroup uartps_v3_5 * @{ * * The implementation of the options functions for the XUartPs driver. @@ -47,6 +47,7 @@ * 1.00 sdm 09/27/11 Fixed a bug in XUartPs_SetFlowDelay where the input * value was not being written to the register. * 3.00 kvn 02/13/15 Modified code for MISRA-C:2012 compliance. +* 3.2 rk 07/20/16 Modified the logic for transmission break bit set * * * @@ -199,6 +200,8 @@ void XUartPs_SetOptions(XUartPs *InstancePtr, u16 Options) * the register. */ if ((Options & OptionsTable[Index].Option) != (u16)0) { + if(OptionsTable[Index].Option == XUARTPS_OPTION_SET_BREAK) + Register &= ~XUARTPS_CR_STOPBRK; Register |= OptionsTable[Index].Mask; } else { diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_3/src/xuartps_selftest.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_6/src/xuartps_selftest.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_3/src/xuartps_selftest.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_6/src/xuartps_selftest.c index a1a7dd366..de58201a1 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/uartps_v3_3/src/xuartps_selftest.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_6/src/xuartps_selftest.c @@ -33,7 +33,7 @@ /** * * @file xuartps_selftest.c -* @addtogroup uartps_v3_1 +* @addtogroup uartps_v3_5 * @{ * * This file contains the self-test functions for the XUartPs driver. diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v3_1/src/xuartps_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_6/src/xuartps_sinit.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v3_1/src/xuartps_sinit.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_6/src/xuartps_sinit.c index 8dc87dae3..22e2f7a83 100644 --- a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/RTOSDemo_bsp/ps7_cortexa9_0/libsrc/uartps_v3_1/src/xuartps_sinit.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_6/src/xuartps_sinit.c @@ -33,7 +33,7 @@ /** * * @file xuartps_sinit.c -* @addtogroup uartps_v3_1 +* @addtogroup uartps_v3_5 * @{ * * The implementation of the XUartPs driver's static initialzation diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_4/src/Makefile similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/Makefile rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_4/src/Makefile diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_4/src/xusb_wrapper.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_4/src/xusb_wrapper.c new file mode 100644 index 000000000..57f859d81 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_4/src/xusb_wrapper.c @@ -0,0 +1,329 @@ +/****************************************************************************** + * + * Copyright (C) 2017 Xilinx, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * Use of the Software is limited solely to applications: + * (a) running on a Xilinx device, or + * (b) that interact with a Xilinx device through a bus or interconnect. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of the Xilinx shall not be used + * in advertising or otherwise to promote the sale, use or other dealings in + * this Software without prior written authorization from Xilinx. + * + ******************************************************************************/ +/*****************************************************************************/ +/** + * + * @file xusb_wrapper.c + * + * This file contains implementation of USBPSU Driver wrappers. + * + * 
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  	Date     Changes
+ * ----- ---- 	-------- -------------------------------------------------------
+ * 1.0   BK 	12/01/18 First release
+ *	 MYK	12/01/18 Added hibernation support for device mode
+ *	 vak	13/03/18 Moved the setup interrupt system calls from driver to
+ *			 example.
+ *
+ *
+ * + *****************************************************************************/ + +/***************************** Include Files *********************************/ +#include "xusb_wrapper.h" + +/************************** Variable Definitions *****************************/ + +/************************** Function Prototypes ******************************/ +Usb_Config* LookupConfig(u16 DeviceId) +{ + return XUsbPsu_LookupConfig(DeviceId); +} + +void CacheInit(void) +{ + +} + +s32 CfgInitialize(struct Usb_DevData *InstancePtr, + Usb_Config *ConfigPtr, u32 BaseAddress) +{ + PrivateData.AppData = InstancePtr; + InstancePtr->PrivateData = (void *)&PrivateData; + + return XUsbPsu_CfgInitialize((struct XUsbPsu *)InstancePtr->PrivateData, + ConfigPtr, BaseAddress); +} + +void Set_Ch9Handler( + void *InstancePtr, + void (*func)(struct Usb_DevData *, SetupPacket *)) +{ + XUsbPsu_set_ch9handler((struct XUsbPsu *)InstancePtr, func); +} + +void Set_RstHandler(void *InstancePtr, void (*func)(struct Usb_DevData *)) +{ + XUsbPsu_set_rsthandler((struct XUsbPsu *)InstancePtr, func); +} + +void Set_Disconnect(void *InstancePtr, void (*func)(struct Usb_DevData *)) +{ + XUsbPsu_set_disconnect((struct XUsbPsu *)InstancePtr, func); +} + +void EpConfigure(void *UsbInstance, u8 EndpointNo, u8 dir, u32 Type) +{ + (void)UsbInstance; + (void)EndpointNo; + (void)dir; + (void)Type; +} + +s32 ConfigureDevice(void *UsbInstance, u8 *MemPtr, u32 memSize) +{ + (void)UsbInstance; + (void)MemPtr; + (void)memSize; + return XST_SUCCESS; +} + +void SetEpHandler(void *InstancePtr, u8 Epnum, + u8 Dir, void (*Handler)(void *, u32, u32)) +{ + XUsbPsu_SetEpHandler((struct XUsbPsu *)InstancePtr, Epnum, Dir, Handler); +} + +s32 Usb_Start(void *InstancePtr) +{ + return XUsbPsu_Start((struct XUsbPsu *)InstancePtr); +} + +void *Get_DrvData(void *InstancePtr) +{ + return XUsbPsu_get_drvdata((struct XUsbPsu *)InstancePtr); +} + +void Set_DrvData(void *InstancePtr, void *data) +{ + XUsbPsu_set_drvdata((struct XUsbPsu *)InstancePtr, data); +} + +s32 IsEpStalled(void *InstancePtr, u8 Epnum, u8 Dir) +{ + return XUsbPsu_IsEpStalled((struct XUsbPsu *)InstancePtr, Epnum, Dir); +} + +void EpClearStall(void *InstancePtr, u8 Epnum, u8 Dir) +{ + XUsbPsu_EpClearStall((struct XUsbPsu *)InstancePtr, Epnum, Dir); +} + +s32 EpBufferSend(void *InstancePtr, u8 UsbEp, + u8 *BufferPtr, u32 BufferLen) +{ + if (UsbEp == 0 && BufferLen == 0) + return XST_SUCCESS; + else + return XUsbPsu_EpBufferSend((struct XUsbPsu *)InstancePtr, + UsbEp, BufferPtr, BufferLen); + +} + +s32 EpBufferRecv(void *InstancePtr, u8 UsbEp, + u8 *BufferPtr, u32 Length) +{ + return XUsbPsu_EpBufferRecv((struct XUsbPsu *)InstancePtr, UsbEp, + BufferPtr, Length); +} + +void EpSetStall(void *InstancePtr, u8 Epnum, u8 Dir) +{ + XUsbPsu_EpSetStall((struct XUsbPsu *)InstancePtr, Epnum, Dir); +} + +void SetBits(void *InstancePtr, u32 TestSel) +{ + (void)InstancePtr; + (void)TestSel; +} + +s32 SetDeviceAddress(void *InstancePtr, u16 Addr) +{ + return XUsbPsu_SetDeviceAddress((struct XUsbPsu *)InstancePtr, Addr); +} + +s32 SetU1SleepTimeout(void *InstancePtr, u8 Sleep) +{ + return XUsbPsu_SetU1SleepTimeout((struct XUsbPsu *)InstancePtr, Sleep); +} + +s32 SetU2SleepTimeout(void *InstancePtr, u8 Sleep) +{ + return XUsbPsu_SetU2SleepTimeout((struct XUsbPsu *)InstancePtr, Sleep); +} + +s32 AcceptU1U2Sleep(void *InstancePtr) +{ + return XUsbPsu_AcceptU1U2Sleep((struct XUsbPsu *)InstancePtr); + +} + +s32 U1SleepEnable(void *InstancePtr) +{ + return XUsbPsu_U1SleepEnable((struct XUsbPsu *)InstancePtr); +} + +s32 U2SleepEnable(void *InstancePtr) +{ + return XUsbPsu_U2SleepEnable((struct XUsbPsu *)InstancePtr); +} + +s32 U1SleepDisable(void *InstancePtr) +{ + return XUsbPsu_U1SleepDisable((struct XUsbPsu *)InstancePtr); +} + +s32 U2SleepDisable(void *InstancePtr) +{ + return XUsbPsu_U2SleepDisable((struct XUsbPsu *)InstancePtr); +} + +s32 EpEnable(void *InstancePtr, u8 UsbEpNum, u8 Dir, u16 Maxsize, u8 Type) +{ + return XUsbPsu_EpEnable((struct XUsbPsu *)InstancePtr, UsbEpNum, Dir, + Maxsize, Type, FALSE); +} + +s32 EpDisable(void *InstancePtr, u8 UsbEpNum, u8 Dir) +{ + return XUsbPsu_EpDisable((struct XUsbPsu *)InstancePtr, UsbEpNum, Dir); +} + +void Usb_SetSpeed(void *InstancePtr, u32 Speed) +{ + XUsbPsu_SetSpeed((struct XUsbPsu *)InstancePtr, Speed); +} + +/****************************************************************************/ +/** +* Sets speed of the Core for connecting to Host +* +* @param InstancePtr is a pointer to the Usb_DevData instance. +* +* @return XST_SUCCESS else XST_FAILURE +* +* @note None. +* +*****************************************************************************/ +s32 IsSuperSpeed(struct Usb_DevData *InstancePtr) +{ + if (InstancePtr->Speed != XUSBPSU_SPEED_SUPER) { + return XST_FAILURE; + } + + return XST_SUCCESS; +} + +/****************************************************************************/ +/** +* Set the Config state +* +* @param InstancePtr is a private member of Usb_DevData instance. +* @param Flag is the config value. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void SetConfigDone(void *InstancePtr, u8 Flag) +{ + ((struct XUsbPsu *)InstancePtr)->IsConfigDone = Flag; +} + +/****************************************************************************/ +/** +* Get the Config state +* +* @param InstancePtr is a private member of Usb_DevData instance. +* +* @return Current configuration value +* +* @note None. +* +*****************************************************************************/ +u8 GetConfigDone(void *InstancePtr) +{ + return (((struct XUsbPsu *)InstancePtr)->IsConfigDone); +} + +void Ep0StallRestart(void *InstancePtr) +{ + XUsbPsu_Ep0StallRestart((struct XUsbPsu *)InstancePtr); +} + +/******************************************************************************/ +/** + * This function sets Endpoint Interval. + * + * @param InstancePtr is a private member of Usb_DevData instance. + * @param UsbEpnum is Endpoint Number. + * @param Dir is Endpoint Direction(In/Out). + * @param Interval is the data transfer service interval + * + * @return None. + * + * @note None. + * + ******************************************************************************/ +void SetEpInterval(void *InstancePtr, u8 UsbEpNum, u8 Dir, u32 Interval) +{ + u32 PhyEpNum; + struct XUsbPsu_Ep *Ept; + + PhyEpNum = PhysicalEp(UsbEpNum, Dir); + Ept = &((struct XUsbPsu *)InstancePtr)->eps[PhyEpNum]; + Ept->Interval = Interval; +} + +void StopTransfer(void *InstancePtr, u8 EpNum, u8 Dir) +{ + XUsbPsu_StopTransfer((struct XUsbPsu *)InstancePtr, EpNum, Dir, TRUE); +} + +s32 StreamOn(void *InstancePtr, u8 EpNum, u8 Dir, u8 *BufferPtr) +{ + (void)InstancePtr; + (void)EpNum; + (void)Dir; + (void)BufferPtr; + /* Streaming will start on TxferNotReady Event */ + return XST_SUCCESS; +} + +void StreamOff(void *InstancePtr, u8 EpNum, u8 Dir) +{ + StopTransfer((struct XUsbPsu *)InstancePtr, EpNum, Dir); +} diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_4/src/xusb_wrapper.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_4/src/xusb_wrapper.h new file mode 100644 index 000000000..d21072bcd --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_4/src/xusb_wrapper.h @@ -0,0 +1,190 @@ +/****************************************************************************** + * + * Copyright (C) 2017 Xilinx, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * Use of the Software is limited solely to applications: + * (a) running on a Xilinx device, or + * (b) that interact with a Xilinx device through a bus or interconnect. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of the Xilinx shall not be used + * in advertising or otherwise to promote the sale, use or other dealings in + * this Software without prior written authorization from Xilinx. + * + ******************************************************************************/ +/*****************************************************************************/ +/** + * + * @file xusb_wrapper.h + * + * This file contains declarations for USBPSU Driver wrappers. + * + * 
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  	Date     Changes
+ * ----- ---- 	-------- -------------------------------------------------------
+ *  1.0  BK	12/01/18 First release
+ *	 MYK	12/01/18 Added hibernation support for device mode
+ *	 vak	22/01/18 Added Microblaze support for usbpsu driver
+ *	 vak	13/03/18 Moved the setup interrupt system calls from driver to
+ *			 example.
+ *
+ *
+ * + *****************************************************************************/ + +#ifndef XUSB_WRAPPER_H /* Prevent circular inclusions */ +#define XUSB_WRAPPER_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files ********************************/ +#include "xusbpsu.h" + +/************************** Constant Definitions ****************************/ +#define USB_DEVICE_ID XPAR_XUSBPSU_0_DEVICE_ID + +#define USB_EP_DIR_IN XUSBPSU_EP_DIR_IN +#define USB_EP_DIR_OUT XUSBPSU_EP_DIR_OUT + +#define USB_DIR_OUT 0U /* to device */ +#define USB_DIR_IN 0x80U /* to host */ + +/** + * @name Endpoint Address + * @{ + */ +#define USB_EP1_IN 0x81 +#define USB_EP1_OUT 0x01 +#define USB_EP2_IN 0x82 +#define USB_EP2_OUT 0x02 +/* @} */ + +/** + * @name Endpoint Type + * @{ + */ +#define USB_EP_TYPE_CONTROL XUSBPSU_ENDPOINT_XFER_CONTROL +#define USB_EP_TYPE_ISOCHRONOUS XUSBPSU_ENDPOINT_XFER_ISOC +#define USB_EP_TYPE_BULK XUSBPSU_ENDPOINT_XFER_BULK +#define USB_EP_TYPE_INTERRUPT XUSBPSU_ENDPOINT_XFER_INT +/* @} */ + +#define USB_ENDPOINT_NUMBER_MASK 0x0f /* in bEndpointAddress */ +#define USB_ENDPOINT_DIR_MASK 0x80 + +/* + * Device States + */ +#define USB_STATE_ATTACHED XUSBPSU_STATE_ATTACHED +#define USB_STATE_POWERED XUSBPSU_STATE_POWERED +#define USB_STATE_DEFAULT XUSBPSU_STATE_DEFAULT +#define USB_STATE_ADDRESS XUSBPSU_STATE_ADDRESS +#define USB_STATE_CONFIGURED XUSBPSU_STATE_CONFIGURED +#define USB_STATE_SUSPENDED XUSBPSU_STATE_SUSPENDED + +#define XUSBPSU_REQ_REPLY_LEN 1024 /**< Max size of reply buffer. */ +#define USB_REQ_REPLY_LEN XUSBPSU_REQ_REPLY_LEN + +/* + * Device Speeds + */ +#define USB_SPEED_UNKNOWN XUSBPSU_SPEED_UNKNOWN +#define USB_SPEED_LOW XUSBPSU_SPEED_LOW +#define USB_SPEED_FULL XUSBPSU_SPEED_FULL +#define USB_SPEED_HIGH XUSBPSU_SPEED_HIGH +#define USB_SPEED_SUPER XUSBPSU_SPEED_SUPER + +/* Device Configuration Speed */ +#define USB_DCFG_SPEED_MASK XUSBPSU_DCFG_SPEED_MASK +#define USB_DCFG_SUPERSPEED XUSBPSU_DCFG_SUPERSPEED +#define USB_DCFG_HIGHSPEED XUSBPSU_DCFG_HIGHSPEED +#define USB_DCFG_FULLSPEED2 XUSBPSU_DCFG_FULLSPEED2 +#define USB_DCFG_LOWSPEED XUSBPSU_DCFG_LOWSPEED +#define USB_DCFG_FULLSPEED1 XUSBPSU_DCFG_FULLSPEED1 + +#define USB_TEST_J XUSBPSU_TEST_J +#define USB_TEST_K XUSBPSU_TEST_K +#define USB_TEST_SE0_NAK XUSBPSU_TEST_SE0_NAK +#define USB_TEST_PACKET XUSBPSU_TEST_PACKET +#define USB_TEST_FORCE_ENABLE XUSBPSU_TEST_FORCE_ENABLE + +/* TODO: If we enable this macro, reconnection is failed with 2017.3 */ +#define USB_LPM_MODE XUSBPSU_LPM_MODE + +/* + * return Physical EP number as dwc3 mapping + */ +#define PhysicalEp(epnum, direction) (((epnum) << 1 ) | (direction)) + +/**************************** Type Definitions ******************************/ + +/************************** Variable Definitions *****************************/ +struct XUsbPsu PrivateData; + +/***************** Macros (Inline Functions) Definitions *********************/ +Usb_Config* LookupConfig(u16 DeviceId); +void CacheInit(void); +s32 CfgInitialize(struct Usb_DevData *InstancePtr, + Usb_Config *ConfigPtr, u32 BaseAddress); +void Set_Ch9Handler(void *InstancePtr, + void (*func)(struct Usb_DevData *, SetupPacket *)); +void Set_RstHandler(void *InstancePtr, void (*func)(struct Usb_DevData *)); +void Set_Disconnect(void *InstancePtr, void (*func)(struct Usb_DevData *)); +void EpConfigure(void *UsbInstance, u8 EndpointNo, u8 dir, u32 Type); +s32 ConfigureDevice(void *UsbInstance, u8 *MemPtr, u32 memSize); +void SetEpHandler(void *InstancePtr, u8 Epnum, + u8 Dir, void (*Handler)(void *, u32, u32)); +s32 Usb_Start(void *InstancePtr); +void *Get_DrvData(void *InstancePtr); +void Set_DrvData(void *InstancePtr, void *data); +s32 IsEpStalled(void *InstancePtr, u8 Epnum, u8 Dir); +void EpClearStall(void *InstancePtr, u8 Epnum, u8 Dir); +s32 EpBufferSend(void *InstancePtr, u8 UsbEp, + u8 *BufferPtr, u32 BufferLen); +s32 EpBufferRecv(void *InstancePtr, u8 UsbEp, + u8 *BufferPtr, u32 Length); +void EpSetStall(void *InstancePtr, u8 Epnum, u8 Dir); +void SetBits(void *InstancePtr, u32 TestSel); +s32 SetDeviceAddress(void *InstancePtr, u16 Addr); +s32 SetU1SleepTimeout(void *InstancePtr, u8 Sleep); +s32 SetU2SleepTimeout(void *InstancePtr, u8 Sleep); +s32 AcceptU1U2Sleep(void *InstancePtr); +s32 U1SleepEnable(void *InstancePtr); +s32 U2SleepEnable(void *InstancePtr); +s32 U1SleepDisable(void *InstancePtr); +s32 U2SleepDisable(void *InstancePtr); +s32 EpEnable(void *InstancePtr, u8 UsbEpNum, u8 Dir, u16 Maxsize, u8 Type); +s32 EpDisable(void *InstancePtr, u8 UsbEpNum, u8 Dir); +void Usb_SetSpeed(void *InstancePtr, u32 Speed); +s32 IsSuperSpeed(struct Usb_DevData *InstancePtr); +void SetConfigDone(void *InstancePtr, u8 Flag); +u8 GetConfigDone(void *InstancePtr); +void Ep0StallRestart(void *InstancePtr); +void SetEpInterval(void *InstancePtr, u8 UsbEpNum, u8 Dir, u32 Interval); +void StopTransfer(void *InstancePtr, u8 EpNum, u8 Dir); +s32 StreamOn(void *InstancePtr, u8 EpNum, u8 Dir, u8 *BufferPtr); +void StreamOff(void *InstancePtr, u8 EpNum, u8 Dir); + +#endif /* End of protection macro. */ +/** @} */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_1/src/xusbpsu.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_4/src/xusbpsu.c similarity index 95% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_1/src/xusbpsu.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_4/src/xusbpsu.c index c39d11a2f..245fba272 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_1/src/xusbpsu.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_4/src/xusbpsu.c @@ -33,7 +33,7 @@ /** * * @file xusbpsu.c -* @addtogroup usbpsu_v1_0 +* @addtogroup usbpsu_v1_3 * @{ * * 
@@ -44,14 +44,16 @@
 * ----- -----  -------- -----------------------------------------------------
 * 1.0   sg    06/16/16 First release
 * 1.1   sg    10/24/16 Added new function XUsbPsu_IsSuperSpeed
-*
+* 1.4	bk    12/01/18 Modify USBPSU driver code to fit USB common example code
+*		       for all USB IPs.
+*	myk   12/01/18 Added hibernation support for device mode
 *
* *****************************************************************************/ /***************************** Include Files ********************************/ -#include "xusbpsu.h" +#include "xusb_wrapper.h" /************************** Constant Definitions *****************************/ @@ -226,19 +228,20 @@ void XUsbPsu_PhyReset(struct XUsbPsu *InstancePtr) ******************************************************************************/ void XUsbPsu_EventBuffersSetup(struct XUsbPsu *InstancePtr) { - struct XUsbPsu_EvtBuffer *Evt; + struct XUsbPsu_EvtBuffer *Evt; Xil_AssertVoid(InstancePtr != NULL); Evt = &InstancePtr->Evt; Evt->BuffAddr = (void *)InstancePtr->EventBuffer; + Evt->Offset = 0; XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTADRLO(0), - (UINTPTR)InstancePtr->EventBuffer); + (UINTPTR)InstancePtr->EventBuffer); XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTADRHI(0), - ((UINTPTR)(InstancePtr->EventBuffer) >> 16U) >> 16U); + ((UINTPTR)(InstancePtr->EventBuffer) >> 16U) >> 16U); XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTSIZ(0), - XUSBPSU_GEVNTSIZ_SIZE(sizeof(InstancePtr->EventBuffer))); + XUSBPSU_GEVNTSIZ_SIZE(sizeof(InstancePtr->EventBuffer))); XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTCOUNT(0), 0); } @@ -321,9 +324,9 @@ s32 XUsbPsu_CoreInit(struct XUsbPsu *InstancePtr) XUsbPsu_PhyReset(InstancePtr); RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GCTL); - RegVal &= ~XUSBPSU_GCTL_SCALEDOWN_MASK; - RegVal &= ~XUSBPSU_GCTL_DISSCRAMBLE; - RegVal |= XUSBPSU_GCTL_U2EXIT_LFPS; + RegVal &= ~XUSBPSU_GCTL_SCALEDOWN_MASK; + RegVal &= ~XUSBPSU_GCTL_DISSCRAMBLE; + RegVal |= XUSBPSU_GCTL_U2EXIT_LFPS; Hwparams1 = XUsbPsu_ReadHwParams(InstancePtr, 1U); @@ -333,7 +336,11 @@ s32 XUsbPsu_CoreInit(struct XUsbPsu *InstancePtr) break; case XUSBPSU_GHWPARAMS1_EN_PWROPT_HIB: - /* enable hibernation here */ + /* enable hibernation here */ +#ifdef XUSBPSU_HIBERNATION_ENABLE + RegVal |= XUSBPSU_GCTL_GBLHIBERNATIONEN; + InstancePtr->HasHibernation = 1; +#endif break; default: @@ -343,6 +350,11 @@ s32 XUsbPsu_CoreInit(struct XUsbPsu *InstancePtr) XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GCTL, RegVal); +#ifdef XUSBPSU_HIBERNATION_ENABLE + if (InstancePtr->HasHibernation) + XUsbPsu_InitHibernation(InstancePtr); +#endif + return XST_SUCCESS; } @@ -441,7 +453,7 @@ void XUsbPsu_DisableIntr(struct XUsbPsu *InstancePtr, u32 Mask) s32 XUsbPsu_CfgInitialize(struct XUsbPsu *InstancePtr, XUsbPsu_Config *ConfigPtr, u32 BaseAddress) { - int Status; + s32 Status; u32 RegVal; @@ -471,10 +483,10 @@ s32 XUsbPsu_CfgInitialize(struct XUsbPsu *InstancePtr, XUsbPsu_SetMode(InstancePtr, XUSBPSU_GCTL_PRTCAP_DEVICE); - /* - * Setting to max speed to support SS and HS - */ - XUsbPsu_SetSpeed(InstancePtr, XUSBPSU_DCFG_SUPERSPEED); + /* + * Setting to max speed to support SS and HS + */ + XUsbPsu_SetSpeed(InstancePtr, XUSBPSU_DCFG_SUPERSPEED); (void)XUsbPsu_SetDeviceAddress(InstancePtr, 0U); @@ -694,7 +706,7 @@ s32 XUsbPsu_SetDeviceAddress(struct XUsbPsu *InstancePtr, u16 Addr) Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(Addr <= 127U); - if (InstancePtr->State == XUSBPSU_STATE_CONFIGURED) { + if (InstancePtr->AppData->State == XUSBPSU_STATE_CONFIGURED) { return XST_FAILURE; } @@ -704,30 +716,10 @@ s32 XUsbPsu_SetDeviceAddress(struct XUsbPsu *InstancePtr, u16 Addr) XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCFG, RegVal); if (Addr) { - InstancePtr->State = XUSBPSU_STATE_ADDRESS; + InstancePtr->AppData->State = XUSBPSU_STATE_ADDRESS; } else { - InstancePtr->State = XUSBPSU_STATE_DEFAULT; - } - - return XST_SUCCESS; -} - -/****************************************************************************/ -/** -* Sets speed of the Core for connecting to Host -* -* @param InstancePtr is a pointer to the XUsbPsu instance. -* -* @return XST_SUCCESS else XST_FAILURE -* -* @note None. -* -*****************************************************************************/ -s32 XUsbPsu_IsSuperSpeed(struct XUsbPsu *InstancePtr) -{ - if (InstancePtr->Speed != XUSBPSU_SPEED_SUPER) { - return XST_FAILURE; + InstancePtr->AppData->State = XUSBPSU_STATE_DEFAULT; } return XST_SUCCESS; diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_4/src/xusbpsu.h similarity index 78% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_4/src/xusbpsu.h index a1366487b..2d1498ac1 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_4/src/xusbpsu.h @@ -33,7 +33,7 @@ /** * * @file xusbpsu.h -* @addtogroup usbpsu_v1_0 +* @addtogroup usbpsu_v1_3 * @{ * @details * @@ -46,6 +46,22 @@ * 1.0 sg 06/06/16 First release * 1.1 sg 10/24/16 Update for backward compatability * Added XUsbPsu_IsSuperSpeed function in xusbpsu.c +* 1.2 mn 01/20/17 removed unnecessary declaration of +* XUsbPsu_SetConfiguration in xusbpsu.h +* 1.2 mn 01/30/17 Corrected InstancePtr->UnalignedTx with +* Ept->UnalignedTx in xusbpsu_controltransfers.c +* 1.2 mus 02/10/17 Updated data structures to fix compilation errors for IAR +* compiler +* ms 03/17/17 Added readme.txt file in examples folder for doxygen +* generation. +* ms 04/10/17 Modified filename tag to include the file in doxygen +* examples. +* 1.4 bk 12/01/18 Modify USBPSU driver code to fit USB common example code +* for all USB IPs. +* myk 12/01/18 Added hibernation support for device mode +* vak 22/01/18 Added changes for supporting microblaze platform +* vak 13/03/18 Moved the setup interrupt system calls from driver to +* example. * * * @@ -58,17 +74,22 @@ extern "C" { #endif /***************************** Include Files ********************************/ + +/* Enable XUSBPSU_HIBERNATION_ENABLE to enable hibernation */ +//#define XUSBPSU_HIBERNATION_ENABLE 1 + #include "xparameters.h" #include "xil_types.h" #include "xil_assert.h" #include "xstatus.h" #include "xusbpsu_hw.h" #include "xil_io.h" + /* * The header sleep.h and API usleep() can only be used with an arm design. * MB_Sleep() is used for microblaze design. */ -#if defined (__arm__) || defined (__aarch64__) +#if defined (__arm__) || defined (__aarch64__) || (__ICCARM__) #include "sleep.h" #endif @@ -79,16 +100,19 @@ extern "C" { /************************** Constant Definitions ****************************/ +#define NO_OF_TRB_PER_EP 2 + +#ifdef PLATFORM_ZYNQMP #define ALIGNMENT_CACHELINE __attribute__ ((aligned(64))) +#else +#define ALIGNMENT_CACHELINE __attribute__ ((aligned(32))) +#endif #define XUSBPSU_PHY_TIMEOUT 5000U /* in micro seconds */ #define XUSBPSU_EP_DIR_IN 1U #define XUSBPSU_EP_DIR_OUT 0U -#define XUSBPSU_ENDPOINT_NUMBER_MASK 0x0f /* in bEndpointAddress */ -#define XUSBPSU_ENDPOINT_DIR_MASK 0x80 - #define XUSBPSU_ENDPOINT_XFERTYPE_MASK 0x03 /* in bmAttributes */ #define XUSBPSU_ENDPOINT_XFER_CONTROL 0U #define XUSBPSU_ENDPOINT_XFER_ISOC 1U @@ -253,15 +277,6 @@ typedef enum { /**************************** Type Definitions ******************************/ -/** - * This typedef contains configuration information for the XUSBPSU - * device. - */ -typedef struct { - u16 DeviceId; /**< Unique ID of controller */ - u32 BaseAddress; /**< Core register base address */ -} XUsbPsu_Config; - /** * Software Event buffer representation */ @@ -275,13 +290,20 @@ struct XUsbPsu_EvtBuffer { /** * Transfer Request Block - Hardware format */ +#if defined (__ICCARM__) +#pragma pack(push, 1) +#endif struct XUsbPsu_Trb { u32 BufferPtrLow; u32 BufferPtrHigh; u32 Size; u32 Ctrl; +#if defined (__ICCARM__) +}; +#pragma pack(pop) +#else } __attribute__((packed)); - +#endif /* * Endpoint Parameters @@ -295,13 +317,21 @@ struct XUsbPsu_EpParams { /** * USB Standard Control Request */ +#if defined (__ICCARM__) +#pragma pack(push, 1) +#endif typedef struct { u8 bRequestType; u8 bRequest; u16 wValue; u16 wIndex; u16 wLength; +#if defined (__ICCARM__) +}SetupPacket; +#pragma pack(pop) +#else } __attribute__ ((packed)) SetupPacket; +#endif /** * Endpoint representation @@ -312,11 +342,22 @@ struct XUsbPsu_Ep { * when data is sent for IN Ep * and received for OUT Ep */ - struct XUsbPsu_Trb EpTrb ALIGNMENT_CACHELINE;/**< TRB used by endpoint */ +#if defined (__ICCARM__) + #pragma data_alignment = 64 + struct XUsbPsu_Trb EpTrb[NO_OF_TRB_PER_EP + 1]; /**< One extra Trb is for Link Trb */ + #pragma data_alignment = 4 +#else + struct XUsbPsu_Trb EpTrb[NO_OF_TRB_PER_EP + 1] ALIGNMENT_CACHELINE;/**< TRB used by endpoint */ +#endif u32 EpStatus; /**< Flags to represent Endpoint status */ + u32 EpSavedState; /**< Endpoint status saved at the time of hibernation */ u32 RequestedBytes; /**< RequestedBytes for transfer */ u32 BytesTxed; /**< Actual Bytes transferred */ + u32 Interval; /**< Data transfer service interval */ + u32 TrbEnqueue; + u32 TrbDequeue; u16 MaxSize; /**< Size of endpoint */ + u16 CurUf; /**< current microframe */ u8 *BufferPtr; /**< Buffer location */ u8 ResourceIndex; /**< Resource Index assigned to * Endpoint by core @@ -330,13 +371,39 @@ struct XUsbPsu_Ep { u8 UnalignedTx; }; +/** + * This typedef contains configuration information for the USB + * device. + */ +typedef struct { + u16 DeviceId; /**< Unique ID of controller */ + u32 BaseAddress; /**< Core register base address */ + u8 IsCacheCoherent; /**< Describes whether Cache Coherent or not */ +} XUsbPsu_Config; + +typedef XUsbPsu_Config Usb_Config; + +struct Usb_DevData { + u8 Speed; + u8 State; + + void *PrivateData; +}; + /** * USB Device Controller representation */ struct XUsbPsu { +#if defined (__ICCARM__) + #pragma data_alignment = 64 + SetupPacket SetupData; + struct XUsbPsu_Trb Ep0_Trb; + #pragma data_alignment = 4 +#else SetupPacket SetupData ALIGNMENT_CACHELINE; /**< Setup Packet buffer */ struct XUsbPsu_Trb Ep0_Trb ALIGNMENT_CACHELINE; +#endif /**< TRB for control transfers */ XUsbPsu_Config *ConfigPtr; /**< Configuration info pointer */ struct XUsbPsu_Ep eps[XUSBPSU_ENDPOINTS_NUM]; /**< Endpoints */ @@ -345,32 +412,48 @@ struct XUsbPsu { u32 BaseAddress; /**< Core register base address */ u32 DevDescSize; u32 ConfigDescSize; - void (*Chapter9)(struct XUsbPsu *, SetupPacket *); - void (*ClassHandler)(struct XUsbPsu *, SetupPacket *); + struct Usb_DevData *AppData; + void (*Chapter9)(struct Usb_DevData *, SetupPacket *); + void (*ResetIntrHandler)(struct Usb_DevData *); + void (*DisconnectIntrHandler)(struct Usb_DevData *); void *DevDesc; void *ConfigDesc; +#if defined(__ICCARM__) + #pragma data_alignment = XUSBPSU_EVENT_BUFFERS_SIZE + u8 EventBuffer[XUSBPSU_EVENT_BUFFERS_SIZE]; + #pragma data_alignment = 4 +#else u8 EventBuffer[XUSBPSU_EVENT_BUFFERS_SIZE] __attribute__((aligned(XUSBPSU_EVENT_BUFFERS_SIZE))); +#endif u8 NumOutEps; u8 NumInEps; u8 ControlDir; u8 IsInTestMode; u8 TestMode; - u8 Speed; - u8 State; u8 Ep0State; u8 LinkState; u8 UnalignedTx; u8 IsConfigDone; u8 IsThreeStage; + u8 IsHibernated; /**< Hibernated state */ + u8 HasHibernation; /**< Has hibernation support */ + void *data_ptr; /* pointer for storing applications data */ }; +#if defined (__ICCARM__) +#pragma pack(push, 1) +#endif struct XUsbPsu_Event_Type { u32 Is_DevEvt:1; u32 Type:7; u32 Reserved8_31:24; +#if defined (__ICCARM__) +}; +#pragma pack(pop) +#else } __attribute__((packed)); - +#endif /** * struct XUsbPsu_event_depvt - Device Endpoint Events * @Is_EpEvt: indicates this is an endpoint event @@ -390,6 +473,9 @@ struct XUsbPsu_Event_Type { * @Parameters: Parameters of the current event. Refer to databook for * more information. */ +#if defined (__ICCARM__) +#pragma pack(push, 1) +#endif struct XUsbPsu_Event_Epevt { u32 Is_EpEvt:1; u32 Epnumber:5; @@ -397,8 +483,12 @@ struct XUsbPsu_Event_Epevt { u32 Reserved11_10:2; u32 Status:4; u32 Parameters:16; +#if defined (__ICCARM__) +}; +#pragma pack(pop) +#else } __attribute__((packed)); - +#endif /** * struct XUsbPsu_event_devt - Device Events * @Is_DevEvt: indicates this is a non-endpoint event @@ -421,6 +511,9 @@ struct XUsbPsu_Event_Epevt { * @Event_Info: Information about this event * @Reserved31_25: Reserved, not used */ +#if defined (__ICCARM__) +#pragma pack(push, 1) +#endif struct XUsbPsu_Event_Devt { u32 Is_DevEvt:1; u32 Device_Event:7; @@ -428,8 +521,12 @@ struct XUsbPsu_Event_Devt { u32 Reserved15_12:4; u32 Event_Info:9; u32 Reserved31_25:7; +#if defined (__ICCARM__) +}; +#pragma pack(pop) +#else } __attribute__((packed)); - +#endif /** * struct XUsbPsu_event_gevt - Other Core Events * @one_bit: indicates this is a non-endpoint event (not used) @@ -437,13 +534,20 @@ struct XUsbPsu_Event_Devt { * @phy_port_number: self-explanatory * @reserved31_12: Reserved, not used. */ +#if defined (__ICCARM__) +#pragma pack(push, 1) +#endif struct XUsbPsu_Event_Gevt { u32 Is_GlobalEvt:1; u32 Device_Event:7; u32 Phy_Port_Number:4; u32 Reserved31_12:20; +#if defined (__ICCARM__) +}; +#pragma pack(pop) +#else } __attribute__((packed)); - +#endif /** * union XUsbPsu_event - representation of Event Buffer contents * @raw: raw 32-bit event @@ -461,16 +565,22 @@ union XUsbPsu_Event { }; /***************** Macros (Inline Functions) Definitions *********************/ - +#if defined (__ICCARM__) +#define IS_ALIGNED(x, a) (((x) & ((u32)(a) - 1)) == 0U) +#else #define IS_ALIGNED(x, a) (((x) & ((typeof(x))(a) - 1)) == 0U) +#endif +#if defined (__ICCARM__) +#define roundup(x, y) (((((x) + (u32)(y - 1)) / (u32)y) * (u32)y)) + +#else #define roundup(x, y) ( \ -{ \ - const typeof(y) y__ = (y); \ - (((x) + (u32)(y__ - 1)) / (u32)y__) * (u32)y__; \ -} \ + (((x) + (u32)((const typeof(y))y - 1)) / \ + (u32)((const typeof(y))y)) * \ + (u32)((const typeof(y))y) \ ) - +#endif #define DECLARE_DEV_DESC(Instance, desc) \ (Instance).DevDesc = &(desc); \ (Instance).DevDescSize = sizeof((desc)) @@ -479,6 +589,32 @@ union XUsbPsu_Event { (Instance).ConfigDesc = &(desc); \ (Instance).ConfigDescSize = sizeof((desc)) +static inline void *XUsbPsu_get_drvdata(struct XUsbPsu *InstancePtr) { + return InstancePtr->data_ptr; +} + +static inline void XUsbPsu_set_drvdata(struct XUsbPsu *InstancePtr, void *data) { + InstancePtr->data_ptr = data; +} + +static inline void XUsbPsu_set_ch9handler( + struct XUsbPsu *InstancePtr, + void (*func)(struct Usb_DevData *, SetupPacket *)) { + InstancePtr->Chapter9 = func; +} + +static inline void XUsbPsu_set_rsthandler( + struct XUsbPsu *InstancePtr, + void (*func)(struct Usb_DevData *)) { + InstancePtr->ResetIntrHandler = func; +} + +static inline void XUsbPsu_set_disconnect( + struct XUsbPsu *InstancePtr, + void (*func)(struct Usb_DevData *)) { + InstancePtr->DisconnectIntrHandler = func; +} + /************************** Function Prototypes ******************************/ /* @@ -510,7 +646,6 @@ s32 XUsbPsu_SendGenericCmd(struct XUsbPsu *InstancePtr, s32 Cmd, u32 Param); void XUsbPsu_SetSpeed(struct XUsbPsu *InstancePtr, u32 Speed); s32 XUsbPsu_SetDeviceAddress(struct XUsbPsu *InstancePtr, u16 Addr); -s32 XUsbPsu_IsSuperSpeed(struct XUsbPsu *InstancePtr); s32 XUsbPsu_SetU1SleepTimeout(struct XUsbPsu *InstancePtr, u8 Sleep); s32 XUsbPsu_SetU2SleepTimeout(struct XUsbPsu *InstancePtr, u8 Sleep); s32 XUsbPsu_AcceptU1U2Sleep(struct XUsbPsu *InstancePtr); @@ -525,23 +660,25 @@ s32 XUsbPsu_U2SleepDisable(struct XUsbPsu *InstancePtr); struct XUsbPsu_EpParams *XUsbPsu_GetEpParams(struct XUsbPsu *InstancePtr); u32 XUsbPsu_EpGetTransferIndex(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir); -const char *XUsbPsu_EpCmdString(u8 Cmd); s32 XUsbPsu_SendEpCmd(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir, u32 Cmd, struct XUsbPsu_EpParams *Params); s32 XUsbPsu_StartEpConfig(struct XUsbPsu *InstancePtr, u32 UsbEpNum, u8 Dir); s32 XUsbPsu_SetEpConfig(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir, - u16 Size, u8 Type); + u16 Size, u8 Type, u8 Restore); s32 XUsbPsu_SetXferResource(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir); s32 XUsbPsu_EpEnable(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir, - u16 Maxsize, u8 Type); + u16 Maxsize, u8 Type, u8 Restore); s32 XUsbPsu_EpDisable(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir); s32 XUsbPsu_EnableControlEp(struct XUsbPsu *InstancePtr, u16 Size); void XUsbPsu_InitializeEps(struct XUsbPsu *InstancePtr); -void XUsbPsu_StopTransfer(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir); +void XUsbPsu_StopTransfer(struct XUsbPsu *InstancePtr, u8 UsbEpNum, + u8 Dir, u8 Force); +void XUsbPsu_SaveEndpointState(struct XUsbPsu *InstancePtr, + struct XUsbPsu_Ep *Ept); void XUsbPsu_ClearStalls(struct XUsbPsu *InstancePtr); s32 XUsbPsu_EpBufferSend(struct XUsbPsu *InstancePtr, u8 UsbEp, - u8 *BufferPtr, u32 BufferLen); + u8 *BufferPtr, u32 BufferLen); s32 XUsbPsu_EpBufferRecv(struct XUsbPsu *InstancePtr, u8 UsbEp, u8 *BufferPtr, u32 Length); void XUsbPsu_EpSetStall(struct XUsbPsu *InstancePtr, u8 Epnum, u8 Dir); @@ -551,14 +688,14 @@ void XUsbPsu_SetEpHandler(struct XUsbPsu *InstancePtr, u8 Epnum, s32 XUsbPsu_IsEpStalled(struct XUsbPsu *InstancePtr, u8 Epnum, u8 Dir); void XUsbPsu_EpXferComplete(struct XUsbPsu *InstancePtr, const struct XUsbPsu_Event_Epevt *Event); +void XUsbPsu_EpXferNotReady(struct XUsbPsu *InstancePtr, + const struct XUsbPsu_Event_Epevt *Event); /* * Functions in xusbpsu_controltransfers.c */ s32 XUsbPsu_RecvSetup(struct XUsbPsu *InstancePtr); void XUsbPsu_Ep0StallRestart(struct XUsbPsu *InstancePtr); -s32 XUsbPsu_SetConfiguration(struct XUsbPsu *InstancePtr, - SetupPacket *Ctrl); void XUsbPsu_Ep0DataDone(struct XUsbPsu *InstancePtr, const struct XUsbPsu_Event_Epevt *Event); void XUsbPsu_Ep0StatusDone(struct XUsbPsu *InstancePtr, @@ -595,6 +732,14 @@ void XUsbPsu_EventHandler(struct XUsbPsu *InstancePtr, void XUsbPsu_EventBufferHandler(struct XUsbPsu *InstancePtr); void XUsbPsu_IntrHandler(void *XUsbPsuInstancePtr); +#ifdef XUSBPSU_HIBERNATION_ENABLE +void XUsbPsu_InitHibernation(struct XUsbPsu *InstancePtr); +void Xusbpsu_HibernationIntr(struct XUsbPsu *InstancePtr); +void XUsbPsu_WakeUpIntrHandler(void *XUsbPsuInstancePtr); +void XUsbPsu_WakeupIntr(struct XUsbPsu *InstancePtr); +s32 XUsbPsu_SetupScratchpad(struct XUsbPsu *InstancePtr); +#endif + /* * Functions in xusbpsu_sinit.c */ diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_controltransfers.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_4/src/xusbpsu_controltransfers.c similarity index 90% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_controltransfers.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_4/src/xusbpsu_controltransfers.c index b3a93dc63..19be417fb 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_controltransfers.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_4/src/xusbpsu_controltransfers.c @@ -42,19 +42,20 @@ * Ver Who Date Changes * ----- ---- -------- ------------------------------------------------------- * 1.0 sg 06/06/16 First release +* 1.3 vak 04/03/17 Added CCI support for USB +* 1.4 bk 12/01/18 Modify USBPSU driver code to fit USB common example code +* for all USB IPs. * * * *****************************************************************************/ /***************************** Include Files *********************************/ - -#include "xusbpsu.h" #include "xusbpsu_endpoint.h" -/************************** Constant Definitions *****************************/ +#include "sleep.h" +#include "xusb_wrapper.h" -#define USB_DIR_OUT 0U /* to device */ -#define USB_DIR_IN 0x80U /* to host */ +/************************** Constant Definitions *****************************/ /**************************** Type Definitions *******************************/ @@ -62,10 +63,8 @@ /************************** Function Prototypes ******************************/ - /************************** Variable Definitions *****************************/ - /****************************************************************************/ /** * Initiates DMA on Control Endpoint 0 to receive Setup packet. @@ -92,7 +91,7 @@ s32 XUsbPsu_RecvSetup(struct XUsbPsu *InstancePtr) /* Setup packet always on EP0 */ Ept = &InstancePtr->eps[0]; if ((Ept->EpStatus & XUSBPSU_EP_BUSY) != 0U) { - return XST_FAILURE; + return (s32)XST_FAILURE; } TrbPtr = &InstancePtr->Ep0_Trb; @@ -107,7 +106,10 @@ s32 XUsbPsu_RecvSetup(struct XUsbPsu *InstancePtr) | XUSBPSU_TRB_CTRL_IOC | XUSBPSU_TRB_CTRL_ISP_IMI); - Xil_DCacheFlushRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb)); + if (InstancePtr->ConfigPtr->IsCacheCoherent == 0) { + Xil_DCacheFlushRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb)); + Xil_DCacheFlushRange((UINTPTR)&InstancePtr->SetupData, sizeof(SetupPacket)); + } Params->Param0 = 0U; Params->Param1 = (UINTPTR)TrbPtr; @@ -117,7 +119,7 @@ s32 XUsbPsu_RecvSetup(struct XUsbPsu *InstancePtr) Ret = XUsbPsu_SendEpCmd(InstancePtr, 0U, XUSBPSU_EP_DIR_OUT, XUSBPSU_DEPCMD_STARTTRANSFER, Params); if (Ret != XST_SUCCESS) { - return XST_FAILURE; + return (s32)XST_FAILURE; } Ept->EpStatus |= XUSBPSU_EP_BUSY; @@ -187,7 +189,8 @@ void XUsbPsu_Ep0DataDone(struct XUsbPsu *InstancePtr, Ept = &InstancePtr->eps[Epnum]; TrbPtr = &InstancePtr->Ep0_Trb; - Xil_DCacheInvalidateRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb)); + if (InstancePtr->ConfigPtr->IsCacheCoherent == 0) + Xil_DCacheInvalidateRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb)); Status = XUSBPSU_TRB_SIZE_TRBSTS(TrbPtr->Size); if (Status == XUSBPSU_TRBSTS_SETUP_PENDING) { @@ -201,21 +204,22 @@ void XUsbPsu_Ep0DataDone(struct XUsbPsu *InstancePtr, } else { if (Dir == XUSBPSU_EP_DIR_IN) { Ept->BytesTxed = Ept->RequestedBytes - Length; - } else if (Dir == XUSBPSU_EP_DIR_OUT) { - if (Ept->UnalignedTx == 1U) { - Ept->BytesTxed = Ept->RequestedBytes; - Ept->UnalignedTx = 0U; + } else { + if ((Dir == XUSBPSU_EP_DIR_OUT) && (Ept->UnalignedTx == 1U)) { + Ept->BytesTxed = Ept->RequestedBytes; + Ept->UnalignedTx = 0U; } } } if (Dir == XUSBPSU_EP_DIR_OUT) { /* Invalidate Cache */ - Xil_DCacheInvalidateRange((INTPTR)Ept->BufferPtr, Ept->BytesTxed); + if (InstancePtr->ConfigPtr->IsCacheCoherent == 0) + Xil_DCacheInvalidateRange((INTPTR)Ept->BufferPtr, Ept->BytesTxed); } if (Ept->Handler != NULL) { - Ept->Handler(InstancePtr, Ept->RequestedBytes, Ept->BytesTxed); + Ept->Handler(InstancePtr->AppData, Ept->RequestedBytes, Ept->BytesTxed); } } @@ -251,7 +255,8 @@ void XUsbPsu_Ep0StatusDone(struct XUsbPsu *InstancePtr, return; } } - Xil_DCacheInvalidateRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb)); + if (InstancePtr->ConfigPtr->IsCacheCoherent == 0) + Xil_DCacheInvalidateRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb)); (void)XUsbPsu_RecvSetup(InstancePtr); } @@ -286,8 +291,10 @@ void XUsbPsu_Ep0XferComplete(struct XUsbPsu *InstancePtr, switch (InstancePtr->Ep0State) { case XUSBPSU_EP0_SETUP_PHASE: - Xil_DCacheInvalidateRange((INTPTR)&InstancePtr->SetupData, + if (InstancePtr->ConfigPtr->IsCacheCoherent == 0) { + Xil_DCacheInvalidateRange((INTPTR)&InstancePtr->SetupData, sizeof(InstancePtr->SetupData)); + } Length = Ctrl->wLength; if (Length == 0U) { InstancePtr->IsThreeStage = 0U; @@ -300,7 +307,7 @@ void XUsbPsu_Ep0XferComplete(struct XUsbPsu *InstancePtr, Xil_AssertVoid(InstancePtr->Chapter9 != NULL); - InstancePtr->Chapter9(InstancePtr, + InstancePtr->Chapter9(InstancePtr->AppData, &InstancePtr->SetupData); break; @@ -347,7 +354,7 @@ s32 XUsbPsu_Ep0StartStatus(struct XUsbPsu *InstancePtr, Params = XUsbPsu_GetEpParams(InstancePtr); Xil_AssertNonvoid(Params != NULL); if ((Ept->EpStatus & XUSBPSU_EP_BUSY) != 0U) { - return XST_FAILURE; + return (s32)XST_FAILURE; } Type = (InstancePtr->IsThreeStage != 0U) ? XUSBPSU_TRBCTL_CONTROL_STATUS3 @@ -364,7 +371,9 @@ s32 XUsbPsu_Ep0StartStatus(struct XUsbPsu *InstancePtr, | XUSBPSU_TRB_CTRL_IOC | XUSBPSU_TRB_CTRL_ISP_IMI); - Xil_DCacheFlushRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb)); + if (InstancePtr->ConfigPtr->IsCacheCoherent == 0) { + Xil_DCacheFlushRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb)); + } Params->Param0 = 0U; Params->Param1 = (UINTPTR)TrbPtr; @@ -380,7 +389,7 @@ s32 XUsbPsu_Ep0StartStatus(struct XUsbPsu *InstancePtr, Ret = XUsbPsu_SendEpCmd(InstancePtr, 0U, Dir, XUSBPSU_DEPCMD_STARTTRANSFER, Params); if (Ret != XST_SUCCESS) { - return XST_FAILURE; + return (s32)XST_FAILURE; } Ept->EpStatus |= XUSBPSU_EP_BUSY; @@ -543,7 +552,7 @@ s32 XUsbPsu_Ep0Send(struct XUsbPsu *InstancePtr, u8 *BufferPtr, u32 BufferLen) Xil_AssertNonvoid(Params != NULL); if ((Ept->EpStatus & XUSBPSU_EP_BUSY) != 0U) { - return XST_FAILURE; + return (s32)XST_FAILURE; } Ept->RequestedBytes = BufferLen; @@ -565,15 +574,17 @@ s32 XUsbPsu_Ep0Send(struct XUsbPsu *InstancePtr, u8 *BufferPtr, u32 BufferLen) Params->Param0 = 0U; Params->Param1 = (UINTPTR)TrbPtr; - Xil_DCacheFlushRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb)); - Xil_DCacheFlushRange((INTPTR)BufferPtr, BufferLen); + if (InstancePtr->ConfigPtr->IsCacheCoherent == 0) { + Xil_DCacheFlushRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb)); + Xil_DCacheFlushRange((INTPTR)BufferPtr, BufferLen); + } InstancePtr->Ep0State = XUSBPSU_EP0_DATA_PHASE; Ret = XUsbPsu_SendEpCmd(InstancePtr, 0U, XUSBPSU_EP_DIR_IN, XUSBPSU_DEPCMD_STARTTRANSFER, Params); if (Ret != XST_SUCCESS) { - return XST_FAILURE; + return (s32)XST_FAILURE; } Ept->EpStatus |= XUSBPSU_EP_BUSY; @@ -612,7 +623,7 @@ s32 XUsbPsu_Ep0Recv(struct XUsbPsu *InstancePtr, u8 *BufferPtr, u32 Length) Xil_AssertNonvoid(Params != NULL); if ((Ept->EpStatus & XUSBPSU_EP_BUSY) != 0U) { - return XST_FAILURE; + return (s32)XST_FAILURE; } Ept->RequestedBytes = Length; @@ -627,7 +638,7 @@ s32 XUsbPsu_Ep0Recv(struct XUsbPsu *InstancePtr, u8 *BufferPtr, u32 Length) */ if (!IS_ALIGNED(Length, Ept->MaxSize)) { Size = (u32)roundup(Length, Ept->MaxSize); - InstancePtr->UnalignedTx = 1U; + Ept->UnalignedTx = 1U; } TrbPtr = &InstancePtr->Ep0_Trb; @@ -642,8 +653,10 @@ s32 XUsbPsu_Ep0Recv(struct XUsbPsu *InstancePtr, u8 *BufferPtr, u32 Length) | XUSBPSU_TRB_CTRL_IOC | XUSBPSU_TRB_CTRL_ISP_IMI); - Xil_DCacheFlushRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb)); - Xil_DCacheInvalidateRange((INTPTR)BufferPtr, Length); + if (InstancePtr->ConfigPtr->IsCacheCoherent == 0) { + Xil_DCacheFlushRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb)); + Xil_DCacheInvalidateRange((INTPTR)BufferPtr, Length); + } Params->Param0 = 0U; Params->Param1 = (UINTPTR)TrbPtr; @@ -653,7 +666,7 @@ s32 XUsbPsu_Ep0Recv(struct XUsbPsu *InstancePtr, u8 *BufferPtr, u32 Length) Ret = XUsbPsu_SendEpCmd(InstancePtr, 0U, XUSBPSU_EP_DIR_OUT, XUSBPSU_DEPCMD_STARTTRANSFER, Params); if (Ret != XST_SUCCESS) { - return XST_FAILURE; + return (s32)XST_FAILURE; } Ept->EpStatus |= XUSBPSU_EP_BUSY; diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_1/src/xusbpsu_endpoint.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_4/src/xusbpsu_endpoint.c similarity index 72% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_1/src/xusbpsu_endpoint.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_4/src/xusbpsu_endpoint.c index 41368e526..42e4108c6 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_1/src/xusbpsu_endpoint.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_4/src/xusbpsu_endpoint.c @@ -33,7 +33,7 @@ /** * * @file xusbpsu_endpoint.c -* @addtogroup usbpsu_v1_0 +* @addtogroup usbpsu_v1_3 * @{ * * @@ -43,32 +43,27 @@ * Ver Who Date Changes * ----- ---- -------- ------------------------------------------------------- * 1.0 sg 06/06/16 First release -* +* 1.3 vak 04/03/17 Added CCI support for USB +* 1.4 bk 12/01/18 Modify USBPSU driver code to fit USB common example code +* for all USB IPs +* myk 12/01/18 Added hibernation support for device mode * * *****************************************************************************/ /***************************** Include Files *********************************/ - -#include "xusbpsu.h" #include "xusbpsu_endpoint.h" -/************************** Constant Definitions *****************************/ +/************************** Constant Definitions *****************************/ /**************************** Type Definitions *******************************/ -/* return Physical EP number as dwc3 mapping */ -#define PhysicalEp(epnum, direction) (((epnum) << 1 ) | (direction)) - /***************** Macros (Inline Functions) Definitions *********************/ - /************************** Function Prototypes ******************************/ - /************************** Variable Definitions *****************************/ - /****************************************************************************/ /** * Returns zeroed parameters to be used by Endpoint commands @@ -233,6 +228,8 @@ s32 XUsbPsu_StartEpConfig(struct XUsbPsu *InstancePtr, u32 UsbEpNum, u8 Dir) * @param Dir is direction of endpoint - XUSBPSU_EP_DIR_IN/XUSBPSU_EP_DIR_OUT. * @param Size is size of Endpoint size. * @param Type is Endpoint type Control/Bulk/Interrupt/Isoc. +* @param Restore should be true if saved state should be restored; +* typically this would be false * * @return XST_SUCCESS else XST_FAILURE. * @@ -240,8 +237,9 @@ s32 XUsbPsu_StartEpConfig(struct XUsbPsu *InstancePtr, u32 UsbEpNum, u8 Dir) * *****************************************************************************/ s32 XUsbPsu_SetEpConfig(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir, - u16 Size, u8 Type) + u16 Size, u8 Type, u8 Restore) { + struct XUsbPsu_Ep *Ept; struct XUsbPsu_EpParams *Params; u8 PhyEpNum; @@ -255,6 +253,7 @@ s32 XUsbPsu_SetEpConfig(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir, Xil_AssertNonvoid(Params != NULL); PhyEpNum = PhysicalEp(UsbEpNum , Dir); + Ept = &InstancePtr->eps[PhyEpNum]; Params->Param0 = XUSBPSU_DEPCFG_EP_TYPE(Type) | XUSBPSU_DEPCFG_MAX_PACKET_SIZE(Size); @@ -262,11 +261,18 @@ s32 XUsbPsu_SetEpConfig(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir, /* * Set burst size to 1 as recommended */ - Params->Param0 |= XUSBPSU_DEPCFG_BURST_SIZE(1); + if (InstancePtr->AppData->Speed == XUSBPSU_SPEED_SUPER) { + Params->Param0 |= XUSBPSU_DEPCFG_BURST_SIZE(1); + } Params->Param1 = XUSBPSU_DEPCFG_XFER_COMPLETE_EN | XUSBPSU_DEPCFG_XFER_NOT_READY_EN; + if (Restore) { + Params->Param0 |= XUSBPSU_DEPCFG_ACTION_RESTORE; + Params->Param2 = Ept->EpSavedState; + } + /* * We are doing 1:1 mapping for endpoints, meaning * Physical Endpoints 2 maps to Logical Endpoint 2 and @@ -279,6 +285,11 @@ s32 XUsbPsu_SetEpConfig(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir, Params->Param0 |= XUSBPSU_DEPCFG_FIFO_NUMBER((u32)PhyEpNum >> 1); } + if (Ept->Type == XUSBPSU_ENDPOINT_XFER_ISOC) { + Params->Param1 |= XUSBPSU_DEPCFG_BINTERVAL_M1(Ept->Interval - 1); + Params->Param1 |= XUSBPSU_DEPCFG_XFER_IN_PROGRESS_EN; + } + return XUsbPsu_SendEpCmd(InstancePtr, UsbEpNum, Dir, XUSBPSU_DEPCMD_SETEPCONFIG, Params); } @@ -325,6 +336,8 @@ s32 XUsbPsu_SetXferResource(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir) * @param Dir is direction of endpoint - XUSBPSU_EP_DIR_IN/XUSBPSU_EP_DIR_OUT. * @param Maxsize is size of Endpoint size. * @param Type is Endpoint type Control/Bulk/Interrupt/Isoc. +* @param Restore should be true if saved state should be restored; +* typically this would be false * * @return XST_SUCCESS else XST_FAILURE. * @@ -332,9 +345,10 @@ s32 XUsbPsu_SetXferResource(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir) * ****************************************************************************/ s32 XUsbPsu_EpEnable(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir, - u16 Maxsize, u8 Type) + u16 Maxsize, u8 Type, u8 Restore) { struct XUsbPsu_Ep *Ept; + struct XUsbPsu_Trb *TrbStHw, *TrbLink; u32 RegVal; s32 Ret = (s32)XST_FAILURE; u32 PhyEpNum; @@ -353,20 +367,28 @@ s32 XUsbPsu_EpEnable(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir, Ept->Type = Type; Ept->MaxSize = Maxsize; Ept->PhyEpNum = (u8)PhyEpNum; + Ept->CurUf = 0; + if (!InstancePtr->IsHibernated) { + Ept->TrbEnqueue = 0; + Ept->TrbDequeue = 0; + } - if ((Ept->EpStatus & XUSBPSU_EP_ENABLED) == 0U) { + if (((Ept->EpStatus & XUSBPSU_EP_ENABLED) == 0U) + || (InstancePtr->IsHibernated)) { Ret = XUsbPsu_StartEpConfig(InstancePtr, UsbEpNum, Dir); if (Ret != 0) { return Ret; } } - Ret = XUsbPsu_SetEpConfig(InstancePtr, UsbEpNum, Dir, Maxsize, Type); + Ret = XUsbPsu_SetEpConfig(InstancePtr, UsbEpNum, Dir, Maxsize, + Type, Restore); if (Ret != 0) { return Ret; } - if ((Ept->EpStatus & XUSBPSU_EP_ENABLED) == 0U) { + if (((Ept->EpStatus & XUSBPSU_EP_ENABLED) == 0U) + || (InstancePtr->IsHibernated)) { Ret = XUsbPsu_SetXferResource(InstancePtr, UsbEpNum, Dir); if (Ret != 0) { return Ret; @@ -377,6 +399,18 @@ s32 XUsbPsu_EpEnable(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir, RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DALEPENA); RegVal |= XUSBPSU_DALEPENA_EP(Ept->PhyEpNum); XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DALEPENA, RegVal); + + /* Following code is only applicable for ISO XFER */ + TrbStHw = &Ept->EpTrb[0]; + + /* Link TRB. The HWO bit is never reset */ + TrbLink = &Ept->EpTrb[NO_OF_TRB_PER_EP]; + memset(TrbLink, 0x00, sizeof(struct XUsbPsu_Trb)); + + TrbLink->BufferPtrLow = (UINTPTR)TrbStHw; + TrbLink->BufferPtrHigh = ((UINTPTR)TrbStHw >> 16) >> 16; + TrbLink->Ctrl |= XUSBPSU_TRBCTL_LINK_TRB; + TrbLink->Ctrl |= XUSBPSU_TRB_CTRL_HWO; } return XST_SUCCESS; @@ -410,6 +444,10 @@ s32 XUsbPsu_EpDisable(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir) PhyEpNum = PhysicalEp(UsbEpNum , Dir); Ept = &InstancePtr->eps[PhyEpNum]; + /* make sure HW endpoint isn't stalled */ + if (Ept->EpStatus & XUSBPSU_EP_STALL) + XUsbPsu_EpClearStall(InstancePtr, Ept->UsbEpNum, Ept->Direction); + RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DALEPENA); RegVal &= ~XUSBPSU_DALEPENA_EP(PhyEpNum); XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DALEPENA, RegVal); @@ -417,6 +455,8 @@ s32 XUsbPsu_EpDisable(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir) Ept->Type = 0U; Ept->EpStatus = 0U; Ept->MaxSize = 0U; + Ept->TrbEnqueue = 0U; + Ept->TrbDequeue = 0U; return XST_SUCCESS; } @@ -441,13 +481,13 @@ s32 XUsbPsu_EnableControlEp(struct XUsbPsu *InstancePtr, u16 Size) Xil_AssertNonvoid((Size >= 64U) && (Size <= 512U)); RetVal = XUsbPsu_EpEnable(InstancePtr, 0U, XUSBPSU_EP_DIR_OUT, Size, - XUSBPSU_ENDPOINT_XFER_CONTROL); + XUSBPSU_ENDPOINT_XFER_CONTROL, FALSE); if (RetVal != 0) { return XST_FAILURE; } RetVal = XUsbPsu_EpEnable(InstancePtr, 0U, XUSBPSU_EP_DIR_IN, Size, - XUSBPSU_ENDPOINT_XFER_CONTROL); + XUSBPSU_ENDPOINT_XFER_CONTROL, FALSE); if (RetVal != 0) { return XST_FAILURE; } @@ -479,11 +519,13 @@ void XUsbPsu_InitializeEps(struct XUsbPsu *InstancePtr) Epnum = (i << 1U) | XUSBPSU_EP_DIR_OUT; InstancePtr->eps[Epnum].PhyEpNum = Epnum; InstancePtr->eps[Epnum].Direction = XUSBPSU_EP_DIR_OUT; + InstancePtr->eps[Epnum].ResourceIndex = 0; } for (i = 0U; i < InstancePtr->NumInEps; i++) { Epnum = (i << 1U) | XUSBPSU_EP_DIR_IN; InstancePtr->eps[Epnum].PhyEpNum = Epnum; InstancePtr->eps[Epnum].Direction = XUSBPSU_EP_DIR_IN; + InstancePtr->eps[Epnum].ResourceIndex = 0; } } @@ -494,13 +536,15 @@ void XUsbPsu_InitializeEps(struct XUsbPsu *InstancePtr) * @param InstancePtr is a pointer to the XUsbPsu instance. * @param UsbEpNum is USB endpoint number. * @param Dir is direction of endpoint - XUSBPSU_EP_DIR_IN/XUSBPSU_EP_DIR_OUT. +* @Force Force flag to stop/pause transfer. * * @return None. * * @note None. * ****************************************************************************/ -void XUsbPsu_StopTransfer(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir) +void XUsbPsu_StopTransfer(struct XUsbPsu *InstancePtr, u8 UsbEpNum, + u8 Dir, u8 Force) { struct XUsbPsu_Ep *Ept; struct XUsbPsu_EpParams *Params; @@ -526,15 +570,37 @@ void XUsbPsu_StopTransfer(struct XUsbPsu *InstancePtr, u8 UsbEpNum, u8 Dir) * - Wait 100us */ Cmd = XUSBPSU_DEPCMD_ENDTRANSFER; + Cmd |= Force ? XUSBPSU_DEPCMD_HIPRI_FORCERM : 0; Cmd |= XUSBPSU_DEPCMD_CMDIOC; Cmd |= XUSBPSU_DEPCMD_PARAM(Ept->ResourceIndex); - (void)XUsbPsu_SendEpCmd(InstancePtr, Ept->PhyEpNum, Ept->Direction, + (void)XUsbPsu_SendEpCmd(InstancePtr, Ept->UsbEpNum, Ept->Direction, Cmd, Params); - Ept->ResourceIndex = 0U; + if (Force) + Ept->ResourceIndex = 0U; Ept->EpStatus &= ~XUSBPSU_EP_BUSY; XUsbSleep(100U); } +/****************************************************************************/ +/** +* Query endpoint state and save it in EpSavedState +* +* @param InstancePtr is a pointer to the XUsbPsu instance. +* @param Ept is a pointer to the XUsbPsu pointer structure. +* +* @return None. +* +* @note None. +* +****************************************************************************/ +void XUsbPsu_SaveEndpointState(struct XUsbPsu *InstancePtr, struct XUsbPsu_Ep *Ept) +{ + struct XUsbPsu_EpParams *Params = XUsbPsu_GetEpParams(InstancePtr); + XUsbPsu_SendEpCmd(InstancePtr, Ept->UsbEpNum, Ept->Direction, + XUSBPSU_DEPCMD_GETEPSTATE, Params); + Ept->EpSavedState = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DEPCMDPAR2(Ept->PhyEpNum)); +} + /****************************************************************************/ /** * Clears Stall on all endpoints. @@ -570,7 +636,7 @@ void XUsbPsu_ClearStalls(struct XUsbPsu *InstancePtr) Ept->EpStatus &= ~XUSBPSU_EP_STALL; - (void)XUsbPsu_SendEpCmd(InstancePtr, Ept->PhyEpNum, + (void)XUsbPsu_SendEpCmd(InstancePtr, Ept->UsbEpNum, Ept->Direction, XUSBPSU_DEPCMD_CLEARSTALL, Params); } @@ -594,6 +660,7 @@ s32 XUsbPsu_EpBufferSend(struct XUsbPsu *InstancePtr, u8 UsbEp, u8 *BufferPtr, u32 BufferLen) { u8 PhyEpNum; + u32 cmd; s32 RetVal; struct XUsbPsu_Trb *TrbPtr; struct XUsbPsu_Ep *Ept; @@ -619,35 +686,98 @@ s32 XUsbPsu_EpBufferSend(struct XUsbPsu *InstancePtr, u8 UsbEp, Ept->BytesTxed = 0U; Ept->BufferPtr = BufferPtr; - TrbPtr = &Ept->EpTrb; + TrbPtr = &Ept->EpTrb[Ept->TrbEnqueue]; Xil_AssertNonvoid(TrbPtr != NULL); + Ept->TrbEnqueue++; + if (Ept->TrbEnqueue == NO_OF_TRB_PER_EP) + Ept->TrbEnqueue = 0; TrbPtr->BufferPtrLow = (UINTPTR)BufferPtr; TrbPtr->BufferPtrHigh = ((UINTPTR)BufferPtr >> 16) >> 16; TrbPtr->Size = BufferLen & XUSBPSU_TRB_SIZE_MASK; - TrbPtr->Ctrl = XUSBPSU_TRBCTL_NORMAL; + + switch (Ept->Type) { + case XUSBPSU_ENDPOINT_XFER_ISOC: + /* + * According to DWC3 datasheet, XUSBPSU_TRBCTL_ISOCHRONOUS and + * XUSBPSU_TRBCTL_CHN fields are only set when request has + * scattered list so these fields are not set over here. + */ + TrbPtr->Ctrl = (XUSBPSU_TRBCTL_ISOCHRONOUS_FIRST + | XUSBPSU_TRB_CTRL_CSP); + + break; + case XUSBPSU_ENDPOINT_XFER_INT: + case XUSBPSU_ENDPOINT_XFER_BULK: + TrbPtr->Ctrl = (XUSBPSU_TRBCTL_NORMAL + | XUSBPSU_TRB_CTRL_LST); + + break; + } TrbPtr->Ctrl |= (XUSBPSU_TRB_CTRL_HWO - | XUSBPSU_TRB_CTRL_LST - | XUSBPSU_TRB_CTRL_IOC - | XUSBPSU_TRB_CTRL_ISP_IMI); + | XUSBPSU_TRB_CTRL_IOC + | XUSBPSU_TRB_CTRL_ISP_IMI); - Xil_DCacheFlushRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb)); - Xil_DCacheFlushRange((INTPTR)BufferPtr, BufferLen); + if (InstancePtr->ConfigPtr->IsCacheCoherent == 0) { + Xil_DCacheFlushRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb)); + Xil_DCacheFlushRange((INTPTR)BufferPtr, BufferLen); + } Params = XUsbPsu_GetEpParams(InstancePtr); Xil_AssertNonvoid(Params != NULL); Params->Param0 = 0U; Params->Param1 = (UINTPTR)TrbPtr; + if (Ept->EpStatus & XUSBPSU_EP_BUSY) { + cmd = XUSBPSU_DEPCMD_UPDATETRANSFER; + cmd |= XUSBPSU_DEPCMD_PARAM(Ept->ResourceIndex); + } else { + if (Ept->Type == XUSBPSU_ENDPOINT_XFER_ISOC) { + BufferPtr += BufferLen; + struct XUsbPsu_Trb *TrbTempNext; + TrbTempNext = &Ept->EpTrb[Ept->TrbEnqueue]; + Xil_AssertNonvoid(TrbTempNext != NULL); + + Ept->TrbEnqueue++; + if (Ept->TrbEnqueue == NO_OF_TRB_PER_EP) + Ept->TrbEnqueue = 0; + TrbTempNext->BufferPtrLow = (UINTPTR)BufferPtr; + TrbTempNext->BufferPtrHigh = ((UINTPTR)BufferPtr >> 16) >> 16; + TrbTempNext->Size = BufferLen & XUSBPSU_TRB_SIZE_MASK; + + TrbTempNext->Ctrl = (XUSBPSU_TRBCTL_ISOCHRONOUS_FIRST + | XUSBPSU_TRB_CTRL_CSP + | XUSBPSU_TRB_CTRL_HWO + | XUSBPSU_TRB_CTRL_IOC + | XUSBPSU_TRB_CTRL_ISP_IMI); + + if (InstancePtr->ConfigPtr->IsCacheCoherent == 0) { + Xil_DCacheFlushRange((INTPTR)TrbTempNext, + sizeof(struct XUsbPsu_Trb)); + Xil_DCacheFlushRange((INTPTR)BufferPtr, BufferLen); + } + + } + + cmd = XUSBPSU_DEPCMD_STARTTRANSFER; + cmd |= XUSBPSU_DEPCMD_PARAM(Ept->CurUf); + } + RetVal = XUsbPsu_SendEpCmd(InstancePtr, UsbEp, Ept->Direction, - XUSBPSU_DEPCMD_STARTTRANSFER, Params); + cmd, Params); if (RetVal != XST_SUCCESS) { return XST_FAILURE; } - Ept->ResourceIndex = (u8)XUsbPsu_EpGetTransferIndex(InstancePtr, - Ept->UsbEpNum, - Ept->Direction); + + if (!(Ept->EpStatus & XUSBPSU_EP_BUSY)) { + Ept->ResourceIndex = (u8)XUsbPsu_EpGetTransferIndex(InstancePtr, + Ept->UsbEpNum, + Ept->Direction); + + Ept->EpStatus |= XUSBPSU_EP_BUSY; + } + return XST_SUCCESS; } @@ -656,7 +786,7 @@ s32 XUsbPsu_EpBufferSend(struct XUsbPsu *InstancePtr, u8 UsbEp, * Initiates DMA to receive data on Endpoint from Host. * * @param InstancePtr is a pointer to the XUsbPsu instance. -* @param EpNum is USB endpoint number. +* @param UsbEp is USB endpoint number. * @param BufferPtr is pointer to data. * @param Length is length of data to be received. * @@ -669,7 +799,8 @@ s32 XUsbPsu_EpBufferRecv(struct XUsbPsu *InstancePtr, u8 UsbEp, u8 *BufferPtr, u32 Length) { u8 PhyEpNum; - u32 Size; + u32 cmd; + u32 Size; s32 RetVal; struct XUsbPsu_Trb *TrbPtr; struct XUsbPsu_Ep *Ept; @@ -706,36 +837,100 @@ s32 XUsbPsu_EpBufferRecv(struct XUsbPsu *InstancePtr, u8 UsbEp, Ept->UnalignedTx = 1U; } - TrbPtr = &Ept->EpTrb; + TrbPtr = &Ept->EpTrb[Ept->TrbEnqueue]; Xil_AssertNonvoid(TrbPtr != NULL); + Ept->TrbEnqueue++; + if (Ept->TrbEnqueue == NO_OF_TRB_PER_EP) + Ept->TrbEnqueue = 0; + TrbPtr->BufferPtrLow = (UINTPTR)BufferPtr; TrbPtr->BufferPtrHigh = ((UINTPTR)BufferPtr >> 16) >> 16; TrbPtr->Size = Size; - TrbPtr->Ctrl = XUSBPSU_TRBCTL_NORMAL; + + switch (Ept->Type) { + case XUSBPSU_ENDPOINT_XFER_ISOC: + /* + * According to Linux driver, XUSBPSU_TRBCTL_ISOCHRONOUS and + * XUSBPSU_TRBCTL_CHN fields are only set when request has + * scattered list so these fields are not set over here. + */ + TrbPtr->Ctrl = (XUSBPSU_TRBCTL_ISOCHRONOUS_FIRST + | XUSBPSU_TRB_CTRL_CSP); + + break; + case XUSBPSU_ENDPOINT_XFER_INT: + case XUSBPSU_ENDPOINT_XFER_BULK: + TrbPtr->Ctrl = (XUSBPSU_TRBCTL_NORMAL + | XUSBPSU_TRB_CTRL_LST); + + break; + } TrbPtr->Ctrl |= (XUSBPSU_TRB_CTRL_HWO - | XUSBPSU_TRB_CTRL_LST - | XUSBPSU_TRB_CTRL_IOC - | XUSBPSU_TRB_CTRL_ISP_IMI); + | XUSBPSU_TRB_CTRL_IOC + | XUSBPSU_TRB_CTRL_ISP_IMI); - Xil_DCacheFlushRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb)); - Xil_DCacheInvalidateRange((INTPTR)BufferPtr, Length); + if (InstancePtr->ConfigPtr->IsCacheCoherent == 0) { + Xil_DCacheFlushRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb)); + Xil_DCacheInvalidateRange((INTPTR)BufferPtr, Length); + } Params = XUsbPsu_GetEpParams(InstancePtr); Xil_AssertNonvoid(Params != NULL); Params->Param0 = 0U; Params->Param1 = (UINTPTR)TrbPtr; + if (Ept->EpStatus & XUSBPSU_EP_BUSY) { + cmd = XUSBPSU_DEPCMD_UPDATETRANSFER; + cmd |= XUSBPSU_DEPCMD_PARAM(Ept->ResourceIndex); + } else { + if (Ept->Type == XUSBPSU_ENDPOINT_XFER_ISOC) { + BufferPtr += Length; + struct XUsbPsu_Trb *TrbTempNext; + TrbTempNext = &Ept->EpTrb[Ept->TrbEnqueue]; + Xil_AssertNonvoid(TrbTempNext != NULL); + + Ept->TrbEnqueue++; + if (Ept->TrbEnqueue == NO_OF_TRB_PER_EP) + Ept->TrbEnqueue = 0; + TrbTempNext->BufferPtrLow = (UINTPTR)BufferPtr; + TrbTempNext->BufferPtrHigh = ((UINTPTR)BufferPtr >> 16) >> 16; + TrbTempNext->Size = Length & XUSBPSU_TRB_SIZE_MASK; + + TrbTempNext->Ctrl = (XUSBPSU_TRBCTL_ISOCHRONOUS_FIRST + | XUSBPSU_TRB_CTRL_CSP + | XUSBPSU_TRB_CTRL_HWO + | XUSBPSU_TRB_CTRL_IOC + | XUSBPSU_TRB_CTRL_ISP_IMI); + + if (InstancePtr->ConfigPtr->IsCacheCoherent == 0) { + Xil_DCacheFlushRange((INTPTR)TrbTempNext, + sizeof(struct XUsbPsu_Trb)); + Xil_DCacheFlushRange((INTPTR)BufferPtr, Length); + } + + } + + cmd = XUSBPSU_DEPCMD_STARTTRANSFER; + cmd |= XUSBPSU_DEPCMD_PARAM(Ept->CurUf); + } + RetVal = XUsbPsu_SendEpCmd(InstancePtr, UsbEp, Ept->Direction, - XUSBPSU_DEPCMD_STARTTRANSFER, Params); + cmd, Params); if (RetVal != XST_SUCCESS) { return XST_FAILURE; } - Ept->ResourceIndex = (u8)XUsbPsu_EpGetTransferIndex(InstancePtr, - Ept->UsbEpNum, - Ept->Direction); + + if (!(Ept->EpStatus & XUSBPSU_EP_BUSY)) { + Ept->ResourceIndex = (u8)XUsbPsu_EpGetTransferIndex(InstancePtr, + Ept->UsbEpNum, + Ept->Direction); + + Ept->EpStatus |= XUSBPSU_EP_BUSY; + } + return XST_SUCCESS; } @@ -744,7 +939,7 @@ s32 XUsbPsu_EpBufferRecv(struct XUsbPsu *InstancePtr, u8 UsbEp, * Stalls an Endpoint. * * @param InstancePtr is a pointer to the XUsbPsu instance. -* @param EpNum is USB endpoint number. +* @param Epnum is USB endpoint number. * @param Dir is direction. * * @return None. @@ -768,7 +963,7 @@ void XUsbPsu_EpSetStall(struct XUsbPsu *InstancePtr, u8 Epnum, u8 Dir) Params = XUsbPsu_GetEpParams(InstancePtr); Xil_AssertVoid(Params != NULL); - (void)XUsbPsu_SendEpCmd(InstancePtr, Ept->PhyEpNum, Ept->Direction, + (void)XUsbPsu_SendEpCmd(InstancePtr, Ept->UsbEpNum, Ept->Direction, XUSBPSU_DEPCMD_SETSTALL, Params); Ept->EpStatus |= XUSBPSU_EP_STALL; @@ -803,7 +998,7 @@ void XUsbPsu_EpClearStall(struct XUsbPsu *InstancePtr, u8 Epnum, u8 Dir) Params = XUsbPsu_GetEpParams(InstancePtr); Xil_AssertVoid(Params != NULL); - (void)XUsbPsu_SendEpCmd(InstancePtr, Ept->PhyEpNum, Ept->Direction, + (void)XUsbPsu_SendEpCmd(InstancePtr, Ept->UsbEpNum, Ept->Direction, XUSBPSU_DEPCMD_CLEARSTALL, Params); Ept->EpStatus &= ~XUSBPSU_EP_STALL; @@ -895,10 +1090,20 @@ void XUsbPsu_EpXferComplete(struct XUsbPsu *InstancePtr, Epnum = Event->Epnumber; Ept = &InstancePtr->eps[Epnum]; Dir = Ept->Direction; - TrbPtr = &Ept->EpTrb; + TrbPtr = &Ept->EpTrb[Ept->TrbDequeue]; Xil_AssertVoid(TrbPtr != NULL); - Xil_DCacheInvalidateRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb)); + Ept->TrbDequeue++; + if (Ept->TrbDequeue == NO_OF_TRB_PER_EP) + Ept->TrbDequeue = 0; + + if (InstancePtr->ConfigPtr->IsCacheCoherent == 0) + Xil_DCacheInvalidateRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb)); + + if (Event->Endpoint_Event == XUSBPSU_DEPEVT_XFERCOMPLETE) { + Ept->EpStatus &= ~(XUSBPSU_EP_BUSY); + Ept->ResourceIndex = 0; + } Length = TrbPtr->Size & XUSBPSU_TRB_SIZE_MASK; @@ -909,19 +1114,64 @@ void XUsbPsu_EpXferComplete(struct XUsbPsu *InstancePtr, Ept->BytesTxed = Ept->RequestedBytes - Length; } else if (Dir == XUSBPSU_EP_DIR_OUT) { if (Ept->UnalignedTx == 1U) { - Ept->BytesTxed = Ept->RequestedBytes; + Ept->BytesTxed = (u32)roundup(Ept->RequestedBytes, + Ept->MaxSize); + Ept->BytesTxed -= Length; Ept->UnalignedTx = 0U; + } else { + /* + * Get the actual number of bytes transmitted + * by host + */ + Ept->BytesTxed = Ept->RequestedBytes - Length; } } } if (Dir == XUSBPSU_EP_DIR_OUT) { /* Invalidate Cache */ - Xil_DCacheInvalidateRange((INTPTR)Ept->BufferPtr, Ept->BytesTxed); + if (InstancePtr->ConfigPtr->IsCacheCoherent == 0) + Xil_DCacheInvalidateRange((INTPTR)Ept->BufferPtr, Ept->BytesTxed); } if (Ept->Handler != NULL) { - Ept->Handler(InstancePtr, Ept->RequestedBytes, Ept->BytesTxed); + Ept->Handler(InstancePtr->AppData, Ept->RequestedBytes, Ept->BytesTxed); + } +} + +/****************************************************************************/ +/** +* For Isochronous transfer, get the microframe time and calls respective Endpoint +* handler. +* +* @param InstancePtr is a pointer to the XUsbPsu instance. +* @param Event is a pointer to the Endpoint event occurred in core. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void XUsbPsu_EpXferNotReady(struct XUsbPsu *InstancePtr, + const struct XUsbPsu_Event_Epevt *Event) +{ + struct XUsbPsu_Ep *Ept; + u32 Epnum; + u32 CurUf, Mask; + + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(Event != NULL); + + Epnum = Event->Epnumber; + Ept = &InstancePtr->eps[Epnum]; + + if (Ept->Type == XUSBPSU_ENDPOINT_XFER_ISOC) { + Mask = ~(1 << (Ept->Interval - 1)); + CurUf = Event->Parameters & Mask; + Ept->CurUf = CurUf + (Ept->Interval * 4); + if (Ept->Handler != NULL) { + Ept->Handler(InstancePtr->AppData, 0, 0); + } } } /** @} */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_1/src/xusbpsu_endpoint.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_4/src/xusbpsu_endpoint.h similarity index 98% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_1/src/xusbpsu_endpoint.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_4/src/xusbpsu_endpoint.h index 299837862..b80da4832 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_1/src/xusbpsu_endpoint.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_4/src/xusbpsu_endpoint.h @@ -33,7 +33,7 @@ /** * * @file xusbps_endpoint.h -* @addtogroup usbpsu_v1_0 +* @addtogroup usbpsu_v1_3 * @{ * * This is an internal file containing the definitions for endpoints. It is @@ -46,6 +46,9 @@ * Ver Who Date Changes * ----- ---- -------- -------------------------------------------------------- * 1.0 sg 06/06/16 First release + * 1.4 bk 12/01/18 Modify USBPSU driver code to fit USB common example code + * for all USB IPs. + * * * ******************************************************************************/ @@ -59,7 +62,7 @@ extern "C" { /***************************** Include Files *********************************/ #include "xil_cache.h" -#include "xusbpsu.h" +#include "xusb_wrapper.h" #include "xil_types.h" /**************************** Type Definitions *******************************/ diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_4/src/xusbpsu_g.c similarity index 86% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_g.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_4/src/xusbpsu_g.c index 41a9b8c7a..4019d76df 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_g.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_4/src/xusbpsu_g.c @@ -5,7 +5,7 @@ * Version: * DO NOT EDIT. * -* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.* +* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.* *Permission is hereby granted, free of charge, to any person obtaining a copy *of this software and associated documentation files (the Software), to deal *in the Software without restriction, including without limitation the rights @@ -44,11 +44,12 @@ * The configuration table for devices */ -XUsbPsu_Config XUsbPsu_ConfigTable[] = +XUsbPsu_Config XUsbPsu_ConfigTable[XPAR_XUSBPSU_NUM_INSTANCES] = { { - XPAR_PSU_USB_0_DEVICE_ID, - XPAR_PSU_USB_0_BASEADDR + XPAR_PSU_USB_XHCI_0_DEVICE_ID, + XPAR_PSU_USB_XHCI_0_BASEADDR, + XPAR_PSU_USB_XHCI_0_IS_CACHE_COHERENT } }; diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_4/src/xusbpsu_hibernation.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_4/src/xusbpsu_hibernation.c new file mode 100644 index 000000000..20f53c974 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_4/src/xusbpsu_hibernation.c @@ -0,0 +1,688 @@ +/****************************************************************************** +* +* Copyright (C) 2017 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xusbpsu_hibernation.c +* +* This patch adds hibernation support to usbpsu driver when dwc3 is operating +* as a gadget +* +* 
+*
+* MODIFICATION HISTORY:
+*
+* Ver    Who    Date     Changes
+* ----- -----  -------- -----------------------------------------------------
+* 1.0   Mayank 12/01/18 First release
+*
+*
+* +*****************************************************************************/ + +/***************************** Include Files ********************************/ + +#include "xusbpsu.h" +#include "xusbpsu_hw.h" +#include "xusbpsu_endpoint.h" + +/************************** Constant Definitions *****************************/ + +#define NUM_OF_NONSTICKY_REGS 27 + +#define XUSBPSU_HIBER_SCRATCHBUF_SIZE 4096U + +#define XUSBPSU_NON_STICKY_SAVE_RETRIES 500U +#define XUSBPSU_PWR_STATE_RETRIES 1500U +#define XUSBPSU_CTRL_RDY_RETRIES 5000U +#define XUSBPSU_TIMEOUT 1000U + +/**************************** Type Definitions *******************************/ + + +/***************** Macros (Inline Functions) Definitions *********************/ + + +/************************** Function Prototypes ******************************/ + + +/************************** Variable Definitions *****************************/ + +static u8 ScratchBuf[XUSBPSU_HIBER_SCRATCHBUF_SIZE]; + +/* Registers saved during hibernation and restored at wakeup */ +static u32 save_reg_addr[] = { + XUSBPSU_DCTL, + XUSBPSU_DCFG, + XUSBPSU_DEVTEN, + XUSBPSU_GSBUSCFG0, + XUSBPSU_GSBUSCFG1, + XUSBPSU_GCTL, + XUSBPSU_GTXTHRCFG, + XUSBPSU_GRXTHRCFG, + XUSBPSU_GTXFIFOSIZ(0), + XUSBPSU_GTXFIFOSIZ(1), + XUSBPSU_GTXFIFOSIZ(2), + XUSBPSU_GTXFIFOSIZ(3), + XUSBPSU_GTXFIFOSIZ(4), + XUSBPSU_GTXFIFOSIZ(5), + XUSBPSU_GTXFIFOSIZ(6), + XUSBPSU_GTXFIFOSIZ(7), + XUSBPSU_GTXFIFOSIZ(8), + XUSBPSU_GTXFIFOSIZ(9), + XUSBPSU_GTXFIFOSIZ(10), + XUSBPSU_GTXFIFOSIZ(11), + XUSBPSU_GTXFIFOSIZ(12), + XUSBPSU_GTXFIFOSIZ(13), + XUSBPSU_GTXFIFOSIZ(14), + XUSBPSU_GTXFIFOSIZ(15), + XUSBPSU_GRXFIFOSIZ(0), + XUSBPSU_GUSB3PIPECTL(0), + XUSBPSU_GUSB2PHYCFG(0), +}; +static u32 saved_regs[NUM_OF_NONSTICKY_REGS]; + +/*****************************************************************************/ +/** +* Save non sticky registers +* +* @param InstancePtr is a pointer to the XUsbPsu instance to be worked +* on. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +static void save_regs(struct XUsbPsu *InstancePtr) +{ + u32 i; + + for (i = 0; i < NUM_OF_NONSTICKY_REGS; i++) + saved_regs[i] = XUsbPsu_ReadReg(InstancePtr, save_reg_addr[i]); +} + +/*****************************************************************************/ +/** +* Restore non sticky registers +* +* @param InstancePtr is a pointer to the XUsbPsu instance to be worked +* on. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +static void restore_regs(struct XUsbPsu *InstancePtr) +{ + u32 i; + + for (i = 0; i < NUM_OF_NONSTICKY_REGS; i++) + XUsbPsu_WriteReg(InstancePtr, save_reg_addr[i], saved_regs[i]); +} + +/*****************************************************************************/ +/** +* Send generic command for gadget +* +* @param InstancePtr is a pointer to the XUsbPsu instance to be worked +* on. +* @param cmd is command to be sent +* @param param is parameter for the command, to be written in DGCMDPAR +* register +* +* @return +* - XST_SUCCESS on success +* - XST_FAILURE on timeout +* - XST_REGISTER_ERROR on status error +* +* @note None. +* +******************************************************************************/ +s32 XUsbPsu_SendGadgetGenericCmd(struct XUsbPsu *InstancePtr, u32 cmd, + u32 param) +{ + u32 RegVal, retry = 500; + XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DGCMDPAR, param); + XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DGCMD, cmd | XUSBPSU_DGCMD_CMDACT); + + do { + RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DGCMD); + if (!(RegVal & XUSBPSU_DGCMD_CMDACT)) { + if (XUSBPSU_DGCMD_STATUS(RegVal)) + return XST_REGISTER_ERROR; + return 0; + } + } while (--retry); + + return XST_FAILURE; +} + +/*****************************************************************************/ +/** +* Sets scratchpad buffers +* +* @param InstancePtr is a pointer to the XUsbPsu instance to be worked +* on. +* +* @return XST_SUCCESS on success or else error code +* +* @note None. +* +******************************************************************************/ +s32 XUsbPsu_SetupScratchpad(struct XUsbPsu *InstancePtr) +{ + s32 Ret; + Ret = XUsbPsu_SendGadgetGenericCmd(InstancePtr, + XUSBPSU_DGCMD_SET_SCRATCHPAD_ADDR_LO, (UINTPTR)ScratchBuf & 0xffffffff); + if (Ret) { + xil_printf("Failed to set scratchpad low addr: %d\n", Ret); + return Ret; + } + + Ret = XUsbPsu_SendGadgetGenericCmd(InstancePtr, + XUSBPSU_DGCMD_SET_SCRATCHPAD_ADDR_HI, ((UINTPTR)ScratchBuf >> 16) >> 16); + if (Ret) { + xil_printf("Failed to set scratchpad high addr: %d\n", Ret); + return Ret; + } + + return XST_SUCCESS; +} + +/*****************************************************************************/ +/** +* Initialize to handle hibernation event when it comes +* +* @param InstancePtr is a pointer to the XUsbPsu instance to be worked +* on. +* +* @return none +* +* @note None. +* +******************************************************************************/ +void XUsbPsu_InitHibernation(struct XUsbPsu *InstancePtr) +{ + u32 RegVal; + + InstancePtr->IsHibernated = 0; + + memset(ScratchBuf, 0, sizeof(ScratchBuf)); + if (InstancePtr->ConfigPtr->IsCacheCoherent == 0) + Xil_DCacheFlushRange((INTPTR)ScratchBuf, XUSBPSU_HIBER_SCRATCHBUF_SIZE); + + XUsbPsu_SetupScratchpad(InstancePtr); + + /* enable PHY suspend */ + RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GUSB2PHYCFG(0)); + RegVal |= XUSBPSU_GUSB2PHYCFG_SUSPHY; + XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GUSB2PHYCFG(0), RegVal); + + RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GUSB3PIPECTL(0)); + RegVal |= XUSBPSU_GUSB3PIPECTL_SUSPHY; + XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GUSB3PIPECTL(0), RegVal); +} + +/*****************************************************************************/ +/** +* Handle hibernation event +* +* @param InstancePtr is a pointer to the XUsbPsu instance to be worked +* on. +* +* @return none +* +* @note None. +* +******************************************************************************/ +void Xusbpsu_HibernationIntr(struct XUsbPsu *InstancePtr) +{ + u8 EpNum; + u32 RegVal; + s32 retries; + XusbPsuLinkState LinkState; + + /* sanity check */ + switch(XUsbPsu_GetLinkState(InstancePtr)) { + case XUSBPSU_LINK_STATE_SS_DIS: + case XUSBPSU_LINK_STATE_U3: + break; + default: + /* fake hiber interrupt */ + xil_printf("got fake interrupt\r\n"); + return; + }; + + if (InstancePtr->Ep0State == XUSBPSU_EP0_SETUP_PHASE) { + XUsbPsu_StopTransfer(InstancePtr, 0, XUSBPSU_EP_DIR_OUT, TRUE); + XUsbPsu_RecvSetup(InstancePtr); + } + + /* stop active transfers for all endpoints including control + * endpoints force rm bit should be 0 when we do this */ + for (EpNum = 0; EpNum < XUSBPSU_ENDPOINTS_NUM; EpNum++) { + struct XUsbPsu_Ep *Ept; + + Ept = &InstancePtr->eps[EpNum]; + if (!Ept) + continue; + + if (!(Ept->EpStatus & XUSBPSU_EP_ENABLED)) + continue; + + /* save srsource index for later use */ + XUsbPsu_StopTransfer(InstancePtr, Ept->UsbEpNum, + Ept->Direction, FALSE); + + XUsbPsu_SaveEndpointState(InstancePtr, Ept); + } + + /* + * ack events, don't process them; h/w decrements the count by the value + * written + */ + RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GEVNTCOUNT(0)); + XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTCOUNT(0), RegVal); + InstancePtr->Evt.Count = 0; + InstancePtr->Evt.Flags &= ~XUSBPSU_EVENT_PENDING; + + if (XUsbPsu_Stop(InstancePtr)) { + xil_printf("Failed to stop USB core\r\n"); + return; + } + + RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL); + + /* Check the link state and if it is disconnected, set + * KEEP_CONNECT to 0 + */ + LinkState = XUsbPsu_GetLinkState(InstancePtr); + if (LinkState == XUSBPSU_LINK_STATE_SS_DIS) { + RegVal &= ~XUSBPSU_DCTL_KEEP_CONNECT; + XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal); + + /* update LinkState to be used while wakeup */ + InstancePtr->LinkState = XUSBPSU_LINK_STATE_SS_DIS; + } + + save_regs(InstancePtr); + + /* ask core to save state */ + RegVal |= XUSBPSU_DCTL_CSS; + XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal); + + /* wait till core saves */ + if (XUsbPsu_Wait_Clear_Timeout(InstancePtr, XUSBPSU_DSTS, + XUSBPSU_DSTS_SSS, XUSBPSU_NON_STICKY_SAVE_RETRIES) == XST_FAILURE) { + xil_printf("Failed to save core state\r\n"); + return; + } + + /* Enable PME to wakeup from hibernation */ + XUsbPsu_WriteVendorReg(XIL_PME_ENABLE, XIL_PME_ENABLE_SIG_GEN); + + /* change power state to D3 */ + XUsbPsu_WriteVendorReg(XIL_REQ_PWR_STATE, XIL_REQ_PWR_STATE_D3); + + /* wait till current state is changed to D3 */ + retries = XUSBPSU_PWR_STATE_RETRIES; + do { + RegVal = XUsbPsu_ReadVendorReg(XIL_CUR_PWR_STATE); + if ((RegVal & XIL_CUR_PWR_STATE_BITMASK) == XIL_CUR_PWR_STATE_D3) + break; + + XUsbSleep(XUSBPSU_TIMEOUT); + } while (--retries); + + if (retries < 0) { + xil_printf("Failed to change power state to D3\r\n"); + return; + } + XUsbSleep(XUSBPSU_TIMEOUT); + + RegVal = XUsbPsu_ReadLpdReg(RST_LPD_TOP); + if (InstancePtr->ConfigPtr->DeviceId == XPAR_XUSBPSU_0_DEVICE_ID) + XUsbPsu_WriteLpdReg(RST_LPD_TOP, RegVal | USB0_CORE_RST); + + InstancePtr->IsHibernated = 1; + xil_printf("Hibernated!\r\n"); +} + +/*****************************************************************************/ +/** +* Restarts transfer for active endpoint +* +* @param InstancePtr is a pointer to the XUsbPsu instance to be worked +* on. +* @param EpNum is an endpoint number. +* +* @return XST_SUCCESS on success or else XST_FAILURE. +* +* @note None. +* +******************************************************************************/ +static s32 XUsbPsu_RestartEp(struct XUsbPsu *InstancePtr, u8 EpNum) +{ + struct XUsbPsu_EpParams *Params; + struct XUsbPsu_Trb *TrbPtr; + struct XUsbPsu_Ep *Ept; + u32 Cmd; + s32 Ret; + + Xil_AssertNonvoid(InstancePtr != NULL); + + Params = XUsbPsu_GetEpParams(InstancePtr); + Xil_AssertNonvoid(Params != NULL); + + Ept = &InstancePtr->eps[EpNum]; + + /* check if we need to restart transfer */ + if (!Ept->ResourceIndex && Ept->PhyEpNum) + return XST_SUCCESS; + + if (Ept->UsbEpNum) { + TrbPtr = &Ept->EpTrb[Ept->TrbDequeue]; + } else { + TrbPtr = &InstancePtr->Ep0_Trb; + } + + Xil_AssertNonvoid(TrbPtr != NULL); + + TrbPtr->Ctrl |= XUSBPSU_TRB_CTRL_HWO; + + if (InstancePtr->ConfigPtr->IsCacheCoherent == 0) { + Xil_DCacheFlushRange((INTPTR)TrbPtr, sizeof(struct XUsbPsu_Trb)); + Xil_DCacheInvalidateRange((INTPTR)Ept->BufferPtr, Ept->RequestedBytes); + } + + Params->Param0 = 0U; + Params->Param1 = (UINTPTR)TrbPtr; + + Cmd = XUSBPSU_DEPCMD_STARTTRANSFER; + + Ret = XUsbPsu_SendEpCmd(InstancePtr, Ept->UsbEpNum, Ept->Direction, + Cmd, Params); + if (Ret) + return XST_FAILURE; + + Ept->EpStatus |= XUSBPSU_EP_BUSY; + Ept->ResourceIndex = (u8)XUsbPsu_EpGetTransferIndex(InstancePtr, + Ept->UsbEpNum, Ept->Direction); + + return XST_SUCCESS; +} + +/*****************************************************************************/ +/** +* Restarts EP0 endpoint +* +* @param InstancePtr is a pointer to the XUsbPsu instance to be worked +* on. +* +* @return XST_SUCCESS on success or else XST_FAILURE. +* +* @note None. +* +******************************************************************************/ +static s32 XUsbPsu_RestoreEp0(struct XUsbPsu *InstancePtr) +{ + struct XUsbPsu_Ep *Ept; + s32 Ret; + u8 EpNum; + + for (EpNum = 0; EpNum < 2; EpNum++) { + Ept = &InstancePtr->eps[EpNum]; + + if (!Ept) + continue; + + if (!(Ept->EpStatus & XUSBPSU_EP_ENABLED)) + continue; + + Ret = XUsbPsu_EpEnable(InstancePtr, Ept->UsbEpNum, + Ept->Direction, Ept->MaxSize, Ept->Type, TRUE); + if (Ret) { + xil_printf("Failed to enable EP %d on wakeup: %d\r\n", + EpNum, Ret); + return XST_FAILURE; + } + + if (Ept->EpStatus & XUSBPSU_EP_STALL) { + XUsbPsu_Ep0StallRestart(InstancePtr); + } else { + Ret = XUsbPsu_RestartEp(InstancePtr, Ept->PhyEpNum); + if (Ret) { + xil_printf("Failed to restart EP %d on wakeup: %d\r\n", + EpNum, Ret); + return XST_FAILURE; + } + } + } + + return XST_SUCCESS; +} + +/*****************************************************************************/ +/** +* Restarts non EP0 endpoints +* +* @param InstancePtr is a pointer to the XUsbPsu instance to be worked +* on. +* +* @return XST_SUCCESS on success or else XST_FAILURE. +* +* @note None. +* +******************************************************************************/ +static s32 XUsbPsu_RestoreEps(struct XUsbPsu *InstancePtr) +{ + struct XUsbPsu_Ep *Ept; + s32 Ret; + u8 EpNum; + + for (EpNum = 2; EpNum < XUSBPSU_ENDPOINTS_NUM; EpNum++) { + Ept = &InstancePtr->eps[EpNum]; + + if (!Ept) + continue; + + if (!(Ept->EpStatus & XUSBPSU_EP_ENABLED)) + continue; + + Ret = XUsbPsu_EpEnable(InstancePtr, Ept->UsbEpNum, + Ept->Direction, Ept->MaxSize, Ept->Type, TRUE); + if (Ret) { + xil_printf("Failed to enable EP %d on wakeup: %d\r\n", + EpNum, Ret); + return XST_FAILURE; + } + } + + for (EpNum = 2; EpNum < XUSBPSU_ENDPOINTS_NUM; EpNum++) { + Ept = &InstancePtr->eps[EpNum]; + + if (!Ept) + continue; + + if (!(Ept->EpStatus & XUSBPSU_EP_ENABLED)) + continue; + + if (Ept->EpStatus & XUSBPSU_EP_STALL) { + XUsbPsu_EpSetStall(InstancePtr, Ept->UsbEpNum, Ept->Direction); + } else { + Ret = XUsbPsu_RestartEp(InstancePtr, Ept->PhyEpNum); + if (Ret) { + xil_printf("Failed to restart EP %d on wakeup: %d\r\n", + EpNum, Ret); + return XST_FAILURE; + } + } + } + + return XST_SUCCESS; +} + +/*****************************************************************************/ +/** +* Handle wakeup event +* +* @param InstancePtr is a pointer to the XUsbPsu instance to be worked +* on. +* +* @return none +* +* @note None. +* +******************************************************************************/ +void XUsbPsu_WakeupIntr(struct XUsbPsu *InstancePtr) +{ + u32 RegVal, link_state; + s32 retries; + char enter_hiber; + + RegVal = XUsbPsu_ReadLpdReg(RST_LPD_TOP); + if (InstancePtr->ConfigPtr->DeviceId == XPAR_XUSBPSU_0_DEVICE_ID) + XUsbPsu_WriteLpdReg(RST_LPD_TOP, RegVal & ~USB0_CORE_RST); + + /* change power state to D0 */ + XUsbPsu_WriteVendorReg(XIL_REQ_PWR_STATE, XIL_REQ_PWR_STATE_D0); + + /* wait till current state is changed to D0 */ + retries = XUSBPSU_PWR_STATE_RETRIES; + do { + RegVal = XUsbPsu_ReadVendorReg(XIL_CUR_PWR_STATE); + if ((RegVal & XIL_CUR_PWR_STATE_BITMASK) == XIL_CUR_PWR_STATE_D0) + break; + + XUsbSleep(XUSBPSU_TIMEOUT); + } while (--retries); + + if (retries < 0) { + xil_printf("Failed to change power state to D0\r\n"); + return; + } + + /* ask core to restore non-sticky registers */ + XUsbPsu_SetupScratchpad(InstancePtr); + + RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL); + RegVal |= XUSBPSU_DCTL_CRS; + XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal); + + /* wait till non-sticky registers are restored */ + if (XUsbPsu_Wait_Clear_Timeout(InstancePtr, XUSBPSU_DSTS, + XUSBPSU_DSTS_RSS, XUSBPSU_NON_STICKY_SAVE_RETRIES) == XST_FAILURE) { + xil_printf("Failed to restore USB core\r\n"); + return; + } + + restore_regs(InstancePtr); + + /* setup event buffers */ + XUsbPsu_EventBuffersSetup(InstancePtr); + + /* nothing to do when in OTG host mode */ + if (XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GSTS) & XUSBPSU_GSTS_CUR_MODE) + return; + + if (XUsbPsu_RestoreEp0(InstancePtr)) { + xil_printf("Failed to restore EP0\r\n"); + return; + } + + /* start controller */ + if (XUsbPsu_Start(InstancePtr)) { + xil_printf("Failed to start core on wakeup\r\n"); + return; + } + + /* Wait until device controller is ready */ + if (XUsbPsu_Wait_Clear_Timeout(InstancePtr, XUSBPSU_DSTS, + XUSBPSU_DSTS_DCNRD, XUSBPSU_CTRL_RDY_RETRIES) == XST_FAILURE) { + xil_printf("Failed to ready device controller\r\n"); + return; + } + + /* + * there can be suprious wakeup events , so wait for some time and check + * the link state + */ + XUsbSleep(XUSBPSU_TIMEOUT * 10); + + link_state = XUsbPsu_GetLinkState(InstancePtr); + + switch(link_state) { + case XUSBPSU_LINK_STATE_RESET: + RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DSTS); + RegVal &= ~XUSBPSU_DCFG_DEVADDR_MASK; + XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DSTS, RegVal); + + if (XUsbPsu_SetLinkState(InstancePtr, XUSBPSU_LINK_STATE_RECOV)) { + xil_printf("Failed to put link in Recovery\r\n"); + return; + } + break; + case XUSBPSU_LINK_STATE_SS_DIS: + RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL); + RegVal &= ~XUSBPSU_DCTL_KEEP_CONNECT; + XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal); + + /* fall Through */ + case XUSBPSU_LINK_STATE_U3: + /* enter hibernation again */ + enter_hiber = 1; + break; + default: + if (XUsbPsu_SetLinkState(InstancePtr, XUSBPSU_LINK_STATE_RECOV)) { + xil_printf("Failed to put link in Recovery\r\n"); + return; + } + break; + }; + + if (XUsbPsu_RestoreEps(InstancePtr)) { + xil_printf("Failed to restore EPs\r\n"); + return; + } + + InstancePtr->IsHibernated = 0; + + if (enter_hiber) { + Xusbpsu_HibernationIntr(InstancePtr); + return; + } + + xil_printf("We are back from hibernation!\r\n"); +} +/** @} */ diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_4/src/xusbpsu_hw.h similarity index 83% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_hw.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_4/src/xusbpsu_hw.h index db612b00f..344f919f3 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_1/src/xusbpsu_hw.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_4/src/xusbpsu_hw.h @@ -33,7 +33,7 @@ /** * * @file xusbpsu_hw.h -* @addtogroup usbpsu_v1_0 +* @addtogroup usbpsu_v1_3 * @{ * * 
@@ -43,6 +43,7 @@
 * Ver   Who    Date     Changes
 * ----- -----  -------- -----------------------------------------------------
 * 1.0   sg    06/06/16 First release
+* 1.4   myk   12/01/18 Added support of hibernation
 *
 *
* @@ -174,6 +175,7 @@ extern "C" { /* Global Status Register Device Interrupt Mask */ #define XUSBPSU_GSTS_DEVICE_IP_MASK 0x00000040 +#define XUSBPSU_GSTS_CUR_MODE (0x00000001U << 0) /* Global USB2 PHY Configuration Register */ #define XUSBPSU_GUSB2PHYCFG_PHYSOFTRST (0x00000001U << 31) @@ -308,8 +310,28 @@ extern "C" { #define XUSBPSU_PORTMSC_30_U1_TIMEOUT_MASK (0xffU << 0) #define XUSBPSU_PORTMSC_30_U1_TIMEOUT_SHIFT (0U) +/* Register for LPD block */ +#define RST_LPD_TOP 0x23C +#define USB0_CORE_RST (1 << 6) +#define USB1_CORE_RST (1 << 7) -/*@}*/ +/* Vendor registers for Xilinx */ +#define XIL_CUR_PWR_STATE 0x00 +#define XIL_PME_ENABLE 0x34 +#define XIL_REQ_PWR_STATE 0x3c +#define XIL_PWR_CONFIG_USB3 0x48 + +#define XIL_REQ_PWR_STATE_D0 0 +#define XIL_REQ_PWR_STATE_D3 3 +#define XIL_PME_ENABLE_SIG_GEN 1 +#define XIL_CUR_PWR_STATE_D0 0 +#define XIL_CUR_PWR_STATE_D3 3 +#define XIL_CUR_PWR_STATE_BITMASK 0x03 + +#define VENDOR_BASE_ADDRESS 0xFF9D0000 +#define LPD_BASE_ADDRESS 0xFF5E0000 + + /*@}*/ /**************************** Type Definitions *******************************/ @@ -353,6 +375,76 @@ extern "C" { #define XUsbPsu_WriteReg(InstancePtr, Offset, Data) \ Xil_Out32((InstancePtr)->ConfigPtr->BaseAddress + (u32)(Offset), (u32)(Data)) +/*****************************************************************************/ +/** +* +* Read a vendor register of the USBPS8 device. +* +* @param Offset is the offset of the register to read. +* +* @return The contents of the register. +* +* @note C-style Signature: +* u32 XUsbPsu_ReadVendorReg(struct XUsbPsu *InstancePtr, u32 Offset); +* +******************************************************************************/ +#define XUsbPsu_ReadVendorReg(Offset) \ + Xil_In32(VENDOR_BASE_ADDRESS + (u32)(Offset)) + +/*****************************************************************************/ +/** +* +* Write a Vendor register of the USBPS8 device. +* +* @param RegOffset is the offset of the register to write. +* @param Data is the value to write to the register. +* +* @return None. +* +* @note C-style Signature: +* void XUsbPsu_WriteVendorReg(struct XUsbPsu *InstancePtr, +* u32 Offset,u32 Data) +* +******************************************************************************/ +#define XUsbPsu_WriteVendorReg(Offset, Data) \ + Xil_Out32(VENDOR_BASE_ADDRESS + (u32)(Offset), (u32)(Data)) + +/*****************************************************************************/ +/** +* +* Read a LPD register of the USBPS8 device. +* +* @param InstancePtr is a pointer to the XUsbPsu instance. +* @param Offset is the offset of the register to read. +* +* @return The contents of the register. +* +* @note C-style Signature: +* u32 XUsbPsu_ReadLpdReg(struct XUsbPsu *InstancePtr, u32 Offset); +* +******************************************************************************/ +#define XUsbPsu_ReadLpdReg(Offset) \ + Xil_In32(LPD_BASE_ADDRESS + (u32)(Offset)) + +/*****************************************************************************/ +/** +* +* Write a LPD register of the USBPS8 device. +* +* @param InstancePtr is a pointer to the XUsbPsu instance. +* @param RegOffset is the offset of the register to write. +* @param Data is the value to write to the register. +* +* @return None. +* +* @note C-style Signature: +* void XUsbPsu_WriteLpdReg(struct XUsbPsu *InstancePtr, +* u32 Offset,u32 Data) +* +******************************************************************************/ +#define XUsbPsu_WriteLpdReg(Offset, Data) \ + Xil_Out32(LPD_BASE_ADDRESS + (u32)(Offset), (u32)(Data)) + /************************** Function Prototypes ******************************/ #ifdef __cplusplus diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_1/src/xusbpsu_intr.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_4/src/xusbpsu_intr.c similarity index 70% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_1/src/xusbpsu_intr.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_4/src/xusbpsu_intr.c index 85baab0f8..6124783fc 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_1/src/xusbpsu_intr.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_4/src/xusbpsu_intr.c @@ -33,7 +33,7 @@ /** * * @file xusbpsu_intr.c -* @addtogroup usbpsu_v1_0 +* @addtogroup usbpsu_v1_3 * @{ * * @@ -43,6 +43,13 @@ * Ver Who Date Changes * ----- ---- -------- ------------------------------------------------------- * 1.0 sg 06/06/16 First release +* 1.3 vak 04/03/17 Added CCI support for USB +* 1.4 bk 12/01/18 Modify USBPSU driver code to fit USB common example code +* for all USB IPs +* myk 12/01/18 Added hibernation support +* vak 22/01/18 Added changes for supporting microblaze platform +* vak 13/03/18 Moved the setup interrupt system calls from driver to +* example. * * * @@ -50,7 +57,7 @@ /***************************** Include Files ********************************/ -#include "xusbpsu.h" +#include "xusb_wrapper.h" /************************** Constant Definitions *****************************/ @@ -95,10 +102,12 @@ void XUsbPsu_EpInterrupt(struct XUsbPsu *InstancePtr, /* Handle other end point events */ switch (Event->Endpoint_Event) { case XUSBPSU_DEPEVT_XFERCOMPLETE: + case XUSBPSU_DEPEVT_XFERINPROGRESS: XUsbPsu_EpXferComplete(InstancePtr, Event); break; case XUSBPSU_DEPEVT_XFERNOTREADY: + XUsbPsu_EpXferNotReady(InstancePtr, Event); break; default: @@ -130,7 +139,87 @@ void XUsbPsu_DisconnectIntr(struct XUsbPsu *InstancePtr) XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal); InstancePtr->IsConfigDone = 0U; - InstancePtr->Speed = XUSBPSU_SPEED_UNKNOWN; + InstancePtr->AppData->Speed = XUSBPSU_SPEED_UNKNOWN; + +#ifdef XUSBPSU_HIBERNATION_ENABLE + /* In USB 2.0, to avoid hibernation interrupt at the time of connection + * clear KEEP_CONNECT bit. + */ + if (InstancePtr->HasHibernation) { + RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL); + if (RegVal & XUSBPSU_DCTL_KEEP_CONNECT) { + RegVal &= ~XUSBPSU_DCTL_KEEP_CONNECT; + XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal); + } + } +#endif + + /* Call the handler if necessary */ + if (InstancePtr->DisconnectIntrHandler != NULL) { + InstancePtr->DisconnectIntrHandler(InstancePtr->AppData); + } +} + +/****************************************************************************/ +/** +* Stops any active transfer. +* +* @param InstancePtr is a pointer to the XUsbPsu instance. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +static void XUsbPsu_stop_active_transfers(struct XUsbPsu *InstancePtr) +{ + u32 Epnum; + + for (Epnum = 2; Epnum < XUSBPSU_ENDPOINTS_NUM; Epnum++) { + struct XUsbPsu_Ep *Ept; + + Ept = &InstancePtr->eps[Epnum]; + if (!Ept) + continue; + + if (!(Ept->EpStatus & XUSBPSU_EP_ENABLED)) + continue; + + XUsbPsu_StopTransfer(InstancePtr, Ept->UsbEpNum, + Ept->Direction, TRUE); + } +} + +/****************************************************************************/ +/** +* Clears stall on all stalled Eps. +* +* @param InstancePtr is a pointer to the XUsbPsu instance. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +static void XUsbPsu_clear_stall_all_ep(struct XUsbPsu *InstancePtr) +{ + u32 Epnum; + + for (Epnum = 1; Epnum < XUSBPSU_ENDPOINTS_NUM; Epnum++) { + struct XUsbPsu_Ep *Ept; + + Ept = &InstancePtr->eps[Epnum]; + if (!Ept) + continue; + + if (!(Ept->EpStatus & XUSBPSU_EP_ENABLED)) + continue; + + if (!(Ept->EpStatus & XUSBPSU_EP_STALL)) + continue; + + XUsbPsu_EpClearStall(InstancePtr, Ept->UsbEpNum, Ept->Direction); + } } /****************************************************************************/ @@ -149,13 +238,16 @@ void XUsbPsu_ResetIntr(struct XUsbPsu *InstancePtr) u32 RegVal; u32 Index; - InstancePtr->State = XUSBPSU_STATE_DEFAULT; + InstancePtr->AppData->State = XUSBPSU_STATE_DEFAULT; RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL); RegVal &= ~XUSBPSU_DCTL_TSTCTRL_MASK; XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal); InstancePtr->TestMode = 0U; + XUsbPsu_stop_active_transfers(InstancePtr); + XUsbPsu_clear_stall_all_ep(InstancePtr); + for (Index = 0U; Index < (InstancePtr->NumInEps + InstancePtr->NumOutEps); Index++) { @@ -168,6 +260,11 @@ void XUsbPsu_ResetIntr(struct XUsbPsu *InstancePtr) RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCFG); RegVal &= ~(XUSBPSU_DCFG_DEVADDR_MASK); XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCFG, RegVal); + + /* Call the handler if necessary */ + if (InstancePtr->ResetIntrHandler != NULL) { + InstancePtr->ResetIntrHandler(InstancePtr->AppData); + } } /****************************************************************************/ @@ -189,7 +286,7 @@ void XUsbPsu_ConnDoneIntr(struct XUsbPsu *InstancePtr) RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DSTS); Speed = (u8)(RegVal & XUSBPSU_DSTS_CONNECTSPD); - InstancePtr->Speed = Speed; + InstancePtr->AppData->Speed = Speed; switch (Speed) { case XUSBPSU_DCFG_SUPERSPEED: @@ -197,7 +294,7 @@ void XUsbPsu_ConnDoneIntr(struct XUsbPsu *InstancePtr) xil_printf("Super Speed\r\n"); #endif Size = 512U; - InstancePtr->Speed = XUSBPSU_SPEED_SUPER; + InstancePtr->AppData->Speed = XUSBPSU_SPEED_SUPER; break; case XUSBPSU_DCFG_HIGHSPEED: @@ -205,7 +302,7 @@ void XUsbPsu_ConnDoneIntr(struct XUsbPsu *InstancePtr) xil_printf("High Speed\r\n"); #endif Size = 64U; - InstancePtr->Speed = XUSBPSU_SPEED_HIGH; + InstancePtr->AppData->Speed = XUSBPSU_SPEED_HIGH; break; case XUSBPSU_DCFG_FULLSPEED2: @@ -214,7 +311,7 @@ void XUsbPsu_ConnDoneIntr(struct XUsbPsu *InstancePtr) xil_printf("Full Speed\r\n"); #endif Size = 64U; - InstancePtr->Speed = XUSBPSU_SPEED_FULL; + InstancePtr->AppData->Speed = XUSBPSU_SPEED_FULL; break; case XUSBPSU_DCFG_LOWSPEED: @@ -222,15 +319,34 @@ void XUsbPsu_ConnDoneIntr(struct XUsbPsu *InstancePtr) xil_printf("Low Speed\r\n"); #endif Size = 64U; - InstancePtr->Speed = XUSBPSU_SPEED_LOW; + InstancePtr->AppData->Speed = XUSBPSU_SPEED_LOW; break; default : Size = 64U; break; } + if (InstancePtr->AppData->Speed == XUSBPSU_SPEED_SUPER) { + RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL); + RegVal &= ~XUSBPSU_DCTL_HIRD_THRES_MASK; + XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal); + } + (void)XUsbPsu_EnableControlEp(InstancePtr, Size); (void)XUsbPsu_RecvSetup(InstancePtr); + +#ifdef XUSBPSU_HIBERNATION_ENABLE + /* In USB 2.0, to avoid hibernation interrupt at the time of connection + * clear KEEP_CONNECT bit. + */ + if (InstancePtr->HasHibernation) { + RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_DCTL); + if (!(RegVal & XUSBPSU_DCTL_KEEP_CONNECT)) { + RegVal |= XUSBPSU_DCTL_KEEP_CONNECT; + XUsbPsu_WriteReg(InstancePtr, XUSBPSU_DCTL, RegVal); + } + } +#endif } /****************************************************************************/ @@ -284,6 +400,10 @@ void XUsbPsu_DevInterrupt(struct XUsbPsu *InstancePtr, break; case XUSBPSU_DEVICE_EVENT_HIBER_REQ: +#ifdef XUSBPSU_HIBERNATION_ENABLE + if (InstancePtr->HasHibernation) + Xusbpsu_HibernationIntr(InstancePtr); +#endif break; case XUSBPSU_DEVICE_EVENT_LINK_STATUS_CHANGE: @@ -362,26 +482,39 @@ void XUsbPsu_EventBufferHandler(struct XUsbPsu *InstancePtr) { struct XUsbPsu_EvtBuffer *Evt; union XUsbPsu_Event Event = {0}; + u32 RegVal; Evt = &InstancePtr->Evt; - Xil_DCacheInvalidateRange((INTPTR)Evt->BuffAddr, + if (InstancePtr->ConfigPtr->IsCacheCoherent == 0) { + Xil_DCacheInvalidateRange((INTPTR)Evt->BuffAddr, (u32)XUSBPSU_EVENT_BUFFERS_SIZE); + } while (Evt->Count > 0) { - Event.Raw = *(UINTPTR *)(Evt->BuffAddr + Evt->Offset); + Event.Raw = *(UINTPTR *)((UINTPTR)Evt->BuffAddr + Evt->Offset); /* - * Process the event received - */ - XUsbPsu_EventHandler(InstancePtr, &Event); + * Process the event received + */ + XUsbPsu_EventHandler(InstancePtr, &Event); + + /* don't process anymore events if core is hibernated */ + if (InstancePtr->IsHibernated) + return; Evt->Offset = (Evt->Offset + 4U) % XUSBPSU_EVENT_BUFFERS_SIZE; Evt->Count -= 4; XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTCOUNT(0), 4U); } + Evt->Count = 0; Evt->Flags &= ~XUSBPSU_EVENT_PENDING; + + /* Unmask event interrupt */ + RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GEVNTSIZ(0)); + RegVal &= ~XUSBPSU_GEVNTSIZ_INTMASK; + XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTSIZ(0), RegVal); } /****************************************************************************/ @@ -424,11 +557,24 @@ void XUsbPsu_IntrHandler(void *XUsbPsuInstancePtr) /* Processes events in an Event Buffer */ XUsbPsu_EventBufferHandler(InstancePtr); - - /* Unmask event interrupt */ - RegVal = XUsbPsu_ReadReg(InstancePtr, XUSBPSU_GEVNTSIZ(0)); - RegVal &= ~XUSBPSU_GEVNTSIZ_INTMASK; - XUsbPsu_WriteReg(InstancePtr, XUSBPSU_GEVNTSIZ(0), RegVal); } +#ifdef XUSBPSU_HIBERNATION_ENABLE +/****************************************************************************/ +/** +* Wakeup Interrupt Handler. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void XUsbPsu_WakeUpIntrHandler(void *XUsbPsuInstancePtr) +{ + struct XUsbPsu *InstancePtr = (struct XUsbPsu *)XUsbPsuInstancePtr; + + XUsbPsu_WakeupIntr(InstancePtr); +} +#endif + /** @} */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_1/src/xusbpsu_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_4/src/xusbpsu_sinit.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_1/src/xusbpsu_sinit.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_4/src/xusbpsu_sinit.c index c172c5d69..bee46bc4c 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/usbpsu_v1_1/src/xusbpsu_sinit.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/usbpsu_v1_4/src/xusbpsu_sinit.c @@ -33,7 +33,7 @@ /** * * @file xusbpsu_sinit.h -* @addtogroup usbpsu_v1_0 +* @addtogroup usbpsu_v1_3 * @{ * * diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/video_common_v4_3/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/video_common_v4_3/src/Makefile new file mode 100644 index 000000000..9cb03a481 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/video_common_v4_3/src/Makefile @@ -0,0 +1,40 @@ +COMPILER= +ARCHIVER= +CP=cp +COMPILER_FLAGS=-ffunction-sections -fdata-sections +EXTRA_COMPILER_FLAGS=-Wall -Wextra +LIB=libxil.a + +CC_FLAGS = $(COMPILER_FLAGS) +ECC_FLAGS = $(EXTRA_COMPILER_FLAGS) + +RELEASEDIR=../../../lib +INCLUDEDIR=../../../include +INCLUDES=-I./. -I${INCLUDEDIR} + +OUTS = *.o + +LIBSOURCES:=*.c +INCLUDEFILES:=*.h + +OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c))) + +libs: banner video_common_libs clean + +%.o: %.c + ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $< + +banner: + echo "Compiling video_common" + +video_common_libs: ${OBJECTS} + $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS} + +.PHONY: include +include: video_common_includes + +video_common_includes: + ${CP} ${INCLUDEFILES} ${INCLUDEDIR} + +clean: + rm -rf ${OBJECTS} diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/video_common_v4_3/src/xvidc.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/video_common_v4_3/src/xvidc.c new file mode 100644 index 000000000..ba4f789b0 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/video_common_v4_3/src/xvidc.c @@ -0,0 +1,1204 @@ +/******************************************************************************* + * + * Copyright (C) 2017 Xilinx, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * Use of the Software is limited solely to applications: + * (a) running on a Xilinx device, or + * (b) that interact with a Xilinx device through a bus or interconnect. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of the Xilinx shall not be used + * in advertising or otherwise to promote the sale, use or other dealings in + * this Software without prior written authorization from Xilinx. + * +*******************************************************************************/ +/******************************************************************************/ +/** + * + * @file xvidc.c + * @addtogroup video_common_v4_3 + * @{ + * + * Contains common utility functions that are typically used by video-related + * drivers and applications. + * + * @note None. + * + * 
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -----------------------------------------------
+ * 1.0   rc,  01/10/15 Initial release.
+ *       als
+ * 2.2   als  02/01/16 Functions with pointer arguments that don't modify
+ *                     contents now const.
+ *                     Added ability to insert a custom video timing table.
+ *       yh            Added 3D support.
+ * 3.0   aad  05/13/16 Added API to search for RB video modes.
+ * 3.1   rco  07/26/16 Added extern definition for timing table array
+ *                     Added video-in-memory color formats
+ *                     Updated XVidC_RegisterCustomTimingModes API signature
+ * 4.1   rco  11/23/16 Added new memory formats
+ *                     Added new API to get video mode id that matches exactly
+ *                     with provided timing information
+ *                     Fix c++ warnings
+ * 4.2	 jsr  07/22/17 Added new framerates and color formats to support SDI
+ *                     Reordered YCBCR422 colorforamt and removed other formats
+ *                     that are not needed for SDI which were added earlier.
+ *       vyc  10/04/17 Added new streaming alpha formats and new memory formats
+ * 4.3   eb   26/01/18 Added API XVidC_GetVideoModeIdExtensive
+ *       jsr  02/22/18 Added XVIDC_CSF_YCBCR_420 color space format
+ *       vyc  04/04/18 Added BGR8 memory format
+ *
+ * +*******************************************************************************/ + +/******************************* Include Files ********************************/ + +#include "xil_assert.h" +#include "xstatus.h" +#include "xvidc.h" + +/*************************** Variable Declarations ****************************/ +extern const XVidC_VideoTimingMode XVidC_VideoTimingModes[XVIDC_VM_NUM_SUPPORTED]; + +const XVidC_VideoTimingMode *XVidC_CustomTimingModes = NULL; +int XVidC_NumCustomModes = 0; + +/**************************** Function Prototypes *****************************/ + +static const XVidC_VideoTimingMode *XVidC_GetCustomVideoModeData( + XVidC_VideoMode VmId); +static u8 XVidC_IsVtmRb(const char *VideoModeStr, u8 RbN); + +/*************************** Function Definitions *****************************/ + +/******************************************************************************/ +/** + * This function registers a user-defined custom video mode timing table with + * video_common. Functions which search the available video modes, or take VmId + * as an input, will operate on or check the custom video mode timing table in + * addition to the pre-defined video mode timing table (XVidC_VideoTimingModes). + * + * @param CustomTable is a pointer to the user-defined custom vide mode + * timing table to register. + * @param NumElems is the number of video modes supported by CustomTable. + * + * @return + * - XST_SUCCESS if the custom table was successfully registered. + * - XST_FAILURE if an existing custom table is already present. + * + * @note IDs in the custom table may not conflict with IDs reserved by + * the XVidC_VideoMode enum. + * +*******************************************************************************/ +u32 XVidC_RegisterCustomTimingModes(const XVidC_VideoTimingMode *CustomTable, + u16 NumElems) +{ + u16 Index; + + /* Verify arguments. */ + Xil_AssertNonvoid(CustomTable != NULL); + for (Index = 0; Index < NumElems; Index++) { + Xil_AssertNonvoid((CustomTable[Index].VmId > XVIDC_VM_CUSTOM)); + /* The IDs of each video mode in the custom table must not + * conflict with IDs reserved by video_common. */ + } + + /* Fail if a custom table is currently already registered. */ + if (XVidC_CustomTimingModes) { + return XST_FAILURE; + } + + XVidC_CustomTimingModes = CustomTable; + XVidC_NumCustomModes = NumElems; + + return XST_SUCCESS; +} + +/******************************************************************************/ +/** + * This function unregisters the user-defined custom video mode timing table + * previously registered by XVidC_RegisterCustomTimingModes(). + * + * @return None. + * + * @note None. + * +*******************************************************************************/ +void XVidC_UnregisterCustomTimingModes(void) +{ + XVidC_CustomTimingModes = NULL; + XVidC_NumCustomModes = 0; +} + +/******************************************************************************/ +/** + * This function calculates pixel clock based on the inputs. + * + * @param HTotal specifies horizontal total. + * @param VTotal specifies vertical total. + * @param FrameRate specifies rate at which frames are generated. + * + * @return Pixel clock in Hz. + * + * @note None. + * +*******************************************************************************/ +u32 XVidC_GetPixelClockHzByHVFr(u32 HTotal, u32 VTotal, u8 FrameRate) +{ + return (HTotal * VTotal * FrameRate); +} + +/******************************************************************************/ +/** + * This function calculates pixel clock from video mode. + * + * @param VmId specifies the resolution id. + * + * @return Pixel clock in Hz. + * + * @note None. + * +*******************************************************************************/ +u32 XVidC_GetPixelClockHzByVmId(XVidC_VideoMode VmId) +{ + u32 ClkHz; + const XVidC_VideoTimingMode *VmPtr; + + VmPtr = XVidC_GetVideoModeData(VmId); + if (!VmPtr) { + return 0; + } + + if (XVidC_IsInterlaced(VmId)) { + /* For interlaced mode, use both frame 0 and frame 1 vertical + * totals. */ + ClkHz = VmPtr->Timing.F0PVTotal + VmPtr->Timing.F1VTotal; + + /* Multiply the number of pixels by the frame rate of each + * individual frame (half of the total frame rate). */ + ClkHz *= VmPtr->FrameRate / 2; + } + else { + /* For progressive mode, use only frame 0 vertical total. */ + ClkHz = VmPtr->Timing.F0PVTotal; + + /* Multiply the number of pixels by the frame rate. */ + ClkHz *= VmPtr->FrameRate; + } + + /* Multiply the vertical total by the horizontal total for number of + * pixels. */ + ClkHz *= VmPtr->Timing.HTotal; + + return ClkHz; +} + +/******************************************************************************/ +/** + * This function checks if the input video mode is interlaced/progressive based + * on its ID from the video timings table. + * + * @param VmId specifies the resolution ID from the video timings table. + * + * @return Video format. + * - XVIDC_VF_PROGRESSIVE + * - XVIDC_VF_INTERLACED + * + * @note None. + * +*******************************************************************************/ +XVidC_VideoFormat XVidC_GetVideoFormat(XVidC_VideoMode VmId) +{ + const XVidC_VideoTimingMode *VmPtr; + + VmPtr = XVidC_GetVideoModeData(VmId); + if (!VmPtr) { + return XVIDC_VF_UNKNOWN; + } + + if (VmPtr->Timing.F1VTotal == 0) { + return (XVIDC_VF_PROGRESSIVE); + } + + return (XVIDC_VF_INTERLACED); +} + +/******************************************************************************/ +/** + * This function checks if the input video mode is interlaced based on its ID + * from the video timings table. + * + * @param VmId specifies the resolution ID from the video timings table. + * + * @return + * - 1 if the video timing with the supplied table ID is + * interlaced. + * - 0 if the video timing is progressive. + * + * @note None. + * +*******************************************************************************/ +u8 XVidC_IsInterlaced(XVidC_VideoMode VmId) +{ + if (XVidC_GetVideoFormat(VmId) == XVIDC_VF_INTERLACED) { + return 1; + } + + return 0; +} + +/******************************************************************************/ +/** + * This function returns the Video Mode ID that matches the detected input + * timing, frame rate and I/P flag + * + * @param Timing is the pointer to timing parameters to match + * @param FrameRate specifies refresh rate in HZ + * @param IsInterlaced is flag. + * - 0 = Progressive + * - 1 = Interlaced. + * + * @return Id of a supported video mode. + * + * @note This is an extension of XVidC_GetVideoModeId API to include + * blanking information in match process. No attempt is made to + * search for reduced blanking entries, if any. + * +*******************************************************************************/ +XVidC_VideoMode XVidC_GetVideoModeIdWBlanking(const XVidC_VideoTiming *Timing, + u32 FrameRate, u8 IsInterlaced) +{ + XVidC_VideoMode VmId; + XVidC_VideoTiming const *StdTiming = NULL; + + /* First search for ID with matching Width & Height */ + VmId = XVidC_GetVideoModeId(Timing->HActive, Timing->VActive, FrameRate, + IsInterlaced); + + if(VmId == XVIDC_VM_NOT_SUPPORTED) { + return(VmId); + } else { + + /* Get standard timing info from default timing table */ + StdTiming = XVidC_GetTimingInfo(VmId); + + /* Match against detected timing parameters */ + if((Timing->HActive == StdTiming->HActive) && + (Timing->VActive == StdTiming->VActive) && + (Timing->HTotal == StdTiming->HTotal) && + (Timing->F0PVTotal == StdTiming->F0PVTotal) && + (Timing->HFrontPorch == StdTiming->HFrontPorch) && + (Timing->HSyncWidth == StdTiming->HSyncWidth) && + (Timing->HBackPorch == StdTiming->HBackPorch) && + (Timing->F0PVFrontPorch == StdTiming->F0PVFrontPorch) && + (Timing->F0PVSyncWidth == StdTiming->F0PVSyncWidth) && + (Timing->F0PVBackPorch == StdTiming->F0PVBackPorch)) { + return(VmId); + } else { + return(XVIDC_VM_NOT_SUPPORTED); + } + } +} + +/******************************************************************************/ +/** + * This function returns the Video Mode ID that matches the detected input + * width, height, frame rate and I/P flag + * + * @param Width specifies the number pixels per scanline. + * @param Height specifies the number of scanline's. + * @param FrameRate specifies refresh rate in HZ + * @param IsInterlaced is flag. + * - 0 = Progressive + * - 1 = Interlaced. + * + * @return Id of a supported video mode. + * + * @note None. + * +*******************************************************************************/ +XVidC_VideoMode XVidC_GetVideoModeId(u32 Width, u32 Height, u32 FrameRate, + u8 IsInterlaced) +{ + u32 Low; + u32 High; + u32 Mid; + u32 HActive; + u32 VActive; + u32 Rate; + u32 ResFound = (FALSE); + XVidC_VideoMode Mode; + u16 Index; + + /* First, attempt a linear search on the custom video timing table. */ + if(XVidC_CustomTimingModes) { + for (Index = 0; Index < XVidC_NumCustomModes; Index++) { + HActive = XVidC_CustomTimingModes[Index].Timing.HActive; + VActive = XVidC_CustomTimingModes[Index].Timing.VActive; + Rate = XVidC_CustomTimingModes[Index].FrameRate; + if ((Width == HActive) && + (Height == VActive) && + (FrameRate == Rate)) { + return XVidC_CustomTimingModes[Index].VmId; + } + } + } + + if (IsInterlaced) { + Low = (XVIDC_VM_INTL_START); + High = (XVIDC_VM_INTL_END); + } + else { + Low = (XVIDC_VM_PROG_START); + High = (XVIDC_VM_PROG_END); + } + + HActive = VActive = Rate = 0; + + /* Binary search finds item in sorted array. + * And returns index (zero based) of item + * If item is not found returns flag remains + * FALSE. Search key is "width or HActive" + */ + while (Low <= High) { + Mid = (Low + High) / 2; + HActive = XVidC_VideoTimingModes[Mid].Timing.HActive; + if (Width == HActive) { + ResFound = (TRUE); + break; + } + else if (Width < HActive) { + if (Mid == 0) { + break; + } + else { + High = Mid - 1; + } + } + else { + Low = Mid + 1; + } + } + + /* HActive matched at middle */ + if (ResFound) { + /* Rewind to start index of mode with matching width */ + while ((Mid > 0) && + (XVidC_VideoTimingModes[Mid - 1].Timing.HActive == + Width)) { + --Mid; + } + + ResFound = (FALSE); + VActive = XVidC_VideoTimingModes[Mid].Timing.VActive; + Rate = XVidC_VideoTimingModes[Mid].FrameRate; + + /* Now do a linear search for matching VActive and Frame + * Rate + */ + while (HActive == Width) { + /* check current entry */ + if ((VActive == Height) && (Rate == FrameRate)) { + ResFound = (TRUE); + break; + } + /* Check next entry */ + else { + Mid = Mid + 1; + HActive = + XVidC_VideoTimingModes[Mid].Timing.HActive; + VActive = + XVidC_VideoTimingModes[Mid].Timing.VActive; + Rate = XVidC_VideoTimingModes[Mid].FrameRate; + } + } + Mode = + (ResFound) ? (XVidC_VideoMode)Mid : (XVIDC_VM_NOT_SUPPORTED); + } + else { + Mode = (XVIDC_VM_NOT_SUPPORTED); + } + + return (Mode); +} + +/******************************************************************************/ +/** + * This function returns the Video Mode ID that matches the detected input + * timing, frame rate and I/P flag + * + * @param Timing is the pointer to timing parameters to match + * @param FrameRate specifies refresh rate in HZ + * @param IsInterlaced is flag. + * - 0 = Progressive + * - 1 = Interlaced. + * @param IsExtensive is flag. + * - 0 = Basic matching of timing parameters + * - 1 = Extensive matching of timing parameters + * + * @return Id of a supported video mode. + * + * @note This function attempts to search for reduced blanking entries, if + * any. + * +*******************************************************************************/ +XVidC_VideoMode XVidC_GetVideoModeIdExtensive(XVidC_VideoTiming *Timing, + u32 FrameRate, + u8 IsInterlaced, + u8 IsExtensive) +{ + u32 Low; + u32 High; + u32 Mid; + u32 HActive; + u32 VActive; + u32 Rate; + u32 ResFound = (FALSE); + XVidC_VideoMode Mode; + u16 Index; + + /* First, attempt a linear search on the custom video timing table. */ + if(XVidC_CustomTimingModes) { + for (Index = 0; Index < XVidC_NumCustomModes; Index++) { + HActive = XVidC_CustomTimingModes[Index].Timing.HActive; + VActive = XVidC_CustomTimingModes[Index].Timing.VActive; + Rate = XVidC_CustomTimingModes[Index].FrameRate; + if ((HActive == Timing->HActive) && (VActive == Timing->VActive) && + (Rate == FrameRate) && (IsExtensive == 0 || ( + XVidC_CustomTimingModes[Index].Timing.HTotal == Timing->HTotal && + XVidC_CustomTimingModes[Index].Timing.F0PVTotal == + Timing->F0PVTotal && + XVidC_CustomTimingModes[Index].Timing.HFrontPorch == + Timing->HFrontPorch && + XVidC_CustomTimingModes[Index].Timing.F0PVFrontPorch == + Timing->F0PVFrontPorch && + XVidC_CustomTimingModes[Index].Timing.HSyncWidth == + Timing->HSyncWidth && + XVidC_CustomTimingModes[Index].Timing.F0PVSyncWidth == + Timing->F0PVSyncWidth && + XVidC_CustomTimingModes[Index].Timing.VSyncPolarity == + Timing->VSyncPolarity))) { + if (!IsInterlaced || IsExtensive == 0 || ( + XVidC_CustomTimingModes[Index].Timing.F1VTotal == + Timing->F1VTotal && + XVidC_CustomTimingModes[Index].Timing.F1VFrontPorch == + Timing->F1VFrontPorch && + XVidC_CustomTimingModes[Index].Timing.F1VSyncWidth == + Timing->F1VSyncWidth)) { + return XVidC_CustomTimingModes[Index].VmId; + } + } + } + } + + if (IsInterlaced) { + Low = (XVIDC_VM_INTL_START); + High = (XVIDC_VM_INTL_END); + } + else { + Low = (XVIDC_VM_PROG_START); + High = (XVIDC_VM_PROG_END); + } + + HActive = VActive = Rate = 0; + + /* Binary search finds item in sorted array. + * And returns index (zero based) of item + * If item is not found returns flag remains + * FALSE. Search key is "Timing->HActive or HActive" + */ + while (Low <= High) { + Mid = (Low + High) / 2; + HActive = XVidC_VideoTimingModes[Mid].Timing.HActive; + if (Timing->HActive == HActive) { + ResFound = (TRUE); + break; + } + else if (Timing->HActive < HActive) { + if (Mid == 0) { + break; + } + else { + High = Mid - 1; + } + } + else { + Low = Mid + 1; + } + } + + /* HActive matched at middle */ + if (ResFound) { + /* Rewind to start index of mode with matching Timing->HActive */ + while ((Mid > 0) && + (XVidC_VideoTimingModes[Mid - 1].Timing.HActive == + Timing->HActive)) { + --Mid; + } + + ResFound = (FALSE); + VActive = XVidC_VideoTimingModes[Mid].Timing.VActive; + Rate = XVidC_VideoTimingModes[Mid].FrameRate; + + /* Now do a linear search for matching VActive and Frame + * Rate + */ + while (HActive == Timing->HActive) { + /* check current entry */ + if ((VActive == Timing->VActive) && (Rate == FrameRate) && + (IsExtensive == 0 || + (XVidC_VideoTimingModes[Mid].Timing.HTotal == + Timing->HTotal && + XVidC_VideoTimingModes[Mid].Timing.F0PVTotal == + Timing->F0PVTotal && + XVidC_VideoTimingModes[Mid].Timing.HFrontPorch == + Timing->HFrontPorch && + XVidC_VideoTimingModes[Mid].Timing.F0PVFrontPorch == + Timing->F0PVFrontPorch && + XVidC_VideoTimingModes[Mid].Timing.HSyncWidth == + Timing->HSyncWidth && + XVidC_VideoTimingModes[Mid].Timing.F0PVSyncWidth == + Timing->F0PVSyncWidth && + XVidC_VideoTimingModes[Mid].Timing.VSyncPolarity == + Timing->VSyncPolarity))) { + if (!IsInterlaced || IsExtensive == 0 || ( + XVidC_VideoTimingModes[Mid].Timing.F1VTotal == + Timing->F1VTotal && + XVidC_VideoTimingModes[Mid].Timing.F1VFrontPorch == + Timing->F1VFrontPorch && + XVidC_VideoTimingModes[Mid].Timing.F1VSyncWidth == + Timing->F1VSyncWidth)) { + ResFound = (TRUE); + break; + } + } + /* Check next entry */ + else { + Mid = Mid + 1; + HActive = + XVidC_VideoTimingModes[Mid].Timing.HActive; + VActive = + XVidC_VideoTimingModes[Mid].Timing.VActive; + Rate = XVidC_VideoTimingModes[Mid].FrameRate; + } + } + Mode = + (ResFound) ? (XVidC_VideoMode)Mid : (XVIDC_VM_NOT_SUPPORTED); + } + else { + Mode = (XVIDC_VM_NOT_SUPPORTED); + } + + return (Mode); +} + +/******************************************************************************/ +/** + * This function returns the video mode ID that matches the detected input + * width, height, frame rate, interlaced or progressive, and reduced blanking. + * + * @param Width specifies the number pixels per scanline. + * @param Height specifies the number of scanline's. + * @param FrameRate specifies refresh rate in HZ + * @param IsInterlaced specifies interlaced or progressive mode: + * - 0 = Progressive + * - 1 = Interlaced. + * @param RbN specifies the type of reduced blanking: + * - 0 = No reduced blanking + * - 1 = RB + * - 2 = RB2 + * + * @return ID of a supported video mode. + * + * @note None. + * +*******************************************************************************/ +XVidC_VideoMode XVidC_GetVideoModeIdRb(u32 Width, u32 Height, + u32 FrameRate, u8 IsInterlaced, u8 RbN) +{ + XVidC_VideoMode VmId; + const XVidC_VideoTimingMode *VtmPtr; + u8 Found = 0; + + VmId = XVidC_GetVideoModeId(Width, Height, FrameRate, + IsInterlaced); + + VtmPtr = XVidC_GetVideoModeData(VmId); + if (!VtmPtr) { + return XVIDC_VM_NOT_SUPPORTED; + } + + while (!Found) { + VtmPtr = XVidC_GetVideoModeData(VmId); + if ((Height != VtmPtr->Timing.VActive) || + (Width != VtmPtr->Timing.HActive) || + (FrameRate != VtmPtr->FrameRate) || + (IsInterlaced && !XVidC_IsInterlaced(VmId))) { + VmId = XVIDC_VM_NOT_SUPPORTED; + break; + } + Found = XVidC_IsVtmRb(XVidC_GetVideoModeStr(VmId), RbN); + if (Found) { + break; + } + VmId = (XVidC_VideoMode)((int)VmId + 1); + } + + return VmId; +} + +/******************************************************************************/ +/** + * This function returns the pointer to video mode data at index provided. + * + * @param VmId specifies the resolution id. + * + * @return Pointer to XVidC_VideoTimingMode structure based on the given + * video mode. + * + * @note None. + * +*******************************************************************************/ +const XVidC_VideoTimingMode *XVidC_GetVideoModeData(XVidC_VideoMode VmId) +{ + if (VmId < XVIDC_VM_NUM_SUPPORTED) { + return &XVidC_VideoTimingModes[VmId]; + } + + return XVidC_GetCustomVideoModeData(VmId); +} + +/******************************************************************************/ +/** + * + * This function returns the resolution name for index specified. + * + * @param VmId specifies the resolution id. + * + * @return Pointer to a resolution name string. + * + * @note None. + * +*******************************************************************************/ +const char *XVidC_GetVideoModeStr(XVidC_VideoMode VmId) +{ + const XVidC_VideoTimingMode *VmPtr; + + if (VmId == XVIDC_VM_CUSTOM) { + return ("Custom video mode"); + } + + VmPtr = XVidC_GetVideoModeData(VmId); + if (!VmPtr) { + return ("Video mode not supported"); + } + + return VmPtr->Name; +} + +/******************************************************************************/ +/** + * This function returns the frame rate name for index specified. + * + * @param VmId specifies the resolution id. + * + * @return Pointer to a frame rate name string. + * + * @note None. + * +*******************************************************************************/ +const char *XVidC_GetFrameRateStr(XVidC_VideoMode VmId) +{ + const XVidC_VideoTimingMode *VmPtr; + + VmPtr = XVidC_GetVideoModeData(VmId); + if (!VmPtr) { + return ("Video mode not supported"); + } + + switch (VmPtr->FrameRate) { + case (XVIDC_FR_24HZ): return ("24Hz"); + case (XVIDC_FR_25HZ): return ("25Hz"); + case (XVIDC_FR_30HZ): return ("30Hz"); + case (XVIDC_FR_48HZ): return ("48Hz"); + case (XVIDC_FR_50HZ): return ("50Hz"); + case (XVIDC_FR_56HZ): return ("56Hz"); + case (XVIDC_FR_60HZ): return ("60Hz"); + case (XVIDC_FR_65HZ): return ("65Hz"); + case (XVIDC_FR_67HZ): return ("67Hz"); + case (XVIDC_FR_70HZ): return ("70Hz"); + case (XVIDC_FR_72HZ): return ("72Hz"); + case (XVIDC_FR_75HZ): return ("75Hz"); + case (XVIDC_FR_85HZ): return ("85Hz"); + case (XVIDC_FR_87HZ): return ("87Hz"); + case (XVIDC_FR_88HZ): return ("88Hz"); + case (XVIDC_FR_96HZ): return ("96Hz"); + case (XVIDC_FR_100HZ): return ("100Hz"); + case (XVIDC_FR_120HZ): return ("120Hz"); + + default: + return ("Frame rate not supported"); + } +} + +/******************************************************************************/ +/** + * This function returns a string representation of the enumerated type, + * XVidC_3DFormat. + * + * @param Format specifies the value to convert. + * + * @return Pointer to the converted string. + * + * @note None. + * +*******************************************************************************/ +const char *XVidC_Get3DFormatStr(XVidC_3DFormat Format) +{ + switch (Format) { + case XVIDC_3D_FRAME_PACKING: + return ("Frame Packing"); + + case XVIDC_3D_FIELD_ALTERNATIVE: + return ("Field Alternative"); + + case XVIDC_3D_LINE_ALTERNATIVE: + return ("Line Alternative"); + + case XVIDC_3D_SIDE_BY_SIDE_FULL: + return ("Side-by-Side(full)"); + + case XVIDC_3D_TOP_AND_BOTTOM_HALF: + return ("Top-and-Bottom(half)"); + + case XVIDC_3D_SIDE_BY_SIDE_HALF: + return ("Side-by-Side(half)"); + + default: + return ("Unknown"); + } +} + +/******************************************************************************/ +/** + * This function returns the color format name for index specified. + * + * @param ColorFormatId specifies the index of color format space. + * + * @return Pointer to a color space name string. + * + * @note None. + * +*******************************************************************************/ +const char *XVidC_GetColorFormatStr(XVidC_ColorFormat ColorFormatId) +{ + switch (ColorFormatId) { + case XVIDC_CSF_RGB: return ("RGB"); + case XVIDC_CSF_YCRCB_444: return ("YUV_444"); + case XVIDC_CSF_YCRCB_422: return ("YUV_422"); + case XVIDC_CSF_YCRCB_420: return ("YUV_420"); + case XVIDC_CSF_YONLY: return ("Y_ONLY"); + case XVIDC_CSF_RGBA: return ("RGBA"); + case XVIDC_CSF_YCRCBA_444: return ("YUVA_444"); + case XVIDC_CSF_MEM_RGBX8: return ("RGBX8"); + case XVIDC_CSF_MEM_YUVX8: return ("YUVX8"); + case XVIDC_CSF_MEM_YUYV8: return ("YUYV8"); + case XVIDC_CSF_MEM_RGBA8: return ("RGBA8"); + case XVIDC_CSF_MEM_YUVA8: return ("YUVA8"); + case XVIDC_CSF_MEM_RGBX10: return ("RGBX10"); + case XVIDC_CSF_MEM_YUVX10: return ("YUVX10"); + case XVIDC_CSF_MEM_RGB565: return ("RGB565"); + case XVIDC_CSF_MEM_Y_UV8: return ("Y_UV8"); + case XVIDC_CSF_MEM_Y_UV8_420: return ("Y_UV8_420"); + case XVIDC_CSF_MEM_RGB8: return ("RGB8"); + case XVIDC_CSF_MEM_YUV8: return ("YUV8"); + case XVIDC_CSF_MEM_Y_UV10: return ("Y_UV10"); + case XVIDC_CSF_MEM_Y_UV10_420: return ("Y_UV10_420"); + case XVIDC_CSF_MEM_Y8: return ("Y8"); + case XVIDC_CSF_MEM_Y10: return ("Y10"); + case XVIDC_CSF_MEM_BGRA8: return ("BGRA8"); + case XVIDC_CSF_MEM_BGRX8: return ("BGRX8"); + case XVIDC_CSF_MEM_UYVY8: return ("UYVY8"); + case XVIDC_CSF_MEM_BGR8: return ("BGR8"); + case XVIDC_CSF_YCBCR_422: return ("YCBCR_422"); + case XVIDC_CSF_YCBCR_420: return ("YCBCR_420"); + default: + return ("Color space format not supported"); + } +} + +/******************************************************************************/ +/** + * This function returns the frame rate for index specified. + * + * @param VmId specifies the resolution id. + * + * @return Frame rate in Hz. + * + * @note None. + * +*******************************************************************************/ +XVidC_FrameRate XVidC_GetFrameRate(XVidC_VideoMode VmId) +{ + const XVidC_VideoTimingMode *VmPtr; + + VmPtr = XVidC_GetVideoModeData(VmId); + if (!VmPtr) { + return XVIDC_FR_NUM_SUPPORTED; + } + + return VmPtr->FrameRate; +} + +/******************************************************************************/ +/** + * This function returns the timing parameters for specified resolution. + * + * @param VmId specifies the resolution id. + * + * @return Pointer to a XVidC_VideoTiming structure. + * + * @note None. + * +*******************************************************************************/ +const XVidC_VideoTiming *XVidC_GetTimingInfo(XVidC_VideoMode VmId) +{ + const XVidC_VideoTimingMode *VmPtr; + + VmPtr = XVidC_GetVideoModeData(VmId); + if (!VmPtr) { + return NULL; + } + + return &VmPtr->Timing; +} + +/******************************************************************************/ +/** + * This function sets the VideoStream structure for the specified video format. + * + * @param VidStrmPtr is a pointer to the XVidC_VideoStream structure to be + * set. + * @param VmId specifies the resolution ID. + * @param ColorFormat specifies the color format type. + * @param Bpc specifies the color depth/bits per color component. + * @param Ppc specifies the pixels per clock. + * + * @return + * - XST_SUCCESS if the timing for the supplied ID was found. + * - XST_FAILURE, otherwise. + * + * @note None. + * +*******************************************************************************/ +u32 XVidC_SetVideoStream(XVidC_VideoStream *VidStrmPtr, XVidC_VideoMode VmId, + XVidC_ColorFormat ColorFormat, XVidC_ColorDepth Bpc, + XVidC_PixelsPerClock Ppc) +{ + const XVidC_VideoTiming *TimingPtr; + + /* Verify arguments. */ + Xil_AssertNonvoid(VidStrmPtr != NULL); + Xil_AssertNonvoid(ColorFormat < XVIDC_CSF_NUM_SUPPORTED); + Xil_AssertNonvoid((Bpc == XVIDC_BPC_6) || + (Bpc == XVIDC_BPC_8) || + (Bpc == XVIDC_BPC_10) || + (Bpc == XVIDC_BPC_12) || + (Bpc == XVIDC_BPC_14) || + (Bpc == XVIDC_BPC_16) || + (Bpc == XVIDC_BPC_UNKNOWN)); + Xil_AssertNonvoid((Ppc == XVIDC_PPC_1) || + (Ppc == XVIDC_PPC_2) || + (Ppc == XVIDC_PPC_4)); + + /* Get the timing from the video timing table. */ + TimingPtr = XVidC_GetTimingInfo(VmId); + if (!TimingPtr) { + return XST_FAILURE; + } + VidStrmPtr->VmId = VmId; + VidStrmPtr->Timing = *TimingPtr; + VidStrmPtr->FrameRate = XVidC_GetFrameRate(VmId); + VidStrmPtr->IsInterlaced = XVidC_IsInterlaced(VmId); + VidStrmPtr->ColorFormatId = ColorFormat; + VidStrmPtr->ColorDepth = Bpc; + VidStrmPtr->PixPerClk = Ppc; + + /* Set stream to 2D. */ + VidStrmPtr->Is3D = FALSE; + VidStrmPtr->Info_3D.Format = XVIDC_3D_UNKNOWN; + VidStrmPtr->Info_3D.Sampling.Method = XVIDC_3D_SAMPLING_UNKNOWN; + VidStrmPtr->Info_3D.Sampling.Position = XVIDC_3D_SAMPPOS_UNKNOWN; + + return XST_SUCCESS; +} + +/******************************************************************************/ +/** + * This function sets the VideoStream structure for the specified 3D video + * format. + * + * @param VidStrmPtr is a pointer to the XVidC_VideoStream structure to be + * set. + * @param VmId specifies the resolution ID. + * @param ColorFormat specifies the color format type. + * @param Bpc specifies the color depth/bits per color component. + * @param Ppc specifies the pixels per clock. + * @param Info3DPtr is a pointer to a XVidC_3DInfo structure. + * + * @return + * - XST_SUCCESS if the timing for the supplied ID was found. + * - XST_FAILURE, otherwise. + * + * @return + * - XST_SUCCESS + * - XST_FAILURE + * + * @note None. + * +*******************************************************************************/ +u32 XVidC_Set3DVideoStream(XVidC_VideoStream *VidStrmPtr, XVidC_VideoMode VmId, + XVidC_ColorFormat ColorFormat, XVidC_ColorDepth Bpc, + XVidC_PixelsPerClock Ppc, XVidC_3DInfo *Info3DPtr) +{ + u32 Status; + u16 Vblank0; + u16 Vblank1; + + /* Verify arguments */ + Xil_AssertNonvoid(Info3DPtr != NULL); + + /* Initialize with info for 2D frame. */ + Status = XVidC_SetVideoStream(VidStrmPtr, VmId, ColorFormat, Bpc, Ppc); + if (Status != XST_SUCCESS) { + return XST_FAILURE; + } + + /* Set stream to 3D. */ + VidStrmPtr->Is3D = TRUE; + VidStrmPtr->Info_3D = *Info3DPtr; + + /* Only 3D format supported is frame packing. */ + if (Info3DPtr->Format != XVIDC_3D_FRAME_PACKING) { + return XST_FAILURE; + } + + /* Update the timing based on the 3D format. */ + + /* An interlaced format is converted to a progressive frame: */ + /* 3D VActive = (2D VActive * 4) + (2D VBlank field0) + + (2D Vblank field1 * 2) */ + if (VidStrmPtr->IsInterlaced) { + Vblank0 = VidStrmPtr->Timing.F0PVTotal - + VidStrmPtr->Timing.VActive; + Vblank1 = VidStrmPtr->Timing.F1VTotal - + VidStrmPtr->Timing.VActive; + VidStrmPtr->Timing.VActive = (VidStrmPtr->Timing.VActive * 4) + + Vblank0 + (Vblank1 * 2); + + /* Set VTotal */ + VidStrmPtr->Timing.F0PVTotal *= 2; + VidStrmPtr->Timing.F0PVTotal += VidStrmPtr->Timing.F1VTotal * 2; + + /* Clear field 1 values. */ + VidStrmPtr->Timing.F1VFrontPorch = 0; + VidStrmPtr->Timing.F1VSyncWidth = 0; + VidStrmPtr->Timing.F1VBackPorch = 0; + VidStrmPtr->Timing.F1VTotal = 0; + + /* Set format to progressive */ + VidStrmPtr->IsInterlaced = FALSE; + } + /* Progressive */ + else { + /* 3D Vactive = (2D VActive * 2) + (2D VBlank) */ + Vblank0 = VidStrmPtr->Timing.F0PVTotal - + VidStrmPtr->Timing.VActive; + VidStrmPtr->Timing.VActive = (VidStrmPtr->Timing.VActive * 2) + + Vblank0; + + /* Set VTotal. */ + VidStrmPtr->Timing.F0PVTotal = VidStrmPtr->Timing.F0PVTotal * 2; + } + + return XST_SUCCESS; +} + +/******************************************************************************/ +/** + * This function prints the stream information on STDIO/UART console. + * + * @param Stream is a pointer to video stream. + * + * @return None. + * + * @note None. + * +*******************************************************************************/ +void XVidC_ReportStreamInfo(const XVidC_VideoStream *Stream) +{ + if (!XVidC_GetVideoModeData(Stream->VmId) && + (Stream->VmId != XVIDC_VM_CUSTOM)) { + xil_printf("\tThe stream ID (%d) is not supported.\r\n", + Stream->VmId); + return; + } + + xil_printf("\tColor Format: %s\r\n", + XVidC_GetColorFormatStr(Stream->ColorFormatId)); + xil_printf("\tColor Depth: %d\r\n", Stream->ColorDepth); + xil_printf("\tPixels Per Clock: %d\r\n", Stream->PixPerClk); + xil_printf("\tMode: %s\r\n", + Stream->IsInterlaced ? "Interlaced" : "Progressive"); + + if (Stream->Is3D) { + xil_printf("\t3D Format: %s\r\n", + XVidC_Get3DFormatStr(Stream->Info_3D.Format)); + } + + if (Stream->VmId == XVIDC_VM_CUSTOM) { + xil_printf("\tFrame Rate: %dHz\r\n", + Stream->FrameRate); + xil_printf("\tResolution: %dx%d [Custom Mode]\r\n", + Stream->Timing.HActive, Stream->Timing.VActive); + xil_printf("\tPixel Clock: %d\r\n", + XVidC_GetPixelClockHzByHVFr( + Stream->Timing.HTotal, + Stream->Timing.F0PVTotal, + Stream->FrameRate)); + } + else { + xil_printf("\tFrame Rate: %s\r\n", + XVidC_GetFrameRateStr(Stream->VmId)); + xil_printf("\tResolution: %s\r\n", + XVidC_GetVideoModeStr(Stream->VmId)); + xil_printf("\tPixel Clock: %d\r\n", + XVidC_GetPixelClockHzByVmId(Stream->VmId)); + } +} + +/******************************************************************************/ +/** + * This function prints timing information on STDIO/Uart console. + * + * @param Timing is a pointer to Video Timing structure of the stream. + * @param IsInterlaced is a TRUE/FALSE flag that denotes the timing + * parameter is for interlaced/progressive stream. + * + * @return None. + * + * @note None. + * +*******************************************************************************/ +void XVidC_ReportTiming(const XVidC_VideoTiming *Timing, u8 IsInterlaced) +{ + xil_printf("\r\n\tHSYNC Timing: hav=%04d, hfp=%02d, hsw=%02d(hsp=%d), " + "hbp=%03d, htot=%04d \n\r", Timing->HActive, + Timing->HFrontPorch, Timing->HSyncWidth, + Timing->HSyncPolarity, + Timing->HBackPorch, Timing->HTotal); + + /* Interlaced */ + if (IsInterlaced) { + xil_printf("\tVSYNC Timing (Field 0): vav=%04d, vfp=%02d, " + "vsw=%02d(vsp=%d), vbp=%03d, vtot=%04d\n\r", + Timing->VActive, Timing->F0PVFrontPorch, + Timing->F0PVSyncWidth, Timing->VSyncPolarity, + Timing->F0PVBackPorch, Timing->F0PVTotal); + xil_printf("\tVSYNC Timing (Field 1): vav=%04d, vfp=%02d, " + "vsw=%02d(vsp=%d), vbp=%03d, vtot=%04d\n\r", + Timing->VActive, Timing->F1VFrontPorch, + Timing->F1VSyncWidth, Timing->VSyncPolarity, + Timing->F1VBackPorch, Timing->F1VTotal); + } + /* Progressive */ + else { + xil_printf("\tVSYNC Timing: vav=%04d, vfp=%02d, " + "vsw=%02d(vsp=%d), vbp=%03d, vtot=%04d\n\r", + Timing->VActive, Timing->F0PVFrontPorch, + Timing->F0PVSyncWidth, Timing->VSyncPolarity, + Timing->F0PVBackPorch, Timing->F0PVTotal); + } +} + +/******************************************************************************/ +/** + * This function returns the pointer to video mode data at the provided index + * of the custom video mode table. + * + * @param VmId specifies the resolution ID. + * + * @return Pointer to XVidC_VideoTimingMode structure based on the given + * video mode. + * + * @note None. + * +*******************************************************************************/ +static const XVidC_VideoTimingMode *XVidC_GetCustomVideoModeData( + XVidC_VideoMode VmId) +{ + u16 Index; + + for (Index = 0; Index < XVidC_NumCustomModes; Index++) { + if (VmId == (XVidC_CustomTimingModes[Index].VmId)) { + return &(XVidC_CustomTimingModes[Index]); + } + } + + /* ID not found within the custom video mode table. */ + return NULL; +} + +/******************************************************************************/ +/** + * This function returns whether or not the video timing mode is a reduced + * blanking mode or not. + * + * @param VideoModeStr specifies the resolution name string. + * @param RbN specifies the type of reduced blanking: + * - 0 = No Reduced Blanking + * - 1 = RB + * - 2 = RB2 + * + * @return If the reduced blanking type is compatible with the video mode: + * - 0 = Not supported + * - 1 = Video mode supports the RB type + * + * @note None. + * +*******************************************************************************/ +static u8 XVidC_IsVtmRb(const char *VideoModeStr, u8 RbN) +{ + while ((*VideoModeStr !='\0') && (*VideoModeStr != 'R')) { + VideoModeStr++; + } + + if (*(VideoModeStr + 2) == ')') { + return RbN == 1; + } + if (*(VideoModeStr + 2) == '2') { + return RbN == 2; + } + return 0; +} +/** @} */ diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/video_common_v4_3/src/xvidc.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/video_common_v4_3/src/xvidc.h new file mode 100644 index 000000000..bcd3d0b7a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/video_common_v4_3/src/xvidc.h @@ -0,0 +1,621 @@ +/******************************************************************************* + * + * Copyright (C) 2017 Xilinx, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * Use of the Software is limited solely to applications: + * (a) running on a Xilinx device, or + * (b) that interact with a Xilinx device through a bus or interconnect. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of the Xilinx shall not be used + * in advertising or otherwise to promote the sale, use or other dealings in + * this Software without prior written authorization from Xilinx. + * +*******************************************************************************/ +/******************************************************************************/ +/** + * + * @file xvidc.h + * @addtogroup video_common_v4_3 + * @{ + * @details + * + * Contains common structures, definitions, macros, and utility functions that + * are typically used by video-related drivers and applications. + * + * @note None. + * + * 
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -----------------------------------------------
+ * 1.0   rc,  01/10/15 Initial release.
+ *       als
+ * 2.0   als  08/14/15 Added new video timings.
+ * 2.2   als  02/01/16 Functions with pointer arguments that don't modify
+ *                     contents now const.
+ *                     Added ability to insert a custom video timing table:
+ *                         XVidC_RegisterCustomTimingModes
+ *                         XVidC_UnregisterCustomTimingMode
+ *       yh            Added 3D support.
+ * 3.0   aad  05/13/16 Added API to search for RB video modes.
+ *       als  05/16/16 Added Y-only to color format enum.
+ * 3.1   rco  07/26/17 Moved timing table extern definition to xvidc.c
+ *                     Added video-in-memory color formats
+ *                     Updated XVidC_RegisterCustomTimingModes API signature
+ * 4.1   rco  11/23/17 Added new memory formats
+ *                     Added xil_printf include statement
+ *                     Added new API XVidC_GetVideoModeIdWBlanking
+ *                     Fix C++ warnings
+ * 4.2   jsr  07/22/17 Added new video modes, framerates, color formats for SDI
+ *                     New member AspectRatio is added to video stream structure
+ *                     Reordered XVidC_VideoMode enum variables and corrected the
+ *                     memory format enums
+ *       aad  07/10/17 Add XVIDC_VM_3840x2160_60_P_RB video format
+ *       vyc  10/04/17 Added new streaming alpha formats and new memory formats
+ *       aad  09/05/17 Add XVIDC_VM_1366x768_60_P_RB resolution
+ * 4.3   eb   26/01/18 Added API XVidC_GetVideoModeIdExtensive
+ *       jsr  02/22/18 Added XVIDC_CSF_YCBCR_420 color space format
+ *       vyc  04/04/18 Added BGR8 memory format
+ *
+ * +*******************************************************************************/ + +#ifndef XVIDC_H_ /* Prevent circular inclusions by using protection macros. */ +#define XVIDC_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************* Include Files ********************************/ + +#include "xil_types.h" +#include "xil_printf.h" + +/************************** Constant Definitions ******************************/ + +/** + * This typedef enumerates the list of available standard display monitor + * timings as specified in the xvidc_timings_table.c file. The naming format is: + * + * XVIDC_VM___(_RB) + * + * Where RB stands for reduced blanking. + */ +typedef enum { + /* Interlaced modes. */ + XVIDC_VM_720x480_60_I = 0, + XVIDC_VM_720x576_50_I, + XVIDC_VM_1440x480_60_I, + XVIDC_VM_1440x576_50_I, + XVIDC_VM_1920x1080_48_I, + XVIDC_VM_1920x1080_50_I, + XVIDC_VM_1920x1080_60_I, + XVIDC_VM_1920x1080_96_I, + XVIDC_VM_1920x1080_100_I, + XVIDC_VM_1920x1080_120_I, + XVIDC_VM_2048x1080_48_I, + XVIDC_VM_2048x1080_50_I, + XVIDC_VM_2048x1080_60_I, + XVIDC_VM_2048x1080_96_I, + XVIDC_VM_2048x1080_100_I, + XVIDC_VM_2048x1080_120_I, + + + /* Progressive modes. */ + XVIDC_VM_640x350_85_P, + XVIDC_VM_640x480_60_P, + XVIDC_VM_640x480_72_P, + XVIDC_VM_640x480_75_P, + XVIDC_VM_640x480_85_P, + XVIDC_VM_720x400_85_P, + XVIDC_VM_720x480_60_P, + XVIDC_VM_720x576_50_P, + XVIDC_VM_800x600_56_P, + XVIDC_VM_800x600_60_P, + XVIDC_VM_800x600_72_P, + XVIDC_VM_800x600_75_P, + XVIDC_VM_800x600_85_P, + XVIDC_VM_800x600_120_P_RB, + XVIDC_VM_848x480_60_P, + XVIDC_VM_1024x768_60_P, + XVIDC_VM_1024x768_70_P, + XVIDC_VM_1024x768_75_P, + XVIDC_VM_1024x768_85_P, + XVIDC_VM_1024x768_120_P_RB, + XVIDC_VM_1152x864_75_P, + XVIDC_VM_1280x720_24_P, + XVIDC_VM_1280x720_25_P, + XVIDC_VM_1280x720_30_P, + XVIDC_VM_1280x720_50_P, + XVIDC_VM_1280x720_60_P, + XVIDC_VM_1280x768_60_P, + XVIDC_VM_1280x768_60_P_RB, + XVIDC_VM_1280x768_75_P, + XVIDC_VM_1280x768_85_P, + XVIDC_VM_1280x768_120_P_RB, + XVIDC_VM_1280x800_60_P, + XVIDC_VM_1280x800_60_P_RB, + XVIDC_VM_1280x800_75_P, + XVIDC_VM_1280x800_85_P, + XVIDC_VM_1280x800_120_P_RB, + XVIDC_VM_1280x960_60_P, + XVIDC_VM_1280x960_85_P, + XVIDC_VM_1280x960_120_P_RB, + XVIDC_VM_1280x1024_60_P, + XVIDC_VM_1280x1024_75_P, + XVIDC_VM_1280x1024_85_P, + XVIDC_VM_1280x1024_120_P_RB, + XVIDC_VM_1360x768_60_P, + XVIDC_VM_1360x768_120_P_RB, + XVIDC_VM_1366x768_60_P, + XVIDC_VM_1366x768_60_P_RB, + XVIDC_VM_1400x1050_60_P, + XVIDC_VM_1400x1050_60_P_RB, + XVIDC_VM_1400x1050_75_P, + XVIDC_VM_1400x1050_85_P, + XVIDC_VM_1400x1050_120_P_RB, + XVIDC_VM_1440x240_60_P, + XVIDC_VM_1440x900_60_P, + XVIDC_VM_1440x900_60_P_RB, + XVIDC_VM_1440x900_75_P, + XVIDC_VM_1440x900_85_P, + XVIDC_VM_1440x900_120_P_RB, + XVIDC_VM_1600x1200_60_P, + XVIDC_VM_1600x1200_65_P, + XVIDC_VM_1600x1200_70_P, + XVIDC_VM_1600x1200_75_P, + XVIDC_VM_1600x1200_85_P, + XVIDC_VM_1600x1200_120_P_RB, + XVIDC_VM_1680x720_50_P, + XVIDC_VM_1680x720_60_P, + XVIDC_VM_1680x720_100_P, + XVIDC_VM_1680x720_120_P, + XVIDC_VM_1680x1050_50_P, + XVIDC_VM_1680x1050_60_P, + XVIDC_VM_1680x1050_60_P_RB, + XVIDC_VM_1680x1050_75_P, + XVIDC_VM_1680x1050_85_P, + XVIDC_VM_1680x1050_120_P_RB, + XVIDC_VM_1792x1344_60_P, + XVIDC_VM_1792x1344_75_P, + XVIDC_VM_1792x1344_120_P_RB, + XVIDC_VM_1856x1392_60_P, + XVIDC_VM_1856x1392_75_P, + XVIDC_VM_1856x1392_120_P_RB, + XVIDC_VM_1920x1080_24_P, + XVIDC_VM_1920x1080_25_P, + XVIDC_VM_1920x1080_30_P, + XVIDC_VM_1920x1080_48_P, + XVIDC_VM_1920x1080_50_P, + XVIDC_VM_1920x1080_60_P, + XVIDC_VM_1920x1080_100_P, + XVIDC_VM_1920x1080_120_P, + XVIDC_VM_1920x1200_60_P, + XVIDC_VM_1920x1200_60_P_RB, + XVIDC_VM_1920x1200_75_P, + XVIDC_VM_1920x1200_85_P, + XVIDC_VM_1920x1200_120_P_RB, + XVIDC_VM_1920x1440_60_P, + XVIDC_VM_1920x1440_75_P, + XVIDC_VM_1920x1440_120_P_RB, + XVIDC_VM_1920x2160_60_P, + XVIDC_VM_2048x1080_24_P, + XVIDC_VM_2048x1080_25_P, + XVIDC_VM_2048x1080_30_P, + XVIDC_VM_2048x1080_48_P, + XVIDC_VM_2048x1080_50_P, + XVIDC_VM_2048x1080_60_P, + XVIDC_VM_2048x1080_100_P, + XVIDC_VM_2048x1080_120_P, + XVIDC_VM_2560x1080_50_P, + XVIDC_VM_2560x1080_60_P, + XVIDC_VM_2560x1080_100_P, + XVIDC_VM_2560x1080_120_P, + XVIDC_VM_2560x1600_60_P, + XVIDC_VM_2560x1600_60_P_RB, + XVIDC_VM_2560x1600_75_P, + XVIDC_VM_2560x1600_85_P, + XVIDC_VM_2560x1600_120_P_RB, + XVIDC_VM_3840x2160_24_P, + XVIDC_VM_3840x2160_25_P, + XVIDC_VM_3840x2160_30_P, + XVIDC_VM_3840x2160_48_P, + XVIDC_VM_3840x2160_50_P, + XVIDC_VM_3840x2160_60_P, + XVIDC_VM_3840x2160_60_P_RB, + XVIDC_VM_4096x2160_24_P, + XVIDC_VM_4096x2160_25_P, + XVIDC_VM_4096x2160_30_P, + XVIDC_VM_4096x2160_48_P, + XVIDC_VM_4096x2160_50_P, + XVIDC_VM_4096x2160_60_P, + XVIDC_VM_4096x2160_60_P_RB, + + XVIDC_VM_NUM_SUPPORTED, + XVIDC_VM_USE_EDID_PREFERRED, + XVIDC_VM_NO_INPUT, + XVIDC_VM_NOT_SUPPORTED, + XVIDC_VM_CUSTOM, + + /* Marks beginning/end of interlaced/progressive modes in the table. */ + XVIDC_VM_INTL_START = XVIDC_VM_720x480_60_I, + XVIDC_VM_PROG_START = XVIDC_VM_640x350_85_P, + XVIDC_VM_INTL_END = (XVIDC_VM_PROG_START - 1), + XVIDC_VM_PROG_END = (XVIDC_VM_NUM_SUPPORTED - 1), + + /* Common naming. */ + XVIDC_VM_480_60_I = XVIDC_VM_720x480_60_I, + XVIDC_VM_576_50_I = XVIDC_VM_720x576_50_I, + XVIDC_VM_1080_50_I = XVIDC_VM_1920x1080_50_I, + XVIDC_VM_1080_60_I = XVIDC_VM_1920x1080_60_I, + XVIDC_VM_VGA_60_P = XVIDC_VM_640x480_60_P, + XVIDC_VM_480_60_P = XVIDC_VM_720x480_60_P, + XVIDC_VM_SVGA_60_P = XVIDC_VM_800x600_60_P, + XVIDC_VM_XGA_60_P = XVIDC_VM_1024x768_60_P, + XVIDC_VM_720_50_P = XVIDC_VM_1280x720_50_P, + XVIDC_VM_720_60_P = XVIDC_VM_1280x720_60_P, + XVIDC_VM_WXGA_60_P = XVIDC_VM_1366x768_60_P, + XVIDC_VM_UXGA_60_P = XVIDC_VM_1600x1200_60_P, + XVIDC_VM_WSXGA_60_P = XVIDC_VM_1680x1050_60_P, + XVIDC_VM_1080_24_P = XVIDC_VM_1920x1080_24_P, + XVIDC_VM_1080_25_P = XVIDC_VM_1920x1080_25_P, + XVIDC_VM_1080_30_P = XVIDC_VM_1920x1080_30_P, + XVIDC_VM_1080_50_P = XVIDC_VM_1920x1080_50_P, + XVIDC_VM_1080_60_P = XVIDC_VM_1920x1080_60_P, + XVIDC_VM_WUXGA_60_P = XVIDC_VM_1920x1200_60_P, + XVIDC_VM_UHD2_60_P = XVIDC_VM_1920x2160_60_P, + XVIDC_VM_UHD_24_P = XVIDC_VM_3840x2160_24_P, + XVIDC_VM_UHD_25_P = XVIDC_VM_3840x2160_25_P, + XVIDC_VM_UHD_30_P = XVIDC_VM_3840x2160_30_P, + XVIDC_VM_UHD_60_P = XVIDC_VM_3840x2160_60_P, + XVIDC_VM_4K2K_60_P = XVIDC_VM_4096x2160_60_P, + XVIDC_VM_4K2K_60_P_RB = XVIDC_VM_4096x2160_60_P_RB, +} XVidC_VideoMode; + +/** + * Progressive/interlaced video format. + */ +typedef enum { + XVIDC_VF_PROGRESSIVE = 0, + XVIDC_VF_INTERLACED, + XVIDC_VF_UNKNOWN +} XVidC_VideoFormat; + +/** + * Frame rate. + */ +typedef enum { + XVIDC_FR_24HZ = 24, + XVIDC_FR_25HZ = 25, + XVIDC_FR_30HZ = 30, + XVIDC_FR_48HZ = 48, + XVIDC_FR_50HZ = 50, + XVIDC_FR_56HZ = 56, + XVIDC_FR_60HZ = 60, + XVIDC_FR_65HZ = 65, + XVIDC_FR_67HZ = 67, + XVIDC_FR_70HZ = 70, + XVIDC_FR_72HZ = 72, + XVIDC_FR_75HZ = 75, + XVIDC_FR_85HZ = 85, + XVIDC_FR_87HZ = 87, + XVIDC_FR_88HZ = 88, + XVIDC_FR_96HZ = 96, + XVIDC_FR_100HZ = 100, + XVIDC_FR_120HZ = 120, + XVIDC_FR_NUM_SUPPORTED = 18, + XVIDC_FR_UNKNOWN +} XVidC_FrameRate; + +/** + * Color depth - bits per color component. + */ +typedef enum { + XVIDC_BPC_6 = 6, + XVIDC_BPC_8 = 8, + XVIDC_BPC_10 = 10, + XVIDC_BPC_12 = 12, + XVIDC_BPC_14 = 14, + XVIDC_BPC_16 = 16, + XVIDC_BPC_NUM_SUPPORTED = 6, + XVIDC_BPC_UNKNOWN +} XVidC_ColorDepth; + +/** + * Pixels per clock. + */ +typedef enum { + XVIDC_PPC_1 = 1, + XVIDC_PPC_2 = 2, + XVIDC_PPC_4 = 4, + XVIDC_PPC_8 = 8, + XVIDC_PPC_NUM_SUPPORTED = 4, +} XVidC_PixelsPerClock; + +/** + * Color space format. + */ +typedef enum { + /* Streaming video formats */ + XVIDC_CSF_RGB = 0, + XVIDC_CSF_YCRCB_444, + XVIDC_CSF_YCRCB_422, + XVIDC_CSF_YCRCB_420, + XVIDC_CSF_YONLY, + XVIDC_CSF_RGBA, + XVIDC_CSF_YCRCBA_444, + + /* 6 empty slots reserved for video formats for future + * extension + */ + + /* Video in memory formats */ + XVIDC_CSF_MEM_RGBX8 = 10, // [31:0] x:B:G:R 8:8:8:8 + XVIDC_CSF_MEM_YUVX8, // [31:0] x:V:U:Y 8:8:8:8 + XVIDC_CSF_MEM_YUYV8, // [31:0] V:Y:U:Y 8:8:8:8 + XVIDC_CSF_MEM_RGBA8, // [31:0] A:B:G:R 8:8:8:8 + XVIDC_CSF_MEM_YUVA8, // [31:0] A:V:U:Y 8:8:8:8 + XVIDC_CSF_MEM_RGBX10, // [31:0] x:B:G:R 2:10:10:10 + XVIDC_CSF_MEM_YUVX10, // [31:0] x:V:U:Y 2:10:10:10 + XVIDC_CSF_MEM_RGB565, // [15:0] B:G:R 5:6:5 + XVIDC_CSF_MEM_Y_UV8, // [15:0] Y:Y 8:8, [15:0] V:U 8:8 + XVIDC_CSF_MEM_Y_UV8_420, // [15:0] Y:Y 8:8, [15:0] V:U 8:8 + XVIDC_CSF_MEM_RGB8, // [23:0] B:G:R 8:8:8 + XVIDC_CSF_MEM_YUV8, // [24:0] V:U:Y 8:8:8 + XVIDC_CSF_MEM_Y_UV10, // [31:0] x:Y:Y:Y 2:10:10:10 [31:0] x:U:V:U 2:10:10:10 + XVIDC_CSF_MEM_Y_UV10_420, // [31:0] x:Y:Y:Y 2:10:10:10 [31:0] x:U:V:U 2:10:10:10 + XVIDC_CSF_MEM_Y8, // [31:0] Y:Y:Y:Y 8:8:8:8 + XVIDC_CSF_MEM_Y10, // [31:0] x:Y:Y:Y 2:10:10:10 + XVIDC_CSF_MEM_BGRA8, // [31:0] A:R:G:B 8:8:8:8 + XVIDC_CSF_MEM_BGRX8, // [31:0] X:R:G:B 8:8:8:8 + XVIDC_CSF_MEM_UYVY8, // [31:0] Y:V:Y:U 8:8:8:8 + XVIDC_CSF_MEM_BGR8, // [23:0] R:G:B 8:8:8 + XVIDC_CSF_MEM_END, // End of memory formats + + /* Streaming formats with components re-ordered */ + XVIDC_CSF_YCBCR_422 = 64, + XVIDC_CSF_YCBCR_420, + + + XVIDC_CSF_NUM_SUPPORTED, // includes the reserved slots + XVIDC_CSF_UNKNOWN, + XVIDC_CSF_STRM_START = XVIDC_CSF_RGB, + XVIDC_CSF_STRM_END = XVIDC_CSF_YONLY, + XVIDC_CSF_MEM_START = XVIDC_CSF_MEM_RGBX8, + XVIDC_CSF_NUM_STRM = (XVIDC_CSF_STRM_END - XVIDC_CSF_STRM_START + 1), + XVIDC_CSF_NUM_MEM = (XVIDC_CSF_MEM_END - XVIDC_CSF_MEM_START) +} XVidC_ColorFormat; + + +/** + * Image Aspect Ratio. + */ +typedef enum { + XVIDC_AR_4_3 = 0, + XVIDC_AR_16_9 = 1 +} XVidC_AspectRatio; + +/** + * Color space conversion standard. + */ +typedef enum { + XVIDC_BT_2020 = 0, + XVIDC_BT_709, + XVIDC_BT_601, + XVIDC_BT_NUM_SUPPORTED, + XVIDC_BT_UNKNOWN +} XVidC_ColorStd; + +/** + * Color conversion output range. + */ +typedef enum { + XVIDC_CR_16_235 = 0, + XVIDC_CR_16_240, + XVIDC_CR_0_255, + XVIDC_CR_NUM_SUPPORTED, + XVIDC_CR_UNKNOWN_RANGE +} XVidC_ColorRange; + +/** + * 3D formats. + */ +typedef enum { + XVIDC_3D_FRAME_PACKING = 0, /**< Frame packing. */ + XVIDC_3D_FIELD_ALTERNATIVE, /**< Field alternative. */ + XVIDC_3D_LINE_ALTERNATIVE, /**< Line alternative. */ + XVIDC_3D_SIDE_BY_SIDE_FULL, /**< Side-by-side (full). */ + XVIDC_3D_TOP_AND_BOTTOM_HALF, /**< Top-and-bottom (half). */ + XVIDC_3D_SIDE_BY_SIDE_HALF, /**< Side-by-side (half). */ + XVIDC_3D_UNKNOWN +} XVidC_3DFormat; + +/** + * 3D Sub-sampling methods. + */ +typedef enum { + XVIDC_3D_SAMPLING_HORIZONTAL = 0, /**< Horizontal sub-sampling. */ + XVIDC_3D_SAMPLING_QUINCUNX, /**< Quincunx matrix. */ + XVIDC_3D_SAMPLING_UNKNOWN +} XVidC_3DSamplingMethod; + +/** + * 3D Sub-sampling positions. + */ +typedef enum { + XVIDC_3D_SAMPPOS_OLOR = 0, /**< Odd/Left, Odd/Right. */ + XVIDC_3D_SAMPPOS_OLER, /**< Odd/Left, Even/Right. */ + XVIDC_3D_SAMPPOS_ELOR, /**< Even/Left, Odd/Right. */ + XVIDC_3D_SAMPPOS_ELER, /**< Even/Left, Even/Right. */ + XVIDC_3D_SAMPPOS_UNKNOWN +} XVidC_3DSamplingPosition; + +/****************************** Type Definitions ******************************/ + +/** + * Video timing structure. + */ +typedef struct { + u16 HActive; + u16 HFrontPorch; + u16 HSyncWidth; + u16 HBackPorch; + u16 HTotal; + u8 HSyncPolarity; + u16 VActive; + u16 F0PVFrontPorch; + u16 F0PVSyncWidth; + u16 F0PVBackPorch; + u16 F0PVTotal; + u16 F1VFrontPorch; + u16 F1VSyncWidth; + u16 F1VBackPorch; + u16 F1VTotal; + u8 VSyncPolarity; +} XVidC_VideoTiming; + +/** + * 3D Sampling info structure. + */ +typedef struct { + XVidC_3DSamplingMethod Method; + XVidC_3DSamplingPosition Position; +} XVidC_3DSamplingInfo; + +/** + * 3D info structure. + */ +typedef struct { + XVidC_3DFormat Format; + XVidC_3DSamplingInfo Sampling; +} XVidC_3DInfo; + +/** + * Video stream structure. + */ +typedef struct { + XVidC_ColorFormat ColorFormatId; + XVidC_ColorDepth ColorDepth; + XVidC_PixelsPerClock PixPerClk; + XVidC_FrameRate FrameRate; + XVidC_AspectRatio AspectRatio; + u8 IsInterlaced; + u8 Is3D; + XVidC_3DInfo Info_3D; + XVidC_VideoMode VmId; + XVidC_VideoTiming Timing; +} XVidC_VideoStream; + +/** + * Video window structure. + */ +typedef struct { + u32 StartX; + u32 StartY; + u32 Width; + u32 Height; +} XVidC_VideoWindow; + +/** + * Video timing mode from the video timing table. + */ +typedef struct { + XVidC_VideoMode VmId; + const char Name[21]; + XVidC_FrameRate FrameRate; + XVidC_VideoTiming Timing; +} XVidC_VideoTimingMode; + +/** + * Callback type which represents a custom timer wait handler. This is only + * used for Microblaze since it doesn't have a native sleep function. To avoid + * dependency on a hardware timer, the default wait functionality is implemented + * using loop iterations; this isn't too accurate. Therefore a custom timer + * handler is used, the user may implement their own wait implementation. + * + * @param TimerPtr is a pointer to the timer instance. + * @param Delay is the duration (msec/usec) to be passed to the timer + * function. + * +*******************************************************************************/ +typedef void (*XVidC_DelayHandler)(void *TimerPtr, u32 Delay); + +/**************************** Function Prototypes *****************************/ + +u32 XVidC_RegisterCustomTimingModes(const XVidC_VideoTimingMode *CustomTable, + u16 NumElems); +void XVidC_UnregisterCustomTimingModes(void); +u32 XVidC_GetPixelClockHzByHVFr(u32 HTotal, u32 VTotal, u8 FrameRate); +u32 XVidC_GetPixelClockHzByVmId(XVidC_VideoMode VmId); +XVidC_VideoFormat XVidC_GetVideoFormat(XVidC_VideoMode VmId); +u8 XVidC_IsInterlaced(XVidC_VideoMode VmId); +const XVidC_VideoTimingMode* XVidC_GetVideoModeData(XVidC_VideoMode VmId); +const char *XVidC_GetVideoModeStr(XVidC_VideoMode VmId); +const char *XVidC_GetFrameRateStr(XVidC_VideoMode VmId); +const char *XVidC_GetColorFormatStr(XVidC_ColorFormat ColorFormatId); +XVidC_FrameRate XVidC_GetFrameRate(XVidC_VideoMode VmId); +const XVidC_VideoTiming* XVidC_GetTimingInfo(XVidC_VideoMode VmId); +void XVidC_ReportStreamInfo(const XVidC_VideoStream *Stream); +void XVidC_ReportTiming(const XVidC_VideoTiming *Timing, u8 IsInterlaced); +const char *XVidC_Get3DFormatStr(XVidC_3DFormat Format); +u32 XVidC_SetVideoStream(XVidC_VideoStream *VidStrmPtr, XVidC_VideoMode VmId, + XVidC_ColorFormat ColorFormat, XVidC_ColorDepth Bpc, + XVidC_PixelsPerClock Ppc); +u32 XVidC_Set3DVideoStream(XVidC_VideoStream *VidStrmPtr, XVidC_VideoMode VmId, + XVidC_ColorFormat ColorFormat, XVidC_ColorDepth Bpc, + XVidC_PixelsPerClock Ppc, XVidC_3DInfo *Info3DPtr); +XVidC_VideoMode XVidC_GetVideoModeId(u32 Width, u32 Height, u32 FrameRate, + u8 IsInterlaced); +XVidC_VideoMode XVidC_GetVideoModeIdExtensive(XVidC_VideoTiming *Timing, + u32 FrameRate, + u8 IsInterlaced, + u8 IsExtensive); +XVidC_VideoMode XVidC_GetVideoModeIdRb(u32 Width, u32 Height, u32 FrameRate, + u8 IsInterlaced, u8 RbN); +XVidC_VideoMode XVidC_GetVideoModeIdWBlanking(const XVidC_VideoTiming *Timing, + u32 FrameRate, u8 IsInterlaced); + +/******************* Macros (Inline Functions) Definitions ********************/ + +/*****************************************************************************/ +/** + * This macro check if video stream is 3D or 2D. + * + * @param VidStreamPtr is a pointer to the XVidC_VideoStream structure. + * + * @return 3D(1)/2D(0) + * + * @note C-style signature: + * u8 XDp_IsStream3D(XVidC_VideoStream *VidStreamPtr) + * + *****************************************************************************/ +#define XVidC_IsStream3D(VidStreamPtr) ((VidStreamPtr)->Is3D) + +/*************************** Variable Declarations ****************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* XVIDC_H_ */ +/** @} */ diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/video_common_v4_3/src/xvidc_cea861.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/video_common_v4_3/src/xvidc_cea861.h new file mode 100644 index 000000000..9e50b9d4b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/video_common_v4_3/src/xvidc_cea861.h @@ -0,0 +1,399 @@ +/* vim: set et fde fdm=syntax ft=c.doxygen ts=4 sts=4 sw=4 : */ +/* + * Copyright © 2010-2011 Saleem Abdulrasool . + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO + * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef xvidc_cea861_h +#define xvidc_cea861_h + +#define XVIDC_EDID_VERBOSITY 0 + +#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof(arr[0])) + +#define XVIDC_CEA861_NO_DTDS_PRESENT (0x04) + +#define HDMI_VSDB_EXTENSION_FLAGS_OFFSET (0x06) +#define HDMI_VSDB_MAX_TMDS_OFFSET (0x07) +#define HDMI_VSDB_LATENCY_FIELDS_OFFSET (0x08) + +static const u8 HDMI_OUI[] = { 0x00, 0x0C, 0x03 }; +static const u8 HDMI_OUI_HF[] = { 0xC4, 0x5D, 0xD8 }; + +enum xvidc_cea861_data_block_type { + XVIDC_CEA861_DATA_BLOCK_TYPE_RESERVED0, + XVIDC_CEA861_DATA_BLOCK_TYPE_AUDIO, + XVIDC_CEA861_DATA_BLOCK_TYPE_VIDEO, + XVIDC_CEA861_DATA_BLOCK_TYPE_VENDOR_SPECIFIC, + XVIDC_CEA861_DATA_BLOCK_TYPE_SPEAKER_ALLOCATION, + XVIDC_CEA861_DATA_BLOCK_TYPE_VESA_DTC, + XVIDC_CEA861_DATA_BLOCK_TYPE_RESERVED6, + XVIDC_CEA861_DATA_BLOCK_TYPE_EXTENDED, +}; + +enum xvidc_cea861_extended_tag_type_data_block { + XVIDC_CEA861_EXT_TAG_TYPE_VIDEO_CAPABILITY, + XVIDC_CEA861_EXT_TAG_TYPE_VENDOR_SPECIFIC, + XVIDC_CEA861_EXT_TAG_TYPE_VESA_DISPLAY_DEVICE, + XVIDC_CEA861_EXT_TAG_TYPE_VESA_VIDEO_TIMING_BLOCK_EXT, + XVIDC_CEA861_EXT_TAG_TYPE_RESERVED_FOR_HDMI_VIDEO_DATA_BLOCK, + XVIDC_CEA861_EXT_TAG_TYPE_COLORIMETRY, + XVIDC_CEA861_EXT_TAG_TYPE_HDR_STATIC_METADATA, + XVIDC_CEA861_EXT_TAG_TYPE_HDR_DYNAMIC_METADATA, + XVIDC_CEA861_EXT_TAG_TYPE_RESERVED2, + XVIDC_CEA861_EXT_TAG_TYPE_RESERVED3, + XVIDC_CEA861_EXT_TAG_TYPE_RESERVED4, + XVIDC_CEA861_EXT_TAG_TYPE_RESERVED5, + XVIDC_CEA861_EXT_TAG_TYPE_RESERVED6, + XVIDC_CEA861_EXT_TAG_TYPE_VIDEO_FRMT_PREFERENCE, + XVIDC_CEA861_EXT_TAG_TYPE_YCBCR420_VIDEO, + XVIDC_CEA861_EXT_TAG_TYPE_YCBCR420_CAPABILITY_MAP, + XVIDC_CEA861_EXT_TAG_TYPE_CEA_MISC_AUDIO_FIELDS, + XVIDC_CEA861_EXT_TAG_TYPE_VENDOR_SPECIFC_AUDIO, + XVIDC_CEA861_EXT_TAG_TYPE_HDMI_AUDIO, + XVIDC_CEA861_EXT_TAG_TYPE_ROOM_CONFIGURATION, + XVIDC_CEA861_EXT_TAG_TYPE_SPEAKER_LOCATION, + XVIDC_CEA861_EXT_TAG_TYPE_INFOFRAME = 32, +/* Can be extend to 255, refer table 46 cea data block tag codes cea-861-f */ +}; + +enum xvidc_cea861_audio_format { + XVIDC_CEA861_AUDIO_FORMAT_RESERVED, + XVIDC_CEA861_AUDIO_FORMAT_LPCM, + XVIDC_CEA861_AUDIO_FORMAT_AC_3, + XVIDC_CEA861_AUDIO_FORMAT_MPEG_1, + XVIDC_CEA861_AUDIO_FORMAT_MP3, + XVIDC_CEA861_AUDIO_FORMAT_MPEG2, + XVIDC_CEA861_AUDIO_FORMAT_AAC_LC, + XVIDC_CEA861_AUDIO_FORMAT_DTS, + XVIDC_CEA861_AUDIO_FORMAT_ATRAC, + XVIDC_CEA861_AUDIO_FORMAT_DSD, + XVIDC_CEA861_AUDIO_FORMAT_E_AC_3, + XVIDC_CEA861_AUDIO_FORMAT_DTS_HD, + XVIDC_CEA861_AUDIO_FORMAT_MLP, + XVIDC_CEA861_AUDIO_FORMAT_DST, + XVIDC_CEA861_AUDIO_FORMAT_WMA_PRO, + XVIDC_CEA861_AUDIO_FORMAT_EXTENDED, +}; + +struct __attribute__ (( packed )) xvidc_cea861_timing_block { + /* CEA Extension Header */ + u8 tag; + u8 revision; + u8 dtd_offset; + + /* Global Declarations */ + unsigned native_dtds : 4; + unsigned yuv_422_supported : 1; + unsigned yuv_444_supported : 1; + unsigned basic_audio_supported : 1; + unsigned underscan_supported : 1; + + u8 data[123]; + + u8 checksum; +}; + +struct __attribute__ (( packed )) xvidc_cea861_data_block_header { + unsigned length : 5; + unsigned tag : 3; +}; + +struct __attribute__ (( packed )) xvidc_cea861_short_video_descriptor { + unsigned video_identification_code : 7; + unsigned native : 1; +}; +#if XVIDC_EDID_VERBOSITY > 1 +struct __attribute__ (( packed )) xvidc_cea861_video_data_block { + struct xvidc_cea861_data_block_header header; + struct xvidc_cea861_short_video_descriptor svd[]; +}; +#endif +struct __attribute__ (( packed )) xvidc_cea861_short_audio_descriptor { + unsigned channels : 3; /* = value + 1 */ + unsigned audio_format : 4; + unsigned : 1; + + unsigned sample_rate_32_kHz : 1; + unsigned sample_rate_44_1_kHz : 1; + unsigned sample_rate_48_kHz : 1; + unsigned sample_rate_88_2_kHz : 1; + unsigned sample_rate_96_kHz : 1; + unsigned sample_rate_176_4_kHz : 1; + unsigned sample_rate_192_kHz : 1; + unsigned : 1; + + union { + struct __attribute__ (( packed )) { + unsigned bitrate_16_bit : 1; + unsigned bitrate_20_bit : 1; + unsigned bitrate_24_bit : 1; + unsigned : 5; + } lpcm; + + u8 maximum_bit_rate; /* formats 2-8; = value * 8 kHz */ + + u8 format_dependent; /* formats 9-13; */ + + struct __attribute__ (( packed )) { + unsigned profile : 3; + unsigned : 5; + } wma_pro; + + struct __attribute__ (( packed )) { + unsigned : 3; + unsigned code : 5; + } extension; + } flags; +}; +#if XVIDC_EDID_VERBOSITY > 1 +struct __attribute__ (( packed )) xvidc_cea861_audio_data_block { + struct xvidc_cea861_data_block_header header; + struct xvidc_cea861_short_audio_descriptor sad[]; +}; +#endif +#if XVIDC_EDID_VERBOSITY > 1 +struct __attribute__ (( packed )) xvidc_cea861_speaker_allocation { + unsigned front_left_right : 1; + unsigned front_lfe : 1; /* low frequency effects */ + unsigned front_center : 1; + unsigned rear_left_right : 1; + unsigned rear_center : 1; + unsigned front_left_right_center : 1; + unsigned rear_left_right_center : 1; + unsigned front_left_right_wide : 1; + + unsigned front_left_right_high : 1; + unsigned top_center : 1; + unsigned front_center_high : 1; + unsigned : 5; + + unsigned : 8; +}; +#endif +#if XVIDC_EDID_VERBOSITY > 1 +struct __attribute__ (( packed )) xvidc_cea861_speaker_allocation_data_block { + struct xvidc_cea861_data_block_header header; + struct xvidc_cea861_speaker_allocation payload; +}; +#endif +struct __attribute__ (( packed )) xvidc_cea861_vendor_specific_data_block { + struct xvidc_cea861_data_block_header header; + u8 ieee_registration[3]; + u8 data[30]; +}; + +struct __attribute__ (( packed )) xvidc_cea861_extended_data_block { + struct xvidc_cea861_data_block_header header; + u8 xvidc_cea861_extended_tag_codes; + u8 data[30]; +}; + +#if XVIDC_EDID_VERBOSITY > 1 +static const struct xvidc_cea861_timing { + const u16 hactive; + const u16 vactive; + const enum { + INTERLACED, + PROGRESSIVE, + } mode; + const u16 htotal; + const u16 hblank; + const u16 vtotal; + const double vblank; + const double hfreq; + const double vfreq; + const double pixclk; +} xvidc_cea861_timings[] = { + [ 1] = { 640, 480, PROGRESSIVE, 800, 160, 525, 45.0, 31.469, 59.940, 25.175 }, + [ 2] = { 720, 480, PROGRESSIVE, 858, 138, 525, 45.0, 31.469, 59.940, 27.000 }, + [ 3] = { 720, 480, PROGRESSIVE, 858, 138, 525, 45.0, 31.469, 59.940, 27.000 }, + [ 4] = { 1280, 720, PROGRESSIVE, 1650, 370, 750, 30.0, 45.000, 60.000, 74.250 }, + [ 5] = { 1920,1080, INTERLACED, 2200, 280, 1125, 22.5, 33.750, 60.000, 72.250 }, + [ 6] = { 1440, 480, INTERLACED, 1716, 276, 525, 22.5, 15.734, 59.940, 27.000 }, + [ 7] = { 1440, 480, INTERLACED, 1716, 276, 525, 22.5, 15.734, 59.940, 27.000 }, + [ 8] = { 1440, 240, PROGRESSIVE, 1716, 276, 262, 22.0, 15.734, 60.054, 27.000 }, + [ 9] = { 1440, 240, PROGRESSIVE, 1716, 276, 262, 22.0, 15.734, 59.826, 27.000 }, + [ 10] = { 2880, 480, INTERLACED, 3432, 552, 525, 22.5, 15.734, 59.940, 54.000 }, + [ 11] = { 2880, 480, INTERLACED, 3432, 552, 525, 22.5, 15.734, 59.940, 54.000 }, + [ 12] = { 2880, 240, PROGRESSIVE, 3432, 552, 262, 22.0, 15.734, 60.054, 54.000 }, + [ 13] = { 2880, 240, PROGRESSIVE, 3432, 552, 262, 22.0, 15.734, 59.826, 54.000 }, + [ 14] = { 1440, 480, PROGRESSIVE, 1716, 276, 525, 45.0, 31.469, 59.940, 54.000 }, + [ 15] = { 1440, 480, PROGRESSIVE, 1716, 276, 525, 45.0, 31.469, 59.940, 54.000 }, + [ 16] = { 1920, 1080, PROGRESSIVE, 2200, 280, 1125, 45.0, 67.500, 60.000, 148.500 }, + [ 17] = { 720, 576, PROGRESSIVE, 864, 144, 625, 49.0, 31.250, 50.000, 27.000 }, + [ 18] = { 720, 576, PROGRESSIVE, 864, 144, 625, 49.0, 31.250, 50.000, 27.000 }, + [ 19] = { 1280, 720, PROGRESSIVE, 1980, 700, 750, 30.0, 37.500, 50.000, 74.250 }, + [ 20] = { 1920, 1080, INTERLACED, 2640, 720, 1125, 22.5, 28.125, 50.000, 74.250 }, + [ 21] = { 1440, 576, INTERLACED, 1728, 288, 625, 24.5, 15.625, 50.000, 27.000 }, + [ 22] = { 1440, 576, INTERLACED, 1728, 288, 625, 24.5, 15.625, 50.000, 27.000 }, + [ 23] = { 1440, 288, PROGRESSIVE, 1728, 288, 312, 24.0, 15.625, 50.080, 27.000 }, + [ 24] = { 1440, 288, PROGRESSIVE, 1728, 288, 313, 25.0, 15.625, 49.920, 27.000 }, + [ 25] = { 2880, 576, INTERLACED, 3456, 576, 625, 24.5, 15.625, 50.000, 54.000 }, + [ 26] = { 2880, 576, INTERLACED, 3456, 576, 625, 24.5, 15.625, 50.000, 54.000 }, + [ 27] = { 2880, 288, PROGRESSIVE, 3456, 576, 312, 24.0, 15.625, 50.080, 54.000 }, + [ 28] = { 2880, 288, PROGRESSIVE, 3456, 576, 313, 25.0, 15.625, 49.920, 54.000 }, + [ 29] = { 1440, 576, PROGRESSIVE, 1728, 288, 625, 49.0, 31.250, 50.000, 54.000 }, + [ 30] = { 1440, 576, PROGRESSIVE, 1728, 288, 625, 49.0, 31.250, 50.000, 54.000 }, + [ 31] = { 1920, 1080, PROGRESSIVE, 2640, 720, 1125, 45.0, 56.250, 50.000, 148.500 }, + [ 32] = { 1920, 1080, PROGRESSIVE, 2750, 830, 1125, 45.0, 27.000, 24.000, 74.250 }, + [ 33] = { 1920, 1080, PROGRESSIVE, 2640, 720, 1125, 45.0, 28.125, 25.000, 74.250 }, + [ 34] = { 1920, 1080, PROGRESSIVE, 2200, 280, 1125, 45.0, 33.750, 30.000, 74.250 }, + [ 35] = { 2880, 480, PROGRESSIVE, 3432, 552, 525, 45.0, 31.469, 59.940, 108.500 }, + [ 36] = { 2880, 480, PROGRESSIVE, 3432, 552, 525, 45.0, 31.469, 59.940, 108.500 }, + [ 37] = { 2880, 576, PROGRESSIVE, 3456, 576, 625, 49.0, 31.250, 50.000, 108.000 }, + [ 38] = { 2880, 576, PROGRESSIVE, 3456, 576, 625, 49.0, 31.250, 50.000, 108.000 }, + [ 39] = { 1920, 1080, INTERLACED, 2304, 384, 1250, 85.0, 31.250, 50.000, 72.000 }, + [ 40] = { 1920, 1080, INTERLACED, 2640, 720, 1125, 22.5, 56.250, 100.000, 148.500 }, + [ 41] = { 1280, 720, PROGRESSIVE, 1980, 700, 750, 30.0, 75.000, 100.000, 148.500 }, + [ 42] = { 720, 576, PROGRESSIVE, 864, 144, 625, 49.0, 62.500, 100.000, 54.000 }, + [ 43] = { 720, 576, PROGRESSIVE, 864, 144, 625, 49.0, 62.500, 100.000, 54.000 }, + [ 44] = { 1440, 576, INTERLACED, 1728, 288, 625, 24.5, 31.250, 100.000, 54.000 }, + [ 45] = { 1440, 576, INTERLACED, 1728, 288, 625, 24.5, 31.250, 100.000, 54.000 }, + [ 46] = { 1920, 1080, INTERLACED, 2200, 280, 1125, 22.5, 67.500, 120.000, 148.500 }, + [ 47] = { 1280, 720, PROGRESSIVE, 1650, 370, 750, 30.0, 90.000, 120.000, 148.500 }, + [ 48] = { 720, 480, PROGRESSIVE, 858, 138, 525, 45.0, 62.937, 119.880, 54.000 }, + [ 49] = { 720, 480, PROGRESSIVE, 858, 138, 525, 45.0, 62.937, 119.880, 54.000 }, + [ 50] = { 1440, 480, INTERLACED, 1716, 276, 525, 22.5, 31.469, 119.880, 54.000 }, + [ 51] = { 1440, 480, INTERLACED, 1716, 276, 525, 22.5, 31.469, 119.880, 54.000 }, + [ 52] = { 720, 576, PROGRESSIVE, 864, 144, 625, 49.0, 125.000, 200.000, 108.000 }, + [ 53] = { 720, 576, PROGRESSIVE, 864, 144, 625, 49.0, 125.000, 200.000, 108.000 }, + [ 54] = { 1440, 576, INTERLACED, 1728, 288, 625, 24.5, 62.500, 200.000, 108.000 }, + [ 55] = { 1440, 576, INTERLACED, 1728, 288, 625, 24.5, 62.500, 200.000, 108.000 }, + [ 56] = { 720, 480, PROGRESSIVE, 858, 138, 525, 45.0, 125.874, 239.760, 108.000 }, + [ 57] = { 720, 480, PROGRESSIVE, 858, 138, 525, 45.0, 125.874, 239.760, 108.000 }, + [ 58] = { 1440, 480, INTERLACED, 1716, 276, 525, 22.5, 62.937, 239.760, 108.000 }, + [ 59] = { 1440, 480, INTERLACED, 1716, 276, 525, 22.5, 62.937, 239.760, 108.000 }, + [60 ] = {1280, 720 , PROGRESSIVE, 3300, 2020, 750 , 30 , 18 , 24.0003, 59.4 }, + [61 ] = {1280, 720 , PROGRESSIVE, 3960, 2680, 750 , 30 , 18.75 , 25 , 74.25 }, + [62 ] = {1280, 720 , PROGRESSIVE, 3300, 2020, 750 , 30 , 22.5 , 30.0003, 74.25 }, + [63 ] = {1920, 1080, PROGRESSIVE, 2200, 280 , 1125, 45 , 135 , 120.003, 297 }, + [64 ] = {1920, 1080, PROGRESSIVE, 2640, 720 , 1125, 45 , 112.5 , 100 , 297 }, + [65 ] = {1280, 720 , PROGRESSIVE, 3300, 2020, 750 , 30 , 18 , 24.0003, 59.4 }, + [66 ] = {1280, 720 , PROGRESSIVE, 3960, 2680, 750 , 30 , 18.75 , 25 , 74.25 }, + [67 ] = {1280, 720 , PROGRESSIVE, 3300, 2020, 750 , 30 , 22.5 , 30.0003, 74.25 }, + [68 ] = {1280, 720 , PROGRESSIVE, 1980, 700 , 750 , 30 , 37.5 , 50 , 74.25 }, + [69 ] = {1280, 720 , PROGRESSIVE, 1650, 370 , 750 , 30 , 45 , 60.0003, 74.25 }, + [70 ] = {1280, 720 , PROGRESSIVE, 1980, 700 , 750 , 30 , 75 , 100 , 148.5 }, + [71 ] = {1280, 720 , PROGRESSIVE, 1650, 370 , 750 , 30 , 90 , 120.003, 148.5 }, + [72 ] = {1920, 1080, PROGRESSIVE, 2750, 830 , 1125, 45 , 27 , 24.0003, 74.25 }, + [73 ] = {1920, 1080, PROGRESSIVE, 2640, 720 , 1125, 45 , 28.125 , 25 , 74.25 }, + [74 ] = {1920, 1080, PROGRESSIVE, 2200, 280 , 1125, 45 , 33.75 , 30.0003, 74.25 }, + [75 ] = {1920, 1080, PROGRESSIVE, 2640, 720 , 1125, 45 , 56.25 , 50 , 148.5 }, + [76 ] = {1920, 1080, PROGRESSIVE, 2200, 280 , 1125, 45 , 67.5 , 60.0003, 148.5 }, + [77 ] = {1920, 1080, PROGRESSIVE, 2640, 720 , 1125, 45 , 112.5 , 100 , 297 }, + [78 ] = {1920, 1080, PROGRESSIVE, 2200, 280 , 1125, 45 , 135 , 120.003, 297 }, + [79 ] = {1680, 720 , PROGRESSIVE, 3300, 1620, 750 , 30 , 18 , 24.0003, 59.4 }, + [80 ] = {1680, 720 , PROGRESSIVE, 3168, 1488, 750 , 30 , 18.75 , 25 , 59.4 }, + [81 ] = {1680, 720 , PROGRESSIVE, 2640, 960 , 750 , 30 , 22.5 , 30.0003, 59.4 }, + [82 ] = {1680, 720 , PROGRESSIVE, 2200, 520 , 750 , 30 , 37.5 , 50 , 82.5 }, + [83 ] = {1680, 720 , PROGRESSIVE, 2200, 520 , 750 , 30 , 45 , 60.0003, 99 }, + [84 ] = {1680, 720 , PROGRESSIVE, 2000, 320 , 825 , 105 , 82.5 , 100 , 165 }, + [85 ] = {1680, 720 , PROGRESSIVE, 2000, 320 , 825 , 105 , 99 , 120.003, 198 }, + [86 ] = {2560, 1080, PROGRESSIVE, 3750, 1190, 1100, 20 , 26.4 , 24.0003, 99 }, + [87 ] = {2560, 1080, PROGRESSIVE, 3200, 640 , 1125, 45 , 28.125 , 25 , 90 }, + [88 ] = {2560, 1080, PROGRESSIVE, 3520, 960 , 1125, 45 , 33.75 , 30.0003, 118.8 }, + [89 ] = {2560, 1080, PROGRESSIVE, 3300, 740 , 1125, 45 , 56.25 , 50 , 185.625 }, + [90 ] = {2560, 1080, PROGRESSIVE, 3000, 440 , 1100, 20 , 66 , 60.0003, 198 }, + [91 ] = {2560, 1080, PROGRESSIVE, 2970, 410 , 1250, 170 , 125 , 100 , 371.25 }, + [92 ] = {2560, 1080, PROGRESSIVE, 3300, 740 , 1250, 170 , 150 , 120.003, 495 }, + [93 ] = {3840, 2160, PROGRESSIVE, 5500, 1660, 2250, 90 , 54 , 24.0003, 297 }, + [94 ] = {3840, 2160, PROGRESSIVE, 5280, 1440, 2250, 90 , 56.25 , 25 , 297 }, + [95 ] = {3840, 2160, PROGRESSIVE, 4400, 560 , 2250, 90 , 67.5 , 30.0003, 297 }, + [96 ] = {3840, 2160, PROGRESSIVE, 5280, 1440, 2250, 90 , 112.5 , 50 , 594 }, + [97 ] = {3840, 2160, PROGRESSIVE, 4400, 560 , 2250, 90 , 135 , 60.0003, 594 }, + [98 ] = {4096, 2160, PROGRESSIVE, 5500, 1404, 2250, 90 , 54 , 24.0003, 297 }, + [99 ] = {4096, 2160, PROGRESSIVE, 5280, 1184, 2250, 90 , 56.25 , 25 , 297 }, + [100] = {4096, 2160, PROGRESSIVE, 4400, 304 , 2250, 90 , 67.5 , 30.0003, 297 }, + [101] = {4096, 2160, PROGRESSIVE, 5280, 1184, 2250, 90 , 112.5 , 50 , 594 }, + [102] = {4096, 2160, PROGRESSIVE, 4400, 304 , 2250, 90 , 135 , 60.0003, 594 }, + [103] = {3840, 2160, PROGRESSIVE, 5500, 1660, 2250, 90 , 54 , 24.0003, 297 }, + [104] = {3840, 2160, PROGRESSIVE, 5280, 1440, 2250, 90 , 56.25 , 25 , 297 }, + [105] = {3840, 2160, PROGRESSIVE, 4400, 560 , 2250, 90 , 67.5 , 30.0003, 297 }, + [106] = {3840, 2160, PROGRESSIVE, 5280, 1440, 2250, 90 , 112.5 , 50 , 594 }, + [107] = {3840, 2160, PROGRESSIVE, 4400, 560 , 2250, 90 , 135 , 60.0003, 594 }, +}; +#endif + +struct __attribute__ (( packed )) xvidc_cea861_hdmi_vendor_specific_data_block { + struct xvidc_cea861_data_block_header header; + + u8 ieee_registration_id[3]; /* LSB */ + + unsigned port_configuration_b : 4; + unsigned port_configuration_a : 4; + unsigned port_configuration_d : 4; + unsigned port_configuration_c : 4; + + /* extension fields */ + unsigned dvi_dual_link : 1; + unsigned : 2; + unsigned yuv_444_supported : 1; + unsigned colour_depth_30_bit : 1; + unsigned colour_depth_36_bit : 1; + unsigned colour_depth_48_bit : 1; + unsigned audio_info_frame : 1; + + u8 max_tmds_clock; /* = value * 5 */ + + unsigned : 6; + unsigned interlaced_latency_fields : 1; + unsigned latency_fields : 1; + + u8 video_latency; /* = (value - 1) * 2 */ + u8 audio_latency; /* = (value - 1) * 2 */ + u8 interlaced_video_latency; + u8 interlaced_audio_latency; + + u8 reserved[]; +}; + +struct __attribute__ (( packed )) xvidc_cea861_hdmi_hf_vendor_specific_data_block { + struct xvidc_cea861_data_block_header header; + + u8 ieee_registration_id[3]; /* LSB */ + + u8 version; + u8 max_tmds_char_rate; + + unsigned osd_disparity_3d : 1; + unsigned dual_view_3d : 1; + unsigned independent_view_3d : 1; + unsigned lte_340mcsc_scramble : 1; + + unsigned : 2; + + unsigned rr_capable : 1; + unsigned scdc_present : 1; + unsigned dc_30bit_yuv420 : 1; + unsigned dc_36bit_yuv420 : 1; + unsigned dc_48bit_yuv420 : 1; + + u8 reserved[]; +}; + +#endif diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/video_common_v4_3/src/xvidc_edid.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/video_common_v4_3/src/xvidc_edid.c new file mode 100644 index 000000000..585f7b8a3 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/video_common_v4_3/src/xvidc_edid.c @@ -0,0 +1,707 @@ +/******************************************************************************* + * + * Copyright (C) 2017 Xilinx, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * Use of the Software is limited solely to applications: + * (a) running on a Xilinx device, or + * (b) that interact with a Xilinx device through a bus or interconnect. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of the Xilinx shall not be used + * in advertising or otherwise to promote the sale, use or other dealings in + * this Software without prior written authorization from Xilinx. + * +*******************************************************************************/ +/******************************************************************************/ +/** + * + * @file xvidc_edid.c + * @addtogroup video_common_v4_2 + * @{ + * + * Contains function definitions related to the Extended Display Identification + * Data (EDID) structure which is present in all monitors. All content in this + * file is agnostic of communication interface protocol. + * + * @note None. + * + * 
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -----------------------------------------------
+ * 1.0   als  11/09/14 Initial release.
+ * 2.2   als  02/01/16 Functions with pointer arguments that don't modify
+ *                     contents now const.
+ * 4.0   aad  10/26/16 Added API for colormetry which returns fixed point
+ *		       in Q0.10 format instead of float.
+ *
+ * +*******************************************************************************/ + +/******************************* Include Files ********************************/ + +#include "xvidc_edid.h" + +/**************************** Function Prototypes *****************************/ + +static u32 XVidC_EdidIsVideoTimingSupportedPreferredTiming(const u8 *EdidRaw, + const XVidC_VideoTimingMode *VtMode); +static u32 XVidC_EdidIsVideoTimingSupportedEstablishedTimings(const u8 *EdidRaw, + const XVidC_VideoTimingMode *VtMode); +static u32 XVidC_EdidIsVideoTimingSupportedStandardTimings(const u8 *EdidRaw, + const XVidC_VideoTimingMode *VtMode); +static int XVidC_CalculatePower(u8 Base, u8 Power); +static int XVidC_CalculateBinaryFraction_QFormat(u16 Val, u8 DecPtIndex); + +/**************************** Function Definitions ****************************/ + +/******************************************************************************/ +/** + * Get the manufacturer name as specified in the vendor and product ID field of + * the supplied base Extended Display Identification Data (EDID). + * + * @param EdidRaw is the supplied base EDID to retrieve the manufacturer + * name from. + * @param ManName is the string that will be modified to hold the + * retrieved manufacturer name. + * + * @return None. + * + * @note The ManName argument is modified with the manufacturer name. + * +*******************************************************************************/ +void XVidC_EdidGetManName(const u8 *EdidRaw, char ManName[4]) +{ + ManName[0] = 0x40 + ((EdidRaw[XVIDC_EDID_VPI_ID_MAN_NAME0] & + XVIDC_EDID_VPI_ID_MAN_NAME0_CHAR0_MASK) >> + XVIDC_EDID_VPI_ID_MAN_NAME0_CHAR0_SHIFT); + ManName[1] = 0x40 + (((EdidRaw[XVIDC_EDID_VPI_ID_MAN_NAME0] & + XVIDC_EDID_VPI_ID_MAN_NAME0_CHAR1_MASK) << + XVIDC_EDID_VPI_ID_MAN_NAME0_CHAR1_POS) | + (EdidRaw[XVIDC_EDID_VPI_ID_MAN_NAME1] >> + XVIDC_EDID_VPI_ID_MAN_NAME1_CHAR1_SHIFT)); + ManName[2] = 0x40 + (EdidRaw[XVIDC_EDID_VPI_ID_MAN_NAME1] & + XVIDC_EDID_VPI_ID_MAN_NAME1_CHAR2_MASK); + ManName[3] = '\0'; +} + +/******************************************************************************/ +/** + * Get the color bit depth (bits per primary color) as specified in the basic + * display parameters and features, video input definition field of the supplied + * base Extended Display Identification Data (EDID). + * + * @param EdidRaw is the supplied base EDID to retrieve color depth + * information from. + * + * @return The number of bits per primary color as specified by the + * supplied base EDID. + * + * @note None. + * +*******************************************************************************/ +XVidC_ColorDepth XVidC_EdidGetColorDepth(const u8 *EdidRaw) +{ + XVidC_ColorDepth Bpc; + + switch (((EdidRaw[XVIDC_EDID_BDISP_VID] & + XVIDC_EDID_BDISP_VID_DIG_BPC_MASK) >> + XVIDC_EDID_BDISP_VID_DIG_BPC_SHIFT)) { + case XVIDC_EDID_BDISP_VID_DIG_BPC_6: + Bpc = XVIDC_BPC_6; + break; + + case XVIDC_EDID_BDISP_VID_DIG_BPC_8: + Bpc = XVIDC_BPC_8; + break; + + case XVIDC_EDID_BDISP_VID_DIG_BPC_10: + Bpc = XVIDC_BPC_10; + break; + + case XVIDC_EDID_BDISP_VID_DIG_BPC_12: + Bpc = XVIDC_BPC_12; + break; + + case XVIDC_EDID_BDISP_VID_DIG_BPC_14: + Bpc = XVIDC_BPC_14; + break; + + case XVIDC_EDID_BDISP_VID_DIG_BPC_16: + Bpc = XVIDC_BPC_16; + break; + + default: + Bpc = XVIDC_BPC_UNKNOWN; + break; + } + + return Bpc; +} + +/******************************************************************************/ +/** + * Calculates the x chromaticity coordinate for red by converting a 10 bit + * binary fraction representation from the supplied base Extended Display + * Identification Data (EDID) to a integer in Q0.10 Format. To convert back + * to float divide the fixed point value by 2^10. + * + * @param EdidRaw is the supplied base EDID to retrieve chromaticity + * information from. + * + * @return The x chromatacity coordinate for red. + * + * @note All values will be accurate to +/-0.0005. + * +*******************************************************************************/ +int XVidC_EdidGetCcRedX(const u8 *EdidRaw) +{ + return XVidC_CalculateBinaryFraction_QFormat( + (EdidRaw[XVIDC_EDID_CC_REDX_HIGH] << + XVIDC_EDID_CC_HIGH_SHIFT) | (EdidRaw[XVIDC_EDID_CC_RG_LOW] >> + XVIDC_EDID_CC_RBX_LOW_SHIFT), 10); +} + +/******************************************************************************/ +/** + * Calculates the y chromaticity coordinate for red by converting a 10 bit + * binary fraction representation from the supplied base Extended Display + * Identification Data (EDID) to a integer in Q0.10 Format. To convert back + * to float divide the fixed point value by 2^10. + * + * @param EdidRaw is the supplied base EDID to retrieve chromaticity + * information from. + * + * @return The y chromatacity coordinate for red. + * + * @note All values will be accurate to +/-0.0005. + * +*******************************************************************************/ +int XVidC_EdidGetCcRedY(const u8 *EdidRaw) +{ + return XVidC_CalculateBinaryFraction_QFormat( + (EdidRaw[XVIDC_EDID_CC_REDY_HIGH] << + XVIDC_EDID_CC_HIGH_SHIFT) | ((EdidRaw[XVIDC_EDID_CC_RG_LOW] & + XVIDC_EDID_CC_RBY_LOW_MASK) >> + XVIDC_EDID_CC_RBY_LOW_SHIFT), 10); +} + +/******************************************************************************/ +/** + * Calculates the x chromaticity coordinate for green by converting a 10 bit + * binary fraction representation from the supplied base Extended Display + * Identification Data (EDID) to a integer in Q0.10 Format. To convert back + * to float divide the fixed point value by 2^10. + * + * @param EdidRaw is the supplied base EDID to retrieve chromaticity + * information from. + * + * @return The x chromatacity coordinate for green. + * + * @note All values will be accurate to +/-0.0005. + * +*******************************************************************************/ +int XVidC_EdidGetCcGreenX(const u8 *EdidRaw) +{ + return XVidC_CalculateBinaryFraction_QFormat( + (EdidRaw[XVIDC_EDID_CC_GREENX_HIGH] << + XVIDC_EDID_CC_HIGH_SHIFT) | ((EdidRaw[XVIDC_EDID_CC_RG_LOW] & + XVIDC_EDID_CC_GWX_LOW_MASK) >> + XVIDC_EDID_CC_GWX_LOW_SHIFT), 10); +} + +/******************************************************************************/ +/** + * Calculates the y chromaticity coordinate for green by converting a 10 bit + * binary fraction representation from the supplied base Extended Display + * Identification Data (EDID) to a integer in Q0.10 Format. To convert back + * to float divide the fixed point value by 2^10. + * + * @param EdidRaw is the supplied base EDID to retrieve chromaticity + * information from. + * + * @return The y chromatacity coordinate for green. + * + * @note All values will be accurate to +/-0.0005. + * +*******************************************************************************/ +int XVidC_EdidGetCcGreenY(const u8 *EdidRaw) +{ + return XVidC_CalculateBinaryFraction_QFormat( + (EdidRaw[XVIDC_EDID_CC_GREENY_HIGH] << + XVIDC_EDID_CC_HIGH_SHIFT) | (EdidRaw[XVIDC_EDID_CC_RG_LOW] & + XVIDC_EDID_CC_GWY_LOW_MASK), 10); +} + +/******************************************************************************/ +/** + * Calculates the x chromaticity coordinate for blue by converting a 10 bit + * binary fraction representation from the supplied base Extended Display + * Identification Data (EDID) to a integer in Q0.10 Format. To convert back + * to float divide the fixed point value by 2^10. + * + * @param EdidRaw is the supplied base EDID to retrieve chromaticity + * information from. + * + * @return The x chromatacity coordinate for blue. + * + * @note All values will be accurate to +/-0.0005. + * +*******************************************************************************/ +int XVidC_EdidGetCcBlueX(const u8 *EdidRaw) +{ + return XVidC_CalculateBinaryFraction_QFormat( + (EdidRaw[XVIDC_EDID_CC_BLUEX_HIGH] << + XVIDC_EDID_CC_HIGH_SHIFT) | (EdidRaw[XVIDC_EDID_CC_BW_LOW] >> + XVIDC_EDID_CC_RBX_LOW_SHIFT), 10); +} + +/******************************************************************************/ +/** + * Calculates the y chromaticity coordinate for blue by converting a 10 bit + * binary fraction representation from the supplied base Extended Display + * Identification Data (EDID) to a integer in Q0.10 Format. To convert back + * to float divide the fixed point value by 2^10. + * + * @param EdidRaw is the supplied base EDID to retrieve chromaticity + * information from. + * + * @return The y chromatacity coordinate for blue. + * + * @note All values will be accurate to +/-0.0005. + * +*******************************************************************************/ +int XVidC_EdidGetCcBlueY(const u8 *EdidRaw) +{ + return XVidC_CalculateBinaryFraction_QFormat( + (EdidRaw[XVIDC_EDID_CC_BLUEY_HIGH] << + XVIDC_EDID_CC_HIGH_SHIFT) | ((EdidRaw[XVIDC_EDID_CC_BW_LOW] & + XVIDC_EDID_CC_RBY_LOW_MASK) >> + XVIDC_EDID_CC_RBY_LOW_SHIFT), 10); +} + +/******************************************************************************/ +/** + * Calculates the x chromaticity coordinate for white by converting a 10 bit + * binary fraction representation from the supplied base Extended Display + * Identification Data (EDID) to a integer in Q0.10 Format. To convert back + * to float divide the fixed point value by 2^10. + * + * @param EdidRaw is the supplied base EDID to retrieve chromaticity + * information from. + * + * @return The x chromatacity coordinate for white. + * + * @note All values will be accurate to +/-0.0005. + * +*******************************************************************************/ +int XVidC_EdidGetCcWhiteX(const u8 *EdidRaw) +{ + return XVidC_CalculateBinaryFraction_QFormat( + (EdidRaw[XVIDC_EDID_CC_WHITEX_HIGH] << + XVIDC_EDID_CC_HIGH_SHIFT) | ((EdidRaw[XVIDC_EDID_CC_BW_LOW] & + XVIDC_EDID_CC_GWX_LOW_MASK) >> XVIDC_EDID_CC_GWX_LOW_SHIFT), 10); +} + +/******************************************************************************/ +/** + * Calculates the y chromaticity coordinate for white by converting a 10 bit + * binary fraction representation from the supplied base Extended Display + * Identification Data (EDID) to an integer in Q0.10 Format. To convert back + * to float divide the fixed point value by 2^10. + * + * @param EdidRaw is the supplied base EDID to retrieve chromaticity + * information from. + * + * @return The y chromatacity coordinate for white. + * + * @note All values will be accurate to +/-0.0005. + * +*******************************************************************************/ +int XVidC_EdidGetCcWhiteY(const u8 *EdidRaw) +{ + return XVidC_CalculateBinaryFraction_QFormat( + (EdidRaw[XVIDC_EDID_CC_WHITEY_HIGH] << + XVIDC_EDID_CC_HIGH_SHIFT) | (EdidRaw[XVIDC_EDID_CC_BW_LOW] & + XVIDC_EDID_CC_GWY_LOW_MASK), 10); +} + +/******************************************************************************/ +/** + * Retrieves the active vertical resolution from the standard timings field of + * the supplied base Extended Display Identification Data (EDID). + * + * @param EdidRaw is the supplied base EDID to check the timing against. + * @param StdTimingsNum specifies which one of the standard timings to + * retrieve from the standard timings field. + * + * @return The vertical active resolution of the specified standard timing + * from the supplied base EDID. + * + * @note StdTimingsNum is an index 1-8. + * +*******************************************************************************/ +u16 XVidC_EdidGetStdTimingsV(const u8 *EdidRaw, u8 StdTimingsNum) +{ + u16 V; + + switch (XVidC_EdidGetStdTimingsAr(EdidRaw, StdTimingsNum)) { + case XVIDC_EDID_STD_TIMINGS_AR_16_10: + V = (10 * XVidC_EdidGetStdTimingsH(EdidRaw, + StdTimingsNum)) / 16; + break; + + case XVIDC_EDID_STD_TIMINGS_AR_4_3: + V = (3 * XVidC_EdidGetStdTimingsH(EdidRaw, + StdTimingsNum)) / 4; + break; + + case XVIDC_EDID_STD_TIMINGS_AR_5_4: + V = (4 * XVidC_EdidGetStdTimingsH(EdidRaw, + StdTimingsNum)) / 5; + break; + + case XVIDC_EDID_STD_TIMINGS_AR_16_9: + V = (9 * XVidC_EdidGetStdTimingsH(EdidRaw, + StdTimingsNum)) / 16; + break; + default: + V = 0; + break; + } + + return V; +} + +/******************************************************************************/ +/** + * Checks whether or not a specified video timing mode is supported as specified + * in the supplied base Extended Display Identification Data (EDID). The + * preferred timing, established timings (I, II, II), and the standard timings + * fields are checked for support. + * + * @param EdidRaw is the supplied base EDID to check the timing against. + * @param VtMode is the video timing mode to check for support. + * + * @return + * - XST_SUCCESS if the video timing mode is supported as specified + * in the supplied base EDID. + * - XST_FAILURE otherwise. + * + * @note None. + * +*******************************************************************************/ +u32 XVidC_EdidIsVideoTimingSupported(const u8 *EdidRaw, + const XVidC_VideoTimingMode *VtMode) +{ + u32 Status; + + /* Check if the video mode is the preferred timing. */ + Status = XVidC_EdidIsVideoTimingSupportedPreferredTiming(EdidRaw, + VtMode); + if (Status == XST_SUCCESS) { + return Status; + } + + /* Check established timings I, II, and III. */ + Status = XVidC_EdidIsVideoTimingSupportedEstablishedTimings(EdidRaw, + VtMode); + if (Status == XST_SUCCESS) { + return Status; + } + + /* Check in standard timings support. */ + Status = XVidC_EdidIsVideoTimingSupportedStandardTimings(EdidRaw, + VtMode); + + return Status; +} + +/******************************************************************************/ +/** + * Checks whether or not a specified video timing mode is the preferred timing + * of the supplied base Extended Display Identification Data (EDID). + * + * @param EdidRaw is the supplied base EDID to check the timing against. + * @param VtMode is the video timing mode to check for support. + * + * @return + * - XST_SUCCESS if the video timing mode is the preferred timing + * as specified in the base EDID. + * - XST_FAILURE otherwise. + * + * @note None. + * +*******************************************************************************/ +static u32 XVidC_EdidIsVideoTimingSupportedPreferredTiming(const u8 *EdidRaw, + const XVidC_VideoTimingMode *VtMode) +{ + const u8 *Ptm; + + Ptm = &EdidRaw[XVIDC_EDID_PTM]; + + u32 HActive = (((Ptm[XVIDC_EDID_DTD_PTM_HRES_HBLANK_U4] & + XVIDC_EDID_DTD_PTM_XRES_XBLANK_U4_XRES_MASK) >> + XVIDC_EDID_DTD_PTM_XRES_XBLANK_U4_XRES_SHIFT) << 8) | + Ptm[XVIDC_EDID_DTD_PTM_HRES_LSB]; + + u32 VActive = (((Ptm[XVIDC_EDID_DTD_PTM_VRES_VBLANK_U4] & + XVIDC_EDID_DTD_PTM_XRES_XBLANK_U4_XRES_MASK) >> + XVIDC_EDID_DTD_PTM_XRES_XBLANK_U4_XRES_SHIFT) << 8) | + Ptm[XVIDC_EDID_DTD_PTM_VRES_LSB]; + + if (VtMode->Timing.F1VTotal != XVidC_EdidIsDtdPtmInterlaced(EdidRaw)) { + return (XST_FAILURE); + } + else if ((VtMode->Timing.HActive == HActive) && + (VtMode->Timing.VActive == VActive)) { + return (XST_SUCCESS); + } + + return XST_FAILURE; +} + +/******************************************************************************/ +/** + * Checks whether or not a specified video timing mode is supported in the + * established timings field of the supplied base Extended Display + * Identification Data (EDID). + * + * @param EdidRaw is the supplied base EDID to check the timing against. + * @param VtMode is the video timing mode to check for support. + * + * @return + * - XST_SUCCESS if the video timing mode is supported in the + * base EDID's established timings field. + * - XST_FAILURE otherwise. + * + * @note None. + * +*******************************************************************************/ +static u32 XVidC_EdidIsVideoTimingSupportedEstablishedTimings(const u8 *EdidRaw, + const XVidC_VideoTimingMode *VtMode) +{ + u32 Status = XST_FAILURE; + + /* Check established timings I, II, and III. */ + if ((VtMode->Timing.HActive == 800) && + (VtMode->Timing.VActive == 640) && + (VtMode->FrameRate == XVIDC_FR_56HZ) && + XVidC_EdidSuppEstTimings800x600_56(EdidRaw)) { + Status = XST_SUCCESS; + } + else if ((VtMode->Timing.HActive == 640) && + (VtMode->Timing.VActive == 480) && + (VtMode->FrameRate == XVIDC_FR_60HZ) && + XVidC_EdidSuppEstTimings640x480_60(EdidRaw)) { + Status = XST_SUCCESS; + } + else if ((VtMode->Timing.HActive == 800) && + (VtMode->Timing.VActive == 600) && + (VtMode->FrameRate == XVIDC_FR_60HZ) && + XVidC_EdidSuppEstTimings800x600_60(EdidRaw)) { + Status = XST_SUCCESS; + } + else if ((VtMode->Timing.HActive == 1024) && + (VtMode->Timing.VActive == 768) && + (VtMode->FrameRate == XVIDC_FR_60HZ) && + XVidC_EdidSuppEstTimings1024x768_60(EdidRaw)) { + Status = XST_SUCCESS; + } + else if ((VtMode->Timing.HActive == 640) && + (VtMode->Timing.VActive == 480) && + (VtMode->FrameRate == XVIDC_FR_67HZ) && + XVidC_EdidSuppEstTimings640x480_67(EdidRaw)) { + Status = XST_SUCCESS; + } + else if ((VtMode->Timing.HActive == 720) && + (VtMode->Timing.VActive == 400) && + (VtMode->FrameRate == XVIDC_FR_70HZ) && + XVidC_EdidSuppEstTimings720x400_70(EdidRaw)) { + Status = XST_SUCCESS; + } + else if ((VtMode->Timing.HActive == 1024) && + (VtMode->Timing.VActive == 768) && + (VtMode->FrameRate == XVIDC_FR_70HZ) && + XVidC_EdidSuppEstTimings1024x768_70(EdidRaw)) { + Status = XST_SUCCESS; + } + else if ((VtMode->Timing.HActive == 640) && + (VtMode->Timing.VActive == 480) && + (VtMode->FrameRate == XVIDC_FR_72HZ) && + XVidC_EdidSuppEstTimings640x480_72(EdidRaw)) { + Status = XST_SUCCESS; + } + else if ((VtMode->Timing.HActive == 800) && + (VtMode->Timing.VActive == 600) && + (VtMode->FrameRate == XVIDC_FR_72HZ) && + XVidC_EdidSuppEstTimings800x600_72(EdidRaw)) { + Status = XST_SUCCESS; + } + else if ((VtMode->Timing.HActive == 640) && + (VtMode->Timing.VActive == 480) && + (VtMode->FrameRate == XVIDC_FR_75HZ) && + XVidC_EdidSuppEstTimings640x480_75(EdidRaw)) { + Status = XST_SUCCESS; + } + else if ((VtMode->Timing.HActive == 800) && + (VtMode->Timing.VActive == 600) && + (VtMode->FrameRate == XVIDC_FR_75HZ) && + XVidC_EdidSuppEstTimings800x600_75(EdidRaw)) { + Status = XST_SUCCESS; + } + else if ((VtMode->Timing.HActive == 832) && + (VtMode->Timing.VActive == 624) && + (VtMode->FrameRate == XVIDC_FR_75HZ) && + XVidC_EdidSuppEstTimings832x624_75(EdidRaw)) { + Status = XST_SUCCESS; + } + else if ((VtMode->Timing.HActive == 1024) && + (VtMode->Timing.VActive == 768) && + (VtMode->FrameRate == XVIDC_FR_75HZ) && + XVidC_EdidSuppEstTimings1024x768_75(EdidRaw)) { + Status = XST_SUCCESS; + } + else if ((VtMode->Timing.HActive == 1152) && + (VtMode->Timing.VActive == 870) && + (VtMode->FrameRate == XVIDC_FR_75HZ) && + XVidC_EdidSuppEstTimings1152x870_75(EdidRaw)) { + Status = XST_SUCCESS; + } + else if ((VtMode->Timing.HActive == 1280) && + (VtMode->Timing.VActive == 1024) && + (VtMode->FrameRate == XVIDC_FR_75HZ) && + XVidC_EdidSuppEstTimings1280x1024_75(EdidRaw)) { + Status = XST_SUCCESS; + } + else if ((VtMode->Timing.HActive == 1024) && + (VtMode->Timing.VActive == 768) && + (VtMode->FrameRate == XVIDC_FR_87HZ) && + XVidC_EdidSuppEstTimings1024x768_87(EdidRaw)) { + Status = XST_SUCCESS; + } + else if ((VtMode->Timing.HActive == 720) && + (VtMode->Timing.VActive == 400) && + (VtMode->FrameRate == XVIDC_FR_88HZ) && + XVidC_EdidSuppEstTimings720x400_88(EdidRaw)) { + Status = XST_SUCCESS; + } + + return Status; +} + +/******************************************************************************/ +/** + * Checks whether or not a specified video timing mode is supported in the + * standard timings field of the supplied base Extended Display Identification + * Data (EDID). + * + * @param EdidRaw is the supplied base EDID to check the timing against. + * @param VtMode is the video timing mode to check for support. + * + * @return + * - XST_SUCCESS if the video timing mode is supported in the + * base EDID's standard timings fields. + * - XST_FAILURE otherwise. + * + * @note None. + * +*******************************************************************************/ +static u32 XVidC_EdidIsVideoTimingSupportedStandardTimings(const u8 *EdidRaw, + const XVidC_VideoTimingMode *VtMode) +{ + u8 Index; + + for (Index = 0; Index < 8; Index++) { + if ((VtMode->Timing.HActive == + XVidC_EdidGetStdTimingsH(EdidRaw, Index + 1)) && + (VtMode->Timing.VActive == + XVidC_EdidGetStdTimingsV(EdidRaw, Index + 1)) && + (VtMode->FrameRate == (u8)XVidC_EdidGetStdTimingsFrr( + EdidRaw, Index + 1))) { + return XST_SUCCESS; + } + } + + return XST_FAILURE; +} + +/******************************************************************************/ +/** + * Perform a power operation. + * + * @param Base is b in the power operation, b^n. + * @param Power is n in the power operation, b^n. + * + * @return Base^Power (Base to the power of Power). + * + * @note None. + * +*******************************************************************************/ +static int XVidC_CalculatePower(u8 Base, u8 Power) +{ + u8 Index; + u32 Res = 1; + + for (Index = 0; Index < Power; Index++) { + Res *= Base; + } + + return Res; +} + + +/******************************************************************************/ +/** + * Convert a fractional binary number into a fixed point Q0.DecPtIndex number + * Binary digits to the right of the decimal point represent 2^-1 to + * 2^-(DecPtIndex+1). Binary digits to the left of the decimal point represent + * 2^0, 2^1, etc. For a given Q format, using an unsigned integer container with + * n fractional bits: + * its range is [0, 2^-n] + * its resolution is 2^n + * + * @param Val is the binary representation of the fraction. + * @param DecPtIndex is the index of the decimal point in the binary + * number. The decimal point is between the binary digits at Val's + * indices (DecPtIndex -1) and (DecPtIndex). DecPtIndex will + * determine the Q format resolution. + * + * @return Fixed point representation of the fractional part of the binary + * number in Q format. + * + * @note None. + * +*******************************************************************************/ +static int XVidC_CalculateBinaryFraction_QFormat(u16 Val, u8 DecPtIndex) +{ + int Index; + u32 Res; + + for (Index = DecPtIndex - 1, Res = 0; Index >= 0; Index--) { + if (((Val >> Index) & 0x1) == 1) { + Res += XVidC_CalculatePower(2 , Index); + } + } + + return Res; +} +/** @} */ diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/video_common_v4_3/src/xvidc_edid.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/video_common_v4_3/src/xvidc_edid.h new file mode 100644 index 000000000..347b4f362 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/video_common_v4_3/src/xvidc_edid.h @@ -0,0 +1,484 @@ +/******************************************************************************* + * + * Copyright (C) 2017 Xilinx, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * Use of the Software is limited solely to applications: + * (a) running on a Xilinx device, or + * (b) that interact with a Xilinx device through a bus or interconnect. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of the Xilinx shall not be used + * in advertising or otherwise to promote the sale, use or other dealings in + * this Software without prior written authorization from Xilinx. + * +*******************************************************************************/ +/******************************************************************************/ +/** + * + * @file xvidc_edid.h + * @addtogroup video_common_v4_2 + * @{ + * + * Contains macros, definitions, and function declarations related to the + * Extended Display Identification Data (EDID) structure which is present in all + * monitors. All content in this file is agnostic of communication interface + * protocol. + * + * @note None. + * + * 
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -----------------------------------------------
+ * 1.0   als  11/09/14 Initial release.
+ * 2.2   als  02/01/16 Functions with pointer arguments that don't modify
+ *                     contents now const.
+ * 4.0   aad  10/26/16 Functions which return fixed point values instead of
+ *		       float
+ *
+ * +*******************************************************************************/ + +#ifndef XVIDC_EDID_H_ +/* Prevent circular inclusions by using protection macros. */ +#define XVIDC_EDID_H_ + +#ifdef __cplusplus +extern "C" { +#endif +/******************************* Include Files ********************************/ + +#include "xstatus.h" +#include "xvidc.h" + +/************************** Constant Definitions ******************************/ + +/** @name Address mapping for the base EDID block. + * @{ + */ +#define XVIDC_EDID_HEADER 0x00 +/* Vendor and product identification. */ +#define XVIDC_EDID_VPI_ID_MAN_NAME0 0x08 +#define XVIDC_EDID_VPI_ID_MAN_NAME1 0x09 +#define XVIDC_EDID_VPI_ID_PROD_CODE_LSB 0x0A +#define XVIDC_EDID_VPI_ID_PROD_CODE_MSB 0x0B +#define XVIDC_EDID_VPI_ID_SN0 0x0C +#define XVIDC_EDID_VPI_ID_SN1 0x0D +#define XVIDC_EDID_VPI_ID_SN2 0x0E +#define XVIDC_EDID_VPI_ID_SN3 0x0F +#define XVIDC_EDID_VPI_WEEK_MAN 0x10 +#define XVIDC_EDID_VPI_YEAR 0x11 +/* EDID structure version and revision. */ +#define XVIDC_EDID_STRUCT_VER 0x12 +#define XVIDC_EDID_STRUCT_REV 0x13 +/* Basic display parameters and features. */ +#define XVIDC_EDID_BDISP_VID 0x14 +#define XVIDC_EDID_BDISP_H_SSAR 0x15 +#define XVIDC_EDID_BDISP_V_SSAR 0x16 +#define XVIDC_EDID_BDISP_GAMMA 0x17 +#define XVIDC_EDID_BDISP_FEATURE 0x18 +/* Color characteristics (display x,y chromaticity coordinates). */ +#define XVIDC_EDID_CC_RG_LOW 0x19 +#define XVIDC_EDID_CC_BW_LOW 0x1A +#define XVIDC_EDID_CC_REDX_HIGH 0x1B +#define XVIDC_EDID_CC_REDY_HIGH 0x1C +#define XVIDC_EDID_CC_GREENX_HIGH 0x1D +#define XVIDC_EDID_CC_GREENY_HIGH 0x1E +#define XVIDC_EDID_CC_BLUEX_HIGH 0x1F +#define XVIDC_EDID_CC_BLUEY_HIGH 0x20 +#define XVIDC_EDID_CC_WHITEX_HIGH 0x21 +#define XVIDC_EDID_CC_WHITEY_HIGH 0x22 +/* Established timings. */ +#define XVIDC_EDID_EST_TIMINGS_I 0x23 +#define XVIDC_EDID_EST_TIMINGS_II 0x24 +#define XVIDC_EDID_EST_TIMINGS_MAN 0x25 +/* Standard timings. */ +#define XVIDC_EDID_STD_TIMINGS_H(N) (0x26 + 2 * (N - 1)) +#define XVIDC_EDID_STD_TIMINGS_AR_FRR(N) (0x27 + 2 * (N - 1)) +/* 18 byte descriptors. */ +#define XVIDC_EDID_18BYTE_DESCRIPTOR(N) (0x36 + 18 * (N - 1)) +#define XVIDC_EDID_PTM (XVIDC_EDID_18BYTE_DESCRIPTOR(1)) +/* - Detailed timing descriptor (DTD) / Preferred timing mode (PTM). */ +#define XVIDC_EDID_DTD_PTM_PIXEL_CLK_KHZ_LSB 0x00 +#define XVIDC_EDID_DTD_PTM_PIXEL_CLK_KHZ_MSB 0x01 +#define XVIDC_EDID_DTD_PTM_HRES_LSB 0x02 +#define XVIDC_EDID_DTD_PTM_HBLANK_LSB 0x03 +#define XVIDC_EDID_DTD_PTM_HRES_HBLANK_U4 0x04 +#define XVIDC_EDID_DTD_PTM_VRES_LSB 0x05 +#define XVIDC_EDID_DTD_PTM_VBLANK_LSB 0x06 +#define XVIDC_EDID_DTD_PTM_VRES_VBLANK_U4 0x07 +#define XVIDC_EDID_DTD_PTM_HFPORCH_LSB 0x08 +#define XVIDC_EDID_DTD_PTM_HSPW_LSB 0x09 +#define XVIDC_EDID_DTD_PTM_VFPORCH_VSPW_L4 0x0A +#define XVIDC_EDID_DTD_PTM_XFPORCH_XSPW_U2 0x0B +#define XVIDC_EDID_DTD_PTM_HIMGSIZE_MM_LSB 0x0C +#define XVIDC_EDID_DTD_PTM_VIMGSIZE_MM_LSB 0x0D +#define XVIDC_EDID_DTD_PTM_XIMGSIZE_MM_U4 0x0E +#define XVIDC_EDID_DTD_PTM_HBORDER 0x0F +#define XVIDC_EDID_DTD_PTM_VBORDER 0x10 +#define XVIDC_EDID_DTD_PTM_SIGNAL 0x11 + +/* Extension block count. */ +#define XVIDC_EDID_EXT_BLK_COUNT 0x7E +/* Checksum. */ +#define XVIDC_EDID_CHECKSUM 0x7F +/* @} */ + +/******************************************************************************/ + +/** @name Extended Display Identification Data: Masks, shifts, and values. + * @{ + */ +#define XVIDC_EDID_VPI_ID_MAN_NAME0_CHAR0_SHIFT 2 +#define XVIDC_EDID_VPI_ID_MAN_NAME0_CHAR0_MASK (0x1F << 2) +#define XVIDC_EDID_VPI_ID_MAN_NAME0_CHAR1_MASK 0x03 +#define XVIDC_EDID_VPI_ID_MAN_NAME0_CHAR1_POS 3 +#define XVIDC_EDID_VPI_ID_MAN_NAME1_CHAR1_SHIFT 5 +#define XVIDC_EDID_VPI_ID_MAN_NAME1_CHAR2_MASK 0x1F + +/* Basic display parameters and features: Video input definition. */ +#define XVIDC_EDID_BDISP_VID_VSI_SHIFT 7 +#define XVIDC_EDID_BDISP_VID_VSI_MASK (0x01 << 7) +#define XVIDC_EDID_BDISP_VID_ANA_SLS_SHIFT 5 +#define XVIDC_EDID_BDISP_VID_ANA_SLS_MASK (0x03 << 5) +#define XVIDC_EDID_BDISP_VID_ANA_SLS_0700_0300_1000 0x0 +#define XVIDC_EDID_BDISP_VID_ANA_SLS_0714_0286_1000 0x1 +#define XVIDC_EDID_BDISP_VID_ANA_SLS_1000_0400_1400 0x2 +#define XVIDC_EDID_BDISP_VID_ANA_SLS_0700_0000_0700 0x3 +#define XVIDC_EDID_BDISP_VID_ANA_VID_SETUP_MASK (0x01 << 4) +#define XVIDC_EDID_BDISP_VID_ANA_SEP_SYNC_HV_MASK (0x01 << 3) +#define XVIDC_EDID_BDISP_VID_ANA_COMP_SYNC_H_MASK (0x01 << 2) +#define XVIDC_EDID_BDISP_VID_ANA_COMP_SYNC_G_MASK (0x01 << 1) +#define XVIDC_EDID_BDISP_VID_ANA_SERR_V_SYNC_MASK (0x01) +#define XVIDC_EDID_BDISP_VID_DIG_BPC_SHIFT 4 +#define XVIDC_EDID_BDISP_VID_DIG_BPC_MASK (0x7 << 4) +#define XVIDC_EDID_BDISP_VID_DIG_BPC_UNDEF 0x0 +#define XVIDC_EDID_BDISP_VID_DIG_BPC_6 0x1 +#define XVIDC_EDID_BDISP_VID_DIG_BPC_8 0x2 +#define XVIDC_EDID_BDISP_VID_DIG_BPC_10 0x3 +#define XVIDC_EDID_BDISP_VID_DIG_BPC_12 0x4 +#define XVIDC_EDID_BDISP_VID_DIG_BPC_14 0x5 +#define XVIDC_EDID_BDISP_VID_DIG_BPC_16 0x6 +#define XVIDC_EDID_BDISP_VID_DIG_VIS_MASK 0xF +#define XVIDC_EDID_BDISP_VID_DIG_VIS_UNDEF 0x0 +#define XVIDC_EDID_BDISP_VID_DIG_VIS_DVI 0x1 +#define XVIDC_EDID_BDISP_VID_DIG_VIS_HDMIA 0x2 +#define XVIDC_EDID_BDISP_VID_DIG_VIS_HDMIB 0x3 +#define XVIDC_EDID_BDISP_VID_DIG_VIS_MDDI 0x4 +#define XVIDC_EDID_BDISP_VID_DIG_VIS_DP 0x5 + +/* Basic display parameters and features: Feature support. */ +#define XVIDC_EDID_BDISP_FEATURE_PM_STANDBY_MASK (0x1 << 7) +#define XVIDC_EDID_BDISP_FEATURE_PM_SUSPEND_MASK (0x1 << 6) +#define XVIDC_EDID_BDISP_FEATURE_PM_OFF_VLP_MASK (0x1 << 5) +#define XVIDC_EDID_BDISP_FEATURE_ANA_COLORTYPE_SHIFT 3 +#define XVIDC_EDID_BDISP_FEATURE_ANA_COLORTYPE_MASK (0x3 << 3) +#define XVIDC_EDID_BDISP_FEATURE_ANA_COLORTYPE_MCG 0x0 +#define XVIDC_EDID_BDISP_FEATURE_ANA_COLORTYPE_RGB 0x1 +#define XVIDC_EDID_BDISP_FEATURE_ANA_COLORTYPE_NRGB 0x2 +#define XVIDC_EDID_BDISP_FEATURE_ANA_COLORTYPE_UNDEF 0x3 +#define XVIDC_EDID_BDISP_FEATURE_DIG_COLORENC_YCRCB444_MASK (0x1 << 3) +#define XVIDC_EDID_BDISP_FEATURE_DIG_COLORENC_YCRCB422_MASK (0x1 << 4) +#define XVIDC_EDID_BDISP_FEATURE_SRGB_DEF_MASK (0x1 << 2) +#define XVIDC_EDID_BDISP_FEATURE_PTM_INC_MASK (0x1 << 1) +#define XVIDC_EDID_BDISP_FEATURE_CONTFREQ_MASK (0x1) + +/* Color characteristics (display x,y chromaticity coordinates). */ +#define XVIDC_EDID_CC_HIGH_SHIFT 2 +#define XVIDC_EDID_CC_RBX_LOW_SHIFT 6 +#define XVIDC_EDID_CC_RBY_LOW_SHIFT 4 +#define XVIDC_EDID_CC_RBY_LOW_MASK (0x3 << 4) +#define XVIDC_EDID_CC_GWX_LOW_SHIFT 2 +#define XVIDC_EDID_CC_GWX_LOW_MASK (0x3 << 2) +#define XVIDC_EDID_CC_GWY_LOW_MASK (0x3) +#define XVIDC_EDID_CC_GREENY_HIGH 0x1E +#define XVIDC_EDID_CC_BLUEX_HIGH 0x1F +#define XVIDC_EDID_CC_BLUEY_HIGH 0x20 +#define XVIDC_EDID_CC_WHITEX_HIGH 0x21 +#define XVIDC_EDID_CC_WHITEY_HIGH 0x22 + +/* Established timings. */ +#define XVIDC_EDID_EST_TIMINGS_I_720x400_70_MASK (0x1 << 7) +#define XVIDC_EDID_EST_TIMINGS_I_720x400_88_MASK (0x1 << 6) +#define XVIDC_EDID_EST_TIMINGS_I_640x480_60_MASK (0x1 << 5) +#define XVIDC_EDID_EST_TIMINGS_I_640x480_67_MASK (0x1 << 4) +#define XVIDC_EDID_EST_TIMINGS_I_640x480_72_MASK (0x1 << 3) +#define XVIDC_EDID_EST_TIMINGS_I_640x480_75_MASK (0x1 << 2) +#define XVIDC_EDID_EST_TIMINGS_I_800x600_56_MASK (0x1 << 1) +#define XVIDC_EDID_EST_TIMINGS_I_800x600_60_MASK (0x1) +#define XVIDC_EDID_EST_TIMINGS_II_800x600_72_MASK (0x1 << 7) +#define XVIDC_EDID_EST_TIMINGS_II_800x600_75_MASK (0x1 << 6) +#define XVIDC_EDID_EST_TIMINGS_II_832x624_75_MASK (0x1 << 5) +#define XVIDC_EDID_EST_TIMINGS_II_1024x768_87_MASK (0x1 << 4) +#define XVIDC_EDID_EST_TIMINGS_II_1024x768_60_MASK (0x1 << 3) +#define XVIDC_EDID_EST_TIMINGS_II_1024x768_70_MASK (0x1 << 2) +#define XVIDC_EDID_EST_TIMINGS_II_1024x768_75_MASK (0x1 << 1) +#define XVIDC_EDID_EST_TIMINGS_II_1280x1024_75_MASK (0x1) +#define XVIDC_EDID_EST_TIMINGS_MAN_1152x870_75_MASK (0x1 << 7) +#define XVIDC_EDID_EST_TIMINGS_MAN_MASK (0x7F) + +/* Standard timings. */ +#define XVIDC_EDID_STD_TIMINGS_AR_SHIFT 6 +#define XVIDC_EDID_STD_TIMINGS_AR_16_10 0x0 +#define XVIDC_EDID_STD_TIMINGS_AR_4_3 0x1 +#define XVIDC_EDID_STD_TIMINGS_AR_5_4 0x2 +#define XVIDC_EDID_STD_TIMINGS_AR_16_9 0x3 +#define XVIDC_EDID_STD_TIMINGS_FRR_MASK (0x3F) + +/* Detailed timing descriptor (DTD) / Preferred timing mode (PTM). */ +#define XVIDC_EDID_DTD_PTM_XRES_XBLANK_U4_XBLANK_MASK 0x0F +#define XVIDC_EDID_DTD_PTM_XRES_XBLANK_U4_XRES_MASK 0xF0 +#define XVIDC_EDID_DTD_PTM_XRES_XBLANK_U4_XRES_SHIFT 4 +#define XVIDC_EDID_DTD_PTM_VFPORCH_VSPW_L4_VSPW_MASK 0x0F +#define XVIDC_EDID_DTD_PTM_VFPORCH_VSPW_L4_VFPORCH_MASK 0xF0 +#define XVIDC_EDID_DTD_PTM_VFPORCH_VSPW_L4_VFPORCH_SHIFT 4 +#define XVIDC_EDID_DTD_PTM_XFPORCH_XSPW_U2_HFPORCH_MASK 0xC0 +#define XVIDC_EDID_DTD_PTM_XFPORCH_XSPW_U2_HSPW_MASK 0x30 +#define XVIDC_EDID_DTD_PTM_XFPORCH_XSPW_U2_VFPORCH_MASK 0x0C +#define XVIDC_EDID_DTD_PTM_XFPORCH_XSPW_U2_VSPW_MASK 0x03 +#define XVIDC_EDID_DTD_PTM_XFPORCH_XSPW_U2_HFPORCH_SHIFT 6 +#define XVIDC_EDID_DTD_PTM_XFPORCH_XSPW_U2_HSPW_SHIFT 4 +#define XVIDC_EDID_DTD_PTM_XFPORCH_XSPW_U2_VFPORCH_SHIFT 2 +#define XVIDC_EDID_DTD_PTM_XIMGSIZE_MM_U4_VIMGSIZE_MM_MASK 0x0F +#define XVIDC_EDID_DTD_PTM_XIMGSIZE_MM_U4_HIMGSIZE_MM_MASK 0xF0 +#define XVIDC_EDID_DTD_PTM_XIMGSIZE_MM_U4_HIMGSIZE_MM_SHIFT 4 +#define XVIDC_EDID_DTD_PTM_SIGNAL_INTERLACED_MASK 0x80 +#define XVIDC_EDID_DTD_PTM_SIGNAL_INTERLACED_SHIFT 7 +#define XVIDC_EDID_DTD_PTM_SIGNAL_HPOLARITY_MASK 0x02 +#define XVIDC_EDID_DTD_PTM_SIGNAL_VPOLARITY_MASK 0x04 +#define XVIDC_EDID_DTD_PTM_SIGNAL_HPOLARITY_SHIFT 1 +#define XVIDC_EDID_DTD_PTM_SIGNAL_VPOLARITY_SHIFT 2 +/* @} */ + +/******************* Macros (Inline Functions) Definitions ********************/ + +#define XVidC_EdidIsHeaderValid(E) \ + !memcmp(E, "\x00\xFF\xFF\xFF\xFF\xFF\xFF\x00", 8) + +/* Vendor and product identification: ID manufacturer name. */ +/* void XVidC_EdidGetManName(const u8 *EdidRaw, char ManName[4]); */ + +/* Vendor and product identification: ID product code. */ +#define XVidC_EdidGetIdProdCode(E) \ + ((u16)((E[XVIDC_EDID_VPI_ID_PROD_CODE_MSB] << 8) | \ + E[XVIDC_EDID_VPI_ID_PROD_CODE_LSB])) + +/* Vendor and product identification: ID serial number. */ +#define XVidC_EdidGetIdSn(E) \ + ((u32)((E[XVIDC_EDID_VPI_ID_SN3] << 24) | \ + (E[XVIDC_EDID_VPI_ID_SN2] << 16) | (E[XVIDC_EDID_VPI_ID_SN1] << 8) | \ + E[XVIDC_EDID_VPI_ID_SN0])) + +/* Vendor and product identification: Week and year of manufacture or model + * year. */ +#define XVidC_EdidGetManWeek(E) (E[XVIDC_EDID_VPI_WEEK_MAN]) +#define XVidC_EdidGetModManYear(E) (E[XVIDC_EDID_VPI_YEAR] + 1990) +#define XVidC_EdidIsYearModel(E) (XVidC_EdidGetManWeek(E) == 0xFF) +#define XVidC_EdidIsYearMan(E) (XVidC_EdidGetManWeek(E) != 0xFF) + +/* EDID structure version and revision. */ +#define XVidC_EdidGetStructVer(E) (E[XVIDC_EDID_STRUCT_VER]) +#define XVidC_EdidGetStructRev(E) (E[XVIDC_EDID_STRUCT_REV]) + +/* Basic display parameters and features: Video input definition. */ +#define XVidC_EdidIsDigitalSig(E) \ + ((E[XVIDC_EDID_BDISP_VID] & XVIDC_EDID_BDISP_VID_VSI_MASK) != 0) +#define XVidC_EdidIsAnalogSig(E) \ + ((E[XVIDC_EDID_BDISP_VID] & XVIDC_EDID_BDISP_VID_VSI_MASK) == 0) +#define XVidC_EdidGetAnalogSigLvlStd(E) \ + ((E[XVIDC_EDID_BDISP_VID] & XVIDC_EDID_BDISP_VID_ANA_SLS_MASK) >> \ + XVIDC_EDID_BDISP_VID_ANA_SLS_SHIFT) +#define XVidC_EdidGetAnalogSigVidSetup(E) \ + ((E[XVIDC_EDID_BDISP_VID] & \ + XVIDC_EDID_BDISP_VID_ANA_VID_SETUP_MASK) != 0) +#define XVidC_EdidSuppAnalogSigSepSyncHv(E) \ + ((E[XVIDC_EDID_BDISP_VID] & \ + XVIDC_EDID_BDISP_VID_ANA_SEP_SYNC_HV_MASK) != 0) +#define XVidC_EdidSuppAnalogSigCompSyncH(E) \ + ((E[XVIDC_EDID_BDISP_VID] & \ + XVIDC_EDID_BDISP_VID_ANA_COMP_SYNC_H_MASK) != 0) +#define XVidC_EdidSuppAnalogSigCompSyncG(E) \ + ((E[XVIDC_EDID_BDISP_VID] & \ + XVIDC_EDID_BDISP_VID_ANA_COMP_SYNC_G_MASK) != 0) +#define XVidC_EdidSuppAnalogSigSerrVsync(E) \ + ((E[XVIDC_EDID_BDISP_VID] & \ + XVIDC_EDID_BDISP_VID_ANA_SERR_V_SYNC_MASK) != 0) +/* XVidC_ColorDepth XVidC_EdidGetColorDepth(const u8 *EdidRaw); */ +#define XVidC_EdidGetDigitalSigIfaceStd(E) \ + (E[XVIDC_EDID_BDISP_VID] & XVIDC_EDID_BDISP_VID_DIG_VIS_MASK) + +/* Basic display parameters and features: Horizontal and vertical screen size or + * aspect ratio. */ +#define XVidC_EdidIsSsArDefined(E) \ + ((E[XVIDC_EDID_BDISP_H_SSAR] | E[XVIDC_EDID_BDISP_V_SSAR]) != 0) +#define XVidC_EdidGetSsArH(E) E[XVIDC_EDID_BDISP_H_SSAR] +#define XVidC_EdidGetSsArV(E) E[XVIDC_EDID_BDISP_V_SSAR] +#define XVidC_EdidIsSsArSs(E) \ + ((XVidC_EdidGetSsArH(E) != 0) && (XVidC_EdidGetSsArV(E) != 0)) +#define XVidC_EdidIsSsArArL(E) \ + ((XVidC_EdidGetSsArH(E) != 0) && (XVidC_EdidGetSsArV(E) == 0)) +#define XVidC_EdidIsSsArArP(E) \ + ((XVidC_EdidGetSsArH(E) == 0) && (XVidC_EdidGetSsArV(E) != 0)) +#define XVidC_EdidGetSsArArL(E) \ + ((float)((XVidC_EdidGetSsArH(E) + 99.0) / 100.0)) +#define XVidC_EdidGetSsArArP(E) \ + ((float)(100.0 / (XVidC_EdidGetSsArV(E) + 99.0))) + +/* Basic display parameters and features: Gamma. */ +#define XVidC_EdidIsGammaInExt(E) (E[XVIDC_EDID_BDISP_GAMMA] == 0xFF) +#define XVidC_EdidGetGamma(E) \ + ((float)((E[XVIDC_EDID_BDISP_GAMMA] + 100.0) / 100.0)) + +/* Basic display parameters and features: Feature support. */ +#define XVidC_EdidSuppFeaturePmStandby(E) \ + ((E[XVIDC_EDID_BDISP_FEATURE] & \ + XVIDC_EDID_BDISP_FEATURE_PM_STANDBY_MASK) != 0) +#define XVidC_EdidSuppFeaturePmSuspend(E) \ + ((E[XVIDC_EDID_BDISP_FEATURE] & \ + XVIDC_EDID_BDISP_FEATURE_PM_SUSPEND_MASK) != 0) +#define XVidC_EdidSuppFeaturePmOffVlp(E) \ + ((E[XVIDC_EDID_BDISP_FEATURE] & \ + XVIDC_EDID_BDISP_FEATURE_PM_OFF_VLP_MASK) != 0) +#define XVidC_EdidGetFeatureAnaColorType(E) \ + ((E[XVIDC_EDID_BDISP_FEATURE] & \ + XVIDC_EDID_BDISP_FEATURE_ANA_COLORTYPE_MASK) >> \ + XVIDC_EDID_BDISP_FEATURE_ANA_COLORTYPE_SHIFT) +#define XVidC_EdidSuppFeatureDigColorEncYCrCb444(E) \ + ((E[XVIDC_EDID_BDISP_FEATURE] & \ + XVIDC_EDID_BDISP_FEATURE_DIG_COLORENC_YCRCB444_MASK) != 0) +#define XVidC_EdidSuppFeatureDigColorEncYCrCb422(E) \ + ((E[XVIDC_EDID_BDISP_FEATURE] & \ + XVIDC_EDID_BDISP_FEATURE_DIG_COLORENC_YCRCB422_MASK) != 0) +#define XVidC_EdidIsFeatureSrgbDef(E) \ + ((E[XVIDC_EDID_BDISP_FEATURE] & \ + XVIDC_EDID_BDISP_FEATURE_SRGB_DEF_MASK) != 0) +#define XVidC_EdidIsFeaturePtmInc(E) \ + ((E[XVIDC_EDID_BDISP_FEATURE] & \ + XVIDC_EDID_BDISP_FEATURE_PTM_INC_MASK) != 0) +#define XVidC_EdidIsFeatureContFreq(E) \ + ((E[XVIDC_EDID_BDISP_FEATURE] & \ + XVIDC_EDID_BDISP_FEATURE_CONTFREQ_MASK) != 0) + +/* Established timings. */ +#define XVidC_EdidSuppEstTimings720x400_70(E) \ + ((E[XVIDC_EDID_EST_TIMINGS_I] & \ + XVIDC_EDID_EST_TIMINGS_I_720x400_70_MASK) != 0) +#define XVidC_EdidSuppEstTimings720x400_88(E) \ + ((E[XVIDC_EDID_EST_TIMINGS_I] & \ + XVIDC_EDID_EST_TIMINGS_I_720x400_88_MASK) != 0) +#define XVidC_EdidSuppEstTimings640x480_60(E) \ + ((E[XVIDC_EDID_EST_TIMINGS_I] & \ + XVIDC_EDID_EST_TIMINGS_I_640x480_60_MASK) != 0) +#define XVidC_EdidSuppEstTimings640x480_67(E) \ + ((E[XVIDC_EDID_EST_TIMINGS_I] & \ + XVIDC_EDID_EST_TIMINGS_I_640x480_67_MASK) != 0) +#define XVidC_EdidSuppEstTimings640x480_72(E) \ + ((E[XVIDC_EDID_EST_TIMINGS_I] & \ + XVIDC_EDID_EST_TIMINGS_I_640x480_72_MASK) != 0) +#define XVidC_EdidSuppEstTimings640x480_75(E) \ + ((E[XVIDC_EDID_EST_TIMINGS_I] & \ + XVIDC_EDID_EST_TIMINGS_I_640x480_75_MASK) != 0) +#define XVidC_EdidSuppEstTimings800x600_56(E) \ + ((E[XVIDC_EDID_EST_TIMINGS_I] & \ + XVIDC_EDID_EST_TIMINGS_I_800x600_56_MASK) != 0) +#define XVidC_EdidSuppEstTimings800x600_60(E) \ + ((E[XVIDC_EDID_EST_TIMINGS_I] & \ + XVIDC_EDID_EST_TIMINGS_I_800x600_60_MASK) != 0) +#define XVidC_EdidSuppEstTimings800x600_72(E) \ + ((E[XVIDC_EDID_EST_TIMINGS_II] & \ + XVIDC_EDID_EST_TIMINGS_II_800x600_72_MASK) != 0) +#define XVidC_EdidSuppEstTimings800x600_75(E) \ + ((E[XVIDC_EDID_EST_TIMINGS_II] & \ + XVIDC_EDID_EST_TIMINGS_II_800x600_75_MASK) != 0) +#define XVidC_EdidSuppEstTimings832x624_75(E) \ + ((E[XVIDC_EDID_EST_TIMINGS_II] & \ + XVIDC_EDID_EST_TIMINGS_II_832x624_75_MASK) != 0) +#define XVidC_EdidSuppEstTimings1024x768_87(E) \ + ((E[XVIDC_EDID_EST_TIMINGS_II] & \ + XVIDC_EDID_EST_TIMINGS_II_1024x768_87_MASK) != 0) +#define XVidC_EdidSuppEstTimings1024x768_60(E) \ + ((E[XVIDC_EDID_EST_TIMINGS_II] & \ + XVIDC_EDID_EST_TIMINGS_II_1024x768_60_MASK) != 0) +#define XVidC_EdidSuppEstTimings1024x768_70(E) \ + ((E[XVIDC_EDID_EST_TIMINGS_II] & \ + XVIDC_EDID_EST_TIMINGS_II_1024x768_70_MASK) != 0) +#define XVidC_EdidSuppEstTimings1024x768_75(E) \ + ((E[XVIDC_EDID_EST_TIMINGS_II] & \ + XVIDC_EDID_EST_TIMINGS_II_1024x768_75_MASK) != 0) +#define XVidC_EdidSuppEstTimings1280x1024_75(E) \ + ((E[XVIDC_EDID_EST_TIMINGS_II] & \ + XVIDC_EDID_EST_TIMINGS_II_1280x1024_75_MASK) != 0) +#define XVidC_EdidSuppEstTimings1152x870_75(E) \ + ((E[XVIDC_EDID_EST_TIMINGS_MAN] & \ + XVIDC_EDID_EST_TIMINGS_MAN_1152x870_75_MASK) != 0) +#define XVidC_EdidGetTimingsMan(E) \ + (E[XVIDC_EDID_EST_TIMINGS_MAN] & XVIDC_EDID_EST_TIMINGS_MAN_MASK) + +/* Standard timings. */ +#define XVidC_EdidGetStdTimingsH(E, N) \ + ((E[XVIDC_EDID_STD_TIMINGS_H(N)] + 31) * 8) +#define XVidC_EdidGetStdTimingsAr(E, N) \ + (E[XVIDC_EDID_STD_TIMINGS_AR_FRR(N)] >> XVIDC_EDID_STD_TIMINGS_AR_SHIFT) +#define XVidC_EdidGetStdTimingsFrr(E, N) \ + ((E[XVIDC_EDID_STD_TIMINGS_AR_FRR(N)] & \ + XVIDC_EDID_STD_TIMINGS_FRR_MASK) + 60) +/* u16 XVidC_EdidGetStdTimingsV(const u8 *EdidRaw, u8 StdTimingsNum); */ +#define XVidC_EdidIsDtdPtmInterlaced(E) \ + ((E[XVIDC_EDID_PTM + XVIDC_EDID_DTD_PTM_SIGNAL] & \ + XVIDC_EDID_DTD_PTM_SIGNAL_INTERLACED_MASK) >> \ + XVIDC_EDID_DTD_PTM_SIGNAL_INTERLACED_SHIFT) + +/* Extension block count. */ +#define XVidC_EdidGetExtBlkCount(E) (E[XVIDC_EDID_EXT_BLK_COUNT]) + +/* Checksum. */ +#define XVidC_EdidGetChecksum(E) (E[XVIDC_EDID_CHECKSUM]) + +/**************************** Function Prototypes *****************************/ + +/* Vendor and product identification: ID manufacturer name. */ +void XVidC_EdidGetManName(const u8 *EdidRaw, char ManName[4]); + +/* Basic display parameters and features: Video input definition. */ +XVidC_ColorDepth XVidC_EdidGetColorDepth(const u8 *EdidRaw); + +/* Color characteristics (display x,y chromaticity coordinates). */ +int XVidC_EdidGetCcRedX(const u8 *EdidRaw); +int XVidC_EdidGetCcRedY(const u8 *EdidRaw); +int XVidC_EdidGetCcGreenX(const u8 *EdidRaw); +int XVidC_EdidGetCcGreenY(const u8 *EdidRaw); +int XVidC_EdidGetCcBlueX(const u8 *EdidRaw); +int XVidC_EdidGetCcBlueY(const u8 *EdidRaw); +int XVidC_EdidGetCcWhiteX(const u8 *EdidRaw); +int XVidC_EdidGetCcWhiteY(const u8 *EdidRaw); + +/* Standard timings. */ +u16 XVidC_EdidGetStdTimingsV(const u8 *EdidRaw, u8 StdTimingsNum); + +/* Utility functions. */ +u32 XVidC_EdidIsVideoTimingSupported(const u8 *EdidRaw, + const XVidC_VideoTimingMode *VtMode); + +#ifdef __cplusplus +} +#endif +#endif /* XVIDC_EDID_H_ */ +/** @} */ diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/video_common_v4_3/src/xvidc_edid_ext.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/video_common_v4_3/src/xvidc_edid_ext.c new file mode 100644 index 000000000..c8ce9f125 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/video_common_v4_3/src/xvidc_edid_ext.c @@ -0,0 +1,174 @@ +/****************************************************************************** +* +* Copyright (C) 2017 - 2018 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xhdmi_edid.h +* +* Software Initalization & Configuration +* +* Interrupts +* +* Virtual Memory +* +* This driver supports Virtual Memory. The RTOS is responsible for calculating +* the correct device base address in Virtual Memory space. +* +* Threads +* +* This driver is not thread safe. Any needs for threads or thread mutual +* exclusion must be satisfied by the layer above this driver. +* +* Asserts +* +* Asserts are used within all Xilinx drivers to enforce constraints on argument +* values. Asserts can be turned off on a system-wide basis by defining at +* compile time, the NDEBUG identifier. By default, asserts are turned on and it +* is recommended that users leave asserts on during development. +* +* Building the driver +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date       Changes
+* ----- ---- ---------- --------------------------------------------------
+* 1.0   mmo  24-01-2017 EDID Parser capability
+*
+* +******************************************************************************/ +#include "stdio.h" +#include "string.h" +#include "stdlib.h" +#include "stdbool.h" +#include "xil_types.h" +#include "xstatus.h" +#include "xil_exception.h" +#include "xvidc_edid_ext.h" + +static XV_VidC_PicAspectRatio xv_vidc_getPicAspectRatio(u16 hres, u16 vres); + +static XV_VidC_PicAspectRatio xv_vidc_getPicAspectRatio(u16 hres, u16 vres) { + XV_VidC_PicAspectRatio ar; +#define HAS_RATIO_OF(x, y) (hres == (vres*(x)/(y))&&!((vres*(x))%(y))) + if (HAS_RATIO_OF(16, 10)) { + ar.width = 16; + ar.height = 10; + return ar; + } + if (HAS_RATIO_OF(4, 3)) { + ar.width = 4; + ar.height = 3; + return ar; + } + if (HAS_RATIO_OF(5, 4)) { + ar.width = 5; + ar.height = 4; + return ar; + } + if (HAS_RATIO_OF(16, 9)) { + ar.width = 16; + ar.height = 9; + return ar; +#undef HAS_RATIO + } else { + ar.width = 0; + ar.height = 0; + return ar; + } +} + + +void XV_VidC_EdidCtrlParamInit (XV_VidC_EdidCntrlParam *EdidCtrlParam) { + + /* Verify arguments. */ + Xil_AssertVoid(EdidCtrlParam != NULL); + + (void)memset((void *)EdidCtrlParam, 0, + sizeof(XV_VidC_EdidCntrlParam)); + + EdidCtrlParam->IsHdmi = XVIDC_ISDVI; + EdidCtrlParam->IsYCbCr444Supp = XVIDC_NOT_SUPPORTED; + EdidCtrlParam->IsYCbCr420Supp = XVIDC_NOT_SUPPORTED; + EdidCtrlParam->IsYCbCr422Supp = XVIDC_NOT_SUPPORTED; + EdidCtrlParam->IsYCbCr444DeepColSupp = XVIDC_NOT_SUPPORTED; + EdidCtrlParam->Is30bppSupp = XVIDC_NOT_SUPPORTED; + EdidCtrlParam->Is36bppSupp = XVIDC_NOT_SUPPORTED; + EdidCtrlParam->Is48bppSupp = XVIDC_NOT_SUPPORTED; + EdidCtrlParam->IsYCbCr420dc30bppSupp = XVIDC_NOT_SUPPORTED; + EdidCtrlParam->IsYCbCr420dc36bppSupp = XVIDC_NOT_SUPPORTED; + EdidCtrlParam->IsYCbCr420dc48bppSupp = XVIDC_NOT_SUPPORTED; + EdidCtrlParam->IsSCDCReadRequestReady= XVIDC_NOT_SUPPORTED; + EdidCtrlParam->IsSCDCPresent = XVIDC_NOT_SUPPORTED; + EdidCtrlParam->MaxFrameRateSupp = 0; + EdidCtrlParam->MaxTmdsMhz = 0; +} + +XV_VidC_TimingParam +XV_VidC_timing + (const struct xvidc_edid_detailed_timing_descriptor * const dtb) +{ + XV_VidC_TimingParam timing; + + timing.hres = xvidc_edid_detailed_timing_horizontal_active(dtb); + timing.vres = xvidc_edid_detailed_timing_vertical_active(dtb); + timing.htotal = timing.hres + + xvidc_edid_detailed_timing_horizontal_blanking(dtb); + timing.vtotal = timing.vres + + xvidc_edid_detailed_timing_vertical_blanking(dtb); + timing.hfp = xvidc_edid_detailed_timing_horizontal_sync_offset(dtb); + timing.vfp = xvidc_edid_detailed_timing_vertical_sync_offset(dtb); + timing.hsync_width = + xvidc_edid_detailed_timing_horizontal_sync_pulse_width(dtb); + timing.vsync_width = + xvidc_edid_detailed_timing_vertical_sync_pulse_width(dtb); + timing.pixclk = xvidc_edid_detailed_timing_pixel_clock(dtb); + timing.vfreq = (timing.pixclk / (timing.vtotal * timing.htotal)); + timing.vidfrmt = (XVidC_VideoFormat) dtb->interlaced; + timing.aspect_ratio = + xv_vidc_getPicAspectRatio (timing.hres, timing.vres); + timing.hsync_polarity = dtb->signal_pulse_polarity; + timing.vsync_polarity = dtb->signal_serration_polarity; + + return timing; +} + +#if XVIDC_EDID_VERBOSITY > 1 +XV_VidC_DoubleRep Double2Int (double in_val) { + XV_VidC_DoubleRep DR; + + DR.Integer = in_val; + DR.Decimal = (in_val - DR.Integer) * 10000; + + return (DR); +} +#endif diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/video_common_v4_3/src/xvidc_edid_ext.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/video_common_v4_3/src/xvidc_edid_ext.h new file mode 100644 index 000000000..d685723f5 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/video_common_v4_3/src/xvidc_edid_ext.h @@ -0,0 +1,626 @@ +/* vim: set et fde fdm=syntax ft=c.doxygen ts=4 sts=4 sw=4 : */ +/* + * Copyright © 2010-2011 Saleem Abdulrasool . + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO + * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef xvidc_edid_h +#define xvidc_edid_h + +#include "stdbool.h" +#include "xvidc.h" +#include "xil_assert.h" +#include "xvidc_cea861.h" + +#define XVIDC_EDID_BLOCK_SIZE (0x80) +#define XVIDC_EDID_MAX_EXTENSIONS (0xFE) + + +static const u8 XVIDC_EDID_EXT_HEADER[] = + { 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 }; +static const u8 XVIDC_EDID_STANDARD_TIMING_DESCRIPTOR_INVALID[] = + { 0x01, 0x01 }; + +enum xvidc_edid_extension_type { + XVIDC_EDID_EXTENSION_TIMING = 0x01, /* Timing Extension */ + XVIDC_EDID_EXTENSION_CEA = 0x02, /* Additional Timing Block + Data (CEA EDID Timing Extension)*/ + XVIDC_EDID_EXTENSION_VTB = 0x10, /* Video Timing Block + Extension (VTB-EXT)*/ + XVIDC_EDID_EXTENSION_XVIDC_EDID_2_0= 0x20, /* EDID 2.0 Extension */ + XVIDC_EDID_EXTENSION_DI = 0x40, /* Display Information + Extension (DI-EXT) */ + XVIDC_EDID_EXTENSION_LS = 0x50, /* Localised String + Extension (LS-EXT) */ + XVIDC_EDID_EXTENSION_MI = 0x60, /* Microdisplay Interface + Extension (MI-EXT) */ + XVIDC_EDID_EXTENSION_DTCDB_1 = 0xA7, /* Display Transfer + Characteristics Data Block (DTCDB) */ + XVIDC_EDID_EXTENSION_DTCDB_2 = 0xAF, + XVIDC_EDID_EXTENSION_DTCDB_3 = 0xBF, + XVIDC_EDID_EXTENSION_BLOCK_MAP = 0xF0, /* Block Map*/ + XVIDC_EDID_EXTENSION_DDDB = 0xFF, /* Display Device Data + Block (DDDB)*/ +}; + +enum xvidc_edid_display_type { + XVIDC_EDID_DISPLAY_TYPE_MONOCHROME, + XVIDC_EDID_DISPLAY_TYPE_RGB, + XVIDC_EDID_DISPLAY_TYPE_NON_RGB, + XVIDC_EDID_DISPLAY_TYPE_UNDEFINED, +}; + +enum xvidc_edid_aspect_ratio { + XVIDC_EDID_ASPECT_RATIO_16_10, + XVIDC_EDID_ASPECT_RATIO_4_3, + XVIDC_EDID_ASPECT_RATIO_5_4, + XVIDC_EDID_ASPECT_RATIO_16_9, +}; + +enum xvidc_edid_signal_sync { + XVIDC_EDID_SIGNAL_SYNC_ANALOG_COMPOSITE, + XVIDC_EDID_SIGNAL_SYNC_BIPOLAR_ANALOG_COMPOSITE, + XVIDC_EDID_SIGNAL_SYNC_DIGITAL_COMPOSITE, + XVIDC_EDID_SIGNAL_SYNC_DIGITAL_SEPARATE, +}; + +enum xvidc_edid_stereo_mode { + XVIDC_EDID_STEREO_MODE_NONE, + XVIDC_EDID_STEREO_MODE_RESERVED, + XVIDC_EDID_STEREO_MODE_FIELD_SEQUENTIAL_RIGHT, + XVIDC_EDID_STEREO_MODE_2_WAY_INTERLEAVED_RIGHT, + XVIDC_EDID_STEREO_MODE_FIELD_SEQUENTIAL_LEFT, + XVIDC_EDID_STEREO_MODE_2_WAY_INTERLEAVED_LEFT, + XVIDC_EDID_STEREO_MODE_4_WAY_INTERLEAVED, + XVIDC_EDID_STEREO_MODE_SIDE_BY_SIDE_INTERLEAVED, +}; + +enum xvidc_edid_monitor_descriptor_type { + XVIDC_EDID_MONTIOR_DESCRIPTOR_MANUFACTURER_DEFINED = 0x0F, + XVIDC_EDID_MONITOR_DESCRIPTOR_STANDARD_TIMING_IDENTIFIERS = 0xFA, + XVIDC_EDID_MONITOR_DESCRIPTOR_COLOR_POINT = 0xFB, + XVIDC_EDID_MONITOR_DESCRIPTOR_MONITOR_NAME = 0xFC, + XVIDC_EDID_MONITOR_DESCRIPTOR_MONITOR_RANGE_LIMITS = 0xFD, + XVIDC_EDID_MONITOR_DESCRIPTOR_ASCII_STRING = 0xFE, + XVIDC_EDID_MONITOR_DESCRIPTOR_MONITOR_SERIAL_NUMBER = 0xFF, +}; + +enum xvidc_edid_secondary_timing_support { + XVIDC_EDID_SECONDARY_TIMING_NOT_SUPPORTED, + XVIDC_EDID_SECONDARY_TIMING_GFT = 0x02, +}; + + +struct __attribute__ (( packed )) xvidc_edid_detailed_timing_descriptor { + u16 pixel_clock; /* = value * 10000 */ + + u8 horizontal_active_lo; + u8 horizontal_blanking_lo; + + unsigned horizontal_blanking_hi : 4; + unsigned horizontal_active_hi : 4; + + u8 vertical_active_lo; + u8 vertical_blanking_lo; + + unsigned vertical_blanking_hi : 4; + unsigned vertical_active_hi : 4; + + u8 horizontal_sync_offset_lo; + u8 horizontal_sync_pulse_width_lo; + + unsigned vertical_sync_pulse_width_lo : 4; + unsigned vertical_sync_offset_lo : 4; + + unsigned vertical_sync_pulse_width_hi : 2; + unsigned vertical_sync_offset_hi : 2; + unsigned horizontal_sync_pulse_width_hi : 2; + unsigned horizontal_sync_offset_hi : 2; + + u8 horizontal_image_size_lo; + u8 vertical_image_size_lo; + + unsigned vertical_image_size_hi : 4; + unsigned horizontal_image_size_hi : 4; + + u8 horizontal_border; + u8 vertical_border; + + unsigned stereo_mode_lo : 1; + unsigned signal_pulse_polarity : 1; /* pulse on sync, + composite/horizontal polarity */ + unsigned signal_serration_polarity : 1; /* serrate on sync, vertical + polarity */ + unsigned signal_sync : 2; + unsigned stereo_mode_hi : 2; + unsigned interlaced : 1; +}; + +static inline u32 +xvidc_edid_detailed_timing_pixel_clock + (const struct xvidc_edid_detailed_timing_descriptor * const dtb) +{ + return dtb->pixel_clock * 10000; +} + +static inline u16 +xvidc_edid_detailed_timing_horizontal_blanking + (const struct xvidc_edid_detailed_timing_descriptor * const dtb) +{ + return (dtb->horizontal_blanking_hi << 8) | dtb->horizontal_blanking_lo; +} + +static inline u16 +xvidc_edid_detailed_timing_horizontal_active + (const struct xvidc_edid_detailed_timing_descriptor * const dtb) +{ + return (dtb->horizontal_active_hi << 8) | dtb->horizontal_active_lo; +} + +static inline u16 +xvidc_edid_detailed_timing_vertical_blanking + (const struct xvidc_edid_detailed_timing_descriptor * const dtb) +{ + return (dtb->vertical_blanking_hi << 8) | dtb->vertical_blanking_lo; +} + +static inline u16 +xvidc_edid_detailed_timing_vertical_active + (const struct xvidc_edid_detailed_timing_descriptor * const dtb) +{ + return (dtb->vertical_active_hi << 8) | dtb->vertical_active_lo; +} + +static inline u8 +xvidc_edid_detailed_timing_vertical_sync_offset + (const struct xvidc_edid_detailed_timing_descriptor * const dtb) +{ + return (dtb->vertical_sync_offset_hi << 4) | dtb->vertical_sync_offset_lo; +} + +static inline u8 +xvidc_edid_detailed_timing_vertical_sync_pulse_width + (const struct xvidc_edid_detailed_timing_descriptor * const dtb) +{ + return (dtb->vertical_sync_pulse_width_hi << 4) | + dtb->vertical_sync_pulse_width_lo; +} + +static inline u8 +xvidc_edid_detailed_timing_horizontal_sync_offset + (const struct xvidc_edid_detailed_timing_descriptor * const dtb) +{ + return (dtb->horizontal_sync_offset_hi << 4) | + dtb->horizontal_sync_offset_lo; +} + +static inline u8 +xvidc_edid_detailed_timing_horizontal_sync_pulse_width + (const struct xvidc_edid_detailed_timing_descriptor * const dtb) +{ + return (dtb->horizontal_sync_pulse_width_hi << 4) | + dtb->horizontal_sync_pulse_width_lo; +} + +static inline u16 +xvidc_edid_detailed_timing_horizontal_image_size + (const struct xvidc_edid_detailed_timing_descriptor * const dtb) +{ + return + (dtb->horizontal_image_size_hi << 8) | dtb->horizontal_image_size_lo; +} + +static inline u16 +xvidc_edid_detailed_timing_vertical_image_size + (const struct xvidc_edid_detailed_timing_descriptor * const dtb) +{ + return (dtb->vertical_image_size_hi << 8) | dtb->vertical_image_size_lo; +} + +static inline u8 +xvidc_edid_detailed_timing_stereo_mode + (const struct xvidc_edid_detailed_timing_descriptor * const dtb) +{ + return (dtb->stereo_mode_hi << 2 | dtb->stereo_mode_lo); +} + + +struct __attribute__ (( packed )) xvidc_edid_monitor_descriptor { + u16 flag0; + u8 flag1; + u8 tag; + u8 flag2; + u8 data[13]; +}; + +typedef char xvidc_edid_monitor_descriptor_string + [sizeof(((struct xvidc_edid_monitor_descriptor *)0)->data) + 1]; + + +struct __attribute__ (( packed )) xvidc_edid_monitor_range_limits { + u8 minimum_vertical_rate; /* Hz */ + u8 maximum_vertical_rate; /* Hz */ + u8 minimum_horizontal_rate; /* kHz */ + u8 maximum_horizontal_rate; /* kHz */ + u8 maximum_supported_pixel_clock; /* = (value * 10) Mhz + (round to 10 MHz) */ + + /* secondary timing formula */ + u8 secondary_timing_support; + u8 reserved; + u8 secondary_curve_start_frequency; /* horizontal frequency / 2 kHz */ + u8 c; /* = (value >> 1) */ + u16 m; + u8 k; + u8 j; /* = (value >> 1) */ +}; + + +struct __attribute__ (( packed )) xvidc_edid_standard_timing_descriptor { + u8 horizontal_active_pixels; /* = (value + 31) * 8 */ + + unsigned refresh_rate : 6; /* = value + 60 */ + unsigned image_aspect_ratio : 2; +}; + +inline u32 +xvidc_edid_standard_timing_horizontal_active +(const struct xvidc_edid_standard_timing_descriptor * const desc) { + return ((desc->horizontal_active_pixels + 31) << 3); +} + +inline u32 +xvidc_edid_standard_timing_vertical_active +(const struct xvidc_edid_standard_timing_descriptor * const desc) { + const u32 hres = xvidc_edid_standard_timing_horizontal_active(desc); + + switch (desc->image_aspect_ratio) { + case XVIDC_EDID_ASPECT_RATIO_16_10: + return ((hres * 10) >> 4); + case XVIDC_EDID_ASPECT_RATIO_4_3: + return ((hres * 3) >> 2); + case XVIDC_EDID_ASPECT_RATIO_5_4: + return ((hres << 2) / 5); + case XVIDC_EDID_ASPECT_RATIO_16_9: + return ((hres * 9) >> 4); + } + + return hres; +} + +inline u32 +xvidc_edid_standard_timing_refresh_rate +(const struct xvidc_edid_standard_timing_descriptor * const desc) { + return (desc->refresh_rate + 60); +} + + +struct __attribute__ (( packed )) edid { + /* header information */ + u8 header[8]; + + /* vendor/product identification */ + u16 manufacturer; + union { + u16 product_u16; + u8 product[2]; + }; + union { + u32 serial_number_u32; + u8 serial_number[4]; + }; + u8 manufacture_week; + u8 manufacture_year; /* = value + 1990 */ + + /* EDID version */ + u8 version; + u8 revision; + + /* basic display parameters and features */ + union { + struct __attribute__ (( packed )) { + unsigned dfp_1x : 1; /* VESA DFP 1.x */ + unsigned : 6; + unsigned digital : 1; + } digital; + struct __attribute__ (( packed )) { + unsigned vsync_serration : 1; + unsigned green_video_sync : 1; + unsigned composite_sync : 1; + unsigned separate_sync : 1; + unsigned blank_to_black_setup : 1; + unsigned signal_level_standard : 2; + unsigned digital : 1; + } analog; + } video_input_definition; + + u8 maximum_horizontal_image_size; /* cm */ + u8 maximum_vertical_image_size; /* cm */ + + u8 display_transfer_characteristics; /* gamma = (value + 100) / 100 */ + + struct __attribute__ (( packed )) { + unsigned default_gtf : 1; /* generalised timing + formula */ + unsigned preferred_timing_mode : 1; + unsigned standard_default_color_space : 1; + unsigned display_type : 2; + unsigned active_off : 1; + unsigned suspend : 1; + unsigned standby : 1; + } feature_support; + + /* color characteristics block */ + unsigned green_y_low : 2; + unsigned green_x_low : 2; + unsigned red_y_low : 2; + unsigned red_x_low : 2; + + unsigned white_y_low : 2; + unsigned white_x_low : 2; + unsigned blue_y_low : 2; + unsigned blue_x_low : 2; + + u8 red_x; + u8 red_y; + u8 green_x; + u8 green_y; + u8 blue_x; + u8 blue_y; + u8 white_x; + u8 white_y; + + /* established timings */ + struct __attribute__ (( packed )) { + unsigned timing_800x600_60 : 1; + unsigned timing_800x600_56 : 1; + unsigned timing_640x480_75 : 1; + unsigned timing_640x480_72 : 1; + unsigned timing_640x480_67 : 1; + unsigned timing_640x480_60 : 1; + unsigned timing_720x400_88 : 1; + unsigned timing_720x400_70 : 1; + + unsigned timing_1280x1024_75 : 1; + unsigned timing_1024x768_75 : 1; + unsigned timing_1024x768_70 : 1; + unsigned timing_1024x768_60 : 1; + unsigned timing_1024x768_87 : 1; + unsigned timing_832x624_75 : 1; + unsigned timing_800x600_75 : 1; + unsigned timing_800x600_72 : 1; + } established_timings; + + struct __attribute__ (( packed )) { + unsigned reserved : 7; + unsigned timing_1152x870_75 : 1; + } manufacturer_timings; + + /* standard timing id */ + struct xvidc_edid_standard_timing_descriptor standard_timing_id[8]; + + /* detailed timing */ + union { + struct xvidc_edid_monitor_descriptor monitor; + struct xvidc_edid_detailed_timing_descriptor timing; + } detailed_timings[4]; + + u8 extensions; + u8 checksum; +}; + +static inline void +xvidc_edid_manufacturer(const struct edid * const edid, char manufacturer[4]) +{ + manufacturer[0] = '@' + ((edid->manufacturer & 0x007c) >> 2); + manufacturer[1] = '@' + ((((edid->manufacturer & 0x0003) >> 00) << 3) | (((edid->manufacturer & 0xe000) >> 13) << 0)); + manufacturer[2] = '@' + ((edid->manufacturer & 0x1f00) >> 8); + manufacturer[3] = '\0'; +} + +static inline double +xvidc_edid_gamma(const struct edid * const edid) +{ + return (edid->display_transfer_characteristics + 100) / 100.0; +} + +static inline bool +xvidc_edid_detailed_timing_is_monitor_descriptor(const struct edid * const edid, + const u8 timing) +{ + const struct xvidc_edid_monitor_descriptor * const mon = + &edid->detailed_timings[timing].monitor; + + Xil_AssertNonvoid(timing < ARRAY_SIZE(edid->detailed_timings)); + + return mon->flag0 == 0x0000 && mon->flag1 == 0x00 && mon->flag2 == 0x00; +} + + +struct __attribute__ (( packed )) xvidc_edid_color_characteristics_data { + struct { + u16 x; + u16 y; + } red, green, blue, white; +}; + +static inline struct xvidc_edid_color_characteristics_data +xvidc_edid_color_characteristics(const struct edid * const edid) +{ + const struct xvidc_edid_color_characteristics_data characteristics = { + .red = { + .x = (edid->red_x << 2) | edid->red_x_low, + .y = (edid->red_y << 2) | edid->red_y_low, + }, + .green = { + .x = (edid->green_x << 2) | edid->green_x_low, + .y = (edid->green_y << 2) | edid->green_y_low, + }, + .blue = { + .x = (edid->blue_x << 2) | edid->blue_x_low, + .y = (edid->blue_y << 2) | edid->blue_y_low, + }, + .white = { + .x = (edid->white_x << 2) | edid->white_x_low, + .y = (edid->white_y << 2) | edid->white_y_low, + }, + }; + + return characteristics; +} + + +struct __attribute__ (( packed )) xvidc_edid_block_map { + u8 tag; + u8 extension_tag[126]; + u8 checksum; +}; + + +struct __attribute__ (( packed )) xvidc_edid_extension { + u8 tag; + u8 revision; + u8 extension_data[125]; + u8 checksum; +}; + + +static inline bool +xvidc_edid_verify_checksum(const u8 * const block) +{ + u8 checksum = 0; + int i; + + for (i = 0; i < XVIDC_EDID_BLOCK_SIZE; i++) + checksum += block[i]; + + return (checksum == 0); +} + +static inline double +xvidc_edid_decode_fixed_point(u16 value) +{ + double result = 0.0; + + Xil_AssertNonvoid((~value & 0xfc00) == 0xfc00); + /* edid fraction is 10 bits */ + + for (u8 i = 0; value && (i < 10); i++, value >>= 1) + result = result + ((value & 0x1) * (1.0 / (1 << (10 - i)))); + + return result; +} + +typedef enum { + XVIDC_VERBOSE_DISABLE, + XVIDC_VERBOSE_ENABLE +} XV_VidC_Verbose; + +typedef enum { + XVIDC_ISDVI, + XVIDC_ISHDMI +} XV_VidC_IsHdmi; + +typedef enum { + XVIDC_NOT_SUPPORTED, + XVIDC_SUPPORTED +} XV_VidC_Supp; +#if XVIDC_EDID_VERBOSITY > 1 +typedef struct { + u32 Integer; + u32 Decimal; +} XV_VidC_DoubleRep; +#endif + +typedef struct { + u8 width; + u8 height; +} XV_VidC_PicAspectRatio; + +typedef struct { + u16 hres; + u16 vres; + u16 htotal; + u16 vtotal; + XVidC_VideoFormat vidfrmt; + u32 pixclk; + u16 hsync_width; + u16 vsync_width; + u16 hfp; + u16 vfp; + u8 vfreq; + XV_VidC_PicAspectRatio aspect_ratio; + unsigned hsync_polarity : 1; + unsigned vsync_polarity : 1; +} XV_VidC_TimingParam; + +typedef struct { + /*Checks whether Sink able to support HDMI*/ + XV_VidC_IsHdmi IsHdmi; + /*Color Space Support*/ + XV_VidC_Supp IsYCbCr444Supp; + XV_VidC_Supp IsYCbCr420Supp; + XV_VidC_Supp IsYCbCr422Supp; + /*YCbCr444/YCbCr422/RGB444 Deep Color Support*/ + XV_VidC_Supp IsYCbCr444DeepColSupp; + XV_VidC_Supp Is30bppSupp; + XV_VidC_Supp Is36bppSupp; + XV_VidC_Supp Is48bppSupp; + /*YCbCr420 Deep Color Support*/ + XV_VidC_Supp IsYCbCr420dc30bppSupp; + XV_VidC_Supp IsYCbCr420dc36bppSupp; + XV_VidC_Supp IsYCbCr420dc48bppSupp; + /*SCDC and SCDC ReadRequest Support*/ + XV_VidC_Supp IsSCDCReadRequestReady; + XV_VidC_Supp IsSCDCPresent; + /*Sink Capability Support*/ + u8 MaxFrameRateSupp; + u16 MaxTmdsMhz; + /*CEA 861 Supported VIC Support*/ + u8 SuppCeaVIC[32]; + /*VESA Sink Preffered Timing Support*/ + XV_VidC_TimingParam PreferedTiming[4]; +} XV_VidC_EdidCntrlParam; + + +XV_VidC_TimingParam +XV_VidC_timing + (const struct xvidc_edid_detailed_timing_descriptor * const dtb); +#if XVIDC_EDID_VERBOSITY > 1 +XV_VidC_DoubleRep Double2Int (double in_val); +#endif +void XV_VidC_EdidCtrlParamInit (XV_VidC_EdidCntrlParam *EdidCtrlParam); + +void +XV_VidC_parse_edid(const u8 * const data, + XV_VidC_EdidCntrlParam *EdidCtrlParam, + XV_VidC_Verbose VerboseEn); + +#ifdef __cplusplus +} +#endif +#endif diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/video_common_v4_3/src/xvidc_parse_edid.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/video_common_v4_3/src/xvidc_parse_edid.c new file mode 100644 index 000000000..6b0edb61c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/video_common_v4_3/src/xvidc_parse_edid.c @@ -0,0 +1,1332 @@ +/* vim: set et fde fdm=syntax ft=c.doxygen ts=4 sts=4 sw=4 : */ +/* + * Copyright © 2011 Saleem Abdulrasool . + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR "AS IS" AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO + * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include "string.h" +#include "stdlib.h" +#include "stddef.h" + +#include "xil_types.h" +#include "xstatus.h" +#include "xil_exception.h" + +#include "xvidc_edid_ext.h" + +#if XVIDC_EDID_VERBOSITY > 1 +#include "math.h" + +#define CM_2_MM(cm) ((cm) * 10) +#define CM_2_IN(cm) ((cm) * 0.3937) +#endif +#if XVIDC_EDID_VERBOSITY > 0 +#define HZ_2_MHZ(hz) ((hz) / 1000000) +#endif +#if XVIDC_EDID_VERBOSITY > 1 +static void +xvidc_disp_cea861_audio_data( + const struct xvidc_cea861_audio_data_block * const adb, + XV_VidC_EdidCntrlParam *EdidCtrlParam, + XV_VidC_Verbose VerboseEn); + +static void +xvidc_disp_cea861_speaker_allocation_data( + const struct xvidc_cea861_speaker_allocation_data_block * const sadb, + XV_VidC_EdidCntrlParam *EdidCtrlParam, + XV_VidC_Verbose VerboseEn); + +static void +xvidc_disp_cea861_video_data( + const struct xvidc_cea861_video_data_block * const vdb, + XV_VidC_EdidCntrlParam *EdidCtrlParam, + XV_VidC_Verbose VerboseEn); +#endif + +static void +xvidc_disp_cea861_extended_data( + const struct xvidc_cea861_extended_data_block * const edb, + XV_VidC_EdidCntrlParam *EdidCtrlParam, + XV_VidC_Verbose VerboseEn); + +static void +xvidc_disp_cea861_vendor_data( + const struct xvidc_cea861_vendor_specific_data_block * vsdb, + XV_VidC_EdidCntrlParam *EdidCtrlParam, + XV_VidC_Verbose VerboseEn); + +static void +xvidc_disp_cea861(const struct xvidc_edid_extension * const ext, + XV_VidC_EdidCntrlParam *EdidCtrlParam, + XV_VidC_Verbose VerboseEn); + +static void +xvidc_disp_edid1(const struct edid * const edid, + XV_VidC_EdidCntrlParam *EdidCtrlParam, + XV_VidC_Verbose VerboseEn); + +/*****************************************************************************/ +/** +* +* This function parse EDID on General Data & VESA Data +* +* @param data is a pointer to the EDID array. +* @param EdidCtrlParam is a pointer the EDID Control parameter +* @param VerboseEn is a pointer to the XV_HdmiTxSs core instance. +* +* @return None +* +* @note API Define below here are CEA861 routines +* +******************************************************************************/ +static void +xvidc_disp_edid1(const struct edid * const edid, + XV_VidC_EdidCntrlParam *EdidCtrlParam, + XV_VidC_Verbose VerboseEn) +{ + const struct xvidc_edid_monitor_range_limits *monitor_range_limits = NULL; + xvidc_edid_monitor_descriptor_string monitor_serial_number = {0}; + xvidc_edid_monitor_descriptor_string monitor_model_name = {0}; + bool has_ascii_string = false; + char manufacturer[4] = {0}; +#if XVIDC_EDID_VERBOSITY > 1 + XV_VidC_DoubleRep min_doubleval; + XV_VidC_DoubleRep max_doubleval; +#endif + + u8 i; +#if XVIDC_EDID_VERBOSITY > 0 + //add by mmo + XV_VidC_TimingParam timing_params; +#endif + +#if XVIDC_EDID_VERBOSITY > 1 + struct xvidc_edid_color_characteristics_data characteristics; + const u8 vlen = edid->maximum_vertical_image_size; + const u8 hlen = edid->maximum_horizontal_image_size; + + + static const char * const display_type[] = { + [XVIDC_EDID_DISPLAY_TYPE_MONOCHROME] = "Monochrome or greyscale", + [XVIDC_EDID_DISPLAY_TYPE_RGB] = "sRGB colour", + [XVIDC_EDID_DISPLAY_TYPE_NON_RGB] = "Non-sRGB colour", + [XVIDC_EDID_DISPLAY_TYPE_UNDEFINED] = "Undefined", + }; +#endif + xvidc_edid_manufacturer(edid, manufacturer); + + for (i = 0; i < ARRAY_SIZE(edid->detailed_timings); i++) { + const struct xvidc_edid_monitor_descriptor * const mon = + &edid->detailed_timings[i].monitor; + + if (!xvidc_edid_detailed_timing_is_monitor_descriptor(edid, i)) + continue; + + switch (mon->tag) { + case XVIDC_EDID_MONTIOR_DESCRIPTOR_MANUFACTURER_DEFINED: + /* This is arbitrary data, just silently ignore it. */ + break; + case XVIDC_EDID_MONITOR_DESCRIPTOR_ASCII_STRING: + has_ascii_string = true; + break; + case XVIDC_EDID_MONITOR_DESCRIPTOR_MONITOR_NAME: + strncpy(monitor_model_name, (char *) mon->data, + sizeof(monitor_model_name) - 1); + break; + case XVIDC_EDID_MONITOR_DESCRIPTOR_MONITOR_RANGE_LIMITS: + monitor_range_limits = + (struct xvidc_edid_monitor_range_limits *) &mon->data; + break; + case XVIDC_EDID_MONITOR_DESCRIPTOR_MONITOR_SERIAL_NUMBER: + strncpy(monitor_serial_number, (char *) mon->data, + sizeof(monitor_serial_number) - 1); + break; + default: + if (VerboseEn) { + xil_printf("unknown monitor descriptor type 0x%02x\n", + mon->tag); + } + break; + } + } + +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { + xil_printf("Sink Information\r\n"); + + xil_printf(" Model name............... %s\r\n", + *monitor_model_name ? monitor_model_name : "n/a"); +#if XVIDC_EDID_VERBOSITY > 1 + xil_printf(" Manufacturer............. %s\r\n", + manufacturer); + + xil_printf(" Product code............. %u\r\n", + (u16) edid->product_u16); + + if (*(u32 *) edid->serial_number_u32) + xil_printf(" Module serial number..... %u\r\n", + (u32) edid->serial_number_u32); +#endif +#if defined(DISPLAY_UNKNOWN) + xil_printf(" Plug and Play ID......... %s\r\n", NULL); +#endif +#if XVIDC_EDID_VERBOSITY > 1 + xil_printf(" Serial number............ %s\r\n", + *monitor_serial_number ? monitor_serial_number : "n/a"); + + xil_printf(" Manufacture date......... %u", + edid->manufacture_year + 1990); + if (edid->manufacture_week <= 52) + xil_printf(", ISO week %u", edid->manufacture_week); + xil_printf("\r\n"); +#endif + xil_printf(" EDID revision............ %u.%u\r\n", + edid->version, edid->revision); +#if XVIDC_EDID_VERBOSITY > 1 + xil_printf(" Input signal type........ %s\r\n", + edid->video_input_definition.digital.digital ? "Digital" : "Analog"); + + if (edid->video_input_definition.digital.digital) { + xil_printf(" VESA DFP 1.x supported... %s\r\n", + edid->video_input_definition.digital.dfp_1x ? "Yes" : "No"); + } else { + /* Missing Piece: To print analog flags */ + } +#endif +#if defined(DISPLAY_UNKNOWN) + xil_printf(" Color bit depth.......... %s\r\n", NULL); +#endif +#if XVIDC_EDID_VERBOSITY > 1 + xil_printf(" Display type............. %s\r\n", + display_type[edid->feature_support.display_type]); + + xil_printf(" Screen size.............. %u mm x %u mm (%.1f in)\r\n", + CM_2_MM(hlen), CM_2_MM(vlen), + CM_2_IN(sqrt(hlen * hlen + vlen * vlen))); + + xil_printf(" Power management......... %s%s%s%s\r\n", + edid->feature_support.active_off ? "Active off, " : "", + edid->feature_support.suspend ? "Suspend, " : "", + edid->feature_support.standby ? "Standby, " : "", + + (edid->feature_support.active_off || + edid->feature_support.suspend || + edid->feature_support.standby) ? "\b\b " : "n/a"); +#endif + xil_printf(" Extension blocks......... %u\r\n", + edid->extensions); + +#if defined(DISPLAY_UNKNOWN) + xil_printf(" DDC/CI................... %s\r\n", NULL); +#endif + + xil_printf("\r\n"); + } +#endif + if (has_ascii_string) { + if (VerboseEn) { +#if XVIDC_EDID_VERBOSITY > 1 + xil_printf("General purpose ASCII string\r\n"); +#endif + } + + for (i = 0; i < ARRAY_SIZE(edid->detailed_timings); i++) { + if (!xvidc_edid_detailed_timing_is_monitor_descriptor(edid, i)) + continue; + } + + if (VerboseEn) { +#if XVIDC_EDID_VERBOSITY > 1 + xil_printf("\r\n"); +#endif + } + } +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { + xil_printf("Color characteristics\r\n"); + + xil_printf(" Default color space...... %ssRGB\r\n", + edid->feature_support.standard_default_color_space ? "":"Non-"); +#if XVIDC_EDID_VERBOSITY > 1 + min_doubleval = + Double2Int(xvidc_edid_gamma(edid)); + xil_printf(" Display gamma............ %d.%03d\r\n", + min_doubleval.Integer, min_doubleval.Decimal); + + characteristics = xvidc_edid_color_characteristics(edid); + + min_doubleval = + Double2Int(xvidc_edid_decode_fixed_point(characteristics.red.x)); + max_doubleval = + Double2Int(xvidc_edid_decode_fixed_point(characteristics.red.y)); + + xil_printf(" Red chromaticity......... Rx %d.%03d - Ry %d.%03d\r\n", + min_doubleval.Integer, min_doubleval.Decimal, + max_doubleval.Integer, max_doubleval.Decimal); + + min_doubleval = + Double2Int(xvidc_edid_decode_fixed_point(characteristics.green.x)); + max_doubleval = + Double2Int(xvidc_edid_decode_fixed_point(characteristics.green.y)); + + xil_printf(" Green chromaticity....... Gx %d.%03d - Gy %d.%03d\r\n", + min_doubleval.Integer, min_doubleval.Decimal, + max_doubleval.Integer, max_doubleval.Decimal); + + min_doubleval = + Double2Int(xvidc_edid_decode_fixed_point(characteristics.blue.x)); + max_doubleval = + Double2Int(xvidc_edid_decode_fixed_point(characteristics.blue.y)); + + xil_printf(" Blue chromaticity........ Bx %d.%03d - By %d.%03d\r\n", + min_doubleval.Integer, min_doubleval.Decimal, + max_doubleval.Integer, max_doubleval.Decimal); + + min_doubleval = + Double2Int(xvidc_edid_decode_fixed_point(characteristics.white.x)); + max_doubleval = + Double2Int(xvidc_edid_decode_fixed_point(characteristics.white.y)); + + xil_printf(" White point (default).... Wx %d.%03d - Wy %d.%03d\r\n", + min_doubleval.Integer, min_doubleval.Decimal, + max_doubleval.Integer, max_doubleval.Decimal); +#endif +#if defined(DISPLAY_UNKNOWN) + xil_printf(" Additional descriptors... %s\r\n", NULL); +#endif + xil_printf("\r\n"); + + xil_printf("VESA Timing characteristics\r\n"); + } +#endif + if (monitor_range_limits) { +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { + xil_printf(" Horizontal scan range.... %u - %u kHz\r\n", + monitor_range_limits->minimum_horizontal_rate, + monitor_range_limits->maximum_horizontal_rate); + + xil_printf(" Vertical scan range...... %u - %u Hz\r\n", + monitor_range_limits->minimum_vertical_rate, + monitor_range_limits->maximum_vertical_rate); + + xil_printf(" Video bandwidth.......... %u MHz\r\n", + monitor_range_limits->maximum_supported_pixel_clock * 10); + } +#endif + EdidCtrlParam->MaxFrameRateSupp = + monitor_range_limits->maximum_vertical_rate; + EdidCtrlParam->MaxTmdsMhz = + (monitor_range_limits->maximum_supported_pixel_clock * 10); + } + +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { +#if defined(DISPLAY_UNKNOWN) + xil_printf(" CVT standard............. %s\r\n", NULL); +#endif +#if XVIDC_EDID_VERBOSITY > 1 + xil_printf(" GTF standard............. %sSupported\r\n", + edid->feature_support.default_gtf ? "" : "Not "); +#endif +#if defined(DISPLAY_UNKNOWN) + xil_printf(" Additional descriptors... %s\r\n", NULL); +#endif +#if XVIDC_EDID_VERBOSITY > 0 + xil_printf(" Preferred timing......... %s\r\n", + edid->feature_support.preferred_timing_mode ? "Yes" : "No"); +#endif + for (i = 0; i < ARRAY_SIZE(edid->detailed_timings); i++) { + if (xvidc_edid_detailed_timing_is_monitor_descriptor(edid, i)) + continue; + + timing_params = XV_VidC_timing(&edid->detailed_timings[i].timing); + EdidCtrlParam->PreferedTiming[i] = + XV_VidC_timing(&edid->detailed_timings[i].timing); +#if XVIDC_EDID_VERBOSITY > 0 + if (edid->feature_support.preferred_timing_mode) { + xil_printf(" Native/preferred timing.. %ux%u%c at %uHz" + " (%u:%u)\r\n", + timing_params.hres, + timing_params.vres, + timing_params.vidfrmt ? 'i' : 'p', + timing_params.vfreq, + timing_params.aspect_ratio.width, + timing_params.aspect_ratio.height); + xil_printf(" Modeline............... \"%ux%u\" %u %u %u %u" + " %u %u %u %u %u %chsync %cvsync\r\n", + timing_params.hres, + timing_params.vres, + HZ_2_MHZ (timing_params.pixclk), + (timing_params.hres), + (timing_params.hres + timing_params.hfp), + (timing_params.hres + timing_params.hfp + + timing_params.hsync_width), + (timing_params.htotal), + (timing_params.vres), + (timing_params.vres + timing_params.vfp), + (timing_params.vres + timing_params.vfp + + timing_params.vsync_width), + (timing_params.vtotal), + timing_params.hsync_polarity ? '+' : '-', + timing_params.vsync_polarity ? '+' : '-'); + } else { + xil_printf(" Native/preferred timing.. n/a\r\n"); + } +#endif + } +#if XVIDC_EDID_VERBOSITY > 0 + xil_printf("\r\n"); +#endif +#if XVIDC_EDID_VERBOSITY > 1 + xil_printf("Established Timings supported\r\n"); + if (edid->established_timings.timing_720x400_70) + xil_printf(" 720 x 400p @ 70Hz - IBM VGA\r\n"); + if (edid->established_timings.timing_720x400_88) + xil_printf(" 720 x 400p @ 88Hz - IBM XGA2\r\n"); + if (edid->established_timings.timing_640x480_60) + xil_printf(" 640 x 480p @ 60Hz - IBM VGA\r\n"); + if (edid->established_timings.timing_640x480_67) + xil_printf(" 640 x 480p @ 67Hz - Apple Mac II\r\n"); + if (edid->established_timings.timing_640x480_72) + xil_printf(" 640 x 480p @ 72Hz - VESA\r\n"); + if (edid->established_timings.timing_640x480_75) + xil_printf(" 640 x 480p @ 75Hz - VESA\r\n"); + if (edid->established_timings.timing_800x600_56) + xil_printf(" 800 x 600p @ 56Hz - VESA\r\n"); + if (edid->established_timings.timing_800x600_60) + xil_printf(" 800 x 600p @ 60Hz - VESA\r\n"); + + if (edid->established_timings.timing_800x600_72) + xil_printf(" 800 x 600p @ 72Hz - VESA\r\n"); + if (edid->established_timings.timing_800x600_75) + xil_printf(" 800 x 600p @ 75Hz - VESA\r\n"); + if (edid->established_timings.timing_832x624_75) + xil_printf(" 832 x 624p @ 75Hz - Apple Mac II\r\n"); + if (edid->established_timings.timing_1024x768_87) + xil_printf(" 1024 x 768i @ 87Hz - VESA\r\n"); + if (edid->established_timings.timing_1024x768_60) + xil_printf(" 1024 x 768p @ 60Hz - VESA\r\n"); + if (edid->established_timings.timing_1024x768_70) + xil_printf(" 1024 x 768p @ 70Hz - VESA\r\n"); + if (edid->established_timings.timing_1024x768_75) + xil_printf(" 1024 x 768p @ 75Hz - VESA\r\n"); + if (edid->established_timings.timing_1280x1024_75) + xil_printf(" 1280 x 1024p @ 75Hz - VESA\r\n"); +#endif + } +#endif + +#if XVIDC_EDID_VERBOSITY > 1 + if (VerboseEn) { + xil_printf("Standard Timings supported\r\n"); + for (i = 0; i < ARRAY_SIZE(edid->standard_timing_id); i++) { + const struct xvidc_edid_standard_timing_descriptor * const desc = + &edid->standard_timing_id[i]; + + if (!memcmp(desc, XVIDC_EDID_STANDARD_TIMING_DESCRIPTOR_INVALID, + sizeof(*desc))) + { + continue; + } else { + if (((desc->horizontal_active_pixels + 31)* 8) >= 1000) { + xil_printf(" %u x",(desc->horizontal_active_pixels + 31)* 8); + } else { + xil_printf(" %u x",(desc->horizontal_active_pixels + 31)* 8); + } + switch (desc->image_aspect_ratio) { + case 0: //Aspect Ratio = 16:10 + xil_printf(" %up ", + (((desc->horizontal_active_pixels + 31)* 8) * 10) / 16); + break; + case 1: //Aspect Ratio = 4:3 + xil_printf(" %up ", + (((desc->horizontal_active_pixels + 31)* 8) * 3) / 4); + break; + case 2: //Aspect Ratio = 5:4 + xil_printf(" %up ", + (((desc->horizontal_active_pixels + 31)* 8) * 4) / 5); + break; + case 3: //Aspect Ratio = 16:9 + xil_printf(" %up ", + (((desc->horizontal_active_pixels + 31)* 8) * 9) / 16); + break; + default: //Aspect Ratio = 16:10 + xil_printf(" %up ", + (((desc->horizontal_active_pixels + 31)* 8) * 10) / 16); + break; + } + xil_printf("@ %uHz\r\n",(desc->refresh_rate + 60)); + } + } + } +#endif +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { + xil_printf("\r\n"); + } +#endif +} + + + +/*****************************************************************************/ +/** +* +* This function parse EDID on CEA 861 Audio Data +* +* @param data is a pointer to the EDID array. +* @param EdidCtrlParam is a pointer the EDID Control parameter +* @param VerboseEn is a pointer to the XV_HdmiTxSs core instance. +* +* @return None +* +* @note API Define below here are CEA861 routines +* +******************************************************************************/ +#if XVIDC_EDID_VERBOSITY > 1 +static void +xvidc_disp_cea861_audio_data( + const struct xvidc_cea861_audio_data_block * const adb, + XV_VidC_EdidCntrlParam *EdidCtrlParam, + XV_VidC_Verbose VerboseEn) { + /* For Future Usage */ + EdidCtrlParam = EdidCtrlParam; + + const u8 descriptors = adb->header.length / sizeof(*adb->sad); +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { + xil_printf("CE audio data (formats supported)\r\n"); + } +#endif + for (u8 i = 0; i < descriptors; i++) { + const struct xvidc_cea861_short_audio_descriptor * const sad = + (struct xvidc_cea861_short_audio_descriptor *) &adb->sad[i]; + + switch (sad->audio_format) { + case XVIDC_CEA861_AUDIO_FORMAT_LPCM: +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { + xil_printf(" LPCM %u-channel, %s%s%s\b%s", + sad->channels + 1, + sad->flags.lpcm.bitrate_16_bit ? "16/" : "", + sad->flags.lpcm.bitrate_20_bit ? "20/" : "", + sad->flags.lpcm.bitrate_24_bit ? "24/" : "", + + ((sad->flags.lpcm.bitrate_16_bit + + sad->flags.lpcm.bitrate_20_bit + + sad->flags.lpcm.bitrate_24_bit) > 1) ? + " bit depths" : "-bit"); + } +#endif + break; + case XVIDC_CEA861_AUDIO_FORMAT_AC_3: +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { + xil_printf(" AC-3 %u-channel, %4uk max. bit rate", + sad->channels + 1, + (sad->flags.maximum_bit_rate << 3)); + } +#endif + break; + default: +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { + xil_printf("Unknown audio format 0x%02x\r\n", + sad->audio_format); + } +#endif + continue; + } +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { + xil_printf(" at %s%s%s%s%s%s%s\b kHz\r\n", + sad->sample_rate_32_kHz ? "32/" : "", + sad->sample_rate_44_1_kHz ? "44.1/" : "", + sad->sample_rate_48_kHz ? "48/" : "", + sad->sample_rate_88_2_kHz ? "88.2/" : "", + sad->sample_rate_96_kHz ? "96/" : "", + sad->sample_rate_176_4_kHz ? "176.4/" : "", + sad->sample_rate_192_kHz ? "192/" : ""); + } +#endif + } +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { + xil_printf("\r\n"); + } +#endif +} +#endif + +/*****************************************************************************/ +/** +* +* This function parse EDID on CEA 861 Extended Data +* +* @param data is a pointer to the EDID array. +* @param EdidCtrlParam is a pointer the EDID Control parameter +* @param VerboseEn is a pointer to the XV_HdmiTxSs core instance. +* +* @return None +* +* @note None. +* +******************************************************************************/ +static void +xvidc_disp_cea861_extended_data( + const struct xvidc_cea861_extended_data_block * const edb, + XV_VidC_EdidCntrlParam *EdidCtrlParam, + XV_VidC_Verbose VerboseEn) { + + /* During Verbosity 0, VerboseEn won't be used */ + /* To avoid compilation warnings */ + VerboseEn = VerboseEn; + +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { + xil_printf("CEA Extended Tags\r\n"); + } +#endif + switch(edb->xvidc_cea861_extended_tag_codes) { +#if XVIDC_EDID_VERBOSITY > 1 + case XVIDC_CEA861_EXT_TAG_TYPE_VIDEO_CAPABILITY: + if (VerboseEn) { + xil_printf(" Video capability data block\r\n"); + } + break; + + case XVIDC_CEA861_EXT_TAG_TYPE_VENDOR_SPECIFIC: + if (VerboseEn) { + xil_printf(" Vendor-specific video data block\r\n"); + } + break; + + case XVIDC_CEA861_EXT_TAG_TYPE_VESA_DISPLAY_DEVICE: + if (VerboseEn) { + xil_printf(" VESA video display device data block\r\n"); + } + break; + + case XVIDC_CEA861_EXT_TAG_TYPE_VESA_VIDEO_TIMING_BLOCK_EXT: + if (VerboseEn) { + xil_printf("VESA video timing block extension\r\n"); + } + break; + + case XVIDC_CEA861_EXT_TAG_TYPE_RESERVED_FOR_HDMI_VIDEO_DATA_BLOCK: + if (VerboseEn) { + xil_printf("Reserved for HDMI video data block\r\n"); + } + break; + + case XVIDC_CEA861_EXT_TAG_TYPE_COLORIMETRY: + if (VerboseEn) { + xil_printf(" Colorimetry data block\r\n"); + } + break; + + case XVIDC_CEA861_EXT_TAG_TYPE_HDR_STATIC_METADATA: + if (VerboseEn) { + xil_printf("HDR static metadata data block\r\n"); + } + break; + + case XVIDC_CEA861_EXT_TAG_TYPE_HDR_DYNAMIC_METADATA: + if (VerboseEn) { + xil_printf(" HDR dynamic metadata data block\r\n"); + } + break; + + case XVIDC_CEA861_EXT_TAG_TYPE_VIDEO_FRMT_PREFERENCE: + if (VerboseEn) { + xil_printf(" Video format preference data block\r\n"); + } + break; + + case XVIDC_CEA861_EXT_TAG_TYPE_CEA_MISC_AUDIO_FIELDS: + if (VerboseEn) { + xil_printf("Reserved for CEA miscellaneous audio fields\r\n"); + } + break; + + case XVIDC_CEA861_EXT_TAG_TYPE_VENDOR_SPECIFC_AUDIO: + if (VerboseEn) { + xil_printf(" Vendor-specific audio data block\r\n\r\n"); + } + break; + + case XVIDC_CEA861_EXT_TAG_TYPE_HDMI_AUDIO: + if (VerboseEn) { + xil_printf(" HDMI audio data block\r\n"); + } + break; + + case XVIDC_CEA861_EXT_TAG_TYPE_ROOM_CONFIGURATION: + if (VerboseEn) { + xil_printf(" Room configuration data block\r\n"); + } + break; + + case XVIDC_CEA861_EXT_TAG_TYPE_SPEAKER_LOCATION: + if (VerboseEn) { + xil_printf(" Speaker location data block\r\n"); + } + break; + + case XVIDC_CEA861_EXT_TAG_TYPE_INFOFRAME: + if (VerboseEn) { + xil_printf(" Video capability data block\r\n"); + } + break; +#endif + case XVIDC_CEA861_EXT_TAG_TYPE_YCBCR420_VIDEO: +#if XVIDC_EDID_VERBOSITY > 1 + if (VerboseEn) { + xil_printf(" YCbCr 4:2:0 video data block\r\n"); + xil_printf(" YCbCr 4:2:0.............. Supported\r\n"); + } +#endif + EdidCtrlParam->IsYCbCr420Supp = XVIDC_SUPPORTED; + +#if XVIDC_EDID_VERBOSITY > 1 + if (VerboseEn) { + xil_printf(" CE video identifiers (VICs) - " + " timing/formats supported\r\n"); + } + for (u8 i = 0; i < edb->header.length - 1; i++) { + u8 vic; + u8 native=0; + if ((edb->data[i] & 0x7F) == 0) { + continue; + } else if (((edb->data[i]) >= 1) && ((edb->data[i]) <= 64)){ + vic = (edb->data[i]) & 0x7F; + } else if (((edb->data[i]) >= 65) && ((edb->data[i]) <= 127)){ + vic = (edb->data[i]); + } else if (((edb->data[i]) >= 129) && ((edb->data[i]) <= 192)){ + vic = (edb->data[i]) & 0x7F; + native = 1; + } else if (((edb->data[i]) >= 193) && ((edb->data[i]) <= 253)){ + vic = (edb->data[i]); + } else { + continue; + } + + const struct xvidc_cea861_timing * const timing = + &xvidc_cea861_timings[vic]; + + if (VerboseEn) { + xil_printf(" %s CEA Mode %02u: %4u x %4u%c @ %dHz\r\n", + native ? "*" : " ", + vic, + timing->hactive, timing->vactive, + (timing->mode == INTERLACED) ? 'i' : 'p', + (u32)(timing->vfreq)); + } + } + if (VerboseEn) { + xil_printf("\r\n"); + } +#endif + break; + + case XVIDC_CEA861_EXT_TAG_TYPE_YCBCR420_CAPABILITY_MAP: +#if XVIDC_EDID_VERBOSITY > 1 + if (VerboseEn) { + xil_printf(" YCbCr 4:2:0 capability map data block\r\n"); + xil_printf(" YCbCr 4:2:0.............. Supported\r\n"); + } +#endif + EdidCtrlParam->IsYCbCr420Supp = XVIDC_SUPPORTED; +#if XVIDC_EDID_VERBOSITY > 1 + for (u8 i = 0; i < edb->header.length - 1; i++) { + u8 v = edb->data[i]; + + for (u8 j = 0; j < 8; j++) { + if (v & (1 << j)) { + if (VerboseEn) { + const struct xvidc_cea861_timing * const timing = + &xvidc_cea861_timings[EdidCtrlParam->SuppCeaVIC[(i * 8) + j]]; + xil_printf(" CEA Mode %02u: %4u x %4u%c" + "@ %dHz\r\n", + EdidCtrlParam->SuppCeaVIC[(i * 8) + j], + timing->hactive, timing->vactive, + (timing->mode == INTERLACED) ? 'i' : 'p', + (u32)(timing->vfreq)); + } + } + } + } +#endif +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { + xil_printf("\r\n"); + } +#endif + break; + + default : +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { +#if XVIDC_EDID_VERBOSITY > 1 + xil_printf(" Not Supported: Ext Tag: %03x\r\n", + edb->xvidc_cea861_extended_tag_codes); +#endif + xil_printf("\r\n"); + } +#endif + break; + } +} +#if XVIDC_EDID_VERBOSITY > 1 +static void +xvidc_disp_cea861_video_data( + const struct xvidc_cea861_video_data_block * const vdb, + XV_VidC_EdidCntrlParam *EdidCtrlParam, + XV_VidC_Verbose VerboseEn) { + /* For Future Usage */ + EdidCtrlParam = EdidCtrlParam; + + if (VerboseEn) { + xil_printf("CE video identifiers (VICs) - timing/formats" + " supported\r\n"); + } + + for (u8 i = 0; i < vdb->header.length; i++) { + + const struct xvidc_cea861_timing * const timing = + &xvidc_cea861_timings[vdb->svd[i].video_identification_code]; + + EdidCtrlParam->SuppCeaVIC[i] = vdb->svd[i].video_identification_code; + if (VerboseEn) { + xil_printf(" %s CEA Mode %02u: %4u x %4u%c @ %dHz\r\n", + vdb->svd[i].native ? "*" : " ", + vdb->svd[i].video_identification_code, + timing->hactive, timing->vactive, + (timing->mode == INTERLACED) ? 'i' : 'p', + (u32)(timing->vfreq)); + } + } + if (VerboseEn) { + xil_printf("\r\n"); + } +} +#endif + +/*****************************************************************************/ +/** +* +* This function parse EDID on CEA 861 Vendor Specific Data +* +* @param data is a pointer to the EDID array. +* @param EdidCtrlParam is a pointer the EDID Control parameter +* @param VerboseEn is a pointer to the XV_HdmiTxSs core instance. +* +* @return None +* +* @note None. +* +******************************************************************************/ +static void +xvidc_disp_cea861_vendor_data( + const struct xvidc_cea861_vendor_specific_data_block * vsdb, + XV_VidC_EdidCntrlParam *EdidCtrlParam, + XV_VidC_Verbose VerboseEn) { + + /* During Verbosity 0, VerboseEn won't be used */ + /* To avoid compilation warnings */ + VerboseEn = VerboseEn; + + const u8 oui[] = { vsdb->ieee_registration[2], + vsdb->ieee_registration[1], + vsdb->ieee_registration[0] }; +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { + xil_printf("CEA vendor specific data (VSDB)\r\n"); + xil_printf(" IEEE registration number. 0x"); + for (u8 i = 0; i < ARRAY_SIZE(oui); i++) + xil_printf("%02X", oui[i]); + xil_printf("\r\n"); + } +#endif + if (!memcmp(oui, HDMI_OUI, sizeof(oui))) { + const struct xvidc_cea861_hdmi_vendor_specific_data_block * const hdmi = + (struct xvidc_cea861_hdmi_vendor_specific_data_block *) vsdb; +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { + xil_printf(" CEC physical address..... %u.%u.%u.%u\r\n", + hdmi->port_configuration_a, + hdmi->port_configuration_b, + hdmi->port_configuration_c, + hdmi->port_configuration_d); + } +#endif + + if (hdmi->header.length >= HDMI_VSDB_EXTENSION_FLAGS_OFFSET) { +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { +#if XVIDC_EDID_VERBOSITY > 1 + xil_printf(" Supports AI (ACP, ISRC).. %s\r\n", + hdmi->audio_info_frame ? "Yes" : "No"); +#endif + xil_printf(" Supports 48bpp........... %s\r\n", + hdmi->colour_depth_48_bit ? "Yes" : "No"); + xil_printf(" Supports 36bpp........... %s\r\n", + hdmi->colour_depth_36_bit ? "Yes" : "No"); + xil_printf(" Supports 30bpp........... %s\r\n", + hdmi->colour_depth_30_bit ? "Yes" : "No"); + xil_printf(" Supp. YUV444 Deep Color.. %s\r\n", + hdmi->yuv_444_supported ? "Yes" : "No"); +#if XVIDC_EDID_VERBOSITY > 1 + xil_printf(" Supports dual-link DVI... %s\r\n", + hdmi->dvi_dual_link ? "Yes" : "No"); +#endif + } +#endif + EdidCtrlParam->Is30bppSupp = hdmi->colour_depth_30_bit; + EdidCtrlParam->Is36bppSupp = hdmi->colour_depth_36_bit; + EdidCtrlParam->Is48bppSupp = hdmi->colour_depth_48_bit; + EdidCtrlParam->IsYCbCr444DeepColSupp = hdmi->yuv_444_supported; + } + + if (hdmi->header.length >= HDMI_VSDB_MAX_TMDS_OFFSET) { + if (hdmi->max_tmds_clock) { +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { + xil_printf(" Maximum TMDS clock....... %uMHz\r\n", + hdmi->max_tmds_clock * 5); + } +#endif + EdidCtrlParam->MaxTmdsMhz = (hdmi->max_tmds_clock * 5); + } else { +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { + xil_printf(" Maximum TMDS clock....... n/a\r\n"); + } +#endif + } + } + + if (hdmi->header.length >= HDMI_VSDB_LATENCY_FIELDS_OFFSET) { + if (hdmi->latency_fields) { +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { + xil_printf(" Video latency %s........ %ums\r\n", + hdmi->interlaced_latency_fields ? "(p)" : "...", + (hdmi->video_latency - 1) << 1); + xil_printf(" Audio latency %s........ %ums\r\n", + hdmi->interlaced_latency_fields ? "(p)" : "...", + (hdmi->audio_latency - 1) << 1); + } +#endif + } + + if (hdmi->interlaced_latency_fields) { +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { + xil_printf(" Video latency (i)........ %ums\r\n", + hdmi->interlaced_video_latency); + xil_printf(" Audio latency (i)........ %ums\r\n", + hdmi->interlaced_audio_latency); + } +#endif + } + } + } else if (!memcmp(oui, HDMI_OUI_HF, sizeof(oui))) { + const struct xvidc_cea861_hdmi_hf_vendor_specific_data_block * const hdmi = + (struct xvidc_cea861_hdmi_hf_vendor_specific_data_block *) vsdb; + +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { + xil_printf(" Version.................. %d\r\n",hdmi->version); + } +#endif + + if (hdmi->max_tmds_char_rate) { +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { + xil_printf(" Maximum TMDS clock....... %uMHz\r\n", + hdmi->max_tmds_char_rate * 5); + } +#endif + EdidCtrlParam->MaxTmdsMhz = (hdmi->max_tmds_char_rate * 5); + } else { +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { + xil_printf(" Max. Supp. TMDS clock (<=340MHz)\r\n"); + } +#endif + } + + if (hdmi->header.length >= HDMI_VSDB_EXTENSION_FLAGS_OFFSET) { +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { +#if XVIDC_EDID_VERBOSITY > 1 + xil_printf(" RRC Capable Support...... %s\r\n", + hdmi->rr_capable ? "Yes" : "No"); + xil_printf(" SCDC Present............. %s\r\n", + hdmi->scdc_present ? "Yes" : "No"); + xil_printf(" HDMI1.4 Scramble Support. %s\r\n", + hdmi->lte_340mcsc_scramble ? "Yes" : "No"); +#endif + xil_printf(" YUV 420 Deep.C. Support..\r\n"); + xil_printf(" Supports 48bpp......... %s\r\n", + hdmi->dc_48bit_yuv420 ? "Yes" : "No"); + xil_printf(" Supports 36bpp......... %s\r\n", + hdmi->dc_36bit_yuv420 ? "Yes" : "No"); + xil_printf(" Supports 30bpp......... %s\r\n", + hdmi->dc_30bit_yuv420 ? "Yes" : "No"); + } +#endif + EdidCtrlParam->IsYCbCr420dc30bppSupp = hdmi->dc_30bit_yuv420; + EdidCtrlParam->IsYCbCr420dc36bppSupp = hdmi->dc_36bit_yuv420; + EdidCtrlParam->IsYCbCr420dc48bppSupp = hdmi->dc_48bit_yuv420; + EdidCtrlParam->IsSCDCReadRequestReady = hdmi->rr_capable; + EdidCtrlParam->IsSCDCPresent = hdmi->scdc_present; + } + } +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { + xil_printf("\r\n"); + } +#endif +} + +#if XVIDC_EDID_VERBOSITY > 1 +/*****************************************************************************/ +/** +* +* This function parse EDID on CEA 861 Speaker Allocation +* +* @param data is a pointer to the EDID array. +* @param EdidCtrlParam is a pointer the EDID Control parameter +* @param VerboseEn is a pointer to the XV_HdmiTxSs core instance. +* +* @return None +* +* @note None. +* +******************************************************************************/ +static void +xvidc_disp_cea861_speaker_allocation_data( + const struct xvidc_cea861_speaker_allocation_data_block * const sadb, + XV_VidC_EdidCntrlParam *EdidCtrlParam, + XV_VidC_Verbose VerboseEn) { + /* For Future Usage */ + EdidCtrlParam = EdidCtrlParam; + + const struct xvidc_cea861_speaker_allocation * const sa = &sadb->payload; + const u8 * const channel_configuration = (u8 *) sa; + + if (VerboseEn) { + xil_printf("CEA speaker allocation data\r\n"); + xil_printf(" Channel configuration.... %u.%u\r\n", + (__builtin_popcountll(channel_configuration[0] & 0xe9) << 1) + + (__builtin_popcountll(channel_configuration[0] & 0x14) << 0) + + (__builtin_popcountll(channel_configuration[1] & 0x01) << 1) + + (__builtin_popcountll(channel_configuration[1] & 0x06) << 0), + (channel_configuration[0] & 0x02)); + xil_printf(" Front left/right......... %s\r\n", + sa->front_left_right ? "Yes" : "No"); + xil_printf(" Front LFE................ %s\r\n", + sa->front_lfe ? "Yes" : "No"); + xil_printf(" Front center............. %s\r\n", + sa->front_center ? "Yes" : "No"); + xil_printf(" Rear left/right.......... %s\r\n", + sa->rear_left_right ? "Yes" : "No"); + xil_printf(" Rear center.............. %s\r\n", + sa->rear_center ? "Yes" : "No"); + xil_printf(" Front left/right center.. %s\r\n", + sa->front_left_right_center ? "Yes" : "No"); + xil_printf(" Rear left/right center... %s\r\n", + sa->rear_left_right_center ? "Yes" : "No"); + xil_printf(" Front left/right wide.... %s\r\n", + sa->front_left_right_wide ? "Yes" : "No"); + xil_printf(" Front left/right high.... %s\r\n", + sa->front_left_right_high ? "Yes" : "No"); + xil_printf(" Top center............... %s\r\n", + sa->top_center ? "Yes" : "No"); + xil_printf(" Front center high........ %s\r\n", + sa->front_center_high ? "Yes" : "No"); + + xil_printf("\r\n"); + } + +} +#endif + +/*****************************************************************************/ +/** +* +* This function Parse and Display the CEA-861 +* +* @param data is a pointer to the EDID array. +* @param EdidCtrlParam is a pointer the EDID Control parameter +* @param VerboseEn is a pointer to the XV_HdmiTxSs core instance. +* +* @return None +* +* @note None. +* +******************************************************************************/ +static void +xvidc_disp_cea861(const struct xvidc_edid_extension * const ext, + XV_VidC_EdidCntrlParam *EdidCtrlParam, + XV_VidC_Verbose VerboseEn) { + + const struct xvidc_cea861_timing_block * const ctb = + (struct xvidc_cea861_timing_block *) ext; + const u8 offset = offsetof(struct xvidc_cea861_timing_block, data); + u8 index = 0; + +#if XVIDC_EDID_VERBOSITY > 1 + const struct xvidc_edid_detailed_timing_descriptor *dtd = NULL; + u8 i; + + XV_VidC_TimingParam timing_params; +#endif + +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { + + xil_printf("CEA-861 Information\r\n"); + xil_printf(" Revision number.......... %u\r\n", + ctb->revision); + } +#endif + + if (ctb->revision >= 2) { +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { +#if XVIDC_EDID_VERBOSITY > 1 + xil_printf(" IT underscan............. %supported\r\n", + ctb->underscan_supported ? "S" : "Not s"); +#endif + xil_printf(" Basic audio.............. %supported\r\n", + ctb->basic_audio_supported ? "S" : "Not s"); + xil_printf(" YCbCr 4:4:4.............. %supported\r\n", + ctb->yuv_444_supported ? "S" : "Not s"); + xil_printf(" YCbCr 4:2:2.............. %supported\r\n", + ctb->yuv_422_supported ? "S" : "Not s"); +#if XVIDC_EDID_VERBOSITY > 1 + xil_printf(" Native formats........... %u\r\n", + ctb->native_dtds); +#endif + } +#endif + EdidCtrlParam->IsYCbCr444Supp = ctb->yuv_444_supported; + EdidCtrlParam->IsYCbCr422Supp = ctb->yuv_422_supported; + } + +#if XVIDC_EDID_VERBOSITY > 1 + dtd = (struct xvidc_edid_detailed_timing_descriptor *) + ((u8 *) ctb + ctb->dtd_offset); + for (i = 0; dtd->pixel_clock; i++, dtd++) { + + timing_params = XV_VidC_timing(dtd); + if (VerboseEn) { + xil_printf(" Detailed timing #%u....... %ux%u%c at %uHz " + "(%u:%u)\r\n", + i + 1, + timing_params.hres, + timing_params.vres, + timing_params.vidfrmt ? 'i' : 'p', + timing_params.vfreq, + timing_params.aspect_ratio.width, + timing_params.aspect_ratio.height); + + xil_printf( + " Modeline............... \"%ux%u\" %u %u %u %u %u %u %u %u %u" + " %chsync %cvsync\r\n", + timing_params.hres, + timing_params.vres, + HZ_2_MHZ (timing_params.pixclk), + (timing_params.hres), + (timing_params.hres + timing_params.hfp), + (timing_params.hres + timing_params.hfp + + timing_params.hsync_width), + (timing_params.htotal), + (timing_params.vres), + (timing_params.vres + timing_params.vfp), + (timing_params.vres + timing_params.vfp + + timing_params.vsync_width), + (timing_params.vtotal), + timing_params.hsync_polarity ? '+' : '-', + timing_params.vsync_polarity ? '+' : '-'); + } + } +#endif +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { + xil_printf("\r\n"); + } +#endif + + if (ctb->revision >= 3) { + do { + const struct xvidc_cea861_data_block_header * const header = + (struct xvidc_cea861_data_block_header *) &ctb->data[index]; + + switch (header->tag) { + + case XVIDC_CEA861_DATA_BLOCK_TYPE_AUDIO: + { +#if XVIDC_EDID_VERBOSITY > 1 + const struct xvidc_cea861_audio_data_block * const db = + (struct xvidc_cea861_audio_data_block *) header; + + xvidc_disp_cea861_audio_data(db,EdidCtrlParam,VerboseEn); +#endif + } + break; + + case XVIDC_CEA861_DATA_BLOCK_TYPE_VIDEO: + { +#if XVIDC_EDID_VERBOSITY > 1 + const struct xvidc_cea861_video_data_block * const db = + (struct xvidc_cea861_video_data_block *) header; + + xvidc_disp_cea861_video_data(db,EdidCtrlParam,VerboseEn); +#endif + } + break; + + case XVIDC_CEA861_DATA_BLOCK_TYPE_VENDOR_SPECIFIC: + { + const struct + xvidc_cea861_vendor_specific_data_block * const db = + (struct xvidc_cea861_vendor_specific_data_block *) header; + + xvidc_disp_cea861_vendor_data(db,EdidCtrlParam,VerboseEn); + } + break; + + case XVIDC_CEA861_DATA_BLOCK_TYPE_SPEAKER_ALLOCATION: + { +#if XVIDC_EDID_VERBOSITY > 1 + const struct + xvidc_cea861_speaker_allocation_data_block * const db = + (struct xvidc_cea861_speaker_allocation_data_block *) header; + + xvidc_disp_cea861_speaker_allocation_data(db, + EdidCtrlParam,VerboseEn); +#endif + } + break; + + case XVIDC_CEA861_DATA_BLOCK_TYPE_EXTENDED: + { + const struct xvidc_cea861_extended_data_block * const db = + (struct xvidc_cea861_extended_data_block *) header; + + xvidc_disp_cea861_extended_data(db,EdidCtrlParam,VerboseEn); + } + break; + + default: +#if XVIDC_EDID_VERBOSITY > 1 + if (VerboseEn) { + xil_printf("Unknown CEA-861 data block type 0x%02x\r\n", + header->tag); + } +#endif + break; + } + + index = index + header->length + sizeof(*header); + } while (index < ctb->dtd_offset - offset); + } +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { + xil_printf("\r\n"); + } +#endif +} + + +/*****************************************************************************/ +/** +* +* This structure parse parse EDID routines +* +* +* @note None. +* +******************************************************************************/ +static const struct xvidc_edid_extension_handler { + void (* const inf_disp)(const struct xvidc_edid_extension * const, + XV_VidC_EdidCntrlParam *EdidCtrlParam, XV_VidC_Verbose VerboseEn); +} xvidc_edid_extension_handlers[] = { + [XVIDC_EDID_EXTENSION_CEA] = { xvidc_disp_cea861 }, +}; + + +/*****************************************************************************/ +/** +* +* This function parse and print the EDID of the Sink +* +* @param data is a pointer to the EDID array. +* @param EdidCtrlParam is a pointer the EDID Control parameter +* @param VerboseEn is a pointer to the XV_HdmiTxSs core instance. +* +* @return None +* +* @note None. +* +******************************************************************************/ +void +XV_VidC_parse_edid(const u8 * const data, + XV_VidC_EdidCntrlParam *EdidCtrlParam, + XV_VidC_Verbose VerboseEn) { + const struct edid * const edid = (struct edid *) data; + const struct xvidc_edid_extension * const extensions = + (struct xvidc_edid_extension *) (data + sizeof(*edid)); + + XV_VidC_EdidCtrlParamInit(EdidCtrlParam); + + xvidc_disp_edid1(edid,EdidCtrlParam,VerboseEn); + + for (u8 i = 0; i < edid->extensions; i++) { + const struct xvidc_edid_extension * const extension = &extensions[i]; + const struct xvidc_edid_extension_handler * const handler = + &xvidc_edid_extension_handlers[extension->tag]; + + if (!handler) { +#if XVIDC_EDID_VERBOSITY > 0 + if (VerboseEn) { + xil_printf("WARNING: block %u contains unknown extension " + " (%#04x)\r\n", i, extensions[i].tag); + } +#endif + continue; + } + + if (handler->inf_disp) { + (*handler->inf_disp)(extension,EdidCtrlParam,VerboseEn); + } + } +} diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/video_common_v4_3/src/xvidc_timings_table.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/video_common_v4_3/src/xvidc_timings_table.c new file mode 100644 index 000000000..ee1cb4f28 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/video_common_v4_3/src/xvidc_timings_table.c @@ -0,0 +1,534 @@ +/******************************************************************************* + * + * Copyright (C) 2017 Xilinx, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * Use of the Software is limited solely to applications: + * (a) running on a Xilinx device, or + * (b) that interact with a Xilinx device through a bus or interconnect. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF + * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + * Except as contained in this notice, the name of the Xilinx shall not be used + * in advertising or otherwise to promote the sale, use or other dealings in + * this Software without prior written authorization from Xilinx. + * +*******************************************************************************/ +/******************************************************************************/ +/** + * + * @file xvidc_timings_table.c + * @addtogroup video_common_v4_2 + * @{ + * + * Contains video timings for various standard resolutions. + * + * @note None. + * + * 
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -----------------------------------------------
+ * 1.0   als, 01/10/15 Initial release.
+ *       rc
+ * 2.0   als  08/14/15 Added new video timings.
+ * 2.1   als  11/04/15 Fixed video timings for some resolutions.
+ *       rco  02/09/17 Fix c++ compilation warnings
+ * 4.2   jsr  07/08/17 Added new video timings for SDI supported resolutions
+ *       aad  07/10/17 Add XVIDC_VM_3840x2160_60_P_RB video format
+ *       aad  09/05/17 Fixed timings for 1366x768_60_P
+ *       aad  09/05/17 Added 1366x768_60_P_RB
+ *
+ * +*******************************************************************************/ + +/******************************* Include Files ********************************/ + +#include "xvidc.h" + +/**************************** Variable Definitions ****************************/ + +/** + * This table contains the main stream attributes for various standard + * resolutions. Each entry is of the format: + * 1) ID: XVIDC_VM_x__(_RB = Reduced Blanking) + * 2) Resolution naming: "x@" + * 3) Frame rate: XVIDC_FR_ + * 4) Video timing structure: + * 1) Horizontal active resolution (pixels) + * 2) Horizontal front porch (pixels) + * 3) Horizontal sync width (pixels) + * 4) Horizontal back porch (pixels) + * 5) Horizontal total (pixels) + * 6) Horizontal sync polarity (0=negative|1=positive) + * 7) Vertical active resolution (lines) + * 8) Frame 0: Vertical front porch (lines) + * 9) Frame 0: Vertical sync width (lines) + * 10) Frame 0: Vertical back porch (lines) + * 11) Frame 0: Vertical total (lines) + * 12) Frame 1: Vertical front porch (lines) + * 13) Frame 1: Vertical sync width (lines) + * 14) Frame 1: Vertical back porch (lines) + * 15) Frame 1: Vertical total (lines) + * 16) Vertical sync polarity (0=negative|1=positive) + */ +#ifdef __cplusplus +extern "C" +#endif +const XVidC_VideoTimingMode XVidC_VideoTimingModes[XVIDC_VM_NUM_SUPPORTED] = +{ + /* Interlaced modes. */ + { XVIDC_VM_720x480_60_I, "720x480@60Hz (I)", XVIDC_FR_60HZ, + {720, 19, 62, 57, 858, 0, + 240, 4, 3, 15, 262, 5, 3, 15, 263, 0} }, + { XVIDC_VM_720x576_50_I, "720x576@50Hz (I)", XVIDC_FR_50HZ, + {720, 12, 63, 69, 864, 0, + 288, 2, 3, 19, 312, 3, 3, 19, 313, 0} }, + { XVIDC_VM_1440x480_60_I, "1440x480@60Hz (I)", XVIDC_FR_60HZ, + {1440, 38, 124, 114, 1716, 0, + 240, 4, 3, 15, 262, 5, 3, 15, 263, 0} }, + { XVIDC_VM_1440x576_50_I, "1440x576@50Hz (I)", XVIDC_FR_50HZ, + {1440, 24, 126, 138, 1728, 0, + 288, 2, 3, 19, 312, 3, 3, 19, 313, 0} }, + { XVIDC_VM_1920x1080_48_I, "1920x1080@48Hz (I)", XVIDC_FR_48HZ, + {1920, 371, 88, 371, 2750, 1, + 540, 2, 5, 15, 562, 3, 5, 15, 563, 1} }, + { XVIDC_VM_1920x1080_50_I, "1920x1080@50Hz (I)", XVIDC_FR_50HZ, + {1920, 528, 44, 148, 2640, 1, + 540, 2, 5, 15, 562, 3, 5, 15, 563, 1} }, + { XVIDC_VM_1920x1080_60_I, "1920x1080@60Hz (I)", XVIDC_FR_60HZ, + {1920, 88, 44, 148, 2200, 1, + 540, 2, 5, 15, 562, 3, 5, 15, 563, 1} }, + { XVIDC_VM_1920x1080_96_I, "1920x1080@96Hz (I)", XVIDC_FR_96HZ, + {1920, 371, 88, 371, 2750, 1, + 1080, 4, 10, 30, 1124, 6, 10, 30, 1126, 1} }, + { XVIDC_VM_1920x1080_100_I, "1920x1080@100Hz (I)", XVIDC_FR_100HZ, + {1920, 528, 44, 148, 2640, 1, + 1080, 4, 10, 30, 1124, 6, 10, 30, 1126, 1} }, + { XVIDC_VM_1920x1080_120_I, "1920x1080@120Hz (I)", XVIDC_FR_120HZ, + {1920, 88, 44, 148, 2200, 1, + 1080, 4, 10, 30, 1124, 6, 10, 30, 1126, 1} }, + { XVIDC_VM_2048x1080_48_I, "2048x1080@48Hz (I)", XVIDC_FR_48HZ, + {2048, 329, 44, 329, 2750, 1, + 540, 2, 5, 15, 562, 3, 5, 15, 563, 1} }, + { XVIDC_VM_2048x1080_50_I, "2048x1080@50Hz (I)", XVIDC_FR_50HZ, + {2048, 274, 44, 274, 2640, 1, + 540, 2, 5, 15, 562, 3, 5, 15, 563, 1} }, + { XVIDC_VM_2048x1080_60_I, "2048x1080@60Hz (I)", XVIDC_FR_60HZ, + {2048, 66, 20, 66, 2200, 1, + 540, 2, 5, 15, 562, 3, 5, 15, 563, 1} }, + { XVIDC_VM_2048x1080_96_I, "2048x1080@96Hz (I)", XVIDC_FR_96HZ, + {2048, 329, 44, 329, 2750, 1, + 1080, 4, 10, 30, 1124, 6, 10, 30, 1126, 1} }, + { XVIDC_VM_2048x1080_100_I, "2048x1080@100Hz (I)", XVIDC_FR_100HZ, + {2048, 274, 44, 274, 2640, 1, + 1080, 4, 10, 30, 1124, 6, 10, 30, 1126, 1} }, + { XVIDC_VM_2048x1080_120_I, "2048x1080@120Hz (I)", XVIDC_FR_120HZ, + {2048, 66, 20, 66, 2200, 1, + 1080, 4, 10, 30, 1124, 6, 10, 30, 1126, 1} }, + + + /* Progressive modes. */ + { XVIDC_VM_640x350_85_P, "640x350@85Hz", XVIDC_FR_85HZ, + {640, 32, 64, 96, 832, 1, + 350, 32, 3, 60, 445, 0, 0, 0, 0, 0} }, + { XVIDC_VM_640x480_60_P, "640x480@60Hz", XVIDC_FR_60HZ, + {640, 8+8, 96, 40+8, 800, 0, + 480, 2+8, 2, 25+8, 525, 0, 0, 0, 0, 0} }, + { XVIDC_VM_640x480_72_P, "640x480@72Hz", XVIDC_FR_72HZ, + {640, 8+16, 40, 120+8, 832, 0, + 480, 8+1, 3, 20+8, 520, 0, 0, 0, 0, 0} }, + { XVIDC_VM_640x480_75_P, "640x480@75Hz", XVIDC_FR_75HZ, + {640, 16, 64, 120, 840, 0, + 480, 1, 3, 16, 500, 0, 0, 0, 0, 0} }, + { XVIDC_VM_640x480_85_P, "640x480@85Hz", XVIDC_FR_85HZ, + {640, 56, 56, 80, 832, 0, + 480, 1, 3, 25, 509, 0, 0, 0, 0, 0} }, + { XVIDC_VM_720x400_85_P, "720x400@85Hz", XVIDC_FR_85HZ, + {720, 36, 72, 108, 936, 0, + 400, 1, 3, 42, 446, 0, 0, 0, 0, 1} }, + { XVIDC_VM_720x480_60_P, "720x480@60Hz", XVIDC_FR_60HZ, + {720, 16, 62, 60, 858, 0, + 480, 9, 6, 30, 525, 0, 0, 0, 0, 0} }, + { XVIDC_VM_720x576_50_P, "720x576@50Hz", XVIDC_FR_50HZ, + {720, 12, 64, 68, 864, 0, + 576, 5, 5, 39, 625, 0, 0, 0, 0, 0} }, + { XVIDC_VM_800x600_56_P, "800x600@56Hz", XVIDC_FR_56HZ, + {800, 24, 72, 128, 1024, 1, + 600, 1, 2, 22, 625, 0, 0, 0, 0, 1} }, + { XVIDC_VM_800x600_60_P, "800x600@60Hz", XVIDC_FR_60HZ, + {800, 40, 128, 88, 1056, 1, + 600, 1, 4, 23, 628, 0, 0, 0, 0, 1} }, + { XVIDC_VM_800x600_72_P, "800x600@72Hz", XVIDC_FR_72HZ, + {800, 56, 120, 64, 1040, 1, + 600, 37, 6, 23, 666, 0, 0, 0, 0, 1} }, + { XVIDC_VM_800x600_75_P, "800x600@75Hz", XVIDC_FR_75HZ, + {800, 16, 80, 160, 1056, 1, + 600, 1, 3, 21, 625, 0, 0, 0, 0, 1} }, + { XVIDC_VM_800x600_85_P, "800x600@85Hz", XVIDC_FR_85HZ, + {800, 32, 64, 152, 1048, 1, + 600, 1, 3, 27, 631, 0, 0, 0, 0, 1} }, + { XVIDC_VM_800x600_120_P_RB, "800x600@120Hz (RB)", XVIDC_FR_120HZ, + {800, 48, 32, 80, 960, 1, + 600, 3, 4, 29, 636, 0, 0, 0, 0, 0} }, + { XVIDC_VM_848x480_60_P, "848x480@60Hz", XVIDC_FR_60HZ, + {848, 16, 112, 112, 1088, 1, + 480, 6, 8, 23, 517, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1024x768_60_P, "1024x768@60Hz", XVIDC_FR_60HZ, + {1024, 24, 136, 160, 1344, 0, + 768, 3, 6, 29, 806, 0, 0, 0, 0, 0} }, + { XVIDC_VM_1024x768_70_P, "1024x768@70Hz", XVIDC_FR_70HZ, + {1024, 24, 136, 144, 1328, 0, + 768, 3, 6, 29, 806, 0, 0, 0, 0, 0} }, + { XVIDC_VM_1024x768_75_P, "1024x768@75Hz", XVIDC_FR_75HZ, + {1024, 16, 96, 176, 1312, 1, + 768, 1, 3, 28, 800, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1024x768_85_P, "1024x768@85Hz", XVIDC_FR_85HZ, + {1024, 48, 96, 208, 1376, 1, + 768, 1, 3, 36, 808, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1024x768_120_P_RB, "1024x768@120Hz (RB)", XVIDC_FR_120HZ, + {1024, 48, 32, 80, 1184, 1, + 768, 3, 4, 38, 813, 0, 0, 0, 0, 0} }, + { XVIDC_VM_1152x864_75_P, "1152x864@75Hz", XVIDC_FR_75HZ, + {1152, 64, 128, 256, 1600, 1, + 864, 1, 3, 32, 900, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1280x720_24_P, "1280x720@24Hz", XVIDC_FR_24HZ, + {1280, 970, 905, 970, 4125, 1, + 720, 5, 5, 20, 750, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1280x720_25_P, "1280x720@25Hz", XVIDC_FR_25HZ, + {1280, 970, 740, 970, 3960, 1, + 720, 5, 5, 20, 750, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1280x720_30_P, "1280x720@30Hz", XVIDC_FR_30HZ, + {1280, 970, 80, 970, 3300, 1, + 720, 5, 5, 20, 750, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1280x720_50_P, "1280x720@50Hz", XVIDC_FR_50HZ, + {1280, 440, 40, 220, 1980, 1, + 720, 5, 5, 20, 750, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1280x720_60_P, "1280x720@60Hz", XVIDC_FR_60HZ, + {1280, 110, 40, 220, 1650, 1, + 720, 5, 5, 20, 750, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1280x768_60_P, "1280x768@60Hz", XVIDC_FR_60HZ, + {1280, 64, 128, 192, 1664, 0, + 768, 3, 7, 20, 798, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1280x768_60_P_RB, "1280x768@60Hz (RB)", XVIDC_FR_60HZ, + {1280, 48, 32, 80, 1440, 1, + 768, 3, 7, 12, 790, 0, 0, 0, 0, 0} }, + { XVIDC_VM_1280x768_75_P, "1280x768@75Hz", XVIDC_FR_75HZ, + {1280, 80, 128, 208, 1696, 0, + 768, 3, 7, 27, 805, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1280x768_85_P, "1280x768@85Hz", XVIDC_FR_85HZ, + {1280, 80, 136, 216, 1712, 0, + 768, 3, 7, 31, 809, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1280x768_120_P_RB, "1280x768@120Hz (RB)", XVIDC_FR_120HZ, + {1280, 48, 32, 80, 1440, 1, + 768, 3, 7, 35, 813, 0, 0, 0, 0, 0} }, + { XVIDC_VM_1280x800_60_P, "1280x800@60Hz", XVIDC_FR_60HZ, + {1280, 72, 128, 200, 1680, 0, + 800, 3, 6, 22, 831, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1280x800_60_P_RB, "1280x800@60Hz (RB)", XVIDC_FR_60HZ, + {1280, 48, 32, 80, 1440, 1, + 800, 3, 6, 14, 823, 0, 0, 0, 0, 0} }, + { XVIDC_VM_1280x800_75_P, "1280x800@75Hz", XVIDC_FR_75HZ, + {1280, 80, 128, 208, 1696, 0, + 800, 3, 6, 29, 838, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1280x800_85_P, "1280x800@85Hz", XVIDC_FR_85HZ, + {1280, 80, 136, 216, 1712, 0, + 800, 3, 6, 34, 843, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1280x800_120_P_RB, "1280x800@120Hz (RB)", XVIDC_FR_120HZ, + {1280, 48, 32, 80, 1440, 1, + 800, 3, 6, 38, 847, 0, 0, 0, 0, 0} }, + { XVIDC_VM_1280x960_60_P, "1280x960@60Hz", XVIDC_FR_60HZ, + {1280, 96, 112, 312, 1800, 1, + 960, 1, 3, 36, 1000, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1280x960_85_P, "1280x960@85Hz", XVIDC_FR_85HZ, + {1280, 64, 160, 224, 1728, 1, + 960, 1, 3, 47, 1011, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1280x960_120_P_RB, "1280x960@120Hz (RB)", XVIDC_FR_120HZ, + {1280, 48, 32, 80, 1440, 1, + 960, 3, 4, 50, 1017, 0, 0, 0, 0, 0} }, + { XVIDC_VM_1280x1024_60_P, "1280x1024@60Hz", XVIDC_FR_60HZ, + {1280, 48, 112, 248, 1688, 1, + 1024, 1, 3, 38, 1066, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1280x1024_75_P, "1280x1024@75Hz", XVIDC_FR_75HZ, + {1280, 16, 144, 248, 1688, 1, + 1024, 1, 3, 38, 1066, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1280x1024_85_P, "1280x1024@85Hz", XVIDC_FR_85HZ, + {1280, 64, 160, 224, 1728, 1, + 1024, 1, 3, 44, 1072, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1280x1024_120_P_RB, "1280x1024@120Hz (RB)", XVIDC_FR_120HZ, + {1280, 48, 32, 80, 1440, 1, + 1024, 3, 7, 50, 1084, 0, 0, 0, 0, 0} }, + { XVIDC_VM_1360x768_60_P, "1360x768@60Hz", XVIDC_FR_60HZ, + {1360, 64, 112, 256, 1792, 1, + 768, 3, 6, 18, 795, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1360x768_120_P_RB, "1360x768@120Hz (RB)", XVIDC_FR_120HZ, + {1360, 48, 32, 80, 1520, 1, + 768, 3, 5, 37, 813, 0, 0, 0, 0, 0} }, + { XVIDC_VM_1366x768_60_P, "1366x768@60Hz", XVIDC_FR_60HZ, + {1366, 70, 143, 213, 1792, 1, + 768, 3, 3, 24, 798, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1366x768_60_P_RB, "1366x768@60Hz (RB)", XVIDC_FR_60HZ, + {1366, 14, 56, 64, 1500, 1, + 768, 1, 3, 28, 800, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1400x1050_60_P, "1400x1050@60Hz", XVIDC_FR_60HZ, + {1400, 88, 144, 232, 1864, 0, + 1050, 3, 4, 32, 1089, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1400x1050_60_P_RB, "1400x1050@60Hz (RB)", XVIDC_FR_60HZ, + {1400, 48, 32, 80, 1560, 1, + 1050, 3, 4, 23, 1080, 0, 0, 0, 0, 0} }, + { XVIDC_VM_1400x1050_75_P, "1400x1050@75Hz", XVIDC_FR_75HZ, + {1400, 104, 144, 248, 1896, 0, + 1050, 3, 4, 42, 1099, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1400x1050_85_P, "1400x1050@85Hz", XVIDC_FR_85HZ, + {1400, 104, 152, 256, 1912, 0, + 1050, 3, 4, 48, 1105, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1400x1050_120_P_RB, "1400x1050@120Hz (RB)", XVIDC_FR_120HZ, + {1400, 48, 32, 80, 1560, 1, + 1050, 3, 4, 55, 1112, 0, 0, 0, 0, 0} }, + { XVIDC_VM_1440x240_60_P, "1440x240@60Hz", XVIDC_FR_60HZ, + {1440, 38, 124, 114, 1716, 0, + 240, 14, 3, 4, 262, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1440x900_60_P, "1440x900@60Hz", XVIDC_FR_60HZ, + {1440, 80, 152, 232, 1904, 0, + 900, 3, 6, 25, 934, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1440x900_60_P_RB, "1440x900@60Hz (RB)", XVIDC_FR_60HZ, + {1440, 48, 32, 80, 1600, 1, + 900, 3, 6, 17, 926, 0, 0, 0, 0, 0} }, + { XVIDC_VM_1440x900_75_P, "1440x900@75Hz", XVIDC_FR_75HZ, + {1440, 96, 152, 248, 1936, 0, + 900, 3, 6, 33, 942, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1440x900_85_P, "1440x900@85Hz", XVIDC_FR_85HZ, + {1440, 104, 152, 256, 1952, 0, + 900, 3, 6, 39, 948, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1440x900_120_P_RB, "1440x900@120Hz (RB)", XVIDC_FR_120HZ, + {1440, 48, 32, 80, 1600, 1, + 900, 3, 6, 44, 953, 0, 0, 0, 0, 0} }, + { XVIDC_VM_1600x1200_60_P, "1600x1200@60Hz", XVIDC_FR_60HZ, + {1600, 64, 192, 304, 2160, 1, + 1200, 1, 3, 46, 1250, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1600x1200_65_P, "1600x1200@65Hz", XVIDC_FR_65HZ, + {1600, 64, 192, 304, 2160, 1, + 1200, 1, 3, 46, 1250, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1600x1200_70_P, "1600x1200@70Hz", XVIDC_FR_70HZ, + {1600, 64, 192, 304, 2160, 1, + 1200, 1, 3, 46, 1250, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1600x1200_75_P, "1600x1200@75Hz", XVIDC_FR_75HZ, + {1600, 64, 192, 304, 2160, 1, + 1200, 1, 3, 46, 1250, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1600x1200_85_P, "1600x1200@85Hz", XVIDC_FR_85HZ, + {1600, 64, 192, 304, 2160, 1, + 1200, 1, 3, 46, 1250, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1600x1200_120_P_RB, "1600x1200@120Hz (RB)", XVIDC_FR_120HZ, + {1600, 48, 32, 80, 1760, 1, + 1200, 3, 4, 64, 1271, 0, 0, 0, 0, 0} }, + { XVIDC_VM_1680x720_50_P, "1680x720@50Hz", XVIDC_FR_50HZ, + {1680, 260, 40, 220, 2200, 1, + 720, 5, 5, 20, 750, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1680x720_60_P, "1680x720@60Hz", XVIDC_FR_60HZ, + {1680, 260, 40, 220, 2200, 1, + 720, 5, 5, 20, 750, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1680x720_100_P, "1680x720@100Hz", XVIDC_FR_100HZ, + {1680, 60, 40, 220, 2000, 1, + 720, 5, 5, 95, 825, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1680x720_120_P, "1680x720@120Hz", XVIDC_FR_120HZ, + {1680, 60, 40, 220, 2000, 1, + 720, 5, 5, 95, 825, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1680x1050_50_P, "1680x1050@50Hz", XVIDC_FR_50HZ, + {1680, 88, 176, 264, 2208, 0, + 1050, 3, 6, 24, 1083, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1680x1050_60_P, "1680x1050@60Hz", XVIDC_FR_60HZ, + {1680, 104, 176, 280, 2240, 0, + 1050, 3, 6, 30, 1089, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1680x1050_60_P_RB, "1680x1050@60Hz (RB)", XVIDC_FR_60HZ, + {1680, 48, 32, 80, 1840, 1, + 1050, 3, 6, 21, 1080, 0, 0, 0, 0, 0} }, + { XVIDC_VM_1680x1050_75_P, "1680x1050@75Hz", XVIDC_FR_75HZ, + {1680, 120, 176, 296, 2272, 0, + 1050, 3, 6, 40, 1099, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1680x1050_85_P, "1680x1050@85Hz", XVIDC_FR_85HZ, + {1680, 128, 176, 304, 2288, 0, + 1050, 3, 6, 46, 1105, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1680x1050_120_P_RB, "1680x1050@120Hz (RB)", XVIDC_FR_120HZ, + {1680, 48, 32, 80, 1840, 1, + 1050, 3, 6, 53, 1112, 0, 0, 0, 0, 0} }, + { XVIDC_VM_1792x1344_60_P, "1792x1344@60Hz", XVIDC_FR_60HZ, + {1792, 128, 200, 328, 2448, 0, + 1344, 1, 3, 46, 1394, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1792x1344_75_P, "1792x1344@75Hz", XVIDC_FR_75HZ, + {1792, 96, 216, 352, 2456, 0, + 1344, 1, 3, 69, 1417, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1792x1344_120_P_RB, "1792x1344@120Hz (RB)", XVIDC_FR_120HZ, + {1792, 48, 32, 80, 1952, 1, + 1344, 3, 4, 72, 1423, 0, 0, 0, 0, 0} }, + { XVIDC_VM_1856x1392_60_P, "1856x1392@60Hz", XVIDC_FR_60HZ, + {1856, 96, 224, 352, 2528, 0, + 1392, 1, 3, 43, 1439, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1856x1392_75_P, "1856x1392@75Hz", XVIDC_FR_75HZ, + {1856, 128, 224, 352, 2560, 0, + 1392, 1, 3, 104, 1500, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1856x1392_120_P_RB, "1856x1392@120Hz (RB)", XVIDC_FR_120HZ, + {1856, 48, 32, 80, 2016, 1, + 1392, 3, 4, 75, 1474, 0, 0, 0, 0, 0} }, + { XVIDC_VM_1920x1080_24_P, "1920x1080@24Hz", XVIDC_FR_24HZ, + {1920, 638, 44, 148, 2750, 1, + 1080, 4, 5, 36, 1125, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1920x1080_25_P, "1920x1080@25Hz", XVIDC_FR_25HZ, + {1920, 528, 44, 148, 2640, 1, + 1080, 4, 5, 36, 1125, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1920x1080_30_P, "1920x1080@30Hz", XVIDC_FR_30HZ, + {1920, 88, 44, 148, 2200, 1, + 1080, 4, 5, 36, 1125, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1920x1080_48_P, "1920x1080@48Hz", XVIDC_FR_48HZ, + {1920, 638, 44, 148, 2750, 1, + 1080, 4, 5, 36, 1125, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1920x1080_50_P, "1920x1080@50Hz", XVIDC_FR_50HZ, + {1920, 528, 44, 148, 2640, 1, + 1080, 4, 5, 36, 1125, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1920x1080_60_P, "1920x1080@60Hz", XVIDC_FR_60HZ, + {1920, 88, 44, 148, 2200, 1, + 1080, 4, 5, 36, 1125, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1920x1080_100_P, "1920x1080@100Hz", XVIDC_FR_100HZ, + {1920, 528, 44, 148, 2640, 1, + 1080, 4, 5, 36, 1125, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1920x1080_120_P, "1920x1080@120Hz", XVIDC_FR_120HZ, + {1920, 88, 44, 148, 2200, 1, + 1080, 4, 5, 36, 1125, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1920x1200_60_P, "1920x1200@60Hz", XVIDC_FR_60HZ, + {1920, 136, 200, 336, 2592, 0, + 1200, 3, 6, 36, 1245, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1920x1200_60_P_RB, "1920x1200@60Hz (RB)", XVIDC_FR_60HZ, + {1920, 48, 32, 80, 2080, 1, + 1200, 3, 6, 26, 1235, 0, 0, 0, 0, 0} }, + { XVIDC_VM_1920x1200_75_P, "1920x1200@75Hz", XVIDC_FR_75HZ, + {1920, 136, 208, 344, 2608, 0, + 1200, 3, 6, 46, 1255, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1920x1200_85_P, "1920x1200@85Hz", XVIDC_FR_85HZ, + {1920, 144, 208, 352, 2624, 0, + 1200, 3, 6, 53, 1262, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1920x1200_120_P_RB, "1920x1200@120Hz (RB)", XVIDC_FR_120HZ, + {1920, 48, 32, 80, 2080, 1, + 1200, 3, 6, 62, 1271, 0, 0, 0, 0, 0} }, + { XVIDC_VM_1920x1440_60_P, "1920x1440@60Hz", XVIDC_FR_60HZ, + {1920, 128, 208, 344, 2600, 0, + 1440, 1, 3, 56, 1500, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1920x1440_75_P, "1920x1440@75Hz", XVIDC_FR_75HZ, + {1920, 144, 224, 352, 2640, 0, + 1440, 1, 3, 56, 1500, 0, 0, 0, 0, 1} }, + { XVIDC_VM_1920x1440_120_P_RB, "1920x1440@120Hz (RB)", XVIDC_FR_120HZ, + {1920, 48, 32, 80, 2080, 1, + 1440, 3, 4, 78, 1525, 0, 0, 0, 0, 0} }, + { XVIDC_VM_1920x2160_60_P, "1920x2160@60Hz", XVIDC_FR_60HZ, + {1920, 88, 44, 148, 2200, 1, + 2160, 20, 10, 60, 2250, 0, 0, 0, 0, 0} }, + { XVIDC_VM_2048x1080_24_P, "2048x1080@24Hz", XVIDC_FR_24HZ, + {2048, 510, 44, 148, 2750, 1, + 1080, 4, 5, 36, 1125, 0, 0, 0, 0, 1} }, + { XVIDC_VM_2048x1080_25_P, "2048x1080@25Hz", XVIDC_FR_25HZ, + {2048, 400, 44, 148, 2640, 1, + 1080, 4, 5, 36, 1125, 0, 0, 0, 0, 1} }, + { XVIDC_VM_2048x1080_30_P, "2048x1080@30Hz", XVIDC_FR_30HZ, + {2048, 66, 20, 66, 2200, 1, + 1080, 4, 5, 36, 1125, 0, 0, 0, 0, 1} }, + { XVIDC_VM_2048x1080_48_P, "2048x1080@48Hz", XVIDC_FR_48HZ, + {2048, 510, 44, 148, 2750, 1, + 1080, 4, 5, 36, 1125, 0, 0, 0, 0, 1} }, + { XVIDC_VM_2048x1080_50_P, "2048x1080@50Hz", XVIDC_FR_50HZ, + {2048, 400, 44, 148, 2640, 1, + 1080, 4, 5, 36, 1125, 0, 0, 0, 0, 1} }, + { XVIDC_VM_2048x1080_60_P, "2048x1080@60Hz", XVIDC_FR_60HZ, + {2048, 88, 44, 20, 2200, 1, + 1080, 4, 5, 36, 1125, 0, 0, 0, 0, 1} }, + { XVIDC_VM_2048x1080_100_P, "2048x1080@100Hz", XVIDC_FR_100HZ, + {2048, 528, 44, 148, 2640, 1, + 1080, 4, 5, 36, 1125, 0, 0, 0, 0, 1} }, + { XVIDC_VM_2048x1080_120_P, "2048x1080@120Hz", XVIDC_FR_120HZ, + {2048, 88, 44, 148, 2200, 1, + 1080, 4, 5, 36, 1125, 0, 0, 0, 0, 1} }, + { XVIDC_VM_2560x1080_50_P, "2560x1080@50Hz", XVIDC_FR_50HZ, + {2560, 548, 44, 148, 3300, 1, + 1080, 4, 5, 36, 1125, 0, 0, 0, 0, 1} }, + { XVIDC_VM_2560x1080_60_P, "2560x1080@60Hz", XVIDC_FR_60HZ, + {2560, 248, 44, 148, 3000, 1, + 1080, 4, 5, 11, 1100, 0, 0, 0, 0, 1} }, + { XVIDC_VM_2560x1080_100_P, "2560x1080@100Hz", XVIDC_FR_100HZ, + {2560, 218, 44, 148, 2970, 1, + 1080, 4, 5, 161, 1250, 0, 0, 0, 0, 1} }, + { XVIDC_VM_2560x1080_120_P, "2560x1080@120Hz", XVIDC_FR_120HZ, + {2560, 548, 44, 148, 3300, 1, + 1080, 4, 5, 161, 1250, 0, 0, 0, 0, 1} }, + { XVIDC_VM_2560x1600_60_P, "2560x1600@60Hz", XVIDC_FR_60HZ, + {2560, 192, 280, 472, 3504, 0, + 1600, 3, 6, 49, 1658, 0, 0, 0, 0, 1} }, + { XVIDC_VM_2560x1600_60_P_RB, "2560x1600@60Hz (RB)", XVIDC_FR_60HZ, + {2560, 48, 32, 80, 2720, 1, + 1600, 3, 6, 37, 1646, 0, 0, 0, 0, 0} }, + { XVIDC_VM_2560x1600_75_P, "2560x1600@75Hz", XVIDC_FR_75HZ, + {2560, 208, 280, 488, 3536, 0, + 1600, 3, 6, 63, 1672, 0, 0, 0, 0, 1} }, + { XVIDC_VM_2560x1600_85_P, "2560x1600@85Hz", XVIDC_FR_85HZ, + {2560, 208, 280, 488, 3536, 0, + 1600, 3, 6, 73, 1682, 0, 0, 0, 0, 1} }, + { XVIDC_VM_2560x1600_120_P_RB, "2560x1600@120Hz (RB)", XVIDC_FR_120HZ, + {2560, 48, 32, 80, 2720, 1, + 1600, 3, 6, 85, 1694, 0, 0, 0, 0, 0} }, + { XVIDC_VM_3840x2160_24_P, "3840x2160@24Hz", XVIDC_FR_24HZ, + {3840, 1276, 88, 296, 5500, 1, + 2160, 8, 10, 72, 2250, 0, 0, 0, 0, 1} }, + { XVIDC_VM_3840x2160_25_P, "3840x2160@25Hz", XVIDC_FR_25HZ, + {3840, 1056, 88, 296, 5280, 1, + 2160, 8, 10, 72, 2250, 0, 0, 0, 0, 1} }, + { XVIDC_VM_3840x2160_30_P, "3840x2160@30Hz", XVIDC_FR_30HZ, + {3840, 176, 88, 296, 4400, 1, + 2160, 8, 10, 72, 2250, 0, 0, 0, 0, 1} }, + { XVIDC_VM_3840x2160_48_P, "3840x2160@48Hz", XVIDC_FR_48HZ, + {3840, 1276, 88, 296, 5500, 1, + 2160, 8, 10, 72, 2250, 0, 0, 0, 0, 1} }, + { XVIDC_VM_3840x2160_50_P, "3840x2160@50Hz", XVIDC_FR_50HZ, + {3840, 1056, 88, 296, 5280, 1, + 2160, 8, 10, 72, 2250, 0, 0, 0, 0, 1} }, + { XVIDC_VM_3840x2160_60_P, "3840x2160@60Hz", XVIDC_FR_60HZ, + {3840, 176, 88, 296, 4400, 1, + 2160, 8, 10, 72, 2250, 0, 0, 0, 0, 1} }, + { XVIDC_VM_3840x2160_60_P_RB, "3840x2160@60Hz (RB)", XVIDC_FR_60HZ, + {3840, 48, 32, 80, 4000, 1, + 2160, 3, 5, 54, 2222, 0, 0, 0, 0, 0} }, + { XVIDC_VM_4096x2160_24_P, "4096x2160@24Hz", XVIDC_FR_24HZ, + {4096, 1020, 88, 296, 5500, 1, + 2160, 8, 10, 72, 2250, 0, 0, 0, 0, 1} }, + { XVIDC_VM_4096x2160_25_P, "4096x2160@25Hz", XVIDC_FR_25HZ, + {4096, 968, 88, 128, 5280, 1, + 2160, 8, 10, 72, 2250, 0, 0, 0, 0, 1} }, + { XVIDC_VM_4096x2160_30_P, "4096x2160@30Hz", XVIDC_FR_30HZ, + {4096, 88, 88, 128, 4400, 1, + 2160, 8, 10, 72, 2250, 0, 0, 0, 0, 1} }, + { XVIDC_VM_4096x2160_48_P, "4096x2160@48Hz", XVIDC_FR_48HZ, + {4096, 1020, 88, 296, 5500, 1, + 2160, 8, 10, 72, 2250, 0, 0, 0, 0, 1} }, + { XVIDC_VM_4096x2160_50_P, "4096x2160@50Hz", XVIDC_FR_50HZ, + {4096, 968, 88, 128, 5280, 1, + 2160, 8, 10, 72, 2250, 0, 0, 0, 0, 1} }, + { XVIDC_VM_4096x2160_60_P, "4096x2160@60Hz", XVIDC_FR_60HZ, + {4096, 88, 88, 128, 4400, 1, + 2160, 8, 10, 72, 2250, 0, 0, 0, 0, 1} }, + { XVIDC_VM_4096x2160_60_P_RB, "4096x2160@60Hz (RB)", XVIDC_FR_60HZ, + {4096, 8, 32, 40, 4176, 1, + 2160, 48, 8, 6, 2222, 0, 0, 0, 0, 0} }, +}; + +/** @} */ diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/wdtps_v3_0/src/xwdtps.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/wdtps_v3_0/src/xwdtps.h index 893d516e7..58e559635 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/wdtps_v3_0/src/xwdtps.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/wdtps_v3_0/src/xwdtps.h @@ -88,6 +88,8 @@ * for CR 658287 * 3.0 pkp 12/09/14 Added support for Zynq Ultrascale Mp.Also * modified code for MISRA-C:2012 compliance. +* ms 03/17/17 Added readme.txt file in examples folder for doxygen +* generation. * * ******************************************************************************/ diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/wdtps_v3_0/src/xwdtps_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/wdtps_v3_0/src/xwdtps_g.c index 6ea6b192b..94d8c4733 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/wdtps_v3_0/src/xwdtps_g.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/wdtps_v3_0/src/xwdtps_g.c @@ -5,7 +5,7 @@ * Version: * DO NOT EDIT. * -* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.* +* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.* *Permission is hereby granted, free of charge, to any person obtaining a copy *of this software and associated documentation files (the Software), to deal *in the Software without restriction, including without limitation the rights @@ -44,8 +44,12 @@ * The configuration table for devices */ -XWdtPs_Config XWdtPs_ConfigTable[] = +XWdtPs_Config XWdtPs_ConfigTable[XPAR_XWDTPS_NUM_INSTANCES] = { + { + XPAR_PSU_CSU_WDT_DEVICE_ID, + XPAR_PSU_CSU_WDT_BASEADDR + }, { XPAR_PSU_WDT_0_DEVICE_ID, XPAR_PSU_WDT_0_BASEADDR diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_5/src/Makefile similarity index 100% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/Makefile rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_5/src/Makefile diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/zdma_v1_1/src/xzdma.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_5/src/xzdma.c similarity index 98% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/zdma_v1_1/src/xzdma.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_5/src/xzdma.c index c203f585d..8cad941f8 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/zdma_v1_1/src/xzdma.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_5/src/xzdma.c @@ -33,7 +33,7 @@ /** * * @file xzdma.c -* @addtogroup zdma_v1_0 +* @addtogroup zdma_v1_5 * @{ * * This file contains the implementation of the interface functions for ZDMA @@ -52,6 +52,7 @@ * scatter gather mode data transfer and corrected * XZDma_SetChDataConfig API to set over fetch and * src issue parameters correctly. +* 1.3 mus 08/14/17 Add CCI support for A53 in EL1 NS * * ******************************************************************************/ @@ -117,6 +118,7 @@ s32 XZDma_CfgInitialize(XZDma *InstancePtr, XZDma_Config *CfgPtr, InstancePtr->Config.BaseAddress = CfgPtr->BaseAddress; InstancePtr->Config.DeviceId = CfgPtr->DeviceId; InstancePtr->Config.DmaType = CfgPtr->DmaType; + InstancePtr->Config.IsCacheCoherent = CfgPtr->IsCacheCoherent; InstancePtr->Config.BaseAddress = EffectiveAddr; @@ -279,8 +281,9 @@ u32 XZDma_CreateBDList(XZDma *InstancePtr, XZDma_DscrType TypeOfDscr, (NoOfBytes >> 1) / Size; InstancePtr->Descriptor.SrcDscrPtr = (void *)Dscr_MemPtr; InstancePtr->Descriptor.DstDscrPtr = - (void *)Dscr_MemPtr + (Size * InstancePtr->Descriptor.DscrCount); + (void *)(Dscr_MemPtr + (Size * InstancePtr->Descriptor.DscrCount)); + if (!InstancePtr->Config.IsCacheCoherent) Xil_DCacheInvalidateRange((INTPTR)Dscr_MemPtr, NoOfBytes); return (InstancePtr->Descriptor.DscrCount); @@ -701,6 +704,17 @@ void XZDma_Reset(XZDma *InstancePtr) (void)XZDma_GetSrcIntrCnt(InstancePtr); (void)XZDma_GetDstIntrCnt(InstancePtr); + if (InstancePtr->Config.IsCacheCoherent) { + XZDma_WriteReg((InstancePtr->Config.BaseAddress), + XZDMA_CH_DSCR_ATTR_OFFSET, + InstancePtr->Config.IsCacheCoherent << XZDMA_DSCR_ATTR_AXCOHRNT_SHIFT); + XZDma_WriteReg((InstancePtr->Config.BaseAddress), + XZDMA_CH_SRC_DSCR_WORD3_OFFSET, + InstancePtr->Config.IsCacheCoherent & XZDMA_WORD3_COHRNT_MASK); + XZDma_WriteReg((InstancePtr->Config.BaseAddress), + XZDMA_CH_DST_DSCR_WORD3_OFFSET, + InstancePtr->Config.IsCacheCoherent & XZDMA_WORD3_COHRNT_MASK); + } InstancePtr->ChannelState = XZDMA_IDLE; } diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/xzdma.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_5/src/xzdma.h similarity index 93% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/xzdma.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_5/src/xzdma.h index 1f268d43c..9ff690795 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/xzdma.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_5/src/xzdma.h @@ -1,6 +1,6 @@ /****************************************************************************** * -* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* Copyright (C) 2014-2017 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -33,12 +33,12 @@ /** * * @file xzdma.h -* @addtogroup zdma_v1_0 +* @addtogroup zdma_v1_5 * @{ * @details * * ZDMA is a general purpose DMA designed to support memory to memory and memory -* to IO buffer transfers. ALTO has two instance of general purpose ZDMA. +* to IO buffer transfers. ZynqMP has two instance of general purpose ZDMA. * One is located in FPD (full power domain) which is GDMA and other is located * in LPD (low power domain) which is ADMA. * @@ -115,7 +115,20 @@ * scatter gather mode data transfer and corrected * XZDma_SetChDataConfig API to set over fetch and * src issue parameters correctly. - +* ms 03/17/17 Added readme.txt file in examples folder for doxygen +* generation. +* ms 04/05/17 Modified comment lines notation in functions of zdma +* examples to avoid unnecessary description to get +* displayed while generating doxygen and also changed +* filename tag to include the readonly mode example file +* in doxygen. +* 1.3 mus 08/14/17 Update cache coherency information of the interface in +* its config structure. +* 1.4 adk 11/02/17 Updated examples to fix compilation errors for IAR +* compiler. +* 1.5 adk 11/22/17 Added peripheral test app support for ZDMA driver. +* 12/11/17 Fixed peripheral test app generation issues when dma +* buffers are configured on OCM memory(CR#990806). * * ******************************************************************************/ @@ -132,6 +145,7 @@ extern "C" { #include "xil_assert.h" #include "xstatus.h" #include "xil_cache.h" +#include "bspconfig.h" /************************** Constant Definitions *****************************/ @@ -202,24 +216,38 @@ typedef struct { /** * This typedef contains scatter gather descriptor fields for ZDMA core. */ +#if defined (__ICCARM__) +#pragma pack(push, 1) +#endif typedef struct { u64 Address; /**< Address */ u32 Size; /**< Word2, Size of data */ u32 Cntl; /**< Word3 Control data */ u64 NextDscr; /**< Address of next descriptor */ u64 Reserved; /**< Reserved address */ +#if defined (__ICCARM__) +} XZDma_LlDscr ; +#pragma pack(pop) +#else } __attribute__ ((packed)) XZDma_LlDscr; - +#endif /******************************************************************************/ /** * This typedef contains Linear descriptor fields for ZDMA core. */ +#if defined (__ICCARM__) +#pragma pack(push, 1) +#endif typedef struct { u64 Address; /**< Address */ u32 Size; /**< Word3, Size of data */ u32 Cntl; /**< Word4, control data */ +#if defined (__ICCARM__) +}XZDma_LiDscr; +#pragma pack(pop) +#else } __attribute__ ((packed)) XZDma_LiDscr; - +#endif /******************************************************************************/ /** * @@ -282,6 +310,8 @@ typedef struct { u16 DeviceId; /**< Device Id of ZDMA */ u32 BaseAddress; /**< BaseAddress of ZDMA */ u8 DmaType; /**< Type of DMA */ + u8 IsCacheCoherent; /**< Describes whether Cache Coherent or not; + * Applicable only to A53 in EL1 NS mode */ } XZDma_Config; /******************************************************************************/ @@ -300,6 +330,8 @@ typedef struct { XZDma_Mode Mode; /**< Mode of ZDMA core to be operated */ u8 IsSgDma; /**< Is ZDMA core is in scatter gather or * not will be specified */ + u32 Slcr_adma; /**< Used to hold SLCR ADMA register + * contents */ XZDma_Descriptor Descriptor; /**< It contains information about * descriptors */ diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/zdma_v1_1/src/xzdma_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_5/src/xzdma_g.c similarity index 68% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/zdma_v1_1/src/xzdma_g.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_5/src/xzdma_g.c index 194aac12e..984bf9cbb 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/zdma_v1_1/src/xzdma_g.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_5/src/xzdma_g.c @@ -5,7 +5,7 @@ * Version: * DO NOT EDIT. * -* Copyright (C) 2010-2017 Xilinx, Inc. All Rights Reserved.* +* Copyright (C) 2010-2018 Xilinx, Inc. All Rights Reserved.* *Permission is hereby granted, free of charge, to any person obtaining a copy *of this software and associated documentation files (the Software), to deal *in the Software without restriction, including without limitation the rights @@ -44,87 +44,103 @@ * The configuration table for devices */ -XZDma_Config XZDma_ConfigTable[] = +XZDma_Config XZDma_ConfigTable[XPAR_XZDMA_NUM_INSTANCES] = { { XPAR_PSU_ADMA_0_DEVICE_ID, XPAR_PSU_ADMA_0_BASEADDR, - XPAR_PSU_ADMA_0_DMA_MODE + XPAR_PSU_ADMA_0_DMA_MODE, + XPAR_PSU_ADMA_0_IS_CACHE_COHERENT }, { XPAR_PSU_ADMA_1_DEVICE_ID, XPAR_PSU_ADMA_1_BASEADDR, - XPAR_PSU_ADMA_1_DMA_MODE + XPAR_PSU_ADMA_1_DMA_MODE, + XPAR_PSU_ADMA_1_IS_CACHE_COHERENT }, { XPAR_PSU_ADMA_2_DEVICE_ID, XPAR_PSU_ADMA_2_BASEADDR, - XPAR_PSU_ADMA_2_DMA_MODE + XPAR_PSU_ADMA_2_DMA_MODE, + XPAR_PSU_ADMA_2_IS_CACHE_COHERENT }, { XPAR_PSU_ADMA_3_DEVICE_ID, XPAR_PSU_ADMA_3_BASEADDR, - XPAR_PSU_ADMA_3_DMA_MODE + XPAR_PSU_ADMA_3_DMA_MODE, + XPAR_PSU_ADMA_3_IS_CACHE_COHERENT }, { XPAR_PSU_ADMA_4_DEVICE_ID, XPAR_PSU_ADMA_4_BASEADDR, - XPAR_PSU_ADMA_4_DMA_MODE + XPAR_PSU_ADMA_4_DMA_MODE, + XPAR_PSU_ADMA_4_IS_CACHE_COHERENT }, { XPAR_PSU_ADMA_5_DEVICE_ID, XPAR_PSU_ADMA_5_BASEADDR, - XPAR_PSU_ADMA_5_DMA_MODE + XPAR_PSU_ADMA_5_DMA_MODE, + XPAR_PSU_ADMA_5_IS_CACHE_COHERENT }, { XPAR_PSU_ADMA_6_DEVICE_ID, XPAR_PSU_ADMA_6_BASEADDR, - XPAR_PSU_ADMA_6_DMA_MODE + XPAR_PSU_ADMA_6_DMA_MODE, + XPAR_PSU_ADMA_6_IS_CACHE_COHERENT }, { XPAR_PSU_ADMA_7_DEVICE_ID, XPAR_PSU_ADMA_7_BASEADDR, - XPAR_PSU_ADMA_7_DMA_MODE + XPAR_PSU_ADMA_7_DMA_MODE, + XPAR_PSU_ADMA_7_IS_CACHE_COHERENT }, { XPAR_PSU_GDMA_0_DEVICE_ID, XPAR_PSU_GDMA_0_BASEADDR, - XPAR_PSU_GDMA_0_DMA_MODE + XPAR_PSU_GDMA_0_DMA_MODE, + XPAR_PSU_GDMA_0_IS_CACHE_COHERENT }, { XPAR_PSU_GDMA_1_DEVICE_ID, XPAR_PSU_GDMA_1_BASEADDR, - XPAR_PSU_GDMA_1_DMA_MODE + XPAR_PSU_GDMA_1_DMA_MODE, + XPAR_PSU_GDMA_1_IS_CACHE_COHERENT }, { XPAR_PSU_GDMA_2_DEVICE_ID, XPAR_PSU_GDMA_2_BASEADDR, - XPAR_PSU_GDMA_2_DMA_MODE + XPAR_PSU_GDMA_2_DMA_MODE, + XPAR_PSU_GDMA_2_IS_CACHE_COHERENT }, { XPAR_PSU_GDMA_3_DEVICE_ID, XPAR_PSU_GDMA_3_BASEADDR, - XPAR_PSU_GDMA_3_DMA_MODE + XPAR_PSU_GDMA_3_DMA_MODE, + XPAR_PSU_GDMA_3_IS_CACHE_COHERENT }, { XPAR_PSU_GDMA_4_DEVICE_ID, XPAR_PSU_GDMA_4_BASEADDR, - XPAR_PSU_GDMA_4_DMA_MODE + XPAR_PSU_GDMA_4_DMA_MODE, + XPAR_PSU_GDMA_4_IS_CACHE_COHERENT }, { XPAR_PSU_GDMA_5_DEVICE_ID, XPAR_PSU_GDMA_5_BASEADDR, - XPAR_PSU_GDMA_5_DMA_MODE + XPAR_PSU_GDMA_5_DMA_MODE, + XPAR_PSU_GDMA_5_IS_CACHE_COHERENT }, { XPAR_PSU_GDMA_6_DEVICE_ID, XPAR_PSU_GDMA_6_BASEADDR, - XPAR_PSU_GDMA_6_DMA_MODE + XPAR_PSU_GDMA_6_DMA_MODE, + XPAR_PSU_GDMA_6_IS_CACHE_COHERENT }, { XPAR_PSU_GDMA_7_DEVICE_ID, XPAR_PSU_GDMA_7_BASEADDR, - XPAR_PSU_GDMA_7_DMA_MODE + XPAR_PSU_GDMA_7_DMA_MODE, + XPAR_PSU_GDMA_7_IS_CACHE_COHERENT } }; diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/zdma_v1_1/src/xzdma_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_5/src/xzdma_hw.h similarity index 99% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/zdma_v1_1/src/xzdma_hw.h rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_5/src/xzdma_hw.h index 85f630228..046921cf5 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/zdma_v1_1/src/xzdma_hw.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_5/src/xzdma_hw.h @@ -33,7 +33,7 @@ /** * * @file xzdma_hw.h -* @addtogroup zdma_v1_0 +* @addtogroup zdma_v1_5 * @{ * * This header file contains identifiers and register-level driver functions (or @@ -107,6 +107,7 @@ extern "C" { #define XZDMA_CH_CTRL2_OFFSET (0x200U) /*@}*/ +#define XZDMA_SLCR_SECURE_OFFSET (0xff4b0024) /** @name Interrupt Enable/Disable/Mask/Status registers bit masks and shifts * @{ */ @@ -240,7 +241,7 @@ extern "C" { * mask */ #define XZDMA_DSCR_ATTR_AXCOHRNT_SHIFT (8U) /**< Descriptor coherent shift */ -#define XZDMA_DSCR_ATTR_AXCACHE_SHIFT (7U) /**< Descriptor cache shift */ +#define XZDMA_DSCR_ATTR_AXCACHE_SHIFT (4U) /**< Descriptor cache shift */ #define XZDMA_DSCR_ATTR_RESET_VALUE (0x00000000U) /**< Dscr Attributes * reset value */ diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/xzdma_intr.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_5/src/xzdma_intr.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/xzdma_intr.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_5/src/xzdma_intr.c index e828d16a4..0e6af86e0 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/xzdma_intr.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_5/src/xzdma_intr.c @@ -33,7 +33,7 @@ /** * * @file xzdma_intr.c -* @addtogroup zdma_v1_0 +* @addtogroup zdma_v1_5 * @{ * * This file contains interrupt related functions of Xilinx ZDMA core. diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/zdma_v1_1/src/xzdma_selftest.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_5/src/xzdma_selftest.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/zdma_v1_1/src/xzdma_selftest.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_5/src/xzdma_selftest.c index 893a5402f..9e8b9dcad 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53_bsp/psu_cortexa53_0/libsrc/zdma_v1_1/src/xzdma_selftest.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_5/src/xzdma_selftest.c @@ -33,7 +33,7 @@ /** * * @file xzdma_selftest.c -* @addtogroup zdma_v1_0 +* @addtogroup zdma_v1_5 * @{ * * This file contains the self-test function for the ZDMA core. diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/xzdma_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_5/src/xzdma_sinit.c similarity index 99% rename from FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/xzdma_sinit.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_5/src/xzdma_sinit.c index ae2c44d1c..b033d46b5 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/xzdma_sinit.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_5/src/xzdma_sinit.c @@ -33,7 +33,7 @@ /** * * @file xzdma_sinit.c -* @addtogroup zdma_v1_0 +* @addtogroup zdma_v1_5 * @{ * * This file contains static initialization methods for Xilinx ZDMA core. diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/system.mss b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/system.mss index 1c8fbdb9b..416b7a80d 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/system.mss +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/system.mss @@ -4,7 +4,7 @@ BEGIN OS PARAMETER OS_NAME = standalone - PARAMETER OS_VER = 6.1 + PARAMETER OS_VER = 6.6 PARAMETER PROC_INSTANCE = psu_cortexr5_0 PARAMETER stdin = psu_uart_0 PARAMETER stdout = psu_uart_0 @@ -13,62 +13,62 @@ END BEGIN PROCESSOR PARAMETER DRIVER_NAME = cpu_cortexr5 - PARAMETER DRIVER_VER = 1.1 + PARAMETER DRIVER_VER = 1.4 PARAMETER HW_INSTANCE = psu_cortexr5_0 END BEGIN DRIVER PARAMETER DRIVER_NAME = scugic - PARAMETER DRIVER_VER = 3.5 + PARAMETER DRIVER_VER = 3.9 PARAMETER HW_INSTANCE = psu_acpu_gic END BEGIN DRIVER PARAMETER DRIVER_NAME = zdma - PARAMETER DRIVER_VER = 1.1 + PARAMETER DRIVER_VER = 1.5 PARAMETER HW_INSTANCE = psu_adma_0 END BEGIN DRIVER PARAMETER DRIVER_NAME = zdma - PARAMETER DRIVER_VER = 1.1 + PARAMETER DRIVER_VER = 1.5 PARAMETER HW_INSTANCE = psu_adma_1 END BEGIN DRIVER PARAMETER DRIVER_NAME = zdma - PARAMETER DRIVER_VER = 1.1 + PARAMETER DRIVER_VER = 1.5 PARAMETER HW_INSTANCE = psu_adma_2 END BEGIN DRIVER PARAMETER DRIVER_NAME = zdma - PARAMETER DRIVER_VER = 1.1 + PARAMETER DRIVER_VER = 1.5 PARAMETER HW_INSTANCE = psu_adma_3 END BEGIN DRIVER PARAMETER DRIVER_NAME = zdma - PARAMETER DRIVER_VER = 1.1 + PARAMETER DRIVER_VER = 1.5 PARAMETER HW_INSTANCE = psu_adma_4 END BEGIN DRIVER PARAMETER DRIVER_NAME = zdma - PARAMETER DRIVER_VER = 1.1 + PARAMETER DRIVER_VER = 1.5 PARAMETER HW_INSTANCE = psu_adma_5 END BEGIN DRIVER PARAMETER DRIVER_NAME = zdma - PARAMETER DRIVER_VER = 1.1 + PARAMETER DRIVER_VER = 1.5 PARAMETER HW_INSTANCE = psu_adma_6 END BEGIN DRIVER PARAMETER DRIVER_NAME = zdma - PARAMETER DRIVER_VER = 1.1 + PARAMETER DRIVER_VER = 1.5 PARAMETER HW_INSTANCE = psu_adma_7 END @@ -116,31 +116,31 @@ END BEGIN DRIVER PARAMETER DRIVER_NAME = sysmonpsu - PARAMETER DRIVER_VER = 2.0 + PARAMETER DRIVER_VER = 2.3 PARAMETER HW_INSTANCE = psu_ams END BEGIN DRIVER PARAMETER DRIVER_NAME = axipmon - PARAMETER DRIVER_VER = 6.5 + PARAMETER DRIVER_VER = 6.6 PARAMETER HW_INSTANCE = psu_apm_0 END BEGIN DRIVER PARAMETER DRIVER_NAME = axipmon - PARAMETER DRIVER_VER = 6.5 + PARAMETER DRIVER_VER = 6.6 PARAMETER HW_INSTANCE = psu_apm_1 END BEGIN DRIVER PARAMETER DRIVER_NAME = axipmon - PARAMETER DRIVER_VER = 6.5 + PARAMETER DRIVER_VER = 6.6 PARAMETER HW_INSTANCE = psu_apm_2 END BEGIN DRIVER PARAMETER DRIVER_NAME = axipmon - PARAMETER DRIVER_VER = 6.5 + PARAMETER DRIVER_VER = 6.6 PARAMETER HW_INSTANCE = psu_apm_5 END @@ -170,13 +170,13 @@ END BEGIN DRIVER PARAMETER DRIVER_NAME = coresightps_dcc - PARAMETER DRIVER_VER = 1.3 + PARAMETER DRIVER_VER = 1.4 PARAMETER HW_INSTANCE = psu_coresight_0 END BEGIN DRIVER - PARAMETER DRIVER_NAME = generic - PARAMETER DRIVER_VER = 2.0 + PARAMETER DRIVER_NAME = resetps + PARAMETER DRIVER_VER = 1.0 PARAMETER HW_INSTANCE = psu_crf_apb END @@ -186,12 +186,24 @@ BEGIN DRIVER PARAMETER HW_INSTANCE = psu_crl_apb END +BEGIN DRIVER + PARAMETER DRIVER_NAME = wdtps + PARAMETER DRIVER_VER = 3.0 + PARAMETER HW_INSTANCE = psu_csu_wdt +END + BEGIN DRIVER PARAMETER DRIVER_NAME = csudma - PARAMETER DRIVER_VER = 1.1 + PARAMETER DRIVER_VER = 1.2 PARAMETER HW_INSTANCE = psu_csudma END +BEGIN DRIVER + PARAMETER DRIVER_NAME = generic + PARAMETER DRIVER_VER = 2.0 + PARAMETER HW_INSTANCE = psu_ctrl_ipi +END + BEGIN DRIVER PARAMETER DRIVER_NAME = generic PARAMETER DRIVER_VER = 2.0 @@ -247,14 +259,14 @@ BEGIN DRIVER END BEGIN DRIVER - PARAMETER DRIVER_NAME = generic - PARAMETER DRIVER_VER = 2.0 + PARAMETER DRIVER_NAME = avbuf + PARAMETER DRIVER_VER = 2.1 PARAMETER HW_INSTANCE = psu_dp END BEGIN DRIVER - PARAMETER DRIVER_NAME = generic - PARAMETER DRIVER_VER = 2.0 + PARAMETER DRIVER_NAME = dpdma + PARAMETER DRIVER_VER = 1.0 PARAMETER HW_INSTANCE = psu_dpdma END @@ -266,7 +278,7 @@ END BEGIN DRIVER PARAMETER DRIVER_NAME = emacps - PARAMETER DRIVER_VER = 3.3 + PARAMETER DRIVER_VER = 3.7 PARAMETER HW_INSTANCE = psu_ethernet_3 END @@ -302,55 +314,55 @@ END BEGIN DRIVER PARAMETER DRIVER_NAME = zdma - PARAMETER DRIVER_VER = 1.1 + PARAMETER DRIVER_VER = 1.5 PARAMETER HW_INSTANCE = psu_gdma_0 END BEGIN DRIVER PARAMETER DRIVER_NAME = zdma - PARAMETER DRIVER_VER = 1.1 + PARAMETER DRIVER_VER = 1.5 PARAMETER HW_INSTANCE = psu_gdma_1 END BEGIN DRIVER PARAMETER DRIVER_NAME = zdma - PARAMETER DRIVER_VER = 1.1 + PARAMETER DRIVER_VER = 1.5 PARAMETER HW_INSTANCE = psu_gdma_2 END BEGIN DRIVER PARAMETER DRIVER_NAME = zdma - PARAMETER DRIVER_VER = 1.1 + PARAMETER DRIVER_VER = 1.5 PARAMETER HW_INSTANCE = psu_gdma_3 END BEGIN DRIVER PARAMETER DRIVER_NAME = zdma - PARAMETER DRIVER_VER = 1.1 + PARAMETER DRIVER_VER = 1.5 PARAMETER HW_INSTANCE = psu_gdma_4 END BEGIN DRIVER PARAMETER DRIVER_NAME = zdma - PARAMETER DRIVER_VER = 1.1 + PARAMETER DRIVER_VER = 1.5 PARAMETER HW_INSTANCE = psu_gdma_5 END BEGIN DRIVER PARAMETER DRIVER_NAME = zdma - PARAMETER DRIVER_VER = 1.1 + PARAMETER DRIVER_VER = 1.5 PARAMETER HW_INSTANCE = psu_gdma_6 END BEGIN DRIVER PARAMETER DRIVER_NAME = zdma - PARAMETER DRIVER_VER = 1.1 + PARAMETER DRIVER_VER = 1.5 PARAMETER HW_INSTANCE = psu_gdma_7 END BEGIN DRIVER PARAMETER DRIVER_NAME = gpiops - PARAMETER DRIVER_VER = 3.1 + PARAMETER DRIVER_VER = 3.3 PARAMETER HW_INSTANCE = psu_gpio_0 END @@ -362,13 +374,13 @@ END BEGIN DRIVER PARAMETER DRIVER_NAME = iicps - PARAMETER DRIVER_VER = 3.4 + PARAMETER DRIVER_VER = 3.6 PARAMETER HW_INSTANCE = psu_i2c_0 END BEGIN DRIVER PARAMETER DRIVER_NAME = iicps - PARAMETER DRIVER_VER = 3.4 + PARAMETER DRIVER_VER = 3.6 PARAMETER HW_INSTANCE = psu_i2c_1 END @@ -398,7 +410,7 @@ END BEGIN DRIVER PARAMETER DRIVER_NAME = ipipsu - PARAMETER DRIVER_VER = 2.1 + PARAMETER DRIVER_VER = 2.3 PARAMETER HW_INSTANCE = psu_ipi_1 END @@ -432,6 +444,12 @@ BEGIN DRIVER PARAMETER HW_INSTANCE = psu_mbistjtag END +BEGIN DRIVER + PARAMETER DRIVER_NAME = generic + PARAMETER DRIVER_VER = 2.0 + PARAMETER HW_INSTANCE = psu_message_buffers +END + BEGIN DRIVER PARAMETER DRIVER_NAME = generic PARAMETER DRIVER_VER = 2.0 @@ -468,6 +486,18 @@ BEGIN DRIVER PARAMETER HW_INSTANCE = psu_pcie_dma END +BEGIN DRIVER + PARAMETER DRIVER_NAME = generic + PARAMETER DRIVER_VER = 2.0 + PARAMETER HW_INSTANCE = psu_pcie_high1 +END + +BEGIN DRIVER + PARAMETER DRIVER_NAME = generic + PARAMETER DRIVER_VER = 2.0 + PARAMETER HW_INSTANCE = psu_pcie_high2 +END + BEGIN DRIVER PARAMETER DRIVER_NAME = generic PARAMETER DRIVER_VER = 2.0 @@ -480,15 +510,9 @@ BEGIN DRIVER PARAMETER HW_INSTANCE = psu_pmu_global_0 END -BEGIN DRIVER - PARAMETER DRIVER_NAME = generic - PARAMETER DRIVER_VER = 2.0 - PARAMETER HW_INSTANCE = psu_pmu_iomodule -END - BEGIN DRIVER PARAMETER DRIVER_NAME = qspipsu - PARAMETER DRIVER_VER = 1.3 + PARAMETER DRIVER_VER = 1.7 PARAMETER HW_INSTANCE = psu_qspi_0 END @@ -524,7 +548,7 @@ END BEGIN DRIVER PARAMETER DRIVER_NAME = scugic - PARAMETER DRIVER_VER = 3.5 + PARAMETER DRIVER_VER = 3.9 PARAMETER HW_INSTANCE = psu_rcpu_gic END @@ -542,7 +566,7 @@ END BEGIN DRIVER PARAMETER DRIVER_NAME = rtcpsu - PARAMETER DRIVER_VER = 1.3 + PARAMETER DRIVER_VER = 1.5 PARAMETER HW_INSTANCE = psu_rtc END @@ -554,7 +578,7 @@ END BEGIN DRIVER PARAMETER DRIVER_NAME = sdps - PARAMETER DRIVER_VER = 3.1 + PARAMETER DRIVER_VER = 3.4 PARAMETER HW_INSTANCE = psu_sd_1 END @@ -584,46 +608,52 @@ END BEGIN DRIVER PARAMETER DRIVER_NAME = ttcps - PARAMETER DRIVER_VER = 3.2 + PARAMETER DRIVER_VER = 3.5 PARAMETER HW_INSTANCE = psu_ttc_0 END BEGIN DRIVER PARAMETER DRIVER_NAME = ttcps - PARAMETER DRIVER_VER = 3.2 + PARAMETER DRIVER_VER = 3.5 PARAMETER HW_INSTANCE = psu_ttc_1 END BEGIN DRIVER PARAMETER DRIVER_NAME = ttcps - PARAMETER DRIVER_VER = 3.2 + PARAMETER DRIVER_VER = 3.5 PARAMETER HW_INSTANCE = psu_ttc_2 END BEGIN DRIVER PARAMETER DRIVER_NAME = ttcps - PARAMETER DRIVER_VER = 3.2 + PARAMETER DRIVER_VER = 3.5 PARAMETER HW_INSTANCE = psu_ttc_3 END BEGIN DRIVER PARAMETER DRIVER_NAME = uartps - PARAMETER DRIVER_VER = 3.3 + PARAMETER DRIVER_VER = 3.6 PARAMETER HW_INSTANCE = psu_uart_0 END BEGIN DRIVER PARAMETER DRIVER_NAME = uartps - PARAMETER DRIVER_VER = 3.3 + PARAMETER DRIVER_VER = 3.6 PARAMETER HW_INSTANCE = psu_uart_1 END BEGIN DRIVER - PARAMETER DRIVER_NAME = usbpsu - PARAMETER DRIVER_VER = 1.1 + PARAMETER DRIVER_NAME = generic + PARAMETER DRIVER_VER = 2.0 PARAMETER HW_INSTANCE = psu_usb_0 END +BEGIN DRIVER + PARAMETER DRIVER_NAME = usbpsu + PARAMETER DRIVER_VER = 1.4 + PARAMETER HW_INSTANCE = psu_usb_xhci_0 +END + BEGIN DRIVER PARAMETER DRIVER_NAME = wdtps PARAMETER DRIVER_VER = 3.0 diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init.c index f206bc7bf..5331ca872 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init.c @@ -34,21100 +34,21787 @@ * * @file psu_init.c * -* This file is automatically generated +* This file is automatically generated * *****************************************************************************/ #include #include #include "psu_init.h" +#define DPLL_CFG_LOCK_DLY 63 +#define DPLL_CFG_LOCK_CNT 625 +#define DPLL_CFG_LFHF 3 +#define DPLL_CFG_CP 3 +#define DPLL_CFG_RES 2 -int mask_pollOnValue(u32 add , u32 mask, u32 value ); +static int mask_pollOnValue(u32 add, u32 mask, u32 value); -int mask_poll(u32 add , u32 mask ); +static int mask_poll(u32 add, u32 mask); -void mask_delay(u32 delay); +static void mask_delay(u32 delay); -u32 mask_read(u32 add , u32 mask ); +static u32 mask_read(u32 add, u32 mask); -static void PSU_Mask_Write (unsigned long offset, unsigned long mask, unsigned long val) +static void dpll_prog(int ddr_pll_fbdiv, int d_lock_dly, + int d_lock_cnt, int d_lfhf, int d_cp, int d_res); + +static +void PSU_Mask_Write(unsigned long offset, unsigned long mask, + unsigned long val) { unsigned long RegVal = 0x0; - RegVal = Xil_In32 (offset); + + RegVal = Xil_In32(offset); RegVal &= ~(mask); RegVal |= (val & mask); - Xil_Out32 (offset, RegVal); + Xil_Out32(offset, RegVal); } - void prog_reg (unsigned long addr, unsigned long mask, unsigned long shift, unsigned long value) { - int rdata =0; + void prog_reg(unsigned long addr, unsigned long mask, + unsigned long shift, unsigned long value) { + int rdata = 0; + rdata = Xil_In32(addr); rdata = rdata & (~mask); rdata = rdata | (value << shift); - Xil_Out32(addr,rdata); - } - -unsigned long psu_pll_init_data() { - // : RPLL INIT - /*Register : RPLL_CFG @ 0XFF5E0034

- - PLL loop filter resistor control - PSU_CRL_APB_RPLL_CFG_RES 0x2 - - PLL charge pump control - PSU_CRL_APB_RPLL_CFG_CP 0x3 - - PLL loop filter high frequency capacitor control - PSU_CRL_APB_RPLL_CFG_LFHF 0x3 - - Lock circuit counter setting - PSU_CRL_APB_RPLL_CFG_LOCK_CNT 0x258 - - Lock circuit configuration settings for lock windowsize - PSU_CRL_APB_RPLL_CFG_LOCK_DLY 0x3f - - Helper data. Values are to be looked up in a table from Data Sheet - (OFFSET, MASK, VALUE) (0XFF5E0034, 0xFE7FEDEFU ,0x7E4B0C62U) - RegMask = (CRL_APB_RPLL_CFG_RES_MASK | CRL_APB_RPLL_CFG_CP_MASK | CRL_APB_RPLL_CFG_LFHF_MASK | CRL_APB_RPLL_CFG_LOCK_CNT_MASK | CRL_APB_RPLL_CFG_LOCK_DLY_MASK | 0 ); - - RegVal = ((0x00000002U << CRL_APB_RPLL_CFG_RES_SHIFT - | 0x00000003U << CRL_APB_RPLL_CFG_CP_SHIFT - | 0x00000003U << CRL_APB_RPLL_CFG_LFHF_SHIFT - | 0x00000258U << CRL_APB_RPLL_CFG_LOCK_CNT_SHIFT - | 0x0000003FU << CRL_APB_RPLL_CFG_LOCK_DLY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RPLL_CFG_OFFSET ,0xFE7FEDEFU ,0x7E4B0C62U); - /*############################################################################################################################ */ - - // : UPDATE FB_DIV - /*Register : RPLL_CTRL @ 0XFF5E0030

- - Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_ - ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source - PSU_CRL_APB_RPLL_CTRL_PRE_SRC 0x0 - - The integer portion of the feedback divider to the PLL - PSU_CRL_APB_RPLL_CTRL_FBDIV 0x48 - - This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency - PSU_CRL_APB_RPLL_CTRL_DIV2 0x1 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFF5E0030, 0x00717F00U ,0x00014800U) - RegMask = (CRL_APB_RPLL_CTRL_PRE_SRC_MASK | CRL_APB_RPLL_CTRL_FBDIV_MASK | CRL_APB_RPLL_CTRL_DIV2_MASK | 0 ); - - RegVal = ((0x00000000U << CRL_APB_RPLL_CTRL_PRE_SRC_SHIFT - | 0x00000048U << CRL_APB_RPLL_CTRL_FBDIV_SHIFT - | 0x00000001U << CRL_APB_RPLL_CTRL_DIV2_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RPLL_CTRL_OFFSET ,0x00717F00U ,0x00014800U); - /*############################################################################################################################ */ - - // : BY PASS PLL - /*Register : RPLL_CTRL @ 0XFF5E0030

- - Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_RPLL_CTRL_BYPASS 1 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFF5E0030, 0x00000008U ,0x00000008U) - RegMask = (CRL_APB_RPLL_CTRL_BYPASS_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_RPLL_CTRL_BYPASS_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RPLL_CTRL_OFFSET ,0x00000008U ,0x00000008U); - /*############################################################################################################################ */ - - // : ASSERT RESET - /*Register : RPLL_CTRL @ 0XFF5E0030

- - Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS. - PSU_CRL_APB_RPLL_CTRL_RESET 1 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFF5E0030, 0x00000001U ,0x00000001U) - RegMask = (CRL_APB_RPLL_CTRL_RESET_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_RPLL_CTRL_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RPLL_CTRL_OFFSET ,0x00000001U ,0x00000001U); - /*############################################################################################################################ */ - - // : DEASSERT RESET - /*Register : RPLL_CTRL @ 0XFF5E0030

- - Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS. - PSU_CRL_APB_RPLL_CTRL_RESET 0 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFF5E0030, 0x00000001U ,0x00000000U) - RegMask = (CRL_APB_RPLL_CTRL_RESET_MASK | 0 ); - - RegVal = ((0x00000000U << CRL_APB_RPLL_CTRL_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RPLL_CTRL_OFFSET ,0x00000001U ,0x00000000U); - /*############################################################################################################################ */ - - // : CHECK PLL STATUS - /*Register : PLL_STATUS @ 0XFF5E0040

- - RPLL is locked - PSU_CRL_APB_PLL_STATUS_RPLL_LOCK 1 - (OFFSET, MASK, VALUE) (0XFF5E0040, 0x00000002U ,0x00000002U) */ - mask_poll(CRL_APB_PLL_STATUS_OFFSET,0x00000002U); - - /*############################################################################################################################ */ - - // : REMOVE PLL BY PASS - /*Register : RPLL_CTRL @ 0XFF5E0030

- - Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_RPLL_CTRL_BYPASS 0 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFF5E0030, 0x00000008U ,0x00000000U) - RegMask = (CRL_APB_RPLL_CTRL_BYPASS_MASK | 0 ); - - RegVal = ((0x00000000U << CRL_APB_RPLL_CTRL_BYPASS_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RPLL_CTRL_OFFSET ,0x00000008U ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : RPLL_TO_FPD_CTRL @ 0XFF5E0048

- - Divisor value for this clock. - PSU_CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0 0x3 - - Control for a clock that will be generated in the LPD, but used in the FPD as a clock source for the peripheral clock muxes. - (OFFSET, MASK, VALUE) (0XFF5E0048, 0x00003F00U ,0x00000300U) - RegMask = (CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_MASK | 0 ); - - RegVal = ((0x00000003U << CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RPLL_TO_FPD_CTRL_OFFSET ,0x00003F00U ,0x00000300U); - /*############################################################################################################################ */ - - // : RPLL FRAC CFG - /*Register : RPLL_FRAC_CFG @ 0XFF5E0038

- - Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona - mode and uses DATA of this register for the fractional portion of the feedback divider. - PSU_CRL_APB_RPLL_FRAC_CFG_ENABLED 0x0 - - Fractional value for the Feedback value. - PSU_CRL_APB_RPLL_FRAC_CFG_DATA 0x0 - - Fractional control for the PLL - (OFFSET, MASK, VALUE) (0XFF5E0038, 0x8000FFFFU ,0x00000000U) - RegMask = (CRL_APB_RPLL_FRAC_CFG_ENABLED_MASK | CRL_APB_RPLL_FRAC_CFG_DATA_MASK | 0 ); - - RegVal = ((0x00000000U << CRL_APB_RPLL_FRAC_CFG_ENABLED_SHIFT - | 0x00000000U << CRL_APB_RPLL_FRAC_CFG_DATA_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RPLL_FRAC_CFG_OFFSET ,0x8000FFFFU ,0x00000000U); - /*############################################################################################################################ */ - - // : IOPLL INIT - /*Register : IOPLL_CFG @ 0XFF5E0024

- - PLL loop filter resistor control - PSU_CRL_APB_IOPLL_CFG_RES 0xc - - PLL charge pump control - PSU_CRL_APB_IOPLL_CFG_CP 0x3 - - PLL loop filter high frequency capacitor control - PSU_CRL_APB_IOPLL_CFG_LFHF 0x3 - - Lock circuit counter setting - PSU_CRL_APB_IOPLL_CFG_LOCK_CNT 0x339 - - Lock circuit configuration settings for lock windowsize - PSU_CRL_APB_IOPLL_CFG_LOCK_DLY 0x3f - - Helper data. Values are to be looked up in a table from Data Sheet - (OFFSET, MASK, VALUE) (0XFF5E0024, 0xFE7FEDEFU ,0x7E672C6CU) - RegMask = (CRL_APB_IOPLL_CFG_RES_MASK | CRL_APB_IOPLL_CFG_CP_MASK | CRL_APB_IOPLL_CFG_LFHF_MASK | CRL_APB_IOPLL_CFG_LOCK_CNT_MASK | CRL_APB_IOPLL_CFG_LOCK_DLY_MASK | 0 ); - - RegVal = ((0x0000000CU << CRL_APB_IOPLL_CFG_RES_SHIFT - | 0x00000003U << CRL_APB_IOPLL_CFG_CP_SHIFT - | 0x00000003U << CRL_APB_IOPLL_CFG_LFHF_SHIFT - | 0x00000339U << CRL_APB_IOPLL_CFG_LOCK_CNT_SHIFT - | 0x0000003FU << CRL_APB_IOPLL_CFG_LOCK_DLY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_IOPLL_CFG_OFFSET ,0xFE7FEDEFU ,0x7E672C6CU); - /*############################################################################################################################ */ - - // : UPDATE FB_DIV - /*Register : IOPLL_CTRL @ 0XFF5E0020

- - Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_ - ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source - PSU_CRL_APB_IOPLL_CTRL_PRE_SRC 0x0 - - The integer portion of the feedback divider to the PLL - PSU_CRL_APB_IOPLL_CTRL_FBDIV 0x2d - - This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency - PSU_CRL_APB_IOPLL_CTRL_DIV2 0x0 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFF5E0020, 0x00717F00U ,0x00002D00U) - RegMask = (CRL_APB_IOPLL_CTRL_PRE_SRC_MASK | CRL_APB_IOPLL_CTRL_FBDIV_MASK | CRL_APB_IOPLL_CTRL_DIV2_MASK | 0 ); - - RegVal = ((0x00000000U << CRL_APB_IOPLL_CTRL_PRE_SRC_SHIFT - | 0x0000002DU << CRL_APB_IOPLL_CTRL_FBDIV_SHIFT - | 0x00000000U << CRL_APB_IOPLL_CTRL_DIV2_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_IOPLL_CTRL_OFFSET ,0x00717F00U ,0x00002D00U); - /*############################################################################################################################ */ - - // : BY PASS PLL - /*Register : IOPLL_CTRL @ 0XFF5E0020

- - Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_IOPLL_CTRL_BYPASS 1 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFF5E0020, 0x00000008U ,0x00000008U) - RegMask = (CRL_APB_IOPLL_CTRL_BYPASS_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_IOPLL_CTRL_BYPASS_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_IOPLL_CTRL_OFFSET ,0x00000008U ,0x00000008U); - /*############################################################################################################################ */ - - // : ASSERT RESET - /*Register : IOPLL_CTRL @ 0XFF5E0020

- - Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS. - PSU_CRL_APB_IOPLL_CTRL_RESET 1 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFF5E0020, 0x00000001U ,0x00000001U) - RegMask = (CRL_APB_IOPLL_CTRL_RESET_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_IOPLL_CTRL_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_IOPLL_CTRL_OFFSET ,0x00000001U ,0x00000001U); - /*############################################################################################################################ */ - - // : DEASSERT RESET - /*Register : IOPLL_CTRL @ 0XFF5E0020

- - Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS. - PSU_CRL_APB_IOPLL_CTRL_RESET 0 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFF5E0020, 0x00000001U ,0x00000000U) - RegMask = (CRL_APB_IOPLL_CTRL_RESET_MASK | 0 ); - - RegVal = ((0x00000000U << CRL_APB_IOPLL_CTRL_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_IOPLL_CTRL_OFFSET ,0x00000001U ,0x00000000U); - /*############################################################################################################################ */ - - // : CHECK PLL STATUS - /*Register : PLL_STATUS @ 0XFF5E0040

- - IOPLL is locked - PSU_CRL_APB_PLL_STATUS_IOPLL_LOCK 1 - (OFFSET, MASK, VALUE) (0XFF5E0040, 0x00000001U ,0x00000001U) */ - mask_poll(CRL_APB_PLL_STATUS_OFFSET,0x00000001U); - - /*############################################################################################################################ */ - - // : REMOVE PLL BY PASS - /*Register : IOPLL_CTRL @ 0XFF5E0020

- - Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_IOPLL_CTRL_BYPASS 0 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFF5E0020, 0x00000008U ,0x00000000U) - RegMask = (CRL_APB_IOPLL_CTRL_BYPASS_MASK | 0 ); - - RegVal = ((0x00000000U << CRL_APB_IOPLL_CTRL_BYPASS_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_IOPLL_CTRL_OFFSET ,0x00000008U ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : IOPLL_TO_FPD_CTRL @ 0XFF5E0044

- - Divisor value for this clock. - PSU_CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0 0x3 - - Control for a clock that will be generated in the LPD, but used in the FPD as a clock source for the peripheral clock muxes. - (OFFSET, MASK, VALUE) (0XFF5E0044, 0x00003F00U ,0x00000300U) - RegMask = (CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_MASK | 0 ); - - RegVal = ((0x00000003U << CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_IOPLL_TO_FPD_CTRL_OFFSET ,0x00003F00U ,0x00000300U); - /*############################################################################################################################ */ - - // : IOPLL FRAC CFG - /*Register : IOPLL_FRAC_CFG @ 0XFF5E0028

- - Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona - mode and uses DATA of this register for the fractional portion of the feedback divider. - PSU_CRL_APB_IOPLL_FRAC_CFG_ENABLED 0x0 - - Fractional value for the Feedback value. - PSU_CRL_APB_IOPLL_FRAC_CFG_DATA 0x0 - - Fractional control for the PLL - (OFFSET, MASK, VALUE) (0XFF5E0028, 0x8000FFFFU ,0x00000000U) - RegMask = (CRL_APB_IOPLL_FRAC_CFG_ENABLED_MASK | CRL_APB_IOPLL_FRAC_CFG_DATA_MASK | 0 ); - - RegVal = ((0x00000000U << CRL_APB_IOPLL_FRAC_CFG_ENABLED_SHIFT - | 0x00000000U << CRL_APB_IOPLL_FRAC_CFG_DATA_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_IOPLL_FRAC_CFG_OFFSET ,0x8000FFFFU ,0x00000000U); - /*############################################################################################################################ */ - - // : APU_PLL INIT - /*Register : APLL_CFG @ 0XFD1A0024

- - PLL loop filter resistor control - PSU_CRF_APB_APLL_CFG_RES 0x2 - - PLL charge pump control - PSU_CRF_APB_APLL_CFG_CP 0x3 - - PLL loop filter high frequency capacitor control - PSU_CRF_APB_APLL_CFG_LFHF 0x3 - - Lock circuit counter setting - PSU_CRF_APB_APLL_CFG_LOCK_CNT 0x258 - - Lock circuit configuration settings for lock windowsize - PSU_CRF_APB_APLL_CFG_LOCK_DLY 0x3f - - Helper data. Values are to be looked up in a table from Data Sheet - (OFFSET, MASK, VALUE) (0XFD1A0024, 0xFE7FEDEFU ,0x7E4B0C62U) - RegMask = (CRF_APB_APLL_CFG_RES_MASK | CRF_APB_APLL_CFG_CP_MASK | CRF_APB_APLL_CFG_LFHF_MASK | CRF_APB_APLL_CFG_LOCK_CNT_MASK | CRF_APB_APLL_CFG_LOCK_DLY_MASK | 0 ); - - RegVal = ((0x00000002U << CRF_APB_APLL_CFG_RES_SHIFT - | 0x00000003U << CRF_APB_APLL_CFG_CP_SHIFT - | 0x00000003U << CRF_APB_APLL_CFG_LFHF_SHIFT - | 0x00000258U << CRF_APB_APLL_CFG_LOCK_CNT_SHIFT - | 0x0000003FU << CRF_APB_APLL_CFG_LOCK_DLY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_APLL_CFG_OFFSET ,0xFE7FEDEFU ,0x7E4B0C62U); - /*############################################################################################################################ */ - - // : UPDATE FB_DIV - /*Register : APLL_CTRL @ 0XFD1A0020

- - Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_ - ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source - PSU_CRF_APB_APLL_CTRL_PRE_SRC 0x0 - - The integer portion of the feedback divider to the PLL - PSU_CRF_APB_APLL_CTRL_FBDIV 0x42 - - This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency - PSU_CRF_APB_APLL_CTRL_DIV2 0x1 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFD1A0020, 0x00717F00U ,0x00014200U) - RegMask = (CRF_APB_APLL_CTRL_PRE_SRC_MASK | CRF_APB_APLL_CTRL_FBDIV_MASK | CRF_APB_APLL_CTRL_DIV2_MASK | 0 ); - - RegVal = ((0x00000000U << CRF_APB_APLL_CTRL_PRE_SRC_SHIFT - | 0x00000042U << CRF_APB_APLL_CTRL_FBDIV_SHIFT - | 0x00000001U << CRF_APB_APLL_CTRL_DIV2_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_APLL_CTRL_OFFSET ,0x00717F00U ,0x00014200U); - /*############################################################################################################################ */ - - // : BY PASS PLL - /*Register : APLL_CTRL @ 0XFD1A0020

- - Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.) - PSU_CRF_APB_APLL_CTRL_BYPASS 1 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFD1A0020, 0x00000008U ,0x00000008U) - RegMask = (CRF_APB_APLL_CTRL_BYPASS_MASK | 0 ); - - RegVal = ((0x00000001U << CRF_APB_APLL_CTRL_BYPASS_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_APLL_CTRL_OFFSET ,0x00000008U ,0x00000008U); - /*############################################################################################################################ */ - - // : ASSERT RESET - /*Register : APLL_CTRL @ 0XFD1A0020

- - Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS. - PSU_CRF_APB_APLL_CTRL_RESET 1 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFD1A0020, 0x00000001U ,0x00000001U) - RegMask = (CRF_APB_APLL_CTRL_RESET_MASK | 0 ); - - RegVal = ((0x00000001U << CRF_APB_APLL_CTRL_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_APLL_CTRL_OFFSET ,0x00000001U ,0x00000001U); - /*############################################################################################################################ */ - - // : DEASSERT RESET - /*Register : APLL_CTRL @ 0XFD1A0020

- - Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS. - PSU_CRF_APB_APLL_CTRL_RESET 0 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFD1A0020, 0x00000001U ,0x00000000U) - RegMask = (CRF_APB_APLL_CTRL_RESET_MASK | 0 ); - - RegVal = ((0x00000000U << CRF_APB_APLL_CTRL_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_APLL_CTRL_OFFSET ,0x00000001U ,0x00000000U); - /*############################################################################################################################ */ - - // : CHECK PLL STATUS - /*Register : PLL_STATUS @ 0XFD1A0044

- - APLL is locked - PSU_CRF_APB_PLL_STATUS_APLL_LOCK 1 - (OFFSET, MASK, VALUE) (0XFD1A0044, 0x00000001U ,0x00000001U) */ - mask_poll(CRF_APB_PLL_STATUS_OFFSET,0x00000001U); - - /*############################################################################################################################ */ - - // : REMOVE PLL BY PASS - /*Register : APLL_CTRL @ 0XFD1A0020

- - Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.) - PSU_CRF_APB_APLL_CTRL_BYPASS 0 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFD1A0020, 0x00000008U ,0x00000000U) - RegMask = (CRF_APB_APLL_CTRL_BYPASS_MASK | 0 ); - - RegVal = ((0x00000000U << CRF_APB_APLL_CTRL_BYPASS_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_APLL_CTRL_OFFSET ,0x00000008U ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : APLL_TO_LPD_CTRL @ 0XFD1A0048

- - Divisor value for this clock. - PSU_CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0 0x3 - - Control for a clock that will be generated in the FPD, but used in the LPD as a clock source for the peripheral clock muxes. - (OFFSET, MASK, VALUE) (0XFD1A0048, 0x00003F00U ,0x00000300U) - RegMask = (CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_MASK | 0 ); - - RegVal = ((0x00000003U << CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_APLL_TO_LPD_CTRL_OFFSET ,0x00003F00U ,0x00000300U); - /*############################################################################################################################ */ - - // : APLL FRAC CFG - /*Register : APLL_FRAC_CFG @ 0XFD1A0028

- - Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona - mode and uses DATA of this register for the fractional portion of the feedback divider. - PSU_CRF_APB_APLL_FRAC_CFG_ENABLED 0x0 - - Fractional value for the Feedback value. - PSU_CRF_APB_APLL_FRAC_CFG_DATA 0x0 - - Fractional control for the PLL - (OFFSET, MASK, VALUE) (0XFD1A0028, 0x8000FFFFU ,0x00000000U) - RegMask = (CRF_APB_APLL_FRAC_CFG_ENABLED_MASK | CRF_APB_APLL_FRAC_CFG_DATA_MASK | 0 ); - - RegVal = ((0x00000000U << CRF_APB_APLL_FRAC_CFG_ENABLED_SHIFT - | 0x00000000U << CRF_APB_APLL_FRAC_CFG_DATA_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_APLL_FRAC_CFG_OFFSET ,0x8000FFFFU ,0x00000000U); - /*############################################################################################################################ */ - - // : DDR_PLL INIT - /*Register : DPLL_CFG @ 0XFD1A0030

- - PLL loop filter resistor control - PSU_CRF_APB_DPLL_CFG_RES 0x2 - - PLL charge pump control - PSU_CRF_APB_DPLL_CFG_CP 0x3 - - PLL loop filter high frequency capacitor control - PSU_CRF_APB_DPLL_CFG_LFHF 0x3 - - Lock circuit counter setting - PSU_CRF_APB_DPLL_CFG_LOCK_CNT 0x258 - - Lock circuit configuration settings for lock windowsize - PSU_CRF_APB_DPLL_CFG_LOCK_DLY 0x3f - - Helper data. Values are to be looked up in a table from Data Sheet - (OFFSET, MASK, VALUE) (0XFD1A0030, 0xFE7FEDEFU ,0x7E4B0C62U) - RegMask = (CRF_APB_DPLL_CFG_RES_MASK | CRF_APB_DPLL_CFG_CP_MASK | CRF_APB_DPLL_CFG_LFHF_MASK | CRF_APB_DPLL_CFG_LOCK_CNT_MASK | CRF_APB_DPLL_CFG_LOCK_DLY_MASK | 0 ); - - RegVal = ((0x00000002U << CRF_APB_DPLL_CFG_RES_SHIFT - | 0x00000003U << CRF_APB_DPLL_CFG_CP_SHIFT - | 0x00000003U << CRF_APB_DPLL_CFG_LFHF_SHIFT - | 0x00000258U << CRF_APB_DPLL_CFG_LOCK_CNT_SHIFT - | 0x0000003FU << CRF_APB_DPLL_CFG_LOCK_DLY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_DPLL_CFG_OFFSET ,0xFE7FEDEFU ,0x7E4B0C62U); - /*############################################################################################################################ */ - - // : UPDATE FB_DIV - /*Register : DPLL_CTRL @ 0XFD1A002C

- - Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_ - ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source - PSU_CRF_APB_DPLL_CTRL_PRE_SRC 0x0 - - The integer portion of the feedback divider to the PLL - PSU_CRF_APB_DPLL_CTRL_FBDIV 0x40 - - This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency - PSU_CRF_APB_DPLL_CTRL_DIV2 0x1 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFD1A002C, 0x00717F00U ,0x00014000U) - RegMask = (CRF_APB_DPLL_CTRL_PRE_SRC_MASK | CRF_APB_DPLL_CTRL_FBDIV_MASK | CRF_APB_DPLL_CTRL_DIV2_MASK | 0 ); - - RegVal = ((0x00000000U << CRF_APB_DPLL_CTRL_PRE_SRC_SHIFT - | 0x00000040U << CRF_APB_DPLL_CTRL_FBDIV_SHIFT - | 0x00000001U << CRF_APB_DPLL_CTRL_DIV2_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_DPLL_CTRL_OFFSET ,0x00717F00U ,0x00014000U); - /*############################################################################################################################ */ - - // : BY PASS PLL - /*Register : DPLL_CTRL @ 0XFD1A002C

- - Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.) - PSU_CRF_APB_DPLL_CTRL_BYPASS 1 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFD1A002C, 0x00000008U ,0x00000008U) - RegMask = (CRF_APB_DPLL_CTRL_BYPASS_MASK | 0 ); - - RegVal = ((0x00000001U << CRF_APB_DPLL_CTRL_BYPASS_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_DPLL_CTRL_OFFSET ,0x00000008U ,0x00000008U); - /*############################################################################################################################ */ - - // : ASSERT RESET - /*Register : DPLL_CTRL @ 0XFD1A002C

- - Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS. - PSU_CRF_APB_DPLL_CTRL_RESET 1 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFD1A002C, 0x00000001U ,0x00000001U) - RegMask = (CRF_APB_DPLL_CTRL_RESET_MASK | 0 ); - - RegVal = ((0x00000001U << CRF_APB_DPLL_CTRL_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_DPLL_CTRL_OFFSET ,0x00000001U ,0x00000001U); - /*############################################################################################################################ */ - - // : DEASSERT RESET - /*Register : DPLL_CTRL @ 0XFD1A002C

- - Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS. - PSU_CRF_APB_DPLL_CTRL_RESET 0 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFD1A002C, 0x00000001U ,0x00000000U) - RegMask = (CRF_APB_DPLL_CTRL_RESET_MASK | 0 ); - - RegVal = ((0x00000000U << CRF_APB_DPLL_CTRL_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_DPLL_CTRL_OFFSET ,0x00000001U ,0x00000000U); - /*############################################################################################################################ */ - - // : CHECK PLL STATUS - /*Register : PLL_STATUS @ 0XFD1A0044

- - DPLL is locked - PSU_CRF_APB_PLL_STATUS_DPLL_LOCK 1 - (OFFSET, MASK, VALUE) (0XFD1A0044, 0x00000002U ,0x00000002U) */ - mask_poll(CRF_APB_PLL_STATUS_OFFSET,0x00000002U); - - /*############################################################################################################################ */ - - // : REMOVE PLL BY PASS - /*Register : DPLL_CTRL @ 0XFD1A002C

- - Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.) - PSU_CRF_APB_DPLL_CTRL_BYPASS 0 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFD1A002C, 0x00000008U ,0x00000000U) - RegMask = (CRF_APB_DPLL_CTRL_BYPASS_MASK | 0 ); - - RegVal = ((0x00000000U << CRF_APB_DPLL_CTRL_BYPASS_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_DPLL_CTRL_OFFSET ,0x00000008U ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : DPLL_TO_LPD_CTRL @ 0XFD1A004C

- - Divisor value for this clock. - PSU_CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0 0x3 - - Control for a clock that will be generated in the FPD, but used in the LPD as a clock source for the peripheral clock muxes. - (OFFSET, MASK, VALUE) (0XFD1A004C, 0x00003F00U ,0x00000300U) - RegMask = (CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_MASK | 0 ); - - RegVal = ((0x00000003U << CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_DPLL_TO_LPD_CTRL_OFFSET ,0x00003F00U ,0x00000300U); - /*############################################################################################################################ */ - - // : DPLL FRAC CFG - /*Register : DPLL_FRAC_CFG @ 0XFD1A0034

- - Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona - mode and uses DATA of this register for the fractional portion of the feedback divider. - PSU_CRF_APB_DPLL_FRAC_CFG_ENABLED 0x0 - - Fractional value for the Feedback value. - PSU_CRF_APB_DPLL_FRAC_CFG_DATA 0x0 - - Fractional control for the PLL - (OFFSET, MASK, VALUE) (0XFD1A0034, 0x8000FFFFU ,0x00000000U) - RegMask = (CRF_APB_DPLL_FRAC_CFG_ENABLED_MASK | CRF_APB_DPLL_FRAC_CFG_DATA_MASK | 0 ); - - RegVal = ((0x00000000U << CRF_APB_DPLL_FRAC_CFG_ENABLED_SHIFT - | 0x00000000U << CRF_APB_DPLL_FRAC_CFG_DATA_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_DPLL_FRAC_CFG_OFFSET ,0x8000FFFFU ,0x00000000U); - /*############################################################################################################################ */ - - // : VIDEO_PLL INIT - /*Register : VPLL_CFG @ 0XFD1A003C

- - PLL loop filter resistor control - PSU_CRF_APB_VPLL_CFG_RES 0x2 - - PLL charge pump control - PSU_CRF_APB_VPLL_CFG_CP 0x3 - - PLL loop filter high frequency capacitor control - PSU_CRF_APB_VPLL_CFG_LFHF 0x3 - - Lock circuit counter setting - PSU_CRF_APB_VPLL_CFG_LOCK_CNT 0x28a - - Lock circuit configuration settings for lock windowsize - PSU_CRF_APB_VPLL_CFG_LOCK_DLY 0x3f - - Helper data. Values are to be looked up in a table from Data Sheet - (OFFSET, MASK, VALUE) (0XFD1A003C, 0xFE7FEDEFU ,0x7E514C62U) - RegMask = (CRF_APB_VPLL_CFG_RES_MASK | CRF_APB_VPLL_CFG_CP_MASK | CRF_APB_VPLL_CFG_LFHF_MASK | CRF_APB_VPLL_CFG_LOCK_CNT_MASK | CRF_APB_VPLL_CFG_LOCK_DLY_MASK | 0 ); - - RegVal = ((0x00000002U << CRF_APB_VPLL_CFG_RES_SHIFT - | 0x00000003U << CRF_APB_VPLL_CFG_CP_SHIFT - | 0x00000003U << CRF_APB_VPLL_CFG_LFHF_SHIFT - | 0x0000028AU << CRF_APB_VPLL_CFG_LOCK_CNT_SHIFT - | 0x0000003FU << CRF_APB_VPLL_CFG_LOCK_DLY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_VPLL_CFG_OFFSET ,0xFE7FEDEFU ,0x7E514C62U); - /*############################################################################################################################ */ - - // : UPDATE FB_DIV - /*Register : VPLL_CTRL @ 0XFD1A0038

- - Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_ - ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source - PSU_CRF_APB_VPLL_CTRL_PRE_SRC 0x0 - - The integer portion of the feedback divider to the PLL - PSU_CRF_APB_VPLL_CTRL_FBDIV 0x39 - - This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency - PSU_CRF_APB_VPLL_CTRL_DIV2 0x1 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFD1A0038, 0x00717F00U ,0x00013900U) - RegMask = (CRF_APB_VPLL_CTRL_PRE_SRC_MASK | CRF_APB_VPLL_CTRL_FBDIV_MASK | CRF_APB_VPLL_CTRL_DIV2_MASK | 0 ); - - RegVal = ((0x00000000U << CRF_APB_VPLL_CTRL_PRE_SRC_SHIFT - | 0x00000039U << CRF_APB_VPLL_CTRL_FBDIV_SHIFT - | 0x00000001U << CRF_APB_VPLL_CTRL_DIV2_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_VPLL_CTRL_OFFSET ,0x00717F00U ,0x00013900U); - /*############################################################################################################################ */ - - // : BY PASS PLL - /*Register : VPLL_CTRL @ 0XFD1A0038

- - Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.) - PSU_CRF_APB_VPLL_CTRL_BYPASS 1 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFD1A0038, 0x00000008U ,0x00000008U) - RegMask = (CRF_APB_VPLL_CTRL_BYPASS_MASK | 0 ); - - RegVal = ((0x00000001U << CRF_APB_VPLL_CTRL_BYPASS_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_VPLL_CTRL_OFFSET ,0x00000008U ,0x00000008U); - /*############################################################################################################################ */ - - // : ASSERT RESET - /*Register : VPLL_CTRL @ 0XFD1A0038

- - Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS. - PSU_CRF_APB_VPLL_CTRL_RESET 1 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFD1A0038, 0x00000001U ,0x00000001U) - RegMask = (CRF_APB_VPLL_CTRL_RESET_MASK | 0 ); - - RegVal = ((0x00000001U << CRF_APB_VPLL_CTRL_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_VPLL_CTRL_OFFSET ,0x00000001U ,0x00000001U); - /*############################################################################################################################ */ - - // : DEASSERT RESET - /*Register : VPLL_CTRL @ 0XFD1A0038

- - Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS. - PSU_CRF_APB_VPLL_CTRL_RESET 0 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFD1A0038, 0x00000001U ,0x00000000U) - RegMask = (CRF_APB_VPLL_CTRL_RESET_MASK | 0 ); - - RegVal = ((0x00000000U << CRF_APB_VPLL_CTRL_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_VPLL_CTRL_OFFSET ,0x00000001U ,0x00000000U); - /*############################################################################################################################ */ - - // : CHECK PLL STATUS - /*Register : PLL_STATUS @ 0XFD1A0044

- - VPLL is locked - PSU_CRF_APB_PLL_STATUS_VPLL_LOCK 1 - (OFFSET, MASK, VALUE) (0XFD1A0044, 0x00000004U ,0x00000004U) */ - mask_poll(CRF_APB_PLL_STATUS_OFFSET,0x00000004U); - - /*############################################################################################################################ */ - - // : REMOVE PLL BY PASS - /*Register : VPLL_CTRL @ 0XFD1A0038

- - Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.) - PSU_CRF_APB_VPLL_CTRL_BYPASS 0 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFD1A0038, 0x00000008U ,0x00000000U) - RegMask = (CRF_APB_VPLL_CTRL_BYPASS_MASK | 0 ); - - RegVal = ((0x00000000U << CRF_APB_VPLL_CTRL_BYPASS_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_VPLL_CTRL_OFFSET ,0x00000008U ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : VPLL_TO_LPD_CTRL @ 0XFD1A0050

- - Divisor value for this clock. - PSU_CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0 0x3 - - Control for a clock that will be generated in the FPD, but used in the LPD as a clock source for the peripheral clock muxes. - (OFFSET, MASK, VALUE) (0XFD1A0050, 0x00003F00U ,0x00000300U) - RegMask = (CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_MASK | 0 ); - - RegVal = ((0x00000003U << CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_VPLL_TO_LPD_CTRL_OFFSET ,0x00003F00U ,0x00000300U); - /*############################################################################################################################ */ - - // : VIDEO FRAC CFG - /*Register : VPLL_FRAC_CFG @ 0XFD1A0040

- - Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona - mode and uses DATA of this register for the fractional portion of the feedback divider. - PSU_CRF_APB_VPLL_FRAC_CFG_ENABLED 0x1 - - Fractional value for the Feedback value. - PSU_CRF_APB_VPLL_FRAC_CFG_DATA 0x820c - - Fractional control for the PLL - (OFFSET, MASK, VALUE) (0XFD1A0040, 0x8000FFFFU ,0x8000820CU) - RegMask = (CRF_APB_VPLL_FRAC_CFG_ENABLED_MASK | CRF_APB_VPLL_FRAC_CFG_DATA_MASK | 0 ); - - RegVal = ((0x00000001U << CRF_APB_VPLL_FRAC_CFG_ENABLED_SHIFT - | 0x0000820CU << CRF_APB_VPLL_FRAC_CFG_DATA_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_VPLL_FRAC_CFG_OFFSET ,0x8000FFFFU ,0x8000820CU); - /*############################################################################################################################ */ - - - return 1; + Xil_Out32(addr, rdata); + } + +unsigned long psu_pll_init_data(void) +{ + /* + * RPLL INIT + */ + /* + * Register : RPLL_CFG @ 0XFF5E0034 + + * PLL loop filter resistor control + * PSU_CRL_APB_RPLL_CFG_RES 0xc + + * PLL charge pump control + * PSU_CRL_APB_RPLL_CFG_CP 0x3 + + * PLL loop filter high frequency capacitor control + * PSU_CRL_APB_RPLL_CFG_LFHF 0x3 + + * Lock circuit counter setting + * PSU_CRL_APB_RPLL_CFG_LOCK_CNT 0x339 + + * Lock circuit configuration settings for lock windowsize + * PSU_CRL_APB_RPLL_CFG_LOCK_DLY 0x3f + + * Helper data. Values are to be looked up in a table from Data Sheet + * (OFFSET, MASK, VALUE) (0XFF5E0034, 0xFE7FEDEFU ,0x7E672C6CU) + */ + PSU_Mask_Write(CRL_APB_RPLL_CFG_OFFSET, 0xFE7FEDEFU, 0x7E672C6CU); +/*##################################################################### */ + + /* + * UPDATE FB_DIV + */ + /* + * Register : RPLL_CTRL @ 0XFF5E0030 + + * Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i + * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour + * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source + * PSU_CRL_APB_RPLL_CTRL_PRE_SRC 0x0 + + * The integer portion of the feedback divider to the PLL + * PSU_CRL_APB_RPLL_CTRL_FBDIV 0x2d + + * This turns on the divide by 2 that is inside of the PLL. This does not c + * hange the VCO frequency, just the output frequency + * PSU_CRL_APB_RPLL_CTRL_DIV2 0x1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFF5E0030, 0x00717F00U ,0x00012D00U) + */ + PSU_Mask_Write(CRL_APB_RPLL_CTRL_OFFSET, 0x00717F00U, 0x00012D00U); +/*##################################################################### */ + + /* + * BY PASS PLL + */ + /* + * Register : RPLL_CTRL @ 0XFF5E0030 + + * Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) + * PSU_CRL_APB_RPLL_CTRL_BYPASS 1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFF5E0030, 0x00000008U ,0x00000008U) + */ + PSU_Mask_Write(CRL_APB_RPLL_CTRL_OFFSET, 0x00000008U, 0x00000008U); +/*##################################################################### */ + + /* + * ASSERT RESET + */ + /* + * Register : RPLL_CTRL @ 0XFF5E0030 + + * Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. + * PSU_CRL_APB_RPLL_CTRL_RESET 1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFF5E0030, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(CRL_APB_RPLL_CTRL_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * DEASSERT RESET + */ + /* + * Register : RPLL_CTRL @ 0XFF5E0030 + + * Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. + * PSU_CRL_APB_RPLL_CTRL_RESET 0 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFF5E0030, 0x00000001U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RPLL_CTRL_OFFSET, 0x00000001U, 0x00000000U); +/*##################################################################### */ + + /* + * CHECK PLL STATUS + */ + /* + * Register : PLL_STATUS @ 0XFF5E0040 + + * RPLL is locked + * PSU_CRL_APB_PLL_STATUS_RPLL_LOCK 1 + * (OFFSET, MASK, VALUE) (0XFF5E0040, 0x00000002U ,0x00000002U) + */ + mask_poll(CRL_APB_PLL_STATUS_OFFSET, 0x00000002U); + +/*##################################################################### */ + + /* + * REMOVE PLL BY PASS + */ + /* + * Register : RPLL_CTRL @ 0XFF5E0030 + + * Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) + * PSU_CRL_APB_RPLL_CTRL_BYPASS 0 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFF5E0030, 0x00000008U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RPLL_CTRL_OFFSET, 0x00000008U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : RPLL_TO_FPD_CTRL @ 0XFF5E0048 + + * Divisor value for this clock. + * PSU_CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0 0x2 + + * Control for a clock that will be generated in the LPD, but used in the F + * PD as a clock source for the peripheral clock muxes. + * (OFFSET, MASK, VALUE) (0XFF5E0048, 0x00003F00U ,0x00000200U) + */ + PSU_Mask_Write(CRL_APB_RPLL_TO_FPD_CTRL_OFFSET, + 0x00003F00U, 0x00000200U); +/*##################################################################### */ + + /* + * RPLL FRAC CFG + */ + /* + * IOPLL INIT + */ + /* + * Register : IOPLL_CFG @ 0XFF5E0024 + + * PLL loop filter resistor control + * PSU_CRL_APB_IOPLL_CFG_RES 0x2 + + * PLL charge pump control + * PSU_CRL_APB_IOPLL_CFG_CP 0x4 + + * PLL loop filter high frequency capacitor control + * PSU_CRL_APB_IOPLL_CFG_LFHF 0x3 + + * Lock circuit counter setting + * PSU_CRL_APB_IOPLL_CFG_LOCK_CNT 0x258 + + * Lock circuit configuration settings for lock windowsize + * PSU_CRL_APB_IOPLL_CFG_LOCK_DLY 0x3f + + * Helper data. Values are to be looked up in a table from Data Sheet + * (OFFSET, MASK, VALUE) (0XFF5E0024, 0xFE7FEDEFU ,0x7E4B0C82U) + */ + PSU_Mask_Write(CRL_APB_IOPLL_CFG_OFFSET, 0xFE7FEDEFU, 0x7E4B0C82U); +/*##################################################################### */ + + /* + * UPDATE FB_DIV + */ + /* + * Register : IOPLL_CTRL @ 0XFF5E0020 + + * Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i + * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour + * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source + * PSU_CRL_APB_IOPLL_CTRL_PRE_SRC 0x0 + + * The integer portion of the feedback divider to the PLL + * PSU_CRL_APB_IOPLL_CTRL_FBDIV 0x5a + + * This turns on the divide by 2 that is inside of the PLL. This does not c + * hange the VCO frequency, just the output frequency + * PSU_CRL_APB_IOPLL_CTRL_DIV2 0x1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFF5E0020, 0x00717F00U ,0x00015A00U) + */ + PSU_Mask_Write(CRL_APB_IOPLL_CTRL_OFFSET, 0x00717F00U, 0x00015A00U); +/*##################################################################### */ + + /* + * BY PASS PLL + */ + /* + * Register : IOPLL_CTRL @ 0XFF5E0020 + + * Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) + * PSU_CRL_APB_IOPLL_CTRL_BYPASS 1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFF5E0020, 0x00000008U ,0x00000008U) + */ + PSU_Mask_Write(CRL_APB_IOPLL_CTRL_OFFSET, 0x00000008U, 0x00000008U); +/*##################################################################### */ + + /* + * ASSERT RESET + */ + /* + * Register : IOPLL_CTRL @ 0XFF5E0020 + + * Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. + * PSU_CRL_APB_IOPLL_CTRL_RESET 1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFF5E0020, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(CRL_APB_IOPLL_CTRL_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * DEASSERT RESET + */ + /* + * Register : IOPLL_CTRL @ 0XFF5E0020 + + * Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. + * PSU_CRL_APB_IOPLL_CTRL_RESET 0 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFF5E0020, 0x00000001U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_IOPLL_CTRL_OFFSET, 0x00000001U, 0x00000000U); +/*##################################################################### */ + + /* + * CHECK PLL STATUS + */ + /* + * Register : PLL_STATUS @ 0XFF5E0040 + + * IOPLL is locked + * PSU_CRL_APB_PLL_STATUS_IOPLL_LOCK 1 + * (OFFSET, MASK, VALUE) (0XFF5E0040, 0x00000001U ,0x00000001U) + */ + mask_poll(CRL_APB_PLL_STATUS_OFFSET, 0x00000001U); + +/*##################################################################### */ + + /* + * REMOVE PLL BY PASS + */ + /* + * Register : IOPLL_CTRL @ 0XFF5E0020 + + * Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) + * PSU_CRL_APB_IOPLL_CTRL_BYPASS 0 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFF5E0020, 0x00000008U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_IOPLL_CTRL_OFFSET, 0x00000008U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : IOPLL_TO_FPD_CTRL @ 0XFF5E0044 + + * Divisor value for this clock. + * PSU_CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0 0x3 + + * Control for a clock that will be generated in the LPD, but used in the F + * PD as a clock source for the peripheral clock muxes. + * (OFFSET, MASK, VALUE) (0XFF5E0044, 0x00003F00U ,0x00000300U) + */ + PSU_Mask_Write(CRL_APB_IOPLL_TO_FPD_CTRL_OFFSET, + 0x00003F00U, 0x00000300U); +/*##################################################################### */ + + /* + * IOPLL FRAC CFG + */ + /* + * APU_PLL INIT + */ + /* + * Register : APLL_CFG @ 0XFD1A0024 + + * PLL loop filter resistor control + * PSU_CRF_APB_APLL_CFG_RES 0x2 + + * PLL charge pump control + * PSU_CRF_APB_APLL_CFG_CP 0x3 + + * PLL loop filter high frequency capacitor control + * PSU_CRF_APB_APLL_CFG_LFHF 0x3 + + * Lock circuit counter setting + * PSU_CRF_APB_APLL_CFG_LOCK_CNT 0x258 + + * Lock circuit configuration settings for lock windowsize + * PSU_CRF_APB_APLL_CFG_LOCK_DLY 0x3f + + * Helper data. Values are to be looked up in a table from Data Sheet + * (OFFSET, MASK, VALUE) (0XFD1A0024, 0xFE7FEDEFU ,0x7E4B0C62U) + */ + PSU_Mask_Write(CRF_APB_APLL_CFG_OFFSET, 0xFE7FEDEFU, 0x7E4B0C62U); +/*##################################################################### */ + + /* + * UPDATE FB_DIV + */ + /* + * Register : APLL_CTRL @ 0XFD1A0020 + + * Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i + * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour + * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source + * PSU_CRF_APB_APLL_CTRL_PRE_SRC 0x0 + + * The integer portion of the feedback divider to the PLL + * PSU_CRF_APB_APLL_CTRL_FBDIV 0x48 + + * This turns on the divide by 2 that is inside of the PLL. This does not c + * hange the VCO frequency, just the output frequency + * PSU_CRF_APB_APLL_CTRL_DIV2 0x1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A0020, 0x00717F00U ,0x00014800U) + */ + PSU_Mask_Write(CRF_APB_APLL_CTRL_OFFSET, 0x00717F00U, 0x00014800U); +/*##################################################################### */ + + /* + * BY PASS PLL + */ + /* + * Register : APLL_CTRL @ 0XFD1A0020 + + * Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) + * PSU_CRF_APB_APLL_CTRL_BYPASS 1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A0020, 0x00000008U ,0x00000008U) + */ + PSU_Mask_Write(CRF_APB_APLL_CTRL_OFFSET, 0x00000008U, 0x00000008U); +/*##################################################################### */ + + /* + * ASSERT RESET + */ + /* + * Register : APLL_CTRL @ 0XFD1A0020 + + * Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. + * PSU_CRF_APB_APLL_CTRL_RESET 1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A0020, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(CRF_APB_APLL_CTRL_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * DEASSERT RESET + */ + /* + * Register : APLL_CTRL @ 0XFD1A0020 + + * Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. + * PSU_CRF_APB_APLL_CTRL_RESET 0 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A0020, 0x00000001U ,0x00000000U) + */ + PSU_Mask_Write(CRF_APB_APLL_CTRL_OFFSET, 0x00000001U, 0x00000000U); +/*##################################################################### */ + + /* + * CHECK PLL STATUS + */ + /* + * Register : PLL_STATUS @ 0XFD1A0044 + + * APLL is locked + * PSU_CRF_APB_PLL_STATUS_APLL_LOCK 1 + * (OFFSET, MASK, VALUE) (0XFD1A0044, 0x00000001U ,0x00000001U) + */ + mask_poll(CRF_APB_PLL_STATUS_OFFSET, 0x00000001U); + +/*##################################################################### */ + + /* + * REMOVE PLL BY PASS + */ + /* + * Register : APLL_CTRL @ 0XFD1A0020 + + * Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) + * PSU_CRF_APB_APLL_CTRL_BYPASS 0 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A0020, 0x00000008U ,0x00000000U) + */ + PSU_Mask_Write(CRF_APB_APLL_CTRL_OFFSET, 0x00000008U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : APLL_TO_LPD_CTRL @ 0XFD1A0048 + + * Divisor value for this clock. + * PSU_CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0 0x3 + + * Control for a clock that will be generated in the FPD, but used in the L + * PD as a clock source for the peripheral clock muxes. + * (OFFSET, MASK, VALUE) (0XFD1A0048, 0x00003F00U ,0x00000300U) + */ + PSU_Mask_Write(CRF_APB_APLL_TO_LPD_CTRL_OFFSET, + 0x00003F00U, 0x00000300U); +/*##################################################################### */ + + /* + * APLL FRAC CFG + */ + /* + * DDR_PLL INIT + */ + /* + * Register : DPLL_CFG @ 0XFD1A0030 + + * PLL loop filter resistor control + * PSU_CRF_APB_DPLL_CFG_RES 0x2 + + * PLL charge pump control + * PSU_CRF_APB_DPLL_CFG_CP 0x3 + + * PLL loop filter high frequency capacitor control + * PSU_CRF_APB_DPLL_CFG_LFHF 0x3 + + * Lock circuit counter setting + * PSU_CRF_APB_DPLL_CFG_LOCK_CNT 0x258 + + * Lock circuit configuration settings for lock windowsize + * PSU_CRF_APB_DPLL_CFG_LOCK_DLY 0x3f + + * Helper data. Values are to be looked up in a table from Data Sheet + * (OFFSET, MASK, VALUE) (0XFD1A0030, 0xFE7FEDEFU ,0x7E4B0C62U) + */ + PSU_Mask_Write(CRF_APB_DPLL_CFG_OFFSET, 0xFE7FEDEFU, 0x7E4B0C62U); +/*##################################################################### */ + + /* + * UPDATE FB_DIV + */ + /* + * Register : DPLL_CTRL @ 0XFD1A002C + + * Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i + * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour + * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source + * PSU_CRF_APB_DPLL_CTRL_PRE_SRC 0x0 + + * The integer portion of the feedback divider to the PLL + * PSU_CRF_APB_DPLL_CTRL_FBDIV 0x40 + + * This turns on the divide by 2 that is inside of the PLL. This does not c + * hange the VCO frequency, just the output frequency + * PSU_CRF_APB_DPLL_CTRL_DIV2 0x1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A002C, 0x00717F00U ,0x00014000U) + */ + PSU_Mask_Write(CRF_APB_DPLL_CTRL_OFFSET, 0x00717F00U, 0x00014000U); +/*##################################################################### */ + + /* + * BY PASS PLL + */ + /* + * Register : DPLL_CTRL @ 0XFD1A002C + + * Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) + * PSU_CRF_APB_DPLL_CTRL_BYPASS 1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A002C, 0x00000008U ,0x00000008U) + */ + PSU_Mask_Write(CRF_APB_DPLL_CTRL_OFFSET, 0x00000008U, 0x00000008U); +/*##################################################################### */ + + /* + * ASSERT RESET + */ + /* + * Register : DPLL_CTRL @ 0XFD1A002C + + * Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. + * PSU_CRF_APB_DPLL_CTRL_RESET 1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A002C, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(CRF_APB_DPLL_CTRL_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * DEASSERT RESET + */ + /* + * Register : DPLL_CTRL @ 0XFD1A002C + + * Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. + * PSU_CRF_APB_DPLL_CTRL_RESET 0 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A002C, 0x00000001U ,0x00000000U) + */ + PSU_Mask_Write(CRF_APB_DPLL_CTRL_OFFSET, 0x00000001U, 0x00000000U); +/*##################################################################### */ + + /* + * CHECK PLL STATUS + */ + /* + * Register : PLL_STATUS @ 0XFD1A0044 + + * DPLL is locked + * PSU_CRF_APB_PLL_STATUS_DPLL_LOCK 1 + * (OFFSET, MASK, VALUE) (0XFD1A0044, 0x00000002U ,0x00000002U) + */ + mask_poll(CRF_APB_PLL_STATUS_OFFSET, 0x00000002U); + +/*##################################################################### */ + + /* + * REMOVE PLL BY PASS + */ + /* + * Register : DPLL_CTRL @ 0XFD1A002C + + * Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) + * PSU_CRF_APB_DPLL_CTRL_BYPASS 0 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A002C, 0x00000008U ,0x00000000U) + */ + PSU_Mask_Write(CRF_APB_DPLL_CTRL_OFFSET, 0x00000008U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : DPLL_TO_LPD_CTRL @ 0XFD1A004C + + * Divisor value for this clock. + * PSU_CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0 0x2 + + * Control for a clock that will be generated in the FPD, but used in the L + * PD as a clock source for the peripheral clock muxes. + * (OFFSET, MASK, VALUE) (0XFD1A004C, 0x00003F00U ,0x00000200U) + */ + PSU_Mask_Write(CRF_APB_DPLL_TO_LPD_CTRL_OFFSET, + 0x00003F00U, 0x00000200U); +/*##################################################################### */ + + /* + * DPLL FRAC CFG + */ + /* + * VIDEO_PLL INIT + */ + /* + * Register : VPLL_CFG @ 0XFD1A003C + + * PLL loop filter resistor control + * PSU_CRF_APB_VPLL_CFG_RES 0x2 + + * PLL charge pump control + * PSU_CRF_APB_VPLL_CFG_CP 0x4 + + * PLL loop filter high frequency capacitor control + * PSU_CRF_APB_VPLL_CFG_LFHF 0x3 + + * Lock circuit counter setting + * PSU_CRF_APB_VPLL_CFG_LOCK_CNT 0x258 + + * Lock circuit configuration settings for lock windowsize + * PSU_CRF_APB_VPLL_CFG_LOCK_DLY 0x3f + + * Helper data. Values are to be looked up in a table from Data Sheet + * (OFFSET, MASK, VALUE) (0XFD1A003C, 0xFE7FEDEFU ,0x7E4B0C82U) + */ + PSU_Mask_Write(CRF_APB_VPLL_CFG_OFFSET, 0xFE7FEDEFU, 0x7E4B0C82U); +/*##################################################################### */ + + /* + * UPDATE FB_DIV + */ + /* + * Register : VPLL_CTRL @ 0XFD1A0038 + + * Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i + * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour + * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source + * PSU_CRF_APB_VPLL_CTRL_PRE_SRC 0x0 + + * The integer portion of the feedback divider to the PLL + * PSU_CRF_APB_VPLL_CTRL_FBDIV 0x5a + + * This turns on the divide by 2 that is inside of the PLL. This does not c + * hange the VCO frequency, just the output frequency + * PSU_CRF_APB_VPLL_CTRL_DIV2 0x1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A0038, 0x00717F00U ,0x00015A00U) + */ + PSU_Mask_Write(CRF_APB_VPLL_CTRL_OFFSET, 0x00717F00U, 0x00015A00U); +/*##################################################################### */ + + /* + * BY PASS PLL + */ + /* + * Register : VPLL_CTRL @ 0XFD1A0038 + + * Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) + * PSU_CRF_APB_VPLL_CTRL_BYPASS 1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A0038, 0x00000008U ,0x00000008U) + */ + PSU_Mask_Write(CRF_APB_VPLL_CTRL_OFFSET, 0x00000008U, 0x00000008U); +/*##################################################################### */ + + /* + * ASSERT RESET + */ + /* + * Register : VPLL_CTRL @ 0XFD1A0038 + + * Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. + * PSU_CRF_APB_VPLL_CTRL_RESET 1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A0038, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(CRF_APB_VPLL_CTRL_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * DEASSERT RESET + */ + /* + * Register : VPLL_CTRL @ 0XFD1A0038 + + * Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. + * PSU_CRF_APB_VPLL_CTRL_RESET 0 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A0038, 0x00000001U ,0x00000000U) + */ + PSU_Mask_Write(CRF_APB_VPLL_CTRL_OFFSET, 0x00000001U, 0x00000000U); +/*##################################################################### */ + + /* + * CHECK PLL STATUS + */ + /* + * Register : PLL_STATUS @ 0XFD1A0044 + + * VPLL is locked + * PSU_CRF_APB_PLL_STATUS_VPLL_LOCK 1 + * (OFFSET, MASK, VALUE) (0XFD1A0044, 0x00000004U ,0x00000004U) + */ + mask_poll(CRF_APB_PLL_STATUS_OFFSET, 0x00000004U); + +/*##################################################################### */ + + /* + * REMOVE PLL BY PASS + */ + /* + * Register : VPLL_CTRL @ 0XFD1A0038 + + * Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) + * PSU_CRF_APB_VPLL_CTRL_BYPASS 0 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A0038, 0x00000008U ,0x00000000U) + */ + PSU_Mask_Write(CRF_APB_VPLL_CTRL_OFFSET, 0x00000008U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : VPLL_TO_LPD_CTRL @ 0XFD1A0050 + + * Divisor value for this clock. + * PSU_CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0 0x3 + + * Control for a clock that will be generated in the FPD, but used in the L + * PD as a clock source for the peripheral clock muxes. + * (OFFSET, MASK, VALUE) (0XFD1A0050, 0x00003F00U ,0x00000300U) + */ + PSU_Mask_Write(CRF_APB_VPLL_TO_LPD_CTRL_OFFSET, + 0x00003F00U, 0x00000300U); +/*##################################################################### */ + + /* + * VIDEO FRAC CFG + */ + + return 1; } -unsigned long psu_clock_init_data() { - // : CLOCK CONTROL SLCR REGISTER - /*Register : GEM3_REF_CTRL @ 0XFF5E005C

+unsigned long psu_clock_init_data(void) +{ + /* + * CLOCK CONTROL SLCR REGISTER + */ + /* + * Register : GEM3_REF_CTRL @ 0XFF5E005C + + * Clock active for the RX channel + * PSU_CRL_APB_GEM3_REF_CTRL_RX_CLKACT 0x1 - Clock active for the RX channel - PSU_CRL_APB_GEM3_REF_CTRL_RX_CLKACT 0x1 + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_GEM3_REF_CTRL_CLKACT 0x1 - Clock active signal. Switch to 0 to disable the clock - PSU_CRL_APB_GEM3_REF_CTRL_CLKACT 0x1 + * 6 bit divider + * PSU_CRL_APB_GEM3_REF_CTRL_DIVISOR1 0x1 - 6 bit divider - PSU_CRL_APB_GEM3_REF_CTRL_DIVISOR1 0x1 + * 6 bit divider + * PSU_CRL_APB_GEM3_REF_CTRL_DIVISOR0 0xc + + * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_GEM3_REF_CTRL_SRCSEL 0x0 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E005C, 0x063F3F07U ,0x06010C00U) + */ + PSU_Mask_Write(CRL_APB_GEM3_REF_CTRL_OFFSET, + 0x063F3F07U, 0x06010C00U); +/*##################################################################### */ + + /* + * Register : GEM_TSU_REF_CTRL @ 0XFF5E0100 - 6 bit divider - PSU_CRL_APB_GEM3_REF_CTRL_DIVISOR0 0xc + * 6 bit divider + * PSU_CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0 0x6 - 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_GEM3_REF_CTRL_SRCSEL 0x0 + * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_GEM_TSU_REF_CTRL_SRCSEL 0x0 - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E005C, 0x063F3F07U ,0x06010C00U) - RegMask = (CRL_APB_GEM3_REF_CTRL_RX_CLKACT_MASK | CRL_APB_GEM3_REF_CTRL_CLKACT_MASK | CRL_APB_GEM3_REF_CTRL_DIVISOR1_MASK | CRL_APB_GEM3_REF_CTRL_DIVISOR0_MASK | CRL_APB_GEM3_REF_CTRL_SRCSEL_MASK | 0 ); + * 6 bit divider + * PSU_CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1 0x1 - RegVal = ((0x00000001U << CRL_APB_GEM3_REF_CTRL_RX_CLKACT_SHIFT - | 0x00000001U << CRL_APB_GEM3_REF_CTRL_CLKACT_SHIFT - | 0x00000001U << CRL_APB_GEM3_REF_CTRL_DIVISOR1_SHIFT - | 0x0000000CU << CRL_APB_GEM3_REF_CTRL_DIVISOR0_SHIFT - | 0x00000000U << CRL_APB_GEM3_REF_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_GEM3_REF_CTRL_OFFSET ,0x063F3F07U ,0x06010C00U); - /*############################################################################################################################ */ + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_GEM_TSU_REF_CTRL_CLKACT 0x1 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E0100, 0x013F3F07U ,0x01010600U) + */ + PSU_Mask_Write(CRL_APB_GEM_TSU_REF_CTRL_OFFSET, + 0x013F3F07U, 0x01010600U); +/*##################################################################### */ + + /* + * Register : USB0_BUS_REF_CTRL @ 0XFF5E0060 - /*Register : USB0_BUS_REF_CTRL @ 0XFF5E0060

+ * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_USB0_BUS_REF_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1 0x1 + + * 6 bit divider + * PSU_CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0 0x6 + + * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_USB0_BUS_REF_CTRL_SRCSEL 0x0 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E0060, 0x023F3F07U ,0x02010600U) + */ + PSU_Mask_Write(CRL_APB_USB0_BUS_REF_CTRL_OFFSET, + 0x023F3F07U, 0x02010600U); +/*##################################################################### */ + + /* + * Register : USB3_DUAL_REF_CTRL @ 0XFF5E004C - Clock active signal. Switch to 0 to disable the clock - PSU_CRL_APB_USB0_BUS_REF_CTRL_CLKACT 0x1 + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_USB3_DUAL_REF_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1 0x3 + + * 6 bit divider + * PSU_CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0 0x19 + + * 000 = IOPLL; 010 = RPLL; 011 = DPLL. (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL 0x0 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E004C, 0x023F3F07U ,0x02031900U) + */ + PSU_Mask_Write(CRL_APB_USB3_DUAL_REF_CTRL_OFFSET, + 0x023F3F07U, 0x02031900U); +/*##################################################################### */ - 6 bit divider - PSU_CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1 0x1 + /* + * Register : QSPI_REF_CTRL @ 0XFF5E0068 - 6 bit divider - PSU_CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0 0x6 + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_QSPI_REF_CTRL_CLKACT 0x1 - 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_USB0_BUS_REF_CTRL_SRCSEL 0x0 + * 6 bit divider + * PSU_CRL_APB_QSPI_REF_CTRL_DIVISOR1 0x1 + + * 6 bit divider + * PSU_CRL_APB_QSPI_REF_CTRL_DIVISOR0 0xc + + * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_QSPI_REF_CTRL_SRCSEL 0x0 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E0068, 0x013F3F07U ,0x01010C00U) + */ + PSU_Mask_Write(CRL_APB_QSPI_REF_CTRL_OFFSET, + 0x013F3F07U, 0x01010C00U); +/*##################################################################### */ - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E0060, 0x023F3F07U ,0x02010600U) - RegMask = (CRL_APB_USB0_BUS_REF_CTRL_CLKACT_MASK | CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_MASK | CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_MASK | CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_MASK | 0 ); + /* + * Register : SDIO1_REF_CTRL @ 0XFF5E0070 - RegVal = ((0x00000001U << CRL_APB_USB0_BUS_REF_CTRL_CLKACT_SHIFT - | 0x00000001U << CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_SHIFT - | 0x00000006U << CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_SHIFT - | 0x00000000U << CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_USB0_BUS_REF_CTRL_OFFSET ,0x023F3F07U ,0x02010600U); - /*############################################################################################################################ */ + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_SDIO1_REF_CTRL_CLKACT 0x1 - /*Register : USB3_DUAL_REF_CTRL @ 0XFF5E004C

+ * 6 bit divider + * PSU_CRL_APB_SDIO1_REF_CTRL_DIVISOR1 0x1 + + * 6 bit divider + * PSU_CRL_APB_SDIO1_REF_CTRL_DIVISOR0 0x8 + + * 000 = IOPLL; 010 = RPLL; 011 = VPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_SDIO1_REF_CTRL_SRCSEL 0x0 - Clock active signal. Switch to 0 to disable the clock - PSU_CRL_APB_USB3_DUAL_REF_CTRL_CLKACT 0x1 + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E0070, 0x013F3F07U ,0x01010800U) + */ + PSU_Mask_Write(CRL_APB_SDIO1_REF_CTRL_OFFSET, + 0x013F3F07U, 0x01010800U); +/*##################################################################### */ - 6 bit divider - PSU_CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1 0xf + /* + * Register : SDIO_CLK_CTRL @ 0XFF18030C - 6 bit divider - PSU_CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0 0x5 + * MIO pad selection for sdio1_rx_clk (feedback clock from the PAD) 0: MIO + * [51] 1: MIO [76] + * PSU_IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL 0 - 000 = IOPLL; 010 = RPLL; 011 = DPLL. (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL 0x0 + * SoC Debug Clock Control + * (OFFSET, MASK, VALUE) (0XFF18030C, 0x00020000U ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_SDIO_CLK_CTRL_OFFSET, + 0x00020000U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : UART0_REF_CTRL @ 0XFF5E0074 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_UART0_REF_CTRL_CLKACT 0x1 - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E004C, 0x023F3F07U ,0x020F0500U) - RegMask = (CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_MASK | CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_MASK | CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_MASK | CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_MASK | 0 ); + * 6 bit divider + * PSU_CRL_APB_UART0_REF_CTRL_DIVISOR1 0x1 - RegVal = ((0x00000001U << CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_SHIFT - | 0x0000000FU << CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_SHIFT - | 0x00000005U << CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_SHIFT - | 0x00000000U << CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_USB3_DUAL_REF_CTRL_OFFSET ,0x023F3F07U ,0x020F0500U); - /*############################################################################################################################ */ + * 6 bit divider + * PSU_CRL_APB_UART0_REF_CTRL_DIVISOR0 0xf - /*Register : QSPI_REF_CTRL @ 0XFF5E0068

+ * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_UART0_REF_CTRL_SRCSEL 0x0 - Clock active signal. Switch to 0 to disable the clock - PSU_CRL_APB_QSPI_REF_CTRL_CLKACT 0x1 + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E0074, 0x013F3F07U ,0x01010F00U) + */ + PSU_Mask_Write(CRL_APB_UART0_REF_CTRL_OFFSET, + 0x013F3F07U, 0x01010F00U); +/*##################################################################### */ + + /* + * Register : UART1_REF_CTRL @ 0XFF5E0078 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_UART1_REF_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_UART1_REF_CTRL_DIVISOR1 0x1 + + * 6 bit divider + * PSU_CRL_APB_UART1_REF_CTRL_DIVISOR0 0xf - 6 bit divider - PSU_CRL_APB_QSPI_REF_CTRL_DIVISOR1 0x1 + * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_UART1_REF_CTRL_SRCSEL 0x0 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E0078, 0x013F3F07U ,0x01010F00U) + */ + PSU_Mask_Write(CRL_APB_UART1_REF_CTRL_OFFSET, + 0x013F3F07U, 0x01010F00U); +/*##################################################################### */ + + /* + * Register : I2C0_REF_CTRL @ 0XFF5E0120 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_I2C0_REF_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_I2C0_REF_CTRL_DIVISOR1 0x1 + + * 6 bit divider + * PSU_CRL_APB_I2C0_REF_CTRL_DIVISOR0 0xf + + * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_I2C0_REF_CTRL_SRCSEL 0x0 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E0120, 0x013F3F07U ,0x01010F00U) + */ + PSU_Mask_Write(CRL_APB_I2C0_REF_CTRL_OFFSET, + 0x013F3F07U, 0x01010F00U); +/*##################################################################### */ + + /* + * Register : I2C1_REF_CTRL @ 0XFF5E0124 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_I2C1_REF_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_I2C1_REF_CTRL_DIVISOR1 0x1 + + * 6 bit divider + * PSU_CRL_APB_I2C1_REF_CTRL_DIVISOR0 0xf + + * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_I2C1_REF_CTRL_SRCSEL 0x0 - 6 bit divider - PSU_CRL_APB_QSPI_REF_CTRL_DIVISOR0 0xc + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E0124, 0x013F3F07U ,0x01010F00U) + */ + PSU_Mask_Write(CRL_APB_I2C1_REF_CTRL_OFFSET, + 0x013F3F07U, 0x01010F00U); +/*##################################################################### */ + + /* + * Register : CAN1_REF_CTRL @ 0XFF5E0088 - 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_QSPI_REF_CTRL_SRCSEL 0x0 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E0068, 0x013F3F07U ,0x01010C00U) - RegMask = (CRL_APB_QSPI_REF_CTRL_CLKACT_MASK | CRL_APB_QSPI_REF_CTRL_DIVISOR1_MASK | CRL_APB_QSPI_REF_CTRL_DIVISOR0_MASK | CRL_APB_QSPI_REF_CTRL_SRCSEL_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_QSPI_REF_CTRL_CLKACT_SHIFT - | 0x00000001U << CRL_APB_QSPI_REF_CTRL_DIVISOR1_SHIFT - | 0x0000000CU << CRL_APB_QSPI_REF_CTRL_DIVISOR0_SHIFT - | 0x00000000U << CRL_APB_QSPI_REF_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_QSPI_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010C00U); - /*############################################################################################################################ */ - - /*Register : SDIO1_REF_CTRL @ 0XFF5E0070

- - Clock active signal. Switch to 0 to disable the clock - PSU_CRL_APB_SDIO1_REF_CTRL_CLKACT 0x1 - - 6 bit divider - PSU_CRL_APB_SDIO1_REF_CTRL_DIVISOR1 0x1 - - 6 bit divider - PSU_CRL_APB_SDIO1_REF_CTRL_DIVISOR0 0x6 - - 000 = IOPLL; 010 = RPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_SDIO1_REF_CTRL_SRCSEL 0x2 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E0070, 0x013F3F07U ,0x01010602U) - RegMask = (CRL_APB_SDIO1_REF_CTRL_CLKACT_MASK | CRL_APB_SDIO1_REF_CTRL_DIVISOR1_MASK | CRL_APB_SDIO1_REF_CTRL_DIVISOR0_MASK | CRL_APB_SDIO1_REF_CTRL_SRCSEL_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_SDIO1_REF_CTRL_CLKACT_SHIFT - | 0x00000001U << CRL_APB_SDIO1_REF_CTRL_DIVISOR1_SHIFT - | 0x00000006U << CRL_APB_SDIO1_REF_CTRL_DIVISOR0_SHIFT - | 0x00000002U << CRL_APB_SDIO1_REF_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_SDIO1_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010602U); - /*############################################################################################################################ */ - - /*Register : SDIO_CLK_CTRL @ 0XFF18030C

- - MIO pad selection for sdio1_rx_clk (feedback clock from the PAD) 0: MIO [51] 1: MIO [76] - PSU_IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL 0 - - SoC Debug Clock Control - (OFFSET, MASK, VALUE) (0XFF18030C, 0x00020000U ,0x00000000U) - RegMask = (IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_SDIO_CLK_CTRL_OFFSET ,0x00020000U ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : UART0_REF_CTRL @ 0XFF5E0074

- - Clock active signal. Switch to 0 to disable the clock - PSU_CRL_APB_UART0_REF_CTRL_CLKACT 0x1 - - 6 bit divider - PSU_CRL_APB_UART0_REF_CTRL_DIVISOR1 0x1 - - 6 bit divider - PSU_CRL_APB_UART0_REF_CTRL_DIVISOR0 0xf - - 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_UART0_REF_CTRL_SRCSEL 0x0 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E0074, 0x013F3F07U ,0x01010F00U) - RegMask = (CRL_APB_UART0_REF_CTRL_CLKACT_MASK | CRL_APB_UART0_REF_CTRL_DIVISOR1_MASK | CRL_APB_UART0_REF_CTRL_DIVISOR0_MASK | CRL_APB_UART0_REF_CTRL_SRCSEL_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_UART0_REF_CTRL_CLKACT_SHIFT - | 0x00000001U << CRL_APB_UART0_REF_CTRL_DIVISOR1_SHIFT - | 0x0000000FU << CRL_APB_UART0_REF_CTRL_DIVISOR0_SHIFT - | 0x00000000U << CRL_APB_UART0_REF_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_UART0_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010F00U); - /*############################################################################################################################ */ - - /*Register : UART1_REF_CTRL @ 0XFF5E0078

- - Clock active signal. Switch to 0 to disable the clock - PSU_CRL_APB_UART1_REF_CTRL_CLKACT 0x1 - - 6 bit divider - PSU_CRL_APB_UART1_REF_CTRL_DIVISOR1 0x1 - - 6 bit divider - PSU_CRL_APB_UART1_REF_CTRL_DIVISOR0 0xf - - 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_UART1_REF_CTRL_SRCSEL 0x0 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E0078, 0x013F3F07U ,0x01010F00U) - RegMask = (CRL_APB_UART1_REF_CTRL_CLKACT_MASK | CRL_APB_UART1_REF_CTRL_DIVISOR1_MASK | CRL_APB_UART1_REF_CTRL_DIVISOR0_MASK | CRL_APB_UART1_REF_CTRL_SRCSEL_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_UART1_REF_CTRL_CLKACT_SHIFT - | 0x00000001U << CRL_APB_UART1_REF_CTRL_DIVISOR1_SHIFT - | 0x0000000FU << CRL_APB_UART1_REF_CTRL_DIVISOR0_SHIFT - | 0x00000000U << CRL_APB_UART1_REF_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_UART1_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010F00U); - /*############################################################################################################################ */ - - /*Register : I2C0_REF_CTRL @ 0XFF5E0120

- - Clock active signal. Switch to 0 to disable the clock - PSU_CRL_APB_I2C0_REF_CTRL_CLKACT 0x1 - - 6 bit divider - PSU_CRL_APB_I2C0_REF_CTRL_DIVISOR1 0x1 - - 6 bit divider - PSU_CRL_APB_I2C0_REF_CTRL_DIVISOR0 0xf - - 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_I2C0_REF_CTRL_SRCSEL 0x0 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E0120, 0x013F3F07U ,0x01010F00U) - RegMask = (CRL_APB_I2C0_REF_CTRL_CLKACT_MASK | CRL_APB_I2C0_REF_CTRL_DIVISOR1_MASK | CRL_APB_I2C0_REF_CTRL_DIVISOR0_MASK | CRL_APB_I2C0_REF_CTRL_SRCSEL_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_I2C0_REF_CTRL_CLKACT_SHIFT - | 0x00000001U << CRL_APB_I2C0_REF_CTRL_DIVISOR1_SHIFT - | 0x0000000FU << CRL_APB_I2C0_REF_CTRL_DIVISOR0_SHIFT - | 0x00000000U << CRL_APB_I2C0_REF_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_I2C0_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010F00U); - /*############################################################################################################################ */ - - /*Register : I2C1_REF_CTRL @ 0XFF5E0124

- - Clock active signal. Switch to 0 to disable the clock - PSU_CRL_APB_I2C1_REF_CTRL_CLKACT 0x1 - - 6 bit divider - PSU_CRL_APB_I2C1_REF_CTRL_DIVISOR1 0x1 - - 6 bit divider - PSU_CRL_APB_I2C1_REF_CTRL_DIVISOR0 0xf - - 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_I2C1_REF_CTRL_SRCSEL 0x0 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E0124, 0x013F3F07U ,0x01010F00U) - RegMask = (CRL_APB_I2C1_REF_CTRL_CLKACT_MASK | CRL_APB_I2C1_REF_CTRL_DIVISOR1_MASK | CRL_APB_I2C1_REF_CTRL_DIVISOR0_MASK | CRL_APB_I2C1_REF_CTRL_SRCSEL_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_I2C1_REF_CTRL_CLKACT_SHIFT - | 0x00000001U << CRL_APB_I2C1_REF_CTRL_DIVISOR1_SHIFT - | 0x0000000FU << CRL_APB_I2C1_REF_CTRL_DIVISOR0_SHIFT - | 0x00000000U << CRL_APB_I2C1_REF_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_I2C1_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010F00U); - /*############################################################################################################################ */ - - /*Register : CAN1_REF_CTRL @ 0XFF5E0088

- - Clock active signal. Switch to 0 to disable the clock - PSU_CRL_APB_CAN1_REF_CTRL_CLKACT 0x1 - - 6 bit divider - PSU_CRL_APB_CAN1_REF_CTRL_DIVISOR1 0x1 - - 6 bit divider - PSU_CRL_APB_CAN1_REF_CTRL_DIVISOR0 0xf - - 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_CAN1_REF_CTRL_SRCSEL 0x0 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E0088, 0x013F3F07U ,0x01010F00U) - RegMask = (CRL_APB_CAN1_REF_CTRL_CLKACT_MASK | CRL_APB_CAN1_REF_CTRL_DIVISOR1_MASK | CRL_APB_CAN1_REF_CTRL_DIVISOR0_MASK | CRL_APB_CAN1_REF_CTRL_SRCSEL_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_CAN1_REF_CTRL_CLKACT_SHIFT - | 0x00000001U << CRL_APB_CAN1_REF_CTRL_DIVISOR1_SHIFT - | 0x0000000FU << CRL_APB_CAN1_REF_CTRL_DIVISOR0_SHIFT - | 0x00000000U << CRL_APB_CAN1_REF_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_CAN1_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010F00U); - /*############################################################################################################################ */ - - /*Register : CPU_R5_CTRL @ 0XFF5E0090

- - Turing this off will shut down the OCM, some parts of the APM, and prevent transactions going from the FPD to the LPD and cou - d lead to system hang - PSU_CRL_APB_CPU_R5_CTRL_CLKACT 0x1 - - 6 bit divider - PSU_CRL_APB_CPU_R5_CTRL_DIVISOR0 0x3 - - 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_CPU_R5_CTRL_SRCSEL 0x2 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E0090, 0x01003F07U ,0x01000302U) - RegMask = (CRL_APB_CPU_R5_CTRL_CLKACT_MASK | CRL_APB_CPU_R5_CTRL_DIVISOR0_MASK | CRL_APB_CPU_R5_CTRL_SRCSEL_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_CPU_R5_CTRL_CLKACT_SHIFT - | 0x00000003U << CRL_APB_CPU_R5_CTRL_DIVISOR0_SHIFT - | 0x00000002U << CRL_APB_CPU_R5_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_CPU_R5_CTRL_OFFSET ,0x01003F07U ,0x01000302U); - /*############################################################################################################################ */ - - /*Register : IOU_SWITCH_CTRL @ 0XFF5E009C

- - Clock active signal. Switch to 0 to disable the clock - PSU_CRL_APB_IOU_SWITCH_CTRL_CLKACT 0x1 - - 6 bit divider - PSU_CRL_APB_IOU_SWITCH_CTRL_DIVISOR0 0x6 - - 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_IOU_SWITCH_CTRL_SRCSEL 0x2 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E009C, 0x01003F07U ,0x01000602U) - RegMask = (CRL_APB_IOU_SWITCH_CTRL_CLKACT_MASK | CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_MASK | CRL_APB_IOU_SWITCH_CTRL_SRCSEL_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_IOU_SWITCH_CTRL_CLKACT_SHIFT - | 0x00000006U << CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_SHIFT - | 0x00000002U << CRL_APB_IOU_SWITCH_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_IOU_SWITCH_CTRL_OFFSET ,0x01003F07U ,0x01000602U); - /*############################################################################################################################ */ - - /*Register : PCAP_CTRL @ 0XFF5E00A4

- - Clock active signal. Switch to 0 to disable the clock - PSU_CRL_APB_PCAP_CTRL_CLKACT 0x1 - - 6 bit divider - PSU_CRL_APB_PCAP_CTRL_DIVISOR0 0x6 - - 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_PCAP_CTRL_SRCSEL 0x2 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E00A4, 0x01003F07U ,0x01000602U) - RegMask = (CRL_APB_PCAP_CTRL_CLKACT_MASK | CRL_APB_PCAP_CTRL_DIVISOR0_MASK | CRL_APB_PCAP_CTRL_SRCSEL_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_PCAP_CTRL_CLKACT_SHIFT - | 0x00000006U << CRL_APB_PCAP_CTRL_DIVISOR0_SHIFT - | 0x00000002U << CRL_APB_PCAP_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_PCAP_CTRL_OFFSET ,0x01003F07U ,0x01000602U); - /*############################################################################################################################ */ - - /*Register : LPD_SWITCH_CTRL @ 0XFF5E00A8

- - Clock active signal. Switch to 0 to disable the clock - PSU_CRL_APB_LPD_SWITCH_CTRL_CLKACT 0x1 - - 6 bit divider - PSU_CRL_APB_LPD_SWITCH_CTRL_DIVISOR0 0x3 - - 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_LPD_SWITCH_CTRL_SRCSEL 0x2 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E00A8, 0x01003F07U ,0x01000302U) - RegMask = (CRL_APB_LPD_SWITCH_CTRL_CLKACT_MASK | CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_MASK | CRL_APB_LPD_SWITCH_CTRL_SRCSEL_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_LPD_SWITCH_CTRL_CLKACT_SHIFT - | 0x00000003U << CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_SHIFT - | 0x00000002U << CRL_APB_LPD_SWITCH_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_LPD_SWITCH_CTRL_OFFSET ,0x01003F07U ,0x01000302U); - /*############################################################################################################################ */ - - /*Register : LPD_LSBUS_CTRL @ 0XFF5E00AC

- - Clock active signal. Switch to 0 to disable the clock - PSU_CRL_APB_LPD_LSBUS_CTRL_CLKACT 0x1 - - 6 bit divider - PSU_CRL_APB_LPD_LSBUS_CTRL_DIVISOR0 0xf - - 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_LPD_LSBUS_CTRL_SRCSEL 0x2 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E00AC, 0x01003F07U ,0x01000F02U) - RegMask = (CRL_APB_LPD_LSBUS_CTRL_CLKACT_MASK | CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_MASK | CRL_APB_LPD_LSBUS_CTRL_SRCSEL_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_LPD_LSBUS_CTRL_CLKACT_SHIFT - | 0x0000000FU << CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_SHIFT - | 0x00000002U << CRL_APB_LPD_LSBUS_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_LPD_LSBUS_CTRL_OFFSET ,0x01003F07U ,0x01000F02U); - /*############################################################################################################################ */ - - /*Register : DBG_LPD_CTRL @ 0XFF5E00B0

- - Clock active signal. Switch to 0 to disable the clock - PSU_CRL_APB_DBG_LPD_CTRL_CLKACT 0x1 - - 6 bit divider - PSU_CRL_APB_DBG_LPD_CTRL_DIVISOR0 0x6 - - 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_DBG_LPD_CTRL_SRCSEL 0x2 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E00B0, 0x01003F07U ,0x01000602U) - RegMask = (CRL_APB_DBG_LPD_CTRL_CLKACT_MASK | CRL_APB_DBG_LPD_CTRL_DIVISOR0_MASK | CRL_APB_DBG_LPD_CTRL_SRCSEL_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_DBG_LPD_CTRL_CLKACT_SHIFT - | 0x00000006U << CRL_APB_DBG_LPD_CTRL_DIVISOR0_SHIFT - | 0x00000002U << CRL_APB_DBG_LPD_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_DBG_LPD_CTRL_OFFSET ,0x01003F07U ,0x01000602U); - /*############################################################################################################################ */ - - /*Register : ADMA_REF_CTRL @ 0XFF5E00B8

- - Clock active signal. Switch to 0 to disable the clock - PSU_CRL_APB_ADMA_REF_CTRL_CLKACT 0x1 - - 6 bit divider - PSU_CRL_APB_ADMA_REF_CTRL_DIVISOR0 0x3 - - 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_ADMA_REF_CTRL_SRCSEL 0x2 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E00B8, 0x01003F07U ,0x01000302U) - RegMask = (CRL_APB_ADMA_REF_CTRL_CLKACT_MASK | CRL_APB_ADMA_REF_CTRL_DIVISOR0_MASK | CRL_APB_ADMA_REF_CTRL_SRCSEL_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_ADMA_REF_CTRL_CLKACT_SHIFT - | 0x00000003U << CRL_APB_ADMA_REF_CTRL_DIVISOR0_SHIFT - | 0x00000002U << CRL_APB_ADMA_REF_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_ADMA_REF_CTRL_OFFSET ,0x01003F07U ,0x01000302U); - /*############################################################################################################################ */ - - /*Register : PL0_REF_CTRL @ 0XFF5E00C0

- - Clock active signal. Switch to 0 to disable the clock - PSU_CRL_APB_PL0_REF_CTRL_CLKACT 0x1 - - 6 bit divider - PSU_CRL_APB_PL0_REF_CTRL_DIVISOR1 0x1 - - 6 bit divider - PSU_CRL_APB_PL0_REF_CTRL_DIVISOR0 0xf - - 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_PL0_REF_CTRL_SRCSEL 0x0 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E00C0, 0x013F3F07U ,0x01010F00U) - RegMask = (CRL_APB_PL0_REF_CTRL_CLKACT_MASK | CRL_APB_PL0_REF_CTRL_DIVISOR1_MASK | CRL_APB_PL0_REF_CTRL_DIVISOR0_MASK | CRL_APB_PL0_REF_CTRL_SRCSEL_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_PL0_REF_CTRL_CLKACT_SHIFT - | 0x00000001U << CRL_APB_PL0_REF_CTRL_DIVISOR1_SHIFT - | 0x0000000FU << CRL_APB_PL0_REF_CTRL_DIVISOR0_SHIFT - | 0x00000000U << CRL_APB_PL0_REF_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_PL0_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010F00U); - /*############################################################################################################################ */ - - /*Register : PL1_REF_CTRL @ 0XFF5E00C4

- - Clock active signal. Switch to 0 to disable the clock - PSU_CRL_APB_PL1_REF_CTRL_CLKACT 0x1 - - 6 bit divider - PSU_CRL_APB_PL1_REF_CTRL_DIVISOR1 0x4 - - 6 bit divider - PSU_CRL_APB_PL1_REF_CTRL_DIVISOR0 0xf - - 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_PL1_REF_CTRL_SRCSEL 0x0 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E00C4, 0x013F3F07U ,0x01040F00U) - RegMask = (CRL_APB_PL1_REF_CTRL_CLKACT_MASK | CRL_APB_PL1_REF_CTRL_DIVISOR1_MASK | CRL_APB_PL1_REF_CTRL_DIVISOR0_MASK | CRL_APB_PL1_REF_CTRL_SRCSEL_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_PL1_REF_CTRL_CLKACT_SHIFT - | 0x00000004U << CRL_APB_PL1_REF_CTRL_DIVISOR1_SHIFT - | 0x0000000FU << CRL_APB_PL1_REF_CTRL_DIVISOR0_SHIFT - | 0x00000000U << CRL_APB_PL1_REF_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_PL1_REF_CTRL_OFFSET ,0x013F3F07U ,0x01040F00U); - /*############################################################################################################################ */ - - /*Register : PL2_REF_CTRL @ 0XFF5E00C8

- - Clock active signal. Switch to 0 to disable the clock - PSU_CRL_APB_PL2_REF_CTRL_CLKACT 0x1 - - 6 bit divider - PSU_CRL_APB_PL2_REF_CTRL_DIVISOR1 0x1 - - 6 bit divider - PSU_CRL_APB_PL2_REF_CTRL_DIVISOR0 0x4 - - 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_PL2_REF_CTRL_SRCSEL 0x2 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E00C8, 0x013F3F07U ,0x01010402U) - RegMask = (CRL_APB_PL2_REF_CTRL_CLKACT_MASK | CRL_APB_PL2_REF_CTRL_DIVISOR1_MASK | CRL_APB_PL2_REF_CTRL_DIVISOR0_MASK | CRL_APB_PL2_REF_CTRL_SRCSEL_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_PL2_REF_CTRL_CLKACT_SHIFT - | 0x00000001U << CRL_APB_PL2_REF_CTRL_DIVISOR1_SHIFT - | 0x00000004U << CRL_APB_PL2_REF_CTRL_DIVISOR0_SHIFT - | 0x00000002U << CRL_APB_PL2_REF_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_PL2_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010402U); - /*############################################################################################################################ */ - - /*Register : PL3_REF_CTRL @ 0XFF5E00CC

- - Clock active signal. Switch to 0 to disable the clock - PSU_CRL_APB_PL3_REF_CTRL_CLKACT 0x1 - - 6 bit divider - PSU_CRL_APB_PL3_REF_CTRL_DIVISOR1 0x1 - - 6 bit divider - PSU_CRL_APB_PL3_REF_CTRL_DIVISOR0 0x3 - - 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_PL3_REF_CTRL_SRCSEL 0x2 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E00CC, 0x013F3F07U ,0x01010302U) - RegMask = (CRL_APB_PL3_REF_CTRL_CLKACT_MASK | CRL_APB_PL3_REF_CTRL_DIVISOR1_MASK | CRL_APB_PL3_REF_CTRL_DIVISOR0_MASK | CRL_APB_PL3_REF_CTRL_SRCSEL_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_PL3_REF_CTRL_CLKACT_SHIFT - | 0x00000001U << CRL_APB_PL3_REF_CTRL_DIVISOR1_SHIFT - | 0x00000003U << CRL_APB_PL3_REF_CTRL_DIVISOR0_SHIFT - | 0x00000002U << CRL_APB_PL3_REF_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_PL3_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010302U); - /*############################################################################################################################ */ - - /*Register : AMS_REF_CTRL @ 0XFF5E0108

- - 6 bit divider - PSU_CRL_APB_AMS_REF_CTRL_DIVISOR1 0x1 - - 6 bit divider - PSU_CRL_APB_AMS_REF_CTRL_DIVISOR0 0x1d - - 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_AMS_REF_CTRL_SRCSEL 0x2 - - Clock active signal. Switch to 0 to disable the clock - PSU_CRL_APB_AMS_REF_CTRL_CLKACT 0x1 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E0108, 0x013F3F07U ,0x01011D02U) - RegMask = (CRL_APB_AMS_REF_CTRL_DIVISOR1_MASK | CRL_APB_AMS_REF_CTRL_DIVISOR0_MASK | CRL_APB_AMS_REF_CTRL_SRCSEL_MASK | CRL_APB_AMS_REF_CTRL_CLKACT_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_AMS_REF_CTRL_DIVISOR1_SHIFT - | 0x0000001DU << CRL_APB_AMS_REF_CTRL_DIVISOR0_SHIFT - | 0x00000002U << CRL_APB_AMS_REF_CTRL_SRCSEL_SHIFT - | 0x00000001U << CRL_APB_AMS_REF_CTRL_CLKACT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_AMS_REF_CTRL_OFFSET ,0x013F3F07U ,0x01011D02U); - /*############################################################################################################################ */ - - /*Register : DLL_REF_CTRL @ 0XFF5E0104

- - 000 = IOPLL; 001 = RPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This - is not usually an issue, but designers must be aware.) - PSU_CRL_APB_DLL_REF_CTRL_SRCSEL 0 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E0104, 0x00000007U ,0x00000000U) - RegMask = (CRL_APB_DLL_REF_CTRL_SRCSEL_MASK | 0 ); - - RegVal = ((0x00000000U << CRL_APB_DLL_REF_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_DLL_REF_CTRL_OFFSET ,0x00000007U ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : TIMESTAMP_REF_CTRL @ 0XFF5E0128

- - 6 bit divider - PSU_CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0 0xf - - 1XX = pss_ref_clk; 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and - cycles of the new clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL 0x0 - - Clock active signal. Switch to 0 to disable the clock - PSU_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT 0x1 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E0128, 0x01003F07U ,0x01000F00U) - RegMask = (CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_MASK | CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_MASK | CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_MASK | 0 ); - - RegVal = ((0x0000000FU << CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_SHIFT - | 0x00000000U << CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_SHIFT - | 0x00000001U << CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_TIMESTAMP_REF_CTRL_OFFSET ,0x01003F07U ,0x01000F00U); - /*############################################################################################################################ */ - - /*Register : SATA_REF_CTRL @ 0XFD1A00A0

- - 000 = IOPLL_TO_FPD; 010 = APLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of - he new clock. This is not usually an issue, but designers must be aware.) - PSU_CRF_APB_SATA_REF_CTRL_SRCSEL 0x0 - - Clock active signal. Switch to 0 to disable the clock - PSU_CRF_APB_SATA_REF_CTRL_CLKACT 0x1 - - 6 bit divider - PSU_CRF_APB_SATA_REF_CTRL_DIVISOR0 0x2 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFD1A00A0, 0x01003F07U ,0x01000200U) - RegMask = (CRF_APB_SATA_REF_CTRL_SRCSEL_MASK | CRF_APB_SATA_REF_CTRL_CLKACT_MASK | CRF_APB_SATA_REF_CTRL_DIVISOR0_MASK | 0 ); - - RegVal = ((0x00000000U << CRF_APB_SATA_REF_CTRL_SRCSEL_SHIFT - | 0x00000001U << CRF_APB_SATA_REF_CTRL_CLKACT_SHIFT - | 0x00000002U << CRF_APB_SATA_REF_CTRL_DIVISOR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_SATA_REF_CTRL_OFFSET ,0x01003F07U ,0x01000200U); - /*############################################################################################################################ */ - - /*Register : PCIE_REF_CTRL @ 0XFD1A00B4

- - 000 = IOPLL_TO_FPD; 010 = RPLL_TO_FPD; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cyc - es of the new clock. This is not usually an issue, but designers must be aware.) - PSU_CRF_APB_PCIE_REF_CTRL_SRCSEL 0x0 - - Clock active signal. Switch to 0 to disable the clock - PSU_CRF_APB_PCIE_REF_CTRL_CLKACT 0x1 - - 6 bit divider - PSU_CRF_APB_PCIE_REF_CTRL_DIVISOR0 0x2 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFD1A00B4, 0x01003F07U ,0x01000200U) - RegMask = (CRF_APB_PCIE_REF_CTRL_SRCSEL_MASK | CRF_APB_PCIE_REF_CTRL_CLKACT_MASK | CRF_APB_PCIE_REF_CTRL_DIVISOR0_MASK | 0 ); - - RegVal = ((0x00000000U << CRF_APB_PCIE_REF_CTRL_SRCSEL_SHIFT - | 0x00000001U << CRF_APB_PCIE_REF_CTRL_CLKACT_SHIFT - | 0x00000002U << CRF_APB_PCIE_REF_CTRL_DIVISOR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_PCIE_REF_CTRL_OFFSET ,0x01003F07U ,0x01000200U); - /*############################################################################################################################ */ - - /*Register : DP_VIDEO_REF_CTRL @ 0XFD1A0070

- - 6 bit divider - PSU_CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1 0x1 - - 6 bit divider - PSU_CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0 0x3 - - 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (This signal may only be toggled after 4 cycles of the - ld clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.) - PSU_CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL 0x3 - - Clock active signal. Switch to 0 to disable the clock - PSU_CRF_APB_DP_VIDEO_REF_CTRL_CLKACT 0x1 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFD1A0070, 0x013F3F07U ,0x01010303U) - RegMask = (CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_MASK | CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_MASK | CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_MASK | CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_MASK | 0 ); - - RegVal = ((0x00000001U << CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_SHIFT - | 0x00000003U << CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_SHIFT - | 0x00000003U << CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_SHIFT - | 0x00000001U << CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_DP_VIDEO_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010303U); - /*############################################################################################################################ */ - - /*Register : DP_AUDIO_REF_CTRL @ 0XFD1A0074

- - 6 bit divider - PSU_CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1 0x1 - - 6 bit divider - PSU_CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0 0x27 - - 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (This signal may only be toggled after 4 cycles of the - ld clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.) - PSU_CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL 0x0 - - Clock active signal. Switch to 0 to disable the clock - PSU_CRF_APB_DP_AUDIO_REF_CTRL_CLKACT 0x1 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFD1A0074, 0x013F3F07U ,0x01012700U) - RegMask = (CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_MASK | CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_MASK | CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_MASK | CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_MASK | 0 ); - - RegVal = ((0x00000001U << CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_SHIFT - | 0x00000027U << CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_SHIFT - | 0x00000000U << CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_SHIFT - | 0x00000001U << CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_DP_AUDIO_REF_CTRL_OFFSET ,0x013F3F07U ,0x01012700U); - /*############################################################################################################################ */ - - /*Register : DP_STC_REF_CTRL @ 0XFD1A007C

- - 6 bit divider - PSU_CRF_APB_DP_STC_REF_CTRL_DIVISOR1 0x1 - - 6 bit divider - PSU_CRF_APB_DP_STC_REF_CTRL_DIVISOR0 0x11 - - 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of t - e new clock. This is not usually an issue, but designers must be aware.) - PSU_CRF_APB_DP_STC_REF_CTRL_SRCSEL 0x3 - - Clock active signal. Switch to 0 to disable the clock - PSU_CRF_APB_DP_STC_REF_CTRL_CLKACT 0x1 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFD1A007C, 0x013F3F07U ,0x01011103U) - RegMask = (CRF_APB_DP_STC_REF_CTRL_DIVISOR1_MASK | CRF_APB_DP_STC_REF_CTRL_DIVISOR0_MASK | CRF_APB_DP_STC_REF_CTRL_SRCSEL_MASK | CRF_APB_DP_STC_REF_CTRL_CLKACT_MASK | 0 ); - - RegVal = ((0x00000001U << CRF_APB_DP_STC_REF_CTRL_DIVISOR1_SHIFT - | 0x00000011U << CRF_APB_DP_STC_REF_CTRL_DIVISOR0_SHIFT - | 0x00000003U << CRF_APB_DP_STC_REF_CTRL_SRCSEL_SHIFT - | 0x00000001U << CRF_APB_DP_STC_REF_CTRL_CLKACT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_DP_STC_REF_CTRL_OFFSET ,0x013F3F07U ,0x01011103U); - /*############################################################################################################################ */ - - /*Register : ACPU_CTRL @ 0XFD1A0060

- - 6 bit divider - PSU_CRF_APB_ACPU_CTRL_DIVISOR0 0x1 - - 000 = APLL; 010 = DPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - lock. This is not usually an issue, but designers must be aware.) - PSU_CRF_APB_ACPU_CTRL_SRCSEL 0x0 - - Clock active signal. Switch to 0 to disable the clock. For the half speed APU Clock - PSU_CRF_APB_ACPU_CTRL_CLKACT_HALF 0x1 - - Clock active signal. Switch to 0 to disable the clock. For the full speed ACPUX Clock. This will shut off the high speed cloc - to the entire APU - PSU_CRF_APB_ACPU_CTRL_CLKACT_FULL 0x1 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFD1A0060, 0x03003F07U ,0x03000100U) - RegMask = (CRF_APB_ACPU_CTRL_DIVISOR0_MASK | CRF_APB_ACPU_CTRL_SRCSEL_MASK | CRF_APB_ACPU_CTRL_CLKACT_HALF_MASK | CRF_APB_ACPU_CTRL_CLKACT_FULL_MASK | 0 ); - - RegVal = ((0x00000001U << CRF_APB_ACPU_CTRL_DIVISOR0_SHIFT - | 0x00000000U << CRF_APB_ACPU_CTRL_SRCSEL_SHIFT - | 0x00000001U << CRF_APB_ACPU_CTRL_CLKACT_HALF_SHIFT - | 0x00000001U << CRF_APB_ACPU_CTRL_CLKACT_FULL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_ACPU_CTRL_OFFSET ,0x03003F07U ,0x03000100U); - /*############################################################################################################################ */ - - /*Register : DBG_TRACE_CTRL @ 0XFD1A0064

- - 6 bit divider - PSU_CRF_APB_DBG_TRACE_CTRL_DIVISOR0 0x2 - - 000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of - he new clock. This is not usually an issue, but designers must be aware.) - PSU_CRF_APB_DBG_TRACE_CTRL_SRCSEL 0x0 - - Clock active signal. Switch to 0 to disable the clock - PSU_CRF_APB_DBG_TRACE_CTRL_CLKACT 0x1 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFD1A0064, 0x01003F07U ,0x01000200U) - RegMask = (CRF_APB_DBG_TRACE_CTRL_DIVISOR0_MASK | CRF_APB_DBG_TRACE_CTRL_SRCSEL_MASK | CRF_APB_DBG_TRACE_CTRL_CLKACT_MASK | 0 ); - - RegVal = ((0x00000002U << CRF_APB_DBG_TRACE_CTRL_DIVISOR0_SHIFT - | 0x00000000U << CRF_APB_DBG_TRACE_CTRL_SRCSEL_SHIFT - | 0x00000001U << CRF_APB_DBG_TRACE_CTRL_CLKACT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_DBG_TRACE_CTRL_OFFSET ,0x01003F07U ,0x01000200U); - /*############################################################################################################################ */ - - /*Register : DBG_FPD_CTRL @ 0XFD1A0068

- - 6 bit divider - PSU_CRF_APB_DBG_FPD_CTRL_DIVISOR0 0x2 - - 000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of - he new clock. This is not usually an issue, but designers must be aware.) - PSU_CRF_APB_DBG_FPD_CTRL_SRCSEL 0x0 - - Clock active signal. Switch to 0 to disable the clock - PSU_CRF_APB_DBG_FPD_CTRL_CLKACT 0x1 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFD1A0068, 0x01003F07U ,0x01000200U) - RegMask = (CRF_APB_DBG_FPD_CTRL_DIVISOR0_MASK | CRF_APB_DBG_FPD_CTRL_SRCSEL_MASK | CRF_APB_DBG_FPD_CTRL_CLKACT_MASK | 0 ); - - RegVal = ((0x00000002U << CRF_APB_DBG_FPD_CTRL_DIVISOR0_SHIFT - | 0x00000000U << CRF_APB_DBG_FPD_CTRL_SRCSEL_SHIFT - | 0x00000001U << CRF_APB_DBG_FPD_CTRL_CLKACT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_DBG_FPD_CTRL_OFFSET ,0x01003F07U ,0x01000200U); - /*############################################################################################################################ */ - - /*Register : DDR_CTRL @ 0XFD1A0080

- - 6 bit divider - PSU_CRF_APB_DDR_CTRL_DIVISOR0 0x2 - - 000 = DPLL; 001 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This - s not usually an issue, but designers must be aware.) - PSU_CRF_APB_DDR_CTRL_SRCSEL 0x0 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFD1A0080, 0x00003F07U ,0x00000200U) - RegMask = (CRF_APB_DDR_CTRL_DIVISOR0_MASK | CRF_APB_DDR_CTRL_SRCSEL_MASK | 0 ); - - RegVal = ((0x00000002U << CRF_APB_DDR_CTRL_DIVISOR0_SHIFT - | 0x00000000U << CRF_APB_DDR_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_DDR_CTRL_OFFSET ,0x00003F07U ,0x00000200U); - /*############################################################################################################################ */ - - /*Register : GPU_REF_CTRL @ 0XFD1A0084

- - 6 bit divider - PSU_CRF_APB_GPU_REF_CTRL_DIVISOR0 0x1 - - 000 = IOPLL_TO_FPD; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of - he new clock. This is not usually an issue, but designers must be aware.) - PSU_CRF_APB_GPU_REF_CTRL_SRCSEL 0x0 - - Clock active signal. Switch to 0 to disable the clock, which will stop clock for GPU (and both Pixel Processors). - PSU_CRF_APB_GPU_REF_CTRL_CLKACT 0x1 - - Clock active signal for Pixel Processor. Switch to 0 to disable the clock only to this Pixel Processor - PSU_CRF_APB_GPU_REF_CTRL_PP0_CLKACT 0x1 - - Clock active signal for Pixel Processor. Switch to 0 to disable the clock only to this Pixel Processor - PSU_CRF_APB_GPU_REF_CTRL_PP1_CLKACT 0x1 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFD1A0084, 0x07003F07U ,0x07000100U) - RegMask = (CRF_APB_GPU_REF_CTRL_DIVISOR0_MASK | CRF_APB_GPU_REF_CTRL_SRCSEL_MASK | CRF_APB_GPU_REF_CTRL_CLKACT_MASK | CRF_APB_GPU_REF_CTRL_PP0_CLKACT_MASK | CRF_APB_GPU_REF_CTRL_PP1_CLKACT_MASK | 0 ); - - RegVal = ((0x00000001U << CRF_APB_GPU_REF_CTRL_DIVISOR0_SHIFT - | 0x00000000U << CRF_APB_GPU_REF_CTRL_SRCSEL_SHIFT - | 0x00000001U << CRF_APB_GPU_REF_CTRL_CLKACT_SHIFT - | 0x00000001U << CRF_APB_GPU_REF_CTRL_PP0_CLKACT_SHIFT - | 0x00000001U << CRF_APB_GPU_REF_CTRL_PP1_CLKACT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_GPU_REF_CTRL_OFFSET ,0x07003F07U ,0x07000100U); - /*############################################################################################################################ */ - - /*Register : GDMA_REF_CTRL @ 0XFD1A00B8

- - 6 bit divider - PSU_CRF_APB_GDMA_REF_CTRL_DIVISOR0 0x2 - - 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - lock. This is not usually an issue, but designers must be aware.) - PSU_CRF_APB_GDMA_REF_CTRL_SRCSEL 0x0 - - Clock active signal. Switch to 0 to disable the clock - PSU_CRF_APB_GDMA_REF_CTRL_CLKACT 0x1 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFD1A00B8, 0x01003F07U ,0x01000200U) - RegMask = (CRF_APB_GDMA_REF_CTRL_DIVISOR0_MASK | CRF_APB_GDMA_REF_CTRL_SRCSEL_MASK | CRF_APB_GDMA_REF_CTRL_CLKACT_MASK | 0 ); - - RegVal = ((0x00000002U << CRF_APB_GDMA_REF_CTRL_DIVISOR0_SHIFT - | 0x00000000U << CRF_APB_GDMA_REF_CTRL_SRCSEL_SHIFT - | 0x00000001U << CRF_APB_GDMA_REF_CTRL_CLKACT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_GDMA_REF_CTRL_OFFSET ,0x01003F07U ,0x01000200U); - /*############################################################################################################################ */ - - /*Register : DPDMA_REF_CTRL @ 0XFD1A00BC

- - 6 bit divider - PSU_CRF_APB_DPDMA_REF_CTRL_DIVISOR0 0x2 - - 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - lock. This is not usually an issue, but designers must be aware.) - PSU_CRF_APB_DPDMA_REF_CTRL_SRCSEL 0x0 - - Clock active signal. Switch to 0 to disable the clock - PSU_CRF_APB_DPDMA_REF_CTRL_CLKACT 0x1 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFD1A00BC, 0x01003F07U ,0x01000200U) - RegMask = (CRF_APB_DPDMA_REF_CTRL_DIVISOR0_MASK | CRF_APB_DPDMA_REF_CTRL_SRCSEL_MASK | CRF_APB_DPDMA_REF_CTRL_CLKACT_MASK | 0 ); - - RegVal = ((0x00000002U << CRF_APB_DPDMA_REF_CTRL_DIVISOR0_SHIFT - | 0x00000000U << CRF_APB_DPDMA_REF_CTRL_SRCSEL_SHIFT - | 0x00000001U << CRF_APB_DPDMA_REF_CTRL_CLKACT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_DPDMA_REF_CTRL_OFFSET ,0x01003F07U ,0x01000200U); - /*############################################################################################################################ */ - - /*Register : TOPSW_MAIN_CTRL @ 0XFD1A00C0

- - 6 bit divider - PSU_CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0 0x2 - - 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - lock. This is not usually an issue, but designers must be aware.) - PSU_CRF_APB_TOPSW_MAIN_CTRL_SRCSEL 0x2 - - Clock active signal. Switch to 0 to disable the clock - PSU_CRF_APB_TOPSW_MAIN_CTRL_CLKACT 0x1 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFD1A00C0, 0x01003F07U ,0x01000202U) - RegMask = (CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_MASK | CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_MASK | CRF_APB_TOPSW_MAIN_CTRL_CLKACT_MASK | 0 ); - - RegVal = ((0x00000002U << CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_SHIFT - | 0x00000002U << CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_SHIFT - | 0x00000001U << CRF_APB_TOPSW_MAIN_CTRL_CLKACT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_TOPSW_MAIN_CTRL_OFFSET ,0x01003F07U ,0x01000202U); - /*############################################################################################################################ */ - - /*Register : TOPSW_LSBUS_CTRL @ 0XFD1A00C4

- - 6 bit divider - PSU_CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0 0x5 - - 000 = APLL; 010 = IOPLL_TO_FPD; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of - he new clock. This is not usually an issue, but designers must be aware.) - PSU_CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL 0x2 - - Clock active signal. Switch to 0 to disable the clock - PSU_CRF_APB_TOPSW_LSBUS_CTRL_CLKACT 0x1 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFD1A00C4, 0x01003F07U ,0x01000502U) - RegMask = (CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_MASK | CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_MASK | CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_MASK | 0 ); - - RegVal = ((0x00000005U << CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_SHIFT - | 0x00000002U << CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_SHIFT - | 0x00000001U << CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_TOPSW_LSBUS_CTRL_OFFSET ,0x01003F07U ,0x01000502U); - /*############################################################################################################################ */ - - /*Register : DBG_TSTMP_CTRL @ 0XFD1A00F8

- - 6 bit divider - PSU_CRF_APB_DBG_TSTMP_CTRL_DIVISOR0 0x2 - - 000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of - he new clock. This is not usually an issue, but designers must be aware.) - PSU_CRF_APB_DBG_TSTMP_CTRL_SRCSEL 0x0 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFD1A00F8, 0x00003F07U ,0x00000200U) - RegMask = (CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_MASK | CRF_APB_DBG_TSTMP_CTRL_SRCSEL_MASK | 0 ); - - RegVal = ((0x00000002U << CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_SHIFT - | 0x00000000U << CRF_APB_DBG_TSTMP_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_DBG_TSTMP_CTRL_OFFSET ,0x00003F07U ,0x00000200U); - /*############################################################################################################################ */ - - /*Register : IOU_TTC_APB_CLK @ 0XFF180380

- - 00" = Select the APB switch clock for the APB interface of TTC0'01" = Select the PLL ref clock for the APB interface of TTC0' - 0" = Select the R5 clock for the APB interface of TTC0 - PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL 0 - - 00" = Select the APB switch clock for the APB interface of TTC1'01" = Select the PLL ref clock for the APB interface of TTC1' - 0" = Select the R5 clock for the APB interface of TTC1 - PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL 0 - - 00" = Select the APB switch clock for the APB interface of TTC2'01" = Select the PLL ref clock for the APB interface of TTC2' - 0" = Select the R5 clock for the APB interface of TTC2 - PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL 0 - - 00" = Select the APB switch clock for the APB interface of TTC3'01" = Select the PLL ref clock for the APB interface of TTC3' - 0" = Select the R5 clock for the APB interface of TTC3 - PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL 0 - - TTC APB clock select - (OFFSET, MASK, VALUE) (0XFF180380, 0x000000FFU ,0x00000000U) - RegMask = (IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_MASK | IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_MASK | IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_MASK | IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_IOU_TTC_APB_CLK_OFFSET ,0x000000FFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : WDT_CLK_SEL @ 0XFD610100

- - System watchdog timer clock source selection: 0: Internal APB clock 1: External (PL clock via EMIO or Pinout clock via MIO) - PSU_FPD_SLCR_WDT_CLK_SEL_SELECT 0 - - SWDT clock source select - (OFFSET, MASK, VALUE) (0XFD610100, 0x00000001U ,0x00000000U) - RegMask = (FPD_SLCR_WDT_CLK_SEL_SELECT_MASK | 0 ); - - RegVal = ((0x00000000U << FPD_SLCR_WDT_CLK_SEL_SELECT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (FPD_SLCR_WDT_CLK_SEL_OFFSET ,0x00000001U ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : WDT_CLK_SEL @ 0XFF180300

- - System watchdog timer clock source selection: 0: internal clock APB clock 1: external clock from PL via EMIO, or from pinout - ia MIO - PSU_IOU_SLCR_WDT_CLK_SEL_SELECT 0 - - SWDT clock source select - (OFFSET, MASK, VALUE) (0XFF180300, 0x00000001U ,0x00000000U) - RegMask = (IOU_SLCR_WDT_CLK_SEL_SELECT_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_WDT_CLK_SEL_SELECT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_WDT_CLK_SEL_OFFSET ,0x00000001U ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : CSUPMU_WDT_CLK_SEL @ 0XFF410050

- - System watchdog timer clock source selection: 0: internal clock APB clock 1: external clock pss_ref_clk - PSU_LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT 0 - - SWDT clock source select - (OFFSET, MASK, VALUE) (0XFF410050, 0x00000001U ,0x00000000U) - RegMask = (LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_MASK | 0 ); - - RegVal = ((0x00000000U << LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (LPD_SLCR_CSUPMU_WDT_CLK_SEL_OFFSET ,0x00000001U ,0x00000000U); - /*############################################################################################################################ */ - - - return 1; + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_CAN1_REF_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_CAN1_REF_CTRL_DIVISOR1 0x1 + + * 6 bit divider + * PSU_CRL_APB_CAN1_REF_CTRL_DIVISOR0 0xf + + * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_CAN1_REF_CTRL_SRCSEL 0x0 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E0088, 0x013F3F07U ,0x01010F00U) + */ + PSU_Mask_Write(CRL_APB_CAN1_REF_CTRL_OFFSET, + 0x013F3F07U, 0x01010F00U); +/*##################################################################### */ + + /* + * Register : CPU_R5_CTRL @ 0XFF5E0090 + + * Turing this off will shut down the OCM, some parts of the APM, and preve + * nt transactions going from the FPD to the LPD and could lead to system h + * ang + * PSU_CRL_APB_CPU_R5_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_CPU_R5_CTRL_DIVISOR0 0x3 + + * 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_CPU_R5_CTRL_SRCSEL 0x2 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E0090, 0x01003F07U ,0x01000302U) + */ + PSU_Mask_Write(CRL_APB_CPU_R5_CTRL_OFFSET, 0x01003F07U, 0x01000302U); +/*##################################################################### */ + + /* + * Register : IOU_SWITCH_CTRL @ 0XFF5E009C + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_IOU_SWITCH_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_IOU_SWITCH_CTRL_DIVISOR0 0x6 + + * 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_IOU_SWITCH_CTRL_SRCSEL 0x2 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E009C, 0x01003F07U ,0x01000602U) + */ + PSU_Mask_Write(CRL_APB_IOU_SWITCH_CTRL_OFFSET, + 0x01003F07U, 0x01000602U); +/*##################################################################### */ + + /* + * Register : PCAP_CTRL @ 0XFF5E00A4 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_PCAP_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_PCAP_CTRL_DIVISOR0 0x8 + + * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_PCAP_CTRL_SRCSEL 0x0 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E00A4, 0x01003F07U ,0x01000800U) + */ + PSU_Mask_Write(CRL_APB_PCAP_CTRL_OFFSET, 0x01003F07U, 0x01000800U); +/*##################################################################### */ + + /* + * Register : LPD_SWITCH_CTRL @ 0XFF5E00A8 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_LPD_SWITCH_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_LPD_SWITCH_CTRL_DIVISOR0 0x3 + + * 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_LPD_SWITCH_CTRL_SRCSEL 0x2 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E00A8, 0x01003F07U ,0x01000302U) + */ + PSU_Mask_Write(CRL_APB_LPD_SWITCH_CTRL_OFFSET, + 0x01003F07U, 0x01000302U); +/*##################################################################### */ + + /* + * Register : LPD_LSBUS_CTRL @ 0XFF5E00AC + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_LPD_LSBUS_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_LPD_LSBUS_CTRL_DIVISOR0 0xf + + * 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_LPD_LSBUS_CTRL_SRCSEL 0x2 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E00AC, 0x01003F07U ,0x01000F02U) + */ + PSU_Mask_Write(CRL_APB_LPD_LSBUS_CTRL_OFFSET, + 0x01003F07U, 0x01000F02U); +/*##################################################################### */ + + /* + * Register : DBG_LPD_CTRL @ 0XFF5E00B0 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_DBG_LPD_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_DBG_LPD_CTRL_DIVISOR0 0x6 + + * 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_DBG_LPD_CTRL_SRCSEL 0x2 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E00B0, 0x01003F07U ,0x01000602U) + */ + PSU_Mask_Write(CRL_APB_DBG_LPD_CTRL_OFFSET, + 0x01003F07U, 0x01000602U); +/*##################################################################### */ + + /* + * Register : ADMA_REF_CTRL @ 0XFF5E00B8 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_ADMA_REF_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_ADMA_REF_CTRL_DIVISOR0 0x3 + + * 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_ADMA_REF_CTRL_SRCSEL 0x2 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E00B8, 0x01003F07U ,0x01000302U) + */ + PSU_Mask_Write(CRL_APB_ADMA_REF_CTRL_OFFSET, + 0x01003F07U, 0x01000302U); +/*##################################################################### */ + + /* + * Register : PL0_REF_CTRL @ 0XFF5E00C0 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_PL0_REF_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_PL0_REF_CTRL_DIVISOR1 0x1 + + * 6 bit divider + * PSU_CRL_APB_PL0_REF_CTRL_DIVISOR0 0xf + + * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_PL0_REF_CTRL_SRCSEL 0x0 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E00C0, 0x013F3F07U ,0x01010F00U) + */ + PSU_Mask_Write(CRL_APB_PL0_REF_CTRL_OFFSET, + 0x013F3F07U, 0x01010F00U); +/*##################################################################### */ + + /* + * Register : AMS_REF_CTRL @ 0XFF5E0108 + + * 6 bit divider + * PSU_CRL_APB_AMS_REF_CTRL_DIVISOR1 0x1 + + * 6 bit divider + * PSU_CRL_APB_AMS_REF_CTRL_DIVISOR0 0x1e + + * 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_AMS_REF_CTRL_SRCSEL 0x2 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_AMS_REF_CTRL_CLKACT 0x1 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E0108, 0x013F3F07U ,0x01011E02U) + */ + PSU_Mask_Write(CRL_APB_AMS_REF_CTRL_OFFSET, + 0x013F3F07U, 0x01011E02U); +/*##################################################################### */ + + /* + * Register : DLL_REF_CTRL @ 0XFF5E0104 + + * 000 = IOPLL; 001 = RPLL; (This signal may only be toggled after 4 cycles + * of the old clock and 4 cycles of the new clock. This is not usually an + * issue, but designers must be aware.) + * PSU_CRL_APB_DLL_REF_CTRL_SRCSEL 0 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E0104, 0x00000007U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_DLL_REF_CTRL_OFFSET, + 0x00000007U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : TIMESTAMP_REF_CTRL @ 0XFF5E0128 + + * 6 bit divider + * PSU_CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0 0xf + + * 1XX = pss_ref_clk; 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may + * only be toggled after 4 cycles of the old clock and 4 cycles of the new + * clock. This is not usually an issue, but designers must be aware.) + * PSU_CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL 0x0 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT 0x1 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E0128, 0x01003F07U ,0x01000F00U) + */ + PSU_Mask_Write(CRL_APB_TIMESTAMP_REF_CTRL_OFFSET, + 0x01003F07U, 0x01000F00U); +/*##################################################################### */ + + /* + * Register : SATA_REF_CTRL @ 0XFD1A00A0 + + * 000 = IOPLL_TO_FPD; 010 = APLL; 011 = DPLL; (This signal may only be tog + * gled after 4 cycles of the old clock and 4 cycles of the new clock. This + * is not usually an issue, but designers must be aware.) + * PSU_CRF_APB_SATA_REF_CTRL_SRCSEL 0x0 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRF_APB_SATA_REF_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRF_APB_SATA_REF_CTRL_DIVISOR0 0x2 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFD1A00A0, 0x01003F07U ,0x01000200U) + */ + PSU_Mask_Write(CRF_APB_SATA_REF_CTRL_OFFSET, + 0x01003F07U, 0x01000200U); +/*##################################################################### */ + + /* + * Register : PCIE_REF_CTRL @ 0XFD1A00B4 + + * 000 = IOPLL_TO_FPD; 010 = RPLL_TO_FPD; 011 = DPLL; (This signal may only + * be toggled after 4 cycles of the old clock and 4 cycles of the new cloc + * k. This is not usually an issue, but designers must be aware.) + * PSU_CRF_APB_PCIE_REF_CTRL_SRCSEL 0x0 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRF_APB_PCIE_REF_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRF_APB_PCIE_REF_CTRL_DIVISOR0 0x2 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFD1A00B4, 0x01003F07U ,0x01000200U) + */ + PSU_Mask_Write(CRF_APB_PCIE_REF_CTRL_OFFSET, + 0x01003F07U, 0x01000200U); +/*##################################################################### */ + + /* + * Register : DP_VIDEO_REF_CTRL @ 0XFD1A0070 + + * 6 bit divider + * PSU_CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1 0x1 + + * 6 bit divider + * PSU_CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0 0x5 + + * 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (T + * his signal may only be toggled after 4 cycles of the old clock and 4 cyc + * les of the new clock. This is not usually an issue, but designers must b + * e aware.) + * PSU_CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL 0x0 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRF_APB_DP_VIDEO_REF_CTRL_CLKACT 0x1 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFD1A0070, 0x013F3F07U ,0x01010500U) + */ + PSU_Mask_Write(CRF_APB_DP_VIDEO_REF_CTRL_OFFSET, + 0x013F3F07U, 0x01010500U); +/*##################################################################### */ + + /* + * Register : DP_AUDIO_REF_CTRL @ 0XFD1A0074 + + * 6 bit divider + * PSU_CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1 0x1 + + * 6 bit divider + * PSU_CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0 0xf + + * 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (T + * his signal may only be toggled after 4 cycles of the old clock and 4 cyc + * les of the new clock. This is not usually an issue, but designers must b + * e aware.) + * PSU_CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL 0x3 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRF_APB_DP_AUDIO_REF_CTRL_CLKACT 0x1 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFD1A0074, 0x013F3F07U ,0x01010F03U) + */ + PSU_Mask_Write(CRF_APB_DP_AUDIO_REF_CTRL_OFFSET, + 0x013F3F07U, 0x01010F03U); +/*##################################################################### */ + + /* + * Register : DP_STC_REF_CTRL @ 0XFD1A007C + + * 6 bit divider + * PSU_CRF_APB_DP_STC_REF_CTRL_DIVISOR1 0x1 + + * 6 bit divider + * PSU_CRF_APB_DP_STC_REF_CTRL_DIVISOR0 0xe + + * 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD; (This signal may only be togg + * led after 4 cycles of the old clock and 4 cycles of the new clock. This + * is not usually an issue, but designers must be aware.) + * PSU_CRF_APB_DP_STC_REF_CTRL_SRCSEL 0x3 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRF_APB_DP_STC_REF_CTRL_CLKACT 0x1 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFD1A007C, 0x013F3F07U ,0x01010E03U) + */ + PSU_Mask_Write(CRF_APB_DP_STC_REF_CTRL_OFFSET, + 0x013F3F07U, 0x01010E03U); +/*##################################################################### */ + + /* + * Register : ACPU_CTRL @ 0XFD1A0060 + + * 6 bit divider + * PSU_CRF_APB_ACPU_CTRL_DIVISOR0 0x1 + + * 000 = APLL; 010 = DPLL; 011 = VPLL; (This signal may only be toggled aft + * er 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRF_APB_ACPU_CTRL_SRCSEL 0x0 + + * Clock active signal. Switch to 0 to disable the clock. For the half spee + * d APU Clock + * PSU_CRF_APB_ACPU_CTRL_CLKACT_HALF 0x1 + + * Clock active signal. Switch to 0 to disable the clock. For the full spee + * d ACPUX Clock. This will shut off the high speed clock to the entire APU + * PSU_CRF_APB_ACPU_CTRL_CLKACT_FULL 0x1 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFD1A0060, 0x03003F07U ,0x03000100U) + */ + PSU_Mask_Write(CRF_APB_ACPU_CTRL_OFFSET, 0x03003F07U, 0x03000100U); +/*##################################################################### */ + + /* + * Register : DBG_FPD_CTRL @ 0XFD1A0068 + + * 6 bit divider + * PSU_CRF_APB_DBG_FPD_CTRL_DIVISOR0 0x2 + + * 000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be tog + * gled after 4 cycles of the old clock and 4 cycles of the new clock. This + * is not usually an issue, but designers must be aware.) + * PSU_CRF_APB_DBG_FPD_CTRL_SRCSEL 0x0 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRF_APB_DBG_FPD_CTRL_CLKACT 0x1 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFD1A0068, 0x01003F07U ,0x01000200U) + */ + PSU_Mask_Write(CRF_APB_DBG_FPD_CTRL_OFFSET, + 0x01003F07U, 0x01000200U); +/*##################################################################### */ + + /* + * Register : DDR_CTRL @ 0XFD1A0080 + + * 6 bit divider + * PSU_CRF_APB_DDR_CTRL_DIVISOR0 0x2 + + * 000 = DPLL; 001 = VPLL; (This signal may only be toggled after 4 cycles + * of the old clock and 4 cycles of the new clock. This is not usually an i + * ssue, but designers must be aware.) + * PSU_CRF_APB_DDR_CTRL_SRCSEL 0x0 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFD1A0080, 0x00003F07U ,0x00000200U) + */ + PSU_Mask_Write(CRF_APB_DDR_CTRL_OFFSET, 0x00003F07U, 0x00000200U); +/*##################################################################### */ + + /* + * Register : GPU_REF_CTRL @ 0XFD1A0084 + + * 6 bit divider + * PSU_CRF_APB_GPU_REF_CTRL_DIVISOR0 0x1 + + * 000 = IOPLL_TO_FPD; 010 = VPLL; 011 = DPLL; (This signal may only be tog + * gled after 4 cycles of the old clock and 4 cycles of the new clock. This + * is not usually an issue, but designers must be aware.) + * PSU_CRF_APB_GPU_REF_CTRL_SRCSEL 0x0 + + * Clock active signal. Switch to 0 to disable the clock, which will stop c + * lock for GPU (and both Pixel Processors). + * PSU_CRF_APB_GPU_REF_CTRL_CLKACT 0x1 + + * Clock active signal for Pixel Processor. Switch to 0 to disable the cloc + * k only to this Pixel Processor + * PSU_CRF_APB_GPU_REF_CTRL_PP0_CLKACT 0x1 + + * Clock active signal for Pixel Processor. Switch to 0 to disable the cloc + * k only to this Pixel Processor + * PSU_CRF_APB_GPU_REF_CTRL_PP1_CLKACT 0x1 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFD1A0084, 0x07003F07U ,0x07000100U) + */ + PSU_Mask_Write(CRF_APB_GPU_REF_CTRL_OFFSET, + 0x07003F07U, 0x07000100U); +/*##################################################################### */ + + /* + * Register : GDMA_REF_CTRL @ 0XFD1A00B8 + + * 6 bit divider + * PSU_CRF_APB_GDMA_REF_CTRL_DIVISOR0 0x2 + + * 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled aft + * er 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRF_APB_GDMA_REF_CTRL_SRCSEL 0x0 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRF_APB_GDMA_REF_CTRL_CLKACT 0x1 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFD1A00B8, 0x01003F07U ,0x01000200U) + */ + PSU_Mask_Write(CRF_APB_GDMA_REF_CTRL_OFFSET, + 0x01003F07U, 0x01000200U); +/*##################################################################### */ + + /* + * Register : DPDMA_REF_CTRL @ 0XFD1A00BC + + * 6 bit divider + * PSU_CRF_APB_DPDMA_REF_CTRL_DIVISOR0 0x2 + + * 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled aft + * er 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRF_APB_DPDMA_REF_CTRL_SRCSEL 0x0 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRF_APB_DPDMA_REF_CTRL_CLKACT 0x1 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFD1A00BC, 0x01003F07U ,0x01000200U) + */ + PSU_Mask_Write(CRF_APB_DPDMA_REF_CTRL_OFFSET, + 0x01003F07U, 0x01000200U); +/*##################################################################### */ + + /* + * Register : TOPSW_MAIN_CTRL @ 0XFD1A00C0 + + * 6 bit divider + * PSU_CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0 0x2 + + * 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled aft + * er 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRF_APB_TOPSW_MAIN_CTRL_SRCSEL 0x3 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRF_APB_TOPSW_MAIN_CTRL_CLKACT 0x1 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFD1A00C0, 0x01003F07U ,0x01000203U) + */ + PSU_Mask_Write(CRF_APB_TOPSW_MAIN_CTRL_OFFSET, + 0x01003F07U, 0x01000203U); +/*##################################################################### */ + + /* + * Register : TOPSW_LSBUS_CTRL @ 0XFD1A00C4 + + * 6 bit divider + * PSU_CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0 0x5 + + * 000 = APLL; 010 = IOPLL_TO_FPD; 011 = DPLL; (This signal may only be tog + * gled after 4 cycles of the old clock and 4 cycles of the new clock. This + * is not usually an issue, but designers must be aware.) + * PSU_CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL 0x2 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRF_APB_TOPSW_LSBUS_CTRL_CLKACT 0x1 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFD1A00C4, 0x01003F07U ,0x01000502U) + */ + PSU_Mask_Write(CRF_APB_TOPSW_LSBUS_CTRL_OFFSET, + 0x01003F07U, 0x01000502U); +/*##################################################################### */ + + /* + * Register : DBG_TSTMP_CTRL @ 0XFD1A00F8 + + * 6 bit divider + * PSU_CRF_APB_DBG_TSTMP_CTRL_DIVISOR0 0x2 + + * 000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be tog + * gled after 4 cycles of the old clock and 4 cycles of the new clock. This + * is not usually an issue, but designers must be aware.) + * PSU_CRF_APB_DBG_TSTMP_CTRL_SRCSEL 0x0 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFD1A00F8, 0x00003F07U ,0x00000200U) + */ + PSU_Mask_Write(CRF_APB_DBG_TSTMP_CTRL_OFFSET, + 0x00003F07U, 0x00000200U); +/*##################################################################### */ + + /* + * Register : IOU_TTC_APB_CLK @ 0XFF180380 + + * 00" = Select the APB switch clock for the APB interface of TTC0'01" = Se + * lect the PLL ref clock for the APB interface of TTC0'10" = Select the R5 + * clock for the APB interface of TTC0 + * PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL 0 + + * 00" = Select the APB switch clock for the APB interface of TTC1'01" = Se + * lect the PLL ref clock for the APB interface of TTC1'10" = Select the R5 + * clock for the APB interface of TTC1 + * PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL 0 + + * 00" = Select the APB switch clock for the APB interface of TTC2'01" = Se + * lect the PLL ref clock for the APB interface of TTC2'10" = Select the R5 + * clock for the APB interface of TTC2 + * PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL 0 + + * 00" = Select the APB switch clock for the APB interface of TTC3'01" = Se + * lect the PLL ref clock for the APB interface of TTC3'10" = Select the R5 + * clock for the APB interface of TTC3 + * PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL 0 + + * TTC APB clock select + * (OFFSET, MASK, VALUE) (0XFF180380, 0x000000FFU ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_IOU_TTC_APB_CLK_OFFSET, + 0x000000FFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : WDT_CLK_SEL @ 0XFD610100 + + * System watchdog timer clock source selection: 0: Internal APB clock 1: E + * xternal (PL clock via EMIO or Pinout clock via MIO) + * PSU_FPD_SLCR_WDT_CLK_SEL_SELECT 0 + + * SWDT clock source select + * (OFFSET, MASK, VALUE) (0XFD610100, 0x00000001U ,0x00000000U) + */ + PSU_Mask_Write(FPD_SLCR_WDT_CLK_SEL_OFFSET, + 0x00000001U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : WDT_CLK_SEL @ 0XFF180300 + + * System watchdog timer clock source selection: 0: internal clock APB cloc + * k 1: external clock from PL via EMIO, or from pinout via MIO + * PSU_IOU_SLCR_WDT_CLK_SEL_SELECT 0 + + * SWDT clock source select + * (OFFSET, MASK, VALUE) (0XFF180300, 0x00000001U ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_WDT_CLK_SEL_OFFSET, + 0x00000001U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : CSUPMU_WDT_CLK_SEL @ 0XFF410050 + + * System watchdog timer clock source selection: 0: internal clock APB cloc + * k 1: external clock pss_ref_clk + * PSU_LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT 0 + + * SWDT clock source select + * (OFFSET, MASK, VALUE) (0XFF410050, 0x00000001U ,0x00000000U) + */ + PSU_Mask_Write(LPD_SLCR_CSUPMU_WDT_CLK_SEL_OFFSET, + 0x00000001U, 0x00000000U); +/*##################################################################### */ + + + return 1; } -unsigned long psu_ddr_init_data() { - // : DDR INITIALIZATION - // : DDR CONTROLLER RESET - /*Register : RST_DDR_SS @ 0XFD1A0108

- - DDR block level reset inside of the DDR Sub System - PSU_CRF_APB_RST_DDR_SS_DDR_RESET 0X1 - - DDR sub system block level reset - (OFFSET, MASK, VALUE) (0XFD1A0108, 0x00000008U ,0x00000008U) - RegMask = (CRF_APB_RST_DDR_SS_DDR_RESET_MASK | 0 ); - - RegVal = ((0x00000001U << CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_RST_DDR_SS_OFFSET ,0x00000008U ,0x00000008U); - /*############################################################################################################################ */ - - /*Register : MSTR @ 0XFD070000

- - Indicates the configuration of the device used in the system. - 00 - x4 device - 01 - x8 device - 10 - x16 device - 11 - x32 - evice - PSU_DDRC_MSTR_DEVICE_CONFIG 0x1 - - Choose which registers are used. - 0 - Original registers - 1 - Shadow registers - PSU_DDRC_MSTR_FREQUENCY_MODE 0x0 - - Only present for multi-rank configurations. Each bit represents one rank. For two-rank configurations, only bits[25:24] are p - esent. - 1 - populated - 0 - unpopulated LSB is the lowest rank number. For 2 ranks following combinations are legal: - 01 - - ne rank - 11 - Two ranks - Others - Reserved. For 4 ranks following combinations are legal: - 0001 - One rank - 0011 - Two ra - ks - 1111 - Four ranks - PSU_DDRC_MSTR_ACTIVE_RANKS 0x1 - - SDRAM burst length used: - 0001 - Burst length of 2 (only supported for mDDR) - 0010 - Burst length of 4 - 0100 - Burst lengt - of 8 - 1000 - Burst length of 16 (only supported for mDDR, LPDDR2, and LPDDR4) All other values are reserved. This controls - he burst size used to access the SDRAM. This must match the burst length mode register setting in the SDRAM. (For BC4/8 on-th - -fly mode of DDR3 and DDR4, set this field to 0x0100) Burst length of 2 is not supported with AXI ports when MEMC_BURST_LENGT - is 8. Burst length of 2 is only supported with MEMC_FREQ_RATIO = 1 - PSU_DDRC_MSTR_BURST_RDWR 0x4 - - Set to 1 when the uMCTL2 and DRAM has to be put in DLL-off mode for low frequency operation. Set to 0 to put uMCTL2 and DRAM - n DLL-on mode for normal frequency operation. If DDR4 CRC/parity retry is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), d - l_off_mode is not supported, and this bit must be set to '0'. - PSU_DDRC_MSTR_DLL_OFF_MODE 0x0 - - Selects proportion of DQ bus width that is used by the SDRAM - 00 - Full DQ bus width to SDRAM - 01 - Half DQ bus width to SD - AM - 10 - Quarter DQ bus width to SDRAM - 11 - Reserved. Note that half bus width mode is only supported when the SDRAM bus w - dth is a multiple of 16, and quarter bus width mode is only supported when the SDRAM bus width is a multiple of 32 and the co - figuration parameter MEMC_QBUS_SUPPORT is set. Bus width refers to DQ bus width (excluding any ECC width). - PSU_DDRC_MSTR_DATA_BUS_WIDTH 0x0 - - 1 indicates put the DRAM in geardown mode (2N) and 0 indicates put the DRAM in normal mode (1N). This register can be changed - only when the Controller is in self-refresh mode. This signal must be set the same value as MR3 bit A3. Note: Geardown mode - s not supported if the configuration parameter MEMC_CMD_RTN2IDLE is set - PSU_DDRC_MSTR_GEARDOWN_MODE 0x0 - - If 1, then uMCTL2 uses 2T timing. Otherwise, uses 1T timing. In 2T timing, all command signals (except chip select) are held - or 2 clocks on the SDRAM bus. Chip select is asserted on the second cycle of the command Note: 2T timing is not supported in - PDDR2/LPDDR3/LPDDR4 mode Note: 2T timing is not supported if the configuration parameter MEMC_CMD_RTN2IDLE is set Note: 2T ti - ing is not supported in DDR4 geardown mode. - PSU_DDRC_MSTR_EN_2T_TIMING_MODE 0x0 - - When set, enable burst-chop in DDR3/DDR4. Burst Chop for Reads is exercised only in HIF configurations (UMCTL2_INCL_ARB not s - t) and if in full bus width mode (MSTR.data_bus_width = 00). Burst Chop for Writes is exercised only if Partial Writes enable - (UMCTL2_PARTIAL_WR=1) and if CRC is disabled (CRCPARCTL1.crc_enable = 0). If DDR4 CRC/parity retry is enabled (CRCPARCTL1.cr - _parity_retry_enable = 1), burst chop is not supported, and this bit must be set to '0' - PSU_DDRC_MSTR_BURSTCHOP 0x0 - - Select LPDDR4 SDRAM - 1 - LPDDR4 SDRAM device in use. - 0 - non-LPDDR4 device in use Present only in designs configured to su - port LPDDR4. - PSU_DDRC_MSTR_LPDDR4 0x0 - - Select DDR4 SDRAM - 1 - DDR4 SDRAM device in use. - 0 - non-DDR4 device in use Present only in designs configured to support - DR4. - PSU_DDRC_MSTR_DDR4 0x1 - - Select LPDDR3 SDRAM - 1 - LPDDR3 SDRAM device in use. - 0 - non-LPDDR3 device in use Present only in designs configured to su - port LPDDR3. - PSU_DDRC_MSTR_LPDDR3 0x0 - - Select LPDDR2 SDRAM - 1 - LPDDR2 SDRAM device in use. - 0 - non-LPDDR2 device in use Present only in designs configured to su - port LPDDR2. - PSU_DDRC_MSTR_LPDDR2 0x0 - - Select DDR3 SDRAM - 1 - DDR3 SDRAM device in use - 0 - non-DDR3 SDRAM device in use Only present in designs that support DDR3 - - PSU_DDRC_MSTR_DDR3 0x0 - - Master Register - (OFFSET, MASK, VALUE) (0XFD070000, 0xE30FBE3DU ,0x41040010U) - RegMask = (DDRC_MSTR_DEVICE_CONFIG_MASK | DDRC_MSTR_FREQUENCY_MODE_MASK | DDRC_MSTR_ACTIVE_RANKS_MASK | DDRC_MSTR_BURST_RDWR_MASK | DDRC_MSTR_DLL_OFF_MODE_MASK | DDRC_MSTR_DATA_BUS_WIDTH_MASK | DDRC_MSTR_GEARDOWN_MODE_MASK | DDRC_MSTR_EN_2T_TIMING_MODE_MASK | DDRC_MSTR_BURSTCHOP_MASK | DDRC_MSTR_LPDDR4_MASK | DDRC_MSTR_DDR4_MASK | DDRC_MSTR_LPDDR3_MASK | DDRC_MSTR_LPDDR2_MASK | DDRC_MSTR_DDR3_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_MSTR_DEVICE_CONFIG_SHIFT - | 0x00000000U << DDRC_MSTR_FREQUENCY_MODE_SHIFT - | 0x00000001U << DDRC_MSTR_ACTIVE_RANKS_SHIFT - | 0x00000004U << DDRC_MSTR_BURST_RDWR_SHIFT - | 0x00000000U << DDRC_MSTR_DLL_OFF_MODE_SHIFT - | 0x00000000U << DDRC_MSTR_DATA_BUS_WIDTH_SHIFT - | 0x00000000U << DDRC_MSTR_GEARDOWN_MODE_SHIFT - | 0x00000000U << DDRC_MSTR_EN_2T_TIMING_MODE_SHIFT - | 0x00000000U << DDRC_MSTR_BURSTCHOP_SHIFT - | 0x00000000U << DDRC_MSTR_LPDDR4_SHIFT - | 0x00000001U << DDRC_MSTR_DDR4_SHIFT - | 0x00000000U << DDRC_MSTR_LPDDR3_SHIFT - | 0x00000000U << DDRC_MSTR_LPDDR2_SHIFT - | 0x00000000U << DDRC_MSTR_DDR3_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_MSTR_OFFSET ,0xE30FBE3DU ,0x41040010U); - /*############################################################################################################################ */ - - /*Register : MRCTRL0 @ 0XFD070010

- - Setting this register bit to 1 triggers a mode register read or write operation. When the MR operation is complete, the uMCTL - automatically clears this bit. The other register fields of this register must be written in a separate APB transaction, bef - re setting this mr_wr bit. It is recommended NOT to set this signal if in Init, Deep power-down or MPSM operating modes. - PSU_DDRC_MRCTRL0_MR_WR 0x0 - - Address of the mode register that is to be written to. - 0000 - MR0 - 0001 - MR1 - 0010 - MR2 - 0011 - MR3 - 0100 - MR4 - 010 - - MR5 - 0110 - MR6 - 0111 - MR7 Don't Care for LPDDR2/LPDDR3/LPDDR4 (see MRCTRL1.mr_data for mode register addressing in LPD - R2/LPDDR3/LPDDR4) This signal is also used for writing to control words of RDIMMs. In that case, it corresponds to the bank a - dress bits sent to the RDIMM In case of DDR4, the bit[3:2] corresponds to the bank group bits. Therefore, the bit[3] as well - s the bit[2:0] must be set to an appropriate value which is considered both the Address Mirroring of UDIMMs/RDIMMs and the Ou - put Inversion of RDIMMs. - PSU_DDRC_MRCTRL0_MR_ADDR 0x0 - - Controls which rank is accessed by MRCTRL0.mr_wr. Normally, it is desired to access all ranks, so all bits should be set to 1 - However, for multi-rank UDIMMs/RDIMMs which implement address mirroring, it may be necessary to access ranks individually. E - amples (assume uMCTL2 is configured for 4 ranks): - 0x1 - select rank 0 only - 0x2 - select rank 1 only - 0x5 - select ranks - and 2 - 0xA - select ranks 1 and 3 - 0xF - select ranks 0, 1, 2 and 3 - PSU_DDRC_MRCTRL0_MR_RANK 0x3 - - Indicates whether Software intervention is allowed via MRCTRL0/MRCTRL1 before automatic SDRAM initialization routine or not. - or DDR4, this bit can be used to initialize the DDR4 RCD (MR7) before automatic SDRAM initialization. For LPDDR4, this bit ca - be used to program additional mode registers before automatic SDRAM initialization if necessary. Note: This must be cleared - o 0 after completing Software operation. Otherwise, SDRAM initialization routine will not re-start. - 0 - Software interventi - n is not allowed - 1 - Software intervention is allowed - PSU_DDRC_MRCTRL0_SW_INIT_INT 0x0 - - Indicates whether the mode register operation is MRS in PDA mode or not - 0 - MRS - 1 - MRS in Per DRAM Addressability mode - PSU_DDRC_MRCTRL0_PDA_EN 0x0 - - Indicates whether the mode register operation is MRS or WR/RD for MPR (only supported for DDR4) - 0 - MRS - 1 - WR/RD for MPR - PSU_DDRC_MRCTRL0_MPR_EN 0x0 - - Indicates whether the mode register operation is read or write. Only used for LPDDR2/LPDDR3/LPDDR4/DDR4. - 0 - Write - 1 - Re - d - PSU_DDRC_MRCTRL0_MR_TYPE 0x0 - - Mode Register Read/Write Control Register 0. Note: Do not enable more than one of the following fields simultaneously: - sw_i - it_int - pda_en - mpr_en - (OFFSET, MASK, VALUE) (0XFD070010, 0x8000F03FU ,0x00000030U) - RegMask = (DDRC_MRCTRL0_MR_WR_MASK | DDRC_MRCTRL0_MR_ADDR_MASK | DDRC_MRCTRL0_MR_RANK_MASK | DDRC_MRCTRL0_SW_INIT_INT_MASK | DDRC_MRCTRL0_PDA_EN_MASK | DDRC_MRCTRL0_MPR_EN_MASK | DDRC_MRCTRL0_MR_TYPE_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_MRCTRL0_MR_WR_SHIFT - | 0x00000000U << DDRC_MRCTRL0_MR_ADDR_SHIFT - | 0x00000003U << DDRC_MRCTRL0_MR_RANK_SHIFT - | 0x00000000U << DDRC_MRCTRL0_SW_INIT_INT_SHIFT - | 0x00000000U << DDRC_MRCTRL0_PDA_EN_SHIFT - | 0x00000000U << DDRC_MRCTRL0_MPR_EN_SHIFT - | 0x00000000U << DDRC_MRCTRL0_MR_TYPE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_MRCTRL0_OFFSET ,0x8000F03FU ,0x00000030U); - /*############################################################################################################################ */ - - /*Register : DERATEEN @ 0XFD070020

- - Derate value of tRC for LPDDR4 - 0 - Derating uses +1. - 1 - Derating uses +2. - 2 - Derating uses +3. - 3 - Derating uses +4 - Present only in designs configured to support LPDDR4. The required number of cycles for derating can be determined by dividi - g 3.75ns by the core_ddrc_core_clk period, and rounding up the next integer. - PSU_DDRC_DERATEEN_RC_DERATE_VALUE 0x3 - - Derate byte Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4 Indicates which byte of the MRR data is used f - r derating. The maximum valid value depends on MEMC_DRAM_TOTAL_DATA_WIDTH. - PSU_DDRC_DERATEEN_DERATE_BYTE 0x0 - - Derate value - 0 - Derating uses +1. - 1 - Derating uses +2. Present only in designs configured to support LPDDR2/LPDDR3/LPDD - 4 Set to 0 for all LPDDR2 speed grades as derating value of +1.875 ns is less than a core_ddrc_core_clk period. Can be 0 or 1 - for LPDDR3/LPDDR4, depending if +1.875 ns is less than a core_ddrc_core_clk period or not. - PSU_DDRC_DERATEEN_DERATE_VALUE 0x0 - - Enables derating - 0 - Timing parameter derating is disabled - 1 - Timing parameter derating is enabled using MR4 read value. - Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4 This field must be set to '0' for non-LPDDR2/LPDDR3/LPDDR4 - mode. - PSU_DDRC_DERATEEN_DERATE_ENABLE 0x0 - - Temperature Derate Enable Register - (OFFSET, MASK, VALUE) (0XFD070020, 0x000003F3U ,0x00000300U) - RegMask = (DDRC_DERATEEN_RC_DERATE_VALUE_MASK | DDRC_DERATEEN_DERATE_BYTE_MASK | DDRC_DERATEEN_DERATE_VALUE_MASK | DDRC_DERATEEN_DERATE_ENABLE_MASK | 0 ); - - RegVal = ((0x00000003U << DDRC_DERATEEN_RC_DERATE_VALUE_SHIFT - | 0x00000000U << DDRC_DERATEEN_DERATE_BYTE_SHIFT - | 0x00000000U << DDRC_DERATEEN_DERATE_VALUE_SHIFT - | 0x00000000U << DDRC_DERATEEN_DERATE_ENABLE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DERATEEN_OFFSET ,0x000003F3U ,0x00000300U); - /*############################################################################################################################ */ - - /*Register : DERATEINT @ 0XFD070024

- - Interval between two MR4 reads, used to derate the timing parameters. Present only in designs configured to support LPDDR2/LP - DR3/LPDDR4. This register must not be set to zero - PSU_DDRC_DERATEINT_MR4_READ_INTERVAL 0x800000 - - Temperature Derate Interval Register - (OFFSET, MASK, VALUE) (0XFD070024, 0xFFFFFFFFU ,0x00800000U) - RegMask = (DDRC_DERATEINT_MR4_READ_INTERVAL_MASK | 0 ); - - RegVal = ((0x00800000U << DDRC_DERATEINT_MR4_READ_INTERVAL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DERATEINT_OFFSET ,0xFFFFFFFFU ,0x00800000U); - /*############################################################################################################################ */ - - /*Register : PWRCTL @ 0XFD070030

- - Self refresh state is an intermediate state to enter to Self refresh power down state or exit Self refresh power down state f - r LPDDR4. This register controls transition from the Self refresh state. - 1 - Prohibit transition from Self refresh state - - - Allow transition from Self refresh state - PSU_DDRC_PWRCTL_STAY_IN_SELFREF 0x0 - - A value of 1 to this register causes system to move to Self Refresh state immediately, as long as it is not in INIT or DPD/MP - M operating_mode. This is referred to as Software Entry/Exit to Self Refresh. - 1 - Software Entry to Self Refresh - 0 - Soft - are Exit from Self Refresh - PSU_DDRC_PWRCTL_SELFREF_SW 0x0 - - When this is 1, the uMCTL2 puts the SDRAM into maximum power saving mode when the transaction store is empty. This register m - st be reset to '0' to bring uMCTL2 out of maximum power saving mode. Present only in designs configured to support DDR4. For - on-DDR4, this register should not be set to 1. Note that MPSM is not supported when using a DWC DDR PHY, if the PHY parameter - DWC_AC_CS_USE is disabled, as the MPSM exit sequence requires the chip-select signal to toggle. FOR PERFORMANCE ONLY. - PSU_DDRC_PWRCTL_MPSM_EN 0x0 - - Enable the assertion of dfi_dram_clk_disable whenever a clock is not required by the SDRAM. If set to 0, dfi_dram_clk_disable - is never asserted. Assertion of dfi_dram_clk_disable is as follows: In DDR2/DDR3, can only be asserted in Self Refresh. In DD - 4, can be asserted in following: - in Self Refresh. - in Maximum Power Saving Mode In mDDR/LPDDR2/LPDDR3, can be asserted in - ollowing: - in Self Refresh - in Power Down - in Deep Power Down - during Normal operation (Clock Stop) In LPDDR4, can be ass - rted in following: - in Self Refresh Power Down - in Power Down - during Normal operation (Clock Stop) - PSU_DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE 0x0 - - When this is 1, uMCTL2 puts the SDRAM into deep power-down mode when the transaction store is empty. This register must be re - et to '0' to bring uMCTL2 out of deep power-down mode. Controller performs automatic SDRAM initialization on deep power-down - xit. Present only in designs configured to support mDDR or LPDDR2 or LPDDR3. For non-mDDR/non-LPDDR2/non-LPDDR3, this registe - should not be set to 1. FOR PERFORMANCE ONLY. - PSU_DDRC_PWRCTL_DEEPPOWERDOWN_EN 0x0 - - If true then the uMCTL2 goes into power-down after a programmable number of cycles 'maximum idle clocks before power down' (P - RTMG.powerdown_to_x32). This register bit may be re-programmed during the course of normal operation. - PSU_DDRC_PWRCTL_POWERDOWN_EN 0x0 - - If true then the uMCTL2 puts the SDRAM into Self Refresh after a programmable number of cycles 'maximum idle clocks before Se - f Refresh (PWRTMG.selfref_to_x32)'. This register bit may be re-programmed during the course of normal operation. - PSU_DDRC_PWRCTL_SELFREF_EN 0x0 - - Low Power Control Register - (OFFSET, MASK, VALUE) (0XFD070030, 0x0000007FU ,0x00000000U) - RegMask = (DDRC_PWRCTL_STAY_IN_SELFREF_MASK | DDRC_PWRCTL_SELFREF_SW_MASK | DDRC_PWRCTL_MPSM_EN_MASK | DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_MASK | DDRC_PWRCTL_DEEPPOWERDOWN_EN_MASK | DDRC_PWRCTL_POWERDOWN_EN_MASK | DDRC_PWRCTL_SELFREF_EN_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_PWRCTL_STAY_IN_SELFREF_SHIFT - | 0x00000000U << DDRC_PWRCTL_SELFREF_SW_SHIFT - | 0x00000000U << DDRC_PWRCTL_MPSM_EN_SHIFT - | 0x00000000U << DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_SHIFT - | 0x00000000U << DDRC_PWRCTL_DEEPPOWERDOWN_EN_SHIFT - | 0x00000000U << DDRC_PWRCTL_POWERDOWN_EN_SHIFT - | 0x00000000U << DDRC_PWRCTL_SELFREF_EN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PWRCTL_OFFSET ,0x0000007FU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : PWRTMG @ 0XFD070034

- - After this many clocks of NOP or deselect the uMCTL2 automatically puts the SDRAM into Self Refresh. This must be enabled in - he PWRCTL.selfref_en. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY. - PSU_DDRC_PWRTMG_SELFREF_TO_X32 0x40 - - Minimum deep power-down time. For mDDR, value from the JEDEC specification is 0 as mDDR exits from deep power-down mode immed - ately after PWRCTL.deeppowerdown_en is de-asserted. For LPDDR2/LPDDR3, value from the JEDEC specification is 500us. Unit: Mul - iples of 4096 clocks. Present only in designs configured to support mDDR, LPDDR2 or LPDDR3. FOR PERFORMANCE ONLY. - PSU_DDRC_PWRTMG_T_DPD_X4096 0x84 - - After this many clocks of NOP or deselect the uMCTL2 automatically puts the SDRAM into power-down. This must be enabled in th - PWRCTL.powerdown_en. Unit: Multiples of 32 clocks FOR PERFORMANCE ONLY. - PSU_DDRC_PWRTMG_POWERDOWN_TO_X32 0x10 - - Low Power Timing Register - (OFFSET, MASK, VALUE) (0XFD070034, 0x00FFFF1FU ,0x00408410U) - RegMask = (DDRC_PWRTMG_SELFREF_TO_X32_MASK | DDRC_PWRTMG_T_DPD_X4096_MASK | DDRC_PWRTMG_POWERDOWN_TO_X32_MASK | 0 ); - - RegVal = ((0x00000040U << DDRC_PWRTMG_SELFREF_TO_X32_SHIFT - | 0x00000084U << DDRC_PWRTMG_T_DPD_X4096_SHIFT - | 0x00000010U << DDRC_PWRTMG_POWERDOWN_TO_X32_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PWRTMG_OFFSET ,0x00FFFF1FU ,0x00408410U); - /*############################################################################################################################ */ - - /*Register : RFSHCTL0 @ 0XFD070050

- - Threshold value in number of clock cycles before the critical refresh or page timer expires. A critical refresh is to be issu - d before this threshold is reached. It is recommended that this not be changed from the default value, currently shown as 0x2 - It must always be less than internally used t_rfc_nom_x32. Note that, in LPDDR2/LPDDR3/LPDDR4, internally used t_rfc_nom_x32 - may be equal to RFSHTMG.t_rfc_nom_x32>>2 if derating is enabled (DERATEEN.derate_enable=1). Otherwise, internally used t_rfc_ - om_x32 will be equal to RFSHTMG.t_rfc_nom_x32. Unit: Multiples of 32 clocks. - PSU_DDRC_RFSHCTL0_REFRESH_MARGIN 0x2 - - If the refresh timer (tRFCnom, also known as tREFI) has expired at least once, but it has not expired (RFSHCTL0.refresh_burst - 1) times yet, then a speculative refresh may be performed. A speculative refresh is a refresh performed at a time when refres - would be useful, but before it is absolutely required. When the SDRAM bus is idle for a period of time determined by this RF - HCTL0.refresh_to_x32 and the refresh timer has expired at least once since the last refresh, then a speculative refresh is pe - formed. Speculative refreshes continues successively until there are no refreshes pending or until new reads or writes are is - ued to the uMCTL2. FOR PERFORMANCE ONLY. - PSU_DDRC_RFSHCTL0_REFRESH_TO_X32 0x10 - - The programmed value + 1 is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the re - reshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of re - reshes. Therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for - RFSHCTL.refresh_burst slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshe - . - 0 - single refresh - 1 - burst-of-2 refresh - 7 - burst-of-8 refresh For information on burst refresh feature refer to se - tion 3.9 of DDR2 JEDEC specification - JESD79-2F.pdf. For DDR2/3, the refresh is always per-rank and not per-bank. The rank r - fresh can be accumulated over 8*tREFI cycles using the burst refresh feature. In DDR4 mode, according to Fine Granularity fea - ure, 8 refreshes can be postponed in 1X mode, 16 refreshes in 2X mode and 32 refreshes in 4X mode. If using PHY-initiated upd - tes, care must be taken in the setting of RFSHCTL0.refresh_burst, to ensure that tRFCmax is not violated due to a PHY-initiat - d update occurring shortly before a refresh burst was due. In this situation, the refresh burst will be delayed until the PHY - initiated update is complete. - PSU_DDRC_RFSHCTL0_REFRESH_BURST 0x0 - - - 1 - Per bank refresh; - 0 - All bank refresh. Per bank refresh allows traffic to flow to other banks. Per bank refresh is n - t supported by all LPDDR2 devices but should be supported by all LPDDR3/LPDDR4 devices. Present only in designs configured to - support LPDDR2/LPDDR3/LPDDR4 - PSU_DDRC_RFSHCTL0_PER_BANK_REFRESH 0x0 - - Refresh Control Register 0 - (OFFSET, MASK, VALUE) (0XFD070050, 0x00F1F1F4U ,0x00210000U) - RegMask = (DDRC_RFSHCTL0_REFRESH_MARGIN_MASK | DDRC_RFSHCTL0_REFRESH_TO_X32_MASK | DDRC_RFSHCTL0_REFRESH_BURST_MASK | DDRC_RFSHCTL0_PER_BANK_REFRESH_MASK | 0 ); - - RegVal = ((0x00000002U << DDRC_RFSHCTL0_REFRESH_MARGIN_SHIFT - | 0x00000010U << DDRC_RFSHCTL0_REFRESH_TO_X32_SHIFT - | 0x00000000U << DDRC_RFSHCTL0_REFRESH_BURST_SHIFT - | 0x00000000U << DDRC_RFSHCTL0_PER_BANK_REFRESH_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_RFSHCTL0_OFFSET ,0x00F1F1F4U ,0x00210000U); - /*############################################################################################################################ */ - - /*Register : RFSHCTL3 @ 0XFD070060

- - Fine Granularity Refresh Mode - 000 - Fixed 1x (Normal mode) - 001 - Fixed 2x - 010 - Fixed 4x - 101 - Enable on the fly 2x ( - ot supported) - 110 - Enable on the fly 4x (not supported) - Everything else - reserved Note: The on-the-fly modes is not sup - orted in this version of the uMCTL2. Note: This must be set up while the Controller is in reset or while the Controller is in - self-refresh mode. Changing this during normal operation is not allowed. Making this a dynamic register will be supported in - uture version of the uMCTL2. - PSU_DDRC_RFSHCTL3_REFRESH_MODE 0x0 - - Toggle this signal (either from 0 to 1 or from 1 to 0) to indicate that the refresh register(s) have been updated. The value - s automatically updated when exiting reset, so it does not need to be toggled initially. - PSU_DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL 0x0 - - When '1', disable auto-refresh generated by the uMCTL2. When auto-refresh is disabled, the SoC core must generate refreshes u - ing the registers reg_ddrc_rank0_refresh, reg_ddrc_rank1_refresh, reg_ddrc_rank2_refresh and reg_ddrc_rank3_refresh. When dis - auto_refresh transitions from 0 to 1, any pending refreshes are immediately scheduled by the uMCTL2. If DDR4 CRC/parity retry - is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), disable auto-refresh is not supported, and this bit must be set to '0'. - his register field is changeable on the fly. - PSU_DDRC_RFSHCTL3_DIS_AUTO_REFRESH 0x1 - - Refresh Control Register 3 - (OFFSET, MASK, VALUE) (0XFD070060, 0x00000073U ,0x00000001U) - RegMask = (DDRC_RFSHCTL3_REFRESH_MODE_MASK | DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_MASK | DDRC_RFSHCTL3_DIS_AUTO_REFRESH_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_RFSHCTL3_REFRESH_MODE_SHIFT - | 0x00000000U << DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_SHIFT - | 0x00000001U << DDRC_RFSHCTL3_DIS_AUTO_REFRESH_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_RFSHCTL3_OFFSET ,0x00000073U ,0x00000001U); - /*############################################################################################################################ */ - - /*Register : RFSHTMG @ 0XFD070064

- - tREFI: Average time interval between refreshes per rank (Specification: 7.8us for DDR2, DDR3 and DDR4. See JEDEC specificatio - for mDDR, LPDDR2, LPDDR3 and LPDDR4). For LPDDR2/LPDDR3/LPDDR4: - if using all-bank refreshes (RFSHCTL0.per_bank_refresh = 0 - , this register should be set to tREFIab - if using per-bank refreshes (RFSHCTL0.per_bank_refresh = 1), this register should - e set to tREFIpb For configurations with MEMC_FREQ_RATIO=2, program this to (tREFI/2), no rounding up. In DDR4 mode, tREFI va - ue is different depending on the refresh mode. The user should program the appropriate value from the spec based on the value - programmed in the refresh mode register. Note that RFSHTMG.t_rfc_nom_x32 * 32 must be greater than RFSHTMG.t_rfc_min, and RFS - TMG.t_rfc_nom_x32 must be greater than 0x1. Unit: Multiples of 32 clocks. - PSU_DDRC_RFSHTMG_T_RFC_NOM_X32 0x82 - - Used only when LPDDR3 memory type is connected. Should only be changed when uMCTL2 is in reset. Specifies whether to use the - REFBW parameter (required by some LPDDR3 devices which comply with earlier versions of the LPDDR3 JEDEC specification) or not - - 0 - tREFBW parameter not used - 1 - tREFBW parameter used - PSU_DDRC_RFSHTMG_LPDDR3_TREFBW_EN 0x1 - - tRFC (min): Minimum time from refresh to refresh or activate. For MEMC_FREQ_RATIO=1 configurations, t_rfc_min should be set t - RoundUp(tRFCmin/tCK). For MEMC_FREQ_RATIO=2 configurations, t_rfc_min should be set to RoundUp(RoundUp(tRFCmin/tCK)/2). In L - DDR2/LPDDR3/LPDDR4 mode: - if using all-bank refreshes, the tRFCmin value in the above equations is equal to tRFCab - if usin - per-bank refreshes, the tRFCmin value in the above equations is equal to tRFCpb In DDR4 mode, the tRFCmin value in the above - equations is different depending on the refresh mode (fixed 1X,2X,4X) and the device density. The user should program the app - opriate value from the spec based on the 'refresh_mode' and the device density that is used. Unit: Clocks. - PSU_DDRC_RFSHTMG_T_RFC_MIN 0x8b - - Refresh Timing Register - (OFFSET, MASK, VALUE) (0XFD070064, 0x0FFF83FFU ,0x0082808BU) - RegMask = (DDRC_RFSHTMG_T_RFC_NOM_X32_MASK | DDRC_RFSHTMG_LPDDR3_TREFBW_EN_MASK | DDRC_RFSHTMG_T_RFC_MIN_MASK | 0 ); - - RegVal = ((0x00000082U << DDRC_RFSHTMG_T_RFC_NOM_X32_SHIFT - | 0x00000001U << DDRC_RFSHTMG_LPDDR3_TREFBW_EN_SHIFT - | 0x0000008BU << DDRC_RFSHTMG_T_RFC_MIN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_RFSHTMG_OFFSET ,0x0FFF83FFU ,0x0082808BU); - /*############################################################################################################################ */ - - /*Register : ECCCFG0 @ 0XFD070070

- - Disable ECC scrubs. Valid only when ECCCFG0.ecc_mode = 3'b100 and MEMC_USE_RMW is defined - PSU_DDRC_ECCCFG0_DIS_SCRUB 0x1 - - ECC mode indicator - 000 - ECC disabled - 100 - ECC enabled - SEC/DED over 1 beat - all other settings are reserved for futur - use - PSU_DDRC_ECCCFG0_ECC_MODE 0x0 - - ECC Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD070070, 0x00000017U ,0x00000010U) - RegMask = (DDRC_ECCCFG0_DIS_SCRUB_MASK | DDRC_ECCCFG0_ECC_MODE_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_ECCCFG0_DIS_SCRUB_SHIFT - | 0x00000000U << DDRC_ECCCFG0_ECC_MODE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_ECCCFG0_OFFSET ,0x00000017U ,0x00000010U); - /*############################################################################################################################ */ - - /*Register : ECCCFG1 @ 0XFD070074

- - Selects whether to poison 1 or 2 bits - if 0 -> 2-bit (uncorrectable) data poisoning, if 1 -> 1-bit (correctable) data poison - ng, if ECCCFG1.data_poison_en=1 - PSU_DDRC_ECCCFG1_DATA_POISON_BIT 0x0 - - Enable ECC data poisoning - introduces ECC errors on writes to address specified by the ECCPOISONADDR0/1 registers - PSU_DDRC_ECCCFG1_DATA_POISON_EN 0x0 - - ECC Configuration Register 1 - (OFFSET, MASK, VALUE) (0XFD070074, 0x00000003U ,0x00000000U) - RegMask = (DDRC_ECCCFG1_DATA_POISON_BIT_MASK | DDRC_ECCCFG1_DATA_POISON_EN_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_ECCCFG1_DATA_POISON_BIT_SHIFT - | 0x00000000U << DDRC_ECCCFG1_DATA_POISON_EN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_ECCCFG1_OFFSET ,0x00000003U ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : CRCPARCTL1 @ 0XFD0700C4

- - The maximum number of DFI PHY clock cycles allowed from the assertion of the dfi_rddata_en signal to the assertion of each of - the corresponding bits of the dfi_rddata_valid signal. This corresponds to the DFI timing parameter tphy_rdlat. Refer to PHY - pecification for correct value. This value it only used for detecting read data timeout when DDR4 retry is enabled by CRCPARC - L1.crc_parity_retry_enable=1. Maximum supported value: - 1:1 Frequency mode : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_ - dlat < 'd114 - 1:2 Frequency mode ANDAND DFITMG0.dfi_rddata_use_sdr == 1 : CRCPARCTL1.dfi_t_phy_rdlat < 64 - 1:2 Frequency mo - e ANDAND DFITMG0.dfi_rddata_use_sdr == 0 : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_rdlat < 'd114 Unit: DFI Clocks - PSU_DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT 0x10 - - After a Parity or CRC error is flagged on dfi_alert_n signal, the software has an option to read the mode registers in the DR - M before the hardware begins the retry process - 1: Wait for software to read/write the mode registers before hardware begins - the retry. After software is done with its operations, it will clear the alert interrupt register bit - 0: Hardware can begin - the retry right away after the dfi_alert_n pulse goes away. The value on this register is valid only when retry is enabled (P - RCTRL.crc_parity_retry_enable = 1) If this register is set to 1 and if the software doesn't clear the interrupt register afte - handling the parity/CRC error, then the hardware will not begin the retry process and the system will hang. In the case of P - rity/CRC error, there are two possibilities when the software doesn't reset MR5[4] to 0. - (i) If 'Persistent parity' mode re - ister bit is NOT set: the commands sent during retry and normal operation are executed without parity checking. The value in - he Parity error log register MPR Page 1 is valid. - (ii) If 'Persistent parity' mode register bit is SET: Parity checking is - one for commands sent during retry and normal operation. If multiple errors occur before MR5[4] is cleared, the error log in - PR Page 1 should be treated as 'Don't care'. - PSU_DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW 0x1 - - - 1: Enable command retry mechanism in case of C/A Parity or CRC error - 0: Disable command retry mechanism when C/A Parity o - CRC features are enabled. Note that retry functionality is not supported if burst chop is enabled (MSTR.burstchop = 1) and/o - disable auto-refresh is enabled (RFSHCTL3.dis_auto_refresh = 1) - PSU_DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE 0x0 - - CRC Calculation setting register - 1: CRC includes DM signal - 0: CRC not includes DM signal Present only in designs configur - d to support DDR4. - PSU_DDRC_CRCPARCTL1_CRC_INC_DM 0x0 - - CRC enable Register - 1: Enable generation of CRC - 0: Disable generation of CRC The setting of this register should match th - CRC mode register setting in the DRAM. - PSU_DDRC_CRCPARCTL1_CRC_ENABLE 0x0 - - C/A Parity enable register - 1: Enable generation of C/A parity and detection of C/A parity error - 0: Disable generation of - /A parity and disable detection of C/A parity error If RCD's parity error detection or SDRAM's parity detection is enabled, t - is register should be 1. - PSU_DDRC_CRCPARCTL1_PARITY_ENABLE 0x0 - - CRC Parity Control Register1 - (OFFSET, MASK, VALUE) (0XFD0700C4, 0x3F000391U ,0x10000200U) - RegMask = (DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_MASK | DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_MASK | DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_MASK | DDRC_CRCPARCTL1_CRC_INC_DM_MASK | DDRC_CRCPARCTL1_CRC_ENABLE_MASK | DDRC_CRCPARCTL1_PARITY_ENABLE_MASK | 0 ); - - RegVal = ((0x00000010U << DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_SHIFT - | 0x00000001U << DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_SHIFT - | 0x00000000U << DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_SHIFT - | 0x00000000U << DDRC_CRCPARCTL1_CRC_INC_DM_SHIFT - | 0x00000000U << DDRC_CRCPARCTL1_CRC_ENABLE_SHIFT - | 0x00000000U << DDRC_CRCPARCTL1_PARITY_ENABLE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_CRCPARCTL1_OFFSET ,0x3F000391U ,0x10000200U); - /*############################################################################################################################ */ - - /*Register : CRCPARCTL2 @ 0XFD0700C8

- - Value from the DRAM spec indicating the maximum width of the dfi_alert_n pulse when a parity error occurs. Recommended values - - tPAR_ALERT_PW.MAX For configurations with MEMC_FREQ_RATIO=2, program this to tPAR_ALERT_PW.MAX/2 and round up to next inte - er value. Values of 0, 1 and 2 are illegal. This value must be greater than CRCPARCTL2.t_crc_alert_pw_max. - PSU_DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX 0x40 - - Value from the DRAM spec indicating the maximum width of the dfi_alert_n pulse when a CRC error occurs. Recommended values: - - tCRC_ALERT_PW.MAX For configurations with MEMC_FREQ_RATIO=2, program this to tCRC_ALERT_PW.MAX/2 and round up to next integer - value. Values of 0, 1 and 2 are illegal. This value must be less than CRCPARCTL2.t_par_alert_pw_max. - PSU_DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX 0x5 - - Indicates the maximum duration in number of DRAM clock cycles for which a command should be held in the Command Retry FIFO be - ore it is popped out. Every location in the Command Retry FIFO has an associated down counting timer that will use this regis - er as the start value. The down counting starts when a command is loaded into the FIFO. The timer counts down every 4 DRAM cy - les. When the counter reaches zero, the entry is popped from the FIFO. All the counters are frozen, if a C/A Parity or CRC er - or occurs before the counter reaches zero. The counter is reset to 0, after all the commands in the FIFO are retried. Recomme - ded(minimum) values: - Only C/A Parity is enabled. RoundUp((PHY Command Latency(DRAM CLK) + CAL + RDIMM delay + tPAR_ALERT_ON - max + tPAR_UNKNOWN + PHY Alert Latency(DRAM CLK) + board delay) / 4) + 2 - Both C/A Parity and CRC is enabled/ Only CRC is en - bled. RoundUp((PHY Command Latency(DRAM CLK) + CAL + RDIMM delay + WL + 5(BL10)+ tCRC_ALERT.max + PHY Alert Latency(DRAM CLK) - + board delay) / 4) + 2 Note 1: All value (e.g. tPAR_ALERT_ON) should be in terms of DRAM Clock and round up Note 2: Board de - ay(Command/Alert_n) should be considered. Note 3: Use the worst case(longer) value for PHY Latencies/Board delay Note 4: The - ecommended values are minimum value to be set. For mode detail, See 'Calculation of FIFO Depth' section. Max value can be set - to this register is defined below: - MEMC_BURST_LENGTH == 16 Full bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH- - Full bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Half bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_D - PTH-4 Half bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-6 Quarter bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CM - _FIFO_DEPTH-8 Quarter bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-12 - MEMC_BURST_LENGTH != 16 Full bus Mode (C - C=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-1 Full bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mo - e (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Quarte - bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-4 Quarter bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEP - H-6 Values of 0, 1 and 2 are illegal. - PSU_DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4 0x1f - - CRC Parity Control Register2 - (OFFSET, MASK, VALUE) (0XFD0700C8, 0x01FF1F3FU ,0x0040051FU) - RegMask = (DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_MASK | DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_MASK | DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_MASK | 0 ); - - RegVal = ((0x00000040U << DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_SHIFT - | 0x00000005U << DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_SHIFT - | 0x0000001FU << DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_CRCPARCTL2_OFFSET ,0x01FF1F3FU ,0x0040051FU); - /*############################################################################################################################ */ - - /*Register : INIT0 @ 0XFD0700D0

- - If lower bit is enabled the SDRAM initialization routine is skipped. The upper bit decides what state the controller starts u - in when reset is removed - 00 - SDRAM Intialization routine is run after power-up - 01 - SDRAM Intialization routine is skip - ed after power-up. Controller starts up in Normal Mode - 11 - SDRAM Intialization routine is skipped after power-up. Controll - r starts up in Self-refresh Mode - 10 - SDRAM Intialization routine is run after power-up. Note: The only 2'b00 is supported - or LPDDR4 in this version of the uMCTL2. - PSU_DDRC_INIT0_SKIP_DRAM_INIT 0x0 - - Cycles to wait after driving CKE high to start the SDRAM initialization sequence. Unit: 1024 clocks. DDR2 typically requires - 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2/LPDDR3 typically requires this to be pr - grammed for a delay of 200 us. LPDDR4 typically requires this to be programmed for a delay of 2 us. For configurations with M - MC_FREQ_RATIO=2, program this to JEDEC spec value divided by 2, and round it up to next integer value. - PSU_DDRC_INIT0_POST_CKE_X1024 0x2 - - Cycles to wait after reset before driving CKE high to start the SDRAM initialization sequence. Unit: 1024 clock cycles. DDR2 - pecifications typically require this to be programmed for a delay of >= 200 us. LPDDR2/LPDDR3: tINIT1 of 100 ns (min) LPDDR4: - tINIT3 of 2 ms (min) For configurations with MEMC_FREQ_RATIO=2, program this to JEDEC spec value divided by 2, and round it u - to next integer value. - PSU_DDRC_INIT0_PRE_CKE_X1024 0x106 - - SDRAM Initialization Register 0 - (OFFSET, MASK, VALUE) (0XFD0700D0, 0xC3FF0FFFU ,0x00020106U) - RegMask = (DDRC_INIT0_SKIP_DRAM_INIT_MASK | DDRC_INIT0_POST_CKE_X1024_MASK | DDRC_INIT0_PRE_CKE_X1024_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_INIT0_SKIP_DRAM_INIT_SHIFT - | 0x00000002U << DDRC_INIT0_POST_CKE_X1024_SHIFT - | 0x00000106U << DDRC_INIT0_PRE_CKE_X1024_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_INIT0_OFFSET ,0xC3FF0FFFU ,0x00020106U); - /*############################################################################################################################ */ - - /*Register : INIT1 @ 0XFD0700D4

- - Number of cycles to assert SDRAM reset signal during init sequence. This is only present for designs supporting DDR3, DDR4 or - LPDDR4 devices. For use with a DDR PHY, this should be set to a minimum of 1 - PSU_DDRC_INIT1_DRAM_RSTN_X1024 0x2 - - Cycles to wait after completing the SDRAM initialization sequence before starting the dynamic scheduler. Unit: Counts of a gl - bal timer that pulses every 32 clock cycles. There is no known specific requirement for this; it may be set to zero. - PSU_DDRC_INIT1_FINAL_WAIT_X32 0x0 - - Wait period before driving the OCD complete command to SDRAM. Unit: Counts of a global timer that pulses every 32 clock cycle - . There is no known specific requirement for this; it may be set to zero. - PSU_DDRC_INIT1_PRE_OCD_X32 0x0 - - SDRAM Initialization Register 1 - (OFFSET, MASK, VALUE) (0XFD0700D4, 0x01FF7F0FU ,0x00020000U) - RegMask = (DDRC_INIT1_DRAM_RSTN_X1024_MASK | DDRC_INIT1_FINAL_WAIT_X32_MASK | DDRC_INIT1_PRE_OCD_X32_MASK | 0 ); - - RegVal = ((0x00000002U << DDRC_INIT1_DRAM_RSTN_X1024_SHIFT - | 0x00000000U << DDRC_INIT1_FINAL_WAIT_X32_SHIFT - | 0x00000000U << DDRC_INIT1_PRE_OCD_X32_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_INIT1_OFFSET ,0x01FF7F0FU ,0x00020000U); - /*############################################################################################################################ */ - - /*Register : INIT2 @ 0XFD0700D8

- - Idle time after the reset command, tINIT4. Present only in designs configured to support LPDDR2. Unit: 32 clock cycles. - PSU_DDRC_INIT2_IDLE_AFTER_RESET_X32 0x23 - - Time to wait after the first CKE high, tINIT2. Present only in designs configured to support LPDDR2/LPDDR3. Unit: 1 clock cyc - e. LPDDR2/LPDDR3 typically requires 5 x tCK delay. - PSU_DDRC_INIT2_MIN_STABLE_CLOCK_X1 0x5 - - SDRAM Initialization Register 2 - (OFFSET, MASK, VALUE) (0XFD0700D8, 0x0000FF0FU ,0x00002305U) - RegMask = (DDRC_INIT2_IDLE_AFTER_RESET_X32_MASK | DDRC_INIT2_MIN_STABLE_CLOCK_X1_MASK | 0 ); - - RegVal = ((0x00000023U << DDRC_INIT2_IDLE_AFTER_RESET_X32_SHIFT - | 0x00000005U << DDRC_INIT2_MIN_STABLE_CLOCK_X1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_INIT2_OFFSET ,0x0000FF0FU ,0x00002305U); - /*############################################################################################################################ */ - - /*Register : INIT3 @ 0XFD0700DC

- - DDR2: Value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The uMCTL2 sets this bit appropriately - DDR3/DDR4: Value loaded into MR0 register. mDDR: Value to write to MR register. LPDDR2/LPDDR3/LPDDR4 - Value to write to MR1 - register - PSU_DDRC_INIT3_MR 0x930 - - DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setting in this register is ignored. The uMCTL2 sets those - bits appropriately. DDR3/DDR4: Value to write to MR1 register Set bit 7 to 0. If PHY-evaluation mode training is enabled, thi - bit is set appropriately by the uMCTL2 during write leveling. mDDR: Value to write to EMR register. LPDDR2/LPDDR3/LPDDR4 - V - lue to write to MR2 register - PSU_DDRC_INIT3_EMR 0x301 - - SDRAM Initialization Register 3 - (OFFSET, MASK, VALUE) (0XFD0700DC, 0xFFFFFFFFU ,0x09300301U) - RegMask = (DDRC_INIT3_MR_MASK | DDRC_INIT3_EMR_MASK | 0 ); - - RegVal = ((0x00000930U << DDRC_INIT3_MR_SHIFT - | 0x00000301U << DDRC_INIT3_EMR_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_INIT3_OFFSET ,0xFFFFFFFFU ,0x09300301U); - /*############################################################################################################################ */ - - /*Register : INIT4 @ 0XFD0700E0

- - DDR2: Value to write to EMR2 register. DDR3/DDR4: Value to write to MR2 register LPDDR2/LPDDR3/LPDDR4: Value to write to MR3 - egister mDDR: Unused - PSU_DDRC_INIT4_EMR2 0x20 - - DDR2: Value to write to EMR3 register. DDR3/DDR4: Value to write to MR3 register mDDR/LPDDR2/LPDDR3: Unused LPDDR4: Value to - rite to MR13 register - PSU_DDRC_INIT4_EMR3 0x200 - - SDRAM Initialization Register 4 - (OFFSET, MASK, VALUE) (0XFD0700E0, 0xFFFFFFFFU ,0x00200200U) - RegMask = (DDRC_INIT4_EMR2_MASK | DDRC_INIT4_EMR3_MASK | 0 ); - - RegVal = ((0x00000020U << DDRC_INIT4_EMR2_SHIFT - | 0x00000200U << DDRC_INIT4_EMR3_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_INIT4_OFFSET ,0xFFFFFFFFU ,0x00200200U); - /*############################################################################################################################ */ - - /*Register : INIT5 @ 0XFD0700E4

- - ZQ initial calibration, tZQINIT. Present only in designs configured to support DDR3 or DDR4 or LPDDR2/LPDDR3. Unit: 32 clock - ycles. DDR3 typically requires 512 clocks. DDR4 requires 1024 clocks. LPDDR2/LPDDR3 requires 1 us. - PSU_DDRC_INIT5_DEV_ZQINIT_X32 0x21 - - Maximum duration of the auto initialization, tINIT5. Present only in designs configured to support LPDDR2/LPDDR3. LPDDR2/LPDD - 3 typically requires 10 us. - PSU_DDRC_INIT5_MAX_AUTO_INIT_X1024 0x4 - - SDRAM Initialization Register 5 - (OFFSET, MASK, VALUE) (0XFD0700E4, 0x00FF03FFU ,0x00210004U) - RegMask = (DDRC_INIT5_DEV_ZQINIT_X32_MASK | DDRC_INIT5_MAX_AUTO_INIT_X1024_MASK | 0 ); - - RegVal = ((0x00000021U << DDRC_INIT5_DEV_ZQINIT_X32_SHIFT - | 0x00000004U << DDRC_INIT5_MAX_AUTO_INIT_X1024_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_INIT5_OFFSET ,0x00FF03FFU ,0x00210004U); - /*############################################################################################################################ */ - - /*Register : INIT6 @ 0XFD0700E8

- - DDR4- Value to be loaded into SDRAM MR4 registers. Used in DDR4 designs only. - PSU_DDRC_INIT6_MR4 0x0 - - DDR4- Value to be loaded into SDRAM MR5 registers. Used in DDR4 designs only. - PSU_DDRC_INIT6_MR5 0x6c0 - - SDRAM Initialization Register 6 - (OFFSET, MASK, VALUE) (0XFD0700E8, 0xFFFFFFFFU ,0x000006C0U) - RegMask = (DDRC_INIT6_MR4_MASK | DDRC_INIT6_MR5_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_INIT6_MR4_SHIFT - | 0x000006C0U << DDRC_INIT6_MR5_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_INIT6_OFFSET ,0xFFFFFFFFU ,0x000006C0U); - /*############################################################################################################################ */ - - /*Register : INIT7 @ 0XFD0700EC

- - DDR4- Value to be loaded into SDRAM MR6 registers. Used in DDR4 designs only. - PSU_DDRC_INIT7_MR6 0x819 - - SDRAM Initialization Register 7 - (OFFSET, MASK, VALUE) (0XFD0700EC, 0xFFFF0000U ,0x08190000U) - RegMask = (DDRC_INIT7_MR6_MASK | 0 ); - - RegVal = ((0x00000819U << DDRC_INIT7_MR6_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_INIT7_OFFSET ,0xFFFF0000U ,0x08190000U); - /*############################################################################################################################ */ - - /*Register : DIMMCTL @ 0XFD0700F0

- - Disabling Address Mirroring for BG bits. When this is set to 1, BG0 and BG1 are NOT swapped even if Address Mirroring is enab - ed. This will be required for DDR4 DIMMs with x16 devices. - 1 - BG0 and BG1 are NOT swapped. - 0 - BG0 and BG1 are swapped i - address mirroring is enabled. - PSU_DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING 0x0 - - Enable for BG1 bit of MRS command. BG1 bit of the mode register address is specified as RFU (Reserved for Future Use) and mus - be programmed to 0 during MRS. In case where DRAMs which do not have BG1 are attached and both the CA parity and the Output - nversion are enabled, this must be set to 0, so that the calculation of CA parity will not include BG1 bit. Note: This has no - effect on the address of any other memory accesses, or of software-driven mode register accesses. If address mirroring is ena - led, this is applied to BG1 of even ranks and BG0 of odd ranks. - 1 - Enabled - 0 - Disabled - PSU_DDRC_DIMMCTL_MRS_BG1_EN 0x1 - - Enable for A17 bit of MRS command. A17 bit of the mode register address is specified as RFU (Reserved for Future Use) and mus - be programmed to 0 during MRS. In case where DRAMs which do not have A17 are attached and the Output Inversion are enabled, - his must be set to 0, so that the calculation of CA parity will not include A17 bit. Note: This has no effect on the address - f any other memory accesses, or of software-driven mode register accesses. - 1 - Enabled - 0 - Disabled - PSU_DDRC_DIMMCTL_MRS_A17_EN 0x0 - - Output Inversion Enable (for DDR4 RDIMM implementations only). DDR4 RDIMM implements the Output Inversion feature by default, - which means that the following address, bank address and bank group bits of B-side DRAMs are inverted: A3-A9, A11, A13, A17, - A0-BA1, BG0-BG1. Setting this bit ensures that, for mode register accesses generated by the uMCTL2 during the automatic initi - lization routine and enabling of a particular DDR4 feature, separate A-side and B-side mode register accesses are generated. - or B-side mode register accesses, these bits are inverted within the uMCTL2 to compensate for this RDIMM inversion. Note: Thi - has no effect on the address of any other memory accesses, or of software-driven mode register accesses. - 1 - Implement out - ut inversion for B-side DRAMs. - 0 - Do not implement output inversion for B-side DRAMs. - PSU_DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN 0x0 - - Address Mirroring Enable (for multi-rank UDIMM implementations and multi-rank DDR4 RDIMM implementations). Some UDIMMs and DD - 4 RDIMMs implement address mirroring for odd ranks, which means that the following address, bank address and bank group bits - re swapped: (A3, A4), (A5, A6), (A7, A8), (BA0, BA1) and also (A11, A13), (BG0, BG1) for the DDR4. Setting this bit ensures t - at, for mode register accesses during the automatic initialization routine, these bits are swapped within the uMCTL2 to compe - sate for this UDIMM/RDIMM swapping. In addition to the automatic initialization routine, in case of DDR4 UDIMM/RDIMM, they ar - swapped during the automatic MRS access to enable/disable of a particular DDR4 feature. Note: This has no effect on the addr - ss of any other memory accesses, or of software-driven mode register accesses. This is not supported for mDDR, LPDDR2, LPDDR3 - or LPDDR4 SDRAMs. Note: In case of x16 DDR4 DIMMs, BG1 output of MRS for the odd ranks is same as BG0 because BG1 is invalid, - hence dimm_dis_bg_mirroring register must be set to 1. - 1 - For odd ranks, implement address mirroring for MRS commands to d - ring initialization and for any automatic DDR4 MRS commands (to be used if UDIMM/RDIMM implements address mirroring) - 0 - Do - not implement address mirroring - PSU_DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN 0x0 - - Staggering enable for multi-rank accesses (for multi-rank UDIMM and RDIMM implementations only). This is not supported for mD - R, LPDDR2, LPDDR3 or LPDDR4 SDRAMs. Note: Even if this bit is set it does not take care of software driven MR commands (via M - CTRL0/MRCTRL1), where software is responsible to send them to seperate ranks as appropriate. - 1 - (DDR4) Send MRS commands t - each ranks seperately - 1 - (non-DDR4) Send all commands to even and odd ranks seperately - 0 - Do not stagger accesses - PSU_DDRC_DIMMCTL_DIMM_STAGGER_CS_EN 0x0 - - DIMM Control Register - (OFFSET, MASK, VALUE) (0XFD0700F0, 0x0000003FU ,0x00000010U) - RegMask = (DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_MASK | DDRC_DIMMCTL_MRS_BG1_EN_MASK | DDRC_DIMMCTL_MRS_A17_EN_MASK | DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_MASK | DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_MASK | DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_SHIFT - | 0x00000001U << DDRC_DIMMCTL_MRS_BG1_EN_SHIFT - | 0x00000000U << DDRC_DIMMCTL_MRS_A17_EN_SHIFT - | 0x00000000U << DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_SHIFT - | 0x00000000U << DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_SHIFT - | 0x00000000U << DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DIMMCTL_OFFSET ,0x0000003FU ,0x00000010U); - /*############################################################################################################################ */ - - /*Register : RANKCTL @ 0XFD0700F4

- - Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecuti - e writes to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This value should c - nsider both PHY requirement and ODT requirement. - PHY requirement: tphy_wrcsgap + 1 (see PHY databook for value of tphy_wrcs - ap) If CRC feature is enabled, should be increased by 1. If write preamble is set to 2tCK(DDR4/LPDDR4 only), should be increa - ed by 1. If write postamble is set to 1.5tCK(LPDDR4 only), should be increased by 1. - ODT requirement: The value programmed - n this register takes care of the ODT switch off timing requirement when switching ranks during writes. For LPDDR4, the requi - ement is ODTLoff - ODTLon - BL/2 + 1 For configurations with MEMC_FREQ_RATIO=1, program this to the larger of PHY requirement - or ODT requirement. For configurations with MEMC_FREQ_RATIO=2, program this to the larger value divided by two and round it u - to the next integer. - PSU_DDRC_RANKCTL_DIFF_RANK_WR_GAP 0x6 - - Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecuti - e reads to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This value should co - sider both PHY requirement and ODT requirement. - PHY requirement: tphy_rdcsgap + 1 (see PHY databook for value of tphy_rdcsg - p) If read preamble is set to 2tCK(DDR4/LPDDR4 only), should be increased by 1. If read postamble is set to 1.5tCK(LPDDR4 onl - ), should be increased by 1. - ODT requirement: The value programmed in this register takes care of the ODT switch off timing - requirement when switching ranks during reads. For configurations with MEMC_FREQ_RATIO=1, program this to the larger of PHY r - quirement or ODT requirement. For configurations with MEMC_FREQ_RATIO=2, program this to the larger value divided by two and - ound it up to the next integer. - PSU_DDRC_RANKCTL_DIFF_RANK_RD_GAP 0x6 - - Only present for multi-rank configurations. Background: Reads to the same rank can be performed back-to-back. Reads to differ - nt ranks require additional gap dictated by the register RANKCTL.diff_rank_rd_gap. This is to avoid possible data bus content - on as well as to give PHY enough time to switch the delay when changing ranks. The uMCTL2 arbitrates for bus access on a cycl - -by-cycle basis; therefore after a read is scheduled, there are few clock cycles (determined by the value on RANKCTL.diff_ran - _rd_gap register) in which only reads from the same rank are eligible to be scheduled. This prevents reads from other ranks f - om having fair access to the data bus. This parameter represents the maximum number of reads that can be scheduled consecutiv - ly to the same rank. After this number is reached, a delay equal to RANKCTL.diff_rank_rd_gap is inserted by the scheduler to - llow all ranks a fair opportunity to be scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fair - ess. This feature can be DISABLED by setting this register to 0. When set to 0, the Controller will stay on the same rank as - ong as commands are available for it. Minimum programmable value is 0 (feature disabled) and maximum programmable value is 0x - . FOR PERFORMANCE ONLY. - PSU_DDRC_RANKCTL_MAX_RANK_RD 0xf - - Rank Control Register - (OFFSET, MASK, VALUE) (0XFD0700F4, 0x00000FFFU ,0x0000066FU) - RegMask = (DDRC_RANKCTL_DIFF_RANK_WR_GAP_MASK | DDRC_RANKCTL_DIFF_RANK_RD_GAP_MASK | DDRC_RANKCTL_MAX_RANK_RD_MASK | 0 ); - - RegVal = ((0x00000006U << DDRC_RANKCTL_DIFF_RANK_WR_GAP_SHIFT - | 0x00000006U << DDRC_RANKCTL_DIFF_RANK_RD_GAP_SHIFT - | 0x0000000FU << DDRC_RANKCTL_MAX_RANK_RD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_RANKCTL_OFFSET ,0x00000FFFU ,0x0000066FU); - /*############################################################################################################################ */ - - /*Register : DRAMTMG0 @ 0XFD070100

- - Minimum time between write and precharge to same bank. Unit: Clocks Specifications: WL + BL/2 + tWR = approximately 8 cycles - 15 ns = 14 clocks @400MHz and less for lower frequencies where: - WL = write latency - BL = burst length. This must match th - value programmed in the BL bit of the mode register to the SDRAM. BST (burst terminate) is not supported at present. - tWR = - Write recovery time. This comes directly from the SDRAM specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 for this - arameter. For configurations with MEMC_FREQ_RATIO=2, 1T mode, divide the above value by 2. No rounding up. For configurations - with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, divide the above value by 2 and round it up to the next integer value. - PSU_DDRC_DRAMTMG0_WR2PRE 0x11 - - tFAW Valid only when 8 or more banks(or banks x bank groups) are present. In 8-bank design, at most 4 banks must be activated - in a rolling window of tFAW cycles. For configurations with MEMC_FREQ_RATIO=2, program this to (tFAW/2) and round up to next - nteger value. In a 4-bank design, set this register to 0x1 independent of the MEMC_FREQ_RATIO configuration. Unit: Clocks - PSU_DDRC_DRAMTMG0_T_FAW 0xc - - tRAS(max): Maximum time between activate and precharge to same bank. This is the maximum time that a page can be kept open Mi - imum value of this register is 1. Zero is invalid. For configurations with MEMC_FREQ_RATIO=2, program this to (tRAS(max)-1)/2 - No rounding up. Unit: Multiples of 1024 clocks. - PSU_DDRC_DRAMTMG0_T_RAS_MAX 0x24 - - tRAS(min): Minimum time between activate and precharge to the same bank. For configurations with MEMC_FREQ_RATIO=2, 1T mode, - rogram this to tRAS(min)/2. No rounding up. For configurations with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, program this t - (tRAS(min)/2) and round it up to the next integer value. Unit: Clocks - PSU_DDRC_DRAMTMG0_T_RAS_MIN 0x12 - - SDRAM Timing Register 0 - (OFFSET, MASK, VALUE) (0XFD070100, 0x7F3F7F3FU ,0x110C2412U) - RegMask = (DDRC_DRAMTMG0_WR2PRE_MASK | DDRC_DRAMTMG0_T_FAW_MASK | DDRC_DRAMTMG0_T_RAS_MAX_MASK | DDRC_DRAMTMG0_T_RAS_MIN_MASK | 0 ); - - RegVal = ((0x00000011U << DDRC_DRAMTMG0_WR2PRE_SHIFT - | 0x0000000CU << DDRC_DRAMTMG0_T_FAW_SHIFT - | 0x00000024U << DDRC_DRAMTMG0_T_RAS_MAX_SHIFT - | 0x00000012U << DDRC_DRAMTMG0_T_RAS_MIN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DRAMTMG0_OFFSET ,0x7F3F7F3FU ,0x110C2412U); - /*############################################################################################################################ */ - - /*Register : DRAMTMG1 @ 0XFD070104

- - tXP: Minimum time after power-down exit to any operation. For DDR3, this should be programmed to tXPDLL if slow powerdown exi - is selected in MR0[12]. If C/A parity for DDR4 is used, set to (tXP+PL) instead. For configurations with MEMC_FREQ_RATIO=2, - rogram this to (tXP/2) and round it up to the next integer value. Units: Clocks - PSU_DDRC_DRAMTMG1_T_XP 0x4 - - tRTP: Minimum time from read to precharge of same bank. - DDR2: tAL + BL/2 + max(tRTP, 2) - 2 - DDR3: tAL + max (tRTP, 4) - D - R4: Max of following two equations: tAL + max (tRTP, 4) or, RL + BL/2 - tRP. - mDDR: BL/2 - LPDDR2: Depends on if it's LPDDR2 - S2 or LPDDR2-S4: LPDDR2-S2: BL/2 + tRTP - 1. LPDDR2-S4: BL/2 + max(tRTP,2) - 2. - LPDDR3: BL/2 + max(tRTP,4) - 4 - LPDDR4: BL - 2 + max(tRTP,8) - 8 For configurations with MEMC_FREQ_RATIO=2, 1T mode, divide the above value by 2. No rounding up. For conf - gurations with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, divide the above value by 2 and round it up to the next integer val - e. Unit: Clocks. - PSU_DDRC_DRAMTMG1_RD2PRE 0x4 - - tRC: Minimum time between activates to same bank. For configurations with MEMC_FREQ_RATIO=2, program this to (tRC/2) and roun - up to next integer value. Unit: Clocks. - PSU_DDRC_DRAMTMG1_T_RC 0x19 - - SDRAM Timing Register 1 - (OFFSET, MASK, VALUE) (0XFD070104, 0x001F1F7FU ,0x00040419U) - RegMask = (DDRC_DRAMTMG1_T_XP_MASK | DDRC_DRAMTMG1_RD2PRE_MASK | DDRC_DRAMTMG1_T_RC_MASK | 0 ); - - RegVal = ((0x00000004U << DDRC_DRAMTMG1_T_XP_SHIFT - | 0x00000004U << DDRC_DRAMTMG1_RD2PRE_SHIFT - | 0x00000019U << DDRC_DRAMTMG1_T_RC_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DRAMTMG1_OFFSET ,0x001F1F7FU ,0x00040419U); - /*############################################################################################################################ */ - - /*Register : DRAMTMG2 @ 0XFD070108

- - Set to WL Time from write command to write data on SDRAM interface. This must be set to WL. For mDDR, it should normally be s - t to 1. Note that, depending on the PHY, if using RDIMM, it may be necessary to use a value of WL + 1 to compensate for the e - tra cycle of latency through the RDIMM For configurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above - equation by 2, and round it up to next integer. This register field is not required for DDR2 and DDR3 (except if MEMC_TRAININ - is set), as the DFI read and write latencies defined in DFITMG0 and DFITMG1 are sufficient for those protocols Unit: clocks - PSU_DDRC_DRAMTMG2_WRITE_LATENCY 0x7 - - Set to RL Time from read command to read data on SDRAM interface. This must be set to RL. Note that, depending on the PHY, if - using RDIMM, it mat be necessary to use a value of RL + 1 to compensate for the extra cycle of latency through the RDIMM For - onfigurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next inte - er. This register field is not required for DDR2 and DDR3 (except if MEMC_TRAINING is set), as the DFI read and write latenci - s defined in DFITMG0 and DFITMG1 are sufficient for those protocols Unit: clocks - PSU_DDRC_DRAMTMG2_READ_LATENCY 0x8 - - DDR2/3/mDDR: RL + BL/2 + 2 - WL DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL LPDDR2/LPDDR3: RL + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL - PDDR4(DQ ODT is Disabled): RL + BL/2 + RU(tDQSCKmax/tCK) + WR_PREAMBLE + RD_POSTAMBLE - WL LPDDR4(DQ ODT is Enabled) : RL + B - /2 + RU(tDQSCKmax/tCK) + RD_POSTAMBLE - ODTLon - RU(tODTon(min)/tCK) Minimum time from read command to write command. Include - time for bus turnaround and all per-bank, per-rank, and global constraints. Unit: Clocks. Where: - WL = write latency - BL = - urst length. This must match the value programmed in the BL bit of the mode register to the SDRAM - RL = read latency = CAS l - tency - WR_PREAMBLE = write preamble. This is unique to DDR4 and LPDDR4. - RD_POSTAMBLE = read postamble. This is unique to L - DDR4. For LPDDR2/LPDDR3/LPDDR4, if derating is enabled (DERATEEN.derate_enable=1), derated tDQSCKmax should be used. For conf - gurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next integer. - PSU_DDRC_DRAMTMG2_RD2WR 0x6 - - DDR4: CWL + PL + BL/2 + tWTR_L Others: CWL + BL/2 + tWTR In DDR4, minimum time from write command to read command for same ba - k group. In others, minimum time from write command to read command. Includes time for bus turnaround, recovery times, and al - per-bank, per-rank, and global constraints. Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity latency - BL = burs - length. This must match the value programmed in the BL bit of the mode register to the SDRAM - tWTR_L = internal write to re - d command delay for same bank group. This comes directly from the SDRAM specification. - tWTR = internal write to read comman - delay. This comes directly from the SDRAM specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 operation. For configu - ations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next integer. - PSU_DDRC_DRAMTMG2_WR2RD 0xe - - SDRAM Timing Register 2 - (OFFSET, MASK, VALUE) (0XFD070108, 0x3F3F3F3FU ,0x0708060EU) - RegMask = (DDRC_DRAMTMG2_WRITE_LATENCY_MASK | DDRC_DRAMTMG2_READ_LATENCY_MASK | DDRC_DRAMTMG2_RD2WR_MASK | DDRC_DRAMTMG2_WR2RD_MASK | 0 ); - - RegVal = ((0x00000007U << DDRC_DRAMTMG2_WRITE_LATENCY_SHIFT - | 0x00000008U << DDRC_DRAMTMG2_READ_LATENCY_SHIFT - | 0x00000006U << DDRC_DRAMTMG2_RD2WR_SHIFT - | 0x0000000EU << DDRC_DRAMTMG2_WR2RD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DRAMTMG2_OFFSET ,0x3F3F3F3FU ,0x0708060EU); - /*############################################################################################################################ */ - - /*Register : DRAMTMG3 @ 0XFD07010C

- - Time to wait after a mode register write or read (MRW or MRR). Present only in designs configured to support LPDDR2, LPDDR3 o - LPDDR4. LPDDR2 typically requires value of 5. LPDDR3 typically requires value of 10. LPDDR4: Set this to the larger of tMRW - nd tMRWCKEL. For LPDDR2, this register is used for the time from a MRW/MRR to all other commands. For LDPDR3, this register i - used for the time from a MRW/MRR to a MRW/MRR. - PSU_DDRC_DRAMTMG3_T_MRW 0x5 - - tMRD: Cycles to wait after a mode register write or read. Depending on the connected SDRAM, tMRD represents: DDR2/mDDR: Time - rom MRS to any command DDR3/4: Time from MRS to MRS command LPDDR2: not used LPDDR3/4: Time from MRS to non-MRS command For c - nfigurations with MEMC_FREQ_RATIO=2, program this to (tMRD/2) and round it up to the next integer value. If C/A parity for DD - 4 is used, set to tMRD_PAR(tMOD+PL) instead. - PSU_DDRC_DRAMTMG3_T_MRD 0x4 - - tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode command and following non-load mode command. If C/A pari - y for DDR4 is used, set to tMOD_PAR(tMOD+PL) instead. Set to tMOD if MEMC_FREQ_RATIO=1, or tMOD/2 (rounded up to next integer - if MEMC_FREQ_RATIO=2. Note that if using RDIMM, depending on the PHY, it may be necessary to use a value of tMOD + 1 or (tMO - + 1)/2 to compensate for the extra cycle of latency applied to mode register writes by the RDIMM chip. - PSU_DDRC_DRAMTMG3_T_MOD 0xc - - SDRAM Timing Register 3 - (OFFSET, MASK, VALUE) (0XFD07010C, 0x3FF3F3FFU ,0x0050400CU) - RegMask = (DDRC_DRAMTMG3_T_MRW_MASK | DDRC_DRAMTMG3_T_MRD_MASK | DDRC_DRAMTMG3_T_MOD_MASK | 0 ); - - RegVal = ((0x00000005U << DDRC_DRAMTMG3_T_MRW_SHIFT - | 0x00000004U << DDRC_DRAMTMG3_T_MRD_SHIFT - | 0x0000000CU << DDRC_DRAMTMG3_T_MOD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DRAMTMG3_OFFSET ,0x3FF3F3FFU ,0x0050400CU); - /*############################################################################################################################ */ - - /*Register : DRAMTMG4 @ 0XFD070110

- - tRCD - tAL: Minimum time from activate to read or write command to same bank. For configurations with MEMC_FREQ_RATIO=2, prog - am this to ((tRCD - tAL)/2) and round it up to the next integer value. Minimum value allowed for this register is 1, which im - lies minimum (tRCD - tAL) value to be 2 in configurations with MEMC_FREQ_RATIO=2. Unit: Clocks. - PSU_DDRC_DRAMTMG4_T_RCD 0x8 - - DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank group. Others: tCCD: This is the minimum - time between two reads or two writes. For configurations with MEMC_FREQ_RATIO=2, program this to (tCCD_L/2 or tCCD/2) and rou - d it up to the next integer value. Unit: clocks. - PSU_DDRC_DRAMTMG4_T_CCD 0x3 - - DDR4: tRRD_L: Minimum time between activates from bank 'a' to bank 'b' for same bank group. Others: tRRD: Minimum time betwee - activates from bank 'a' to bank 'b'For configurations with MEMC_FREQ_RATIO=2, program this to (tRRD_L/2 or tRRD/2) and round - it up to the next integer value. Unit: Clocks. - PSU_DDRC_DRAMTMG4_T_RRD 0x3 - - tRP: Minimum time from precharge to activate of same bank. For MEMC_FREQ_RATIO=1 configurations, t_rp should be set to RoundU - (tRP/tCK). For MEMC_FREQ_RATIO=2 configurations, t_rp should be set to RoundDown(RoundUp(tRP/tCK)/2) + 1. For MEMC_FREQ_RATIO - 2 configurations in LPDDR4, t_rp should be set to RoundUp(RoundUp(tRP/tCK)/2). Unit: Clocks. - PSU_DDRC_DRAMTMG4_T_RP 0x9 - - SDRAM Timing Register 4 - (OFFSET, MASK, VALUE) (0XFD070110, 0x1F0F0F1FU ,0x08030309U) - RegMask = (DDRC_DRAMTMG4_T_RCD_MASK | DDRC_DRAMTMG4_T_CCD_MASK | DDRC_DRAMTMG4_T_RRD_MASK | DDRC_DRAMTMG4_T_RP_MASK | 0 ); - - RegVal = ((0x00000008U << DDRC_DRAMTMG4_T_RCD_SHIFT - | 0x00000003U << DDRC_DRAMTMG4_T_CCD_SHIFT - | 0x00000003U << DDRC_DRAMTMG4_T_RRD_SHIFT - | 0x00000009U << DDRC_DRAMTMG4_T_RP_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DRAMTMG4_OFFSET ,0x1F0F0F1FU ,0x08030309U); - /*############################################################################################################################ */ - - /*Register : DRAMTMG5 @ 0XFD070114

- - This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stab - e time before SRX. Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEH - DDR2: 1 - DDR3: tCKSRX - DDR4: - tCKSRX For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it up to next in - eger. - PSU_DDRC_DRAMTMG5_T_CKSRX 0x6 - - This is the time after Self Refresh Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay afte - SRE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL - DDR2: 1 - DDR3: max (10 ns, 5 tCK) - DDR4: - ax (10 ns, 5 tCK) For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it up - to next integer. - PSU_DDRC_DRAMTMG5_T_CKSRE 0x6 - - Minimum CKE low width for Self refresh or Self refresh power down entry to exit timing in memory clock cycles. Recommended se - tings: - mDDR: tRFC - LPDDR2: tCKESR - LPDDR3: tCKESR - LPDDR4: max(tCKELPD, tSR) - DDR2: tCKE - DDR3: tCKE + 1 - DDR4: tCKE - 1 For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it up to next intege - . - PSU_DDRC_DRAMTMG5_T_CKESR 0x4 - - Minimum number of cycles of CKE HIGH/LOW during power-down and self refresh. - LPDDR2/LPDDR3 mode: Set this to the larger of - CKE or tCKESR - LPDDR4 mode: Set this to the larger of tCKE, tCKELPD or tSR. - Non-LPDDR2/non-LPDDR3/non-LPDDR4 designs: Set - his to tCKE value. For configurations with MEMC_FREQ_RATIO=2, program this to (value described above)/2 and round it up to th - next integer value. Unit: Clocks. - PSU_DDRC_DRAMTMG5_T_CKE 0x3 - - SDRAM Timing Register 5 - (OFFSET, MASK, VALUE) (0XFD070114, 0x0F0F3F1FU ,0x06060403U) - RegMask = (DDRC_DRAMTMG5_T_CKSRX_MASK | DDRC_DRAMTMG5_T_CKSRE_MASK | DDRC_DRAMTMG5_T_CKESR_MASK | DDRC_DRAMTMG5_T_CKE_MASK | 0 ); - - RegVal = ((0x00000006U << DDRC_DRAMTMG5_T_CKSRX_SHIFT - | 0x00000006U << DDRC_DRAMTMG5_T_CKSRE_SHIFT - | 0x00000004U << DDRC_DRAMTMG5_T_CKESR_SHIFT - | 0x00000003U << DDRC_DRAMTMG5_T_CKE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DRAMTMG5_OFFSET ,0x0F0F3F1FU ,0x06060403U); - /*############################################################################################################################ */ - - /*Register : DRAMTMG6 @ 0XFD070118

- - This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after - PDE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 For configurations with MEMC_FREQ_RATIO=2, program this to recom - ended value divided by two and round it up to next integer. This is only present for designs supporting mDDR or LPDDR2/LPDDR3 - devices. - PSU_DDRC_DRAMTMG6_T_CKDPDE 0x1 - - This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock - table time before DPDX. Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 For configurations with MEMC_FREQ_RATIO=2, pr - gram this to recommended value divided by two and round it up to next integer. This is only present for designs supporting mD - R or LPDDR2 devices. - PSU_DDRC_DRAMTMG6_T_CKDPDX 0x1 - - This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing Clock Stop Exit. Specifies the - lock stable time before next command after Clock Stop Exit. Recommended settings: - mDDR: 1 - LPDDR2: tXP + 2 - LPDDR3: tXP + - 2 - LPDDR4: tXP + 2 For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it - p to next integer. This is only present for designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices. - PSU_DDRC_DRAMTMG6_T_CKCSX 0x4 - - SDRAM Timing Register 6 - (OFFSET, MASK, VALUE) (0XFD070118, 0x0F0F000FU ,0x01010004U) - RegMask = (DDRC_DRAMTMG6_T_CKDPDE_MASK | DDRC_DRAMTMG6_T_CKDPDX_MASK | DDRC_DRAMTMG6_T_CKCSX_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_DRAMTMG6_T_CKDPDE_SHIFT - | 0x00000001U << DDRC_DRAMTMG6_T_CKDPDX_SHIFT - | 0x00000004U << DDRC_DRAMTMG6_T_CKCSX_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DRAMTMG6_OFFSET ,0x0F0F000FU ,0x01010004U); - /*############################################################################################################################ */ - - /*Register : DRAMTMG7 @ 0XFD07011C

- - This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. - ecommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL For configurations with MEMC_FREQ_RATIO=2, program t - is to recommended value divided by two and round it up to next integer. This is only present for designs supporting mDDR or L - DDR2/LPDDR3/LPDDR4 devices. - PSU_DDRC_DRAMTMG7_T_CKPDE 0x6 - - This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable - time before PDX. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: 2 For configurations with MEMC_FREQ_RATIO= - , program this to recommended value divided by two and round it up to next integer. This is only present for designs supporti - g mDDR or LPDDR2/LPDDR3/LPDDR4 devices. - PSU_DDRC_DRAMTMG7_T_CKPDX 0x6 - - SDRAM Timing Register 7 - (OFFSET, MASK, VALUE) (0XFD07011C, 0x00000F0FU ,0x00000606U) - RegMask = (DDRC_DRAMTMG7_T_CKPDE_MASK | DDRC_DRAMTMG7_T_CKPDX_MASK | 0 ); - - RegVal = ((0x00000006U << DDRC_DRAMTMG7_T_CKPDE_SHIFT - | 0x00000006U << DDRC_DRAMTMG7_T_CKPDX_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DRAMTMG7_OFFSET ,0x00000F0FU ,0x00000606U); - /*############################################################################################################################ */ - - /*Register : DRAMTMG8 @ 0XFD070120

- - tXS_FAST: Exit Self Refresh to ZQCL, ZQCS and MRS (only CL, WR, RTP and Geardown mode). For configurations with MEMC_FREQ_RAT - O=2, program this to the above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: Thi - is applicable to only ZQCL/ZQCS commands. Note: Ensure this is less than or equal to t_xs_x32. - PSU_DDRC_DRAMTMG8_T_XS_FAST_X32 0x4 - - tXS_ABORT: Exit Self Refresh to commands not requiring a locked DLL in Self Refresh Abort. For configurations with MEMC_FREQ_ - ATIO=2, program this to the above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: - nsure this is less than or equal to t_xs_x32. - PSU_DDRC_DRAMTMG8_T_XS_ABORT_X32 0x4 - - tXSDLL: Exit Self Refresh to commands requiring a locked DLL. For configurations with MEMC_FREQ_RATIO=2, program this to the - bove value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: Used only for DDR2, DDR3 and - DR4 SDRAMs. - PSU_DDRC_DRAMTMG8_T_XS_DLL_X32 0xd - - tXS: Exit Self Refresh to commands not requiring a locked DLL. For configurations with MEMC_FREQ_RATIO=2, program this to the - above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: Used only for DDR2, DDR3 and - DDR4 SDRAMs. - PSU_DDRC_DRAMTMG8_T_XS_X32 0x6 - - SDRAM Timing Register 8 - (OFFSET, MASK, VALUE) (0XFD070120, 0x7F7F7F7FU ,0x04040D06U) - RegMask = (DDRC_DRAMTMG8_T_XS_FAST_X32_MASK | DDRC_DRAMTMG8_T_XS_ABORT_X32_MASK | DDRC_DRAMTMG8_T_XS_DLL_X32_MASK | DDRC_DRAMTMG8_T_XS_X32_MASK | 0 ); - - RegVal = ((0x00000004U << DDRC_DRAMTMG8_T_XS_FAST_X32_SHIFT - | 0x00000004U << DDRC_DRAMTMG8_T_XS_ABORT_X32_SHIFT - | 0x0000000DU << DDRC_DRAMTMG8_T_XS_DLL_X32_SHIFT - | 0x00000006U << DDRC_DRAMTMG8_T_XS_X32_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DRAMTMG8_OFFSET ,0x7F7F7F7FU ,0x04040D06U); - /*############################################################################################################################ */ - - /*Register : DRAMTMG9 @ 0XFD070124

- - DDR4 Write preamble mode - 0: 1tCK preamble - 1: 2tCK preamble Present only with MEMC_FREQ_RATIO=2 - PSU_DDRC_DRAMTMG9_DDR4_WR_PREAMBLE 0x0 - - tCCD_S: This is the minimum time between two reads or two writes for different bank group. For bank switching (from bank 'a' - o bank 'b'), the minimum time is this value + 1. For configurations with MEMC_FREQ_RATIO=2, program this to (tCCD_S/2) and ro - nd it up to the next integer value. Present only in designs configured to support DDR4. Unit: clocks. - PSU_DDRC_DRAMTMG9_T_CCD_S 0x2 - - tRRD_S: Minimum time between activates from bank 'a' to bank 'b' for different bank group. For configurations with MEMC_FREQ_ - ATIO=2, program this to (tRRD_S/2) and round it up to the next integer value. Present only in designs configured to support D - R4. Unit: Clocks. - PSU_DDRC_DRAMTMG9_T_RRD_S 0x2 - - CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command for different bank group. Includes time for bus turn - round, recovery times, and all per-bank, per-rank, and global constraints. Present only in designs configured to support DDR4 - Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity latency - BL = burst length. This must match the value programm - d in the BL bit of the mode register to the SDRAM - tWTR_S = internal write to read command delay for different bank group. T - is comes directly from the SDRAM specification. For configurations with MEMC_FREQ_RATIO=2, divide the value calculated using - he above equation by 2, and round it up to next integer. - PSU_DDRC_DRAMTMG9_WR2RD_S 0xb - - SDRAM Timing Register 9 - (OFFSET, MASK, VALUE) (0XFD070124, 0x40070F3FU ,0x0002020BU) - RegMask = (DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_MASK | DDRC_DRAMTMG9_T_CCD_S_MASK | DDRC_DRAMTMG9_T_RRD_S_MASK | DDRC_DRAMTMG9_WR2RD_S_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_SHIFT - | 0x00000002U << DDRC_DRAMTMG9_T_CCD_S_SHIFT - | 0x00000002U << DDRC_DRAMTMG9_T_RRD_S_SHIFT - | 0x0000000BU << DDRC_DRAMTMG9_WR2RD_S_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DRAMTMG9_OFFSET ,0x40070F3FU ,0x0002020BU); - /*############################################################################################################################ */ - - /*Register : DRAMTMG11 @ 0XFD07012C

- - tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DLL. For configurations with MEMC_FREQ_RATIO=2, program - this to (tXMPDLL/2) and round it up to the next integer value. Present only in designs configured to support DDR4. Unit: Mult - ples of 32 clocks. - PSU_DDRC_DRAMTMG11_POST_MPSM_GAP_X32 0x6f - - tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge. For configurations with MEMC_FREQ_RATIO=2, program this t - RoundUp(tMPX_LH/2)+1. Present only in designs configured to support DDR4. Unit: clocks. - PSU_DDRC_DRAMTMG11_T_MPX_LH 0x7 - - tMPX_S: Minimum time CS setup time to CKE. For configurations with MEMC_FREQ_RATIO=2, program this to (tMPX_S/2) and round it - up to the next integer value. Present only in designs configured to support DDR4. Unit: Clocks. - PSU_DDRC_DRAMTMG11_T_MPX_S 0x1 - - tCKMPE: Minimum valid clock requirement after MPSM entry. Present only in designs configured to support DDR4. Unit: Clocks. F - r configurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next i - teger. - PSU_DDRC_DRAMTMG11_T_CKMPE 0xe - - SDRAM Timing Register 11 - (OFFSET, MASK, VALUE) (0XFD07012C, 0x7F1F031FU ,0x6F07010EU) - RegMask = (DDRC_DRAMTMG11_POST_MPSM_GAP_X32_MASK | DDRC_DRAMTMG11_T_MPX_LH_MASK | DDRC_DRAMTMG11_T_MPX_S_MASK | DDRC_DRAMTMG11_T_CKMPE_MASK | 0 ); - - RegVal = ((0x0000006FU << DDRC_DRAMTMG11_POST_MPSM_GAP_X32_SHIFT - | 0x00000007U << DDRC_DRAMTMG11_T_MPX_LH_SHIFT - | 0x00000001U << DDRC_DRAMTMG11_T_MPX_S_SHIFT - | 0x0000000EU << DDRC_DRAMTMG11_T_CKMPE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DRAMTMG11_OFFSET ,0x7F1F031FU ,0x6F07010EU); - /*############################################################################################################################ */ - - /*Register : DRAMTMG12 @ 0XFD070130

- - tCMDCKE: Delay from valid command to CKE input LOW. Set this to the larger of tESCKE or tCMDCKE For configurations with MEMC_ - REQ_RATIO=2, program this to (max(tESCKE, tCMDCKE)/2) and round it up to next integer value. - PSU_DDRC_DRAMTMG12_T_CMDCKE 0x2 - - tCKEHCMD: Valid command requirement after CKE input HIGH. For configurations with MEMC_FREQ_RATIO=2, program this to (tCKEHCM - /2) and round it up to next integer value. - PSU_DDRC_DRAMTMG12_T_CKEHCMD 0x6 - - tMRD_PDA: This is the Mode Register Set command cycle time in PDA mode. For configurations with MEMC_FREQ_RATIO=2, program th - s to (tMRD_PDA/2) and round it up to next integer value. - PSU_DDRC_DRAMTMG12_T_MRD_PDA 0x8 - - SDRAM Timing Register 12 - (OFFSET, MASK, VALUE) (0XFD070130, 0x00030F1FU ,0x00020608U) - RegMask = (DDRC_DRAMTMG12_T_CMDCKE_MASK | DDRC_DRAMTMG12_T_CKEHCMD_MASK | DDRC_DRAMTMG12_T_MRD_PDA_MASK | 0 ); - - RegVal = ((0x00000002U << DDRC_DRAMTMG12_T_CMDCKE_SHIFT - | 0x00000006U << DDRC_DRAMTMG12_T_CKEHCMD_SHIFT - | 0x00000008U << DDRC_DRAMTMG12_T_MRD_PDA_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DRAMTMG12_OFFSET ,0x00030F1FU ,0x00020608U); - /*############################################################################################################################ */ - - /*Register : ZQCTL0 @ 0XFD070180

- - - 1 - Disable uMCTL2 generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used instead to is - ue ZQ calibration request from APB module. - 0 - Internally generate ZQCS/MPC(ZQ calibration) commands based on ZQCTL1.t_zq_s - ort_interval_x1024. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. - PSU_DDRC_ZQCTL0_DIS_AUTO_ZQ 0x1 - - - 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable when run in DDR3 - or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. - 0 - Enable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Power - own exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. This is only present for designs suppo - ting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. - PSU_DDRC_ZQCTL0_DIS_SRX_ZQCL 0x0 - - - 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are sent to one r - nk at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to different ranks do not ov - rlap. - 0 - ZQ resistor is not shared. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. - PSU_DDRC_ZQCTL0_ZQ_RESISTOR_SHARED 0x0 - - - 1 - Disable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode. - 0 - Enable - ssuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode. This is only present for des - gns supporting DDR4 devices. - PSU_DDRC_ZQCTL0_DIS_MPSMX_ZQCL 0x0 - - tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Number of cycles of NOP required after a ZQCL (ZQ calibrat - on long)/MPC(ZQ Start) command is issued to SDRAM. For configurations with MEMC_FREQ_RATIO=2: DDR3/DDR4: program this to tZQo - er/2 and round it up to the next integer value. LPDDR2/LPDDR3: program this to tZQCL/2 and round it up to the next integer va - ue. LPDDR4: program this to tZQCAL/2 and round it up to the next integer value. Unit: Clock cycles. This is only present for - esigns supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. - PSU_DDRC_ZQCTL0_T_ZQ_LONG_NOP 0x100 - - tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of cycles of NOP required after a ZQCS (ZQ calibration short)/MPC - ZQ Latch) command is issued to SDRAM. For configurations with MEMC_FREQ_RATIO=2, program this to tZQCS/2 and round it up to t - e next integer value. Unit: Clock cycles. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devic - s. - PSU_DDRC_ZQCTL0_T_ZQ_SHORT_NOP 0x40 - - ZQ Control Register 0 - (OFFSET, MASK, VALUE) (0XFD070180, 0xF7FF03FFU ,0x81000040U) - RegMask = (DDRC_ZQCTL0_DIS_AUTO_ZQ_MASK | DDRC_ZQCTL0_DIS_SRX_ZQCL_MASK | DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_MASK | DDRC_ZQCTL0_DIS_MPSMX_ZQCL_MASK | DDRC_ZQCTL0_T_ZQ_LONG_NOP_MASK | DDRC_ZQCTL0_T_ZQ_SHORT_NOP_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_ZQCTL0_DIS_AUTO_ZQ_SHIFT - | 0x00000000U << DDRC_ZQCTL0_DIS_SRX_ZQCL_SHIFT - | 0x00000000U << DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_SHIFT - | 0x00000000U << DDRC_ZQCTL0_DIS_MPSMX_ZQCL_SHIFT - | 0x00000100U << DDRC_ZQCTL0_T_ZQ_LONG_NOP_SHIFT - | 0x00000040U << DDRC_ZQCTL0_T_ZQ_SHORT_NOP_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_ZQCTL0_OFFSET ,0xF7FF03FFU ,0x81000040U); - /*############################################################################################################################ */ - - /*Register : ZQCTL1 @ 0XFD070184

- - tZQReset: Number of cycles of NOP required after a ZQReset (ZQ calibration Reset) command is issued to SDRAM. For configurati - ns with MEMC_FREQ_RATIO=2, program this to tZQReset/2 and round it up to the next integer value. Unit: Clock cycles. This is - nly present for designs supporting LPDDR2/LPDDR3/LPDDR4 devices. - PSU_DDRC_ZQCTL1_T_ZQ_RESET_NOP 0x20 - - Average interval to wait between automatically issuing ZQCS (ZQ calibration short)/MPC(ZQ calibration) commands to DDR3/DDR4/ - PDDR2/LPDDR3/LPDDR4 devices. Meaningless, if ZQCTL0.dis_auto_zq=1. Unit: 1024 clock cycles. This is only present for designs - upporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. - PSU_DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024 0x19707 - - ZQ Control Register 1 - (OFFSET, MASK, VALUE) (0XFD070184, 0x3FFFFFFFU ,0x02019707U) - RegMask = (DDRC_ZQCTL1_T_ZQ_RESET_NOP_MASK | DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_MASK | 0 ); - - RegVal = ((0x00000020U << DDRC_ZQCTL1_T_ZQ_RESET_NOP_SHIFT - | 0x00019707U << DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_ZQCTL1_OFFSET ,0x3FFFFFFFU ,0x02019707U); - /*############################################################################################################################ */ - - /*Register : DFITMG0 @ 0XFD070190

- - Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signa - s at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligne - , this timing parameter should be rounded up to the next integer value. Note that if using RDIMM, it is necessary to incremen - this parameter by RDIMM's extra cycle of latency in terms of DFI clock. - PSU_DDRC_DFITMG0_DFI_T_CTRL_DELAY 0x4 - - Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR or SDR values Selects whether value in DFITM - 0.dfi_t_rddata_en is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles R - fer to PHY specification for correct value. - PSU_DDRC_DFITMG0_DFI_RDDATA_USE_SDR 0x1 - - Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. Refer to PHY spe - ification for correct value. This corresponds to the DFI parameter trddata_en. Note that, depending on the PHY, if using RDIM - , it may be necessary to use the value (CL + 1) in the calculation of trddata_en. This is to compensate for the extra cycle o - latency through the RDIMM. Unit: Clocks - PSU_DDRC_DFITMG0_DFI_T_RDDATA_EN 0xb - - Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using HDR or SDR values Selects whether value in DFITMG - .dfi_tphy_wrlat is in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.dfi_tphy_wrdata is in terms of SDR or - HDR clock cycles - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles Refer to PHY specification for correct val - e. - PSU_DDRC_DFITMG0_DFI_WRDATA_USE_SDR 0x1 - - Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on th - dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. N - te, max supported value is 8. Unit: Clocks - PSU_DDRC_DFITMG0_DFI_TPHY_WRDATA 0x2 - - Write latency Number of clocks from the write command to write data enable (dfi_wrdata_en). This corresponds to the DFI timin - parameter tphy_wrlat. Refer to PHY specification for correct value.Note that, depending on the PHY, if using RDIMM, it may b - necessary to use the value (CL + 1) in the calculation of tphy_wrlat. This is to compensate for the extra cycle of latency t - rough the RDIMM. - PSU_DDRC_DFITMG0_DFI_TPHY_WRLAT 0xb - - DFI Timing Register 0 - (OFFSET, MASK, VALUE) (0XFD070190, 0x1FBFBF3FU ,0x048B820BU) - RegMask = (DDRC_DFITMG0_DFI_T_CTRL_DELAY_MASK | DDRC_DFITMG0_DFI_RDDATA_USE_SDR_MASK | DDRC_DFITMG0_DFI_T_RDDATA_EN_MASK | DDRC_DFITMG0_DFI_WRDATA_USE_SDR_MASK | DDRC_DFITMG0_DFI_TPHY_WRDATA_MASK | DDRC_DFITMG0_DFI_TPHY_WRLAT_MASK | 0 ); - - RegVal = ((0x00000004U << DDRC_DFITMG0_DFI_T_CTRL_DELAY_SHIFT - | 0x00000001U << DDRC_DFITMG0_DFI_RDDATA_USE_SDR_SHIFT - | 0x0000000BU << DDRC_DFITMG0_DFI_T_RDDATA_EN_SHIFT - | 0x00000001U << DDRC_DFITMG0_DFI_WRDATA_USE_SDR_SHIFT - | 0x00000002U << DDRC_DFITMG0_DFI_TPHY_WRDATA_SHIFT - | 0x0000000BU << DDRC_DFITMG0_DFI_TPHY_WRLAT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DFITMG0_OFFSET ,0x1FBFBF3FU ,0x048B820BU); - /*############################################################################################################################ */ - - /*Register : DFITMG1 @ 0XFD070194

- - Specifies the number of DFI PHY clocks between when the dfi_cs signal is asserted and when the associated command is driven. - his field is used for CAL mode, should be set to '0' or the value which matches the CAL mode register setting in the DRAM. If - the PHY can add the latency for CAL mode, this should be set to '0'. Valid Range: 0, 3, 4, 5, 6, and 8 - PSU_DDRC_DFITMG1_DFI_T_CMD_LAT 0x0 - - Specifies the number of DFI PHY clocks between when the dfi_cs signal is asserted and when the associated dfi_parity_in signa - is driven. - PSU_DDRC_DFITMG1_DFI_T_PARIN_LAT 0x0 - - Specifies the number of DFI clocks between when the dfi_wrdata_en signal is asserted and when the corresponding write data tr - nsfer is completed on the DRAM bus. This corresponds to the DFI timing parameter twrdata_delay. Refer to PHY specification fo - correct value. For DFI 3.0 PHY, set to twrdata_delay, a new timing parameter introduced in DFI 3.0. For DFI 2.1 PHY, set to - phy_wrdata + (delay of DFI write data to the DRAM). Value to be programmed is in terms of DFI clocks, not PHY clocks. In FREQ - RATIO=2, divide PHY's value by 2 and round up to next integer. If using DFITMG0.dfi_wrdata_use_sdr=1, add 1 to the value. Uni - : Clocks - PSU_DDRC_DFITMG1_DFI_T_WRDATA_DELAY 0x3 - - Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to - he DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase - ligned, this timing parameter should be rounded up to the next integer value. - PSU_DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE 0x3 - - Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first - alid rising edge of the clock to the DRAM memory devices, at the PHY-DRAM boundary. If the DFI clock and the memory clock are - not phase aligned, this timing parameter should be rounded up to the next integer value. - PSU_DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE 0x4 - - DFI Timing Register 1 - (OFFSET, MASK, VALUE) (0XFD070194, 0xF31F0F0FU ,0x00030304U) - RegMask = (DDRC_DFITMG1_DFI_T_CMD_LAT_MASK | DDRC_DFITMG1_DFI_T_PARIN_LAT_MASK | DDRC_DFITMG1_DFI_T_WRDATA_DELAY_MASK | DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_MASK | DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_DFITMG1_DFI_T_CMD_LAT_SHIFT - | 0x00000000U << DDRC_DFITMG1_DFI_T_PARIN_LAT_SHIFT - | 0x00000003U << DDRC_DFITMG1_DFI_T_WRDATA_DELAY_SHIFT - | 0x00000003U << DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_SHIFT - | 0x00000004U << DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DFITMG1_OFFSET ,0xF31F0F0FU ,0x00030304U); - /*############################################################################################################################ */ - - /*Register : DFILPCFG0 @ 0XFD070198

- - Setting for DFI's tlp_resp time. Same value is used for both Power Down, Self Refresh, Deep Power Down and Maximum Power Savi - g modes. DFI 2.1 specification onwards, recommends using a fixed value of 7 always. - PSU_DDRC_DFILPCFG0_DFI_TLP_RESP 0x7 - - Value to drive on dfi_lp_wakeup signal when Deep Power Down mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 - cycles - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles - 0x7 - - 2048 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0xD - - 31072 cycles - 0xE - 262144 cycles - 0xF - Unlimited This is only present for designs supporting mDDR or LPDDR2/LPDDR3 device - . - PSU_DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD 0x0 - - Enables DFI Low Power interface handshaking during Deep Power Down Entry/Exit. - 0 - Disabled - 1 - Enabled This is only pres - nt for designs supporting mDDR or LPDDR2/LPDDR3 devices. - PSU_DDRC_DFILPCFG0_DFI_LP_EN_DPD 0x0 - - Value to drive on dfi_lp_wakeup signal when Self Refresh mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cy - les - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles - 0x7 - - 048 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0xD - 131 - 72 cycles - 0xE - 262144 cycles - 0xF - Unlimited - PSU_DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR 0x0 - - Enables DFI Low Power interface handshaking during Self Refresh Entry/Exit. - 0 - Disabled - 1 - Enabled - PSU_DDRC_DFILPCFG0_DFI_LP_EN_SR 0x1 - - Value to drive on dfi_lp_wakeup signal when Power Down mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycl - s - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles - 0x7 - 20 - 8 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0xD - 13107 - cycles - 0xE - 262144 cycles - 0xF - Unlimited - PSU_DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD 0x0 - - Enables DFI Low Power interface handshaking during Power Down Entry/Exit. - 0 - Disabled - 1 - Enabled - PSU_DDRC_DFILPCFG0_DFI_LP_EN_PD 0x1 - - DFI Low Power Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD070198, 0x0FF1F1F1U ,0x07000101U) - RegMask = (DDRC_DFILPCFG0_DFI_TLP_RESP_MASK | DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_MASK | DDRC_DFILPCFG0_DFI_LP_EN_DPD_MASK | DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_MASK | DDRC_DFILPCFG0_DFI_LP_EN_SR_MASK | DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_MASK | DDRC_DFILPCFG0_DFI_LP_EN_PD_MASK | 0 ); - - RegVal = ((0x00000007U << DDRC_DFILPCFG0_DFI_TLP_RESP_SHIFT - | 0x00000000U << DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_SHIFT - | 0x00000000U << DDRC_DFILPCFG0_DFI_LP_EN_DPD_SHIFT - | 0x00000000U << DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_SHIFT - | 0x00000001U << DDRC_DFILPCFG0_DFI_LP_EN_SR_SHIFT - | 0x00000000U << DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_SHIFT - | 0x00000001U << DDRC_DFILPCFG0_DFI_LP_EN_PD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DFILPCFG0_OFFSET ,0x0FF1F1F1U ,0x07000101U); - /*############################################################################################################################ */ - - /*Register : DFILPCFG1 @ 0XFD07019C

- - Value to drive on dfi_lp_wakeup signal when Maximum Power Saving Mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - - 16 cycles - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0 - D - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited This is only present for designs supporting DDR4 devices. - PSU_DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM 0x2 - - Enables DFI Low Power interface handshaking during Maximum Power Saving Mode Entry/Exit. - 0 - Disabled - 1 - Enabled This is - only present for designs supporting DDR4 devices. - PSU_DDRC_DFILPCFG1_DFI_LP_EN_MPSM 0x1 - - DFI Low Power Configuration Register 1 - (OFFSET, MASK, VALUE) (0XFD07019C, 0x000000F1U ,0x00000021U) - RegMask = (DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_MASK | DDRC_DFILPCFG1_DFI_LP_EN_MPSM_MASK | 0 ); - - RegVal = ((0x00000002U << DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_SHIFT - | 0x00000001U << DDRC_DFILPCFG1_DFI_LP_EN_MPSM_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DFILPCFG1_OFFSET ,0x000000F1U ,0x00000021U); - /*############################################################################################################################ */ - - /*Register : DFIUPD1 @ 0XFD0701A4

- - This is the minimum amount of time between uMCTL2 initiated DFI update requests (which is executed whenever the uMCTL2 is idl - ). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the fir - t read request when the uMCTL2 is idle. Unit: 1024 clocks - PSU_DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024 0x41 - - This is the maximum amount of time between uMCTL2 initiated DFI update requests. This timer resets with each update request; - hen the timer expires dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd_ackx is received. PHY can use this - idle time to recalibrate the delay lines to the DLLs. The DFI controller update is also used to reset PHY FIFO pointers in ca - e of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. - Note: Value programmed for DFIUPD1.dfi_t_ctrlupd_interval_max_x1024 must be greater than DFIUPD1.dfi_t_ctrlupd_interval_min_x - 024. Unit: 1024 clocks - PSU_DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024 0xe2 - - DFI Update Register 1 - (OFFSET, MASK, VALUE) (0XFD0701A4, 0x00FF00FFU ,0x004100E2U) - RegMask = (DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_MASK | DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_MASK | 0 ); - - RegVal = ((0x00000041U << DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_SHIFT - | 0x000000E2U << DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DFIUPD1_OFFSET ,0x00FF00FFU ,0x004100E2U); - /*############################################################################################################################ */ - - /*Register : DFIMISC @ 0XFD0701B0

- - Defines polarity of dfi_wrdata_cs and dfi_rddata_cs signals. - 0: Signals are active low - 1: Signals are active high - PSU_DDRC_DFIMISC_DFI_DATA_CS_POLARITY 0x0 - - DBI implemented in DDRC or PHY. - 0 - DDRC implements DBI functionality. - 1 - PHY implements DBI functionality. Present only - in designs configured to support DDR4 and LPDDR4. - PSU_DDRC_DFIMISC_PHY_DBI_MODE 0x0 - - PHY initialization complete enable signal. When asserted the dfi_init_complete signal can be used to trigger SDRAM initialisa - ion - PSU_DDRC_DFIMISC_DFI_INIT_COMPLETE_EN 0x0 - - DFI Miscellaneous Control Register - (OFFSET, MASK, VALUE) (0XFD0701B0, 0x00000007U ,0x00000000U) - RegMask = (DDRC_DFIMISC_DFI_DATA_CS_POLARITY_MASK | DDRC_DFIMISC_PHY_DBI_MODE_MASK | DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_DFIMISC_DFI_DATA_CS_POLARITY_SHIFT - | 0x00000000U << DDRC_DFIMISC_PHY_DBI_MODE_SHIFT - | 0x00000000U << DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DFIMISC_OFFSET ,0x00000007U ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : DFITMG2 @ 0XFD0701B4

- - >Number of clocks between when a read command is sent on the DFI control interface and when the associated dfi_rddata_cs sign - l is asserted. This corresponds to the DFI timing parameter tphy_rdcslat. Refer to PHY specification for correct value. - PSU_DDRC_DFITMG2_DFI_TPHY_RDCSLAT 0x9 - - Number of clocks between when a write command is sent on the DFI control interface and when the associated dfi_wrdata_cs sign - l is asserted. This corresponds to the DFI timing parameter tphy_wrcslat. Refer to PHY specification for correct value. - PSU_DDRC_DFITMG2_DFI_TPHY_WRCSLAT 0x6 - - DFI Timing Register 2 - (OFFSET, MASK, VALUE) (0XFD0701B4, 0x00003F3FU ,0x00000906U) - RegMask = (DDRC_DFITMG2_DFI_TPHY_RDCSLAT_MASK | DDRC_DFITMG2_DFI_TPHY_WRCSLAT_MASK | 0 ); - - RegVal = ((0x00000009U << DDRC_DFITMG2_DFI_TPHY_RDCSLAT_SHIFT - | 0x00000006U << DDRC_DFITMG2_DFI_TPHY_WRCSLAT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DFITMG2_OFFSET ,0x00003F3FU ,0x00000906U); - /*############################################################################################################################ */ - - /*Register : DBICTL @ 0XFD0701C0

- - Read DBI enable signal in DDRC. - 0 - Read DBI is disabled. - 1 - Read DBI is enabled. This signal must be set the same value - as DRAM's mode register. - DDR4: MR5 bit A12. When x4 devices are used, this signal must be set to 0. - LPDDR4: MR3[6] - PSU_DDRC_DBICTL_RD_DBI_EN 0x0 - - Write DBI enable signal in DDRC. - 0 - Write DBI is disabled. - 1 - Write DBI is enabled. This signal must be set the same va - ue as DRAM's mode register. - DDR4: MR5 bit A11. When x4 devices are used, this signal must be set to 0. - LPDDR4: MR3[7] - PSU_DDRC_DBICTL_WR_DBI_EN 0x0 - - DM enable signal in DDRC. - 0 - DM is disabled. - 1 - DM is enabled. This signal must be set the same logical value as DRAM's - mode register. - DDR4: Set this to same value as MR5 bit A10. When x4 devices are used, this signal must be set to 0. - LPDDR - : Set this to inverted value of MR13[5] which is opposite polarity from this signal - PSU_DDRC_DBICTL_DM_EN 0x1 - - DM/DBI Control Register - (OFFSET, MASK, VALUE) (0XFD0701C0, 0x00000007U ,0x00000001U) - RegMask = (DDRC_DBICTL_RD_DBI_EN_MASK | DDRC_DBICTL_WR_DBI_EN_MASK | DDRC_DBICTL_DM_EN_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_DBICTL_RD_DBI_EN_SHIFT - | 0x00000000U << DDRC_DBICTL_WR_DBI_EN_SHIFT - | 0x00000001U << DDRC_DBICTL_DM_EN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DBICTL_OFFSET ,0x00000007U ,0x00000001U); - /*############################################################################################################################ */ - - /*Register : ADDRMAP0 @ 0XFD070200

- - Selects the HIF address bit used as rank address bit 0. Valid Range: 0 to 27, and 31 Internal Base: 6 The selected HIF addres - bit is determined by adding the internal base to the value of this field. If set to 31, rank address bit 0 is set to 0. - PSU_DDRC_ADDRMAP0_ADDRMAP_CS_BIT0 0x1f - - Address Map Register 0 - (OFFSET, MASK, VALUE) (0XFD070200, 0x0000001FU ,0x0000001FU) - RegMask = (DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_MASK | 0 ); - - RegVal = ((0x0000001FU << DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_ADDRMAP0_OFFSET ,0x0000001FU ,0x0000001FU); - /*############################################################################################################################ */ - - /*Register : ADDRMAP1 @ 0XFD070204

- - Selects the HIF address bit used as bank address bit 2. Valid Range: 0 to 29 and 31 Internal Base: 4 The selected HIF address - bit is determined by adding the internal base to the value of this field. If set to 31, bank address bit 2 is set to 0. - PSU_DDRC_ADDRMAP1_ADDRMAP_BANK_B2 0x1f - - Selects the HIF address bits used as bank address bit 1. Valid Range: 0 to 30 Internal Base: 3 The selected HIF address bit f - r each of the bank address bits is determined by adding the internal base to the value of this field. - PSU_DDRC_ADDRMAP1_ADDRMAP_BANK_B1 0xa - - Selects the HIF address bits used as bank address bit 0. Valid Range: 0 to 30 Internal Base: 2 The selected HIF address bit f - r each of the bank address bits is determined by adding the internal base to the value of this field. - PSU_DDRC_ADDRMAP1_ADDRMAP_BANK_B0 0xa - - Address Map Register 1 - (OFFSET, MASK, VALUE) (0XFD070204, 0x001F1F1FU ,0x001F0A0AU) - RegMask = (DDRC_ADDRMAP1_ADDRMAP_BANK_B2_MASK | DDRC_ADDRMAP1_ADDRMAP_BANK_B1_MASK | DDRC_ADDRMAP1_ADDRMAP_BANK_B0_MASK | 0 ); - - RegVal = ((0x0000001FU << DDRC_ADDRMAP1_ADDRMAP_BANK_B2_SHIFT - | 0x0000000AU << DDRC_ADDRMAP1_ADDRMAP_BANK_B1_SHIFT - | 0x0000000AU << DDRC_ADDRMAP1_ADDRMAP_BANK_B0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_ADDRMAP1_OFFSET ,0x001F1F1FU ,0x001F0A0AU); - /*############################################################################################################################ */ - - /*Register : ADDRMAP2 @ 0XFD070208

- - - Full bus width mode: Selects the HIF address bit used as column address bit 5. - Half bus width mode: Selects the HIF addre - s bit used as column address bit 6. - Quarter bus width mode: Selects the HIF address bit used as column address bit 7 . Vali - Range: 0 to 7, and 15 Internal Base: 5 The selected HIF address bit is determined by adding the internal base to the value o - this field. If set to 15, this column address bit is set to 0. - PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B5 0x0 - - - Full bus width mode: Selects the HIF address bit used as column address bit 4. - Half bus width mode: Selects the HIF addre - s bit used as column address bit 5. - Quarter bus width mode: Selects the HIF address bit used as column address bit 6. Valid - Range: 0 to 7, and 15 Internal Base: 4 The selected HIF address bit is determined by adding the internal base to the value of - this field. If set to 15, this column address bit is set to 0. - PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B4 0x0 - - - Full bus width mode: Selects the HIF address bit used as column address bit 3. - Half bus width mode: Selects the HIF addre - s bit used as column address bit 4. - Quarter bus width mode: Selects the HIF address bit used as column address bit 5. Valid - Range: 0 to 7 Internal Base: 3 The selected HIF address bit is determined by adding the internal base to the value of this fi - ld. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=16, it is required to program this to 0, hence register does not exist i - this case. - PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B3 0x0 - - - Full bus width mode: Selects the HIF address bit used as column address bit 2. - Half bus width mode: Selects the HIF addre - s bit used as column address bit 3. - Quarter bus width mode: Selects the HIF address bit used as column address bit 4. Valid - Range: 0 to 7 Internal Base: 2 The selected HIF address bit is determined by adding the internal base to the value of this fi - ld. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=8 or 16, it is required to program this to 0. - PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B2 0x0 - - Address Map Register 2 - (OFFSET, MASK, VALUE) (0XFD070208, 0x0F0F0F0FU ,0x00000000U) - RegMask = (DDRC_ADDRMAP2_ADDRMAP_COL_B5_MASK | DDRC_ADDRMAP2_ADDRMAP_COL_B4_MASK | DDRC_ADDRMAP2_ADDRMAP_COL_B3_MASK | DDRC_ADDRMAP2_ADDRMAP_COL_B2_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_ADDRMAP2_ADDRMAP_COL_B5_SHIFT - | 0x00000000U << DDRC_ADDRMAP2_ADDRMAP_COL_B4_SHIFT - | 0x00000000U << DDRC_ADDRMAP2_ADDRMAP_COL_B3_SHIFT - | 0x00000000U << DDRC_ADDRMAP2_ADDRMAP_COL_B2_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_ADDRMAP2_OFFSET ,0x0F0F0F0FU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : ADDRMAP3 @ 0XFD07020C

- - - Full bus width mode: Selects the HIF address bit used as column address bit 9. - Half bus width mode: Selects the HIF addre - s bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). - Quarter bus width mode: Selects the HIF address bit used as - column address bit 13 (11 in LPDDR2/LPDDR3 mode). Valid Range: 0 to 7, and 15 Internal Base: 9 The selected HIF address bit i - determined by adding the internal base to the value of this field. If set to 15, this column address bit is set to 0. Note: - er JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source addr - ss bit can be mapped to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus an - hence column bit 10 is used. - PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B9 0x0 - - - Full bus width mode: Selects the HIF address bit used as column address bit 8. - Half bus width mode: Selects the HIF addre - s bit used as column address bit 9. - Quarter bus width mode: Selects the HIF address bit used as column address bit 11 (10 i - LPDDR2/LPDDR3 mode). Valid Range: 0 to 7, and 15 Internal Base: 8 The selected HIF address bit is determined by adding the i - ternal base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specif - cation, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to col - mn address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and hence column bit 10 is use - . - PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B8 0x0 - - - Full bus width mode: Selects the HIF address bit used as column address bit 7. - Half bus width mode: Selects the HIF addre - s bit used as column address bit 8. - Quarter bus width mode: Selects the HIF address bit used as column address bit 9. Valid - Range: 0 to 7, and 15 Internal Base: 7 The selected HIF address bit is determined by adding the internal base to the value of - this field. If set to 15, this column address bit is set to 0. - PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B7 0x0 - - - Full bus width mode: Selects the HIF address bit used as column address bit 6. - Half bus width mode: Selects the HIF addre - s bit used as column address bit 7. - Quarter bus width mode: Selects the HIF address bit used as column address bit 8. Valid - Range: 0 to 7, and 15 Internal Base: 6 The selected HIF address bit is determined by adding the internal base to the value of - this field. If set to 15, this column address bit is set to 0. - PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B6 0x0 - - Address Map Register 3 - (OFFSET, MASK, VALUE) (0XFD07020C, 0x0F0F0F0FU ,0x00000000U) - RegMask = (DDRC_ADDRMAP3_ADDRMAP_COL_B9_MASK | DDRC_ADDRMAP3_ADDRMAP_COL_B8_MASK | DDRC_ADDRMAP3_ADDRMAP_COL_B7_MASK | DDRC_ADDRMAP3_ADDRMAP_COL_B6_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_ADDRMAP3_ADDRMAP_COL_B9_SHIFT - | 0x00000000U << DDRC_ADDRMAP3_ADDRMAP_COL_B8_SHIFT - | 0x00000000U << DDRC_ADDRMAP3_ADDRMAP_COL_B7_SHIFT - | 0x00000000U << DDRC_ADDRMAP3_ADDRMAP_COL_B6_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_ADDRMAP3_OFFSET ,0x0F0F0F0FU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : ADDRMAP4 @ 0XFD070210

- - - Full bus width mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode). - Half bus width - mode: Unused. To make it unused, this should be tied to 4'hF. - Quarter bus width mode: Unused. To make it unused, this must - e tied to 4'hF. Valid Range: 0 to 7, and 15 Internal Base: 11 The selected HIF address bit is determined by adding the intern - l base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specificati - n, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column a - dress bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and hence column bit 10 is used. - PSU_DDRC_ADDRMAP4_ADDRMAP_COL_B11 0xf - - - Full bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). - Half bus width - mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode). - Quarter bus width mode: UNUSED. - To make it unused, this must be tied to 4'hF. Valid Range: 0 to 7, and 15 Internal Base: 10 The selected HIF address bit is d - termined by adding the internal base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per - JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source address - bit can be mapped to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and h - nce column bit 10 is used. - PSU_DDRC_ADDRMAP4_ADDRMAP_COL_B10 0xf - - Address Map Register 4 - (OFFSET, MASK, VALUE) (0XFD070210, 0x00000F0FU ,0x00000F0FU) - RegMask = (DDRC_ADDRMAP4_ADDRMAP_COL_B11_MASK | DDRC_ADDRMAP4_ADDRMAP_COL_B10_MASK | 0 ); - - RegVal = ((0x0000000FU << DDRC_ADDRMAP4_ADDRMAP_COL_B11_SHIFT - | 0x0000000FU << DDRC_ADDRMAP4_ADDRMAP_COL_B10_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_ADDRMAP4_OFFSET ,0x00000F0FU ,0x00000F0FU); - /*############################################################################################################################ */ - - /*Register : ADDRMAP5 @ 0XFD070214

- - Selects the HIF address bit used as row address bit 11. Valid Range: 0 to 11, and 15 Internal Base: 17 The selected HIF addre - s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 11 is set to 0. - PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B11 0x8 - - Selects the HIF address bits used as row address bits 2 to 10. Valid Range: 0 to 11, and 15 Internal Base: 8 (for row address - bit 2), 9 (for row address bit 3), 10 (for row address bit 4) etc increasing to 16 (for row address bit 10) The selected HIF - ddress bit for each of the row address bits is determined by adding the internal base to the value of this field. When value - 5 is used the values of row address bits 2 to 10 are defined by registers ADDRMAP9, ADDRMAP10, ADDRMAP11. - PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10 0xf - - Selects the HIF address bits used as row address bit 1. Valid Range: 0 to 11 Internal Base: 7 The selected HIF address bit fo - each of the row address bits is determined by adding the internal base to the value of this field. - PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B1 0x8 - - Selects the HIF address bits used as row address bit 0. Valid Range: 0 to 11 Internal Base: 6 The selected HIF address bit fo - each of the row address bits is determined by adding the internal base to the value of this field. - PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B0 0x8 - - Address Map Register 5 - (OFFSET, MASK, VALUE) (0XFD070214, 0x0F0F0F0FU ,0x080F0808U) - RegMask = (DDRC_ADDRMAP5_ADDRMAP_ROW_B11_MASK | DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_MASK | DDRC_ADDRMAP5_ADDRMAP_ROW_B1_MASK | DDRC_ADDRMAP5_ADDRMAP_ROW_B0_MASK | 0 ); - - RegVal = ((0x00000008U << DDRC_ADDRMAP5_ADDRMAP_ROW_B11_SHIFT - | 0x0000000FU << DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_SHIFT - | 0x00000008U << DDRC_ADDRMAP5_ADDRMAP_ROW_B1_SHIFT - | 0x00000008U << DDRC_ADDRMAP5_ADDRMAP_ROW_B0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_ADDRMAP5_OFFSET ,0x0F0F0F0FU ,0x080F0808U); - /*############################################################################################################################ */ - - /*Register : ADDRMAP6 @ 0XFD070218

- - Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use. - 1 - LPDDR3 SDRAM 6Gb/12Gb device in use. Every address - having row[14:13]==2'b11 is considered as invalid - 0 - non-LPDDR3 6Gb/12Gb device in use. All addresses are valid Present on - y in designs configured to support LPDDR3. - PSU_DDRC_ADDRMAP6_LPDDR3_6GB_12GB 0x0 - - Selects the HIF address bit used as row address bit 15. Valid Range: 0 to 11, and 15 Internal Base: 21 The selected HIF addre - s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 15 is set to 0. - PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B15 0xf - - Selects the HIF address bit used as row address bit 14. Valid Range: 0 to 11, and 15 Internal Base: 20 The selected HIF addre - s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 14 is set to 0. - PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B14 0x8 - - Selects the HIF address bit used as row address bit 13. Valid Range: 0 to 11, and 15 Internal Base: 19 The selected HIF addre - s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 13 is set to 0. - PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B13 0x8 - - Selects the HIF address bit used as row address bit 12. Valid Range: 0 to 11, and 15 Internal Base: 18 The selected HIF addre - s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 12 is set to 0. - PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B12 0x8 - - Address Map Register 6 - (OFFSET, MASK, VALUE) (0XFD070218, 0x8F0F0F0FU ,0x0F080808U) - RegMask = (DDRC_ADDRMAP6_LPDDR3_6GB_12GB_MASK | DDRC_ADDRMAP6_ADDRMAP_ROW_B15_MASK | DDRC_ADDRMAP6_ADDRMAP_ROW_B14_MASK | DDRC_ADDRMAP6_ADDRMAP_ROW_B13_MASK | DDRC_ADDRMAP6_ADDRMAP_ROW_B12_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_ADDRMAP6_LPDDR3_6GB_12GB_SHIFT - | 0x0000000FU << DDRC_ADDRMAP6_ADDRMAP_ROW_B15_SHIFT - | 0x00000008U << DDRC_ADDRMAP6_ADDRMAP_ROW_B14_SHIFT - | 0x00000008U << DDRC_ADDRMAP6_ADDRMAP_ROW_B13_SHIFT - | 0x00000008U << DDRC_ADDRMAP6_ADDRMAP_ROW_B12_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_ADDRMAP6_OFFSET ,0x8F0F0F0FU ,0x0F080808U); - /*############################################################################################################################ */ - - /*Register : ADDRMAP7 @ 0XFD07021C

- - Selects the HIF address bit used as row address bit 17. Valid Range: 0 to 10, and 15 Internal Base: 23 The selected HIF addre - s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 17 is set to 0. - PSU_DDRC_ADDRMAP7_ADDRMAP_ROW_B17 0xf - - Selects the HIF address bit used as row address bit 16. Valid Range: 0 to 11, and 15 Internal Base: 22 The selected HIF addre - s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 16 is set to 0. - PSU_DDRC_ADDRMAP7_ADDRMAP_ROW_B16 0xf - - Address Map Register 7 - (OFFSET, MASK, VALUE) (0XFD07021C, 0x00000F0FU ,0x00000F0FU) - RegMask = (DDRC_ADDRMAP7_ADDRMAP_ROW_B17_MASK | DDRC_ADDRMAP7_ADDRMAP_ROW_B16_MASK | 0 ); - - RegVal = ((0x0000000FU << DDRC_ADDRMAP7_ADDRMAP_ROW_B17_SHIFT - | 0x0000000FU << DDRC_ADDRMAP7_ADDRMAP_ROW_B16_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_ADDRMAP7_OFFSET ,0x00000F0FU ,0x00000F0FU); - /*############################################################################################################################ */ - - /*Register : ADDRMAP8 @ 0XFD070220

- - Selects the HIF address bits used as bank group address bit 1. Valid Range: 0 to 30, and 31 Internal Base: 3 The selected HIF - address bit for each of the bank group address bits is determined by adding the internal base to the value of this field. If - et to 31, bank group address bit 1 is set to 0. - PSU_DDRC_ADDRMAP8_ADDRMAP_BG_B1 0x8 - - Selects the HIF address bits used as bank group address bit 0. Valid Range: 0 to 30 Internal Base: 2 The selected HIF address - bit for each of the bank group address bits is determined by adding the internal base to the value of this field. - PSU_DDRC_ADDRMAP8_ADDRMAP_BG_B0 0x8 - - Address Map Register 8 - (OFFSET, MASK, VALUE) (0XFD070220, 0x00001F1FU ,0x00000808U) - RegMask = (DDRC_ADDRMAP8_ADDRMAP_BG_B1_MASK | DDRC_ADDRMAP8_ADDRMAP_BG_B0_MASK | 0 ); - - RegVal = ((0x00000008U << DDRC_ADDRMAP8_ADDRMAP_BG_B1_SHIFT - | 0x00000008U << DDRC_ADDRMAP8_ADDRMAP_BG_B0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_ADDRMAP8_OFFSET ,0x00001F1FU ,0x00000808U); - /*############################################################################################################################ */ - - /*Register : ADDRMAP9 @ 0XFD070224

- - Selects the HIF address bits used as row address bit 5. Valid Range: 0 to 11 Internal Base: 11 The selected HIF address bit f - r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u - ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15. - PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B5 0x8 - - Selects the HIF address bits used as row address bit 4. Valid Range: 0 to 11 Internal Base: 10 The selected HIF address bit f - r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u - ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15. - PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B4 0x8 - - Selects the HIF address bits used as row address bit 3. Valid Range: 0 to 11 Internal Base: 9 The selected HIF address bit fo - each of the row address bits is determined by adding the internal base to the value of this field. This register field is us - d only when ADDRMAP5.addrmap_row_b2_10 is set to value 15. - PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B3 0x8 - - Selects the HIF address bits used as row address bit 2. Valid Range: 0 to 11 Internal Base: 8 The selected HIF address bit fo - each of the row address bits is determined by adding the internal base to the value of this field. This register field is us - d only when ADDRMAP5.addrmap_row_b2_10 is set to value 15. - PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B2 0x8 - - Address Map Register 9 - (OFFSET, MASK, VALUE) (0XFD070224, 0x0F0F0F0FU ,0x08080808U) - RegMask = (DDRC_ADDRMAP9_ADDRMAP_ROW_B5_MASK | DDRC_ADDRMAP9_ADDRMAP_ROW_B4_MASK | DDRC_ADDRMAP9_ADDRMAP_ROW_B3_MASK | DDRC_ADDRMAP9_ADDRMAP_ROW_B2_MASK | 0 ); - - RegVal = ((0x00000008U << DDRC_ADDRMAP9_ADDRMAP_ROW_B5_SHIFT - | 0x00000008U << DDRC_ADDRMAP9_ADDRMAP_ROW_B4_SHIFT - | 0x00000008U << DDRC_ADDRMAP9_ADDRMAP_ROW_B3_SHIFT - | 0x00000008U << DDRC_ADDRMAP9_ADDRMAP_ROW_B2_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_ADDRMAP9_OFFSET ,0x0F0F0F0FU ,0x08080808U); - /*############################################################################################################################ */ - - /*Register : ADDRMAP10 @ 0XFD070228

- - Selects the HIF address bits used as row address bit 9. Valid Range: 0 to 11 Internal Base: 15 The selected HIF address bit f - r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u - ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15. - PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B9 0x8 - - Selects the HIF address bits used as row address bit 8. Valid Range: 0 to 11 Internal Base: 14 The selected HIF address bit f - r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u - ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15. - PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B8 0x8 - - Selects the HIF address bits used as row address bit 7. Valid Range: 0 to 11 Internal Base: 13 The selected HIF address bit f - r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u - ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15. - PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B7 0x8 - - Selects the HIF address bits used as row address bit 6. Valid Range: 0 to 11 Internal Base: 12 The selected HIF address bit f - r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u - ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15. - PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B6 0x8 - - Address Map Register 10 - (OFFSET, MASK, VALUE) (0XFD070228, 0x0F0F0F0FU ,0x08080808U) - RegMask = (DDRC_ADDRMAP10_ADDRMAP_ROW_B9_MASK | DDRC_ADDRMAP10_ADDRMAP_ROW_B8_MASK | DDRC_ADDRMAP10_ADDRMAP_ROW_B7_MASK | DDRC_ADDRMAP10_ADDRMAP_ROW_B6_MASK | 0 ); - - RegVal = ((0x00000008U << DDRC_ADDRMAP10_ADDRMAP_ROW_B9_SHIFT - | 0x00000008U << DDRC_ADDRMAP10_ADDRMAP_ROW_B8_SHIFT - | 0x00000008U << DDRC_ADDRMAP10_ADDRMAP_ROW_B7_SHIFT - | 0x00000008U << DDRC_ADDRMAP10_ADDRMAP_ROW_B6_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_ADDRMAP10_OFFSET ,0x0F0F0F0FU ,0x08080808U); - /*############################################################################################################################ */ - - /*Register : ADDRMAP11 @ 0XFD07022C

- - Selects the HIF address bits used as row address bit 10. Valid Range: 0 to 11 Internal Base: 16 The selected HIF address bit - or each of the row address bits is determined by adding the internal base to the value of this field. This register field is - sed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15. - PSU_DDRC_ADDRMAP11_ADDRMAP_ROW_B10 0x8 - - Address Map Register 11 - (OFFSET, MASK, VALUE) (0XFD07022C, 0x0000000FU ,0x00000008U) - RegMask = (DDRC_ADDRMAP11_ADDRMAP_ROW_B10_MASK | 0 ); - - RegVal = ((0x00000008U << DDRC_ADDRMAP11_ADDRMAP_ROW_B10_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_ADDRMAP11_OFFSET ,0x0000000FU ,0x00000008U); - /*############################################################################################################################ */ - - /*Register : ODTCFG @ 0XFD070240

- - Cycles to hold ODT for a write command. The minimum supported value is 2. Recommended values: DDR2: - BL8: 0x5 (DDR2-400/533/ - 67), 0x6 (DDR2-800), 0x7 (DDR2-1066) - BL4: 0x3 (DDR2-400/533/667), 0x4 (DDR2-800), 0x5 (DDR2-1066) DDR3: - BL8: 0x6 DDR4: - - L8: 5 + WR_PREAMBLE + CRC_MODE WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) CRC_MODE = 0 (not CRC mode), 1 - CRC mode) LPDDR3: - BL8: 7 + RU(tODTon(max)/tCK) - PSU_DDRC_ODTCFG_WR_ODT_HOLD 0x6 - - The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting must - remain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: - CWL + AL - 3 (DDR2-400/533/ - 67), CWL + AL - 4 (DDR2-800), CWL + AL - 5 (DDR2-1066) If (CWL + AL - 3 < 0), uMCTL2 does not support ODT for write operation - DDR3: - 0x0 DDR4: - DFITMG1.dfi_t_cmd_lat (to adjust for CAL mode) LPDDR3: - WL - 1 - RU(tODTon(max)/tCK)) - PSU_DDRC_ODTCFG_WR_ODT_DELAY 0x0 - - Cycles to hold ODT for a read command. The minimum supported value is 2. Recommended values: DDR2: - BL8: 0x6 (not DDR2-1066) - 0x7 (DDR2-1066) - BL4: 0x4 (not DDR2-1066), 0x5 (DDR2-1066) DDR3: - BL8 - 0x6 DDR4: - BL8: 5 + RD_PREAMBLE RD_PREAMBLE = 1 ( - tCK write preamble), 2 (2tCK write preamble) LPDDR3: - BL8: 5 + RU(tDQSCK(max)/tCK) - RD(tDQSCK(min)/tCK) + RU(tODTon(max)/tC - ) - PSU_DDRC_ODTCFG_RD_ODT_HOLD 0x6 - - The delay, in clock cycles, from issuing a read command to setting ODT values associated with that command. ODT setting must - emain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: - CL + AL - 4 (not DDR2-1066), - CL + AL - 5 (DDR2-1066) If (CL + AL - 4 < 0), uMCTL2 does not support ODT for read operation. DDR3: - CL - CWL DDR4: - CL - C - L - RD_PREAMBLE + WR_PREAMBLE + DFITMG1.dfi_t_cmd_lat (to adjust for CAL mode) WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK - write preamble) RD_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) If (CL - CWL - RD_PREAMBLE + WR_PREAMBLE) < 0, - uMCTL2 does not support ODT for read operation. LPDDR3: - RL + RD(tDQSCK(min)/tCK) - 1 - RU(tODTon(max)/tCK) - PSU_DDRC_ODTCFG_RD_ODT_DELAY 0x0 - - ODT Configuration Register - (OFFSET, MASK, VALUE) (0XFD070240, 0x0F1F0F7CU ,0x06000600U) - RegMask = (DDRC_ODTCFG_WR_ODT_HOLD_MASK | DDRC_ODTCFG_WR_ODT_DELAY_MASK | DDRC_ODTCFG_RD_ODT_HOLD_MASK | DDRC_ODTCFG_RD_ODT_DELAY_MASK | 0 ); - - RegVal = ((0x00000006U << DDRC_ODTCFG_WR_ODT_HOLD_SHIFT - | 0x00000000U << DDRC_ODTCFG_WR_ODT_DELAY_SHIFT - | 0x00000006U << DDRC_ODTCFG_RD_ODT_HOLD_SHIFT - | 0x00000000U << DDRC_ODTCFG_RD_ODT_DELAY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_ODTCFG_OFFSET ,0x0F1F0F7CU ,0x06000600U); - /*############################################################################################################################ */ - - /*Register : ODTMAP @ 0XFD070244

- - Indicates which remote ODTs must be turned on during a read from rank 1. Each rank has a remote ODT (in the SDRAM) which can - e turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB - etc. For each rank, set its bit to 1 to enable its ODT. Present only in configurations that have 2 or more ranks - PSU_DDRC_ODTMAP_RANK1_RD_ODT 0x0 - - Indicates which remote ODTs must be turned on during a write to rank 1. Each rank has a remote ODT (in the SDRAM) which can b - turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB, - etc. For each rank, set its bit to 1 to enable its ODT. Present only in configurations that have 2 or more ranks - PSU_DDRC_ODTMAP_RANK1_WR_ODT 0x0 - - Indicates which remote ODTs must be turned on during a read from rank 0. Each rank has a remote ODT (in the SDRAM) which can - e turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB - etc. For each rank, set its bit to 1 to enable its ODT. - PSU_DDRC_ODTMAP_RANK0_RD_ODT 0x0 - - Indicates which remote ODTs must be turned on during a write to rank 0. Each rank has a remote ODT (in the SDRAM) which can b - turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB, - etc. For each rank, set its bit to 1 to enable its ODT. - PSU_DDRC_ODTMAP_RANK0_WR_ODT 0x1 - - ODT/Rank Map Register - (OFFSET, MASK, VALUE) (0XFD070244, 0x00003333U ,0x00000001U) - RegMask = (DDRC_ODTMAP_RANK1_RD_ODT_MASK | DDRC_ODTMAP_RANK1_WR_ODT_MASK | DDRC_ODTMAP_RANK0_RD_ODT_MASK | DDRC_ODTMAP_RANK0_WR_ODT_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_ODTMAP_RANK1_RD_ODT_SHIFT - | 0x00000000U << DDRC_ODTMAP_RANK1_WR_ODT_SHIFT - | 0x00000000U << DDRC_ODTMAP_RANK0_RD_ODT_SHIFT - | 0x00000001U << DDRC_ODTMAP_RANK0_WR_ODT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_ODTMAP_OFFSET ,0x00003333U ,0x00000001U); - /*############################################################################################################################ */ - - /*Register : SCHED @ 0XFD070250

- - When the preferred transaction store is empty for these many clock cycles, switch to the alternate transaction store if it is - non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write t - ansaction store is the alternative store. When prefer write over read is set this is reversed. 0x0 is a legal value for this - egister. When set to 0x0, the transaction store switching will happen immediately when the switching conditions become true. - OR PERFORMANCE ONLY - PSU_DDRC_SCHED_RDWR_IDLE_GAP 0x1 - - UNUSED - PSU_DDRC_SCHED_GO2CRITICAL_HYSTERESIS 0x0 - - Number of entries in the low priority transaction store is this value + 1. (MEMC_NO_OF_ENTRY - (SCHED.lpr_num_entries + 1)) i - the number of entries available for the high priority transaction store. Setting this to maximum value allocates all entries - to low priority transaction store. Setting this to 0 allocates 1 entry to low priority transaction store and the rest to high - priority transaction store. Note: In ECC configurations, the numbers of write and low priority read credits issued is one les - than in the non-ECC case. One entry each is reserved in the write and low-priority read CAMs for storing the RMW requests ar - sing out of single bit error correction RMW operation. - PSU_DDRC_SCHED_LPR_NUM_ENTRIES 0x20 - - If true, bank is kept open only while there are page hit transactions available in the CAM to that bank. The last read or wri - e command in the CAM with a bank and page hit will be executed with auto-precharge if SCHED1.pageclose_timer=0. Even if this - egister set to 1 and SCHED1.pageclose_timer is set to 0, explicit precharge (and not auto-precharge) may be issued in some ca - es where there is a mode switch between Write and Read or between LPR and HPR. The Read and Write commands that are executed - s part of the ECC scrub requests are also executed without auto-precharge. If false, the bank remains open until there is a n - ed to close it (to open a different page, or for page timeout or refresh timeout) - also known as open page policy. The open - age policy can be overridden by setting the per-command-autopre bit on the HIF interface (hif_cmd_autopre). The pageclose fea - ure provids a midway between Open and Close page policies. FOR PERFORMANCE ONLY. - PSU_DDRC_SCHED_PAGECLOSE 0x0 - - If set then the bank selector prefers writes over reads. FOR DEBUG ONLY. - PSU_DDRC_SCHED_PREFER_WRITE 0x0 - - Active low signal. When asserted ('0'), all incoming transactions are forced to low priority. This implies that all High Prio - ity Read (HPR) and Variable Priority Read commands (VPR) will be treated as Low Priority Read (LPR) commands. On the write si - e, all Variable Priority Write (VPW) commands will be treated as Normal Priority Write (NPW) commands. Forcing the incoming t - ansactions to low priority implicitly turns off Bypass path for read commands. FOR PERFORMANCE ONLY. - PSU_DDRC_SCHED_FORCE_LOW_PRI_N 0x1 - - Scheduler Control Register - (OFFSET, MASK, VALUE) (0XFD070250, 0x7FFF3F07U ,0x01002001U) - RegMask = (DDRC_SCHED_RDWR_IDLE_GAP_MASK | DDRC_SCHED_GO2CRITICAL_HYSTERESIS_MASK | DDRC_SCHED_LPR_NUM_ENTRIES_MASK | DDRC_SCHED_PAGECLOSE_MASK | DDRC_SCHED_PREFER_WRITE_MASK | DDRC_SCHED_FORCE_LOW_PRI_N_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_SCHED_RDWR_IDLE_GAP_SHIFT - | 0x00000000U << DDRC_SCHED_GO2CRITICAL_HYSTERESIS_SHIFT - | 0x00000020U << DDRC_SCHED_LPR_NUM_ENTRIES_SHIFT - | 0x00000000U << DDRC_SCHED_PAGECLOSE_SHIFT - | 0x00000000U << DDRC_SCHED_PREFER_WRITE_SHIFT - | 0x00000001U << DDRC_SCHED_FORCE_LOW_PRI_N_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_SCHED_OFFSET ,0x7FFF3F07U ,0x01002001U); - /*############################################################################################################################ */ - - /*Register : PERFLPR1 @ 0XFD070264

- - Number of transactions that are serviced once the LPR queue goes critical is the smaller of: - (a) This number - (b) Number o - transactions available. Unit: Transaction. FOR PERFORMANCE ONLY. - PSU_DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH 0x8 - - Number of clocks that the LPR queue can be starved before it goes critical. The minimum valid functional value for this regis - er is 0x1. Programming it to 0x0 will disable the starvation functionality; during normal operation, this function should not - be disabled as it will cause excessive latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY. - PSU_DDRC_PERFLPR1_LPR_MAX_STARVE 0x40 - - Low Priority Read CAM Register 1 - (OFFSET, MASK, VALUE) (0XFD070264, 0xFF00FFFFU ,0x08000040U) - RegMask = (DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_MASK | DDRC_PERFLPR1_LPR_MAX_STARVE_MASK | 0 ); - - RegVal = ((0x00000008U << DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_SHIFT - | 0x00000040U << DDRC_PERFLPR1_LPR_MAX_STARVE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PERFLPR1_OFFSET ,0xFF00FFFFU ,0x08000040U); - /*############################################################################################################################ */ - - /*Register : PERFWR1 @ 0XFD07026C

- - Number of transactions that are serviced once the WR queue goes critical is the smaller of: - (a) This number - (b) Number of - transactions available. Unit: Transaction. FOR PERFORMANCE ONLY. - PSU_DDRC_PERFWR1_W_XACT_RUN_LENGTH 0x8 - - Number of clocks that the WR queue can be starved before it goes critical. The minimum valid functional value for this regist - r is 0x1. Programming it to 0x0 will disable the starvation functionality; during normal operation, this function should not - e disabled as it will cause excessive latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY. - PSU_DDRC_PERFWR1_W_MAX_STARVE 0x40 - - Write CAM Register 1 - (OFFSET, MASK, VALUE) (0XFD07026C, 0xFF00FFFFU ,0x08000040U) - RegMask = (DDRC_PERFWR1_W_XACT_RUN_LENGTH_MASK | DDRC_PERFWR1_W_MAX_STARVE_MASK | 0 ); - - RegVal = ((0x00000008U << DDRC_PERFWR1_W_XACT_RUN_LENGTH_SHIFT - | 0x00000040U << DDRC_PERFWR1_W_MAX_STARVE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PERFWR1_OFFSET ,0xFF00FFFFU ,0x08000040U); - /*############################################################################################################################ */ - - /*Register : DQMAP5 @ 0XFD070294

- - All even ranks have the same DQ mapping controled by DQMAP0-4 register as rank 0. This register provides DQ swap function for - all odd ranks to support CRC feature. rank based DQ swapping is: swap bit 0 with 1, swap bit 2 with 3, swap bit 4 with 5 and - wap bit 6 with 7. 1: Disable rank based DQ swapping 0: Enable rank based DQ swapping Present only in designs configured to su - port DDR4. - PSU_DDRC_DQMAP5_DIS_DQ_RANK_SWAP 0x1 - - DQ Map Register 5 - (OFFSET, MASK, VALUE) (0XFD070294, 0x00000001U ,0x00000001U) - RegMask = (DDRC_DQMAP5_DIS_DQ_RANK_SWAP_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_DQMAP5_DIS_DQ_RANK_SWAP_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DQMAP5_OFFSET ,0x00000001U ,0x00000001U); - /*############################################################################################################################ */ - - /*Register : DBG0 @ 0XFD070300

- - When this is set to '0', auto-precharge is disabled for the flushed command in a collision case. Collision cases are write fo - lowed by read to same address, read followed by write to same address, or write followed by write to same address with DBG0.d - s_wc bit = 1 (where same address comparisons exclude the two address bits representing critical word). FOR DEBUG ONLY. - PSU_DDRC_DBG0_DIS_COLLISION_PAGE_OPT 0x0 - - When 1, disable write combine. FOR DEBUG ONLY - PSU_DDRC_DBG0_DIS_WC 0x0 - - Debug Register 0 - (OFFSET, MASK, VALUE) (0XFD070300, 0x00000011U ,0x00000000U) - RegMask = (DDRC_DBG0_DIS_COLLISION_PAGE_OPT_MASK | DDRC_DBG0_DIS_WC_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_DBG0_DIS_COLLISION_PAGE_OPT_SHIFT - | 0x00000000U << DDRC_DBG0_DIS_WC_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DBG0_OFFSET ,0x00000011U ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : DBGCMD @ 0XFD07030C

- - Setting this register bit to 1 allows refresh and ZQCS commands to be triggered from hardware via the IOs ext_*. If set to 1, - the fields DBGCMD.zq_calib_short and DBGCMD.rank*_refresh have no function, and are ignored by the uMCTL2 logic. Setting this - register bit to 0 allows refresh and ZQCS to be triggered from software, via the fields DBGCMD.zq_calib_short and DBGCMD.rank - _refresh. If set to 0, the hardware pins ext_* have no function, and are ignored by the uMCTL2 logic. This register is static - and may only be changed when the DDRC reset signal, core_ddrc_rstn, is asserted (0). - PSU_DDRC_DBGCMD_HW_REF_ZQ_EN 0x0 - - Setting this register bit to 1 indicates to the uMCTL2 to issue a dfi_ctrlupd_req to the PHY. When this request is stored in - he uMCTL2, the bit is automatically cleared. This operation must only be performed when DFIUPD0.dis_auto_ctrlupd=1. - PSU_DDRC_DBGCMD_CTRLUPD 0x0 - - Setting this register bit to 1 indicates to the uMCTL2 to issue a ZQCS (ZQ calibration short)/MPC(ZQ calibration) command to - he SDRAM. When this request is stored in the uMCTL2, the bit is automatically cleared. This operation can be performed only w - en ZQCTL0.dis_auto_zq=1. It is recommended NOT to set this register bit if in Init operating mode. This register bit is ignor - d when in Self-Refresh(except LPDDR4) and SR-Powerdown(LPDDR4) and Deep power-down operating modes and Maximum Power Saving M - de. - PSU_DDRC_DBGCMD_ZQ_CALIB_SHORT 0x0 - - Setting this register bit to 1 indicates to the uMCTL2 to issue a refresh to rank 1. Writing to this bit causes DBGSTAT.rank1 - refresh_busy to be set. When DBGSTAT.rank1_refresh_busy is cleared, the command has been stored in uMCTL2. This operation can - be performed only when RFSHCTL3.dis_auto_refresh=1. It is recommended NOT to set this register bit if in Init or Deep power-d - wn operating modes or Maximum Power Saving Mode. - PSU_DDRC_DBGCMD_RANK1_REFRESH 0x0 - - Setting this register bit to 1 indicates to the uMCTL2 to issue a refresh to rank 0. Writing to this bit causes DBGSTAT.rank0 - refresh_busy to be set. When DBGSTAT.rank0_refresh_busy is cleared, the command has been stored in uMCTL2. This operation can - be performed only when RFSHCTL3.dis_auto_refresh=1. It is recommended NOT to set this register bit if in Init or Deep power-d - wn operating modes or Maximum Power Saving Mode. - PSU_DDRC_DBGCMD_RANK0_REFRESH 0x0 - - Command Debug Register - (OFFSET, MASK, VALUE) (0XFD07030C, 0x80000033U ,0x00000000U) - RegMask = (DDRC_DBGCMD_HW_REF_ZQ_EN_MASK | DDRC_DBGCMD_CTRLUPD_MASK | DDRC_DBGCMD_ZQ_CALIB_SHORT_MASK | DDRC_DBGCMD_RANK1_REFRESH_MASK | DDRC_DBGCMD_RANK0_REFRESH_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_DBGCMD_HW_REF_ZQ_EN_SHIFT - | 0x00000000U << DDRC_DBGCMD_CTRLUPD_SHIFT - | 0x00000000U << DDRC_DBGCMD_ZQ_CALIB_SHORT_SHIFT - | 0x00000000U << DDRC_DBGCMD_RANK1_REFRESH_SHIFT - | 0x00000000U << DDRC_DBGCMD_RANK0_REFRESH_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DBGCMD_OFFSET ,0x80000033U ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : SWCTL @ 0XFD070320

- - Enable quasi-dynamic register programming outside reset. Program register to 0 to enable quasi-dynamic programming. Set back - egister to 1 once programming is done. - PSU_DDRC_SWCTL_SW_DONE 0x0 - - Software register programming control enable - (OFFSET, MASK, VALUE) (0XFD070320, 0x00000001U ,0x00000000U) - RegMask = (DDRC_SWCTL_SW_DONE_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_SWCTL_SW_DONE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_SWCTL_OFFSET ,0x00000001U ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : PCCFG @ 0XFD070400

- - Burst length expansion mode. By default (i.e. bl_exp_mode==0) XPI expands every AXI burst into multiple HIF commands, using t - e memory burst length as a unit. If set to 1, then XPI will use half of the memory burst length as a unit. This applies to bo - h reads and writes. When MSTR.data_bus_width==00, setting bl_exp_mode to 1 has no effect. This can be used in cases where Par - ial Writes is enabled (UMCTL2_PARTIAL_WR=1) and DBG0.dis_wc=1, in order to avoid or minimize t_ccd_l penalty in DDR4 and t_cc - _mw penalty in LPDDR4. Note that if DBICTL.reg_ddrc_dm_en=0, functionality is not supported in the following cases: - UMCTL2_ - ARTIAL_WR=0 - UMCTL2_PARTIAL_WR=1, MSTR.reg_ddrc_data_bus_width=01, MEMC_BURST_LENGTH=8 and MSTR.reg_ddrc_burst_rdwr=1000 (LP - DR4 only) - UMCTL2_PARTIAL_WR=1, MSTR.reg_ddrc_data_bus_width=01, MEMC_BURST_LENGTH=4 and MSTR.reg_ddrc_burst_rdwr=0100 (DDR4 - only), with either MSTR.reg_ddrc_burstchop=0 or CRCPARCTL1.reg_ddrc_crc_enable=1 Functionality is also not supported if Share - -AC is enabled - PSU_DDRC_PCCFG_BL_EXP_MODE 0x0 - - Page match four limit. If set to 1, limits the number of consecutive same page DDRC transactions that can be granted by the P - rt Arbiter to four when Page Match feature is enabled. If set to 0, there is no limit imposed on number of consecutive same p - ge DDRC transactions. - PSU_DDRC_PCCFG_PAGEMATCH_LIMIT 0x0 - - If set to 1 (enabled), sets co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals going to DDRC based - n urgent input (awurgent, arurgent) coming from AXI master. If set to 0 (disabled), co_gs_go2critical_wr and co_gs_go2critica - _lpr/co_gs_go2critical_hpr signals at DDRC are driven to 1b'0. - PSU_DDRC_PCCFG_GO2CRITICAL_EN 0x1 - - Port Common Configuration Register - (OFFSET, MASK, VALUE) (0XFD070400, 0x00000111U ,0x00000001U) - RegMask = (DDRC_PCCFG_BL_EXP_MODE_MASK | DDRC_PCCFG_PAGEMATCH_LIMIT_MASK | DDRC_PCCFG_GO2CRITICAL_EN_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_PCCFG_BL_EXP_MODE_SHIFT - | 0x00000000U << DDRC_PCCFG_PAGEMATCH_LIMIT_SHIFT - | 0x00000001U << DDRC_PCCFG_GO2CRITICAL_EN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCCFG_OFFSET ,0x00000111U ,0x00000001U); - /*############################################################################################################################ */ - - /*Register : PCFGR_0 @ 0XFD070404

- - If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register. - PSU_DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN 0x0 - - If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG. - o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add - ess handshaking (it is not associated with any particular command). - PSU_DDRC_PCFGR_0_RD_PORT_URGENT_EN 0x1 - - If set to 1, enables aging function for the read channel of the port. - PSU_DDRC_PCFGR_0_RD_PORT_AGING_EN 0x0 - - Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g - ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority - will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre - ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the - aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st - ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w - ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D - RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: - he two LSBs of this register field are tied internally to 2'b00. - PSU_DDRC_PCFGR_0_RD_PORT_PRIORITY 0xf - - Port n Configuration Read Register - (OFFSET, MASK, VALUE) (0XFD070404, 0x000073FFU ,0x0000200FU) - RegMask = (DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGR_0_RD_PORT_URGENT_EN_MASK | DDRC_PCFGR_0_RD_PORT_AGING_EN_MASK | DDRC_PCFGR_0_RD_PORT_PRIORITY_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_SHIFT - | 0x00000001U << DDRC_PCFGR_0_RD_PORT_URGENT_EN_SHIFT - | 0x00000000U << DDRC_PCFGR_0_RD_PORT_AGING_EN_SHIFT - | 0x0000000FU << DDRC_PCFGR_0_RD_PORT_PRIORITY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGR_0_OFFSET ,0x000073FFU ,0x0000200FU); - /*############################################################################################################################ */ - - /*Register : PCFGW_0 @ 0XFD070408

- - If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register. - PSU_DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN 0x1 - - If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register - Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is - not associated with any particular command). - PSU_DDRC_PCFGW_0_WR_PORT_URGENT_EN 0x1 - - If set to 1, enables aging function for the write channel of the port. - PSU_DDRC_PCFGW_0_WR_PORT_AGING_EN 0x0 - - Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each - rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port - s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0 - the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno - be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For - ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch - ng. Note: The two LSBs of this register field are tied internally to 2'b00. - PSU_DDRC_PCFGW_0_WR_PORT_PRIORITY 0xf - - Port n Configuration Write Register - (OFFSET, MASK, VALUE) (0XFD070408, 0x000073FFU ,0x0000600FU) - RegMask = (DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGW_0_WR_PORT_URGENT_EN_MASK | DDRC_PCFGW_0_WR_PORT_AGING_EN_MASK | DDRC_PCFGW_0_WR_PORT_PRIORITY_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_SHIFT - | 0x00000001U << DDRC_PCFGW_0_WR_PORT_URGENT_EN_SHIFT - | 0x00000000U << DDRC_PCFGW_0_WR_PORT_AGING_EN_SHIFT - | 0x0000000FU << DDRC_PCFGW_0_WR_PORT_PRIORITY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGW_0_OFFSET ,0x000073FFU ,0x0000600FU); - /*############################################################################################################################ */ - - /*Register : PCTRL_0 @ 0XFD070490

- - Enables port n. - PSU_DDRC_PCTRL_0_PORT_EN 0x1 - - Port n Control Register - (OFFSET, MASK, VALUE) (0XFD070490, 0x00000001U ,0x00000001U) - RegMask = (DDRC_PCTRL_0_PORT_EN_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_PCTRL_0_PORT_EN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCTRL_0_OFFSET ,0x00000001U ,0x00000001U); - /*############################################################################################################################ */ - - /*Register : PCFGQOS0_0 @ 0XFD070494

- - This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf - gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is - disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. - PSU_DDRC_PCFGQOS0_0_RQOS_MAP_REGION1 0x2 - - This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi - urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i - disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. - PSU_DDRC_PCFGQOS0_0_RQOS_MAP_REGION0 0x0 - - Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d - al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio - ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc - values. - PSU_DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1 0xb - - Port n Read QoS Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD070494, 0x0033000FU ,0x0020000BU) - RegMask = (DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_MASK | DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_MASK | DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_MASK | 0 ); - - RegVal = ((0x00000002U << DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_SHIFT - | 0x00000000U << DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_SHIFT - | 0x0000000BU << DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGQOS0_0_OFFSET ,0x0033000FU ,0x0020000BU); - /*############################################################################################################################ */ - - /*Register : PCFGQOS1_0 @ 0XFD070498

- - Specifies the timeout value for transactions mapped to the red address queue. - PSU_DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR 0x0 - - Specifies the timeout value for transactions mapped to the blue address queue. - PSU_DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB 0x0 - - Port n Read QoS Configuration Register 1 - (OFFSET, MASK, VALUE) (0XFD070498, 0x07FF07FFU ,0x00000000U) - RegMask = (DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_MASK | DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_SHIFT - | 0x00000000U << DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGQOS1_0_OFFSET ,0x07FF07FFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : PCFGR_1 @ 0XFD0704B4

- - If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register. - PSU_DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN 0x0 - - If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG. - o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add - ess handshaking (it is not associated with any particular command). - PSU_DDRC_PCFGR_1_RD_PORT_URGENT_EN 0x1 - - If set to 1, enables aging function for the read channel of the port. - PSU_DDRC_PCFGR_1_RD_PORT_AGING_EN 0x0 - - Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g - ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority - will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre - ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the - aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st - ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w - ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D - RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: - he two LSBs of this register field are tied internally to 2'b00. - PSU_DDRC_PCFGR_1_RD_PORT_PRIORITY 0xf - - Port n Configuration Read Register - (OFFSET, MASK, VALUE) (0XFD0704B4, 0x000073FFU ,0x0000200FU) - RegMask = (DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGR_1_RD_PORT_URGENT_EN_MASK | DDRC_PCFGR_1_RD_PORT_AGING_EN_MASK | DDRC_PCFGR_1_RD_PORT_PRIORITY_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_SHIFT - | 0x00000001U << DDRC_PCFGR_1_RD_PORT_URGENT_EN_SHIFT - | 0x00000000U << DDRC_PCFGR_1_RD_PORT_AGING_EN_SHIFT - | 0x0000000FU << DDRC_PCFGR_1_RD_PORT_PRIORITY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGR_1_OFFSET ,0x000073FFU ,0x0000200FU); - /*############################################################################################################################ */ - - /*Register : PCFGW_1 @ 0XFD0704B8

- - If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register. - PSU_DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN 0x1 - - If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register - Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is - not associated with any particular command). - PSU_DDRC_PCFGW_1_WR_PORT_URGENT_EN 0x1 - - If set to 1, enables aging function for the write channel of the port. - PSU_DDRC_PCFGW_1_WR_PORT_AGING_EN 0x0 - - Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each - rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port - s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0 - the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno - be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For - ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch - ng. Note: The two LSBs of this register field are tied internally to 2'b00. - PSU_DDRC_PCFGW_1_WR_PORT_PRIORITY 0xf - - Port n Configuration Write Register - (OFFSET, MASK, VALUE) (0XFD0704B8, 0x000073FFU ,0x0000600FU) - RegMask = (DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGW_1_WR_PORT_URGENT_EN_MASK | DDRC_PCFGW_1_WR_PORT_AGING_EN_MASK | DDRC_PCFGW_1_WR_PORT_PRIORITY_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_SHIFT - | 0x00000001U << DDRC_PCFGW_1_WR_PORT_URGENT_EN_SHIFT - | 0x00000000U << DDRC_PCFGW_1_WR_PORT_AGING_EN_SHIFT - | 0x0000000FU << DDRC_PCFGW_1_WR_PORT_PRIORITY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGW_1_OFFSET ,0x000073FFU ,0x0000600FU); - /*############################################################################################################################ */ - - /*Register : PCTRL_1 @ 0XFD070540

- - Enables port n. - PSU_DDRC_PCTRL_1_PORT_EN 0x1 - - Port n Control Register - (OFFSET, MASK, VALUE) (0XFD070540, 0x00000001U ,0x00000001U) - RegMask = (DDRC_PCTRL_1_PORT_EN_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_PCTRL_1_PORT_EN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCTRL_1_OFFSET ,0x00000001U ,0x00000001U); - /*############################################################################################################################ */ - - /*Register : PCFGQOS0_1 @ 0XFD070544

- - This bitfield indicates the traffic class of region2. For dual address queue configurations, region2 maps to the red address - ueue. Valid values are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and traffic class of region2 - s set to 1 (VPR), VPR traffic is aliased to LPR traffic. - PSU_DDRC_PCFGQOS0_1_RQOS_MAP_REGION2 0x2 - - This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf - gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is - disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. - PSU_DDRC_PCFGQOS0_1_RQOS_MAP_REGION1 0x0 - - This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi - urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i - disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. - PSU_DDRC_PCFGQOS0_1_RQOS_MAP_REGION0 0x0 - - Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (le - el1 + 1) to 14 which corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note that for PA, arqos values are used - directly as port priorities, where the higher the value corresponds to higher port priority. All of the map_level* registers - ust be set to distinct values. - PSU_DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2 0xb - - Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d - al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio - ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc - values. - PSU_DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1 0x3 - - Port n Read QoS Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD070544, 0x03330F0FU ,0x02000B03U) - RegMask = (DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_MASK | DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_MASK | DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_MASK | DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_MASK | DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_MASK | 0 ); - - RegVal = ((0x00000002U << DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_SHIFT - | 0x00000000U << DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_SHIFT - | 0x00000000U << DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_SHIFT - | 0x0000000BU << DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_SHIFT - | 0x00000003U << DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGQOS0_1_OFFSET ,0x03330F0FU ,0x02000B03U); - /*############################################################################################################################ */ - - /*Register : PCFGQOS1_1 @ 0XFD070548

- - Specifies the timeout value for transactions mapped to the red address queue. - PSU_DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR 0x0 - - Specifies the timeout value for transactions mapped to the blue address queue. - PSU_DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB 0x0 - - Port n Read QoS Configuration Register 1 - (OFFSET, MASK, VALUE) (0XFD070548, 0x07FF07FFU ,0x00000000U) - RegMask = (DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_MASK | DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_SHIFT - | 0x00000000U << DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGQOS1_1_OFFSET ,0x07FF07FFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : PCFGR_2 @ 0XFD070564

- - If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register. - PSU_DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN 0x0 - - If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG. - o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add - ess handshaking (it is not associated with any particular command). - PSU_DDRC_PCFGR_2_RD_PORT_URGENT_EN 0x1 - - If set to 1, enables aging function for the read channel of the port. - PSU_DDRC_PCFGR_2_RD_PORT_AGING_EN 0x0 - - Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g - ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority - will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre - ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the - aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st - ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w - ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D - RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: - he two LSBs of this register field are tied internally to 2'b00. - PSU_DDRC_PCFGR_2_RD_PORT_PRIORITY 0xf - - Port n Configuration Read Register - (OFFSET, MASK, VALUE) (0XFD070564, 0x000073FFU ,0x0000200FU) - RegMask = (DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGR_2_RD_PORT_URGENT_EN_MASK | DDRC_PCFGR_2_RD_PORT_AGING_EN_MASK | DDRC_PCFGR_2_RD_PORT_PRIORITY_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_SHIFT - | 0x00000001U << DDRC_PCFGR_2_RD_PORT_URGENT_EN_SHIFT - | 0x00000000U << DDRC_PCFGR_2_RD_PORT_AGING_EN_SHIFT - | 0x0000000FU << DDRC_PCFGR_2_RD_PORT_PRIORITY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGR_2_OFFSET ,0x000073FFU ,0x0000200FU); - /*############################################################################################################################ */ - - /*Register : PCFGW_2 @ 0XFD070568

- - If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register. - PSU_DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN 0x1 - - If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register - Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is - not associated with any particular command). - PSU_DDRC_PCFGW_2_WR_PORT_URGENT_EN 0x1 - - If set to 1, enables aging function for the write channel of the port. - PSU_DDRC_PCFGW_2_WR_PORT_AGING_EN 0x0 - - Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each - rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port - s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0 - the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno - be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For - ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch - ng. Note: The two LSBs of this register field are tied internally to 2'b00. - PSU_DDRC_PCFGW_2_WR_PORT_PRIORITY 0xf - - Port n Configuration Write Register - (OFFSET, MASK, VALUE) (0XFD070568, 0x000073FFU ,0x0000600FU) - RegMask = (DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGW_2_WR_PORT_URGENT_EN_MASK | DDRC_PCFGW_2_WR_PORT_AGING_EN_MASK | DDRC_PCFGW_2_WR_PORT_PRIORITY_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_SHIFT - | 0x00000001U << DDRC_PCFGW_2_WR_PORT_URGENT_EN_SHIFT - | 0x00000000U << DDRC_PCFGW_2_WR_PORT_AGING_EN_SHIFT - | 0x0000000FU << DDRC_PCFGW_2_WR_PORT_PRIORITY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGW_2_OFFSET ,0x000073FFU ,0x0000600FU); - /*############################################################################################################################ */ - - /*Register : PCTRL_2 @ 0XFD0705F0

- - Enables port n. - PSU_DDRC_PCTRL_2_PORT_EN 0x1 - - Port n Control Register - (OFFSET, MASK, VALUE) (0XFD0705F0, 0x00000001U ,0x00000001U) - RegMask = (DDRC_PCTRL_2_PORT_EN_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_PCTRL_2_PORT_EN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCTRL_2_OFFSET ,0x00000001U ,0x00000001U); - /*############################################################################################################################ */ - - /*Register : PCFGQOS0_2 @ 0XFD0705F4

- - This bitfield indicates the traffic class of region2. For dual address queue configurations, region2 maps to the red address - ueue. Valid values are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and traffic class of region2 - s set to 1 (VPR), VPR traffic is aliased to LPR traffic. - PSU_DDRC_PCFGQOS0_2_RQOS_MAP_REGION2 0x2 - - This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf - gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is - disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. - PSU_DDRC_PCFGQOS0_2_RQOS_MAP_REGION1 0x0 - - This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi - urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i - disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. - PSU_DDRC_PCFGQOS0_2_RQOS_MAP_REGION0 0x0 - - Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (le - el1 + 1) to 14 which corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note that for PA, arqos values are used - directly as port priorities, where the higher the value corresponds to higher port priority. All of the map_level* registers - ust be set to distinct values. - PSU_DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2 0xb - - Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d - al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio - ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc - values. - PSU_DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1 0x3 - - Port n Read QoS Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD0705F4, 0x03330F0FU ,0x02000B03U) - RegMask = (DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_MASK | DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_MASK | DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_MASK | DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_MASK | DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_MASK | 0 ); - - RegVal = ((0x00000002U << DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_SHIFT - | 0x00000000U << DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_SHIFT - | 0x00000000U << DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_SHIFT - | 0x0000000BU << DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_SHIFT - | 0x00000003U << DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGQOS0_2_OFFSET ,0x03330F0FU ,0x02000B03U); - /*############################################################################################################################ */ - - /*Register : PCFGQOS1_2 @ 0XFD0705F8

- - Specifies the timeout value for transactions mapped to the red address queue. - PSU_DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR 0x0 - - Specifies the timeout value for transactions mapped to the blue address queue. - PSU_DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB 0x0 - - Port n Read QoS Configuration Register 1 - (OFFSET, MASK, VALUE) (0XFD0705F8, 0x07FF07FFU ,0x00000000U) - RegMask = (DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_MASK | DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_SHIFT - | 0x00000000U << DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGQOS1_2_OFFSET ,0x07FF07FFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : PCFGR_3 @ 0XFD070614

- - If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register. - PSU_DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN 0x0 - - If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG. - o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add - ess handshaking (it is not associated with any particular command). - PSU_DDRC_PCFGR_3_RD_PORT_URGENT_EN 0x1 - - If set to 1, enables aging function for the read channel of the port. - PSU_DDRC_PCFGR_3_RD_PORT_AGING_EN 0x0 - - Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g - ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority - will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre - ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the - aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st - ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w - ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D - RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: - he two LSBs of this register field are tied internally to 2'b00. - PSU_DDRC_PCFGR_3_RD_PORT_PRIORITY 0xf - - Port n Configuration Read Register - (OFFSET, MASK, VALUE) (0XFD070614, 0x000073FFU ,0x0000200FU) - RegMask = (DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGR_3_RD_PORT_URGENT_EN_MASK | DDRC_PCFGR_3_RD_PORT_AGING_EN_MASK | DDRC_PCFGR_3_RD_PORT_PRIORITY_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_SHIFT - | 0x00000001U << DDRC_PCFGR_3_RD_PORT_URGENT_EN_SHIFT - | 0x00000000U << DDRC_PCFGR_3_RD_PORT_AGING_EN_SHIFT - | 0x0000000FU << DDRC_PCFGR_3_RD_PORT_PRIORITY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGR_3_OFFSET ,0x000073FFU ,0x0000200FU); - /*############################################################################################################################ */ - - /*Register : PCFGW_3 @ 0XFD070618

- - If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register. - PSU_DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN 0x1 - - If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register - Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is - not associated with any particular command). - PSU_DDRC_PCFGW_3_WR_PORT_URGENT_EN 0x1 - - If set to 1, enables aging function for the write channel of the port. - PSU_DDRC_PCFGW_3_WR_PORT_AGING_EN 0x0 - - Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each - rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port - s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0 - the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno - be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For - ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch - ng. Note: The two LSBs of this register field are tied internally to 2'b00. - PSU_DDRC_PCFGW_3_WR_PORT_PRIORITY 0xf - - Port n Configuration Write Register - (OFFSET, MASK, VALUE) (0XFD070618, 0x000073FFU ,0x0000600FU) - RegMask = (DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGW_3_WR_PORT_URGENT_EN_MASK | DDRC_PCFGW_3_WR_PORT_AGING_EN_MASK | DDRC_PCFGW_3_WR_PORT_PRIORITY_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_SHIFT - | 0x00000001U << DDRC_PCFGW_3_WR_PORT_URGENT_EN_SHIFT - | 0x00000000U << DDRC_PCFGW_3_WR_PORT_AGING_EN_SHIFT - | 0x0000000FU << DDRC_PCFGW_3_WR_PORT_PRIORITY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGW_3_OFFSET ,0x000073FFU ,0x0000600FU); - /*############################################################################################################################ */ - - /*Register : PCTRL_3 @ 0XFD0706A0

- - Enables port n. - PSU_DDRC_PCTRL_3_PORT_EN 0x1 - - Port n Control Register - (OFFSET, MASK, VALUE) (0XFD0706A0, 0x00000001U ,0x00000001U) - RegMask = (DDRC_PCTRL_3_PORT_EN_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_PCTRL_3_PORT_EN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCTRL_3_OFFSET ,0x00000001U ,0x00000001U); - /*############################################################################################################################ */ - - /*Register : PCFGQOS0_3 @ 0XFD0706A4

- - This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf - gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is - disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. - PSU_DDRC_PCFGQOS0_3_RQOS_MAP_REGION1 0x1 - - This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi - urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i - disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. - PSU_DDRC_PCFGQOS0_3_RQOS_MAP_REGION0 0x0 - - Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d - al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio - ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc - values. - PSU_DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1 0x3 - - Port n Read QoS Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD0706A4, 0x0033000FU ,0x00100003U) - RegMask = (DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_MASK | DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_MASK | DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_SHIFT - | 0x00000000U << DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_SHIFT - | 0x00000003U << DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGQOS0_3_OFFSET ,0x0033000FU ,0x00100003U); - /*############################################################################################################################ */ - - /*Register : PCFGQOS1_3 @ 0XFD0706A8

- - Specifies the timeout value for transactions mapped to the red address queue. - PSU_DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR 0x0 - - Specifies the timeout value for transactions mapped to the blue address queue. - PSU_DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB 0x4f - - Port n Read QoS Configuration Register 1 - (OFFSET, MASK, VALUE) (0XFD0706A8, 0x07FF07FFU ,0x0000004FU) - RegMask = (DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_MASK | DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_SHIFT - | 0x0000004FU << DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGQOS1_3_OFFSET ,0x07FF07FFU ,0x0000004FU); - /*############################################################################################################################ */ - - /*Register : PCFGWQOS0_3 @ 0XFD0706AC

- - This bitfield indicates the traffic class of region 1. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2 - VPW_EN = 0) and traffic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW traffic. - PSU_DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1 0x1 - - This bitfield indicates the traffic class of region 0. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2 - VPW_EN = 0) and traffic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW traffic. - PSU_DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0 0x0 - - Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 14 which c - rresponds to awqos. Note that for PA, awqos values are used directly as port priorities, where the higher the value correspon - s to higher port priority. - PSU_DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL 0x3 - - Port n Write QoS Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD0706AC, 0x0033000FU ,0x00100003U) - RegMask = (DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_MASK | DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_MASK | DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_SHIFT - | 0x00000000U << DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_SHIFT - | 0x00000003U << DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGWQOS0_3_OFFSET ,0x0033000FU ,0x00100003U); - /*############################################################################################################################ */ - - /*Register : PCFGWQOS1_3 @ 0XFD0706B0

- - Specifies the timeout value for write transactions. - PSU_DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT 0x4f - - Port n Write QoS Configuration Register 1 - (OFFSET, MASK, VALUE) (0XFD0706B0, 0x000007FFU ,0x0000004FU) - RegMask = (DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_MASK | 0 ); - - RegVal = ((0x0000004FU << DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGWQOS1_3_OFFSET ,0x000007FFU ,0x0000004FU); - /*############################################################################################################################ */ - - /*Register : PCFGR_4 @ 0XFD0706C4

- - If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register. - PSU_DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN 0x1 - - If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG. - o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add - ess handshaking (it is not associated with any particular command). - PSU_DDRC_PCFGR_4_RD_PORT_URGENT_EN 0x1 - - If set to 1, enables aging function for the read channel of the port. - PSU_DDRC_PCFGR_4_RD_PORT_AGING_EN 0x0 - - Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g - ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority - will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre - ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the - aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st - ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w - ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D - RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: - he two LSBs of this register field are tied internally to 2'b00. - PSU_DDRC_PCFGR_4_RD_PORT_PRIORITY 0xf - - Port n Configuration Read Register - (OFFSET, MASK, VALUE) (0XFD0706C4, 0x000073FFU ,0x0000600FU) - RegMask = (DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGR_4_RD_PORT_URGENT_EN_MASK | DDRC_PCFGR_4_RD_PORT_AGING_EN_MASK | DDRC_PCFGR_4_RD_PORT_PRIORITY_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_SHIFT - | 0x00000001U << DDRC_PCFGR_4_RD_PORT_URGENT_EN_SHIFT - | 0x00000000U << DDRC_PCFGR_4_RD_PORT_AGING_EN_SHIFT - | 0x0000000FU << DDRC_PCFGR_4_RD_PORT_PRIORITY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGR_4_OFFSET ,0x000073FFU ,0x0000600FU); - /*############################################################################################################################ */ - - /*Register : PCFGW_4 @ 0XFD0706C8

- - If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register. - PSU_DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN 0x1 - - If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register - Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is - not associated with any particular command). - PSU_DDRC_PCFGW_4_WR_PORT_URGENT_EN 0x1 - - If set to 1, enables aging function for the write channel of the port. - PSU_DDRC_PCFGW_4_WR_PORT_AGING_EN 0x0 - - Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each - rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port - s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0 - the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno - be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For - ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch - ng. Note: The two LSBs of this register field are tied internally to 2'b00. - PSU_DDRC_PCFGW_4_WR_PORT_PRIORITY 0xf - - Port n Configuration Write Register - (OFFSET, MASK, VALUE) (0XFD0706C8, 0x000073FFU ,0x0000600FU) - RegMask = (DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGW_4_WR_PORT_URGENT_EN_MASK | DDRC_PCFGW_4_WR_PORT_AGING_EN_MASK | DDRC_PCFGW_4_WR_PORT_PRIORITY_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_SHIFT - | 0x00000001U << DDRC_PCFGW_4_WR_PORT_URGENT_EN_SHIFT - | 0x00000000U << DDRC_PCFGW_4_WR_PORT_AGING_EN_SHIFT - | 0x0000000FU << DDRC_PCFGW_4_WR_PORT_PRIORITY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGW_4_OFFSET ,0x000073FFU ,0x0000600FU); - /*############################################################################################################################ */ - - /*Register : PCTRL_4 @ 0XFD070750

- - Enables port n. - PSU_DDRC_PCTRL_4_PORT_EN 0x1 - - Port n Control Register - (OFFSET, MASK, VALUE) (0XFD070750, 0x00000001U ,0x00000001U) - RegMask = (DDRC_PCTRL_4_PORT_EN_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_PCTRL_4_PORT_EN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCTRL_4_OFFSET ,0x00000001U ,0x00000001U); - /*############################################################################################################################ */ - - /*Register : PCFGQOS0_4 @ 0XFD070754

- - This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf - gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is - disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. - PSU_DDRC_PCFGQOS0_4_RQOS_MAP_REGION1 0x1 - - This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi - urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i - disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. - PSU_DDRC_PCFGQOS0_4_RQOS_MAP_REGION0 0x0 - - Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d - al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio - ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc - values. - PSU_DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1 0x3 - - Port n Read QoS Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD070754, 0x0033000FU ,0x00100003U) - RegMask = (DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_MASK | DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_MASK | DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_SHIFT - | 0x00000000U << DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_SHIFT - | 0x00000003U << DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGQOS0_4_OFFSET ,0x0033000FU ,0x00100003U); - /*############################################################################################################################ */ - - /*Register : PCFGQOS1_4 @ 0XFD070758

- - Specifies the timeout value for transactions mapped to the red address queue. - PSU_DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR 0x0 - - Specifies the timeout value for transactions mapped to the blue address queue. - PSU_DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB 0x4f - - Port n Read QoS Configuration Register 1 - (OFFSET, MASK, VALUE) (0XFD070758, 0x07FF07FFU ,0x0000004FU) - RegMask = (DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_MASK | DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_SHIFT - | 0x0000004FU << DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGQOS1_4_OFFSET ,0x07FF07FFU ,0x0000004FU); - /*############################################################################################################################ */ - - /*Register : PCFGWQOS0_4 @ 0XFD07075C

- - This bitfield indicates the traffic class of region 1. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2 - VPW_EN = 0) and traffic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW traffic. - PSU_DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1 0x1 - - This bitfield indicates the traffic class of region 0. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2 - VPW_EN = 0) and traffic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW traffic. - PSU_DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0 0x0 - - Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 14 which c - rresponds to awqos. Note that for PA, awqos values are used directly as port priorities, where the higher the value correspon - s to higher port priority. - PSU_DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL 0x3 - - Port n Write QoS Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD07075C, 0x0033000FU ,0x00100003U) - RegMask = (DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_MASK | DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_MASK | DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_SHIFT - | 0x00000000U << DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_SHIFT - | 0x00000003U << DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGWQOS0_4_OFFSET ,0x0033000FU ,0x00100003U); - /*############################################################################################################################ */ - - /*Register : PCFGWQOS1_4 @ 0XFD070760

- - Specifies the timeout value for write transactions. - PSU_DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT 0x4f - - Port n Write QoS Configuration Register 1 - (OFFSET, MASK, VALUE) (0XFD070760, 0x000007FFU ,0x0000004FU) - RegMask = (DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_MASK | 0 ); - - RegVal = ((0x0000004FU << DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGWQOS1_4_OFFSET ,0x000007FFU ,0x0000004FU); - /*############################################################################################################################ */ - - /*Register : PCFGR_5 @ 0XFD070774

- - If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register. - PSU_DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN 0x0 - - If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG. - o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add - ess handshaking (it is not associated with any particular command). - PSU_DDRC_PCFGR_5_RD_PORT_URGENT_EN 0x1 - - If set to 1, enables aging function for the read channel of the port. - PSU_DDRC_PCFGR_5_RD_PORT_AGING_EN 0x0 - - Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g - ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority - will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre - ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the - aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st - ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w - ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D - RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: - he two LSBs of this register field are tied internally to 2'b00. - PSU_DDRC_PCFGR_5_RD_PORT_PRIORITY 0xf - - Port n Configuration Read Register - (OFFSET, MASK, VALUE) (0XFD070774, 0x000073FFU ,0x0000200FU) - RegMask = (DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGR_5_RD_PORT_URGENT_EN_MASK | DDRC_PCFGR_5_RD_PORT_AGING_EN_MASK | DDRC_PCFGR_5_RD_PORT_PRIORITY_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_SHIFT - | 0x00000001U << DDRC_PCFGR_5_RD_PORT_URGENT_EN_SHIFT - | 0x00000000U << DDRC_PCFGR_5_RD_PORT_AGING_EN_SHIFT - | 0x0000000FU << DDRC_PCFGR_5_RD_PORT_PRIORITY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGR_5_OFFSET ,0x000073FFU ,0x0000200FU); - /*############################################################################################################################ */ - - /*Register : PCFGW_5 @ 0XFD070778

- - If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register. - PSU_DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN 0x1 - - If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register - Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is - not associated with any particular command). - PSU_DDRC_PCFGW_5_WR_PORT_URGENT_EN 0x1 - - If set to 1, enables aging function for the write channel of the port. - PSU_DDRC_PCFGW_5_WR_PORT_AGING_EN 0x0 - - Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each - rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port - s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0 - the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno - be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For - ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch - ng. Note: The two LSBs of this register field are tied internally to 2'b00. - PSU_DDRC_PCFGW_5_WR_PORT_PRIORITY 0xf - - Port n Configuration Write Register - (OFFSET, MASK, VALUE) (0XFD070778, 0x000073FFU ,0x0000600FU) - RegMask = (DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGW_5_WR_PORT_URGENT_EN_MASK | DDRC_PCFGW_5_WR_PORT_AGING_EN_MASK | DDRC_PCFGW_5_WR_PORT_PRIORITY_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_SHIFT - | 0x00000001U << DDRC_PCFGW_5_WR_PORT_URGENT_EN_SHIFT - | 0x00000000U << DDRC_PCFGW_5_WR_PORT_AGING_EN_SHIFT - | 0x0000000FU << DDRC_PCFGW_5_WR_PORT_PRIORITY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGW_5_OFFSET ,0x000073FFU ,0x0000600FU); - /*############################################################################################################################ */ - - /*Register : PCTRL_5 @ 0XFD070800

- - Enables port n. - PSU_DDRC_PCTRL_5_PORT_EN 0x1 - - Port n Control Register - (OFFSET, MASK, VALUE) (0XFD070800, 0x00000001U ,0x00000001U) - RegMask = (DDRC_PCTRL_5_PORT_EN_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_PCTRL_5_PORT_EN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCTRL_5_OFFSET ,0x00000001U ,0x00000001U); - /*############################################################################################################################ */ - - /*Register : PCFGQOS0_5 @ 0XFD070804

- - This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf - gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is - disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. - PSU_DDRC_PCFGQOS0_5_RQOS_MAP_REGION1 0x1 - - This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi - urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i - disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. - PSU_DDRC_PCFGQOS0_5_RQOS_MAP_REGION0 0x0 - - Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d - al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio - ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc - values. - PSU_DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1 0x3 - - Port n Read QoS Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD070804, 0x0033000FU ,0x00100003U) - RegMask = (DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_MASK | DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_MASK | DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_SHIFT - | 0x00000000U << DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_SHIFT - | 0x00000003U << DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGQOS0_5_OFFSET ,0x0033000FU ,0x00100003U); - /*############################################################################################################################ */ - - /*Register : PCFGQOS1_5 @ 0XFD070808

- - Specifies the timeout value for transactions mapped to the red address queue. - PSU_DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR 0x0 - - Specifies the timeout value for transactions mapped to the blue address queue. - PSU_DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB 0x4f - - Port n Read QoS Configuration Register 1 - (OFFSET, MASK, VALUE) (0XFD070808, 0x07FF07FFU ,0x0000004FU) - RegMask = (DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_MASK | DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_SHIFT - | 0x0000004FU << DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGQOS1_5_OFFSET ,0x07FF07FFU ,0x0000004FU); - /*############################################################################################################################ */ - - /*Register : PCFGWQOS0_5 @ 0XFD07080C

- - This bitfield indicates the traffic class of region 1. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2 - VPW_EN = 0) and traffic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW traffic. - PSU_DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1 0x1 - - This bitfield indicates the traffic class of region 0. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2 - VPW_EN = 0) and traffic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW traffic. - PSU_DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0 0x0 - - Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 14 which c - rresponds to awqos. Note that for PA, awqos values are used directly as port priorities, where the higher the value correspon - s to higher port priority. - PSU_DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL 0x3 - - Port n Write QoS Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD07080C, 0x0033000FU ,0x00100003U) - RegMask = (DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_MASK | DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_MASK | DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_SHIFT - | 0x00000000U << DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_SHIFT - | 0x00000003U << DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGWQOS0_5_OFFSET ,0x0033000FU ,0x00100003U); - /*############################################################################################################################ */ - - /*Register : PCFGWQOS1_5 @ 0XFD070810

- - Specifies the timeout value for write transactions. - PSU_DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT 0x4f - - Port n Write QoS Configuration Register 1 - (OFFSET, MASK, VALUE) (0XFD070810, 0x000007FFU ,0x0000004FU) - RegMask = (DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_MASK | 0 ); - - RegVal = ((0x0000004FU << DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGWQOS1_5_OFFSET ,0x000007FFU ,0x0000004FU); - /*############################################################################################################################ */ - - /*Register : SARBASE0 @ 0XFD070F04

- - Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x] and araddr[UMCTL2_A_ADDRW-1:x] where x is determine - by the minimum block size parameter UMCTL2_SARMINSIZE: (x=log2(block size)). - PSU_DDRC_SARBASE0_BASE_ADDR 0x0 - - SAR Base Address Register n - (OFFSET, MASK, VALUE) (0XFD070F04, 0x000001FFU ,0x00000000U) - RegMask = (DDRC_SARBASE0_BASE_ADDR_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_SARBASE0_BASE_ADDR_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_SARBASE0_OFFSET ,0x000001FFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : SARSIZE0 @ 0XFD070F08

- - Number of blocks for address region n. This register determines the total size of the region in multiples of minimum block si - e as specified by the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded as number of blocks = nblocks + 1. - or example, if register is programmed to 0, region will have 1 block. - PSU_DDRC_SARSIZE0_NBLOCKS 0x0 - - SAR Size Register n - (OFFSET, MASK, VALUE) (0XFD070F08, 0x000000FFU ,0x00000000U) - RegMask = (DDRC_SARSIZE0_NBLOCKS_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_SARSIZE0_NBLOCKS_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_SARSIZE0_OFFSET ,0x000000FFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : SARBASE1 @ 0XFD070F0C

- - Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x] and araddr[UMCTL2_A_ADDRW-1:x] where x is determine - by the minimum block size parameter UMCTL2_SARMINSIZE: (x=log2(block size)). - PSU_DDRC_SARBASE1_BASE_ADDR 0x10 - - SAR Base Address Register n - (OFFSET, MASK, VALUE) (0XFD070F0C, 0x000001FFU ,0x00000010U) - RegMask = (DDRC_SARBASE1_BASE_ADDR_MASK | 0 ); - - RegVal = ((0x00000010U << DDRC_SARBASE1_BASE_ADDR_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_SARBASE1_OFFSET ,0x000001FFU ,0x00000010U); - /*############################################################################################################################ */ - - /*Register : SARSIZE1 @ 0XFD070F10

- - Number of blocks for address region n. This register determines the total size of the region in multiples of minimum block si - e as specified by the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded as number of blocks = nblocks + 1. - or example, if register is programmed to 0, region will have 1 block. - PSU_DDRC_SARSIZE1_NBLOCKS 0xf - - SAR Size Register n - (OFFSET, MASK, VALUE) (0XFD070F10, 0x000000FFU ,0x0000000FU) - RegMask = (DDRC_SARSIZE1_NBLOCKS_MASK | 0 ); +unsigned long psu_ddr_init_data(void) +{ + /* + * DDR INITIALIZATION + */ + /* + * DDR CONTROLLER RESET + */ + /* + * Register : RST_DDR_SS @ 0XFD1A0108 + + * DDR block level reset inside of the DDR Sub System + * PSU_CRF_APB_RST_DDR_SS_DDR_RESET 0X1 + + * DDR sub system block level reset + * (OFFSET, MASK, VALUE) (0XFD1A0108, 0x00000008U ,0x00000008U) + */ + PSU_Mask_Write(CRF_APB_RST_DDR_SS_OFFSET, 0x00000008U, 0x00000008U); +/*##################################################################### */ + + /* + * Register : MSTR @ 0XFD070000 + + * Indicates the configuration of the device used in the system. - 00 - x4 + * device - 01 - x8 device - 10 - x16 device - 11 - x32 device + * PSU_DDRC_MSTR_DEVICE_CONFIG 0x1 + + * Choose which registers are used. - 0 - Original registers - 1 - Shadow r + * egisters + * PSU_DDRC_MSTR_FREQUENCY_MODE 0x0 + + * Only present for multi-rank configurations. Each bit represents one rank + * . For two-rank configurations, only bits[25:24] are present. - 1 - popul + * ated - 0 - unpopulated LSB is the lowest rank number. For 2 ranks follow + * ing combinations are legal: - 01 - One rank - 11 - Two ranks - Others - + * Reserved. For 4 ranks following combinations are legal: - 0001 - One ran + * k - 0011 - Two ranks - 1111 - Four ranks + * PSU_DDRC_MSTR_ACTIVE_RANKS 0x1 + + * SDRAM burst length used: - 0001 - Burst length of 2 (only supported for + * mDDR) - 0010 - Burst length of 4 - 0100 - Burst length of 8 - 1000 - Bur + * st length of 16 (only supported for mDDR, LPDDR2, and LPDDR4) All other + * values are reserved. This controls the burst size used to access the SDR + * AM. This must match the burst length mode register setting in the SDRAM. + * (For BC4/8 on-the-fly mode of DDR3 and DDR4, set this field to 0x0100) + * Burst length of 2 is not supported with AXI ports when MEMC_BURST_LENGTH + * is 8. Burst length of 2 is only supported with MEMC_FREQ_RATIO = 1 + * PSU_DDRC_MSTR_BURST_RDWR 0x4 + + * Set to 1 when the uMCTL2 and DRAM has to be put in DLL-off mode for low + * frequency operation. Set to 0 to put uMCTL2 and DRAM in DLL-on mode for + * normal frequency operation. If DDR4 CRC/parity retry is enabled (CRCPARC + * TL1.crc_parity_retry_enable = 1), dll_off_mode is not supported, and thi + * s bit must be set to '0'. + * PSU_DDRC_MSTR_DLL_OFF_MODE 0x0 + + * Selects proportion of DQ bus width that is used by the SDRAM - 00 - Full + * DQ bus width to SDRAM - 01 - Half DQ bus width to SDRAM - 10 - Quarter + * DQ bus width to SDRAM - 11 - Reserved. Note that half bus width mode is + * only supported when the SDRAM bus width is a multiple of 16, and quarter + * bus width mode is only supported when the SDRAM bus width is a multiple + * of 32 and the configuration parameter MEMC_QBUS_SUPPORT is set. Bus wid + * th refers to DQ bus width (excluding any ECC width). + * PSU_DDRC_MSTR_DATA_BUS_WIDTH 0x0 + + * 1 indicates put the DRAM in geardown mode (2N) and 0 indicates put the D + * RAM in normal mode (1N). This register can be changed, only when the Con + * troller is in self-refresh mode. This signal must be set the same value + * as MR3 bit A3. Note: Geardown mode is not supported if the configuration + * parameter MEMC_CMD_RTN2IDLE is set + * PSU_DDRC_MSTR_GEARDOWN_MODE 0x0 + + * If 1, then uMCTL2 uses 2T timing. Otherwise, uses 1T timing. In 2T timin + * g, all command signals (except chip select) are held for 2 clocks on the + * SDRAM bus. Chip select is asserted on the second cycle of the command N + * ote: 2T timing is not supported in LPDDR2/LPDDR3/LPDDR4 mode Note: 2T ti + * ming is not supported if the configuration parameter MEMC_CMD_RTN2IDLE i + * s set Note: 2T timing is not supported in DDR4 geardown mode. + * PSU_DDRC_MSTR_EN_2T_TIMING_MODE 0x0 + + * When set, enable burst-chop in DDR3/DDR4. Burst Chop for Reads is exerci + * sed only in HIF configurations (UMCTL2_INCL_ARB not set) and if in full + * bus width mode (MSTR.data_bus_width = 00). Burst Chop for Writes is exer + * cised only if Partial Writes enabled (UMCTL2_PARTIAL_WR=1) and if CRC is + * disabled (CRCPARCTL1.crc_enable = 0). If DDR4 CRC/parity retry is enabl + * ed (CRCPARCTL1.crc_parity_retry_enable = 1), burst chop is not supported + * , and this bit must be set to '0' + * PSU_DDRC_MSTR_BURSTCHOP 0x0 + + * Select LPDDR4 SDRAM - 1 - LPDDR4 SDRAM device in use. - 0 - non-LPDDR4 d + * evice in use Present only in designs configured to support LPDDR4. + * PSU_DDRC_MSTR_LPDDR4 0x0 + + * Select DDR4 SDRAM - 1 - DDR4 SDRAM device in use. - 0 - non-DDR4 device + * in use Present only in designs configured to support DDR4. + * PSU_DDRC_MSTR_DDR4 0x1 + + * Select LPDDR3 SDRAM - 1 - LPDDR3 SDRAM device in use. - 0 - non-LPDDR3 d + * evice in use Present only in designs configured to support LPDDR3. + * PSU_DDRC_MSTR_LPDDR3 0x0 + + * Select LPDDR2 SDRAM - 1 - LPDDR2 SDRAM device in use. - 0 - non-LPDDR2 d + * evice in use Present only in designs configured to support LPDDR2. + * PSU_DDRC_MSTR_LPDDR2 0x0 + + * Select DDR3 SDRAM - 1 - DDR3 SDRAM device in use - 0 - non-DDR3 SDRAM de + * vice in use Only present in designs that support DDR3. + * PSU_DDRC_MSTR_DDR3 0x0 + + * Master Register + * (OFFSET, MASK, VALUE) (0XFD070000, 0xE30FBE3DU ,0x41040010U) + */ + PSU_Mask_Write(DDRC_MSTR_OFFSET, 0xE30FBE3DU, 0x41040010U); +/*##################################################################### */ + + /* + * Register : MRCTRL0 @ 0XFD070010 + + * Setting this register bit to 1 triggers a mode register read or write op + * eration. When the MR operation is complete, the uMCTL2 automatically cle + * ars this bit. The other register fields of this register must be written + * in a separate APB transaction, before setting this mr_wr bit. It is rec + * ommended NOT to set this signal if in Init, Deep power-down or MPSM oper + * ating modes. + * PSU_DDRC_MRCTRL0_MR_WR 0x0 + + * Address of the mode register that is to be written to. - 0000 - MR0 - 00 + * 01 - MR1 - 0010 - MR2 - 0011 - MR3 - 0100 - MR4 - 0101 - MR5 - 0110 - MR + * 6 - 0111 - MR7 Don't Care for LPDDR2/LPDDR3/LPDDR4 (see MRCTRL1.mr_data + * for mode register addressing in LPDDR2/LPDDR3/LPDDR4) This signal is als + * o used for writing to control words of RDIMMs. In that case, it correspo + * nds to the bank address bits sent to the RDIMM In case of DDR4, the bit[ + * 3:2] corresponds to the bank group bits. Therefore, the bit[3] as well a + * s the bit[2:0] must be set to an appropriate value which is considered b + * oth the Address Mirroring of UDIMMs/RDIMMs and the Output Inversion of R + * DIMMs. + * PSU_DDRC_MRCTRL0_MR_ADDR 0x0 + + * Controls which rank is accessed by MRCTRL0.mr_wr. Normally, it is desire + * d to access all ranks, so all bits should be set to 1. However, for mult + * i-rank UDIMMs/RDIMMs which implement address mirroring, it may be necess + * ary to access ranks individually. Examples (assume uMCTL2 is configured + * for 4 ranks): - 0x1 - select rank 0 only - 0x2 - select rank 1 only - 0x + * 5 - select ranks 0 and 2 - 0xA - select ranks 1 and 3 - 0xF - select ran + * ks 0, 1, 2 and 3 + * PSU_DDRC_MRCTRL0_MR_RANK 0x3 + + * Indicates whether Software intervention is allowed via MRCTRL0/MRCTRL1 b + * efore automatic SDRAM initialization routine or not. For DDR4, this bit + * can be used to initialize the DDR4 RCD (MR7) before automatic SDRAM init + * ialization. For LPDDR4, this bit can be used to program additional mode + * registers before automatic SDRAM initialization if necessary. Note: This + * must be cleared to 0 after completing Software operation. Otherwise, SD + * RAM initialization routine will not re-start. - 0 - Software interventio + * n is not allowed - 1 - Software intervention is allowed + * PSU_DDRC_MRCTRL0_SW_INIT_INT 0x0 + + * Indicates whether the mode register operation is MRS in PDA mode or not + * - 0 - MRS - 1 - MRS in Per DRAM Addressability mode + * PSU_DDRC_MRCTRL0_PDA_EN 0x0 + + * Indicates whether the mode register operation is MRS or WR/RD for MPR (o + * nly supported for DDR4) - 0 - MRS - 1 - WR/RD for MPR + * PSU_DDRC_MRCTRL0_MPR_EN 0x0 + + * Indicates whether the mode register operation is read or write. Only use + * d for LPDDR2/LPDDR3/LPDDR4/DDR4. - 0 - Write - 1 - Read + * PSU_DDRC_MRCTRL0_MR_TYPE 0x0 + + * Mode Register Read/Write Control Register 0. Note: Do not enable more th + * an one of the following fields simultaneously: - sw_init_int - pda_en - + * mpr_en + * (OFFSET, MASK, VALUE) (0XFD070010, 0x8000F03FU ,0x00000030U) + */ + PSU_Mask_Write(DDRC_MRCTRL0_OFFSET, 0x8000F03FU, 0x00000030U); +/*##################################################################### */ + + /* + * Register : DERATEEN @ 0XFD070020 + + * Derate value of tRC for LPDDR4 - 0 - Derating uses +1. - 1 - Derating us + * es +2. - 2 - Derating uses +3. - 3 - Derating uses +4. Present only in d + * esigns configured to support LPDDR4. The required number of cycles for d + * erating can be determined by dividing 3.75ns by the core_ddrc_core_clk p + * eriod, and rounding up the next integer. + * PSU_DDRC_DERATEEN_RC_DERATE_VALUE 0x2 + + * Derate byte Present only in designs configured to support LPDDR2/LPDDR3/ + * LPDDR4 Indicates which byte of the MRR data is used for derating. The ma + * ximum valid value depends on MEMC_DRAM_TOTAL_DATA_WIDTH. + * PSU_DDRC_DERATEEN_DERATE_BYTE 0x0 + + * Derate value - 0 - Derating uses +1. - 1 - Derating uses +2. Present onl + * y in designs configured to support LPDDR2/LPDDR3/LPDDR4 Set to 0 for all + * LPDDR2 speed grades as derating value of +1.875 ns is less than a core_ + * ddrc_core_clk period. Can be 0 or 1 for LPDDR3/LPDDR4, depending if +1.8 + * 75 ns is less than a core_ddrc_core_clk period or not. + * PSU_DDRC_DERATEEN_DERATE_VALUE 0x0 + + * Enables derating - 0 - Timing parameter derating is disabled - 1 - Timin + * g parameter derating is enabled using MR4 read value. Present only in de + * signs configured to support LPDDR2/LPDDR3/LPDDR4 This field must be set + * to '0' for non-LPDDR2/LPDDR3/LPDDR4 mode. + * PSU_DDRC_DERATEEN_DERATE_ENABLE 0x0 + + * Temperature Derate Enable Register + * (OFFSET, MASK, VALUE) (0XFD070020, 0x000003F3U ,0x00000200U) + */ + PSU_Mask_Write(DDRC_DERATEEN_OFFSET, 0x000003F3U, 0x00000200U); +/*##################################################################### */ + + /* + * Register : DERATEINT @ 0XFD070024 + + * Interval between two MR4 reads, used to derate the timing parameters. Pr + * esent only in designs configured to support LPDDR2/LPDDR3/LPDDR4. This r + * egister must not be set to zero + * PSU_DDRC_DERATEINT_MR4_READ_INTERVAL 0x800000 + + * Temperature Derate Interval Register + * (OFFSET, MASK, VALUE) (0XFD070024, 0xFFFFFFFFU ,0x00800000U) + */ + PSU_Mask_Write(DDRC_DERATEINT_OFFSET, 0xFFFFFFFFU, 0x00800000U); +/*##################################################################### */ + + /* + * Register : PWRCTL @ 0XFD070030 + + * Self refresh state is an intermediate state to enter to Self refresh pow + * er down state or exit Self refresh power down state for LPDDR4. This reg + * ister controls transition from the Self refresh state. - 1 - Prohibit tr + * ansition from Self refresh state - 0 - Allow transition from Self refres + * h state + * PSU_DDRC_PWRCTL_STAY_IN_SELFREF 0x0 + + * A value of 1 to this register causes system to move to Self Refresh stat + * e immediately, as long as it is not in INIT or DPD/MPSM operating_mode. + * This is referred to as Software Entry/Exit to Self Refresh. - 1 - Softwa + * re Entry to Self Refresh - 0 - Software Exit from Self Refresh + * PSU_DDRC_PWRCTL_SELFREF_SW 0x0 + + * When this is 1, the uMCTL2 puts the SDRAM into maximum power saving mode + * when the transaction store is empty. This register must be reset to '0' + * to bring uMCTL2 out of maximum power saving mode. Present only in desig + * ns configured to support DDR4. For non-DDR4, this register should not be + * set to 1. Note that MPSM is not supported when using a DWC DDR PHY, if + * the PHY parameter DWC_AC_CS_USE is disabled, as the MPSM exit sequence r + * equires the chip-select signal to toggle. FOR PERFORMANCE ONLY. + * PSU_DDRC_PWRCTL_MPSM_EN 0x0 + + * Enable the assertion of dfi_dram_clk_disable whenever a clock is not req + * uired by the SDRAM. If set to 0, dfi_dram_clk_disable is never asserted. + * Assertion of dfi_dram_clk_disable is as follows: In DDR2/DDR3, can only + * be asserted in Self Refresh. In DDR4, can be asserted in following: - i + * n Self Refresh. - in Maximum Power Saving Mode In mDDR/LPDDR2/LPDDR3, ca + * n be asserted in following: - in Self Refresh - in Power Down - in Deep + * Power Down - during Normal operation (Clock Stop) In LPDDR4, can be asse + * rted in following: - in Self Refresh Power Down - in Power Down - during + * Normal operation (Clock Stop) + * PSU_DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE 0x0 + + * When this is 1, uMCTL2 puts the SDRAM into deep power-down mode when the + * transaction store is empty. This register must be reset to '0' to bring + * uMCTL2 out of deep power-down mode. Controller performs automatic SDRAM + * initialization on deep power-down exit. Present only in designs configu + * red to support mDDR or LPDDR2 or LPDDR3. For non-mDDR/non-LPDDR2/non-LPD + * DR3, this register should not be set to 1. FOR PERFORMANCE ONLY. + * PSU_DDRC_PWRCTL_DEEPPOWERDOWN_EN 0x0 + + * If true then the uMCTL2 goes into power-down after a programmable number + * of cycles 'maximum idle clocks before power down' (PWRTMG.powerdown_to_ + * x32). This register bit may be re-programmed during the course of normal + * operation. + * PSU_DDRC_PWRCTL_POWERDOWN_EN 0x0 + + * If true then the uMCTL2 puts the SDRAM into Self Refresh after a program + * mable number of cycles 'maximum idle clocks before Self Refresh (PWRTMG. + * selfref_to_x32)'. This register bit may be re-programmed during the cour + * se of normal operation. + * PSU_DDRC_PWRCTL_SELFREF_EN 0x0 + + * Low Power Control Register + * (OFFSET, MASK, VALUE) (0XFD070030, 0x0000007FU ,0x00000000U) + */ + PSU_Mask_Write(DDRC_PWRCTL_OFFSET, 0x0000007FU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : PWRTMG @ 0XFD070034 + + * After this many clocks of NOP or deselect the uMCTL2 automatically puts + * the SDRAM into Self Refresh. This must be enabled in the PWRCTL.selfref_ + * en. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY. + * PSU_DDRC_PWRTMG_SELFREF_TO_X32 0x40 + + * Minimum deep power-down time. For mDDR, value from the JEDEC specificati + * on is 0 as mDDR exits from deep power-down mode immediately after PWRCTL + * .deeppowerdown_en is de-asserted. For LPDDR2/LPDDR3, value from the JEDE + * C specification is 500us. Unit: Multiples of 4096 clocks. Present only i + * n designs configured to support mDDR, LPDDR2 or LPDDR3. FOR PERFORMANCE + * ONLY. + * PSU_DDRC_PWRTMG_T_DPD_X4096 0x84 + + * After this many clocks of NOP or deselect the uMCTL2 automatically puts + * the SDRAM into power-down. This must be enabled in the PWRCTL.powerdown_ + * en. Unit: Multiples of 32 clocks FOR PERFORMANCE ONLY. + * PSU_DDRC_PWRTMG_POWERDOWN_TO_X32 0x10 + + * Low Power Timing Register + * (OFFSET, MASK, VALUE) (0XFD070034, 0x00FFFF1FU ,0x00408410U) + */ + PSU_Mask_Write(DDRC_PWRTMG_OFFSET, 0x00FFFF1FU, 0x00408410U); +/*##################################################################### */ + + /* + * Register : RFSHCTL0 @ 0XFD070050 + + * Threshold value in number of clock cycles before the critical refresh or + * page timer expires. A critical refresh is to be issued before this thre + * shold is reached. It is recommended that this not be changed from the de + * fault value, currently shown as 0x2. It must always be less than interna + * lly used t_rfc_nom_x32. Note that, in LPDDR2/LPDDR3/LPDDR4, internally u + * sed t_rfc_nom_x32 may be equal to RFSHTMG.t_rfc_nom_x32>>2 if derating i + * s enabled (DERATEEN.derate_enable=1). Otherwise, internally used t_rfc_n + * om_x32 will be equal to RFSHTMG.t_rfc_nom_x32. Unit: Multiples of 32 clo + * cks. + * PSU_DDRC_RFSHCTL0_REFRESH_MARGIN 0x2 + + * If the refresh timer (tRFCnom, also known as tREFI) has expired at least + * once, but it has not expired (RFSHCTL0.refresh_burst+1) times yet, then + * a speculative refresh may be performed. A speculative refresh is a refr + * esh performed at a time when refresh would be useful, but before it is a + * bsolutely required. When the SDRAM bus is idle for a period of time dete + * rmined by this RFSHCTL0.refresh_to_x32 and the refresh timer has expired + * at least once since the last refresh, then a speculative refresh is per + * formed. Speculative refreshes continues successively until there are no + * refreshes pending or until new reads or writes are issued to the uMCTL2. + * FOR PERFORMANCE ONLY. + * PSU_DDRC_RFSHCTL0_REFRESH_TO_X32 0x10 + + * The programmed value + 1 is the number of refresh timeouts that is allow + * ed to accumulate before traffic is blocked and the refreshes are forced + * to execute. Closing pages to perform a refresh is a one-time penalty tha + * t must be paid for each group of refreshes. Therefore, performing refres + * hes in a burst reduces the per-refresh penalty of these page closings. H + * igher numbers for RFSHCTL.refresh_burst slightly increases utilization; + * lower numbers decreases the worst-case latency associated with refreshes + * . - 0 - single refresh - 1 - burst-of-2 refresh - 7 - burst-of-8 refresh + * For information on burst refresh feature refer to section 3.9 of DDR2 J + * EDEC specification - JESD79-2F.pdf. For DDR2/3, the refresh is always pe + * r-rank and not per-bank. The rank refresh can be accumulated over 8*tREF + * I cycles using the burst refresh feature. In DDR4 mode, according to Fin + * e Granularity feature, 8 refreshes can be postponed in 1X mode, 16 refre + * shes in 2X mode and 32 refreshes in 4X mode. If using PHY-initiated upda + * tes, care must be taken in the setting of RFSHCTL0.refresh_burst, to ens + * ure that tRFCmax is not violated due to a PHY-initiated update occurring + * shortly before a refresh burst was due. In this situation, the refresh + * burst will be delayed until the PHY-initiated update is complete. + * PSU_DDRC_RFSHCTL0_REFRESH_BURST 0x0 + + * - 1 - Per bank refresh; - 0 - All bank refresh. Per bank refresh allows + * traffic to flow to other banks. Per bank refresh is not supported by all + * LPDDR2 devices but should be supported by all LPDDR3/LPDDR4 devices. Pr + * esent only in designs configured to support LPDDR2/LPDDR3/LPDDR4 + * PSU_DDRC_RFSHCTL0_PER_BANK_REFRESH 0x0 + + * Refresh Control Register 0 + * (OFFSET, MASK, VALUE) (0XFD070050, 0x00F1F1F4U ,0x00210000U) + */ + PSU_Mask_Write(DDRC_RFSHCTL0_OFFSET, 0x00F1F1F4U, 0x00210000U); +/*##################################################################### */ + + /* + * Register : RFSHCTL1 @ 0XFD070054 + + * Refresh timer start for rank 1 (only present in multi-rank configuration + * s). This is useful in staggering the refreshes to multiple ranks to help + * traffic to proceed. This is explained in Refresh Controls section of ar + * chitecture chapter. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY. + * PSU_DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32 0x0 + + * Refresh timer start for rank 0 (only present in multi-rank configuration + * s). This is useful in staggering the refreshes to multiple ranks to help + * traffic to proceed. This is explained in Refresh Controls section of ar + * chitecture chapter. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY. + * PSU_DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32 0x0 + + * Refresh Control Register 1 + * (OFFSET, MASK, VALUE) (0XFD070054, 0x0FFF0FFFU ,0x00000000U) + */ + PSU_Mask_Write(DDRC_RFSHCTL1_OFFSET, 0x0FFF0FFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : RFSHCTL3 @ 0XFD070060 + + * Fine Granularity Refresh Mode - 000 - Fixed 1x (Normal mode) - 001 - Fix + * ed 2x - 010 - Fixed 4x - 101 - Enable on the fly 2x (not supported) - 11 + * 0 - Enable on the fly 4x (not supported) - Everything else - reserved No + * te: The on-the-fly modes is not supported in this version of the uMCTL2. + * Note: This must be set up while the Controller is in reset or while the + * Controller is in self-refresh mode. Changing this during normal operati + * on is not allowed. Making this a dynamic register will be supported in f + * uture version of the uMCTL2. + * PSU_DDRC_RFSHCTL3_REFRESH_MODE 0x0 + + * Toggle this signal (either from 0 to 1 or from 1 to 0) to indicate that + * the refresh register(s) have been updated. The value is automatically up + * dated when exiting reset, so it does not need to be toggled initially. + * PSU_DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL 0x0 + + * When '1', disable auto-refresh generated by the uMCTL2. When auto-refres + * h is disabled, the SoC core must generate refreshes using the registers + * reg_ddrc_rank0_refresh, reg_ddrc_rank1_refresh, reg_ddrc_rank2_refresh a + * nd reg_ddrc_rank3_refresh. When dis_auto_refresh transitions from 0 to 1 + * , any pending refreshes are immediately scheduled by the uMCTL2. If DDR4 + * CRC/parity retry is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), d + * isable auto-refresh is not supported, and this bit must be set to '0'. T + * his register field is changeable on the fly. + * PSU_DDRC_RFSHCTL3_DIS_AUTO_REFRESH 0x1 + + * Refresh Control Register 3 + * (OFFSET, MASK, VALUE) (0XFD070060, 0x00000073U ,0x00000001U) + */ + PSU_Mask_Write(DDRC_RFSHCTL3_OFFSET, 0x00000073U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : RFSHTMG @ 0XFD070064 + + * tREFI: Average time interval between refreshes per rank (Specification: + * 7.8us for DDR2, DDR3 and DDR4. See JEDEC specification for mDDR, LPDDR2, + * LPDDR3 and LPDDR4). For LPDDR2/LPDDR3/LPDDR4: - if using all-bank refre + * shes (RFSHCTL0.per_bank_refresh = 0), this register should be set to tRE + * FIab - if using per-bank refreshes (RFSHCTL0.per_bank_refresh = 1), this + * register should be set to tREFIpb For configurations with MEMC_FREQ_RAT + * IO=2, program this to (tREFI/2), no rounding up. In DDR4 mode, tREFI val + * ue is different depending on the refresh mode. The user should program t + * he appropriate value from the spec based on the value programmed in the + * refresh mode register. Note that RFSHTMG.t_rfc_nom_x32 * 32 must be grea + * ter than RFSHTMG.t_rfc_min, and RFSHTMG.t_rfc_nom_x32 must be greater th + * an 0x1. Unit: Multiples of 32 clocks. + * PSU_DDRC_RFSHTMG_T_RFC_NOM_X32 0x81 + + * Used only when LPDDR3 memory type is connected. Should only be changed w + * hen uMCTL2 is in reset. Specifies whether to use the tREFBW parameter (r + * equired by some LPDDR3 devices which comply with earlier versions of the + * LPDDR3 JEDEC specification) or not: - 0 - tREFBW parameter not used - 1 + * - tREFBW parameter used + * PSU_DDRC_RFSHTMG_LPDDR3_TREFBW_EN 0x1 + + * tRFC (min): Minimum time from refresh to refresh or activate. For MEMC_F + * REQ_RATIO=1 configurations, t_rfc_min should be set to RoundUp(tRFCmin/t + * CK). For MEMC_FREQ_RATIO=2 configurations, t_rfc_min should be set to Ro + * undUp(RoundUp(tRFCmin/tCK)/2). In LPDDR2/LPDDR3/LPDDR4 mode: - if using + * all-bank refreshes, the tRFCmin value in the above equations is equal to + * tRFCab - if using per-bank refreshes, the tRFCmin value in the above eq + * uations is equal to tRFCpb In DDR4 mode, the tRFCmin value in the above + * equations is different depending on the refresh mode (fixed 1X,2X,4X) an + * d the device density. The user should program the appropriate value from + * the spec based on the 'refresh_mode' and the device density that is use + * d. Unit: Clocks. + * PSU_DDRC_RFSHTMG_T_RFC_MIN 0x8b + + * Refresh Timing Register + * (OFFSET, MASK, VALUE) (0XFD070064, 0x0FFF83FFU ,0x0081808BU) + */ + PSU_Mask_Write(DDRC_RFSHTMG_OFFSET, 0x0FFF83FFU, 0x0081808BU); +/*##################################################################### */ + + /* + * Register : ECCCFG0 @ 0XFD070070 + + * Disable ECC scrubs. Valid only when ECCCFG0.ecc_mode = 3'b100 and MEMC_U + * SE_RMW is defined + * PSU_DDRC_ECCCFG0_DIS_SCRUB 0x1 + + * ECC mode indicator - 000 - ECC disabled - 100 - ECC enabled - SEC/DED ov + * er 1 beat - all other settings are reserved for future use + * PSU_DDRC_ECCCFG0_ECC_MODE 0x0 + + * ECC Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD070070, 0x00000017U ,0x00000010U) + */ + PSU_Mask_Write(DDRC_ECCCFG0_OFFSET, 0x00000017U, 0x00000010U); +/*##################################################################### */ + + /* + * Register : ECCCFG1 @ 0XFD070074 + + * Selects whether to poison 1 or 2 bits - if 0 -> 2-bit (uncorrectable) da + * ta poisoning, if 1 -> 1-bit (correctable) data poisoning, if ECCCFG1.dat + * a_poison_en=1 + * PSU_DDRC_ECCCFG1_DATA_POISON_BIT 0x0 + + * Enable ECC data poisoning - introduces ECC errors on writes to address s + * pecified by the ECCPOISONADDR0/1 registers + * PSU_DDRC_ECCCFG1_DATA_POISON_EN 0x0 + + * ECC Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD070074, 0x00000003U ,0x00000000U) + */ + PSU_Mask_Write(DDRC_ECCCFG1_OFFSET, 0x00000003U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : CRCPARCTL1 @ 0XFD0700C4 + + * The maximum number of DFI PHY clock cycles allowed from the assertion of + * the dfi_rddata_en signal to the assertion of each of the corresponding + * bits of the dfi_rddata_valid signal. This corresponds to the DFI timing + * parameter tphy_rdlat. Refer to PHY specification for correct value. This + * value it only used for detecting read data timeout when DDR4 retry is e + * nabled by CRCPARCTL1.crc_parity_retry_enable=1. Maximum supported value: + * - 1:1 Frequency mode : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_r + * dlat < 'd114 - 1:2 Frequency mode ANDAND DFITMG0.dfi_rddata_use_sdr == 1 + * : CRCPARCTL1.dfi_t_phy_rdlat < 64 - 1:2 Frequency mode ANDAND DFITMG0.d + * fi_rddata_use_sdr == 0 : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_ + * rdlat < 'd114 Unit: DFI Clocks + * PSU_DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT 0x10 + + * After a Parity or CRC error is flagged on dfi_alert_n signal, the softwa + * re has an option to read the mode registers in the DRAM before the hardw + * are begins the retry process - 1: Wait for software to read/write the mo + * de registers before hardware begins the retry. After software is done wi + * th its operations, it will clear the alert interrupt register bit - 0: H + * ardware can begin the retry right away after the dfi_alert_n pulse goes + * away. The value on this register is valid only when retry is enabled (PA + * RCTRL.crc_parity_retry_enable = 1) If this register is set to 1 and if t + * he software doesn't clear the interrupt register after handling the pari + * ty/CRC error, then the hardware will not begin the retry process and the + * system will hang. In the case of Parity/CRC error, there are two possib + * ilities when the software doesn't reset MR5[4] to 0. - (i) If 'Persisten + * t parity' mode register bit is NOT set: the commands sent during retry a + * nd normal operation are executed without parity checking. The value in t + * he Parity error log register MPR Page 1 is valid. - (ii) If 'Persistent + * parity' mode register bit is SET: Parity checking is done for commands s + * ent during retry and normal operation. If multiple errors occur before M + * R5[4] is cleared, the error log in MPR Page 1 should be treated as 'Don' + * t care'. + * PSU_DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW 0x1 + + * - 1: Enable command retry mechanism in case of C/A Parity or CRC error - + * 0: Disable command retry mechanism when C/A Parity or CRC features are + * enabled. Note that retry functionality is not supported if burst chop is + * enabled (MSTR.burstchop = 1) and/or disable auto-refresh is enabled (RF + * SHCTL3.dis_auto_refresh = 1) + * PSU_DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE 0x0 + + * CRC Calculation setting register - 1: CRC includes DM signal - 0: CRC no + * t includes DM signal Present only in designs configured to support DDR4. + * PSU_DDRC_CRCPARCTL1_CRC_INC_DM 0x0 + + * CRC enable Register - 1: Enable generation of CRC - 0: Disable generatio + * n of CRC The setting of this register should match the CRC mode register + * setting in the DRAM. + * PSU_DDRC_CRCPARCTL1_CRC_ENABLE 0x0 + + * C/A Parity enable register - 1: Enable generation of C/A parity and dete + * ction of C/A parity error - 0: Disable generation of C/A parity and disa + * ble detection of C/A parity error If RCD's parity error detection or SDR + * AM's parity detection is enabled, this register should be 1. + * PSU_DDRC_CRCPARCTL1_PARITY_ENABLE 0x0 + + * CRC Parity Control Register1 + * (OFFSET, MASK, VALUE) (0XFD0700C4, 0x3F000391U ,0x10000200U) + */ + PSU_Mask_Write(DDRC_CRCPARCTL1_OFFSET, 0x3F000391U, 0x10000200U); +/*##################################################################### */ + + /* + * Register : CRCPARCTL2 @ 0XFD0700C8 + + * Value from the DRAM spec indicating the maximum width of the dfi_alert_n + * pulse when a parity error occurs. Recommended values: - tPAR_ALERT_PW.M + * AX For configurations with MEMC_FREQ_RATIO=2, program this to tPAR_ALERT + * _PW.MAX/2 and round up to next integer value. Values of 0, 1 and 2 are i + * llegal. This value must be greater than CRCPARCTL2.t_crc_alert_pw_max. + * PSU_DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX 0x40 + + * Value from the DRAM spec indicating the maximum width of the dfi_alert_n + * pulse when a CRC error occurs. Recommended values: - tCRC_ALERT_PW.MAX + * For configurations with MEMC_FREQ_RATIO=2, program this to tCRC_ALERT_PW + * .MAX/2 and round up to next integer value. Values of 0, 1 and 2 are ille + * gal. This value must be less than CRCPARCTL2.t_par_alert_pw_max. + * PSU_DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX 0x5 + + * Indicates the maximum duration in number of DRAM clock cycles for which + * a command should be held in the Command Retry FIFO before it is popped o + * ut. Every location in the Command Retry FIFO has an associated down coun + * ting timer that will use this register as the start value. The down coun + * ting starts when a command is loaded into the FIFO. The timer counts dow + * n every 4 DRAM cycles. When the counter reaches zero, the entry is poppe + * d from the FIFO. All the counters are frozen, if a C/A Parity or CRC err + * or occurs before the counter reaches zero. The counter is reset to 0, af + * ter all the commands in the FIFO are retried. Recommended(minimum) value + * s: - Only C/A Parity is enabled. RoundUp((PHY Command Latency(DRAM CLK) + * + CAL + RDIMM delay + tPAR_ALERT_ON.max + tPAR_UNKNOWN + PHY Alert Laten + * cy(DRAM CLK) + board delay) / 4) + 2 - Both C/A Parity and CRC is enable + * d/ Only CRC is enabled. RoundUp((PHY Command Latency(DRAM CLK) + CAL + R + * DIMM delay + WL + 5(BL10)+ tCRC_ALERT.max + PHY Alert Latency(DRAM CLK) + * + board delay) / 4) + 2 Note 1: All value (e.g. tPAR_ALERT_ON) should be + * in terms of DRAM Clock and round up Note 2: Board delay(Command/Alert_n + * ) should be considered. Note 3: Use the worst case(longer) value for PHY + * Latencies/Board delay Note 4: The Recommended values are minimum value + * to be set. For mode detail, See 'Calculation of FIFO Depth' section. Max + * value can be set to this register is defined below: - MEMC_BURST_LENGTH + * == 16 Full bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 + * Full bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Half b + * us Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-4 Half bus Mod + * e (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-6 Quarter bus Mode (C + * RC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-8 Quarter bus Mode (CRC= + * ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-12 - MEMC_BURST_LENGTH != 16 + * Full bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-1 Full + * bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mod + * e (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mode (CRC + * =ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Quarter bus Mode (CRC=OFF + * ) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-4 Quarter bus Mode (CRC=ON) Ma + * x value = UMCTL2_RETRY_CMD_FIFO_DEPTH-6 Values of 0, 1 and 2 are illegal + * . + * PSU_DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4 0x1f + + * CRC Parity Control Register2 + * (OFFSET, MASK, VALUE) (0XFD0700C8, 0x01FF1F3FU ,0x0040051FU) + */ + PSU_Mask_Write(DDRC_CRCPARCTL2_OFFSET, 0x01FF1F3FU, 0x0040051FU); +/*##################################################################### */ + + /* + * Register : INIT0 @ 0XFD0700D0 + + * If lower bit is enabled the SDRAM initialization routine is skipped. The + * upper bit decides what state the controller starts up in when reset is + * removed - 00 - SDRAM Intialization routine is run after power-up - 01 - + * SDRAM Intialization routine is skipped after power-up. Controller starts + * up in Normal Mode - 11 - SDRAM Intialization routine is skipped after p + * ower-up. Controller starts up in Self-refresh Mode - 10 - SDRAM Intializ + * ation routine is run after power-up. Note: The only 2'b00 is supported f + * or LPDDR4 in this version of the uMCTL2. + * PSU_DDRC_INIT0_SKIP_DRAM_INIT 0x0 + + * Cycles to wait after driving CKE high to start the SDRAM initialization + * sequence. Unit: 1024 clocks. DDR2 typically requires a 400 ns delay, req + * uiring this value to be programmed to 2 at all clock speeds. LPDDR2/LPDD + * R3 typically requires this to be programmed for a delay of 200 us. LPDDR + * 4 typically requires this to be programmed for a delay of 2 us. For conf + * igurations with MEMC_FREQ_RATIO=2, program this to JEDEC spec value divi + * ded by 2, and round it up to next integer value. + * PSU_DDRC_INIT0_POST_CKE_X1024 0x2 + + * Cycles to wait after reset before driving CKE high to start the SDRAM in + * itialization sequence. Unit: 1024 clock cycles. DDR2 specifications typi + * cally require this to be programmed for a delay of >= 200 us. LPDDR2/LPD + * DR3: tINIT1 of 100 ns (min) LPDDR4: tINIT3 of 2 ms (min) For configurati + * ons with MEMC_FREQ_RATIO=2, program this to JEDEC spec value divided by + * 2, and round it up to next integer value. + * PSU_DDRC_INIT0_PRE_CKE_X1024 0x106 + + * SDRAM Initialization Register 0 + * (OFFSET, MASK, VALUE) (0XFD0700D0, 0xC3FF0FFFU ,0x00020106U) + */ + PSU_Mask_Write(DDRC_INIT0_OFFSET, 0xC3FF0FFFU, 0x00020106U); +/*##################################################################### */ + + /* + * Register : INIT1 @ 0XFD0700D4 + + * Number of cycles to assert SDRAM reset signal during init sequence. This + * is only present for designs supporting DDR3, DDR4 or LPDDR4 devices. Fo + * r use with a DDR PHY, this should be set to a minimum of 1 + * PSU_DDRC_INIT1_DRAM_RSTN_X1024 0x2 + + * Cycles to wait after completing the SDRAM initialization sequence before + * starting the dynamic scheduler. Unit: Counts of a global timer that pul + * ses every 32 clock cycles. There is no known specific requirement for th + * is; it may be set to zero. + * PSU_DDRC_INIT1_FINAL_WAIT_X32 0x0 + + * Wait period before driving the OCD complete command to SDRAM. Unit: Coun + * ts of a global timer that pulses every 32 clock cycles. There is no know + * n specific requirement for this; it may be set to zero. + * PSU_DDRC_INIT1_PRE_OCD_X32 0x0 + + * SDRAM Initialization Register 1 + * (OFFSET, MASK, VALUE) (0XFD0700D4, 0x01FF7F0FU ,0x00020000U) + */ + PSU_Mask_Write(DDRC_INIT1_OFFSET, 0x01FF7F0FU, 0x00020000U); +/*##################################################################### */ + + /* + * Register : INIT2 @ 0XFD0700D8 + + * Idle time after the reset command, tINIT4. Present only in designs confi + * gured to support LPDDR2. Unit: 32 clock cycles. + * PSU_DDRC_INIT2_IDLE_AFTER_RESET_X32 0x23 + + * Time to wait after the first CKE high, tINIT2. Present only in designs c + * onfigured to support LPDDR2/LPDDR3. Unit: 1 clock cycle. LPDDR2/LPDDR3 t + * ypically requires 5 x tCK delay. + * PSU_DDRC_INIT2_MIN_STABLE_CLOCK_X1 0x5 + + * SDRAM Initialization Register 2 + * (OFFSET, MASK, VALUE) (0XFD0700D8, 0x0000FF0FU ,0x00002305U) + */ + PSU_Mask_Write(DDRC_INIT2_OFFSET, 0x0000FF0FU, 0x00002305U); +/*##################################################################### */ + + /* + * Register : INIT3 @ 0XFD0700DC + + * DDR2: Value to write to MR register. Bit 8 is for DLL and the setting he + * re is ignored. The uMCTL2 sets this bit appropriately. DDR3/DDR4: Value + * loaded into MR0 register. mDDR: Value to write to MR register. LPDDR2/LP + * DDR3/LPDDR4 - Value to write to MR1 register + * PSU_DDRC_INIT3_MR 0x730 + + * DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setti + * ng in this register is ignored. The uMCTL2 sets those bits appropriately + * . DDR3/DDR4: Value to write to MR1 register Set bit 7 to 0. If PHY-evalu + * ation mode training is enabled, this bit is set appropriately by the uMC + * TL2 during write leveling. mDDR: Value to write to EMR register. LPDDR2/ + * LPDDR3/LPDDR4 - Value to write to MR2 register + * PSU_DDRC_INIT3_EMR 0x301 + + * SDRAM Initialization Register 3 + * (OFFSET, MASK, VALUE) (0XFD0700DC, 0xFFFFFFFFU ,0x07300301U) + */ + PSU_Mask_Write(DDRC_INIT3_OFFSET, 0xFFFFFFFFU, 0x07300301U); +/*##################################################################### */ + + /* + * Register : INIT4 @ 0XFD0700E0 + + * DDR2: Value to write to EMR2 register. DDR3/DDR4: Value to write to MR2 + * register LPDDR2/LPDDR3/LPDDR4: Value to write to MR3 register mDDR: Unus + * ed + * PSU_DDRC_INIT4_EMR2 0x20 + + * DDR2: Value to write to EMR3 register. DDR3/DDR4: Value to write to MR3 + * register mDDR/LPDDR2/LPDDR3: Unused LPDDR4: Value to write to MR13 regis + * ter + * PSU_DDRC_INIT4_EMR3 0x200 + + * SDRAM Initialization Register 4 + * (OFFSET, MASK, VALUE) (0XFD0700E0, 0xFFFFFFFFU ,0x00200200U) + */ + PSU_Mask_Write(DDRC_INIT4_OFFSET, 0xFFFFFFFFU, 0x00200200U); +/*##################################################################### */ + + /* + * Register : INIT5 @ 0XFD0700E4 + + * ZQ initial calibration, tZQINIT. Present only in designs configured to s + * upport DDR3 or DDR4 or LPDDR2/LPDDR3. Unit: 32 clock cycles. DDR3 typica + * lly requires 512 clocks. DDR4 requires 1024 clocks. LPDDR2/LPDDR3 requir + * es 1 us. + * PSU_DDRC_INIT5_DEV_ZQINIT_X32 0x21 + + * Maximum duration of the auto initialization, tINIT5. Present only in des + * igns configured to support LPDDR2/LPDDR3. LPDDR2/LPDDR3 typically requir + * es 10 us. + * PSU_DDRC_INIT5_MAX_AUTO_INIT_X1024 0x4 + + * SDRAM Initialization Register 5 + * (OFFSET, MASK, VALUE) (0XFD0700E4, 0x00FF03FFU ,0x00210004U) + */ + PSU_Mask_Write(DDRC_INIT5_OFFSET, 0x00FF03FFU, 0x00210004U); +/*##################################################################### */ + + /* + * Register : INIT6 @ 0XFD0700E8 + + * DDR4- Value to be loaded into SDRAM MR4 registers. Used in DDR4 designs + * only. + * PSU_DDRC_INIT6_MR4 0x0 + + * DDR4- Value to be loaded into SDRAM MR5 registers. Used in DDR4 designs + * only. + * PSU_DDRC_INIT6_MR5 0x6c0 + + * SDRAM Initialization Register 6 + * (OFFSET, MASK, VALUE) (0XFD0700E8, 0xFFFFFFFFU ,0x000006C0U) + */ + PSU_Mask_Write(DDRC_INIT6_OFFSET, 0xFFFFFFFFU, 0x000006C0U); +/*##################################################################### */ + + /* + * Register : INIT7 @ 0XFD0700EC + + * DDR4- Value to be loaded into SDRAM MR6 registers. Used in DDR4 designs + * only. + * PSU_DDRC_INIT7_MR6 0x819 + + * SDRAM Initialization Register 7 + * (OFFSET, MASK, VALUE) (0XFD0700EC, 0xFFFF0000U ,0x08190000U) + */ + PSU_Mask_Write(DDRC_INIT7_OFFSET, 0xFFFF0000U, 0x08190000U); +/*##################################################################### */ + + /* + * Register : DIMMCTL @ 0XFD0700F0 + + * Disabling Address Mirroring for BG bits. When this is set to 1, BG0 and + * BG1 are NOT swapped even if Address Mirroring is enabled. This will be r + * equired for DDR4 DIMMs with x16 devices. - 1 - BG0 and BG1 are NOT swapp + * ed. - 0 - BG0 and BG1 are swapped if address mirroring is enabled. + * PSU_DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING 0x0 + + * Enable for BG1 bit of MRS command. BG1 bit of the mode register address + * is specified as RFU (Reserved for Future Use) and must be programmed to + * 0 during MRS. In case where DRAMs which do not have BG1 are attached and + * both the CA parity and the Output Inversion are enabled, this must be s + * et to 0, so that the calculation of CA parity will not include BG1 bit. + * Note: This has no effect on the address of any other memory accesses, or + * of software-driven mode register accesses. If address mirroring is enab + * led, this is applied to BG1 of even ranks and BG0 of odd ranks. - 1 - En + * abled - 0 - Disabled + * PSU_DDRC_DIMMCTL_MRS_BG1_EN 0x1 + + * Enable for A17 bit of MRS command. A17 bit of the mode register address + * is specified as RFU (Reserved for Future Use) and must be programmed to + * 0 during MRS. In case where DRAMs which do not have A17 are attached and + * the Output Inversion are enabled, this must be set to 0, so that the ca + * lculation of CA parity will not include A17 bit. Note: This has no effec + * t on the address of any other memory accesses, or of software-driven mod + * e register accesses. - 1 - Enabled - 0 - Disabled + * PSU_DDRC_DIMMCTL_MRS_A17_EN 0x0 + + * Output Inversion Enable (for DDR4 RDIMM implementations only). DDR4 RDIM + * M implements the Output Inversion feature by default, which means that t + * he following address, bank address and bank group bits of B-side DRAMs a + * re inverted: A3-A9, A11, A13, A17, BA0-BA1, BG0-BG1. Setting this bit en + * sures that, for mode register accesses generated by the uMCTL2 during th + * e automatic initialization routine and enabling of a particular DDR4 fea + * ture, separate A-side and B-side mode register accesses are generated. F + * or B-side mode register accesses, these bits are inverted within the uMC + * TL2 to compensate for this RDIMM inversion. Note: This has no effect on + * the address of any other memory accesses, or of software-driven mode reg + * ister accesses. - 1 - Implement output inversion for B-side DRAMs. - 0 - + * Do not implement output inversion for B-side DRAMs. + * PSU_DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN 0x0 + + * Address Mirroring Enable (for multi-rank UDIMM implementations and multi + * -rank DDR4 RDIMM implementations). Some UDIMMs and DDR4 RDIMMs implement + * address mirroring for odd ranks, which means that the following address + * , bank address and bank group bits are swapped: (A3, A4), (A5, A6), (A7, + * A8), (BA0, BA1) and also (A11, A13), (BG0, BG1) for the DDR4. Setting t + * his bit ensures that, for mode register accesses during the automatic in + * itialization routine, these bits are swapped within the uMCTL2 to compen + * sate for this UDIMM/RDIMM swapping. In addition to the automatic initial + * ization routine, in case of DDR4 UDIMM/RDIMM, they are swapped during th + * e automatic MRS access to enable/disable of a particular DDR4 feature. N + * ote: This has no effect on the address of any other memory accesses, or + * of software-driven mode register accesses. This is not supported for mDD + * R, LPDDR2, LPDDR3 or LPDDR4 SDRAMs. Note: In case of x16 DDR4 DIMMs, BG1 + * output of MRS for the odd ranks is same as BG0 because BG1 is invalid, + * hence dimm_dis_bg_mirroring register must be set to 1. - 1 - For odd ran + * ks, implement address mirroring for MRS commands to during initializatio + * n and for any automatic DDR4 MRS commands (to be used if UDIMM/RDIMM imp + * lements address mirroring) - 0 - Do not implement address mirroring + * PSU_DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN 0x0 + + * Staggering enable for multi-rank accesses (for multi-rank UDIMM and RDIM + * M implementations only). This is not supported for mDDR, LPDDR2, LPDDR3 + * or LPDDR4 SDRAMs. Note: Even if this bit is set it does not take care of + * software driven MR commands (via MRCTRL0/MRCTRL1), where software is re + * sponsible to send them to seperate ranks as appropriate. - 1 - (DDR4) Se + * nd MRS commands to each ranks seperately - 1 - (non-DDR4) Send all comma + * nds to even and odd ranks seperately - 0 - Do not stagger accesses + * PSU_DDRC_DIMMCTL_DIMM_STAGGER_CS_EN 0x0 + + * DIMM Control Register + * (OFFSET, MASK, VALUE) (0XFD0700F0, 0x0000003FU ,0x00000010U) + */ + PSU_Mask_Write(DDRC_DIMMCTL_OFFSET, 0x0000003FU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : RANKCTL @ 0XFD0700F4 + + * Only present for multi-rank configurations. Indicates the number of cloc + * ks of gap in data responses when performing consecutive writes to differ + * ent ranks. This is used to switch the delays in the PHY to match the ran + * k requirements. This value should consider both PHY requirement and ODT + * requirement. - PHY requirement: tphy_wrcsgap + 1 (see PHY databook for v + * alue of tphy_wrcsgap) If CRC feature is enabled, should be increased by + * 1. If write preamble is set to 2tCK(DDR4/LPDDR4 only), should be increas + * ed by 1. If write postamble is set to 1.5tCK(LPDDR4 only), should be inc + * reased by 1. - ODT requirement: The value programmed in this register ta + * kes care of the ODT switch off timing requirement when switching ranks d + * uring writes. For LPDDR4, the requirement is ODTLoff - ODTLon - BL/2 + 1 + * For configurations with MEMC_FREQ_RATIO=1, program this to the larger o + * f PHY requirement or ODT requirement. For configurations with MEMC_FREQ_ + * RATIO=2, program this to the larger value divided by two and round it up + * to the next integer. + * PSU_DDRC_RANKCTL_DIFF_RANK_WR_GAP 0x6 + + * Only present for multi-rank configurations. Indicates the number of cloc + * ks of gap in data responses when performing consecutive reads to differe + * nt ranks. This is used to switch the delays in the PHY to match the rank + * requirements. This value should consider both PHY requirement and ODT r + * equirement. - PHY requirement: tphy_rdcsgap + 1 (see PHY databook for va + * lue of tphy_rdcsgap) If read preamble is set to 2tCK(DDR4/LPDDR4 only), + * should be increased by 1. If read postamble is set to 1.5tCK(LPDDR4 only + * ), should be increased by 1. - ODT requirement: The value programmed in + * this register takes care of the ODT switch off timing requirement when s + * witching ranks during reads. For configurations with MEMC_FREQ_RATIO=1, + * program this to the larger of PHY requirement or ODT requirement. For co + * nfigurations with MEMC_FREQ_RATIO=2, program this to the larger value di + * vided by two and round it up to the next integer. + * PSU_DDRC_RANKCTL_DIFF_RANK_RD_GAP 0x6 + + * Only present for multi-rank configurations. Background: Reads to the sam + * e rank can be performed back-to-back. Reads to different ranks require a + * dditional gap dictated by the register RANKCTL.diff_rank_rd_gap. This is + * to avoid possible data bus contention as well as to give PHY enough tim + * e to switch the delay when changing ranks. The uMCTL2 arbitrates for bus + * access on a cycle-by-cycle basis; therefore after a read is scheduled, + * there are few clock cycles (determined by the value on RANKCTL.diff_rank + * _rd_gap register) in which only reads from the same rank are eligible to + * be scheduled. This prevents reads from other ranks from having fair acc + * ess to the data bus. This parameter represents the maximum number of rea + * ds that can be scheduled consecutively to the same rank. After this numb + * er is reached, a delay equal to RANKCTL.diff_rank_rd_gap is inserted by + * the scheduler to allow all ranks a fair opportunity to be scheduled. Hig + * her numbers increase bandwidth utilization, lower numbers increase fairn + * ess. This feature can be DISABLED by setting this register to 0. When se + * t to 0, the Controller will stay on the same rank as long as commands ar + * e available for it. Minimum programmable value is 0 (feature disabled) a + * nd maximum programmable value is 0xF. FOR PERFORMANCE ONLY. + * PSU_DDRC_RANKCTL_MAX_RANK_RD 0xf + + * Rank Control Register + * (OFFSET, MASK, VALUE) (0XFD0700F4, 0x00000FFFU ,0x0000066FU) + */ + PSU_Mask_Write(DDRC_RANKCTL_OFFSET, 0x00000FFFU, 0x0000066FU); +/*##################################################################### */ + + /* + * Register : DRAMTMG0 @ 0XFD070100 + + * Minimum time between write and precharge to same bank. Unit: Clocks Spec + * ifications: WL + BL/2 + tWR = approximately 8 cycles + 15 ns = 14 clocks + * @400MHz and less for lower frequencies where: - WL = write latency - BL + * = burst length. This must match the value programmed in the BL bit of t + * he mode register to the SDRAM. BST (burst terminate) is not supported at + * present. - tWR = Write recovery time. This comes directly from the SDRA + * M specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 for this p + * arameter. For configurations with MEMC_FREQ_RATIO=2, 1T mode, divide the + * above value by 2. No rounding up. For configurations with MEMC_FREQ_RAT + * IO=2, 2T mode or LPDDR4 mode, divide the above value by 2 and round it u + * p to the next integer value. + * PSU_DDRC_DRAMTMG0_WR2PRE 0x11 + + * tFAW Valid only when 8 or more banks(or banks x bank groups) are present + * . In 8-bank design, at most 4 banks must be activated in a rolling windo + * w of tFAW cycles. For configurations with MEMC_FREQ_RATIO=2, program thi + * s to (tFAW/2) and round up to next integer value. In a 4-bank design, se + * t this register to 0x1 independent of the MEMC_FREQ_RATIO configuration. + * Unit: Clocks + * PSU_DDRC_DRAMTMG0_T_FAW 0x10 + + * tRAS(max): Maximum time between activate and precharge to same bank. Thi + * s is the maximum time that a page can be kept open Minimum value of this + * register is 1. Zero is invalid. For configurations with MEMC_FREQ_RATIO + * =2, program this to (tRAS(max)-1)/2. No rounding up. Unit: Multiples of + * 1024 clocks. + * PSU_DDRC_DRAMTMG0_T_RAS_MAX 0x24 + + * tRAS(min): Minimum time between activate and precharge to the same bank. + * For configurations with MEMC_FREQ_RATIO=2, 1T mode, program this to tRA + * S(min)/2. No rounding up. For configurations with MEMC_FREQ_RATIO=2, 2T + * mode or LPDDR4 mode, program this to (tRAS(min)/2) and round it up to th + * e next integer value. Unit: Clocks + * PSU_DDRC_DRAMTMG0_T_RAS_MIN 0x12 + + * SDRAM Timing Register 0 + * (OFFSET, MASK, VALUE) (0XFD070100, 0x7F3F7F3FU ,0x11102412U) + */ + PSU_Mask_Write(DDRC_DRAMTMG0_OFFSET, 0x7F3F7F3FU, 0x11102412U); +/*##################################################################### */ + + /* + * Register : DRAMTMG1 @ 0XFD070104 + + * tXP: Minimum time after power-down exit to any operation. For DDR3, this + * should be programmed to tXPDLL if slow powerdown exit is selected in MR + * 0[12]. If C/A parity for DDR4 is used, set to (tXP+PL) instead. For conf + * igurations with MEMC_FREQ_RATIO=2, program this to (tXP/2) and round it + * up to the next integer value. Units: Clocks + * PSU_DDRC_DRAMTMG1_T_XP 0x4 + + * tRTP: Minimum time from read to precharge of same bank. - DDR2: tAL + BL + * /2 + max(tRTP, 2) - 2 - DDR3: tAL + max (tRTP, 4) - DDR4: Max of followi + * ng two equations: tAL + max (tRTP, 4) or, RL + BL/2 - tRP. - mDDR: BL/2 + * - LPDDR2: Depends on if it's LPDDR2-S2 or LPDDR2-S4: LPDDR2-S2: BL/2 + t + * RTP - 1. LPDDR2-S4: BL/2 + max(tRTP,2) - 2. - LPDDR3: BL/2 + max(tRTP,4) + * - 4 - LPDDR4: BL/2 + max(tRTP,8) - 8 For configurations with MEMC_FREQ_ + * RATIO=2, 1T mode, divide the above value by 2. No rounding up. For confi + * gurations with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, divide the abo + * ve value by 2 and round it up to the next integer value. Unit: Clocks. + * PSU_DDRC_DRAMTMG1_RD2PRE 0x4 + + * tRC: Minimum time between activates to same bank. For configurations wit + * h MEMC_FREQ_RATIO=2, program this to (tRC/2) and round up to next intege + * r value. Unit: Clocks. + * PSU_DDRC_DRAMTMG1_T_RC 0x1a + + * SDRAM Timing Register 1 + * (OFFSET, MASK, VALUE) (0XFD070104, 0x001F1F7FU ,0x0004041AU) + */ + PSU_Mask_Write(DDRC_DRAMTMG1_OFFSET, 0x001F1F7FU, 0x0004041AU); +/*##################################################################### */ + + /* + * Register : DRAMTMG2 @ 0XFD070108 + + * Set to WL Time from write command to write data on SDRAM interface. This + * must be set to WL. For mDDR, it should normally be set to 1. Note that, + * depending on the PHY, if using RDIMM, it may be necessary to use a valu + * e of WL + 1 to compensate for the extra cycle of latency through the RDI + * MM For configurations with MEMC_FREQ_RATIO=2, divide the value calculate + * d using the above equation by 2, and round it up to next integer. This r + * egister field is not required for DDR2 and DDR3 (except if MEMC_TRAINING + * is set), as the DFI read and write latencies defined in DFITMG0 and DFI + * TMG1 are sufficient for those protocols Unit: clocks + * PSU_DDRC_DRAMTMG2_WRITE_LATENCY 0x7 + + * Set to RL Time from read command to read data on SDRAM interface. This m + * ust be set to RL. Note that, depending on the PHY, if using RDIMM, it ma + * t be necessary to use a value of RL + 1 to compensate for the extra cycl + * e of latency through the RDIMM For configurations with MEMC_FREQ_RATIO=2 + * , divide the value calculated using the above equation by 2, and round i + * t up to next integer. This register field is not required for DDR2 and D + * DR3 (except if MEMC_TRAINING is set), as the DFI read and write latencie + * s defined in DFITMG0 and DFITMG1 are sufficient for those protocols Unit + * : clocks + * PSU_DDRC_DRAMTMG2_READ_LATENCY 0x8 + + * DDR2/3/mDDR: RL + BL/2 + 2 - WL DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL L + * PDDR2/LPDDR3: RL + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL LPDDR4(DQ ODT is Di + * sabled): RL + BL/2 + RU(tDQSCKmax/tCK) + WR_PREAMBLE + RD_POSTAMBLE - WL + * LPDDR4(DQ ODT is Enabled) : RL + BL/2 + RU(tDQSCKmax/tCK) + RD_POSTAMBL + * E - ODTLon - RU(tODTon(min)/tCK) Minimum time from read command to write + * command. Include time for bus turnaround and all per-bank, per-rank, an + * d global constraints. Unit: Clocks. Where: - WL = write latency - BL = b + * urst length. This must match the value programmed in the BL bit of the m + * ode register to the SDRAM - RL = read latency = CAS latency - WR_PREAMBL + * E = write preamble. This is unique to DDR4 and LPDDR4. - RD_POSTAMBLE = + * read postamble. This is unique to LPDDR4. For LPDDR2/LPDDR3/LPDDR4, if d + * erating is enabled (DERATEEN.derate_enable=1), derated tDQSCKmax should + * be used. For configurations with MEMC_FREQ_RATIO=2, divide the value cal + * culated using the above equation by 2, and round it up to next integer. + * PSU_DDRC_DRAMTMG2_RD2WR 0x6 + + * DDR4: CWL + PL + BL/2 + tWTR_L Others: CWL + BL/2 + tWTR In DDR4, minimu + * m time from write command to read command for same bank group. In others + * , minimum time from write command to read command. Includes time for bus + * turnaround, recovery times, and all per-bank, per-rank, and global cons + * traints. Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity la + * tency - BL = burst length. This must match the value programmed in the B + * L bit of the mode register to the SDRAM - tWTR_L = internal write to rea + * d command delay for same bank group. This comes directly from the SDRAM + * specification. - tWTR = internal write to read command delay. This comes + * directly from the SDRAM specification. Add one extra cycle for LPDDR2/L + * PDDR3/LPDDR4 operation. For configurations with MEMC_FREQ_RATIO=2, divid + * e the value calculated using the above equation by 2, and round it up to + * next integer. + * PSU_DDRC_DRAMTMG2_WR2RD 0xd + + * SDRAM Timing Register 2 + * (OFFSET, MASK, VALUE) (0XFD070108, 0x3F3F3F3FU ,0x0708060DU) + */ + PSU_Mask_Write(DDRC_DRAMTMG2_OFFSET, 0x3F3F3F3FU, 0x0708060DU); +/*##################################################################### */ + + /* + * Register : DRAMTMG3 @ 0XFD07010C + + * Time to wait after a mode register write or read (MRW or MRR). Present o + * nly in designs configured to support LPDDR2, LPDDR3 or LPDDR4. LPDDR2 ty + * pically requires value of 5. LPDDR3 typically requires value of 10. LPDD + * R4: Set this to the larger of tMRW and tMRWCKEL. For LPDDR2, this regist + * er is used for the time from a MRW/MRR to all other commands. For LDPDR3 + * , this register is used for the time from a MRW/MRR to a MRW/MRR. + * PSU_DDRC_DRAMTMG3_T_MRW 0x5 + + * tMRD: Cycles to wait after a mode register write or read. Depending on t + * he connected SDRAM, tMRD represents: DDR2/mDDR: Time from MRS to any com + * mand DDR3/4: Time from MRS to MRS command LPDDR2: not used LPDDR3/4: Tim + * e from MRS to non-MRS command For configurations with MEMC_FREQ_RATIO=2, + * program this to (tMRD/2) and round it up to the next integer value. If + * C/A parity for DDR4 is used, set to tMRD_PAR(tMOD+PL) instead. + * PSU_DDRC_DRAMTMG3_T_MRD 0x4 + + * tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode com + * mand and following non-load mode command. If C/A parity for DDR4 is used + * , set to tMOD_PAR(tMOD+PL) instead. Set to tMOD if MEMC_FREQ_RATIO=1, or + * tMOD/2 (rounded up to next integer) if MEMC_FREQ_RATIO=2. Note that if + * using RDIMM, depending on the PHY, it may be necessary to use a value of + * tMOD + 1 or (tMOD + 1)/2 to compensate for the extra cycle of latency a + * pplied to mode register writes by the RDIMM chip. + * PSU_DDRC_DRAMTMG3_T_MOD 0xc + + * SDRAM Timing Register 3 + * (OFFSET, MASK, VALUE) (0XFD07010C, 0x3FF3F3FFU ,0x0050400CU) + */ + PSU_Mask_Write(DDRC_DRAMTMG3_OFFSET, 0x3FF3F3FFU, 0x0050400CU); +/*##################################################################### */ + + /* + * Register : DRAMTMG4 @ 0XFD070110 + + * tRCD - tAL: Minimum time from activate to read or write command to same + * bank. For configurations with MEMC_FREQ_RATIO=2, program this to ((tRCD + * - tAL)/2) and round it up to the next integer value. Minimum value allow + * ed for this register is 1, which implies minimum (tRCD - tAL) value to b + * e 2 in configurations with MEMC_FREQ_RATIO=2. Unit: Clocks. + * PSU_DDRC_DRAMTMG4_T_RCD 0x8 + + * DDR4: tCCD_L: This is the minimum time between two reads or two writes f + * or same bank group. Others: tCCD: This is the minimum time between two r + * eads or two writes. For configurations with MEMC_FREQ_RATIO=2, program t + * his to (tCCD_L/2 or tCCD/2) and round it up to the next integer value. U + * nit: clocks. + * PSU_DDRC_DRAMTMG4_T_CCD 0x3 + + * DDR4: tRRD_L: Minimum time between activates from bank 'a' to bank 'b' f + * or same bank group. Others: tRRD: Minimum time between activates from ba + * nk 'a' to bank 'b'For configurations with MEMC_FREQ_RATIO=2, program thi + * s to (tRRD_L/2 or tRRD/2) and round it up to the next integer value. Uni + * t: Clocks. + * PSU_DDRC_DRAMTMG4_T_RRD 0x3 + + * tRP: Minimum time from precharge to activate of same bank. For MEMC_FREQ + * _RATIO=1 configurations, t_rp should be set to RoundUp(tRP/tCK). For MEM + * C_FREQ_RATIO=2 configurations, t_rp should be set to RoundDown(RoundUp(t + * RP/tCK)/2) + 1. For MEMC_FREQ_RATIO=2 configurations in LPDDR4, t_rp sho + * uld be set to RoundUp(RoundUp(tRP/tCK)/2). Unit: Clocks. + * PSU_DDRC_DRAMTMG4_T_RP 0x9 + + * SDRAM Timing Register 4 + * (OFFSET, MASK, VALUE) (0XFD070110, 0x1F0F0F1FU ,0x08030309U) + */ + PSU_Mask_Write(DDRC_DRAMTMG4_OFFSET, 0x1F0F0F1FU, 0x08030309U); +/*##################################################################### */ + + /* + * Register : DRAMTMG5 @ 0XFD070114 + + * This is the time before Self Refresh Exit that CK is maintained as a val + * id clock before issuing SRX. Specifies the clock stable time before SRX. + * Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCK + * EH - DDR2: 1 - DDR3: tCKSRX - DDR4: tCKSRX For configurations with MEMC_ + * FREQ_RATIO=2, program this to recommended value divided by two and round + * it up to next integer. + * PSU_DDRC_DRAMTMG5_T_CKSRX 0x6 + + * This is the time after Self Refresh Down Entry that CK is maintained as + * a valid clock. Specifies the clock disable delay after SRE. Recommended + * settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL - DDR2: 1 + * - DDR3: max (10 ns, 5 tCK) - DDR4: max (10 ns, 5 tCK) For configurations + * with MEMC_FREQ_RATIO=2, program this to recommended value divided by tw + * o and round it up to next integer. + * PSU_DDRC_DRAMTMG5_T_CKSRE 0x6 + + * Minimum CKE low width for Self refresh or Self refresh power down entry + * to exit timing in memory clock cycles. Recommended settings: - mDDR: tRF + * C - LPDDR2: tCKESR - LPDDR3: tCKESR - LPDDR4: max(tCKELPD, tSR) - DDR2: + * tCKE - DDR3: tCKE + 1 - DDR4: tCKE + 1 For configurations with MEMC_FREQ + * _RATIO=2, program this to recommended value divided by two and round it + * up to next integer. + * PSU_DDRC_DRAMTMG5_T_CKESR 0x4 + + * Minimum number of cycles of CKE HIGH/LOW during power-down and self refr + * esh. - LPDDR2/LPDDR3 mode: Set this to the larger of tCKE or tCKESR - LP + * DDR4 mode: Set this to the larger of tCKE, tCKELPD or tSR. - Non-LPDDR2/ + * non-LPDDR3/non-LPDDR4 designs: Set this to tCKE value. For configuration + * s with MEMC_FREQ_RATIO=2, program this to (value described above)/2 and + * round it up to the next integer value. Unit: Clocks. + * PSU_DDRC_DRAMTMG5_T_CKE 0x3 + + * SDRAM Timing Register 5 + * (OFFSET, MASK, VALUE) (0XFD070114, 0x0F0F3F1FU ,0x06060403U) + */ + PSU_Mask_Write(DDRC_DRAMTMG5_OFFSET, 0x0F0F3F1FU, 0x06060403U); +/*##################################################################### */ + + /* + * Register : DRAMTMG6 @ 0XFD070118 + + * This is the time after Deep Power Down Entry that CK is maintained as a + * valid clock. Specifies the clock disable delay after DPDE. Recommended s + * ettings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 For configurations with MEMC_ + * FREQ_RATIO=2, program this to recommended value divided by two and round + * it up to next integer. This is only present for designs supporting mDDR + * or LPDDR2/LPDDR3 devices. + * PSU_DDRC_DRAMTMG6_T_CKDPDE 0x1 + + * This is the time before Deep Power Down Exit that CK is maintained as a + * valid clock before issuing DPDX. Specifies the clock stable time before + * DPDX. Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 For config + * urations with MEMC_FREQ_RATIO=2, program this to recommended value divid + * ed by two and round it up to next integer. This is only present for desi + * gns supporting mDDR or LPDDR2 devices. + * PSU_DDRC_DRAMTMG6_T_CKDPDX 0x1 + + * This is the time before Clock Stop Exit that CK is maintained as a valid + * clock before issuing Clock Stop Exit. Specifies the clock stable time b + * efore next command after Clock Stop Exit. Recommended settings: - mDDR: + * 1 - LPDDR2: tXP + 2 - LPDDR3: tXP + 2 - LPDDR4: tXP + 2 For configuratio + * ns with MEMC_FREQ_RATIO=2, program this to recommended value divided by + * two and round it up to next integer. This is only present for designs su + * pporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices. + * PSU_DDRC_DRAMTMG6_T_CKCSX 0x4 + + * SDRAM Timing Register 6 + * (OFFSET, MASK, VALUE) (0XFD070118, 0x0F0F000FU ,0x01010004U) + */ + PSU_Mask_Write(DDRC_DRAMTMG6_OFFSET, 0x0F0F000FU, 0x01010004U); +/*##################################################################### */ + + /* + * Register : DRAMTMG7 @ 0XFD07011C + + * This is the time after Power Down Entry that CK is maintained as a valid + * clock. Specifies the clock disable delay after PDE. Recommended setting + * s: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL For configuration + * s with MEMC_FREQ_RATIO=2, program this to recommended value divided by t + * wo and round it up to next integer. This is only present for designs sup + * porting mDDR or LPDDR2/LPDDR3/LPDDR4 devices. + * PSU_DDRC_DRAMTMG7_T_CKPDE 0x6 + + * This is the time before Power Down Exit that CK is maintained as a valid + * clock before issuing PDX. Specifies the clock stable time before PDX. R + * ecommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: 2 For c + * onfigurations with MEMC_FREQ_RATIO=2, program this to recommended value + * divided by two and round it up to next integer. This is only present for + * designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices. + * PSU_DDRC_DRAMTMG7_T_CKPDX 0x6 + + * SDRAM Timing Register 7 + * (OFFSET, MASK, VALUE) (0XFD07011C, 0x00000F0FU ,0x00000606U) + */ + PSU_Mask_Write(DDRC_DRAMTMG7_OFFSET, 0x00000F0FU, 0x00000606U); +/*##################################################################### */ + + /* + * Register : DRAMTMG8 @ 0XFD070120 + + * tXS_FAST: Exit Self Refresh to ZQCL, ZQCS and MRS (only CL, WR, RTP and + * Geardown mode). For configurations with MEMC_FREQ_RATIO=2, program this + * to the above value divided by 2 and round up to next integer value. Unit + * : Multiples of 32 clocks. Note: This is applicable to only ZQCL/ZQCS com + * mands. Note: Ensure this is less than or equal to t_xs_x32. + * PSU_DDRC_DRAMTMG8_T_XS_FAST_X32 0x3 + + * tXS_ABORT: Exit Self Refresh to commands not requiring a locked DLL in S + * elf Refresh Abort. For configurations with MEMC_FREQ_RATIO=2, program th + * is to the above value divided by 2 and round up to next integer value. U + * nit: Multiples of 32 clocks. Note: Ensure this is less than or equal to + * t_xs_x32. + * PSU_DDRC_DRAMTMG8_T_XS_ABORT_X32 0x3 + + * tXSDLL: Exit Self Refresh to commands requiring a locked DLL. For config + * urations with MEMC_FREQ_RATIO=2, program this to the above value divided + * by 2 and round up to next integer value. Unit: Multiples of 32 clocks. + * Note: Used only for DDR2, DDR3 and DDR4 SDRAMs. + * PSU_DDRC_DRAMTMG8_T_XS_DLL_X32 0xd + + * tXS: Exit Self Refresh to commands not requiring a locked DLL. For confi + * gurations with MEMC_FREQ_RATIO=2, program this to the above value divide + * d by 2 and round up to next integer value. Unit: Multiples of 32 clocks. + * Note: Used only for DDR2, DDR3 and DDR4 SDRAMs. + * PSU_DDRC_DRAMTMG8_T_XS_X32 0x6 + + * SDRAM Timing Register 8 + * (OFFSET, MASK, VALUE) (0XFD070120, 0x7F7F7F7FU ,0x03030D06U) + */ + PSU_Mask_Write(DDRC_DRAMTMG8_OFFSET, 0x7F7F7F7FU, 0x03030D06U); +/*##################################################################### */ + + /* + * Register : DRAMTMG9 @ 0XFD070124 + + * DDR4 Write preamble mode - 0: 1tCK preamble - 1: 2tCK preamble Present o + * nly with MEMC_FREQ_RATIO=2 + * PSU_DDRC_DRAMTMG9_DDR4_WR_PREAMBLE 0x0 + + * tCCD_S: This is the minimum time between two reads or two writes for dif + * ferent bank group. For bank switching (from bank 'a' to bank 'b'), the m + * inimum time is this value + 1. For configurations with MEMC_FREQ_RATIO=2 + * , program this to (tCCD_S/2) and round it up to the next integer value. + * Present only in designs configured to support DDR4. Unit: clocks. + * PSU_DDRC_DRAMTMG9_T_CCD_S 0x2 + + * tRRD_S: Minimum time between activates from bank 'a' to bank 'b' for dif + * ferent bank group. For configurations with MEMC_FREQ_RATIO=2, program th + * is to (tRRD_S/2) and round it up to the next integer value. Present only + * in designs configured to support DDR4. Unit: Clocks. + * PSU_DDRC_DRAMTMG9_T_RRD_S 0x2 + + * CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command + * for different bank group. Includes time for bus turnaround, recovery ti + * mes, and all per-bank, per-rank, and global constraints. Present only in + * designs configured to support DDR4. Unit: Clocks. Where: - CWL = CAS wr + * ite latency - PL = Parity latency - BL = burst length. This must match t + * he value programmed in the BL bit of the mode register to the SDRAM - tW + * TR_S = internal write to read command delay for different bank group. Th + * is comes directly from the SDRAM specification. For configurations with + * MEMC_FREQ_RATIO=2, divide the value calculated using the above equation + * by 2, and round it up to next integer. + * PSU_DDRC_DRAMTMG9_WR2RD_S 0xb + + * SDRAM Timing Register 9 + * (OFFSET, MASK, VALUE) (0XFD070124, 0x40070F3FU ,0x0002020BU) + */ + PSU_Mask_Write(DDRC_DRAMTMG9_OFFSET, 0x40070F3FU, 0x0002020BU); +/*##################################################################### */ + + /* + * Register : DRAMTMG11 @ 0XFD07012C + + * tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DL + * L. For configurations with MEMC_FREQ_RATIO=2, program this to (tXMPDLL/2 + * ) and round it up to the next integer value. Present only in designs con + * figured to support DDR4. Unit: Multiples of 32 clocks. + * PSU_DDRC_DRAMTMG11_POST_MPSM_GAP_X32 0x70 + + * tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge. For + * configurations with MEMC_FREQ_RATIO=2, program this to RoundUp(tMPX_LH/2 + * )+1. Present only in designs configured to support DDR4. Unit: clocks. + * PSU_DDRC_DRAMTMG11_T_MPX_LH 0x7 + + * tMPX_S: Minimum time CS setup time to CKE. For configurations with MEMC_ + * FREQ_RATIO=2, program this to (tMPX_S/2) and round it up to the next int + * eger value. Present only in designs configured to support DDR4. Unit: Cl + * ocks. + * PSU_DDRC_DRAMTMG11_T_MPX_S 0x1 + + * tCKMPE: Minimum valid clock requirement after MPSM entry. Present only i + * n designs configured to support DDR4. Unit: Clocks. For configurations w + * ith MEMC_FREQ_RATIO=2, divide the value calculated using the above equat + * ion by 2, and round it up to next integer. + * PSU_DDRC_DRAMTMG11_T_CKMPE 0xe + + * SDRAM Timing Register 11 + * (OFFSET, MASK, VALUE) (0XFD07012C, 0x7F1F031FU ,0x7007010EU) + */ + PSU_Mask_Write(DDRC_DRAMTMG11_OFFSET, 0x7F1F031FU, 0x7007010EU); +/*##################################################################### */ + + /* + * Register : DRAMTMG12 @ 0XFD070130 + + * tCMDCKE: Delay from valid command to CKE input LOW. Set this to the larg + * er of tESCKE or tCMDCKE For configurations with MEMC_FREQ_RATIO=2, progr + * am this to (max(tESCKE, tCMDCKE)/2) and round it up to next integer valu + * e. + * PSU_DDRC_DRAMTMG12_T_CMDCKE 0x2 + + * tCKEHCMD: Valid command requirement after CKE input HIGH. For configurat + * ions with MEMC_FREQ_RATIO=2, program this to (tCKEHCMD/2) and round it u + * p to next integer value. + * PSU_DDRC_DRAMTMG12_T_CKEHCMD 0x6 + + * tMRD_PDA: This is the Mode Register Set command cycle time in PDA mode. + * For configurations with MEMC_FREQ_RATIO=2, program this to (tMRD_PDA/2) + * and round it up to next integer value. + * PSU_DDRC_DRAMTMG12_T_MRD_PDA 0x8 + + * SDRAM Timing Register 12 + * (OFFSET, MASK, VALUE) (0XFD070130, 0x00030F1FU ,0x00020608U) + */ + PSU_Mask_Write(DDRC_DRAMTMG12_OFFSET, 0x00030F1FU, 0x00020608U); +/*##################################################################### */ + + /* + * Register : ZQCTL0 @ 0XFD070180 + + * - 1 - Disable uMCTL2 generation of ZQCS/MPC(ZQ calibration) command. Reg + * ister DBGCMD.zq_calib_short can be used instead to issue ZQ calibration + * request from APB module. - 0 - Internally generate ZQCS/MPC(ZQ calibrati + * on) commands based on ZQCTL1.t_zq_short_interval_x1024. This is only pre + * sent for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. + * PSU_DDRC_ZQCTL0_DIS_AUTO_ZQ 0x1 + + * - 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refres + * h/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 + * or LPDDR3 or LPDDR4 mode. - 0 - Enable issuing of ZQCL/MPC(ZQ calibratio + * n) command at Self-Refresh/SR-Powerdown exit. Only applicable when run i + * n DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. This is only present + * for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. + * PSU_DDRC_ZQCTL0_DIS_SRX_ZQCL 0x0 + + * - 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQC + * L/ZQCS/MPC(ZQ calibration) commands are sent to one rank at a time with + * tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that co + * mmands to different ranks do not overlap. - 0 - ZQ resistor is not share + * d. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR + * 3/LPDDR4 devices. + * PSU_DDRC_ZQCTL0_ZQ_RESISTOR_SHARED 0x0 + + * - 1 - Disable issuing of ZQCL command at Maximum Power Saving Mode exit. + * Only applicable when run in DDR4 mode. - 0 - Enable issuing of ZQCL com + * mand at Maximum Power Saving Mode exit. Only applicable when run in DDR4 + * mode. This is only present for designs supporting DDR4 devices. + * PSU_DDRC_ZQCTL0_DIS_MPSMX_ZQCL 0x0 + + * tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Numbe + * r of cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ St + * art) command is issued to SDRAM. For configurations with MEMC_FREQ_RATIO + * =2: DDR3/DDR4: program this to tZQoper/2 and round it up to the next int + * eger value. LPDDR2/LPDDR3: program this to tZQCL/2 and round it up to th + * e next integer value. LPDDR4: program this to tZQCAL/2 and round it up t + * o the next integer value. Unit: Clock cycles. This is only present for d + * esigns supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. + * PSU_DDRC_ZQCTL0_T_ZQ_LONG_NOP 0x100 + + * tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of cycles of + * NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command + * is issued to SDRAM. For configurations with MEMC_FREQ_RATIO=2, program t + * his to tZQCS/2 and round it up to the next integer value. Unit: Clock cy + * cles. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LP + * DDR3/LPDDR4 devices. + * PSU_DDRC_ZQCTL0_T_ZQ_SHORT_NOP 0x40 + + * ZQ Control Register 0 + * (OFFSET, MASK, VALUE) (0XFD070180, 0xF7FF03FFU ,0x81000040U) + */ + PSU_Mask_Write(DDRC_ZQCTL0_OFFSET, 0xF7FF03FFU, 0x81000040U); +/*##################################################################### */ + + /* + * Register : ZQCTL1 @ 0XFD070184 + + * tZQReset: Number of cycles of NOP required after a ZQReset (ZQ calibrati + * on Reset) command is issued to SDRAM. For configurations with MEMC_FREQ_ + * RATIO=2, program this to tZQReset/2 and round it up to the next integer + * value. Unit: Clock cycles. This is only present for designs supporting L + * PDDR2/LPDDR3/LPDDR4 devices. + * PSU_DDRC_ZQCTL1_T_ZQ_RESET_NOP 0x20 + + * Average interval to wait between automatically issuing ZQCS (ZQ calibrat + * ion short)/MPC(ZQ calibration) commands to DDR3/DDR4/LPDDR2/LPDDR3/LPDDR + * 4 devices. Meaningless, if ZQCTL0.dis_auto_zq=1. Unit: 1024 clock cycles + * . This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3 + * /LPDDR4 devices. + * PSU_DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024 0x196dc + + * ZQ Control Register 1 + * (OFFSET, MASK, VALUE) (0XFD070184, 0x3FFFFFFFU ,0x020196DCU) + */ + PSU_Mask_Write(DDRC_ZQCTL1_OFFSET, 0x3FFFFFFFU, 0x020196DCU); +/*##################################################################### */ + + /* + * Register : DFITMG0 @ 0XFD070190 + + * Specifies the number of DFI clock cycles after an assertion or de-assert + * ion of the DFI control signals that the control signals at the PHY-DRAM + * interface reflect the assertion or de-assertion. If the DFI clock and th + * e memory clock are not phase-aligned, this timing parameter should be ro + * unded up to the next integer value. Note that if using RDIMM, it is nece + * ssary to increment this parameter by RDIMM's extra cycle of latency in t + * erms of DFI clock. + * PSU_DDRC_DFITMG0_DFI_T_CTRL_DELAY 0x4 + + * Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated u + * sing HDR or SDR values Selects whether value in DFITMG0.dfi_t_rddata_en + * is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles + * - 1 in terms of SDR clock cycles Refer to PHY specification for correct + * value. + * PSU_DDRC_DFITMG0_DFI_RDDATA_USE_SDR 0x1 + + * Time from the assertion of a read command on the DFI interface to the as + * sertion of the dfi_rddata_en signal. Refer to PHY specification for corr + * ect value. This corresponds to the DFI parameter trddata_en. Note that, + * depending on the PHY, if using RDIMM, it may be necessary to use the val + * ue (CL + 1) in the calculation of trddata_en. This is to compensate for + * the extra cycle of latency through the RDIMM. Unit: Clocks + * PSU_DDRC_DFITMG0_DFI_T_RDDATA_EN 0xb + + * Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated us + * ing HDR or SDR values Selects whether value in DFITMG0.dfi_tphy_wrlat is + * in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.df + * i_tphy_wrdata is in terms of SDR or HDR clock cycles - 0 in terms of HDR + * clock cycles - 1 in terms of SDR clock cycles Refer to PHY specificatio + * n for correct value. + * PSU_DDRC_DFITMG0_DFI_WRDATA_USE_SDR 0x1 + + * Specifies the number of clock cycles between when dfi_wrdata_en is asser + * ted to when the associated write data is driven on the dfi_wrdata signal + * . This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY + * specification for correct value. Note, max supported value is 8. Unit: + * Clocks + * PSU_DDRC_DFITMG0_DFI_TPHY_WRDATA 0x2 + + * Write latency Number of clocks from the write command to write data enab + * le (dfi_wrdata_en). This corresponds to the DFI timing parameter tphy_wr + * lat. Refer to PHY specification for correct value.Note that, depending o + * n the PHY, if using RDIMM, it may be necessary to use the value (CL + 1) + * in the calculation of tphy_wrlat. This is to compensate for the extra c + * ycle of latency through the RDIMM. + * PSU_DDRC_DFITMG0_DFI_TPHY_WRLAT 0xb + + * DFI Timing Register 0 + * (OFFSET, MASK, VALUE) (0XFD070190, 0x1FBFBF3FU ,0x048B820BU) + */ + PSU_Mask_Write(DDRC_DFITMG0_OFFSET, 0x1FBFBF3FU, 0x048B820BU); +/*##################################################################### */ + + /* + * Register : DFITMG1 @ 0XFD070194 + + * Specifies the number of DFI PHY clocks between when the dfi_cs signal is + * asserted and when the associated command is driven. This field is used + * for CAL mode, should be set to '0' or the value which matches the CAL mo + * de register setting in the DRAM. If the PHY can add the latency for CAL + * mode, this should be set to '0'. Valid Range: 0, 3, 4, 5, 6, and 8 + * PSU_DDRC_DFITMG1_DFI_T_CMD_LAT 0x0 + + * Specifies the number of DFI PHY clocks between when the dfi_cs signal is + * asserted and when the associated dfi_parity_in signal is driven. + * PSU_DDRC_DFITMG1_DFI_T_PARIN_LAT 0x0 + + * Specifies the number of DFI clocks between when the dfi_wrdata_en signal + * is asserted and when the corresponding write data transfer is completed + * on the DRAM bus. This corresponds to the DFI timing parameter twrdata_d + * elay. Refer to PHY specification for correct value. For DFI 3.0 PHY, set + * to twrdata_delay, a new timing parameter introduced in DFI 3.0. For DFI + * 2.1 PHY, set to tphy_wrdata + (delay of DFI write data to the DRAM). Va + * lue to be programmed is in terms of DFI clocks, not PHY clocks. In FREQ_ + * RATIO=2, divide PHY's value by 2 and round up to next integer. If using + * DFITMG0.dfi_wrdata_use_sdr=1, add 1 to the value. Unit: Clocks + * PSU_DDRC_DFITMG1_DFI_T_WRDATA_DELAY 0x3 + + * Specifies the number of DFI clock cycles from the assertion of the dfi_d + * ram_clk_disable signal on the DFI until the clock to the DRAM memory dev + * ices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock + * and the memory clock are not phase aligned, this timing parameter should + * be rounded up to the next integer value. + * PSU_DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE 0x3 + + * Specifies the number of DFI clock cycles from the de-assertion of the df + * i_dram_clk_disable signal on the DFI until the first valid rising edge o + * f the clock to the DRAM memory devices, at the PHY-DRAM boundary. If the + * DFI clock and the memory clock are not phase aligned, this timing param + * eter should be rounded up to the next integer value. + * PSU_DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE 0x4 + + * DFI Timing Register 1 + * (OFFSET, MASK, VALUE) (0XFD070194, 0xF31F0F0FU ,0x00030304U) + */ + PSU_Mask_Write(DDRC_DFITMG1_OFFSET, 0xF31F0F0FU, 0x00030304U); +/*##################################################################### */ + + /* + * Register : DFILPCFG0 @ 0XFD070198 + + * Setting for DFI's tlp_resp time. Same value is used for both Power Down, + * Self Refresh, Deep Power Down and Maximum Power Saving modes. DFI 2.1 s + * pecification onwards, recommends using a fixed value of 7 always. + * PSU_DDRC_DFILPCFG0_DFI_TLP_RESP 0x7 + + * Value to drive on dfi_lp_wakeup signal when Deep Power Down mode is ente + * red. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32 + * cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 5 + * 12 cycles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycles - + * 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 6553 + * 6 cycles - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited T + * his is only present for designs supporting mDDR or LPDDR2/LPDDR3 devices + * . + * PSU_DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD 0x0 + + * Enables DFI Low Power interface handshaking during Deep Power Down Entry + * /Exit. - 0 - Disabled - 1 - Enabled This is only present for designs sup + * porting mDDR or LPDDR2/LPDDR3 devices. + * PSU_DDRC_DFILPCFG0_DFI_LP_EN_DPD 0x0 + + * Value to drive on dfi_lp_wakeup signal when Self Refresh mode is entered + * . Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32 cyc + * les - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 + * cycles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycles - 0x9 + * - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 c + * ycles - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited + * PSU_DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR 0x0 + + * Enables DFI Low Power interface handshaking during Self Refresh Entry/Ex + * it. - 0 - Disabled - 1 - Enabled + * PSU_DDRC_DFILPCFG0_DFI_LP_EN_SR 0x1 + + * Value to drive on dfi_lp_wakeup signal when Power Down mode is entered. + * Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32 cycle + * s - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cy + * cles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycles - 0x9 - + * 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cyc + * les - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited + * PSU_DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD 0x0 + + * Enables DFI Low Power interface handshaking during Power Down Entry/Exit + * . - 0 - Disabled - 1 - Enabled + * PSU_DDRC_DFILPCFG0_DFI_LP_EN_PD 0x1 + + * DFI Low Power Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD070198, 0x0FF1F1F1U ,0x07000101U) + */ + PSU_Mask_Write(DDRC_DFILPCFG0_OFFSET, 0x0FF1F1F1U, 0x07000101U); +/*##################################################################### */ + + /* + * Register : DFILPCFG1 @ 0XFD07019C + + * Value to drive on dfi_lp_wakeup signal when Maximum Power Saving Mode is + * entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 + * - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x + * 5 - 512 cycles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycl + * es - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - + * 65536 cycles - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimi + * ted This is only present for designs supporting DDR4 devices. + * PSU_DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM 0x2 + + * Enables DFI Low Power interface handshaking during Maximum Power Saving + * Mode Entry/Exit. - 0 - Disabled - 1 - Enabled This is only present for d + * esigns supporting DDR4 devices. + * PSU_DDRC_DFILPCFG1_DFI_LP_EN_MPSM 0x1 + + * DFI Low Power Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD07019C, 0x000000F1U ,0x00000021U) + */ + PSU_Mask_Write(DDRC_DFILPCFG1_OFFSET, 0x000000F1U, 0x00000021U); +/*##################################################################### */ + + /* + * Register : DFIUPD0 @ 0XFD0701A0 + + * When '1', disable the automatic dfi_ctrlupd_req generation by the uMCTL2 + * . The core must issue the dfi_ctrlupd_req signal using register reg_ddrc + * _ctrlupd. When '0', uMCTL2 issues dfi_ctrlupd_req periodically. + * PSU_DDRC_DFIUPD0_DIS_AUTO_CTRLUPD 0x0 + + * When '1', disable the automatic dfi_ctrlupd_req generation by the uMCTL2 + * following a self-refresh exit. The core must issue the dfi_ctrlupd_req + * signal using register reg_ddrc_ctrlupd. When '0', uMCTL2 issues a dfi_ct + * rlupd_req after exiting self-refresh. + * PSU_DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX 0x0 + + * Specifies the maximum number of clock cycles that the dfi_ctrlupd_req si + * gnal can assert. Lowest value to assign to this variable is 0x40. Unit: + * Clocks + * PSU_DDRC_DFIUPD0_DFI_T_CTRLUP_MAX 0x40 + + * Specifies the minimum number of clock cycles that the dfi_ctrlupd_req si + * gnal must be asserted. The uMCTL2 expects the PHY to respond within this + * time. If the PHY does not respond, the uMCTL2 will de-assert dfi_ctrlup + * d_req after dfi_t_ctrlup_min + 2 cycles. Lowest value to assign to this + * variable is 0x3. Unit: Clocks + * PSU_DDRC_DFIUPD0_DFI_T_CTRLUP_MIN 0x3 + + * DFI Update Register 0 + * (OFFSET, MASK, VALUE) (0XFD0701A0, 0xC3FF03FFU ,0x00400003U) + */ + PSU_Mask_Write(DDRC_DFIUPD0_OFFSET, 0xC3FF03FFU, 0x00400003U); +/*##################################################################### */ + + /* + * Register : DFIUPD1 @ 0XFD0701A4 + + * This is the minimum amount of time between uMCTL2 initiated DFI update r + * equests (which is executed whenever the uMCTL2 is idle). Set this number + * higher to reduce the frequency of update requests, which can have a sma + * ll impact on the latency of the first read request when the uMCTL2 is id + * le. Unit: 1024 clocks + * PSU_DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024 0x41 + + * This is the maximum amount of time between uMCTL2 initiated DFI update r + * equests. This timer resets with each update request; when the timer expi + * res dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd + * _ackx is received. PHY can use this idle time to recalibrate the delay l + * ines to the DLLs. The DFI controller update is also used to reset PHY FI + * FO pointers in case of data capture errors. Updates are required to main + * tain calibration over PVT, but frequent updates may impact performance. + * Note: Value programmed for DFIUPD1.dfi_t_ctrlupd_interval_max_x1024 must + * be greater than DFIUPD1.dfi_t_ctrlupd_interval_min_x1024. Unit: 1024 cl + * ocks + * PSU_DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024 0xe1 + + * DFI Update Register 1 + * (OFFSET, MASK, VALUE) (0XFD0701A4, 0x00FF00FFU ,0x004100E1U) + */ + PSU_Mask_Write(DDRC_DFIUPD1_OFFSET, 0x00FF00FFU, 0x004100E1U); +/*##################################################################### */ + + /* + * Register : DFIMISC @ 0XFD0701B0 + + * Defines polarity of dfi_wrdata_cs and dfi_rddata_cs signals. - 0: Signal + * s are active low - 1: Signals are active high + * PSU_DDRC_DFIMISC_DFI_DATA_CS_POLARITY 0x0 + + * DBI implemented in DDRC or PHY. - 0 - DDRC implements DBI functionality. + * - 1 - PHY implements DBI functionality. Present only in designs configu + * red to support DDR4 and LPDDR4. + * PSU_DDRC_DFIMISC_PHY_DBI_MODE 0x0 + + * PHY initialization complete enable signal. When asserted the dfi_init_co + * mplete signal can be used to trigger SDRAM initialisation + * PSU_DDRC_DFIMISC_DFI_INIT_COMPLETE_EN 0x0 + + * DFI Miscellaneous Control Register + * (OFFSET, MASK, VALUE) (0XFD0701B0, 0x00000007U ,0x00000000U) + */ + PSU_Mask_Write(DDRC_DFIMISC_OFFSET, 0x00000007U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : DFITMG2 @ 0XFD0701B4 + + * >Number of clocks between when a read command is sent on the DFI control + * interface and when the associated dfi_rddata_cs signal is asserted. Thi + * s corresponds to the DFI timing parameter tphy_rdcslat. Refer to PHY spe + * cification for correct value. + * PSU_DDRC_DFITMG2_DFI_TPHY_RDCSLAT 0x9 + + * Number of clocks between when a write command is sent on the DFI control + * interface and when the associated dfi_wrdata_cs signal is asserted. Thi + * s corresponds to the DFI timing parameter tphy_wrcslat. Refer to PHY spe + * cification for correct value. + * PSU_DDRC_DFITMG2_DFI_TPHY_WRCSLAT 0x6 + + * DFI Timing Register 2 + * (OFFSET, MASK, VALUE) (0XFD0701B4, 0x00003F3FU ,0x00000906U) + */ + PSU_Mask_Write(DDRC_DFITMG2_OFFSET, 0x00003F3FU, 0x00000906U); +/*##################################################################### */ + + /* + * Register : DBICTL @ 0XFD0701C0 + + * Read DBI enable signal in DDRC. - 0 - Read DBI is disabled. - 1 - Read D + * BI is enabled. This signal must be set the same value as DRAM's mode reg + * ister. - DDR4: MR5 bit A12. When x4 devices are used, this signal must b + * e set to 0. - LPDDR4: MR3[6] + * PSU_DDRC_DBICTL_RD_DBI_EN 0x0 + + * Write DBI enable signal in DDRC. - 0 - Write DBI is disabled. - 1 - Writ + * e DBI is enabled. This signal must be set the same value as DRAM's mode + * register. - DDR4: MR5 bit A11. When x4 devices are used, this signal mus + * t be set to 0. - LPDDR4: MR3[7] + * PSU_DDRC_DBICTL_WR_DBI_EN 0x0 + + * DM enable signal in DDRC. - 0 - DM is disabled. - 1 - DM is enabled. Thi + * s signal must be set the same logical value as DRAM's mode register. - D + * DR4: Set this to same value as MR5 bit A10. When x4 devices are used, th + * is signal must be set to 0. - LPDDR4: Set this to inverted value of MR13 + * [5] which is opposite polarity from this signal + * PSU_DDRC_DBICTL_DM_EN 0x1 + + * DM/DBI Control Register + * (OFFSET, MASK, VALUE) (0XFD0701C0, 0x00000007U ,0x00000001U) + */ + PSU_Mask_Write(DDRC_DBICTL_OFFSET, 0x00000007U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : ADDRMAP0 @ 0XFD070200 + + * Selects the HIF address bit used as rank address bit 0. Valid Range: 0 t + * o 27, and 31 Internal Base: 6 The selected HIF address bit is determined + * by adding the internal base to the value of this field. If set to 31, r + * ank address bit 0 is set to 0. + * PSU_DDRC_ADDRMAP0_ADDRMAP_CS_BIT0 0x1f + + * Address Map Register 0 + * (OFFSET, MASK, VALUE) (0XFD070200, 0x0000001FU ,0x0000001FU) + */ + PSU_Mask_Write(DDRC_ADDRMAP0_OFFSET, 0x0000001FU, 0x0000001FU); +/*##################################################################### */ + + /* + * Register : ADDRMAP1 @ 0XFD070204 + + * Selects the HIF address bit used as bank address bit 2. Valid Range: 0 t + * o 29 and 31 Internal Base: 4 The selected HIF address bit is determined + * by adding the internal base to the value of this field. If set to 31, ba + * nk address bit 2 is set to 0. + * PSU_DDRC_ADDRMAP1_ADDRMAP_BANK_B2 0x1f + + * Selects the HIF address bits used as bank address bit 1. Valid Range: 0 + * to 30 Internal Base: 3 The selected HIF address bit for each of the bank + * address bits is determined by adding the internal base to the value of + * this field. + * PSU_DDRC_ADDRMAP1_ADDRMAP_BANK_B1 0xa + + * Selects the HIF address bits used as bank address bit 0. Valid Range: 0 + * to 30 Internal Base: 2 The selected HIF address bit for each of the bank + * address bits is determined by adding the internal base to the value of + * this field. + * PSU_DDRC_ADDRMAP1_ADDRMAP_BANK_B0 0xa + + * Address Map Register 1 + * (OFFSET, MASK, VALUE) (0XFD070204, 0x001F1F1FU ,0x001F0A0AU) + */ + PSU_Mask_Write(DDRC_ADDRMAP1_OFFSET, 0x001F1F1FU, 0x001F0A0AU); +/*##################################################################### */ + + /* + * Register : ADDRMAP2 @ 0XFD070208 + + * - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 5. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 6. - Quarter bus width mode: Selects the HIF address bit + * used as column address bit 7 . Valid Range: 0 to 7, and 15 Internal Base + * : 5 The selected HIF address bit is determined by adding the internal ba + * se to the value of this field. If set to 15, this column address bit is + * set to 0. + * PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B5 0x0 + + * - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 4. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 5. - Quarter bus width mode: Selects the HIF address bit + * used as column address bit 6. Valid Range: 0 to 7, and 15 Internal Base: + * 4 The selected HIF address bit is determined by adding the internal bas + * e to the value of this field. If set to 15, this column address bit is s + * et to 0. + * PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B4 0x0 + + * - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 3. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 4. - Quarter bus width mode: Selects the HIF address bit + * used as column address bit 5. Valid Range: 0 to 7 Internal Base: 3 The s + * elected HIF address bit is determined by adding the internal base to the + * value of this field. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=1 + * 6, it is required to program this to 0, hence register does not exist in + * this case. + * PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B3 0x0 + + * - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 2. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 3. - Quarter bus width mode: Selects the HIF address bit + * used as column address bit 4. Valid Range: 0 to 7 Internal Base: 2 The s + * elected HIF address bit is determined by adding the internal base to the + * value of this field. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=8 + * or 16, it is required to program this to 0. + * PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B2 0x0 + + * Address Map Register 2 + * (OFFSET, MASK, VALUE) (0XFD070208, 0x0F0F0F0FU ,0x00000000U) + */ + PSU_Mask_Write(DDRC_ADDRMAP2_OFFSET, 0x0F0F0F0FU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ADDRMAP3 @ 0XFD07020C + + * - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 9. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 11 (10 in LPDDR2/LPDDR3 mode). - Quarter bus width mode: + * Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/ + * LPDDR3 mode). Valid Range: 0 to 7, and 15 Internal Base: 9 The selected + * HIF address bit is determined by adding the internal base to the value o + * f this field. If set to 15, this column address bit is set to 0. Note: P + * er JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved fo + * r indicating auto-precharge, and hence no source address bit can be mapp + * ed to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit + * for auto-precharge in the CA bus and hence column bit 10 is used. + * PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B9 0x0 + + * - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 8. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 9. - Quarter bus width mode: Selects the HIF address bit + * used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). Valid Range: 0 + * to 7, and 15 Internal Base: 8 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specifi + * cation, column address bit 10 is reserved for indicating auto-precharge, + * and hence no source address bit can be mapped to column address bit 10. + * In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA + * bus and hence column bit 10 is used. + * PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B8 0x0 + + * - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 7. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 8. - Quarter bus width mode: Selects the HIF address bit + * used as column address bit 9. Valid Range: 0 to 7, and 15 Internal Base: + * 7 The selected HIF address bit is determined by adding the internal bas + * e to the value of this field. If set to 15, this column address bit is s + * et to 0. + * PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B7 0x0 + + * - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 6. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 7. - Quarter bus width mode: Selects the HIF address bit + * used as column address bit 8. Valid Range: 0 to 7, and 15 Internal Base: + * 6 The selected HIF address bit is determined by adding the internal bas + * e to the value of this field. If set to 15, this column address bit is s + * et to 0. + * PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B6 0x0 + + * Address Map Register 3 + * (OFFSET, MASK, VALUE) (0XFD07020C, 0x0F0F0F0FU ,0x00000000U) + */ + PSU_Mask_Write(DDRC_ADDRMAP3_OFFSET, 0x0F0F0F0FU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ADDRMAP4 @ 0XFD070210 + + * - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 13 (11 in LPDDR2/LPDDR3 mode). - Half bus width mode: Unused. To m + * ake it unused, this should be tied to 4'hF. - Quarter bus width mode: Un + * used. To make it unused, this must be tied to 4'hF. Valid Range: 0 to 7, + * and 15 Internal Base: 11 The selected HIF address bit is determined by + * adding the internal base to the value of this field. If set to 15, this + * column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specificatio + * n, column address bit 10 is reserved for indicating auto-precharge, and + * hence no source address bit can be mapped to column address bit 10. In L + * PDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus + * and hence column bit 10 is used. + * PSU_DDRC_ADDRMAP4_ADDRMAP_COL_B11 0xf + + * - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 11 (10 in LPDDR2/LPDDR3 mode). - Half bus width mode: Selects the + * HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode) + * . - Quarter bus width mode: UNUSED. To make it unused, this must be tied + * to 4'hF. Valid Range: 0 to 7, and 15 Internal Base: 10 The selected HIF + * address bit is determined by adding the internal base to the value of t + * his field. If set to 15, this column address bit is set to 0. Note: Per + * JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for i + * ndicating auto-precharge, and hence no source address bit can be mapped + * to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for + * auto-precharge in the CA bus and hence column bit 10 is used. + * PSU_DDRC_ADDRMAP4_ADDRMAP_COL_B10 0xf + + * Address Map Register 4 + * (OFFSET, MASK, VALUE) (0XFD070210, 0x00000F0FU ,0x00000F0FU) + */ + PSU_Mask_Write(DDRC_ADDRMAP4_OFFSET, 0x00000F0FU, 0x00000F0FU); +/*##################################################################### */ + + /* + * Register : ADDRMAP5 @ 0XFD070214 + + * Selects the HIF address bit used as row address bit 11. Valid Range: 0 t + * o 11, and 15 Internal Base: 17 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * row address bit 11 is set to 0. + * PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B11 0x8 + + * Selects the HIF address bits used as row address bits 2 to 10. Valid Ran + * ge: 0 to 11, and 15 Internal Base: 8 (for row address bit 2), 9 (for row + * address bit 3), 10 (for row address bit 4) etc increasing to 16 (for ro + * w address bit 10) The selected HIF address bit for each of the row addre + * ss bits is determined by adding the internal base to the value of this f + * ield. When value 15 is used the values of row address bits 2 to 10 are d + * efined by registers ADDRMAP9, ADDRMAP10, ADDRMAP11. + * PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10 0xf + + * Selects the HIF address bits used as row address bit 1. Valid Range: 0 t + * o 11 Internal Base: 7 The selected HIF address bit for each of the row a + * ddress bits is determined by adding the internal base to the value of th + * is field. + * PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B1 0x8 + + * Selects the HIF address bits used as row address bit 0. Valid Range: 0 t + * o 11 Internal Base: 6 The selected HIF address bit for each of the row a + * ddress bits is determined by adding the internal base to the value of th + * is field. + * PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B0 0x8 + + * Address Map Register 5 + * (OFFSET, MASK, VALUE) (0XFD070214, 0x0F0F0F0FU ,0x080F0808U) + */ + PSU_Mask_Write(DDRC_ADDRMAP5_OFFSET, 0x0F0F0F0FU, 0x080F0808U); +/*##################################################################### */ + + /* + * Register : ADDRMAP6 @ 0XFD070218 + + * Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use. - 1 + * - LPDDR3 SDRAM 6Gb/12Gb device in use. Every address having row[14:13]= + * =2'b11 is considered as invalid - 0 - non-LPDDR3 6Gb/12Gb device in use. + * All addresses are valid Present only in designs configured to support L + * PDDR3. + * PSU_DDRC_ADDRMAP6_LPDDR3_6GB_12GB 0x0 + + * Selects the HIF address bit used as row address bit 15. Valid Range: 0 t + * o 11, and 15 Internal Base: 21 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * row address bit 15 is set to 0. + * PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B15 0xf + + * Selects the HIF address bit used as row address bit 14. Valid Range: 0 t + * o 11, and 15 Internal Base: 20 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * row address bit 14 is set to 0. + * PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B14 0x8 + + * Selects the HIF address bit used as row address bit 13. Valid Range: 0 t + * o 11, and 15 Internal Base: 19 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * row address bit 13 is set to 0. + * PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B13 0x8 + + * Selects the HIF address bit used as row address bit 12. Valid Range: 0 t + * o 11, and 15 Internal Base: 18 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * row address bit 12 is set to 0. + * PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B12 0x8 + + * Address Map Register 6 + * (OFFSET, MASK, VALUE) (0XFD070218, 0x8F0F0F0FU ,0x0F080808U) + */ + PSU_Mask_Write(DDRC_ADDRMAP6_OFFSET, 0x8F0F0F0FU, 0x0F080808U); +/*##################################################################### */ + + /* + * Register : ADDRMAP7 @ 0XFD07021C + + * Selects the HIF address bit used as row address bit 17. Valid Range: 0 t + * o 10, and 15 Internal Base: 23 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * row address bit 17 is set to 0. + * PSU_DDRC_ADDRMAP7_ADDRMAP_ROW_B17 0xf + + * Selects the HIF address bit used as row address bit 16. Valid Range: 0 t + * o 11, and 15 Internal Base: 22 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * row address bit 16 is set to 0. + * PSU_DDRC_ADDRMAP7_ADDRMAP_ROW_B16 0xf + + * Address Map Register 7 + * (OFFSET, MASK, VALUE) (0XFD07021C, 0x00000F0FU ,0x00000F0FU) + */ + PSU_Mask_Write(DDRC_ADDRMAP7_OFFSET, 0x00000F0FU, 0x00000F0FU); +/*##################################################################### */ + + /* + * Register : ADDRMAP8 @ 0XFD070220 + + * Selects the HIF address bits used as bank group address bit 1. Valid Ran + * ge: 0 to 30, and 31 Internal Base: 3 The selected HIF address bit for ea + * ch of the bank group address bits is determined by adding the internal b + * ase to the value of this field. If set to 31, bank group address bit 1 i + * s set to 0. + * PSU_DDRC_ADDRMAP8_ADDRMAP_BG_B1 0x8 + + * Selects the HIF address bits used as bank group address bit 0. Valid Ran + * ge: 0 to 30 Internal Base: 2 The selected HIF address bit for each of th + * e bank group address bits is determined by adding the internal base to t + * he value of this field. + * PSU_DDRC_ADDRMAP8_ADDRMAP_BG_B0 0x8 + + * Address Map Register 8 + * (OFFSET, MASK, VALUE) (0XFD070220, 0x00001F1FU ,0x00000808U) + */ + PSU_Mask_Write(DDRC_ADDRMAP8_OFFSET, 0x00001F1FU, 0x00000808U); +/*##################################################################### */ + + /* + * Register : ADDRMAP9 @ 0XFD070224 + + * Selects the HIF address bits used as row address bit 5. Valid Range: 0 t + * o 11 Internal Base: 11 The selected HIF address bit for each of the row + * address bits is determined by adding the internal base to the value of t + * his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + * _10 is set to value 15. + * PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B5 0x8 + + * Selects the HIF address bits used as row address bit 4. Valid Range: 0 t + * o 11 Internal Base: 10 The selected HIF address bit for each of the row + * address bits is determined by adding the internal base to the value of t + * his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + * _10 is set to value 15. + * PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B4 0x8 + + * Selects the HIF address bits used as row address bit 3. Valid Range: 0 t + * o 11 Internal Base: 9 The selected HIF address bit for each of the row a + * ddress bits is determined by adding the internal base to the value of th + * is field. This register field is used only when ADDRMAP5.addrmap_row_b2_ + * 10 is set to value 15. + * PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B3 0x8 + + * Selects the HIF address bits used as row address bit 2. Valid Range: 0 t + * o 11 Internal Base: 8 The selected HIF address bit for each of the row a + * ddress bits is determined by adding the internal base to the value of th + * is field. This register field is used only when ADDRMAP5.addrmap_row_b2_ + * 10 is set to value 15. + * PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B2 0x8 + + * Address Map Register 9 + * (OFFSET, MASK, VALUE) (0XFD070224, 0x0F0F0F0FU ,0x08080808U) + */ + PSU_Mask_Write(DDRC_ADDRMAP9_OFFSET, 0x0F0F0F0FU, 0x08080808U); +/*##################################################################### */ + + /* + * Register : ADDRMAP10 @ 0XFD070228 + + * Selects the HIF address bits used as row address bit 9. Valid Range: 0 t + * o 11 Internal Base: 15 The selected HIF address bit for each of the row + * address bits is determined by adding the internal base to the value of t + * his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + * _10 is set to value 15. + * PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B9 0x8 + + * Selects the HIF address bits used as row address bit 8. Valid Range: 0 t + * o 11 Internal Base: 14 The selected HIF address bit for each of the row + * address bits is determined by adding the internal base to the value of t + * his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + * _10 is set to value 15. + * PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B8 0x8 + + * Selects the HIF address bits used as row address bit 7. Valid Range: 0 t + * o 11 Internal Base: 13 The selected HIF address bit for each of the row + * address bits is determined by adding the internal base to the value of t + * his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + * _10 is set to value 15. + * PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B7 0x8 + + * Selects the HIF address bits used as row address bit 6. Valid Range: 0 t + * o 11 Internal Base: 12 The selected HIF address bit for each of the row + * address bits is determined by adding the internal base to the value of t + * his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + * _10 is set to value 15. + * PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B6 0x8 + + * Address Map Register 10 + * (OFFSET, MASK, VALUE) (0XFD070228, 0x0F0F0F0FU ,0x08080808U) + */ + PSU_Mask_Write(DDRC_ADDRMAP10_OFFSET, 0x0F0F0F0FU, 0x08080808U); +/*##################################################################### */ + + /* + * Register : ADDRMAP11 @ 0XFD07022C + + * Selects the HIF address bits used as row address bit 10. Valid Range: 0 + * to 11 Internal Base: 16 The selected HIF address bit for each of the row + * address bits is determined by adding the internal base to the value of + * this field. This register field is used only when ADDRMAP5.addrmap_row_b + * 2_10 is set to value 15. + * PSU_DDRC_ADDRMAP11_ADDRMAP_ROW_B10 0x8 + + * Address Map Register 11 + * (OFFSET, MASK, VALUE) (0XFD07022C, 0x0000000FU ,0x00000008U) + */ + PSU_Mask_Write(DDRC_ADDRMAP11_OFFSET, 0x0000000FU, 0x00000008U); +/*##################################################################### */ + + /* + * Register : ODTCFG @ 0XFD070240 + + * Cycles to hold ODT for a write command. The minimum supported value is 2 + * . Recommended values: DDR2: - BL8: 0x5 (DDR2-400/533/667), 0x6 (DDR2-800 + * ), 0x7 (DDR2-1066) - BL4: 0x3 (DDR2-400/533/667), 0x4 (DDR2-800), 0x5 (D + * DR2-1066) DDR3: - BL8: 0x6 DDR4: - BL8: 5 + WR_PREAMBLE + CRC_MODE WR_PR + * EAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) CRC_MODE = 0 ( + * not CRC mode), 1 (CRC mode) LPDDR3: - BL8: 7 + RU(tODTon(max)/tCK) + * PSU_DDRC_ODTCFG_WR_ODT_HOLD 0x6 + + * The delay, in clock cycles, from issuing a write command to setting ODT + * values associated with that command. ODT setting must remain constant fo + * r the entire time that DQS is driven by the uMCTL2. Recommended values: + * DDR2: - CWL + AL - 3 (DDR2-400/533/667), CWL + AL - 4 (DDR2-800), CWL + + * AL - 5 (DDR2-1066) If (CWL + AL - 3 < 0), uMCTL2 does not support ODT fo + * r write operation. DDR3: - 0x0 DDR4: - DFITMG1.dfi_t_cmd_lat (to adjust + * for CAL mode) LPDDR3: - WL - 1 - RU(tODTon(max)/tCK)) + * PSU_DDRC_ODTCFG_WR_ODT_DELAY 0x0 + + * Cycles to hold ODT for a read command. The minimum supported value is 2. + * Recommended values: DDR2: - BL8: 0x6 (not DDR2-1066), 0x7 (DDR2-1066) - + * BL4: 0x4 (not DDR2-1066), 0x5 (DDR2-1066) DDR3: - BL8 - 0x6 DDR4: - BL8 + * : 5 + RD_PREAMBLE RD_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write p + * reamble) LPDDR3: - BL8: 5 + RU(tDQSCK(max)/tCK) - RD(tDQSCK(min)/tCK) + + * RU(tODTon(max)/tCK) + * PSU_DDRC_ODTCFG_RD_ODT_HOLD 0x6 + + * The delay, in clock cycles, from issuing a read command to setting ODT v + * alues associated with that command. ODT setting must remain constant for + * the entire time that DQS is driven by the uMCTL2. Recommended values: D + * DR2: - CL + AL - 4 (not DDR2-1066), CL + AL - 5 (DDR2-1066) If (CL + AL + * - 4 < 0), uMCTL2 does not support ODT for read operation. DDR3: - CL - C + * WL DDR4: - CL - CWL - RD_PREAMBLE + WR_PREAMBLE + DFITMG1.dfi_t_cmd_lat + * (to adjust for CAL mode) WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK + * write preamble) RD_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write pre + * amble) If (CL - CWL - RD_PREAMBLE + WR_PREAMBLE) < 0, uMCTL2 does not su + * pport ODT for read operation. LPDDR3: - RL + RD(tDQSCK(min)/tCK) - 1 - R + * U(tODTon(max)/tCK) + * PSU_DDRC_ODTCFG_RD_ODT_DELAY 0x0 + + * ODT Configuration Register + * (OFFSET, MASK, VALUE) (0XFD070240, 0x0F1F0F7CU ,0x06000600U) + */ + PSU_Mask_Write(DDRC_ODTCFG_OFFSET, 0x0F1F0F7CU, 0x06000600U); +/*##################################################################### */ + + /* + * Register : ODTMAP @ 0XFD070244 + + * Indicates which remote ODTs must be turned on during a read from rank 1. + * Each rank has a remote ODT (in the SDRAM) which can be turned on by set + * ting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 i + * s controlled by bit next to the LSB, etc. For each rank, set its bit to + * 1 to enable its ODT. Present only in configurations that have 2 or more + * ranks + * PSU_DDRC_ODTMAP_RANK1_RD_ODT 0x0 + + * Indicates which remote ODTs must be turned on during a write to rank 1. + * Each rank has a remote ODT (in the SDRAM) which can be turned on by sett + * ing the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is + * controlled by bit next to the LSB, etc. For each rank, set its bit to 1 + * to enable its ODT. Present only in configurations that have 2 or more r + * anks + * PSU_DDRC_ODTMAP_RANK1_WR_ODT 0x0 + + * Indicates which remote ODTs must be turned on during a read from rank 0. + * Each rank has a remote ODT (in the SDRAM) which can be turned on by set + * ting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 i + * s controlled by bit next to the LSB, etc. For each rank, set its bit to + * 1 to enable its ODT. + * PSU_DDRC_ODTMAP_RANK0_RD_ODT 0x0 + + * Indicates which remote ODTs must be turned on during a write to rank 0. + * Each rank has a remote ODT (in the SDRAM) which can be turned on by sett + * ing the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is + * controlled by bit next to the LSB, etc. For each rank, set its bit to 1 + * to enable its ODT. + * PSU_DDRC_ODTMAP_RANK0_WR_ODT 0x1 + + * ODT/Rank Map Register + * (OFFSET, MASK, VALUE) (0XFD070244, 0x00003333U ,0x00000001U) + */ + PSU_Mask_Write(DDRC_ODTMAP_OFFSET, 0x00003333U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : SCHED @ 0XFD070250 + + * When the preferred transaction store is empty for these many clock cycle + * s, switch to the alternate transaction store if it is non-empty. The rea + * d transaction store (both high and low priority) is the default preferre + * d transaction store and the write transaction store is the alternative s + * tore. When prefer write over read is set this is reversed. 0x0 is a lega + * l value for this register. When set to 0x0, the transaction store switch + * ing will happen immediately when the switching conditions become true. F + * OR PERFORMANCE ONLY + * PSU_DDRC_SCHED_RDWR_IDLE_GAP 0x1 + + * UNUSED + * PSU_DDRC_SCHED_GO2CRITICAL_HYSTERESIS 0x0 + + * Number of entries in the low priority transaction store is this value + + * 1. (MEMC_NO_OF_ENTRY - (SCHED.lpr_num_entries + 1)) is the number of ent + * ries available for the high priority transaction store. Setting this to + * maximum value allocates all entries to low priority transaction store. S + * etting this to 0 allocates 1 entry to low priority transaction store and + * the rest to high priority transaction store. Note: In ECC configuration + * s, the numbers of write and low priority read credits issued is one less + * than in the non-ECC case. One entry each is reserved in the write and l + * ow-priority read CAMs for storing the RMW requests arising out of single + * bit error correction RMW operation. + * PSU_DDRC_SCHED_LPR_NUM_ENTRIES 0x20 + + * If true, bank is kept open only while there are page hit transactions av + * ailable in the CAM to that bank. The last read or write command in the C + * AM with a bank and page hit will be executed with auto-precharge if SCHE + * D1.pageclose_timer=0. Even if this register set to 1 and SCHED1.pageclos + * e_timer is set to 0, explicit precharge (and not auto-precharge) may be + * issued in some cases where there is a mode switch between Write and Read + * or between LPR and HPR. The Read and Write commands that are executed a + * s part of the ECC scrub requests are also executed without auto-precharg + * e. If false, the bank remains open until there is a need to close it (to + * open a different page, or for page timeout or refresh timeout) - also k + * nown as open page policy. The open page policy can be overridden by sett + * ing the per-command-autopre bit on the HIF interface (hif_cmd_autopre). + * The pageclose feature provids a midway between Open and Close page polic + * ies. FOR PERFORMANCE ONLY. + * PSU_DDRC_SCHED_PAGECLOSE 0x0 + + * If set then the bank selector prefers writes over reads. FOR DEBUG ONLY. + * PSU_DDRC_SCHED_PREFER_WRITE 0x0 + + * Active low signal. When asserted ('0'), all incoming transactions are fo + * rced to low priority. This implies that all High Priority Read (HPR) and + * Variable Priority Read commands (VPR) will be treated as Low Priority R + * ead (LPR) commands. On the write side, all Variable Priority Write (VPW) + * commands will be treated as Normal Priority Write (NPW) commands. Forci + * ng the incoming transactions to low priority implicitly turns off Bypass + * path for read commands. FOR PERFORMANCE ONLY. + * PSU_DDRC_SCHED_FORCE_LOW_PRI_N 0x1 + + * Scheduler Control Register + * (OFFSET, MASK, VALUE) (0XFD070250, 0x7FFF3F07U ,0x01002001U) + */ + PSU_Mask_Write(DDRC_SCHED_OFFSET, 0x7FFF3F07U, 0x01002001U); +/*##################################################################### */ + + /* + * Register : PERFLPR1 @ 0XFD070264 + + * Number of transactions that are serviced once the LPR queue goes critica + * l is the smaller of: - (a) This number - (b) Number of transactions avai + * lable. Unit: Transaction. FOR PERFORMANCE ONLY. + * PSU_DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH 0x8 + + * Number of clocks that the LPR queue can be starved before it goes critic + * al. The minimum valid functional value for this register is 0x1. Program + * ming it to 0x0 will disable the starvation functionality; during normal + * operation, this function should not be disabled as it will cause excessi + * ve latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY. + * PSU_DDRC_PERFLPR1_LPR_MAX_STARVE 0x40 + + * Low Priority Read CAM Register 1 + * (OFFSET, MASK, VALUE) (0XFD070264, 0xFF00FFFFU ,0x08000040U) + */ + PSU_Mask_Write(DDRC_PERFLPR1_OFFSET, 0xFF00FFFFU, 0x08000040U); +/*##################################################################### */ + + /* + * Register : PERFWR1 @ 0XFD07026C + + * Number of transactions that are serviced once the WR queue goes critical + * is the smaller of: - (a) This number - (b) Number of transactions avail + * able. Unit: Transaction. FOR PERFORMANCE ONLY. + * PSU_DDRC_PERFWR1_W_XACT_RUN_LENGTH 0x8 + + * Number of clocks that the WR queue can be starved before it goes critica + * l. The minimum valid functional value for this register is 0x1. Programm + * ing it to 0x0 will disable the starvation functionality; during normal o + * peration, this function should not be disabled as it will cause excessiv + * e latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY. + * PSU_DDRC_PERFWR1_W_MAX_STARVE 0x40 + + * Write CAM Register 1 + * (OFFSET, MASK, VALUE) (0XFD07026C, 0xFF00FFFFU ,0x08000040U) + */ + PSU_Mask_Write(DDRC_PERFWR1_OFFSET, 0xFF00FFFFU, 0x08000040U); +/*##################################################################### */ + + /* + * Register : DQMAP0 @ 0XFD070280 + + * DQ nibble map for DQ bits [12-15] Present only in designs configured to + * support DDR4. + * PSU_DDRC_DQMAP0_DQ_NIBBLE_MAP_12_15 0x0 + + * DQ nibble map for DQ bits [8-11] Present only in designs configured to s + * upport DDR4. + * PSU_DDRC_DQMAP0_DQ_NIBBLE_MAP_8_11 0x0 + + * DQ nibble map for DQ bits [4-7] Present only in designs configured to su + * pport DDR4. + * PSU_DDRC_DQMAP0_DQ_NIBBLE_MAP_4_7 0x0 + + * DQ nibble map for DQ bits [0-3] Present only in designs configured to su + * pport DDR4. + * PSU_DDRC_DQMAP0_DQ_NIBBLE_MAP_0_3 0x0 + + * DQ Map Register 0 + * (OFFSET, MASK, VALUE) (0XFD070280, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDRC_DQMAP0_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : DQMAP1 @ 0XFD070284 + + * DQ nibble map for DQ bits [28-31] Present only in designs configured to + * support DDR4. + * PSU_DDRC_DQMAP1_DQ_NIBBLE_MAP_28_31 0x0 + + * DQ nibble map for DQ bits [24-27] Present only in designs configured to + * support DDR4. + * PSU_DDRC_DQMAP1_DQ_NIBBLE_MAP_24_27 0x0 + + * DQ nibble map for DQ bits [20-23] Present only in designs configured to + * support DDR4. + * PSU_DDRC_DQMAP1_DQ_NIBBLE_MAP_20_23 0x0 + + * DQ nibble map for DQ bits [16-19] Present only in designs configured to + * support DDR4. + * PSU_DDRC_DQMAP1_DQ_NIBBLE_MAP_16_19 0x0 + + * DQ Map Register 1 + * (OFFSET, MASK, VALUE) (0XFD070284, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDRC_DQMAP1_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : DQMAP2 @ 0XFD070288 + + * DQ nibble map for DQ bits [44-47] Present only in designs configured to + * support DDR4. + * PSU_DDRC_DQMAP2_DQ_NIBBLE_MAP_44_47 0x0 + + * DQ nibble map for DQ bits [40-43] Present only in designs configured to + * support DDR4. + * PSU_DDRC_DQMAP2_DQ_NIBBLE_MAP_40_43 0x0 + + * DQ nibble map for DQ bits [36-39] Present only in designs configured to + * support DDR4. + * PSU_DDRC_DQMAP2_DQ_NIBBLE_MAP_36_39 0x0 + + * DQ nibble map for DQ bits [32-35] Present only in designs configured to + * support DDR4. + * PSU_DDRC_DQMAP2_DQ_NIBBLE_MAP_32_35 0x0 + + * DQ Map Register 2 + * (OFFSET, MASK, VALUE) (0XFD070288, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDRC_DQMAP2_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : DQMAP3 @ 0XFD07028C + + * DQ nibble map for DQ bits [60-63] Present only in designs configured to + * support DDR4. + * PSU_DDRC_DQMAP3_DQ_NIBBLE_MAP_60_63 0x0 + + * DQ nibble map for DQ bits [56-59] Present only in designs configured to + * support DDR4. + * PSU_DDRC_DQMAP3_DQ_NIBBLE_MAP_56_59 0x0 + + * DQ nibble map for DQ bits [52-55] Present only in designs configured to + * support DDR4. + * PSU_DDRC_DQMAP3_DQ_NIBBLE_MAP_52_55 0x0 + + * DQ nibble map for DQ bits [48-51] Present only in designs configured to + * support DDR4. + * PSU_DDRC_DQMAP3_DQ_NIBBLE_MAP_48_51 0x0 + + * DQ Map Register 3 + * (OFFSET, MASK, VALUE) (0XFD07028C, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDRC_DQMAP3_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : DQMAP4 @ 0XFD070290 + + * DQ nibble map for DIMM ECC check bits [4-7] Present only in designs conf + * igured to support DDR4. + * PSU_DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_4_7 0x0 + + * DQ nibble map for DIMM ECC check bits [0-3] Present only in designs conf + * igured to support DDR4. + * PSU_DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_0_3 0x0 + + * DQ Map Register 4 + * (OFFSET, MASK, VALUE) (0XFD070290, 0x0000FFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDRC_DQMAP4_OFFSET, 0x0000FFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : DQMAP5 @ 0XFD070294 + + * All even ranks have the same DQ mapping controled by DQMAP0-4 register a + * s rank 0. This register provides DQ swap function for all odd ranks to s + * upport CRC feature. rank based DQ swapping is: swap bit 0 with 1, swap b + * it 2 with 3, swap bit 4 with 5 and swap bit 6 with 7. 1: Disable rank ba + * sed DQ swapping 0: Enable rank based DQ swapping Present only in designs + * configured to support DDR4. + * PSU_DDRC_DQMAP5_DIS_DQ_RANK_SWAP 0x1 + + * DQ Map Register 5 + * (OFFSET, MASK, VALUE) (0XFD070294, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(DDRC_DQMAP5_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : DBG0 @ 0XFD070300 + + * When this is set to '0', auto-precharge is disabled for the flushed comm + * and in a collision case. Collision cases are write followed by read to s + * ame address, read followed by write to same address, or write followed b + * y write to same address with DBG0.dis_wc bit = 1 (where same address com + * parisons exclude the two address bits representing critical word). FOR D + * EBUG ONLY. + * PSU_DDRC_DBG0_DIS_COLLISION_PAGE_OPT 0x0 + + * When 1, disable write combine. FOR DEBUG ONLY + * PSU_DDRC_DBG0_DIS_WC 0x0 + + * Debug Register 0 + * (OFFSET, MASK, VALUE) (0XFD070300, 0x00000011U ,0x00000000U) + */ + PSU_Mask_Write(DDRC_DBG0_OFFSET, 0x00000011U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : DBGCMD @ 0XFD07030C + + * Setting this register bit to 1 allows refresh and ZQCS commands to be tr + * iggered from hardware via the IOs ext_*. If set to 1, the fields DBGCMD. + * zq_calib_short and DBGCMD.rank*_refresh have no function, and are ignore + * d by the uMCTL2 logic. Setting this register bit to 0 allows refresh and + * ZQCS to be triggered from software, via the fields DBGCMD.zq_calib_shor + * t and DBGCMD.rank*_refresh. If set to 0, the hardware pins ext_* have no + * function, and are ignored by the uMCTL2 logic. This register is static, + * and may only be changed when the DDRC reset signal, core_ddrc_rstn, is + * asserted (0). + * PSU_DDRC_DBGCMD_HW_REF_ZQ_EN 0x0 + + * Setting this register bit to 1 indicates to the uMCTL2 to issue a dfi_ct + * rlupd_req to the PHY. When this request is stored in the uMCTL2, the bit + * is automatically cleared. This operation must only be performed when DF + * IUPD0.dis_auto_ctrlupd=1. + * PSU_DDRC_DBGCMD_CTRLUPD 0x0 + + * Setting this register bit to 1 indicates to the uMCTL2 to issue a ZQCS ( + * ZQ calibration short)/MPC(ZQ calibration) command to the SDRAM. When thi + * s request is stored in the uMCTL2, the bit is automatically cleared. Thi + * s operation can be performed only when ZQCTL0.dis_auto_zq=1. It is recom + * mended NOT to set this register bit if in Init operating mode. This regi + * ster bit is ignored when in Self-Refresh(except LPDDR4) and SR-Powerdown + * (LPDDR4) and Deep power-down operating modes and Maximum Power Saving Mo + * de. + * PSU_DDRC_DBGCMD_ZQ_CALIB_SHORT 0x0 + + * Setting this register bit to 1 indicates to the uMCTL2 to issue a refres + * h to rank 1. Writing to this bit causes DBGSTAT.rank1_refresh_busy to be + * set. When DBGSTAT.rank1_refresh_busy is cleared, the command has been s + * tored in uMCTL2. This operation can be performed only when RFSHCTL3.dis_ + * auto_refresh=1. It is recommended NOT to set this register bit if in Ini + * t or Deep power-down operating modes or Maximum Power Saving Mode. + * PSU_DDRC_DBGCMD_RANK1_REFRESH 0x0 + + * Setting this register bit to 1 indicates to the uMCTL2 to issue a refres + * h to rank 0. Writing to this bit causes DBGSTAT.rank0_refresh_busy to be + * set. When DBGSTAT.rank0_refresh_busy is cleared, the command has been s + * tored in uMCTL2. This operation can be performed only when RFSHCTL3.dis_ + * auto_refresh=1. It is recommended NOT to set this register bit if in Ini + * t or Deep power-down operating modes or Maximum Power Saving Mode. + * PSU_DDRC_DBGCMD_RANK0_REFRESH 0x0 + + * Command Debug Register + * (OFFSET, MASK, VALUE) (0XFD07030C, 0x80000033U ,0x00000000U) + */ + PSU_Mask_Write(DDRC_DBGCMD_OFFSET, 0x80000033U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : SWCTL @ 0XFD070320 + + * Enable quasi-dynamic register programming outside reset. Program registe + * r to 0 to enable quasi-dynamic programming. Set back register to 1 once + * programming is done. + * PSU_DDRC_SWCTL_SW_DONE 0x0 + + * Software register programming control enable + * (OFFSET, MASK, VALUE) (0XFD070320, 0x00000001U ,0x00000000U) + */ + PSU_Mask_Write(DDRC_SWCTL_OFFSET, 0x00000001U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : PCCFG @ 0XFD070400 + + * Burst length expansion mode. By default (i.e. bl_exp_mode==0) XPI expand + * s every AXI burst into multiple HIF commands, using the memory burst len + * gth as a unit. If set to 1, then XPI will use half of the memory burst l + * ength as a unit. This applies to both reads and writes. When MSTR.data_b + * us_width==00, setting bl_exp_mode to 1 has no effect. This can be used i + * n cases where Partial Writes is enabled (UMCTL2_PARTIAL_WR=1) and DBG0.d + * is_wc=1, in order to avoid or minimize t_ccd_l penalty in DDR4 and t_ccd + * _mw penalty in LPDDR4. Note that if DBICTL.reg_ddrc_dm_en=0, functionali + * ty is not supported in the following cases: - UMCTL2_PARTIAL_WR=0 - UMCT + * L2_PARTIAL_WR=1, MSTR.reg_ddrc_data_bus_width=01, MEMC_BURST_LENGTH=8 an + * d MSTR.reg_ddrc_burst_rdwr=1000 (LPDDR4 only) - UMCTL2_PARTIAL_WR=1, MST + * R.reg_ddrc_data_bus_width=01, MEMC_BURST_LENGTH=4 and MSTR.reg_ddrc_burs + * t_rdwr=0100 (DDR4 only), with either MSTR.reg_ddrc_burstchop=0 or CRCPAR + * CTL1.reg_ddrc_crc_enable=1 Functionality is also not supported if Shared + * -AC is enabled + * PSU_DDRC_PCCFG_BL_EXP_MODE 0x0 + + * Page match four limit. If set to 1, limits the number of consecutive sam + * e page DDRC transactions that can be granted by the Port Arbiter to four + * when Page Match feature is enabled. If set to 0, there is no limit impo + * sed on number of consecutive same page DDRC transactions. + * PSU_DDRC_PCCFG_PAGEMATCH_LIMIT 0x0 + + * If set to 1 (enabled), sets co_gs_go2critical_wr and co_gs_go2critical_l + * pr/co_gs_go2critical_hpr signals going to DDRC based on urgent input (aw + * urgent, arurgent) coming from AXI master. If set to 0 (disabled), co_gs_ + * go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals a + * t DDRC are driven to 1b'0. + * PSU_DDRC_PCCFG_GO2CRITICAL_EN 0x1 + + * Port Common Configuration Register + * (OFFSET, MASK, VALUE) (0XFD070400, 0x00000111U ,0x00000001U) + */ + PSU_Mask_Write(DDRC_PCCFG_OFFSET, 0x00000111U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : PCFGR_0 @ 0XFD070404 + + * If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. + * PSU_DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN 0x0 + + * If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + * bled and arurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + * urgent signal can be asserted anytime and as long as required which is i + * ndependent of address handshaking (it is not associated with any particu + * lar command). + * PSU_DDRC_PCFGR_0_RD_PORT_URGENT_EN 0x1 + + * If set to 1, enables aging function for the read channel of the port. + * PSU_DDRC_PCFGR_0_RD_PORT_AGING_EN 0x0 + + * Determines the initial load value of read aging counters. These counters + * will be parallel loaded after reset, or after each grant to the corresp + * onding port. The aging counters down-count every clock cycle where the p + * ort is requesting but not granted. The higher significant 5-bits of the + * read aging counter sets the priority of the read channel of a given port + * . Port's priority will increase as the higher significant 5-bits of the + * counter starts to decrease. When the aging counter becomes 0, the corres + * ponding port channel will have the highest priority level (timeout condi + * tion - Priority0). For multi-port configurations, the aging counters can + * not be used to set port priorities when external dynamic priority inputs + * (arqos) are enabled (timeout is still applicable). For single port conf + * igurations, the aging counters are only used when they timeout (become 0 + * ) to force read-write direction switching. In this case, external dynami + * c priority input, arqos (for reads only) can still be used to set the DD + * RC read priority (2 priority levels: low priority read - LPR, high prior + * ity read - HPR) on a command by command basis. Note: The two LSBs of thi + * s register field are tied internally to 2'b00. + * PSU_DDRC_PCFGR_0_RD_PORT_PRIORITY 0xf + + * Port n Configuration Read Register + * (OFFSET, MASK, VALUE) (0XFD070404, 0x000073FFU ,0x0000200FU) + */ + PSU_Mask_Write(DDRC_PCFGR_0_OFFSET, 0x000073FFU, 0x0000200FU); +/*##################################################################### */ + + /* + * Register : PCFGW_0 @ 0XFD070408 + + * If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. + * PSU_DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN 0x0 + + * If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + * bled and awurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + * serted anytime and as long as required which is independent of address h + * andshaking (it is not associated with any particular command). + * PSU_DDRC_PCFGW_0_WR_PORT_URGENT_EN 0x1 + + * If set to 1, enables aging function for the write channel of the port. + * PSU_DDRC_PCFGW_0_WR_PORT_AGING_EN 0x0 + + * Determines the initial load value of write aging counters. These counter + * s will be parallel loaded after reset, or after each grant to the corres + * ponding port. The aging counters down-count every clock cycle where the + * port is requesting but not granted. The higher significant 5-bits of the + * write aging counter sets the initial priority of the write channel of a + * given port. Port's priority will increase as the higher significant 5-b + * its of the counter starts to decrease. When the aging counter becomes 0, + * the corresponding port channel will have the highest priority level. Fo + * r multi-port configurations, the aging counters cannot be used to set po + * rt priorities when external dynamic priority inputs (awqos) are enabled + * (timeout is still applicable). For single port configurations, the aging + * counters are only used when they timeout (become 0) to force read-write + * direction switching. Note: The two LSBs of this register field are tied + * internally to 2'b00. + * PSU_DDRC_PCFGW_0_WR_PORT_PRIORITY 0xf + + * Port n Configuration Write Register + * (OFFSET, MASK, VALUE) (0XFD070408, 0x000073FFU ,0x0000200FU) + */ + PSU_Mask_Write(DDRC_PCFGW_0_OFFSET, 0x000073FFU, 0x0000200FU); +/*##################################################################### */ + + /* + * Register : PCTRL_0 @ 0XFD070490 + + * Enables port n. + * PSU_DDRC_PCTRL_0_PORT_EN 0x1 + + * Port n Control Register + * (OFFSET, MASK, VALUE) (0XFD070490, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(DDRC_PCTRL_0_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : PCFGQOS0_0 @ 0XFD070494 + + * This bitfield indicates the traffic class of region 1. Valid values are: + * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + * maps to the blue address queue. In this case, valid values are 0: LPR a + * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. + * PSU_DDRC_PCFGQOS0_0_RQOS_MAP_REGION1 0x2 + + * This bitfield indicates the traffic class of region 0. Valid values are: + * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + * maps to the blue address queue. In this case, valid values are: 0: LPR + * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. + * PSU_DDRC_PCFGQOS0_0_RQOS_MAP_REGION0 0x0 + + * Separation level1 indicating the end of region0 mapping; start of region + * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + * lues are used directly as port priorities, where the higher the value co + * rresponds to higher port priority. All of the map_level* registers must + * be set to distinct values. + * PSU_DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1 0xb + + * Port n Read QoS Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD070494, 0x0033000FU ,0x0020000BU) + */ + PSU_Mask_Write(DDRC_PCFGQOS0_0_OFFSET, 0x0033000FU, 0x0020000BU); +/*##################################################################### */ + + /* + * Register : PCFGQOS1_0 @ 0XFD070498 + + * Specifies the timeout value for transactions mapped to the red address q + * ueue. + * PSU_DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR 0x0 + + * Specifies the timeout value for transactions mapped to the blue address + * queue. + * PSU_DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB 0x0 + + * Port n Read QoS Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD070498, 0x07FF07FFU ,0x00000000U) + */ + PSU_Mask_Write(DDRC_PCFGQOS1_0_OFFSET, 0x07FF07FFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : PCFGR_1 @ 0XFD0704B4 + + * If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. + * PSU_DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN 0x0 + + * If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + * bled and arurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + * urgent signal can be asserted anytime and as long as required which is i + * ndependent of address handshaking (it is not associated with any particu + * lar command). + * PSU_DDRC_PCFGR_1_RD_PORT_URGENT_EN 0x1 + + * If set to 1, enables aging function for the read channel of the port. + * PSU_DDRC_PCFGR_1_RD_PORT_AGING_EN 0x0 + + * Determines the initial load value of read aging counters. These counters + * will be parallel loaded after reset, or after each grant to the corresp + * onding port. The aging counters down-count every clock cycle where the p + * ort is requesting but not granted. The higher significant 5-bits of the + * read aging counter sets the priority of the read channel of a given port + * . Port's priority will increase as the higher significant 5-bits of the + * counter starts to decrease. When the aging counter becomes 0, the corres + * ponding port channel will have the highest priority level (timeout condi + * tion - Priority0). For multi-port configurations, the aging counters can + * not be used to set port priorities when external dynamic priority inputs + * (arqos) are enabled (timeout is still applicable). For single port conf + * igurations, the aging counters are only used when they timeout (become 0 + * ) to force read-write direction switching. In this case, external dynami + * c priority input, arqos (for reads only) can still be used to set the DD + * RC read priority (2 priority levels: low priority read - LPR, high prior + * ity read - HPR) on a command by command basis. Note: The two LSBs of thi + * s register field are tied internally to 2'b00. + * PSU_DDRC_PCFGR_1_RD_PORT_PRIORITY 0xf + + * Port n Configuration Read Register + * (OFFSET, MASK, VALUE) (0XFD0704B4, 0x000073FFU ,0x0000200FU) + */ + PSU_Mask_Write(DDRC_PCFGR_1_OFFSET, 0x000073FFU, 0x0000200FU); +/*##################################################################### */ + + /* + * Register : PCFGW_1 @ 0XFD0704B8 + + * If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. + * PSU_DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN 0x0 + + * If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + * bled and awurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + * serted anytime and as long as required which is independent of address h + * andshaking (it is not associated with any particular command). + * PSU_DDRC_PCFGW_1_WR_PORT_URGENT_EN 0x1 + + * If set to 1, enables aging function for the write channel of the port. + * PSU_DDRC_PCFGW_1_WR_PORT_AGING_EN 0x0 + + * Determines the initial load value of write aging counters. These counter + * s will be parallel loaded after reset, or after each grant to the corres + * ponding port. The aging counters down-count every clock cycle where the + * port is requesting but not granted. The higher significant 5-bits of the + * write aging counter sets the initial priority of the write channel of a + * given port. Port's priority will increase as the higher significant 5-b + * its of the counter starts to decrease. When the aging counter becomes 0, + * the corresponding port channel will have the highest priority level. Fo + * r multi-port configurations, the aging counters cannot be used to set po + * rt priorities when external dynamic priority inputs (awqos) are enabled + * (timeout is still applicable). For single port configurations, the aging + * counters are only used when they timeout (become 0) to force read-write + * direction switching. Note: The two LSBs of this register field are tied + * internally to 2'b00. + * PSU_DDRC_PCFGW_1_WR_PORT_PRIORITY 0xf + + * Port n Configuration Write Register + * (OFFSET, MASK, VALUE) (0XFD0704B8, 0x000073FFU ,0x0000200FU) + */ + PSU_Mask_Write(DDRC_PCFGW_1_OFFSET, 0x000073FFU, 0x0000200FU); +/*##################################################################### */ + + /* + * Register : PCTRL_1 @ 0XFD070540 + + * Enables port n. + * PSU_DDRC_PCTRL_1_PORT_EN 0x1 + + * Port n Control Register + * (OFFSET, MASK, VALUE) (0XFD070540, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(DDRC_PCTRL_1_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : PCFGQOS0_1 @ 0XFD070544 + + * This bitfield indicates the traffic class of region2. For dual address q + * ueue configurations, region2 maps to the red address queue. Valid values + * are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN + * = 0) and traffic class of region2 is set to 1 (VPR), VPR traffic is ali + * ased to LPR traffic. + * PSU_DDRC_PCFGQOS0_1_RQOS_MAP_REGION2 0x2 + + * This bitfield indicates the traffic class of region 1. Valid values are: + * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + * maps to the blue address queue. In this case, valid values are 0: LPR a + * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. + * PSU_DDRC_PCFGQOS0_1_RQOS_MAP_REGION1 0x0 + + * This bitfield indicates the traffic class of region 0. Valid values are: + * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + * maps to the blue address queue. In this case, valid values are: 0: LPR + * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. + * PSU_DDRC_PCFGQOS0_1_RQOS_MAP_REGION0 0x0 + + * Separation level2 indicating the end of region1 mapping; start of region + * 1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 whi + * ch corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note + * that for PA, arqos values are used directly as port priorities, where t + * he higher the value corresponds to higher port priority. All of the map_ + * level* registers must be set to distinct values. + * PSU_DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2 0xb + + * Separation level1 indicating the end of region0 mapping; start of region + * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + * lues are used directly as port priorities, where the higher the value co + * rresponds to higher port priority. All of the map_level* registers must + * be set to distinct values. + * PSU_DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1 0x3 + + * Port n Read QoS Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD070544, 0x03330F0FU ,0x02000B03U) + */ + PSU_Mask_Write(DDRC_PCFGQOS0_1_OFFSET, 0x03330F0FU, 0x02000B03U); +/*##################################################################### */ + + /* + * Register : PCFGQOS1_1 @ 0XFD070548 + + * Specifies the timeout value for transactions mapped to the red address q + * ueue. + * PSU_DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR 0x0 + + * Specifies the timeout value for transactions mapped to the blue address + * queue. + * PSU_DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB 0x0 + + * Port n Read QoS Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD070548, 0x07FF07FFU ,0x00000000U) + */ + PSU_Mask_Write(DDRC_PCFGQOS1_1_OFFSET, 0x07FF07FFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : PCFGR_2 @ 0XFD070564 + + * If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. + * PSU_DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN 0x0 + + * If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + * bled and arurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + * urgent signal can be asserted anytime and as long as required which is i + * ndependent of address handshaking (it is not associated with any particu + * lar command). + * PSU_DDRC_PCFGR_2_RD_PORT_URGENT_EN 0x1 + + * If set to 1, enables aging function for the read channel of the port. + * PSU_DDRC_PCFGR_2_RD_PORT_AGING_EN 0x0 + + * Determines the initial load value of read aging counters. These counters + * will be parallel loaded after reset, or after each grant to the corresp + * onding port. The aging counters down-count every clock cycle where the p + * ort is requesting but not granted. The higher significant 5-bits of the + * read aging counter sets the priority of the read channel of a given port + * . Port's priority will increase as the higher significant 5-bits of the + * counter starts to decrease. When the aging counter becomes 0, the corres + * ponding port channel will have the highest priority level (timeout condi + * tion - Priority0). For multi-port configurations, the aging counters can + * not be used to set port priorities when external dynamic priority inputs + * (arqos) are enabled (timeout is still applicable). For single port conf + * igurations, the aging counters are only used when they timeout (become 0 + * ) to force read-write direction switching. In this case, external dynami + * c priority input, arqos (for reads only) can still be used to set the DD + * RC read priority (2 priority levels: low priority read - LPR, high prior + * ity read - HPR) on a command by command basis. Note: The two LSBs of thi + * s register field are tied internally to 2'b00. + * PSU_DDRC_PCFGR_2_RD_PORT_PRIORITY 0xf + + * Port n Configuration Read Register + * (OFFSET, MASK, VALUE) (0XFD070564, 0x000073FFU ,0x0000200FU) + */ + PSU_Mask_Write(DDRC_PCFGR_2_OFFSET, 0x000073FFU, 0x0000200FU); +/*##################################################################### */ + + /* + * Register : PCFGW_2 @ 0XFD070568 + + * If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. + * PSU_DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN 0x0 + + * If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + * bled and awurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + * serted anytime and as long as required which is independent of address h + * andshaking (it is not associated with any particular command). + * PSU_DDRC_PCFGW_2_WR_PORT_URGENT_EN 0x1 + + * If set to 1, enables aging function for the write channel of the port. + * PSU_DDRC_PCFGW_2_WR_PORT_AGING_EN 0x0 + + * Determines the initial load value of write aging counters. These counter + * s will be parallel loaded after reset, or after each grant to the corres + * ponding port. The aging counters down-count every clock cycle where the + * port is requesting but not granted. The higher significant 5-bits of the + * write aging counter sets the initial priority of the write channel of a + * given port. Port's priority will increase as the higher significant 5-b + * its of the counter starts to decrease. When the aging counter becomes 0, + * the corresponding port channel will have the highest priority level. Fo + * r multi-port configurations, the aging counters cannot be used to set po + * rt priorities when external dynamic priority inputs (awqos) are enabled + * (timeout is still applicable). For single port configurations, the aging + * counters are only used when they timeout (become 0) to force read-write + * direction switching. Note: The two LSBs of this register field are tied + * internally to 2'b00. + * PSU_DDRC_PCFGW_2_WR_PORT_PRIORITY 0xf + + * Port n Configuration Write Register + * (OFFSET, MASK, VALUE) (0XFD070568, 0x000073FFU ,0x0000200FU) + */ + PSU_Mask_Write(DDRC_PCFGW_2_OFFSET, 0x000073FFU, 0x0000200FU); +/*##################################################################### */ + + /* + * Register : PCTRL_2 @ 0XFD0705F0 + + * Enables port n. + * PSU_DDRC_PCTRL_2_PORT_EN 0x1 + + * Port n Control Register + * (OFFSET, MASK, VALUE) (0XFD0705F0, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(DDRC_PCTRL_2_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : PCFGQOS0_2 @ 0XFD0705F4 + + * This bitfield indicates the traffic class of region2. For dual address q + * ueue configurations, region2 maps to the red address queue. Valid values + * are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN + * = 0) and traffic class of region2 is set to 1 (VPR), VPR traffic is ali + * ased to LPR traffic. + * PSU_DDRC_PCFGQOS0_2_RQOS_MAP_REGION2 0x2 + + * This bitfield indicates the traffic class of region 1. Valid values are: + * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + * maps to the blue address queue. In this case, valid values are 0: LPR a + * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. + * PSU_DDRC_PCFGQOS0_2_RQOS_MAP_REGION1 0x0 + + * This bitfield indicates the traffic class of region 0. Valid values are: + * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + * maps to the blue address queue. In this case, valid values are: 0: LPR + * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. + * PSU_DDRC_PCFGQOS0_2_RQOS_MAP_REGION0 0x0 + + * Separation level2 indicating the end of region1 mapping; start of region + * 1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 whi + * ch corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note + * that for PA, arqos values are used directly as port priorities, where t + * he higher the value corresponds to higher port priority. All of the map_ + * level* registers must be set to distinct values. + * PSU_DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2 0xb + + * Separation level1 indicating the end of region0 mapping; start of region + * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + * lues are used directly as port priorities, where the higher the value co + * rresponds to higher port priority. All of the map_level* registers must + * be set to distinct values. + * PSU_DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1 0x3 + + * Port n Read QoS Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD0705F4, 0x03330F0FU ,0x02000B03U) + */ + PSU_Mask_Write(DDRC_PCFGQOS0_2_OFFSET, 0x03330F0FU, 0x02000B03U); +/*##################################################################### */ + + /* + * Register : PCFGQOS1_2 @ 0XFD0705F8 + + * Specifies the timeout value for transactions mapped to the red address q + * ueue. + * PSU_DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR 0x0 + + * Specifies the timeout value for transactions mapped to the blue address + * queue. + * PSU_DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB 0x0 + + * Port n Read QoS Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD0705F8, 0x07FF07FFU ,0x00000000U) + */ + PSU_Mask_Write(DDRC_PCFGQOS1_2_OFFSET, 0x07FF07FFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : PCFGR_3 @ 0XFD070614 + + * If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. + * PSU_DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN 0x0 + + * If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + * bled and arurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + * urgent signal can be asserted anytime and as long as required which is i + * ndependent of address handshaking (it is not associated with any particu + * lar command). + * PSU_DDRC_PCFGR_3_RD_PORT_URGENT_EN 0x1 + + * If set to 1, enables aging function for the read channel of the port. + * PSU_DDRC_PCFGR_3_RD_PORT_AGING_EN 0x0 + + * Determines the initial load value of read aging counters. These counters + * will be parallel loaded after reset, or after each grant to the corresp + * onding port. The aging counters down-count every clock cycle where the p + * ort is requesting but not granted. The higher significant 5-bits of the + * read aging counter sets the priority of the read channel of a given port + * . Port's priority will increase as the higher significant 5-bits of the + * counter starts to decrease. When the aging counter becomes 0, the corres + * ponding port channel will have the highest priority level (timeout condi + * tion - Priority0). For multi-port configurations, the aging counters can + * not be used to set port priorities when external dynamic priority inputs + * (arqos) are enabled (timeout is still applicable). For single port conf + * igurations, the aging counters are only used when they timeout (become 0 + * ) to force read-write direction switching. In this case, external dynami + * c priority input, arqos (for reads only) can still be used to set the DD + * RC read priority (2 priority levels: low priority read - LPR, high prior + * ity read - HPR) on a command by command basis. Note: The two LSBs of thi + * s register field are tied internally to 2'b00. + * PSU_DDRC_PCFGR_3_RD_PORT_PRIORITY 0xf + + * Port n Configuration Read Register + * (OFFSET, MASK, VALUE) (0XFD070614, 0x000073FFU ,0x0000200FU) + */ + PSU_Mask_Write(DDRC_PCFGR_3_OFFSET, 0x000073FFU, 0x0000200FU); +/*##################################################################### */ + + /* + * Register : PCFGW_3 @ 0XFD070618 + + * If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. + * PSU_DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN 0x0 + + * If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + * bled and awurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + * serted anytime and as long as required which is independent of address h + * andshaking (it is not associated with any particular command). + * PSU_DDRC_PCFGW_3_WR_PORT_URGENT_EN 0x1 + + * If set to 1, enables aging function for the write channel of the port. + * PSU_DDRC_PCFGW_3_WR_PORT_AGING_EN 0x0 + + * Determines the initial load value of write aging counters. These counter + * s will be parallel loaded after reset, or after each grant to the corres + * ponding port. The aging counters down-count every clock cycle where the + * port is requesting but not granted. The higher significant 5-bits of the + * write aging counter sets the initial priority of the write channel of a + * given port. Port's priority will increase as the higher significant 5-b + * its of the counter starts to decrease. When the aging counter becomes 0, + * the corresponding port channel will have the highest priority level. Fo + * r multi-port configurations, the aging counters cannot be used to set po + * rt priorities when external dynamic priority inputs (awqos) are enabled + * (timeout is still applicable). For single port configurations, the aging + * counters are only used when they timeout (become 0) to force read-write + * direction switching. Note: The two LSBs of this register field are tied + * internally to 2'b00. + * PSU_DDRC_PCFGW_3_WR_PORT_PRIORITY 0xf + + * Port n Configuration Write Register + * (OFFSET, MASK, VALUE) (0XFD070618, 0x000073FFU ,0x0000200FU) + */ + PSU_Mask_Write(DDRC_PCFGW_3_OFFSET, 0x000073FFU, 0x0000200FU); +/*##################################################################### */ + + /* + * Register : PCTRL_3 @ 0XFD0706A0 + + * Enables port n. + * PSU_DDRC_PCTRL_3_PORT_EN 0x1 + + * Port n Control Register + * (OFFSET, MASK, VALUE) (0XFD0706A0, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(DDRC_PCTRL_3_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : PCFGQOS0_3 @ 0XFD0706A4 + + * This bitfield indicates the traffic class of region 1. Valid values are: + * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + * maps to the blue address queue. In this case, valid values are 0: LPR a + * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. + * PSU_DDRC_PCFGQOS0_3_RQOS_MAP_REGION1 0x1 + + * This bitfield indicates the traffic class of region 0. Valid values are: + * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + * maps to the blue address queue. In this case, valid values are: 0: LPR + * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. + * PSU_DDRC_PCFGQOS0_3_RQOS_MAP_REGION0 0x0 + + * Separation level1 indicating the end of region0 mapping; start of region + * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + * lues are used directly as port priorities, where the higher the value co + * rresponds to higher port priority. All of the map_level* registers must + * be set to distinct values. + * PSU_DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1 0x3 + + * Port n Read QoS Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD0706A4, 0x0033000FU ,0x00100003U) + */ + PSU_Mask_Write(DDRC_PCFGQOS0_3_OFFSET, 0x0033000FU, 0x00100003U); +/*##################################################################### */ + + /* + * Register : PCFGQOS1_3 @ 0XFD0706A8 + + * Specifies the timeout value for transactions mapped to the red address q + * ueue. + * PSU_DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR 0x0 + + * Specifies the timeout value for transactions mapped to the blue address + * queue. + * PSU_DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB 0x4f + + * Port n Read QoS Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD0706A8, 0x07FF07FFU ,0x0000004FU) + */ + PSU_Mask_Write(DDRC_PCFGQOS1_3_OFFSET, 0x07FF07FFU, 0x0000004FU); +/*##################################################################### */ + + /* + * Register : PCFGWQOS0_3 @ 0XFD0706AC + + * This bitfield indicates the traffic class of region 1. Valid values are: + * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + * affic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW + * traffic. + * PSU_DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1 0x1 + + * This bitfield indicates the traffic class of region 0. Valid values are: + * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + * affic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW + * traffic. + * PSU_DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0 0x0 + + * Separation level indicating the end of region0 mapping; start of region0 + * is 0. Possible values for level1 are 0 to 14 which corresponds to awqos + * . Note that for PA, awqos values are used directly as port priorities, w + * here the higher the value corresponds to higher port priority. + * PSU_DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL 0x3 + + * Port n Write QoS Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD0706AC, 0x0033000FU ,0x00100003U) + */ + PSU_Mask_Write(DDRC_PCFGWQOS0_3_OFFSET, 0x0033000FU, 0x00100003U); +/*##################################################################### */ + + /* + * Register : PCFGWQOS1_3 @ 0XFD0706B0 + + * Specifies the timeout value for write transactions. + * PSU_DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT 0x4f + + * Port n Write QoS Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD0706B0, 0x000007FFU ,0x0000004FU) + */ + PSU_Mask_Write(DDRC_PCFGWQOS1_3_OFFSET, 0x000007FFU, 0x0000004FU); +/*##################################################################### */ + + /* + * Register : PCFGR_4 @ 0XFD0706C4 + + * If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. + * PSU_DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN 0x0 + + * If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + * bled and arurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + * urgent signal can be asserted anytime and as long as required which is i + * ndependent of address handshaking (it is not associated with any particu + * lar command). + * PSU_DDRC_PCFGR_4_RD_PORT_URGENT_EN 0x1 + + * If set to 1, enables aging function for the read channel of the port. + * PSU_DDRC_PCFGR_4_RD_PORT_AGING_EN 0x0 + + * Determines the initial load value of read aging counters. These counters + * will be parallel loaded after reset, or after each grant to the corresp + * onding port. The aging counters down-count every clock cycle where the p + * ort is requesting but not granted. The higher significant 5-bits of the + * read aging counter sets the priority of the read channel of a given port + * . Port's priority will increase as the higher significant 5-bits of the + * counter starts to decrease. When the aging counter becomes 0, the corres + * ponding port channel will have the highest priority level (timeout condi + * tion - Priority0). For multi-port configurations, the aging counters can + * not be used to set port priorities when external dynamic priority inputs + * (arqos) are enabled (timeout is still applicable). For single port conf + * igurations, the aging counters are only used when they timeout (become 0 + * ) to force read-write direction switching. In this case, external dynami + * c priority input, arqos (for reads only) can still be used to set the DD + * RC read priority (2 priority levels: low priority read - LPR, high prior + * ity read - HPR) on a command by command basis. Note: The two LSBs of thi + * s register field are tied internally to 2'b00. + * PSU_DDRC_PCFGR_4_RD_PORT_PRIORITY 0xf + + * Port n Configuration Read Register + * (OFFSET, MASK, VALUE) (0XFD0706C4, 0x000073FFU ,0x0000200FU) + */ + PSU_Mask_Write(DDRC_PCFGR_4_OFFSET, 0x000073FFU, 0x0000200FU); +/*##################################################################### */ + + /* + * Register : PCFGW_4 @ 0XFD0706C8 + + * If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. + * PSU_DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN 0x0 + + * If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + * bled and awurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + * serted anytime and as long as required which is independent of address h + * andshaking (it is not associated with any particular command). + * PSU_DDRC_PCFGW_4_WR_PORT_URGENT_EN 0x1 + + * If set to 1, enables aging function for the write channel of the port. + * PSU_DDRC_PCFGW_4_WR_PORT_AGING_EN 0x0 + + * Determines the initial load value of write aging counters. These counter + * s will be parallel loaded after reset, or after each grant to the corres + * ponding port. The aging counters down-count every clock cycle where the + * port is requesting but not granted. The higher significant 5-bits of the + * write aging counter sets the initial priority of the write channel of a + * given port. Port's priority will increase as the higher significant 5-b + * its of the counter starts to decrease. When the aging counter becomes 0, + * the corresponding port channel will have the highest priority level. Fo + * r multi-port configurations, the aging counters cannot be used to set po + * rt priorities when external dynamic priority inputs (awqos) are enabled + * (timeout is still applicable). For single port configurations, the aging + * counters are only used when they timeout (become 0) to force read-write + * direction switching. Note: The two LSBs of this register field are tied + * internally to 2'b00. + * PSU_DDRC_PCFGW_4_WR_PORT_PRIORITY 0xf + + * Port n Configuration Write Register + * (OFFSET, MASK, VALUE) (0XFD0706C8, 0x000073FFU ,0x0000200FU) + */ + PSU_Mask_Write(DDRC_PCFGW_4_OFFSET, 0x000073FFU, 0x0000200FU); +/*##################################################################### */ + + /* + * Register : PCTRL_4 @ 0XFD070750 + + * Enables port n. + * PSU_DDRC_PCTRL_4_PORT_EN 0x1 + + * Port n Control Register + * (OFFSET, MASK, VALUE) (0XFD070750, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(DDRC_PCTRL_4_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : PCFGQOS0_4 @ 0XFD070754 + + * This bitfield indicates the traffic class of region 1. Valid values are: + * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + * maps to the blue address queue. In this case, valid values are 0: LPR a + * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. + * PSU_DDRC_PCFGQOS0_4_RQOS_MAP_REGION1 0x1 + + * This bitfield indicates the traffic class of region 0. Valid values are: + * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + * maps to the blue address queue. In this case, valid values are: 0: LPR + * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. + * PSU_DDRC_PCFGQOS0_4_RQOS_MAP_REGION0 0x0 + + * Separation level1 indicating the end of region0 mapping; start of region + * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + * lues are used directly as port priorities, where the higher the value co + * rresponds to higher port priority. All of the map_level* registers must + * be set to distinct values. + * PSU_DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1 0x3 + + * Port n Read QoS Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD070754, 0x0033000FU ,0x00100003U) + */ + PSU_Mask_Write(DDRC_PCFGQOS0_4_OFFSET, 0x0033000FU, 0x00100003U); +/*##################################################################### */ + + /* + * Register : PCFGQOS1_4 @ 0XFD070758 + + * Specifies the timeout value for transactions mapped to the red address q + * ueue. + * PSU_DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR 0x0 + + * Specifies the timeout value for transactions mapped to the blue address + * queue. + * PSU_DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB 0x4f + + * Port n Read QoS Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD070758, 0x07FF07FFU ,0x0000004FU) + */ + PSU_Mask_Write(DDRC_PCFGQOS1_4_OFFSET, 0x07FF07FFU, 0x0000004FU); +/*##################################################################### */ + + /* + * Register : PCFGWQOS0_4 @ 0XFD07075C + + * This bitfield indicates the traffic class of region 1. Valid values are: + * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + * affic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW + * traffic. + * PSU_DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1 0x1 + + * This bitfield indicates the traffic class of region 0. Valid values are: + * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + * affic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW + * traffic. + * PSU_DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0 0x0 + + * Separation level indicating the end of region0 mapping; start of region0 + * is 0. Possible values for level1 are 0 to 14 which corresponds to awqos + * . Note that for PA, awqos values are used directly as port priorities, w + * here the higher the value corresponds to higher port priority. + * PSU_DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL 0x3 + + * Port n Write QoS Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD07075C, 0x0033000FU ,0x00100003U) + */ + PSU_Mask_Write(DDRC_PCFGWQOS0_4_OFFSET, 0x0033000FU, 0x00100003U); +/*##################################################################### */ + + /* + * Register : PCFGWQOS1_4 @ 0XFD070760 + + * Specifies the timeout value for write transactions. + * PSU_DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT 0x4f + + * Port n Write QoS Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD070760, 0x000007FFU ,0x0000004FU) + */ + PSU_Mask_Write(DDRC_PCFGWQOS1_4_OFFSET, 0x000007FFU, 0x0000004FU); +/*##################################################################### */ + + /* + * Register : PCFGR_5 @ 0XFD070774 + + * If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. + * PSU_DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN 0x0 + + * If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + * bled and arurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + * urgent signal can be asserted anytime and as long as required which is i + * ndependent of address handshaking (it is not associated with any particu + * lar command). + * PSU_DDRC_PCFGR_5_RD_PORT_URGENT_EN 0x1 + + * If set to 1, enables aging function for the read channel of the port. + * PSU_DDRC_PCFGR_5_RD_PORT_AGING_EN 0x0 + + * Determines the initial load value of read aging counters. These counters + * will be parallel loaded after reset, or after each grant to the corresp + * onding port. The aging counters down-count every clock cycle where the p + * ort is requesting but not granted. The higher significant 5-bits of the + * read aging counter sets the priority of the read channel of a given port + * . Port's priority will increase as the higher significant 5-bits of the + * counter starts to decrease. When the aging counter becomes 0, the corres + * ponding port channel will have the highest priority level (timeout condi + * tion - Priority0). For multi-port configurations, the aging counters can + * not be used to set port priorities when external dynamic priority inputs + * (arqos) are enabled (timeout is still applicable). For single port conf + * igurations, the aging counters are only used when they timeout (become 0 + * ) to force read-write direction switching. In this case, external dynami + * c priority input, arqos (for reads only) can still be used to set the DD + * RC read priority (2 priority levels: low priority read - LPR, high prior + * ity read - HPR) on a command by command basis. Note: The two LSBs of thi + * s register field are tied internally to 2'b00. + * PSU_DDRC_PCFGR_5_RD_PORT_PRIORITY 0xf + + * Port n Configuration Read Register + * (OFFSET, MASK, VALUE) (0XFD070774, 0x000073FFU ,0x0000200FU) + */ + PSU_Mask_Write(DDRC_PCFGR_5_OFFSET, 0x000073FFU, 0x0000200FU); +/*##################################################################### */ + + /* + * Register : PCFGW_5 @ 0XFD070778 + + * If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. + * PSU_DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN 0x0 + + * If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + * bled and awurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + * serted anytime and as long as required which is independent of address h + * andshaking (it is not associated with any particular command). + * PSU_DDRC_PCFGW_5_WR_PORT_URGENT_EN 0x1 + + * If set to 1, enables aging function for the write channel of the port. + * PSU_DDRC_PCFGW_5_WR_PORT_AGING_EN 0x0 + + * Determines the initial load value of write aging counters. These counter + * s will be parallel loaded after reset, or after each grant to the corres + * ponding port. The aging counters down-count every clock cycle where the + * port is requesting but not granted. The higher significant 5-bits of the + * write aging counter sets the initial priority of the write channel of a + * given port. Port's priority will increase as the higher significant 5-b + * its of the counter starts to decrease. When the aging counter becomes 0, + * the corresponding port channel will have the highest priority level. Fo + * r multi-port configurations, the aging counters cannot be used to set po + * rt priorities when external dynamic priority inputs (awqos) are enabled + * (timeout is still applicable). For single port configurations, the aging + * counters are only used when they timeout (become 0) to force read-write + * direction switching. Note: The two LSBs of this register field are tied + * internally to 2'b00. + * PSU_DDRC_PCFGW_5_WR_PORT_PRIORITY 0xf + + * Port n Configuration Write Register + * (OFFSET, MASK, VALUE) (0XFD070778, 0x000073FFU ,0x0000200FU) + */ + PSU_Mask_Write(DDRC_PCFGW_5_OFFSET, 0x000073FFU, 0x0000200FU); +/*##################################################################### */ + + /* + * Register : PCTRL_5 @ 0XFD070800 + + * Enables port n. + * PSU_DDRC_PCTRL_5_PORT_EN 0x1 + + * Port n Control Register + * (OFFSET, MASK, VALUE) (0XFD070800, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(DDRC_PCTRL_5_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : PCFGQOS0_5 @ 0XFD070804 + + * This bitfield indicates the traffic class of region 1. Valid values are: + * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + * maps to the blue address queue. In this case, valid values are 0: LPR a + * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. + * PSU_DDRC_PCFGQOS0_5_RQOS_MAP_REGION1 0x1 + + * This bitfield indicates the traffic class of region 0. Valid values are: + * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + * maps to the blue address queue. In this case, valid values are: 0: LPR + * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. + * PSU_DDRC_PCFGQOS0_5_RQOS_MAP_REGION0 0x0 + + * Separation level1 indicating the end of region0 mapping; start of region + * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + * lues are used directly as port priorities, where the higher the value co + * rresponds to higher port priority. All of the map_level* registers must + * be set to distinct values. + * PSU_DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1 0x3 + + * Port n Read QoS Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD070804, 0x0033000FU ,0x00100003U) + */ + PSU_Mask_Write(DDRC_PCFGQOS0_5_OFFSET, 0x0033000FU, 0x00100003U); +/*##################################################################### */ + + /* + * Register : PCFGQOS1_5 @ 0XFD070808 + + * Specifies the timeout value for transactions mapped to the red address q + * ueue. + * PSU_DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR 0x0 + + * Specifies the timeout value for transactions mapped to the blue address + * queue. + * PSU_DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB 0x4f + + * Port n Read QoS Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD070808, 0x07FF07FFU ,0x0000004FU) + */ + PSU_Mask_Write(DDRC_PCFGQOS1_5_OFFSET, 0x07FF07FFU, 0x0000004FU); +/*##################################################################### */ + + /* + * Register : PCFGWQOS0_5 @ 0XFD07080C + + * This bitfield indicates the traffic class of region 1. Valid values are: + * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + * affic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW + * traffic. + * PSU_DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1 0x1 + + * This bitfield indicates the traffic class of region 0. Valid values are: + * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + * affic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW + * traffic. + * PSU_DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0 0x0 + + * Separation level indicating the end of region0 mapping; start of region0 + * is 0. Possible values for level1 are 0 to 14 which corresponds to awqos + * . Note that for PA, awqos values are used directly as port priorities, w + * here the higher the value corresponds to higher port priority. + * PSU_DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL 0x3 + + * Port n Write QoS Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD07080C, 0x0033000FU ,0x00100003U) + */ + PSU_Mask_Write(DDRC_PCFGWQOS0_5_OFFSET, 0x0033000FU, 0x00100003U); +/*##################################################################### */ + + /* + * Register : PCFGWQOS1_5 @ 0XFD070810 + + * Specifies the timeout value for write transactions. + * PSU_DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT 0x4f + + * Port n Write QoS Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD070810, 0x000007FFU ,0x0000004FU) + */ + PSU_Mask_Write(DDRC_PCFGWQOS1_5_OFFSET, 0x000007FFU, 0x0000004FU); +/*##################################################################### */ + + /* + * Register : SARBASE0 @ 0XFD070F04 + + * Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x + * ] and araddr[UMCTL2_A_ADDRW-1:x] where x is determined by the minimum bl + * ock size parameter UMCTL2_SARMINSIZE: (x=log2(block size)). + * PSU_DDRC_SARBASE0_BASE_ADDR 0x0 + + * SAR Base Address Register n + * (OFFSET, MASK, VALUE) (0XFD070F04, 0x000001FFU ,0x00000000U) + */ + PSU_Mask_Write(DDRC_SARBASE0_OFFSET, 0x000001FFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : SARSIZE0 @ 0XFD070F08 + + * Number of blocks for address region n. This register determines the tota + * l size of the region in multiples of minimum block size as specified by + * the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded + * as number of blocks = nblocks + 1. For example, if register is programme + * d to 0, region will have 1 block. + * PSU_DDRC_SARSIZE0_NBLOCKS 0x0 + + * SAR Size Register n + * (OFFSET, MASK, VALUE) (0XFD070F08, 0x000000FFU ,0x00000000U) + */ + PSU_Mask_Write(DDRC_SARSIZE0_OFFSET, 0x000000FFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : SARBASE1 @ 0XFD070F0C + + * Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x + * ] and araddr[UMCTL2_A_ADDRW-1:x] where x is determined by the minimum bl + * ock size parameter UMCTL2_SARMINSIZE: (x=log2(block size)). + * PSU_DDRC_SARBASE1_BASE_ADDR 0x10 + + * SAR Base Address Register n + * (OFFSET, MASK, VALUE) (0XFD070F0C, 0x000001FFU ,0x00000010U) + */ + PSU_Mask_Write(DDRC_SARBASE1_OFFSET, 0x000001FFU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : SARSIZE1 @ 0XFD070F10 + + * Number of blocks for address region n. This register determines the tota + * l size of the region in multiples of minimum block size as specified by + * the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded + * as number of blocks = nblocks + 1. For example, if register is programme + * d to 0, region will have 1 block. + * PSU_DDRC_SARSIZE1_NBLOCKS 0xf + + * SAR Size Register n + * (OFFSET, MASK, VALUE) (0XFD070F10, 0x000000FFU ,0x0000000FU) + */ + PSU_Mask_Write(DDRC_SARSIZE1_OFFSET, 0x000000FFU, 0x0000000FU); +/*##################################################################### */ + + /* + * Register : DFITMG0_SHADOW @ 0XFD072190 + + * Specifies the number of DFI clock cycles after an assertion or de-assert + * ion of the DFI control signals that the control signals at the PHY-DRAM + * interface reflect the assertion or de-assertion. If the DFI clock and th + * e memory clock are not phase-aligned, this timing parameter should be ro + * unded up to the next integer value. Note that if using RDIMM, it is nece + * ssary to increment this parameter by RDIMM's extra cycle of latency in t + * erms of DFI clock. + * PSU_DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY 0x7 + + * Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated u + * sing HDR or SDR values Selects whether value in DFITMG0.dfi_t_rddata_en + * is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles + * - 1 in terms of SDR clock cycles Refer to PHY specification for correct + * value. + * PSU_DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR 0x1 + + * Time from the assertion of a read command on the DFI interface to the as + * sertion of the dfi_rddata_en signal. Refer to PHY specification for corr + * ect value. This corresponds to the DFI parameter trddata_en. Note that, + * depending on the PHY, if using RDIMM, it may be necessary to use the val + * ue (CL + 1) in the calculation of trddata_en. This is to compensate for + * the extra cycle of latency through the RDIMM. Unit: Clocks + * PSU_DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN 0x2 + + * Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated us + * ing HDR or SDR values Selects whether value in DFITMG0.dfi_tphy_wrlat is + * in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.df + * i_tphy_wrdata is in terms of SDR or HDR clock cycles - 0 in terms of HDR + * clock cycles - 1 in terms of SDR clock cycles Refer to PHY specificatio + * n for correct value. + * PSU_DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR 0x1 + + * Specifies the number of clock cycles between when dfi_wrdata_en is asser + * ted to when the associated write data is driven on the dfi_wrdata signal + * . This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY + * specification for correct value. Note, max supported value is 8. Unit: + * Clocks + * PSU_DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA 0x0 + + * Write latency Number of clocks from the write command to write data enab + * le (dfi_wrdata_en). This corresponds to the DFI timing parameter tphy_wr + * lat. Refer to PHY specification for correct value.Note that, depending o + * n the PHY, if using RDIMM, it may be necessary to use the value (CL + 1) + * in the calculation of tphy_wrlat. This is to compensate for the extra c + * ycle of latency through the RDIMM. + * PSU_DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT 0x2 + + * DFI Timing Shadow Register 0 + * (OFFSET, MASK, VALUE) (0XFD072190, 0x1FBFBF3FU ,0x07828002U) + */ + PSU_Mask_Write(DDRC_DFITMG0_SHADOW_OFFSET, 0x1FBFBF3FU, 0x07828002U); +/*##################################################################### */ + + /* + * DDR CONTROLLER RESET + */ + /* + * Register : RST_DDR_SS @ 0XFD1A0108 + + * DDR block level reset inside of the DDR Sub System + * PSU_CRF_APB_RST_DDR_SS_DDR_RESET 0X0 + + * APM block level reset inside of the DDR Sub System + * PSU_CRF_APB_RST_DDR_SS_APM_RESET 0X0 + + * DDR sub system block level reset + * (OFFSET, MASK, VALUE) (0XFD1A0108, 0x0000000CU ,0x00000000U) + */ + PSU_Mask_Write(CRF_APB_RST_DDR_SS_OFFSET, 0x0000000CU, 0x00000000U); +/*##################################################################### */ + + /* + * DDR PHY + */ + /* + * Register : PGCR0 @ 0XFD080010 + + * Address Copy + * PSU_DDR_PHY_PGCR0_ADCP 0x0 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_PGCR0_RESERVED_30_27 0x0 + + * PHY FIFO Reset + * PSU_DDR_PHY_PGCR0_PHYFRST 0x1 + + * Oscillator Mode Address/Command Delay Line Select + * PSU_DDR_PHY_PGCR0_OSCACDL 0x3 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_PGCR0_RESERVED_23_19 0x0 + + * Digital Test Output Select + * PSU_DDR_PHY_PGCR0_DTOSEL 0x0 - RegVal = ((0x0000000FU << DDRC_SARSIZE1_NBLOCKS_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_SARSIZE1_OFFSET ,0x000000FFU ,0x0000000FU); - /*############################################################################################################################ */ + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_PGCR0_RESERVED_13 0x0 - /*Register : DFITMG0_SHADOW @ 0XFD072190

+ * Oscillator Mode Division + * PSU_DDR_PHY_PGCR0_OSCDIV 0xf - Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signa - s at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligne - , this timing parameter should be rounded up to the next integer value. Note that if using RDIMM, it is necessary to incremen - this parameter by RDIMM's extra cycle of latency in terms of DFI clock. - PSU_DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY 0x7 - - Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR or SDR values Selects whether value in DFITM - 0.dfi_t_rddata_en is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles R - fer to PHY specification for correct value. - PSU_DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR 0x1 - - Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. Refer to PHY spe - ification for correct value. This corresponds to the DFI parameter trddata_en. Note that, depending on the PHY, if using RDIM - , it may be necessary to use the value (CL + 1) in the calculation of trddata_en. This is to compensate for the extra cycle o - latency through the RDIMM. Unit: Clocks - PSU_DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN 0x2 - - Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using HDR or SDR values Selects whether value in DFITMG - .dfi_tphy_wrlat is in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.dfi_tphy_wrdata is in terms of SDR or - HDR clock cycles - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles Refer to PHY specification for correct val - e. - PSU_DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR 0x1 - - Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on th - dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. N - te, max supported value is 8. Unit: Clocks - PSU_DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA 0x0 - - Write latency Number of clocks from the write command to write data enable (dfi_wrdata_en). This corresponds to the DFI timin - parameter tphy_wrlat. Refer to PHY specification for correct value.Note that, depending on the PHY, if using RDIMM, it may b - necessary to use the value (CL + 1) in the calculation of tphy_wrlat. This is to compensate for the extra cycle of latency t - rough the RDIMM. - PSU_DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT 0x2 + * Oscillator Enable + * PSU_DDR_PHY_PGCR0_OSCEN 0x0 - DFI Timing Shadow Register 0 - (OFFSET, MASK, VALUE) (0XFD072190, 0x1FBFBF3FU ,0x07828002U) - RegMask = (DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_MASK | DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_MASK | DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_MASK | DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_MASK | DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_MASK | DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_MASK | 0 ); + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_PGCR0_RESERVED_7_0 0x0 - RegVal = ((0x00000007U << DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_SHIFT - | 0x00000001U << DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_SHIFT - | 0x00000002U << DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_SHIFT - | 0x00000001U << DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_SHIFT - | 0x00000000U << DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_SHIFT - | 0x00000002U << DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DFITMG0_SHADOW_OFFSET ,0x1FBFBF3FU ,0x07828002U); - /*############################################################################################################################ */ - - // : DDR CONTROLLER RESET - /*Register : RST_DDR_SS @ 0XFD1A0108

- - DDR block level reset inside of the DDR Sub System - PSU_CRF_APB_RST_DDR_SS_DDR_RESET 0X0 - - DDR sub system block level reset - (OFFSET, MASK, VALUE) (0XFD1A0108, 0x00000008U ,0x00000000U) - RegMask = (CRF_APB_RST_DDR_SS_DDR_RESET_MASK | 0 ); - - RegVal = ((0x00000000U << CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_RST_DDR_SS_OFFSET ,0x00000008U ,0x00000000U); - /*############################################################################################################################ */ - - // : DDR PHY - /*Register : PGCR0 @ 0XFD080010

- - Address Copy - PSU_DDR_PHY_PGCR0_ADCP 0x0 - - Reserved. Returns zeroes on reads. - PSU_DDR_PHY_PGCR0_RESERVED_30_27 0x0 - - PHY FIFO Reset - PSU_DDR_PHY_PGCR0_PHYFRST 0x1 - - Oscillator Mode Address/Command Delay Line Select - PSU_DDR_PHY_PGCR0_OSCACDL 0x3 - - Reserved. Returns zeroes on reads. - PSU_DDR_PHY_PGCR0_RESERVED_23_19 0x0 + * PHY General Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD080010, 0xFFFFFFFFU ,0x07001E00U) + */ + PSU_Mask_Write(DDR_PHY_PGCR0_OFFSET, 0xFFFFFFFFU, 0x07001E00U); +/*##################################################################### */ - Digital Test Output Select - PSU_DDR_PHY_PGCR0_DTOSEL 0x0 + /* + * Register : PGCR2 @ 0XFD080018 - Reserved. Returns zeroes on reads. - PSU_DDR_PHY_PGCR0_RESERVED_13 0x0 + * Clear Training Status Registers + * PSU_DDR_PHY_PGCR2_CLRTSTAT 0x0 - Oscillator Mode Division - PSU_DDR_PHY_PGCR0_OSCDIV 0xf + * Clear Impedance Calibration + * PSU_DDR_PHY_PGCR2_CLRZCAL 0x0 - Oscillator Enable - PSU_DDR_PHY_PGCR0_OSCEN 0x0 + * Clear Parity Error + * PSU_DDR_PHY_PGCR2_CLRPERR 0x0 - Reserved. Returns zeroes on reads. - PSU_DDR_PHY_PGCR0_RESERVED_7_0 0x0 + * Initialization Complete Pin Configuration + * PSU_DDR_PHY_PGCR2_ICPC 0x0 - PHY General Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD080010, 0xFFFFFFFFU ,0x07001E00U) - RegMask = (DDR_PHY_PGCR0_ADCP_MASK | DDR_PHY_PGCR0_RESERVED_30_27_MASK | DDR_PHY_PGCR0_PHYFRST_MASK | DDR_PHY_PGCR0_OSCACDL_MASK | DDR_PHY_PGCR0_RESERVED_23_19_MASK | DDR_PHY_PGCR0_DTOSEL_MASK | DDR_PHY_PGCR0_RESERVED_13_MASK | DDR_PHY_PGCR0_OSCDIV_MASK | DDR_PHY_PGCR0_OSCEN_MASK | DDR_PHY_PGCR0_RESERVED_7_0_MASK | 0 ); + * Data Training PUB Mode Exit Timer + * PSU_DDR_PHY_PGCR2_DTPMXTMR 0xf - RegVal = ((0x00000000U << DDR_PHY_PGCR0_ADCP_SHIFT - | 0x00000000U << DDR_PHY_PGCR0_RESERVED_30_27_SHIFT - | 0x00000001U << DDR_PHY_PGCR0_PHYFRST_SHIFT - | 0x00000003U << DDR_PHY_PGCR0_OSCACDL_SHIFT - | 0x00000000U << DDR_PHY_PGCR0_RESERVED_23_19_SHIFT - | 0x00000000U << DDR_PHY_PGCR0_DTOSEL_SHIFT - | 0x00000000U << DDR_PHY_PGCR0_RESERVED_13_SHIFT - | 0x0000000FU << DDR_PHY_PGCR0_OSCDIV_SHIFT - | 0x00000000U << DDR_PHY_PGCR0_OSCEN_SHIFT - | 0x00000000U << DDR_PHY_PGCR0_RESERVED_7_0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_PGCR0_OFFSET ,0xFFFFFFFFU ,0x07001E00U); - /*############################################################################################################################ */ - - /*Register : PGCR2 @ 0XFD080018

+ * Initialization Bypass + * PSU_DDR_PHY_PGCR2_INITFSMBYP 0x0 - Clear Training Status Registers - PSU_DDR_PHY_PGCR2_CLRTSTAT 0x0 + * PLL FSM Bypass + * PSU_DDR_PHY_PGCR2_PLLFSMBYP 0x0 - Clear Impedance Calibration - PSU_DDR_PHY_PGCR2_CLRZCAL 0x0 + * Refresh Period + * PSU_DDR_PHY_PGCR2_TREFPRD 0x10010 - Clear Parity Error - PSU_DDR_PHY_PGCR2_CLRPERR 0x0 + * PHY General Configuration Register 2 + * (OFFSET, MASK, VALUE) (0XFD080018, 0xFFFFFFFFU ,0x00F10010U) + */ + PSU_Mask_Write(DDR_PHY_PGCR2_OFFSET, 0xFFFFFFFFU, 0x00F10010U); +/*##################################################################### */ - Initialization Complete Pin Configuration - PSU_DDR_PHY_PGCR2_ICPC 0x0 + /* + * Register : PGCR3 @ 0XFD08001C - Data Training PUB Mode Exit Timer - PSU_DDR_PHY_PGCR2_DTPMXTMR 0xf + * CKN Enable + * PSU_DDR_PHY_PGCR3_CKNEN 0x55 - Initialization Bypass - PSU_DDR_PHY_PGCR2_INITFSMBYP 0x0 + * CK Enable + * PSU_DDR_PHY_PGCR3_CKEN 0xaa - PLL FSM Bypass - PSU_DDR_PHY_PGCR2_PLLFSMBYP 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_PGCR3_RESERVED_15 0x0 - Refresh Period - PSU_DDR_PHY_PGCR2_TREFPRD 0x10028 + * Enable Clock Gating for AC [0] ctl_rd_clk + * PSU_DDR_PHY_PGCR3_GATEACRDCLK 0x2 - PHY General Configuration Register 2 - (OFFSET, MASK, VALUE) (0XFD080018, 0xFFFFFFFFU ,0x00F10028U) - RegMask = (DDR_PHY_PGCR2_CLRTSTAT_MASK | DDR_PHY_PGCR2_CLRZCAL_MASK | DDR_PHY_PGCR2_CLRPERR_MASK | DDR_PHY_PGCR2_ICPC_MASK | DDR_PHY_PGCR2_DTPMXTMR_MASK | DDR_PHY_PGCR2_INITFSMBYP_MASK | DDR_PHY_PGCR2_PLLFSMBYP_MASK | DDR_PHY_PGCR2_TREFPRD_MASK | 0 ); + * Enable Clock Gating for AC [0] ddr_clk + * PSU_DDR_PHY_PGCR3_GATEACDDRCLK 0x2 - RegVal = ((0x00000000U << DDR_PHY_PGCR2_CLRTSTAT_SHIFT - | 0x00000000U << DDR_PHY_PGCR2_CLRZCAL_SHIFT - | 0x00000000U << DDR_PHY_PGCR2_CLRPERR_SHIFT - | 0x00000000U << DDR_PHY_PGCR2_ICPC_SHIFT - | 0x0000000FU << DDR_PHY_PGCR2_DTPMXTMR_SHIFT - | 0x00000000U << DDR_PHY_PGCR2_INITFSMBYP_SHIFT - | 0x00000000U << DDR_PHY_PGCR2_PLLFSMBYP_SHIFT - | 0x00010028U << DDR_PHY_PGCR2_TREFPRD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_PGCR2_OFFSET ,0xFFFFFFFFU ,0x00F10028U); - /*############################################################################################################################ */ + * Enable Clock Gating for AC [0] ctl_clk + * PSU_DDR_PHY_PGCR3_GATEACCTLCLK 0x2 - /*Register : PGCR3 @ 0XFD08001C

+ * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_PGCR3_RESERVED_8 0x0 - CKN Enable - PSU_DDR_PHY_PGCR3_CKNEN 0x55 + * Controls DDL Bypass Modes + * PSU_DDR_PHY_PGCR3_DDLBYPMODE 0x2 - CK Enable - PSU_DDR_PHY_PGCR3_CKEN 0xaa + * IO Loop-Back Select + * PSU_DDR_PHY_PGCR3_IOLB 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_PGCR3_RESERVED_15 0x0 + * AC Receive FIFO Read Mode + * PSU_DDR_PHY_PGCR3_RDMODE 0x0 - Enable Clock Gating for AC [0] ctl_rd_clk - PSU_DDR_PHY_PGCR3_GATEACRDCLK 0x2 + * Read FIFO Reset Disable + * PSU_DDR_PHY_PGCR3_DISRST 0x0 - Enable Clock Gating for AC [0] ddr_clk - PSU_DDR_PHY_PGCR3_GATEACDDRCLK 0x2 + * Clock Level when Clock Gating + * PSU_DDR_PHY_PGCR3_CLKLEVEL 0x0 - Enable Clock Gating for AC [0] ctl_clk - PSU_DDR_PHY_PGCR3_GATEACCTLCLK 0x2 + * PHY General Configuration Register 3 + * (OFFSET, MASK, VALUE) (0XFD08001C, 0xFFFFFFFFU ,0x55AA5480U) + */ + PSU_Mask_Write(DDR_PHY_PGCR3_OFFSET, 0xFFFFFFFFU, 0x55AA5480U); +/*##################################################################### */ - Reserved. Return zeroes on reads. - PSU_DDR_PHY_PGCR3_RESERVED_8 0x0 + /* + * Register : PGCR5 @ 0XFD080024 - Controls DDL Bypass Modes - PSU_DDR_PHY_PGCR3_DDLBYPMODE 0x2 + * Frequency B Ratio Term + * PSU_DDR_PHY_PGCR5_FRQBT 0x1 - IO Loop-Back Select - PSU_DDR_PHY_PGCR3_IOLB 0x0 + * Frequency A Ratio Term + * PSU_DDR_PHY_PGCR5_FRQAT 0x1 - AC Receive FIFO Read Mode - PSU_DDR_PHY_PGCR3_RDMODE 0x0 + * DFI Disconnect Time Period + * PSU_DDR_PHY_PGCR5_DISCNPERIOD 0x0 - Read FIFO Reset Disable - PSU_DDR_PHY_PGCR3_DISRST 0x0 + * Receiver bias core side control + * PSU_DDR_PHY_PGCR5_VREF_RBCTRL 0xf - Clock Level when Clock Gating - PSU_DDR_PHY_PGCR3_CLKLEVEL 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_PGCR5_RESERVED_3 0x0 - PHY General Configuration Register 3 - (OFFSET, MASK, VALUE) (0XFD08001C, 0xFFFFFFFFU ,0x55AA5480U) - RegMask = (DDR_PHY_PGCR3_CKNEN_MASK | DDR_PHY_PGCR3_CKEN_MASK | DDR_PHY_PGCR3_RESERVED_15_MASK | DDR_PHY_PGCR3_GATEACRDCLK_MASK | DDR_PHY_PGCR3_GATEACDDRCLK_MASK | DDR_PHY_PGCR3_GATEACCTLCLK_MASK | DDR_PHY_PGCR3_RESERVED_8_MASK | DDR_PHY_PGCR3_DDLBYPMODE_MASK | DDR_PHY_PGCR3_IOLB_MASK | DDR_PHY_PGCR3_RDMODE_MASK | DDR_PHY_PGCR3_DISRST_MASK | DDR_PHY_PGCR3_CLKLEVEL_MASK | 0 ); + * Internal VREF generator REFSEL ragne select + * PSU_DDR_PHY_PGCR5_DXREFISELRANGE 0x1 - RegVal = ((0x00000055U << DDR_PHY_PGCR3_CKNEN_SHIFT - | 0x000000AAU << DDR_PHY_PGCR3_CKEN_SHIFT - | 0x00000000U << DDR_PHY_PGCR3_RESERVED_15_SHIFT - | 0x00000002U << DDR_PHY_PGCR3_GATEACRDCLK_SHIFT - | 0x00000002U << DDR_PHY_PGCR3_GATEACDDRCLK_SHIFT - | 0x00000002U << DDR_PHY_PGCR3_GATEACCTLCLK_SHIFT - | 0x00000000U << DDR_PHY_PGCR3_RESERVED_8_SHIFT - | 0x00000002U << DDR_PHY_PGCR3_DDLBYPMODE_SHIFT - | 0x00000000U << DDR_PHY_PGCR3_IOLB_SHIFT - | 0x00000000U << DDR_PHY_PGCR3_RDMODE_SHIFT - | 0x00000000U << DDR_PHY_PGCR3_DISRST_SHIFT - | 0x00000000U << DDR_PHY_PGCR3_CLKLEVEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_PGCR3_OFFSET ,0xFFFFFFFFU ,0x55AA5480U); - /*############################################################################################################################ */ + * DDL Page Read Write select + * PSU_DDR_PHY_PGCR5_DDLPGACT 0x0 - /*Register : PGCR5 @ 0XFD080024

+ * DDL Page Read Write select + * PSU_DDR_PHY_PGCR5_DDLPGRW 0x0 - Frequency B Ratio Term - PSU_DDR_PHY_PGCR5_FRQBT 0x1 + * PHY General Configuration Register 5 + * (OFFSET, MASK, VALUE) (0XFD080024, 0xFFFFFFFFU ,0x010100F4U) + */ + PSU_Mask_Write(DDR_PHY_PGCR5_OFFSET, 0xFFFFFFFFU, 0x010100F4U); +/*##################################################################### */ - Frequency A Ratio Term - PSU_DDR_PHY_PGCR5_FRQAT 0x1 + /* + * Register : PTR0 @ 0XFD080040 - DFI Disconnect Time Period - PSU_DDR_PHY_PGCR5_DISCNPERIOD 0x0 + * PLL Power-Down Time + * PSU_DDR_PHY_PTR0_TPLLPD 0x56 - Receiver bias core side control - PSU_DDR_PHY_PGCR5_VREF_RBCTRL 0xf + * PLL Gear Shift Time + * PSU_DDR_PHY_PTR0_TPLLGS 0x2155 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_PGCR5_RESERVED_3 0x0 + * PHY Reset Time + * PSU_DDR_PHY_PTR0_TPHYRST 0x10 - Internal VREF generator REFSEL ragne select - PSU_DDR_PHY_PGCR5_DXREFISELRANGE 0x1 + * PHY Timing Register 0 + * (OFFSET, MASK, VALUE) (0XFD080040, 0xFFFFFFFFU ,0x0AC85550U) + */ + PSU_Mask_Write(DDR_PHY_PTR0_OFFSET, 0xFFFFFFFFU, 0x0AC85550U); +/*##################################################################### */ - DDL Page Read Write select - PSU_DDR_PHY_PGCR5_DDLPGACT 0x0 + /* + * Register : PTR1 @ 0XFD080044 - DDL Page Read Write select - PSU_DDR_PHY_PGCR5_DDLPGRW 0x0 + * PLL Lock Time + * PSU_DDR_PHY_PTR1_TPLLLOCK 0x4141 - PHY General Configuration Register 5 - (OFFSET, MASK, VALUE) (0XFD080024, 0xFFFFFFFFU ,0x010100F4U) - RegMask = (DDR_PHY_PGCR5_FRQBT_MASK | DDR_PHY_PGCR5_FRQAT_MASK | DDR_PHY_PGCR5_DISCNPERIOD_MASK | DDR_PHY_PGCR5_VREF_RBCTRL_MASK | DDR_PHY_PGCR5_RESERVED_3_MASK | DDR_PHY_PGCR5_DXREFISELRANGE_MASK | DDR_PHY_PGCR5_DDLPGACT_MASK | DDR_PHY_PGCR5_DDLPGRW_MASK | 0 ); + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_PTR1_RESERVED_15_13 0x0 - RegVal = ((0x00000001U << DDR_PHY_PGCR5_FRQBT_SHIFT - | 0x00000001U << DDR_PHY_PGCR5_FRQAT_SHIFT - | 0x00000000U << DDR_PHY_PGCR5_DISCNPERIOD_SHIFT - | 0x0000000FU << DDR_PHY_PGCR5_VREF_RBCTRL_SHIFT - | 0x00000000U << DDR_PHY_PGCR5_RESERVED_3_SHIFT - | 0x00000001U << DDR_PHY_PGCR5_DXREFISELRANGE_SHIFT - | 0x00000000U << DDR_PHY_PGCR5_DDLPGACT_SHIFT - | 0x00000000U << DDR_PHY_PGCR5_DDLPGRW_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_PGCR5_OFFSET ,0xFFFFFFFFU ,0x010100F4U); - /*############################################################################################################################ */ + * PLL Reset Time + * PSU_DDR_PHY_PTR1_TPLLRST 0xaff - /*Register : PTR0 @ 0XFD080040

+ * PHY Timing Register 1 + * (OFFSET, MASK, VALUE) (0XFD080044, 0xFFFFFFFFU ,0x41410AFFU) + */ + PSU_Mask_Write(DDR_PHY_PTR1_OFFSET, 0xFFFFFFFFU, 0x41410AFFU); +/*##################################################################### */ - PLL Power-Down Time - PSU_DDR_PHY_PTR0_TPLLPD 0x2f0 + /* + * Register : PLLCR0 @ 0XFD080068 - PLL Gear Shift Time - PSU_DDR_PHY_PTR0_TPLLGS 0x60 + * PLL Bypass + * PSU_DDR_PHY_PLLCR0_PLLBYP 0x0 - PHY Reset Time - PSU_DDR_PHY_PTR0_TPHYRST 0x10 + * PLL Reset + * PSU_DDR_PHY_PLLCR0_PLLRST 0x0 - PHY Timing Register 0 - (OFFSET, MASK, VALUE) (0XFD080040, 0xFFFFFFFFU ,0x5E001810U) - RegMask = (DDR_PHY_PTR0_TPLLPD_MASK | DDR_PHY_PTR0_TPLLGS_MASK | DDR_PHY_PTR0_TPHYRST_MASK | 0 ); + * PLL Power Down + * PSU_DDR_PHY_PLLCR0_PLLPD 0x0 - RegVal = ((0x000002F0U << DDR_PHY_PTR0_TPLLPD_SHIFT - | 0x00000060U << DDR_PHY_PTR0_TPLLGS_SHIFT - | 0x00000010U << DDR_PHY_PTR0_TPHYRST_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_PTR0_OFFSET ,0xFFFFFFFFU ,0x5E001810U); - /*############################################################################################################################ */ + * Reference Stop Mode + * PSU_DDR_PHY_PLLCR0_RSTOPM 0x0 - /*Register : PTR1 @ 0XFD080044

+ * PLL Frequency Select + * PSU_DDR_PHY_PLLCR0_FRQSEL 0x1 - PLL Lock Time - PSU_DDR_PHY_PTR1_TPLLLOCK 0x80 + * Relock Mode + * PSU_DDR_PHY_PLLCR0_RLOCKM 0x0 - Reserved. Returns zeroes on reads. - PSU_DDR_PHY_PTR1_RESERVED_15_13 0x0 + * Charge Pump Proportional Current Control + * PSU_DDR_PHY_PLLCR0_CPPC 0x8 - PLL Reset Time - PSU_DDR_PHY_PTR1_TPLLRST 0x5f0 - - PHY Timing Register 1 - (OFFSET, MASK, VALUE) (0XFD080044, 0xFFFFFFFFU ,0x008005F0U) - RegMask = (DDR_PHY_PTR1_TPLLLOCK_MASK | DDR_PHY_PTR1_RESERVED_15_13_MASK | DDR_PHY_PTR1_TPLLRST_MASK | 0 ); + * Charge Pump Integrating Current Control + * PSU_DDR_PHY_PLLCR0_CPIC 0x0 - RegVal = ((0x00000080U << DDR_PHY_PTR1_TPLLLOCK_SHIFT - | 0x00000000U << DDR_PHY_PTR1_RESERVED_15_13_SHIFT - | 0x000005F0U << DDR_PHY_PTR1_TPLLRST_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_PTR1_OFFSET ,0xFFFFFFFFU ,0x008005F0U); - /*############################################################################################################################ */ + * Gear Shift + * PSU_DDR_PHY_PLLCR0_GSHIFT 0x0 - /*Register : DSGCR @ 0XFD080090

+ * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_PLLCR0_RESERVED_11_9 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DSGCR_RESERVED_31_28 0x0 + * Analog Test Enable + * PSU_DDR_PHY_PLLCR0_ATOEN 0x0 - When RDBI enabled, this bit is used to select RDBI CL calculation, if it is 1b1, calculation will use RDBICL, otherwise use d - fault calculation. - PSU_DDR_PHY_DSGCR_RDBICLSEL 0x0 + * Analog Test Control + * PSU_DDR_PHY_PLLCR0_ATC 0x0 - When RDBI enabled, if RDBICLSEL is asserted, RDBI CL adjust using this value. - PSU_DDR_PHY_DSGCR_RDBICL 0x2 + * Digital Test Control + * PSU_DDR_PHY_PLLCR0_DTC 0x0 - PHY Impedance Update Enable - PSU_DDR_PHY_DSGCR_PHYZUEN 0x1 + * PLL Control Register 0 (Type B PLL Only) + * (OFFSET, MASK, VALUE) (0XFD080068, 0xFFFFFFFFU ,0x01100000U) + */ + PSU_Mask_Write(DDR_PHY_PLLCR0_OFFSET, 0xFFFFFFFFU, 0x01100000U); +/*##################################################################### */ - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DSGCR_RESERVED_22 0x0 + /* + * Register : DSGCR @ 0XFD080090 - SDRAM Reset Output Enable - PSU_DDR_PHY_DSGCR_RSTOE 0x1 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DSGCR_RESERVED_31_28 0x0 - Single Data Rate Mode - PSU_DDR_PHY_DSGCR_SDRMODE 0x0 + * When RDBI enabled, this bit is used to select RDBI CL calculation, if it + * is 1b1, calculation will use RDBICL, otherwise use default calculation. + * PSU_DDR_PHY_DSGCR_RDBICLSEL 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DSGCR_RESERVED_18 0x0 + * When RDBI enabled, if RDBICLSEL is asserted, RDBI CL adjust using this v + * alue. + * PSU_DDR_PHY_DSGCR_RDBICL 0x2 - ATO Analog Test Enable - PSU_DDR_PHY_DSGCR_ATOAE 0x0 + * PHY Impedance Update Enable + * PSU_DDR_PHY_DSGCR_PHYZUEN 0x1 - DTO Output Enable - PSU_DDR_PHY_DSGCR_DTOOE 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DSGCR_RESERVED_22 0x0 - DTO I/O Mode - PSU_DDR_PHY_DSGCR_DTOIOM 0x0 + * SDRAM Reset Output Enable + * PSU_DDR_PHY_DSGCR_RSTOE 0x1 - DTO Power Down Receiver - PSU_DDR_PHY_DSGCR_DTOPDR 0x1 + * Single Data Rate Mode + * PSU_DDR_PHY_DSGCR_SDRMODE 0x0 - Reserved. Return zeroes on reads - PSU_DDR_PHY_DSGCR_RESERVED_13 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DSGCR_RESERVED_18 0x0 - DTO On-Die Termination - PSU_DDR_PHY_DSGCR_DTOODT 0x0 + * ATO Analog Test Enable + * PSU_DDR_PHY_DSGCR_ATOAE 0x0 - PHY Update Acknowledge Delay - PSU_DDR_PHY_DSGCR_PUAD 0x4 + * DTO Output Enable + * PSU_DDR_PHY_DSGCR_DTOOE 0x0 - Controller Update Acknowledge Enable - PSU_DDR_PHY_DSGCR_CUAEN 0x1 + * DTO I/O Mode + * PSU_DDR_PHY_DSGCR_DTOIOM 0x0 - Reserved. Return zeroes on reads - PSU_DDR_PHY_DSGCR_RESERVED_4_3 0x0 + * DTO Power Down Receiver + * PSU_DDR_PHY_DSGCR_DTOPDR 0x1 - Controller Impedance Update Enable - PSU_DDR_PHY_DSGCR_CTLZUEN 0x0 + * Reserved. Return zeroes on reads + * PSU_DDR_PHY_DSGCR_RESERVED_13 0x0 - Reserved. Return zeroes on reads - PSU_DDR_PHY_DSGCR_RESERVED_1 0x0 + * DTO On-Die Termination + * PSU_DDR_PHY_DSGCR_DTOODT 0x0 - PHY Update Request Enable - PSU_DDR_PHY_DSGCR_PUREN 0x1 + * PHY Update Acknowledge Delay + * PSU_DDR_PHY_DSGCR_PUAD 0x5 - DDR System General Configuration Register - (OFFSET, MASK, VALUE) (0XFD080090, 0xFFFFFFFFU ,0x02A04121U) - RegMask = (DDR_PHY_DSGCR_RESERVED_31_28_MASK | DDR_PHY_DSGCR_RDBICLSEL_MASK | DDR_PHY_DSGCR_RDBICL_MASK | DDR_PHY_DSGCR_PHYZUEN_MASK | DDR_PHY_DSGCR_RESERVED_22_MASK | DDR_PHY_DSGCR_RSTOE_MASK | DDR_PHY_DSGCR_SDRMODE_MASK | DDR_PHY_DSGCR_RESERVED_18_MASK | DDR_PHY_DSGCR_ATOAE_MASK | DDR_PHY_DSGCR_DTOOE_MASK | DDR_PHY_DSGCR_DTOIOM_MASK | DDR_PHY_DSGCR_DTOPDR_MASK | DDR_PHY_DSGCR_RESERVED_13_MASK | DDR_PHY_DSGCR_DTOODT_MASK | DDR_PHY_DSGCR_PUAD_MASK | DDR_PHY_DSGCR_CUAEN_MASK | DDR_PHY_DSGCR_RESERVED_4_3_MASK | DDR_PHY_DSGCR_CTLZUEN_MASK | DDR_PHY_DSGCR_RESERVED_1_MASK | DDR_PHY_DSGCR_PUREN_MASK | 0 ); + * Controller Update Acknowledge Enable + * PSU_DDR_PHY_DSGCR_CUAEN 0x1 - RegVal = ((0x00000000U << DDR_PHY_DSGCR_RESERVED_31_28_SHIFT - | 0x00000000U << DDR_PHY_DSGCR_RDBICLSEL_SHIFT - | 0x00000002U << DDR_PHY_DSGCR_RDBICL_SHIFT - | 0x00000001U << DDR_PHY_DSGCR_PHYZUEN_SHIFT - | 0x00000000U << DDR_PHY_DSGCR_RESERVED_22_SHIFT - | 0x00000001U << DDR_PHY_DSGCR_RSTOE_SHIFT - | 0x00000000U << DDR_PHY_DSGCR_SDRMODE_SHIFT - | 0x00000000U << DDR_PHY_DSGCR_RESERVED_18_SHIFT - | 0x00000000U << DDR_PHY_DSGCR_ATOAE_SHIFT - | 0x00000000U << DDR_PHY_DSGCR_DTOOE_SHIFT - | 0x00000000U << DDR_PHY_DSGCR_DTOIOM_SHIFT - | 0x00000001U << DDR_PHY_DSGCR_DTOPDR_SHIFT - | 0x00000000U << DDR_PHY_DSGCR_RESERVED_13_SHIFT - | 0x00000000U << DDR_PHY_DSGCR_DTOODT_SHIFT - | 0x00000004U << DDR_PHY_DSGCR_PUAD_SHIFT - | 0x00000001U << DDR_PHY_DSGCR_CUAEN_SHIFT - | 0x00000000U << DDR_PHY_DSGCR_RESERVED_4_3_SHIFT - | 0x00000000U << DDR_PHY_DSGCR_CTLZUEN_SHIFT - | 0x00000000U << DDR_PHY_DSGCR_RESERVED_1_SHIFT - | 0x00000001U << DDR_PHY_DSGCR_PUREN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DSGCR_OFFSET ,0xFFFFFFFFU ,0x02A04121U); - /*############################################################################################################################ */ + * Reserved. Return zeroes on reads + * PSU_DDR_PHY_DSGCR_RESERVED_4_3 0x0 - /*Register : DCR @ 0XFD080100

+ * Controller Impedance Update Enable + * PSU_DDR_PHY_DSGCR_CTLZUEN 0x0 - DDR4 Gear Down Timing. - PSU_DDR_PHY_DCR_GEARDN 0x0 + * Reserved. Return zeroes on reads + * PSU_DDR_PHY_DSGCR_RESERVED_1 0x0 - Un-used Bank Group - PSU_DDR_PHY_DCR_UBG 0x0 + * PHY Update Request Enable + * PSU_DDR_PHY_DSGCR_PUREN 0x1 - Un-buffered DIMM Address Mirroring - PSU_DDR_PHY_DCR_UDIMM 0x0 + * DDR System General Configuration Register + * (OFFSET, MASK, VALUE) (0XFD080090, 0xFFFFFFFFU ,0x02A04161U) + */ + PSU_Mask_Write(DDR_PHY_DSGCR_OFFSET, 0xFFFFFFFFU, 0x02A04161U); +/*##################################################################### */ - DDR 2T Timing - PSU_DDR_PHY_DCR_DDR2T 0x0 + /* + * Register : GPR0 @ 0XFD0800C0 - No Simultaneous Rank Access - PSU_DDR_PHY_DCR_NOSRA 0x1 + * General Purpose Register 0 + * PSU_DDR_PHY_GPR0_GPR0 0xd3 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DCR_RESERVED_26_18 0x0 + * General Purpose Register 0 + * (OFFSET, MASK, VALUE) (0XFD0800C0, 0xFFFFFFFFU ,0x000000D3U) + */ + PSU_Mask_Write(DDR_PHY_GPR0_OFFSET, 0xFFFFFFFFU, 0x000000D3U); +/*##################################################################### */ - Byte Mask - PSU_DDR_PHY_DCR_BYTEMASK 0x1 + /* + * Register : DCR @ 0XFD080100 - DDR Type - PSU_DDR_PHY_DCR_DDRTYPE 0x0 + * DDR4 Gear Down Timing. + * PSU_DDR_PHY_DCR_GEARDN 0x0 - Multi-Purpose Register (MPR) DQ (DDR3 Only) - PSU_DDR_PHY_DCR_MPRDQ 0x0 + * Un-used Bank Group + * PSU_DDR_PHY_DCR_UBG 0x0 - Primary DQ (DDR3 Only) - PSU_DDR_PHY_DCR_PDQ 0x0 + * Un-buffered DIMM Address Mirroring + * PSU_DDR_PHY_DCR_UDIMM 0x0 - DDR 8-Bank - PSU_DDR_PHY_DCR_DDR8BNK 0x1 + * DDR 2T Timing + * PSU_DDR_PHY_DCR_DDR2T 0x0 - DDR Mode - PSU_DDR_PHY_DCR_DDRMD 0x4 + * No Simultaneous Rank Access + * PSU_DDR_PHY_DCR_NOSRA 0x1 - DRAM Configuration Register - (OFFSET, MASK, VALUE) (0XFD080100, 0xFFFFFFFFU ,0x0800040CU) - RegMask = (DDR_PHY_DCR_GEARDN_MASK | DDR_PHY_DCR_UBG_MASK | DDR_PHY_DCR_UDIMM_MASK | DDR_PHY_DCR_DDR2T_MASK | DDR_PHY_DCR_NOSRA_MASK | DDR_PHY_DCR_RESERVED_26_18_MASK | DDR_PHY_DCR_BYTEMASK_MASK | DDR_PHY_DCR_DDRTYPE_MASK | DDR_PHY_DCR_MPRDQ_MASK | DDR_PHY_DCR_PDQ_MASK | DDR_PHY_DCR_DDR8BNK_MASK | DDR_PHY_DCR_DDRMD_MASK | 0 ); + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DCR_RESERVED_26_18 0x0 - RegVal = ((0x00000000U << DDR_PHY_DCR_GEARDN_SHIFT - | 0x00000000U << DDR_PHY_DCR_UBG_SHIFT - | 0x00000000U << DDR_PHY_DCR_UDIMM_SHIFT - | 0x00000000U << DDR_PHY_DCR_DDR2T_SHIFT - | 0x00000001U << DDR_PHY_DCR_NOSRA_SHIFT - | 0x00000000U << DDR_PHY_DCR_RESERVED_26_18_SHIFT - | 0x00000001U << DDR_PHY_DCR_BYTEMASK_SHIFT - | 0x00000000U << DDR_PHY_DCR_DDRTYPE_SHIFT - | 0x00000000U << DDR_PHY_DCR_MPRDQ_SHIFT - | 0x00000000U << DDR_PHY_DCR_PDQ_SHIFT - | 0x00000001U << DDR_PHY_DCR_DDR8BNK_SHIFT - | 0x00000004U << DDR_PHY_DCR_DDRMD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DCR_OFFSET ,0xFFFFFFFFU ,0x0800040CU); - /*############################################################################################################################ */ - - /*Register : DTPR0 @ 0XFD080110

+ * Byte Mask + * PSU_DDR_PHY_DCR_BYTEMASK 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR0_RESERVED_31_29 0x0 + * DDR Type + * PSU_DDR_PHY_DCR_DDRTYPE 0x0 - Activate to activate command delay (different banks) - PSU_DDR_PHY_DTPR0_TRRD 0x6 + * Multi-Purpose Register (MPR) DQ (DDR3 Only) + * PSU_DDR_PHY_DCR_MPRDQ 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR0_RESERVED_23 0x0 + * Primary DQ (DDR3 Only) + * PSU_DDR_PHY_DCR_PDQ 0x0 - Activate to precharge command delay - PSU_DDR_PHY_DTPR0_TRAS 0x24 + * DDR 8-Bank + * PSU_DDR_PHY_DCR_DDR8BNK 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR0_RESERVED_15 0x0 - - Precharge command period - PSU_DDR_PHY_DTPR0_TRP 0xf - - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR0_RESERVED_7_5 0x0 - - Internal read to precharge command delay - PSU_DDR_PHY_DTPR0_TRTP 0x9 - - DRAM Timing Parameters Register 0 - (OFFSET, MASK, VALUE) (0XFD080110, 0xFFFFFFFFU ,0x06240F09U) - RegMask = (DDR_PHY_DTPR0_RESERVED_31_29_MASK | DDR_PHY_DTPR0_TRRD_MASK | DDR_PHY_DTPR0_RESERVED_23_MASK | DDR_PHY_DTPR0_TRAS_MASK | DDR_PHY_DTPR0_RESERVED_15_MASK | DDR_PHY_DTPR0_TRP_MASK | DDR_PHY_DTPR0_RESERVED_7_5_MASK | DDR_PHY_DTPR0_TRTP_MASK | 0 ); + * DDR Mode + * PSU_DDR_PHY_DCR_DDRMD 0x4 - RegVal = ((0x00000000U << DDR_PHY_DTPR0_RESERVED_31_29_SHIFT - | 0x00000006U << DDR_PHY_DTPR0_TRRD_SHIFT - | 0x00000000U << DDR_PHY_DTPR0_RESERVED_23_SHIFT - | 0x00000024U << DDR_PHY_DTPR0_TRAS_SHIFT - | 0x00000000U << DDR_PHY_DTPR0_RESERVED_15_SHIFT - | 0x0000000FU << DDR_PHY_DTPR0_TRP_SHIFT - | 0x00000000U << DDR_PHY_DTPR0_RESERVED_7_5_SHIFT - | 0x00000009U << DDR_PHY_DTPR0_TRTP_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DTPR0_OFFSET ,0xFFFFFFFFU ,0x06240F09U); - /*############################################################################################################################ */ + * DRAM Configuration Register + * (OFFSET, MASK, VALUE) (0XFD080100, 0xFFFFFFFFU ,0x0800040CU) + */ + PSU_Mask_Write(DDR_PHY_DCR_OFFSET, 0xFFFFFFFFU, 0x0800040CU); +/*##################################################################### */ - /*Register : DTPR1 @ 0XFD080114

+ /* + * Register : DTPR0 @ 0XFD080110 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR1_RESERVED_31 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR0_RESERVED_31_29 0x0 - Minimum delay from when write leveling mode is programmed to the first DQS/DQS# rising edge. - PSU_DDR_PHY_DTPR1_TWLMRD 0x28 + * Activate to activate command delay (different banks) + * PSU_DDR_PHY_DTPR0_TRRD 0x6 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR1_RESERVED_23 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR0_RESERVED_23 0x0 - 4-bank activate period - PSU_DDR_PHY_DTPR1_TFAW 0x18 + * Activate to precharge command delay + * PSU_DDR_PHY_DTPR0_TRAS 0x24 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR1_RESERVED_15_11 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR0_RESERVED_15 0x0 - Load mode update delay (DDR4 and DDR3 only) - PSU_DDR_PHY_DTPR1_TMOD 0x7 + * Precharge command period + * PSU_DDR_PHY_DTPR0_TRP 0xf - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR1_RESERVED_7_5 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR0_RESERVED_7_5 0x0 - Load mode cycle time - PSU_DDR_PHY_DTPR1_TMRD 0x8 + * Internal read to precharge command delay + * PSU_DDR_PHY_DTPR0_TRTP 0x8 - DRAM Timing Parameters Register 1 - (OFFSET, MASK, VALUE) (0XFD080114, 0xFFFFFFFFU ,0x28180708U) - RegMask = (DDR_PHY_DTPR1_RESERVED_31_MASK | DDR_PHY_DTPR1_TWLMRD_MASK | DDR_PHY_DTPR1_RESERVED_23_MASK | DDR_PHY_DTPR1_TFAW_MASK | DDR_PHY_DTPR1_RESERVED_15_11_MASK | DDR_PHY_DTPR1_TMOD_MASK | DDR_PHY_DTPR1_RESERVED_7_5_MASK | DDR_PHY_DTPR1_TMRD_MASK | 0 ); + * DRAM Timing Parameters Register 0 + * (OFFSET, MASK, VALUE) (0XFD080110, 0xFFFFFFFFU ,0x06240F08U) + */ + PSU_Mask_Write(DDR_PHY_DTPR0_OFFSET, 0xFFFFFFFFU, 0x06240F08U); +/*##################################################################### */ - RegVal = ((0x00000000U << DDR_PHY_DTPR1_RESERVED_31_SHIFT - | 0x00000028U << DDR_PHY_DTPR1_TWLMRD_SHIFT - | 0x00000000U << DDR_PHY_DTPR1_RESERVED_23_SHIFT - | 0x00000018U << DDR_PHY_DTPR1_TFAW_SHIFT - | 0x00000000U << DDR_PHY_DTPR1_RESERVED_15_11_SHIFT - | 0x00000007U << DDR_PHY_DTPR1_TMOD_SHIFT - | 0x00000000U << DDR_PHY_DTPR1_RESERVED_7_5_SHIFT - | 0x00000008U << DDR_PHY_DTPR1_TMRD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DTPR1_OFFSET ,0xFFFFFFFFU ,0x28180708U); - /*############################################################################################################################ */ + /* + * Register : DTPR1 @ 0XFD080114 - /*Register : DTPR2 @ 0XFD080118

+ * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR1_RESERVED_31 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR2_RESERVED_31_29 0x0 + * Minimum delay from when write leveling mode is programmed to the first D + * QS/DQS# rising edge. + * PSU_DDR_PHY_DTPR1_TWLMRD 0x28 - Read to Write command delay. Valid values are - PSU_DDR_PHY_DTPR2_TRTW 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR1_RESERVED_23 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR2_RESERVED_27_25 0x0 + * 4-bank activate period + * PSU_DDR_PHY_DTPR1_TFAW 0x20 - Read to ODT delay (DDR3 only) - PSU_DDR_PHY_DTPR2_TRTODT 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR1_RESERVED_15_11 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR2_RESERVED_23_20 0x0 + * Load mode update delay (DDR4 and DDR3 only) + * PSU_DDR_PHY_DTPR1_TMOD 0x0 - CKE minimum pulse width - PSU_DDR_PHY_DTPR2_TCKE 0x8 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR1_RESERVED_7_5 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR2_RESERVED_15_10 0x0 + * Load mode cycle time + * PSU_DDR_PHY_DTPR1_TMRD 0x8 - Self refresh exit delay - PSU_DDR_PHY_DTPR2_TXS 0x200 + * DRAM Timing Parameters Register 1 + * (OFFSET, MASK, VALUE) (0XFD080114, 0xFFFFFFFFU ,0x28200008U) + */ + PSU_Mask_Write(DDR_PHY_DTPR1_OFFSET, 0xFFFFFFFFU, 0x28200008U); +/*##################################################################### */ - DRAM Timing Parameters Register 2 - (OFFSET, MASK, VALUE) (0XFD080118, 0xFFFFFFFFU ,0x00080200U) - RegMask = (DDR_PHY_DTPR2_RESERVED_31_29_MASK | DDR_PHY_DTPR2_TRTW_MASK | DDR_PHY_DTPR2_RESERVED_27_25_MASK | DDR_PHY_DTPR2_TRTODT_MASK | DDR_PHY_DTPR2_RESERVED_23_20_MASK | DDR_PHY_DTPR2_TCKE_MASK | DDR_PHY_DTPR2_RESERVED_15_10_MASK | DDR_PHY_DTPR2_TXS_MASK | 0 ); + /* + * Register : DTPR2 @ 0XFD080118 - RegVal = ((0x00000000U << DDR_PHY_DTPR2_RESERVED_31_29_SHIFT - | 0x00000000U << DDR_PHY_DTPR2_TRTW_SHIFT - | 0x00000000U << DDR_PHY_DTPR2_RESERVED_27_25_SHIFT - | 0x00000000U << DDR_PHY_DTPR2_TRTODT_SHIFT - | 0x00000000U << DDR_PHY_DTPR2_RESERVED_23_20_SHIFT - | 0x00000008U << DDR_PHY_DTPR2_TCKE_SHIFT - | 0x00000000U << DDR_PHY_DTPR2_RESERVED_15_10_SHIFT - | 0x00000200U << DDR_PHY_DTPR2_TXS_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DTPR2_OFFSET ,0xFFFFFFFFU ,0x00080200U); - /*############################################################################################################################ */ + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR2_RESERVED_31_29 0x0 - /*Register : DTPR3 @ 0XFD08011C

+ * Read to Write command delay. Valid values are + * PSU_DDR_PHY_DTPR2_TRTW 0x0 - ODT turn-off delay extension - PSU_DDR_PHY_DTPR3_TOFDX 0x4 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR2_RESERVED_27_25 0x0 - Read to read and write to write command delay - PSU_DDR_PHY_DTPR3_TCCD 0x0 + * Read to ODT delay (DDR3 only) + * PSU_DDR_PHY_DTPR2_TRTODT 0x0 - DLL locking time - PSU_DDR_PHY_DTPR3_TDLLK 0x300 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR2_RESERVED_23_20 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR3_RESERVED_15_12 0x0 + * CKE minimum pulse width + * PSU_DDR_PHY_DTPR2_TCKE 0x7 - Maximum DQS output access time from CK/CK# (LPDDR2/3 only) - PSU_DDR_PHY_DTPR3_TDQSCKMAX 0x8 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR2_RESERVED_15_10 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR3_RESERVED_7_3 0x0 + * Self refresh exit delay + * PSU_DDR_PHY_DTPR2_TXS 0x300 - DQS output access time from CK/CK# (LPDDR2/3 only) - PSU_DDR_PHY_DTPR3_TDQSCK 0x0 + * DRAM Timing Parameters Register 2 + * (OFFSET, MASK, VALUE) (0XFD080118, 0xFFFFFFFFU ,0x00070300U) + */ + PSU_Mask_Write(DDR_PHY_DTPR2_OFFSET, 0xFFFFFFFFU, 0x00070300U); +/*##################################################################### */ - DRAM Timing Parameters Register 3 - (OFFSET, MASK, VALUE) (0XFD08011C, 0xFFFFFFFFU ,0x83000800U) - RegMask = (DDR_PHY_DTPR3_TOFDX_MASK | DDR_PHY_DTPR3_TCCD_MASK | DDR_PHY_DTPR3_TDLLK_MASK | DDR_PHY_DTPR3_RESERVED_15_12_MASK | DDR_PHY_DTPR3_TDQSCKMAX_MASK | DDR_PHY_DTPR3_RESERVED_7_3_MASK | DDR_PHY_DTPR3_TDQSCK_MASK | 0 ); + /* + * Register : DTPR3 @ 0XFD08011C - RegVal = ((0x00000004U << DDR_PHY_DTPR3_TOFDX_SHIFT - | 0x00000000U << DDR_PHY_DTPR3_TCCD_SHIFT - | 0x00000300U << DDR_PHY_DTPR3_TDLLK_SHIFT - | 0x00000000U << DDR_PHY_DTPR3_RESERVED_15_12_SHIFT - | 0x00000008U << DDR_PHY_DTPR3_TDQSCKMAX_SHIFT - | 0x00000000U << DDR_PHY_DTPR3_RESERVED_7_3_SHIFT - | 0x00000000U << DDR_PHY_DTPR3_TDQSCK_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DTPR3_OFFSET ,0xFFFFFFFFU ,0x83000800U); - /*############################################################################################################################ */ + * ODT turn-off delay extension + * PSU_DDR_PHY_DTPR3_TOFDX 0x4 - /*Register : DTPR4 @ 0XFD080120

+ * Read to read and write to write command delay + * PSU_DDR_PHY_DTPR3_TCCD 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR4_RESERVED_31_30 0x0 + * DLL locking time + * PSU_DDR_PHY_DTPR3_TDLLK 0x300 - ODT turn-on/turn-off delays (DDR2 only) - PSU_DDR_PHY_DTPR4_TAOND_TAOFD 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR3_RESERVED_15_12 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR4_RESERVED_27_26 0x0 + * Maximum DQS output access time from CK/CK# (LPDDR2/3 only) + * PSU_DDR_PHY_DTPR3_TDQSCKMAX 0x8 - Refresh-to-Refresh - PSU_DDR_PHY_DTPR4_TRFC 0x116 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR3_RESERVED_7_3 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR4_RESERVED_15_14 0x0 + * DQS output access time from CK/CK# (LPDDR2/3 only) + * PSU_DDR_PHY_DTPR3_TDQSCK 0x0 - Write leveling output delay - PSU_DDR_PHY_DTPR4_TWLO 0x2b + * DRAM Timing Parameters Register 3 + * (OFFSET, MASK, VALUE) (0XFD08011C, 0xFFFFFFFFU ,0x83000800U) + */ + PSU_Mask_Write(DDR_PHY_DTPR3_OFFSET, 0xFFFFFFFFU, 0x83000800U); +/*##################################################################### */ - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR4_RESERVED_7_5 0x0 + /* + * Register : DTPR4 @ 0XFD080120 - Power down exit delay - PSU_DDR_PHY_DTPR4_TXP 0x8 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR4_RESERVED_31_30 0x0 - DRAM Timing Parameters Register 4 - (OFFSET, MASK, VALUE) (0XFD080120, 0xFFFFFFFFU ,0x01162B08U) - RegMask = (DDR_PHY_DTPR4_RESERVED_31_30_MASK | DDR_PHY_DTPR4_TAOND_TAOFD_MASK | DDR_PHY_DTPR4_RESERVED_27_26_MASK | DDR_PHY_DTPR4_TRFC_MASK | DDR_PHY_DTPR4_RESERVED_15_14_MASK | DDR_PHY_DTPR4_TWLO_MASK | DDR_PHY_DTPR4_RESERVED_7_5_MASK | DDR_PHY_DTPR4_TXP_MASK | 0 ); + * ODT turn-on/turn-off delays (DDR2 only) + * PSU_DDR_PHY_DTPR4_TAOND_TAOFD 0x0 - RegVal = ((0x00000000U << DDR_PHY_DTPR4_RESERVED_31_30_SHIFT - | 0x00000000U << DDR_PHY_DTPR4_TAOND_TAOFD_SHIFT - | 0x00000000U << DDR_PHY_DTPR4_RESERVED_27_26_SHIFT - | 0x00000116U << DDR_PHY_DTPR4_TRFC_SHIFT - | 0x00000000U << DDR_PHY_DTPR4_RESERVED_15_14_SHIFT - | 0x0000002BU << DDR_PHY_DTPR4_TWLO_SHIFT - | 0x00000000U << DDR_PHY_DTPR4_RESERVED_7_5_SHIFT - | 0x00000008U << DDR_PHY_DTPR4_TXP_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DTPR4_OFFSET ,0xFFFFFFFFU ,0x01162B08U); - /*############################################################################################################################ */ + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR4_RESERVED_27_26 0x0 - /*Register : DTPR5 @ 0XFD080124

+ * Refresh-to-Refresh + * PSU_DDR_PHY_DTPR4_TRFC 0x116 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR5_RESERVED_31_24 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR4_RESERVED_15_14 0x0 - Activate to activate command delay (same bank) - PSU_DDR_PHY_DTPR5_TRC 0x32 + * Write leveling output delay + * PSU_DDR_PHY_DTPR4_TWLO 0x2b - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR5_RESERVED_15 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR4_RESERVED_7_5 0x0 - Activate to read or write delay - PSU_DDR_PHY_DTPR5_TRCD 0xf + * Power down exit delay + * PSU_DDR_PHY_DTPR4_TXP 0x7 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR5_RESERVED_7_5 0x0 + * DRAM Timing Parameters Register 4 + * (OFFSET, MASK, VALUE) (0XFD080120, 0xFFFFFFFFU ,0x01162B07U) + */ + PSU_Mask_Write(DDR_PHY_DTPR4_OFFSET, 0xFFFFFFFFU, 0x01162B07U); +/*##################################################################### */ - Internal write to read command delay - PSU_DDR_PHY_DTPR5_TWTR 0x9 + /* + * Register : DTPR5 @ 0XFD080124 - DRAM Timing Parameters Register 5 - (OFFSET, MASK, VALUE) (0XFD080124, 0xFFFFFFFFU ,0x00320F09U) - RegMask = (DDR_PHY_DTPR5_RESERVED_31_24_MASK | DDR_PHY_DTPR5_TRC_MASK | DDR_PHY_DTPR5_RESERVED_15_MASK | DDR_PHY_DTPR5_TRCD_MASK | DDR_PHY_DTPR5_RESERVED_7_5_MASK | DDR_PHY_DTPR5_TWTR_MASK | 0 ); + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR5_RESERVED_31_24 0x0 - RegVal = ((0x00000000U << DDR_PHY_DTPR5_RESERVED_31_24_SHIFT - | 0x00000032U << DDR_PHY_DTPR5_TRC_SHIFT - | 0x00000000U << DDR_PHY_DTPR5_RESERVED_15_SHIFT - | 0x0000000FU << DDR_PHY_DTPR5_TRCD_SHIFT - | 0x00000000U << DDR_PHY_DTPR5_RESERVED_7_5_SHIFT - | 0x00000009U << DDR_PHY_DTPR5_TWTR_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DTPR5_OFFSET ,0xFFFFFFFFU ,0x00320F09U); - /*############################################################################################################################ */ + * Activate to activate command delay (same bank) + * PSU_DDR_PHY_DTPR5_TRC 0x33 - /*Register : DTPR6 @ 0XFD080128

+ * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR5_RESERVED_15 0x0 - PUB Write Latency Enable - PSU_DDR_PHY_DTPR6_PUBWLEN 0x0 + * Activate to read or write delay + * PSU_DDR_PHY_DTPR5_TRCD 0xf - PUB Read Latency Enable - PSU_DDR_PHY_DTPR6_PUBRLEN 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR5_RESERVED_7_5 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR6_RESERVED_29_14 0x0 + * Internal write to read command delay + * PSU_DDR_PHY_DTPR5_TWTR 0x8 - Write Latency - PSU_DDR_PHY_DTPR6_PUBWL 0xe + * DRAM Timing Parameters Register 5 + * (OFFSET, MASK, VALUE) (0XFD080124, 0xFFFFFFFFU ,0x00330F08U) + */ + PSU_Mask_Write(DDR_PHY_DTPR5_OFFSET, 0xFFFFFFFFU, 0x00330F08U); +/*##################################################################### */ - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR6_RESERVED_7_6 0x0 + /* + * Register : DTPR6 @ 0XFD080128 - Read Latency - PSU_DDR_PHY_DTPR6_PUBRL 0xf + * PUB Write Latency Enable + * PSU_DDR_PHY_DTPR6_PUBWLEN 0x0 - DRAM Timing Parameters Register 6 - (OFFSET, MASK, VALUE) (0XFD080128, 0xFFFFFFFFU ,0x00000E0FU) - RegMask = (DDR_PHY_DTPR6_PUBWLEN_MASK | DDR_PHY_DTPR6_PUBRLEN_MASK | DDR_PHY_DTPR6_RESERVED_29_14_MASK | DDR_PHY_DTPR6_PUBWL_MASK | DDR_PHY_DTPR6_RESERVED_7_6_MASK | DDR_PHY_DTPR6_PUBRL_MASK | 0 ); + * PUB Read Latency Enable + * PSU_DDR_PHY_DTPR6_PUBRLEN 0x0 - RegVal = ((0x00000000U << DDR_PHY_DTPR6_PUBWLEN_SHIFT - | 0x00000000U << DDR_PHY_DTPR6_PUBRLEN_SHIFT - | 0x00000000U << DDR_PHY_DTPR6_RESERVED_29_14_SHIFT - | 0x0000000EU << DDR_PHY_DTPR6_PUBWL_SHIFT - | 0x00000000U << DDR_PHY_DTPR6_RESERVED_7_6_SHIFT - | 0x0000000FU << DDR_PHY_DTPR6_PUBRL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DTPR6_OFFSET ,0xFFFFFFFFU ,0x00000E0FU); - /*############################################################################################################################ */ + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR6_RESERVED_29_14 0x0 - /*Register : RDIMMGCR0 @ 0XFD080140

+ * Write Latency + * PSU_DDR_PHY_DTPR6_PUBWL 0xe - Reserved. Return zeroes on reads. - PSU_DDR_PHY_RDIMMGCR0_RESERVED_31 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR6_RESERVED_7_6 0x0 - RDMIMM Quad CS Enable - PSU_DDR_PHY_RDIMMGCR0_QCSEN 0x0 + * Read Latency + * PSU_DDR_PHY_DTPR6_PUBRL 0xf - Reserved. Return zeroes on reads. - PSU_DDR_PHY_RDIMMGCR0_RESERVED_29_28 0x0 + * DRAM Timing Parameters Register 6 + * (OFFSET, MASK, VALUE) (0XFD080128, 0xFFFFFFFFU ,0x00000E0FU) + */ + PSU_Mask_Write(DDR_PHY_DTPR6_OFFSET, 0xFFFFFFFFU, 0x00000E0FU); +/*##################################################################### */ - RDIMM Outputs I/O Mode - PSU_DDR_PHY_RDIMMGCR0_RDIMMIOM 0x1 + /* + * Register : RDIMMGCR0 @ 0XFD080140 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_RDIMMGCR0_RESERVED_26_24 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_RDIMMGCR0_RESERVED_31 0x0 - ERROUT# Output Enable - PSU_DDR_PHY_RDIMMGCR0_ERROUTOE 0x0 + * RDMIMM Quad CS Enable + * PSU_DDR_PHY_RDIMMGCR0_QCSEN 0x0 - ERROUT# I/O Mode - PSU_DDR_PHY_RDIMMGCR0_ERROUTIOM 0x1 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_RDIMMGCR0_RESERVED_29_28 0x0 - ERROUT# Power Down Receiver - PSU_DDR_PHY_RDIMMGCR0_ERROUTPDR 0x0 + * RDIMM Outputs I/O Mode + * PSU_DDR_PHY_RDIMMGCR0_RDIMMIOM 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_RDIMMGCR0_RESERVED_20 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_RDIMMGCR0_RESERVED_26_24 0x0 - ERROUT# On-Die Termination - PSU_DDR_PHY_RDIMMGCR0_ERROUTODT 0x0 + * ERROUT# Output Enable + * PSU_DDR_PHY_RDIMMGCR0_ERROUTOE 0x0 - Load Reduced DIMM - PSU_DDR_PHY_RDIMMGCR0_LRDIMM 0x0 + * ERROUT# I/O Mode + * PSU_DDR_PHY_RDIMMGCR0_ERROUTIOM 0x1 - PAR_IN I/O Mode - PSU_DDR_PHY_RDIMMGCR0_PARINIOM 0x0 + * ERROUT# Power Down Receiver + * PSU_DDR_PHY_RDIMMGCR0_ERROUTPDR 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_RDIMMGCR0_RESERVED_16_8 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_RDIMMGCR0_RESERVED_20 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD 0x0 + * ERROUT# On-Die Termination + * PSU_DDR_PHY_RDIMMGCR0_ERROUTODT 0x0 - Rank Mirror Enable. - PSU_DDR_PHY_RDIMMGCR0_RNKMRREN 0x2 + * Load Reduced DIMM + * PSU_DDR_PHY_RDIMMGCR0_LRDIMM 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_RDIMMGCR0_RESERVED_3 0x0 + * PAR_IN I/O Mode + * PSU_DDR_PHY_RDIMMGCR0_PARINIOM 0x0 - Stop on Parity Error - PSU_DDR_PHY_RDIMMGCR0_SOPERR 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_RDIMMGCR0_RESERVED_16_8 0x0 - Parity Error No Registering - PSU_DDR_PHY_RDIMMGCR0_ERRNOREG 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD 0x0 - Registered DIMM - PSU_DDR_PHY_RDIMMGCR0_RDIMM 0x0 + * Rank Mirror Enable. + * PSU_DDR_PHY_RDIMMGCR0_RNKMRREN 0x2 - RDIMM General Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD080140, 0xFFFFFFFFU ,0x08400020U) - RegMask = (DDR_PHY_RDIMMGCR0_RESERVED_31_MASK | DDR_PHY_RDIMMGCR0_QCSEN_MASK | DDR_PHY_RDIMMGCR0_RESERVED_29_28_MASK | DDR_PHY_RDIMMGCR0_RDIMMIOM_MASK | DDR_PHY_RDIMMGCR0_RESERVED_26_24_MASK | DDR_PHY_RDIMMGCR0_ERROUTOE_MASK | DDR_PHY_RDIMMGCR0_ERROUTIOM_MASK | DDR_PHY_RDIMMGCR0_ERROUTPDR_MASK | DDR_PHY_RDIMMGCR0_RESERVED_20_MASK | DDR_PHY_RDIMMGCR0_ERROUTODT_MASK | DDR_PHY_RDIMMGCR0_LRDIMM_MASK | DDR_PHY_RDIMMGCR0_PARINIOM_MASK | DDR_PHY_RDIMMGCR0_RESERVED_16_8_MASK | DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_MASK | DDR_PHY_RDIMMGCR0_RNKMRREN_MASK | DDR_PHY_RDIMMGCR0_RESERVED_3_MASK | DDR_PHY_RDIMMGCR0_SOPERR_MASK | DDR_PHY_RDIMMGCR0_ERRNOREG_MASK | DDR_PHY_RDIMMGCR0_RDIMM_MASK | 0 ); + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_RDIMMGCR0_RESERVED_3 0x0 - RegVal = ((0x00000000U << DDR_PHY_RDIMMGCR0_RESERVED_31_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR0_QCSEN_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR0_RESERVED_29_28_SHIFT - | 0x00000001U << DDR_PHY_RDIMMGCR0_RDIMMIOM_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR0_RESERVED_26_24_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR0_ERROUTOE_SHIFT - | 0x00000001U << DDR_PHY_RDIMMGCR0_ERROUTIOM_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR0_ERROUTPDR_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR0_RESERVED_20_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR0_ERROUTODT_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR0_LRDIMM_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR0_PARINIOM_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR0_RESERVED_16_8_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_SHIFT - | 0x00000002U << DDR_PHY_RDIMMGCR0_RNKMRREN_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR0_RESERVED_3_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR0_SOPERR_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR0_ERRNOREG_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR0_RDIMM_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_RDIMMGCR0_OFFSET ,0xFFFFFFFFU ,0x08400020U); - /*############################################################################################################################ */ + * Stop on Parity Error + * PSU_DDR_PHY_RDIMMGCR0_SOPERR 0x0 - /*Register : RDIMMGCR1 @ 0XFD080144

+ * Parity Error No Registering + * PSU_DDR_PHY_RDIMMGCR0_ERRNOREG 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_RDIMMGCR1_RESERVED_31_29 0x0 + * Registered DIMM + * PSU_DDR_PHY_RDIMMGCR0_RDIMM 0x0 - Address [17] B-side Inversion Disable - PSU_DDR_PHY_RDIMMGCR1_A17BID 0x0 + * RDIMM General Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD080140, 0xFFFFFFFFU ,0x08400020U) + */ + PSU_Mask_Write(DDR_PHY_RDIMMGCR0_OFFSET, 0xFFFFFFFFU, 0x08400020U); +/*##################################################################### */ - Reserved. Return zeroes on reads. - PSU_DDR_PHY_RDIMMGCR1_RESERVED_27 0x0 + /* + * Register : RDIMMGCR1 @ 0XFD080144 - Command word to command word programming delay - PSU_DDR_PHY_RDIMMGCR1_TBCMRD_L2 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_RDIMMGCR1_RESERVED_31_29 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_RDIMMGCR1_RESERVED_23 0x0 + * Address [17] B-side Inversion Disable + * PSU_DDR_PHY_RDIMMGCR1_A17BID 0x0 - Command word to command word programming delay - PSU_DDR_PHY_RDIMMGCR1_TBCMRD_L 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_RDIMMGCR1_RESERVED_27 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_RDIMMGCR1_RESERVED_19 0x0 + * Command word to command word programming delay + * PSU_DDR_PHY_RDIMMGCR1_TBCMRD_L2 0x0 - Command word to command word programming delay - PSU_DDR_PHY_RDIMMGCR1_TBCMRD 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_RDIMMGCR1_RESERVED_23 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_RDIMMGCR1_RESERVED_15_14 0x0 + * Command word to command word programming delay + * PSU_DDR_PHY_RDIMMGCR1_TBCMRD_L 0x0 - Stabilization time - PSU_DDR_PHY_RDIMMGCR1_TBCSTAB 0xc80 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_RDIMMGCR1_RESERVED_19 0x0 - RDIMM General Configuration Register 1 - (OFFSET, MASK, VALUE) (0XFD080144, 0xFFFFFFFFU ,0x00000C80U) - RegMask = (DDR_PHY_RDIMMGCR1_RESERVED_31_29_MASK | DDR_PHY_RDIMMGCR1_A17BID_MASK | DDR_PHY_RDIMMGCR1_RESERVED_27_MASK | DDR_PHY_RDIMMGCR1_TBCMRD_L2_MASK | DDR_PHY_RDIMMGCR1_RESERVED_23_MASK | DDR_PHY_RDIMMGCR1_TBCMRD_L_MASK | DDR_PHY_RDIMMGCR1_RESERVED_19_MASK | DDR_PHY_RDIMMGCR1_TBCMRD_MASK | DDR_PHY_RDIMMGCR1_RESERVED_15_14_MASK | DDR_PHY_RDIMMGCR1_TBCSTAB_MASK | 0 ); - - RegVal = ((0x00000000U << DDR_PHY_RDIMMGCR1_RESERVED_31_29_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR1_A17BID_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR1_RESERVED_27_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR1_TBCMRD_L2_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR1_RESERVED_23_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR1_TBCMRD_L_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR1_RESERVED_19_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR1_TBCMRD_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR1_RESERVED_15_14_SHIFT - | 0x00000C80U << DDR_PHY_RDIMMGCR1_TBCSTAB_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_RDIMMGCR1_OFFSET ,0xFFFFFFFFU ,0x00000C80U); - /*############################################################################################################################ */ - - /*Register : RDIMMCR0 @ 0XFD080150

+ * Command word to command word programming delay + * PSU_DDR_PHY_RDIMMGCR1_TBCMRD 0x0 - DDR4/DDR3 Control Word 7 - PSU_DDR_PHY_RDIMMCR0_RC7 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_RDIMMGCR1_RESERVED_15_14 0x0 - DDR4 Control Word 6 (Comman space Control Word) / DDR3 Reserved - PSU_DDR_PHY_RDIMMCR0_RC6 0x0 - - DDR4/DDR3 Control Word 5 (CK Driver Characteristics Control Word) - PSU_DDR_PHY_RDIMMCR0_RC5 0x0 - - DDR4 Control Word 4 (ODT and CKE Signals Driver Characteristics Control Word) / DDR3 Control Word 4 (Control Signals Driver C - aracteristics Control Word) - PSU_DDR_PHY_RDIMMCR0_RC4 0x0 - - DDR4 Control Word 3 (CA and CS Signals Driver Characteristics Control Word) / DDR3 Control Word 3 (Command/Address Signals Dr - ver Characteristrics Control Word) - PSU_DDR_PHY_RDIMMCR0_RC3 0x0 - - DDR4 Control Word 2 (Timing and IBT Control Word) / DDR3 Control Word 2 (Timing Control Word) - PSU_DDR_PHY_RDIMMCR0_RC2 0x0 - - DDR4/DDR3 Control Word 1 (Clock Driver Enable Control Word) - PSU_DDR_PHY_RDIMMCR0_RC1 0x0 - - DDR4/DDR3 Control Word 0 (Global Features Control Word) - PSU_DDR_PHY_RDIMMCR0_RC0 0x0 - - RDIMM Control Register 0 - (OFFSET, MASK, VALUE) (0XFD080150, 0xFFFFFFFFU ,0x00000000U) - RegMask = (DDR_PHY_RDIMMCR0_RC7_MASK | DDR_PHY_RDIMMCR0_RC6_MASK | DDR_PHY_RDIMMCR0_RC5_MASK | DDR_PHY_RDIMMCR0_RC4_MASK | DDR_PHY_RDIMMCR0_RC3_MASK | DDR_PHY_RDIMMCR0_RC2_MASK | DDR_PHY_RDIMMCR0_RC1_MASK | DDR_PHY_RDIMMCR0_RC0_MASK | 0 ); - - RegVal = ((0x00000000U << DDR_PHY_RDIMMCR0_RC7_SHIFT - | 0x00000000U << DDR_PHY_RDIMMCR0_RC6_SHIFT - | 0x00000000U << DDR_PHY_RDIMMCR0_RC5_SHIFT - | 0x00000000U << DDR_PHY_RDIMMCR0_RC4_SHIFT - | 0x00000000U << DDR_PHY_RDIMMCR0_RC3_SHIFT - | 0x00000000U << DDR_PHY_RDIMMCR0_RC2_SHIFT - | 0x00000000U << DDR_PHY_RDIMMCR0_RC1_SHIFT - | 0x00000000U << DDR_PHY_RDIMMCR0_RC0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_RDIMMCR0_OFFSET ,0xFFFFFFFFU ,0x00000000U); - /*############################################################################################################################ */ + * Stabilization time + * PSU_DDR_PHY_RDIMMGCR1_TBCSTAB 0xc80 - /*Register : RDIMMCR1 @ 0XFD080154

+ * RDIMM General Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD080144, 0xFFFFFFFFU ,0x00000C80U) + */ + PSU_Mask_Write(DDR_PHY_RDIMMGCR1_OFFSET, 0xFFFFFFFFU, 0x00000C80U); +/*##################################################################### */ - Control Word 15 - PSU_DDR_PHY_RDIMMCR1_RC15 0x0 + /* + * Register : RDIMMCR0 @ 0XFD080150 - DDR4 Control Word 14 (Parity Control Word) / DDR3 Reserved - PSU_DDR_PHY_RDIMMCR1_RC14 0x0 + * DDR4/DDR3 Control Word 7 + * PSU_DDR_PHY_RDIMMCR0_RC7 0x0 - DDR4 Control Word 13 (DIMM Configuration Control Word) / DDR3 Reserved - PSU_DDR_PHY_RDIMMCR1_RC13 0x0 + * DDR4 Control Word 6 (Comman space Control Word) / DDR3 Reserved + * PSU_DDR_PHY_RDIMMCR0_RC6 0x0 - DDR4 Control Word 12 (Training Control Word) / DDR3 Reserved - PSU_DDR_PHY_RDIMMCR1_RC12 0x0 + * DDR4/DDR3 Control Word 5 (CK Driver Characteristics Control Word) + * PSU_DDR_PHY_RDIMMCR0_RC5 0x0 - DDR4 Control Word 11 (Operating Voltage VDD and VREFCA Source Control Word) / DDR3 Control Word 11 (Operation Voltage VDD Con - rol Word) - PSU_DDR_PHY_RDIMMCR1_RC11 0x0 + * DDR4 Control Word 4 (ODT and CKE Signals Driver Characteristics Control + * Word) / DDR3 Control Word 4 (Control Signals Driver Characteristics Cont + * rol Word) + * PSU_DDR_PHY_RDIMMCR0_RC4 0x0 - DDR4/DDR3 Control Word 10 (RDIMM Operating Speed Control Word) - PSU_DDR_PHY_RDIMMCR1_RC10 0x2 + * DDR4 Control Word 3 (CA and CS Signals Driver Characteristics Control Wo + * rd) / DDR3 Control Word 3 (Command/Address Signals Driver Characteristri + * cs Control Word) + * PSU_DDR_PHY_RDIMMCR0_RC3 0x0 - DDR4/DDR3 Control Word 9 (Power Saving Settings Control Word) - PSU_DDR_PHY_RDIMMCR1_RC9 0x0 + * DDR4 Control Word 2 (Timing and IBT Control Word) / DDR3 Control Word 2 + * (Timing Control Word) + * PSU_DDR_PHY_RDIMMCR0_RC2 0x0 - DDR4 Control Word 8 (Input/Output Configuration Control Word) / DDR3 Control Word 8 (Additional Input Bus Termination Setting - Control Word) - PSU_DDR_PHY_RDIMMCR1_RC8 0x0 + * DDR4/DDR3 Control Word 1 (Clock Driver Enable Control Word) + * PSU_DDR_PHY_RDIMMCR0_RC1 0x0 - RDIMM Control Register 1 - (OFFSET, MASK, VALUE) (0XFD080154, 0xFFFFFFFFU ,0x00000200U) - RegMask = (DDR_PHY_RDIMMCR1_RC15_MASK | DDR_PHY_RDIMMCR1_RC14_MASK | DDR_PHY_RDIMMCR1_RC13_MASK | DDR_PHY_RDIMMCR1_RC12_MASK | DDR_PHY_RDIMMCR1_RC11_MASK | DDR_PHY_RDIMMCR1_RC10_MASK | DDR_PHY_RDIMMCR1_RC9_MASK | DDR_PHY_RDIMMCR1_RC8_MASK | 0 ); + * DDR4/DDR3 Control Word 0 (Global Features Control Word) + * PSU_DDR_PHY_RDIMMCR0_RC0 0x0 - RegVal = ((0x00000000U << DDR_PHY_RDIMMCR1_RC15_SHIFT - | 0x00000000U << DDR_PHY_RDIMMCR1_RC14_SHIFT - | 0x00000000U << DDR_PHY_RDIMMCR1_RC13_SHIFT - | 0x00000000U << DDR_PHY_RDIMMCR1_RC12_SHIFT - | 0x00000000U << DDR_PHY_RDIMMCR1_RC11_SHIFT - | 0x00000002U << DDR_PHY_RDIMMCR1_RC10_SHIFT - | 0x00000000U << DDR_PHY_RDIMMCR1_RC9_SHIFT - | 0x00000000U << DDR_PHY_RDIMMCR1_RC8_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_RDIMMCR1_OFFSET ,0xFFFFFFFFU ,0x00000200U); - /*############################################################################################################################ */ + * RDIMM Control Register 0 + * (OFFSET, MASK, VALUE) (0XFD080150, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDR_PHY_RDIMMCR0_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ - /*Register : MR0 @ 0XFD080180

+ /* + * Register : RDIMMCR1 @ 0XFD080154 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_MR0_RESERVED_31_8 0x8 + * Control Word 15 + * PSU_DDR_PHY_RDIMMCR1_RC15 0x0 - CA Terminating Rank - PSU_DDR_PHY_MR0_CATR 0x0 + * DDR4 Control Word 14 (Parity Control Word) / DDR3 Reserved + * PSU_DDR_PHY_RDIMMCR1_RC14 0x0 - Reserved. These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0. - PSU_DDR_PHY_MR0_RSVD_6_5 0x1 + * DDR4 Control Word 13 (DIMM Configuration Control Word) / DDR3 Reserved + * PSU_DDR_PHY_RDIMMCR1_RC13 0x0 - Built-in Self-Test for RZQ - PSU_DDR_PHY_MR0_RZQI 0x2 + * DDR4 Control Word 12 (Training Control Word) / DDR3 Reserved + * PSU_DDR_PHY_RDIMMCR1_RC12 0x0 - Reserved. These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0. - PSU_DDR_PHY_MR0_RSVD_2_0 0x0 + * DDR4 Control Word 11 (Operating Voltage VDD and VREFCA Source Control Wo + * rd) / DDR3 Control Word 11 (Operation Voltage VDD Control Word) + * PSU_DDR_PHY_RDIMMCR1_RC11 0x0 - LPDDR4 Mode Register 0 - (OFFSET, MASK, VALUE) (0XFD080180, 0xFFFFFFFFU ,0x00000830U) - RegMask = (DDR_PHY_MR0_RESERVED_31_8_MASK | DDR_PHY_MR0_CATR_MASK | DDR_PHY_MR0_RSVD_6_5_MASK | DDR_PHY_MR0_RZQI_MASK | DDR_PHY_MR0_RSVD_2_0_MASK | 0 ); + * DDR4/DDR3 Control Word 10 (RDIMM Operating Speed Control Word) + * PSU_DDR_PHY_RDIMMCR1_RC10 0x2 - RegVal = ((0x00000008U << DDR_PHY_MR0_RESERVED_31_8_SHIFT - | 0x00000000U << DDR_PHY_MR0_CATR_SHIFT - | 0x00000001U << DDR_PHY_MR0_RSVD_6_5_SHIFT - | 0x00000002U << DDR_PHY_MR0_RZQI_SHIFT - | 0x00000000U << DDR_PHY_MR0_RSVD_2_0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_MR0_OFFSET ,0xFFFFFFFFU ,0x00000830U); - /*############################################################################################################################ */ + * DDR4/DDR3 Control Word 9 (Power Saving Settings Control Word) + * PSU_DDR_PHY_RDIMMCR1_RC9 0x0 - /*Register : MR1 @ 0XFD080184

+ * DDR4 Control Word 8 (Input/Output Configuration Control Word) / DDR3 Con + * trol Word 8 (Additional Input Bus Termination Setting Control Word) + * PSU_DDR_PHY_RDIMMCR1_RC8 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_MR1_RESERVED_31_8 0x3 + * RDIMM Control Register 1 + * (OFFSET, MASK, VALUE) (0XFD080154, 0xFFFFFFFFU ,0x00000200U) + */ + PSU_Mask_Write(DDR_PHY_RDIMMCR1_OFFSET, 0xFFFFFFFFU, 0x00000200U); +/*##################################################################### */ - Read Postamble Length - PSU_DDR_PHY_MR1_RDPST 0x0 + /* + * Register : MR0 @ 0XFD080180 - Write-recovery for auto-precharge command - PSU_DDR_PHY_MR1_NWR 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_MR0_RESERVED_31_8 0x6 - Read Preamble Length - PSU_DDR_PHY_MR1_RDPRE 0x0 + * CA Terminating Rank + * PSU_DDR_PHY_MR0_CATR 0x0 - Write Preamble Length - PSU_DDR_PHY_MR1_WRPRE 0x0 + * Reserved. These are JEDEC reserved bits and are recommended by JEDEC to + * be programmed to 0x0. + * PSU_DDR_PHY_MR0_RSVD_6_5 0x1 - Burst Length - PSU_DDR_PHY_MR1_BL 0x1 + * Built-in Self-Test for RZQ + * PSU_DDR_PHY_MR0_RZQI 0x2 - LPDDR4 Mode Register 1 - (OFFSET, MASK, VALUE) (0XFD080184, 0xFFFFFFFFU ,0x00000301U) - RegMask = (DDR_PHY_MR1_RESERVED_31_8_MASK | DDR_PHY_MR1_RDPST_MASK | DDR_PHY_MR1_NWR_MASK | DDR_PHY_MR1_RDPRE_MASK | DDR_PHY_MR1_WRPRE_MASK | DDR_PHY_MR1_BL_MASK | 0 ); + * Reserved. These are JEDEC reserved bits and are recommended by JEDEC to + * be programmed to 0x0. + * PSU_DDR_PHY_MR0_RSVD_2_0 0x0 - RegVal = ((0x00000003U << DDR_PHY_MR1_RESERVED_31_8_SHIFT - | 0x00000000U << DDR_PHY_MR1_RDPST_SHIFT - | 0x00000000U << DDR_PHY_MR1_NWR_SHIFT - | 0x00000000U << DDR_PHY_MR1_RDPRE_SHIFT - | 0x00000000U << DDR_PHY_MR1_WRPRE_SHIFT - | 0x00000001U << DDR_PHY_MR1_BL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_MR1_OFFSET ,0xFFFFFFFFU ,0x00000301U); - /*############################################################################################################################ */ + * LPDDR4 Mode Register 0 + * (OFFSET, MASK, VALUE) (0XFD080180, 0xFFFFFFFFU ,0x00000630U) + */ + PSU_Mask_Write(DDR_PHY_MR0_OFFSET, 0xFFFFFFFFU, 0x00000630U); +/*##################################################################### */ - /*Register : MR2 @ 0XFD080188

+ /* + * Register : MR1 @ 0XFD080184 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_MR2_RESERVED_31_8 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_MR1_RESERVED_31_8 0x3 - Write Leveling - PSU_DDR_PHY_MR2_WRL 0x0 + * Read Postamble Length + * PSU_DDR_PHY_MR1_RDPST 0x0 - Write Latency Set - PSU_DDR_PHY_MR2_WLS 0x0 + * Write-recovery for auto-precharge command + * PSU_DDR_PHY_MR1_NWR 0x0 - Write Latency - PSU_DDR_PHY_MR2_WL 0x4 + * Read Preamble Length + * PSU_DDR_PHY_MR1_RDPRE 0x0 - Read Latency - PSU_DDR_PHY_MR2_RL 0x0 + * Write Preamble Length + * PSU_DDR_PHY_MR1_WRPRE 0x0 - LPDDR4 Mode Register 2 - (OFFSET, MASK, VALUE) (0XFD080188, 0xFFFFFFFFU ,0x00000020U) - RegMask = (DDR_PHY_MR2_RESERVED_31_8_MASK | DDR_PHY_MR2_WRL_MASK | DDR_PHY_MR2_WLS_MASK | DDR_PHY_MR2_WL_MASK | DDR_PHY_MR2_RL_MASK | 0 ); + * Burst Length + * PSU_DDR_PHY_MR1_BL 0x1 - RegVal = ((0x00000000U << DDR_PHY_MR2_RESERVED_31_8_SHIFT - | 0x00000000U << DDR_PHY_MR2_WRL_SHIFT - | 0x00000000U << DDR_PHY_MR2_WLS_SHIFT - | 0x00000004U << DDR_PHY_MR2_WL_SHIFT - | 0x00000000U << DDR_PHY_MR2_RL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_MR2_OFFSET ,0xFFFFFFFFU ,0x00000020U); - /*############################################################################################################################ */ + * LPDDR4 Mode Register 1 + * (OFFSET, MASK, VALUE) (0XFD080184, 0xFFFFFFFFU ,0x00000301U) + */ + PSU_Mask_Write(DDR_PHY_MR1_OFFSET, 0xFFFFFFFFU, 0x00000301U); +/*##################################################################### */ - /*Register : MR3 @ 0XFD08018C

+ /* + * Register : MR2 @ 0XFD080188 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_MR3_RESERVED_31_8 0x2 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_MR2_RESERVED_31_8 0x0 - DBI-Write Enable - PSU_DDR_PHY_MR3_DBIWR 0x0 + * Write Leveling + * PSU_DDR_PHY_MR2_WRL 0x0 - DBI-Read Enable - PSU_DDR_PHY_MR3_DBIRD 0x0 + * Write Latency Set + * PSU_DDR_PHY_MR2_WLS 0x0 - Pull-down Drive Strength - PSU_DDR_PHY_MR3_PDDS 0x0 + * Write Latency + * PSU_DDR_PHY_MR2_WL 0x4 - These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0. - PSU_DDR_PHY_MR3_RSVD 0x0 + * Read Latency + * PSU_DDR_PHY_MR2_RL 0x0 - Write Postamble Length - PSU_DDR_PHY_MR3_WRPST 0x0 + * LPDDR4 Mode Register 2 + * (OFFSET, MASK, VALUE) (0XFD080188, 0xFFFFFFFFU ,0x00000020U) + */ + PSU_Mask_Write(DDR_PHY_MR2_OFFSET, 0xFFFFFFFFU, 0x00000020U); +/*##################################################################### */ - Pull-up Calibration Point - PSU_DDR_PHY_MR3_PUCAL 0x0 + /* + * Register : MR3 @ 0XFD08018C - LPDDR4 Mode Register 3 - (OFFSET, MASK, VALUE) (0XFD08018C, 0xFFFFFFFFU ,0x00000200U) - RegMask = (DDR_PHY_MR3_RESERVED_31_8_MASK | DDR_PHY_MR3_DBIWR_MASK | DDR_PHY_MR3_DBIRD_MASK | DDR_PHY_MR3_PDDS_MASK | DDR_PHY_MR3_RSVD_MASK | DDR_PHY_MR3_WRPST_MASK | DDR_PHY_MR3_PUCAL_MASK | 0 ); + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_MR3_RESERVED_31_8 0x2 - RegVal = ((0x00000002U << DDR_PHY_MR3_RESERVED_31_8_SHIFT - | 0x00000000U << DDR_PHY_MR3_DBIWR_SHIFT - | 0x00000000U << DDR_PHY_MR3_DBIRD_SHIFT - | 0x00000000U << DDR_PHY_MR3_PDDS_SHIFT - | 0x00000000U << DDR_PHY_MR3_RSVD_SHIFT - | 0x00000000U << DDR_PHY_MR3_WRPST_SHIFT - | 0x00000000U << DDR_PHY_MR3_PUCAL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_MR3_OFFSET ,0xFFFFFFFFU ,0x00000200U); - /*############################################################################################################################ */ + * DBI-Write Enable + * PSU_DDR_PHY_MR3_DBIWR 0x0 - /*Register : MR4 @ 0XFD080190

+ * DBI-Read Enable + * PSU_DDR_PHY_MR3_DBIRD 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_MR4_RESERVED_31_16 0x0 + * Pull-down Drive Strength + * PSU_DDR_PHY_MR3_PDDS 0x0 - These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0. - PSU_DDR_PHY_MR4_RSVD_15_13 0x0 + * These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. + * PSU_DDR_PHY_MR3_RSVD 0x0 - Write Preamble - PSU_DDR_PHY_MR4_WRP 0x0 + * Write Postamble Length + * PSU_DDR_PHY_MR3_WRPST 0x0 - Read Preamble - PSU_DDR_PHY_MR4_RDP 0x0 + * Pull-up Calibration Point + * PSU_DDR_PHY_MR3_PUCAL 0x0 - Read Preamble Training Mode - PSU_DDR_PHY_MR4_RPTM 0x0 + * LPDDR4 Mode Register 3 + * (OFFSET, MASK, VALUE) (0XFD08018C, 0xFFFFFFFFU ,0x00000200U) + */ + PSU_Mask_Write(DDR_PHY_MR3_OFFSET, 0xFFFFFFFFU, 0x00000200U); +/*##################################################################### */ - Self Refresh Abort - PSU_DDR_PHY_MR4_SRA 0x0 + /* + * Register : MR4 @ 0XFD080190 - CS to Command Latency Mode - PSU_DDR_PHY_MR4_CS2CMDL 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_MR4_RESERVED_31_16 0x0 - These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0. - PSU_DDR_PHY_MR4_RSVD1 0x0 + * These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. + * PSU_DDR_PHY_MR4_RSVD_15_13 0x0 - Internal VREF Monitor - PSU_DDR_PHY_MR4_IVM 0x0 + * Write Preamble + * PSU_DDR_PHY_MR4_WRP 0x0 - Temperature Controlled Refresh Mode - PSU_DDR_PHY_MR4_TCRM 0x0 + * Read Preamble + * PSU_DDR_PHY_MR4_RDP 0x0 - Temperature Controlled Refresh Range - PSU_DDR_PHY_MR4_TCRR 0x0 + * Read Preamble Training Mode + * PSU_DDR_PHY_MR4_RPTM 0x0 - Maximum Power Down Mode - PSU_DDR_PHY_MR4_MPDM 0x0 + * Self Refresh Abort + * PSU_DDR_PHY_MR4_SRA 0x0 - This is a JEDEC reserved bit and is recommended by JEDEC to be programmed to 0x0. - PSU_DDR_PHY_MR4_RSVD_0 0x0 + * CS to Command Latency Mode + * PSU_DDR_PHY_MR4_CS2CMDL 0x0 - DDR4 Mode Register 4 - (OFFSET, MASK, VALUE) (0XFD080190, 0xFFFFFFFFU ,0x00000000U) - RegMask = (DDR_PHY_MR4_RESERVED_31_16_MASK | DDR_PHY_MR4_RSVD_15_13_MASK | DDR_PHY_MR4_WRP_MASK | DDR_PHY_MR4_RDP_MASK | DDR_PHY_MR4_RPTM_MASK | DDR_PHY_MR4_SRA_MASK | DDR_PHY_MR4_CS2CMDL_MASK | DDR_PHY_MR4_RSVD1_MASK | DDR_PHY_MR4_IVM_MASK | DDR_PHY_MR4_TCRM_MASK | DDR_PHY_MR4_TCRR_MASK | DDR_PHY_MR4_MPDM_MASK | DDR_PHY_MR4_RSVD_0_MASK | 0 ); + * These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. + * PSU_DDR_PHY_MR4_RSVD1 0x0 - RegVal = ((0x00000000U << DDR_PHY_MR4_RESERVED_31_16_SHIFT - | 0x00000000U << DDR_PHY_MR4_RSVD_15_13_SHIFT - | 0x00000000U << DDR_PHY_MR4_WRP_SHIFT - | 0x00000000U << DDR_PHY_MR4_RDP_SHIFT - | 0x00000000U << DDR_PHY_MR4_RPTM_SHIFT - | 0x00000000U << DDR_PHY_MR4_SRA_SHIFT - | 0x00000000U << DDR_PHY_MR4_CS2CMDL_SHIFT - | 0x00000000U << DDR_PHY_MR4_RSVD1_SHIFT - | 0x00000000U << DDR_PHY_MR4_IVM_SHIFT - | 0x00000000U << DDR_PHY_MR4_TCRM_SHIFT - | 0x00000000U << DDR_PHY_MR4_TCRR_SHIFT - | 0x00000000U << DDR_PHY_MR4_MPDM_SHIFT - | 0x00000000U << DDR_PHY_MR4_RSVD_0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_MR4_OFFSET ,0xFFFFFFFFU ,0x00000000U); - /*############################################################################################################################ */ + * Internal VREF Monitor + * PSU_DDR_PHY_MR4_IVM 0x0 - /*Register : MR5 @ 0XFD080194

+ * Temperature Controlled Refresh Mode + * PSU_DDR_PHY_MR4_TCRM 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_MR5_RESERVED_31_16 0x0 + * Temperature Controlled Refresh Range + * PSU_DDR_PHY_MR4_TCRR 0x0 - These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0. - PSU_DDR_PHY_MR5_RSVD 0x0 + * Maximum Power Down Mode + * PSU_DDR_PHY_MR4_MPDM 0x0 - Read DBI - PSU_DDR_PHY_MR5_RDBI 0x0 + * This is a JEDEC reserved bit and is recommended by JEDEC to be programme + * d to 0x0. + * PSU_DDR_PHY_MR4_RSVD_0 0x0 - Write DBI - PSU_DDR_PHY_MR5_WDBI 0x0 + * DDR4 Mode Register 4 + * (OFFSET, MASK, VALUE) (0XFD080190, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDR_PHY_MR4_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ - Data Mask - PSU_DDR_PHY_MR5_DM 0x1 + /* + * Register : MR5 @ 0XFD080194 - CA Parity Persistent Error - PSU_DDR_PHY_MR5_CAPPE 0x1 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_MR5_RESERVED_31_16 0x0 - RTT_PARK - PSU_DDR_PHY_MR5_RTTPARK 0x3 + * These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. + * PSU_DDR_PHY_MR5_RSVD 0x0 - ODT Input Buffer during Power Down mode - PSU_DDR_PHY_MR5_ODTIBPD 0x0 + * Read DBI + * PSU_DDR_PHY_MR5_RDBI 0x0 - C/A Parity Error Status - PSU_DDR_PHY_MR5_CAPES 0x0 + * Write DBI + * PSU_DDR_PHY_MR5_WDBI 0x0 - CRC Error Clear - PSU_DDR_PHY_MR5_CRCEC 0x0 + * Data Mask + * PSU_DDR_PHY_MR5_DM 0x1 - C/A Parity Latency Mode - PSU_DDR_PHY_MR5_CAPM 0x0 + * CA Parity Persistent Error + * PSU_DDR_PHY_MR5_CAPPE 0x1 - DDR4 Mode Register 5 - (OFFSET, MASK, VALUE) (0XFD080194, 0xFFFFFFFFU ,0x000006C0U) - RegMask = (DDR_PHY_MR5_RESERVED_31_16_MASK | DDR_PHY_MR5_RSVD_MASK | DDR_PHY_MR5_RDBI_MASK | DDR_PHY_MR5_WDBI_MASK | DDR_PHY_MR5_DM_MASK | DDR_PHY_MR5_CAPPE_MASK | DDR_PHY_MR5_RTTPARK_MASK | DDR_PHY_MR5_ODTIBPD_MASK | DDR_PHY_MR5_CAPES_MASK | DDR_PHY_MR5_CRCEC_MASK | DDR_PHY_MR5_CAPM_MASK | 0 ); + * RTT_PARK + * PSU_DDR_PHY_MR5_RTTPARK 0x3 - RegVal = ((0x00000000U << DDR_PHY_MR5_RESERVED_31_16_SHIFT - | 0x00000000U << DDR_PHY_MR5_RSVD_SHIFT - | 0x00000000U << DDR_PHY_MR5_RDBI_SHIFT - | 0x00000000U << DDR_PHY_MR5_WDBI_SHIFT - | 0x00000001U << DDR_PHY_MR5_DM_SHIFT - | 0x00000001U << DDR_PHY_MR5_CAPPE_SHIFT - | 0x00000003U << DDR_PHY_MR5_RTTPARK_SHIFT - | 0x00000000U << DDR_PHY_MR5_ODTIBPD_SHIFT - | 0x00000000U << DDR_PHY_MR5_CAPES_SHIFT - | 0x00000000U << DDR_PHY_MR5_CRCEC_SHIFT - | 0x00000000U << DDR_PHY_MR5_CAPM_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_MR5_OFFSET ,0xFFFFFFFFU ,0x000006C0U); - /*############################################################################################################################ */ + * ODT Input Buffer during Power Down mode + * PSU_DDR_PHY_MR5_ODTIBPD 0x0 - /*Register : MR6 @ 0XFD080198

+ * C/A Parity Error Status + * PSU_DDR_PHY_MR5_CAPES 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_MR6_RESERVED_31_16 0x0 + * CRC Error Clear + * PSU_DDR_PHY_MR5_CRCEC 0x0 - These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0. - PSU_DDR_PHY_MR6_RSVD_15_13 0x0 + * C/A Parity Latency Mode + * PSU_DDR_PHY_MR5_CAPM 0x0 - CAS_n to CAS_n command delay for same bank group (tCCD_L) - PSU_DDR_PHY_MR6_TCCDL 0x2 + * DDR4 Mode Register 5 + * (OFFSET, MASK, VALUE) (0XFD080194, 0xFFFFFFFFU ,0x000006C0U) + */ + PSU_Mask_Write(DDR_PHY_MR5_OFFSET, 0xFFFFFFFFU, 0x000006C0U); +/*##################################################################### */ - These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0. - PSU_DDR_PHY_MR6_RSVD_9_8 0x0 + /* + * Register : MR6 @ 0XFD080198 - VrefDQ Training Enable - PSU_DDR_PHY_MR6_VDDQTEN 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_MR6_RESERVED_31_16 0x0 - VrefDQ Training Range - PSU_DDR_PHY_MR6_VDQTRG 0x0 + * These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. + * PSU_DDR_PHY_MR6_RSVD_15_13 0x0 - VrefDQ Training Values - PSU_DDR_PHY_MR6_VDQTVAL 0x19 + * CAS_n to CAS_n command delay for same bank group (tCCD_L) + * PSU_DDR_PHY_MR6_TCCDL 0x2 - DDR4 Mode Register 6 - (OFFSET, MASK, VALUE) (0XFD080198, 0xFFFFFFFFU ,0x00000819U) - RegMask = (DDR_PHY_MR6_RESERVED_31_16_MASK | DDR_PHY_MR6_RSVD_15_13_MASK | DDR_PHY_MR6_TCCDL_MASK | DDR_PHY_MR6_RSVD_9_8_MASK | DDR_PHY_MR6_VDDQTEN_MASK | DDR_PHY_MR6_VDQTRG_MASK | DDR_PHY_MR6_VDQTVAL_MASK | 0 ); + * These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. + * PSU_DDR_PHY_MR6_RSVD_9_8 0x0 - RegVal = ((0x00000000U << DDR_PHY_MR6_RESERVED_31_16_SHIFT - | 0x00000000U << DDR_PHY_MR6_RSVD_15_13_SHIFT - | 0x00000002U << DDR_PHY_MR6_TCCDL_SHIFT - | 0x00000000U << DDR_PHY_MR6_RSVD_9_8_SHIFT - | 0x00000000U << DDR_PHY_MR6_VDDQTEN_SHIFT - | 0x00000000U << DDR_PHY_MR6_VDQTRG_SHIFT - | 0x00000019U << DDR_PHY_MR6_VDQTVAL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_MR6_OFFSET ,0xFFFFFFFFU ,0x00000819U); - /*############################################################################################################################ */ + * VrefDQ Training Enable + * PSU_DDR_PHY_MR6_VDDQTEN 0x0 - /*Register : MR11 @ 0XFD0801AC

+ * VrefDQ Training Range + * PSU_DDR_PHY_MR6_VDQTRG 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_MR11_RESERVED_31_8 0x0 + * VrefDQ Training Values + * PSU_DDR_PHY_MR6_VDQTVAL 0x19 - These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0. - PSU_DDR_PHY_MR11_RSVD 0x0 + * DDR4 Mode Register 6 + * (OFFSET, MASK, VALUE) (0XFD080198, 0xFFFFFFFFU ,0x00000819U) + */ + PSU_Mask_Write(DDR_PHY_MR6_OFFSET, 0xFFFFFFFFU, 0x00000819U); +/*##################################################################### */ - Power Down Control - PSU_DDR_PHY_MR11_PDCTL 0x0 + /* + * Register : MR11 @ 0XFD0801AC - DQ Bus Receiver On-Die-Termination - PSU_DDR_PHY_MR11_DQODT 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_MR11_RESERVED_31_8 0x0 - LPDDR4 Mode Register 11 - (OFFSET, MASK, VALUE) (0XFD0801AC, 0xFFFFFFFFU ,0x00000000U) - RegMask = (DDR_PHY_MR11_RESERVED_31_8_MASK | DDR_PHY_MR11_RSVD_MASK | DDR_PHY_MR11_PDCTL_MASK | DDR_PHY_MR11_DQODT_MASK | 0 ); + * These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. + * PSU_DDR_PHY_MR11_RSVD 0x0 - RegVal = ((0x00000000U << DDR_PHY_MR11_RESERVED_31_8_SHIFT - | 0x00000000U << DDR_PHY_MR11_RSVD_SHIFT - | 0x00000000U << DDR_PHY_MR11_PDCTL_SHIFT - | 0x00000000U << DDR_PHY_MR11_DQODT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_MR11_OFFSET ,0xFFFFFFFFU ,0x00000000U); - /*############################################################################################################################ */ + * Power Down Control + * PSU_DDR_PHY_MR11_PDCTL 0x0 - /*Register : MR12 @ 0XFD0801B0

+ * DQ Bus Receiver On-Die-Termination + * PSU_DDR_PHY_MR11_DQODT 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_MR12_RESERVED_31_8 0x0 + * LPDDR4 Mode Register 11 + * (OFFSET, MASK, VALUE) (0XFD0801AC, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDR_PHY_MR11_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ - These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0. - PSU_DDR_PHY_MR12_RSVD 0x0 + /* + * Register : MR12 @ 0XFD0801B0 - VREF_CA Range Select. - PSU_DDR_PHY_MR12_VR_CA 0x1 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_MR12_RESERVED_31_8 0x0 - Controls the VREF(ca) levels for Frequency-Set-Point[1:0]. - PSU_DDR_PHY_MR12_VREF_CA 0xd + * These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. + * PSU_DDR_PHY_MR12_RSVD 0x0 - LPDDR4 Mode Register 12 - (OFFSET, MASK, VALUE) (0XFD0801B0, 0xFFFFFFFFU ,0x0000004DU) - RegMask = (DDR_PHY_MR12_RESERVED_31_8_MASK | DDR_PHY_MR12_RSVD_MASK | DDR_PHY_MR12_VR_CA_MASK | DDR_PHY_MR12_VREF_CA_MASK | 0 ); + * VREF_CA Range Select. + * PSU_DDR_PHY_MR12_VR_CA 0x1 - RegVal = ((0x00000000U << DDR_PHY_MR12_RESERVED_31_8_SHIFT - | 0x00000000U << DDR_PHY_MR12_RSVD_SHIFT - | 0x00000001U << DDR_PHY_MR12_VR_CA_SHIFT - | 0x0000000DU << DDR_PHY_MR12_VREF_CA_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_MR12_OFFSET ,0xFFFFFFFFU ,0x0000004DU); - /*############################################################################################################################ */ + * Controls the VREF(ca) levels for Frequency-Set-Point[1:0]. + * PSU_DDR_PHY_MR12_VREF_CA 0xd - /*Register : MR13 @ 0XFD0801B4

+ * LPDDR4 Mode Register 12 + * (OFFSET, MASK, VALUE) (0XFD0801B0, 0xFFFFFFFFU ,0x0000004DU) + */ + PSU_Mask_Write(DDR_PHY_MR12_OFFSET, 0xFFFFFFFFU, 0x0000004DU); +/*##################################################################### */ - Reserved. Return zeroes on reads. - PSU_DDR_PHY_MR13_RESERVED_31_8 0x0 + /* + * Register : MR13 @ 0XFD0801B4 - Frequency Set Point Operation Mode - PSU_DDR_PHY_MR13_FSPOP 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_MR13_RESERVED_31_8 0x0 - Frequency Set Point Write Enable - PSU_DDR_PHY_MR13_FSPWR 0x0 + * Frequency Set Point Operation Mode + * PSU_DDR_PHY_MR13_FSPOP 0x0 - Data Mask Enable - PSU_DDR_PHY_MR13_DMD 0x0 + * Frequency Set Point Write Enable + * PSU_DDR_PHY_MR13_FSPWR 0x0 - Refresh Rate Option - PSU_DDR_PHY_MR13_RRO 0x0 + * Data Mask Enable + * PSU_DDR_PHY_MR13_DMD 0x0 - VREF Current Generator - PSU_DDR_PHY_MR13_VRCG 0x1 + * Refresh Rate Option + * PSU_DDR_PHY_MR13_RRO 0x0 - VREF Output - PSU_DDR_PHY_MR13_VRO 0x0 + * VREF Current Generator + * PSU_DDR_PHY_MR13_VRCG 0x1 - Read Preamble Training Mode - PSU_DDR_PHY_MR13_RPT 0x0 + * VREF Output + * PSU_DDR_PHY_MR13_VRO 0x0 - Command Bus Training - PSU_DDR_PHY_MR13_CBT 0x0 + * Read Preamble Training Mode + * PSU_DDR_PHY_MR13_RPT 0x0 - LPDDR4 Mode Register 13 - (OFFSET, MASK, VALUE) (0XFD0801B4, 0xFFFFFFFFU ,0x00000008U) - RegMask = (DDR_PHY_MR13_RESERVED_31_8_MASK | DDR_PHY_MR13_FSPOP_MASK | DDR_PHY_MR13_FSPWR_MASK | DDR_PHY_MR13_DMD_MASK | DDR_PHY_MR13_RRO_MASK | DDR_PHY_MR13_VRCG_MASK | DDR_PHY_MR13_VRO_MASK | DDR_PHY_MR13_RPT_MASK | DDR_PHY_MR13_CBT_MASK | 0 ); + * Command Bus Training + * PSU_DDR_PHY_MR13_CBT 0x0 - RegVal = ((0x00000000U << DDR_PHY_MR13_RESERVED_31_8_SHIFT - | 0x00000000U << DDR_PHY_MR13_FSPOP_SHIFT - | 0x00000000U << DDR_PHY_MR13_FSPWR_SHIFT - | 0x00000000U << DDR_PHY_MR13_DMD_SHIFT - | 0x00000000U << DDR_PHY_MR13_RRO_SHIFT - | 0x00000001U << DDR_PHY_MR13_VRCG_SHIFT - | 0x00000000U << DDR_PHY_MR13_VRO_SHIFT - | 0x00000000U << DDR_PHY_MR13_RPT_SHIFT - | 0x00000000U << DDR_PHY_MR13_CBT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_MR13_OFFSET ,0xFFFFFFFFU ,0x00000008U); - /*############################################################################################################################ */ + * LPDDR4 Mode Register 13 + * (OFFSET, MASK, VALUE) (0XFD0801B4, 0xFFFFFFFFU ,0x00000008U) + */ + PSU_Mask_Write(DDR_PHY_MR13_OFFSET, 0xFFFFFFFFU, 0x00000008U); +/*##################################################################### */ - /*Register : MR14 @ 0XFD0801B8

+ /* + * Register : MR14 @ 0XFD0801B8 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_MR14_RESERVED_31_8 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_MR14_RESERVED_31_8 0x0 - These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0. - PSU_DDR_PHY_MR14_RSVD 0x0 + * These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. + * PSU_DDR_PHY_MR14_RSVD 0x0 - VREFDQ Range Selects. - PSU_DDR_PHY_MR14_VR_DQ 0x1 + * VREFDQ Range Selects. + * PSU_DDR_PHY_MR14_VR_DQ 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_MR14_VREF_DQ 0xd + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_MR14_VREF_DQ 0xd - LPDDR4 Mode Register 14 - (OFFSET, MASK, VALUE) (0XFD0801B8, 0xFFFFFFFFU ,0x0000004DU) - RegMask = (DDR_PHY_MR14_RESERVED_31_8_MASK | DDR_PHY_MR14_RSVD_MASK | DDR_PHY_MR14_VR_DQ_MASK | DDR_PHY_MR14_VREF_DQ_MASK | 0 ); + * LPDDR4 Mode Register 14 + * (OFFSET, MASK, VALUE) (0XFD0801B8, 0xFFFFFFFFU ,0x0000004DU) + */ + PSU_Mask_Write(DDR_PHY_MR14_OFFSET, 0xFFFFFFFFU, 0x0000004DU); +/*##################################################################### */ - RegVal = ((0x00000000U << DDR_PHY_MR14_RESERVED_31_8_SHIFT - | 0x00000000U << DDR_PHY_MR14_RSVD_SHIFT - | 0x00000001U << DDR_PHY_MR14_VR_DQ_SHIFT - | 0x0000000DU << DDR_PHY_MR14_VREF_DQ_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_MR14_OFFSET ,0xFFFFFFFFU ,0x0000004DU); - /*############################################################################################################################ */ + /* + * Register : MR22 @ 0XFD0801D8 - /*Register : MR22 @ 0XFD0801D8

+ * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_MR22_RESERVED_31_8 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_MR22_RESERVED_31_8 0x0 + * These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. + * PSU_DDR_PHY_MR22_RSVD 0x0 - These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0. - PSU_DDR_PHY_MR22_RSVD 0x0 + * CA ODT termination disable. + * PSU_DDR_PHY_MR22_ODTD_CA 0x0 - CA ODT termination disable. - PSU_DDR_PHY_MR22_ODTD_CA 0x0 + * ODT CS override. + * PSU_DDR_PHY_MR22_ODTE_CS 0x0 - ODT CS override. - PSU_DDR_PHY_MR22_ODTE_CS 0x0 + * ODT CK override. + * PSU_DDR_PHY_MR22_ODTE_CK 0x0 - ODT CK override. - PSU_DDR_PHY_MR22_ODTE_CK 0x0 + * Controller ODT value for VOH calibration. + * PSU_DDR_PHY_MR22_CODT 0x0 - Controller ODT value for VOH calibration. - PSU_DDR_PHY_MR22_CODT 0x0 + * LPDDR4 Mode Register 22 + * (OFFSET, MASK, VALUE) (0XFD0801D8, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDR_PHY_MR22_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ - LPDDR4 Mode Register 22 - (OFFSET, MASK, VALUE) (0XFD0801D8, 0xFFFFFFFFU ,0x00000000U) - RegMask = (DDR_PHY_MR22_RESERVED_31_8_MASK | DDR_PHY_MR22_RSVD_MASK | DDR_PHY_MR22_ODTD_CA_MASK | DDR_PHY_MR22_ODTE_CS_MASK | DDR_PHY_MR22_ODTE_CK_MASK | DDR_PHY_MR22_CODT_MASK | 0 ); + /* + * Register : DTCR0 @ 0XFD080200 - RegVal = ((0x00000000U << DDR_PHY_MR22_RESERVED_31_8_SHIFT - | 0x00000000U << DDR_PHY_MR22_RSVD_SHIFT - | 0x00000000U << DDR_PHY_MR22_ODTD_CA_SHIFT - | 0x00000000U << DDR_PHY_MR22_ODTE_CS_SHIFT - | 0x00000000U << DDR_PHY_MR22_ODTE_CK_SHIFT - | 0x00000000U << DDR_PHY_MR22_CODT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_MR22_OFFSET ,0xFFFFFFFFU ,0x00000000U); - /*############################################################################################################################ */ + * Refresh During Training + * PSU_DDR_PHY_DTCR0_RFSHDT 0x8 - /*Register : DTCR0 @ 0XFD080200

+ * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTCR0_RESERVED_27_26 0x0 - Refresh During Training - PSU_DDR_PHY_DTCR0_RFSHDT 0x8 + * Data Training Debug Rank Select + * PSU_DDR_PHY_DTCR0_DTDRS 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTCR0_RESERVED_27_26 0x0 + * Data Training with Early/Extended Gate + * PSU_DDR_PHY_DTCR0_DTEXG 0x0 - Data Training Debug Rank Select - PSU_DDR_PHY_DTCR0_DTDRS 0x0 + * Data Training Extended Write DQS + * PSU_DDR_PHY_DTCR0_DTEXD 0x0 - Data Training with Early/Extended Gate - PSU_DDR_PHY_DTCR0_DTEXG 0x0 + * Data Training Debug Step + * PSU_DDR_PHY_DTCR0_DTDSTP 0x0 - Data Training Extended Write DQS - PSU_DDR_PHY_DTCR0_DTEXD 0x0 + * Data Training Debug Enable + * PSU_DDR_PHY_DTCR0_DTDEN 0x0 - Data Training Debug Step - PSU_DDR_PHY_DTCR0_DTDSTP 0x0 + * Data Training Debug Byte Select + * PSU_DDR_PHY_DTCR0_DTDBS 0x0 - Data Training Debug Enable - PSU_DDR_PHY_DTCR0_DTDEN 0x0 + * Data Training read DBI deskewing configuration + * PSU_DDR_PHY_DTCR0_DTRDBITR 0x2 - Data Training Debug Byte Select - PSU_DDR_PHY_DTCR0_DTDBS 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTCR0_RESERVED_13 0x0 - Data Training read DBI deskewing configuration - PSU_DDR_PHY_DTCR0_DTRDBITR 0x2 + * Data Training Write Bit Deskew Data Mask + * PSU_DDR_PHY_DTCR0_DTWBDDM 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTCR0_RESERVED_13 0x0 + * Refreshes Issued During Entry to Training + * PSU_DDR_PHY_DTCR0_RFSHEN 0x1 - Data Training Write Bit Deskew Data Mask - PSU_DDR_PHY_DTCR0_DTWBDDM 0x1 + * Data Training Compare Data + * PSU_DDR_PHY_DTCR0_DTCMPD 0x1 - Refreshes Issued During Entry to Training - PSU_DDR_PHY_DTCR0_RFSHEN 0x1 + * Data Training Using MPR + * PSU_DDR_PHY_DTCR0_DTMPR 0x1 - Data Training Compare Data - PSU_DDR_PHY_DTCR0_DTCMPD 0x1 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTCR0_RESERVED_5_4 0x0 - Data Training Using MPR - PSU_DDR_PHY_DTCR0_DTMPR 0x1 + * Data Training Repeat Number + * PSU_DDR_PHY_DTCR0_DTRPTN 0x7 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTCR0_RESERVED_5_4 0x0 + * Data Training Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD080200, 0xFFFFFFFFU ,0x800091C7U) + */ + PSU_Mask_Write(DDR_PHY_DTCR0_OFFSET, 0xFFFFFFFFU, 0x800091C7U); +/*##################################################################### */ - Data Training Repeat Number - PSU_DDR_PHY_DTCR0_DTRPTN 0x7 + /* + * Register : DTCR1 @ 0XFD080204 - Data Training Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD080200, 0xFFFFFFFFU ,0x800091C7U) - RegMask = (DDR_PHY_DTCR0_RFSHDT_MASK | DDR_PHY_DTCR0_RESERVED_27_26_MASK | DDR_PHY_DTCR0_DTDRS_MASK | DDR_PHY_DTCR0_DTEXG_MASK | DDR_PHY_DTCR0_DTEXD_MASK | DDR_PHY_DTCR0_DTDSTP_MASK | DDR_PHY_DTCR0_DTDEN_MASK | DDR_PHY_DTCR0_DTDBS_MASK | DDR_PHY_DTCR0_DTRDBITR_MASK | DDR_PHY_DTCR0_RESERVED_13_MASK | DDR_PHY_DTCR0_DTWBDDM_MASK | DDR_PHY_DTCR0_RFSHEN_MASK | DDR_PHY_DTCR0_DTCMPD_MASK | DDR_PHY_DTCR0_DTMPR_MASK | DDR_PHY_DTCR0_RESERVED_5_4_MASK | DDR_PHY_DTCR0_DTRPTN_MASK | 0 ); + * Rank Enable. + * PSU_DDR_PHY_DTCR1_RANKEN_RSVD 0x0 - RegVal = ((0x00000008U << DDR_PHY_DTCR0_RFSHDT_SHIFT - | 0x00000000U << DDR_PHY_DTCR0_RESERVED_27_26_SHIFT - | 0x00000000U << DDR_PHY_DTCR0_DTDRS_SHIFT - | 0x00000000U << DDR_PHY_DTCR0_DTEXG_SHIFT - | 0x00000000U << DDR_PHY_DTCR0_DTEXD_SHIFT - | 0x00000000U << DDR_PHY_DTCR0_DTDSTP_SHIFT - | 0x00000000U << DDR_PHY_DTCR0_DTDEN_SHIFT - | 0x00000000U << DDR_PHY_DTCR0_DTDBS_SHIFT - | 0x00000002U << DDR_PHY_DTCR0_DTRDBITR_SHIFT - | 0x00000000U << DDR_PHY_DTCR0_RESERVED_13_SHIFT - | 0x00000001U << DDR_PHY_DTCR0_DTWBDDM_SHIFT - | 0x00000001U << DDR_PHY_DTCR0_RFSHEN_SHIFT - | 0x00000001U << DDR_PHY_DTCR0_DTCMPD_SHIFT - | 0x00000001U << DDR_PHY_DTCR0_DTMPR_SHIFT - | 0x00000000U << DDR_PHY_DTCR0_RESERVED_5_4_SHIFT - | 0x00000007U << DDR_PHY_DTCR0_DTRPTN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DTCR0_OFFSET ,0xFFFFFFFFU ,0x800091C7U); - /*############################################################################################################################ */ + * Rank Enable. + * PSU_DDR_PHY_DTCR1_RANKEN 0x1 - /*Register : DTCR1 @ 0XFD080204

+ * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTCR1_RESERVED_15_14 0x0 - Rank Enable. - PSU_DDR_PHY_DTCR1_RANKEN_RSVD 0x0 + * Data Training Rank + * PSU_DDR_PHY_DTCR1_DTRANK 0x0 - Rank Enable. - PSU_DDR_PHY_DTCR1_RANKEN 0x1 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTCR1_RESERVED_11 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTCR1_RESERVED_15_14 0x0 + * Read Leveling Gate Sampling Difference + * PSU_DDR_PHY_DTCR1_RDLVLGDIFF 0x2 - Data Training Rank - PSU_DDR_PHY_DTCR1_DTRANK 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTCR1_RESERVED_7 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTCR1_RESERVED_11 0x0 + * Read Leveling Gate Shift + * PSU_DDR_PHY_DTCR1_RDLVLGS 0x3 - Read Leveling Gate Sampling Difference - PSU_DDR_PHY_DTCR1_RDLVLGDIFF 0x2 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTCR1_RESERVED_3 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTCR1_RESERVED_7 0x0 + * Read Preamble Training enable + * PSU_DDR_PHY_DTCR1_RDPRMVL_TRN 0x1 - Read Leveling Gate Shift - PSU_DDR_PHY_DTCR1_RDLVLGS 0x3 + * Read Leveling Enable + * PSU_DDR_PHY_DTCR1_RDLVLEN 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTCR1_RESERVED_3 0x0 + * Basic Gate Training Enable + * PSU_DDR_PHY_DTCR1_BSTEN 0x0 - Read Preamble Training enable - PSU_DDR_PHY_DTCR1_RDPRMVL_TRN 0x1 + * Data Training Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD080204, 0xFFFFFFFFU ,0x00010236U) + */ + PSU_Mask_Write(DDR_PHY_DTCR1_OFFSET, 0xFFFFFFFFU, 0x00010236U); +/*##################################################################### */ - Read Leveling Enable - PSU_DDR_PHY_DTCR1_RDLVLEN 0x1 + /* + * Register : CATR0 @ 0XFD080240 - Basic Gate Training Enable - PSU_DDR_PHY_DTCR1_BSTEN 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_CATR0_RESERVED_31_21 0x0 - Data Training Configuration Register 1 - (OFFSET, MASK, VALUE) (0XFD080204, 0xFFFFFFFFU ,0x00010236U) - RegMask = (DDR_PHY_DTCR1_RANKEN_RSVD_MASK | DDR_PHY_DTCR1_RANKEN_MASK | DDR_PHY_DTCR1_RESERVED_15_14_MASK | DDR_PHY_DTCR1_DTRANK_MASK | DDR_PHY_DTCR1_RESERVED_11_MASK | DDR_PHY_DTCR1_RDLVLGDIFF_MASK | DDR_PHY_DTCR1_RESERVED_7_MASK | DDR_PHY_DTCR1_RDLVLGS_MASK | DDR_PHY_DTCR1_RESERVED_3_MASK | DDR_PHY_DTCR1_RDPRMVL_TRN_MASK | DDR_PHY_DTCR1_RDLVLEN_MASK | DDR_PHY_DTCR1_BSTEN_MASK | 0 ); + * Minimum time (in terms of number of dram clocks) between two consectuve + * CA calibration command + * PSU_DDR_PHY_CATR0_CACD 0x14 - RegVal = ((0x00000000U << DDR_PHY_DTCR1_RANKEN_RSVD_SHIFT - | 0x00000001U << DDR_PHY_DTCR1_RANKEN_SHIFT - | 0x00000000U << DDR_PHY_DTCR1_RESERVED_15_14_SHIFT - | 0x00000000U << DDR_PHY_DTCR1_DTRANK_SHIFT - | 0x00000000U << DDR_PHY_DTCR1_RESERVED_11_SHIFT - | 0x00000002U << DDR_PHY_DTCR1_RDLVLGDIFF_SHIFT - | 0x00000000U << DDR_PHY_DTCR1_RESERVED_7_SHIFT - | 0x00000003U << DDR_PHY_DTCR1_RDLVLGS_SHIFT - | 0x00000000U << DDR_PHY_DTCR1_RESERVED_3_SHIFT - | 0x00000001U << DDR_PHY_DTCR1_RDPRMVL_TRN_SHIFT - | 0x00000001U << DDR_PHY_DTCR1_RDLVLEN_SHIFT - | 0x00000000U << DDR_PHY_DTCR1_BSTEN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DTCR1_OFFSET ,0xFFFFFFFFU ,0x00010236U); - /*############################################################################################################################ */ + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_CATR0_RESERVED_15_13 0x0 - /*Register : CATR0 @ 0XFD080240

+ * Minimum time (in terms of number of dram clocks) PUB should wait before + * sampling the CA response after Calibration command has been sent to the + * memory + * PSU_DDR_PHY_CATR0_CAADR 0x10 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_CATR0_RESERVED_31_21 0x0 + * CA_1 Response Byte Lane 1 + * PSU_DDR_PHY_CATR0_CA1BYTE1 0x5 - Minimum time (in terms of number of dram clocks) between two consectuve CA calibration command - PSU_DDR_PHY_CATR0_CACD 0x14 + * CA_1 Response Byte Lane 0 + * PSU_DDR_PHY_CATR0_CA1BYTE0 0x4 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_CATR0_RESERVED_15_13 0x0 + * CA Training Register 0 + * (OFFSET, MASK, VALUE) (0XFD080240, 0xFFFFFFFFU ,0x00141054U) + */ + PSU_Mask_Write(DDR_PHY_CATR0_OFFSET, 0xFFFFFFFFU, 0x00141054U); +/*##################################################################### */ - Minimum time (in terms of number of dram clocks) PUB should wait before sampling the CA response after Calibration command ha - been sent to the memory - PSU_DDR_PHY_CATR0_CAADR 0x10 + /* + * Register : DQSDR0 @ 0XFD080250 - CA_1 Response Byte Lane 1 - PSU_DDR_PHY_CATR0_CA1BYTE1 0x5 + * Number of delay taps by which the DQS gate LCDL will be updated when DQS + * drift is detected + * PSU_DDR_PHY_DQSDR0_DFTDLY 0x0 - CA_1 Response Byte Lane 0 - PSU_DDR_PHY_CATR0_CA1BYTE0 0x4 - - CA Training Register 0 - (OFFSET, MASK, VALUE) (0XFD080240, 0xFFFFFFFFU ,0x00141054U) - RegMask = (DDR_PHY_CATR0_RESERVED_31_21_MASK | DDR_PHY_CATR0_CACD_MASK | DDR_PHY_CATR0_RESERVED_15_13_MASK | DDR_PHY_CATR0_CAADR_MASK | DDR_PHY_CATR0_CA1BYTE1_MASK | DDR_PHY_CATR0_CA1BYTE0_MASK | 0 ); - - RegVal = ((0x00000000U << DDR_PHY_CATR0_RESERVED_31_21_SHIFT - | 0x00000014U << DDR_PHY_CATR0_CACD_SHIFT - | 0x00000000U << DDR_PHY_CATR0_RESERVED_15_13_SHIFT - | 0x00000010U << DDR_PHY_CATR0_CAADR_SHIFT - | 0x00000005U << DDR_PHY_CATR0_CA1BYTE1_SHIFT - | 0x00000004U << DDR_PHY_CATR0_CA1BYTE0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_CATR0_OFFSET ,0xFFFFFFFFU ,0x00141054U); - /*############################################################################################################################ */ + * Drift Impedance Update + * PSU_DDR_PHY_DQSDR0_DFTZQUP 0x0 - /*Register : BISTLSR @ 0XFD080414

+ * Drift DDL Update + * PSU_DDR_PHY_DQSDR0_DFTDDLUP 0x0 - LFSR seed for pseudo-random BIST patterns - PSU_DDR_PHY_BISTLSR_SEED 0x12341000 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DQSDR0_RESERVED_25_22 0x0 - BIST LFSR Seed Register - (OFFSET, MASK, VALUE) (0XFD080414, 0xFFFFFFFFU ,0x12341000U) - RegMask = (DDR_PHY_BISTLSR_SEED_MASK | 0 ); + * Drift Read Spacing + * PSU_DDR_PHY_DQSDR0_DFTRDSPC 0x0 - RegVal = ((0x12341000U << DDR_PHY_BISTLSR_SEED_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_BISTLSR_OFFSET ,0xFFFFFFFFU ,0x12341000U); - /*############################################################################################################################ */ + * Drift Back-to-Back Reads + * PSU_DDR_PHY_DQSDR0_DFTB2BRD 0x8 - /*Register : RIOCR5 @ 0XFD0804F4

+ * Drift Idle Reads + * PSU_DDR_PHY_DQSDR0_DFTIDLRD 0x8 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_RIOCR5_RESERVED_31_16 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DQSDR0_RESERVED_11_8 0x0 - Reserved. Return zeros on reads. - PSU_DDR_PHY_RIOCR5_ODTOEMODE_RSVD 0x0 + * Gate Pulse Enable + * PSU_DDR_PHY_DQSDR0_DFTGPULSE 0x0 - SDRAM On-die Termination Output Enable (OE) Mode Selection. - PSU_DDR_PHY_RIOCR5_ODTOEMODE 0x5 + * DQS Drift Update Mode + * PSU_DDR_PHY_DQSDR0_DFTUPMODE 0x0 - Rank I/O Configuration Register 5 - (OFFSET, MASK, VALUE) (0XFD0804F4, 0xFFFFFFFFU ,0x00000005U) - RegMask = (DDR_PHY_RIOCR5_RESERVED_31_16_MASK | DDR_PHY_RIOCR5_ODTOEMODE_RSVD_MASK | DDR_PHY_RIOCR5_ODTOEMODE_MASK | 0 ); + * DQS Drift Detection Mode + * PSU_DDR_PHY_DQSDR0_DFTDTMODE 0x0 - RegVal = ((0x00000000U << DDR_PHY_RIOCR5_RESERVED_31_16_SHIFT - | 0x00000000U << DDR_PHY_RIOCR5_ODTOEMODE_RSVD_SHIFT - | 0x00000005U << DDR_PHY_RIOCR5_ODTOEMODE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_RIOCR5_OFFSET ,0xFFFFFFFFU ,0x00000005U); - /*############################################################################################################################ */ + * DQS Drift Detection Enable + * PSU_DDR_PHY_DQSDR0_DFTDTEN 0x0 - /*Register : ACIOCR0 @ 0XFD080500

+ * DQS Drift Register 0 + * (OFFSET, MASK, VALUE) (0XFD080250, 0xFFFFFFFFU ,0x00088000U) + */ + PSU_Mask_Write(DDR_PHY_DQSDR0_OFFSET, 0xFFFFFFFFU, 0x00088000U); +/*##################################################################### */ - Address/Command Slew Rate (D3F I/O Only) - PSU_DDR_PHY_ACIOCR0_ACSR 0x0 + /* + * Register : BISTLSR @ 0XFD080414 - SDRAM Reset I/O Mode - PSU_DDR_PHY_ACIOCR0_RSTIOM 0x1 + * LFSR seed for pseudo-random BIST patterns + * PSU_DDR_PHY_BISTLSR_SEED 0x12341000 - SDRAM Reset Power Down Receiver - PSU_DDR_PHY_ACIOCR0_RSTPDR 0x1 + * BIST LFSR Seed Register + * (OFFSET, MASK, VALUE) (0XFD080414, 0xFFFFFFFFU ,0x12341000U) + */ + PSU_Mask_Write(DDR_PHY_BISTLSR_OFFSET, 0xFFFFFFFFU, 0x12341000U); +/*##################################################################### */ - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACIOCR0_RESERVED_27 0x0 + /* + * Register : RIOCR5 @ 0XFD0804F4 - SDRAM Reset On-Die Termination - PSU_DDR_PHY_ACIOCR0_RSTODT 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_RIOCR5_RESERVED_31_16 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACIOCR0_RESERVED_25_10 0x0 + * Reserved. Return zeros on reads. + * PSU_DDR_PHY_RIOCR5_ODTOEMODE_RSVD 0x0 - CK Duty Cycle Correction - PSU_DDR_PHY_ACIOCR0_CKDCC 0x0 + * SDRAM On-die Termination Output Enable (OE) Mode Selection. + * PSU_DDR_PHY_RIOCR5_ODTOEMODE 0x5 - AC Power Down Receiver Mode - PSU_DDR_PHY_ACIOCR0_ACPDRMODE 0x2 + * Rank I/O Configuration Register 5 + * (OFFSET, MASK, VALUE) (0XFD0804F4, 0xFFFFFFFFU ,0x00000005U) + */ + PSU_Mask_Write(DDR_PHY_RIOCR5_OFFSET, 0xFFFFFFFFU, 0x00000005U); +/*##################################################################### */ - AC On-die Termination Mode - PSU_DDR_PHY_ACIOCR0_ACODTMODE 0x2 + /* + * Register : ACIOCR0 @ 0XFD080500 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACIOCR0_RESERVED_1 0x0 + * Address/Command Slew Rate (D3F I/O Only) + * PSU_DDR_PHY_ACIOCR0_ACSR 0x0 - Control delayed or non-delayed clock to CS_N/ODT?CKE AC slices. - PSU_DDR_PHY_ACIOCR0_ACRANKCLKSEL 0x0 + * SDRAM Reset I/O Mode + * PSU_DDR_PHY_ACIOCR0_RSTIOM 0x1 - AC I/O Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD080500, 0xFFFFFFFFU ,0x30000028U) - RegMask = (DDR_PHY_ACIOCR0_ACSR_MASK | DDR_PHY_ACIOCR0_RSTIOM_MASK | DDR_PHY_ACIOCR0_RSTPDR_MASK | DDR_PHY_ACIOCR0_RESERVED_27_MASK | DDR_PHY_ACIOCR0_RSTODT_MASK | DDR_PHY_ACIOCR0_RESERVED_25_10_MASK | DDR_PHY_ACIOCR0_CKDCC_MASK | DDR_PHY_ACIOCR0_ACPDRMODE_MASK | DDR_PHY_ACIOCR0_ACODTMODE_MASK | DDR_PHY_ACIOCR0_RESERVED_1_MASK | DDR_PHY_ACIOCR0_ACRANKCLKSEL_MASK | 0 ); + * SDRAM Reset Power Down Receiver + * PSU_DDR_PHY_ACIOCR0_RSTPDR 0x1 - RegVal = ((0x00000000U << DDR_PHY_ACIOCR0_ACSR_SHIFT - | 0x00000001U << DDR_PHY_ACIOCR0_RSTIOM_SHIFT - | 0x00000001U << DDR_PHY_ACIOCR0_RSTPDR_SHIFT - | 0x00000000U << DDR_PHY_ACIOCR0_RESERVED_27_SHIFT - | 0x00000000U << DDR_PHY_ACIOCR0_RSTODT_SHIFT - | 0x00000000U << DDR_PHY_ACIOCR0_RESERVED_25_10_SHIFT - | 0x00000000U << DDR_PHY_ACIOCR0_CKDCC_SHIFT - | 0x00000002U << DDR_PHY_ACIOCR0_ACPDRMODE_SHIFT - | 0x00000002U << DDR_PHY_ACIOCR0_ACODTMODE_SHIFT - | 0x00000000U << DDR_PHY_ACIOCR0_RESERVED_1_SHIFT - | 0x00000000U << DDR_PHY_ACIOCR0_ACRANKCLKSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_ACIOCR0_OFFSET ,0xFFFFFFFFU ,0x30000028U); - /*############################################################################################################################ */ + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACIOCR0_RESERVED_27 0x0 - /*Register : ACIOCR2 @ 0XFD080508

+ * SDRAM Reset On-Die Termination + * PSU_DDR_PHY_ACIOCR0_RSTODT 0x0 - Clock gating for glue logic inside CLKGEN and glue logic inside CONTROL slice - PSU_DDR_PHY_ACIOCR2_CLKGENCLKGATE 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACIOCR0_RESERVED_25_10 0x0 - Clock gating for Output Enable D slices [0] - PSU_DDR_PHY_ACIOCR2_ACOECLKGATE0 0x0 + * CK Duty Cycle Correction + * PSU_DDR_PHY_ACIOCR0_CKDCC 0x0 - Clock gating for Power Down Receiver D slices [0] - PSU_DDR_PHY_ACIOCR2_ACPDRCLKGATE0 0x0 + * AC Power Down Receiver Mode + * PSU_DDR_PHY_ACIOCR0_ACPDRMODE 0x2 - Clock gating for Termination Enable D slices [0] - PSU_DDR_PHY_ACIOCR2_ACTECLKGATE0 0x0 + * AC On-die Termination Mode + * PSU_DDR_PHY_ACIOCR0_ACODTMODE 0x2 - Clock gating for CK# D slices [1:0] - PSU_DDR_PHY_ACIOCR2_CKNCLKGATE0 0x2 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACIOCR0_RESERVED_1 0x0 - Clock gating for CK D slices [1:0] - PSU_DDR_PHY_ACIOCR2_CKCLKGATE0 0x2 + * Control delayed or non-delayed clock to CS_N/ODT?CKE AC slices. + * PSU_DDR_PHY_ACIOCR0_ACRANKCLKSEL 0x0 - Clock gating for AC D slices [23:0] - PSU_DDR_PHY_ACIOCR2_ACCLKGATE0 0x0 + * AC I/O Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD080500, 0xFFFFFFFFU ,0x30000028U) + */ + PSU_Mask_Write(DDR_PHY_ACIOCR0_OFFSET, 0xFFFFFFFFU, 0x30000028U); +/*##################################################################### */ - AC I/O Configuration Register 2 - (OFFSET, MASK, VALUE) (0XFD080508, 0xFFFFFFFFU ,0x0A000000U) - RegMask = (DDR_PHY_ACIOCR2_CLKGENCLKGATE_MASK | DDR_PHY_ACIOCR2_ACOECLKGATE0_MASK | DDR_PHY_ACIOCR2_ACPDRCLKGATE0_MASK | DDR_PHY_ACIOCR2_ACTECLKGATE0_MASK | DDR_PHY_ACIOCR2_CKNCLKGATE0_MASK | DDR_PHY_ACIOCR2_CKCLKGATE0_MASK | DDR_PHY_ACIOCR2_ACCLKGATE0_MASK | 0 ); + /* + * Register : ACIOCR2 @ 0XFD080508 - RegVal = ((0x00000000U << DDR_PHY_ACIOCR2_CLKGENCLKGATE_SHIFT - | 0x00000000U << DDR_PHY_ACIOCR2_ACOECLKGATE0_SHIFT - | 0x00000000U << DDR_PHY_ACIOCR2_ACPDRCLKGATE0_SHIFT - | 0x00000000U << DDR_PHY_ACIOCR2_ACTECLKGATE0_SHIFT - | 0x00000002U << DDR_PHY_ACIOCR2_CKNCLKGATE0_SHIFT - | 0x00000002U << DDR_PHY_ACIOCR2_CKCLKGATE0_SHIFT - | 0x00000000U << DDR_PHY_ACIOCR2_ACCLKGATE0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_ACIOCR2_OFFSET ,0xFFFFFFFFU ,0x0A000000U); - /*############################################################################################################################ */ + * Clock gating for glue logic inside CLKGEN and glue logic inside CONTROL + * slice + * PSU_DDR_PHY_ACIOCR2_CLKGENCLKGATE 0x0 - /*Register : ACIOCR3 @ 0XFD08050C

+ * Clock gating for Output Enable D slices [0] + * PSU_DDR_PHY_ACIOCR2_ACOECLKGATE0 0x0 - SDRAM Parity Output Enable (OE) Mode Selection - PSU_DDR_PHY_ACIOCR3_PAROEMODE 0x0 + * Clock gating for Power Down Receiver D slices [0] + * PSU_DDR_PHY_ACIOCR2_ACPDRCLKGATE0 0x0 - SDRAM Bank Group Output Enable (OE) Mode Selection - PSU_DDR_PHY_ACIOCR3_BGOEMODE 0x0 + * Clock gating for Termination Enable D slices [0] + * PSU_DDR_PHY_ACIOCR2_ACTECLKGATE0 0x0 - SDRAM Bank Address Output Enable (OE) Mode Selection - PSU_DDR_PHY_ACIOCR3_BAOEMODE 0x0 + * Clock gating for CK# D slices [1:0] + * PSU_DDR_PHY_ACIOCR2_CKNCLKGATE0 0x2 - SDRAM A[17] Output Enable (OE) Mode Selection - PSU_DDR_PHY_ACIOCR3_A17OEMODE 0x0 + * Clock gating for CK D slices [1:0] + * PSU_DDR_PHY_ACIOCR2_CKCLKGATE0 0x2 - SDRAM A[16] / RAS_n Output Enable (OE) Mode Selection - PSU_DDR_PHY_ACIOCR3_A16OEMODE 0x0 + * Clock gating for AC D slices [23:0] + * PSU_DDR_PHY_ACIOCR2_ACCLKGATE0 0x0 - SDRAM ACT_n Output Enable (OE) Mode Selection (DDR4 only) - PSU_DDR_PHY_ACIOCR3_ACTOEMODE 0x0 + * AC I/O Configuration Register 2 + * (OFFSET, MASK, VALUE) (0XFD080508, 0xFFFFFFFFU ,0x0A000000U) + */ + PSU_Mask_Write(DDR_PHY_ACIOCR2_OFFSET, 0xFFFFFFFFU, 0x0A000000U); +/*##################################################################### */ - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACIOCR3_RESERVED_15_8 0x0 + /* + * Register : ACIOCR3 @ 0XFD08050C - Reserved. Return zeros on reads. - PSU_DDR_PHY_ACIOCR3_CKOEMODE_RSVD 0x0 + * SDRAM Parity Output Enable (OE) Mode Selection + * PSU_DDR_PHY_ACIOCR3_PAROEMODE 0x0 - SDRAM CK Output Enable (OE) Mode Selection. - PSU_DDR_PHY_ACIOCR3_CKOEMODE 0x9 + * SDRAM Bank Group Output Enable (OE) Mode Selection + * PSU_DDR_PHY_ACIOCR3_BGOEMODE 0x0 - AC I/O Configuration Register 3 - (OFFSET, MASK, VALUE) (0XFD08050C, 0xFFFFFFFFU ,0x00000009U) - RegMask = (DDR_PHY_ACIOCR3_PAROEMODE_MASK | DDR_PHY_ACIOCR3_BGOEMODE_MASK | DDR_PHY_ACIOCR3_BAOEMODE_MASK | DDR_PHY_ACIOCR3_A17OEMODE_MASK | DDR_PHY_ACIOCR3_A16OEMODE_MASK | DDR_PHY_ACIOCR3_ACTOEMODE_MASK | DDR_PHY_ACIOCR3_RESERVED_15_8_MASK | DDR_PHY_ACIOCR3_CKOEMODE_RSVD_MASK | DDR_PHY_ACIOCR3_CKOEMODE_MASK | 0 ); + * SDRAM Bank Address Output Enable (OE) Mode Selection + * PSU_DDR_PHY_ACIOCR3_BAOEMODE 0x0 - RegVal = ((0x00000000U << DDR_PHY_ACIOCR3_PAROEMODE_SHIFT - | 0x00000000U << DDR_PHY_ACIOCR3_BGOEMODE_SHIFT - | 0x00000000U << DDR_PHY_ACIOCR3_BAOEMODE_SHIFT - | 0x00000000U << DDR_PHY_ACIOCR3_A17OEMODE_SHIFT - | 0x00000000U << DDR_PHY_ACIOCR3_A16OEMODE_SHIFT - | 0x00000000U << DDR_PHY_ACIOCR3_ACTOEMODE_SHIFT - | 0x00000000U << DDR_PHY_ACIOCR3_RESERVED_15_8_SHIFT - | 0x00000000U << DDR_PHY_ACIOCR3_CKOEMODE_RSVD_SHIFT - | 0x00000009U << DDR_PHY_ACIOCR3_CKOEMODE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_ACIOCR3_OFFSET ,0xFFFFFFFFU ,0x00000009U); - /*############################################################################################################################ */ + * SDRAM A[17] Output Enable (OE) Mode Selection + * PSU_DDR_PHY_ACIOCR3_A17OEMODE 0x0 - /*Register : ACIOCR4 @ 0XFD080510

+ * SDRAM A[16] / RAS_n Output Enable (OE) Mode Selection + * PSU_DDR_PHY_ACIOCR3_A16OEMODE 0x0 - Clock gating for AC LB slices and loopback read valid slices - PSU_DDR_PHY_ACIOCR4_LBCLKGATE 0x0 + * SDRAM ACT_n Output Enable (OE) Mode Selection (DDR4 only) + * PSU_DDR_PHY_ACIOCR3_ACTOEMODE 0x0 - Clock gating for Output Enable D slices [1] - PSU_DDR_PHY_ACIOCR4_ACOECLKGATE1 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACIOCR3_RESERVED_15_8 0x0 - Clock gating for Power Down Receiver D slices [1] - PSU_DDR_PHY_ACIOCR4_ACPDRCLKGATE1 0x0 + * Reserved. Return zeros on reads. + * PSU_DDR_PHY_ACIOCR3_CKOEMODE_RSVD 0x0 - Clock gating for Termination Enable D slices [1] - PSU_DDR_PHY_ACIOCR4_ACTECLKGATE1 0x0 + * SDRAM CK Output Enable (OE) Mode Selection. + * PSU_DDR_PHY_ACIOCR3_CKOEMODE 0x9 - Clock gating for CK# D slices [3:2] - PSU_DDR_PHY_ACIOCR4_CKNCLKGATE1 0x2 + * AC I/O Configuration Register 3 + * (OFFSET, MASK, VALUE) (0XFD08050C, 0xFFFFFFFFU ,0x00000009U) + */ + PSU_Mask_Write(DDR_PHY_ACIOCR3_OFFSET, 0xFFFFFFFFU, 0x00000009U); +/*##################################################################### */ - Clock gating for CK D slices [3:2] - PSU_DDR_PHY_ACIOCR4_CKCLKGATE1 0x2 + /* + * Register : ACIOCR4 @ 0XFD080510 - Clock gating for AC D slices [47:24] - PSU_DDR_PHY_ACIOCR4_ACCLKGATE1 0x0 + * Clock gating for AC LB slices and loopback read valid slices + * PSU_DDR_PHY_ACIOCR4_LBCLKGATE 0x0 - AC I/O Configuration Register 4 - (OFFSET, MASK, VALUE) (0XFD080510, 0xFFFFFFFFU ,0x0A000000U) - RegMask = (DDR_PHY_ACIOCR4_LBCLKGATE_MASK | DDR_PHY_ACIOCR4_ACOECLKGATE1_MASK | DDR_PHY_ACIOCR4_ACPDRCLKGATE1_MASK | DDR_PHY_ACIOCR4_ACTECLKGATE1_MASK | DDR_PHY_ACIOCR4_CKNCLKGATE1_MASK | DDR_PHY_ACIOCR4_CKCLKGATE1_MASK | DDR_PHY_ACIOCR4_ACCLKGATE1_MASK | 0 ); + * Clock gating for Output Enable D slices [1] + * PSU_DDR_PHY_ACIOCR4_ACOECLKGATE1 0x0 - RegVal = ((0x00000000U << DDR_PHY_ACIOCR4_LBCLKGATE_SHIFT - | 0x00000000U << DDR_PHY_ACIOCR4_ACOECLKGATE1_SHIFT - | 0x00000000U << DDR_PHY_ACIOCR4_ACPDRCLKGATE1_SHIFT - | 0x00000000U << DDR_PHY_ACIOCR4_ACTECLKGATE1_SHIFT - | 0x00000002U << DDR_PHY_ACIOCR4_CKNCLKGATE1_SHIFT - | 0x00000002U << DDR_PHY_ACIOCR4_CKCLKGATE1_SHIFT - | 0x00000000U << DDR_PHY_ACIOCR4_ACCLKGATE1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_ACIOCR4_OFFSET ,0xFFFFFFFFU ,0x0A000000U); - /*############################################################################################################################ */ + * Clock gating for Power Down Receiver D slices [1] + * PSU_DDR_PHY_ACIOCR4_ACPDRCLKGATE1 0x0 - /*Register : IOVCR0 @ 0XFD080520

+ * Clock gating for Termination Enable D slices [1] + * PSU_DDR_PHY_ACIOCR4_ACTECLKGATE1 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_IOVCR0_RESERVED_31_29 0x0 + * Clock gating for CK# D slices [3:2] + * PSU_DDR_PHY_ACIOCR4_CKNCLKGATE1 0x2 - Address/command lane VREF Pad Enable - PSU_DDR_PHY_IOVCR0_ACREFPEN 0x0 + * Clock gating for CK D slices [3:2] + * PSU_DDR_PHY_ACIOCR4_CKCLKGATE1 0x2 - Address/command lane Internal VREF Enable - PSU_DDR_PHY_IOVCR0_ACREFEEN 0x0 + * Clock gating for AC D slices [47:24] + * PSU_DDR_PHY_ACIOCR4_ACCLKGATE1 0x0 - Address/command lane Single-End VREF Enable - PSU_DDR_PHY_IOVCR0_ACREFSEN 0x1 + * AC I/O Configuration Register 4 + * (OFFSET, MASK, VALUE) (0XFD080510, 0xFFFFFFFFU ,0x0A000000U) + */ + PSU_Mask_Write(DDR_PHY_ACIOCR4_OFFSET, 0xFFFFFFFFU, 0x0A000000U); +/*##################################################################### */ - Address/command lane Internal VREF Enable - PSU_DDR_PHY_IOVCR0_ACREFIEN 0x1 + /* + * Register : IOVCR0 @ 0XFD080520 - External VREF generato REFSEL range select - PSU_DDR_PHY_IOVCR0_ACREFESELRANGE 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_IOVCR0_RESERVED_31_29 0x0 - Address/command lane External VREF Select - PSU_DDR_PHY_IOVCR0_ACREFESEL 0x0 + * Address/command lane VREF Pad Enable + * PSU_DDR_PHY_IOVCR0_ACREFPEN 0x0 - Single ended VREF generator REFSEL range select - PSU_DDR_PHY_IOVCR0_ACREFSSELRANGE 0x1 + * Address/command lane Internal VREF Enable + * PSU_DDR_PHY_IOVCR0_ACREFEEN 0x0 - Address/command lane Single-End VREF Select - PSU_DDR_PHY_IOVCR0_ACREFSSEL 0x30 + * Address/command lane Single-End VREF Enable + * PSU_DDR_PHY_IOVCR0_ACREFSEN 0x1 - Internal VREF generator REFSEL ragne select - PSU_DDR_PHY_IOVCR0_ACVREFISELRANGE 0x1 + * Address/command lane Internal VREF Enable + * PSU_DDR_PHY_IOVCR0_ACREFIEN 0x1 - REFSEL Control for internal AC IOs - PSU_DDR_PHY_IOVCR0_ACVREFISEL 0x30 + * External VREF generato REFSEL range select + * PSU_DDR_PHY_IOVCR0_ACREFESELRANGE 0x0 - IO VREF Control Register 0 - (OFFSET, MASK, VALUE) (0XFD080520, 0xFFFFFFFFU ,0x0300B0B0U) - RegMask = (DDR_PHY_IOVCR0_RESERVED_31_29_MASK | DDR_PHY_IOVCR0_ACREFPEN_MASK | DDR_PHY_IOVCR0_ACREFEEN_MASK | DDR_PHY_IOVCR0_ACREFSEN_MASK | DDR_PHY_IOVCR0_ACREFIEN_MASK | DDR_PHY_IOVCR0_ACREFESELRANGE_MASK | DDR_PHY_IOVCR0_ACREFESEL_MASK | DDR_PHY_IOVCR0_ACREFSSELRANGE_MASK | DDR_PHY_IOVCR0_ACREFSSEL_MASK | DDR_PHY_IOVCR0_ACVREFISELRANGE_MASK | DDR_PHY_IOVCR0_ACVREFISEL_MASK | 0 ); + * Address/command lane External VREF Select + * PSU_DDR_PHY_IOVCR0_ACREFESEL 0x0 - RegVal = ((0x00000000U << DDR_PHY_IOVCR0_RESERVED_31_29_SHIFT - | 0x00000000U << DDR_PHY_IOVCR0_ACREFPEN_SHIFT - | 0x00000000U << DDR_PHY_IOVCR0_ACREFEEN_SHIFT - | 0x00000001U << DDR_PHY_IOVCR0_ACREFSEN_SHIFT - | 0x00000001U << DDR_PHY_IOVCR0_ACREFIEN_SHIFT - | 0x00000000U << DDR_PHY_IOVCR0_ACREFESELRANGE_SHIFT - | 0x00000000U << DDR_PHY_IOVCR0_ACREFESEL_SHIFT - | 0x00000001U << DDR_PHY_IOVCR0_ACREFSSELRANGE_SHIFT - | 0x00000030U << DDR_PHY_IOVCR0_ACREFSSEL_SHIFT - | 0x00000001U << DDR_PHY_IOVCR0_ACVREFISELRANGE_SHIFT - | 0x00000030U << DDR_PHY_IOVCR0_ACVREFISEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_IOVCR0_OFFSET ,0xFFFFFFFFU ,0x0300B0B0U); - /*############################################################################################################################ */ + * Single ended VREF generator REFSEL range select + * PSU_DDR_PHY_IOVCR0_ACREFSSELRANGE 0x1 - /*Register : VTCR0 @ 0XFD080528

+ * Address/command lane Single-End VREF Select + * PSU_DDR_PHY_IOVCR0_ACREFSSEL 0x30 - Number of ctl_clk required to meet (> 150ns) timing requirements during DRAM DQ VREF training - PSU_DDR_PHY_VTCR0_TVREF 0x7 + * Internal VREF generator REFSEL ragne select + * PSU_DDR_PHY_IOVCR0_ACVREFISELRANGE 0x1 - DRM DQ VREF training Enable - PSU_DDR_PHY_VTCR0_DVEN 0x1 + * REFSEL Control for internal AC IOs + * PSU_DDR_PHY_IOVCR0_ACVREFISEL 0x4e - Per Device Addressability Enable - PSU_DDR_PHY_VTCR0_PDAEN 0x1 + * IO VREF Control Register 0 + * (OFFSET, MASK, VALUE) (0XFD080520, 0xFFFFFFFFU ,0x0300B0CEU) + */ + PSU_Mask_Write(DDR_PHY_IOVCR0_OFFSET, 0xFFFFFFFFU, 0x0300B0CEU); +/*##################################################################### */ - Reserved. Returns zeroes on reads. - PSU_DDR_PHY_VTCR0_RESERVED_26 0x0 + /* + * Register : VTCR0 @ 0XFD080528 - VREF Word Count - PSU_DDR_PHY_VTCR0_VWCR 0x4 + * Number of ctl_clk required to meet (> 150ns) timing requirements during + * DRAM DQ VREF training + * PSU_DDR_PHY_VTCR0_TVREF 0x7 - DRAM DQ VREF step size used during DRAM VREF training - PSU_DDR_PHY_VTCR0_DVSS 0x0 + * DRM DQ VREF training Enable + * PSU_DDR_PHY_VTCR0_DVEN 0x1 - Maximum VREF limit value used during DRAM VREF training - PSU_DDR_PHY_VTCR0_DVMAX 0x32 + * Per Device Addressability Enable + * PSU_DDR_PHY_VTCR0_PDAEN 0x1 - Minimum VREF limit value used during DRAM VREF training - PSU_DDR_PHY_VTCR0_DVMIN 0x0 + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_VTCR0_RESERVED_26 0x0 - Initial DRAM DQ VREF value used during DRAM VREF training - PSU_DDR_PHY_VTCR0_DVINIT 0x19 + * VREF Word Count + * PSU_DDR_PHY_VTCR0_VWCR 0x4 - VREF Training Control Register 0 - (OFFSET, MASK, VALUE) (0XFD080528, 0xFFFFFFFFU ,0xF9032019U) - RegMask = (DDR_PHY_VTCR0_TVREF_MASK | DDR_PHY_VTCR0_DVEN_MASK | DDR_PHY_VTCR0_PDAEN_MASK | DDR_PHY_VTCR0_RESERVED_26_MASK | DDR_PHY_VTCR0_VWCR_MASK | DDR_PHY_VTCR0_DVSS_MASK | DDR_PHY_VTCR0_DVMAX_MASK | DDR_PHY_VTCR0_DVMIN_MASK | DDR_PHY_VTCR0_DVINIT_MASK | 0 ); + * DRAM DQ VREF step size used during DRAM VREF training + * PSU_DDR_PHY_VTCR0_DVSS 0x0 - RegVal = ((0x00000007U << DDR_PHY_VTCR0_TVREF_SHIFT - | 0x00000001U << DDR_PHY_VTCR0_DVEN_SHIFT - | 0x00000001U << DDR_PHY_VTCR0_PDAEN_SHIFT - | 0x00000000U << DDR_PHY_VTCR0_RESERVED_26_SHIFT - | 0x00000004U << DDR_PHY_VTCR0_VWCR_SHIFT - | 0x00000000U << DDR_PHY_VTCR0_DVSS_SHIFT - | 0x00000032U << DDR_PHY_VTCR0_DVMAX_SHIFT - | 0x00000000U << DDR_PHY_VTCR0_DVMIN_SHIFT - | 0x00000019U << DDR_PHY_VTCR0_DVINIT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_VTCR0_OFFSET ,0xFFFFFFFFU ,0xF9032019U); - /*############################################################################################################################ */ + * Maximum VREF limit value used during DRAM VREF training + * PSU_DDR_PHY_VTCR0_DVMAX 0x32 - /*Register : VTCR1 @ 0XFD08052C

+ * Minimum VREF limit value used during DRAM VREF training + * PSU_DDR_PHY_VTCR0_DVMIN 0x0 - Host VREF step size used during VREF training. The register value of N indicates step size of (N+1) - PSU_DDR_PHY_VTCR1_HVSS 0x0 + * Initial DRAM DQ VREF value used during DRAM VREF training + * PSU_DDR_PHY_VTCR0_DVINIT 0x19 - Reserved. Returns zeroes on reads. - PSU_DDR_PHY_VTCR1_RESERVED_27 0x0 + * VREF Training Control Register 0 + * (OFFSET, MASK, VALUE) (0XFD080528, 0xFFFFFFFFU ,0xF9032019U) + */ + PSU_Mask_Write(DDR_PHY_VTCR0_OFFSET, 0xFFFFFFFFU, 0xF9032019U); +/*##################################################################### */ - Maximum VREF limit value used during DRAM VREF training. - PSU_DDR_PHY_VTCR1_HVMAX 0x7f + /* + * Register : VTCR1 @ 0XFD08052C - Reserved. Returns zeroes on reads. - PSU_DDR_PHY_VTCR1_RESERVED_19 0x0 + * Host VREF step size used during VREF training. The register value of N i + * ndicates step size of (N+1) + * PSU_DDR_PHY_VTCR1_HVSS 0x0 - Minimum VREF limit value used during DRAM VREF training. - PSU_DDR_PHY_VTCR1_HVMIN 0x0 + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_VTCR1_RESERVED_27 0x0 - Reserved. Returns zeroes on reads. - PSU_DDR_PHY_VTCR1_RESERVED_11 0x0 + * Maximum VREF limit value used during DRAM VREF training. + * PSU_DDR_PHY_VTCR1_HVMAX 0x7f - Static Host Vref Rank Value - PSU_DDR_PHY_VTCR1_SHRNK 0x0 + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_VTCR1_RESERVED_19 0x0 - Static Host Vref Rank Enable - PSU_DDR_PHY_VTCR1_SHREN 0x1 + * Minimum VREF limit value used during DRAM VREF training. + * PSU_DDR_PHY_VTCR1_HVMIN 0x0 - Number of ctl_clk required to meet (> 200ns) VREF Settling timing requirements during Host IO VREF training - PSU_DDR_PHY_VTCR1_TVREFIO 0x7 + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_VTCR1_RESERVED_11 0x0 - Eye LCDL Offset value for VREF training - PSU_DDR_PHY_VTCR1_EOFF 0x0 + * Static Host Vref Rank Value + * PSU_DDR_PHY_VTCR1_SHRNK 0x0 - Number of LCDL Eye points for which VREF training is repeated - PSU_DDR_PHY_VTCR1_ENUM 0x0 + * Static Host Vref Rank Enable + * PSU_DDR_PHY_VTCR1_SHREN 0x1 - HOST (IO) internal VREF training Enable - PSU_DDR_PHY_VTCR1_HVEN 0x1 + * Number of ctl_clk required to meet (> 200ns) VREF Settling timing requir + * ements during Host IO VREF training + * PSU_DDR_PHY_VTCR1_TVREFIO 0x7 - Host IO Type Control - PSU_DDR_PHY_VTCR1_HVIO 0x1 + * Eye LCDL Offset value for VREF training + * PSU_DDR_PHY_VTCR1_EOFF 0x0 - VREF Training Control Register 1 - (OFFSET, MASK, VALUE) (0XFD08052C, 0xFFFFFFFFU ,0x07F001E3U) - RegMask = (DDR_PHY_VTCR1_HVSS_MASK | DDR_PHY_VTCR1_RESERVED_27_MASK | DDR_PHY_VTCR1_HVMAX_MASK | DDR_PHY_VTCR1_RESERVED_19_MASK | DDR_PHY_VTCR1_HVMIN_MASK | DDR_PHY_VTCR1_RESERVED_11_MASK | DDR_PHY_VTCR1_SHRNK_MASK | DDR_PHY_VTCR1_SHREN_MASK | DDR_PHY_VTCR1_TVREFIO_MASK | DDR_PHY_VTCR1_EOFF_MASK | DDR_PHY_VTCR1_ENUM_MASK | DDR_PHY_VTCR1_HVEN_MASK | DDR_PHY_VTCR1_HVIO_MASK | 0 ); + * Number of LCDL Eye points for which VREF training is repeated + * PSU_DDR_PHY_VTCR1_ENUM 0x0 - RegVal = ((0x00000000U << DDR_PHY_VTCR1_HVSS_SHIFT - | 0x00000000U << DDR_PHY_VTCR1_RESERVED_27_SHIFT - | 0x0000007FU << DDR_PHY_VTCR1_HVMAX_SHIFT - | 0x00000000U << DDR_PHY_VTCR1_RESERVED_19_SHIFT - | 0x00000000U << DDR_PHY_VTCR1_HVMIN_SHIFT - | 0x00000000U << DDR_PHY_VTCR1_RESERVED_11_SHIFT - | 0x00000000U << DDR_PHY_VTCR1_SHRNK_SHIFT - | 0x00000001U << DDR_PHY_VTCR1_SHREN_SHIFT - | 0x00000007U << DDR_PHY_VTCR1_TVREFIO_SHIFT - | 0x00000000U << DDR_PHY_VTCR1_EOFF_SHIFT - | 0x00000000U << DDR_PHY_VTCR1_ENUM_SHIFT - | 0x00000001U << DDR_PHY_VTCR1_HVEN_SHIFT - | 0x00000001U << DDR_PHY_VTCR1_HVIO_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_VTCR1_OFFSET ,0xFFFFFFFFU ,0x07F001E3U); - /*############################################################################################################################ */ + * HOST (IO) internal VREF training Enable + * PSU_DDR_PHY_VTCR1_HVEN 0x1 - /*Register : ACBDLR1 @ 0XFD080544

+ * Host IO Type Control + * PSU_DDR_PHY_VTCR1_HVIO 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR1_RESERVED_31_30 0x0 + * VREF Training Control Register 1 + * (OFFSET, MASK, VALUE) (0XFD08052C, 0xFFFFFFFFU ,0x07F001E3U) + */ + PSU_Mask_Write(DDR_PHY_VTCR1_OFFSET, 0xFFFFFFFFU, 0x07F001E3U); +/*##################################################################### */ - Delay select for the BDL on Parity. - PSU_DDR_PHY_ACBDLR1_PARBD 0x0 + /* + * Register : ACBDLR1 @ 0XFD080544 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR1_RESERVED_23_22 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR1_RESERVED_31_30 0x0 - Delay select for the BDL on Address A[16]. In DDR3 mode this pin is connected to WE. - PSU_DDR_PHY_ACBDLR1_A16BD 0x0 + * Delay select for the BDL on Parity. + * PSU_DDR_PHY_ACBDLR1_PARBD 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR1_RESERVED_15_14 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR1_RESERVED_23_22 0x0 - Delay select for the BDL on Address A[17]. When not in DDR4 modemode this pin is connected to CAS. - PSU_DDR_PHY_ACBDLR1_A17BD 0x0 + * Delay select for the BDL on Address A[16]. In DDR3 mode this pin is conn + * ected to WE. + * PSU_DDR_PHY_ACBDLR1_A16BD 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR1_RESERVED_7_6 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR1_RESERVED_15_14 0x0 - Delay select for the BDL on ACTN. - PSU_DDR_PHY_ACBDLR1_ACTBD 0x0 + * Delay select for the BDL on Address A[17]. When not in DDR4 modemode thi + * s pin is connected to CAS. + * PSU_DDR_PHY_ACBDLR1_A17BD 0x0 - AC Bit Delay Line Register 1 - (OFFSET, MASK, VALUE) (0XFD080544, 0xFFFFFFFFU ,0x00000000U) - RegMask = (DDR_PHY_ACBDLR1_RESERVED_31_30_MASK | DDR_PHY_ACBDLR1_PARBD_MASK | DDR_PHY_ACBDLR1_RESERVED_23_22_MASK | DDR_PHY_ACBDLR1_A16BD_MASK | DDR_PHY_ACBDLR1_RESERVED_15_14_MASK | DDR_PHY_ACBDLR1_A17BD_MASK | DDR_PHY_ACBDLR1_RESERVED_7_6_MASK | DDR_PHY_ACBDLR1_ACTBD_MASK | 0 ); + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR1_RESERVED_7_6 0x0 - RegVal = ((0x00000000U << DDR_PHY_ACBDLR1_RESERVED_31_30_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR1_PARBD_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR1_RESERVED_23_22_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR1_A16BD_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR1_RESERVED_15_14_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR1_A17BD_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR1_RESERVED_7_6_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR1_ACTBD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_ACBDLR1_OFFSET ,0xFFFFFFFFU ,0x00000000U); - /*############################################################################################################################ */ + * Delay select for the BDL on ACTN. + * PSU_DDR_PHY_ACBDLR1_ACTBD 0x0 - /*Register : ACBDLR2 @ 0XFD080548

+ * AC Bit Delay Line Register 1 + * (OFFSET, MASK, VALUE) (0XFD080544, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDR_PHY_ACBDLR1_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR2_RESERVED_31_30 0x0 + /* + * Register : ACBDLR2 @ 0XFD080548 - Delay select for the BDL on BG[1]. - PSU_DDR_PHY_ACBDLR2_BG1BD 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR2_RESERVED_31_30 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR2_RESERVED_23_22 0x0 + * Delay select for the BDL on BG[1]. + * PSU_DDR_PHY_ACBDLR2_BG1BD 0x0 - Delay select for the BDL on BG[0]. - PSU_DDR_PHY_ACBDLR2_BG0BD 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR2_RESERVED_23_22 0x0 - Reser.ved Return zeroes on reads. - PSU_DDR_PHY_ACBDLR2_RESERVED_15_14 0x0 + * Delay select for the BDL on BG[0]. + * PSU_DDR_PHY_ACBDLR2_BG0BD 0x0 - Delay select for the BDL on BA[1]. - PSU_DDR_PHY_ACBDLR2_BA1BD 0x0 + * Reser.ved Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR2_RESERVED_15_14 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR2_RESERVED_7_6 0x0 + * Delay select for the BDL on BA[1]. + * PSU_DDR_PHY_ACBDLR2_BA1BD 0x0 - Delay select for the BDL on BA[0]. - PSU_DDR_PHY_ACBDLR2_BA0BD 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR2_RESERVED_7_6 0x0 - AC Bit Delay Line Register 2 - (OFFSET, MASK, VALUE) (0XFD080548, 0xFFFFFFFFU ,0x00000000U) - RegMask = (DDR_PHY_ACBDLR2_RESERVED_31_30_MASK | DDR_PHY_ACBDLR2_BG1BD_MASK | DDR_PHY_ACBDLR2_RESERVED_23_22_MASK | DDR_PHY_ACBDLR2_BG0BD_MASK | DDR_PHY_ACBDLR2_RESERVED_15_14_MASK | DDR_PHY_ACBDLR2_BA1BD_MASK | DDR_PHY_ACBDLR2_RESERVED_7_6_MASK | DDR_PHY_ACBDLR2_BA0BD_MASK | 0 ); + * Delay select for the BDL on BA[0]. + * PSU_DDR_PHY_ACBDLR2_BA0BD 0x0 - RegVal = ((0x00000000U << DDR_PHY_ACBDLR2_RESERVED_31_30_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR2_BG1BD_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR2_RESERVED_23_22_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR2_BG0BD_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR2_RESERVED_15_14_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR2_BA1BD_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR2_RESERVED_7_6_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR2_BA0BD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_ACBDLR2_OFFSET ,0xFFFFFFFFU ,0x00000000U); - /*############################################################################################################################ */ + * AC Bit Delay Line Register 2 + * (OFFSET, MASK, VALUE) (0XFD080548, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDR_PHY_ACBDLR2_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ - /*Register : ACBDLR6 @ 0XFD080558

+ /* + * Register : ACBDLR6 @ 0XFD080558 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR6_RESERVED_31_30 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR6_RESERVED_31_30 0x0 - Delay select for the BDL on Address A[3]. - PSU_DDR_PHY_ACBDLR6_A03BD 0x0 + * Delay select for the BDL on Address A[3]. + * PSU_DDR_PHY_ACBDLR6_A03BD 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR6_RESERVED_23_22 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR6_RESERVED_23_22 0x0 - Delay select for the BDL on Address A[2]. - PSU_DDR_PHY_ACBDLR6_A02BD 0x0 + * Delay select for the BDL on Address A[2]. + * PSU_DDR_PHY_ACBDLR6_A02BD 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR6_RESERVED_15_14 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR6_RESERVED_15_14 0x0 - Delay select for the BDL on Address A[1]. - PSU_DDR_PHY_ACBDLR6_A01BD 0x0 + * Delay select for the BDL on Address A[1]. + * PSU_DDR_PHY_ACBDLR6_A01BD 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR6_RESERVED_7_6 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR6_RESERVED_7_6 0x0 - Delay select for the BDL on Address A[0]. - PSU_DDR_PHY_ACBDLR6_A00BD 0x0 + * Delay select for the BDL on Address A[0]. + * PSU_DDR_PHY_ACBDLR6_A00BD 0x0 - AC Bit Delay Line Register 6 - (OFFSET, MASK, VALUE) (0XFD080558, 0xFFFFFFFFU ,0x00000000U) - RegMask = (DDR_PHY_ACBDLR6_RESERVED_31_30_MASK | DDR_PHY_ACBDLR6_A03BD_MASK | DDR_PHY_ACBDLR6_RESERVED_23_22_MASK | DDR_PHY_ACBDLR6_A02BD_MASK | DDR_PHY_ACBDLR6_RESERVED_15_14_MASK | DDR_PHY_ACBDLR6_A01BD_MASK | DDR_PHY_ACBDLR6_RESERVED_7_6_MASK | DDR_PHY_ACBDLR6_A00BD_MASK | 0 ); + * AC Bit Delay Line Register 6 + * (OFFSET, MASK, VALUE) (0XFD080558, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDR_PHY_ACBDLR6_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ - RegVal = ((0x00000000U << DDR_PHY_ACBDLR6_RESERVED_31_30_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR6_A03BD_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR6_RESERVED_23_22_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR6_A02BD_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR6_RESERVED_15_14_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR6_A01BD_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR6_RESERVED_7_6_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR6_A00BD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_ACBDLR6_OFFSET ,0xFFFFFFFFU ,0x00000000U); - /*############################################################################################################################ */ + /* + * Register : ACBDLR7 @ 0XFD08055C - /*Register : ACBDLR7 @ 0XFD08055C

+ * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR7_RESERVED_31_30 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR7_RESERVED_31_30 0x0 + * Delay select for the BDL on Address A[7]. + * PSU_DDR_PHY_ACBDLR7_A07BD 0x0 - Delay select for the BDL on Address A[7]. - PSU_DDR_PHY_ACBDLR7_A07BD 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR7_RESERVED_23_22 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR7_RESERVED_23_22 0x0 + * Delay select for the BDL on Address A[6]. + * PSU_DDR_PHY_ACBDLR7_A06BD 0x0 - Delay select for the BDL on Address A[6]. - PSU_DDR_PHY_ACBDLR7_A06BD 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR7_RESERVED_15_14 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR7_RESERVED_15_14 0x0 + * Delay select for the BDL on Address A[5]. + * PSU_DDR_PHY_ACBDLR7_A05BD 0x0 - Delay select for the BDL on Address A[5]. - PSU_DDR_PHY_ACBDLR7_A05BD 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR7_RESERVED_7_6 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR7_RESERVED_7_6 0x0 + * Delay select for the BDL on Address A[4]. + * PSU_DDR_PHY_ACBDLR7_A04BD 0x0 - Delay select for the BDL on Address A[4]. - PSU_DDR_PHY_ACBDLR7_A04BD 0x0 + * AC Bit Delay Line Register 7 + * (OFFSET, MASK, VALUE) (0XFD08055C, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDR_PHY_ACBDLR7_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ - AC Bit Delay Line Register 7 - (OFFSET, MASK, VALUE) (0XFD08055C, 0xFFFFFFFFU ,0x00000000U) - RegMask = (DDR_PHY_ACBDLR7_RESERVED_31_30_MASK | DDR_PHY_ACBDLR7_A07BD_MASK | DDR_PHY_ACBDLR7_RESERVED_23_22_MASK | DDR_PHY_ACBDLR7_A06BD_MASK | DDR_PHY_ACBDLR7_RESERVED_15_14_MASK | DDR_PHY_ACBDLR7_A05BD_MASK | DDR_PHY_ACBDLR7_RESERVED_7_6_MASK | DDR_PHY_ACBDLR7_A04BD_MASK | 0 ); + /* + * Register : ACBDLR8 @ 0XFD080560 - RegVal = ((0x00000000U << DDR_PHY_ACBDLR7_RESERVED_31_30_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR7_A07BD_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR7_RESERVED_23_22_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR7_A06BD_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR7_RESERVED_15_14_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR7_A05BD_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR7_RESERVED_7_6_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR7_A04BD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_ACBDLR7_OFFSET ,0xFFFFFFFFU ,0x00000000U); - /*############################################################################################################################ */ + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR8_RESERVED_31_30 0x0 - /*Register : ACBDLR8 @ 0XFD080560

+ * Delay select for the BDL on Address A[11]. + * PSU_DDR_PHY_ACBDLR8_A11BD 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR8_RESERVED_31_30 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR8_RESERVED_23_22 0x0 - Delay select for the BDL on Address A[11]. - PSU_DDR_PHY_ACBDLR8_A11BD 0x0 + * Delay select for the BDL on Address A[10]. + * PSU_DDR_PHY_ACBDLR8_A10BD 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR8_RESERVED_23_22 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR8_RESERVED_15_14 0x0 - Delay select for the BDL on Address A[10]. - PSU_DDR_PHY_ACBDLR8_A10BD 0x0 + * Delay select for the BDL on Address A[9]. + * PSU_DDR_PHY_ACBDLR8_A09BD 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR8_RESERVED_15_14 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR8_RESERVED_7_6 0x0 - Delay select for the BDL on Address A[9]. - PSU_DDR_PHY_ACBDLR8_A09BD 0x0 + * Delay select for the BDL on Address A[8]. + * PSU_DDR_PHY_ACBDLR8_A08BD 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR8_RESERVED_7_6 0x0 + * AC Bit Delay Line Register 8 + * (OFFSET, MASK, VALUE) (0XFD080560, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDR_PHY_ACBDLR8_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ - Delay select for the BDL on Address A[8]. - PSU_DDR_PHY_ACBDLR8_A08BD 0x0 + /* + * Register : ACBDLR9 @ 0XFD080564 - AC Bit Delay Line Register 8 - (OFFSET, MASK, VALUE) (0XFD080560, 0xFFFFFFFFU ,0x00000000U) - RegMask = (DDR_PHY_ACBDLR8_RESERVED_31_30_MASK | DDR_PHY_ACBDLR8_A11BD_MASK | DDR_PHY_ACBDLR8_RESERVED_23_22_MASK | DDR_PHY_ACBDLR8_A10BD_MASK | DDR_PHY_ACBDLR8_RESERVED_15_14_MASK | DDR_PHY_ACBDLR8_A09BD_MASK | DDR_PHY_ACBDLR8_RESERVED_7_6_MASK | DDR_PHY_ACBDLR8_A08BD_MASK | 0 ); + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR9_RESERVED_31_30 0x0 - RegVal = ((0x00000000U << DDR_PHY_ACBDLR8_RESERVED_31_30_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR8_A11BD_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR8_RESERVED_23_22_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR8_A10BD_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR8_RESERVED_15_14_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR8_A09BD_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR8_RESERVED_7_6_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR8_A08BD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_ACBDLR8_OFFSET ,0xFFFFFFFFU ,0x00000000U); - /*############################################################################################################################ */ + * Delay select for the BDL on Address A[15]. + * PSU_DDR_PHY_ACBDLR9_A15BD 0x0 - /*Register : ACBDLR9 @ 0XFD080564

+ * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR9_RESERVED_23_22 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR9_RESERVED_31_30 0x0 + * Delay select for the BDL on Address A[14]. + * PSU_DDR_PHY_ACBDLR9_A14BD 0x0 - Delay select for the BDL on Address A[15]. - PSU_DDR_PHY_ACBDLR9_A15BD 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR9_RESERVED_15_14 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR9_RESERVED_23_22 0x0 + * Delay select for the BDL on Address A[13]. + * PSU_DDR_PHY_ACBDLR9_A13BD 0x0 - Delay select for the BDL on Address A[14]. - PSU_DDR_PHY_ACBDLR9_A14BD 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR9_RESERVED_7_6 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR9_RESERVED_15_14 0x0 + * Delay select for the BDL on Address A[12]. + * PSU_DDR_PHY_ACBDLR9_A12BD 0x0 - Delay select for the BDL on Address A[13]. - PSU_DDR_PHY_ACBDLR9_A13BD 0x0 + * AC Bit Delay Line Register 9 + * (OFFSET, MASK, VALUE) (0XFD080564, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDR_PHY_ACBDLR9_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR9_RESERVED_7_6 0x0 + /* + * Register : ZQCR @ 0XFD080680 - Delay select for the BDL on Address A[12]. - PSU_DDR_PHY_ACBDLR9_A12BD 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ZQCR_RESERVED_31_26 0x0 - AC Bit Delay Line Register 9 - (OFFSET, MASK, VALUE) (0XFD080564, 0xFFFFFFFFU ,0x00000000U) - RegMask = (DDR_PHY_ACBDLR9_RESERVED_31_30_MASK | DDR_PHY_ACBDLR9_A15BD_MASK | DDR_PHY_ACBDLR9_RESERVED_23_22_MASK | DDR_PHY_ACBDLR9_A14BD_MASK | DDR_PHY_ACBDLR9_RESERVED_15_14_MASK | DDR_PHY_ACBDLR9_A13BD_MASK | DDR_PHY_ACBDLR9_RESERVED_7_6_MASK | DDR_PHY_ACBDLR9_A12BD_MASK | 0 ); + * ZQ VREF Range + * PSU_DDR_PHY_ZQCR_ZQREFISELRANGE 0x0 - RegVal = ((0x00000000U << DDR_PHY_ACBDLR9_RESERVED_31_30_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR9_A15BD_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR9_RESERVED_23_22_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR9_A14BD_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR9_RESERVED_15_14_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR9_A13BD_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR9_RESERVED_7_6_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR9_A12BD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_ACBDLR9_OFFSET ,0xFFFFFFFFU ,0x00000000U); - /*############################################################################################################################ */ + * Programmable Wait for Frequency B + * PSU_DDR_PHY_ZQCR_PGWAIT_FRQB 0x11 - /*Register : ZQCR @ 0XFD080680

+ * Programmable Wait for Frequency A + * PSU_DDR_PHY_ZQCR_PGWAIT_FRQA 0x15 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ZQCR_RESERVED_31_26 0x0 + * ZQ VREF Pad Enable + * PSU_DDR_PHY_ZQCR_ZQREFPEN 0x0 - ZQ VREF Range - PSU_DDR_PHY_ZQCR_ZQREFISELRANGE 0x0 + * ZQ Internal VREF Enable + * PSU_DDR_PHY_ZQCR_ZQREFIEN 0x1 - Programmable Wait for Frequency B - PSU_DDR_PHY_ZQCR_PGWAIT_FRQB 0x11 + * Choice of termination mode + * PSU_DDR_PHY_ZQCR_ODT_MODE 0x1 - Programmable Wait for Frequency A - PSU_DDR_PHY_ZQCR_PGWAIT_FRQA 0x11 + * Force ZCAL VT update + * PSU_DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE 0x0 - ZQ VREF Pad Enable - PSU_DDR_PHY_ZQCR_ZQREFPEN 0x0 + * IO VT Drift Limit + * PSU_DDR_PHY_ZQCR_IODLMT 0x2 - ZQ Internal VREF Enable - PSU_DDR_PHY_ZQCR_ZQREFIEN 0x1 + * Averaging algorithm enable, if set, enables averaging algorithm + * PSU_DDR_PHY_ZQCR_AVGEN 0x1 - Choice of termination mode - PSU_DDR_PHY_ZQCR_ODT_MODE 0x1 + * Maximum number of averaging rounds to be used by averaging algorithm + * PSU_DDR_PHY_ZQCR_AVGMAX 0x2 - Force ZCAL VT update - PSU_DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE 0x0 + * ZQ Calibration Type + * PSU_DDR_PHY_ZQCR_ZCALT 0x0 - IO VT Drift Limit - PSU_DDR_PHY_ZQCR_IODLMT 0x2 + * ZQ Power Down + * PSU_DDR_PHY_ZQCR_ZQPD 0x0 - Averaging algorithm enable, if set, enables averaging algorithm - PSU_DDR_PHY_ZQCR_AVGEN 0x1 + * ZQ Impedance Control Register + * (OFFSET, MASK, VALUE) (0XFD080680, 0xFFFFFFFFU ,0x008AAA58U) + */ + PSU_Mask_Write(DDR_PHY_ZQCR_OFFSET, 0xFFFFFFFFU, 0x008AAA58U); +/*##################################################################### */ - Maximum number of averaging rounds to be used by averaging algorithm - PSU_DDR_PHY_ZQCR_AVGMAX 0x2 + /* + * Register : ZQ0PR0 @ 0XFD080684 - ZQ Calibration Type - PSU_DDR_PHY_ZQCR_ZCALT 0x0 + * Pull-down drive strength ZCTRL over-ride enable + * PSU_DDR_PHY_ZQ0PR0_PD_DRV_ZDEN 0x0 - ZQ Power Down - PSU_DDR_PHY_ZQCR_ZQPD 0x0 + * Pull-up drive strength ZCTRL over-ride enable + * PSU_DDR_PHY_ZQ0PR0_PU_DRV_ZDEN 0x0 - ZQ Impedance Control Register - (OFFSET, MASK, VALUE) (0XFD080680, 0xFFFFFFFFU ,0x008A2A58U) - RegMask = (DDR_PHY_ZQCR_RESERVED_31_26_MASK | DDR_PHY_ZQCR_ZQREFISELRANGE_MASK | DDR_PHY_ZQCR_PGWAIT_FRQB_MASK | DDR_PHY_ZQCR_PGWAIT_FRQA_MASK | DDR_PHY_ZQCR_ZQREFPEN_MASK | DDR_PHY_ZQCR_ZQREFIEN_MASK | DDR_PHY_ZQCR_ODT_MODE_MASK | DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_MASK | DDR_PHY_ZQCR_IODLMT_MASK | DDR_PHY_ZQCR_AVGEN_MASK | DDR_PHY_ZQCR_AVGMAX_MASK | DDR_PHY_ZQCR_ZCALT_MASK | DDR_PHY_ZQCR_ZQPD_MASK | 0 ); + * Pull-down termination ZCTRL over-ride enable + * PSU_DDR_PHY_ZQ0PR0_PD_ODT_ZDEN 0x0 - RegVal = ((0x00000000U << DDR_PHY_ZQCR_RESERVED_31_26_SHIFT - | 0x00000000U << DDR_PHY_ZQCR_ZQREFISELRANGE_SHIFT - | 0x00000011U << DDR_PHY_ZQCR_PGWAIT_FRQB_SHIFT - | 0x00000011U << DDR_PHY_ZQCR_PGWAIT_FRQA_SHIFT - | 0x00000000U << DDR_PHY_ZQCR_ZQREFPEN_SHIFT - | 0x00000001U << DDR_PHY_ZQCR_ZQREFIEN_SHIFT - | 0x00000001U << DDR_PHY_ZQCR_ODT_MODE_SHIFT - | 0x00000000U << DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_SHIFT - | 0x00000002U << DDR_PHY_ZQCR_IODLMT_SHIFT - | 0x00000001U << DDR_PHY_ZQCR_AVGEN_SHIFT - | 0x00000002U << DDR_PHY_ZQCR_AVGMAX_SHIFT - | 0x00000000U << DDR_PHY_ZQCR_ZCALT_SHIFT - | 0x00000000U << DDR_PHY_ZQCR_ZQPD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_ZQCR_OFFSET ,0xFFFFFFFFU ,0x008A2A58U); - /*############################################################################################################################ */ + * Pull-up termination ZCTRL over-ride enable + * PSU_DDR_PHY_ZQ0PR0_PU_ODT_ZDEN 0x0 - /*Register : ZQ0PR0 @ 0XFD080684

+ * Calibration segment bypass + * PSU_DDR_PHY_ZQ0PR0_ZSEGBYP 0x0 - Pull-down drive strength ZCTRL over-ride enable - PSU_DDR_PHY_ZQ0PR0_PD_DRV_ZDEN 0x0 + * VREF latch mode controls the mode in which the ZLE pin of the PVREF cell + * is driven by the PUB + * PSU_DDR_PHY_ZQ0PR0_ZLE_MODE 0x0 - Pull-up drive strength ZCTRL over-ride enable - PSU_DDR_PHY_ZQ0PR0_PU_DRV_ZDEN 0x0 + * Termination adjustment + * PSU_DDR_PHY_ZQ0PR0_ODT_ADJUST 0x0 - Pull-down termination ZCTRL over-ride enable - PSU_DDR_PHY_ZQ0PR0_PD_ODT_ZDEN 0x0 + * Pulldown drive strength adjustment + * PSU_DDR_PHY_ZQ0PR0_PD_DRV_ADJUST 0x0 - Pull-up termination ZCTRL over-ride enable - PSU_DDR_PHY_ZQ0PR0_PU_ODT_ZDEN 0x0 + * Pullup drive strength adjustment + * PSU_DDR_PHY_ZQ0PR0_PU_DRV_ADJUST 0x0 - Calibration segment bypass - PSU_DDR_PHY_ZQ0PR0_ZSEGBYP 0x0 + * DRAM Impedance Divide Ratio + * PSU_DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT 0x7 - VREF latch mode controls the mode in which the ZLE pin of the PVREF cell is driven by the PUB - PSU_DDR_PHY_ZQ0PR0_ZLE_MODE 0x0 + * HOST Impedance Divide Ratio + * PSU_DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT 0x9 - Termination adjustment - PSU_DDR_PHY_ZQ0PR0_ODT_ADJUST 0x0 + * Impedance Divide Ratio (pulldown drive calibration during asymmetric dri + * ve strength calibration) + * PSU_DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD 0xd - Pulldown drive strength adjustment - PSU_DDR_PHY_ZQ0PR0_PD_DRV_ADJUST 0x0 + * Impedance Divide Ratio (pullup drive calibration during asymmetric drive + * strength calibration) + * PSU_DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU 0xd - Pullup drive strength adjustment - PSU_DDR_PHY_ZQ0PR0_PU_DRV_ADJUST 0x0 + * ZQ n Impedance Control Program Register 0 + * (OFFSET, MASK, VALUE) (0XFD080684, 0xFFFFFFFFU ,0x000079DDU) + */ + PSU_Mask_Write(DDR_PHY_ZQ0PR0_OFFSET, 0xFFFFFFFFU, 0x000079DDU); +/*##################################################################### */ - DRAM Impedance Divide Ratio - PSU_DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT 0x7 + /* + * Register : ZQ0OR0 @ 0XFD080694 - HOST Impedance Divide Ratio - PSU_DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT 0x7 + * Reserved. Return zeros on reads. + * PSU_DDR_PHY_ZQ0OR0_RESERVED_31_26 0x0 - Impedance Divide Ratio (pulldown drive calibration during asymmetric drive strength calibration) - PSU_DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD 0xd + * Override value for the pull-up output impedance + * PSU_DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD 0x1e1 - Impedance Divide Ratio (pullup drive calibration during asymmetric drive strength calibration) - PSU_DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU 0xd + * Reserved. Return zeros on reads. + * PSU_DDR_PHY_ZQ0OR0_RESERVED_15_10 0x0 - ZQ n Impedance Control Program Register 0 - (OFFSET, MASK, VALUE) (0XFD080684, 0xFFFFFFFFU ,0x000077DDU) - RegMask = (DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_MASK | DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_MASK | DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_MASK | DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_MASK | DDR_PHY_ZQ0PR0_ZSEGBYP_MASK | DDR_PHY_ZQ0PR0_ZLE_MODE_MASK | DDR_PHY_ZQ0PR0_ODT_ADJUST_MASK | DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_MASK | DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_MASK | DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_MASK | DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_MASK | DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_MASK | DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_MASK | 0 ); + * Override value for the pull-down output impedance + * PSU_DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD 0x210 - RegVal = ((0x00000000U << DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_SHIFT - | 0x00000000U << DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_SHIFT - | 0x00000000U << DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_SHIFT - | 0x00000000U << DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_SHIFT - | 0x00000000U << DDR_PHY_ZQ0PR0_ZSEGBYP_SHIFT - | 0x00000000U << DDR_PHY_ZQ0PR0_ZLE_MODE_SHIFT - | 0x00000000U << DDR_PHY_ZQ0PR0_ODT_ADJUST_SHIFT - | 0x00000000U << DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_SHIFT - | 0x00000000U << DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_SHIFT - | 0x00000007U << DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_SHIFT - | 0x00000007U << DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_SHIFT - | 0x0000000DU << DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_SHIFT - | 0x0000000DU << DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_ZQ0PR0_OFFSET ,0xFFFFFFFFU ,0x000077DDU); - /*############################################################################################################################ */ + * ZQ n Impedance Control Override Data Register 0 + * (OFFSET, MASK, VALUE) (0XFD080694, 0xFFFFFFFFU ,0x01E10210U) + */ + PSU_Mask_Write(DDR_PHY_ZQ0OR0_OFFSET, 0xFFFFFFFFU, 0x01E10210U); +/*##################################################################### */ - /*Register : ZQ0OR0 @ 0XFD080694

+ /* + * Register : ZQ0OR1 @ 0XFD080698 - Reserved. Return zeros on reads. - PSU_DDR_PHY_ZQ0OR0_RESERVED_31_26 0x0 + * Reserved. Return zeros on reads. + * PSU_DDR_PHY_ZQ0OR1_RESERVED_31_26 0x0 - Override value for the pull-up output impedance - PSU_DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD 0x1e1 + * Override value for the pull-up termination + * PSU_DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD 0x1e1 - Reserved. Return zeros on reads. - PSU_DDR_PHY_ZQ0OR0_RESERVED_15_10 0x0 + * Reserved. Return zeros on reads. + * PSU_DDR_PHY_ZQ0OR1_RESERVED_15_10 0x0 - Override value for the pull-down output impedance - PSU_DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD 0x210 + * Override value for the pull-down termination + * PSU_DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD 0x0 - ZQ n Impedance Control Override Data Register 0 - (OFFSET, MASK, VALUE) (0XFD080694, 0xFFFFFFFFU ,0x01E10210U) - RegMask = (DDR_PHY_ZQ0OR0_RESERVED_31_26_MASK | DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_MASK | DDR_PHY_ZQ0OR0_RESERVED_15_10_MASK | DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_MASK | 0 ); - - RegVal = ((0x00000000U << DDR_PHY_ZQ0OR0_RESERVED_31_26_SHIFT - | 0x000001E1U << DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_SHIFT - | 0x00000000U << DDR_PHY_ZQ0OR0_RESERVED_15_10_SHIFT - | 0x00000210U << DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_ZQ0OR0_OFFSET ,0xFFFFFFFFU ,0x01E10210U); - /*############################################################################################################################ */ + * ZQ n Impedance Control Override Data Register 1 + * (OFFSET, MASK, VALUE) (0XFD080698, 0xFFFFFFFFU ,0x01E10000U) + */ + PSU_Mask_Write(DDR_PHY_ZQ0OR1_OFFSET, 0xFFFFFFFFU, 0x01E10000U); +/*##################################################################### */ - /*Register : ZQ0OR1 @ 0XFD080698

+ /* + * Register : ZQ1PR0 @ 0XFD0806A4 - Reserved. Return zeros on reads. - PSU_DDR_PHY_ZQ0OR1_RESERVED_31_26 0x0 + * Pull-down drive strength ZCTRL over-ride enable + * PSU_DDR_PHY_ZQ1PR0_PD_DRV_ZDEN 0x0 - Override value for the pull-up termination - PSU_DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD 0x1e1 + * Pull-up drive strength ZCTRL over-ride enable + * PSU_DDR_PHY_ZQ1PR0_PU_DRV_ZDEN 0x0 - Reserved. Return zeros on reads. - PSU_DDR_PHY_ZQ0OR1_RESERVED_15_10 0x0 + * Pull-down termination ZCTRL over-ride enable + * PSU_DDR_PHY_ZQ1PR0_PD_ODT_ZDEN 0x0 - Override value for the pull-down termination - PSU_DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD 0x0 + * Pull-up termination ZCTRL over-ride enable + * PSU_DDR_PHY_ZQ1PR0_PU_ODT_ZDEN 0x0 - ZQ n Impedance Control Override Data Register 1 - (OFFSET, MASK, VALUE) (0XFD080698, 0xFFFFFFFFU ,0x01E10000U) - RegMask = (DDR_PHY_ZQ0OR1_RESERVED_31_26_MASK | DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_MASK | DDR_PHY_ZQ0OR1_RESERVED_15_10_MASK | DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_MASK | 0 ); + * Calibration segment bypass + * PSU_DDR_PHY_ZQ1PR0_ZSEGBYP 0x0 - RegVal = ((0x00000000U << DDR_PHY_ZQ0OR1_RESERVED_31_26_SHIFT - | 0x000001E1U << DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_SHIFT - | 0x00000000U << DDR_PHY_ZQ0OR1_RESERVED_15_10_SHIFT - | 0x00000000U << DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_ZQ0OR1_OFFSET ,0xFFFFFFFFU ,0x01E10000U); - /*############################################################################################################################ */ + * VREF latch mode controls the mode in which the ZLE pin of the PVREF cell + * is driven by the PUB + * PSU_DDR_PHY_ZQ1PR0_ZLE_MODE 0x0 - /*Register : ZQ1PR0 @ 0XFD0806A4

+ * Termination adjustment + * PSU_DDR_PHY_ZQ1PR0_ODT_ADJUST 0x0 - Pull-down drive strength ZCTRL over-ride enable - PSU_DDR_PHY_ZQ1PR0_PD_DRV_ZDEN 0x0 + * Pulldown drive strength adjustment + * PSU_DDR_PHY_ZQ1PR0_PD_DRV_ADJUST 0x1 - Pull-up drive strength ZCTRL over-ride enable - PSU_DDR_PHY_ZQ1PR0_PU_DRV_ZDEN 0x0 + * Pullup drive strength adjustment + * PSU_DDR_PHY_ZQ1PR0_PU_DRV_ADJUST 0x0 - Pull-down termination ZCTRL over-ride enable - PSU_DDR_PHY_ZQ1PR0_PD_ODT_ZDEN 0x0 + * DRAM Impedance Divide Ratio + * PSU_DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT 0x7 - Pull-up termination ZCTRL over-ride enable - PSU_DDR_PHY_ZQ1PR0_PU_ODT_ZDEN 0x0 + * HOST Impedance Divide Ratio + * PSU_DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT 0xb - Calibration segment bypass - PSU_DDR_PHY_ZQ1PR0_ZSEGBYP 0x0 + * Impedance Divide Ratio (pulldown drive calibration during asymmetric dri + * ve strength calibration) + * PSU_DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD 0xd - VREF latch mode controls the mode in which the ZLE pin of the PVREF cell is driven by the PUB - PSU_DDR_PHY_ZQ1PR0_ZLE_MODE 0x0 + * Impedance Divide Ratio (pullup drive calibration during asymmetric drive + * strength calibration) + * PSU_DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU 0xb - Termination adjustment - PSU_DDR_PHY_ZQ1PR0_ODT_ADJUST 0x0 + * ZQ n Impedance Control Program Register 0 + * (OFFSET, MASK, VALUE) (0XFD0806A4, 0xFFFFFFFFU ,0x00087BDBU) + */ + PSU_Mask_Write(DDR_PHY_ZQ1PR0_OFFSET, 0xFFFFFFFFU, 0x00087BDBU); +/*##################################################################### */ - Pulldown drive strength adjustment - PSU_DDR_PHY_ZQ1PR0_PD_DRV_ADJUST 0x1 + /* + * Register : DX0GCR0 @ 0XFD080700 - Pullup drive strength adjustment - PSU_DDR_PHY_ZQ1PR0_PU_DRV_ADJUST 0x0 + * Calibration Bypass + * PSU_DDR_PHY_DX0GCR0_CALBYP 0x0 - DRAM Impedance Divide Ratio - PSU_DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT 0x7 + * Master Delay Line Enable + * PSU_DDR_PHY_DX0GCR0_MDLEN 0x1 - HOST Impedance Divide Ratio - PSU_DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT 0xb + * Configurable ODT(TE) Phase Shift + * PSU_DDR_PHY_DX0GCR0_CODTSHFT 0x0 - Impedance Divide Ratio (pulldown drive calibration during asymmetric drive strength calibration) - PSU_DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD 0xd + * DQS Duty Cycle Correction + * PSU_DDR_PHY_DX0GCR0_DQSDCC 0x0 - Impedance Divide Ratio (pullup drive calibration during asymmetric drive strength calibration) - PSU_DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU 0xb + * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY + * PSU_DDR_PHY_DX0GCR0_RDDLY 0x8 - ZQ n Impedance Control Program Register 0 - (OFFSET, MASK, VALUE) (0XFD0806A4, 0xFFFFFFFFU ,0x00087BDBU) - RegMask = (DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_MASK | DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_MASK | DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_MASK | DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_MASK | DDR_PHY_ZQ1PR0_ZSEGBYP_MASK | DDR_PHY_ZQ1PR0_ZLE_MODE_MASK | DDR_PHY_ZQ1PR0_ODT_ADJUST_MASK | DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_MASK | DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_MASK | DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_MASK | DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_MASK | DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_MASK | DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_MASK | 0 ); + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX0GCR0_RESERVED_19_14 0x0 - RegVal = ((0x00000000U << DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_SHIFT - | 0x00000000U << DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_SHIFT - | 0x00000000U << DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_SHIFT - | 0x00000000U << DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_SHIFT - | 0x00000000U << DDR_PHY_ZQ1PR0_ZSEGBYP_SHIFT - | 0x00000000U << DDR_PHY_ZQ1PR0_ZLE_MODE_SHIFT - | 0x00000000U << DDR_PHY_ZQ1PR0_ODT_ADJUST_SHIFT - | 0x00000001U << DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_SHIFT - | 0x00000000U << DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_SHIFT - | 0x00000007U << DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_SHIFT - | 0x0000000BU << DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_SHIFT - | 0x0000000DU << DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_SHIFT - | 0x0000000BU << DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_ZQ1PR0_OFFSET ,0xFFFFFFFFU ,0x00087BDBU); - /*############################################################################################################################ */ + * DQSNSE Power Down Receiver + * PSU_DDR_PHY_DX0GCR0_DQSNSEPDR 0x0 - /*Register : DX0GCR0 @ 0XFD080700

+ * DQSSE Power Down Receiver + * PSU_DDR_PHY_DX0GCR0_DQSSEPDR 0x0 - Calibration Bypass - PSU_DDR_PHY_DX0GCR0_CALBYP 0x0 + * RTT On Additive Latency + * PSU_DDR_PHY_DX0GCR0_RTTOAL 0x0 - Master Delay Line Enable - PSU_DDR_PHY_DX0GCR0_MDLEN 0x1 + * RTT Output Hold + * PSU_DDR_PHY_DX0GCR0_RTTOH 0x3 - Configurable ODT(TE) Phase Shift - PSU_DDR_PHY_DX0GCR0_CODTSHFT 0x0 + * Configurable PDR Phase Shift + * PSU_DDR_PHY_DX0GCR0_CPDRSHFT 0x0 - DQS Duty Cycle Correction - PSU_DDR_PHY_DX0GCR0_DQSDCC 0x0 + * DQSR Power Down + * PSU_DDR_PHY_DX0GCR0_DQSRPD 0x0 - Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY - PSU_DDR_PHY_DX0GCR0_RDDLY 0x8 + * DQSG Power Down Receiver + * PSU_DDR_PHY_DX0GCR0_DQSGPDR 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX0GCR0_RESERVED_19_14 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX0GCR0_RESERVED_4 0x0 - DQSNSE Power Down Receiver - PSU_DDR_PHY_DX0GCR0_DQSNSEPDR 0x0 + * DQSG On-Die Termination + * PSU_DDR_PHY_DX0GCR0_DQSGODT 0x0 - DQSSE Power Down Receiver - PSU_DDR_PHY_DX0GCR0_DQSSEPDR 0x0 + * DQSG Output Enable + * PSU_DDR_PHY_DX0GCR0_DQSGOE 0x1 - RTT On Additive Latency - PSU_DDR_PHY_DX0GCR0_RTTOAL 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX0GCR0_RESERVED_1_0 0x0 - RTT Output Hold - PSU_DDR_PHY_DX0GCR0_RTTOH 0x3 + * DATX8 n General Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD080700, 0xFFFFFFFFU ,0x40800604U) + */ + PSU_Mask_Write(DDR_PHY_DX0GCR0_OFFSET, 0xFFFFFFFFU, 0x40800604U); +/*##################################################################### */ - Configurable PDR Phase Shift - PSU_DDR_PHY_DX0GCR0_CPDRSHFT 0x0 + /* + * Register : DX0GCR4 @ 0XFD080710 - DQSR Power Down - PSU_DDR_PHY_DX0GCR0_DQSRPD 0x0 + * Byte lane VREF IOM (Used only by D4MU IOs) + * PSU_DDR_PHY_DX0GCR4_RESERVED_31_29 0x0 - DQSG Power Down Receiver - PSU_DDR_PHY_DX0GCR0_DQSGPDR 0x0 + * Byte Lane VREF Pad Enable + * PSU_DDR_PHY_DX0GCR4_DXREFPEN 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX0GCR0_RESERVED_4 0x0 + * Byte Lane Internal VREF Enable + * PSU_DDR_PHY_DX0GCR4_DXREFEEN 0x3 - DQSG On-Die Termination - PSU_DDR_PHY_DX0GCR0_DQSGODT 0x0 + * Byte Lane Single-End VREF Enable + * PSU_DDR_PHY_DX0GCR4_DXREFSEN 0x1 - DQSG Output Enable - PSU_DDR_PHY_DX0GCR0_DQSGOE 0x1 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX0GCR4_RESERVED_24 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX0GCR0_RESERVED_1_0 0x0 + * External VREF generator REFSEL range select + * PSU_DDR_PHY_DX0GCR4_DXREFESELRANGE 0x0 - DATX8 n General Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD080700, 0xFFFFFFFFU ,0x40800604U) - RegMask = (DDR_PHY_DX0GCR0_CALBYP_MASK | DDR_PHY_DX0GCR0_MDLEN_MASK | DDR_PHY_DX0GCR0_CODTSHFT_MASK | DDR_PHY_DX0GCR0_DQSDCC_MASK | DDR_PHY_DX0GCR0_RDDLY_MASK | DDR_PHY_DX0GCR0_RESERVED_19_14_MASK | DDR_PHY_DX0GCR0_DQSNSEPDR_MASK | DDR_PHY_DX0GCR0_DQSSEPDR_MASK | DDR_PHY_DX0GCR0_RTTOAL_MASK | DDR_PHY_DX0GCR0_RTTOH_MASK | DDR_PHY_DX0GCR0_CPDRSHFT_MASK | DDR_PHY_DX0GCR0_DQSRPD_MASK | DDR_PHY_DX0GCR0_DQSGPDR_MASK | DDR_PHY_DX0GCR0_RESERVED_4_MASK | DDR_PHY_DX0GCR0_DQSGODT_MASK | DDR_PHY_DX0GCR0_DQSGOE_MASK | DDR_PHY_DX0GCR0_RESERVED_1_0_MASK | 0 ); + * Byte Lane External VREF Select + * PSU_DDR_PHY_DX0GCR4_DXREFESEL 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX0GCR0_CALBYP_SHIFT - | 0x00000001U << DDR_PHY_DX0GCR0_MDLEN_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR0_CODTSHFT_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR0_DQSDCC_SHIFT - | 0x00000008U << DDR_PHY_DX0GCR0_RDDLY_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR0_RESERVED_19_14_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR0_DQSNSEPDR_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR0_DQSSEPDR_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR0_RTTOAL_SHIFT - | 0x00000003U << DDR_PHY_DX0GCR0_RTTOH_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR0_CPDRSHFT_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR0_DQSRPD_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR0_DQSGPDR_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR0_RESERVED_4_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR0_DQSGODT_SHIFT - | 0x00000001U << DDR_PHY_DX0GCR0_DQSGOE_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR0_RESERVED_1_0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX0GCR0_OFFSET ,0xFFFFFFFFU ,0x40800604U); - /*############################################################################################################################ */ - - /*Register : DX0GCR4 @ 0XFD080710

- - Byte lane VREF IOM (Used only by D4MU IOs) - PSU_DDR_PHY_DX0GCR4_RESERVED_31_29 0x0 + * Single ended VREF generator REFSEL range select + * PSU_DDR_PHY_DX0GCR4_DXREFSSELRANGE 0x1 - Byte Lane VREF Pad Enable - PSU_DDR_PHY_DX0GCR4_DXREFPEN 0x0 + * Byte Lane Single-End VREF Select + * PSU_DDR_PHY_DX0GCR4_DXREFSSEL 0x30 - Byte Lane Internal VREF Enable - PSU_DDR_PHY_DX0GCR4_DXREFEEN 0x3 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX0GCR4_RESERVED_7_6 0x0 - Byte Lane Single-End VREF Enable - PSU_DDR_PHY_DX0GCR4_DXREFSEN 0x1 + * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX0GCR4_DXREFIEN 0xf - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX0GCR4_RESERVED_24 0x0 + * VRMON control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX0GCR4_DXREFIMON 0x0 - External VREF generator REFSEL range select - PSU_DDR_PHY_DX0GCR4_DXREFESELRANGE 0x0 + * DATX8 n General Configuration Register 4 + * (OFFSET, MASK, VALUE) (0XFD080710, 0xFFFFFFFFU ,0x0E00B03CU) + */ + PSU_Mask_Write(DDR_PHY_DX0GCR4_OFFSET, 0xFFFFFFFFU, 0x0E00B03CU); +/*##################################################################### */ - Byte Lane External VREF Select - PSU_DDR_PHY_DX0GCR4_DXREFESEL 0x0 + /* + * Register : DX0GCR5 @ 0XFD080714 - Single ended VREF generator REFSEL range select - PSU_DDR_PHY_DX0GCR4_DXREFSSELRANGE 0x1 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX0GCR5_RESERVED_31 0x0 - Byte Lane Single-End VREF Select - PSU_DDR_PHY_DX0GCR4_DXREFSSEL 0x30 + * Byte Lane internal VREF Select for Rank 3 + * PSU_DDR_PHY_DX0GCR5_DXREFISELR3 0x9 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX0GCR4_RESERVED_7_6 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX0GCR5_RESERVED_23 0x0 - VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. - PSU_DDR_PHY_DX0GCR4_DXREFIEN 0xf + * Byte Lane internal VREF Select for Rank 2 + * PSU_DDR_PHY_DX0GCR5_DXREFISELR2 0x9 - VRMON control for DQ IO (Single Ended) buffers of a byte lane. - PSU_DDR_PHY_DX0GCR4_DXREFIMON 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX0GCR5_RESERVED_15 0x0 - DATX8 n General Configuration Register 4 - (OFFSET, MASK, VALUE) (0XFD080710, 0xFFFFFFFFU ,0x0E00B03CU) - RegMask = (DDR_PHY_DX0GCR4_RESERVED_31_29_MASK | DDR_PHY_DX0GCR4_DXREFPEN_MASK | DDR_PHY_DX0GCR4_DXREFEEN_MASK | DDR_PHY_DX0GCR4_DXREFSEN_MASK | DDR_PHY_DX0GCR4_RESERVED_24_MASK | DDR_PHY_DX0GCR4_DXREFESELRANGE_MASK | DDR_PHY_DX0GCR4_DXREFESEL_MASK | DDR_PHY_DX0GCR4_DXREFSSELRANGE_MASK | DDR_PHY_DX0GCR4_DXREFSSEL_MASK | DDR_PHY_DX0GCR4_RESERVED_7_6_MASK | DDR_PHY_DX0GCR4_DXREFIEN_MASK | DDR_PHY_DX0GCR4_DXREFIMON_MASK | 0 ); + * Byte Lane internal VREF Select for Rank 1 + * PSU_DDR_PHY_DX0GCR5_DXREFISELR1 0x55 - RegVal = ((0x00000000U << DDR_PHY_DX0GCR4_RESERVED_31_29_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR4_DXREFPEN_SHIFT - | 0x00000003U << DDR_PHY_DX0GCR4_DXREFEEN_SHIFT - | 0x00000001U << DDR_PHY_DX0GCR4_DXREFSEN_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR4_RESERVED_24_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR4_DXREFESELRANGE_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR4_DXREFESEL_SHIFT - | 0x00000001U << DDR_PHY_DX0GCR4_DXREFSSELRANGE_SHIFT - | 0x00000030U << DDR_PHY_DX0GCR4_DXREFSSEL_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR4_RESERVED_7_6_SHIFT - | 0x0000000FU << DDR_PHY_DX0GCR4_DXREFIEN_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR4_DXREFIMON_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX0GCR4_OFFSET ,0xFFFFFFFFU ,0x0E00B03CU); - /*############################################################################################################################ */ + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX0GCR5_RESERVED_7 0x0 - /*Register : DX0GCR5 @ 0XFD080714

+ * Byte Lane internal VREF Select for Rank 0 + * PSU_DDR_PHY_DX0GCR5_DXREFISELR0 0x55 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX0GCR5_RESERVED_31 0x0 + * DATX8 n General Configuration Register 5 + * (OFFSET, MASK, VALUE) (0XFD080714, 0xFFFFFFFFU ,0x09095555U) + */ + PSU_Mask_Write(DDR_PHY_DX0GCR5_OFFSET, 0xFFFFFFFFU, 0x09095555U); +/*##################################################################### */ - Byte Lane internal VREF Select for Rank 3 - PSU_DDR_PHY_DX0GCR5_DXREFISELR3 0x9 - - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX0GCR5_RESERVED_23 0x0 - - Byte Lane internal VREF Select for Rank 2 - PSU_DDR_PHY_DX0GCR5_DXREFISELR2 0x9 - - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX0GCR5_RESERVED_15 0x0 - - Byte Lane internal VREF Select for Rank 1 - PSU_DDR_PHY_DX0GCR5_DXREFISELR1 0x4f - - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX0GCR5_RESERVED_7 0x0 - - Byte Lane internal VREF Select for Rank 0 - PSU_DDR_PHY_DX0GCR5_DXREFISELR0 0x4f + /* + * Register : DX0GCR6 @ 0XFD080718 - DATX8 n General Configuration Register 5 - (OFFSET, MASK, VALUE) (0XFD080714, 0xFFFFFFFFU ,0x09094F4FU) - RegMask = (DDR_PHY_DX0GCR5_RESERVED_31_MASK | DDR_PHY_DX0GCR5_DXREFISELR3_MASK | DDR_PHY_DX0GCR5_RESERVED_23_MASK | DDR_PHY_DX0GCR5_DXREFISELR2_MASK | DDR_PHY_DX0GCR5_RESERVED_15_MASK | DDR_PHY_DX0GCR5_DXREFISELR1_MASK | DDR_PHY_DX0GCR5_RESERVED_7_MASK | DDR_PHY_DX0GCR5_DXREFISELR0_MASK | 0 ); + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX0GCR6_RESERVED_31_30 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX0GCR5_RESERVED_31_SHIFT - | 0x00000009U << DDR_PHY_DX0GCR5_DXREFISELR3_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR5_RESERVED_23_SHIFT - | 0x00000009U << DDR_PHY_DX0GCR5_DXREFISELR2_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR5_RESERVED_15_SHIFT - | 0x0000004FU << DDR_PHY_DX0GCR5_DXREFISELR1_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR5_RESERVED_7_SHIFT - | 0x0000004FU << DDR_PHY_DX0GCR5_DXREFISELR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX0GCR5_OFFSET ,0xFFFFFFFFU ,0x09094F4FU); - /*############################################################################################################################ */ + * DRAM DQ VREF Select for Rank3 + * PSU_DDR_PHY_DX0GCR6_DXDQVREFR3 0x9 - /*Register : DX0GCR6 @ 0XFD080718

+ * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX0GCR6_RESERVED_23_22 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX0GCR6_RESERVED_31_30 0x0 + * DRAM DQ VREF Select for Rank2 + * PSU_DDR_PHY_DX0GCR6_DXDQVREFR2 0x9 - DRAM DQ VREF Select for Rank3 - PSU_DDR_PHY_DX0GCR6_DXDQVREFR3 0x9 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX0GCR6_RESERVED_15_14 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX0GCR6_RESERVED_23_22 0x0 + * DRAM DQ VREF Select for Rank1 + * PSU_DDR_PHY_DX0GCR6_DXDQVREFR1 0x2b - DRAM DQ VREF Select for Rank2 - PSU_DDR_PHY_DX0GCR6_DXDQVREFR2 0x9 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX0GCR6_RESERVED_7_6 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX0GCR6_RESERVED_15_14 0x0 + * DRAM DQ VREF Select for Rank0 + * PSU_DDR_PHY_DX0GCR6_DXDQVREFR0 0x2b - DRAM DQ VREF Select for Rank1 - PSU_DDR_PHY_DX0GCR6_DXDQVREFR1 0x2b + * DATX8 n General Configuration Register 6 + * (OFFSET, MASK, VALUE) (0XFD080718, 0xFFFFFFFFU ,0x09092B2BU) + */ + PSU_Mask_Write(DDR_PHY_DX0GCR6_OFFSET, 0xFFFFFFFFU, 0x09092B2BU); +/*##################################################################### */ - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX0GCR6_RESERVED_7_6 0x0 + /* + * Register : DX1GCR0 @ 0XFD080800 - DRAM DQ VREF Select for Rank0 - PSU_DDR_PHY_DX0GCR6_DXDQVREFR0 0x2b + * Calibration Bypass + * PSU_DDR_PHY_DX1GCR0_CALBYP 0x0 - DATX8 n General Configuration Register 6 - (OFFSET, MASK, VALUE) (0XFD080718, 0xFFFFFFFFU ,0x09092B2BU) - RegMask = (DDR_PHY_DX0GCR6_RESERVED_31_30_MASK | DDR_PHY_DX0GCR6_DXDQVREFR3_MASK | DDR_PHY_DX0GCR6_RESERVED_23_22_MASK | DDR_PHY_DX0GCR6_DXDQVREFR2_MASK | DDR_PHY_DX0GCR6_RESERVED_15_14_MASK | DDR_PHY_DX0GCR6_DXDQVREFR1_MASK | DDR_PHY_DX0GCR6_RESERVED_7_6_MASK | DDR_PHY_DX0GCR6_DXDQVREFR0_MASK | 0 ); + * Master Delay Line Enable + * PSU_DDR_PHY_DX1GCR0_MDLEN 0x1 - RegVal = ((0x00000000U << DDR_PHY_DX0GCR6_RESERVED_31_30_SHIFT - | 0x00000009U << DDR_PHY_DX0GCR6_DXDQVREFR3_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR6_RESERVED_23_22_SHIFT - | 0x00000009U << DDR_PHY_DX0GCR6_DXDQVREFR2_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR6_RESERVED_15_14_SHIFT - | 0x0000002BU << DDR_PHY_DX0GCR6_DXDQVREFR1_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR6_RESERVED_7_6_SHIFT - | 0x0000002BU << DDR_PHY_DX0GCR6_DXDQVREFR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX0GCR6_OFFSET ,0xFFFFFFFFU ,0x09092B2BU); - /*############################################################################################################################ */ + * Configurable ODT(TE) Phase Shift + * PSU_DDR_PHY_DX1GCR0_CODTSHFT 0x0 - /*Register : DX0LCDLR2 @ 0XFD080788

+ * DQS Duty Cycle Correction + * PSU_DDR_PHY_DX1GCR0_DQSDCC 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX0LCDLR2_RESERVED_31_25 0x0 + * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY + * PSU_DDR_PHY_DX1GCR0_RDDLY 0x8 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX0LCDLR2_RESERVED_24_16 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX1GCR0_RESERVED_19_14 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX0LCDLR2_RESERVED_15_9 0x0 + * DQSNSE Power Down Receiver + * PSU_DDR_PHY_DX1GCR0_DQSNSEPDR 0x0 - Read DQS Gating Delay - PSU_DDR_PHY_DX0LCDLR2_DQSGD 0x0 + * DQSSE Power Down Receiver + * PSU_DDR_PHY_DX1GCR0_DQSSEPDR 0x0 - DATX8 n Local Calibrated Delay Line Register 2 - (OFFSET, MASK, VALUE) (0XFD080788, 0xFFFFFFFFU ,0x00000000U) - RegMask = (DDR_PHY_DX0LCDLR2_RESERVED_31_25_MASK | DDR_PHY_DX0LCDLR2_RESERVED_24_16_MASK | DDR_PHY_DX0LCDLR2_RESERVED_15_9_MASK | DDR_PHY_DX0LCDLR2_DQSGD_MASK | 0 ); + * RTT On Additive Latency + * PSU_DDR_PHY_DX1GCR0_RTTOAL 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX0LCDLR2_RESERVED_31_25_SHIFT - | 0x00000000U << DDR_PHY_DX0LCDLR2_RESERVED_24_16_SHIFT - | 0x00000000U << DDR_PHY_DX0LCDLR2_RESERVED_15_9_SHIFT - | 0x00000000U << DDR_PHY_DX0LCDLR2_DQSGD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX0LCDLR2_OFFSET ,0xFFFFFFFFU ,0x00000000U); - /*############################################################################################################################ */ + * RTT Output Hold + * PSU_DDR_PHY_DX1GCR0_RTTOH 0x3 - /*Register : DX0GTR0 @ 0XFD0807C0

+ * Configurable PDR Phase Shift + * PSU_DDR_PHY_DX1GCR0_CPDRSHFT 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX0GTR0_RESERVED_31_24 0x0 + * DQSR Power Down + * PSU_DDR_PHY_DX1GCR0_DQSRPD 0x0 - DQ Write Path Latency Pipeline - PSU_DDR_PHY_DX0GTR0_WDQSL 0x0 + * DQSG Power Down Receiver + * PSU_DDR_PHY_DX1GCR0_DQSGPDR 0x0 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX0GTR0_RESERVED_23_20 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX1GCR0_RESERVED_4 0x0 - Write Leveling System Latency - PSU_DDR_PHY_DX0GTR0_WLSL 0x2 + * DQSG On-Die Termination + * PSU_DDR_PHY_DX1GCR0_DQSGODT 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX0GTR0_RESERVED_15_13 0x0 + * DQSG Output Enable + * PSU_DDR_PHY_DX1GCR0_DQSGOE 0x1 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX0GTR0_RESERVED_12_8 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX1GCR0_RESERVED_1_0 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX0GTR0_RESERVED_7_5 0x0 + * DATX8 n General Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD080800, 0xFFFFFFFFU ,0x40800604U) + */ + PSU_Mask_Write(DDR_PHY_DX1GCR0_OFFSET, 0xFFFFFFFFU, 0x40800604U); +/*##################################################################### */ - DQS Gating System Latency - PSU_DDR_PHY_DX0GTR0_DGSL 0x0 + /* + * Register : DX1GCR4 @ 0XFD080810 - DATX8 n General Timing Register 0 - (OFFSET, MASK, VALUE) (0XFD0807C0, 0xFFFFFFFFU ,0x00020000U) - RegMask = (DDR_PHY_DX0GTR0_RESERVED_31_24_MASK | DDR_PHY_DX0GTR0_WDQSL_MASK | DDR_PHY_DX0GTR0_RESERVED_23_20_MASK | DDR_PHY_DX0GTR0_WLSL_MASK | DDR_PHY_DX0GTR0_RESERVED_15_13_MASK | DDR_PHY_DX0GTR0_RESERVED_12_8_MASK | DDR_PHY_DX0GTR0_RESERVED_7_5_MASK | DDR_PHY_DX0GTR0_DGSL_MASK | 0 ); + * Byte lane VREF IOM (Used only by D4MU IOs) + * PSU_DDR_PHY_DX1GCR4_RESERVED_31_29 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX0GTR0_RESERVED_31_24_SHIFT - | 0x00000000U << DDR_PHY_DX0GTR0_WDQSL_SHIFT - | 0x00000000U << DDR_PHY_DX0GTR0_RESERVED_23_20_SHIFT - | 0x00000002U << DDR_PHY_DX0GTR0_WLSL_SHIFT - | 0x00000000U << DDR_PHY_DX0GTR0_RESERVED_15_13_SHIFT - | 0x00000000U << DDR_PHY_DX0GTR0_RESERVED_12_8_SHIFT - | 0x00000000U << DDR_PHY_DX0GTR0_RESERVED_7_5_SHIFT - | 0x00000000U << DDR_PHY_DX0GTR0_DGSL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX0GTR0_OFFSET ,0xFFFFFFFFU ,0x00020000U); - /*############################################################################################################################ */ + * Byte Lane VREF Pad Enable + * PSU_DDR_PHY_DX1GCR4_DXREFPEN 0x0 - /*Register : DX1GCR0 @ 0XFD080800

+ * Byte Lane Internal VREF Enable + * PSU_DDR_PHY_DX1GCR4_DXREFEEN 0x3 - Calibration Bypass - PSU_DDR_PHY_DX1GCR0_CALBYP 0x0 + * Byte Lane Single-End VREF Enable + * PSU_DDR_PHY_DX1GCR4_DXREFSEN 0x1 - Master Delay Line Enable - PSU_DDR_PHY_DX1GCR0_MDLEN 0x1 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX1GCR4_RESERVED_24 0x0 - Configurable ODT(TE) Phase Shift - PSU_DDR_PHY_DX1GCR0_CODTSHFT 0x0 + * External VREF generator REFSEL range select + * PSU_DDR_PHY_DX1GCR4_DXREFESELRANGE 0x0 - DQS Duty Cycle Correction - PSU_DDR_PHY_DX1GCR0_DQSDCC 0x0 + * Byte Lane External VREF Select + * PSU_DDR_PHY_DX1GCR4_DXREFESEL 0x0 - Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY - PSU_DDR_PHY_DX1GCR0_RDDLY 0x8 + * Single ended VREF generator REFSEL range select + * PSU_DDR_PHY_DX1GCR4_DXREFSSELRANGE 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX1GCR0_RESERVED_19_14 0x0 + * Byte Lane Single-End VREF Select + * PSU_DDR_PHY_DX1GCR4_DXREFSSEL 0x30 - DQSNSE Power Down Receiver - PSU_DDR_PHY_DX1GCR0_DQSNSEPDR 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX1GCR4_RESERVED_7_6 0x0 - DQSSE Power Down Receiver - PSU_DDR_PHY_DX1GCR0_DQSSEPDR 0x0 + * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX1GCR4_DXREFIEN 0xf - RTT On Additive Latency - PSU_DDR_PHY_DX1GCR0_RTTOAL 0x0 + * VRMON control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX1GCR4_DXREFIMON 0x0 - RTT Output Hold - PSU_DDR_PHY_DX1GCR0_RTTOH 0x3 + * DATX8 n General Configuration Register 4 + * (OFFSET, MASK, VALUE) (0XFD080810, 0xFFFFFFFFU ,0x0E00B03CU) + */ + PSU_Mask_Write(DDR_PHY_DX1GCR4_OFFSET, 0xFFFFFFFFU, 0x0E00B03CU); +/*##################################################################### */ - Configurable PDR Phase Shift - PSU_DDR_PHY_DX1GCR0_CPDRSHFT 0x0 + /* + * Register : DX1GCR5 @ 0XFD080814 - DQSR Power Down - PSU_DDR_PHY_DX1GCR0_DQSRPD 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX1GCR5_RESERVED_31 0x0 - DQSG Power Down Receiver - PSU_DDR_PHY_DX1GCR0_DQSGPDR 0x0 + * Byte Lane internal VREF Select for Rank 3 + * PSU_DDR_PHY_DX1GCR5_DXREFISELR3 0x9 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX1GCR0_RESERVED_4 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX1GCR5_RESERVED_23 0x0 - DQSG On-Die Termination - PSU_DDR_PHY_DX1GCR0_DQSGODT 0x0 + * Byte Lane internal VREF Select for Rank 2 + * PSU_DDR_PHY_DX1GCR5_DXREFISELR2 0x9 - DQSG Output Enable - PSU_DDR_PHY_DX1GCR0_DQSGOE 0x1 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX1GCR5_RESERVED_15 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX1GCR0_RESERVED_1_0 0x0 + * Byte Lane internal VREF Select for Rank 1 + * PSU_DDR_PHY_DX1GCR5_DXREFISELR1 0x55 - DATX8 n General Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD080800, 0xFFFFFFFFU ,0x40800604U) - RegMask = (DDR_PHY_DX1GCR0_CALBYP_MASK | DDR_PHY_DX1GCR0_MDLEN_MASK | DDR_PHY_DX1GCR0_CODTSHFT_MASK | DDR_PHY_DX1GCR0_DQSDCC_MASK | DDR_PHY_DX1GCR0_RDDLY_MASK | DDR_PHY_DX1GCR0_RESERVED_19_14_MASK | DDR_PHY_DX1GCR0_DQSNSEPDR_MASK | DDR_PHY_DX1GCR0_DQSSEPDR_MASK | DDR_PHY_DX1GCR0_RTTOAL_MASK | DDR_PHY_DX1GCR0_RTTOH_MASK | DDR_PHY_DX1GCR0_CPDRSHFT_MASK | DDR_PHY_DX1GCR0_DQSRPD_MASK | DDR_PHY_DX1GCR0_DQSGPDR_MASK | DDR_PHY_DX1GCR0_RESERVED_4_MASK | DDR_PHY_DX1GCR0_DQSGODT_MASK | DDR_PHY_DX1GCR0_DQSGOE_MASK | DDR_PHY_DX1GCR0_RESERVED_1_0_MASK | 0 ); + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX1GCR5_RESERVED_7 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX1GCR0_CALBYP_SHIFT - | 0x00000001U << DDR_PHY_DX1GCR0_MDLEN_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR0_CODTSHFT_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR0_DQSDCC_SHIFT - | 0x00000008U << DDR_PHY_DX1GCR0_RDDLY_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR0_RESERVED_19_14_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR0_DQSNSEPDR_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR0_DQSSEPDR_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR0_RTTOAL_SHIFT - | 0x00000003U << DDR_PHY_DX1GCR0_RTTOH_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR0_CPDRSHFT_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR0_DQSRPD_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR0_DQSGPDR_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR0_RESERVED_4_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR0_DQSGODT_SHIFT - | 0x00000001U << DDR_PHY_DX1GCR0_DQSGOE_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR0_RESERVED_1_0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX1GCR0_OFFSET ,0xFFFFFFFFU ,0x40800604U); - /*############################################################################################################################ */ + * Byte Lane internal VREF Select for Rank 0 + * PSU_DDR_PHY_DX1GCR5_DXREFISELR0 0x55 - /*Register : DX1GCR4 @ 0XFD080810

+ * DATX8 n General Configuration Register 5 + * (OFFSET, MASK, VALUE) (0XFD080814, 0xFFFFFFFFU ,0x09095555U) + */ + PSU_Mask_Write(DDR_PHY_DX1GCR5_OFFSET, 0xFFFFFFFFU, 0x09095555U); +/*##################################################################### */ - Byte lane VREF IOM (Used only by D4MU IOs) - PSU_DDR_PHY_DX1GCR4_RESERVED_31_29 0x0 + /* + * Register : DX1GCR6 @ 0XFD080818 - Byte Lane VREF Pad Enable - PSU_DDR_PHY_DX1GCR4_DXREFPEN 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX1GCR6_RESERVED_31_30 0x0 - Byte Lane Internal VREF Enable - PSU_DDR_PHY_DX1GCR4_DXREFEEN 0x3 + * DRAM DQ VREF Select for Rank3 + * PSU_DDR_PHY_DX1GCR6_DXDQVREFR3 0x9 - Byte Lane Single-End VREF Enable - PSU_DDR_PHY_DX1GCR4_DXREFSEN 0x1 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX1GCR6_RESERVED_23_22 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX1GCR4_RESERVED_24 0x0 + * DRAM DQ VREF Select for Rank2 + * PSU_DDR_PHY_DX1GCR6_DXDQVREFR2 0x9 - External VREF generator REFSEL range select - PSU_DDR_PHY_DX1GCR4_DXREFESELRANGE 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX1GCR6_RESERVED_15_14 0x0 - Byte Lane External VREF Select - PSU_DDR_PHY_DX1GCR4_DXREFESEL 0x0 + * DRAM DQ VREF Select for Rank1 + * PSU_DDR_PHY_DX1GCR6_DXDQVREFR1 0x2b - Single ended VREF generator REFSEL range select - PSU_DDR_PHY_DX1GCR4_DXREFSSELRANGE 0x1 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX1GCR6_RESERVED_7_6 0x0 - Byte Lane Single-End VREF Select - PSU_DDR_PHY_DX1GCR4_DXREFSSEL 0x30 + * DRAM DQ VREF Select for Rank0 + * PSU_DDR_PHY_DX1GCR6_DXDQVREFR0 0x2b - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX1GCR4_RESERVED_7_6 0x0 + * DATX8 n General Configuration Register 6 + * (OFFSET, MASK, VALUE) (0XFD080818, 0xFFFFFFFFU ,0x09092B2BU) + */ + PSU_Mask_Write(DDR_PHY_DX1GCR6_OFFSET, 0xFFFFFFFFU, 0x09092B2BU); +/*##################################################################### */ - VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. - PSU_DDR_PHY_DX1GCR4_DXREFIEN 0xf + /* + * Register : DX2GCR0 @ 0XFD080900 - VRMON control for DQ IO (Single Ended) buffers of a byte lane. - PSU_DDR_PHY_DX1GCR4_DXREFIMON 0x0 + * Calibration Bypass + * PSU_DDR_PHY_DX2GCR0_CALBYP 0x0 - DATX8 n General Configuration Register 4 - (OFFSET, MASK, VALUE) (0XFD080810, 0xFFFFFFFFU ,0x0E00B03CU) - RegMask = (DDR_PHY_DX1GCR4_RESERVED_31_29_MASK | DDR_PHY_DX1GCR4_DXREFPEN_MASK | DDR_PHY_DX1GCR4_DXREFEEN_MASK | DDR_PHY_DX1GCR4_DXREFSEN_MASK | DDR_PHY_DX1GCR4_RESERVED_24_MASK | DDR_PHY_DX1GCR4_DXREFESELRANGE_MASK | DDR_PHY_DX1GCR4_DXREFESEL_MASK | DDR_PHY_DX1GCR4_DXREFSSELRANGE_MASK | DDR_PHY_DX1GCR4_DXREFSSEL_MASK | DDR_PHY_DX1GCR4_RESERVED_7_6_MASK | DDR_PHY_DX1GCR4_DXREFIEN_MASK | DDR_PHY_DX1GCR4_DXREFIMON_MASK | 0 ); + * Master Delay Line Enable + * PSU_DDR_PHY_DX2GCR0_MDLEN 0x1 - RegVal = ((0x00000000U << DDR_PHY_DX1GCR4_RESERVED_31_29_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR4_DXREFPEN_SHIFT - | 0x00000003U << DDR_PHY_DX1GCR4_DXREFEEN_SHIFT - | 0x00000001U << DDR_PHY_DX1GCR4_DXREFSEN_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR4_RESERVED_24_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR4_DXREFESELRANGE_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR4_DXREFESEL_SHIFT - | 0x00000001U << DDR_PHY_DX1GCR4_DXREFSSELRANGE_SHIFT - | 0x00000030U << DDR_PHY_DX1GCR4_DXREFSSEL_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR4_RESERVED_7_6_SHIFT - | 0x0000000FU << DDR_PHY_DX1GCR4_DXREFIEN_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR4_DXREFIMON_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX1GCR4_OFFSET ,0xFFFFFFFFU ,0x0E00B03CU); - /*############################################################################################################################ */ + * Configurable ODT(TE) Phase Shift + * PSU_DDR_PHY_DX2GCR0_CODTSHFT 0x0 - /*Register : DX1GCR5 @ 0XFD080814

+ * DQS Duty Cycle Correction + * PSU_DDR_PHY_DX2GCR0_DQSDCC 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX1GCR5_RESERVED_31 0x0 + * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY + * PSU_DDR_PHY_DX2GCR0_RDDLY 0x8 - Byte Lane internal VREF Select for Rank 3 - PSU_DDR_PHY_DX1GCR5_DXREFISELR3 0x9 - - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX1GCR5_RESERVED_23 0x0 - - Byte Lane internal VREF Select for Rank 2 - PSU_DDR_PHY_DX1GCR5_DXREFISELR2 0x9 - - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX1GCR5_RESERVED_15 0x0 - - Byte Lane internal VREF Select for Rank 1 - PSU_DDR_PHY_DX1GCR5_DXREFISELR1 0x4f - - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX1GCR5_RESERVED_7 0x0 - - Byte Lane internal VREF Select for Rank 0 - PSU_DDR_PHY_DX1GCR5_DXREFISELR0 0x4f + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX2GCR0_RESERVED_19_14 0x0 - DATX8 n General Configuration Register 5 - (OFFSET, MASK, VALUE) (0XFD080814, 0xFFFFFFFFU ,0x09094F4FU) - RegMask = (DDR_PHY_DX1GCR5_RESERVED_31_MASK | DDR_PHY_DX1GCR5_DXREFISELR3_MASK | DDR_PHY_DX1GCR5_RESERVED_23_MASK | DDR_PHY_DX1GCR5_DXREFISELR2_MASK | DDR_PHY_DX1GCR5_RESERVED_15_MASK | DDR_PHY_DX1GCR5_DXREFISELR1_MASK | DDR_PHY_DX1GCR5_RESERVED_7_MASK | DDR_PHY_DX1GCR5_DXREFISELR0_MASK | 0 ); + * DQSNSE Power Down Receiver + * PSU_DDR_PHY_DX2GCR0_DQSNSEPDR 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX1GCR5_RESERVED_31_SHIFT - | 0x00000009U << DDR_PHY_DX1GCR5_DXREFISELR3_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR5_RESERVED_23_SHIFT - | 0x00000009U << DDR_PHY_DX1GCR5_DXREFISELR2_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR5_RESERVED_15_SHIFT - | 0x0000004FU << DDR_PHY_DX1GCR5_DXREFISELR1_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR5_RESERVED_7_SHIFT - | 0x0000004FU << DDR_PHY_DX1GCR5_DXREFISELR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX1GCR5_OFFSET ,0xFFFFFFFFU ,0x09094F4FU); - /*############################################################################################################################ */ + * DQSSE Power Down Receiver + * PSU_DDR_PHY_DX2GCR0_DQSSEPDR 0x0 - /*Register : DX1GCR6 @ 0XFD080818

+ * RTT On Additive Latency + * PSU_DDR_PHY_DX2GCR0_RTTOAL 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX1GCR6_RESERVED_31_30 0x0 + * RTT Output Hold + * PSU_DDR_PHY_DX2GCR0_RTTOH 0x3 - DRAM DQ VREF Select for Rank3 - PSU_DDR_PHY_DX1GCR6_DXDQVREFR3 0x9 + * Configurable PDR Phase Shift + * PSU_DDR_PHY_DX2GCR0_CPDRSHFT 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX1GCR6_RESERVED_23_22 0x0 + * DQSR Power Down + * PSU_DDR_PHY_DX2GCR0_DQSRPD 0x0 - DRAM DQ VREF Select for Rank2 - PSU_DDR_PHY_DX1GCR6_DXDQVREFR2 0x9 + * DQSG Power Down Receiver + * PSU_DDR_PHY_DX2GCR0_DQSGPDR 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX1GCR6_RESERVED_15_14 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX2GCR0_RESERVED_4 0x0 - DRAM DQ VREF Select for Rank1 - PSU_DDR_PHY_DX1GCR6_DXDQVREFR1 0x2b + * DQSG On-Die Termination + * PSU_DDR_PHY_DX2GCR0_DQSGODT 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX1GCR6_RESERVED_7_6 0x0 + * DQSG Output Enable + * PSU_DDR_PHY_DX2GCR0_DQSGOE 0x1 - DRAM DQ VREF Select for Rank0 - PSU_DDR_PHY_DX1GCR6_DXDQVREFR0 0x2b + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX2GCR0_RESERVED_1_0 0x0 - DATX8 n General Configuration Register 6 - (OFFSET, MASK, VALUE) (0XFD080818, 0xFFFFFFFFU ,0x09092B2BU) - RegMask = (DDR_PHY_DX1GCR6_RESERVED_31_30_MASK | DDR_PHY_DX1GCR6_DXDQVREFR3_MASK | DDR_PHY_DX1GCR6_RESERVED_23_22_MASK | DDR_PHY_DX1GCR6_DXDQVREFR2_MASK | DDR_PHY_DX1GCR6_RESERVED_15_14_MASK | DDR_PHY_DX1GCR6_DXDQVREFR1_MASK | DDR_PHY_DX1GCR6_RESERVED_7_6_MASK | DDR_PHY_DX1GCR6_DXDQVREFR0_MASK | 0 ); + * DATX8 n General Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD080900, 0xFFFFFFFFU ,0x40800604U) + */ + PSU_Mask_Write(DDR_PHY_DX2GCR0_OFFSET, 0xFFFFFFFFU, 0x40800604U); +/*##################################################################### */ - RegVal = ((0x00000000U << DDR_PHY_DX1GCR6_RESERVED_31_30_SHIFT - | 0x00000009U << DDR_PHY_DX1GCR6_DXDQVREFR3_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR6_RESERVED_23_22_SHIFT - | 0x00000009U << DDR_PHY_DX1GCR6_DXDQVREFR2_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR6_RESERVED_15_14_SHIFT - | 0x0000002BU << DDR_PHY_DX1GCR6_DXDQVREFR1_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR6_RESERVED_7_6_SHIFT - | 0x0000002BU << DDR_PHY_DX1GCR6_DXDQVREFR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX1GCR6_OFFSET ,0xFFFFFFFFU ,0x09092B2BU); - /*############################################################################################################################ */ + /* + * Register : DX2GCR1 @ 0XFD080904 - /*Register : DX1LCDLR2 @ 0XFD080888

+ * Enables the PDR mode for DQ[7:0] + * PSU_DDR_PHY_DX2GCR1_DXPDRMODE 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX1LCDLR2_RESERVED_31_25 0x0 + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX2GCR1_RESERVED_15 0x0 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX1LCDLR2_RESERVED_24_16 0x0 + * Select the delayed or non-delayed read data strobe # + * PSU_DDR_PHY_DX2GCR1_QSNSEL 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX1LCDLR2_RESERVED_15_9 0x0 + * Select the delayed or non-delayed read data strobe + * PSU_DDR_PHY_DX2GCR1_QSSEL 0x1 - Read DQS Gating Delay - PSU_DDR_PHY_DX1LCDLR2_DQSGD 0x0 + * Enables Read Data Strobe in a byte lane + * PSU_DDR_PHY_DX2GCR1_OEEN 0x1 - DATX8 n Local Calibrated Delay Line Register 2 - (OFFSET, MASK, VALUE) (0XFD080888, 0xFFFFFFFFU ,0x00000000U) - RegMask = (DDR_PHY_DX1LCDLR2_RESERVED_31_25_MASK | DDR_PHY_DX1LCDLR2_RESERVED_24_16_MASK | DDR_PHY_DX1LCDLR2_RESERVED_15_9_MASK | DDR_PHY_DX1LCDLR2_DQSGD_MASK | 0 ); + * Enables PDR in a byte lane + * PSU_DDR_PHY_DX2GCR1_PDREN 0x1 - RegVal = ((0x00000000U << DDR_PHY_DX1LCDLR2_RESERVED_31_25_SHIFT - | 0x00000000U << DDR_PHY_DX1LCDLR2_RESERVED_24_16_SHIFT - | 0x00000000U << DDR_PHY_DX1LCDLR2_RESERVED_15_9_SHIFT - | 0x00000000U << DDR_PHY_DX1LCDLR2_DQSGD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX1LCDLR2_OFFSET ,0xFFFFFFFFU ,0x00000000U); - /*############################################################################################################################ */ + * Enables ODT/TE in a byte lane + * PSU_DDR_PHY_DX2GCR1_TEEN 0x1 - /*Register : DX1GTR0 @ 0XFD0808C0

+ * Enables Write Data strobe in a byte lane + * PSU_DDR_PHY_DX2GCR1_DSEN 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX1GTR0_RESERVED_31_24 0x0 + * Enables DM pin in a byte lane + * PSU_DDR_PHY_DX2GCR1_DMEN 0x1 - DQ Write Path Latency Pipeline - PSU_DDR_PHY_DX1GTR0_WDQSL 0x0 + * Enables DQ corresponding to each bit in a byte + * PSU_DDR_PHY_DX2GCR1_DQEN 0xff - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX1GTR0_RESERVED_23_20 0x0 + * DATX8 n General Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD080904, 0xFFFFFFFFU ,0x00007FFFU) + */ + PSU_Mask_Write(DDR_PHY_DX2GCR1_OFFSET, 0xFFFFFFFFU, 0x00007FFFU); +/*##################################################################### */ - Write Leveling System Latency - PSU_DDR_PHY_DX1GTR0_WLSL 0x2 + /* + * Register : DX2GCR4 @ 0XFD080910 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX1GTR0_RESERVED_15_13 0x0 + * Byte lane VREF IOM (Used only by D4MU IOs) + * PSU_DDR_PHY_DX2GCR4_RESERVED_31_29 0x0 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX1GTR0_RESERVED_12_8 0x0 + * Byte Lane VREF Pad Enable + * PSU_DDR_PHY_DX2GCR4_DXREFPEN 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX1GTR0_RESERVED_7_5 0x0 + * Byte Lane Internal VREF Enable + * PSU_DDR_PHY_DX2GCR4_DXREFEEN 0x3 - DQS Gating System Latency - PSU_DDR_PHY_DX1GTR0_DGSL 0x0 + * Byte Lane Single-End VREF Enable + * PSU_DDR_PHY_DX2GCR4_DXREFSEN 0x1 - DATX8 n General Timing Register 0 - (OFFSET, MASK, VALUE) (0XFD0808C0, 0xFFFFFFFFU ,0x00020000U) - RegMask = (DDR_PHY_DX1GTR0_RESERVED_31_24_MASK | DDR_PHY_DX1GTR0_WDQSL_MASK | DDR_PHY_DX1GTR0_RESERVED_23_20_MASK | DDR_PHY_DX1GTR0_WLSL_MASK | DDR_PHY_DX1GTR0_RESERVED_15_13_MASK | DDR_PHY_DX1GTR0_RESERVED_12_8_MASK | DDR_PHY_DX1GTR0_RESERVED_7_5_MASK | DDR_PHY_DX1GTR0_DGSL_MASK | 0 ); + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX2GCR4_RESERVED_24 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX1GTR0_RESERVED_31_24_SHIFT - | 0x00000000U << DDR_PHY_DX1GTR0_WDQSL_SHIFT - | 0x00000000U << DDR_PHY_DX1GTR0_RESERVED_23_20_SHIFT - | 0x00000002U << DDR_PHY_DX1GTR0_WLSL_SHIFT - | 0x00000000U << DDR_PHY_DX1GTR0_RESERVED_15_13_SHIFT - | 0x00000000U << DDR_PHY_DX1GTR0_RESERVED_12_8_SHIFT - | 0x00000000U << DDR_PHY_DX1GTR0_RESERVED_7_5_SHIFT - | 0x00000000U << DDR_PHY_DX1GTR0_DGSL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX1GTR0_OFFSET ,0xFFFFFFFFU ,0x00020000U); - /*############################################################################################################################ */ + * External VREF generator REFSEL range select + * PSU_DDR_PHY_DX2GCR4_DXREFESELRANGE 0x0 - /*Register : DX2GCR0 @ 0XFD080900

+ * Byte Lane External VREF Select + * PSU_DDR_PHY_DX2GCR4_DXREFESEL 0x0 - Calibration Bypass - PSU_DDR_PHY_DX2GCR0_CALBYP 0x0 + * Single ended VREF generator REFSEL range select + * PSU_DDR_PHY_DX2GCR4_DXREFSSELRANGE 0x1 - Master Delay Line Enable - PSU_DDR_PHY_DX2GCR0_MDLEN 0x1 + * Byte Lane Single-End VREF Select + * PSU_DDR_PHY_DX2GCR4_DXREFSSEL 0x30 - Configurable ODT(TE) Phase Shift - PSU_DDR_PHY_DX2GCR0_CODTSHFT 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX2GCR4_RESERVED_7_6 0x0 - DQS Duty Cycle Correction - PSU_DDR_PHY_DX2GCR0_DQSDCC 0x0 + * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX2GCR4_DXREFIEN 0xf - Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY - PSU_DDR_PHY_DX2GCR0_RDDLY 0x8 + * VRMON control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX2GCR4_DXREFIMON 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX2GCR0_RESERVED_19_14 0x0 + * DATX8 n General Configuration Register 4 + * (OFFSET, MASK, VALUE) (0XFD080910, 0xFFFFFFFFU ,0x0E00B03CU) + */ + PSU_Mask_Write(DDR_PHY_DX2GCR4_OFFSET, 0xFFFFFFFFU, 0x0E00B03CU); +/*##################################################################### */ - DQSNSE Power Down Receiver - PSU_DDR_PHY_DX2GCR0_DQSNSEPDR 0x0 + /* + * Register : DX2GCR5 @ 0XFD080914 - DQSSE Power Down Receiver - PSU_DDR_PHY_DX2GCR0_DQSSEPDR 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX2GCR5_RESERVED_31 0x0 - RTT On Additive Latency - PSU_DDR_PHY_DX2GCR0_RTTOAL 0x0 + * Byte Lane internal VREF Select for Rank 3 + * PSU_DDR_PHY_DX2GCR5_DXREFISELR3 0x9 - RTT Output Hold - PSU_DDR_PHY_DX2GCR0_RTTOH 0x3 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX2GCR5_RESERVED_23 0x0 - Configurable PDR Phase Shift - PSU_DDR_PHY_DX2GCR0_CPDRSHFT 0x0 + * Byte Lane internal VREF Select for Rank 2 + * PSU_DDR_PHY_DX2GCR5_DXREFISELR2 0x9 - DQSR Power Down - PSU_DDR_PHY_DX2GCR0_DQSRPD 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX2GCR5_RESERVED_15 0x0 - DQSG Power Down Receiver - PSU_DDR_PHY_DX2GCR0_DQSGPDR 0x0 + * Byte Lane internal VREF Select for Rank 1 + * PSU_DDR_PHY_DX2GCR5_DXREFISELR1 0x55 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX2GCR0_RESERVED_4 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX2GCR5_RESERVED_7 0x0 - DQSG On-Die Termination - PSU_DDR_PHY_DX2GCR0_DQSGODT 0x0 + * Byte Lane internal VREF Select for Rank 0 + * PSU_DDR_PHY_DX2GCR5_DXREFISELR0 0x55 - DQSG Output Enable - PSU_DDR_PHY_DX2GCR0_DQSGOE 0x1 + * DATX8 n General Configuration Register 5 + * (OFFSET, MASK, VALUE) (0XFD080914, 0xFFFFFFFFU ,0x09095555U) + */ + PSU_Mask_Write(DDR_PHY_DX2GCR5_OFFSET, 0xFFFFFFFFU, 0x09095555U); +/*##################################################################### */ - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX2GCR0_RESERVED_1_0 0x0 + /* + * Register : DX2GCR6 @ 0XFD080918 - DATX8 n General Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD080900, 0xFFFFFFFFU ,0x40800604U) - RegMask = (DDR_PHY_DX2GCR0_CALBYP_MASK | DDR_PHY_DX2GCR0_MDLEN_MASK | DDR_PHY_DX2GCR0_CODTSHFT_MASK | DDR_PHY_DX2GCR0_DQSDCC_MASK | DDR_PHY_DX2GCR0_RDDLY_MASK | DDR_PHY_DX2GCR0_RESERVED_19_14_MASK | DDR_PHY_DX2GCR0_DQSNSEPDR_MASK | DDR_PHY_DX2GCR0_DQSSEPDR_MASK | DDR_PHY_DX2GCR0_RTTOAL_MASK | DDR_PHY_DX2GCR0_RTTOH_MASK | DDR_PHY_DX2GCR0_CPDRSHFT_MASK | DDR_PHY_DX2GCR0_DQSRPD_MASK | DDR_PHY_DX2GCR0_DQSGPDR_MASK | DDR_PHY_DX2GCR0_RESERVED_4_MASK | DDR_PHY_DX2GCR0_DQSGODT_MASK | DDR_PHY_DX2GCR0_DQSGOE_MASK | DDR_PHY_DX2GCR0_RESERVED_1_0_MASK | 0 ); + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX2GCR6_RESERVED_31_30 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX2GCR0_CALBYP_SHIFT - | 0x00000001U << DDR_PHY_DX2GCR0_MDLEN_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR0_CODTSHFT_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR0_DQSDCC_SHIFT - | 0x00000008U << DDR_PHY_DX2GCR0_RDDLY_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR0_RESERVED_19_14_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR0_DQSNSEPDR_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR0_DQSSEPDR_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR0_RTTOAL_SHIFT - | 0x00000003U << DDR_PHY_DX2GCR0_RTTOH_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR0_CPDRSHFT_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR0_DQSRPD_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR0_DQSGPDR_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR0_RESERVED_4_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR0_DQSGODT_SHIFT - | 0x00000001U << DDR_PHY_DX2GCR0_DQSGOE_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR0_RESERVED_1_0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX2GCR0_OFFSET ,0xFFFFFFFFU ,0x40800604U); - /*############################################################################################################################ */ + * DRAM DQ VREF Select for Rank3 + * PSU_DDR_PHY_DX2GCR6_DXDQVREFR3 0x9 - /*Register : DX2GCR1 @ 0XFD080904

+ * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX2GCR6_RESERVED_23_22 0x0 - Enables the PDR mode for DQ[7:0] - PSU_DDR_PHY_DX2GCR1_DXPDRMODE 0x0 + * DRAM DQ VREF Select for Rank2 + * PSU_DDR_PHY_DX2GCR6_DXDQVREFR2 0x9 - Reserved. Returns zeroes on reads. - PSU_DDR_PHY_DX2GCR1_RESERVED_15 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX2GCR6_RESERVED_15_14 0x0 - Select the delayed or non-delayed read data strobe # - PSU_DDR_PHY_DX2GCR1_QSNSEL 0x1 + * DRAM DQ VREF Select for Rank1 + * PSU_DDR_PHY_DX2GCR6_DXDQVREFR1 0x2b - Select the delayed or non-delayed read data strobe - PSU_DDR_PHY_DX2GCR1_QSSEL 0x1 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX2GCR6_RESERVED_7_6 0x0 - Enables Read Data Strobe in a byte lane - PSU_DDR_PHY_DX2GCR1_OEEN 0x1 + * DRAM DQ VREF Select for Rank0 + * PSU_DDR_PHY_DX2GCR6_DXDQVREFR0 0x2b - Enables PDR in a byte lane - PSU_DDR_PHY_DX2GCR1_PDREN 0x1 + * DATX8 n General Configuration Register 6 + * (OFFSET, MASK, VALUE) (0XFD080918, 0xFFFFFFFFU ,0x09092B2BU) + */ + PSU_Mask_Write(DDR_PHY_DX2GCR6_OFFSET, 0xFFFFFFFFU, 0x09092B2BU); +/*##################################################################### */ - Enables ODT/TE in a byte lane - PSU_DDR_PHY_DX2GCR1_TEEN 0x1 + /* + * Register : DX3GCR0 @ 0XFD080A00 - Enables Write Data strobe in a byte lane - PSU_DDR_PHY_DX2GCR1_DSEN 0x1 + * Calibration Bypass + * PSU_DDR_PHY_DX3GCR0_CALBYP 0x0 - Enables DM pin in a byte lane - PSU_DDR_PHY_DX2GCR1_DMEN 0x1 + * Master Delay Line Enable + * PSU_DDR_PHY_DX3GCR0_MDLEN 0x1 - Enables DQ corresponding to each bit in a byte - PSU_DDR_PHY_DX2GCR1_DQEN 0xff + * Configurable ODT(TE) Phase Shift + * PSU_DDR_PHY_DX3GCR0_CODTSHFT 0x0 - DATX8 n General Configuration Register 1 - (OFFSET, MASK, VALUE) (0XFD080904, 0xFFFFFFFFU ,0x00007FFFU) - RegMask = (DDR_PHY_DX2GCR1_DXPDRMODE_MASK | DDR_PHY_DX2GCR1_RESERVED_15_MASK | DDR_PHY_DX2GCR1_QSNSEL_MASK | DDR_PHY_DX2GCR1_QSSEL_MASK | DDR_PHY_DX2GCR1_OEEN_MASK | DDR_PHY_DX2GCR1_PDREN_MASK | DDR_PHY_DX2GCR1_TEEN_MASK | DDR_PHY_DX2GCR1_DSEN_MASK | DDR_PHY_DX2GCR1_DMEN_MASK | DDR_PHY_DX2GCR1_DQEN_MASK | 0 ); + * DQS Duty Cycle Correction + * PSU_DDR_PHY_DX3GCR0_DQSDCC 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX2GCR1_DXPDRMODE_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR1_RESERVED_15_SHIFT - | 0x00000001U << DDR_PHY_DX2GCR1_QSNSEL_SHIFT - | 0x00000001U << DDR_PHY_DX2GCR1_QSSEL_SHIFT - | 0x00000001U << DDR_PHY_DX2GCR1_OEEN_SHIFT - | 0x00000001U << DDR_PHY_DX2GCR1_PDREN_SHIFT - | 0x00000001U << DDR_PHY_DX2GCR1_TEEN_SHIFT - | 0x00000001U << DDR_PHY_DX2GCR1_DSEN_SHIFT - | 0x00000001U << DDR_PHY_DX2GCR1_DMEN_SHIFT - | 0x000000FFU << DDR_PHY_DX2GCR1_DQEN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX2GCR1_OFFSET ,0xFFFFFFFFU ,0x00007FFFU); - /*############################################################################################################################ */ + * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY + * PSU_DDR_PHY_DX3GCR0_RDDLY 0x8 - /*Register : DX2GCR4 @ 0XFD080910

+ * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX3GCR0_RESERVED_19_14 0x0 - Byte lane VREF IOM (Used only by D4MU IOs) - PSU_DDR_PHY_DX2GCR4_RESERVED_31_29 0x0 + * DQSNSE Power Down Receiver + * PSU_DDR_PHY_DX3GCR0_DQSNSEPDR 0x0 - Byte Lane VREF Pad Enable - PSU_DDR_PHY_DX2GCR4_DXREFPEN 0x0 + * DQSSE Power Down Receiver + * PSU_DDR_PHY_DX3GCR0_DQSSEPDR 0x0 - Byte Lane Internal VREF Enable - PSU_DDR_PHY_DX2GCR4_DXREFEEN 0x3 + * RTT On Additive Latency + * PSU_DDR_PHY_DX3GCR0_RTTOAL 0x0 - Byte Lane Single-End VREF Enable - PSU_DDR_PHY_DX2GCR4_DXREFSEN 0x1 + * RTT Output Hold + * PSU_DDR_PHY_DX3GCR0_RTTOH 0x3 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX2GCR4_RESERVED_24 0x0 + * Configurable PDR Phase Shift + * PSU_DDR_PHY_DX3GCR0_CPDRSHFT 0x0 - External VREF generator REFSEL range select - PSU_DDR_PHY_DX2GCR4_DXREFESELRANGE 0x0 + * DQSR Power Down + * PSU_DDR_PHY_DX3GCR0_DQSRPD 0x0 - Byte Lane External VREF Select - PSU_DDR_PHY_DX2GCR4_DXREFESEL 0x0 + * DQSG Power Down Receiver + * PSU_DDR_PHY_DX3GCR0_DQSGPDR 0x0 - Single ended VREF generator REFSEL range select - PSU_DDR_PHY_DX2GCR4_DXREFSSELRANGE 0x1 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX3GCR0_RESERVED_4 0x0 - Byte Lane Single-End VREF Select - PSU_DDR_PHY_DX2GCR4_DXREFSSEL 0x30 + * DQSG On-Die Termination + * PSU_DDR_PHY_DX3GCR0_DQSGODT 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX2GCR4_RESERVED_7_6 0x0 + * DQSG Output Enable + * PSU_DDR_PHY_DX3GCR0_DQSGOE 0x1 - VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. - PSU_DDR_PHY_DX2GCR4_DXREFIEN 0xf + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX3GCR0_RESERVED_1_0 0x0 - VRMON control for DQ IO (Single Ended) buffers of a byte lane. - PSU_DDR_PHY_DX2GCR4_DXREFIMON 0x0 + * DATX8 n General Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD080A00, 0xFFFFFFFFU ,0x40800604U) + */ + PSU_Mask_Write(DDR_PHY_DX3GCR0_OFFSET, 0xFFFFFFFFU, 0x40800604U); +/*##################################################################### */ - DATX8 n General Configuration Register 4 - (OFFSET, MASK, VALUE) (0XFD080910, 0xFFFFFFFFU ,0x0E00B03CU) - RegMask = (DDR_PHY_DX2GCR4_RESERVED_31_29_MASK | DDR_PHY_DX2GCR4_DXREFPEN_MASK | DDR_PHY_DX2GCR4_DXREFEEN_MASK | DDR_PHY_DX2GCR4_DXREFSEN_MASK | DDR_PHY_DX2GCR4_RESERVED_24_MASK | DDR_PHY_DX2GCR4_DXREFESELRANGE_MASK | DDR_PHY_DX2GCR4_DXREFESEL_MASK | DDR_PHY_DX2GCR4_DXREFSSELRANGE_MASK | DDR_PHY_DX2GCR4_DXREFSSEL_MASK | DDR_PHY_DX2GCR4_RESERVED_7_6_MASK | DDR_PHY_DX2GCR4_DXREFIEN_MASK | DDR_PHY_DX2GCR4_DXREFIMON_MASK | 0 ); + /* + * Register : DX3GCR1 @ 0XFD080A04 - RegVal = ((0x00000000U << DDR_PHY_DX2GCR4_RESERVED_31_29_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR4_DXREFPEN_SHIFT - | 0x00000003U << DDR_PHY_DX2GCR4_DXREFEEN_SHIFT - | 0x00000001U << DDR_PHY_DX2GCR4_DXREFSEN_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR4_RESERVED_24_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR4_DXREFESELRANGE_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR4_DXREFESEL_SHIFT - | 0x00000001U << DDR_PHY_DX2GCR4_DXREFSSELRANGE_SHIFT - | 0x00000030U << DDR_PHY_DX2GCR4_DXREFSSEL_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR4_RESERVED_7_6_SHIFT - | 0x0000000FU << DDR_PHY_DX2GCR4_DXREFIEN_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR4_DXREFIMON_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX2GCR4_OFFSET ,0xFFFFFFFFU ,0x0E00B03CU); - /*############################################################################################################################ */ + * Enables the PDR mode for DQ[7:0] + * PSU_DDR_PHY_DX3GCR1_DXPDRMODE 0x0 - /*Register : DX2GCR5 @ 0XFD080914

+ * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX3GCR1_RESERVED_15 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX2GCR5_RESERVED_31 0x0 + * Select the delayed or non-delayed read data strobe # + * PSU_DDR_PHY_DX3GCR1_QSNSEL 0x1 - Byte Lane internal VREF Select for Rank 3 - PSU_DDR_PHY_DX2GCR5_DXREFISELR3 0x9 + * Select the delayed or non-delayed read data strobe + * PSU_DDR_PHY_DX3GCR1_QSSEL 0x1 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX2GCR5_RESERVED_23 0x0 + * Enables Read Data Strobe in a byte lane + * PSU_DDR_PHY_DX3GCR1_OEEN 0x1 - Byte Lane internal VREF Select for Rank 2 - PSU_DDR_PHY_DX2GCR5_DXREFISELR2 0x9 + * Enables PDR in a byte lane + * PSU_DDR_PHY_DX3GCR1_PDREN 0x1 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX2GCR5_RESERVED_15 0x0 + * Enables ODT/TE in a byte lane + * PSU_DDR_PHY_DX3GCR1_TEEN 0x1 - Byte Lane internal VREF Select for Rank 1 - PSU_DDR_PHY_DX2GCR5_DXREFISELR1 0x4f + * Enables Write Data strobe in a byte lane + * PSU_DDR_PHY_DX3GCR1_DSEN 0x1 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX2GCR5_RESERVED_7 0x0 + * Enables DM pin in a byte lane + * PSU_DDR_PHY_DX3GCR1_DMEN 0x1 - Byte Lane internal VREF Select for Rank 0 - PSU_DDR_PHY_DX2GCR5_DXREFISELR0 0x4f + * Enables DQ corresponding to each bit in a byte + * PSU_DDR_PHY_DX3GCR1_DQEN 0xff - DATX8 n General Configuration Register 5 - (OFFSET, MASK, VALUE) (0XFD080914, 0xFFFFFFFFU ,0x09094F4FU) - RegMask = (DDR_PHY_DX2GCR5_RESERVED_31_MASK | DDR_PHY_DX2GCR5_DXREFISELR3_MASK | DDR_PHY_DX2GCR5_RESERVED_23_MASK | DDR_PHY_DX2GCR5_DXREFISELR2_MASK | DDR_PHY_DX2GCR5_RESERVED_15_MASK | DDR_PHY_DX2GCR5_DXREFISELR1_MASK | DDR_PHY_DX2GCR5_RESERVED_7_MASK | DDR_PHY_DX2GCR5_DXREFISELR0_MASK | 0 ); + * DATX8 n General Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD080A04, 0xFFFFFFFFU ,0x00007FFFU) + */ + PSU_Mask_Write(DDR_PHY_DX3GCR1_OFFSET, 0xFFFFFFFFU, 0x00007FFFU); +/*##################################################################### */ - RegVal = ((0x00000000U << DDR_PHY_DX2GCR5_RESERVED_31_SHIFT - | 0x00000009U << DDR_PHY_DX2GCR5_DXREFISELR3_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR5_RESERVED_23_SHIFT - | 0x00000009U << DDR_PHY_DX2GCR5_DXREFISELR2_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR5_RESERVED_15_SHIFT - | 0x0000004FU << DDR_PHY_DX2GCR5_DXREFISELR1_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR5_RESERVED_7_SHIFT - | 0x0000004FU << DDR_PHY_DX2GCR5_DXREFISELR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX2GCR5_OFFSET ,0xFFFFFFFFU ,0x09094F4FU); - /*############################################################################################################################ */ + /* + * Register : DX3GCR4 @ 0XFD080A10 - /*Register : DX2GCR6 @ 0XFD080918

+ * Byte lane VREF IOM (Used only by D4MU IOs) + * PSU_DDR_PHY_DX3GCR4_RESERVED_31_29 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX2GCR6_RESERVED_31_30 0x0 + * Byte Lane VREF Pad Enable + * PSU_DDR_PHY_DX3GCR4_DXREFPEN 0x0 - DRAM DQ VREF Select for Rank3 - PSU_DDR_PHY_DX2GCR6_DXDQVREFR3 0x9 + * Byte Lane Internal VREF Enable + * PSU_DDR_PHY_DX3GCR4_DXREFEEN 0x3 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX2GCR6_RESERVED_23_22 0x0 + * Byte Lane Single-End VREF Enable + * PSU_DDR_PHY_DX3GCR4_DXREFSEN 0x1 - DRAM DQ VREF Select for Rank2 - PSU_DDR_PHY_DX2GCR6_DXDQVREFR2 0x9 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX3GCR4_RESERVED_24 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX2GCR6_RESERVED_15_14 0x0 + * External VREF generator REFSEL range select + * PSU_DDR_PHY_DX3GCR4_DXREFESELRANGE 0x0 - DRAM DQ VREF Select for Rank1 - PSU_DDR_PHY_DX2GCR6_DXDQVREFR1 0x2b + * Byte Lane External VREF Select + * PSU_DDR_PHY_DX3GCR4_DXREFESEL 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX2GCR6_RESERVED_7_6 0x0 + * Single ended VREF generator REFSEL range select + * PSU_DDR_PHY_DX3GCR4_DXREFSSELRANGE 0x1 - DRAM DQ VREF Select for Rank0 - PSU_DDR_PHY_DX2GCR6_DXDQVREFR0 0x2b + * Byte Lane Single-End VREF Select + * PSU_DDR_PHY_DX3GCR4_DXREFSSEL 0x30 - DATX8 n General Configuration Register 6 - (OFFSET, MASK, VALUE) (0XFD080918, 0xFFFFFFFFU ,0x09092B2BU) - RegMask = (DDR_PHY_DX2GCR6_RESERVED_31_30_MASK | DDR_PHY_DX2GCR6_DXDQVREFR3_MASK | DDR_PHY_DX2GCR6_RESERVED_23_22_MASK | DDR_PHY_DX2GCR6_DXDQVREFR2_MASK | DDR_PHY_DX2GCR6_RESERVED_15_14_MASK | DDR_PHY_DX2GCR6_DXDQVREFR1_MASK | DDR_PHY_DX2GCR6_RESERVED_7_6_MASK | DDR_PHY_DX2GCR6_DXDQVREFR0_MASK | 0 ); + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX3GCR4_RESERVED_7_6 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX2GCR6_RESERVED_31_30_SHIFT - | 0x00000009U << DDR_PHY_DX2GCR6_DXDQVREFR3_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR6_RESERVED_23_22_SHIFT - | 0x00000009U << DDR_PHY_DX2GCR6_DXDQVREFR2_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR6_RESERVED_15_14_SHIFT - | 0x0000002BU << DDR_PHY_DX2GCR6_DXDQVREFR1_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR6_RESERVED_7_6_SHIFT - | 0x0000002BU << DDR_PHY_DX2GCR6_DXDQVREFR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX2GCR6_OFFSET ,0xFFFFFFFFU ,0x09092B2BU); - /*############################################################################################################################ */ + * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX3GCR4_DXREFIEN 0xf - /*Register : DX2LCDLR2 @ 0XFD080988

+ * VRMON control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX3GCR4_DXREFIMON 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX2LCDLR2_RESERVED_31_25 0x0 + * DATX8 n General Configuration Register 4 + * (OFFSET, MASK, VALUE) (0XFD080A10, 0xFFFFFFFFU ,0x0E00B03CU) + */ + PSU_Mask_Write(DDR_PHY_DX3GCR4_OFFSET, 0xFFFFFFFFU, 0x0E00B03CU); +/*##################################################################### */ - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX2LCDLR2_RESERVED_24_16 0x0 + /* + * Register : DX3GCR5 @ 0XFD080A14 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX2LCDLR2_RESERVED_15_9 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX3GCR5_RESERVED_31 0x0 - Read DQS Gating Delay - PSU_DDR_PHY_DX2LCDLR2_DQSGD 0x0 + * Byte Lane internal VREF Select for Rank 3 + * PSU_DDR_PHY_DX3GCR5_DXREFISELR3 0x9 - DATX8 n Local Calibrated Delay Line Register 2 - (OFFSET, MASK, VALUE) (0XFD080988, 0xFFFFFFFFU ,0x00000000U) - RegMask = (DDR_PHY_DX2LCDLR2_RESERVED_31_25_MASK | DDR_PHY_DX2LCDLR2_RESERVED_24_16_MASK | DDR_PHY_DX2LCDLR2_RESERVED_15_9_MASK | DDR_PHY_DX2LCDLR2_DQSGD_MASK | 0 ); + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX3GCR5_RESERVED_23 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX2LCDLR2_RESERVED_31_25_SHIFT - | 0x00000000U << DDR_PHY_DX2LCDLR2_RESERVED_24_16_SHIFT - | 0x00000000U << DDR_PHY_DX2LCDLR2_RESERVED_15_9_SHIFT - | 0x00000000U << DDR_PHY_DX2LCDLR2_DQSGD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX2LCDLR2_OFFSET ,0xFFFFFFFFU ,0x00000000U); - /*############################################################################################################################ */ + * Byte Lane internal VREF Select for Rank 2 + * PSU_DDR_PHY_DX3GCR5_DXREFISELR2 0x9 - /*Register : DX2GTR0 @ 0XFD0809C0

+ * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX3GCR5_RESERVED_15 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX2GTR0_RESERVED_31_24 0x0 + * Byte Lane internal VREF Select for Rank 1 + * PSU_DDR_PHY_DX3GCR5_DXREFISELR1 0x55 - DQ Write Path Latency Pipeline - PSU_DDR_PHY_DX2GTR0_WDQSL 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX3GCR5_RESERVED_7 0x0 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX2GTR0_RESERVED_23_20 0x0 + * Byte Lane internal VREF Select for Rank 0 + * PSU_DDR_PHY_DX3GCR5_DXREFISELR0 0x55 - Write Leveling System Latency - PSU_DDR_PHY_DX2GTR0_WLSL 0x2 + * DATX8 n General Configuration Register 5 + * (OFFSET, MASK, VALUE) (0XFD080A14, 0xFFFFFFFFU ,0x09095555U) + */ + PSU_Mask_Write(DDR_PHY_DX3GCR5_OFFSET, 0xFFFFFFFFU, 0x09095555U); +/*##################################################################### */ - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX2GTR0_RESERVED_15_13 0x0 + /* + * Register : DX3GCR6 @ 0XFD080A18 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX2GTR0_RESERVED_12_8 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX3GCR6_RESERVED_31_30 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX2GTR0_RESERVED_7_5 0x0 + * DRAM DQ VREF Select for Rank3 + * PSU_DDR_PHY_DX3GCR6_DXDQVREFR3 0x9 - DQS Gating System Latency - PSU_DDR_PHY_DX2GTR0_DGSL 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX3GCR6_RESERVED_23_22 0x0 - DATX8 n General Timing Register 0 - (OFFSET, MASK, VALUE) (0XFD0809C0, 0xFFFFFFFFU ,0x00020000U) - RegMask = (DDR_PHY_DX2GTR0_RESERVED_31_24_MASK | DDR_PHY_DX2GTR0_WDQSL_MASK | DDR_PHY_DX2GTR0_RESERVED_23_20_MASK | DDR_PHY_DX2GTR0_WLSL_MASK | DDR_PHY_DX2GTR0_RESERVED_15_13_MASK | DDR_PHY_DX2GTR0_RESERVED_12_8_MASK | DDR_PHY_DX2GTR0_RESERVED_7_5_MASK | DDR_PHY_DX2GTR0_DGSL_MASK | 0 ); + * DRAM DQ VREF Select for Rank2 + * PSU_DDR_PHY_DX3GCR6_DXDQVREFR2 0x9 - RegVal = ((0x00000000U << DDR_PHY_DX2GTR0_RESERVED_31_24_SHIFT - | 0x00000000U << DDR_PHY_DX2GTR0_WDQSL_SHIFT - | 0x00000000U << DDR_PHY_DX2GTR0_RESERVED_23_20_SHIFT - | 0x00000002U << DDR_PHY_DX2GTR0_WLSL_SHIFT - | 0x00000000U << DDR_PHY_DX2GTR0_RESERVED_15_13_SHIFT - | 0x00000000U << DDR_PHY_DX2GTR0_RESERVED_12_8_SHIFT - | 0x00000000U << DDR_PHY_DX2GTR0_RESERVED_7_5_SHIFT - | 0x00000000U << DDR_PHY_DX2GTR0_DGSL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX2GTR0_OFFSET ,0xFFFFFFFFU ,0x00020000U); - /*############################################################################################################################ */ + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX3GCR6_RESERVED_15_14 0x0 - /*Register : DX3GCR0 @ 0XFD080A00

+ * DRAM DQ VREF Select for Rank1 + * PSU_DDR_PHY_DX3GCR6_DXDQVREFR1 0x2b - Calibration Bypass - PSU_DDR_PHY_DX3GCR0_CALBYP 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX3GCR6_RESERVED_7_6 0x0 - Master Delay Line Enable - PSU_DDR_PHY_DX3GCR0_MDLEN 0x1 + * DRAM DQ VREF Select for Rank0 + * PSU_DDR_PHY_DX3GCR6_DXDQVREFR0 0x2b - Configurable ODT(TE) Phase Shift - PSU_DDR_PHY_DX3GCR0_CODTSHFT 0x0 + * DATX8 n General Configuration Register 6 + * (OFFSET, MASK, VALUE) (0XFD080A18, 0xFFFFFFFFU ,0x09092B2BU) + */ + PSU_Mask_Write(DDR_PHY_DX3GCR6_OFFSET, 0xFFFFFFFFU, 0x09092B2BU); +/*##################################################################### */ - DQS Duty Cycle Correction - PSU_DDR_PHY_DX3GCR0_DQSDCC 0x0 + /* + * Register : DX4GCR0 @ 0XFD080B00 - Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY - PSU_DDR_PHY_DX3GCR0_RDDLY 0x8 + * Calibration Bypass + * PSU_DDR_PHY_DX4GCR0_CALBYP 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX3GCR0_RESERVED_19_14 0x0 + * Master Delay Line Enable + * PSU_DDR_PHY_DX4GCR0_MDLEN 0x1 - DQSNSE Power Down Receiver - PSU_DDR_PHY_DX3GCR0_DQSNSEPDR 0x0 + * Configurable ODT(TE) Phase Shift + * PSU_DDR_PHY_DX4GCR0_CODTSHFT 0x0 - DQSSE Power Down Receiver - PSU_DDR_PHY_DX3GCR0_DQSSEPDR 0x0 + * DQS Duty Cycle Correction + * PSU_DDR_PHY_DX4GCR0_DQSDCC 0x0 - RTT On Additive Latency - PSU_DDR_PHY_DX3GCR0_RTTOAL 0x0 + * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY + * PSU_DDR_PHY_DX4GCR0_RDDLY 0x8 - RTT Output Hold - PSU_DDR_PHY_DX3GCR0_RTTOH 0x3 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX4GCR0_RESERVED_19_14 0x0 - Configurable PDR Phase Shift - PSU_DDR_PHY_DX3GCR0_CPDRSHFT 0x0 + * DQSNSE Power Down Receiver + * PSU_DDR_PHY_DX4GCR0_DQSNSEPDR 0x0 - DQSR Power Down - PSU_DDR_PHY_DX3GCR0_DQSRPD 0x0 + * DQSSE Power Down Receiver + * PSU_DDR_PHY_DX4GCR0_DQSSEPDR 0x0 - DQSG Power Down Receiver - PSU_DDR_PHY_DX3GCR0_DQSGPDR 0x0 + * RTT On Additive Latency + * PSU_DDR_PHY_DX4GCR0_RTTOAL 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX3GCR0_RESERVED_4 0x0 + * RTT Output Hold + * PSU_DDR_PHY_DX4GCR0_RTTOH 0x3 - DQSG On-Die Termination - PSU_DDR_PHY_DX3GCR0_DQSGODT 0x0 + * Configurable PDR Phase Shift + * PSU_DDR_PHY_DX4GCR0_CPDRSHFT 0x0 - DQSG Output Enable - PSU_DDR_PHY_DX3GCR0_DQSGOE 0x1 + * DQSR Power Down + * PSU_DDR_PHY_DX4GCR0_DQSRPD 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX3GCR0_RESERVED_1_0 0x0 + * DQSG Power Down Receiver + * PSU_DDR_PHY_DX4GCR0_DQSGPDR 0x0 - DATX8 n General Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD080A00, 0xFFFFFFFFU ,0x40800604U) - RegMask = (DDR_PHY_DX3GCR0_CALBYP_MASK | DDR_PHY_DX3GCR0_MDLEN_MASK | DDR_PHY_DX3GCR0_CODTSHFT_MASK | DDR_PHY_DX3GCR0_DQSDCC_MASK | DDR_PHY_DX3GCR0_RDDLY_MASK | DDR_PHY_DX3GCR0_RESERVED_19_14_MASK | DDR_PHY_DX3GCR0_DQSNSEPDR_MASK | DDR_PHY_DX3GCR0_DQSSEPDR_MASK | DDR_PHY_DX3GCR0_RTTOAL_MASK | DDR_PHY_DX3GCR0_RTTOH_MASK | DDR_PHY_DX3GCR0_CPDRSHFT_MASK | DDR_PHY_DX3GCR0_DQSRPD_MASK | DDR_PHY_DX3GCR0_DQSGPDR_MASK | DDR_PHY_DX3GCR0_RESERVED_4_MASK | DDR_PHY_DX3GCR0_DQSGODT_MASK | DDR_PHY_DX3GCR0_DQSGOE_MASK | DDR_PHY_DX3GCR0_RESERVED_1_0_MASK | 0 ); + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX4GCR0_RESERVED_4 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX3GCR0_CALBYP_SHIFT - | 0x00000001U << DDR_PHY_DX3GCR0_MDLEN_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR0_CODTSHFT_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR0_DQSDCC_SHIFT - | 0x00000008U << DDR_PHY_DX3GCR0_RDDLY_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR0_RESERVED_19_14_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR0_DQSNSEPDR_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR0_DQSSEPDR_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR0_RTTOAL_SHIFT - | 0x00000003U << DDR_PHY_DX3GCR0_RTTOH_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR0_CPDRSHFT_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR0_DQSRPD_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR0_DQSGPDR_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR0_RESERVED_4_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR0_DQSGODT_SHIFT - | 0x00000001U << DDR_PHY_DX3GCR0_DQSGOE_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR0_RESERVED_1_0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX3GCR0_OFFSET ,0xFFFFFFFFU ,0x40800604U); - /*############################################################################################################################ */ + * DQSG On-Die Termination + * PSU_DDR_PHY_DX4GCR0_DQSGODT 0x0 - /*Register : DX3GCR1 @ 0XFD080A04

+ * DQSG Output Enable + * PSU_DDR_PHY_DX4GCR0_DQSGOE 0x1 - Enables the PDR mode for DQ[7:0] - PSU_DDR_PHY_DX3GCR1_DXPDRMODE 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX4GCR0_RESERVED_1_0 0x0 - Reserved. Returns zeroes on reads. - PSU_DDR_PHY_DX3GCR1_RESERVED_15 0x0 + * DATX8 n General Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD080B00, 0xFFFFFFFFU ,0x40800604U) + */ + PSU_Mask_Write(DDR_PHY_DX4GCR0_OFFSET, 0xFFFFFFFFU, 0x40800604U); +/*##################################################################### */ - Select the delayed or non-delayed read data strobe # - PSU_DDR_PHY_DX3GCR1_QSNSEL 0x1 + /* + * Register : DX4GCR1 @ 0XFD080B04 - Select the delayed or non-delayed read data strobe - PSU_DDR_PHY_DX3GCR1_QSSEL 0x1 + * Enables the PDR mode for DQ[7:0] + * PSU_DDR_PHY_DX4GCR1_DXPDRMODE 0x0 - Enables Read Data Strobe in a byte lane - PSU_DDR_PHY_DX3GCR1_OEEN 0x1 + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX4GCR1_RESERVED_15 0x0 - Enables PDR in a byte lane - PSU_DDR_PHY_DX3GCR1_PDREN 0x1 + * Select the delayed or non-delayed read data strobe # + * PSU_DDR_PHY_DX4GCR1_QSNSEL 0x1 - Enables ODT/TE in a byte lane - PSU_DDR_PHY_DX3GCR1_TEEN 0x1 + * Select the delayed or non-delayed read data strobe + * PSU_DDR_PHY_DX4GCR1_QSSEL 0x1 - Enables Write Data strobe in a byte lane - PSU_DDR_PHY_DX3GCR1_DSEN 0x1 + * Enables Read Data Strobe in a byte lane + * PSU_DDR_PHY_DX4GCR1_OEEN 0x1 - Enables DM pin in a byte lane - PSU_DDR_PHY_DX3GCR1_DMEN 0x1 + * Enables PDR in a byte lane + * PSU_DDR_PHY_DX4GCR1_PDREN 0x1 - Enables DQ corresponding to each bit in a byte - PSU_DDR_PHY_DX3GCR1_DQEN 0xff + * Enables ODT/TE in a byte lane + * PSU_DDR_PHY_DX4GCR1_TEEN 0x1 - DATX8 n General Configuration Register 1 - (OFFSET, MASK, VALUE) (0XFD080A04, 0xFFFFFFFFU ,0x00007FFFU) - RegMask = (DDR_PHY_DX3GCR1_DXPDRMODE_MASK | DDR_PHY_DX3GCR1_RESERVED_15_MASK | DDR_PHY_DX3GCR1_QSNSEL_MASK | DDR_PHY_DX3GCR1_QSSEL_MASK | DDR_PHY_DX3GCR1_OEEN_MASK | DDR_PHY_DX3GCR1_PDREN_MASK | DDR_PHY_DX3GCR1_TEEN_MASK | DDR_PHY_DX3GCR1_DSEN_MASK | DDR_PHY_DX3GCR1_DMEN_MASK | DDR_PHY_DX3GCR1_DQEN_MASK | 0 ); + * Enables Write Data strobe in a byte lane + * PSU_DDR_PHY_DX4GCR1_DSEN 0x1 - RegVal = ((0x00000000U << DDR_PHY_DX3GCR1_DXPDRMODE_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR1_RESERVED_15_SHIFT - | 0x00000001U << DDR_PHY_DX3GCR1_QSNSEL_SHIFT - | 0x00000001U << DDR_PHY_DX3GCR1_QSSEL_SHIFT - | 0x00000001U << DDR_PHY_DX3GCR1_OEEN_SHIFT - | 0x00000001U << DDR_PHY_DX3GCR1_PDREN_SHIFT - | 0x00000001U << DDR_PHY_DX3GCR1_TEEN_SHIFT - | 0x00000001U << DDR_PHY_DX3GCR1_DSEN_SHIFT - | 0x00000001U << DDR_PHY_DX3GCR1_DMEN_SHIFT - | 0x000000FFU << DDR_PHY_DX3GCR1_DQEN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX3GCR1_OFFSET ,0xFFFFFFFFU ,0x00007FFFU); - /*############################################################################################################################ */ + * Enables DM pin in a byte lane + * PSU_DDR_PHY_DX4GCR1_DMEN 0x1 - /*Register : DX3GCR4 @ 0XFD080A10

+ * Enables DQ corresponding to each bit in a byte + * PSU_DDR_PHY_DX4GCR1_DQEN 0xff - Byte lane VREF IOM (Used only by D4MU IOs) - PSU_DDR_PHY_DX3GCR4_RESERVED_31_29 0x0 + * DATX8 n General Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD080B04, 0xFFFFFFFFU ,0x00007FFFU) + */ + PSU_Mask_Write(DDR_PHY_DX4GCR1_OFFSET, 0xFFFFFFFFU, 0x00007FFFU); +/*##################################################################### */ - Byte Lane VREF Pad Enable - PSU_DDR_PHY_DX3GCR4_DXREFPEN 0x0 + /* + * Register : DX4GCR4 @ 0XFD080B10 - Byte Lane Internal VREF Enable - PSU_DDR_PHY_DX3GCR4_DXREFEEN 0x3 + * Byte lane VREF IOM (Used only by D4MU IOs) + * PSU_DDR_PHY_DX4GCR4_RESERVED_31_29 0x0 - Byte Lane Single-End VREF Enable - PSU_DDR_PHY_DX3GCR4_DXREFSEN 0x1 + * Byte Lane VREF Pad Enable + * PSU_DDR_PHY_DX4GCR4_DXREFPEN 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX3GCR4_RESERVED_24 0x0 + * Byte Lane Internal VREF Enable + * PSU_DDR_PHY_DX4GCR4_DXREFEEN 0x3 - External VREF generator REFSEL range select - PSU_DDR_PHY_DX3GCR4_DXREFESELRANGE 0x0 + * Byte Lane Single-End VREF Enable + * PSU_DDR_PHY_DX4GCR4_DXREFSEN 0x1 - Byte Lane External VREF Select - PSU_DDR_PHY_DX3GCR4_DXREFESEL 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX4GCR4_RESERVED_24 0x0 - Single ended VREF generator REFSEL range select - PSU_DDR_PHY_DX3GCR4_DXREFSSELRANGE 0x1 + * External VREF generator REFSEL range select + * PSU_DDR_PHY_DX4GCR4_DXREFESELRANGE 0x0 - Byte Lane Single-End VREF Select - PSU_DDR_PHY_DX3GCR4_DXREFSSEL 0x30 + * Byte Lane External VREF Select + * PSU_DDR_PHY_DX4GCR4_DXREFESEL 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX3GCR4_RESERVED_7_6 0x0 + * Single ended VREF generator REFSEL range select + * PSU_DDR_PHY_DX4GCR4_DXREFSSELRANGE 0x1 - VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. - PSU_DDR_PHY_DX3GCR4_DXREFIEN 0xf + * Byte Lane Single-End VREF Select + * PSU_DDR_PHY_DX4GCR4_DXREFSSEL 0x30 - VRMON control for DQ IO (Single Ended) buffers of a byte lane. - PSU_DDR_PHY_DX3GCR4_DXREFIMON 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX4GCR4_RESERVED_7_6 0x0 - DATX8 n General Configuration Register 4 - (OFFSET, MASK, VALUE) (0XFD080A10, 0xFFFFFFFFU ,0x0E00B03CU) - RegMask = (DDR_PHY_DX3GCR4_RESERVED_31_29_MASK | DDR_PHY_DX3GCR4_DXREFPEN_MASK | DDR_PHY_DX3GCR4_DXREFEEN_MASK | DDR_PHY_DX3GCR4_DXREFSEN_MASK | DDR_PHY_DX3GCR4_RESERVED_24_MASK | DDR_PHY_DX3GCR4_DXREFESELRANGE_MASK | DDR_PHY_DX3GCR4_DXREFESEL_MASK | DDR_PHY_DX3GCR4_DXREFSSELRANGE_MASK | DDR_PHY_DX3GCR4_DXREFSSEL_MASK | DDR_PHY_DX3GCR4_RESERVED_7_6_MASK | DDR_PHY_DX3GCR4_DXREFIEN_MASK | DDR_PHY_DX3GCR4_DXREFIMON_MASK | 0 ); + * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX4GCR4_DXREFIEN 0xf - RegVal = ((0x00000000U << DDR_PHY_DX3GCR4_RESERVED_31_29_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR4_DXREFPEN_SHIFT - | 0x00000003U << DDR_PHY_DX3GCR4_DXREFEEN_SHIFT - | 0x00000001U << DDR_PHY_DX3GCR4_DXREFSEN_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR4_RESERVED_24_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR4_DXREFESELRANGE_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR4_DXREFESEL_SHIFT - | 0x00000001U << DDR_PHY_DX3GCR4_DXREFSSELRANGE_SHIFT - | 0x00000030U << DDR_PHY_DX3GCR4_DXREFSSEL_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR4_RESERVED_7_6_SHIFT - | 0x0000000FU << DDR_PHY_DX3GCR4_DXREFIEN_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR4_DXREFIMON_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX3GCR4_OFFSET ,0xFFFFFFFFU ,0x0E00B03CU); - /*############################################################################################################################ */ + * VRMON control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX4GCR4_DXREFIMON 0x0 - /*Register : DX3GCR5 @ 0XFD080A14

+ * DATX8 n General Configuration Register 4 + * (OFFSET, MASK, VALUE) (0XFD080B10, 0xFFFFFFFFU ,0x0E00B03CU) + */ + PSU_Mask_Write(DDR_PHY_DX4GCR4_OFFSET, 0xFFFFFFFFU, 0x0E00B03CU); +/*##################################################################### */ - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX3GCR5_RESERVED_31 0x0 + /* + * Register : DX4GCR5 @ 0XFD080B14 - Byte Lane internal VREF Select for Rank 3 - PSU_DDR_PHY_DX3GCR5_DXREFISELR3 0x9 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX4GCR5_RESERVED_31 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX3GCR5_RESERVED_23 0x0 + * Byte Lane internal VREF Select for Rank 3 + * PSU_DDR_PHY_DX4GCR5_DXREFISELR3 0x9 - Byte Lane internal VREF Select for Rank 2 - PSU_DDR_PHY_DX3GCR5_DXREFISELR2 0x9 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX4GCR5_RESERVED_23 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX3GCR5_RESERVED_15 0x0 + * Byte Lane internal VREF Select for Rank 2 + * PSU_DDR_PHY_DX4GCR5_DXREFISELR2 0x9 - Byte Lane internal VREF Select for Rank 1 - PSU_DDR_PHY_DX3GCR5_DXREFISELR1 0x4f + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX4GCR5_RESERVED_15 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX3GCR5_RESERVED_7 0x0 + * Byte Lane internal VREF Select for Rank 1 + * PSU_DDR_PHY_DX4GCR5_DXREFISELR1 0x55 - Byte Lane internal VREF Select for Rank 0 - PSU_DDR_PHY_DX3GCR5_DXREFISELR0 0x4f + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX4GCR5_RESERVED_7 0x0 - DATX8 n General Configuration Register 5 - (OFFSET, MASK, VALUE) (0XFD080A14, 0xFFFFFFFFU ,0x09094F4FU) - RegMask = (DDR_PHY_DX3GCR5_RESERVED_31_MASK | DDR_PHY_DX3GCR5_DXREFISELR3_MASK | DDR_PHY_DX3GCR5_RESERVED_23_MASK | DDR_PHY_DX3GCR5_DXREFISELR2_MASK | DDR_PHY_DX3GCR5_RESERVED_15_MASK | DDR_PHY_DX3GCR5_DXREFISELR1_MASK | DDR_PHY_DX3GCR5_RESERVED_7_MASK | DDR_PHY_DX3GCR5_DXREFISELR0_MASK | 0 ); + * Byte Lane internal VREF Select for Rank 0 + * PSU_DDR_PHY_DX4GCR5_DXREFISELR0 0x55 - RegVal = ((0x00000000U << DDR_PHY_DX3GCR5_RESERVED_31_SHIFT - | 0x00000009U << DDR_PHY_DX3GCR5_DXREFISELR3_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR5_RESERVED_23_SHIFT - | 0x00000009U << DDR_PHY_DX3GCR5_DXREFISELR2_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR5_RESERVED_15_SHIFT - | 0x0000004FU << DDR_PHY_DX3GCR5_DXREFISELR1_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR5_RESERVED_7_SHIFT - | 0x0000004FU << DDR_PHY_DX3GCR5_DXREFISELR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX3GCR5_OFFSET ,0xFFFFFFFFU ,0x09094F4FU); - /*############################################################################################################################ */ + * DATX8 n General Configuration Register 5 + * (OFFSET, MASK, VALUE) (0XFD080B14, 0xFFFFFFFFU ,0x09095555U) + */ + PSU_Mask_Write(DDR_PHY_DX4GCR5_OFFSET, 0xFFFFFFFFU, 0x09095555U); +/*##################################################################### */ - /*Register : DX3GCR6 @ 0XFD080A18

+ /* + * Register : DX4GCR6 @ 0XFD080B18 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX3GCR6_RESERVED_31_30 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX4GCR6_RESERVED_31_30 0x0 - DRAM DQ VREF Select for Rank3 - PSU_DDR_PHY_DX3GCR6_DXDQVREFR3 0x9 + * DRAM DQ VREF Select for Rank3 + * PSU_DDR_PHY_DX4GCR6_DXDQVREFR3 0x9 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX3GCR6_RESERVED_23_22 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX4GCR6_RESERVED_23_22 0x0 - DRAM DQ VREF Select for Rank2 - PSU_DDR_PHY_DX3GCR6_DXDQVREFR2 0x9 + * DRAM DQ VREF Select for Rank2 + * PSU_DDR_PHY_DX4GCR6_DXDQVREFR2 0x9 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX3GCR6_RESERVED_15_14 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX4GCR6_RESERVED_15_14 0x0 - DRAM DQ VREF Select for Rank1 - PSU_DDR_PHY_DX3GCR6_DXDQVREFR1 0x2b + * DRAM DQ VREF Select for Rank1 + * PSU_DDR_PHY_DX4GCR6_DXDQVREFR1 0x2b - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX3GCR6_RESERVED_7_6 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX4GCR6_RESERVED_7_6 0x0 - DRAM DQ VREF Select for Rank0 - PSU_DDR_PHY_DX3GCR6_DXDQVREFR0 0x2b + * DRAM DQ VREF Select for Rank0 + * PSU_DDR_PHY_DX4GCR6_DXDQVREFR0 0x2b - DATX8 n General Configuration Register 6 - (OFFSET, MASK, VALUE) (0XFD080A18, 0xFFFFFFFFU ,0x09092B2BU) - RegMask = (DDR_PHY_DX3GCR6_RESERVED_31_30_MASK | DDR_PHY_DX3GCR6_DXDQVREFR3_MASK | DDR_PHY_DX3GCR6_RESERVED_23_22_MASK | DDR_PHY_DX3GCR6_DXDQVREFR2_MASK | DDR_PHY_DX3GCR6_RESERVED_15_14_MASK | DDR_PHY_DX3GCR6_DXDQVREFR1_MASK | DDR_PHY_DX3GCR6_RESERVED_7_6_MASK | DDR_PHY_DX3GCR6_DXDQVREFR0_MASK | 0 ); + * DATX8 n General Configuration Register 6 + * (OFFSET, MASK, VALUE) (0XFD080B18, 0xFFFFFFFFU ,0x09092B2BU) + */ + PSU_Mask_Write(DDR_PHY_DX4GCR6_OFFSET, 0xFFFFFFFFU, 0x09092B2BU); +/*##################################################################### */ - RegVal = ((0x00000000U << DDR_PHY_DX3GCR6_RESERVED_31_30_SHIFT - | 0x00000009U << DDR_PHY_DX3GCR6_DXDQVREFR3_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR6_RESERVED_23_22_SHIFT - | 0x00000009U << DDR_PHY_DX3GCR6_DXDQVREFR2_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR6_RESERVED_15_14_SHIFT - | 0x0000002BU << DDR_PHY_DX3GCR6_DXDQVREFR1_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR6_RESERVED_7_6_SHIFT - | 0x0000002BU << DDR_PHY_DX3GCR6_DXDQVREFR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX3GCR6_OFFSET ,0xFFFFFFFFU ,0x09092B2BU); - /*############################################################################################################################ */ + /* + * Register : DX5GCR0 @ 0XFD080C00 - /*Register : DX3LCDLR2 @ 0XFD080A88

+ * Calibration Bypass + * PSU_DDR_PHY_DX5GCR0_CALBYP 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX3LCDLR2_RESERVED_31_25 0x0 + * Master Delay Line Enable + * PSU_DDR_PHY_DX5GCR0_MDLEN 0x1 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX3LCDLR2_RESERVED_24_16 0x0 + * Configurable ODT(TE) Phase Shift + * PSU_DDR_PHY_DX5GCR0_CODTSHFT 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX3LCDLR2_RESERVED_15_9 0x0 + * DQS Duty Cycle Correction + * PSU_DDR_PHY_DX5GCR0_DQSDCC 0x0 - Read DQS Gating Delay - PSU_DDR_PHY_DX3LCDLR2_DQSGD 0x0 + * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY + * PSU_DDR_PHY_DX5GCR0_RDDLY 0x8 - DATX8 n Local Calibrated Delay Line Register 2 - (OFFSET, MASK, VALUE) (0XFD080A88, 0xFFFFFFFFU ,0x00000000U) - RegMask = (DDR_PHY_DX3LCDLR2_RESERVED_31_25_MASK | DDR_PHY_DX3LCDLR2_RESERVED_24_16_MASK | DDR_PHY_DX3LCDLR2_RESERVED_15_9_MASK | DDR_PHY_DX3LCDLR2_DQSGD_MASK | 0 ); + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX5GCR0_RESERVED_19_14 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX3LCDLR2_RESERVED_31_25_SHIFT - | 0x00000000U << DDR_PHY_DX3LCDLR2_RESERVED_24_16_SHIFT - | 0x00000000U << DDR_PHY_DX3LCDLR2_RESERVED_15_9_SHIFT - | 0x00000000U << DDR_PHY_DX3LCDLR2_DQSGD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX3LCDLR2_OFFSET ,0xFFFFFFFFU ,0x00000000U); - /*############################################################################################################################ */ + * DQSNSE Power Down Receiver + * PSU_DDR_PHY_DX5GCR0_DQSNSEPDR 0x0 - /*Register : DX3GTR0 @ 0XFD080AC0

+ * DQSSE Power Down Receiver + * PSU_DDR_PHY_DX5GCR0_DQSSEPDR 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX3GTR0_RESERVED_31_24 0x0 + * RTT On Additive Latency + * PSU_DDR_PHY_DX5GCR0_RTTOAL 0x0 - DQ Write Path Latency Pipeline - PSU_DDR_PHY_DX3GTR0_WDQSL 0x0 + * RTT Output Hold + * PSU_DDR_PHY_DX5GCR0_RTTOH 0x3 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX3GTR0_RESERVED_23_20 0x0 + * Configurable PDR Phase Shift + * PSU_DDR_PHY_DX5GCR0_CPDRSHFT 0x0 - Write Leveling System Latency - PSU_DDR_PHY_DX3GTR0_WLSL 0x2 + * DQSR Power Down + * PSU_DDR_PHY_DX5GCR0_DQSRPD 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX3GTR0_RESERVED_15_13 0x0 + * DQSG Power Down Receiver + * PSU_DDR_PHY_DX5GCR0_DQSGPDR 0x0 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX3GTR0_RESERVED_12_8 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX5GCR0_RESERVED_4 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX3GTR0_RESERVED_7_5 0x0 + * DQSG On-Die Termination + * PSU_DDR_PHY_DX5GCR0_DQSGODT 0x0 - DQS Gating System Latency - PSU_DDR_PHY_DX3GTR0_DGSL 0x0 + * DQSG Output Enable + * PSU_DDR_PHY_DX5GCR0_DQSGOE 0x1 - DATX8 n General Timing Register 0 - (OFFSET, MASK, VALUE) (0XFD080AC0, 0xFFFFFFFFU ,0x00020000U) - RegMask = (DDR_PHY_DX3GTR0_RESERVED_31_24_MASK | DDR_PHY_DX3GTR0_WDQSL_MASK | DDR_PHY_DX3GTR0_RESERVED_23_20_MASK | DDR_PHY_DX3GTR0_WLSL_MASK | DDR_PHY_DX3GTR0_RESERVED_15_13_MASK | DDR_PHY_DX3GTR0_RESERVED_12_8_MASK | DDR_PHY_DX3GTR0_RESERVED_7_5_MASK | DDR_PHY_DX3GTR0_DGSL_MASK | 0 ); + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX5GCR0_RESERVED_1_0 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX3GTR0_RESERVED_31_24_SHIFT - | 0x00000000U << DDR_PHY_DX3GTR0_WDQSL_SHIFT - | 0x00000000U << DDR_PHY_DX3GTR0_RESERVED_23_20_SHIFT - | 0x00000002U << DDR_PHY_DX3GTR0_WLSL_SHIFT - | 0x00000000U << DDR_PHY_DX3GTR0_RESERVED_15_13_SHIFT - | 0x00000000U << DDR_PHY_DX3GTR0_RESERVED_12_8_SHIFT - | 0x00000000U << DDR_PHY_DX3GTR0_RESERVED_7_5_SHIFT - | 0x00000000U << DDR_PHY_DX3GTR0_DGSL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX3GTR0_OFFSET ,0xFFFFFFFFU ,0x00020000U); - /*############################################################################################################################ */ + * DATX8 n General Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD080C00, 0xFFFFFFFFU ,0x40800604U) + */ + PSU_Mask_Write(DDR_PHY_DX5GCR0_OFFSET, 0xFFFFFFFFU, 0x40800604U); +/*##################################################################### */ - /*Register : DX4GCR0 @ 0XFD080B00

+ /* + * Register : DX5GCR1 @ 0XFD080C04 - Calibration Bypass - PSU_DDR_PHY_DX4GCR0_CALBYP 0x0 + * Enables the PDR mode for DQ[7:0] + * PSU_DDR_PHY_DX5GCR1_DXPDRMODE 0x0 - Master Delay Line Enable - PSU_DDR_PHY_DX4GCR0_MDLEN 0x1 + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX5GCR1_RESERVED_15 0x0 - Configurable ODT(TE) Phase Shift - PSU_DDR_PHY_DX4GCR0_CODTSHFT 0x0 + * Select the delayed or non-delayed read data strobe # + * PSU_DDR_PHY_DX5GCR1_QSNSEL 0x1 - DQS Duty Cycle Correction - PSU_DDR_PHY_DX4GCR0_DQSDCC 0x0 + * Select the delayed or non-delayed read data strobe + * PSU_DDR_PHY_DX5GCR1_QSSEL 0x1 - Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY - PSU_DDR_PHY_DX4GCR0_RDDLY 0x8 + * Enables Read Data Strobe in a byte lane + * PSU_DDR_PHY_DX5GCR1_OEEN 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX4GCR0_RESERVED_19_14 0x0 + * Enables PDR in a byte lane + * PSU_DDR_PHY_DX5GCR1_PDREN 0x1 - DQSNSE Power Down Receiver - PSU_DDR_PHY_DX4GCR0_DQSNSEPDR 0x0 + * Enables ODT/TE in a byte lane + * PSU_DDR_PHY_DX5GCR1_TEEN 0x1 - DQSSE Power Down Receiver - PSU_DDR_PHY_DX4GCR0_DQSSEPDR 0x0 + * Enables Write Data strobe in a byte lane + * PSU_DDR_PHY_DX5GCR1_DSEN 0x1 - RTT On Additive Latency - PSU_DDR_PHY_DX4GCR0_RTTOAL 0x0 + * Enables DM pin in a byte lane + * PSU_DDR_PHY_DX5GCR1_DMEN 0x1 - RTT Output Hold - PSU_DDR_PHY_DX4GCR0_RTTOH 0x3 + * Enables DQ corresponding to each bit in a byte + * PSU_DDR_PHY_DX5GCR1_DQEN 0xff - Configurable PDR Phase Shift - PSU_DDR_PHY_DX4GCR0_CPDRSHFT 0x0 + * DATX8 n General Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD080C04, 0xFFFFFFFFU ,0x00007FFFU) + */ + PSU_Mask_Write(DDR_PHY_DX5GCR1_OFFSET, 0xFFFFFFFFU, 0x00007FFFU); +/*##################################################################### */ - DQSR Power Down - PSU_DDR_PHY_DX4GCR0_DQSRPD 0x0 + /* + * Register : DX5GCR4 @ 0XFD080C10 - DQSG Power Down Receiver - PSU_DDR_PHY_DX4GCR0_DQSGPDR 0x0 + * Byte lane VREF IOM (Used only by D4MU IOs) + * PSU_DDR_PHY_DX5GCR4_RESERVED_31_29 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX4GCR0_RESERVED_4 0x0 + * Byte Lane VREF Pad Enable + * PSU_DDR_PHY_DX5GCR4_DXREFPEN 0x0 - DQSG On-Die Termination - PSU_DDR_PHY_DX4GCR0_DQSGODT 0x0 + * Byte Lane Internal VREF Enable + * PSU_DDR_PHY_DX5GCR4_DXREFEEN 0x3 - DQSG Output Enable - PSU_DDR_PHY_DX4GCR0_DQSGOE 0x1 + * Byte Lane Single-End VREF Enable + * PSU_DDR_PHY_DX5GCR4_DXREFSEN 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX4GCR0_RESERVED_1_0 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX5GCR4_RESERVED_24 0x0 - DATX8 n General Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD080B00, 0xFFFFFFFFU ,0x40800604U) - RegMask = (DDR_PHY_DX4GCR0_CALBYP_MASK | DDR_PHY_DX4GCR0_MDLEN_MASK | DDR_PHY_DX4GCR0_CODTSHFT_MASK | DDR_PHY_DX4GCR0_DQSDCC_MASK | DDR_PHY_DX4GCR0_RDDLY_MASK | DDR_PHY_DX4GCR0_RESERVED_19_14_MASK | DDR_PHY_DX4GCR0_DQSNSEPDR_MASK | DDR_PHY_DX4GCR0_DQSSEPDR_MASK | DDR_PHY_DX4GCR0_RTTOAL_MASK | DDR_PHY_DX4GCR0_RTTOH_MASK | DDR_PHY_DX4GCR0_CPDRSHFT_MASK | DDR_PHY_DX4GCR0_DQSRPD_MASK | DDR_PHY_DX4GCR0_DQSGPDR_MASK | DDR_PHY_DX4GCR0_RESERVED_4_MASK | DDR_PHY_DX4GCR0_DQSGODT_MASK | DDR_PHY_DX4GCR0_DQSGOE_MASK | DDR_PHY_DX4GCR0_RESERVED_1_0_MASK | 0 ); + * External VREF generator REFSEL range select + * PSU_DDR_PHY_DX5GCR4_DXREFESELRANGE 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX4GCR0_CALBYP_SHIFT - | 0x00000001U << DDR_PHY_DX4GCR0_MDLEN_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR0_CODTSHFT_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR0_DQSDCC_SHIFT - | 0x00000008U << DDR_PHY_DX4GCR0_RDDLY_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR0_RESERVED_19_14_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR0_DQSNSEPDR_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR0_DQSSEPDR_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR0_RTTOAL_SHIFT - | 0x00000003U << DDR_PHY_DX4GCR0_RTTOH_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR0_CPDRSHFT_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR0_DQSRPD_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR0_DQSGPDR_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR0_RESERVED_4_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR0_DQSGODT_SHIFT - | 0x00000001U << DDR_PHY_DX4GCR0_DQSGOE_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR0_RESERVED_1_0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX4GCR0_OFFSET ,0xFFFFFFFFU ,0x40800604U); - /*############################################################################################################################ */ + * Byte Lane External VREF Select + * PSU_DDR_PHY_DX5GCR4_DXREFESEL 0x0 - /*Register : DX4GCR1 @ 0XFD080B04

+ * Single ended VREF generator REFSEL range select + * PSU_DDR_PHY_DX5GCR4_DXREFSSELRANGE 0x1 - Enables the PDR mode for DQ[7:0] - PSU_DDR_PHY_DX4GCR1_DXPDRMODE 0x0 + * Byte Lane Single-End VREF Select + * PSU_DDR_PHY_DX5GCR4_DXREFSSEL 0x30 - Reserved. Returns zeroes on reads. - PSU_DDR_PHY_DX4GCR1_RESERVED_15 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX5GCR4_RESERVED_7_6 0x0 - Select the delayed or non-delayed read data strobe # - PSU_DDR_PHY_DX4GCR1_QSNSEL 0x1 + * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX5GCR4_DXREFIEN 0xf - Select the delayed or non-delayed read data strobe - PSU_DDR_PHY_DX4GCR1_QSSEL 0x1 + * VRMON control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX5GCR4_DXREFIMON 0x0 - Enables Read Data Strobe in a byte lane - PSU_DDR_PHY_DX4GCR1_OEEN 0x1 + * DATX8 n General Configuration Register 4 + * (OFFSET, MASK, VALUE) (0XFD080C10, 0xFFFFFFFFU ,0x0E00B03CU) + */ + PSU_Mask_Write(DDR_PHY_DX5GCR4_OFFSET, 0xFFFFFFFFU, 0x0E00B03CU); +/*##################################################################### */ - Enables PDR in a byte lane - PSU_DDR_PHY_DX4GCR1_PDREN 0x1 + /* + * Register : DX5GCR5 @ 0XFD080C14 - Enables ODT/TE in a byte lane - PSU_DDR_PHY_DX4GCR1_TEEN 0x1 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX5GCR5_RESERVED_31 0x0 - Enables Write Data strobe in a byte lane - PSU_DDR_PHY_DX4GCR1_DSEN 0x1 + * Byte Lane internal VREF Select for Rank 3 + * PSU_DDR_PHY_DX5GCR5_DXREFISELR3 0x9 - Enables DM pin in a byte lane - PSU_DDR_PHY_DX4GCR1_DMEN 0x1 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX5GCR5_RESERVED_23 0x0 - Enables DQ corresponding to each bit in a byte - PSU_DDR_PHY_DX4GCR1_DQEN 0xff + * Byte Lane internal VREF Select for Rank 2 + * PSU_DDR_PHY_DX5GCR5_DXREFISELR2 0x9 - DATX8 n General Configuration Register 1 - (OFFSET, MASK, VALUE) (0XFD080B04, 0xFFFFFFFFU ,0x00007FFFU) - RegMask = (DDR_PHY_DX4GCR1_DXPDRMODE_MASK | DDR_PHY_DX4GCR1_RESERVED_15_MASK | DDR_PHY_DX4GCR1_QSNSEL_MASK | DDR_PHY_DX4GCR1_QSSEL_MASK | DDR_PHY_DX4GCR1_OEEN_MASK | DDR_PHY_DX4GCR1_PDREN_MASK | DDR_PHY_DX4GCR1_TEEN_MASK | DDR_PHY_DX4GCR1_DSEN_MASK | DDR_PHY_DX4GCR1_DMEN_MASK | DDR_PHY_DX4GCR1_DQEN_MASK | 0 ); + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX5GCR5_RESERVED_15 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX4GCR1_DXPDRMODE_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR1_RESERVED_15_SHIFT - | 0x00000001U << DDR_PHY_DX4GCR1_QSNSEL_SHIFT - | 0x00000001U << DDR_PHY_DX4GCR1_QSSEL_SHIFT - | 0x00000001U << DDR_PHY_DX4GCR1_OEEN_SHIFT - | 0x00000001U << DDR_PHY_DX4GCR1_PDREN_SHIFT - | 0x00000001U << DDR_PHY_DX4GCR1_TEEN_SHIFT - | 0x00000001U << DDR_PHY_DX4GCR1_DSEN_SHIFT - | 0x00000001U << DDR_PHY_DX4GCR1_DMEN_SHIFT - | 0x000000FFU << DDR_PHY_DX4GCR1_DQEN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX4GCR1_OFFSET ,0xFFFFFFFFU ,0x00007FFFU); - /*############################################################################################################################ */ + * Byte Lane internal VREF Select for Rank 1 + * PSU_DDR_PHY_DX5GCR5_DXREFISELR1 0x55 - /*Register : DX4GCR4 @ 0XFD080B10

+ * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX5GCR5_RESERVED_7 0x0 - Byte lane VREF IOM (Used only by D4MU IOs) - PSU_DDR_PHY_DX4GCR4_RESERVED_31_29 0x0 + * Byte Lane internal VREF Select for Rank 0 + * PSU_DDR_PHY_DX5GCR5_DXREFISELR0 0x55 - Byte Lane VREF Pad Enable - PSU_DDR_PHY_DX4GCR4_DXREFPEN 0x0 + * DATX8 n General Configuration Register 5 + * (OFFSET, MASK, VALUE) (0XFD080C14, 0xFFFFFFFFU ,0x09095555U) + */ + PSU_Mask_Write(DDR_PHY_DX5GCR5_OFFSET, 0xFFFFFFFFU, 0x09095555U); +/*##################################################################### */ - Byte Lane Internal VREF Enable - PSU_DDR_PHY_DX4GCR4_DXREFEEN 0x3 + /* + * Register : DX5GCR6 @ 0XFD080C18 - Byte Lane Single-End VREF Enable - PSU_DDR_PHY_DX4GCR4_DXREFSEN 0x1 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX5GCR6_RESERVED_31_30 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX4GCR4_RESERVED_24 0x0 + * DRAM DQ VREF Select for Rank3 + * PSU_DDR_PHY_DX5GCR6_DXDQVREFR3 0x9 - External VREF generator REFSEL range select - PSU_DDR_PHY_DX4GCR4_DXREFESELRANGE 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX5GCR6_RESERVED_23_22 0x0 - Byte Lane External VREF Select - PSU_DDR_PHY_DX4GCR4_DXREFESEL 0x0 + * DRAM DQ VREF Select for Rank2 + * PSU_DDR_PHY_DX5GCR6_DXDQVREFR2 0x9 - Single ended VREF generator REFSEL range select - PSU_DDR_PHY_DX4GCR4_DXREFSSELRANGE 0x1 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX5GCR6_RESERVED_15_14 0x0 - Byte Lane Single-End VREF Select - PSU_DDR_PHY_DX4GCR4_DXREFSSEL 0x30 + * DRAM DQ VREF Select for Rank1 + * PSU_DDR_PHY_DX5GCR6_DXDQVREFR1 0x2b - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX4GCR4_RESERVED_7_6 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX5GCR6_RESERVED_7_6 0x0 - VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. - PSU_DDR_PHY_DX4GCR4_DXREFIEN 0xf + * DRAM DQ VREF Select for Rank0 + * PSU_DDR_PHY_DX5GCR6_DXDQVREFR0 0x2b - VRMON control for DQ IO (Single Ended) buffers of a byte lane. - PSU_DDR_PHY_DX4GCR4_DXREFIMON 0x0 + * DATX8 n General Configuration Register 6 + * (OFFSET, MASK, VALUE) (0XFD080C18, 0xFFFFFFFFU ,0x09092B2BU) + */ + PSU_Mask_Write(DDR_PHY_DX5GCR6_OFFSET, 0xFFFFFFFFU, 0x09092B2BU); +/*##################################################################### */ - DATX8 n General Configuration Register 4 - (OFFSET, MASK, VALUE) (0XFD080B10, 0xFFFFFFFFU ,0x0E00B03CU) - RegMask = (DDR_PHY_DX4GCR4_RESERVED_31_29_MASK | DDR_PHY_DX4GCR4_DXREFPEN_MASK | DDR_PHY_DX4GCR4_DXREFEEN_MASK | DDR_PHY_DX4GCR4_DXREFSEN_MASK | DDR_PHY_DX4GCR4_RESERVED_24_MASK | DDR_PHY_DX4GCR4_DXREFESELRANGE_MASK | DDR_PHY_DX4GCR4_DXREFESEL_MASK | DDR_PHY_DX4GCR4_DXREFSSELRANGE_MASK | DDR_PHY_DX4GCR4_DXREFSSEL_MASK | DDR_PHY_DX4GCR4_RESERVED_7_6_MASK | DDR_PHY_DX4GCR4_DXREFIEN_MASK | DDR_PHY_DX4GCR4_DXREFIMON_MASK | 0 ); + /* + * Register : DX6GCR0 @ 0XFD080D00 - RegVal = ((0x00000000U << DDR_PHY_DX4GCR4_RESERVED_31_29_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR4_DXREFPEN_SHIFT - | 0x00000003U << DDR_PHY_DX4GCR4_DXREFEEN_SHIFT - | 0x00000001U << DDR_PHY_DX4GCR4_DXREFSEN_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR4_RESERVED_24_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR4_DXREFESELRANGE_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR4_DXREFESEL_SHIFT - | 0x00000001U << DDR_PHY_DX4GCR4_DXREFSSELRANGE_SHIFT - | 0x00000030U << DDR_PHY_DX4GCR4_DXREFSSEL_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR4_RESERVED_7_6_SHIFT - | 0x0000000FU << DDR_PHY_DX4GCR4_DXREFIEN_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR4_DXREFIMON_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX4GCR4_OFFSET ,0xFFFFFFFFU ,0x0E00B03CU); - /*############################################################################################################################ */ + * Calibration Bypass + * PSU_DDR_PHY_DX6GCR0_CALBYP 0x0 - /*Register : DX4GCR5 @ 0XFD080B14

+ * Master Delay Line Enable + * PSU_DDR_PHY_DX6GCR0_MDLEN 0x1 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX4GCR5_RESERVED_31 0x0 + * Configurable ODT(TE) Phase Shift + * PSU_DDR_PHY_DX6GCR0_CODTSHFT 0x0 - Byte Lane internal VREF Select for Rank 3 - PSU_DDR_PHY_DX4GCR5_DXREFISELR3 0x9 + * DQS Duty Cycle Correction + * PSU_DDR_PHY_DX6GCR0_DQSDCC 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX4GCR5_RESERVED_23 0x0 + * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY + * PSU_DDR_PHY_DX6GCR0_RDDLY 0x8 - Byte Lane internal VREF Select for Rank 2 - PSU_DDR_PHY_DX4GCR5_DXREFISELR2 0x9 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX6GCR0_RESERVED_19_14 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX4GCR5_RESERVED_15 0x0 + * DQSNSE Power Down Receiver + * PSU_DDR_PHY_DX6GCR0_DQSNSEPDR 0x0 - Byte Lane internal VREF Select for Rank 1 - PSU_DDR_PHY_DX4GCR5_DXREFISELR1 0x4f + * DQSSE Power Down Receiver + * PSU_DDR_PHY_DX6GCR0_DQSSEPDR 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX4GCR5_RESERVED_7 0x0 + * RTT On Additive Latency + * PSU_DDR_PHY_DX6GCR0_RTTOAL 0x0 - Byte Lane internal VREF Select for Rank 0 - PSU_DDR_PHY_DX4GCR5_DXREFISELR0 0x4f + * RTT Output Hold + * PSU_DDR_PHY_DX6GCR0_RTTOH 0x3 - DATX8 n General Configuration Register 5 - (OFFSET, MASK, VALUE) (0XFD080B14, 0xFFFFFFFFU ,0x09094F4FU) - RegMask = (DDR_PHY_DX4GCR5_RESERVED_31_MASK | DDR_PHY_DX4GCR5_DXREFISELR3_MASK | DDR_PHY_DX4GCR5_RESERVED_23_MASK | DDR_PHY_DX4GCR5_DXREFISELR2_MASK | DDR_PHY_DX4GCR5_RESERVED_15_MASK | DDR_PHY_DX4GCR5_DXREFISELR1_MASK | DDR_PHY_DX4GCR5_RESERVED_7_MASK | DDR_PHY_DX4GCR5_DXREFISELR0_MASK | 0 ); + * Configurable PDR Phase Shift + * PSU_DDR_PHY_DX6GCR0_CPDRSHFT 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX4GCR5_RESERVED_31_SHIFT - | 0x00000009U << DDR_PHY_DX4GCR5_DXREFISELR3_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR5_RESERVED_23_SHIFT - | 0x00000009U << DDR_PHY_DX4GCR5_DXREFISELR2_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR5_RESERVED_15_SHIFT - | 0x0000004FU << DDR_PHY_DX4GCR5_DXREFISELR1_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR5_RESERVED_7_SHIFT - | 0x0000004FU << DDR_PHY_DX4GCR5_DXREFISELR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX4GCR5_OFFSET ,0xFFFFFFFFU ,0x09094F4FU); - /*############################################################################################################################ */ + * DQSR Power Down + * PSU_DDR_PHY_DX6GCR0_DQSRPD 0x0 - /*Register : DX4GCR6 @ 0XFD080B18

+ * DQSG Power Down Receiver + * PSU_DDR_PHY_DX6GCR0_DQSGPDR 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX4GCR6_RESERVED_31_30 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX6GCR0_RESERVED_4 0x0 - DRAM DQ VREF Select for Rank3 - PSU_DDR_PHY_DX4GCR6_DXDQVREFR3 0x9 + * DQSG On-Die Termination + * PSU_DDR_PHY_DX6GCR0_DQSGODT 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX4GCR6_RESERVED_23_22 0x0 + * DQSG Output Enable + * PSU_DDR_PHY_DX6GCR0_DQSGOE 0x1 - DRAM DQ VREF Select for Rank2 - PSU_DDR_PHY_DX4GCR6_DXDQVREFR2 0x9 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX6GCR0_RESERVED_1_0 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX4GCR6_RESERVED_15_14 0x0 + * DATX8 n General Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD080D00, 0xFFFFFFFFU ,0x40800604U) + */ + PSU_Mask_Write(DDR_PHY_DX6GCR0_OFFSET, 0xFFFFFFFFU, 0x40800604U); +/*##################################################################### */ - DRAM DQ VREF Select for Rank1 - PSU_DDR_PHY_DX4GCR6_DXDQVREFR1 0x2b + /* + * Register : DX6GCR1 @ 0XFD080D04 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX4GCR6_RESERVED_7_6 0x0 + * Enables the PDR mode for DQ[7:0] + * PSU_DDR_PHY_DX6GCR1_DXPDRMODE 0x0 - DRAM DQ VREF Select for Rank0 - PSU_DDR_PHY_DX4GCR6_DXDQVREFR0 0x2b + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX6GCR1_RESERVED_15 0x0 - DATX8 n General Configuration Register 6 - (OFFSET, MASK, VALUE) (0XFD080B18, 0xFFFFFFFFU ,0x09092B2BU) - RegMask = (DDR_PHY_DX4GCR6_RESERVED_31_30_MASK | DDR_PHY_DX4GCR6_DXDQVREFR3_MASK | DDR_PHY_DX4GCR6_RESERVED_23_22_MASK | DDR_PHY_DX4GCR6_DXDQVREFR2_MASK | DDR_PHY_DX4GCR6_RESERVED_15_14_MASK | DDR_PHY_DX4GCR6_DXDQVREFR1_MASK | DDR_PHY_DX4GCR6_RESERVED_7_6_MASK | DDR_PHY_DX4GCR6_DXDQVREFR0_MASK | 0 ); + * Select the delayed or non-delayed read data strobe # + * PSU_DDR_PHY_DX6GCR1_QSNSEL 0x1 - RegVal = ((0x00000000U << DDR_PHY_DX4GCR6_RESERVED_31_30_SHIFT - | 0x00000009U << DDR_PHY_DX4GCR6_DXDQVREFR3_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR6_RESERVED_23_22_SHIFT - | 0x00000009U << DDR_PHY_DX4GCR6_DXDQVREFR2_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR6_RESERVED_15_14_SHIFT - | 0x0000002BU << DDR_PHY_DX4GCR6_DXDQVREFR1_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR6_RESERVED_7_6_SHIFT - | 0x0000002BU << DDR_PHY_DX4GCR6_DXDQVREFR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX4GCR6_OFFSET ,0xFFFFFFFFU ,0x09092B2BU); - /*############################################################################################################################ */ + * Select the delayed or non-delayed read data strobe + * PSU_DDR_PHY_DX6GCR1_QSSEL 0x1 - /*Register : DX4LCDLR2 @ 0XFD080B88

+ * Enables Read Data Strobe in a byte lane + * PSU_DDR_PHY_DX6GCR1_OEEN 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX4LCDLR2_RESERVED_31_25 0x0 + * Enables PDR in a byte lane + * PSU_DDR_PHY_DX6GCR1_PDREN 0x1 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX4LCDLR2_RESERVED_24_16 0x0 + * Enables ODT/TE in a byte lane + * PSU_DDR_PHY_DX6GCR1_TEEN 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX4LCDLR2_RESERVED_15_9 0x0 + * Enables Write Data strobe in a byte lane + * PSU_DDR_PHY_DX6GCR1_DSEN 0x1 - Read DQS Gating Delay - PSU_DDR_PHY_DX4LCDLR2_DQSGD 0x0 + * Enables DM pin in a byte lane + * PSU_DDR_PHY_DX6GCR1_DMEN 0x1 - DATX8 n Local Calibrated Delay Line Register 2 - (OFFSET, MASK, VALUE) (0XFD080B88, 0xFFFFFFFFU ,0x00000000U) - RegMask = (DDR_PHY_DX4LCDLR2_RESERVED_31_25_MASK | DDR_PHY_DX4LCDLR2_RESERVED_24_16_MASK | DDR_PHY_DX4LCDLR2_RESERVED_15_9_MASK | DDR_PHY_DX4LCDLR2_DQSGD_MASK | 0 ); + * Enables DQ corresponding to each bit in a byte + * PSU_DDR_PHY_DX6GCR1_DQEN 0xff - RegVal = ((0x00000000U << DDR_PHY_DX4LCDLR2_RESERVED_31_25_SHIFT - | 0x00000000U << DDR_PHY_DX4LCDLR2_RESERVED_24_16_SHIFT - | 0x00000000U << DDR_PHY_DX4LCDLR2_RESERVED_15_9_SHIFT - | 0x00000000U << DDR_PHY_DX4LCDLR2_DQSGD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX4LCDLR2_OFFSET ,0xFFFFFFFFU ,0x00000000U); - /*############################################################################################################################ */ + * DATX8 n General Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD080D04, 0xFFFFFFFFU ,0x00007FFFU) + */ + PSU_Mask_Write(DDR_PHY_DX6GCR1_OFFSET, 0xFFFFFFFFU, 0x00007FFFU); +/*##################################################################### */ - /*Register : DX4GTR0 @ 0XFD080BC0

+ /* + * Register : DX6GCR4 @ 0XFD080D10 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX4GTR0_RESERVED_31_24 0x0 + * Byte lane VREF IOM (Used only by D4MU IOs) + * PSU_DDR_PHY_DX6GCR4_RESERVED_31_29 0x0 - DQ Write Path Latency Pipeline - PSU_DDR_PHY_DX4GTR0_WDQSL 0x0 + * Byte Lane VREF Pad Enable + * PSU_DDR_PHY_DX6GCR4_DXREFPEN 0x0 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX4GTR0_RESERVED_23_20 0x0 + * Byte Lane Internal VREF Enable + * PSU_DDR_PHY_DX6GCR4_DXREFEEN 0x3 - Write Leveling System Latency - PSU_DDR_PHY_DX4GTR0_WLSL 0x2 + * Byte Lane Single-End VREF Enable + * PSU_DDR_PHY_DX6GCR4_DXREFSEN 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX4GTR0_RESERVED_15_13 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX6GCR4_RESERVED_24 0x0 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX4GTR0_RESERVED_12_8 0x0 + * External VREF generator REFSEL range select + * PSU_DDR_PHY_DX6GCR4_DXREFESELRANGE 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX4GTR0_RESERVED_7_5 0x0 + * Byte Lane External VREF Select + * PSU_DDR_PHY_DX6GCR4_DXREFESEL 0x0 - DQS Gating System Latency - PSU_DDR_PHY_DX4GTR0_DGSL 0x0 + * Single ended VREF generator REFSEL range select + * PSU_DDR_PHY_DX6GCR4_DXREFSSELRANGE 0x1 - DATX8 n General Timing Register 0 - (OFFSET, MASK, VALUE) (0XFD080BC0, 0xFFFFFFFFU ,0x00020000U) - RegMask = (DDR_PHY_DX4GTR0_RESERVED_31_24_MASK | DDR_PHY_DX4GTR0_WDQSL_MASK | DDR_PHY_DX4GTR0_RESERVED_23_20_MASK | DDR_PHY_DX4GTR0_WLSL_MASK | DDR_PHY_DX4GTR0_RESERVED_15_13_MASK | DDR_PHY_DX4GTR0_RESERVED_12_8_MASK | DDR_PHY_DX4GTR0_RESERVED_7_5_MASK | DDR_PHY_DX4GTR0_DGSL_MASK | 0 ); + * Byte Lane Single-End VREF Select + * PSU_DDR_PHY_DX6GCR4_DXREFSSEL 0x30 - RegVal = ((0x00000000U << DDR_PHY_DX4GTR0_RESERVED_31_24_SHIFT - | 0x00000000U << DDR_PHY_DX4GTR0_WDQSL_SHIFT - | 0x00000000U << DDR_PHY_DX4GTR0_RESERVED_23_20_SHIFT - | 0x00000002U << DDR_PHY_DX4GTR0_WLSL_SHIFT - | 0x00000000U << DDR_PHY_DX4GTR0_RESERVED_15_13_SHIFT - | 0x00000000U << DDR_PHY_DX4GTR0_RESERVED_12_8_SHIFT - | 0x00000000U << DDR_PHY_DX4GTR0_RESERVED_7_5_SHIFT - | 0x00000000U << DDR_PHY_DX4GTR0_DGSL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX4GTR0_OFFSET ,0xFFFFFFFFU ,0x00020000U); - /*############################################################################################################################ */ + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX6GCR4_RESERVED_7_6 0x0 - /*Register : DX5GCR0 @ 0XFD080C00

+ * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX6GCR4_DXREFIEN 0xf - Calibration Bypass - PSU_DDR_PHY_DX5GCR0_CALBYP 0x0 + * VRMON control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX6GCR4_DXREFIMON 0x0 - Master Delay Line Enable - PSU_DDR_PHY_DX5GCR0_MDLEN 0x1 + * DATX8 n General Configuration Register 4 + * (OFFSET, MASK, VALUE) (0XFD080D10, 0xFFFFFFFFU ,0x0E00B03CU) + */ + PSU_Mask_Write(DDR_PHY_DX6GCR4_OFFSET, 0xFFFFFFFFU, 0x0E00B03CU); +/*##################################################################### */ - Configurable ODT(TE) Phase Shift - PSU_DDR_PHY_DX5GCR0_CODTSHFT 0x0 + /* + * Register : DX6GCR5 @ 0XFD080D14 - DQS Duty Cycle Correction - PSU_DDR_PHY_DX5GCR0_DQSDCC 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX6GCR5_RESERVED_31 0x0 - Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY - PSU_DDR_PHY_DX5GCR0_RDDLY 0x8 + * Byte Lane internal VREF Select for Rank 3 + * PSU_DDR_PHY_DX6GCR5_DXREFISELR3 0x9 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX5GCR0_RESERVED_19_14 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX6GCR5_RESERVED_23 0x0 - DQSNSE Power Down Receiver - PSU_DDR_PHY_DX5GCR0_DQSNSEPDR 0x0 + * Byte Lane internal VREF Select for Rank 2 + * PSU_DDR_PHY_DX6GCR5_DXREFISELR2 0x9 - DQSSE Power Down Receiver - PSU_DDR_PHY_DX5GCR0_DQSSEPDR 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX6GCR5_RESERVED_15 0x0 - RTT On Additive Latency - PSU_DDR_PHY_DX5GCR0_RTTOAL 0x0 + * Byte Lane internal VREF Select for Rank 1 + * PSU_DDR_PHY_DX6GCR5_DXREFISELR1 0x55 - RTT Output Hold - PSU_DDR_PHY_DX5GCR0_RTTOH 0x3 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX6GCR5_RESERVED_7 0x0 - Configurable PDR Phase Shift - PSU_DDR_PHY_DX5GCR0_CPDRSHFT 0x0 + * Byte Lane internal VREF Select for Rank 0 + * PSU_DDR_PHY_DX6GCR5_DXREFISELR0 0x55 - DQSR Power Down - PSU_DDR_PHY_DX5GCR0_DQSRPD 0x0 + * DATX8 n General Configuration Register 5 + * (OFFSET, MASK, VALUE) (0XFD080D14, 0xFFFFFFFFU ,0x09095555U) + */ + PSU_Mask_Write(DDR_PHY_DX6GCR5_OFFSET, 0xFFFFFFFFU, 0x09095555U); +/*##################################################################### */ - DQSG Power Down Receiver - PSU_DDR_PHY_DX5GCR0_DQSGPDR 0x0 + /* + * Register : DX6GCR6 @ 0XFD080D18 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX5GCR0_RESERVED_4 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX6GCR6_RESERVED_31_30 0x0 - DQSG On-Die Termination - PSU_DDR_PHY_DX5GCR0_DQSGODT 0x0 + * DRAM DQ VREF Select for Rank3 + * PSU_DDR_PHY_DX6GCR6_DXDQVREFR3 0x9 - DQSG Output Enable - PSU_DDR_PHY_DX5GCR0_DQSGOE 0x1 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX6GCR6_RESERVED_23_22 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX5GCR0_RESERVED_1_0 0x0 + * DRAM DQ VREF Select for Rank2 + * PSU_DDR_PHY_DX6GCR6_DXDQVREFR2 0x9 - DATX8 n General Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD080C00, 0xFFFFFFFFU ,0x40800604U) - RegMask = (DDR_PHY_DX5GCR0_CALBYP_MASK | DDR_PHY_DX5GCR0_MDLEN_MASK | DDR_PHY_DX5GCR0_CODTSHFT_MASK | DDR_PHY_DX5GCR0_DQSDCC_MASK | DDR_PHY_DX5GCR0_RDDLY_MASK | DDR_PHY_DX5GCR0_RESERVED_19_14_MASK | DDR_PHY_DX5GCR0_DQSNSEPDR_MASK | DDR_PHY_DX5GCR0_DQSSEPDR_MASK | DDR_PHY_DX5GCR0_RTTOAL_MASK | DDR_PHY_DX5GCR0_RTTOH_MASK | DDR_PHY_DX5GCR0_CPDRSHFT_MASK | DDR_PHY_DX5GCR0_DQSRPD_MASK | DDR_PHY_DX5GCR0_DQSGPDR_MASK | DDR_PHY_DX5GCR0_RESERVED_4_MASK | DDR_PHY_DX5GCR0_DQSGODT_MASK | DDR_PHY_DX5GCR0_DQSGOE_MASK | DDR_PHY_DX5GCR0_RESERVED_1_0_MASK | 0 ); + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX6GCR6_RESERVED_15_14 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX5GCR0_CALBYP_SHIFT - | 0x00000001U << DDR_PHY_DX5GCR0_MDLEN_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR0_CODTSHFT_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR0_DQSDCC_SHIFT - | 0x00000008U << DDR_PHY_DX5GCR0_RDDLY_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR0_RESERVED_19_14_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR0_DQSNSEPDR_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR0_DQSSEPDR_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR0_RTTOAL_SHIFT - | 0x00000003U << DDR_PHY_DX5GCR0_RTTOH_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR0_CPDRSHFT_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR0_DQSRPD_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR0_DQSGPDR_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR0_RESERVED_4_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR0_DQSGODT_SHIFT - | 0x00000001U << DDR_PHY_DX5GCR0_DQSGOE_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR0_RESERVED_1_0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX5GCR0_OFFSET ,0xFFFFFFFFU ,0x40800604U); - /*############################################################################################################################ */ + * DRAM DQ VREF Select for Rank1 + * PSU_DDR_PHY_DX6GCR6_DXDQVREFR1 0x2b - /*Register : DX5GCR1 @ 0XFD080C04

+ * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX6GCR6_RESERVED_7_6 0x0 - Enables the PDR mode for DQ[7:0] - PSU_DDR_PHY_DX5GCR1_DXPDRMODE 0x0 + * DRAM DQ VREF Select for Rank0 + * PSU_DDR_PHY_DX6GCR6_DXDQVREFR0 0x2b - Reserved. Returns zeroes on reads. - PSU_DDR_PHY_DX5GCR1_RESERVED_15 0x0 + * DATX8 n General Configuration Register 6 + * (OFFSET, MASK, VALUE) (0XFD080D18, 0xFFFFFFFFU ,0x09092B2BU) + */ + PSU_Mask_Write(DDR_PHY_DX6GCR6_OFFSET, 0xFFFFFFFFU, 0x09092B2BU); +/*##################################################################### */ - Select the delayed or non-delayed read data strobe # - PSU_DDR_PHY_DX5GCR1_QSNSEL 0x1 + /* + * Register : DX7GCR0 @ 0XFD080E00 - Select the delayed or non-delayed read data strobe - PSU_DDR_PHY_DX5GCR1_QSSEL 0x1 + * Calibration Bypass + * PSU_DDR_PHY_DX7GCR0_CALBYP 0x0 - Enables Read Data Strobe in a byte lane - PSU_DDR_PHY_DX5GCR1_OEEN 0x1 + * Master Delay Line Enable + * PSU_DDR_PHY_DX7GCR0_MDLEN 0x1 - Enables PDR in a byte lane - PSU_DDR_PHY_DX5GCR1_PDREN 0x1 + * Configurable ODT(TE) Phase Shift + * PSU_DDR_PHY_DX7GCR0_CODTSHFT 0x0 - Enables ODT/TE in a byte lane - PSU_DDR_PHY_DX5GCR1_TEEN 0x1 + * DQS Duty Cycle Correction + * PSU_DDR_PHY_DX7GCR0_DQSDCC 0x0 - Enables Write Data strobe in a byte lane - PSU_DDR_PHY_DX5GCR1_DSEN 0x1 + * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY + * PSU_DDR_PHY_DX7GCR0_RDDLY 0x8 - Enables DM pin in a byte lane - PSU_DDR_PHY_DX5GCR1_DMEN 0x1 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX7GCR0_RESERVED_19_14 0x0 - Enables DQ corresponding to each bit in a byte - PSU_DDR_PHY_DX5GCR1_DQEN 0xff + * DQSNSE Power Down Receiver + * PSU_DDR_PHY_DX7GCR0_DQSNSEPDR 0x0 - DATX8 n General Configuration Register 1 - (OFFSET, MASK, VALUE) (0XFD080C04, 0xFFFFFFFFU ,0x00007FFFU) - RegMask = (DDR_PHY_DX5GCR1_DXPDRMODE_MASK | DDR_PHY_DX5GCR1_RESERVED_15_MASK | DDR_PHY_DX5GCR1_QSNSEL_MASK | DDR_PHY_DX5GCR1_QSSEL_MASK | DDR_PHY_DX5GCR1_OEEN_MASK | DDR_PHY_DX5GCR1_PDREN_MASK | DDR_PHY_DX5GCR1_TEEN_MASK | DDR_PHY_DX5GCR1_DSEN_MASK | DDR_PHY_DX5GCR1_DMEN_MASK | DDR_PHY_DX5GCR1_DQEN_MASK | 0 ); + * DQSSE Power Down Receiver + * PSU_DDR_PHY_DX7GCR0_DQSSEPDR 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX5GCR1_DXPDRMODE_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR1_RESERVED_15_SHIFT - | 0x00000001U << DDR_PHY_DX5GCR1_QSNSEL_SHIFT - | 0x00000001U << DDR_PHY_DX5GCR1_QSSEL_SHIFT - | 0x00000001U << DDR_PHY_DX5GCR1_OEEN_SHIFT - | 0x00000001U << DDR_PHY_DX5GCR1_PDREN_SHIFT - | 0x00000001U << DDR_PHY_DX5GCR1_TEEN_SHIFT - | 0x00000001U << DDR_PHY_DX5GCR1_DSEN_SHIFT - | 0x00000001U << DDR_PHY_DX5GCR1_DMEN_SHIFT - | 0x000000FFU << DDR_PHY_DX5GCR1_DQEN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX5GCR1_OFFSET ,0xFFFFFFFFU ,0x00007FFFU); - /*############################################################################################################################ */ + * RTT On Additive Latency + * PSU_DDR_PHY_DX7GCR0_RTTOAL 0x0 - /*Register : DX5GCR4 @ 0XFD080C10

+ * RTT Output Hold + * PSU_DDR_PHY_DX7GCR0_RTTOH 0x3 - Byte lane VREF IOM (Used only by D4MU IOs) - PSU_DDR_PHY_DX5GCR4_RESERVED_31_29 0x0 + * Configurable PDR Phase Shift + * PSU_DDR_PHY_DX7GCR0_CPDRSHFT 0x0 - Byte Lane VREF Pad Enable - PSU_DDR_PHY_DX5GCR4_DXREFPEN 0x0 + * DQSR Power Down + * PSU_DDR_PHY_DX7GCR0_DQSRPD 0x0 - Byte Lane Internal VREF Enable - PSU_DDR_PHY_DX5GCR4_DXREFEEN 0x3 + * DQSG Power Down Receiver + * PSU_DDR_PHY_DX7GCR0_DQSGPDR 0x0 - Byte Lane Single-End VREF Enable - PSU_DDR_PHY_DX5GCR4_DXREFSEN 0x1 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX7GCR0_RESERVED_4 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX5GCR4_RESERVED_24 0x0 + * DQSG On-Die Termination + * PSU_DDR_PHY_DX7GCR0_DQSGODT 0x0 - External VREF generator REFSEL range select - PSU_DDR_PHY_DX5GCR4_DXREFESELRANGE 0x0 + * DQSG Output Enable + * PSU_DDR_PHY_DX7GCR0_DQSGOE 0x1 - Byte Lane External VREF Select - PSU_DDR_PHY_DX5GCR4_DXREFESEL 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX7GCR0_RESERVED_1_0 0x0 - Single ended VREF generator REFSEL range select - PSU_DDR_PHY_DX5GCR4_DXREFSSELRANGE 0x1 + * DATX8 n General Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD080E00, 0xFFFFFFFFU ,0x40800604U) + */ + PSU_Mask_Write(DDR_PHY_DX7GCR0_OFFSET, 0xFFFFFFFFU, 0x40800604U); +/*##################################################################### */ - Byte Lane Single-End VREF Select - PSU_DDR_PHY_DX5GCR4_DXREFSSEL 0x30 + /* + * Register : DX7GCR1 @ 0XFD080E04 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX5GCR4_RESERVED_7_6 0x0 + * Enables the PDR mode for DQ[7:0] + * PSU_DDR_PHY_DX7GCR1_DXPDRMODE 0x0 - VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. - PSU_DDR_PHY_DX5GCR4_DXREFIEN 0xf + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX7GCR1_RESERVED_15 0x0 - VRMON control for DQ IO (Single Ended) buffers of a byte lane. - PSU_DDR_PHY_DX5GCR4_DXREFIMON 0x0 + * Select the delayed or non-delayed read data strobe # + * PSU_DDR_PHY_DX7GCR1_QSNSEL 0x1 - DATX8 n General Configuration Register 4 - (OFFSET, MASK, VALUE) (0XFD080C10, 0xFFFFFFFFU ,0x0E00B03CU) - RegMask = (DDR_PHY_DX5GCR4_RESERVED_31_29_MASK | DDR_PHY_DX5GCR4_DXREFPEN_MASK | DDR_PHY_DX5GCR4_DXREFEEN_MASK | DDR_PHY_DX5GCR4_DXREFSEN_MASK | DDR_PHY_DX5GCR4_RESERVED_24_MASK | DDR_PHY_DX5GCR4_DXREFESELRANGE_MASK | DDR_PHY_DX5GCR4_DXREFESEL_MASK | DDR_PHY_DX5GCR4_DXREFSSELRANGE_MASK | DDR_PHY_DX5GCR4_DXREFSSEL_MASK | DDR_PHY_DX5GCR4_RESERVED_7_6_MASK | DDR_PHY_DX5GCR4_DXREFIEN_MASK | DDR_PHY_DX5GCR4_DXREFIMON_MASK | 0 ); + * Select the delayed or non-delayed read data strobe + * PSU_DDR_PHY_DX7GCR1_QSSEL 0x1 - RegVal = ((0x00000000U << DDR_PHY_DX5GCR4_RESERVED_31_29_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR4_DXREFPEN_SHIFT - | 0x00000003U << DDR_PHY_DX5GCR4_DXREFEEN_SHIFT - | 0x00000001U << DDR_PHY_DX5GCR4_DXREFSEN_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR4_RESERVED_24_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR4_DXREFESELRANGE_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR4_DXREFESEL_SHIFT - | 0x00000001U << DDR_PHY_DX5GCR4_DXREFSSELRANGE_SHIFT - | 0x00000030U << DDR_PHY_DX5GCR4_DXREFSSEL_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR4_RESERVED_7_6_SHIFT - | 0x0000000FU << DDR_PHY_DX5GCR4_DXREFIEN_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR4_DXREFIMON_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX5GCR4_OFFSET ,0xFFFFFFFFU ,0x0E00B03CU); - /*############################################################################################################################ */ + * Enables Read Data Strobe in a byte lane + * PSU_DDR_PHY_DX7GCR1_OEEN 0x1 - /*Register : DX5GCR5 @ 0XFD080C14

+ * Enables PDR in a byte lane + * PSU_DDR_PHY_DX7GCR1_PDREN 0x1 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX5GCR5_RESERVED_31 0x0 + * Enables ODT/TE in a byte lane + * PSU_DDR_PHY_DX7GCR1_TEEN 0x1 - Byte Lane internal VREF Select for Rank 3 - PSU_DDR_PHY_DX5GCR5_DXREFISELR3 0x9 + * Enables Write Data strobe in a byte lane + * PSU_DDR_PHY_DX7GCR1_DSEN 0x1 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX5GCR5_RESERVED_23 0x0 + * Enables DM pin in a byte lane + * PSU_DDR_PHY_DX7GCR1_DMEN 0x1 - Byte Lane internal VREF Select for Rank 2 - PSU_DDR_PHY_DX5GCR5_DXREFISELR2 0x9 + * Enables DQ corresponding to each bit in a byte + * PSU_DDR_PHY_DX7GCR1_DQEN 0xff - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX5GCR5_RESERVED_15 0x0 + * DATX8 n General Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD080E04, 0xFFFFFFFFU ,0x00007FFFU) + */ + PSU_Mask_Write(DDR_PHY_DX7GCR1_OFFSET, 0xFFFFFFFFU, 0x00007FFFU); +/*##################################################################### */ - Byte Lane internal VREF Select for Rank 1 - PSU_DDR_PHY_DX5GCR5_DXREFISELR1 0x4f + /* + * Register : DX7GCR4 @ 0XFD080E10 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX5GCR5_RESERVED_7 0x0 + * Byte lane VREF IOM (Used only by D4MU IOs) + * PSU_DDR_PHY_DX7GCR4_RESERVED_31_29 0x0 - Byte Lane internal VREF Select for Rank 0 - PSU_DDR_PHY_DX5GCR5_DXREFISELR0 0x4f + * Byte Lane VREF Pad Enable + * PSU_DDR_PHY_DX7GCR4_DXREFPEN 0x0 - DATX8 n General Configuration Register 5 - (OFFSET, MASK, VALUE) (0XFD080C14, 0xFFFFFFFFU ,0x09094F4FU) - RegMask = (DDR_PHY_DX5GCR5_RESERVED_31_MASK | DDR_PHY_DX5GCR5_DXREFISELR3_MASK | DDR_PHY_DX5GCR5_RESERVED_23_MASK | DDR_PHY_DX5GCR5_DXREFISELR2_MASK | DDR_PHY_DX5GCR5_RESERVED_15_MASK | DDR_PHY_DX5GCR5_DXREFISELR1_MASK | DDR_PHY_DX5GCR5_RESERVED_7_MASK | DDR_PHY_DX5GCR5_DXREFISELR0_MASK | 0 ); + * Byte Lane Internal VREF Enable + * PSU_DDR_PHY_DX7GCR4_DXREFEEN 0x3 - RegVal = ((0x00000000U << DDR_PHY_DX5GCR5_RESERVED_31_SHIFT - | 0x00000009U << DDR_PHY_DX5GCR5_DXREFISELR3_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR5_RESERVED_23_SHIFT - | 0x00000009U << DDR_PHY_DX5GCR5_DXREFISELR2_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR5_RESERVED_15_SHIFT - | 0x0000004FU << DDR_PHY_DX5GCR5_DXREFISELR1_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR5_RESERVED_7_SHIFT - | 0x0000004FU << DDR_PHY_DX5GCR5_DXREFISELR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX5GCR5_OFFSET ,0xFFFFFFFFU ,0x09094F4FU); - /*############################################################################################################################ */ + * Byte Lane Single-End VREF Enable + * PSU_DDR_PHY_DX7GCR4_DXREFSEN 0x1 - /*Register : DX5GCR6 @ 0XFD080C18

+ * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX7GCR4_RESERVED_24 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX5GCR6_RESERVED_31_30 0x0 + * External VREF generator REFSEL range select + * PSU_DDR_PHY_DX7GCR4_DXREFESELRANGE 0x0 - DRAM DQ VREF Select for Rank3 - PSU_DDR_PHY_DX5GCR6_DXDQVREFR3 0x9 + * Byte Lane External VREF Select + * PSU_DDR_PHY_DX7GCR4_DXREFESEL 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX5GCR6_RESERVED_23_22 0x0 + * Single ended VREF generator REFSEL range select + * PSU_DDR_PHY_DX7GCR4_DXREFSSELRANGE 0x1 - DRAM DQ VREF Select for Rank2 - PSU_DDR_PHY_DX5GCR6_DXDQVREFR2 0x9 + * Byte Lane Single-End VREF Select + * PSU_DDR_PHY_DX7GCR4_DXREFSSEL 0x30 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX5GCR6_RESERVED_15_14 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX7GCR4_RESERVED_7_6 0x0 - DRAM DQ VREF Select for Rank1 - PSU_DDR_PHY_DX5GCR6_DXDQVREFR1 0x2b + * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX7GCR4_DXREFIEN 0xf - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX5GCR6_RESERVED_7_6 0x0 + * VRMON control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX7GCR4_DXREFIMON 0x0 - DRAM DQ VREF Select for Rank0 - PSU_DDR_PHY_DX5GCR6_DXDQVREFR0 0x2b + * DATX8 n General Configuration Register 4 + * (OFFSET, MASK, VALUE) (0XFD080E10, 0xFFFFFFFFU ,0x0E00B03CU) + */ + PSU_Mask_Write(DDR_PHY_DX7GCR4_OFFSET, 0xFFFFFFFFU, 0x0E00B03CU); +/*##################################################################### */ - DATX8 n General Configuration Register 6 - (OFFSET, MASK, VALUE) (0XFD080C18, 0xFFFFFFFFU ,0x09092B2BU) - RegMask = (DDR_PHY_DX5GCR6_RESERVED_31_30_MASK | DDR_PHY_DX5GCR6_DXDQVREFR3_MASK | DDR_PHY_DX5GCR6_RESERVED_23_22_MASK | DDR_PHY_DX5GCR6_DXDQVREFR2_MASK | DDR_PHY_DX5GCR6_RESERVED_15_14_MASK | DDR_PHY_DX5GCR6_DXDQVREFR1_MASK | DDR_PHY_DX5GCR6_RESERVED_7_6_MASK | DDR_PHY_DX5GCR6_DXDQVREFR0_MASK | 0 ); + /* + * Register : DX7GCR5 @ 0XFD080E14 - RegVal = ((0x00000000U << DDR_PHY_DX5GCR6_RESERVED_31_30_SHIFT - | 0x00000009U << DDR_PHY_DX5GCR6_DXDQVREFR3_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR6_RESERVED_23_22_SHIFT - | 0x00000009U << DDR_PHY_DX5GCR6_DXDQVREFR2_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR6_RESERVED_15_14_SHIFT - | 0x0000002BU << DDR_PHY_DX5GCR6_DXDQVREFR1_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR6_RESERVED_7_6_SHIFT - | 0x0000002BU << DDR_PHY_DX5GCR6_DXDQVREFR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX5GCR6_OFFSET ,0xFFFFFFFFU ,0x09092B2BU); - /*############################################################################################################################ */ + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX7GCR5_RESERVED_31 0x0 - /*Register : DX5LCDLR2 @ 0XFD080C88

+ * Byte Lane internal VREF Select for Rank 3 + * PSU_DDR_PHY_DX7GCR5_DXREFISELR3 0x9 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX5LCDLR2_RESERVED_31_25 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX7GCR5_RESERVED_23 0x0 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX5LCDLR2_RESERVED_24_16 0x0 + * Byte Lane internal VREF Select for Rank 2 + * PSU_DDR_PHY_DX7GCR5_DXREFISELR2 0x9 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX5LCDLR2_RESERVED_15_9 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX7GCR5_RESERVED_15 0x0 - Read DQS Gating Delay - PSU_DDR_PHY_DX5LCDLR2_DQSGD 0x0 + * Byte Lane internal VREF Select for Rank 1 + * PSU_DDR_PHY_DX7GCR5_DXREFISELR1 0x55 - DATX8 n Local Calibrated Delay Line Register 2 - (OFFSET, MASK, VALUE) (0XFD080C88, 0xFFFFFFFFU ,0x00000000U) - RegMask = (DDR_PHY_DX5LCDLR2_RESERVED_31_25_MASK | DDR_PHY_DX5LCDLR2_RESERVED_24_16_MASK | DDR_PHY_DX5LCDLR2_RESERVED_15_9_MASK | DDR_PHY_DX5LCDLR2_DQSGD_MASK | 0 ); + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX7GCR5_RESERVED_7 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX5LCDLR2_RESERVED_31_25_SHIFT - | 0x00000000U << DDR_PHY_DX5LCDLR2_RESERVED_24_16_SHIFT - | 0x00000000U << DDR_PHY_DX5LCDLR2_RESERVED_15_9_SHIFT - | 0x00000000U << DDR_PHY_DX5LCDLR2_DQSGD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX5LCDLR2_OFFSET ,0xFFFFFFFFU ,0x00000000U); - /*############################################################################################################################ */ + * Byte Lane internal VREF Select for Rank 0 + * PSU_DDR_PHY_DX7GCR5_DXREFISELR0 0x55 - /*Register : DX5GTR0 @ 0XFD080CC0

+ * DATX8 n General Configuration Register 5 + * (OFFSET, MASK, VALUE) (0XFD080E14, 0xFFFFFFFFU ,0x09095555U) + */ + PSU_Mask_Write(DDR_PHY_DX7GCR5_OFFSET, 0xFFFFFFFFU, 0x09095555U); +/*##################################################################### */ - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX5GTR0_RESERVED_31_24 0x0 + /* + * Register : DX7GCR6 @ 0XFD080E18 - DQ Write Path Latency Pipeline - PSU_DDR_PHY_DX5GTR0_WDQSL 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX7GCR6_RESERVED_31_30 0x0 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX5GTR0_RESERVED_23_20 0x0 + * DRAM DQ VREF Select for Rank3 + * PSU_DDR_PHY_DX7GCR6_DXDQVREFR3 0x9 - Write Leveling System Latency - PSU_DDR_PHY_DX5GTR0_WLSL 0x2 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX7GCR6_RESERVED_23_22 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX5GTR0_RESERVED_15_13 0x0 + * DRAM DQ VREF Select for Rank2 + * PSU_DDR_PHY_DX7GCR6_DXDQVREFR2 0x9 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX5GTR0_RESERVED_12_8 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX7GCR6_RESERVED_15_14 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX5GTR0_RESERVED_7_5 0x0 + * DRAM DQ VREF Select for Rank1 + * PSU_DDR_PHY_DX7GCR6_DXDQVREFR1 0x2b - DQS Gating System Latency - PSU_DDR_PHY_DX5GTR0_DGSL 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX7GCR6_RESERVED_7_6 0x0 - DATX8 n General Timing Register 0 - (OFFSET, MASK, VALUE) (0XFD080CC0, 0xFFFFFFFFU ,0x00020000U) - RegMask = (DDR_PHY_DX5GTR0_RESERVED_31_24_MASK | DDR_PHY_DX5GTR0_WDQSL_MASK | DDR_PHY_DX5GTR0_RESERVED_23_20_MASK | DDR_PHY_DX5GTR0_WLSL_MASK | DDR_PHY_DX5GTR0_RESERVED_15_13_MASK | DDR_PHY_DX5GTR0_RESERVED_12_8_MASK | DDR_PHY_DX5GTR0_RESERVED_7_5_MASK | DDR_PHY_DX5GTR0_DGSL_MASK | 0 ); + * DRAM DQ VREF Select for Rank0 + * PSU_DDR_PHY_DX7GCR6_DXDQVREFR0 0x2b - RegVal = ((0x00000000U << DDR_PHY_DX5GTR0_RESERVED_31_24_SHIFT - | 0x00000000U << DDR_PHY_DX5GTR0_WDQSL_SHIFT - | 0x00000000U << DDR_PHY_DX5GTR0_RESERVED_23_20_SHIFT - | 0x00000002U << DDR_PHY_DX5GTR0_WLSL_SHIFT - | 0x00000000U << DDR_PHY_DX5GTR0_RESERVED_15_13_SHIFT - | 0x00000000U << DDR_PHY_DX5GTR0_RESERVED_12_8_SHIFT - | 0x00000000U << DDR_PHY_DX5GTR0_RESERVED_7_5_SHIFT - | 0x00000000U << DDR_PHY_DX5GTR0_DGSL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX5GTR0_OFFSET ,0xFFFFFFFFU ,0x00020000U); - /*############################################################################################################################ */ + * DATX8 n General Configuration Register 6 + * (OFFSET, MASK, VALUE) (0XFD080E18, 0xFFFFFFFFU ,0x09092B2BU) + */ + PSU_Mask_Write(DDR_PHY_DX7GCR6_OFFSET, 0xFFFFFFFFU, 0x09092B2BU); +/*##################################################################### */ - /*Register : DX6GCR0 @ 0XFD080D00

+ /* + * Register : DX8GCR0 @ 0XFD080F00 - Calibration Bypass - PSU_DDR_PHY_DX6GCR0_CALBYP 0x0 + * Calibration Bypass + * PSU_DDR_PHY_DX8GCR0_CALBYP 0x0 - Master Delay Line Enable - PSU_DDR_PHY_DX6GCR0_MDLEN 0x1 + * Master Delay Line Enable + * PSU_DDR_PHY_DX8GCR0_MDLEN 0x1 - Configurable ODT(TE) Phase Shift - PSU_DDR_PHY_DX6GCR0_CODTSHFT 0x0 + * Configurable ODT(TE) Phase Shift + * PSU_DDR_PHY_DX8GCR0_CODTSHFT 0x0 - DQS Duty Cycle Correction - PSU_DDR_PHY_DX6GCR0_DQSDCC 0x0 + * DQS Duty Cycle Correction + * PSU_DDR_PHY_DX8GCR0_DQSDCC 0x0 - Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY - PSU_DDR_PHY_DX6GCR0_RDDLY 0x8 + * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY + * PSU_DDR_PHY_DX8GCR0_RDDLY 0x8 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX6GCR0_RESERVED_19_14 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8GCR0_RESERVED_19_14 0x0 - DQSNSE Power Down Receiver - PSU_DDR_PHY_DX6GCR0_DQSNSEPDR 0x0 + * DQSNSE Power Down Receiver + * PSU_DDR_PHY_DX8GCR0_DQSNSEPDR 0x0 - DQSSE Power Down Receiver - PSU_DDR_PHY_DX6GCR0_DQSSEPDR 0x0 + * DQSSE Power Down Receiver + * PSU_DDR_PHY_DX8GCR0_DQSSEPDR 0x0 - RTT On Additive Latency - PSU_DDR_PHY_DX6GCR0_RTTOAL 0x0 + * RTT On Additive Latency + * PSU_DDR_PHY_DX8GCR0_RTTOAL 0x0 - RTT Output Hold - PSU_DDR_PHY_DX6GCR0_RTTOH 0x3 + * RTT Output Hold + * PSU_DDR_PHY_DX8GCR0_RTTOH 0x3 - Configurable PDR Phase Shift - PSU_DDR_PHY_DX6GCR0_CPDRSHFT 0x0 + * Configurable PDR Phase Shift + * PSU_DDR_PHY_DX8GCR0_CPDRSHFT 0x0 - DQSR Power Down - PSU_DDR_PHY_DX6GCR0_DQSRPD 0x0 + * DQSR Power Down + * PSU_DDR_PHY_DX8GCR0_DQSRPD 0x0 - DQSG Power Down Receiver - PSU_DDR_PHY_DX6GCR0_DQSGPDR 0x0 + * DQSG Power Down Receiver + * PSU_DDR_PHY_DX8GCR0_DQSGPDR 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX6GCR0_RESERVED_4 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8GCR0_RESERVED_4 0x0 - DQSG On-Die Termination - PSU_DDR_PHY_DX6GCR0_DQSGODT 0x0 + * DQSG On-Die Termination + * PSU_DDR_PHY_DX8GCR0_DQSGODT 0x0 - DQSG Output Enable - PSU_DDR_PHY_DX6GCR0_DQSGOE 0x1 + * DQSG Output Enable + * PSU_DDR_PHY_DX8GCR0_DQSGOE 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX6GCR0_RESERVED_1_0 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8GCR0_RESERVED_1_0 0x0 - DATX8 n General Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD080D00, 0xFFFFFFFFU ,0x40800604U) - RegMask = (DDR_PHY_DX6GCR0_CALBYP_MASK | DDR_PHY_DX6GCR0_MDLEN_MASK | DDR_PHY_DX6GCR0_CODTSHFT_MASK | DDR_PHY_DX6GCR0_DQSDCC_MASK | DDR_PHY_DX6GCR0_RDDLY_MASK | DDR_PHY_DX6GCR0_RESERVED_19_14_MASK | DDR_PHY_DX6GCR0_DQSNSEPDR_MASK | DDR_PHY_DX6GCR0_DQSSEPDR_MASK | DDR_PHY_DX6GCR0_RTTOAL_MASK | DDR_PHY_DX6GCR0_RTTOH_MASK | DDR_PHY_DX6GCR0_CPDRSHFT_MASK | DDR_PHY_DX6GCR0_DQSRPD_MASK | DDR_PHY_DX6GCR0_DQSGPDR_MASK | DDR_PHY_DX6GCR0_RESERVED_4_MASK | DDR_PHY_DX6GCR0_DQSGODT_MASK | DDR_PHY_DX6GCR0_DQSGOE_MASK | DDR_PHY_DX6GCR0_RESERVED_1_0_MASK | 0 ); + * DATX8 n General Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD080F00, 0xFFFFFFFFU ,0x40800624U) + */ + PSU_Mask_Write(DDR_PHY_DX8GCR0_OFFSET, 0xFFFFFFFFU, 0x40800624U); +/*##################################################################### */ - RegVal = ((0x00000000U << DDR_PHY_DX6GCR0_CALBYP_SHIFT - | 0x00000001U << DDR_PHY_DX6GCR0_MDLEN_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR0_CODTSHFT_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR0_DQSDCC_SHIFT - | 0x00000008U << DDR_PHY_DX6GCR0_RDDLY_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR0_RESERVED_19_14_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR0_DQSNSEPDR_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR0_DQSSEPDR_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR0_RTTOAL_SHIFT - | 0x00000003U << DDR_PHY_DX6GCR0_RTTOH_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR0_CPDRSHFT_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR0_DQSRPD_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR0_DQSGPDR_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR0_RESERVED_4_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR0_DQSGODT_SHIFT - | 0x00000001U << DDR_PHY_DX6GCR0_DQSGOE_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR0_RESERVED_1_0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX6GCR0_OFFSET ,0xFFFFFFFFU ,0x40800604U); - /*############################################################################################################################ */ + /* + * Register : DX8GCR1 @ 0XFD080F04 - /*Register : DX6GCR1 @ 0XFD080D04

+ * Enables the PDR mode for DQ[7:0] + * PSU_DDR_PHY_DX8GCR1_DXPDRMODE 0x0 - Enables the PDR mode for DQ[7:0] - PSU_DDR_PHY_DX6GCR1_DXPDRMODE 0x0 + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX8GCR1_RESERVED_15 0x0 - Reserved. Returns zeroes on reads. - PSU_DDR_PHY_DX6GCR1_RESERVED_15 0x0 + * Select the delayed or non-delayed read data strobe # + * PSU_DDR_PHY_DX8GCR1_QSNSEL 0x1 - Select the delayed or non-delayed read data strobe # - PSU_DDR_PHY_DX6GCR1_QSNSEL 0x1 + * Select the delayed or non-delayed read data strobe + * PSU_DDR_PHY_DX8GCR1_QSSEL 0x1 - Select the delayed or non-delayed read data strobe - PSU_DDR_PHY_DX6GCR1_QSSEL 0x1 + * Enables Read Data Strobe in a byte lane + * PSU_DDR_PHY_DX8GCR1_OEEN 0x1 - Enables Read Data Strobe in a byte lane - PSU_DDR_PHY_DX6GCR1_OEEN 0x1 + * Enables PDR in a byte lane + * PSU_DDR_PHY_DX8GCR1_PDREN 0x1 - Enables PDR in a byte lane - PSU_DDR_PHY_DX6GCR1_PDREN 0x1 + * Enables ODT/TE in a byte lane + * PSU_DDR_PHY_DX8GCR1_TEEN 0x1 - Enables ODT/TE in a byte lane - PSU_DDR_PHY_DX6GCR1_TEEN 0x1 + * Enables Write Data strobe in a byte lane + * PSU_DDR_PHY_DX8GCR1_DSEN 0x1 - Enables Write Data strobe in a byte lane - PSU_DDR_PHY_DX6GCR1_DSEN 0x1 + * Enables DM pin in a byte lane + * PSU_DDR_PHY_DX8GCR1_DMEN 0x1 - Enables DM pin in a byte lane - PSU_DDR_PHY_DX6GCR1_DMEN 0x1 + * Enables DQ corresponding to each bit in a byte + * PSU_DDR_PHY_DX8GCR1_DQEN 0x0 - Enables DQ corresponding to each bit in a byte - PSU_DDR_PHY_DX6GCR1_DQEN 0xff + * DATX8 n General Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD080F04, 0xFFFFFFFFU ,0x00007F00U) + */ + PSU_Mask_Write(DDR_PHY_DX8GCR1_OFFSET, 0xFFFFFFFFU, 0x00007F00U); +/*##################################################################### */ - DATX8 n General Configuration Register 1 - (OFFSET, MASK, VALUE) (0XFD080D04, 0xFFFFFFFFU ,0x00007FFFU) - RegMask = (DDR_PHY_DX6GCR1_DXPDRMODE_MASK | DDR_PHY_DX6GCR1_RESERVED_15_MASK | DDR_PHY_DX6GCR1_QSNSEL_MASK | DDR_PHY_DX6GCR1_QSSEL_MASK | DDR_PHY_DX6GCR1_OEEN_MASK | DDR_PHY_DX6GCR1_PDREN_MASK | DDR_PHY_DX6GCR1_TEEN_MASK | DDR_PHY_DX6GCR1_DSEN_MASK | DDR_PHY_DX6GCR1_DMEN_MASK | DDR_PHY_DX6GCR1_DQEN_MASK | 0 ); + /* + * Register : DX8GCR4 @ 0XFD080F10 - RegVal = ((0x00000000U << DDR_PHY_DX6GCR1_DXPDRMODE_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR1_RESERVED_15_SHIFT - | 0x00000001U << DDR_PHY_DX6GCR1_QSNSEL_SHIFT - | 0x00000001U << DDR_PHY_DX6GCR1_QSSEL_SHIFT - | 0x00000001U << DDR_PHY_DX6GCR1_OEEN_SHIFT - | 0x00000001U << DDR_PHY_DX6GCR1_PDREN_SHIFT - | 0x00000001U << DDR_PHY_DX6GCR1_TEEN_SHIFT - | 0x00000001U << DDR_PHY_DX6GCR1_DSEN_SHIFT - | 0x00000001U << DDR_PHY_DX6GCR1_DMEN_SHIFT - | 0x000000FFU << DDR_PHY_DX6GCR1_DQEN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX6GCR1_OFFSET ,0xFFFFFFFFU ,0x00007FFFU); - /*############################################################################################################################ */ + * Byte lane VREF IOM (Used only by D4MU IOs) + * PSU_DDR_PHY_DX8GCR4_RESERVED_31_29 0x0 - /*Register : DX6GCR4 @ 0XFD080D10

+ * Byte Lane VREF Pad Enable + * PSU_DDR_PHY_DX8GCR4_DXREFPEN 0x0 - Byte lane VREF IOM (Used only by D4MU IOs) - PSU_DDR_PHY_DX6GCR4_RESERVED_31_29 0x0 + * Byte Lane Internal VREF Enable + * PSU_DDR_PHY_DX8GCR4_DXREFEEN 0x3 - Byte Lane VREF Pad Enable - PSU_DDR_PHY_DX6GCR4_DXREFPEN 0x0 + * Byte Lane Single-End VREF Enable + * PSU_DDR_PHY_DX8GCR4_DXREFSEN 0x1 - Byte Lane Internal VREF Enable - PSU_DDR_PHY_DX6GCR4_DXREFEEN 0x3 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX8GCR4_RESERVED_24 0x0 - Byte Lane Single-End VREF Enable - PSU_DDR_PHY_DX6GCR4_DXREFSEN 0x1 + * External VREF generator REFSEL range select + * PSU_DDR_PHY_DX8GCR4_DXREFESELRANGE 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX6GCR4_RESERVED_24 0x0 + * Byte Lane External VREF Select + * PSU_DDR_PHY_DX8GCR4_DXREFESEL 0x0 - External VREF generator REFSEL range select - PSU_DDR_PHY_DX6GCR4_DXREFESELRANGE 0x0 + * Single ended VREF generator REFSEL range select + * PSU_DDR_PHY_DX8GCR4_DXREFSSELRANGE 0x1 - Byte Lane External VREF Select - PSU_DDR_PHY_DX6GCR4_DXREFESEL 0x0 + * Byte Lane Single-End VREF Select + * PSU_DDR_PHY_DX8GCR4_DXREFSSEL 0x30 - Single ended VREF generator REFSEL range select - PSU_DDR_PHY_DX6GCR4_DXREFSSELRANGE 0x1 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX8GCR4_RESERVED_7_6 0x0 - Byte Lane Single-End VREF Select - PSU_DDR_PHY_DX6GCR4_DXREFSSEL 0x30 + * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX8GCR4_DXREFIEN 0xf - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX6GCR4_RESERVED_7_6 0x0 + * VRMON control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX8GCR4_DXREFIMON 0x0 - VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. - PSU_DDR_PHY_DX6GCR4_DXREFIEN 0xf + * DATX8 n General Configuration Register 4 + * (OFFSET, MASK, VALUE) (0XFD080F10, 0xFFFFFFFFU ,0x0E00B03CU) + */ + PSU_Mask_Write(DDR_PHY_DX8GCR4_OFFSET, 0xFFFFFFFFU, 0x0E00B03CU); +/*##################################################################### */ - VRMON control for DQ IO (Single Ended) buffers of a byte lane. - PSU_DDR_PHY_DX6GCR4_DXREFIMON 0x0 + /* + * Register : DX8GCR5 @ 0XFD080F14 - DATX8 n General Configuration Register 4 - (OFFSET, MASK, VALUE) (0XFD080D10, 0xFFFFFFFFU ,0x0E00B03CU) - RegMask = (DDR_PHY_DX6GCR4_RESERVED_31_29_MASK | DDR_PHY_DX6GCR4_DXREFPEN_MASK | DDR_PHY_DX6GCR4_DXREFEEN_MASK | DDR_PHY_DX6GCR4_DXREFSEN_MASK | DDR_PHY_DX6GCR4_RESERVED_24_MASK | DDR_PHY_DX6GCR4_DXREFESELRANGE_MASK | DDR_PHY_DX6GCR4_DXREFESEL_MASK | DDR_PHY_DX6GCR4_DXREFSSELRANGE_MASK | DDR_PHY_DX6GCR4_DXREFSSEL_MASK | DDR_PHY_DX6GCR4_RESERVED_7_6_MASK | DDR_PHY_DX6GCR4_DXREFIEN_MASK | DDR_PHY_DX6GCR4_DXREFIMON_MASK | 0 ); + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX8GCR5_RESERVED_31 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX6GCR4_RESERVED_31_29_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR4_DXREFPEN_SHIFT - | 0x00000003U << DDR_PHY_DX6GCR4_DXREFEEN_SHIFT - | 0x00000001U << DDR_PHY_DX6GCR4_DXREFSEN_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR4_RESERVED_24_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR4_DXREFESELRANGE_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR4_DXREFESEL_SHIFT - | 0x00000001U << DDR_PHY_DX6GCR4_DXREFSSELRANGE_SHIFT - | 0x00000030U << DDR_PHY_DX6GCR4_DXREFSSEL_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR4_RESERVED_7_6_SHIFT - | 0x0000000FU << DDR_PHY_DX6GCR4_DXREFIEN_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR4_DXREFIMON_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX6GCR4_OFFSET ,0xFFFFFFFFU ,0x0E00B03CU); - /*############################################################################################################################ */ + * Byte Lane internal VREF Select for Rank 3 + * PSU_DDR_PHY_DX8GCR5_DXREFISELR3 0x9 - /*Register : DX6GCR5 @ 0XFD080D14

+ * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX8GCR5_RESERVED_23 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX6GCR5_RESERVED_31 0x0 + * Byte Lane internal VREF Select for Rank 2 + * PSU_DDR_PHY_DX8GCR5_DXREFISELR2 0x9 - Byte Lane internal VREF Select for Rank 3 - PSU_DDR_PHY_DX6GCR5_DXREFISELR3 0x9 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX8GCR5_RESERVED_15 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX6GCR5_RESERVED_23 0x0 + * Byte Lane internal VREF Select for Rank 1 + * PSU_DDR_PHY_DX8GCR5_DXREFISELR1 0x55 - Byte Lane internal VREF Select for Rank 2 - PSU_DDR_PHY_DX6GCR5_DXREFISELR2 0x9 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX8GCR5_RESERVED_7 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX6GCR5_RESERVED_15 0x0 + * Byte Lane internal VREF Select for Rank 0 + * PSU_DDR_PHY_DX8GCR5_DXREFISELR0 0x55 - Byte Lane internal VREF Select for Rank 1 - PSU_DDR_PHY_DX6GCR5_DXREFISELR1 0x4f + * DATX8 n General Configuration Register 5 + * (OFFSET, MASK, VALUE) (0XFD080F14, 0xFFFFFFFFU ,0x09095555U) + */ + PSU_Mask_Write(DDR_PHY_DX8GCR5_OFFSET, 0xFFFFFFFFU, 0x09095555U); +/*##################################################################### */ - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX6GCR5_RESERVED_7 0x0 + /* + * Register : DX8GCR6 @ 0XFD080F18 - Byte Lane internal VREF Select for Rank 0 - PSU_DDR_PHY_DX6GCR5_DXREFISELR0 0x4f + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX8GCR6_RESERVED_31_30 0x0 - DATX8 n General Configuration Register 5 - (OFFSET, MASK, VALUE) (0XFD080D14, 0xFFFFFFFFU ,0x09094F4FU) - RegMask = (DDR_PHY_DX6GCR5_RESERVED_31_MASK | DDR_PHY_DX6GCR5_DXREFISELR3_MASK | DDR_PHY_DX6GCR5_RESERVED_23_MASK | DDR_PHY_DX6GCR5_DXREFISELR2_MASK | DDR_PHY_DX6GCR5_RESERVED_15_MASK | DDR_PHY_DX6GCR5_DXREFISELR1_MASK | DDR_PHY_DX6GCR5_RESERVED_7_MASK | DDR_PHY_DX6GCR5_DXREFISELR0_MASK | 0 ); + * DRAM DQ VREF Select for Rank3 + * PSU_DDR_PHY_DX8GCR6_DXDQVREFR3 0x9 - RegVal = ((0x00000000U << DDR_PHY_DX6GCR5_RESERVED_31_SHIFT - | 0x00000009U << DDR_PHY_DX6GCR5_DXREFISELR3_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR5_RESERVED_23_SHIFT - | 0x00000009U << DDR_PHY_DX6GCR5_DXREFISELR2_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR5_RESERVED_15_SHIFT - | 0x0000004FU << DDR_PHY_DX6GCR5_DXREFISELR1_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR5_RESERVED_7_SHIFT - | 0x0000004FU << DDR_PHY_DX6GCR5_DXREFISELR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX6GCR5_OFFSET ,0xFFFFFFFFU ,0x09094F4FU); - /*############################################################################################################################ */ + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX8GCR6_RESERVED_23_22 0x0 - /*Register : DX6GCR6 @ 0XFD080D18

+ * DRAM DQ VREF Select for Rank2 + * PSU_DDR_PHY_DX8GCR6_DXDQVREFR2 0x9 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX6GCR6_RESERVED_31_30 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX8GCR6_RESERVED_15_14 0x0 - DRAM DQ VREF Select for Rank3 - PSU_DDR_PHY_DX6GCR6_DXDQVREFR3 0x9 + * DRAM DQ VREF Select for Rank1 + * PSU_DDR_PHY_DX8GCR6_DXDQVREFR1 0x2b - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX6GCR6_RESERVED_23_22 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX8GCR6_RESERVED_7_6 0x0 - DRAM DQ VREF Select for Rank2 - PSU_DDR_PHY_DX6GCR6_DXDQVREFR2 0x9 + * DRAM DQ VREF Select for Rank0 + * PSU_DDR_PHY_DX8GCR6_DXDQVREFR0 0x2b - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX6GCR6_RESERVED_15_14 0x0 + * DATX8 n General Configuration Register 6 + * (OFFSET, MASK, VALUE) (0XFD080F18, 0xFFFFFFFFU ,0x09092B2BU) + */ + PSU_Mask_Write(DDR_PHY_DX8GCR6_OFFSET, 0xFFFFFFFFU, 0x09092B2BU); +/*##################################################################### */ - DRAM DQ VREF Select for Rank1 - PSU_DDR_PHY_DX6GCR6_DXDQVREFR1 0x2b + /* + * Register : DX8SL0OSC @ 0XFD081400 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX6GCR6_RESERVED_7_6 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL0OSC_RESERVED_31_30 0x0 - DRAM DQ VREF Select for Rank0 - PSU_DDR_PHY_DX6GCR6_DXDQVREFR0 0x2b + * Enable Clock Gating for DX ddr_clk + * PSU_DDR_PHY_DX8SL0OSC_GATEDXRDCLK 0x2 - DATX8 n General Configuration Register 6 - (OFFSET, MASK, VALUE) (0XFD080D18, 0xFFFFFFFFU ,0x09092B2BU) - RegMask = (DDR_PHY_DX6GCR6_RESERVED_31_30_MASK | DDR_PHY_DX6GCR6_DXDQVREFR3_MASK | DDR_PHY_DX6GCR6_RESERVED_23_22_MASK | DDR_PHY_DX6GCR6_DXDQVREFR2_MASK | DDR_PHY_DX6GCR6_RESERVED_15_14_MASK | DDR_PHY_DX6GCR6_DXDQVREFR1_MASK | DDR_PHY_DX6GCR6_RESERVED_7_6_MASK | DDR_PHY_DX6GCR6_DXDQVREFR0_MASK | 0 ); + * Enable Clock Gating for DX ctl_rd_clk + * PSU_DDR_PHY_DX8SL0OSC_GATEDXDDRCLK 0x2 - RegVal = ((0x00000000U << DDR_PHY_DX6GCR6_RESERVED_31_30_SHIFT - | 0x00000009U << DDR_PHY_DX6GCR6_DXDQVREFR3_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR6_RESERVED_23_22_SHIFT - | 0x00000009U << DDR_PHY_DX6GCR6_DXDQVREFR2_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR6_RESERVED_15_14_SHIFT - | 0x0000002BU << DDR_PHY_DX6GCR6_DXDQVREFR1_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR6_RESERVED_7_6_SHIFT - | 0x0000002BU << DDR_PHY_DX6GCR6_DXDQVREFR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX6GCR6_OFFSET ,0xFFFFFFFFU ,0x09092B2BU); - /*############################################################################################################################ */ + * Enable Clock Gating for DX ctl_clk + * PSU_DDR_PHY_DX8SL0OSC_GATEDXCTLCLK 0x2 - /*Register : DX6LCDLR2 @ 0XFD080D88

+ * Selects the level to which clocks will be stalled when clock gating is e + * nabled. + * PSU_DDR_PHY_DX8SL0OSC_CLKLEVEL 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX6LCDLR2_RESERVED_31_25 0x0 + * Loopback Mode + * PSU_DDR_PHY_DX8SL0OSC_LBMODE 0x0 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX6LCDLR2_RESERVED_24_16 0x0 + * Load GSDQS LCDL with 2x the calibrated GSDQSPRD value + * PSU_DDR_PHY_DX8SL0OSC_LBGSDQS 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX6LCDLR2_RESERVED_15_9 0x0 + * Loopback DQS Gating + * PSU_DDR_PHY_DX8SL0OSC_LBGDQS 0x0 - Read DQS Gating Delay - PSU_DDR_PHY_DX6LCDLR2_DQSGD 0x0 + * Loopback DQS Shift + * PSU_DDR_PHY_DX8SL0OSC_LBDQSS 0x0 - DATX8 n Local Calibrated Delay Line Register 2 - (OFFSET, MASK, VALUE) (0XFD080D88, 0xFFFFFFFFU ,0x00000000U) - RegMask = (DDR_PHY_DX6LCDLR2_RESERVED_31_25_MASK | DDR_PHY_DX6LCDLR2_RESERVED_24_16_MASK | DDR_PHY_DX6LCDLR2_RESERVED_15_9_MASK | DDR_PHY_DX6LCDLR2_DQSGD_MASK | 0 ); + * PHY High-Speed Reset + * PSU_DDR_PHY_DX8SL0OSC_PHYHRST 0x1 - RegVal = ((0x00000000U << DDR_PHY_DX6LCDLR2_RESERVED_31_25_SHIFT - | 0x00000000U << DDR_PHY_DX6LCDLR2_RESERVED_24_16_SHIFT - | 0x00000000U << DDR_PHY_DX6LCDLR2_RESERVED_15_9_SHIFT - | 0x00000000U << DDR_PHY_DX6LCDLR2_DQSGD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX6LCDLR2_OFFSET ,0xFFFFFFFFU ,0x00000000U); - /*############################################################################################################################ */ + * PHY FIFO Reset + * PSU_DDR_PHY_DX8SL0OSC_PHYFRST 0x1 - /*Register : DX6GTR0 @ 0XFD080DC0

+ * Delay Line Test Start + * PSU_DDR_PHY_DX8SL0OSC_DLTST 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX6GTR0_RESERVED_31_24 0x0 + * Delay Line Test Mode + * PSU_DDR_PHY_DX8SL0OSC_DLTMODE 0x0 - DQ Write Path Latency Pipeline - PSU_DDR_PHY_DX6GTR0_WDQSL 0x0 + * Reserved. Caution, do not write to this register field. + * PSU_DDR_PHY_DX8SL0OSC_RESERVED_12_11 0x3 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX6GTR0_RESERVED_23_20 0x0 + * Oscillator Mode Write-Data Delay Line Select + * PSU_DDR_PHY_DX8SL0OSC_OSCWDDL 0x3 - Write Leveling System Latency - PSU_DDR_PHY_DX6GTR0_WLSL 0x2 + * Reserved. Caution, do not write to this register field. + * PSU_DDR_PHY_DX8SL0OSC_RESERVED_8_7 0x3 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX6GTR0_RESERVED_15_13 0x0 + * Oscillator Mode Write-Leveling Delay Line Select + * PSU_DDR_PHY_DX8SL0OSC_OSCWDL 0x3 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX6GTR0_RESERVED_12_8 0x0 + * Oscillator Mode Division + * PSU_DDR_PHY_DX8SL0OSC_OSCDIV 0xf - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX6GTR0_RESERVED_7_5 0x0 + * Oscillator Enable + * PSU_DDR_PHY_DX8SL0OSC_OSCEN 0x0 - DQS Gating System Latency - PSU_DDR_PHY_DX6GTR0_DGSL 0x0 + * DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Lo + * opback, and Gated Clock Control Register + * (OFFSET, MASK, VALUE) (0XFD081400, 0xFFFFFFFFU ,0x2A019FFEU) + */ + PSU_Mask_Write(DDR_PHY_DX8SL0OSC_OFFSET, 0xFFFFFFFFU, 0x2A019FFEU); +/*##################################################################### */ - DATX8 n General Timing Register 0 - (OFFSET, MASK, VALUE) (0XFD080DC0, 0xFFFFFFFFU ,0x00020000U) - RegMask = (DDR_PHY_DX6GTR0_RESERVED_31_24_MASK | DDR_PHY_DX6GTR0_WDQSL_MASK | DDR_PHY_DX6GTR0_RESERVED_23_20_MASK | DDR_PHY_DX6GTR0_WLSL_MASK | DDR_PHY_DX6GTR0_RESERVED_15_13_MASK | DDR_PHY_DX6GTR0_RESERVED_12_8_MASK | DDR_PHY_DX6GTR0_RESERVED_7_5_MASK | DDR_PHY_DX6GTR0_DGSL_MASK | 0 ); + /* + * Register : DX8SL0PLLCR0 @ 0XFD081404 - RegVal = ((0x00000000U << DDR_PHY_DX6GTR0_RESERVED_31_24_SHIFT - | 0x00000000U << DDR_PHY_DX6GTR0_WDQSL_SHIFT - | 0x00000000U << DDR_PHY_DX6GTR0_RESERVED_23_20_SHIFT - | 0x00000002U << DDR_PHY_DX6GTR0_WLSL_SHIFT - | 0x00000000U << DDR_PHY_DX6GTR0_RESERVED_15_13_SHIFT - | 0x00000000U << DDR_PHY_DX6GTR0_RESERVED_12_8_SHIFT - | 0x00000000U << DDR_PHY_DX6GTR0_RESERVED_7_5_SHIFT - | 0x00000000U << DDR_PHY_DX6GTR0_DGSL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX6GTR0_OFFSET ,0xFFFFFFFFU ,0x00020000U); - /*############################################################################################################################ */ + * PLL Bypass + * PSU_DDR_PHY_DX8SL0PLLCR0_PLLBYP 0x0 - /*Register : DX7GCR0 @ 0XFD080E00

+ * PLL Reset + * PSU_DDR_PHY_DX8SL0PLLCR0_PLLRST 0x0 - Calibration Bypass - PSU_DDR_PHY_DX7GCR0_CALBYP 0x0 + * PLL Power Down + * PSU_DDR_PHY_DX8SL0PLLCR0_PLLPD 0x0 - Master Delay Line Enable - PSU_DDR_PHY_DX7GCR0_MDLEN 0x1 + * Reference Stop Mode + * PSU_DDR_PHY_DX8SL0PLLCR0_RSTOPM 0x0 - Configurable ODT(TE) Phase Shift - PSU_DDR_PHY_DX7GCR0_CODTSHFT 0x0 + * PLL Frequency Select + * PSU_DDR_PHY_DX8SL0PLLCR0_FRQSEL 0x1 - DQS Duty Cycle Correction - PSU_DDR_PHY_DX7GCR0_DQSDCC 0x0 + * Relock Mode + * PSU_DDR_PHY_DX8SL0PLLCR0_RLOCKM 0x0 - Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY - PSU_DDR_PHY_DX7GCR0_RDDLY 0x8 + * Charge Pump Proportional Current Control + * PSU_DDR_PHY_DX8SL0PLLCR0_CPPC 0x8 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX7GCR0_RESERVED_19_14 0x0 + * Charge Pump Integrating Current Control + * PSU_DDR_PHY_DX8SL0PLLCR0_CPIC 0x0 - DQSNSE Power Down Receiver - PSU_DDR_PHY_DX7GCR0_DQSNSEPDR 0x0 + * Gear Shift + * PSU_DDR_PHY_DX8SL0PLLCR0_GSHIFT 0x0 - DQSSE Power Down Receiver - PSU_DDR_PHY_DX7GCR0_DQSSEPDR 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL0PLLCR0_RESERVED_11_9 0x0 - RTT On Additive Latency - PSU_DDR_PHY_DX7GCR0_RTTOAL 0x0 + * Analog Test Enable (ATOEN) + * PSU_DDR_PHY_DX8SL0PLLCR0_ATOEN 0x0 - RTT Output Hold - PSU_DDR_PHY_DX7GCR0_RTTOH 0x3 + * Analog Test Control + * PSU_DDR_PHY_DX8SL0PLLCR0_ATC 0x0 - Configurable PDR Phase Shift - PSU_DDR_PHY_DX7GCR0_CPDRSHFT 0x0 + * Digital Test Control + * PSU_DDR_PHY_DX8SL0PLLCR0_DTC 0x0 - DQSR Power Down - PSU_DDR_PHY_DX7GCR0_DQSRPD 0x0 + * DAXT8 0-1 PLL Control Register 0 + * (OFFSET, MASK, VALUE) (0XFD081404, 0xFFFFFFFFU ,0x01100000U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL0PLLCR0_OFFSET, + 0xFFFFFFFFU, 0x01100000U); +/*##################################################################### */ - DQSG Power Down Receiver - PSU_DDR_PHY_DX7GCR0_DQSGPDR 0x0 + /* + * Register : DX8SL0DQSCTL @ 0XFD08141C - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX7GCR0_RESERVED_4 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25 0x0 - DQSG On-Die Termination - PSU_DDR_PHY_DX7GCR0_DQSGODT 0x0 + * Read Path Rise-to-Rise Mode + * PSU_DDR_PHY_DX8SL0DQSCTL_RRRMODE 0x1 - DQSG Output Enable - PSU_DDR_PHY_DX7GCR0_DQSGOE 0x1 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX7GCR0_RESERVED_1_0 0x0 + * Write Path Rise-to-Rise Mode + * PSU_DDR_PHY_DX8SL0DQSCTL_WRRMODE 0x1 - DATX8 n General Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD080E00, 0xFFFFFFFFU ,0x40800604U) - RegMask = (DDR_PHY_DX7GCR0_CALBYP_MASK | DDR_PHY_DX7GCR0_MDLEN_MASK | DDR_PHY_DX7GCR0_CODTSHFT_MASK | DDR_PHY_DX7GCR0_DQSDCC_MASK | DDR_PHY_DX7GCR0_RDDLY_MASK | DDR_PHY_DX7GCR0_RESERVED_19_14_MASK | DDR_PHY_DX7GCR0_DQSNSEPDR_MASK | DDR_PHY_DX7GCR0_DQSSEPDR_MASK | DDR_PHY_DX7GCR0_RTTOAL_MASK | DDR_PHY_DX7GCR0_RTTOH_MASK | DDR_PHY_DX7GCR0_CPDRSHFT_MASK | DDR_PHY_DX7GCR0_DQSRPD_MASK | DDR_PHY_DX7GCR0_DQSGPDR_MASK | DDR_PHY_DX7GCR0_RESERVED_4_MASK | DDR_PHY_DX7GCR0_DQSGODT_MASK | DDR_PHY_DX7GCR0_DQSGOE_MASK | DDR_PHY_DX7GCR0_RESERVED_1_0_MASK | 0 ); + * DQS Gate Extension + * PSU_DDR_PHY_DX8SL0DQSCTL_DQSGX 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX7GCR0_CALBYP_SHIFT - | 0x00000001U << DDR_PHY_DX7GCR0_MDLEN_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR0_CODTSHFT_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR0_DQSDCC_SHIFT - | 0x00000008U << DDR_PHY_DX7GCR0_RDDLY_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR0_RESERVED_19_14_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR0_DQSNSEPDR_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR0_DQSSEPDR_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR0_RTTOAL_SHIFT - | 0x00000003U << DDR_PHY_DX7GCR0_RTTOH_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR0_CPDRSHFT_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR0_DQSRPD_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR0_DQSGPDR_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR0_RESERVED_4_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR0_DQSGODT_SHIFT - | 0x00000001U << DDR_PHY_DX7GCR0_DQSGOE_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR0_RESERVED_1_0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX7GCR0_OFFSET ,0xFFFFFFFFU ,0x40800604U); - /*############################################################################################################################ */ + * Low Power PLL Power Down + * PSU_DDR_PHY_DX8SL0DQSCTL_LPPLLPD 0x1 - /*Register : DX7GCR1 @ 0XFD080E04

+ * Low Power I/O Power Down + * PSU_DDR_PHY_DX8SL0DQSCTL_LPIOPD 0x1 - Enables the PDR mode for DQ[7:0] - PSU_DDR_PHY_DX7GCR1_DXPDRMODE 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15 0x0 - Reserved. Returns zeroes on reads. - PSU_DDR_PHY_DX7GCR1_RESERVED_15 0x0 + * QS Counter Enable + * PSU_DDR_PHY_DX8SL0DQSCTL_QSCNTEN 0x1 - Select the delayed or non-delayed read data strobe # - PSU_DDR_PHY_DX7GCR1_QSNSEL 0x1 + * Unused DQ I/O Mode + * PSU_DDR_PHY_DX8SL0DQSCTL_UDQIOM 0x0 - Select the delayed or non-delayed read data strobe - PSU_DDR_PHY_DX7GCR1_QSSEL 0x1 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10 0x0 - Enables Read Data Strobe in a byte lane - PSU_DDR_PHY_DX7GCR1_OEEN 0x1 + * Data Slew Rate + * PSU_DDR_PHY_DX8SL0DQSCTL_DXSR 0x3 - Enables PDR in a byte lane - PSU_DDR_PHY_DX7GCR1_PDREN 0x1 + * DQS_N Resistor + * PSU_DDR_PHY_DX8SL0DQSCTL_DQSNRES 0x0 - Enables ODT/TE in a byte lane - PSU_DDR_PHY_DX7GCR1_TEEN 0x1 + * DQS Resistor + * PSU_DDR_PHY_DX8SL0DQSCTL_DQSRES 0x0 - Enables Write Data strobe in a byte lane - PSU_DDR_PHY_DX7GCR1_DSEN 0x1 + * DATX8 0-1 DQS Control Register + * (OFFSET, MASK, VALUE) (0XFD08141C, 0xFFFFFFFFU ,0x01264300U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL0DQSCTL_OFFSET, + 0xFFFFFFFFU, 0x01264300U); +/*##################################################################### */ - Enables DM pin in a byte lane - PSU_DDR_PHY_DX7GCR1_DMEN 0x1 + /* + * Register : DX8SL0DXCTL2 @ 0XFD08142C - Enables DQ corresponding to each bit in a byte - PSU_DDR_PHY_DX7GCR1_DQEN 0xff + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24 0x0 - DATX8 n General Configuration Register 1 - (OFFSET, MASK, VALUE) (0XFD080E04, 0xFFFFFFFFU ,0x00007FFFU) - RegMask = (DDR_PHY_DX7GCR1_DXPDRMODE_MASK | DDR_PHY_DX7GCR1_RESERVED_15_MASK | DDR_PHY_DX7GCR1_QSNSEL_MASK | DDR_PHY_DX7GCR1_QSSEL_MASK | DDR_PHY_DX7GCR1_OEEN_MASK | DDR_PHY_DX7GCR1_PDREN_MASK | DDR_PHY_DX7GCR1_TEEN_MASK | DDR_PHY_DX7GCR1_DSEN_MASK | DDR_PHY_DX7GCR1_DMEN_MASK | DDR_PHY_DX7GCR1_DQEN_MASK | 0 ); + * Configurable Read Data Enable + * PSU_DDR_PHY_DX8SL0DXCTL2_CRDEN 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX7GCR1_DXPDRMODE_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR1_RESERVED_15_SHIFT - | 0x00000001U << DDR_PHY_DX7GCR1_QSNSEL_SHIFT - | 0x00000001U << DDR_PHY_DX7GCR1_QSSEL_SHIFT - | 0x00000001U << DDR_PHY_DX7GCR1_OEEN_SHIFT - | 0x00000001U << DDR_PHY_DX7GCR1_PDREN_SHIFT - | 0x00000001U << DDR_PHY_DX7GCR1_TEEN_SHIFT - | 0x00000001U << DDR_PHY_DX7GCR1_DSEN_SHIFT - | 0x00000001U << DDR_PHY_DX7GCR1_DMEN_SHIFT - | 0x000000FFU << DDR_PHY_DX7GCR1_DQEN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX7GCR1_OFFSET ,0xFFFFFFFFU ,0x00007FFFU); - /*############################################################################################################################ */ + * OX Extension during Post-amble + * PSU_DDR_PHY_DX8SL0DXCTL2_POSOEX 0x0 - /*Register : DX7GCR4 @ 0XFD080E10

+ * OE Extension during Pre-amble + * PSU_DDR_PHY_DX8SL0DXCTL2_PREOEX 0x1 - Byte lane VREF IOM (Used only by D4MU IOs) - PSU_DDR_PHY_DX7GCR4_RESERVED_31_29 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_17 0x0 - Byte Lane VREF Pad Enable - PSU_DDR_PHY_DX7GCR4_DXREFPEN 0x0 + * I/O Assisted Gate Select + * PSU_DDR_PHY_DX8SL0DXCTL2_IOAG 0x0 - Byte Lane Internal VREF Enable - PSU_DDR_PHY_DX7GCR4_DXREFEEN 0x3 + * I/O Loopback Select + * PSU_DDR_PHY_DX8SL0DXCTL2_IOLB 0x0 - Byte Lane Single-End VREF Enable - PSU_DDR_PHY_DX7GCR4_DXREFSEN 0x1 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX7GCR4_RESERVED_24 0x0 + * Low Power Wakeup Threshold + * PSU_DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH 0xc - External VREF generator REFSEL range select - PSU_DDR_PHY_DX7GCR4_DXREFESELRANGE 0x0 + * Read Data Bus Inversion Enable + * PSU_DDR_PHY_DX8SL0DXCTL2_RDBI 0x0 - Byte Lane External VREF Select - PSU_DDR_PHY_DX7GCR4_DXREFESEL 0x0 + * Write Data Bus Inversion Enable + * PSU_DDR_PHY_DX8SL0DXCTL2_WDBI 0x0 - Single ended VREF generator REFSEL range select - PSU_DDR_PHY_DX7GCR4_DXREFSSELRANGE 0x1 + * PUB Read FIFO Bypass + * PSU_DDR_PHY_DX8SL0DXCTL2_PRFBYP 0x0 - Byte Lane Single-End VREF Select - PSU_DDR_PHY_DX7GCR4_DXREFSSEL 0x30 + * DATX8 Receive FIFO Read Mode + * PSU_DDR_PHY_DX8SL0DXCTL2_RDMODE 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX7GCR4_RESERVED_7_6 0x0 + * Disables the Read FIFO Reset + * PSU_DDR_PHY_DX8SL0DXCTL2_DISRST 0x0 - VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. - PSU_DDR_PHY_DX7GCR4_DXREFIEN 0xf + * Read DQS Gate I/O Loopback + * PSU_DDR_PHY_DX8SL0DXCTL2_DQSGLB 0x0 - VRMON control for DQ IO (Single Ended) buffers of a byte lane. - PSU_DDR_PHY_DX7GCR4_DXREFIMON 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_0 0x0 - DATX8 n General Configuration Register 4 - (OFFSET, MASK, VALUE) (0XFD080E10, 0xFFFFFFFFU ,0x0E00B03CU) - RegMask = (DDR_PHY_DX7GCR4_RESERVED_31_29_MASK | DDR_PHY_DX7GCR4_DXREFPEN_MASK | DDR_PHY_DX7GCR4_DXREFEEN_MASK | DDR_PHY_DX7GCR4_DXREFSEN_MASK | DDR_PHY_DX7GCR4_RESERVED_24_MASK | DDR_PHY_DX7GCR4_DXREFESELRANGE_MASK | DDR_PHY_DX7GCR4_DXREFESEL_MASK | DDR_PHY_DX7GCR4_DXREFSSELRANGE_MASK | DDR_PHY_DX7GCR4_DXREFSSEL_MASK | DDR_PHY_DX7GCR4_RESERVED_7_6_MASK | DDR_PHY_DX7GCR4_DXREFIEN_MASK | DDR_PHY_DX7GCR4_DXREFIMON_MASK | 0 ); + * DATX8 0-1 DX Control Register 2 + * (OFFSET, MASK, VALUE) (0XFD08142C, 0xFFFFFFFFU ,0x00041800U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL0DXCTL2_OFFSET, + 0xFFFFFFFFU, 0x00041800U); +/*##################################################################### */ - RegVal = ((0x00000000U << DDR_PHY_DX7GCR4_RESERVED_31_29_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR4_DXREFPEN_SHIFT - | 0x00000003U << DDR_PHY_DX7GCR4_DXREFEEN_SHIFT - | 0x00000001U << DDR_PHY_DX7GCR4_DXREFSEN_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR4_RESERVED_24_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR4_DXREFESELRANGE_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR4_DXREFESEL_SHIFT - | 0x00000001U << DDR_PHY_DX7GCR4_DXREFSSELRANGE_SHIFT - | 0x00000030U << DDR_PHY_DX7GCR4_DXREFSSEL_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR4_RESERVED_7_6_SHIFT - | 0x0000000FU << DDR_PHY_DX7GCR4_DXREFIEN_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR4_DXREFIMON_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX7GCR4_OFFSET ,0xFFFFFFFFU ,0x0E00B03CU); - /*############################################################################################################################ */ + /* + * Register : DX8SL0IOCR @ 0XFD081430 - /*Register : DX7GCR5 @ 0XFD080E14

+ * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL0IOCR_RESERVED_31 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX7GCR5_RESERVED_31 0x0 + * PVREF_DAC REFSEL range select + * PSU_DDR_PHY_DX8SL0IOCR_DXDACRANGE 0x7 - Byte Lane internal VREF Select for Rank 3 - PSU_DDR_PHY_DX7GCR5_DXREFISELR3 0x9 + * IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring + * PSU_DDR_PHY_DX8SL0IOCR_DXVREFIOM 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX7GCR5_RESERVED_23 0x0 + * DX IO Mode + * PSU_DDR_PHY_DX8SL0IOCR_DXIOM 0x2 - Byte Lane internal VREF Select for Rank 2 - PSU_DDR_PHY_DX7GCR5_DXREFISELR2 0x9 + * DX IO Transmitter Mode + * PSU_DDR_PHY_DX8SL0IOCR_DXTXM 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX7GCR5_RESERVED_15 0x0 + * DX IO Receiver Mode + * PSU_DDR_PHY_DX8SL0IOCR_DXRXM 0x0 - Byte Lane internal VREF Select for Rank 1 - PSU_DDR_PHY_DX7GCR5_DXREFISELR1 0x4f + * DATX8 0-1 I/O Configuration Register + * (OFFSET, MASK, VALUE) (0XFD081430, 0xFFFFFFFFU ,0x70800000U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL0IOCR_OFFSET, 0xFFFFFFFFU, 0x70800000U); +/*##################################################################### */ - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX7GCR5_RESERVED_7 0x0 + /* + * Register : DX8SL1OSC @ 0XFD081440 - Byte Lane internal VREF Select for Rank 0 - PSU_DDR_PHY_DX7GCR5_DXREFISELR0 0x4f + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL1OSC_RESERVED_31_30 0x0 - DATX8 n General Configuration Register 5 - (OFFSET, MASK, VALUE) (0XFD080E14, 0xFFFFFFFFU ,0x09094F4FU) - RegMask = (DDR_PHY_DX7GCR5_RESERVED_31_MASK | DDR_PHY_DX7GCR5_DXREFISELR3_MASK | DDR_PHY_DX7GCR5_RESERVED_23_MASK | DDR_PHY_DX7GCR5_DXREFISELR2_MASK | DDR_PHY_DX7GCR5_RESERVED_15_MASK | DDR_PHY_DX7GCR5_DXREFISELR1_MASK | DDR_PHY_DX7GCR5_RESERVED_7_MASK | DDR_PHY_DX7GCR5_DXREFISELR0_MASK | 0 ); + * Enable Clock Gating for DX ddr_clk + * PSU_DDR_PHY_DX8SL1OSC_GATEDXRDCLK 0x2 - RegVal = ((0x00000000U << DDR_PHY_DX7GCR5_RESERVED_31_SHIFT - | 0x00000009U << DDR_PHY_DX7GCR5_DXREFISELR3_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR5_RESERVED_23_SHIFT - | 0x00000009U << DDR_PHY_DX7GCR5_DXREFISELR2_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR5_RESERVED_15_SHIFT - | 0x0000004FU << DDR_PHY_DX7GCR5_DXREFISELR1_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR5_RESERVED_7_SHIFT - | 0x0000004FU << DDR_PHY_DX7GCR5_DXREFISELR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX7GCR5_OFFSET ,0xFFFFFFFFU ,0x09094F4FU); - /*############################################################################################################################ */ + * Enable Clock Gating for DX ctl_rd_clk + * PSU_DDR_PHY_DX8SL1OSC_GATEDXDDRCLK 0x2 - /*Register : DX7GCR6 @ 0XFD080E18

+ * Enable Clock Gating for DX ctl_clk + * PSU_DDR_PHY_DX8SL1OSC_GATEDXCTLCLK 0x2 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX7GCR6_RESERVED_31_30 0x0 + * Selects the level to which clocks will be stalled when clock gating is e + * nabled. + * PSU_DDR_PHY_DX8SL1OSC_CLKLEVEL 0x0 - DRAM DQ VREF Select for Rank3 - PSU_DDR_PHY_DX7GCR6_DXDQVREFR3 0x9 + * Loopback Mode + * PSU_DDR_PHY_DX8SL1OSC_LBMODE 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX7GCR6_RESERVED_23_22 0x0 + * Load GSDQS LCDL with 2x the calibrated GSDQSPRD value + * PSU_DDR_PHY_DX8SL1OSC_LBGSDQS 0x0 - DRAM DQ VREF Select for Rank2 - PSU_DDR_PHY_DX7GCR6_DXDQVREFR2 0x9 + * Loopback DQS Gating + * PSU_DDR_PHY_DX8SL1OSC_LBGDQS 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX7GCR6_RESERVED_15_14 0x0 + * Loopback DQS Shift + * PSU_DDR_PHY_DX8SL1OSC_LBDQSS 0x0 - DRAM DQ VREF Select for Rank1 - PSU_DDR_PHY_DX7GCR6_DXDQVREFR1 0x2b + * PHY High-Speed Reset + * PSU_DDR_PHY_DX8SL1OSC_PHYHRST 0x1 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX7GCR6_RESERVED_7_6 0x0 + * PHY FIFO Reset + * PSU_DDR_PHY_DX8SL1OSC_PHYFRST 0x1 - DRAM DQ VREF Select for Rank0 - PSU_DDR_PHY_DX7GCR6_DXDQVREFR0 0x2b + * Delay Line Test Start + * PSU_DDR_PHY_DX8SL1OSC_DLTST 0x0 - DATX8 n General Configuration Register 6 - (OFFSET, MASK, VALUE) (0XFD080E18, 0xFFFFFFFFU ,0x09092B2BU) - RegMask = (DDR_PHY_DX7GCR6_RESERVED_31_30_MASK | DDR_PHY_DX7GCR6_DXDQVREFR3_MASK | DDR_PHY_DX7GCR6_RESERVED_23_22_MASK | DDR_PHY_DX7GCR6_DXDQVREFR2_MASK | DDR_PHY_DX7GCR6_RESERVED_15_14_MASK | DDR_PHY_DX7GCR6_DXDQVREFR1_MASK | DDR_PHY_DX7GCR6_RESERVED_7_6_MASK | DDR_PHY_DX7GCR6_DXDQVREFR0_MASK | 0 ); + * Delay Line Test Mode + * PSU_DDR_PHY_DX8SL1OSC_DLTMODE 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX7GCR6_RESERVED_31_30_SHIFT - | 0x00000009U << DDR_PHY_DX7GCR6_DXDQVREFR3_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR6_RESERVED_23_22_SHIFT - | 0x00000009U << DDR_PHY_DX7GCR6_DXDQVREFR2_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR6_RESERVED_15_14_SHIFT - | 0x0000002BU << DDR_PHY_DX7GCR6_DXDQVREFR1_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR6_RESERVED_7_6_SHIFT - | 0x0000002BU << DDR_PHY_DX7GCR6_DXDQVREFR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX7GCR6_OFFSET ,0xFFFFFFFFU ,0x09092B2BU); - /*############################################################################################################################ */ + * Reserved. Caution, do not write to this register field. + * PSU_DDR_PHY_DX8SL1OSC_RESERVED_12_11 0x3 - /*Register : DX7LCDLR2 @ 0XFD080E88

+ * Oscillator Mode Write-Data Delay Line Select + * PSU_DDR_PHY_DX8SL1OSC_OSCWDDL 0x3 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX7LCDLR2_RESERVED_31_25 0x0 + * Reserved. Caution, do not write to this register field. + * PSU_DDR_PHY_DX8SL1OSC_RESERVED_8_7 0x3 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX7LCDLR2_RESERVED_24_16 0x0 + * Oscillator Mode Write-Leveling Delay Line Select + * PSU_DDR_PHY_DX8SL1OSC_OSCWDL 0x3 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX7LCDLR2_RESERVED_15_9 0x0 + * Oscillator Mode Division + * PSU_DDR_PHY_DX8SL1OSC_OSCDIV 0xf - Read DQS Gating Delay - PSU_DDR_PHY_DX7LCDLR2_DQSGD 0xa + * Oscillator Enable + * PSU_DDR_PHY_DX8SL1OSC_OSCEN 0x0 - DATX8 n Local Calibrated Delay Line Register 2 - (OFFSET, MASK, VALUE) (0XFD080E88, 0xFFFFFFFFU ,0x0000000AU) - RegMask = (DDR_PHY_DX7LCDLR2_RESERVED_31_25_MASK | DDR_PHY_DX7LCDLR2_RESERVED_24_16_MASK | DDR_PHY_DX7LCDLR2_RESERVED_15_9_MASK | DDR_PHY_DX7LCDLR2_DQSGD_MASK | 0 ); + * DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Lo + * opback, and Gated Clock Control Register + * (OFFSET, MASK, VALUE) (0XFD081440, 0xFFFFFFFFU ,0x2A019FFEU) + */ + PSU_Mask_Write(DDR_PHY_DX8SL1OSC_OFFSET, 0xFFFFFFFFU, 0x2A019FFEU); +/*##################################################################### */ - RegVal = ((0x00000000U << DDR_PHY_DX7LCDLR2_RESERVED_31_25_SHIFT - | 0x00000000U << DDR_PHY_DX7LCDLR2_RESERVED_24_16_SHIFT - | 0x00000000U << DDR_PHY_DX7LCDLR2_RESERVED_15_9_SHIFT - | 0x0000000AU << DDR_PHY_DX7LCDLR2_DQSGD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX7LCDLR2_OFFSET ,0xFFFFFFFFU ,0x0000000AU); - /*############################################################################################################################ */ + /* + * Register : DX8SL1PLLCR0 @ 0XFD081444 - /*Register : DX7GTR0 @ 0XFD080EC0

+ * PLL Bypass + * PSU_DDR_PHY_DX8SL1PLLCR0_PLLBYP 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX7GTR0_RESERVED_31_24 0x0 + * PLL Reset + * PSU_DDR_PHY_DX8SL1PLLCR0_PLLRST 0x0 - DQ Write Path Latency Pipeline - PSU_DDR_PHY_DX7GTR0_WDQSL 0x0 + * PLL Power Down + * PSU_DDR_PHY_DX8SL1PLLCR0_PLLPD 0x0 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX7GTR0_RESERVED_23_20 0x0 + * Reference Stop Mode + * PSU_DDR_PHY_DX8SL1PLLCR0_RSTOPM 0x0 - Write Leveling System Latency - PSU_DDR_PHY_DX7GTR0_WLSL 0x2 + * PLL Frequency Select + * PSU_DDR_PHY_DX8SL1PLLCR0_FRQSEL 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX7GTR0_RESERVED_15_13 0x0 + * Relock Mode + * PSU_DDR_PHY_DX8SL1PLLCR0_RLOCKM 0x0 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX7GTR0_RESERVED_12_8 0x0 + * Charge Pump Proportional Current Control + * PSU_DDR_PHY_DX8SL1PLLCR0_CPPC 0x8 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX7GTR0_RESERVED_7_5 0x0 + * Charge Pump Integrating Current Control + * PSU_DDR_PHY_DX8SL1PLLCR0_CPIC 0x0 - DQS Gating System Latency - PSU_DDR_PHY_DX7GTR0_DGSL 0x0 + * Gear Shift + * PSU_DDR_PHY_DX8SL1PLLCR0_GSHIFT 0x0 - DATX8 n General Timing Register 0 - (OFFSET, MASK, VALUE) (0XFD080EC0, 0xFFFFFFFFU ,0x00020000U) - RegMask = (DDR_PHY_DX7GTR0_RESERVED_31_24_MASK | DDR_PHY_DX7GTR0_WDQSL_MASK | DDR_PHY_DX7GTR0_RESERVED_23_20_MASK | DDR_PHY_DX7GTR0_WLSL_MASK | DDR_PHY_DX7GTR0_RESERVED_15_13_MASK | DDR_PHY_DX7GTR0_RESERVED_12_8_MASK | DDR_PHY_DX7GTR0_RESERVED_7_5_MASK | DDR_PHY_DX7GTR0_DGSL_MASK | 0 ); + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL1PLLCR0_RESERVED_11_9 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX7GTR0_RESERVED_31_24_SHIFT - | 0x00000000U << DDR_PHY_DX7GTR0_WDQSL_SHIFT - | 0x00000000U << DDR_PHY_DX7GTR0_RESERVED_23_20_SHIFT - | 0x00000002U << DDR_PHY_DX7GTR0_WLSL_SHIFT - | 0x00000000U << DDR_PHY_DX7GTR0_RESERVED_15_13_SHIFT - | 0x00000000U << DDR_PHY_DX7GTR0_RESERVED_12_8_SHIFT - | 0x00000000U << DDR_PHY_DX7GTR0_RESERVED_7_5_SHIFT - | 0x00000000U << DDR_PHY_DX7GTR0_DGSL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX7GTR0_OFFSET ,0xFFFFFFFFU ,0x00020000U); - /*############################################################################################################################ */ + * Analog Test Enable (ATOEN) + * PSU_DDR_PHY_DX8SL1PLLCR0_ATOEN 0x0 - /*Register : DX8GCR0 @ 0XFD080F00

+ * Analog Test Control + * PSU_DDR_PHY_DX8SL1PLLCR0_ATC 0x0 - Calibration Bypass - PSU_DDR_PHY_DX8GCR0_CALBYP 0x0 + * Digital Test Control + * PSU_DDR_PHY_DX8SL1PLLCR0_DTC 0x0 - Master Delay Line Enable - PSU_DDR_PHY_DX8GCR0_MDLEN 0x1 + * DAXT8 0-1 PLL Control Register 0 + * (OFFSET, MASK, VALUE) (0XFD081444, 0xFFFFFFFFU ,0x01100000U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL1PLLCR0_OFFSET, + 0xFFFFFFFFU, 0x01100000U); +/*##################################################################### */ - Configurable ODT(TE) Phase Shift - PSU_DDR_PHY_DX8GCR0_CODTSHFT 0x0 + /* + * Register : DX8SL1DQSCTL @ 0XFD08145C - DQS Duty Cycle Correction - PSU_DDR_PHY_DX8GCR0_DQSDCC 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25 0x0 - Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY - PSU_DDR_PHY_DX8GCR0_RDDLY 0x8 + * Read Path Rise-to-Rise Mode + * PSU_DDR_PHY_DX8SL1DQSCTL_RRRMODE 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8GCR0_RESERVED_19_14 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22 0x0 - DQSNSE Power Down Receiver - PSU_DDR_PHY_DX8GCR0_DQSNSEPDR 0x0 + * Write Path Rise-to-Rise Mode + * PSU_DDR_PHY_DX8SL1DQSCTL_WRRMODE 0x1 - DQSSE Power Down Receiver - PSU_DDR_PHY_DX8GCR0_DQSSEPDR 0x0 + * DQS Gate Extension + * PSU_DDR_PHY_DX8SL1DQSCTL_DQSGX 0x0 - RTT On Additive Latency - PSU_DDR_PHY_DX8GCR0_RTTOAL 0x0 + * Low Power PLL Power Down + * PSU_DDR_PHY_DX8SL1DQSCTL_LPPLLPD 0x1 - RTT Output Hold - PSU_DDR_PHY_DX8GCR0_RTTOH 0x3 + * Low Power I/O Power Down + * PSU_DDR_PHY_DX8SL1DQSCTL_LPIOPD 0x1 - Configurable PDR Phase Shift - PSU_DDR_PHY_DX8GCR0_CPDRSHFT 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15 0x0 - DQSR Power Down - PSU_DDR_PHY_DX8GCR0_DQSRPD 0x0 + * QS Counter Enable + * PSU_DDR_PHY_DX8SL1DQSCTL_QSCNTEN 0x1 - DQSG Power Down Receiver - PSU_DDR_PHY_DX8GCR0_DQSGPDR 0x1 + * Unused DQ I/O Mode + * PSU_DDR_PHY_DX8SL1DQSCTL_UDQIOM 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8GCR0_RESERVED_4 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10 0x0 - DQSG On-Die Termination - PSU_DDR_PHY_DX8GCR0_DQSGODT 0x0 + * Data Slew Rate + * PSU_DDR_PHY_DX8SL1DQSCTL_DXSR 0x3 - DQSG Output Enable - PSU_DDR_PHY_DX8GCR0_DQSGOE 0x1 + * DQS_N Resistor + * PSU_DDR_PHY_DX8SL1DQSCTL_DQSNRES 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8GCR0_RESERVED_1_0 0x0 + * DQS Resistor + * PSU_DDR_PHY_DX8SL1DQSCTL_DQSRES 0x0 - DATX8 n General Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD080F00, 0xFFFFFFFFU ,0x40800624U) - RegMask = (DDR_PHY_DX8GCR0_CALBYP_MASK | DDR_PHY_DX8GCR0_MDLEN_MASK | DDR_PHY_DX8GCR0_CODTSHFT_MASK | DDR_PHY_DX8GCR0_DQSDCC_MASK | DDR_PHY_DX8GCR0_RDDLY_MASK | DDR_PHY_DX8GCR0_RESERVED_19_14_MASK | DDR_PHY_DX8GCR0_DQSNSEPDR_MASK | DDR_PHY_DX8GCR0_DQSSEPDR_MASK | DDR_PHY_DX8GCR0_RTTOAL_MASK | DDR_PHY_DX8GCR0_RTTOH_MASK | DDR_PHY_DX8GCR0_CPDRSHFT_MASK | DDR_PHY_DX8GCR0_DQSRPD_MASK | DDR_PHY_DX8GCR0_DQSGPDR_MASK | DDR_PHY_DX8GCR0_RESERVED_4_MASK | DDR_PHY_DX8GCR0_DQSGODT_MASK | DDR_PHY_DX8GCR0_DQSGOE_MASK | DDR_PHY_DX8GCR0_RESERVED_1_0_MASK | 0 ); + * DATX8 0-1 DQS Control Register + * (OFFSET, MASK, VALUE) (0XFD08145C, 0xFFFFFFFFU ,0x01264300U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL1DQSCTL_OFFSET, + 0xFFFFFFFFU, 0x01264300U); +/*##################################################################### */ - RegVal = ((0x00000000U << DDR_PHY_DX8GCR0_CALBYP_SHIFT - | 0x00000001U << DDR_PHY_DX8GCR0_MDLEN_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR0_CODTSHFT_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR0_DQSDCC_SHIFT - | 0x00000008U << DDR_PHY_DX8GCR0_RDDLY_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR0_RESERVED_19_14_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR0_DQSNSEPDR_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR0_DQSSEPDR_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR0_RTTOAL_SHIFT - | 0x00000003U << DDR_PHY_DX8GCR0_RTTOH_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR0_CPDRSHFT_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR0_DQSRPD_SHIFT - | 0x00000001U << DDR_PHY_DX8GCR0_DQSGPDR_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR0_RESERVED_4_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR0_DQSGODT_SHIFT - | 0x00000001U << DDR_PHY_DX8GCR0_DQSGOE_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR0_RESERVED_1_0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8GCR0_OFFSET ,0xFFFFFFFFU ,0x40800624U); - /*############################################################################################################################ */ + /* + * Register : DX8SL1DXCTL2 @ 0XFD08146C - /*Register : DX8GCR1 @ 0XFD080F04

+ * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24 0x0 - Enables the PDR mode for DQ[7:0] - PSU_DDR_PHY_DX8GCR1_DXPDRMODE 0x0 + * Configurable Read Data Enable + * PSU_DDR_PHY_DX8SL1DXCTL2_CRDEN 0x0 - Reserved. Returns zeroes on reads. - PSU_DDR_PHY_DX8GCR1_RESERVED_15 0x0 + * OX Extension during Post-amble + * PSU_DDR_PHY_DX8SL1DXCTL2_POSOEX 0x0 - Select the delayed or non-delayed read data strobe # - PSU_DDR_PHY_DX8GCR1_QSNSEL 0x1 + * OE Extension during Pre-amble + * PSU_DDR_PHY_DX8SL1DXCTL2_PREOEX 0x1 - Select the delayed or non-delayed read data strobe - PSU_DDR_PHY_DX8GCR1_QSSEL 0x1 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_17 0x0 - Enables Read Data Strobe in a byte lane - PSU_DDR_PHY_DX8GCR1_OEEN 0x1 + * I/O Assisted Gate Select + * PSU_DDR_PHY_DX8SL1DXCTL2_IOAG 0x0 - Enables PDR in a byte lane - PSU_DDR_PHY_DX8GCR1_PDREN 0x1 + * I/O Loopback Select + * PSU_DDR_PHY_DX8SL1DXCTL2_IOLB 0x0 - Enables ODT/TE in a byte lane - PSU_DDR_PHY_DX8GCR1_TEEN 0x1 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13 0x0 - Enables Write Data strobe in a byte lane - PSU_DDR_PHY_DX8GCR1_DSEN 0x1 + * Low Power Wakeup Threshold + * PSU_DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH 0xc - Enables DM pin in a byte lane - PSU_DDR_PHY_DX8GCR1_DMEN 0x1 + * Read Data Bus Inversion Enable + * PSU_DDR_PHY_DX8SL1DXCTL2_RDBI 0x0 - Enables DQ corresponding to each bit in a byte - PSU_DDR_PHY_DX8GCR1_DQEN 0x0 + * Write Data Bus Inversion Enable + * PSU_DDR_PHY_DX8SL1DXCTL2_WDBI 0x0 - DATX8 n General Configuration Register 1 - (OFFSET, MASK, VALUE) (0XFD080F04, 0xFFFFFFFFU ,0x00007F00U) - RegMask = (DDR_PHY_DX8GCR1_DXPDRMODE_MASK | DDR_PHY_DX8GCR1_RESERVED_15_MASK | DDR_PHY_DX8GCR1_QSNSEL_MASK | DDR_PHY_DX8GCR1_QSSEL_MASK | DDR_PHY_DX8GCR1_OEEN_MASK | DDR_PHY_DX8GCR1_PDREN_MASK | DDR_PHY_DX8GCR1_TEEN_MASK | DDR_PHY_DX8GCR1_DSEN_MASK | DDR_PHY_DX8GCR1_DMEN_MASK | DDR_PHY_DX8GCR1_DQEN_MASK | 0 ); + * PUB Read FIFO Bypass + * PSU_DDR_PHY_DX8SL1DXCTL2_PRFBYP 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX8GCR1_DXPDRMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR1_RESERVED_15_SHIFT - | 0x00000001U << DDR_PHY_DX8GCR1_QSNSEL_SHIFT - | 0x00000001U << DDR_PHY_DX8GCR1_QSSEL_SHIFT - | 0x00000001U << DDR_PHY_DX8GCR1_OEEN_SHIFT - | 0x00000001U << DDR_PHY_DX8GCR1_PDREN_SHIFT - | 0x00000001U << DDR_PHY_DX8GCR1_TEEN_SHIFT - | 0x00000001U << DDR_PHY_DX8GCR1_DSEN_SHIFT - | 0x00000001U << DDR_PHY_DX8GCR1_DMEN_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR1_DQEN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8GCR1_OFFSET ,0xFFFFFFFFU ,0x00007F00U); - /*############################################################################################################################ */ + * DATX8 Receive FIFO Read Mode + * PSU_DDR_PHY_DX8SL1DXCTL2_RDMODE 0x0 - /*Register : DX8GCR4 @ 0XFD080F10

+ * Disables the Read FIFO Reset + * PSU_DDR_PHY_DX8SL1DXCTL2_DISRST 0x0 - Byte lane VREF IOM (Used only by D4MU IOs) - PSU_DDR_PHY_DX8GCR4_RESERVED_31_29 0x0 + * Read DQS Gate I/O Loopback + * PSU_DDR_PHY_DX8SL1DXCTL2_DQSGLB 0x0 - Byte Lane VREF Pad Enable - PSU_DDR_PHY_DX8GCR4_DXREFPEN 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_0 0x0 - Byte Lane Internal VREF Enable - PSU_DDR_PHY_DX8GCR4_DXREFEEN 0x3 + * DATX8 0-1 DX Control Register 2 + * (OFFSET, MASK, VALUE) (0XFD08146C, 0xFFFFFFFFU ,0x00041800U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL1DXCTL2_OFFSET, + 0xFFFFFFFFU, 0x00041800U); +/*##################################################################### */ - Byte Lane Single-End VREF Enable - PSU_DDR_PHY_DX8GCR4_DXREFSEN 0x1 + /* + * Register : DX8SL1IOCR @ 0XFD081470 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX8GCR4_RESERVED_24 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL1IOCR_RESERVED_31 0x0 - External VREF generator REFSEL range select - PSU_DDR_PHY_DX8GCR4_DXREFESELRANGE 0x0 + * PVREF_DAC REFSEL range select + * PSU_DDR_PHY_DX8SL1IOCR_DXDACRANGE 0x7 - Byte Lane External VREF Select - PSU_DDR_PHY_DX8GCR4_DXREFESEL 0x0 + * IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring + * PSU_DDR_PHY_DX8SL1IOCR_DXVREFIOM 0x0 - Single ended VREF generator REFSEL range select - PSU_DDR_PHY_DX8GCR4_DXREFSSELRANGE 0x1 + * DX IO Mode + * PSU_DDR_PHY_DX8SL1IOCR_DXIOM 0x2 - Byte Lane Single-End VREF Select - PSU_DDR_PHY_DX8GCR4_DXREFSSEL 0x30 + * DX IO Transmitter Mode + * PSU_DDR_PHY_DX8SL1IOCR_DXTXM 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX8GCR4_RESERVED_7_6 0x0 + * DX IO Receiver Mode + * PSU_DDR_PHY_DX8SL1IOCR_DXRXM 0x0 - VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. - PSU_DDR_PHY_DX8GCR4_DXREFIEN 0xf + * DATX8 0-1 I/O Configuration Register + * (OFFSET, MASK, VALUE) (0XFD081470, 0xFFFFFFFFU ,0x70800000U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL1IOCR_OFFSET, 0xFFFFFFFFU, 0x70800000U); +/*##################################################################### */ - VRMON control for DQ IO (Single Ended) buffers of a byte lane. - PSU_DDR_PHY_DX8GCR4_DXREFIMON 0x0 + /* + * Register : DX8SL2OSC @ 0XFD081480 - DATX8 n General Configuration Register 4 - (OFFSET, MASK, VALUE) (0XFD080F10, 0xFFFFFFFFU ,0x0E00B03CU) - RegMask = (DDR_PHY_DX8GCR4_RESERVED_31_29_MASK | DDR_PHY_DX8GCR4_DXREFPEN_MASK | DDR_PHY_DX8GCR4_DXREFEEN_MASK | DDR_PHY_DX8GCR4_DXREFSEN_MASK | DDR_PHY_DX8GCR4_RESERVED_24_MASK | DDR_PHY_DX8GCR4_DXREFESELRANGE_MASK | DDR_PHY_DX8GCR4_DXREFESEL_MASK | DDR_PHY_DX8GCR4_DXREFSSELRANGE_MASK | DDR_PHY_DX8GCR4_DXREFSSEL_MASK | DDR_PHY_DX8GCR4_RESERVED_7_6_MASK | DDR_PHY_DX8GCR4_DXREFIEN_MASK | DDR_PHY_DX8GCR4_DXREFIMON_MASK | 0 ); + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL2OSC_RESERVED_31_30 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX8GCR4_RESERVED_31_29_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR4_DXREFPEN_SHIFT - | 0x00000003U << DDR_PHY_DX8GCR4_DXREFEEN_SHIFT - | 0x00000001U << DDR_PHY_DX8GCR4_DXREFSEN_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR4_RESERVED_24_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR4_DXREFESELRANGE_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR4_DXREFESEL_SHIFT - | 0x00000001U << DDR_PHY_DX8GCR4_DXREFSSELRANGE_SHIFT - | 0x00000030U << DDR_PHY_DX8GCR4_DXREFSSEL_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR4_RESERVED_7_6_SHIFT - | 0x0000000FU << DDR_PHY_DX8GCR4_DXREFIEN_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR4_DXREFIMON_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8GCR4_OFFSET ,0xFFFFFFFFU ,0x0E00B03CU); - /*############################################################################################################################ */ + * Enable Clock Gating for DX ddr_clk + * PSU_DDR_PHY_DX8SL2OSC_GATEDXRDCLK 0x2 - /*Register : DX8GCR5 @ 0XFD080F14

+ * Enable Clock Gating for DX ctl_rd_clk + * PSU_DDR_PHY_DX8SL2OSC_GATEDXDDRCLK 0x2 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX8GCR5_RESERVED_31 0x0 + * Enable Clock Gating for DX ctl_clk + * PSU_DDR_PHY_DX8SL2OSC_GATEDXCTLCLK 0x2 - Byte Lane internal VREF Select for Rank 3 - PSU_DDR_PHY_DX8GCR5_DXREFISELR3 0x9 + * Selects the level to which clocks will be stalled when clock gating is e + * nabled. + * PSU_DDR_PHY_DX8SL2OSC_CLKLEVEL 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX8GCR5_RESERVED_23 0x0 + * Loopback Mode + * PSU_DDR_PHY_DX8SL2OSC_LBMODE 0x0 - Byte Lane internal VREF Select for Rank 2 - PSU_DDR_PHY_DX8GCR5_DXREFISELR2 0x9 + * Load GSDQS LCDL with 2x the calibrated GSDQSPRD value + * PSU_DDR_PHY_DX8SL2OSC_LBGSDQS 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX8GCR5_RESERVED_15 0x0 + * Loopback DQS Gating + * PSU_DDR_PHY_DX8SL2OSC_LBGDQS 0x0 - Byte Lane internal VREF Select for Rank 1 - PSU_DDR_PHY_DX8GCR5_DXREFISELR1 0x4f + * Loopback DQS Shift + * PSU_DDR_PHY_DX8SL2OSC_LBDQSS 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX8GCR5_RESERVED_7 0x0 + * PHY High-Speed Reset + * PSU_DDR_PHY_DX8SL2OSC_PHYHRST 0x1 - Byte Lane internal VREF Select for Rank 0 - PSU_DDR_PHY_DX8GCR5_DXREFISELR0 0x4f + * PHY FIFO Reset + * PSU_DDR_PHY_DX8SL2OSC_PHYFRST 0x1 - DATX8 n General Configuration Register 5 - (OFFSET, MASK, VALUE) (0XFD080F14, 0xFFFFFFFFU ,0x09094F4FU) - RegMask = (DDR_PHY_DX8GCR5_RESERVED_31_MASK | DDR_PHY_DX8GCR5_DXREFISELR3_MASK | DDR_PHY_DX8GCR5_RESERVED_23_MASK | DDR_PHY_DX8GCR5_DXREFISELR2_MASK | DDR_PHY_DX8GCR5_RESERVED_15_MASK | DDR_PHY_DX8GCR5_DXREFISELR1_MASK | DDR_PHY_DX8GCR5_RESERVED_7_MASK | DDR_PHY_DX8GCR5_DXREFISELR0_MASK | 0 ); + * Delay Line Test Start + * PSU_DDR_PHY_DX8SL2OSC_DLTST 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX8GCR5_RESERVED_31_SHIFT - | 0x00000009U << DDR_PHY_DX8GCR5_DXREFISELR3_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR5_RESERVED_23_SHIFT - | 0x00000009U << DDR_PHY_DX8GCR5_DXREFISELR2_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR5_RESERVED_15_SHIFT - | 0x0000004FU << DDR_PHY_DX8GCR5_DXREFISELR1_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR5_RESERVED_7_SHIFT - | 0x0000004FU << DDR_PHY_DX8GCR5_DXREFISELR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8GCR5_OFFSET ,0xFFFFFFFFU ,0x09094F4FU); - /*############################################################################################################################ */ + * Delay Line Test Mode + * PSU_DDR_PHY_DX8SL2OSC_DLTMODE 0x0 - /*Register : DX8GCR6 @ 0XFD080F18

+ * Reserved. Caution, do not write to this register field. + * PSU_DDR_PHY_DX8SL2OSC_RESERVED_12_11 0x3 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX8GCR6_RESERVED_31_30 0x0 + * Oscillator Mode Write-Data Delay Line Select + * PSU_DDR_PHY_DX8SL2OSC_OSCWDDL 0x3 - DRAM DQ VREF Select for Rank3 - PSU_DDR_PHY_DX8GCR6_DXDQVREFR3 0x9 + * Reserved. Caution, do not write to this register field. + * PSU_DDR_PHY_DX8SL2OSC_RESERVED_8_7 0x3 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX8GCR6_RESERVED_23_22 0x0 + * Oscillator Mode Write-Leveling Delay Line Select + * PSU_DDR_PHY_DX8SL2OSC_OSCWDL 0x3 - DRAM DQ VREF Select for Rank2 - PSU_DDR_PHY_DX8GCR6_DXDQVREFR2 0x9 + * Oscillator Mode Division + * PSU_DDR_PHY_DX8SL2OSC_OSCDIV 0xf - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX8GCR6_RESERVED_15_14 0x0 + * Oscillator Enable + * PSU_DDR_PHY_DX8SL2OSC_OSCEN 0x0 - DRAM DQ VREF Select for Rank1 - PSU_DDR_PHY_DX8GCR6_DXDQVREFR1 0x2b + * DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Lo + * opback, and Gated Clock Control Register + * (OFFSET, MASK, VALUE) (0XFD081480, 0xFFFFFFFFU ,0x2A019FFEU) + */ + PSU_Mask_Write(DDR_PHY_DX8SL2OSC_OFFSET, 0xFFFFFFFFU, 0x2A019FFEU); +/*##################################################################### */ - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX8GCR6_RESERVED_7_6 0x0 + /* + * Register : DX8SL2PLLCR0 @ 0XFD081484 - DRAM DQ VREF Select for Rank0 - PSU_DDR_PHY_DX8GCR6_DXDQVREFR0 0x2b + * PLL Bypass + * PSU_DDR_PHY_DX8SL2PLLCR0_PLLBYP 0x0 - DATX8 n General Configuration Register 6 - (OFFSET, MASK, VALUE) (0XFD080F18, 0xFFFFFFFFU ,0x09092B2BU) - RegMask = (DDR_PHY_DX8GCR6_RESERVED_31_30_MASK | DDR_PHY_DX8GCR6_DXDQVREFR3_MASK | DDR_PHY_DX8GCR6_RESERVED_23_22_MASK | DDR_PHY_DX8GCR6_DXDQVREFR2_MASK | DDR_PHY_DX8GCR6_RESERVED_15_14_MASK | DDR_PHY_DX8GCR6_DXDQVREFR1_MASK | DDR_PHY_DX8GCR6_RESERVED_7_6_MASK | DDR_PHY_DX8GCR6_DXDQVREFR0_MASK | 0 ); + * PLL Reset + * PSU_DDR_PHY_DX8SL2PLLCR0_PLLRST 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX8GCR6_RESERVED_31_30_SHIFT - | 0x00000009U << DDR_PHY_DX8GCR6_DXDQVREFR3_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR6_RESERVED_23_22_SHIFT - | 0x00000009U << DDR_PHY_DX8GCR6_DXDQVREFR2_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR6_RESERVED_15_14_SHIFT - | 0x0000002BU << DDR_PHY_DX8GCR6_DXDQVREFR1_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR6_RESERVED_7_6_SHIFT - | 0x0000002BU << DDR_PHY_DX8GCR6_DXDQVREFR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8GCR6_OFFSET ,0xFFFFFFFFU ,0x09092B2BU); - /*############################################################################################################################ */ + * PLL Power Down + * PSU_DDR_PHY_DX8SL2PLLCR0_PLLPD 0x0 - /*Register : DX8LCDLR2 @ 0XFD080F88

+ * Reference Stop Mode + * PSU_DDR_PHY_DX8SL2PLLCR0_RSTOPM 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8LCDLR2_RESERVED_31_25 0x0 + * PLL Frequency Select + * PSU_DDR_PHY_DX8SL2PLLCR0_FRQSEL 0x1 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX8LCDLR2_RESERVED_24_16 0x0 + * Relock Mode + * PSU_DDR_PHY_DX8SL2PLLCR0_RLOCKM 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8LCDLR2_RESERVED_15_9 0x0 + * Charge Pump Proportional Current Control + * PSU_DDR_PHY_DX8SL2PLLCR0_CPPC 0x8 - Read DQS Gating Delay - PSU_DDR_PHY_DX8LCDLR2_DQSGD 0x0 + * Charge Pump Integrating Current Control + * PSU_DDR_PHY_DX8SL2PLLCR0_CPIC 0x0 - DATX8 n Local Calibrated Delay Line Register 2 - (OFFSET, MASK, VALUE) (0XFD080F88, 0xFFFFFFFFU ,0x00000000U) - RegMask = (DDR_PHY_DX8LCDLR2_RESERVED_31_25_MASK | DDR_PHY_DX8LCDLR2_RESERVED_24_16_MASK | DDR_PHY_DX8LCDLR2_RESERVED_15_9_MASK | DDR_PHY_DX8LCDLR2_DQSGD_MASK | 0 ); + * Gear Shift + * PSU_DDR_PHY_DX8SL2PLLCR0_GSHIFT 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX8LCDLR2_RESERVED_31_25_SHIFT - | 0x00000000U << DDR_PHY_DX8LCDLR2_RESERVED_24_16_SHIFT - | 0x00000000U << DDR_PHY_DX8LCDLR2_RESERVED_15_9_SHIFT - | 0x00000000U << DDR_PHY_DX8LCDLR2_DQSGD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8LCDLR2_OFFSET ,0xFFFFFFFFU ,0x00000000U); - /*############################################################################################################################ */ + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL2PLLCR0_RESERVED_11_9 0x0 - /*Register : DX8GTR0 @ 0XFD080FC0

+ * Analog Test Enable (ATOEN) + * PSU_DDR_PHY_DX8SL2PLLCR0_ATOEN 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8GTR0_RESERVED_31_24 0x0 + * Analog Test Control + * PSU_DDR_PHY_DX8SL2PLLCR0_ATC 0x0 - DQ Write Path Latency Pipeline - PSU_DDR_PHY_DX8GTR0_WDQSL 0x0 + * Digital Test Control + * PSU_DDR_PHY_DX8SL2PLLCR0_DTC 0x0 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX8GTR0_RESERVED_23_20 0x0 + * DAXT8 0-1 PLL Control Register 0 + * (OFFSET, MASK, VALUE) (0XFD081484, 0xFFFFFFFFU ,0x01100000U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL2PLLCR0_OFFSET, + 0xFFFFFFFFU, 0x01100000U); +/*##################################################################### */ - Write Leveling System Latency - PSU_DDR_PHY_DX8GTR0_WLSL 0x2 + /* + * Register : DX8SL2DQSCTL @ 0XFD08149C - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8GTR0_RESERVED_15_13 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25 0x0 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX8GTR0_RESERVED_12_8 0x0 + * Read Path Rise-to-Rise Mode + * PSU_DDR_PHY_DX8SL2DQSCTL_RRRMODE 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8GTR0_RESERVED_7_5 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22 0x0 - DQS Gating System Latency - PSU_DDR_PHY_DX8GTR0_DGSL 0x0 + * Write Path Rise-to-Rise Mode + * PSU_DDR_PHY_DX8SL2DQSCTL_WRRMODE 0x1 - DATX8 n General Timing Register 0 - (OFFSET, MASK, VALUE) (0XFD080FC0, 0xFFFFFFFFU ,0x00020000U) - RegMask = (DDR_PHY_DX8GTR0_RESERVED_31_24_MASK | DDR_PHY_DX8GTR0_WDQSL_MASK | DDR_PHY_DX8GTR0_RESERVED_23_20_MASK | DDR_PHY_DX8GTR0_WLSL_MASK | DDR_PHY_DX8GTR0_RESERVED_15_13_MASK | DDR_PHY_DX8GTR0_RESERVED_12_8_MASK | DDR_PHY_DX8GTR0_RESERVED_7_5_MASK | DDR_PHY_DX8GTR0_DGSL_MASK | 0 ); + * DQS Gate Extension + * PSU_DDR_PHY_DX8SL2DQSCTL_DQSGX 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX8GTR0_RESERVED_31_24_SHIFT - | 0x00000000U << DDR_PHY_DX8GTR0_WDQSL_SHIFT - | 0x00000000U << DDR_PHY_DX8GTR0_RESERVED_23_20_SHIFT - | 0x00000002U << DDR_PHY_DX8GTR0_WLSL_SHIFT - | 0x00000000U << DDR_PHY_DX8GTR0_RESERVED_15_13_SHIFT - | 0x00000000U << DDR_PHY_DX8GTR0_RESERVED_12_8_SHIFT - | 0x00000000U << DDR_PHY_DX8GTR0_RESERVED_7_5_SHIFT - | 0x00000000U << DDR_PHY_DX8GTR0_DGSL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8GTR0_OFFSET ,0xFFFFFFFFU ,0x00020000U); - /*############################################################################################################################ */ + * Low Power PLL Power Down + * PSU_DDR_PHY_DX8SL2DQSCTL_LPPLLPD 0x1 - /*Register : DX8SL0OSC @ 0XFD081400

+ * Low Power I/O Power Down + * PSU_DDR_PHY_DX8SL2DQSCTL_LPIOPD 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL0OSC_RESERVED_31_30 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15 0x0 - Enable Clock Gating for DX ddr_clk - PSU_DDR_PHY_DX8SL0OSC_GATEDXRDCLK 0x2 + * QS Counter Enable + * PSU_DDR_PHY_DX8SL2DQSCTL_QSCNTEN 0x1 - Enable Clock Gating for DX ctl_rd_clk - PSU_DDR_PHY_DX8SL0OSC_GATEDXDDRCLK 0x2 + * Unused DQ I/O Mode + * PSU_DDR_PHY_DX8SL2DQSCTL_UDQIOM 0x0 - Enable Clock Gating for DX ctl_clk - PSU_DDR_PHY_DX8SL0OSC_GATEDXCTLCLK 0x2 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10 0x0 - Selects the level to which clocks will be stalled when clock gating is enabled. - PSU_DDR_PHY_DX8SL0OSC_CLKLEVEL 0x0 + * Data Slew Rate + * PSU_DDR_PHY_DX8SL2DQSCTL_DXSR 0x3 - Loopback Mode - PSU_DDR_PHY_DX8SL0OSC_LBMODE 0x0 + * DQS_N Resistor + * PSU_DDR_PHY_DX8SL2DQSCTL_DQSNRES 0x0 - Load GSDQS LCDL with 2x the calibrated GSDQSPRD value - PSU_DDR_PHY_DX8SL0OSC_LBGSDQS 0x0 + * DQS Resistor + * PSU_DDR_PHY_DX8SL2DQSCTL_DQSRES 0x0 - Loopback DQS Gating - PSU_DDR_PHY_DX8SL0OSC_LBGDQS 0x0 + * DATX8 0-1 DQS Control Register + * (OFFSET, MASK, VALUE) (0XFD08149C, 0xFFFFFFFFU ,0x01264300U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL2DQSCTL_OFFSET, + 0xFFFFFFFFU, 0x01264300U); +/*##################################################################### */ - Loopback DQS Shift - PSU_DDR_PHY_DX8SL0OSC_LBDQSS 0x0 + /* + * Register : DX8SL2DXCTL2 @ 0XFD0814AC - PHY High-Speed Reset - PSU_DDR_PHY_DX8SL0OSC_PHYHRST 0x1 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24 0x0 - PHY FIFO Reset - PSU_DDR_PHY_DX8SL0OSC_PHYFRST 0x1 + * Configurable Read Data Enable + * PSU_DDR_PHY_DX8SL2DXCTL2_CRDEN 0x0 - Delay Line Test Start - PSU_DDR_PHY_DX8SL0OSC_DLTST 0x0 + * OX Extension during Post-amble + * PSU_DDR_PHY_DX8SL2DXCTL2_POSOEX 0x0 - Delay Line Test Mode - PSU_DDR_PHY_DX8SL0OSC_DLTMODE 0x0 + * OE Extension during Pre-amble + * PSU_DDR_PHY_DX8SL2DXCTL2_PREOEX 0x1 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX8SL0OSC_RESERVED_12_11 0x3 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_17 0x0 - Oscillator Mode Write-Data Delay Line Select - PSU_DDR_PHY_DX8SL0OSC_OSCWDDL 0x3 + * I/O Assisted Gate Select + * PSU_DDR_PHY_DX8SL2DXCTL2_IOAG 0x0 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX8SL0OSC_RESERVED_8_7 0x3 + * I/O Loopback Select + * PSU_DDR_PHY_DX8SL2DXCTL2_IOLB 0x0 - Oscillator Mode Write-Leveling Delay Line Select - PSU_DDR_PHY_DX8SL0OSC_OSCWDL 0x3 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13 0x0 - Oscillator Mode Division - PSU_DDR_PHY_DX8SL0OSC_OSCDIV 0xf + * Low Power Wakeup Threshold + * PSU_DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH 0xc - Oscillator Enable - PSU_DDR_PHY_DX8SL0OSC_OSCEN 0x0 + * Read Data Bus Inversion Enable + * PSU_DDR_PHY_DX8SL2DXCTL2_RDBI 0x0 - DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register - (OFFSET, MASK, VALUE) (0XFD081400, 0xFFFFFFFFU ,0x2A019FFEU) - RegMask = (DDR_PHY_DX8SL0OSC_RESERVED_31_30_MASK | DDR_PHY_DX8SL0OSC_GATEDXRDCLK_MASK | DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_MASK | DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_MASK | DDR_PHY_DX8SL0OSC_CLKLEVEL_MASK | DDR_PHY_DX8SL0OSC_LBMODE_MASK | DDR_PHY_DX8SL0OSC_LBGSDQS_MASK | DDR_PHY_DX8SL0OSC_LBGDQS_MASK | DDR_PHY_DX8SL0OSC_LBDQSS_MASK | DDR_PHY_DX8SL0OSC_PHYHRST_MASK | DDR_PHY_DX8SL0OSC_PHYFRST_MASK | DDR_PHY_DX8SL0OSC_DLTST_MASK | DDR_PHY_DX8SL0OSC_DLTMODE_MASK | DDR_PHY_DX8SL0OSC_RESERVED_12_11_MASK | DDR_PHY_DX8SL0OSC_OSCWDDL_MASK | DDR_PHY_DX8SL0OSC_RESERVED_8_7_MASK | DDR_PHY_DX8SL0OSC_OSCWDL_MASK | DDR_PHY_DX8SL0OSC_OSCDIV_MASK | DDR_PHY_DX8SL0OSC_OSCEN_MASK | 0 ); + * Write Data Bus Inversion Enable + * PSU_DDR_PHY_DX8SL2DXCTL2_WDBI 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX8SL0OSC_RESERVED_31_30_SHIFT - | 0x00000002U << DDR_PHY_DX8SL0OSC_GATEDXRDCLK_SHIFT - | 0x00000002U << DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_SHIFT - | 0x00000002U << DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0OSC_CLKLEVEL_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0OSC_LBMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0OSC_LBGSDQS_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0OSC_LBGDQS_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0OSC_LBDQSS_SHIFT - | 0x00000001U << DDR_PHY_DX8SL0OSC_PHYHRST_SHIFT - | 0x00000001U << DDR_PHY_DX8SL0OSC_PHYFRST_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0OSC_DLTST_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0OSC_DLTMODE_SHIFT - | 0x00000003U << DDR_PHY_DX8SL0OSC_RESERVED_12_11_SHIFT - | 0x00000003U << DDR_PHY_DX8SL0OSC_OSCWDDL_SHIFT - | 0x00000003U << DDR_PHY_DX8SL0OSC_RESERVED_8_7_SHIFT - | 0x00000003U << DDR_PHY_DX8SL0OSC_OSCWDL_SHIFT - | 0x0000000FU << DDR_PHY_DX8SL0OSC_OSCDIV_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0OSC_OSCEN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8SL0OSC_OFFSET ,0xFFFFFFFFU ,0x2A019FFEU); - /*############################################################################################################################ */ + * PUB Read FIFO Bypass + * PSU_DDR_PHY_DX8SL2DXCTL2_PRFBYP 0x0 - /*Register : DX8SL0DQSCTL @ 0XFD08141C

+ * DATX8 Receive FIFO Read Mode + * PSU_DDR_PHY_DX8SL2DXCTL2_RDMODE 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25 0x0 + * Disables the Read FIFO Reset + * PSU_DDR_PHY_DX8SL2DXCTL2_DISRST 0x0 - Read Path Rise-to-Rise Mode - PSU_DDR_PHY_DX8SL0DQSCTL_RRRMODE 0x1 + * Read DQS Gate I/O Loopback + * PSU_DDR_PHY_DX8SL2DXCTL2_DQSGLB 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_0 0x0 - Write Path Rise-to-Rise Mode - PSU_DDR_PHY_DX8SL0DQSCTL_WRRMODE 0x1 + * DATX8 0-1 DX Control Register 2 + * (OFFSET, MASK, VALUE) (0XFD0814AC, 0xFFFFFFFFU ,0x00041800U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL2DXCTL2_OFFSET, + 0xFFFFFFFFU, 0x00041800U); +/*##################################################################### */ - DQS Gate Extension - PSU_DDR_PHY_DX8SL0DQSCTL_DQSGX 0x0 + /* + * Register : DX8SL2IOCR @ 0XFD0814B0 - Low Power PLL Power Down - PSU_DDR_PHY_DX8SL0DQSCTL_LPPLLPD 0x1 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL2IOCR_RESERVED_31 0x0 - Low Power I/O Power Down - PSU_DDR_PHY_DX8SL0DQSCTL_LPIOPD 0x1 + * PVREF_DAC REFSEL range select + * PSU_DDR_PHY_DX8SL2IOCR_DXDACRANGE 0x7 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15 0x0 + * IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring + * PSU_DDR_PHY_DX8SL2IOCR_DXVREFIOM 0x0 - QS Counter Enable - PSU_DDR_PHY_DX8SL0DQSCTL_QSCNTEN 0x1 + * DX IO Mode + * PSU_DDR_PHY_DX8SL2IOCR_DXIOM 0x2 - Unused DQ I/O Mode - PSU_DDR_PHY_DX8SL0DQSCTL_UDQIOM 0x0 + * DX IO Transmitter Mode + * PSU_DDR_PHY_DX8SL2IOCR_DXTXM 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10 0x0 + * DX IO Receiver Mode + * PSU_DDR_PHY_DX8SL2IOCR_DXRXM 0x0 - Data Slew Rate - PSU_DDR_PHY_DX8SL0DQSCTL_DXSR 0x3 - - DQS_N Resistor - PSU_DDR_PHY_DX8SL0DQSCTL_DQSNRES 0x0 - - DQS Resistor - PSU_DDR_PHY_DX8SL0DQSCTL_DQSRES 0x0 - - DATX8 0-1 DQS Control Register - (OFFSET, MASK, VALUE) (0XFD08141C, 0xFFFFFFFFU ,0x01264300U) - RegMask = (DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_MASK | DDR_PHY_DX8SL0DQSCTL_RRRMODE_MASK | DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_MASK | DDR_PHY_DX8SL0DQSCTL_WRRMODE_MASK | DDR_PHY_DX8SL0DQSCTL_DQSGX_MASK | DDR_PHY_DX8SL0DQSCTL_LPPLLPD_MASK | DDR_PHY_DX8SL0DQSCTL_LPIOPD_MASK | DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_MASK | DDR_PHY_DX8SL0DQSCTL_QSCNTEN_MASK | DDR_PHY_DX8SL0DQSCTL_UDQIOM_MASK | DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_MASK | DDR_PHY_DX8SL0DQSCTL_DXSR_MASK | DDR_PHY_DX8SL0DQSCTL_DQSNRES_MASK | DDR_PHY_DX8SL0DQSCTL_DQSRES_MASK | 0 ); + * DATX8 0-1 I/O Configuration Register + * (OFFSET, MASK, VALUE) (0XFD0814B0, 0xFFFFFFFFU ,0x70800000U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL2IOCR_OFFSET, 0xFFFFFFFFU, 0x70800000U); +/*##################################################################### */ - RegVal = ((0x00000000U << DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_SHIFT - | 0x00000001U << DDR_PHY_DX8SL0DQSCTL_RRRMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_SHIFT - | 0x00000001U << DDR_PHY_DX8SL0DQSCTL_WRRMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0DQSCTL_DQSGX_SHIFT - | 0x00000001U << DDR_PHY_DX8SL0DQSCTL_LPPLLPD_SHIFT - | 0x00000001U << DDR_PHY_DX8SL0DQSCTL_LPIOPD_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_SHIFT - | 0x00000001U << DDR_PHY_DX8SL0DQSCTL_QSCNTEN_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0DQSCTL_UDQIOM_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_SHIFT - | 0x00000003U << DDR_PHY_DX8SL0DQSCTL_DXSR_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0DQSCTL_DQSNRES_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0DQSCTL_DQSRES_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8SL0DQSCTL_OFFSET ,0xFFFFFFFFU ,0x01264300U); - /*############################################################################################################################ */ - - /*Register : DX8SL0DXCTL2 @ 0XFD08142C

- - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24 0x0 - - Configurable Read Data Enable - PSU_DDR_PHY_DX8SL0DXCTL2_CRDEN 0x0 - - OX Extension during Post-amble - PSU_DDR_PHY_DX8SL0DXCTL2_POSOEX 0x0 - - OE Extension during Pre-amble - PSU_DDR_PHY_DX8SL0DXCTL2_PREOEX 0x1 - - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_17 0x0 - - I/O Assisted Gate Select - PSU_DDR_PHY_DX8SL0DXCTL2_IOAG 0x0 + /* + * Register : DX8SL3OSC @ 0XFD0814C0 - I/O Loopback Select - PSU_DDR_PHY_DX8SL0DXCTL2_IOLB 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL3OSC_RESERVED_31_30 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13 0x0 + * Enable Clock Gating for DX ddr_clk + * PSU_DDR_PHY_DX8SL3OSC_GATEDXRDCLK 0x2 - Low Power Wakeup Threshold - PSU_DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH 0xc + * Enable Clock Gating for DX ctl_rd_clk + * PSU_DDR_PHY_DX8SL3OSC_GATEDXDDRCLK 0x2 - Read Data Bus Inversion Enable - PSU_DDR_PHY_DX8SL0DXCTL2_RDBI 0x0 + * Enable Clock Gating for DX ctl_clk + * PSU_DDR_PHY_DX8SL3OSC_GATEDXCTLCLK 0x2 - Write Data Bus Inversion Enable - PSU_DDR_PHY_DX8SL0DXCTL2_WDBI 0x0 + * Selects the level to which clocks will be stalled when clock gating is e + * nabled. + * PSU_DDR_PHY_DX8SL3OSC_CLKLEVEL 0x0 - PUB Read FIFO Bypass - PSU_DDR_PHY_DX8SL0DXCTL2_PRFBYP 0x0 + * Loopback Mode + * PSU_DDR_PHY_DX8SL3OSC_LBMODE 0x0 - DATX8 Receive FIFO Read Mode - PSU_DDR_PHY_DX8SL0DXCTL2_RDMODE 0x0 + * Load GSDQS LCDL with 2x the calibrated GSDQSPRD value + * PSU_DDR_PHY_DX8SL3OSC_LBGSDQS 0x0 - Disables the Read FIFO Reset - PSU_DDR_PHY_DX8SL0DXCTL2_DISRST 0x0 + * Loopback DQS Gating + * PSU_DDR_PHY_DX8SL3OSC_LBGDQS 0x0 - Read DQS Gate I/O Loopback - PSU_DDR_PHY_DX8SL0DXCTL2_DQSGLB 0x0 + * Loopback DQS Shift + * PSU_DDR_PHY_DX8SL3OSC_LBDQSS 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_0 0x0 + * PHY High-Speed Reset + * PSU_DDR_PHY_DX8SL3OSC_PHYHRST 0x1 - DATX8 0-1 DX Control Register 2 - (OFFSET, MASK, VALUE) (0XFD08142C, 0xFFFFFFFFU ,0x00041800U) - RegMask = (DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_MASK | DDR_PHY_DX8SL0DXCTL2_CRDEN_MASK | DDR_PHY_DX8SL0DXCTL2_POSOEX_MASK | DDR_PHY_DX8SL0DXCTL2_PREOEX_MASK | DDR_PHY_DX8SL0DXCTL2_RESERVED_17_MASK | DDR_PHY_DX8SL0DXCTL2_IOAG_MASK | DDR_PHY_DX8SL0DXCTL2_IOLB_MASK | DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_MASK | DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_MASK | DDR_PHY_DX8SL0DXCTL2_RDBI_MASK | DDR_PHY_DX8SL0DXCTL2_WDBI_MASK | DDR_PHY_DX8SL0DXCTL2_PRFBYP_MASK | DDR_PHY_DX8SL0DXCTL2_RDMODE_MASK | DDR_PHY_DX8SL0DXCTL2_DISRST_MASK | DDR_PHY_DX8SL0DXCTL2_DQSGLB_MASK | DDR_PHY_DX8SL0DXCTL2_RESERVED_0_MASK | 0 ); + * PHY FIFO Reset + * PSU_DDR_PHY_DX8SL3OSC_PHYFRST 0x1 - RegVal = ((0x00000000U << DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_CRDEN_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_POSOEX_SHIFT - | 0x00000001U << DDR_PHY_DX8SL0DXCTL2_PREOEX_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_RESERVED_17_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_IOAG_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_IOLB_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_SHIFT - | 0x0000000CU << DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_RDBI_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_WDBI_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_PRFBYP_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_RDMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_DISRST_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_DQSGLB_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_RESERVED_0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8SL0DXCTL2_OFFSET ,0xFFFFFFFFU ,0x00041800U); - /*############################################################################################################################ */ + * Delay Line Test Start + * PSU_DDR_PHY_DX8SL3OSC_DLTST 0x0 - /*Register : DX8SL0IOCR @ 0XFD081430

+ * Delay Line Test Mode + * PSU_DDR_PHY_DX8SL3OSC_DLTMODE 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL0IOCR_RESERVED_31 0x0 + * Reserved. Caution, do not write to this register field. + * PSU_DDR_PHY_DX8SL3OSC_RESERVED_12_11 0x3 - PVREF_DAC REFSEL range select - PSU_DDR_PHY_DX8SL0IOCR_DXDACRANGE 0x7 + * Oscillator Mode Write-Data Delay Line Select + * PSU_DDR_PHY_DX8SL3OSC_OSCWDDL 0x3 - IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring - PSU_DDR_PHY_DX8SL0IOCR_DXVREFIOM 0x0 + * Reserved. Caution, do not write to this register field. + * PSU_DDR_PHY_DX8SL3OSC_RESERVED_8_7 0x3 - DX IO Mode - PSU_DDR_PHY_DX8SL0IOCR_DXIOM 0x2 + * Oscillator Mode Write-Leveling Delay Line Select + * PSU_DDR_PHY_DX8SL3OSC_OSCWDL 0x3 - DX IO Transmitter Mode - PSU_DDR_PHY_DX8SL0IOCR_DXTXM 0x0 + * Oscillator Mode Division + * PSU_DDR_PHY_DX8SL3OSC_OSCDIV 0xf - DX IO Receiver Mode - PSU_DDR_PHY_DX8SL0IOCR_DXRXM 0x0 + * Oscillator Enable + * PSU_DDR_PHY_DX8SL3OSC_OSCEN 0x0 - DATX8 0-1 I/O Configuration Register - (OFFSET, MASK, VALUE) (0XFD081430, 0xFFFFFFFFU ,0x70800000U) - RegMask = (DDR_PHY_DX8SL0IOCR_RESERVED_31_MASK | DDR_PHY_DX8SL0IOCR_DXDACRANGE_MASK | DDR_PHY_DX8SL0IOCR_DXVREFIOM_MASK | DDR_PHY_DX8SL0IOCR_DXIOM_MASK | DDR_PHY_DX8SL0IOCR_DXTXM_MASK | DDR_PHY_DX8SL0IOCR_DXRXM_MASK | 0 ); + * DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Lo + * opback, and Gated Clock Control Register + * (OFFSET, MASK, VALUE) (0XFD0814C0, 0xFFFFFFFFU ,0x2A019FFEU) + */ + PSU_Mask_Write(DDR_PHY_DX8SL3OSC_OFFSET, 0xFFFFFFFFU, 0x2A019FFEU); +/*##################################################################### */ - RegVal = ((0x00000000U << DDR_PHY_DX8SL0IOCR_RESERVED_31_SHIFT - | 0x00000007U << DDR_PHY_DX8SL0IOCR_DXDACRANGE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0IOCR_DXVREFIOM_SHIFT - | 0x00000002U << DDR_PHY_DX8SL0IOCR_DXIOM_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0IOCR_DXTXM_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0IOCR_DXRXM_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8SL0IOCR_OFFSET ,0xFFFFFFFFU ,0x70800000U); - /*############################################################################################################################ */ + /* + * Register : DX8SL3PLLCR0 @ 0XFD0814C4 - /*Register : DX8SL1OSC @ 0XFD081440

+ * PLL Bypass + * PSU_DDR_PHY_DX8SL3PLLCR0_PLLBYP 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL1OSC_RESERVED_31_30 0x0 + * PLL Reset + * PSU_DDR_PHY_DX8SL3PLLCR0_PLLRST 0x0 - Enable Clock Gating for DX ddr_clk - PSU_DDR_PHY_DX8SL1OSC_GATEDXRDCLK 0x2 + * PLL Power Down + * PSU_DDR_PHY_DX8SL3PLLCR0_PLLPD 0x0 - Enable Clock Gating for DX ctl_rd_clk - PSU_DDR_PHY_DX8SL1OSC_GATEDXDDRCLK 0x2 + * Reference Stop Mode + * PSU_DDR_PHY_DX8SL3PLLCR0_RSTOPM 0x0 - Enable Clock Gating for DX ctl_clk - PSU_DDR_PHY_DX8SL1OSC_GATEDXCTLCLK 0x2 + * PLL Frequency Select + * PSU_DDR_PHY_DX8SL3PLLCR0_FRQSEL 0x1 - Selects the level to which clocks will be stalled when clock gating is enabled. - PSU_DDR_PHY_DX8SL1OSC_CLKLEVEL 0x0 + * Relock Mode + * PSU_DDR_PHY_DX8SL3PLLCR0_RLOCKM 0x0 - Loopback Mode - PSU_DDR_PHY_DX8SL1OSC_LBMODE 0x0 + * Charge Pump Proportional Current Control + * PSU_DDR_PHY_DX8SL3PLLCR0_CPPC 0x8 - Load GSDQS LCDL with 2x the calibrated GSDQSPRD value - PSU_DDR_PHY_DX8SL1OSC_LBGSDQS 0x0 + * Charge Pump Integrating Current Control + * PSU_DDR_PHY_DX8SL3PLLCR0_CPIC 0x0 - Loopback DQS Gating - PSU_DDR_PHY_DX8SL1OSC_LBGDQS 0x0 + * Gear Shift + * PSU_DDR_PHY_DX8SL3PLLCR0_GSHIFT 0x0 - Loopback DQS Shift - PSU_DDR_PHY_DX8SL1OSC_LBDQSS 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL3PLLCR0_RESERVED_11_9 0x0 - PHY High-Speed Reset - PSU_DDR_PHY_DX8SL1OSC_PHYHRST 0x1 + * Analog Test Enable (ATOEN) + * PSU_DDR_PHY_DX8SL3PLLCR0_ATOEN 0x0 - PHY FIFO Reset - PSU_DDR_PHY_DX8SL1OSC_PHYFRST 0x1 + * Analog Test Control + * PSU_DDR_PHY_DX8SL3PLLCR0_ATC 0x0 - Delay Line Test Start - PSU_DDR_PHY_DX8SL1OSC_DLTST 0x0 + * Digital Test Control + * PSU_DDR_PHY_DX8SL3PLLCR0_DTC 0x0 - Delay Line Test Mode - PSU_DDR_PHY_DX8SL1OSC_DLTMODE 0x0 + * DAXT8 0-1 PLL Control Register 0 + * (OFFSET, MASK, VALUE) (0XFD0814C4, 0xFFFFFFFFU ,0x01100000U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL3PLLCR0_OFFSET, + 0xFFFFFFFFU, 0x01100000U); +/*##################################################################### */ - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX8SL1OSC_RESERVED_12_11 0x3 - - Oscillator Mode Write-Data Delay Line Select - PSU_DDR_PHY_DX8SL1OSC_OSCWDDL 0x3 - - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX8SL1OSC_RESERVED_8_7 0x3 - - Oscillator Mode Write-Leveling Delay Line Select - PSU_DDR_PHY_DX8SL1OSC_OSCWDL 0x3 - - Oscillator Mode Division - PSU_DDR_PHY_DX8SL1OSC_OSCDIV 0xf + /* + * Register : DX8SL3DQSCTL @ 0XFD0814DC - Oscillator Enable - PSU_DDR_PHY_DX8SL1OSC_OSCEN 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25 0x0 - DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register - (OFFSET, MASK, VALUE) (0XFD081440, 0xFFFFFFFFU ,0x2A019FFEU) - RegMask = (DDR_PHY_DX8SL1OSC_RESERVED_31_30_MASK | DDR_PHY_DX8SL1OSC_GATEDXRDCLK_MASK | DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_MASK | DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_MASK | DDR_PHY_DX8SL1OSC_CLKLEVEL_MASK | DDR_PHY_DX8SL1OSC_LBMODE_MASK | DDR_PHY_DX8SL1OSC_LBGSDQS_MASK | DDR_PHY_DX8SL1OSC_LBGDQS_MASK | DDR_PHY_DX8SL1OSC_LBDQSS_MASK | DDR_PHY_DX8SL1OSC_PHYHRST_MASK | DDR_PHY_DX8SL1OSC_PHYFRST_MASK | DDR_PHY_DX8SL1OSC_DLTST_MASK | DDR_PHY_DX8SL1OSC_DLTMODE_MASK | DDR_PHY_DX8SL1OSC_RESERVED_12_11_MASK | DDR_PHY_DX8SL1OSC_OSCWDDL_MASK | DDR_PHY_DX8SL1OSC_RESERVED_8_7_MASK | DDR_PHY_DX8SL1OSC_OSCWDL_MASK | DDR_PHY_DX8SL1OSC_OSCDIV_MASK | DDR_PHY_DX8SL1OSC_OSCEN_MASK | 0 ); + * Read Path Rise-to-Rise Mode + * PSU_DDR_PHY_DX8SL3DQSCTL_RRRMODE 0x1 - RegVal = ((0x00000000U << DDR_PHY_DX8SL1OSC_RESERVED_31_30_SHIFT - | 0x00000002U << DDR_PHY_DX8SL1OSC_GATEDXRDCLK_SHIFT - | 0x00000002U << DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_SHIFT - | 0x00000002U << DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1OSC_CLKLEVEL_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1OSC_LBMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1OSC_LBGSDQS_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1OSC_LBGDQS_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1OSC_LBDQSS_SHIFT - | 0x00000001U << DDR_PHY_DX8SL1OSC_PHYHRST_SHIFT - | 0x00000001U << DDR_PHY_DX8SL1OSC_PHYFRST_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1OSC_DLTST_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1OSC_DLTMODE_SHIFT - | 0x00000003U << DDR_PHY_DX8SL1OSC_RESERVED_12_11_SHIFT - | 0x00000003U << DDR_PHY_DX8SL1OSC_OSCWDDL_SHIFT - | 0x00000003U << DDR_PHY_DX8SL1OSC_RESERVED_8_7_SHIFT - | 0x00000003U << DDR_PHY_DX8SL1OSC_OSCWDL_SHIFT - | 0x0000000FU << DDR_PHY_DX8SL1OSC_OSCDIV_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1OSC_OSCEN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8SL1OSC_OFFSET ,0xFFFFFFFFU ,0x2A019FFEU); - /*############################################################################################################################ */ + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22 0x0 - /*Register : DX8SL1DQSCTL @ 0XFD08145C

+ * Write Path Rise-to-Rise Mode + * PSU_DDR_PHY_DX8SL3DQSCTL_WRRMODE 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25 0x0 + * DQS Gate Extension + * PSU_DDR_PHY_DX8SL3DQSCTL_DQSGX 0x0 - Read Path Rise-to-Rise Mode - PSU_DDR_PHY_DX8SL1DQSCTL_RRRMODE 0x1 + * Low Power PLL Power Down + * PSU_DDR_PHY_DX8SL3DQSCTL_LPPLLPD 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22 0x0 + * Low Power I/O Power Down + * PSU_DDR_PHY_DX8SL3DQSCTL_LPIOPD 0x1 - Write Path Rise-to-Rise Mode - PSU_DDR_PHY_DX8SL1DQSCTL_WRRMODE 0x1 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15 0x0 - DQS Gate Extension - PSU_DDR_PHY_DX8SL1DQSCTL_DQSGX 0x0 + * QS Counter Enable + * PSU_DDR_PHY_DX8SL3DQSCTL_QSCNTEN 0x1 - Low Power PLL Power Down - PSU_DDR_PHY_DX8SL1DQSCTL_LPPLLPD 0x1 + * Unused DQ I/O Mode + * PSU_DDR_PHY_DX8SL3DQSCTL_UDQIOM 0x0 - Low Power I/O Power Down - PSU_DDR_PHY_DX8SL1DQSCTL_LPIOPD 0x1 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15 0x0 + * Data Slew Rate + * PSU_DDR_PHY_DX8SL3DQSCTL_DXSR 0x3 - QS Counter Enable - PSU_DDR_PHY_DX8SL1DQSCTL_QSCNTEN 0x1 + * DQS_N Resistor + * PSU_DDR_PHY_DX8SL3DQSCTL_DQSNRES 0x0 - Unused DQ I/O Mode - PSU_DDR_PHY_DX8SL1DQSCTL_UDQIOM 0x0 + * DQS Resistor + * PSU_DDR_PHY_DX8SL3DQSCTL_DQSRES 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10 0x0 + * DATX8 0-1 DQS Control Register + * (OFFSET, MASK, VALUE) (0XFD0814DC, 0xFFFFFFFFU ,0x01264300U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL3DQSCTL_OFFSET, + 0xFFFFFFFFU, 0x01264300U); +/*##################################################################### */ - Data Slew Rate - PSU_DDR_PHY_DX8SL1DQSCTL_DXSR 0x3 - - DQS_N Resistor - PSU_DDR_PHY_DX8SL1DQSCTL_DQSNRES 0x0 - - DQS Resistor - PSU_DDR_PHY_DX8SL1DQSCTL_DQSRES 0x0 - - DATX8 0-1 DQS Control Register - (OFFSET, MASK, VALUE) (0XFD08145C, 0xFFFFFFFFU ,0x01264300U) - RegMask = (DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_MASK | DDR_PHY_DX8SL1DQSCTL_RRRMODE_MASK | DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_MASK | DDR_PHY_DX8SL1DQSCTL_WRRMODE_MASK | DDR_PHY_DX8SL1DQSCTL_DQSGX_MASK | DDR_PHY_DX8SL1DQSCTL_LPPLLPD_MASK | DDR_PHY_DX8SL1DQSCTL_LPIOPD_MASK | DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_MASK | DDR_PHY_DX8SL1DQSCTL_QSCNTEN_MASK | DDR_PHY_DX8SL1DQSCTL_UDQIOM_MASK | DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_MASK | DDR_PHY_DX8SL1DQSCTL_DXSR_MASK | DDR_PHY_DX8SL1DQSCTL_DQSNRES_MASK | DDR_PHY_DX8SL1DQSCTL_DQSRES_MASK | 0 ); + /* + * Register : DX8SL3DXCTL2 @ 0XFD0814EC - RegVal = ((0x00000000U << DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_SHIFT - | 0x00000001U << DDR_PHY_DX8SL1DQSCTL_RRRMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_SHIFT - | 0x00000001U << DDR_PHY_DX8SL1DQSCTL_WRRMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1DQSCTL_DQSGX_SHIFT - | 0x00000001U << DDR_PHY_DX8SL1DQSCTL_LPPLLPD_SHIFT - | 0x00000001U << DDR_PHY_DX8SL1DQSCTL_LPIOPD_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_SHIFT - | 0x00000001U << DDR_PHY_DX8SL1DQSCTL_QSCNTEN_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1DQSCTL_UDQIOM_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_SHIFT - | 0x00000003U << DDR_PHY_DX8SL1DQSCTL_DXSR_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1DQSCTL_DQSNRES_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1DQSCTL_DQSRES_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8SL1DQSCTL_OFFSET ,0xFFFFFFFFU ,0x01264300U); - /*############################################################################################################################ */ - - /*Register : DX8SL1DXCTL2 @ 0XFD08146C

- - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24 0x0 - - Configurable Read Data Enable - PSU_DDR_PHY_DX8SL1DXCTL2_CRDEN 0x0 - - OX Extension during Post-amble - PSU_DDR_PHY_DX8SL1DXCTL2_POSOEX 0x0 - - OE Extension during Pre-amble - PSU_DDR_PHY_DX8SL1DXCTL2_PREOEX 0x1 - - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_17 0x0 - - I/O Assisted Gate Select - PSU_DDR_PHY_DX8SL1DXCTL2_IOAG 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24 0x0 - I/O Loopback Select - PSU_DDR_PHY_DX8SL1DXCTL2_IOLB 0x0 + * Configurable Read Data Enable + * PSU_DDR_PHY_DX8SL3DXCTL2_CRDEN 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13 0x0 + * OX Extension during Post-amble + * PSU_DDR_PHY_DX8SL3DXCTL2_POSOEX 0x0 - Low Power Wakeup Threshold - PSU_DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH 0xc + * OE Extension during Pre-amble + * PSU_DDR_PHY_DX8SL3DXCTL2_PREOEX 0x1 - Read Data Bus Inversion Enable - PSU_DDR_PHY_DX8SL1DXCTL2_RDBI 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_17 0x0 - Write Data Bus Inversion Enable - PSU_DDR_PHY_DX8SL1DXCTL2_WDBI 0x0 + * I/O Assisted Gate Select + * PSU_DDR_PHY_DX8SL3DXCTL2_IOAG 0x0 - PUB Read FIFO Bypass - PSU_DDR_PHY_DX8SL1DXCTL2_PRFBYP 0x0 + * I/O Loopback Select + * PSU_DDR_PHY_DX8SL3DXCTL2_IOLB 0x0 - DATX8 Receive FIFO Read Mode - PSU_DDR_PHY_DX8SL1DXCTL2_RDMODE 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13 0x0 - Disables the Read FIFO Reset - PSU_DDR_PHY_DX8SL1DXCTL2_DISRST 0x0 + * Low Power Wakeup Threshold + * PSU_DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH 0xc - Read DQS Gate I/O Loopback - PSU_DDR_PHY_DX8SL1DXCTL2_DQSGLB 0x0 + * Read Data Bus Inversion Enable + * PSU_DDR_PHY_DX8SL3DXCTL2_RDBI 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_0 0x0 + * Write Data Bus Inversion Enable + * PSU_DDR_PHY_DX8SL3DXCTL2_WDBI 0x0 - DATX8 0-1 DX Control Register 2 - (OFFSET, MASK, VALUE) (0XFD08146C, 0xFFFFFFFFU ,0x00041800U) - RegMask = (DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_MASK | DDR_PHY_DX8SL1DXCTL2_CRDEN_MASK | DDR_PHY_DX8SL1DXCTL2_POSOEX_MASK | DDR_PHY_DX8SL1DXCTL2_PREOEX_MASK | DDR_PHY_DX8SL1DXCTL2_RESERVED_17_MASK | DDR_PHY_DX8SL1DXCTL2_IOAG_MASK | DDR_PHY_DX8SL1DXCTL2_IOLB_MASK | DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_MASK | DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_MASK | DDR_PHY_DX8SL1DXCTL2_RDBI_MASK | DDR_PHY_DX8SL1DXCTL2_WDBI_MASK | DDR_PHY_DX8SL1DXCTL2_PRFBYP_MASK | DDR_PHY_DX8SL1DXCTL2_RDMODE_MASK | DDR_PHY_DX8SL1DXCTL2_DISRST_MASK | DDR_PHY_DX8SL1DXCTL2_DQSGLB_MASK | DDR_PHY_DX8SL1DXCTL2_RESERVED_0_MASK | 0 ); + * PUB Read FIFO Bypass + * PSU_DDR_PHY_DX8SL3DXCTL2_PRFBYP 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_CRDEN_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_POSOEX_SHIFT - | 0x00000001U << DDR_PHY_DX8SL1DXCTL2_PREOEX_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_RESERVED_17_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_IOAG_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_IOLB_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_SHIFT - | 0x0000000CU << DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_RDBI_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_WDBI_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_PRFBYP_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_RDMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_DISRST_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_DQSGLB_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_RESERVED_0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8SL1DXCTL2_OFFSET ,0xFFFFFFFFU ,0x00041800U); - /*############################################################################################################################ */ + * DATX8 Receive FIFO Read Mode + * PSU_DDR_PHY_DX8SL3DXCTL2_RDMODE 0x0 - /*Register : DX8SL1IOCR @ 0XFD081470

+ * Disables the Read FIFO Reset + * PSU_DDR_PHY_DX8SL3DXCTL2_DISRST 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL1IOCR_RESERVED_31 0x0 + * Read DQS Gate I/O Loopback + * PSU_DDR_PHY_DX8SL3DXCTL2_DQSGLB 0x0 - PVREF_DAC REFSEL range select - PSU_DDR_PHY_DX8SL1IOCR_DXDACRANGE 0x7 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_0 0x0 - IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring - PSU_DDR_PHY_DX8SL1IOCR_DXVREFIOM 0x0 + * DATX8 0-1 DX Control Register 2 + * (OFFSET, MASK, VALUE) (0XFD0814EC, 0xFFFFFFFFU ,0x00041800U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL3DXCTL2_OFFSET, + 0xFFFFFFFFU, 0x00041800U); +/*##################################################################### */ - DX IO Mode - PSU_DDR_PHY_DX8SL1IOCR_DXIOM 0x2 + /* + * Register : DX8SL3IOCR @ 0XFD0814F0 - DX IO Transmitter Mode - PSU_DDR_PHY_DX8SL1IOCR_DXTXM 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL3IOCR_RESERVED_31 0x0 - DX IO Receiver Mode - PSU_DDR_PHY_DX8SL1IOCR_DXRXM 0x0 + * PVREF_DAC REFSEL range select + * PSU_DDR_PHY_DX8SL3IOCR_DXDACRANGE 0x7 - DATX8 0-1 I/O Configuration Register - (OFFSET, MASK, VALUE) (0XFD081470, 0xFFFFFFFFU ,0x70800000U) - RegMask = (DDR_PHY_DX8SL1IOCR_RESERVED_31_MASK | DDR_PHY_DX8SL1IOCR_DXDACRANGE_MASK | DDR_PHY_DX8SL1IOCR_DXVREFIOM_MASK | DDR_PHY_DX8SL1IOCR_DXIOM_MASK | DDR_PHY_DX8SL1IOCR_DXTXM_MASK | DDR_PHY_DX8SL1IOCR_DXRXM_MASK | 0 ); + * IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring + * PSU_DDR_PHY_DX8SL3IOCR_DXVREFIOM 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX8SL1IOCR_RESERVED_31_SHIFT - | 0x00000007U << DDR_PHY_DX8SL1IOCR_DXDACRANGE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1IOCR_DXVREFIOM_SHIFT - | 0x00000002U << DDR_PHY_DX8SL1IOCR_DXIOM_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1IOCR_DXTXM_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1IOCR_DXRXM_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8SL1IOCR_OFFSET ,0xFFFFFFFFU ,0x70800000U); - /*############################################################################################################################ */ + * DX IO Mode + * PSU_DDR_PHY_DX8SL3IOCR_DXIOM 0x2 - /*Register : DX8SL2OSC @ 0XFD081480

+ * DX IO Transmitter Mode + * PSU_DDR_PHY_DX8SL3IOCR_DXTXM 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL2OSC_RESERVED_31_30 0x0 + * DX IO Receiver Mode + * PSU_DDR_PHY_DX8SL3IOCR_DXRXM 0x0 - Enable Clock Gating for DX ddr_clk - PSU_DDR_PHY_DX8SL2OSC_GATEDXRDCLK 0x2 + * DATX8 0-1 I/O Configuration Register + * (OFFSET, MASK, VALUE) (0XFD0814F0, 0xFFFFFFFFU ,0x70800000U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL3IOCR_OFFSET, 0xFFFFFFFFU, 0x70800000U); +/*##################################################################### */ - Enable Clock Gating for DX ctl_rd_clk - PSU_DDR_PHY_DX8SL2OSC_GATEDXDDRCLK 0x2 + /* + * Register : DX8SL4OSC @ 0XFD081500 - Enable Clock Gating for DX ctl_clk - PSU_DDR_PHY_DX8SL2OSC_GATEDXCTLCLK 0x2 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL4OSC_RESERVED_31_30 0x0 - Selects the level to which clocks will be stalled when clock gating is enabled. - PSU_DDR_PHY_DX8SL2OSC_CLKLEVEL 0x0 + * Enable Clock Gating for DX ddr_clk + * PSU_DDR_PHY_DX8SL4OSC_GATEDXRDCLK 0x2 - Loopback Mode - PSU_DDR_PHY_DX8SL2OSC_LBMODE 0x0 + * Enable Clock Gating for DX ctl_rd_clk + * PSU_DDR_PHY_DX8SL4OSC_GATEDXDDRCLK 0x2 - Load GSDQS LCDL with 2x the calibrated GSDQSPRD value - PSU_DDR_PHY_DX8SL2OSC_LBGSDQS 0x0 + * Enable Clock Gating for DX ctl_clk + * PSU_DDR_PHY_DX8SL4OSC_GATEDXCTLCLK 0x2 - Loopback DQS Gating - PSU_DDR_PHY_DX8SL2OSC_LBGDQS 0x0 + * Selects the level to which clocks will be stalled when clock gating is e + * nabled. + * PSU_DDR_PHY_DX8SL4OSC_CLKLEVEL 0x0 - Loopback DQS Shift - PSU_DDR_PHY_DX8SL2OSC_LBDQSS 0x0 + * Loopback Mode + * PSU_DDR_PHY_DX8SL4OSC_LBMODE 0x0 - PHY High-Speed Reset - PSU_DDR_PHY_DX8SL2OSC_PHYHRST 0x1 + * Load GSDQS LCDL with 2x the calibrated GSDQSPRD value + * PSU_DDR_PHY_DX8SL4OSC_LBGSDQS 0x0 - PHY FIFO Reset - PSU_DDR_PHY_DX8SL2OSC_PHYFRST 0x1 + * Loopback DQS Gating + * PSU_DDR_PHY_DX8SL4OSC_LBGDQS 0x0 - Delay Line Test Start - PSU_DDR_PHY_DX8SL2OSC_DLTST 0x0 + * Loopback DQS Shift + * PSU_DDR_PHY_DX8SL4OSC_LBDQSS 0x0 - Delay Line Test Mode - PSU_DDR_PHY_DX8SL2OSC_DLTMODE 0x0 + * PHY High-Speed Reset + * PSU_DDR_PHY_DX8SL4OSC_PHYHRST 0x1 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX8SL2OSC_RESERVED_12_11 0x3 - - Oscillator Mode Write-Data Delay Line Select - PSU_DDR_PHY_DX8SL2OSC_OSCWDDL 0x3 - - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX8SL2OSC_RESERVED_8_7 0x3 - - Oscillator Mode Write-Leveling Delay Line Select - PSU_DDR_PHY_DX8SL2OSC_OSCWDL 0x3 - - Oscillator Mode Division - PSU_DDR_PHY_DX8SL2OSC_OSCDIV 0xf + * PHY FIFO Reset + * PSU_DDR_PHY_DX8SL4OSC_PHYFRST 0x1 - Oscillator Enable - PSU_DDR_PHY_DX8SL2OSC_OSCEN 0x0 + * Delay Line Test Start + * PSU_DDR_PHY_DX8SL4OSC_DLTST 0x0 - DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register - (OFFSET, MASK, VALUE) (0XFD081480, 0xFFFFFFFFU ,0x2A019FFEU) - RegMask = (DDR_PHY_DX8SL2OSC_RESERVED_31_30_MASK | DDR_PHY_DX8SL2OSC_GATEDXRDCLK_MASK | DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_MASK | DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_MASK | DDR_PHY_DX8SL2OSC_CLKLEVEL_MASK | DDR_PHY_DX8SL2OSC_LBMODE_MASK | DDR_PHY_DX8SL2OSC_LBGSDQS_MASK | DDR_PHY_DX8SL2OSC_LBGDQS_MASK | DDR_PHY_DX8SL2OSC_LBDQSS_MASK | DDR_PHY_DX8SL2OSC_PHYHRST_MASK | DDR_PHY_DX8SL2OSC_PHYFRST_MASK | DDR_PHY_DX8SL2OSC_DLTST_MASK | DDR_PHY_DX8SL2OSC_DLTMODE_MASK | DDR_PHY_DX8SL2OSC_RESERVED_12_11_MASK | DDR_PHY_DX8SL2OSC_OSCWDDL_MASK | DDR_PHY_DX8SL2OSC_RESERVED_8_7_MASK | DDR_PHY_DX8SL2OSC_OSCWDL_MASK | DDR_PHY_DX8SL2OSC_OSCDIV_MASK | DDR_PHY_DX8SL2OSC_OSCEN_MASK | 0 ); + * Delay Line Test Mode + * PSU_DDR_PHY_DX8SL4OSC_DLTMODE 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX8SL2OSC_RESERVED_31_30_SHIFT - | 0x00000002U << DDR_PHY_DX8SL2OSC_GATEDXRDCLK_SHIFT - | 0x00000002U << DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_SHIFT - | 0x00000002U << DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2OSC_CLKLEVEL_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2OSC_LBMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2OSC_LBGSDQS_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2OSC_LBGDQS_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2OSC_LBDQSS_SHIFT - | 0x00000001U << DDR_PHY_DX8SL2OSC_PHYHRST_SHIFT - | 0x00000001U << DDR_PHY_DX8SL2OSC_PHYFRST_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2OSC_DLTST_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2OSC_DLTMODE_SHIFT - | 0x00000003U << DDR_PHY_DX8SL2OSC_RESERVED_12_11_SHIFT - | 0x00000003U << DDR_PHY_DX8SL2OSC_OSCWDDL_SHIFT - | 0x00000003U << DDR_PHY_DX8SL2OSC_RESERVED_8_7_SHIFT - | 0x00000003U << DDR_PHY_DX8SL2OSC_OSCWDL_SHIFT - | 0x0000000FU << DDR_PHY_DX8SL2OSC_OSCDIV_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2OSC_OSCEN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8SL2OSC_OFFSET ,0xFFFFFFFFU ,0x2A019FFEU); - /*############################################################################################################################ */ + * Reserved. Caution, do not write to this register field. + * PSU_DDR_PHY_DX8SL4OSC_RESERVED_12_11 0x3 - /*Register : DX8SL2DQSCTL @ 0XFD08149C

+ * Oscillator Mode Write-Data Delay Line Select + * PSU_DDR_PHY_DX8SL4OSC_OSCWDDL 0x3 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25 0x0 + * Reserved. Caution, do not write to this register field. + * PSU_DDR_PHY_DX8SL4OSC_RESERVED_8_7 0x3 - Read Path Rise-to-Rise Mode - PSU_DDR_PHY_DX8SL2DQSCTL_RRRMODE 0x1 + * Oscillator Mode Write-Leveling Delay Line Select + * PSU_DDR_PHY_DX8SL4OSC_OSCWDL 0x3 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22 0x0 + * Oscillator Mode Division + * PSU_DDR_PHY_DX8SL4OSC_OSCDIV 0xf - Write Path Rise-to-Rise Mode - PSU_DDR_PHY_DX8SL2DQSCTL_WRRMODE 0x1 + * Oscillator Enable + * PSU_DDR_PHY_DX8SL4OSC_OSCEN 0x0 - DQS Gate Extension - PSU_DDR_PHY_DX8SL2DQSCTL_DQSGX 0x0 + * DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Lo + * opback, and Gated Clock Control Register + * (OFFSET, MASK, VALUE) (0XFD081500, 0xFFFFFFFFU ,0x2A019FFEU) + */ + PSU_Mask_Write(DDR_PHY_DX8SL4OSC_OFFSET, 0xFFFFFFFFU, 0x2A019FFEU); +/*##################################################################### */ - Low Power PLL Power Down - PSU_DDR_PHY_DX8SL2DQSCTL_LPPLLPD 0x1 + /* + * Register : DX8SL4PLLCR0 @ 0XFD081504 - Low Power I/O Power Down - PSU_DDR_PHY_DX8SL2DQSCTL_LPIOPD 0x1 + * PLL Bypass + * PSU_DDR_PHY_DX8SL4PLLCR0_PLLBYP 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15 0x0 + * PLL Reset + * PSU_DDR_PHY_DX8SL4PLLCR0_PLLRST 0x0 - QS Counter Enable - PSU_DDR_PHY_DX8SL2DQSCTL_QSCNTEN 0x1 + * PLL Power Down + * PSU_DDR_PHY_DX8SL4PLLCR0_PLLPD 0x0 - Unused DQ I/O Mode - PSU_DDR_PHY_DX8SL2DQSCTL_UDQIOM 0x0 + * Reference Stop Mode + * PSU_DDR_PHY_DX8SL4PLLCR0_RSTOPM 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10 0x0 + * PLL Frequency Select + * PSU_DDR_PHY_DX8SL4PLLCR0_FRQSEL 0x1 - Data Slew Rate - PSU_DDR_PHY_DX8SL2DQSCTL_DXSR 0x3 - - DQS_N Resistor - PSU_DDR_PHY_DX8SL2DQSCTL_DQSNRES 0x0 - - DQS Resistor - PSU_DDR_PHY_DX8SL2DQSCTL_DQSRES 0x0 - - DATX8 0-1 DQS Control Register - (OFFSET, MASK, VALUE) (0XFD08149C, 0xFFFFFFFFU ,0x01264300U) - RegMask = (DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_MASK | DDR_PHY_DX8SL2DQSCTL_RRRMODE_MASK | DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_MASK | DDR_PHY_DX8SL2DQSCTL_WRRMODE_MASK | DDR_PHY_DX8SL2DQSCTL_DQSGX_MASK | DDR_PHY_DX8SL2DQSCTL_LPPLLPD_MASK | DDR_PHY_DX8SL2DQSCTL_LPIOPD_MASK | DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_MASK | DDR_PHY_DX8SL2DQSCTL_QSCNTEN_MASK | DDR_PHY_DX8SL2DQSCTL_UDQIOM_MASK | DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_MASK | DDR_PHY_DX8SL2DQSCTL_DXSR_MASK | DDR_PHY_DX8SL2DQSCTL_DQSNRES_MASK | DDR_PHY_DX8SL2DQSCTL_DQSRES_MASK | 0 ); + * Relock Mode + * PSU_DDR_PHY_DX8SL4PLLCR0_RLOCKM 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_SHIFT - | 0x00000001U << DDR_PHY_DX8SL2DQSCTL_RRRMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_SHIFT - | 0x00000001U << DDR_PHY_DX8SL2DQSCTL_WRRMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2DQSCTL_DQSGX_SHIFT - | 0x00000001U << DDR_PHY_DX8SL2DQSCTL_LPPLLPD_SHIFT - | 0x00000001U << DDR_PHY_DX8SL2DQSCTL_LPIOPD_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_SHIFT - | 0x00000001U << DDR_PHY_DX8SL2DQSCTL_QSCNTEN_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2DQSCTL_UDQIOM_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_SHIFT - | 0x00000003U << DDR_PHY_DX8SL2DQSCTL_DXSR_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2DQSCTL_DQSNRES_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2DQSCTL_DQSRES_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8SL2DQSCTL_OFFSET ,0xFFFFFFFFU ,0x01264300U); - /*############################################################################################################################ */ - - /*Register : DX8SL2DXCTL2 @ 0XFD0814AC

- - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24 0x0 - - Configurable Read Data Enable - PSU_DDR_PHY_DX8SL2DXCTL2_CRDEN 0x0 - - OX Extension during Post-amble - PSU_DDR_PHY_DX8SL2DXCTL2_POSOEX 0x0 - - OE Extension during Pre-amble - PSU_DDR_PHY_DX8SL2DXCTL2_PREOEX 0x1 - - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_17 0x0 - - I/O Assisted Gate Select - PSU_DDR_PHY_DX8SL2DXCTL2_IOAG 0x0 + * Charge Pump Proportional Current Control + * PSU_DDR_PHY_DX8SL4PLLCR0_CPPC 0x8 - I/O Loopback Select - PSU_DDR_PHY_DX8SL2DXCTL2_IOLB 0x0 + * Charge Pump Integrating Current Control + * PSU_DDR_PHY_DX8SL4PLLCR0_CPIC 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13 0x0 + * Gear Shift + * PSU_DDR_PHY_DX8SL4PLLCR0_GSHIFT 0x0 - Low Power Wakeup Threshold - PSU_DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH 0xc + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL4PLLCR0_RESERVED_11_9 0x0 - Read Data Bus Inversion Enable - PSU_DDR_PHY_DX8SL2DXCTL2_RDBI 0x0 + * Analog Test Enable (ATOEN) + * PSU_DDR_PHY_DX8SL4PLLCR0_ATOEN 0x0 - Write Data Bus Inversion Enable - PSU_DDR_PHY_DX8SL2DXCTL2_WDBI 0x0 + * Analog Test Control + * PSU_DDR_PHY_DX8SL4PLLCR0_ATC 0x0 - PUB Read FIFO Bypass - PSU_DDR_PHY_DX8SL2DXCTL2_PRFBYP 0x0 + * Digital Test Control + * PSU_DDR_PHY_DX8SL4PLLCR0_DTC 0x0 - DATX8 Receive FIFO Read Mode - PSU_DDR_PHY_DX8SL2DXCTL2_RDMODE 0x0 + * DAXT8 0-1 PLL Control Register 0 + * (OFFSET, MASK, VALUE) (0XFD081504, 0xFFFFFFFFU ,0x01100000U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL4PLLCR0_OFFSET, + 0xFFFFFFFFU, 0x01100000U); +/*##################################################################### */ - Disables the Read FIFO Reset - PSU_DDR_PHY_DX8SL2DXCTL2_DISRST 0x0 + /* + * Register : DX8SL4DQSCTL @ 0XFD08151C - Read DQS Gate I/O Loopback - PSU_DDR_PHY_DX8SL2DXCTL2_DQSGLB 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_0 0x0 + * Read Path Rise-to-Rise Mode + * PSU_DDR_PHY_DX8SL4DQSCTL_RRRMODE 0x1 - DATX8 0-1 DX Control Register 2 - (OFFSET, MASK, VALUE) (0XFD0814AC, 0xFFFFFFFFU ,0x00041800U) - RegMask = (DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_MASK | DDR_PHY_DX8SL2DXCTL2_CRDEN_MASK | DDR_PHY_DX8SL2DXCTL2_POSOEX_MASK | DDR_PHY_DX8SL2DXCTL2_PREOEX_MASK | DDR_PHY_DX8SL2DXCTL2_RESERVED_17_MASK | DDR_PHY_DX8SL2DXCTL2_IOAG_MASK | DDR_PHY_DX8SL2DXCTL2_IOLB_MASK | DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_MASK | DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_MASK | DDR_PHY_DX8SL2DXCTL2_RDBI_MASK | DDR_PHY_DX8SL2DXCTL2_WDBI_MASK | DDR_PHY_DX8SL2DXCTL2_PRFBYP_MASK | DDR_PHY_DX8SL2DXCTL2_RDMODE_MASK | DDR_PHY_DX8SL2DXCTL2_DISRST_MASK | DDR_PHY_DX8SL2DXCTL2_DQSGLB_MASK | DDR_PHY_DX8SL2DXCTL2_RESERVED_0_MASK | 0 ); + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_CRDEN_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_POSOEX_SHIFT - | 0x00000001U << DDR_PHY_DX8SL2DXCTL2_PREOEX_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_RESERVED_17_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_IOAG_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_IOLB_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_SHIFT - | 0x0000000CU << DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_RDBI_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_WDBI_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_PRFBYP_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_RDMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_DISRST_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_DQSGLB_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_RESERVED_0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8SL2DXCTL2_OFFSET ,0xFFFFFFFFU ,0x00041800U); - /*############################################################################################################################ */ + * Write Path Rise-to-Rise Mode + * PSU_DDR_PHY_DX8SL4DQSCTL_WRRMODE 0x1 - /*Register : DX8SL2IOCR @ 0XFD0814B0

+ * DQS Gate Extension + * PSU_DDR_PHY_DX8SL4DQSCTL_DQSGX 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL2IOCR_RESERVED_31 0x0 + * Low Power PLL Power Down + * PSU_DDR_PHY_DX8SL4DQSCTL_LPPLLPD 0x1 - PVREF_DAC REFSEL range select - PSU_DDR_PHY_DX8SL2IOCR_DXDACRANGE 0x7 + * Low Power I/O Power Down + * PSU_DDR_PHY_DX8SL4DQSCTL_LPIOPD 0x1 - IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring - PSU_DDR_PHY_DX8SL2IOCR_DXVREFIOM 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15 0x0 - DX IO Mode - PSU_DDR_PHY_DX8SL2IOCR_DXIOM 0x2 + * QS Counter Enable + * PSU_DDR_PHY_DX8SL4DQSCTL_QSCNTEN 0x1 - DX IO Transmitter Mode - PSU_DDR_PHY_DX8SL2IOCR_DXTXM 0x0 + * Unused DQ I/O Mode + * PSU_DDR_PHY_DX8SL4DQSCTL_UDQIOM 0x0 - DX IO Receiver Mode - PSU_DDR_PHY_DX8SL2IOCR_DXRXM 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10 0x0 - DATX8 0-1 I/O Configuration Register - (OFFSET, MASK, VALUE) (0XFD0814B0, 0xFFFFFFFFU ,0x70800000U) - RegMask = (DDR_PHY_DX8SL2IOCR_RESERVED_31_MASK | DDR_PHY_DX8SL2IOCR_DXDACRANGE_MASK | DDR_PHY_DX8SL2IOCR_DXVREFIOM_MASK | DDR_PHY_DX8SL2IOCR_DXIOM_MASK | DDR_PHY_DX8SL2IOCR_DXTXM_MASK | DDR_PHY_DX8SL2IOCR_DXRXM_MASK | 0 ); + * Data Slew Rate + * PSU_DDR_PHY_DX8SL4DQSCTL_DXSR 0x3 - RegVal = ((0x00000000U << DDR_PHY_DX8SL2IOCR_RESERVED_31_SHIFT - | 0x00000007U << DDR_PHY_DX8SL2IOCR_DXDACRANGE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2IOCR_DXVREFIOM_SHIFT - | 0x00000002U << DDR_PHY_DX8SL2IOCR_DXIOM_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2IOCR_DXTXM_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2IOCR_DXRXM_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8SL2IOCR_OFFSET ,0xFFFFFFFFU ,0x70800000U); - /*############################################################################################################################ */ + * DQS_N Resistor + * PSU_DDR_PHY_DX8SL4DQSCTL_DQSNRES 0x0 - /*Register : DX8SL3OSC @ 0XFD0814C0

+ * DQS Resistor + * PSU_DDR_PHY_DX8SL4DQSCTL_DQSRES 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL3OSC_RESERVED_31_30 0x0 + * DATX8 0-1 DQS Control Register + * (OFFSET, MASK, VALUE) (0XFD08151C, 0xFFFFFFFFU ,0x01264300U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL4DQSCTL_OFFSET, + 0xFFFFFFFFU, 0x01264300U); +/*##################################################################### */ - Enable Clock Gating for DX ddr_clk - PSU_DDR_PHY_DX8SL3OSC_GATEDXRDCLK 0x2 + /* + * Register : DX8SL4DXCTL2 @ 0XFD08152C - Enable Clock Gating for DX ctl_rd_clk - PSU_DDR_PHY_DX8SL3OSC_GATEDXDDRCLK 0x2 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24 0x0 - Enable Clock Gating for DX ctl_clk - PSU_DDR_PHY_DX8SL3OSC_GATEDXCTLCLK 0x2 + * Configurable Read Data Enable + * PSU_DDR_PHY_DX8SL4DXCTL2_CRDEN 0x0 - Selects the level to which clocks will be stalled when clock gating is enabled. - PSU_DDR_PHY_DX8SL3OSC_CLKLEVEL 0x0 + * OX Extension during Post-amble + * PSU_DDR_PHY_DX8SL4DXCTL2_POSOEX 0x0 - Loopback Mode - PSU_DDR_PHY_DX8SL3OSC_LBMODE 0x0 + * OE Extension during Pre-amble + * PSU_DDR_PHY_DX8SL4DXCTL2_PREOEX 0x1 - Load GSDQS LCDL with 2x the calibrated GSDQSPRD value - PSU_DDR_PHY_DX8SL3OSC_LBGSDQS 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_17 0x0 - Loopback DQS Gating - PSU_DDR_PHY_DX8SL3OSC_LBGDQS 0x0 + * I/O Assisted Gate Select + * PSU_DDR_PHY_DX8SL4DXCTL2_IOAG 0x0 - Loopback DQS Shift - PSU_DDR_PHY_DX8SL3OSC_LBDQSS 0x0 + * I/O Loopback Select + * PSU_DDR_PHY_DX8SL4DXCTL2_IOLB 0x0 - PHY High-Speed Reset - PSU_DDR_PHY_DX8SL3OSC_PHYHRST 0x1 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13 0x0 - PHY FIFO Reset - PSU_DDR_PHY_DX8SL3OSC_PHYFRST 0x1 + * Low Power Wakeup Threshold + * PSU_DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH 0xc - Delay Line Test Start - PSU_DDR_PHY_DX8SL3OSC_DLTST 0x0 + * Read Data Bus Inversion Enable + * PSU_DDR_PHY_DX8SL4DXCTL2_RDBI 0x0 - Delay Line Test Mode - PSU_DDR_PHY_DX8SL3OSC_DLTMODE 0x0 + * Write Data Bus Inversion Enable + * PSU_DDR_PHY_DX8SL4DXCTL2_WDBI 0x0 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX8SL3OSC_RESERVED_12_11 0x3 - - Oscillator Mode Write-Data Delay Line Select - PSU_DDR_PHY_DX8SL3OSC_OSCWDDL 0x3 - - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX8SL3OSC_RESERVED_8_7 0x3 - - Oscillator Mode Write-Leveling Delay Line Select - PSU_DDR_PHY_DX8SL3OSC_OSCWDL 0x3 - - Oscillator Mode Division - PSU_DDR_PHY_DX8SL3OSC_OSCDIV 0xf + * PUB Read FIFO Bypass + * PSU_DDR_PHY_DX8SL4DXCTL2_PRFBYP 0x0 - Oscillator Enable - PSU_DDR_PHY_DX8SL3OSC_OSCEN 0x0 + * DATX8 Receive FIFO Read Mode + * PSU_DDR_PHY_DX8SL4DXCTL2_RDMODE 0x0 - DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register - (OFFSET, MASK, VALUE) (0XFD0814C0, 0xFFFFFFFFU ,0x2A019FFEU) - RegMask = (DDR_PHY_DX8SL3OSC_RESERVED_31_30_MASK | DDR_PHY_DX8SL3OSC_GATEDXRDCLK_MASK | DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_MASK | DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_MASK | DDR_PHY_DX8SL3OSC_CLKLEVEL_MASK | DDR_PHY_DX8SL3OSC_LBMODE_MASK | DDR_PHY_DX8SL3OSC_LBGSDQS_MASK | DDR_PHY_DX8SL3OSC_LBGDQS_MASK | DDR_PHY_DX8SL3OSC_LBDQSS_MASK | DDR_PHY_DX8SL3OSC_PHYHRST_MASK | DDR_PHY_DX8SL3OSC_PHYFRST_MASK | DDR_PHY_DX8SL3OSC_DLTST_MASK | DDR_PHY_DX8SL3OSC_DLTMODE_MASK | DDR_PHY_DX8SL3OSC_RESERVED_12_11_MASK | DDR_PHY_DX8SL3OSC_OSCWDDL_MASK | DDR_PHY_DX8SL3OSC_RESERVED_8_7_MASK | DDR_PHY_DX8SL3OSC_OSCWDL_MASK | DDR_PHY_DX8SL3OSC_OSCDIV_MASK | DDR_PHY_DX8SL3OSC_OSCEN_MASK | 0 ); + * Disables the Read FIFO Reset + * PSU_DDR_PHY_DX8SL4DXCTL2_DISRST 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX8SL3OSC_RESERVED_31_30_SHIFT - | 0x00000002U << DDR_PHY_DX8SL3OSC_GATEDXRDCLK_SHIFT - | 0x00000002U << DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_SHIFT - | 0x00000002U << DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3OSC_CLKLEVEL_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3OSC_LBMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3OSC_LBGSDQS_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3OSC_LBGDQS_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3OSC_LBDQSS_SHIFT - | 0x00000001U << DDR_PHY_DX8SL3OSC_PHYHRST_SHIFT - | 0x00000001U << DDR_PHY_DX8SL3OSC_PHYFRST_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3OSC_DLTST_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3OSC_DLTMODE_SHIFT - | 0x00000003U << DDR_PHY_DX8SL3OSC_RESERVED_12_11_SHIFT - | 0x00000003U << DDR_PHY_DX8SL3OSC_OSCWDDL_SHIFT - | 0x00000003U << DDR_PHY_DX8SL3OSC_RESERVED_8_7_SHIFT - | 0x00000003U << DDR_PHY_DX8SL3OSC_OSCWDL_SHIFT - | 0x0000000FU << DDR_PHY_DX8SL3OSC_OSCDIV_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3OSC_OSCEN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8SL3OSC_OFFSET ,0xFFFFFFFFU ,0x2A019FFEU); - /*############################################################################################################################ */ + * Read DQS Gate I/O Loopback + * PSU_DDR_PHY_DX8SL4DXCTL2_DQSGLB 0x0 - /*Register : DX8SL3DQSCTL @ 0XFD0814DC

+ * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_0 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25 0x0 + * DATX8 0-1 DX Control Register 2 + * (OFFSET, MASK, VALUE) (0XFD08152C, 0xFFFFFFFFU ,0x00041800U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL4DXCTL2_OFFSET, + 0xFFFFFFFFU, 0x00041800U); +/*##################################################################### */ - Read Path Rise-to-Rise Mode - PSU_DDR_PHY_DX8SL3DQSCTL_RRRMODE 0x1 + /* + * Register : DX8SL4IOCR @ 0XFD081530 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL4IOCR_RESERVED_31 0x0 - Write Path Rise-to-Rise Mode - PSU_DDR_PHY_DX8SL3DQSCTL_WRRMODE 0x1 + * PVREF_DAC REFSEL range select + * PSU_DDR_PHY_DX8SL4IOCR_DXDACRANGE 0x7 - DQS Gate Extension - PSU_DDR_PHY_DX8SL3DQSCTL_DQSGX 0x0 + * IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring + * PSU_DDR_PHY_DX8SL4IOCR_DXVREFIOM 0x0 - Low Power PLL Power Down - PSU_DDR_PHY_DX8SL3DQSCTL_LPPLLPD 0x1 + * DX IO Mode + * PSU_DDR_PHY_DX8SL4IOCR_DXIOM 0x2 - Low Power I/O Power Down - PSU_DDR_PHY_DX8SL3DQSCTL_LPIOPD 0x1 + * DX IO Transmitter Mode + * PSU_DDR_PHY_DX8SL4IOCR_DXTXM 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15 0x0 + * DX IO Receiver Mode + * PSU_DDR_PHY_DX8SL4IOCR_DXRXM 0x0 - QS Counter Enable - PSU_DDR_PHY_DX8SL3DQSCTL_QSCNTEN 0x1 + * DATX8 0-1 I/O Configuration Register + * (OFFSET, MASK, VALUE) (0XFD081530, 0xFFFFFFFFU ,0x70800000U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL4IOCR_OFFSET, 0xFFFFFFFFU, 0x70800000U); +/*##################################################################### */ - Unused DQ I/O Mode - PSU_DDR_PHY_DX8SL3DQSCTL_UDQIOM 0x0 + /* + * Register : DX8SLbPLLCR0 @ 0XFD0817C4 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10 0x0 + * PLL Bypass + * PSU_DDR_PHY_DX8SLBPLLCR0_PLLBYP 0x0 - Data Slew Rate - PSU_DDR_PHY_DX8SL3DQSCTL_DXSR 0x3 - - DQS_N Resistor - PSU_DDR_PHY_DX8SL3DQSCTL_DQSNRES 0x0 - - DQS Resistor - PSU_DDR_PHY_DX8SL3DQSCTL_DQSRES 0x0 - - DATX8 0-1 DQS Control Register - (OFFSET, MASK, VALUE) (0XFD0814DC, 0xFFFFFFFFU ,0x01264300U) - RegMask = (DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_MASK | DDR_PHY_DX8SL3DQSCTL_RRRMODE_MASK | DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_MASK | DDR_PHY_DX8SL3DQSCTL_WRRMODE_MASK | DDR_PHY_DX8SL3DQSCTL_DQSGX_MASK | DDR_PHY_DX8SL3DQSCTL_LPPLLPD_MASK | DDR_PHY_DX8SL3DQSCTL_LPIOPD_MASK | DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_MASK | DDR_PHY_DX8SL3DQSCTL_QSCNTEN_MASK | DDR_PHY_DX8SL3DQSCTL_UDQIOM_MASK | DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_MASK | DDR_PHY_DX8SL3DQSCTL_DXSR_MASK | DDR_PHY_DX8SL3DQSCTL_DQSNRES_MASK | DDR_PHY_DX8SL3DQSCTL_DQSRES_MASK | 0 ); + * PLL Reset + * PSU_DDR_PHY_DX8SLBPLLCR0_PLLRST 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_SHIFT - | 0x00000001U << DDR_PHY_DX8SL3DQSCTL_RRRMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_SHIFT - | 0x00000001U << DDR_PHY_DX8SL3DQSCTL_WRRMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3DQSCTL_DQSGX_SHIFT - | 0x00000001U << DDR_PHY_DX8SL3DQSCTL_LPPLLPD_SHIFT - | 0x00000001U << DDR_PHY_DX8SL3DQSCTL_LPIOPD_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_SHIFT - | 0x00000001U << DDR_PHY_DX8SL3DQSCTL_QSCNTEN_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3DQSCTL_UDQIOM_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_SHIFT - | 0x00000003U << DDR_PHY_DX8SL3DQSCTL_DXSR_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3DQSCTL_DQSNRES_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3DQSCTL_DQSRES_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8SL3DQSCTL_OFFSET ,0xFFFFFFFFU ,0x01264300U); - /*############################################################################################################################ */ - - /*Register : DX8SL3DXCTL2 @ 0XFD0814EC

- - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24 0x0 - - Configurable Read Data Enable - PSU_DDR_PHY_DX8SL3DXCTL2_CRDEN 0x0 - - OX Extension during Post-amble - PSU_DDR_PHY_DX8SL3DXCTL2_POSOEX 0x0 - - OE Extension during Pre-amble - PSU_DDR_PHY_DX8SL3DXCTL2_PREOEX 0x1 - - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_17 0x0 - - I/O Assisted Gate Select - PSU_DDR_PHY_DX8SL3DXCTL2_IOAG 0x0 + * PLL Power Down + * PSU_DDR_PHY_DX8SLBPLLCR0_PLLPD 0x0 - I/O Loopback Select - PSU_DDR_PHY_DX8SL3DXCTL2_IOLB 0x0 + * Reference Stop Mode + * PSU_DDR_PHY_DX8SLBPLLCR0_RSTOPM 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13 0x0 + * PLL Frequency Select + * PSU_DDR_PHY_DX8SLBPLLCR0_FRQSEL 0x1 - Low Power Wakeup Threshold - PSU_DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH 0xc + * Relock Mode + * PSU_DDR_PHY_DX8SLBPLLCR0_RLOCKM 0x0 - Read Data Bus Inversion Enable - PSU_DDR_PHY_DX8SL3DXCTL2_RDBI 0x0 + * Charge Pump Proportional Current Control + * PSU_DDR_PHY_DX8SLBPLLCR0_CPPC 0x8 - Write Data Bus Inversion Enable - PSU_DDR_PHY_DX8SL3DXCTL2_WDBI 0x0 + * Charge Pump Integrating Current Control + * PSU_DDR_PHY_DX8SLBPLLCR0_CPIC 0x0 - PUB Read FIFO Bypass - PSU_DDR_PHY_DX8SL3DXCTL2_PRFBYP 0x0 + * Gear Shift + * PSU_DDR_PHY_DX8SLBPLLCR0_GSHIFT 0x0 - DATX8 Receive FIFO Read Mode - PSU_DDR_PHY_DX8SL3DXCTL2_RDMODE 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SLBPLLCR0_RESERVED_11_9 0x0 - Disables the Read FIFO Reset - PSU_DDR_PHY_DX8SL3DXCTL2_DISRST 0x0 + * Analog Test Enable (ATOEN) + * PSU_DDR_PHY_DX8SLBPLLCR0_ATOEN 0x0 - Read DQS Gate I/O Loopback - PSU_DDR_PHY_DX8SL3DXCTL2_DQSGLB 0x0 + * Analog Test Control + * PSU_DDR_PHY_DX8SLBPLLCR0_ATC 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_0 0x0 + * Digital Test Control + * PSU_DDR_PHY_DX8SLBPLLCR0_DTC 0x0 - DATX8 0-1 DX Control Register 2 - (OFFSET, MASK, VALUE) (0XFD0814EC, 0xFFFFFFFFU ,0x00041800U) - RegMask = (DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_MASK | DDR_PHY_DX8SL3DXCTL2_CRDEN_MASK | DDR_PHY_DX8SL3DXCTL2_POSOEX_MASK | DDR_PHY_DX8SL3DXCTL2_PREOEX_MASK | DDR_PHY_DX8SL3DXCTL2_RESERVED_17_MASK | DDR_PHY_DX8SL3DXCTL2_IOAG_MASK | DDR_PHY_DX8SL3DXCTL2_IOLB_MASK | DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_MASK | DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_MASK | DDR_PHY_DX8SL3DXCTL2_RDBI_MASK | DDR_PHY_DX8SL3DXCTL2_WDBI_MASK | DDR_PHY_DX8SL3DXCTL2_PRFBYP_MASK | DDR_PHY_DX8SL3DXCTL2_RDMODE_MASK | DDR_PHY_DX8SL3DXCTL2_DISRST_MASK | DDR_PHY_DX8SL3DXCTL2_DQSGLB_MASK | DDR_PHY_DX8SL3DXCTL2_RESERVED_0_MASK | 0 ); + * DAXT8 0-8 PLL Control Register 0 + * (OFFSET, MASK, VALUE) (0XFD0817C4, 0xFFFFFFFFU ,0x01100000U) + */ + PSU_Mask_Write(DDR_PHY_DX8SLBPLLCR0_OFFSET, + 0xFFFFFFFFU, 0x01100000U); +/*##################################################################### */ - RegVal = ((0x00000000U << DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_CRDEN_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_POSOEX_SHIFT - | 0x00000001U << DDR_PHY_DX8SL3DXCTL2_PREOEX_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_RESERVED_17_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_IOAG_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_IOLB_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_SHIFT - | 0x0000000CU << DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_RDBI_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_WDBI_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_PRFBYP_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_RDMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_DISRST_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_DQSGLB_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_RESERVED_0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8SL3DXCTL2_OFFSET ,0xFFFFFFFFU ,0x00041800U); - /*############################################################################################################################ */ + /* + * Register : DX8SLbDQSCTL @ 0XFD0817DC - /*Register : DX8SL3IOCR @ 0XFD0814F0

+ * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL3IOCR_RESERVED_31 0x0 + * Read Path Rise-to-Rise Mode + * PSU_DDR_PHY_DX8SLBDQSCTL_RRRMODE 0x1 - PVREF_DAC REFSEL range select - PSU_DDR_PHY_DX8SL3IOCR_DXDACRANGE 0x7 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22 0x0 - IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring - PSU_DDR_PHY_DX8SL3IOCR_DXVREFIOM 0x0 + * Write Path Rise-to-Rise Mode + * PSU_DDR_PHY_DX8SLBDQSCTL_WRRMODE 0x1 - DX IO Mode - PSU_DDR_PHY_DX8SL3IOCR_DXIOM 0x2 + * DQS Gate Extension + * PSU_DDR_PHY_DX8SLBDQSCTL_DQSGX 0x0 - DX IO Transmitter Mode - PSU_DDR_PHY_DX8SL3IOCR_DXTXM 0x0 + * Low Power PLL Power Down + * PSU_DDR_PHY_DX8SLBDQSCTL_LPPLLPD 0x1 - DX IO Receiver Mode - PSU_DDR_PHY_DX8SL3IOCR_DXRXM 0x0 + * Low Power I/O Power Down + * PSU_DDR_PHY_DX8SLBDQSCTL_LPIOPD 0x1 - DATX8 0-1 I/O Configuration Register - (OFFSET, MASK, VALUE) (0XFD0814F0, 0xFFFFFFFFU ,0x70800000U) - RegMask = (DDR_PHY_DX8SL3IOCR_RESERVED_31_MASK | DDR_PHY_DX8SL3IOCR_DXDACRANGE_MASK | DDR_PHY_DX8SL3IOCR_DXVREFIOM_MASK | DDR_PHY_DX8SL3IOCR_DXIOM_MASK | DDR_PHY_DX8SL3IOCR_DXTXM_MASK | DDR_PHY_DX8SL3IOCR_DXRXM_MASK | 0 ); + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX8SL3IOCR_RESERVED_31_SHIFT - | 0x00000007U << DDR_PHY_DX8SL3IOCR_DXDACRANGE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3IOCR_DXVREFIOM_SHIFT - | 0x00000002U << DDR_PHY_DX8SL3IOCR_DXIOM_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3IOCR_DXTXM_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3IOCR_DXRXM_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8SL3IOCR_OFFSET ,0xFFFFFFFFU ,0x70800000U); - /*############################################################################################################################ */ + * QS Counter Enable + * PSU_DDR_PHY_DX8SLBDQSCTL_QSCNTEN 0x1 - /*Register : DX8SL4OSC @ 0XFD081500

+ * Unused DQ I/O Mode + * PSU_DDR_PHY_DX8SLBDQSCTL_UDQIOM 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL4OSC_RESERVED_31_30 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10 0x0 - Enable Clock Gating for DX ddr_clk - PSU_DDR_PHY_DX8SL4OSC_GATEDXRDCLK 0x2 + * Data Slew Rate + * PSU_DDR_PHY_DX8SLBDQSCTL_DXSR 0x3 - Enable Clock Gating for DX ctl_rd_clk - PSU_DDR_PHY_DX8SL4OSC_GATEDXDDRCLK 0x2 + * DQS# Resistor + * PSU_DDR_PHY_DX8SLBDQSCTL_DQSNRES 0xc - Enable Clock Gating for DX ctl_clk - PSU_DDR_PHY_DX8SL4OSC_GATEDXCTLCLK 0x2 + * DQS Resistor + * PSU_DDR_PHY_DX8SLBDQSCTL_DQSRES 0x4 - Selects the level to which clocks will be stalled when clock gating is enabled. - PSU_DDR_PHY_DX8SL4OSC_CLKLEVEL 0x0 + * DATX8 0-8 DQS Control Register + * (OFFSET, MASK, VALUE) (0XFD0817DC, 0xFFFFFFFFU ,0x012643C4U) + */ + PSU_Mask_Write(DDR_PHY_DX8SLBDQSCTL_OFFSET, + 0xFFFFFFFFU, 0x012643C4U); +/*##################################################################### */ - Loopback Mode - PSU_DDR_PHY_DX8SL4OSC_LBMODE 0x0 - Load GSDQS LCDL with 2x the calibrated GSDQSPRD value - PSU_DDR_PHY_DX8SL4OSC_LBGSDQS 0x0 - - Loopback DQS Gating - PSU_DDR_PHY_DX8SL4OSC_LBGDQS 0x0 - - Loopback DQS Shift - PSU_DDR_PHY_DX8SL4OSC_LBDQSS 0x0 - - PHY High-Speed Reset - PSU_DDR_PHY_DX8SL4OSC_PHYHRST 0x1 - - PHY FIFO Reset - PSU_DDR_PHY_DX8SL4OSC_PHYFRST 0x1 - - Delay Line Test Start - PSU_DDR_PHY_DX8SL4OSC_DLTST 0x0 - - Delay Line Test Mode - PSU_DDR_PHY_DX8SL4OSC_DLTMODE 0x0 - - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX8SL4OSC_RESERVED_12_11 0x3 - - Oscillator Mode Write-Data Delay Line Select - PSU_DDR_PHY_DX8SL4OSC_OSCWDDL 0x3 - - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX8SL4OSC_RESERVED_8_7 0x3 - - Oscillator Mode Write-Leveling Delay Line Select - PSU_DDR_PHY_DX8SL4OSC_OSCWDL 0x3 - - Oscillator Mode Division - PSU_DDR_PHY_DX8SL4OSC_OSCDIV 0xf - - Oscillator Enable - PSU_DDR_PHY_DX8SL4OSC_OSCEN 0x0 - - DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register - (OFFSET, MASK, VALUE) (0XFD081500, 0xFFFFFFFFU ,0x2A019FFEU) - RegMask = (DDR_PHY_DX8SL4OSC_RESERVED_31_30_MASK | DDR_PHY_DX8SL4OSC_GATEDXRDCLK_MASK | DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_MASK | DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_MASK | DDR_PHY_DX8SL4OSC_CLKLEVEL_MASK | DDR_PHY_DX8SL4OSC_LBMODE_MASK | DDR_PHY_DX8SL4OSC_LBGSDQS_MASK | DDR_PHY_DX8SL4OSC_LBGDQS_MASK | DDR_PHY_DX8SL4OSC_LBDQSS_MASK | DDR_PHY_DX8SL4OSC_PHYHRST_MASK | DDR_PHY_DX8SL4OSC_PHYFRST_MASK | DDR_PHY_DX8SL4OSC_DLTST_MASK | DDR_PHY_DX8SL4OSC_DLTMODE_MASK | DDR_PHY_DX8SL4OSC_RESERVED_12_11_MASK | DDR_PHY_DX8SL4OSC_OSCWDDL_MASK | DDR_PHY_DX8SL4OSC_RESERVED_8_7_MASK | DDR_PHY_DX8SL4OSC_OSCWDL_MASK | DDR_PHY_DX8SL4OSC_OSCDIV_MASK | DDR_PHY_DX8SL4OSC_OSCEN_MASK | 0 ); - - RegVal = ((0x00000000U << DDR_PHY_DX8SL4OSC_RESERVED_31_30_SHIFT - | 0x00000002U << DDR_PHY_DX8SL4OSC_GATEDXRDCLK_SHIFT - | 0x00000002U << DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_SHIFT - | 0x00000002U << DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4OSC_CLKLEVEL_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4OSC_LBMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4OSC_LBGSDQS_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4OSC_LBGDQS_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4OSC_LBDQSS_SHIFT - | 0x00000001U << DDR_PHY_DX8SL4OSC_PHYHRST_SHIFT - | 0x00000001U << DDR_PHY_DX8SL4OSC_PHYFRST_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4OSC_DLTST_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4OSC_DLTMODE_SHIFT - | 0x00000003U << DDR_PHY_DX8SL4OSC_RESERVED_12_11_SHIFT - | 0x00000003U << DDR_PHY_DX8SL4OSC_OSCWDDL_SHIFT - | 0x00000003U << DDR_PHY_DX8SL4OSC_RESERVED_8_7_SHIFT - | 0x00000003U << DDR_PHY_DX8SL4OSC_OSCWDL_SHIFT - | 0x0000000FU << DDR_PHY_DX8SL4OSC_OSCDIV_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4OSC_OSCEN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8SL4OSC_OFFSET ,0xFFFFFFFFU ,0x2A019FFEU); - /*############################################################################################################################ */ - - /*Register : DX8SL4DQSCTL @ 0XFD08151C

- - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25 0x0 - - Read Path Rise-to-Rise Mode - PSU_DDR_PHY_DX8SL4DQSCTL_RRRMODE 0x1 - - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22 0x0 - - Write Path Rise-to-Rise Mode - PSU_DDR_PHY_DX8SL4DQSCTL_WRRMODE 0x1 - - DQS Gate Extension - PSU_DDR_PHY_DX8SL4DQSCTL_DQSGX 0x0 - - Low Power PLL Power Down - PSU_DDR_PHY_DX8SL4DQSCTL_LPPLLPD 0x1 - - Low Power I/O Power Down - PSU_DDR_PHY_DX8SL4DQSCTL_LPIOPD 0x1 - - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15 0x0 - - QS Counter Enable - PSU_DDR_PHY_DX8SL4DQSCTL_QSCNTEN 0x1 - - Unused DQ I/O Mode - PSU_DDR_PHY_DX8SL4DQSCTL_UDQIOM 0x0 - - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10 0x0 - - Data Slew Rate - PSU_DDR_PHY_DX8SL4DQSCTL_DXSR 0x3 - - DQS_N Resistor - PSU_DDR_PHY_DX8SL4DQSCTL_DQSNRES 0x0 - - DQS Resistor - PSU_DDR_PHY_DX8SL4DQSCTL_DQSRES 0x0 - - DATX8 0-1 DQS Control Register - (OFFSET, MASK, VALUE) (0XFD08151C, 0xFFFFFFFFU ,0x01264300U) - RegMask = (DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_MASK | DDR_PHY_DX8SL4DQSCTL_RRRMODE_MASK | DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_MASK | DDR_PHY_DX8SL4DQSCTL_WRRMODE_MASK | DDR_PHY_DX8SL4DQSCTL_DQSGX_MASK | DDR_PHY_DX8SL4DQSCTL_LPPLLPD_MASK | DDR_PHY_DX8SL4DQSCTL_LPIOPD_MASK | DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_MASK | DDR_PHY_DX8SL4DQSCTL_QSCNTEN_MASK | DDR_PHY_DX8SL4DQSCTL_UDQIOM_MASK | DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_MASK | DDR_PHY_DX8SL4DQSCTL_DXSR_MASK | DDR_PHY_DX8SL4DQSCTL_DQSNRES_MASK | DDR_PHY_DX8SL4DQSCTL_DQSRES_MASK | 0 ); - - RegVal = ((0x00000000U << DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_SHIFT - | 0x00000001U << DDR_PHY_DX8SL4DQSCTL_RRRMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_SHIFT - | 0x00000001U << DDR_PHY_DX8SL4DQSCTL_WRRMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4DQSCTL_DQSGX_SHIFT - | 0x00000001U << DDR_PHY_DX8SL4DQSCTL_LPPLLPD_SHIFT - | 0x00000001U << DDR_PHY_DX8SL4DQSCTL_LPIOPD_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_SHIFT - | 0x00000001U << DDR_PHY_DX8SL4DQSCTL_QSCNTEN_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4DQSCTL_UDQIOM_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_SHIFT - | 0x00000003U << DDR_PHY_DX8SL4DQSCTL_DXSR_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4DQSCTL_DQSNRES_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4DQSCTL_DQSRES_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8SL4DQSCTL_OFFSET ,0xFFFFFFFFU ,0x01264300U); - /*############################################################################################################################ */ - - /*Register : DX8SL4DXCTL2 @ 0XFD08152C

- - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24 0x0 - - Configurable Read Data Enable - PSU_DDR_PHY_DX8SL4DXCTL2_CRDEN 0x0 - - OX Extension during Post-amble - PSU_DDR_PHY_DX8SL4DXCTL2_POSOEX 0x0 - - OE Extension during Pre-amble - PSU_DDR_PHY_DX8SL4DXCTL2_PREOEX 0x1 - - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_17 0x0 - - I/O Assisted Gate Select - PSU_DDR_PHY_DX8SL4DXCTL2_IOAG 0x0 - - I/O Loopback Select - PSU_DDR_PHY_DX8SL4DXCTL2_IOLB 0x0 - - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13 0x0 - - Low Power Wakeup Threshold - PSU_DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH 0xc - - Read Data Bus Inversion Enable - PSU_DDR_PHY_DX8SL4DXCTL2_RDBI 0x0 - - Write Data Bus Inversion Enable - PSU_DDR_PHY_DX8SL4DXCTL2_WDBI 0x0 - - PUB Read FIFO Bypass - PSU_DDR_PHY_DX8SL4DXCTL2_PRFBYP 0x0 - - DATX8 Receive FIFO Read Mode - PSU_DDR_PHY_DX8SL4DXCTL2_RDMODE 0x0 - - Disables the Read FIFO Reset - PSU_DDR_PHY_DX8SL4DXCTL2_DISRST 0x0 - - Read DQS Gate I/O Loopback - PSU_DDR_PHY_DX8SL4DXCTL2_DQSGLB 0x0 - - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_0 0x0 - - DATX8 0-1 DX Control Register 2 - (OFFSET, MASK, VALUE) (0XFD08152C, 0xFFFFFFFFU ,0x00041800U) - RegMask = (DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_MASK | DDR_PHY_DX8SL4DXCTL2_CRDEN_MASK | DDR_PHY_DX8SL4DXCTL2_POSOEX_MASK | DDR_PHY_DX8SL4DXCTL2_PREOEX_MASK | DDR_PHY_DX8SL4DXCTL2_RESERVED_17_MASK | DDR_PHY_DX8SL4DXCTL2_IOAG_MASK | DDR_PHY_DX8SL4DXCTL2_IOLB_MASK | DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_MASK | DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_MASK | DDR_PHY_DX8SL4DXCTL2_RDBI_MASK | DDR_PHY_DX8SL4DXCTL2_WDBI_MASK | DDR_PHY_DX8SL4DXCTL2_PRFBYP_MASK | DDR_PHY_DX8SL4DXCTL2_RDMODE_MASK | DDR_PHY_DX8SL4DXCTL2_DISRST_MASK | DDR_PHY_DX8SL4DXCTL2_DQSGLB_MASK | DDR_PHY_DX8SL4DXCTL2_RESERVED_0_MASK | 0 ); - - RegVal = ((0x00000000U << DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_CRDEN_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_POSOEX_SHIFT - | 0x00000001U << DDR_PHY_DX8SL4DXCTL2_PREOEX_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_RESERVED_17_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_IOAG_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_IOLB_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_SHIFT - | 0x0000000CU << DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_RDBI_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_WDBI_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_PRFBYP_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_RDMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_DISRST_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_DQSGLB_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_RESERVED_0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8SL4DXCTL2_OFFSET ,0xFFFFFFFFU ,0x00041800U); - /*############################################################################################################################ */ - - /*Register : DX8SL4IOCR @ 0XFD081530

- - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL4IOCR_RESERVED_31 0x0 - - PVREF_DAC REFSEL range select - PSU_DDR_PHY_DX8SL4IOCR_DXDACRANGE 0x7 - - IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring - PSU_DDR_PHY_DX8SL4IOCR_DXVREFIOM 0x0 - - DX IO Mode - PSU_DDR_PHY_DX8SL4IOCR_DXIOM 0x2 - - DX IO Transmitter Mode - PSU_DDR_PHY_DX8SL4IOCR_DXTXM 0x0 - - DX IO Receiver Mode - PSU_DDR_PHY_DX8SL4IOCR_DXRXM 0x0 - - DATX8 0-1 I/O Configuration Register - (OFFSET, MASK, VALUE) (0XFD081530, 0xFFFFFFFFU ,0x70800000U) - RegMask = (DDR_PHY_DX8SL4IOCR_RESERVED_31_MASK | DDR_PHY_DX8SL4IOCR_DXDACRANGE_MASK | DDR_PHY_DX8SL4IOCR_DXVREFIOM_MASK | DDR_PHY_DX8SL4IOCR_DXIOM_MASK | DDR_PHY_DX8SL4IOCR_DXTXM_MASK | DDR_PHY_DX8SL4IOCR_DXRXM_MASK | 0 ); - - RegVal = ((0x00000000U << DDR_PHY_DX8SL4IOCR_RESERVED_31_SHIFT - | 0x00000007U << DDR_PHY_DX8SL4IOCR_DXDACRANGE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4IOCR_DXVREFIOM_SHIFT - | 0x00000002U << DDR_PHY_DX8SL4IOCR_DXIOM_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4IOCR_DXTXM_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4IOCR_DXRXM_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8SL4IOCR_OFFSET ,0xFFFFFFFFU ,0x70800000U); - /*############################################################################################################################ */ - - /*Register : DX8SLbDQSCTL @ 0XFD0817DC

- - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25 0x0 - - Read Path Rise-to-Rise Mode - PSU_DDR_PHY_DX8SLBDQSCTL_RRRMODE 0x1 - - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22 0x0 - - Write Path Rise-to-Rise Mode - PSU_DDR_PHY_DX8SLBDQSCTL_WRRMODE 0x1 - - DQS Gate Extension - PSU_DDR_PHY_DX8SLBDQSCTL_DQSGX 0x0 - - Low Power PLL Power Down - PSU_DDR_PHY_DX8SLBDQSCTL_LPPLLPD 0x1 - - Low Power I/O Power Down - PSU_DDR_PHY_DX8SLBDQSCTL_LPIOPD 0x1 - - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15 0x0 - - QS Counter Enable - PSU_DDR_PHY_DX8SLBDQSCTL_QSCNTEN 0x1 - - Unused DQ I/O Mode - PSU_DDR_PHY_DX8SLBDQSCTL_UDQIOM 0x0 - - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10 0x0 - - Data Slew Rate - PSU_DDR_PHY_DX8SLBDQSCTL_DXSR 0x3 - - DQS# Resistor - PSU_DDR_PHY_DX8SLBDQSCTL_DQSNRES 0xc - - DQS Resistor - PSU_DDR_PHY_DX8SLBDQSCTL_DQSRES 0x4 - - DATX8 0-8 DQS Control Register - (OFFSET, MASK, VALUE) (0XFD0817DC, 0xFFFFFFFFU ,0x012643C4U) - RegMask = (DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_MASK | DDR_PHY_DX8SLBDQSCTL_RRRMODE_MASK | DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_MASK | DDR_PHY_DX8SLBDQSCTL_WRRMODE_MASK | DDR_PHY_DX8SLBDQSCTL_DQSGX_MASK | DDR_PHY_DX8SLBDQSCTL_LPPLLPD_MASK | DDR_PHY_DX8SLBDQSCTL_LPIOPD_MASK | DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_MASK | DDR_PHY_DX8SLBDQSCTL_QSCNTEN_MASK | DDR_PHY_DX8SLBDQSCTL_UDQIOM_MASK | DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_MASK | DDR_PHY_DX8SLBDQSCTL_DXSR_MASK | DDR_PHY_DX8SLBDQSCTL_DQSNRES_MASK | DDR_PHY_DX8SLBDQSCTL_DQSRES_MASK | 0 ); - - RegVal = ((0x00000000U << DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_SHIFT - | 0x00000001U << DDR_PHY_DX8SLBDQSCTL_RRRMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_SHIFT - | 0x00000001U << DDR_PHY_DX8SLBDQSCTL_WRRMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8SLBDQSCTL_DQSGX_SHIFT - | 0x00000001U << DDR_PHY_DX8SLBDQSCTL_LPPLLPD_SHIFT - | 0x00000001U << DDR_PHY_DX8SLBDQSCTL_LPIOPD_SHIFT - | 0x00000000U << DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_SHIFT - | 0x00000001U << DDR_PHY_DX8SLBDQSCTL_QSCNTEN_SHIFT - | 0x00000000U << DDR_PHY_DX8SLBDQSCTL_UDQIOM_SHIFT - | 0x00000000U << DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_SHIFT - | 0x00000003U << DDR_PHY_DX8SLBDQSCTL_DXSR_SHIFT - | 0x0000000CU << DDR_PHY_DX8SLBDQSCTL_DQSNRES_SHIFT - | 0x00000004U << DDR_PHY_DX8SLBDQSCTL_DQSRES_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8SLBDQSCTL_OFFSET ,0xFFFFFFFFU ,0x012643C4U); - /*############################################################################################################################ */ - - /*Register : PIR @ 0XFD080004

- - Reserved. Return zeroes on reads. - PSU_DDR_PHY_PIR_RESERVED_31 0x0 - - Impedance Calibration Bypass - PSU_DDR_PHY_PIR_ZCALBYP 0x0 - - Digital Delay Line (DDL) Calibration Pause - PSU_DDR_PHY_PIR_DCALPSE 0x0 - - Reserved. Return zeroes on reads. - PSU_DDR_PHY_PIR_RESERVED_28_21 0x0 - - Write DQS2DQ Training - PSU_DDR_PHY_PIR_DQS2DQ 0x0 - - RDIMM Initialization - PSU_DDR_PHY_PIR_RDIMMINIT 0x0 - - Controller DRAM Initialization - PSU_DDR_PHY_PIR_CTLDINIT 0x1 - - VREF Training - PSU_DDR_PHY_PIR_VREF 0x0 - - Static Read Training - PSU_DDR_PHY_PIR_SRD 0x0 - - Write Data Eye Training - PSU_DDR_PHY_PIR_WREYE 0x0 - - Read Data Eye Training - PSU_DDR_PHY_PIR_RDEYE 0x0 - - Write Data Bit Deskew - PSU_DDR_PHY_PIR_WRDSKW 0x0 - - Read Data Bit Deskew - PSU_DDR_PHY_PIR_RDDSKW 0x0 - - Write Leveling Adjust - PSU_DDR_PHY_PIR_WLADJ 0x0 - - Read DQS Gate Training - PSU_DDR_PHY_PIR_QSGATE 0x0 - - Write Leveling - PSU_DDR_PHY_PIR_WL 0x0 - - DRAM Initialization - PSU_DDR_PHY_PIR_DRAMINIT 0x0 - - DRAM Reset (DDR3/DDR4/LPDDR4 Only) - PSU_DDR_PHY_PIR_DRAMRST 0x0 - - PHY Reset - PSU_DDR_PHY_PIR_PHYRST 0x1 - - Digital Delay Line (DDL) Calibration - PSU_DDR_PHY_PIR_DCAL 0x1 - - PLL Initialiazation - PSU_DDR_PHY_PIR_PLLINIT 0x1 - - Reserved. Return zeroes on reads. - PSU_DDR_PHY_PIR_RESERVED_3 0x0 - - CA Training - PSU_DDR_PHY_PIR_CA 0x0 - - Impedance Calibration - PSU_DDR_PHY_PIR_ZCAL 0x1 - - Initialization Trigger - PSU_DDR_PHY_PIR_INIT 0x1 - - PHY Initialization Register - (OFFSET, MASK, VALUE) (0XFD080004, 0xFFFFFFFFU ,0x00040073U) - RegMask = (DDR_PHY_PIR_RESERVED_31_MASK | DDR_PHY_PIR_ZCALBYP_MASK | DDR_PHY_PIR_DCALPSE_MASK | DDR_PHY_PIR_RESERVED_28_21_MASK | DDR_PHY_PIR_DQS2DQ_MASK | DDR_PHY_PIR_RDIMMINIT_MASK | DDR_PHY_PIR_CTLDINIT_MASK | DDR_PHY_PIR_VREF_MASK | DDR_PHY_PIR_SRD_MASK | DDR_PHY_PIR_WREYE_MASK | DDR_PHY_PIR_RDEYE_MASK | DDR_PHY_PIR_WRDSKW_MASK | DDR_PHY_PIR_RDDSKW_MASK | DDR_PHY_PIR_WLADJ_MASK | DDR_PHY_PIR_QSGATE_MASK | DDR_PHY_PIR_WL_MASK | DDR_PHY_PIR_DRAMINIT_MASK | DDR_PHY_PIR_DRAMRST_MASK | DDR_PHY_PIR_PHYRST_MASK | DDR_PHY_PIR_DCAL_MASK | DDR_PHY_PIR_PLLINIT_MASK | DDR_PHY_PIR_RESERVED_3_MASK | DDR_PHY_PIR_CA_MASK | DDR_PHY_PIR_ZCAL_MASK | DDR_PHY_PIR_INIT_MASK | 0 ); - - RegVal = ((0x00000000U << DDR_PHY_PIR_RESERVED_31_SHIFT - | 0x00000000U << DDR_PHY_PIR_ZCALBYP_SHIFT - | 0x00000000U << DDR_PHY_PIR_DCALPSE_SHIFT - | 0x00000000U << DDR_PHY_PIR_RESERVED_28_21_SHIFT - | 0x00000000U << DDR_PHY_PIR_DQS2DQ_SHIFT - | 0x00000000U << DDR_PHY_PIR_RDIMMINIT_SHIFT - | 0x00000001U << DDR_PHY_PIR_CTLDINIT_SHIFT - | 0x00000000U << DDR_PHY_PIR_VREF_SHIFT - | 0x00000000U << DDR_PHY_PIR_SRD_SHIFT - | 0x00000000U << DDR_PHY_PIR_WREYE_SHIFT - | 0x00000000U << DDR_PHY_PIR_RDEYE_SHIFT - | 0x00000000U << DDR_PHY_PIR_WRDSKW_SHIFT - | 0x00000000U << DDR_PHY_PIR_RDDSKW_SHIFT - | 0x00000000U << DDR_PHY_PIR_WLADJ_SHIFT - | 0x00000000U << DDR_PHY_PIR_QSGATE_SHIFT - | 0x00000000U << DDR_PHY_PIR_WL_SHIFT - | 0x00000000U << DDR_PHY_PIR_DRAMINIT_SHIFT - | 0x00000000U << DDR_PHY_PIR_DRAMRST_SHIFT - | 0x00000001U << DDR_PHY_PIR_PHYRST_SHIFT - | 0x00000001U << DDR_PHY_PIR_DCAL_SHIFT - | 0x00000001U << DDR_PHY_PIR_PLLINIT_SHIFT - | 0x00000000U << DDR_PHY_PIR_RESERVED_3_SHIFT - | 0x00000000U << DDR_PHY_PIR_CA_SHIFT - | 0x00000001U << DDR_PHY_PIR_ZCAL_SHIFT - | 0x00000001U << DDR_PHY_PIR_INIT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_PIR_OFFSET ,0xFFFFFFFFU ,0x00040073U); - /*############################################################################################################################ */ - - - return 1; + return 1; } -unsigned long psu_mio_init_data() { - // : MIO PROGRAMMING - /*Register : MIO_PIN_0 @ 0XFF180000

+unsigned long psu_ddr_qos_init_data(void) +{ - Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out- (QSPI Clock) - PSU_IOU_SLCR_MIO_PIN_0_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_0_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[0]- (Test Scan Port) = test_scan, Outp - t, test_scan_out[0]- (Test Scan Port) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_0_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[0]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[0]- (GPIO bank 0) 1= can - , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa - ) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Cloc - ) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_ - lk- (Trace Port Clock) - PSU_IOU_SLCR_MIO_PIN_0_L3_SEL 0 - - Configures MIO Pin 0 peripheral interface mapping. S - (OFFSET, MASK, VALUE) (0XFF180000, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_0_L0_SEL_MASK | IOU_SLCR_MIO_PIN_0_L1_SEL_MASK | IOU_SLCR_MIO_PIN_0_L2_SEL_MASK | IOU_SLCR_MIO_PIN_0_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_0_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_0_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_0_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_0_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_0_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_1 @ 0XFF180004

- - Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (QSPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Data - us) - PSU_IOU_SLCR_MIO_PIN_1_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_1_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[1]- (Test Scan Port) = test_scan, Outp - t, test_scan_out[1]- (Test Scan Port) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_1_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[1]- (GPIO bank 0) 1= can - , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal - 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_o - t- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control - Signal) - PSU_IOU_SLCR_MIO_PIN_1_L3_SEL 0 - - Configures MIO Pin 1 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180004, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_1_L0_SEL_MASK | IOU_SLCR_MIO_PIN_1_L1_SEL_MASK | IOU_SLCR_MIO_PIN_1_L2_SEL_MASK | IOU_SLCR_MIO_PIN_1_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_1_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_1_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_1_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_1_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_1_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_2 @ 0XFF180008

- - Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus) - PSU_IOU_SLCR_MIO_PIN_2_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_2_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[2]- (Test Scan Port) = test_scan, Outp - t, test_scan_out[2]- (Test Scan Port) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_2_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[2]- (GPIO bank 0) 1= can - , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal - 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc2, Input, ttc2_clk_in - (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[0]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_2_L3_SEL 0 - - Configures MIO Pin 2 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180008, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_2_L0_SEL_MASK | IOU_SLCR_MIO_PIN_2_L1_SEL_MASK | IOU_SLCR_MIO_PIN_2_L2_SEL_MASK | IOU_SLCR_MIO_PIN_2_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_2_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_2_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_2_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_2_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_2_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_3 @ 0XFF18000C

- - Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus) - PSU_IOU_SLCR_MIO_PIN_3_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_3_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[3]- (Test Scan Port) = test_scan, Outp - t, test_scan_out[3]- (Test Scan Port) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_3_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[3]- (GPIO bank 0) 1= can - , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa - ) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0 - - (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial - output) 7= trace, Output, tracedq[1]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_3_L3_SEL 0 - - Configures MIO Pin 3 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF18000C, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_3_L0_SEL_MASK | IOU_SLCR_MIO_PIN_3_L1_SEL_MASK | IOU_SLCR_MIO_PIN_3_L2_SEL_MASK | IOU_SLCR_MIO_PIN_3_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_3_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_3_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_3_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_3_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_3_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_4 @ 0XFF180010

- - Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- (QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Data - us) - PSU_IOU_SLCR_MIO_PIN_4_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_4_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[4]- (Test Scan Port) = test_scan, Outp - t, test_scan_out[4]- (Test Scan Port) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_4_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[4]- (GPIO bank 0) 1= can - , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa - ) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_s - - (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, - utput, tracedq[2]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_4_L3_SEL 0 - - Configures MIO Pin 4 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180010, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_4_L0_SEL_MASK | IOU_SLCR_MIO_PIN_4_L1_SEL_MASK | IOU_SLCR_MIO_PIN_4_L2_SEL_MASK | IOU_SLCR_MIO_PIN_4_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_4_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_4_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_4_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_4_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_4_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_5 @ 0XFF180014

- - Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out- (QSPI Slave Select) - PSU_IOU_SLCR_MIO_PIN_5_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_5_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[5]- (Test Scan Port) = test_scan, Outp - t, test_scan_out[5]- (Test Scan Port) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_5_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[5]- (GPIO bank 0) 1= can - , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal - 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi0 - si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7 - trace, Output, tracedq[3]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_5_L3_SEL 0 - - Configures MIO Pin 5 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180014, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_5_L0_SEL_MASK | IOU_SLCR_MIO_PIN_5_L1_SEL_MASK | IOU_SLCR_MIO_PIN_5_L2_SEL_MASK | IOU_SLCR_MIO_PIN_5_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_5_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_5_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_5_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_5_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_5_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_6 @ 0XFF180018

- - Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_clk_for_lpbk- (QSPI Clock to be fed-back) - PSU_IOU_SLCR_MIO_PIN_6_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_6_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[6]- (Test Scan Port) = test_scan, Outp - t, test_scan_out[6]- (Test Scan Port) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_6_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[6]- (GPIO bank 0) 1= can - , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal - 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1 - sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, - Output, tracedq[4]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_6_L3_SEL 0 - - Configures MIO Pin 6 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180018, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_6_L0_SEL_MASK | IOU_SLCR_MIO_PIN_6_L1_SEL_MASK | IOU_SLCR_MIO_PIN_6_L2_SEL_MASK | IOU_SLCR_MIO_PIN_6_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_6_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_6_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_6_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_6_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_6_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_7 @ 0XFF18001C

- - Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out_upper- (QSPI Slave Select upper) - PSU_IOU_SLCR_MIO_PIN_7_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_7_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[7]- (Test Scan Port) = test_scan, Outp - t, test_scan_out[7]- (Test Scan Port) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_7_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[7]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[7]- (GPIO bank 0) 1= can - , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa - ) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= - tc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, - racedq[5]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_7_L3_SEL 0 - - Configures MIO Pin 7 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF18001C, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_7_L0_SEL_MASK | IOU_SLCR_MIO_PIN_7_L1_SEL_MASK | IOU_SLCR_MIO_PIN_7_L2_SEL_MASK | IOU_SLCR_MIO_PIN_7_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_7_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_7_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_7_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_7_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_7_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_8 @ 0XFF180020

- - Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[0]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe - [0]- (QSPI Upper Databus) - PSU_IOU_SLCR_MIO_PIN_8_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_8_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[8]- (Test Scan Port) = test_scan, Outp - t, test_scan_out[8]- (Test Scan Port) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_8_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[8]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[8]- (GPIO bank 0) 1= can - , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa - ) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc - , Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Tr - ce Port Databus) - PSU_IOU_SLCR_MIO_PIN_8_L3_SEL 0 - - Configures MIO Pin 8 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180020, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_8_L0_SEL_MASK | IOU_SLCR_MIO_PIN_8_L1_SEL_MASK | IOU_SLCR_MIO_PIN_8_L2_SEL_MASK | IOU_SLCR_MIO_PIN_8_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_8_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_8_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_8_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_8_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_8_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_9 @ 0XFF180024

- - Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[1]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe - [1]- (QSPI Upper Databus) - PSU_IOU_SLCR_MIO_PIN_9_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NAND chip enable) - PSU_IOU_SLCR_MIO_PIN_9_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[9]- (Test Scan Port) = test_scan, Outp - t, test_scan_out[9]- (Test Scan Port) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_9_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[9]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[9]- (GPIO bank 0) 1= can - , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal - 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, - utput, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (U - RT receiver serial input) 7= trace, Output, tracedq[7]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_9_L3_SEL 0 - - Configures MIO Pin 9 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180024, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_9_L0_SEL_MASK | IOU_SLCR_MIO_PIN_9_L1_SEL_MASK | IOU_SLCR_MIO_PIN_9_L2_SEL_MASK | IOU_SLCR_MIO_PIN_9_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_9_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_9_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_9_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_9_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_9_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_10 @ 0XFF180028

- - Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[2]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe - [2]- (QSPI Upper Databus) - PSU_IOU_SLCR_MIO_PIN_10_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (NAND Ready/Busy) - PSU_IOU_SLCR_MIO_PIN_10_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[10]- (Test Scan Port) = test_scan, Out - ut, test_scan_out[10]- (Test Scan Port) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_10_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[10]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[10]- (GPIO bank 0) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_ - o- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outp - t, tracedq[8]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_10_L3_SEL 0 - - Configures MIO Pin 10 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180028, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_10_L0_SEL_MASK | IOU_SLCR_MIO_PIN_10_L1_SEL_MASK | IOU_SLCR_MIO_PIN_10_L2_SEL_MASK | IOU_SLCR_MIO_PIN_10_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_10_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_10_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_10_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_10_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_10_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_11 @ 0XFF18002C

- - Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[3]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe - [3]- (QSPI Upper Databus) - PSU_IOU_SLCR_MIO_PIN_11_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (NAND Ready/Busy) - PSU_IOU_SLCR_MIO_PIN_11_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[11]- (Test Scan Port) = test_scan, Out - ut, test_scan_out[11]- (Test Scan Port) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_11_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s - i1_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o - tput) 7= trace, Output, tracedq[9]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_11_L3_SEL 0 - - Configures MIO Pin 11 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF18002C, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_11_L0_SEL_MASK | IOU_SLCR_MIO_PIN_11_L1_SEL_MASK | IOU_SLCR_MIO_PIN_11_L2_SEL_MASK | IOU_SLCR_MIO_PIN_11_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_11_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_11_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_11_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_11_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_11_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_12 @ 0XFF180030

- - Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out_upper- (QSPI Upper Clock) - PSU_IOU_SLCR_MIO_PIN_12_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NAND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe - - PSU_IOU_SLCR_MIO_PIN_12_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[12]- (Test Scan Port) = test_scan, Out - ut, test_scan_out[12]- (Test Scan Port) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_12_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[12]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[12]- (GPIO bank 0) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Cl - ck) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trac - dq[10]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_12_L3_SEL 0 - - Configures MIO Pin 12 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180030, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_12_L0_SEL_MASK | IOU_SLCR_MIO_PIN_12_L1_SEL_MASK | IOU_SLCR_MIO_PIN_12_L2_SEL_MASK | IOU_SLCR_MIO_PIN_12_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_12_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_12_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_12_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_12_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_12_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_13 @ 0XFF180034

- - Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_13_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[0]- (NAND chip enable) - PSU_IOU_SLCR_MIO_PIN_13_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8 - bit Data bus) 2= test_scan, Input, test_scan_in[13]- (Test Scan Port) = test_scan, Output, test_scan_out[13]- (Test Scan Port - 3= Not Used - PSU_IOU_SLCR_MIO_PIN_13_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[13]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[13]- (GPIO bank 0) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave - out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq[11]- (Trace Port Dat - bus) - PSU_IOU_SLCR_MIO_PIN_13_L3_SEL 0 - - Configures MIO Pin 13 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180034, 0x000000FEU ,0x00000000U) - RegMask = (IOU_SLCR_MIO_PIN_13_L0_SEL_MASK | IOU_SLCR_MIO_PIN_13_L1_SEL_MASK | IOU_SLCR_MIO_PIN_13_L2_SEL_MASK | IOU_SLCR_MIO_PIN_13_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_13_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_13_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_13_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_13_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_13_OFFSET ,0x000000FEU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_14 @ 0XFF180038

- - Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_14_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_cle- (NAND Command Latch Enable) - PSU_IOU_SLCR_MIO_PIN_14_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8 - bit Data bus) 2= test_scan, Input, test_scan_in[14]- (Test Scan Port) = test_scan, Output, test_scan_out[14]- (Test Scan Port - 3= Not Used - PSU_IOU_SLCR_MIO_PIN_14_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, Input, ttc0_clk_ - n- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_14_L3_SEL 2 - - Configures MIO Pin 14 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180038, 0x000000FEU ,0x00000040U) - RegMask = (IOU_SLCR_MIO_PIN_14_L0_SEL_MASK | IOU_SLCR_MIO_PIN_14_L1_SEL_MASK | IOU_SLCR_MIO_PIN_14_L2_SEL_MASK | IOU_SLCR_MIO_PIN_14_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_14_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_14_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_14_L2_SEL_SHIFT - | 0x00000002U << IOU_SLCR_MIO_PIN_14_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_14_OFFSET ,0x000000FEU ,0x00000040U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_15 @ 0XFF18003C

- - Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_15_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ale- (NAND Address Latch Enable) - PSU_IOU_SLCR_MIO_PIN_15_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8 - bit Data bus) 2= test_scan, Input, test_scan_in[15]- (Test Scan Port) = test_scan, Output, test_scan_out[15]- (Test Scan Port - 3= Not Used - PSU_IOU_SLCR_MIO_PIN_15_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[15]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[15]- (GPIO bank 0) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out - 0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter seri - l output) 7= trace, Output, tracedq[13]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_15_L3_SEL 2 - - Configures MIO Pin 15 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF18003C, 0x000000FEU ,0x00000040U) - RegMask = (IOU_SLCR_MIO_PIN_15_L0_SEL_MASK | IOU_SLCR_MIO_PIN_15_L1_SEL_MASK | IOU_SLCR_MIO_PIN_15_L2_SEL_MASK | IOU_SLCR_MIO_PIN_15_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_15_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_15_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_15_L2_SEL_SHIFT - | 0x00000002U << IOU_SLCR_MIO_PIN_15_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_15_OFFSET ,0x000000FEU ,0x00000040U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_16 @ 0XFF180040

- - Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_16_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[0]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[0]- (NAND - ata Bus) - PSU_IOU_SLCR_MIO_PIN_16_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8 - bit Data bus) 2= test_scan, Input, test_scan_in[16]- (Test Scan Port) = test_scan, Output, test_scan_out[16]- (Test Scan Port - 3= Not Used - PSU_IOU_SLCR_MIO_PIN_16_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[16]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[16]- (GPIO bank 0) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0 - so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace - Output, tracedq[14]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_16_L3_SEL 2 - - Configures MIO Pin 16 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180040, 0x000000FEU ,0x00000040U) - RegMask = (IOU_SLCR_MIO_PIN_16_L0_SEL_MASK | IOU_SLCR_MIO_PIN_16_L1_SEL_MASK | IOU_SLCR_MIO_PIN_16_L2_SEL_MASK | IOU_SLCR_MIO_PIN_16_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_16_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_16_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_16_L2_SEL_SHIFT - | 0x00000002U << IOU_SLCR_MIO_PIN_16_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_16_OFFSET ,0x000000FEU ,0x00000040U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_17 @ 0XFF180044

- - Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_17_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[1]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[1]- (NAND - ata Bus) - PSU_IOU_SLCR_MIO_PIN_17_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8 - bit Data bus) 2= test_scan, Input, test_scan_in[17]- (Test Scan Port) = test_scan, Output, test_scan_out[17]- (Test Scan Port - 3= Not Used - PSU_IOU_SLCR_MIO_PIN_17_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[17]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[17]- (GPIO bank 0) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, sp - 0_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) - 7= trace, Output, tracedq[15]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_17_L3_SEL 2 - - Configures MIO Pin 17 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180044, 0x000000FEU ,0x00000040U) - RegMask = (IOU_SLCR_MIO_PIN_17_L0_SEL_MASK | IOU_SLCR_MIO_PIN_17_L1_SEL_MASK | IOU_SLCR_MIO_PIN_17_L2_SEL_MASK | IOU_SLCR_MIO_PIN_17_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_17_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_17_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_17_L2_SEL_SHIFT - | 0x00000002U << IOU_SLCR_MIO_PIN_17_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_17_OFFSET ,0x000000FEU ,0x00000040U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_18 @ 0XFF180048

- - Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_18_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[2]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[2]- (NAND - ata Bus) - PSU_IOU_SLCR_MIO_PIN_18_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8 - bit Data bus) 2= test_scan, Input, test_scan_in[18]- (Test Scan Port) = test_scan, Output, test_scan_out[18]- (Test Scan Port - 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper) - PSU_IOU_SLCR_MIO_PIN_18_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[18]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[18]- (GPIO bank 0) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_ - o- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used - PSU_IOU_SLCR_MIO_PIN_18_L3_SEL 6 - - Configures MIO Pin 18 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180048, 0x000000FEU ,0x000000C0U) - RegMask = (IOU_SLCR_MIO_PIN_18_L0_SEL_MASK | IOU_SLCR_MIO_PIN_18_L1_SEL_MASK | IOU_SLCR_MIO_PIN_18_L2_SEL_MASK | IOU_SLCR_MIO_PIN_18_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_18_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_18_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_18_L2_SEL_SHIFT - | 0x00000006U << IOU_SLCR_MIO_PIN_18_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_18_OFFSET ,0x000000FEU ,0x000000C0U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_19 @ 0XFF18004C

- - Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_19_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[3]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[3]- (NAND - ata Bus) - PSU_IOU_SLCR_MIO_PIN_19_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8 - bit Data bus) 2= test_scan, Input, test_scan_in[19]- (Test Scan Port) = test_scan, Output, test_scan_out[19]- (Test Scan Port - 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper) - PSU_IOU_SLCR_MIO_PIN_19_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[19]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[19]- (GPIO bank 0) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5 - ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used - PSU_IOU_SLCR_MIO_PIN_19_L3_SEL 6 - - Configures MIO Pin 19 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF18004C, 0x000000FEU ,0x000000C0U) - RegMask = (IOU_SLCR_MIO_PIN_19_L0_SEL_MASK | IOU_SLCR_MIO_PIN_19_L1_SEL_MASK | IOU_SLCR_MIO_PIN_19_L2_SEL_MASK | IOU_SLCR_MIO_PIN_19_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_19_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_19_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_19_L2_SEL_SHIFT - | 0x00000006U << IOU_SLCR_MIO_PIN_19_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_19_OFFSET ,0x000000FEU ,0x000000C0U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_20 @ 0XFF180050

- - Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_20_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[4]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[4]- (NAND - ata Bus) - PSU_IOU_SLCR_MIO_PIN_20_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8 - bit Data bus) 2= test_scan, Input, test_scan_in[20]- (Test Scan Port) = test_scan, Output, test_scan_out[20]- (Test Scan Port - 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper) - PSU_IOU_SLCR_MIO_PIN_20_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[20]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[20]- (GPIO bank 0) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= t - c1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Used - PSU_IOU_SLCR_MIO_PIN_20_L3_SEL 6 - - Configures MIO Pin 20 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180050, 0x000000FEU ,0x000000C0U) - RegMask = (IOU_SLCR_MIO_PIN_20_L0_SEL_MASK | IOU_SLCR_MIO_PIN_20_L1_SEL_MASK | IOU_SLCR_MIO_PIN_20_L2_SEL_MASK | IOU_SLCR_MIO_PIN_20_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_20_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_20_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_20_L2_SEL_SHIFT - | 0x00000006U << IOU_SLCR_MIO_PIN_20_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_20_OFFSET ,0x000000FEU ,0x000000C0U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_21 @ 0XFF180054

- - Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_21_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[5]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[5]- (NAND - ata Bus) - PSU_IOU_SLCR_MIO_PIN_21_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Comman - Indicator) 2= test_scan, Input, test_scan_in[21]- (Test Scan Port) = test_scan, Output, test_scan_out[21]- (Test Scan Port) - = csu, Input, csu_ext_tamper- (CSU Ext Tamper) - PSU_IOU_SLCR_MIO_PIN_21_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[21]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[21]- (GPIO bank 0) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1 - Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- - UART receiver serial input) 7= Not Used - PSU_IOU_SLCR_MIO_PIN_21_L3_SEL 6 - - Configures MIO Pin 21 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180054, 0x000000FEU ,0x000000C0U) - RegMask = (IOU_SLCR_MIO_PIN_21_L0_SEL_MASK | IOU_SLCR_MIO_PIN_21_L1_SEL_MASK | IOU_SLCR_MIO_PIN_21_L2_SEL_MASK | IOU_SLCR_MIO_PIN_21_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_21_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_21_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_21_L2_SEL_SHIFT - | 0x00000006U << IOU_SLCR_MIO_PIN_21_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_21_OFFSET ,0x000000FEU ,0x000000C0U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_22 @ 0XFF180058

- - Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_22_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_we_b- (NAND Write Enable) - PSU_IOU_SLCR_MIO_PIN_22_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= test_scan, Input, test_scan_in[22]- - (Test Scan Port) = test_scan, Output, test_scan_out[22]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper) - PSU_IOU_SLCR_MIO_PIN_22_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[22]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[22]- (GPIO bank 0) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, sp - 1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not - sed - PSU_IOU_SLCR_MIO_PIN_22_L3_SEL 0 - - Configures MIO Pin 22 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180058, 0x000000FEU ,0x00000000U) - RegMask = (IOU_SLCR_MIO_PIN_22_L0_SEL_MASK | IOU_SLCR_MIO_PIN_22_L1_SEL_MASK | IOU_SLCR_MIO_PIN_22_L2_SEL_MASK | IOU_SLCR_MIO_PIN_22_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_22_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_22_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_22_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_22_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_22_OFFSET ,0x000000FEU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_23 @ 0XFF18005C

- - Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_23_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[6]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[6]- (NAND - ata Bus) - PSU_IOU_SLCR_MIO_PIN_23_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= test_scan, Input, test_scan_in - 23]- (Test Scan Port) = test_scan, Output, test_scan_out[23]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper - - PSU_IOU_SLCR_MIO_PIN_23_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[23]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[23]- (GPIO bank 0) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s - i1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o - tput) 7= Not Used - PSU_IOU_SLCR_MIO_PIN_23_L3_SEL 0 - - Configures MIO Pin 23 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF18005C, 0x000000FEU ,0x00000000U) - RegMask = (IOU_SLCR_MIO_PIN_23_L0_SEL_MASK | IOU_SLCR_MIO_PIN_23_L1_SEL_MASK | IOU_SLCR_MIO_PIN_23_L2_SEL_MASK | IOU_SLCR_MIO_PIN_23_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_23_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_23_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_23_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_23_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_23_OFFSET ,0x000000FEU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_24 @ 0XFF180060

- - Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_24_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[7]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[7]- (NAND - ata Bus) - PSU_IOU_SLCR_MIO_PIN_24_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= test_scan, Input, test - scan_in[24]- (Test Scan Port) = test_scan, Output, test_scan_out[24]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ex - Tamper) - PSU_IOU_SLCR_MIO_PIN_24_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[24]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[24]- (GPIO bank 0) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= Not Used 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, - Output, ua1_txd- (UART transmitter serial output) 7= Not Used - PSU_IOU_SLCR_MIO_PIN_24_L3_SEL 1 - - Configures MIO Pin 24 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180060, 0x000000FEU ,0x00000020U) - RegMask = (IOU_SLCR_MIO_PIN_24_L0_SEL_MASK | IOU_SLCR_MIO_PIN_24_L1_SEL_MASK | IOU_SLCR_MIO_PIN_24_L2_SEL_MASK | IOU_SLCR_MIO_PIN_24_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_24_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_24_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_24_L2_SEL_SHIFT - | 0x00000001U << IOU_SLCR_MIO_PIN_24_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_24_OFFSET ,0x000000FEU ,0x00000020U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_25 @ 0XFF180064

- - Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_25_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_re_n- (NAND Read Enable) - PSU_IOU_SLCR_MIO_PIN_25_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= test_scan, Input, - test_scan_in[25]- (Test Scan Port) = test_scan, Output, test_scan_out[25]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (C - U Ext Tamper) - PSU_IOU_SLCR_MIO_PIN_25_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[25]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[25]- (GPIO bank 0) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= Not Used 5= ttc3, Output, ttc3_wave_out- (TTC Waveform - lock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used - PSU_IOU_SLCR_MIO_PIN_25_L3_SEL 1 - - Configures MIO Pin 25 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180064, 0x000000FEU ,0x00000020U) - RegMask = (IOU_SLCR_MIO_PIN_25_L0_SEL_MASK | IOU_SLCR_MIO_PIN_25_L1_SEL_MASK | IOU_SLCR_MIO_PIN_25_L2_SEL_MASK | IOU_SLCR_MIO_PIN_25_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_25_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_25_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_25_L2_SEL_SHIFT - | 0x00000001U << IOU_SLCR_MIO_PIN_25_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_25_OFFSET ,0x000000FEU ,0x00000020U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_26 @ 0XFF180068

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_clk- (TX RGMII clock) - PSU_IOU_SLCR_MIO_PIN_26_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NAND chip enable) - PSU_IOU_SLCR_MIO_PIN_26_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[0]- (PMU GPI) 2= test_scan, Input, test_scan_in[26]- (Test Sc - n Port) = test_scan, Output, test_scan_out[26]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper) - PSU_IOU_SLCR_MIO_PIN_26_L2_SEL 0 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[0]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[0]- (GPIO bank 1) 1= can - , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal - 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Clock - 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- - Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_26_L3_SEL 0 - - Configures MIO Pin 26 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180068, 0x000000FEU ,0x00000000U) - RegMask = (IOU_SLCR_MIO_PIN_26_L0_SEL_MASK | IOU_SLCR_MIO_PIN_26_L1_SEL_MASK | IOU_SLCR_MIO_PIN_26_L2_SEL_MASK | IOU_SLCR_MIO_PIN_26_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_26_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_26_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_26_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_26_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_26_OFFSET ,0x000000FEU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_27 @ 0XFF18006C

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[0]- (TX RGMII data) - PSU_IOU_SLCR_MIO_PIN_27_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (NAND Ready/Busy) - PSU_IOU_SLCR_MIO_PIN_27_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[1]- (PMU GPI) 2= test_scan, Input, test_scan_in[27]- (Test Sc - n Port) = test_scan, Output, test_scan_out[27]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Outp - t, dp_aux_data_out- (Dp Aux Data) - PSU_IOU_SLCR_MIO_PIN_27_L2_SEL 3 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[1]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[1]- (GPIO bank 1) 1= can - , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa - ) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_ - ut- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port - atabus) - PSU_IOU_SLCR_MIO_PIN_27_L3_SEL 0 - - Configures MIO Pin 27 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF18006C, 0x000000FEU ,0x00000018U) - RegMask = (IOU_SLCR_MIO_PIN_27_L0_SEL_MASK | IOU_SLCR_MIO_PIN_27_L1_SEL_MASK | IOU_SLCR_MIO_PIN_27_L2_SEL_MASK | IOU_SLCR_MIO_PIN_27_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_27_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_27_L1_SEL_SHIFT - | 0x00000003U << IOU_SLCR_MIO_PIN_27_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_27_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_27_OFFSET ,0x000000FEU ,0x00000018U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_28 @ 0XFF180070

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[1]- (TX RGMII data) - PSU_IOU_SLCR_MIO_PIN_28_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (NAND Ready/Busy) - PSU_IOU_SLCR_MIO_PIN_28_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[2]- (PMU GPI) 2= test_scan, Input, test_scan_in[28]- (Test Sc - n Port) = test_scan, Output, test_scan_out[28]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug) - PSU_IOU_SLCR_MIO_PIN_28_L2_SEL 3 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[2]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[2]- (GPIO bank 1) 1= can - , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa - ) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc1, Input, ttc1_clk_i - - (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_28_L3_SEL 0 - - Configures MIO Pin 28 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180070, 0x000000FEU ,0x00000018U) - RegMask = (IOU_SLCR_MIO_PIN_28_L0_SEL_MASK | IOU_SLCR_MIO_PIN_28_L1_SEL_MASK | IOU_SLCR_MIO_PIN_28_L2_SEL_MASK | IOU_SLCR_MIO_PIN_28_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_28_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_28_L1_SEL_SHIFT - | 0x00000003U << IOU_SLCR_MIO_PIN_28_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_28_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_28_OFFSET ,0x000000FEU ,0x00000018U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_29 @ 0XFF180074

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[2]- (TX RGMII data) - PSU_IOU_SLCR_MIO_PIN_29_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal) - PSU_IOU_SLCR_MIO_PIN_29_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[3]- (PMU GPI) 2= test_scan, Input, test_scan_in[29]- (Test Sc - n Port) = test_scan, Output, test_scan_out[29]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Outp - t, dp_aux_data_out- (Dp Aux Data) - PSU_IOU_SLCR_MIO_PIN_29_L2_SEL 3 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[3]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[3]- (GPIO bank 1) 1= can - , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal - 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0] - (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial inpu - ) 7= trace, Output, tracedq[7]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_29_L3_SEL 0 - - Configures MIO Pin 29 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180074, 0x000000FEU ,0x00000018U) - RegMask = (IOU_SLCR_MIO_PIN_29_L0_SEL_MASK | IOU_SLCR_MIO_PIN_29_L1_SEL_MASK | IOU_SLCR_MIO_PIN_29_L2_SEL_MASK | IOU_SLCR_MIO_PIN_29_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_29_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_29_L1_SEL_SHIFT - | 0x00000003U << IOU_SLCR_MIO_PIN_29_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_29_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_29_OFFSET ,0x000000FEU ,0x00000018U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_30 @ 0XFF180078

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[3]- (TX RGMII data) - PSU_IOU_SLCR_MIO_PIN_30_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal) - PSU_IOU_SLCR_MIO_PIN_30_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[4]- (PMU GPI) 2= test_scan, Input, test_scan_in[30]- (Test Sc - n Port) = test_scan, Output, test_scan_out[30]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug) - PSU_IOU_SLCR_MIO_PIN_30_L2_SEL 3 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[4]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[4]- (GPIO bank 1) 1= can - , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal - 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_so - (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output - tracedq[8]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_30_L3_SEL 0 - - Configures MIO Pin 30 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180078, 0x000000FEU ,0x00000018U) - RegMask = (IOU_SLCR_MIO_PIN_30_L0_SEL_MASK | IOU_SLCR_MIO_PIN_30_L1_SEL_MASK | IOU_SLCR_MIO_PIN_30_L2_SEL_MASK | IOU_SLCR_MIO_PIN_30_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_30_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_30_L1_SEL_SHIFT - | 0x00000003U << IOU_SLCR_MIO_PIN_30_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_30_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_30_OFFSET ,0x000000FEU ,0x00000018U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_31 @ 0XFF18007C

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ctl- (TX RGMII control) - PSU_IOU_SLCR_MIO_PIN_31_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal) - PSU_IOU_SLCR_MIO_PIN_31_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[5]- (PMU GPI) 2= test_scan, Input, test_scan_in[31]- (Test Sc - n Port) = test_scan, Output, test_scan_out[31]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper) - PSU_IOU_SLCR_MIO_PIN_31_L2_SEL 0 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[5]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[5]- (GPIO bank 1) 1= can - , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa - ) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi - _si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial out - ut) 7= trace, Output, tracedq[9]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_31_L3_SEL 0 - - Configures MIO Pin 31 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF18007C, 0x000000FEU ,0x00000000U) - RegMask = (IOU_SLCR_MIO_PIN_31_L0_SEL_MASK | IOU_SLCR_MIO_PIN_31_L1_SEL_MASK | IOU_SLCR_MIO_PIN_31_L2_SEL_MASK | IOU_SLCR_MIO_PIN_31_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_31_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_31_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_31_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_31_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_31_OFFSET ,0x000000FEU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_32 @ 0XFF180080

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_clk- (RX RGMII clock) - PSU_IOU_SLCR_MIO_PIN_32_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NAND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe - - PSU_IOU_SLCR_MIO_PIN_32_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[0]- (PMU GPI) 2= test_scan, Input, test_scan_in[32]- (Test S - an Port) = test_scan, Output, test_scan_out[32]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper) - PSU_IOU_SLCR_MIO_PIN_32_L2_SEL 1 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[6]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[6]- (GPIO bank 1) 1= can - , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa - ) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi - _sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= - race, Output, tracedq[10]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_32_L3_SEL 0 - - Configures MIO Pin 32 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180080, 0x000000FEU ,0x00000008U) - RegMask = (IOU_SLCR_MIO_PIN_32_L0_SEL_MASK | IOU_SLCR_MIO_PIN_32_L1_SEL_MASK | IOU_SLCR_MIO_PIN_32_L2_SEL_MASK | IOU_SLCR_MIO_PIN_32_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_32_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_32_L1_SEL_SHIFT - | 0x00000001U << IOU_SLCR_MIO_PIN_32_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_32_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_32_OFFSET ,0x000000FEU ,0x00000008U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_33 @ 0XFF180084

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[0]- (RX RGMII data) - PSU_IOU_SLCR_MIO_PIN_33_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal) - PSU_IOU_SLCR_MIO_PIN_33_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[1]- (PMU GPI) 2= test_scan, Input, test_scan_in[33]- (Test S - an Port) = test_scan, Output, test_scan_out[33]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper) - PSU_IOU_SLCR_MIO_PIN_33_L2_SEL 1 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[7]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[7]- (GPIO bank 1) 1= can - , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal - 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= t - c3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, traced - [11]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_33_L3_SEL 0 - - Configures MIO Pin 33 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180084, 0x000000FEU ,0x00000008U) - RegMask = (IOU_SLCR_MIO_PIN_33_L0_SEL_MASK | IOU_SLCR_MIO_PIN_33_L1_SEL_MASK | IOU_SLCR_MIO_PIN_33_L2_SEL_MASK | IOU_SLCR_MIO_PIN_33_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_33_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_33_L1_SEL_SHIFT - | 0x00000001U << IOU_SLCR_MIO_PIN_33_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_33_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_33_OFFSET ,0x000000FEU ,0x00000008U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_34 @ 0XFF180088

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[1]- (RX RGMII data) - PSU_IOU_SLCR_MIO_PIN_34_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal) - PSU_IOU_SLCR_MIO_PIN_34_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[2]- (PMU GPI) 2= test_scan, Input, test_scan_in[34]- (Test S - an Port) = test_scan, Output, test_scan_out[34]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Out - ut, dp_aux_data_out- (Dp Aux Data) - PSU_IOU_SLCR_MIO_PIN_34_L2_SEL 1 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[8]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[8]- (GPIO bank 1) 1= can - , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal - 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc2 - Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace P - rt Databus) - PSU_IOU_SLCR_MIO_PIN_34_L3_SEL 0 - - Configures MIO Pin 34 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180088, 0x000000FEU ,0x00000008U) - RegMask = (IOU_SLCR_MIO_PIN_34_L0_SEL_MASK | IOU_SLCR_MIO_PIN_34_L1_SEL_MASK | IOU_SLCR_MIO_PIN_34_L2_SEL_MASK | IOU_SLCR_MIO_PIN_34_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_34_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_34_L1_SEL_SHIFT - | 0x00000001U << IOU_SLCR_MIO_PIN_34_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_34_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_34_OFFSET ,0x000000FEU ,0x00000008U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_35 @ 0XFF18008C

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[2]- (RX RGMII data) - PSU_IOU_SLCR_MIO_PIN_35_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal) - PSU_IOU_SLCR_MIO_PIN_35_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[3]- (PMU GPI) 2= test_scan, Input, test_scan_in[35]- (Test S - an Port) = test_scan, Output, test_scan_out[35]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug) - PSU_IOU_SLCR_MIO_PIN_35_L2_SEL 1 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[9]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[9]- (GPIO bank 1) 1= can - , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa - ) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, - Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- - UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_35_L3_SEL 0 - - Configures MIO Pin 35 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF18008C, 0x000000FEU ,0x00000008U) - RegMask = (IOU_SLCR_MIO_PIN_35_L0_SEL_MASK | IOU_SLCR_MIO_PIN_35_L1_SEL_MASK | IOU_SLCR_MIO_PIN_35_L2_SEL_MASK | IOU_SLCR_MIO_PIN_35_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_35_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_35_L1_SEL_SHIFT - | 0x00000001U << IOU_SLCR_MIO_PIN_35_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_35_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_35_OFFSET ,0x000000FEU ,0x00000008U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_36 @ 0XFF180090

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[3]- (RX RGMII data) - PSU_IOU_SLCR_MIO_PIN_36_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal) - PSU_IOU_SLCR_MIO_PIN_36_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[4]- (PMU GPI) 2= test_scan, Input, test_scan_in[36]- (Test S - an Port) = test_scan, Output, test_scan_out[36]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Out - ut, dp_aux_data_out- (Dp Aux Data) - PSU_IOU_SLCR_MIO_PIN_36_L2_SEL 1 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[10]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[10]- (GPIO bank 1) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1 - so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace - Output, tracedq[14]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_36_L3_SEL 0 - - Configures MIO Pin 36 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180090, 0x000000FEU ,0x00000008U) - RegMask = (IOU_SLCR_MIO_PIN_36_L0_SEL_MASK | IOU_SLCR_MIO_PIN_36_L1_SEL_MASK | IOU_SLCR_MIO_PIN_36_L2_SEL_MASK | IOU_SLCR_MIO_PIN_36_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_36_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_36_L1_SEL_SHIFT - | 0x00000001U << IOU_SLCR_MIO_PIN_36_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_36_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_36_OFFSET ,0x000000FEU ,0x00000008U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_37 @ 0XFF180094

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_ctl- (RX RGMII control ) - PSU_IOU_SLCR_MIO_PIN_37_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal) - PSU_IOU_SLCR_MIO_PIN_37_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[5]- (PMU GPI) 2= test_scan, Input, test_scan_in[37]- (Test S - an Port) = test_scan, Output, test_scan_out[37]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug) - PSU_IOU_SLCR_MIO_PIN_37_L2_SEL 1 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[11]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[11]- (GPIO bank 1) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, sp - 1_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) - 7= trace, Output, tracedq[15]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_37_L3_SEL 0 - - Configures MIO Pin 37 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180094, 0x000000FEU ,0x00000008U) - RegMask = (IOU_SLCR_MIO_PIN_37_L0_SEL_MASK | IOU_SLCR_MIO_PIN_37_L1_SEL_MASK | IOU_SLCR_MIO_PIN_37_L2_SEL_MASK | IOU_SLCR_MIO_PIN_37_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_37_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_37_L1_SEL_SHIFT - | 0x00000001U << IOU_SLCR_MIO_PIN_37_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_37_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_37_OFFSET ,0x000000FEU ,0x00000008U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_38 @ 0XFF180098

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_clk- (TX RGMII clock) - PSU_IOU_SLCR_MIO_PIN_38_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_38_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= Not Used 3= Not Used - PSU_IOU_SLCR_MIO_PIN_38_L2_SEL 0 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[12]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[12]- (GPIO bank 1) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Clo - k) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, trace_clk- - (Trace Port Clock) - PSU_IOU_SLCR_MIO_PIN_38_L3_SEL 0 - - Configures MIO Pin 38 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180098, 0x000000FEU ,0x00000000U) - RegMask = (IOU_SLCR_MIO_PIN_38_L0_SEL_MASK | IOU_SLCR_MIO_PIN_38_L1_SEL_MASK | IOU_SLCR_MIO_PIN_38_L2_SEL_MASK | IOU_SLCR_MIO_PIN_38_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_38_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_38_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_38_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_38_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_38_OFFSET ,0x000000FEU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_39 @ 0XFF18009C

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[0]- (TX RGMII data) - PSU_IOU_SLCR_MIO_PIN_39_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_39_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= sd1, Input, sd1_data_i - [4]- (8-bit Data bus) = sd1, Output, sdio1_data_out[4]- (8-bit Data bus) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_39_L2_SEL 0 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[13]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[13]- (GPIO bank 1) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc0, Output, ttc0_wav - _out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, trace_ctl- (Trace Port - Control Signal) - PSU_IOU_SLCR_MIO_PIN_39_L3_SEL 0 - - Configures MIO Pin 39 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF18009C, 0x000000FEU ,0x00000000U) - RegMask = (IOU_SLCR_MIO_PIN_39_L0_SEL_MASK | IOU_SLCR_MIO_PIN_39_L1_SEL_MASK | IOU_SLCR_MIO_PIN_39_L2_SEL_MASK | IOU_SLCR_MIO_PIN_39_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_39_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_39_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_39_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_39_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_39_OFFSET ,0x000000FEU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_40 @ 0XFF1800A0

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[1]- (TX RGMII data) - PSU_IOU_SLCR_MIO_PIN_40_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_40_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Comman - Indicator) 2= sd1, Input, sd1_data_in[5]- (8-bit Data bus) = sd1, Output, sdio1_data_out[5]- (8-bit Data bus) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_40_L2_SEL 0 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[14]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[14]- (GPIO bank 1) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc3, Input, ttc3_clk - in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[0]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_40_L3_SEL 0 - - Configures MIO Pin 40 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800A0, 0x000000FEU ,0x00000000U) - RegMask = (IOU_SLCR_MIO_PIN_40_L0_SEL_MASK | IOU_SLCR_MIO_PIN_40_L1_SEL_MASK | IOU_SLCR_MIO_PIN_40_L2_SEL_MASK | IOU_SLCR_MIO_PIN_40_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_40_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_40_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_40_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_40_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_40_OFFSET ,0x000000FEU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_41 @ 0XFF1800A4

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[2]- (TX RGMII data) - PSU_IOU_SLCR_MIO_PIN_41_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_41_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8 - bit Data bus) 2= sd1, Input, sd1_data_in[6]- (8-bit Data bus) = sd1, Output, sdio1_data_out[6]- (8-bit Data bus) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_41_L2_SEL 0 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[15]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[15]- (GPIO bank 1) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[ - ]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial in - ut) 7= trace, Output, tracedq[1]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_41_L3_SEL 0 - - Configures MIO Pin 41 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800A4, 0x000000FEU ,0x00000000U) - RegMask = (IOU_SLCR_MIO_PIN_41_L0_SEL_MASK | IOU_SLCR_MIO_PIN_41_L1_SEL_MASK | IOU_SLCR_MIO_PIN_41_L2_SEL_MASK | IOU_SLCR_MIO_PIN_41_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_41_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_41_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_41_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_41_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_41_OFFSET ,0x000000FEU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_42 @ 0XFF1800A8

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[3]- (TX RGMII data) - PSU_IOU_SLCR_MIO_PIN_42_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_42_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8 - bit Data bus) 2= sd1, Input, sd1_data_in[7]- (8-bit Data bus) = sd1, Output, sdio1_data_out[7]- (8-bit Data bus) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_42_L2_SEL 0 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_ - o- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outp - t, tracedq[2]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_42_L3_SEL 0 - - Configures MIO Pin 42 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800A8, 0x000000FEU ,0x00000000U) - RegMask = (IOU_SLCR_MIO_PIN_42_L0_SEL_MASK | IOU_SLCR_MIO_PIN_42_L1_SEL_MASK | IOU_SLCR_MIO_PIN_42_L2_SEL_MASK | IOU_SLCR_MIO_PIN_42_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_42_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_42_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_42_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_42_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_42_OFFSET ,0x000000FEU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_43 @ 0XFF1800AC

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ctl- (TX RGMII control) - PSU_IOU_SLCR_MIO_PIN_43_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_43_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8 - bit Data bus) 2= sd1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_43_L2_SEL 2 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, s - i0_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o - tput) 7= trace, Output, tracedq[3]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_43_L3_SEL 0 - - Configures MIO Pin 43 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800AC, 0x000000FEU ,0x00000010U) - RegMask = (IOU_SLCR_MIO_PIN_43_L0_SEL_MASK | IOU_SLCR_MIO_PIN_43_L1_SEL_MASK | IOU_SLCR_MIO_PIN_43_L2_SEL_MASK | IOU_SLCR_MIO_PIN_43_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_43_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_43_L1_SEL_SHIFT - | 0x00000002U << IOU_SLCR_MIO_PIN_43_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_43_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_43_OFFSET ,0x000000FEU ,0x00000010U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_44 @ 0XFF1800B0

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_clk- (RX RGMII clock) - PSU_IOU_SLCR_MIO_PIN_44_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_44_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8 - bit Data bus) 2= sd1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_44_L2_SEL 2 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[18]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[18]- (GPIO bank 1) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, s - i1_sclk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7 - Not Used - PSU_IOU_SLCR_MIO_PIN_44_L3_SEL 0 - - Configures MIO Pin 44 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800B0, 0x000000FEU ,0x00000010U) - RegMask = (IOU_SLCR_MIO_PIN_44_L0_SEL_MASK | IOU_SLCR_MIO_PIN_44_L1_SEL_MASK | IOU_SLCR_MIO_PIN_44_L2_SEL_MASK | IOU_SLCR_MIO_PIN_44_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_44_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_44_L1_SEL_SHIFT - | 0x00000002U << IOU_SLCR_MIO_PIN_44_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_44_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_44_OFFSET ,0x000000FEU ,0x00000010U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_45 @ 0XFF1800B4

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[0]- (RX RGMII data) - PSU_IOU_SLCR_MIO_PIN_45_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_45_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8 - bit Data bus) 2= sd1, Input, sdio1_cd_n- (SD card detect from connector) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_45_L2_SEL 2 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[19]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[19]- (GPIO bank 1) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= - ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used - PSU_IOU_SLCR_MIO_PIN_45_L3_SEL 0 - - Configures MIO Pin 45 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800B4, 0x000000FEU ,0x00000010U) - RegMask = (IOU_SLCR_MIO_PIN_45_L0_SEL_MASK | IOU_SLCR_MIO_PIN_45_L1_SEL_MASK | IOU_SLCR_MIO_PIN_45_L2_SEL_MASK | IOU_SLCR_MIO_PIN_45_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_45_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_45_L1_SEL_SHIFT - | 0x00000002U << IOU_SLCR_MIO_PIN_45_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_45_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_45_OFFSET ,0x000000FEU ,0x00000010U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_46 @ 0XFF1800B8

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[1]- (RX RGMII data) - PSU_IOU_SLCR_MIO_PIN_46_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_46_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8 - bit Data bus) 2= sd1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_out[0]- (8-bit Data bus) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_46_L2_SEL 2 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= tt - 0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used - PSU_IOU_SLCR_MIO_PIN_46_L3_SEL 0 - - Configures MIO Pin 46 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800B8, 0x000000FEU ,0x00000010U) - RegMask = (IOU_SLCR_MIO_PIN_46_L0_SEL_MASK | IOU_SLCR_MIO_PIN_46_L1_SEL_MASK | IOU_SLCR_MIO_PIN_46_L2_SEL_MASK | IOU_SLCR_MIO_PIN_46_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_46_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_46_L1_SEL_SHIFT - | 0x00000002U << IOU_SLCR_MIO_PIN_46_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_46_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_46_OFFSET ,0x000000FEU ,0x00000010U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_47 @ 0XFF1800BC

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[2]- (RX RGMII data) - PSU_IOU_SLCR_MIO_PIN_47_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_47_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8 - bit Data bus) 2= sd1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_out[1]- (8-bit Data bus) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_47_L2_SEL 2 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi - , Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd - (UART transmitter serial output) 7= Not Used - PSU_IOU_SLCR_MIO_PIN_47_L3_SEL 0 - - Configures MIO Pin 47 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800BC, 0x000000FEU ,0x00000010U) - RegMask = (IOU_SLCR_MIO_PIN_47_L0_SEL_MASK | IOU_SLCR_MIO_PIN_47_L1_SEL_MASK | IOU_SLCR_MIO_PIN_47_L2_SEL_MASK | IOU_SLCR_MIO_PIN_47_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_47_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_47_L1_SEL_SHIFT - | 0x00000002U << IOU_SLCR_MIO_PIN_47_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_47_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_47_OFFSET ,0x000000FEU ,0x00000010U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_48 @ 0XFF1800C0

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[3]- (RX RGMII data) - PSU_IOU_SLCR_MIO_PIN_48_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_48_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8 - bit Data bus) 2= sd1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_out[2]- (8-bit Data bus) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_48_L2_SEL 2 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[22]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[22]- (GPIO bank 1) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1 - so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not U - ed - PSU_IOU_SLCR_MIO_PIN_48_L3_SEL 0 - - Configures MIO Pin 48 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800C0, 0x000000FEU ,0x00000010U) - RegMask = (IOU_SLCR_MIO_PIN_48_L0_SEL_MASK | IOU_SLCR_MIO_PIN_48_L1_SEL_MASK | IOU_SLCR_MIO_PIN_48_L2_SEL_MASK | IOU_SLCR_MIO_PIN_48_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_48_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_48_L1_SEL_SHIFT - | 0x00000002U << IOU_SLCR_MIO_PIN_48_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_48_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_48_OFFSET ,0x000000FEU ,0x00000010U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_49 @ 0XFF1800C4

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_ctl- (RX RGMII control ) - PSU_IOU_SLCR_MIO_PIN_49_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_49_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= sd1, Input, sd1_data_in[3]- (8 - bit Data bus) = sd1, Output, sdio1_data_out[3]- (8-bit Data bus) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_49_L2_SEL 2 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[23]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[23]- (GPIO bank 1) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, sp - 1_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) - 7= Not Used - PSU_IOU_SLCR_MIO_PIN_49_L3_SEL 0 - - Configures MIO Pin 49 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800C4, 0x000000FEU ,0x00000010U) - RegMask = (IOU_SLCR_MIO_PIN_49_L0_SEL_MASK | IOU_SLCR_MIO_PIN_49_L1_SEL_MASK | IOU_SLCR_MIO_PIN_49_L2_SEL_MASK | IOU_SLCR_MIO_PIN_49_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_49_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_49_L1_SEL_SHIFT - | 0x00000002U << IOU_SLCR_MIO_PIN_49_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_49_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_49_OFFSET ,0x000000FEU ,0x00000010U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_50 @ 0XFF1800C8

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- (TSU clock) - PSU_IOU_SLCR_MIO_PIN_50_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_50_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= sd1, Input, sd1_c - d_in- (Command Indicator) = sd1, Output, sdio1_cmd_out- (Command Indicator) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_50_L2_SEL 2 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[24]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[24]- (GPIO bank 1) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= ttc2, Input, ttc2 - clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used - PSU_IOU_SLCR_MIO_PIN_50_L3_SEL 0 - - Configures MIO Pin 50 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800C8, 0x000000FEU ,0x00000010U) - RegMask = (IOU_SLCR_MIO_PIN_50_L0_SEL_MASK | IOU_SLCR_MIO_PIN_50_L1_SEL_MASK | IOU_SLCR_MIO_PIN_50_L2_SEL_MASK | IOU_SLCR_MIO_PIN_50_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_50_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_50_L1_SEL_SHIFT - | 0x00000002U << IOU_SLCR_MIO_PIN_50_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_50_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_50_OFFSET ,0x000000FEU ,0x00000010U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_51 @ 0XFF1800CC

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- (TSU clock) - PSU_IOU_SLCR_MIO_PIN_51_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_51_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Output, sdio1_clk_out- (SDSDIO clock) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_51_L2_SEL 2 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[25]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[25]- (GPIO bank 1) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= mdio1, Input, gem1_mdio_in- (MDIO Data) 4= mdio1, Outp - t, gem1_mdio_out- (MDIO Data) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter - serial output) 7= Not Used - PSU_IOU_SLCR_MIO_PIN_51_L3_SEL 0 - - Configures MIO Pin 51 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800CC, 0x000000FEU ,0x00000010U) - RegMask = (IOU_SLCR_MIO_PIN_51_L0_SEL_MASK | IOU_SLCR_MIO_PIN_51_L1_SEL_MASK | IOU_SLCR_MIO_PIN_51_L2_SEL_MASK | IOU_SLCR_MIO_PIN_51_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_51_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_51_L1_SEL_SHIFT - | 0x00000002U << IOU_SLCR_MIO_PIN_51_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_51_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_51_OFFSET ,0x000000FEU ,0x00000010U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_52 @ 0XFF1800D0

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_clk- (TX RGMII clock) - PSU_IOU_SLCR_MIO_PIN_52_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_clk_in- (ULPI Clock) - PSU_IOU_SLCR_MIO_PIN_52_L1_SEL 1 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used - PSU_IOU_SLCR_MIO_PIN_52_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[0]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[0]- (GPIO bank 2) 1= can - , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa - ) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Cloc - ) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_ - lk- (Trace Port Clock) - PSU_IOU_SLCR_MIO_PIN_52_L3_SEL 0 - - Configures MIO Pin 52 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800D0, 0x000000FEU ,0x00000004U) - RegMask = (IOU_SLCR_MIO_PIN_52_L0_SEL_MASK | IOU_SLCR_MIO_PIN_52_L1_SEL_MASK | IOU_SLCR_MIO_PIN_52_L2_SEL_MASK | IOU_SLCR_MIO_PIN_52_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_52_L0_SEL_SHIFT - | 0x00000001U << IOU_SLCR_MIO_PIN_52_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_52_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_52_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_52_OFFSET ,0x000000FEU ,0x00000004U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_53 @ 0XFF1800D4

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[0]- (TX RGMII data) - PSU_IOU_SLCR_MIO_PIN_53_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_dir- (Data bus direction control) - PSU_IOU_SLCR_MIO_PIN_53_L1_SEL 1 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used - PSU_IOU_SLCR_MIO_PIN_53_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[1]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[1]- (GPIO bank 2) 1= can - , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal - 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_o - t- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control - Signal) - PSU_IOU_SLCR_MIO_PIN_53_L3_SEL 0 - - Configures MIO Pin 53 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800D4, 0x000000FEU ,0x00000004U) - RegMask = (IOU_SLCR_MIO_PIN_53_L0_SEL_MASK | IOU_SLCR_MIO_PIN_53_L1_SEL_MASK | IOU_SLCR_MIO_PIN_53_L2_SEL_MASK | IOU_SLCR_MIO_PIN_53_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_53_L0_SEL_SHIFT - | 0x00000001U << IOU_SLCR_MIO_PIN_53_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_53_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_53_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_53_OFFSET ,0x000000FEU ,0x00000004U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_54 @ 0XFF1800D8

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[1]- (TX RGMII data) - PSU_IOU_SLCR_MIO_PIN_54_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[2]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_ - ata[2]- (ULPI data bus) - PSU_IOU_SLCR_MIO_PIN_54_L1_SEL 1 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used - PSU_IOU_SLCR_MIO_PIN_54_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[2]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[2]- (GPIO bank 2) 1= can - , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal - 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, Input, ttc0_clk_in - (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[0]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_54_L3_SEL 0 - - Configures MIO Pin 54 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800D8, 0x000000FEU ,0x00000004U) - RegMask = (IOU_SLCR_MIO_PIN_54_L0_SEL_MASK | IOU_SLCR_MIO_PIN_54_L1_SEL_MASK | IOU_SLCR_MIO_PIN_54_L2_SEL_MASK | IOU_SLCR_MIO_PIN_54_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_54_L0_SEL_SHIFT - | 0x00000001U << IOU_SLCR_MIO_PIN_54_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_54_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_54_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_54_OFFSET ,0x000000FEU ,0x00000004U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_55 @ 0XFF1800DC

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[2]- (TX RGMII data) - PSU_IOU_SLCR_MIO_PIN_55_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_nxt- (Data flow control signal from the PHY) - PSU_IOU_SLCR_MIO_PIN_55_L1_SEL 1 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used - PSU_IOU_SLCR_MIO_PIN_55_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[3]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[3]- (GPIO bank 2) 1= can - , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa - ) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0 - - (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial - output) 7= trace, Output, tracedq[1]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_55_L3_SEL 0 - - Configures MIO Pin 55 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800DC, 0x000000FEU ,0x00000004U) - RegMask = (IOU_SLCR_MIO_PIN_55_L0_SEL_MASK | IOU_SLCR_MIO_PIN_55_L1_SEL_MASK | IOU_SLCR_MIO_PIN_55_L2_SEL_MASK | IOU_SLCR_MIO_PIN_55_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_55_L0_SEL_SHIFT - | 0x00000001U << IOU_SLCR_MIO_PIN_55_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_55_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_55_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_55_OFFSET ,0x000000FEU ,0x00000004U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_56 @ 0XFF1800E0

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[3]- (TX RGMII data) - PSU_IOU_SLCR_MIO_PIN_56_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[0]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_ - ata[0]- (ULPI data bus) - PSU_IOU_SLCR_MIO_PIN_56_L1_SEL 1 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used - PSU_IOU_SLCR_MIO_PIN_56_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[4]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[4]- (GPIO bank 2) 1= can - , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa - ) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_s - - (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, - utput, tracedq[2]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_56_L3_SEL 0 - - Configures MIO Pin 56 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800E0, 0x000000FEU ,0x00000004U) - RegMask = (IOU_SLCR_MIO_PIN_56_L0_SEL_MASK | IOU_SLCR_MIO_PIN_56_L1_SEL_MASK | IOU_SLCR_MIO_PIN_56_L2_SEL_MASK | IOU_SLCR_MIO_PIN_56_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_56_L0_SEL_SHIFT - | 0x00000001U << IOU_SLCR_MIO_PIN_56_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_56_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_56_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_56_OFFSET ,0x000000FEU ,0x00000004U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_57 @ 0XFF1800E4

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_ctl- (TX RGMII control) - PSU_IOU_SLCR_MIO_PIN_57_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[1]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_ - ata[1]- (ULPI data bus) - PSU_IOU_SLCR_MIO_PIN_57_L1_SEL 1 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used - PSU_IOU_SLCR_MIO_PIN_57_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[5]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[5]- (GPIO bank 2) 1= can - , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal - 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi0 - si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7 - trace, Output, tracedq[3]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_57_L3_SEL 0 - - Configures MIO Pin 57 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800E4, 0x000000FEU ,0x00000004U) - RegMask = (IOU_SLCR_MIO_PIN_57_L0_SEL_MASK | IOU_SLCR_MIO_PIN_57_L1_SEL_MASK | IOU_SLCR_MIO_PIN_57_L2_SEL_MASK | IOU_SLCR_MIO_PIN_57_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_57_L0_SEL_SHIFT - | 0x00000001U << IOU_SLCR_MIO_PIN_57_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_57_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_57_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_57_OFFSET ,0x000000FEU ,0x00000004U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_58 @ 0XFF1800E8

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_clk- (RX RGMII clock) - PSU_IOU_SLCR_MIO_PIN_58_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Output, usb0_ulpi_stp- (Asserted to end or interrupt transfers) - PSU_IOU_SLCR_MIO_PIN_58_L1_SEL 1 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used - PSU_IOU_SLCR_MIO_PIN_58_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[6]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[6]- (GPIO bank 2) 1= can - , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal - 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1_sclk_out- (SPI Clock - 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- - Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_58_L3_SEL 0 - - Configures MIO Pin 58 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800E8, 0x000000FEU ,0x00000004U) - RegMask = (IOU_SLCR_MIO_PIN_58_L0_SEL_MASK | IOU_SLCR_MIO_PIN_58_L1_SEL_MASK | IOU_SLCR_MIO_PIN_58_L2_SEL_MASK | IOU_SLCR_MIO_PIN_58_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_58_L0_SEL_SHIFT - | 0x00000001U << IOU_SLCR_MIO_PIN_58_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_58_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_58_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_58_OFFSET ,0x000000FEU ,0x00000004U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_59 @ 0XFF1800EC

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[0]- (RX RGMII data) - PSU_IOU_SLCR_MIO_PIN_59_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[3]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_ - ata[3]- (ULPI data bus) - PSU_IOU_SLCR_MIO_PIN_59_L1_SEL 1 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used - PSU_IOU_SLCR_MIO_PIN_59_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[7]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[7]- (GPIO bank 2) 1= can - , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa - ) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_ - ut- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port - atabus) - PSU_IOU_SLCR_MIO_PIN_59_L3_SEL 0 - - Configures MIO Pin 59 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800EC, 0x000000FEU ,0x00000004U) - RegMask = (IOU_SLCR_MIO_PIN_59_L0_SEL_MASK | IOU_SLCR_MIO_PIN_59_L1_SEL_MASK | IOU_SLCR_MIO_PIN_59_L2_SEL_MASK | IOU_SLCR_MIO_PIN_59_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_59_L0_SEL_SHIFT - | 0x00000001U << IOU_SLCR_MIO_PIN_59_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_59_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_59_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_59_OFFSET ,0x000000FEU ,0x00000004U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_60 @ 0XFF1800F0

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[1]- (RX RGMII data) - PSU_IOU_SLCR_MIO_PIN_60_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[4]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_ - ata[4]- (ULPI data bus) - PSU_IOU_SLCR_MIO_PIN_60_L1_SEL 1 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used - PSU_IOU_SLCR_MIO_PIN_60_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[8]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[8]- (GPIO bank 2) 1= can - , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa - ) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc1, Input, ttc1_clk_i - - (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_60_L3_SEL 0 - - Configures MIO Pin 60 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800F0, 0x000000FEU ,0x00000004U) - RegMask = (IOU_SLCR_MIO_PIN_60_L0_SEL_MASK | IOU_SLCR_MIO_PIN_60_L1_SEL_MASK | IOU_SLCR_MIO_PIN_60_L2_SEL_MASK | IOU_SLCR_MIO_PIN_60_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_60_L0_SEL_SHIFT - | 0x00000001U << IOU_SLCR_MIO_PIN_60_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_60_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_60_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_60_OFFSET ,0x000000FEU ,0x00000004U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_61 @ 0XFF1800F4

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[2]- (RX RGMII data) - PSU_IOU_SLCR_MIO_PIN_61_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[5]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_ - ata[5]- (ULPI data bus) - PSU_IOU_SLCR_MIO_PIN_61_L1_SEL 1 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used - PSU_IOU_SLCR_MIO_PIN_61_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[9]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[9]- (GPIO bank 2) 1= can - , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal - 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, Output, spi1_n_ss_out[0] - (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial inpu - ) 7= trace, Output, tracedq[7]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_61_L3_SEL 0 - - Configures MIO Pin 61 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800F4, 0x000000FEU ,0x00000004U) - RegMask = (IOU_SLCR_MIO_PIN_61_L0_SEL_MASK | IOU_SLCR_MIO_PIN_61_L1_SEL_MASK | IOU_SLCR_MIO_PIN_61_L2_SEL_MASK | IOU_SLCR_MIO_PIN_61_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_61_L0_SEL_SHIFT - | 0x00000001U << IOU_SLCR_MIO_PIN_61_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_61_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_61_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_61_OFFSET ,0x000000FEU ,0x00000004U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_62 @ 0XFF1800F8

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[3]- (RX RGMII data) - PSU_IOU_SLCR_MIO_PIN_62_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[6]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_ - ata[6]- (ULPI data bus) - PSU_IOU_SLCR_MIO_PIN_62_L1_SEL 1 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used - PSU_IOU_SLCR_MIO_PIN_62_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[10]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[10]- (GPIO bank 2) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_ - o- (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outp - t, tracedq[8]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_62_L3_SEL 0 - - Configures MIO Pin 62 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800F8, 0x000000FEU ,0x00000004U) - RegMask = (IOU_SLCR_MIO_PIN_62_L0_SEL_MASK | IOU_SLCR_MIO_PIN_62_L1_SEL_MASK | IOU_SLCR_MIO_PIN_62_L2_SEL_MASK | IOU_SLCR_MIO_PIN_62_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_62_L0_SEL_SHIFT - | 0x00000001U << IOU_SLCR_MIO_PIN_62_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_62_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_62_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_62_OFFSET ,0x000000FEU ,0x00000004U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_63 @ 0XFF1800FC

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_ctl- (RX RGMII control ) - PSU_IOU_SLCR_MIO_PIN_63_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[7]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_ - ata[7]- (ULPI data bus) - PSU_IOU_SLCR_MIO_PIN_63_L1_SEL 1 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used - PSU_IOU_SLCR_MIO_PIN_63_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[11]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[11]- (GPIO bank 2) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s - i1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o - tput) 7= trace, Output, tracedq[9]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_63_L3_SEL 0 - - Configures MIO Pin 63 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800FC, 0x000000FEU ,0x00000004U) - RegMask = (IOU_SLCR_MIO_PIN_63_L0_SEL_MASK | IOU_SLCR_MIO_PIN_63_L1_SEL_MASK | IOU_SLCR_MIO_PIN_63_L2_SEL_MASK | IOU_SLCR_MIO_PIN_63_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_63_L0_SEL_SHIFT - | 0x00000001U << IOU_SLCR_MIO_PIN_63_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_63_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_63_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_63_OFFSET ,0x000000FEU ,0x00000004U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_64 @ 0XFF180100

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_clk- (TX RGMII clock) - PSU_IOU_SLCR_MIO_PIN_64_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_clk_in- (ULPI Clock) - PSU_IOU_SLCR_MIO_PIN_64_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= Not Used 3= Not Used - PSU_IOU_SLCR_MIO_PIN_64_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[12]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[12]- (GPIO bank 2) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, s - i0_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7 - trace, Output, tracedq[10]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_64_L3_SEL 0 - - Configures MIO Pin 64 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180100, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_64_L0_SEL_MASK | IOU_SLCR_MIO_PIN_64_L1_SEL_MASK | IOU_SLCR_MIO_PIN_64_L2_SEL_MASK | IOU_SLCR_MIO_PIN_64_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_64_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_64_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_64_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_64_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_64_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_65 @ 0XFF180104

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[0]- (TX RGMII data) - PSU_IOU_SLCR_MIO_PIN_65_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_dir- (Data bus direction control) - PSU_IOU_SLCR_MIO_PIN_65_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= Not Used 3= Not Used - PSU_IOU_SLCR_MIO_PIN_65_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[13]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[13]- (GPIO bank 2) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= - ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trac - dq[11]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_65_L3_SEL 0 - - Configures MIO Pin 65 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180104, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_65_L0_SEL_MASK | IOU_SLCR_MIO_PIN_65_L1_SEL_MASK | IOU_SLCR_MIO_PIN_65_L2_SEL_MASK | IOU_SLCR_MIO_PIN_65_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_65_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_65_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_65_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_65_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_65_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_66 @ 0XFF180108

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[1]- (TX RGMII data) - PSU_IOU_SLCR_MIO_PIN_66_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[2]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_ - ata[2]- (ULPI data bus) - PSU_IOU_SLCR_MIO_PIN_66_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Comman - Indicator) 2= Not Used 3= Not Used - PSU_IOU_SLCR_MIO_PIN_66_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[14]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[14]- (GPIO bank 2) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= tt - 2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace - Port Databus) - PSU_IOU_SLCR_MIO_PIN_66_L3_SEL 0 - - Configures MIO Pin 66 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180108, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_66_L0_SEL_MASK | IOU_SLCR_MIO_PIN_66_L1_SEL_MASK | IOU_SLCR_MIO_PIN_66_L2_SEL_MASK | IOU_SLCR_MIO_PIN_66_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_66_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_66_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_66_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_66_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_66_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_67 @ 0XFF18010C

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[2]- (TX RGMII data) - PSU_IOU_SLCR_MIO_PIN_67_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_nxt- (Data flow control signal from the PHY) - PSU_IOU_SLCR_MIO_PIN_67_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8 - bit Data bus) 2= Not Used 3= Not Used - PSU_IOU_SLCR_MIO_PIN_67_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[15]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[15]- (GPIO bank 2) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi - , Output, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd - (UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_67_L3_SEL 0 - - Configures MIO Pin 67 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF18010C, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_67_L0_SEL_MASK | IOU_SLCR_MIO_PIN_67_L1_SEL_MASK | IOU_SLCR_MIO_PIN_67_L2_SEL_MASK | IOU_SLCR_MIO_PIN_67_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_67_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_67_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_67_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_67_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_67_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_68 @ 0XFF180110

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[3]- (TX RGMII data) - PSU_IOU_SLCR_MIO_PIN_68_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[0]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_ - ata[0]- (ULPI data bus) - PSU_IOU_SLCR_MIO_PIN_68_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8 - bit Data bus) 2= Not Used 3= Not Used - PSU_IOU_SLCR_MIO_PIN_68_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[16]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[16]- (GPIO bank 2) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0 - so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace - Output, tracedq[14]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_68_L3_SEL 0 - - Configures MIO Pin 68 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180110, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_68_L0_SEL_MASK | IOU_SLCR_MIO_PIN_68_L1_SEL_MASK | IOU_SLCR_MIO_PIN_68_L2_SEL_MASK | IOU_SLCR_MIO_PIN_68_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_68_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_68_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_68_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_68_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_68_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_69 @ 0XFF180114

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_ctl- (TX RGMII control) - PSU_IOU_SLCR_MIO_PIN_69_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[1]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_ - ata[1]- (ULPI data bus) - PSU_IOU_SLCR_MIO_PIN_69_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8 - bit Data bus) 2= sd1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_69_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[17]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[17]- (GPIO bank 2) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, sp - 0_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) - 7= trace, Output, tracedq[15]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_69_L3_SEL 0 - - Configures MIO Pin 69 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180114, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_69_L0_SEL_MASK | IOU_SLCR_MIO_PIN_69_L1_SEL_MASK | IOU_SLCR_MIO_PIN_69_L2_SEL_MASK | IOU_SLCR_MIO_PIN_69_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_69_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_69_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_69_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_69_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_69_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_70 @ 0XFF180118

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_clk- (RX RGMII clock) - PSU_IOU_SLCR_MIO_PIN_70_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Output, usb1_ulpi_stp- (Asserted to end or interrupt transfers) - PSU_IOU_SLCR_MIO_PIN_70_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8 - bit Data bus) 2= sd1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_70_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[18]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[18]- (GPIO bank 2) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, sp - 1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not - sed - PSU_IOU_SLCR_MIO_PIN_70_L3_SEL 0 - - Configures MIO Pin 70 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180118, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_70_L0_SEL_MASK | IOU_SLCR_MIO_PIN_70_L1_SEL_MASK | IOU_SLCR_MIO_PIN_70_L2_SEL_MASK | IOU_SLCR_MIO_PIN_70_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_70_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_70_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_70_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_70_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_70_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_71 @ 0XFF18011C

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[0]- (RX RGMII data) - PSU_IOU_SLCR_MIO_PIN_71_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[3]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_ - ata[3]- (ULPI data bus) - PSU_IOU_SLCR_MIO_PIN_71_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8 - bit Data bus) 2= sd1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_out[0]- (8-bit Data bus) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_71_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[19]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[19]- (GPIO bank 2) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5 - ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used - PSU_IOU_SLCR_MIO_PIN_71_L3_SEL 0 - - Configures MIO Pin 71 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF18011C, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_71_L0_SEL_MASK | IOU_SLCR_MIO_PIN_71_L1_SEL_MASK | IOU_SLCR_MIO_PIN_71_L2_SEL_MASK | IOU_SLCR_MIO_PIN_71_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_71_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_71_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_71_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_71_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_71_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_72 @ 0XFF180120

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[1]- (RX RGMII data) - PSU_IOU_SLCR_MIO_PIN_72_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[4]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_ - ata[4]- (ULPI data bus) - PSU_IOU_SLCR_MIO_PIN_72_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8 - bit Data bus) 2= sd1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_out[1]- (8-bit Data bus) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_72_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[20]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[20]- (GPIO bank 2) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= N - t Used 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Used - PSU_IOU_SLCR_MIO_PIN_72_L3_SEL 0 - - Configures MIO Pin 72 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180120, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_72_L0_SEL_MASK | IOU_SLCR_MIO_PIN_72_L1_SEL_MASK | IOU_SLCR_MIO_PIN_72_L2_SEL_MASK | IOU_SLCR_MIO_PIN_72_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_72_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_72_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_72_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_72_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_72_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_73 @ 0XFF180124

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[2]- (RX RGMII data) - PSU_IOU_SLCR_MIO_PIN_73_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_ - ata[5]- (ULPI data bus) - PSU_IOU_SLCR_MIO_PIN_73_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8 - bit Data bus) 2= sd1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_out[2]- (8-bit Data bus) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_73_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[21]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[21]- (GPIO bank 2) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1 - Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= Not Used 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used - PSU_IOU_SLCR_MIO_PIN_73_L3_SEL 0 - - Configures MIO Pin 73 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180124, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_73_L0_SEL_MASK | IOU_SLCR_MIO_PIN_73_L1_SEL_MASK | IOU_SLCR_MIO_PIN_73_L2_SEL_MASK | IOU_SLCR_MIO_PIN_73_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_73_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_73_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_73_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_73_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_73_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_74 @ 0XFF180128

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[3]- (RX RGMII data) - PSU_IOU_SLCR_MIO_PIN_74_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[6]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_ - ata[6]- (ULPI data bus) - PSU_IOU_SLCR_MIO_PIN_74_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8 - bit Data bus) 2= sd1, Input, sd1_data_in[3]- (8-bit Data bus) = sd1, Output, sdio1_data_out[3]- (8-bit Data bus) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_74_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[22]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[22]- (GPIO bank 2) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_ - o- (MISO signal) 5= Not Used 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used - PSU_IOU_SLCR_MIO_PIN_74_L3_SEL 0 - - Configures MIO Pin 74 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180128, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_74_L0_SEL_MASK | IOU_SLCR_MIO_PIN_74_L1_SEL_MASK | IOU_SLCR_MIO_PIN_74_L2_SEL_MASK | IOU_SLCR_MIO_PIN_74_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_74_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_74_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_74_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_74_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_74_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_75 @ 0XFF18012C

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_ctl- (RX RGMII control ) - PSU_IOU_SLCR_MIO_PIN_75_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[7]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_ - ata[7]- (ULPI data bus) - PSU_IOU_SLCR_MIO_PIN_75_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= sd1, Input, sd1_cmd_in- (Comma - d Indicator) = sd1, Output, sdio1_cmd_out- (Command Indicator) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_75_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[23]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[23]- (GPIO bank 2) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s - i1_si- (MOSI signal) 5= Not Used 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used - PSU_IOU_SLCR_MIO_PIN_75_L3_SEL 0 - - Configures MIO Pin 75 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF18012C, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_75_L0_SEL_MASK | IOU_SLCR_MIO_PIN_75_L1_SEL_MASK | IOU_SLCR_MIO_PIN_75_L2_SEL_MASK | IOU_SLCR_MIO_PIN_75_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_75_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_75_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_75_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_75_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_75_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_76 @ 0XFF180130

- - Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_76_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_76_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= sd1, Output, sdio - _clk_out- (SDSDIO clock) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_76_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[24]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[24]- (GPIO bank 2) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= mdio0, Output, gem0_mdc- (MDIO Clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= mdio2, Output, gem2_mdc- (MDIO Clock - 6= mdio3, Output, gem3_mdc- (MDIO Clock) 7= Not Used - PSU_IOU_SLCR_MIO_PIN_76_L3_SEL 6 - - Configures MIO Pin 76 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180130, 0x000000FEU ,0x000000C0U) - RegMask = (IOU_SLCR_MIO_PIN_76_L0_SEL_MASK | IOU_SLCR_MIO_PIN_76_L1_SEL_MASK | IOU_SLCR_MIO_PIN_76_L2_SEL_MASK | IOU_SLCR_MIO_PIN_76_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_76_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_76_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_76_L2_SEL_SHIFT - | 0x00000006U << IOU_SLCR_MIO_PIN_76_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_76_OFFSET ,0x000000FEU ,0x000000C0U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_77 @ 0XFF180134

- - Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_77_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_77_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Input, sdio1_cd_n- (SD card detect from connector) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_77_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[25]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[25]- (GPIO bank 2) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= mdio0, Input, gem0_mdio_in- (MDIO Data) 3= mdio0, Output, gem0_mdio_out- (MDIO Data) 4= mdio1, Input, gem1_mdio_in- (MD - O Data) 4= mdio1, Output, gem1_mdio_out- (MDIO Data) 5= mdio2, Input, gem2_mdio_in- (MDIO Data) 5= mdio2, Output, gem2_mdio_o - t- (MDIO Data) 6= mdio3, Input, gem3_mdio_in- (MDIO Data) 6= mdio3, Output, gem3_mdio_out- (MDIO Data) 7= Not Used - PSU_IOU_SLCR_MIO_PIN_77_L3_SEL 6 - - Configures MIO Pin 77 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180134, 0x000000FEU ,0x000000C0U) - RegMask = (IOU_SLCR_MIO_PIN_77_L0_SEL_MASK | IOU_SLCR_MIO_PIN_77_L1_SEL_MASK | IOU_SLCR_MIO_PIN_77_L2_SEL_MASK | IOU_SLCR_MIO_PIN_77_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_77_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_77_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_77_L2_SEL_SHIFT - | 0x00000006U << IOU_SLCR_MIO_PIN_77_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_77_OFFSET ,0x000000FEU ,0x000000C0U); - /*############################################################################################################################ */ - - /*Register : MIO_MST_TRI0 @ 0XFF180204

- - Master Tri-state Enable for pin 0, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI 0 - - Master Tri-state Enable for pin 1, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI 0 - - Master Tri-state Enable for pin 2, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI 0 - - Master Tri-state Enable for pin 3, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI 0 - - Master Tri-state Enable for pin 4, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI 0 - - Master Tri-state Enable for pin 5, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI 0 - - Master Tri-state Enable for pin 6, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI 0 - - Master Tri-state Enable for pin 7, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI 0 - - Master Tri-state Enable for pin 8, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI 0 - - Master Tri-state Enable for pin 9, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI 0 - - Master Tri-state Enable for pin 10, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI 0 - - Master Tri-state Enable for pin 11, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI 0 - - Master Tri-state Enable for pin 12, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI 0 - - Master Tri-state Enable for pin 13, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI 0 - - Master Tri-state Enable for pin 14, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI 0 - - Master Tri-state Enable for pin 15, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI 0 - - Master Tri-state Enable for pin 16, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI 0 - - Master Tri-state Enable for pin 17, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI 0 - - Master Tri-state Enable for pin 18, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI 1 - - Master Tri-state Enable for pin 19, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI 0 - - Master Tri-state Enable for pin 20, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI 0 - - Master Tri-state Enable for pin 21, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI 1 - - Master Tri-state Enable for pin 22, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI 0 - - Master Tri-state Enable for pin 23, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI 0 - - Master Tri-state Enable for pin 24, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI 0 - - Master Tri-state Enable for pin 25, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI 1 - - Master Tri-state Enable for pin 26, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI 0 - - Master Tri-state Enable for pin 27, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI 0 - - Master Tri-state Enable for pin 28, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI 1 - - Master Tri-state Enable for pin 29, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI 0 - - Master Tri-state Enable for pin 30, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI 1 - - Master Tri-state Enable for pin 31, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI 0 - - MIO pin Tri-state Enables, 31:0 - (OFFSET, MASK, VALUE) (0XFF180204, 0xFFFFFFFFU ,0x52240000U) - RegMask = (IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_SHIFT - | 0x00000001U << IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_SHIFT - | 0x00000001U << IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_SHIFT - | 0x00000001U << IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_SHIFT - | 0x00000001U << IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_SHIFT - | 0x00000001U << IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_MST_TRI0_OFFSET ,0xFFFFFFFFU ,0x52240000U); - /*############################################################################################################################ */ - - /*Register : MIO_MST_TRI1 @ 0XFF180208

- - Master Tri-state Enable for pin 32, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI 0 - - Master Tri-state Enable for pin 33, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI 0 - - Master Tri-state Enable for pin 34, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI 0 - - Master Tri-state Enable for pin 35, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI 0 - - Master Tri-state Enable for pin 36, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI 0 - - Master Tri-state Enable for pin 37, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI 0 - - Master Tri-state Enable for pin 38, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI 0 - - Master Tri-state Enable for pin 39, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI 0 - - Master Tri-state Enable for pin 40, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI 0 - - Master Tri-state Enable for pin 41, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI 0 - - Master Tri-state Enable for pin 42, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI 0 - - Master Tri-state Enable for pin 43, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI 0 - - Master Tri-state Enable for pin 44, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI 1 - - Master Tri-state Enable for pin 45, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI 1 - - Master Tri-state Enable for pin 46, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI 0 - - Master Tri-state Enable for pin 47, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI 0 - - Master Tri-state Enable for pin 48, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI 0 - - Master Tri-state Enable for pin 49, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI 0 - - Master Tri-state Enable for pin 50, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI 0 - - Master Tri-state Enable for pin 51, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI 0 - - Master Tri-state Enable for pin 52, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI 1 - - Master Tri-state Enable for pin 53, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI 1 - - Master Tri-state Enable for pin 54, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI 0 - - Master Tri-state Enable for pin 55, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI 1 - - Master Tri-state Enable for pin 56, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI 0 - - Master Tri-state Enable for pin 57, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI 0 - - Master Tri-state Enable for pin 58, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI 0 - - Master Tri-state Enable for pin 59, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI 0 - - Master Tri-state Enable for pin 60, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI 0 - - Master Tri-state Enable for pin 61, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI 0 - - Master Tri-state Enable for pin 62, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI 0 - - Master Tri-state Enable for pin 63, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI 0 - - MIO pin Tri-state Enables, 63:32 - (OFFSET, MASK, VALUE) (0XFF180208, 0xFFFFFFFFU ,0x00B03000U) - RegMask = (IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_SHIFT - | 0x00000001U << IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_SHIFT - | 0x00000001U << IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_SHIFT - | 0x00000001U << IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_SHIFT - | 0x00000001U << IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_SHIFT - | 0x00000001U << IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_MST_TRI1_OFFSET ,0xFFFFFFFFU ,0x00B03000U); - /*############################################################################################################################ */ - - /*Register : MIO_MST_TRI2 @ 0XFF18020C

- - Master Tri-state Enable for pin 64, active high - PSU_IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI 0 - - Master Tri-state Enable for pin 65, active high - PSU_IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI 0 - - Master Tri-state Enable for pin 66, active high - PSU_IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI 0 - - Master Tri-state Enable for pin 67, active high - PSU_IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI 0 - - Master Tri-state Enable for pin 68, active high - PSU_IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI 0 - - Master Tri-state Enable for pin 69, active high - PSU_IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI 0 - - Master Tri-state Enable for pin 70, active high - PSU_IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI 1 - - Master Tri-state Enable for pin 71, active high - PSU_IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI 1 - - Master Tri-state Enable for pin 72, active high - PSU_IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI 1 - - Master Tri-state Enable for pin 73, active high - PSU_IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI 1 - - Master Tri-state Enable for pin 74, active high - PSU_IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI 1 - - Master Tri-state Enable for pin 75, active high - PSU_IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI 1 - - Master Tri-state Enable for pin 76, active high - PSU_IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI 0 - - Master Tri-state Enable for pin 77, active high - PSU_IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI 0 - - MIO pin Tri-state Enables, 77:64 - (OFFSET, MASK, VALUE) (0XFF18020C, 0x00003FFFU ,0x00000FC0U) - RegMask = (IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_SHIFT - | 0x00000001U << IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_SHIFT - | 0x00000001U << IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_SHIFT - | 0x00000001U << IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_SHIFT - | 0x00000001U << IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_SHIFT - | 0x00000001U << IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_SHIFT - | 0x00000001U << IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_MST_TRI2_OFFSET ,0x00003FFFU ,0x00000FC0U); - /*############################################################################################################################ */ - - /*Register : bank0_ctrl0 @ 0XFF180138

- - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25 1 - - Drive0 control to MIO Bank 0 - control MIO[25:0] - (OFFSET, MASK, VALUE) (0XFF180138, 0x03FFFFFFU ,0x03FFFFFFU) - RegMask = (IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_BANK0_CTRL0_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU); - /*############################################################################################################################ */ - - /*Register : bank0_ctrl1 @ 0XFF18013C

- - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25 1 - - Drive1 control to MIO Bank 0 - control MIO[25:0] - (OFFSET, MASK, VALUE) (0XFF18013C, 0x03FFFFFFU ,0x03FFFFFFU) - RegMask = (IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_BANK0_CTRL1_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU); - /*############################################################################################################################ */ - - /*Register : bank0_ctrl3 @ 0XFF180140

- - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25 0 - - Selects either Schmitt or CMOS input for MIO Bank 0 - control MIO[25:0] - (OFFSET, MASK, VALUE) (0XFF180140, 0x03FFFFFFU ,0x00000000U) - RegMask = (IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_BANK0_CTRL3_OFFSET ,0x03FFFFFFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : bank0_ctrl4 @ 0XFF180144

- - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25 1 - - When mio_bank0_pull_enable is set, this selects pull up or pull down for MIO Bank 0 - control MIO[25:0] - (OFFSET, MASK, VALUE) (0XFF180144, 0x03FFFFFFU ,0x03FFFFFFU) - RegMask = (IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_BANK0_CTRL4_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU); - /*############################################################################################################################ */ - - /*Register : bank0_ctrl5 @ 0XFF180148

- - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25 1 - - When set, this enables mio_bank0_pullupdown to selects pull up or pull down for MIO Bank 0 - control MIO[25:0] - (OFFSET, MASK, VALUE) (0XFF180148, 0x03FFFFFFU ,0x03FFFFFFU) - RegMask = (IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_BANK0_CTRL5_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU); - /*############################################################################################################################ */ - - /*Register : bank0_ctrl6 @ 0XFF18014C

- - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25 0 - - Slew rate control to MIO Bank 0 - control MIO[25:0] - (OFFSET, MASK, VALUE) (0XFF18014C, 0x03FFFFFFU ,0x00000000U) - RegMask = (IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_BANK0_CTRL6_OFFSET ,0x03FFFFFFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : bank1_ctrl0 @ 0XFF180154

- - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25 1 - - Drive0 control to MIO Bank 1 - control MIO[51:26] - (OFFSET, MASK, VALUE) (0XFF180154, 0x03FFFFFFU ,0x03FFFFFFU) - RegMask = (IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_BANK1_CTRL0_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU); - /*############################################################################################################################ */ - - /*Register : bank1_ctrl1 @ 0XFF180158

- - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25 1 - - Drive1 control to MIO Bank 1 - control MIO[51:26] - (OFFSET, MASK, VALUE) (0XFF180158, 0x03FFFFFFU ,0x03FFFFFFU) - RegMask = (IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_BANK1_CTRL1_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU); - /*############################################################################################################################ */ - - /*Register : bank1_ctrl3 @ 0XFF18015C

- - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25 0 - - Selects either Schmitt or CMOS input for MIO Bank 1 - control MIO[51:26] - (OFFSET, MASK, VALUE) (0XFF18015C, 0x03FFFFFFU ,0x00000000U) - RegMask = (IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_BANK1_CTRL3_OFFSET ,0x03FFFFFFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : bank1_ctrl4 @ 0XFF180160

- - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25 1 - - When mio_bank1_pull_enable is set, this selects pull up or pull down for MIO Bank 1 - control MIO[51:26] - (OFFSET, MASK, VALUE) (0XFF180160, 0x03FFFFFFU ,0x03FFFFFFU) - RegMask = (IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_BANK1_CTRL4_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU); - /*############################################################################################################################ */ - - /*Register : bank1_ctrl5 @ 0XFF180164

- - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25 1 - - When set, this enables mio_bank1_pullupdown to selects pull up or pull down for MIO Bank 1 - control MIO[51:26] - (OFFSET, MASK, VALUE) (0XFF180164, 0x03FFFFFFU ,0x03FFFFFFU) - RegMask = (IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_BANK1_CTRL5_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU); - /*############################################################################################################################ */ - - /*Register : bank1_ctrl6 @ 0XFF180168

- - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25 0 - - Slew rate control to MIO Bank 1 - control MIO[51:26] - (OFFSET, MASK, VALUE) (0XFF180168, 0x03FFFFFFU ,0x00000000U) - RegMask = (IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_BANK1_CTRL6_OFFSET ,0x03FFFFFFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : bank2_ctrl0 @ 0XFF180170

- - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25 1 - - Drive0 control to MIO Bank 2 - control MIO[77:52] - (OFFSET, MASK, VALUE) (0XFF180170, 0x03FFFFFFU ,0x03FFFFFFU) - RegMask = (IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_BANK2_CTRL0_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU); - /*############################################################################################################################ */ - - /*Register : bank2_ctrl1 @ 0XFF180174

- - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25 1 - - Drive1 control to MIO Bank 2 - control MIO[77:52] - (OFFSET, MASK, VALUE) (0XFF180174, 0x03FFFFFFU ,0x03FFFFFFU) - RegMask = (IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_BANK2_CTRL1_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU); - /*############################################################################################################################ */ - - /*Register : bank2_ctrl3 @ 0XFF180178

- - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25 0 - - Selects either Schmitt or CMOS input for MIO Bank 2 - control MIO[77:52] - (OFFSET, MASK, VALUE) (0XFF180178, 0x03FFFFFFU ,0x00000000U) - RegMask = (IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_BANK2_CTRL3_OFFSET ,0x03FFFFFFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : bank2_ctrl4 @ 0XFF18017C

- - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25 1 - - When mio_bank2_pull_enable is set, this selects pull up or pull down for MIO Bank 2 - control MIO[77:52] - (OFFSET, MASK, VALUE) (0XFF18017C, 0x03FFFFFFU ,0x03FFFFFFU) - RegMask = (IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_BANK2_CTRL4_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU); - /*############################################################################################################################ */ - - /*Register : bank2_ctrl5 @ 0XFF180180

- - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25 1 - - When set, this enables mio_bank2_pullupdown to selects pull up or pull down for MIO Bank 2 - control MIO[77:52] - (OFFSET, MASK, VALUE) (0XFF180180, 0x03FFFFFFU ,0x03FFFFFFU) - RegMask = (IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_BANK2_CTRL5_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU); - /*############################################################################################################################ */ - - /*Register : bank2_ctrl6 @ 0XFF180184

- - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25 0 - - Slew rate control to MIO Bank 2 - control MIO[77:52] - (OFFSET, MASK, VALUE) (0XFF180184, 0x03FFFFFFU ,0x00000000U) - RegMask = (IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_BANK2_CTRL6_OFFSET ,0x03FFFFFFU ,0x00000000U); - /*############################################################################################################################ */ - - // : LOOPBACK - /*Register : MIO_LOOPBACK @ 0XFF180200

- - I2C Loopback Control. 0 = Connect I2C inputs according to MIO mapping. 1 = Loop I2C 0 outputs to I2C 1 inputs, and I2C 1 outp - ts to I2C 0 inputs. - PSU_IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1 0 - - CAN Loopback Control. 0 = Connect CAN inputs according to MIO mapping. 1 = Loop CAN 0 Tx to CAN 1 Rx, and CAN 1 Tx to CAN 0 R - . - PSU_IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1 0 - - UART Loopback Control. 0 = Connect UART inputs according to MIO mapping. 1 = Loop UART 0 outputs to UART 1 inputs, and UART 1 - outputs to UART 0 inputs. RXD/TXD cross-connected. RTS/CTS cross-connected. DSR, DTR, DCD and RI not used. - PSU_IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1 0 - - SPI Loopback Control. 0 = Connect SPI inputs according to MIO mapping. 1 = Loop SPI 0 outputs to SPI 1 inputs, and SPI 1 outp - ts to SPI 0 inputs. The other SPI core will appear on the LS Slave Select. - PSU_IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1 0 - - Loopback function within MIO - (OFFSET, MASK, VALUE) (0XFF180200, 0x0000000FU ,0x00000000U) - RegMask = (IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_MASK | IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_MASK | IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_MASK | IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_SHIFT - | 0x00000000U << IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_SHIFT - | 0x00000000U << IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_SHIFT - | 0x00000000U << IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_LOOPBACK_OFFSET ,0x0000000FU ,0x00000000U); - /*############################################################################################################################ */ - - - return 1; + return 1; } -unsigned long psu_peripherals_init_data() { - // : RESET BLOCKS - // : TIMESTAMP - /*Register : RST_LPD_IOU2 @ 0XFF5E0238

+unsigned long psu_mio_init_data(void) +{ + /* + * MIO PROGRAMMING + */ + /* + * Register : MIO_PIN_0 @ 0XFF180000 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out- + * (QSPI Clock) + * PSU_IOU_SLCR_MIO_PIN_0_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_0_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[0]- (Test Scan Port) = test_scan, Output, test_scan_out[0 + * ]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_0_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[0]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[0]- (GPIO bank 0) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG + * TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sc + * lk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Out + * put, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_c + * lk- (Trace Port Clock) + * PSU_IOU_SLCR_MIO_PIN_0_L3_SEL 0 + + * Configures MIO Pin 0 peripheral interface mapping. S + * (OFFSET, MASK, VALUE) (0XFF180000, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_0_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_1 @ 0XFF180004 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (Q + * SPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Databus) + * PSU_IOU_SLCR_MIO_PIN_1_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_1_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[1]- (Test Scan Port) = test_scan, Output, test_scan_out[1 + * ]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_1_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[1]- (GPIO bank 0) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG + * TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc3, Ou + * tput, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART + * receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control + * Signal) + * PSU_IOU_SLCR_MIO_PIN_1_L3_SEL 0 + + * Configures MIO Pin 1 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180004, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_1_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_2 @ 0XFF180008 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI + * Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus) + * PSU_IOU_SLCR_MIO_PIN_2_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_2_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[2]- (Test Scan Port) = test_scan, Output, test_scan_out[2 + * ]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_2_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[2]- (GPIO bank 0) 1= can0, Input, can0_phy_ + * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + * , Output, i2c0_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTAG + * TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc2, I + * nput, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver se + * rial input) 7= trace, Output, tracedq[0]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_2_L3_SEL 0 + + * Configures MIO Pin 2 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180008, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_2_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_3 @ 0XFF18000C + + * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI + * Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus) + * PSU_IOU_SLCR_MIO_PIN_3_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_3_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[3]- (Test Scan Port) = test_scan, Output, test_scan_out[3 + * ]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_3_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[3]- (GPIO bank 0) 1= can0, Output, can0_phy + * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + * 0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG + * TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output + * , spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- + * (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial + * output) 7= trace, Output, tracedq[1]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_3_L3_SEL 0 + + * Configures MIO Pin 3 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF18000C, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_3_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_4 @ 0XFF180010 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- ( + * QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Databus) + * PSU_IOU_SLCR_MIO_PIN_4_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_4_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[4]- (Test Scan Port) = test_scan, Output, test_scan_out[4 + * ]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_4_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[4]- (GPIO bank 0) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Wa + * tch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi + * 0, Output, spi0_so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Cloc + * k) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, O + * utput, tracedq[2]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_4_L3_SEL 0 + + * Configures MIO Pin 4 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180010, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_4_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_5 @ 0XFF180014 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out- + * (QSPI Slave Select) + * PSU_IOU_SLCR_MIO_PIN_5_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_5_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[5]- (Test Scan Port) = test_scan, Output, test_scan_out[5 + * ]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_5_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[5]- (GPIO bank 0) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (W + * atch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= + * spi0, Input, spi0_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC + * Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= + * trace, Output, tracedq[3]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_5_L3_SEL 0 + + * Configures MIO Pin 5 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180014, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_5_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_6 @ 0XFF180018 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_clk_for_l + * pbk- (QSPI Clock to be fed-back) + * PSU_IOU_SLCR_MIO_PIN_6_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_6_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[6]- (Test Scan Port) = test_scan, Output, test_scan_out[6 + * ]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_6_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[6]- (GPIO bank 0) 1= can0, Input, can0_phy_ + * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + * , Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Wat + * ch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= s + * pi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TT + * C Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, + * Output, tracedq[4]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_6_L3_SEL 0 + + * Configures MIO Pin 6 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180018, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_6_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_7 @ 0XFF18001C + + * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out_ + * upper- (QSPI Slave Select upper) + * PSU_IOU_SLCR_MIO_PIN_7_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_7_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[7]- (Test Scan Port) = test_scan, Output, test_scan_out[7 + * ]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_7_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[7]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[7]- (GPIO bank 0) 1= can0, Output, can0_phy + * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + * 0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- ( + * Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Ma + * ster Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua + * 0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, t + * racedq[5]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_7_L3_SEL 0 + + * Configures MIO Pin 7 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF18001C, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_7_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_8 @ 0XFF180020 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[0 + * ]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[0]- (QSPI Upper D + * atabus) + * PSU_IOU_SLCR_MIO_PIN_8_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_8_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[8]- (Test Scan Port) = test_scan, Output, test_scan_out[8 + * ]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_8_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[8]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[8]- (GPIO bank 0) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Wa + * tch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Maste + * r Selects) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_ + * txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Tra + * ce Port Databus) + * PSU_IOU_SLCR_MIO_PIN_8_L3_SEL 0 + + * Configures MIO Pin 8 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180020, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_8_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_9 @ 0XFF180024 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[1 + * ]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[1]- (QSPI Upper D + * atabus) + * PSU_IOU_SLCR_MIO_PIN_9_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NA + * ND chip enable) + * PSU_IOU_SLCR_MIO_PIN_9_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[9]- (Test Scan Port) = test_scan, Output, test_scan_out[9 + * ]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_9_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[9]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[9]- (GPIO bank 0) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (W + * atch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master S + * elects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc3, + * Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UA + * RT receiver serial input) 7= trace, Output, tracedq[7]- (Trace Port Data + * bus) + * PSU_IOU_SLCR_MIO_PIN_9_L3_SEL 0 + + * Configures MIO Pin 9 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180024, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_9_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_10 @ 0XFF180028 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[2 + * ]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[2]- (QSPI Upper D + * atabus) + * PSU_IOU_SLCR_MIO_PIN_10_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (N + * AND Ready/Busy) + * PSU_IOU_SLCR_MIO_PIN_10_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[10]- (Test Scan Port) = test_scan, Output, test_scan_out[ + * 10]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_10_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[10]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[10]- (GPIO bank 0) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= sp + * i1, Output, spi1_so- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clo + * ck) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outpu + * t, tracedq[8]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_10_L3_SEL 0 + + * Configures MIO Pin 10 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180028, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_10_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_11 @ 0XFF18002C + + * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[3 + * ]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[3]- (QSPI Upper D + * atabus) + * PSU_IOU_SLCR_MIO_PIN_11_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (N + * AND Ready/Busy) + * PSU_IOU_SLCR_MIO_PIN_11_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[11]- (Test Scan Port) = test_scan, Output, test_scan_out[ + * 11]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_11_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) + * 4= spi1, Input, spi1_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- ( + * TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial ou + * tput) 7= trace, Output, tracedq[9]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_11_L3_SEL 0 + + * Configures MIO Pin 11 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF18002C, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_11_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_12 @ 0XFF180030 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out_ + * upper- (QSPI Upper Clock) + * PSU_IOU_SLCR_MIO_PIN_12_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NA + * ND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe) + * PSU_IOU_SLCR_MIO_PIN_12_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[12]- (Test Scan Port) = test_scan, Output, test_scan_out[ + * 12]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_12_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[12]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[12]- (GPIO bank 0) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJT + * AG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_ + * sclk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, O + * utput, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace + * dq[10]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_12_L3_SEL 0 + + * Configures MIO Pin 12 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180030, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_12_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_13 @ 0XFF180034 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_13_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[0]- (NA + * ND chip enable) + * PSU_IOU_SLCR_MIO_PIN_13_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[13]- (Test Scan Port) = test_scan, Output, + * test_scan_out[13]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_13_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[13]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[13]- (GPIO bank 0) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTA + * G TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, + * Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UAR + * T receiver serial input) 7= trace, Output, tracedq[11]- (Trace Port Data + * bus) + * PSU_IOU_SLCR_MIO_PIN_13_L3_SEL 0 + + * Configures MIO Pin 13 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180034, 0x000000FEU ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_13_OFFSET, 0x000000FEU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_14 @ 0XFF180038 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_14_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_cle- (NAND + * Command Latch Enable) + * PSU_IOU_SLCR_MIO_PIN_14_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[14]- (Test Scan Port) = test_scan, Output, + * test_scan_out[14]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_14_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJT + * AG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, + * Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver + * serial input) 7= trace, Output, tracedq[12]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_14_L3_SEL 2 + + * Configures MIO Pin 14 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180038, 0x000000FEU ,0x00000040U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_14_OFFSET, 0x000000FEU, 0x00000040U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_15 @ 0XFF18003C + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_15_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ale- (NAND + * Address Latch Enable) + * PSU_IOU_SLCR_MIO_PIN_15_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[15]- (Test Scan Port) = test_scan, Output, + * test_scan_out[15]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_15_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[15]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[15]- (GPIO bank 0) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJT + * AG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Outp + * ut, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_ou + * t- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter seria + * l output) 7= trace, Output, tracedq[13]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_15_L3_SEL 2 + + * Configures MIO Pin 15 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF18003C, 0x000000FEU ,0x00000040U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_15_OFFSET, 0x000000FEU, 0x00000040U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_16 @ 0XFF180040 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_16_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[0]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[0]- (NAND Data Bus) + * PSU_IOU_SLCR_MIO_PIN_16_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[16]- (Test Scan Port) = test_scan, Output, + * test_scan_out[16]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_16_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[16]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[16]- (GPIO bank 0) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= s + * pi0, Output, spi0_so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Cl + * ock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, + * Output, tracedq[14]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_16_L3_SEL 2 + + * Configures MIO Pin 16 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180040, 0x000000FEU ,0x00000040U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_16_OFFSET, 0x000000FEU, 0x00000040U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_17 @ 0XFF180044 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_17_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[1]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[1]- (NAND Data Bus) + * PSU_IOU_SLCR_MIO_PIN_17_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[17]- (Test Scan Port) = test_scan, Output, + * test_scan_out[17]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_17_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[17]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[17]- (GPIO bank 0) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4 + * = spi0, Input, spi0_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (T + * TC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) + * 7= trace, Output, tracedq[15]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_17_L3_SEL 2 + + * Configures MIO Pin 17 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180044, 0x000000FEU ,0x00000040U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_17_OFFSET, 0x000000FEU, 0x00000040U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_18 @ 0XFF180048 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_18_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[2]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[2]- (NAND Data Bus) + * PSU_IOU_SLCR_MIO_PIN_18_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[18]- (Test Scan Port) = test_scan, Output, + * test_scan_out[18]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU + * Ext Tamper) + * PSU_IOU_SLCR_MIO_PIN_18_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[18]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[18]- (GPIO bank 0) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= sp + * i1, Output, spi1_so- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clo + * ck) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_18_L3_SEL 6 + + * Configures MIO Pin 18 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180048, 0x000000FEU ,0x000000C0U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_18_OFFSET, 0x000000FEU, 0x000000C0U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_19 @ 0XFF18004C + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_19_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[3]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[3]- (NAND Data Bus) + * PSU_IOU_SLCR_MIO_PIN_19_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[19]- (Test Scan Port) = test_scan, Output, + * test_scan_out[19]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU + * Ext Tamper) + * PSU_IOU_SLCR_MIO_PIN_19_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[19]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[19]- (GPIO bank 0) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI + * Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= + * ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_19_L3_SEL 6 + + * Configures MIO Pin 19 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF18004C, 0x000000FEU ,0x000000C0U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_19_OFFSET, 0x000000FEU, 0x000000C0U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_20 @ 0XFF180050 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_20_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[4]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[4]- (NAND Data Bus) + * PSU_IOU_SLCR_MIO_PIN_20_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[20]- (Test Scan Port) = test_scan, Output, + * test_scan_out[20]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU + * Ext Tamper) + * PSU_IOU_SLCR_MIO_PIN_20_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[20]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[20]- (GPIO bank 0) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Mas + * ter Selects) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua + * 1_txd- (UART transmitter serial output) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_20_L3_SEL 6 + + * Configures MIO Pin 20 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180050, 0x000000FEU ,0x000000C0U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_20_OFFSET, 0x000000FEU, 0x000000C0U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_21 @ 0XFF180054 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_21_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[5]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[5]- (NAND Data Bus) + * PSU_IOU_SLCR_MIO_PIN_21_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Com + * mand Indicator) = sd0, Output, sdio0_cmd_out- (Command Indicator) 2= tes + * t_scan, Input, test_scan_in[21]- (Test Scan Port) = test_scan, Output, t + * est_scan_out[21]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU E + * xt Tamper) + * PSU_IOU_SLCR_MIO_PIN_21_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[21]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[21]- (GPIO bank 0) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master + * Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc + * 1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- ( + * UART receiver serial input) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_21_L3_SEL 6 + + * Configures MIO Pin 21 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180054, 0x000000FEU ,0x000000C0U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_21_OFFSET, 0x000000FEU, 0x000000C0U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_22 @ 0XFF180058 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_22_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_we_b- (NAN + * D Write Enable) + * PSU_IOU_SLCR_MIO_PIN_22_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- + * (SDSDIO clock) 2= test_scan, Input, test_scan_in[22]- (Test Scan Port) = + * test_scan, Output, test_scan_out[22]- (Test Scan Port) 3= csu, Input, c + * su_ext_tamper- (CSU Ext Tamper) + * PSU_IOU_SLCR_MIO_PIN_22_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[22]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[22]- (GPIO bank 0) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= + * spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- ( + * TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not U + * sed + * PSU_IOU_SLCR_MIO_PIN_22_L3_SEL 0 + + * Configures MIO Pin 22 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180058, 0x000000FEU ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_22_OFFSET, 0x000000FEU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_23 @ 0XFF18005C + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_23_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[6]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[6]- (NAND Data Bus) + * PSU_IOU_SLCR_MIO_PIN_23_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- + * (SD card bus power) 2= test_scan, Input, test_scan_in[23]- (Test Scan Po + * rt) = test_scan, Output, test_scan_out[23]- (Test Scan Port) 3= csu, Inp + * ut, csu_ext_tamper- (CSU Ext Tamper) + * PSU_IOU_SLCR_MIO_PIN_23_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[23]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[23]- (GPIO bank 0) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) + * 4= spi1, Input, spi1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- ( + * TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial ou + * tput) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_23_L3_SEL 0 + + * Configures MIO Pin 23 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF18005C, 0x000000FEU ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_23_OFFSET, 0x000000FEU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_24 @ 0XFF180060 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_24_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[7]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[7]- (NAND Data Bus) + * PSU_IOU_SLCR_MIO_PIN_24_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD + * card detect from connector) 2= test_scan, Input, test_scan_in[24]- (Test + * Scan Port) = test_scan, Output, test_scan_out[24]- (Test Scan Port) 3= + * csu, Input, csu_ext_tamper- (CSU Ext Tamper) + * PSU_IOU_SLCR_MIO_PIN_24_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[24]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[24]- (GPIO bank 0) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= Not Used 5= ttc3, Input, ttc3_clk_in- (T + * TC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= N + * ot Used + * PSU_IOU_SLCR_MIO_PIN_24_L3_SEL 1 + + * Configures MIO Pin 24 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180060, 0x000000FEU ,0x00000020U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_24_OFFSET, 0x000000FEU, 0x00000020U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_25 @ 0XFF180064 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_25_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_re_n- (NAN + * D Read Enable) + * PSU_IOU_SLCR_MIO_PIN_25_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD ca + * rd write protect from connector) 2= test_scan, Input, test_scan_in[25]- + * (Test Scan Port) = test_scan, Output, test_scan_out[25]- (Test Scan Port + * ) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper) + * PSU_IOU_SLCR_MIO_PIN_25_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[25]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[25]- (GPIO bank 0) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= Not Used 5= ttc3, Output, ttc3_wave_ou + * t- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial in + * put) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_25_L3_SEL 1 + + * Configures MIO Pin 25 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180064, 0x000000FEU ,0x00000020U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_25_OFFSET, 0x000000FEU, 0x00000020U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_26 @ 0XFF180068 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ + * clk- (TX RGMII clock) + * PSU_IOU_SLCR_MIO_PIN_26_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NA + * ND chip enable) + * PSU_IOU_SLCR_MIO_PIN_26_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[0]- (PMU + * GPI) 2= test_scan, Input, test_scan_in[26]- (Test Scan Port) = test_sca + * n, Output, test_scan_out[26]- (Test Scan Port) 3= csu, Input, csu_ext_ta + * mper- (CSU Ext Tamper) + * PSU_IOU_SLCR_MIO_PIN_26_L2_SEL 0 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[0]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[0]- (GPIO bank 1) 1= can0, Input, can0_phy_ + * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + * , Output, i2c0_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG + * TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_scl + * k_out- (SPI Clock) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Inpu + * t, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- ( + * Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_26_L3_SEL 0 + + * Configures MIO Pin 26 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180068, 0x000000FEU ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_26_OFFSET, 0x000000FEU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_27 @ 0XFF18006C + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd + * [0]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_27_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (N + * AND Ready/Busy) + * PSU_IOU_SLCR_MIO_PIN_27_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[1]- (PMU + * GPI) 2= test_scan, Input, test_scan_in[27]- (Test Scan Port) = test_sca + * n, Output, test_scan_out[27]- (Test Scan Port) 3= dpaux, Input, dp_aux_d + * ata_in- (Dp Aux Data) = dpaux, Output, dp_aux_data_out- (Dp Aux Data) + * PSU_IOU_SLCR_MIO_PIN_27_L2_SEL 3 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[1]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[1]- (GPIO bank 1) 1= can0, Output, can0_phy + * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + * 0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG + * TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc2, O + * utput, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UAR + * T transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port D + * atabus) + * PSU_IOU_SLCR_MIO_PIN_27_L3_SEL 0 + + * Configures MIO Pin 27 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF18006C, 0x000000FEU ,0x00000018U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_27_OFFSET, 0x000000FEU, 0x00000018U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_28 @ 0XFF180070 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd + * [1]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_28_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (N + * AND Ready/Busy) + * PSU_IOU_SLCR_MIO_PIN_28_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[2]- (PMU + * GPI) 2= test_scan, Input, test_scan_in[28]- (Test Scan Port) = test_sca + * n, Output, test_scan_out[28]- (Test Scan Port) 3= dpaux, Input, dp_hot_p + * lug_detect- (Dp Aux Hot Plug) + * PSU_IOU_SLCR_MIO_PIN_28_L2_SEL 3 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[2]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[2]- (GPIO bank 1) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTA + * G TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc1, + * Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitt + * er serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_28_L3_SEL 0 + + * Configures MIO Pin 28 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180070, 0x000000FEU ,0x00000018U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_28_OFFSET, 0x000000FEU, 0x00000018U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_29 @ 0XFF180074 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd + * [2]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_29_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + * PCIE Reset signal) + * PSU_IOU_SLCR_MIO_PIN_29_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[3]- (PMU + * GPI) 2= test_scan, Input, test_scan_in[29]- (Test Scan Port) = test_sca + * n, Output, test_scan_out[29]- (Test Scan Port) 3= dpaux, Input, dp_aux_d + * ata_in- (Dp Aux Data) = dpaux, Output, dp_aux_data_out- (Dp Aux Data) + * PSU_IOU_SLCR_MIO_PIN_29_L2_SEL 3 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[3]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[3]- (GPIO bank 1) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG + * TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, + * spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- + * (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input + * ) 7= trace, Output, tracedq[7]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_29_L3_SEL 0 + + * Configures MIO Pin 29 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180074, 0x000000FEU ,0x00000018U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_29_OFFSET, 0x000000FEU, 0x00000018U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_30 @ 0XFF180078 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd + * [3]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_30_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + * PCIE Reset signal) + * PSU_IOU_SLCR_MIO_PIN_30_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[4]- (PMU + * GPI) 2= test_scan, Input, test_scan_in[30]- (Test Scan Port) = test_sca + * n, Output, test_scan_out[30]- (Test Scan Port) 3= dpaux, Input, dp_hot_p + * lug_detect- (Dp Aux Hot Plug) + * PSU_IOU_SLCR_MIO_PIN_30_L2_SEL 3 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[4]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[4]- (GPIO bank 1) 1= can0, Input, can0_phy_ + * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + * , Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Wat + * ch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0 + * , Output, spi0_so- (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clock + * ) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, + * tracedq[8]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_30_L3_SEL 0 + + * Configures MIO Pin 30 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180078, 0x000000FEU ,0x00000018U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_30_OFFSET, 0x000000FEU, 0x00000018U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_31 @ 0XFF18007C + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ + * ctl- (TX RGMII control) + * PSU_IOU_SLCR_MIO_PIN_31_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + * PCIE Reset signal) + * PSU_IOU_SLCR_MIO_PIN_31_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[5]- (PMU + * GPI) 2= test_scan, Input, test_scan_in[31]- (Test Scan Port) = test_sca + * n, Output, test_scan_out[31]- (Test Scan Port) 3= csu, Input, csu_ext_ta + * mper- (CSU Ext Tamper) + * PSU_IOU_SLCR_MIO_PIN_31_L2_SEL 0 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[5]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[5]- (GPIO bank 1) 1= can0, Output, can0_phy + * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + * 0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- ( + * Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= + * spi0, Input, spi0_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TT + * C Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial outp + * ut) 7= trace, Output, tracedq[9]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_31_L3_SEL 0 + + * Configures MIO Pin 31 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF18007C, 0x000000FEU ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_31_OFFSET, 0x000000FEU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_32 @ 0XFF180080 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_c + * lk- (RX RGMII clock) + * PSU_IOU_SLCR_MIO_PIN_32_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NA + * ND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe) + * PSU_IOU_SLCR_MIO_PIN_32_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[0]- (PM + * U GPI) 2= test_scan, Input, test_scan_in[32]- (Test Scan Port) = test_sc + * an, Output, test_scan_out[32]- (Test Scan Port) 3= csu, Input, csu_ext_t + * amper- (CSU Ext Tamper) + * PSU_IOU_SLCR_MIO_PIN_32_L2_SEL 1 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[6]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[6]- (GPIO bank 1) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Wa + * tch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= + * spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (T + * TC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= t + * race, Output, tracedq[10]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_32_L3_SEL 0 + + * Configures MIO Pin 32 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180080, 0x000000FEU ,0x00000008U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_32_OFFSET, 0x000000FEU, 0x00000008U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_33 @ 0XFF180084 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[ + * 0]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_33_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + * PCIE Reset signal) + * PSU_IOU_SLCR_MIO_PIN_33_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[1]- (PM + * U GPI) 2= test_scan, Input, test_scan_in[33]- (Test Scan Port) = test_sc + * an, Output, test_scan_out[33]- (Test Scan Port) 3= csu, Input, csu_ext_t + * amper- (CSU Ext Tamper) + * PSU_IOU_SLCR_MIO_PIN_33_L2_SEL 1 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[7]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[7]- (GPIO bank 1) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (W + * atch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Mas + * ter Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1 + * , Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq + * [11]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_33_L3_SEL 0 + + * Configures MIO Pin 33 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180084, 0x000000FEU ,0x00000008U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_33_OFFSET, 0x000000FEU, 0x00000008U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_34 @ 0XFF180088 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[ + * 1]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_34_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + * PCIE Reset signal) + * PSU_IOU_SLCR_MIO_PIN_34_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[2]- (PM + * U GPI) 2= test_scan, Input, test_scan_in[34]- (Test Scan Port) = test_sc + * an, Output, test_scan_out[34]- (Test Scan Port) 3= dpaux, Input, dp_aux_ + * data_in- (Dp Aux Data) = dpaux, Output, dp_aux_data_out- (Dp Aux Data) + * PSU_IOU_SLCR_MIO_PIN_34_L2_SEL 1 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[8]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[8]- (GPIO bank 1) 1= can0, Input, can0_phy_ + * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + * , Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Wat + * ch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master + * Selects) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rx + * d- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace Po + * rt Databus) + * PSU_IOU_SLCR_MIO_PIN_34_L3_SEL 0 + + * Configures MIO Pin 34 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180088, 0x000000FEU ,0x00000008U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_34_OFFSET, 0x000000FEU, 0x00000008U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_35 @ 0XFF18008C + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[ + * 2]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_35_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + * PCIE Reset signal) + * PSU_IOU_SLCR_MIO_PIN_35_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[3]- (PM + * U GPI) 2= test_scan, Input, test_scan_in[35]- (Test Scan Port) = test_sc + * an, Output, test_scan_out[35]- (Test Scan Port) 3= dpaux, Input, dp_hot_ + * plug_detect- (Dp Aux Hot Plug) + * PSU_IOU_SLCR_MIO_PIN_35_L2_SEL 1 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[9]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[9]- (GPIO bank 1) 1= can0, Output, can0_phy + * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + * 0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- ( + * Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master + * Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc2 + * , Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- ( + * UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace Po + * rt Databus) + * PSU_IOU_SLCR_MIO_PIN_35_L3_SEL 0 + + * Configures MIO Pin 35 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF18008C, 0x000000FEU ,0x00000008U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_35_OFFSET, 0x000000FEU, 0x00000008U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_36 @ 0XFF180090 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[ + * 3]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_36_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + * PCIE Reset signal) + * PSU_IOU_SLCR_MIO_PIN_36_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[4]- (PM + * U GPI) 2= test_scan, Input, test_scan_in[36]- (Test Scan Port) = test_sc + * an, Output, test_scan_out[36]- (Test Scan Port) 3= dpaux, Input, dp_aux_ + * data_in- (Dp Aux Data) = dpaux, Output, dp_aux_data_out- (Dp Aux Data) + * PSU_IOU_SLCR_MIO_PIN_36_L2_SEL 1 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[10]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[10]- (GPIO bank 1) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= s + * pi1, Output, spi1_so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Cl + * ock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, + * Output, tracedq[14]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_36_L3_SEL 0 + + * Configures MIO Pin 36 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180090, 0x000000FEU ,0x00000008U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_36_OFFSET, 0x000000FEU, 0x00000008U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_37 @ 0XFF180094 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_c + * tl- (RX RGMII control ) + * PSU_IOU_SLCR_MIO_PIN_37_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + * PCIE Reset signal) + * PSU_IOU_SLCR_MIO_PIN_37_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[5]- (PM + * U GPI) 2= test_scan, Input, test_scan_in[37]- (Test Scan Port) = test_sc + * an, Output, test_scan_out[37]- (Test Scan Port) 3= dpaux, Input, dp_hot_ + * plug_detect- (Dp Aux Hot Plug) + * PSU_IOU_SLCR_MIO_PIN_37_L2_SEL 1 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[11]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[11]- (GPIO bank 1) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4 + * = spi1, Input, spi1_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (T + * TC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) + * 7= trace, Output, tracedq[15]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_37_L3_SEL 0 + + * Configures MIO Pin 37 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180094, 0x000000FEU ,0x00000008U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_37_OFFSET, 0x000000FEU, 0x00000008U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_38 @ 0XFF180098 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ + * clk- (TX RGMII clock) + * PSU_IOU_SLCR_MIO_PIN_38_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_38_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- + * (SDSDIO clock) 2= Not Used 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_38_L2_SEL 0 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[12]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[12]- (GPIO bank 1) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTA + * G TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_s + * clk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, In + * put, ua0_rxd- (UART receiver serial input) 7= trace, Output, trace_clk- + * (Trace Port Clock) + * PSU_IOU_SLCR_MIO_PIN_38_L3_SEL 0 + + * Configures MIO Pin 38 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180098, 0x000000FEU ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_38_OFFSET, 0x000000FEU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_39 @ 0XFF18009C + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd + * [0]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_39_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_39_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD + * card detect from connector) 2= sd1, Input, sd1_data_in[4]- (8-bit Data b + * us) = sd1, Output, sdio1_data_out[4]- (8-bit Data bus) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_39_L2_SEL 2 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[13]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[13]- (GPIO bank 1) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJT + * AG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc0, + * Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (U + * ART transmitter serial output) 7= trace, Output, trace_ctl- (Trace Port + * Control Signal) + * PSU_IOU_SLCR_MIO_PIN_39_L3_SEL 0 + + * Configures MIO Pin 39 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF18009C, 0x000000FEU ,0x00000010U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_39_OFFSET, 0x000000FEU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_40 @ 0XFF1800A0 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd + * [1]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_40_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_40_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Com + * mand Indicator) = sd0, Output, sdio0_cmd_out- (Command Indicator) 2= sd1 + * , Input, sd1_data_in[5]- (8-bit Data bus) = sd1, Output, sdio1_data_out[ + * 5]- (8-bit Data bus) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_40_L2_SEL 2 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[14]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[14]- (GPIO bank 1) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJ + * TAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc3 + * , Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmi + * tter serial output) 7= trace, Output, tracedq[0]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_40_L3_SEL 0 + + * Configures MIO Pin 40 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800A0, 0x000000FEU ,0x00000010U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_40_OFFSET, 0x000000FEU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_41 @ 0XFF1800A4 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd + * [2]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_41_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_41_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[6]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[6]- (8-bit Data bus) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_41_L2_SEL 2 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[15]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[15]- (GPIO bank 1) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTA + * G TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Outpu + * t, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out + * - (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial inp + * ut) 7= trace, Output, tracedq[1]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_41_L3_SEL 0 + + * Configures MIO Pin 41 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800A4, 0x000000FEU ,0x00000010U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_41_OFFSET, 0x000000FEU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_42 @ 0XFF1800A8 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd + * [3]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_42_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_42_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[7]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[7]- (8-bit Data bus) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_42_L2_SEL 2 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= sp + * i0, Output, spi0_so- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clo + * ck) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outpu + * t, tracedq[2]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_42_L3_SEL 0 + + * Configures MIO Pin 42 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800A8, 0x000000FEU ,0x00000010U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_42_OFFSET, 0x000000FEU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_43 @ 0XFF1800AC + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ + * ctl- (TX RGMII control) + * PSU_IOU_SLCR_MIO_PIN_43_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_43_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8-bit Data bus) 2= s + * d1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_43_L2_SEL 0 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) + * 4= spi0, Input, spi0_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- ( + * TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial ou + * tput) 7= trace, Output, tracedq[3]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_43_L3_SEL 0 + + * Configures MIO Pin 43 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800AC, 0x000000FEU ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_43_OFFSET, 0x000000FEU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_44 @ 0XFF1800B0 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_c + * lk- (RX RGMII clock) + * PSU_IOU_SLCR_MIO_PIN_44_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_44_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8-bit Data bus) 2= s + * d1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_44_L2_SEL 2 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[18]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[18]- (GPIO bank 1) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4 + * = spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- + * (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= + * Not Used + * PSU_IOU_SLCR_MIO_PIN_44_L3_SEL 0 + + * Configures MIO Pin 44 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800B0, 0x000000FEU ,0x00000010U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_44_OFFSET, 0x000000FEU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_45 @ 0XFF1800B4 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[ + * 0]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_45_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_45_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8-bit Data bus) 2= s + * d1, Input, sdio1_cd_n- (SD card detect from connector) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_45_L2_SEL 2 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[19]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[19]- (GPIO bank 1) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI M + * aster Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= u + * a1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_45_L3_SEL 0 + + * Configures MIO Pin 45 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800B4, 0x000000FEU ,0x00000010U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_45_OFFSET, 0x000000FEU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_46 @ 0XFF1800B8 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[ + * 1]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_46_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_46_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[0]- (8-bit Data bus) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_46_L2_SEL 2 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Mast + * er Selects) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_ + * rxd- (UART receiver serial input) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_46_L3_SEL 0 + + * Configures MIO Pin 46 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800B8, 0x000000FEU ,0x00000010U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_46_OFFSET, 0x000000FEU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_47 @ 0XFF1800BC + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[ + * 2]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_47_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_47_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[1]- (8-bit Data bus) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_47_L2_SEL 2 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Maste + * r Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= tt + * c0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- + * (UART transmitter serial output) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_47_L3_SEL 0 + + * Configures MIO Pin 47 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800BC, 0x000000FEU ,0x00000010U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_47_OFFSET, 0x000000FEU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_48 @ 0XFF1800C0 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[ + * 3]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_48_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_48_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[2]- (8-bit Data bus) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_48_L2_SEL 2 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[22]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[22]- (GPIO bank 1) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= s + * pi1, Output, spi1_so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Cl + * ock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Us + * ed + * PSU_IOU_SLCR_MIO_PIN_48_L3_SEL 0 + + * Configures MIO Pin 48 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800C0, 0x000000FEU ,0x00000010U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_48_OFFSET, 0x000000FEU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_49 @ 0XFF1800C4 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_c + * tl- (RX RGMII control ) + * PSU_IOU_SLCR_MIO_PIN_49_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_49_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- + * (SD card bus power) 2= sd1, Input, sd1_data_in[3]- (8-bit Data bus) = sd + * 1, Output, sdio1_data_out[3]- (8-bit Data bus) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_49_L2_SEL 2 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[23]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[23]- (GPIO bank 1) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4 + * = spi1, Input, spi1_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (T + * TC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) + * 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_49_L3_SEL 0 + + * Configures MIO Pin 49 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800C4, 0x000000FEU ,0x00000010U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_49_OFFSET, 0x000000FEU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_50 @ 0XFF1800C8 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- + * (TSU clock) + * PSU_IOU_SLCR_MIO_PIN_50_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_50_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD ca + * rd write protect from connector) 2= sd1, Input, sd1_cmd_in- (Command Ind + * icator) = sd1, Output, sdio1_cmd_out- (Command Indicator) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_50_L2_SEL 2 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[24]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[24]- (GPIO bank 1) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= + * ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART rece + * iver serial input) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_50_L3_SEL 0 + + * Configures MIO Pin 50 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800C8, 0x000000FEU ,0x00000010U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_50_OFFSET, 0x000000FEU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_51 @ 0XFF1800CC + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- + * (TSU clock) + * PSU_IOU_SLCR_MIO_PIN_51_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_51_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Output, sdi + * o1_clk_out- (SDSDIO clock) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_51_L2_SEL 2 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[25]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[25]- (GPIO bank 1) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= mdio1, Input, gem1_mdio_in- (MDIO Dat + * a) 4= mdio1, Output, gem1_mdio_out- (MDIO Data) 5= ttc2, Output, ttc2_wa + * ve_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter + * serial output) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_51_L3_SEL 0 + + * Configures MIO Pin 51 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800CC, 0x000000FEU ,0x00000010U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_51_OFFSET, 0x000000FEU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_52 @ 0XFF1800D0 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_ + * clk- (TX RGMII clock) + * PSU_IOU_SLCR_MIO_PIN_52_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_clk_i + * n- (ULPI Clock) + * PSU_IOU_SLCR_MIO_PIN_52_L1_SEL 1 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used + * PSU_IOU_SLCR_MIO_PIN_52_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[0]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[0]- (GPIO bank 2) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG + * TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sc + * lk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Out + * put, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_c + * lk- (Trace Port Clock) + * PSU_IOU_SLCR_MIO_PIN_52_L3_SEL 0 + + * Configures MIO Pin 52 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800D0, 0x000000FEU ,0x00000004U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_52_OFFSET, 0x000000FEU, 0x00000004U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_53 @ 0XFF1800D4 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd + * [0]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_53_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_dir- + * (Data bus direction control) + * PSU_IOU_SLCR_MIO_PIN_53_L1_SEL 1 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used + * PSU_IOU_SLCR_MIO_PIN_53_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[1]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[1]- (GPIO bank 2) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG + * TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Ou + * tput, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART + * receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control + * Signal) + * PSU_IOU_SLCR_MIO_PIN_53_L3_SEL 0 + + * Configures MIO Pin 53 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800D4, 0x000000FEU ,0x00000004U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_53_OFFSET, 0x000000FEU, 0x00000004U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_54 @ 0XFF1800D8 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd + * [1]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_54_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[2]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[2]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_54_L1_SEL 1 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used + * PSU_IOU_SLCR_MIO_PIN_54_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[2]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[2]- (GPIO bank 2) 1= can0, Input, can0_phy_ + * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + * , Output, i2c0_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTAG + * TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, I + * nput, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver se + * rial input) 7= trace, Output, tracedq[0]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_54_L3_SEL 0 + + * Configures MIO Pin 54 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800D8, 0x000000FEU ,0x00000004U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_54_OFFSET, 0x000000FEU, 0x00000004U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_55 @ 0XFF1800DC + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd + * [2]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_55_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_nxt- + * (Data flow control signal from the PHY) + * PSU_IOU_SLCR_MIO_PIN_55_L1_SEL 1 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used + * PSU_IOU_SLCR_MIO_PIN_55_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[3]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[3]- (GPIO bank 2) 1= can0, Output, can0_phy + * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + * 0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG + * TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output + * , spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- + * (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial + * output) 7= trace, Output, tracedq[1]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_55_L3_SEL 0 + + * Configures MIO Pin 55 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800DC, 0x000000FEU ,0x00000004U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_55_OFFSET, 0x000000FEU, 0x00000004U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_56 @ 0XFF1800E0 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd + * [3]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_56_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[0]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[0]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_56_L1_SEL 1 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used + * PSU_IOU_SLCR_MIO_PIN_56_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[4]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[4]- (GPIO bank 2) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Wa + * tch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi + * 0, Output, spi0_so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Cloc + * k) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, O + * utput, tracedq[2]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_56_L3_SEL 0 + + * Configures MIO Pin 56 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800E0, 0x000000FEU ,0x00000004U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_56_OFFSET, 0x000000FEU, 0x00000004U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_57 @ 0XFF1800E4 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_ + * ctl- (TX RGMII control) + * PSU_IOU_SLCR_MIO_PIN_57_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[1]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[1]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_57_L1_SEL 1 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used + * PSU_IOU_SLCR_MIO_PIN_57_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[5]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[5]- (GPIO bank 2) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (W + * atch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= + * spi0, Input, spi0_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC + * Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= + * trace, Output, tracedq[3]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_57_L3_SEL 0 + + * Configures MIO Pin 57 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800E4, 0x000000FEU ,0x00000004U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_57_OFFSET, 0x000000FEU, 0x00000004U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_58 @ 0XFF1800E8 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_c + * lk- (RX RGMII clock) + * PSU_IOU_SLCR_MIO_PIN_58_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Output, usb0_ulpi_stp- + * (Asserted to end or interrupt transfers) + * PSU_IOU_SLCR_MIO_PIN_58_L1_SEL 1 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used + * PSU_IOU_SLCR_MIO_PIN_58_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[6]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[6]- (GPIO bank 2) 1= can0, Input, can0_phy_ + * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + * , Output, i2c0_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG + * TCK) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1_scl + * k_out- (SPI Clock) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Inpu + * t, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- ( + * Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_58_L3_SEL 0 + + * Configures MIO Pin 58 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800E8, 0x000000FEU ,0x00000004U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_58_OFFSET, 0x000000FEU, 0x00000004U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_59 @ 0XFF1800EC + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[ + * 0]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_59_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[3]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[3]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_59_L1_SEL 1 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used + * PSU_IOU_SLCR_MIO_PIN_59_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[7]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[7]- (GPIO bank 2) 1= can0, Output, can0_phy + * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + * 0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG + * TDI) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= ttc2, O + * utput, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UAR + * T transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port D + * atabus) + * PSU_IOU_SLCR_MIO_PIN_59_L3_SEL 0 + + * Configures MIO Pin 59 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800EC, 0x000000FEU ,0x00000004U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_59_OFFSET, 0x000000FEU, 0x00000004U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_60 @ 0XFF1800F0 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[ + * 1]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_60_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[4]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[4]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_60_L1_SEL 1 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used + * PSU_IOU_SLCR_MIO_PIN_60_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[8]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[8]- (GPIO bank 2) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTA + * G TDO) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc1, + * Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitt + * er serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_60_L3_SEL 0 + + * Configures MIO Pin 60 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800F0, 0x000000FEU ,0x00000004U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_60_OFFSET, 0x000000FEU, 0x00000004U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_61 @ 0XFF1800F4 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[ + * 2]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_61_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[5]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[5]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_61_L1_SEL 1 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used + * PSU_IOU_SLCR_MIO_PIN_61_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[9]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[9]- (GPIO bank 2) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG + * TMS) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, Output, + * spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- + * (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input + * ) 7= trace, Output, tracedq[7]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_61_L3_SEL 0 + + * Configures MIO Pin 61 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800F4, 0x000000FEU ,0x00000004U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_61_OFFSET, 0x000000FEU, 0x00000004U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_62 @ 0XFF1800F8 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[ + * 3]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_62_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[6]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[6]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_62_L1_SEL 1 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used + * PSU_IOU_SLCR_MIO_PIN_62_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[10]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[10]- (GPIO bank 2) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= sp + * i1, Output, spi1_so- (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clo + * ck) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outpu + * t, tracedq[8]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_62_L3_SEL 0 + + * Configures MIO Pin 62 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800F8, 0x000000FEU ,0x00000004U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_62_OFFSET, 0x000000FEU, 0x00000004U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_63 @ 0XFF1800FC + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_c + * tl- (RX RGMII control ) + * PSU_IOU_SLCR_MIO_PIN_63_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[7]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[7]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_63_L1_SEL 1 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used + * PSU_IOU_SLCR_MIO_PIN_63_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[11]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[11]- (GPIO bank 2) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) + * 4= spi1, Input, spi1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- ( + * TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial ou + * tput) 7= trace, Output, tracedq[9]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_63_L3_SEL 0 + + * Configures MIO Pin 63 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800FC, 0x000000FEU ,0x00000004U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_63_OFFSET, 0x000000FEU, 0x00000004U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_64 @ 0XFF180100 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_ + * clk- (TX RGMII clock) + * PSU_IOU_SLCR_MIO_PIN_64_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_clk_i + * n- (ULPI Clock) + * PSU_IOU_SLCR_MIO_PIN_64_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- + * (SDSDIO clock) 2= Not Used 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_64_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[12]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[12]- (GPIO bank 2) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4 + * = spi0, Output, spi0_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- + * (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= + * trace, Output, tracedq[10]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_64_L3_SEL 0 + + * Configures MIO Pin 64 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180100, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_64_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_65 @ 0XFF180104 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd + * [0]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_65_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_dir- + * (Data bus direction control) + * PSU_IOU_SLCR_MIO_PIN_65_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD + * card detect from connector) 2= Not Used 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_65_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[13]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[13]- (GPIO bank 2) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi0, Output, spi0_n_ss_out[2]- (SPI M + * aster Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= u + * a1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trace + * dq[11]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_65_L3_SEL 0 + + * Configures MIO Pin 65 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180104, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_65_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_66 @ 0XFF180108 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd + * [1]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_66_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[2]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[2]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_66_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Com + * mand Indicator) = sd0, Output, sdio0_cmd_out- (Command Indicator) 2= Not + * Used 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_66_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[14]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[14]- (GPIO bank 2) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Mast + * er Selects) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_ + * rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace + * Port Databus) + * PSU_IOU_SLCR_MIO_PIN_66_L3_SEL 0 + + * Configures MIO Pin 66 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180108, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_66_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_67 @ 0XFF18010C + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd + * [2]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_67_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_nxt- + * (Data flow control signal from the PHY) + * PSU_IOU_SLCR_MIO_PIN_67_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8-bit Data bus) 2= N + * ot Used 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_67_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[15]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[15]- (GPIO bank 2) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi0, Input, spi0_n_ss_in- (SPI Maste + * r Selects) 4= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 5= tt + * c2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- + * (UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace + * Port Databus) + * PSU_IOU_SLCR_MIO_PIN_67_L3_SEL 0 + + * Configures MIO Pin 67 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF18010C, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_67_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_68 @ 0XFF180110 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd + * [3]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_68_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[0]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[0]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_68_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8-bit Data bus) 2= N + * ot Used 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_68_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[16]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[16]- (GPIO bank 2) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= s + * pi0, Output, spi0_so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Cl + * ock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, + * Output, tracedq[14]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_68_L3_SEL 0 + + * Configures MIO Pin 68 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180110, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_68_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_69 @ 0XFF180114 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_ + * ctl- (TX RGMII control) + * PSU_IOU_SLCR_MIO_PIN_69_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[1]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[1]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_69_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8-bit Data bus) 2= s + * d1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_69_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[17]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[17]- (GPIO bank 2) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4 + * = spi0, Input, spi0_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (T + * TC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) + * 7= trace, Output, tracedq[15]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_69_L3_SEL 0 + + * Configures MIO Pin 69 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180114, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_69_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_70 @ 0XFF180118 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_c + * lk- (RX RGMII clock) + * PSU_IOU_SLCR_MIO_PIN_70_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Output, usb1_ulpi_stp- + * (Asserted to end or interrupt transfers) + * PSU_IOU_SLCR_MIO_PIN_70_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8-bit Data bus) 2= s + * d1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_70_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[18]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[18]- (GPIO bank 2) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= + * spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- ( + * TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not U + * sed + * PSU_IOU_SLCR_MIO_PIN_70_L3_SEL 0 + + * Configures MIO Pin 70 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180118, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_70_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_71 @ 0XFF18011C + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[ + * 0]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_71_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[3]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[3]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_71_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[0]- (8-bit Data bus) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_71_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[19]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[19]- (GPIO bank 2) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI + * Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= + * ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_71_L3_SEL 0 + + * Configures MIO Pin 71 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF18011C, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_71_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_72 @ 0XFF180120 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[ + * 1]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_72_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[4]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[4]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_72_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[1]- (8-bit Data bus) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_72_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[20]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[20]- (GPIO bank 2) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Mas + * ter Selects) 5= Not Used 6= ua1, Output, ua1_txd- (UART transmitter seri + * al output) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_72_L3_SEL 0 + + * Configures MIO Pin 72 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180120, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_72_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_73 @ 0XFF180124 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[ + * 2]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_73_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[5]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_73_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[2]- (8-bit Data bus) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_73_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[21]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[21]- (GPIO bank 2) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master + * Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= Not + * Used 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_73_L3_SEL 0 + + * Configures MIO Pin 73 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180124, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_73_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_74 @ 0XFF180128 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[ + * 3]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_74_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[6]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[6]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_74_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[3]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[3]- (8-bit Data bus) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_74_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[22]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[22]- (GPIO bank 2) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= sp + * i1, Output, spi1_so- (MISO signal) 5= Not Used 6= ua0, Input, ua0_rxd- ( + * UART receiver serial input) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_74_L3_SEL 0 + + * Configures MIO Pin 74 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180128, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_74_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_75 @ 0XFF18012C + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_c + * tl- (RX RGMII control ) + * PSU_IOU_SLCR_MIO_PIN_75_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[7]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[7]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_75_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- + * (SD card bus power) 2= sd1, Input, sd1_cmd_in- (Command Indicator) = sd1 + * , Output, sdio1_cmd_out- (Command Indicator) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_75_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[23]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[23]- (GPIO bank 2) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) + * 4= spi1, Input, spi1_si- (MOSI signal) 5= Not Used 6= ua0, Output, ua0_t + * xd- (UART transmitter serial output) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_75_L3_SEL 0 + + * Configures MIO Pin 75 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF18012C, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_75_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_76 @ 0XFF180130 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_76_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_76_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD ca + * rd write protect from connector) 2= sd1, Output, sdio1_clk_out- (SDSDIO + * clock) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_76_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[24]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[24]- (GPIO bank 2) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= mdio0, Output, gem0_mdc- (MDI + * O Clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= mdio2, Output, gem2 + * _mdc- (MDIO Clock) 6= mdio3, Output, gem3_mdc- (MDIO Clock) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_76_L3_SEL 6 + + * Configures MIO Pin 76 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180130, 0x000000FEU ,0x000000C0U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_76_OFFSET, 0x000000FEU, 0x000000C0U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_77 @ 0XFF180134 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_77_L0_SEL 0 - Block level reset - PSU_CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET 0 + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_77_L1_SEL 0 - Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset. - (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00100000U ,0x00000000U) - RegMask = (CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_MASK | 0 ); + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Input, sdio + * 1_cd_n- (SD card detect from connector) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_77_L2_SEL 0 - RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RST_LPD_IOU2_OFFSET ,0x00100000U ,0x00000000U); - /*############################################################################################################################ */ + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[25]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[25]- (GPIO bank 2) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= mdio0, Input, gem0_mdio_in- (M + * DIO Data) 3= mdio0, Output, gem0_mdio_out- (MDIO Data) 4= mdio1, Input, + * gem1_mdio_in- (MDIO Data) 4= mdio1, Output, gem1_mdio_out- (MDIO Data) 5 + * = mdio2, Input, gem2_mdio_in- (MDIO Data) 5= mdio2, Output, gem2_mdio_ou + * t- (MDIO Data) 6= mdio3, Input, gem3_mdio_in- (MDIO Data) 6= mdio3, Outp + * ut, gem3_mdio_out- (MDIO Data) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_77_L3_SEL 6 - // : ENET - /*Register : RST_LPD_IOU0 @ 0XFF5E0230

+ * Configures MIO Pin 77 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180134, 0x000000FEU ,0x000000C0U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_77_OFFSET, 0x000000FEU, 0x000000C0U); +/*##################################################################### */ - GEM 3 reset - PSU_CRL_APB_RST_LPD_IOU0_GEM3_RESET 0 + /* + * Register : MIO_MST_TRI0 @ 0XFF180204 - Software controlled reset for the GEMs - (OFFSET, MASK, VALUE) (0XFF5E0230, 0x00000008U ,0x00000000U) - RegMask = (CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK | 0 ); + * Master Tri-state Enable for pin 0, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI 0 - RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RST_LPD_IOU0_OFFSET ,0x00000008U ,0x00000000U); - /*############################################################################################################################ */ + * Master Tri-state Enable for pin 1, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI 0 - // : QSPI - /*Register : RST_LPD_IOU2 @ 0XFF5E0238

+ * Master Tri-state Enable for pin 2, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI 0 - Block level reset - PSU_CRL_APB_RST_LPD_IOU2_QSPI_RESET 0 + * Master Tri-state Enable for pin 3, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI 0 - Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset. - (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000001U ,0x00000000U) - RegMask = (CRL_APB_RST_LPD_IOU2_QSPI_RESET_MASK | 0 ); + * Master Tri-state Enable for pin 4, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI 0 - RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU2_QSPI_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RST_LPD_IOU2_OFFSET ,0x00000001U ,0x00000000U); - /*############################################################################################################################ */ + * Master Tri-state Enable for pin 5, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI 0 - // : QSPI TAP DELAY - /*Register : IOU_TAPDLY_BYPASS @ 0XFF180390

+ * Master Tri-state Enable for pin 6, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI 0 - 0: Do not by pass the tap delays on the Rx clock signal of LQSPI 1: Bypass the Tap delay on the Rx clock signal of LQSPI - PSU_IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX 1 + * Master Tri-state Enable for pin 7, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI 0 - IOU tap delay bypass for the LQSPI and NAND controllers - (OFFSET, MASK, VALUE) (0XFF180390, 0x00000004U ,0x00000004U) - RegMask = (IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_MASK | 0 ); + * Master Tri-state Enable for pin 8, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI 0 - RegVal = ((0x00000001U << IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_IOU_TAPDLY_BYPASS_OFFSET ,0x00000004U ,0x00000004U); - /*############################################################################################################################ */ + * Master Tri-state Enable for pin 9, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI 0 - // : NAND - // : USB - /*Register : RST_LPD_TOP @ 0XFF5E023C

+ * Master Tri-state Enable for pin 10, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI 0 - USB 0 reset for control registers - PSU_CRL_APB_RST_LPD_TOP_USB0_APB_RESET 0 + * Master Tri-state Enable for pin 11, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI 0 - USB 0 sleep circuit reset - PSU_CRL_APB_RST_LPD_TOP_USB0_HIBERRESET 0 + * Master Tri-state Enable for pin 12, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI 0 - USB 0 reset - PSU_CRL_APB_RST_LPD_TOP_USB0_CORERESET 0 + * Master Tri-state Enable for pin 13, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI 0 - Software control register for the LPD block. - (OFFSET, MASK, VALUE) (0XFF5E023C, 0x00000540U ,0x00000000U) - RegMask = (CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK | CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK | CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK | 0 ); + * Master Tri-state Enable for pin 14, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI 0 - RegVal = ((0x00000000U << CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT - | 0x00000000U << CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT - | 0x00000000U << CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RST_LPD_TOP_OFFSET ,0x00000540U ,0x00000000U); - /*############################################################################################################################ */ + * Master Tri-state Enable for pin 15, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI 0 - // : FPD RESET - /*Register : RST_FPD_TOP @ 0XFD1A0100

+ * Master Tri-state Enable for pin 16, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI 0 - PCIE config reset - PSU_CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET 0 + * Master Tri-state Enable for pin 17, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI 0 - PCIE control block level reset - PSU_CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET 0 + * Master Tri-state Enable for pin 18, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI 1 - PCIE bridge block level reset (AXI interface) - PSU_CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET 0 + * Master Tri-state Enable for pin 19, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI 0 - Display Port block level reset (includes DPDMA) - PSU_CRF_APB_RST_FPD_TOP_DP_RESET 0 + * Master Tri-state Enable for pin 20, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI 0 - FPD WDT reset - PSU_CRF_APB_RST_FPD_TOP_SWDT_RESET 0 + * Master Tri-state Enable for pin 21, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI 1 - GDMA block level reset - PSU_CRF_APB_RST_FPD_TOP_GDMA_RESET 0 + * Master Tri-state Enable for pin 22, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI 0 - Pixel Processor (submodule of GPU) block level reset - PSU_CRF_APB_RST_FPD_TOP_GPU_PP0_RESET 0 + * Master Tri-state Enable for pin 23, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI 0 - Pixel Processor (submodule of GPU) block level reset - PSU_CRF_APB_RST_FPD_TOP_GPU_PP1_RESET 0 + * Master Tri-state Enable for pin 24, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI 0 - GPU block level reset - PSU_CRF_APB_RST_FPD_TOP_GPU_RESET 0 + * Master Tri-state Enable for pin 25, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI 1 - GT block level reset - PSU_CRF_APB_RST_FPD_TOP_GT_RESET 0 + * Master Tri-state Enable for pin 26, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI 0 - Sata block level reset - PSU_CRF_APB_RST_FPD_TOP_SATA_RESET 0 + * Master Tri-state Enable for pin 27, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI 0 - FPD Block level software controlled reset - (OFFSET, MASK, VALUE) (0XFD1A0100, 0x000F807EU ,0x00000000U) - RegMask = (CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK | CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK | CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK | CRF_APB_RST_FPD_TOP_DP_RESET_MASK | CRF_APB_RST_FPD_TOP_SWDT_RESET_MASK | CRF_APB_RST_FPD_TOP_GDMA_RESET_MASK | CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_MASK | CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_MASK | CRF_APB_RST_FPD_TOP_GPU_RESET_MASK | CRF_APB_RST_FPD_TOP_GT_RESET_MASK | CRF_APB_RST_FPD_TOP_SATA_RESET_MASK | 0 ); + * Master Tri-state Enable for pin 28, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI 1 - RegVal = ((0x00000000U << CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT - | 0x00000000U << CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT - | 0x00000000U << CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT - | 0x00000000U << CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT - | 0x00000000U << CRF_APB_RST_FPD_TOP_SWDT_RESET_SHIFT - | 0x00000000U << CRF_APB_RST_FPD_TOP_GDMA_RESET_SHIFT - | 0x00000000U << CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_SHIFT - | 0x00000000U << CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_SHIFT - | 0x00000000U << CRF_APB_RST_FPD_TOP_GPU_RESET_SHIFT - | 0x00000000U << CRF_APB_RST_FPD_TOP_GT_RESET_SHIFT - | 0x00000000U << CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_RST_FPD_TOP_OFFSET ,0x000F807EU ,0x00000000U); - /*############################################################################################################################ */ + * Master Tri-state Enable for pin 29, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI 0 - // : SD - /*Register : RST_LPD_IOU2 @ 0XFF5E0238

+ * Master Tri-state Enable for pin 30, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI 1 - Block level reset - PSU_CRL_APB_RST_LPD_IOU2_SDIO1_RESET 0 + * Master Tri-state Enable for pin 31, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI 0 - Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset. - (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000040U ,0x00000000U) - RegMask = (CRL_APB_RST_LPD_IOU2_SDIO1_RESET_MASK | 0 ); + * MIO pin Tri-state Enables, 31:0 + * (OFFSET, MASK, VALUE) (0XFF180204, 0xFFFFFFFFU ,0x52240000U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_MST_TRI0_OFFSET, + 0xFFFFFFFFU, 0x52240000U); +/*##################################################################### */ - RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU2_SDIO1_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RST_LPD_IOU2_OFFSET ,0x00000040U ,0x00000000U); - /*############################################################################################################################ */ + /* + * Register : MIO_MST_TRI1 @ 0XFF180208 - /*Register : CTRL_REG_SD @ 0XFF180310

+ * Master Tri-state Enable for pin 32, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI 0 - SD or eMMC selection on SDIO1 0: SD enabled 1: eMMC enabled - PSU_IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL 0 + * Master Tri-state Enable for pin 33, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI 0 - SD eMMC selection - (OFFSET, MASK, VALUE) (0XFF180310, 0x00008000U ,0x00000000U) - RegMask = (IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_MASK | 0 ); + * Master Tri-state Enable for pin 34, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI 0 - RegVal = ((0x00000000U << IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_CTRL_REG_SD_OFFSET ,0x00008000U ,0x00000000U); - /*############################################################################################################################ */ + * Master Tri-state Enable for pin 35, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI 0 - /*Register : SD_CONFIG_REG2 @ 0XFF180320

+ * Master Tri-state Enable for pin 36, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI 0 - Should be set based on the final product usage 00 - Removable SCard Slot 01 - Embedded Slot for One Device 10 - Shared Bus Sl - t 11 - Reserved - PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE 0 + * Master Tri-state Enable for pin 37, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI 0 - 1.8V Support 1: 1.8V supported 0: 1.8V not supported support - PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V 0 + * Master Tri-state Enable for pin 38, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI 0 - 3.0V Support 1: 3.0V supported 0: 3.0V not supported support - PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V 0 + * Master Tri-state Enable for pin 39, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI 0 - 3.3V Support 1: 3.3V supported 0: 3.3V not supported support - PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V 1 + * Master Tri-state Enable for pin 40, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI 0 - SD Config Register 2 - (OFFSET, MASK, VALUE) (0XFF180320, 0x33800000U ,0x00800000U) - RegMask = (IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_MASK | IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_MASK | IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_MASK | IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_MASK | 0 ); + * Master Tri-state Enable for pin 41, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI 0 - RegVal = ((0x00000000U << IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_SHIFT - | 0x00000000U << IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_SHIFT - | 0x00000000U << IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_SHIFT - | 0x00000001U << IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_SD_CONFIG_REG2_OFFSET ,0x33800000U ,0x00800000U); - /*############################################################################################################################ */ + * Master Tri-state Enable for pin 42, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI 0 - // : SD1 BASE CLOCK - /*Register : SD_CONFIG_REG1 @ 0XFF18031C

+ * Master Tri-state Enable for pin 43, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI 0 - Base Clock Frequency for SD Clock. This is the frequency of the xin_clk. - PSU_IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK 0xc7 + * Master Tri-state Enable for pin 44, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI 1 - SD Config Register 1 - (OFFSET, MASK, VALUE) (0XFF18031C, 0x7F800000U ,0x63800000U) - RegMask = (IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_MASK | 0 ); + * Master Tri-state Enable for pin 45, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI 1 - RegVal = ((0x000000C7U << IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_SD_CONFIG_REG1_OFFSET ,0x7F800000U ,0x63800000U); - /*############################################################################################################################ */ + * Master Tri-state Enable for pin 46, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI 0 - // : SD1 RETUNER - /*Register : SD_CONFIG_REG3 @ 0XFF180324

+ * Master Tri-state Enable for pin 47, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI 0 - This is the Timer Count for Re-Tuning Timer for Re-Tuning Mode 1 to 3. Setting to 4'b0 disables Re-Tuning Timer. 0h - Get inf - rmation via other source 1h = 1 seconds 2h = 2 seconds 3h = 4 seconds 4h = 8 seconds -- n = 2(n-1) seconds -- Bh = 1024 secon - s Fh - Ch = Reserved - PSU_IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR 0X0 + * Master Tri-state Enable for pin 48, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI 0 - SD Config Register 3 - (OFFSET, MASK, VALUE) (0XFF180324, 0x03C00000U ,0x00000000U) - RegMask = (IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_SD_CONFIG_REG3_OFFSET ,0x03C00000U ,0x00000000U); - /*############################################################################################################################ */ + * Master Tri-state Enable for pin 49, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI 0 - // : CAN - /*Register : RST_LPD_IOU2 @ 0XFF5E0238

+ * Master Tri-state Enable for pin 50, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI 0 - Block level reset - PSU_CRL_APB_RST_LPD_IOU2_CAN1_RESET 0 + * Master Tri-state Enable for pin 51, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI 0 - Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset. - (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000100U ,0x00000000U) - RegMask = (CRL_APB_RST_LPD_IOU2_CAN1_RESET_MASK | 0 ); + * Master Tri-state Enable for pin 52, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI 1 - RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU2_CAN1_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RST_LPD_IOU2_OFFSET ,0x00000100U ,0x00000000U); - /*############################################################################################################################ */ + * Master Tri-state Enable for pin 53, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI 1 - // : I2C - /*Register : RST_LPD_IOU2 @ 0XFF5E0238

+ * Master Tri-state Enable for pin 54, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI 0 - Block level reset - PSU_CRL_APB_RST_LPD_IOU2_I2C0_RESET 0 + * Master Tri-state Enable for pin 55, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI 1 - Block level reset - PSU_CRL_APB_RST_LPD_IOU2_I2C1_RESET 0 + * Master Tri-state Enable for pin 56, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI 0 - Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset. - (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000600U ,0x00000000U) - RegMask = (CRL_APB_RST_LPD_IOU2_I2C0_RESET_MASK | CRL_APB_RST_LPD_IOU2_I2C1_RESET_MASK | 0 ); + * Master Tri-state Enable for pin 57, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI 0 - RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU2_I2C0_RESET_SHIFT - | 0x00000000U << CRL_APB_RST_LPD_IOU2_I2C1_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RST_LPD_IOU2_OFFSET ,0x00000600U ,0x00000000U); - /*############################################################################################################################ */ + * Master Tri-state Enable for pin 58, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI 0 - // : SWDT - /*Register : RST_LPD_IOU2 @ 0XFF5E0238

+ * Master Tri-state Enable for pin 59, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI 0 - Block level reset - PSU_CRL_APB_RST_LPD_IOU2_SWDT_RESET 0 + * Master Tri-state Enable for pin 60, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI 0 - Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset. - (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00008000U ,0x00000000U) - RegMask = (CRL_APB_RST_LPD_IOU2_SWDT_RESET_MASK | 0 ); + * Master Tri-state Enable for pin 61, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI 0 - RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU2_SWDT_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RST_LPD_IOU2_OFFSET ,0x00008000U ,0x00000000U); - /*############################################################################################################################ */ + * Master Tri-state Enable for pin 62, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI 0 - // : SPI - // : TTC - /*Register : RST_LPD_IOU2 @ 0XFF5E0238

+ * Master Tri-state Enable for pin 63, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI 0 - Block level reset - PSU_CRL_APB_RST_LPD_IOU2_TTC0_RESET 0 + * MIO pin Tri-state Enables, 63:32 + * (OFFSET, MASK, VALUE) (0XFF180208, 0xFFFFFFFFU ,0x00B03000U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_MST_TRI1_OFFSET, + 0xFFFFFFFFU, 0x00B03000U); +/*##################################################################### */ - Block level reset - PSU_CRL_APB_RST_LPD_IOU2_TTC1_RESET 0 + /* + * Register : MIO_MST_TRI2 @ 0XFF18020C - Block level reset - PSU_CRL_APB_RST_LPD_IOU2_TTC2_RESET 0 + * Master Tri-state Enable for pin 64, active high + * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI 0 - Block level reset - PSU_CRL_APB_RST_LPD_IOU2_TTC3_RESET 0 + * Master Tri-state Enable for pin 65, active high + * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI 0 - Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset. - (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00007800U ,0x00000000U) - RegMask = (CRL_APB_RST_LPD_IOU2_TTC0_RESET_MASK | CRL_APB_RST_LPD_IOU2_TTC1_RESET_MASK | CRL_APB_RST_LPD_IOU2_TTC2_RESET_MASK | CRL_APB_RST_LPD_IOU2_TTC3_RESET_MASK | 0 ); + * Master Tri-state Enable for pin 66, active high + * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI 0 - RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU2_TTC0_RESET_SHIFT - | 0x00000000U << CRL_APB_RST_LPD_IOU2_TTC1_RESET_SHIFT - | 0x00000000U << CRL_APB_RST_LPD_IOU2_TTC2_RESET_SHIFT - | 0x00000000U << CRL_APB_RST_LPD_IOU2_TTC3_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RST_LPD_IOU2_OFFSET ,0x00007800U ,0x00000000U); - /*############################################################################################################################ */ + * Master Tri-state Enable for pin 67, active high + * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI 0 - // : UART - /*Register : RST_LPD_IOU2 @ 0XFF5E0238

+ * Master Tri-state Enable for pin 68, active high + * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI 0 - Block level reset - PSU_CRL_APB_RST_LPD_IOU2_UART0_RESET 0 + * Master Tri-state Enable for pin 69, active high + * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI 0 - Block level reset - PSU_CRL_APB_RST_LPD_IOU2_UART1_RESET 0 + * Master Tri-state Enable for pin 70, active high + * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI 1 - Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset. - (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000006U ,0x00000000U) - RegMask = (CRL_APB_RST_LPD_IOU2_UART0_RESET_MASK | CRL_APB_RST_LPD_IOU2_UART1_RESET_MASK | 0 ); + * Master Tri-state Enable for pin 71, active high + * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI 1 - RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU2_UART0_RESET_SHIFT - | 0x00000000U << CRL_APB_RST_LPD_IOU2_UART1_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RST_LPD_IOU2_OFFSET ,0x00000006U ,0x00000000U); - /*############################################################################################################################ */ + * Master Tri-state Enable for pin 72, active high + * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI 1 - // : UART BAUD RATE - /*Register : Baud_rate_divider_reg0 @ 0XFF000034

+ * Master Tri-state Enable for pin 73, active high + * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI 1 - Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate - PSU_UART0_BAUD_RATE_DIVIDER_REG0_BDIV 0x5 + * Master Tri-state Enable for pin 74, active high + * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI 1 - Baud Rate Divider Register - (OFFSET, MASK, VALUE) (0XFF000034, 0x000000FFU ,0x00000005U) - RegMask = (UART0_BAUD_RATE_DIVIDER_REG0_BDIV_MASK | 0 ); + * Master Tri-state Enable for pin 75, active high + * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI 1 - RegVal = ((0x00000005U << UART0_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (UART0_BAUD_RATE_DIVIDER_REG0_OFFSET ,0x000000FFU ,0x00000005U); - /*############################################################################################################################ */ + * Master Tri-state Enable for pin 76, active high + * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI 0 - /*Register : Baud_rate_gen_reg0 @ 0XFF000018

+ * Master Tri-state Enable for pin 77, active high + * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI 0 - Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample - PSU_UART0_BAUD_RATE_GEN_REG0_CD 0x8f + * MIO pin Tri-state Enables, 77:64 + * (OFFSET, MASK, VALUE) (0XFF18020C, 0x00003FFFU ,0x00000FC0U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_MST_TRI2_OFFSET, + 0x00003FFFU, 0x00000FC0U); +/*##################################################################### */ - Baud Rate Generator Register. - (OFFSET, MASK, VALUE) (0XFF000018, 0x0000FFFFU ,0x0000008FU) - RegMask = (UART0_BAUD_RATE_GEN_REG0_CD_MASK | 0 ); + /* + * Register : bank0_ctrl0 @ 0XFF180138 - RegVal = ((0x0000008FU << UART0_BAUD_RATE_GEN_REG0_CD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (UART0_BAUD_RATE_GEN_REG0_OFFSET ,0x0000FFFFU ,0x0000008FU); - /*############################################################################################################################ */ + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0 1 - /*Register : Control_reg0 @ 0XFF000000

+ * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1 1 - Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a - high level during 12 bit periods. It can be set regardless of the value of STTBRK. - PSU_UART0_CONTROL_REG0_STPBRK 0x0 + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2 1 - Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the - transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high. - PSU_UART0_CONTROL_REG0_STTBRK 0x0 + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3 1 - Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has co - pleted. - PSU_UART0_CONTROL_REG0_RSTTO 0x0 + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4 1 - Transmit disable: 0: enable transmitter 1: disable transmitter - PSU_UART0_CONTROL_REG0_TXDIS 0x0 + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5 1 - Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0. - PSU_UART0_CONTROL_REG0_TXEN 0x1 + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6 1 - Receive disable: 0: enable 1: disable, regardless of the value of RXEN - PSU_UART0_CONTROL_REG0_RXDIS 0x0 + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7 1 - Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero. - PSU_UART0_CONTROL_REG0_RXEN 0x1 + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8 1 - Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded Thi - bit is self clearing once the reset has completed. - PSU_UART0_CONTROL_REG0_TXRES 0x1 + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9 1 - Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit - is self clearing once the reset has completed. - PSU_UART0_CONTROL_REG0_RXRES 0x1 + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10 1 - UART Control Register - (OFFSET, MASK, VALUE) (0XFF000000, 0x000001FFU ,0x00000017U) - RegMask = (UART0_CONTROL_REG0_STPBRK_MASK | UART0_CONTROL_REG0_STTBRK_MASK | UART0_CONTROL_REG0_RSTTO_MASK | UART0_CONTROL_REG0_TXDIS_MASK | UART0_CONTROL_REG0_TXEN_MASK | UART0_CONTROL_REG0_RXDIS_MASK | UART0_CONTROL_REG0_RXEN_MASK | UART0_CONTROL_REG0_TXRES_MASK | UART0_CONTROL_REG0_RXRES_MASK | 0 ); + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11 1 - RegVal = ((0x00000000U << UART0_CONTROL_REG0_STPBRK_SHIFT - | 0x00000000U << UART0_CONTROL_REG0_STTBRK_SHIFT - | 0x00000000U << UART0_CONTROL_REG0_RSTTO_SHIFT - | 0x00000000U << UART0_CONTROL_REG0_TXDIS_SHIFT - | 0x00000001U << UART0_CONTROL_REG0_TXEN_SHIFT - | 0x00000000U << UART0_CONTROL_REG0_RXDIS_SHIFT - | 0x00000001U << UART0_CONTROL_REG0_RXEN_SHIFT - | 0x00000001U << UART0_CONTROL_REG0_TXRES_SHIFT - | 0x00000001U << UART0_CONTROL_REG0_RXRES_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (UART0_CONTROL_REG0_OFFSET ,0x000001FFU ,0x00000017U); - /*############################################################################################################################ */ + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12 1 - /*Register : mode_reg0 @ 0XFF000004

+ * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13 1 - Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback - PSU_UART0_MODE_REG0_CHMODE 0x0 + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14 1 - Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5 - stop bits 10: 2 stop bits 11: reserved - PSU_UART0_MODE_REG0_NBSTOP 0x0 + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15 1 - Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity - 01: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity - PSU_UART0_MODE_REG0_PAR 0x4 + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16 1 - Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits - PSU_UART0_MODE_REG0_CHRL 0x0 + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17 1 - Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock - source is uart_ref_clk 1: clock source is uart_ref_clk/8 - PSU_UART0_MODE_REG0_CLKS 0x0 + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18 1 - UART Mode Register - (OFFSET, MASK, VALUE) (0XFF000004, 0x000003FFU ,0x00000020U) - RegMask = (UART0_MODE_REG0_CHMODE_MASK | UART0_MODE_REG0_NBSTOP_MASK | UART0_MODE_REG0_PAR_MASK | UART0_MODE_REG0_CHRL_MASK | UART0_MODE_REG0_CLKS_MASK | 0 ); + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19 1 - RegVal = ((0x00000000U << UART0_MODE_REG0_CHMODE_SHIFT - | 0x00000000U << UART0_MODE_REG0_NBSTOP_SHIFT - | 0x00000004U << UART0_MODE_REG0_PAR_SHIFT - | 0x00000000U << UART0_MODE_REG0_CHRL_SHIFT - | 0x00000000U << UART0_MODE_REG0_CLKS_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (UART0_MODE_REG0_OFFSET ,0x000003FFU ,0x00000020U); - /*############################################################################################################################ */ + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20 1 - /*Register : Baud_rate_divider_reg0 @ 0XFF010034

+ * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21 1 - Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate - PSU_UART1_BAUD_RATE_DIVIDER_REG0_BDIV 0x5 + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22 1 - Baud Rate Divider Register - (OFFSET, MASK, VALUE) (0XFF010034, 0x000000FFU ,0x00000005U) - RegMask = (UART1_BAUD_RATE_DIVIDER_REG0_BDIV_MASK | 0 ); - - RegVal = ((0x00000005U << UART1_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (UART1_BAUD_RATE_DIVIDER_REG0_OFFSET ,0x000000FFU ,0x00000005U); - /*############################################################################################################################ */ - - /*Register : Baud_rate_gen_reg0 @ 0XFF010018

+ * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23 1 - Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample - PSU_UART1_BAUD_RATE_GEN_REG0_CD 0x8f - - Baud Rate Generator Register. - (OFFSET, MASK, VALUE) (0XFF010018, 0x0000FFFFU ,0x0000008FU) - RegMask = (UART1_BAUD_RATE_GEN_REG0_CD_MASK | 0 ); - - RegVal = ((0x0000008FU << UART1_BAUD_RATE_GEN_REG0_CD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (UART1_BAUD_RATE_GEN_REG0_OFFSET ,0x0000FFFFU ,0x0000008FU); - /*############################################################################################################################ */ - - /*Register : Control_reg0 @ 0XFF010000

- - Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a - high level during 12 bit periods. It can be set regardless of the value of STTBRK. - PSU_UART1_CONTROL_REG0_STPBRK 0x0 - - Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the - transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high. - PSU_UART1_CONTROL_REG0_STTBRK 0x0 - - Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has co - pleted. - PSU_UART1_CONTROL_REG0_RSTTO 0x0 - - Transmit disable: 0: enable transmitter 1: disable transmitter - PSU_UART1_CONTROL_REG0_TXDIS 0x0 - - Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0. - PSU_UART1_CONTROL_REG0_TXEN 0x1 - - Receive disable: 0: enable 1: disable, regardless of the value of RXEN - PSU_UART1_CONTROL_REG0_RXDIS 0x0 - - Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero. - PSU_UART1_CONTROL_REG0_RXEN 0x1 + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24 1 - Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded Thi - bit is self clearing once the reset has completed. - PSU_UART1_CONTROL_REG0_TXRES 0x1 + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25 1 - Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit - is self clearing once the reset has completed. - PSU_UART1_CONTROL_REG0_RXRES 0x1 + * Drive0 control to MIO Bank 0 - control MIO[25:0] + * (OFFSET, MASK, VALUE) (0XFF180138, 0x03FFFFFFU ,0x03FFFFFFU) + */ + PSU_Mask_Write(IOU_SLCR_BANK0_CTRL0_OFFSET, + 0x03FFFFFFU, 0x03FFFFFFU); +/*##################################################################### */ - UART Control Register - (OFFSET, MASK, VALUE) (0XFF010000, 0x000001FFU ,0x00000017U) - RegMask = (UART1_CONTROL_REG0_STPBRK_MASK | UART1_CONTROL_REG0_STTBRK_MASK | UART1_CONTROL_REG0_RSTTO_MASK | UART1_CONTROL_REG0_TXDIS_MASK | UART1_CONTROL_REG0_TXEN_MASK | UART1_CONTROL_REG0_RXDIS_MASK | UART1_CONTROL_REG0_RXEN_MASK | UART1_CONTROL_REG0_TXRES_MASK | UART1_CONTROL_REG0_RXRES_MASK | 0 ); + /* + * Register : bank0_ctrl1 @ 0XFF18013C - RegVal = ((0x00000000U << UART1_CONTROL_REG0_STPBRK_SHIFT - | 0x00000000U << UART1_CONTROL_REG0_STTBRK_SHIFT - | 0x00000000U << UART1_CONTROL_REG0_RSTTO_SHIFT - | 0x00000000U << UART1_CONTROL_REG0_TXDIS_SHIFT - | 0x00000001U << UART1_CONTROL_REG0_TXEN_SHIFT - | 0x00000000U << UART1_CONTROL_REG0_RXDIS_SHIFT - | 0x00000001U << UART1_CONTROL_REG0_RXEN_SHIFT - | 0x00000001U << UART1_CONTROL_REG0_TXRES_SHIFT - | 0x00000001U << UART1_CONTROL_REG0_RXRES_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (UART1_CONTROL_REG0_OFFSET ,0x000001FFU ,0x00000017U); - /*############################################################################################################################ */ + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0 1 - /*Register : mode_reg0 @ 0XFF010004

+ * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1 1 - Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback - PSU_UART1_MODE_REG0_CHMODE 0x0 + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2 1 - Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5 - stop bits 10: 2 stop bits 11: reserved - PSU_UART1_MODE_REG0_NBSTOP 0x0 - - Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity - 01: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity - PSU_UART1_MODE_REG0_PAR 0x4 - - Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits - PSU_UART1_MODE_REG0_CHRL 0x0 - - Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock - source is uart_ref_clk 1: clock source is uart_ref_clk/8 - PSU_UART1_MODE_REG0_CLKS 0x0 + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3 1 - UART Mode Register - (OFFSET, MASK, VALUE) (0XFF010004, 0x000003FFU ,0x00000020U) - RegMask = (UART1_MODE_REG0_CHMODE_MASK | UART1_MODE_REG0_NBSTOP_MASK | UART1_MODE_REG0_PAR_MASK | UART1_MODE_REG0_CHRL_MASK | UART1_MODE_REG0_CLKS_MASK | 0 ); + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4 1 - RegVal = ((0x00000000U << UART1_MODE_REG0_CHMODE_SHIFT - | 0x00000000U << UART1_MODE_REG0_NBSTOP_SHIFT - | 0x00000004U << UART1_MODE_REG0_PAR_SHIFT - | 0x00000000U << UART1_MODE_REG0_CHRL_SHIFT - | 0x00000000U << UART1_MODE_REG0_CLKS_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (UART1_MODE_REG0_OFFSET ,0x000003FFU ,0x00000020U); - /*############################################################################################################################ */ - - // : GPIO - // : ADMA TZ - /*Register : slcr_adma @ 0XFF4B0024

+ * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5 1 - TrustZone Classification for ADMA - PSU_LPD_SLCR_SECURE_SLCR_ADMA_TZ 0XFF - - RPU TrustZone settings - (OFFSET, MASK, VALUE) (0XFF4B0024, 0x000000FFU ,0x000000FFU) - RegMask = (LPD_SLCR_SECURE_SLCR_ADMA_TZ_MASK | 0 ); - - RegVal = ((0x000000FFU << LPD_SLCR_SECURE_SLCR_ADMA_TZ_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (LPD_SLCR_SECURE_SLCR_ADMA_OFFSET ,0x000000FFU ,0x000000FFU); - /*############################################################################################################################ */ - - // : CSU TAMPERING - // : CSU TAMPER STATUS - /*Register : tamper_status @ 0XFFCA5000

- - CSU regsiter - PSU_CSU_TAMPER_STATUS_TAMPER_0 0 - - External MIO - PSU_CSU_TAMPER_STATUS_TAMPER_1 0 - - JTAG toggle detect - PSU_CSU_TAMPER_STATUS_TAMPER_2 0 - - PL SEU error - PSU_CSU_TAMPER_STATUS_TAMPER_3 0 - - AMS over temperature alarm for LPD - PSU_CSU_TAMPER_STATUS_TAMPER_4 0 - - AMS over temperature alarm for APU - PSU_CSU_TAMPER_STATUS_TAMPER_5 0 - - AMS voltage alarm for VCCPINT_FPD - PSU_CSU_TAMPER_STATUS_TAMPER_6 0 - - AMS voltage alarm for VCCPINT_LPD - PSU_CSU_TAMPER_STATUS_TAMPER_7 0 - - AMS voltage alarm for VCCPAUX - PSU_CSU_TAMPER_STATUS_TAMPER_8 0 - - AMS voltage alarm for DDRPHY - PSU_CSU_TAMPER_STATUS_TAMPER_9 0 - - AMS voltage alarm for PSIO bank 0/1/2 - PSU_CSU_TAMPER_STATUS_TAMPER_10 0 - - AMS voltage alarm for PSIO bank 3 (dedicated pins) - PSU_CSU_TAMPER_STATUS_TAMPER_11 0 - - AMS voltaage alarm for GT - PSU_CSU_TAMPER_STATUS_TAMPER_12 0 - - Tamper Response Status - (OFFSET, MASK, VALUE) (0XFFCA5000, 0x00001FFFU ,0x00000000U) - RegMask = (CSU_TAMPER_STATUS_TAMPER_0_MASK | CSU_TAMPER_STATUS_TAMPER_1_MASK | CSU_TAMPER_STATUS_TAMPER_2_MASK | CSU_TAMPER_STATUS_TAMPER_3_MASK | CSU_TAMPER_STATUS_TAMPER_4_MASK | CSU_TAMPER_STATUS_TAMPER_5_MASK | CSU_TAMPER_STATUS_TAMPER_6_MASK | CSU_TAMPER_STATUS_TAMPER_7_MASK | CSU_TAMPER_STATUS_TAMPER_8_MASK | CSU_TAMPER_STATUS_TAMPER_9_MASK | CSU_TAMPER_STATUS_TAMPER_10_MASK | CSU_TAMPER_STATUS_TAMPER_11_MASK | CSU_TAMPER_STATUS_TAMPER_12_MASK | 0 ); + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6 1 - RegVal = ((0x00000000U << CSU_TAMPER_STATUS_TAMPER_0_SHIFT - | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_1_SHIFT - | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_2_SHIFT - | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_3_SHIFT - | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_4_SHIFT - | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_5_SHIFT - | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_6_SHIFT - | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_7_SHIFT - | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_8_SHIFT - | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_9_SHIFT - | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_10_SHIFT - | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_11_SHIFT - | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_12_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CSU_TAMPER_STATUS_OFFSET ,0x00001FFFU ,0x00000000U); - /*############################################################################################################################ */ + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7 1 - // : CSU TAMPER RESPONSE - // : AFIFM INTERFACE WIDTH - // : CPU QOS DEFAULT - /*Register : ACE_CTRL @ 0XFD5C0060

- - Set ACE outgoing AWQOS value - PSU_APU_ACE_CTRL_AWQOS 0X0 - - Set ACE outgoing ARQOS value - PSU_APU_ACE_CTRL_ARQOS 0X0 + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8 1 - ACE Control Register - (OFFSET, MASK, VALUE) (0XFD5C0060, 0x000F000FU ,0x00000000U) - RegMask = (APU_ACE_CTRL_AWQOS_MASK | APU_ACE_CTRL_ARQOS_MASK | 0 ); + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9 1 - RegVal = ((0x00000000U << APU_ACE_CTRL_AWQOS_SHIFT - | 0x00000000U << APU_ACE_CTRL_ARQOS_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (APU_ACE_CTRL_OFFSET ,0x000F000FU ,0x00000000U); - /*############################################################################################################################ */ + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10 1 - // : ENABLES RTC SWITCH TO BATTERY WHEN VCC_PSAUX IS NOT AVAILABLE - /*Register : CONTROL @ 0XFFA60040

+ * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11 1 - Enables the RTC. By writing a 0 to this bit, RTC will be powered off and the only module that potentially draws current from - he battery will be BBRAM. The value read through this bit does not necessarily reflect whether RTC is enabled or not. It is e - pected that RTC is enabled every time it is being configured. If RTC is not used in the design, FSBL will disable it by writi - g a 0 to this bit. - PSU_RTC_CONTROL_BATTERY_DISABLE 0X1 + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12 1 - This register controls various functionalities within the RTC - (OFFSET, MASK, VALUE) (0XFFA60040, 0x80000000U ,0x80000000U) - RegMask = (RTC_CONTROL_BATTERY_DISABLE_MASK | 0 ); + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13 1 - RegVal = ((0x00000001U << RTC_CONTROL_BATTERY_DISABLE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (RTC_CONTROL_OFFSET ,0x80000000U ,0x80000000U); - /*############################################################################################################################ */ + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14 1 - // : TIMESTAMP COUNTER - /*Register : base_frequency_ID_register @ 0XFF260020

+ * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15 1 - Frequency in number of ticks per second. Valid range from 10 MHz to 100 MHz. - PSU_IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ 0x5f5e100 + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16 1 - Program this register to match the clock frequency of the timestamp generator, in ticks per second. For example, for a 50 MHz - clock, program 0x02FAF080. This register is not accessible to the read-only programming interface. - (OFFSET, MASK, VALUE) (0XFF260020, 0xFFFFFFFFU ,0x05F5E100U) - RegMask = (IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_MASK | 0 ); + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17 1 - RegVal = ((0x05F5E100U << IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_OFFSET ,0xFFFFFFFFU ,0x05F5E100U); - /*############################################################################################################################ */ + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18 1 - /*Register : counter_control_register @ 0XFF260000

- - Enable 0: The counter is disabled and not incrementing. 1: The counter is enabled and is incrementing. - PSU_IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN 0x1 - - Controls the counter increments. This register is not accessible to the read-only programming interface. - (OFFSET, MASK, VALUE) (0XFF260000, 0x00000001U ,0x00000001U) - RegMask = (IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SCNTRS_COUNTER_CONTROL_REGISTER_OFFSET ,0x00000001U ,0x00000001U); - /*############################################################################################################################ */ - - // : TTC SRC SELECT - - return 1; + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25 1 + + * Drive1 control to MIO Bank 0 - control MIO[25:0] + * (OFFSET, MASK, VALUE) (0XFF18013C, 0x03FFFFFFU ,0x03FFFFFFU) + */ + PSU_Mask_Write(IOU_SLCR_BANK0_CTRL1_OFFSET, + 0x03FFFFFFU, 0x03FFFFFFU); +/*##################################################################### */ + + /* + * Register : bank0_ctrl3 @ 0XFF180140 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25 0 + + * Selects either Schmitt or CMOS input for MIO Bank 0 - control MIO[25:0] + * (OFFSET, MASK, VALUE) (0XFF180140, 0x03FFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_BANK0_CTRL3_OFFSET, + 0x03FFFFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : bank0_ctrl4 @ 0XFF180144 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25 1 + + * When mio_bank0_pull_enable is set, this selects pull up or pull down for + * MIO Bank 0 - control MIO[25:0] + * (OFFSET, MASK, VALUE) (0XFF180144, 0x03FFFFFFU ,0x03FFFFFFU) + */ + PSU_Mask_Write(IOU_SLCR_BANK0_CTRL4_OFFSET, + 0x03FFFFFFU, 0x03FFFFFFU); +/*##################################################################### */ + + /* + * Register : bank0_ctrl5 @ 0XFF180148 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25 1 + + * When set, this enables mio_bank0_pullupdown to selects pull up or pull d + * own for MIO Bank 0 - control MIO[25:0] + * (OFFSET, MASK, VALUE) (0XFF180148, 0x03FFFFFFU ,0x03FFFFFFU) + */ + PSU_Mask_Write(IOU_SLCR_BANK0_CTRL5_OFFSET, + 0x03FFFFFFU, 0x03FFFFFFU); +/*##################################################################### */ + + /* + * Register : bank0_ctrl6 @ 0XFF18014C + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25 0 + + * Slew rate control to MIO Bank 0 - control MIO[25:0] + * (OFFSET, MASK, VALUE) (0XFF18014C, 0x03FFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_BANK0_CTRL6_OFFSET, + 0x03FFFFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : bank1_ctrl0 @ 0XFF180154 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25 1 + + * Drive0 control to MIO Bank 1 - control MIO[51:26] + * (OFFSET, MASK, VALUE) (0XFF180154, 0x03FFFFFFU ,0x03FFFFFFU) + */ + PSU_Mask_Write(IOU_SLCR_BANK1_CTRL0_OFFSET, + 0x03FFFFFFU, 0x03FFFFFFU); +/*##################################################################### */ + + /* + * Register : bank1_ctrl1 @ 0XFF180158 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25 1 + + * Drive1 control to MIO Bank 1 - control MIO[51:26] + * (OFFSET, MASK, VALUE) (0XFF180158, 0x03FFFFFFU ,0x03FFFFFFU) + */ + PSU_Mask_Write(IOU_SLCR_BANK1_CTRL1_OFFSET, + 0x03FFFFFFU, 0x03FFFFFFU); +/*##################################################################### */ + + /* + * Register : bank1_ctrl3 @ 0XFF18015C + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25 0 + + * Selects either Schmitt or CMOS input for MIO Bank 1 - control MIO[51:26] + * (OFFSET, MASK, VALUE) (0XFF18015C, 0x03FFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_BANK1_CTRL3_OFFSET, + 0x03FFFFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : bank1_ctrl4 @ 0XFF180160 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25 1 + + * When mio_bank1_pull_enable is set, this selects pull up or pull down for + * MIO Bank 1 - control MIO[51:26] + * (OFFSET, MASK, VALUE) (0XFF180160, 0x03FFFFFFU ,0x03FFFFFFU) + */ + PSU_Mask_Write(IOU_SLCR_BANK1_CTRL4_OFFSET, + 0x03FFFFFFU, 0x03FFFFFFU); +/*##################################################################### */ + + /* + * Register : bank1_ctrl5 @ 0XFF180164 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25 1 + + * When set, this enables mio_bank1_pullupdown to selects pull up or pull d + * own for MIO Bank 1 - control MIO[51:26] + * (OFFSET, MASK, VALUE) (0XFF180164, 0x03FFFFFFU ,0x03FFFFFFU) + */ + PSU_Mask_Write(IOU_SLCR_BANK1_CTRL5_OFFSET, + 0x03FFFFFFU, 0x03FFFFFFU); +/*##################################################################### */ + + /* + * Register : bank1_ctrl6 @ 0XFF180168 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25 0 + + * Slew rate control to MIO Bank 1 - control MIO[51:26] + * (OFFSET, MASK, VALUE) (0XFF180168, 0x03FFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_BANK1_CTRL6_OFFSET, + 0x03FFFFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : bank2_ctrl0 @ 0XFF180170 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25 1 + + * Drive0 control to MIO Bank 2 - control MIO[77:52] + * (OFFSET, MASK, VALUE) (0XFF180170, 0x03FFFFFFU ,0x03FFFFFFU) + */ + PSU_Mask_Write(IOU_SLCR_BANK2_CTRL0_OFFSET, + 0x03FFFFFFU, 0x03FFFFFFU); +/*##################################################################### */ + + /* + * Register : bank2_ctrl1 @ 0XFF180174 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25 1 + + * Drive1 control to MIO Bank 2 - control MIO[77:52] + * (OFFSET, MASK, VALUE) (0XFF180174, 0x03FFFFFFU ,0x03FFFFFFU) + */ + PSU_Mask_Write(IOU_SLCR_BANK2_CTRL1_OFFSET, + 0x03FFFFFFU, 0x03FFFFFFU); +/*##################################################################### */ + + /* + * Register : bank2_ctrl3 @ 0XFF180178 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25 0 + + * Selects either Schmitt or CMOS input for MIO Bank 2 - control MIO[77:52] + * (OFFSET, MASK, VALUE) (0XFF180178, 0x03FFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_BANK2_CTRL3_OFFSET, + 0x03FFFFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : bank2_ctrl4 @ 0XFF18017C + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25 1 + + * When mio_bank2_pull_enable is set, this selects pull up or pull down for + * MIO Bank 2 - control MIO[77:52] + * (OFFSET, MASK, VALUE) (0XFF18017C, 0x03FFFFFFU ,0x03FFFFFFU) + */ + PSU_Mask_Write(IOU_SLCR_BANK2_CTRL4_OFFSET, + 0x03FFFFFFU, 0x03FFFFFFU); +/*##################################################################### */ + + /* + * Register : bank2_ctrl5 @ 0XFF180180 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25 1 + + * When set, this enables mio_bank2_pullupdown to selects pull up or pull d + * own for MIO Bank 2 - control MIO[77:52] + * (OFFSET, MASK, VALUE) (0XFF180180, 0x03FFFFFFU ,0x03FFFFFFU) + */ + PSU_Mask_Write(IOU_SLCR_BANK2_CTRL5_OFFSET, + 0x03FFFFFFU, 0x03FFFFFFU); +/*##################################################################### */ + + /* + * Register : bank2_ctrl6 @ 0XFF180184 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25 0 + + * Slew rate control to MIO Bank 2 - control MIO[77:52] + * (OFFSET, MASK, VALUE) (0XFF180184, 0x03FFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_BANK2_CTRL6_OFFSET, + 0x03FFFFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * LOOPBACK + */ + /* + * Register : MIO_LOOPBACK @ 0XFF180200 + + * I2C Loopback Control. 0 = Connect I2C inputs according to MIO mapping. 1 + * = Loop I2C 0 outputs to I2C 1 inputs, and I2C 1 outputs to I2C 0 inputs + * . + * PSU_IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1 0 + + * CAN Loopback Control. 0 = Connect CAN inputs according to MIO mapping. 1 + * = Loop CAN 0 Tx to CAN 1 Rx, and CAN 1 Tx to CAN 0 Rx. + * PSU_IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1 0 + + * UART Loopback Control. 0 = Connect UART inputs according to MIO mapping. + * 1 = Loop UART 0 outputs to UART 1 inputs, and UART 1 outputs to UART 0 + * inputs. RXD/TXD cross-connected. RTS/CTS cross-connected. DSR, DTR, DCD + * and RI not used. + * PSU_IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1 0 + + * SPI Loopback Control. 0 = Connect SPI inputs according to MIO mapping. 1 + * = Loop SPI 0 outputs to SPI 1 inputs, and SPI 1 outputs to SPI 0 inputs + * . The other SPI core will appear on the LS Slave Select. + * PSU_IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1 0 + + * Loopback function within MIO + * (OFFSET, MASK, VALUE) (0XFF180200, 0x0000000FU ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_LOOPBACK_OFFSET, + 0x0000000FU, 0x00000000U); +/*##################################################################### */ + + + return 1; } -unsigned long psu_post_config_data() { - // : POST_CONFIG +unsigned long psu_peripherals_init_data(void) +{ + /* + * COHERENCY + */ + /* + * FPD RESET + */ + /* + * Register : RST_FPD_TOP @ 0XFD1A0100 - return 1; + * PCIE config reset + * PSU_CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET 0 + + * PCIE control block level reset + * PSU_CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET 0 + + * PCIE bridge block level reset (AXI interface) + * PSU_CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET 0 + + * Display Port block level reset (includes DPDMA) + * PSU_CRF_APB_RST_FPD_TOP_DP_RESET 0 + + * FPD WDT reset + * PSU_CRF_APB_RST_FPD_TOP_SWDT_RESET 0 + + * GDMA block level reset + * PSU_CRF_APB_RST_FPD_TOP_GDMA_RESET 0 + + * Pixel Processor (submodule of GPU) block level reset + * PSU_CRF_APB_RST_FPD_TOP_GPU_PP0_RESET 0 + + * Pixel Processor (submodule of GPU) block level reset + * PSU_CRF_APB_RST_FPD_TOP_GPU_PP1_RESET 0 + + * GPU block level reset + * PSU_CRF_APB_RST_FPD_TOP_GPU_RESET 0 + + * GT block level reset + * PSU_CRF_APB_RST_FPD_TOP_GT_RESET 0 + + * Sata block level reset + * PSU_CRF_APB_RST_FPD_TOP_SATA_RESET 0 + + * FPD Block level software controlled reset + * (OFFSET, MASK, VALUE) (0XFD1A0100, 0x000F807EU ,0x00000000U) + */ + PSU_Mask_Write(CRF_APB_RST_FPD_TOP_OFFSET, 0x000F807EU, 0x00000000U); +/*##################################################################### */ + + /* + * RESET BLOCKS + */ + /* + * TIMESTAMP + */ + /* + * Register : RST_LPD_IOU2 @ 0XFF5E0238 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET 0 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_IOU_CC_RESET 0 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_ADMA_RESET 0 + + * Software control register for the IOU block. Each bit will cause a singl + * erperipheral or part of the peripheral to be reset. + * (OFFSET, MASK, VALUE) (0XFF5E0238, 0x001A0000U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_IOU2_OFFSET, + 0x001A0000U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : RST_LPD_TOP @ 0XFF5E023C + + * Reset entire full power domain. + * PSU_CRL_APB_RST_LPD_TOP_FPD_RESET 0 + + * LPD SWDT + * PSU_CRL_APB_RST_LPD_TOP_LPD_SWDT_RESET 0 + + * Sysmonitor reset + * PSU_CRL_APB_RST_LPD_TOP_SYSMON_RESET 0 + + * Real Time Clock reset + * PSU_CRL_APB_RST_LPD_TOP_RTC_RESET 0 + + * APM reset + * PSU_CRL_APB_RST_LPD_TOP_APM_RESET 0 + + * IPI reset + * PSU_CRL_APB_RST_LPD_TOP_IPI_RESET 0 + + * reset entire RPU power island + * PSU_CRL_APB_RST_LPD_TOP_RPU_PGE_RESET 0 + + * reset ocm + * PSU_CRL_APB_RST_LPD_TOP_OCM_RESET 0 + + * Software control register for the LPD block. + * (OFFSET, MASK, VALUE) (0XFF5E023C, 0x0093C018U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_TOP_OFFSET, 0x0093C018U, 0x00000000U); +/*##################################################################### */ + + /* + * ENET + */ + /* + * Register : RST_LPD_IOU0 @ 0XFF5E0230 + + * GEM 3 reset + * PSU_CRL_APB_RST_LPD_IOU0_GEM3_RESET 0 + + * Software controlled reset for the GEMs + * (OFFSET, MASK, VALUE) (0XFF5E0230, 0x00000008U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_IOU0_OFFSET, + 0x00000008U, 0x00000000U); +/*##################################################################### */ + + /* + * QSPI + */ + /* + * Register : RST_LPD_IOU2 @ 0XFF5E0238 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_QSPI_RESET 0 + + * Software control register for the IOU block. Each bit will cause a singl + * erperipheral or part of the peripheral to be reset. + * (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000001U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_IOU2_OFFSET, + 0x00000001U, 0x00000000U); +/*##################################################################### */ + + /* + * QSPI TAP DELAY + */ + /* + * Register : IOU_TAPDLY_BYPASS @ 0XFF180390 + + * 0: Do not by pass the tap delays on the Rx clock signal of LQSPI 1: Bypa + * ss the Tap delay on the Rx clock signal of LQSPI + * PSU_IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX 1 + + * IOU tap delay bypass for the LQSPI and NAND controllers + * (OFFSET, MASK, VALUE) (0XFF180390, 0x00000004U ,0x00000004U) + */ + PSU_Mask_Write(IOU_SLCR_IOU_TAPDLY_BYPASS_OFFSET, + 0x00000004U, 0x00000004U); +/*##################################################################### */ + + /* + * NAND + */ + /* + * USB + */ + /* + * Register : RST_LPD_TOP @ 0XFF5E023C + + * USB 0 reset for control registers + * PSU_CRL_APB_RST_LPD_TOP_USB0_APB_RESET 0 + + * USB 0 sleep circuit reset + * PSU_CRL_APB_RST_LPD_TOP_USB0_HIBERRESET 0 + + * USB 0 reset + * PSU_CRL_APB_RST_LPD_TOP_USB0_CORERESET 0 + + * Software control register for the LPD block. + * (OFFSET, MASK, VALUE) (0XFF5E023C, 0x00000540U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_TOP_OFFSET, 0x00000540U, 0x00000000U); +/*##################################################################### */ + + /* + * USB0 PIPE POWER PRESENT + */ + /* + * Register : fpd_power_prsnt @ 0XFF9D0080 + + * This bit is used to choose between PIPE power present and 1'b1 + * PSU_USB3_0_FPD_POWER_PRSNT_OPTION 0X1 + + * fpd_power_prsnt + * (OFFSET, MASK, VALUE) (0XFF9D0080, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(USB3_0_FPD_POWER_PRSNT_OFFSET, + 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : fpd_pipe_clk @ 0XFF9D007C + + * This bit is used to choose between PIPE clock coming from SerDes and the + * suspend clk + * PSU_USB3_0_FPD_PIPE_CLK_OPTION 0x0 + + * fpd_pipe_clk + * (OFFSET, MASK, VALUE) (0XFF9D007C, 0x00000001U ,0x00000000U) + */ + PSU_Mask_Write(USB3_0_FPD_PIPE_CLK_OFFSET, 0x00000001U, 0x00000000U); +/*##################################################################### */ + + /* + * SD + */ + /* + * Register : RST_LPD_IOU2 @ 0XFF5E0238 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_SDIO1_RESET 0 + + * Software control register for the IOU block. Each bit will cause a singl + * erperipheral or part of the peripheral to be reset. + * (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000040U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_IOU2_OFFSET, + 0x00000040U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : CTRL_REG_SD @ 0XFF180310 + + * SD or eMMC selection on SDIO1 0: SD enabled 1: eMMC enabled + * PSU_IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL 0 + + * SD eMMC selection + * (OFFSET, MASK, VALUE) (0XFF180310, 0x00008000U ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_CTRL_REG_SD_OFFSET, + 0x00008000U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : SD_CONFIG_REG2 @ 0XFF180320 + + * Should be set based on the final product usage 00 - Removable SCard Slot + * 01 - Embedded Slot for One Device 10 - Shared Bus Slot 11 - Reserved + * PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE 0 + + * 1.8V Support 1: 1.8V supported 0: 1.8V not supported support + * PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V 1 + + * 3.0V Support 1: 3.0V supported 0: 3.0V not supported support + * PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V 0 + + * 3.3V Support 1: 3.3V supported 0: 3.3V not supported support + * PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V 1 + + * SD Config Register 2 + * (OFFSET, MASK, VALUE) (0XFF180320, 0x33800000U ,0x02800000U) + */ + PSU_Mask_Write(IOU_SLCR_SD_CONFIG_REG2_OFFSET, + 0x33800000U, 0x02800000U); +/*##################################################################### */ + + /* + * SD1 BASE CLOCK + */ + /* + * Register : SD_CONFIG_REG1 @ 0XFF18031C + + * Base Clock Frequency for SD Clock. This is the frequency of the xin_clk. + * PSU_IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK 0xc8 + + * Configures the Number of Taps (Phases) of the rxclk_in that is supported + * . + * PSU_IOU_SLCR_SD_CONFIG_REG1_SD1_TUNIGCOUNT 0x28 + + * SD Config Register 1 + * (OFFSET, MASK, VALUE) (0XFF18031C, 0x7FFE0000U ,0x64500000U) + */ + PSU_Mask_Write(IOU_SLCR_SD_CONFIG_REG1_OFFSET, + 0x7FFE0000U, 0x64500000U); +/*##################################################################### */ + + /* + * Register : SD_DLL_CTRL @ 0XFF180358 + + * Reserved. + * PSU_IOU_SLCR_SD_DLL_CTRL_RESERVED 1 + + * SDIO status register + * (OFFSET, MASK, VALUE) (0XFF180358, 0x00000008U ,0x00000008U) + */ + PSU_Mask_Write(IOU_SLCR_SD_DLL_CTRL_OFFSET, + 0x00000008U, 0x00000008U); +/*##################################################################### */ + + /* + * SD1 RETUNER + */ + /* + * Register : SD_CONFIG_REG3 @ 0XFF180324 + + * This is the Timer Count for Re-Tuning Timer for Re-Tuning Mode 1 to 3. S + * etting to 4'b0 disables Re-Tuning Timer. 0h - Get information via other + * source 1h = 1 seconds 2h = 2 seconds 3h = 4 seconds 4h = 8 seconds -- n + * = 2(n-1) seconds -- Bh = 1024 seconds Fh - Ch = Reserved + * PSU_IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR 0X0 + + * SD Config Register 3 + * (OFFSET, MASK, VALUE) (0XFF180324, 0x03C00000U ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_SD_CONFIG_REG3_OFFSET, + 0x03C00000U, 0x00000000U); +/*##################################################################### */ + + /* + * CAN + */ + /* + * Register : RST_LPD_IOU2 @ 0XFF5E0238 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_CAN1_RESET 0 + + * Software control register for the IOU block. Each bit will cause a singl + * erperipheral or part of the peripheral to be reset. + * (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000100U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_IOU2_OFFSET, + 0x00000100U, 0x00000000U); +/*##################################################################### */ + + /* + * I2C + */ + /* + * Register : RST_LPD_IOU2 @ 0XFF5E0238 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_I2C0_RESET 0 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_I2C1_RESET 0 + + * Software control register for the IOU block. Each bit will cause a singl + * erperipheral or part of the peripheral to be reset. + * (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000600U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_IOU2_OFFSET, + 0x00000600U, 0x00000000U); +/*##################################################################### */ + + /* + * SWDT + */ + /* + * Register : RST_LPD_IOU2 @ 0XFF5E0238 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_SWDT_RESET 0 + + * Software control register for the IOU block. Each bit will cause a singl + * erperipheral or part of the peripheral to be reset. + * (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00008000U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_IOU2_OFFSET, + 0x00008000U, 0x00000000U); +/*##################################################################### */ + + /* + * SPI + */ + /* + * TTC + */ + /* + * Register : RST_LPD_IOU2 @ 0XFF5E0238 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_TTC0_RESET 0 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_TTC1_RESET 0 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_TTC2_RESET 0 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_TTC3_RESET 0 + + * Software control register for the IOU block. Each bit will cause a singl + * erperipheral or part of the peripheral to be reset. + * (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00007800U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_IOU2_OFFSET, + 0x00007800U, 0x00000000U); +/*##################################################################### */ + + /* + * UART + */ + /* + * Register : RST_LPD_IOU2 @ 0XFF5E0238 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_UART0_RESET 0 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_UART1_RESET 0 + + * Software control register for the IOU block. Each bit will cause a singl + * erperipheral or part of the peripheral to be reset. + * (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000006U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_IOU2_OFFSET, + 0x00000006U, 0x00000000U); +/*##################################################################### */ + + /* + * UART BAUD RATE + */ + /* + * Register : Baud_rate_divider_reg0 @ 0XFF000034 + + * Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate + * PSU_UART0_BAUD_RATE_DIVIDER_REG0_BDIV 0x5 + + * Baud Rate Divider Register + * (OFFSET, MASK, VALUE) (0XFF000034, 0x000000FFU ,0x00000005U) + */ + PSU_Mask_Write(UART0_BAUD_RATE_DIVIDER_REG0_OFFSET, + 0x000000FFU, 0x00000005U); +/*##################################################################### */ + + /* + * Register : Baud_rate_gen_reg0 @ 0XFF000018 + + * Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor + * bypass (baud_sample = sel_clk) 2 - 65535: baud_sample + * PSU_UART0_BAUD_RATE_GEN_REG0_CD 0x8f + + * Baud Rate Generator Register. + * (OFFSET, MASK, VALUE) (0XFF000018, 0x0000FFFFU ,0x0000008FU) + */ + PSU_Mask_Write(UART0_BAUD_RATE_GEN_REG0_OFFSET, + 0x0000FFFFU, 0x0000008FU); +/*##################################################################### */ + + /* + * Register : Control_reg0 @ 0XFF000000 + + * Stop transmitter break: 0: no affect 1: stop transmission of the break a + * fter a minimum of one character length and transmit a high level during + * 12 bit periods. It can be set regardless of the value of STTBRK. + * PSU_UART0_CONTROL_REG0_STPBRK 0x0 + + * Start transmitter break: 0: no affect 1: start to transmit a break after + * the characters currently present in the FIFO and the transmit shift reg + * ister have been transmitted. It can only be set if STPBRK (Stop transmit + * ter break) is not high. + * PSU_UART0_CONTROL_REG0_STTBRK 0x0 + + * Restart receiver timeout counter: 1: receiver timeout counter is restart + * ed. This bit is self clearing once the restart has completed. + * PSU_UART0_CONTROL_REG0_RSTTO 0x0 + + * Transmit disable: 0: enable transmitter 1: disable transmitter + * PSU_UART0_CONTROL_REG0_TXDIS 0x0 + + * Transmit enable: 0: disable transmitter 1: enable transmitter, provided + * the TXDIS field is set to 0. + * PSU_UART0_CONTROL_REG0_TXEN 0x1 + + * Receive disable: 0: enable 1: disable, regardless of the value of RXEN + * PSU_UART0_CONTROL_REG0_RXDIS 0x0 + + * Receive enable: 0: disable 1: enable When set to one, the receiver logic + * is enabled, provided the RXDIS field is set to zero. + * PSU_UART0_CONTROL_REG0_RXEN 0x1 + + * Software reset for Tx data path: 0: no affect 1: transmitter logic is re + * set and all pending transmitter data is discarded This bit is self clear + * ing once the reset has completed. + * PSU_UART0_CONTROL_REG0_TXRES 0x1 + + * Software reset for Rx data path: 0: no affect 1: receiver logic is reset + * and all pending receiver data is discarded. This bit is self clearing o + * nce the reset has completed. + * PSU_UART0_CONTROL_REG0_RXRES 0x1 + + * UART Control Register + * (OFFSET, MASK, VALUE) (0XFF000000, 0x000001FFU ,0x00000017U) + */ + PSU_Mask_Write(UART0_CONTROL_REG0_OFFSET, 0x000001FFU, 0x00000017U); +/*##################################################################### */ + + /* + * Register : mode_reg0 @ 0XFF000004 + + * Channel mode: Defines the mode of operation of the UART. 00: normal 01: + * automatic echo 10: local loopback 11: remote loopback + * PSU_UART0_MODE_REG0_CHMODE 0x0 + + * Number of stop bits: Defines the number of stop bits to detect on receiv + * e and to generate on transmit. 00: 1 stop bit 01: 1.5 stop bits 10: 2 st + * op bits 11: reserved + * PSU_UART0_MODE_REG0_NBSTOP 0x0 + + * Parity type select: Defines the expected parity to check on receive and + * the parity to generate on transmit. 000: even parity 001: odd parity 010 + * : forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no pari + * ty + * PSU_UART0_MODE_REG0_PAR 0x4 + + * Character length select: Defines the number of bits in each character. 1 + * 1: 6 bits 10: 7 bits 0x: 8 bits + * PSU_UART0_MODE_REG0_CHRL 0x0 + + * Clock source select: This field defines whether a pre-scalar of 8 is app + * lied to the baud rate generator input clock. 0: clock source is uart_ref + * _clk 1: clock source is uart_ref_clk/8 + * PSU_UART0_MODE_REG0_CLKS 0x0 + + * UART Mode Register + * (OFFSET, MASK, VALUE) (0XFF000004, 0x000003FFU ,0x00000020U) + */ + PSU_Mask_Write(UART0_MODE_REG0_OFFSET, 0x000003FFU, 0x00000020U); +/*##################################################################### */ + + /* + * Register : Baud_rate_divider_reg0 @ 0XFF010034 + + * Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate + * PSU_UART1_BAUD_RATE_DIVIDER_REG0_BDIV 0x5 + + * Baud Rate Divider Register + * (OFFSET, MASK, VALUE) (0XFF010034, 0x000000FFU ,0x00000005U) + */ + PSU_Mask_Write(UART1_BAUD_RATE_DIVIDER_REG0_OFFSET, + 0x000000FFU, 0x00000005U); +/*##################################################################### */ + + /* + * Register : Baud_rate_gen_reg0 @ 0XFF010018 + + * Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor + * bypass (baud_sample = sel_clk) 2 - 65535: baud_sample + * PSU_UART1_BAUD_RATE_GEN_REG0_CD 0x8f + + * Baud Rate Generator Register. + * (OFFSET, MASK, VALUE) (0XFF010018, 0x0000FFFFU ,0x0000008FU) + */ + PSU_Mask_Write(UART1_BAUD_RATE_GEN_REG0_OFFSET, + 0x0000FFFFU, 0x0000008FU); +/*##################################################################### */ + + /* + * Register : Control_reg0 @ 0XFF010000 + + * Stop transmitter break: 0: no affect 1: stop transmission of the break a + * fter a minimum of one character length and transmit a high level during + * 12 bit periods. It can be set regardless of the value of STTBRK. + * PSU_UART1_CONTROL_REG0_STPBRK 0x0 + + * Start transmitter break: 0: no affect 1: start to transmit a break after + * the characters currently present in the FIFO and the transmit shift reg + * ister have been transmitted. It can only be set if STPBRK (Stop transmit + * ter break) is not high. + * PSU_UART1_CONTROL_REG0_STTBRK 0x0 + + * Restart receiver timeout counter: 1: receiver timeout counter is restart + * ed. This bit is self clearing once the restart has completed. + * PSU_UART1_CONTROL_REG0_RSTTO 0x0 + + * Transmit disable: 0: enable transmitter 1: disable transmitter + * PSU_UART1_CONTROL_REG0_TXDIS 0x0 + + * Transmit enable: 0: disable transmitter 1: enable transmitter, provided + * the TXDIS field is set to 0. + * PSU_UART1_CONTROL_REG0_TXEN 0x1 + + * Receive disable: 0: enable 1: disable, regardless of the value of RXEN + * PSU_UART1_CONTROL_REG0_RXDIS 0x0 + + * Receive enable: 0: disable 1: enable When set to one, the receiver logic + * is enabled, provided the RXDIS field is set to zero. + * PSU_UART1_CONTROL_REG0_RXEN 0x1 + + * Software reset for Tx data path: 0: no affect 1: transmitter logic is re + * set and all pending transmitter data is discarded This bit is self clear + * ing once the reset has completed. + * PSU_UART1_CONTROL_REG0_TXRES 0x1 + + * Software reset for Rx data path: 0: no affect 1: receiver logic is reset + * and all pending receiver data is discarded. This bit is self clearing o + * nce the reset has completed. + * PSU_UART1_CONTROL_REG0_RXRES 0x1 + + * UART Control Register + * (OFFSET, MASK, VALUE) (0XFF010000, 0x000001FFU ,0x00000017U) + */ + PSU_Mask_Write(UART1_CONTROL_REG0_OFFSET, 0x000001FFU, 0x00000017U); +/*##################################################################### */ + + /* + * Register : mode_reg0 @ 0XFF010004 + + * Channel mode: Defines the mode of operation of the UART. 00: normal 01: + * automatic echo 10: local loopback 11: remote loopback + * PSU_UART1_MODE_REG0_CHMODE 0x0 + + * Number of stop bits: Defines the number of stop bits to detect on receiv + * e and to generate on transmit. 00: 1 stop bit 01: 1.5 stop bits 10: 2 st + * op bits 11: reserved + * PSU_UART1_MODE_REG0_NBSTOP 0x0 + + * Parity type select: Defines the expected parity to check on receive and + * the parity to generate on transmit. 000: even parity 001: odd parity 010 + * : forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no pari + * ty + * PSU_UART1_MODE_REG0_PAR 0x4 + + * Character length select: Defines the number of bits in each character. 1 + * 1: 6 bits 10: 7 bits 0x: 8 bits + * PSU_UART1_MODE_REG0_CHRL 0x0 + + * Clock source select: This field defines whether a pre-scalar of 8 is app + * lied to the baud rate generator input clock. 0: clock source is uart_ref + * _clk 1: clock source is uart_ref_clk/8 + * PSU_UART1_MODE_REG0_CLKS 0x0 + + * UART Mode Register + * (OFFSET, MASK, VALUE) (0XFF010004, 0x000003FFU ,0x00000020U) + */ + PSU_Mask_Write(UART1_MODE_REG0_OFFSET, 0x000003FFU, 0x00000020U); +/*##################################################################### */ + + /* + * GPIO + */ + /* + * Register : RST_LPD_IOU2 @ 0XFF5E0238 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_GPIO_RESET 0 + + * Software control register for the IOU block. Each bit will cause a singl + * erperipheral or part of the peripheral to be reset. + * (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00040000U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_IOU2_OFFSET, + 0x00040000U, 0x00000000U); +/*##################################################################### */ + + /* + * ADMA TZ + */ + /* + * Register : slcr_adma @ 0XFF4B0024 + + * TrustZone Classification for ADMA + * PSU_LPD_SLCR_SECURE_SLCR_ADMA_TZ 0XFF + + * RPU TrustZone settings + * (OFFSET, MASK, VALUE) (0XFF4B0024, 0x000000FFU ,0x000000FFU) + */ + PSU_Mask_Write(LPD_SLCR_SECURE_SLCR_ADMA_OFFSET, + 0x000000FFU, 0x000000FFU); +/*##################################################################### */ + + /* + * CSU TAMPERING + */ + /* + * CSU TAMPER STATUS + */ + /* + * Register : tamper_status @ 0XFFCA5000 + + * CSU regsiter + * PSU_CSU_TAMPER_STATUS_TAMPER_0 0 + + * External MIO + * PSU_CSU_TAMPER_STATUS_TAMPER_1 0 + + * JTAG toggle detect + * PSU_CSU_TAMPER_STATUS_TAMPER_2 0 + + * PL SEU error + * PSU_CSU_TAMPER_STATUS_TAMPER_3 0 + + * AMS over temperature alarm for LPD + * PSU_CSU_TAMPER_STATUS_TAMPER_4 0 + + * AMS over temperature alarm for APU + * PSU_CSU_TAMPER_STATUS_TAMPER_5 0 + + * AMS voltage alarm for VCCPINT_FPD + * PSU_CSU_TAMPER_STATUS_TAMPER_6 0 + + * AMS voltage alarm for VCCPINT_LPD + * PSU_CSU_TAMPER_STATUS_TAMPER_7 0 + + * AMS voltage alarm for VCCPAUX + * PSU_CSU_TAMPER_STATUS_TAMPER_8 0 + + * AMS voltage alarm for DDRPHY + * PSU_CSU_TAMPER_STATUS_TAMPER_9 0 + + * AMS voltage alarm for PSIO bank 0/1/2 + * PSU_CSU_TAMPER_STATUS_TAMPER_10 0 + + * AMS voltage alarm for PSIO bank 3 (dedicated pins) + * PSU_CSU_TAMPER_STATUS_TAMPER_11 0 + + * AMS voltaage alarm for GT + * PSU_CSU_TAMPER_STATUS_TAMPER_12 0 + + * Tamper Response Status + * (OFFSET, MASK, VALUE) (0XFFCA5000, 0x00001FFFU ,0x00000000U) + */ + PSU_Mask_Write(CSU_TAMPER_STATUS_OFFSET, 0x00001FFFU, 0x00000000U); +/*##################################################################### */ + + /* + * CSU TAMPER RESPONSE + */ + /* + * CPU QOS DEFAULT + */ + /* + * Register : ACE_CTRL @ 0XFD5C0060 + + * Set ACE outgoing AWQOS value + * PSU_APU_ACE_CTRL_AWQOS 0X0 + + * Set ACE outgoing ARQOS value + * PSU_APU_ACE_CTRL_ARQOS 0X0 + + * ACE Control Register + * (OFFSET, MASK, VALUE) (0XFD5C0060, 0x000F000FU ,0x00000000U) + */ + PSU_Mask_Write(APU_ACE_CTRL_OFFSET, 0x000F000FU, 0x00000000U); +/*##################################################################### */ + + /* + * ENABLES RTC SWITCH TO BATTERY WHEN VCC_PSAUX IS NOT AVAILABLE + */ + /* + * Register : CONTROL @ 0XFFA60040 + + * Enables the RTC. By writing a 0 to this bit, RTC will be powered off and + * the only module that potentially draws current from the battery will be + * BBRAM. The value read through this bit does not necessarily reflect whe + * ther RTC is enabled or not. It is expected that RTC is enabled every tim + * e it is being configured. If RTC is not used in the design, FSBL will di + * sable it by writing a 0 to this bit. + * PSU_RTC_CONTROL_BATTERY_DISABLE 0X1 + + * This register controls various functionalities within the RTC + * (OFFSET, MASK, VALUE) (0XFFA60040, 0x80000000U ,0x80000000U) + */ + PSU_Mask_Write(RTC_CONTROL_OFFSET, 0x80000000U, 0x80000000U); +/*##################################################################### */ + + /* + * TIMESTAMP COUNTER + */ + /* + * Register : base_frequency_ID_register @ 0XFF260020 + + * Frequency in number of ticks per second. Valid range from 10 MHz to 100 + * MHz. + * PSU_IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ 0x5f5b9f0 + + * Program this register to match the clock frequency of the timestamp gene + * rator, in ticks per second. For example, for a 50 MHz clock, program 0x0 + * 2FAF080. This register is not accessible to the read-only programming in + * terface. + * (OFFSET, MASK, VALUE) (0XFF260020, 0xFFFFFFFFU ,0x05F5B9F0U) + */ + PSU_Mask_Write(IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_OFFSET, + 0xFFFFFFFFU, 0x05F5B9F0U); +/*##################################################################### */ + + /* + * Register : counter_control_register @ 0XFF260000 + + * Enable 0: The counter is disabled and not incrementing. 1: The counter i + * s enabled and is incrementing. + * PSU_IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN 0x1 + + * Controls the counter increments. This register is not accessible to the + * read-only programming interface. + * (OFFSET, MASK, VALUE) (0XFF260000, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(IOU_SCNTRS_COUNTER_CONTROL_REGISTER_OFFSET, + 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * TTC SRC SELECT + */ + /* + * PCIE GPIO RESET + */ + /* + * PCIE RESET + */ + /* + * DIR MODE BANK 0 + */ + /* + * DIR MODE BANK 1 + */ + /* + * Register : DIRM_1 @ 0XFF0A0244 + + * Operation is the same as DIRM_0[DIRECTION_0] + * PSU_GPIO_DIRM_1_DIRECTION_1 0x20 + + * Direction mode (GPIO Bank1, MIO) + * (OFFSET, MASK, VALUE) (0XFF0A0244, 0x03FFFFFFU ,0x00000020U) + */ + PSU_Mask_Write(GPIO_DIRM_1_OFFSET, 0x03FFFFFFU, 0x00000020U); +/*##################################################################### */ + + /* + * DIR MODE BANK 2 + */ + /* + * OUTPUT ENABLE BANK 0 + */ + /* + * OUTPUT ENABLE BANK 1 + */ + /* + * Register : OEN_1 @ 0XFF0A0248 + + * Operation is the same as OEN_0[OP_ENABLE_0] + * PSU_GPIO_OEN_1_OP_ENABLE_1 0x20 + + * Output enable (GPIO Bank1, MIO) + * (OFFSET, MASK, VALUE) (0XFF0A0248, 0x03FFFFFFU ,0x00000020U) + */ + PSU_Mask_Write(GPIO_OEN_1_OFFSET, 0x03FFFFFFU, 0x00000020U); +/*##################################################################### */ + + /* + * OUTPUT ENABLE BANK 2 + */ + /* + * MASK_DATA_0_LSW LOW BANK [15:0] + */ + /* + * MASK_DATA_0_MSW LOW BANK [25:16] + */ + /* + * MASK_DATA_1_LSW LOW BANK [41:26] + */ + /* + * Register : MASK_DATA_1_LSW @ 0XFF0A0008 + + * Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW] + * PSU_GPIO_MASK_DATA_1_LSW_MASK_1_LSW 0xffdf + + * Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW] + * PSU_GPIO_MASK_DATA_1_LSW_DATA_1_LSW 0x20 + + * Maskable Output Data (GPIO Bank1, MIO, Lower 16bits) + * (OFFSET, MASK, VALUE) (0XFF0A0008, 0xFFFFFFFFU ,0xFFDF0020U) + */ + PSU_Mask_Write(GPIO_MASK_DATA_1_LSW_OFFSET, + 0xFFFFFFFFU, 0xFFDF0020U); +/*##################################################################### */ + + /* + * MASK_DATA_1_MSW HIGH BANK [51:42] + */ + /* + * MASK_DATA_1_LSW HIGH BANK [67:52] + */ + /* + * MASK_DATA_1_LSW HIGH BANK [77:68] + */ + /* + * ADD 1 MS DELAY + */ + mask_delay(1); + +/*##################################################################### */ + + /* + * MASK_DATA_0_LSW LOW BANK [15:0] + */ + /* + * MASK_DATA_0_MSW LOW BANK [25:16] + */ + /* + * MASK_DATA_1_LSW LOW BANK [41:26] + */ + /* + * Register : MASK_DATA_1_LSW @ 0XFF0A0008 + + * Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW] + * PSU_GPIO_MASK_DATA_1_LSW_MASK_1_LSW 0xffdf + + * Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW] + * PSU_GPIO_MASK_DATA_1_LSW_DATA_1_LSW 0x0 + + * Maskable Output Data (GPIO Bank1, MIO, Lower 16bits) + * (OFFSET, MASK, VALUE) (0XFF0A0008, 0xFFFFFFFFU ,0xFFDF0000U) + */ + PSU_Mask_Write(GPIO_MASK_DATA_1_LSW_OFFSET, + 0xFFFFFFFFU, 0xFFDF0000U); +/*##################################################################### */ + + /* + * MASK_DATA_1_MSW HIGH BANK [51:42] + */ + /* + * MASK_DATA_1_LSW HIGH BANK [67:52] + */ + /* + * MASK_DATA_1_LSW HIGH BANK [77:68] + */ + /* + * ADD 5 MS DELAY + */ + mask_delay(5); + +/*##################################################################### */ + + + return 1; } -unsigned long psu_peripherals_powerdwn_data() { - // : POWER DOWN REQUEST INTERRUPT ENABLE - // : POWER DOWN TRIGGER +unsigned long psu_post_config_data(void) +{ + /* + * POST_CONFIG + */ - return 1; + return 1; } -unsigned long psu_lpd_xppu_data() { - // : XPPU INTERRUPT ENABLE - /*Register : IEN @ 0XFF980018

+unsigned long psu_peripherals_powerdwn_data(void) +{ + /* + * POWER DOWN REQUEST INTERRUPT ENABLE + */ + /* + * POWER DOWN TRIGGER + */ - See Interuppt Status Register for details - PSU_LPD_XPPU_CFG_IEN_APER_PARITY 0X1 - - See Interuppt Status Register for details - PSU_LPD_XPPU_CFG_IEN_APER_TZ 0X1 - - See Interuppt Status Register for details - PSU_LPD_XPPU_CFG_IEN_APER_PERM 0X1 - - See Interuppt Status Register for details - PSU_LPD_XPPU_CFG_IEN_MID_PARITY 0X1 - - See Interuppt Status Register for details - PSU_LPD_XPPU_CFG_IEN_MID_RO 0X1 - - See Interuppt Status Register for details - PSU_LPD_XPPU_CFG_IEN_MID_MISS 0X1 - - See Interuppt Status Register for details - PSU_LPD_XPPU_CFG_IEN_INV_APB 0X1 - - Interrupt Enable Register - (OFFSET, MASK, VALUE) (0XFF980018, 0x000000EFU ,0x000000EFU) - RegMask = (LPD_XPPU_CFG_IEN_APER_PARITY_MASK | LPD_XPPU_CFG_IEN_APER_TZ_MASK | LPD_XPPU_CFG_IEN_APER_PERM_MASK | LPD_XPPU_CFG_IEN_MID_PARITY_MASK | LPD_XPPU_CFG_IEN_MID_RO_MASK | LPD_XPPU_CFG_IEN_MID_MISS_MASK | LPD_XPPU_CFG_IEN_INV_APB_MASK | 0 ); - - RegVal = ((0x00000001U << LPD_XPPU_CFG_IEN_APER_PARITY_SHIFT - | 0x00000001U << LPD_XPPU_CFG_IEN_APER_TZ_SHIFT - | 0x00000001U << LPD_XPPU_CFG_IEN_APER_PERM_SHIFT - | 0x00000001U << LPD_XPPU_CFG_IEN_MID_PARITY_SHIFT - | 0x00000001U << LPD_XPPU_CFG_IEN_MID_RO_SHIFT - | 0x00000001U << LPD_XPPU_CFG_IEN_MID_MISS_SHIFT - | 0x00000001U << LPD_XPPU_CFG_IEN_INV_APB_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (LPD_XPPU_CFG_IEN_OFFSET ,0x000000EFU ,0x000000EFU); - /*############################################################################################################################ */ - - - return 1; + return 1; } -unsigned long psu_ddr_xmpu0_data() { +unsigned long psu_lpd_xppu_data(void) +{ + /* + * MASTER ID LIST + */ + /* + * APERTURE PERMISIION LIST + */ + /* + * APERTURE NAME: UART0, START ADDRESS: FF000000, END ADDRESS: FF00FFFF + */ + /* + * APERTURE NAME: UART1, START ADDRESS: FF010000, END ADDRESS: FF01FFFF + */ + /* + * APERTURE NAME: I2C0, START ADDRESS: FF020000, END ADDRESS: FF02FFFF + */ + /* + * APERTURE NAME: I2C1, START ADDRESS: FF030000, END ADDRESS: FF03FFFF + */ + /* + * APERTURE NAME: SPI0, START ADDRESS: FF040000, END ADDRESS: FF04FFFF + */ + /* + * APERTURE NAME: SPI1, START ADDRESS: FF050000, END ADDRESS: FF05FFFF + */ + /* + * APERTURE NAME: CAN0, START ADDRESS: FF060000, END ADDRESS: FF06FFFF + */ + /* + * APERTURE NAME: CAN1, START ADDRESS: FF070000, END ADDRESS: FF07FFFF + */ + /* + * APERTURE NAME: RPU_UNUSED_12, START ADDRESS: FF080000, END ADDRESS: FF09 + * FFFF + */ + /* + * APERTURE NAME: RPU_UNUSED_12, START ADDRESS: FF080000, END ADDRESS: FF09 + * FFFF + */ + /* + * APERTURE NAME: GPIO, START ADDRESS: FF0A0000, END ADDRESS: FF0AFFFF + */ + /* + * APERTURE NAME: GEM0, START ADDRESS: FF0B0000, END ADDRESS: FF0BFFFF + */ + /* + * APERTURE NAME: GEM1, START ADDRESS: FF0C0000, END ADDRESS: FF0CFFFF + */ + /* + * APERTURE NAME: GEM2, START ADDRESS: FF0D0000, END ADDRESS: FF0DFFFF + */ + /* + * APERTURE NAME: GEM3, START ADDRESS: FF0E0000, END ADDRESS: FF0EFFFF + */ + /* + * APERTURE NAME: QSPI, START ADDRESS: FF0F0000, END ADDRESS: FF0FFFFF + */ + /* + * APERTURE NAME: NAND, START ADDRESS: FF100000, END ADDRESS: FF10FFFF + */ + /* + * APERTURE NAME: TTC0, START ADDRESS: FF110000, END ADDRESS: FF11FFFF + */ + /* + * APERTURE NAME: TTC1, START ADDRESS: FF120000, END ADDRESS: FF12FFFF + */ + /* + * APERTURE NAME: TTC2, START ADDRESS: FF130000, END ADDRESS: FF13FFFF + */ + /* + * APERTURE NAME: TTC3, START ADDRESS: FF140000, END ADDRESS: FF14FFFF + */ + /* + * APERTURE NAME: SWDT, START ADDRESS: FF150000, END ADDRESS: FF15FFFF + */ + /* + * APERTURE NAME: SD0, START ADDRESS: FF160000, END ADDRESS: FF16FFFF + */ + /* + * APERTURE NAME: SD1, START ADDRESS: FF170000, END ADDRESS: FF17FFFF + */ + /* + * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + */ + /* + * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + */ + /* + * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + */ + /* + * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + */ + /* + * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + */ + /* + * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + */ + /* + * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + */ + /* + * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + */ + /* + * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + */ + /* + * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + */ + /* + * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + */ + /* + * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + */ + /* + * APERTURE NAME: IOU_SECURE_SLCR, START ADDRESS: FF240000, END ADDRESS: FF + * 24FFFF + */ + /* + * APERTURE NAME: IOU_SCNTR, START ADDRESS: FF250000, END ADDRESS: FF25FFFF + */ + /* + * APERTURE NAME: IOU_SCNTRS, START ADDRESS: FF260000, END ADDRESS: FF26FFF + * F + */ + /* + * APERTURE NAME: RPU_UNUSED_11, START ADDRESS: FF270000, END ADDRESS: FF2A + * FFFF + */ + /* + * APERTURE NAME: RPU_UNUSED_11, START ADDRESS: FF270000, END ADDRESS: FF2A + * FFFF + */ + /* + * APERTURE NAME: RPU_UNUSED_11, START ADDRESS: FF270000, END ADDRESS: FF2A + * FFFF + */ + /* + * APERTURE NAME: RPU_UNUSED_11, START ADDRESS: FF270000, END ADDRESS: FF2A + * FFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_14, START ADDRESS: FF2B0000, END ADDRESS: FF2F + * FFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_14, START ADDRESS: FF2B0000, END ADDRESS: FF2F + * FFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_14, START ADDRESS: FF2B0000, END ADDRESS: FF2F + * FFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_14, START ADDRESS: FF2B0000, END ADDRESS: FF2F + * FFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_14, START ADDRESS: FF2B0000, END ADDRESS: FF2F + * FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF + */ + /* + * APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF + */ + /* + * APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF + */ + /* + * APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF + */ + /* + * APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF + */ + /* + * APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF + */ + /* + * APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF + */ + /* + * APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_1, START ADDRESS: FF400000, END ADDRESS: FF40F + * FFF + */ + /* + * APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + */ + /* + * APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + */ + /* + * APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + */ + /* + * APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + */ + /* + * APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + */ + /* + * APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + */ + /* + * APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + */ + /* + * APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + */ + /* + * APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + */ + /* + * APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + */ + /* + * APERTURE NAME: LPD_SLCR_SECURE, START ADDRESS: FF4B0000, END ADDRESS: FF + * 4DFFFF + */ + /* + * APERTURE NAME: LPD_SLCR_SECURE, START ADDRESS: FF4B0000, END ADDRESS: FF + * 4DFFFF + */ + /* + * APERTURE NAME: LPD_SLCR_SECURE, START ADDRESS: FF4B0000, END ADDRESS: FF + * 4DFFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: OCM_SLCR, START ADDRESS: FF960000, END ADDRESS: FF96FFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_4, START ADDRESS: FF970000, END ADDRESS: FF97F + * FFF + */ + /* + * APERTURE NAME: LPD_XPPU, START ADDRESS: FF980000, END ADDRESS: FF99FFFF + */ + /* + * APERTURE NAME: RPU, START ADDRESS: FF9A0000, END ADDRESS: FF9AFFFF + */ + /* + * APERTURE NAME: AFIFM6, START ADDRESS: FF9B0000, END ADDRESS: FF9BFFFF + */ + /* + * APERTURE NAME: LPD_XPPU_SINK, START ADDRESS: FF9C0000, END ADDRESS: FF9C + * FFFF + */ + /* + * APERTURE NAME: USB3_0, START ADDRESS: FF9D0000, END ADDRESS: FF9DFFFF + */ + /* + * APERTURE NAME: USB3_1, START ADDRESS: FF9E0000, END ADDRESS: FF9EFFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_5, START ADDRESS: FF9F0000, END ADDRESS: FF9FF + * FFF + */ + /* + * APERTURE NAME: APM0, START ADDRESS: FFA00000, END ADDRESS: FFA0FFFF + */ + /* + * APERTURE NAME: APM1, START ADDRESS: FFA10000, END ADDRESS: FFA1FFFF + */ + /* + * APERTURE NAME: APM_INTC_IOU, START ADDRESS: FFA20000, END ADDRESS: FFA2F + * FFF + */ + /* + * APERTURE NAME: APM_FPD_LPD, START ADDRESS: FFA30000, END ADDRESS: FFA3FF + * FF + */ + /* + * APERTURE NAME: LPD_UNUSED_6, START ADDRESS: FFA40000, END ADDRESS: FFA4F + * FFF + */ + /* + * APERTURE NAME: AMS, START ADDRESS: FFA50000, END ADDRESS: FFA5FFFF + */ + /* + * APERTURE NAME: RTC, START ADDRESS: FFA60000, END ADDRESS: FFA6FFFF + */ + /* + * APERTURE NAME: OCM_XMPU_CFG, START ADDRESS: FFA70000, END ADDRESS: FFA7F + * FFF + */ + /* + * APERTURE NAME: ADMA_0, START ADDRESS: FFA80000, END ADDRESS: FFA8FFFF + */ + /* + * APERTURE NAME: ADMA_1, START ADDRESS: FFA90000, END ADDRESS: FFA9FFFF + */ + /* + * APERTURE NAME: ADMA_2, START ADDRESS: FFAA0000, END ADDRESS: FFAAFFFF + */ + /* + * APERTURE NAME: ADMA_3, START ADDRESS: FFAB0000, END ADDRESS: FFABFFFF + */ + /* + * APERTURE NAME: ADMA_4, START ADDRESS: FFAC0000, END ADDRESS: FFACFFFF + */ + /* + * APERTURE NAME: ADMA_5, START ADDRESS: FFAD0000, END ADDRESS: FFADFFFF + */ + /* + * APERTURE NAME: ADMA_6, START ADDRESS: FFAE0000, END ADDRESS: FFAEFFFF + */ + /* + * APERTURE NAME: ADMA_7, START ADDRESS: FFAF0000, END ADDRESS: FFAFFFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: CSU_ROM, START ADDRESS: FFC00000, END ADDRESS: FFC1FFFF + */ + /* + * APERTURE NAME: CSU_ROM, START ADDRESS: FFC00000, END ADDRESS: FFC1FFFF + */ + /* + * APERTURE NAME: CSU_LOCAL, START ADDRESS: FFC20000, END ADDRESS: FFC2FFFF + */ + /* + * APERTURE NAME: PUF, START ADDRESS: FFC30000, END ADDRESS: FFC3FFFF + */ + /* + * APERTURE NAME: CSU_RAM, START ADDRESS: FFC40000, END ADDRESS: FFC5FFFF + */ + /* + * APERTURE NAME: CSU_RAM, START ADDRESS: FFC40000, END ADDRESS: FFC5FFFF + */ + /* + * APERTURE NAME: CSU_IOMODULE, START ADDRESS: FFC60000, END ADDRESS: FFC7F + * FFF + */ + /* + * APERTURE NAME: CSU_IOMODULE, START ADDRESS: FFC60000, END ADDRESS: FFC7F + * FFF + */ + /* + * APERTURE NAME: CSUDMA, START ADDRESS: FFC80000, END ADDRESS: FFC9FFFF + */ + /* + * APERTURE NAME: CSUDMA, START ADDRESS: FFC80000, END ADDRESS: FFC9FFFF + */ + /* + * APERTURE NAME: CSU, START ADDRESS: FFCA0000, END ADDRESS: FFCAFFFF + */ + /* + * APERTURE NAME: CSU_WDT, START ADDRESS: FFCB0000, END ADDRESS: FFCBFFFF + */ + /* + * APERTURE NAME: EFUSE, START ADDRESS: FFCC0000, END ADDRESS: FFCCFFFF + */ + /* + * APERTURE NAME: BBRAM, START ADDRESS: FFCD0000, END ADDRESS: FFCDFFFF + */ + /* + * APERTURE NAME: RSA_CORE, START ADDRESS: FFCE0000, END ADDRESS: FFCEFFFF + */ + /* + * APERTURE NAME: MBISTJTAG, START ADDRESS: FFCF0000, END ADDRESS: FFCFFFFF + */ + /* + * APERTURE NAME: PMU_ROM, START ADDRESS: FFD00000, END ADDRESS: FFD3FFFF + */ + /* + * APERTURE NAME: PMU_ROM, START ADDRESS: FFD00000, END ADDRESS: FFD3FFFF + */ + /* + * APERTURE NAME: PMU_ROM, START ADDRESS: FFD00000, END ADDRESS: FFD3FFFF + */ + /* + * APERTURE NAME: PMU_ROM, START ADDRESS: FFD00000, END ADDRESS: FFD3FFFF + */ + /* + * APERTURE NAME: PMU_IOMODULE, START ADDRESS: FFD40000, END ADDRESS: FFD5F + * FFF + */ + /* + * APERTURE NAME: PMU_IOMODULE, START ADDRESS: FFD40000, END ADDRESS: FFD5F + * FFF + */ + /* + * APERTURE NAME: PMU_LOCAL, START ADDRESS: FFD60000, END ADDRESS: FFD7FFFF + */ + /* + * APERTURE NAME: PMU_LOCAL, START ADDRESS: FFD60000, END ADDRESS: FFD7FFFF + */ + /* + * APERTURE NAME: PMU_GLOBAL, START ADDRESS: FFD80000, END ADDRESS: FFDBFFF + * F + */ + /* + * APERTURE NAME: PMU_GLOBAL, START ADDRESS: FFD80000, END ADDRESS: FFDBFFF + * F + */ + /* + * APERTURE NAME: PMU_GLOBAL, START ADDRESS: FFD80000, END ADDRESS: FFDBFFF + * F + */ + /* + * APERTURE NAME: PMU_GLOBAL, START ADDRESS: FFD80000, END ADDRESS: FFDBFFF + * F + */ + /* + * APERTURE NAME: PMU_RAM, START ADDRESS: FFDC0000, END ADDRESS: FFDFFFFF + */ + /* + * APERTURE NAME: PMU_RAM, START ADDRESS: FFDC0000, END ADDRESS: FFDFFFFF + */ + /* + * APERTURE NAME: PMU_RAM, START ADDRESS: FFDC0000, END ADDRESS: FFDFFFFF + */ + /* + * APERTURE NAME: PMU_RAM, START ADDRESS: FFDC0000, END ADDRESS: FFDFFFFF + */ + /* + * APERTURE NAME: R5_0_ATCM, START ADDRESS: FFE00000, END ADDRESS: FFE0FFFF + */ + /* + * APERTURE NAME: R5_0_ATCM_LOCKSTEP, START ADDRESS: FFE10000, END ADDRESS: + * FFE1FFFF + */ + /* + * APERTURE NAME: R5_0_BTCM, START ADDRESS: FFE20000, END ADDRESS: FFE2FFFF + */ + /* + * APERTURE NAME: R5_0_BTCM_LOCKSTEP, START ADDRESS: FFE30000, END ADDRESS: + * FFE3FFFF + */ + /* + * APERTURE NAME: R5_0_INSTRUCTION_CACHE, START ADDRESS: FFE40000, END ADDR + * ESS: FFE4FFFF + */ + /* + * APERTURE NAME: R5_0_DATA_CACHE, START ADDRESS: FFE50000, END ADDRESS: FF + * E5FFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_8, START ADDRESS: FFE60000, END ADDRESS: FFE8F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_8, START ADDRESS: FFE60000, END ADDRESS: FFE8F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_8, START ADDRESS: FFE60000, END ADDRESS: FFE8F + * FFF + */ + /* + * APERTURE NAME: R5_1_ATCM_, START ADDRESS: FFE90000, END ADDRESS: FFE9FFF + * F + */ + /* + * APERTURE NAME: RPU_UNUSED_10, START ADDRESS: FFEA0000, END ADDRESS: FFEA + * FFFF + */ + /* + * APERTURE NAME: R5_1_BTCM_, START ADDRESS: FFEB0000, END ADDRESS: FFEBFFF + * F + */ + /* + * APERTURE NAME: R5_1_INSTRUCTION_CACHE, START ADDRESS: FFEC0000, END ADDR + * ESS: FFECFFFF + */ + /* + * APERTURE NAME: R5_1_DATA_CACHE, START ADDRESS: FFED0000, END ADDRESS: FF + * EDFFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_15, START ADDRESS: FFFD0000, END ADDRESS: FFFF + * FFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_15, START ADDRESS: FFFD0000, END ADDRESS: FFFF + * FFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_15, START ADDRESS: FFFD0000, END ADDRESS: FFFF + * FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IOU_GPV, START ADDRESS: FE000000, END ADDRESS: FE0FFFFF + */ + /* + * APERTURE NAME: LPD_GPV, START ADDRESS: FE100000, END ADDRESS: FE1FFFFF + */ + /* + * APERTURE NAME: USB3_0_XHCI, START ADDRESS: FE200000, END ADDRESS: FE2FFF + * FF + */ + /* + * APERTURE NAME: USB3_1_XHCI, START ADDRESS: FE300000, END ADDRESS: FE3FFF + * FF + */ + /* + * APERTURE NAME: LPD_UNUSED_13, START ADDRESS: FE400000, END ADDRESS: FE7F + * FFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_13, START ADDRESS: FE400000, END ADDRESS: FE7F + * FFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_13, START ADDRESS: FE400000, END ADDRESS: FE7F + * FFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_13, START ADDRESS: FE400000, END ADDRESS: FE7F + * FFFF + */ + /* + * APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF + */ + /* + * APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF + */ + /* + * APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF + */ + /* + * APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF + */ + /* + * APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF + */ + /* + * APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF + */ + /* + * APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF + */ + /* + * APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF + */ + /* + * APERTURE NAME: QSPI_LINEAR_ADDRESS, START ADDRESS: C0000000, END ADDRESS + * : DFFFFFFF + */ + /* + * XPPU CONTROL + */ - return 1; + return 1; } -unsigned long psu_ddr_xmpu1_data() { +unsigned long psu_ddr_xmpu0_data(void) +{ + /* + * DDR XMPU0 + */ - return 1; + return 1; } -unsigned long psu_ddr_xmpu2_data() { +unsigned long psu_ddr_xmpu1_data(void) +{ + /* + * DDR XMPU1 + */ - return 1; + return 1; } -unsigned long psu_ddr_xmpu3_data() { +unsigned long psu_ddr_xmpu2_data(void) +{ + /* + * DDR XMPU2 + */ - return 1; + return 1; } -unsigned long psu_ddr_xmpu4_data() { +unsigned long psu_ddr_xmpu3_data(void) +{ + /* + * DDR XMPU3 + */ - return 1; + return 1; } -unsigned long psu_ddr_xmpu5_data() { +unsigned long psu_ddr_xmpu4_data(void) +{ + /* + * DDR XMPU4 + */ - return 1; + return 1; } -unsigned long psu_ocm_xmpu_data() { +unsigned long psu_ddr_xmpu5_data(void) +{ + /* + * DDR XMPU5 + */ - return 1; + return 1; } -unsigned long psu_fpd_xmpu_data() { +unsigned long psu_ocm_xmpu_data(void) +{ + /* + * OCM XMPU + */ - return 1; + return 1; } -unsigned long psu_protection_lock_data() { +unsigned long psu_fpd_xmpu_data(void) +{ + /* + * FPD XMPU + */ - return 1; + return 1; } -unsigned long psu_apply_master_tz() { - // : RPU - // : DP TZ - // : SATA TZ - // : PCIE TZ - // : USB TZ - // : SD TZ - // : GEM TZ - // : QSPI TZ - // : NAND TZ +unsigned long psu_protection_lock_data(void) +{ + /* + * LOCKING PROTECTION MODULE + */ + /* + * XPPU LOCK + */ + /* + * APERTURE NAME: LPD_XPPU, START ADDRESS: FF980000, END ADDRESS: FF99FFFF + */ + /* + * XMPU LOCK + */ + /* + * LOCK OCM XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER + */ + /* + * LOCK FPD XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER + */ + /* + * LOCK DDR XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER + */ + /* + * LOCK DDR XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER + */ + /* + * LOCK DDR XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER + */ + /* + * LOCK DDR XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER + */ + /* + * LOCK DDR XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER + */ + /* + * LOCK DDR XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER + */ - return 1; + return 1; } -unsigned long psu_serdes_init_data() { - // : SERDES INITIALIZATION - // : GT REFERENCE CLOCK SOURCE SELECTION - /*Register : PLL_REF_SEL0 @ 0XFD410000

+unsigned long psu_apply_master_tz(void) +{ + /* + * RPU + */ + /* + * DP TZ + */ + /* + * Register : slcr_dpdma @ 0XFD690040 - PLL0 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - - 4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135 - Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved - PSU_SERDES_PLL_REF_SEL0_PLLREFSEL0 0xD + * TrustZone classification for DisplayPort DMA + * PSU_FPD_SLCR_SECURE_SLCR_DPDMA_TZ 1 - PLL0 Reference Selection Register - (OFFSET, MASK, VALUE) (0XFD410000, 0x0000001FU ,0x0000000DU) - RegMask = (SERDES_PLL_REF_SEL0_PLLREFSEL0_MASK | 0 ); + * DPDMA TrustZone Settings + * (OFFSET, MASK, VALUE) (0XFD690040, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(FPD_SLCR_SECURE_SLCR_DPDMA_OFFSET, + 0x00000001U, 0x00000001U); +/*##################################################################### */ - RegVal = ((0x0000000DU << SERDES_PLL_REF_SEL0_PLLREFSEL0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_PLL_REF_SEL0_OFFSET ,0x0000001FU ,0x0000000DU); - /*############################################################################################################################ */ + /* + * SATA TZ + */ + /* + * PCIE TZ + */ + /* + * Register : slcr_pcie @ 0XFD690030 - /*Register : PLL_REF_SEL1 @ 0XFD410004

+ * TrustZone classification for DMA Channel 0 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_0 1 - PLL1 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - - 4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135 - Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved - PSU_SERDES_PLL_REF_SEL1_PLLREFSEL1 0x9 + * TrustZone classification for DMA Channel 1 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_1 1 - PLL1 Reference Selection Register - (OFFSET, MASK, VALUE) (0XFD410004, 0x0000001FU ,0x00000009U) - RegMask = (SERDES_PLL_REF_SEL1_PLLREFSEL1_MASK | 0 ); + * TrustZone classification for DMA Channel 2 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_2 1 - RegVal = ((0x00000009U << SERDES_PLL_REF_SEL1_PLLREFSEL1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_PLL_REF_SEL1_OFFSET ,0x0000001FU ,0x00000009U); - /*############################################################################################################################ */ + * TrustZone classification for DMA Channel 3 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_3 1 - /*Register : PLL_REF_SEL2 @ 0XFD410008

+ * TrustZone classification for Ingress Address Translation 0 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_0 1 - PLL2 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - - 4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135 - Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved - PSU_SERDES_PLL_REF_SEL2_PLLREFSEL2 0x8 + * TrustZone classification for Ingress Address Translation 1 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_1 1 - PLL2 Reference Selection Register - (OFFSET, MASK, VALUE) (0XFD410008, 0x0000001FU ,0x00000008U) - RegMask = (SERDES_PLL_REF_SEL2_PLLREFSEL2_MASK | 0 ); + * TrustZone classification for Ingress Address Translation 2 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_2 1 - RegVal = ((0x00000008U << SERDES_PLL_REF_SEL2_PLLREFSEL2_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_PLL_REF_SEL2_OFFSET ,0x0000001FU ,0x00000008U); - /*############################################################################################################################ */ + * TrustZone classification for Ingress Address Translation 3 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_3 1 + + * TrustZone classification for Ingress Address Translation 4 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_4 1 + + * TrustZone classification for Ingress Address Translation 5 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_5 1 + + * TrustZone classification for Ingress Address Translation 6 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_6 1 - /*Register : PLL_REF_SEL3 @ 0XFD41000C

- - PLL3 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - - 4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135 - Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved - PSU_SERDES_PLL_REF_SEL3_PLLREFSEL3 0xF - - PLL3 Reference Selection Register - (OFFSET, MASK, VALUE) (0XFD41000C, 0x0000001FU ,0x0000000FU) - RegMask = (SERDES_PLL_REF_SEL3_PLLREFSEL3_MASK | 0 ); - - RegVal = ((0x0000000FU << SERDES_PLL_REF_SEL3_PLLREFSEL3_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_PLL_REF_SEL3_OFFSET ,0x0000001FU ,0x0000000FU); - /*############################################################################################################################ */ - - // : GT REFERENCE CLOCK FREQUENCY SELECTION - /*Register : L0_L0_REF_CLK_SEL @ 0XFD402860

- - Sel of lane 0 ref clock local mux. Set to 1 to select lane 0 slicer output. Set to 0 to select lane0 ref clock mux output. - PSU_SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL 0x1 - - Lane0 Ref Clock Selection Register - (OFFSET, MASK, VALUE) (0XFD402860, 0x00000080U ,0x00000080U) - RegMask = (SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_L0_REF_CLK_SEL_OFFSET ,0x00000080U ,0x00000080U); - /*############################################################################################################################ */ - - /*Register : L0_L1_REF_CLK_SEL @ 0XFD402864

- - Sel of lane 1 ref clock local mux. Set to 1 to select lane 1 slicer output. Set to 0 to select lane1 ref clock mux output. - PSU_SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL 0x0 - - Bit 3 of lane 1 ref clock mux one hot sel. Set to 1 to select lane 3 slicer output from ref clock network - PSU_SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3 0x1 - - Lane1 Ref Clock Selection Register - (OFFSET, MASK, VALUE) (0XFD402864, 0x00000088U ,0x00000008U) - RegMask = (SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_MASK | SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_MASK | 0 ); - - RegVal = ((0x00000000U << SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_SHIFT - | 0x00000001U << SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_L1_REF_CLK_SEL_OFFSET ,0x00000088U ,0x00000008U); - /*############################################################################################################################ */ - - /*Register : L0_L2_REF_CLK_SEL @ 0XFD402868

- - Sel of lane 2 ref clock local mux. Set to 1 to select lane 1 slicer output. Set to 0 to select lane2 ref clock mux output. - PSU_SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL 0x1 - - Lane2 Ref Clock Selection Register - (OFFSET, MASK, VALUE) (0XFD402868, 0x00000080U ,0x00000080U) - RegMask = (SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_L2_REF_CLK_SEL_OFFSET ,0x00000080U ,0x00000080U); - /*############################################################################################################################ */ - - /*Register : L0_L3_REF_CLK_SEL @ 0XFD40286C

- - Sel of lane 3 ref clock local mux. Set to 1 to select lane 3 slicer output. Set to 0 to select lane3 ref clock mux output. - PSU_SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL 0x0 - - Bit 1 of lane 3 ref clock mux one hot sel. Set to 1 to select lane 1 slicer output from ref clock network - PSU_SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1 0x1 - - Lane3 Ref Clock Selection Register - (OFFSET, MASK, VALUE) (0XFD40286C, 0x00000082U ,0x00000002U) - RegMask = (SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_MASK | SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_MASK | 0 ); - - RegVal = ((0x00000000U << SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_SHIFT - | 0x00000001U << SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_L3_REF_CLK_SEL_OFFSET ,0x00000082U ,0x00000002U); - /*############################################################################################################################ */ - - // : ENABLE SPREAD SPECTRUM - /*Register : L2_TM_PLL_DIG_37 @ 0XFD40A094

- - Enable/Disable coarse code satureation limiting logic - PSU_SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION 0x1 - - Test mode register 37 - (OFFSET, MASK, VALUE) (0XFD40A094, 0x00000010U ,0x00000010U) - RegMask = (SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_TM_PLL_DIG_37_OFFSET ,0x00000010U ,0x00000010U); - /*############################################################################################################################ */ - - /*Register : L2_PLL_SS_STEPS_0_LSB @ 0XFD40A368

- - Spread Spectrum No of Steps [7:0] - PSU_SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB 0x38 - - Spread Spectrum No of Steps bits 7:0 - (OFFSET, MASK, VALUE) (0XFD40A368, 0x000000FFU ,0x00000038U) - RegMask = (SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK | 0 ); - - RegVal = ((0x00000038U << SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_PLL_SS_STEPS_0_LSB_OFFSET ,0x000000FFU ,0x00000038U); - /*############################################################################################################################ */ - - /*Register : L2_PLL_SS_STEPS_1_MSB @ 0XFD40A36C

- - Spread Spectrum No of Steps [10:8] - PSU_SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB 0x03 - - Spread Spectrum No of Steps bits 10:8 - (OFFSET, MASK, VALUE) (0XFD40A36C, 0x00000007U ,0x00000003U) - RegMask = (SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK | 0 ); - - RegVal = ((0x00000003U << SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_PLL_SS_STEPS_1_MSB_OFFSET ,0x00000007U ,0x00000003U); - /*############################################################################################################################ */ - - /*Register : L3_PLL_SS_STEPS_0_LSB @ 0XFD40E368

- - Spread Spectrum No of Steps [7:0] - PSU_SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB 0xE0 - - Spread Spectrum No of Steps bits 7:0 - (OFFSET, MASK, VALUE) (0XFD40E368, 0x000000FFU ,0x000000E0U) - RegMask = (SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK | 0 ); - - RegVal = ((0x000000E0U << SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_PLL_SS_STEPS_0_LSB_OFFSET ,0x000000FFU ,0x000000E0U); - /*############################################################################################################################ */ - - /*Register : L3_PLL_SS_STEPS_1_MSB @ 0XFD40E36C

- - Spread Spectrum No of Steps [10:8] - PSU_SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB 0x3 - - Spread Spectrum No of Steps bits 10:8 - (OFFSET, MASK, VALUE) (0XFD40E36C, 0x00000007U ,0x00000003U) - RegMask = (SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK | 0 ); - - RegVal = ((0x00000003U << SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_PLL_SS_STEPS_1_MSB_OFFSET ,0x00000007U ,0x00000003U); - /*############################################################################################################################ */ - - /*Register : L1_PLL_SS_STEPS_0_LSB @ 0XFD406368

- - Spread Spectrum No of Steps [7:0] - PSU_SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB 0x58 - - Spread Spectrum No of Steps bits 7:0 - (OFFSET, MASK, VALUE) (0XFD406368, 0x000000FFU ,0x00000058U) - RegMask = (SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK | 0 ); - - RegVal = ((0x00000058U << SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L1_PLL_SS_STEPS_0_LSB_OFFSET ,0x000000FFU ,0x00000058U); - /*############################################################################################################################ */ - - /*Register : L1_PLL_SS_STEPS_1_MSB @ 0XFD40636C

- - Spread Spectrum No of Steps [10:8] - PSU_SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB 0x3 - - Spread Spectrum No of Steps bits 10:8 - (OFFSET, MASK, VALUE) (0XFD40636C, 0x00000007U ,0x00000003U) - RegMask = (SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK | 0 ); - - RegVal = ((0x00000003U << SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L1_PLL_SS_STEPS_1_MSB_OFFSET ,0x00000007U ,0x00000003U); - /*############################################################################################################################ */ - - /*Register : L1_PLL_SS_STEP_SIZE_0_LSB @ 0XFD406370

- - Step Size for Spread Spectrum [7:0] - PSU_SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB 0x7C - - Step Size for Spread Spectrum LSB - (OFFSET, MASK, VALUE) (0XFD406370, 0x000000FFU ,0x0000007CU) - RegMask = (SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK | 0 ); - - RegVal = ((0x0000007CU << SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_OFFSET ,0x000000FFU ,0x0000007CU); - /*############################################################################################################################ */ - - /*Register : L1_PLL_SS_STEP_SIZE_1 @ 0XFD406374

- - Step Size for Spread Spectrum [15:8] - PSU_SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1 0x33 - - Step Size for Spread Spectrum 1 - (OFFSET, MASK, VALUE) (0XFD406374, 0x000000FFU ,0x00000033U) - RegMask = (SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK | 0 ); - - RegVal = ((0x00000033U << SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L1_PLL_SS_STEP_SIZE_1_OFFSET ,0x000000FFU ,0x00000033U); - /*############################################################################################################################ */ - - /*Register : L1_PLL_SS_STEP_SIZE_2 @ 0XFD406378

- - Step Size for Spread Spectrum [23:16] - PSU_SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2 0x2 - - Step Size for Spread Spectrum 2 - (OFFSET, MASK, VALUE) (0XFD406378, 0x000000FFU ,0x00000002U) - RegMask = (SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK | 0 ); - - RegVal = ((0x00000002U << SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L1_PLL_SS_STEP_SIZE_2_OFFSET ,0x000000FFU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : L1_PLL_SS_STEP_SIZE_3_MSB @ 0XFD40637C

- - Step Size for Spread Spectrum [25:24] - PSU_SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB 0x0 - - Enable/Disable test mode force on SS step size - PSU_SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE 0x1 - - Enable/Disable test mode force on SS no of steps - PSU_SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS 0x1 - - Enable force on enable Spread Spectrum - (OFFSET, MASK, VALUE) (0XFD40637C, 0x00000033U ,0x00000030U) - RegMask = (SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK | SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK | SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK | 0 ); - - RegVal = ((0x00000000U << SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT - | 0x00000001U << SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT - | 0x00000001U << SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_OFFSET ,0x00000033U ,0x00000030U); - /*############################################################################################################################ */ - - /*Register : L2_PLL_SS_STEP_SIZE_0_LSB @ 0XFD40A370

- - Step Size for Spread Spectrum [7:0] - PSU_SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB 0xF4 - - Step Size for Spread Spectrum LSB - (OFFSET, MASK, VALUE) (0XFD40A370, 0x000000FFU ,0x000000F4U) - RegMask = (SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK | 0 ); - - RegVal = ((0x000000F4U << SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_OFFSET ,0x000000FFU ,0x000000F4U); - /*############################################################################################################################ */ - - /*Register : L2_PLL_SS_STEP_SIZE_1 @ 0XFD40A374

- - Step Size for Spread Spectrum [15:8] - PSU_SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1 0x31 - - Step Size for Spread Spectrum 1 - (OFFSET, MASK, VALUE) (0XFD40A374, 0x000000FFU ,0x00000031U) - RegMask = (SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK | 0 ); - - RegVal = ((0x00000031U << SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_PLL_SS_STEP_SIZE_1_OFFSET ,0x000000FFU ,0x00000031U); - /*############################################################################################################################ */ - - /*Register : L2_PLL_SS_STEP_SIZE_2 @ 0XFD40A378

- - Step Size for Spread Spectrum [23:16] - PSU_SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2 0x2 - - Step Size for Spread Spectrum 2 - (OFFSET, MASK, VALUE) (0XFD40A378, 0x000000FFU ,0x00000002U) - RegMask = (SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK | 0 ); - - RegVal = ((0x00000002U << SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_PLL_SS_STEP_SIZE_2_OFFSET ,0x000000FFU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : L2_PLL_SS_STEP_SIZE_3_MSB @ 0XFD40A37C

- - Step Size for Spread Spectrum [25:24] - PSU_SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB 0x0 - - Enable/Disable test mode force on SS step size - PSU_SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE 0x1 - - Enable/Disable test mode force on SS no of steps - PSU_SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS 0x1 - - Enable force on enable Spread Spectrum - (OFFSET, MASK, VALUE) (0XFD40A37C, 0x00000033U ,0x00000030U) - RegMask = (SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK | SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK | SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK | 0 ); - - RegVal = ((0x00000000U << SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT - | 0x00000001U << SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT - | 0x00000001U << SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_OFFSET ,0x00000033U ,0x00000030U); - /*############################################################################################################################ */ - - /*Register : L3_PLL_SS_STEP_SIZE_0_LSB @ 0XFD40E370

- - Step Size for Spread Spectrum [7:0] - PSU_SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB 0xC9 - - Step Size for Spread Spectrum LSB - (OFFSET, MASK, VALUE) (0XFD40E370, 0x000000FFU ,0x000000C9U) - RegMask = (SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK | 0 ); - - RegVal = ((0x000000C9U << SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_OFFSET ,0x000000FFU ,0x000000C9U); - /*############################################################################################################################ */ - - /*Register : L3_PLL_SS_STEP_SIZE_1 @ 0XFD40E374

- - Step Size for Spread Spectrum [15:8] - PSU_SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1 0xD2 - - Step Size for Spread Spectrum 1 - (OFFSET, MASK, VALUE) (0XFD40E374, 0x000000FFU ,0x000000D2U) - RegMask = (SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK | 0 ); - - RegVal = ((0x000000D2U << SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_PLL_SS_STEP_SIZE_1_OFFSET ,0x000000FFU ,0x000000D2U); - /*############################################################################################################################ */ - - /*Register : L3_PLL_SS_STEP_SIZE_2 @ 0XFD40E378

- - Step Size for Spread Spectrum [23:16] - PSU_SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2 0x1 - - Step Size for Spread Spectrum 2 - (OFFSET, MASK, VALUE) (0XFD40E378, 0x000000FFU ,0x00000001U) - RegMask = (SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_PLL_SS_STEP_SIZE_2_OFFSET ,0x000000FFU ,0x00000001U); - /*############################################################################################################################ */ - - /*Register : L3_PLL_SS_STEP_SIZE_3_MSB @ 0XFD40E37C

- - Step Size for Spread Spectrum [25:24] - PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB 0x0 - - Enable/Disable test mode force on SS step size - PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE 0x1 - - Enable/Disable test mode force on SS no of steps - PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS 0x1 - - Enable test mode forcing on enable Spread Spectrum - PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS 0x1 - - Enable force on enable Spread Spectrum - (OFFSET, MASK, VALUE) (0XFD40E37C, 0x000000B3U ,0x000000B0U) - RegMask = (SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK | SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK | SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK | SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_MASK | 0 ); - - RegVal = ((0x00000000U << SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT - | 0x00000001U << SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT - | 0x00000001U << SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT - | 0x00000001U << SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_OFFSET ,0x000000B3U ,0x000000B0U); - /*############################################################################################################################ */ - - /*Register : L2_TM_DIG_6 @ 0XFD40906C

- - Bypass Descrambler - PSU_SERDES_L2_TM_DIG_6_BYPASS_DESCRAM 0x1 - - Enable Bypass for <1> TM_DIG_CTRL_6 - PSU_SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM 0x1 - - Data path test modes in decoder and descram - (OFFSET, MASK, VALUE) (0XFD40906C, 0x00000003U ,0x00000003U) - RegMask = (SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_MASK | SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_SHIFT - | 0x00000001U << SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_TM_DIG_6_OFFSET ,0x00000003U ,0x00000003U); - /*############################################################################################################################ */ - - /*Register : L2_TX_DIG_TM_61 @ 0XFD4080F4

- - Bypass scrambler signal - PSU_SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM 0x1 - - Enable/disable scrambler bypass signal - PSU_SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM 0x1 - - MPHY PLL Gear and bypass scrambler - (OFFSET, MASK, VALUE) (0XFD4080F4, 0x00000003U ,0x00000003U) - RegMask = (SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_MASK | SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_SHIFT - | 0x00000001U << SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_TX_DIG_TM_61_OFFSET ,0x00000003U ,0x00000003U); - /*############################################################################################################################ */ - - /*Register : L3_PLL_FBDIV_FRAC_3_MSB @ 0XFD40E360

- - Enable test mode force on fractional mode enable - PSU_SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC 0x1 - - Fractional feedback division control and fractional value for feedback division bits 26:24 - (OFFSET, MASK, VALUE) (0XFD40E360, 0x00000040U ,0x00000040U) - RegMask = (SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_PLL_FBDIV_FRAC_3_MSB_OFFSET ,0x00000040U ,0x00000040U); - /*############################################################################################################################ */ - - /*Register : L3_TM_DIG_6 @ 0XFD40D06C

- - Bypass 8b10b decoder - PSU_SERDES_L3_TM_DIG_6_BYPASS_DECODER 0x1 - - Enable Bypass for <3> TM_DIG_CTRL_6 - PSU_SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC 0x1 - - Bypass Descrambler - PSU_SERDES_L3_TM_DIG_6_BYPASS_DESCRAM 0x1 - - Enable Bypass for <1> TM_DIG_CTRL_6 - PSU_SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM 0x1 - - Data path test modes in decoder and descram - (OFFSET, MASK, VALUE) (0XFD40D06C, 0x0000000FU ,0x0000000FU) - RegMask = (SERDES_L3_TM_DIG_6_BYPASS_DECODER_MASK | SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_MASK | SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_MASK | SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L3_TM_DIG_6_BYPASS_DECODER_SHIFT - | 0x00000001U << SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_SHIFT - | 0x00000001U << SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_SHIFT - | 0x00000001U << SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_DIG_6_OFFSET ,0x0000000FU ,0x0000000FU); - /*############################################################################################################################ */ - - /*Register : L3_TX_DIG_TM_61 @ 0XFD40C0F4

- - Enable/disable encoder bypass signal - PSU_SERDES_L3_TX_DIG_TM_61_BYPASS_ENC 0x1 - - Bypass scrambler signal - PSU_SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM 0x1 - - Enable/disable scrambler bypass signal - PSU_SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM 0x1 - - MPHY PLL Gear and bypass scrambler - (OFFSET, MASK, VALUE) (0XFD40C0F4, 0x0000000BU ,0x0000000BU) - RegMask = (SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_MASK | SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_MASK | SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_SHIFT - | 0x00000001U << SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_SHIFT - | 0x00000001U << SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TX_DIG_TM_61_OFFSET ,0x0000000BU ,0x0000000BU); - /*############################################################################################################################ */ - - /*Register : L3_TXPMA_ST_0 @ 0XFD40CB00

- - PHY Mode: 4'b000 - PCIe, 4'b001 - USB3, 4'b0010 - SATA, 4'b0100 - SGMII, 4'b0101 - DP, 4'b1000 - MPHY - PSU_SERDES_L3_TXPMA_ST_0_TX_PHY_MODE 0x21 - - Opmode Info - (OFFSET, MASK, VALUE) (0XFD40CB00, 0x000000F0U ,0x000000F0U) - RegMask = (SERDES_L3_TXPMA_ST_0_TX_PHY_MODE_MASK | 0 ); - - RegVal = ((0x00000021U << SERDES_L3_TXPMA_ST_0_TX_PHY_MODE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TXPMA_ST_0_OFFSET ,0x000000F0U ,0x000000F0U); - /*############################################################################################################################ */ - - // : ENABLE CHICKEN BIT FOR PCIE AND USB - /*Register : L0_TM_AUX_0 @ 0XFD4010CC

- - Spare- not used - PSU_SERDES_L0_TM_AUX_0_BIT_2 1 - - Spare registers - (OFFSET, MASK, VALUE) (0XFD4010CC, 0x00000020U ,0x00000020U) - RegMask = (SERDES_L0_TM_AUX_0_BIT_2_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L0_TM_AUX_0_BIT_2_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_TM_AUX_0_OFFSET ,0x00000020U ,0x00000020U); - /*############################################################################################################################ */ - - /*Register : L2_TM_AUX_0 @ 0XFD4090CC

- - Spare- not used - PSU_SERDES_L2_TM_AUX_0_BIT_2 1 - - Spare registers - (OFFSET, MASK, VALUE) (0XFD4090CC, 0x00000020U ,0x00000020U) - RegMask = (SERDES_L2_TM_AUX_0_BIT_2_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L2_TM_AUX_0_BIT_2_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_TM_AUX_0_OFFSET ,0x00000020U ,0x00000020U); - /*############################################################################################################################ */ - - // : ENABLING EYE SURF - /*Register : L0_TM_DIG_8 @ 0XFD401074

- - Enable Eye Surf - PSU_SERDES_L0_TM_DIG_8_EYESURF_ENABLE 0x1 - - Test modes for Elastic buffer and enabling Eye Surf - (OFFSET, MASK, VALUE) (0XFD401074, 0x00000010U ,0x00000010U) - RegMask = (SERDES_L0_TM_DIG_8_EYESURF_ENABLE_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L0_TM_DIG_8_EYESURF_ENABLE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_TM_DIG_8_OFFSET ,0x00000010U ,0x00000010U); - /*############################################################################################################################ */ - - /*Register : L1_TM_DIG_8 @ 0XFD405074

- - Enable Eye Surf - PSU_SERDES_L1_TM_DIG_8_EYESURF_ENABLE 0x1 - - Test modes for Elastic buffer and enabling Eye Surf - (OFFSET, MASK, VALUE) (0XFD405074, 0x00000010U ,0x00000010U) - RegMask = (SERDES_L1_TM_DIG_8_EYESURF_ENABLE_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L1_TM_DIG_8_EYESURF_ENABLE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L1_TM_DIG_8_OFFSET ,0x00000010U ,0x00000010U); - /*############################################################################################################################ */ - - /*Register : L2_TM_DIG_8 @ 0XFD409074

- - Enable Eye Surf - PSU_SERDES_L2_TM_DIG_8_EYESURF_ENABLE 0x1 - - Test modes for Elastic buffer and enabling Eye Surf - (OFFSET, MASK, VALUE) (0XFD409074, 0x00000010U ,0x00000010U) - RegMask = (SERDES_L2_TM_DIG_8_EYESURF_ENABLE_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L2_TM_DIG_8_EYESURF_ENABLE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_TM_DIG_8_OFFSET ,0x00000010U ,0x00000010U); - /*############################################################################################################################ */ - - /*Register : L3_TM_DIG_8 @ 0XFD40D074

- - Enable Eye Surf - PSU_SERDES_L3_TM_DIG_8_EYESURF_ENABLE 0x1 - - Test modes for Elastic buffer and enabling Eye Surf - (OFFSET, MASK, VALUE) (0XFD40D074, 0x00000010U ,0x00000010U) - RegMask = (SERDES_L3_TM_DIG_8_EYESURF_ENABLE_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L3_TM_DIG_8_EYESURF_ENABLE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_DIG_8_OFFSET ,0x00000010U ,0x00000010U); - /*############################################################################################################################ */ - - // : ILL SETTINGS FOR GAIN AND LOCK SETTINGS - /*Register : L0_TM_MISC2 @ 0XFD40189C

- - ILL calib counts BYPASSED with calcode bits - PSU_SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS 0x1 - - sampler cal - (OFFSET, MASK, VALUE) (0XFD40189C, 0x00000080U ,0x00000080U) - RegMask = (SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_TM_MISC2_OFFSET ,0x00000080U ,0x00000080U); - /*############################################################################################################################ */ - - /*Register : L0_TM_IQ_ILL1 @ 0XFD4018F8

- - IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS - PSU_SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0 0x64 - - iqpi cal code - (OFFSET, MASK, VALUE) (0XFD4018F8, 0x000000FFU ,0x00000064U) - RegMask = (SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK | 0 ); - - RegVal = ((0x00000064U << SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_TM_IQ_ILL1_OFFSET ,0x000000FFU ,0x00000064U); - /*############################################################################################################################ */ - - /*Register : L0_TM_IQ_ILL2 @ 0XFD4018FC

- - IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 - PSU_SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1 0x64 - - iqpi cal code - (OFFSET, MASK, VALUE) (0XFD4018FC, 0x000000FFU ,0x00000064U) - RegMask = (SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK | 0 ); - - RegVal = ((0x00000064U << SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_TM_IQ_ILL2_OFFSET ,0x000000FFU ,0x00000064U); - /*############################################################################################################################ */ - - /*Register : L0_TM_ILL12 @ 0XFD401990

- - G1A pll ctr bypass value - PSU_SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL 0x11 - - ill pll counter values - (OFFSET, MASK, VALUE) (0XFD401990, 0x000000FFU ,0x00000011U) - RegMask = (SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK | 0 ); - - RegVal = ((0x00000011U << SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_TM_ILL12_OFFSET ,0x000000FFU ,0x00000011U); - /*############################################################################################################################ */ - - /*Register : L0_TM_E_ILL1 @ 0XFD401924

- - E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS - PSU_SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0 0x4 - - epi cal code - (OFFSET, MASK, VALUE) (0XFD401924, 0x000000FFU ,0x00000004U) - RegMask = (SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK | 0 ); - - RegVal = ((0x00000004U << SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_TM_E_ILL1_OFFSET ,0x000000FFU ,0x00000004U); - /*############################################################################################################################ */ - - /*Register : L0_TM_E_ILL2 @ 0XFD401928

- - E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 - PSU_SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1 0xFE - - epi cal code - (OFFSET, MASK, VALUE) (0XFD401928, 0x000000FFU ,0x000000FEU) - RegMask = (SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK | 0 ); - - RegVal = ((0x000000FEU << SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_TM_E_ILL2_OFFSET ,0x000000FFU ,0x000000FEU); - /*############################################################################################################################ */ - - /*Register : L0_TM_IQ_ILL3 @ 0XFD401900

- - IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 - PSU_SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2 0x64 - - iqpi cal code - (OFFSET, MASK, VALUE) (0XFD401900, 0x000000FFU ,0x00000064U) - RegMask = (SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK | 0 ); - - RegVal = ((0x00000064U << SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_TM_IQ_ILL3_OFFSET ,0x000000FFU ,0x00000064U); - /*############################################################################################################################ */ - - /*Register : L0_TM_E_ILL3 @ 0XFD40192C

- - E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 - PSU_SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2 0x0 - - epi cal code - (OFFSET, MASK, VALUE) (0XFD40192C, 0x000000FFU ,0x00000000U) - RegMask = (SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK | 0 ); - - RegVal = ((0x00000000U << SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_TM_E_ILL3_OFFSET ,0x000000FFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : L0_TM_ILL8 @ 0XFD401980

- - ILL calibration code change wait time - PSU_SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT 0xFF - - ILL cal routine control - (OFFSET, MASK, VALUE) (0XFD401980, 0x000000FFU ,0x000000FFU) - RegMask = (SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_MASK | 0 ); - - RegVal = ((0x000000FFU << SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_TM_ILL8_OFFSET ,0x000000FFU ,0x000000FFU); - /*############################################################################################################################ */ - - /*Register : L0_TM_IQ_ILL8 @ 0XFD401914

- - IQ ILL polytrim bypass value - PSU_SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL 0xF7 - - iqpi polytrim - (OFFSET, MASK, VALUE) (0XFD401914, 0x000000FFU ,0x000000F7U) - RegMask = (SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK | 0 ); - - RegVal = ((0x000000F7U << SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_TM_IQ_ILL8_OFFSET ,0x000000FFU ,0x000000F7U); - /*############################################################################################################################ */ - - /*Register : L0_TM_IQ_ILL9 @ 0XFD401918

- - bypass IQ polytrim - PSU_SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM 0x1 - - enables for lf,constant gm trim and polytirm - (OFFSET, MASK, VALUE) (0XFD401918, 0x00000001U ,0x00000001U) - RegMask = (SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_TM_IQ_ILL9_OFFSET ,0x00000001U ,0x00000001U); - /*############################################################################################################################ */ - - /*Register : L0_TM_E_ILL8 @ 0XFD401940

- - E ILL polytrim bypass value - PSU_SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL 0xF7 - - epi polytrim - (OFFSET, MASK, VALUE) (0XFD401940, 0x000000FFU ,0x000000F7U) - RegMask = (SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK | 0 ); - - RegVal = ((0x000000F7U << SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_TM_E_ILL8_OFFSET ,0x000000FFU ,0x000000F7U); - /*############################################################################################################################ */ - - /*Register : L0_TM_E_ILL9 @ 0XFD401944

- - bypass E polytrim - PSU_SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM 0x1 - - enables for lf,constant gm trim and polytirm - (OFFSET, MASK, VALUE) (0XFD401944, 0x00000001U ,0x00000001U) - RegMask = (SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_TM_E_ILL9_OFFSET ,0x00000001U ,0x00000001U); - /*############################################################################################################################ */ - - /*Register : L2_TM_MISC2 @ 0XFD40989C

- - ILL calib counts BYPASSED with calcode bits - PSU_SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS 0x1 - - sampler cal - (OFFSET, MASK, VALUE) (0XFD40989C, 0x00000080U ,0x00000080U) - RegMask = (SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_TM_MISC2_OFFSET ,0x00000080U ,0x00000080U); - /*############################################################################################################################ */ - - /*Register : L2_TM_IQ_ILL1 @ 0XFD4098F8

- - IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS - PSU_SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0 0x1A - - iqpi cal code - (OFFSET, MASK, VALUE) (0XFD4098F8, 0x000000FFU ,0x0000001AU) - RegMask = (SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK | 0 ); - - RegVal = ((0x0000001AU << SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_TM_IQ_ILL1_OFFSET ,0x000000FFU ,0x0000001AU); - /*############################################################################################################################ */ - - /*Register : L2_TM_IQ_ILL2 @ 0XFD4098FC

- - IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 - PSU_SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1 0x1A - - iqpi cal code - (OFFSET, MASK, VALUE) (0XFD4098FC, 0x000000FFU ,0x0000001AU) - RegMask = (SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK | 0 ); - - RegVal = ((0x0000001AU << SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_TM_IQ_ILL2_OFFSET ,0x000000FFU ,0x0000001AU); - /*############################################################################################################################ */ - - /*Register : L2_TM_ILL12 @ 0XFD409990

- - G1A pll ctr bypass value - PSU_SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL 0x10 - - ill pll counter values - (OFFSET, MASK, VALUE) (0XFD409990, 0x000000FFU ,0x00000010U) - RegMask = (SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK | 0 ); - - RegVal = ((0x00000010U << SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_TM_ILL12_OFFSET ,0x000000FFU ,0x00000010U); - /*############################################################################################################################ */ - - /*Register : L2_TM_E_ILL1 @ 0XFD409924

- - E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS - PSU_SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0 0xFE - - epi cal code - (OFFSET, MASK, VALUE) (0XFD409924, 0x000000FFU ,0x000000FEU) - RegMask = (SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK | 0 ); - - RegVal = ((0x000000FEU << SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_TM_E_ILL1_OFFSET ,0x000000FFU ,0x000000FEU); - /*############################################################################################################################ */ - - /*Register : L2_TM_E_ILL2 @ 0XFD409928

- - E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 - PSU_SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1 0x0 - - epi cal code - (OFFSET, MASK, VALUE) (0XFD409928, 0x000000FFU ,0x00000000U) - RegMask = (SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK | 0 ); - - RegVal = ((0x00000000U << SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_TM_E_ILL2_OFFSET ,0x000000FFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : L2_TM_IQ_ILL3 @ 0XFD409900

- - IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 - PSU_SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2 0x1A - - iqpi cal code - (OFFSET, MASK, VALUE) (0XFD409900, 0x000000FFU ,0x0000001AU) - RegMask = (SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK | 0 ); - - RegVal = ((0x0000001AU << SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_TM_IQ_ILL3_OFFSET ,0x000000FFU ,0x0000001AU); - /*############################################################################################################################ */ - - /*Register : L2_TM_E_ILL3 @ 0XFD40992C

- - E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 - PSU_SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2 0x0 - - epi cal code - (OFFSET, MASK, VALUE) (0XFD40992C, 0x000000FFU ,0x00000000U) - RegMask = (SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK | 0 ); - - RegVal = ((0x00000000U << SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_TM_E_ILL3_OFFSET ,0x000000FFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : L2_TM_ILL8 @ 0XFD409980

- - ILL calibration code change wait time - PSU_SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT 0xFF - - ILL cal routine control - (OFFSET, MASK, VALUE) (0XFD409980, 0x000000FFU ,0x000000FFU) - RegMask = (SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_MASK | 0 ); - - RegVal = ((0x000000FFU << SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_TM_ILL8_OFFSET ,0x000000FFU ,0x000000FFU); - /*############################################################################################################################ */ - - /*Register : L2_TM_IQ_ILL8 @ 0XFD409914

- - IQ ILL polytrim bypass value - PSU_SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL 0xF7 - - iqpi polytrim - (OFFSET, MASK, VALUE) (0XFD409914, 0x000000FFU ,0x000000F7U) - RegMask = (SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK | 0 ); - - RegVal = ((0x000000F7U << SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_TM_IQ_ILL8_OFFSET ,0x000000FFU ,0x000000F7U); - /*############################################################################################################################ */ - - /*Register : L2_TM_IQ_ILL9 @ 0XFD409918

- - bypass IQ polytrim - PSU_SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM 0x1 - - enables for lf,constant gm trim and polytirm - (OFFSET, MASK, VALUE) (0XFD409918, 0x00000001U ,0x00000001U) - RegMask = (SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_TM_IQ_ILL9_OFFSET ,0x00000001U ,0x00000001U); - /*############################################################################################################################ */ - - /*Register : L2_TM_E_ILL8 @ 0XFD409940

- - E ILL polytrim bypass value - PSU_SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL 0xF7 - - epi polytrim - (OFFSET, MASK, VALUE) (0XFD409940, 0x000000FFU ,0x000000F7U) - RegMask = (SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK | 0 ); - - RegVal = ((0x000000F7U << SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_TM_E_ILL8_OFFSET ,0x000000FFU ,0x000000F7U); - /*############################################################################################################################ */ - - /*Register : L2_TM_E_ILL9 @ 0XFD409944

- - bypass E polytrim - PSU_SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM 0x1 - - enables for lf,constant gm trim and polytirm - (OFFSET, MASK, VALUE) (0XFD409944, 0x00000001U ,0x00000001U) - RegMask = (SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_TM_E_ILL9_OFFSET ,0x00000001U ,0x00000001U); - /*############################################################################################################################ */ - - /*Register : L3_TM_MISC2 @ 0XFD40D89C

- - ILL calib counts BYPASSED with calcode bits - PSU_SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS 0x1 - - sampler cal - (OFFSET, MASK, VALUE) (0XFD40D89C, 0x00000080U ,0x00000080U) - RegMask = (SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_MISC2_OFFSET ,0x00000080U ,0x00000080U); - /*############################################################################################################################ */ - - /*Register : L3_TM_IQ_ILL1 @ 0XFD40D8F8

- - IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS - PSU_SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0 0x7D - - iqpi cal code - (OFFSET, MASK, VALUE) (0XFD40D8F8, 0x000000FFU ,0x0000007DU) - RegMask = (SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK | 0 ); - - RegVal = ((0x0000007DU << SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_IQ_ILL1_OFFSET ,0x000000FFU ,0x0000007DU); - /*############################################################################################################################ */ - - /*Register : L3_TM_IQ_ILL2 @ 0XFD40D8FC

- - IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 - PSU_SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1 0x7D - - iqpi cal code - (OFFSET, MASK, VALUE) (0XFD40D8FC, 0x000000FFU ,0x0000007DU) - RegMask = (SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK | 0 ); - - RegVal = ((0x0000007DU << SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_IQ_ILL2_OFFSET ,0x000000FFU ,0x0000007DU); - /*############################################################################################################################ */ - - /*Register : L3_TM_ILL12 @ 0XFD40D990

- - G1A pll ctr bypass value - PSU_SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL 0x1 - - ill pll counter values - (OFFSET, MASK, VALUE) (0XFD40D990, 0x000000FFU ,0x00000001U) - RegMask = (SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_ILL12_OFFSET ,0x000000FFU ,0x00000001U); - /*############################################################################################################################ */ - - /*Register : L3_TM_E_ILL1 @ 0XFD40D924

- - E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS - PSU_SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0 0x9C - - epi cal code - (OFFSET, MASK, VALUE) (0XFD40D924, 0x000000FFU ,0x0000009CU) - RegMask = (SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK | 0 ); - - RegVal = ((0x0000009CU << SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_E_ILL1_OFFSET ,0x000000FFU ,0x0000009CU); - /*############################################################################################################################ */ - - /*Register : L3_TM_E_ILL2 @ 0XFD40D928

- - E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 - PSU_SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1 0x39 - - epi cal code - (OFFSET, MASK, VALUE) (0XFD40D928, 0x000000FFU ,0x00000039U) - RegMask = (SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK | 0 ); - - RegVal = ((0x00000039U << SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_E_ILL2_OFFSET ,0x000000FFU ,0x00000039U); - /*############################################################################################################################ */ - - /*Register : L3_TM_ILL11 @ 0XFD40D98C

- - G2A_PCIe1 PLL ctr bypass value - PSU_SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL 0x2 - - ill pll counter values - (OFFSET, MASK, VALUE) (0XFD40D98C, 0x000000F0U ,0x00000020U) - RegMask = (SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_MASK | 0 ); - - RegVal = ((0x00000002U << SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_ILL11_OFFSET ,0x000000F0U ,0x00000020U); - /*############################################################################################################################ */ - - /*Register : L3_TM_IQ_ILL3 @ 0XFD40D900

- - IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 - PSU_SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2 0x7D - - iqpi cal code - (OFFSET, MASK, VALUE) (0XFD40D900, 0x000000FFU ,0x0000007DU) - RegMask = (SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK | 0 ); - - RegVal = ((0x0000007DU << SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_IQ_ILL3_OFFSET ,0x000000FFU ,0x0000007DU); - /*############################################################################################################################ */ - - /*Register : L3_TM_E_ILL3 @ 0XFD40D92C

- - E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 - PSU_SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2 0x64 - - epi cal code - (OFFSET, MASK, VALUE) (0XFD40D92C, 0x000000FFU ,0x00000064U) - RegMask = (SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK | 0 ); - - RegVal = ((0x00000064U << SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_E_ILL3_OFFSET ,0x000000FFU ,0x00000064U); - /*############################################################################################################################ */ - - /*Register : L3_TM_ILL8 @ 0XFD40D980

- - ILL calibration code change wait time - PSU_SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT 0xFF - - ILL cal routine control - (OFFSET, MASK, VALUE) (0XFD40D980, 0x000000FFU ,0x000000FFU) - RegMask = (SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_MASK | 0 ); - - RegVal = ((0x000000FFU << SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_ILL8_OFFSET ,0x000000FFU ,0x000000FFU); - /*############################################################################################################################ */ - - /*Register : L3_TM_IQ_ILL8 @ 0XFD40D914

- - IQ ILL polytrim bypass value - PSU_SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL 0xF7 - - iqpi polytrim - (OFFSET, MASK, VALUE) (0XFD40D914, 0x000000FFU ,0x000000F7U) - RegMask = (SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK | 0 ); - - RegVal = ((0x000000F7U << SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_IQ_ILL8_OFFSET ,0x000000FFU ,0x000000F7U); - /*############################################################################################################################ */ - - /*Register : L3_TM_IQ_ILL9 @ 0XFD40D918

- - bypass IQ polytrim - PSU_SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM 0x1 - - enables for lf,constant gm trim and polytirm - (OFFSET, MASK, VALUE) (0XFD40D918, 0x00000001U ,0x00000001U) - RegMask = (SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_IQ_ILL9_OFFSET ,0x00000001U ,0x00000001U); - /*############################################################################################################################ */ - - /*Register : L3_TM_E_ILL8 @ 0XFD40D940

- - E ILL polytrim bypass value - PSU_SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL 0xF7 - - epi polytrim - (OFFSET, MASK, VALUE) (0XFD40D940, 0x000000FFU ,0x000000F7U) - RegMask = (SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK | 0 ); - - RegVal = ((0x000000F7U << SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_E_ILL8_OFFSET ,0x000000FFU ,0x000000F7U); - /*############################################################################################################################ */ - - /*Register : L3_TM_E_ILL9 @ 0XFD40D944

- - bypass E polytrim - PSU_SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM 0x1 - - enables for lf,constant gm trim and polytirm - (OFFSET, MASK, VALUE) (0XFD40D944, 0x00000001U ,0x00000001U) - RegMask = (SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_E_ILL9_OFFSET ,0x00000001U ,0x00000001U); - /*############################################################################################################################ */ - - // : SYMBOL LOCK AND WAIT - /*Register : L0_TM_DIG_21 @ 0XFD4010A8

- - pre lock comma count threshold. 2'b 00 : 3, 2'b 01 : 5, 2'b 10 : 10, 2'b 11 : 20 - PSU_SERDES_L0_TM_DIG_21_COMMA_PRE_LOCK_THRESH 0x11 - - Control symbol alignment locking - wait counts - (OFFSET, MASK, VALUE) (0XFD4010A8, 0x00000003U ,0x00000003U) - RegMask = (SERDES_L0_TM_DIG_21_COMMA_PRE_LOCK_THRESH_MASK | 0 ); - - RegVal = ((0x00000011U << SERDES_L0_TM_DIG_21_COMMA_PRE_LOCK_THRESH_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_TM_DIG_21_OFFSET ,0x00000003U ,0x00000003U); - /*############################################################################################################################ */ - - /*Register : L0_TM_DIG_10 @ 0XFD40107C

- - CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001 - PSU_SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME 0xF - - test control for changing cdr lock wait time - (OFFSET, MASK, VALUE) (0XFD40107C, 0x0000000FU ,0x0000000FU) - RegMask = (SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK | 0 ); - - RegVal = ((0x0000000FU << SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_TM_DIG_10_OFFSET ,0x0000000FU ,0x0000000FU); - /*############################################################################################################################ */ - - // : SIOU SETTINGS FOR BYPASS CONTROL,HSRX-DIG - /*Register : L0_TM_RST_DLY @ 0XFD4019A4

- - Delay apb reset by specified amount - PSU_SERDES_L0_TM_RST_DLY_APB_RST_DLY 0xFF - - reset delay for apb reset w.r.t pso of hsrx - (OFFSET, MASK, VALUE) (0XFD4019A4, 0x000000FFU ,0x000000FFU) - RegMask = (SERDES_L0_TM_RST_DLY_APB_RST_DLY_MASK | 0 ); - - RegVal = ((0x000000FFU << SERDES_L0_TM_RST_DLY_APB_RST_DLY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_TM_RST_DLY_OFFSET ,0x000000FFU ,0x000000FFU); - /*############################################################################################################################ */ - - /*Register : L0_TM_ANA_BYP_15 @ 0XFD401038

- - Enable Bypass for <7> of TM_ANA_BYPS_15 - PSU_SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE 0x1 - - Bypass control for pcs-pma interface. EQ supplies, main master supply and ps for samp c2c - (OFFSET, MASK, VALUE) (0XFD401038, 0x00000040U ,0x00000040U) - RegMask = (SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_TM_ANA_BYP_15_OFFSET ,0x00000040U ,0x00000040U); - /*############################################################################################################################ */ - - /*Register : L0_TM_ANA_BYP_12 @ 0XFD40102C

- - Enable Bypass for <7> of TM_ANA_BYPS_12 - PSU_SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG 0x1 - - Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr enable controls - (OFFSET, MASK, VALUE) (0XFD40102C, 0x00000040U ,0x00000040U) - RegMask = (SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_TM_ANA_BYP_12_OFFSET ,0x00000040U ,0x00000040U); - /*############################################################################################################################ */ - - /*Register : L1_TM_RST_DLY @ 0XFD4059A4

- - Delay apb reset by specified amount - PSU_SERDES_L1_TM_RST_DLY_APB_RST_DLY 0xFF - - reset delay for apb reset w.r.t pso of hsrx - (OFFSET, MASK, VALUE) (0XFD4059A4, 0x000000FFU ,0x000000FFU) - RegMask = (SERDES_L1_TM_RST_DLY_APB_RST_DLY_MASK | 0 ); - - RegVal = ((0x000000FFU << SERDES_L1_TM_RST_DLY_APB_RST_DLY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L1_TM_RST_DLY_OFFSET ,0x000000FFU ,0x000000FFU); - /*############################################################################################################################ */ - - /*Register : L1_TM_ANA_BYP_15 @ 0XFD405038

- - Enable Bypass for <7> of TM_ANA_BYPS_15 - PSU_SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE 0x1 - - Bypass control for pcs-pma interface. EQ supplies, main master supply and ps for samp c2c - (OFFSET, MASK, VALUE) (0XFD405038, 0x00000040U ,0x00000040U) - RegMask = (SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L1_TM_ANA_BYP_15_OFFSET ,0x00000040U ,0x00000040U); - /*############################################################################################################################ */ - - /*Register : L1_TM_ANA_BYP_12 @ 0XFD40502C

- - Enable Bypass for <7> of TM_ANA_BYPS_12 - PSU_SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG 0x1 - - Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr enable controls - (OFFSET, MASK, VALUE) (0XFD40502C, 0x00000040U ,0x00000040U) - RegMask = (SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L1_TM_ANA_BYP_12_OFFSET ,0x00000040U ,0x00000040U); - /*############################################################################################################################ */ - - /*Register : L2_TM_RST_DLY @ 0XFD4099A4

- - Delay apb reset by specified amount - PSU_SERDES_L2_TM_RST_DLY_APB_RST_DLY 0xFF - - reset delay for apb reset w.r.t pso of hsrx - (OFFSET, MASK, VALUE) (0XFD4099A4, 0x000000FFU ,0x000000FFU) - RegMask = (SERDES_L2_TM_RST_DLY_APB_RST_DLY_MASK | 0 ); - - RegVal = ((0x000000FFU << SERDES_L2_TM_RST_DLY_APB_RST_DLY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_TM_RST_DLY_OFFSET ,0x000000FFU ,0x000000FFU); - /*############################################################################################################################ */ - - /*Register : L2_TM_ANA_BYP_15 @ 0XFD409038

- - Enable Bypass for <7> of TM_ANA_BYPS_15 - PSU_SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE 0x1 - - Bypass control for pcs-pma interface. EQ supplies, main master supply and ps for samp c2c - (OFFSET, MASK, VALUE) (0XFD409038, 0x00000040U ,0x00000040U) - RegMask = (SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_TM_ANA_BYP_15_OFFSET ,0x00000040U ,0x00000040U); - /*############################################################################################################################ */ - - /*Register : L2_TM_ANA_BYP_12 @ 0XFD40902C

- - Enable Bypass for <7> of TM_ANA_BYPS_12 - PSU_SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG 0x1 - - Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr enable controls - (OFFSET, MASK, VALUE) (0XFD40902C, 0x00000040U ,0x00000040U) - RegMask = (SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_TM_ANA_BYP_12_OFFSET ,0x00000040U ,0x00000040U); - /*############################################################################################################################ */ - - /*Register : L3_TM_RST_DLY @ 0XFD40D9A4

- - Delay apb reset by specified amount - PSU_SERDES_L3_TM_RST_DLY_APB_RST_DLY 0xFF - - reset delay for apb reset w.r.t pso of hsrx - (OFFSET, MASK, VALUE) (0XFD40D9A4, 0x000000FFU ,0x000000FFU) - RegMask = (SERDES_L3_TM_RST_DLY_APB_RST_DLY_MASK | 0 ); - - RegVal = ((0x000000FFU << SERDES_L3_TM_RST_DLY_APB_RST_DLY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_RST_DLY_OFFSET ,0x000000FFU ,0x000000FFU); - /*############################################################################################################################ */ - - /*Register : L3_TM_ANA_BYP_15 @ 0XFD40D038

- - Enable Bypass for <7> of TM_ANA_BYPS_15 - PSU_SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE 0x1 - - Bypass control for pcs-pma interface. EQ supplies, main master supply and ps for samp c2c - (OFFSET, MASK, VALUE) (0XFD40D038, 0x00000040U ,0x00000040U) - RegMask = (SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_ANA_BYP_15_OFFSET ,0x00000040U ,0x00000040U); - /*############################################################################################################################ */ - - /*Register : L3_TM_ANA_BYP_12 @ 0XFD40D02C

- - Enable Bypass for <7> of TM_ANA_BYPS_12 - PSU_SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG 0x1 - - Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr enable controls - (OFFSET, MASK, VALUE) (0XFD40D02C, 0x00000040U ,0x00000040U) - RegMask = (SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_ANA_BYP_12_OFFSET ,0x00000040U ,0x00000040U); - /*############################################################################################################################ */ - - // : GT LANE SETTINGS - /*Register : ICM_CFG0 @ 0XFD410010

- - Controls UPHY Lane 0 protocol configuration. 0 - PowerDown, 1 - PCIe .0, 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII0, 6 - Unuse - , 7 - Unused - PSU_SERDES_ICM_CFG0_L0_ICM_CFG 1 - - Controls UPHY Lane 1 protocol configuration. 0 - PowerDown, 1 - PCIe.1, 2 - Sata1, 3 - USB0, 4 - DP.0, 5 - SGMII1, 6 - Unused - 7 - Unused - PSU_SERDES_ICM_CFG0_L1_ICM_CFG 4 - - ICM Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD410010, 0x00000077U ,0x00000041U) - RegMask = (SERDES_ICM_CFG0_L0_ICM_CFG_MASK | SERDES_ICM_CFG0_L1_ICM_CFG_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_ICM_CFG0_L0_ICM_CFG_SHIFT - | 0x00000004U << SERDES_ICM_CFG0_L1_ICM_CFG_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_ICM_CFG0_OFFSET ,0x00000077U ,0x00000041U); - /*############################################################################################################################ */ - - /*Register : ICM_CFG1 @ 0XFD410014

- - Controls UPHY Lane 2 protocol configuration. 0 - PowerDown, 1 - PCIe.1, 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII2, 6 - Unused - 7 - Unused - PSU_SERDES_ICM_CFG1_L2_ICM_CFG 3 - - Controls UPHY Lane 3 protocol configuration. 0 - PowerDown, 1 - PCIe.3, 2 - Sata1, 3 - USB1, 4 - DP.0, 5 - SGMII3, 6 - Unused - 7 - Unused - PSU_SERDES_ICM_CFG1_L3_ICM_CFG 2 - - ICM Configuration Register 1 - (OFFSET, MASK, VALUE) (0XFD410014, 0x00000077U ,0x00000023U) - RegMask = (SERDES_ICM_CFG1_L2_ICM_CFG_MASK | SERDES_ICM_CFG1_L3_ICM_CFG_MASK | 0 ); - - RegVal = ((0x00000003U << SERDES_ICM_CFG1_L2_ICM_CFG_SHIFT - | 0x00000002U << SERDES_ICM_CFG1_L3_ICM_CFG_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_ICM_CFG1_OFFSET ,0x00000077U ,0x00000023U); - /*############################################################################################################################ */ - - // : CHECKING PLL LOCK - // : ENABLE SERIAL DATA MUX DEEMPH - /*Register : L1_TXPMD_TM_45 @ 0XFD404CB4

- - Enable/disable DP post2 path - PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH 0x1 - - Override enable/disable of DP post2 path - PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH 0x1 - - Override enable/disable of DP post1 path - PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH 0x1 - - Enable/disable DP main path - PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH 0x1 - - Override enable/disable of DP main path - PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH 0x1 - - Post or pre or main DP path selection - (OFFSET, MASK, VALUE) (0XFD404CB4, 0x00000037U ,0x00000037U) - RegMask = (SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_MASK | SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_MASK | SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_MASK | SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_MASK | SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_SHIFT - | 0x00000001U << SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_SHIFT - | 0x00000001U << SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_SHIFT - | 0x00000001U << SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_SHIFT - | 0x00000001U << SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L1_TXPMD_TM_45_OFFSET ,0x00000037U ,0x00000037U); - /*############################################################################################################################ */ - - /*Register : L1_TX_ANA_TM_118 @ 0XFD4041D8

- - Test register force for enabling/disablign TX deemphasis bits <17:0> - PSU_SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0 0x1 - - Enable Override of TX deemphasis - (OFFSET, MASK, VALUE) (0XFD4041D8, 0x00000001U ,0x00000001U) - RegMask = (SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L1_TX_ANA_TM_118_OFFSET ,0x00000001U ,0x00000001U); - /*############################################################################################################################ */ - - /*Register : L3_TX_ANA_TM_118 @ 0XFD40C1D8

- - Test register force for enabling/disablign TX deemphasis bits <17:0> - PSU_SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0 0x1 - - Enable Override of TX deemphasis - (OFFSET, MASK, VALUE) (0XFD40C1D8, 0x00000001U ,0x00000001U) - RegMask = (SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TX_ANA_TM_118_OFFSET ,0x00000001U ,0x00000001U); - /*############################################################################################################################ */ - - // : CDR AND RX EQUALIZATION SETTINGS - /*Register : L3_TM_CDR5 @ 0XFD40DC14

- - FPHL FSM accumulate cycles - PSU_SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES 0x7 - - FFL Phase0 int gain aka 2ol SD update rate - PSU_SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN 0x6 - - Fast phase lock controls -- FSM accumulator cycle control and phase 0 int gain control. - (OFFSET, MASK, VALUE) (0XFD40DC14, 0x000000FFU ,0x000000E6U) - RegMask = (SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_MASK | SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_MASK | 0 ); - - RegVal = ((0x00000007U << SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_SHIFT - | 0x00000006U << SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_CDR5_OFFSET ,0x000000FFU ,0x000000E6U); - /*############################################################################################################################ */ - - /*Register : L3_TM_CDR16 @ 0XFD40DC40

- - FFL Phase0 prop gain aka 1ol SD update rate - PSU_SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN 0xC - - Fast phase lock controls -- phase 0 prop gain - (OFFSET, MASK, VALUE) (0XFD40DC40, 0x0000001FU ,0x0000000CU) - RegMask = (SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_MASK | 0 ); - - RegVal = ((0x0000000CU << SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_CDR16_OFFSET ,0x0000001FU ,0x0000000CU); - /*############################################################################################################################ */ - - /*Register : L3_TM_EQ0 @ 0XFD40D94C

- - EQ stg 2 controls BYPASSED - PSU_SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP 1 - - eq stg1 and stg2 controls - (OFFSET, MASK, VALUE) (0XFD40D94C, 0x00000020U ,0x00000020U) - RegMask = (SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_EQ0_OFFSET ,0x00000020U ,0x00000020U); - /*############################################################################################################################ */ - - /*Register : L3_TM_EQ1 @ 0XFD40D950

- - EQ STG2 RL PROG - PSU_SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG 0x2 - - EQ stg 2 preamp mode val - PSU_SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL 0x1 - - eq stg1 and stg2 controls - (OFFSET, MASK, VALUE) (0XFD40D950, 0x00000007U ,0x00000006U) - RegMask = (SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_MASK | SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_MASK | 0 ); - - RegVal = ((0x00000002U << SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_SHIFT - | 0x00000001U << SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_EQ1_OFFSET ,0x00000007U ,0x00000006U); - /*############################################################################################################################ */ - - // : GEM SERDES SETTINGS - // : ENABLE PRE EMPHAIS AND VOLTAGE SWING - /*Register : L1_TXPMD_TM_48 @ 0XFD404CC0

- - Margining factor value - PSU_SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR 0 - - Margining factor - (OFFSET, MASK, VALUE) (0XFD404CC0, 0x0000001FU ,0x00000000U) - RegMask = (SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_MASK | 0 ); - - RegVal = ((0x00000000U << SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L1_TXPMD_TM_48_OFFSET ,0x0000001FU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : L1_TX_ANA_TM_18 @ 0XFD404048

- - pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-emphasis, Others: reserved - PSU_SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0 0 - - Override for PIPE TX de-emphasis - (OFFSET, MASK, VALUE) (0XFD404048, 0x000000FFU ,0x00000000U) - RegMask = (SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK | 0 ); - - RegVal = ((0x00000000U << SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L1_TX_ANA_TM_18_OFFSET ,0x000000FFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : L3_TX_ANA_TM_18 @ 0XFD40C048

- - pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-emphasis, Others: reserved - PSU_SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0 0x1 - - Override for PIPE TX de-emphasis - (OFFSET, MASK, VALUE) (0XFD40C048, 0x000000FFU ,0x00000001U) - RegMask = (SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TX_ANA_TM_18_OFFSET ,0x000000FFU ,0x00000001U); - /*############################################################################################################################ */ - - - return 1; + * TrustZone classification for Ingress Address Translation 7 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_7 1 + + * TrustZone classification for Egress Address Translation 0 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_0 1 + + * TrustZone classification for Egress Address Translation 1 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_1 1 + + * TrustZone classification for Egress Address Translation 2 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_2 1 + + * TrustZone classification for Egress Address Translation 3 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_3 1 + + * TrustZone classification for Egress Address Translation 4 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_4 1 + + * TrustZone classification for Egress Address Translation 5 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_5 1 + + * TrustZone classification for Egress Address Translation 6 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_6 1 + + * TrustZone classification for Egress Address Translation 7 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_7 1 + + * TrustZone classification for DMA Registers + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_REGS 1 + + * TrustZone classification for MSIx Table + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_TABLE 1 + + * TrustZone classification for MSIx PBA + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_PBA 1 + + * TrustZone classification for ECAM + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_ECAM 1 + + * TrustZone classification for Bridge Common Registers + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_BRIDGE_REGS 1 + + * PCIe TrustZone settings. This register may only be modified during bootu + * p (while PCIe block is disabled) + * (OFFSET, MASK, VALUE) (0XFD690030, 0x01FFFFFFU ,0x01FFFFFFU) + */ + PSU_Mask_Write(FPD_SLCR_SECURE_SLCR_PCIE_OFFSET, + 0x01FFFFFFU, 0x01FFFFFFU); +/*##################################################################### */ + + /* + * USB TZ + */ + /* + * Register : slcr_usb @ 0XFF4B0034 + + * TrustZone Classification for USB3_0 + * PSU_LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_0 1 + + * TrustZone Classification for USB3_1 + * PSU_LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_1 1 + + * USB3 TrustZone settings + * (OFFSET, MASK, VALUE) (0XFF4B0034, 0x00000003U ,0x00000003U) + */ + PSU_Mask_Write(LPD_SLCR_SECURE_SLCR_USB_OFFSET, + 0x00000003U, 0x00000003U); +/*##################################################################### */ + + /* + * SD TZ + */ + /* + * Register : IOU_AXI_RPRTCN @ 0XFF240004 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD0_AXI_ARPROT 2 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD1_AXI_ARPROT 2 + + * AXI read protection type selection + * (OFFSET, MASK, VALUE) (0XFF240004, 0x003F0000U ,0x00120000U) + */ + PSU_Mask_Write(IOU_SECURE_SLCR_IOU_AXI_RPRTCN_OFFSET, + 0x003F0000U, 0x00120000U); +/*##################################################################### */ + + /* + * Register : IOU_AXI_WPRTCN @ 0XFF240000 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD0_AXI_AWPROT 2 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD1_AXI_AWPROT 2 + + * AXI write protection type selection + * (OFFSET, MASK, VALUE) (0XFF240000, 0x003F0000U ,0x00120000U) + */ + PSU_Mask_Write(IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET, + 0x003F0000U, 0x00120000U); +/*##################################################################### */ + + /* + * GEM TZ + */ + /* + * Register : IOU_AXI_RPRTCN @ 0XFF240004 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM0_AXI_ARPROT 2 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM1_AXI_ARPROT 2 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM2_AXI_ARPROT 2 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM3_AXI_ARPROT 2 + + * AXI read protection type selection + * (OFFSET, MASK, VALUE) (0XFF240004, 0x00000FFFU ,0x00000492U) + */ + PSU_Mask_Write(IOU_SECURE_SLCR_IOU_AXI_RPRTCN_OFFSET, + 0x00000FFFU, 0x00000492U); +/*##################################################################### */ + + /* + * Register : IOU_AXI_WPRTCN @ 0XFF240000 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM0_AXI_AWPROT 2 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM1_AXI_AWPROT 2 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM2_AXI_AWPROT 2 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM3_AXI_AWPROT 2 + + * AXI write protection type selection + * (OFFSET, MASK, VALUE) (0XFF240000, 0x00000FFFU ,0x00000492U) + */ + PSU_Mask_Write(IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET, + 0x00000FFFU, 0x00000492U); +/*##################################################################### */ + + /* + * QSPI TZ + */ + /* + * Register : IOU_AXI_WPRTCN @ 0XFF240000 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_QSPI_AXI_AWPROT 2 + + * AXI write protection type selection + * (OFFSET, MASK, VALUE) (0XFF240000, 0x0E000000U ,0x04000000U) + */ + PSU_Mask_Write(IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET, + 0x0E000000U, 0x04000000U); +/*##################################################################### */ + + /* + * NAND TZ + */ + /* + * Register : IOU_AXI_RPRTCN @ 0XFF240004 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_RPRTCN_NAND_AXI_ARPROT 2 + + * AXI read protection type selection + * (OFFSET, MASK, VALUE) (0XFF240004, 0x01C00000U ,0x00800000U) + */ + PSU_Mask_Write(IOU_SECURE_SLCR_IOU_AXI_RPRTCN_OFFSET, + 0x01C00000U, 0x00800000U); +/*##################################################################### */ + + /* + * Register : IOU_AXI_WPRTCN @ 0XFF240000 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_NAND_AXI_AWPROT 2 + + * AXI write protection type selection + * (OFFSET, MASK, VALUE) (0XFF240000, 0x01C00000U ,0x00800000U) + */ + PSU_Mask_Write(IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET, + 0x01C00000U, 0x00800000U); +/*##################################################################### */ + + /* + * DMA TZ + */ + /* + * Register : slcr_adma @ 0XFF4B0024 + + * TrustZone Classification for ADMA + * PSU_LPD_SLCR_SECURE_SLCR_ADMA_TZ 0xFF + + * RPU TrustZone settings + * (OFFSET, MASK, VALUE) (0XFF4B0024, 0x000000FFU ,0x000000FFU) + */ + PSU_Mask_Write(LPD_SLCR_SECURE_SLCR_ADMA_OFFSET, + 0x000000FFU, 0x000000FFU); +/*##################################################################### */ + + /* + * Register : slcr_gdma @ 0XFD690050 + + * TrustZone Classification for GDMA + * PSU_FPD_SLCR_SECURE_SLCR_GDMA_TZ 0xFF + + * GDMA Trustzone Settings + * (OFFSET, MASK, VALUE) (0XFD690050, 0x000000FFU ,0x000000FFU) + */ + PSU_Mask_Write(FPD_SLCR_SECURE_SLCR_GDMA_OFFSET, + 0x000000FFU, 0x000000FFU); +/*##################################################################### */ + + + return 1; } -unsigned long psu_resetout_init_data() { - // : TAKING SERDES PERIPHERAL OUT OF RESET RESET - // : PUTTING USB0 IN RESET - /*Register : RST_LPD_TOP @ 0XFF5E023C

+unsigned long psu_serdes_init_data(void) +{ + /* + * SERDES INITIALIZATION + */ + /* + * GT REFERENCE CLOCK SOURCE SELECTION + */ + /* + * Register : PLL_REF_SEL0 @ 0XFD410000 + + * PLL0 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 1 + * 2MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 24MHz, 0x8 - 26MHz, + * 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE + * - 108MHz, 0xF - 125MHz, 0x10 - 135MHz, 0x11 - 150 MHz. 0x12 to 0x1F - R + * eserved + * PSU_SERDES_PLL_REF_SEL0_PLLREFSEL0 0xD + + * PLL0 Reference Selection Register + * (OFFSET, MASK, VALUE) (0XFD410000, 0x0000001FU ,0x0000000DU) + */ + PSU_Mask_Write(SERDES_PLL_REF_SEL0_OFFSET, 0x0000001FU, 0x0000000DU); +/*##################################################################### */ + + /* + * Register : PLL_REF_SEL1 @ 0XFD410004 + + * PLL1 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 1 + * 2MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 24MHz, 0x8 - 26MHz, + * 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE + * - 108MHz, 0xF - 125MHz, 0x10 - 135MHz, 0x11 - 150 MHz. 0x12 to 0x1F - R + * eserved + * PSU_SERDES_PLL_REF_SEL1_PLLREFSEL1 0x9 + + * PLL1 Reference Selection Register + * (OFFSET, MASK, VALUE) (0XFD410004, 0x0000001FU ,0x00000009U) + */ + PSU_Mask_Write(SERDES_PLL_REF_SEL1_OFFSET, 0x0000001FU, 0x00000009U); +/*##################################################################### */ + + /* + * Register : PLL_REF_SEL2 @ 0XFD410008 + + * PLL2 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 1 + * 2MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 24MHz, 0x8 - 26MHz, + * 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE + * - 108MHz, 0xF - 125MHz, 0x10 - 135MHz, 0x11 - 150 MHz. 0x12 to 0x1F - R + * eserved + * PSU_SERDES_PLL_REF_SEL2_PLLREFSEL2 0x8 + + * PLL2 Reference Selection Register + * (OFFSET, MASK, VALUE) (0XFD410008, 0x0000001FU ,0x00000008U) + */ + PSU_Mask_Write(SERDES_PLL_REF_SEL2_OFFSET, 0x0000001FU, 0x00000008U); +/*##################################################################### */ + + /* + * Register : PLL_REF_SEL3 @ 0XFD41000C + + * PLL3 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 1 + * 2MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 24MHz, 0x8 - 26MHz, + * 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE + * - 108MHz, 0xF - 125MHz, 0x10 - 135MHz, 0x11 - 150 MHz. 0x12 to 0x1F - R + * eserved + * PSU_SERDES_PLL_REF_SEL3_PLLREFSEL3 0xF + + * PLL3 Reference Selection Register + * (OFFSET, MASK, VALUE) (0XFD41000C, 0x0000001FU ,0x0000000FU) + */ + PSU_Mask_Write(SERDES_PLL_REF_SEL3_OFFSET, 0x0000001FU, 0x0000000FU); +/*##################################################################### */ + + /* + * GT REFERENCE CLOCK FREQUENCY SELECTION + */ + /* + * Register : L0_L0_REF_CLK_SEL @ 0XFD402860 + + * Sel of lane 0 ref clock local mux. Set to 1 to select lane 0 slicer outp + * ut. Set to 0 to select lane0 ref clock mux output. + * PSU_SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL 0x1 + + * Lane0 Ref Clock Selection Register + * (OFFSET, MASK, VALUE) (0XFD402860, 0x00000080U ,0x00000080U) + */ + PSU_Mask_Write(SERDES_L0_L0_REF_CLK_SEL_OFFSET, + 0x00000080U, 0x00000080U); +/*##################################################################### */ + + /* + * Register : L0_L1_REF_CLK_SEL @ 0XFD402864 + + * Sel of lane 1 ref clock local mux. Set to 1 to select lane 1 slicer outp + * ut. Set to 0 to select lane1 ref clock mux output. + * PSU_SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL 0x0 + + * Bit 3 of lane 1 ref clock mux one hot sel. Set to 1 to select lane 3 sli + * cer output from ref clock network + * PSU_SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3 0x1 + + * Lane1 Ref Clock Selection Register + * (OFFSET, MASK, VALUE) (0XFD402864, 0x00000088U ,0x00000008U) + */ + PSU_Mask_Write(SERDES_L0_L1_REF_CLK_SEL_OFFSET, + 0x00000088U, 0x00000008U); +/*##################################################################### */ + + /* + * Register : L0_L2_REF_CLK_SEL @ 0XFD402868 + + * Sel of lane 2 ref clock local mux. Set to 1 to select lane 1 slicer outp + * ut. Set to 0 to select lane2 ref clock mux output. + * PSU_SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL 0x1 + + * Lane2 Ref Clock Selection Register + * (OFFSET, MASK, VALUE) (0XFD402868, 0x00000080U ,0x00000080U) + */ + PSU_Mask_Write(SERDES_L0_L2_REF_CLK_SEL_OFFSET, + 0x00000080U, 0x00000080U); +/*##################################################################### */ + + /* + * Register : L0_L3_REF_CLK_SEL @ 0XFD40286C + + * Sel of lane 3 ref clock local mux. Set to 1 to select lane 3 slicer outp + * ut. Set to 0 to select lane3 ref clock mux output. + * PSU_SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL 0x0 + + * Bit 1 of lane 3 ref clock mux one hot sel. Set to 1 to select lane 1 sli + * cer output from ref clock network + * PSU_SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1 0x1 + + * Lane3 Ref Clock Selection Register + * (OFFSET, MASK, VALUE) (0XFD40286C, 0x00000082U ,0x00000002U) + */ + PSU_Mask_Write(SERDES_L0_L3_REF_CLK_SEL_OFFSET, + 0x00000082U, 0x00000002U); +/*##################################################################### */ + + /* + * ENABLE SPREAD SPECTRUM + */ + /* + * Register : L2_TM_PLL_DIG_37 @ 0XFD40A094 + + * Enable/Disable coarse code satureation limiting logic + * PSU_SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION 0x1 + + * Test mode register 37 + * (OFFSET, MASK, VALUE) (0XFD40A094, 0x00000010U ,0x00000010U) + */ + PSU_Mask_Write(SERDES_L2_TM_PLL_DIG_37_OFFSET, + 0x00000010U, 0x00000010U); +/*##################################################################### */ + + /* + * Register : L2_PLL_SS_STEPS_0_LSB @ 0XFD40A368 + + * Spread Spectrum No of Steps [7:0] + * PSU_SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB 0x38 + + * Spread Spectrum No of Steps bits 7:0 + * (OFFSET, MASK, VALUE) (0XFD40A368, 0x000000FFU ,0x00000038U) + */ + PSU_Mask_Write(SERDES_L2_PLL_SS_STEPS_0_LSB_OFFSET, + 0x000000FFU, 0x00000038U); +/*##################################################################### */ + + /* + * Register : L2_PLL_SS_STEPS_1_MSB @ 0XFD40A36C + + * Spread Spectrum No of Steps [10:8] + * PSU_SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB 0x03 + + * Spread Spectrum No of Steps bits 10:8 + * (OFFSET, MASK, VALUE) (0XFD40A36C, 0x00000007U ,0x00000003U) + */ + PSU_Mask_Write(SERDES_L2_PLL_SS_STEPS_1_MSB_OFFSET, + 0x00000007U, 0x00000003U); +/*##################################################################### */ + + /* + * Register : L3_PLL_SS_STEPS_0_LSB @ 0XFD40E368 + + * Spread Spectrum No of Steps [7:0] + * PSU_SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB 0xE0 + + * Spread Spectrum No of Steps bits 7:0 + * (OFFSET, MASK, VALUE) (0XFD40E368, 0x000000FFU ,0x000000E0U) + */ + PSU_Mask_Write(SERDES_L3_PLL_SS_STEPS_0_LSB_OFFSET, + 0x000000FFU, 0x000000E0U); +/*##################################################################### */ + + /* + * Register : L3_PLL_SS_STEPS_1_MSB @ 0XFD40E36C + + * Spread Spectrum No of Steps [10:8] + * PSU_SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB 0x3 + + * Spread Spectrum No of Steps bits 10:8 + * (OFFSET, MASK, VALUE) (0XFD40E36C, 0x00000007U ,0x00000003U) + */ + PSU_Mask_Write(SERDES_L3_PLL_SS_STEPS_1_MSB_OFFSET, + 0x00000007U, 0x00000003U); +/*##################################################################### */ + + /* + * Register : L1_PLL_SS_STEPS_0_LSB @ 0XFD406368 + + * Spread Spectrum No of Steps [7:0] + * PSU_SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB 0x58 + + * Spread Spectrum No of Steps bits 7:0 + * (OFFSET, MASK, VALUE) (0XFD406368, 0x000000FFU ,0x00000058U) + */ + PSU_Mask_Write(SERDES_L1_PLL_SS_STEPS_0_LSB_OFFSET, + 0x000000FFU, 0x00000058U); +/*##################################################################### */ + + /* + * Register : L1_PLL_SS_STEPS_1_MSB @ 0XFD40636C + + * Spread Spectrum No of Steps [10:8] + * PSU_SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB 0x3 + + * Spread Spectrum No of Steps bits 10:8 + * (OFFSET, MASK, VALUE) (0XFD40636C, 0x00000007U ,0x00000003U) + */ + PSU_Mask_Write(SERDES_L1_PLL_SS_STEPS_1_MSB_OFFSET, + 0x00000007U, 0x00000003U); +/*##################################################################### */ + + /* + * Register : L1_PLL_SS_STEP_SIZE_0_LSB @ 0XFD406370 + + * Step Size for Spread Spectrum [7:0] + * PSU_SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB 0x7C + + * Step Size for Spread Spectrum LSB + * (OFFSET, MASK, VALUE) (0XFD406370, 0x000000FFU ,0x0000007CU) + */ + PSU_Mask_Write(SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_OFFSET, + 0x000000FFU, 0x0000007CU); +/*##################################################################### */ + + /* + * Register : L1_PLL_SS_STEP_SIZE_1 @ 0XFD406374 + + * Step Size for Spread Spectrum [15:8] + * PSU_SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1 0x33 + + * Step Size for Spread Spectrum 1 + * (OFFSET, MASK, VALUE) (0XFD406374, 0x000000FFU ,0x00000033U) + */ + PSU_Mask_Write(SERDES_L1_PLL_SS_STEP_SIZE_1_OFFSET, + 0x000000FFU, 0x00000033U); +/*##################################################################### */ + + /* + * Register : L1_PLL_SS_STEP_SIZE_2 @ 0XFD406378 + + * Step Size for Spread Spectrum [23:16] + * PSU_SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2 0x2 + + * Step Size for Spread Spectrum 2 + * (OFFSET, MASK, VALUE) (0XFD406378, 0x000000FFU ,0x00000002U) + */ + PSU_Mask_Write(SERDES_L1_PLL_SS_STEP_SIZE_2_OFFSET, + 0x000000FFU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : L1_PLL_SS_STEP_SIZE_3_MSB @ 0XFD40637C + + * Step Size for Spread Spectrum [25:24] + * PSU_SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB 0x0 + + * Enable/Disable test mode force on SS step size + * PSU_SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE 0x1 + + * Enable/Disable test mode force on SS no of steps + * PSU_SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS 0x1 + + * Enable force on enable Spread Spectrum + * (OFFSET, MASK, VALUE) (0XFD40637C, 0x00000033U ,0x00000030U) + */ + PSU_Mask_Write(SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_OFFSET, + 0x00000033U, 0x00000030U); +/*##################################################################### */ + + /* + * Register : L2_PLL_SS_STEP_SIZE_0_LSB @ 0XFD40A370 + + * Step Size for Spread Spectrum [7:0] + * PSU_SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB 0xF4 + + * Step Size for Spread Spectrum LSB + * (OFFSET, MASK, VALUE) (0XFD40A370, 0x000000FFU ,0x000000F4U) + */ + PSU_Mask_Write(SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_OFFSET, + 0x000000FFU, 0x000000F4U); +/*##################################################################### */ + + /* + * Register : L2_PLL_SS_STEP_SIZE_1 @ 0XFD40A374 + + * Step Size for Spread Spectrum [15:8] + * PSU_SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1 0x31 + + * Step Size for Spread Spectrum 1 + * (OFFSET, MASK, VALUE) (0XFD40A374, 0x000000FFU ,0x00000031U) + */ + PSU_Mask_Write(SERDES_L2_PLL_SS_STEP_SIZE_1_OFFSET, + 0x000000FFU, 0x00000031U); +/*##################################################################### */ + + /* + * Register : L2_PLL_SS_STEP_SIZE_2 @ 0XFD40A378 - USB 0 reset for control registers - PSU_CRL_APB_RST_LPD_TOP_USB0_APB_RESET 0X0 + * Step Size for Spread Spectrum [23:16] + * PSU_SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2 0x2 + + * Step Size for Spread Spectrum 2 + * (OFFSET, MASK, VALUE) (0XFD40A378, 0x000000FFU ,0x00000002U) + */ + PSU_Mask_Write(SERDES_L2_PLL_SS_STEP_SIZE_2_OFFSET, + 0x000000FFU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : L2_PLL_SS_STEP_SIZE_3_MSB @ 0XFD40A37C - Software control register for the LPD block. - (OFFSET, MASK, VALUE) (0XFF5E023C, 0x00000400U ,0x00000000U) - RegMask = (CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK | 0 ); + * Step Size for Spread Spectrum [25:24] + * PSU_SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB 0x0 - RegVal = ((0x00000000U << CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RST_LPD_TOP_OFFSET ,0x00000400U ,0x00000000U); - /*############################################################################################################################ */ + * Enable/Disable test mode force on SS step size + * PSU_SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE 0x1 + + * Enable/Disable test mode force on SS no of steps + * PSU_SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS 0x1 + + * Enable force on enable Spread Spectrum + * (OFFSET, MASK, VALUE) (0XFD40A37C, 0x00000033U ,0x00000030U) + */ + PSU_Mask_Write(SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_OFFSET, + 0x00000033U, 0x00000030U); +/*##################################################################### */ - // : USB0 PIPE POWER PRESENT - /*Register : fpd_power_prsnt @ 0XFF9D0080

+ /* + * Register : L3_PLL_SS_STEP_SIZE_0_LSB @ 0XFD40E370 + + * Step Size for Spread Spectrum [7:0] + * PSU_SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB 0xC9 + + * Step Size for Spread Spectrum LSB + * (OFFSET, MASK, VALUE) (0XFD40E370, 0x000000FFU ,0x000000C9U) + */ + PSU_Mask_Write(SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_OFFSET, + 0x000000FFU, 0x000000C9U); +/*##################################################################### */ - This bit is used to choose between PIPE power present and 1'b1 - PSU_USB3_0_FPD_POWER_PRSNT_OPTION 0X1 + /* + * Register : L3_PLL_SS_STEP_SIZE_1 @ 0XFD40E374 - fpd_power_prsnt - (OFFSET, MASK, VALUE) (0XFF9D0080, 0x00000001U ,0x00000001U) - RegMask = (USB3_0_FPD_POWER_PRSNT_OPTION_MASK | 0 ); + * Step Size for Spread Spectrum [15:8] + * PSU_SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1 0xD2 - RegVal = ((0x00000001U << USB3_0_FPD_POWER_PRSNT_OPTION_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (USB3_0_FPD_POWER_PRSNT_OFFSET ,0x00000001U ,0x00000001U); - /*############################################################################################################################ */ + * Step Size for Spread Spectrum 1 + * (OFFSET, MASK, VALUE) (0XFD40E374, 0x000000FFU ,0x000000D2U) + */ + PSU_Mask_Write(SERDES_L3_PLL_SS_STEP_SIZE_1_OFFSET, + 0x000000FFU, 0x000000D2U); +/*##################################################################### */ - /*Register : fpd_pipe_clk @ 0XFF9D007C

+ /* + * Register : L3_PLL_SS_STEP_SIZE_2 @ 0XFD40E378 - This bit is used to choose between PIPE clock coming from SerDes and the suspend clk - PSU_USB3_0_FPD_PIPE_CLK_OPTION 0x0 + * Step Size for Spread Spectrum [23:16] + * PSU_SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2 0x1 - fpd_pipe_clk - (OFFSET, MASK, VALUE) (0XFF9D007C, 0x00000001U ,0x00000000U) - RegMask = (USB3_0_FPD_PIPE_CLK_OPTION_MASK | 0 ); + * Step Size for Spread Spectrum 2 + * (OFFSET, MASK, VALUE) (0XFD40E378, 0x000000FFU ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L3_PLL_SS_STEP_SIZE_2_OFFSET, + 0x000000FFU, 0x00000001U); +/*##################################################################### */ - RegVal = ((0x00000000U << USB3_0_FPD_PIPE_CLK_OPTION_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (USB3_0_FPD_PIPE_CLK_OFFSET ,0x00000001U ,0x00000000U); - /*############################################################################################################################ */ + /* + * Register : L3_PLL_SS_STEP_SIZE_3_MSB @ 0XFD40E37C - // : - /*Register : RST_LPD_TOP @ 0XFF5E023C

+ * Step Size for Spread Spectrum [25:24] + * PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB 0x0 - USB 0 sleep circuit reset - PSU_CRL_APB_RST_LPD_TOP_USB0_HIBERRESET 0X0 + * Enable/Disable test mode force on SS step size + * PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE 0x1 - USB 0 reset - PSU_CRL_APB_RST_LPD_TOP_USB0_CORERESET 0X0 + * Enable/Disable test mode force on SS no of steps + * PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS 0x1 + + * Enable test mode forcing on enable Spread Spectrum + * PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS 0x1 - Software control register for the LPD block. - (OFFSET, MASK, VALUE) (0XFF5E023C, 0x00000140U ,0x00000000U) - RegMask = (CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK | CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK | 0 ); + * Enable force on enable Spread Spectrum + * (OFFSET, MASK, VALUE) (0XFD40E37C, 0x000000B3U ,0x000000B0U) + */ + PSU_Mask_Write(SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_OFFSET, + 0x000000B3U, 0x000000B0U); +/*##################################################################### */ - RegVal = ((0x00000000U << CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT - | 0x00000000U << CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RST_LPD_TOP_OFFSET ,0x00000140U ,0x00000000U); - /*############################################################################################################################ */ + /* + * Register : L2_TM_DIG_6 @ 0XFD40906C - // : PUTTING GEM0 IN RESET - /*Register : RST_LPD_IOU0 @ 0XFF5E0230

+ * Bypass Descrambler + * PSU_SERDES_L2_TM_DIG_6_BYPASS_DESCRAM 0x1 - GEM 3 reset - PSU_CRL_APB_RST_LPD_IOU0_GEM3_RESET 0X0 + * Enable Bypass for <1> TM_DIG_CTRL_6 + * PSU_SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM 0x1 - Software controlled reset for the GEMs - (OFFSET, MASK, VALUE) (0XFF5E0230, 0x00000008U ,0x00000000U) - RegMask = (CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK | 0 ); + * Data path test modes in decoder and descram + * (OFFSET, MASK, VALUE) (0XFD40906C, 0x00000003U ,0x00000003U) + */ + PSU_Mask_Write(SERDES_L2_TM_DIG_6_OFFSET, 0x00000003U, 0x00000003U); +/*##################################################################### */ + + /* + * Register : L2_TX_DIG_TM_61 @ 0XFD4080F4 - RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RST_LPD_IOU0_OFFSET ,0x00000008U ,0x00000000U); - /*############################################################################################################################ */ + * Bypass scrambler signal + * PSU_SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM 0x1 - // : PUTTING SATA IN RESET - /*Register : sata_misc_ctrl @ 0XFD3D0100

+ * Enable/disable scrambler bypass signal + * PSU_SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM 0x1 + + * MPHY PLL Gear and bypass scrambler + * (OFFSET, MASK, VALUE) (0XFD4080F4, 0x00000003U ,0x00000003U) + */ + PSU_Mask_Write(SERDES_L2_TX_DIG_TM_61_OFFSET, + 0x00000003U, 0x00000003U); +/*##################################################################### */ + + /* + * Register : L3_PLL_FBDIV_FRAC_3_MSB @ 0XFD40E360 + + * Enable test mode force on fractional mode enable + * PSU_SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC 0x1 + + * Fractional feedback division control and fractional value for feedback d + * ivision bits 26:24 + * (OFFSET, MASK, VALUE) (0XFD40E360, 0x00000040U ,0x00000040U) + */ + PSU_Mask_Write(SERDES_L3_PLL_FBDIV_FRAC_3_MSB_OFFSET, + 0x00000040U, 0x00000040U); +/*##################################################################### */ - Sata PM clock control select - PSU_SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL 0x3 + /* + * Register : L3_TM_DIG_6 @ 0XFD40D06C + + * Bypass 8b10b decoder + * PSU_SERDES_L3_TM_DIG_6_BYPASS_DECODER 0x1 - Misc Contorls for SATA.This register may only be modified during bootup (while SATA block is disabled) - (OFFSET, MASK, VALUE) (0XFD3D0100, 0x00000003U ,0x00000003U) - RegMask = (SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_MASK | 0 ); + * Enable Bypass for <3> TM_DIG_CTRL_6 + * PSU_SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC 0x1 - RegVal = ((0x00000003U << SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SIOU_SATA_MISC_CTRL_OFFSET ,0x00000003U ,0x00000003U); - /*############################################################################################################################ */ + * Bypass Descrambler + * PSU_SERDES_L3_TM_DIG_6_BYPASS_DESCRAM 0x1 - /*Register : RST_FPD_TOP @ 0XFD1A0100

+ * Enable Bypass for <1> TM_DIG_CTRL_6 + * PSU_SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM 0x1 + + * Data path test modes in decoder and descram + * (OFFSET, MASK, VALUE) (0XFD40D06C, 0x0000000FU ,0x0000000FU) + */ + PSU_Mask_Write(SERDES_L3_TM_DIG_6_OFFSET, 0x0000000FU, 0x0000000FU); +/*##################################################################### */ + + /* + * Register : L3_TX_DIG_TM_61 @ 0XFD40C0F4 + + * Enable/disable encoder bypass signal + * PSU_SERDES_L3_TX_DIG_TM_61_BYPASS_ENC 0x1 + + * Bypass scrambler signal + * PSU_SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM 0x1 + + * Enable/disable scrambler bypass signal + * PSU_SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM 0x1 - Sata block level reset - PSU_CRF_APB_RST_FPD_TOP_SATA_RESET 0X0 - - FPD Block level software controlled reset - (OFFSET, MASK, VALUE) (0XFD1A0100, 0x00000002U ,0x00000000U) - RegMask = (CRF_APB_RST_FPD_TOP_SATA_RESET_MASK | 0 ); - - RegVal = ((0x00000000U << CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_RST_FPD_TOP_OFFSET ,0x00000002U ,0x00000000U); - /*############################################################################################################################ */ - - // : PUTTING PCIE CFG AND BRIDGE IN RESET - /*Register : RST_FPD_TOP @ 0XFD1A0100

- - PCIE config reset - PSU_CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET 0X0 - - PCIE bridge block level reset (AXI interface) - PSU_CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET 0X0 - - FPD Block level software controlled reset - (OFFSET, MASK, VALUE) (0XFD1A0100, 0x000C0000U ,0x00000000U) - RegMask = (CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK | CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK | 0 ); - - RegVal = ((0x00000000U << CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT - | 0x00000000U << CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_RST_FPD_TOP_OFFSET ,0x000C0000U ,0x00000000U); - /*############################################################################################################################ */ - - // : PUTTING DP IN RESET - /*Register : RST_FPD_TOP @ 0XFD1A0100

- - Display Port block level reset (includes DPDMA) - PSU_CRF_APB_RST_FPD_TOP_DP_RESET 0X0 - - FPD Block level software controlled reset - (OFFSET, MASK, VALUE) (0XFD1A0100, 0x00010000U ,0x00000000U) - RegMask = (CRF_APB_RST_FPD_TOP_DP_RESET_MASK | 0 ); - - RegVal = ((0x00000000U << CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_RST_FPD_TOP_OFFSET ,0x00010000U ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : DP_PHY_RESET @ 0XFD4A0200

- - Set to '1' to hold the GT in reset. Clear to release. - PSU_DP_DP_PHY_RESET_GT_RESET 0X0 - - Reset the transmitter PHY. - (OFFSET, MASK, VALUE) (0XFD4A0200, 0x00000002U ,0x00000000U) - RegMask = (DP_DP_PHY_RESET_GT_RESET_MASK | 0 ); - - RegVal = ((0x00000000U << DP_DP_PHY_RESET_GT_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DP_DP_PHY_RESET_OFFSET ,0x00000002U ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : DP_TX_PHY_POWER_DOWN @ 0XFD4A0238

- - Two bits per lane. When set to 11, moves the GT to power down mode. When set to 00, GT will be in active state. bits [1:0] - - ane0 Bits [3:2] - lane 1 - PSU_DP_DP_TX_PHY_POWER_DOWN_POWER_DWN 0X0 - - Control PHY Power down - (OFFSET, MASK, VALUE) (0XFD4A0238, 0x0000000FU ,0x00000000U) - RegMask = (DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK | 0 ); - - RegVal = ((0x00000000U << DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DP_DP_TX_PHY_POWER_DOWN_OFFSET ,0x0000000FU ,0x00000000U); - /*############################################################################################################################ */ - - // : USB0 GFLADJ - /*Register : GUSB2PHYCFG @ 0XFE20C200

- - USB 2.0 Turnaround Time (USBTrdTim) Sets the turnaround time in PHY clocks. Specifies the response time for a MAC request to - he Packet FIFO Controller (PFC) to fetch data from the DFIFO (SPRAM). The following are the required values for the minimum S - C bus frequency of 60 MHz. USB turnaround time is a critical certification criteria when using long cables and five hub level - . The required values for this field: - 4'h5: When the MAC interface is 16-bit UTMI+. - 4'h9: When the MAC interface is 8-bit - UTMI+/ULPI. If SoC bus clock is less than 60 MHz, and USB turnaround time is not critical, this field can be set to a larger - alue. Note: This field is valid only in device mode. - PSU_USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM 0x9 - - Transceiver Delay: Enables a delay between the assertion of the UTMI/ULPI Transceiver Select signal (for HS) and the assertio - of the TxValid signal during a HS Chirp. When this bit is set to 1, a delay (of approximately 2.5 us) is introduced from the - time when the Transceiver Select is set to 2'b00 (HS) to the time the TxValid is driven to 0 for sending the chirp-K. This de - ay is required for some UTMI/ULPI PHYs. Note: - If you enable the hibernation feature when the device core comes out of power - off, you must re-initialize this bit with the appropriate value because the core does not save and restore this bit value dur - ng hibernation. - This bit is valid only in device mode. - PSU_USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY 0x0 - - Enable utmi_sleep_n and utmi_l1_suspend_n (EnblSlpM) The application uses this bit to control utmi_sleep_n and utmi_l1_suspen - _n assertion to the PHY in the L1 state. - 1'b0: utmi_sleep_n and utmi_l1_suspend_n assertion from the core is not transferre - to the external PHY. - 1'b1: utmi_sleep_n and utmi_l1_suspend_n assertion from the core is transferred to the external PHY. - ote: This bit must be set high for Port0 if PHY is used. Note: In Device mode - Before issuing any device endpoint command wh - n operating in 2.0 speeds, disable this bit and enable it after the command completes. Without disabling this bit, if a comma - d is issued when the device is in L1 state and if mac2_clk (utmi_clk/ulpi_clk) is gated off, the command will not get complet - d. - PSU_USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM 0x0 - - USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial Transceiver Select The application uses this bit to select a high-speed P - Y or a full-speed transceiver. - 1'b0: USB 2.0 high-speed UTMI+ or ULPI PHY. This bit is always 0, with Write Only access. - - 'b1: USB 1.1 full-speed serial transceiver. This bit is always 1, with Write Only access. If both interface types are selecte - in coreConsultant (that is, parameters' values are not zero), the application uses this bit to select the active interface i - active, with Read-Write bit access. Note: USB 1.1 full-serial transceiver is not supported. This bit always reads as 1'b0. - PSU_USB3_0_XHCI_GUSB2PHYCFG_PHYSEL 0x0 - - Full-Speed Serial Interface Select (FSIntf) The application uses this bit to select a unidirectional or bidirectional USB 1.1 - full-speed serial transceiver interface. - 1'b0: 6-pin unidirectional full-speed serial interface. This bit is set to 0 with - ead Only access. - 1'b1: 3-pin bidirectional full-speed serial interface. This bit is set to 0 with Read Only access. Note: U - B 1.1 full-speed serial interface is not supported. This bit always reads as 1'b0. - PSU_USB3_0_XHCI_GUSB2PHYCFG_FSINTF 0x0 - - ULPI or UTMI+ Select (ULPI_UTMI_Sel) The application uses this bit to select a UTMI+ or ULPI Interface. - 1'b0: UTMI+ Interfa - e - 1'b1: ULPI Interface This bit is writable only if UTMI+ and ULPI is specified for High-Speed PHY Interface(s) in coreCons - ltant configuration (DWC_USB3_HSPHY_INTERFACE = 3). Otherwise, this bit is read-only and the value depends on the interface s - lected through DWC_USB3_HSPHY_INTERFACE. - PSU_USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL 0x1 - - PHY Interface (PHYIf) If UTMI+ is selected, the application uses this bit to configure the core to support a UTMI+ PHY with a - 8- or 16-bit interface. - 1'b0: 8 bits - 1'b1: 16 bits ULPI Mode: 1'b0 Note: - All the enabled 2.0 ports must have the same - lock frequency as Port0 clock frequency (utmi_clk[0]). - The UTMI 8-bit and 16-bit modes cannot be used together for differen - ports at the same time (that is, all the ports must be in 8-bit mode, or all of them must be in 16-bit mode, at a time). - I - any of the USB 2.0 ports is selected as ULPI port for operation, then all the USB 2.0 ports must be operating at 60 MHz. - PSU_USB3_0_XHCI_GUSB2PHYCFG_PHYIF 0x0 - - HS/FS Timeout Calibration (TOutCal) The number of PHY clocks, as indicated by the application in this field, is multiplied by - a bit-time factor; this factor is added to the high-speed/full-speed interpacket timeout duration in the core to account for - dditional delays introduced by the PHY. This may be required, since the delay introduced by the PHY in generating the linesta - e condition may vary among PHYs. The USB standard timeout value for high-speed operation is 736 to 816 (inclusive) bit times. - The USB standard timeout value for full-speed operation is 16 to 18 (inclusive) bit times. The application must program this - ield based on the speed of connection. The number of bit times added per PHY clock are: High-speed operation: - One 30-MHz PH - clock = 16 bit times - One 60-MHz PHY clock = 8 bit times Full-speed operation: - One 30-MHz PHY clock = 0.4 bit times - One - 60-MHz PHY clock = 0.2 bit times - One 48-MHz PHY clock = 0.25 bit times - PSU_USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL 0x7 - - Global USB2 PHY Configuration Register The application must program this register before starting any transactions on either - he SoC bus or the USB. In Device-only configurations, only one register is needed. In Host mode, per-port registers are imple - ented. - (OFFSET, MASK, VALUE) (0XFE20C200, 0x00003FBFU ,0x00002417U) - RegMask = (USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_MASK | USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_MASK | USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_MASK | USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_MASK | USB3_0_XHCI_GUSB2PHYCFG_FSINTF_MASK | USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_MASK | USB3_0_XHCI_GUSB2PHYCFG_PHYIF_MASK | USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_MASK | 0 ); - - RegVal = ((0x00000009U << USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_SHIFT - | 0x00000000U << USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_SHIFT - | 0x00000000U << USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_SHIFT - | 0x00000000U << USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_SHIFT - | 0x00000000U << USB3_0_XHCI_GUSB2PHYCFG_FSINTF_SHIFT - | 0x00000001U << USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_SHIFT - | 0x00000000U << USB3_0_XHCI_GUSB2PHYCFG_PHYIF_SHIFT - | 0x00000007U << USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (USB3_0_XHCI_GUSB2PHYCFG_OFFSET ,0x00003FBFU ,0x00002417U); - /*############################################################################################################################ */ - - /*Register : GFLADJ @ 0XFE20C630

- - This field indicates the frame length adjustment to be applied when SOF/ITP counter is running on the ref_clk. This register - alue is used to adjust the ITP interval when GCTL[SOFITPSYNC] is set to '1'; SOF and ITP interval when GLADJ.GFLADJ_REFCLK_LP - _SEL is set to '1'. This field must be programmed to a non-zero value only if GFLADJ_REFCLK_LPM_SEL is set to '1' or GCTL.SOF - TPSYNC is set to '1'. The value is derived as follows: FLADJ_REF_CLK_FLADJ=((125000/ref_clk_period_integer)-(125000/ref_clk_p - riod)) * ref_clk_period where - the ref_clk_period_integer is the integer value of the ref_clk period got by truncating the d - cimal (fractional) value that is programmed in the GUCTL.REF_CLK_PERIOD field. - the ref_clk_period is the ref_clk period inc - uding the fractional value. Examples: If the ref_clk is 24 MHz then - GUCTL.REF_CLK_PERIOD = 41 - GFLADJ.GLADJ_REFCLK_FLADJ = - ((125000/41)-(125000/41.6666))*41.6666 = 2032 (ignoring the fractional value) If the ref_clk is 48 MHz then - GUCTL.REF_CLK_P - RIOD = 20 - GFLADJ.GLADJ_REFCLK_FLADJ = ((125000/20)-(125000/20.8333))*20.8333 = 5208 (ignoring the fractional value) - PSU_USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ 0x0 - - Global Frame Length Adjustment Register This register provides options for the software to control the core behavior with res - ect to SOF (Start of Frame) and ITP (Isochronous Timestamp Packet) timers and frame timer functionality. It provides an optio - to override the fladj_30mhz_reg sideband signal. In addition, it enables running SOF or ITP frame timer counters completely - rom the ref_clk. This facilitates hardware LPM in host mode with the SOF or ITP counters being run from the ref_clk signal. - (OFFSET, MASK, VALUE) (0XFE20C630, 0x003FFF00U ,0x00000000U) - RegMask = (USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_MASK | 0 ); - - RegVal = ((0x00000000U << USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (USB3_0_XHCI_GFLADJ_OFFSET ,0x003FFF00U ,0x00000000U); - /*############################################################################################################################ */ - - // : UPDATING TWO PCIE REGISTERS DEFAULT VALUES, AS THESE REGISTERS HAVE INCORRECT RESET VALUES IN SILICON. - /*Register : ATTR_25 @ 0XFD480064

- - If TRUE Completion Timeout Disable is supported. This is required to be TRUE for Endpoint and either setting allowed for Root - ports. Drives Device Capability 2 [4]; EP=0x0001; RP=0x0001 - PSU_PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED 0X1 - - ATTR_25 - (OFFSET, MASK, VALUE) (0XFD480064, 0x00000200U ,0x00000200U) - RegMask = (PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_MASK | 0 ); - - RegVal = ((0x00000001U << PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_25_OFFSET ,0x00000200U ,0x00000200U); - /*############################################################################################################################ */ - - // : PCIE SETTINGS - /*Register : ATTR_7 @ 0XFD48001C

- - Specifies mask/settings for Base Address Register (BAR) 0. If BAR is not to be implemented, set to 32'h00000000. Bits are def - ned as follows: Memory Space BAR [0] = Mem Space Indicator (set to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = - Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory a - erture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR1,BAR0\'7d to 1. IO Space BAR 0] = IO Space Indicator - set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o apert - re size in bytes.; EP=0x0004; RP=0x0000 - PSU_PCIE_ATTRIB_ATTR_7_ATTR_BAR0 0x0 - - ATTR_7 - (OFFSET, MASK, VALUE) (0XFD48001C, 0x0000FFFFU ,0x00000000U) - RegMask = (PCIE_ATTRIB_ATTR_7_ATTR_BAR0_MASK | 0 ); - - RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_7_ATTR_BAR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_7_OFFSET ,0x0000FFFFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : ATTR_8 @ 0XFD480020

- - Specifies mask/settings for Base Address Register (BAR) 0. If BAR is not to be implemented, set to 32'h00000000. Bits are def - ned as follows: Memory Space BAR [0] = Mem Space Indicator (set to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = - Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory a - erture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR1,BAR0\'7d to 1. IO Space BAR 0] = IO Space Indicator - set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o apert - re size in bytes.; EP=0xFFF0; RP=0x0000 - PSU_PCIE_ATTRIB_ATTR_8_ATTR_BAR0 0x0 - - ATTR_8 - (OFFSET, MASK, VALUE) (0XFD480020, 0x0000FFFFU ,0x00000000U) - RegMask = (PCIE_ATTRIB_ATTR_8_ATTR_BAR0_MASK | 0 ); - - RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_8_ATTR_BAR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_8_OFFSET ,0x0000FFFFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : ATTR_9 @ 0XFD480024

- - Specifies mask/settings for Base Address Register (BAR) 1 if BAR0 is a 32-bit BAR, or the upper bits of \'7bBAR1,BAR0\'7d if - AR0 is a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR0 description if this functions as the uppe - bits of a 64-bit BAR. Bits are defined as follows: Memory Space BAR (not upper bits of BAR0) [0] = Mem Space Indicator (set - o 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if - 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of - '7bBAR2,BAR1\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable b - ts of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000 - PSU_PCIE_ATTRIB_ATTR_9_ATTR_BAR1 0x0 - - ATTR_9 - (OFFSET, MASK, VALUE) (0XFD480024, 0x0000FFFFU ,0x00000000U) - RegMask = (PCIE_ATTRIB_ATTR_9_ATTR_BAR1_MASK | 0 ); - - RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_9_ATTR_BAR1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_9_OFFSET ,0x0000FFFFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : ATTR_10 @ 0XFD480028

- - Specifies mask/settings for Base Address Register (BAR) 1 if BAR0 is a 32-bit BAR, or the upper bits of \'7bBAR1,BAR0\'7d if - AR0 is a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR0 description if this functions as the uppe - bits of a 64-bit BAR. Bits are defined as follows: Memory Space BAR (not upper bits of BAR0) [0] = Mem Space Indicator (set - o 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if - 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of - '7bBAR2,BAR1\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable b - ts of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000 - PSU_PCIE_ATTRIB_ATTR_10_ATTR_BAR1 0x0 - - ATTR_10 - (OFFSET, MASK, VALUE) (0XFD480028, 0x0000FFFFU ,0x00000000U) - RegMask = (PCIE_ATTRIB_ATTR_10_ATTR_BAR1_MASK | 0 ); - - RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_10_ATTR_BAR1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_10_OFFSET ,0x0000FFFFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : ATTR_11 @ 0XFD48002C

- - For an endpoint, specifies mask/settings for Base Address Register (BAR) 2 if BAR1 is a 32-bit BAR, or the upper bits of \'7b - AR2,BAR1\'7d if BAR1 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR1 descri - tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to 00FF_FFFF. For an endpoin - , bits are defined as follows: Memory Space BAR (not upper bits of BAR1) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi - ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe - most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR3,BAR2\'7d to - . IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper - ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0x0004; RP=0xFFFF - PSU_PCIE_ATTRIB_ATTR_11_ATTR_BAR2 0xFFFF - - ATTR_11 - (OFFSET, MASK, VALUE) (0XFD48002C, 0x0000FFFFU ,0x0000FFFFU) - RegMask = (PCIE_ATTRIB_ATTR_11_ATTR_BAR2_MASK | 0 ); - - RegVal = ((0x0000FFFFU << PCIE_ATTRIB_ATTR_11_ATTR_BAR2_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_11_OFFSET ,0x0000FFFFU ,0x0000FFFFU); - /*############################################################################################################################ */ - - /*Register : ATTR_12 @ 0XFD480030

- - For an endpoint, specifies mask/settings for Base Address Register (BAR) 2 if BAR1 is a 32-bit BAR, or the upper bits of \'7b - AR2,BAR1\'7d if BAR1 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR1 descri - tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to 00FF_FFFF. For an endpoin - , bits are defined as follows: Memory Space BAR (not upper bits of BAR1) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi - ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe - most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR3,BAR2\'7d to - . IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper - ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFF0; RP=0x00FF - PSU_PCIE_ATTRIB_ATTR_12_ATTR_BAR2 0xFF - - ATTR_12 - (OFFSET, MASK, VALUE) (0XFD480030, 0x0000FFFFU ,0x000000FFU) - RegMask = (PCIE_ATTRIB_ATTR_12_ATTR_BAR2_MASK | 0 ); - - RegVal = ((0x000000FFU << PCIE_ATTRIB_ATTR_12_ATTR_BAR2_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_12_OFFSET ,0x0000FFFFU ,0x000000FFU); - /*############################################################################################################################ */ - - /*Register : ATTR_13 @ 0XFD480034

- - For an endpoint, specifies mask/settings for Base Address Register (BAR) 3 if BAR2 is a 32-bit BAR, or the upper bits of \'7b - AR3,BAR2\'7d if BAR2 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR2 descri - tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: FFFF_0000 = IO Limit/Bas - Registers not implemented FFFF_F0F0 = IO Limit/Base Registers use 16-bit decode FFFF_F1F1 = IO Limit/Base Registers use 32-b - t decode For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of BAR2) [0] = Mem Space Indicator (s - t to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; - if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits - f \'7bBAR4,BAR3\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writabl - bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000 - PSU_PCIE_ATTRIB_ATTR_13_ATTR_BAR3 0x0 - - ATTR_13 - (OFFSET, MASK, VALUE) (0XFD480034, 0x0000FFFFU ,0x00000000U) - RegMask = (PCIE_ATTRIB_ATTR_13_ATTR_BAR3_MASK | 0 ); - - RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_13_ATTR_BAR3_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_13_OFFSET ,0x0000FFFFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : ATTR_14 @ 0XFD480038

- - For an endpoint, specifies mask/settings for Base Address Register (BAR) 3 if BAR2 is a 32-bit BAR, or the upper bits of \'7b - AR3,BAR2\'7d if BAR2 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR2 descri - tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: FFFF_0000 = IO Limit/Bas - Registers not implemented FFFF_F0F0 = IO Limit/Base Registers use 16-bit decode FFFF_F1F1 = IO Limit/Base Registers use 32-b - t decode For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of BAR2) [0] = Mem Space Indicator (s - t to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; - if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits - f \'7bBAR4,BAR3\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writabl - bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0xFFFF - PSU_PCIE_ATTRIB_ATTR_14_ATTR_BAR3 0xFFFF - - ATTR_14 - (OFFSET, MASK, VALUE) (0XFD480038, 0x0000FFFFU ,0x0000FFFFU) - RegMask = (PCIE_ATTRIB_ATTR_14_ATTR_BAR3_MASK | 0 ); - - RegVal = ((0x0000FFFFU << PCIE_ATTRIB_ATTR_14_ATTR_BAR3_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_14_OFFSET ,0x0000FFFFU ,0x0000FFFFU); - /*############################################################################################################################ */ - - /*Register : ATTR_15 @ 0XFD48003C

- - For an endpoint, specifies mask/settings for Base Address Register (BAR) 4 if BAR3 is a 32-bit BAR, or the upper bits of \'7b - AR4,BAR3\'7d if BAR3 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR3 descri - tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to FFF0_FFF0. For an endpoin - , bits are defined as follows: Memory Space BAR (not upper bits of BAR3) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi - ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe - most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR5,BAR4\'7d to - . IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper - ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0x0004; RP=0xFFF0 - PSU_PCIE_ATTRIB_ATTR_15_ATTR_BAR4 0xFFF0 - - ATTR_15 - (OFFSET, MASK, VALUE) (0XFD48003C, 0x0000FFFFU ,0x0000FFF0U) - RegMask = (PCIE_ATTRIB_ATTR_15_ATTR_BAR4_MASK | 0 ); - - RegVal = ((0x0000FFF0U << PCIE_ATTRIB_ATTR_15_ATTR_BAR4_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_15_OFFSET ,0x0000FFFFU ,0x0000FFF0U); - /*############################################################################################################################ */ - - /*Register : ATTR_16 @ 0XFD480040

- - For an endpoint, specifies mask/settings for Base Address Register (BAR) 4 if BAR3 is a 32-bit BAR, or the upper bits of \'7b - AR4,BAR3\'7d if BAR3 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR3 descri - tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to FFF0_FFF0. For an endpoin - , bits are defined as follows: Memory Space BAR (not upper bits of BAR3) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi - ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe - most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR5,BAR4\'7d to - . IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper - ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFF0; RP=0xFFF0 - PSU_PCIE_ATTRIB_ATTR_16_ATTR_BAR4 0xFFF0 - - ATTR_16 - (OFFSET, MASK, VALUE) (0XFD480040, 0x0000FFFFU ,0x0000FFF0U) - RegMask = (PCIE_ATTRIB_ATTR_16_ATTR_BAR4_MASK | 0 ); - - RegVal = ((0x0000FFF0U << PCIE_ATTRIB_ATTR_16_ATTR_BAR4_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_16_OFFSET ,0x0000FFFFU ,0x0000FFF0U); - /*############################################################################################################################ */ - - /*Register : ATTR_17 @ 0XFD480044

- - For an endpoint, specifies mask/settings for Base Address Register (BAR) 5 if BAR4 is a 32-bit BAR, or the upper bits of \'7b - AR5,BAR4\'7d if BAR4 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR4 descri - tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: 0000_0000 = Prefetchable - Memory Limit/Base Registers not implemented FFF0_FFF0 = 32-bit Prefetchable Memory Limit/Base implemented FFF1_FFF1 = 64-bit - refetchable Memory Limit/Base implemented For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of B - R4) [0] = Mem Space Indicator (set to 0) [2:1] = Type field (00 for 32-bit; BAR5 cannot be lower part of a 64-bit BAR) [3] = - refetchable (0 or 1) [31:4] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=memory aperture size in - ytes. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set u - permost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0xFFF1 - PSU_PCIE_ATTRIB_ATTR_17_ATTR_BAR5 0xFFF1 - - ATTR_17 - (OFFSET, MASK, VALUE) (0XFD480044, 0x0000FFFFU ,0x0000FFF1U) - RegMask = (PCIE_ATTRIB_ATTR_17_ATTR_BAR5_MASK | 0 ); - - RegVal = ((0x0000FFF1U << PCIE_ATTRIB_ATTR_17_ATTR_BAR5_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_17_OFFSET ,0x0000FFFFU ,0x0000FFF1U); - /*############################################################################################################################ */ - - /*Register : ATTR_18 @ 0XFD480048

- - For an endpoint, specifies mask/settings for Base Address Register (BAR) 5 if BAR4 is a 32-bit BAR, or the upper bits of \'7b - AR5,BAR4\'7d if BAR4 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR4 descri - tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: 0000_0000 = Prefetchable - Memory Limit/Base Registers not implemented FFF0_FFF0 = 32-bit Prefetchable Memory Limit/Base implemented FFF1_FFF1 = 64-bit - refetchable Memory Limit/Base implemented For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of B - R4) [0] = Mem Space Indicator (set to 0) [2:1] = Type field (00 for 32-bit; BAR5 cannot be lower part of a 64-bit BAR) [3] = - refetchable (0 or 1) [31:4] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=memory aperture size in - ytes. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set u - permost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0xFFF1 - PSU_PCIE_ATTRIB_ATTR_18_ATTR_BAR5 0xFFF1 - - ATTR_18 - (OFFSET, MASK, VALUE) (0XFD480048, 0x0000FFFFU ,0x0000FFF1U) - RegMask = (PCIE_ATTRIB_ATTR_18_ATTR_BAR5_MASK | 0 ); - - RegVal = ((0x0000FFF1U << PCIE_ATTRIB_ATTR_18_ATTR_BAR5_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_18_OFFSET ,0x0000FFFFU ,0x0000FFF1U); - /*############################################################################################################################ */ - - /*Register : ATTR_27 @ 0XFD48006C

- - Specifies maximum payload supported. Valid settings are: 0- 128 bytes, 1- 256 bytes, 2- 512 bytes, 3- 1024 bytes. Transferred - to the Device Capabilities register. The values: 4-2048 bytes, 5- 4096 bytes are not supported; EP=0x0001; RP=0x0001 - PSU_PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED 1 - - Endpoint L1 Acceptable Latency. Records the latency that the endpoint can withstand on transitions from L1 state to L0 (if L1 - state supported). Valid settings are: 0h less than 1us, 1h 1 to 2us, 2h 2 to 4us, 3h 4 to 8us, 4h 8 to 16us, 5h 16 to 32us, 6 - 32 to 64us, 7h more than 64us. For Endpoints only. Must be 0h for other devices.; EP=0x0007; RP=0x0000 - PSU_PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY 0x0 - - ATTR_27 - (OFFSET, MASK, VALUE) (0XFD48006C, 0x00000738U ,0x00000100U) - RegMask = (PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_MASK | PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_MASK | 0 ); - - RegVal = ((0x00000001U << PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_SHIFT - | 0x00000000U << PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_27_OFFSET ,0x00000738U ,0x00000100U); - /*############################################################################################################################ */ - - /*Register : ATTR_50 @ 0XFD4800C8

- - Identifies the type of device/port as follows: 0000b PCI Express Endpoint device, 0001b Legacy PCI Express Endpoint device, 0 - 00b Root Port of PCI Express Root Complex, 0101b Upstream Port of PCI Express Switch, 0110b Downstream Port of PCI Express Sw - tch, 0111b PCIE Express to PCI/PCI-X Bridge, 1000b PCI/PCI-X to PCI Express Bridge. Transferred to PCI Express Capabilities r - gister. Must be consistent with IS_SWITCH and UPSTREAM_FACING settings.; EP=0x0000; RP=0x0004 - PSU_PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE 4 - - PCIe Capability's Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capab - lity.; EP=0x009C; RP=0x0000 - PSU_PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR 0 - - ATTR_50 - (OFFSET, MASK, VALUE) (0XFD4800C8, 0x0000FFF0U ,0x00000040U) - RegMask = (PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_MASK | PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_MASK | 0 ); - - RegVal = ((0x00000004U << PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_SHIFT - | 0x00000000U << PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_50_OFFSET ,0x0000FFF0U ,0x00000040U); - /*############################################################################################################################ */ - - /*Register : ATTR_105 @ 0XFD4801A4

- - Number of credits that should be advertised for Completion data received on Virtual Channel 0. The bytes advertised must be l - ss than or equal to the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0172; RP=0x00CD - PSU_PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD 0xCD - - ATTR_105 - (OFFSET, MASK, VALUE) (0XFD4801A4, 0x000007FFU ,0x000000CDU) - RegMask = (PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_MASK | 0 ); - - RegVal = ((0x000000CDU << PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_105_OFFSET ,0x000007FFU ,0x000000CDU); - /*############################################################################################################################ */ - - /*Register : ATTR_106 @ 0XFD4801A8

- - Number of credits that should be advertised for Completion headers received on Virtual Channel 0. The sum of the posted, non - osted, and completion header credits must be <= 80; EP=0x0048; RP=0x0024 - PSU_PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH 0x24 - - Number of credits that should be advertised for Non-Posted headers received on Virtual Channel 0. The number of non posted da - a credits advertised by the block is equal to the number of non posted header credits. The sum of the posted, non posted, and - completion header credits must be <= 80; EP=0x0004; RP=0x000C - PSU_PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH 0xC - - ATTR_106 - (OFFSET, MASK, VALUE) (0XFD4801A8, 0x00003FFFU ,0x00000624U) - RegMask = (PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_MASK | PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_MASK | 0 ); - - RegVal = ((0x00000024U << PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_SHIFT - | 0x0000000CU << PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_106_OFFSET ,0x00003FFFU ,0x00000624U); - /*############################################################################################################################ */ - - /*Register : ATTR_107 @ 0XFD4801AC

- - Number of credits that should be advertised for Non-Posted data received on Virtual Channel 0. The number of non posted data - redits advertised by the block is equal to two times the number of non posted header credits if atomic operations are support - d or is equal to the number of non posted header credits if atomic operations are not supported. The bytes advertised must be - less than or equal to the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0008; RP=0x0018 - PSU_PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD 0x18 - - ATTR_107 - (OFFSET, MASK, VALUE) (0XFD4801AC, 0x000007FFU ,0x00000018U) - RegMask = (PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_MASK | 0 ); - - RegVal = ((0x00000018U << PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_107_OFFSET ,0x000007FFU ,0x00000018U); - /*############################################################################################################################ */ - - /*Register : ATTR_108 @ 0XFD4801B0

- - Number of credits that should be advertised for Posted data received on Virtual Channel 0. The bytes advertised must be less - han or equal to the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0020; RP=0x00B5 - PSU_PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD 0xB5 - - ATTR_108 - (OFFSET, MASK, VALUE) (0XFD4801B0, 0x000007FFU ,0x000000B5U) - RegMask = (PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_MASK | 0 ); - - RegVal = ((0x000000B5U << PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_108_OFFSET ,0x000007FFU ,0x000000B5U); - /*############################################################################################################################ */ - - /*Register : ATTR_109 @ 0XFD4801B4

- - Not currently in use. Invert ECRC generated by block when trn_tecrc_gen_n and trn_terrfwd_n are asserted.; EP=0x0000; RP=0x00 - 0 - PSU_PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV 0x0 - - Enables td bit clear and ECRC trim on received TLP's FALSE == don't trim TRUE == trim.; EP=0x0001; RP=0x0001 - PSU_PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM 0x1 - - Enables ECRC check on received TLP's 0 == don't check 1 == always check 3 == check if enabled by ECRC check enable bit of AER - cap structure; EP=0x0003; RP=0x0003 - PSU_PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK 0x3 - - Index of last packet buffer used by TX TLM (i.e. number of buffers - 1). Calculated from max payload size supported and the n - mber of brams configured for transmit; EP=0x001C; RP=0x001C - PSU_PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET 0x1c - - Number of credits that should be advertised for Posted headers received on Virtual Channel 0. The sum of the posted, non post - d, and completion header credits must be <= 80; EP=0x0004; RP=0x0020 - PSU_PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH 0x20 - - ATTR_109 - (OFFSET, MASK, VALUE) (0XFD4801B4, 0x0000FFFFU ,0x00007E20U) - RegMask = (PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_MASK | PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_MASK | PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_MASK | PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_MASK | PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_MASK | 0 ); - - RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_SHIFT - | 0x00000001U << PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_SHIFT - | 0x00000003U << PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_SHIFT - | 0x0000001CU << PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_SHIFT - | 0x00000020U << PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_109_OFFSET ,0x0000FFFFU ,0x00007E20U); - /*############################################################################################################################ */ - - /*Register : ATTR_34 @ 0XFD480088

- - Specifies values to be transferred to Header Type register. Bit 7 should be set to '0' indicating single-function device. Bit - 0 identifies header as Type 0 or Type 1, with '0' indicating a Type 0 header.; EP=0x0000; RP=0x0001 - PSU_PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE 0x1 - - ATTR_34 - (OFFSET, MASK, VALUE) (0XFD480088, 0x000000FFU ,0x00000001U) - RegMask = (PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_MASK | 0 ); - - RegVal = ((0x00000001U << PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_34_OFFSET ,0x000000FFU ,0x00000001U); - /*############################################################################################################################ */ - - /*Register : ATTR_53 @ 0XFD4800D4

- - PM Capability's Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capabil - ty.; EP=0x0048; RP=0x0060 - PSU_PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR 0x60 - - ATTR_53 - (OFFSET, MASK, VALUE) (0XFD4800D4, 0x000000FFU ,0x00000060U) - RegMask = (PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_MASK | 0 ); - - RegVal = ((0x00000060U << PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_53_OFFSET ,0x000000FFU ,0x00000060U); - /*############################################################################################################################ */ - - /*Register : ATTR_41 @ 0XFD4800A4

- - MSI Per-Vector Masking Capable. The value is transferred to the MSI Control Register[8]. When set, adds Mask and Pending Dwor - to Cap structure; EP=0x0000; RP=0x0000 - PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE 0x0 - - Indicates that the MSI structures exists. If this is FALSE, then the MSI structure cannot be accessed via either the link or - he management port.; EP=0x0001; RP=0x0000 - PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON 0 - - MSI Capability's Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capabi - ity.; EP=0x0060; RP=0x0000 - PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR 0x0 - - Indicates that the MSI structures exists. If this is FALSE, then the MSI structure cannot be accessed via either the link or - he management port.; EP=0x0001; RP=0x0000 - PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON 0 - - ATTR_41 - (OFFSET, MASK, VALUE) (0XFD4800A4, 0x000003FFU ,0x00000000U) - RegMask = (PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_MASK | PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_MASK | PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_MASK | PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_MASK | 0 ); - - RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_SHIFT - | 0x00000000U << PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_SHIFT - | 0x00000000U << PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_SHIFT - | 0x00000000U << PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_41_OFFSET ,0x000003FFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : ATTR_97 @ 0XFD480184

- - Maximum Link Width. Valid settings are: 000001b x1, 000010b x2, 000100b x4, 001000b x8.; EP=0x0004; RP=0x0004 - PSU_PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH 0x1 - - Used by LTSSM to set Maximum Link Width. Valid settings are: 000001b [x1], 000010b [x2], 000100b [x4], 001000b [x8].; EP=0x00 - 4; RP=0x0004 - PSU_PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH 0x1 - - ATTR_97 - (OFFSET, MASK, VALUE) (0XFD480184, 0x00000FFFU ,0x00000041U) - RegMask = (PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_MASK | PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_MASK | 0 ); - - RegVal = ((0x00000001U << PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_SHIFT - | 0x00000001U << PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_97_OFFSET ,0x00000FFFU ,0x00000041U); - /*############################################################################################################################ */ - - /*Register : ATTR_100 @ 0XFD480190

- - TRUE specifies upstream-facing port. FALSE specifies downstream-facing port.; EP=0x0001; RP=0x0000 - PSU_PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING 0x0 - - ATTR_100 - (OFFSET, MASK, VALUE) (0XFD480190, 0x00000040U ,0x00000000U) - RegMask = (PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_MASK | 0 ); - - RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_100_OFFSET ,0x00000040U ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : ATTR_101 @ 0XFD480194

- - Enable the routing of message TLPs to the user through the TRN RX interface. A bit value of 1 enables routing of the message - LP to the user. Messages are always decoded by the message decoder. Bit 0 - ERR COR, Bit 1 - ERR NONFATAL, Bit 2 - ERR FATAL, - Bit 3 - INTA Bit 4 - INTB, Bit 5 - INTC, Bit 6 - INTD, Bit 7 PM_PME, Bit 8 - PME_TO_ACK, Bit 9 - unlock, Bit 10 PME_Turn_Off; - EP=0x0000; RP=0x07FF - PSU_PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE 0x7FF - - Disable BAR filtering. Does not change the behavior of the bar hit outputs; EP=0x0000; RP=0x0001 - PSU_PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING 0x1 - - ATTR_101 - (OFFSET, MASK, VALUE) (0XFD480194, 0x0000FFE2U ,0x0000FFE2U) - RegMask = (PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_MASK | PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_MASK | 0 ); - - RegVal = ((0x000007FFU << PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_SHIFT - | 0x00000001U << PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_101_OFFSET ,0x0000FFE2U ,0x0000FFE2U); - /*############################################################################################################################ */ - - /*Register : ATTR_37 @ 0XFD480094

- - Link Bandwidth notification capability. Indicates support for the link bandwidth notification status and interrupt mechanism. - Required for Root.; EP=0x0000; RP=0x0001 - PSU_PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP 0x1 - - Sets the ASPM Optionality Compliance bit, to comply with the 2.1 ASPM Optionality ECN. Transferred to the Link Capabilities r - gister.; EP=0x0001; RP=0x0001 - PSU_PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY 0x1 - - ATTR_37 - (OFFSET, MASK, VALUE) (0XFD480094, 0x00004200U ,0x00004200U) - RegMask = (PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_MASK | PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_MASK | 0 ); - - RegVal = ((0x00000001U << PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_SHIFT - | 0x00000001U << PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_37_OFFSET ,0x00004200U ,0x00004200U); - /*############################################################################################################################ */ - - /*Register : ATTR_93 @ 0XFD480174

- - Enables the Replay Timer to use the user-defined LL_REPLAY_TIMEOUT value (or combined with the built-in value, depending on L - _REPLAY_TIMEOUT_FUNC). If FALSE, the built-in value is used.; EP=0x0000; RP=0x0000 - PSU_PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN 0x1 - - Sets a user-defined timeout for the Replay Timer to force cause the retransmission of unacknowledged TLPs; refer to LL_REPLAY - TIMEOUT_EN and LL_REPLAY_TIMEOUT_FUNC to see how this value is used. The unit for this attribute is in symbol times, which is - 4ns at GEN1 speeds and 2ns at GEN2.; EP=0x0000; RP=0x0000 - PSU_PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT 0x1000 - - ATTR_93 - (OFFSET, MASK, VALUE) (0XFD480174, 0x0000FFFFU ,0x00009000U) - RegMask = (PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_MASK | PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_MASK | 0 ); - - RegVal = ((0x00000001U << PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_SHIFT - | 0x00001000U << PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_93_OFFSET ,0x0000FFFFU ,0x00009000U); - /*############################################################################################################################ */ - - /*Register : ID @ 0XFD480200

- - Device ID for the the PCIe Cap Structure Device ID field - PSU_PCIE_ATTRIB_ID_CFG_DEV_ID 0xd021 - - Vendor ID for the PCIe Cap Structure Vendor ID field - PSU_PCIE_ATTRIB_ID_CFG_VEND_ID 0x10ee - - ID - (OFFSET, MASK, VALUE) (0XFD480200, 0xFFFFFFFFU ,0x10EED021U) - RegMask = (PCIE_ATTRIB_ID_CFG_DEV_ID_MASK | PCIE_ATTRIB_ID_CFG_VEND_ID_MASK | 0 ); - - RegVal = ((0x0000D021U << PCIE_ATTRIB_ID_CFG_DEV_ID_SHIFT - | 0x000010EEU << PCIE_ATTRIB_ID_CFG_VEND_ID_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ID_OFFSET ,0xFFFFFFFFU ,0x10EED021U); - /*############################################################################################################################ */ - - /*Register : SUBSYS_ID @ 0XFD480204

- - Subsystem ID for the the PCIe Cap Structure Subsystem ID field - PSU_PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID 0x7 - - Subsystem Vendor ID for the PCIe Cap Structure Subsystem Vendor ID field - PSU_PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID 0x10ee - - SUBSYS_ID - (OFFSET, MASK, VALUE) (0XFD480204, 0xFFFFFFFFU ,0x10EE0007U) - RegMask = (PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_MASK | PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_MASK | 0 ); - - RegVal = ((0x00000007U << PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_SHIFT - | 0x000010EEU << PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_SUBSYS_ID_OFFSET ,0xFFFFFFFFU ,0x10EE0007U); - /*############################################################################################################################ */ - - /*Register : REV_ID @ 0XFD480208

- - Revision ID for the the PCIe Cap Structure - PSU_PCIE_ATTRIB_REV_ID_CFG_REV_ID 0x0 - - REV_ID - (OFFSET, MASK, VALUE) (0XFD480208, 0x000000FFU ,0x00000000U) - RegMask = (PCIE_ATTRIB_REV_ID_CFG_REV_ID_MASK | 0 ); - - RegVal = ((0x00000000U << PCIE_ATTRIB_REV_ID_CFG_REV_ID_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_REV_ID_OFFSET ,0x000000FFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : ATTR_24 @ 0XFD480060

- - Code identifying basic function, subclass and applicable programming interface. Transferred to the Class Code register.; EP=0 - 8000; RP=0x8000 - PSU_PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE 0x400 - - ATTR_24 - (OFFSET, MASK, VALUE) (0XFD480060, 0x0000FFFFU ,0x00000400U) - RegMask = (PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_MASK | 0 ); - - RegVal = ((0x00000400U << PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_24_OFFSET ,0x0000FFFFU ,0x00000400U); - /*############################################################################################################################ */ - - /*Register : ATTR_25 @ 0XFD480064

- - Code identifying basic function, subclass and applicable programming interface. Transferred to the Class Code register.; EP=0 - 0005; RP=0x0006 - PSU_PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE 0x6 - - INTX Interrupt Generation Capable. If FALSE, this will cause Command[10] to be hardwired to 0.; EP=0x0001; RP=0x0001 - PSU_PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED 0 - - ATTR_25 - (OFFSET, MASK, VALUE) (0XFD480064, 0x000001FFU ,0x00000006U) - RegMask = (PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_MASK | PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_MASK | 0 ); - - RegVal = ((0x00000006U << PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_SHIFT - | 0x00000000U << PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_25_OFFSET ,0x000001FFU ,0x00000006U); - /*############################################################################################################################ */ - - /*Register : ATTR_4 @ 0XFD480010

- - Indicates that the AER structures exists. If this is FALSE, then the AER structure cannot be accessed via either the link or - he management port, and AER will be considered to not be present for error management tasks (such as what types of error mess - ges are sent if an error is detected).; EP=0x0001; RP=0x0001 - PSU_PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON 0 - - Indicates that the AER structures exists. If this is FALSE, then the AER structure cannot be accessed via either the link or - he management port, and AER will be considered to not be present for error management tasks (such as what types of error mess - ges are sent if an error is detected).; EP=0x0001; RP=0x0001 - PSU_PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON 0 - - ATTR_4 - (OFFSET, MASK, VALUE) (0XFD480010, 0x00001000U ,0x00000000U) - RegMask = (PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_MASK | PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_MASK | 0 ); - - RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_SHIFT - | 0x00000000U << PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_4_OFFSET ,0x00001000U ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : ATTR_89 @ 0XFD480164

- - VSEC's Next Capability Offset pointer to the next item in the capabilities list, or 000h if this is the final capability.; EP - 0x0140; RP=0x0140 - PSU_PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR 0 - - ATTR_89 - (OFFSET, MASK, VALUE) (0XFD480164, 0x00001FFEU ,0x00000000U) - RegMask = (PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_MASK | 0 ); - - RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_89_OFFSET ,0x00001FFEU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : ATTR_79 @ 0XFD48013C

- - CRS SW Visibility. Indicates RC can return CRS to SW. Transferred to the Root Capabilities register.; EP=0x0000; RP=0x0000 - PSU_PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY 1 - - ATTR_79 - (OFFSET, MASK, VALUE) (0XFD48013C, 0x00000020U ,0x00000020U) - RegMask = (PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_MASK | 0 ); - - RegVal = ((0x00000001U << PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_79_OFFSET ,0x00000020U ,0x00000020U); - /*############################################################################################################################ */ - - /*Register : ATTR_43 @ 0XFD4800AC

- - Indicates that the MSIX structures exists. If this is FALSE, then the MSIX structure cannot be accessed via either the link o - the management port.; EP=0x0001; RP=0x0000 - PSU_PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON 0 - - ATTR_43 - (OFFSET, MASK, VALUE) (0XFD4800AC, 0x00000100U ,0x00000000U) - RegMask = (PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_MASK | 0 ); - - RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_43_OFFSET ,0x00000100U ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : ATTR_48 @ 0XFD4800C0

- - MSI-X Table Size. This value is transferred to the MSI-X Message Control[10:0] field. Set to 0 if MSI-X is not enabled. Note - hat the core does not implement the table; that must be implemented in user logic.; EP=0x0003; RP=0x0000 - PSU_PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE 0 - - ATTR_48 - (OFFSET, MASK, VALUE) (0XFD4800C0, 0x000007FFU ,0x00000000U) - RegMask = (PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_MASK | 0 ); - - RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_48_OFFSET ,0x000007FFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : ATTR_46 @ 0XFD4800B8

- - MSI-X Table Offset. This value is transferred to the MSI-X Table Offset field. Set to 0 if MSI-X is not enabled.; EP=0x0001; - P=0x0000 - PSU_PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET 0 - - ATTR_46 - (OFFSET, MASK, VALUE) (0XFD4800B8, 0x0000FFFFU ,0x00000000U) - RegMask = (PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_MASK | 0 ); - - RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_46_OFFSET ,0x0000FFFFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : ATTR_47 @ 0XFD4800BC

- - MSI-X Table Offset. This value is transferred to the MSI-X Table Offset field. Set to 0 if MSI-X is not enabled.; EP=0x0000; - P=0x0000 - PSU_PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET 0 - - ATTR_47 - (OFFSET, MASK, VALUE) (0XFD4800BC, 0x00001FFFU ,0x00000000U) - RegMask = (PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_MASK | 0 ); - - RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_47_OFFSET ,0x00001FFFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : ATTR_44 @ 0XFD4800B0

- - MSI-X Pending Bit Array Offset This value is transferred to the MSI-X PBA Offset field. Set to 0 if MSI-X is not enabled.; EP - 0x0001; RP=0x0000 - PSU_PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET 0 - - ATTR_44 - (OFFSET, MASK, VALUE) (0XFD4800B0, 0x0000FFFFU ,0x00000000U) - RegMask = (PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_MASK | 0 ); - - RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_44_OFFSET ,0x0000FFFFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : ATTR_45 @ 0XFD4800B4

- - MSI-X Pending Bit Array Offset This value is transferred to the MSI-X PBA Offset field. Set to 0 if MSI-X is not enabled.; EP - 0x1000; RP=0x0000 - PSU_PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET 0 - - ATTR_45 - (OFFSET, MASK, VALUE) (0XFD4800B4, 0x0000FFF8U ,0x00000000U) - RegMask = (PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_MASK | 0 ); - - RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_45_OFFSET ,0x0000FFF8U ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : CB @ 0XFD48031C

- - DT837748 Enable - PSU_PCIE_ATTRIB_CB_CB1 0x0 - - ECO Register 1 - (OFFSET, MASK, VALUE) (0XFD48031C, 0x00000002U ,0x00000000U) - RegMask = (PCIE_ATTRIB_CB_CB1_MASK | 0 ); - - RegVal = ((0x00000000U << PCIE_ATTRIB_CB_CB1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_CB_OFFSET ,0x00000002U ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : ATTR_35 @ 0XFD48008C

- - Active State PM Support. Indicates the level of active state power management supported by the selected PCI Express Link, enc - ded as follows: 0 Reserved, 1 L0s entry supported, 2 Reserved, 3 L0s and L1 entry supported.; EP=0x0001; RP=0x0001 - PSU_PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT 0x0 - - ATTR_35 - (OFFSET, MASK, VALUE) (0XFD48008C, 0x00003000U ,0x00000000U) - RegMask = (PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_MASK | 0 ); - - RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_35_OFFSET ,0x00003000U ,0x00000000U); - /*############################################################################################################################ */ - - // : PUTTING PCIE CONTROL IN RESET - /*Register : RST_FPD_TOP @ 0XFD1A0100

- - PCIE control block level reset - PSU_CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET 0X0 - - FPD Block level software controlled reset - (OFFSET, MASK, VALUE) (0XFD1A0100, 0x00020000U ,0x00000000U) - RegMask = (CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK | 0 ); - - RegVal = ((0x00000000U << CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_RST_FPD_TOP_OFFSET ,0x00020000U ,0x00000000U); - /*############################################################################################################################ */ - - // : CHECK PLL LOCK FOR LANE0 - /*Register : L0_PLL_STATUS_READ_1 @ 0XFD4023E4

- - Status Read value of PLL Lock - PSU_SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1 - (OFFSET, MASK, VALUE) (0XFD4023E4, 0x00000010U ,0x00000010U) */ - mask_poll(SERDES_L0_PLL_STATUS_READ_1_OFFSET,0x00000010U); - - /*############################################################################################################################ */ - - // : CHECK PLL LOCK FOR LANE1 - /*Register : L1_PLL_STATUS_READ_1 @ 0XFD4063E4

- - Status Read value of PLL Lock - PSU_SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1 - (OFFSET, MASK, VALUE) (0XFD4063E4, 0x00000010U ,0x00000010U) */ - mask_poll(SERDES_L1_PLL_STATUS_READ_1_OFFSET,0x00000010U); - - /*############################################################################################################################ */ - - // : CHECK PLL LOCK FOR LANE2 - /*Register : L2_PLL_STATUS_READ_1 @ 0XFD40A3E4

- - Status Read value of PLL Lock - PSU_SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1 - (OFFSET, MASK, VALUE) (0XFD40A3E4, 0x00000010U ,0x00000010U) */ - mask_poll(SERDES_L2_PLL_STATUS_READ_1_OFFSET,0x00000010U); - - /*############################################################################################################################ */ - - // : CHECK PLL LOCK FOR LANE3 - /*Register : L3_PLL_STATUS_READ_1 @ 0XFD40E3E4

- - Status Read value of PLL Lock - PSU_SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1 - (OFFSET, MASK, VALUE) (0XFD40E3E4, 0x00000010U ,0x00000010U) */ - mask_poll(SERDES_L3_PLL_STATUS_READ_1_OFFSET,0x00000010U); - - /*############################################################################################################################ */ - - // : SATA AHCI VENDOR SETTING - /*Register : PP2C @ 0XFD0C00AC

- - CIBGMN: COMINIT Burst Gap Minimum. - PSU_SATA_AHCI_VENDOR_PP2C_CIBGMN 0x18 - - CIBGMX: COMINIT Burst Gap Maximum. - PSU_SATA_AHCI_VENDOR_PP2C_CIBGMX 0x40 - - CIBGN: COMINIT Burst Gap Nominal. - PSU_SATA_AHCI_VENDOR_PP2C_CIBGN 0x18 - - CINMP: COMINIT Negate Minimum Period. - PSU_SATA_AHCI_VENDOR_PP2C_CINMP 0x28 - - PP2C - Port Phy2Cfg Register. This register controls the configuration of the Phy Control OOB timing for the COMINIT paramete - s for either Port 0 or Port 1. The Port configured is controlled by the value programmed into the Port Config Register. - (OFFSET, MASK, VALUE) (0XFD0C00AC, 0xFFFFFFFFU ,0x28184018U) - RegMask = (SATA_AHCI_VENDOR_PP2C_CIBGMN_MASK | SATA_AHCI_VENDOR_PP2C_CIBGMX_MASK | SATA_AHCI_VENDOR_PP2C_CIBGN_MASK | SATA_AHCI_VENDOR_PP2C_CINMP_MASK | 0 ); - - RegVal = ((0x00000018U << SATA_AHCI_VENDOR_PP2C_CIBGMN_SHIFT - | 0x00000040U << SATA_AHCI_VENDOR_PP2C_CIBGMX_SHIFT - | 0x00000018U << SATA_AHCI_VENDOR_PP2C_CIBGN_SHIFT - | 0x00000028U << SATA_AHCI_VENDOR_PP2C_CINMP_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SATA_AHCI_VENDOR_PP2C_OFFSET ,0xFFFFFFFFU ,0x28184018U); - /*############################################################################################################################ */ - - /*Register : PP3C @ 0XFD0C00B0

- - CWBGMN: COMWAKE Burst Gap Minimum. - PSU_SATA_AHCI_VENDOR_PP3C_CWBGMN 0x06 - - CWBGMX: COMWAKE Burst Gap Maximum. - PSU_SATA_AHCI_VENDOR_PP3C_CWBGMX 0x14 - - CWBGN: COMWAKE Burst Gap Nominal. - PSU_SATA_AHCI_VENDOR_PP3C_CWBGN 0x08 - - CWNMP: COMWAKE Negate Minimum Period. - PSU_SATA_AHCI_VENDOR_PP3C_CWNMP 0x0E - - PP3C - Port Phy3CfgRegister. This register controls the configuration of the Phy Control OOB timing for the COMWAKE parameter - for either Port 0 or Port 1. The Port configured is controlled by the value programmed into the Port Config Register. - (OFFSET, MASK, VALUE) (0XFD0C00B0, 0xFFFFFFFFU ,0x0E081406U) - RegMask = (SATA_AHCI_VENDOR_PP3C_CWBGMN_MASK | SATA_AHCI_VENDOR_PP3C_CWBGMX_MASK | SATA_AHCI_VENDOR_PP3C_CWBGN_MASK | SATA_AHCI_VENDOR_PP3C_CWNMP_MASK | 0 ); - - RegVal = ((0x00000006U << SATA_AHCI_VENDOR_PP3C_CWBGMN_SHIFT - | 0x00000014U << SATA_AHCI_VENDOR_PP3C_CWBGMX_SHIFT - | 0x00000008U << SATA_AHCI_VENDOR_PP3C_CWBGN_SHIFT - | 0x0000000EU << SATA_AHCI_VENDOR_PP3C_CWNMP_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SATA_AHCI_VENDOR_PP3C_OFFSET ,0xFFFFFFFFU ,0x0E081406U); - /*############################################################################################################################ */ - - /*Register : PP4C @ 0XFD0C00B4

- - BMX: COM Burst Maximum. - PSU_SATA_AHCI_VENDOR_PP4C_BMX 0x13 - - BNM: COM Burst Nominal. - PSU_SATA_AHCI_VENDOR_PP4C_BNM 0x08 - - SFD: Signal Failure Detection, if the signal detection de-asserts for a time greater than this then the OOB detector will det - rmine this is a line idle and cause the PhyInit state machine to exit the Phy Ready State. A value of zero disables the Signa - Failure Detector. The value is based on the OOB Detector Clock typically (PMCLK Clock Period) * SFD giving a nominal time of - 500ns based on a 150MHz PMCLK. - PSU_SATA_AHCI_VENDOR_PP4C_SFD 0x4A - - PTST: Partial to Slumber timer value, specific delay the controller should apply while in partial before entering slumber. Th - value is bases on the system clock divided by 128, total delay = (Sys Clock Period) * PTST * 128 - PSU_SATA_AHCI_VENDOR_PP4C_PTST 0x06 - - PP4C - Port Phy4Cfg Register. This register controls the configuration of the Phy Control Burst timing for the COM parameters - for either Port 0 or Port 1. The Port configured is controlled by the value programmed into the Port Config Register. - (OFFSET, MASK, VALUE) (0XFD0C00B4, 0xFFFFFFFFU ,0x064A0813U) - RegMask = (SATA_AHCI_VENDOR_PP4C_BMX_MASK | SATA_AHCI_VENDOR_PP4C_BNM_MASK | SATA_AHCI_VENDOR_PP4C_SFD_MASK | SATA_AHCI_VENDOR_PP4C_PTST_MASK | 0 ); - - RegVal = ((0x00000013U << SATA_AHCI_VENDOR_PP4C_BMX_SHIFT - | 0x00000008U << SATA_AHCI_VENDOR_PP4C_BNM_SHIFT - | 0x0000004AU << SATA_AHCI_VENDOR_PP4C_SFD_SHIFT - | 0x00000006U << SATA_AHCI_VENDOR_PP4C_PTST_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SATA_AHCI_VENDOR_PP4C_OFFSET ,0xFFFFFFFFU ,0x064A0813U); - /*############################################################################################################################ */ - - /*Register : PP5C @ 0XFD0C00B8

- - RIT: Retry Interval Timer. The calculated value divided by two, the lower digit of precision is not needed. - PSU_SATA_AHCI_VENDOR_PP5C_RIT 0xC96A4 - - RCT: Rate Change Timer, a value based on the 54.2us for which a SATA device will transmit at a fixed rate ALIGNp after OOB ha - completed, for a fast SERDES it is suggested that this value be 54.2us / 4 - PSU_SATA_AHCI_VENDOR_PP5C_RCT 0x3FF - - PP5C - Port Phy5Cfg Register. This register controls the configuration of the Phy Control Retry Interval timing for either Po - t 0 or Port 1. The Port configured is controlled by the value programmed into the Port Config Register. - (OFFSET, MASK, VALUE) (0XFD0C00B8, 0xFFFFFFFFU ,0x3FFC96A4U) - RegMask = (SATA_AHCI_VENDOR_PP5C_RIT_MASK | SATA_AHCI_VENDOR_PP5C_RCT_MASK | 0 ); - - RegVal = ((0x000C96A4U << SATA_AHCI_VENDOR_PP5C_RIT_SHIFT - | 0x000003FFU << SATA_AHCI_VENDOR_PP5C_RCT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SATA_AHCI_VENDOR_PP5C_OFFSET ,0xFFFFFFFFU ,0x3FFC96A4U); - /*############################################################################################################################ */ - - - return 1; + * MPHY PLL Gear and bypass scrambler + * (OFFSET, MASK, VALUE) (0XFD40C0F4, 0x0000000BU ,0x0000000BU) + */ + PSU_Mask_Write(SERDES_L3_TX_DIG_TM_61_OFFSET, + 0x0000000BU, 0x0000000BU); +/*##################################################################### */ + + /* + * ENABLE CHICKEN BIT FOR PCIE AND USB + */ + /* + * Register : L0_TM_AUX_0 @ 0XFD4010CC + + * Spare- not used + * PSU_SERDES_L0_TM_AUX_0_BIT_2 1 + + * Spare registers + * (OFFSET, MASK, VALUE) (0XFD4010CC, 0x00000020U ,0x00000020U) + */ + PSU_Mask_Write(SERDES_L0_TM_AUX_0_OFFSET, 0x00000020U, 0x00000020U); +/*##################################################################### */ + + /* + * Register : L2_TM_AUX_0 @ 0XFD4090CC + + * Spare- not used + * PSU_SERDES_L2_TM_AUX_0_BIT_2 1 + + * Spare registers + * (OFFSET, MASK, VALUE) (0XFD4090CC, 0x00000020U ,0x00000020U) + */ + PSU_Mask_Write(SERDES_L2_TM_AUX_0_OFFSET, 0x00000020U, 0x00000020U); +/*##################################################################### */ + + /* + * ENABLING EYE SURF + */ + /* + * Register : L0_TM_DIG_8 @ 0XFD401074 + + * Enable Eye Surf + * PSU_SERDES_L0_TM_DIG_8_EYESURF_ENABLE 0x1 + + * Test modes for Elastic buffer and enabling Eye Surf + * (OFFSET, MASK, VALUE) (0XFD401074, 0x00000010U ,0x00000010U) + */ + PSU_Mask_Write(SERDES_L0_TM_DIG_8_OFFSET, 0x00000010U, 0x00000010U); +/*##################################################################### */ + + /* + * Register : L1_TM_DIG_8 @ 0XFD405074 + + * Enable Eye Surf + * PSU_SERDES_L1_TM_DIG_8_EYESURF_ENABLE 0x1 + + * Test modes for Elastic buffer and enabling Eye Surf + * (OFFSET, MASK, VALUE) (0XFD405074, 0x00000010U ,0x00000010U) + */ + PSU_Mask_Write(SERDES_L1_TM_DIG_8_OFFSET, 0x00000010U, 0x00000010U); +/*##################################################################### */ + + /* + * Register : L2_TM_DIG_8 @ 0XFD409074 + + * Enable Eye Surf + * PSU_SERDES_L2_TM_DIG_8_EYESURF_ENABLE 0x1 + + * Test modes for Elastic buffer and enabling Eye Surf + * (OFFSET, MASK, VALUE) (0XFD409074, 0x00000010U ,0x00000010U) + */ + PSU_Mask_Write(SERDES_L2_TM_DIG_8_OFFSET, 0x00000010U, 0x00000010U); +/*##################################################################### */ + + /* + * Register : L3_TM_DIG_8 @ 0XFD40D074 + + * Enable Eye Surf + * PSU_SERDES_L3_TM_DIG_8_EYESURF_ENABLE 0x1 + + * Test modes for Elastic buffer and enabling Eye Surf + * (OFFSET, MASK, VALUE) (0XFD40D074, 0x00000010U ,0x00000010U) + */ + PSU_Mask_Write(SERDES_L3_TM_DIG_8_OFFSET, 0x00000010U, 0x00000010U); +/*##################################################################### */ + + /* + * ILL SETTINGS FOR GAIN AND LOCK SETTINGS + */ + /* + * Register : L0_TM_MISC2 @ 0XFD40189C + + * ILL calib counts BYPASSED with calcode bits + * PSU_SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS 0x1 + + * sampler cal + * (OFFSET, MASK, VALUE) (0XFD40189C, 0x00000080U ,0x00000080U) + */ + PSU_Mask_Write(SERDES_L0_TM_MISC2_OFFSET, 0x00000080U, 0x00000080U); +/*##################################################################### */ + + /* + * Register : L0_TM_IQ_ILL1 @ 0XFD4018F8 + + * IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , + * USB3 : SS + * PSU_SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0 0x64 + + * iqpi cal code + * (OFFSET, MASK, VALUE) (0XFD4018F8, 0x000000FFU ,0x00000064U) + */ + PSU_Mask_Write(SERDES_L0_TM_IQ_ILL1_OFFSET, + 0x000000FFU, 0x00000064U); +/*##################################################################### */ + + /* + * Register : L0_TM_IQ_ILL2 @ 0XFD4018FC + + * IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 + * PSU_SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1 0x64 + + * iqpi cal code + * (OFFSET, MASK, VALUE) (0XFD4018FC, 0x000000FFU ,0x00000064U) + */ + PSU_Mask_Write(SERDES_L0_TM_IQ_ILL2_OFFSET, + 0x000000FFU, 0x00000064U); +/*##################################################################### */ + + /* + * Register : L0_TM_ILL12 @ 0XFD401990 + + * G1A pll ctr bypass value + * PSU_SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL 0x11 + + * ill pll counter values + * (OFFSET, MASK, VALUE) (0XFD401990, 0x000000FFU ,0x00000011U) + */ + PSU_Mask_Write(SERDES_L0_TM_ILL12_OFFSET, 0x000000FFU, 0x00000011U); +/*##################################################################### */ + + /* + * Register : L0_TM_E_ILL1 @ 0XFD401924 + + * E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , U + * SB3 : SS + * PSU_SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0 0x4 + + * epi cal code + * (OFFSET, MASK, VALUE) (0XFD401924, 0x000000FFU ,0x00000004U) + */ + PSU_Mask_Write(SERDES_L0_TM_E_ILL1_OFFSET, 0x000000FFU, 0x00000004U); +/*##################################################################### */ + + /* + * Register : L0_TM_E_ILL2 @ 0XFD401928 + + * E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 + * PSU_SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1 0xFE + + * epi cal code + * (OFFSET, MASK, VALUE) (0XFD401928, 0x000000FFU ,0x000000FEU) + */ + PSU_Mask_Write(SERDES_L0_TM_E_ILL2_OFFSET, 0x000000FFU, 0x000000FEU); +/*##################################################################### */ + + /* + * Register : L0_TM_IQ_ILL3 @ 0XFD401900 + + * IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 + * PSU_SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2 0x64 + + * iqpi cal code + * (OFFSET, MASK, VALUE) (0XFD401900, 0x000000FFU ,0x00000064U) + */ + PSU_Mask_Write(SERDES_L0_TM_IQ_ILL3_OFFSET, + 0x000000FFU, 0x00000064U); +/*##################################################################### */ + + /* + * Register : L0_TM_E_ILL3 @ 0XFD40192C + + * E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 + * PSU_SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2 0x0 + + * epi cal code + * (OFFSET, MASK, VALUE) (0XFD40192C, 0x000000FFU ,0x00000000U) + */ + PSU_Mask_Write(SERDES_L0_TM_E_ILL3_OFFSET, 0x000000FFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : L0_TM_ILL8 @ 0XFD401980 + + * ILL calibration code change wait time + * PSU_SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT 0xFF + + * ILL cal routine control + * (OFFSET, MASK, VALUE) (0XFD401980, 0x000000FFU ,0x000000FFU) + */ + PSU_Mask_Write(SERDES_L0_TM_ILL8_OFFSET, 0x000000FFU, 0x000000FFU); +/*##################################################################### */ + + /* + * Register : L0_TM_IQ_ILL8 @ 0XFD401914 + + * IQ ILL polytrim bypass value + * PSU_SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL 0xF7 + + * iqpi polytrim + * (OFFSET, MASK, VALUE) (0XFD401914, 0x000000FFU ,0x000000F7U) + */ + PSU_Mask_Write(SERDES_L0_TM_IQ_ILL8_OFFSET, + 0x000000FFU, 0x000000F7U); +/*##################################################################### */ + + /* + * Register : L0_TM_IQ_ILL9 @ 0XFD401918 + + * bypass IQ polytrim + * PSU_SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM 0x1 + + * enables for lf,constant gm trim and polytirm + * (OFFSET, MASK, VALUE) (0XFD401918, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L0_TM_IQ_ILL9_OFFSET, + 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : L0_TM_E_ILL8 @ 0XFD401940 + + * E ILL polytrim bypass value + * PSU_SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL 0xF7 + + * epi polytrim + * (OFFSET, MASK, VALUE) (0XFD401940, 0x000000FFU ,0x000000F7U) + */ + PSU_Mask_Write(SERDES_L0_TM_E_ILL8_OFFSET, 0x000000FFU, 0x000000F7U); +/*##################################################################### */ + + /* + * Register : L0_TM_E_ILL9 @ 0XFD401944 + + * bypass E polytrim + * PSU_SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM 0x1 + + * enables for lf,constant gm trim and polytirm + * (OFFSET, MASK, VALUE) (0XFD401944, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L0_TM_E_ILL9_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : L0_TM_ILL13 @ 0XFD401994 + + * ILL cal idle val refcnt + * PSU_SERDES_L0_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT 0x7 + + * ill cal idle value count + * (OFFSET, MASK, VALUE) (0XFD401994, 0x00000007U ,0x00000007U) + */ + PSU_Mask_Write(SERDES_L0_TM_ILL13_OFFSET, 0x00000007U, 0x00000007U); +/*##################################################################### */ + + /* + * Register : L1_TM_ILL13 @ 0XFD405994 + + * ILL cal idle val refcnt + * PSU_SERDES_L1_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT 0x7 + + * ill cal idle value count + * (OFFSET, MASK, VALUE) (0XFD405994, 0x00000007U ,0x00000007U) + */ + PSU_Mask_Write(SERDES_L1_TM_ILL13_OFFSET, 0x00000007U, 0x00000007U); +/*##################################################################### */ + + /* + * Register : L2_TM_MISC2 @ 0XFD40989C + + * ILL calib counts BYPASSED with calcode bits + * PSU_SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS 0x1 + + * sampler cal + * (OFFSET, MASK, VALUE) (0XFD40989C, 0x00000080U ,0x00000080U) + */ + PSU_Mask_Write(SERDES_L2_TM_MISC2_OFFSET, 0x00000080U, 0x00000080U); +/*##################################################################### */ + + /* + * Register : L2_TM_IQ_ILL1 @ 0XFD4098F8 + + * IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , + * USB3 : SS + * PSU_SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0 0x1A + + * iqpi cal code + * (OFFSET, MASK, VALUE) (0XFD4098F8, 0x000000FFU ,0x0000001AU) + */ + PSU_Mask_Write(SERDES_L2_TM_IQ_ILL1_OFFSET, + 0x000000FFU, 0x0000001AU); +/*##################################################################### */ + + /* + * Register : L2_TM_IQ_ILL2 @ 0XFD4098FC + + * IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 + * PSU_SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1 0x1A + + * iqpi cal code + * (OFFSET, MASK, VALUE) (0XFD4098FC, 0x000000FFU ,0x0000001AU) + */ + PSU_Mask_Write(SERDES_L2_TM_IQ_ILL2_OFFSET, + 0x000000FFU, 0x0000001AU); +/*##################################################################### */ + + /* + * Register : L2_TM_ILL12 @ 0XFD409990 + + * G1A pll ctr bypass value + * PSU_SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL 0x10 + + * ill pll counter values + * (OFFSET, MASK, VALUE) (0XFD409990, 0x000000FFU ,0x00000010U) + */ + PSU_Mask_Write(SERDES_L2_TM_ILL12_OFFSET, 0x000000FFU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : L2_TM_E_ILL1 @ 0XFD409924 + + * E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , U + * SB3 : SS + * PSU_SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0 0xFE + + * epi cal code + * (OFFSET, MASK, VALUE) (0XFD409924, 0x000000FFU ,0x000000FEU) + */ + PSU_Mask_Write(SERDES_L2_TM_E_ILL1_OFFSET, 0x000000FFU, 0x000000FEU); +/*##################################################################### */ + + /* + * Register : L2_TM_E_ILL2 @ 0XFD409928 + + * E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 + * PSU_SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1 0x0 + + * epi cal code + * (OFFSET, MASK, VALUE) (0XFD409928, 0x000000FFU ,0x00000000U) + */ + PSU_Mask_Write(SERDES_L2_TM_E_ILL2_OFFSET, 0x000000FFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : L2_TM_IQ_ILL3 @ 0XFD409900 + + * IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 + * PSU_SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2 0x1A + + * iqpi cal code + * (OFFSET, MASK, VALUE) (0XFD409900, 0x000000FFU ,0x0000001AU) + */ + PSU_Mask_Write(SERDES_L2_TM_IQ_ILL3_OFFSET, + 0x000000FFU, 0x0000001AU); +/*##################################################################### */ + + /* + * Register : L2_TM_E_ILL3 @ 0XFD40992C + + * E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 + * PSU_SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2 0x0 + + * epi cal code + * (OFFSET, MASK, VALUE) (0XFD40992C, 0x000000FFU ,0x00000000U) + */ + PSU_Mask_Write(SERDES_L2_TM_E_ILL3_OFFSET, 0x000000FFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : L2_TM_ILL8 @ 0XFD409980 + + * ILL calibration code change wait time + * PSU_SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT 0xFF + + * ILL cal routine control + * (OFFSET, MASK, VALUE) (0XFD409980, 0x000000FFU ,0x000000FFU) + */ + PSU_Mask_Write(SERDES_L2_TM_ILL8_OFFSET, 0x000000FFU, 0x000000FFU); +/*##################################################################### */ + + /* + * Register : L2_TM_IQ_ILL8 @ 0XFD409914 + + * IQ ILL polytrim bypass value + * PSU_SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL 0xF7 + + * iqpi polytrim + * (OFFSET, MASK, VALUE) (0XFD409914, 0x000000FFU ,0x000000F7U) + */ + PSU_Mask_Write(SERDES_L2_TM_IQ_ILL8_OFFSET, + 0x000000FFU, 0x000000F7U); +/*##################################################################### */ + + /* + * Register : L2_TM_IQ_ILL9 @ 0XFD409918 + + * bypass IQ polytrim + * PSU_SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM 0x1 + + * enables for lf,constant gm trim and polytirm + * (OFFSET, MASK, VALUE) (0XFD409918, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L2_TM_IQ_ILL9_OFFSET, + 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : L2_TM_E_ILL8 @ 0XFD409940 + + * E ILL polytrim bypass value + * PSU_SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL 0xF7 + + * epi polytrim + * (OFFSET, MASK, VALUE) (0XFD409940, 0x000000FFU ,0x000000F7U) + */ + PSU_Mask_Write(SERDES_L2_TM_E_ILL8_OFFSET, 0x000000FFU, 0x000000F7U); +/*##################################################################### */ + + /* + * Register : L2_TM_E_ILL9 @ 0XFD409944 + + * bypass E polytrim + * PSU_SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM 0x1 + + * enables for lf,constant gm trim and polytirm + * (OFFSET, MASK, VALUE) (0XFD409944, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L2_TM_E_ILL9_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : L2_TM_ILL13 @ 0XFD409994 + + * ILL cal idle val refcnt + * PSU_SERDES_L2_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT 0x7 + + * ill cal idle value count + * (OFFSET, MASK, VALUE) (0XFD409994, 0x00000007U ,0x00000007U) + */ + PSU_Mask_Write(SERDES_L2_TM_ILL13_OFFSET, 0x00000007U, 0x00000007U); +/*##################################################################### */ + + /* + * Register : L3_TM_MISC2 @ 0XFD40D89C + + * ILL calib counts BYPASSED with calcode bits + * PSU_SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS 0x1 + + * sampler cal + * (OFFSET, MASK, VALUE) (0XFD40D89C, 0x00000080U ,0x00000080U) + */ + PSU_Mask_Write(SERDES_L3_TM_MISC2_OFFSET, 0x00000080U, 0x00000080U); +/*##################################################################### */ + + /* + * Register : L3_TM_IQ_ILL1 @ 0XFD40D8F8 + + * IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , + * USB3 : SS + * PSU_SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0 0x7D + + * iqpi cal code + * (OFFSET, MASK, VALUE) (0XFD40D8F8, 0x000000FFU ,0x0000007DU) + */ + PSU_Mask_Write(SERDES_L3_TM_IQ_ILL1_OFFSET, + 0x000000FFU, 0x0000007DU); +/*##################################################################### */ + + /* + * Register : L3_TM_IQ_ILL2 @ 0XFD40D8FC + + * IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 + * PSU_SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1 0x7D + + * iqpi cal code + * (OFFSET, MASK, VALUE) (0XFD40D8FC, 0x000000FFU ,0x0000007DU) + */ + PSU_Mask_Write(SERDES_L3_TM_IQ_ILL2_OFFSET, + 0x000000FFU, 0x0000007DU); +/*##################################################################### */ + + /* + * Register : L3_TM_ILL12 @ 0XFD40D990 + + * G1A pll ctr bypass value + * PSU_SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL 0x1 + + * ill pll counter values + * (OFFSET, MASK, VALUE) (0XFD40D990, 0x000000FFU ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L3_TM_ILL12_OFFSET, 0x000000FFU, 0x00000001U); +/*##################################################################### */ + + /* + * Register : L3_TM_E_ILL1 @ 0XFD40D924 + + * E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , U + * SB3 : SS + * PSU_SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0 0x9C + + * epi cal code + * (OFFSET, MASK, VALUE) (0XFD40D924, 0x000000FFU ,0x0000009CU) + */ + PSU_Mask_Write(SERDES_L3_TM_E_ILL1_OFFSET, 0x000000FFU, 0x0000009CU); +/*##################################################################### */ + + /* + * Register : L3_TM_E_ILL2 @ 0XFD40D928 + + * E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 + * PSU_SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1 0x39 + + * epi cal code + * (OFFSET, MASK, VALUE) (0XFD40D928, 0x000000FFU ,0x00000039U) + */ + PSU_Mask_Write(SERDES_L3_TM_E_ILL2_OFFSET, 0x000000FFU, 0x00000039U); +/*##################################################################### */ + + /* + * Register : L3_TM_ILL11 @ 0XFD40D98C + + * G2A_PCIe1 PLL ctr bypass value + * PSU_SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL 0x2 + + * ill pll counter values + * (OFFSET, MASK, VALUE) (0XFD40D98C, 0x000000F0U ,0x00000020U) + */ + PSU_Mask_Write(SERDES_L3_TM_ILL11_OFFSET, 0x000000F0U, 0x00000020U); +/*##################################################################### */ + + /* + * Register : L3_TM_IQ_ILL3 @ 0XFD40D900 + + * IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 + * PSU_SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2 0x7D + + * iqpi cal code + * (OFFSET, MASK, VALUE) (0XFD40D900, 0x000000FFU ,0x0000007DU) + */ + PSU_Mask_Write(SERDES_L3_TM_IQ_ILL3_OFFSET, + 0x000000FFU, 0x0000007DU); +/*##################################################################### */ + + /* + * Register : L3_TM_E_ILL3 @ 0XFD40D92C + + * E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 + * PSU_SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2 0x64 + + * epi cal code + * (OFFSET, MASK, VALUE) (0XFD40D92C, 0x000000FFU ,0x00000064U) + */ + PSU_Mask_Write(SERDES_L3_TM_E_ILL3_OFFSET, 0x000000FFU, 0x00000064U); +/*##################################################################### */ + + /* + * Register : L3_TM_ILL8 @ 0XFD40D980 + + * ILL calibration code change wait time + * PSU_SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT 0xFF + + * ILL cal routine control + * (OFFSET, MASK, VALUE) (0XFD40D980, 0x000000FFU ,0x000000FFU) + */ + PSU_Mask_Write(SERDES_L3_TM_ILL8_OFFSET, 0x000000FFU, 0x000000FFU); +/*##################################################################### */ + + /* + * Register : L3_TM_IQ_ILL8 @ 0XFD40D914 + + * IQ ILL polytrim bypass value + * PSU_SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL 0xF7 + + * iqpi polytrim + * (OFFSET, MASK, VALUE) (0XFD40D914, 0x000000FFU ,0x000000F7U) + */ + PSU_Mask_Write(SERDES_L3_TM_IQ_ILL8_OFFSET, + 0x000000FFU, 0x000000F7U); +/*##################################################################### */ + + /* + * Register : L3_TM_IQ_ILL9 @ 0XFD40D918 + + * bypass IQ polytrim + * PSU_SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM 0x1 + + * enables for lf,constant gm trim and polytirm + * (OFFSET, MASK, VALUE) (0XFD40D918, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L3_TM_IQ_ILL9_OFFSET, + 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : L3_TM_E_ILL8 @ 0XFD40D940 + + * E ILL polytrim bypass value + * PSU_SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL 0xF7 + + * epi polytrim + * (OFFSET, MASK, VALUE) (0XFD40D940, 0x000000FFU ,0x000000F7U) + */ + PSU_Mask_Write(SERDES_L3_TM_E_ILL8_OFFSET, 0x000000FFU, 0x000000F7U); +/*##################################################################### */ + + /* + * Register : L3_TM_E_ILL9 @ 0XFD40D944 + + * bypass E polytrim + * PSU_SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM 0x1 + + * enables for lf,constant gm trim and polytirm + * (OFFSET, MASK, VALUE) (0XFD40D944, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L3_TM_E_ILL9_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : L3_TM_ILL13 @ 0XFD40D994 + + * ILL cal idle val refcnt + * PSU_SERDES_L3_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT 0x7 + + * ill cal idle value count + * (OFFSET, MASK, VALUE) (0XFD40D994, 0x00000007U ,0x00000007U) + */ + PSU_Mask_Write(SERDES_L3_TM_ILL13_OFFSET, 0x00000007U, 0x00000007U); +/*##################################################################### */ + + /* + * SYMBOL LOCK AND WAIT + */ + /* + * Register : L0_TM_DIG_10 @ 0XFD40107C + + * CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001 + * PSU_SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME 0x1 + + * test control for changing cdr lock wait time + * (OFFSET, MASK, VALUE) (0XFD40107C, 0x0000000FU ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L0_TM_DIG_10_OFFSET, 0x0000000FU, 0x00000001U); +/*##################################################################### */ + + /* + * Register : L1_TM_DIG_10 @ 0XFD40507C + + * CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001 + * PSU_SERDES_L1_TM_DIG_10_CDR_BIT_LOCK_TIME 0x1 + + * test control for changing cdr lock wait time + * (OFFSET, MASK, VALUE) (0XFD40507C, 0x0000000FU ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L1_TM_DIG_10_OFFSET, 0x0000000FU, 0x00000001U); +/*##################################################################### */ + + /* + * Register : L2_TM_DIG_10 @ 0XFD40907C + + * CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001 + * PSU_SERDES_L2_TM_DIG_10_CDR_BIT_LOCK_TIME 0x1 + + * test control for changing cdr lock wait time + * (OFFSET, MASK, VALUE) (0XFD40907C, 0x0000000FU ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L2_TM_DIG_10_OFFSET, 0x0000000FU, 0x00000001U); +/*##################################################################### */ + + /* + * Register : L3_TM_DIG_10 @ 0XFD40D07C + + * CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001 + * PSU_SERDES_L3_TM_DIG_10_CDR_BIT_LOCK_TIME 0x1 + + * test control for changing cdr lock wait time + * (OFFSET, MASK, VALUE) (0XFD40D07C, 0x0000000FU ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L3_TM_DIG_10_OFFSET, 0x0000000FU, 0x00000001U); +/*##################################################################### */ + + /* + * SIOU SETTINGS FOR BYPASS CONTROL,HSRX-DIG + */ + /* + * Register : L0_TM_RST_DLY @ 0XFD4019A4 + + * Delay apb reset by specified amount + * PSU_SERDES_L0_TM_RST_DLY_APB_RST_DLY 0xFF + + * reset delay for apb reset w.r.t pso of hsrx + * (OFFSET, MASK, VALUE) (0XFD4019A4, 0x000000FFU ,0x000000FFU) + */ + PSU_Mask_Write(SERDES_L0_TM_RST_DLY_OFFSET, + 0x000000FFU, 0x000000FFU); +/*##################################################################### */ + + /* + * Register : L0_TM_ANA_BYP_15 @ 0XFD401038 + + * Enable Bypass for <7> of TM_ANA_BYPS_15 + * PSU_SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE 0x1 + + * Bypass control for pcs-pma interface. EQ supplies, main master supply an + * d ps for samp c2c + * (OFFSET, MASK, VALUE) (0XFD401038, 0x00000040U ,0x00000040U) + */ + PSU_Mask_Write(SERDES_L0_TM_ANA_BYP_15_OFFSET, + 0x00000040U, 0x00000040U); +/*##################################################################### */ + + /* + * Register : L0_TM_ANA_BYP_12 @ 0XFD40102C + + * Enable Bypass for <7> of TM_ANA_BYPS_12 + * PSU_SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG 0x1 + + * Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr ena + * ble controls + * (OFFSET, MASK, VALUE) (0XFD40102C, 0x00000040U ,0x00000040U) + */ + PSU_Mask_Write(SERDES_L0_TM_ANA_BYP_12_OFFSET, + 0x00000040U, 0x00000040U); +/*##################################################################### */ + + /* + * Register : L1_TM_RST_DLY @ 0XFD4059A4 + + * Delay apb reset by specified amount + * PSU_SERDES_L1_TM_RST_DLY_APB_RST_DLY 0xFF + + * reset delay for apb reset w.r.t pso of hsrx + * (OFFSET, MASK, VALUE) (0XFD4059A4, 0x000000FFU ,0x000000FFU) + */ + PSU_Mask_Write(SERDES_L1_TM_RST_DLY_OFFSET, + 0x000000FFU, 0x000000FFU); +/*##################################################################### */ + + /* + * Register : L1_TM_ANA_BYP_15 @ 0XFD405038 + + * Enable Bypass for <7> of TM_ANA_BYPS_15 + * PSU_SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE 0x1 + + * Bypass control for pcs-pma interface. EQ supplies, main master supply an + * d ps for samp c2c + * (OFFSET, MASK, VALUE) (0XFD405038, 0x00000040U ,0x00000040U) + */ + PSU_Mask_Write(SERDES_L1_TM_ANA_BYP_15_OFFSET, + 0x00000040U, 0x00000040U); +/*##################################################################### */ + + /* + * Register : L1_TM_ANA_BYP_12 @ 0XFD40502C + + * Enable Bypass for <7> of TM_ANA_BYPS_12 + * PSU_SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG 0x1 + + * Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr ena + * ble controls + * (OFFSET, MASK, VALUE) (0XFD40502C, 0x00000040U ,0x00000040U) + */ + PSU_Mask_Write(SERDES_L1_TM_ANA_BYP_12_OFFSET, + 0x00000040U, 0x00000040U); +/*##################################################################### */ + + /* + * Register : L2_TM_RST_DLY @ 0XFD4099A4 + + * Delay apb reset by specified amount + * PSU_SERDES_L2_TM_RST_DLY_APB_RST_DLY 0xFF + + * reset delay for apb reset w.r.t pso of hsrx + * (OFFSET, MASK, VALUE) (0XFD4099A4, 0x000000FFU ,0x000000FFU) + */ + PSU_Mask_Write(SERDES_L2_TM_RST_DLY_OFFSET, + 0x000000FFU, 0x000000FFU); +/*##################################################################### */ + + /* + * Register : L2_TM_ANA_BYP_15 @ 0XFD409038 + + * Enable Bypass for <7> of TM_ANA_BYPS_15 + * PSU_SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE 0x1 + + * Bypass control for pcs-pma interface. EQ supplies, main master supply an + * d ps for samp c2c + * (OFFSET, MASK, VALUE) (0XFD409038, 0x00000040U ,0x00000040U) + */ + PSU_Mask_Write(SERDES_L2_TM_ANA_BYP_15_OFFSET, + 0x00000040U, 0x00000040U); +/*##################################################################### */ + + /* + * Register : L2_TM_ANA_BYP_12 @ 0XFD40902C + + * Enable Bypass for <7> of TM_ANA_BYPS_12 + * PSU_SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG 0x1 + + * Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr ena + * ble controls + * (OFFSET, MASK, VALUE) (0XFD40902C, 0x00000040U ,0x00000040U) + */ + PSU_Mask_Write(SERDES_L2_TM_ANA_BYP_12_OFFSET, + 0x00000040U, 0x00000040U); +/*##################################################################### */ + + /* + * Register : L3_TM_RST_DLY @ 0XFD40D9A4 + + * Delay apb reset by specified amount + * PSU_SERDES_L3_TM_RST_DLY_APB_RST_DLY 0xFF + + * reset delay for apb reset w.r.t pso of hsrx + * (OFFSET, MASK, VALUE) (0XFD40D9A4, 0x000000FFU ,0x000000FFU) + */ + PSU_Mask_Write(SERDES_L3_TM_RST_DLY_OFFSET, + 0x000000FFU, 0x000000FFU); +/*##################################################################### */ + + /* + * Register : L3_TM_ANA_BYP_15 @ 0XFD40D038 + + * Enable Bypass for <7> of TM_ANA_BYPS_15 + * PSU_SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE 0x1 + + * Bypass control for pcs-pma interface. EQ supplies, main master supply an + * d ps for samp c2c + * (OFFSET, MASK, VALUE) (0XFD40D038, 0x00000040U ,0x00000040U) + */ + PSU_Mask_Write(SERDES_L3_TM_ANA_BYP_15_OFFSET, + 0x00000040U, 0x00000040U); +/*##################################################################### */ + + /* + * Register : L3_TM_ANA_BYP_12 @ 0XFD40D02C + + * Enable Bypass for <7> of TM_ANA_BYPS_12 + * PSU_SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG 0x1 + + * Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr ena + * ble controls + * (OFFSET, MASK, VALUE) (0XFD40D02C, 0x00000040U ,0x00000040U) + */ + PSU_Mask_Write(SERDES_L3_TM_ANA_BYP_12_OFFSET, + 0x00000040U, 0x00000040U); +/*##################################################################### */ + + /* + * DISABLE FPL/FFL + */ + /* + * Register : L0_TM_MISC3 @ 0XFD4019AC + + * CDR fast phase lock control + * PSU_SERDES_L0_TM_MISC3_CDR_EN_FPL 0x0 + + * CDR fast frequency lock control + * PSU_SERDES_L0_TM_MISC3_CDR_EN_FFL 0x0 + + * debug bus selection bit, cdr fast phase and freq controls + * (OFFSET, MASK, VALUE) (0XFD4019AC, 0x00000003U ,0x00000000U) + */ + PSU_Mask_Write(SERDES_L0_TM_MISC3_OFFSET, 0x00000003U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : L1_TM_MISC3 @ 0XFD4059AC + + * CDR fast phase lock control + * PSU_SERDES_L1_TM_MISC3_CDR_EN_FPL 0x0 + + * CDR fast frequency lock control + * PSU_SERDES_L1_TM_MISC3_CDR_EN_FFL 0x0 + + * debug bus selection bit, cdr fast phase and freq controls + * (OFFSET, MASK, VALUE) (0XFD4059AC, 0x00000003U ,0x00000000U) + */ + PSU_Mask_Write(SERDES_L1_TM_MISC3_OFFSET, 0x00000003U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : L2_TM_MISC3 @ 0XFD4099AC + + * CDR fast phase lock control + * PSU_SERDES_L2_TM_MISC3_CDR_EN_FPL 0x0 + + * CDR fast frequency lock control + * PSU_SERDES_L2_TM_MISC3_CDR_EN_FFL 0x0 + + * debug bus selection bit, cdr fast phase and freq controls + * (OFFSET, MASK, VALUE) (0XFD4099AC, 0x00000003U ,0x00000000U) + */ + PSU_Mask_Write(SERDES_L2_TM_MISC3_OFFSET, 0x00000003U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : L3_TM_MISC3 @ 0XFD40D9AC + + * CDR fast phase lock control + * PSU_SERDES_L3_TM_MISC3_CDR_EN_FPL 0x0 + + * CDR fast frequency lock control + * PSU_SERDES_L3_TM_MISC3_CDR_EN_FFL 0x0 + + * debug bus selection bit, cdr fast phase and freq controls + * (OFFSET, MASK, VALUE) (0XFD40D9AC, 0x00000003U ,0x00000000U) + */ + PSU_Mask_Write(SERDES_L3_TM_MISC3_OFFSET, 0x00000003U, 0x00000000U); +/*##################################################################### */ + + /* + * DISABLE DYNAMIC OFFSET CALIBRATION + */ + /* + * Register : L0_TM_EQ11 @ 0XFD401978 + + * Force EQ offset correction algo off if not forced on + * PSU_SERDES_L0_TM_EQ11_FORCE_EQ_OFFS_OFF 0x1 + + * eq dynamic offset correction + * (OFFSET, MASK, VALUE) (0XFD401978, 0x00000010U ,0x00000010U) + */ + PSU_Mask_Write(SERDES_L0_TM_EQ11_OFFSET, 0x00000010U, 0x00000010U); +/*##################################################################### */ + + /* + * Register : L1_TM_EQ11 @ 0XFD405978 + + * Force EQ offset correction algo off if not forced on + * PSU_SERDES_L1_TM_EQ11_FORCE_EQ_OFFS_OFF 0x1 + + * eq dynamic offset correction + * (OFFSET, MASK, VALUE) (0XFD405978, 0x00000010U ,0x00000010U) + */ + PSU_Mask_Write(SERDES_L1_TM_EQ11_OFFSET, 0x00000010U, 0x00000010U); +/*##################################################################### */ + + /* + * Register : L2_TM_EQ11 @ 0XFD409978 + + * Force EQ offset correction algo off if not forced on + * PSU_SERDES_L2_TM_EQ11_FORCE_EQ_OFFS_OFF 0x1 + + * eq dynamic offset correction + * (OFFSET, MASK, VALUE) (0XFD409978, 0x00000010U ,0x00000010U) + */ + PSU_Mask_Write(SERDES_L2_TM_EQ11_OFFSET, 0x00000010U, 0x00000010U); +/*##################################################################### */ + + /* + * Register : L3_TM_EQ11 @ 0XFD40D978 + + * Force EQ offset correction algo off if not forced on + * PSU_SERDES_L3_TM_EQ11_FORCE_EQ_OFFS_OFF 0x1 + + * eq dynamic offset correction + * (OFFSET, MASK, VALUE) (0XFD40D978, 0x00000010U ,0x00000010U) + */ + PSU_Mask_Write(SERDES_L3_TM_EQ11_OFFSET, 0x00000010U, 0x00000010U); +/*##################################################################### */ + + /* + * DISABLE ECO FOR PCIE + */ + /* + * Register : eco_0 @ 0XFD3D001C + + * For future use + * PSU_SIOU_ECO_0_FIELD 0x1 + + * ECO Register for future use + * (OFFSET, MASK, VALUE) (0XFD3D001C, 0xFFFFFFFFU ,0x00000001U) + */ + PSU_Mask_Write(SIOU_ECO_0_OFFSET, 0xFFFFFFFFU, 0x00000001U); +/*##################################################################### */ + + /* + * GT LANE SETTINGS + */ + /* + * Register : ICM_CFG0 @ 0XFD410010 + + * Controls UPHY Lane 0 protocol configuration. 0 - PowerDown, 1 - PCIe .0, + * 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII0, 6 - Unused, 7 - Unused + * PSU_SERDES_ICM_CFG0_L0_ICM_CFG 1 + + * Controls UPHY Lane 1 protocol configuration. 0 - PowerDown, 1 - PCIe.1, + * 2 - Sata1, 3 - USB0, 4 - DP.0, 5 - SGMII1, 6 - Unused, 7 - Unused + * PSU_SERDES_ICM_CFG0_L1_ICM_CFG 4 + + * ICM Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD410010, 0x00000077U ,0x00000041U) + */ + PSU_Mask_Write(SERDES_ICM_CFG0_OFFSET, 0x00000077U, 0x00000041U); +/*##################################################################### */ + + /* + * Register : ICM_CFG1 @ 0XFD410014 + + * Controls UPHY Lane 2 protocol configuration. 0 - PowerDown, 1 - PCIe.1, + * 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII2, 6 - Unused, 7 - Unused + * PSU_SERDES_ICM_CFG1_L2_ICM_CFG 3 + + * Controls UPHY Lane 3 protocol configuration. 0 - PowerDown, 1 - PCIe.3, + * 2 - Sata1, 3 - USB1, 4 - DP.0, 5 - SGMII3, 6 - Unused, 7 - Unused + * PSU_SERDES_ICM_CFG1_L3_ICM_CFG 2 + + * ICM Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD410014, 0x00000077U ,0x00000023U) + */ + PSU_Mask_Write(SERDES_ICM_CFG1_OFFSET, 0x00000077U, 0x00000023U); +/*##################################################################### */ + + /* + * CHECKING PLL LOCK + */ + /* + * ENABLE SERIAL DATA MUX DEEMPH + */ + /* + * Register : L1_TXPMD_TM_45 @ 0XFD404CB4 + + * Enable/disable DP post2 path + * PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH 0x1 + + * Override enable/disable of DP post2 path + * PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH 0x1 + + * Override enable/disable of DP post1 path + * PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH 0x1 + + * Enable/disable DP main path + * PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH 0x1 + + * Override enable/disable of DP main path + * PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH 0x1 + + * Post or pre or main DP path selection + * (OFFSET, MASK, VALUE) (0XFD404CB4, 0x00000037U ,0x00000037U) + */ + PSU_Mask_Write(SERDES_L1_TXPMD_TM_45_OFFSET, + 0x00000037U, 0x00000037U); +/*##################################################################### */ + + /* + * Register : L1_TX_ANA_TM_118 @ 0XFD4041D8 + + * Test register force for enabling/disablign TX deemphasis bits <17:0> + * PSU_SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0 0x1 + + * Enable Override of TX deemphasis + * (OFFSET, MASK, VALUE) (0XFD4041D8, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L1_TX_ANA_TM_118_OFFSET, + 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : L3_TX_ANA_TM_118 @ 0XFD40C1D8 + + * Test register force for enabling/disablign TX deemphasis bits <17:0> + * PSU_SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0 0x1 + + * Enable Override of TX deemphasis + * (OFFSET, MASK, VALUE) (0XFD40C1D8, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L3_TX_ANA_TM_118_OFFSET, + 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * CDR AND RX EQUALIZATION SETTINGS + */ + /* + * Register : L3_TM_CDR5 @ 0XFD40DC14 + + * FPHL FSM accumulate cycles + * PSU_SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES 0x7 + + * FFL Phase0 int gain aka 2ol SD update rate + * PSU_SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN 0x6 + + * Fast phase lock controls -- FSM accumulator cycle control and phase 0 in + * t gain control. + * (OFFSET, MASK, VALUE) (0XFD40DC14, 0x000000FFU ,0x000000E6U) + */ + PSU_Mask_Write(SERDES_L3_TM_CDR5_OFFSET, 0x000000FFU, 0x000000E6U); +/*##################################################################### */ + + /* + * Register : L3_TM_CDR16 @ 0XFD40DC40 + + * FFL Phase0 prop gain aka 1ol SD update rate + * PSU_SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN 0xC + + * Fast phase lock controls -- phase 0 prop gain + * (OFFSET, MASK, VALUE) (0XFD40DC40, 0x0000001FU ,0x0000000CU) + */ + PSU_Mask_Write(SERDES_L3_TM_CDR16_OFFSET, 0x0000001FU, 0x0000000CU); +/*##################################################################### */ + + /* + * Register : L3_TM_EQ0 @ 0XFD40D94C + + * EQ stg 2 controls BYPASSED + * PSU_SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP 1 + + * eq stg1 and stg2 controls + * (OFFSET, MASK, VALUE) (0XFD40D94C, 0x00000020U ,0x00000020U) + */ + PSU_Mask_Write(SERDES_L3_TM_EQ0_OFFSET, 0x00000020U, 0x00000020U); +/*##################################################################### */ + + /* + * Register : L3_TM_EQ1 @ 0XFD40D950 + + * EQ STG2 RL PROG + * PSU_SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG 0x2 + + * EQ stg 2 preamp mode val + * PSU_SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL 0x1 + + * eq stg1 and stg2 controls + * (OFFSET, MASK, VALUE) (0XFD40D950, 0x00000007U ,0x00000006U) + */ + PSU_Mask_Write(SERDES_L3_TM_EQ1_OFFSET, 0x00000007U, 0x00000006U); +/*##################################################################### */ + + /* + * GEM SERDES SETTINGS + */ + /* + * ENABLE PRE EMPHAIS AND VOLTAGE SWING + */ + /* + * Register : L1_TXPMD_TM_48 @ 0XFD404CC0 + + * Margining factor value + * PSU_SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR 0 + + * Margining factor + * (OFFSET, MASK, VALUE) (0XFD404CC0, 0x0000001FU ,0x00000000U) + */ + PSU_Mask_Write(SERDES_L1_TXPMD_TM_48_OFFSET, + 0x0000001FU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : L1_TX_ANA_TM_18 @ 0XFD404048 + + * pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-em + * phasis, Others: reserved + * PSU_SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0 0 + + * Override for PIPE TX de-emphasis + * (OFFSET, MASK, VALUE) (0XFD404048, 0x000000FFU ,0x00000000U) + */ + PSU_Mask_Write(SERDES_L1_TX_ANA_TM_18_OFFSET, + 0x000000FFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : L3_TX_ANA_TM_18 @ 0XFD40C048 + + * pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-em + * phasis, Others: reserved + * PSU_SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0 0x1 + + * Override for PIPE TX de-emphasis + * (OFFSET, MASK, VALUE) (0XFD40C048, 0x000000FFU ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L3_TX_ANA_TM_18_OFFSET, + 0x000000FFU, 0x00000001U); +/*##################################################################### */ + + + return 1; } -unsigned long psu_resetin_init_data() { - // : PUTTING SERDES PERIPHERAL IN RESET - // : PUTTING USB0 IN RESET - /*Register : RST_LPD_TOP @ 0XFF5E023C

+unsigned long psu_resetout_init_data(void) +{ + /* + * TAKING SERDES PERIPHERAL OUT OF RESET RESET + */ + /* + * PUTTING USB0 IN RESET + */ + /* + * Register : RST_LPD_TOP @ 0XFF5E023C - USB 0 reset for control registers - PSU_CRL_APB_RST_LPD_TOP_USB0_APB_RESET 0X1 + * USB 0 reset for control registers + * PSU_CRL_APB_RST_LPD_TOP_USB0_APB_RESET 0X0 - USB 0 sleep circuit reset - PSU_CRL_APB_RST_LPD_TOP_USB0_HIBERRESET 0X1 + * Software control register for the LPD block. + * (OFFSET, MASK, VALUE) (0XFF5E023C, 0x00000400U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_TOP_OFFSET, 0x00000400U, 0x00000000U); +/*##################################################################### */ - USB 0 reset - PSU_CRL_APB_RST_LPD_TOP_USB0_CORERESET 0X1 + /* + * HIBERREST + */ + /* + * Register : RST_LPD_TOP @ 0XFF5E023C - Software control register for the LPD block. - (OFFSET, MASK, VALUE) (0XFF5E023C, 0x00000540U ,0x00000540U) - RegMask = (CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK | CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK | CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK | 0 ); + * USB 0 sleep circuit reset + * PSU_CRL_APB_RST_LPD_TOP_USB0_HIBERRESET 0X0 - RegVal = ((0x00000001U << CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT - | 0x00000001U << CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT - | 0x00000001U << CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RST_LPD_TOP_OFFSET ,0x00000540U ,0x00000540U); - /*############################################################################################################################ */ + * USB 0 reset + * PSU_CRL_APB_RST_LPD_TOP_USB0_CORERESET 0X0 - // : PUTTING GEM0 IN RESET - /*Register : RST_LPD_IOU0 @ 0XFF5E0230

+ * Software control register for the LPD block. + * (OFFSET, MASK, VALUE) (0XFF5E023C, 0x00000140U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_TOP_OFFSET, 0x00000140U, 0x00000000U); +/*##################################################################### */ - GEM 3 reset - PSU_CRL_APB_RST_LPD_IOU0_GEM3_RESET 0X1 + /* + * PUTTING GEM0 IN RESET + */ + /* + * Register : RST_LPD_IOU0 @ 0XFF5E0230 - Software controlled reset for the GEMs - (OFFSET, MASK, VALUE) (0XFF5E0230, 0x00000008U ,0x00000008U) - RegMask = (CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK | 0 ); + * GEM 3 reset + * PSU_CRL_APB_RST_LPD_IOU0_GEM3_RESET 0X0 - RegVal = ((0x00000001U << CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RST_LPD_IOU0_OFFSET ,0x00000008U ,0x00000008U); - /*############################################################################################################################ */ + * Software controlled reset for the GEMs + * (OFFSET, MASK, VALUE) (0XFF5E0230, 0x00000008U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_IOU0_OFFSET, + 0x00000008U, 0x00000000U); +/*##################################################################### */ - // : PUTTING SATA IN RESET - /*Register : RST_FPD_TOP @ 0XFD1A0100

+ /* + * PUTTING SATA IN RESET + */ + /* + * Register : sata_misc_ctrl @ 0XFD3D0100 - Sata block level reset - PSU_CRF_APB_RST_FPD_TOP_SATA_RESET 0X1 + * Sata PM clock control select + * PSU_SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL 0x3 - FPD Block level software controlled reset - (OFFSET, MASK, VALUE) (0XFD1A0100, 0x00000002U ,0x00000002U) - RegMask = (CRF_APB_RST_FPD_TOP_SATA_RESET_MASK | 0 ); + * Misc Contorls for SATA.This register may only be modified during bootup + * (while SATA block is disabled) + * (OFFSET, MASK, VALUE) (0XFD3D0100, 0x00000003U ,0x00000003U) + */ + PSU_Mask_Write(SIOU_SATA_MISC_CTRL_OFFSET, 0x00000003U, 0x00000003U); +/*##################################################################### */ - RegVal = ((0x00000001U << CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_RST_FPD_TOP_OFFSET ,0x00000002U ,0x00000002U); - /*############################################################################################################################ */ + /* + * Register : RST_FPD_TOP @ 0XFD1A0100 - // : PUTTING PCIE IN RESET - /*Register : RST_FPD_TOP @ 0XFD1A0100

+ * Sata block level reset + * PSU_CRF_APB_RST_FPD_TOP_SATA_RESET 0X0 - PCIE config reset - PSU_CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET 0X1 + * FPD Block level software controlled reset + * (OFFSET, MASK, VALUE) (0XFD1A0100, 0x00000002U ,0x00000000U) + */ + PSU_Mask_Write(CRF_APB_RST_FPD_TOP_OFFSET, 0x00000002U, 0x00000000U); +/*##################################################################### */ - PCIE control block level reset - PSU_CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET 0X1 + /* + * PUTTING PCIE CFG AND BRIDGE IN RESET + */ + /* + * Register : RST_FPD_TOP @ 0XFD1A0100 - PCIE bridge block level reset (AXI interface) - PSU_CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET 0X1 + * PCIE config reset + * PSU_CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET 0X0 - FPD Block level software controlled reset - (OFFSET, MASK, VALUE) (0XFD1A0100, 0x000E0000U ,0x000E0000U) - RegMask = (CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK | CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK | CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK | 0 ); + * PCIE bridge block level reset (AXI interface) + * PSU_CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET 0X0 - RegVal = ((0x00000001U << CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT - | 0x00000001U << CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT - | 0x00000001U << CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_RST_FPD_TOP_OFFSET ,0x000E0000U ,0x000E0000U); - /*############################################################################################################################ */ + * FPD Block level software controlled reset + * (OFFSET, MASK, VALUE) (0XFD1A0100, 0x000C0000U ,0x00000000U) + */ + PSU_Mask_Write(CRF_APB_RST_FPD_TOP_OFFSET, 0x000C0000U, 0x00000000U); +/*##################################################################### */ - // : PUTTING DP IN RESET - /*Register : DP_TX_PHY_POWER_DOWN @ 0XFD4A0238

+ /* + * PUTTING DP IN RESET + */ + /* + * Register : RST_FPD_TOP @ 0XFD1A0100 - Two bits per lane. When set to 11, moves the GT to power down mode. When set to 00, GT will be in active state. bits [1:0] - - ane0 Bits [3:2] - lane 1 - PSU_DP_DP_TX_PHY_POWER_DOWN_POWER_DWN 0XA + * Display Port block level reset (includes DPDMA) + * PSU_CRF_APB_RST_FPD_TOP_DP_RESET 0X0 - Control PHY Power down - (OFFSET, MASK, VALUE) (0XFD4A0238, 0x0000000FU ,0x0000000AU) - RegMask = (DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK | 0 ); + * FPD Block level software controlled reset + * (OFFSET, MASK, VALUE) (0XFD1A0100, 0x00010000U ,0x00000000U) + */ + PSU_Mask_Write(CRF_APB_RST_FPD_TOP_OFFSET, 0x00010000U, 0x00000000U); +/*##################################################################### */ - RegVal = ((0x0000000AU << DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DP_DP_TX_PHY_POWER_DOWN_OFFSET ,0x0000000FU ,0x0000000AU); - /*############################################################################################################################ */ + /* + * Register : DP_PHY_RESET @ 0XFD4A0200 - /*Register : DP_PHY_RESET @ 0XFD4A0200

+ * Set to '1' to hold the GT in reset. Clear to release. + * PSU_DP_DP_PHY_RESET_GT_RESET 0X0 - Set to '1' to hold the GT in reset. Clear to release. - PSU_DP_DP_PHY_RESET_GT_RESET 0X1 + * Reset the transmitter PHY. + * (OFFSET, MASK, VALUE) (0XFD4A0200, 0x00000002U ,0x00000000U) + */ + PSU_Mask_Write(DP_DP_PHY_RESET_OFFSET, 0x00000002U, 0x00000000U); +/*##################################################################### */ - Reset the transmitter PHY. - (OFFSET, MASK, VALUE) (0XFD4A0200, 0x00000002U ,0x00000002U) - RegMask = (DP_DP_PHY_RESET_GT_RESET_MASK | 0 ); + /* + * Register : DP_TX_PHY_POWER_DOWN @ 0XFD4A0238 - RegVal = ((0x00000001U << DP_DP_PHY_RESET_GT_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DP_DP_PHY_RESET_OFFSET ,0x00000002U ,0x00000002U); - /*############################################################################################################################ */ + * Two bits per lane. When set to 11, moves the GT to power down mode. When + * set to 00, GT will be in active state. bits [1:0] - lane0 Bits [3:2] - + * lane 1 + * PSU_DP_DP_TX_PHY_POWER_DOWN_POWER_DWN 0X0 - /*Register : RST_FPD_TOP @ 0XFD1A0100

+ * Control PHY Power down + * (OFFSET, MASK, VALUE) (0XFD4A0238, 0x0000000FU ,0x00000000U) + */ + PSU_Mask_Write(DP_DP_TX_PHY_POWER_DOWN_OFFSET, + 0x0000000FU, 0x00000000U); +/*##################################################################### */ - Display Port block level reset (includes DPDMA) - PSU_CRF_APB_RST_FPD_TOP_DP_RESET 0X1 + /* + * USB0 GFLADJ + */ + /* + * Register : GUSB2PHYCFG @ 0XFE20C200 - FPD Block level software controlled reset - (OFFSET, MASK, VALUE) (0XFD1A0100, 0x00010000U ,0x00010000U) - RegMask = (CRF_APB_RST_FPD_TOP_DP_RESET_MASK | 0 ); + * USB 2.0 Turnaround Time (USBTrdTim) Sets the turnaround time in PHY cloc + * ks. Specifies the response time for a MAC request to the Packet FIFO Con + * troller (PFC) to fetch data from the DFIFO (SPRAM). The following are th + * e required values for the minimum SoC bus frequency of 60 MHz. USB turna + * round time is a critical certification criteria when using long cables a + * nd five hub levels. The required values for this field: - 4'h5: When the + * MAC interface is 16-bit UTMI+. - 4'h9: When the MAC interface is 8-bit + * UTMI+/ULPI. If SoC bus clock is less than 60 MHz, and USB turnaround tim + * e is not critical, this field can be set to a larger value. Note: This f + * ield is valid only in device mode. + * PSU_USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM 0x9 - RegVal = ((0x00000001U << CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_RST_FPD_TOP_OFFSET ,0x00010000U ,0x00010000U); - /*############################################################################################################################ */ + * Transceiver Delay: Enables a delay between the assertion of the UTMI/ULP + * I Transceiver Select signal (for HS) and the assertion of the TxValid si + * gnal during a HS Chirp. When this bit is set to 1, a delay (of approxima + * tely 2.5 us) is introduced from the time when the Transceiver Select is + * set to 2'b00 (HS) to the time the TxValid is driven to 0 for sending the + * chirp-K. This delay is required for some UTMI/ULPI PHYs. Note: - If you + * enable the hibernation feature when the device core comes out of power- + * off, you must re-initialize this bit with the appropriate value because + * the core does not save and restore this bit value during hibernation. - + * This bit is valid only in device mode. + * PSU_USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY 0x0 + + * Enable utmi_sleep_n and utmi_l1_suspend_n (EnblSlpM) The application use + * s this bit to control utmi_sleep_n and utmi_l1_suspend_n assertion to th + * e PHY in the L1 state. - 1'b0: utmi_sleep_n and utmi_l1_suspend_n assert + * ion from the core is not transferred to the external PHY. - 1'b1: utmi_s + * leep_n and utmi_l1_suspend_n assertion from the core is transferred to t + * he external PHY. Note: This bit must be set high for Port0 if PHY is use + * d. Note: In Device mode - Before issuing any device endpoint command whe + * n operating in 2.0 speeds, disable this bit and enable it after the comm + * and completes. Without disabling this bit, if a command is issued when t + * he device is in L1 state and if mac2_clk (utmi_clk/ulpi_clk) is gated of + * f, the command will not get completed. + * PSU_USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM 0x0 + + * USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial Transceiver Select T + * he application uses this bit to select a high-speed PHY or a full-speed + * transceiver. - 1'b0: USB 2.0 high-speed UTMI+ or ULPI PHY. This bit is a + * lways 0, with Write Only access. - 1'b1: USB 1.1 full-speed serial trans + * ceiver. This bit is always 1, with Write Only access. If both interface + * types are selected in coreConsultant (that is, parameters' values are no + * t zero), the application uses this bit to select the active interface is + * active, with Read-Write bit access. Note: USB 1.1 full-serial transceiv + * er is not supported. This bit always reads as 1'b0. + * PSU_USB3_0_XHCI_GUSB2PHYCFG_PHYSEL 0x0 + + * Suspend USB2.0 HS/FS/LS PHY (SusPHY) When set, USB2.0 PHY enters Suspend + * mode if Suspend conditions are valid. For DRD/OTG configurations, it is + * recommended that this bit is set to 0 during coreConsultant configurati + * on. If it is set to 1, then the application must clear this bit after po + * wer-on reset. Application needs to set it to 1 after the core initializa + * tion completes. For all other configurations, this bit can be set to 1 d + * uring core configuration. Note: - In host mode, on reset, this bit is se + * t to 1. Software can override this bit after reset. - In device mode, be + * fore issuing any device endpoint command when operating in 2.0 speeds, d + * isable this bit and enable it after the command completes. If you issue + * a command without disabling this bit when the device is in L2 state and + * if mac2_clk (utmi_clk/ulpi_clk) is gated off, the command will not get c + * ompleted. + * PSU_USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20 0x1 + + * Full-Speed Serial Interface Select (FSIntf) The application uses this bi + * t to select a unidirectional or bidirectional USB 1.1 full-speed serial + * transceiver interface. - 1'b0: 6-pin unidirectional full-speed serial in + * terface. This bit is set to 0 with Read Only access. - 1'b1: 3-pin bidir + * ectional full-speed serial interface. This bit is set to 0 with Read Onl + * y access. Note: USB 1.1 full-speed serial interface is not supported. Th + * is bit always reads as 1'b0. + * PSU_USB3_0_XHCI_GUSB2PHYCFG_FSINTF 0x0 + + * ULPI or UTMI+ Select (ULPI_UTMI_Sel) The application uses this bit to se + * lect a UTMI+ or ULPI Interface. - 1'b0: UTMI+ Interface - 1'b1: ULPI Int + * erface This bit is writable only if UTMI+ and ULPI is specified for High + * -Speed PHY Interface(s) in coreConsultant configuration (DWC_USB3_HSPHY_ + * INTERFACE = 3). Otherwise, this bit is read-only and the value depends o + * n the interface selected through DWC_USB3_HSPHY_INTERFACE. + * PSU_USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL 0x1 + + * PHY Interface (PHYIf) If UTMI+ is selected, the application uses this bi + * t to configure the core to support a UTMI+ PHY with an 8- or 16-bit inte + * rface. - 1'b0: 8 bits - 1'b1: 16 bits ULPI Mode: 1'b0 Note: - All the en + * abled 2.0 ports must have the same clock frequency as Port0 clock freque + * ncy (utmi_clk[0]). - The UTMI 8-bit and 16-bit modes cannot be used toge + * ther for different ports at the same time (that is, all the ports must b + * e in 8-bit mode, or all of them must be in 16-bit mode, at a time). - If + * any of the USB 2.0 ports is selected as ULPI port for operation, then a + * ll the USB 2.0 ports must be operating at 60 MHz. + * PSU_USB3_0_XHCI_GUSB2PHYCFG_PHYIF 0x0 + + * HS/FS Timeout Calibration (TOutCal) The number of PHY clocks, as indicat + * ed by the application in this field, is multiplied by a bit-time factor; + * this factor is added to the high-speed/full-speed interpacket timeout d + * uration in the core to account for additional delays introduced by the P + * HY. This may be required, since the delay introduced by the PHY in gener + * ating the linestate condition may vary among PHYs. The USB standard time + * out value for high-speed operation is 736 to 816 (inclusive) bit times. + * The USB standard timeout value for full-speed operation is 16 to 18 (inc + * lusive) bit times. The application must program this field based on the + * speed of connection. The number of bit times added per PHY clock are: Hi + * gh-speed operation: - One 30-MHz PHY clock = 16 bit times - One 60-MHz P + * HY clock = 8 bit times Full-speed operation: - One 30-MHz PHY clock = 0. + * 4 bit times - One 60-MHz PHY clock = 0.2 bit times - One 48-MHz PHY cloc + * k = 0.25 bit times + * PSU_USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL 0x7 + + * ULPI External VBUS Drive (ULPIExtVbusDrv) Selects supply source to drive + * 5V on VBUS, in the ULPI PHY. - 1'b0: PHY drives VBUS with internal char + * ge pump (default). - 1'b1: PHY drives VBUS with an external supply. (Onl + * y when RTL parameter DWC_USB3_HSPHY_INTERFACE = 2 or 3) + * PSU_USB3_0_XHCI_GUSB2PHYCFG_ULPIEXTVBUSDRV 0x1 + + * Global USB2 PHY Configuration Register The application must program this + * register before starting any transactions on either the SoC bus or the + * USB. In Device-only configurations, only one register is needed. In Host + * mode, per-port registers are implemented. + * (OFFSET, MASK, VALUE) (0XFE20C200, 0x00023FFFU ,0x00022457U) + */ + PSU_Mask_Write(USB3_0_XHCI_GUSB2PHYCFG_OFFSET, + 0x00023FFFU, 0x00022457U); +/*##################################################################### */ + + /* + * Register : GFLADJ @ 0XFE20C630 + + * This field indicates the frame length adjustment to be applied when SOF/ + * ITP counter is running on the ref_clk. This register value is used to ad + * just the ITP interval when GCTL[SOFITPSYNC] is set to '1'; SOF and ITP i + * nterval when GLADJ.GFLADJ_REFCLK_LPM_SEL is set to '1'. This field must + * be programmed to a non-zero value only if GFLADJ_REFCLK_LPM_SEL is set t + * o '1' or GCTL.SOFITPSYNC is set to '1'. The value is derived as follows: + * FLADJ_REF_CLK_FLADJ=((125000/ref_clk_period_integer)-(125000/ref_clk_pe + * riod)) * ref_clk_period where - the ref_clk_period_integer is the intege + * r value of the ref_clk period got by truncating the decimal (fractional) + * value that is programmed in the GUCTL.REF_CLK_PERIOD field. - the ref_c + * lk_period is the ref_clk period including the fractional value. Examples + * : If the ref_clk is 24 MHz then - GUCTL.REF_CLK_PERIOD = 41 - GFLADJ.GLA + * DJ_REFCLK_FLADJ = ((125000/41)-(125000/41.6666))*41.6666 = 2032 (ignorin + * g the fractional value) If the ref_clk is 48 MHz then - GUCTL.REF_CLK_PE + * RIOD = 20 - GFLADJ.GLADJ_REFCLK_FLADJ = ((125000/20)-(125000/20.8333))*2 + * 0.8333 = 5208 (ignoring the fractional value) + * PSU_USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ 0x0 + + * Global Frame Length Adjustment Register This register provides options f + * or the software to control the core behavior with respect to SOF (Start + * of Frame) and ITP (Isochronous Timestamp Packet) timers and frame timer + * functionality. It provides an option to override the fladj_30mhz_reg sid + * eband signal. In addition, it enables running SOF or ITP frame timer cou + * nters completely from the ref_clk. This facilitates hardware LPM in host + * mode with the SOF or ITP counters being run from the ref_clk signal. + * (OFFSET, MASK, VALUE) (0XFE20C630, 0x003FFF00U ,0x00000000U) + */ + PSU_Mask_Write(USB3_0_XHCI_GFLADJ_OFFSET, 0x003FFF00U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : GUCTL1 @ 0XFE20C11C + + * When this bit is set to '0', termsel, xcvrsel will become 0 during end o + * f resume while the opmode will become 0 once controller completes end of + * resume and enters U0 state (2 separate commandswill be issued). When th + * is bit is set to '1', all the termsel, xcvrsel, opmode becomes 0 during + * end of resume itself (only 1 command will be issued) + * PSU_USB3_0_XHCI_GUCTL1_RESUME_TERMSEL_XCVRSEL_UNIFY 0x1 + + * Reserved + * PSU_USB3_0_XHCI_GUCTL1_RESERVED_9 0x1 + + * Global User Control Register 1 + * (OFFSET, MASK, VALUE) (0XFE20C11C, 0x00000600U ,0x00000600U) + */ + PSU_Mask_Write(USB3_0_XHCI_GUCTL1_OFFSET, 0x00000600U, 0x00000600U); +/*##################################################################### */ + + /* + * Register : GUCTL @ 0XFE20C12C + + * Host IN Auto Retry (USBHstInAutoRetryEn) When set, this field enables th + * e Auto Retry feature. For IN transfers (non-isochronous) that encounter + * data packets with CRC errors or internal overrun scenarios, the auto ret + * ry feature causes the Host core to reply to the device with a non-termin + * ating retry ACK (that is, an ACK transaction packet with Retry = 1 and N + * umP != 0). If the Auto Retry feature is disabled (default), the core wil + * l respond with a terminating retry ACK (that is, an ACK transaction pack + * et with Retry = 1 and NumP = 0). - 1'b0: Auto Retry Disabled - 1'b1: Aut + * o Retry Enabled Note: This bit is also applicable to the device mode. + * PSU_USB3_0_XHCI_GUCTL_USBHSTINAUTORETRYEN 0x1 + + * Global User Control Register: This register provides a few options for t + * he software to control the core behavior in the Host mode. Most of the o + * ptions are used to improve host inter-operability with different devices + * . + * (OFFSET, MASK, VALUE) (0XFE20C12C, 0x00004000U ,0x00004000U) + */ + PSU_Mask_Write(USB3_0_XHCI_GUCTL_OFFSET, 0x00004000U, 0x00004000U); +/*##################################################################### */ + + /* + * UPDATING TWO PCIE REGISTERS DEFAULT VALUES, AS THESE REGISTERS HAVE INCO + * RRECT RESET VALUES IN SILICON. + */ + /* + * Register : ATTR_25 @ 0XFD480064 + + * If TRUE Completion Timeout Disable is supported. This is required to be + * TRUE for Endpoint and either setting allowed for Root ports. Drives Devi + * ce Capability 2 [4]; EP=0x0001; RP=0x0001 + * PSU_PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED 0X1 + + * ATTR_25 + * (OFFSET, MASK, VALUE) (0XFD480064, 0x00000200U ,0x00000200U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_25_OFFSET, 0x00000200U, 0x00000200U); +/*##################################################################### */ + + /* + * PCIE SETTINGS + */ + /* + * Register : ATTR_7 @ 0XFD48001C + + * Specifies mask/settings for Base Address Register (BAR) 0. If BAR is not + * to be implemented, set to 32'h00000000. Bits are defined as follows: Me + * mory Space BAR [0] = Mem Space Indicator (set to 0) [2:1] = Type field ( + * 10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask + * for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to 1, w + * here 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63: + * n bits of \'7bBAR1,BAR0\'7d to 1. IO Space BAR 0] = IO Space Indicator ( + * set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of B + * AR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; + * EP=0x0004; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_7_ATTR_BAR0 0x0 + + * ATTR_7 + * (OFFSET, MASK, VALUE) (0XFD48001C, 0x0000FFFFU ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_7_OFFSET, 0x0000FFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_8 @ 0XFD480020 + + * Specifies mask/settings for Base Address Register (BAR) 0. If BAR is not + * to be implemented, set to 32'h00000000. Bits are defined as follows: Me + * mory Space BAR [0] = Mem Space Indicator (set to 0) [2:1] = Type field ( + * 10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask + * for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to 1, w + * here 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63: + * n bits of \'7bBAR1,BAR0\'7d to 1. IO Space BAR 0] = IO Space Indicator ( + * set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of B + * AR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; + * EP=0xFFF0; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_8_ATTR_BAR0 0x0 + + * ATTR_8 + * (OFFSET, MASK, VALUE) (0XFD480020, 0x0000FFFFU ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_8_OFFSET, 0x0000FFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_9 @ 0XFD480024 + + * Specifies mask/settings for Base Address Register (BAR) 1 if BAR0 is a 3 + * 2-bit BAR, or the upper bits of \'7bBAR1,BAR0\'7d if BAR0 is a 64-bit BA + * R. If BAR is not to be implemented, set to 32'h00000000. See BAR0 descri + * ption if this functions as the upper bits of a 64-bit BAR. Bits are defi + * ned as follows: Memory Space BAR (not upper bits of BAR0) [0] = Mem Spac + * e Indicator (set to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) + * [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if + * 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size + * in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR2,BAR1\'7d t + * o 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set + * to 0) [31:2] = Mask for writable bits of BAR; set uppermost 31:n bits t + * o 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_9_ATTR_BAR1 0x0 + + * ATTR_9 + * (OFFSET, MASK, VALUE) (0XFD480024, 0x0000FFFFU ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_9_OFFSET, 0x0000FFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_10 @ 0XFD480028 + + * Specifies mask/settings for Base Address Register (BAR) 1 if BAR0 is a 3 + * 2-bit BAR, or the upper bits of \'7bBAR1,BAR0\'7d if BAR0 is a 64-bit BA + * R. If BAR is not to be implemented, set to 32'h00000000. See BAR0 descri + * ption if this functions as the upper bits of a 64-bit BAR. Bits are defi + * ned as follows: Memory Space BAR (not upper bits of BAR0) [0] = Mem Spac + * e Indicator (set to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) + * [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if + * 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size + * in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR2,BAR1\'7d t + * o 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set + * to 0) [31:2] = Mask for writable bits of BAR; set uppermost 31:n bits t + * o 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_10_ATTR_BAR1 0x0 + + * ATTR_10 + * (OFFSET, MASK, VALUE) (0XFD480028, 0x0000FFFFU ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_10_OFFSET, 0x0000FFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_11 @ 0XFD48002C + + * For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 2 if BAR1 is a 32-bit BAR, or the upper bits of \'7bBAR2,BAR1\'7d if BA + * R1 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR1 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root: This must be set to 00FF_FFF + * F. For an endpoint, bits are defined as follows: Memory Space BAR (not u + * pper bits of BAR1) [0] = Mem Space Indicator (set to 0) [2:1] = Type fie + * ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = M + * ask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to + * 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost + * 63:n bits of \'7bBAR3,BAR2\'7d to 1. IO Space BAR 0] = IO Space Indicat + * or (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits + * of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in byt + * es.; EP=0x0004; RP=0xFFFF + * PSU_PCIE_ATTRIB_ATTR_11_ATTR_BAR2 0xFFFF + + * ATTR_11 + * (OFFSET, MASK, VALUE) (0XFD48002C, 0x0000FFFFU ,0x0000FFFFU) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_11_OFFSET, 0x0000FFFFU, 0x0000FFFFU); +/*##################################################################### */ + + /* + * Register : ATTR_12 @ 0XFD480030 + + * For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 2 if BAR1 is a 32-bit BAR, or the upper bits of \'7bBAR2,BAR1\'7d if BA + * R1 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR1 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root: This must be set to 00FF_FFF + * F. For an endpoint, bits are defined as follows: Memory Space BAR (not u + * pper bits of BAR1) [0] = Mem Space Indicator (set to 0) [2:1] = Type fie + * ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = M + * ask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to + * 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost + * 63:n bits of \'7bBAR3,BAR2\'7d to 1. IO Space BAR 0] = IO Space Indicat + * or (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits + * of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in byt + * es.; EP=0xFFF0; RP=0x00FF + * PSU_PCIE_ATTRIB_ATTR_12_ATTR_BAR2 0xFF + + * ATTR_12 + * (OFFSET, MASK, VALUE) (0XFD480030, 0x0000FFFFU ,0x000000FFU) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_12_OFFSET, 0x0000FFFFU, 0x000000FFU); +/*##################################################################### */ + + /* + * Register : ATTR_13 @ 0XFD480034 + + * For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 3 if BAR2 is a 32-bit BAR, or the upper bits of \'7bBAR3,BAR2\'7d if BA + * R2 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR2 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root, this must be set to: FFFF_00 + * 00 = IO Limit/Base Registers not implemented FFFF_F0F0 = IO Limit/Base R + * egisters use 16-bit decode FFFF_F1F1 = IO Limit/Base Registers use 32-bi + * t decode For an endpoint, bits are defined as follows: Memory Space BAR + * (not upper bits of BAR2) [0] = Mem Space Indicator (set to 0) [2:1] = Ty + * pe field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31: + * 4] = Mask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bi + * ts to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set upp + * ermost 63:n bits of \'7bBAR4,BAR3\'7d to 1. IO Space BAR 0] = IO Space I + * ndicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable + * bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size + * in bytes.; EP=0xFFFF; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_13_ATTR_BAR3 0x0 + + * ATTR_13 + * (OFFSET, MASK, VALUE) (0XFD480034, 0x0000FFFFU ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_13_OFFSET, 0x0000FFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_14 @ 0XFD480038 + + * For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 3 if BAR2 is a 32-bit BAR, or the upper bits of \'7bBAR3,BAR2\'7d if BA + * R2 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR2 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root, this must be set to: FFFF_00 + * 00 = IO Limit/Base Registers not implemented FFFF_F0F0 = IO Limit/Base R + * egisters use 16-bit decode FFFF_F1F1 = IO Limit/Base Registers use 32-bi + * t decode For an endpoint, bits are defined as follows: Memory Space BAR + * (not upper bits of BAR2) [0] = Mem Space Indicator (set to 0) [2:1] = Ty + * pe field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31: + * 4] = Mask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bi + * ts to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set upp + * ermost 63:n bits of \'7bBAR4,BAR3\'7d to 1. IO Space BAR 0] = IO Space I + * ndicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable + * bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size + * in bytes.; EP=0xFFFF; RP=0xFFFF + * PSU_PCIE_ATTRIB_ATTR_14_ATTR_BAR3 0xFFFF + + * ATTR_14 + * (OFFSET, MASK, VALUE) (0XFD480038, 0x0000FFFFU ,0x0000FFFFU) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_14_OFFSET, 0x0000FFFFU, 0x0000FFFFU); +/*##################################################################### */ + + /* + * Register : ATTR_15 @ 0XFD48003C + + * For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 4 if BAR3 is a 32-bit BAR, or the upper bits of \'7bBAR4,BAR3\'7d if BA + * R3 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR3 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root: This must be set to FFF0_FFF + * 0. For an endpoint, bits are defined as follows: Memory Space BAR (not u + * pper bits of BAR3) [0] = Mem Space Indicator (set to 0) [2:1] = Type fie + * ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = M + * ask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to + * 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost + * 63:n bits of \'7bBAR5,BAR4\'7d to 1. IO Space BAR 0] = IO Space Indicat + * or (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits + * of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in byt + * es.; EP=0x0004; RP=0xFFF0 + * PSU_PCIE_ATTRIB_ATTR_15_ATTR_BAR4 0xFFF0 + + * ATTR_15 + * (OFFSET, MASK, VALUE) (0XFD48003C, 0x0000FFFFU ,0x0000FFF0U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_15_OFFSET, 0x0000FFFFU, 0x0000FFF0U); +/*##################################################################### */ + + /* + * Register : ATTR_16 @ 0XFD480040 + + * For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 4 if BAR3 is a 32-bit BAR, or the upper bits of \'7bBAR4,BAR3\'7d if BA + * R3 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR3 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root: This must be set to FFF0_FFF + * 0. For an endpoint, bits are defined as follows: Memory Space BAR (not u + * pper bits of BAR3) [0] = Mem Space Indicator (set to 0) [2:1] = Type fie + * ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = M + * ask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to + * 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost + * 63:n bits of \'7bBAR5,BAR4\'7d to 1. IO Space BAR 0] = IO Space Indicat + * or (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits + * of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in byt + * es.; EP=0xFFF0; RP=0xFFF0 + * PSU_PCIE_ATTRIB_ATTR_16_ATTR_BAR4 0xFFF0 + + * ATTR_16 + * (OFFSET, MASK, VALUE) (0XFD480040, 0x0000FFFFU ,0x0000FFF0U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_16_OFFSET, 0x0000FFFFU, 0x0000FFF0U); +/*##################################################################### */ + + /* + * Register : ATTR_17 @ 0XFD480044 + + * For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 5 if BAR4 is a 32-bit BAR, or the upper bits of \'7bBAR5,BAR4\'7d if BA + * R4 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR4 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root, this must be set to: 0000_00 + * 00 = Prefetchable Memory Limit/Base Registers not implemented FFF0_FFF0 + * = 32-bit Prefetchable Memory Limit/Base implemented FFF1_FFF1 = 64-bit P + * refetchable Memory Limit/Base implemented For an endpoint, bits are defi + * ned as follows: Memory Space BAR (not upper bits of BAR4) [0] = Mem Spac + * e Indicator (set to 0) [2:1] = Type field (00 for 32-bit; BAR5 cannot be + * lower part of a 64-bit BAR) [3] = Prefetchable (0 or 1) [31:4] = Mask f + * or writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=memory + * aperture size in bytes. IO Space BAR 0] = IO Space Indicator (set to 1) + * [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set up + * permost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF + * ; RP=0xFFF1 + * PSU_PCIE_ATTRIB_ATTR_17_ATTR_BAR5 0xFFF1 + + * ATTR_17 + * (OFFSET, MASK, VALUE) (0XFD480044, 0x0000FFFFU ,0x0000FFF1U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_17_OFFSET, 0x0000FFFFU, 0x0000FFF1U); +/*##################################################################### */ + + /* + * Register : ATTR_18 @ 0XFD480048 + + * For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 5 if BAR4 is a 32-bit BAR, or the upper bits of \'7bBAR5,BAR4\'7d if BA + * R4 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR4 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root, this must be set to: 0000_00 + * 00 = Prefetchable Memory Limit/Base Registers not implemented FFF0_FFF0 + * = 32-bit Prefetchable Memory Limit/Base implemented FFF1_FFF1 = 64-bit P + * refetchable Memory Limit/Base implemented For an endpoint, bits are defi + * ned as follows: Memory Space BAR (not upper bits of BAR4) [0] = Mem Spac + * e Indicator (set to 0) [2:1] = Type field (00 for 32-bit; BAR5 cannot be + * lower part of a 64-bit BAR) [3] = Prefetchable (0 or 1) [31:4] = Mask f + * or writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=memory + * aperture size in bytes. IO Space BAR 0] = IO Space Indicator (set to 1) + * [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set up + * permost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF + * ; RP=0xFFF1 + * PSU_PCIE_ATTRIB_ATTR_18_ATTR_BAR5 0xFFF1 + + * ATTR_18 + * (OFFSET, MASK, VALUE) (0XFD480048, 0x0000FFFFU ,0x0000FFF1U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_18_OFFSET, 0x0000FFFFU, 0x0000FFF1U); +/*##################################################################### */ + + /* + * Register : ATTR_27 @ 0XFD48006C + + * Specifies maximum payload supported. Valid settings are: 0- 128 bytes, 1 + * - 256 bytes, 2- 512 bytes, 3- 1024 bytes. Transferred to the Device Capa + * bilities register. The values: 4-2048 bytes, 5- 4096 bytes are not suppo + * rted; EP=0x0001; RP=0x0001 + * PSU_PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED 1 + + * Endpoint L1 Acceptable Latency. Records the latency that the endpoint ca + * n withstand on transitions from L1 state to L0 (if L1 state supported). + * Valid settings are: 0h less than 1us, 1h 1 to 2us, 2h 2 to 4us, 3h 4 to + * 8us, 4h 8 to 16us, 5h 16 to 32us, 6h 32 to 64us, 7h more than 64us. For + * Endpoints only. Must be 0h for other devices.; EP=0x0007; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY 0x0 + + * ATTR_27 + * (OFFSET, MASK, VALUE) (0XFD48006C, 0x00000738U ,0x00000100U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_27_OFFSET, 0x00000738U, 0x00000100U); +/*##################################################################### */ + + /* + * Register : ATTR_50 @ 0XFD4800C8 + + * Identifies the type of device/port as follows: 0000b PCI Express Endpoin + * t device, 0001b Legacy PCI Express Endpoint device, 0100b Root Port of P + * CI Express Root Complex, 0101b Upstream Port of PCI Express Switch, 0110 + * b Downstream Port of PCI Express Switch, 0111b PCIE Express to PCI/PCI-X + * Bridge, 1000b PCI/PCI-X to PCI Express Bridge. Transferred to PCI Expre + * ss Capabilities register. Must be consistent with IS_SWITCH and UPSTREAM + * _FACING settings.; EP=0x0000; RP=0x0004 + * PSU_PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE 4 + + * PCIe Capability's Next Capability Offset pointer to the next item in the + * capabilities list, or 00h if this is the final capability.; EP=0x009C; + * RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR 0 + + * ATTR_50 + * (OFFSET, MASK, VALUE) (0XFD4800C8, 0x0000FFF0U ,0x00000040U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_50_OFFSET, 0x0000FFF0U, 0x00000040U); +/*##################################################################### */ + + /* + * Register : ATTR_105 @ 0XFD4801A4 + + * Number of credits that should be advertised for Completion data received + * on Virtual Channel 0. The bytes advertised must be less than or equal t + * o the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0172; RP=0x00CD + * PSU_PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD 0xCD + + * ATTR_105 + * (OFFSET, MASK, VALUE) (0XFD4801A4, 0x000007FFU ,0x000000CDU) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_105_OFFSET, + 0x000007FFU, 0x000000CDU); +/*##################################################################### */ + + /* + * Register : ATTR_106 @ 0XFD4801A8 + + * Number of credits that should be advertised for Completion headers recei + * ved on Virtual Channel 0. The sum of the posted, non posted, and complet + * ion header credits must be <= 80; EP=0x0048; RP=0x0024 + * PSU_PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH 0x24 + + * Number of credits that should be advertised for Non-Posted headers recei + * ved on Virtual Channel 0. The number of non posted data credits advertis + * ed by the block is equal to the number of non posted header credits. The + * sum of the posted, non posted, and completion header credits must be <= + * 80; EP=0x0004; RP=0x000C + * PSU_PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH 0xC + + * ATTR_106 + * (OFFSET, MASK, VALUE) (0XFD4801A8, 0x00003FFFU ,0x00000624U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_106_OFFSET, + 0x00003FFFU, 0x00000624U); +/*##################################################################### */ + + /* + * Register : ATTR_107 @ 0XFD4801AC + + * Number of credits that should be advertised for Non-Posted data received + * on Virtual Channel 0. The number of non posted data credits advertised + * by the block is equal to two times the number of non posted header credi + * ts if atomic operations are supported or is equal to the number of non p + * osted header credits if atomic operations are not supported. The bytes a + * dvertised must be less than or equal to the bram bytes available. See VC + * 0_RX_RAM_LIMIT; EP=0x0008; RP=0x0018 + * PSU_PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD 0x18 + + * ATTR_107 + * (OFFSET, MASK, VALUE) (0XFD4801AC, 0x000007FFU ,0x00000018U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_107_OFFSET, + 0x000007FFU, 0x00000018U); +/*##################################################################### */ + + /* + * Register : ATTR_108 @ 0XFD4801B0 + + * Number of credits that should be advertised for Posted data received on + * Virtual Channel 0. The bytes advertised must be less than or equal to th + * e bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0020; RP=0x00B5 + * PSU_PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD 0xB5 + + * ATTR_108 + * (OFFSET, MASK, VALUE) (0XFD4801B0, 0x000007FFU ,0x000000B5U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_108_OFFSET, + 0x000007FFU, 0x000000B5U); +/*##################################################################### */ + + /* + * Register : ATTR_109 @ 0XFD4801B4 + + * Not currently in use. Invert ECRC generated by block when trn_tecrc_gen_ + * n and trn_terrfwd_n are asserted.; EP=0x0000; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV 0x0 + + * Enables td bit clear and ECRC trim on received TLP's FALSE == don't trim + * TRUE == trim.; EP=0x0001; RP=0x0001 + * PSU_PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM 0x1 + + * Enables ECRC check on received TLP's 0 == don't check 1 == always check + * 3 == check if enabled by ECRC check enable bit of AER cap structure; EP= + * 0x0003; RP=0x0003 + * PSU_PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK 0x3 + + * Index of last packet buffer used by TX TLM (i.e. number of buffers - 1). + * Calculated from max payload size supported and the number of brams conf + * igured for transmit; EP=0x001C; RP=0x001C + * PSU_PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET 0x1c + + * Number of credits that should be advertised for Posted headers received + * on Virtual Channel 0. The sum of the posted, non posted, and completion + * header credits must be <= 80; EP=0x0004; RP=0x0020 + * PSU_PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH 0x20 + + * ATTR_109 + * (OFFSET, MASK, VALUE) (0XFD4801B4, 0x0000FFFFU ,0x00007E20U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_109_OFFSET, + 0x0000FFFFU, 0x00007E20U); +/*##################################################################### */ + + /* + * Register : ATTR_34 @ 0XFD480088 + + * Specifies values to be transferred to Header Type register. Bit 7 should + * be set to '0' indicating single-function device. Bit 0 identifies heade + * r as Type 0 or Type 1, with '0' indicating a Type 0 header.; EP=0x0000; + * RP=0x0001 + * PSU_PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE 0x1 + + * ATTR_34 + * (OFFSET, MASK, VALUE) (0XFD480088, 0x000000FFU ,0x00000001U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_34_OFFSET, 0x000000FFU, 0x00000001U); +/*##################################################################### */ + + /* + * Register : ATTR_53 @ 0XFD4800D4 + + * PM Capability's Next Capability Offset pointer to the next item in the c + * apabilities list, or 00h if this is the final capability.; EP=0x0048; RP + * =0x0060 + * PSU_PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR 0x60 + + * ATTR_53 + * (OFFSET, MASK, VALUE) (0XFD4800D4, 0x000000FFU ,0x00000060U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_53_OFFSET, 0x000000FFU, 0x00000060U); +/*##################################################################### */ + + /* + * Register : ATTR_41 @ 0XFD4800A4 + + * MSI Per-Vector Masking Capable. The value is transferred to the MSI Cont + * rol Register[8]. When set, adds Mask and Pending Dword to Cap structure; + * EP=0x0000; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE 0x0 + + * Indicates that the MSI structures exists. If this is FALSE, then the MSI + * structure cannot be accessed via either the link or the management port + * .; EP=0x0001; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON 0 + + * MSI Capability's Next Capability Offset pointer to the next item in the + * capabilities list, or 00h if this is the final capability.; EP=0x0060; R + * P=0x0000 + * PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR 0x0 + + * Indicates that the MSI structures exists. If this is FALSE, then the MSI + * structure cannot be accessed via either the link or the management port + * .; EP=0x0001; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON 0 + + * ATTR_41 + * (OFFSET, MASK, VALUE) (0XFD4800A4, 0x000003FFU ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_41_OFFSET, 0x000003FFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_97 @ 0XFD480184 + + * Maximum Link Width. Valid settings are: 000001b x1, 000010b x2, 000100b + * x4, 001000b x8.; EP=0x0004; RP=0x0004 + * PSU_PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH 0x1 + + * Used by LTSSM to set Maximum Link Width. Valid settings are: 000001b [x1 + * ], 000010b [x2], 000100b [x4], 001000b [x8].; EP=0x0004; RP=0x0004 + * PSU_PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH 0x1 + + * ATTR_97 + * (OFFSET, MASK, VALUE) (0XFD480184, 0x00000FFFU ,0x00000041U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_97_OFFSET, 0x00000FFFU, 0x00000041U); +/*##################################################################### */ + + /* + * Register : ATTR_100 @ 0XFD480190 + + * TRUE specifies upstream-facing port. FALSE specifies downstream-facing p + * ort.; EP=0x0001; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING 0x0 + + * ATTR_100 + * (OFFSET, MASK, VALUE) (0XFD480190, 0x00000040U ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_100_OFFSET, + 0x00000040U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_101 @ 0XFD480194 + + * Enable the routing of message TLPs to the user through the TRN RX interf + * ace. A bit value of 1 enables routing of the message TLP to the user. Me + * ssages are always decoded by the message decoder. Bit 0 - ERR COR, Bit 1 + * - ERR NONFATAL, Bit 2 - ERR FATAL, Bit 3 - INTA Bit 4 - INTB, Bit 5 - I + * NTC, Bit 6 - INTD, Bit 7 PM_PME, Bit 8 - PME_TO_ACK, Bit 9 - unlock, Bit + * 10 PME_Turn_Off; EP=0x0000; RP=0x07FF + * PSU_PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE 0x7FF + + * Disable BAR filtering. Does not change the behavior of the bar hit outpu + * ts; EP=0x0000; RP=0x0001 + * PSU_PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING 0x1 + + * ATTR_101 + * (OFFSET, MASK, VALUE) (0XFD480194, 0x0000FFE2U ,0x0000FFE2U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_101_OFFSET, + 0x0000FFE2U, 0x0000FFE2U); +/*##################################################################### */ + + /* + * Register : ATTR_37 @ 0XFD480094 + + * Link Bandwidth notification capability. Indicates support for the link b + * andwidth notification status and interrupt mechanism. Required for Root. + * ; EP=0x0000; RP=0x0001 + * PSU_PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP 0x1 + + * Sets the ASPM Optionality Compliance bit, to comply with the 2.1 ASPM Op + * tionality ECN. Transferred to the Link Capabilities register.; EP=0x0001 + * ; RP=0x0001 + * PSU_PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY 0x1 + + * ATTR_37 + * (OFFSET, MASK, VALUE) (0XFD480094, 0x00004200U ,0x00004200U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_37_OFFSET, 0x00004200U, 0x00004200U); +/*##################################################################### */ + + /* + * Register : ATTR_93 @ 0XFD480174 + + * Enables the Replay Timer to use the user-defined LL_REPLAY_TIMEOUT value + * (or combined with the built-in value, depending on LL_REPLAY_TIMEOUT_FU + * NC). If FALSE, the built-in value is used.; EP=0x0000; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN 0x1 + + * Sets a user-defined timeout for the Replay Timer to force cause the retr + * ansmission of unacknowledged TLPs; refer to LL_REPLAY_TIMEOUT_EN and LL_ + * REPLAY_TIMEOUT_FUNC to see how this value is used. The unit for this att + * ribute is in symbol times, which is 4ns at GEN1 speeds and 2ns at GEN2.; + * EP=0x0000; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT 0x1000 + + * ATTR_93 + * (OFFSET, MASK, VALUE) (0XFD480174, 0x0000FFFFU ,0x00009000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_93_OFFSET, 0x0000FFFFU, 0x00009000U); +/*##################################################################### */ + + /* + * Register : ID @ 0XFD480200 + + * Device ID for the the PCIe Cap Structure Device ID field + * PSU_PCIE_ATTRIB_ID_CFG_DEV_ID 0xd021 + + * Vendor ID for the PCIe Cap Structure Vendor ID field + * PSU_PCIE_ATTRIB_ID_CFG_VEND_ID 0x10ee + + * ID + * (OFFSET, MASK, VALUE) (0XFD480200, 0xFFFFFFFFU ,0x10EED021U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ID_OFFSET, 0xFFFFFFFFU, 0x10EED021U); +/*##################################################################### */ + + /* + * Register : SUBSYS_ID @ 0XFD480204 + + * Subsystem ID for the the PCIe Cap Structure Subsystem ID field + * PSU_PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID 0x7 + + * Subsystem Vendor ID for the PCIe Cap Structure Subsystem Vendor ID field + * PSU_PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID 0x10ee + + * SUBSYS_ID + * (OFFSET, MASK, VALUE) (0XFD480204, 0xFFFFFFFFU ,0x10EE0007U) + */ + PSU_Mask_Write(PCIE_ATTRIB_SUBSYS_ID_OFFSET, + 0xFFFFFFFFU, 0x10EE0007U); +/*##################################################################### */ + + /* + * Register : REV_ID @ 0XFD480208 + + * Revision ID for the the PCIe Cap Structure + * PSU_PCIE_ATTRIB_REV_ID_CFG_REV_ID 0x0 + + * REV_ID + * (OFFSET, MASK, VALUE) (0XFD480208, 0x000000FFU ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_REV_ID_OFFSET, 0x000000FFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_24 @ 0XFD480060 + + * Code identifying basic function, subclass and applicable programming int + * erface. Transferred to the Class Code register.; EP=0x8000; RP=0x8000 + * PSU_PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE 0x400 + + * ATTR_24 + * (OFFSET, MASK, VALUE) (0XFD480060, 0x0000FFFFU ,0x00000400U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_24_OFFSET, 0x0000FFFFU, 0x00000400U); +/*##################################################################### */ + + /* + * Register : ATTR_25 @ 0XFD480064 + + * Code identifying basic function, subclass and applicable programming int + * erface. Transferred to the Class Code register.; EP=0x0005; RP=0x0006 + * PSU_PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE 0x6 + + * INTX Interrupt Generation Capable. If FALSE, this will cause Command[10] + * to be hardwired to 0.; EP=0x0001; RP=0x0001 + * PSU_PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED 0 + + * ATTR_25 + * (OFFSET, MASK, VALUE) (0XFD480064, 0x000001FFU ,0x00000006U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_25_OFFSET, 0x000001FFU, 0x00000006U); +/*##################################################################### */ + + /* + * Register : ATTR_4 @ 0XFD480010 + + * Indicates that the AER structures exists. If this is FALSE, then the AER + * structure cannot be accessed via either the link or the management port + * , and AER will be considered to not be present for error management task + * s (such as what types of error messages are sent if an error is detected + * ).; EP=0x0001; RP=0x0001 + * PSU_PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON 0 + + * Indicates that the AER structures exists. If this is FALSE, then the AER + * structure cannot be accessed via either the link or the management port + * , and AER will be considered to not be present for error management task + * s (such as what types of error messages are sent if an error is detected + * ).; EP=0x0001; RP=0x0001 + * PSU_PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON 0 + + * ATTR_4 + * (OFFSET, MASK, VALUE) (0XFD480010, 0x00001000U ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_4_OFFSET, 0x00001000U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_89 @ 0XFD480164 + + * VSEC's Next Capability Offset pointer to the next item in the capabiliti + * es list, or 000h if this is the final capability.; EP=0x0140; RP=0x0140 + * PSU_PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR 0 + + * ATTR_89 + * (OFFSET, MASK, VALUE) (0XFD480164, 0x00001FFEU ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_89_OFFSET, 0x00001FFEU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_79 @ 0XFD48013C + + * CRS SW Visibility. Indicates RC can return CRS to SW. Transferred to the + * Root Capabilities register.; EP=0x0000; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY 1 + + * ATTR_79 + * (OFFSET, MASK, VALUE) (0XFD48013C, 0x00000020U ,0x00000020U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_79_OFFSET, 0x00000020U, 0x00000020U); +/*##################################################################### */ + + /* + * Register : ATTR_43 @ 0XFD4800AC + + * Indicates that the MSIX structures exists. If this is FALSE, then the MS + * IX structure cannot be accessed via either the link or the management po + * rt.; EP=0x0001; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON 0 + + * ATTR_43 + * (OFFSET, MASK, VALUE) (0XFD4800AC, 0x00000100U ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_43_OFFSET, 0x00000100U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_48 @ 0XFD4800C0 + + * MSI-X Table Size. This value is transferred to the MSI-X Message Control + * [10:0] field. Set to 0 if MSI-X is not enabled. Note that the core does + * not implement the table; that must be implemented in user logic.; EP=0x0 + * 003; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE 0 + + * ATTR_48 + * (OFFSET, MASK, VALUE) (0XFD4800C0, 0x000007FFU ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_48_OFFSET, 0x000007FFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_46 @ 0XFD4800B8 + + * MSI-X Table Offset. This value is transferred to the MSI-X Table Offset + * field. Set to 0 if MSI-X is not enabled.; EP=0x0001; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET 0 + + * ATTR_46 + * (OFFSET, MASK, VALUE) (0XFD4800B8, 0x0000FFFFU ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_46_OFFSET, 0x0000FFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_47 @ 0XFD4800BC + + * MSI-X Table Offset. This value is transferred to the MSI-X Table Offset + * field. Set to 0 if MSI-X is not enabled.; EP=0x0000; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET 0 + + * ATTR_47 + * (OFFSET, MASK, VALUE) (0XFD4800BC, 0x00001FFFU ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_47_OFFSET, 0x00001FFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_44 @ 0XFD4800B0 + + * MSI-X Pending Bit Array Offset This value is transferred to the MSI-X PB + * A Offset field. Set to 0 if MSI-X is not enabled.; EP=0x0001; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET 0 + + * ATTR_44 + * (OFFSET, MASK, VALUE) (0XFD4800B0, 0x0000FFFFU ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_44_OFFSET, 0x0000FFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_45 @ 0XFD4800B4 + + * MSI-X Pending Bit Array Offset This value is transferred to the MSI-X PB + * A Offset field. Set to 0 if MSI-X is not enabled.; EP=0x1000; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET 0 + + * ATTR_45 + * (OFFSET, MASK, VALUE) (0XFD4800B4, 0x0000FFF8U ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_45_OFFSET, 0x0000FFF8U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : CB @ 0XFD48031C + + * DT837748 Enable + * PSU_PCIE_ATTRIB_CB_CB1 0x0 + + * ECO Register 1 + * (OFFSET, MASK, VALUE) (0XFD48031C, 0x00000002U ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_CB_OFFSET, 0x00000002U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_35 @ 0XFD48008C + + * Active State PM Support. Indicates the level of active state power manag + * ement supported by the selected PCI Express Link, encoded as follows: 0 + * Reserved, 1 L0s entry supported, 2 Reserved, 3 L0s and L1 entry supporte + * d.; EP=0x0001; RP=0x0001 + * PSU_PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT 0x0 + + * ATTR_35 + * (OFFSET, MASK, VALUE) (0XFD48008C, 0x00003000U ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_35_OFFSET, 0x00003000U, 0x00000000U); +/*##################################################################### */ + + /* + * PUTTING PCIE CONTROL IN RESET + */ + /* + * Register : RST_FPD_TOP @ 0XFD1A0100 + + * PCIE control block level reset + * PSU_CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET 0X0 + + * FPD Block level software controlled reset + * (OFFSET, MASK, VALUE) (0XFD1A0100, 0x00020000U ,0x00000000U) + */ + PSU_Mask_Write(CRF_APB_RST_FPD_TOP_OFFSET, 0x00020000U, 0x00000000U); +/*##################################################################### */ + + /* + * PCIE GPIO RESET + */ + /* + * MASK_DATA_0_LSW LOW BANK [15:0] + */ + /* + * MASK_DATA_0_MSW LOW BANK [25:16] + */ + /* + * MASK_DATA_1_LSW LOW BANK [41:26] + */ + /* + * Register : MASK_DATA_1_LSW @ 0XFF0A0008 + + * Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW] + * PSU_GPIO_MASK_DATA_1_LSW_MASK_1_LSW 0xffdf + + * Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW] + * PSU_GPIO_MASK_DATA_1_LSW_DATA_1_LSW 0x20 + + * Maskable Output Data (GPIO Bank1, MIO, Lower 16bits) + * (OFFSET, MASK, VALUE) (0XFF0A0008, 0xFFFFFFFFU ,0xFFDF0020U) + */ + PSU_Mask_Write(GPIO_MASK_DATA_1_LSW_OFFSET, + 0xFFFFFFFFU, 0xFFDF0020U); +/*##################################################################### */ + + /* + * MASK_DATA_1_MSW HIGH BANK [51:42] + */ + /* + * MASK_DATA_1_LSW HIGH BANK [67:52] + */ + /* + * MASK_DATA_1_LSW HIGH BANK [77:68] + */ + /* + * CHECK PLL LOCK FOR LANE0 + */ + /* + * Register : L0_PLL_STATUS_READ_1 @ 0XFD4023E4 + + * Status Read value of PLL Lock + * PSU_SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1 + * (OFFSET, MASK, VALUE) (0XFD4023E4, 0x00000010U ,0x00000010U) + */ + mask_poll(SERDES_L0_PLL_STATUS_READ_1_OFFSET, 0x00000010U); + +/*##################################################################### */ + + /* + * CHECK PLL LOCK FOR LANE1 + */ + /* + * Register : L1_PLL_STATUS_READ_1 @ 0XFD4063E4 + + * Status Read value of PLL Lock + * PSU_SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1 + * (OFFSET, MASK, VALUE) (0XFD4063E4, 0x00000010U ,0x00000010U) + */ + mask_poll(SERDES_L1_PLL_STATUS_READ_1_OFFSET, 0x00000010U); + +/*##################################################################### */ + + /* + * CHECK PLL LOCK FOR LANE2 + */ + /* + * Register : L2_PLL_STATUS_READ_1 @ 0XFD40A3E4 + + * Status Read value of PLL Lock + * PSU_SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1 + * (OFFSET, MASK, VALUE) (0XFD40A3E4, 0x00000010U ,0x00000010U) + */ + mask_poll(SERDES_L2_PLL_STATUS_READ_1_OFFSET, 0x00000010U); + +/*##################################################################### */ + + /* + * CHECK PLL LOCK FOR LANE3 + */ + /* + * Register : L3_PLL_STATUS_READ_1 @ 0XFD40E3E4 + + * Status Read value of PLL Lock + * PSU_SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1 + * (OFFSET, MASK, VALUE) (0XFD40E3E4, 0x00000010U ,0x00000010U) + */ + mask_poll(SERDES_L3_PLL_STATUS_READ_1_OFFSET, 0x00000010U); + +/*##################################################################### */ + + /* + * SATA AHCI VENDOR SETTING + */ + /* + * Register : PP2C @ 0XFD0C00AC + + * CIBGMN: COMINIT Burst Gap Minimum. + * PSU_SATA_AHCI_VENDOR_PP2C_CIBGMN 0x18 + + * CIBGMX: COMINIT Burst Gap Maximum. + * PSU_SATA_AHCI_VENDOR_PP2C_CIBGMX 0x40 + + * CIBGN: COMINIT Burst Gap Nominal. + * PSU_SATA_AHCI_VENDOR_PP2C_CIBGN 0x18 + + * CINMP: COMINIT Negate Minimum Period. + * PSU_SATA_AHCI_VENDOR_PP2C_CINMP 0x28 + + * PP2C - Port Phy2Cfg Register. This register controls the configuration o + * f the Phy Control OOB timing for the COMINIT parameters for either Port + * 0 or Port 1. The Port configured is controlled by the value programmed i + * nto the Port Config Register. + * (OFFSET, MASK, VALUE) (0XFD0C00AC, 0xFFFFFFFFU ,0x28184018U) + */ + PSU_Mask_Write(SATA_AHCI_VENDOR_PP2C_OFFSET, + 0xFFFFFFFFU, 0x28184018U); +/*##################################################################### */ + + /* + * Register : PP3C @ 0XFD0C00B0 + + * CWBGMN: COMWAKE Burst Gap Minimum. + * PSU_SATA_AHCI_VENDOR_PP3C_CWBGMN 0x06 + + * CWBGMX: COMWAKE Burst Gap Maximum. + * PSU_SATA_AHCI_VENDOR_PP3C_CWBGMX 0x14 + + * CWBGN: COMWAKE Burst Gap Nominal. + * PSU_SATA_AHCI_VENDOR_PP3C_CWBGN 0x08 + + * CWNMP: COMWAKE Negate Minimum Period. + * PSU_SATA_AHCI_VENDOR_PP3C_CWNMP 0x0E + + * PP3C - Port Phy3CfgRegister. This register controls the configuration of + * the Phy Control OOB timing for the COMWAKE parameters for either Port 0 + * or Port 1. The Port configured is controlled by the value programmed in + * to the Port Config Register. + * (OFFSET, MASK, VALUE) (0XFD0C00B0, 0xFFFFFFFFU ,0x0E081406U) + */ + PSU_Mask_Write(SATA_AHCI_VENDOR_PP3C_OFFSET, + 0xFFFFFFFFU, 0x0E081406U); +/*##################################################################### */ + + /* + * Register : PP4C @ 0XFD0C00B4 + + * BMX: COM Burst Maximum. + * PSU_SATA_AHCI_VENDOR_PP4C_BMX 0x13 + + * BNM: COM Burst Nominal. + * PSU_SATA_AHCI_VENDOR_PP4C_BNM 0x08 + + * SFD: Signal Failure Detection, if the signal detection de-asserts for a + * time greater than this then the OOB detector will determine this is a li + * ne idle and cause the PhyInit state machine to exit the Phy Ready State. + * A value of zero disables the Signal Failure Detector. The value is base + * d on the OOB Detector Clock typically (PMCLK Clock Period) * SFD giving + * a nominal time of 500ns based on a 150MHz PMCLK. + * PSU_SATA_AHCI_VENDOR_PP4C_SFD 0x4A + + * PTST: Partial to Slumber timer value, specific delay the controller shou + * ld apply while in partial before entering slumber. The value is bases on + * the system clock divided by 128, total delay = (Sys Clock Period) * PTS + * T * 128 + * PSU_SATA_AHCI_VENDOR_PP4C_PTST 0x06 + + * PP4C - Port Phy4Cfg Register. This register controls the configuration o + * f the Phy Control Burst timing for the COM parameters for either Port 0 + * or Port 1. The Port configured is controlled by the value programmed int + * o the Port Config Register. + * (OFFSET, MASK, VALUE) (0XFD0C00B4, 0xFFFFFFFFU ,0x064A0813U) + */ + PSU_Mask_Write(SATA_AHCI_VENDOR_PP4C_OFFSET, + 0xFFFFFFFFU, 0x064A0813U); +/*##################################################################### */ + + /* + * Register : PP5C @ 0XFD0C00B8 + + * RIT: Retry Interval Timer. The calculated value divided by two, the lowe + * r digit of precision is not needed. + * PSU_SATA_AHCI_VENDOR_PP5C_RIT 0xC96A4 + + * RCT: Rate Change Timer, a value based on the 54.2us for which a SATA dev + * ice will transmit at a fixed rate ALIGNp after OOB has completed, for a + * fast SERDES it is suggested that this value be 54.2us / 4 + * PSU_SATA_AHCI_VENDOR_PP5C_RCT 0x3FF + + * PP5C - Port Phy5Cfg Register. This register controls the configuration o + * f the Phy Control Retry Interval timing for either Port 0 or Port 1. The + * Port configured is controlled by the value programmed into the Port Con + * fig Register. + * (OFFSET, MASK, VALUE) (0XFD0C00B8, 0xFFFFFFFFU ,0x3FFC96A4U) + */ + PSU_Mask_Write(SATA_AHCI_VENDOR_PP5C_OFFSET, + 0xFFFFFFFFU, 0x3FFC96A4U); +/*##################################################################### */ - return 1; + return 1; } -unsigned long psu_ps_pl_isolation_removal_data() { - // : PS-PL POWER UP REQUEST - /*Register : REQ_PWRUP_INT_EN @ 0XFFD80118

+unsigned long psu_resetin_init_data(void) +{ + /* + * PUTTING SERDES PERIPHERAL IN RESET + */ + /* + * PUTTING USB0 IN RESET + */ + /* + * Register : RST_LPD_TOP @ 0XFF5E023C - Power-up Request Interrupt Enable for PL - PSU_PMU_GLOBAL_REQ_PWRUP_INT_EN_PL 1 + * USB 0 reset for control registers + * PSU_CRL_APB_RST_LPD_TOP_USB0_APB_RESET 0X1 - Power-up Request Interrupt Enable Register. Writing a 1 to this location will unmask the interrupt. - (OFFSET, MASK, VALUE) (0XFFD80118, 0x00800000U ,0x00800000U) - RegMask = (PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_MASK | 0 ); + * USB 0 sleep circuit reset + * PSU_CRL_APB_RST_LPD_TOP_USB0_HIBERRESET 0X1 - RegVal = ((0x00000001U << PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PMU_GLOBAL_REQ_PWRUP_INT_EN_OFFSET ,0x00800000U ,0x00800000U); - /*############################################################################################################################ */ + * USB 0 reset + * PSU_CRL_APB_RST_LPD_TOP_USB0_CORERESET 0X1 - /*Register : REQ_PWRUP_TRIG @ 0XFFD80120

+ * Software control register for the LPD block. + * (OFFSET, MASK, VALUE) (0XFF5E023C, 0x00000540U ,0x00000540U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_TOP_OFFSET, 0x00000540U, 0x00000540U); +/*##################################################################### */ - Power-up Request Trigger for PL - PSU_PMU_GLOBAL_REQ_PWRUP_TRIG_PL 1 + /* + * PUTTING GEM0 IN RESET + */ + /* + * Register : RST_LPD_IOU0 @ 0XFF5E0230 - Power-up Request Trigger Register. A write of one to this location will generate a power-up request to the PMU. - (OFFSET, MASK, VALUE) (0XFFD80120, 0x00800000U ,0x00800000U) - RegMask = (PMU_GLOBAL_REQ_PWRUP_TRIG_PL_MASK | 0 ); + * GEM 3 reset + * PSU_CRL_APB_RST_LPD_IOU0_GEM3_RESET 0X1 - RegVal = ((0x00000001U << PMU_GLOBAL_REQ_PWRUP_TRIG_PL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PMU_GLOBAL_REQ_PWRUP_TRIG_OFFSET ,0x00800000U ,0x00800000U); - /*############################################################################################################################ */ + * Software controlled reset for the GEMs + * (OFFSET, MASK, VALUE) (0XFF5E0230, 0x00000008U ,0x00000008U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_IOU0_OFFSET, + 0x00000008U, 0x00000008U); +/*##################################################################### */ - // : POLL ON PL POWER STATUS - /*Register : REQ_PWRUP_STATUS @ 0XFFD80110

+ /* + * PUTTING SATA IN RESET + */ + /* + * Register : RST_FPD_TOP @ 0XFD1A0100 - Power-up Request Status for PL - PSU_PMU_GLOBAL_REQ_PWRUP_STATUS_PL 1 - (OFFSET, MASK, VALUE) (0XFFD80110, 0x00800000U ,0x00000000U) */ - mask_pollOnValue(PMU_GLOBAL_REQ_PWRUP_STATUS_OFFSET,0x00800000U,0x00000000U); + * Sata block level reset + * PSU_CRF_APB_RST_FPD_TOP_SATA_RESET 0X1 - /*############################################################################################################################ */ + * FPD Block level software controlled reset + * (OFFSET, MASK, VALUE) (0XFD1A0100, 0x00000002U ,0x00000002U) + */ + PSU_Mask_Write(CRF_APB_RST_FPD_TOP_OFFSET, 0x00000002U, 0x00000002U); +/*##################################################################### */ + + /* + * PUTTING PCIE IN RESET + */ + /* + * Register : RST_FPD_TOP @ 0XFD1A0100 + + * PCIE config reset + * PSU_CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET 0X1 + + * PCIE control block level reset + * PSU_CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET 0X1 + + * PCIE bridge block level reset (AXI interface) + * PSU_CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET 0X1 + + * FPD Block level software controlled reset + * (OFFSET, MASK, VALUE) (0XFD1A0100, 0x000E0000U ,0x000E0000U) + */ + PSU_Mask_Write(CRF_APB_RST_FPD_TOP_OFFSET, 0x000E0000U, 0x000E0000U); +/*##################################################################### */ + + /* + * PUTTING DP IN RESET + */ + /* + * Register : DP_TX_PHY_POWER_DOWN @ 0XFD4A0238 + + * Two bits per lane. When set to 11, moves the GT to power down mode. When + * set to 00, GT will be in active state. bits [1:0] - lane0 Bits [3:2] - + * lane 1 + * PSU_DP_DP_TX_PHY_POWER_DOWN_POWER_DWN 0XA + + * Control PHY Power down + * (OFFSET, MASK, VALUE) (0XFD4A0238, 0x0000000FU ,0x0000000AU) + */ + PSU_Mask_Write(DP_DP_TX_PHY_POWER_DOWN_OFFSET, + 0x0000000FU, 0x0000000AU); +/*##################################################################### */ + + /* + * Register : DP_PHY_RESET @ 0XFD4A0200 + + * Set to '1' to hold the GT in reset. Clear to release. + * PSU_DP_DP_PHY_RESET_GT_RESET 0X1 + + * Reset the transmitter PHY. + * (OFFSET, MASK, VALUE) (0XFD4A0200, 0x00000002U ,0x00000002U) + */ + PSU_Mask_Write(DP_DP_PHY_RESET_OFFSET, 0x00000002U, 0x00000002U); +/*##################################################################### */ + + /* + * Register : RST_FPD_TOP @ 0XFD1A0100 + + * Display Port block level reset (includes DPDMA) + * PSU_CRF_APB_RST_FPD_TOP_DP_RESET 0X1 + + * FPD Block level software controlled reset + * (OFFSET, MASK, VALUE) (0XFD1A0100, 0x00010000U ,0x00010000U) + */ + PSU_Mask_Write(CRF_APB_RST_FPD_TOP_OFFSET, 0x00010000U, 0x00010000U); +/*##################################################################### */ - return 1; + return 1; } -unsigned long psu_ps_pl_reset_config_data() { - // : PS PL RESET SEQUENCE - // : FABRIC RESET USING EMIO - /*Register : MASK_DATA_5_MSW @ 0XFF0A002C

+unsigned long psu_ps_pl_isolation_removal_data(void) +{ + /* + * PS-PL POWER UP REQUEST + */ + /* + * Register : REQ_PWRUP_INT_EN @ 0XFFD80118 - Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW] - PSU_GPIO_MASK_DATA_5_MSW_MASK_5_MSW 0x8000 + * Power-up Request Interrupt Enable for PL + * PSU_PMU_GLOBAL_REQ_PWRUP_INT_EN_PL 1 - Maskable Output Data (GPIO Bank5, EMIO, Upper 16bits) - (OFFSET, MASK, VALUE) (0XFF0A002C, 0xFFFF0000U ,0x80000000U) - RegMask = (GPIO_MASK_DATA_5_MSW_MASK_5_MSW_MASK | 0 ); + * Power-up Request Interrupt Enable Register. Writing a 1 to this location + * will unmask the interrupt. + * (OFFSET, MASK, VALUE) (0XFFD80118, 0x00800000U ,0x00800000U) + */ + PSU_Mask_Write(PMU_GLOBAL_REQ_PWRUP_INT_EN_OFFSET, + 0x00800000U, 0x00800000U); +/*##################################################################### */ - RegVal = ((0x00008000U << GPIO_MASK_DATA_5_MSW_MASK_5_MSW_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (GPIO_MASK_DATA_5_MSW_OFFSET ,0xFFFF0000U ,0x80000000U); - /*############################################################################################################################ */ + /* + * Register : REQ_PWRUP_TRIG @ 0XFFD80120 - /*Register : DIRM_5 @ 0XFF0A0344

+ * Power-up Request Trigger for PL + * PSU_PMU_GLOBAL_REQ_PWRUP_TRIG_PL 1 - Operation is the same as DIRM_0[DIRECTION_0] - PSU_GPIO_DIRM_5_DIRECTION_5 0x80000000 + * Power-up Request Trigger Register. A write of one to this location will + * generate a power-up request to the PMU. + * (OFFSET, MASK, VALUE) (0XFFD80120, 0x00800000U ,0x00800000U) + */ + PSU_Mask_Write(PMU_GLOBAL_REQ_PWRUP_TRIG_OFFSET, + 0x00800000U, 0x00800000U); +/*##################################################################### */ - Direction mode (GPIO Bank5, EMIO) - (OFFSET, MASK, VALUE) (0XFF0A0344, 0xFFFFFFFFU ,0x80000000U) - RegMask = (GPIO_DIRM_5_DIRECTION_5_MASK | 0 ); + /* + * POLL ON PL POWER STATUS + */ + /* + * Register : REQ_PWRUP_STATUS @ 0XFFD80110 - RegVal = ((0x80000000U << GPIO_DIRM_5_DIRECTION_5_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (GPIO_DIRM_5_OFFSET ,0xFFFFFFFFU ,0x80000000U); - /*############################################################################################################################ */ + * Power-up Request Status for PL + * PSU_PMU_GLOBAL_REQ_PWRUP_STATUS_PL 1 + * (OFFSET, MASK, VALUE) (0XFFD80110, 0x00800000U ,0x00000000U) + */ + mask_pollOnValue(PMU_GLOBAL_REQ_PWRUP_STATUS_OFFSET, + 0x00800000U, 0x00000000U); - /*Register : OEN_5 @ 0XFF0A0348

+/*##################################################################### */ - Operation is the same as OEN_0[OP_ENABLE_0] - PSU_GPIO_OEN_5_OP_ENABLE_5 0x80000000 - Output enable (GPIO Bank5, EMIO) - (OFFSET, MASK, VALUE) (0XFF0A0348, 0xFFFFFFFFU ,0x80000000U) - RegMask = (GPIO_OEN_5_OP_ENABLE_5_MASK | 0 ); + return 1; +} +unsigned long psu_afi_config(void) +{ + /* + * AFI RESET + */ + /* + * Register : RST_FPD_TOP @ 0XFD1A0100 - RegVal = ((0x80000000U << GPIO_OEN_5_OP_ENABLE_5_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (GPIO_OEN_5_OFFSET ,0xFFFFFFFFU ,0x80000000U); - /*############################################################################################################################ */ + * AF_FM0 block level reset + * PSU_CRF_APB_RST_FPD_TOP_AFI_FM0_RESET 0 - /*Register : DATA_5 @ 0XFF0A0054

+ * AF_FM1 block level reset + * PSU_CRF_APB_RST_FPD_TOP_AFI_FM1_RESET 0 - Output Data - PSU_GPIO_DATA_5_DATA_5 0x80000000 + * AF_FM2 block level reset + * PSU_CRF_APB_RST_FPD_TOP_AFI_FM2_RESET 0 - Output Data (GPIO Bank5, EMIO) - (OFFSET, MASK, VALUE) (0XFF0A0054, 0xFFFFFFFFU ,0x80000000U) - RegMask = (GPIO_DATA_5_DATA_5_MASK | 0 ); + * AF_FM3 block level reset + * PSU_CRF_APB_RST_FPD_TOP_AFI_FM3_RESET 0 - RegVal = ((0x80000000U << GPIO_DATA_5_DATA_5_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (GPIO_DATA_5_OFFSET ,0xFFFFFFFFU ,0x80000000U); - /*############################################################################################################################ */ + * AF_FM4 block level reset + * PSU_CRF_APB_RST_FPD_TOP_AFI_FM4_RESET 0 + + * AF_FM5 block level reset + * PSU_CRF_APB_RST_FPD_TOP_AFI_FM5_RESET 0 + + * FPD Block level software controlled reset + * (OFFSET, MASK, VALUE) (0XFD1A0100, 0x00001F80U ,0x00000000U) + */ + PSU_Mask_Write(CRF_APB_RST_FPD_TOP_OFFSET, 0x00001F80U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : RST_LPD_TOP @ 0XFF5E023C + + * AFI FM 6 + * PSU_CRL_APB_RST_LPD_TOP_AFI_FM6_RESET 0 + + * Software control register for the LPD block. + * (OFFSET, MASK, VALUE) (0XFF5E023C, 0x00080000U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_TOP_OFFSET, 0x00080000U, 0x00000000U); +/*##################################################################### */ + + /* + * AFIFM INTERFACE WIDTH + */ + /* + * Register : afi_fs @ 0XFD615000 + + * Select the 32/64/128-bit data width selection for the Slave 0 00: 32-bit + * AXI data width (default) 01: 64-bit AXI data width 10: 128-bit AXI data + * width 11: reserved + * PSU_FPD_SLCR_AFI_FS_DW_SS0_SEL 0x2 + + * Select the 32/64/128-bit data width selection for the Slave 1 00: 32-bit + * AXI data width (default) 01: 64-bit AXI data width 10: 128-bit AXI data + * width 11: reserved + * PSU_FPD_SLCR_AFI_FS_DW_SS1_SEL 0x2 + + * afi fs SLCR control register. This register is static and should not be + * modified during operation. + * (OFFSET, MASK, VALUE) (0XFD615000, 0x00000F00U ,0x00000A00U) + */ + PSU_Mask_Write(FPD_SLCR_AFI_FS_OFFSET, 0x00000F00U, 0x00000A00U); +/*##################################################################### */ + + + return 1; +} +unsigned long psu_ps_pl_reset_config_data(void) +{ + /* + * PS PL RESET SEQUENCE + */ + /* + * FABRIC RESET USING EMIO + */ + /* + * Register : MASK_DATA_5_MSW @ 0XFF0A002C + + * Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW] + * PSU_GPIO_MASK_DATA_5_MSW_MASK_5_MSW 0x8000 + + * Maskable Output Data (GPIO Bank5, EMIO, Upper 16bits) + * (OFFSET, MASK, VALUE) (0XFF0A002C, 0xFFFF0000U ,0x80000000U) + */ + PSU_Mask_Write(GPIO_MASK_DATA_5_MSW_OFFSET, + 0xFFFF0000U, 0x80000000U); +/*##################################################################### */ + + /* + * Register : DIRM_5 @ 0XFF0A0344 + + * Operation is the same as DIRM_0[DIRECTION_0] + * PSU_GPIO_DIRM_5_DIRECTION_5 0x80000000 + + * Direction mode (GPIO Bank5, EMIO) + * (OFFSET, MASK, VALUE) (0XFF0A0344, 0xFFFFFFFFU ,0x80000000U) + */ + PSU_Mask_Write(GPIO_DIRM_5_OFFSET, 0xFFFFFFFFU, 0x80000000U); +/*##################################################################### */ + + /* + * Register : OEN_5 @ 0XFF0A0348 + + * Operation is the same as OEN_0[OP_ENABLE_0] + * PSU_GPIO_OEN_5_OP_ENABLE_5 0x80000000 + + * Output enable (GPIO Bank5, EMIO) + * (OFFSET, MASK, VALUE) (0XFF0A0348, 0xFFFFFFFFU ,0x80000000U) + */ + PSU_Mask_Write(GPIO_OEN_5_OFFSET, 0xFFFFFFFFU, 0x80000000U); +/*##################################################################### */ + + /* + * Register : DATA_5 @ 0XFF0A0054 + + * Output Data + * PSU_GPIO_DATA_5_DATA_5 0x80000000 + + * Output Data (GPIO Bank5, EMIO) + * (OFFSET, MASK, VALUE) (0XFF0A0054, 0xFFFFFFFFU ,0x80000000U) + */ + PSU_Mask_Write(GPIO_DATA_5_OFFSET, 0xFFFFFFFFU, 0x80000000U); +/*##################################################################### */ mask_delay(1); - /*############################################################################################################################ */ +/*##################################################################### */ - // : FABRIC RESET USING DATA_5 TOGGLE - /*Register : DATA_5 @ 0XFF0A0054

+ /* + * FABRIC RESET USING DATA_5 TOGGLE + */ + /* + * Register : DATA_5 @ 0XFF0A0054 - Output Data - PSU_GPIO_DATA_5_DATA_5 0X00000000 + * Output Data + * PSU_GPIO_DATA_5_DATA_5 0X00000000 - Output Data (GPIO Bank5, EMIO) - (OFFSET, MASK, VALUE) (0XFF0A0054, 0xFFFFFFFFU ,0x00000000U) - RegMask = (GPIO_DATA_5_DATA_5_MASK | 0 ); - - RegVal = ((0x00000000U << GPIO_DATA_5_DATA_5_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (GPIO_DATA_5_OFFSET ,0xFFFFFFFFU ,0x00000000U); - /*############################################################################################################################ */ + * Output Data (GPIO Bank5, EMIO) + * (OFFSET, MASK, VALUE) (0XFF0A0054, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(GPIO_DATA_5_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ mask_delay(1); - /*############################################################################################################################ */ +/*##################################################################### */ - // : FABRIC RESET USING DATA_5 TOGGLE - /*Register : DATA_5 @ 0XFF0A0054

+ /* + * FABRIC RESET USING DATA_5 TOGGLE + */ + /* + * Register : DATA_5 @ 0XFF0A0054 - Output Data - PSU_GPIO_DATA_5_DATA_5 0x80000000 + * Output Data + * PSU_GPIO_DATA_5_DATA_5 0x80000000 - Output Data (GPIO Bank5, EMIO) - (OFFSET, MASK, VALUE) (0XFF0A0054, 0xFFFFFFFFU ,0x80000000U) - RegMask = (GPIO_DATA_5_DATA_5_MASK | 0 ); - - RegVal = ((0x80000000U << GPIO_DATA_5_DATA_5_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (GPIO_DATA_5_OFFSET ,0xFFFFFFFFU ,0x80000000U); - /*############################################################################################################################ */ + * Output Data (GPIO Bank5, EMIO) + * (OFFSET, MASK, VALUE) (0XFF0A0054, 0xFFFFFFFFU ,0x80000000U) + */ + PSU_Mask_Write(GPIO_DATA_5_OFFSET, 0xFFFFFFFFU, 0x80000000U); +/*##################################################################### */ - return 1; + return 1; } -unsigned long psu_ddr_phybringup_data() { +unsigned long psu_ddr_phybringup_data(void) +{ + + + unsigned int regval = 0; + + unsigned int pll_retry = 10; + + unsigned int pll_locked = 0; + + + while ((pll_retry > 0) && (!pll_locked)) { + + Xil_Out32(0xFD080004, 0x00040010);/*PIR*/ + Xil_Out32(0xFD080004, 0x00040011);/*PIR*/ + + while ((Xil_In32(0xFD080030) & 0x1) != 1) { + /*****TODO*****/ + + /*TIMEOUT poll mechanism need to be inserted in this block*/ + + } + + + pll_locked = (Xil_In32(0xFD080030) & 0x80000000) + >> 31;/*PGSR0*/ + pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000) + >> 16;/*DX0GSR0*/ + pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000) + >> 16;/*DX2GSR0*/ + pll_locked &= (Xil_In32(0xFD080BE0) & 0x10000) + >> 16;/*DX4GSR0*/ + pll_locked &= (Xil_In32(0xFD080DE0) & 0x10000) + >> 16;/*DX6GSR0*/ + pll_retry--; + } + Xil_Out32(0xFD0800C0, Xil_In32(0xFD0800C0) | + (pll_retry << 16));/*GPR0*/ + Xil_Out32(0xFD080004U, 0x00040063U); + /* PHY BRINGUP SEQ */ + while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU) { + /*****TODO*****/ + + /*TIMEOUT poll mechanism need to be inserted in this block*/ + + } + + prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U); + /* poll for PHY initialization to complete */ + while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU) { + /*****TODO*****/ + + /*TIMEOUT poll mechanism need to be inserted in this block*/ + + } - unsigned int regval = 0; - int dpll_divisor; - dpll_divisor = (Xil_In32(0xFD1A0080U) & 0x00003F00U) >> 0x00000008U; - prog_reg (0xFD1A0080U, 0x00003F00U, 0x00000008U, 0x00000005U); - prog_reg (0xFD080028U, 0x00000001U, 0x00000000U, 0x00000001U); - Xil_Out32(0xFD080004U, 0x00040003U); - while ((Xil_In32(0xFD080030U) & 0x00000001U) != 0x00000001U); - prog_reg (0xFD080684U, 0x06000000U, 0x00000019U, 0x00000001U); - prog_reg (0xFD0806A4U, 0x06000000U, 0x00000019U, 0x00000001U); - prog_reg (0xFD0806C4U, 0x06000000U, 0x00000019U, 0x00000001U); - prog_reg (0xFD0806E4U, 0x06000000U, 0x00000019U, 0x00000001U); - prog_reg (0xFD1A0080, 0x3F00, 0x8, dpll_divisor); - Xil_Out32(0xFD080004U, 0x40040071U); - while ((Xil_In32(0xFD080030U) & 0x00000001U) != 0x00000001U); - Xil_Out32(0xFD080004U, 0x40040001U); - while ((Xil_In32(0xFD080030U) & 0x00000001U) != 0x00000001U); - // PHY BRINGUP SEQ - while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU); - prog_reg (0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U); - //poll for PHY initialization to complete - while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU); - Xil_Out32(0xFD0701B0U, 0x00000001U); Xil_Out32(0xFD070320U, 0x00000001U); - while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U); - prog_reg (0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U); - Xil_Out32(0xFD080004, 0x0004FE01); //PUB_PIR - regval = Xil_In32(0xFD080030); //PUB_PGSR0 - while(regval != 0x80000FFF){ - regval = Xil_In32(0xFD080030); //PUB_PGSR0 - } + while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U) { + /*****TODO*****/ - - // Run Vref training in static read mode + /*TIMEOUT poll mechanism need to be inserted in this block*/ + + } + + prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U); + Xil_Out32(0xFD080004, 0x0004FE01); /*PUB_PIR*/ + regval = Xil_In32(0xFD080030); /*PUB_PGSR0*/ + while (regval != 0x80000FFF) + regval = Xil_In32(0xFD080030); /*PUB_PGSR0*/ + +/* Run Vref training in static read mode*/ Xil_Out32(0xFD080200U, 0x100091C7U); - Xil_Out32(0xFD080018U, 0x00F01EF2U); - Xil_Out32(0xFD08001CU, 0x55AA5498U); - Xil_Out32(0xFD08142CU, 0x00041830U); - Xil_Out32(0xFD08146CU, 0x00041830U); - Xil_Out32(0xFD0814ACU, 0x00041830U); - Xil_Out32(0xFD0814ECU, 0x00041830U); - Xil_Out32(0xFD08152CU, 0x00041830U); - + Xil_Out32(0xFD080018U, 0x00F01EEFU); + prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U); + prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U); - Xil_Out32(0xFD080004, 0x00060001); //PUB_PIR - regval = Xil_In32(0xFD080030); //PUB_PGSR0 - while((regval & 0x80004001) != 0x80004001){ - regval = Xil_In32(0xFD080030); //PUB_PGSR0 - } - // Vref training is complete, disabling static read mode + Xil_Out32(0xFD080004, 0x00060001); /*PUB_PIR*/ + regval = Xil_In32(0xFD080030); /*PUB_PGSR0*/ + while ((regval & 0x80004001) != 0x80004001) { + /*PUB_PGSR0*/ + regval = Xil_In32(0xFD080030); + } + + prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U); + prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U); +/*Vref training is complete, disabling static read mode*/ Xil_Out32(0xFD080200U, 0x800091C7U); - Xil_Out32(0xFD080018U, 0x00F12302U); - Xil_Out32(0xFD08001CU, 0x55AA5480U); - Xil_Out32(0xFD08142CU, 0x00041800U); - Xil_Out32(0xFD08146CU, 0x00041800U); - Xil_Out32(0xFD0814ACU, 0x00041800U); - Xil_Out32(0xFD0814ECU, 0x00041800U); - Xil_Out32(0xFD08152CU, 0x00041800U); - + Xil_Out32(0xFD080018U, 0x00F122E7U); - Xil_Out32(0xFD080004, 0x0000C001); //PUB_PIR - regval = Xil_In32(0xFD080030); //PUB_PGSR0 - while((regval & 0x80000C01) != 0x80000C01){ - regval = Xil_In32(0xFD080030); //PUB_PGSR0 - } + + Xil_Out32(0xFD080004, 0x0000C001); /*PUB_PIR*/ + regval = Xil_In32(0xFD080030); /*PUB_PGSR0*/ + while ((regval & 0x80000C01) != 0x80000C01) { + /*PUB_PGSR0*/ + regval = Xil_In32(0xFD080030); + } Xil_Out32(0xFD070180U, 0x01000040U); Xil_Out32(0xFD070060U, 0x00000000U); - prog_reg (0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U); + prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U); -return 1; +return 1; } /** * CRL_APB Base Address */ #define CRL_APB_BASEADDR 0XFF5E0000U -#define CRL_APB_RST_LPD_IOU0 ( ( CRL_APB_BASEADDR ) + 0X00000230U ) -#define CRL_APB_RST_LPD_IOU1 ( ( CRL_APB_BASEADDR ) + 0X00000234U ) -#define CRL_APB_RST_LPD_IOU2 ( ( CRL_APB_BASEADDR ) + 0X00000238U ) -#define CRL_APB_RST_LPD_TOP ( ( CRL_APB_BASEADDR ) + 0X0000023CU ) -#define CRL_APB_IOU_SWITCH_CTRL ( ( CRL_APB_BASEADDR ) + 0X0000009CU ) +#define CRL_APB_RST_LPD_IOU0 ((CRL_APB_BASEADDR) + 0X00000230U) +#define CRL_APB_RST_LPD_IOU1 ((CRL_APB_BASEADDR) + 0X00000234U) +#define CRL_APB_RST_LPD_IOU2 ((CRL_APB_BASEADDR) + 0X00000238U) +#define CRL_APB_RST_LPD_TOP ((CRL_APB_BASEADDR) + 0X0000023CU) +#define CRL_APB_IOU_SWITCH_CTRL ((CRL_APB_BASEADDR) + 0X0000009CU) /** * CRF_APB Base Address */ #define CRF_APB_BASEADDR 0XFD1A0000U -#define CRF_APB_RST_FPD_TOP ( ( CRF_APB_BASEADDR ) + 0X00000100U ) -#define CRF_APB_GPU_REF_CTRL ( ( CRF_APB_BASEADDR ) + 0X00000084U ) -#define CRF_APB_RST_DDR_SS ( ( CRF_APB_BASEADDR ) + 0X00000108U ) +#define CRF_APB_RST_FPD_TOP ((CRF_APB_BASEADDR) + 0X00000100U) +#define CRF_APB_GPU_REF_CTRL ((CRF_APB_BASEADDR) + 0X00000084U) +#define CRF_APB_RST_DDR_SS ((CRF_APB_BASEADDR) + 0X00000108U) #define PSU_MASK_POLL_TIME 1100000 +/** + * * Register: CRF_APB_DPLL_CTRL + */ +#define CRF_APB_DPLL_CTRL ((CRF_APB_BASEADDR) + 0X0000002C) -int mask_pollOnValue(u32 add , u32 mask, u32 value ) { - volatile u32 *addr = (volatile u32*)(unsigned long) add; + +#define CRF_APB_DPLL_CTRL_DIV2_SHIFT 16 +#define CRF_APB_DPLL_CTRL_DIV2_WIDTH 1 + +#define CRF_APB_DPLL_CTRL_FBDIV_SHIFT 8 +#define CRF_APB_DPLL_CTRL_FBDIV_WIDTH 7 + +#define CRF_APB_DPLL_CTRL_BYPASS_SHIFT 3 +#define CRF_APB_DPLL_CTRL_BYPASS_WIDTH 1 + +#define CRF_APB_DPLL_CTRL_RESET_SHIFT 0 +#define CRF_APB_DPLL_CTRL_RESET_WIDTH 1 + +/** + * * Register: CRF_APB_DPLL_CFG + */ +#define CRF_APB_DPLL_CFG ((CRF_APB_BASEADDR) + 0X00000030) + +#define CRF_APB_DPLL_CFG_LOCK_DLY_SHIFT 25 +#define CRF_APB_DPLL_CFG_LOCK_DLY_WIDTH 7 + +#define CRF_APB_DPLL_CFG_LOCK_CNT_SHIFT 13 +#define CRF_APB_DPLL_CFG_LOCK_CNT_WIDTH 10 + +#define CRF_APB_DPLL_CFG_LFHF_SHIFT 10 +#define CRF_APB_DPLL_CFG_LFHF_WIDTH 2 + +#define CRF_APB_DPLL_CFG_CP_SHIFT 5 +#define CRF_APB_DPLL_CFG_CP_WIDTH 4 + +#define CRF_APB_DPLL_CFG_RES_SHIFT 0 +#define CRF_APB_DPLL_CFG_RES_WIDTH 4 + +/** + * Register: CRF_APB_PLL_STATUS + */ +#define CRF_APB_PLL_STATUS ((CRF_APB_BASEADDR) + 0X00000044) + + +static int mask_pollOnValue(u32 add, u32 mask, u32 value) +{ + volatile u32 *addr = (volatile u32 *)(unsigned long) add; int i = 0; - while ((*addr & mask)!= value) { - if (i == PSU_MASK_POLL_TIME) { + + while ((*addr & mask) != value) { + if (i == PSU_MASK_POLL_TIME) return 0; - } i++; } - return 1; - //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr); + return 1; } -int mask_poll(u32 add , u32 mask) { - volatile u32 *addr = (volatile u32*)(unsigned long) add; +static int mask_poll(u32 add, u32 mask) +{ + volatile u32 *addr = (volatile u32 *)(unsigned long) add; int i = 0; + while (!(*addr & mask)) { - if (i == PSU_MASK_POLL_TIME) { + if (i == PSU_MASK_POLL_TIME) return 0; - } i++; } - return 1; - //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr); + return 1; } -void mask_delay(u32 delay) { - usleep (delay); +static void mask_delay(u32 delay) +{ + usleep(delay); } -u32 mask_read(u32 add , u32 mask ) { - volatile u32 *addr = (volatile u32*)(unsigned long) add; - u32 val = (*addr & mask); - //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val); - return val; +static u32 mask_read(u32 add, u32 mask) +{ + volatile u32 *addr = (volatile u32 *)(unsigned long) add; + u32 val = (*addr & mask); + return val; } +static void dpll_prog(int ddr_pll_fbdiv, int d_lock_dly, int d_lock_cnt, + int d_lfhf, int d_cp, int d_res) { -//Following SERDES programming sequences that a user need to follow to work around the known limitation with SERDES. -//These sequences should done before STEP 1 and STEP 2 as described in previous section. These programming steps are -//required for current silicon version and are likely to undergo further changes with subsequent silicon versions. + unsigned int pll_ctrl_regval; + unsigned int pll_status_regval; + + pll_ctrl_regval = Xil_In32(CRF_APB_DPLL_CTRL); + pll_ctrl_regval = pll_ctrl_regval & (~CRF_APB_DPLL_CTRL_DIV2_MASK); + pll_ctrl_regval = pll_ctrl_regval | (1 << CRF_APB_DPLL_CTRL_DIV2_SHIFT); + Xil_Out32(CRF_APB_DPLL_CTRL, pll_ctrl_regval); + + pll_ctrl_regval = Xil_In32(CRF_APB_DPLL_CFG); + pll_ctrl_regval = pll_ctrl_regval & (~CRF_APB_DPLL_CFG_LOCK_DLY_MASK); + pll_ctrl_regval = pll_ctrl_regval | + (d_lock_dly << CRF_APB_DPLL_CFG_LOCK_DLY_SHIFT); + Xil_Out32(CRF_APB_DPLL_CFG, pll_ctrl_regval); + + pll_ctrl_regval = Xil_In32(CRF_APB_DPLL_CFG); + pll_ctrl_regval = pll_ctrl_regval & (~CRF_APB_DPLL_CFG_LOCK_CNT_MASK); + pll_ctrl_regval = pll_ctrl_regval | + (d_lock_cnt << CRF_APB_DPLL_CFG_LOCK_CNT_SHIFT); + Xil_Out32(CRF_APB_DPLL_CFG, pll_ctrl_regval); + + pll_ctrl_regval = Xil_In32(CRF_APB_DPLL_CFG); + pll_ctrl_regval = pll_ctrl_regval & (~CRF_APB_DPLL_CFG_LFHF_MASK); + pll_ctrl_regval = pll_ctrl_regval | + (d_lfhf << CRF_APB_DPLL_CFG_LFHF_SHIFT); + Xil_Out32(CRF_APB_DPLL_CFG, pll_ctrl_regval); + + pll_ctrl_regval = Xil_In32(CRF_APB_DPLL_CFG); + pll_ctrl_regval = pll_ctrl_regval & (~CRF_APB_DPLL_CFG_CP_MASK); + pll_ctrl_regval = pll_ctrl_regval | + (d_cp << CRF_APB_DPLL_CFG_CP_SHIFT); + Xil_Out32(CRF_APB_DPLL_CFG, pll_ctrl_regval); + + pll_ctrl_regval = Xil_In32(CRF_APB_DPLL_CFG); + pll_ctrl_regval = pll_ctrl_regval & (~CRF_APB_DPLL_CFG_RES_MASK); + pll_ctrl_regval = pll_ctrl_regval | + (d_res << CRF_APB_DPLL_CFG_RES_SHIFT); + Xil_Out32(CRF_APB_DPLL_CFG, pll_ctrl_regval); + + pll_ctrl_regval = Xil_In32(CRF_APB_DPLL_CTRL); + pll_ctrl_regval = pll_ctrl_regval & (~CRF_APB_DPLL_CTRL_FBDIV_MASK); + pll_ctrl_regval = pll_ctrl_regval | + (ddr_pll_fbdiv << CRF_APB_DPLL_CTRL_FBDIV_SHIFT); + Xil_Out32(CRF_APB_DPLL_CTRL, pll_ctrl_regval); + + /*Setting PLL BYPASS*/ + pll_ctrl_regval = Xil_In32(CRF_APB_DPLL_CTRL); + pll_ctrl_regval = pll_ctrl_regval & (~CRF_APB_DPLL_CTRL_BYPASS_MASK); + pll_ctrl_regval = pll_ctrl_regval | + (1 << CRF_APB_DPLL_CTRL_BYPASS_SHIFT); + Xil_Out32(CRF_APB_DPLL_CTRL, pll_ctrl_regval); + + /*Setting PLL RESET*/ + pll_ctrl_regval = Xil_In32(CRF_APB_DPLL_CTRL); + pll_ctrl_regval = pll_ctrl_regval & (~CRF_APB_DPLL_CTRL_RESET_MASK); + pll_ctrl_regval = pll_ctrl_regval | + (1 << CRF_APB_DPLL_CTRL_RESET_SHIFT); + Xil_Out32(CRF_APB_DPLL_CTRL, pll_ctrl_regval); + + /*Clearing PLL RESET*/ + pll_ctrl_regval = Xil_In32(CRF_APB_DPLL_CTRL); + pll_ctrl_regval = pll_ctrl_regval & (~CRF_APB_DPLL_CTRL_RESET_MASK); + pll_ctrl_regval = pll_ctrl_regval | + (0 << CRF_APB_DPLL_CTRL_RESET_SHIFT); + Xil_Out32(CRF_APB_DPLL_CTRL, pll_ctrl_regval); + + /*Checking PLL lock*/ + pll_status_regval = 0x00000000; + while ((pll_status_regval & CRF_APB_PLL_STATUS_DPLL_LOCK_MASK) != + CRF_APB_PLL_STATUS_DPLL_LOCK_MASK) + pll_status_regval = Xil_In32(CRF_APB_PLL_STATUS); -int serdes_fixcal_code() { + + /*Clearing PLL BYPASS*/ + pll_ctrl_regval = Xil_In32(CRF_APB_DPLL_CTRL); + pll_ctrl_regval = pll_ctrl_regval & (~CRF_APB_DPLL_CTRL_BYPASS_MASK); + pll_ctrl_regval = pll_ctrl_regval | + (0 << CRF_APB_DPLL_CTRL_BYPASS_SHIFT); + Xil_Out32(CRF_APB_DPLL_CTRL, pll_ctrl_regval); + +} + +/*Following SERDES programming sequences that a user need to follow to work + * around the known limitation with SERDES. These sequences should done + * before STEP 1 and STEP 2 as described in previous section. These + * programming steps are *required for current silicon version and are + * likely to undergo further changes with subsequent silicon versions. + */ + + +static int serdes_enb_coarse_saturation(void) +{ + /*Enable PLL Coarse Code saturation Logic*/ + Xil_Out32(0xFD402094, 0x00000010); + Xil_Out32(0xFD406094, 0x00000010); + Xil_Out32(0xFD40A094, 0x00000010); + Xil_Out32(0xFD40E094, 0x00000010); + return 1; +} + +int serdes_fixcal_code(void) +{ int MaskStatus = 1; - // L3_TM_CALIB_DIG19 - Xil_Out32(0xFD40EC4C,0x00000020); - //ICM_CFG0 - Xil_Out32(0xFD410010,0x00000001); + unsigned int rdata = 0; + + /*The valid codes are from 0x26 to 0x3C. + *There are 23 valid codes in total. + */ + /*Each element of array stands for count of occurence of valid code.*/ + unsigned int match_pmos_code[23]; + /*Each element of array stands for count of occurence of valid code.*/ + /*The valid codes are from 0xC to 0x12. + *There are 7 valid codes in total. + */ + unsigned int match_nmos_code[23]; + /*Each element of array stands for count of occurence of valid code.*/ + /*The valid codes are from 0x6 to 0xC. + * There are 7 valid codes in total. + */ + unsigned int match_ical_code[7]; + /*Each element of array stands for count of occurence of valid code.*/ + unsigned int match_rcal_code[7]; - //is calibration done, polling on L3_CALIB_DONE_STATUS - MaskStatus = mask_poll(0xFD40EF14, 0x2); - - if (MaskStatus == 0) - { - xil_printf("SERDES initialization timed out\n\r"); - } - - unsigned int tmp_0_1; - tmp_0_1 = mask_read(0xFD400B0C, 0x3F); - - unsigned int tmp_0_2 = tmp_0_1 & (0x7); - unsigned int tmp_0_3 = tmp_0_1 & (0x38); - //Configure ICM for de-asserting CMN_Resetn - Xil_Out32(0xFD410010,0x00000000); - Xil_Out32(0xFD410014,0x00000000); - - unsigned int tmp_0_2_mod = (tmp_0_2 <<1) | (0x1); - tmp_0_2_mod = (tmp_0_2_mod <<4); - - tmp_0_3 = tmp_0_3 >>3; - Xil_Out32(0xFD40EC4C,tmp_0_3); + unsigned int p_code = 0; + unsigned int n_code = 0; + unsigned int i_code = 0; + unsigned int r_code = 0; + unsigned int repeat_count = 0; + unsigned int L3_TM_CALIB_DIG20 = 0; + unsigned int L3_TM_CALIB_DIG19 = 0; + unsigned int L3_TM_CALIB_DIG18 = 0; + unsigned int L3_TM_CALIB_DIG16 = 0; + unsigned int L3_TM_CALIB_DIG15 = 0; + unsigned int L3_TM_CALIB_DIG14 = 0; - //L3_TM_CALIB_DIG18 - Xil_Out32(0xFD40EC48,tmp_0_2_mod); - return MaskStatus; + int i = 0; + rdata = Xil_In32(0XFD40289C); + rdata = rdata & ~0x03; + rdata = rdata | 0x1; + Xil_Out32(0XFD40289C, rdata); + // check supply good status before starting AFE sequencing + int count = 0; + do + { + if (count == PSU_MASK_POLL_TIME) + break; + rdata = Xil_In32(0xFD402B1C); + count++; + }while((rdata&0x0000000E) !=0x0000000E); + + for (i = 0; i < 23; i++) { + match_pmos_code[i] = 0; + match_nmos_code[i] = 0; + } + for (i = 0; i < 7; i++) { + match_ical_code[i] = 0; + match_rcal_code[i] = 0; + } + + + do { + /*Clear ICM_CFG value*/ + Xil_Out32(0xFD410010, 0x00000000); + Xil_Out32(0xFD410014, 0x00000000); + + /*Set ICM_CFG value*/ + /*This will trigger recalibration of all stages*/ + Xil_Out32(0xFD410010, 0x00000001); + Xil_Out32(0xFD410014, 0x00000000); + + /*is calibration done? polling on L3_CALIB_DONE_STATUS*/ + MaskStatus = mask_poll(0xFD40EF14, 0x2); + if (MaskStatus == 0) { + /*failure here is because of calibration done timeout*/ + xil_printf("#SERDES initialization timed out\n\r"); + return MaskStatus; + } + + p_code = mask_read(0xFD40EF18, 0xFFFFFFFF);/*PMOS code*/ + n_code = mask_read(0xFD40EF1C, 0xFFFFFFFF);/*NMOS code*/ + /*m_code = mask_read(0xFD40EF20, 0xFFFFFFFF)*/;/*MPHY code*/ + i_code = mask_read(0xFD40EF24, 0xFFFFFFFF);/*ICAL code*/ + r_code = mask_read(0xFD40EF28, 0xFFFFFFFF);/*RX code*/ + /*u_code = mask_read(0xFD40EF2C, 0xFFFFFFFF)*/;/*USB2 code*/ + + /*PMOS code in acceptable range*/ + if ((p_code >= 0x26) && (p_code <= 0x3C)) + match_pmos_code[p_code - 0x26] += 1; + + /*NMOS code in acceptable range*/ + if ((n_code >= 0x26) && (n_code <= 0x3C)) + match_nmos_code[n_code - 0x26] += 1; + + /*PMOS code in acceptable range*/ + if ((i_code >= 0xC) && (i_code <= 0x12)) + match_ical_code[i_code - 0xC] += 1; + + /*NMOS code in acceptable range*/ + if ((r_code >= 0x6) && (r_code <= 0xC)) + match_rcal_code[r_code - 0x6] += 1; + + + } while (repeat_count++ < 10); + + /*find the valid code which resulted in maximum times in 10 iterations*/ + for (i = 0; i < 23; i++) { + if (match_pmos_code[i] >= match_pmos_code[0]) { + match_pmos_code[0] = match_pmos_code[i]; + p_code = 0x26 + i; + } + if (match_nmos_code[i] >= match_nmos_code[0]) { + match_nmos_code[0] = match_nmos_code[i]; + n_code = 0x26 + i; + } + } + + for (i = 0; i < 7; i++) { + if (match_ical_code[i] >= match_ical_code[0]) { + match_ical_code[0] = match_ical_code[i]; + i_code = 0xC + i; + } + if (match_rcal_code[i] >= match_rcal_code[0]) { + match_rcal_code[0] = match_rcal_code[i]; + r_code = 0x6 + i; + } + } + /*L3_TM_CALIB_DIG20[3] PSW MSB Override*/ + /*L3_TM_CALIB_DIG20[2:0] PSW Code [4:2]*/ + L3_TM_CALIB_DIG20 = mask_read(0xFD40EC50, 0xFFFFFFF0);/*read DIG20*/ + L3_TM_CALIB_DIG20 = L3_TM_CALIB_DIG20 | 0x8 | ((p_code >> 2) & 0x7); + + + /*L3_TM_CALIB_DIG19[7:6] PSW Code [1:0]*/ + /*L3_TM_CALIB_DIG19[5] PSW Override*/ + /*L3_TM_CALIB_DIG19[2] NSW MSB Override*/ + /*L3_TM_CALIB_DIG19[1:0] NSW Code [4:3]*/ + L3_TM_CALIB_DIG19 = mask_read(0xFD40EC4C, 0xFFFFFF18);/*read DIG19*/ + L3_TM_CALIB_DIG19 = L3_TM_CALIB_DIG19 | ((p_code & 0x3) << 6) + | 0x20 | 0x4 | ((n_code >> 3) & 0x3); + + /*L3_TM_CALIB_DIG18[7:5] NSW Code [2:0]*/ + /*L3_TM_CALIB_DIG18[4] NSW Override*/ + L3_TM_CALIB_DIG18 = mask_read(0xFD40EC48, 0xFFFFFF0F);/*read DIG18*/ + L3_TM_CALIB_DIG18 = L3_TM_CALIB_DIG18 | ((n_code & 0x7) << 5) | 0x10; + + + /*L3_TM_CALIB_DIG16[2:0] RX Code [3:1]*/ + L3_TM_CALIB_DIG16 = mask_read(0xFD40EC40, 0xFFFFFFF8);/*read DIG16*/ + L3_TM_CALIB_DIG16 = L3_TM_CALIB_DIG16 | ((r_code >> 1) & 0x7); + + /*L3_TM_CALIB_DIG15[7] RX Code [0]*/ + /*L3_TM_CALIB_DIG15[6] RX CODE Override*/ + /*L3_TM_CALIB_DIG15[3] ICAL MSB Override*/ + /*L3_TM_CALIB_DIG15[2:0] ICAL Code [3:1]*/ + L3_TM_CALIB_DIG15 = mask_read(0xFD40EC3C, 0xFFFFFF30);/*read DIG15*/ + L3_TM_CALIB_DIG15 = L3_TM_CALIB_DIG15 | ((r_code & 0x1) << 7) + | 0x40 | 0x8 | ((i_code >> 1) & 0x7); + + /*L3_TM_CALIB_DIG14[7] ICAL Code [0]*/ + /*L3_TM_CALIB_DIG14[6] ICAL Override*/ + L3_TM_CALIB_DIG14 = mask_read(0xFD40EC38, 0xFFFFFF3F);/*read DIG14*/ + L3_TM_CALIB_DIG14 = L3_TM_CALIB_DIG14 | ((i_code & 0x1) << 7) | 0x40; + + /*Forces the calibration values*/ + Xil_Out32(0xFD40EC50, L3_TM_CALIB_DIG20); + Xil_Out32(0xFD40EC4C, L3_TM_CALIB_DIG19); + Xil_Out32(0xFD40EC48, L3_TM_CALIB_DIG18); + Xil_Out32(0xFD40EC40, L3_TM_CALIB_DIG16); + Xil_Out32(0xFD40EC3C, L3_TM_CALIB_DIG15); + Xil_Out32(0xFD40EC38, L3_TM_CALIB_DIG14); + return MaskStatus; } - -int serdes_enb_coarse_saturation() { - //Enable PLL Coarse Code saturation Logic - Xil_Out32(0xFD402094,0x00000010); - Xil_Out32(0xFD406094,0x00000010); - Xil_Out32(0xFD40A094,0x00000010); - Xil_Out32(0xFD40E094,0x00000010); - return 1; -} - -int init_serdes() { +static int init_serdes(void) +{ int status = 1; + status &= psu_resetin_init_data(); status &= serdes_fixcal_code(); status &= serdes_enb_coarse_saturation(); - status &= psu_serdes_init_data(); + status &= psu_serdes_init_data(); status &= psu_resetout_init_data(); return status; } - - - - -void init_peripheral() +static void init_peripheral(void) { - unsigned int RegValue; - - /* Turn on IOU Clock */ - //Xil_Out32( CRL_APB_IOU_SWITCH_CTRL, 0x01001500); - - /* Release all resets in the IOU */ - Xil_Out32( CRL_APB_RST_LPD_IOU0, 0x00000000); - Xil_Out32( CRL_APB_RST_LPD_IOU1, 0x00000000); - Xil_Out32( CRL_APB_RST_LPD_IOU2, 0x00000000); - - /* Activate GPU clocks */ - //Xil_Out32(CRF_APB_GPU_REF_CTRL, 0x07001500); - - /* Take LPD out of reset except R5 */ - RegValue = Xil_In32(CRL_APB_RST_LPD_TOP); - RegValue &= 0x7; - Xil_Out32( CRL_APB_RST_LPD_TOP, RegValue); - - /* Take most of FPD out of reset */ - Xil_Out32( CRF_APB_RST_FPD_TOP, 0x00000000); - - /* Making DPDMA as secure */ - unsigned int tmp_regval; - tmp_regval = Xil_In32(0xFD690040); - tmp_regval &= ~0x00000001; - Xil_Out32(0xFD690040, tmp_regval); - - /* Making PCIe as secure */ - tmp_regval = Xil_In32(0xFD690030); - tmp_regval &= ~0x00000001; - Xil_Out32(0xFD690030, tmp_regval); +/*SMMU_REG Interrrupt Enable: Followig register need to be written all the time to properly catch SMMU messages.*/ + PSU_Mask_Write(0xFD5F0018, 0x8000001FU, 0x8000001FU); } -int psu_init_xppu_aper_ram() { - unsigned long APER_OFFSET = 0xFF981000; - int i = 0; - for (; i <= 400; i++) { - PSU_Mask_Write (APER_OFFSET ,0xF80FFFFFU ,0x08080000U); - APER_OFFSET = APER_OFFSET + 0x4; - } +static int psu_init_xppu_aper_ram(void) +{ return 0; } -int psu_lpd_protection() { - psu_init_xppu_aper_ram(); - psu_lpd_xppu_data(); - return 0; +int psu_lpd_protection(void) +{ + psu_init_xppu_aper_ram(); + return 0; } -int psu_ddr_protection() { - psu_ddr_xmpu0_data(); - psu_ddr_xmpu1_data(); - psu_ddr_xmpu2_data(); - psu_ddr_xmpu3_data(); - psu_ddr_xmpu4_data(); - psu_ddr_xmpu5_data(); - return 0; +int psu_ddr_protection(void) +{ + psu_ddr_xmpu0_data(); + psu_ddr_xmpu1_data(); + psu_ddr_xmpu2_data(); + psu_ddr_xmpu3_data(); + psu_ddr_xmpu4_data(); + psu_ddr_xmpu5_data(); + return 0; } -int psu_ocm_protection() { - psu_ocm_xmpu_data(); - return 0; +int psu_ocm_protection(void) +{ + psu_ocm_xmpu_data(); + return 0; } -int psu_fpd_protection() { - psu_fpd_xmpu_data(); - return 0; +int psu_fpd_protection(void) +{ + psu_fpd_xmpu_data(); + return 0; } -int psu_protection_lock() { - psu_protection_lock_data(); - return 0; +int psu_protection_lock(void) +{ + psu_protection_lock_data(); + return 0; } -int psu_protection() { - psu_ddr_protection(); - psu_ocm_protection(); - psu_fpd_protection(); - psu_lpd_protection(); - return 0; +int psu_protection(void) +{ + psu_apply_master_tz(); + psu_ddr_protection(); + psu_ocm_protection(); + psu_fpd_protection(); + psu_lpd_protection(); + return 0; } - - int -psu_init() +psu_init(void) { - int status = 1; - status &= psu_mio_init_data (); - status &= psu_pll_init_data (); - status &= psu_clock_init_data (); - - status &= psu_ddr_init_data (); - status &= psu_ddr_phybringup_data (); - status &= psu_peripherals_init_data (); + int status = 1; + status &= psu_mio_init_data(); + status &= psu_pll_init_data(); + status &= psu_clock_init_data(); + status &= psu_ddr_init_data(); + status &= psu_ddr_phybringup_data(); + status &= psu_peripherals_init_data(); status &= init_serdes(); - init_peripheral (); + init_peripheral(); - status &= psu_peripherals_powerdwn_data (); - - if (status == 0) { + status &= psu_peripherals_powerdwn_data(); + status &= psu_afi_config(); + psu_ddr_qos_init_data(); + + if (status == 0) return 1; - } return 0; } diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init.h index e9741eb2f..591552936 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init.h @@ -34,7 +34,7 @@ * * @file psu_init.h * -* This file is automatically generated +* This file is automatically generated * *****************************************************************************/ @@ -53,8 +53,6 @@ #define CRL_APB_RPLL_CTRL_OFFSET 0XFF5E0030 #undef CRL_APB_RPLL_TO_FPD_CTRL_OFFSET #define CRL_APB_RPLL_TO_FPD_CTRL_OFFSET 0XFF5E0048 -#undef CRL_APB_RPLL_FRAC_CFG_OFFSET -#define CRL_APB_RPLL_FRAC_CFG_OFFSET 0XFF5E0038 #undef CRL_APB_IOPLL_CFG_OFFSET #define CRL_APB_IOPLL_CFG_OFFSET 0XFF5E0024 #undef CRL_APB_IOPLL_CTRL_OFFSET @@ -69,8 +67,6 @@ #define CRL_APB_IOPLL_CTRL_OFFSET 0XFF5E0020 #undef CRL_APB_IOPLL_TO_FPD_CTRL_OFFSET #define CRL_APB_IOPLL_TO_FPD_CTRL_OFFSET 0XFF5E0044 -#undef CRL_APB_IOPLL_FRAC_CFG_OFFSET -#define CRL_APB_IOPLL_FRAC_CFG_OFFSET 0XFF5E0028 #undef CRF_APB_APLL_CFG_OFFSET #define CRF_APB_APLL_CFG_OFFSET 0XFD1A0024 #undef CRF_APB_APLL_CTRL_OFFSET @@ -85,8 +81,6 @@ #define CRF_APB_APLL_CTRL_OFFSET 0XFD1A0020 #undef CRF_APB_APLL_TO_LPD_CTRL_OFFSET #define CRF_APB_APLL_TO_LPD_CTRL_OFFSET 0XFD1A0048 -#undef CRF_APB_APLL_FRAC_CFG_OFFSET -#define CRF_APB_APLL_FRAC_CFG_OFFSET 0XFD1A0028 #undef CRF_APB_DPLL_CFG_OFFSET #define CRF_APB_DPLL_CFG_OFFSET 0XFD1A0030 #undef CRF_APB_DPLL_CTRL_OFFSET @@ -101,8 +95,6 @@ #define CRF_APB_DPLL_CTRL_OFFSET 0XFD1A002C #undef CRF_APB_DPLL_TO_LPD_CTRL_OFFSET #define CRF_APB_DPLL_TO_LPD_CTRL_OFFSET 0XFD1A004C -#undef CRF_APB_DPLL_FRAC_CFG_OFFSET -#define CRF_APB_DPLL_FRAC_CFG_OFFSET 0XFD1A0034 #undef CRF_APB_VPLL_CFG_OFFSET #define CRF_APB_VPLL_CFG_OFFSET 0XFD1A003C #undef CRF_APB_VPLL_CTRL_OFFSET @@ -117,675 +109,770 @@ #define CRF_APB_VPLL_CTRL_OFFSET 0XFD1A0038 #undef CRF_APB_VPLL_TO_LPD_CTRL_OFFSET #define CRF_APB_VPLL_TO_LPD_CTRL_OFFSET 0XFD1A0050 -#undef CRF_APB_VPLL_FRAC_CFG_OFFSET -#define CRF_APB_VPLL_FRAC_CFG_OFFSET 0XFD1A0040 -/*PLL loop filter resistor control*/ +/* +* PLL loop filter resistor control +*/ #undef CRL_APB_RPLL_CFG_RES_DEFVAL #undef CRL_APB_RPLL_CFG_RES_SHIFT #undef CRL_APB_RPLL_CFG_RES_MASK -#define CRL_APB_RPLL_CFG_RES_DEFVAL 0x00000000 -#define CRL_APB_RPLL_CFG_RES_SHIFT 0 -#define CRL_APB_RPLL_CFG_RES_MASK 0x0000000FU +#define CRL_APB_RPLL_CFG_RES_DEFVAL 0x00000000 +#define CRL_APB_RPLL_CFG_RES_SHIFT 0 +#define CRL_APB_RPLL_CFG_RES_MASK 0x0000000FU -/*PLL charge pump control*/ +/* +* PLL charge pump control +*/ #undef CRL_APB_RPLL_CFG_CP_DEFVAL #undef CRL_APB_RPLL_CFG_CP_SHIFT #undef CRL_APB_RPLL_CFG_CP_MASK -#define CRL_APB_RPLL_CFG_CP_DEFVAL 0x00000000 -#define CRL_APB_RPLL_CFG_CP_SHIFT 5 -#define CRL_APB_RPLL_CFG_CP_MASK 0x000001E0U +#define CRL_APB_RPLL_CFG_CP_DEFVAL 0x00000000 +#define CRL_APB_RPLL_CFG_CP_SHIFT 5 +#define CRL_APB_RPLL_CFG_CP_MASK 0x000001E0U -/*PLL loop filter high frequency capacitor control*/ +/* +* PLL loop filter high frequency capacitor control +*/ #undef CRL_APB_RPLL_CFG_LFHF_DEFVAL #undef CRL_APB_RPLL_CFG_LFHF_SHIFT #undef CRL_APB_RPLL_CFG_LFHF_MASK -#define CRL_APB_RPLL_CFG_LFHF_DEFVAL 0x00000000 -#define CRL_APB_RPLL_CFG_LFHF_SHIFT 10 -#define CRL_APB_RPLL_CFG_LFHF_MASK 0x00000C00U +#define CRL_APB_RPLL_CFG_LFHF_DEFVAL 0x00000000 +#define CRL_APB_RPLL_CFG_LFHF_SHIFT 10 +#define CRL_APB_RPLL_CFG_LFHF_MASK 0x00000C00U -/*Lock circuit counter setting*/ +/* +* Lock circuit counter setting +*/ #undef CRL_APB_RPLL_CFG_LOCK_CNT_DEFVAL #undef CRL_APB_RPLL_CFG_LOCK_CNT_SHIFT #undef CRL_APB_RPLL_CFG_LOCK_CNT_MASK -#define CRL_APB_RPLL_CFG_LOCK_CNT_DEFVAL 0x00000000 -#define CRL_APB_RPLL_CFG_LOCK_CNT_SHIFT 13 -#define CRL_APB_RPLL_CFG_LOCK_CNT_MASK 0x007FE000U +#define CRL_APB_RPLL_CFG_LOCK_CNT_DEFVAL 0x00000000 +#define CRL_APB_RPLL_CFG_LOCK_CNT_SHIFT 13 +#define CRL_APB_RPLL_CFG_LOCK_CNT_MASK 0x007FE000U -/*Lock circuit configuration settings for lock windowsize*/ +/* +* Lock circuit configuration settings for lock windowsize +*/ #undef CRL_APB_RPLL_CFG_LOCK_DLY_DEFVAL #undef CRL_APB_RPLL_CFG_LOCK_DLY_SHIFT #undef CRL_APB_RPLL_CFG_LOCK_DLY_MASK -#define CRL_APB_RPLL_CFG_LOCK_DLY_DEFVAL 0x00000000 -#define CRL_APB_RPLL_CFG_LOCK_DLY_SHIFT 25 -#define CRL_APB_RPLL_CFG_LOCK_DLY_MASK 0xFE000000U +#define CRL_APB_RPLL_CFG_LOCK_DLY_DEFVAL 0x00000000 +#define CRL_APB_RPLL_CFG_LOCK_DLY_SHIFT 25 +#define CRL_APB_RPLL_CFG_LOCK_DLY_MASK 0xFE000000U -/*Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_ - ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source*/ +/* +* Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i + * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour + * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source +*/ #undef CRL_APB_RPLL_CTRL_PRE_SRC_DEFVAL #undef CRL_APB_RPLL_CTRL_PRE_SRC_SHIFT #undef CRL_APB_RPLL_CTRL_PRE_SRC_MASK -#define CRL_APB_RPLL_CTRL_PRE_SRC_DEFVAL 0x00012C09 -#define CRL_APB_RPLL_CTRL_PRE_SRC_SHIFT 20 -#define CRL_APB_RPLL_CTRL_PRE_SRC_MASK 0x00700000U +#define CRL_APB_RPLL_CTRL_PRE_SRC_DEFVAL 0x00012C09 +#define CRL_APB_RPLL_CTRL_PRE_SRC_SHIFT 20 +#define CRL_APB_RPLL_CTRL_PRE_SRC_MASK 0x00700000U -/*The integer portion of the feedback divider to the PLL*/ +/* +* The integer portion of the feedback divider to the PLL +*/ #undef CRL_APB_RPLL_CTRL_FBDIV_DEFVAL #undef CRL_APB_RPLL_CTRL_FBDIV_SHIFT #undef CRL_APB_RPLL_CTRL_FBDIV_MASK -#define CRL_APB_RPLL_CTRL_FBDIV_DEFVAL 0x00012C09 -#define CRL_APB_RPLL_CTRL_FBDIV_SHIFT 8 -#define CRL_APB_RPLL_CTRL_FBDIV_MASK 0x00007F00U +#define CRL_APB_RPLL_CTRL_FBDIV_DEFVAL 0x00012C09 +#define CRL_APB_RPLL_CTRL_FBDIV_SHIFT 8 +#define CRL_APB_RPLL_CTRL_FBDIV_MASK 0x00007F00U -/*This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency*/ +/* +* This turns on the divide by 2 that is inside of the PLL. This does not c + * hange the VCO frequency, just the output frequency +*/ #undef CRL_APB_RPLL_CTRL_DIV2_DEFVAL #undef CRL_APB_RPLL_CTRL_DIV2_SHIFT #undef CRL_APB_RPLL_CTRL_DIV2_MASK -#define CRL_APB_RPLL_CTRL_DIV2_DEFVAL 0x00012C09 -#define CRL_APB_RPLL_CTRL_DIV2_SHIFT 16 -#define CRL_APB_RPLL_CTRL_DIV2_MASK 0x00010000U +#define CRL_APB_RPLL_CTRL_DIV2_DEFVAL 0x00012C09 +#define CRL_APB_RPLL_CTRL_DIV2_SHIFT 16 +#define CRL_APB_RPLL_CTRL_DIV2_MASK 0x00010000U -/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/ +/* +* Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) +*/ #undef CRL_APB_RPLL_CTRL_BYPASS_DEFVAL #undef CRL_APB_RPLL_CTRL_BYPASS_SHIFT #undef CRL_APB_RPLL_CTRL_BYPASS_MASK -#define CRL_APB_RPLL_CTRL_BYPASS_DEFVAL 0x00012C09 -#define CRL_APB_RPLL_CTRL_BYPASS_SHIFT 3 -#define CRL_APB_RPLL_CTRL_BYPASS_MASK 0x00000008U +#define CRL_APB_RPLL_CTRL_BYPASS_DEFVAL 0x00012C09 +#define CRL_APB_RPLL_CTRL_BYPASS_SHIFT 3 +#define CRL_APB_RPLL_CTRL_BYPASS_MASK 0x00000008U -/*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/ +/* +* Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. +*/ #undef CRL_APB_RPLL_CTRL_RESET_DEFVAL #undef CRL_APB_RPLL_CTRL_RESET_SHIFT #undef CRL_APB_RPLL_CTRL_RESET_MASK -#define CRL_APB_RPLL_CTRL_RESET_DEFVAL 0x00012C09 -#define CRL_APB_RPLL_CTRL_RESET_SHIFT 0 -#define CRL_APB_RPLL_CTRL_RESET_MASK 0x00000001U +#define CRL_APB_RPLL_CTRL_RESET_DEFVAL 0x00012C09 +#define CRL_APB_RPLL_CTRL_RESET_SHIFT 0 +#define CRL_APB_RPLL_CTRL_RESET_MASK 0x00000001U -/*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/ +/* +* Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. +*/ #undef CRL_APB_RPLL_CTRL_RESET_DEFVAL #undef CRL_APB_RPLL_CTRL_RESET_SHIFT #undef CRL_APB_RPLL_CTRL_RESET_MASK -#define CRL_APB_RPLL_CTRL_RESET_DEFVAL 0x00012C09 -#define CRL_APB_RPLL_CTRL_RESET_SHIFT 0 -#define CRL_APB_RPLL_CTRL_RESET_MASK 0x00000001U +#define CRL_APB_RPLL_CTRL_RESET_DEFVAL 0x00012C09 +#define CRL_APB_RPLL_CTRL_RESET_SHIFT 0 +#define CRL_APB_RPLL_CTRL_RESET_MASK 0x00000001U -/*RPLL is locked*/ +/* +* RPLL is locked +*/ #undef CRL_APB_PLL_STATUS_RPLL_LOCK_DEFVAL #undef CRL_APB_PLL_STATUS_RPLL_LOCK_SHIFT #undef CRL_APB_PLL_STATUS_RPLL_LOCK_MASK -#define CRL_APB_PLL_STATUS_RPLL_LOCK_DEFVAL 0x00000018 -#define CRL_APB_PLL_STATUS_RPLL_LOCK_SHIFT 1 -#define CRL_APB_PLL_STATUS_RPLL_LOCK_MASK 0x00000002U +#define CRL_APB_PLL_STATUS_RPLL_LOCK_DEFVAL 0x00000018 +#define CRL_APB_PLL_STATUS_RPLL_LOCK_SHIFT 1 +#define CRL_APB_PLL_STATUS_RPLL_LOCK_MASK 0x00000002U #define CRL_APB_PLL_STATUS_OFFSET 0XFF5E0040 -/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/ +/* +* Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) +*/ #undef CRL_APB_RPLL_CTRL_BYPASS_DEFVAL #undef CRL_APB_RPLL_CTRL_BYPASS_SHIFT #undef CRL_APB_RPLL_CTRL_BYPASS_MASK -#define CRL_APB_RPLL_CTRL_BYPASS_DEFVAL 0x00012C09 -#define CRL_APB_RPLL_CTRL_BYPASS_SHIFT 3 -#define CRL_APB_RPLL_CTRL_BYPASS_MASK 0x00000008U +#define CRL_APB_RPLL_CTRL_BYPASS_DEFVAL 0x00012C09 +#define CRL_APB_RPLL_CTRL_BYPASS_SHIFT 3 +#define CRL_APB_RPLL_CTRL_BYPASS_MASK 0x00000008U -/*Divisor value for this clock.*/ +/* +* Divisor value for this clock. +*/ #undef CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL #undef CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_SHIFT #undef CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_MASK -#define CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL 0x00000400 -#define CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL 0x00000400 +#define CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_MASK 0x00003F00U -/*Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona - mode and uses DATA of this register for the fractional portion of the feedback divider.*/ -#undef CRL_APB_RPLL_FRAC_CFG_ENABLED_DEFVAL -#undef CRL_APB_RPLL_FRAC_CFG_ENABLED_SHIFT -#undef CRL_APB_RPLL_FRAC_CFG_ENABLED_MASK -#define CRL_APB_RPLL_FRAC_CFG_ENABLED_DEFVAL 0x00000000 -#define CRL_APB_RPLL_FRAC_CFG_ENABLED_SHIFT 31 -#define CRL_APB_RPLL_FRAC_CFG_ENABLED_MASK 0x80000000U - -/*Fractional value for the Feedback value.*/ -#undef CRL_APB_RPLL_FRAC_CFG_DATA_DEFVAL -#undef CRL_APB_RPLL_FRAC_CFG_DATA_SHIFT -#undef CRL_APB_RPLL_FRAC_CFG_DATA_MASK -#define CRL_APB_RPLL_FRAC_CFG_DATA_DEFVAL 0x00000000 -#define CRL_APB_RPLL_FRAC_CFG_DATA_SHIFT 0 -#define CRL_APB_RPLL_FRAC_CFG_DATA_MASK 0x0000FFFFU - -/*PLL loop filter resistor control*/ +/* +* PLL loop filter resistor control +*/ #undef CRL_APB_IOPLL_CFG_RES_DEFVAL #undef CRL_APB_IOPLL_CFG_RES_SHIFT #undef CRL_APB_IOPLL_CFG_RES_MASK -#define CRL_APB_IOPLL_CFG_RES_DEFVAL 0x00000000 -#define CRL_APB_IOPLL_CFG_RES_SHIFT 0 -#define CRL_APB_IOPLL_CFG_RES_MASK 0x0000000FU +#define CRL_APB_IOPLL_CFG_RES_DEFVAL 0x00000000 +#define CRL_APB_IOPLL_CFG_RES_SHIFT 0 +#define CRL_APB_IOPLL_CFG_RES_MASK 0x0000000FU -/*PLL charge pump control*/ +/* +* PLL charge pump control +*/ #undef CRL_APB_IOPLL_CFG_CP_DEFVAL #undef CRL_APB_IOPLL_CFG_CP_SHIFT #undef CRL_APB_IOPLL_CFG_CP_MASK -#define CRL_APB_IOPLL_CFG_CP_DEFVAL 0x00000000 -#define CRL_APB_IOPLL_CFG_CP_SHIFT 5 -#define CRL_APB_IOPLL_CFG_CP_MASK 0x000001E0U +#define CRL_APB_IOPLL_CFG_CP_DEFVAL 0x00000000 +#define CRL_APB_IOPLL_CFG_CP_SHIFT 5 +#define CRL_APB_IOPLL_CFG_CP_MASK 0x000001E0U -/*PLL loop filter high frequency capacitor control*/ +/* +* PLL loop filter high frequency capacitor control +*/ #undef CRL_APB_IOPLL_CFG_LFHF_DEFVAL #undef CRL_APB_IOPLL_CFG_LFHF_SHIFT #undef CRL_APB_IOPLL_CFG_LFHF_MASK -#define CRL_APB_IOPLL_CFG_LFHF_DEFVAL 0x00000000 -#define CRL_APB_IOPLL_CFG_LFHF_SHIFT 10 -#define CRL_APB_IOPLL_CFG_LFHF_MASK 0x00000C00U +#define CRL_APB_IOPLL_CFG_LFHF_DEFVAL 0x00000000 +#define CRL_APB_IOPLL_CFG_LFHF_SHIFT 10 +#define CRL_APB_IOPLL_CFG_LFHF_MASK 0x00000C00U -/*Lock circuit counter setting*/ +/* +* Lock circuit counter setting +*/ #undef CRL_APB_IOPLL_CFG_LOCK_CNT_DEFVAL #undef CRL_APB_IOPLL_CFG_LOCK_CNT_SHIFT #undef CRL_APB_IOPLL_CFG_LOCK_CNT_MASK -#define CRL_APB_IOPLL_CFG_LOCK_CNT_DEFVAL 0x00000000 -#define CRL_APB_IOPLL_CFG_LOCK_CNT_SHIFT 13 -#define CRL_APB_IOPLL_CFG_LOCK_CNT_MASK 0x007FE000U +#define CRL_APB_IOPLL_CFG_LOCK_CNT_DEFVAL 0x00000000 +#define CRL_APB_IOPLL_CFG_LOCK_CNT_SHIFT 13 +#define CRL_APB_IOPLL_CFG_LOCK_CNT_MASK 0x007FE000U -/*Lock circuit configuration settings for lock windowsize*/ +/* +* Lock circuit configuration settings for lock windowsize +*/ #undef CRL_APB_IOPLL_CFG_LOCK_DLY_DEFVAL #undef CRL_APB_IOPLL_CFG_LOCK_DLY_SHIFT #undef CRL_APB_IOPLL_CFG_LOCK_DLY_MASK -#define CRL_APB_IOPLL_CFG_LOCK_DLY_DEFVAL 0x00000000 -#define CRL_APB_IOPLL_CFG_LOCK_DLY_SHIFT 25 -#define CRL_APB_IOPLL_CFG_LOCK_DLY_MASK 0xFE000000U +#define CRL_APB_IOPLL_CFG_LOCK_DLY_DEFVAL 0x00000000 +#define CRL_APB_IOPLL_CFG_LOCK_DLY_SHIFT 25 +#define CRL_APB_IOPLL_CFG_LOCK_DLY_MASK 0xFE000000U -/*Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_ - ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source*/ +/* +* Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i + * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour + * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source +*/ #undef CRL_APB_IOPLL_CTRL_PRE_SRC_DEFVAL #undef CRL_APB_IOPLL_CTRL_PRE_SRC_SHIFT #undef CRL_APB_IOPLL_CTRL_PRE_SRC_MASK -#define CRL_APB_IOPLL_CTRL_PRE_SRC_DEFVAL 0x00012C09 -#define CRL_APB_IOPLL_CTRL_PRE_SRC_SHIFT 20 -#define CRL_APB_IOPLL_CTRL_PRE_SRC_MASK 0x00700000U +#define CRL_APB_IOPLL_CTRL_PRE_SRC_DEFVAL 0x00012C09 +#define CRL_APB_IOPLL_CTRL_PRE_SRC_SHIFT 20 +#define CRL_APB_IOPLL_CTRL_PRE_SRC_MASK 0x00700000U -/*The integer portion of the feedback divider to the PLL*/ +/* +* The integer portion of the feedback divider to the PLL +*/ #undef CRL_APB_IOPLL_CTRL_FBDIV_DEFVAL #undef CRL_APB_IOPLL_CTRL_FBDIV_SHIFT #undef CRL_APB_IOPLL_CTRL_FBDIV_MASK -#define CRL_APB_IOPLL_CTRL_FBDIV_DEFVAL 0x00012C09 -#define CRL_APB_IOPLL_CTRL_FBDIV_SHIFT 8 -#define CRL_APB_IOPLL_CTRL_FBDIV_MASK 0x00007F00U +#define CRL_APB_IOPLL_CTRL_FBDIV_DEFVAL 0x00012C09 +#define CRL_APB_IOPLL_CTRL_FBDIV_SHIFT 8 +#define CRL_APB_IOPLL_CTRL_FBDIV_MASK 0x00007F00U -/*This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency*/ +/* +* This turns on the divide by 2 that is inside of the PLL. This does not c + * hange the VCO frequency, just the output frequency +*/ #undef CRL_APB_IOPLL_CTRL_DIV2_DEFVAL #undef CRL_APB_IOPLL_CTRL_DIV2_SHIFT #undef CRL_APB_IOPLL_CTRL_DIV2_MASK -#define CRL_APB_IOPLL_CTRL_DIV2_DEFVAL 0x00012C09 -#define CRL_APB_IOPLL_CTRL_DIV2_SHIFT 16 -#define CRL_APB_IOPLL_CTRL_DIV2_MASK 0x00010000U +#define CRL_APB_IOPLL_CTRL_DIV2_DEFVAL 0x00012C09 +#define CRL_APB_IOPLL_CTRL_DIV2_SHIFT 16 +#define CRL_APB_IOPLL_CTRL_DIV2_MASK 0x00010000U -/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/ +/* +* Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) +*/ #undef CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL #undef CRL_APB_IOPLL_CTRL_BYPASS_SHIFT #undef CRL_APB_IOPLL_CTRL_BYPASS_MASK -#define CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL 0x00012C09 -#define CRL_APB_IOPLL_CTRL_BYPASS_SHIFT 3 -#define CRL_APB_IOPLL_CTRL_BYPASS_MASK 0x00000008U +#define CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL 0x00012C09 +#define CRL_APB_IOPLL_CTRL_BYPASS_SHIFT 3 +#define CRL_APB_IOPLL_CTRL_BYPASS_MASK 0x00000008U -/*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/ +/* +* Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. +*/ #undef CRL_APB_IOPLL_CTRL_RESET_DEFVAL #undef CRL_APB_IOPLL_CTRL_RESET_SHIFT #undef CRL_APB_IOPLL_CTRL_RESET_MASK -#define CRL_APB_IOPLL_CTRL_RESET_DEFVAL 0x00012C09 -#define CRL_APB_IOPLL_CTRL_RESET_SHIFT 0 -#define CRL_APB_IOPLL_CTRL_RESET_MASK 0x00000001U +#define CRL_APB_IOPLL_CTRL_RESET_DEFVAL 0x00012C09 +#define CRL_APB_IOPLL_CTRL_RESET_SHIFT 0 +#define CRL_APB_IOPLL_CTRL_RESET_MASK 0x00000001U -/*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/ +/* +* Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. +*/ #undef CRL_APB_IOPLL_CTRL_RESET_DEFVAL #undef CRL_APB_IOPLL_CTRL_RESET_SHIFT #undef CRL_APB_IOPLL_CTRL_RESET_MASK -#define CRL_APB_IOPLL_CTRL_RESET_DEFVAL 0x00012C09 -#define CRL_APB_IOPLL_CTRL_RESET_SHIFT 0 -#define CRL_APB_IOPLL_CTRL_RESET_MASK 0x00000001U +#define CRL_APB_IOPLL_CTRL_RESET_DEFVAL 0x00012C09 +#define CRL_APB_IOPLL_CTRL_RESET_SHIFT 0 +#define CRL_APB_IOPLL_CTRL_RESET_MASK 0x00000001U -/*IOPLL is locked*/ +/* +* IOPLL is locked +*/ #undef CRL_APB_PLL_STATUS_IOPLL_LOCK_DEFVAL #undef CRL_APB_PLL_STATUS_IOPLL_LOCK_SHIFT #undef CRL_APB_PLL_STATUS_IOPLL_LOCK_MASK -#define CRL_APB_PLL_STATUS_IOPLL_LOCK_DEFVAL 0x00000018 -#define CRL_APB_PLL_STATUS_IOPLL_LOCK_SHIFT 0 -#define CRL_APB_PLL_STATUS_IOPLL_LOCK_MASK 0x00000001U +#define CRL_APB_PLL_STATUS_IOPLL_LOCK_DEFVAL 0x00000018 +#define CRL_APB_PLL_STATUS_IOPLL_LOCK_SHIFT 0 +#define CRL_APB_PLL_STATUS_IOPLL_LOCK_MASK 0x00000001U #define CRL_APB_PLL_STATUS_OFFSET 0XFF5E0040 -/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/ +/* +* Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) +*/ #undef CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL #undef CRL_APB_IOPLL_CTRL_BYPASS_SHIFT #undef CRL_APB_IOPLL_CTRL_BYPASS_MASK -#define CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL 0x00012C09 -#define CRL_APB_IOPLL_CTRL_BYPASS_SHIFT 3 -#define CRL_APB_IOPLL_CTRL_BYPASS_MASK 0x00000008U +#define CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL 0x00012C09 +#define CRL_APB_IOPLL_CTRL_BYPASS_SHIFT 3 +#define CRL_APB_IOPLL_CTRL_BYPASS_MASK 0x00000008U -/*Divisor value for this clock.*/ +/* +* Divisor value for this clock. +*/ #undef CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL #undef CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_SHIFT #undef CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_MASK -#define CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL 0x00000400 -#define CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL 0x00000400 +#define CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_MASK 0x00003F00U -/*Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona - mode and uses DATA of this register for the fractional portion of the feedback divider.*/ -#undef CRL_APB_IOPLL_FRAC_CFG_ENABLED_DEFVAL -#undef CRL_APB_IOPLL_FRAC_CFG_ENABLED_SHIFT -#undef CRL_APB_IOPLL_FRAC_CFG_ENABLED_MASK -#define CRL_APB_IOPLL_FRAC_CFG_ENABLED_DEFVAL 0x00000000 -#define CRL_APB_IOPLL_FRAC_CFG_ENABLED_SHIFT 31 -#define CRL_APB_IOPLL_FRAC_CFG_ENABLED_MASK 0x80000000U - -/*Fractional value for the Feedback value.*/ -#undef CRL_APB_IOPLL_FRAC_CFG_DATA_DEFVAL -#undef CRL_APB_IOPLL_FRAC_CFG_DATA_SHIFT -#undef CRL_APB_IOPLL_FRAC_CFG_DATA_MASK -#define CRL_APB_IOPLL_FRAC_CFG_DATA_DEFVAL 0x00000000 -#define CRL_APB_IOPLL_FRAC_CFG_DATA_SHIFT 0 -#define CRL_APB_IOPLL_FRAC_CFG_DATA_MASK 0x0000FFFFU - -/*PLL loop filter resistor control*/ +/* +* PLL loop filter resistor control +*/ #undef CRF_APB_APLL_CFG_RES_DEFVAL #undef CRF_APB_APLL_CFG_RES_SHIFT #undef CRF_APB_APLL_CFG_RES_MASK -#define CRF_APB_APLL_CFG_RES_DEFVAL 0x00000000 -#define CRF_APB_APLL_CFG_RES_SHIFT 0 -#define CRF_APB_APLL_CFG_RES_MASK 0x0000000FU +#define CRF_APB_APLL_CFG_RES_DEFVAL 0x00000000 +#define CRF_APB_APLL_CFG_RES_SHIFT 0 +#define CRF_APB_APLL_CFG_RES_MASK 0x0000000FU -/*PLL charge pump control*/ +/* +* PLL charge pump control +*/ #undef CRF_APB_APLL_CFG_CP_DEFVAL #undef CRF_APB_APLL_CFG_CP_SHIFT #undef CRF_APB_APLL_CFG_CP_MASK -#define CRF_APB_APLL_CFG_CP_DEFVAL 0x00000000 -#define CRF_APB_APLL_CFG_CP_SHIFT 5 -#define CRF_APB_APLL_CFG_CP_MASK 0x000001E0U +#define CRF_APB_APLL_CFG_CP_DEFVAL 0x00000000 +#define CRF_APB_APLL_CFG_CP_SHIFT 5 +#define CRF_APB_APLL_CFG_CP_MASK 0x000001E0U -/*PLL loop filter high frequency capacitor control*/ +/* +* PLL loop filter high frequency capacitor control +*/ #undef CRF_APB_APLL_CFG_LFHF_DEFVAL #undef CRF_APB_APLL_CFG_LFHF_SHIFT #undef CRF_APB_APLL_CFG_LFHF_MASK -#define CRF_APB_APLL_CFG_LFHF_DEFVAL 0x00000000 -#define CRF_APB_APLL_CFG_LFHF_SHIFT 10 -#define CRF_APB_APLL_CFG_LFHF_MASK 0x00000C00U +#define CRF_APB_APLL_CFG_LFHF_DEFVAL 0x00000000 +#define CRF_APB_APLL_CFG_LFHF_SHIFT 10 +#define CRF_APB_APLL_CFG_LFHF_MASK 0x00000C00U -/*Lock circuit counter setting*/ +/* +* Lock circuit counter setting +*/ #undef CRF_APB_APLL_CFG_LOCK_CNT_DEFVAL #undef CRF_APB_APLL_CFG_LOCK_CNT_SHIFT #undef CRF_APB_APLL_CFG_LOCK_CNT_MASK -#define CRF_APB_APLL_CFG_LOCK_CNT_DEFVAL 0x00000000 -#define CRF_APB_APLL_CFG_LOCK_CNT_SHIFT 13 -#define CRF_APB_APLL_CFG_LOCK_CNT_MASK 0x007FE000U +#define CRF_APB_APLL_CFG_LOCK_CNT_DEFVAL 0x00000000 +#define CRF_APB_APLL_CFG_LOCK_CNT_SHIFT 13 +#define CRF_APB_APLL_CFG_LOCK_CNT_MASK 0x007FE000U -/*Lock circuit configuration settings for lock windowsize*/ +/* +* Lock circuit configuration settings for lock windowsize +*/ #undef CRF_APB_APLL_CFG_LOCK_DLY_DEFVAL #undef CRF_APB_APLL_CFG_LOCK_DLY_SHIFT #undef CRF_APB_APLL_CFG_LOCK_DLY_MASK -#define CRF_APB_APLL_CFG_LOCK_DLY_DEFVAL 0x00000000 -#define CRF_APB_APLL_CFG_LOCK_DLY_SHIFT 25 -#define CRF_APB_APLL_CFG_LOCK_DLY_MASK 0xFE000000U +#define CRF_APB_APLL_CFG_LOCK_DLY_DEFVAL 0x00000000 +#define CRF_APB_APLL_CFG_LOCK_DLY_SHIFT 25 +#define CRF_APB_APLL_CFG_LOCK_DLY_MASK 0xFE000000U -/*Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_ - ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source*/ +/* +* Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i + * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour + * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source +*/ #undef CRF_APB_APLL_CTRL_PRE_SRC_DEFVAL #undef CRF_APB_APLL_CTRL_PRE_SRC_SHIFT #undef CRF_APB_APLL_CTRL_PRE_SRC_MASK -#define CRF_APB_APLL_CTRL_PRE_SRC_DEFVAL 0x00012C09 -#define CRF_APB_APLL_CTRL_PRE_SRC_SHIFT 20 -#define CRF_APB_APLL_CTRL_PRE_SRC_MASK 0x00700000U +#define CRF_APB_APLL_CTRL_PRE_SRC_DEFVAL 0x00012C09 +#define CRF_APB_APLL_CTRL_PRE_SRC_SHIFT 20 +#define CRF_APB_APLL_CTRL_PRE_SRC_MASK 0x00700000U -/*The integer portion of the feedback divider to the PLL*/ +/* +* The integer portion of the feedback divider to the PLL +*/ #undef CRF_APB_APLL_CTRL_FBDIV_DEFVAL #undef CRF_APB_APLL_CTRL_FBDIV_SHIFT #undef CRF_APB_APLL_CTRL_FBDIV_MASK -#define CRF_APB_APLL_CTRL_FBDIV_DEFVAL 0x00012C09 -#define CRF_APB_APLL_CTRL_FBDIV_SHIFT 8 -#define CRF_APB_APLL_CTRL_FBDIV_MASK 0x00007F00U +#define CRF_APB_APLL_CTRL_FBDIV_DEFVAL 0x00012C09 +#define CRF_APB_APLL_CTRL_FBDIV_SHIFT 8 +#define CRF_APB_APLL_CTRL_FBDIV_MASK 0x00007F00U -/*This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency*/ +/* +* This turns on the divide by 2 that is inside of the PLL. This does not c + * hange the VCO frequency, just the output frequency +*/ #undef CRF_APB_APLL_CTRL_DIV2_DEFVAL #undef CRF_APB_APLL_CTRL_DIV2_SHIFT #undef CRF_APB_APLL_CTRL_DIV2_MASK -#define CRF_APB_APLL_CTRL_DIV2_DEFVAL 0x00012C09 -#define CRF_APB_APLL_CTRL_DIV2_SHIFT 16 -#define CRF_APB_APLL_CTRL_DIV2_MASK 0x00010000U +#define CRF_APB_APLL_CTRL_DIV2_DEFVAL 0x00012C09 +#define CRF_APB_APLL_CTRL_DIV2_SHIFT 16 +#define CRF_APB_APLL_CTRL_DIV2_MASK 0x00010000U -/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/ +/* +* Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) +*/ #undef CRF_APB_APLL_CTRL_BYPASS_DEFVAL #undef CRF_APB_APLL_CTRL_BYPASS_SHIFT #undef CRF_APB_APLL_CTRL_BYPASS_MASK -#define CRF_APB_APLL_CTRL_BYPASS_DEFVAL 0x00012C09 -#define CRF_APB_APLL_CTRL_BYPASS_SHIFT 3 -#define CRF_APB_APLL_CTRL_BYPASS_MASK 0x00000008U +#define CRF_APB_APLL_CTRL_BYPASS_DEFVAL 0x00012C09 +#define CRF_APB_APLL_CTRL_BYPASS_SHIFT 3 +#define CRF_APB_APLL_CTRL_BYPASS_MASK 0x00000008U -/*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/ +/* +* Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. +*/ #undef CRF_APB_APLL_CTRL_RESET_DEFVAL #undef CRF_APB_APLL_CTRL_RESET_SHIFT #undef CRF_APB_APLL_CTRL_RESET_MASK -#define CRF_APB_APLL_CTRL_RESET_DEFVAL 0x00012C09 -#define CRF_APB_APLL_CTRL_RESET_SHIFT 0 -#define CRF_APB_APLL_CTRL_RESET_MASK 0x00000001U +#define CRF_APB_APLL_CTRL_RESET_DEFVAL 0x00012C09 +#define CRF_APB_APLL_CTRL_RESET_SHIFT 0 +#define CRF_APB_APLL_CTRL_RESET_MASK 0x00000001U -/*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/ +/* +* Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. +*/ #undef CRF_APB_APLL_CTRL_RESET_DEFVAL #undef CRF_APB_APLL_CTRL_RESET_SHIFT #undef CRF_APB_APLL_CTRL_RESET_MASK -#define CRF_APB_APLL_CTRL_RESET_DEFVAL 0x00012C09 -#define CRF_APB_APLL_CTRL_RESET_SHIFT 0 -#define CRF_APB_APLL_CTRL_RESET_MASK 0x00000001U +#define CRF_APB_APLL_CTRL_RESET_DEFVAL 0x00012C09 +#define CRF_APB_APLL_CTRL_RESET_SHIFT 0 +#define CRF_APB_APLL_CTRL_RESET_MASK 0x00000001U -/*APLL is locked*/ +/* +* APLL is locked +*/ #undef CRF_APB_PLL_STATUS_APLL_LOCK_DEFVAL #undef CRF_APB_PLL_STATUS_APLL_LOCK_SHIFT #undef CRF_APB_PLL_STATUS_APLL_LOCK_MASK -#define CRF_APB_PLL_STATUS_APLL_LOCK_DEFVAL 0x00000038 -#define CRF_APB_PLL_STATUS_APLL_LOCK_SHIFT 0 -#define CRF_APB_PLL_STATUS_APLL_LOCK_MASK 0x00000001U +#define CRF_APB_PLL_STATUS_APLL_LOCK_DEFVAL 0x00000038 +#define CRF_APB_PLL_STATUS_APLL_LOCK_SHIFT 0 +#define CRF_APB_PLL_STATUS_APLL_LOCK_MASK 0x00000001U #define CRF_APB_PLL_STATUS_OFFSET 0XFD1A0044 -/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/ +/* +* Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) +*/ #undef CRF_APB_APLL_CTRL_BYPASS_DEFVAL #undef CRF_APB_APLL_CTRL_BYPASS_SHIFT #undef CRF_APB_APLL_CTRL_BYPASS_MASK -#define CRF_APB_APLL_CTRL_BYPASS_DEFVAL 0x00012C09 -#define CRF_APB_APLL_CTRL_BYPASS_SHIFT 3 -#define CRF_APB_APLL_CTRL_BYPASS_MASK 0x00000008U +#define CRF_APB_APLL_CTRL_BYPASS_DEFVAL 0x00012C09 +#define CRF_APB_APLL_CTRL_BYPASS_SHIFT 3 +#define CRF_APB_APLL_CTRL_BYPASS_MASK 0x00000008U -/*Divisor value for this clock.*/ +/* +* Divisor value for this clock. +*/ #undef CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_DEFVAL #undef CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_SHIFT #undef CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_MASK -#define CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_DEFVAL 0x00000400 -#define CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_SHIFT 8 -#define CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_DEFVAL 0x00000400 +#define CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_MASK 0x00003F00U -/*Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona - mode and uses DATA of this register for the fractional portion of the feedback divider.*/ -#undef CRF_APB_APLL_FRAC_CFG_ENABLED_DEFVAL -#undef CRF_APB_APLL_FRAC_CFG_ENABLED_SHIFT -#undef CRF_APB_APLL_FRAC_CFG_ENABLED_MASK -#define CRF_APB_APLL_FRAC_CFG_ENABLED_DEFVAL 0x00000000 -#define CRF_APB_APLL_FRAC_CFG_ENABLED_SHIFT 31 -#define CRF_APB_APLL_FRAC_CFG_ENABLED_MASK 0x80000000U - -/*Fractional value for the Feedback value.*/ -#undef CRF_APB_APLL_FRAC_CFG_DATA_DEFVAL -#undef CRF_APB_APLL_FRAC_CFG_DATA_SHIFT -#undef CRF_APB_APLL_FRAC_CFG_DATA_MASK -#define CRF_APB_APLL_FRAC_CFG_DATA_DEFVAL 0x00000000 -#define CRF_APB_APLL_FRAC_CFG_DATA_SHIFT 0 -#define CRF_APB_APLL_FRAC_CFG_DATA_MASK 0x0000FFFFU - -/*PLL loop filter resistor control*/ +/* +* PLL loop filter resistor control +*/ #undef CRF_APB_DPLL_CFG_RES_DEFVAL #undef CRF_APB_DPLL_CFG_RES_SHIFT #undef CRF_APB_DPLL_CFG_RES_MASK -#define CRF_APB_DPLL_CFG_RES_DEFVAL 0x00000000 -#define CRF_APB_DPLL_CFG_RES_SHIFT 0 -#define CRF_APB_DPLL_CFG_RES_MASK 0x0000000FU +#define CRF_APB_DPLL_CFG_RES_DEFVAL 0x00000000 +#define CRF_APB_DPLL_CFG_RES_SHIFT 0 +#define CRF_APB_DPLL_CFG_RES_MASK 0x0000000FU -/*PLL charge pump control*/ +/* +* PLL charge pump control +*/ #undef CRF_APB_DPLL_CFG_CP_DEFVAL #undef CRF_APB_DPLL_CFG_CP_SHIFT #undef CRF_APB_DPLL_CFG_CP_MASK -#define CRF_APB_DPLL_CFG_CP_DEFVAL 0x00000000 -#define CRF_APB_DPLL_CFG_CP_SHIFT 5 -#define CRF_APB_DPLL_CFG_CP_MASK 0x000001E0U +#define CRF_APB_DPLL_CFG_CP_DEFVAL 0x00000000 +#define CRF_APB_DPLL_CFG_CP_SHIFT 5 +#define CRF_APB_DPLL_CFG_CP_MASK 0x000001E0U -/*PLL loop filter high frequency capacitor control*/ +/* +* PLL loop filter high frequency capacitor control +*/ #undef CRF_APB_DPLL_CFG_LFHF_DEFVAL #undef CRF_APB_DPLL_CFG_LFHF_SHIFT #undef CRF_APB_DPLL_CFG_LFHF_MASK -#define CRF_APB_DPLL_CFG_LFHF_DEFVAL 0x00000000 -#define CRF_APB_DPLL_CFG_LFHF_SHIFT 10 -#define CRF_APB_DPLL_CFG_LFHF_MASK 0x00000C00U +#define CRF_APB_DPLL_CFG_LFHF_DEFVAL 0x00000000 +#define CRF_APB_DPLL_CFG_LFHF_SHIFT 10 +#define CRF_APB_DPLL_CFG_LFHF_MASK 0x00000C00U -/*Lock circuit counter setting*/ +/* +* Lock circuit counter setting +*/ #undef CRF_APB_DPLL_CFG_LOCK_CNT_DEFVAL #undef CRF_APB_DPLL_CFG_LOCK_CNT_SHIFT #undef CRF_APB_DPLL_CFG_LOCK_CNT_MASK -#define CRF_APB_DPLL_CFG_LOCK_CNT_DEFVAL 0x00000000 -#define CRF_APB_DPLL_CFG_LOCK_CNT_SHIFT 13 -#define CRF_APB_DPLL_CFG_LOCK_CNT_MASK 0x007FE000U +#define CRF_APB_DPLL_CFG_LOCK_CNT_DEFVAL 0x00000000 +#define CRF_APB_DPLL_CFG_LOCK_CNT_SHIFT 13 +#define CRF_APB_DPLL_CFG_LOCK_CNT_MASK 0x007FE000U -/*Lock circuit configuration settings for lock windowsize*/ +/* +* Lock circuit configuration settings for lock windowsize +*/ #undef CRF_APB_DPLL_CFG_LOCK_DLY_DEFVAL #undef CRF_APB_DPLL_CFG_LOCK_DLY_SHIFT #undef CRF_APB_DPLL_CFG_LOCK_DLY_MASK -#define CRF_APB_DPLL_CFG_LOCK_DLY_DEFVAL 0x00000000 -#define CRF_APB_DPLL_CFG_LOCK_DLY_SHIFT 25 -#define CRF_APB_DPLL_CFG_LOCK_DLY_MASK 0xFE000000U +#define CRF_APB_DPLL_CFG_LOCK_DLY_DEFVAL 0x00000000 +#define CRF_APB_DPLL_CFG_LOCK_DLY_SHIFT 25 +#define CRF_APB_DPLL_CFG_LOCK_DLY_MASK 0xFE000000U -/*Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_ - ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source*/ +/* +* Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i + * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour + * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source +*/ #undef CRF_APB_DPLL_CTRL_PRE_SRC_DEFVAL #undef CRF_APB_DPLL_CTRL_PRE_SRC_SHIFT #undef CRF_APB_DPLL_CTRL_PRE_SRC_MASK -#define CRF_APB_DPLL_CTRL_PRE_SRC_DEFVAL 0x00002C09 -#define CRF_APB_DPLL_CTRL_PRE_SRC_SHIFT 20 -#define CRF_APB_DPLL_CTRL_PRE_SRC_MASK 0x00700000U +#define CRF_APB_DPLL_CTRL_PRE_SRC_DEFVAL 0x00002C09 +#define CRF_APB_DPLL_CTRL_PRE_SRC_SHIFT 20 +#define CRF_APB_DPLL_CTRL_PRE_SRC_MASK 0x00700000U -/*The integer portion of the feedback divider to the PLL*/ +/* +* The integer portion of the feedback divider to the PLL +*/ #undef CRF_APB_DPLL_CTRL_FBDIV_DEFVAL #undef CRF_APB_DPLL_CTRL_FBDIV_SHIFT #undef CRF_APB_DPLL_CTRL_FBDIV_MASK -#define CRF_APB_DPLL_CTRL_FBDIV_DEFVAL 0x00002C09 -#define CRF_APB_DPLL_CTRL_FBDIV_SHIFT 8 -#define CRF_APB_DPLL_CTRL_FBDIV_MASK 0x00007F00U +#define CRF_APB_DPLL_CTRL_FBDIV_DEFVAL 0x00002C09 +#define CRF_APB_DPLL_CTRL_FBDIV_SHIFT 8 +#define CRF_APB_DPLL_CTRL_FBDIV_MASK 0x00007F00U -/*This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency*/ +/* +* This turns on the divide by 2 that is inside of the PLL. This does not c + * hange the VCO frequency, just the output frequency +*/ #undef CRF_APB_DPLL_CTRL_DIV2_DEFVAL #undef CRF_APB_DPLL_CTRL_DIV2_SHIFT #undef CRF_APB_DPLL_CTRL_DIV2_MASK -#define CRF_APB_DPLL_CTRL_DIV2_DEFVAL 0x00002C09 -#define CRF_APB_DPLL_CTRL_DIV2_SHIFT 16 -#define CRF_APB_DPLL_CTRL_DIV2_MASK 0x00010000U +#define CRF_APB_DPLL_CTRL_DIV2_DEFVAL 0x00002C09 +#define CRF_APB_DPLL_CTRL_DIV2_SHIFT 16 +#define CRF_APB_DPLL_CTRL_DIV2_MASK 0x00010000U -/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/ +/* +* Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) +*/ #undef CRF_APB_DPLL_CTRL_BYPASS_DEFVAL #undef CRF_APB_DPLL_CTRL_BYPASS_SHIFT #undef CRF_APB_DPLL_CTRL_BYPASS_MASK -#define CRF_APB_DPLL_CTRL_BYPASS_DEFVAL 0x00002C09 -#define CRF_APB_DPLL_CTRL_BYPASS_SHIFT 3 -#define CRF_APB_DPLL_CTRL_BYPASS_MASK 0x00000008U +#define CRF_APB_DPLL_CTRL_BYPASS_DEFVAL 0x00002C09 +#define CRF_APB_DPLL_CTRL_BYPASS_SHIFT 3 +#define CRF_APB_DPLL_CTRL_BYPASS_MASK 0x00000008U -/*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/ +/* +* Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. +*/ #undef CRF_APB_DPLL_CTRL_RESET_DEFVAL #undef CRF_APB_DPLL_CTRL_RESET_SHIFT #undef CRF_APB_DPLL_CTRL_RESET_MASK -#define CRF_APB_DPLL_CTRL_RESET_DEFVAL 0x00002C09 -#define CRF_APB_DPLL_CTRL_RESET_SHIFT 0 -#define CRF_APB_DPLL_CTRL_RESET_MASK 0x00000001U +#define CRF_APB_DPLL_CTRL_RESET_DEFVAL 0x00002C09 +#define CRF_APB_DPLL_CTRL_RESET_SHIFT 0 +#define CRF_APB_DPLL_CTRL_RESET_MASK 0x00000001U -/*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/ +/* +* Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. +*/ #undef CRF_APB_DPLL_CTRL_RESET_DEFVAL #undef CRF_APB_DPLL_CTRL_RESET_SHIFT #undef CRF_APB_DPLL_CTRL_RESET_MASK -#define CRF_APB_DPLL_CTRL_RESET_DEFVAL 0x00002C09 -#define CRF_APB_DPLL_CTRL_RESET_SHIFT 0 -#define CRF_APB_DPLL_CTRL_RESET_MASK 0x00000001U +#define CRF_APB_DPLL_CTRL_RESET_DEFVAL 0x00002C09 +#define CRF_APB_DPLL_CTRL_RESET_SHIFT 0 +#define CRF_APB_DPLL_CTRL_RESET_MASK 0x00000001U -/*DPLL is locked*/ +/* +* DPLL is locked +*/ #undef CRF_APB_PLL_STATUS_DPLL_LOCK_DEFVAL #undef CRF_APB_PLL_STATUS_DPLL_LOCK_SHIFT #undef CRF_APB_PLL_STATUS_DPLL_LOCK_MASK -#define CRF_APB_PLL_STATUS_DPLL_LOCK_DEFVAL 0x00000038 -#define CRF_APB_PLL_STATUS_DPLL_LOCK_SHIFT 1 -#define CRF_APB_PLL_STATUS_DPLL_LOCK_MASK 0x00000002U +#define CRF_APB_PLL_STATUS_DPLL_LOCK_DEFVAL 0x00000038 +#define CRF_APB_PLL_STATUS_DPLL_LOCK_SHIFT 1 +#define CRF_APB_PLL_STATUS_DPLL_LOCK_MASK 0x00000002U #define CRF_APB_PLL_STATUS_OFFSET 0XFD1A0044 -/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/ +/* +* Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) +*/ #undef CRF_APB_DPLL_CTRL_BYPASS_DEFVAL #undef CRF_APB_DPLL_CTRL_BYPASS_SHIFT #undef CRF_APB_DPLL_CTRL_BYPASS_MASK -#define CRF_APB_DPLL_CTRL_BYPASS_DEFVAL 0x00002C09 -#define CRF_APB_DPLL_CTRL_BYPASS_SHIFT 3 -#define CRF_APB_DPLL_CTRL_BYPASS_MASK 0x00000008U +#define CRF_APB_DPLL_CTRL_BYPASS_DEFVAL 0x00002C09 +#define CRF_APB_DPLL_CTRL_BYPASS_SHIFT 3 +#define CRF_APB_DPLL_CTRL_BYPASS_MASK 0x00000008U -/*Divisor value for this clock.*/ +/* +* Divisor value for this clock. +*/ #undef CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL #undef CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_SHIFT #undef CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_MASK -#define CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL 0x00000400 -#define CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_SHIFT 8 -#define CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL 0x00000400 +#define CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_MASK 0x00003F00U -/*Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona - mode and uses DATA of this register for the fractional portion of the feedback divider.*/ -#undef CRF_APB_DPLL_FRAC_CFG_ENABLED_DEFVAL -#undef CRF_APB_DPLL_FRAC_CFG_ENABLED_SHIFT -#undef CRF_APB_DPLL_FRAC_CFG_ENABLED_MASK -#define CRF_APB_DPLL_FRAC_CFG_ENABLED_DEFVAL 0x00000000 -#define CRF_APB_DPLL_FRAC_CFG_ENABLED_SHIFT 31 -#define CRF_APB_DPLL_FRAC_CFG_ENABLED_MASK 0x80000000U - -/*Fractional value for the Feedback value.*/ -#undef CRF_APB_DPLL_FRAC_CFG_DATA_DEFVAL -#undef CRF_APB_DPLL_FRAC_CFG_DATA_SHIFT -#undef CRF_APB_DPLL_FRAC_CFG_DATA_MASK -#define CRF_APB_DPLL_FRAC_CFG_DATA_DEFVAL 0x00000000 -#define CRF_APB_DPLL_FRAC_CFG_DATA_SHIFT 0 -#define CRF_APB_DPLL_FRAC_CFG_DATA_MASK 0x0000FFFFU - -/*PLL loop filter resistor control*/ +/* +* PLL loop filter resistor control +*/ #undef CRF_APB_VPLL_CFG_RES_DEFVAL #undef CRF_APB_VPLL_CFG_RES_SHIFT #undef CRF_APB_VPLL_CFG_RES_MASK -#define CRF_APB_VPLL_CFG_RES_DEFVAL 0x00000000 -#define CRF_APB_VPLL_CFG_RES_SHIFT 0 -#define CRF_APB_VPLL_CFG_RES_MASK 0x0000000FU +#define CRF_APB_VPLL_CFG_RES_DEFVAL 0x00000000 +#define CRF_APB_VPLL_CFG_RES_SHIFT 0 +#define CRF_APB_VPLL_CFG_RES_MASK 0x0000000FU -/*PLL charge pump control*/ +/* +* PLL charge pump control +*/ #undef CRF_APB_VPLL_CFG_CP_DEFVAL #undef CRF_APB_VPLL_CFG_CP_SHIFT #undef CRF_APB_VPLL_CFG_CP_MASK -#define CRF_APB_VPLL_CFG_CP_DEFVAL 0x00000000 -#define CRF_APB_VPLL_CFG_CP_SHIFT 5 -#define CRF_APB_VPLL_CFG_CP_MASK 0x000001E0U +#define CRF_APB_VPLL_CFG_CP_DEFVAL 0x00000000 +#define CRF_APB_VPLL_CFG_CP_SHIFT 5 +#define CRF_APB_VPLL_CFG_CP_MASK 0x000001E0U -/*PLL loop filter high frequency capacitor control*/ +/* +* PLL loop filter high frequency capacitor control +*/ #undef CRF_APB_VPLL_CFG_LFHF_DEFVAL #undef CRF_APB_VPLL_CFG_LFHF_SHIFT #undef CRF_APB_VPLL_CFG_LFHF_MASK -#define CRF_APB_VPLL_CFG_LFHF_DEFVAL 0x00000000 -#define CRF_APB_VPLL_CFG_LFHF_SHIFT 10 -#define CRF_APB_VPLL_CFG_LFHF_MASK 0x00000C00U +#define CRF_APB_VPLL_CFG_LFHF_DEFVAL 0x00000000 +#define CRF_APB_VPLL_CFG_LFHF_SHIFT 10 +#define CRF_APB_VPLL_CFG_LFHF_MASK 0x00000C00U -/*Lock circuit counter setting*/ +/* +* Lock circuit counter setting +*/ #undef CRF_APB_VPLL_CFG_LOCK_CNT_DEFVAL #undef CRF_APB_VPLL_CFG_LOCK_CNT_SHIFT #undef CRF_APB_VPLL_CFG_LOCK_CNT_MASK -#define CRF_APB_VPLL_CFG_LOCK_CNT_DEFVAL 0x00000000 -#define CRF_APB_VPLL_CFG_LOCK_CNT_SHIFT 13 -#define CRF_APB_VPLL_CFG_LOCK_CNT_MASK 0x007FE000U +#define CRF_APB_VPLL_CFG_LOCK_CNT_DEFVAL 0x00000000 +#define CRF_APB_VPLL_CFG_LOCK_CNT_SHIFT 13 +#define CRF_APB_VPLL_CFG_LOCK_CNT_MASK 0x007FE000U -/*Lock circuit configuration settings for lock windowsize*/ +/* +* Lock circuit configuration settings for lock windowsize +*/ #undef CRF_APB_VPLL_CFG_LOCK_DLY_DEFVAL #undef CRF_APB_VPLL_CFG_LOCK_DLY_SHIFT #undef CRF_APB_VPLL_CFG_LOCK_DLY_MASK -#define CRF_APB_VPLL_CFG_LOCK_DLY_DEFVAL 0x00000000 -#define CRF_APB_VPLL_CFG_LOCK_DLY_SHIFT 25 -#define CRF_APB_VPLL_CFG_LOCK_DLY_MASK 0xFE000000U +#define CRF_APB_VPLL_CFG_LOCK_DLY_DEFVAL 0x00000000 +#define CRF_APB_VPLL_CFG_LOCK_DLY_SHIFT 25 +#define CRF_APB_VPLL_CFG_LOCK_DLY_MASK 0xFE000000U -/*Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_ - ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source*/ +/* +* Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i + * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour + * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source +*/ #undef CRF_APB_VPLL_CTRL_PRE_SRC_DEFVAL #undef CRF_APB_VPLL_CTRL_PRE_SRC_SHIFT #undef CRF_APB_VPLL_CTRL_PRE_SRC_MASK -#define CRF_APB_VPLL_CTRL_PRE_SRC_DEFVAL 0x00012809 -#define CRF_APB_VPLL_CTRL_PRE_SRC_SHIFT 20 -#define CRF_APB_VPLL_CTRL_PRE_SRC_MASK 0x00700000U +#define CRF_APB_VPLL_CTRL_PRE_SRC_DEFVAL 0x00012809 +#define CRF_APB_VPLL_CTRL_PRE_SRC_SHIFT 20 +#define CRF_APB_VPLL_CTRL_PRE_SRC_MASK 0x00700000U -/*The integer portion of the feedback divider to the PLL*/ +/* +* The integer portion of the feedback divider to the PLL +*/ #undef CRF_APB_VPLL_CTRL_FBDIV_DEFVAL #undef CRF_APB_VPLL_CTRL_FBDIV_SHIFT #undef CRF_APB_VPLL_CTRL_FBDIV_MASK -#define CRF_APB_VPLL_CTRL_FBDIV_DEFVAL 0x00012809 -#define CRF_APB_VPLL_CTRL_FBDIV_SHIFT 8 -#define CRF_APB_VPLL_CTRL_FBDIV_MASK 0x00007F00U +#define CRF_APB_VPLL_CTRL_FBDIV_DEFVAL 0x00012809 +#define CRF_APB_VPLL_CTRL_FBDIV_SHIFT 8 +#define CRF_APB_VPLL_CTRL_FBDIV_MASK 0x00007F00U -/*This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency*/ +/* +* This turns on the divide by 2 that is inside of the PLL. This does not c + * hange the VCO frequency, just the output frequency +*/ #undef CRF_APB_VPLL_CTRL_DIV2_DEFVAL #undef CRF_APB_VPLL_CTRL_DIV2_SHIFT #undef CRF_APB_VPLL_CTRL_DIV2_MASK -#define CRF_APB_VPLL_CTRL_DIV2_DEFVAL 0x00012809 -#define CRF_APB_VPLL_CTRL_DIV2_SHIFT 16 -#define CRF_APB_VPLL_CTRL_DIV2_MASK 0x00010000U +#define CRF_APB_VPLL_CTRL_DIV2_DEFVAL 0x00012809 +#define CRF_APB_VPLL_CTRL_DIV2_SHIFT 16 +#define CRF_APB_VPLL_CTRL_DIV2_MASK 0x00010000U -/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/ +/* +* Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) +*/ #undef CRF_APB_VPLL_CTRL_BYPASS_DEFVAL #undef CRF_APB_VPLL_CTRL_BYPASS_SHIFT #undef CRF_APB_VPLL_CTRL_BYPASS_MASK -#define CRF_APB_VPLL_CTRL_BYPASS_DEFVAL 0x00012809 -#define CRF_APB_VPLL_CTRL_BYPASS_SHIFT 3 -#define CRF_APB_VPLL_CTRL_BYPASS_MASK 0x00000008U +#define CRF_APB_VPLL_CTRL_BYPASS_DEFVAL 0x00012809 +#define CRF_APB_VPLL_CTRL_BYPASS_SHIFT 3 +#define CRF_APB_VPLL_CTRL_BYPASS_MASK 0x00000008U -/*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/ +/* +* Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. +*/ #undef CRF_APB_VPLL_CTRL_RESET_DEFVAL #undef CRF_APB_VPLL_CTRL_RESET_SHIFT #undef CRF_APB_VPLL_CTRL_RESET_MASK -#define CRF_APB_VPLL_CTRL_RESET_DEFVAL 0x00012809 -#define CRF_APB_VPLL_CTRL_RESET_SHIFT 0 -#define CRF_APB_VPLL_CTRL_RESET_MASK 0x00000001U +#define CRF_APB_VPLL_CTRL_RESET_DEFVAL 0x00012809 +#define CRF_APB_VPLL_CTRL_RESET_SHIFT 0 +#define CRF_APB_VPLL_CTRL_RESET_MASK 0x00000001U -/*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/ +/* +* Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. +*/ #undef CRF_APB_VPLL_CTRL_RESET_DEFVAL #undef CRF_APB_VPLL_CTRL_RESET_SHIFT #undef CRF_APB_VPLL_CTRL_RESET_MASK -#define CRF_APB_VPLL_CTRL_RESET_DEFVAL 0x00012809 -#define CRF_APB_VPLL_CTRL_RESET_SHIFT 0 -#define CRF_APB_VPLL_CTRL_RESET_MASK 0x00000001U +#define CRF_APB_VPLL_CTRL_RESET_DEFVAL 0x00012809 +#define CRF_APB_VPLL_CTRL_RESET_SHIFT 0 +#define CRF_APB_VPLL_CTRL_RESET_MASK 0x00000001U -/*VPLL is locked*/ +/* +* VPLL is locked +*/ #undef CRF_APB_PLL_STATUS_VPLL_LOCK_DEFVAL #undef CRF_APB_PLL_STATUS_VPLL_LOCK_SHIFT #undef CRF_APB_PLL_STATUS_VPLL_LOCK_MASK -#define CRF_APB_PLL_STATUS_VPLL_LOCK_DEFVAL 0x00000038 -#define CRF_APB_PLL_STATUS_VPLL_LOCK_SHIFT 2 -#define CRF_APB_PLL_STATUS_VPLL_LOCK_MASK 0x00000004U +#define CRF_APB_PLL_STATUS_VPLL_LOCK_DEFVAL 0x00000038 +#define CRF_APB_PLL_STATUS_VPLL_LOCK_SHIFT 2 +#define CRF_APB_PLL_STATUS_VPLL_LOCK_MASK 0x00000004U #define CRF_APB_PLL_STATUS_OFFSET 0XFD1A0044 -/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/ +/* +* Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) +*/ #undef CRF_APB_VPLL_CTRL_BYPASS_DEFVAL #undef CRF_APB_VPLL_CTRL_BYPASS_SHIFT #undef CRF_APB_VPLL_CTRL_BYPASS_MASK -#define CRF_APB_VPLL_CTRL_BYPASS_DEFVAL 0x00012809 -#define CRF_APB_VPLL_CTRL_BYPASS_SHIFT 3 -#define CRF_APB_VPLL_CTRL_BYPASS_MASK 0x00000008U +#define CRF_APB_VPLL_CTRL_BYPASS_DEFVAL 0x00012809 +#define CRF_APB_VPLL_CTRL_BYPASS_SHIFT 3 +#define CRF_APB_VPLL_CTRL_BYPASS_MASK 0x00000008U -/*Divisor value for this clock.*/ +/* +* Divisor value for this clock. +*/ #undef CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL #undef CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_SHIFT #undef CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_MASK -#define CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL 0x00000400 -#define CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_SHIFT 8 -#define CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_MASK 0x00003F00U - -/*Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona - mode and uses DATA of this register for the fractional portion of the feedback divider.*/ -#undef CRF_APB_VPLL_FRAC_CFG_ENABLED_DEFVAL -#undef CRF_APB_VPLL_FRAC_CFG_ENABLED_SHIFT -#undef CRF_APB_VPLL_FRAC_CFG_ENABLED_MASK -#define CRF_APB_VPLL_FRAC_CFG_ENABLED_DEFVAL 0x00000000 -#define CRF_APB_VPLL_FRAC_CFG_ENABLED_SHIFT 31 -#define CRF_APB_VPLL_FRAC_CFG_ENABLED_MASK 0x80000000U - -/*Fractional value for the Feedback value.*/ -#undef CRF_APB_VPLL_FRAC_CFG_DATA_DEFVAL -#undef CRF_APB_VPLL_FRAC_CFG_DATA_SHIFT -#undef CRF_APB_VPLL_FRAC_CFG_DATA_MASK -#define CRF_APB_VPLL_FRAC_CFG_DATA_DEFVAL 0x00000000 -#define CRF_APB_VPLL_FRAC_CFG_DATA_SHIFT 0 -#define CRF_APB_VPLL_FRAC_CFG_DATA_MASK 0x0000FFFFU +#define CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL 0x00000400 +#define CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_MASK 0x00003F00U #undef CRL_APB_GEM3_REF_CTRL_OFFSET #define CRL_APB_GEM3_REF_CTRL_OFFSET 0XFF5E005C +#undef CRL_APB_GEM_TSU_REF_CTRL_OFFSET +#define CRL_APB_GEM_TSU_REF_CTRL_OFFSET 0XFF5E0100 #undef CRL_APB_USB0_BUS_REF_CTRL_OFFSET #define CRL_APB_USB0_BUS_REF_CTRL_OFFSET 0XFF5E0060 #undef CRL_APB_USB3_DUAL_REF_CTRL_OFFSET @@ -822,12 +909,6 @@ #define CRL_APB_ADMA_REF_CTRL_OFFSET 0XFF5E00B8 #undef CRL_APB_PL0_REF_CTRL_OFFSET #define CRL_APB_PL0_REF_CTRL_OFFSET 0XFF5E00C0 -#undef CRL_APB_PL1_REF_CTRL_OFFSET -#define CRL_APB_PL1_REF_CTRL_OFFSET 0XFF5E00C4 -#undef CRL_APB_PL2_REF_CTRL_OFFSET -#define CRL_APB_PL2_REF_CTRL_OFFSET 0XFF5E00C8 -#undef CRL_APB_PL3_REF_CTRL_OFFSET -#define CRL_APB_PL3_REF_CTRL_OFFSET 0XFF5E00CC #undef CRL_APB_AMS_REF_CTRL_OFFSET #define CRL_APB_AMS_REF_CTRL_OFFSET 0XFF5E0108 #undef CRL_APB_DLL_REF_CTRL_OFFSET @@ -846,8 +927,6 @@ #define CRF_APB_DP_STC_REF_CTRL_OFFSET 0XFD1A007C #undef CRF_APB_ACPU_CTRL_OFFSET #define CRF_APB_ACPU_CTRL_OFFSET 0XFD1A0060 -#undef CRF_APB_DBG_TRACE_CTRL_OFFSET -#define CRF_APB_DBG_TRACE_CTRL_OFFSET 0XFD1A0064 #undef CRF_APB_DBG_FPD_CTRL_OFFSET #define CRF_APB_DBG_FPD_CTRL_OFFSET 0XFD1A0068 #undef CRF_APB_DDR_CTRL_OFFSET @@ -873,1195 +952,1418 @@ #undef LPD_SLCR_CSUPMU_WDT_CLK_SEL_OFFSET #define LPD_SLCR_CSUPMU_WDT_CLK_SEL_OFFSET 0XFF410050 -/*Clock active for the RX channel*/ +/* +* Clock active for the RX channel +*/ #undef CRL_APB_GEM3_REF_CTRL_RX_CLKACT_DEFVAL #undef CRL_APB_GEM3_REF_CTRL_RX_CLKACT_SHIFT #undef CRL_APB_GEM3_REF_CTRL_RX_CLKACT_MASK -#define CRL_APB_GEM3_REF_CTRL_RX_CLKACT_DEFVAL 0x00002500 -#define CRL_APB_GEM3_REF_CTRL_RX_CLKACT_SHIFT 26 -#define CRL_APB_GEM3_REF_CTRL_RX_CLKACT_MASK 0x04000000U +#define CRL_APB_GEM3_REF_CTRL_RX_CLKACT_DEFVAL 0x00002500 +#define CRL_APB_GEM3_REF_CTRL_RX_CLKACT_SHIFT 26 +#define CRL_APB_GEM3_REF_CTRL_RX_CLKACT_MASK 0x04000000U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRL_APB_GEM3_REF_CTRL_CLKACT_DEFVAL #undef CRL_APB_GEM3_REF_CTRL_CLKACT_SHIFT #undef CRL_APB_GEM3_REF_CTRL_CLKACT_MASK -#define CRL_APB_GEM3_REF_CTRL_CLKACT_DEFVAL 0x00002500 -#define CRL_APB_GEM3_REF_CTRL_CLKACT_SHIFT 25 -#define CRL_APB_GEM3_REF_CTRL_CLKACT_MASK 0x02000000U +#define CRL_APB_GEM3_REF_CTRL_CLKACT_DEFVAL 0x00002500 +#define CRL_APB_GEM3_REF_CTRL_CLKACT_SHIFT 25 +#define CRL_APB_GEM3_REF_CTRL_CLKACT_MASK 0x02000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_GEM3_REF_CTRL_DIVISOR1_DEFVAL #undef CRL_APB_GEM3_REF_CTRL_DIVISOR1_SHIFT #undef CRL_APB_GEM3_REF_CTRL_DIVISOR1_MASK -#define CRL_APB_GEM3_REF_CTRL_DIVISOR1_DEFVAL 0x00002500 -#define CRL_APB_GEM3_REF_CTRL_DIVISOR1_SHIFT 16 -#define CRL_APB_GEM3_REF_CTRL_DIVISOR1_MASK 0x003F0000U +#define CRL_APB_GEM3_REF_CTRL_DIVISOR1_DEFVAL 0x00002500 +#define CRL_APB_GEM3_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_GEM3_REF_CTRL_DIVISOR1_MASK 0x003F0000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_GEM3_REF_CTRL_DIVISOR0_DEFVAL #undef CRL_APB_GEM3_REF_CTRL_DIVISOR0_SHIFT #undef CRL_APB_GEM3_REF_CTRL_DIVISOR0_MASK -#define CRL_APB_GEM3_REF_CTRL_DIVISOR0_DEFVAL 0x00002500 -#define CRL_APB_GEM3_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_GEM3_REF_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRL_APB_GEM3_REF_CTRL_DIVISOR0_DEFVAL 0x00002500 +#define CRL_APB_GEM3_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_GEM3_REF_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRL_APB_GEM3_REF_CTRL_SRCSEL_DEFVAL #undef CRL_APB_GEM3_REF_CTRL_SRCSEL_SHIFT #undef CRL_APB_GEM3_REF_CTRL_SRCSEL_MASK -#define CRL_APB_GEM3_REF_CTRL_SRCSEL_DEFVAL 0x00002500 -#define CRL_APB_GEM3_REF_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_GEM3_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRL_APB_GEM3_REF_CTRL_SRCSEL_DEFVAL 0x00002500 +#define CRL_APB_GEM3_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_GEM3_REF_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* 6 bit divider +*/ +#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_DEFVAL +#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_SHIFT +#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_MASK +#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_DEFVAL 0x00051000 +#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_MASK 0x00003F00U + +/* +* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ +#undef CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_DEFVAL +#undef CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_SHIFT +#undef CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_MASK +#define CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_DEFVAL 0x00051000 +#define CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_MASK 0x00000007U + +/* +* 6 bit divider +*/ +#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_DEFVAL +#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_SHIFT +#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_MASK +#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_DEFVAL 0x00051000 +#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_MASK 0x003F0000U + +/* +* Clock active signal. Switch to 0 to disable the clock +*/ +#undef CRL_APB_GEM_TSU_REF_CTRL_CLKACT_DEFVAL +#undef CRL_APB_GEM_TSU_REF_CTRL_CLKACT_SHIFT +#undef CRL_APB_GEM_TSU_REF_CTRL_CLKACT_MASK +#define CRL_APB_GEM_TSU_REF_CTRL_CLKACT_DEFVAL 0x00051000 +#define CRL_APB_GEM_TSU_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_GEM_TSU_REF_CTRL_CLKACT_MASK 0x01000000U + +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRL_APB_USB0_BUS_REF_CTRL_CLKACT_DEFVAL #undef CRL_APB_USB0_BUS_REF_CTRL_CLKACT_SHIFT #undef CRL_APB_USB0_BUS_REF_CTRL_CLKACT_MASK -#define CRL_APB_USB0_BUS_REF_CTRL_CLKACT_DEFVAL 0x00052000 -#define CRL_APB_USB0_BUS_REF_CTRL_CLKACT_SHIFT 25 -#define CRL_APB_USB0_BUS_REF_CTRL_CLKACT_MASK 0x02000000U +#define CRL_APB_USB0_BUS_REF_CTRL_CLKACT_DEFVAL 0x00052000 +#define CRL_APB_USB0_BUS_REF_CTRL_CLKACT_SHIFT 25 +#define CRL_APB_USB0_BUS_REF_CTRL_CLKACT_MASK 0x02000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_DEFVAL #undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_SHIFT #undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_MASK -#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_DEFVAL 0x00052000 -#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_SHIFT 16 -#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_MASK 0x003F0000U +#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_DEFVAL 0x00052000 +#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_MASK 0x003F0000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_DEFVAL #undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_SHIFT #undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_MASK -#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_DEFVAL 0x00052000 -#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_DEFVAL 0x00052000 +#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_DEFVAL #undef CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_SHIFT #undef CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_MASK -#define CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_DEFVAL 0x00052000 -#define CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_DEFVAL 0x00052000 +#define CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_DEFVAL #undef CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_SHIFT #undef CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_MASK -#define CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_DEFVAL 0x00052000 -#define CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_SHIFT 25 -#define CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_MASK 0x02000000U +#define CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_DEFVAL 0x00052000 +#define CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_SHIFT 25 +#define CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_MASK 0x02000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_DEFVAL #undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_SHIFT #undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_MASK -#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_DEFVAL 0x00052000 -#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_SHIFT 16 -#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_MASK 0x003F0000U +#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_DEFVAL 0x00052000 +#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_MASK 0x003F0000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_DEFVAL #undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_SHIFT #undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_MASK -#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_DEFVAL 0x00052000 -#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_DEFVAL 0x00052000 +#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = IOPLL; 010 = RPLL; 011 = DPLL. (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = IOPLL; 010 = RPLL; 011 = DPLL. (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_DEFVAL #undef CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_SHIFT #undef CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_MASK -#define CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_DEFVAL 0x00052000 -#define CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_DEFVAL 0x00052000 +#define CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRL_APB_QSPI_REF_CTRL_CLKACT_DEFVAL #undef CRL_APB_QSPI_REF_CTRL_CLKACT_SHIFT #undef CRL_APB_QSPI_REF_CTRL_CLKACT_MASK -#define CRL_APB_QSPI_REF_CTRL_CLKACT_DEFVAL 0x01000800 -#define CRL_APB_QSPI_REF_CTRL_CLKACT_SHIFT 24 -#define CRL_APB_QSPI_REF_CTRL_CLKACT_MASK 0x01000000U +#define CRL_APB_QSPI_REF_CTRL_CLKACT_DEFVAL 0x01000800 +#define CRL_APB_QSPI_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_QSPI_REF_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_QSPI_REF_CTRL_DIVISOR1_DEFVAL #undef CRL_APB_QSPI_REF_CTRL_DIVISOR1_SHIFT #undef CRL_APB_QSPI_REF_CTRL_DIVISOR1_MASK -#define CRL_APB_QSPI_REF_CTRL_DIVISOR1_DEFVAL 0x01000800 -#define CRL_APB_QSPI_REF_CTRL_DIVISOR1_SHIFT 16 -#define CRL_APB_QSPI_REF_CTRL_DIVISOR1_MASK 0x003F0000U +#define CRL_APB_QSPI_REF_CTRL_DIVISOR1_DEFVAL 0x01000800 +#define CRL_APB_QSPI_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_QSPI_REF_CTRL_DIVISOR1_MASK 0x003F0000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_QSPI_REF_CTRL_DIVISOR0_DEFVAL #undef CRL_APB_QSPI_REF_CTRL_DIVISOR0_SHIFT #undef CRL_APB_QSPI_REF_CTRL_DIVISOR0_MASK -#define CRL_APB_QSPI_REF_CTRL_DIVISOR0_DEFVAL 0x01000800 -#define CRL_APB_QSPI_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_QSPI_REF_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRL_APB_QSPI_REF_CTRL_DIVISOR0_DEFVAL 0x01000800 +#define CRL_APB_QSPI_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_QSPI_REF_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRL_APB_QSPI_REF_CTRL_SRCSEL_DEFVAL #undef CRL_APB_QSPI_REF_CTRL_SRCSEL_SHIFT #undef CRL_APB_QSPI_REF_CTRL_SRCSEL_MASK -#define CRL_APB_QSPI_REF_CTRL_SRCSEL_DEFVAL 0x01000800 -#define CRL_APB_QSPI_REF_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_QSPI_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRL_APB_QSPI_REF_CTRL_SRCSEL_DEFVAL 0x01000800 +#define CRL_APB_QSPI_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_QSPI_REF_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRL_APB_SDIO1_REF_CTRL_CLKACT_DEFVAL #undef CRL_APB_SDIO1_REF_CTRL_CLKACT_SHIFT #undef CRL_APB_SDIO1_REF_CTRL_CLKACT_MASK -#define CRL_APB_SDIO1_REF_CTRL_CLKACT_DEFVAL 0x01000F00 -#define CRL_APB_SDIO1_REF_CTRL_CLKACT_SHIFT 24 -#define CRL_APB_SDIO1_REF_CTRL_CLKACT_MASK 0x01000000U +#define CRL_APB_SDIO1_REF_CTRL_CLKACT_DEFVAL 0x01000F00 +#define CRL_APB_SDIO1_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_SDIO1_REF_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_SDIO1_REF_CTRL_DIVISOR1_DEFVAL #undef CRL_APB_SDIO1_REF_CTRL_DIVISOR1_SHIFT #undef CRL_APB_SDIO1_REF_CTRL_DIVISOR1_MASK -#define CRL_APB_SDIO1_REF_CTRL_DIVISOR1_DEFVAL 0x01000F00 -#define CRL_APB_SDIO1_REF_CTRL_DIVISOR1_SHIFT 16 -#define CRL_APB_SDIO1_REF_CTRL_DIVISOR1_MASK 0x003F0000U +#define CRL_APB_SDIO1_REF_CTRL_DIVISOR1_DEFVAL 0x01000F00 +#define CRL_APB_SDIO1_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_SDIO1_REF_CTRL_DIVISOR1_MASK 0x003F0000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_SDIO1_REF_CTRL_DIVISOR0_DEFVAL #undef CRL_APB_SDIO1_REF_CTRL_DIVISOR0_SHIFT #undef CRL_APB_SDIO1_REF_CTRL_DIVISOR0_MASK -#define CRL_APB_SDIO1_REF_CTRL_DIVISOR0_DEFVAL 0x01000F00 -#define CRL_APB_SDIO1_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_SDIO1_REF_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRL_APB_SDIO1_REF_CTRL_DIVISOR0_DEFVAL 0x01000F00 +#define CRL_APB_SDIO1_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_SDIO1_REF_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = IOPLL; 010 = RPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = IOPLL; 010 = RPLL; 011 = VPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRL_APB_SDIO1_REF_CTRL_SRCSEL_DEFVAL #undef CRL_APB_SDIO1_REF_CTRL_SRCSEL_SHIFT #undef CRL_APB_SDIO1_REF_CTRL_SRCSEL_MASK -#define CRL_APB_SDIO1_REF_CTRL_SRCSEL_DEFVAL 0x01000F00 -#define CRL_APB_SDIO1_REF_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_SDIO1_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRL_APB_SDIO1_REF_CTRL_SRCSEL_DEFVAL 0x01000F00 +#define CRL_APB_SDIO1_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_SDIO1_REF_CTRL_SRCSEL_MASK 0x00000007U -/*MIO pad selection for sdio1_rx_clk (feedback clock from the PAD) 0: MIO [51] 1: MIO [76]*/ +/* +* MIO pad selection for sdio1_rx_clk (feedback clock from the PAD) 0: MIO + * [51] 1: MIO [76] +*/ #undef IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_DEFVAL #undef IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_SHIFT #undef IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_MASK -#define IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_SHIFT 17 -#define IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_MASK 0x00020000U +#define IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_SHIFT 17 +#define IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_MASK 0x00020000U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRL_APB_UART0_REF_CTRL_CLKACT_DEFVAL #undef CRL_APB_UART0_REF_CTRL_CLKACT_SHIFT #undef CRL_APB_UART0_REF_CTRL_CLKACT_MASK -#define CRL_APB_UART0_REF_CTRL_CLKACT_DEFVAL 0x01001800 -#define CRL_APB_UART0_REF_CTRL_CLKACT_SHIFT 24 -#define CRL_APB_UART0_REF_CTRL_CLKACT_MASK 0x01000000U +#define CRL_APB_UART0_REF_CTRL_CLKACT_DEFVAL 0x01001800 +#define CRL_APB_UART0_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_UART0_REF_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_UART0_REF_CTRL_DIVISOR1_DEFVAL #undef CRL_APB_UART0_REF_CTRL_DIVISOR1_SHIFT #undef CRL_APB_UART0_REF_CTRL_DIVISOR1_MASK -#define CRL_APB_UART0_REF_CTRL_DIVISOR1_DEFVAL 0x01001800 -#define CRL_APB_UART0_REF_CTRL_DIVISOR1_SHIFT 16 -#define CRL_APB_UART0_REF_CTRL_DIVISOR1_MASK 0x003F0000U +#define CRL_APB_UART0_REF_CTRL_DIVISOR1_DEFVAL 0x01001800 +#define CRL_APB_UART0_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_UART0_REF_CTRL_DIVISOR1_MASK 0x003F0000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_UART0_REF_CTRL_DIVISOR0_DEFVAL #undef CRL_APB_UART0_REF_CTRL_DIVISOR0_SHIFT #undef CRL_APB_UART0_REF_CTRL_DIVISOR0_MASK -#define CRL_APB_UART0_REF_CTRL_DIVISOR0_DEFVAL 0x01001800 -#define CRL_APB_UART0_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_UART0_REF_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRL_APB_UART0_REF_CTRL_DIVISOR0_DEFVAL 0x01001800 +#define CRL_APB_UART0_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_UART0_REF_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRL_APB_UART0_REF_CTRL_SRCSEL_DEFVAL #undef CRL_APB_UART0_REF_CTRL_SRCSEL_SHIFT #undef CRL_APB_UART0_REF_CTRL_SRCSEL_MASK -#define CRL_APB_UART0_REF_CTRL_SRCSEL_DEFVAL 0x01001800 -#define CRL_APB_UART0_REF_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_UART0_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRL_APB_UART0_REF_CTRL_SRCSEL_DEFVAL 0x01001800 +#define CRL_APB_UART0_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_UART0_REF_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRL_APB_UART1_REF_CTRL_CLKACT_DEFVAL #undef CRL_APB_UART1_REF_CTRL_CLKACT_SHIFT #undef CRL_APB_UART1_REF_CTRL_CLKACT_MASK -#define CRL_APB_UART1_REF_CTRL_CLKACT_DEFVAL 0x01001800 -#define CRL_APB_UART1_REF_CTRL_CLKACT_SHIFT 24 -#define CRL_APB_UART1_REF_CTRL_CLKACT_MASK 0x01000000U +#define CRL_APB_UART1_REF_CTRL_CLKACT_DEFVAL 0x01001800 +#define CRL_APB_UART1_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_UART1_REF_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_UART1_REF_CTRL_DIVISOR1_DEFVAL #undef CRL_APB_UART1_REF_CTRL_DIVISOR1_SHIFT #undef CRL_APB_UART1_REF_CTRL_DIVISOR1_MASK -#define CRL_APB_UART1_REF_CTRL_DIVISOR1_DEFVAL 0x01001800 -#define CRL_APB_UART1_REF_CTRL_DIVISOR1_SHIFT 16 -#define CRL_APB_UART1_REF_CTRL_DIVISOR1_MASK 0x003F0000U +#define CRL_APB_UART1_REF_CTRL_DIVISOR1_DEFVAL 0x01001800 +#define CRL_APB_UART1_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_UART1_REF_CTRL_DIVISOR1_MASK 0x003F0000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_UART1_REF_CTRL_DIVISOR0_DEFVAL #undef CRL_APB_UART1_REF_CTRL_DIVISOR0_SHIFT #undef CRL_APB_UART1_REF_CTRL_DIVISOR0_MASK -#define CRL_APB_UART1_REF_CTRL_DIVISOR0_DEFVAL 0x01001800 -#define CRL_APB_UART1_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_UART1_REF_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRL_APB_UART1_REF_CTRL_DIVISOR0_DEFVAL 0x01001800 +#define CRL_APB_UART1_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_UART1_REF_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRL_APB_UART1_REF_CTRL_SRCSEL_DEFVAL #undef CRL_APB_UART1_REF_CTRL_SRCSEL_SHIFT #undef CRL_APB_UART1_REF_CTRL_SRCSEL_MASK -#define CRL_APB_UART1_REF_CTRL_SRCSEL_DEFVAL 0x01001800 -#define CRL_APB_UART1_REF_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_UART1_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRL_APB_UART1_REF_CTRL_SRCSEL_DEFVAL 0x01001800 +#define CRL_APB_UART1_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_UART1_REF_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRL_APB_I2C0_REF_CTRL_CLKACT_DEFVAL #undef CRL_APB_I2C0_REF_CTRL_CLKACT_SHIFT #undef CRL_APB_I2C0_REF_CTRL_CLKACT_MASK -#define CRL_APB_I2C0_REF_CTRL_CLKACT_DEFVAL 0x01000500 -#define CRL_APB_I2C0_REF_CTRL_CLKACT_SHIFT 24 -#define CRL_APB_I2C0_REF_CTRL_CLKACT_MASK 0x01000000U +#define CRL_APB_I2C0_REF_CTRL_CLKACT_DEFVAL 0x01000500 +#define CRL_APB_I2C0_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_I2C0_REF_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_I2C0_REF_CTRL_DIVISOR1_DEFVAL #undef CRL_APB_I2C0_REF_CTRL_DIVISOR1_SHIFT #undef CRL_APB_I2C0_REF_CTRL_DIVISOR1_MASK -#define CRL_APB_I2C0_REF_CTRL_DIVISOR1_DEFVAL 0x01000500 -#define CRL_APB_I2C0_REF_CTRL_DIVISOR1_SHIFT 16 -#define CRL_APB_I2C0_REF_CTRL_DIVISOR1_MASK 0x003F0000U +#define CRL_APB_I2C0_REF_CTRL_DIVISOR1_DEFVAL 0x01000500 +#define CRL_APB_I2C0_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_I2C0_REF_CTRL_DIVISOR1_MASK 0x003F0000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_I2C0_REF_CTRL_DIVISOR0_DEFVAL #undef CRL_APB_I2C0_REF_CTRL_DIVISOR0_SHIFT #undef CRL_APB_I2C0_REF_CTRL_DIVISOR0_MASK -#define CRL_APB_I2C0_REF_CTRL_DIVISOR0_DEFVAL 0x01000500 -#define CRL_APB_I2C0_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_I2C0_REF_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRL_APB_I2C0_REF_CTRL_DIVISOR0_DEFVAL 0x01000500 +#define CRL_APB_I2C0_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_I2C0_REF_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRL_APB_I2C0_REF_CTRL_SRCSEL_DEFVAL #undef CRL_APB_I2C0_REF_CTRL_SRCSEL_SHIFT #undef CRL_APB_I2C0_REF_CTRL_SRCSEL_MASK -#define CRL_APB_I2C0_REF_CTRL_SRCSEL_DEFVAL 0x01000500 -#define CRL_APB_I2C0_REF_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_I2C0_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRL_APB_I2C0_REF_CTRL_SRCSEL_DEFVAL 0x01000500 +#define CRL_APB_I2C0_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_I2C0_REF_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRL_APB_I2C1_REF_CTRL_CLKACT_DEFVAL #undef CRL_APB_I2C1_REF_CTRL_CLKACT_SHIFT #undef CRL_APB_I2C1_REF_CTRL_CLKACT_MASK -#define CRL_APB_I2C1_REF_CTRL_CLKACT_DEFVAL 0x01000500 -#define CRL_APB_I2C1_REF_CTRL_CLKACT_SHIFT 24 -#define CRL_APB_I2C1_REF_CTRL_CLKACT_MASK 0x01000000U +#define CRL_APB_I2C1_REF_CTRL_CLKACT_DEFVAL 0x01000500 +#define CRL_APB_I2C1_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_I2C1_REF_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_I2C1_REF_CTRL_DIVISOR1_DEFVAL #undef CRL_APB_I2C1_REF_CTRL_DIVISOR1_SHIFT #undef CRL_APB_I2C1_REF_CTRL_DIVISOR1_MASK -#define CRL_APB_I2C1_REF_CTRL_DIVISOR1_DEFVAL 0x01000500 -#define CRL_APB_I2C1_REF_CTRL_DIVISOR1_SHIFT 16 -#define CRL_APB_I2C1_REF_CTRL_DIVISOR1_MASK 0x003F0000U +#define CRL_APB_I2C1_REF_CTRL_DIVISOR1_DEFVAL 0x01000500 +#define CRL_APB_I2C1_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_I2C1_REF_CTRL_DIVISOR1_MASK 0x003F0000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_I2C1_REF_CTRL_DIVISOR0_DEFVAL #undef CRL_APB_I2C1_REF_CTRL_DIVISOR0_SHIFT #undef CRL_APB_I2C1_REF_CTRL_DIVISOR0_MASK -#define CRL_APB_I2C1_REF_CTRL_DIVISOR0_DEFVAL 0x01000500 -#define CRL_APB_I2C1_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_I2C1_REF_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRL_APB_I2C1_REF_CTRL_DIVISOR0_DEFVAL 0x01000500 +#define CRL_APB_I2C1_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_I2C1_REF_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRL_APB_I2C1_REF_CTRL_SRCSEL_DEFVAL #undef CRL_APB_I2C1_REF_CTRL_SRCSEL_SHIFT #undef CRL_APB_I2C1_REF_CTRL_SRCSEL_MASK -#define CRL_APB_I2C1_REF_CTRL_SRCSEL_DEFVAL 0x01000500 -#define CRL_APB_I2C1_REF_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_I2C1_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRL_APB_I2C1_REF_CTRL_SRCSEL_DEFVAL 0x01000500 +#define CRL_APB_I2C1_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_I2C1_REF_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRL_APB_CAN1_REF_CTRL_CLKACT_DEFVAL #undef CRL_APB_CAN1_REF_CTRL_CLKACT_SHIFT #undef CRL_APB_CAN1_REF_CTRL_CLKACT_MASK -#define CRL_APB_CAN1_REF_CTRL_CLKACT_DEFVAL 0x01001800 -#define CRL_APB_CAN1_REF_CTRL_CLKACT_SHIFT 24 -#define CRL_APB_CAN1_REF_CTRL_CLKACT_MASK 0x01000000U +#define CRL_APB_CAN1_REF_CTRL_CLKACT_DEFVAL 0x01001800 +#define CRL_APB_CAN1_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_CAN1_REF_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_CAN1_REF_CTRL_DIVISOR1_DEFVAL #undef CRL_APB_CAN1_REF_CTRL_DIVISOR1_SHIFT #undef CRL_APB_CAN1_REF_CTRL_DIVISOR1_MASK -#define CRL_APB_CAN1_REF_CTRL_DIVISOR1_DEFVAL 0x01001800 -#define CRL_APB_CAN1_REF_CTRL_DIVISOR1_SHIFT 16 -#define CRL_APB_CAN1_REF_CTRL_DIVISOR1_MASK 0x003F0000U +#define CRL_APB_CAN1_REF_CTRL_DIVISOR1_DEFVAL 0x01001800 +#define CRL_APB_CAN1_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_CAN1_REF_CTRL_DIVISOR1_MASK 0x003F0000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_CAN1_REF_CTRL_DIVISOR0_DEFVAL #undef CRL_APB_CAN1_REF_CTRL_DIVISOR0_SHIFT #undef CRL_APB_CAN1_REF_CTRL_DIVISOR0_MASK -#define CRL_APB_CAN1_REF_CTRL_DIVISOR0_DEFVAL 0x01001800 -#define CRL_APB_CAN1_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_CAN1_REF_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRL_APB_CAN1_REF_CTRL_DIVISOR0_DEFVAL 0x01001800 +#define CRL_APB_CAN1_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_CAN1_REF_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRL_APB_CAN1_REF_CTRL_SRCSEL_DEFVAL #undef CRL_APB_CAN1_REF_CTRL_SRCSEL_SHIFT #undef CRL_APB_CAN1_REF_CTRL_SRCSEL_MASK -#define CRL_APB_CAN1_REF_CTRL_SRCSEL_DEFVAL 0x01001800 -#define CRL_APB_CAN1_REF_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_CAN1_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRL_APB_CAN1_REF_CTRL_SRCSEL_DEFVAL 0x01001800 +#define CRL_APB_CAN1_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_CAN1_REF_CTRL_SRCSEL_MASK 0x00000007U -/*Turing this off will shut down the OCM, some parts of the APM, and prevent transactions going from the FPD to the LPD and cou - d lead to system hang*/ +/* +* Turing this off will shut down the OCM, some parts of the APM, and preve + * nt transactions going from the FPD to the LPD and could lead to system h + * ang +*/ #undef CRL_APB_CPU_R5_CTRL_CLKACT_DEFVAL #undef CRL_APB_CPU_R5_CTRL_CLKACT_SHIFT #undef CRL_APB_CPU_R5_CTRL_CLKACT_MASK -#define CRL_APB_CPU_R5_CTRL_CLKACT_DEFVAL 0x03000600 -#define CRL_APB_CPU_R5_CTRL_CLKACT_SHIFT 24 -#define CRL_APB_CPU_R5_CTRL_CLKACT_MASK 0x01000000U +#define CRL_APB_CPU_R5_CTRL_CLKACT_DEFVAL 0x03000600 +#define CRL_APB_CPU_R5_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_CPU_R5_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_CPU_R5_CTRL_DIVISOR0_DEFVAL #undef CRL_APB_CPU_R5_CTRL_DIVISOR0_SHIFT #undef CRL_APB_CPU_R5_CTRL_DIVISOR0_MASK -#define CRL_APB_CPU_R5_CTRL_DIVISOR0_DEFVAL 0x03000600 -#define CRL_APB_CPU_R5_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_CPU_R5_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRL_APB_CPU_R5_CTRL_DIVISOR0_DEFVAL 0x03000600 +#define CRL_APB_CPU_R5_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_CPU_R5_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRL_APB_CPU_R5_CTRL_SRCSEL_DEFVAL #undef CRL_APB_CPU_R5_CTRL_SRCSEL_SHIFT #undef CRL_APB_CPU_R5_CTRL_SRCSEL_MASK -#define CRL_APB_CPU_R5_CTRL_SRCSEL_DEFVAL 0x03000600 -#define CRL_APB_CPU_R5_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_CPU_R5_CTRL_SRCSEL_MASK 0x00000007U +#define CRL_APB_CPU_R5_CTRL_SRCSEL_DEFVAL 0x03000600 +#define CRL_APB_CPU_R5_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_CPU_R5_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRL_APB_IOU_SWITCH_CTRL_CLKACT_DEFVAL #undef CRL_APB_IOU_SWITCH_CTRL_CLKACT_SHIFT #undef CRL_APB_IOU_SWITCH_CTRL_CLKACT_MASK -#define CRL_APB_IOU_SWITCH_CTRL_CLKACT_DEFVAL 0x00001500 -#define CRL_APB_IOU_SWITCH_CTRL_CLKACT_SHIFT 24 -#define CRL_APB_IOU_SWITCH_CTRL_CLKACT_MASK 0x01000000U +#define CRL_APB_IOU_SWITCH_CTRL_CLKACT_DEFVAL 0x00001500 +#define CRL_APB_IOU_SWITCH_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_IOU_SWITCH_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_DEFVAL #undef CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_SHIFT #undef CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_MASK -#define CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_DEFVAL 0x00001500 -#define CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_DEFVAL 0x00001500 +#define CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRL_APB_IOU_SWITCH_CTRL_SRCSEL_DEFVAL #undef CRL_APB_IOU_SWITCH_CTRL_SRCSEL_SHIFT #undef CRL_APB_IOU_SWITCH_CTRL_SRCSEL_MASK -#define CRL_APB_IOU_SWITCH_CTRL_SRCSEL_DEFVAL 0x00001500 -#define CRL_APB_IOU_SWITCH_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_IOU_SWITCH_CTRL_SRCSEL_MASK 0x00000007U +#define CRL_APB_IOU_SWITCH_CTRL_SRCSEL_DEFVAL 0x00001500 +#define CRL_APB_IOU_SWITCH_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_IOU_SWITCH_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRL_APB_PCAP_CTRL_CLKACT_DEFVAL #undef CRL_APB_PCAP_CTRL_CLKACT_SHIFT #undef CRL_APB_PCAP_CTRL_CLKACT_MASK -#define CRL_APB_PCAP_CTRL_CLKACT_DEFVAL 0x00001500 -#define CRL_APB_PCAP_CTRL_CLKACT_SHIFT 24 -#define CRL_APB_PCAP_CTRL_CLKACT_MASK 0x01000000U +#define CRL_APB_PCAP_CTRL_CLKACT_DEFVAL 0x00001500 +#define CRL_APB_PCAP_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_PCAP_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_PCAP_CTRL_DIVISOR0_DEFVAL #undef CRL_APB_PCAP_CTRL_DIVISOR0_SHIFT #undef CRL_APB_PCAP_CTRL_DIVISOR0_MASK -#define CRL_APB_PCAP_CTRL_DIVISOR0_DEFVAL 0x00001500 -#define CRL_APB_PCAP_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_PCAP_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRL_APB_PCAP_CTRL_DIVISOR0_DEFVAL 0x00001500 +#define CRL_APB_PCAP_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_PCAP_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRL_APB_PCAP_CTRL_SRCSEL_DEFVAL #undef CRL_APB_PCAP_CTRL_SRCSEL_SHIFT #undef CRL_APB_PCAP_CTRL_SRCSEL_MASK -#define CRL_APB_PCAP_CTRL_SRCSEL_DEFVAL 0x00001500 -#define CRL_APB_PCAP_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_PCAP_CTRL_SRCSEL_MASK 0x00000007U +#define CRL_APB_PCAP_CTRL_SRCSEL_DEFVAL 0x00001500 +#define CRL_APB_PCAP_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_PCAP_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRL_APB_LPD_SWITCH_CTRL_CLKACT_DEFVAL #undef CRL_APB_LPD_SWITCH_CTRL_CLKACT_SHIFT #undef CRL_APB_LPD_SWITCH_CTRL_CLKACT_MASK -#define CRL_APB_LPD_SWITCH_CTRL_CLKACT_DEFVAL 0x01000500 -#define CRL_APB_LPD_SWITCH_CTRL_CLKACT_SHIFT 24 -#define CRL_APB_LPD_SWITCH_CTRL_CLKACT_MASK 0x01000000U +#define CRL_APB_LPD_SWITCH_CTRL_CLKACT_DEFVAL 0x01000500 +#define CRL_APB_LPD_SWITCH_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_LPD_SWITCH_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_DEFVAL #undef CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_SHIFT #undef CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_MASK -#define CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_DEFVAL 0x01000500 -#define CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_DEFVAL 0x01000500 +#define CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRL_APB_LPD_SWITCH_CTRL_SRCSEL_DEFVAL #undef CRL_APB_LPD_SWITCH_CTRL_SRCSEL_SHIFT #undef CRL_APB_LPD_SWITCH_CTRL_SRCSEL_MASK -#define CRL_APB_LPD_SWITCH_CTRL_SRCSEL_DEFVAL 0x01000500 -#define CRL_APB_LPD_SWITCH_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_LPD_SWITCH_CTRL_SRCSEL_MASK 0x00000007U +#define CRL_APB_LPD_SWITCH_CTRL_SRCSEL_DEFVAL 0x01000500 +#define CRL_APB_LPD_SWITCH_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_LPD_SWITCH_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRL_APB_LPD_LSBUS_CTRL_CLKACT_DEFVAL #undef CRL_APB_LPD_LSBUS_CTRL_CLKACT_SHIFT #undef CRL_APB_LPD_LSBUS_CTRL_CLKACT_MASK -#define CRL_APB_LPD_LSBUS_CTRL_CLKACT_DEFVAL 0x01001800 -#define CRL_APB_LPD_LSBUS_CTRL_CLKACT_SHIFT 24 -#define CRL_APB_LPD_LSBUS_CTRL_CLKACT_MASK 0x01000000U +#define CRL_APB_LPD_LSBUS_CTRL_CLKACT_DEFVAL 0x01001800 +#define CRL_APB_LPD_LSBUS_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_LPD_LSBUS_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_DEFVAL #undef CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_SHIFT #undef CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_MASK -#define CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_DEFVAL 0x01001800 -#define CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_DEFVAL 0x01001800 +#define CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRL_APB_LPD_LSBUS_CTRL_SRCSEL_DEFVAL #undef CRL_APB_LPD_LSBUS_CTRL_SRCSEL_SHIFT #undef CRL_APB_LPD_LSBUS_CTRL_SRCSEL_MASK -#define CRL_APB_LPD_LSBUS_CTRL_SRCSEL_DEFVAL 0x01001800 -#define CRL_APB_LPD_LSBUS_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_LPD_LSBUS_CTRL_SRCSEL_MASK 0x00000007U +#define CRL_APB_LPD_LSBUS_CTRL_SRCSEL_DEFVAL 0x01001800 +#define CRL_APB_LPD_LSBUS_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_LPD_LSBUS_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRL_APB_DBG_LPD_CTRL_CLKACT_DEFVAL #undef CRL_APB_DBG_LPD_CTRL_CLKACT_SHIFT #undef CRL_APB_DBG_LPD_CTRL_CLKACT_MASK -#define CRL_APB_DBG_LPD_CTRL_CLKACT_DEFVAL 0x01002000 -#define CRL_APB_DBG_LPD_CTRL_CLKACT_SHIFT 24 -#define CRL_APB_DBG_LPD_CTRL_CLKACT_MASK 0x01000000U +#define CRL_APB_DBG_LPD_CTRL_CLKACT_DEFVAL 0x01002000 +#define CRL_APB_DBG_LPD_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_DBG_LPD_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_DBG_LPD_CTRL_DIVISOR0_DEFVAL #undef CRL_APB_DBG_LPD_CTRL_DIVISOR0_SHIFT #undef CRL_APB_DBG_LPD_CTRL_DIVISOR0_MASK -#define CRL_APB_DBG_LPD_CTRL_DIVISOR0_DEFVAL 0x01002000 -#define CRL_APB_DBG_LPD_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_DBG_LPD_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRL_APB_DBG_LPD_CTRL_DIVISOR0_DEFVAL 0x01002000 +#define CRL_APB_DBG_LPD_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_DBG_LPD_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRL_APB_DBG_LPD_CTRL_SRCSEL_DEFVAL #undef CRL_APB_DBG_LPD_CTRL_SRCSEL_SHIFT #undef CRL_APB_DBG_LPD_CTRL_SRCSEL_MASK -#define CRL_APB_DBG_LPD_CTRL_SRCSEL_DEFVAL 0x01002000 -#define CRL_APB_DBG_LPD_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_DBG_LPD_CTRL_SRCSEL_MASK 0x00000007U +#define CRL_APB_DBG_LPD_CTRL_SRCSEL_DEFVAL 0x01002000 +#define CRL_APB_DBG_LPD_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_DBG_LPD_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRL_APB_ADMA_REF_CTRL_CLKACT_DEFVAL #undef CRL_APB_ADMA_REF_CTRL_CLKACT_SHIFT #undef CRL_APB_ADMA_REF_CTRL_CLKACT_MASK -#define CRL_APB_ADMA_REF_CTRL_CLKACT_DEFVAL 0x00002000 -#define CRL_APB_ADMA_REF_CTRL_CLKACT_SHIFT 24 -#define CRL_APB_ADMA_REF_CTRL_CLKACT_MASK 0x01000000U +#define CRL_APB_ADMA_REF_CTRL_CLKACT_DEFVAL 0x00002000 +#define CRL_APB_ADMA_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_ADMA_REF_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_ADMA_REF_CTRL_DIVISOR0_DEFVAL #undef CRL_APB_ADMA_REF_CTRL_DIVISOR0_SHIFT #undef CRL_APB_ADMA_REF_CTRL_DIVISOR0_MASK -#define CRL_APB_ADMA_REF_CTRL_DIVISOR0_DEFVAL 0x00002000 -#define CRL_APB_ADMA_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_ADMA_REF_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRL_APB_ADMA_REF_CTRL_DIVISOR0_DEFVAL 0x00002000 +#define CRL_APB_ADMA_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_ADMA_REF_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRL_APB_ADMA_REF_CTRL_SRCSEL_DEFVAL #undef CRL_APB_ADMA_REF_CTRL_SRCSEL_SHIFT #undef CRL_APB_ADMA_REF_CTRL_SRCSEL_MASK -#define CRL_APB_ADMA_REF_CTRL_SRCSEL_DEFVAL 0x00002000 -#define CRL_APB_ADMA_REF_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_ADMA_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRL_APB_ADMA_REF_CTRL_SRCSEL_DEFVAL 0x00002000 +#define CRL_APB_ADMA_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_ADMA_REF_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRL_APB_PL0_REF_CTRL_CLKACT_DEFVAL #undef CRL_APB_PL0_REF_CTRL_CLKACT_SHIFT #undef CRL_APB_PL0_REF_CTRL_CLKACT_MASK -#define CRL_APB_PL0_REF_CTRL_CLKACT_DEFVAL 0x00052000 -#define CRL_APB_PL0_REF_CTRL_CLKACT_SHIFT 24 -#define CRL_APB_PL0_REF_CTRL_CLKACT_MASK 0x01000000U +#define CRL_APB_PL0_REF_CTRL_CLKACT_DEFVAL 0x00052000 +#define CRL_APB_PL0_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_PL0_REF_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_PL0_REF_CTRL_DIVISOR1_DEFVAL #undef CRL_APB_PL0_REF_CTRL_DIVISOR1_SHIFT #undef CRL_APB_PL0_REF_CTRL_DIVISOR1_MASK -#define CRL_APB_PL0_REF_CTRL_DIVISOR1_DEFVAL 0x00052000 -#define CRL_APB_PL0_REF_CTRL_DIVISOR1_SHIFT 16 -#define CRL_APB_PL0_REF_CTRL_DIVISOR1_MASK 0x003F0000U +#define CRL_APB_PL0_REF_CTRL_DIVISOR1_DEFVAL 0x00052000 +#define CRL_APB_PL0_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_PL0_REF_CTRL_DIVISOR1_MASK 0x003F0000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_PL0_REF_CTRL_DIVISOR0_DEFVAL #undef CRL_APB_PL0_REF_CTRL_DIVISOR0_SHIFT #undef CRL_APB_PL0_REF_CTRL_DIVISOR0_MASK -#define CRL_APB_PL0_REF_CTRL_DIVISOR0_DEFVAL 0x00052000 -#define CRL_APB_PL0_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_PL0_REF_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRL_APB_PL0_REF_CTRL_DIVISOR0_DEFVAL 0x00052000 +#define CRL_APB_PL0_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_PL0_REF_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRL_APB_PL0_REF_CTRL_SRCSEL_DEFVAL #undef CRL_APB_PL0_REF_CTRL_SRCSEL_SHIFT #undef CRL_APB_PL0_REF_CTRL_SRCSEL_MASK -#define CRL_APB_PL0_REF_CTRL_SRCSEL_DEFVAL 0x00052000 -#define CRL_APB_PL0_REF_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_PL0_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRL_APB_PL0_REF_CTRL_SRCSEL_DEFVAL 0x00052000 +#define CRL_APB_PL0_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_PL0_REF_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ -#undef CRL_APB_PL1_REF_CTRL_CLKACT_DEFVAL -#undef CRL_APB_PL1_REF_CTRL_CLKACT_SHIFT -#undef CRL_APB_PL1_REF_CTRL_CLKACT_MASK -#define CRL_APB_PL1_REF_CTRL_CLKACT_DEFVAL 0x00052000 -#define CRL_APB_PL1_REF_CTRL_CLKACT_SHIFT 24 -#define CRL_APB_PL1_REF_CTRL_CLKACT_MASK 0x01000000U - -/*6 bit divider*/ -#undef CRL_APB_PL1_REF_CTRL_DIVISOR1_DEFVAL -#undef CRL_APB_PL1_REF_CTRL_DIVISOR1_SHIFT -#undef CRL_APB_PL1_REF_CTRL_DIVISOR1_MASK -#define CRL_APB_PL1_REF_CTRL_DIVISOR1_DEFVAL 0x00052000 -#define CRL_APB_PL1_REF_CTRL_DIVISOR1_SHIFT 16 -#define CRL_APB_PL1_REF_CTRL_DIVISOR1_MASK 0x003F0000U - -/*6 bit divider*/ -#undef CRL_APB_PL1_REF_CTRL_DIVISOR0_DEFVAL -#undef CRL_APB_PL1_REF_CTRL_DIVISOR0_SHIFT -#undef CRL_APB_PL1_REF_CTRL_DIVISOR0_MASK -#define CRL_APB_PL1_REF_CTRL_DIVISOR0_DEFVAL 0x00052000 -#define CRL_APB_PL1_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_PL1_REF_CTRL_DIVISOR0_MASK 0x00003F00U - -/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.)*/ -#undef CRL_APB_PL1_REF_CTRL_SRCSEL_DEFVAL -#undef CRL_APB_PL1_REF_CTRL_SRCSEL_SHIFT -#undef CRL_APB_PL1_REF_CTRL_SRCSEL_MASK -#define CRL_APB_PL1_REF_CTRL_SRCSEL_DEFVAL 0x00052000 -#define CRL_APB_PL1_REF_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_PL1_REF_CTRL_SRCSEL_MASK 0x00000007U - -/*Clock active signal. Switch to 0 to disable the clock*/ -#undef CRL_APB_PL2_REF_CTRL_CLKACT_DEFVAL -#undef CRL_APB_PL2_REF_CTRL_CLKACT_SHIFT -#undef CRL_APB_PL2_REF_CTRL_CLKACT_MASK -#define CRL_APB_PL2_REF_CTRL_CLKACT_DEFVAL 0x00052000 -#define CRL_APB_PL2_REF_CTRL_CLKACT_SHIFT 24 -#define CRL_APB_PL2_REF_CTRL_CLKACT_MASK 0x01000000U - -/*6 bit divider*/ -#undef CRL_APB_PL2_REF_CTRL_DIVISOR1_DEFVAL -#undef CRL_APB_PL2_REF_CTRL_DIVISOR1_SHIFT -#undef CRL_APB_PL2_REF_CTRL_DIVISOR1_MASK -#define CRL_APB_PL2_REF_CTRL_DIVISOR1_DEFVAL 0x00052000 -#define CRL_APB_PL2_REF_CTRL_DIVISOR1_SHIFT 16 -#define CRL_APB_PL2_REF_CTRL_DIVISOR1_MASK 0x003F0000U - -/*6 bit divider*/ -#undef CRL_APB_PL2_REF_CTRL_DIVISOR0_DEFVAL -#undef CRL_APB_PL2_REF_CTRL_DIVISOR0_SHIFT -#undef CRL_APB_PL2_REF_CTRL_DIVISOR0_MASK -#define CRL_APB_PL2_REF_CTRL_DIVISOR0_DEFVAL 0x00052000 -#define CRL_APB_PL2_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_PL2_REF_CTRL_DIVISOR0_MASK 0x00003F00U - -/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.)*/ -#undef CRL_APB_PL2_REF_CTRL_SRCSEL_DEFVAL -#undef CRL_APB_PL2_REF_CTRL_SRCSEL_SHIFT -#undef CRL_APB_PL2_REF_CTRL_SRCSEL_MASK -#define CRL_APB_PL2_REF_CTRL_SRCSEL_DEFVAL 0x00052000 -#define CRL_APB_PL2_REF_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_PL2_REF_CTRL_SRCSEL_MASK 0x00000007U - -/*Clock active signal. Switch to 0 to disable the clock*/ -#undef CRL_APB_PL3_REF_CTRL_CLKACT_DEFVAL -#undef CRL_APB_PL3_REF_CTRL_CLKACT_SHIFT -#undef CRL_APB_PL3_REF_CTRL_CLKACT_MASK -#define CRL_APB_PL3_REF_CTRL_CLKACT_DEFVAL 0x00052000 -#define CRL_APB_PL3_REF_CTRL_CLKACT_SHIFT 24 -#define CRL_APB_PL3_REF_CTRL_CLKACT_MASK 0x01000000U - -/*6 bit divider*/ -#undef CRL_APB_PL3_REF_CTRL_DIVISOR1_DEFVAL -#undef CRL_APB_PL3_REF_CTRL_DIVISOR1_SHIFT -#undef CRL_APB_PL3_REF_CTRL_DIVISOR1_MASK -#define CRL_APB_PL3_REF_CTRL_DIVISOR1_DEFVAL 0x00052000 -#define CRL_APB_PL3_REF_CTRL_DIVISOR1_SHIFT 16 -#define CRL_APB_PL3_REF_CTRL_DIVISOR1_MASK 0x003F0000U - -/*6 bit divider*/ -#undef CRL_APB_PL3_REF_CTRL_DIVISOR0_DEFVAL -#undef CRL_APB_PL3_REF_CTRL_DIVISOR0_SHIFT -#undef CRL_APB_PL3_REF_CTRL_DIVISOR0_MASK -#define CRL_APB_PL3_REF_CTRL_DIVISOR0_DEFVAL 0x00052000 -#define CRL_APB_PL3_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_PL3_REF_CTRL_DIVISOR0_MASK 0x00003F00U - -/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.)*/ -#undef CRL_APB_PL3_REF_CTRL_SRCSEL_DEFVAL -#undef CRL_APB_PL3_REF_CTRL_SRCSEL_SHIFT -#undef CRL_APB_PL3_REF_CTRL_SRCSEL_MASK -#define CRL_APB_PL3_REF_CTRL_SRCSEL_DEFVAL 0x00052000 -#define CRL_APB_PL3_REF_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_PL3_REF_CTRL_SRCSEL_MASK 0x00000007U - -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_AMS_REF_CTRL_DIVISOR1_DEFVAL #undef CRL_APB_AMS_REF_CTRL_DIVISOR1_SHIFT #undef CRL_APB_AMS_REF_CTRL_DIVISOR1_MASK -#define CRL_APB_AMS_REF_CTRL_DIVISOR1_DEFVAL 0x01001800 -#define CRL_APB_AMS_REF_CTRL_DIVISOR1_SHIFT 16 -#define CRL_APB_AMS_REF_CTRL_DIVISOR1_MASK 0x003F0000U +#define CRL_APB_AMS_REF_CTRL_DIVISOR1_DEFVAL 0x01001800 +#define CRL_APB_AMS_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_AMS_REF_CTRL_DIVISOR1_MASK 0x003F0000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_AMS_REF_CTRL_DIVISOR0_DEFVAL #undef CRL_APB_AMS_REF_CTRL_DIVISOR0_SHIFT #undef CRL_APB_AMS_REF_CTRL_DIVISOR0_MASK -#define CRL_APB_AMS_REF_CTRL_DIVISOR0_DEFVAL 0x01001800 -#define CRL_APB_AMS_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_AMS_REF_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRL_APB_AMS_REF_CTRL_DIVISOR0_DEFVAL 0x01001800 +#define CRL_APB_AMS_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_AMS_REF_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRL_APB_AMS_REF_CTRL_SRCSEL_DEFVAL #undef CRL_APB_AMS_REF_CTRL_SRCSEL_SHIFT #undef CRL_APB_AMS_REF_CTRL_SRCSEL_MASK -#define CRL_APB_AMS_REF_CTRL_SRCSEL_DEFVAL 0x01001800 -#define CRL_APB_AMS_REF_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_AMS_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRL_APB_AMS_REF_CTRL_SRCSEL_DEFVAL 0x01001800 +#define CRL_APB_AMS_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_AMS_REF_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRL_APB_AMS_REF_CTRL_CLKACT_DEFVAL #undef CRL_APB_AMS_REF_CTRL_CLKACT_SHIFT #undef CRL_APB_AMS_REF_CTRL_CLKACT_MASK -#define CRL_APB_AMS_REF_CTRL_CLKACT_DEFVAL 0x01001800 -#define CRL_APB_AMS_REF_CTRL_CLKACT_SHIFT 24 -#define CRL_APB_AMS_REF_CTRL_CLKACT_MASK 0x01000000U +#define CRL_APB_AMS_REF_CTRL_CLKACT_DEFVAL 0x01001800 +#define CRL_APB_AMS_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_AMS_REF_CTRL_CLKACT_MASK 0x01000000U -/*000 = IOPLL; 001 = RPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This - is not usually an issue, but designers must be aware.)*/ +/* +* 000 = IOPLL; 001 = RPLL; (This signal may only be toggled after 4 cycles + * of the old clock and 4 cycles of the new clock. This is not usually an + * issue, but designers must be aware.) +*/ #undef CRL_APB_DLL_REF_CTRL_SRCSEL_DEFVAL #undef CRL_APB_DLL_REF_CTRL_SRCSEL_SHIFT #undef CRL_APB_DLL_REF_CTRL_SRCSEL_MASK -#define CRL_APB_DLL_REF_CTRL_SRCSEL_DEFVAL 0x00000000 -#define CRL_APB_DLL_REF_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_DLL_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRL_APB_DLL_REF_CTRL_SRCSEL_DEFVAL 0x00000000 +#define CRL_APB_DLL_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_DLL_REF_CTRL_SRCSEL_MASK 0x00000007U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_DEFVAL #undef CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_SHIFT #undef CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_MASK -#define CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_DEFVAL 0x00001800 -#define CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_DEFVAL 0x00001800 +#define CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_MASK 0x00003F00U -/*1XX = pss_ref_clk; 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and - cycles of the new clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 1XX = pss_ref_clk; 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may + * only be toggled after 4 cycles of the old clock and 4 cycles of the new + * clock. This is not usually an issue, but designers must be aware.) +*/ #undef CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_DEFVAL #undef CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_SHIFT #undef CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_MASK -#define CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_DEFVAL 0x00001800 -#define CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_DEFVAL 0x00001800 +#define CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_DEFVAL #undef CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_SHIFT #undef CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_MASK -#define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_DEFVAL 0x00001800 -#define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_SHIFT 24 -#define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_MASK 0x01000000U +#define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_DEFVAL 0x00001800 +#define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_MASK 0x01000000U -/*000 = IOPLL_TO_FPD; 010 = APLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of - he new clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = IOPLL_TO_FPD; 010 = APLL; 011 = DPLL; (This signal may only be tog + * gled after 4 cycles of the old clock and 4 cycles of the new clock. This + * is not usually an issue, but designers must be aware.) +*/ #undef CRF_APB_SATA_REF_CTRL_SRCSEL_DEFVAL #undef CRF_APB_SATA_REF_CTRL_SRCSEL_SHIFT #undef CRF_APB_SATA_REF_CTRL_SRCSEL_MASK -#define CRF_APB_SATA_REF_CTRL_SRCSEL_DEFVAL 0x01001600 -#define CRF_APB_SATA_REF_CTRL_SRCSEL_SHIFT 0 -#define CRF_APB_SATA_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRF_APB_SATA_REF_CTRL_SRCSEL_DEFVAL 0x01001600 +#define CRF_APB_SATA_REF_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_SATA_REF_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRF_APB_SATA_REF_CTRL_CLKACT_DEFVAL #undef CRF_APB_SATA_REF_CTRL_CLKACT_SHIFT #undef CRF_APB_SATA_REF_CTRL_CLKACT_MASK -#define CRF_APB_SATA_REF_CTRL_CLKACT_DEFVAL 0x01001600 -#define CRF_APB_SATA_REF_CTRL_CLKACT_SHIFT 24 -#define CRF_APB_SATA_REF_CTRL_CLKACT_MASK 0x01000000U +#define CRF_APB_SATA_REF_CTRL_CLKACT_DEFVAL 0x01001600 +#define CRF_APB_SATA_REF_CTRL_CLKACT_SHIFT 24 +#define CRF_APB_SATA_REF_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRF_APB_SATA_REF_CTRL_DIVISOR0_DEFVAL #undef CRF_APB_SATA_REF_CTRL_DIVISOR0_SHIFT #undef CRF_APB_SATA_REF_CTRL_DIVISOR0_MASK -#define CRF_APB_SATA_REF_CTRL_DIVISOR0_DEFVAL 0x01001600 -#define CRF_APB_SATA_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRF_APB_SATA_REF_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRF_APB_SATA_REF_CTRL_DIVISOR0_DEFVAL 0x01001600 +#define CRF_APB_SATA_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_SATA_REF_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = IOPLL_TO_FPD; 010 = RPLL_TO_FPD; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cyc - es of the new clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = IOPLL_TO_FPD; 010 = RPLL_TO_FPD; 011 = DPLL; (This signal may only + * be toggled after 4 cycles of the old clock and 4 cycles of the new cloc + * k. This is not usually an issue, but designers must be aware.) +*/ #undef CRF_APB_PCIE_REF_CTRL_SRCSEL_DEFVAL #undef CRF_APB_PCIE_REF_CTRL_SRCSEL_SHIFT #undef CRF_APB_PCIE_REF_CTRL_SRCSEL_MASK -#define CRF_APB_PCIE_REF_CTRL_SRCSEL_DEFVAL 0x00001500 -#define CRF_APB_PCIE_REF_CTRL_SRCSEL_SHIFT 0 -#define CRF_APB_PCIE_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRF_APB_PCIE_REF_CTRL_SRCSEL_DEFVAL 0x00001500 +#define CRF_APB_PCIE_REF_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_PCIE_REF_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRF_APB_PCIE_REF_CTRL_CLKACT_DEFVAL #undef CRF_APB_PCIE_REF_CTRL_CLKACT_SHIFT #undef CRF_APB_PCIE_REF_CTRL_CLKACT_MASK -#define CRF_APB_PCIE_REF_CTRL_CLKACT_DEFVAL 0x00001500 -#define CRF_APB_PCIE_REF_CTRL_CLKACT_SHIFT 24 -#define CRF_APB_PCIE_REF_CTRL_CLKACT_MASK 0x01000000U +#define CRF_APB_PCIE_REF_CTRL_CLKACT_DEFVAL 0x00001500 +#define CRF_APB_PCIE_REF_CTRL_CLKACT_SHIFT 24 +#define CRF_APB_PCIE_REF_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRF_APB_PCIE_REF_CTRL_DIVISOR0_DEFVAL #undef CRF_APB_PCIE_REF_CTRL_DIVISOR0_SHIFT #undef CRF_APB_PCIE_REF_CTRL_DIVISOR0_MASK -#define CRF_APB_PCIE_REF_CTRL_DIVISOR0_DEFVAL 0x00001500 -#define CRF_APB_PCIE_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRF_APB_PCIE_REF_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRF_APB_PCIE_REF_CTRL_DIVISOR0_DEFVAL 0x00001500 +#define CRF_APB_PCIE_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_PCIE_REF_CTRL_DIVISOR0_MASK 0x00003F00U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_DEFVAL #undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_SHIFT #undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_MASK -#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_DEFVAL 0x01002300 -#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_SHIFT 16 -#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_MASK 0x003F0000U +#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_DEFVAL 0x01002300 +#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_MASK 0x003F0000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_DEFVAL #undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_SHIFT #undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_MASK -#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_DEFVAL 0x01002300 -#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_DEFVAL 0x01002300 +#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (This signal may only be toggled after 4 cycles of the - ld clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (T + * his signal may only be toggled after 4 cycles of the old clock and 4 cyc + * les of the new clock. This is not usually an issue, but designers must b + * e aware.) +*/ #undef CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_DEFVAL #undef CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_SHIFT #undef CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_MASK -#define CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_DEFVAL 0x01002300 -#define CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_SHIFT 0 -#define CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_DEFVAL 0x01002300 +#define CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_DEFVAL #undef CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_SHIFT #undef CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_MASK -#define CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_DEFVAL 0x01002300 -#define CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_SHIFT 24 -#define CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_MASK 0x01000000U +#define CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_DEFVAL 0x01002300 +#define CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_SHIFT 24 +#define CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_DEFVAL #undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_SHIFT #undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_MASK -#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_DEFVAL 0x01032300 -#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_SHIFT 16 -#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_MASK 0x003F0000U +#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_DEFVAL 0x01032300 +#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_MASK 0x003F0000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_DEFVAL #undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_SHIFT #undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_MASK -#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_DEFVAL 0x01032300 -#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_DEFVAL 0x01032300 +#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (This signal may only be toggled after 4 cycles of the - ld clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (T + * his signal may only be toggled after 4 cycles of the old clock and 4 cyc + * les of the new clock. This is not usually an issue, but designers must b + * e aware.) +*/ #undef CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_DEFVAL #undef CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_SHIFT #undef CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_MASK -#define CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_DEFVAL 0x01032300 -#define CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_SHIFT 0 -#define CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_DEFVAL 0x01032300 +#define CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_DEFVAL #undef CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_SHIFT #undef CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_MASK -#define CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_DEFVAL 0x01032300 -#define CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_SHIFT 24 -#define CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_MASK 0x01000000U +#define CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_DEFVAL 0x01032300 +#define CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_SHIFT 24 +#define CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRF_APB_DP_STC_REF_CTRL_DIVISOR1_DEFVAL #undef CRF_APB_DP_STC_REF_CTRL_DIVISOR1_SHIFT #undef CRF_APB_DP_STC_REF_CTRL_DIVISOR1_MASK -#define CRF_APB_DP_STC_REF_CTRL_DIVISOR1_DEFVAL 0x01203200 -#define CRF_APB_DP_STC_REF_CTRL_DIVISOR1_SHIFT 16 -#define CRF_APB_DP_STC_REF_CTRL_DIVISOR1_MASK 0x003F0000U +#define CRF_APB_DP_STC_REF_CTRL_DIVISOR1_DEFVAL 0x01203200 +#define CRF_APB_DP_STC_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRF_APB_DP_STC_REF_CTRL_DIVISOR1_MASK 0x003F0000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRF_APB_DP_STC_REF_CTRL_DIVISOR0_DEFVAL #undef CRF_APB_DP_STC_REF_CTRL_DIVISOR0_SHIFT #undef CRF_APB_DP_STC_REF_CTRL_DIVISOR0_MASK -#define CRF_APB_DP_STC_REF_CTRL_DIVISOR0_DEFVAL 0x01203200 -#define CRF_APB_DP_STC_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRF_APB_DP_STC_REF_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRF_APB_DP_STC_REF_CTRL_DIVISOR0_DEFVAL 0x01203200 +#define CRF_APB_DP_STC_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_DP_STC_REF_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of t - e new clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD; (This signal may only be togg + * led after 4 cycles of the old clock and 4 cycles of the new clock. This + * is not usually an issue, but designers must be aware.) +*/ #undef CRF_APB_DP_STC_REF_CTRL_SRCSEL_DEFVAL #undef CRF_APB_DP_STC_REF_CTRL_SRCSEL_SHIFT #undef CRF_APB_DP_STC_REF_CTRL_SRCSEL_MASK -#define CRF_APB_DP_STC_REF_CTRL_SRCSEL_DEFVAL 0x01203200 -#define CRF_APB_DP_STC_REF_CTRL_SRCSEL_SHIFT 0 -#define CRF_APB_DP_STC_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRF_APB_DP_STC_REF_CTRL_SRCSEL_DEFVAL 0x01203200 +#define CRF_APB_DP_STC_REF_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_DP_STC_REF_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRF_APB_DP_STC_REF_CTRL_CLKACT_DEFVAL #undef CRF_APB_DP_STC_REF_CTRL_CLKACT_SHIFT #undef CRF_APB_DP_STC_REF_CTRL_CLKACT_MASK -#define CRF_APB_DP_STC_REF_CTRL_CLKACT_DEFVAL 0x01203200 -#define CRF_APB_DP_STC_REF_CTRL_CLKACT_SHIFT 24 -#define CRF_APB_DP_STC_REF_CTRL_CLKACT_MASK 0x01000000U +#define CRF_APB_DP_STC_REF_CTRL_CLKACT_DEFVAL 0x01203200 +#define CRF_APB_DP_STC_REF_CTRL_CLKACT_SHIFT 24 +#define CRF_APB_DP_STC_REF_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRF_APB_ACPU_CTRL_DIVISOR0_DEFVAL #undef CRF_APB_ACPU_CTRL_DIVISOR0_SHIFT #undef CRF_APB_ACPU_CTRL_DIVISOR0_MASK -#define CRF_APB_ACPU_CTRL_DIVISOR0_DEFVAL 0x03000400 -#define CRF_APB_ACPU_CTRL_DIVISOR0_SHIFT 8 -#define CRF_APB_ACPU_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRF_APB_ACPU_CTRL_DIVISOR0_DEFVAL 0x03000400 +#define CRF_APB_ACPU_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_ACPU_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = APLL; 010 = DPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - lock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = APLL; 010 = DPLL; 011 = VPLL; (This signal may only be toggled aft + * er 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRF_APB_ACPU_CTRL_SRCSEL_DEFVAL #undef CRF_APB_ACPU_CTRL_SRCSEL_SHIFT #undef CRF_APB_ACPU_CTRL_SRCSEL_MASK -#define CRF_APB_ACPU_CTRL_SRCSEL_DEFVAL 0x03000400 -#define CRF_APB_ACPU_CTRL_SRCSEL_SHIFT 0 -#define CRF_APB_ACPU_CTRL_SRCSEL_MASK 0x00000007U +#define CRF_APB_ACPU_CTRL_SRCSEL_DEFVAL 0x03000400 +#define CRF_APB_ACPU_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_ACPU_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock. For the half speed APU Clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock. For the half spee + * d APU Clock +*/ #undef CRF_APB_ACPU_CTRL_CLKACT_HALF_DEFVAL #undef CRF_APB_ACPU_CTRL_CLKACT_HALF_SHIFT #undef CRF_APB_ACPU_CTRL_CLKACT_HALF_MASK -#define CRF_APB_ACPU_CTRL_CLKACT_HALF_DEFVAL 0x03000400 -#define CRF_APB_ACPU_CTRL_CLKACT_HALF_SHIFT 25 -#define CRF_APB_ACPU_CTRL_CLKACT_HALF_MASK 0x02000000U +#define CRF_APB_ACPU_CTRL_CLKACT_HALF_DEFVAL 0x03000400 +#define CRF_APB_ACPU_CTRL_CLKACT_HALF_SHIFT 25 +#define CRF_APB_ACPU_CTRL_CLKACT_HALF_MASK 0x02000000U -/*Clock active signal. Switch to 0 to disable the clock. For the full speed ACPUX Clock. This will shut off the high speed cloc - to the entire APU*/ +/* +* Clock active signal. Switch to 0 to disable the clock. For the full spee + * d ACPUX Clock. This will shut off the high speed clock to the entire APU +*/ #undef CRF_APB_ACPU_CTRL_CLKACT_FULL_DEFVAL #undef CRF_APB_ACPU_CTRL_CLKACT_FULL_SHIFT #undef CRF_APB_ACPU_CTRL_CLKACT_FULL_MASK -#define CRF_APB_ACPU_CTRL_CLKACT_FULL_DEFVAL 0x03000400 -#define CRF_APB_ACPU_CTRL_CLKACT_FULL_SHIFT 24 -#define CRF_APB_ACPU_CTRL_CLKACT_FULL_MASK 0x01000000U +#define CRF_APB_ACPU_CTRL_CLKACT_FULL_DEFVAL 0x03000400 +#define CRF_APB_ACPU_CTRL_CLKACT_FULL_SHIFT 24 +#define CRF_APB_ACPU_CTRL_CLKACT_FULL_MASK 0x01000000U -/*6 bit divider*/ -#undef CRF_APB_DBG_TRACE_CTRL_DIVISOR0_DEFVAL -#undef CRF_APB_DBG_TRACE_CTRL_DIVISOR0_SHIFT -#undef CRF_APB_DBG_TRACE_CTRL_DIVISOR0_MASK -#define CRF_APB_DBG_TRACE_CTRL_DIVISOR0_DEFVAL 0x00002500 -#define CRF_APB_DBG_TRACE_CTRL_DIVISOR0_SHIFT 8 -#define CRF_APB_DBG_TRACE_CTRL_DIVISOR0_MASK 0x00003F00U - -/*000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of - he new clock. This is not usually an issue, but designers must be aware.)*/ -#undef CRF_APB_DBG_TRACE_CTRL_SRCSEL_DEFVAL -#undef CRF_APB_DBG_TRACE_CTRL_SRCSEL_SHIFT -#undef CRF_APB_DBG_TRACE_CTRL_SRCSEL_MASK -#define CRF_APB_DBG_TRACE_CTRL_SRCSEL_DEFVAL 0x00002500 -#define CRF_APB_DBG_TRACE_CTRL_SRCSEL_SHIFT 0 -#define CRF_APB_DBG_TRACE_CTRL_SRCSEL_MASK 0x00000007U - -/*Clock active signal. Switch to 0 to disable the clock*/ -#undef CRF_APB_DBG_TRACE_CTRL_CLKACT_DEFVAL -#undef CRF_APB_DBG_TRACE_CTRL_CLKACT_SHIFT -#undef CRF_APB_DBG_TRACE_CTRL_CLKACT_MASK -#define CRF_APB_DBG_TRACE_CTRL_CLKACT_DEFVAL 0x00002500 -#define CRF_APB_DBG_TRACE_CTRL_CLKACT_SHIFT 24 -#define CRF_APB_DBG_TRACE_CTRL_CLKACT_MASK 0x01000000U - -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRF_APB_DBG_FPD_CTRL_DIVISOR0_DEFVAL #undef CRF_APB_DBG_FPD_CTRL_DIVISOR0_SHIFT #undef CRF_APB_DBG_FPD_CTRL_DIVISOR0_MASK -#define CRF_APB_DBG_FPD_CTRL_DIVISOR0_DEFVAL 0x01002500 -#define CRF_APB_DBG_FPD_CTRL_DIVISOR0_SHIFT 8 -#define CRF_APB_DBG_FPD_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRF_APB_DBG_FPD_CTRL_DIVISOR0_DEFVAL 0x01002500 +#define CRF_APB_DBG_FPD_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_DBG_FPD_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of - he new clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be tog + * gled after 4 cycles of the old clock and 4 cycles of the new clock. This + * is not usually an issue, but designers must be aware.) +*/ #undef CRF_APB_DBG_FPD_CTRL_SRCSEL_DEFVAL #undef CRF_APB_DBG_FPD_CTRL_SRCSEL_SHIFT #undef CRF_APB_DBG_FPD_CTRL_SRCSEL_MASK -#define CRF_APB_DBG_FPD_CTRL_SRCSEL_DEFVAL 0x01002500 -#define CRF_APB_DBG_FPD_CTRL_SRCSEL_SHIFT 0 -#define CRF_APB_DBG_FPD_CTRL_SRCSEL_MASK 0x00000007U +#define CRF_APB_DBG_FPD_CTRL_SRCSEL_DEFVAL 0x01002500 +#define CRF_APB_DBG_FPD_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_DBG_FPD_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRF_APB_DBG_FPD_CTRL_CLKACT_DEFVAL #undef CRF_APB_DBG_FPD_CTRL_CLKACT_SHIFT #undef CRF_APB_DBG_FPD_CTRL_CLKACT_MASK -#define CRF_APB_DBG_FPD_CTRL_CLKACT_DEFVAL 0x01002500 -#define CRF_APB_DBG_FPD_CTRL_CLKACT_SHIFT 24 -#define CRF_APB_DBG_FPD_CTRL_CLKACT_MASK 0x01000000U +#define CRF_APB_DBG_FPD_CTRL_CLKACT_DEFVAL 0x01002500 +#define CRF_APB_DBG_FPD_CTRL_CLKACT_SHIFT 24 +#define CRF_APB_DBG_FPD_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRF_APB_DDR_CTRL_DIVISOR0_DEFVAL #undef CRF_APB_DDR_CTRL_DIVISOR0_SHIFT #undef CRF_APB_DDR_CTRL_DIVISOR0_MASK -#define CRF_APB_DDR_CTRL_DIVISOR0_DEFVAL 0x01000500 -#define CRF_APB_DDR_CTRL_DIVISOR0_SHIFT 8 -#define CRF_APB_DDR_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRF_APB_DDR_CTRL_DIVISOR0_DEFVAL 0x01000500 +#define CRF_APB_DDR_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_DDR_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = DPLL; 001 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This - s not usually an issue, but designers must be aware.)*/ +/* +* 000 = DPLL; 001 = VPLL; (This signal may only be toggled after 4 cycles + * of the old clock and 4 cycles of the new clock. This is not usually an i + * ssue, but designers must be aware.) +*/ #undef CRF_APB_DDR_CTRL_SRCSEL_DEFVAL #undef CRF_APB_DDR_CTRL_SRCSEL_SHIFT #undef CRF_APB_DDR_CTRL_SRCSEL_MASK -#define CRF_APB_DDR_CTRL_SRCSEL_DEFVAL 0x01000500 -#define CRF_APB_DDR_CTRL_SRCSEL_SHIFT 0 -#define CRF_APB_DDR_CTRL_SRCSEL_MASK 0x00000007U +#define CRF_APB_DDR_CTRL_SRCSEL_DEFVAL 0x01000500 +#define CRF_APB_DDR_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_DDR_CTRL_SRCSEL_MASK 0x00000007U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRF_APB_GPU_REF_CTRL_DIVISOR0_DEFVAL #undef CRF_APB_GPU_REF_CTRL_DIVISOR0_SHIFT #undef CRF_APB_GPU_REF_CTRL_DIVISOR0_MASK -#define CRF_APB_GPU_REF_CTRL_DIVISOR0_DEFVAL 0x00001500 -#define CRF_APB_GPU_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRF_APB_GPU_REF_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRF_APB_GPU_REF_CTRL_DIVISOR0_DEFVAL 0x00001500 +#define CRF_APB_GPU_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_GPU_REF_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = IOPLL_TO_FPD; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of - he new clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = IOPLL_TO_FPD; 010 = VPLL; 011 = DPLL; (This signal may only be tog + * gled after 4 cycles of the old clock and 4 cycles of the new clock. This + * is not usually an issue, but designers must be aware.) +*/ #undef CRF_APB_GPU_REF_CTRL_SRCSEL_DEFVAL #undef CRF_APB_GPU_REF_CTRL_SRCSEL_SHIFT #undef CRF_APB_GPU_REF_CTRL_SRCSEL_MASK -#define CRF_APB_GPU_REF_CTRL_SRCSEL_DEFVAL 0x00001500 -#define CRF_APB_GPU_REF_CTRL_SRCSEL_SHIFT 0 -#define CRF_APB_GPU_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRF_APB_GPU_REF_CTRL_SRCSEL_DEFVAL 0x00001500 +#define CRF_APB_GPU_REF_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_GPU_REF_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock, which will stop clock for GPU (and both Pixel Processors).*/ +/* +* Clock active signal. Switch to 0 to disable the clock, which will stop c + * lock for GPU (and both Pixel Processors). +*/ #undef CRF_APB_GPU_REF_CTRL_CLKACT_DEFVAL #undef CRF_APB_GPU_REF_CTRL_CLKACT_SHIFT #undef CRF_APB_GPU_REF_CTRL_CLKACT_MASK -#define CRF_APB_GPU_REF_CTRL_CLKACT_DEFVAL 0x00001500 -#define CRF_APB_GPU_REF_CTRL_CLKACT_SHIFT 24 -#define CRF_APB_GPU_REF_CTRL_CLKACT_MASK 0x01000000U +#define CRF_APB_GPU_REF_CTRL_CLKACT_DEFVAL 0x00001500 +#define CRF_APB_GPU_REF_CTRL_CLKACT_SHIFT 24 +#define CRF_APB_GPU_REF_CTRL_CLKACT_MASK 0x01000000U -/*Clock active signal for Pixel Processor. Switch to 0 to disable the clock only to this Pixel Processor*/ +/* +* Clock active signal for Pixel Processor. Switch to 0 to disable the cloc + * k only to this Pixel Processor +*/ #undef CRF_APB_GPU_REF_CTRL_PP0_CLKACT_DEFVAL #undef CRF_APB_GPU_REF_CTRL_PP0_CLKACT_SHIFT #undef CRF_APB_GPU_REF_CTRL_PP0_CLKACT_MASK -#define CRF_APB_GPU_REF_CTRL_PP0_CLKACT_DEFVAL 0x00001500 -#define CRF_APB_GPU_REF_CTRL_PP0_CLKACT_SHIFT 25 -#define CRF_APB_GPU_REF_CTRL_PP0_CLKACT_MASK 0x02000000U +#define CRF_APB_GPU_REF_CTRL_PP0_CLKACT_DEFVAL 0x00001500 +#define CRF_APB_GPU_REF_CTRL_PP0_CLKACT_SHIFT 25 +#define CRF_APB_GPU_REF_CTRL_PP0_CLKACT_MASK 0x02000000U -/*Clock active signal for Pixel Processor. Switch to 0 to disable the clock only to this Pixel Processor*/ +/* +* Clock active signal for Pixel Processor. Switch to 0 to disable the cloc + * k only to this Pixel Processor +*/ #undef CRF_APB_GPU_REF_CTRL_PP1_CLKACT_DEFVAL #undef CRF_APB_GPU_REF_CTRL_PP1_CLKACT_SHIFT #undef CRF_APB_GPU_REF_CTRL_PP1_CLKACT_MASK -#define CRF_APB_GPU_REF_CTRL_PP1_CLKACT_DEFVAL 0x00001500 -#define CRF_APB_GPU_REF_CTRL_PP1_CLKACT_SHIFT 26 -#define CRF_APB_GPU_REF_CTRL_PP1_CLKACT_MASK 0x04000000U +#define CRF_APB_GPU_REF_CTRL_PP1_CLKACT_DEFVAL 0x00001500 +#define CRF_APB_GPU_REF_CTRL_PP1_CLKACT_SHIFT 26 +#define CRF_APB_GPU_REF_CTRL_PP1_CLKACT_MASK 0x04000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRF_APB_GDMA_REF_CTRL_DIVISOR0_DEFVAL #undef CRF_APB_GDMA_REF_CTRL_DIVISOR0_SHIFT #undef CRF_APB_GDMA_REF_CTRL_DIVISOR0_MASK -#define CRF_APB_GDMA_REF_CTRL_DIVISOR0_DEFVAL 0x01000500 -#define CRF_APB_GDMA_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRF_APB_GDMA_REF_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRF_APB_GDMA_REF_CTRL_DIVISOR0_DEFVAL 0x01000500 +#define CRF_APB_GDMA_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_GDMA_REF_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - lock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled aft + * er 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRF_APB_GDMA_REF_CTRL_SRCSEL_DEFVAL #undef CRF_APB_GDMA_REF_CTRL_SRCSEL_SHIFT #undef CRF_APB_GDMA_REF_CTRL_SRCSEL_MASK -#define CRF_APB_GDMA_REF_CTRL_SRCSEL_DEFVAL 0x01000500 -#define CRF_APB_GDMA_REF_CTRL_SRCSEL_SHIFT 0 -#define CRF_APB_GDMA_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRF_APB_GDMA_REF_CTRL_SRCSEL_DEFVAL 0x01000500 +#define CRF_APB_GDMA_REF_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_GDMA_REF_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRF_APB_GDMA_REF_CTRL_CLKACT_DEFVAL #undef CRF_APB_GDMA_REF_CTRL_CLKACT_SHIFT #undef CRF_APB_GDMA_REF_CTRL_CLKACT_MASK -#define CRF_APB_GDMA_REF_CTRL_CLKACT_DEFVAL 0x01000500 -#define CRF_APB_GDMA_REF_CTRL_CLKACT_SHIFT 24 -#define CRF_APB_GDMA_REF_CTRL_CLKACT_MASK 0x01000000U +#define CRF_APB_GDMA_REF_CTRL_CLKACT_DEFVAL 0x01000500 +#define CRF_APB_GDMA_REF_CTRL_CLKACT_SHIFT 24 +#define CRF_APB_GDMA_REF_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRF_APB_DPDMA_REF_CTRL_DIVISOR0_DEFVAL #undef CRF_APB_DPDMA_REF_CTRL_DIVISOR0_SHIFT #undef CRF_APB_DPDMA_REF_CTRL_DIVISOR0_MASK -#define CRF_APB_DPDMA_REF_CTRL_DIVISOR0_DEFVAL 0x01000500 -#define CRF_APB_DPDMA_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRF_APB_DPDMA_REF_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRF_APB_DPDMA_REF_CTRL_DIVISOR0_DEFVAL 0x01000500 +#define CRF_APB_DPDMA_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_DPDMA_REF_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - lock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled aft + * er 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRF_APB_DPDMA_REF_CTRL_SRCSEL_DEFVAL #undef CRF_APB_DPDMA_REF_CTRL_SRCSEL_SHIFT #undef CRF_APB_DPDMA_REF_CTRL_SRCSEL_MASK -#define CRF_APB_DPDMA_REF_CTRL_SRCSEL_DEFVAL 0x01000500 -#define CRF_APB_DPDMA_REF_CTRL_SRCSEL_SHIFT 0 -#define CRF_APB_DPDMA_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRF_APB_DPDMA_REF_CTRL_SRCSEL_DEFVAL 0x01000500 +#define CRF_APB_DPDMA_REF_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_DPDMA_REF_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRF_APB_DPDMA_REF_CTRL_CLKACT_DEFVAL #undef CRF_APB_DPDMA_REF_CTRL_CLKACT_SHIFT #undef CRF_APB_DPDMA_REF_CTRL_CLKACT_MASK -#define CRF_APB_DPDMA_REF_CTRL_CLKACT_DEFVAL 0x01000500 -#define CRF_APB_DPDMA_REF_CTRL_CLKACT_SHIFT 24 -#define CRF_APB_DPDMA_REF_CTRL_CLKACT_MASK 0x01000000U +#define CRF_APB_DPDMA_REF_CTRL_CLKACT_DEFVAL 0x01000500 +#define CRF_APB_DPDMA_REF_CTRL_CLKACT_SHIFT 24 +#define CRF_APB_DPDMA_REF_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_DEFVAL #undef CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_SHIFT #undef CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_MASK -#define CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_DEFVAL 0x01000400 -#define CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_SHIFT 8 -#define CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_DEFVAL 0x01000400 +#define CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - lock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled aft + * er 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_DEFVAL #undef CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_SHIFT #undef CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_MASK -#define CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_DEFVAL 0x01000400 -#define CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_SHIFT 0 -#define CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_MASK 0x00000007U +#define CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_DEFVAL 0x01000400 +#define CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRF_APB_TOPSW_MAIN_CTRL_CLKACT_DEFVAL #undef CRF_APB_TOPSW_MAIN_CTRL_CLKACT_SHIFT #undef CRF_APB_TOPSW_MAIN_CTRL_CLKACT_MASK -#define CRF_APB_TOPSW_MAIN_CTRL_CLKACT_DEFVAL 0x01000400 -#define CRF_APB_TOPSW_MAIN_CTRL_CLKACT_SHIFT 24 -#define CRF_APB_TOPSW_MAIN_CTRL_CLKACT_MASK 0x01000000U +#define CRF_APB_TOPSW_MAIN_CTRL_CLKACT_DEFVAL 0x01000400 +#define CRF_APB_TOPSW_MAIN_CTRL_CLKACT_SHIFT 24 +#define CRF_APB_TOPSW_MAIN_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_DEFVAL #undef CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_SHIFT #undef CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_MASK -#define CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_DEFVAL 0x01000800 -#define CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_SHIFT 8 -#define CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_DEFVAL 0x01000800 +#define CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = APLL; 010 = IOPLL_TO_FPD; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of - he new clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = APLL; 010 = IOPLL_TO_FPD; 011 = DPLL; (This signal may only be tog + * gled after 4 cycles of the old clock and 4 cycles of the new clock. This + * is not usually an issue, but designers must be aware.) +*/ #undef CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_DEFVAL #undef CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_SHIFT #undef CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_MASK -#define CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_DEFVAL 0x01000800 -#define CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_SHIFT 0 -#define CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_MASK 0x00000007U +#define CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_DEFVAL 0x01000800 +#define CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_DEFVAL #undef CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_SHIFT #undef CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_MASK -#define CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_DEFVAL 0x01000800 -#define CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_SHIFT 24 -#define CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_MASK 0x01000000U +#define CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_DEFVAL 0x01000800 +#define CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_SHIFT 24 +#define CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_DEFVAL #undef CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_SHIFT #undef CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_MASK -#define CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_DEFVAL 0x00000A00 -#define CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_SHIFT 8 -#define CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_DEFVAL 0x00000A00 +#define CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of - he new clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be tog + * gled after 4 cycles of the old clock and 4 cycles of the new clock. This + * is not usually an issue, but designers must be aware.) +*/ #undef CRF_APB_DBG_TSTMP_CTRL_SRCSEL_DEFVAL #undef CRF_APB_DBG_TSTMP_CTRL_SRCSEL_SHIFT #undef CRF_APB_DBG_TSTMP_CTRL_SRCSEL_MASK -#define CRF_APB_DBG_TSTMP_CTRL_SRCSEL_DEFVAL 0x00000A00 -#define CRF_APB_DBG_TSTMP_CTRL_SRCSEL_SHIFT 0 -#define CRF_APB_DBG_TSTMP_CTRL_SRCSEL_MASK 0x00000007U +#define CRF_APB_DBG_TSTMP_CTRL_SRCSEL_DEFVAL 0x00000A00 +#define CRF_APB_DBG_TSTMP_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_DBG_TSTMP_CTRL_SRCSEL_MASK 0x00000007U -/*00" = Select the APB switch clock for the APB interface of TTC0'01" = Select the PLL ref clock for the APB interface of TTC0' - 0" = Select the R5 clock for the APB interface of TTC0*/ +/* +* 00" = Select the APB switch clock for the APB interface of TTC0'01" = Se + * lect the PLL ref clock for the APB interface of TTC0'10" = Select the R5 + * clock for the APB interface of TTC0 +*/ #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_DEFVAL #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_SHIFT #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_MASK -#define IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_SHIFT 0 -#define IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_MASK 0x00000003U +#define IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_SHIFT 0 +#define IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_MASK 0x00000003U -/*00" = Select the APB switch clock for the APB interface of TTC1'01" = Select the PLL ref clock for the APB interface of TTC1' - 0" = Select the R5 clock for the APB interface of TTC1*/ +/* +* 00" = Select the APB switch clock for the APB interface of TTC1'01" = Se + * lect the PLL ref clock for the APB interface of TTC1'10" = Select the R5 + * clock for the APB interface of TTC1 +*/ #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_DEFVAL #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_SHIFT #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_MASK -#define IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_SHIFT 2 -#define IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_MASK 0x0000000CU +#define IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_SHIFT 2 +#define IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_MASK 0x0000000CU -/*00" = Select the APB switch clock for the APB interface of TTC2'01" = Select the PLL ref clock for the APB interface of TTC2' - 0" = Select the R5 clock for the APB interface of TTC2*/ +/* +* 00" = Select the APB switch clock for the APB interface of TTC2'01" = Se + * lect the PLL ref clock for the APB interface of TTC2'10" = Select the R5 + * clock for the APB interface of TTC2 +*/ #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_DEFVAL #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_SHIFT #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_MASK -#define IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_SHIFT 4 -#define IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_MASK 0x00000030U +#define IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_SHIFT 4 +#define IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_MASK 0x00000030U -/*00" = Select the APB switch clock for the APB interface of TTC3'01" = Select the PLL ref clock for the APB interface of TTC3' - 0" = Select the R5 clock for the APB interface of TTC3*/ +/* +* 00" = Select the APB switch clock for the APB interface of TTC3'01" = Se + * lect the PLL ref clock for the APB interface of TTC3'10" = Select the R5 + * clock for the APB interface of TTC3 +*/ #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_DEFVAL #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_SHIFT #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_MASK -#define IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_SHIFT 6 -#define IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_MASK 0x000000C0U +#define IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_SHIFT 6 +#define IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_MASK 0x000000C0U -/*System watchdog timer clock source selection: 0: Internal APB clock 1: External (PL clock via EMIO or Pinout clock via MIO)*/ +/* +* System watchdog timer clock source selection: 0: Internal APB clock 1: E + * xternal (PL clock via EMIO or Pinout clock via MIO) +*/ #undef FPD_SLCR_WDT_CLK_SEL_SELECT_DEFVAL #undef FPD_SLCR_WDT_CLK_SEL_SELECT_SHIFT #undef FPD_SLCR_WDT_CLK_SEL_SELECT_MASK -#define FPD_SLCR_WDT_CLK_SEL_SELECT_DEFVAL 0x00000000 -#define FPD_SLCR_WDT_CLK_SEL_SELECT_SHIFT 0 -#define FPD_SLCR_WDT_CLK_SEL_SELECT_MASK 0x00000001U +#define FPD_SLCR_WDT_CLK_SEL_SELECT_DEFVAL 0x00000000 +#define FPD_SLCR_WDT_CLK_SEL_SELECT_SHIFT 0 +#define FPD_SLCR_WDT_CLK_SEL_SELECT_MASK 0x00000001U -/*System watchdog timer clock source selection: 0: internal clock APB clock 1: external clock from PL via EMIO, or from pinout - ia MIO*/ +/* +* System watchdog timer clock source selection: 0: internal clock APB cloc + * k 1: external clock from PL via EMIO, or from pinout via MIO +*/ #undef IOU_SLCR_WDT_CLK_SEL_SELECT_DEFVAL #undef IOU_SLCR_WDT_CLK_SEL_SELECT_SHIFT #undef IOU_SLCR_WDT_CLK_SEL_SELECT_MASK -#define IOU_SLCR_WDT_CLK_SEL_SELECT_DEFVAL 0x00000000 -#define IOU_SLCR_WDT_CLK_SEL_SELECT_SHIFT 0 -#define IOU_SLCR_WDT_CLK_SEL_SELECT_MASK 0x00000001U +#define IOU_SLCR_WDT_CLK_SEL_SELECT_DEFVAL 0x00000000 +#define IOU_SLCR_WDT_CLK_SEL_SELECT_SHIFT 0 +#define IOU_SLCR_WDT_CLK_SEL_SELECT_MASK 0x00000001U -/*System watchdog timer clock source selection: 0: internal clock APB clock 1: external clock pss_ref_clk*/ +/* +* System watchdog timer clock source selection: 0: internal clock APB cloc + * k 1: external clock pss_ref_clk +*/ #undef LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_DEFVAL #undef LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_SHIFT #undef LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_MASK -#define LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_DEFVAL 0x00000000 -#define LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_SHIFT 0 -#define LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_MASK 0x00000001U +#define LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_DEFVAL 0x00000000 +#define LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_SHIFT 0 +#define LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_MASK 0x00000001U #undef CRF_APB_RST_DDR_SS_OFFSET #define CRF_APB_RST_DDR_SS_OFFSET 0XFD1A0108 #undef DDRC_MSTR_OFFSET @@ -2078,6 +2380,8 @@ #define DDRC_PWRTMG_OFFSET 0XFD070034 #undef DDRC_RFSHCTL0_OFFSET #define DDRC_RFSHCTL0_OFFSET 0XFD070050 +#undef DDRC_RFSHCTL1_OFFSET +#define DDRC_RFSHCTL1_OFFSET 0XFD070054 #undef DDRC_RFSHCTL3_OFFSET #define DDRC_RFSHCTL3_OFFSET 0XFD070060 #undef DDRC_RFSHTMG_OFFSET @@ -2146,6 +2450,8 @@ #define DDRC_DFILPCFG0_OFFSET 0XFD070198 #undef DDRC_DFILPCFG1_OFFSET #define DDRC_DFILPCFG1_OFFSET 0XFD07019C +#undef DDRC_DFIUPD0_OFFSET +#define DDRC_DFIUPD0_OFFSET 0XFD0701A0 #undef DDRC_DFIUPD1_OFFSET #define DDRC_DFIUPD1_OFFSET 0XFD0701A4 #undef DDRC_DFIMISC_OFFSET @@ -2188,6 +2494,16 @@ #define DDRC_PERFLPR1_OFFSET 0XFD070264 #undef DDRC_PERFWR1_OFFSET #define DDRC_PERFWR1_OFFSET 0XFD07026C +#undef DDRC_DQMAP0_OFFSET +#define DDRC_DQMAP0_OFFSET 0XFD070280 +#undef DDRC_DQMAP1_OFFSET +#define DDRC_DQMAP1_OFFSET 0XFD070284 +#undef DDRC_DQMAP2_OFFSET +#define DDRC_DQMAP2_OFFSET 0XFD070288 +#undef DDRC_DQMAP3_OFFSET +#define DDRC_DQMAP3_OFFSET 0XFD07028C +#undef DDRC_DQMAP4_OFFSET +#define DDRC_DQMAP4_OFFSET 0XFD070290 #undef DDRC_DQMAP5_OFFSET #define DDRC_DQMAP5_OFFSET 0XFD070294 #undef DDRC_DBG0_OFFSET @@ -2294,8 +2610,12 @@ #define DDR_PHY_PTR0_OFFSET 0XFD080040 #undef DDR_PHY_PTR1_OFFSET #define DDR_PHY_PTR1_OFFSET 0XFD080044 +#undef DDR_PHY_PLLCR0_OFFSET +#define DDR_PHY_PLLCR0_OFFSET 0XFD080068 #undef DDR_PHY_DSGCR_OFFSET #define DDR_PHY_DSGCR_OFFSET 0XFD080090 +#undef DDR_PHY_GPR0_OFFSET +#define DDR_PHY_GPR0_OFFSET 0XFD0800C0 #undef DDR_PHY_DCR_OFFSET #define DDR_PHY_DCR_OFFSET 0XFD080100 #undef DDR_PHY_DTPR0_OFFSET @@ -2350,6 +2670,8 @@ #define DDR_PHY_DTCR1_OFFSET 0XFD080204 #undef DDR_PHY_CATR0_OFFSET #define DDR_PHY_CATR0_OFFSET 0XFD080240 +#undef DDR_PHY_DQSDR0_OFFSET +#define DDR_PHY_DQSDR0_OFFSET 0XFD080250 #undef DDR_PHY_BISTLSR_OFFSET #define DDR_PHY_BISTLSR_OFFSET 0XFD080414 #undef DDR_PHY_RIOCR5_OFFSET @@ -2398,10 +2720,6 @@ #define DDR_PHY_DX0GCR5_OFFSET 0XFD080714 #undef DDR_PHY_DX0GCR6_OFFSET #define DDR_PHY_DX0GCR6_OFFSET 0XFD080718 -#undef DDR_PHY_DX0LCDLR2_OFFSET -#define DDR_PHY_DX0LCDLR2_OFFSET 0XFD080788 -#undef DDR_PHY_DX0GTR0_OFFSET -#define DDR_PHY_DX0GTR0_OFFSET 0XFD0807C0 #undef DDR_PHY_DX1GCR0_OFFSET #define DDR_PHY_DX1GCR0_OFFSET 0XFD080800 #undef DDR_PHY_DX1GCR4_OFFSET @@ -2410,10 +2728,6 @@ #define DDR_PHY_DX1GCR5_OFFSET 0XFD080814 #undef DDR_PHY_DX1GCR6_OFFSET #define DDR_PHY_DX1GCR6_OFFSET 0XFD080818 -#undef DDR_PHY_DX1LCDLR2_OFFSET -#define DDR_PHY_DX1LCDLR2_OFFSET 0XFD080888 -#undef DDR_PHY_DX1GTR0_OFFSET -#define DDR_PHY_DX1GTR0_OFFSET 0XFD0808C0 #undef DDR_PHY_DX2GCR0_OFFSET #define DDR_PHY_DX2GCR0_OFFSET 0XFD080900 #undef DDR_PHY_DX2GCR1_OFFSET @@ -2424,10 +2738,6 @@ #define DDR_PHY_DX2GCR5_OFFSET 0XFD080914 #undef DDR_PHY_DX2GCR6_OFFSET #define DDR_PHY_DX2GCR6_OFFSET 0XFD080918 -#undef DDR_PHY_DX2LCDLR2_OFFSET -#define DDR_PHY_DX2LCDLR2_OFFSET 0XFD080988 -#undef DDR_PHY_DX2GTR0_OFFSET -#define DDR_PHY_DX2GTR0_OFFSET 0XFD0809C0 #undef DDR_PHY_DX3GCR0_OFFSET #define DDR_PHY_DX3GCR0_OFFSET 0XFD080A00 #undef DDR_PHY_DX3GCR1_OFFSET @@ -2438,10 +2748,6 @@ #define DDR_PHY_DX3GCR5_OFFSET 0XFD080A14 #undef DDR_PHY_DX3GCR6_OFFSET #define DDR_PHY_DX3GCR6_OFFSET 0XFD080A18 -#undef DDR_PHY_DX3LCDLR2_OFFSET -#define DDR_PHY_DX3LCDLR2_OFFSET 0XFD080A88 -#undef DDR_PHY_DX3GTR0_OFFSET -#define DDR_PHY_DX3GTR0_OFFSET 0XFD080AC0 #undef DDR_PHY_DX4GCR0_OFFSET #define DDR_PHY_DX4GCR0_OFFSET 0XFD080B00 #undef DDR_PHY_DX4GCR1_OFFSET @@ -2452,10 +2758,6 @@ #define DDR_PHY_DX4GCR5_OFFSET 0XFD080B14 #undef DDR_PHY_DX4GCR6_OFFSET #define DDR_PHY_DX4GCR6_OFFSET 0XFD080B18 -#undef DDR_PHY_DX4LCDLR2_OFFSET -#define DDR_PHY_DX4LCDLR2_OFFSET 0XFD080B88 -#undef DDR_PHY_DX4GTR0_OFFSET -#define DDR_PHY_DX4GTR0_OFFSET 0XFD080BC0 #undef DDR_PHY_DX5GCR0_OFFSET #define DDR_PHY_DX5GCR0_OFFSET 0XFD080C00 #undef DDR_PHY_DX5GCR1_OFFSET @@ -2466,10 +2768,6 @@ #define DDR_PHY_DX5GCR5_OFFSET 0XFD080C14 #undef DDR_PHY_DX5GCR6_OFFSET #define DDR_PHY_DX5GCR6_OFFSET 0XFD080C18 -#undef DDR_PHY_DX5LCDLR2_OFFSET -#define DDR_PHY_DX5LCDLR2_OFFSET 0XFD080C88 -#undef DDR_PHY_DX5GTR0_OFFSET -#define DDR_PHY_DX5GTR0_OFFSET 0XFD080CC0 #undef DDR_PHY_DX6GCR0_OFFSET #define DDR_PHY_DX6GCR0_OFFSET 0XFD080D00 #undef DDR_PHY_DX6GCR1_OFFSET @@ -2480,10 +2778,6 @@ #define DDR_PHY_DX6GCR5_OFFSET 0XFD080D14 #undef DDR_PHY_DX6GCR6_OFFSET #define DDR_PHY_DX6GCR6_OFFSET 0XFD080D18 -#undef DDR_PHY_DX6LCDLR2_OFFSET -#define DDR_PHY_DX6LCDLR2_OFFSET 0XFD080D88 -#undef DDR_PHY_DX6GTR0_OFFSET -#define DDR_PHY_DX6GTR0_OFFSET 0XFD080DC0 #undef DDR_PHY_DX7GCR0_OFFSET #define DDR_PHY_DX7GCR0_OFFSET 0XFD080E00 #undef DDR_PHY_DX7GCR1_OFFSET @@ -2494,10 +2788,6 @@ #define DDR_PHY_DX7GCR5_OFFSET 0XFD080E14 #undef DDR_PHY_DX7GCR6_OFFSET #define DDR_PHY_DX7GCR6_OFFSET 0XFD080E18 -#undef DDR_PHY_DX7LCDLR2_OFFSET -#define DDR_PHY_DX7LCDLR2_OFFSET 0XFD080E88 -#undef DDR_PHY_DX7GTR0_OFFSET -#define DDR_PHY_DX7GTR0_OFFSET 0XFD080EC0 #undef DDR_PHY_DX8GCR0_OFFSET #define DDR_PHY_DX8GCR0_OFFSET 0XFD080F00 #undef DDR_PHY_DX8GCR1_OFFSET @@ -2508,12 +2798,10 @@ #define DDR_PHY_DX8GCR5_OFFSET 0XFD080F14 #undef DDR_PHY_DX8GCR6_OFFSET #define DDR_PHY_DX8GCR6_OFFSET 0XFD080F18 -#undef DDR_PHY_DX8LCDLR2_OFFSET -#define DDR_PHY_DX8LCDLR2_OFFSET 0XFD080F88 -#undef DDR_PHY_DX8GTR0_OFFSET -#define DDR_PHY_DX8GTR0_OFFSET 0XFD080FC0 #undef DDR_PHY_DX8SL0OSC_OFFSET #define DDR_PHY_DX8SL0OSC_OFFSET 0XFD081400 +#undef DDR_PHY_DX8SL0PLLCR0_OFFSET +#define DDR_PHY_DX8SL0PLLCR0_OFFSET 0XFD081404 #undef DDR_PHY_DX8SL0DQSCTL_OFFSET #define DDR_PHY_DX8SL0DQSCTL_OFFSET 0XFD08141C #undef DDR_PHY_DX8SL0DXCTL2_OFFSET @@ -2522,6 +2810,8 @@ #define DDR_PHY_DX8SL0IOCR_OFFSET 0XFD081430 #undef DDR_PHY_DX8SL1OSC_OFFSET #define DDR_PHY_DX8SL1OSC_OFFSET 0XFD081440 +#undef DDR_PHY_DX8SL1PLLCR0_OFFSET +#define DDR_PHY_DX8SL1PLLCR0_OFFSET 0XFD081444 #undef DDR_PHY_DX8SL1DQSCTL_OFFSET #define DDR_PHY_DX8SL1DQSCTL_OFFSET 0XFD08145C #undef DDR_PHY_DX8SL1DXCTL2_OFFSET @@ -2530,6 +2820,8 @@ #define DDR_PHY_DX8SL1IOCR_OFFSET 0XFD081470 #undef DDR_PHY_DX8SL2OSC_OFFSET #define DDR_PHY_DX8SL2OSC_OFFSET 0XFD081480 +#undef DDR_PHY_DX8SL2PLLCR0_OFFSET +#define DDR_PHY_DX8SL2PLLCR0_OFFSET 0XFD081484 #undef DDR_PHY_DX8SL2DQSCTL_OFFSET #define DDR_PHY_DX8SL2DQSCTL_OFFSET 0XFD08149C #undef DDR_PHY_DX8SL2DXCTL2_OFFSET @@ -2538,6 +2830,8 @@ #define DDR_PHY_DX8SL2IOCR_OFFSET 0XFD0814B0 #undef DDR_PHY_DX8SL3OSC_OFFSET #define DDR_PHY_DX8SL3OSC_OFFSET 0XFD0814C0 +#undef DDR_PHY_DX8SL3PLLCR0_OFFSET +#define DDR_PHY_DX8SL3PLLCR0_OFFSET 0XFD0814C4 #undef DDR_PHY_DX8SL3DQSCTL_OFFSET #define DDR_PHY_DX8SL3DQSCTL_OFFSET 0XFD0814DC #undef DDR_PHY_DX8SL3DXCTL2_OFFSET @@ -2546,14391 +2840,18570 @@ #define DDR_PHY_DX8SL3IOCR_OFFSET 0XFD0814F0 #undef DDR_PHY_DX8SL4OSC_OFFSET #define DDR_PHY_DX8SL4OSC_OFFSET 0XFD081500 +#undef DDR_PHY_DX8SL4PLLCR0_OFFSET +#define DDR_PHY_DX8SL4PLLCR0_OFFSET 0XFD081504 #undef DDR_PHY_DX8SL4DQSCTL_OFFSET #define DDR_PHY_DX8SL4DQSCTL_OFFSET 0XFD08151C #undef DDR_PHY_DX8SL4DXCTL2_OFFSET #define DDR_PHY_DX8SL4DXCTL2_OFFSET 0XFD08152C #undef DDR_PHY_DX8SL4IOCR_OFFSET #define DDR_PHY_DX8SL4IOCR_OFFSET 0XFD081530 +#undef DDR_PHY_DX8SLBPLLCR0_OFFSET +#define DDR_PHY_DX8SLBPLLCR0_OFFSET 0XFD0817C4 #undef DDR_PHY_DX8SLBDQSCTL_OFFSET #define DDR_PHY_DX8SLBDQSCTL_OFFSET 0XFD0817DC -#undef DDR_PHY_PIR_OFFSET -#define DDR_PHY_PIR_OFFSET 0XFD080004 -/*DDR block level reset inside of the DDR Sub System*/ +/* +* DDR block level reset inside of the DDR Sub System +*/ #undef CRF_APB_RST_DDR_SS_DDR_RESET_DEFVAL #undef CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT #undef CRF_APB_RST_DDR_SS_DDR_RESET_MASK -#define CRF_APB_RST_DDR_SS_DDR_RESET_DEFVAL 0x0000000F -#define CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT 3 -#define CRF_APB_RST_DDR_SS_DDR_RESET_MASK 0x00000008U +#define CRF_APB_RST_DDR_SS_DDR_RESET_DEFVAL 0x0000000F +#define CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT 3 +#define CRF_APB_RST_DDR_SS_DDR_RESET_MASK 0x00000008U -/*Indicates the configuration of the device used in the system. - 00 - x4 device - 01 - x8 device - 10 - x16 device - 11 - x32 - evice*/ +/* +* Indicates the configuration of the device used in the system. - 00 - x4 + * device - 01 - x8 device - 10 - x16 device - 11 - x32 device +*/ #undef DDRC_MSTR_DEVICE_CONFIG_DEFVAL #undef DDRC_MSTR_DEVICE_CONFIG_SHIFT #undef DDRC_MSTR_DEVICE_CONFIG_MASK -#define DDRC_MSTR_DEVICE_CONFIG_DEFVAL 0x03040001 -#define DDRC_MSTR_DEVICE_CONFIG_SHIFT 30 -#define DDRC_MSTR_DEVICE_CONFIG_MASK 0xC0000000U +#define DDRC_MSTR_DEVICE_CONFIG_DEFVAL 0x03040001 +#define DDRC_MSTR_DEVICE_CONFIG_SHIFT 30 +#define DDRC_MSTR_DEVICE_CONFIG_MASK 0xC0000000U -/*Choose which registers are used. - 0 - Original registers - 1 - Shadow registers*/ +/* +* Choose which registers are used. - 0 - Original registers - 1 - Shadow r + * egisters +*/ #undef DDRC_MSTR_FREQUENCY_MODE_DEFVAL #undef DDRC_MSTR_FREQUENCY_MODE_SHIFT #undef DDRC_MSTR_FREQUENCY_MODE_MASK -#define DDRC_MSTR_FREQUENCY_MODE_DEFVAL 0x03040001 -#define DDRC_MSTR_FREQUENCY_MODE_SHIFT 29 -#define DDRC_MSTR_FREQUENCY_MODE_MASK 0x20000000U +#define DDRC_MSTR_FREQUENCY_MODE_DEFVAL 0x03040001 +#define DDRC_MSTR_FREQUENCY_MODE_SHIFT 29 +#define DDRC_MSTR_FREQUENCY_MODE_MASK 0x20000000U -/*Only present for multi-rank configurations. Each bit represents one rank. For two-rank configurations, only bits[25:24] are p - esent. - 1 - populated - 0 - unpopulated LSB is the lowest rank number. For 2 ranks following combinations are legal: - 01 - - ne rank - 11 - Two ranks - Others - Reserved. For 4 ranks following combinations are legal: - 0001 - One rank - 0011 - Two ra - ks - 1111 - Four ranks*/ +/* +* Only present for multi-rank configurations. Each bit represents one rank + * . For two-rank configurations, only bits[25:24] are present. - 1 - popul + * ated - 0 - unpopulated LSB is the lowest rank number. For 2 ranks follow + * ing combinations are legal: - 01 - One rank - 11 - Two ranks - Others - + * Reserved. For 4 ranks following combinations are legal: - 0001 - One ran + * k - 0011 - Two ranks - 1111 - Four ranks +*/ #undef DDRC_MSTR_ACTIVE_RANKS_DEFVAL #undef DDRC_MSTR_ACTIVE_RANKS_SHIFT #undef DDRC_MSTR_ACTIVE_RANKS_MASK -#define DDRC_MSTR_ACTIVE_RANKS_DEFVAL 0x03040001 -#define DDRC_MSTR_ACTIVE_RANKS_SHIFT 24 -#define DDRC_MSTR_ACTIVE_RANKS_MASK 0x03000000U +#define DDRC_MSTR_ACTIVE_RANKS_DEFVAL 0x03040001 +#define DDRC_MSTR_ACTIVE_RANKS_SHIFT 24 +#define DDRC_MSTR_ACTIVE_RANKS_MASK 0x03000000U -/*SDRAM burst length used: - 0001 - Burst length of 2 (only supported for mDDR) - 0010 - Burst length of 4 - 0100 - Burst lengt - of 8 - 1000 - Burst length of 16 (only supported for mDDR, LPDDR2, and LPDDR4) All other values are reserved. This controls - he burst size used to access the SDRAM. This must match the burst length mode register setting in the SDRAM. (For BC4/8 on-th - -fly mode of DDR3 and DDR4, set this field to 0x0100) Burst length of 2 is not supported with AXI ports when MEMC_BURST_LENGT - is 8. Burst length of 2 is only supported with MEMC_FREQ_RATIO = 1*/ +/* +* SDRAM burst length used: - 0001 - Burst length of 2 (only supported for + * mDDR) - 0010 - Burst length of 4 - 0100 - Burst length of 8 - 1000 - Bur + * st length of 16 (only supported for mDDR, LPDDR2, and LPDDR4) All other + * values are reserved. This controls the burst size used to access the SDR + * AM. This must match the burst length mode register setting in the SDRAM. + * (For BC4/8 on-the-fly mode of DDR3 and DDR4, set this field to 0x0100) + * Burst length of 2 is not supported with AXI ports when MEMC_BURST_LENGTH + * is 8. Burst length of 2 is only supported with MEMC_FREQ_RATIO = 1 +*/ #undef DDRC_MSTR_BURST_RDWR_DEFVAL #undef DDRC_MSTR_BURST_RDWR_SHIFT #undef DDRC_MSTR_BURST_RDWR_MASK -#define DDRC_MSTR_BURST_RDWR_DEFVAL 0x03040001 -#define DDRC_MSTR_BURST_RDWR_SHIFT 16 -#define DDRC_MSTR_BURST_RDWR_MASK 0x000F0000U +#define DDRC_MSTR_BURST_RDWR_DEFVAL 0x03040001 +#define DDRC_MSTR_BURST_RDWR_SHIFT 16 +#define DDRC_MSTR_BURST_RDWR_MASK 0x000F0000U -/*Set to 1 when the uMCTL2 and DRAM has to be put in DLL-off mode for low frequency operation. Set to 0 to put uMCTL2 and DRAM - n DLL-on mode for normal frequency operation. If DDR4 CRC/parity retry is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), d - l_off_mode is not supported, and this bit must be set to '0'.*/ +/* +* Set to 1 when the uMCTL2 and DRAM has to be put in DLL-off mode for low + * frequency operation. Set to 0 to put uMCTL2 and DRAM in DLL-on mode for + * normal frequency operation. If DDR4 CRC/parity retry is enabled (CRCPARC + * TL1.crc_parity_retry_enable = 1), dll_off_mode is not supported, and thi + * s bit must be set to '0'. +*/ #undef DDRC_MSTR_DLL_OFF_MODE_DEFVAL #undef DDRC_MSTR_DLL_OFF_MODE_SHIFT #undef DDRC_MSTR_DLL_OFF_MODE_MASK -#define DDRC_MSTR_DLL_OFF_MODE_DEFVAL 0x03040001 -#define DDRC_MSTR_DLL_OFF_MODE_SHIFT 15 -#define DDRC_MSTR_DLL_OFF_MODE_MASK 0x00008000U +#define DDRC_MSTR_DLL_OFF_MODE_DEFVAL 0x03040001 +#define DDRC_MSTR_DLL_OFF_MODE_SHIFT 15 +#define DDRC_MSTR_DLL_OFF_MODE_MASK 0x00008000U -/*Selects proportion of DQ bus width that is used by the SDRAM - 00 - Full DQ bus width to SDRAM - 01 - Half DQ bus width to SD - AM - 10 - Quarter DQ bus width to SDRAM - 11 - Reserved. Note that half bus width mode is only supported when the SDRAM bus w - dth is a multiple of 16, and quarter bus width mode is only supported when the SDRAM bus width is a multiple of 32 and the co - figuration parameter MEMC_QBUS_SUPPORT is set. Bus width refers to DQ bus width (excluding any ECC width).*/ +/* +* Selects proportion of DQ bus width that is used by the SDRAM - 00 - Full + * DQ bus width to SDRAM - 01 - Half DQ bus width to SDRAM - 10 - Quarter + * DQ bus width to SDRAM - 11 - Reserved. Note that half bus width mode is + * only supported when the SDRAM bus width is a multiple of 16, and quarter + * bus width mode is only supported when the SDRAM bus width is a multiple + * of 32 and the configuration parameter MEMC_QBUS_SUPPORT is set. Bus wid + * th refers to DQ bus width (excluding any ECC width). +*/ #undef DDRC_MSTR_DATA_BUS_WIDTH_DEFVAL #undef DDRC_MSTR_DATA_BUS_WIDTH_SHIFT #undef DDRC_MSTR_DATA_BUS_WIDTH_MASK -#define DDRC_MSTR_DATA_BUS_WIDTH_DEFVAL 0x03040001 -#define DDRC_MSTR_DATA_BUS_WIDTH_SHIFT 12 -#define DDRC_MSTR_DATA_BUS_WIDTH_MASK 0x00003000U +#define DDRC_MSTR_DATA_BUS_WIDTH_DEFVAL 0x03040001 +#define DDRC_MSTR_DATA_BUS_WIDTH_SHIFT 12 +#define DDRC_MSTR_DATA_BUS_WIDTH_MASK 0x00003000U -/*1 indicates put the DRAM in geardown mode (2N) and 0 indicates put the DRAM in normal mode (1N). This register can be changed - only when the Controller is in self-refresh mode. This signal must be set the same value as MR3 bit A3. Note: Geardown mode - s not supported if the configuration parameter MEMC_CMD_RTN2IDLE is set*/ +/* +* 1 indicates put the DRAM in geardown mode (2N) and 0 indicates put the D + * RAM in normal mode (1N). This register can be changed, only when the Con + * troller is in self-refresh mode. This signal must be set the same value + * as MR3 bit A3. Note: Geardown mode is not supported if the configuration + * parameter MEMC_CMD_RTN2IDLE is set +*/ #undef DDRC_MSTR_GEARDOWN_MODE_DEFVAL #undef DDRC_MSTR_GEARDOWN_MODE_SHIFT #undef DDRC_MSTR_GEARDOWN_MODE_MASK -#define DDRC_MSTR_GEARDOWN_MODE_DEFVAL 0x03040001 -#define DDRC_MSTR_GEARDOWN_MODE_SHIFT 11 -#define DDRC_MSTR_GEARDOWN_MODE_MASK 0x00000800U +#define DDRC_MSTR_GEARDOWN_MODE_DEFVAL 0x03040001 +#define DDRC_MSTR_GEARDOWN_MODE_SHIFT 11 +#define DDRC_MSTR_GEARDOWN_MODE_MASK 0x00000800U -/*If 1, then uMCTL2 uses 2T timing. Otherwise, uses 1T timing. In 2T timing, all command signals (except chip select) are held - or 2 clocks on the SDRAM bus. Chip select is asserted on the second cycle of the command Note: 2T timing is not supported in - PDDR2/LPDDR3/LPDDR4 mode Note: 2T timing is not supported if the configuration parameter MEMC_CMD_RTN2IDLE is set Note: 2T ti - ing is not supported in DDR4 geardown mode.*/ +/* +* If 1, then uMCTL2 uses 2T timing. Otherwise, uses 1T timing. In 2T timin + * g, all command signals (except chip select) are held for 2 clocks on the + * SDRAM bus. Chip select is asserted on the second cycle of the command N + * ote: 2T timing is not supported in LPDDR2/LPDDR3/LPDDR4 mode Note: 2T ti + * ming is not supported if the configuration parameter MEMC_CMD_RTN2IDLE i + * s set Note: 2T timing is not supported in DDR4 geardown mode. +*/ #undef DDRC_MSTR_EN_2T_TIMING_MODE_DEFVAL #undef DDRC_MSTR_EN_2T_TIMING_MODE_SHIFT #undef DDRC_MSTR_EN_2T_TIMING_MODE_MASK -#define DDRC_MSTR_EN_2T_TIMING_MODE_DEFVAL 0x03040001 -#define DDRC_MSTR_EN_2T_TIMING_MODE_SHIFT 10 -#define DDRC_MSTR_EN_2T_TIMING_MODE_MASK 0x00000400U +#define DDRC_MSTR_EN_2T_TIMING_MODE_DEFVAL 0x03040001 +#define DDRC_MSTR_EN_2T_TIMING_MODE_SHIFT 10 +#define DDRC_MSTR_EN_2T_TIMING_MODE_MASK 0x00000400U -/*When set, enable burst-chop in DDR3/DDR4. Burst Chop for Reads is exercised only in HIF configurations (UMCTL2_INCL_ARB not s - t) and if in full bus width mode (MSTR.data_bus_width = 00). Burst Chop for Writes is exercised only if Partial Writes enable - (UMCTL2_PARTIAL_WR=1) and if CRC is disabled (CRCPARCTL1.crc_enable = 0). If DDR4 CRC/parity retry is enabled (CRCPARCTL1.cr - _parity_retry_enable = 1), burst chop is not supported, and this bit must be set to '0'*/ +/* +* When set, enable burst-chop in DDR3/DDR4. Burst Chop for Reads is exerci + * sed only in HIF configurations (UMCTL2_INCL_ARB not set) and if in full + * bus width mode (MSTR.data_bus_width = 00). Burst Chop for Writes is exer + * cised only if Partial Writes enabled (UMCTL2_PARTIAL_WR=1) and if CRC is + * disabled (CRCPARCTL1.crc_enable = 0). If DDR4 CRC/parity retry is enabl + * ed (CRCPARCTL1.crc_parity_retry_enable = 1), burst chop is not supported + * , and this bit must be set to '0' +*/ #undef DDRC_MSTR_BURSTCHOP_DEFVAL #undef DDRC_MSTR_BURSTCHOP_SHIFT #undef DDRC_MSTR_BURSTCHOP_MASK -#define DDRC_MSTR_BURSTCHOP_DEFVAL 0x03040001 -#define DDRC_MSTR_BURSTCHOP_SHIFT 9 -#define DDRC_MSTR_BURSTCHOP_MASK 0x00000200U +#define DDRC_MSTR_BURSTCHOP_DEFVAL 0x03040001 +#define DDRC_MSTR_BURSTCHOP_SHIFT 9 +#define DDRC_MSTR_BURSTCHOP_MASK 0x00000200U -/*Select LPDDR4 SDRAM - 1 - LPDDR4 SDRAM device in use. - 0 - non-LPDDR4 device in use Present only in designs configured to su - port LPDDR4.*/ +/* +* Select LPDDR4 SDRAM - 1 - LPDDR4 SDRAM device in use. - 0 - non-LPDDR4 d + * evice in use Present only in designs configured to support LPDDR4. +*/ #undef DDRC_MSTR_LPDDR4_DEFVAL #undef DDRC_MSTR_LPDDR4_SHIFT #undef DDRC_MSTR_LPDDR4_MASK -#define DDRC_MSTR_LPDDR4_DEFVAL 0x03040001 -#define DDRC_MSTR_LPDDR4_SHIFT 5 -#define DDRC_MSTR_LPDDR4_MASK 0x00000020U +#define DDRC_MSTR_LPDDR4_DEFVAL 0x03040001 +#define DDRC_MSTR_LPDDR4_SHIFT 5 +#define DDRC_MSTR_LPDDR4_MASK 0x00000020U -/*Select DDR4 SDRAM - 1 - DDR4 SDRAM device in use. - 0 - non-DDR4 device in use Present only in designs configured to support - DR4.*/ +/* +* Select DDR4 SDRAM - 1 - DDR4 SDRAM device in use. - 0 - non-DDR4 device + * in use Present only in designs configured to support DDR4. +*/ #undef DDRC_MSTR_DDR4_DEFVAL #undef DDRC_MSTR_DDR4_SHIFT #undef DDRC_MSTR_DDR4_MASK -#define DDRC_MSTR_DDR4_DEFVAL 0x03040001 -#define DDRC_MSTR_DDR4_SHIFT 4 -#define DDRC_MSTR_DDR4_MASK 0x00000010U +#define DDRC_MSTR_DDR4_DEFVAL 0x03040001 +#define DDRC_MSTR_DDR4_SHIFT 4 +#define DDRC_MSTR_DDR4_MASK 0x00000010U -/*Select LPDDR3 SDRAM - 1 - LPDDR3 SDRAM device in use. - 0 - non-LPDDR3 device in use Present only in designs configured to su - port LPDDR3.*/ +/* +* Select LPDDR3 SDRAM - 1 - LPDDR3 SDRAM device in use. - 0 - non-LPDDR3 d + * evice in use Present only in designs configured to support LPDDR3. +*/ #undef DDRC_MSTR_LPDDR3_DEFVAL #undef DDRC_MSTR_LPDDR3_SHIFT #undef DDRC_MSTR_LPDDR3_MASK -#define DDRC_MSTR_LPDDR3_DEFVAL 0x03040001 -#define DDRC_MSTR_LPDDR3_SHIFT 3 -#define DDRC_MSTR_LPDDR3_MASK 0x00000008U +#define DDRC_MSTR_LPDDR3_DEFVAL 0x03040001 +#define DDRC_MSTR_LPDDR3_SHIFT 3 +#define DDRC_MSTR_LPDDR3_MASK 0x00000008U -/*Select LPDDR2 SDRAM - 1 - LPDDR2 SDRAM device in use. - 0 - non-LPDDR2 device in use Present only in designs configured to su - port LPDDR2.*/ +/* +* Select LPDDR2 SDRAM - 1 - LPDDR2 SDRAM device in use. - 0 - non-LPDDR2 d + * evice in use Present only in designs configured to support LPDDR2. +*/ #undef DDRC_MSTR_LPDDR2_DEFVAL #undef DDRC_MSTR_LPDDR2_SHIFT #undef DDRC_MSTR_LPDDR2_MASK -#define DDRC_MSTR_LPDDR2_DEFVAL 0x03040001 -#define DDRC_MSTR_LPDDR2_SHIFT 2 -#define DDRC_MSTR_LPDDR2_MASK 0x00000004U +#define DDRC_MSTR_LPDDR2_DEFVAL 0x03040001 +#define DDRC_MSTR_LPDDR2_SHIFT 2 +#define DDRC_MSTR_LPDDR2_MASK 0x00000004U -/*Select DDR3 SDRAM - 1 - DDR3 SDRAM device in use - 0 - non-DDR3 SDRAM device in use Only present in designs that support DDR3 - */ +/* +* Select DDR3 SDRAM - 1 - DDR3 SDRAM device in use - 0 - non-DDR3 SDRAM de + * vice in use Only present in designs that support DDR3. +*/ #undef DDRC_MSTR_DDR3_DEFVAL #undef DDRC_MSTR_DDR3_SHIFT #undef DDRC_MSTR_DDR3_MASK -#define DDRC_MSTR_DDR3_DEFVAL 0x03040001 -#define DDRC_MSTR_DDR3_SHIFT 0 -#define DDRC_MSTR_DDR3_MASK 0x00000001U +#define DDRC_MSTR_DDR3_DEFVAL 0x03040001 +#define DDRC_MSTR_DDR3_SHIFT 0 +#define DDRC_MSTR_DDR3_MASK 0x00000001U -/*Setting this register bit to 1 triggers a mode register read or write operation. When the MR operation is complete, the uMCTL - automatically clears this bit. The other register fields of this register must be written in a separate APB transaction, bef - re setting this mr_wr bit. It is recommended NOT to set this signal if in Init, Deep power-down or MPSM operating modes.*/ +/* +* Setting this register bit to 1 triggers a mode register read or write op + * eration. When the MR operation is complete, the uMCTL2 automatically cle + * ars this bit. The other register fields of this register must be written + * in a separate APB transaction, before setting this mr_wr bit. It is rec + * ommended NOT to set this signal if in Init, Deep power-down or MPSM oper + * ating modes. +*/ #undef DDRC_MRCTRL0_MR_WR_DEFVAL #undef DDRC_MRCTRL0_MR_WR_SHIFT #undef DDRC_MRCTRL0_MR_WR_MASK -#define DDRC_MRCTRL0_MR_WR_DEFVAL 0x00000030 -#define DDRC_MRCTRL0_MR_WR_SHIFT 31 -#define DDRC_MRCTRL0_MR_WR_MASK 0x80000000U +#define DDRC_MRCTRL0_MR_WR_DEFVAL 0x00000030 +#define DDRC_MRCTRL0_MR_WR_SHIFT 31 +#define DDRC_MRCTRL0_MR_WR_MASK 0x80000000U -/*Address of the mode register that is to be written to. - 0000 - MR0 - 0001 - MR1 - 0010 - MR2 - 0011 - MR3 - 0100 - MR4 - 010 - - MR5 - 0110 - MR6 - 0111 - MR7 Don't Care for LPDDR2/LPDDR3/LPDDR4 (see MRCTRL1.mr_data for mode register addressing in LPD - R2/LPDDR3/LPDDR4) This signal is also used for writing to control words of RDIMMs. In that case, it corresponds to the bank a - dress bits sent to the RDIMM In case of DDR4, the bit[3:2] corresponds to the bank group bits. Therefore, the bit[3] as well - s the bit[2:0] must be set to an appropriate value which is considered both the Address Mirroring of UDIMMs/RDIMMs and the Ou - put Inversion of RDIMMs.*/ +/* +* Address of the mode register that is to be written to. - 0000 - MR0 - 00 + * 01 - MR1 - 0010 - MR2 - 0011 - MR3 - 0100 - MR4 - 0101 - MR5 - 0110 - MR + * 6 - 0111 - MR7 Don't Care for LPDDR2/LPDDR3/LPDDR4 (see MRCTRL1.mr_data + * for mode register addressing in LPDDR2/LPDDR3/LPDDR4) This signal is als + * o used for writing to control words of RDIMMs. In that case, it correspo + * nds to the bank address bits sent to the RDIMM In case of DDR4, the bit[ + * 3:2] corresponds to the bank group bits. Therefore, the bit[3] as well a + * s the bit[2:0] must be set to an appropriate value which is considered b + * oth the Address Mirroring of UDIMMs/RDIMMs and the Output Inversion of R + * DIMMs. +*/ #undef DDRC_MRCTRL0_MR_ADDR_DEFVAL #undef DDRC_MRCTRL0_MR_ADDR_SHIFT #undef DDRC_MRCTRL0_MR_ADDR_MASK -#define DDRC_MRCTRL0_MR_ADDR_DEFVAL 0x00000030 -#define DDRC_MRCTRL0_MR_ADDR_SHIFT 12 -#define DDRC_MRCTRL0_MR_ADDR_MASK 0x0000F000U +#define DDRC_MRCTRL0_MR_ADDR_DEFVAL 0x00000030 +#define DDRC_MRCTRL0_MR_ADDR_SHIFT 12 +#define DDRC_MRCTRL0_MR_ADDR_MASK 0x0000F000U -/*Controls which rank is accessed by MRCTRL0.mr_wr. Normally, it is desired to access all ranks, so all bits should be set to 1 - However, for multi-rank UDIMMs/RDIMMs which implement address mirroring, it may be necessary to access ranks individually. E - amples (assume uMCTL2 is configured for 4 ranks): - 0x1 - select rank 0 only - 0x2 - select rank 1 only - 0x5 - select ranks - and 2 - 0xA - select ranks 1 and 3 - 0xF - select ranks 0, 1, 2 and 3*/ +/* +* Controls which rank is accessed by MRCTRL0.mr_wr. Normally, it is desire + * d to access all ranks, so all bits should be set to 1. However, for mult + * i-rank UDIMMs/RDIMMs which implement address mirroring, it may be necess + * ary to access ranks individually. Examples (assume uMCTL2 is configured + * for 4 ranks): - 0x1 - select rank 0 only - 0x2 - select rank 1 only - 0x + * 5 - select ranks 0 and 2 - 0xA - select ranks 1 and 3 - 0xF - select ran + * ks 0, 1, 2 and 3 +*/ #undef DDRC_MRCTRL0_MR_RANK_DEFVAL #undef DDRC_MRCTRL0_MR_RANK_SHIFT #undef DDRC_MRCTRL0_MR_RANK_MASK -#define DDRC_MRCTRL0_MR_RANK_DEFVAL 0x00000030 -#define DDRC_MRCTRL0_MR_RANK_SHIFT 4 -#define DDRC_MRCTRL0_MR_RANK_MASK 0x00000030U +#define DDRC_MRCTRL0_MR_RANK_DEFVAL 0x00000030 +#define DDRC_MRCTRL0_MR_RANK_SHIFT 4 +#define DDRC_MRCTRL0_MR_RANK_MASK 0x00000030U -/*Indicates whether Software intervention is allowed via MRCTRL0/MRCTRL1 before automatic SDRAM initialization routine or not. - or DDR4, this bit can be used to initialize the DDR4 RCD (MR7) before automatic SDRAM initialization. For LPDDR4, this bit ca - be used to program additional mode registers before automatic SDRAM initialization if necessary. Note: This must be cleared - o 0 after completing Software operation. Otherwise, SDRAM initialization routine will not re-start. - 0 - Software interventi - n is not allowed - 1 - Software intervention is allowed*/ +/* +* Indicates whether Software intervention is allowed via MRCTRL0/MRCTRL1 b + * efore automatic SDRAM initialization routine or not. For DDR4, this bit + * can be used to initialize the DDR4 RCD (MR7) before automatic SDRAM init + * ialization. For LPDDR4, this bit can be used to program additional mode + * registers before automatic SDRAM initialization if necessary. Note: This + * must be cleared to 0 after completing Software operation. Otherwise, SD + * RAM initialization routine will not re-start. - 0 - Software interventio + * n is not allowed - 1 - Software intervention is allowed +*/ #undef DDRC_MRCTRL0_SW_INIT_INT_DEFVAL #undef DDRC_MRCTRL0_SW_INIT_INT_SHIFT #undef DDRC_MRCTRL0_SW_INIT_INT_MASK -#define DDRC_MRCTRL0_SW_INIT_INT_DEFVAL 0x00000030 -#define DDRC_MRCTRL0_SW_INIT_INT_SHIFT 3 -#define DDRC_MRCTRL0_SW_INIT_INT_MASK 0x00000008U +#define DDRC_MRCTRL0_SW_INIT_INT_DEFVAL 0x00000030 +#define DDRC_MRCTRL0_SW_INIT_INT_SHIFT 3 +#define DDRC_MRCTRL0_SW_INIT_INT_MASK 0x00000008U -/*Indicates whether the mode register operation is MRS in PDA mode or not - 0 - MRS - 1 - MRS in Per DRAM Addressability mode*/ +/* +* Indicates whether the mode register operation is MRS in PDA mode or not + * - 0 - MRS - 1 - MRS in Per DRAM Addressability mode +*/ #undef DDRC_MRCTRL0_PDA_EN_DEFVAL #undef DDRC_MRCTRL0_PDA_EN_SHIFT #undef DDRC_MRCTRL0_PDA_EN_MASK -#define DDRC_MRCTRL0_PDA_EN_DEFVAL 0x00000030 -#define DDRC_MRCTRL0_PDA_EN_SHIFT 2 -#define DDRC_MRCTRL0_PDA_EN_MASK 0x00000004U +#define DDRC_MRCTRL0_PDA_EN_DEFVAL 0x00000030 +#define DDRC_MRCTRL0_PDA_EN_SHIFT 2 +#define DDRC_MRCTRL0_PDA_EN_MASK 0x00000004U -/*Indicates whether the mode register operation is MRS or WR/RD for MPR (only supported for DDR4) - 0 - MRS - 1 - WR/RD for MPR*/ +/* +* Indicates whether the mode register operation is MRS or WR/RD for MPR (o + * nly supported for DDR4) - 0 - MRS - 1 - WR/RD for MPR +*/ #undef DDRC_MRCTRL0_MPR_EN_DEFVAL #undef DDRC_MRCTRL0_MPR_EN_SHIFT #undef DDRC_MRCTRL0_MPR_EN_MASK -#define DDRC_MRCTRL0_MPR_EN_DEFVAL 0x00000030 -#define DDRC_MRCTRL0_MPR_EN_SHIFT 1 -#define DDRC_MRCTRL0_MPR_EN_MASK 0x00000002U +#define DDRC_MRCTRL0_MPR_EN_DEFVAL 0x00000030 +#define DDRC_MRCTRL0_MPR_EN_SHIFT 1 +#define DDRC_MRCTRL0_MPR_EN_MASK 0x00000002U -/*Indicates whether the mode register operation is read or write. Only used for LPDDR2/LPDDR3/LPDDR4/DDR4. - 0 - Write - 1 - Re - d*/ +/* +* Indicates whether the mode register operation is read or write. Only use + * d for LPDDR2/LPDDR3/LPDDR4/DDR4. - 0 - Write - 1 - Read +*/ #undef DDRC_MRCTRL0_MR_TYPE_DEFVAL #undef DDRC_MRCTRL0_MR_TYPE_SHIFT #undef DDRC_MRCTRL0_MR_TYPE_MASK -#define DDRC_MRCTRL0_MR_TYPE_DEFVAL 0x00000030 -#define DDRC_MRCTRL0_MR_TYPE_SHIFT 0 -#define DDRC_MRCTRL0_MR_TYPE_MASK 0x00000001U +#define DDRC_MRCTRL0_MR_TYPE_DEFVAL 0x00000030 +#define DDRC_MRCTRL0_MR_TYPE_SHIFT 0 +#define DDRC_MRCTRL0_MR_TYPE_MASK 0x00000001U -/*Derate value of tRC for LPDDR4 - 0 - Derating uses +1. - 1 - Derating uses +2. - 2 - Derating uses +3. - 3 - Derating uses +4 - Present only in designs configured to support LPDDR4. The required number of cycles for derating can be determined by dividi - g 3.75ns by the core_ddrc_core_clk period, and rounding up the next integer.*/ +/* +* Derate value of tRC for LPDDR4 - 0 - Derating uses +1. - 1 - Derating us + * es +2. - 2 - Derating uses +3. - 3 - Derating uses +4. Present only in d + * esigns configured to support LPDDR4. The required number of cycles for d + * erating can be determined by dividing 3.75ns by the core_ddrc_core_clk p + * eriod, and rounding up the next integer. +*/ #undef DDRC_DERATEEN_RC_DERATE_VALUE_DEFVAL #undef DDRC_DERATEEN_RC_DERATE_VALUE_SHIFT #undef DDRC_DERATEEN_RC_DERATE_VALUE_MASK -#define DDRC_DERATEEN_RC_DERATE_VALUE_DEFVAL 0x00000000 -#define DDRC_DERATEEN_RC_DERATE_VALUE_SHIFT 8 -#define DDRC_DERATEEN_RC_DERATE_VALUE_MASK 0x00000300U +#define DDRC_DERATEEN_RC_DERATE_VALUE_DEFVAL 0x00000000 +#define DDRC_DERATEEN_RC_DERATE_VALUE_SHIFT 8 +#define DDRC_DERATEEN_RC_DERATE_VALUE_MASK 0x00000300U -/*Derate byte Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4 Indicates which byte of the MRR data is used f - r derating. The maximum valid value depends on MEMC_DRAM_TOTAL_DATA_WIDTH.*/ +/* +* Derate byte Present only in designs configured to support LPDDR2/LPDDR3/ + * LPDDR4 Indicates which byte of the MRR data is used for derating. The ma + * ximum valid value depends on MEMC_DRAM_TOTAL_DATA_WIDTH. +*/ #undef DDRC_DERATEEN_DERATE_BYTE_DEFVAL #undef DDRC_DERATEEN_DERATE_BYTE_SHIFT #undef DDRC_DERATEEN_DERATE_BYTE_MASK -#define DDRC_DERATEEN_DERATE_BYTE_DEFVAL 0x00000000 -#define DDRC_DERATEEN_DERATE_BYTE_SHIFT 4 -#define DDRC_DERATEEN_DERATE_BYTE_MASK 0x000000F0U +#define DDRC_DERATEEN_DERATE_BYTE_DEFVAL 0x00000000 +#define DDRC_DERATEEN_DERATE_BYTE_SHIFT 4 +#define DDRC_DERATEEN_DERATE_BYTE_MASK 0x000000F0U -/*Derate value - 0 - Derating uses +1. - 1 - Derating uses +2. Present only in designs configured to support LPDDR2/LPDDR3/LPDD - 4 Set to 0 for all LPDDR2 speed grades as derating value of +1.875 ns is less than a core_ddrc_core_clk period. Can be 0 or 1 - for LPDDR3/LPDDR4, depending if +1.875 ns is less than a core_ddrc_core_clk period or not.*/ +/* +* Derate value - 0 - Derating uses +1. - 1 - Derating uses +2. Present onl + * y in designs configured to support LPDDR2/LPDDR3/LPDDR4 Set to 0 for all + * LPDDR2 speed grades as derating value of +1.875 ns is less than a core_ + * ddrc_core_clk period. Can be 0 or 1 for LPDDR3/LPDDR4, depending if +1.8 + * 75 ns is less than a core_ddrc_core_clk period or not. +*/ #undef DDRC_DERATEEN_DERATE_VALUE_DEFVAL #undef DDRC_DERATEEN_DERATE_VALUE_SHIFT #undef DDRC_DERATEEN_DERATE_VALUE_MASK -#define DDRC_DERATEEN_DERATE_VALUE_DEFVAL 0x00000000 -#define DDRC_DERATEEN_DERATE_VALUE_SHIFT 1 -#define DDRC_DERATEEN_DERATE_VALUE_MASK 0x00000002U +#define DDRC_DERATEEN_DERATE_VALUE_DEFVAL 0x00000000 +#define DDRC_DERATEEN_DERATE_VALUE_SHIFT 1 +#define DDRC_DERATEEN_DERATE_VALUE_MASK 0x00000002U -/*Enables derating - 0 - Timing parameter derating is disabled - 1 - Timing parameter derating is enabled using MR4 read value. - Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4 This field must be set to '0' for non-LPDDR2/LPDDR3/LPDDR4 - mode.*/ +/* +* Enables derating - 0 - Timing parameter derating is disabled - 1 - Timin + * g parameter derating is enabled using MR4 read value. Present only in de + * signs configured to support LPDDR2/LPDDR3/LPDDR4 This field must be set + * to '0' for non-LPDDR2/LPDDR3/LPDDR4 mode. +*/ #undef DDRC_DERATEEN_DERATE_ENABLE_DEFVAL #undef DDRC_DERATEEN_DERATE_ENABLE_SHIFT #undef DDRC_DERATEEN_DERATE_ENABLE_MASK -#define DDRC_DERATEEN_DERATE_ENABLE_DEFVAL 0x00000000 -#define DDRC_DERATEEN_DERATE_ENABLE_SHIFT 0 -#define DDRC_DERATEEN_DERATE_ENABLE_MASK 0x00000001U +#define DDRC_DERATEEN_DERATE_ENABLE_DEFVAL 0x00000000 +#define DDRC_DERATEEN_DERATE_ENABLE_SHIFT 0 +#define DDRC_DERATEEN_DERATE_ENABLE_MASK 0x00000001U -/*Interval between two MR4 reads, used to derate the timing parameters. Present only in designs configured to support LPDDR2/LP - DR3/LPDDR4. This register must not be set to zero*/ +/* +* Interval between two MR4 reads, used to derate the timing parameters. Pr + * esent only in designs configured to support LPDDR2/LPDDR3/LPDDR4. This r + * egister must not be set to zero +*/ #undef DDRC_DERATEINT_MR4_READ_INTERVAL_DEFVAL #undef DDRC_DERATEINT_MR4_READ_INTERVAL_SHIFT #undef DDRC_DERATEINT_MR4_READ_INTERVAL_MASK -#define DDRC_DERATEINT_MR4_READ_INTERVAL_DEFVAL -#define DDRC_DERATEINT_MR4_READ_INTERVAL_SHIFT 0 -#define DDRC_DERATEINT_MR4_READ_INTERVAL_MASK 0xFFFFFFFFU +#define DDRC_DERATEINT_MR4_READ_INTERVAL_DEFVAL +#define DDRC_DERATEINT_MR4_READ_INTERVAL_SHIFT 0 +#define DDRC_DERATEINT_MR4_READ_INTERVAL_MASK 0xFFFFFFFFU -/*Self refresh state is an intermediate state to enter to Self refresh power down state or exit Self refresh power down state f - r LPDDR4. This register controls transition from the Self refresh state. - 1 - Prohibit transition from Self refresh state - - - Allow transition from Self refresh state*/ +/* +* Self refresh state is an intermediate state to enter to Self refresh pow + * er down state or exit Self refresh power down state for LPDDR4. This reg + * ister controls transition from the Self refresh state. - 1 - Prohibit tr + * ansition from Self refresh state - 0 - Allow transition from Self refres + * h state +*/ #undef DDRC_PWRCTL_STAY_IN_SELFREF_DEFVAL #undef DDRC_PWRCTL_STAY_IN_SELFREF_SHIFT #undef DDRC_PWRCTL_STAY_IN_SELFREF_MASK -#define DDRC_PWRCTL_STAY_IN_SELFREF_DEFVAL 0x00000000 -#define DDRC_PWRCTL_STAY_IN_SELFREF_SHIFT 6 -#define DDRC_PWRCTL_STAY_IN_SELFREF_MASK 0x00000040U +#define DDRC_PWRCTL_STAY_IN_SELFREF_DEFVAL 0x00000000 +#define DDRC_PWRCTL_STAY_IN_SELFREF_SHIFT 6 +#define DDRC_PWRCTL_STAY_IN_SELFREF_MASK 0x00000040U -/*A value of 1 to this register causes system to move to Self Refresh state immediately, as long as it is not in INIT or DPD/MP - M operating_mode. This is referred to as Software Entry/Exit to Self Refresh. - 1 - Software Entry to Self Refresh - 0 - Soft - are Exit from Self Refresh*/ +/* +* A value of 1 to this register causes system to move to Self Refresh stat + * e immediately, as long as it is not in INIT or DPD/MPSM operating_mode. + * This is referred to as Software Entry/Exit to Self Refresh. - 1 - Softwa + * re Entry to Self Refresh - 0 - Software Exit from Self Refresh +*/ #undef DDRC_PWRCTL_SELFREF_SW_DEFVAL #undef DDRC_PWRCTL_SELFREF_SW_SHIFT #undef DDRC_PWRCTL_SELFREF_SW_MASK -#define DDRC_PWRCTL_SELFREF_SW_DEFVAL 0x00000000 -#define DDRC_PWRCTL_SELFREF_SW_SHIFT 5 -#define DDRC_PWRCTL_SELFREF_SW_MASK 0x00000020U +#define DDRC_PWRCTL_SELFREF_SW_DEFVAL 0x00000000 +#define DDRC_PWRCTL_SELFREF_SW_SHIFT 5 +#define DDRC_PWRCTL_SELFREF_SW_MASK 0x00000020U -/*When this is 1, the uMCTL2 puts the SDRAM into maximum power saving mode when the transaction store is empty. This register m - st be reset to '0' to bring uMCTL2 out of maximum power saving mode. Present only in designs configured to support DDR4. For - on-DDR4, this register should not be set to 1. Note that MPSM is not supported when using a DWC DDR PHY, if the PHY parameter - DWC_AC_CS_USE is disabled, as the MPSM exit sequence requires the chip-select signal to toggle. FOR PERFORMANCE ONLY.*/ +/* +* When this is 1, the uMCTL2 puts the SDRAM into maximum power saving mode + * when the transaction store is empty. This register must be reset to '0' + * to bring uMCTL2 out of maximum power saving mode. Present only in desig + * ns configured to support DDR4. For non-DDR4, this register should not be + * set to 1. Note that MPSM is not supported when using a DWC DDR PHY, if + * the PHY parameter DWC_AC_CS_USE is disabled, as the MPSM exit sequence r + * equires the chip-select signal to toggle. FOR PERFORMANCE ONLY. +*/ #undef DDRC_PWRCTL_MPSM_EN_DEFVAL #undef DDRC_PWRCTL_MPSM_EN_SHIFT #undef DDRC_PWRCTL_MPSM_EN_MASK -#define DDRC_PWRCTL_MPSM_EN_DEFVAL 0x00000000 -#define DDRC_PWRCTL_MPSM_EN_SHIFT 4 -#define DDRC_PWRCTL_MPSM_EN_MASK 0x00000010U +#define DDRC_PWRCTL_MPSM_EN_DEFVAL 0x00000000 +#define DDRC_PWRCTL_MPSM_EN_SHIFT 4 +#define DDRC_PWRCTL_MPSM_EN_MASK 0x00000010U -/*Enable the assertion of dfi_dram_clk_disable whenever a clock is not required by the SDRAM. If set to 0, dfi_dram_clk_disable - is never asserted. Assertion of dfi_dram_clk_disable is as follows: In DDR2/DDR3, can only be asserted in Self Refresh. In DD - 4, can be asserted in following: - in Self Refresh. - in Maximum Power Saving Mode In mDDR/LPDDR2/LPDDR3, can be asserted in - ollowing: - in Self Refresh - in Power Down - in Deep Power Down - during Normal operation (Clock Stop) In LPDDR4, can be ass - rted in following: - in Self Refresh Power Down - in Power Down - during Normal operation (Clock Stop)*/ +/* +* Enable the assertion of dfi_dram_clk_disable whenever a clock is not req + * uired by the SDRAM. If set to 0, dfi_dram_clk_disable is never asserted. + * Assertion of dfi_dram_clk_disable is as follows: In DDR2/DDR3, can only + * be asserted in Self Refresh. In DDR4, can be asserted in following: - i + * n Self Refresh. - in Maximum Power Saving Mode In mDDR/LPDDR2/LPDDR3, ca + * n be asserted in following: - in Self Refresh - in Power Down - in Deep + * Power Down - during Normal operation (Clock Stop) In LPDDR4, can be asse + * rted in following: - in Self Refresh Power Down - in Power Down - during + * Normal operation (Clock Stop) +*/ #undef DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_DEFVAL #undef DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_SHIFT #undef DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_MASK -#define DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_DEFVAL 0x00000000 -#define DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_SHIFT 3 -#define DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_MASK 0x00000008U +#define DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_DEFVAL 0x00000000 +#define DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_SHIFT 3 +#define DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_MASK 0x00000008U -/*When this is 1, uMCTL2 puts the SDRAM into deep power-down mode when the transaction store is empty. This register must be re - et to '0' to bring uMCTL2 out of deep power-down mode. Controller performs automatic SDRAM initialization on deep power-down - xit. Present only in designs configured to support mDDR or LPDDR2 or LPDDR3. For non-mDDR/non-LPDDR2/non-LPDDR3, this registe - should not be set to 1. FOR PERFORMANCE ONLY.*/ +/* +* When this is 1, uMCTL2 puts the SDRAM into deep power-down mode when the + * transaction store is empty. This register must be reset to '0' to bring + * uMCTL2 out of deep power-down mode. Controller performs automatic SDRAM + * initialization on deep power-down exit. Present only in designs configu + * red to support mDDR or LPDDR2 or LPDDR3. For non-mDDR/non-LPDDR2/non-LPD + * DR3, this register should not be set to 1. FOR PERFORMANCE ONLY. +*/ #undef DDRC_PWRCTL_DEEPPOWERDOWN_EN_DEFVAL #undef DDRC_PWRCTL_DEEPPOWERDOWN_EN_SHIFT #undef DDRC_PWRCTL_DEEPPOWERDOWN_EN_MASK -#define DDRC_PWRCTL_DEEPPOWERDOWN_EN_DEFVAL 0x00000000 -#define DDRC_PWRCTL_DEEPPOWERDOWN_EN_SHIFT 2 -#define DDRC_PWRCTL_DEEPPOWERDOWN_EN_MASK 0x00000004U +#define DDRC_PWRCTL_DEEPPOWERDOWN_EN_DEFVAL 0x00000000 +#define DDRC_PWRCTL_DEEPPOWERDOWN_EN_SHIFT 2 +#define DDRC_PWRCTL_DEEPPOWERDOWN_EN_MASK 0x00000004U -/*If true then the uMCTL2 goes into power-down after a programmable number of cycles 'maximum idle clocks before power down' (P - RTMG.powerdown_to_x32). This register bit may be re-programmed during the course of normal operation.*/ +/* +* If true then the uMCTL2 goes into power-down after a programmable number + * of cycles 'maximum idle clocks before power down' (PWRTMG.powerdown_to_ + * x32). This register bit may be re-programmed during the course of normal + * operation. +*/ #undef DDRC_PWRCTL_POWERDOWN_EN_DEFVAL #undef DDRC_PWRCTL_POWERDOWN_EN_SHIFT #undef DDRC_PWRCTL_POWERDOWN_EN_MASK -#define DDRC_PWRCTL_POWERDOWN_EN_DEFVAL 0x00000000 -#define DDRC_PWRCTL_POWERDOWN_EN_SHIFT 1 -#define DDRC_PWRCTL_POWERDOWN_EN_MASK 0x00000002U +#define DDRC_PWRCTL_POWERDOWN_EN_DEFVAL 0x00000000 +#define DDRC_PWRCTL_POWERDOWN_EN_SHIFT 1 +#define DDRC_PWRCTL_POWERDOWN_EN_MASK 0x00000002U -/*If true then the uMCTL2 puts the SDRAM into Self Refresh after a programmable number of cycles 'maximum idle clocks before Se - f Refresh (PWRTMG.selfref_to_x32)'. This register bit may be re-programmed during the course of normal operation.*/ +/* +* If true then the uMCTL2 puts the SDRAM into Self Refresh after a program + * mable number of cycles 'maximum idle clocks before Self Refresh (PWRTMG. + * selfref_to_x32)'. This register bit may be re-programmed during the cour + * se of normal operation. +*/ #undef DDRC_PWRCTL_SELFREF_EN_DEFVAL #undef DDRC_PWRCTL_SELFREF_EN_SHIFT #undef DDRC_PWRCTL_SELFREF_EN_MASK -#define DDRC_PWRCTL_SELFREF_EN_DEFVAL 0x00000000 -#define DDRC_PWRCTL_SELFREF_EN_SHIFT 0 -#define DDRC_PWRCTL_SELFREF_EN_MASK 0x00000001U +#define DDRC_PWRCTL_SELFREF_EN_DEFVAL 0x00000000 +#define DDRC_PWRCTL_SELFREF_EN_SHIFT 0 +#define DDRC_PWRCTL_SELFREF_EN_MASK 0x00000001U -/*After this many clocks of NOP or deselect the uMCTL2 automatically puts the SDRAM into Self Refresh. This must be enabled in - he PWRCTL.selfref_en. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY.*/ +/* +* After this many clocks of NOP or deselect the uMCTL2 automatically puts + * the SDRAM into Self Refresh. This must be enabled in the PWRCTL.selfref_ + * en. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY. +*/ #undef DDRC_PWRTMG_SELFREF_TO_X32_DEFVAL #undef DDRC_PWRTMG_SELFREF_TO_X32_SHIFT #undef DDRC_PWRTMG_SELFREF_TO_X32_MASK -#define DDRC_PWRTMG_SELFREF_TO_X32_DEFVAL 0x00402010 -#define DDRC_PWRTMG_SELFREF_TO_X32_SHIFT 16 -#define DDRC_PWRTMG_SELFREF_TO_X32_MASK 0x00FF0000U +#define DDRC_PWRTMG_SELFREF_TO_X32_DEFVAL 0x00402010 +#define DDRC_PWRTMG_SELFREF_TO_X32_SHIFT 16 +#define DDRC_PWRTMG_SELFREF_TO_X32_MASK 0x00FF0000U -/*Minimum deep power-down time. For mDDR, value from the JEDEC specification is 0 as mDDR exits from deep power-down mode immed - ately after PWRCTL.deeppowerdown_en is de-asserted. For LPDDR2/LPDDR3, value from the JEDEC specification is 500us. Unit: Mul - iples of 4096 clocks. Present only in designs configured to support mDDR, LPDDR2 or LPDDR3. FOR PERFORMANCE ONLY.*/ +/* +* Minimum deep power-down time. For mDDR, value from the JEDEC specificati + * on is 0 as mDDR exits from deep power-down mode immediately after PWRCTL + * .deeppowerdown_en is de-asserted. For LPDDR2/LPDDR3, value from the JEDE + * C specification is 500us. Unit: Multiples of 4096 clocks. Present only i + * n designs configured to support mDDR, LPDDR2 or LPDDR3. FOR PERFORMANCE + * ONLY. +*/ #undef DDRC_PWRTMG_T_DPD_X4096_DEFVAL #undef DDRC_PWRTMG_T_DPD_X4096_SHIFT #undef DDRC_PWRTMG_T_DPD_X4096_MASK -#define DDRC_PWRTMG_T_DPD_X4096_DEFVAL 0x00402010 -#define DDRC_PWRTMG_T_DPD_X4096_SHIFT 8 -#define DDRC_PWRTMG_T_DPD_X4096_MASK 0x0000FF00U +#define DDRC_PWRTMG_T_DPD_X4096_DEFVAL 0x00402010 +#define DDRC_PWRTMG_T_DPD_X4096_SHIFT 8 +#define DDRC_PWRTMG_T_DPD_X4096_MASK 0x0000FF00U -/*After this many clocks of NOP or deselect the uMCTL2 automatically puts the SDRAM into power-down. This must be enabled in th - PWRCTL.powerdown_en. Unit: Multiples of 32 clocks FOR PERFORMANCE ONLY.*/ +/* +* After this many clocks of NOP or deselect the uMCTL2 automatically puts + * the SDRAM into power-down. This must be enabled in the PWRCTL.powerdown_ + * en. Unit: Multiples of 32 clocks FOR PERFORMANCE ONLY. +*/ #undef DDRC_PWRTMG_POWERDOWN_TO_X32_DEFVAL #undef DDRC_PWRTMG_POWERDOWN_TO_X32_SHIFT #undef DDRC_PWRTMG_POWERDOWN_TO_X32_MASK -#define DDRC_PWRTMG_POWERDOWN_TO_X32_DEFVAL 0x00402010 -#define DDRC_PWRTMG_POWERDOWN_TO_X32_SHIFT 0 -#define DDRC_PWRTMG_POWERDOWN_TO_X32_MASK 0x0000001FU +#define DDRC_PWRTMG_POWERDOWN_TO_X32_DEFVAL 0x00402010 +#define DDRC_PWRTMG_POWERDOWN_TO_X32_SHIFT 0 +#define DDRC_PWRTMG_POWERDOWN_TO_X32_MASK 0x0000001FU -/*Threshold value in number of clock cycles before the critical refresh or page timer expires. A critical refresh is to be issu - d before this threshold is reached. It is recommended that this not be changed from the default value, currently shown as 0x2 - It must always be less than internally used t_rfc_nom_x32. Note that, in LPDDR2/LPDDR3/LPDDR4, internally used t_rfc_nom_x32 - may be equal to RFSHTMG.t_rfc_nom_x32>>2 if derating is enabled (DERATEEN.derate_enable=1). Otherwise, internally used t_rfc_ - om_x32 will be equal to RFSHTMG.t_rfc_nom_x32. Unit: Multiples of 32 clocks.*/ +/* +* Threshold value in number of clock cycles before the critical refresh or + * page timer expires. A critical refresh is to be issued before this thre + * shold is reached. It is recommended that this not be changed from the de + * fault value, currently shown as 0x2. It must always be less than interna + * lly used t_rfc_nom_x32. Note that, in LPDDR2/LPDDR3/LPDDR4, internally u + * sed t_rfc_nom_x32 may be equal to RFSHTMG.t_rfc_nom_x32>>2 if derating i + * s enabled (DERATEEN.derate_enable=1). Otherwise, internally used t_rfc_n + * om_x32 will be equal to RFSHTMG.t_rfc_nom_x32. Unit: Multiples of 32 clo + * cks. +*/ #undef DDRC_RFSHCTL0_REFRESH_MARGIN_DEFVAL #undef DDRC_RFSHCTL0_REFRESH_MARGIN_SHIFT #undef DDRC_RFSHCTL0_REFRESH_MARGIN_MASK -#define DDRC_RFSHCTL0_REFRESH_MARGIN_DEFVAL 0x00210000 -#define DDRC_RFSHCTL0_REFRESH_MARGIN_SHIFT 20 -#define DDRC_RFSHCTL0_REFRESH_MARGIN_MASK 0x00F00000U +#define DDRC_RFSHCTL0_REFRESH_MARGIN_DEFVAL 0x00210000 +#define DDRC_RFSHCTL0_REFRESH_MARGIN_SHIFT 20 +#define DDRC_RFSHCTL0_REFRESH_MARGIN_MASK 0x00F00000U -/*If the refresh timer (tRFCnom, also known as tREFI) has expired at least once, but it has not expired (RFSHCTL0.refresh_burst - 1) times yet, then a speculative refresh may be performed. A speculative refresh is a refresh performed at a time when refres - would be useful, but before it is absolutely required. When the SDRAM bus is idle for a period of time determined by this RF - HCTL0.refresh_to_x32 and the refresh timer has expired at least once since the last refresh, then a speculative refresh is pe - formed. Speculative refreshes continues successively until there are no refreshes pending or until new reads or writes are is - ued to the uMCTL2. FOR PERFORMANCE ONLY.*/ +/* +* If the refresh timer (tRFCnom, also known as tREFI) has expired at least + * once, but it has not expired (RFSHCTL0.refresh_burst+1) times yet, then + * a speculative refresh may be performed. A speculative refresh is a refr + * esh performed at a time when refresh would be useful, but before it is a + * bsolutely required. When the SDRAM bus is idle for a period of time dete + * rmined by this RFSHCTL0.refresh_to_x32 and the refresh timer has expired + * at least once since the last refresh, then a speculative refresh is per + * formed. Speculative refreshes continues successively until there are no + * refreshes pending or until new reads or writes are issued to the uMCTL2. + * FOR PERFORMANCE ONLY. +*/ #undef DDRC_RFSHCTL0_REFRESH_TO_X32_DEFVAL #undef DDRC_RFSHCTL0_REFRESH_TO_X32_SHIFT #undef DDRC_RFSHCTL0_REFRESH_TO_X32_MASK -#define DDRC_RFSHCTL0_REFRESH_TO_X32_DEFVAL 0x00210000 -#define DDRC_RFSHCTL0_REFRESH_TO_X32_SHIFT 12 -#define DDRC_RFSHCTL0_REFRESH_TO_X32_MASK 0x0001F000U +#define DDRC_RFSHCTL0_REFRESH_TO_X32_DEFVAL 0x00210000 +#define DDRC_RFSHCTL0_REFRESH_TO_X32_SHIFT 12 +#define DDRC_RFSHCTL0_REFRESH_TO_X32_MASK 0x0001F000U -/*The programmed value + 1 is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the re - reshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of re - reshes. Therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for - RFSHCTL.refresh_burst slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshe - . - 0 - single refresh - 1 - burst-of-2 refresh - 7 - burst-of-8 refresh For information on burst refresh feature refer to se - tion 3.9 of DDR2 JEDEC specification - JESD79-2F.pdf. For DDR2/3, the refresh is always per-rank and not per-bank. The rank r - fresh can be accumulated over 8*tREFI cycles using the burst refresh feature. In DDR4 mode, according to Fine Granularity fea - ure, 8 refreshes can be postponed in 1X mode, 16 refreshes in 2X mode and 32 refreshes in 4X mode. If using PHY-initiated upd - tes, care must be taken in the setting of RFSHCTL0.refresh_burst, to ensure that tRFCmax is not violated due to a PHY-initiat - d update occurring shortly before a refresh burst was due. In this situation, the refresh burst will be delayed until the PHY - initiated update is complete.*/ +/* +* The programmed value + 1 is the number of refresh timeouts that is allow + * ed to accumulate before traffic is blocked and the refreshes are forced + * to execute. Closing pages to perform a refresh is a one-time penalty tha + * t must be paid for each group of refreshes. Therefore, performing refres + * hes in a burst reduces the per-refresh penalty of these page closings. H + * igher numbers for RFSHCTL.refresh_burst slightly increases utilization; + * lower numbers decreases the worst-case latency associated with refreshes + * . - 0 - single refresh - 1 - burst-of-2 refresh - 7 - burst-of-8 refresh + * For information on burst refresh feature refer to section 3.9 of DDR2 J + * EDEC specification - JESD79-2F.pdf. For DDR2/3, the refresh is always pe + * r-rank and not per-bank. The rank refresh can be accumulated over 8*tREF + * I cycles using the burst refresh feature. In DDR4 mode, according to Fin + * e Granularity feature, 8 refreshes can be postponed in 1X mode, 16 refre + * shes in 2X mode and 32 refreshes in 4X mode. If using PHY-initiated upda + * tes, care must be taken in the setting of RFSHCTL0.refresh_burst, to ens + * ure that tRFCmax is not violated due to a PHY-initiated update occurring + * shortly before a refresh burst was due. In this situation, the refresh + * burst will be delayed until the PHY-initiated update is complete. +*/ #undef DDRC_RFSHCTL0_REFRESH_BURST_DEFVAL #undef DDRC_RFSHCTL0_REFRESH_BURST_SHIFT #undef DDRC_RFSHCTL0_REFRESH_BURST_MASK -#define DDRC_RFSHCTL0_REFRESH_BURST_DEFVAL 0x00210000 -#define DDRC_RFSHCTL0_REFRESH_BURST_SHIFT 4 -#define DDRC_RFSHCTL0_REFRESH_BURST_MASK 0x000001F0U +#define DDRC_RFSHCTL0_REFRESH_BURST_DEFVAL 0x00210000 +#define DDRC_RFSHCTL0_REFRESH_BURST_SHIFT 4 +#define DDRC_RFSHCTL0_REFRESH_BURST_MASK 0x000001F0U -/*- 1 - Per bank refresh; - 0 - All bank refresh. Per bank refresh allows traffic to flow to other banks. Per bank refresh is n - t supported by all LPDDR2 devices but should be supported by all LPDDR3/LPDDR4 devices. Present only in designs configured to - support LPDDR2/LPDDR3/LPDDR4*/ +/* +* - 1 - Per bank refresh; - 0 - All bank refresh. Per bank refresh allows + * traffic to flow to other banks. Per bank refresh is not supported by all + * LPDDR2 devices but should be supported by all LPDDR3/LPDDR4 devices. Pr + * esent only in designs configured to support LPDDR2/LPDDR3/LPDDR4 +*/ #undef DDRC_RFSHCTL0_PER_BANK_REFRESH_DEFVAL #undef DDRC_RFSHCTL0_PER_BANK_REFRESH_SHIFT #undef DDRC_RFSHCTL0_PER_BANK_REFRESH_MASK -#define DDRC_RFSHCTL0_PER_BANK_REFRESH_DEFVAL 0x00210000 -#define DDRC_RFSHCTL0_PER_BANK_REFRESH_SHIFT 2 -#define DDRC_RFSHCTL0_PER_BANK_REFRESH_MASK 0x00000004U +#define DDRC_RFSHCTL0_PER_BANK_REFRESH_DEFVAL 0x00210000 +#define DDRC_RFSHCTL0_PER_BANK_REFRESH_SHIFT 2 +#define DDRC_RFSHCTL0_PER_BANK_REFRESH_MASK 0x00000004U -/*Fine Granularity Refresh Mode - 000 - Fixed 1x (Normal mode) - 001 - Fixed 2x - 010 - Fixed 4x - 101 - Enable on the fly 2x ( - ot supported) - 110 - Enable on the fly 4x (not supported) - Everything else - reserved Note: The on-the-fly modes is not sup - orted in this version of the uMCTL2. Note: This must be set up while the Controller is in reset or while the Controller is in - self-refresh mode. Changing this during normal operation is not allowed. Making this a dynamic register will be supported in - uture version of the uMCTL2.*/ +/* +* Refresh timer start for rank 1 (only present in multi-rank configuration + * s). This is useful in staggering the refreshes to multiple ranks to help + * traffic to proceed. This is explained in Refresh Controls section of ar + * chitecture chapter. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY. +*/ +#undef DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_DEFVAL +#undef DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_SHIFT +#undef DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_MASK +#define DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_DEFVAL 0x00000000 +#define DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_SHIFT 16 +#define DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_MASK 0x0FFF0000U + +/* +* Refresh timer start for rank 0 (only present in multi-rank configuration + * s). This is useful in staggering the refreshes to multiple ranks to help + * traffic to proceed. This is explained in Refresh Controls section of ar + * chitecture chapter. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY. +*/ +#undef DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_DEFVAL +#undef DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_SHIFT +#undef DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_MASK +#define DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_DEFVAL 0x00000000 +#define DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_SHIFT 0 +#define DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_MASK 0x00000FFFU + +/* +* Fine Granularity Refresh Mode - 000 - Fixed 1x (Normal mode) - 001 - Fix + * ed 2x - 010 - Fixed 4x - 101 - Enable on the fly 2x (not supported) - 11 + * 0 - Enable on the fly 4x (not supported) - Everything else - reserved No + * te: The on-the-fly modes is not supported in this version of the uMCTL2. + * Note: This must be set up while the Controller is in reset or while the + * Controller is in self-refresh mode. Changing this during normal operati + * on is not allowed. Making this a dynamic register will be supported in f + * uture version of the uMCTL2. +*/ #undef DDRC_RFSHCTL3_REFRESH_MODE_DEFVAL #undef DDRC_RFSHCTL3_REFRESH_MODE_SHIFT #undef DDRC_RFSHCTL3_REFRESH_MODE_MASK -#define DDRC_RFSHCTL3_REFRESH_MODE_DEFVAL 0x00000000 -#define DDRC_RFSHCTL3_REFRESH_MODE_SHIFT 4 -#define DDRC_RFSHCTL3_REFRESH_MODE_MASK 0x00000070U +#define DDRC_RFSHCTL3_REFRESH_MODE_DEFVAL 0x00000000 +#define DDRC_RFSHCTL3_REFRESH_MODE_SHIFT 4 +#define DDRC_RFSHCTL3_REFRESH_MODE_MASK 0x00000070U -/*Toggle this signal (either from 0 to 1 or from 1 to 0) to indicate that the refresh register(s) have been updated. The value - s automatically updated when exiting reset, so it does not need to be toggled initially.*/ +/* +* Toggle this signal (either from 0 to 1 or from 1 to 0) to indicate that + * the refresh register(s) have been updated. The value is automatically up + * dated when exiting reset, so it does not need to be toggled initially. +*/ #undef DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_DEFVAL #undef DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_SHIFT #undef DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_MASK -#define DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_DEFVAL 0x00000000 -#define DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_SHIFT 1 -#define DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_MASK 0x00000002U +#define DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_DEFVAL 0x00000000 +#define DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_SHIFT 1 +#define DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_MASK 0x00000002U -/*When '1', disable auto-refresh generated by the uMCTL2. When auto-refresh is disabled, the SoC core must generate refreshes u - ing the registers reg_ddrc_rank0_refresh, reg_ddrc_rank1_refresh, reg_ddrc_rank2_refresh and reg_ddrc_rank3_refresh. When dis - auto_refresh transitions from 0 to 1, any pending refreshes are immediately scheduled by the uMCTL2. If DDR4 CRC/parity retry - is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), disable auto-refresh is not supported, and this bit must be set to '0'. - his register field is changeable on the fly.*/ +/* +* When '1', disable auto-refresh generated by the uMCTL2. When auto-refres + * h is disabled, the SoC core must generate refreshes using the registers + * reg_ddrc_rank0_refresh, reg_ddrc_rank1_refresh, reg_ddrc_rank2_refresh a + * nd reg_ddrc_rank3_refresh. When dis_auto_refresh transitions from 0 to 1 + * , any pending refreshes are immediately scheduled by the uMCTL2. If DDR4 + * CRC/parity retry is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), d + * isable auto-refresh is not supported, and this bit must be set to '0'. T + * his register field is changeable on the fly. +*/ #undef DDRC_RFSHCTL3_DIS_AUTO_REFRESH_DEFVAL #undef DDRC_RFSHCTL3_DIS_AUTO_REFRESH_SHIFT #undef DDRC_RFSHCTL3_DIS_AUTO_REFRESH_MASK -#define DDRC_RFSHCTL3_DIS_AUTO_REFRESH_DEFVAL 0x00000000 -#define DDRC_RFSHCTL3_DIS_AUTO_REFRESH_SHIFT 0 -#define DDRC_RFSHCTL3_DIS_AUTO_REFRESH_MASK 0x00000001U +#define DDRC_RFSHCTL3_DIS_AUTO_REFRESH_DEFVAL 0x00000000 +#define DDRC_RFSHCTL3_DIS_AUTO_REFRESH_SHIFT 0 +#define DDRC_RFSHCTL3_DIS_AUTO_REFRESH_MASK 0x00000001U -/*tREFI: Average time interval between refreshes per rank (Specification: 7.8us for DDR2, DDR3 and DDR4. See JEDEC specificatio - for mDDR, LPDDR2, LPDDR3 and LPDDR4). For LPDDR2/LPDDR3/LPDDR4: - if using all-bank refreshes (RFSHCTL0.per_bank_refresh = 0 - , this register should be set to tREFIab - if using per-bank refreshes (RFSHCTL0.per_bank_refresh = 1), this register should - e set to tREFIpb For configurations with MEMC_FREQ_RATIO=2, program this to (tREFI/2), no rounding up. In DDR4 mode, tREFI va - ue is different depending on the refresh mode. The user should program the appropriate value from the spec based on the value - programmed in the refresh mode register. Note that RFSHTMG.t_rfc_nom_x32 * 32 must be greater than RFSHTMG.t_rfc_min, and RFS - TMG.t_rfc_nom_x32 must be greater than 0x1. Unit: Multiples of 32 clocks.*/ +/* +* tREFI: Average time interval between refreshes per rank (Specification: + * 7.8us for DDR2, DDR3 and DDR4. See JEDEC specification for mDDR, LPDDR2, + * LPDDR3 and LPDDR4). For LPDDR2/LPDDR3/LPDDR4: - if using all-bank refre + * shes (RFSHCTL0.per_bank_refresh = 0), this register should be set to tRE + * FIab - if using per-bank refreshes (RFSHCTL0.per_bank_refresh = 1), this + * register should be set to tREFIpb For configurations with MEMC_FREQ_RAT + * IO=2, program this to (tREFI/2), no rounding up. In DDR4 mode, tREFI val + * ue is different depending on the refresh mode. The user should program t + * he appropriate value from the spec based on the value programmed in the + * refresh mode register. Note that RFSHTMG.t_rfc_nom_x32 * 32 must be grea + * ter than RFSHTMG.t_rfc_min, and RFSHTMG.t_rfc_nom_x32 must be greater th + * an 0x1. Unit: Multiples of 32 clocks. +*/ #undef DDRC_RFSHTMG_T_RFC_NOM_X32_DEFVAL #undef DDRC_RFSHTMG_T_RFC_NOM_X32_SHIFT #undef DDRC_RFSHTMG_T_RFC_NOM_X32_MASK -#define DDRC_RFSHTMG_T_RFC_NOM_X32_DEFVAL 0x0062008C -#define DDRC_RFSHTMG_T_RFC_NOM_X32_SHIFT 16 -#define DDRC_RFSHTMG_T_RFC_NOM_X32_MASK 0x0FFF0000U +#define DDRC_RFSHTMG_T_RFC_NOM_X32_DEFVAL 0x0062008C +#define DDRC_RFSHTMG_T_RFC_NOM_X32_SHIFT 16 +#define DDRC_RFSHTMG_T_RFC_NOM_X32_MASK 0x0FFF0000U -/*Used only when LPDDR3 memory type is connected. Should only be changed when uMCTL2 is in reset. Specifies whether to use the - REFBW parameter (required by some LPDDR3 devices which comply with earlier versions of the LPDDR3 JEDEC specification) or not - - 0 - tREFBW parameter not used - 1 - tREFBW parameter used*/ +/* +* Used only when LPDDR3 memory type is connected. Should only be changed w + * hen uMCTL2 is in reset. Specifies whether to use the tREFBW parameter (r + * equired by some LPDDR3 devices which comply with earlier versions of the + * LPDDR3 JEDEC specification) or not: - 0 - tREFBW parameter not used - 1 + * - tREFBW parameter used +*/ #undef DDRC_RFSHTMG_LPDDR3_TREFBW_EN_DEFVAL #undef DDRC_RFSHTMG_LPDDR3_TREFBW_EN_SHIFT #undef DDRC_RFSHTMG_LPDDR3_TREFBW_EN_MASK -#define DDRC_RFSHTMG_LPDDR3_TREFBW_EN_DEFVAL 0x0062008C -#define DDRC_RFSHTMG_LPDDR3_TREFBW_EN_SHIFT 15 -#define DDRC_RFSHTMG_LPDDR3_TREFBW_EN_MASK 0x00008000U +#define DDRC_RFSHTMG_LPDDR3_TREFBW_EN_DEFVAL 0x0062008C +#define DDRC_RFSHTMG_LPDDR3_TREFBW_EN_SHIFT 15 +#define DDRC_RFSHTMG_LPDDR3_TREFBW_EN_MASK 0x00008000U -/*tRFC (min): Minimum time from refresh to refresh or activate. For MEMC_FREQ_RATIO=1 configurations, t_rfc_min should be set t - RoundUp(tRFCmin/tCK). For MEMC_FREQ_RATIO=2 configurations, t_rfc_min should be set to RoundUp(RoundUp(tRFCmin/tCK)/2). In L - DDR2/LPDDR3/LPDDR4 mode: - if using all-bank refreshes, the tRFCmin value in the above equations is equal to tRFCab - if usin - per-bank refreshes, the tRFCmin value in the above equations is equal to tRFCpb In DDR4 mode, the tRFCmin value in the above - equations is different depending on the refresh mode (fixed 1X,2X,4X) and the device density. The user should program the app - opriate value from the spec based on the 'refresh_mode' and the device density that is used. Unit: Clocks.*/ +/* +* tRFC (min): Minimum time from refresh to refresh or activate. For MEMC_F + * REQ_RATIO=1 configurations, t_rfc_min should be set to RoundUp(tRFCmin/t + * CK). For MEMC_FREQ_RATIO=2 configurations, t_rfc_min should be set to Ro + * undUp(RoundUp(tRFCmin/tCK)/2). In LPDDR2/LPDDR3/LPDDR4 mode: - if using + * all-bank refreshes, the tRFCmin value in the above equations is equal to + * tRFCab - if using per-bank refreshes, the tRFCmin value in the above eq + * uations is equal to tRFCpb In DDR4 mode, the tRFCmin value in the above + * equations is different depending on the refresh mode (fixed 1X,2X,4X) an + * d the device density. The user should program the appropriate value from + * the spec based on the 'refresh_mode' and the device density that is use + * d. Unit: Clocks. +*/ #undef DDRC_RFSHTMG_T_RFC_MIN_DEFVAL #undef DDRC_RFSHTMG_T_RFC_MIN_SHIFT #undef DDRC_RFSHTMG_T_RFC_MIN_MASK -#define DDRC_RFSHTMG_T_RFC_MIN_DEFVAL 0x0062008C -#define DDRC_RFSHTMG_T_RFC_MIN_SHIFT 0 -#define DDRC_RFSHTMG_T_RFC_MIN_MASK 0x000003FFU +#define DDRC_RFSHTMG_T_RFC_MIN_DEFVAL 0x0062008C +#define DDRC_RFSHTMG_T_RFC_MIN_SHIFT 0 +#define DDRC_RFSHTMG_T_RFC_MIN_MASK 0x000003FFU -/*Disable ECC scrubs. Valid only when ECCCFG0.ecc_mode = 3'b100 and MEMC_USE_RMW is defined*/ +/* +* Disable ECC scrubs. Valid only when ECCCFG0.ecc_mode = 3'b100 and MEMC_U + * SE_RMW is defined +*/ #undef DDRC_ECCCFG0_DIS_SCRUB_DEFVAL #undef DDRC_ECCCFG0_DIS_SCRUB_SHIFT #undef DDRC_ECCCFG0_DIS_SCRUB_MASK -#define DDRC_ECCCFG0_DIS_SCRUB_DEFVAL 0x00000000 -#define DDRC_ECCCFG0_DIS_SCRUB_SHIFT 4 -#define DDRC_ECCCFG0_DIS_SCRUB_MASK 0x00000010U +#define DDRC_ECCCFG0_DIS_SCRUB_DEFVAL 0x00000000 +#define DDRC_ECCCFG0_DIS_SCRUB_SHIFT 4 +#define DDRC_ECCCFG0_DIS_SCRUB_MASK 0x00000010U -/*ECC mode indicator - 000 - ECC disabled - 100 - ECC enabled - SEC/DED over 1 beat - all other settings are reserved for futur - use*/ +/* +* ECC mode indicator - 000 - ECC disabled - 100 - ECC enabled - SEC/DED ov + * er 1 beat - all other settings are reserved for future use +*/ #undef DDRC_ECCCFG0_ECC_MODE_DEFVAL #undef DDRC_ECCCFG0_ECC_MODE_SHIFT #undef DDRC_ECCCFG0_ECC_MODE_MASK -#define DDRC_ECCCFG0_ECC_MODE_DEFVAL 0x00000000 -#define DDRC_ECCCFG0_ECC_MODE_SHIFT 0 -#define DDRC_ECCCFG0_ECC_MODE_MASK 0x00000007U +#define DDRC_ECCCFG0_ECC_MODE_DEFVAL 0x00000000 +#define DDRC_ECCCFG0_ECC_MODE_SHIFT 0 +#define DDRC_ECCCFG0_ECC_MODE_MASK 0x00000007U -/*Selects whether to poison 1 or 2 bits - if 0 -> 2-bit (uncorrectable) data poisoning, if 1 -> 1-bit (correctable) data poison - ng, if ECCCFG1.data_poison_en=1*/ +/* +* Selects whether to poison 1 or 2 bits - if 0 -> 2-bit (uncorrectable) da + * ta poisoning, if 1 -> 1-bit (correctable) data poisoning, if ECCCFG1.dat + * a_poison_en=1 +*/ #undef DDRC_ECCCFG1_DATA_POISON_BIT_DEFVAL #undef DDRC_ECCCFG1_DATA_POISON_BIT_SHIFT #undef DDRC_ECCCFG1_DATA_POISON_BIT_MASK -#define DDRC_ECCCFG1_DATA_POISON_BIT_DEFVAL 0x00000000 -#define DDRC_ECCCFG1_DATA_POISON_BIT_SHIFT 1 -#define DDRC_ECCCFG1_DATA_POISON_BIT_MASK 0x00000002U +#define DDRC_ECCCFG1_DATA_POISON_BIT_DEFVAL 0x00000000 +#define DDRC_ECCCFG1_DATA_POISON_BIT_SHIFT 1 +#define DDRC_ECCCFG1_DATA_POISON_BIT_MASK 0x00000002U -/*Enable ECC data poisoning - introduces ECC errors on writes to address specified by the ECCPOISONADDR0/1 registers*/ +/* +* Enable ECC data poisoning - introduces ECC errors on writes to address s + * pecified by the ECCPOISONADDR0/1 registers +*/ #undef DDRC_ECCCFG1_DATA_POISON_EN_DEFVAL #undef DDRC_ECCCFG1_DATA_POISON_EN_SHIFT #undef DDRC_ECCCFG1_DATA_POISON_EN_MASK -#define DDRC_ECCCFG1_DATA_POISON_EN_DEFVAL 0x00000000 -#define DDRC_ECCCFG1_DATA_POISON_EN_SHIFT 0 -#define DDRC_ECCCFG1_DATA_POISON_EN_MASK 0x00000001U +#define DDRC_ECCCFG1_DATA_POISON_EN_DEFVAL 0x00000000 +#define DDRC_ECCCFG1_DATA_POISON_EN_SHIFT 0 +#define DDRC_ECCCFG1_DATA_POISON_EN_MASK 0x00000001U -/*The maximum number of DFI PHY clock cycles allowed from the assertion of the dfi_rddata_en signal to the assertion of each of - the corresponding bits of the dfi_rddata_valid signal. This corresponds to the DFI timing parameter tphy_rdlat. Refer to PHY - pecification for correct value. This value it only used for detecting read data timeout when DDR4 retry is enabled by CRCPARC - L1.crc_parity_retry_enable=1. Maximum supported value: - 1:1 Frequency mode : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_ - dlat < 'd114 - 1:2 Frequency mode ANDAND DFITMG0.dfi_rddata_use_sdr == 1 : CRCPARCTL1.dfi_t_phy_rdlat < 64 - 1:2 Frequency mo - e ANDAND DFITMG0.dfi_rddata_use_sdr == 0 : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_rdlat < 'd114 Unit: DFI Clocks*/ +/* +* The maximum number of DFI PHY clock cycles allowed from the assertion of + * the dfi_rddata_en signal to the assertion of each of the corresponding + * bits of the dfi_rddata_valid signal. This corresponds to the DFI timing + * parameter tphy_rdlat. Refer to PHY specification for correct value. This + * value it only used for detecting read data timeout when DDR4 retry is e + * nabled by CRCPARCTL1.crc_parity_retry_enable=1. Maximum supported value: + * - 1:1 Frequency mode : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_r + * dlat < 'd114 - 1:2 Frequency mode ANDAND DFITMG0.dfi_rddata_use_sdr == 1 + * : CRCPARCTL1.dfi_t_phy_rdlat < 64 - 1:2 Frequency mode ANDAND DFITMG0.d + * fi_rddata_use_sdr == 0 : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_ + * rdlat < 'd114 Unit: DFI Clocks +*/ #undef DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_DEFVAL #undef DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_SHIFT #undef DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_MASK -#define DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_DEFVAL 0x10000200 -#define DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_SHIFT 24 -#define DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_MASK 0x3F000000U +#define DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_DEFVAL 0x10000200 +#define DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_SHIFT 24 +#define DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_MASK 0x3F000000U -/*After a Parity or CRC error is flagged on dfi_alert_n signal, the software has an option to read the mode registers in the DR - M before the hardware begins the retry process - 1: Wait for software to read/write the mode registers before hardware begins - the retry. After software is done with its operations, it will clear the alert interrupt register bit - 0: Hardware can begin - the retry right away after the dfi_alert_n pulse goes away. The value on this register is valid only when retry is enabled (P - RCTRL.crc_parity_retry_enable = 1) If this register is set to 1 and if the software doesn't clear the interrupt register afte - handling the parity/CRC error, then the hardware will not begin the retry process and the system will hang. In the case of P - rity/CRC error, there are two possibilities when the software doesn't reset MR5[4] to 0. - (i) If 'Persistent parity' mode re - ister bit is NOT set: the commands sent during retry and normal operation are executed without parity checking. The value in - he Parity error log register MPR Page 1 is valid. - (ii) If 'Persistent parity' mode register bit is SET: Parity checking is - one for commands sent during retry and normal operation. If multiple errors occur before MR5[4] is cleared, the error log in - PR Page 1 should be treated as 'Don't care'.*/ +/* +* After a Parity or CRC error is flagged on dfi_alert_n signal, the softwa + * re has an option to read the mode registers in the DRAM before the hardw + * are begins the retry process - 1: Wait for software to read/write the mo + * de registers before hardware begins the retry. After software is done wi + * th its operations, it will clear the alert interrupt register bit - 0: H + * ardware can begin the retry right away after the dfi_alert_n pulse goes + * away. The value on this register is valid only when retry is enabled (PA + * RCTRL.crc_parity_retry_enable = 1) If this register is set to 1 and if t + * he software doesn't clear the interrupt register after handling the pari + * ty/CRC error, then the hardware will not begin the retry process and the + * system will hang. In the case of Parity/CRC error, there are two possib + * ilities when the software doesn't reset MR5[4] to 0. - (i) If 'Persisten + * t parity' mode register bit is NOT set: the commands sent during retry a + * nd normal operation are executed without parity checking. The value in t + * he Parity error log register MPR Page 1 is valid. - (ii) If 'Persistent + * parity' mode register bit is SET: Parity checking is done for commands s + * ent during retry and normal operation. If multiple errors occur before M + * R5[4] is cleared, the error log in MPR Page 1 should be treated as 'Don' + * t care'. +*/ #undef DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_DEFVAL #undef DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_SHIFT #undef DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_MASK -#define DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_DEFVAL 0x10000200 -#define DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_SHIFT 9 -#define DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_MASK 0x00000200U +#define DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_DEFVAL 0x10000200 +#define DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_SHIFT 9 +#define DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_MASK 0x00000200U -/*- 1: Enable command retry mechanism in case of C/A Parity or CRC error - 0: Disable command retry mechanism when C/A Parity o - CRC features are enabled. Note that retry functionality is not supported if burst chop is enabled (MSTR.burstchop = 1) and/o - disable auto-refresh is enabled (RFSHCTL3.dis_auto_refresh = 1)*/ +/* +* - 1: Enable command retry mechanism in case of C/A Parity or CRC error - + * 0: Disable command retry mechanism when C/A Parity or CRC features are + * enabled. Note that retry functionality is not supported if burst chop is + * enabled (MSTR.burstchop = 1) and/or disable auto-refresh is enabled (RF + * SHCTL3.dis_auto_refresh = 1) +*/ #undef DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_DEFVAL #undef DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_SHIFT #undef DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_MASK -#define DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_DEFVAL 0x10000200 -#define DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_SHIFT 8 -#define DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_MASK 0x00000100U +#define DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_DEFVAL 0x10000200 +#define DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_SHIFT 8 +#define DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_MASK 0x00000100U -/*CRC Calculation setting register - 1: CRC includes DM signal - 0: CRC not includes DM signal Present only in designs configur - d to support DDR4.*/ +/* +* CRC Calculation setting register - 1: CRC includes DM signal - 0: CRC no + * t includes DM signal Present only in designs configured to support DDR4. +*/ #undef DDRC_CRCPARCTL1_CRC_INC_DM_DEFVAL #undef DDRC_CRCPARCTL1_CRC_INC_DM_SHIFT #undef DDRC_CRCPARCTL1_CRC_INC_DM_MASK -#define DDRC_CRCPARCTL1_CRC_INC_DM_DEFVAL 0x10000200 -#define DDRC_CRCPARCTL1_CRC_INC_DM_SHIFT 7 -#define DDRC_CRCPARCTL1_CRC_INC_DM_MASK 0x00000080U +#define DDRC_CRCPARCTL1_CRC_INC_DM_DEFVAL 0x10000200 +#define DDRC_CRCPARCTL1_CRC_INC_DM_SHIFT 7 +#define DDRC_CRCPARCTL1_CRC_INC_DM_MASK 0x00000080U -/*CRC enable Register - 1: Enable generation of CRC - 0: Disable generation of CRC The setting of this register should match th - CRC mode register setting in the DRAM.*/ +/* +* CRC enable Register - 1: Enable generation of CRC - 0: Disable generatio + * n of CRC The setting of this register should match the CRC mode register + * setting in the DRAM. +*/ #undef DDRC_CRCPARCTL1_CRC_ENABLE_DEFVAL #undef DDRC_CRCPARCTL1_CRC_ENABLE_SHIFT #undef DDRC_CRCPARCTL1_CRC_ENABLE_MASK -#define DDRC_CRCPARCTL1_CRC_ENABLE_DEFVAL 0x10000200 -#define DDRC_CRCPARCTL1_CRC_ENABLE_SHIFT 4 -#define DDRC_CRCPARCTL1_CRC_ENABLE_MASK 0x00000010U +#define DDRC_CRCPARCTL1_CRC_ENABLE_DEFVAL 0x10000200 +#define DDRC_CRCPARCTL1_CRC_ENABLE_SHIFT 4 +#define DDRC_CRCPARCTL1_CRC_ENABLE_MASK 0x00000010U -/*C/A Parity enable register - 1: Enable generation of C/A parity and detection of C/A parity error - 0: Disable generation of - /A parity and disable detection of C/A parity error If RCD's parity error detection or SDRAM's parity detection is enabled, t - is register should be 1.*/ +/* +* C/A Parity enable register - 1: Enable generation of C/A parity and dete + * ction of C/A parity error - 0: Disable generation of C/A parity and disa + * ble detection of C/A parity error If RCD's parity error detection or SDR + * AM's parity detection is enabled, this register should be 1. +*/ #undef DDRC_CRCPARCTL1_PARITY_ENABLE_DEFVAL #undef DDRC_CRCPARCTL1_PARITY_ENABLE_SHIFT #undef DDRC_CRCPARCTL1_PARITY_ENABLE_MASK -#define DDRC_CRCPARCTL1_PARITY_ENABLE_DEFVAL 0x10000200 -#define DDRC_CRCPARCTL1_PARITY_ENABLE_SHIFT 0 -#define DDRC_CRCPARCTL1_PARITY_ENABLE_MASK 0x00000001U +#define DDRC_CRCPARCTL1_PARITY_ENABLE_DEFVAL 0x10000200 +#define DDRC_CRCPARCTL1_PARITY_ENABLE_SHIFT 0 +#define DDRC_CRCPARCTL1_PARITY_ENABLE_MASK 0x00000001U -/*Value from the DRAM spec indicating the maximum width of the dfi_alert_n pulse when a parity error occurs. Recommended values - - tPAR_ALERT_PW.MAX For configurations with MEMC_FREQ_RATIO=2, program this to tPAR_ALERT_PW.MAX/2 and round up to next inte - er value. Values of 0, 1 and 2 are illegal. This value must be greater than CRCPARCTL2.t_crc_alert_pw_max.*/ +/* +* Value from the DRAM spec indicating the maximum width of the dfi_alert_n + * pulse when a parity error occurs. Recommended values: - tPAR_ALERT_PW.M + * AX For configurations with MEMC_FREQ_RATIO=2, program this to tPAR_ALERT + * _PW.MAX/2 and round up to next integer value. Values of 0, 1 and 2 are i + * llegal. This value must be greater than CRCPARCTL2.t_crc_alert_pw_max. +*/ #undef DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_DEFVAL #undef DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_SHIFT #undef DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_MASK -#define DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_DEFVAL 0x0030050C -#define DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_SHIFT 16 -#define DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_MASK 0x01FF0000U +#define DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_DEFVAL 0x0030050C +#define DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_SHIFT 16 +#define DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_MASK 0x01FF0000U -/*Value from the DRAM spec indicating the maximum width of the dfi_alert_n pulse when a CRC error occurs. Recommended values: - - tCRC_ALERT_PW.MAX For configurations with MEMC_FREQ_RATIO=2, program this to tCRC_ALERT_PW.MAX/2 and round up to next integer - value. Values of 0, 1 and 2 are illegal. This value must be less than CRCPARCTL2.t_par_alert_pw_max.*/ +/* +* Value from the DRAM spec indicating the maximum width of the dfi_alert_n + * pulse when a CRC error occurs. Recommended values: - tCRC_ALERT_PW.MAX + * For configurations with MEMC_FREQ_RATIO=2, program this to tCRC_ALERT_PW + * .MAX/2 and round up to next integer value. Values of 0, 1 and 2 are ille + * gal. This value must be less than CRCPARCTL2.t_par_alert_pw_max. +*/ #undef DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_DEFVAL #undef DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_SHIFT #undef DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_MASK -#define DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_DEFVAL 0x0030050C -#define DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_SHIFT 8 -#define DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_MASK 0x00001F00U +#define DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_DEFVAL 0x0030050C +#define DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_SHIFT 8 +#define DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_MASK 0x00001F00U -/*Indicates the maximum duration in number of DRAM clock cycles for which a command should be held in the Command Retry FIFO be - ore it is popped out. Every location in the Command Retry FIFO has an associated down counting timer that will use this regis - er as the start value. The down counting starts when a command is loaded into the FIFO. The timer counts down every 4 DRAM cy - les. When the counter reaches zero, the entry is popped from the FIFO. All the counters are frozen, if a C/A Parity or CRC er - or occurs before the counter reaches zero. The counter is reset to 0, after all the commands in the FIFO are retried. Recomme - ded(minimum) values: - Only C/A Parity is enabled. RoundUp((PHY Command Latency(DRAM CLK) + CAL + RDIMM delay + tPAR_ALERT_ON - max + tPAR_UNKNOWN + PHY Alert Latency(DRAM CLK) + board delay) / 4) + 2 - Both C/A Parity and CRC is enabled/ Only CRC is en - bled. RoundUp((PHY Command Latency(DRAM CLK) + CAL + RDIMM delay + WL + 5(BL10)+ tCRC_ALERT.max + PHY Alert Latency(DRAM CLK) - + board delay) / 4) + 2 Note 1: All value (e.g. tPAR_ALERT_ON) should be in terms of DRAM Clock and round up Note 2: Board de - ay(Command/Alert_n) should be considered. Note 3: Use the worst case(longer) value for PHY Latencies/Board delay Note 4: The - ecommended values are minimum value to be set. For mode detail, See 'Calculation of FIFO Depth' section. Max value can be set - to this register is defined below: - MEMC_BURST_LENGTH == 16 Full bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH- - Full bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Half bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_D - PTH-4 Half bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-6 Quarter bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CM - _FIFO_DEPTH-8 Quarter bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-12 - MEMC_BURST_LENGTH != 16 Full bus Mode (C - C=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-1 Full bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mo - e (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Quarte - bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-4 Quarter bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEP - H-6 Values of 0, 1 and 2 are illegal.*/ +/* +* Indicates the maximum duration in number of DRAM clock cycles for which + * a command should be held in the Command Retry FIFO before it is popped o + * ut. Every location in the Command Retry FIFO has an associated down coun + * ting timer that will use this register as the start value. The down coun + * ting starts when a command is loaded into the FIFO. The timer counts dow + * n every 4 DRAM cycles. When the counter reaches zero, the entry is poppe + * d from the FIFO. All the counters are frozen, if a C/A Parity or CRC err + * or occurs before the counter reaches zero. The counter is reset to 0, af + * ter all the commands in the FIFO are retried. Recommended(minimum) value + * s: - Only C/A Parity is enabled. RoundUp((PHY Command Latency(DRAM CLK) + * + CAL + RDIMM delay + tPAR_ALERT_ON.max + tPAR_UNKNOWN + PHY Alert Laten + * cy(DRAM CLK) + board delay) / 4) + 2 - Both C/A Parity and CRC is enable + * d/ Only CRC is enabled. RoundUp((PHY Command Latency(DRAM CLK) + CAL + R + * DIMM delay + WL + 5(BL10)+ tCRC_ALERT.max + PHY Alert Latency(DRAM CLK) + * + board delay) / 4) + 2 Note 1: All value (e.g. tPAR_ALERT_ON) should be + * in terms of DRAM Clock and round up Note 2: Board delay(Command/Alert_n + * ) should be considered. Note 3: Use the worst case(longer) value for PHY + * Latencies/Board delay Note 4: The Recommended values are minimum value + * to be set. For mode detail, See 'Calculation of FIFO Depth' section. Max + * value can be set to this register is defined below: - MEMC_BURST_LENGTH + * == 16 Full bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 + * Full bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Half b + * us Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-4 Half bus Mod + * e (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-6 Quarter bus Mode (C + * RC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-8 Quarter bus Mode (CRC= + * ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-12 - MEMC_BURST_LENGTH != 16 + * Full bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-1 Full + * bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mod + * e (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mode (CRC + * =ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Quarter bus Mode (CRC=OFF + * ) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-4 Quarter bus Mode (CRC=ON) Ma + * x value = UMCTL2_RETRY_CMD_FIFO_DEPTH-6 Values of 0, 1 and 2 are illegal + * . +*/ #undef DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_DEFVAL #undef DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_SHIFT #undef DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_MASK -#define DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_DEFVAL 0x0030050C -#define DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_SHIFT 0 -#define DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_MASK 0x0000003FU +#define DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_DEFVAL 0x0030050C +#define DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_SHIFT 0 +#define DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_MASK 0x0000003FU -/*If lower bit is enabled the SDRAM initialization routine is skipped. The upper bit decides what state the controller starts u - in when reset is removed - 00 - SDRAM Intialization routine is run after power-up - 01 - SDRAM Intialization routine is skip - ed after power-up. Controller starts up in Normal Mode - 11 - SDRAM Intialization routine is skipped after power-up. Controll - r starts up in Self-refresh Mode - 10 - SDRAM Intialization routine is run after power-up. Note: The only 2'b00 is supported - or LPDDR4 in this version of the uMCTL2.*/ +/* +* If lower bit is enabled the SDRAM initialization routine is skipped. The + * upper bit decides what state the controller starts up in when reset is + * removed - 00 - SDRAM Intialization routine is run after power-up - 01 - + * SDRAM Intialization routine is skipped after power-up. Controller starts + * up in Normal Mode - 11 - SDRAM Intialization routine is skipped after p + * ower-up. Controller starts up in Self-refresh Mode - 10 - SDRAM Intializ + * ation routine is run after power-up. Note: The only 2'b00 is supported f + * or LPDDR4 in this version of the uMCTL2. +*/ #undef DDRC_INIT0_SKIP_DRAM_INIT_DEFVAL #undef DDRC_INIT0_SKIP_DRAM_INIT_SHIFT #undef DDRC_INIT0_SKIP_DRAM_INIT_MASK -#define DDRC_INIT0_SKIP_DRAM_INIT_DEFVAL 0x0002004E -#define DDRC_INIT0_SKIP_DRAM_INIT_SHIFT 30 -#define DDRC_INIT0_SKIP_DRAM_INIT_MASK 0xC0000000U +#define DDRC_INIT0_SKIP_DRAM_INIT_DEFVAL 0x0002004E +#define DDRC_INIT0_SKIP_DRAM_INIT_SHIFT 30 +#define DDRC_INIT0_SKIP_DRAM_INIT_MASK 0xC0000000U -/*Cycles to wait after driving CKE high to start the SDRAM initialization sequence. Unit: 1024 clocks. DDR2 typically requires - 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2/LPDDR3 typically requires this to be pr - grammed for a delay of 200 us. LPDDR4 typically requires this to be programmed for a delay of 2 us. For configurations with M - MC_FREQ_RATIO=2, program this to JEDEC spec value divided by 2, and round it up to next integer value.*/ +/* +* Cycles to wait after driving CKE high to start the SDRAM initialization + * sequence. Unit: 1024 clocks. DDR2 typically requires a 400 ns delay, req + * uiring this value to be programmed to 2 at all clock speeds. LPDDR2/LPDD + * R3 typically requires this to be programmed for a delay of 200 us. LPDDR + * 4 typically requires this to be programmed for a delay of 2 us. For conf + * igurations with MEMC_FREQ_RATIO=2, program this to JEDEC spec value divi + * ded by 2, and round it up to next integer value. +*/ #undef DDRC_INIT0_POST_CKE_X1024_DEFVAL #undef DDRC_INIT0_POST_CKE_X1024_SHIFT #undef DDRC_INIT0_POST_CKE_X1024_MASK -#define DDRC_INIT0_POST_CKE_X1024_DEFVAL 0x0002004E -#define DDRC_INIT0_POST_CKE_X1024_SHIFT 16 -#define DDRC_INIT0_POST_CKE_X1024_MASK 0x03FF0000U +#define DDRC_INIT0_POST_CKE_X1024_DEFVAL 0x0002004E +#define DDRC_INIT0_POST_CKE_X1024_SHIFT 16 +#define DDRC_INIT0_POST_CKE_X1024_MASK 0x03FF0000U -/*Cycles to wait after reset before driving CKE high to start the SDRAM initialization sequence. Unit: 1024 clock cycles. DDR2 - pecifications typically require this to be programmed for a delay of >= 200 us. LPDDR2/LPDDR3: tINIT1 of 100 ns (min) LPDDR4: - tINIT3 of 2 ms (min) For configurations with MEMC_FREQ_RATIO=2, program this to JEDEC spec value divided by 2, and round it u - to next integer value.*/ +/* +* Cycles to wait after reset before driving CKE high to start the SDRAM in + * itialization sequence. Unit: 1024 clock cycles. DDR2 specifications typi + * cally require this to be programmed for a delay of >= 200 us. LPDDR2/LPD + * DR3: tINIT1 of 100 ns (min) LPDDR4: tINIT3 of 2 ms (min) For configurati + * ons with MEMC_FREQ_RATIO=2, program this to JEDEC spec value divided by + * 2, and round it up to next integer value. +*/ #undef DDRC_INIT0_PRE_CKE_X1024_DEFVAL #undef DDRC_INIT0_PRE_CKE_X1024_SHIFT #undef DDRC_INIT0_PRE_CKE_X1024_MASK -#define DDRC_INIT0_PRE_CKE_X1024_DEFVAL 0x0002004E -#define DDRC_INIT0_PRE_CKE_X1024_SHIFT 0 -#define DDRC_INIT0_PRE_CKE_X1024_MASK 0x00000FFFU +#define DDRC_INIT0_PRE_CKE_X1024_DEFVAL 0x0002004E +#define DDRC_INIT0_PRE_CKE_X1024_SHIFT 0 +#define DDRC_INIT0_PRE_CKE_X1024_MASK 0x00000FFFU -/*Number of cycles to assert SDRAM reset signal during init sequence. This is only present for designs supporting DDR3, DDR4 or - LPDDR4 devices. For use with a DDR PHY, this should be set to a minimum of 1*/ +/* +* Number of cycles to assert SDRAM reset signal during init sequence. This + * is only present for designs supporting DDR3, DDR4 or LPDDR4 devices. Fo + * r use with a DDR PHY, this should be set to a minimum of 1 +*/ #undef DDRC_INIT1_DRAM_RSTN_X1024_DEFVAL #undef DDRC_INIT1_DRAM_RSTN_X1024_SHIFT #undef DDRC_INIT1_DRAM_RSTN_X1024_MASK -#define DDRC_INIT1_DRAM_RSTN_X1024_DEFVAL 0x00000000 -#define DDRC_INIT1_DRAM_RSTN_X1024_SHIFT 16 -#define DDRC_INIT1_DRAM_RSTN_X1024_MASK 0x01FF0000U +#define DDRC_INIT1_DRAM_RSTN_X1024_DEFVAL 0x00000000 +#define DDRC_INIT1_DRAM_RSTN_X1024_SHIFT 16 +#define DDRC_INIT1_DRAM_RSTN_X1024_MASK 0x01FF0000U -/*Cycles to wait after completing the SDRAM initialization sequence before starting the dynamic scheduler. Unit: Counts of a gl - bal timer that pulses every 32 clock cycles. There is no known specific requirement for this; it may be set to zero.*/ +/* +* Cycles to wait after completing the SDRAM initialization sequence before + * starting the dynamic scheduler. Unit: Counts of a global timer that pul + * ses every 32 clock cycles. There is no known specific requirement for th + * is; it may be set to zero. +*/ #undef DDRC_INIT1_FINAL_WAIT_X32_DEFVAL #undef DDRC_INIT1_FINAL_WAIT_X32_SHIFT #undef DDRC_INIT1_FINAL_WAIT_X32_MASK -#define DDRC_INIT1_FINAL_WAIT_X32_DEFVAL 0x00000000 -#define DDRC_INIT1_FINAL_WAIT_X32_SHIFT 8 -#define DDRC_INIT1_FINAL_WAIT_X32_MASK 0x00007F00U +#define DDRC_INIT1_FINAL_WAIT_X32_DEFVAL 0x00000000 +#define DDRC_INIT1_FINAL_WAIT_X32_SHIFT 8 +#define DDRC_INIT1_FINAL_WAIT_X32_MASK 0x00007F00U -/*Wait period before driving the OCD complete command to SDRAM. Unit: Counts of a global timer that pulses every 32 clock cycle - . There is no known specific requirement for this; it may be set to zero.*/ +/* +* Wait period before driving the OCD complete command to SDRAM. Unit: Coun + * ts of a global timer that pulses every 32 clock cycles. There is no know + * n specific requirement for this; it may be set to zero. +*/ #undef DDRC_INIT1_PRE_OCD_X32_DEFVAL #undef DDRC_INIT1_PRE_OCD_X32_SHIFT #undef DDRC_INIT1_PRE_OCD_X32_MASK -#define DDRC_INIT1_PRE_OCD_X32_DEFVAL 0x00000000 -#define DDRC_INIT1_PRE_OCD_X32_SHIFT 0 -#define DDRC_INIT1_PRE_OCD_X32_MASK 0x0000000FU +#define DDRC_INIT1_PRE_OCD_X32_DEFVAL 0x00000000 +#define DDRC_INIT1_PRE_OCD_X32_SHIFT 0 +#define DDRC_INIT1_PRE_OCD_X32_MASK 0x0000000FU -/*Idle time after the reset command, tINIT4. Present only in designs configured to support LPDDR2. Unit: 32 clock cycles.*/ +/* +* Idle time after the reset command, tINIT4. Present only in designs confi + * gured to support LPDDR2. Unit: 32 clock cycles. +*/ #undef DDRC_INIT2_IDLE_AFTER_RESET_X32_DEFVAL #undef DDRC_INIT2_IDLE_AFTER_RESET_X32_SHIFT #undef DDRC_INIT2_IDLE_AFTER_RESET_X32_MASK -#define DDRC_INIT2_IDLE_AFTER_RESET_X32_DEFVAL 0x00000D05 -#define DDRC_INIT2_IDLE_AFTER_RESET_X32_SHIFT 8 -#define DDRC_INIT2_IDLE_AFTER_RESET_X32_MASK 0x0000FF00U +#define DDRC_INIT2_IDLE_AFTER_RESET_X32_DEFVAL 0x00000D05 +#define DDRC_INIT2_IDLE_AFTER_RESET_X32_SHIFT 8 +#define DDRC_INIT2_IDLE_AFTER_RESET_X32_MASK 0x0000FF00U -/*Time to wait after the first CKE high, tINIT2. Present only in designs configured to support LPDDR2/LPDDR3. Unit: 1 clock cyc - e. LPDDR2/LPDDR3 typically requires 5 x tCK delay.*/ +/* +* Time to wait after the first CKE high, tINIT2. Present only in designs c + * onfigured to support LPDDR2/LPDDR3. Unit: 1 clock cycle. LPDDR2/LPDDR3 t + * ypically requires 5 x tCK delay. +*/ #undef DDRC_INIT2_MIN_STABLE_CLOCK_X1_DEFVAL #undef DDRC_INIT2_MIN_STABLE_CLOCK_X1_SHIFT #undef DDRC_INIT2_MIN_STABLE_CLOCK_X1_MASK -#define DDRC_INIT2_MIN_STABLE_CLOCK_X1_DEFVAL 0x00000D05 -#define DDRC_INIT2_MIN_STABLE_CLOCK_X1_SHIFT 0 -#define DDRC_INIT2_MIN_STABLE_CLOCK_X1_MASK 0x0000000FU +#define DDRC_INIT2_MIN_STABLE_CLOCK_X1_DEFVAL 0x00000D05 +#define DDRC_INIT2_MIN_STABLE_CLOCK_X1_SHIFT 0 +#define DDRC_INIT2_MIN_STABLE_CLOCK_X1_MASK 0x0000000FU -/*DDR2: Value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The uMCTL2 sets this bit appropriately - DDR3/DDR4: Value loaded into MR0 register. mDDR: Value to write to MR register. LPDDR2/LPDDR3/LPDDR4 - Value to write to MR1 - register*/ +/* +* DDR2: Value to write to MR register. Bit 8 is for DLL and the setting he + * re is ignored. The uMCTL2 sets this bit appropriately. DDR3/DDR4: Value + * loaded into MR0 register. mDDR: Value to write to MR register. LPDDR2/LP + * DDR3/LPDDR4 - Value to write to MR1 register +*/ #undef DDRC_INIT3_MR_DEFVAL #undef DDRC_INIT3_MR_SHIFT #undef DDRC_INIT3_MR_MASK -#define DDRC_INIT3_MR_DEFVAL 0x00000510 -#define DDRC_INIT3_MR_SHIFT 16 -#define DDRC_INIT3_MR_MASK 0xFFFF0000U +#define DDRC_INIT3_MR_DEFVAL 0x00000510 +#define DDRC_INIT3_MR_SHIFT 16 +#define DDRC_INIT3_MR_MASK 0xFFFF0000U -/*DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setting in this register is ignored. The uMCTL2 sets those - bits appropriately. DDR3/DDR4: Value to write to MR1 register Set bit 7 to 0. If PHY-evaluation mode training is enabled, thi - bit is set appropriately by the uMCTL2 during write leveling. mDDR: Value to write to EMR register. LPDDR2/LPDDR3/LPDDR4 - V - lue to write to MR2 register*/ +/* +* DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setti + * ng in this register is ignored. The uMCTL2 sets those bits appropriately + * . DDR3/DDR4: Value to write to MR1 register Set bit 7 to 0. If PHY-evalu + * ation mode training is enabled, this bit is set appropriately by the uMC + * TL2 during write leveling. mDDR: Value to write to EMR register. LPDDR2/ + * LPDDR3/LPDDR4 - Value to write to MR2 register +*/ #undef DDRC_INIT3_EMR_DEFVAL #undef DDRC_INIT3_EMR_SHIFT #undef DDRC_INIT3_EMR_MASK -#define DDRC_INIT3_EMR_DEFVAL 0x00000510 -#define DDRC_INIT3_EMR_SHIFT 0 -#define DDRC_INIT3_EMR_MASK 0x0000FFFFU +#define DDRC_INIT3_EMR_DEFVAL 0x00000510 +#define DDRC_INIT3_EMR_SHIFT 0 +#define DDRC_INIT3_EMR_MASK 0x0000FFFFU -/*DDR2: Value to write to EMR2 register. DDR3/DDR4: Value to write to MR2 register LPDDR2/LPDDR3/LPDDR4: Value to write to MR3 - egister mDDR: Unused*/ +/* +* DDR2: Value to write to EMR2 register. DDR3/DDR4: Value to write to MR2 + * register LPDDR2/LPDDR3/LPDDR4: Value to write to MR3 register mDDR: Unus + * ed +*/ #undef DDRC_INIT4_EMR2_DEFVAL #undef DDRC_INIT4_EMR2_SHIFT #undef DDRC_INIT4_EMR2_MASK -#define DDRC_INIT4_EMR2_DEFVAL 0x00000000 -#define DDRC_INIT4_EMR2_SHIFT 16 -#define DDRC_INIT4_EMR2_MASK 0xFFFF0000U +#define DDRC_INIT4_EMR2_DEFVAL 0x00000000 +#define DDRC_INIT4_EMR2_SHIFT 16 +#define DDRC_INIT4_EMR2_MASK 0xFFFF0000U -/*DDR2: Value to write to EMR3 register. DDR3/DDR4: Value to write to MR3 register mDDR/LPDDR2/LPDDR3: Unused LPDDR4: Value to - rite to MR13 register*/ +/* +* DDR2: Value to write to EMR3 register. DDR3/DDR4: Value to write to MR3 + * register mDDR/LPDDR2/LPDDR3: Unused LPDDR4: Value to write to MR13 regis + * ter +*/ #undef DDRC_INIT4_EMR3_DEFVAL #undef DDRC_INIT4_EMR3_SHIFT #undef DDRC_INIT4_EMR3_MASK -#define DDRC_INIT4_EMR3_DEFVAL 0x00000000 -#define DDRC_INIT4_EMR3_SHIFT 0 -#define DDRC_INIT4_EMR3_MASK 0x0000FFFFU +#define DDRC_INIT4_EMR3_DEFVAL 0x00000000 +#define DDRC_INIT4_EMR3_SHIFT 0 +#define DDRC_INIT4_EMR3_MASK 0x0000FFFFU -/*ZQ initial calibration, tZQINIT. Present only in designs configured to support DDR3 or DDR4 or LPDDR2/LPDDR3. Unit: 32 clock - ycles. DDR3 typically requires 512 clocks. DDR4 requires 1024 clocks. LPDDR2/LPDDR3 requires 1 us.*/ +/* +* ZQ initial calibration, tZQINIT. Present only in designs configured to s + * upport DDR3 or DDR4 or LPDDR2/LPDDR3. Unit: 32 clock cycles. DDR3 typica + * lly requires 512 clocks. DDR4 requires 1024 clocks. LPDDR2/LPDDR3 requir + * es 1 us. +*/ #undef DDRC_INIT5_DEV_ZQINIT_X32_DEFVAL #undef DDRC_INIT5_DEV_ZQINIT_X32_SHIFT #undef DDRC_INIT5_DEV_ZQINIT_X32_MASK -#define DDRC_INIT5_DEV_ZQINIT_X32_DEFVAL 0x00100004 -#define DDRC_INIT5_DEV_ZQINIT_X32_SHIFT 16 -#define DDRC_INIT5_DEV_ZQINIT_X32_MASK 0x00FF0000U +#define DDRC_INIT5_DEV_ZQINIT_X32_DEFVAL 0x00100004 +#define DDRC_INIT5_DEV_ZQINIT_X32_SHIFT 16 +#define DDRC_INIT5_DEV_ZQINIT_X32_MASK 0x00FF0000U -/*Maximum duration of the auto initialization, tINIT5. Present only in designs configured to support LPDDR2/LPDDR3. LPDDR2/LPDD - 3 typically requires 10 us.*/ +/* +* Maximum duration of the auto initialization, tINIT5. Present only in des + * igns configured to support LPDDR2/LPDDR3. LPDDR2/LPDDR3 typically requir + * es 10 us. +*/ #undef DDRC_INIT5_MAX_AUTO_INIT_X1024_DEFVAL #undef DDRC_INIT5_MAX_AUTO_INIT_X1024_SHIFT #undef DDRC_INIT5_MAX_AUTO_INIT_X1024_MASK -#define DDRC_INIT5_MAX_AUTO_INIT_X1024_DEFVAL 0x00100004 -#define DDRC_INIT5_MAX_AUTO_INIT_X1024_SHIFT 0 -#define DDRC_INIT5_MAX_AUTO_INIT_X1024_MASK 0x000003FFU +#define DDRC_INIT5_MAX_AUTO_INIT_X1024_DEFVAL 0x00100004 +#define DDRC_INIT5_MAX_AUTO_INIT_X1024_SHIFT 0 +#define DDRC_INIT5_MAX_AUTO_INIT_X1024_MASK 0x000003FFU -/*DDR4- Value to be loaded into SDRAM MR4 registers. Used in DDR4 designs only.*/ +/* +* DDR4- Value to be loaded into SDRAM MR4 registers. Used in DDR4 designs + * only. +*/ #undef DDRC_INIT6_MR4_DEFVAL #undef DDRC_INIT6_MR4_SHIFT #undef DDRC_INIT6_MR4_MASK -#define DDRC_INIT6_MR4_DEFVAL 0x00000000 -#define DDRC_INIT6_MR4_SHIFT 16 -#define DDRC_INIT6_MR4_MASK 0xFFFF0000U +#define DDRC_INIT6_MR4_DEFVAL 0x00000000 +#define DDRC_INIT6_MR4_SHIFT 16 +#define DDRC_INIT6_MR4_MASK 0xFFFF0000U -/*DDR4- Value to be loaded into SDRAM MR5 registers. Used in DDR4 designs only.*/ +/* +* DDR4- Value to be loaded into SDRAM MR5 registers. Used in DDR4 designs + * only. +*/ #undef DDRC_INIT6_MR5_DEFVAL #undef DDRC_INIT6_MR5_SHIFT #undef DDRC_INIT6_MR5_MASK -#define DDRC_INIT6_MR5_DEFVAL 0x00000000 -#define DDRC_INIT6_MR5_SHIFT 0 -#define DDRC_INIT6_MR5_MASK 0x0000FFFFU +#define DDRC_INIT6_MR5_DEFVAL 0x00000000 +#define DDRC_INIT6_MR5_SHIFT 0 +#define DDRC_INIT6_MR5_MASK 0x0000FFFFU -/*DDR4- Value to be loaded into SDRAM MR6 registers. Used in DDR4 designs only.*/ +/* +* DDR4- Value to be loaded into SDRAM MR6 registers. Used in DDR4 designs + * only. +*/ #undef DDRC_INIT7_MR6_DEFVAL #undef DDRC_INIT7_MR6_SHIFT #undef DDRC_INIT7_MR6_MASK -#define DDRC_INIT7_MR6_DEFVAL -#define DDRC_INIT7_MR6_SHIFT 16 -#define DDRC_INIT7_MR6_MASK 0xFFFF0000U +#define DDRC_INIT7_MR6_DEFVAL +#define DDRC_INIT7_MR6_SHIFT 16 +#define DDRC_INIT7_MR6_MASK 0xFFFF0000U -/*Disabling Address Mirroring for BG bits. When this is set to 1, BG0 and BG1 are NOT swapped even if Address Mirroring is enab - ed. This will be required for DDR4 DIMMs with x16 devices. - 1 - BG0 and BG1 are NOT swapped. - 0 - BG0 and BG1 are swapped i - address mirroring is enabled.*/ +/* +* Disabling Address Mirroring for BG bits. When this is set to 1, BG0 and + * BG1 are NOT swapped even if Address Mirroring is enabled. This will be r + * equired for DDR4 DIMMs with x16 devices. - 1 - BG0 and BG1 are NOT swapp + * ed. - 0 - BG0 and BG1 are swapped if address mirroring is enabled. +*/ #undef DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_DEFVAL #undef DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_SHIFT #undef DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_MASK -#define DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_DEFVAL 0x00000000 -#define DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_SHIFT 5 -#define DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_MASK 0x00000020U +#define DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_DEFVAL 0x00000000 +#define DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_SHIFT 5 +#define DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_MASK 0x00000020U -/*Enable for BG1 bit of MRS command. BG1 bit of the mode register address is specified as RFU (Reserved for Future Use) and mus - be programmed to 0 during MRS. In case where DRAMs which do not have BG1 are attached and both the CA parity and the Output - nversion are enabled, this must be set to 0, so that the calculation of CA parity will not include BG1 bit. Note: This has no - effect on the address of any other memory accesses, or of software-driven mode register accesses. If address mirroring is ena - led, this is applied to BG1 of even ranks and BG0 of odd ranks. - 1 - Enabled - 0 - Disabled*/ +/* +* Enable for BG1 bit of MRS command. BG1 bit of the mode register address + * is specified as RFU (Reserved for Future Use) and must be programmed to + * 0 during MRS. In case where DRAMs which do not have BG1 are attached and + * both the CA parity and the Output Inversion are enabled, this must be s + * et to 0, so that the calculation of CA parity will not include BG1 bit. + * Note: This has no effect on the address of any other memory accesses, or + * of software-driven mode register accesses. If address mirroring is enab + * led, this is applied to BG1 of even ranks and BG0 of odd ranks. - 1 - En + * abled - 0 - Disabled +*/ #undef DDRC_DIMMCTL_MRS_BG1_EN_DEFVAL #undef DDRC_DIMMCTL_MRS_BG1_EN_SHIFT #undef DDRC_DIMMCTL_MRS_BG1_EN_MASK -#define DDRC_DIMMCTL_MRS_BG1_EN_DEFVAL 0x00000000 -#define DDRC_DIMMCTL_MRS_BG1_EN_SHIFT 4 -#define DDRC_DIMMCTL_MRS_BG1_EN_MASK 0x00000010U +#define DDRC_DIMMCTL_MRS_BG1_EN_DEFVAL 0x00000000 +#define DDRC_DIMMCTL_MRS_BG1_EN_SHIFT 4 +#define DDRC_DIMMCTL_MRS_BG1_EN_MASK 0x00000010U -/*Enable for A17 bit of MRS command. A17 bit of the mode register address is specified as RFU (Reserved for Future Use) and mus - be programmed to 0 during MRS. In case where DRAMs which do not have A17 are attached and the Output Inversion are enabled, - his must be set to 0, so that the calculation of CA parity will not include A17 bit. Note: This has no effect on the address - f any other memory accesses, or of software-driven mode register accesses. - 1 - Enabled - 0 - Disabled*/ +/* +* Enable for A17 bit of MRS command. A17 bit of the mode register address + * is specified as RFU (Reserved for Future Use) and must be programmed to + * 0 during MRS. In case where DRAMs which do not have A17 are attached and + * the Output Inversion are enabled, this must be set to 0, so that the ca + * lculation of CA parity will not include A17 bit. Note: This has no effec + * t on the address of any other memory accesses, or of software-driven mod + * e register accesses. - 1 - Enabled - 0 - Disabled +*/ #undef DDRC_DIMMCTL_MRS_A17_EN_DEFVAL #undef DDRC_DIMMCTL_MRS_A17_EN_SHIFT #undef DDRC_DIMMCTL_MRS_A17_EN_MASK -#define DDRC_DIMMCTL_MRS_A17_EN_DEFVAL 0x00000000 -#define DDRC_DIMMCTL_MRS_A17_EN_SHIFT 3 -#define DDRC_DIMMCTL_MRS_A17_EN_MASK 0x00000008U +#define DDRC_DIMMCTL_MRS_A17_EN_DEFVAL 0x00000000 +#define DDRC_DIMMCTL_MRS_A17_EN_SHIFT 3 +#define DDRC_DIMMCTL_MRS_A17_EN_MASK 0x00000008U -/*Output Inversion Enable (for DDR4 RDIMM implementations only). DDR4 RDIMM implements the Output Inversion feature by default, - which means that the following address, bank address and bank group bits of B-side DRAMs are inverted: A3-A9, A11, A13, A17, - A0-BA1, BG0-BG1. Setting this bit ensures that, for mode register accesses generated by the uMCTL2 during the automatic initi - lization routine and enabling of a particular DDR4 feature, separate A-side and B-side mode register accesses are generated. - or B-side mode register accesses, these bits are inverted within the uMCTL2 to compensate for this RDIMM inversion. Note: Thi - has no effect on the address of any other memory accesses, or of software-driven mode register accesses. - 1 - Implement out - ut inversion for B-side DRAMs. - 0 - Do not implement output inversion for B-side DRAMs.*/ +/* +* Output Inversion Enable (for DDR4 RDIMM implementations only). DDR4 RDIM + * M implements the Output Inversion feature by default, which means that t + * he following address, bank address and bank group bits of B-side DRAMs a + * re inverted: A3-A9, A11, A13, A17, BA0-BA1, BG0-BG1. Setting this bit en + * sures that, for mode register accesses generated by the uMCTL2 during th + * e automatic initialization routine and enabling of a particular DDR4 fea + * ture, separate A-side and B-side mode register accesses are generated. F + * or B-side mode register accesses, these bits are inverted within the uMC + * TL2 to compensate for this RDIMM inversion. Note: This has no effect on + * the address of any other memory accesses, or of software-driven mode reg + * ister accesses. - 1 - Implement output inversion for B-side DRAMs. - 0 - + * Do not implement output inversion for B-side DRAMs. +*/ #undef DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_DEFVAL #undef DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_SHIFT #undef DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_MASK -#define DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_DEFVAL 0x00000000 -#define DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_SHIFT 2 -#define DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_MASK 0x00000004U +#define DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_DEFVAL 0x00000000 +#define DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_SHIFT 2 +#define DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_MASK 0x00000004U -/*Address Mirroring Enable (for multi-rank UDIMM implementations and multi-rank DDR4 RDIMM implementations). Some UDIMMs and DD - 4 RDIMMs implement address mirroring for odd ranks, which means that the following address, bank address and bank group bits - re swapped: (A3, A4), (A5, A6), (A7, A8), (BA0, BA1) and also (A11, A13), (BG0, BG1) for the DDR4. Setting this bit ensures t - at, for mode register accesses during the automatic initialization routine, these bits are swapped within the uMCTL2 to compe - sate for this UDIMM/RDIMM swapping. In addition to the automatic initialization routine, in case of DDR4 UDIMM/RDIMM, they ar - swapped during the automatic MRS access to enable/disable of a particular DDR4 feature. Note: This has no effect on the addr - ss of any other memory accesses, or of software-driven mode register accesses. This is not supported for mDDR, LPDDR2, LPDDR3 - or LPDDR4 SDRAMs. Note: In case of x16 DDR4 DIMMs, BG1 output of MRS for the odd ranks is same as BG0 because BG1 is invalid, - hence dimm_dis_bg_mirroring register must be set to 1. - 1 - For odd ranks, implement address mirroring for MRS commands to d - ring initialization and for any automatic DDR4 MRS commands (to be used if UDIMM/RDIMM implements address mirroring) - 0 - Do - not implement address mirroring*/ +/* +* Address Mirroring Enable (for multi-rank UDIMM implementations and multi + * -rank DDR4 RDIMM implementations). Some UDIMMs and DDR4 RDIMMs implement + * address mirroring for odd ranks, which means that the following address + * , bank address and bank group bits are swapped: (A3, A4), (A5, A6), (A7, + * A8), (BA0, BA1) and also (A11, A13), (BG0, BG1) for the DDR4. Setting t + * his bit ensures that, for mode register accesses during the automatic in + * itialization routine, these bits are swapped within the uMCTL2 to compen + * sate for this UDIMM/RDIMM swapping. In addition to the automatic initial + * ization routine, in case of DDR4 UDIMM/RDIMM, they are swapped during th + * e automatic MRS access to enable/disable of a particular DDR4 feature. N + * ote: This has no effect on the address of any other memory accesses, or + * of software-driven mode register accesses. This is not supported for mDD + * R, LPDDR2, LPDDR3 or LPDDR4 SDRAMs. Note: In case of x16 DDR4 DIMMs, BG1 + * output of MRS for the odd ranks is same as BG0 because BG1 is invalid, + * hence dimm_dis_bg_mirroring register must be set to 1. - 1 - For odd ran + * ks, implement address mirroring for MRS commands to during initializatio + * n and for any automatic DDR4 MRS commands (to be used if UDIMM/RDIMM imp + * lements address mirroring) - 0 - Do not implement address mirroring +*/ #undef DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_DEFVAL #undef DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_SHIFT #undef DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_MASK -#define DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_DEFVAL 0x00000000 -#define DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_SHIFT 1 -#define DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_MASK 0x00000002U +#define DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_DEFVAL 0x00000000 +#define DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_SHIFT 1 +#define DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_MASK 0x00000002U -/*Staggering enable for multi-rank accesses (for multi-rank UDIMM and RDIMM implementations only). This is not supported for mD - R, LPDDR2, LPDDR3 or LPDDR4 SDRAMs. Note: Even if this bit is set it does not take care of software driven MR commands (via M - CTRL0/MRCTRL1), where software is responsible to send them to seperate ranks as appropriate. - 1 - (DDR4) Send MRS commands t - each ranks seperately - 1 - (non-DDR4) Send all commands to even and odd ranks seperately - 0 - Do not stagger accesses*/ +/* +* Staggering enable for multi-rank accesses (for multi-rank UDIMM and RDIM + * M implementations only). This is not supported for mDDR, LPDDR2, LPDDR3 + * or LPDDR4 SDRAMs. Note: Even if this bit is set it does not take care of + * software driven MR commands (via MRCTRL0/MRCTRL1), where software is re + * sponsible to send them to seperate ranks as appropriate. - 1 - (DDR4) Se + * nd MRS commands to each ranks seperately - 1 - (non-DDR4) Send all comma + * nds to even and odd ranks seperately - 0 - Do not stagger accesses +*/ #undef DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_DEFVAL #undef DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_SHIFT #undef DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_MASK -#define DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_DEFVAL 0x00000000 -#define DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_SHIFT 0 -#define DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_MASK 0x00000001U +#define DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_DEFVAL 0x00000000 +#define DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_SHIFT 0 +#define DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_MASK 0x00000001U -/*Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecuti - e writes to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This value should c - nsider both PHY requirement and ODT requirement. - PHY requirement: tphy_wrcsgap + 1 (see PHY databook for value of tphy_wrcs - ap) If CRC feature is enabled, should be increased by 1. If write preamble is set to 2tCK(DDR4/LPDDR4 only), should be increa - ed by 1. If write postamble is set to 1.5tCK(LPDDR4 only), should be increased by 1. - ODT requirement: The value programmed - n this register takes care of the ODT switch off timing requirement when switching ranks during writes. For LPDDR4, the requi - ement is ODTLoff - ODTLon - BL/2 + 1 For configurations with MEMC_FREQ_RATIO=1, program this to the larger of PHY requirement - or ODT requirement. For configurations with MEMC_FREQ_RATIO=2, program this to the larger value divided by two and round it u - to the next integer.*/ +/* +* Only present for multi-rank configurations. Indicates the number of cloc + * ks of gap in data responses when performing consecutive writes to differ + * ent ranks. This is used to switch the delays in the PHY to match the ran + * k requirements. This value should consider both PHY requirement and ODT + * requirement. - PHY requirement: tphy_wrcsgap + 1 (see PHY databook for v + * alue of tphy_wrcsgap) If CRC feature is enabled, should be increased by + * 1. If write preamble is set to 2tCK(DDR4/LPDDR4 only), should be increas + * ed by 1. If write postamble is set to 1.5tCK(LPDDR4 only), should be inc + * reased by 1. - ODT requirement: The value programmed in this register ta + * kes care of the ODT switch off timing requirement when switching ranks d + * uring writes. For LPDDR4, the requirement is ODTLoff - ODTLon - BL/2 + 1 + * For configurations with MEMC_FREQ_RATIO=1, program this to the larger o + * f PHY requirement or ODT requirement. For configurations with MEMC_FREQ_ + * RATIO=2, program this to the larger value divided by two and round it up + * to the next integer. +*/ #undef DDRC_RANKCTL_DIFF_RANK_WR_GAP_DEFVAL #undef DDRC_RANKCTL_DIFF_RANK_WR_GAP_SHIFT #undef DDRC_RANKCTL_DIFF_RANK_WR_GAP_MASK -#define DDRC_RANKCTL_DIFF_RANK_WR_GAP_DEFVAL 0x0000066F -#define DDRC_RANKCTL_DIFF_RANK_WR_GAP_SHIFT 8 -#define DDRC_RANKCTL_DIFF_RANK_WR_GAP_MASK 0x00000F00U +#define DDRC_RANKCTL_DIFF_RANK_WR_GAP_DEFVAL 0x0000066F +#define DDRC_RANKCTL_DIFF_RANK_WR_GAP_SHIFT 8 +#define DDRC_RANKCTL_DIFF_RANK_WR_GAP_MASK 0x00000F00U -/*Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecuti - e reads to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This value should co - sider both PHY requirement and ODT requirement. - PHY requirement: tphy_rdcsgap + 1 (see PHY databook for value of tphy_rdcsg - p) If read preamble is set to 2tCK(DDR4/LPDDR4 only), should be increased by 1. If read postamble is set to 1.5tCK(LPDDR4 onl - ), should be increased by 1. - ODT requirement: The value programmed in this register takes care of the ODT switch off timing - requirement when switching ranks during reads. For configurations with MEMC_FREQ_RATIO=1, program this to the larger of PHY r - quirement or ODT requirement. For configurations with MEMC_FREQ_RATIO=2, program this to the larger value divided by two and - ound it up to the next integer.*/ +/* +* Only present for multi-rank configurations. Indicates the number of cloc + * ks of gap in data responses when performing consecutive reads to differe + * nt ranks. This is used to switch the delays in the PHY to match the rank + * requirements. This value should consider both PHY requirement and ODT r + * equirement. - PHY requirement: tphy_rdcsgap + 1 (see PHY databook for va + * lue of tphy_rdcsgap) If read preamble is set to 2tCK(DDR4/LPDDR4 only), + * should be increased by 1. If read postamble is set to 1.5tCK(LPDDR4 only + * ), should be increased by 1. - ODT requirement: The value programmed in + * this register takes care of the ODT switch off timing requirement when s + * witching ranks during reads. For configurations with MEMC_FREQ_RATIO=1, + * program this to the larger of PHY requirement or ODT requirement. For co + * nfigurations with MEMC_FREQ_RATIO=2, program this to the larger value di + * vided by two and round it up to the next integer. +*/ #undef DDRC_RANKCTL_DIFF_RANK_RD_GAP_DEFVAL #undef DDRC_RANKCTL_DIFF_RANK_RD_GAP_SHIFT #undef DDRC_RANKCTL_DIFF_RANK_RD_GAP_MASK -#define DDRC_RANKCTL_DIFF_RANK_RD_GAP_DEFVAL 0x0000066F -#define DDRC_RANKCTL_DIFF_RANK_RD_GAP_SHIFT 4 -#define DDRC_RANKCTL_DIFF_RANK_RD_GAP_MASK 0x000000F0U +#define DDRC_RANKCTL_DIFF_RANK_RD_GAP_DEFVAL 0x0000066F +#define DDRC_RANKCTL_DIFF_RANK_RD_GAP_SHIFT 4 +#define DDRC_RANKCTL_DIFF_RANK_RD_GAP_MASK 0x000000F0U -/*Only present for multi-rank configurations. Background: Reads to the same rank can be performed back-to-back. Reads to differ - nt ranks require additional gap dictated by the register RANKCTL.diff_rank_rd_gap. This is to avoid possible data bus content - on as well as to give PHY enough time to switch the delay when changing ranks. The uMCTL2 arbitrates for bus access on a cycl - -by-cycle basis; therefore after a read is scheduled, there are few clock cycles (determined by the value on RANKCTL.diff_ran - _rd_gap register) in which only reads from the same rank are eligible to be scheduled. This prevents reads from other ranks f - om having fair access to the data bus. This parameter represents the maximum number of reads that can be scheduled consecutiv - ly to the same rank. After this number is reached, a delay equal to RANKCTL.diff_rank_rd_gap is inserted by the scheduler to - llow all ranks a fair opportunity to be scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fair - ess. This feature can be DISABLED by setting this register to 0. When set to 0, the Controller will stay on the same rank as - ong as commands are available for it. Minimum programmable value is 0 (feature disabled) and maximum programmable value is 0x - . FOR PERFORMANCE ONLY.*/ +/* +* Only present for multi-rank configurations. Background: Reads to the sam + * e rank can be performed back-to-back. Reads to different ranks require a + * dditional gap dictated by the register RANKCTL.diff_rank_rd_gap. This is + * to avoid possible data bus contention as well as to give PHY enough tim + * e to switch the delay when changing ranks. The uMCTL2 arbitrates for bus + * access on a cycle-by-cycle basis; therefore after a read is scheduled, + * there are few clock cycles (determined by the value on RANKCTL.diff_rank + * _rd_gap register) in which only reads from the same rank are eligible to + * be scheduled. This prevents reads from other ranks from having fair acc + * ess to the data bus. This parameter represents the maximum number of rea + * ds that can be scheduled consecutively to the same rank. After this numb + * er is reached, a delay equal to RANKCTL.diff_rank_rd_gap is inserted by + * the scheduler to allow all ranks a fair opportunity to be scheduled. Hig + * her numbers increase bandwidth utilization, lower numbers increase fairn + * ess. This feature can be DISABLED by setting this register to 0. When se + * t to 0, the Controller will stay on the same rank as long as commands ar + * e available for it. Minimum programmable value is 0 (feature disabled) a + * nd maximum programmable value is 0xF. FOR PERFORMANCE ONLY. +*/ #undef DDRC_RANKCTL_MAX_RANK_RD_DEFVAL #undef DDRC_RANKCTL_MAX_RANK_RD_SHIFT #undef DDRC_RANKCTL_MAX_RANK_RD_MASK -#define DDRC_RANKCTL_MAX_RANK_RD_DEFVAL 0x0000066F -#define DDRC_RANKCTL_MAX_RANK_RD_SHIFT 0 -#define DDRC_RANKCTL_MAX_RANK_RD_MASK 0x0000000FU +#define DDRC_RANKCTL_MAX_RANK_RD_DEFVAL 0x0000066F +#define DDRC_RANKCTL_MAX_RANK_RD_SHIFT 0 +#define DDRC_RANKCTL_MAX_RANK_RD_MASK 0x0000000FU -/*Minimum time between write and precharge to same bank. Unit: Clocks Specifications: WL + BL/2 + tWR = approximately 8 cycles - 15 ns = 14 clocks @400MHz and less for lower frequencies where: - WL = write latency - BL = burst length. This must match th - value programmed in the BL bit of the mode register to the SDRAM. BST (burst terminate) is not supported at present. - tWR = - Write recovery time. This comes directly from the SDRAM specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 for this - arameter. For configurations with MEMC_FREQ_RATIO=2, 1T mode, divide the above value by 2. No rounding up. For configurations - with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, divide the above value by 2 and round it up to the next integer value.*/ +/* +* Minimum time between write and precharge to same bank. Unit: Clocks Spec + * ifications: WL + BL/2 + tWR = approximately 8 cycles + 15 ns = 14 clocks + * @400MHz and less for lower frequencies where: - WL = write latency - BL + * = burst length. This must match the value programmed in the BL bit of t + * he mode register to the SDRAM. BST (burst terminate) is not supported at + * present. - tWR = Write recovery time. This comes directly from the SDRA + * M specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 for this p + * arameter. For configurations with MEMC_FREQ_RATIO=2, 1T mode, divide the + * above value by 2. No rounding up. For configurations with MEMC_FREQ_RAT + * IO=2, 2T mode or LPDDR4 mode, divide the above value by 2 and round it u + * p to the next integer value. +*/ #undef DDRC_DRAMTMG0_WR2PRE_DEFVAL #undef DDRC_DRAMTMG0_WR2PRE_SHIFT #undef DDRC_DRAMTMG0_WR2PRE_MASK -#define DDRC_DRAMTMG0_WR2PRE_DEFVAL 0x0F101B0F -#define DDRC_DRAMTMG0_WR2PRE_SHIFT 24 -#define DDRC_DRAMTMG0_WR2PRE_MASK 0x7F000000U +#define DDRC_DRAMTMG0_WR2PRE_DEFVAL 0x0F101B0F +#define DDRC_DRAMTMG0_WR2PRE_SHIFT 24 +#define DDRC_DRAMTMG0_WR2PRE_MASK 0x7F000000U -/*tFAW Valid only when 8 or more banks(or banks x bank groups) are present. In 8-bank design, at most 4 banks must be activated - in a rolling window of tFAW cycles. For configurations with MEMC_FREQ_RATIO=2, program this to (tFAW/2) and round up to next - nteger value. In a 4-bank design, set this register to 0x1 independent of the MEMC_FREQ_RATIO configuration. Unit: Clocks*/ +/* +* tFAW Valid only when 8 or more banks(or banks x bank groups) are present + * . In 8-bank design, at most 4 banks must be activated in a rolling windo + * w of tFAW cycles. For configurations with MEMC_FREQ_RATIO=2, program thi + * s to (tFAW/2) and round up to next integer value. In a 4-bank design, se + * t this register to 0x1 independent of the MEMC_FREQ_RATIO configuration. + * Unit: Clocks +*/ #undef DDRC_DRAMTMG0_T_FAW_DEFVAL #undef DDRC_DRAMTMG0_T_FAW_SHIFT #undef DDRC_DRAMTMG0_T_FAW_MASK -#define DDRC_DRAMTMG0_T_FAW_DEFVAL 0x0F101B0F -#define DDRC_DRAMTMG0_T_FAW_SHIFT 16 -#define DDRC_DRAMTMG0_T_FAW_MASK 0x003F0000U +#define DDRC_DRAMTMG0_T_FAW_DEFVAL 0x0F101B0F +#define DDRC_DRAMTMG0_T_FAW_SHIFT 16 +#define DDRC_DRAMTMG0_T_FAW_MASK 0x003F0000U -/*tRAS(max): Maximum time between activate and precharge to same bank. This is the maximum time that a page can be kept open Mi - imum value of this register is 1. Zero is invalid. For configurations with MEMC_FREQ_RATIO=2, program this to (tRAS(max)-1)/2 - No rounding up. Unit: Multiples of 1024 clocks.*/ +/* +* tRAS(max): Maximum time between activate and precharge to same bank. Thi + * s is the maximum time that a page can be kept open Minimum value of this + * register is 1. Zero is invalid. For configurations with MEMC_FREQ_RATIO + * =2, program this to (tRAS(max)-1)/2. No rounding up. Unit: Multiples of + * 1024 clocks. +*/ #undef DDRC_DRAMTMG0_T_RAS_MAX_DEFVAL #undef DDRC_DRAMTMG0_T_RAS_MAX_SHIFT #undef DDRC_DRAMTMG0_T_RAS_MAX_MASK -#define DDRC_DRAMTMG0_T_RAS_MAX_DEFVAL 0x0F101B0F -#define DDRC_DRAMTMG0_T_RAS_MAX_SHIFT 8 -#define DDRC_DRAMTMG0_T_RAS_MAX_MASK 0x00007F00U +#define DDRC_DRAMTMG0_T_RAS_MAX_DEFVAL 0x0F101B0F +#define DDRC_DRAMTMG0_T_RAS_MAX_SHIFT 8 +#define DDRC_DRAMTMG0_T_RAS_MAX_MASK 0x00007F00U -/*tRAS(min): Minimum time between activate and precharge to the same bank. For configurations with MEMC_FREQ_RATIO=2, 1T mode, - rogram this to tRAS(min)/2. No rounding up. For configurations with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, program this t - (tRAS(min)/2) and round it up to the next integer value. Unit: Clocks*/ +/* +* tRAS(min): Minimum time between activate and precharge to the same bank. + * For configurations with MEMC_FREQ_RATIO=2, 1T mode, program this to tRA + * S(min)/2. No rounding up. For configurations with MEMC_FREQ_RATIO=2, 2T + * mode or LPDDR4 mode, program this to (tRAS(min)/2) and round it up to th + * e next integer value. Unit: Clocks +*/ #undef DDRC_DRAMTMG0_T_RAS_MIN_DEFVAL #undef DDRC_DRAMTMG0_T_RAS_MIN_SHIFT #undef DDRC_DRAMTMG0_T_RAS_MIN_MASK -#define DDRC_DRAMTMG0_T_RAS_MIN_DEFVAL 0x0F101B0F -#define DDRC_DRAMTMG0_T_RAS_MIN_SHIFT 0 -#define DDRC_DRAMTMG0_T_RAS_MIN_MASK 0x0000003FU +#define DDRC_DRAMTMG0_T_RAS_MIN_DEFVAL 0x0F101B0F +#define DDRC_DRAMTMG0_T_RAS_MIN_SHIFT 0 +#define DDRC_DRAMTMG0_T_RAS_MIN_MASK 0x0000003FU -/*tXP: Minimum time after power-down exit to any operation. For DDR3, this should be programmed to tXPDLL if slow powerdown exi - is selected in MR0[12]. If C/A parity for DDR4 is used, set to (tXP+PL) instead. For configurations with MEMC_FREQ_RATIO=2, - rogram this to (tXP/2) and round it up to the next integer value. Units: Clocks*/ +/* +* tXP: Minimum time after power-down exit to any operation. For DDR3, this + * should be programmed to tXPDLL if slow powerdown exit is selected in MR + * 0[12]. If C/A parity for DDR4 is used, set to (tXP+PL) instead. For conf + * igurations with MEMC_FREQ_RATIO=2, program this to (tXP/2) and round it + * up to the next integer value. Units: Clocks +*/ #undef DDRC_DRAMTMG1_T_XP_DEFVAL #undef DDRC_DRAMTMG1_T_XP_SHIFT #undef DDRC_DRAMTMG1_T_XP_MASK -#define DDRC_DRAMTMG1_T_XP_DEFVAL 0x00080414 -#define DDRC_DRAMTMG1_T_XP_SHIFT 16 -#define DDRC_DRAMTMG1_T_XP_MASK 0x001F0000U +#define DDRC_DRAMTMG1_T_XP_DEFVAL 0x00080414 +#define DDRC_DRAMTMG1_T_XP_SHIFT 16 +#define DDRC_DRAMTMG1_T_XP_MASK 0x001F0000U -/*tRTP: Minimum time from read to precharge of same bank. - DDR2: tAL + BL/2 + max(tRTP, 2) - 2 - DDR3: tAL + max (tRTP, 4) - D - R4: Max of following two equations: tAL + max (tRTP, 4) or, RL + BL/2 - tRP. - mDDR: BL/2 - LPDDR2: Depends on if it's LPDDR2 - S2 or LPDDR2-S4: LPDDR2-S2: BL/2 + tRTP - 1. LPDDR2-S4: BL/2 + max(tRTP,2) - 2. - LPDDR3: BL/2 + max(tRTP,4) - 4 - LPDDR4: BL - 2 + max(tRTP,8) - 8 For configurations with MEMC_FREQ_RATIO=2, 1T mode, divide the above value by 2. No rounding up. For conf - gurations with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, divide the above value by 2 and round it up to the next integer val - e. Unit: Clocks.*/ +/* +* tRTP: Minimum time from read to precharge of same bank. - DDR2: tAL + BL + * /2 + max(tRTP, 2) - 2 - DDR3: tAL + max (tRTP, 4) - DDR4: Max of followi + * ng two equations: tAL + max (tRTP, 4) or, RL + BL/2 - tRP. - mDDR: BL/2 + * - LPDDR2: Depends on if it's LPDDR2-S2 or LPDDR2-S4: LPDDR2-S2: BL/2 + t + * RTP - 1. LPDDR2-S4: BL/2 + max(tRTP,2) - 2. - LPDDR3: BL/2 + max(tRTP,4) + * - 4 - LPDDR4: BL/2 + max(tRTP,8) - 8 For configurations with MEMC_FREQ_ + * RATIO=2, 1T mode, divide the above value by 2. No rounding up. For confi + * gurations with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, divide the abo + * ve value by 2 and round it up to the next integer value. Unit: Clocks. +*/ #undef DDRC_DRAMTMG1_RD2PRE_DEFVAL #undef DDRC_DRAMTMG1_RD2PRE_SHIFT #undef DDRC_DRAMTMG1_RD2PRE_MASK -#define DDRC_DRAMTMG1_RD2PRE_DEFVAL 0x00080414 -#define DDRC_DRAMTMG1_RD2PRE_SHIFT 8 -#define DDRC_DRAMTMG1_RD2PRE_MASK 0x00001F00U +#define DDRC_DRAMTMG1_RD2PRE_DEFVAL 0x00080414 +#define DDRC_DRAMTMG1_RD2PRE_SHIFT 8 +#define DDRC_DRAMTMG1_RD2PRE_MASK 0x00001F00U -/*tRC: Minimum time between activates to same bank. For configurations with MEMC_FREQ_RATIO=2, program this to (tRC/2) and roun - up to next integer value. Unit: Clocks.*/ +/* +* tRC: Minimum time between activates to same bank. For configurations wit + * h MEMC_FREQ_RATIO=2, program this to (tRC/2) and round up to next intege + * r value. Unit: Clocks. +*/ #undef DDRC_DRAMTMG1_T_RC_DEFVAL #undef DDRC_DRAMTMG1_T_RC_SHIFT #undef DDRC_DRAMTMG1_T_RC_MASK -#define DDRC_DRAMTMG1_T_RC_DEFVAL 0x00080414 -#define DDRC_DRAMTMG1_T_RC_SHIFT 0 -#define DDRC_DRAMTMG1_T_RC_MASK 0x0000007FU +#define DDRC_DRAMTMG1_T_RC_DEFVAL 0x00080414 +#define DDRC_DRAMTMG1_T_RC_SHIFT 0 +#define DDRC_DRAMTMG1_T_RC_MASK 0x0000007FU -/*Set to WL Time from write command to write data on SDRAM interface. This must be set to WL. For mDDR, it should normally be s - t to 1. Note that, depending on the PHY, if using RDIMM, it may be necessary to use a value of WL + 1 to compensate for the e - tra cycle of latency through the RDIMM For configurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above - equation by 2, and round it up to next integer. This register field is not required for DDR2 and DDR3 (except if MEMC_TRAININ - is set), as the DFI read and write latencies defined in DFITMG0 and DFITMG1 are sufficient for those protocols Unit: clocks*/ +/* +* Set to WL Time from write command to write data on SDRAM interface. This + * must be set to WL. For mDDR, it should normally be set to 1. Note that, + * depending on the PHY, if using RDIMM, it may be necessary to use a valu + * e of WL + 1 to compensate for the extra cycle of latency through the RDI + * MM For configurations with MEMC_FREQ_RATIO=2, divide the value calculate + * d using the above equation by 2, and round it up to next integer. This r + * egister field is not required for DDR2 and DDR3 (except if MEMC_TRAINING + * is set), as the DFI read and write latencies defined in DFITMG0 and DFI + * TMG1 are sufficient for those protocols Unit: clocks +*/ #undef DDRC_DRAMTMG2_WRITE_LATENCY_DEFVAL #undef DDRC_DRAMTMG2_WRITE_LATENCY_SHIFT #undef DDRC_DRAMTMG2_WRITE_LATENCY_MASK -#define DDRC_DRAMTMG2_WRITE_LATENCY_DEFVAL 0x0305060D -#define DDRC_DRAMTMG2_WRITE_LATENCY_SHIFT 24 -#define DDRC_DRAMTMG2_WRITE_LATENCY_MASK 0x3F000000U +#define DDRC_DRAMTMG2_WRITE_LATENCY_DEFVAL 0x0305060D +#define DDRC_DRAMTMG2_WRITE_LATENCY_SHIFT 24 +#define DDRC_DRAMTMG2_WRITE_LATENCY_MASK 0x3F000000U -/*Set to RL Time from read command to read data on SDRAM interface. This must be set to RL. Note that, depending on the PHY, if - using RDIMM, it mat be necessary to use a value of RL + 1 to compensate for the extra cycle of latency through the RDIMM For - onfigurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next inte - er. This register field is not required for DDR2 and DDR3 (except if MEMC_TRAINING is set), as the DFI read and write latenci - s defined in DFITMG0 and DFITMG1 are sufficient for those protocols Unit: clocks*/ +/* +* Set to RL Time from read command to read data on SDRAM interface. This m + * ust be set to RL. Note that, depending on the PHY, if using RDIMM, it ma + * t be necessary to use a value of RL + 1 to compensate for the extra cycl + * e of latency through the RDIMM For configurations with MEMC_FREQ_RATIO=2 + * , divide the value calculated using the above equation by 2, and round i + * t up to next integer. This register field is not required for DDR2 and D + * DR3 (except if MEMC_TRAINING is set), as the DFI read and write latencie + * s defined in DFITMG0 and DFITMG1 are sufficient for those protocols Unit + * : clocks +*/ #undef DDRC_DRAMTMG2_READ_LATENCY_DEFVAL #undef DDRC_DRAMTMG2_READ_LATENCY_SHIFT #undef DDRC_DRAMTMG2_READ_LATENCY_MASK -#define DDRC_DRAMTMG2_READ_LATENCY_DEFVAL 0x0305060D -#define DDRC_DRAMTMG2_READ_LATENCY_SHIFT 16 -#define DDRC_DRAMTMG2_READ_LATENCY_MASK 0x003F0000U +#define DDRC_DRAMTMG2_READ_LATENCY_DEFVAL 0x0305060D +#define DDRC_DRAMTMG2_READ_LATENCY_SHIFT 16 +#define DDRC_DRAMTMG2_READ_LATENCY_MASK 0x003F0000U -/*DDR2/3/mDDR: RL + BL/2 + 2 - WL DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL LPDDR2/LPDDR3: RL + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL - PDDR4(DQ ODT is Disabled): RL + BL/2 + RU(tDQSCKmax/tCK) + WR_PREAMBLE + RD_POSTAMBLE - WL LPDDR4(DQ ODT is Enabled) : RL + B - /2 + RU(tDQSCKmax/tCK) + RD_POSTAMBLE - ODTLon - RU(tODTon(min)/tCK) Minimum time from read command to write command. Include - time for bus turnaround and all per-bank, per-rank, and global constraints. Unit: Clocks. Where: - WL = write latency - BL = - urst length. This must match the value programmed in the BL bit of the mode register to the SDRAM - RL = read latency = CAS l - tency - WR_PREAMBLE = write preamble. This is unique to DDR4 and LPDDR4. - RD_POSTAMBLE = read postamble. This is unique to L - DDR4. For LPDDR2/LPDDR3/LPDDR4, if derating is enabled (DERATEEN.derate_enable=1), derated tDQSCKmax should be used. For conf - gurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next integer.*/ +/* +* DDR2/3/mDDR: RL + BL/2 + 2 - WL DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL L + * PDDR2/LPDDR3: RL + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL LPDDR4(DQ ODT is Di + * sabled): RL + BL/2 + RU(tDQSCKmax/tCK) + WR_PREAMBLE + RD_POSTAMBLE - WL + * LPDDR4(DQ ODT is Enabled) : RL + BL/2 + RU(tDQSCKmax/tCK) + RD_POSTAMBL + * E - ODTLon - RU(tODTon(min)/tCK) Minimum time from read command to write + * command. Include time for bus turnaround and all per-bank, per-rank, an + * d global constraints. Unit: Clocks. Where: - WL = write latency - BL = b + * urst length. This must match the value programmed in the BL bit of the m + * ode register to the SDRAM - RL = read latency = CAS latency - WR_PREAMBL + * E = write preamble. This is unique to DDR4 and LPDDR4. - RD_POSTAMBLE = + * read postamble. This is unique to LPDDR4. For LPDDR2/LPDDR3/LPDDR4, if d + * erating is enabled (DERATEEN.derate_enable=1), derated tDQSCKmax should + * be used. For configurations with MEMC_FREQ_RATIO=2, divide the value cal + * culated using the above equation by 2, and round it up to next integer. +*/ #undef DDRC_DRAMTMG2_RD2WR_DEFVAL #undef DDRC_DRAMTMG2_RD2WR_SHIFT #undef DDRC_DRAMTMG2_RD2WR_MASK -#define DDRC_DRAMTMG2_RD2WR_DEFVAL 0x0305060D -#define DDRC_DRAMTMG2_RD2WR_SHIFT 8 -#define DDRC_DRAMTMG2_RD2WR_MASK 0x00003F00U +#define DDRC_DRAMTMG2_RD2WR_DEFVAL 0x0305060D +#define DDRC_DRAMTMG2_RD2WR_SHIFT 8 +#define DDRC_DRAMTMG2_RD2WR_MASK 0x00003F00U -/*DDR4: CWL + PL + BL/2 + tWTR_L Others: CWL + BL/2 + tWTR In DDR4, minimum time from write command to read command for same ba - k group. In others, minimum time from write command to read command. Includes time for bus turnaround, recovery times, and al - per-bank, per-rank, and global constraints. Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity latency - BL = burs - length. This must match the value programmed in the BL bit of the mode register to the SDRAM - tWTR_L = internal write to re - d command delay for same bank group. This comes directly from the SDRAM specification. - tWTR = internal write to read comman - delay. This comes directly from the SDRAM specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 operation. For configu - ations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next integer.*/ +/* +* DDR4: CWL + PL + BL/2 + tWTR_L Others: CWL + BL/2 + tWTR In DDR4, minimu + * m time from write command to read command for same bank group. In others + * , minimum time from write command to read command. Includes time for bus + * turnaround, recovery times, and all per-bank, per-rank, and global cons + * traints. Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity la + * tency - BL = burst length. This must match the value programmed in the B + * L bit of the mode register to the SDRAM - tWTR_L = internal write to rea + * d command delay for same bank group. This comes directly from the SDRAM + * specification. - tWTR = internal write to read command delay. This comes + * directly from the SDRAM specification. Add one extra cycle for LPDDR2/L + * PDDR3/LPDDR4 operation. For configurations with MEMC_FREQ_RATIO=2, divid + * e the value calculated using the above equation by 2, and round it up to + * next integer. +*/ #undef DDRC_DRAMTMG2_WR2RD_DEFVAL #undef DDRC_DRAMTMG2_WR2RD_SHIFT #undef DDRC_DRAMTMG2_WR2RD_MASK -#define DDRC_DRAMTMG2_WR2RD_DEFVAL 0x0305060D -#define DDRC_DRAMTMG2_WR2RD_SHIFT 0 -#define DDRC_DRAMTMG2_WR2RD_MASK 0x0000003FU +#define DDRC_DRAMTMG2_WR2RD_DEFVAL 0x0305060D +#define DDRC_DRAMTMG2_WR2RD_SHIFT 0 +#define DDRC_DRAMTMG2_WR2RD_MASK 0x0000003FU -/*Time to wait after a mode register write or read (MRW or MRR). Present only in designs configured to support LPDDR2, LPDDR3 o - LPDDR4. LPDDR2 typically requires value of 5. LPDDR3 typically requires value of 10. LPDDR4: Set this to the larger of tMRW - nd tMRWCKEL. For LPDDR2, this register is used for the time from a MRW/MRR to all other commands. For LDPDR3, this register i - used for the time from a MRW/MRR to a MRW/MRR.*/ +/* +* Time to wait after a mode register write or read (MRW or MRR). Present o + * nly in designs configured to support LPDDR2, LPDDR3 or LPDDR4. LPDDR2 ty + * pically requires value of 5. LPDDR3 typically requires value of 10. LPDD + * R4: Set this to the larger of tMRW and tMRWCKEL. For LPDDR2, this regist + * er is used for the time from a MRW/MRR to all other commands. For LDPDR3 + * , this register is used for the time from a MRW/MRR to a MRW/MRR. +*/ #undef DDRC_DRAMTMG3_T_MRW_DEFVAL #undef DDRC_DRAMTMG3_T_MRW_SHIFT #undef DDRC_DRAMTMG3_T_MRW_MASK -#define DDRC_DRAMTMG3_T_MRW_DEFVAL 0x0050400C -#define DDRC_DRAMTMG3_T_MRW_SHIFT 20 -#define DDRC_DRAMTMG3_T_MRW_MASK 0x3FF00000U +#define DDRC_DRAMTMG3_T_MRW_DEFVAL 0x0050400C +#define DDRC_DRAMTMG3_T_MRW_SHIFT 20 +#define DDRC_DRAMTMG3_T_MRW_MASK 0x3FF00000U -/*tMRD: Cycles to wait after a mode register write or read. Depending on the connected SDRAM, tMRD represents: DDR2/mDDR: Time - rom MRS to any command DDR3/4: Time from MRS to MRS command LPDDR2: not used LPDDR3/4: Time from MRS to non-MRS command For c - nfigurations with MEMC_FREQ_RATIO=2, program this to (tMRD/2) and round it up to the next integer value. If C/A parity for DD - 4 is used, set to tMRD_PAR(tMOD+PL) instead.*/ +/* +* tMRD: Cycles to wait after a mode register write or read. Depending on t + * he connected SDRAM, tMRD represents: DDR2/mDDR: Time from MRS to any com + * mand DDR3/4: Time from MRS to MRS command LPDDR2: not used LPDDR3/4: Tim + * e from MRS to non-MRS command For configurations with MEMC_FREQ_RATIO=2, + * program this to (tMRD/2) and round it up to the next integer value. If + * C/A parity for DDR4 is used, set to tMRD_PAR(tMOD+PL) instead. +*/ #undef DDRC_DRAMTMG3_T_MRD_DEFVAL #undef DDRC_DRAMTMG3_T_MRD_SHIFT #undef DDRC_DRAMTMG3_T_MRD_MASK -#define DDRC_DRAMTMG3_T_MRD_DEFVAL 0x0050400C -#define DDRC_DRAMTMG3_T_MRD_SHIFT 12 -#define DDRC_DRAMTMG3_T_MRD_MASK 0x0003F000U +#define DDRC_DRAMTMG3_T_MRD_DEFVAL 0x0050400C +#define DDRC_DRAMTMG3_T_MRD_SHIFT 12 +#define DDRC_DRAMTMG3_T_MRD_MASK 0x0003F000U -/*tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode command and following non-load mode command. If C/A pari - y for DDR4 is used, set to tMOD_PAR(tMOD+PL) instead. Set to tMOD if MEMC_FREQ_RATIO=1, or tMOD/2 (rounded up to next integer - if MEMC_FREQ_RATIO=2. Note that if using RDIMM, depending on the PHY, it may be necessary to use a value of tMOD + 1 or (tMO - + 1)/2 to compensate for the extra cycle of latency applied to mode register writes by the RDIMM chip.*/ +/* +* tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode com + * mand and following non-load mode command. If C/A parity for DDR4 is used + * , set to tMOD_PAR(tMOD+PL) instead. Set to tMOD if MEMC_FREQ_RATIO=1, or + * tMOD/2 (rounded up to next integer) if MEMC_FREQ_RATIO=2. Note that if + * using RDIMM, depending on the PHY, it may be necessary to use a value of + * tMOD + 1 or (tMOD + 1)/2 to compensate for the extra cycle of latency a + * pplied to mode register writes by the RDIMM chip. +*/ #undef DDRC_DRAMTMG3_T_MOD_DEFVAL #undef DDRC_DRAMTMG3_T_MOD_SHIFT #undef DDRC_DRAMTMG3_T_MOD_MASK -#define DDRC_DRAMTMG3_T_MOD_DEFVAL 0x0050400C -#define DDRC_DRAMTMG3_T_MOD_SHIFT 0 -#define DDRC_DRAMTMG3_T_MOD_MASK 0x000003FFU +#define DDRC_DRAMTMG3_T_MOD_DEFVAL 0x0050400C +#define DDRC_DRAMTMG3_T_MOD_SHIFT 0 +#define DDRC_DRAMTMG3_T_MOD_MASK 0x000003FFU -/*tRCD - tAL: Minimum time from activate to read or write command to same bank. For configurations with MEMC_FREQ_RATIO=2, prog - am this to ((tRCD - tAL)/2) and round it up to the next integer value. Minimum value allowed for this register is 1, which im - lies minimum (tRCD - tAL) value to be 2 in configurations with MEMC_FREQ_RATIO=2. Unit: Clocks.*/ +/* +* tRCD - tAL: Minimum time from activate to read or write command to same + * bank. For configurations with MEMC_FREQ_RATIO=2, program this to ((tRCD + * - tAL)/2) and round it up to the next integer value. Minimum value allow + * ed for this register is 1, which implies minimum (tRCD - tAL) value to b + * e 2 in configurations with MEMC_FREQ_RATIO=2. Unit: Clocks. +*/ #undef DDRC_DRAMTMG4_T_RCD_DEFVAL #undef DDRC_DRAMTMG4_T_RCD_SHIFT #undef DDRC_DRAMTMG4_T_RCD_MASK -#define DDRC_DRAMTMG4_T_RCD_DEFVAL 0x05040405 -#define DDRC_DRAMTMG4_T_RCD_SHIFT 24 -#define DDRC_DRAMTMG4_T_RCD_MASK 0x1F000000U +#define DDRC_DRAMTMG4_T_RCD_DEFVAL 0x05040405 +#define DDRC_DRAMTMG4_T_RCD_SHIFT 24 +#define DDRC_DRAMTMG4_T_RCD_MASK 0x1F000000U -/*DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank group. Others: tCCD: This is the minimum - time between two reads or two writes. For configurations with MEMC_FREQ_RATIO=2, program this to (tCCD_L/2 or tCCD/2) and rou - d it up to the next integer value. Unit: clocks.*/ +/* +* DDR4: tCCD_L: This is the minimum time between two reads or two writes f + * or same bank group. Others: tCCD: This is the minimum time between two r + * eads or two writes. For configurations with MEMC_FREQ_RATIO=2, program t + * his to (tCCD_L/2 or tCCD/2) and round it up to the next integer value. U + * nit: clocks. +*/ #undef DDRC_DRAMTMG4_T_CCD_DEFVAL #undef DDRC_DRAMTMG4_T_CCD_SHIFT #undef DDRC_DRAMTMG4_T_CCD_MASK -#define DDRC_DRAMTMG4_T_CCD_DEFVAL 0x05040405 -#define DDRC_DRAMTMG4_T_CCD_SHIFT 16 -#define DDRC_DRAMTMG4_T_CCD_MASK 0x000F0000U +#define DDRC_DRAMTMG4_T_CCD_DEFVAL 0x05040405 +#define DDRC_DRAMTMG4_T_CCD_SHIFT 16 +#define DDRC_DRAMTMG4_T_CCD_MASK 0x000F0000U -/*DDR4: tRRD_L: Minimum time between activates from bank 'a' to bank 'b' for same bank group. Others: tRRD: Minimum time betwee - activates from bank 'a' to bank 'b'For configurations with MEMC_FREQ_RATIO=2, program this to (tRRD_L/2 or tRRD/2) and round - it up to the next integer value. Unit: Clocks.*/ +/* +* DDR4: tRRD_L: Minimum time between activates from bank 'a' to bank 'b' f + * or same bank group. Others: tRRD: Minimum time between activates from ba + * nk 'a' to bank 'b'For configurations with MEMC_FREQ_RATIO=2, program thi + * s to (tRRD_L/2 or tRRD/2) and round it up to the next integer value. Uni + * t: Clocks. +*/ #undef DDRC_DRAMTMG4_T_RRD_DEFVAL #undef DDRC_DRAMTMG4_T_RRD_SHIFT #undef DDRC_DRAMTMG4_T_RRD_MASK -#define DDRC_DRAMTMG4_T_RRD_DEFVAL 0x05040405 -#define DDRC_DRAMTMG4_T_RRD_SHIFT 8 -#define DDRC_DRAMTMG4_T_RRD_MASK 0x00000F00U +#define DDRC_DRAMTMG4_T_RRD_DEFVAL 0x05040405 +#define DDRC_DRAMTMG4_T_RRD_SHIFT 8 +#define DDRC_DRAMTMG4_T_RRD_MASK 0x00000F00U -/*tRP: Minimum time from precharge to activate of same bank. For MEMC_FREQ_RATIO=1 configurations, t_rp should be set to RoundU - (tRP/tCK). For MEMC_FREQ_RATIO=2 configurations, t_rp should be set to RoundDown(RoundUp(tRP/tCK)/2) + 1. For MEMC_FREQ_RATIO - 2 configurations in LPDDR4, t_rp should be set to RoundUp(RoundUp(tRP/tCK)/2). Unit: Clocks.*/ +/* +* tRP: Minimum time from precharge to activate of same bank. For MEMC_FREQ + * _RATIO=1 configurations, t_rp should be set to RoundUp(tRP/tCK). For MEM + * C_FREQ_RATIO=2 configurations, t_rp should be set to RoundDown(RoundUp(t + * RP/tCK)/2) + 1. For MEMC_FREQ_RATIO=2 configurations in LPDDR4, t_rp sho + * uld be set to RoundUp(RoundUp(tRP/tCK)/2). Unit: Clocks. +*/ #undef DDRC_DRAMTMG4_T_RP_DEFVAL #undef DDRC_DRAMTMG4_T_RP_SHIFT #undef DDRC_DRAMTMG4_T_RP_MASK -#define DDRC_DRAMTMG4_T_RP_DEFVAL 0x05040405 -#define DDRC_DRAMTMG4_T_RP_SHIFT 0 -#define DDRC_DRAMTMG4_T_RP_MASK 0x0000001FU +#define DDRC_DRAMTMG4_T_RP_DEFVAL 0x05040405 +#define DDRC_DRAMTMG4_T_RP_SHIFT 0 +#define DDRC_DRAMTMG4_T_RP_MASK 0x0000001FU -/*This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stab - e time before SRX. Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEH - DDR2: 1 - DDR3: tCKSRX - DDR4: - tCKSRX For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it up to next in - eger.*/ +/* +* This is the time before Self Refresh Exit that CK is maintained as a val + * id clock before issuing SRX. Specifies the clock stable time before SRX. + * Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCK + * EH - DDR2: 1 - DDR3: tCKSRX - DDR4: tCKSRX For configurations with MEMC_ + * FREQ_RATIO=2, program this to recommended value divided by two and round + * it up to next integer. +*/ #undef DDRC_DRAMTMG5_T_CKSRX_DEFVAL #undef DDRC_DRAMTMG5_T_CKSRX_SHIFT #undef DDRC_DRAMTMG5_T_CKSRX_MASK -#define DDRC_DRAMTMG5_T_CKSRX_DEFVAL 0x05050403 -#define DDRC_DRAMTMG5_T_CKSRX_SHIFT 24 -#define DDRC_DRAMTMG5_T_CKSRX_MASK 0x0F000000U +#define DDRC_DRAMTMG5_T_CKSRX_DEFVAL 0x05050403 +#define DDRC_DRAMTMG5_T_CKSRX_SHIFT 24 +#define DDRC_DRAMTMG5_T_CKSRX_MASK 0x0F000000U -/*This is the time after Self Refresh Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay afte - SRE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL - DDR2: 1 - DDR3: max (10 ns, 5 tCK) - DDR4: - ax (10 ns, 5 tCK) For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it up - to next integer.*/ +/* +* This is the time after Self Refresh Down Entry that CK is maintained as + * a valid clock. Specifies the clock disable delay after SRE. Recommended + * settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL - DDR2: 1 + * - DDR3: max (10 ns, 5 tCK) - DDR4: max (10 ns, 5 tCK) For configurations + * with MEMC_FREQ_RATIO=2, program this to recommended value divided by tw + * o and round it up to next integer. +*/ #undef DDRC_DRAMTMG5_T_CKSRE_DEFVAL #undef DDRC_DRAMTMG5_T_CKSRE_SHIFT #undef DDRC_DRAMTMG5_T_CKSRE_MASK -#define DDRC_DRAMTMG5_T_CKSRE_DEFVAL 0x05050403 -#define DDRC_DRAMTMG5_T_CKSRE_SHIFT 16 -#define DDRC_DRAMTMG5_T_CKSRE_MASK 0x000F0000U +#define DDRC_DRAMTMG5_T_CKSRE_DEFVAL 0x05050403 +#define DDRC_DRAMTMG5_T_CKSRE_SHIFT 16 +#define DDRC_DRAMTMG5_T_CKSRE_MASK 0x000F0000U -/*Minimum CKE low width for Self refresh or Self refresh power down entry to exit timing in memory clock cycles. Recommended se - tings: - mDDR: tRFC - LPDDR2: tCKESR - LPDDR3: tCKESR - LPDDR4: max(tCKELPD, tSR) - DDR2: tCKE - DDR3: tCKE + 1 - DDR4: tCKE - 1 For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it up to next intege - .*/ +/* +* Minimum CKE low width for Self refresh or Self refresh power down entry + * to exit timing in memory clock cycles. Recommended settings: - mDDR: tRF + * C - LPDDR2: tCKESR - LPDDR3: tCKESR - LPDDR4: max(tCKELPD, tSR) - DDR2: + * tCKE - DDR3: tCKE + 1 - DDR4: tCKE + 1 For configurations with MEMC_FREQ + * _RATIO=2, program this to recommended value divided by two and round it + * up to next integer. +*/ #undef DDRC_DRAMTMG5_T_CKESR_DEFVAL #undef DDRC_DRAMTMG5_T_CKESR_SHIFT #undef DDRC_DRAMTMG5_T_CKESR_MASK -#define DDRC_DRAMTMG5_T_CKESR_DEFVAL 0x05050403 -#define DDRC_DRAMTMG5_T_CKESR_SHIFT 8 -#define DDRC_DRAMTMG5_T_CKESR_MASK 0x00003F00U +#define DDRC_DRAMTMG5_T_CKESR_DEFVAL 0x05050403 +#define DDRC_DRAMTMG5_T_CKESR_SHIFT 8 +#define DDRC_DRAMTMG5_T_CKESR_MASK 0x00003F00U -/*Minimum number of cycles of CKE HIGH/LOW during power-down and self refresh. - LPDDR2/LPDDR3 mode: Set this to the larger of - CKE or tCKESR - LPDDR4 mode: Set this to the larger of tCKE, tCKELPD or tSR. - Non-LPDDR2/non-LPDDR3/non-LPDDR4 designs: Set - his to tCKE value. For configurations with MEMC_FREQ_RATIO=2, program this to (value described above)/2 and round it up to th - next integer value. Unit: Clocks.*/ +/* +* Minimum number of cycles of CKE HIGH/LOW during power-down and self refr + * esh. - LPDDR2/LPDDR3 mode: Set this to the larger of tCKE or tCKESR - LP + * DDR4 mode: Set this to the larger of tCKE, tCKELPD or tSR. - Non-LPDDR2/ + * non-LPDDR3/non-LPDDR4 designs: Set this to tCKE value. For configuration + * s with MEMC_FREQ_RATIO=2, program this to (value described above)/2 and + * round it up to the next integer value. Unit: Clocks. +*/ #undef DDRC_DRAMTMG5_T_CKE_DEFVAL #undef DDRC_DRAMTMG5_T_CKE_SHIFT #undef DDRC_DRAMTMG5_T_CKE_MASK -#define DDRC_DRAMTMG5_T_CKE_DEFVAL 0x05050403 -#define DDRC_DRAMTMG5_T_CKE_SHIFT 0 -#define DDRC_DRAMTMG5_T_CKE_MASK 0x0000001FU +#define DDRC_DRAMTMG5_T_CKE_DEFVAL 0x05050403 +#define DDRC_DRAMTMG5_T_CKE_SHIFT 0 +#define DDRC_DRAMTMG5_T_CKE_MASK 0x0000001FU -/*This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after - PDE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 For configurations with MEMC_FREQ_RATIO=2, program this to recom - ended value divided by two and round it up to next integer. This is only present for designs supporting mDDR or LPDDR2/LPDDR3 - devices.*/ +/* +* This is the time after Deep Power Down Entry that CK is maintained as a + * valid clock. Specifies the clock disable delay after DPDE. Recommended s + * ettings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 For configurations with MEMC_ + * FREQ_RATIO=2, program this to recommended value divided by two and round + * it up to next integer. This is only present for designs supporting mDDR + * or LPDDR2/LPDDR3 devices. +*/ #undef DDRC_DRAMTMG6_T_CKDPDE_DEFVAL #undef DDRC_DRAMTMG6_T_CKDPDE_SHIFT #undef DDRC_DRAMTMG6_T_CKDPDE_MASK -#define DDRC_DRAMTMG6_T_CKDPDE_DEFVAL 0x02020005 -#define DDRC_DRAMTMG6_T_CKDPDE_SHIFT 24 -#define DDRC_DRAMTMG6_T_CKDPDE_MASK 0x0F000000U +#define DDRC_DRAMTMG6_T_CKDPDE_DEFVAL 0x02020005 +#define DDRC_DRAMTMG6_T_CKDPDE_SHIFT 24 +#define DDRC_DRAMTMG6_T_CKDPDE_MASK 0x0F000000U -/*This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock - table time before DPDX. Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 For configurations with MEMC_FREQ_RATIO=2, pr - gram this to recommended value divided by two and round it up to next integer. This is only present for designs supporting mD - R or LPDDR2 devices.*/ +/* +* This is the time before Deep Power Down Exit that CK is maintained as a + * valid clock before issuing DPDX. Specifies the clock stable time before + * DPDX. Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 For config + * urations with MEMC_FREQ_RATIO=2, program this to recommended value divid + * ed by two and round it up to next integer. This is only present for desi + * gns supporting mDDR or LPDDR2 devices. +*/ #undef DDRC_DRAMTMG6_T_CKDPDX_DEFVAL #undef DDRC_DRAMTMG6_T_CKDPDX_SHIFT #undef DDRC_DRAMTMG6_T_CKDPDX_MASK -#define DDRC_DRAMTMG6_T_CKDPDX_DEFVAL 0x02020005 -#define DDRC_DRAMTMG6_T_CKDPDX_SHIFT 16 -#define DDRC_DRAMTMG6_T_CKDPDX_MASK 0x000F0000U +#define DDRC_DRAMTMG6_T_CKDPDX_DEFVAL 0x02020005 +#define DDRC_DRAMTMG6_T_CKDPDX_SHIFT 16 +#define DDRC_DRAMTMG6_T_CKDPDX_MASK 0x000F0000U -/*This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing Clock Stop Exit. Specifies the - lock stable time before next command after Clock Stop Exit. Recommended settings: - mDDR: 1 - LPDDR2: tXP + 2 - LPDDR3: tXP + - 2 - LPDDR4: tXP + 2 For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it - p to next integer. This is only present for designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices.*/ +/* +* This is the time before Clock Stop Exit that CK is maintained as a valid + * clock before issuing Clock Stop Exit. Specifies the clock stable time b + * efore next command after Clock Stop Exit. Recommended settings: - mDDR: + * 1 - LPDDR2: tXP + 2 - LPDDR3: tXP + 2 - LPDDR4: tXP + 2 For configuratio + * ns with MEMC_FREQ_RATIO=2, program this to recommended value divided by + * two and round it up to next integer. This is only present for designs su + * pporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices. +*/ #undef DDRC_DRAMTMG6_T_CKCSX_DEFVAL #undef DDRC_DRAMTMG6_T_CKCSX_SHIFT #undef DDRC_DRAMTMG6_T_CKCSX_MASK -#define DDRC_DRAMTMG6_T_CKCSX_DEFVAL 0x02020005 -#define DDRC_DRAMTMG6_T_CKCSX_SHIFT 0 -#define DDRC_DRAMTMG6_T_CKCSX_MASK 0x0000000FU +#define DDRC_DRAMTMG6_T_CKCSX_DEFVAL 0x02020005 +#define DDRC_DRAMTMG6_T_CKCSX_SHIFT 0 +#define DDRC_DRAMTMG6_T_CKCSX_MASK 0x0000000FU -/*This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. - ecommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL For configurations with MEMC_FREQ_RATIO=2, program t - is to recommended value divided by two and round it up to next integer. This is only present for designs supporting mDDR or L - DDR2/LPDDR3/LPDDR4 devices.*/ +/* +* This is the time after Power Down Entry that CK is maintained as a valid + * clock. Specifies the clock disable delay after PDE. Recommended setting + * s: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL For configuration + * s with MEMC_FREQ_RATIO=2, program this to recommended value divided by t + * wo and round it up to next integer. This is only present for designs sup + * porting mDDR or LPDDR2/LPDDR3/LPDDR4 devices. +*/ #undef DDRC_DRAMTMG7_T_CKPDE_DEFVAL #undef DDRC_DRAMTMG7_T_CKPDE_SHIFT #undef DDRC_DRAMTMG7_T_CKPDE_MASK -#define DDRC_DRAMTMG7_T_CKPDE_DEFVAL 0x00000202 -#define DDRC_DRAMTMG7_T_CKPDE_SHIFT 8 -#define DDRC_DRAMTMG7_T_CKPDE_MASK 0x00000F00U +#define DDRC_DRAMTMG7_T_CKPDE_DEFVAL 0x00000202 +#define DDRC_DRAMTMG7_T_CKPDE_SHIFT 8 +#define DDRC_DRAMTMG7_T_CKPDE_MASK 0x00000F00U -/*This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable - time before PDX. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: 2 For configurations with MEMC_FREQ_RATIO= - , program this to recommended value divided by two and round it up to next integer. This is only present for designs supporti - g mDDR or LPDDR2/LPDDR3/LPDDR4 devices.*/ +/* +* This is the time before Power Down Exit that CK is maintained as a valid + * clock before issuing PDX. Specifies the clock stable time before PDX. R + * ecommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: 2 For c + * onfigurations with MEMC_FREQ_RATIO=2, program this to recommended value + * divided by two and round it up to next integer. This is only present for + * designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices. +*/ #undef DDRC_DRAMTMG7_T_CKPDX_DEFVAL #undef DDRC_DRAMTMG7_T_CKPDX_SHIFT #undef DDRC_DRAMTMG7_T_CKPDX_MASK -#define DDRC_DRAMTMG7_T_CKPDX_DEFVAL 0x00000202 -#define DDRC_DRAMTMG7_T_CKPDX_SHIFT 0 -#define DDRC_DRAMTMG7_T_CKPDX_MASK 0x0000000FU +#define DDRC_DRAMTMG7_T_CKPDX_DEFVAL 0x00000202 +#define DDRC_DRAMTMG7_T_CKPDX_SHIFT 0 +#define DDRC_DRAMTMG7_T_CKPDX_MASK 0x0000000FU -/*tXS_FAST: Exit Self Refresh to ZQCL, ZQCS and MRS (only CL, WR, RTP and Geardown mode). For configurations with MEMC_FREQ_RAT - O=2, program this to the above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: Thi - is applicable to only ZQCL/ZQCS commands. Note: Ensure this is less than or equal to t_xs_x32.*/ +/* +* tXS_FAST: Exit Self Refresh to ZQCL, ZQCS and MRS (only CL, WR, RTP and + * Geardown mode). For configurations with MEMC_FREQ_RATIO=2, program this + * to the above value divided by 2 and round up to next integer value. Unit + * : Multiples of 32 clocks. Note: This is applicable to only ZQCL/ZQCS com + * mands. Note: Ensure this is less than or equal to t_xs_x32. +*/ #undef DDRC_DRAMTMG8_T_XS_FAST_X32_DEFVAL #undef DDRC_DRAMTMG8_T_XS_FAST_X32_SHIFT #undef DDRC_DRAMTMG8_T_XS_FAST_X32_MASK -#define DDRC_DRAMTMG8_T_XS_FAST_X32_DEFVAL 0x03034405 -#define DDRC_DRAMTMG8_T_XS_FAST_X32_SHIFT 24 -#define DDRC_DRAMTMG8_T_XS_FAST_X32_MASK 0x7F000000U +#define DDRC_DRAMTMG8_T_XS_FAST_X32_DEFVAL 0x03034405 +#define DDRC_DRAMTMG8_T_XS_FAST_X32_SHIFT 24 +#define DDRC_DRAMTMG8_T_XS_FAST_X32_MASK 0x7F000000U -/*tXS_ABORT: Exit Self Refresh to commands not requiring a locked DLL in Self Refresh Abort. For configurations with MEMC_FREQ_ - ATIO=2, program this to the above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: - nsure this is less than or equal to t_xs_x32.*/ +/* +* tXS_ABORT: Exit Self Refresh to commands not requiring a locked DLL in S + * elf Refresh Abort. For configurations with MEMC_FREQ_RATIO=2, program th + * is to the above value divided by 2 and round up to next integer value. U + * nit: Multiples of 32 clocks. Note: Ensure this is less than or equal to + * t_xs_x32. +*/ #undef DDRC_DRAMTMG8_T_XS_ABORT_X32_DEFVAL #undef DDRC_DRAMTMG8_T_XS_ABORT_X32_SHIFT #undef DDRC_DRAMTMG8_T_XS_ABORT_X32_MASK -#define DDRC_DRAMTMG8_T_XS_ABORT_X32_DEFVAL 0x03034405 -#define DDRC_DRAMTMG8_T_XS_ABORT_X32_SHIFT 16 -#define DDRC_DRAMTMG8_T_XS_ABORT_X32_MASK 0x007F0000U +#define DDRC_DRAMTMG8_T_XS_ABORT_X32_DEFVAL 0x03034405 +#define DDRC_DRAMTMG8_T_XS_ABORT_X32_SHIFT 16 +#define DDRC_DRAMTMG8_T_XS_ABORT_X32_MASK 0x007F0000U -/*tXSDLL: Exit Self Refresh to commands requiring a locked DLL. For configurations with MEMC_FREQ_RATIO=2, program this to the - bove value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: Used only for DDR2, DDR3 and - DR4 SDRAMs.*/ +/* +* tXSDLL: Exit Self Refresh to commands requiring a locked DLL. For config + * urations with MEMC_FREQ_RATIO=2, program this to the above value divided + * by 2 and round up to next integer value. Unit: Multiples of 32 clocks. + * Note: Used only for DDR2, DDR3 and DDR4 SDRAMs. +*/ #undef DDRC_DRAMTMG8_T_XS_DLL_X32_DEFVAL #undef DDRC_DRAMTMG8_T_XS_DLL_X32_SHIFT #undef DDRC_DRAMTMG8_T_XS_DLL_X32_MASK -#define DDRC_DRAMTMG8_T_XS_DLL_X32_DEFVAL 0x03034405 -#define DDRC_DRAMTMG8_T_XS_DLL_X32_SHIFT 8 -#define DDRC_DRAMTMG8_T_XS_DLL_X32_MASK 0x00007F00U +#define DDRC_DRAMTMG8_T_XS_DLL_X32_DEFVAL 0x03034405 +#define DDRC_DRAMTMG8_T_XS_DLL_X32_SHIFT 8 +#define DDRC_DRAMTMG8_T_XS_DLL_X32_MASK 0x00007F00U -/*tXS: Exit Self Refresh to commands not requiring a locked DLL. For configurations with MEMC_FREQ_RATIO=2, program this to the - above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: Used only for DDR2, DDR3 and - DDR4 SDRAMs.*/ +/* +* tXS: Exit Self Refresh to commands not requiring a locked DLL. For confi + * gurations with MEMC_FREQ_RATIO=2, program this to the above value divide + * d by 2 and round up to next integer value. Unit: Multiples of 32 clocks. + * Note: Used only for DDR2, DDR3 and DDR4 SDRAMs. +*/ #undef DDRC_DRAMTMG8_T_XS_X32_DEFVAL #undef DDRC_DRAMTMG8_T_XS_X32_SHIFT #undef DDRC_DRAMTMG8_T_XS_X32_MASK -#define DDRC_DRAMTMG8_T_XS_X32_DEFVAL 0x03034405 -#define DDRC_DRAMTMG8_T_XS_X32_SHIFT 0 -#define DDRC_DRAMTMG8_T_XS_X32_MASK 0x0000007FU +#define DDRC_DRAMTMG8_T_XS_X32_DEFVAL 0x03034405 +#define DDRC_DRAMTMG8_T_XS_X32_SHIFT 0 +#define DDRC_DRAMTMG8_T_XS_X32_MASK 0x0000007FU -/*DDR4 Write preamble mode - 0: 1tCK preamble - 1: 2tCK preamble Present only with MEMC_FREQ_RATIO=2*/ +/* +* DDR4 Write preamble mode - 0: 1tCK preamble - 1: 2tCK preamble Present o + * nly with MEMC_FREQ_RATIO=2 +*/ #undef DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_DEFVAL #undef DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_SHIFT #undef DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_MASK -#define DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_DEFVAL 0x0004040D -#define DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_SHIFT 30 -#define DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_MASK 0x40000000U +#define DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_DEFVAL 0x0004040D +#define DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_SHIFT 30 +#define DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_MASK 0x40000000U -/*tCCD_S: This is the minimum time between two reads or two writes for different bank group. For bank switching (from bank 'a' - o bank 'b'), the minimum time is this value + 1. For configurations with MEMC_FREQ_RATIO=2, program this to (tCCD_S/2) and ro - nd it up to the next integer value. Present only in designs configured to support DDR4. Unit: clocks.*/ +/* +* tCCD_S: This is the minimum time between two reads or two writes for dif + * ferent bank group. For bank switching (from bank 'a' to bank 'b'), the m + * inimum time is this value + 1. For configurations with MEMC_FREQ_RATIO=2 + * , program this to (tCCD_S/2) and round it up to the next integer value. + * Present only in designs configured to support DDR4. Unit: clocks. +*/ #undef DDRC_DRAMTMG9_T_CCD_S_DEFVAL #undef DDRC_DRAMTMG9_T_CCD_S_SHIFT #undef DDRC_DRAMTMG9_T_CCD_S_MASK -#define DDRC_DRAMTMG9_T_CCD_S_DEFVAL 0x0004040D -#define DDRC_DRAMTMG9_T_CCD_S_SHIFT 16 -#define DDRC_DRAMTMG9_T_CCD_S_MASK 0x00070000U +#define DDRC_DRAMTMG9_T_CCD_S_DEFVAL 0x0004040D +#define DDRC_DRAMTMG9_T_CCD_S_SHIFT 16 +#define DDRC_DRAMTMG9_T_CCD_S_MASK 0x00070000U -/*tRRD_S: Minimum time between activates from bank 'a' to bank 'b' for different bank group. For configurations with MEMC_FREQ_ - ATIO=2, program this to (tRRD_S/2) and round it up to the next integer value. Present only in designs configured to support D - R4. Unit: Clocks.*/ +/* +* tRRD_S: Minimum time between activates from bank 'a' to bank 'b' for dif + * ferent bank group. For configurations with MEMC_FREQ_RATIO=2, program th + * is to (tRRD_S/2) and round it up to the next integer value. Present only + * in designs configured to support DDR4. Unit: Clocks. +*/ #undef DDRC_DRAMTMG9_T_RRD_S_DEFVAL #undef DDRC_DRAMTMG9_T_RRD_S_SHIFT #undef DDRC_DRAMTMG9_T_RRD_S_MASK -#define DDRC_DRAMTMG9_T_RRD_S_DEFVAL 0x0004040D -#define DDRC_DRAMTMG9_T_RRD_S_SHIFT 8 -#define DDRC_DRAMTMG9_T_RRD_S_MASK 0x00000F00U +#define DDRC_DRAMTMG9_T_RRD_S_DEFVAL 0x0004040D +#define DDRC_DRAMTMG9_T_RRD_S_SHIFT 8 +#define DDRC_DRAMTMG9_T_RRD_S_MASK 0x00000F00U -/*CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command for different bank group. Includes time for bus turn - round, recovery times, and all per-bank, per-rank, and global constraints. Present only in designs configured to support DDR4 - Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity latency - BL = burst length. This must match the value programm - d in the BL bit of the mode register to the SDRAM - tWTR_S = internal write to read command delay for different bank group. T - is comes directly from the SDRAM specification. For configurations with MEMC_FREQ_RATIO=2, divide the value calculated using - he above equation by 2, and round it up to next integer.*/ +/* +* CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command + * for different bank group. Includes time for bus turnaround, recovery ti + * mes, and all per-bank, per-rank, and global constraints. Present only in + * designs configured to support DDR4. Unit: Clocks. Where: - CWL = CAS wr + * ite latency - PL = Parity latency - BL = burst length. This must match t + * he value programmed in the BL bit of the mode register to the SDRAM - tW + * TR_S = internal write to read command delay for different bank group. Th + * is comes directly from the SDRAM specification. For configurations with + * MEMC_FREQ_RATIO=2, divide the value calculated using the above equation + * by 2, and round it up to next integer. +*/ #undef DDRC_DRAMTMG9_WR2RD_S_DEFVAL #undef DDRC_DRAMTMG9_WR2RD_S_SHIFT #undef DDRC_DRAMTMG9_WR2RD_S_MASK -#define DDRC_DRAMTMG9_WR2RD_S_DEFVAL 0x0004040D -#define DDRC_DRAMTMG9_WR2RD_S_SHIFT 0 -#define DDRC_DRAMTMG9_WR2RD_S_MASK 0x0000003FU +#define DDRC_DRAMTMG9_WR2RD_S_DEFVAL 0x0004040D +#define DDRC_DRAMTMG9_WR2RD_S_SHIFT 0 +#define DDRC_DRAMTMG9_WR2RD_S_MASK 0x0000003FU -/*tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DLL. For configurations with MEMC_FREQ_RATIO=2, program - this to (tXMPDLL/2) and round it up to the next integer value. Present only in designs configured to support DDR4. Unit: Mult - ples of 32 clocks.*/ +/* +* tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DL + * L. For configurations with MEMC_FREQ_RATIO=2, program this to (tXMPDLL/2 + * ) and round it up to the next integer value. Present only in designs con + * figured to support DDR4. Unit: Multiples of 32 clocks. +*/ #undef DDRC_DRAMTMG11_POST_MPSM_GAP_X32_DEFVAL #undef DDRC_DRAMTMG11_POST_MPSM_GAP_X32_SHIFT #undef DDRC_DRAMTMG11_POST_MPSM_GAP_X32_MASK -#define DDRC_DRAMTMG11_POST_MPSM_GAP_X32_DEFVAL 0x440C021C -#define DDRC_DRAMTMG11_POST_MPSM_GAP_X32_SHIFT 24 -#define DDRC_DRAMTMG11_POST_MPSM_GAP_X32_MASK 0x7F000000U +#define DDRC_DRAMTMG11_POST_MPSM_GAP_X32_DEFVAL 0x440C021C +#define DDRC_DRAMTMG11_POST_MPSM_GAP_X32_SHIFT 24 +#define DDRC_DRAMTMG11_POST_MPSM_GAP_X32_MASK 0x7F000000U -/*tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge. For configurations with MEMC_FREQ_RATIO=2, program this t - RoundUp(tMPX_LH/2)+1. Present only in designs configured to support DDR4. Unit: clocks.*/ +/* +* tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge. For + * configurations with MEMC_FREQ_RATIO=2, program this to RoundUp(tMPX_LH/2 + * )+1. Present only in designs configured to support DDR4. Unit: clocks. +*/ #undef DDRC_DRAMTMG11_T_MPX_LH_DEFVAL #undef DDRC_DRAMTMG11_T_MPX_LH_SHIFT #undef DDRC_DRAMTMG11_T_MPX_LH_MASK -#define DDRC_DRAMTMG11_T_MPX_LH_DEFVAL 0x440C021C -#define DDRC_DRAMTMG11_T_MPX_LH_SHIFT 16 -#define DDRC_DRAMTMG11_T_MPX_LH_MASK 0x001F0000U +#define DDRC_DRAMTMG11_T_MPX_LH_DEFVAL 0x440C021C +#define DDRC_DRAMTMG11_T_MPX_LH_SHIFT 16 +#define DDRC_DRAMTMG11_T_MPX_LH_MASK 0x001F0000U -/*tMPX_S: Minimum time CS setup time to CKE. For configurations with MEMC_FREQ_RATIO=2, program this to (tMPX_S/2) and round it - up to the next integer value. Present only in designs configured to support DDR4. Unit: Clocks.*/ +/* +* tMPX_S: Minimum time CS setup time to CKE. For configurations with MEMC_ + * FREQ_RATIO=2, program this to (tMPX_S/2) and round it up to the next int + * eger value. Present only in designs configured to support DDR4. Unit: Cl + * ocks. +*/ #undef DDRC_DRAMTMG11_T_MPX_S_DEFVAL #undef DDRC_DRAMTMG11_T_MPX_S_SHIFT #undef DDRC_DRAMTMG11_T_MPX_S_MASK -#define DDRC_DRAMTMG11_T_MPX_S_DEFVAL 0x440C021C -#define DDRC_DRAMTMG11_T_MPX_S_SHIFT 8 -#define DDRC_DRAMTMG11_T_MPX_S_MASK 0x00000300U +#define DDRC_DRAMTMG11_T_MPX_S_DEFVAL 0x440C021C +#define DDRC_DRAMTMG11_T_MPX_S_SHIFT 8 +#define DDRC_DRAMTMG11_T_MPX_S_MASK 0x00000300U -/*tCKMPE: Minimum valid clock requirement after MPSM entry. Present only in designs configured to support DDR4. Unit: Clocks. F - r configurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next i - teger.*/ +/* +* tCKMPE: Minimum valid clock requirement after MPSM entry. Present only i + * n designs configured to support DDR4. Unit: Clocks. For configurations w + * ith MEMC_FREQ_RATIO=2, divide the value calculated using the above equat + * ion by 2, and round it up to next integer. +*/ #undef DDRC_DRAMTMG11_T_CKMPE_DEFVAL #undef DDRC_DRAMTMG11_T_CKMPE_SHIFT #undef DDRC_DRAMTMG11_T_CKMPE_MASK -#define DDRC_DRAMTMG11_T_CKMPE_DEFVAL 0x440C021C -#define DDRC_DRAMTMG11_T_CKMPE_SHIFT 0 -#define DDRC_DRAMTMG11_T_CKMPE_MASK 0x0000001FU +#define DDRC_DRAMTMG11_T_CKMPE_DEFVAL 0x440C021C +#define DDRC_DRAMTMG11_T_CKMPE_SHIFT 0 +#define DDRC_DRAMTMG11_T_CKMPE_MASK 0x0000001FU -/*tCMDCKE: Delay from valid command to CKE input LOW. Set this to the larger of tESCKE or tCMDCKE For configurations with MEMC_ - REQ_RATIO=2, program this to (max(tESCKE, tCMDCKE)/2) and round it up to next integer value.*/ +/* +* tCMDCKE: Delay from valid command to CKE input LOW. Set this to the larg + * er of tESCKE or tCMDCKE For configurations with MEMC_FREQ_RATIO=2, progr + * am this to (max(tESCKE, tCMDCKE)/2) and round it up to next integer valu + * e. +*/ #undef DDRC_DRAMTMG12_T_CMDCKE_DEFVAL #undef DDRC_DRAMTMG12_T_CMDCKE_SHIFT #undef DDRC_DRAMTMG12_T_CMDCKE_MASK -#define DDRC_DRAMTMG12_T_CMDCKE_DEFVAL 0x00020610 -#define DDRC_DRAMTMG12_T_CMDCKE_SHIFT 16 -#define DDRC_DRAMTMG12_T_CMDCKE_MASK 0x00030000U +#define DDRC_DRAMTMG12_T_CMDCKE_DEFVAL 0x00020610 +#define DDRC_DRAMTMG12_T_CMDCKE_SHIFT 16 +#define DDRC_DRAMTMG12_T_CMDCKE_MASK 0x00030000U -/*tCKEHCMD: Valid command requirement after CKE input HIGH. For configurations with MEMC_FREQ_RATIO=2, program this to (tCKEHCM - /2) and round it up to next integer value.*/ +/* +* tCKEHCMD: Valid command requirement after CKE input HIGH. For configurat + * ions with MEMC_FREQ_RATIO=2, program this to (tCKEHCMD/2) and round it u + * p to next integer value. +*/ #undef DDRC_DRAMTMG12_T_CKEHCMD_DEFVAL #undef DDRC_DRAMTMG12_T_CKEHCMD_SHIFT #undef DDRC_DRAMTMG12_T_CKEHCMD_MASK -#define DDRC_DRAMTMG12_T_CKEHCMD_DEFVAL 0x00020610 -#define DDRC_DRAMTMG12_T_CKEHCMD_SHIFT 8 -#define DDRC_DRAMTMG12_T_CKEHCMD_MASK 0x00000F00U +#define DDRC_DRAMTMG12_T_CKEHCMD_DEFVAL 0x00020610 +#define DDRC_DRAMTMG12_T_CKEHCMD_SHIFT 8 +#define DDRC_DRAMTMG12_T_CKEHCMD_MASK 0x00000F00U -/*tMRD_PDA: This is the Mode Register Set command cycle time in PDA mode. For configurations with MEMC_FREQ_RATIO=2, program th - s to (tMRD_PDA/2) and round it up to next integer value.*/ +/* +* tMRD_PDA: This is the Mode Register Set command cycle time in PDA mode. + * For configurations with MEMC_FREQ_RATIO=2, program this to (tMRD_PDA/2) + * and round it up to next integer value. +*/ #undef DDRC_DRAMTMG12_T_MRD_PDA_DEFVAL #undef DDRC_DRAMTMG12_T_MRD_PDA_SHIFT #undef DDRC_DRAMTMG12_T_MRD_PDA_MASK -#define DDRC_DRAMTMG12_T_MRD_PDA_DEFVAL 0x00020610 -#define DDRC_DRAMTMG12_T_MRD_PDA_SHIFT 0 -#define DDRC_DRAMTMG12_T_MRD_PDA_MASK 0x0000001FU +#define DDRC_DRAMTMG12_T_MRD_PDA_DEFVAL 0x00020610 +#define DDRC_DRAMTMG12_T_MRD_PDA_SHIFT 0 +#define DDRC_DRAMTMG12_T_MRD_PDA_MASK 0x0000001FU -/*- 1 - Disable uMCTL2 generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used instead to is - ue ZQ calibration request from APB module. - 0 - Internally generate ZQCS/MPC(ZQ calibration) commands based on ZQCTL1.t_zq_s - ort_interval_x1024. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.*/ +/* +* - 1 - Disable uMCTL2 generation of ZQCS/MPC(ZQ calibration) command. Reg + * ister DBGCMD.zq_calib_short can be used instead to issue ZQ calibration + * request from APB module. - 0 - Internally generate ZQCS/MPC(ZQ calibrati + * on) commands based on ZQCTL1.t_zq_short_interval_x1024. This is only pre + * sent for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. +*/ #undef DDRC_ZQCTL0_DIS_AUTO_ZQ_DEFVAL #undef DDRC_ZQCTL0_DIS_AUTO_ZQ_SHIFT #undef DDRC_ZQCTL0_DIS_AUTO_ZQ_MASK -#define DDRC_ZQCTL0_DIS_AUTO_ZQ_DEFVAL 0x02000040 -#define DDRC_ZQCTL0_DIS_AUTO_ZQ_SHIFT 31 -#define DDRC_ZQCTL0_DIS_AUTO_ZQ_MASK 0x80000000U +#define DDRC_ZQCTL0_DIS_AUTO_ZQ_DEFVAL 0x02000040 +#define DDRC_ZQCTL0_DIS_AUTO_ZQ_SHIFT 31 +#define DDRC_ZQCTL0_DIS_AUTO_ZQ_MASK 0x80000000U -/*- 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable when run in DDR3 - or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. - 0 - Enable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Power - own exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. This is only present for designs suppo - ting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.*/ +/* +* - 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refres + * h/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 + * or LPDDR3 or LPDDR4 mode. - 0 - Enable issuing of ZQCL/MPC(ZQ calibratio + * n) command at Self-Refresh/SR-Powerdown exit. Only applicable when run i + * n DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. This is only present + * for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. +*/ #undef DDRC_ZQCTL0_DIS_SRX_ZQCL_DEFVAL #undef DDRC_ZQCTL0_DIS_SRX_ZQCL_SHIFT #undef DDRC_ZQCTL0_DIS_SRX_ZQCL_MASK -#define DDRC_ZQCTL0_DIS_SRX_ZQCL_DEFVAL 0x02000040 -#define DDRC_ZQCTL0_DIS_SRX_ZQCL_SHIFT 30 -#define DDRC_ZQCTL0_DIS_SRX_ZQCL_MASK 0x40000000U +#define DDRC_ZQCTL0_DIS_SRX_ZQCL_DEFVAL 0x02000040 +#define DDRC_ZQCTL0_DIS_SRX_ZQCL_SHIFT 30 +#define DDRC_ZQCTL0_DIS_SRX_ZQCL_MASK 0x40000000U -/*- 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are sent to one r - nk at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to different ranks do not ov - rlap. - 0 - ZQ resistor is not shared. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.*/ +/* +* - 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQC + * L/ZQCS/MPC(ZQ calibration) commands are sent to one rank at a time with + * tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that co + * mmands to different ranks do not overlap. - 0 - ZQ resistor is not share + * d. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR + * 3/LPDDR4 devices. +*/ #undef DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_DEFVAL #undef DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_SHIFT #undef DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_MASK -#define DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_DEFVAL 0x02000040 -#define DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_SHIFT 29 -#define DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_MASK 0x20000000U +#define DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_DEFVAL 0x02000040 +#define DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_SHIFT 29 +#define DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_MASK 0x20000000U -/*- 1 - Disable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode. - 0 - Enable - ssuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode. This is only present for des - gns supporting DDR4 devices.*/ +/* +* - 1 - Disable issuing of ZQCL command at Maximum Power Saving Mode exit. + * Only applicable when run in DDR4 mode. - 0 - Enable issuing of ZQCL com + * mand at Maximum Power Saving Mode exit. Only applicable when run in DDR4 + * mode. This is only present for designs supporting DDR4 devices. +*/ #undef DDRC_ZQCTL0_DIS_MPSMX_ZQCL_DEFVAL #undef DDRC_ZQCTL0_DIS_MPSMX_ZQCL_SHIFT #undef DDRC_ZQCTL0_DIS_MPSMX_ZQCL_MASK -#define DDRC_ZQCTL0_DIS_MPSMX_ZQCL_DEFVAL 0x02000040 -#define DDRC_ZQCTL0_DIS_MPSMX_ZQCL_SHIFT 28 -#define DDRC_ZQCTL0_DIS_MPSMX_ZQCL_MASK 0x10000000U +#define DDRC_ZQCTL0_DIS_MPSMX_ZQCL_DEFVAL 0x02000040 +#define DDRC_ZQCTL0_DIS_MPSMX_ZQCL_SHIFT 28 +#define DDRC_ZQCTL0_DIS_MPSMX_ZQCL_MASK 0x10000000U -/*tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Number of cycles of NOP required after a ZQCL (ZQ calibrat - on long)/MPC(ZQ Start) command is issued to SDRAM. For configurations with MEMC_FREQ_RATIO=2: DDR3/DDR4: program this to tZQo - er/2 and round it up to the next integer value. LPDDR2/LPDDR3: program this to tZQCL/2 and round it up to the next integer va - ue. LPDDR4: program this to tZQCAL/2 and round it up to the next integer value. Unit: Clock cycles. This is only present for - esigns supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.*/ +/* +* tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Numbe + * r of cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ St + * art) command is issued to SDRAM. For configurations with MEMC_FREQ_RATIO + * =2: DDR3/DDR4: program this to tZQoper/2 and round it up to the next int + * eger value. LPDDR2/LPDDR3: program this to tZQCL/2 and round it up to th + * e next integer value. LPDDR4: program this to tZQCAL/2 and round it up t + * o the next integer value. Unit: Clock cycles. This is only present for d + * esigns supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. +*/ #undef DDRC_ZQCTL0_T_ZQ_LONG_NOP_DEFVAL #undef DDRC_ZQCTL0_T_ZQ_LONG_NOP_SHIFT #undef DDRC_ZQCTL0_T_ZQ_LONG_NOP_MASK -#define DDRC_ZQCTL0_T_ZQ_LONG_NOP_DEFVAL 0x02000040 -#define DDRC_ZQCTL0_T_ZQ_LONG_NOP_SHIFT 16 -#define DDRC_ZQCTL0_T_ZQ_LONG_NOP_MASK 0x07FF0000U +#define DDRC_ZQCTL0_T_ZQ_LONG_NOP_DEFVAL 0x02000040 +#define DDRC_ZQCTL0_T_ZQ_LONG_NOP_SHIFT 16 +#define DDRC_ZQCTL0_T_ZQ_LONG_NOP_MASK 0x07FF0000U -/*tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of cycles of NOP required after a ZQCS (ZQ calibration short)/MPC - ZQ Latch) command is issued to SDRAM. For configurations with MEMC_FREQ_RATIO=2, program this to tZQCS/2 and round it up to t - e next integer value. Unit: Clock cycles. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devic - s.*/ +/* +* tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of cycles of + * NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command + * is issued to SDRAM. For configurations with MEMC_FREQ_RATIO=2, program t + * his to tZQCS/2 and round it up to the next integer value. Unit: Clock cy + * cles. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LP + * DDR3/LPDDR4 devices. +*/ #undef DDRC_ZQCTL0_T_ZQ_SHORT_NOP_DEFVAL #undef DDRC_ZQCTL0_T_ZQ_SHORT_NOP_SHIFT #undef DDRC_ZQCTL0_T_ZQ_SHORT_NOP_MASK -#define DDRC_ZQCTL0_T_ZQ_SHORT_NOP_DEFVAL 0x02000040 -#define DDRC_ZQCTL0_T_ZQ_SHORT_NOP_SHIFT 0 -#define DDRC_ZQCTL0_T_ZQ_SHORT_NOP_MASK 0x000003FFU +#define DDRC_ZQCTL0_T_ZQ_SHORT_NOP_DEFVAL 0x02000040 +#define DDRC_ZQCTL0_T_ZQ_SHORT_NOP_SHIFT 0 +#define DDRC_ZQCTL0_T_ZQ_SHORT_NOP_MASK 0x000003FFU -/*tZQReset: Number of cycles of NOP required after a ZQReset (ZQ calibration Reset) command is issued to SDRAM. For configurati - ns with MEMC_FREQ_RATIO=2, program this to tZQReset/2 and round it up to the next integer value. Unit: Clock cycles. This is - nly present for designs supporting LPDDR2/LPDDR3/LPDDR4 devices.*/ +/* +* tZQReset: Number of cycles of NOP required after a ZQReset (ZQ calibrati + * on Reset) command is issued to SDRAM. For configurations with MEMC_FREQ_ + * RATIO=2, program this to tZQReset/2 and round it up to the next integer + * value. Unit: Clock cycles. This is only present for designs supporting L + * PDDR2/LPDDR3/LPDDR4 devices. +*/ #undef DDRC_ZQCTL1_T_ZQ_RESET_NOP_DEFVAL #undef DDRC_ZQCTL1_T_ZQ_RESET_NOP_SHIFT #undef DDRC_ZQCTL1_T_ZQ_RESET_NOP_MASK -#define DDRC_ZQCTL1_T_ZQ_RESET_NOP_DEFVAL 0x02000100 -#define DDRC_ZQCTL1_T_ZQ_RESET_NOP_SHIFT 20 -#define DDRC_ZQCTL1_T_ZQ_RESET_NOP_MASK 0x3FF00000U +#define DDRC_ZQCTL1_T_ZQ_RESET_NOP_DEFVAL 0x02000100 +#define DDRC_ZQCTL1_T_ZQ_RESET_NOP_SHIFT 20 +#define DDRC_ZQCTL1_T_ZQ_RESET_NOP_MASK 0x3FF00000U -/*Average interval to wait between automatically issuing ZQCS (ZQ calibration short)/MPC(ZQ calibration) commands to DDR3/DDR4/ - PDDR2/LPDDR3/LPDDR4 devices. Meaningless, if ZQCTL0.dis_auto_zq=1. Unit: 1024 clock cycles. This is only present for designs - upporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.*/ +/* +* Average interval to wait between automatically issuing ZQCS (ZQ calibrat + * ion short)/MPC(ZQ calibration) commands to DDR3/DDR4/LPDDR2/LPDDR3/LPDDR + * 4 devices. Meaningless, if ZQCTL0.dis_auto_zq=1. Unit: 1024 clock cycles + * . This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3 + * /LPDDR4 devices. +*/ #undef DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_DEFVAL #undef DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_SHIFT #undef DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_MASK -#define DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_DEFVAL 0x02000100 -#define DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_SHIFT 0 -#define DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_MASK 0x000FFFFFU +#define DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_DEFVAL 0x02000100 +#define DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_SHIFT 0 +#define DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_MASK 0x000FFFFFU -/*Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signa - s at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligne - , this timing parameter should be rounded up to the next integer value. Note that if using RDIMM, it is necessary to incremen - this parameter by RDIMM's extra cycle of latency in terms of DFI clock.*/ +/* +* Specifies the number of DFI clock cycles after an assertion or de-assert + * ion of the DFI control signals that the control signals at the PHY-DRAM + * interface reflect the assertion or de-assertion. If the DFI clock and th + * e memory clock are not phase-aligned, this timing parameter should be ro + * unded up to the next integer value. Note that if using RDIMM, it is nece + * ssary to increment this parameter by RDIMM's extra cycle of latency in t + * erms of DFI clock. +*/ #undef DDRC_DFITMG0_DFI_T_CTRL_DELAY_DEFVAL #undef DDRC_DFITMG0_DFI_T_CTRL_DELAY_SHIFT #undef DDRC_DFITMG0_DFI_T_CTRL_DELAY_MASK -#define DDRC_DFITMG0_DFI_T_CTRL_DELAY_DEFVAL 0x07020002 -#define DDRC_DFITMG0_DFI_T_CTRL_DELAY_SHIFT 24 -#define DDRC_DFITMG0_DFI_T_CTRL_DELAY_MASK 0x1F000000U +#define DDRC_DFITMG0_DFI_T_CTRL_DELAY_DEFVAL 0x07020002 +#define DDRC_DFITMG0_DFI_T_CTRL_DELAY_SHIFT 24 +#define DDRC_DFITMG0_DFI_T_CTRL_DELAY_MASK 0x1F000000U -/*Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR or SDR values Selects whether value in DFITM - 0.dfi_t_rddata_en is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles R - fer to PHY specification for correct value.*/ +/* +* Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated u + * sing HDR or SDR values Selects whether value in DFITMG0.dfi_t_rddata_en + * is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles + * - 1 in terms of SDR clock cycles Refer to PHY specification for correct + * value. +*/ #undef DDRC_DFITMG0_DFI_RDDATA_USE_SDR_DEFVAL #undef DDRC_DFITMG0_DFI_RDDATA_USE_SDR_SHIFT #undef DDRC_DFITMG0_DFI_RDDATA_USE_SDR_MASK -#define DDRC_DFITMG0_DFI_RDDATA_USE_SDR_DEFVAL 0x07020002 -#define DDRC_DFITMG0_DFI_RDDATA_USE_SDR_SHIFT 23 -#define DDRC_DFITMG0_DFI_RDDATA_USE_SDR_MASK 0x00800000U +#define DDRC_DFITMG0_DFI_RDDATA_USE_SDR_DEFVAL 0x07020002 +#define DDRC_DFITMG0_DFI_RDDATA_USE_SDR_SHIFT 23 +#define DDRC_DFITMG0_DFI_RDDATA_USE_SDR_MASK 0x00800000U -/*Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. Refer to PHY spe - ification for correct value. This corresponds to the DFI parameter trddata_en. Note that, depending on the PHY, if using RDIM - , it may be necessary to use the value (CL + 1) in the calculation of trddata_en. This is to compensate for the extra cycle o - latency through the RDIMM. Unit: Clocks*/ +/* +* Time from the assertion of a read command on the DFI interface to the as + * sertion of the dfi_rddata_en signal. Refer to PHY specification for corr + * ect value. This corresponds to the DFI parameter trddata_en. Note that, + * depending on the PHY, if using RDIMM, it may be necessary to use the val + * ue (CL + 1) in the calculation of trddata_en. This is to compensate for + * the extra cycle of latency through the RDIMM. Unit: Clocks +*/ #undef DDRC_DFITMG0_DFI_T_RDDATA_EN_DEFVAL #undef DDRC_DFITMG0_DFI_T_RDDATA_EN_SHIFT #undef DDRC_DFITMG0_DFI_T_RDDATA_EN_MASK -#define DDRC_DFITMG0_DFI_T_RDDATA_EN_DEFVAL 0x07020002 -#define DDRC_DFITMG0_DFI_T_RDDATA_EN_SHIFT 16 -#define DDRC_DFITMG0_DFI_T_RDDATA_EN_MASK 0x003F0000U +#define DDRC_DFITMG0_DFI_T_RDDATA_EN_DEFVAL 0x07020002 +#define DDRC_DFITMG0_DFI_T_RDDATA_EN_SHIFT 16 +#define DDRC_DFITMG0_DFI_T_RDDATA_EN_MASK 0x003F0000U -/*Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using HDR or SDR values Selects whether value in DFITMG - .dfi_tphy_wrlat is in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.dfi_tphy_wrdata is in terms of SDR or - HDR clock cycles - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles Refer to PHY specification for correct val - e.*/ +/* +* Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated us + * ing HDR or SDR values Selects whether value in DFITMG0.dfi_tphy_wrlat is + * in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.df + * i_tphy_wrdata is in terms of SDR or HDR clock cycles - 0 in terms of HDR + * clock cycles - 1 in terms of SDR clock cycles Refer to PHY specificatio + * n for correct value. +*/ #undef DDRC_DFITMG0_DFI_WRDATA_USE_SDR_DEFVAL #undef DDRC_DFITMG0_DFI_WRDATA_USE_SDR_SHIFT #undef DDRC_DFITMG0_DFI_WRDATA_USE_SDR_MASK -#define DDRC_DFITMG0_DFI_WRDATA_USE_SDR_DEFVAL 0x07020002 -#define DDRC_DFITMG0_DFI_WRDATA_USE_SDR_SHIFT 15 -#define DDRC_DFITMG0_DFI_WRDATA_USE_SDR_MASK 0x00008000U +#define DDRC_DFITMG0_DFI_WRDATA_USE_SDR_DEFVAL 0x07020002 +#define DDRC_DFITMG0_DFI_WRDATA_USE_SDR_SHIFT 15 +#define DDRC_DFITMG0_DFI_WRDATA_USE_SDR_MASK 0x00008000U -/*Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on th - dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. N - te, max supported value is 8. Unit: Clocks*/ +/* +* Specifies the number of clock cycles between when dfi_wrdata_en is asser + * ted to when the associated write data is driven on the dfi_wrdata signal + * . This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY + * specification for correct value. Note, max supported value is 8. Unit: + * Clocks +*/ #undef DDRC_DFITMG0_DFI_TPHY_WRDATA_DEFVAL #undef DDRC_DFITMG0_DFI_TPHY_WRDATA_SHIFT #undef DDRC_DFITMG0_DFI_TPHY_WRDATA_MASK -#define DDRC_DFITMG0_DFI_TPHY_WRDATA_DEFVAL 0x07020002 -#define DDRC_DFITMG0_DFI_TPHY_WRDATA_SHIFT 8 -#define DDRC_DFITMG0_DFI_TPHY_WRDATA_MASK 0x00003F00U +#define DDRC_DFITMG0_DFI_TPHY_WRDATA_DEFVAL 0x07020002 +#define DDRC_DFITMG0_DFI_TPHY_WRDATA_SHIFT 8 +#define DDRC_DFITMG0_DFI_TPHY_WRDATA_MASK 0x00003F00U -/*Write latency Number of clocks from the write command to write data enable (dfi_wrdata_en). This corresponds to the DFI timin - parameter tphy_wrlat. Refer to PHY specification for correct value.Note that, depending on the PHY, if using RDIMM, it may b - necessary to use the value (CL + 1) in the calculation of tphy_wrlat. This is to compensate for the extra cycle of latency t - rough the RDIMM.*/ +/* +* Write latency Number of clocks from the write command to write data enab + * le (dfi_wrdata_en). This corresponds to the DFI timing parameter tphy_wr + * lat. Refer to PHY specification for correct value.Note that, depending o + * n the PHY, if using RDIMM, it may be necessary to use the value (CL + 1) + * in the calculation of tphy_wrlat. This is to compensate for the extra c + * ycle of latency through the RDIMM. +*/ #undef DDRC_DFITMG0_DFI_TPHY_WRLAT_DEFVAL #undef DDRC_DFITMG0_DFI_TPHY_WRLAT_SHIFT #undef DDRC_DFITMG0_DFI_TPHY_WRLAT_MASK -#define DDRC_DFITMG0_DFI_TPHY_WRLAT_DEFVAL 0x07020002 -#define DDRC_DFITMG0_DFI_TPHY_WRLAT_SHIFT 0 -#define DDRC_DFITMG0_DFI_TPHY_WRLAT_MASK 0x0000003FU +#define DDRC_DFITMG0_DFI_TPHY_WRLAT_DEFVAL 0x07020002 +#define DDRC_DFITMG0_DFI_TPHY_WRLAT_SHIFT 0 +#define DDRC_DFITMG0_DFI_TPHY_WRLAT_MASK 0x0000003FU -/*Specifies the number of DFI PHY clocks between when the dfi_cs signal is asserted and when the associated command is driven. - his field is used for CAL mode, should be set to '0' or the value which matches the CAL mode register setting in the DRAM. If - the PHY can add the latency for CAL mode, this should be set to '0'. Valid Range: 0, 3, 4, 5, 6, and 8*/ +/* +* Specifies the number of DFI PHY clocks between when the dfi_cs signal is + * asserted and when the associated command is driven. This field is used + * for CAL mode, should be set to '0' or the value which matches the CAL mo + * de register setting in the DRAM. If the PHY can add the latency for CAL + * mode, this should be set to '0'. Valid Range: 0, 3, 4, 5, 6, and 8 +*/ #undef DDRC_DFITMG1_DFI_T_CMD_LAT_DEFVAL #undef DDRC_DFITMG1_DFI_T_CMD_LAT_SHIFT #undef DDRC_DFITMG1_DFI_T_CMD_LAT_MASK -#define DDRC_DFITMG1_DFI_T_CMD_LAT_DEFVAL 0x00000404 -#define DDRC_DFITMG1_DFI_T_CMD_LAT_SHIFT 28 -#define DDRC_DFITMG1_DFI_T_CMD_LAT_MASK 0xF0000000U +#define DDRC_DFITMG1_DFI_T_CMD_LAT_DEFVAL 0x00000404 +#define DDRC_DFITMG1_DFI_T_CMD_LAT_SHIFT 28 +#define DDRC_DFITMG1_DFI_T_CMD_LAT_MASK 0xF0000000U -/*Specifies the number of DFI PHY clocks between when the dfi_cs signal is asserted and when the associated dfi_parity_in signa - is driven.*/ +/* +* Specifies the number of DFI PHY clocks between when the dfi_cs signal is + * asserted and when the associated dfi_parity_in signal is driven. +*/ #undef DDRC_DFITMG1_DFI_T_PARIN_LAT_DEFVAL #undef DDRC_DFITMG1_DFI_T_PARIN_LAT_SHIFT #undef DDRC_DFITMG1_DFI_T_PARIN_LAT_MASK -#define DDRC_DFITMG1_DFI_T_PARIN_LAT_DEFVAL 0x00000404 -#define DDRC_DFITMG1_DFI_T_PARIN_LAT_SHIFT 24 -#define DDRC_DFITMG1_DFI_T_PARIN_LAT_MASK 0x03000000U +#define DDRC_DFITMG1_DFI_T_PARIN_LAT_DEFVAL 0x00000404 +#define DDRC_DFITMG1_DFI_T_PARIN_LAT_SHIFT 24 +#define DDRC_DFITMG1_DFI_T_PARIN_LAT_MASK 0x03000000U -/*Specifies the number of DFI clocks between when the dfi_wrdata_en signal is asserted and when the corresponding write data tr - nsfer is completed on the DRAM bus. This corresponds to the DFI timing parameter twrdata_delay. Refer to PHY specification fo - correct value. For DFI 3.0 PHY, set to twrdata_delay, a new timing parameter introduced in DFI 3.0. For DFI 2.1 PHY, set to - phy_wrdata + (delay of DFI write data to the DRAM). Value to be programmed is in terms of DFI clocks, not PHY clocks. In FREQ - RATIO=2, divide PHY's value by 2 and round up to next integer. If using DFITMG0.dfi_wrdata_use_sdr=1, add 1 to the value. Uni - : Clocks*/ +/* +* Specifies the number of DFI clocks between when the dfi_wrdata_en signal + * is asserted and when the corresponding write data transfer is completed + * on the DRAM bus. This corresponds to the DFI timing parameter twrdata_d + * elay. Refer to PHY specification for correct value. For DFI 3.0 PHY, set + * to twrdata_delay, a new timing parameter introduced in DFI 3.0. For DFI + * 2.1 PHY, set to tphy_wrdata + (delay of DFI write data to the DRAM). Va + * lue to be programmed is in terms of DFI clocks, not PHY clocks. In FREQ_ + * RATIO=2, divide PHY's value by 2 and round up to next integer. If using + * DFITMG0.dfi_wrdata_use_sdr=1, add 1 to the value. Unit: Clocks +*/ #undef DDRC_DFITMG1_DFI_T_WRDATA_DELAY_DEFVAL #undef DDRC_DFITMG1_DFI_T_WRDATA_DELAY_SHIFT #undef DDRC_DFITMG1_DFI_T_WRDATA_DELAY_MASK -#define DDRC_DFITMG1_DFI_T_WRDATA_DELAY_DEFVAL 0x00000404 -#define DDRC_DFITMG1_DFI_T_WRDATA_DELAY_SHIFT 16 -#define DDRC_DFITMG1_DFI_T_WRDATA_DELAY_MASK 0x001F0000U +#define DDRC_DFITMG1_DFI_T_WRDATA_DELAY_DEFVAL 0x00000404 +#define DDRC_DFITMG1_DFI_T_WRDATA_DELAY_SHIFT 16 +#define DDRC_DFITMG1_DFI_T_WRDATA_DELAY_MASK 0x001F0000U -/*Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to - he DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase - ligned, this timing parameter should be rounded up to the next integer value.*/ +/* +* Specifies the number of DFI clock cycles from the assertion of the dfi_d + * ram_clk_disable signal on the DFI until the clock to the DRAM memory dev + * ices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock + * and the memory clock are not phase aligned, this timing parameter should + * be rounded up to the next integer value. +*/ #undef DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_DEFVAL #undef DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_SHIFT #undef DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_MASK -#define DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_DEFVAL 0x00000404 -#define DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_SHIFT 8 -#define DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_MASK 0x00000F00U +#define DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_DEFVAL 0x00000404 +#define DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_SHIFT 8 +#define DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_MASK 0x00000F00U -/*Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first - alid rising edge of the clock to the DRAM memory devices, at the PHY-DRAM boundary. If the DFI clock and the memory clock are - not phase aligned, this timing parameter should be rounded up to the next integer value.*/ +/* +* Specifies the number of DFI clock cycles from the de-assertion of the df + * i_dram_clk_disable signal on the DFI until the first valid rising edge o + * f the clock to the DRAM memory devices, at the PHY-DRAM boundary. If the + * DFI clock and the memory clock are not phase aligned, this timing param + * eter should be rounded up to the next integer value. +*/ #undef DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_DEFVAL #undef DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_SHIFT #undef DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_MASK -#define DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_DEFVAL 0x00000404 -#define DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_SHIFT 0 -#define DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_MASK 0x0000000FU +#define DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_DEFVAL 0x00000404 +#define DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_SHIFT 0 +#define DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_MASK 0x0000000FU -/*Setting for DFI's tlp_resp time. Same value is used for both Power Down, Self Refresh, Deep Power Down and Maximum Power Savi - g modes. DFI 2.1 specification onwards, recommends using a fixed value of 7 always.*/ +/* +* Setting for DFI's tlp_resp time. Same value is used for both Power Down, + * Self Refresh, Deep Power Down and Maximum Power Saving modes. DFI 2.1 s + * pecification onwards, recommends using a fixed value of 7 always. +*/ #undef DDRC_DFILPCFG0_DFI_TLP_RESP_DEFVAL #undef DDRC_DFILPCFG0_DFI_TLP_RESP_SHIFT #undef DDRC_DFILPCFG0_DFI_TLP_RESP_MASK -#define DDRC_DFILPCFG0_DFI_TLP_RESP_DEFVAL 0x07000000 -#define DDRC_DFILPCFG0_DFI_TLP_RESP_SHIFT 24 -#define DDRC_DFILPCFG0_DFI_TLP_RESP_MASK 0x0F000000U +#define DDRC_DFILPCFG0_DFI_TLP_RESP_DEFVAL 0x07000000 +#define DDRC_DFILPCFG0_DFI_TLP_RESP_SHIFT 24 +#define DDRC_DFILPCFG0_DFI_TLP_RESP_MASK 0x0F000000U -/*Value to drive on dfi_lp_wakeup signal when Deep Power Down mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 - cycles - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles - 0x7 - - 2048 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0xD - - 31072 cycles - 0xE - 262144 cycles - 0xF - Unlimited This is only present for designs supporting mDDR or LPDDR2/LPDDR3 device - .*/ +/* +* Value to drive on dfi_lp_wakeup signal when Deep Power Down mode is ente + * red. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32 + * cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 5 + * 12 cycles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycles - + * 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 6553 + * 6 cycles - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited T + * his is only present for designs supporting mDDR or LPDDR2/LPDDR3 devices + * . +*/ #undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_DEFVAL #undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_SHIFT #undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_MASK -#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_DEFVAL 0x07000000 -#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_SHIFT 20 -#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_MASK 0x00F00000U +#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_DEFVAL 0x07000000 +#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_SHIFT 20 +#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_MASK 0x00F00000U -/*Enables DFI Low Power interface handshaking during Deep Power Down Entry/Exit. - 0 - Disabled - 1 - Enabled This is only pres - nt for designs supporting mDDR or LPDDR2/LPDDR3 devices.*/ +/* +* Enables DFI Low Power interface handshaking during Deep Power Down Entry + * /Exit. - 0 - Disabled - 1 - Enabled This is only present for designs sup + * porting mDDR or LPDDR2/LPDDR3 devices. +*/ #undef DDRC_DFILPCFG0_DFI_LP_EN_DPD_DEFVAL #undef DDRC_DFILPCFG0_DFI_LP_EN_DPD_SHIFT #undef DDRC_DFILPCFG0_DFI_LP_EN_DPD_MASK -#define DDRC_DFILPCFG0_DFI_LP_EN_DPD_DEFVAL 0x07000000 -#define DDRC_DFILPCFG0_DFI_LP_EN_DPD_SHIFT 16 -#define DDRC_DFILPCFG0_DFI_LP_EN_DPD_MASK 0x00010000U +#define DDRC_DFILPCFG0_DFI_LP_EN_DPD_DEFVAL 0x07000000 +#define DDRC_DFILPCFG0_DFI_LP_EN_DPD_SHIFT 16 +#define DDRC_DFILPCFG0_DFI_LP_EN_DPD_MASK 0x00010000U -/*Value to drive on dfi_lp_wakeup signal when Self Refresh mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cy - les - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles - 0x7 - - 048 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0xD - 131 - 72 cycles - 0xE - 262144 cycles - 0xF - Unlimited*/ +/* +* Value to drive on dfi_lp_wakeup signal when Self Refresh mode is entered + * . Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32 cyc + * les - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 + * cycles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycles - 0x9 + * - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 c + * ycles - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited +*/ #undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_DEFVAL #undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_SHIFT #undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_MASK -#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_DEFVAL 0x07000000 -#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_SHIFT 12 -#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_MASK 0x0000F000U +#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_DEFVAL 0x07000000 +#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_SHIFT 12 +#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_MASK 0x0000F000U -/*Enables DFI Low Power interface handshaking during Self Refresh Entry/Exit. - 0 - Disabled - 1 - Enabled*/ +/* +* Enables DFI Low Power interface handshaking during Self Refresh Entry/Ex + * it. - 0 - Disabled - 1 - Enabled +*/ #undef DDRC_DFILPCFG0_DFI_LP_EN_SR_DEFVAL #undef DDRC_DFILPCFG0_DFI_LP_EN_SR_SHIFT #undef DDRC_DFILPCFG0_DFI_LP_EN_SR_MASK -#define DDRC_DFILPCFG0_DFI_LP_EN_SR_DEFVAL 0x07000000 -#define DDRC_DFILPCFG0_DFI_LP_EN_SR_SHIFT 8 -#define DDRC_DFILPCFG0_DFI_LP_EN_SR_MASK 0x00000100U +#define DDRC_DFILPCFG0_DFI_LP_EN_SR_DEFVAL 0x07000000 +#define DDRC_DFILPCFG0_DFI_LP_EN_SR_SHIFT 8 +#define DDRC_DFILPCFG0_DFI_LP_EN_SR_MASK 0x00000100U -/*Value to drive on dfi_lp_wakeup signal when Power Down mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycl - s - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles - 0x7 - 20 - 8 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0xD - 13107 - cycles - 0xE - 262144 cycles - 0xF - Unlimited*/ +/* +* Value to drive on dfi_lp_wakeup signal when Power Down mode is entered. + * Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32 cycle + * s - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cy + * cles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycles - 0x9 - + * 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cyc + * les - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited +*/ #undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_DEFVAL #undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_SHIFT #undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_MASK -#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_DEFVAL 0x07000000 -#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_SHIFT 4 -#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_MASK 0x000000F0U +#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_DEFVAL 0x07000000 +#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_SHIFT 4 +#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_MASK 0x000000F0U -/*Enables DFI Low Power interface handshaking during Power Down Entry/Exit. - 0 - Disabled - 1 - Enabled*/ +/* +* Enables DFI Low Power interface handshaking during Power Down Entry/Exit + * . - 0 - Disabled - 1 - Enabled +*/ #undef DDRC_DFILPCFG0_DFI_LP_EN_PD_DEFVAL #undef DDRC_DFILPCFG0_DFI_LP_EN_PD_SHIFT #undef DDRC_DFILPCFG0_DFI_LP_EN_PD_MASK -#define DDRC_DFILPCFG0_DFI_LP_EN_PD_DEFVAL 0x07000000 -#define DDRC_DFILPCFG0_DFI_LP_EN_PD_SHIFT 0 -#define DDRC_DFILPCFG0_DFI_LP_EN_PD_MASK 0x00000001U +#define DDRC_DFILPCFG0_DFI_LP_EN_PD_DEFVAL 0x07000000 +#define DDRC_DFILPCFG0_DFI_LP_EN_PD_SHIFT 0 +#define DDRC_DFILPCFG0_DFI_LP_EN_PD_MASK 0x00000001U -/*Value to drive on dfi_lp_wakeup signal when Maximum Power Saving Mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - - 16 cycles - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0 - D - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited This is only present for designs supporting DDR4 devices.*/ +/* +* Value to drive on dfi_lp_wakeup signal when Maximum Power Saving Mode is + * entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 + * - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x + * 5 - 512 cycles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycl + * es - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - + * 65536 cycles - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimi + * ted This is only present for designs supporting DDR4 devices. +*/ #undef DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_DEFVAL #undef DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_SHIFT #undef DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_MASK -#define DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_DEFVAL 0x00000000 -#define DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_SHIFT 4 -#define DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_MASK 0x000000F0U +#define DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_DEFVAL 0x00000000 +#define DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_SHIFT 4 +#define DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_MASK 0x000000F0U -/*Enables DFI Low Power interface handshaking during Maximum Power Saving Mode Entry/Exit. - 0 - Disabled - 1 - Enabled This is - only present for designs supporting DDR4 devices.*/ +/* +* Enables DFI Low Power interface handshaking during Maximum Power Saving + * Mode Entry/Exit. - 0 - Disabled - 1 - Enabled This is only present for d + * esigns supporting DDR4 devices. +*/ #undef DDRC_DFILPCFG1_DFI_LP_EN_MPSM_DEFVAL #undef DDRC_DFILPCFG1_DFI_LP_EN_MPSM_SHIFT #undef DDRC_DFILPCFG1_DFI_LP_EN_MPSM_MASK -#define DDRC_DFILPCFG1_DFI_LP_EN_MPSM_DEFVAL 0x00000000 -#define DDRC_DFILPCFG1_DFI_LP_EN_MPSM_SHIFT 0 -#define DDRC_DFILPCFG1_DFI_LP_EN_MPSM_MASK 0x00000001U +#define DDRC_DFILPCFG1_DFI_LP_EN_MPSM_DEFVAL 0x00000000 +#define DDRC_DFILPCFG1_DFI_LP_EN_MPSM_SHIFT 0 +#define DDRC_DFILPCFG1_DFI_LP_EN_MPSM_MASK 0x00000001U -/*This is the minimum amount of time between uMCTL2 initiated DFI update requests (which is executed whenever the uMCTL2 is idl - ). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the fir - t read request when the uMCTL2 is idle. Unit: 1024 clocks*/ +/* +* When '1', disable the automatic dfi_ctrlupd_req generation by the uMCTL2 + * . The core must issue the dfi_ctrlupd_req signal using register reg_ddrc + * _ctrlupd. When '0', uMCTL2 issues dfi_ctrlupd_req periodically. +*/ +#undef DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_DEFVAL +#undef DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SHIFT +#undef DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_MASK +#define DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_DEFVAL 0x00400003 +#define DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SHIFT 31 +#define DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_MASK 0x80000000U + +/* +* When '1', disable the automatic dfi_ctrlupd_req generation by the uMCTL2 + * following a self-refresh exit. The core must issue the dfi_ctrlupd_req + * signal using register reg_ddrc_ctrlupd. When '0', uMCTL2 issues a dfi_ct + * rlupd_req after exiting self-refresh. +*/ +#undef DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_DEFVAL +#undef DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_SHIFT +#undef DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_MASK +#define DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_DEFVAL 0x00400003 +#define DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_SHIFT 30 +#define DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_MASK 0x40000000U + +/* +* Specifies the maximum number of clock cycles that the dfi_ctrlupd_req si + * gnal can assert. Lowest value to assign to this variable is 0x40. Unit: + * Clocks +*/ +#undef DDRC_DFIUPD0_DFI_T_CTRLUP_MAX_DEFVAL +#undef DDRC_DFIUPD0_DFI_T_CTRLUP_MAX_SHIFT +#undef DDRC_DFIUPD0_DFI_T_CTRLUP_MAX_MASK +#define DDRC_DFIUPD0_DFI_T_CTRLUP_MAX_DEFVAL 0x00400003 +#define DDRC_DFIUPD0_DFI_T_CTRLUP_MAX_SHIFT 16 +#define DDRC_DFIUPD0_DFI_T_CTRLUP_MAX_MASK 0x03FF0000U + +/* +* Specifies the minimum number of clock cycles that the dfi_ctrlupd_req si + * gnal must be asserted. The uMCTL2 expects the PHY to respond within this + * time. If the PHY does not respond, the uMCTL2 will de-assert dfi_ctrlup + * d_req after dfi_t_ctrlup_min + 2 cycles. Lowest value to assign to this + * variable is 0x3. Unit: Clocks +*/ +#undef DDRC_DFIUPD0_DFI_T_CTRLUP_MIN_DEFVAL +#undef DDRC_DFIUPD0_DFI_T_CTRLUP_MIN_SHIFT +#undef DDRC_DFIUPD0_DFI_T_CTRLUP_MIN_MASK +#define DDRC_DFIUPD0_DFI_T_CTRLUP_MIN_DEFVAL 0x00400003 +#define DDRC_DFIUPD0_DFI_T_CTRLUP_MIN_SHIFT 0 +#define DDRC_DFIUPD0_DFI_T_CTRLUP_MIN_MASK 0x000003FFU + +/* +* This is the minimum amount of time between uMCTL2 initiated DFI update r + * equests (which is executed whenever the uMCTL2 is idle). Set this number + * higher to reduce the frequency of update requests, which can have a sma + * ll impact on the latency of the first read request when the uMCTL2 is id + * le. Unit: 1024 clocks +*/ #undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_DEFVAL #undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_SHIFT #undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_MASK -#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_DEFVAL 0x00000000 -#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_SHIFT 16 -#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_MASK 0x00FF0000U +#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_DEFVAL 0x00000000 +#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_SHIFT 16 +#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_MASK 0x00FF0000U -/*This is the maximum amount of time between uMCTL2 initiated DFI update requests. This timer resets with each update request; - hen the timer expires dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd_ackx is received. PHY can use this - idle time to recalibrate the delay lines to the DLLs. The DFI controller update is also used to reset PHY FIFO pointers in ca - e of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. - Note: Value programmed for DFIUPD1.dfi_t_ctrlupd_interval_max_x1024 must be greater than DFIUPD1.dfi_t_ctrlupd_interval_min_x - 024. Unit: 1024 clocks*/ +/* +* This is the maximum amount of time between uMCTL2 initiated DFI update r + * equests. This timer resets with each update request; when the timer expi + * res dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd + * _ackx is received. PHY can use this idle time to recalibrate the delay l + * ines to the DLLs. The DFI controller update is also used to reset PHY FI + * FO pointers in case of data capture errors. Updates are required to main + * tain calibration over PVT, but frequent updates may impact performance. + * Note: Value programmed for DFIUPD1.dfi_t_ctrlupd_interval_max_x1024 must + * be greater than DFIUPD1.dfi_t_ctrlupd_interval_min_x1024. Unit: 1024 cl + * ocks +*/ #undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_DEFVAL #undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_SHIFT #undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_MASK -#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_DEFVAL 0x00000000 -#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_SHIFT 0 -#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_MASK 0x000000FFU +#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_DEFVAL 0x00000000 +#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_SHIFT 0 +#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_MASK 0x000000FFU -/*Defines polarity of dfi_wrdata_cs and dfi_rddata_cs signals. - 0: Signals are active low - 1: Signals are active high*/ +/* +* Defines polarity of dfi_wrdata_cs and dfi_rddata_cs signals. - 0: Signal + * s are active low - 1: Signals are active high +*/ #undef DDRC_DFIMISC_DFI_DATA_CS_POLARITY_DEFVAL #undef DDRC_DFIMISC_DFI_DATA_CS_POLARITY_SHIFT #undef DDRC_DFIMISC_DFI_DATA_CS_POLARITY_MASK -#define DDRC_DFIMISC_DFI_DATA_CS_POLARITY_DEFVAL 0x00000001 -#define DDRC_DFIMISC_DFI_DATA_CS_POLARITY_SHIFT 2 -#define DDRC_DFIMISC_DFI_DATA_CS_POLARITY_MASK 0x00000004U +#define DDRC_DFIMISC_DFI_DATA_CS_POLARITY_DEFVAL 0x00000001 +#define DDRC_DFIMISC_DFI_DATA_CS_POLARITY_SHIFT 2 +#define DDRC_DFIMISC_DFI_DATA_CS_POLARITY_MASK 0x00000004U -/*DBI implemented in DDRC or PHY. - 0 - DDRC implements DBI functionality. - 1 - PHY implements DBI functionality. Present only - in designs configured to support DDR4 and LPDDR4.*/ +/* +* DBI implemented in DDRC or PHY. - 0 - DDRC implements DBI functionality. + * - 1 - PHY implements DBI functionality. Present only in designs configu + * red to support DDR4 and LPDDR4. +*/ #undef DDRC_DFIMISC_PHY_DBI_MODE_DEFVAL #undef DDRC_DFIMISC_PHY_DBI_MODE_SHIFT #undef DDRC_DFIMISC_PHY_DBI_MODE_MASK -#define DDRC_DFIMISC_PHY_DBI_MODE_DEFVAL 0x00000001 -#define DDRC_DFIMISC_PHY_DBI_MODE_SHIFT 1 -#define DDRC_DFIMISC_PHY_DBI_MODE_MASK 0x00000002U +#define DDRC_DFIMISC_PHY_DBI_MODE_DEFVAL 0x00000001 +#define DDRC_DFIMISC_PHY_DBI_MODE_SHIFT 1 +#define DDRC_DFIMISC_PHY_DBI_MODE_MASK 0x00000002U -/*PHY initialization complete enable signal. When asserted the dfi_init_complete signal can be used to trigger SDRAM initialisa - ion*/ +/* +* PHY initialization complete enable signal. When asserted the dfi_init_co + * mplete signal can be used to trigger SDRAM initialisation +*/ #undef DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_DEFVAL #undef DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_SHIFT #undef DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_MASK -#define DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_DEFVAL 0x00000001 -#define DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_SHIFT 0 -#define DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_MASK 0x00000001U +#define DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_DEFVAL 0x00000001 +#define DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_SHIFT 0 +#define DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_MASK 0x00000001U -/*>Number of clocks between when a read command is sent on the DFI control interface and when the associated dfi_rddata_cs sign - l is asserted. This corresponds to the DFI timing parameter tphy_rdcslat. Refer to PHY specification for correct value.*/ +/* +* >Number of clocks between when a read command is sent on the DFI control + * interface and when the associated dfi_rddata_cs signal is asserted. Thi + * s corresponds to the DFI timing parameter tphy_rdcslat. Refer to PHY spe + * cification for correct value. +*/ #undef DDRC_DFITMG2_DFI_TPHY_RDCSLAT_DEFVAL #undef DDRC_DFITMG2_DFI_TPHY_RDCSLAT_SHIFT #undef DDRC_DFITMG2_DFI_TPHY_RDCSLAT_MASK -#define DDRC_DFITMG2_DFI_TPHY_RDCSLAT_DEFVAL 0x00000202 -#define DDRC_DFITMG2_DFI_TPHY_RDCSLAT_SHIFT 8 -#define DDRC_DFITMG2_DFI_TPHY_RDCSLAT_MASK 0x00003F00U +#define DDRC_DFITMG2_DFI_TPHY_RDCSLAT_DEFVAL 0x00000202 +#define DDRC_DFITMG2_DFI_TPHY_RDCSLAT_SHIFT 8 +#define DDRC_DFITMG2_DFI_TPHY_RDCSLAT_MASK 0x00003F00U -/*Number of clocks between when a write command is sent on the DFI control interface and when the associated dfi_wrdata_cs sign - l is asserted. This corresponds to the DFI timing parameter tphy_wrcslat. Refer to PHY specification for correct value.*/ +/* +* Number of clocks between when a write command is sent on the DFI control + * interface and when the associated dfi_wrdata_cs signal is asserted. Thi + * s corresponds to the DFI timing parameter tphy_wrcslat. Refer to PHY spe + * cification for correct value. +*/ #undef DDRC_DFITMG2_DFI_TPHY_WRCSLAT_DEFVAL #undef DDRC_DFITMG2_DFI_TPHY_WRCSLAT_SHIFT #undef DDRC_DFITMG2_DFI_TPHY_WRCSLAT_MASK -#define DDRC_DFITMG2_DFI_TPHY_WRCSLAT_DEFVAL 0x00000202 -#define DDRC_DFITMG2_DFI_TPHY_WRCSLAT_SHIFT 0 -#define DDRC_DFITMG2_DFI_TPHY_WRCSLAT_MASK 0x0000003FU +#define DDRC_DFITMG2_DFI_TPHY_WRCSLAT_DEFVAL 0x00000202 +#define DDRC_DFITMG2_DFI_TPHY_WRCSLAT_SHIFT 0 +#define DDRC_DFITMG2_DFI_TPHY_WRCSLAT_MASK 0x0000003FU -/*Read DBI enable signal in DDRC. - 0 - Read DBI is disabled. - 1 - Read DBI is enabled. This signal must be set the same value - as DRAM's mode register. - DDR4: MR5 bit A12. When x4 devices are used, this signal must be set to 0. - LPDDR4: MR3[6]*/ +/* +* Read DBI enable signal in DDRC. - 0 - Read DBI is disabled. - 1 - Read D + * BI is enabled. This signal must be set the same value as DRAM's mode reg + * ister. - DDR4: MR5 bit A12. When x4 devices are used, this signal must b + * e set to 0. - LPDDR4: MR3[6] +*/ #undef DDRC_DBICTL_RD_DBI_EN_DEFVAL #undef DDRC_DBICTL_RD_DBI_EN_SHIFT #undef DDRC_DBICTL_RD_DBI_EN_MASK -#define DDRC_DBICTL_RD_DBI_EN_DEFVAL 0x00000001 -#define DDRC_DBICTL_RD_DBI_EN_SHIFT 2 -#define DDRC_DBICTL_RD_DBI_EN_MASK 0x00000004U +#define DDRC_DBICTL_RD_DBI_EN_DEFVAL 0x00000001 +#define DDRC_DBICTL_RD_DBI_EN_SHIFT 2 +#define DDRC_DBICTL_RD_DBI_EN_MASK 0x00000004U -/*Write DBI enable signal in DDRC. - 0 - Write DBI is disabled. - 1 - Write DBI is enabled. This signal must be set the same va - ue as DRAM's mode register. - DDR4: MR5 bit A11. When x4 devices are used, this signal must be set to 0. - LPDDR4: MR3[7]*/ +/* +* Write DBI enable signal in DDRC. - 0 - Write DBI is disabled. - 1 - Writ + * e DBI is enabled. This signal must be set the same value as DRAM's mode + * register. - DDR4: MR5 bit A11. When x4 devices are used, this signal mus + * t be set to 0. - LPDDR4: MR3[7] +*/ #undef DDRC_DBICTL_WR_DBI_EN_DEFVAL #undef DDRC_DBICTL_WR_DBI_EN_SHIFT #undef DDRC_DBICTL_WR_DBI_EN_MASK -#define DDRC_DBICTL_WR_DBI_EN_DEFVAL 0x00000001 -#define DDRC_DBICTL_WR_DBI_EN_SHIFT 1 -#define DDRC_DBICTL_WR_DBI_EN_MASK 0x00000002U +#define DDRC_DBICTL_WR_DBI_EN_DEFVAL 0x00000001 +#define DDRC_DBICTL_WR_DBI_EN_SHIFT 1 +#define DDRC_DBICTL_WR_DBI_EN_MASK 0x00000002U -/*DM enable signal in DDRC. - 0 - DM is disabled. - 1 - DM is enabled. This signal must be set the same logical value as DRAM's - mode register. - DDR4: Set this to same value as MR5 bit A10. When x4 devices are used, this signal must be set to 0. - LPDDR - : Set this to inverted value of MR13[5] which is opposite polarity from this signal*/ +/* +* DM enable signal in DDRC. - 0 - DM is disabled. - 1 - DM is enabled. Thi + * s signal must be set the same logical value as DRAM's mode register. - D + * DR4: Set this to same value as MR5 bit A10. When x4 devices are used, th + * is signal must be set to 0. - LPDDR4: Set this to inverted value of MR13 + * [5] which is opposite polarity from this signal +*/ #undef DDRC_DBICTL_DM_EN_DEFVAL #undef DDRC_DBICTL_DM_EN_SHIFT #undef DDRC_DBICTL_DM_EN_MASK -#define DDRC_DBICTL_DM_EN_DEFVAL 0x00000001 -#define DDRC_DBICTL_DM_EN_SHIFT 0 -#define DDRC_DBICTL_DM_EN_MASK 0x00000001U +#define DDRC_DBICTL_DM_EN_DEFVAL 0x00000001 +#define DDRC_DBICTL_DM_EN_SHIFT 0 +#define DDRC_DBICTL_DM_EN_MASK 0x00000001U -/*Selects the HIF address bit used as rank address bit 0. Valid Range: 0 to 27, and 31 Internal Base: 6 The selected HIF addres - bit is determined by adding the internal base to the value of this field. If set to 31, rank address bit 0 is set to 0.*/ +/* +* Selects the HIF address bit used as rank address bit 0. Valid Range: 0 t + * o 27, and 31 Internal Base: 6 The selected HIF address bit is determined + * by adding the internal base to the value of this field. If set to 31, r + * ank address bit 0 is set to 0. +*/ #undef DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_DEFVAL #undef DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_SHIFT #undef DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_MASK -#define DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_DEFVAL -#define DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_SHIFT 0 -#define DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_MASK 0x0000001FU +#define DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_DEFVAL +#define DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_SHIFT 0 +#define DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_MASK 0x0000001FU -/*Selects the HIF address bit used as bank address bit 2. Valid Range: 0 to 29 and 31 Internal Base: 4 The selected HIF address - bit is determined by adding the internal base to the value of this field. If set to 31, bank address bit 2 is set to 0.*/ +/* +* Selects the HIF address bit used as bank address bit 2. Valid Range: 0 t + * o 29 and 31 Internal Base: 4 The selected HIF address bit is determined + * by adding the internal base to the value of this field. If set to 31, ba + * nk address bit 2 is set to 0. +*/ #undef DDRC_ADDRMAP1_ADDRMAP_BANK_B2_DEFVAL #undef DDRC_ADDRMAP1_ADDRMAP_BANK_B2_SHIFT #undef DDRC_ADDRMAP1_ADDRMAP_BANK_B2_MASK -#define DDRC_ADDRMAP1_ADDRMAP_BANK_B2_DEFVAL 0x00000000 -#define DDRC_ADDRMAP1_ADDRMAP_BANK_B2_SHIFT 16 -#define DDRC_ADDRMAP1_ADDRMAP_BANK_B2_MASK 0x001F0000U +#define DDRC_ADDRMAP1_ADDRMAP_BANK_B2_DEFVAL 0x00000000 +#define DDRC_ADDRMAP1_ADDRMAP_BANK_B2_SHIFT 16 +#define DDRC_ADDRMAP1_ADDRMAP_BANK_B2_MASK 0x001F0000U -/*Selects the HIF address bits used as bank address bit 1. Valid Range: 0 to 30 Internal Base: 3 The selected HIF address bit f - r each of the bank address bits is determined by adding the internal base to the value of this field.*/ +/* +* Selects the HIF address bits used as bank address bit 1. Valid Range: 0 + * to 30 Internal Base: 3 The selected HIF address bit for each of the bank + * address bits is determined by adding the internal base to the value of + * this field. +*/ #undef DDRC_ADDRMAP1_ADDRMAP_BANK_B1_DEFVAL #undef DDRC_ADDRMAP1_ADDRMAP_BANK_B1_SHIFT #undef DDRC_ADDRMAP1_ADDRMAP_BANK_B1_MASK -#define DDRC_ADDRMAP1_ADDRMAP_BANK_B1_DEFVAL 0x00000000 -#define DDRC_ADDRMAP1_ADDRMAP_BANK_B1_SHIFT 8 -#define DDRC_ADDRMAP1_ADDRMAP_BANK_B1_MASK 0x00001F00U +#define DDRC_ADDRMAP1_ADDRMAP_BANK_B1_DEFVAL 0x00000000 +#define DDRC_ADDRMAP1_ADDRMAP_BANK_B1_SHIFT 8 +#define DDRC_ADDRMAP1_ADDRMAP_BANK_B1_MASK 0x00001F00U -/*Selects the HIF address bits used as bank address bit 0. Valid Range: 0 to 30 Internal Base: 2 The selected HIF address bit f - r each of the bank address bits is determined by adding the internal base to the value of this field.*/ +/* +* Selects the HIF address bits used as bank address bit 0. Valid Range: 0 + * to 30 Internal Base: 2 The selected HIF address bit for each of the bank + * address bits is determined by adding the internal base to the value of + * this field. +*/ #undef DDRC_ADDRMAP1_ADDRMAP_BANK_B0_DEFVAL #undef DDRC_ADDRMAP1_ADDRMAP_BANK_B0_SHIFT #undef DDRC_ADDRMAP1_ADDRMAP_BANK_B0_MASK -#define DDRC_ADDRMAP1_ADDRMAP_BANK_B0_DEFVAL 0x00000000 -#define DDRC_ADDRMAP1_ADDRMAP_BANK_B0_SHIFT 0 -#define DDRC_ADDRMAP1_ADDRMAP_BANK_B0_MASK 0x0000001FU +#define DDRC_ADDRMAP1_ADDRMAP_BANK_B0_DEFVAL 0x00000000 +#define DDRC_ADDRMAP1_ADDRMAP_BANK_B0_SHIFT 0 +#define DDRC_ADDRMAP1_ADDRMAP_BANK_B0_MASK 0x0000001FU -/*- Full bus width mode: Selects the HIF address bit used as column address bit 5. - Half bus width mode: Selects the HIF addre - s bit used as column address bit 6. - Quarter bus width mode: Selects the HIF address bit used as column address bit 7 . Vali - Range: 0 to 7, and 15 Internal Base: 5 The selected HIF address bit is determined by adding the internal base to the value o - this field. If set to 15, this column address bit is set to 0.*/ +/* +* - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 5. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 6. - Quarter bus width mode: Selects the HIF address bit + * used as column address bit 7 . Valid Range: 0 to 7, and 15 Internal Base + * : 5 The selected HIF address bit is determined by adding the internal ba + * se to the value of this field. If set to 15, this column address bit is + * set to 0. +*/ #undef DDRC_ADDRMAP2_ADDRMAP_COL_B5_DEFVAL #undef DDRC_ADDRMAP2_ADDRMAP_COL_B5_SHIFT #undef DDRC_ADDRMAP2_ADDRMAP_COL_B5_MASK -#define DDRC_ADDRMAP2_ADDRMAP_COL_B5_DEFVAL 0x00000000 -#define DDRC_ADDRMAP2_ADDRMAP_COL_B5_SHIFT 24 -#define DDRC_ADDRMAP2_ADDRMAP_COL_B5_MASK 0x0F000000U +#define DDRC_ADDRMAP2_ADDRMAP_COL_B5_DEFVAL 0x00000000 +#define DDRC_ADDRMAP2_ADDRMAP_COL_B5_SHIFT 24 +#define DDRC_ADDRMAP2_ADDRMAP_COL_B5_MASK 0x0F000000U -/*- Full bus width mode: Selects the HIF address bit used as column address bit 4. - Half bus width mode: Selects the HIF addre - s bit used as column address bit 5. - Quarter bus width mode: Selects the HIF address bit used as column address bit 6. Valid - Range: 0 to 7, and 15 Internal Base: 4 The selected HIF address bit is determined by adding the internal base to the value of - this field. If set to 15, this column address bit is set to 0.*/ +/* +* - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 4. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 5. - Quarter bus width mode: Selects the HIF address bit + * used as column address bit 6. Valid Range: 0 to 7, and 15 Internal Base: + * 4 The selected HIF address bit is determined by adding the internal bas + * e to the value of this field. If set to 15, this column address bit is s + * et to 0. +*/ #undef DDRC_ADDRMAP2_ADDRMAP_COL_B4_DEFVAL #undef DDRC_ADDRMAP2_ADDRMAP_COL_B4_SHIFT #undef DDRC_ADDRMAP2_ADDRMAP_COL_B4_MASK -#define DDRC_ADDRMAP2_ADDRMAP_COL_B4_DEFVAL 0x00000000 -#define DDRC_ADDRMAP2_ADDRMAP_COL_B4_SHIFT 16 -#define DDRC_ADDRMAP2_ADDRMAP_COL_B4_MASK 0x000F0000U +#define DDRC_ADDRMAP2_ADDRMAP_COL_B4_DEFVAL 0x00000000 +#define DDRC_ADDRMAP2_ADDRMAP_COL_B4_SHIFT 16 +#define DDRC_ADDRMAP2_ADDRMAP_COL_B4_MASK 0x000F0000U -/*- Full bus width mode: Selects the HIF address bit used as column address bit 3. - Half bus width mode: Selects the HIF addre - s bit used as column address bit 4. - Quarter bus width mode: Selects the HIF address bit used as column address bit 5. Valid - Range: 0 to 7 Internal Base: 3 The selected HIF address bit is determined by adding the internal base to the value of this fi - ld. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=16, it is required to program this to 0, hence register does not exist i - this case.*/ +/* +* - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 3. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 4. - Quarter bus width mode: Selects the HIF address bit + * used as column address bit 5. Valid Range: 0 to 7 Internal Base: 3 The s + * elected HIF address bit is determined by adding the internal base to the + * value of this field. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=1 + * 6, it is required to program this to 0, hence register does not exist in + * this case. +*/ #undef DDRC_ADDRMAP2_ADDRMAP_COL_B3_DEFVAL #undef DDRC_ADDRMAP2_ADDRMAP_COL_B3_SHIFT #undef DDRC_ADDRMAP2_ADDRMAP_COL_B3_MASK -#define DDRC_ADDRMAP2_ADDRMAP_COL_B3_DEFVAL 0x00000000 -#define DDRC_ADDRMAP2_ADDRMAP_COL_B3_SHIFT 8 -#define DDRC_ADDRMAP2_ADDRMAP_COL_B3_MASK 0x00000F00U +#define DDRC_ADDRMAP2_ADDRMAP_COL_B3_DEFVAL 0x00000000 +#define DDRC_ADDRMAP2_ADDRMAP_COL_B3_SHIFT 8 +#define DDRC_ADDRMAP2_ADDRMAP_COL_B3_MASK 0x00000F00U -/*- Full bus width mode: Selects the HIF address bit used as column address bit 2. - Half bus width mode: Selects the HIF addre - s bit used as column address bit 3. - Quarter bus width mode: Selects the HIF address bit used as column address bit 4. Valid - Range: 0 to 7 Internal Base: 2 The selected HIF address bit is determined by adding the internal base to the value of this fi - ld. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=8 or 16, it is required to program this to 0.*/ +/* +* - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 2. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 3. - Quarter bus width mode: Selects the HIF address bit + * used as column address bit 4. Valid Range: 0 to 7 Internal Base: 2 The s + * elected HIF address bit is determined by adding the internal base to the + * value of this field. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=8 + * or 16, it is required to program this to 0. +*/ #undef DDRC_ADDRMAP2_ADDRMAP_COL_B2_DEFVAL #undef DDRC_ADDRMAP2_ADDRMAP_COL_B2_SHIFT #undef DDRC_ADDRMAP2_ADDRMAP_COL_B2_MASK -#define DDRC_ADDRMAP2_ADDRMAP_COL_B2_DEFVAL 0x00000000 -#define DDRC_ADDRMAP2_ADDRMAP_COL_B2_SHIFT 0 -#define DDRC_ADDRMAP2_ADDRMAP_COL_B2_MASK 0x0000000FU +#define DDRC_ADDRMAP2_ADDRMAP_COL_B2_DEFVAL 0x00000000 +#define DDRC_ADDRMAP2_ADDRMAP_COL_B2_SHIFT 0 +#define DDRC_ADDRMAP2_ADDRMAP_COL_B2_MASK 0x0000000FU -/*- Full bus width mode: Selects the HIF address bit used as column address bit 9. - Half bus width mode: Selects the HIF addre - s bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). - Quarter bus width mode: Selects the HIF address bit used as - column address bit 13 (11 in LPDDR2/LPDDR3 mode). Valid Range: 0 to 7, and 15 Internal Base: 9 The selected HIF address bit i - determined by adding the internal base to the value of this field. If set to 15, this column address bit is set to 0. Note: - er JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source addr - ss bit can be mapped to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus an - hence column bit 10 is used.*/ +/* +* - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 9. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 11 (10 in LPDDR2/LPDDR3 mode). - Quarter bus width mode: + * Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/ + * LPDDR3 mode). Valid Range: 0 to 7, and 15 Internal Base: 9 The selected + * HIF address bit is determined by adding the internal base to the value o + * f this field. If set to 15, this column address bit is set to 0. Note: P + * er JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved fo + * r indicating auto-precharge, and hence no source address bit can be mapp + * ed to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit + * for auto-precharge in the CA bus and hence column bit 10 is used. +*/ #undef DDRC_ADDRMAP3_ADDRMAP_COL_B9_DEFVAL #undef DDRC_ADDRMAP3_ADDRMAP_COL_B9_SHIFT #undef DDRC_ADDRMAP3_ADDRMAP_COL_B9_MASK -#define DDRC_ADDRMAP3_ADDRMAP_COL_B9_DEFVAL 0x00000000 -#define DDRC_ADDRMAP3_ADDRMAP_COL_B9_SHIFT 24 -#define DDRC_ADDRMAP3_ADDRMAP_COL_B9_MASK 0x0F000000U +#define DDRC_ADDRMAP3_ADDRMAP_COL_B9_DEFVAL 0x00000000 +#define DDRC_ADDRMAP3_ADDRMAP_COL_B9_SHIFT 24 +#define DDRC_ADDRMAP3_ADDRMAP_COL_B9_MASK 0x0F000000U -/*- Full bus width mode: Selects the HIF address bit used as column address bit 8. - Half bus width mode: Selects the HIF addre - s bit used as column address bit 9. - Quarter bus width mode: Selects the HIF address bit used as column address bit 11 (10 i - LPDDR2/LPDDR3 mode). Valid Range: 0 to 7, and 15 Internal Base: 8 The selected HIF address bit is determined by adding the i - ternal base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specif - cation, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to col - mn address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and hence column bit 10 is use - .*/ +/* +* - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 8. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 9. - Quarter bus width mode: Selects the HIF address bit + * used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). Valid Range: 0 + * to 7, and 15 Internal Base: 8 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specifi + * cation, column address bit 10 is reserved for indicating auto-precharge, + * and hence no source address bit can be mapped to column address bit 10. + * In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA + * bus and hence column bit 10 is used. +*/ #undef DDRC_ADDRMAP3_ADDRMAP_COL_B8_DEFVAL #undef DDRC_ADDRMAP3_ADDRMAP_COL_B8_SHIFT #undef DDRC_ADDRMAP3_ADDRMAP_COL_B8_MASK -#define DDRC_ADDRMAP3_ADDRMAP_COL_B8_DEFVAL 0x00000000 -#define DDRC_ADDRMAP3_ADDRMAP_COL_B8_SHIFT 16 -#define DDRC_ADDRMAP3_ADDRMAP_COL_B8_MASK 0x000F0000U +#define DDRC_ADDRMAP3_ADDRMAP_COL_B8_DEFVAL 0x00000000 +#define DDRC_ADDRMAP3_ADDRMAP_COL_B8_SHIFT 16 +#define DDRC_ADDRMAP3_ADDRMAP_COL_B8_MASK 0x000F0000U -/*- Full bus width mode: Selects the HIF address bit used as column address bit 7. - Half bus width mode: Selects the HIF addre - s bit used as column address bit 8. - Quarter bus width mode: Selects the HIF address bit used as column address bit 9. Valid - Range: 0 to 7, and 15 Internal Base: 7 The selected HIF address bit is determined by adding the internal base to the value of - this field. If set to 15, this column address bit is set to 0.*/ +/* +* - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 7. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 8. - Quarter bus width mode: Selects the HIF address bit + * used as column address bit 9. Valid Range: 0 to 7, and 15 Internal Base: + * 7 The selected HIF address bit is determined by adding the internal bas + * e to the value of this field. If set to 15, this column address bit is s + * et to 0. +*/ #undef DDRC_ADDRMAP3_ADDRMAP_COL_B7_DEFVAL #undef DDRC_ADDRMAP3_ADDRMAP_COL_B7_SHIFT #undef DDRC_ADDRMAP3_ADDRMAP_COL_B7_MASK -#define DDRC_ADDRMAP3_ADDRMAP_COL_B7_DEFVAL 0x00000000 -#define DDRC_ADDRMAP3_ADDRMAP_COL_B7_SHIFT 8 -#define DDRC_ADDRMAP3_ADDRMAP_COL_B7_MASK 0x00000F00U +#define DDRC_ADDRMAP3_ADDRMAP_COL_B7_DEFVAL 0x00000000 +#define DDRC_ADDRMAP3_ADDRMAP_COL_B7_SHIFT 8 +#define DDRC_ADDRMAP3_ADDRMAP_COL_B7_MASK 0x00000F00U -/*- Full bus width mode: Selects the HIF address bit used as column address bit 6. - Half bus width mode: Selects the HIF addre - s bit used as column address bit 7. - Quarter bus width mode: Selects the HIF address bit used as column address bit 8. Valid - Range: 0 to 7, and 15 Internal Base: 6 The selected HIF address bit is determined by adding the internal base to the value of - this field. If set to 15, this column address bit is set to 0.*/ +/* +* - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 6. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 7. - Quarter bus width mode: Selects the HIF address bit + * used as column address bit 8. Valid Range: 0 to 7, and 15 Internal Base: + * 6 The selected HIF address bit is determined by adding the internal bas + * e to the value of this field. If set to 15, this column address bit is s + * et to 0. +*/ #undef DDRC_ADDRMAP3_ADDRMAP_COL_B6_DEFVAL #undef DDRC_ADDRMAP3_ADDRMAP_COL_B6_SHIFT #undef DDRC_ADDRMAP3_ADDRMAP_COL_B6_MASK -#define DDRC_ADDRMAP3_ADDRMAP_COL_B6_DEFVAL 0x00000000 -#define DDRC_ADDRMAP3_ADDRMAP_COL_B6_SHIFT 0 -#define DDRC_ADDRMAP3_ADDRMAP_COL_B6_MASK 0x0000000FU +#define DDRC_ADDRMAP3_ADDRMAP_COL_B6_DEFVAL 0x00000000 +#define DDRC_ADDRMAP3_ADDRMAP_COL_B6_SHIFT 0 +#define DDRC_ADDRMAP3_ADDRMAP_COL_B6_MASK 0x0000000FU -/*- Full bus width mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode). - Half bus width - mode: Unused. To make it unused, this should be tied to 4'hF. - Quarter bus width mode: Unused. To make it unused, this must - e tied to 4'hF. Valid Range: 0 to 7, and 15 Internal Base: 11 The selected HIF address bit is determined by adding the intern - l base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specificati - n, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column a - dress bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and hence column bit 10 is used.*/ +/* +* - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 13 (11 in LPDDR2/LPDDR3 mode). - Half bus width mode: Unused. To m + * ake it unused, this should be tied to 4'hF. - Quarter bus width mode: Un + * used. To make it unused, this must be tied to 4'hF. Valid Range: 0 to 7, + * and 15 Internal Base: 11 The selected HIF address bit is determined by + * adding the internal base to the value of this field. If set to 15, this + * column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specificatio + * n, column address bit 10 is reserved for indicating auto-precharge, and + * hence no source address bit can be mapped to column address bit 10. In L + * PDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus + * and hence column bit 10 is used. +*/ #undef DDRC_ADDRMAP4_ADDRMAP_COL_B11_DEFVAL #undef DDRC_ADDRMAP4_ADDRMAP_COL_B11_SHIFT #undef DDRC_ADDRMAP4_ADDRMAP_COL_B11_MASK -#define DDRC_ADDRMAP4_ADDRMAP_COL_B11_DEFVAL 0x00000000 -#define DDRC_ADDRMAP4_ADDRMAP_COL_B11_SHIFT 8 -#define DDRC_ADDRMAP4_ADDRMAP_COL_B11_MASK 0x00000F00U +#define DDRC_ADDRMAP4_ADDRMAP_COL_B11_DEFVAL 0x00000000 +#define DDRC_ADDRMAP4_ADDRMAP_COL_B11_SHIFT 8 +#define DDRC_ADDRMAP4_ADDRMAP_COL_B11_MASK 0x00000F00U -/*- Full bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). - Half bus width - mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode). - Quarter bus width mode: UNUSED. - To make it unused, this must be tied to 4'hF. Valid Range: 0 to 7, and 15 Internal Base: 10 The selected HIF address bit is d - termined by adding the internal base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per - JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source address - bit can be mapped to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and h - nce column bit 10 is used.*/ +/* +* - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 11 (10 in LPDDR2/LPDDR3 mode). - Half bus width mode: Selects the + * HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode) + * . - Quarter bus width mode: UNUSED. To make it unused, this must be tied + * to 4'hF. Valid Range: 0 to 7, and 15 Internal Base: 10 The selected HIF + * address bit is determined by adding the internal base to the value of t + * his field. If set to 15, this column address bit is set to 0. Note: Per + * JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for i + * ndicating auto-precharge, and hence no source address bit can be mapped + * to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for + * auto-precharge in the CA bus and hence column bit 10 is used. +*/ #undef DDRC_ADDRMAP4_ADDRMAP_COL_B10_DEFVAL #undef DDRC_ADDRMAP4_ADDRMAP_COL_B10_SHIFT #undef DDRC_ADDRMAP4_ADDRMAP_COL_B10_MASK -#define DDRC_ADDRMAP4_ADDRMAP_COL_B10_DEFVAL 0x00000000 -#define DDRC_ADDRMAP4_ADDRMAP_COL_B10_SHIFT 0 -#define DDRC_ADDRMAP4_ADDRMAP_COL_B10_MASK 0x0000000FU +#define DDRC_ADDRMAP4_ADDRMAP_COL_B10_DEFVAL 0x00000000 +#define DDRC_ADDRMAP4_ADDRMAP_COL_B10_SHIFT 0 +#define DDRC_ADDRMAP4_ADDRMAP_COL_B10_MASK 0x0000000FU -/*Selects the HIF address bit used as row address bit 11. Valid Range: 0 to 11, and 15 Internal Base: 17 The selected HIF addre - s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 11 is set to 0.*/ +/* +* Selects the HIF address bit used as row address bit 11. Valid Range: 0 t + * o 11, and 15 Internal Base: 17 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * row address bit 11 is set to 0. +*/ #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B11_DEFVAL #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B11_SHIFT #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B11_MASK -#define DDRC_ADDRMAP5_ADDRMAP_ROW_B11_DEFVAL 0x00000000 -#define DDRC_ADDRMAP5_ADDRMAP_ROW_B11_SHIFT 24 -#define DDRC_ADDRMAP5_ADDRMAP_ROW_B11_MASK 0x0F000000U +#define DDRC_ADDRMAP5_ADDRMAP_ROW_B11_DEFVAL 0x00000000 +#define DDRC_ADDRMAP5_ADDRMAP_ROW_B11_SHIFT 24 +#define DDRC_ADDRMAP5_ADDRMAP_ROW_B11_MASK 0x0F000000U -/*Selects the HIF address bits used as row address bits 2 to 10. Valid Range: 0 to 11, and 15 Internal Base: 8 (for row address - bit 2), 9 (for row address bit 3), 10 (for row address bit 4) etc increasing to 16 (for row address bit 10) The selected HIF - ddress bit for each of the row address bits is determined by adding the internal base to the value of this field. When value - 5 is used the values of row address bits 2 to 10 are defined by registers ADDRMAP9, ADDRMAP10, ADDRMAP11.*/ +/* +* Selects the HIF address bits used as row address bits 2 to 10. Valid Ran + * ge: 0 to 11, and 15 Internal Base: 8 (for row address bit 2), 9 (for row + * address bit 3), 10 (for row address bit 4) etc increasing to 16 (for ro + * w address bit 10) The selected HIF address bit for each of the row addre + * ss bits is determined by adding the internal base to the value of this f + * ield. When value 15 is used the values of row address bits 2 to 10 are d + * efined by registers ADDRMAP9, ADDRMAP10, ADDRMAP11. +*/ #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_DEFVAL #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_SHIFT #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_MASK -#define DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_DEFVAL 0x00000000 -#define DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_SHIFT 16 -#define DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_MASK 0x000F0000U +#define DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_DEFVAL 0x00000000 +#define DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_SHIFT 16 +#define DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_MASK 0x000F0000U -/*Selects the HIF address bits used as row address bit 1. Valid Range: 0 to 11 Internal Base: 7 The selected HIF address bit fo - each of the row address bits is determined by adding the internal base to the value of this field.*/ +/* +* Selects the HIF address bits used as row address bit 1. Valid Range: 0 t + * o 11 Internal Base: 7 The selected HIF address bit for each of the row a + * ddress bits is determined by adding the internal base to the value of th + * is field. +*/ #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B1_DEFVAL #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B1_SHIFT #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B1_MASK -#define DDRC_ADDRMAP5_ADDRMAP_ROW_B1_DEFVAL 0x00000000 -#define DDRC_ADDRMAP5_ADDRMAP_ROW_B1_SHIFT 8 -#define DDRC_ADDRMAP5_ADDRMAP_ROW_B1_MASK 0x00000F00U +#define DDRC_ADDRMAP5_ADDRMAP_ROW_B1_DEFVAL 0x00000000 +#define DDRC_ADDRMAP5_ADDRMAP_ROW_B1_SHIFT 8 +#define DDRC_ADDRMAP5_ADDRMAP_ROW_B1_MASK 0x00000F00U -/*Selects the HIF address bits used as row address bit 0. Valid Range: 0 to 11 Internal Base: 6 The selected HIF address bit fo - each of the row address bits is determined by adding the internal base to the value of this field.*/ +/* +* Selects the HIF address bits used as row address bit 0. Valid Range: 0 t + * o 11 Internal Base: 6 The selected HIF address bit for each of the row a + * ddress bits is determined by adding the internal base to the value of th + * is field. +*/ #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B0_DEFVAL #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B0_SHIFT #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B0_MASK -#define DDRC_ADDRMAP5_ADDRMAP_ROW_B0_DEFVAL 0x00000000 -#define DDRC_ADDRMAP5_ADDRMAP_ROW_B0_SHIFT 0 -#define DDRC_ADDRMAP5_ADDRMAP_ROW_B0_MASK 0x0000000FU +#define DDRC_ADDRMAP5_ADDRMAP_ROW_B0_DEFVAL 0x00000000 +#define DDRC_ADDRMAP5_ADDRMAP_ROW_B0_SHIFT 0 +#define DDRC_ADDRMAP5_ADDRMAP_ROW_B0_MASK 0x0000000FU -/*Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use. - 1 - LPDDR3 SDRAM 6Gb/12Gb device in use. Every address - having row[14:13]==2'b11 is considered as invalid - 0 - non-LPDDR3 6Gb/12Gb device in use. All addresses are valid Present on - y in designs configured to support LPDDR3.*/ +/* +* Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use. - 1 + * - LPDDR3 SDRAM 6Gb/12Gb device in use. Every address having row[14:13]= + * =2'b11 is considered as invalid - 0 - non-LPDDR3 6Gb/12Gb device in use. + * All addresses are valid Present only in designs configured to support L + * PDDR3. +*/ #undef DDRC_ADDRMAP6_LPDDR3_6GB_12GB_DEFVAL #undef DDRC_ADDRMAP6_LPDDR3_6GB_12GB_SHIFT #undef DDRC_ADDRMAP6_LPDDR3_6GB_12GB_MASK -#define DDRC_ADDRMAP6_LPDDR3_6GB_12GB_DEFVAL 0x00000000 -#define DDRC_ADDRMAP6_LPDDR3_6GB_12GB_SHIFT 31 -#define DDRC_ADDRMAP6_LPDDR3_6GB_12GB_MASK 0x80000000U +#define DDRC_ADDRMAP6_LPDDR3_6GB_12GB_DEFVAL 0x00000000 +#define DDRC_ADDRMAP6_LPDDR3_6GB_12GB_SHIFT 31 +#define DDRC_ADDRMAP6_LPDDR3_6GB_12GB_MASK 0x80000000U -/*Selects the HIF address bit used as row address bit 15. Valid Range: 0 to 11, and 15 Internal Base: 21 The selected HIF addre - s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 15 is set to 0.*/ +/* +* Selects the HIF address bit used as row address bit 15. Valid Range: 0 t + * o 11, and 15 Internal Base: 21 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * row address bit 15 is set to 0. +*/ #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B15_DEFVAL #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B15_SHIFT #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B15_MASK -#define DDRC_ADDRMAP6_ADDRMAP_ROW_B15_DEFVAL 0x00000000 -#define DDRC_ADDRMAP6_ADDRMAP_ROW_B15_SHIFT 24 -#define DDRC_ADDRMAP6_ADDRMAP_ROW_B15_MASK 0x0F000000U +#define DDRC_ADDRMAP6_ADDRMAP_ROW_B15_DEFVAL 0x00000000 +#define DDRC_ADDRMAP6_ADDRMAP_ROW_B15_SHIFT 24 +#define DDRC_ADDRMAP6_ADDRMAP_ROW_B15_MASK 0x0F000000U -/*Selects the HIF address bit used as row address bit 14. Valid Range: 0 to 11, and 15 Internal Base: 20 The selected HIF addre - s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 14 is set to 0.*/ +/* +* Selects the HIF address bit used as row address bit 14. Valid Range: 0 t + * o 11, and 15 Internal Base: 20 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * row address bit 14 is set to 0. +*/ #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B14_DEFVAL #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B14_SHIFT #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B14_MASK -#define DDRC_ADDRMAP6_ADDRMAP_ROW_B14_DEFVAL 0x00000000 -#define DDRC_ADDRMAP6_ADDRMAP_ROW_B14_SHIFT 16 -#define DDRC_ADDRMAP6_ADDRMAP_ROW_B14_MASK 0x000F0000U +#define DDRC_ADDRMAP6_ADDRMAP_ROW_B14_DEFVAL 0x00000000 +#define DDRC_ADDRMAP6_ADDRMAP_ROW_B14_SHIFT 16 +#define DDRC_ADDRMAP6_ADDRMAP_ROW_B14_MASK 0x000F0000U -/*Selects the HIF address bit used as row address bit 13. Valid Range: 0 to 11, and 15 Internal Base: 19 The selected HIF addre - s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 13 is set to 0.*/ +/* +* Selects the HIF address bit used as row address bit 13. Valid Range: 0 t + * o 11, and 15 Internal Base: 19 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * row address bit 13 is set to 0. +*/ #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B13_DEFVAL #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B13_SHIFT #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B13_MASK -#define DDRC_ADDRMAP6_ADDRMAP_ROW_B13_DEFVAL 0x00000000 -#define DDRC_ADDRMAP6_ADDRMAP_ROW_B13_SHIFT 8 -#define DDRC_ADDRMAP6_ADDRMAP_ROW_B13_MASK 0x00000F00U +#define DDRC_ADDRMAP6_ADDRMAP_ROW_B13_DEFVAL 0x00000000 +#define DDRC_ADDRMAP6_ADDRMAP_ROW_B13_SHIFT 8 +#define DDRC_ADDRMAP6_ADDRMAP_ROW_B13_MASK 0x00000F00U -/*Selects the HIF address bit used as row address bit 12. Valid Range: 0 to 11, and 15 Internal Base: 18 The selected HIF addre - s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 12 is set to 0.*/ +/* +* Selects the HIF address bit used as row address bit 12. Valid Range: 0 t + * o 11, and 15 Internal Base: 18 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * row address bit 12 is set to 0. +*/ #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B12_DEFVAL #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B12_SHIFT #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B12_MASK -#define DDRC_ADDRMAP6_ADDRMAP_ROW_B12_DEFVAL 0x00000000 -#define DDRC_ADDRMAP6_ADDRMAP_ROW_B12_SHIFT 0 -#define DDRC_ADDRMAP6_ADDRMAP_ROW_B12_MASK 0x0000000FU +#define DDRC_ADDRMAP6_ADDRMAP_ROW_B12_DEFVAL 0x00000000 +#define DDRC_ADDRMAP6_ADDRMAP_ROW_B12_SHIFT 0 +#define DDRC_ADDRMAP6_ADDRMAP_ROW_B12_MASK 0x0000000FU -/*Selects the HIF address bit used as row address bit 17. Valid Range: 0 to 10, and 15 Internal Base: 23 The selected HIF addre - s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 17 is set to 0.*/ +/* +* Selects the HIF address bit used as row address bit 17. Valid Range: 0 t + * o 10, and 15 Internal Base: 23 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * row address bit 17 is set to 0. +*/ #undef DDRC_ADDRMAP7_ADDRMAP_ROW_B17_DEFVAL #undef DDRC_ADDRMAP7_ADDRMAP_ROW_B17_SHIFT #undef DDRC_ADDRMAP7_ADDRMAP_ROW_B17_MASK -#define DDRC_ADDRMAP7_ADDRMAP_ROW_B17_DEFVAL 0x00000000 -#define DDRC_ADDRMAP7_ADDRMAP_ROW_B17_SHIFT 8 -#define DDRC_ADDRMAP7_ADDRMAP_ROW_B17_MASK 0x00000F00U +#define DDRC_ADDRMAP7_ADDRMAP_ROW_B17_DEFVAL 0x00000000 +#define DDRC_ADDRMAP7_ADDRMAP_ROW_B17_SHIFT 8 +#define DDRC_ADDRMAP7_ADDRMAP_ROW_B17_MASK 0x00000F00U -/*Selects the HIF address bit used as row address bit 16. Valid Range: 0 to 11, and 15 Internal Base: 22 The selected HIF addre - s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 16 is set to 0.*/ +/* +* Selects the HIF address bit used as row address bit 16. Valid Range: 0 t + * o 11, and 15 Internal Base: 22 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * row address bit 16 is set to 0. +*/ #undef DDRC_ADDRMAP7_ADDRMAP_ROW_B16_DEFVAL #undef DDRC_ADDRMAP7_ADDRMAP_ROW_B16_SHIFT #undef DDRC_ADDRMAP7_ADDRMAP_ROW_B16_MASK -#define DDRC_ADDRMAP7_ADDRMAP_ROW_B16_DEFVAL 0x00000000 -#define DDRC_ADDRMAP7_ADDRMAP_ROW_B16_SHIFT 0 -#define DDRC_ADDRMAP7_ADDRMAP_ROW_B16_MASK 0x0000000FU +#define DDRC_ADDRMAP7_ADDRMAP_ROW_B16_DEFVAL 0x00000000 +#define DDRC_ADDRMAP7_ADDRMAP_ROW_B16_SHIFT 0 +#define DDRC_ADDRMAP7_ADDRMAP_ROW_B16_MASK 0x0000000FU -/*Selects the HIF address bits used as bank group address bit 1. Valid Range: 0 to 30, and 31 Internal Base: 3 The selected HIF - address bit for each of the bank group address bits is determined by adding the internal base to the value of this field. If - et to 31, bank group address bit 1 is set to 0.*/ +/* +* Selects the HIF address bits used as bank group address bit 1. Valid Ran + * ge: 0 to 30, and 31 Internal Base: 3 The selected HIF address bit for ea + * ch of the bank group address bits is determined by adding the internal b + * ase to the value of this field. If set to 31, bank group address bit 1 i + * s set to 0. +*/ #undef DDRC_ADDRMAP8_ADDRMAP_BG_B1_DEFVAL #undef DDRC_ADDRMAP8_ADDRMAP_BG_B1_SHIFT #undef DDRC_ADDRMAP8_ADDRMAP_BG_B1_MASK -#define DDRC_ADDRMAP8_ADDRMAP_BG_B1_DEFVAL 0x00000000 -#define DDRC_ADDRMAP8_ADDRMAP_BG_B1_SHIFT 8 -#define DDRC_ADDRMAP8_ADDRMAP_BG_B1_MASK 0x00001F00U +#define DDRC_ADDRMAP8_ADDRMAP_BG_B1_DEFVAL 0x00000000 +#define DDRC_ADDRMAP8_ADDRMAP_BG_B1_SHIFT 8 +#define DDRC_ADDRMAP8_ADDRMAP_BG_B1_MASK 0x00001F00U -/*Selects the HIF address bits used as bank group address bit 0. Valid Range: 0 to 30 Internal Base: 2 The selected HIF address - bit for each of the bank group address bits is determined by adding the internal base to the value of this field.*/ +/* +* Selects the HIF address bits used as bank group address bit 0. Valid Ran + * ge: 0 to 30 Internal Base: 2 The selected HIF address bit for each of th + * e bank group address bits is determined by adding the internal base to t + * he value of this field. +*/ #undef DDRC_ADDRMAP8_ADDRMAP_BG_B0_DEFVAL #undef DDRC_ADDRMAP8_ADDRMAP_BG_B0_SHIFT #undef DDRC_ADDRMAP8_ADDRMAP_BG_B0_MASK -#define DDRC_ADDRMAP8_ADDRMAP_BG_B0_DEFVAL 0x00000000 -#define DDRC_ADDRMAP8_ADDRMAP_BG_B0_SHIFT 0 -#define DDRC_ADDRMAP8_ADDRMAP_BG_B0_MASK 0x0000001FU +#define DDRC_ADDRMAP8_ADDRMAP_BG_B0_DEFVAL 0x00000000 +#define DDRC_ADDRMAP8_ADDRMAP_BG_B0_SHIFT 0 +#define DDRC_ADDRMAP8_ADDRMAP_BG_B0_MASK 0x0000001FU -/*Selects the HIF address bits used as row address bit 5. Valid Range: 0 to 11 Internal Base: 11 The selected HIF address bit f - r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u - ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/ +/* +* Selects the HIF address bits used as row address bit 5. Valid Range: 0 t + * o 11 Internal Base: 11 The selected HIF address bit for each of the row + * address bits is determined by adding the internal base to the value of t + * his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + * _10 is set to value 15. +*/ #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B5_DEFVAL #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B5_SHIFT #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B5_MASK -#define DDRC_ADDRMAP9_ADDRMAP_ROW_B5_DEFVAL 0x00000000 -#define DDRC_ADDRMAP9_ADDRMAP_ROW_B5_SHIFT 24 -#define DDRC_ADDRMAP9_ADDRMAP_ROW_B5_MASK 0x0F000000U +#define DDRC_ADDRMAP9_ADDRMAP_ROW_B5_DEFVAL 0x00000000 +#define DDRC_ADDRMAP9_ADDRMAP_ROW_B5_SHIFT 24 +#define DDRC_ADDRMAP9_ADDRMAP_ROW_B5_MASK 0x0F000000U -/*Selects the HIF address bits used as row address bit 4. Valid Range: 0 to 11 Internal Base: 10 The selected HIF address bit f - r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u - ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/ +/* +* Selects the HIF address bits used as row address bit 4. Valid Range: 0 t + * o 11 Internal Base: 10 The selected HIF address bit for each of the row + * address bits is determined by adding the internal base to the value of t + * his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + * _10 is set to value 15. +*/ #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B4_DEFVAL #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B4_SHIFT #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B4_MASK -#define DDRC_ADDRMAP9_ADDRMAP_ROW_B4_DEFVAL 0x00000000 -#define DDRC_ADDRMAP9_ADDRMAP_ROW_B4_SHIFT 16 -#define DDRC_ADDRMAP9_ADDRMAP_ROW_B4_MASK 0x000F0000U +#define DDRC_ADDRMAP9_ADDRMAP_ROW_B4_DEFVAL 0x00000000 +#define DDRC_ADDRMAP9_ADDRMAP_ROW_B4_SHIFT 16 +#define DDRC_ADDRMAP9_ADDRMAP_ROW_B4_MASK 0x000F0000U -/*Selects the HIF address bits used as row address bit 3. Valid Range: 0 to 11 Internal Base: 9 The selected HIF address bit fo - each of the row address bits is determined by adding the internal base to the value of this field. This register field is us - d only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/ +/* +* Selects the HIF address bits used as row address bit 3. Valid Range: 0 t + * o 11 Internal Base: 9 The selected HIF address bit for each of the row a + * ddress bits is determined by adding the internal base to the value of th + * is field. This register field is used only when ADDRMAP5.addrmap_row_b2_ + * 10 is set to value 15. +*/ #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B3_DEFVAL #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B3_SHIFT #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B3_MASK -#define DDRC_ADDRMAP9_ADDRMAP_ROW_B3_DEFVAL 0x00000000 -#define DDRC_ADDRMAP9_ADDRMAP_ROW_B3_SHIFT 8 -#define DDRC_ADDRMAP9_ADDRMAP_ROW_B3_MASK 0x00000F00U +#define DDRC_ADDRMAP9_ADDRMAP_ROW_B3_DEFVAL 0x00000000 +#define DDRC_ADDRMAP9_ADDRMAP_ROW_B3_SHIFT 8 +#define DDRC_ADDRMAP9_ADDRMAP_ROW_B3_MASK 0x00000F00U -/*Selects the HIF address bits used as row address bit 2. Valid Range: 0 to 11 Internal Base: 8 The selected HIF address bit fo - each of the row address bits is determined by adding the internal base to the value of this field. This register field is us - d only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/ +/* +* Selects the HIF address bits used as row address bit 2. Valid Range: 0 t + * o 11 Internal Base: 8 The selected HIF address bit for each of the row a + * ddress bits is determined by adding the internal base to the value of th + * is field. This register field is used only when ADDRMAP5.addrmap_row_b2_ + * 10 is set to value 15. +*/ #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B2_DEFVAL #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B2_SHIFT #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B2_MASK -#define DDRC_ADDRMAP9_ADDRMAP_ROW_B2_DEFVAL 0x00000000 -#define DDRC_ADDRMAP9_ADDRMAP_ROW_B2_SHIFT 0 -#define DDRC_ADDRMAP9_ADDRMAP_ROW_B2_MASK 0x0000000FU +#define DDRC_ADDRMAP9_ADDRMAP_ROW_B2_DEFVAL 0x00000000 +#define DDRC_ADDRMAP9_ADDRMAP_ROW_B2_SHIFT 0 +#define DDRC_ADDRMAP9_ADDRMAP_ROW_B2_MASK 0x0000000FU -/*Selects the HIF address bits used as row address bit 9. Valid Range: 0 to 11 Internal Base: 15 The selected HIF address bit f - r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u - ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/ +/* +* Selects the HIF address bits used as row address bit 9. Valid Range: 0 t + * o 11 Internal Base: 15 The selected HIF address bit for each of the row + * address bits is determined by adding the internal base to the value of t + * his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + * _10 is set to value 15. +*/ #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B9_DEFVAL #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B9_SHIFT #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B9_MASK -#define DDRC_ADDRMAP10_ADDRMAP_ROW_B9_DEFVAL 0x00000000 -#define DDRC_ADDRMAP10_ADDRMAP_ROW_B9_SHIFT 24 -#define DDRC_ADDRMAP10_ADDRMAP_ROW_B9_MASK 0x0F000000U +#define DDRC_ADDRMAP10_ADDRMAP_ROW_B9_DEFVAL 0x00000000 +#define DDRC_ADDRMAP10_ADDRMAP_ROW_B9_SHIFT 24 +#define DDRC_ADDRMAP10_ADDRMAP_ROW_B9_MASK 0x0F000000U -/*Selects the HIF address bits used as row address bit 8. Valid Range: 0 to 11 Internal Base: 14 The selected HIF address bit f - r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u - ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/ +/* +* Selects the HIF address bits used as row address bit 8. Valid Range: 0 t + * o 11 Internal Base: 14 The selected HIF address bit for each of the row + * address bits is determined by adding the internal base to the value of t + * his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + * _10 is set to value 15. +*/ #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B8_DEFVAL #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B8_SHIFT #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B8_MASK -#define DDRC_ADDRMAP10_ADDRMAP_ROW_B8_DEFVAL 0x00000000 -#define DDRC_ADDRMAP10_ADDRMAP_ROW_B8_SHIFT 16 -#define DDRC_ADDRMAP10_ADDRMAP_ROW_B8_MASK 0x000F0000U +#define DDRC_ADDRMAP10_ADDRMAP_ROW_B8_DEFVAL 0x00000000 +#define DDRC_ADDRMAP10_ADDRMAP_ROW_B8_SHIFT 16 +#define DDRC_ADDRMAP10_ADDRMAP_ROW_B8_MASK 0x000F0000U -/*Selects the HIF address bits used as row address bit 7. Valid Range: 0 to 11 Internal Base: 13 The selected HIF address bit f - r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u - ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/ +/* +* Selects the HIF address bits used as row address bit 7. Valid Range: 0 t + * o 11 Internal Base: 13 The selected HIF address bit for each of the row + * address bits is determined by adding the internal base to the value of t + * his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + * _10 is set to value 15. +*/ #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B7_DEFVAL #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B7_SHIFT #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B7_MASK -#define DDRC_ADDRMAP10_ADDRMAP_ROW_B7_DEFVAL 0x00000000 -#define DDRC_ADDRMAP10_ADDRMAP_ROW_B7_SHIFT 8 -#define DDRC_ADDRMAP10_ADDRMAP_ROW_B7_MASK 0x00000F00U +#define DDRC_ADDRMAP10_ADDRMAP_ROW_B7_DEFVAL 0x00000000 +#define DDRC_ADDRMAP10_ADDRMAP_ROW_B7_SHIFT 8 +#define DDRC_ADDRMAP10_ADDRMAP_ROW_B7_MASK 0x00000F00U -/*Selects the HIF address bits used as row address bit 6. Valid Range: 0 to 11 Internal Base: 12 The selected HIF address bit f - r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u - ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/ +/* +* Selects the HIF address bits used as row address bit 6. Valid Range: 0 t + * o 11 Internal Base: 12 The selected HIF address bit for each of the row + * address bits is determined by adding the internal base to the value of t + * his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + * _10 is set to value 15. +*/ #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B6_DEFVAL #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B6_SHIFT #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B6_MASK -#define DDRC_ADDRMAP10_ADDRMAP_ROW_B6_DEFVAL 0x00000000 -#define DDRC_ADDRMAP10_ADDRMAP_ROW_B6_SHIFT 0 -#define DDRC_ADDRMAP10_ADDRMAP_ROW_B6_MASK 0x0000000FU +#define DDRC_ADDRMAP10_ADDRMAP_ROW_B6_DEFVAL 0x00000000 +#define DDRC_ADDRMAP10_ADDRMAP_ROW_B6_SHIFT 0 +#define DDRC_ADDRMAP10_ADDRMAP_ROW_B6_MASK 0x0000000FU -/*Selects the HIF address bits used as row address bit 10. Valid Range: 0 to 11 Internal Base: 16 The selected HIF address bit - or each of the row address bits is determined by adding the internal base to the value of this field. This register field is - sed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/ +/* +* Selects the HIF address bits used as row address bit 10. Valid Range: 0 + * to 11 Internal Base: 16 The selected HIF address bit for each of the row + * address bits is determined by adding the internal base to the value of + * this field. This register field is used only when ADDRMAP5.addrmap_row_b + * 2_10 is set to value 15. +*/ #undef DDRC_ADDRMAP11_ADDRMAP_ROW_B10_DEFVAL #undef DDRC_ADDRMAP11_ADDRMAP_ROW_B10_SHIFT #undef DDRC_ADDRMAP11_ADDRMAP_ROW_B10_MASK -#define DDRC_ADDRMAP11_ADDRMAP_ROW_B10_DEFVAL -#define DDRC_ADDRMAP11_ADDRMAP_ROW_B10_SHIFT 0 -#define DDRC_ADDRMAP11_ADDRMAP_ROW_B10_MASK 0x0000000FU +#define DDRC_ADDRMAP11_ADDRMAP_ROW_B10_DEFVAL +#define DDRC_ADDRMAP11_ADDRMAP_ROW_B10_SHIFT 0 +#define DDRC_ADDRMAP11_ADDRMAP_ROW_B10_MASK 0x0000000FU -/*Cycles to hold ODT for a write command. The minimum supported value is 2. Recommended values: DDR2: - BL8: 0x5 (DDR2-400/533/ - 67), 0x6 (DDR2-800), 0x7 (DDR2-1066) - BL4: 0x3 (DDR2-400/533/667), 0x4 (DDR2-800), 0x5 (DDR2-1066) DDR3: - BL8: 0x6 DDR4: - - L8: 5 + WR_PREAMBLE + CRC_MODE WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) CRC_MODE = 0 (not CRC mode), 1 - CRC mode) LPDDR3: - BL8: 7 + RU(tODTon(max)/tCK)*/ +/* +* Cycles to hold ODT for a write command. The minimum supported value is 2 + * . Recommended values: DDR2: - BL8: 0x5 (DDR2-400/533/667), 0x6 (DDR2-800 + * ), 0x7 (DDR2-1066) - BL4: 0x3 (DDR2-400/533/667), 0x4 (DDR2-800), 0x5 (D + * DR2-1066) DDR3: - BL8: 0x6 DDR4: - BL8: 5 + WR_PREAMBLE + CRC_MODE WR_PR + * EAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) CRC_MODE = 0 ( + * not CRC mode), 1 (CRC mode) LPDDR3: - BL8: 7 + RU(tODTon(max)/tCK) +*/ #undef DDRC_ODTCFG_WR_ODT_HOLD_DEFVAL #undef DDRC_ODTCFG_WR_ODT_HOLD_SHIFT #undef DDRC_ODTCFG_WR_ODT_HOLD_MASK -#define DDRC_ODTCFG_WR_ODT_HOLD_DEFVAL 0x04000400 -#define DDRC_ODTCFG_WR_ODT_HOLD_SHIFT 24 -#define DDRC_ODTCFG_WR_ODT_HOLD_MASK 0x0F000000U +#define DDRC_ODTCFG_WR_ODT_HOLD_DEFVAL 0x04000400 +#define DDRC_ODTCFG_WR_ODT_HOLD_SHIFT 24 +#define DDRC_ODTCFG_WR_ODT_HOLD_MASK 0x0F000000U -/*The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting must - remain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: - CWL + AL - 3 (DDR2-400/533/ - 67), CWL + AL - 4 (DDR2-800), CWL + AL - 5 (DDR2-1066) If (CWL + AL - 3 < 0), uMCTL2 does not support ODT for write operation - DDR3: - 0x0 DDR4: - DFITMG1.dfi_t_cmd_lat (to adjust for CAL mode) LPDDR3: - WL - 1 - RU(tODTon(max)/tCK))*/ +/* +* The delay, in clock cycles, from issuing a write command to setting ODT + * values associated with that command. ODT setting must remain constant fo + * r the entire time that DQS is driven by the uMCTL2. Recommended values: + * DDR2: - CWL + AL - 3 (DDR2-400/533/667), CWL + AL - 4 (DDR2-800), CWL + + * AL - 5 (DDR2-1066) If (CWL + AL - 3 < 0), uMCTL2 does not support ODT fo + * r write operation. DDR3: - 0x0 DDR4: - DFITMG1.dfi_t_cmd_lat (to adjust + * for CAL mode) LPDDR3: - WL - 1 - RU(tODTon(max)/tCK)) +*/ #undef DDRC_ODTCFG_WR_ODT_DELAY_DEFVAL #undef DDRC_ODTCFG_WR_ODT_DELAY_SHIFT #undef DDRC_ODTCFG_WR_ODT_DELAY_MASK -#define DDRC_ODTCFG_WR_ODT_DELAY_DEFVAL 0x04000400 -#define DDRC_ODTCFG_WR_ODT_DELAY_SHIFT 16 -#define DDRC_ODTCFG_WR_ODT_DELAY_MASK 0x001F0000U +#define DDRC_ODTCFG_WR_ODT_DELAY_DEFVAL 0x04000400 +#define DDRC_ODTCFG_WR_ODT_DELAY_SHIFT 16 +#define DDRC_ODTCFG_WR_ODT_DELAY_MASK 0x001F0000U -/*Cycles to hold ODT for a read command. The minimum supported value is 2. Recommended values: DDR2: - BL8: 0x6 (not DDR2-1066) - 0x7 (DDR2-1066) - BL4: 0x4 (not DDR2-1066), 0x5 (DDR2-1066) DDR3: - BL8 - 0x6 DDR4: - BL8: 5 + RD_PREAMBLE RD_PREAMBLE = 1 ( - tCK write preamble), 2 (2tCK write preamble) LPDDR3: - BL8: 5 + RU(tDQSCK(max)/tCK) - RD(tDQSCK(min)/tCK) + RU(tODTon(max)/tC - )*/ +/* +* Cycles to hold ODT for a read command. The minimum supported value is 2. + * Recommended values: DDR2: - BL8: 0x6 (not DDR2-1066), 0x7 (DDR2-1066) - + * BL4: 0x4 (not DDR2-1066), 0x5 (DDR2-1066) DDR3: - BL8 - 0x6 DDR4: - BL8 + * : 5 + RD_PREAMBLE RD_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write p + * reamble) LPDDR3: - BL8: 5 + RU(tDQSCK(max)/tCK) - RD(tDQSCK(min)/tCK) + + * RU(tODTon(max)/tCK) +*/ #undef DDRC_ODTCFG_RD_ODT_HOLD_DEFVAL #undef DDRC_ODTCFG_RD_ODT_HOLD_SHIFT #undef DDRC_ODTCFG_RD_ODT_HOLD_MASK -#define DDRC_ODTCFG_RD_ODT_HOLD_DEFVAL 0x04000400 -#define DDRC_ODTCFG_RD_ODT_HOLD_SHIFT 8 -#define DDRC_ODTCFG_RD_ODT_HOLD_MASK 0x00000F00U +#define DDRC_ODTCFG_RD_ODT_HOLD_DEFVAL 0x04000400 +#define DDRC_ODTCFG_RD_ODT_HOLD_SHIFT 8 +#define DDRC_ODTCFG_RD_ODT_HOLD_MASK 0x00000F00U -/*The delay, in clock cycles, from issuing a read command to setting ODT values associated with that command. ODT setting must - emain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: - CL + AL - 4 (not DDR2-1066), - CL + AL - 5 (DDR2-1066) If (CL + AL - 4 < 0), uMCTL2 does not support ODT for read operation. DDR3: - CL - CWL DDR4: - CL - C - L - RD_PREAMBLE + WR_PREAMBLE + DFITMG1.dfi_t_cmd_lat (to adjust for CAL mode) WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK - write preamble) RD_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) If (CL - CWL - RD_PREAMBLE + WR_PREAMBLE) < 0, - uMCTL2 does not support ODT for read operation. LPDDR3: - RL + RD(tDQSCK(min)/tCK) - 1 - RU(tODTon(max)/tCK)*/ +/* +* The delay, in clock cycles, from issuing a read command to setting ODT v + * alues associated with that command. ODT setting must remain constant for + * the entire time that DQS is driven by the uMCTL2. Recommended values: D + * DR2: - CL + AL - 4 (not DDR2-1066), CL + AL - 5 (DDR2-1066) If (CL + AL + * - 4 < 0), uMCTL2 does not support ODT for read operation. DDR3: - CL - C + * WL DDR4: - CL - CWL - RD_PREAMBLE + WR_PREAMBLE + DFITMG1.dfi_t_cmd_lat + * (to adjust for CAL mode) WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK + * write preamble) RD_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write pre + * amble) If (CL - CWL - RD_PREAMBLE + WR_PREAMBLE) < 0, uMCTL2 does not su + * pport ODT for read operation. LPDDR3: - RL + RD(tDQSCK(min)/tCK) - 1 - R + * U(tODTon(max)/tCK) +*/ #undef DDRC_ODTCFG_RD_ODT_DELAY_DEFVAL #undef DDRC_ODTCFG_RD_ODT_DELAY_SHIFT #undef DDRC_ODTCFG_RD_ODT_DELAY_MASK -#define DDRC_ODTCFG_RD_ODT_DELAY_DEFVAL 0x04000400 -#define DDRC_ODTCFG_RD_ODT_DELAY_SHIFT 2 -#define DDRC_ODTCFG_RD_ODT_DELAY_MASK 0x0000007CU +#define DDRC_ODTCFG_RD_ODT_DELAY_DEFVAL 0x04000400 +#define DDRC_ODTCFG_RD_ODT_DELAY_SHIFT 2 +#define DDRC_ODTCFG_RD_ODT_DELAY_MASK 0x0000007CU -/*Indicates which remote ODTs must be turned on during a read from rank 1. Each rank has a remote ODT (in the SDRAM) which can - e turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB - etc. For each rank, set its bit to 1 to enable its ODT. Present only in configurations that have 2 or more ranks*/ +/* +* Indicates which remote ODTs must be turned on during a read from rank 1. + * Each rank has a remote ODT (in the SDRAM) which can be turned on by set + * ting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 i + * s controlled by bit next to the LSB, etc. For each rank, set its bit to + * 1 to enable its ODT. Present only in configurations that have 2 or more + * ranks +*/ #undef DDRC_ODTMAP_RANK1_RD_ODT_DEFVAL #undef DDRC_ODTMAP_RANK1_RD_ODT_SHIFT #undef DDRC_ODTMAP_RANK1_RD_ODT_MASK -#define DDRC_ODTMAP_RANK1_RD_ODT_DEFVAL 0x00002211 -#define DDRC_ODTMAP_RANK1_RD_ODT_SHIFT 12 -#define DDRC_ODTMAP_RANK1_RD_ODT_MASK 0x00003000U +#define DDRC_ODTMAP_RANK1_RD_ODT_DEFVAL 0x00002211 +#define DDRC_ODTMAP_RANK1_RD_ODT_SHIFT 12 +#define DDRC_ODTMAP_RANK1_RD_ODT_MASK 0x00003000U -/*Indicates which remote ODTs must be turned on during a write to rank 1. Each rank has a remote ODT (in the SDRAM) which can b - turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB, - etc. For each rank, set its bit to 1 to enable its ODT. Present only in configurations that have 2 or more ranks*/ +/* +* Indicates which remote ODTs must be turned on during a write to rank 1. + * Each rank has a remote ODT (in the SDRAM) which can be turned on by sett + * ing the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is + * controlled by bit next to the LSB, etc. For each rank, set its bit to 1 + * to enable its ODT. Present only in configurations that have 2 or more r + * anks +*/ #undef DDRC_ODTMAP_RANK1_WR_ODT_DEFVAL #undef DDRC_ODTMAP_RANK1_WR_ODT_SHIFT #undef DDRC_ODTMAP_RANK1_WR_ODT_MASK -#define DDRC_ODTMAP_RANK1_WR_ODT_DEFVAL 0x00002211 -#define DDRC_ODTMAP_RANK1_WR_ODT_SHIFT 8 -#define DDRC_ODTMAP_RANK1_WR_ODT_MASK 0x00000300U +#define DDRC_ODTMAP_RANK1_WR_ODT_DEFVAL 0x00002211 +#define DDRC_ODTMAP_RANK1_WR_ODT_SHIFT 8 +#define DDRC_ODTMAP_RANK1_WR_ODT_MASK 0x00000300U -/*Indicates which remote ODTs must be turned on during a read from rank 0. Each rank has a remote ODT (in the SDRAM) which can - e turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB - etc. For each rank, set its bit to 1 to enable its ODT.*/ +/* +* Indicates which remote ODTs must be turned on during a read from rank 0. + * Each rank has a remote ODT (in the SDRAM) which can be turned on by set + * ting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 i + * s controlled by bit next to the LSB, etc. For each rank, set its bit to + * 1 to enable its ODT. +*/ #undef DDRC_ODTMAP_RANK0_RD_ODT_DEFVAL #undef DDRC_ODTMAP_RANK0_RD_ODT_SHIFT #undef DDRC_ODTMAP_RANK0_RD_ODT_MASK -#define DDRC_ODTMAP_RANK0_RD_ODT_DEFVAL 0x00002211 -#define DDRC_ODTMAP_RANK0_RD_ODT_SHIFT 4 -#define DDRC_ODTMAP_RANK0_RD_ODT_MASK 0x00000030U +#define DDRC_ODTMAP_RANK0_RD_ODT_DEFVAL 0x00002211 +#define DDRC_ODTMAP_RANK0_RD_ODT_SHIFT 4 +#define DDRC_ODTMAP_RANK0_RD_ODT_MASK 0x00000030U -/*Indicates which remote ODTs must be turned on during a write to rank 0. Each rank has a remote ODT (in the SDRAM) which can b - turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB, - etc. For each rank, set its bit to 1 to enable its ODT.*/ +/* +* Indicates which remote ODTs must be turned on during a write to rank 0. + * Each rank has a remote ODT (in the SDRAM) which can be turned on by sett + * ing the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is + * controlled by bit next to the LSB, etc. For each rank, set its bit to 1 + * to enable its ODT. +*/ #undef DDRC_ODTMAP_RANK0_WR_ODT_DEFVAL #undef DDRC_ODTMAP_RANK0_WR_ODT_SHIFT #undef DDRC_ODTMAP_RANK0_WR_ODT_MASK -#define DDRC_ODTMAP_RANK0_WR_ODT_DEFVAL 0x00002211 -#define DDRC_ODTMAP_RANK0_WR_ODT_SHIFT 0 -#define DDRC_ODTMAP_RANK0_WR_ODT_MASK 0x00000003U +#define DDRC_ODTMAP_RANK0_WR_ODT_DEFVAL 0x00002211 +#define DDRC_ODTMAP_RANK0_WR_ODT_SHIFT 0 +#define DDRC_ODTMAP_RANK0_WR_ODT_MASK 0x00000003U -/*When the preferred transaction store is empty for these many clock cycles, switch to the alternate transaction store if it is - non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write t - ansaction store is the alternative store. When prefer write over read is set this is reversed. 0x0 is a legal value for this - egister. When set to 0x0, the transaction store switching will happen immediately when the switching conditions become true. - OR PERFORMANCE ONLY*/ +/* +* When the preferred transaction store is empty for these many clock cycle + * s, switch to the alternate transaction store if it is non-empty. The rea + * d transaction store (both high and low priority) is the default preferre + * d transaction store and the write transaction store is the alternative s + * tore. When prefer write over read is set this is reversed. 0x0 is a lega + * l value for this register. When set to 0x0, the transaction store switch + * ing will happen immediately when the switching conditions become true. F + * OR PERFORMANCE ONLY +*/ #undef DDRC_SCHED_RDWR_IDLE_GAP_DEFVAL #undef DDRC_SCHED_RDWR_IDLE_GAP_SHIFT #undef DDRC_SCHED_RDWR_IDLE_GAP_MASK -#define DDRC_SCHED_RDWR_IDLE_GAP_DEFVAL 0x00002005 -#define DDRC_SCHED_RDWR_IDLE_GAP_SHIFT 24 -#define DDRC_SCHED_RDWR_IDLE_GAP_MASK 0x7F000000U +#define DDRC_SCHED_RDWR_IDLE_GAP_DEFVAL 0x00002005 +#define DDRC_SCHED_RDWR_IDLE_GAP_SHIFT 24 +#define DDRC_SCHED_RDWR_IDLE_GAP_MASK 0x7F000000U -/*UNUSED*/ +/* +* UNUSED +*/ #undef DDRC_SCHED_GO2CRITICAL_HYSTERESIS_DEFVAL #undef DDRC_SCHED_GO2CRITICAL_HYSTERESIS_SHIFT #undef DDRC_SCHED_GO2CRITICAL_HYSTERESIS_MASK -#define DDRC_SCHED_GO2CRITICAL_HYSTERESIS_DEFVAL 0x00002005 -#define DDRC_SCHED_GO2CRITICAL_HYSTERESIS_SHIFT 16 -#define DDRC_SCHED_GO2CRITICAL_HYSTERESIS_MASK 0x00FF0000U +#define DDRC_SCHED_GO2CRITICAL_HYSTERESIS_DEFVAL 0x00002005 +#define DDRC_SCHED_GO2CRITICAL_HYSTERESIS_SHIFT 16 +#define DDRC_SCHED_GO2CRITICAL_HYSTERESIS_MASK 0x00FF0000U -/*Number of entries in the low priority transaction store is this value + 1. (MEMC_NO_OF_ENTRY - (SCHED.lpr_num_entries + 1)) i - the number of entries available for the high priority transaction store. Setting this to maximum value allocates all entries - to low priority transaction store. Setting this to 0 allocates 1 entry to low priority transaction store and the rest to high - priority transaction store. Note: In ECC configurations, the numbers of write and low priority read credits issued is one les - than in the non-ECC case. One entry each is reserved in the write and low-priority read CAMs for storing the RMW requests ar - sing out of single bit error correction RMW operation.*/ +/* +* Number of entries in the low priority transaction store is this value + + * 1. (MEMC_NO_OF_ENTRY - (SCHED.lpr_num_entries + 1)) is the number of ent + * ries available for the high priority transaction store. Setting this to + * maximum value allocates all entries to low priority transaction store. S + * etting this to 0 allocates 1 entry to low priority transaction store and + * the rest to high priority transaction store. Note: In ECC configuration + * s, the numbers of write and low priority read credits issued is one less + * than in the non-ECC case. One entry each is reserved in the write and l + * ow-priority read CAMs for storing the RMW requests arising out of single + * bit error correction RMW operation. +*/ #undef DDRC_SCHED_LPR_NUM_ENTRIES_DEFVAL #undef DDRC_SCHED_LPR_NUM_ENTRIES_SHIFT #undef DDRC_SCHED_LPR_NUM_ENTRIES_MASK -#define DDRC_SCHED_LPR_NUM_ENTRIES_DEFVAL 0x00002005 -#define DDRC_SCHED_LPR_NUM_ENTRIES_SHIFT 8 -#define DDRC_SCHED_LPR_NUM_ENTRIES_MASK 0x00003F00U +#define DDRC_SCHED_LPR_NUM_ENTRIES_DEFVAL 0x00002005 +#define DDRC_SCHED_LPR_NUM_ENTRIES_SHIFT 8 +#define DDRC_SCHED_LPR_NUM_ENTRIES_MASK 0x00003F00U -/*If true, bank is kept open only while there are page hit transactions available in the CAM to that bank. The last read or wri - e command in the CAM with a bank and page hit will be executed with auto-precharge if SCHED1.pageclose_timer=0. Even if this - egister set to 1 and SCHED1.pageclose_timer is set to 0, explicit precharge (and not auto-precharge) may be issued in some ca - es where there is a mode switch between Write and Read or between LPR and HPR. The Read and Write commands that are executed - s part of the ECC scrub requests are also executed without auto-precharge. If false, the bank remains open until there is a n - ed to close it (to open a different page, or for page timeout or refresh timeout) - also known as open page policy. The open - age policy can be overridden by setting the per-command-autopre bit on the HIF interface (hif_cmd_autopre). The pageclose fea - ure provids a midway between Open and Close page policies. FOR PERFORMANCE ONLY.*/ +/* +* If true, bank is kept open only while there are page hit transactions av + * ailable in the CAM to that bank. The last read or write command in the C + * AM with a bank and page hit will be executed with auto-precharge if SCHE + * D1.pageclose_timer=0. Even if this register set to 1 and SCHED1.pageclos + * e_timer is set to 0, explicit precharge (and not auto-precharge) may be + * issued in some cases where there is a mode switch between Write and Read + * or between LPR and HPR. The Read and Write commands that are executed a + * s part of the ECC scrub requests are also executed without auto-precharg + * e. If false, the bank remains open until there is a need to close it (to + * open a different page, or for page timeout or refresh timeout) - also k + * nown as open page policy. The open page policy can be overridden by sett + * ing the per-command-autopre bit on the HIF interface (hif_cmd_autopre). + * The pageclose feature provids a midway between Open and Close page polic + * ies. FOR PERFORMANCE ONLY. +*/ #undef DDRC_SCHED_PAGECLOSE_DEFVAL #undef DDRC_SCHED_PAGECLOSE_SHIFT #undef DDRC_SCHED_PAGECLOSE_MASK -#define DDRC_SCHED_PAGECLOSE_DEFVAL 0x00002005 -#define DDRC_SCHED_PAGECLOSE_SHIFT 2 -#define DDRC_SCHED_PAGECLOSE_MASK 0x00000004U +#define DDRC_SCHED_PAGECLOSE_DEFVAL 0x00002005 +#define DDRC_SCHED_PAGECLOSE_SHIFT 2 +#define DDRC_SCHED_PAGECLOSE_MASK 0x00000004U -/*If set then the bank selector prefers writes over reads. FOR DEBUG ONLY.*/ +/* +* If set then the bank selector prefers writes over reads. FOR DEBUG ONLY. +*/ #undef DDRC_SCHED_PREFER_WRITE_DEFVAL #undef DDRC_SCHED_PREFER_WRITE_SHIFT #undef DDRC_SCHED_PREFER_WRITE_MASK -#define DDRC_SCHED_PREFER_WRITE_DEFVAL 0x00002005 -#define DDRC_SCHED_PREFER_WRITE_SHIFT 1 -#define DDRC_SCHED_PREFER_WRITE_MASK 0x00000002U +#define DDRC_SCHED_PREFER_WRITE_DEFVAL 0x00002005 +#define DDRC_SCHED_PREFER_WRITE_SHIFT 1 +#define DDRC_SCHED_PREFER_WRITE_MASK 0x00000002U -/*Active low signal. When asserted ('0'), all incoming transactions are forced to low priority. This implies that all High Prio - ity Read (HPR) and Variable Priority Read commands (VPR) will be treated as Low Priority Read (LPR) commands. On the write si - e, all Variable Priority Write (VPW) commands will be treated as Normal Priority Write (NPW) commands. Forcing the incoming t - ansactions to low priority implicitly turns off Bypass path for read commands. FOR PERFORMANCE ONLY.*/ +/* +* Active low signal. When asserted ('0'), all incoming transactions are fo + * rced to low priority. This implies that all High Priority Read (HPR) and + * Variable Priority Read commands (VPR) will be treated as Low Priority R + * ead (LPR) commands. On the write side, all Variable Priority Write (VPW) + * commands will be treated as Normal Priority Write (NPW) commands. Forci + * ng the incoming transactions to low priority implicitly turns off Bypass + * path for read commands. FOR PERFORMANCE ONLY. +*/ #undef DDRC_SCHED_FORCE_LOW_PRI_N_DEFVAL #undef DDRC_SCHED_FORCE_LOW_PRI_N_SHIFT #undef DDRC_SCHED_FORCE_LOW_PRI_N_MASK -#define DDRC_SCHED_FORCE_LOW_PRI_N_DEFVAL 0x00002005 -#define DDRC_SCHED_FORCE_LOW_PRI_N_SHIFT 0 -#define DDRC_SCHED_FORCE_LOW_PRI_N_MASK 0x00000001U +#define DDRC_SCHED_FORCE_LOW_PRI_N_DEFVAL 0x00002005 +#define DDRC_SCHED_FORCE_LOW_PRI_N_SHIFT 0 +#define DDRC_SCHED_FORCE_LOW_PRI_N_MASK 0x00000001U -/*Number of transactions that are serviced once the LPR queue goes critical is the smaller of: - (a) This number - (b) Number o - transactions available. Unit: Transaction. FOR PERFORMANCE ONLY.*/ +/* +* Number of transactions that are serviced once the LPR queue goes critica + * l is the smaller of: - (a) This number - (b) Number of transactions avai + * lable. Unit: Transaction. FOR PERFORMANCE ONLY. +*/ #undef DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_DEFVAL #undef DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_SHIFT #undef DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_MASK -#define DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_DEFVAL 0x0F00007F -#define DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_SHIFT 24 -#define DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_MASK 0xFF000000U +#define DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_DEFVAL 0x0F00007F +#define DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_SHIFT 24 +#define DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_MASK 0xFF000000U -/*Number of clocks that the LPR queue can be starved before it goes critical. The minimum valid functional value for this regis - er is 0x1. Programming it to 0x0 will disable the starvation functionality; during normal operation, this function should not - be disabled as it will cause excessive latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY.*/ +/* +* Number of clocks that the LPR queue can be starved before it goes critic + * al. The minimum valid functional value for this register is 0x1. Program + * ming it to 0x0 will disable the starvation functionality; during normal + * operation, this function should not be disabled as it will cause excessi + * ve latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY. +*/ #undef DDRC_PERFLPR1_LPR_MAX_STARVE_DEFVAL #undef DDRC_PERFLPR1_LPR_MAX_STARVE_SHIFT #undef DDRC_PERFLPR1_LPR_MAX_STARVE_MASK -#define DDRC_PERFLPR1_LPR_MAX_STARVE_DEFVAL 0x0F00007F -#define DDRC_PERFLPR1_LPR_MAX_STARVE_SHIFT 0 -#define DDRC_PERFLPR1_LPR_MAX_STARVE_MASK 0x0000FFFFU +#define DDRC_PERFLPR1_LPR_MAX_STARVE_DEFVAL 0x0F00007F +#define DDRC_PERFLPR1_LPR_MAX_STARVE_SHIFT 0 +#define DDRC_PERFLPR1_LPR_MAX_STARVE_MASK 0x0000FFFFU -/*Number of transactions that are serviced once the WR queue goes critical is the smaller of: - (a) This number - (b) Number of - transactions available. Unit: Transaction. FOR PERFORMANCE ONLY.*/ +/* +* Number of transactions that are serviced once the WR queue goes critical + * is the smaller of: - (a) This number - (b) Number of transactions avail + * able. Unit: Transaction. FOR PERFORMANCE ONLY. +*/ #undef DDRC_PERFWR1_W_XACT_RUN_LENGTH_DEFVAL #undef DDRC_PERFWR1_W_XACT_RUN_LENGTH_SHIFT #undef DDRC_PERFWR1_W_XACT_RUN_LENGTH_MASK -#define DDRC_PERFWR1_W_XACT_RUN_LENGTH_DEFVAL 0x0F00007F -#define DDRC_PERFWR1_W_XACT_RUN_LENGTH_SHIFT 24 -#define DDRC_PERFWR1_W_XACT_RUN_LENGTH_MASK 0xFF000000U +#define DDRC_PERFWR1_W_XACT_RUN_LENGTH_DEFVAL 0x0F00007F +#define DDRC_PERFWR1_W_XACT_RUN_LENGTH_SHIFT 24 +#define DDRC_PERFWR1_W_XACT_RUN_LENGTH_MASK 0xFF000000U -/*Number of clocks that the WR queue can be starved before it goes critical. The minimum valid functional value for this regist - r is 0x1. Programming it to 0x0 will disable the starvation functionality; during normal operation, this function should not - e disabled as it will cause excessive latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY.*/ +/* +* Number of clocks that the WR queue can be starved before it goes critica + * l. The minimum valid functional value for this register is 0x1. Programm + * ing it to 0x0 will disable the starvation functionality; during normal o + * peration, this function should not be disabled as it will cause excessiv + * e latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY. +*/ #undef DDRC_PERFWR1_W_MAX_STARVE_DEFVAL #undef DDRC_PERFWR1_W_MAX_STARVE_SHIFT #undef DDRC_PERFWR1_W_MAX_STARVE_MASK -#define DDRC_PERFWR1_W_MAX_STARVE_DEFVAL 0x0F00007F -#define DDRC_PERFWR1_W_MAX_STARVE_SHIFT 0 -#define DDRC_PERFWR1_W_MAX_STARVE_MASK 0x0000FFFFU +#define DDRC_PERFWR1_W_MAX_STARVE_DEFVAL 0x0F00007F +#define DDRC_PERFWR1_W_MAX_STARVE_SHIFT 0 +#define DDRC_PERFWR1_W_MAX_STARVE_MASK 0x0000FFFFU -/*All even ranks have the same DQ mapping controled by DQMAP0-4 register as rank 0. This register provides DQ swap function for - all odd ranks to support CRC feature. rank based DQ swapping is: swap bit 0 with 1, swap bit 2 with 3, swap bit 4 with 5 and - wap bit 6 with 7. 1: Disable rank based DQ swapping 0: Enable rank based DQ swapping Present only in designs configured to su - port DDR4.*/ +/* +* DQ nibble map for DQ bits [12-15] Present only in designs configured to + * support DDR4. +*/ +#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_12_15_DEFVAL +#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_12_15_SHIFT +#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_12_15_MASK +#define DDRC_DQMAP0_DQ_NIBBLE_MAP_12_15_DEFVAL 0x00000000 +#define DDRC_DQMAP0_DQ_NIBBLE_MAP_12_15_SHIFT 24 +#define DDRC_DQMAP0_DQ_NIBBLE_MAP_12_15_MASK 0xFF000000U + +/* +* DQ nibble map for DQ bits [8-11] Present only in designs configured to s + * upport DDR4. +*/ +#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_8_11_DEFVAL +#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_8_11_SHIFT +#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_8_11_MASK +#define DDRC_DQMAP0_DQ_NIBBLE_MAP_8_11_DEFVAL 0x00000000 +#define DDRC_DQMAP0_DQ_NIBBLE_MAP_8_11_SHIFT 16 +#define DDRC_DQMAP0_DQ_NIBBLE_MAP_8_11_MASK 0x00FF0000U + +/* +* DQ nibble map for DQ bits [4-7] Present only in designs configured to su + * pport DDR4. +*/ +#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_4_7_DEFVAL +#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_4_7_SHIFT +#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_4_7_MASK +#define DDRC_DQMAP0_DQ_NIBBLE_MAP_4_7_DEFVAL 0x00000000 +#define DDRC_DQMAP0_DQ_NIBBLE_MAP_4_7_SHIFT 8 +#define DDRC_DQMAP0_DQ_NIBBLE_MAP_4_7_MASK 0x0000FF00U + +/* +* DQ nibble map for DQ bits [0-3] Present only in designs configured to su + * pport DDR4. +*/ +#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_0_3_DEFVAL +#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_0_3_SHIFT +#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_0_3_MASK +#define DDRC_DQMAP0_DQ_NIBBLE_MAP_0_3_DEFVAL 0x00000000 +#define DDRC_DQMAP0_DQ_NIBBLE_MAP_0_3_SHIFT 0 +#define DDRC_DQMAP0_DQ_NIBBLE_MAP_0_3_MASK 0x000000FFU + +/* +* DQ nibble map for DQ bits [28-31] Present only in designs configured to + * support DDR4. +*/ +#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_28_31_DEFVAL +#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_28_31_SHIFT +#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_28_31_MASK +#define DDRC_DQMAP1_DQ_NIBBLE_MAP_28_31_DEFVAL 0x00000000 +#define DDRC_DQMAP1_DQ_NIBBLE_MAP_28_31_SHIFT 24 +#define DDRC_DQMAP1_DQ_NIBBLE_MAP_28_31_MASK 0xFF000000U + +/* +* DQ nibble map for DQ bits [24-27] Present only in designs configured to + * support DDR4. +*/ +#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_24_27_DEFVAL +#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_24_27_SHIFT +#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_24_27_MASK +#define DDRC_DQMAP1_DQ_NIBBLE_MAP_24_27_DEFVAL 0x00000000 +#define DDRC_DQMAP1_DQ_NIBBLE_MAP_24_27_SHIFT 16 +#define DDRC_DQMAP1_DQ_NIBBLE_MAP_24_27_MASK 0x00FF0000U + +/* +* DQ nibble map for DQ bits [20-23] Present only in designs configured to + * support DDR4. +*/ +#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_20_23_DEFVAL +#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_20_23_SHIFT +#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_20_23_MASK +#define DDRC_DQMAP1_DQ_NIBBLE_MAP_20_23_DEFVAL 0x00000000 +#define DDRC_DQMAP1_DQ_NIBBLE_MAP_20_23_SHIFT 8 +#define DDRC_DQMAP1_DQ_NIBBLE_MAP_20_23_MASK 0x0000FF00U + +/* +* DQ nibble map for DQ bits [16-19] Present only in designs configured to + * support DDR4. +*/ +#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_16_19_DEFVAL +#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_16_19_SHIFT +#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_16_19_MASK +#define DDRC_DQMAP1_DQ_NIBBLE_MAP_16_19_DEFVAL 0x00000000 +#define DDRC_DQMAP1_DQ_NIBBLE_MAP_16_19_SHIFT 0 +#define DDRC_DQMAP1_DQ_NIBBLE_MAP_16_19_MASK 0x000000FFU + +/* +* DQ nibble map for DQ bits [44-47] Present only in designs configured to + * support DDR4. +*/ +#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_44_47_DEFVAL +#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_44_47_SHIFT +#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_44_47_MASK +#define DDRC_DQMAP2_DQ_NIBBLE_MAP_44_47_DEFVAL 0x00000000 +#define DDRC_DQMAP2_DQ_NIBBLE_MAP_44_47_SHIFT 24 +#define DDRC_DQMAP2_DQ_NIBBLE_MAP_44_47_MASK 0xFF000000U + +/* +* DQ nibble map for DQ bits [40-43] Present only in designs configured to + * support DDR4. +*/ +#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_40_43_DEFVAL +#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_40_43_SHIFT +#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_40_43_MASK +#define DDRC_DQMAP2_DQ_NIBBLE_MAP_40_43_DEFVAL 0x00000000 +#define DDRC_DQMAP2_DQ_NIBBLE_MAP_40_43_SHIFT 16 +#define DDRC_DQMAP2_DQ_NIBBLE_MAP_40_43_MASK 0x00FF0000U + +/* +* DQ nibble map for DQ bits [36-39] Present only in designs configured to + * support DDR4. +*/ +#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_36_39_DEFVAL +#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_36_39_SHIFT +#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_36_39_MASK +#define DDRC_DQMAP2_DQ_NIBBLE_MAP_36_39_DEFVAL 0x00000000 +#define DDRC_DQMAP2_DQ_NIBBLE_MAP_36_39_SHIFT 8 +#define DDRC_DQMAP2_DQ_NIBBLE_MAP_36_39_MASK 0x0000FF00U + +/* +* DQ nibble map for DQ bits [32-35] Present only in designs configured to + * support DDR4. +*/ +#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_32_35_DEFVAL +#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_32_35_SHIFT +#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_32_35_MASK +#define DDRC_DQMAP2_DQ_NIBBLE_MAP_32_35_DEFVAL 0x00000000 +#define DDRC_DQMAP2_DQ_NIBBLE_MAP_32_35_SHIFT 0 +#define DDRC_DQMAP2_DQ_NIBBLE_MAP_32_35_MASK 0x000000FFU + +/* +* DQ nibble map for DQ bits [60-63] Present only in designs configured to + * support DDR4. +*/ +#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_60_63_DEFVAL +#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_60_63_SHIFT +#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_60_63_MASK +#define DDRC_DQMAP3_DQ_NIBBLE_MAP_60_63_DEFVAL 0x00000000 +#define DDRC_DQMAP3_DQ_NIBBLE_MAP_60_63_SHIFT 24 +#define DDRC_DQMAP3_DQ_NIBBLE_MAP_60_63_MASK 0xFF000000U + +/* +* DQ nibble map for DQ bits [56-59] Present only in designs configured to + * support DDR4. +*/ +#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_56_59_DEFVAL +#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_56_59_SHIFT +#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_56_59_MASK +#define DDRC_DQMAP3_DQ_NIBBLE_MAP_56_59_DEFVAL 0x00000000 +#define DDRC_DQMAP3_DQ_NIBBLE_MAP_56_59_SHIFT 16 +#define DDRC_DQMAP3_DQ_NIBBLE_MAP_56_59_MASK 0x00FF0000U + +/* +* DQ nibble map for DQ bits [52-55] Present only in designs configured to + * support DDR4. +*/ +#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_52_55_DEFVAL +#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_52_55_SHIFT +#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_52_55_MASK +#define DDRC_DQMAP3_DQ_NIBBLE_MAP_52_55_DEFVAL 0x00000000 +#define DDRC_DQMAP3_DQ_NIBBLE_MAP_52_55_SHIFT 8 +#define DDRC_DQMAP3_DQ_NIBBLE_MAP_52_55_MASK 0x0000FF00U + +/* +* DQ nibble map for DQ bits [48-51] Present only in designs configured to + * support DDR4. +*/ +#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_48_51_DEFVAL +#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_48_51_SHIFT +#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_48_51_MASK +#define DDRC_DQMAP3_DQ_NIBBLE_MAP_48_51_DEFVAL 0x00000000 +#define DDRC_DQMAP3_DQ_NIBBLE_MAP_48_51_SHIFT 0 +#define DDRC_DQMAP3_DQ_NIBBLE_MAP_48_51_MASK 0x000000FFU + +/* +* DQ nibble map for DIMM ECC check bits [4-7] Present only in designs conf + * igured to support DDR4. +*/ +#undef DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_4_7_DEFVAL +#undef DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_4_7_SHIFT +#undef DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_4_7_MASK +#define DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_4_7_DEFVAL 0x00000000 +#define DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_4_7_SHIFT 8 +#define DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_4_7_MASK 0x0000FF00U + +/* +* DQ nibble map for DIMM ECC check bits [0-3] Present only in designs conf + * igured to support DDR4. +*/ +#undef DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_0_3_DEFVAL +#undef DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_0_3_SHIFT +#undef DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_0_3_MASK +#define DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_0_3_DEFVAL 0x00000000 +#define DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_0_3_SHIFT 0 +#define DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_0_3_MASK 0x000000FFU + +/* +* All even ranks have the same DQ mapping controled by DQMAP0-4 register a + * s rank 0. This register provides DQ swap function for all odd ranks to s + * upport CRC feature. rank based DQ swapping is: swap bit 0 with 1, swap b + * it 2 with 3, swap bit 4 with 5 and swap bit 6 with 7. 1: Disable rank ba + * sed DQ swapping 0: Enable rank based DQ swapping Present only in designs + * configured to support DDR4. +*/ #undef DDRC_DQMAP5_DIS_DQ_RANK_SWAP_DEFVAL #undef DDRC_DQMAP5_DIS_DQ_RANK_SWAP_SHIFT #undef DDRC_DQMAP5_DIS_DQ_RANK_SWAP_MASK -#define DDRC_DQMAP5_DIS_DQ_RANK_SWAP_DEFVAL -#define DDRC_DQMAP5_DIS_DQ_RANK_SWAP_SHIFT 0 -#define DDRC_DQMAP5_DIS_DQ_RANK_SWAP_MASK 0x00000001U +#define DDRC_DQMAP5_DIS_DQ_RANK_SWAP_DEFVAL +#define DDRC_DQMAP5_DIS_DQ_RANK_SWAP_SHIFT 0 +#define DDRC_DQMAP5_DIS_DQ_RANK_SWAP_MASK 0x00000001U -/*When this is set to '0', auto-precharge is disabled for the flushed command in a collision case. Collision cases are write fo - lowed by read to same address, read followed by write to same address, or write followed by write to same address with DBG0.d - s_wc bit = 1 (where same address comparisons exclude the two address bits representing critical word). FOR DEBUG ONLY.*/ +/* +* When this is set to '0', auto-precharge is disabled for the flushed comm + * and in a collision case. Collision cases are write followed by read to s + * ame address, read followed by write to same address, or write followed b + * y write to same address with DBG0.dis_wc bit = 1 (where same address com + * parisons exclude the two address bits representing critical word). FOR D + * EBUG ONLY. +*/ #undef DDRC_DBG0_DIS_COLLISION_PAGE_OPT_DEFVAL #undef DDRC_DBG0_DIS_COLLISION_PAGE_OPT_SHIFT #undef DDRC_DBG0_DIS_COLLISION_PAGE_OPT_MASK -#define DDRC_DBG0_DIS_COLLISION_PAGE_OPT_DEFVAL 0x00000000 -#define DDRC_DBG0_DIS_COLLISION_PAGE_OPT_SHIFT 4 -#define DDRC_DBG0_DIS_COLLISION_PAGE_OPT_MASK 0x00000010U +#define DDRC_DBG0_DIS_COLLISION_PAGE_OPT_DEFVAL 0x00000000 +#define DDRC_DBG0_DIS_COLLISION_PAGE_OPT_SHIFT 4 +#define DDRC_DBG0_DIS_COLLISION_PAGE_OPT_MASK 0x00000010U -/*When 1, disable write combine. FOR DEBUG ONLY*/ +/* +* When 1, disable write combine. FOR DEBUG ONLY +*/ #undef DDRC_DBG0_DIS_WC_DEFVAL #undef DDRC_DBG0_DIS_WC_SHIFT #undef DDRC_DBG0_DIS_WC_MASK -#define DDRC_DBG0_DIS_WC_DEFVAL 0x00000000 -#define DDRC_DBG0_DIS_WC_SHIFT 0 -#define DDRC_DBG0_DIS_WC_MASK 0x00000001U +#define DDRC_DBG0_DIS_WC_DEFVAL 0x00000000 +#define DDRC_DBG0_DIS_WC_SHIFT 0 +#define DDRC_DBG0_DIS_WC_MASK 0x00000001U -/*Setting this register bit to 1 allows refresh and ZQCS commands to be triggered from hardware via the IOs ext_*. If set to 1, - the fields DBGCMD.zq_calib_short and DBGCMD.rank*_refresh have no function, and are ignored by the uMCTL2 logic. Setting this - register bit to 0 allows refresh and ZQCS to be triggered from software, via the fields DBGCMD.zq_calib_short and DBGCMD.rank - _refresh. If set to 0, the hardware pins ext_* have no function, and are ignored by the uMCTL2 logic. This register is static - and may only be changed when the DDRC reset signal, core_ddrc_rstn, is asserted (0).*/ +/* +* Setting this register bit to 1 allows refresh and ZQCS commands to be tr + * iggered from hardware via the IOs ext_*. If set to 1, the fields DBGCMD. + * zq_calib_short and DBGCMD.rank*_refresh have no function, and are ignore + * d by the uMCTL2 logic. Setting this register bit to 0 allows refresh and + * ZQCS to be triggered from software, via the fields DBGCMD.zq_calib_shor + * t and DBGCMD.rank*_refresh. If set to 0, the hardware pins ext_* have no + * function, and are ignored by the uMCTL2 logic. This register is static, + * and may only be changed when the DDRC reset signal, core_ddrc_rstn, is + * asserted (0). +*/ #undef DDRC_DBGCMD_HW_REF_ZQ_EN_DEFVAL #undef DDRC_DBGCMD_HW_REF_ZQ_EN_SHIFT #undef DDRC_DBGCMD_HW_REF_ZQ_EN_MASK -#define DDRC_DBGCMD_HW_REF_ZQ_EN_DEFVAL 0x00000000 -#define DDRC_DBGCMD_HW_REF_ZQ_EN_SHIFT 31 -#define DDRC_DBGCMD_HW_REF_ZQ_EN_MASK 0x80000000U +#define DDRC_DBGCMD_HW_REF_ZQ_EN_DEFVAL 0x00000000 +#define DDRC_DBGCMD_HW_REF_ZQ_EN_SHIFT 31 +#define DDRC_DBGCMD_HW_REF_ZQ_EN_MASK 0x80000000U -/*Setting this register bit to 1 indicates to the uMCTL2 to issue a dfi_ctrlupd_req to the PHY. When this request is stored in - he uMCTL2, the bit is automatically cleared. This operation must only be performed when DFIUPD0.dis_auto_ctrlupd=1.*/ +/* +* Setting this register bit to 1 indicates to the uMCTL2 to issue a dfi_ct + * rlupd_req to the PHY. When this request is stored in the uMCTL2, the bit + * is automatically cleared. This operation must only be performed when DF + * IUPD0.dis_auto_ctrlupd=1. +*/ #undef DDRC_DBGCMD_CTRLUPD_DEFVAL #undef DDRC_DBGCMD_CTRLUPD_SHIFT #undef DDRC_DBGCMD_CTRLUPD_MASK -#define DDRC_DBGCMD_CTRLUPD_DEFVAL 0x00000000 -#define DDRC_DBGCMD_CTRLUPD_SHIFT 5 -#define DDRC_DBGCMD_CTRLUPD_MASK 0x00000020U +#define DDRC_DBGCMD_CTRLUPD_DEFVAL 0x00000000 +#define DDRC_DBGCMD_CTRLUPD_SHIFT 5 +#define DDRC_DBGCMD_CTRLUPD_MASK 0x00000020U -/*Setting this register bit to 1 indicates to the uMCTL2 to issue a ZQCS (ZQ calibration short)/MPC(ZQ calibration) command to - he SDRAM. When this request is stored in the uMCTL2, the bit is automatically cleared. This operation can be performed only w - en ZQCTL0.dis_auto_zq=1. It is recommended NOT to set this register bit if in Init operating mode. This register bit is ignor - d when in Self-Refresh(except LPDDR4) and SR-Powerdown(LPDDR4) and Deep power-down operating modes and Maximum Power Saving M - de.*/ +/* +* Setting this register bit to 1 indicates to the uMCTL2 to issue a ZQCS ( + * ZQ calibration short)/MPC(ZQ calibration) command to the SDRAM. When thi + * s request is stored in the uMCTL2, the bit is automatically cleared. Thi + * s operation can be performed only when ZQCTL0.dis_auto_zq=1. It is recom + * mended NOT to set this register bit if in Init operating mode. This regi + * ster bit is ignored when in Self-Refresh(except LPDDR4) and SR-Powerdown + * (LPDDR4) and Deep power-down operating modes and Maximum Power Saving Mo + * de. +*/ #undef DDRC_DBGCMD_ZQ_CALIB_SHORT_DEFVAL #undef DDRC_DBGCMD_ZQ_CALIB_SHORT_SHIFT #undef DDRC_DBGCMD_ZQ_CALIB_SHORT_MASK -#define DDRC_DBGCMD_ZQ_CALIB_SHORT_DEFVAL 0x00000000 -#define DDRC_DBGCMD_ZQ_CALIB_SHORT_SHIFT 4 -#define DDRC_DBGCMD_ZQ_CALIB_SHORT_MASK 0x00000010U +#define DDRC_DBGCMD_ZQ_CALIB_SHORT_DEFVAL 0x00000000 +#define DDRC_DBGCMD_ZQ_CALIB_SHORT_SHIFT 4 +#define DDRC_DBGCMD_ZQ_CALIB_SHORT_MASK 0x00000010U -/*Setting this register bit to 1 indicates to the uMCTL2 to issue a refresh to rank 1. Writing to this bit causes DBGSTAT.rank1 - refresh_busy to be set. When DBGSTAT.rank1_refresh_busy is cleared, the command has been stored in uMCTL2. This operation can - be performed only when RFSHCTL3.dis_auto_refresh=1. It is recommended NOT to set this register bit if in Init or Deep power-d - wn operating modes or Maximum Power Saving Mode.*/ +/* +* Setting this register bit to 1 indicates to the uMCTL2 to issue a refres + * h to rank 1. Writing to this bit causes DBGSTAT.rank1_refresh_busy to be + * set. When DBGSTAT.rank1_refresh_busy is cleared, the command has been s + * tored in uMCTL2. This operation can be performed only when RFSHCTL3.dis_ + * auto_refresh=1. It is recommended NOT to set this register bit if in Ini + * t or Deep power-down operating modes or Maximum Power Saving Mode. +*/ #undef DDRC_DBGCMD_RANK1_REFRESH_DEFVAL #undef DDRC_DBGCMD_RANK1_REFRESH_SHIFT #undef DDRC_DBGCMD_RANK1_REFRESH_MASK -#define DDRC_DBGCMD_RANK1_REFRESH_DEFVAL 0x00000000 -#define DDRC_DBGCMD_RANK1_REFRESH_SHIFT 1 -#define DDRC_DBGCMD_RANK1_REFRESH_MASK 0x00000002U +#define DDRC_DBGCMD_RANK1_REFRESH_DEFVAL 0x00000000 +#define DDRC_DBGCMD_RANK1_REFRESH_SHIFT 1 +#define DDRC_DBGCMD_RANK1_REFRESH_MASK 0x00000002U -/*Setting this register bit to 1 indicates to the uMCTL2 to issue a refresh to rank 0. Writing to this bit causes DBGSTAT.rank0 - refresh_busy to be set. When DBGSTAT.rank0_refresh_busy is cleared, the command has been stored in uMCTL2. This operation can - be performed only when RFSHCTL3.dis_auto_refresh=1. It is recommended NOT to set this register bit if in Init or Deep power-d - wn operating modes or Maximum Power Saving Mode.*/ +/* +* Setting this register bit to 1 indicates to the uMCTL2 to issue a refres + * h to rank 0. Writing to this bit causes DBGSTAT.rank0_refresh_busy to be + * set. When DBGSTAT.rank0_refresh_busy is cleared, the command has been s + * tored in uMCTL2. This operation can be performed only when RFSHCTL3.dis_ + * auto_refresh=1. It is recommended NOT to set this register bit if in Ini + * t or Deep power-down operating modes or Maximum Power Saving Mode. +*/ #undef DDRC_DBGCMD_RANK0_REFRESH_DEFVAL #undef DDRC_DBGCMD_RANK0_REFRESH_SHIFT #undef DDRC_DBGCMD_RANK0_REFRESH_MASK -#define DDRC_DBGCMD_RANK0_REFRESH_DEFVAL 0x00000000 -#define DDRC_DBGCMD_RANK0_REFRESH_SHIFT 0 -#define DDRC_DBGCMD_RANK0_REFRESH_MASK 0x00000001U +#define DDRC_DBGCMD_RANK0_REFRESH_DEFVAL 0x00000000 +#define DDRC_DBGCMD_RANK0_REFRESH_SHIFT 0 +#define DDRC_DBGCMD_RANK0_REFRESH_MASK 0x00000001U -/*Enable quasi-dynamic register programming outside reset. Program register to 0 to enable quasi-dynamic programming. Set back - egister to 1 once programming is done.*/ +/* +* Enable quasi-dynamic register programming outside reset. Program registe + * r to 0 to enable quasi-dynamic programming. Set back register to 1 once + * programming is done. +*/ #undef DDRC_SWCTL_SW_DONE_DEFVAL #undef DDRC_SWCTL_SW_DONE_SHIFT #undef DDRC_SWCTL_SW_DONE_MASK -#define DDRC_SWCTL_SW_DONE_DEFVAL -#define DDRC_SWCTL_SW_DONE_SHIFT 0 -#define DDRC_SWCTL_SW_DONE_MASK 0x00000001U +#define DDRC_SWCTL_SW_DONE_DEFVAL +#define DDRC_SWCTL_SW_DONE_SHIFT 0 +#define DDRC_SWCTL_SW_DONE_MASK 0x00000001U -/*Burst length expansion mode. By default (i.e. bl_exp_mode==0) XPI expands every AXI burst into multiple HIF commands, using t - e memory burst length as a unit. If set to 1, then XPI will use half of the memory burst length as a unit. This applies to bo - h reads and writes. When MSTR.data_bus_width==00, setting bl_exp_mode to 1 has no effect. This can be used in cases where Par - ial Writes is enabled (UMCTL2_PARTIAL_WR=1) and DBG0.dis_wc=1, in order to avoid or minimize t_ccd_l penalty in DDR4 and t_cc - _mw penalty in LPDDR4. Note that if DBICTL.reg_ddrc_dm_en=0, functionality is not supported in the following cases: - UMCTL2_ - ARTIAL_WR=0 - UMCTL2_PARTIAL_WR=1, MSTR.reg_ddrc_data_bus_width=01, MEMC_BURST_LENGTH=8 and MSTR.reg_ddrc_burst_rdwr=1000 (LP - DR4 only) - UMCTL2_PARTIAL_WR=1, MSTR.reg_ddrc_data_bus_width=01, MEMC_BURST_LENGTH=4 and MSTR.reg_ddrc_burst_rdwr=0100 (DDR4 - only), with either MSTR.reg_ddrc_burstchop=0 or CRCPARCTL1.reg_ddrc_crc_enable=1 Functionality is also not supported if Share - -AC is enabled*/ +/* +* Burst length expansion mode. By default (i.e. bl_exp_mode==0) XPI expand + * s every AXI burst into multiple HIF commands, using the memory burst len + * gth as a unit. If set to 1, then XPI will use half of the memory burst l + * ength as a unit. This applies to both reads and writes. When MSTR.data_b + * us_width==00, setting bl_exp_mode to 1 has no effect. This can be used i + * n cases where Partial Writes is enabled (UMCTL2_PARTIAL_WR=1) and DBG0.d + * is_wc=1, in order to avoid or minimize t_ccd_l penalty in DDR4 and t_ccd + * _mw penalty in LPDDR4. Note that if DBICTL.reg_ddrc_dm_en=0, functionali + * ty is not supported in the following cases: - UMCTL2_PARTIAL_WR=0 - UMCT + * L2_PARTIAL_WR=1, MSTR.reg_ddrc_data_bus_width=01, MEMC_BURST_LENGTH=8 an + * d MSTR.reg_ddrc_burst_rdwr=1000 (LPDDR4 only) - UMCTL2_PARTIAL_WR=1, MST + * R.reg_ddrc_data_bus_width=01, MEMC_BURST_LENGTH=4 and MSTR.reg_ddrc_burs + * t_rdwr=0100 (DDR4 only), with either MSTR.reg_ddrc_burstchop=0 or CRCPAR + * CTL1.reg_ddrc_crc_enable=1 Functionality is also not supported if Shared + * -AC is enabled +*/ #undef DDRC_PCCFG_BL_EXP_MODE_DEFVAL #undef DDRC_PCCFG_BL_EXP_MODE_SHIFT #undef DDRC_PCCFG_BL_EXP_MODE_MASK -#define DDRC_PCCFG_BL_EXP_MODE_DEFVAL 0x00000000 -#define DDRC_PCCFG_BL_EXP_MODE_SHIFT 8 -#define DDRC_PCCFG_BL_EXP_MODE_MASK 0x00000100U +#define DDRC_PCCFG_BL_EXP_MODE_DEFVAL 0x00000000 +#define DDRC_PCCFG_BL_EXP_MODE_SHIFT 8 +#define DDRC_PCCFG_BL_EXP_MODE_MASK 0x00000100U -/*Page match four limit. If set to 1, limits the number of consecutive same page DDRC transactions that can be granted by the P - rt Arbiter to four when Page Match feature is enabled. If set to 0, there is no limit imposed on number of consecutive same p - ge DDRC transactions.*/ +/* +* Page match four limit. If set to 1, limits the number of consecutive sam + * e page DDRC transactions that can be granted by the Port Arbiter to four + * when Page Match feature is enabled. If set to 0, there is no limit impo + * sed on number of consecutive same page DDRC transactions. +*/ #undef DDRC_PCCFG_PAGEMATCH_LIMIT_DEFVAL #undef DDRC_PCCFG_PAGEMATCH_LIMIT_SHIFT #undef DDRC_PCCFG_PAGEMATCH_LIMIT_MASK -#define DDRC_PCCFG_PAGEMATCH_LIMIT_DEFVAL 0x00000000 -#define DDRC_PCCFG_PAGEMATCH_LIMIT_SHIFT 4 -#define DDRC_PCCFG_PAGEMATCH_LIMIT_MASK 0x00000010U +#define DDRC_PCCFG_PAGEMATCH_LIMIT_DEFVAL 0x00000000 +#define DDRC_PCCFG_PAGEMATCH_LIMIT_SHIFT 4 +#define DDRC_PCCFG_PAGEMATCH_LIMIT_MASK 0x00000010U -/*If set to 1 (enabled), sets co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals going to DDRC based - n urgent input (awurgent, arurgent) coming from AXI master. If set to 0 (disabled), co_gs_go2critical_wr and co_gs_go2critica - _lpr/co_gs_go2critical_hpr signals at DDRC are driven to 1b'0.*/ +/* +* If set to 1 (enabled), sets co_gs_go2critical_wr and co_gs_go2critical_l + * pr/co_gs_go2critical_hpr signals going to DDRC based on urgent input (aw + * urgent, arurgent) coming from AXI master. If set to 0 (disabled), co_gs_ + * go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals a + * t DDRC are driven to 1b'0. +*/ #undef DDRC_PCCFG_GO2CRITICAL_EN_DEFVAL #undef DDRC_PCCFG_GO2CRITICAL_EN_SHIFT #undef DDRC_PCCFG_GO2CRITICAL_EN_MASK -#define DDRC_PCCFG_GO2CRITICAL_EN_DEFVAL 0x00000000 -#define DDRC_PCCFG_GO2CRITICAL_EN_SHIFT 0 -#define DDRC_PCCFG_GO2CRITICAL_EN_MASK 0x00000001U +#define DDRC_PCCFG_GO2CRITICAL_EN_DEFVAL 0x00000000 +#define DDRC_PCCFG_GO2CRITICAL_EN_SHIFT 0 +#define DDRC_PCCFG_GO2CRITICAL_EN_MASK 0x00000001U -/*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register.*/ +/* +* If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. +*/ #undef DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_DEFVAL #undef DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_SHIFT #undef DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_MASK -#define DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_DEFVAL 0x00000000 -#define DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_SHIFT 14 -#define DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_MASK 0x00004000U +#define DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_SHIFT 14 +#define DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_MASK 0x00004000U -/*If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG. - o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add - ess handshaking (it is not associated with any particular command).*/ +/* +* If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + * bled and arurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + * urgent signal can be asserted anytime and as long as required which is i + * ndependent of address handshaking (it is not associated with any particu + * lar command). +*/ #undef DDRC_PCFGR_0_RD_PORT_URGENT_EN_DEFVAL #undef DDRC_PCFGR_0_RD_PORT_URGENT_EN_SHIFT #undef DDRC_PCFGR_0_RD_PORT_URGENT_EN_MASK -#define DDRC_PCFGR_0_RD_PORT_URGENT_EN_DEFVAL 0x00000000 -#define DDRC_PCFGR_0_RD_PORT_URGENT_EN_SHIFT 13 -#define DDRC_PCFGR_0_RD_PORT_URGENT_EN_MASK 0x00002000U +#define DDRC_PCFGR_0_RD_PORT_URGENT_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_0_RD_PORT_URGENT_EN_SHIFT 13 +#define DDRC_PCFGR_0_RD_PORT_URGENT_EN_MASK 0x00002000U -/*If set to 1, enables aging function for the read channel of the port.*/ +/* +* If set to 1, enables aging function for the read channel of the port. +*/ #undef DDRC_PCFGR_0_RD_PORT_AGING_EN_DEFVAL #undef DDRC_PCFGR_0_RD_PORT_AGING_EN_SHIFT #undef DDRC_PCFGR_0_RD_PORT_AGING_EN_MASK -#define DDRC_PCFGR_0_RD_PORT_AGING_EN_DEFVAL 0x00000000 -#define DDRC_PCFGR_0_RD_PORT_AGING_EN_SHIFT 12 -#define DDRC_PCFGR_0_RD_PORT_AGING_EN_MASK 0x00001000U +#define DDRC_PCFGR_0_RD_PORT_AGING_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_0_RD_PORT_AGING_EN_SHIFT 12 +#define DDRC_PCFGR_0_RD_PORT_AGING_EN_MASK 0x00001000U -/*Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g - ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority - will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre - ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the - aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st - ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w - ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D - RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: - he two LSBs of this register field are tied internally to 2'b00.*/ +/* +* Determines the initial load value of read aging counters. These counters + * will be parallel loaded after reset, or after each grant to the corresp + * onding port. The aging counters down-count every clock cycle where the p + * ort is requesting but not granted. The higher significant 5-bits of the + * read aging counter sets the priority of the read channel of a given port + * . Port's priority will increase as the higher significant 5-bits of the + * counter starts to decrease. When the aging counter becomes 0, the corres + * ponding port channel will have the highest priority level (timeout condi + * tion - Priority0). For multi-port configurations, the aging counters can + * not be used to set port priorities when external dynamic priority inputs + * (arqos) are enabled (timeout is still applicable). For single port conf + * igurations, the aging counters are only used when they timeout (become 0 + * ) to force read-write direction switching. In this case, external dynami + * c priority input, arqos (for reads only) can still be used to set the DD + * RC read priority (2 priority levels: low priority read - LPR, high prior + * ity read - HPR) on a command by command basis. Note: The two LSBs of thi + * s register field are tied internally to 2'b00. +*/ #undef DDRC_PCFGR_0_RD_PORT_PRIORITY_DEFVAL #undef DDRC_PCFGR_0_RD_PORT_PRIORITY_SHIFT #undef DDRC_PCFGR_0_RD_PORT_PRIORITY_MASK -#define DDRC_PCFGR_0_RD_PORT_PRIORITY_DEFVAL 0x00000000 -#define DDRC_PCFGR_0_RD_PORT_PRIORITY_SHIFT 0 -#define DDRC_PCFGR_0_RD_PORT_PRIORITY_MASK 0x000003FFU +#define DDRC_PCFGR_0_RD_PORT_PRIORITY_DEFVAL 0x00000000 +#define DDRC_PCFGR_0_RD_PORT_PRIORITY_SHIFT 0 +#define DDRC_PCFGR_0_RD_PORT_PRIORITY_MASK 0x000003FFU -/*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register.*/ +/* +* If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. +*/ #undef DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_DEFVAL #undef DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_SHIFT #undef DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_MASK -#define DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_DEFVAL 0x00004000 -#define DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_SHIFT 14 -#define DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_MASK 0x00004000U +#define DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_SHIFT 14 +#define DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_MASK 0x00004000U -/*If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register - Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is - not associated with any particular command).*/ +/* +* If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + * bled and awurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + * serted anytime and as long as required which is independent of address h + * andshaking (it is not associated with any particular command). +*/ #undef DDRC_PCFGW_0_WR_PORT_URGENT_EN_DEFVAL #undef DDRC_PCFGW_0_WR_PORT_URGENT_EN_SHIFT #undef DDRC_PCFGW_0_WR_PORT_URGENT_EN_MASK -#define DDRC_PCFGW_0_WR_PORT_URGENT_EN_DEFVAL 0x00004000 -#define DDRC_PCFGW_0_WR_PORT_URGENT_EN_SHIFT 13 -#define DDRC_PCFGW_0_WR_PORT_URGENT_EN_MASK 0x00002000U +#define DDRC_PCFGW_0_WR_PORT_URGENT_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_0_WR_PORT_URGENT_EN_SHIFT 13 +#define DDRC_PCFGW_0_WR_PORT_URGENT_EN_MASK 0x00002000U -/*If set to 1, enables aging function for the write channel of the port.*/ +/* +* If set to 1, enables aging function for the write channel of the port. +*/ #undef DDRC_PCFGW_0_WR_PORT_AGING_EN_DEFVAL #undef DDRC_PCFGW_0_WR_PORT_AGING_EN_SHIFT #undef DDRC_PCFGW_0_WR_PORT_AGING_EN_MASK -#define DDRC_PCFGW_0_WR_PORT_AGING_EN_DEFVAL 0x00004000 -#define DDRC_PCFGW_0_WR_PORT_AGING_EN_SHIFT 12 -#define DDRC_PCFGW_0_WR_PORT_AGING_EN_MASK 0x00001000U +#define DDRC_PCFGW_0_WR_PORT_AGING_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_0_WR_PORT_AGING_EN_SHIFT 12 +#define DDRC_PCFGW_0_WR_PORT_AGING_EN_MASK 0x00001000U -/*Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each - rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port - s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0 - the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno - be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For - ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch - ng. Note: The two LSBs of this register field are tied internally to 2'b00.*/ +/* +* Determines the initial load value of write aging counters. These counter + * s will be parallel loaded after reset, or after each grant to the corres + * ponding port. The aging counters down-count every clock cycle where the + * port is requesting but not granted. The higher significant 5-bits of the + * write aging counter sets the initial priority of the write channel of a + * given port. Port's priority will increase as the higher significant 5-b + * its of the counter starts to decrease. When the aging counter becomes 0, + * the corresponding port channel will have the highest priority level. Fo + * r multi-port configurations, the aging counters cannot be used to set po + * rt priorities when external dynamic priority inputs (awqos) are enabled + * (timeout is still applicable). For single port configurations, the aging + * counters are only used when they timeout (become 0) to force read-write + * direction switching. Note: The two LSBs of this register field are tied + * internally to 2'b00. +*/ #undef DDRC_PCFGW_0_WR_PORT_PRIORITY_DEFVAL #undef DDRC_PCFGW_0_WR_PORT_PRIORITY_SHIFT #undef DDRC_PCFGW_0_WR_PORT_PRIORITY_MASK -#define DDRC_PCFGW_0_WR_PORT_PRIORITY_DEFVAL 0x00004000 -#define DDRC_PCFGW_0_WR_PORT_PRIORITY_SHIFT 0 -#define DDRC_PCFGW_0_WR_PORT_PRIORITY_MASK 0x000003FFU +#define DDRC_PCFGW_0_WR_PORT_PRIORITY_DEFVAL 0x00004000 +#define DDRC_PCFGW_0_WR_PORT_PRIORITY_SHIFT 0 +#define DDRC_PCFGW_0_WR_PORT_PRIORITY_MASK 0x000003FFU -/*Enables port n.*/ +/* +* Enables port n. +*/ #undef DDRC_PCTRL_0_PORT_EN_DEFVAL #undef DDRC_PCTRL_0_PORT_EN_SHIFT #undef DDRC_PCTRL_0_PORT_EN_MASK -#define DDRC_PCTRL_0_PORT_EN_DEFVAL -#define DDRC_PCTRL_0_PORT_EN_SHIFT 0 -#define DDRC_PCTRL_0_PORT_EN_MASK 0x00000001U +#define DDRC_PCTRL_0_PORT_EN_DEFVAL +#define DDRC_PCTRL_0_PORT_EN_SHIFT 0 +#define DDRC_PCTRL_0_PORT_EN_MASK 0x00000001U -/*This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf - gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is - disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/ +/* +* This bitfield indicates the traffic class of region 1. Valid values are: + * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + * maps to the blue address queue. In this case, valid values are 0: LPR a + * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. +*/ #undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_DEFVAL #undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_SHIFT #undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_MASK -#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_DEFVAL 0x00000000 -#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_SHIFT 20 -#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_MASK 0x00300000U +#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_DEFVAL 0x00000000 +#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_SHIFT 20 +#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_MASK 0x00300000U -/*This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi - urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i - disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/ +/* +* This bitfield indicates the traffic class of region 0. Valid values are: + * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + * maps to the blue address queue. In this case, valid values are: 0: LPR + * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. +*/ #undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_DEFVAL #undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_SHIFT #undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_MASK -#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_DEFVAL 0x00000000 -#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_SHIFT 16 -#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_MASK 0x00030000U +#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_DEFVAL 0x00000000 +#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_SHIFT 16 +#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_MASK 0x00030000U -/*Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d - al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio - ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc - values.*/ +/* +* Separation level1 indicating the end of region0 mapping; start of region + * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + * lues are used directly as port priorities, where the higher the value co + * rresponds to higher port priority. All of the map_level* registers must + * be set to distinct values. +*/ #undef DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_DEFVAL #undef DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_SHIFT #undef DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_MASK -#define DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_DEFVAL 0x00000000 -#define DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_SHIFT 0 -#define DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_MASK 0x0000000FU +#define DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_DEFVAL 0x00000000 +#define DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_SHIFT 0 +#define DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_MASK 0x0000000FU -/*Specifies the timeout value for transactions mapped to the red address queue.*/ +/* +* Specifies the timeout value for transactions mapped to the red address q + * ueue. +*/ #undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_DEFVAL #undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_SHIFT #undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_MASK -#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_DEFVAL 0x00000000 -#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_SHIFT 16 -#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_MASK 0x07FF0000U +#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_DEFVAL 0x00000000 +#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_SHIFT 16 +#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_MASK 0x07FF0000U -/*Specifies the timeout value for transactions mapped to the blue address queue.*/ +/* +* Specifies the timeout value for transactions mapped to the blue address + * queue. +*/ #undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_DEFVAL #undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_SHIFT #undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_MASK -#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_DEFVAL 0x00000000 -#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_SHIFT 0 -#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_MASK 0x000007FFU +#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_DEFVAL 0x00000000 +#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_SHIFT 0 +#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_MASK 0x000007FFU -/*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register.*/ +/* +* If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. +*/ #undef DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_DEFVAL #undef DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_SHIFT #undef DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_MASK -#define DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_DEFVAL 0x00000000 -#define DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_SHIFT 14 -#define DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_MASK 0x00004000U +#define DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_SHIFT 14 +#define DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_MASK 0x00004000U -/*If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG. - o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add - ess handshaking (it is not associated with any particular command).*/ +/* +* If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + * bled and arurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + * urgent signal can be asserted anytime and as long as required which is i + * ndependent of address handshaking (it is not associated with any particu + * lar command). +*/ #undef DDRC_PCFGR_1_RD_PORT_URGENT_EN_DEFVAL #undef DDRC_PCFGR_1_RD_PORT_URGENT_EN_SHIFT #undef DDRC_PCFGR_1_RD_PORT_URGENT_EN_MASK -#define DDRC_PCFGR_1_RD_PORT_URGENT_EN_DEFVAL 0x00000000 -#define DDRC_PCFGR_1_RD_PORT_URGENT_EN_SHIFT 13 -#define DDRC_PCFGR_1_RD_PORT_URGENT_EN_MASK 0x00002000U +#define DDRC_PCFGR_1_RD_PORT_URGENT_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_1_RD_PORT_URGENT_EN_SHIFT 13 +#define DDRC_PCFGR_1_RD_PORT_URGENT_EN_MASK 0x00002000U -/*If set to 1, enables aging function for the read channel of the port.*/ +/* +* If set to 1, enables aging function for the read channel of the port. +*/ #undef DDRC_PCFGR_1_RD_PORT_AGING_EN_DEFVAL #undef DDRC_PCFGR_1_RD_PORT_AGING_EN_SHIFT #undef DDRC_PCFGR_1_RD_PORT_AGING_EN_MASK -#define DDRC_PCFGR_1_RD_PORT_AGING_EN_DEFVAL 0x00000000 -#define DDRC_PCFGR_1_RD_PORT_AGING_EN_SHIFT 12 -#define DDRC_PCFGR_1_RD_PORT_AGING_EN_MASK 0x00001000U +#define DDRC_PCFGR_1_RD_PORT_AGING_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_1_RD_PORT_AGING_EN_SHIFT 12 +#define DDRC_PCFGR_1_RD_PORT_AGING_EN_MASK 0x00001000U -/*Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g - ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority - will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre - ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the - aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st - ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w - ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D - RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: - he two LSBs of this register field are tied internally to 2'b00.*/ +/* +* Determines the initial load value of read aging counters. These counters + * will be parallel loaded after reset, or after each grant to the corresp + * onding port. The aging counters down-count every clock cycle where the p + * ort is requesting but not granted. The higher significant 5-bits of the + * read aging counter sets the priority of the read channel of a given port + * . Port's priority will increase as the higher significant 5-bits of the + * counter starts to decrease. When the aging counter becomes 0, the corres + * ponding port channel will have the highest priority level (timeout condi + * tion - Priority0). For multi-port configurations, the aging counters can + * not be used to set port priorities when external dynamic priority inputs + * (arqos) are enabled (timeout is still applicable). For single port conf + * igurations, the aging counters are only used when they timeout (become 0 + * ) to force read-write direction switching. In this case, external dynami + * c priority input, arqos (for reads only) can still be used to set the DD + * RC read priority (2 priority levels: low priority read - LPR, high prior + * ity read - HPR) on a command by command basis. Note: The two LSBs of thi + * s register field are tied internally to 2'b00. +*/ #undef DDRC_PCFGR_1_RD_PORT_PRIORITY_DEFVAL #undef DDRC_PCFGR_1_RD_PORT_PRIORITY_SHIFT #undef DDRC_PCFGR_1_RD_PORT_PRIORITY_MASK -#define DDRC_PCFGR_1_RD_PORT_PRIORITY_DEFVAL 0x00000000 -#define DDRC_PCFGR_1_RD_PORT_PRIORITY_SHIFT 0 -#define DDRC_PCFGR_1_RD_PORT_PRIORITY_MASK 0x000003FFU +#define DDRC_PCFGR_1_RD_PORT_PRIORITY_DEFVAL 0x00000000 +#define DDRC_PCFGR_1_RD_PORT_PRIORITY_SHIFT 0 +#define DDRC_PCFGR_1_RD_PORT_PRIORITY_MASK 0x000003FFU -/*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register.*/ +/* +* If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. +*/ #undef DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_DEFVAL #undef DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_SHIFT #undef DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_MASK -#define DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_DEFVAL 0x00004000 -#define DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_SHIFT 14 -#define DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_MASK 0x00004000U +#define DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_SHIFT 14 +#define DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_MASK 0x00004000U -/*If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register - Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is - not associated with any particular command).*/ +/* +* If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + * bled and awurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + * serted anytime and as long as required which is independent of address h + * andshaking (it is not associated with any particular command). +*/ #undef DDRC_PCFGW_1_WR_PORT_URGENT_EN_DEFVAL #undef DDRC_PCFGW_1_WR_PORT_URGENT_EN_SHIFT #undef DDRC_PCFGW_1_WR_PORT_URGENT_EN_MASK -#define DDRC_PCFGW_1_WR_PORT_URGENT_EN_DEFVAL 0x00004000 -#define DDRC_PCFGW_1_WR_PORT_URGENT_EN_SHIFT 13 -#define DDRC_PCFGW_1_WR_PORT_URGENT_EN_MASK 0x00002000U +#define DDRC_PCFGW_1_WR_PORT_URGENT_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_1_WR_PORT_URGENT_EN_SHIFT 13 +#define DDRC_PCFGW_1_WR_PORT_URGENT_EN_MASK 0x00002000U -/*If set to 1, enables aging function for the write channel of the port.*/ +/* +* If set to 1, enables aging function for the write channel of the port. +*/ #undef DDRC_PCFGW_1_WR_PORT_AGING_EN_DEFVAL #undef DDRC_PCFGW_1_WR_PORT_AGING_EN_SHIFT #undef DDRC_PCFGW_1_WR_PORT_AGING_EN_MASK -#define DDRC_PCFGW_1_WR_PORT_AGING_EN_DEFVAL 0x00004000 -#define DDRC_PCFGW_1_WR_PORT_AGING_EN_SHIFT 12 -#define DDRC_PCFGW_1_WR_PORT_AGING_EN_MASK 0x00001000U +#define DDRC_PCFGW_1_WR_PORT_AGING_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_1_WR_PORT_AGING_EN_SHIFT 12 +#define DDRC_PCFGW_1_WR_PORT_AGING_EN_MASK 0x00001000U -/*Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each - rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port - s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0 - the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno - be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For - ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch - ng. Note: The two LSBs of this register field are tied internally to 2'b00.*/ +/* +* Determines the initial load value of write aging counters. These counter + * s will be parallel loaded after reset, or after each grant to the corres + * ponding port. The aging counters down-count every clock cycle where the + * port is requesting but not granted. The higher significant 5-bits of the + * write aging counter sets the initial priority of the write channel of a + * given port. Port's priority will increase as the higher significant 5-b + * its of the counter starts to decrease. When the aging counter becomes 0, + * the corresponding port channel will have the highest priority level. Fo + * r multi-port configurations, the aging counters cannot be used to set po + * rt priorities when external dynamic priority inputs (awqos) are enabled + * (timeout is still applicable). For single port configurations, the aging + * counters are only used when they timeout (become 0) to force read-write + * direction switching. Note: The two LSBs of this register field are tied + * internally to 2'b00. +*/ #undef DDRC_PCFGW_1_WR_PORT_PRIORITY_DEFVAL #undef DDRC_PCFGW_1_WR_PORT_PRIORITY_SHIFT #undef DDRC_PCFGW_1_WR_PORT_PRIORITY_MASK -#define DDRC_PCFGW_1_WR_PORT_PRIORITY_DEFVAL 0x00004000 -#define DDRC_PCFGW_1_WR_PORT_PRIORITY_SHIFT 0 -#define DDRC_PCFGW_1_WR_PORT_PRIORITY_MASK 0x000003FFU +#define DDRC_PCFGW_1_WR_PORT_PRIORITY_DEFVAL 0x00004000 +#define DDRC_PCFGW_1_WR_PORT_PRIORITY_SHIFT 0 +#define DDRC_PCFGW_1_WR_PORT_PRIORITY_MASK 0x000003FFU -/*Enables port n.*/ +/* +* Enables port n. +*/ #undef DDRC_PCTRL_1_PORT_EN_DEFVAL #undef DDRC_PCTRL_1_PORT_EN_SHIFT #undef DDRC_PCTRL_1_PORT_EN_MASK -#define DDRC_PCTRL_1_PORT_EN_DEFVAL -#define DDRC_PCTRL_1_PORT_EN_SHIFT 0 -#define DDRC_PCTRL_1_PORT_EN_MASK 0x00000001U +#define DDRC_PCTRL_1_PORT_EN_DEFVAL +#define DDRC_PCTRL_1_PORT_EN_SHIFT 0 +#define DDRC_PCTRL_1_PORT_EN_MASK 0x00000001U -/*This bitfield indicates the traffic class of region2. For dual address queue configurations, region2 maps to the red address - ueue. Valid values are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and traffic class of region2 - s set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/ +/* +* This bitfield indicates the traffic class of region2. For dual address q + * ueue configurations, region2 maps to the red address queue. Valid values + * are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN + * = 0) and traffic class of region2 is set to 1 (VPR), VPR traffic is ali + * ased to LPR traffic. +*/ #undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_DEFVAL #undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_SHIFT #undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_MASK -#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_DEFVAL 0x02000E00 -#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_SHIFT 24 -#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_MASK 0x03000000U +#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_DEFVAL 0x02000E00 +#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_SHIFT 24 +#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_MASK 0x03000000U -/*This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf - gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is - disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/ +/* +* This bitfield indicates the traffic class of region 1. Valid values are: + * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + * maps to the blue address queue. In this case, valid values are 0: LPR a + * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. +*/ #undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_DEFVAL #undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_SHIFT #undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_MASK -#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_DEFVAL 0x02000E00 -#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_SHIFT 20 -#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_MASK 0x00300000U +#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_DEFVAL 0x02000E00 +#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_SHIFT 20 +#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_MASK 0x00300000U -/*This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi - urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i - disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/ +/* +* This bitfield indicates the traffic class of region 0. Valid values are: + * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + * maps to the blue address queue. In this case, valid values are: 0: LPR + * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. +*/ #undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_DEFVAL #undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_SHIFT #undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_MASK -#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_DEFVAL 0x02000E00 -#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_SHIFT 16 -#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_MASK 0x00030000U +#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_DEFVAL 0x02000E00 +#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_SHIFT 16 +#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_MASK 0x00030000U -/*Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (le - el1 + 1) to 14 which corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note that for PA, arqos values are used - directly as port priorities, where the higher the value corresponds to higher port priority. All of the map_level* registers - ust be set to distinct values.*/ +/* +* Separation level2 indicating the end of region1 mapping; start of region + * 1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 whi + * ch corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note + * that for PA, arqos values are used directly as port priorities, where t + * he higher the value corresponds to higher port priority. All of the map_ + * level* registers must be set to distinct values. +*/ #undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_DEFVAL #undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_SHIFT #undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_MASK -#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_DEFVAL 0x02000E00 -#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_SHIFT 8 -#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_MASK 0x00000F00U +#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_DEFVAL 0x02000E00 +#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_SHIFT 8 +#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_MASK 0x00000F00U -/*Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d - al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio - ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc - values.*/ +/* +* Separation level1 indicating the end of region0 mapping; start of region + * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + * lues are used directly as port priorities, where the higher the value co + * rresponds to higher port priority. All of the map_level* registers must + * be set to distinct values. +*/ #undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_DEFVAL #undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_SHIFT #undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_MASK -#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_DEFVAL 0x02000E00 -#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_SHIFT 0 -#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_MASK 0x0000000FU +#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_DEFVAL 0x02000E00 +#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_SHIFT 0 +#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_MASK 0x0000000FU -/*Specifies the timeout value for transactions mapped to the red address queue.*/ +/* +* Specifies the timeout value for transactions mapped to the red address q + * ueue. +*/ #undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_DEFVAL #undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_SHIFT #undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_MASK -#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_DEFVAL 0x00000000 -#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_SHIFT 16 -#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_MASK 0x07FF0000U +#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_DEFVAL 0x00000000 +#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_SHIFT 16 +#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_MASK 0x07FF0000U -/*Specifies the timeout value for transactions mapped to the blue address queue.*/ +/* +* Specifies the timeout value for transactions mapped to the blue address + * queue. +*/ #undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_DEFVAL #undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_SHIFT #undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_MASK -#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_DEFVAL 0x00000000 -#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_SHIFT 0 -#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_MASK 0x000007FFU +#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_DEFVAL 0x00000000 +#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_SHIFT 0 +#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_MASK 0x000007FFU -/*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register.*/ +/* +* If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. +*/ #undef DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_DEFVAL #undef DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_SHIFT #undef DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_MASK -#define DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_DEFVAL 0x00000000 -#define DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_SHIFT 14 -#define DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_MASK 0x00004000U +#define DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_SHIFT 14 +#define DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_MASK 0x00004000U -/*If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG. - o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add - ess handshaking (it is not associated with any particular command).*/ +/* +* If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + * bled and arurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + * urgent signal can be asserted anytime and as long as required which is i + * ndependent of address handshaking (it is not associated with any particu + * lar command). +*/ #undef DDRC_PCFGR_2_RD_PORT_URGENT_EN_DEFVAL #undef DDRC_PCFGR_2_RD_PORT_URGENT_EN_SHIFT #undef DDRC_PCFGR_2_RD_PORT_URGENT_EN_MASK -#define DDRC_PCFGR_2_RD_PORT_URGENT_EN_DEFVAL 0x00000000 -#define DDRC_PCFGR_2_RD_PORT_URGENT_EN_SHIFT 13 -#define DDRC_PCFGR_2_RD_PORT_URGENT_EN_MASK 0x00002000U +#define DDRC_PCFGR_2_RD_PORT_URGENT_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_2_RD_PORT_URGENT_EN_SHIFT 13 +#define DDRC_PCFGR_2_RD_PORT_URGENT_EN_MASK 0x00002000U -/*If set to 1, enables aging function for the read channel of the port.*/ +/* +* If set to 1, enables aging function for the read channel of the port. +*/ #undef DDRC_PCFGR_2_RD_PORT_AGING_EN_DEFVAL #undef DDRC_PCFGR_2_RD_PORT_AGING_EN_SHIFT #undef DDRC_PCFGR_2_RD_PORT_AGING_EN_MASK -#define DDRC_PCFGR_2_RD_PORT_AGING_EN_DEFVAL 0x00000000 -#define DDRC_PCFGR_2_RD_PORT_AGING_EN_SHIFT 12 -#define DDRC_PCFGR_2_RD_PORT_AGING_EN_MASK 0x00001000U +#define DDRC_PCFGR_2_RD_PORT_AGING_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_2_RD_PORT_AGING_EN_SHIFT 12 +#define DDRC_PCFGR_2_RD_PORT_AGING_EN_MASK 0x00001000U -/*Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g - ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority - will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre - ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the - aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st - ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w - ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D - RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: - he two LSBs of this register field are tied internally to 2'b00.*/ +/* +* Determines the initial load value of read aging counters. These counters + * will be parallel loaded after reset, or after each grant to the corresp + * onding port. The aging counters down-count every clock cycle where the p + * ort is requesting but not granted. The higher significant 5-bits of the + * read aging counter sets the priority of the read channel of a given port + * . Port's priority will increase as the higher significant 5-bits of the + * counter starts to decrease. When the aging counter becomes 0, the corres + * ponding port channel will have the highest priority level (timeout condi + * tion - Priority0). For multi-port configurations, the aging counters can + * not be used to set port priorities when external dynamic priority inputs + * (arqos) are enabled (timeout is still applicable). For single port conf + * igurations, the aging counters are only used when they timeout (become 0 + * ) to force read-write direction switching. In this case, external dynami + * c priority input, arqos (for reads only) can still be used to set the DD + * RC read priority (2 priority levels: low priority read - LPR, high prior + * ity read - HPR) on a command by command basis. Note: The two LSBs of thi + * s register field are tied internally to 2'b00. +*/ #undef DDRC_PCFGR_2_RD_PORT_PRIORITY_DEFVAL #undef DDRC_PCFGR_2_RD_PORT_PRIORITY_SHIFT #undef DDRC_PCFGR_2_RD_PORT_PRIORITY_MASK -#define DDRC_PCFGR_2_RD_PORT_PRIORITY_DEFVAL 0x00000000 -#define DDRC_PCFGR_2_RD_PORT_PRIORITY_SHIFT 0 -#define DDRC_PCFGR_2_RD_PORT_PRIORITY_MASK 0x000003FFU +#define DDRC_PCFGR_2_RD_PORT_PRIORITY_DEFVAL 0x00000000 +#define DDRC_PCFGR_2_RD_PORT_PRIORITY_SHIFT 0 +#define DDRC_PCFGR_2_RD_PORT_PRIORITY_MASK 0x000003FFU -/*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register.*/ +/* +* If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. +*/ #undef DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_DEFVAL #undef DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_SHIFT #undef DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_MASK -#define DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_DEFVAL 0x00004000 -#define DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_SHIFT 14 -#define DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_MASK 0x00004000U +#define DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_SHIFT 14 +#define DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_MASK 0x00004000U -/*If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register - Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is - not associated with any particular command).*/ +/* +* If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + * bled and awurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + * serted anytime and as long as required which is independent of address h + * andshaking (it is not associated with any particular command). +*/ #undef DDRC_PCFGW_2_WR_PORT_URGENT_EN_DEFVAL #undef DDRC_PCFGW_2_WR_PORT_URGENT_EN_SHIFT #undef DDRC_PCFGW_2_WR_PORT_URGENT_EN_MASK -#define DDRC_PCFGW_2_WR_PORT_URGENT_EN_DEFVAL 0x00004000 -#define DDRC_PCFGW_2_WR_PORT_URGENT_EN_SHIFT 13 -#define DDRC_PCFGW_2_WR_PORT_URGENT_EN_MASK 0x00002000U +#define DDRC_PCFGW_2_WR_PORT_URGENT_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_2_WR_PORT_URGENT_EN_SHIFT 13 +#define DDRC_PCFGW_2_WR_PORT_URGENT_EN_MASK 0x00002000U -/*If set to 1, enables aging function for the write channel of the port.*/ +/* +* If set to 1, enables aging function for the write channel of the port. +*/ #undef DDRC_PCFGW_2_WR_PORT_AGING_EN_DEFVAL #undef DDRC_PCFGW_2_WR_PORT_AGING_EN_SHIFT #undef DDRC_PCFGW_2_WR_PORT_AGING_EN_MASK -#define DDRC_PCFGW_2_WR_PORT_AGING_EN_DEFVAL 0x00004000 -#define DDRC_PCFGW_2_WR_PORT_AGING_EN_SHIFT 12 -#define DDRC_PCFGW_2_WR_PORT_AGING_EN_MASK 0x00001000U +#define DDRC_PCFGW_2_WR_PORT_AGING_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_2_WR_PORT_AGING_EN_SHIFT 12 +#define DDRC_PCFGW_2_WR_PORT_AGING_EN_MASK 0x00001000U -/*Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each - rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port - s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0 - the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno - be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For - ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch - ng. Note: The two LSBs of this register field are tied internally to 2'b00.*/ +/* +* Determines the initial load value of write aging counters. These counter + * s will be parallel loaded after reset, or after each grant to the corres + * ponding port. The aging counters down-count every clock cycle where the + * port is requesting but not granted. The higher significant 5-bits of the + * write aging counter sets the initial priority of the write channel of a + * given port. Port's priority will increase as the higher significant 5-b + * its of the counter starts to decrease. When the aging counter becomes 0, + * the corresponding port channel will have the highest priority level. Fo + * r multi-port configurations, the aging counters cannot be used to set po + * rt priorities when external dynamic priority inputs (awqos) are enabled + * (timeout is still applicable). For single port configurations, the aging + * counters are only used when they timeout (become 0) to force read-write + * direction switching. Note: The two LSBs of this register field are tied + * internally to 2'b00. +*/ #undef DDRC_PCFGW_2_WR_PORT_PRIORITY_DEFVAL #undef DDRC_PCFGW_2_WR_PORT_PRIORITY_SHIFT #undef DDRC_PCFGW_2_WR_PORT_PRIORITY_MASK -#define DDRC_PCFGW_2_WR_PORT_PRIORITY_DEFVAL 0x00004000 -#define DDRC_PCFGW_2_WR_PORT_PRIORITY_SHIFT 0 -#define DDRC_PCFGW_2_WR_PORT_PRIORITY_MASK 0x000003FFU +#define DDRC_PCFGW_2_WR_PORT_PRIORITY_DEFVAL 0x00004000 +#define DDRC_PCFGW_2_WR_PORT_PRIORITY_SHIFT 0 +#define DDRC_PCFGW_2_WR_PORT_PRIORITY_MASK 0x000003FFU -/*Enables port n.*/ +/* +* Enables port n. +*/ #undef DDRC_PCTRL_2_PORT_EN_DEFVAL #undef DDRC_PCTRL_2_PORT_EN_SHIFT #undef DDRC_PCTRL_2_PORT_EN_MASK -#define DDRC_PCTRL_2_PORT_EN_DEFVAL -#define DDRC_PCTRL_2_PORT_EN_SHIFT 0 -#define DDRC_PCTRL_2_PORT_EN_MASK 0x00000001U +#define DDRC_PCTRL_2_PORT_EN_DEFVAL +#define DDRC_PCTRL_2_PORT_EN_SHIFT 0 +#define DDRC_PCTRL_2_PORT_EN_MASK 0x00000001U -/*This bitfield indicates the traffic class of region2. For dual address queue configurations, region2 maps to the red address - ueue. Valid values are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and traffic class of region2 - s set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/ +/* +* This bitfield indicates the traffic class of region2. For dual address q + * ueue configurations, region2 maps to the red address queue. Valid values + * are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN + * = 0) and traffic class of region2 is set to 1 (VPR), VPR traffic is ali + * ased to LPR traffic. +*/ #undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_DEFVAL #undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_SHIFT #undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_MASK -#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_DEFVAL 0x02000E00 -#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_SHIFT 24 -#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_MASK 0x03000000U +#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_DEFVAL 0x02000E00 +#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_SHIFT 24 +#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_MASK 0x03000000U -/*This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf - gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is - disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/ +/* +* This bitfield indicates the traffic class of region 1. Valid values are: + * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + * maps to the blue address queue. In this case, valid values are 0: LPR a + * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. +*/ #undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_DEFVAL #undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_SHIFT #undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_MASK -#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_DEFVAL 0x02000E00 -#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_SHIFT 20 -#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_MASK 0x00300000U +#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_DEFVAL 0x02000E00 +#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_SHIFT 20 +#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_MASK 0x00300000U -/*This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi - urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i - disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/ +/* +* This bitfield indicates the traffic class of region 0. Valid values are: + * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + * maps to the blue address queue. In this case, valid values are: 0: LPR + * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. +*/ #undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_DEFVAL #undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_SHIFT #undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_MASK -#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_DEFVAL 0x02000E00 -#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_SHIFT 16 -#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_MASK 0x00030000U +#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_DEFVAL 0x02000E00 +#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_SHIFT 16 +#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_MASK 0x00030000U -/*Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (le - el1 + 1) to 14 which corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note that for PA, arqos values are used - directly as port priorities, where the higher the value corresponds to higher port priority. All of the map_level* registers - ust be set to distinct values.*/ +/* +* Separation level2 indicating the end of region1 mapping; start of region + * 1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 whi + * ch corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note + * that for PA, arqos values are used directly as port priorities, where t + * he higher the value corresponds to higher port priority. All of the map_ + * level* registers must be set to distinct values. +*/ #undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_DEFVAL #undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_SHIFT #undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_MASK -#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_DEFVAL 0x02000E00 -#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_SHIFT 8 -#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_MASK 0x00000F00U +#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_DEFVAL 0x02000E00 +#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_SHIFT 8 +#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_MASK 0x00000F00U -/*Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d - al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio - ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc - values.*/ +/* +* Separation level1 indicating the end of region0 mapping; start of region + * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + * lues are used directly as port priorities, where the higher the value co + * rresponds to higher port priority. All of the map_level* registers must + * be set to distinct values. +*/ #undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_DEFVAL #undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_SHIFT #undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_MASK -#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_DEFVAL 0x02000E00 -#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_SHIFT 0 -#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_MASK 0x0000000FU +#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_DEFVAL 0x02000E00 +#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_SHIFT 0 +#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_MASK 0x0000000FU -/*Specifies the timeout value for transactions mapped to the red address queue.*/ +/* +* Specifies the timeout value for transactions mapped to the red address q + * ueue. +*/ #undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_DEFVAL #undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_SHIFT #undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_MASK -#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_DEFVAL 0x00000000 -#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_SHIFT 16 -#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_MASK 0x07FF0000U +#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_DEFVAL 0x00000000 +#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_SHIFT 16 +#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_MASK 0x07FF0000U -/*Specifies the timeout value for transactions mapped to the blue address queue.*/ +/* +* Specifies the timeout value for transactions mapped to the blue address + * queue. +*/ #undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_DEFVAL #undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_SHIFT #undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_MASK -#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_DEFVAL 0x00000000 -#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_SHIFT 0 -#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_MASK 0x000007FFU +#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_DEFVAL 0x00000000 +#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_SHIFT 0 +#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_MASK 0x000007FFU -/*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register.*/ +/* +* If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. +*/ #undef DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_DEFVAL #undef DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_SHIFT #undef DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_MASK -#define DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_DEFVAL 0x00000000 -#define DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_SHIFT 14 -#define DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_MASK 0x00004000U +#define DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_SHIFT 14 +#define DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_MASK 0x00004000U -/*If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG. - o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add - ess handshaking (it is not associated with any particular command).*/ +/* +* If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + * bled and arurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + * urgent signal can be asserted anytime and as long as required which is i + * ndependent of address handshaking (it is not associated with any particu + * lar command). +*/ #undef DDRC_PCFGR_3_RD_PORT_URGENT_EN_DEFVAL #undef DDRC_PCFGR_3_RD_PORT_URGENT_EN_SHIFT #undef DDRC_PCFGR_3_RD_PORT_URGENT_EN_MASK -#define DDRC_PCFGR_3_RD_PORT_URGENT_EN_DEFVAL 0x00000000 -#define DDRC_PCFGR_3_RD_PORT_URGENT_EN_SHIFT 13 -#define DDRC_PCFGR_3_RD_PORT_URGENT_EN_MASK 0x00002000U +#define DDRC_PCFGR_3_RD_PORT_URGENT_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_3_RD_PORT_URGENT_EN_SHIFT 13 +#define DDRC_PCFGR_3_RD_PORT_URGENT_EN_MASK 0x00002000U -/*If set to 1, enables aging function for the read channel of the port.*/ +/* +* If set to 1, enables aging function for the read channel of the port. +*/ #undef DDRC_PCFGR_3_RD_PORT_AGING_EN_DEFVAL #undef DDRC_PCFGR_3_RD_PORT_AGING_EN_SHIFT #undef DDRC_PCFGR_3_RD_PORT_AGING_EN_MASK -#define DDRC_PCFGR_3_RD_PORT_AGING_EN_DEFVAL 0x00000000 -#define DDRC_PCFGR_3_RD_PORT_AGING_EN_SHIFT 12 -#define DDRC_PCFGR_3_RD_PORT_AGING_EN_MASK 0x00001000U +#define DDRC_PCFGR_3_RD_PORT_AGING_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_3_RD_PORT_AGING_EN_SHIFT 12 +#define DDRC_PCFGR_3_RD_PORT_AGING_EN_MASK 0x00001000U -/*Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g - ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority - will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre - ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the - aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st - ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w - ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D - RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: - he two LSBs of this register field are tied internally to 2'b00.*/ +/* +* Determines the initial load value of read aging counters. These counters + * will be parallel loaded after reset, or after each grant to the corresp + * onding port. The aging counters down-count every clock cycle where the p + * ort is requesting but not granted. The higher significant 5-bits of the + * read aging counter sets the priority of the read channel of a given port + * . Port's priority will increase as the higher significant 5-bits of the + * counter starts to decrease. When the aging counter becomes 0, the corres + * ponding port channel will have the highest priority level (timeout condi + * tion - Priority0). For multi-port configurations, the aging counters can + * not be used to set port priorities when external dynamic priority inputs + * (arqos) are enabled (timeout is still applicable). For single port conf + * igurations, the aging counters are only used when they timeout (become 0 + * ) to force read-write direction switching. In this case, external dynami + * c priority input, arqos (for reads only) can still be used to set the DD + * RC read priority (2 priority levels: low priority read - LPR, high prior + * ity read - HPR) on a command by command basis. Note: The two LSBs of thi + * s register field are tied internally to 2'b00. +*/ #undef DDRC_PCFGR_3_RD_PORT_PRIORITY_DEFVAL #undef DDRC_PCFGR_3_RD_PORT_PRIORITY_SHIFT #undef DDRC_PCFGR_3_RD_PORT_PRIORITY_MASK -#define DDRC_PCFGR_3_RD_PORT_PRIORITY_DEFVAL 0x00000000 -#define DDRC_PCFGR_3_RD_PORT_PRIORITY_SHIFT 0 -#define DDRC_PCFGR_3_RD_PORT_PRIORITY_MASK 0x000003FFU +#define DDRC_PCFGR_3_RD_PORT_PRIORITY_DEFVAL 0x00000000 +#define DDRC_PCFGR_3_RD_PORT_PRIORITY_SHIFT 0 +#define DDRC_PCFGR_3_RD_PORT_PRIORITY_MASK 0x000003FFU -/*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register.*/ +/* +* If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. +*/ #undef DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_DEFVAL #undef DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_SHIFT #undef DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_MASK -#define DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_DEFVAL 0x00004000 -#define DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_SHIFT 14 -#define DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_MASK 0x00004000U +#define DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_SHIFT 14 +#define DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_MASK 0x00004000U -/*If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register - Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is - not associated with any particular command).*/ +/* +* If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + * bled and awurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + * serted anytime and as long as required which is independent of address h + * andshaking (it is not associated with any particular command). +*/ #undef DDRC_PCFGW_3_WR_PORT_URGENT_EN_DEFVAL #undef DDRC_PCFGW_3_WR_PORT_URGENT_EN_SHIFT #undef DDRC_PCFGW_3_WR_PORT_URGENT_EN_MASK -#define DDRC_PCFGW_3_WR_PORT_URGENT_EN_DEFVAL 0x00004000 -#define DDRC_PCFGW_3_WR_PORT_URGENT_EN_SHIFT 13 -#define DDRC_PCFGW_3_WR_PORT_URGENT_EN_MASK 0x00002000U +#define DDRC_PCFGW_3_WR_PORT_URGENT_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_3_WR_PORT_URGENT_EN_SHIFT 13 +#define DDRC_PCFGW_3_WR_PORT_URGENT_EN_MASK 0x00002000U -/*If set to 1, enables aging function for the write channel of the port.*/ +/* +* If set to 1, enables aging function for the write channel of the port. +*/ #undef DDRC_PCFGW_3_WR_PORT_AGING_EN_DEFVAL #undef DDRC_PCFGW_3_WR_PORT_AGING_EN_SHIFT #undef DDRC_PCFGW_3_WR_PORT_AGING_EN_MASK -#define DDRC_PCFGW_3_WR_PORT_AGING_EN_DEFVAL 0x00004000 -#define DDRC_PCFGW_3_WR_PORT_AGING_EN_SHIFT 12 -#define DDRC_PCFGW_3_WR_PORT_AGING_EN_MASK 0x00001000U +#define DDRC_PCFGW_3_WR_PORT_AGING_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_3_WR_PORT_AGING_EN_SHIFT 12 +#define DDRC_PCFGW_3_WR_PORT_AGING_EN_MASK 0x00001000U -/*Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each - rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port - s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0 - the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno - be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For - ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch - ng. Note: The two LSBs of this register field are tied internally to 2'b00.*/ +/* +* Determines the initial load value of write aging counters. These counter + * s will be parallel loaded after reset, or after each grant to the corres + * ponding port. The aging counters down-count every clock cycle where the + * port is requesting but not granted. The higher significant 5-bits of the + * write aging counter sets the initial priority of the write channel of a + * given port. Port's priority will increase as the higher significant 5-b + * its of the counter starts to decrease. When the aging counter becomes 0, + * the corresponding port channel will have the highest priority level. Fo + * r multi-port configurations, the aging counters cannot be used to set po + * rt priorities when external dynamic priority inputs (awqos) are enabled + * (timeout is still applicable). For single port configurations, the aging + * counters are only used when they timeout (become 0) to force read-write + * direction switching. Note: The two LSBs of this register field are tied + * internally to 2'b00. +*/ #undef DDRC_PCFGW_3_WR_PORT_PRIORITY_DEFVAL #undef DDRC_PCFGW_3_WR_PORT_PRIORITY_SHIFT #undef DDRC_PCFGW_3_WR_PORT_PRIORITY_MASK -#define DDRC_PCFGW_3_WR_PORT_PRIORITY_DEFVAL 0x00004000 -#define DDRC_PCFGW_3_WR_PORT_PRIORITY_SHIFT 0 -#define DDRC_PCFGW_3_WR_PORT_PRIORITY_MASK 0x000003FFU +#define DDRC_PCFGW_3_WR_PORT_PRIORITY_DEFVAL 0x00004000 +#define DDRC_PCFGW_3_WR_PORT_PRIORITY_SHIFT 0 +#define DDRC_PCFGW_3_WR_PORT_PRIORITY_MASK 0x000003FFU -/*Enables port n.*/ +/* +* Enables port n. +*/ #undef DDRC_PCTRL_3_PORT_EN_DEFVAL #undef DDRC_PCTRL_3_PORT_EN_SHIFT #undef DDRC_PCTRL_3_PORT_EN_MASK -#define DDRC_PCTRL_3_PORT_EN_DEFVAL -#define DDRC_PCTRL_3_PORT_EN_SHIFT 0 -#define DDRC_PCTRL_3_PORT_EN_MASK 0x00000001U +#define DDRC_PCTRL_3_PORT_EN_DEFVAL +#define DDRC_PCTRL_3_PORT_EN_SHIFT 0 +#define DDRC_PCTRL_3_PORT_EN_MASK 0x00000001U -/*This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf - gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is - disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/ +/* +* This bitfield indicates the traffic class of region 1. Valid values are: + * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + * maps to the blue address queue. In this case, valid values are 0: LPR a + * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. +*/ #undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_DEFVAL #undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_SHIFT #undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_MASK -#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_DEFVAL 0x00000000 -#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_SHIFT 20 -#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_MASK 0x00300000U +#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_DEFVAL 0x00000000 +#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_SHIFT 20 +#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_MASK 0x00300000U -/*This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi - urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i - disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/ +/* +* This bitfield indicates the traffic class of region 0. Valid values are: + * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + * maps to the blue address queue. In this case, valid values are: 0: LPR + * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. +*/ #undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_DEFVAL #undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_SHIFT #undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_MASK -#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_DEFVAL 0x00000000 -#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_SHIFT 16 -#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_MASK 0x00030000U +#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_DEFVAL 0x00000000 +#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_SHIFT 16 +#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_MASK 0x00030000U -/*Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d - al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio - ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc - values.*/ +/* +* Separation level1 indicating the end of region0 mapping; start of region + * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + * lues are used directly as port priorities, where the higher the value co + * rresponds to higher port priority. All of the map_level* registers must + * be set to distinct values. +*/ #undef DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_DEFVAL #undef DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_SHIFT #undef DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_MASK -#define DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_DEFVAL 0x00000000 -#define DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_SHIFT 0 -#define DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_MASK 0x0000000FU +#define DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_DEFVAL 0x00000000 +#define DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_SHIFT 0 +#define DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_MASK 0x0000000FU -/*Specifies the timeout value for transactions mapped to the red address queue.*/ +/* +* Specifies the timeout value for transactions mapped to the red address q + * ueue. +*/ #undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_DEFVAL #undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_SHIFT #undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_MASK -#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_DEFVAL 0x00000000 -#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_SHIFT 16 -#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_MASK 0x07FF0000U +#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_DEFVAL 0x00000000 +#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_SHIFT 16 +#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_MASK 0x07FF0000U -/*Specifies the timeout value for transactions mapped to the blue address queue.*/ +/* +* Specifies the timeout value for transactions mapped to the blue address + * queue. +*/ #undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_DEFVAL #undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_SHIFT #undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_MASK -#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_DEFVAL 0x00000000 -#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_SHIFT 0 -#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_MASK 0x000007FFU +#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_DEFVAL 0x00000000 +#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_SHIFT 0 +#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_MASK 0x000007FFU -/*This bitfield indicates the traffic class of region 1. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2 - VPW_EN = 0) and traffic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW traffic.*/ +/* +* This bitfield indicates the traffic class of region 1. Valid values are: + * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + * affic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW + * traffic. +*/ #undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_DEFVAL #undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_SHIFT #undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_MASK -#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_DEFVAL 0x00000000 -#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_SHIFT 20 -#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_MASK 0x00300000U +#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_DEFVAL 0x00000000 +#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_SHIFT 20 +#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_MASK 0x00300000U -/*This bitfield indicates the traffic class of region 0. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2 - VPW_EN = 0) and traffic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW traffic.*/ +/* +* This bitfield indicates the traffic class of region 0. Valid values are: + * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + * affic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW + * traffic. +*/ #undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_DEFVAL #undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_SHIFT #undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_MASK -#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_DEFVAL 0x00000000 -#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_SHIFT 16 -#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_MASK 0x00030000U +#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_DEFVAL 0x00000000 +#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_SHIFT 16 +#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_MASK 0x00030000U -/*Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 14 which c - rresponds to awqos. Note that for PA, awqos values are used directly as port priorities, where the higher the value correspon - s to higher port priority.*/ +/* +* Separation level indicating the end of region0 mapping; start of region0 + * is 0. Possible values for level1 are 0 to 14 which corresponds to awqos + * . Note that for PA, awqos values are used directly as port priorities, w + * here the higher the value corresponds to higher port priority. +*/ #undef DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_DEFVAL #undef DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_SHIFT #undef DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_MASK -#define DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_DEFVAL 0x00000000 -#define DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_SHIFT 0 -#define DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_MASK 0x0000000FU +#define DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_DEFVAL 0x00000000 +#define DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_SHIFT 0 +#define DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_MASK 0x0000000FU -/*Specifies the timeout value for write transactions.*/ +/* +* Specifies the timeout value for write transactions. +*/ #undef DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_DEFVAL #undef DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_SHIFT #undef DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_MASK -#define DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_DEFVAL -#define DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_SHIFT 0 -#define DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_MASK 0x000007FFU +#define DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_DEFVAL +#define DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_SHIFT 0 +#define DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_MASK 0x000007FFU -/*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register.*/ +/* +* If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. +*/ #undef DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_DEFVAL #undef DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_SHIFT #undef DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_MASK -#define DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_DEFVAL 0x00000000 -#define DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_SHIFT 14 -#define DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_MASK 0x00004000U +#define DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_SHIFT 14 +#define DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_MASK 0x00004000U -/*If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG. - o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add - ess handshaking (it is not associated with any particular command).*/ +/* +* If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + * bled and arurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + * urgent signal can be asserted anytime and as long as required which is i + * ndependent of address handshaking (it is not associated with any particu + * lar command). +*/ #undef DDRC_PCFGR_4_RD_PORT_URGENT_EN_DEFVAL #undef DDRC_PCFGR_4_RD_PORT_URGENT_EN_SHIFT #undef DDRC_PCFGR_4_RD_PORT_URGENT_EN_MASK -#define DDRC_PCFGR_4_RD_PORT_URGENT_EN_DEFVAL 0x00000000 -#define DDRC_PCFGR_4_RD_PORT_URGENT_EN_SHIFT 13 -#define DDRC_PCFGR_4_RD_PORT_URGENT_EN_MASK 0x00002000U +#define DDRC_PCFGR_4_RD_PORT_URGENT_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_4_RD_PORT_URGENT_EN_SHIFT 13 +#define DDRC_PCFGR_4_RD_PORT_URGENT_EN_MASK 0x00002000U -/*If set to 1, enables aging function for the read channel of the port.*/ +/* +* If set to 1, enables aging function for the read channel of the port. +*/ #undef DDRC_PCFGR_4_RD_PORT_AGING_EN_DEFVAL #undef DDRC_PCFGR_4_RD_PORT_AGING_EN_SHIFT #undef DDRC_PCFGR_4_RD_PORT_AGING_EN_MASK -#define DDRC_PCFGR_4_RD_PORT_AGING_EN_DEFVAL 0x00000000 -#define DDRC_PCFGR_4_RD_PORT_AGING_EN_SHIFT 12 -#define DDRC_PCFGR_4_RD_PORT_AGING_EN_MASK 0x00001000U +#define DDRC_PCFGR_4_RD_PORT_AGING_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_4_RD_PORT_AGING_EN_SHIFT 12 +#define DDRC_PCFGR_4_RD_PORT_AGING_EN_MASK 0x00001000U -/*Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g - ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority - will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre - ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the - aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st - ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w - ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D - RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: - he two LSBs of this register field are tied internally to 2'b00.*/ +/* +* Determines the initial load value of read aging counters. These counters + * will be parallel loaded after reset, or after each grant to the corresp + * onding port. The aging counters down-count every clock cycle where the p + * ort is requesting but not granted. The higher significant 5-bits of the + * read aging counter sets the priority of the read channel of a given port + * . Port's priority will increase as the higher significant 5-bits of the + * counter starts to decrease. When the aging counter becomes 0, the corres + * ponding port channel will have the highest priority level (timeout condi + * tion - Priority0). For multi-port configurations, the aging counters can + * not be used to set port priorities when external dynamic priority inputs + * (arqos) are enabled (timeout is still applicable). For single port conf + * igurations, the aging counters are only used when they timeout (become 0 + * ) to force read-write direction switching. In this case, external dynami + * c priority input, arqos (for reads only) can still be used to set the DD + * RC read priority (2 priority levels: low priority read - LPR, high prior + * ity read - HPR) on a command by command basis. Note: The two LSBs of thi + * s register field are tied internally to 2'b00. +*/ #undef DDRC_PCFGR_4_RD_PORT_PRIORITY_DEFVAL #undef DDRC_PCFGR_4_RD_PORT_PRIORITY_SHIFT #undef DDRC_PCFGR_4_RD_PORT_PRIORITY_MASK -#define DDRC_PCFGR_4_RD_PORT_PRIORITY_DEFVAL 0x00000000 -#define DDRC_PCFGR_4_RD_PORT_PRIORITY_SHIFT 0 -#define DDRC_PCFGR_4_RD_PORT_PRIORITY_MASK 0x000003FFU +#define DDRC_PCFGR_4_RD_PORT_PRIORITY_DEFVAL 0x00000000 +#define DDRC_PCFGR_4_RD_PORT_PRIORITY_SHIFT 0 +#define DDRC_PCFGR_4_RD_PORT_PRIORITY_MASK 0x000003FFU -/*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register.*/ +/* +* If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. +*/ #undef DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_DEFVAL #undef DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_SHIFT #undef DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_MASK -#define DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_DEFVAL 0x00004000 -#define DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_SHIFT 14 -#define DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_MASK 0x00004000U +#define DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_SHIFT 14 +#define DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_MASK 0x00004000U -/*If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register - Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is - not associated with any particular command).*/ +/* +* If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + * bled and awurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + * serted anytime and as long as required which is independent of address h + * andshaking (it is not associated with any particular command). +*/ #undef DDRC_PCFGW_4_WR_PORT_URGENT_EN_DEFVAL #undef DDRC_PCFGW_4_WR_PORT_URGENT_EN_SHIFT #undef DDRC_PCFGW_4_WR_PORT_URGENT_EN_MASK -#define DDRC_PCFGW_4_WR_PORT_URGENT_EN_DEFVAL 0x00004000 -#define DDRC_PCFGW_4_WR_PORT_URGENT_EN_SHIFT 13 -#define DDRC_PCFGW_4_WR_PORT_URGENT_EN_MASK 0x00002000U +#define DDRC_PCFGW_4_WR_PORT_URGENT_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_4_WR_PORT_URGENT_EN_SHIFT 13 +#define DDRC_PCFGW_4_WR_PORT_URGENT_EN_MASK 0x00002000U -/*If set to 1, enables aging function for the write channel of the port.*/ +/* +* If set to 1, enables aging function for the write channel of the port. +*/ #undef DDRC_PCFGW_4_WR_PORT_AGING_EN_DEFVAL #undef DDRC_PCFGW_4_WR_PORT_AGING_EN_SHIFT #undef DDRC_PCFGW_4_WR_PORT_AGING_EN_MASK -#define DDRC_PCFGW_4_WR_PORT_AGING_EN_DEFVAL 0x00004000 -#define DDRC_PCFGW_4_WR_PORT_AGING_EN_SHIFT 12 -#define DDRC_PCFGW_4_WR_PORT_AGING_EN_MASK 0x00001000U +#define DDRC_PCFGW_4_WR_PORT_AGING_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_4_WR_PORT_AGING_EN_SHIFT 12 +#define DDRC_PCFGW_4_WR_PORT_AGING_EN_MASK 0x00001000U -/*Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each - rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port - s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0 - the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno - be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For - ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch - ng. Note: The two LSBs of this register field are tied internally to 2'b00.*/ +/* +* Determines the initial load value of write aging counters. These counter + * s will be parallel loaded after reset, or after each grant to the corres + * ponding port. The aging counters down-count every clock cycle where the + * port is requesting but not granted. The higher significant 5-bits of the + * write aging counter sets the initial priority of the write channel of a + * given port. Port's priority will increase as the higher significant 5-b + * its of the counter starts to decrease. When the aging counter becomes 0, + * the corresponding port channel will have the highest priority level. Fo + * r multi-port configurations, the aging counters cannot be used to set po + * rt priorities when external dynamic priority inputs (awqos) are enabled + * (timeout is still applicable). For single port configurations, the aging + * counters are only used when they timeout (become 0) to force read-write + * direction switching. Note: The two LSBs of this register field are tied + * internally to 2'b00. +*/ #undef DDRC_PCFGW_4_WR_PORT_PRIORITY_DEFVAL #undef DDRC_PCFGW_4_WR_PORT_PRIORITY_SHIFT #undef DDRC_PCFGW_4_WR_PORT_PRIORITY_MASK -#define DDRC_PCFGW_4_WR_PORT_PRIORITY_DEFVAL 0x00004000 -#define DDRC_PCFGW_4_WR_PORT_PRIORITY_SHIFT 0 -#define DDRC_PCFGW_4_WR_PORT_PRIORITY_MASK 0x000003FFU +#define DDRC_PCFGW_4_WR_PORT_PRIORITY_DEFVAL 0x00004000 +#define DDRC_PCFGW_4_WR_PORT_PRIORITY_SHIFT 0 +#define DDRC_PCFGW_4_WR_PORT_PRIORITY_MASK 0x000003FFU -/*Enables port n.*/ +/* +* Enables port n. +*/ #undef DDRC_PCTRL_4_PORT_EN_DEFVAL #undef DDRC_PCTRL_4_PORT_EN_SHIFT #undef DDRC_PCTRL_4_PORT_EN_MASK -#define DDRC_PCTRL_4_PORT_EN_DEFVAL -#define DDRC_PCTRL_4_PORT_EN_SHIFT 0 -#define DDRC_PCTRL_4_PORT_EN_MASK 0x00000001U +#define DDRC_PCTRL_4_PORT_EN_DEFVAL +#define DDRC_PCTRL_4_PORT_EN_SHIFT 0 +#define DDRC_PCTRL_4_PORT_EN_MASK 0x00000001U -/*This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf - gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is - disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/ +/* +* This bitfield indicates the traffic class of region 1. Valid values are: + * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + * maps to the blue address queue. In this case, valid values are 0: LPR a + * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. +*/ #undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_DEFVAL #undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_SHIFT #undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_MASK -#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_DEFVAL 0x00000000 -#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_SHIFT 20 -#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_MASK 0x00300000U +#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_DEFVAL 0x00000000 +#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_SHIFT 20 +#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_MASK 0x00300000U -/*This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi - urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i - disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/ +/* +* This bitfield indicates the traffic class of region 0. Valid values are: + * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + * maps to the blue address queue. In this case, valid values are: 0: LPR + * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. +*/ #undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_DEFVAL #undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_SHIFT #undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_MASK -#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_DEFVAL 0x00000000 -#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_SHIFT 16 -#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_MASK 0x00030000U +#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_DEFVAL 0x00000000 +#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_SHIFT 16 +#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_MASK 0x00030000U -/*Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d - al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio - ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc - values.*/ +/* +* Separation level1 indicating the end of region0 mapping; start of region + * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + * lues are used directly as port priorities, where the higher the value co + * rresponds to higher port priority. All of the map_level* registers must + * be set to distinct values. +*/ #undef DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_DEFVAL #undef DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_SHIFT #undef DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_MASK -#define DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_DEFVAL 0x00000000 -#define DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_SHIFT 0 -#define DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_MASK 0x0000000FU +#define DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_DEFVAL 0x00000000 +#define DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_SHIFT 0 +#define DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_MASK 0x0000000FU -/*Specifies the timeout value for transactions mapped to the red address queue.*/ +/* +* Specifies the timeout value for transactions mapped to the red address q + * ueue. +*/ #undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_DEFVAL #undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_SHIFT #undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_MASK -#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_DEFVAL 0x00000000 -#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_SHIFT 16 -#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_MASK 0x07FF0000U +#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_DEFVAL 0x00000000 +#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_SHIFT 16 +#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_MASK 0x07FF0000U -/*Specifies the timeout value for transactions mapped to the blue address queue.*/ +/* +* Specifies the timeout value for transactions mapped to the blue address + * queue. +*/ #undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_DEFVAL #undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_SHIFT #undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_MASK -#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_DEFVAL 0x00000000 -#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_SHIFT 0 -#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_MASK 0x000007FFU +#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_DEFVAL 0x00000000 +#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_SHIFT 0 +#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_MASK 0x000007FFU -/*This bitfield indicates the traffic class of region 1. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2 - VPW_EN = 0) and traffic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW traffic.*/ +/* +* This bitfield indicates the traffic class of region 1. Valid values are: + * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + * affic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW + * traffic. +*/ #undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_DEFVAL #undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_SHIFT #undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_MASK -#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_DEFVAL 0x00000000 -#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_SHIFT 20 -#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_MASK 0x00300000U +#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_DEFVAL 0x00000000 +#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_SHIFT 20 +#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_MASK 0x00300000U -/*This bitfield indicates the traffic class of region 0. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2 - VPW_EN = 0) and traffic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW traffic.*/ +/* +* This bitfield indicates the traffic class of region 0. Valid values are: + * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + * affic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW + * traffic. +*/ #undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_DEFVAL #undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_SHIFT #undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_MASK -#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_DEFVAL 0x00000000 -#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_SHIFT 16 -#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_MASK 0x00030000U +#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_DEFVAL 0x00000000 +#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_SHIFT 16 +#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_MASK 0x00030000U -/*Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 14 which c - rresponds to awqos. Note that for PA, awqos values are used directly as port priorities, where the higher the value correspon - s to higher port priority.*/ +/* +* Separation level indicating the end of region0 mapping; start of region0 + * is 0. Possible values for level1 are 0 to 14 which corresponds to awqos + * . Note that for PA, awqos values are used directly as port priorities, w + * here the higher the value corresponds to higher port priority. +*/ #undef DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_DEFVAL #undef DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_SHIFT #undef DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_MASK -#define DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_DEFVAL 0x00000000 -#define DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_SHIFT 0 -#define DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_MASK 0x0000000FU +#define DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_DEFVAL 0x00000000 +#define DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_SHIFT 0 +#define DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_MASK 0x0000000FU -/*Specifies the timeout value for write transactions.*/ +/* +* Specifies the timeout value for write transactions. +*/ #undef DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_DEFVAL #undef DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_SHIFT #undef DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_MASK -#define DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_DEFVAL -#define DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_SHIFT 0 -#define DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_MASK 0x000007FFU +#define DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_DEFVAL +#define DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_SHIFT 0 +#define DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_MASK 0x000007FFU -/*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register.*/ +/* +* If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. +*/ #undef DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_DEFVAL #undef DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_SHIFT #undef DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_MASK -#define DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_DEFVAL 0x00000000 -#define DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_SHIFT 14 -#define DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_MASK 0x00004000U +#define DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_SHIFT 14 +#define DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_MASK 0x00004000U -/*If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG. - o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add - ess handshaking (it is not associated with any particular command).*/ +/* +* If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + * bled and arurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + * urgent signal can be asserted anytime and as long as required which is i + * ndependent of address handshaking (it is not associated with any particu + * lar command). +*/ #undef DDRC_PCFGR_5_RD_PORT_URGENT_EN_DEFVAL #undef DDRC_PCFGR_5_RD_PORT_URGENT_EN_SHIFT #undef DDRC_PCFGR_5_RD_PORT_URGENT_EN_MASK -#define DDRC_PCFGR_5_RD_PORT_URGENT_EN_DEFVAL 0x00000000 -#define DDRC_PCFGR_5_RD_PORT_URGENT_EN_SHIFT 13 -#define DDRC_PCFGR_5_RD_PORT_URGENT_EN_MASK 0x00002000U +#define DDRC_PCFGR_5_RD_PORT_URGENT_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_5_RD_PORT_URGENT_EN_SHIFT 13 +#define DDRC_PCFGR_5_RD_PORT_URGENT_EN_MASK 0x00002000U -/*If set to 1, enables aging function for the read channel of the port.*/ +/* +* If set to 1, enables aging function for the read channel of the port. +*/ #undef DDRC_PCFGR_5_RD_PORT_AGING_EN_DEFVAL #undef DDRC_PCFGR_5_RD_PORT_AGING_EN_SHIFT #undef DDRC_PCFGR_5_RD_PORT_AGING_EN_MASK -#define DDRC_PCFGR_5_RD_PORT_AGING_EN_DEFVAL 0x00000000 -#define DDRC_PCFGR_5_RD_PORT_AGING_EN_SHIFT 12 -#define DDRC_PCFGR_5_RD_PORT_AGING_EN_MASK 0x00001000U +#define DDRC_PCFGR_5_RD_PORT_AGING_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_5_RD_PORT_AGING_EN_SHIFT 12 +#define DDRC_PCFGR_5_RD_PORT_AGING_EN_MASK 0x00001000U -/*Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g - ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority - will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre - ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the - aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st - ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w - ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D - RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: - he two LSBs of this register field are tied internally to 2'b00.*/ +/* +* Determines the initial load value of read aging counters. These counters + * will be parallel loaded after reset, or after each grant to the corresp + * onding port. The aging counters down-count every clock cycle where the p + * ort is requesting but not granted. The higher significant 5-bits of the + * read aging counter sets the priority of the read channel of a given port + * . Port's priority will increase as the higher significant 5-bits of the + * counter starts to decrease. When the aging counter becomes 0, the corres + * ponding port channel will have the highest priority level (timeout condi + * tion - Priority0). For multi-port configurations, the aging counters can + * not be used to set port priorities when external dynamic priority inputs + * (arqos) are enabled (timeout is still applicable). For single port conf + * igurations, the aging counters are only used when they timeout (become 0 + * ) to force read-write direction switching. In this case, external dynami + * c priority input, arqos (for reads only) can still be used to set the DD + * RC read priority (2 priority levels: low priority read - LPR, high prior + * ity read - HPR) on a command by command basis. Note: The two LSBs of thi + * s register field are tied internally to 2'b00. +*/ #undef DDRC_PCFGR_5_RD_PORT_PRIORITY_DEFVAL #undef DDRC_PCFGR_5_RD_PORT_PRIORITY_SHIFT #undef DDRC_PCFGR_5_RD_PORT_PRIORITY_MASK -#define DDRC_PCFGR_5_RD_PORT_PRIORITY_DEFVAL 0x00000000 -#define DDRC_PCFGR_5_RD_PORT_PRIORITY_SHIFT 0 -#define DDRC_PCFGR_5_RD_PORT_PRIORITY_MASK 0x000003FFU +#define DDRC_PCFGR_5_RD_PORT_PRIORITY_DEFVAL 0x00000000 +#define DDRC_PCFGR_5_RD_PORT_PRIORITY_SHIFT 0 +#define DDRC_PCFGR_5_RD_PORT_PRIORITY_MASK 0x000003FFU -/*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register.*/ +/* +* If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. +*/ #undef DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_DEFVAL #undef DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_SHIFT #undef DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_MASK -#define DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_DEFVAL 0x00004000 -#define DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_SHIFT 14 -#define DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_MASK 0x00004000U +#define DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_SHIFT 14 +#define DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_MASK 0x00004000U -/*If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register - Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is - not associated with any particular command).*/ +/* +* If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + * bled and awurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + * serted anytime and as long as required which is independent of address h + * andshaking (it is not associated with any particular command). +*/ #undef DDRC_PCFGW_5_WR_PORT_URGENT_EN_DEFVAL #undef DDRC_PCFGW_5_WR_PORT_URGENT_EN_SHIFT #undef DDRC_PCFGW_5_WR_PORT_URGENT_EN_MASK -#define DDRC_PCFGW_5_WR_PORT_URGENT_EN_DEFVAL 0x00004000 -#define DDRC_PCFGW_5_WR_PORT_URGENT_EN_SHIFT 13 -#define DDRC_PCFGW_5_WR_PORT_URGENT_EN_MASK 0x00002000U +#define DDRC_PCFGW_5_WR_PORT_URGENT_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_5_WR_PORT_URGENT_EN_SHIFT 13 +#define DDRC_PCFGW_5_WR_PORT_URGENT_EN_MASK 0x00002000U -/*If set to 1, enables aging function for the write channel of the port.*/ +/* +* If set to 1, enables aging function for the write channel of the port. +*/ #undef DDRC_PCFGW_5_WR_PORT_AGING_EN_DEFVAL #undef DDRC_PCFGW_5_WR_PORT_AGING_EN_SHIFT #undef DDRC_PCFGW_5_WR_PORT_AGING_EN_MASK -#define DDRC_PCFGW_5_WR_PORT_AGING_EN_DEFVAL 0x00004000 -#define DDRC_PCFGW_5_WR_PORT_AGING_EN_SHIFT 12 -#define DDRC_PCFGW_5_WR_PORT_AGING_EN_MASK 0x00001000U +#define DDRC_PCFGW_5_WR_PORT_AGING_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_5_WR_PORT_AGING_EN_SHIFT 12 +#define DDRC_PCFGW_5_WR_PORT_AGING_EN_MASK 0x00001000U -/*Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each - rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port - s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0 - the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno - be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For - ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch - ng. Note: The two LSBs of this register field are tied internally to 2'b00.*/ +/* +* Determines the initial load value of write aging counters. These counter + * s will be parallel loaded after reset, or after each grant to the corres + * ponding port. The aging counters down-count every clock cycle where the + * port is requesting but not granted. The higher significant 5-bits of the + * write aging counter sets the initial priority of the write channel of a + * given port. Port's priority will increase as the higher significant 5-b + * its of the counter starts to decrease. When the aging counter becomes 0, + * the corresponding port channel will have the highest priority level. Fo + * r multi-port configurations, the aging counters cannot be used to set po + * rt priorities when external dynamic priority inputs (awqos) are enabled + * (timeout is still applicable). For single port configurations, the aging + * counters are only used when they timeout (become 0) to force read-write + * direction switching. Note: The two LSBs of this register field are tied + * internally to 2'b00. +*/ #undef DDRC_PCFGW_5_WR_PORT_PRIORITY_DEFVAL #undef DDRC_PCFGW_5_WR_PORT_PRIORITY_SHIFT #undef DDRC_PCFGW_5_WR_PORT_PRIORITY_MASK -#define DDRC_PCFGW_5_WR_PORT_PRIORITY_DEFVAL 0x00004000 -#define DDRC_PCFGW_5_WR_PORT_PRIORITY_SHIFT 0 -#define DDRC_PCFGW_5_WR_PORT_PRIORITY_MASK 0x000003FFU +#define DDRC_PCFGW_5_WR_PORT_PRIORITY_DEFVAL 0x00004000 +#define DDRC_PCFGW_5_WR_PORT_PRIORITY_SHIFT 0 +#define DDRC_PCFGW_5_WR_PORT_PRIORITY_MASK 0x000003FFU -/*Enables port n.*/ +/* +* Enables port n. +*/ #undef DDRC_PCTRL_5_PORT_EN_DEFVAL #undef DDRC_PCTRL_5_PORT_EN_SHIFT #undef DDRC_PCTRL_5_PORT_EN_MASK -#define DDRC_PCTRL_5_PORT_EN_DEFVAL -#define DDRC_PCTRL_5_PORT_EN_SHIFT 0 -#define DDRC_PCTRL_5_PORT_EN_MASK 0x00000001U +#define DDRC_PCTRL_5_PORT_EN_DEFVAL +#define DDRC_PCTRL_5_PORT_EN_SHIFT 0 +#define DDRC_PCTRL_5_PORT_EN_MASK 0x00000001U -/*This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf - gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is - disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/ +/* +* This bitfield indicates the traffic class of region 1. Valid values are: + * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + * maps to the blue address queue. In this case, valid values are 0: LPR a + * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. +*/ #undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_DEFVAL #undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_SHIFT #undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_MASK -#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_DEFVAL 0x00000000 -#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_SHIFT 20 -#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_MASK 0x00300000U +#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_DEFVAL 0x00000000 +#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_SHIFT 20 +#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_MASK 0x00300000U -/*This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi - urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i - disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/ +/* +* This bitfield indicates the traffic class of region 0. Valid values are: + * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + * maps to the blue address queue. In this case, valid values are: 0: LPR + * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. +*/ #undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_DEFVAL #undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_SHIFT #undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_MASK -#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_DEFVAL 0x00000000 -#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_SHIFT 16 -#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_MASK 0x00030000U +#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_DEFVAL 0x00000000 +#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_SHIFT 16 +#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_MASK 0x00030000U -/*Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d - al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio - ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc - values.*/ +/* +* Separation level1 indicating the end of region0 mapping; start of region + * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + * lues are used directly as port priorities, where the higher the value co + * rresponds to higher port priority. All of the map_level* registers must + * be set to distinct values. +*/ #undef DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_DEFVAL #undef DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_SHIFT #undef DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_MASK -#define DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_DEFVAL 0x00000000 -#define DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_SHIFT 0 -#define DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_MASK 0x0000000FU +#define DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_DEFVAL 0x00000000 +#define DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_SHIFT 0 +#define DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_MASK 0x0000000FU -/*Specifies the timeout value for transactions mapped to the red address queue.*/ +/* +* Specifies the timeout value for transactions mapped to the red address q + * ueue. +*/ #undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_DEFVAL #undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_SHIFT #undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_MASK -#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_DEFVAL 0x00000000 -#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_SHIFT 16 -#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_MASK 0x07FF0000U +#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_DEFVAL 0x00000000 +#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_SHIFT 16 +#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_MASK 0x07FF0000U -/*Specifies the timeout value for transactions mapped to the blue address queue.*/ +/* +* Specifies the timeout value for transactions mapped to the blue address + * queue. +*/ #undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_DEFVAL #undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_SHIFT #undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_MASK -#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_DEFVAL 0x00000000 -#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_SHIFT 0 -#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_MASK 0x000007FFU +#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_DEFVAL 0x00000000 +#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_SHIFT 0 +#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_MASK 0x000007FFU -/*This bitfield indicates the traffic class of region 1. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2 - VPW_EN = 0) and traffic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW traffic.*/ +/* +* This bitfield indicates the traffic class of region 1. Valid values are: + * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + * affic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW + * traffic. +*/ #undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_DEFVAL #undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_SHIFT #undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_MASK -#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_DEFVAL 0x00000000 -#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_SHIFT 20 -#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_MASK 0x00300000U +#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_DEFVAL 0x00000000 +#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_SHIFT 20 +#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_MASK 0x00300000U -/*This bitfield indicates the traffic class of region 0. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2 - VPW_EN = 0) and traffic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW traffic.*/ +/* +* This bitfield indicates the traffic class of region 0. Valid values are: + * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + * affic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW + * traffic. +*/ #undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_DEFVAL #undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_SHIFT #undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_MASK -#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_DEFVAL 0x00000000 -#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_SHIFT 16 -#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_MASK 0x00030000U +#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_DEFVAL 0x00000000 +#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_SHIFT 16 +#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_MASK 0x00030000U -/*Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 14 which c - rresponds to awqos. Note that for PA, awqos values are used directly as port priorities, where the higher the value correspon - s to higher port priority.*/ +/* +* Separation level indicating the end of region0 mapping; start of region0 + * is 0. Possible values for level1 are 0 to 14 which corresponds to awqos + * . Note that for PA, awqos values are used directly as port priorities, w + * here the higher the value corresponds to higher port priority. +*/ #undef DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_DEFVAL #undef DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_SHIFT #undef DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_MASK -#define DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_DEFVAL 0x00000000 -#define DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_SHIFT 0 -#define DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_MASK 0x0000000FU +#define DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_DEFVAL 0x00000000 +#define DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_SHIFT 0 +#define DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_MASK 0x0000000FU -/*Specifies the timeout value for write transactions.*/ +/* +* Specifies the timeout value for write transactions. +*/ #undef DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_DEFVAL #undef DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_SHIFT #undef DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_MASK -#define DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_DEFVAL -#define DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_SHIFT 0 -#define DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_MASK 0x000007FFU +#define DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_DEFVAL +#define DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_SHIFT 0 +#define DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_MASK 0x000007FFU -/*Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x] and araddr[UMCTL2_A_ADDRW-1:x] where x is determine - by the minimum block size parameter UMCTL2_SARMINSIZE: (x=log2(block size)).*/ +/* +* Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x + * ] and araddr[UMCTL2_A_ADDRW-1:x] where x is determined by the minimum bl + * ock size parameter UMCTL2_SARMINSIZE: (x=log2(block size)). +*/ #undef DDRC_SARBASE0_BASE_ADDR_DEFVAL #undef DDRC_SARBASE0_BASE_ADDR_SHIFT #undef DDRC_SARBASE0_BASE_ADDR_MASK -#define DDRC_SARBASE0_BASE_ADDR_DEFVAL -#define DDRC_SARBASE0_BASE_ADDR_SHIFT 0 -#define DDRC_SARBASE0_BASE_ADDR_MASK 0x000001FFU +#define DDRC_SARBASE0_BASE_ADDR_DEFVAL +#define DDRC_SARBASE0_BASE_ADDR_SHIFT 0 +#define DDRC_SARBASE0_BASE_ADDR_MASK 0x000001FFU -/*Number of blocks for address region n. This register determines the total size of the region in multiples of minimum block si - e as specified by the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded as number of blocks = nblocks + 1. - or example, if register is programmed to 0, region will have 1 block.*/ +/* +* Number of blocks for address region n. This register determines the tota + * l size of the region in multiples of minimum block size as specified by + * the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded + * as number of blocks = nblocks + 1. For example, if register is programme + * d to 0, region will have 1 block. +*/ #undef DDRC_SARSIZE0_NBLOCKS_DEFVAL #undef DDRC_SARSIZE0_NBLOCKS_SHIFT #undef DDRC_SARSIZE0_NBLOCKS_MASK -#define DDRC_SARSIZE0_NBLOCKS_DEFVAL -#define DDRC_SARSIZE0_NBLOCKS_SHIFT 0 -#define DDRC_SARSIZE0_NBLOCKS_MASK 0x000000FFU +#define DDRC_SARSIZE0_NBLOCKS_DEFVAL +#define DDRC_SARSIZE0_NBLOCKS_SHIFT 0 +#define DDRC_SARSIZE0_NBLOCKS_MASK 0x000000FFU -/*Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x] and araddr[UMCTL2_A_ADDRW-1:x] where x is determine - by the minimum block size parameter UMCTL2_SARMINSIZE: (x=log2(block size)).*/ +/* +* Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x + * ] and araddr[UMCTL2_A_ADDRW-1:x] where x is determined by the minimum bl + * ock size parameter UMCTL2_SARMINSIZE: (x=log2(block size)). +*/ #undef DDRC_SARBASE1_BASE_ADDR_DEFVAL #undef DDRC_SARBASE1_BASE_ADDR_SHIFT #undef DDRC_SARBASE1_BASE_ADDR_MASK -#define DDRC_SARBASE1_BASE_ADDR_DEFVAL -#define DDRC_SARBASE1_BASE_ADDR_SHIFT 0 -#define DDRC_SARBASE1_BASE_ADDR_MASK 0x000001FFU +#define DDRC_SARBASE1_BASE_ADDR_DEFVAL +#define DDRC_SARBASE1_BASE_ADDR_SHIFT 0 +#define DDRC_SARBASE1_BASE_ADDR_MASK 0x000001FFU -/*Number of blocks for address region n. This register determines the total size of the region in multiples of minimum block si - e as specified by the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded as number of blocks = nblocks + 1. - or example, if register is programmed to 0, region will have 1 block.*/ +/* +* Number of blocks for address region n. This register determines the tota + * l size of the region in multiples of minimum block size as specified by + * the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded + * as number of blocks = nblocks + 1. For example, if register is programme + * d to 0, region will have 1 block. +*/ #undef DDRC_SARSIZE1_NBLOCKS_DEFVAL #undef DDRC_SARSIZE1_NBLOCKS_SHIFT #undef DDRC_SARSIZE1_NBLOCKS_MASK -#define DDRC_SARSIZE1_NBLOCKS_DEFVAL -#define DDRC_SARSIZE1_NBLOCKS_SHIFT 0 -#define DDRC_SARSIZE1_NBLOCKS_MASK 0x000000FFU +#define DDRC_SARSIZE1_NBLOCKS_DEFVAL +#define DDRC_SARSIZE1_NBLOCKS_SHIFT 0 +#define DDRC_SARSIZE1_NBLOCKS_MASK 0x000000FFU -/*Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signa - s at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligne - , this timing parameter should be rounded up to the next integer value. Note that if using RDIMM, it is necessary to incremen - this parameter by RDIMM's extra cycle of latency in terms of DFI clock.*/ +/* +* Specifies the number of DFI clock cycles after an assertion or de-assert + * ion of the DFI control signals that the control signals at the PHY-DRAM + * interface reflect the assertion or de-assertion. If the DFI clock and th + * e memory clock are not phase-aligned, this timing parameter should be ro + * unded up to the next integer value. Note that if using RDIMM, it is nece + * ssary to increment this parameter by RDIMM's extra cycle of latency in t + * erms of DFI clock. +*/ #undef DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_DEFVAL #undef DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_SHIFT #undef DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_MASK -#define DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_DEFVAL 0x07020002 -#define DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_SHIFT 24 -#define DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_MASK 0x1F000000U +#define DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_DEFVAL 0x07020002 +#define DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_SHIFT 24 +#define DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_MASK 0x1F000000U -/*Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR or SDR values Selects whether value in DFITM - 0.dfi_t_rddata_en is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles R - fer to PHY specification for correct value.*/ +/* +* Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated u + * sing HDR or SDR values Selects whether value in DFITMG0.dfi_t_rddata_en + * is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles + * - 1 in terms of SDR clock cycles Refer to PHY specification for correct + * value. +*/ #undef DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_DEFVAL #undef DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_SHIFT #undef DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_MASK -#define DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_DEFVAL 0x07020002 -#define DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_SHIFT 23 -#define DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_MASK 0x00800000U +#define DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_DEFVAL 0x07020002 +#define DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_SHIFT 23 +#define DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_MASK 0x00800000U -/*Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. Refer to PHY spe - ification for correct value. This corresponds to the DFI parameter trddata_en. Note that, depending on the PHY, if using RDIM - , it may be necessary to use the value (CL + 1) in the calculation of trddata_en. This is to compensate for the extra cycle o - latency through the RDIMM. Unit: Clocks*/ +/* +* Time from the assertion of a read command on the DFI interface to the as + * sertion of the dfi_rddata_en signal. Refer to PHY specification for corr + * ect value. This corresponds to the DFI parameter trddata_en. Note that, + * depending on the PHY, if using RDIMM, it may be necessary to use the val + * ue (CL + 1) in the calculation of trddata_en. This is to compensate for + * the extra cycle of latency through the RDIMM. Unit: Clocks +*/ #undef DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_DEFVAL #undef DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_SHIFT #undef DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_MASK -#define DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_DEFVAL 0x07020002 -#define DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_SHIFT 16 -#define DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_MASK 0x003F0000U +#define DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_DEFVAL 0x07020002 +#define DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_SHIFT 16 +#define DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_MASK 0x003F0000U -/*Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using HDR or SDR values Selects whether value in DFITMG - .dfi_tphy_wrlat is in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.dfi_tphy_wrdata is in terms of SDR or - HDR clock cycles - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles Refer to PHY specification for correct val - e.*/ +/* +* Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated us + * ing HDR or SDR values Selects whether value in DFITMG0.dfi_tphy_wrlat is + * in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.df + * i_tphy_wrdata is in terms of SDR or HDR clock cycles - 0 in terms of HDR + * clock cycles - 1 in terms of SDR clock cycles Refer to PHY specificatio + * n for correct value. +*/ #undef DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_DEFVAL #undef DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_SHIFT #undef DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_MASK -#define DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_DEFVAL 0x07020002 -#define DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_SHIFT 15 -#define DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_MASK 0x00008000U +#define DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_DEFVAL 0x07020002 +#define DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_SHIFT 15 +#define DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_MASK 0x00008000U -/*Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on th - dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. N - te, max supported value is 8. Unit: Clocks*/ +/* +* Specifies the number of clock cycles between when dfi_wrdata_en is asser + * ted to when the associated write data is driven on the dfi_wrdata signal + * . This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY + * specification for correct value. Note, max supported value is 8. Unit: + * Clocks +*/ #undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_DEFVAL #undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_SHIFT #undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_MASK -#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_DEFVAL 0x07020002 -#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_SHIFT 8 -#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_MASK 0x00003F00U +#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_DEFVAL 0x07020002 +#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_SHIFT 8 +#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_MASK 0x00003F00U -/*Write latency Number of clocks from the write command to write data enable (dfi_wrdata_en). This corresponds to the DFI timin - parameter tphy_wrlat. Refer to PHY specification for correct value.Note that, depending on the PHY, if using RDIMM, it may b - necessary to use the value (CL + 1) in the calculation of tphy_wrlat. This is to compensate for the extra cycle of latency t - rough the RDIMM.*/ +/* +* Write latency Number of clocks from the write command to write data enab + * le (dfi_wrdata_en). This corresponds to the DFI timing parameter tphy_wr + * lat. Refer to PHY specification for correct value.Note that, depending o + * n the PHY, if using RDIMM, it may be necessary to use the value (CL + 1) + * in the calculation of tphy_wrlat. This is to compensate for the extra c + * ycle of latency through the RDIMM. +*/ #undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_DEFVAL #undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_SHIFT #undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_MASK -#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_DEFVAL 0x07020002 -#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_SHIFT 0 -#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_MASK 0x0000003FU +#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_DEFVAL 0x07020002 +#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_SHIFT 0 +#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_MASK 0x0000003FU -/*DDR block level reset inside of the DDR Sub System*/ +/* +* DDR block level reset inside of the DDR Sub System +*/ #undef CRF_APB_RST_DDR_SS_DDR_RESET_DEFVAL #undef CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT #undef CRF_APB_RST_DDR_SS_DDR_RESET_MASK -#define CRF_APB_RST_DDR_SS_DDR_RESET_DEFVAL 0x0000000F -#define CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT 3 -#define CRF_APB_RST_DDR_SS_DDR_RESET_MASK 0x00000008U +#define CRF_APB_RST_DDR_SS_DDR_RESET_DEFVAL 0x0000000F +#define CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT 3 +#define CRF_APB_RST_DDR_SS_DDR_RESET_MASK 0x00000008U -/*Address Copy*/ +/* +* APM block level reset inside of the DDR Sub System +*/ +#undef CRF_APB_RST_DDR_SS_APM_RESET_DEFVAL +#undef CRF_APB_RST_DDR_SS_APM_RESET_SHIFT +#undef CRF_APB_RST_DDR_SS_APM_RESET_MASK +#define CRF_APB_RST_DDR_SS_APM_RESET_DEFVAL 0x0000000F +#define CRF_APB_RST_DDR_SS_APM_RESET_SHIFT 2 +#define CRF_APB_RST_DDR_SS_APM_RESET_MASK 0x00000004U + +/* +* Address Copy +*/ #undef DDR_PHY_PGCR0_ADCP_DEFVAL #undef DDR_PHY_PGCR0_ADCP_SHIFT #undef DDR_PHY_PGCR0_ADCP_MASK -#define DDR_PHY_PGCR0_ADCP_DEFVAL 0x07001E00 -#define DDR_PHY_PGCR0_ADCP_SHIFT 31 -#define DDR_PHY_PGCR0_ADCP_MASK 0x80000000U +#define DDR_PHY_PGCR0_ADCP_DEFVAL 0x07001E00 +#define DDR_PHY_PGCR0_ADCP_SHIFT 31 +#define DDR_PHY_PGCR0_ADCP_MASK 0x80000000U -/*Reserved. Returns zeroes on reads.*/ +/* +* Reserved. Returns zeroes on reads. +*/ #undef DDR_PHY_PGCR0_RESERVED_30_27_DEFVAL #undef DDR_PHY_PGCR0_RESERVED_30_27_SHIFT #undef DDR_PHY_PGCR0_RESERVED_30_27_MASK -#define DDR_PHY_PGCR0_RESERVED_30_27_DEFVAL 0x07001E00 -#define DDR_PHY_PGCR0_RESERVED_30_27_SHIFT 27 -#define DDR_PHY_PGCR0_RESERVED_30_27_MASK 0x78000000U +#define DDR_PHY_PGCR0_RESERVED_30_27_DEFVAL 0x07001E00 +#define DDR_PHY_PGCR0_RESERVED_30_27_SHIFT 27 +#define DDR_PHY_PGCR0_RESERVED_30_27_MASK 0x78000000U -/*PHY FIFO Reset*/ +/* +* PHY FIFO Reset +*/ #undef DDR_PHY_PGCR0_PHYFRST_DEFVAL #undef DDR_PHY_PGCR0_PHYFRST_SHIFT #undef DDR_PHY_PGCR0_PHYFRST_MASK -#define DDR_PHY_PGCR0_PHYFRST_DEFVAL 0x07001E00 -#define DDR_PHY_PGCR0_PHYFRST_SHIFT 26 -#define DDR_PHY_PGCR0_PHYFRST_MASK 0x04000000U +#define DDR_PHY_PGCR0_PHYFRST_DEFVAL 0x07001E00 +#define DDR_PHY_PGCR0_PHYFRST_SHIFT 26 +#define DDR_PHY_PGCR0_PHYFRST_MASK 0x04000000U -/*Oscillator Mode Address/Command Delay Line Select*/ +/* +* Oscillator Mode Address/Command Delay Line Select +*/ #undef DDR_PHY_PGCR0_OSCACDL_DEFVAL #undef DDR_PHY_PGCR0_OSCACDL_SHIFT #undef DDR_PHY_PGCR0_OSCACDL_MASK -#define DDR_PHY_PGCR0_OSCACDL_DEFVAL 0x07001E00 -#define DDR_PHY_PGCR0_OSCACDL_SHIFT 24 -#define DDR_PHY_PGCR0_OSCACDL_MASK 0x03000000U +#define DDR_PHY_PGCR0_OSCACDL_DEFVAL 0x07001E00 +#define DDR_PHY_PGCR0_OSCACDL_SHIFT 24 +#define DDR_PHY_PGCR0_OSCACDL_MASK 0x03000000U -/*Reserved. Returns zeroes on reads.*/ +/* +* Reserved. Returns zeroes on reads. +*/ #undef DDR_PHY_PGCR0_RESERVED_23_19_DEFVAL #undef DDR_PHY_PGCR0_RESERVED_23_19_SHIFT #undef DDR_PHY_PGCR0_RESERVED_23_19_MASK -#define DDR_PHY_PGCR0_RESERVED_23_19_DEFVAL 0x07001E00 -#define DDR_PHY_PGCR0_RESERVED_23_19_SHIFT 19 -#define DDR_PHY_PGCR0_RESERVED_23_19_MASK 0x00F80000U +#define DDR_PHY_PGCR0_RESERVED_23_19_DEFVAL 0x07001E00 +#define DDR_PHY_PGCR0_RESERVED_23_19_SHIFT 19 +#define DDR_PHY_PGCR0_RESERVED_23_19_MASK 0x00F80000U -/*Digital Test Output Select*/ +/* +* Digital Test Output Select +*/ #undef DDR_PHY_PGCR0_DTOSEL_DEFVAL #undef DDR_PHY_PGCR0_DTOSEL_SHIFT #undef DDR_PHY_PGCR0_DTOSEL_MASK -#define DDR_PHY_PGCR0_DTOSEL_DEFVAL 0x07001E00 -#define DDR_PHY_PGCR0_DTOSEL_SHIFT 14 -#define DDR_PHY_PGCR0_DTOSEL_MASK 0x0007C000U +#define DDR_PHY_PGCR0_DTOSEL_DEFVAL 0x07001E00 +#define DDR_PHY_PGCR0_DTOSEL_SHIFT 14 +#define DDR_PHY_PGCR0_DTOSEL_MASK 0x0007C000U -/*Reserved. Returns zeroes on reads.*/ +/* +* Reserved. Returns zeroes on reads. +*/ #undef DDR_PHY_PGCR0_RESERVED_13_DEFVAL #undef DDR_PHY_PGCR0_RESERVED_13_SHIFT #undef DDR_PHY_PGCR0_RESERVED_13_MASK -#define DDR_PHY_PGCR0_RESERVED_13_DEFVAL 0x07001E00 -#define DDR_PHY_PGCR0_RESERVED_13_SHIFT 13 -#define DDR_PHY_PGCR0_RESERVED_13_MASK 0x00002000U +#define DDR_PHY_PGCR0_RESERVED_13_DEFVAL 0x07001E00 +#define DDR_PHY_PGCR0_RESERVED_13_SHIFT 13 +#define DDR_PHY_PGCR0_RESERVED_13_MASK 0x00002000U -/*Oscillator Mode Division*/ +/* +* Oscillator Mode Division +*/ #undef DDR_PHY_PGCR0_OSCDIV_DEFVAL #undef DDR_PHY_PGCR0_OSCDIV_SHIFT #undef DDR_PHY_PGCR0_OSCDIV_MASK -#define DDR_PHY_PGCR0_OSCDIV_DEFVAL 0x07001E00 -#define DDR_PHY_PGCR0_OSCDIV_SHIFT 9 -#define DDR_PHY_PGCR0_OSCDIV_MASK 0x00001E00U +#define DDR_PHY_PGCR0_OSCDIV_DEFVAL 0x07001E00 +#define DDR_PHY_PGCR0_OSCDIV_SHIFT 9 +#define DDR_PHY_PGCR0_OSCDIV_MASK 0x00001E00U -/*Oscillator Enable*/ +/* +* Oscillator Enable +*/ #undef DDR_PHY_PGCR0_OSCEN_DEFVAL #undef DDR_PHY_PGCR0_OSCEN_SHIFT #undef DDR_PHY_PGCR0_OSCEN_MASK -#define DDR_PHY_PGCR0_OSCEN_DEFVAL 0x07001E00 -#define DDR_PHY_PGCR0_OSCEN_SHIFT 8 -#define DDR_PHY_PGCR0_OSCEN_MASK 0x00000100U +#define DDR_PHY_PGCR0_OSCEN_DEFVAL 0x07001E00 +#define DDR_PHY_PGCR0_OSCEN_SHIFT 8 +#define DDR_PHY_PGCR0_OSCEN_MASK 0x00000100U -/*Reserved. Returns zeroes on reads.*/ +/* +* Reserved. Returns zeroes on reads. +*/ #undef DDR_PHY_PGCR0_RESERVED_7_0_DEFVAL #undef DDR_PHY_PGCR0_RESERVED_7_0_SHIFT #undef DDR_PHY_PGCR0_RESERVED_7_0_MASK -#define DDR_PHY_PGCR0_RESERVED_7_0_DEFVAL 0x07001E00 -#define DDR_PHY_PGCR0_RESERVED_7_0_SHIFT 0 -#define DDR_PHY_PGCR0_RESERVED_7_0_MASK 0x000000FFU +#define DDR_PHY_PGCR0_RESERVED_7_0_DEFVAL 0x07001E00 +#define DDR_PHY_PGCR0_RESERVED_7_0_SHIFT 0 +#define DDR_PHY_PGCR0_RESERVED_7_0_MASK 0x000000FFU -/*Clear Training Status Registers*/ +/* +* Clear Training Status Registers +*/ #undef DDR_PHY_PGCR2_CLRTSTAT_DEFVAL #undef DDR_PHY_PGCR2_CLRTSTAT_SHIFT #undef DDR_PHY_PGCR2_CLRTSTAT_MASK -#define DDR_PHY_PGCR2_CLRTSTAT_DEFVAL 0x00F12480 -#define DDR_PHY_PGCR2_CLRTSTAT_SHIFT 31 -#define DDR_PHY_PGCR2_CLRTSTAT_MASK 0x80000000U +#define DDR_PHY_PGCR2_CLRTSTAT_DEFVAL 0x00F12480 +#define DDR_PHY_PGCR2_CLRTSTAT_SHIFT 31 +#define DDR_PHY_PGCR2_CLRTSTAT_MASK 0x80000000U -/*Clear Impedance Calibration*/ +/* +* Clear Impedance Calibration +*/ #undef DDR_PHY_PGCR2_CLRZCAL_DEFVAL #undef DDR_PHY_PGCR2_CLRZCAL_SHIFT #undef DDR_PHY_PGCR2_CLRZCAL_MASK -#define DDR_PHY_PGCR2_CLRZCAL_DEFVAL 0x00F12480 -#define DDR_PHY_PGCR2_CLRZCAL_SHIFT 30 -#define DDR_PHY_PGCR2_CLRZCAL_MASK 0x40000000U +#define DDR_PHY_PGCR2_CLRZCAL_DEFVAL 0x00F12480 +#define DDR_PHY_PGCR2_CLRZCAL_SHIFT 30 +#define DDR_PHY_PGCR2_CLRZCAL_MASK 0x40000000U -/*Clear Parity Error*/ +/* +* Clear Parity Error +*/ #undef DDR_PHY_PGCR2_CLRPERR_DEFVAL #undef DDR_PHY_PGCR2_CLRPERR_SHIFT #undef DDR_PHY_PGCR2_CLRPERR_MASK -#define DDR_PHY_PGCR2_CLRPERR_DEFVAL 0x00F12480 -#define DDR_PHY_PGCR2_CLRPERR_SHIFT 29 -#define DDR_PHY_PGCR2_CLRPERR_MASK 0x20000000U +#define DDR_PHY_PGCR2_CLRPERR_DEFVAL 0x00F12480 +#define DDR_PHY_PGCR2_CLRPERR_SHIFT 29 +#define DDR_PHY_PGCR2_CLRPERR_MASK 0x20000000U -/*Initialization Complete Pin Configuration*/ +/* +* Initialization Complete Pin Configuration +*/ #undef DDR_PHY_PGCR2_ICPC_DEFVAL #undef DDR_PHY_PGCR2_ICPC_SHIFT #undef DDR_PHY_PGCR2_ICPC_MASK -#define DDR_PHY_PGCR2_ICPC_DEFVAL 0x00F12480 -#define DDR_PHY_PGCR2_ICPC_SHIFT 28 -#define DDR_PHY_PGCR2_ICPC_MASK 0x10000000U +#define DDR_PHY_PGCR2_ICPC_DEFVAL 0x00F12480 +#define DDR_PHY_PGCR2_ICPC_SHIFT 28 +#define DDR_PHY_PGCR2_ICPC_MASK 0x10000000U -/*Data Training PUB Mode Exit Timer*/ +/* +* Data Training PUB Mode Exit Timer +*/ #undef DDR_PHY_PGCR2_DTPMXTMR_DEFVAL #undef DDR_PHY_PGCR2_DTPMXTMR_SHIFT #undef DDR_PHY_PGCR2_DTPMXTMR_MASK -#define DDR_PHY_PGCR2_DTPMXTMR_DEFVAL 0x00F12480 -#define DDR_PHY_PGCR2_DTPMXTMR_SHIFT 20 -#define DDR_PHY_PGCR2_DTPMXTMR_MASK 0x0FF00000U +#define DDR_PHY_PGCR2_DTPMXTMR_DEFVAL 0x00F12480 +#define DDR_PHY_PGCR2_DTPMXTMR_SHIFT 20 +#define DDR_PHY_PGCR2_DTPMXTMR_MASK 0x0FF00000U -/*Initialization Bypass*/ +/* +* Initialization Bypass +*/ #undef DDR_PHY_PGCR2_INITFSMBYP_DEFVAL #undef DDR_PHY_PGCR2_INITFSMBYP_SHIFT #undef DDR_PHY_PGCR2_INITFSMBYP_MASK -#define DDR_PHY_PGCR2_INITFSMBYP_DEFVAL 0x00F12480 -#define DDR_PHY_PGCR2_INITFSMBYP_SHIFT 19 -#define DDR_PHY_PGCR2_INITFSMBYP_MASK 0x00080000U +#define DDR_PHY_PGCR2_INITFSMBYP_DEFVAL 0x00F12480 +#define DDR_PHY_PGCR2_INITFSMBYP_SHIFT 19 +#define DDR_PHY_PGCR2_INITFSMBYP_MASK 0x00080000U -/*PLL FSM Bypass*/ +/* +* PLL FSM Bypass +*/ #undef DDR_PHY_PGCR2_PLLFSMBYP_DEFVAL #undef DDR_PHY_PGCR2_PLLFSMBYP_SHIFT #undef DDR_PHY_PGCR2_PLLFSMBYP_MASK -#define DDR_PHY_PGCR2_PLLFSMBYP_DEFVAL 0x00F12480 -#define DDR_PHY_PGCR2_PLLFSMBYP_SHIFT 18 -#define DDR_PHY_PGCR2_PLLFSMBYP_MASK 0x00040000U +#define DDR_PHY_PGCR2_PLLFSMBYP_DEFVAL 0x00F12480 +#define DDR_PHY_PGCR2_PLLFSMBYP_SHIFT 18 +#define DDR_PHY_PGCR2_PLLFSMBYP_MASK 0x00040000U -/*Refresh Period*/ +/* +* Refresh Period +*/ #undef DDR_PHY_PGCR2_TREFPRD_DEFVAL #undef DDR_PHY_PGCR2_TREFPRD_SHIFT #undef DDR_PHY_PGCR2_TREFPRD_MASK -#define DDR_PHY_PGCR2_TREFPRD_DEFVAL 0x00F12480 -#define DDR_PHY_PGCR2_TREFPRD_SHIFT 0 -#define DDR_PHY_PGCR2_TREFPRD_MASK 0x0003FFFFU +#define DDR_PHY_PGCR2_TREFPRD_DEFVAL 0x00F12480 +#define DDR_PHY_PGCR2_TREFPRD_SHIFT 0 +#define DDR_PHY_PGCR2_TREFPRD_MASK 0x0003FFFFU -/*CKN Enable*/ +/* +* CKN Enable +*/ #undef DDR_PHY_PGCR3_CKNEN_DEFVAL #undef DDR_PHY_PGCR3_CKNEN_SHIFT #undef DDR_PHY_PGCR3_CKNEN_MASK -#define DDR_PHY_PGCR3_CKNEN_DEFVAL 0x55AA0080 -#define DDR_PHY_PGCR3_CKNEN_SHIFT 24 -#define DDR_PHY_PGCR3_CKNEN_MASK 0xFF000000U +#define DDR_PHY_PGCR3_CKNEN_DEFVAL 0x55AA0080 +#define DDR_PHY_PGCR3_CKNEN_SHIFT 24 +#define DDR_PHY_PGCR3_CKNEN_MASK 0xFF000000U -/*CK Enable*/ +/* +* CK Enable +*/ #undef DDR_PHY_PGCR3_CKEN_DEFVAL #undef DDR_PHY_PGCR3_CKEN_SHIFT #undef DDR_PHY_PGCR3_CKEN_MASK -#define DDR_PHY_PGCR3_CKEN_DEFVAL 0x55AA0080 -#define DDR_PHY_PGCR3_CKEN_SHIFT 16 -#define DDR_PHY_PGCR3_CKEN_MASK 0x00FF0000U +#define DDR_PHY_PGCR3_CKEN_DEFVAL 0x55AA0080 +#define DDR_PHY_PGCR3_CKEN_SHIFT 16 +#define DDR_PHY_PGCR3_CKEN_MASK 0x00FF0000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_PGCR3_RESERVED_15_DEFVAL #undef DDR_PHY_PGCR3_RESERVED_15_SHIFT #undef DDR_PHY_PGCR3_RESERVED_15_MASK -#define DDR_PHY_PGCR3_RESERVED_15_DEFVAL 0x55AA0080 -#define DDR_PHY_PGCR3_RESERVED_15_SHIFT 15 -#define DDR_PHY_PGCR3_RESERVED_15_MASK 0x00008000U +#define DDR_PHY_PGCR3_RESERVED_15_DEFVAL 0x55AA0080 +#define DDR_PHY_PGCR3_RESERVED_15_SHIFT 15 +#define DDR_PHY_PGCR3_RESERVED_15_MASK 0x00008000U -/*Enable Clock Gating for AC [0] ctl_rd_clk*/ +/* +* Enable Clock Gating for AC [0] ctl_rd_clk +*/ #undef DDR_PHY_PGCR3_GATEACRDCLK_DEFVAL #undef DDR_PHY_PGCR3_GATEACRDCLK_SHIFT #undef DDR_PHY_PGCR3_GATEACRDCLK_MASK -#define DDR_PHY_PGCR3_GATEACRDCLK_DEFVAL 0x55AA0080 -#define DDR_PHY_PGCR3_GATEACRDCLK_SHIFT 13 -#define DDR_PHY_PGCR3_GATEACRDCLK_MASK 0x00006000U +#define DDR_PHY_PGCR3_GATEACRDCLK_DEFVAL 0x55AA0080 +#define DDR_PHY_PGCR3_GATEACRDCLK_SHIFT 13 +#define DDR_PHY_PGCR3_GATEACRDCLK_MASK 0x00006000U -/*Enable Clock Gating for AC [0] ddr_clk*/ +/* +* Enable Clock Gating for AC [0] ddr_clk +*/ #undef DDR_PHY_PGCR3_GATEACDDRCLK_DEFVAL #undef DDR_PHY_PGCR3_GATEACDDRCLK_SHIFT #undef DDR_PHY_PGCR3_GATEACDDRCLK_MASK -#define DDR_PHY_PGCR3_GATEACDDRCLK_DEFVAL 0x55AA0080 -#define DDR_PHY_PGCR3_GATEACDDRCLK_SHIFT 11 -#define DDR_PHY_PGCR3_GATEACDDRCLK_MASK 0x00001800U +#define DDR_PHY_PGCR3_GATEACDDRCLK_DEFVAL 0x55AA0080 +#define DDR_PHY_PGCR3_GATEACDDRCLK_SHIFT 11 +#define DDR_PHY_PGCR3_GATEACDDRCLK_MASK 0x00001800U -/*Enable Clock Gating for AC [0] ctl_clk*/ +/* +* Enable Clock Gating for AC [0] ctl_clk +*/ #undef DDR_PHY_PGCR3_GATEACCTLCLK_DEFVAL #undef DDR_PHY_PGCR3_GATEACCTLCLK_SHIFT #undef DDR_PHY_PGCR3_GATEACCTLCLK_MASK -#define DDR_PHY_PGCR3_GATEACCTLCLK_DEFVAL 0x55AA0080 -#define DDR_PHY_PGCR3_GATEACCTLCLK_SHIFT 9 -#define DDR_PHY_PGCR3_GATEACCTLCLK_MASK 0x00000600U +#define DDR_PHY_PGCR3_GATEACCTLCLK_DEFVAL 0x55AA0080 +#define DDR_PHY_PGCR3_GATEACCTLCLK_SHIFT 9 +#define DDR_PHY_PGCR3_GATEACCTLCLK_MASK 0x00000600U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_PGCR3_RESERVED_8_DEFVAL #undef DDR_PHY_PGCR3_RESERVED_8_SHIFT #undef DDR_PHY_PGCR3_RESERVED_8_MASK -#define DDR_PHY_PGCR3_RESERVED_8_DEFVAL 0x55AA0080 -#define DDR_PHY_PGCR3_RESERVED_8_SHIFT 8 -#define DDR_PHY_PGCR3_RESERVED_8_MASK 0x00000100U +#define DDR_PHY_PGCR3_RESERVED_8_DEFVAL 0x55AA0080 +#define DDR_PHY_PGCR3_RESERVED_8_SHIFT 8 +#define DDR_PHY_PGCR3_RESERVED_8_MASK 0x00000100U -/*Controls DDL Bypass Modes*/ +/* +* Controls DDL Bypass Modes +*/ #undef DDR_PHY_PGCR3_DDLBYPMODE_DEFVAL #undef DDR_PHY_PGCR3_DDLBYPMODE_SHIFT #undef DDR_PHY_PGCR3_DDLBYPMODE_MASK -#define DDR_PHY_PGCR3_DDLBYPMODE_DEFVAL 0x55AA0080 -#define DDR_PHY_PGCR3_DDLBYPMODE_SHIFT 6 -#define DDR_PHY_PGCR3_DDLBYPMODE_MASK 0x000000C0U +#define DDR_PHY_PGCR3_DDLBYPMODE_DEFVAL 0x55AA0080 +#define DDR_PHY_PGCR3_DDLBYPMODE_SHIFT 6 +#define DDR_PHY_PGCR3_DDLBYPMODE_MASK 0x000000C0U -/*IO Loop-Back Select*/ +/* +* IO Loop-Back Select +*/ #undef DDR_PHY_PGCR3_IOLB_DEFVAL #undef DDR_PHY_PGCR3_IOLB_SHIFT #undef DDR_PHY_PGCR3_IOLB_MASK -#define DDR_PHY_PGCR3_IOLB_DEFVAL 0x55AA0080 -#define DDR_PHY_PGCR3_IOLB_SHIFT 5 -#define DDR_PHY_PGCR3_IOLB_MASK 0x00000020U +#define DDR_PHY_PGCR3_IOLB_DEFVAL 0x55AA0080 +#define DDR_PHY_PGCR3_IOLB_SHIFT 5 +#define DDR_PHY_PGCR3_IOLB_MASK 0x00000020U -/*AC Receive FIFO Read Mode*/ +/* +* AC Receive FIFO Read Mode +*/ #undef DDR_PHY_PGCR3_RDMODE_DEFVAL #undef DDR_PHY_PGCR3_RDMODE_SHIFT #undef DDR_PHY_PGCR3_RDMODE_MASK -#define DDR_PHY_PGCR3_RDMODE_DEFVAL 0x55AA0080 -#define DDR_PHY_PGCR3_RDMODE_SHIFT 3 -#define DDR_PHY_PGCR3_RDMODE_MASK 0x00000018U +#define DDR_PHY_PGCR3_RDMODE_DEFVAL 0x55AA0080 +#define DDR_PHY_PGCR3_RDMODE_SHIFT 3 +#define DDR_PHY_PGCR3_RDMODE_MASK 0x00000018U -/*Read FIFO Reset Disable*/ +/* +* Read FIFO Reset Disable +*/ #undef DDR_PHY_PGCR3_DISRST_DEFVAL #undef DDR_PHY_PGCR3_DISRST_SHIFT #undef DDR_PHY_PGCR3_DISRST_MASK -#define DDR_PHY_PGCR3_DISRST_DEFVAL 0x55AA0080 -#define DDR_PHY_PGCR3_DISRST_SHIFT 2 -#define DDR_PHY_PGCR3_DISRST_MASK 0x00000004U +#define DDR_PHY_PGCR3_DISRST_DEFVAL 0x55AA0080 +#define DDR_PHY_PGCR3_DISRST_SHIFT 2 +#define DDR_PHY_PGCR3_DISRST_MASK 0x00000004U -/*Clock Level when Clock Gating*/ +/* +* Clock Level when Clock Gating +*/ #undef DDR_PHY_PGCR3_CLKLEVEL_DEFVAL #undef DDR_PHY_PGCR3_CLKLEVEL_SHIFT #undef DDR_PHY_PGCR3_CLKLEVEL_MASK -#define DDR_PHY_PGCR3_CLKLEVEL_DEFVAL 0x55AA0080 -#define DDR_PHY_PGCR3_CLKLEVEL_SHIFT 0 -#define DDR_PHY_PGCR3_CLKLEVEL_MASK 0x00000003U +#define DDR_PHY_PGCR3_CLKLEVEL_DEFVAL 0x55AA0080 +#define DDR_PHY_PGCR3_CLKLEVEL_SHIFT 0 +#define DDR_PHY_PGCR3_CLKLEVEL_MASK 0x00000003U -/*Frequency B Ratio Term*/ +/* +* Frequency B Ratio Term +*/ #undef DDR_PHY_PGCR5_FRQBT_DEFVAL #undef DDR_PHY_PGCR5_FRQBT_SHIFT #undef DDR_PHY_PGCR5_FRQBT_MASK -#define DDR_PHY_PGCR5_FRQBT_DEFVAL 0x01010000 -#define DDR_PHY_PGCR5_FRQBT_SHIFT 24 -#define DDR_PHY_PGCR5_FRQBT_MASK 0xFF000000U +#define DDR_PHY_PGCR5_FRQBT_DEFVAL 0x01010000 +#define DDR_PHY_PGCR5_FRQBT_SHIFT 24 +#define DDR_PHY_PGCR5_FRQBT_MASK 0xFF000000U -/*Frequency A Ratio Term*/ +/* +* Frequency A Ratio Term +*/ #undef DDR_PHY_PGCR5_FRQAT_DEFVAL #undef DDR_PHY_PGCR5_FRQAT_SHIFT #undef DDR_PHY_PGCR5_FRQAT_MASK -#define DDR_PHY_PGCR5_FRQAT_DEFVAL 0x01010000 -#define DDR_PHY_PGCR5_FRQAT_SHIFT 16 -#define DDR_PHY_PGCR5_FRQAT_MASK 0x00FF0000U +#define DDR_PHY_PGCR5_FRQAT_DEFVAL 0x01010000 +#define DDR_PHY_PGCR5_FRQAT_SHIFT 16 +#define DDR_PHY_PGCR5_FRQAT_MASK 0x00FF0000U -/*DFI Disconnect Time Period*/ +/* +* DFI Disconnect Time Period +*/ #undef DDR_PHY_PGCR5_DISCNPERIOD_DEFVAL #undef DDR_PHY_PGCR5_DISCNPERIOD_SHIFT #undef DDR_PHY_PGCR5_DISCNPERIOD_MASK -#define DDR_PHY_PGCR5_DISCNPERIOD_DEFVAL 0x01010000 -#define DDR_PHY_PGCR5_DISCNPERIOD_SHIFT 8 -#define DDR_PHY_PGCR5_DISCNPERIOD_MASK 0x0000FF00U +#define DDR_PHY_PGCR5_DISCNPERIOD_DEFVAL 0x01010000 +#define DDR_PHY_PGCR5_DISCNPERIOD_SHIFT 8 +#define DDR_PHY_PGCR5_DISCNPERIOD_MASK 0x0000FF00U -/*Receiver bias core side control*/ +/* +* Receiver bias core side control +*/ #undef DDR_PHY_PGCR5_VREF_RBCTRL_DEFVAL #undef DDR_PHY_PGCR5_VREF_RBCTRL_SHIFT #undef DDR_PHY_PGCR5_VREF_RBCTRL_MASK -#define DDR_PHY_PGCR5_VREF_RBCTRL_DEFVAL 0x01010000 -#define DDR_PHY_PGCR5_VREF_RBCTRL_SHIFT 4 -#define DDR_PHY_PGCR5_VREF_RBCTRL_MASK 0x000000F0U +#define DDR_PHY_PGCR5_VREF_RBCTRL_DEFVAL 0x01010000 +#define DDR_PHY_PGCR5_VREF_RBCTRL_SHIFT 4 +#define DDR_PHY_PGCR5_VREF_RBCTRL_MASK 0x000000F0U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_PGCR5_RESERVED_3_DEFVAL #undef DDR_PHY_PGCR5_RESERVED_3_SHIFT #undef DDR_PHY_PGCR5_RESERVED_3_MASK -#define DDR_PHY_PGCR5_RESERVED_3_DEFVAL 0x01010000 -#define DDR_PHY_PGCR5_RESERVED_3_SHIFT 3 -#define DDR_PHY_PGCR5_RESERVED_3_MASK 0x00000008U +#define DDR_PHY_PGCR5_RESERVED_3_DEFVAL 0x01010000 +#define DDR_PHY_PGCR5_RESERVED_3_SHIFT 3 +#define DDR_PHY_PGCR5_RESERVED_3_MASK 0x00000008U -/*Internal VREF generator REFSEL ragne select*/ +/* +* Internal VREF generator REFSEL ragne select +*/ #undef DDR_PHY_PGCR5_DXREFISELRANGE_DEFVAL #undef DDR_PHY_PGCR5_DXREFISELRANGE_SHIFT #undef DDR_PHY_PGCR5_DXREFISELRANGE_MASK -#define DDR_PHY_PGCR5_DXREFISELRANGE_DEFVAL 0x01010000 -#define DDR_PHY_PGCR5_DXREFISELRANGE_SHIFT 2 -#define DDR_PHY_PGCR5_DXREFISELRANGE_MASK 0x00000004U +#define DDR_PHY_PGCR5_DXREFISELRANGE_DEFVAL 0x01010000 +#define DDR_PHY_PGCR5_DXREFISELRANGE_SHIFT 2 +#define DDR_PHY_PGCR5_DXREFISELRANGE_MASK 0x00000004U -/*DDL Page Read Write select*/ +/* +* DDL Page Read Write select +*/ #undef DDR_PHY_PGCR5_DDLPGACT_DEFVAL #undef DDR_PHY_PGCR5_DDLPGACT_SHIFT #undef DDR_PHY_PGCR5_DDLPGACT_MASK -#define DDR_PHY_PGCR5_DDLPGACT_DEFVAL 0x01010000 -#define DDR_PHY_PGCR5_DDLPGACT_SHIFT 1 -#define DDR_PHY_PGCR5_DDLPGACT_MASK 0x00000002U +#define DDR_PHY_PGCR5_DDLPGACT_DEFVAL 0x01010000 +#define DDR_PHY_PGCR5_DDLPGACT_SHIFT 1 +#define DDR_PHY_PGCR5_DDLPGACT_MASK 0x00000002U -/*DDL Page Read Write select*/ +/* +* DDL Page Read Write select +*/ #undef DDR_PHY_PGCR5_DDLPGRW_DEFVAL #undef DDR_PHY_PGCR5_DDLPGRW_SHIFT #undef DDR_PHY_PGCR5_DDLPGRW_MASK -#define DDR_PHY_PGCR5_DDLPGRW_DEFVAL 0x01010000 -#define DDR_PHY_PGCR5_DDLPGRW_SHIFT 0 -#define DDR_PHY_PGCR5_DDLPGRW_MASK 0x00000001U +#define DDR_PHY_PGCR5_DDLPGRW_DEFVAL 0x01010000 +#define DDR_PHY_PGCR5_DDLPGRW_SHIFT 0 +#define DDR_PHY_PGCR5_DDLPGRW_MASK 0x00000001U -/*PLL Power-Down Time*/ +/* +* PLL Power-Down Time +*/ #undef DDR_PHY_PTR0_TPLLPD_DEFVAL #undef DDR_PHY_PTR0_TPLLPD_SHIFT #undef DDR_PHY_PTR0_TPLLPD_MASK -#define DDR_PHY_PTR0_TPLLPD_DEFVAL 0x42C21590 -#define DDR_PHY_PTR0_TPLLPD_SHIFT 21 -#define DDR_PHY_PTR0_TPLLPD_MASK 0xFFE00000U +#define DDR_PHY_PTR0_TPLLPD_DEFVAL 0x42C21590 +#define DDR_PHY_PTR0_TPLLPD_SHIFT 21 +#define DDR_PHY_PTR0_TPLLPD_MASK 0xFFE00000U -/*PLL Gear Shift Time*/ +/* +* PLL Gear Shift Time +*/ #undef DDR_PHY_PTR0_TPLLGS_DEFVAL #undef DDR_PHY_PTR0_TPLLGS_SHIFT #undef DDR_PHY_PTR0_TPLLGS_MASK -#define DDR_PHY_PTR0_TPLLGS_DEFVAL 0x42C21590 -#define DDR_PHY_PTR0_TPLLGS_SHIFT 6 -#define DDR_PHY_PTR0_TPLLGS_MASK 0x001FFFC0U +#define DDR_PHY_PTR0_TPLLGS_DEFVAL 0x42C21590 +#define DDR_PHY_PTR0_TPLLGS_SHIFT 6 +#define DDR_PHY_PTR0_TPLLGS_MASK 0x001FFFC0U -/*PHY Reset Time*/ +/* +* PHY Reset Time +*/ #undef DDR_PHY_PTR0_TPHYRST_DEFVAL #undef DDR_PHY_PTR0_TPHYRST_SHIFT #undef DDR_PHY_PTR0_TPHYRST_MASK -#define DDR_PHY_PTR0_TPHYRST_DEFVAL 0x42C21590 -#define DDR_PHY_PTR0_TPHYRST_SHIFT 0 -#define DDR_PHY_PTR0_TPHYRST_MASK 0x0000003FU +#define DDR_PHY_PTR0_TPHYRST_DEFVAL 0x42C21590 +#define DDR_PHY_PTR0_TPHYRST_SHIFT 0 +#define DDR_PHY_PTR0_TPHYRST_MASK 0x0000003FU -/*PLL Lock Time*/ +/* +* PLL Lock Time +*/ #undef DDR_PHY_PTR1_TPLLLOCK_DEFVAL #undef DDR_PHY_PTR1_TPLLLOCK_SHIFT #undef DDR_PHY_PTR1_TPLLLOCK_MASK -#define DDR_PHY_PTR1_TPLLLOCK_DEFVAL 0xD05612C0 -#define DDR_PHY_PTR1_TPLLLOCK_SHIFT 16 -#define DDR_PHY_PTR1_TPLLLOCK_MASK 0xFFFF0000U +#define DDR_PHY_PTR1_TPLLLOCK_DEFVAL 0xD05612C0 +#define DDR_PHY_PTR1_TPLLLOCK_SHIFT 16 +#define DDR_PHY_PTR1_TPLLLOCK_MASK 0xFFFF0000U -/*Reserved. Returns zeroes on reads.*/ +/* +* Reserved. Returns zeroes on reads. +*/ #undef DDR_PHY_PTR1_RESERVED_15_13_DEFVAL #undef DDR_PHY_PTR1_RESERVED_15_13_SHIFT #undef DDR_PHY_PTR1_RESERVED_15_13_MASK -#define DDR_PHY_PTR1_RESERVED_15_13_DEFVAL 0xD05612C0 -#define DDR_PHY_PTR1_RESERVED_15_13_SHIFT 13 -#define DDR_PHY_PTR1_RESERVED_15_13_MASK 0x0000E000U +#define DDR_PHY_PTR1_RESERVED_15_13_DEFVAL 0xD05612C0 +#define DDR_PHY_PTR1_RESERVED_15_13_SHIFT 13 +#define DDR_PHY_PTR1_RESERVED_15_13_MASK 0x0000E000U -/*PLL Reset Time*/ +/* +* PLL Reset Time +*/ #undef DDR_PHY_PTR1_TPLLRST_DEFVAL #undef DDR_PHY_PTR1_TPLLRST_SHIFT #undef DDR_PHY_PTR1_TPLLRST_MASK -#define DDR_PHY_PTR1_TPLLRST_DEFVAL 0xD05612C0 -#define DDR_PHY_PTR1_TPLLRST_SHIFT 0 -#define DDR_PHY_PTR1_TPLLRST_MASK 0x00001FFFU +#define DDR_PHY_PTR1_TPLLRST_DEFVAL 0xD05612C0 +#define DDR_PHY_PTR1_TPLLRST_SHIFT 0 +#define DDR_PHY_PTR1_TPLLRST_MASK 0x00001FFFU -/*Reserved. Return zeroes on reads.*/ +/* +* PLL Bypass +*/ +#undef DDR_PHY_PLLCR0_PLLBYP_DEFVAL +#undef DDR_PHY_PLLCR0_PLLBYP_SHIFT +#undef DDR_PHY_PLLCR0_PLLBYP_MASK +#define DDR_PHY_PLLCR0_PLLBYP_DEFVAL 0x001C0000 +#define DDR_PHY_PLLCR0_PLLBYP_SHIFT 31 +#define DDR_PHY_PLLCR0_PLLBYP_MASK 0x80000000U + +/* +* PLL Reset +*/ +#undef DDR_PHY_PLLCR0_PLLRST_DEFVAL +#undef DDR_PHY_PLLCR0_PLLRST_SHIFT +#undef DDR_PHY_PLLCR0_PLLRST_MASK +#define DDR_PHY_PLLCR0_PLLRST_DEFVAL 0x001C0000 +#define DDR_PHY_PLLCR0_PLLRST_SHIFT 30 +#define DDR_PHY_PLLCR0_PLLRST_MASK 0x40000000U + +/* +* PLL Power Down +*/ +#undef DDR_PHY_PLLCR0_PLLPD_DEFVAL +#undef DDR_PHY_PLLCR0_PLLPD_SHIFT +#undef DDR_PHY_PLLCR0_PLLPD_MASK +#define DDR_PHY_PLLCR0_PLLPD_DEFVAL 0x001C0000 +#define DDR_PHY_PLLCR0_PLLPD_SHIFT 29 +#define DDR_PHY_PLLCR0_PLLPD_MASK 0x20000000U + +/* +* Reference Stop Mode +*/ +#undef DDR_PHY_PLLCR0_RSTOPM_DEFVAL +#undef DDR_PHY_PLLCR0_RSTOPM_SHIFT +#undef DDR_PHY_PLLCR0_RSTOPM_MASK +#define DDR_PHY_PLLCR0_RSTOPM_DEFVAL 0x001C0000 +#define DDR_PHY_PLLCR0_RSTOPM_SHIFT 28 +#define DDR_PHY_PLLCR0_RSTOPM_MASK 0x10000000U + +/* +* PLL Frequency Select +*/ +#undef DDR_PHY_PLLCR0_FRQSEL_DEFVAL +#undef DDR_PHY_PLLCR0_FRQSEL_SHIFT +#undef DDR_PHY_PLLCR0_FRQSEL_MASK +#define DDR_PHY_PLLCR0_FRQSEL_DEFVAL 0x001C0000 +#define DDR_PHY_PLLCR0_FRQSEL_SHIFT 24 +#define DDR_PHY_PLLCR0_FRQSEL_MASK 0x0F000000U + +/* +* Relock Mode +*/ +#undef DDR_PHY_PLLCR0_RLOCKM_DEFVAL +#undef DDR_PHY_PLLCR0_RLOCKM_SHIFT +#undef DDR_PHY_PLLCR0_RLOCKM_MASK +#define DDR_PHY_PLLCR0_RLOCKM_DEFVAL 0x001C0000 +#define DDR_PHY_PLLCR0_RLOCKM_SHIFT 23 +#define DDR_PHY_PLLCR0_RLOCKM_MASK 0x00800000U + +/* +* Charge Pump Proportional Current Control +*/ +#undef DDR_PHY_PLLCR0_CPPC_DEFVAL +#undef DDR_PHY_PLLCR0_CPPC_SHIFT +#undef DDR_PHY_PLLCR0_CPPC_MASK +#define DDR_PHY_PLLCR0_CPPC_DEFVAL 0x001C0000 +#define DDR_PHY_PLLCR0_CPPC_SHIFT 17 +#define DDR_PHY_PLLCR0_CPPC_MASK 0x007E0000U + +/* +* Charge Pump Integrating Current Control +*/ +#undef DDR_PHY_PLLCR0_CPIC_DEFVAL +#undef DDR_PHY_PLLCR0_CPIC_SHIFT +#undef DDR_PHY_PLLCR0_CPIC_MASK +#define DDR_PHY_PLLCR0_CPIC_DEFVAL 0x001C0000 +#define DDR_PHY_PLLCR0_CPIC_SHIFT 13 +#define DDR_PHY_PLLCR0_CPIC_MASK 0x0001E000U + +/* +* Gear Shift +*/ +#undef DDR_PHY_PLLCR0_GSHIFT_DEFVAL +#undef DDR_PHY_PLLCR0_GSHIFT_SHIFT +#undef DDR_PHY_PLLCR0_GSHIFT_MASK +#define DDR_PHY_PLLCR0_GSHIFT_DEFVAL 0x001C0000 +#define DDR_PHY_PLLCR0_GSHIFT_SHIFT 12 +#define DDR_PHY_PLLCR0_GSHIFT_MASK 0x00001000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_PLLCR0_RESERVED_11_9_DEFVAL +#undef DDR_PHY_PLLCR0_RESERVED_11_9_SHIFT +#undef DDR_PHY_PLLCR0_RESERVED_11_9_MASK +#define DDR_PHY_PLLCR0_RESERVED_11_9_DEFVAL 0x001C0000 +#define DDR_PHY_PLLCR0_RESERVED_11_9_SHIFT 9 +#define DDR_PHY_PLLCR0_RESERVED_11_9_MASK 0x00000E00U + +/* +* Analog Test Enable +*/ +#undef DDR_PHY_PLLCR0_ATOEN_DEFVAL +#undef DDR_PHY_PLLCR0_ATOEN_SHIFT +#undef DDR_PHY_PLLCR0_ATOEN_MASK +#define DDR_PHY_PLLCR0_ATOEN_DEFVAL 0x001C0000 +#define DDR_PHY_PLLCR0_ATOEN_SHIFT 8 +#define DDR_PHY_PLLCR0_ATOEN_MASK 0x00000100U + +/* +* Analog Test Control +*/ +#undef DDR_PHY_PLLCR0_ATC_DEFVAL +#undef DDR_PHY_PLLCR0_ATC_SHIFT +#undef DDR_PHY_PLLCR0_ATC_MASK +#define DDR_PHY_PLLCR0_ATC_DEFVAL 0x001C0000 +#define DDR_PHY_PLLCR0_ATC_SHIFT 4 +#define DDR_PHY_PLLCR0_ATC_MASK 0x000000F0U + +/* +* Digital Test Control +*/ +#undef DDR_PHY_PLLCR0_DTC_DEFVAL +#undef DDR_PHY_PLLCR0_DTC_SHIFT +#undef DDR_PHY_PLLCR0_DTC_MASK +#define DDR_PHY_PLLCR0_DTC_DEFVAL 0x001C0000 +#define DDR_PHY_PLLCR0_DTC_SHIFT 0 +#define DDR_PHY_PLLCR0_DTC_MASK 0x0000000FU + +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DSGCR_RESERVED_31_28_DEFVAL #undef DDR_PHY_DSGCR_RESERVED_31_28_SHIFT #undef DDR_PHY_DSGCR_RESERVED_31_28_MASK -#define DDR_PHY_DSGCR_RESERVED_31_28_DEFVAL 0x02A04101 -#define DDR_PHY_DSGCR_RESERVED_31_28_SHIFT 28 -#define DDR_PHY_DSGCR_RESERVED_31_28_MASK 0xF0000000U +#define DDR_PHY_DSGCR_RESERVED_31_28_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_RESERVED_31_28_SHIFT 28 +#define DDR_PHY_DSGCR_RESERVED_31_28_MASK 0xF0000000U -/*When RDBI enabled, this bit is used to select RDBI CL calculation, if it is 1b1, calculation will use RDBICL, otherwise use d - fault calculation.*/ +/* +* When RDBI enabled, this bit is used to select RDBI CL calculation, if it + * is 1b1, calculation will use RDBICL, otherwise use default calculation. +*/ #undef DDR_PHY_DSGCR_RDBICLSEL_DEFVAL #undef DDR_PHY_DSGCR_RDBICLSEL_SHIFT #undef DDR_PHY_DSGCR_RDBICLSEL_MASK -#define DDR_PHY_DSGCR_RDBICLSEL_DEFVAL 0x02A04101 -#define DDR_PHY_DSGCR_RDBICLSEL_SHIFT 27 -#define DDR_PHY_DSGCR_RDBICLSEL_MASK 0x08000000U +#define DDR_PHY_DSGCR_RDBICLSEL_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_RDBICLSEL_SHIFT 27 +#define DDR_PHY_DSGCR_RDBICLSEL_MASK 0x08000000U -/*When RDBI enabled, if RDBICLSEL is asserted, RDBI CL adjust using this value.*/ +/* +* When RDBI enabled, if RDBICLSEL is asserted, RDBI CL adjust using this v + * alue. +*/ #undef DDR_PHY_DSGCR_RDBICL_DEFVAL #undef DDR_PHY_DSGCR_RDBICL_SHIFT #undef DDR_PHY_DSGCR_RDBICL_MASK -#define DDR_PHY_DSGCR_RDBICL_DEFVAL 0x02A04101 -#define DDR_PHY_DSGCR_RDBICL_SHIFT 24 -#define DDR_PHY_DSGCR_RDBICL_MASK 0x07000000U +#define DDR_PHY_DSGCR_RDBICL_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_RDBICL_SHIFT 24 +#define DDR_PHY_DSGCR_RDBICL_MASK 0x07000000U -/*PHY Impedance Update Enable*/ +/* +* PHY Impedance Update Enable +*/ #undef DDR_PHY_DSGCR_PHYZUEN_DEFVAL #undef DDR_PHY_DSGCR_PHYZUEN_SHIFT #undef DDR_PHY_DSGCR_PHYZUEN_MASK -#define DDR_PHY_DSGCR_PHYZUEN_DEFVAL 0x02A04101 -#define DDR_PHY_DSGCR_PHYZUEN_SHIFT 23 -#define DDR_PHY_DSGCR_PHYZUEN_MASK 0x00800000U +#define DDR_PHY_DSGCR_PHYZUEN_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_PHYZUEN_SHIFT 23 +#define DDR_PHY_DSGCR_PHYZUEN_MASK 0x00800000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DSGCR_RESERVED_22_DEFVAL #undef DDR_PHY_DSGCR_RESERVED_22_SHIFT #undef DDR_PHY_DSGCR_RESERVED_22_MASK -#define DDR_PHY_DSGCR_RESERVED_22_DEFVAL 0x02A04101 -#define DDR_PHY_DSGCR_RESERVED_22_SHIFT 22 -#define DDR_PHY_DSGCR_RESERVED_22_MASK 0x00400000U +#define DDR_PHY_DSGCR_RESERVED_22_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_RESERVED_22_SHIFT 22 +#define DDR_PHY_DSGCR_RESERVED_22_MASK 0x00400000U -/*SDRAM Reset Output Enable*/ +/* +* SDRAM Reset Output Enable +*/ #undef DDR_PHY_DSGCR_RSTOE_DEFVAL #undef DDR_PHY_DSGCR_RSTOE_SHIFT #undef DDR_PHY_DSGCR_RSTOE_MASK -#define DDR_PHY_DSGCR_RSTOE_DEFVAL 0x02A04101 -#define DDR_PHY_DSGCR_RSTOE_SHIFT 21 -#define DDR_PHY_DSGCR_RSTOE_MASK 0x00200000U +#define DDR_PHY_DSGCR_RSTOE_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_RSTOE_SHIFT 21 +#define DDR_PHY_DSGCR_RSTOE_MASK 0x00200000U -/*Single Data Rate Mode*/ +/* +* Single Data Rate Mode +*/ #undef DDR_PHY_DSGCR_SDRMODE_DEFVAL #undef DDR_PHY_DSGCR_SDRMODE_SHIFT #undef DDR_PHY_DSGCR_SDRMODE_MASK -#define DDR_PHY_DSGCR_SDRMODE_DEFVAL 0x02A04101 -#define DDR_PHY_DSGCR_SDRMODE_SHIFT 19 -#define DDR_PHY_DSGCR_SDRMODE_MASK 0x00180000U +#define DDR_PHY_DSGCR_SDRMODE_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_SDRMODE_SHIFT 19 +#define DDR_PHY_DSGCR_SDRMODE_MASK 0x00180000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DSGCR_RESERVED_18_DEFVAL #undef DDR_PHY_DSGCR_RESERVED_18_SHIFT #undef DDR_PHY_DSGCR_RESERVED_18_MASK -#define DDR_PHY_DSGCR_RESERVED_18_DEFVAL 0x02A04101 -#define DDR_PHY_DSGCR_RESERVED_18_SHIFT 18 -#define DDR_PHY_DSGCR_RESERVED_18_MASK 0x00040000U +#define DDR_PHY_DSGCR_RESERVED_18_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_RESERVED_18_SHIFT 18 +#define DDR_PHY_DSGCR_RESERVED_18_MASK 0x00040000U -/*ATO Analog Test Enable*/ +/* +* ATO Analog Test Enable +*/ #undef DDR_PHY_DSGCR_ATOAE_DEFVAL #undef DDR_PHY_DSGCR_ATOAE_SHIFT #undef DDR_PHY_DSGCR_ATOAE_MASK -#define DDR_PHY_DSGCR_ATOAE_DEFVAL 0x02A04101 -#define DDR_PHY_DSGCR_ATOAE_SHIFT 17 -#define DDR_PHY_DSGCR_ATOAE_MASK 0x00020000U +#define DDR_PHY_DSGCR_ATOAE_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_ATOAE_SHIFT 17 +#define DDR_PHY_DSGCR_ATOAE_MASK 0x00020000U -/*DTO Output Enable*/ +/* +* DTO Output Enable +*/ #undef DDR_PHY_DSGCR_DTOOE_DEFVAL #undef DDR_PHY_DSGCR_DTOOE_SHIFT #undef DDR_PHY_DSGCR_DTOOE_MASK -#define DDR_PHY_DSGCR_DTOOE_DEFVAL 0x02A04101 -#define DDR_PHY_DSGCR_DTOOE_SHIFT 16 -#define DDR_PHY_DSGCR_DTOOE_MASK 0x00010000U +#define DDR_PHY_DSGCR_DTOOE_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_DTOOE_SHIFT 16 +#define DDR_PHY_DSGCR_DTOOE_MASK 0x00010000U -/*DTO I/O Mode*/ +/* +* DTO I/O Mode +*/ #undef DDR_PHY_DSGCR_DTOIOM_DEFVAL #undef DDR_PHY_DSGCR_DTOIOM_SHIFT #undef DDR_PHY_DSGCR_DTOIOM_MASK -#define DDR_PHY_DSGCR_DTOIOM_DEFVAL 0x02A04101 -#define DDR_PHY_DSGCR_DTOIOM_SHIFT 15 -#define DDR_PHY_DSGCR_DTOIOM_MASK 0x00008000U +#define DDR_PHY_DSGCR_DTOIOM_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_DTOIOM_SHIFT 15 +#define DDR_PHY_DSGCR_DTOIOM_MASK 0x00008000U -/*DTO Power Down Receiver*/ +/* +* DTO Power Down Receiver +*/ #undef DDR_PHY_DSGCR_DTOPDR_DEFVAL #undef DDR_PHY_DSGCR_DTOPDR_SHIFT #undef DDR_PHY_DSGCR_DTOPDR_MASK -#define DDR_PHY_DSGCR_DTOPDR_DEFVAL 0x02A04101 -#define DDR_PHY_DSGCR_DTOPDR_SHIFT 14 -#define DDR_PHY_DSGCR_DTOPDR_MASK 0x00004000U +#define DDR_PHY_DSGCR_DTOPDR_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_DTOPDR_SHIFT 14 +#define DDR_PHY_DSGCR_DTOPDR_MASK 0x00004000U -/*Reserved. Return zeroes on reads*/ +/* +* Reserved. Return zeroes on reads +*/ #undef DDR_PHY_DSGCR_RESERVED_13_DEFVAL #undef DDR_PHY_DSGCR_RESERVED_13_SHIFT #undef DDR_PHY_DSGCR_RESERVED_13_MASK -#define DDR_PHY_DSGCR_RESERVED_13_DEFVAL 0x02A04101 -#define DDR_PHY_DSGCR_RESERVED_13_SHIFT 13 -#define DDR_PHY_DSGCR_RESERVED_13_MASK 0x00002000U +#define DDR_PHY_DSGCR_RESERVED_13_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_RESERVED_13_SHIFT 13 +#define DDR_PHY_DSGCR_RESERVED_13_MASK 0x00002000U -/*DTO On-Die Termination*/ +/* +* DTO On-Die Termination +*/ #undef DDR_PHY_DSGCR_DTOODT_DEFVAL #undef DDR_PHY_DSGCR_DTOODT_SHIFT #undef DDR_PHY_DSGCR_DTOODT_MASK -#define DDR_PHY_DSGCR_DTOODT_DEFVAL 0x02A04101 -#define DDR_PHY_DSGCR_DTOODT_SHIFT 12 -#define DDR_PHY_DSGCR_DTOODT_MASK 0x00001000U +#define DDR_PHY_DSGCR_DTOODT_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_DTOODT_SHIFT 12 +#define DDR_PHY_DSGCR_DTOODT_MASK 0x00001000U -/*PHY Update Acknowledge Delay*/ +/* +* PHY Update Acknowledge Delay +*/ #undef DDR_PHY_DSGCR_PUAD_DEFVAL #undef DDR_PHY_DSGCR_PUAD_SHIFT #undef DDR_PHY_DSGCR_PUAD_MASK -#define DDR_PHY_DSGCR_PUAD_DEFVAL 0x02A04101 -#define DDR_PHY_DSGCR_PUAD_SHIFT 6 -#define DDR_PHY_DSGCR_PUAD_MASK 0x00000FC0U +#define DDR_PHY_DSGCR_PUAD_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_PUAD_SHIFT 6 +#define DDR_PHY_DSGCR_PUAD_MASK 0x00000FC0U -/*Controller Update Acknowledge Enable*/ +/* +* Controller Update Acknowledge Enable +*/ #undef DDR_PHY_DSGCR_CUAEN_DEFVAL #undef DDR_PHY_DSGCR_CUAEN_SHIFT #undef DDR_PHY_DSGCR_CUAEN_MASK -#define DDR_PHY_DSGCR_CUAEN_DEFVAL 0x02A04101 -#define DDR_PHY_DSGCR_CUAEN_SHIFT 5 -#define DDR_PHY_DSGCR_CUAEN_MASK 0x00000020U +#define DDR_PHY_DSGCR_CUAEN_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_CUAEN_SHIFT 5 +#define DDR_PHY_DSGCR_CUAEN_MASK 0x00000020U -/*Reserved. Return zeroes on reads*/ +/* +* Reserved. Return zeroes on reads +*/ #undef DDR_PHY_DSGCR_RESERVED_4_3_DEFVAL #undef DDR_PHY_DSGCR_RESERVED_4_3_SHIFT #undef DDR_PHY_DSGCR_RESERVED_4_3_MASK -#define DDR_PHY_DSGCR_RESERVED_4_3_DEFVAL 0x02A04101 -#define DDR_PHY_DSGCR_RESERVED_4_3_SHIFT 3 -#define DDR_PHY_DSGCR_RESERVED_4_3_MASK 0x00000018U +#define DDR_PHY_DSGCR_RESERVED_4_3_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_RESERVED_4_3_SHIFT 3 +#define DDR_PHY_DSGCR_RESERVED_4_3_MASK 0x00000018U -/*Controller Impedance Update Enable*/ +/* +* Controller Impedance Update Enable +*/ #undef DDR_PHY_DSGCR_CTLZUEN_DEFVAL #undef DDR_PHY_DSGCR_CTLZUEN_SHIFT #undef DDR_PHY_DSGCR_CTLZUEN_MASK -#define DDR_PHY_DSGCR_CTLZUEN_DEFVAL 0x02A04101 -#define DDR_PHY_DSGCR_CTLZUEN_SHIFT 2 -#define DDR_PHY_DSGCR_CTLZUEN_MASK 0x00000004U +#define DDR_PHY_DSGCR_CTLZUEN_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_CTLZUEN_SHIFT 2 +#define DDR_PHY_DSGCR_CTLZUEN_MASK 0x00000004U -/*Reserved. Return zeroes on reads*/ +/* +* Reserved. Return zeroes on reads +*/ #undef DDR_PHY_DSGCR_RESERVED_1_DEFVAL #undef DDR_PHY_DSGCR_RESERVED_1_SHIFT #undef DDR_PHY_DSGCR_RESERVED_1_MASK -#define DDR_PHY_DSGCR_RESERVED_1_DEFVAL 0x02A04101 -#define DDR_PHY_DSGCR_RESERVED_1_SHIFT 1 -#define DDR_PHY_DSGCR_RESERVED_1_MASK 0x00000002U +#define DDR_PHY_DSGCR_RESERVED_1_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_RESERVED_1_SHIFT 1 +#define DDR_PHY_DSGCR_RESERVED_1_MASK 0x00000002U -/*PHY Update Request Enable*/ +/* +* PHY Update Request Enable +*/ #undef DDR_PHY_DSGCR_PUREN_DEFVAL #undef DDR_PHY_DSGCR_PUREN_SHIFT #undef DDR_PHY_DSGCR_PUREN_MASK -#define DDR_PHY_DSGCR_PUREN_DEFVAL 0x02A04101 -#define DDR_PHY_DSGCR_PUREN_SHIFT 0 -#define DDR_PHY_DSGCR_PUREN_MASK 0x00000001U +#define DDR_PHY_DSGCR_PUREN_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_PUREN_SHIFT 0 +#define DDR_PHY_DSGCR_PUREN_MASK 0x00000001U -/*DDR4 Gear Down Timing.*/ +/* +* General Purpose Register 0 +*/ +#undef DDR_PHY_GPR0_GPR0_DEFVAL +#undef DDR_PHY_GPR0_GPR0_SHIFT +#undef DDR_PHY_GPR0_GPR0_MASK +#define DDR_PHY_GPR0_GPR0_DEFVAL +#define DDR_PHY_GPR0_GPR0_SHIFT 0 +#define DDR_PHY_GPR0_GPR0_MASK 0xFFFFFFFFU + +/* +* DDR4 Gear Down Timing. +*/ #undef DDR_PHY_DCR_GEARDN_DEFVAL #undef DDR_PHY_DCR_GEARDN_SHIFT #undef DDR_PHY_DCR_GEARDN_MASK -#define DDR_PHY_DCR_GEARDN_DEFVAL 0x0000040D -#define DDR_PHY_DCR_GEARDN_SHIFT 31 -#define DDR_PHY_DCR_GEARDN_MASK 0x80000000U +#define DDR_PHY_DCR_GEARDN_DEFVAL 0x0000040D +#define DDR_PHY_DCR_GEARDN_SHIFT 31 +#define DDR_PHY_DCR_GEARDN_MASK 0x80000000U -/*Un-used Bank Group*/ +/* +* Un-used Bank Group +*/ #undef DDR_PHY_DCR_UBG_DEFVAL #undef DDR_PHY_DCR_UBG_SHIFT #undef DDR_PHY_DCR_UBG_MASK -#define DDR_PHY_DCR_UBG_DEFVAL 0x0000040D -#define DDR_PHY_DCR_UBG_SHIFT 30 -#define DDR_PHY_DCR_UBG_MASK 0x40000000U +#define DDR_PHY_DCR_UBG_DEFVAL 0x0000040D +#define DDR_PHY_DCR_UBG_SHIFT 30 +#define DDR_PHY_DCR_UBG_MASK 0x40000000U -/*Un-buffered DIMM Address Mirroring*/ +/* +* Un-buffered DIMM Address Mirroring +*/ #undef DDR_PHY_DCR_UDIMM_DEFVAL #undef DDR_PHY_DCR_UDIMM_SHIFT #undef DDR_PHY_DCR_UDIMM_MASK -#define DDR_PHY_DCR_UDIMM_DEFVAL 0x0000040D -#define DDR_PHY_DCR_UDIMM_SHIFT 29 -#define DDR_PHY_DCR_UDIMM_MASK 0x20000000U +#define DDR_PHY_DCR_UDIMM_DEFVAL 0x0000040D +#define DDR_PHY_DCR_UDIMM_SHIFT 29 +#define DDR_PHY_DCR_UDIMM_MASK 0x20000000U -/*DDR 2T Timing*/ +/* +* DDR 2T Timing +*/ #undef DDR_PHY_DCR_DDR2T_DEFVAL #undef DDR_PHY_DCR_DDR2T_SHIFT #undef DDR_PHY_DCR_DDR2T_MASK -#define DDR_PHY_DCR_DDR2T_DEFVAL 0x0000040D -#define DDR_PHY_DCR_DDR2T_SHIFT 28 -#define DDR_PHY_DCR_DDR2T_MASK 0x10000000U +#define DDR_PHY_DCR_DDR2T_DEFVAL 0x0000040D +#define DDR_PHY_DCR_DDR2T_SHIFT 28 +#define DDR_PHY_DCR_DDR2T_MASK 0x10000000U -/*No Simultaneous Rank Access*/ +/* +* No Simultaneous Rank Access +*/ #undef DDR_PHY_DCR_NOSRA_DEFVAL #undef DDR_PHY_DCR_NOSRA_SHIFT #undef DDR_PHY_DCR_NOSRA_MASK -#define DDR_PHY_DCR_NOSRA_DEFVAL 0x0000040D -#define DDR_PHY_DCR_NOSRA_SHIFT 27 -#define DDR_PHY_DCR_NOSRA_MASK 0x08000000U +#define DDR_PHY_DCR_NOSRA_DEFVAL 0x0000040D +#define DDR_PHY_DCR_NOSRA_SHIFT 27 +#define DDR_PHY_DCR_NOSRA_MASK 0x08000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DCR_RESERVED_26_18_DEFVAL #undef DDR_PHY_DCR_RESERVED_26_18_SHIFT #undef DDR_PHY_DCR_RESERVED_26_18_MASK -#define DDR_PHY_DCR_RESERVED_26_18_DEFVAL 0x0000040D -#define DDR_PHY_DCR_RESERVED_26_18_SHIFT 18 -#define DDR_PHY_DCR_RESERVED_26_18_MASK 0x07FC0000U +#define DDR_PHY_DCR_RESERVED_26_18_DEFVAL 0x0000040D +#define DDR_PHY_DCR_RESERVED_26_18_SHIFT 18 +#define DDR_PHY_DCR_RESERVED_26_18_MASK 0x07FC0000U -/*Byte Mask*/ +/* +* Byte Mask +*/ #undef DDR_PHY_DCR_BYTEMASK_DEFVAL #undef DDR_PHY_DCR_BYTEMASK_SHIFT #undef DDR_PHY_DCR_BYTEMASK_MASK -#define DDR_PHY_DCR_BYTEMASK_DEFVAL 0x0000040D -#define DDR_PHY_DCR_BYTEMASK_SHIFT 10 -#define DDR_PHY_DCR_BYTEMASK_MASK 0x0003FC00U +#define DDR_PHY_DCR_BYTEMASK_DEFVAL 0x0000040D +#define DDR_PHY_DCR_BYTEMASK_SHIFT 10 +#define DDR_PHY_DCR_BYTEMASK_MASK 0x0003FC00U -/*DDR Type*/ +/* +* DDR Type +*/ #undef DDR_PHY_DCR_DDRTYPE_DEFVAL #undef DDR_PHY_DCR_DDRTYPE_SHIFT #undef DDR_PHY_DCR_DDRTYPE_MASK -#define DDR_PHY_DCR_DDRTYPE_DEFVAL 0x0000040D -#define DDR_PHY_DCR_DDRTYPE_SHIFT 8 -#define DDR_PHY_DCR_DDRTYPE_MASK 0x00000300U +#define DDR_PHY_DCR_DDRTYPE_DEFVAL 0x0000040D +#define DDR_PHY_DCR_DDRTYPE_SHIFT 8 +#define DDR_PHY_DCR_DDRTYPE_MASK 0x00000300U -/*Multi-Purpose Register (MPR) DQ (DDR3 Only)*/ +/* +* Multi-Purpose Register (MPR) DQ (DDR3 Only) +*/ #undef DDR_PHY_DCR_MPRDQ_DEFVAL #undef DDR_PHY_DCR_MPRDQ_SHIFT #undef DDR_PHY_DCR_MPRDQ_MASK -#define DDR_PHY_DCR_MPRDQ_DEFVAL 0x0000040D -#define DDR_PHY_DCR_MPRDQ_SHIFT 7 -#define DDR_PHY_DCR_MPRDQ_MASK 0x00000080U +#define DDR_PHY_DCR_MPRDQ_DEFVAL 0x0000040D +#define DDR_PHY_DCR_MPRDQ_SHIFT 7 +#define DDR_PHY_DCR_MPRDQ_MASK 0x00000080U -/*Primary DQ (DDR3 Only)*/ +/* +* Primary DQ (DDR3 Only) +*/ #undef DDR_PHY_DCR_PDQ_DEFVAL #undef DDR_PHY_DCR_PDQ_SHIFT #undef DDR_PHY_DCR_PDQ_MASK -#define DDR_PHY_DCR_PDQ_DEFVAL 0x0000040D -#define DDR_PHY_DCR_PDQ_SHIFT 4 -#define DDR_PHY_DCR_PDQ_MASK 0x00000070U +#define DDR_PHY_DCR_PDQ_DEFVAL 0x0000040D +#define DDR_PHY_DCR_PDQ_SHIFT 4 +#define DDR_PHY_DCR_PDQ_MASK 0x00000070U -/*DDR 8-Bank*/ +/* +* DDR 8-Bank +*/ #undef DDR_PHY_DCR_DDR8BNK_DEFVAL #undef DDR_PHY_DCR_DDR8BNK_SHIFT #undef DDR_PHY_DCR_DDR8BNK_MASK -#define DDR_PHY_DCR_DDR8BNK_DEFVAL 0x0000040D -#define DDR_PHY_DCR_DDR8BNK_SHIFT 3 -#define DDR_PHY_DCR_DDR8BNK_MASK 0x00000008U +#define DDR_PHY_DCR_DDR8BNK_DEFVAL 0x0000040D +#define DDR_PHY_DCR_DDR8BNK_SHIFT 3 +#define DDR_PHY_DCR_DDR8BNK_MASK 0x00000008U -/*DDR Mode*/ +/* +* DDR Mode +*/ #undef DDR_PHY_DCR_DDRMD_DEFVAL #undef DDR_PHY_DCR_DDRMD_SHIFT #undef DDR_PHY_DCR_DDRMD_MASK -#define DDR_PHY_DCR_DDRMD_DEFVAL 0x0000040D -#define DDR_PHY_DCR_DDRMD_SHIFT 0 -#define DDR_PHY_DCR_DDRMD_MASK 0x00000007U +#define DDR_PHY_DCR_DDRMD_DEFVAL 0x0000040D +#define DDR_PHY_DCR_DDRMD_SHIFT 0 +#define DDR_PHY_DCR_DDRMD_MASK 0x00000007U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR0_RESERVED_31_29_DEFVAL #undef DDR_PHY_DTPR0_RESERVED_31_29_SHIFT #undef DDR_PHY_DTPR0_RESERVED_31_29_MASK -#define DDR_PHY_DTPR0_RESERVED_31_29_DEFVAL 0x105A2D08 -#define DDR_PHY_DTPR0_RESERVED_31_29_SHIFT 29 -#define DDR_PHY_DTPR0_RESERVED_31_29_MASK 0xE0000000U +#define DDR_PHY_DTPR0_RESERVED_31_29_DEFVAL 0x105A2D08 +#define DDR_PHY_DTPR0_RESERVED_31_29_SHIFT 29 +#define DDR_PHY_DTPR0_RESERVED_31_29_MASK 0xE0000000U -/*Activate to activate command delay (different banks)*/ +/* +* Activate to activate command delay (different banks) +*/ #undef DDR_PHY_DTPR0_TRRD_DEFVAL #undef DDR_PHY_DTPR0_TRRD_SHIFT #undef DDR_PHY_DTPR0_TRRD_MASK -#define DDR_PHY_DTPR0_TRRD_DEFVAL 0x105A2D08 -#define DDR_PHY_DTPR0_TRRD_SHIFT 24 -#define DDR_PHY_DTPR0_TRRD_MASK 0x1F000000U +#define DDR_PHY_DTPR0_TRRD_DEFVAL 0x105A2D08 +#define DDR_PHY_DTPR0_TRRD_SHIFT 24 +#define DDR_PHY_DTPR0_TRRD_MASK 0x1F000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR0_RESERVED_23_DEFVAL #undef DDR_PHY_DTPR0_RESERVED_23_SHIFT #undef DDR_PHY_DTPR0_RESERVED_23_MASK -#define DDR_PHY_DTPR0_RESERVED_23_DEFVAL 0x105A2D08 -#define DDR_PHY_DTPR0_RESERVED_23_SHIFT 23 -#define DDR_PHY_DTPR0_RESERVED_23_MASK 0x00800000U +#define DDR_PHY_DTPR0_RESERVED_23_DEFVAL 0x105A2D08 +#define DDR_PHY_DTPR0_RESERVED_23_SHIFT 23 +#define DDR_PHY_DTPR0_RESERVED_23_MASK 0x00800000U -/*Activate to precharge command delay*/ +/* +* Activate to precharge command delay +*/ #undef DDR_PHY_DTPR0_TRAS_DEFVAL #undef DDR_PHY_DTPR0_TRAS_SHIFT #undef DDR_PHY_DTPR0_TRAS_MASK -#define DDR_PHY_DTPR0_TRAS_DEFVAL 0x105A2D08 -#define DDR_PHY_DTPR0_TRAS_SHIFT 16 -#define DDR_PHY_DTPR0_TRAS_MASK 0x007F0000U +#define DDR_PHY_DTPR0_TRAS_DEFVAL 0x105A2D08 +#define DDR_PHY_DTPR0_TRAS_SHIFT 16 +#define DDR_PHY_DTPR0_TRAS_MASK 0x007F0000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR0_RESERVED_15_DEFVAL #undef DDR_PHY_DTPR0_RESERVED_15_SHIFT #undef DDR_PHY_DTPR0_RESERVED_15_MASK -#define DDR_PHY_DTPR0_RESERVED_15_DEFVAL 0x105A2D08 -#define DDR_PHY_DTPR0_RESERVED_15_SHIFT 15 -#define DDR_PHY_DTPR0_RESERVED_15_MASK 0x00008000U +#define DDR_PHY_DTPR0_RESERVED_15_DEFVAL 0x105A2D08 +#define DDR_PHY_DTPR0_RESERVED_15_SHIFT 15 +#define DDR_PHY_DTPR0_RESERVED_15_MASK 0x00008000U -/*Precharge command period*/ +/* +* Precharge command period +*/ #undef DDR_PHY_DTPR0_TRP_DEFVAL #undef DDR_PHY_DTPR0_TRP_SHIFT #undef DDR_PHY_DTPR0_TRP_MASK -#define DDR_PHY_DTPR0_TRP_DEFVAL 0x105A2D08 -#define DDR_PHY_DTPR0_TRP_SHIFT 8 -#define DDR_PHY_DTPR0_TRP_MASK 0x00007F00U +#define DDR_PHY_DTPR0_TRP_DEFVAL 0x105A2D08 +#define DDR_PHY_DTPR0_TRP_SHIFT 8 +#define DDR_PHY_DTPR0_TRP_MASK 0x00007F00U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR0_RESERVED_7_5_DEFVAL #undef DDR_PHY_DTPR0_RESERVED_7_5_SHIFT #undef DDR_PHY_DTPR0_RESERVED_7_5_MASK -#define DDR_PHY_DTPR0_RESERVED_7_5_DEFVAL 0x105A2D08 -#define DDR_PHY_DTPR0_RESERVED_7_5_SHIFT 5 -#define DDR_PHY_DTPR0_RESERVED_7_5_MASK 0x000000E0U +#define DDR_PHY_DTPR0_RESERVED_7_5_DEFVAL 0x105A2D08 +#define DDR_PHY_DTPR0_RESERVED_7_5_SHIFT 5 +#define DDR_PHY_DTPR0_RESERVED_7_5_MASK 0x000000E0U -/*Internal read to precharge command delay*/ +/* +* Internal read to precharge command delay +*/ #undef DDR_PHY_DTPR0_TRTP_DEFVAL #undef DDR_PHY_DTPR0_TRTP_SHIFT #undef DDR_PHY_DTPR0_TRTP_MASK -#define DDR_PHY_DTPR0_TRTP_DEFVAL 0x105A2D08 -#define DDR_PHY_DTPR0_TRTP_SHIFT 0 -#define DDR_PHY_DTPR0_TRTP_MASK 0x0000001FU +#define DDR_PHY_DTPR0_TRTP_DEFVAL 0x105A2D08 +#define DDR_PHY_DTPR0_TRTP_SHIFT 0 +#define DDR_PHY_DTPR0_TRTP_MASK 0x0000001FU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR1_RESERVED_31_DEFVAL #undef DDR_PHY_DTPR1_RESERVED_31_SHIFT #undef DDR_PHY_DTPR1_RESERVED_31_MASK -#define DDR_PHY_DTPR1_RESERVED_31_DEFVAL 0x5656041E -#define DDR_PHY_DTPR1_RESERVED_31_SHIFT 31 -#define DDR_PHY_DTPR1_RESERVED_31_MASK 0x80000000U +#define DDR_PHY_DTPR1_RESERVED_31_DEFVAL 0x5656041E +#define DDR_PHY_DTPR1_RESERVED_31_SHIFT 31 +#define DDR_PHY_DTPR1_RESERVED_31_MASK 0x80000000U -/*Minimum delay from when write leveling mode is programmed to the first DQS/DQS# rising edge.*/ +/* +* Minimum delay from when write leveling mode is programmed to the first D + * QS/DQS# rising edge. +*/ #undef DDR_PHY_DTPR1_TWLMRD_DEFVAL #undef DDR_PHY_DTPR1_TWLMRD_SHIFT #undef DDR_PHY_DTPR1_TWLMRD_MASK -#define DDR_PHY_DTPR1_TWLMRD_DEFVAL 0x5656041E -#define DDR_PHY_DTPR1_TWLMRD_SHIFT 24 -#define DDR_PHY_DTPR1_TWLMRD_MASK 0x7F000000U +#define DDR_PHY_DTPR1_TWLMRD_DEFVAL 0x5656041E +#define DDR_PHY_DTPR1_TWLMRD_SHIFT 24 +#define DDR_PHY_DTPR1_TWLMRD_MASK 0x7F000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR1_RESERVED_23_DEFVAL #undef DDR_PHY_DTPR1_RESERVED_23_SHIFT #undef DDR_PHY_DTPR1_RESERVED_23_MASK -#define DDR_PHY_DTPR1_RESERVED_23_DEFVAL 0x5656041E -#define DDR_PHY_DTPR1_RESERVED_23_SHIFT 23 -#define DDR_PHY_DTPR1_RESERVED_23_MASK 0x00800000U +#define DDR_PHY_DTPR1_RESERVED_23_DEFVAL 0x5656041E +#define DDR_PHY_DTPR1_RESERVED_23_SHIFT 23 +#define DDR_PHY_DTPR1_RESERVED_23_MASK 0x00800000U -/*4-bank activate period*/ +/* +* 4-bank activate period +*/ #undef DDR_PHY_DTPR1_TFAW_DEFVAL #undef DDR_PHY_DTPR1_TFAW_SHIFT #undef DDR_PHY_DTPR1_TFAW_MASK -#define DDR_PHY_DTPR1_TFAW_DEFVAL 0x5656041E -#define DDR_PHY_DTPR1_TFAW_SHIFT 16 -#define DDR_PHY_DTPR1_TFAW_MASK 0x007F0000U +#define DDR_PHY_DTPR1_TFAW_DEFVAL 0x5656041E +#define DDR_PHY_DTPR1_TFAW_SHIFT 16 +#define DDR_PHY_DTPR1_TFAW_MASK 0x007F0000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR1_RESERVED_15_11_DEFVAL #undef DDR_PHY_DTPR1_RESERVED_15_11_SHIFT #undef DDR_PHY_DTPR1_RESERVED_15_11_MASK -#define DDR_PHY_DTPR1_RESERVED_15_11_DEFVAL 0x5656041E -#define DDR_PHY_DTPR1_RESERVED_15_11_SHIFT 11 -#define DDR_PHY_DTPR1_RESERVED_15_11_MASK 0x0000F800U +#define DDR_PHY_DTPR1_RESERVED_15_11_DEFVAL 0x5656041E +#define DDR_PHY_DTPR1_RESERVED_15_11_SHIFT 11 +#define DDR_PHY_DTPR1_RESERVED_15_11_MASK 0x0000F800U -/*Load mode update delay (DDR4 and DDR3 only)*/ +/* +* Load mode update delay (DDR4 and DDR3 only) +*/ #undef DDR_PHY_DTPR1_TMOD_DEFVAL #undef DDR_PHY_DTPR1_TMOD_SHIFT #undef DDR_PHY_DTPR1_TMOD_MASK -#define DDR_PHY_DTPR1_TMOD_DEFVAL 0x5656041E -#define DDR_PHY_DTPR1_TMOD_SHIFT 8 -#define DDR_PHY_DTPR1_TMOD_MASK 0x00000700U +#define DDR_PHY_DTPR1_TMOD_DEFVAL 0x5656041E +#define DDR_PHY_DTPR1_TMOD_SHIFT 8 +#define DDR_PHY_DTPR1_TMOD_MASK 0x00000700U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR1_RESERVED_7_5_DEFVAL #undef DDR_PHY_DTPR1_RESERVED_7_5_SHIFT #undef DDR_PHY_DTPR1_RESERVED_7_5_MASK -#define DDR_PHY_DTPR1_RESERVED_7_5_DEFVAL 0x5656041E -#define DDR_PHY_DTPR1_RESERVED_7_5_SHIFT 5 -#define DDR_PHY_DTPR1_RESERVED_7_5_MASK 0x000000E0U +#define DDR_PHY_DTPR1_RESERVED_7_5_DEFVAL 0x5656041E +#define DDR_PHY_DTPR1_RESERVED_7_5_SHIFT 5 +#define DDR_PHY_DTPR1_RESERVED_7_5_MASK 0x000000E0U -/*Load mode cycle time*/ +/* +* Load mode cycle time +*/ #undef DDR_PHY_DTPR1_TMRD_DEFVAL #undef DDR_PHY_DTPR1_TMRD_SHIFT #undef DDR_PHY_DTPR1_TMRD_MASK -#define DDR_PHY_DTPR1_TMRD_DEFVAL 0x5656041E -#define DDR_PHY_DTPR1_TMRD_SHIFT 0 -#define DDR_PHY_DTPR1_TMRD_MASK 0x0000001FU +#define DDR_PHY_DTPR1_TMRD_DEFVAL 0x5656041E +#define DDR_PHY_DTPR1_TMRD_SHIFT 0 +#define DDR_PHY_DTPR1_TMRD_MASK 0x0000001FU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR2_RESERVED_31_29_DEFVAL #undef DDR_PHY_DTPR2_RESERVED_31_29_SHIFT #undef DDR_PHY_DTPR2_RESERVED_31_29_MASK -#define DDR_PHY_DTPR2_RESERVED_31_29_DEFVAL 0x000B01D0 -#define DDR_PHY_DTPR2_RESERVED_31_29_SHIFT 29 -#define DDR_PHY_DTPR2_RESERVED_31_29_MASK 0xE0000000U +#define DDR_PHY_DTPR2_RESERVED_31_29_DEFVAL 0x000B01D0 +#define DDR_PHY_DTPR2_RESERVED_31_29_SHIFT 29 +#define DDR_PHY_DTPR2_RESERVED_31_29_MASK 0xE0000000U -/*Read to Write command delay. Valid values are*/ +/* +* Read to Write command delay. Valid values are +*/ #undef DDR_PHY_DTPR2_TRTW_DEFVAL #undef DDR_PHY_DTPR2_TRTW_SHIFT #undef DDR_PHY_DTPR2_TRTW_MASK -#define DDR_PHY_DTPR2_TRTW_DEFVAL 0x000B01D0 -#define DDR_PHY_DTPR2_TRTW_SHIFT 28 -#define DDR_PHY_DTPR2_TRTW_MASK 0x10000000U +#define DDR_PHY_DTPR2_TRTW_DEFVAL 0x000B01D0 +#define DDR_PHY_DTPR2_TRTW_SHIFT 28 +#define DDR_PHY_DTPR2_TRTW_MASK 0x10000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR2_RESERVED_27_25_DEFVAL #undef DDR_PHY_DTPR2_RESERVED_27_25_SHIFT #undef DDR_PHY_DTPR2_RESERVED_27_25_MASK -#define DDR_PHY_DTPR2_RESERVED_27_25_DEFVAL 0x000B01D0 -#define DDR_PHY_DTPR2_RESERVED_27_25_SHIFT 25 -#define DDR_PHY_DTPR2_RESERVED_27_25_MASK 0x0E000000U +#define DDR_PHY_DTPR2_RESERVED_27_25_DEFVAL 0x000B01D0 +#define DDR_PHY_DTPR2_RESERVED_27_25_SHIFT 25 +#define DDR_PHY_DTPR2_RESERVED_27_25_MASK 0x0E000000U -/*Read to ODT delay (DDR3 only)*/ +/* +* Read to ODT delay (DDR3 only) +*/ #undef DDR_PHY_DTPR2_TRTODT_DEFVAL #undef DDR_PHY_DTPR2_TRTODT_SHIFT #undef DDR_PHY_DTPR2_TRTODT_MASK -#define DDR_PHY_DTPR2_TRTODT_DEFVAL 0x000B01D0 -#define DDR_PHY_DTPR2_TRTODT_SHIFT 24 -#define DDR_PHY_DTPR2_TRTODT_MASK 0x01000000U +#define DDR_PHY_DTPR2_TRTODT_DEFVAL 0x000B01D0 +#define DDR_PHY_DTPR2_TRTODT_SHIFT 24 +#define DDR_PHY_DTPR2_TRTODT_MASK 0x01000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR2_RESERVED_23_20_DEFVAL #undef DDR_PHY_DTPR2_RESERVED_23_20_SHIFT #undef DDR_PHY_DTPR2_RESERVED_23_20_MASK -#define DDR_PHY_DTPR2_RESERVED_23_20_DEFVAL 0x000B01D0 -#define DDR_PHY_DTPR2_RESERVED_23_20_SHIFT 20 -#define DDR_PHY_DTPR2_RESERVED_23_20_MASK 0x00F00000U +#define DDR_PHY_DTPR2_RESERVED_23_20_DEFVAL 0x000B01D0 +#define DDR_PHY_DTPR2_RESERVED_23_20_SHIFT 20 +#define DDR_PHY_DTPR2_RESERVED_23_20_MASK 0x00F00000U -/*CKE minimum pulse width*/ +/* +* CKE minimum pulse width +*/ #undef DDR_PHY_DTPR2_TCKE_DEFVAL #undef DDR_PHY_DTPR2_TCKE_SHIFT #undef DDR_PHY_DTPR2_TCKE_MASK -#define DDR_PHY_DTPR2_TCKE_DEFVAL 0x000B01D0 -#define DDR_PHY_DTPR2_TCKE_SHIFT 16 -#define DDR_PHY_DTPR2_TCKE_MASK 0x000F0000U +#define DDR_PHY_DTPR2_TCKE_DEFVAL 0x000B01D0 +#define DDR_PHY_DTPR2_TCKE_SHIFT 16 +#define DDR_PHY_DTPR2_TCKE_MASK 0x000F0000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR2_RESERVED_15_10_DEFVAL #undef DDR_PHY_DTPR2_RESERVED_15_10_SHIFT #undef DDR_PHY_DTPR2_RESERVED_15_10_MASK -#define DDR_PHY_DTPR2_RESERVED_15_10_DEFVAL 0x000B01D0 -#define DDR_PHY_DTPR2_RESERVED_15_10_SHIFT 10 -#define DDR_PHY_DTPR2_RESERVED_15_10_MASK 0x0000FC00U +#define DDR_PHY_DTPR2_RESERVED_15_10_DEFVAL 0x000B01D0 +#define DDR_PHY_DTPR2_RESERVED_15_10_SHIFT 10 +#define DDR_PHY_DTPR2_RESERVED_15_10_MASK 0x0000FC00U -/*Self refresh exit delay*/ +/* +* Self refresh exit delay +*/ #undef DDR_PHY_DTPR2_TXS_DEFVAL #undef DDR_PHY_DTPR2_TXS_SHIFT #undef DDR_PHY_DTPR2_TXS_MASK -#define DDR_PHY_DTPR2_TXS_DEFVAL 0x000B01D0 -#define DDR_PHY_DTPR2_TXS_SHIFT 0 -#define DDR_PHY_DTPR2_TXS_MASK 0x000003FFU +#define DDR_PHY_DTPR2_TXS_DEFVAL 0x000B01D0 +#define DDR_PHY_DTPR2_TXS_SHIFT 0 +#define DDR_PHY_DTPR2_TXS_MASK 0x000003FFU -/*ODT turn-off delay extension*/ +/* +* ODT turn-off delay extension +*/ #undef DDR_PHY_DTPR3_TOFDX_DEFVAL #undef DDR_PHY_DTPR3_TOFDX_SHIFT #undef DDR_PHY_DTPR3_TOFDX_MASK -#define DDR_PHY_DTPR3_TOFDX_DEFVAL 0x02000804 -#define DDR_PHY_DTPR3_TOFDX_SHIFT 29 -#define DDR_PHY_DTPR3_TOFDX_MASK 0xE0000000U +#define DDR_PHY_DTPR3_TOFDX_DEFVAL 0x02000804 +#define DDR_PHY_DTPR3_TOFDX_SHIFT 29 +#define DDR_PHY_DTPR3_TOFDX_MASK 0xE0000000U -/*Read to read and write to write command delay*/ +/* +* Read to read and write to write command delay +*/ #undef DDR_PHY_DTPR3_TCCD_DEFVAL #undef DDR_PHY_DTPR3_TCCD_SHIFT #undef DDR_PHY_DTPR3_TCCD_MASK -#define DDR_PHY_DTPR3_TCCD_DEFVAL 0x02000804 -#define DDR_PHY_DTPR3_TCCD_SHIFT 26 -#define DDR_PHY_DTPR3_TCCD_MASK 0x1C000000U +#define DDR_PHY_DTPR3_TCCD_DEFVAL 0x02000804 +#define DDR_PHY_DTPR3_TCCD_SHIFT 26 +#define DDR_PHY_DTPR3_TCCD_MASK 0x1C000000U -/*DLL locking time*/ +/* +* DLL locking time +*/ #undef DDR_PHY_DTPR3_TDLLK_DEFVAL #undef DDR_PHY_DTPR3_TDLLK_SHIFT #undef DDR_PHY_DTPR3_TDLLK_MASK -#define DDR_PHY_DTPR3_TDLLK_DEFVAL 0x02000804 -#define DDR_PHY_DTPR3_TDLLK_SHIFT 16 -#define DDR_PHY_DTPR3_TDLLK_MASK 0x03FF0000U +#define DDR_PHY_DTPR3_TDLLK_DEFVAL 0x02000804 +#define DDR_PHY_DTPR3_TDLLK_SHIFT 16 +#define DDR_PHY_DTPR3_TDLLK_MASK 0x03FF0000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR3_RESERVED_15_12_DEFVAL #undef DDR_PHY_DTPR3_RESERVED_15_12_SHIFT #undef DDR_PHY_DTPR3_RESERVED_15_12_MASK -#define DDR_PHY_DTPR3_RESERVED_15_12_DEFVAL 0x02000804 -#define DDR_PHY_DTPR3_RESERVED_15_12_SHIFT 12 -#define DDR_PHY_DTPR3_RESERVED_15_12_MASK 0x0000F000U +#define DDR_PHY_DTPR3_RESERVED_15_12_DEFVAL 0x02000804 +#define DDR_PHY_DTPR3_RESERVED_15_12_SHIFT 12 +#define DDR_PHY_DTPR3_RESERVED_15_12_MASK 0x0000F000U -/*Maximum DQS output access time from CK/CK# (LPDDR2/3 only)*/ +/* +* Maximum DQS output access time from CK/CK# (LPDDR2/3 only) +*/ #undef DDR_PHY_DTPR3_TDQSCKMAX_DEFVAL #undef DDR_PHY_DTPR3_TDQSCKMAX_SHIFT #undef DDR_PHY_DTPR3_TDQSCKMAX_MASK -#define DDR_PHY_DTPR3_TDQSCKMAX_DEFVAL 0x02000804 -#define DDR_PHY_DTPR3_TDQSCKMAX_SHIFT 8 -#define DDR_PHY_DTPR3_TDQSCKMAX_MASK 0x00000F00U +#define DDR_PHY_DTPR3_TDQSCKMAX_DEFVAL 0x02000804 +#define DDR_PHY_DTPR3_TDQSCKMAX_SHIFT 8 +#define DDR_PHY_DTPR3_TDQSCKMAX_MASK 0x00000F00U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR3_RESERVED_7_3_DEFVAL #undef DDR_PHY_DTPR3_RESERVED_7_3_SHIFT #undef DDR_PHY_DTPR3_RESERVED_7_3_MASK -#define DDR_PHY_DTPR3_RESERVED_7_3_DEFVAL 0x02000804 -#define DDR_PHY_DTPR3_RESERVED_7_3_SHIFT 3 -#define DDR_PHY_DTPR3_RESERVED_7_3_MASK 0x000000F8U +#define DDR_PHY_DTPR3_RESERVED_7_3_DEFVAL 0x02000804 +#define DDR_PHY_DTPR3_RESERVED_7_3_SHIFT 3 +#define DDR_PHY_DTPR3_RESERVED_7_3_MASK 0x000000F8U -/*DQS output access time from CK/CK# (LPDDR2/3 only)*/ +/* +* DQS output access time from CK/CK# (LPDDR2/3 only) +*/ #undef DDR_PHY_DTPR3_TDQSCK_DEFVAL #undef DDR_PHY_DTPR3_TDQSCK_SHIFT #undef DDR_PHY_DTPR3_TDQSCK_MASK -#define DDR_PHY_DTPR3_TDQSCK_DEFVAL 0x02000804 -#define DDR_PHY_DTPR3_TDQSCK_SHIFT 0 -#define DDR_PHY_DTPR3_TDQSCK_MASK 0x00000007U +#define DDR_PHY_DTPR3_TDQSCK_DEFVAL 0x02000804 +#define DDR_PHY_DTPR3_TDQSCK_SHIFT 0 +#define DDR_PHY_DTPR3_TDQSCK_MASK 0x00000007U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR4_RESERVED_31_30_DEFVAL #undef DDR_PHY_DTPR4_RESERVED_31_30_SHIFT #undef DDR_PHY_DTPR4_RESERVED_31_30_MASK -#define DDR_PHY_DTPR4_RESERVED_31_30_DEFVAL 0x01C02B10 -#define DDR_PHY_DTPR4_RESERVED_31_30_SHIFT 30 -#define DDR_PHY_DTPR4_RESERVED_31_30_MASK 0xC0000000U +#define DDR_PHY_DTPR4_RESERVED_31_30_DEFVAL 0x01C02B10 +#define DDR_PHY_DTPR4_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DTPR4_RESERVED_31_30_MASK 0xC0000000U -/*ODT turn-on/turn-off delays (DDR2 only)*/ +/* +* ODT turn-on/turn-off delays (DDR2 only) +*/ #undef DDR_PHY_DTPR4_TAOND_TAOFD_DEFVAL #undef DDR_PHY_DTPR4_TAOND_TAOFD_SHIFT #undef DDR_PHY_DTPR4_TAOND_TAOFD_MASK -#define DDR_PHY_DTPR4_TAOND_TAOFD_DEFVAL 0x01C02B10 -#define DDR_PHY_DTPR4_TAOND_TAOFD_SHIFT 28 -#define DDR_PHY_DTPR4_TAOND_TAOFD_MASK 0x30000000U +#define DDR_PHY_DTPR4_TAOND_TAOFD_DEFVAL 0x01C02B10 +#define DDR_PHY_DTPR4_TAOND_TAOFD_SHIFT 28 +#define DDR_PHY_DTPR4_TAOND_TAOFD_MASK 0x30000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR4_RESERVED_27_26_DEFVAL #undef DDR_PHY_DTPR4_RESERVED_27_26_SHIFT #undef DDR_PHY_DTPR4_RESERVED_27_26_MASK -#define DDR_PHY_DTPR4_RESERVED_27_26_DEFVAL 0x01C02B10 -#define DDR_PHY_DTPR4_RESERVED_27_26_SHIFT 26 -#define DDR_PHY_DTPR4_RESERVED_27_26_MASK 0x0C000000U +#define DDR_PHY_DTPR4_RESERVED_27_26_DEFVAL 0x01C02B10 +#define DDR_PHY_DTPR4_RESERVED_27_26_SHIFT 26 +#define DDR_PHY_DTPR4_RESERVED_27_26_MASK 0x0C000000U -/*Refresh-to-Refresh*/ +/* +* Refresh-to-Refresh +*/ #undef DDR_PHY_DTPR4_TRFC_DEFVAL #undef DDR_PHY_DTPR4_TRFC_SHIFT #undef DDR_PHY_DTPR4_TRFC_MASK -#define DDR_PHY_DTPR4_TRFC_DEFVAL 0x01C02B10 -#define DDR_PHY_DTPR4_TRFC_SHIFT 16 -#define DDR_PHY_DTPR4_TRFC_MASK 0x03FF0000U +#define DDR_PHY_DTPR4_TRFC_DEFVAL 0x01C02B10 +#define DDR_PHY_DTPR4_TRFC_SHIFT 16 +#define DDR_PHY_DTPR4_TRFC_MASK 0x03FF0000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR4_RESERVED_15_14_DEFVAL #undef DDR_PHY_DTPR4_RESERVED_15_14_SHIFT #undef DDR_PHY_DTPR4_RESERVED_15_14_MASK -#define DDR_PHY_DTPR4_RESERVED_15_14_DEFVAL 0x01C02B10 -#define DDR_PHY_DTPR4_RESERVED_15_14_SHIFT 14 -#define DDR_PHY_DTPR4_RESERVED_15_14_MASK 0x0000C000U +#define DDR_PHY_DTPR4_RESERVED_15_14_DEFVAL 0x01C02B10 +#define DDR_PHY_DTPR4_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_DTPR4_RESERVED_15_14_MASK 0x0000C000U -/*Write leveling output delay*/ +/* +* Write leveling output delay +*/ #undef DDR_PHY_DTPR4_TWLO_DEFVAL #undef DDR_PHY_DTPR4_TWLO_SHIFT #undef DDR_PHY_DTPR4_TWLO_MASK -#define DDR_PHY_DTPR4_TWLO_DEFVAL 0x01C02B10 -#define DDR_PHY_DTPR4_TWLO_SHIFT 8 -#define DDR_PHY_DTPR4_TWLO_MASK 0x00003F00U +#define DDR_PHY_DTPR4_TWLO_DEFVAL 0x01C02B10 +#define DDR_PHY_DTPR4_TWLO_SHIFT 8 +#define DDR_PHY_DTPR4_TWLO_MASK 0x00003F00U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR4_RESERVED_7_5_DEFVAL #undef DDR_PHY_DTPR4_RESERVED_7_5_SHIFT #undef DDR_PHY_DTPR4_RESERVED_7_5_MASK -#define DDR_PHY_DTPR4_RESERVED_7_5_DEFVAL 0x01C02B10 -#define DDR_PHY_DTPR4_RESERVED_7_5_SHIFT 5 -#define DDR_PHY_DTPR4_RESERVED_7_5_MASK 0x000000E0U +#define DDR_PHY_DTPR4_RESERVED_7_5_DEFVAL 0x01C02B10 +#define DDR_PHY_DTPR4_RESERVED_7_5_SHIFT 5 +#define DDR_PHY_DTPR4_RESERVED_7_5_MASK 0x000000E0U -/*Power down exit delay*/ +/* +* Power down exit delay +*/ #undef DDR_PHY_DTPR4_TXP_DEFVAL #undef DDR_PHY_DTPR4_TXP_SHIFT #undef DDR_PHY_DTPR4_TXP_MASK -#define DDR_PHY_DTPR4_TXP_DEFVAL 0x01C02B10 -#define DDR_PHY_DTPR4_TXP_SHIFT 0 -#define DDR_PHY_DTPR4_TXP_MASK 0x0000001FU +#define DDR_PHY_DTPR4_TXP_DEFVAL 0x01C02B10 +#define DDR_PHY_DTPR4_TXP_SHIFT 0 +#define DDR_PHY_DTPR4_TXP_MASK 0x0000001FU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR5_RESERVED_31_24_DEFVAL #undef DDR_PHY_DTPR5_RESERVED_31_24_SHIFT #undef DDR_PHY_DTPR5_RESERVED_31_24_MASK -#define DDR_PHY_DTPR5_RESERVED_31_24_DEFVAL 0x00872716 -#define DDR_PHY_DTPR5_RESERVED_31_24_SHIFT 24 -#define DDR_PHY_DTPR5_RESERVED_31_24_MASK 0xFF000000U +#define DDR_PHY_DTPR5_RESERVED_31_24_DEFVAL 0x00872716 +#define DDR_PHY_DTPR5_RESERVED_31_24_SHIFT 24 +#define DDR_PHY_DTPR5_RESERVED_31_24_MASK 0xFF000000U -/*Activate to activate command delay (same bank)*/ +/* +* Activate to activate command delay (same bank) +*/ #undef DDR_PHY_DTPR5_TRC_DEFVAL #undef DDR_PHY_DTPR5_TRC_SHIFT #undef DDR_PHY_DTPR5_TRC_MASK -#define DDR_PHY_DTPR5_TRC_DEFVAL 0x00872716 -#define DDR_PHY_DTPR5_TRC_SHIFT 16 -#define DDR_PHY_DTPR5_TRC_MASK 0x00FF0000U +#define DDR_PHY_DTPR5_TRC_DEFVAL 0x00872716 +#define DDR_PHY_DTPR5_TRC_SHIFT 16 +#define DDR_PHY_DTPR5_TRC_MASK 0x00FF0000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR5_RESERVED_15_DEFVAL #undef DDR_PHY_DTPR5_RESERVED_15_SHIFT #undef DDR_PHY_DTPR5_RESERVED_15_MASK -#define DDR_PHY_DTPR5_RESERVED_15_DEFVAL 0x00872716 -#define DDR_PHY_DTPR5_RESERVED_15_SHIFT 15 -#define DDR_PHY_DTPR5_RESERVED_15_MASK 0x00008000U +#define DDR_PHY_DTPR5_RESERVED_15_DEFVAL 0x00872716 +#define DDR_PHY_DTPR5_RESERVED_15_SHIFT 15 +#define DDR_PHY_DTPR5_RESERVED_15_MASK 0x00008000U -/*Activate to read or write delay*/ +/* +* Activate to read or write delay +*/ #undef DDR_PHY_DTPR5_TRCD_DEFVAL #undef DDR_PHY_DTPR5_TRCD_SHIFT #undef DDR_PHY_DTPR5_TRCD_MASK -#define DDR_PHY_DTPR5_TRCD_DEFVAL 0x00872716 -#define DDR_PHY_DTPR5_TRCD_SHIFT 8 -#define DDR_PHY_DTPR5_TRCD_MASK 0x00007F00U +#define DDR_PHY_DTPR5_TRCD_DEFVAL 0x00872716 +#define DDR_PHY_DTPR5_TRCD_SHIFT 8 +#define DDR_PHY_DTPR5_TRCD_MASK 0x00007F00U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR5_RESERVED_7_5_DEFVAL #undef DDR_PHY_DTPR5_RESERVED_7_5_SHIFT #undef DDR_PHY_DTPR5_RESERVED_7_5_MASK -#define DDR_PHY_DTPR5_RESERVED_7_5_DEFVAL 0x00872716 -#define DDR_PHY_DTPR5_RESERVED_7_5_SHIFT 5 -#define DDR_PHY_DTPR5_RESERVED_7_5_MASK 0x000000E0U +#define DDR_PHY_DTPR5_RESERVED_7_5_DEFVAL 0x00872716 +#define DDR_PHY_DTPR5_RESERVED_7_5_SHIFT 5 +#define DDR_PHY_DTPR5_RESERVED_7_5_MASK 0x000000E0U -/*Internal write to read command delay*/ +/* +* Internal write to read command delay +*/ #undef DDR_PHY_DTPR5_TWTR_DEFVAL #undef DDR_PHY_DTPR5_TWTR_SHIFT #undef DDR_PHY_DTPR5_TWTR_MASK -#define DDR_PHY_DTPR5_TWTR_DEFVAL 0x00872716 -#define DDR_PHY_DTPR5_TWTR_SHIFT 0 -#define DDR_PHY_DTPR5_TWTR_MASK 0x0000001FU +#define DDR_PHY_DTPR5_TWTR_DEFVAL 0x00872716 +#define DDR_PHY_DTPR5_TWTR_SHIFT 0 +#define DDR_PHY_DTPR5_TWTR_MASK 0x0000001FU -/*PUB Write Latency Enable*/ +/* +* PUB Write Latency Enable +*/ #undef DDR_PHY_DTPR6_PUBWLEN_DEFVAL #undef DDR_PHY_DTPR6_PUBWLEN_SHIFT #undef DDR_PHY_DTPR6_PUBWLEN_MASK -#define DDR_PHY_DTPR6_PUBWLEN_DEFVAL 0x00000505 -#define DDR_PHY_DTPR6_PUBWLEN_SHIFT 31 -#define DDR_PHY_DTPR6_PUBWLEN_MASK 0x80000000U +#define DDR_PHY_DTPR6_PUBWLEN_DEFVAL 0x00000505 +#define DDR_PHY_DTPR6_PUBWLEN_SHIFT 31 +#define DDR_PHY_DTPR6_PUBWLEN_MASK 0x80000000U -/*PUB Read Latency Enable*/ +/* +* PUB Read Latency Enable +*/ #undef DDR_PHY_DTPR6_PUBRLEN_DEFVAL #undef DDR_PHY_DTPR6_PUBRLEN_SHIFT #undef DDR_PHY_DTPR6_PUBRLEN_MASK -#define DDR_PHY_DTPR6_PUBRLEN_DEFVAL 0x00000505 -#define DDR_PHY_DTPR6_PUBRLEN_SHIFT 30 -#define DDR_PHY_DTPR6_PUBRLEN_MASK 0x40000000U +#define DDR_PHY_DTPR6_PUBRLEN_DEFVAL 0x00000505 +#define DDR_PHY_DTPR6_PUBRLEN_SHIFT 30 +#define DDR_PHY_DTPR6_PUBRLEN_MASK 0x40000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR6_RESERVED_29_14_DEFVAL #undef DDR_PHY_DTPR6_RESERVED_29_14_SHIFT #undef DDR_PHY_DTPR6_RESERVED_29_14_MASK -#define DDR_PHY_DTPR6_RESERVED_29_14_DEFVAL 0x00000505 -#define DDR_PHY_DTPR6_RESERVED_29_14_SHIFT 14 -#define DDR_PHY_DTPR6_RESERVED_29_14_MASK 0x3FFFC000U +#define DDR_PHY_DTPR6_RESERVED_29_14_DEFVAL 0x00000505 +#define DDR_PHY_DTPR6_RESERVED_29_14_SHIFT 14 +#define DDR_PHY_DTPR6_RESERVED_29_14_MASK 0x3FFFC000U -/*Write Latency*/ +/* +* Write Latency +*/ #undef DDR_PHY_DTPR6_PUBWL_DEFVAL #undef DDR_PHY_DTPR6_PUBWL_SHIFT #undef DDR_PHY_DTPR6_PUBWL_MASK -#define DDR_PHY_DTPR6_PUBWL_DEFVAL 0x00000505 -#define DDR_PHY_DTPR6_PUBWL_SHIFT 8 -#define DDR_PHY_DTPR6_PUBWL_MASK 0x00003F00U +#define DDR_PHY_DTPR6_PUBWL_DEFVAL 0x00000505 +#define DDR_PHY_DTPR6_PUBWL_SHIFT 8 +#define DDR_PHY_DTPR6_PUBWL_MASK 0x00003F00U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR6_RESERVED_7_6_DEFVAL #undef DDR_PHY_DTPR6_RESERVED_7_6_SHIFT #undef DDR_PHY_DTPR6_RESERVED_7_6_MASK -#define DDR_PHY_DTPR6_RESERVED_7_6_DEFVAL 0x00000505 -#define DDR_PHY_DTPR6_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_DTPR6_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_DTPR6_RESERVED_7_6_DEFVAL 0x00000505 +#define DDR_PHY_DTPR6_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DTPR6_RESERVED_7_6_MASK 0x000000C0U -/*Read Latency*/ +/* +* Read Latency +*/ #undef DDR_PHY_DTPR6_PUBRL_DEFVAL #undef DDR_PHY_DTPR6_PUBRL_SHIFT #undef DDR_PHY_DTPR6_PUBRL_MASK -#define DDR_PHY_DTPR6_PUBRL_DEFVAL 0x00000505 -#define DDR_PHY_DTPR6_PUBRL_SHIFT 0 -#define DDR_PHY_DTPR6_PUBRL_MASK 0x0000003FU +#define DDR_PHY_DTPR6_PUBRL_DEFVAL 0x00000505 +#define DDR_PHY_DTPR6_PUBRL_SHIFT 0 +#define DDR_PHY_DTPR6_PUBRL_MASK 0x0000003FU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_RDIMMGCR0_RESERVED_31_DEFVAL #undef DDR_PHY_RDIMMGCR0_RESERVED_31_SHIFT #undef DDR_PHY_RDIMMGCR0_RESERVED_31_MASK -#define DDR_PHY_RDIMMGCR0_RESERVED_31_DEFVAL 0x08400020 -#define DDR_PHY_RDIMMGCR0_RESERVED_31_SHIFT 31 -#define DDR_PHY_RDIMMGCR0_RESERVED_31_MASK 0x80000000U +#define DDR_PHY_RDIMMGCR0_RESERVED_31_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_RESERVED_31_SHIFT 31 +#define DDR_PHY_RDIMMGCR0_RESERVED_31_MASK 0x80000000U -/*RDMIMM Quad CS Enable*/ +/* +* RDMIMM Quad CS Enable +*/ #undef DDR_PHY_RDIMMGCR0_QCSEN_DEFVAL #undef DDR_PHY_RDIMMGCR0_QCSEN_SHIFT #undef DDR_PHY_RDIMMGCR0_QCSEN_MASK -#define DDR_PHY_RDIMMGCR0_QCSEN_DEFVAL 0x08400020 -#define DDR_PHY_RDIMMGCR0_QCSEN_SHIFT 30 -#define DDR_PHY_RDIMMGCR0_QCSEN_MASK 0x40000000U +#define DDR_PHY_RDIMMGCR0_QCSEN_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_QCSEN_SHIFT 30 +#define DDR_PHY_RDIMMGCR0_QCSEN_MASK 0x40000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_RDIMMGCR0_RESERVED_29_28_DEFVAL #undef DDR_PHY_RDIMMGCR0_RESERVED_29_28_SHIFT #undef DDR_PHY_RDIMMGCR0_RESERVED_29_28_MASK -#define DDR_PHY_RDIMMGCR0_RESERVED_29_28_DEFVAL 0x08400020 -#define DDR_PHY_RDIMMGCR0_RESERVED_29_28_SHIFT 28 -#define DDR_PHY_RDIMMGCR0_RESERVED_29_28_MASK 0x30000000U +#define DDR_PHY_RDIMMGCR0_RESERVED_29_28_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_RESERVED_29_28_SHIFT 28 +#define DDR_PHY_RDIMMGCR0_RESERVED_29_28_MASK 0x30000000U -/*RDIMM Outputs I/O Mode*/ +/* +* RDIMM Outputs I/O Mode +*/ #undef DDR_PHY_RDIMMGCR0_RDIMMIOM_DEFVAL #undef DDR_PHY_RDIMMGCR0_RDIMMIOM_SHIFT #undef DDR_PHY_RDIMMGCR0_RDIMMIOM_MASK -#define DDR_PHY_RDIMMGCR0_RDIMMIOM_DEFVAL 0x08400020 -#define DDR_PHY_RDIMMGCR0_RDIMMIOM_SHIFT 27 -#define DDR_PHY_RDIMMGCR0_RDIMMIOM_MASK 0x08000000U +#define DDR_PHY_RDIMMGCR0_RDIMMIOM_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_RDIMMIOM_SHIFT 27 +#define DDR_PHY_RDIMMGCR0_RDIMMIOM_MASK 0x08000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_RDIMMGCR0_RESERVED_26_24_DEFVAL #undef DDR_PHY_RDIMMGCR0_RESERVED_26_24_SHIFT #undef DDR_PHY_RDIMMGCR0_RESERVED_26_24_MASK -#define DDR_PHY_RDIMMGCR0_RESERVED_26_24_DEFVAL 0x08400020 -#define DDR_PHY_RDIMMGCR0_RESERVED_26_24_SHIFT 24 -#define DDR_PHY_RDIMMGCR0_RESERVED_26_24_MASK 0x07000000U +#define DDR_PHY_RDIMMGCR0_RESERVED_26_24_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_RESERVED_26_24_SHIFT 24 +#define DDR_PHY_RDIMMGCR0_RESERVED_26_24_MASK 0x07000000U -/*ERROUT# Output Enable*/ +/* +* ERROUT# Output Enable +*/ #undef DDR_PHY_RDIMMGCR0_ERROUTOE_DEFVAL #undef DDR_PHY_RDIMMGCR0_ERROUTOE_SHIFT #undef DDR_PHY_RDIMMGCR0_ERROUTOE_MASK -#define DDR_PHY_RDIMMGCR0_ERROUTOE_DEFVAL 0x08400020 -#define DDR_PHY_RDIMMGCR0_ERROUTOE_SHIFT 23 -#define DDR_PHY_RDIMMGCR0_ERROUTOE_MASK 0x00800000U +#define DDR_PHY_RDIMMGCR0_ERROUTOE_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_ERROUTOE_SHIFT 23 +#define DDR_PHY_RDIMMGCR0_ERROUTOE_MASK 0x00800000U -/*ERROUT# I/O Mode*/ +/* +* ERROUT# I/O Mode +*/ #undef DDR_PHY_RDIMMGCR0_ERROUTIOM_DEFVAL #undef DDR_PHY_RDIMMGCR0_ERROUTIOM_SHIFT #undef DDR_PHY_RDIMMGCR0_ERROUTIOM_MASK -#define DDR_PHY_RDIMMGCR0_ERROUTIOM_DEFVAL 0x08400020 -#define DDR_PHY_RDIMMGCR0_ERROUTIOM_SHIFT 22 -#define DDR_PHY_RDIMMGCR0_ERROUTIOM_MASK 0x00400000U +#define DDR_PHY_RDIMMGCR0_ERROUTIOM_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_ERROUTIOM_SHIFT 22 +#define DDR_PHY_RDIMMGCR0_ERROUTIOM_MASK 0x00400000U -/*ERROUT# Power Down Receiver*/ +/* +* ERROUT# Power Down Receiver +*/ #undef DDR_PHY_RDIMMGCR0_ERROUTPDR_DEFVAL #undef DDR_PHY_RDIMMGCR0_ERROUTPDR_SHIFT #undef DDR_PHY_RDIMMGCR0_ERROUTPDR_MASK -#define DDR_PHY_RDIMMGCR0_ERROUTPDR_DEFVAL 0x08400020 -#define DDR_PHY_RDIMMGCR0_ERROUTPDR_SHIFT 21 -#define DDR_PHY_RDIMMGCR0_ERROUTPDR_MASK 0x00200000U +#define DDR_PHY_RDIMMGCR0_ERROUTPDR_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_ERROUTPDR_SHIFT 21 +#define DDR_PHY_RDIMMGCR0_ERROUTPDR_MASK 0x00200000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_RDIMMGCR0_RESERVED_20_DEFVAL #undef DDR_PHY_RDIMMGCR0_RESERVED_20_SHIFT #undef DDR_PHY_RDIMMGCR0_RESERVED_20_MASK -#define DDR_PHY_RDIMMGCR0_RESERVED_20_DEFVAL 0x08400020 -#define DDR_PHY_RDIMMGCR0_RESERVED_20_SHIFT 20 -#define DDR_PHY_RDIMMGCR0_RESERVED_20_MASK 0x00100000U +#define DDR_PHY_RDIMMGCR0_RESERVED_20_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_RESERVED_20_SHIFT 20 +#define DDR_PHY_RDIMMGCR0_RESERVED_20_MASK 0x00100000U -/*ERROUT# On-Die Termination*/ +/* +* ERROUT# On-Die Termination +*/ #undef DDR_PHY_RDIMMGCR0_ERROUTODT_DEFVAL #undef DDR_PHY_RDIMMGCR0_ERROUTODT_SHIFT #undef DDR_PHY_RDIMMGCR0_ERROUTODT_MASK -#define DDR_PHY_RDIMMGCR0_ERROUTODT_DEFVAL 0x08400020 -#define DDR_PHY_RDIMMGCR0_ERROUTODT_SHIFT 19 -#define DDR_PHY_RDIMMGCR0_ERROUTODT_MASK 0x00080000U +#define DDR_PHY_RDIMMGCR0_ERROUTODT_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_ERROUTODT_SHIFT 19 +#define DDR_PHY_RDIMMGCR0_ERROUTODT_MASK 0x00080000U -/*Load Reduced DIMM*/ +/* +* Load Reduced DIMM +*/ #undef DDR_PHY_RDIMMGCR0_LRDIMM_DEFVAL #undef DDR_PHY_RDIMMGCR0_LRDIMM_SHIFT #undef DDR_PHY_RDIMMGCR0_LRDIMM_MASK -#define DDR_PHY_RDIMMGCR0_LRDIMM_DEFVAL 0x08400020 -#define DDR_PHY_RDIMMGCR0_LRDIMM_SHIFT 18 -#define DDR_PHY_RDIMMGCR0_LRDIMM_MASK 0x00040000U +#define DDR_PHY_RDIMMGCR0_LRDIMM_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_LRDIMM_SHIFT 18 +#define DDR_PHY_RDIMMGCR0_LRDIMM_MASK 0x00040000U -/*PAR_IN I/O Mode*/ +/* +* PAR_IN I/O Mode +*/ #undef DDR_PHY_RDIMMGCR0_PARINIOM_DEFVAL #undef DDR_PHY_RDIMMGCR0_PARINIOM_SHIFT #undef DDR_PHY_RDIMMGCR0_PARINIOM_MASK -#define DDR_PHY_RDIMMGCR0_PARINIOM_DEFVAL 0x08400020 -#define DDR_PHY_RDIMMGCR0_PARINIOM_SHIFT 17 -#define DDR_PHY_RDIMMGCR0_PARINIOM_MASK 0x00020000U +#define DDR_PHY_RDIMMGCR0_PARINIOM_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_PARINIOM_SHIFT 17 +#define DDR_PHY_RDIMMGCR0_PARINIOM_MASK 0x00020000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_RDIMMGCR0_RESERVED_16_8_DEFVAL #undef DDR_PHY_RDIMMGCR0_RESERVED_16_8_SHIFT #undef DDR_PHY_RDIMMGCR0_RESERVED_16_8_MASK -#define DDR_PHY_RDIMMGCR0_RESERVED_16_8_DEFVAL 0x08400020 -#define DDR_PHY_RDIMMGCR0_RESERVED_16_8_SHIFT 8 -#define DDR_PHY_RDIMMGCR0_RESERVED_16_8_MASK 0x0001FF00U +#define DDR_PHY_RDIMMGCR0_RESERVED_16_8_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_RESERVED_16_8_SHIFT 8 +#define DDR_PHY_RDIMMGCR0_RESERVED_16_8_MASK 0x0001FF00U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_DEFVAL #undef DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_SHIFT #undef DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_MASK -#define DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_DEFVAL 0x08400020 -#define DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_SHIFT 6 -#define DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_MASK 0x000000C0U +#define DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_SHIFT 6 +#define DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_MASK 0x000000C0U -/*Rank Mirror Enable.*/ +/* +* Rank Mirror Enable. +*/ #undef DDR_PHY_RDIMMGCR0_RNKMRREN_DEFVAL #undef DDR_PHY_RDIMMGCR0_RNKMRREN_SHIFT #undef DDR_PHY_RDIMMGCR0_RNKMRREN_MASK -#define DDR_PHY_RDIMMGCR0_RNKMRREN_DEFVAL 0x08400020 -#define DDR_PHY_RDIMMGCR0_RNKMRREN_SHIFT 4 -#define DDR_PHY_RDIMMGCR0_RNKMRREN_MASK 0x00000030U +#define DDR_PHY_RDIMMGCR0_RNKMRREN_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_RNKMRREN_SHIFT 4 +#define DDR_PHY_RDIMMGCR0_RNKMRREN_MASK 0x00000030U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_RDIMMGCR0_RESERVED_3_DEFVAL #undef DDR_PHY_RDIMMGCR0_RESERVED_3_SHIFT #undef DDR_PHY_RDIMMGCR0_RESERVED_3_MASK -#define DDR_PHY_RDIMMGCR0_RESERVED_3_DEFVAL 0x08400020 -#define DDR_PHY_RDIMMGCR0_RESERVED_3_SHIFT 3 -#define DDR_PHY_RDIMMGCR0_RESERVED_3_MASK 0x00000008U +#define DDR_PHY_RDIMMGCR0_RESERVED_3_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_RESERVED_3_SHIFT 3 +#define DDR_PHY_RDIMMGCR0_RESERVED_3_MASK 0x00000008U -/*Stop on Parity Error*/ +/* +* Stop on Parity Error +*/ #undef DDR_PHY_RDIMMGCR0_SOPERR_DEFVAL #undef DDR_PHY_RDIMMGCR0_SOPERR_SHIFT #undef DDR_PHY_RDIMMGCR0_SOPERR_MASK -#define DDR_PHY_RDIMMGCR0_SOPERR_DEFVAL 0x08400020 -#define DDR_PHY_RDIMMGCR0_SOPERR_SHIFT 2 -#define DDR_PHY_RDIMMGCR0_SOPERR_MASK 0x00000004U +#define DDR_PHY_RDIMMGCR0_SOPERR_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_SOPERR_SHIFT 2 +#define DDR_PHY_RDIMMGCR0_SOPERR_MASK 0x00000004U -/*Parity Error No Registering*/ +/* +* Parity Error No Registering +*/ #undef DDR_PHY_RDIMMGCR0_ERRNOREG_DEFVAL #undef DDR_PHY_RDIMMGCR0_ERRNOREG_SHIFT #undef DDR_PHY_RDIMMGCR0_ERRNOREG_MASK -#define DDR_PHY_RDIMMGCR0_ERRNOREG_DEFVAL 0x08400020 -#define DDR_PHY_RDIMMGCR0_ERRNOREG_SHIFT 1 -#define DDR_PHY_RDIMMGCR0_ERRNOREG_MASK 0x00000002U +#define DDR_PHY_RDIMMGCR0_ERRNOREG_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_ERRNOREG_SHIFT 1 +#define DDR_PHY_RDIMMGCR0_ERRNOREG_MASK 0x00000002U -/*Registered DIMM*/ +/* +* Registered DIMM +*/ #undef DDR_PHY_RDIMMGCR0_RDIMM_DEFVAL #undef DDR_PHY_RDIMMGCR0_RDIMM_SHIFT #undef DDR_PHY_RDIMMGCR0_RDIMM_MASK -#define DDR_PHY_RDIMMGCR0_RDIMM_DEFVAL 0x08400020 -#define DDR_PHY_RDIMMGCR0_RDIMM_SHIFT 0 -#define DDR_PHY_RDIMMGCR0_RDIMM_MASK 0x00000001U +#define DDR_PHY_RDIMMGCR0_RDIMM_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_RDIMM_SHIFT 0 +#define DDR_PHY_RDIMMGCR0_RDIMM_MASK 0x00000001U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_RDIMMGCR1_RESERVED_31_29_DEFVAL #undef DDR_PHY_RDIMMGCR1_RESERVED_31_29_SHIFT #undef DDR_PHY_RDIMMGCR1_RESERVED_31_29_MASK -#define DDR_PHY_RDIMMGCR1_RESERVED_31_29_DEFVAL 0x00000C80 -#define DDR_PHY_RDIMMGCR1_RESERVED_31_29_SHIFT 29 -#define DDR_PHY_RDIMMGCR1_RESERVED_31_29_MASK 0xE0000000U +#define DDR_PHY_RDIMMGCR1_RESERVED_31_29_DEFVAL 0x00000C80 +#define DDR_PHY_RDIMMGCR1_RESERVED_31_29_SHIFT 29 +#define DDR_PHY_RDIMMGCR1_RESERVED_31_29_MASK 0xE0000000U -/*Address [17] B-side Inversion Disable*/ +/* +* Address [17] B-side Inversion Disable +*/ #undef DDR_PHY_RDIMMGCR1_A17BID_DEFVAL #undef DDR_PHY_RDIMMGCR1_A17BID_SHIFT #undef DDR_PHY_RDIMMGCR1_A17BID_MASK -#define DDR_PHY_RDIMMGCR1_A17BID_DEFVAL 0x00000C80 -#define DDR_PHY_RDIMMGCR1_A17BID_SHIFT 28 -#define DDR_PHY_RDIMMGCR1_A17BID_MASK 0x10000000U +#define DDR_PHY_RDIMMGCR1_A17BID_DEFVAL 0x00000C80 +#define DDR_PHY_RDIMMGCR1_A17BID_SHIFT 28 +#define DDR_PHY_RDIMMGCR1_A17BID_MASK 0x10000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_RDIMMGCR1_RESERVED_27_DEFVAL #undef DDR_PHY_RDIMMGCR1_RESERVED_27_SHIFT #undef DDR_PHY_RDIMMGCR1_RESERVED_27_MASK -#define DDR_PHY_RDIMMGCR1_RESERVED_27_DEFVAL 0x00000C80 -#define DDR_PHY_RDIMMGCR1_RESERVED_27_SHIFT 27 -#define DDR_PHY_RDIMMGCR1_RESERVED_27_MASK 0x08000000U +#define DDR_PHY_RDIMMGCR1_RESERVED_27_DEFVAL 0x00000C80 +#define DDR_PHY_RDIMMGCR1_RESERVED_27_SHIFT 27 +#define DDR_PHY_RDIMMGCR1_RESERVED_27_MASK 0x08000000U -/*Command word to command word programming delay*/ +/* +* Command word to command word programming delay +*/ #undef DDR_PHY_RDIMMGCR1_TBCMRD_L2_DEFVAL #undef DDR_PHY_RDIMMGCR1_TBCMRD_L2_SHIFT #undef DDR_PHY_RDIMMGCR1_TBCMRD_L2_MASK -#define DDR_PHY_RDIMMGCR1_TBCMRD_L2_DEFVAL 0x00000C80 -#define DDR_PHY_RDIMMGCR1_TBCMRD_L2_SHIFT 24 -#define DDR_PHY_RDIMMGCR1_TBCMRD_L2_MASK 0x07000000U +#define DDR_PHY_RDIMMGCR1_TBCMRD_L2_DEFVAL 0x00000C80 +#define DDR_PHY_RDIMMGCR1_TBCMRD_L2_SHIFT 24 +#define DDR_PHY_RDIMMGCR1_TBCMRD_L2_MASK 0x07000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_RDIMMGCR1_RESERVED_23_DEFVAL #undef DDR_PHY_RDIMMGCR1_RESERVED_23_SHIFT #undef DDR_PHY_RDIMMGCR1_RESERVED_23_MASK -#define DDR_PHY_RDIMMGCR1_RESERVED_23_DEFVAL 0x00000C80 -#define DDR_PHY_RDIMMGCR1_RESERVED_23_SHIFT 23 -#define DDR_PHY_RDIMMGCR1_RESERVED_23_MASK 0x00800000U +#define DDR_PHY_RDIMMGCR1_RESERVED_23_DEFVAL 0x00000C80 +#define DDR_PHY_RDIMMGCR1_RESERVED_23_SHIFT 23 +#define DDR_PHY_RDIMMGCR1_RESERVED_23_MASK 0x00800000U -/*Command word to command word programming delay*/ +/* +* Command word to command word programming delay +*/ #undef DDR_PHY_RDIMMGCR1_TBCMRD_L_DEFVAL #undef DDR_PHY_RDIMMGCR1_TBCMRD_L_SHIFT #undef DDR_PHY_RDIMMGCR1_TBCMRD_L_MASK -#define DDR_PHY_RDIMMGCR1_TBCMRD_L_DEFVAL 0x00000C80 -#define DDR_PHY_RDIMMGCR1_TBCMRD_L_SHIFT 20 -#define DDR_PHY_RDIMMGCR1_TBCMRD_L_MASK 0x00700000U +#define DDR_PHY_RDIMMGCR1_TBCMRD_L_DEFVAL 0x00000C80 +#define DDR_PHY_RDIMMGCR1_TBCMRD_L_SHIFT 20 +#define DDR_PHY_RDIMMGCR1_TBCMRD_L_MASK 0x00700000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_RDIMMGCR1_RESERVED_19_DEFVAL #undef DDR_PHY_RDIMMGCR1_RESERVED_19_SHIFT #undef DDR_PHY_RDIMMGCR1_RESERVED_19_MASK -#define DDR_PHY_RDIMMGCR1_RESERVED_19_DEFVAL 0x00000C80 -#define DDR_PHY_RDIMMGCR1_RESERVED_19_SHIFT 19 -#define DDR_PHY_RDIMMGCR1_RESERVED_19_MASK 0x00080000U +#define DDR_PHY_RDIMMGCR1_RESERVED_19_DEFVAL 0x00000C80 +#define DDR_PHY_RDIMMGCR1_RESERVED_19_SHIFT 19 +#define DDR_PHY_RDIMMGCR1_RESERVED_19_MASK 0x00080000U -/*Command word to command word programming delay*/ +/* +* Command word to command word programming delay +*/ #undef DDR_PHY_RDIMMGCR1_TBCMRD_DEFVAL #undef DDR_PHY_RDIMMGCR1_TBCMRD_SHIFT #undef DDR_PHY_RDIMMGCR1_TBCMRD_MASK -#define DDR_PHY_RDIMMGCR1_TBCMRD_DEFVAL 0x00000C80 -#define DDR_PHY_RDIMMGCR1_TBCMRD_SHIFT 16 -#define DDR_PHY_RDIMMGCR1_TBCMRD_MASK 0x00070000U +#define DDR_PHY_RDIMMGCR1_TBCMRD_DEFVAL 0x00000C80 +#define DDR_PHY_RDIMMGCR1_TBCMRD_SHIFT 16 +#define DDR_PHY_RDIMMGCR1_TBCMRD_MASK 0x00070000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_RDIMMGCR1_RESERVED_15_14_DEFVAL #undef DDR_PHY_RDIMMGCR1_RESERVED_15_14_SHIFT #undef DDR_PHY_RDIMMGCR1_RESERVED_15_14_MASK -#define DDR_PHY_RDIMMGCR1_RESERVED_15_14_DEFVAL 0x00000C80 -#define DDR_PHY_RDIMMGCR1_RESERVED_15_14_SHIFT 14 -#define DDR_PHY_RDIMMGCR1_RESERVED_15_14_MASK 0x0000C000U +#define DDR_PHY_RDIMMGCR1_RESERVED_15_14_DEFVAL 0x00000C80 +#define DDR_PHY_RDIMMGCR1_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_RDIMMGCR1_RESERVED_15_14_MASK 0x0000C000U -/*Stabilization time*/ +/* +* Stabilization time +*/ #undef DDR_PHY_RDIMMGCR1_TBCSTAB_DEFVAL #undef DDR_PHY_RDIMMGCR1_TBCSTAB_SHIFT #undef DDR_PHY_RDIMMGCR1_TBCSTAB_MASK -#define DDR_PHY_RDIMMGCR1_TBCSTAB_DEFVAL 0x00000C80 -#define DDR_PHY_RDIMMGCR1_TBCSTAB_SHIFT 0 -#define DDR_PHY_RDIMMGCR1_TBCSTAB_MASK 0x00003FFFU +#define DDR_PHY_RDIMMGCR1_TBCSTAB_DEFVAL 0x00000C80 +#define DDR_PHY_RDIMMGCR1_TBCSTAB_SHIFT 0 +#define DDR_PHY_RDIMMGCR1_TBCSTAB_MASK 0x00003FFFU -/*DDR4/DDR3 Control Word 7*/ +/* +* DDR4/DDR3 Control Word 7 +*/ #undef DDR_PHY_RDIMMCR0_RC7_DEFVAL #undef DDR_PHY_RDIMMCR0_RC7_SHIFT #undef DDR_PHY_RDIMMCR0_RC7_MASK -#define DDR_PHY_RDIMMCR0_RC7_DEFVAL 0x00000000 -#define DDR_PHY_RDIMMCR0_RC7_SHIFT 28 -#define DDR_PHY_RDIMMCR0_RC7_MASK 0xF0000000U +#define DDR_PHY_RDIMMCR0_RC7_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR0_RC7_SHIFT 28 +#define DDR_PHY_RDIMMCR0_RC7_MASK 0xF0000000U -/*DDR4 Control Word 6 (Comman space Control Word) / DDR3 Reserved*/ +/* +* DDR4 Control Word 6 (Comman space Control Word) / DDR3 Reserved +*/ #undef DDR_PHY_RDIMMCR0_RC6_DEFVAL #undef DDR_PHY_RDIMMCR0_RC6_SHIFT #undef DDR_PHY_RDIMMCR0_RC6_MASK -#define DDR_PHY_RDIMMCR0_RC6_DEFVAL 0x00000000 -#define DDR_PHY_RDIMMCR0_RC6_SHIFT 24 -#define DDR_PHY_RDIMMCR0_RC6_MASK 0x0F000000U +#define DDR_PHY_RDIMMCR0_RC6_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR0_RC6_SHIFT 24 +#define DDR_PHY_RDIMMCR0_RC6_MASK 0x0F000000U -/*DDR4/DDR3 Control Word 5 (CK Driver Characteristics Control Word)*/ +/* +* DDR4/DDR3 Control Word 5 (CK Driver Characteristics Control Word) +*/ #undef DDR_PHY_RDIMMCR0_RC5_DEFVAL #undef DDR_PHY_RDIMMCR0_RC5_SHIFT #undef DDR_PHY_RDIMMCR0_RC5_MASK -#define DDR_PHY_RDIMMCR0_RC5_DEFVAL 0x00000000 -#define DDR_PHY_RDIMMCR0_RC5_SHIFT 20 -#define DDR_PHY_RDIMMCR0_RC5_MASK 0x00F00000U +#define DDR_PHY_RDIMMCR0_RC5_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR0_RC5_SHIFT 20 +#define DDR_PHY_RDIMMCR0_RC5_MASK 0x00F00000U -/*DDR4 Control Word 4 (ODT and CKE Signals Driver Characteristics Control Word) / DDR3 Control Word 4 (Control Signals Driver C - aracteristics Control Word)*/ +/* +* DDR4 Control Word 4 (ODT and CKE Signals Driver Characteristics Control + * Word) / DDR3 Control Word 4 (Control Signals Driver Characteristics Cont + * rol Word) +*/ #undef DDR_PHY_RDIMMCR0_RC4_DEFVAL #undef DDR_PHY_RDIMMCR0_RC4_SHIFT #undef DDR_PHY_RDIMMCR0_RC4_MASK -#define DDR_PHY_RDIMMCR0_RC4_DEFVAL 0x00000000 -#define DDR_PHY_RDIMMCR0_RC4_SHIFT 16 -#define DDR_PHY_RDIMMCR0_RC4_MASK 0x000F0000U +#define DDR_PHY_RDIMMCR0_RC4_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR0_RC4_SHIFT 16 +#define DDR_PHY_RDIMMCR0_RC4_MASK 0x000F0000U -/*DDR4 Control Word 3 (CA and CS Signals Driver Characteristics Control Word) / DDR3 Control Word 3 (Command/Address Signals Dr - ver Characteristrics Control Word)*/ +/* +* DDR4 Control Word 3 (CA and CS Signals Driver Characteristics Control Wo + * rd) / DDR3 Control Word 3 (Command/Address Signals Driver Characteristri + * cs Control Word) +*/ #undef DDR_PHY_RDIMMCR0_RC3_DEFVAL #undef DDR_PHY_RDIMMCR0_RC3_SHIFT #undef DDR_PHY_RDIMMCR0_RC3_MASK -#define DDR_PHY_RDIMMCR0_RC3_DEFVAL 0x00000000 -#define DDR_PHY_RDIMMCR0_RC3_SHIFT 12 -#define DDR_PHY_RDIMMCR0_RC3_MASK 0x0000F000U +#define DDR_PHY_RDIMMCR0_RC3_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR0_RC3_SHIFT 12 +#define DDR_PHY_RDIMMCR0_RC3_MASK 0x0000F000U -/*DDR4 Control Word 2 (Timing and IBT Control Word) / DDR3 Control Word 2 (Timing Control Word)*/ +/* +* DDR4 Control Word 2 (Timing and IBT Control Word) / DDR3 Control Word 2 + * (Timing Control Word) +*/ #undef DDR_PHY_RDIMMCR0_RC2_DEFVAL #undef DDR_PHY_RDIMMCR0_RC2_SHIFT #undef DDR_PHY_RDIMMCR0_RC2_MASK -#define DDR_PHY_RDIMMCR0_RC2_DEFVAL 0x00000000 -#define DDR_PHY_RDIMMCR0_RC2_SHIFT 8 -#define DDR_PHY_RDIMMCR0_RC2_MASK 0x00000F00U +#define DDR_PHY_RDIMMCR0_RC2_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR0_RC2_SHIFT 8 +#define DDR_PHY_RDIMMCR0_RC2_MASK 0x00000F00U -/*DDR4/DDR3 Control Word 1 (Clock Driver Enable Control Word)*/ +/* +* DDR4/DDR3 Control Word 1 (Clock Driver Enable Control Word) +*/ #undef DDR_PHY_RDIMMCR0_RC1_DEFVAL #undef DDR_PHY_RDIMMCR0_RC1_SHIFT #undef DDR_PHY_RDIMMCR0_RC1_MASK -#define DDR_PHY_RDIMMCR0_RC1_DEFVAL 0x00000000 -#define DDR_PHY_RDIMMCR0_RC1_SHIFT 4 -#define DDR_PHY_RDIMMCR0_RC1_MASK 0x000000F0U +#define DDR_PHY_RDIMMCR0_RC1_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR0_RC1_SHIFT 4 +#define DDR_PHY_RDIMMCR0_RC1_MASK 0x000000F0U -/*DDR4/DDR3 Control Word 0 (Global Features Control Word)*/ +/* +* DDR4/DDR3 Control Word 0 (Global Features Control Word) +*/ #undef DDR_PHY_RDIMMCR0_RC0_DEFVAL #undef DDR_PHY_RDIMMCR0_RC0_SHIFT #undef DDR_PHY_RDIMMCR0_RC0_MASK -#define DDR_PHY_RDIMMCR0_RC0_DEFVAL 0x00000000 -#define DDR_PHY_RDIMMCR0_RC0_SHIFT 0 -#define DDR_PHY_RDIMMCR0_RC0_MASK 0x0000000FU +#define DDR_PHY_RDIMMCR0_RC0_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR0_RC0_SHIFT 0 +#define DDR_PHY_RDIMMCR0_RC0_MASK 0x0000000FU -/*Control Word 15*/ +/* +* Control Word 15 +*/ #undef DDR_PHY_RDIMMCR1_RC15_DEFVAL #undef DDR_PHY_RDIMMCR1_RC15_SHIFT #undef DDR_PHY_RDIMMCR1_RC15_MASK -#define DDR_PHY_RDIMMCR1_RC15_DEFVAL 0x00000000 -#define DDR_PHY_RDIMMCR1_RC15_SHIFT 28 -#define DDR_PHY_RDIMMCR1_RC15_MASK 0xF0000000U +#define DDR_PHY_RDIMMCR1_RC15_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR1_RC15_SHIFT 28 +#define DDR_PHY_RDIMMCR1_RC15_MASK 0xF0000000U -/*DDR4 Control Word 14 (Parity Control Word) / DDR3 Reserved*/ +/* +* DDR4 Control Word 14 (Parity Control Word) / DDR3 Reserved +*/ #undef DDR_PHY_RDIMMCR1_RC14_DEFVAL #undef DDR_PHY_RDIMMCR1_RC14_SHIFT #undef DDR_PHY_RDIMMCR1_RC14_MASK -#define DDR_PHY_RDIMMCR1_RC14_DEFVAL 0x00000000 -#define DDR_PHY_RDIMMCR1_RC14_SHIFT 24 -#define DDR_PHY_RDIMMCR1_RC14_MASK 0x0F000000U +#define DDR_PHY_RDIMMCR1_RC14_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR1_RC14_SHIFT 24 +#define DDR_PHY_RDIMMCR1_RC14_MASK 0x0F000000U -/*DDR4 Control Word 13 (DIMM Configuration Control Word) / DDR3 Reserved*/ +/* +* DDR4 Control Word 13 (DIMM Configuration Control Word) / DDR3 Reserved +*/ #undef DDR_PHY_RDIMMCR1_RC13_DEFVAL #undef DDR_PHY_RDIMMCR1_RC13_SHIFT #undef DDR_PHY_RDIMMCR1_RC13_MASK -#define DDR_PHY_RDIMMCR1_RC13_DEFVAL 0x00000000 -#define DDR_PHY_RDIMMCR1_RC13_SHIFT 20 -#define DDR_PHY_RDIMMCR1_RC13_MASK 0x00F00000U +#define DDR_PHY_RDIMMCR1_RC13_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR1_RC13_SHIFT 20 +#define DDR_PHY_RDIMMCR1_RC13_MASK 0x00F00000U -/*DDR4 Control Word 12 (Training Control Word) / DDR3 Reserved*/ +/* +* DDR4 Control Word 12 (Training Control Word) / DDR3 Reserved +*/ #undef DDR_PHY_RDIMMCR1_RC12_DEFVAL #undef DDR_PHY_RDIMMCR1_RC12_SHIFT #undef DDR_PHY_RDIMMCR1_RC12_MASK -#define DDR_PHY_RDIMMCR1_RC12_DEFVAL 0x00000000 -#define DDR_PHY_RDIMMCR1_RC12_SHIFT 16 -#define DDR_PHY_RDIMMCR1_RC12_MASK 0x000F0000U +#define DDR_PHY_RDIMMCR1_RC12_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR1_RC12_SHIFT 16 +#define DDR_PHY_RDIMMCR1_RC12_MASK 0x000F0000U -/*DDR4 Control Word 11 (Operating Voltage VDD and VREFCA Source Control Word) / DDR3 Control Word 11 (Operation Voltage VDD Con - rol Word)*/ +/* +* DDR4 Control Word 11 (Operating Voltage VDD and VREFCA Source Control Wo + * rd) / DDR3 Control Word 11 (Operation Voltage VDD Control Word) +*/ #undef DDR_PHY_RDIMMCR1_RC11_DEFVAL #undef DDR_PHY_RDIMMCR1_RC11_SHIFT #undef DDR_PHY_RDIMMCR1_RC11_MASK -#define DDR_PHY_RDIMMCR1_RC11_DEFVAL 0x00000000 -#define DDR_PHY_RDIMMCR1_RC11_SHIFT 12 -#define DDR_PHY_RDIMMCR1_RC11_MASK 0x0000F000U +#define DDR_PHY_RDIMMCR1_RC11_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR1_RC11_SHIFT 12 +#define DDR_PHY_RDIMMCR1_RC11_MASK 0x0000F000U -/*DDR4/DDR3 Control Word 10 (RDIMM Operating Speed Control Word)*/ +/* +* DDR4/DDR3 Control Word 10 (RDIMM Operating Speed Control Word) +*/ #undef DDR_PHY_RDIMMCR1_RC10_DEFVAL #undef DDR_PHY_RDIMMCR1_RC10_SHIFT #undef DDR_PHY_RDIMMCR1_RC10_MASK -#define DDR_PHY_RDIMMCR1_RC10_DEFVAL 0x00000000 -#define DDR_PHY_RDIMMCR1_RC10_SHIFT 8 -#define DDR_PHY_RDIMMCR1_RC10_MASK 0x00000F00U +#define DDR_PHY_RDIMMCR1_RC10_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR1_RC10_SHIFT 8 +#define DDR_PHY_RDIMMCR1_RC10_MASK 0x00000F00U -/*DDR4/DDR3 Control Word 9 (Power Saving Settings Control Word)*/ +/* +* DDR4/DDR3 Control Word 9 (Power Saving Settings Control Word) +*/ #undef DDR_PHY_RDIMMCR1_RC9_DEFVAL #undef DDR_PHY_RDIMMCR1_RC9_SHIFT #undef DDR_PHY_RDIMMCR1_RC9_MASK -#define DDR_PHY_RDIMMCR1_RC9_DEFVAL 0x00000000 -#define DDR_PHY_RDIMMCR1_RC9_SHIFT 4 -#define DDR_PHY_RDIMMCR1_RC9_MASK 0x000000F0U +#define DDR_PHY_RDIMMCR1_RC9_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR1_RC9_SHIFT 4 +#define DDR_PHY_RDIMMCR1_RC9_MASK 0x000000F0U -/*DDR4 Control Word 8 (Input/Output Configuration Control Word) / DDR3 Control Word 8 (Additional Input Bus Termination Setting - Control Word)*/ +/* +* DDR4 Control Word 8 (Input/Output Configuration Control Word) / DDR3 Con + * trol Word 8 (Additional Input Bus Termination Setting Control Word) +*/ #undef DDR_PHY_RDIMMCR1_RC8_DEFVAL #undef DDR_PHY_RDIMMCR1_RC8_SHIFT #undef DDR_PHY_RDIMMCR1_RC8_MASK -#define DDR_PHY_RDIMMCR1_RC8_DEFVAL 0x00000000 -#define DDR_PHY_RDIMMCR1_RC8_SHIFT 0 -#define DDR_PHY_RDIMMCR1_RC8_MASK 0x0000000FU +#define DDR_PHY_RDIMMCR1_RC8_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR1_RC8_SHIFT 0 +#define DDR_PHY_RDIMMCR1_RC8_MASK 0x0000000FU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_MR0_RESERVED_31_8_DEFVAL #undef DDR_PHY_MR0_RESERVED_31_8_SHIFT #undef DDR_PHY_MR0_RESERVED_31_8_MASK -#define DDR_PHY_MR0_RESERVED_31_8_DEFVAL 0x00000052 -#define DDR_PHY_MR0_RESERVED_31_8_SHIFT 8 -#define DDR_PHY_MR0_RESERVED_31_8_MASK 0xFFFFFF00U +#define DDR_PHY_MR0_RESERVED_31_8_DEFVAL 0x00000052 +#define DDR_PHY_MR0_RESERVED_31_8_SHIFT 8 +#define DDR_PHY_MR0_RESERVED_31_8_MASK 0xFFFFFF00U -/*CA Terminating Rank*/ +/* +* CA Terminating Rank +*/ #undef DDR_PHY_MR0_CATR_DEFVAL #undef DDR_PHY_MR0_CATR_SHIFT #undef DDR_PHY_MR0_CATR_MASK -#define DDR_PHY_MR0_CATR_DEFVAL 0x00000052 -#define DDR_PHY_MR0_CATR_SHIFT 7 -#define DDR_PHY_MR0_CATR_MASK 0x00000080U +#define DDR_PHY_MR0_CATR_DEFVAL 0x00000052 +#define DDR_PHY_MR0_CATR_SHIFT 7 +#define DDR_PHY_MR0_CATR_MASK 0x00000080U -/*Reserved. These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/ +/* +* Reserved. These are JEDEC reserved bits and are recommended by JEDEC to + * be programmed to 0x0. +*/ #undef DDR_PHY_MR0_RSVD_6_5_DEFVAL #undef DDR_PHY_MR0_RSVD_6_5_SHIFT #undef DDR_PHY_MR0_RSVD_6_5_MASK -#define DDR_PHY_MR0_RSVD_6_5_DEFVAL 0x00000052 -#define DDR_PHY_MR0_RSVD_6_5_SHIFT 5 -#define DDR_PHY_MR0_RSVD_6_5_MASK 0x00000060U +#define DDR_PHY_MR0_RSVD_6_5_DEFVAL 0x00000052 +#define DDR_PHY_MR0_RSVD_6_5_SHIFT 5 +#define DDR_PHY_MR0_RSVD_6_5_MASK 0x00000060U -/*Built-in Self-Test for RZQ*/ +/* +* Built-in Self-Test for RZQ +*/ #undef DDR_PHY_MR0_RZQI_DEFVAL #undef DDR_PHY_MR0_RZQI_SHIFT #undef DDR_PHY_MR0_RZQI_MASK -#define DDR_PHY_MR0_RZQI_DEFVAL 0x00000052 -#define DDR_PHY_MR0_RZQI_SHIFT 3 -#define DDR_PHY_MR0_RZQI_MASK 0x00000018U +#define DDR_PHY_MR0_RZQI_DEFVAL 0x00000052 +#define DDR_PHY_MR0_RZQI_SHIFT 3 +#define DDR_PHY_MR0_RZQI_MASK 0x00000018U -/*Reserved. These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/ +/* +* Reserved. These are JEDEC reserved bits and are recommended by JEDEC to + * be programmed to 0x0. +*/ #undef DDR_PHY_MR0_RSVD_2_0_DEFVAL #undef DDR_PHY_MR0_RSVD_2_0_SHIFT #undef DDR_PHY_MR0_RSVD_2_0_MASK -#define DDR_PHY_MR0_RSVD_2_0_DEFVAL 0x00000052 -#define DDR_PHY_MR0_RSVD_2_0_SHIFT 0 -#define DDR_PHY_MR0_RSVD_2_0_MASK 0x00000007U +#define DDR_PHY_MR0_RSVD_2_0_DEFVAL 0x00000052 +#define DDR_PHY_MR0_RSVD_2_0_SHIFT 0 +#define DDR_PHY_MR0_RSVD_2_0_MASK 0x00000007U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_MR1_RESERVED_31_8_DEFVAL #undef DDR_PHY_MR1_RESERVED_31_8_SHIFT #undef DDR_PHY_MR1_RESERVED_31_8_MASK -#define DDR_PHY_MR1_RESERVED_31_8_DEFVAL 0x00000004 -#define DDR_PHY_MR1_RESERVED_31_8_SHIFT 8 -#define DDR_PHY_MR1_RESERVED_31_8_MASK 0xFFFFFF00U +#define DDR_PHY_MR1_RESERVED_31_8_DEFVAL 0x00000004 +#define DDR_PHY_MR1_RESERVED_31_8_SHIFT 8 +#define DDR_PHY_MR1_RESERVED_31_8_MASK 0xFFFFFF00U -/*Read Postamble Length*/ +/* +* Read Postamble Length +*/ #undef DDR_PHY_MR1_RDPST_DEFVAL #undef DDR_PHY_MR1_RDPST_SHIFT #undef DDR_PHY_MR1_RDPST_MASK -#define DDR_PHY_MR1_RDPST_DEFVAL 0x00000004 -#define DDR_PHY_MR1_RDPST_SHIFT 7 -#define DDR_PHY_MR1_RDPST_MASK 0x00000080U +#define DDR_PHY_MR1_RDPST_DEFVAL 0x00000004 +#define DDR_PHY_MR1_RDPST_SHIFT 7 +#define DDR_PHY_MR1_RDPST_MASK 0x00000080U -/*Write-recovery for auto-precharge command*/ +/* +* Write-recovery for auto-precharge command +*/ #undef DDR_PHY_MR1_NWR_DEFVAL #undef DDR_PHY_MR1_NWR_SHIFT #undef DDR_PHY_MR1_NWR_MASK -#define DDR_PHY_MR1_NWR_DEFVAL 0x00000004 -#define DDR_PHY_MR1_NWR_SHIFT 4 -#define DDR_PHY_MR1_NWR_MASK 0x00000070U +#define DDR_PHY_MR1_NWR_DEFVAL 0x00000004 +#define DDR_PHY_MR1_NWR_SHIFT 4 +#define DDR_PHY_MR1_NWR_MASK 0x00000070U -/*Read Preamble Length*/ +/* +* Read Preamble Length +*/ #undef DDR_PHY_MR1_RDPRE_DEFVAL #undef DDR_PHY_MR1_RDPRE_SHIFT #undef DDR_PHY_MR1_RDPRE_MASK -#define DDR_PHY_MR1_RDPRE_DEFVAL 0x00000004 -#define DDR_PHY_MR1_RDPRE_SHIFT 3 -#define DDR_PHY_MR1_RDPRE_MASK 0x00000008U +#define DDR_PHY_MR1_RDPRE_DEFVAL 0x00000004 +#define DDR_PHY_MR1_RDPRE_SHIFT 3 +#define DDR_PHY_MR1_RDPRE_MASK 0x00000008U -/*Write Preamble Length*/ +/* +* Write Preamble Length +*/ #undef DDR_PHY_MR1_WRPRE_DEFVAL #undef DDR_PHY_MR1_WRPRE_SHIFT #undef DDR_PHY_MR1_WRPRE_MASK -#define DDR_PHY_MR1_WRPRE_DEFVAL 0x00000004 -#define DDR_PHY_MR1_WRPRE_SHIFT 2 -#define DDR_PHY_MR1_WRPRE_MASK 0x00000004U +#define DDR_PHY_MR1_WRPRE_DEFVAL 0x00000004 +#define DDR_PHY_MR1_WRPRE_SHIFT 2 +#define DDR_PHY_MR1_WRPRE_MASK 0x00000004U -/*Burst Length*/ +/* +* Burst Length +*/ #undef DDR_PHY_MR1_BL_DEFVAL #undef DDR_PHY_MR1_BL_SHIFT #undef DDR_PHY_MR1_BL_MASK -#define DDR_PHY_MR1_BL_DEFVAL 0x00000004 -#define DDR_PHY_MR1_BL_SHIFT 0 -#define DDR_PHY_MR1_BL_MASK 0x00000003U +#define DDR_PHY_MR1_BL_DEFVAL 0x00000004 +#define DDR_PHY_MR1_BL_SHIFT 0 +#define DDR_PHY_MR1_BL_MASK 0x00000003U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_MR2_RESERVED_31_8_DEFVAL #undef DDR_PHY_MR2_RESERVED_31_8_SHIFT #undef DDR_PHY_MR2_RESERVED_31_8_MASK -#define DDR_PHY_MR2_RESERVED_31_8_DEFVAL 0x00000000 -#define DDR_PHY_MR2_RESERVED_31_8_SHIFT 8 -#define DDR_PHY_MR2_RESERVED_31_8_MASK 0xFFFFFF00U +#define DDR_PHY_MR2_RESERVED_31_8_DEFVAL 0x00000000 +#define DDR_PHY_MR2_RESERVED_31_8_SHIFT 8 +#define DDR_PHY_MR2_RESERVED_31_8_MASK 0xFFFFFF00U -/*Write Leveling*/ +/* +* Write Leveling +*/ #undef DDR_PHY_MR2_WRL_DEFVAL #undef DDR_PHY_MR2_WRL_SHIFT #undef DDR_PHY_MR2_WRL_MASK -#define DDR_PHY_MR2_WRL_DEFVAL 0x00000000 -#define DDR_PHY_MR2_WRL_SHIFT 7 -#define DDR_PHY_MR2_WRL_MASK 0x00000080U +#define DDR_PHY_MR2_WRL_DEFVAL 0x00000000 +#define DDR_PHY_MR2_WRL_SHIFT 7 +#define DDR_PHY_MR2_WRL_MASK 0x00000080U -/*Write Latency Set*/ +/* +* Write Latency Set +*/ #undef DDR_PHY_MR2_WLS_DEFVAL #undef DDR_PHY_MR2_WLS_SHIFT #undef DDR_PHY_MR2_WLS_MASK -#define DDR_PHY_MR2_WLS_DEFVAL 0x00000000 -#define DDR_PHY_MR2_WLS_SHIFT 6 -#define DDR_PHY_MR2_WLS_MASK 0x00000040U +#define DDR_PHY_MR2_WLS_DEFVAL 0x00000000 +#define DDR_PHY_MR2_WLS_SHIFT 6 +#define DDR_PHY_MR2_WLS_MASK 0x00000040U -/*Write Latency*/ +/* +* Write Latency +*/ #undef DDR_PHY_MR2_WL_DEFVAL #undef DDR_PHY_MR2_WL_SHIFT #undef DDR_PHY_MR2_WL_MASK -#define DDR_PHY_MR2_WL_DEFVAL 0x00000000 -#define DDR_PHY_MR2_WL_SHIFT 3 -#define DDR_PHY_MR2_WL_MASK 0x00000038U +#define DDR_PHY_MR2_WL_DEFVAL 0x00000000 +#define DDR_PHY_MR2_WL_SHIFT 3 +#define DDR_PHY_MR2_WL_MASK 0x00000038U -/*Read Latency*/ +/* +* Read Latency +*/ #undef DDR_PHY_MR2_RL_DEFVAL #undef DDR_PHY_MR2_RL_SHIFT #undef DDR_PHY_MR2_RL_MASK -#define DDR_PHY_MR2_RL_DEFVAL 0x00000000 -#define DDR_PHY_MR2_RL_SHIFT 0 -#define DDR_PHY_MR2_RL_MASK 0x00000007U +#define DDR_PHY_MR2_RL_DEFVAL 0x00000000 +#define DDR_PHY_MR2_RL_SHIFT 0 +#define DDR_PHY_MR2_RL_MASK 0x00000007U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_MR3_RESERVED_31_8_DEFVAL #undef DDR_PHY_MR3_RESERVED_31_8_SHIFT #undef DDR_PHY_MR3_RESERVED_31_8_MASK -#define DDR_PHY_MR3_RESERVED_31_8_DEFVAL 0x00000031 -#define DDR_PHY_MR3_RESERVED_31_8_SHIFT 8 -#define DDR_PHY_MR3_RESERVED_31_8_MASK 0xFFFFFF00U +#define DDR_PHY_MR3_RESERVED_31_8_DEFVAL 0x00000031 +#define DDR_PHY_MR3_RESERVED_31_8_SHIFT 8 +#define DDR_PHY_MR3_RESERVED_31_8_MASK 0xFFFFFF00U -/*DBI-Write Enable*/ +/* +* DBI-Write Enable +*/ #undef DDR_PHY_MR3_DBIWR_DEFVAL #undef DDR_PHY_MR3_DBIWR_SHIFT #undef DDR_PHY_MR3_DBIWR_MASK -#define DDR_PHY_MR3_DBIWR_DEFVAL 0x00000031 -#define DDR_PHY_MR3_DBIWR_SHIFT 7 -#define DDR_PHY_MR3_DBIWR_MASK 0x00000080U +#define DDR_PHY_MR3_DBIWR_DEFVAL 0x00000031 +#define DDR_PHY_MR3_DBIWR_SHIFT 7 +#define DDR_PHY_MR3_DBIWR_MASK 0x00000080U -/*DBI-Read Enable*/ +/* +* DBI-Read Enable +*/ #undef DDR_PHY_MR3_DBIRD_DEFVAL #undef DDR_PHY_MR3_DBIRD_SHIFT #undef DDR_PHY_MR3_DBIRD_MASK -#define DDR_PHY_MR3_DBIRD_DEFVAL 0x00000031 -#define DDR_PHY_MR3_DBIRD_SHIFT 6 -#define DDR_PHY_MR3_DBIRD_MASK 0x00000040U +#define DDR_PHY_MR3_DBIRD_DEFVAL 0x00000031 +#define DDR_PHY_MR3_DBIRD_SHIFT 6 +#define DDR_PHY_MR3_DBIRD_MASK 0x00000040U -/*Pull-down Drive Strength*/ +/* +* Pull-down Drive Strength +*/ #undef DDR_PHY_MR3_PDDS_DEFVAL #undef DDR_PHY_MR3_PDDS_SHIFT #undef DDR_PHY_MR3_PDDS_MASK -#define DDR_PHY_MR3_PDDS_DEFVAL 0x00000031 -#define DDR_PHY_MR3_PDDS_SHIFT 3 -#define DDR_PHY_MR3_PDDS_MASK 0x00000038U +#define DDR_PHY_MR3_PDDS_DEFVAL 0x00000031 +#define DDR_PHY_MR3_PDDS_SHIFT 3 +#define DDR_PHY_MR3_PDDS_MASK 0x00000038U -/*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/ +/* +* These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. +*/ #undef DDR_PHY_MR3_RSVD_DEFVAL #undef DDR_PHY_MR3_RSVD_SHIFT #undef DDR_PHY_MR3_RSVD_MASK -#define DDR_PHY_MR3_RSVD_DEFVAL 0x00000031 -#define DDR_PHY_MR3_RSVD_SHIFT 2 -#define DDR_PHY_MR3_RSVD_MASK 0x00000004U +#define DDR_PHY_MR3_RSVD_DEFVAL 0x00000031 +#define DDR_PHY_MR3_RSVD_SHIFT 2 +#define DDR_PHY_MR3_RSVD_MASK 0x00000004U -/*Write Postamble Length*/ +/* +* Write Postamble Length +*/ #undef DDR_PHY_MR3_WRPST_DEFVAL #undef DDR_PHY_MR3_WRPST_SHIFT #undef DDR_PHY_MR3_WRPST_MASK -#define DDR_PHY_MR3_WRPST_DEFVAL 0x00000031 -#define DDR_PHY_MR3_WRPST_SHIFT 1 -#define DDR_PHY_MR3_WRPST_MASK 0x00000002U +#define DDR_PHY_MR3_WRPST_DEFVAL 0x00000031 +#define DDR_PHY_MR3_WRPST_SHIFT 1 +#define DDR_PHY_MR3_WRPST_MASK 0x00000002U -/*Pull-up Calibration Point*/ +/* +* Pull-up Calibration Point +*/ #undef DDR_PHY_MR3_PUCAL_DEFVAL #undef DDR_PHY_MR3_PUCAL_SHIFT #undef DDR_PHY_MR3_PUCAL_MASK -#define DDR_PHY_MR3_PUCAL_DEFVAL 0x00000031 -#define DDR_PHY_MR3_PUCAL_SHIFT 0 -#define DDR_PHY_MR3_PUCAL_MASK 0x00000001U +#define DDR_PHY_MR3_PUCAL_DEFVAL 0x00000031 +#define DDR_PHY_MR3_PUCAL_SHIFT 0 +#define DDR_PHY_MR3_PUCAL_MASK 0x00000001U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_MR4_RESERVED_31_16_DEFVAL #undef DDR_PHY_MR4_RESERVED_31_16_SHIFT #undef DDR_PHY_MR4_RESERVED_31_16_MASK -#define DDR_PHY_MR4_RESERVED_31_16_DEFVAL 0x00000000 -#define DDR_PHY_MR4_RESERVED_31_16_SHIFT 16 -#define DDR_PHY_MR4_RESERVED_31_16_MASK 0xFFFF0000U +#define DDR_PHY_MR4_RESERVED_31_16_DEFVAL 0x00000000 +#define DDR_PHY_MR4_RESERVED_31_16_SHIFT 16 +#define DDR_PHY_MR4_RESERVED_31_16_MASK 0xFFFF0000U -/*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/ +/* +* These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. +*/ #undef DDR_PHY_MR4_RSVD_15_13_DEFVAL #undef DDR_PHY_MR4_RSVD_15_13_SHIFT #undef DDR_PHY_MR4_RSVD_15_13_MASK -#define DDR_PHY_MR4_RSVD_15_13_DEFVAL 0x00000000 -#define DDR_PHY_MR4_RSVD_15_13_SHIFT 13 -#define DDR_PHY_MR4_RSVD_15_13_MASK 0x0000E000U +#define DDR_PHY_MR4_RSVD_15_13_DEFVAL 0x00000000 +#define DDR_PHY_MR4_RSVD_15_13_SHIFT 13 +#define DDR_PHY_MR4_RSVD_15_13_MASK 0x0000E000U -/*Write Preamble*/ +/* +* Write Preamble +*/ #undef DDR_PHY_MR4_WRP_DEFVAL #undef DDR_PHY_MR4_WRP_SHIFT #undef DDR_PHY_MR4_WRP_MASK -#define DDR_PHY_MR4_WRP_DEFVAL 0x00000000 -#define DDR_PHY_MR4_WRP_SHIFT 12 -#define DDR_PHY_MR4_WRP_MASK 0x00001000U +#define DDR_PHY_MR4_WRP_DEFVAL 0x00000000 +#define DDR_PHY_MR4_WRP_SHIFT 12 +#define DDR_PHY_MR4_WRP_MASK 0x00001000U -/*Read Preamble*/ +/* +* Read Preamble +*/ #undef DDR_PHY_MR4_RDP_DEFVAL #undef DDR_PHY_MR4_RDP_SHIFT #undef DDR_PHY_MR4_RDP_MASK -#define DDR_PHY_MR4_RDP_DEFVAL 0x00000000 -#define DDR_PHY_MR4_RDP_SHIFT 11 -#define DDR_PHY_MR4_RDP_MASK 0x00000800U +#define DDR_PHY_MR4_RDP_DEFVAL 0x00000000 +#define DDR_PHY_MR4_RDP_SHIFT 11 +#define DDR_PHY_MR4_RDP_MASK 0x00000800U -/*Read Preamble Training Mode*/ +/* +* Read Preamble Training Mode +*/ #undef DDR_PHY_MR4_RPTM_DEFVAL #undef DDR_PHY_MR4_RPTM_SHIFT #undef DDR_PHY_MR4_RPTM_MASK -#define DDR_PHY_MR4_RPTM_DEFVAL 0x00000000 -#define DDR_PHY_MR4_RPTM_SHIFT 10 -#define DDR_PHY_MR4_RPTM_MASK 0x00000400U +#define DDR_PHY_MR4_RPTM_DEFVAL 0x00000000 +#define DDR_PHY_MR4_RPTM_SHIFT 10 +#define DDR_PHY_MR4_RPTM_MASK 0x00000400U -/*Self Refresh Abort*/ +/* +* Self Refresh Abort +*/ #undef DDR_PHY_MR4_SRA_DEFVAL #undef DDR_PHY_MR4_SRA_SHIFT #undef DDR_PHY_MR4_SRA_MASK -#define DDR_PHY_MR4_SRA_DEFVAL 0x00000000 -#define DDR_PHY_MR4_SRA_SHIFT 9 -#define DDR_PHY_MR4_SRA_MASK 0x00000200U +#define DDR_PHY_MR4_SRA_DEFVAL 0x00000000 +#define DDR_PHY_MR4_SRA_SHIFT 9 +#define DDR_PHY_MR4_SRA_MASK 0x00000200U -/*CS to Command Latency Mode*/ +/* +* CS to Command Latency Mode +*/ #undef DDR_PHY_MR4_CS2CMDL_DEFVAL #undef DDR_PHY_MR4_CS2CMDL_SHIFT #undef DDR_PHY_MR4_CS2CMDL_MASK -#define DDR_PHY_MR4_CS2CMDL_DEFVAL 0x00000000 -#define DDR_PHY_MR4_CS2CMDL_SHIFT 6 -#define DDR_PHY_MR4_CS2CMDL_MASK 0x000001C0U +#define DDR_PHY_MR4_CS2CMDL_DEFVAL 0x00000000 +#define DDR_PHY_MR4_CS2CMDL_SHIFT 6 +#define DDR_PHY_MR4_CS2CMDL_MASK 0x000001C0U -/*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/ +/* +* These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. +*/ #undef DDR_PHY_MR4_RSVD1_DEFVAL #undef DDR_PHY_MR4_RSVD1_SHIFT #undef DDR_PHY_MR4_RSVD1_MASK -#define DDR_PHY_MR4_RSVD1_DEFVAL 0x00000000 -#define DDR_PHY_MR4_RSVD1_SHIFT 5 -#define DDR_PHY_MR4_RSVD1_MASK 0x00000020U +#define DDR_PHY_MR4_RSVD1_DEFVAL 0x00000000 +#define DDR_PHY_MR4_RSVD1_SHIFT 5 +#define DDR_PHY_MR4_RSVD1_MASK 0x00000020U -/*Internal VREF Monitor*/ +/* +* Internal VREF Monitor +*/ #undef DDR_PHY_MR4_IVM_DEFVAL #undef DDR_PHY_MR4_IVM_SHIFT #undef DDR_PHY_MR4_IVM_MASK -#define DDR_PHY_MR4_IVM_DEFVAL 0x00000000 -#define DDR_PHY_MR4_IVM_SHIFT 4 -#define DDR_PHY_MR4_IVM_MASK 0x00000010U +#define DDR_PHY_MR4_IVM_DEFVAL 0x00000000 +#define DDR_PHY_MR4_IVM_SHIFT 4 +#define DDR_PHY_MR4_IVM_MASK 0x00000010U -/*Temperature Controlled Refresh Mode*/ +/* +* Temperature Controlled Refresh Mode +*/ #undef DDR_PHY_MR4_TCRM_DEFVAL #undef DDR_PHY_MR4_TCRM_SHIFT #undef DDR_PHY_MR4_TCRM_MASK -#define DDR_PHY_MR4_TCRM_DEFVAL 0x00000000 -#define DDR_PHY_MR4_TCRM_SHIFT 3 -#define DDR_PHY_MR4_TCRM_MASK 0x00000008U +#define DDR_PHY_MR4_TCRM_DEFVAL 0x00000000 +#define DDR_PHY_MR4_TCRM_SHIFT 3 +#define DDR_PHY_MR4_TCRM_MASK 0x00000008U -/*Temperature Controlled Refresh Range*/ +/* +* Temperature Controlled Refresh Range +*/ #undef DDR_PHY_MR4_TCRR_DEFVAL #undef DDR_PHY_MR4_TCRR_SHIFT #undef DDR_PHY_MR4_TCRR_MASK -#define DDR_PHY_MR4_TCRR_DEFVAL 0x00000000 -#define DDR_PHY_MR4_TCRR_SHIFT 2 -#define DDR_PHY_MR4_TCRR_MASK 0x00000004U +#define DDR_PHY_MR4_TCRR_DEFVAL 0x00000000 +#define DDR_PHY_MR4_TCRR_SHIFT 2 +#define DDR_PHY_MR4_TCRR_MASK 0x00000004U -/*Maximum Power Down Mode*/ +/* +* Maximum Power Down Mode +*/ #undef DDR_PHY_MR4_MPDM_DEFVAL #undef DDR_PHY_MR4_MPDM_SHIFT #undef DDR_PHY_MR4_MPDM_MASK -#define DDR_PHY_MR4_MPDM_DEFVAL 0x00000000 -#define DDR_PHY_MR4_MPDM_SHIFT 1 -#define DDR_PHY_MR4_MPDM_MASK 0x00000002U +#define DDR_PHY_MR4_MPDM_DEFVAL 0x00000000 +#define DDR_PHY_MR4_MPDM_SHIFT 1 +#define DDR_PHY_MR4_MPDM_MASK 0x00000002U -/*This is a JEDEC reserved bit and is recommended by JEDEC to be programmed to 0x0.*/ +/* +* This is a JEDEC reserved bit and is recommended by JEDEC to be programme + * d to 0x0. +*/ #undef DDR_PHY_MR4_RSVD_0_DEFVAL #undef DDR_PHY_MR4_RSVD_0_SHIFT #undef DDR_PHY_MR4_RSVD_0_MASK -#define DDR_PHY_MR4_RSVD_0_DEFVAL 0x00000000 -#define DDR_PHY_MR4_RSVD_0_SHIFT 0 -#define DDR_PHY_MR4_RSVD_0_MASK 0x00000001U +#define DDR_PHY_MR4_RSVD_0_DEFVAL 0x00000000 +#define DDR_PHY_MR4_RSVD_0_SHIFT 0 +#define DDR_PHY_MR4_RSVD_0_MASK 0x00000001U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_MR5_RESERVED_31_16_DEFVAL #undef DDR_PHY_MR5_RESERVED_31_16_SHIFT #undef DDR_PHY_MR5_RESERVED_31_16_MASK -#define DDR_PHY_MR5_RESERVED_31_16_DEFVAL 0x00000000 -#define DDR_PHY_MR5_RESERVED_31_16_SHIFT 16 -#define DDR_PHY_MR5_RESERVED_31_16_MASK 0xFFFF0000U +#define DDR_PHY_MR5_RESERVED_31_16_DEFVAL 0x00000000 +#define DDR_PHY_MR5_RESERVED_31_16_SHIFT 16 +#define DDR_PHY_MR5_RESERVED_31_16_MASK 0xFFFF0000U -/*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/ +/* +* These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. +*/ #undef DDR_PHY_MR5_RSVD_DEFVAL #undef DDR_PHY_MR5_RSVD_SHIFT #undef DDR_PHY_MR5_RSVD_MASK -#define DDR_PHY_MR5_RSVD_DEFVAL 0x00000000 -#define DDR_PHY_MR5_RSVD_SHIFT 13 -#define DDR_PHY_MR5_RSVD_MASK 0x0000E000U +#define DDR_PHY_MR5_RSVD_DEFVAL 0x00000000 +#define DDR_PHY_MR5_RSVD_SHIFT 13 +#define DDR_PHY_MR5_RSVD_MASK 0x0000E000U -/*Read DBI*/ +/* +* Read DBI +*/ #undef DDR_PHY_MR5_RDBI_DEFVAL #undef DDR_PHY_MR5_RDBI_SHIFT #undef DDR_PHY_MR5_RDBI_MASK -#define DDR_PHY_MR5_RDBI_DEFVAL 0x00000000 -#define DDR_PHY_MR5_RDBI_SHIFT 12 -#define DDR_PHY_MR5_RDBI_MASK 0x00001000U +#define DDR_PHY_MR5_RDBI_DEFVAL 0x00000000 +#define DDR_PHY_MR5_RDBI_SHIFT 12 +#define DDR_PHY_MR5_RDBI_MASK 0x00001000U -/*Write DBI*/ +/* +* Write DBI +*/ #undef DDR_PHY_MR5_WDBI_DEFVAL #undef DDR_PHY_MR5_WDBI_SHIFT #undef DDR_PHY_MR5_WDBI_MASK -#define DDR_PHY_MR5_WDBI_DEFVAL 0x00000000 -#define DDR_PHY_MR5_WDBI_SHIFT 11 -#define DDR_PHY_MR5_WDBI_MASK 0x00000800U +#define DDR_PHY_MR5_WDBI_DEFVAL 0x00000000 +#define DDR_PHY_MR5_WDBI_SHIFT 11 +#define DDR_PHY_MR5_WDBI_MASK 0x00000800U -/*Data Mask*/ +/* +* Data Mask +*/ #undef DDR_PHY_MR5_DM_DEFVAL #undef DDR_PHY_MR5_DM_SHIFT #undef DDR_PHY_MR5_DM_MASK -#define DDR_PHY_MR5_DM_DEFVAL 0x00000000 -#define DDR_PHY_MR5_DM_SHIFT 10 -#define DDR_PHY_MR5_DM_MASK 0x00000400U +#define DDR_PHY_MR5_DM_DEFVAL 0x00000000 +#define DDR_PHY_MR5_DM_SHIFT 10 +#define DDR_PHY_MR5_DM_MASK 0x00000400U -/*CA Parity Persistent Error*/ +/* +* CA Parity Persistent Error +*/ #undef DDR_PHY_MR5_CAPPE_DEFVAL #undef DDR_PHY_MR5_CAPPE_SHIFT #undef DDR_PHY_MR5_CAPPE_MASK -#define DDR_PHY_MR5_CAPPE_DEFVAL 0x00000000 -#define DDR_PHY_MR5_CAPPE_SHIFT 9 -#define DDR_PHY_MR5_CAPPE_MASK 0x00000200U +#define DDR_PHY_MR5_CAPPE_DEFVAL 0x00000000 +#define DDR_PHY_MR5_CAPPE_SHIFT 9 +#define DDR_PHY_MR5_CAPPE_MASK 0x00000200U -/*RTT_PARK*/ +/* +* RTT_PARK +*/ #undef DDR_PHY_MR5_RTTPARK_DEFVAL #undef DDR_PHY_MR5_RTTPARK_SHIFT #undef DDR_PHY_MR5_RTTPARK_MASK -#define DDR_PHY_MR5_RTTPARK_DEFVAL 0x00000000 -#define DDR_PHY_MR5_RTTPARK_SHIFT 6 -#define DDR_PHY_MR5_RTTPARK_MASK 0x000001C0U +#define DDR_PHY_MR5_RTTPARK_DEFVAL 0x00000000 +#define DDR_PHY_MR5_RTTPARK_SHIFT 6 +#define DDR_PHY_MR5_RTTPARK_MASK 0x000001C0U -/*ODT Input Buffer during Power Down mode*/ +/* +* ODT Input Buffer during Power Down mode +*/ #undef DDR_PHY_MR5_ODTIBPD_DEFVAL #undef DDR_PHY_MR5_ODTIBPD_SHIFT #undef DDR_PHY_MR5_ODTIBPD_MASK -#define DDR_PHY_MR5_ODTIBPD_DEFVAL 0x00000000 -#define DDR_PHY_MR5_ODTIBPD_SHIFT 5 -#define DDR_PHY_MR5_ODTIBPD_MASK 0x00000020U +#define DDR_PHY_MR5_ODTIBPD_DEFVAL 0x00000000 +#define DDR_PHY_MR5_ODTIBPD_SHIFT 5 +#define DDR_PHY_MR5_ODTIBPD_MASK 0x00000020U -/*C/A Parity Error Status*/ +/* +* C/A Parity Error Status +*/ #undef DDR_PHY_MR5_CAPES_DEFVAL #undef DDR_PHY_MR5_CAPES_SHIFT #undef DDR_PHY_MR5_CAPES_MASK -#define DDR_PHY_MR5_CAPES_DEFVAL 0x00000000 -#define DDR_PHY_MR5_CAPES_SHIFT 4 -#define DDR_PHY_MR5_CAPES_MASK 0x00000010U +#define DDR_PHY_MR5_CAPES_DEFVAL 0x00000000 +#define DDR_PHY_MR5_CAPES_SHIFT 4 +#define DDR_PHY_MR5_CAPES_MASK 0x00000010U -/*CRC Error Clear*/ +/* +* CRC Error Clear +*/ #undef DDR_PHY_MR5_CRCEC_DEFVAL #undef DDR_PHY_MR5_CRCEC_SHIFT #undef DDR_PHY_MR5_CRCEC_MASK -#define DDR_PHY_MR5_CRCEC_DEFVAL 0x00000000 -#define DDR_PHY_MR5_CRCEC_SHIFT 3 -#define DDR_PHY_MR5_CRCEC_MASK 0x00000008U +#define DDR_PHY_MR5_CRCEC_DEFVAL 0x00000000 +#define DDR_PHY_MR5_CRCEC_SHIFT 3 +#define DDR_PHY_MR5_CRCEC_MASK 0x00000008U -/*C/A Parity Latency Mode*/ +/* +* C/A Parity Latency Mode +*/ #undef DDR_PHY_MR5_CAPM_DEFVAL #undef DDR_PHY_MR5_CAPM_SHIFT #undef DDR_PHY_MR5_CAPM_MASK -#define DDR_PHY_MR5_CAPM_DEFVAL 0x00000000 -#define DDR_PHY_MR5_CAPM_SHIFT 0 -#define DDR_PHY_MR5_CAPM_MASK 0x00000007U +#define DDR_PHY_MR5_CAPM_DEFVAL 0x00000000 +#define DDR_PHY_MR5_CAPM_SHIFT 0 +#define DDR_PHY_MR5_CAPM_MASK 0x00000007U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_MR6_RESERVED_31_16_DEFVAL #undef DDR_PHY_MR6_RESERVED_31_16_SHIFT #undef DDR_PHY_MR6_RESERVED_31_16_MASK -#define DDR_PHY_MR6_RESERVED_31_16_DEFVAL 0x00000000 -#define DDR_PHY_MR6_RESERVED_31_16_SHIFT 16 -#define DDR_PHY_MR6_RESERVED_31_16_MASK 0xFFFF0000U +#define DDR_PHY_MR6_RESERVED_31_16_DEFVAL 0x00000000 +#define DDR_PHY_MR6_RESERVED_31_16_SHIFT 16 +#define DDR_PHY_MR6_RESERVED_31_16_MASK 0xFFFF0000U -/*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/ +/* +* These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. +*/ #undef DDR_PHY_MR6_RSVD_15_13_DEFVAL #undef DDR_PHY_MR6_RSVD_15_13_SHIFT #undef DDR_PHY_MR6_RSVD_15_13_MASK -#define DDR_PHY_MR6_RSVD_15_13_DEFVAL 0x00000000 -#define DDR_PHY_MR6_RSVD_15_13_SHIFT 13 -#define DDR_PHY_MR6_RSVD_15_13_MASK 0x0000E000U +#define DDR_PHY_MR6_RSVD_15_13_DEFVAL 0x00000000 +#define DDR_PHY_MR6_RSVD_15_13_SHIFT 13 +#define DDR_PHY_MR6_RSVD_15_13_MASK 0x0000E000U -/*CAS_n to CAS_n command delay for same bank group (tCCD_L)*/ +/* +* CAS_n to CAS_n command delay for same bank group (tCCD_L) +*/ #undef DDR_PHY_MR6_TCCDL_DEFVAL #undef DDR_PHY_MR6_TCCDL_SHIFT #undef DDR_PHY_MR6_TCCDL_MASK -#define DDR_PHY_MR6_TCCDL_DEFVAL 0x00000000 -#define DDR_PHY_MR6_TCCDL_SHIFT 10 -#define DDR_PHY_MR6_TCCDL_MASK 0x00001C00U +#define DDR_PHY_MR6_TCCDL_DEFVAL 0x00000000 +#define DDR_PHY_MR6_TCCDL_SHIFT 10 +#define DDR_PHY_MR6_TCCDL_MASK 0x00001C00U -/*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/ +/* +* These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. +*/ #undef DDR_PHY_MR6_RSVD_9_8_DEFVAL #undef DDR_PHY_MR6_RSVD_9_8_SHIFT #undef DDR_PHY_MR6_RSVD_9_8_MASK -#define DDR_PHY_MR6_RSVD_9_8_DEFVAL 0x00000000 -#define DDR_PHY_MR6_RSVD_9_8_SHIFT 8 -#define DDR_PHY_MR6_RSVD_9_8_MASK 0x00000300U +#define DDR_PHY_MR6_RSVD_9_8_DEFVAL 0x00000000 +#define DDR_PHY_MR6_RSVD_9_8_SHIFT 8 +#define DDR_PHY_MR6_RSVD_9_8_MASK 0x00000300U -/*VrefDQ Training Enable*/ +/* +* VrefDQ Training Enable +*/ #undef DDR_PHY_MR6_VDDQTEN_DEFVAL #undef DDR_PHY_MR6_VDDQTEN_SHIFT #undef DDR_PHY_MR6_VDDQTEN_MASK -#define DDR_PHY_MR6_VDDQTEN_DEFVAL 0x00000000 -#define DDR_PHY_MR6_VDDQTEN_SHIFT 7 -#define DDR_PHY_MR6_VDDQTEN_MASK 0x00000080U +#define DDR_PHY_MR6_VDDQTEN_DEFVAL 0x00000000 +#define DDR_PHY_MR6_VDDQTEN_SHIFT 7 +#define DDR_PHY_MR6_VDDQTEN_MASK 0x00000080U -/*VrefDQ Training Range*/ +/* +* VrefDQ Training Range +*/ #undef DDR_PHY_MR6_VDQTRG_DEFVAL #undef DDR_PHY_MR6_VDQTRG_SHIFT #undef DDR_PHY_MR6_VDQTRG_MASK -#define DDR_PHY_MR6_VDQTRG_DEFVAL 0x00000000 -#define DDR_PHY_MR6_VDQTRG_SHIFT 6 -#define DDR_PHY_MR6_VDQTRG_MASK 0x00000040U +#define DDR_PHY_MR6_VDQTRG_DEFVAL 0x00000000 +#define DDR_PHY_MR6_VDQTRG_SHIFT 6 +#define DDR_PHY_MR6_VDQTRG_MASK 0x00000040U -/*VrefDQ Training Values*/ +/* +* VrefDQ Training Values +*/ #undef DDR_PHY_MR6_VDQTVAL_DEFVAL #undef DDR_PHY_MR6_VDQTVAL_SHIFT #undef DDR_PHY_MR6_VDQTVAL_MASK -#define DDR_PHY_MR6_VDQTVAL_DEFVAL 0x00000000 -#define DDR_PHY_MR6_VDQTVAL_SHIFT 0 -#define DDR_PHY_MR6_VDQTVAL_MASK 0x0000003FU +#define DDR_PHY_MR6_VDQTVAL_DEFVAL 0x00000000 +#define DDR_PHY_MR6_VDQTVAL_SHIFT 0 +#define DDR_PHY_MR6_VDQTVAL_MASK 0x0000003FU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_MR11_RESERVED_31_8_DEFVAL #undef DDR_PHY_MR11_RESERVED_31_8_SHIFT #undef DDR_PHY_MR11_RESERVED_31_8_MASK -#define DDR_PHY_MR11_RESERVED_31_8_DEFVAL 0x00000000 -#define DDR_PHY_MR11_RESERVED_31_8_SHIFT 8 -#define DDR_PHY_MR11_RESERVED_31_8_MASK 0xFFFFFF00U +#define DDR_PHY_MR11_RESERVED_31_8_DEFVAL 0x00000000 +#define DDR_PHY_MR11_RESERVED_31_8_SHIFT 8 +#define DDR_PHY_MR11_RESERVED_31_8_MASK 0xFFFFFF00U -/*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/ +/* +* These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. +*/ #undef DDR_PHY_MR11_RSVD_DEFVAL #undef DDR_PHY_MR11_RSVD_SHIFT #undef DDR_PHY_MR11_RSVD_MASK -#define DDR_PHY_MR11_RSVD_DEFVAL 0x00000000 -#define DDR_PHY_MR11_RSVD_SHIFT 3 -#define DDR_PHY_MR11_RSVD_MASK 0x000000F8U +#define DDR_PHY_MR11_RSVD_DEFVAL 0x00000000 +#define DDR_PHY_MR11_RSVD_SHIFT 3 +#define DDR_PHY_MR11_RSVD_MASK 0x000000F8U -/*Power Down Control*/ +/* +* Power Down Control +*/ #undef DDR_PHY_MR11_PDCTL_DEFVAL #undef DDR_PHY_MR11_PDCTL_SHIFT #undef DDR_PHY_MR11_PDCTL_MASK -#define DDR_PHY_MR11_PDCTL_DEFVAL 0x00000000 -#define DDR_PHY_MR11_PDCTL_SHIFT 2 -#define DDR_PHY_MR11_PDCTL_MASK 0x00000004U +#define DDR_PHY_MR11_PDCTL_DEFVAL 0x00000000 +#define DDR_PHY_MR11_PDCTL_SHIFT 2 +#define DDR_PHY_MR11_PDCTL_MASK 0x00000004U -/*DQ Bus Receiver On-Die-Termination*/ +/* +* DQ Bus Receiver On-Die-Termination +*/ #undef DDR_PHY_MR11_DQODT_DEFVAL #undef DDR_PHY_MR11_DQODT_SHIFT #undef DDR_PHY_MR11_DQODT_MASK -#define DDR_PHY_MR11_DQODT_DEFVAL 0x00000000 -#define DDR_PHY_MR11_DQODT_SHIFT 0 -#define DDR_PHY_MR11_DQODT_MASK 0x00000003U +#define DDR_PHY_MR11_DQODT_DEFVAL 0x00000000 +#define DDR_PHY_MR11_DQODT_SHIFT 0 +#define DDR_PHY_MR11_DQODT_MASK 0x00000003U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_MR12_RESERVED_31_8_DEFVAL #undef DDR_PHY_MR12_RESERVED_31_8_SHIFT #undef DDR_PHY_MR12_RESERVED_31_8_MASK -#define DDR_PHY_MR12_RESERVED_31_8_DEFVAL 0x0000004D -#define DDR_PHY_MR12_RESERVED_31_8_SHIFT 8 -#define DDR_PHY_MR12_RESERVED_31_8_MASK 0xFFFFFF00U +#define DDR_PHY_MR12_RESERVED_31_8_DEFVAL 0x0000004D +#define DDR_PHY_MR12_RESERVED_31_8_SHIFT 8 +#define DDR_PHY_MR12_RESERVED_31_8_MASK 0xFFFFFF00U -/*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/ +/* +* These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. +*/ #undef DDR_PHY_MR12_RSVD_DEFVAL #undef DDR_PHY_MR12_RSVD_SHIFT #undef DDR_PHY_MR12_RSVD_MASK -#define DDR_PHY_MR12_RSVD_DEFVAL 0x0000004D -#define DDR_PHY_MR12_RSVD_SHIFT 7 -#define DDR_PHY_MR12_RSVD_MASK 0x00000080U +#define DDR_PHY_MR12_RSVD_DEFVAL 0x0000004D +#define DDR_PHY_MR12_RSVD_SHIFT 7 +#define DDR_PHY_MR12_RSVD_MASK 0x00000080U -/*VREF_CA Range Select.*/ +/* +* VREF_CA Range Select. +*/ #undef DDR_PHY_MR12_VR_CA_DEFVAL #undef DDR_PHY_MR12_VR_CA_SHIFT #undef DDR_PHY_MR12_VR_CA_MASK -#define DDR_PHY_MR12_VR_CA_DEFVAL 0x0000004D -#define DDR_PHY_MR12_VR_CA_SHIFT 6 -#define DDR_PHY_MR12_VR_CA_MASK 0x00000040U +#define DDR_PHY_MR12_VR_CA_DEFVAL 0x0000004D +#define DDR_PHY_MR12_VR_CA_SHIFT 6 +#define DDR_PHY_MR12_VR_CA_MASK 0x00000040U -/*Controls the VREF(ca) levels for Frequency-Set-Point[1:0].*/ +/* +* Controls the VREF(ca) levels for Frequency-Set-Point[1:0]. +*/ #undef DDR_PHY_MR12_VREF_CA_DEFVAL #undef DDR_PHY_MR12_VREF_CA_SHIFT #undef DDR_PHY_MR12_VREF_CA_MASK -#define DDR_PHY_MR12_VREF_CA_DEFVAL 0x0000004D -#define DDR_PHY_MR12_VREF_CA_SHIFT 0 -#define DDR_PHY_MR12_VREF_CA_MASK 0x0000003FU +#define DDR_PHY_MR12_VREF_CA_DEFVAL 0x0000004D +#define DDR_PHY_MR12_VREF_CA_SHIFT 0 +#define DDR_PHY_MR12_VREF_CA_MASK 0x0000003FU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_MR13_RESERVED_31_8_DEFVAL #undef DDR_PHY_MR13_RESERVED_31_8_SHIFT #undef DDR_PHY_MR13_RESERVED_31_8_MASK -#define DDR_PHY_MR13_RESERVED_31_8_DEFVAL 0x00000000 -#define DDR_PHY_MR13_RESERVED_31_8_SHIFT 8 -#define DDR_PHY_MR13_RESERVED_31_8_MASK 0xFFFFFF00U +#define DDR_PHY_MR13_RESERVED_31_8_DEFVAL 0x00000000 +#define DDR_PHY_MR13_RESERVED_31_8_SHIFT 8 +#define DDR_PHY_MR13_RESERVED_31_8_MASK 0xFFFFFF00U -/*Frequency Set Point Operation Mode*/ +/* +* Frequency Set Point Operation Mode +*/ #undef DDR_PHY_MR13_FSPOP_DEFVAL #undef DDR_PHY_MR13_FSPOP_SHIFT #undef DDR_PHY_MR13_FSPOP_MASK -#define DDR_PHY_MR13_FSPOP_DEFVAL 0x00000000 -#define DDR_PHY_MR13_FSPOP_SHIFT 7 -#define DDR_PHY_MR13_FSPOP_MASK 0x00000080U +#define DDR_PHY_MR13_FSPOP_DEFVAL 0x00000000 +#define DDR_PHY_MR13_FSPOP_SHIFT 7 +#define DDR_PHY_MR13_FSPOP_MASK 0x00000080U -/*Frequency Set Point Write Enable*/ +/* +* Frequency Set Point Write Enable +*/ #undef DDR_PHY_MR13_FSPWR_DEFVAL #undef DDR_PHY_MR13_FSPWR_SHIFT #undef DDR_PHY_MR13_FSPWR_MASK -#define DDR_PHY_MR13_FSPWR_DEFVAL 0x00000000 -#define DDR_PHY_MR13_FSPWR_SHIFT 6 -#define DDR_PHY_MR13_FSPWR_MASK 0x00000040U +#define DDR_PHY_MR13_FSPWR_DEFVAL 0x00000000 +#define DDR_PHY_MR13_FSPWR_SHIFT 6 +#define DDR_PHY_MR13_FSPWR_MASK 0x00000040U -/*Data Mask Enable*/ +/* +* Data Mask Enable +*/ #undef DDR_PHY_MR13_DMD_DEFVAL #undef DDR_PHY_MR13_DMD_SHIFT #undef DDR_PHY_MR13_DMD_MASK -#define DDR_PHY_MR13_DMD_DEFVAL 0x00000000 -#define DDR_PHY_MR13_DMD_SHIFT 5 -#define DDR_PHY_MR13_DMD_MASK 0x00000020U +#define DDR_PHY_MR13_DMD_DEFVAL 0x00000000 +#define DDR_PHY_MR13_DMD_SHIFT 5 +#define DDR_PHY_MR13_DMD_MASK 0x00000020U -/*Refresh Rate Option*/ +/* +* Refresh Rate Option +*/ #undef DDR_PHY_MR13_RRO_DEFVAL #undef DDR_PHY_MR13_RRO_SHIFT #undef DDR_PHY_MR13_RRO_MASK -#define DDR_PHY_MR13_RRO_DEFVAL 0x00000000 -#define DDR_PHY_MR13_RRO_SHIFT 4 -#define DDR_PHY_MR13_RRO_MASK 0x00000010U +#define DDR_PHY_MR13_RRO_DEFVAL 0x00000000 +#define DDR_PHY_MR13_RRO_SHIFT 4 +#define DDR_PHY_MR13_RRO_MASK 0x00000010U -/*VREF Current Generator*/ +/* +* VREF Current Generator +*/ #undef DDR_PHY_MR13_VRCG_DEFVAL #undef DDR_PHY_MR13_VRCG_SHIFT #undef DDR_PHY_MR13_VRCG_MASK -#define DDR_PHY_MR13_VRCG_DEFVAL 0x00000000 -#define DDR_PHY_MR13_VRCG_SHIFT 3 -#define DDR_PHY_MR13_VRCG_MASK 0x00000008U +#define DDR_PHY_MR13_VRCG_DEFVAL 0x00000000 +#define DDR_PHY_MR13_VRCG_SHIFT 3 +#define DDR_PHY_MR13_VRCG_MASK 0x00000008U -/*VREF Output*/ +/* +* VREF Output +*/ #undef DDR_PHY_MR13_VRO_DEFVAL #undef DDR_PHY_MR13_VRO_SHIFT #undef DDR_PHY_MR13_VRO_MASK -#define DDR_PHY_MR13_VRO_DEFVAL 0x00000000 -#define DDR_PHY_MR13_VRO_SHIFT 2 -#define DDR_PHY_MR13_VRO_MASK 0x00000004U +#define DDR_PHY_MR13_VRO_DEFVAL 0x00000000 +#define DDR_PHY_MR13_VRO_SHIFT 2 +#define DDR_PHY_MR13_VRO_MASK 0x00000004U -/*Read Preamble Training Mode*/ +/* +* Read Preamble Training Mode +*/ #undef DDR_PHY_MR13_RPT_DEFVAL #undef DDR_PHY_MR13_RPT_SHIFT #undef DDR_PHY_MR13_RPT_MASK -#define DDR_PHY_MR13_RPT_DEFVAL 0x00000000 -#define DDR_PHY_MR13_RPT_SHIFT 1 -#define DDR_PHY_MR13_RPT_MASK 0x00000002U +#define DDR_PHY_MR13_RPT_DEFVAL 0x00000000 +#define DDR_PHY_MR13_RPT_SHIFT 1 +#define DDR_PHY_MR13_RPT_MASK 0x00000002U -/*Command Bus Training*/ +/* +* Command Bus Training +*/ #undef DDR_PHY_MR13_CBT_DEFVAL #undef DDR_PHY_MR13_CBT_SHIFT #undef DDR_PHY_MR13_CBT_MASK -#define DDR_PHY_MR13_CBT_DEFVAL 0x00000000 -#define DDR_PHY_MR13_CBT_SHIFT 0 -#define DDR_PHY_MR13_CBT_MASK 0x00000001U +#define DDR_PHY_MR13_CBT_DEFVAL 0x00000000 +#define DDR_PHY_MR13_CBT_SHIFT 0 +#define DDR_PHY_MR13_CBT_MASK 0x00000001U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_MR14_RESERVED_31_8_DEFVAL #undef DDR_PHY_MR14_RESERVED_31_8_SHIFT #undef DDR_PHY_MR14_RESERVED_31_8_MASK -#define DDR_PHY_MR14_RESERVED_31_8_DEFVAL 0x0000004D -#define DDR_PHY_MR14_RESERVED_31_8_SHIFT 8 -#define DDR_PHY_MR14_RESERVED_31_8_MASK 0xFFFFFF00U +#define DDR_PHY_MR14_RESERVED_31_8_DEFVAL 0x0000004D +#define DDR_PHY_MR14_RESERVED_31_8_SHIFT 8 +#define DDR_PHY_MR14_RESERVED_31_8_MASK 0xFFFFFF00U -/*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/ +/* +* These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. +*/ #undef DDR_PHY_MR14_RSVD_DEFVAL #undef DDR_PHY_MR14_RSVD_SHIFT #undef DDR_PHY_MR14_RSVD_MASK -#define DDR_PHY_MR14_RSVD_DEFVAL 0x0000004D -#define DDR_PHY_MR14_RSVD_SHIFT 7 -#define DDR_PHY_MR14_RSVD_MASK 0x00000080U +#define DDR_PHY_MR14_RSVD_DEFVAL 0x0000004D +#define DDR_PHY_MR14_RSVD_SHIFT 7 +#define DDR_PHY_MR14_RSVD_MASK 0x00000080U -/*VREFDQ Range Selects.*/ +/* +* VREFDQ Range Selects. +*/ #undef DDR_PHY_MR14_VR_DQ_DEFVAL #undef DDR_PHY_MR14_VR_DQ_SHIFT #undef DDR_PHY_MR14_VR_DQ_MASK -#define DDR_PHY_MR14_VR_DQ_DEFVAL 0x0000004D -#define DDR_PHY_MR14_VR_DQ_SHIFT 6 -#define DDR_PHY_MR14_VR_DQ_MASK 0x00000040U +#define DDR_PHY_MR14_VR_DQ_DEFVAL 0x0000004D +#define DDR_PHY_MR14_VR_DQ_SHIFT 6 +#define DDR_PHY_MR14_VR_DQ_MASK 0x00000040U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_MR14_VREF_DQ_DEFVAL #undef DDR_PHY_MR14_VREF_DQ_SHIFT #undef DDR_PHY_MR14_VREF_DQ_MASK -#define DDR_PHY_MR14_VREF_DQ_DEFVAL 0x0000004D -#define DDR_PHY_MR14_VREF_DQ_SHIFT 0 -#define DDR_PHY_MR14_VREF_DQ_MASK 0x0000003FU +#define DDR_PHY_MR14_VREF_DQ_DEFVAL 0x0000004D +#define DDR_PHY_MR14_VREF_DQ_SHIFT 0 +#define DDR_PHY_MR14_VREF_DQ_MASK 0x0000003FU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_MR22_RESERVED_31_8_DEFVAL #undef DDR_PHY_MR22_RESERVED_31_8_SHIFT #undef DDR_PHY_MR22_RESERVED_31_8_MASK -#define DDR_PHY_MR22_RESERVED_31_8_DEFVAL 0x00000000 -#define DDR_PHY_MR22_RESERVED_31_8_SHIFT 8 -#define DDR_PHY_MR22_RESERVED_31_8_MASK 0xFFFFFF00U +#define DDR_PHY_MR22_RESERVED_31_8_DEFVAL 0x00000000 +#define DDR_PHY_MR22_RESERVED_31_8_SHIFT 8 +#define DDR_PHY_MR22_RESERVED_31_8_MASK 0xFFFFFF00U -/*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/ +/* +* These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. +*/ #undef DDR_PHY_MR22_RSVD_DEFVAL #undef DDR_PHY_MR22_RSVD_SHIFT #undef DDR_PHY_MR22_RSVD_MASK -#define DDR_PHY_MR22_RSVD_DEFVAL 0x00000000 -#define DDR_PHY_MR22_RSVD_SHIFT 6 -#define DDR_PHY_MR22_RSVD_MASK 0x000000C0U +#define DDR_PHY_MR22_RSVD_DEFVAL 0x00000000 +#define DDR_PHY_MR22_RSVD_SHIFT 6 +#define DDR_PHY_MR22_RSVD_MASK 0x000000C0U -/*CA ODT termination disable.*/ +/* +* CA ODT termination disable. +*/ #undef DDR_PHY_MR22_ODTD_CA_DEFVAL #undef DDR_PHY_MR22_ODTD_CA_SHIFT #undef DDR_PHY_MR22_ODTD_CA_MASK -#define DDR_PHY_MR22_ODTD_CA_DEFVAL 0x00000000 -#define DDR_PHY_MR22_ODTD_CA_SHIFT 5 -#define DDR_PHY_MR22_ODTD_CA_MASK 0x00000020U +#define DDR_PHY_MR22_ODTD_CA_DEFVAL 0x00000000 +#define DDR_PHY_MR22_ODTD_CA_SHIFT 5 +#define DDR_PHY_MR22_ODTD_CA_MASK 0x00000020U -/*ODT CS override.*/ +/* +* ODT CS override. +*/ #undef DDR_PHY_MR22_ODTE_CS_DEFVAL #undef DDR_PHY_MR22_ODTE_CS_SHIFT #undef DDR_PHY_MR22_ODTE_CS_MASK -#define DDR_PHY_MR22_ODTE_CS_DEFVAL 0x00000000 -#define DDR_PHY_MR22_ODTE_CS_SHIFT 4 -#define DDR_PHY_MR22_ODTE_CS_MASK 0x00000010U +#define DDR_PHY_MR22_ODTE_CS_DEFVAL 0x00000000 +#define DDR_PHY_MR22_ODTE_CS_SHIFT 4 +#define DDR_PHY_MR22_ODTE_CS_MASK 0x00000010U -/*ODT CK override.*/ +/* +* ODT CK override. +*/ #undef DDR_PHY_MR22_ODTE_CK_DEFVAL #undef DDR_PHY_MR22_ODTE_CK_SHIFT #undef DDR_PHY_MR22_ODTE_CK_MASK -#define DDR_PHY_MR22_ODTE_CK_DEFVAL 0x00000000 -#define DDR_PHY_MR22_ODTE_CK_SHIFT 3 -#define DDR_PHY_MR22_ODTE_CK_MASK 0x00000008U +#define DDR_PHY_MR22_ODTE_CK_DEFVAL 0x00000000 +#define DDR_PHY_MR22_ODTE_CK_SHIFT 3 +#define DDR_PHY_MR22_ODTE_CK_MASK 0x00000008U -/*Controller ODT value for VOH calibration.*/ +/* +* Controller ODT value for VOH calibration. +*/ #undef DDR_PHY_MR22_CODT_DEFVAL #undef DDR_PHY_MR22_CODT_SHIFT #undef DDR_PHY_MR22_CODT_MASK -#define DDR_PHY_MR22_CODT_DEFVAL 0x00000000 -#define DDR_PHY_MR22_CODT_SHIFT 0 -#define DDR_PHY_MR22_CODT_MASK 0x00000007U +#define DDR_PHY_MR22_CODT_DEFVAL 0x00000000 +#define DDR_PHY_MR22_CODT_SHIFT 0 +#define DDR_PHY_MR22_CODT_MASK 0x00000007U -/*Refresh During Training*/ +/* +* Refresh During Training +*/ #undef DDR_PHY_DTCR0_RFSHDT_DEFVAL #undef DDR_PHY_DTCR0_RFSHDT_SHIFT #undef DDR_PHY_DTCR0_RFSHDT_MASK -#define DDR_PHY_DTCR0_RFSHDT_DEFVAL 0x800091C7 -#define DDR_PHY_DTCR0_RFSHDT_SHIFT 28 -#define DDR_PHY_DTCR0_RFSHDT_MASK 0xF0000000U +#define DDR_PHY_DTCR0_RFSHDT_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_RFSHDT_SHIFT 28 +#define DDR_PHY_DTCR0_RFSHDT_MASK 0xF0000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTCR0_RESERVED_27_26_DEFVAL #undef DDR_PHY_DTCR0_RESERVED_27_26_SHIFT #undef DDR_PHY_DTCR0_RESERVED_27_26_MASK -#define DDR_PHY_DTCR0_RESERVED_27_26_DEFVAL 0x800091C7 -#define DDR_PHY_DTCR0_RESERVED_27_26_SHIFT 26 -#define DDR_PHY_DTCR0_RESERVED_27_26_MASK 0x0C000000U +#define DDR_PHY_DTCR0_RESERVED_27_26_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_RESERVED_27_26_SHIFT 26 +#define DDR_PHY_DTCR0_RESERVED_27_26_MASK 0x0C000000U -/*Data Training Debug Rank Select*/ +/* +* Data Training Debug Rank Select +*/ #undef DDR_PHY_DTCR0_DTDRS_DEFVAL #undef DDR_PHY_DTCR0_DTDRS_SHIFT #undef DDR_PHY_DTCR0_DTDRS_MASK -#define DDR_PHY_DTCR0_DTDRS_DEFVAL 0x800091C7 -#define DDR_PHY_DTCR0_DTDRS_SHIFT 24 -#define DDR_PHY_DTCR0_DTDRS_MASK 0x03000000U +#define DDR_PHY_DTCR0_DTDRS_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_DTDRS_SHIFT 24 +#define DDR_PHY_DTCR0_DTDRS_MASK 0x03000000U -/*Data Training with Early/Extended Gate*/ +/* +* Data Training with Early/Extended Gate +*/ #undef DDR_PHY_DTCR0_DTEXG_DEFVAL #undef DDR_PHY_DTCR0_DTEXG_SHIFT #undef DDR_PHY_DTCR0_DTEXG_MASK -#define DDR_PHY_DTCR0_DTEXG_DEFVAL 0x800091C7 -#define DDR_PHY_DTCR0_DTEXG_SHIFT 23 -#define DDR_PHY_DTCR0_DTEXG_MASK 0x00800000U +#define DDR_PHY_DTCR0_DTEXG_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_DTEXG_SHIFT 23 +#define DDR_PHY_DTCR0_DTEXG_MASK 0x00800000U -/*Data Training Extended Write DQS*/ +/* +* Data Training Extended Write DQS +*/ #undef DDR_PHY_DTCR0_DTEXD_DEFVAL #undef DDR_PHY_DTCR0_DTEXD_SHIFT #undef DDR_PHY_DTCR0_DTEXD_MASK -#define DDR_PHY_DTCR0_DTEXD_DEFVAL 0x800091C7 -#define DDR_PHY_DTCR0_DTEXD_SHIFT 22 -#define DDR_PHY_DTCR0_DTEXD_MASK 0x00400000U +#define DDR_PHY_DTCR0_DTEXD_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_DTEXD_SHIFT 22 +#define DDR_PHY_DTCR0_DTEXD_MASK 0x00400000U -/*Data Training Debug Step*/ +/* +* Data Training Debug Step +*/ #undef DDR_PHY_DTCR0_DTDSTP_DEFVAL #undef DDR_PHY_DTCR0_DTDSTP_SHIFT #undef DDR_PHY_DTCR0_DTDSTP_MASK -#define DDR_PHY_DTCR0_DTDSTP_DEFVAL 0x800091C7 -#define DDR_PHY_DTCR0_DTDSTP_SHIFT 21 -#define DDR_PHY_DTCR0_DTDSTP_MASK 0x00200000U +#define DDR_PHY_DTCR0_DTDSTP_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_DTDSTP_SHIFT 21 +#define DDR_PHY_DTCR0_DTDSTP_MASK 0x00200000U -/*Data Training Debug Enable*/ +/* +* Data Training Debug Enable +*/ #undef DDR_PHY_DTCR0_DTDEN_DEFVAL #undef DDR_PHY_DTCR0_DTDEN_SHIFT #undef DDR_PHY_DTCR0_DTDEN_MASK -#define DDR_PHY_DTCR0_DTDEN_DEFVAL 0x800091C7 -#define DDR_PHY_DTCR0_DTDEN_SHIFT 20 -#define DDR_PHY_DTCR0_DTDEN_MASK 0x00100000U +#define DDR_PHY_DTCR0_DTDEN_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_DTDEN_SHIFT 20 +#define DDR_PHY_DTCR0_DTDEN_MASK 0x00100000U -/*Data Training Debug Byte Select*/ +/* +* Data Training Debug Byte Select +*/ #undef DDR_PHY_DTCR0_DTDBS_DEFVAL #undef DDR_PHY_DTCR0_DTDBS_SHIFT #undef DDR_PHY_DTCR0_DTDBS_MASK -#define DDR_PHY_DTCR0_DTDBS_DEFVAL 0x800091C7 -#define DDR_PHY_DTCR0_DTDBS_SHIFT 16 -#define DDR_PHY_DTCR0_DTDBS_MASK 0x000F0000U +#define DDR_PHY_DTCR0_DTDBS_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_DTDBS_SHIFT 16 +#define DDR_PHY_DTCR0_DTDBS_MASK 0x000F0000U -/*Data Training read DBI deskewing configuration*/ +/* +* Data Training read DBI deskewing configuration +*/ #undef DDR_PHY_DTCR0_DTRDBITR_DEFVAL #undef DDR_PHY_DTCR0_DTRDBITR_SHIFT #undef DDR_PHY_DTCR0_DTRDBITR_MASK -#define DDR_PHY_DTCR0_DTRDBITR_DEFVAL 0x800091C7 -#define DDR_PHY_DTCR0_DTRDBITR_SHIFT 14 -#define DDR_PHY_DTCR0_DTRDBITR_MASK 0x0000C000U +#define DDR_PHY_DTCR0_DTRDBITR_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_DTRDBITR_SHIFT 14 +#define DDR_PHY_DTCR0_DTRDBITR_MASK 0x0000C000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTCR0_RESERVED_13_DEFVAL #undef DDR_PHY_DTCR0_RESERVED_13_SHIFT #undef DDR_PHY_DTCR0_RESERVED_13_MASK -#define DDR_PHY_DTCR0_RESERVED_13_DEFVAL 0x800091C7 -#define DDR_PHY_DTCR0_RESERVED_13_SHIFT 13 -#define DDR_PHY_DTCR0_RESERVED_13_MASK 0x00002000U +#define DDR_PHY_DTCR0_RESERVED_13_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_RESERVED_13_SHIFT 13 +#define DDR_PHY_DTCR0_RESERVED_13_MASK 0x00002000U -/*Data Training Write Bit Deskew Data Mask*/ +/* +* Data Training Write Bit Deskew Data Mask +*/ #undef DDR_PHY_DTCR0_DTWBDDM_DEFVAL #undef DDR_PHY_DTCR0_DTWBDDM_SHIFT #undef DDR_PHY_DTCR0_DTWBDDM_MASK -#define DDR_PHY_DTCR0_DTWBDDM_DEFVAL 0x800091C7 -#define DDR_PHY_DTCR0_DTWBDDM_SHIFT 12 -#define DDR_PHY_DTCR0_DTWBDDM_MASK 0x00001000U +#define DDR_PHY_DTCR0_DTWBDDM_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_DTWBDDM_SHIFT 12 +#define DDR_PHY_DTCR0_DTWBDDM_MASK 0x00001000U -/*Refreshes Issued During Entry to Training*/ +/* +* Refreshes Issued During Entry to Training +*/ #undef DDR_PHY_DTCR0_RFSHEN_DEFVAL #undef DDR_PHY_DTCR0_RFSHEN_SHIFT #undef DDR_PHY_DTCR0_RFSHEN_MASK -#define DDR_PHY_DTCR0_RFSHEN_DEFVAL 0x800091C7 -#define DDR_PHY_DTCR0_RFSHEN_SHIFT 8 -#define DDR_PHY_DTCR0_RFSHEN_MASK 0x00000F00U +#define DDR_PHY_DTCR0_RFSHEN_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_RFSHEN_SHIFT 8 +#define DDR_PHY_DTCR0_RFSHEN_MASK 0x00000F00U -/*Data Training Compare Data*/ +/* +* Data Training Compare Data +*/ #undef DDR_PHY_DTCR0_DTCMPD_DEFVAL #undef DDR_PHY_DTCR0_DTCMPD_SHIFT #undef DDR_PHY_DTCR0_DTCMPD_MASK -#define DDR_PHY_DTCR0_DTCMPD_DEFVAL 0x800091C7 -#define DDR_PHY_DTCR0_DTCMPD_SHIFT 7 -#define DDR_PHY_DTCR0_DTCMPD_MASK 0x00000080U +#define DDR_PHY_DTCR0_DTCMPD_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_DTCMPD_SHIFT 7 +#define DDR_PHY_DTCR0_DTCMPD_MASK 0x00000080U -/*Data Training Using MPR*/ +/* +* Data Training Using MPR +*/ #undef DDR_PHY_DTCR0_DTMPR_DEFVAL #undef DDR_PHY_DTCR0_DTMPR_SHIFT #undef DDR_PHY_DTCR0_DTMPR_MASK -#define DDR_PHY_DTCR0_DTMPR_DEFVAL 0x800091C7 -#define DDR_PHY_DTCR0_DTMPR_SHIFT 6 -#define DDR_PHY_DTCR0_DTMPR_MASK 0x00000040U +#define DDR_PHY_DTCR0_DTMPR_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_DTMPR_SHIFT 6 +#define DDR_PHY_DTCR0_DTMPR_MASK 0x00000040U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTCR0_RESERVED_5_4_DEFVAL #undef DDR_PHY_DTCR0_RESERVED_5_4_SHIFT #undef DDR_PHY_DTCR0_RESERVED_5_4_MASK -#define DDR_PHY_DTCR0_RESERVED_5_4_DEFVAL 0x800091C7 -#define DDR_PHY_DTCR0_RESERVED_5_4_SHIFT 4 -#define DDR_PHY_DTCR0_RESERVED_5_4_MASK 0x00000030U +#define DDR_PHY_DTCR0_RESERVED_5_4_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_RESERVED_5_4_SHIFT 4 +#define DDR_PHY_DTCR0_RESERVED_5_4_MASK 0x00000030U -/*Data Training Repeat Number*/ +/* +* Data Training Repeat Number +*/ #undef DDR_PHY_DTCR0_DTRPTN_DEFVAL #undef DDR_PHY_DTCR0_DTRPTN_SHIFT #undef DDR_PHY_DTCR0_DTRPTN_MASK -#define DDR_PHY_DTCR0_DTRPTN_DEFVAL 0x800091C7 -#define DDR_PHY_DTCR0_DTRPTN_SHIFT 0 -#define DDR_PHY_DTCR0_DTRPTN_MASK 0x0000000FU +#define DDR_PHY_DTCR0_DTRPTN_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_DTRPTN_SHIFT 0 +#define DDR_PHY_DTCR0_DTRPTN_MASK 0x0000000FU -/*Rank Enable.*/ +/* +* Rank Enable. +*/ #undef DDR_PHY_DTCR1_RANKEN_RSVD_DEFVAL #undef DDR_PHY_DTCR1_RANKEN_RSVD_SHIFT #undef DDR_PHY_DTCR1_RANKEN_RSVD_MASK -#define DDR_PHY_DTCR1_RANKEN_RSVD_DEFVAL 0x00030237 -#define DDR_PHY_DTCR1_RANKEN_RSVD_SHIFT 18 -#define DDR_PHY_DTCR1_RANKEN_RSVD_MASK 0xFFFC0000U +#define DDR_PHY_DTCR1_RANKEN_RSVD_DEFVAL 0x00030237 +#define DDR_PHY_DTCR1_RANKEN_RSVD_SHIFT 18 +#define DDR_PHY_DTCR1_RANKEN_RSVD_MASK 0xFFFC0000U -/*Rank Enable.*/ +/* +* Rank Enable. +*/ #undef DDR_PHY_DTCR1_RANKEN_DEFVAL #undef DDR_PHY_DTCR1_RANKEN_SHIFT #undef DDR_PHY_DTCR1_RANKEN_MASK -#define DDR_PHY_DTCR1_RANKEN_DEFVAL 0x00030237 -#define DDR_PHY_DTCR1_RANKEN_SHIFT 16 -#define DDR_PHY_DTCR1_RANKEN_MASK 0x00030000U +#define DDR_PHY_DTCR1_RANKEN_DEFVAL 0x00030237 +#define DDR_PHY_DTCR1_RANKEN_SHIFT 16 +#define DDR_PHY_DTCR1_RANKEN_MASK 0x00030000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTCR1_RESERVED_15_14_DEFVAL #undef DDR_PHY_DTCR1_RESERVED_15_14_SHIFT #undef DDR_PHY_DTCR1_RESERVED_15_14_MASK -#define DDR_PHY_DTCR1_RESERVED_15_14_DEFVAL 0x00030237 -#define DDR_PHY_DTCR1_RESERVED_15_14_SHIFT 14 -#define DDR_PHY_DTCR1_RESERVED_15_14_MASK 0x0000C000U +#define DDR_PHY_DTCR1_RESERVED_15_14_DEFVAL 0x00030237 +#define DDR_PHY_DTCR1_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_DTCR1_RESERVED_15_14_MASK 0x0000C000U -/*Data Training Rank*/ +/* +* Data Training Rank +*/ #undef DDR_PHY_DTCR1_DTRANK_DEFVAL #undef DDR_PHY_DTCR1_DTRANK_SHIFT #undef DDR_PHY_DTCR1_DTRANK_MASK -#define DDR_PHY_DTCR1_DTRANK_DEFVAL 0x00030237 -#define DDR_PHY_DTCR1_DTRANK_SHIFT 12 -#define DDR_PHY_DTCR1_DTRANK_MASK 0x00003000U +#define DDR_PHY_DTCR1_DTRANK_DEFVAL 0x00030237 +#define DDR_PHY_DTCR1_DTRANK_SHIFT 12 +#define DDR_PHY_DTCR1_DTRANK_MASK 0x00003000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTCR1_RESERVED_11_DEFVAL #undef DDR_PHY_DTCR1_RESERVED_11_SHIFT #undef DDR_PHY_DTCR1_RESERVED_11_MASK -#define DDR_PHY_DTCR1_RESERVED_11_DEFVAL 0x00030237 -#define DDR_PHY_DTCR1_RESERVED_11_SHIFT 11 -#define DDR_PHY_DTCR1_RESERVED_11_MASK 0x00000800U +#define DDR_PHY_DTCR1_RESERVED_11_DEFVAL 0x00030237 +#define DDR_PHY_DTCR1_RESERVED_11_SHIFT 11 +#define DDR_PHY_DTCR1_RESERVED_11_MASK 0x00000800U -/*Read Leveling Gate Sampling Difference*/ +/* +* Read Leveling Gate Sampling Difference +*/ #undef DDR_PHY_DTCR1_RDLVLGDIFF_DEFVAL #undef DDR_PHY_DTCR1_RDLVLGDIFF_SHIFT #undef DDR_PHY_DTCR1_RDLVLGDIFF_MASK -#define DDR_PHY_DTCR1_RDLVLGDIFF_DEFVAL 0x00030237 -#define DDR_PHY_DTCR1_RDLVLGDIFF_SHIFT 8 -#define DDR_PHY_DTCR1_RDLVLGDIFF_MASK 0x00000700U +#define DDR_PHY_DTCR1_RDLVLGDIFF_DEFVAL 0x00030237 +#define DDR_PHY_DTCR1_RDLVLGDIFF_SHIFT 8 +#define DDR_PHY_DTCR1_RDLVLGDIFF_MASK 0x00000700U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTCR1_RESERVED_7_DEFVAL #undef DDR_PHY_DTCR1_RESERVED_7_SHIFT #undef DDR_PHY_DTCR1_RESERVED_7_MASK -#define DDR_PHY_DTCR1_RESERVED_7_DEFVAL 0x00030237 -#define DDR_PHY_DTCR1_RESERVED_7_SHIFT 7 -#define DDR_PHY_DTCR1_RESERVED_7_MASK 0x00000080U +#define DDR_PHY_DTCR1_RESERVED_7_DEFVAL 0x00030237 +#define DDR_PHY_DTCR1_RESERVED_7_SHIFT 7 +#define DDR_PHY_DTCR1_RESERVED_7_MASK 0x00000080U -/*Read Leveling Gate Shift*/ +/* +* Read Leveling Gate Shift +*/ #undef DDR_PHY_DTCR1_RDLVLGS_DEFVAL #undef DDR_PHY_DTCR1_RDLVLGS_SHIFT #undef DDR_PHY_DTCR1_RDLVLGS_MASK -#define DDR_PHY_DTCR1_RDLVLGS_DEFVAL 0x00030237 -#define DDR_PHY_DTCR1_RDLVLGS_SHIFT 4 -#define DDR_PHY_DTCR1_RDLVLGS_MASK 0x00000070U +#define DDR_PHY_DTCR1_RDLVLGS_DEFVAL 0x00030237 +#define DDR_PHY_DTCR1_RDLVLGS_SHIFT 4 +#define DDR_PHY_DTCR1_RDLVLGS_MASK 0x00000070U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTCR1_RESERVED_3_DEFVAL #undef DDR_PHY_DTCR1_RESERVED_3_SHIFT #undef DDR_PHY_DTCR1_RESERVED_3_MASK -#define DDR_PHY_DTCR1_RESERVED_3_DEFVAL 0x00030237 -#define DDR_PHY_DTCR1_RESERVED_3_SHIFT 3 -#define DDR_PHY_DTCR1_RESERVED_3_MASK 0x00000008U +#define DDR_PHY_DTCR1_RESERVED_3_DEFVAL 0x00030237 +#define DDR_PHY_DTCR1_RESERVED_3_SHIFT 3 +#define DDR_PHY_DTCR1_RESERVED_3_MASK 0x00000008U -/*Read Preamble Training enable*/ +/* +* Read Preamble Training enable +*/ #undef DDR_PHY_DTCR1_RDPRMVL_TRN_DEFVAL #undef DDR_PHY_DTCR1_RDPRMVL_TRN_SHIFT #undef DDR_PHY_DTCR1_RDPRMVL_TRN_MASK -#define DDR_PHY_DTCR1_RDPRMVL_TRN_DEFVAL 0x00030237 -#define DDR_PHY_DTCR1_RDPRMVL_TRN_SHIFT 2 -#define DDR_PHY_DTCR1_RDPRMVL_TRN_MASK 0x00000004U +#define DDR_PHY_DTCR1_RDPRMVL_TRN_DEFVAL 0x00030237 +#define DDR_PHY_DTCR1_RDPRMVL_TRN_SHIFT 2 +#define DDR_PHY_DTCR1_RDPRMVL_TRN_MASK 0x00000004U -/*Read Leveling Enable*/ +/* +* Read Leveling Enable +*/ #undef DDR_PHY_DTCR1_RDLVLEN_DEFVAL #undef DDR_PHY_DTCR1_RDLVLEN_SHIFT #undef DDR_PHY_DTCR1_RDLVLEN_MASK -#define DDR_PHY_DTCR1_RDLVLEN_DEFVAL 0x00030237 -#define DDR_PHY_DTCR1_RDLVLEN_SHIFT 1 -#define DDR_PHY_DTCR1_RDLVLEN_MASK 0x00000002U +#define DDR_PHY_DTCR1_RDLVLEN_DEFVAL 0x00030237 +#define DDR_PHY_DTCR1_RDLVLEN_SHIFT 1 +#define DDR_PHY_DTCR1_RDLVLEN_MASK 0x00000002U -/*Basic Gate Training Enable*/ +/* +* Basic Gate Training Enable +*/ #undef DDR_PHY_DTCR1_BSTEN_DEFVAL #undef DDR_PHY_DTCR1_BSTEN_SHIFT #undef DDR_PHY_DTCR1_BSTEN_MASK -#define DDR_PHY_DTCR1_BSTEN_DEFVAL 0x00030237 -#define DDR_PHY_DTCR1_BSTEN_SHIFT 0 -#define DDR_PHY_DTCR1_BSTEN_MASK 0x00000001U +#define DDR_PHY_DTCR1_BSTEN_DEFVAL 0x00030237 +#define DDR_PHY_DTCR1_BSTEN_SHIFT 0 +#define DDR_PHY_DTCR1_BSTEN_MASK 0x00000001U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_CATR0_RESERVED_31_21_DEFVAL #undef DDR_PHY_CATR0_RESERVED_31_21_SHIFT #undef DDR_PHY_CATR0_RESERVED_31_21_MASK -#define DDR_PHY_CATR0_RESERVED_31_21_DEFVAL 0x00141054 -#define DDR_PHY_CATR0_RESERVED_31_21_SHIFT 21 -#define DDR_PHY_CATR0_RESERVED_31_21_MASK 0xFFE00000U +#define DDR_PHY_CATR0_RESERVED_31_21_DEFVAL 0x00141054 +#define DDR_PHY_CATR0_RESERVED_31_21_SHIFT 21 +#define DDR_PHY_CATR0_RESERVED_31_21_MASK 0xFFE00000U -/*Minimum time (in terms of number of dram clocks) between two consectuve CA calibration command*/ +/* +* Minimum time (in terms of number of dram clocks) between two consectuve + * CA calibration command +*/ #undef DDR_PHY_CATR0_CACD_DEFVAL #undef DDR_PHY_CATR0_CACD_SHIFT #undef DDR_PHY_CATR0_CACD_MASK -#define DDR_PHY_CATR0_CACD_DEFVAL 0x00141054 -#define DDR_PHY_CATR0_CACD_SHIFT 16 -#define DDR_PHY_CATR0_CACD_MASK 0x001F0000U +#define DDR_PHY_CATR0_CACD_DEFVAL 0x00141054 +#define DDR_PHY_CATR0_CACD_SHIFT 16 +#define DDR_PHY_CATR0_CACD_MASK 0x001F0000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_CATR0_RESERVED_15_13_DEFVAL #undef DDR_PHY_CATR0_RESERVED_15_13_SHIFT #undef DDR_PHY_CATR0_RESERVED_15_13_MASK -#define DDR_PHY_CATR0_RESERVED_15_13_DEFVAL 0x00141054 -#define DDR_PHY_CATR0_RESERVED_15_13_SHIFT 13 -#define DDR_PHY_CATR0_RESERVED_15_13_MASK 0x0000E000U +#define DDR_PHY_CATR0_RESERVED_15_13_DEFVAL 0x00141054 +#define DDR_PHY_CATR0_RESERVED_15_13_SHIFT 13 +#define DDR_PHY_CATR0_RESERVED_15_13_MASK 0x0000E000U -/*Minimum time (in terms of number of dram clocks) PUB should wait before sampling the CA response after Calibration command ha - been sent to the memory*/ +/* +* Minimum time (in terms of number of dram clocks) PUB should wait before + * sampling the CA response after Calibration command has been sent to the + * memory +*/ #undef DDR_PHY_CATR0_CAADR_DEFVAL #undef DDR_PHY_CATR0_CAADR_SHIFT #undef DDR_PHY_CATR0_CAADR_MASK -#define DDR_PHY_CATR0_CAADR_DEFVAL 0x00141054 -#define DDR_PHY_CATR0_CAADR_SHIFT 8 -#define DDR_PHY_CATR0_CAADR_MASK 0x00001F00U +#define DDR_PHY_CATR0_CAADR_DEFVAL 0x00141054 +#define DDR_PHY_CATR0_CAADR_SHIFT 8 +#define DDR_PHY_CATR0_CAADR_MASK 0x00001F00U -/*CA_1 Response Byte Lane 1*/ +/* +* CA_1 Response Byte Lane 1 +*/ #undef DDR_PHY_CATR0_CA1BYTE1_DEFVAL #undef DDR_PHY_CATR0_CA1BYTE1_SHIFT #undef DDR_PHY_CATR0_CA1BYTE1_MASK -#define DDR_PHY_CATR0_CA1BYTE1_DEFVAL 0x00141054 -#define DDR_PHY_CATR0_CA1BYTE1_SHIFT 4 -#define DDR_PHY_CATR0_CA1BYTE1_MASK 0x000000F0U +#define DDR_PHY_CATR0_CA1BYTE1_DEFVAL 0x00141054 +#define DDR_PHY_CATR0_CA1BYTE1_SHIFT 4 +#define DDR_PHY_CATR0_CA1BYTE1_MASK 0x000000F0U -/*CA_1 Response Byte Lane 0*/ +/* +* CA_1 Response Byte Lane 0 +*/ #undef DDR_PHY_CATR0_CA1BYTE0_DEFVAL #undef DDR_PHY_CATR0_CA1BYTE0_SHIFT #undef DDR_PHY_CATR0_CA1BYTE0_MASK -#define DDR_PHY_CATR0_CA1BYTE0_DEFVAL 0x00141054 -#define DDR_PHY_CATR0_CA1BYTE0_SHIFT 0 -#define DDR_PHY_CATR0_CA1BYTE0_MASK 0x0000000FU +#define DDR_PHY_CATR0_CA1BYTE0_DEFVAL 0x00141054 +#define DDR_PHY_CATR0_CA1BYTE0_SHIFT 0 +#define DDR_PHY_CATR0_CA1BYTE0_MASK 0x0000000FU -/*LFSR seed for pseudo-random BIST patterns*/ +/* +* Number of delay taps by which the DQS gate LCDL will be updated when DQS + * drift is detected +*/ +#undef DDR_PHY_DQSDR0_DFTDLY_DEFVAL +#undef DDR_PHY_DQSDR0_DFTDLY_SHIFT +#undef DDR_PHY_DQSDR0_DFTDLY_MASK +#define DDR_PHY_DQSDR0_DFTDLY_DEFVAL 0x00088000 +#define DDR_PHY_DQSDR0_DFTDLY_SHIFT 28 +#define DDR_PHY_DQSDR0_DFTDLY_MASK 0xF0000000U + +/* +* Drift Impedance Update +*/ +#undef DDR_PHY_DQSDR0_DFTZQUP_DEFVAL +#undef DDR_PHY_DQSDR0_DFTZQUP_SHIFT +#undef DDR_PHY_DQSDR0_DFTZQUP_MASK +#define DDR_PHY_DQSDR0_DFTZQUP_DEFVAL 0x00088000 +#define DDR_PHY_DQSDR0_DFTZQUP_SHIFT 27 +#define DDR_PHY_DQSDR0_DFTZQUP_MASK 0x08000000U + +/* +* Drift DDL Update +*/ +#undef DDR_PHY_DQSDR0_DFTDDLUP_DEFVAL +#undef DDR_PHY_DQSDR0_DFTDDLUP_SHIFT +#undef DDR_PHY_DQSDR0_DFTDDLUP_MASK +#define DDR_PHY_DQSDR0_DFTDDLUP_DEFVAL 0x00088000 +#define DDR_PHY_DQSDR0_DFTDDLUP_SHIFT 26 +#define DDR_PHY_DQSDR0_DFTDDLUP_MASK 0x04000000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DQSDR0_RESERVED_25_22_DEFVAL +#undef DDR_PHY_DQSDR0_RESERVED_25_22_SHIFT +#undef DDR_PHY_DQSDR0_RESERVED_25_22_MASK +#define DDR_PHY_DQSDR0_RESERVED_25_22_DEFVAL 0x00088000 +#define DDR_PHY_DQSDR0_RESERVED_25_22_SHIFT 22 +#define DDR_PHY_DQSDR0_RESERVED_25_22_MASK 0x03C00000U + +/* +* Drift Read Spacing +*/ +#undef DDR_PHY_DQSDR0_DFTRDSPC_DEFVAL +#undef DDR_PHY_DQSDR0_DFTRDSPC_SHIFT +#undef DDR_PHY_DQSDR0_DFTRDSPC_MASK +#define DDR_PHY_DQSDR0_DFTRDSPC_DEFVAL 0x00088000 +#define DDR_PHY_DQSDR0_DFTRDSPC_SHIFT 20 +#define DDR_PHY_DQSDR0_DFTRDSPC_MASK 0x00300000U + +/* +* Drift Back-to-Back Reads +*/ +#undef DDR_PHY_DQSDR0_DFTB2BRD_DEFVAL +#undef DDR_PHY_DQSDR0_DFTB2BRD_SHIFT +#undef DDR_PHY_DQSDR0_DFTB2BRD_MASK +#define DDR_PHY_DQSDR0_DFTB2BRD_DEFVAL 0x00088000 +#define DDR_PHY_DQSDR0_DFTB2BRD_SHIFT 16 +#define DDR_PHY_DQSDR0_DFTB2BRD_MASK 0x000F0000U + +/* +* Drift Idle Reads +*/ +#undef DDR_PHY_DQSDR0_DFTIDLRD_DEFVAL +#undef DDR_PHY_DQSDR0_DFTIDLRD_SHIFT +#undef DDR_PHY_DQSDR0_DFTIDLRD_MASK +#define DDR_PHY_DQSDR0_DFTIDLRD_DEFVAL 0x00088000 +#define DDR_PHY_DQSDR0_DFTIDLRD_SHIFT 12 +#define DDR_PHY_DQSDR0_DFTIDLRD_MASK 0x0000F000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DQSDR0_RESERVED_11_8_DEFVAL +#undef DDR_PHY_DQSDR0_RESERVED_11_8_SHIFT +#undef DDR_PHY_DQSDR0_RESERVED_11_8_MASK +#define DDR_PHY_DQSDR0_RESERVED_11_8_DEFVAL 0x00088000 +#define DDR_PHY_DQSDR0_RESERVED_11_8_SHIFT 8 +#define DDR_PHY_DQSDR0_RESERVED_11_8_MASK 0x00000F00U + +/* +* Gate Pulse Enable +*/ +#undef DDR_PHY_DQSDR0_DFTGPULSE_DEFVAL +#undef DDR_PHY_DQSDR0_DFTGPULSE_SHIFT +#undef DDR_PHY_DQSDR0_DFTGPULSE_MASK +#define DDR_PHY_DQSDR0_DFTGPULSE_DEFVAL 0x00088000 +#define DDR_PHY_DQSDR0_DFTGPULSE_SHIFT 4 +#define DDR_PHY_DQSDR0_DFTGPULSE_MASK 0x000000F0U + +/* +* DQS Drift Update Mode +*/ +#undef DDR_PHY_DQSDR0_DFTUPMODE_DEFVAL +#undef DDR_PHY_DQSDR0_DFTUPMODE_SHIFT +#undef DDR_PHY_DQSDR0_DFTUPMODE_MASK +#define DDR_PHY_DQSDR0_DFTUPMODE_DEFVAL 0x00088000 +#define DDR_PHY_DQSDR0_DFTUPMODE_SHIFT 2 +#define DDR_PHY_DQSDR0_DFTUPMODE_MASK 0x0000000CU + +/* +* DQS Drift Detection Mode +*/ +#undef DDR_PHY_DQSDR0_DFTDTMODE_DEFVAL +#undef DDR_PHY_DQSDR0_DFTDTMODE_SHIFT +#undef DDR_PHY_DQSDR0_DFTDTMODE_MASK +#define DDR_PHY_DQSDR0_DFTDTMODE_DEFVAL 0x00088000 +#define DDR_PHY_DQSDR0_DFTDTMODE_SHIFT 1 +#define DDR_PHY_DQSDR0_DFTDTMODE_MASK 0x00000002U + +/* +* DQS Drift Detection Enable +*/ +#undef DDR_PHY_DQSDR0_DFTDTEN_DEFVAL +#undef DDR_PHY_DQSDR0_DFTDTEN_SHIFT +#undef DDR_PHY_DQSDR0_DFTDTEN_MASK +#define DDR_PHY_DQSDR0_DFTDTEN_DEFVAL 0x00088000 +#define DDR_PHY_DQSDR0_DFTDTEN_SHIFT 0 +#define DDR_PHY_DQSDR0_DFTDTEN_MASK 0x00000001U + +/* +* LFSR seed for pseudo-random BIST patterns +*/ #undef DDR_PHY_BISTLSR_SEED_DEFVAL #undef DDR_PHY_BISTLSR_SEED_SHIFT #undef DDR_PHY_BISTLSR_SEED_MASK -#define DDR_PHY_BISTLSR_SEED_DEFVAL -#define DDR_PHY_BISTLSR_SEED_SHIFT 0 -#define DDR_PHY_BISTLSR_SEED_MASK 0xFFFFFFFFU +#define DDR_PHY_BISTLSR_SEED_DEFVAL +#define DDR_PHY_BISTLSR_SEED_SHIFT 0 +#define DDR_PHY_BISTLSR_SEED_MASK 0xFFFFFFFFU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_RIOCR5_RESERVED_31_16_DEFVAL #undef DDR_PHY_RIOCR5_RESERVED_31_16_SHIFT #undef DDR_PHY_RIOCR5_RESERVED_31_16_MASK -#define DDR_PHY_RIOCR5_RESERVED_31_16_DEFVAL 0x00000005 -#define DDR_PHY_RIOCR5_RESERVED_31_16_SHIFT 16 -#define DDR_PHY_RIOCR5_RESERVED_31_16_MASK 0xFFFF0000U +#define DDR_PHY_RIOCR5_RESERVED_31_16_DEFVAL 0x00000005 +#define DDR_PHY_RIOCR5_RESERVED_31_16_SHIFT 16 +#define DDR_PHY_RIOCR5_RESERVED_31_16_MASK 0xFFFF0000U -/*Reserved. Return zeros on reads.*/ +/* +* Reserved. Return zeros on reads. +*/ #undef DDR_PHY_RIOCR5_ODTOEMODE_RSVD_DEFVAL #undef DDR_PHY_RIOCR5_ODTOEMODE_RSVD_SHIFT #undef DDR_PHY_RIOCR5_ODTOEMODE_RSVD_MASK -#define DDR_PHY_RIOCR5_ODTOEMODE_RSVD_DEFVAL 0x00000005 -#define DDR_PHY_RIOCR5_ODTOEMODE_RSVD_SHIFT 4 -#define DDR_PHY_RIOCR5_ODTOEMODE_RSVD_MASK 0x0000FFF0U +#define DDR_PHY_RIOCR5_ODTOEMODE_RSVD_DEFVAL 0x00000005 +#define DDR_PHY_RIOCR5_ODTOEMODE_RSVD_SHIFT 4 +#define DDR_PHY_RIOCR5_ODTOEMODE_RSVD_MASK 0x0000FFF0U -/*SDRAM On-die Termination Output Enable (OE) Mode Selection.*/ +/* +* SDRAM On-die Termination Output Enable (OE) Mode Selection. +*/ #undef DDR_PHY_RIOCR5_ODTOEMODE_DEFVAL #undef DDR_PHY_RIOCR5_ODTOEMODE_SHIFT #undef DDR_PHY_RIOCR5_ODTOEMODE_MASK -#define DDR_PHY_RIOCR5_ODTOEMODE_DEFVAL 0x00000005 -#define DDR_PHY_RIOCR5_ODTOEMODE_SHIFT 0 -#define DDR_PHY_RIOCR5_ODTOEMODE_MASK 0x0000000FU +#define DDR_PHY_RIOCR5_ODTOEMODE_DEFVAL 0x00000005 +#define DDR_PHY_RIOCR5_ODTOEMODE_SHIFT 0 +#define DDR_PHY_RIOCR5_ODTOEMODE_MASK 0x0000000FU -/*Address/Command Slew Rate (D3F I/O Only)*/ +/* +* Address/Command Slew Rate (D3F I/O Only) +*/ #undef DDR_PHY_ACIOCR0_ACSR_DEFVAL #undef DDR_PHY_ACIOCR0_ACSR_SHIFT #undef DDR_PHY_ACIOCR0_ACSR_MASK -#define DDR_PHY_ACIOCR0_ACSR_DEFVAL 0x30000000 -#define DDR_PHY_ACIOCR0_ACSR_SHIFT 30 -#define DDR_PHY_ACIOCR0_ACSR_MASK 0xC0000000U +#define DDR_PHY_ACIOCR0_ACSR_DEFVAL 0x30000000 +#define DDR_PHY_ACIOCR0_ACSR_SHIFT 30 +#define DDR_PHY_ACIOCR0_ACSR_MASK 0xC0000000U -/*SDRAM Reset I/O Mode*/ +/* +* SDRAM Reset I/O Mode +*/ #undef DDR_PHY_ACIOCR0_RSTIOM_DEFVAL #undef DDR_PHY_ACIOCR0_RSTIOM_SHIFT #undef DDR_PHY_ACIOCR0_RSTIOM_MASK -#define DDR_PHY_ACIOCR0_RSTIOM_DEFVAL 0x30000000 -#define DDR_PHY_ACIOCR0_RSTIOM_SHIFT 29 -#define DDR_PHY_ACIOCR0_RSTIOM_MASK 0x20000000U +#define DDR_PHY_ACIOCR0_RSTIOM_DEFVAL 0x30000000 +#define DDR_PHY_ACIOCR0_RSTIOM_SHIFT 29 +#define DDR_PHY_ACIOCR0_RSTIOM_MASK 0x20000000U -/*SDRAM Reset Power Down Receiver*/ +/* +* SDRAM Reset Power Down Receiver +*/ #undef DDR_PHY_ACIOCR0_RSTPDR_DEFVAL #undef DDR_PHY_ACIOCR0_RSTPDR_SHIFT #undef DDR_PHY_ACIOCR0_RSTPDR_MASK -#define DDR_PHY_ACIOCR0_RSTPDR_DEFVAL 0x30000000 -#define DDR_PHY_ACIOCR0_RSTPDR_SHIFT 28 -#define DDR_PHY_ACIOCR0_RSTPDR_MASK 0x10000000U +#define DDR_PHY_ACIOCR0_RSTPDR_DEFVAL 0x30000000 +#define DDR_PHY_ACIOCR0_RSTPDR_SHIFT 28 +#define DDR_PHY_ACIOCR0_RSTPDR_MASK 0x10000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACIOCR0_RESERVED_27_DEFVAL #undef DDR_PHY_ACIOCR0_RESERVED_27_SHIFT #undef DDR_PHY_ACIOCR0_RESERVED_27_MASK -#define DDR_PHY_ACIOCR0_RESERVED_27_DEFVAL 0x30000000 -#define DDR_PHY_ACIOCR0_RESERVED_27_SHIFT 27 -#define DDR_PHY_ACIOCR0_RESERVED_27_MASK 0x08000000U +#define DDR_PHY_ACIOCR0_RESERVED_27_DEFVAL 0x30000000 +#define DDR_PHY_ACIOCR0_RESERVED_27_SHIFT 27 +#define DDR_PHY_ACIOCR0_RESERVED_27_MASK 0x08000000U -/*SDRAM Reset On-Die Termination*/ +/* +* SDRAM Reset On-Die Termination +*/ #undef DDR_PHY_ACIOCR0_RSTODT_DEFVAL #undef DDR_PHY_ACIOCR0_RSTODT_SHIFT #undef DDR_PHY_ACIOCR0_RSTODT_MASK -#define DDR_PHY_ACIOCR0_RSTODT_DEFVAL 0x30000000 -#define DDR_PHY_ACIOCR0_RSTODT_SHIFT 26 -#define DDR_PHY_ACIOCR0_RSTODT_MASK 0x04000000U +#define DDR_PHY_ACIOCR0_RSTODT_DEFVAL 0x30000000 +#define DDR_PHY_ACIOCR0_RSTODT_SHIFT 26 +#define DDR_PHY_ACIOCR0_RSTODT_MASK 0x04000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACIOCR0_RESERVED_25_10_DEFVAL #undef DDR_PHY_ACIOCR0_RESERVED_25_10_SHIFT #undef DDR_PHY_ACIOCR0_RESERVED_25_10_MASK -#define DDR_PHY_ACIOCR0_RESERVED_25_10_DEFVAL 0x30000000 -#define DDR_PHY_ACIOCR0_RESERVED_25_10_SHIFT 10 -#define DDR_PHY_ACIOCR0_RESERVED_25_10_MASK 0x03FFFC00U +#define DDR_PHY_ACIOCR0_RESERVED_25_10_DEFVAL 0x30000000 +#define DDR_PHY_ACIOCR0_RESERVED_25_10_SHIFT 10 +#define DDR_PHY_ACIOCR0_RESERVED_25_10_MASK 0x03FFFC00U -/*CK Duty Cycle Correction*/ +/* +* CK Duty Cycle Correction +*/ #undef DDR_PHY_ACIOCR0_CKDCC_DEFVAL #undef DDR_PHY_ACIOCR0_CKDCC_SHIFT #undef DDR_PHY_ACIOCR0_CKDCC_MASK -#define DDR_PHY_ACIOCR0_CKDCC_DEFVAL 0x30000000 -#define DDR_PHY_ACIOCR0_CKDCC_SHIFT 6 -#define DDR_PHY_ACIOCR0_CKDCC_MASK 0x000003C0U +#define DDR_PHY_ACIOCR0_CKDCC_DEFVAL 0x30000000 +#define DDR_PHY_ACIOCR0_CKDCC_SHIFT 6 +#define DDR_PHY_ACIOCR0_CKDCC_MASK 0x000003C0U -/*AC Power Down Receiver Mode*/ +/* +* AC Power Down Receiver Mode +*/ #undef DDR_PHY_ACIOCR0_ACPDRMODE_DEFVAL #undef DDR_PHY_ACIOCR0_ACPDRMODE_SHIFT #undef DDR_PHY_ACIOCR0_ACPDRMODE_MASK -#define DDR_PHY_ACIOCR0_ACPDRMODE_DEFVAL 0x30000000 -#define DDR_PHY_ACIOCR0_ACPDRMODE_SHIFT 4 -#define DDR_PHY_ACIOCR0_ACPDRMODE_MASK 0x00000030U +#define DDR_PHY_ACIOCR0_ACPDRMODE_DEFVAL 0x30000000 +#define DDR_PHY_ACIOCR0_ACPDRMODE_SHIFT 4 +#define DDR_PHY_ACIOCR0_ACPDRMODE_MASK 0x00000030U -/*AC On-die Termination Mode*/ +/* +* AC On-die Termination Mode +*/ #undef DDR_PHY_ACIOCR0_ACODTMODE_DEFVAL #undef DDR_PHY_ACIOCR0_ACODTMODE_SHIFT #undef DDR_PHY_ACIOCR0_ACODTMODE_MASK -#define DDR_PHY_ACIOCR0_ACODTMODE_DEFVAL 0x30000000 -#define DDR_PHY_ACIOCR0_ACODTMODE_SHIFT 2 -#define DDR_PHY_ACIOCR0_ACODTMODE_MASK 0x0000000CU +#define DDR_PHY_ACIOCR0_ACODTMODE_DEFVAL 0x30000000 +#define DDR_PHY_ACIOCR0_ACODTMODE_SHIFT 2 +#define DDR_PHY_ACIOCR0_ACODTMODE_MASK 0x0000000CU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACIOCR0_RESERVED_1_DEFVAL #undef DDR_PHY_ACIOCR0_RESERVED_1_SHIFT #undef DDR_PHY_ACIOCR0_RESERVED_1_MASK -#define DDR_PHY_ACIOCR0_RESERVED_1_DEFVAL 0x30000000 -#define DDR_PHY_ACIOCR0_RESERVED_1_SHIFT 1 -#define DDR_PHY_ACIOCR0_RESERVED_1_MASK 0x00000002U +#define DDR_PHY_ACIOCR0_RESERVED_1_DEFVAL 0x30000000 +#define DDR_PHY_ACIOCR0_RESERVED_1_SHIFT 1 +#define DDR_PHY_ACIOCR0_RESERVED_1_MASK 0x00000002U -/*Control delayed or non-delayed clock to CS_N/ODT?CKE AC slices.*/ +/* +* Control delayed or non-delayed clock to CS_N/ODT?CKE AC slices. +*/ #undef DDR_PHY_ACIOCR0_ACRANKCLKSEL_DEFVAL #undef DDR_PHY_ACIOCR0_ACRANKCLKSEL_SHIFT #undef DDR_PHY_ACIOCR0_ACRANKCLKSEL_MASK -#define DDR_PHY_ACIOCR0_ACRANKCLKSEL_DEFVAL 0x30000000 -#define DDR_PHY_ACIOCR0_ACRANKCLKSEL_SHIFT 0 -#define DDR_PHY_ACIOCR0_ACRANKCLKSEL_MASK 0x00000001U +#define DDR_PHY_ACIOCR0_ACRANKCLKSEL_DEFVAL 0x30000000 +#define DDR_PHY_ACIOCR0_ACRANKCLKSEL_SHIFT 0 +#define DDR_PHY_ACIOCR0_ACRANKCLKSEL_MASK 0x00000001U -/*Clock gating for glue logic inside CLKGEN and glue logic inside CONTROL slice*/ +/* +* Clock gating for glue logic inside CLKGEN and glue logic inside CONTROL + * slice +*/ #undef DDR_PHY_ACIOCR2_CLKGENCLKGATE_DEFVAL #undef DDR_PHY_ACIOCR2_CLKGENCLKGATE_SHIFT #undef DDR_PHY_ACIOCR2_CLKGENCLKGATE_MASK -#define DDR_PHY_ACIOCR2_CLKGENCLKGATE_DEFVAL 0x00000000 -#define DDR_PHY_ACIOCR2_CLKGENCLKGATE_SHIFT 31 -#define DDR_PHY_ACIOCR2_CLKGENCLKGATE_MASK 0x80000000U +#define DDR_PHY_ACIOCR2_CLKGENCLKGATE_DEFVAL 0x00000000 +#define DDR_PHY_ACIOCR2_CLKGENCLKGATE_SHIFT 31 +#define DDR_PHY_ACIOCR2_CLKGENCLKGATE_MASK 0x80000000U -/*Clock gating for Output Enable D slices [0]*/ +/* +* Clock gating for Output Enable D slices [0] +*/ #undef DDR_PHY_ACIOCR2_ACOECLKGATE0_DEFVAL #undef DDR_PHY_ACIOCR2_ACOECLKGATE0_SHIFT #undef DDR_PHY_ACIOCR2_ACOECLKGATE0_MASK -#define DDR_PHY_ACIOCR2_ACOECLKGATE0_DEFVAL 0x00000000 -#define DDR_PHY_ACIOCR2_ACOECLKGATE0_SHIFT 30 -#define DDR_PHY_ACIOCR2_ACOECLKGATE0_MASK 0x40000000U +#define DDR_PHY_ACIOCR2_ACOECLKGATE0_DEFVAL 0x00000000 +#define DDR_PHY_ACIOCR2_ACOECLKGATE0_SHIFT 30 +#define DDR_PHY_ACIOCR2_ACOECLKGATE0_MASK 0x40000000U -/*Clock gating for Power Down Receiver D slices [0]*/ +/* +* Clock gating for Power Down Receiver D slices [0] +*/ #undef DDR_PHY_ACIOCR2_ACPDRCLKGATE0_DEFVAL #undef DDR_PHY_ACIOCR2_ACPDRCLKGATE0_SHIFT #undef DDR_PHY_ACIOCR2_ACPDRCLKGATE0_MASK -#define DDR_PHY_ACIOCR2_ACPDRCLKGATE0_DEFVAL 0x00000000 -#define DDR_PHY_ACIOCR2_ACPDRCLKGATE0_SHIFT 29 -#define DDR_PHY_ACIOCR2_ACPDRCLKGATE0_MASK 0x20000000U +#define DDR_PHY_ACIOCR2_ACPDRCLKGATE0_DEFVAL 0x00000000 +#define DDR_PHY_ACIOCR2_ACPDRCLKGATE0_SHIFT 29 +#define DDR_PHY_ACIOCR2_ACPDRCLKGATE0_MASK 0x20000000U -/*Clock gating for Termination Enable D slices [0]*/ +/* +* Clock gating for Termination Enable D slices [0] +*/ #undef DDR_PHY_ACIOCR2_ACTECLKGATE0_DEFVAL #undef DDR_PHY_ACIOCR2_ACTECLKGATE0_SHIFT #undef DDR_PHY_ACIOCR2_ACTECLKGATE0_MASK -#define DDR_PHY_ACIOCR2_ACTECLKGATE0_DEFVAL 0x00000000 -#define DDR_PHY_ACIOCR2_ACTECLKGATE0_SHIFT 28 -#define DDR_PHY_ACIOCR2_ACTECLKGATE0_MASK 0x10000000U +#define DDR_PHY_ACIOCR2_ACTECLKGATE0_DEFVAL 0x00000000 +#define DDR_PHY_ACIOCR2_ACTECLKGATE0_SHIFT 28 +#define DDR_PHY_ACIOCR2_ACTECLKGATE0_MASK 0x10000000U -/*Clock gating for CK# D slices [1:0]*/ +/* +* Clock gating for CK# D slices [1:0] +*/ #undef DDR_PHY_ACIOCR2_CKNCLKGATE0_DEFVAL #undef DDR_PHY_ACIOCR2_CKNCLKGATE0_SHIFT #undef DDR_PHY_ACIOCR2_CKNCLKGATE0_MASK -#define DDR_PHY_ACIOCR2_CKNCLKGATE0_DEFVAL 0x00000000 -#define DDR_PHY_ACIOCR2_CKNCLKGATE0_SHIFT 26 -#define DDR_PHY_ACIOCR2_CKNCLKGATE0_MASK 0x0C000000U +#define DDR_PHY_ACIOCR2_CKNCLKGATE0_DEFVAL 0x00000000 +#define DDR_PHY_ACIOCR2_CKNCLKGATE0_SHIFT 26 +#define DDR_PHY_ACIOCR2_CKNCLKGATE0_MASK 0x0C000000U -/*Clock gating for CK D slices [1:0]*/ +/* +* Clock gating for CK D slices [1:0] +*/ #undef DDR_PHY_ACIOCR2_CKCLKGATE0_DEFVAL #undef DDR_PHY_ACIOCR2_CKCLKGATE0_SHIFT #undef DDR_PHY_ACIOCR2_CKCLKGATE0_MASK -#define DDR_PHY_ACIOCR2_CKCLKGATE0_DEFVAL 0x00000000 -#define DDR_PHY_ACIOCR2_CKCLKGATE0_SHIFT 24 -#define DDR_PHY_ACIOCR2_CKCLKGATE0_MASK 0x03000000U +#define DDR_PHY_ACIOCR2_CKCLKGATE0_DEFVAL 0x00000000 +#define DDR_PHY_ACIOCR2_CKCLKGATE0_SHIFT 24 +#define DDR_PHY_ACIOCR2_CKCLKGATE0_MASK 0x03000000U -/*Clock gating for AC D slices [23:0]*/ +/* +* Clock gating for AC D slices [23:0] +*/ #undef DDR_PHY_ACIOCR2_ACCLKGATE0_DEFVAL #undef DDR_PHY_ACIOCR2_ACCLKGATE0_SHIFT #undef DDR_PHY_ACIOCR2_ACCLKGATE0_MASK -#define DDR_PHY_ACIOCR2_ACCLKGATE0_DEFVAL 0x00000000 -#define DDR_PHY_ACIOCR2_ACCLKGATE0_SHIFT 0 -#define DDR_PHY_ACIOCR2_ACCLKGATE0_MASK 0x00FFFFFFU +#define DDR_PHY_ACIOCR2_ACCLKGATE0_DEFVAL 0x00000000 +#define DDR_PHY_ACIOCR2_ACCLKGATE0_SHIFT 0 +#define DDR_PHY_ACIOCR2_ACCLKGATE0_MASK 0x00FFFFFFU -/*SDRAM Parity Output Enable (OE) Mode Selection*/ +/* +* SDRAM Parity Output Enable (OE) Mode Selection +*/ #undef DDR_PHY_ACIOCR3_PAROEMODE_DEFVAL #undef DDR_PHY_ACIOCR3_PAROEMODE_SHIFT #undef DDR_PHY_ACIOCR3_PAROEMODE_MASK -#define DDR_PHY_ACIOCR3_PAROEMODE_DEFVAL 0x00000005 -#define DDR_PHY_ACIOCR3_PAROEMODE_SHIFT 30 -#define DDR_PHY_ACIOCR3_PAROEMODE_MASK 0xC0000000U +#define DDR_PHY_ACIOCR3_PAROEMODE_DEFVAL 0x00000005 +#define DDR_PHY_ACIOCR3_PAROEMODE_SHIFT 30 +#define DDR_PHY_ACIOCR3_PAROEMODE_MASK 0xC0000000U -/*SDRAM Bank Group Output Enable (OE) Mode Selection*/ +/* +* SDRAM Bank Group Output Enable (OE) Mode Selection +*/ #undef DDR_PHY_ACIOCR3_BGOEMODE_DEFVAL #undef DDR_PHY_ACIOCR3_BGOEMODE_SHIFT #undef DDR_PHY_ACIOCR3_BGOEMODE_MASK -#define DDR_PHY_ACIOCR3_BGOEMODE_DEFVAL 0x00000005 -#define DDR_PHY_ACIOCR3_BGOEMODE_SHIFT 26 -#define DDR_PHY_ACIOCR3_BGOEMODE_MASK 0x3C000000U +#define DDR_PHY_ACIOCR3_BGOEMODE_DEFVAL 0x00000005 +#define DDR_PHY_ACIOCR3_BGOEMODE_SHIFT 26 +#define DDR_PHY_ACIOCR3_BGOEMODE_MASK 0x3C000000U -/*SDRAM Bank Address Output Enable (OE) Mode Selection*/ +/* +* SDRAM Bank Address Output Enable (OE) Mode Selection +*/ #undef DDR_PHY_ACIOCR3_BAOEMODE_DEFVAL #undef DDR_PHY_ACIOCR3_BAOEMODE_SHIFT #undef DDR_PHY_ACIOCR3_BAOEMODE_MASK -#define DDR_PHY_ACIOCR3_BAOEMODE_DEFVAL 0x00000005 -#define DDR_PHY_ACIOCR3_BAOEMODE_SHIFT 22 -#define DDR_PHY_ACIOCR3_BAOEMODE_MASK 0x03C00000U +#define DDR_PHY_ACIOCR3_BAOEMODE_DEFVAL 0x00000005 +#define DDR_PHY_ACIOCR3_BAOEMODE_SHIFT 22 +#define DDR_PHY_ACIOCR3_BAOEMODE_MASK 0x03C00000U -/*SDRAM A[17] Output Enable (OE) Mode Selection*/ +/* +* SDRAM A[17] Output Enable (OE) Mode Selection +*/ #undef DDR_PHY_ACIOCR3_A17OEMODE_DEFVAL #undef DDR_PHY_ACIOCR3_A17OEMODE_SHIFT #undef DDR_PHY_ACIOCR3_A17OEMODE_MASK -#define DDR_PHY_ACIOCR3_A17OEMODE_DEFVAL 0x00000005 -#define DDR_PHY_ACIOCR3_A17OEMODE_SHIFT 20 -#define DDR_PHY_ACIOCR3_A17OEMODE_MASK 0x00300000U +#define DDR_PHY_ACIOCR3_A17OEMODE_DEFVAL 0x00000005 +#define DDR_PHY_ACIOCR3_A17OEMODE_SHIFT 20 +#define DDR_PHY_ACIOCR3_A17OEMODE_MASK 0x00300000U -/*SDRAM A[16] / RAS_n Output Enable (OE) Mode Selection*/ +/* +* SDRAM A[16] / RAS_n Output Enable (OE) Mode Selection +*/ #undef DDR_PHY_ACIOCR3_A16OEMODE_DEFVAL #undef DDR_PHY_ACIOCR3_A16OEMODE_SHIFT #undef DDR_PHY_ACIOCR3_A16OEMODE_MASK -#define DDR_PHY_ACIOCR3_A16OEMODE_DEFVAL 0x00000005 -#define DDR_PHY_ACIOCR3_A16OEMODE_SHIFT 18 -#define DDR_PHY_ACIOCR3_A16OEMODE_MASK 0x000C0000U +#define DDR_PHY_ACIOCR3_A16OEMODE_DEFVAL 0x00000005 +#define DDR_PHY_ACIOCR3_A16OEMODE_SHIFT 18 +#define DDR_PHY_ACIOCR3_A16OEMODE_MASK 0x000C0000U -/*SDRAM ACT_n Output Enable (OE) Mode Selection (DDR4 only)*/ +/* +* SDRAM ACT_n Output Enable (OE) Mode Selection (DDR4 only) +*/ #undef DDR_PHY_ACIOCR3_ACTOEMODE_DEFVAL #undef DDR_PHY_ACIOCR3_ACTOEMODE_SHIFT #undef DDR_PHY_ACIOCR3_ACTOEMODE_MASK -#define DDR_PHY_ACIOCR3_ACTOEMODE_DEFVAL 0x00000005 -#define DDR_PHY_ACIOCR3_ACTOEMODE_SHIFT 16 -#define DDR_PHY_ACIOCR3_ACTOEMODE_MASK 0x00030000U +#define DDR_PHY_ACIOCR3_ACTOEMODE_DEFVAL 0x00000005 +#define DDR_PHY_ACIOCR3_ACTOEMODE_SHIFT 16 +#define DDR_PHY_ACIOCR3_ACTOEMODE_MASK 0x00030000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACIOCR3_RESERVED_15_8_DEFVAL #undef DDR_PHY_ACIOCR3_RESERVED_15_8_SHIFT #undef DDR_PHY_ACIOCR3_RESERVED_15_8_MASK -#define DDR_PHY_ACIOCR3_RESERVED_15_8_DEFVAL 0x00000005 -#define DDR_PHY_ACIOCR3_RESERVED_15_8_SHIFT 8 -#define DDR_PHY_ACIOCR3_RESERVED_15_8_MASK 0x0000FF00U +#define DDR_PHY_ACIOCR3_RESERVED_15_8_DEFVAL 0x00000005 +#define DDR_PHY_ACIOCR3_RESERVED_15_8_SHIFT 8 +#define DDR_PHY_ACIOCR3_RESERVED_15_8_MASK 0x0000FF00U -/*Reserved. Return zeros on reads.*/ +/* +* Reserved. Return zeros on reads. +*/ #undef DDR_PHY_ACIOCR3_CKOEMODE_RSVD_DEFVAL #undef DDR_PHY_ACIOCR3_CKOEMODE_RSVD_SHIFT #undef DDR_PHY_ACIOCR3_CKOEMODE_RSVD_MASK -#define DDR_PHY_ACIOCR3_CKOEMODE_RSVD_DEFVAL 0x00000005 -#define DDR_PHY_ACIOCR3_CKOEMODE_RSVD_SHIFT 4 -#define DDR_PHY_ACIOCR3_CKOEMODE_RSVD_MASK 0x000000F0U +#define DDR_PHY_ACIOCR3_CKOEMODE_RSVD_DEFVAL 0x00000005 +#define DDR_PHY_ACIOCR3_CKOEMODE_RSVD_SHIFT 4 +#define DDR_PHY_ACIOCR3_CKOEMODE_RSVD_MASK 0x000000F0U -/*SDRAM CK Output Enable (OE) Mode Selection.*/ +/* +* SDRAM CK Output Enable (OE) Mode Selection. +*/ #undef DDR_PHY_ACIOCR3_CKOEMODE_DEFVAL #undef DDR_PHY_ACIOCR3_CKOEMODE_SHIFT #undef DDR_PHY_ACIOCR3_CKOEMODE_MASK -#define DDR_PHY_ACIOCR3_CKOEMODE_DEFVAL 0x00000005 -#define DDR_PHY_ACIOCR3_CKOEMODE_SHIFT 0 -#define DDR_PHY_ACIOCR3_CKOEMODE_MASK 0x0000000FU +#define DDR_PHY_ACIOCR3_CKOEMODE_DEFVAL 0x00000005 +#define DDR_PHY_ACIOCR3_CKOEMODE_SHIFT 0 +#define DDR_PHY_ACIOCR3_CKOEMODE_MASK 0x0000000FU -/*Clock gating for AC LB slices and loopback read valid slices*/ +/* +* Clock gating for AC LB slices and loopback read valid slices +*/ #undef DDR_PHY_ACIOCR4_LBCLKGATE_DEFVAL #undef DDR_PHY_ACIOCR4_LBCLKGATE_SHIFT #undef DDR_PHY_ACIOCR4_LBCLKGATE_MASK -#define DDR_PHY_ACIOCR4_LBCLKGATE_DEFVAL 0x00000000 -#define DDR_PHY_ACIOCR4_LBCLKGATE_SHIFT 31 -#define DDR_PHY_ACIOCR4_LBCLKGATE_MASK 0x80000000U +#define DDR_PHY_ACIOCR4_LBCLKGATE_DEFVAL 0x00000000 +#define DDR_PHY_ACIOCR4_LBCLKGATE_SHIFT 31 +#define DDR_PHY_ACIOCR4_LBCLKGATE_MASK 0x80000000U -/*Clock gating for Output Enable D slices [1]*/ +/* +* Clock gating for Output Enable D slices [1] +*/ #undef DDR_PHY_ACIOCR4_ACOECLKGATE1_DEFVAL #undef DDR_PHY_ACIOCR4_ACOECLKGATE1_SHIFT #undef DDR_PHY_ACIOCR4_ACOECLKGATE1_MASK -#define DDR_PHY_ACIOCR4_ACOECLKGATE1_DEFVAL 0x00000000 -#define DDR_PHY_ACIOCR4_ACOECLKGATE1_SHIFT 30 -#define DDR_PHY_ACIOCR4_ACOECLKGATE1_MASK 0x40000000U +#define DDR_PHY_ACIOCR4_ACOECLKGATE1_DEFVAL 0x00000000 +#define DDR_PHY_ACIOCR4_ACOECLKGATE1_SHIFT 30 +#define DDR_PHY_ACIOCR4_ACOECLKGATE1_MASK 0x40000000U -/*Clock gating for Power Down Receiver D slices [1]*/ +/* +* Clock gating for Power Down Receiver D slices [1] +*/ #undef DDR_PHY_ACIOCR4_ACPDRCLKGATE1_DEFVAL #undef DDR_PHY_ACIOCR4_ACPDRCLKGATE1_SHIFT #undef DDR_PHY_ACIOCR4_ACPDRCLKGATE1_MASK -#define DDR_PHY_ACIOCR4_ACPDRCLKGATE1_DEFVAL 0x00000000 -#define DDR_PHY_ACIOCR4_ACPDRCLKGATE1_SHIFT 29 -#define DDR_PHY_ACIOCR4_ACPDRCLKGATE1_MASK 0x20000000U +#define DDR_PHY_ACIOCR4_ACPDRCLKGATE1_DEFVAL 0x00000000 +#define DDR_PHY_ACIOCR4_ACPDRCLKGATE1_SHIFT 29 +#define DDR_PHY_ACIOCR4_ACPDRCLKGATE1_MASK 0x20000000U -/*Clock gating for Termination Enable D slices [1]*/ +/* +* Clock gating for Termination Enable D slices [1] +*/ #undef DDR_PHY_ACIOCR4_ACTECLKGATE1_DEFVAL #undef DDR_PHY_ACIOCR4_ACTECLKGATE1_SHIFT #undef DDR_PHY_ACIOCR4_ACTECLKGATE1_MASK -#define DDR_PHY_ACIOCR4_ACTECLKGATE1_DEFVAL 0x00000000 -#define DDR_PHY_ACIOCR4_ACTECLKGATE1_SHIFT 28 -#define DDR_PHY_ACIOCR4_ACTECLKGATE1_MASK 0x10000000U +#define DDR_PHY_ACIOCR4_ACTECLKGATE1_DEFVAL 0x00000000 +#define DDR_PHY_ACIOCR4_ACTECLKGATE1_SHIFT 28 +#define DDR_PHY_ACIOCR4_ACTECLKGATE1_MASK 0x10000000U -/*Clock gating for CK# D slices [3:2]*/ +/* +* Clock gating for CK# D slices [3:2] +*/ #undef DDR_PHY_ACIOCR4_CKNCLKGATE1_DEFVAL #undef DDR_PHY_ACIOCR4_CKNCLKGATE1_SHIFT #undef DDR_PHY_ACIOCR4_CKNCLKGATE1_MASK -#define DDR_PHY_ACIOCR4_CKNCLKGATE1_DEFVAL 0x00000000 -#define DDR_PHY_ACIOCR4_CKNCLKGATE1_SHIFT 26 -#define DDR_PHY_ACIOCR4_CKNCLKGATE1_MASK 0x0C000000U +#define DDR_PHY_ACIOCR4_CKNCLKGATE1_DEFVAL 0x00000000 +#define DDR_PHY_ACIOCR4_CKNCLKGATE1_SHIFT 26 +#define DDR_PHY_ACIOCR4_CKNCLKGATE1_MASK 0x0C000000U -/*Clock gating for CK D slices [3:2]*/ +/* +* Clock gating for CK D slices [3:2] +*/ #undef DDR_PHY_ACIOCR4_CKCLKGATE1_DEFVAL #undef DDR_PHY_ACIOCR4_CKCLKGATE1_SHIFT #undef DDR_PHY_ACIOCR4_CKCLKGATE1_MASK -#define DDR_PHY_ACIOCR4_CKCLKGATE1_DEFVAL 0x00000000 -#define DDR_PHY_ACIOCR4_CKCLKGATE1_SHIFT 24 -#define DDR_PHY_ACIOCR4_CKCLKGATE1_MASK 0x03000000U +#define DDR_PHY_ACIOCR4_CKCLKGATE1_DEFVAL 0x00000000 +#define DDR_PHY_ACIOCR4_CKCLKGATE1_SHIFT 24 +#define DDR_PHY_ACIOCR4_CKCLKGATE1_MASK 0x03000000U -/*Clock gating for AC D slices [47:24]*/ +/* +* Clock gating for AC D slices [47:24] +*/ #undef DDR_PHY_ACIOCR4_ACCLKGATE1_DEFVAL #undef DDR_PHY_ACIOCR4_ACCLKGATE1_SHIFT #undef DDR_PHY_ACIOCR4_ACCLKGATE1_MASK -#define DDR_PHY_ACIOCR4_ACCLKGATE1_DEFVAL 0x00000000 -#define DDR_PHY_ACIOCR4_ACCLKGATE1_SHIFT 0 -#define DDR_PHY_ACIOCR4_ACCLKGATE1_MASK 0x00FFFFFFU +#define DDR_PHY_ACIOCR4_ACCLKGATE1_DEFVAL 0x00000000 +#define DDR_PHY_ACIOCR4_ACCLKGATE1_SHIFT 0 +#define DDR_PHY_ACIOCR4_ACCLKGATE1_MASK 0x00FFFFFFU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_IOVCR0_RESERVED_31_29_DEFVAL #undef DDR_PHY_IOVCR0_RESERVED_31_29_SHIFT #undef DDR_PHY_IOVCR0_RESERVED_31_29_MASK -#define DDR_PHY_IOVCR0_RESERVED_31_29_DEFVAL 0x0F000000 -#define DDR_PHY_IOVCR0_RESERVED_31_29_SHIFT 29 -#define DDR_PHY_IOVCR0_RESERVED_31_29_MASK 0xE0000000U +#define DDR_PHY_IOVCR0_RESERVED_31_29_DEFVAL 0x0F000000 +#define DDR_PHY_IOVCR0_RESERVED_31_29_SHIFT 29 +#define DDR_PHY_IOVCR0_RESERVED_31_29_MASK 0xE0000000U -/*Address/command lane VREF Pad Enable*/ +/* +* Address/command lane VREF Pad Enable +*/ #undef DDR_PHY_IOVCR0_ACREFPEN_DEFVAL #undef DDR_PHY_IOVCR0_ACREFPEN_SHIFT #undef DDR_PHY_IOVCR0_ACREFPEN_MASK -#define DDR_PHY_IOVCR0_ACREFPEN_DEFVAL 0x0F000000 -#define DDR_PHY_IOVCR0_ACREFPEN_SHIFT 28 -#define DDR_PHY_IOVCR0_ACREFPEN_MASK 0x10000000U +#define DDR_PHY_IOVCR0_ACREFPEN_DEFVAL 0x0F000000 +#define DDR_PHY_IOVCR0_ACREFPEN_SHIFT 28 +#define DDR_PHY_IOVCR0_ACREFPEN_MASK 0x10000000U -/*Address/command lane Internal VREF Enable*/ +/* +* Address/command lane Internal VREF Enable +*/ #undef DDR_PHY_IOVCR0_ACREFEEN_DEFVAL #undef DDR_PHY_IOVCR0_ACREFEEN_SHIFT #undef DDR_PHY_IOVCR0_ACREFEEN_MASK -#define DDR_PHY_IOVCR0_ACREFEEN_DEFVAL 0x0F000000 -#define DDR_PHY_IOVCR0_ACREFEEN_SHIFT 26 -#define DDR_PHY_IOVCR0_ACREFEEN_MASK 0x0C000000U +#define DDR_PHY_IOVCR0_ACREFEEN_DEFVAL 0x0F000000 +#define DDR_PHY_IOVCR0_ACREFEEN_SHIFT 26 +#define DDR_PHY_IOVCR0_ACREFEEN_MASK 0x0C000000U -/*Address/command lane Single-End VREF Enable*/ +/* +* Address/command lane Single-End VREF Enable +*/ #undef DDR_PHY_IOVCR0_ACREFSEN_DEFVAL #undef DDR_PHY_IOVCR0_ACREFSEN_SHIFT #undef DDR_PHY_IOVCR0_ACREFSEN_MASK -#define DDR_PHY_IOVCR0_ACREFSEN_DEFVAL 0x0F000000 -#define DDR_PHY_IOVCR0_ACREFSEN_SHIFT 25 -#define DDR_PHY_IOVCR0_ACREFSEN_MASK 0x02000000U +#define DDR_PHY_IOVCR0_ACREFSEN_DEFVAL 0x0F000000 +#define DDR_PHY_IOVCR0_ACREFSEN_SHIFT 25 +#define DDR_PHY_IOVCR0_ACREFSEN_MASK 0x02000000U -/*Address/command lane Internal VREF Enable*/ +/* +* Address/command lane Internal VREF Enable +*/ #undef DDR_PHY_IOVCR0_ACREFIEN_DEFVAL #undef DDR_PHY_IOVCR0_ACREFIEN_SHIFT #undef DDR_PHY_IOVCR0_ACREFIEN_MASK -#define DDR_PHY_IOVCR0_ACREFIEN_DEFVAL 0x0F000000 -#define DDR_PHY_IOVCR0_ACREFIEN_SHIFT 24 -#define DDR_PHY_IOVCR0_ACREFIEN_MASK 0x01000000U +#define DDR_PHY_IOVCR0_ACREFIEN_DEFVAL 0x0F000000 +#define DDR_PHY_IOVCR0_ACREFIEN_SHIFT 24 +#define DDR_PHY_IOVCR0_ACREFIEN_MASK 0x01000000U -/*External VREF generato REFSEL range select*/ +/* +* External VREF generato REFSEL range select +*/ #undef DDR_PHY_IOVCR0_ACREFESELRANGE_DEFVAL #undef DDR_PHY_IOVCR0_ACREFESELRANGE_SHIFT #undef DDR_PHY_IOVCR0_ACREFESELRANGE_MASK -#define DDR_PHY_IOVCR0_ACREFESELRANGE_DEFVAL 0x0F000000 -#define DDR_PHY_IOVCR0_ACREFESELRANGE_SHIFT 23 -#define DDR_PHY_IOVCR0_ACREFESELRANGE_MASK 0x00800000U +#define DDR_PHY_IOVCR0_ACREFESELRANGE_DEFVAL 0x0F000000 +#define DDR_PHY_IOVCR0_ACREFESELRANGE_SHIFT 23 +#define DDR_PHY_IOVCR0_ACREFESELRANGE_MASK 0x00800000U -/*Address/command lane External VREF Select*/ +/* +* Address/command lane External VREF Select +*/ #undef DDR_PHY_IOVCR0_ACREFESEL_DEFVAL #undef DDR_PHY_IOVCR0_ACREFESEL_SHIFT #undef DDR_PHY_IOVCR0_ACREFESEL_MASK -#define DDR_PHY_IOVCR0_ACREFESEL_DEFVAL 0x0F000000 -#define DDR_PHY_IOVCR0_ACREFESEL_SHIFT 16 -#define DDR_PHY_IOVCR0_ACREFESEL_MASK 0x007F0000U +#define DDR_PHY_IOVCR0_ACREFESEL_DEFVAL 0x0F000000 +#define DDR_PHY_IOVCR0_ACREFESEL_SHIFT 16 +#define DDR_PHY_IOVCR0_ACREFESEL_MASK 0x007F0000U -/*Single ended VREF generator REFSEL range select*/ +/* +* Single ended VREF generator REFSEL range select +*/ #undef DDR_PHY_IOVCR0_ACREFSSELRANGE_DEFVAL #undef DDR_PHY_IOVCR0_ACREFSSELRANGE_SHIFT #undef DDR_PHY_IOVCR0_ACREFSSELRANGE_MASK -#define DDR_PHY_IOVCR0_ACREFSSELRANGE_DEFVAL 0x0F000000 -#define DDR_PHY_IOVCR0_ACREFSSELRANGE_SHIFT 15 -#define DDR_PHY_IOVCR0_ACREFSSELRANGE_MASK 0x00008000U +#define DDR_PHY_IOVCR0_ACREFSSELRANGE_DEFVAL 0x0F000000 +#define DDR_PHY_IOVCR0_ACREFSSELRANGE_SHIFT 15 +#define DDR_PHY_IOVCR0_ACREFSSELRANGE_MASK 0x00008000U -/*Address/command lane Single-End VREF Select*/ +/* +* Address/command lane Single-End VREF Select +*/ #undef DDR_PHY_IOVCR0_ACREFSSEL_DEFVAL #undef DDR_PHY_IOVCR0_ACREFSSEL_SHIFT #undef DDR_PHY_IOVCR0_ACREFSSEL_MASK -#define DDR_PHY_IOVCR0_ACREFSSEL_DEFVAL 0x0F000000 -#define DDR_PHY_IOVCR0_ACREFSSEL_SHIFT 8 -#define DDR_PHY_IOVCR0_ACREFSSEL_MASK 0x00007F00U +#define DDR_PHY_IOVCR0_ACREFSSEL_DEFVAL 0x0F000000 +#define DDR_PHY_IOVCR0_ACREFSSEL_SHIFT 8 +#define DDR_PHY_IOVCR0_ACREFSSEL_MASK 0x00007F00U -/*Internal VREF generator REFSEL ragne select*/ +/* +* Internal VREF generator REFSEL ragne select +*/ #undef DDR_PHY_IOVCR0_ACVREFISELRANGE_DEFVAL #undef DDR_PHY_IOVCR0_ACVREFISELRANGE_SHIFT #undef DDR_PHY_IOVCR0_ACVREFISELRANGE_MASK -#define DDR_PHY_IOVCR0_ACVREFISELRANGE_DEFVAL 0x0F000000 -#define DDR_PHY_IOVCR0_ACVREFISELRANGE_SHIFT 7 -#define DDR_PHY_IOVCR0_ACVREFISELRANGE_MASK 0x00000080U +#define DDR_PHY_IOVCR0_ACVREFISELRANGE_DEFVAL 0x0F000000 +#define DDR_PHY_IOVCR0_ACVREFISELRANGE_SHIFT 7 +#define DDR_PHY_IOVCR0_ACVREFISELRANGE_MASK 0x00000080U -/*REFSEL Control for internal AC IOs*/ +/* +* REFSEL Control for internal AC IOs +*/ #undef DDR_PHY_IOVCR0_ACVREFISEL_DEFVAL #undef DDR_PHY_IOVCR0_ACVREFISEL_SHIFT #undef DDR_PHY_IOVCR0_ACVREFISEL_MASK -#define DDR_PHY_IOVCR0_ACVREFISEL_DEFVAL 0x0F000000 -#define DDR_PHY_IOVCR0_ACVREFISEL_SHIFT 0 -#define DDR_PHY_IOVCR0_ACVREFISEL_MASK 0x0000007FU +#define DDR_PHY_IOVCR0_ACVREFISEL_DEFVAL 0x0F000000 +#define DDR_PHY_IOVCR0_ACVREFISEL_SHIFT 0 +#define DDR_PHY_IOVCR0_ACVREFISEL_MASK 0x0000007FU -/*Number of ctl_clk required to meet (> 150ns) timing requirements during DRAM DQ VREF training*/ +/* +* Number of ctl_clk required to meet (> 150ns) timing requirements during + * DRAM DQ VREF training +*/ #undef DDR_PHY_VTCR0_TVREF_DEFVAL #undef DDR_PHY_VTCR0_TVREF_SHIFT #undef DDR_PHY_VTCR0_TVREF_MASK -#define DDR_PHY_VTCR0_TVREF_DEFVAL 0x70032019 -#define DDR_PHY_VTCR0_TVREF_SHIFT 29 -#define DDR_PHY_VTCR0_TVREF_MASK 0xE0000000U +#define DDR_PHY_VTCR0_TVREF_DEFVAL 0x70032019 +#define DDR_PHY_VTCR0_TVREF_SHIFT 29 +#define DDR_PHY_VTCR0_TVREF_MASK 0xE0000000U -/*DRM DQ VREF training Enable*/ +/* +* DRM DQ VREF training Enable +*/ #undef DDR_PHY_VTCR0_DVEN_DEFVAL #undef DDR_PHY_VTCR0_DVEN_SHIFT #undef DDR_PHY_VTCR0_DVEN_MASK -#define DDR_PHY_VTCR0_DVEN_DEFVAL 0x70032019 -#define DDR_PHY_VTCR0_DVEN_SHIFT 28 -#define DDR_PHY_VTCR0_DVEN_MASK 0x10000000U +#define DDR_PHY_VTCR0_DVEN_DEFVAL 0x70032019 +#define DDR_PHY_VTCR0_DVEN_SHIFT 28 +#define DDR_PHY_VTCR0_DVEN_MASK 0x10000000U -/*Per Device Addressability Enable*/ +/* +* Per Device Addressability Enable +*/ #undef DDR_PHY_VTCR0_PDAEN_DEFVAL #undef DDR_PHY_VTCR0_PDAEN_SHIFT #undef DDR_PHY_VTCR0_PDAEN_MASK -#define DDR_PHY_VTCR0_PDAEN_DEFVAL 0x70032019 -#define DDR_PHY_VTCR0_PDAEN_SHIFT 27 -#define DDR_PHY_VTCR0_PDAEN_MASK 0x08000000U +#define DDR_PHY_VTCR0_PDAEN_DEFVAL 0x70032019 +#define DDR_PHY_VTCR0_PDAEN_SHIFT 27 +#define DDR_PHY_VTCR0_PDAEN_MASK 0x08000000U -/*Reserved. Returns zeroes on reads.*/ +/* +* Reserved. Returns zeroes on reads. +*/ #undef DDR_PHY_VTCR0_RESERVED_26_DEFVAL #undef DDR_PHY_VTCR0_RESERVED_26_SHIFT #undef DDR_PHY_VTCR0_RESERVED_26_MASK -#define DDR_PHY_VTCR0_RESERVED_26_DEFVAL 0x70032019 -#define DDR_PHY_VTCR0_RESERVED_26_SHIFT 26 -#define DDR_PHY_VTCR0_RESERVED_26_MASK 0x04000000U +#define DDR_PHY_VTCR0_RESERVED_26_DEFVAL 0x70032019 +#define DDR_PHY_VTCR0_RESERVED_26_SHIFT 26 +#define DDR_PHY_VTCR0_RESERVED_26_MASK 0x04000000U -/*VREF Word Count*/ +/* +* VREF Word Count +*/ #undef DDR_PHY_VTCR0_VWCR_DEFVAL #undef DDR_PHY_VTCR0_VWCR_SHIFT #undef DDR_PHY_VTCR0_VWCR_MASK -#define DDR_PHY_VTCR0_VWCR_DEFVAL 0x70032019 -#define DDR_PHY_VTCR0_VWCR_SHIFT 22 -#define DDR_PHY_VTCR0_VWCR_MASK 0x03C00000U +#define DDR_PHY_VTCR0_VWCR_DEFVAL 0x70032019 +#define DDR_PHY_VTCR0_VWCR_SHIFT 22 +#define DDR_PHY_VTCR0_VWCR_MASK 0x03C00000U -/*DRAM DQ VREF step size used during DRAM VREF training*/ +/* +* DRAM DQ VREF step size used during DRAM VREF training +*/ #undef DDR_PHY_VTCR0_DVSS_DEFVAL #undef DDR_PHY_VTCR0_DVSS_SHIFT #undef DDR_PHY_VTCR0_DVSS_MASK -#define DDR_PHY_VTCR0_DVSS_DEFVAL 0x70032019 -#define DDR_PHY_VTCR0_DVSS_SHIFT 18 -#define DDR_PHY_VTCR0_DVSS_MASK 0x003C0000U +#define DDR_PHY_VTCR0_DVSS_DEFVAL 0x70032019 +#define DDR_PHY_VTCR0_DVSS_SHIFT 18 +#define DDR_PHY_VTCR0_DVSS_MASK 0x003C0000U -/*Maximum VREF limit value used during DRAM VREF training*/ +/* +* Maximum VREF limit value used during DRAM VREF training +*/ #undef DDR_PHY_VTCR0_DVMAX_DEFVAL #undef DDR_PHY_VTCR0_DVMAX_SHIFT #undef DDR_PHY_VTCR0_DVMAX_MASK -#define DDR_PHY_VTCR0_DVMAX_DEFVAL 0x70032019 -#define DDR_PHY_VTCR0_DVMAX_SHIFT 12 -#define DDR_PHY_VTCR0_DVMAX_MASK 0x0003F000U +#define DDR_PHY_VTCR0_DVMAX_DEFVAL 0x70032019 +#define DDR_PHY_VTCR0_DVMAX_SHIFT 12 +#define DDR_PHY_VTCR0_DVMAX_MASK 0x0003F000U -/*Minimum VREF limit value used during DRAM VREF training*/ +/* +* Minimum VREF limit value used during DRAM VREF training +*/ #undef DDR_PHY_VTCR0_DVMIN_DEFVAL #undef DDR_PHY_VTCR0_DVMIN_SHIFT #undef DDR_PHY_VTCR0_DVMIN_MASK -#define DDR_PHY_VTCR0_DVMIN_DEFVAL 0x70032019 -#define DDR_PHY_VTCR0_DVMIN_SHIFT 6 -#define DDR_PHY_VTCR0_DVMIN_MASK 0x00000FC0U +#define DDR_PHY_VTCR0_DVMIN_DEFVAL 0x70032019 +#define DDR_PHY_VTCR0_DVMIN_SHIFT 6 +#define DDR_PHY_VTCR0_DVMIN_MASK 0x00000FC0U -/*Initial DRAM DQ VREF value used during DRAM VREF training*/ +/* +* Initial DRAM DQ VREF value used during DRAM VREF training +*/ #undef DDR_PHY_VTCR0_DVINIT_DEFVAL #undef DDR_PHY_VTCR0_DVINIT_SHIFT #undef DDR_PHY_VTCR0_DVINIT_MASK -#define DDR_PHY_VTCR0_DVINIT_DEFVAL 0x70032019 -#define DDR_PHY_VTCR0_DVINIT_SHIFT 0 -#define DDR_PHY_VTCR0_DVINIT_MASK 0x0000003FU +#define DDR_PHY_VTCR0_DVINIT_DEFVAL 0x70032019 +#define DDR_PHY_VTCR0_DVINIT_SHIFT 0 +#define DDR_PHY_VTCR0_DVINIT_MASK 0x0000003FU -/*Host VREF step size used during VREF training. The register value of N indicates step size of (N+1)*/ +/* +* Host VREF step size used during VREF training. The register value of N i + * ndicates step size of (N+1) +*/ #undef DDR_PHY_VTCR1_HVSS_DEFVAL #undef DDR_PHY_VTCR1_HVSS_SHIFT #undef DDR_PHY_VTCR1_HVSS_MASK -#define DDR_PHY_VTCR1_HVSS_DEFVAL 0x07F00072 -#define DDR_PHY_VTCR1_HVSS_SHIFT 28 -#define DDR_PHY_VTCR1_HVSS_MASK 0xF0000000U +#define DDR_PHY_VTCR1_HVSS_DEFVAL 0x07F00072 +#define DDR_PHY_VTCR1_HVSS_SHIFT 28 +#define DDR_PHY_VTCR1_HVSS_MASK 0xF0000000U -/*Reserved. Returns zeroes on reads.*/ +/* +* Reserved. Returns zeroes on reads. +*/ #undef DDR_PHY_VTCR1_RESERVED_27_DEFVAL #undef DDR_PHY_VTCR1_RESERVED_27_SHIFT #undef DDR_PHY_VTCR1_RESERVED_27_MASK -#define DDR_PHY_VTCR1_RESERVED_27_DEFVAL 0x07F00072 -#define DDR_PHY_VTCR1_RESERVED_27_SHIFT 27 -#define DDR_PHY_VTCR1_RESERVED_27_MASK 0x08000000U +#define DDR_PHY_VTCR1_RESERVED_27_DEFVAL 0x07F00072 +#define DDR_PHY_VTCR1_RESERVED_27_SHIFT 27 +#define DDR_PHY_VTCR1_RESERVED_27_MASK 0x08000000U -/*Maximum VREF limit value used during DRAM VREF training.*/ +/* +* Maximum VREF limit value used during DRAM VREF training. +*/ #undef DDR_PHY_VTCR1_HVMAX_DEFVAL #undef DDR_PHY_VTCR1_HVMAX_SHIFT #undef DDR_PHY_VTCR1_HVMAX_MASK -#define DDR_PHY_VTCR1_HVMAX_DEFVAL 0x07F00072 -#define DDR_PHY_VTCR1_HVMAX_SHIFT 20 -#define DDR_PHY_VTCR1_HVMAX_MASK 0x07F00000U +#define DDR_PHY_VTCR1_HVMAX_DEFVAL 0x07F00072 +#define DDR_PHY_VTCR1_HVMAX_SHIFT 20 +#define DDR_PHY_VTCR1_HVMAX_MASK 0x07F00000U -/*Reserved. Returns zeroes on reads.*/ +/* +* Reserved. Returns zeroes on reads. +*/ #undef DDR_PHY_VTCR1_RESERVED_19_DEFVAL #undef DDR_PHY_VTCR1_RESERVED_19_SHIFT #undef DDR_PHY_VTCR1_RESERVED_19_MASK -#define DDR_PHY_VTCR1_RESERVED_19_DEFVAL 0x07F00072 -#define DDR_PHY_VTCR1_RESERVED_19_SHIFT 19 -#define DDR_PHY_VTCR1_RESERVED_19_MASK 0x00080000U +#define DDR_PHY_VTCR1_RESERVED_19_DEFVAL 0x07F00072 +#define DDR_PHY_VTCR1_RESERVED_19_SHIFT 19 +#define DDR_PHY_VTCR1_RESERVED_19_MASK 0x00080000U -/*Minimum VREF limit value used during DRAM VREF training.*/ +/* +* Minimum VREF limit value used during DRAM VREF training. +*/ #undef DDR_PHY_VTCR1_HVMIN_DEFVAL #undef DDR_PHY_VTCR1_HVMIN_SHIFT #undef DDR_PHY_VTCR1_HVMIN_MASK -#define DDR_PHY_VTCR1_HVMIN_DEFVAL 0x07F00072 -#define DDR_PHY_VTCR1_HVMIN_SHIFT 12 -#define DDR_PHY_VTCR1_HVMIN_MASK 0x0007F000U +#define DDR_PHY_VTCR1_HVMIN_DEFVAL 0x07F00072 +#define DDR_PHY_VTCR1_HVMIN_SHIFT 12 +#define DDR_PHY_VTCR1_HVMIN_MASK 0x0007F000U -/*Reserved. Returns zeroes on reads.*/ +/* +* Reserved. Returns zeroes on reads. +*/ #undef DDR_PHY_VTCR1_RESERVED_11_DEFVAL #undef DDR_PHY_VTCR1_RESERVED_11_SHIFT #undef DDR_PHY_VTCR1_RESERVED_11_MASK -#define DDR_PHY_VTCR1_RESERVED_11_DEFVAL 0x07F00072 -#define DDR_PHY_VTCR1_RESERVED_11_SHIFT 11 -#define DDR_PHY_VTCR1_RESERVED_11_MASK 0x00000800U +#define DDR_PHY_VTCR1_RESERVED_11_DEFVAL 0x07F00072 +#define DDR_PHY_VTCR1_RESERVED_11_SHIFT 11 +#define DDR_PHY_VTCR1_RESERVED_11_MASK 0x00000800U -/*Static Host Vref Rank Value*/ +/* +* Static Host Vref Rank Value +*/ #undef DDR_PHY_VTCR1_SHRNK_DEFVAL #undef DDR_PHY_VTCR1_SHRNK_SHIFT #undef DDR_PHY_VTCR1_SHRNK_MASK -#define DDR_PHY_VTCR1_SHRNK_DEFVAL 0x07F00072 -#define DDR_PHY_VTCR1_SHRNK_SHIFT 9 -#define DDR_PHY_VTCR1_SHRNK_MASK 0x00000600U +#define DDR_PHY_VTCR1_SHRNK_DEFVAL 0x07F00072 +#define DDR_PHY_VTCR1_SHRNK_SHIFT 9 +#define DDR_PHY_VTCR1_SHRNK_MASK 0x00000600U -/*Static Host Vref Rank Enable*/ +/* +* Static Host Vref Rank Enable +*/ #undef DDR_PHY_VTCR1_SHREN_DEFVAL #undef DDR_PHY_VTCR1_SHREN_SHIFT #undef DDR_PHY_VTCR1_SHREN_MASK -#define DDR_PHY_VTCR1_SHREN_DEFVAL 0x07F00072 -#define DDR_PHY_VTCR1_SHREN_SHIFT 8 -#define DDR_PHY_VTCR1_SHREN_MASK 0x00000100U +#define DDR_PHY_VTCR1_SHREN_DEFVAL 0x07F00072 +#define DDR_PHY_VTCR1_SHREN_SHIFT 8 +#define DDR_PHY_VTCR1_SHREN_MASK 0x00000100U -/*Number of ctl_clk required to meet (> 200ns) VREF Settling timing requirements during Host IO VREF training*/ +/* +* Number of ctl_clk required to meet (> 200ns) VREF Settling timing requir + * ements during Host IO VREF training +*/ #undef DDR_PHY_VTCR1_TVREFIO_DEFVAL #undef DDR_PHY_VTCR1_TVREFIO_SHIFT #undef DDR_PHY_VTCR1_TVREFIO_MASK -#define DDR_PHY_VTCR1_TVREFIO_DEFVAL 0x07F00072 -#define DDR_PHY_VTCR1_TVREFIO_SHIFT 5 -#define DDR_PHY_VTCR1_TVREFIO_MASK 0x000000E0U +#define DDR_PHY_VTCR1_TVREFIO_DEFVAL 0x07F00072 +#define DDR_PHY_VTCR1_TVREFIO_SHIFT 5 +#define DDR_PHY_VTCR1_TVREFIO_MASK 0x000000E0U -/*Eye LCDL Offset value for VREF training*/ +/* +* Eye LCDL Offset value for VREF training +*/ #undef DDR_PHY_VTCR1_EOFF_DEFVAL #undef DDR_PHY_VTCR1_EOFF_SHIFT #undef DDR_PHY_VTCR1_EOFF_MASK -#define DDR_PHY_VTCR1_EOFF_DEFVAL 0x07F00072 -#define DDR_PHY_VTCR1_EOFF_SHIFT 3 -#define DDR_PHY_VTCR1_EOFF_MASK 0x00000018U +#define DDR_PHY_VTCR1_EOFF_DEFVAL 0x07F00072 +#define DDR_PHY_VTCR1_EOFF_SHIFT 3 +#define DDR_PHY_VTCR1_EOFF_MASK 0x00000018U -/*Number of LCDL Eye points for which VREF training is repeated*/ +/* +* Number of LCDL Eye points for which VREF training is repeated +*/ #undef DDR_PHY_VTCR1_ENUM_DEFVAL #undef DDR_PHY_VTCR1_ENUM_SHIFT #undef DDR_PHY_VTCR1_ENUM_MASK -#define DDR_PHY_VTCR1_ENUM_DEFVAL 0x07F00072 -#define DDR_PHY_VTCR1_ENUM_SHIFT 2 -#define DDR_PHY_VTCR1_ENUM_MASK 0x00000004U +#define DDR_PHY_VTCR1_ENUM_DEFVAL 0x07F00072 +#define DDR_PHY_VTCR1_ENUM_SHIFT 2 +#define DDR_PHY_VTCR1_ENUM_MASK 0x00000004U -/*HOST (IO) internal VREF training Enable*/ +/* +* HOST (IO) internal VREF training Enable +*/ #undef DDR_PHY_VTCR1_HVEN_DEFVAL #undef DDR_PHY_VTCR1_HVEN_SHIFT #undef DDR_PHY_VTCR1_HVEN_MASK -#define DDR_PHY_VTCR1_HVEN_DEFVAL 0x07F00072 -#define DDR_PHY_VTCR1_HVEN_SHIFT 1 -#define DDR_PHY_VTCR1_HVEN_MASK 0x00000002U +#define DDR_PHY_VTCR1_HVEN_DEFVAL 0x07F00072 +#define DDR_PHY_VTCR1_HVEN_SHIFT 1 +#define DDR_PHY_VTCR1_HVEN_MASK 0x00000002U -/*Host IO Type Control*/ +/* +* Host IO Type Control +*/ #undef DDR_PHY_VTCR1_HVIO_DEFVAL #undef DDR_PHY_VTCR1_HVIO_SHIFT #undef DDR_PHY_VTCR1_HVIO_MASK -#define DDR_PHY_VTCR1_HVIO_DEFVAL 0x07F00072 -#define DDR_PHY_VTCR1_HVIO_SHIFT 0 -#define DDR_PHY_VTCR1_HVIO_MASK 0x00000001U +#define DDR_PHY_VTCR1_HVIO_DEFVAL 0x07F00072 +#define DDR_PHY_VTCR1_HVIO_SHIFT 0 +#define DDR_PHY_VTCR1_HVIO_MASK 0x00000001U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR1_RESERVED_31_30_DEFVAL #undef DDR_PHY_ACBDLR1_RESERVED_31_30_SHIFT #undef DDR_PHY_ACBDLR1_RESERVED_31_30_MASK -#define DDR_PHY_ACBDLR1_RESERVED_31_30_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR1_RESERVED_31_30_SHIFT 30 -#define DDR_PHY_ACBDLR1_RESERVED_31_30_MASK 0xC0000000U +#define DDR_PHY_ACBDLR1_RESERVED_31_30_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR1_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_ACBDLR1_RESERVED_31_30_MASK 0xC0000000U -/*Delay select for the BDL on Parity.*/ +/* +* Delay select for the BDL on Parity. +*/ #undef DDR_PHY_ACBDLR1_PARBD_DEFVAL #undef DDR_PHY_ACBDLR1_PARBD_SHIFT #undef DDR_PHY_ACBDLR1_PARBD_MASK -#define DDR_PHY_ACBDLR1_PARBD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR1_PARBD_SHIFT 24 -#define DDR_PHY_ACBDLR1_PARBD_MASK 0x3F000000U +#define DDR_PHY_ACBDLR1_PARBD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR1_PARBD_SHIFT 24 +#define DDR_PHY_ACBDLR1_PARBD_MASK 0x3F000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR1_RESERVED_23_22_DEFVAL #undef DDR_PHY_ACBDLR1_RESERVED_23_22_SHIFT #undef DDR_PHY_ACBDLR1_RESERVED_23_22_MASK -#define DDR_PHY_ACBDLR1_RESERVED_23_22_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR1_RESERVED_23_22_SHIFT 22 -#define DDR_PHY_ACBDLR1_RESERVED_23_22_MASK 0x00C00000U +#define DDR_PHY_ACBDLR1_RESERVED_23_22_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR1_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_ACBDLR1_RESERVED_23_22_MASK 0x00C00000U -/*Delay select for the BDL on Address A[16]. In DDR3 mode this pin is connected to WE.*/ +/* +* Delay select for the BDL on Address A[16]. In DDR3 mode this pin is conn + * ected to WE. +*/ #undef DDR_PHY_ACBDLR1_A16BD_DEFVAL #undef DDR_PHY_ACBDLR1_A16BD_SHIFT #undef DDR_PHY_ACBDLR1_A16BD_MASK -#define DDR_PHY_ACBDLR1_A16BD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR1_A16BD_SHIFT 16 -#define DDR_PHY_ACBDLR1_A16BD_MASK 0x003F0000U +#define DDR_PHY_ACBDLR1_A16BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR1_A16BD_SHIFT 16 +#define DDR_PHY_ACBDLR1_A16BD_MASK 0x003F0000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR1_RESERVED_15_14_DEFVAL #undef DDR_PHY_ACBDLR1_RESERVED_15_14_SHIFT #undef DDR_PHY_ACBDLR1_RESERVED_15_14_MASK -#define DDR_PHY_ACBDLR1_RESERVED_15_14_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR1_RESERVED_15_14_SHIFT 14 -#define DDR_PHY_ACBDLR1_RESERVED_15_14_MASK 0x0000C000U +#define DDR_PHY_ACBDLR1_RESERVED_15_14_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR1_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_ACBDLR1_RESERVED_15_14_MASK 0x0000C000U -/*Delay select for the BDL on Address A[17]. When not in DDR4 modemode this pin is connected to CAS.*/ +/* +* Delay select for the BDL on Address A[17]. When not in DDR4 modemode thi + * s pin is connected to CAS. +*/ #undef DDR_PHY_ACBDLR1_A17BD_DEFVAL #undef DDR_PHY_ACBDLR1_A17BD_SHIFT #undef DDR_PHY_ACBDLR1_A17BD_MASK -#define DDR_PHY_ACBDLR1_A17BD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR1_A17BD_SHIFT 8 -#define DDR_PHY_ACBDLR1_A17BD_MASK 0x00003F00U +#define DDR_PHY_ACBDLR1_A17BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR1_A17BD_SHIFT 8 +#define DDR_PHY_ACBDLR1_A17BD_MASK 0x00003F00U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR1_RESERVED_7_6_DEFVAL #undef DDR_PHY_ACBDLR1_RESERVED_7_6_SHIFT #undef DDR_PHY_ACBDLR1_RESERVED_7_6_MASK -#define DDR_PHY_ACBDLR1_RESERVED_7_6_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR1_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_ACBDLR1_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_ACBDLR1_RESERVED_7_6_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR1_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_ACBDLR1_RESERVED_7_6_MASK 0x000000C0U -/*Delay select for the BDL on ACTN.*/ +/* +* Delay select for the BDL on ACTN. +*/ #undef DDR_PHY_ACBDLR1_ACTBD_DEFVAL #undef DDR_PHY_ACBDLR1_ACTBD_SHIFT #undef DDR_PHY_ACBDLR1_ACTBD_MASK -#define DDR_PHY_ACBDLR1_ACTBD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR1_ACTBD_SHIFT 0 -#define DDR_PHY_ACBDLR1_ACTBD_MASK 0x0000003FU +#define DDR_PHY_ACBDLR1_ACTBD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR1_ACTBD_SHIFT 0 +#define DDR_PHY_ACBDLR1_ACTBD_MASK 0x0000003FU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR2_RESERVED_31_30_DEFVAL #undef DDR_PHY_ACBDLR2_RESERVED_31_30_SHIFT #undef DDR_PHY_ACBDLR2_RESERVED_31_30_MASK -#define DDR_PHY_ACBDLR2_RESERVED_31_30_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR2_RESERVED_31_30_SHIFT 30 -#define DDR_PHY_ACBDLR2_RESERVED_31_30_MASK 0xC0000000U +#define DDR_PHY_ACBDLR2_RESERVED_31_30_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR2_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_ACBDLR2_RESERVED_31_30_MASK 0xC0000000U -/*Delay select for the BDL on BG[1].*/ +/* +* Delay select for the BDL on BG[1]. +*/ #undef DDR_PHY_ACBDLR2_BG1BD_DEFVAL #undef DDR_PHY_ACBDLR2_BG1BD_SHIFT #undef DDR_PHY_ACBDLR2_BG1BD_MASK -#define DDR_PHY_ACBDLR2_BG1BD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR2_BG1BD_SHIFT 24 -#define DDR_PHY_ACBDLR2_BG1BD_MASK 0x3F000000U +#define DDR_PHY_ACBDLR2_BG1BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR2_BG1BD_SHIFT 24 +#define DDR_PHY_ACBDLR2_BG1BD_MASK 0x3F000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR2_RESERVED_23_22_DEFVAL #undef DDR_PHY_ACBDLR2_RESERVED_23_22_SHIFT #undef DDR_PHY_ACBDLR2_RESERVED_23_22_MASK -#define DDR_PHY_ACBDLR2_RESERVED_23_22_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR2_RESERVED_23_22_SHIFT 22 -#define DDR_PHY_ACBDLR2_RESERVED_23_22_MASK 0x00C00000U +#define DDR_PHY_ACBDLR2_RESERVED_23_22_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR2_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_ACBDLR2_RESERVED_23_22_MASK 0x00C00000U -/*Delay select for the BDL on BG[0].*/ +/* +* Delay select for the BDL on BG[0]. +*/ #undef DDR_PHY_ACBDLR2_BG0BD_DEFVAL #undef DDR_PHY_ACBDLR2_BG0BD_SHIFT #undef DDR_PHY_ACBDLR2_BG0BD_MASK -#define DDR_PHY_ACBDLR2_BG0BD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR2_BG0BD_SHIFT 16 -#define DDR_PHY_ACBDLR2_BG0BD_MASK 0x003F0000U +#define DDR_PHY_ACBDLR2_BG0BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR2_BG0BD_SHIFT 16 +#define DDR_PHY_ACBDLR2_BG0BD_MASK 0x003F0000U -/*Reser.ved Return zeroes on reads.*/ +/* +* Reser.ved Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR2_RESERVED_15_14_DEFVAL #undef DDR_PHY_ACBDLR2_RESERVED_15_14_SHIFT #undef DDR_PHY_ACBDLR2_RESERVED_15_14_MASK -#define DDR_PHY_ACBDLR2_RESERVED_15_14_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR2_RESERVED_15_14_SHIFT 14 -#define DDR_PHY_ACBDLR2_RESERVED_15_14_MASK 0x0000C000U +#define DDR_PHY_ACBDLR2_RESERVED_15_14_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR2_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_ACBDLR2_RESERVED_15_14_MASK 0x0000C000U -/*Delay select for the BDL on BA[1].*/ +/* +* Delay select for the BDL on BA[1]. +*/ #undef DDR_PHY_ACBDLR2_BA1BD_DEFVAL #undef DDR_PHY_ACBDLR2_BA1BD_SHIFT #undef DDR_PHY_ACBDLR2_BA1BD_MASK -#define DDR_PHY_ACBDLR2_BA1BD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR2_BA1BD_SHIFT 8 -#define DDR_PHY_ACBDLR2_BA1BD_MASK 0x00003F00U +#define DDR_PHY_ACBDLR2_BA1BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR2_BA1BD_SHIFT 8 +#define DDR_PHY_ACBDLR2_BA1BD_MASK 0x00003F00U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR2_RESERVED_7_6_DEFVAL #undef DDR_PHY_ACBDLR2_RESERVED_7_6_SHIFT #undef DDR_PHY_ACBDLR2_RESERVED_7_6_MASK -#define DDR_PHY_ACBDLR2_RESERVED_7_6_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR2_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_ACBDLR2_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_ACBDLR2_RESERVED_7_6_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR2_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_ACBDLR2_RESERVED_7_6_MASK 0x000000C0U -/*Delay select for the BDL on BA[0].*/ +/* +* Delay select for the BDL on BA[0]. +*/ #undef DDR_PHY_ACBDLR2_BA0BD_DEFVAL #undef DDR_PHY_ACBDLR2_BA0BD_SHIFT #undef DDR_PHY_ACBDLR2_BA0BD_MASK -#define DDR_PHY_ACBDLR2_BA0BD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR2_BA0BD_SHIFT 0 -#define DDR_PHY_ACBDLR2_BA0BD_MASK 0x0000003FU +#define DDR_PHY_ACBDLR2_BA0BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR2_BA0BD_SHIFT 0 +#define DDR_PHY_ACBDLR2_BA0BD_MASK 0x0000003FU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR6_RESERVED_31_30_DEFVAL #undef DDR_PHY_ACBDLR6_RESERVED_31_30_SHIFT #undef DDR_PHY_ACBDLR6_RESERVED_31_30_MASK -#define DDR_PHY_ACBDLR6_RESERVED_31_30_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR6_RESERVED_31_30_SHIFT 30 -#define DDR_PHY_ACBDLR6_RESERVED_31_30_MASK 0xC0000000U +#define DDR_PHY_ACBDLR6_RESERVED_31_30_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR6_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_ACBDLR6_RESERVED_31_30_MASK 0xC0000000U -/*Delay select for the BDL on Address A[3].*/ +/* +* Delay select for the BDL on Address A[3]. +*/ #undef DDR_PHY_ACBDLR6_A03BD_DEFVAL #undef DDR_PHY_ACBDLR6_A03BD_SHIFT #undef DDR_PHY_ACBDLR6_A03BD_MASK -#define DDR_PHY_ACBDLR6_A03BD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR6_A03BD_SHIFT 24 -#define DDR_PHY_ACBDLR6_A03BD_MASK 0x3F000000U +#define DDR_PHY_ACBDLR6_A03BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR6_A03BD_SHIFT 24 +#define DDR_PHY_ACBDLR6_A03BD_MASK 0x3F000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR6_RESERVED_23_22_DEFVAL #undef DDR_PHY_ACBDLR6_RESERVED_23_22_SHIFT #undef DDR_PHY_ACBDLR6_RESERVED_23_22_MASK -#define DDR_PHY_ACBDLR6_RESERVED_23_22_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR6_RESERVED_23_22_SHIFT 22 -#define DDR_PHY_ACBDLR6_RESERVED_23_22_MASK 0x00C00000U +#define DDR_PHY_ACBDLR6_RESERVED_23_22_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR6_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_ACBDLR6_RESERVED_23_22_MASK 0x00C00000U -/*Delay select for the BDL on Address A[2].*/ +/* +* Delay select for the BDL on Address A[2]. +*/ #undef DDR_PHY_ACBDLR6_A02BD_DEFVAL #undef DDR_PHY_ACBDLR6_A02BD_SHIFT #undef DDR_PHY_ACBDLR6_A02BD_MASK -#define DDR_PHY_ACBDLR6_A02BD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR6_A02BD_SHIFT 16 -#define DDR_PHY_ACBDLR6_A02BD_MASK 0x003F0000U +#define DDR_PHY_ACBDLR6_A02BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR6_A02BD_SHIFT 16 +#define DDR_PHY_ACBDLR6_A02BD_MASK 0x003F0000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR6_RESERVED_15_14_DEFVAL #undef DDR_PHY_ACBDLR6_RESERVED_15_14_SHIFT #undef DDR_PHY_ACBDLR6_RESERVED_15_14_MASK -#define DDR_PHY_ACBDLR6_RESERVED_15_14_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR6_RESERVED_15_14_SHIFT 14 -#define DDR_PHY_ACBDLR6_RESERVED_15_14_MASK 0x0000C000U +#define DDR_PHY_ACBDLR6_RESERVED_15_14_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR6_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_ACBDLR6_RESERVED_15_14_MASK 0x0000C000U -/*Delay select for the BDL on Address A[1].*/ +/* +* Delay select for the BDL on Address A[1]. +*/ #undef DDR_PHY_ACBDLR6_A01BD_DEFVAL #undef DDR_PHY_ACBDLR6_A01BD_SHIFT #undef DDR_PHY_ACBDLR6_A01BD_MASK -#define DDR_PHY_ACBDLR6_A01BD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR6_A01BD_SHIFT 8 -#define DDR_PHY_ACBDLR6_A01BD_MASK 0x00003F00U +#define DDR_PHY_ACBDLR6_A01BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR6_A01BD_SHIFT 8 +#define DDR_PHY_ACBDLR6_A01BD_MASK 0x00003F00U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR6_RESERVED_7_6_DEFVAL #undef DDR_PHY_ACBDLR6_RESERVED_7_6_SHIFT #undef DDR_PHY_ACBDLR6_RESERVED_7_6_MASK -#define DDR_PHY_ACBDLR6_RESERVED_7_6_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR6_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_ACBDLR6_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_ACBDLR6_RESERVED_7_6_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR6_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_ACBDLR6_RESERVED_7_6_MASK 0x000000C0U -/*Delay select for the BDL on Address A[0].*/ +/* +* Delay select for the BDL on Address A[0]. +*/ #undef DDR_PHY_ACBDLR6_A00BD_DEFVAL #undef DDR_PHY_ACBDLR6_A00BD_SHIFT #undef DDR_PHY_ACBDLR6_A00BD_MASK -#define DDR_PHY_ACBDLR6_A00BD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR6_A00BD_SHIFT 0 -#define DDR_PHY_ACBDLR6_A00BD_MASK 0x0000003FU +#define DDR_PHY_ACBDLR6_A00BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR6_A00BD_SHIFT 0 +#define DDR_PHY_ACBDLR6_A00BD_MASK 0x0000003FU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR7_RESERVED_31_30_DEFVAL #undef DDR_PHY_ACBDLR7_RESERVED_31_30_SHIFT #undef DDR_PHY_ACBDLR7_RESERVED_31_30_MASK -#define DDR_PHY_ACBDLR7_RESERVED_31_30_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR7_RESERVED_31_30_SHIFT 30 -#define DDR_PHY_ACBDLR7_RESERVED_31_30_MASK 0xC0000000U +#define DDR_PHY_ACBDLR7_RESERVED_31_30_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR7_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_ACBDLR7_RESERVED_31_30_MASK 0xC0000000U -/*Delay select for the BDL on Address A[7].*/ +/* +* Delay select for the BDL on Address A[7]. +*/ #undef DDR_PHY_ACBDLR7_A07BD_DEFVAL #undef DDR_PHY_ACBDLR7_A07BD_SHIFT #undef DDR_PHY_ACBDLR7_A07BD_MASK -#define DDR_PHY_ACBDLR7_A07BD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR7_A07BD_SHIFT 24 -#define DDR_PHY_ACBDLR7_A07BD_MASK 0x3F000000U +#define DDR_PHY_ACBDLR7_A07BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR7_A07BD_SHIFT 24 +#define DDR_PHY_ACBDLR7_A07BD_MASK 0x3F000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR7_RESERVED_23_22_DEFVAL #undef DDR_PHY_ACBDLR7_RESERVED_23_22_SHIFT #undef DDR_PHY_ACBDLR7_RESERVED_23_22_MASK -#define DDR_PHY_ACBDLR7_RESERVED_23_22_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR7_RESERVED_23_22_SHIFT 22 -#define DDR_PHY_ACBDLR7_RESERVED_23_22_MASK 0x00C00000U +#define DDR_PHY_ACBDLR7_RESERVED_23_22_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR7_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_ACBDLR7_RESERVED_23_22_MASK 0x00C00000U -/*Delay select for the BDL on Address A[6].*/ +/* +* Delay select for the BDL on Address A[6]. +*/ #undef DDR_PHY_ACBDLR7_A06BD_DEFVAL #undef DDR_PHY_ACBDLR7_A06BD_SHIFT #undef DDR_PHY_ACBDLR7_A06BD_MASK -#define DDR_PHY_ACBDLR7_A06BD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR7_A06BD_SHIFT 16 -#define DDR_PHY_ACBDLR7_A06BD_MASK 0x003F0000U +#define DDR_PHY_ACBDLR7_A06BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR7_A06BD_SHIFT 16 +#define DDR_PHY_ACBDLR7_A06BD_MASK 0x003F0000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR7_RESERVED_15_14_DEFVAL #undef DDR_PHY_ACBDLR7_RESERVED_15_14_SHIFT #undef DDR_PHY_ACBDLR7_RESERVED_15_14_MASK -#define DDR_PHY_ACBDLR7_RESERVED_15_14_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR7_RESERVED_15_14_SHIFT 14 -#define DDR_PHY_ACBDLR7_RESERVED_15_14_MASK 0x0000C000U +#define DDR_PHY_ACBDLR7_RESERVED_15_14_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR7_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_ACBDLR7_RESERVED_15_14_MASK 0x0000C000U -/*Delay select for the BDL on Address A[5].*/ +/* +* Delay select for the BDL on Address A[5]. +*/ #undef DDR_PHY_ACBDLR7_A05BD_DEFVAL #undef DDR_PHY_ACBDLR7_A05BD_SHIFT #undef DDR_PHY_ACBDLR7_A05BD_MASK -#define DDR_PHY_ACBDLR7_A05BD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR7_A05BD_SHIFT 8 -#define DDR_PHY_ACBDLR7_A05BD_MASK 0x00003F00U +#define DDR_PHY_ACBDLR7_A05BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR7_A05BD_SHIFT 8 +#define DDR_PHY_ACBDLR7_A05BD_MASK 0x00003F00U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR7_RESERVED_7_6_DEFVAL #undef DDR_PHY_ACBDLR7_RESERVED_7_6_SHIFT #undef DDR_PHY_ACBDLR7_RESERVED_7_6_MASK -#define DDR_PHY_ACBDLR7_RESERVED_7_6_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR7_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_ACBDLR7_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_ACBDLR7_RESERVED_7_6_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR7_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_ACBDLR7_RESERVED_7_6_MASK 0x000000C0U -/*Delay select for the BDL on Address A[4].*/ +/* +* Delay select for the BDL on Address A[4]. +*/ #undef DDR_PHY_ACBDLR7_A04BD_DEFVAL #undef DDR_PHY_ACBDLR7_A04BD_SHIFT #undef DDR_PHY_ACBDLR7_A04BD_MASK -#define DDR_PHY_ACBDLR7_A04BD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR7_A04BD_SHIFT 0 -#define DDR_PHY_ACBDLR7_A04BD_MASK 0x0000003FU +#define DDR_PHY_ACBDLR7_A04BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR7_A04BD_SHIFT 0 +#define DDR_PHY_ACBDLR7_A04BD_MASK 0x0000003FU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR8_RESERVED_31_30_DEFVAL #undef DDR_PHY_ACBDLR8_RESERVED_31_30_SHIFT #undef DDR_PHY_ACBDLR8_RESERVED_31_30_MASK -#define DDR_PHY_ACBDLR8_RESERVED_31_30_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR8_RESERVED_31_30_SHIFT 30 -#define DDR_PHY_ACBDLR8_RESERVED_31_30_MASK 0xC0000000U +#define DDR_PHY_ACBDLR8_RESERVED_31_30_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR8_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_ACBDLR8_RESERVED_31_30_MASK 0xC0000000U -/*Delay select for the BDL on Address A[11].*/ +/* +* Delay select for the BDL on Address A[11]. +*/ #undef DDR_PHY_ACBDLR8_A11BD_DEFVAL #undef DDR_PHY_ACBDLR8_A11BD_SHIFT #undef DDR_PHY_ACBDLR8_A11BD_MASK -#define DDR_PHY_ACBDLR8_A11BD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR8_A11BD_SHIFT 24 -#define DDR_PHY_ACBDLR8_A11BD_MASK 0x3F000000U +#define DDR_PHY_ACBDLR8_A11BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR8_A11BD_SHIFT 24 +#define DDR_PHY_ACBDLR8_A11BD_MASK 0x3F000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR8_RESERVED_23_22_DEFVAL #undef DDR_PHY_ACBDLR8_RESERVED_23_22_SHIFT #undef DDR_PHY_ACBDLR8_RESERVED_23_22_MASK -#define DDR_PHY_ACBDLR8_RESERVED_23_22_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR8_RESERVED_23_22_SHIFT 22 -#define DDR_PHY_ACBDLR8_RESERVED_23_22_MASK 0x00C00000U +#define DDR_PHY_ACBDLR8_RESERVED_23_22_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR8_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_ACBDLR8_RESERVED_23_22_MASK 0x00C00000U -/*Delay select for the BDL on Address A[10].*/ +/* +* Delay select for the BDL on Address A[10]. +*/ #undef DDR_PHY_ACBDLR8_A10BD_DEFVAL #undef DDR_PHY_ACBDLR8_A10BD_SHIFT #undef DDR_PHY_ACBDLR8_A10BD_MASK -#define DDR_PHY_ACBDLR8_A10BD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR8_A10BD_SHIFT 16 -#define DDR_PHY_ACBDLR8_A10BD_MASK 0x003F0000U +#define DDR_PHY_ACBDLR8_A10BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR8_A10BD_SHIFT 16 +#define DDR_PHY_ACBDLR8_A10BD_MASK 0x003F0000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR8_RESERVED_15_14_DEFVAL #undef DDR_PHY_ACBDLR8_RESERVED_15_14_SHIFT #undef DDR_PHY_ACBDLR8_RESERVED_15_14_MASK -#define DDR_PHY_ACBDLR8_RESERVED_15_14_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR8_RESERVED_15_14_SHIFT 14 -#define DDR_PHY_ACBDLR8_RESERVED_15_14_MASK 0x0000C000U +#define DDR_PHY_ACBDLR8_RESERVED_15_14_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR8_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_ACBDLR8_RESERVED_15_14_MASK 0x0000C000U -/*Delay select for the BDL on Address A[9].*/ +/* +* Delay select for the BDL on Address A[9]. +*/ #undef DDR_PHY_ACBDLR8_A09BD_DEFVAL #undef DDR_PHY_ACBDLR8_A09BD_SHIFT #undef DDR_PHY_ACBDLR8_A09BD_MASK -#define DDR_PHY_ACBDLR8_A09BD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR8_A09BD_SHIFT 8 -#define DDR_PHY_ACBDLR8_A09BD_MASK 0x00003F00U +#define DDR_PHY_ACBDLR8_A09BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR8_A09BD_SHIFT 8 +#define DDR_PHY_ACBDLR8_A09BD_MASK 0x00003F00U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR8_RESERVED_7_6_DEFVAL #undef DDR_PHY_ACBDLR8_RESERVED_7_6_SHIFT #undef DDR_PHY_ACBDLR8_RESERVED_7_6_MASK -#define DDR_PHY_ACBDLR8_RESERVED_7_6_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR8_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_ACBDLR8_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_ACBDLR8_RESERVED_7_6_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR8_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_ACBDLR8_RESERVED_7_6_MASK 0x000000C0U -/*Delay select for the BDL on Address A[8].*/ +/* +* Delay select for the BDL on Address A[8]. +*/ #undef DDR_PHY_ACBDLR8_A08BD_DEFVAL #undef DDR_PHY_ACBDLR8_A08BD_SHIFT #undef DDR_PHY_ACBDLR8_A08BD_MASK -#define DDR_PHY_ACBDLR8_A08BD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR8_A08BD_SHIFT 0 -#define DDR_PHY_ACBDLR8_A08BD_MASK 0x0000003FU +#define DDR_PHY_ACBDLR8_A08BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR8_A08BD_SHIFT 0 +#define DDR_PHY_ACBDLR8_A08BD_MASK 0x0000003FU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR9_RESERVED_31_30_DEFVAL #undef DDR_PHY_ACBDLR9_RESERVED_31_30_SHIFT #undef DDR_PHY_ACBDLR9_RESERVED_31_30_MASK -#define DDR_PHY_ACBDLR9_RESERVED_31_30_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR9_RESERVED_31_30_SHIFT 30 -#define DDR_PHY_ACBDLR9_RESERVED_31_30_MASK 0xC0000000U +#define DDR_PHY_ACBDLR9_RESERVED_31_30_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR9_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_ACBDLR9_RESERVED_31_30_MASK 0xC0000000U -/*Delay select for the BDL on Address A[15].*/ +/* +* Delay select for the BDL on Address A[15]. +*/ #undef DDR_PHY_ACBDLR9_A15BD_DEFVAL #undef DDR_PHY_ACBDLR9_A15BD_SHIFT #undef DDR_PHY_ACBDLR9_A15BD_MASK -#define DDR_PHY_ACBDLR9_A15BD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR9_A15BD_SHIFT 24 -#define DDR_PHY_ACBDLR9_A15BD_MASK 0x3F000000U +#define DDR_PHY_ACBDLR9_A15BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR9_A15BD_SHIFT 24 +#define DDR_PHY_ACBDLR9_A15BD_MASK 0x3F000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR9_RESERVED_23_22_DEFVAL #undef DDR_PHY_ACBDLR9_RESERVED_23_22_SHIFT #undef DDR_PHY_ACBDLR9_RESERVED_23_22_MASK -#define DDR_PHY_ACBDLR9_RESERVED_23_22_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR9_RESERVED_23_22_SHIFT 22 -#define DDR_PHY_ACBDLR9_RESERVED_23_22_MASK 0x00C00000U +#define DDR_PHY_ACBDLR9_RESERVED_23_22_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR9_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_ACBDLR9_RESERVED_23_22_MASK 0x00C00000U -/*Delay select for the BDL on Address A[14].*/ +/* +* Delay select for the BDL on Address A[14]. +*/ #undef DDR_PHY_ACBDLR9_A14BD_DEFVAL #undef DDR_PHY_ACBDLR9_A14BD_SHIFT #undef DDR_PHY_ACBDLR9_A14BD_MASK -#define DDR_PHY_ACBDLR9_A14BD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR9_A14BD_SHIFT 16 -#define DDR_PHY_ACBDLR9_A14BD_MASK 0x003F0000U +#define DDR_PHY_ACBDLR9_A14BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR9_A14BD_SHIFT 16 +#define DDR_PHY_ACBDLR9_A14BD_MASK 0x003F0000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR9_RESERVED_15_14_DEFVAL #undef DDR_PHY_ACBDLR9_RESERVED_15_14_SHIFT #undef DDR_PHY_ACBDLR9_RESERVED_15_14_MASK -#define DDR_PHY_ACBDLR9_RESERVED_15_14_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR9_RESERVED_15_14_SHIFT 14 -#define DDR_PHY_ACBDLR9_RESERVED_15_14_MASK 0x0000C000U +#define DDR_PHY_ACBDLR9_RESERVED_15_14_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR9_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_ACBDLR9_RESERVED_15_14_MASK 0x0000C000U -/*Delay select for the BDL on Address A[13].*/ +/* +* Delay select for the BDL on Address A[13]. +*/ #undef DDR_PHY_ACBDLR9_A13BD_DEFVAL #undef DDR_PHY_ACBDLR9_A13BD_SHIFT #undef DDR_PHY_ACBDLR9_A13BD_MASK -#define DDR_PHY_ACBDLR9_A13BD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR9_A13BD_SHIFT 8 -#define DDR_PHY_ACBDLR9_A13BD_MASK 0x00003F00U +#define DDR_PHY_ACBDLR9_A13BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR9_A13BD_SHIFT 8 +#define DDR_PHY_ACBDLR9_A13BD_MASK 0x00003F00U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR9_RESERVED_7_6_DEFVAL #undef DDR_PHY_ACBDLR9_RESERVED_7_6_SHIFT #undef DDR_PHY_ACBDLR9_RESERVED_7_6_MASK -#define DDR_PHY_ACBDLR9_RESERVED_7_6_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR9_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_ACBDLR9_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_ACBDLR9_RESERVED_7_6_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR9_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_ACBDLR9_RESERVED_7_6_MASK 0x000000C0U -/*Delay select for the BDL on Address A[12].*/ +/* +* Delay select for the BDL on Address A[12]. +*/ #undef DDR_PHY_ACBDLR9_A12BD_DEFVAL #undef DDR_PHY_ACBDLR9_A12BD_SHIFT #undef DDR_PHY_ACBDLR9_A12BD_MASK -#define DDR_PHY_ACBDLR9_A12BD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR9_A12BD_SHIFT 0 -#define DDR_PHY_ACBDLR9_A12BD_MASK 0x0000003FU +#define DDR_PHY_ACBDLR9_A12BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR9_A12BD_SHIFT 0 +#define DDR_PHY_ACBDLR9_A12BD_MASK 0x0000003FU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ZQCR_RESERVED_31_26_DEFVAL #undef DDR_PHY_ZQCR_RESERVED_31_26_SHIFT #undef DDR_PHY_ZQCR_RESERVED_31_26_MASK -#define DDR_PHY_ZQCR_RESERVED_31_26_DEFVAL 0x008A2858 -#define DDR_PHY_ZQCR_RESERVED_31_26_SHIFT 26 -#define DDR_PHY_ZQCR_RESERVED_31_26_MASK 0xFC000000U +#define DDR_PHY_ZQCR_RESERVED_31_26_DEFVAL 0x008A2858 +#define DDR_PHY_ZQCR_RESERVED_31_26_SHIFT 26 +#define DDR_PHY_ZQCR_RESERVED_31_26_MASK 0xFC000000U -/*ZQ VREF Range*/ +/* +* ZQ VREF Range +*/ #undef DDR_PHY_ZQCR_ZQREFISELRANGE_DEFVAL #undef DDR_PHY_ZQCR_ZQREFISELRANGE_SHIFT #undef DDR_PHY_ZQCR_ZQREFISELRANGE_MASK -#define DDR_PHY_ZQCR_ZQREFISELRANGE_DEFVAL 0x008A2858 -#define DDR_PHY_ZQCR_ZQREFISELRANGE_SHIFT 25 -#define DDR_PHY_ZQCR_ZQREFISELRANGE_MASK 0x02000000U +#define DDR_PHY_ZQCR_ZQREFISELRANGE_DEFVAL 0x008A2858 +#define DDR_PHY_ZQCR_ZQREFISELRANGE_SHIFT 25 +#define DDR_PHY_ZQCR_ZQREFISELRANGE_MASK 0x02000000U -/*Programmable Wait for Frequency B*/ +/* +* Programmable Wait for Frequency B +*/ #undef DDR_PHY_ZQCR_PGWAIT_FRQB_DEFVAL #undef DDR_PHY_ZQCR_PGWAIT_FRQB_SHIFT #undef DDR_PHY_ZQCR_PGWAIT_FRQB_MASK -#define DDR_PHY_ZQCR_PGWAIT_FRQB_DEFVAL 0x008A2858 -#define DDR_PHY_ZQCR_PGWAIT_FRQB_SHIFT 19 -#define DDR_PHY_ZQCR_PGWAIT_FRQB_MASK 0x01F80000U +#define DDR_PHY_ZQCR_PGWAIT_FRQB_DEFVAL 0x008A2858 +#define DDR_PHY_ZQCR_PGWAIT_FRQB_SHIFT 19 +#define DDR_PHY_ZQCR_PGWAIT_FRQB_MASK 0x01F80000U -/*Programmable Wait for Frequency A*/ +/* +* Programmable Wait for Frequency A +*/ #undef DDR_PHY_ZQCR_PGWAIT_FRQA_DEFVAL #undef DDR_PHY_ZQCR_PGWAIT_FRQA_SHIFT #undef DDR_PHY_ZQCR_PGWAIT_FRQA_MASK -#define DDR_PHY_ZQCR_PGWAIT_FRQA_DEFVAL 0x008A2858 -#define DDR_PHY_ZQCR_PGWAIT_FRQA_SHIFT 13 -#define DDR_PHY_ZQCR_PGWAIT_FRQA_MASK 0x0007E000U +#define DDR_PHY_ZQCR_PGWAIT_FRQA_DEFVAL 0x008A2858 +#define DDR_PHY_ZQCR_PGWAIT_FRQA_SHIFT 13 +#define DDR_PHY_ZQCR_PGWAIT_FRQA_MASK 0x0007E000U -/*ZQ VREF Pad Enable*/ +/* +* ZQ VREF Pad Enable +*/ #undef DDR_PHY_ZQCR_ZQREFPEN_DEFVAL #undef DDR_PHY_ZQCR_ZQREFPEN_SHIFT #undef DDR_PHY_ZQCR_ZQREFPEN_MASK -#define DDR_PHY_ZQCR_ZQREFPEN_DEFVAL 0x008A2858 -#define DDR_PHY_ZQCR_ZQREFPEN_SHIFT 12 -#define DDR_PHY_ZQCR_ZQREFPEN_MASK 0x00001000U +#define DDR_PHY_ZQCR_ZQREFPEN_DEFVAL 0x008A2858 +#define DDR_PHY_ZQCR_ZQREFPEN_SHIFT 12 +#define DDR_PHY_ZQCR_ZQREFPEN_MASK 0x00001000U -/*ZQ Internal VREF Enable*/ +/* +* ZQ Internal VREF Enable +*/ #undef DDR_PHY_ZQCR_ZQREFIEN_DEFVAL #undef DDR_PHY_ZQCR_ZQREFIEN_SHIFT #undef DDR_PHY_ZQCR_ZQREFIEN_MASK -#define DDR_PHY_ZQCR_ZQREFIEN_DEFVAL 0x008A2858 -#define DDR_PHY_ZQCR_ZQREFIEN_SHIFT 11 -#define DDR_PHY_ZQCR_ZQREFIEN_MASK 0x00000800U +#define DDR_PHY_ZQCR_ZQREFIEN_DEFVAL 0x008A2858 +#define DDR_PHY_ZQCR_ZQREFIEN_SHIFT 11 +#define DDR_PHY_ZQCR_ZQREFIEN_MASK 0x00000800U -/*Choice of termination mode*/ +/* +* Choice of termination mode +*/ #undef DDR_PHY_ZQCR_ODT_MODE_DEFVAL #undef DDR_PHY_ZQCR_ODT_MODE_SHIFT #undef DDR_PHY_ZQCR_ODT_MODE_MASK -#define DDR_PHY_ZQCR_ODT_MODE_DEFVAL 0x008A2858 -#define DDR_PHY_ZQCR_ODT_MODE_SHIFT 9 -#define DDR_PHY_ZQCR_ODT_MODE_MASK 0x00000600U +#define DDR_PHY_ZQCR_ODT_MODE_DEFVAL 0x008A2858 +#define DDR_PHY_ZQCR_ODT_MODE_SHIFT 9 +#define DDR_PHY_ZQCR_ODT_MODE_MASK 0x00000600U -/*Force ZCAL VT update*/ +/* +* Force ZCAL VT update +*/ #undef DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_DEFVAL #undef DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_SHIFT #undef DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_MASK -#define DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_DEFVAL 0x008A2858 -#define DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_SHIFT 8 -#define DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_MASK 0x00000100U +#define DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_DEFVAL 0x008A2858 +#define DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_SHIFT 8 +#define DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_MASK 0x00000100U -/*IO VT Drift Limit*/ +/* +* IO VT Drift Limit +*/ #undef DDR_PHY_ZQCR_IODLMT_DEFVAL #undef DDR_PHY_ZQCR_IODLMT_SHIFT #undef DDR_PHY_ZQCR_IODLMT_MASK -#define DDR_PHY_ZQCR_IODLMT_DEFVAL 0x008A2858 -#define DDR_PHY_ZQCR_IODLMT_SHIFT 5 -#define DDR_PHY_ZQCR_IODLMT_MASK 0x000000E0U +#define DDR_PHY_ZQCR_IODLMT_DEFVAL 0x008A2858 +#define DDR_PHY_ZQCR_IODLMT_SHIFT 5 +#define DDR_PHY_ZQCR_IODLMT_MASK 0x000000E0U -/*Averaging algorithm enable, if set, enables averaging algorithm*/ +/* +* Averaging algorithm enable, if set, enables averaging algorithm +*/ #undef DDR_PHY_ZQCR_AVGEN_DEFVAL #undef DDR_PHY_ZQCR_AVGEN_SHIFT #undef DDR_PHY_ZQCR_AVGEN_MASK -#define DDR_PHY_ZQCR_AVGEN_DEFVAL 0x008A2858 -#define DDR_PHY_ZQCR_AVGEN_SHIFT 4 -#define DDR_PHY_ZQCR_AVGEN_MASK 0x00000010U +#define DDR_PHY_ZQCR_AVGEN_DEFVAL 0x008A2858 +#define DDR_PHY_ZQCR_AVGEN_SHIFT 4 +#define DDR_PHY_ZQCR_AVGEN_MASK 0x00000010U -/*Maximum number of averaging rounds to be used by averaging algorithm*/ +/* +* Maximum number of averaging rounds to be used by averaging algorithm +*/ #undef DDR_PHY_ZQCR_AVGMAX_DEFVAL #undef DDR_PHY_ZQCR_AVGMAX_SHIFT #undef DDR_PHY_ZQCR_AVGMAX_MASK -#define DDR_PHY_ZQCR_AVGMAX_DEFVAL 0x008A2858 -#define DDR_PHY_ZQCR_AVGMAX_SHIFT 2 -#define DDR_PHY_ZQCR_AVGMAX_MASK 0x0000000CU +#define DDR_PHY_ZQCR_AVGMAX_DEFVAL 0x008A2858 +#define DDR_PHY_ZQCR_AVGMAX_SHIFT 2 +#define DDR_PHY_ZQCR_AVGMAX_MASK 0x0000000CU -/*ZQ Calibration Type*/ +/* +* ZQ Calibration Type +*/ #undef DDR_PHY_ZQCR_ZCALT_DEFVAL #undef DDR_PHY_ZQCR_ZCALT_SHIFT #undef DDR_PHY_ZQCR_ZCALT_MASK -#define DDR_PHY_ZQCR_ZCALT_DEFVAL 0x008A2858 -#define DDR_PHY_ZQCR_ZCALT_SHIFT 1 -#define DDR_PHY_ZQCR_ZCALT_MASK 0x00000002U +#define DDR_PHY_ZQCR_ZCALT_DEFVAL 0x008A2858 +#define DDR_PHY_ZQCR_ZCALT_SHIFT 1 +#define DDR_PHY_ZQCR_ZCALT_MASK 0x00000002U -/*ZQ Power Down*/ +/* +* ZQ Power Down +*/ #undef DDR_PHY_ZQCR_ZQPD_DEFVAL #undef DDR_PHY_ZQCR_ZQPD_SHIFT #undef DDR_PHY_ZQCR_ZQPD_MASK -#define DDR_PHY_ZQCR_ZQPD_DEFVAL 0x008A2858 -#define DDR_PHY_ZQCR_ZQPD_SHIFT 0 -#define DDR_PHY_ZQCR_ZQPD_MASK 0x00000001U +#define DDR_PHY_ZQCR_ZQPD_DEFVAL 0x008A2858 +#define DDR_PHY_ZQCR_ZQPD_SHIFT 0 +#define DDR_PHY_ZQCR_ZQPD_MASK 0x00000001U -/*Pull-down drive strength ZCTRL over-ride enable*/ +/* +* Pull-down drive strength ZCTRL over-ride enable +*/ #undef DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_DEFVAL #undef DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_SHIFT #undef DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_MASK -#define DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_DEFVAL 0x000077BB -#define DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_SHIFT 31 -#define DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_MASK 0x80000000U +#define DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_DEFVAL 0x000077BB +#define DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_SHIFT 31 +#define DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_MASK 0x80000000U -/*Pull-up drive strength ZCTRL over-ride enable*/ +/* +* Pull-up drive strength ZCTRL over-ride enable +*/ #undef DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_DEFVAL #undef DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_SHIFT #undef DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_MASK -#define DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_DEFVAL 0x000077BB -#define DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_SHIFT 30 -#define DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_MASK 0x40000000U +#define DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_DEFVAL 0x000077BB +#define DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_SHIFT 30 +#define DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_MASK 0x40000000U -/*Pull-down termination ZCTRL over-ride enable*/ +/* +* Pull-down termination ZCTRL over-ride enable +*/ #undef DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_DEFVAL #undef DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_SHIFT #undef DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_MASK -#define DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_DEFVAL 0x000077BB -#define DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_SHIFT 29 -#define DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_MASK 0x20000000U +#define DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_DEFVAL 0x000077BB +#define DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_SHIFT 29 +#define DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_MASK 0x20000000U -/*Pull-up termination ZCTRL over-ride enable*/ +/* +* Pull-up termination ZCTRL over-ride enable +*/ #undef DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_DEFVAL #undef DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_SHIFT #undef DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_MASK -#define DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_DEFVAL 0x000077BB -#define DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_SHIFT 28 -#define DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_MASK 0x10000000U +#define DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_DEFVAL 0x000077BB +#define DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_SHIFT 28 +#define DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_MASK 0x10000000U -/*Calibration segment bypass*/ +/* +* Calibration segment bypass +*/ #undef DDR_PHY_ZQ0PR0_ZSEGBYP_DEFVAL #undef DDR_PHY_ZQ0PR0_ZSEGBYP_SHIFT #undef DDR_PHY_ZQ0PR0_ZSEGBYP_MASK -#define DDR_PHY_ZQ0PR0_ZSEGBYP_DEFVAL 0x000077BB -#define DDR_PHY_ZQ0PR0_ZSEGBYP_SHIFT 27 -#define DDR_PHY_ZQ0PR0_ZSEGBYP_MASK 0x08000000U +#define DDR_PHY_ZQ0PR0_ZSEGBYP_DEFVAL 0x000077BB +#define DDR_PHY_ZQ0PR0_ZSEGBYP_SHIFT 27 +#define DDR_PHY_ZQ0PR0_ZSEGBYP_MASK 0x08000000U -/*VREF latch mode controls the mode in which the ZLE pin of the PVREF cell is driven by the PUB*/ +/* +* VREF latch mode controls the mode in which the ZLE pin of the PVREF cell + * is driven by the PUB +*/ #undef DDR_PHY_ZQ0PR0_ZLE_MODE_DEFVAL #undef DDR_PHY_ZQ0PR0_ZLE_MODE_SHIFT #undef DDR_PHY_ZQ0PR0_ZLE_MODE_MASK -#define DDR_PHY_ZQ0PR0_ZLE_MODE_DEFVAL 0x000077BB -#define DDR_PHY_ZQ0PR0_ZLE_MODE_SHIFT 25 -#define DDR_PHY_ZQ0PR0_ZLE_MODE_MASK 0x06000000U +#define DDR_PHY_ZQ0PR0_ZLE_MODE_DEFVAL 0x000077BB +#define DDR_PHY_ZQ0PR0_ZLE_MODE_SHIFT 25 +#define DDR_PHY_ZQ0PR0_ZLE_MODE_MASK 0x06000000U -/*Termination adjustment*/ +/* +* Termination adjustment +*/ #undef DDR_PHY_ZQ0PR0_ODT_ADJUST_DEFVAL #undef DDR_PHY_ZQ0PR0_ODT_ADJUST_SHIFT #undef DDR_PHY_ZQ0PR0_ODT_ADJUST_MASK -#define DDR_PHY_ZQ0PR0_ODT_ADJUST_DEFVAL 0x000077BB -#define DDR_PHY_ZQ0PR0_ODT_ADJUST_SHIFT 22 -#define DDR_PHY_ZQ0PR0_ODT_ADJUST_MASK 0x01C00000U +#define DDR_PHY_ZQ0PR0_ODT_ADJUST_DEFVAL 0x000077BB +#define DDR_PHY_ZQ0PR0_ODT_ADJUST_SHIFT 22 +#define DDR_PHY_ZQ0PR0_ODT_ADJUST_MASK 0x01C00000U -/*Pulldown drive strength adjustment*/ +/* +* Pulldown drive strength adjustment +*/ #undef DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_DEFVAL #undef DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_SHIFT #undef DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_MASK -#define DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_DEFVAL 0x000077BB -#define DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_SHIFT 19 -#define DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_MASK 0x00380000U +#define DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_DEFVAL 0x000077BB +#define DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_SHIFT 19 +#define DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_MASK 0x00380000U -/*Pullup drive strength adjustment*/ +/* +* Pullup drive strength adjustment +*/ #undef DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_DEFVAL #undef DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_SHIFT #undef DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_MASK -#define DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_DEFVAL 0x000077BB -#define DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_SHIFT 16 -#define DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_MASK 0x00070000U +#define DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_DEFVAL 0x000077BB +#define DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_SHIFT 16 +#define DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_MASK 0x00070000U -/*DRAM Impedance Divide Ratio*/ +/* +* DRAM Impedance Divide Ratio +*/ #undef DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_DEFVAL #undef DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_SHIFT #undef DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_MASK -#define DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_DEFVAL 0x000077BB -#define DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_SHIFT 12 -#define DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_MASK 0x0000F000U +#define DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_DEFVAL 0x000077BB +#define DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_SHIFT 12 +#define DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_MASK 0x0000F000U -/*HOST Impedance Divide Ratio*/ +/* +* HOST Impedance Divide Ratio +*/ #undef DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_DEFVAL #undef DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_SHIFT #undef DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_MASK -#define DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_DEFVAL 0x000077BB -#define DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_SHIFT 8 -#define DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_MASK 0x00000F00U +#define DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_DEFVAL 0x000077BB +#define DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_SHIFT 8 +#define DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_MASK 0x00000F00U -/*Impedance Divide Ratio (pulldown drive calibration during asymmetric drive strength calibration)*/ +/* +* Impedance Divide Ratio (pulldown drive calibration during asymmetric dri + * ve strength calibration) +*/ #undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_DEFVAL #undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_SHIFT #undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_MASK -#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_DEFVAL 0x000077BB -#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_SHIFT 4 -#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_MASK 0x000000F0U +#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_DEFVAL 0x000077BB +#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_SHIFT 4 +#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_MASK 0x000000F0U -/*Impedance Divide Ratio (pullup drive calibration during asymmetric drive strength calibration)*/ +/* +* Impedance Divide Ratio (pullup drive calibration during asymmetric drive + * strength calibration) +*/ #undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_DEFVAL #undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_SHIFT #undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_MASK -#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_DEFVAL 0x000077BB -#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_SHIFT 0 -#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_MASK 0x0000000FU +#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_DEFVAL 0x000077BB +#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_SHIFT 0 +#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_MASK 0x0000000FU -/*Reserved. Return zeros on reads.*/ +/* +* Reserved. Return zeros on reads. +*/ #undef DDR_PHY_ZQ0OR0_RESERVED_31_26_DEFVAL #undef DDR_PHY_ZQ0OR0_RESERVED_31_26_SHIFT #undef DDR_PHY_ZQ0OR0_RESERVED_31_26_MASK -#define DDR_PHY_ZQ0OR0_RESERVED_31_26_DEFVAL 0x00000000 -#define DDR_PHY_ZQ0OR0_RESERVED_31_26_SHIFT 26 -#define DDR_PHY_ZQ0OR0_RESERVED_31_26_MASK 0xFC000000U +#define DDR_PHY_ZQ0OR0_RESERVED_31_26_DEFVAL 0x00000000 +#define DDR_PHY_ZQ0OR0_RESERVED_31_26_SHIFT 26 +#define DDR_PHY_ZQ0OR0_RESERVED_31_26_MASK 0xFC000000U -/*Override value for the pull-up output impedance*/ +/* +* Override value for the pull-up output impedance +*/ #undef DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_DEFVAL #undef DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_SHIFT #undef DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_MASK -#define DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_DEFVAL 0x00000000 -#define DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_SHIFT 16 -#define DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_MASK 0x03FF0000U +#define DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_DEFVAL 0x00000000 +#define DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_SHIFT 16 +#define DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_MASK 0x03FF0000U -/*Reserved. Return zeros on reads.*/ +/* +* Reserved. Return zeros on reads. +*/ #undef DDR_PHY_ZQ0OR0_RESERVED_15_10_DEFVAL #undef DDR_PHY_ZQ0OR0_RESERVED_15_10_SHIFT #undef DDR_PHY_ZQ0OR0_RESERVED_15_10_MASK -#define DDR_PHY_ZQ0OR0_RESERVED_15_10_DEFVAL 0x00000000 -#define DDR_PHY_ZQ0OR0_RESERVED_15_10_SHIFT 10 -#define DDR_PHY_ZQ0OR0_RESERVED_15_10_MASK 0x0000FC00U +#define DDR_PHY_ZQ0OR0_RESERVED_15_10_DEFVAL 0x00000000 +#define DDR_PHY_ZQ0OR0_RESERVED_15_10_SHIFT 10 +#define DDR_PHY_ZQ0OR0_RESERVED_15_10_MASK 0x0000FC00U -/*Override value for the pull-down output impedance*/ +/* +* Override value for the pull-down output impedance +*/ #undef DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_DEFVAL #undef DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_SHIFT #undef DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_MASK -#define DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_DEFVAL 0x00000000 -#define DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_SHIFT 0 -#define DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_MASK 0x000003FFU +#define DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_DEFVAL 0x00000000 +#define DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_SHIFT 0 +#define DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_MASK 0x000003FFU -/*Reserved. Return zeros on reads.*/ +/* +* Reserved. Return zeros on reads. +*/ #undef DDR_PHY_ZQ0OR1_RESERVED_31_26_DEFVAL #undef DDR_PHY_ZQ0OR1_RESERVED_31_26_SHIFT #undef DDR_PHY_ZQ0OR1_RESERVED_31_26_MASK -#define DDR_PHY_ZQ0OR1_RESERVED_31_26_DEFVAL 0x00000000 -#define DDR_PHY_ZQ0OR1_RESERVED_31_26_SHIFT 26 -#define DDR_PHY_ZQ0OR1_RESERVED_31_26_MASK 0xFC000000U +#define DDR_PHY_ZQ0OR1_RESERVED_31_26_DEFVAL 0x00000000 +#define DDR_PHY_ZQ0OR1_RESERVED_31_26_SHIFT 26 +#define DDR_PHY_ZQ0OR1_RESERVED_31_26_MASK 0xFC000000U -/*Override value for the pull-up termination*/ +/* +* Override value for the pull-up termination +*/ #undef DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_DEFVAL #undef DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_SHIFT #undef DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_MASK -#define DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_DEFVAL 0x00000000 -#define DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_SHIFT 16 -#define DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_MASK 0x03FF0000U +#define DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_DEFVAL 0x00000000 +#define DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_SHIFT 16 +#define DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_MASK 0x03FF0000U -/*Reserved. Return zeros on reads.*/ +/* +* Reserved. Return zeros on reads. +*/ #undef DDR_PHY_ZQ0OR1_RESERVED_15_10_DEFVAL #undef DDR_PHY_ZQ0OR1_RESERVED_15_10_SHIFT #undef DDR_PHY_ZQ0OR1_RESERVED_15_10_MASK -#define DDR_PHY_ZQ0OR1_RESERVED_15_10_DEFVAL 0x00000000 -#define DDR_PHY_ZQ0OR1_RESERVED_15_10_SHIFT 10 -#define DDR_PHY_ZQ0OR1_RESERVED_15_10_MASK 0x0000FC00U +#define DDR_PHY_ZQ0OR1_RESERVED_15_10_DEFVAL 0x00000000 +#define DDR_PHY_ZQ0OR1_RESERVED_15_10_SHIFT 10 +#define DDR_PHY_ZQ0OR1_RESERVED_15_10_MASK 0x0000FC00U -/*Override value for the pull-down termination*/ +/* +* Override value for the pull-down termination +*/ #undef DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_DEFVAL #undef DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_SHIFT #undef DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_MASK -#define DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_DEFVAL 0x00000000 -#define DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_SHIFT 0 -#define DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_MASK 0x000003FFU +#define DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_DEFVAL 0x00000000 +#define DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_SHIFT 0 +#define DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_MASK 0x000003FFU -/*Pull-down drive strength ZCTRL over-ride enable*/ +/* +* Pull-down drive strength ZCTRL over-ride enable +*/ #undef DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_DEFVAL #undef DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_SHIFT #undef DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_MASK -#define DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_DEFVAL 0x000077BB -#define DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_SHIFT 31 -#define DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_MASK 0x80000000U +#define DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_DEFVAL 0x000077BB +#define DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_SHIFT 31 +#define DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_MASK 0x80000000U -/*Pull-up drive strength ZCTRL over-ride enable*/ +/* +* Pull-up drive strength ZCTRL over-ride enable +*/ #undef DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_DEFVAL #undef DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_SHIFT #undef DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_MASK -#define DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_DEFVAL 0x000077BB -#define DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_SHIFT 30 -#define DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_MASK 0x40000000U +#define DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_DEFVAL 0x000077BB +#define DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_SHIFT 30 +#define DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_MASK 0x40000000U -/*Pull-down termination ZCTRL over-ride enable*/ +/* +* Pull-down termination ZCTRL over-ride enable +*/ #undef DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_DEFVAL #undef DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_SHIFT #undef DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_MASK -#define DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_DEFVAL 0x000077BB -#define DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_SHIFT 29 -#define DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_MASK 0x20000000U +#define DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_DEFVAL 0x000077BB +#define DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_SHIFT 29 +#define DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_MASK 0x20000000U -/*Pull-up termination ZCTRL over-ride enable*/ +/* +* Pull-up termination ZCTRL over-ride enable +*/ #undef DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_DEFVAL #undef DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_SHIFT #undef DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_MASK -#define DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_DEFVAL 0x000077BB -#define DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_SHIFT 28 -#define DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_MASK 0x10000000U +#define DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_DEFVAL 0x000077BB +#define DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_SHIFT 28 +#define DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_MASK 0x10000000U -/*Calibration segment bypass*/ +/* +* Calibration segment bypass +*/ #undef DDR_PHY_ZQ1PR0_ZSEGBYP_DEFVAL #undef DDR_PHY_ZQ1PR0_ZSEGBYP_SHIFT #undef DDR_PHY_ZQ1PR0_ZSEGBYP_MASK -#define DDR_PHY_ZQ1PR0_ZSEGBYP_DEFVAL 0x000077BB -#define DDR_PHY_ZQ1PR0_ZSEGBYP_SHIFT 27 -#define DDR_PHY_ZQ1PR0_ZSEGBYP_MASK 0x08000000U +#define DDR_PHY_ZQ1PR0_ZSEGBYP_DEFVAL 0x000077BB +#define DDR_PHY_ZQ1PR0_ZSEGBYP_SHIFT 27 +#define DDR_PHY_ZQ1PR0_ZSEGBYP_MASK 0x08000000U -/*VREF latch mode controls the mode in which the ZLE pin of the PVREF cell is driven by the PUB*/ +/* +* VREF latch mode controls the mode in which the ZLE pin of the PVREF cell + * is driven by the PUB +*/ #undef DDR_PHY_ZQ1PR0_ZLE_MODE_DEFVAL #undef DDR_PHY_ZQ1PR0_ZLE_MODE_SHIFT #undef DDR_PHY_ZQ1PR0_ZLE_MODE_MASK -#define DDR_PHY_ZQ1PR0_ZLE_MODE_DEFVAL 0x000077BB -#define DDR_PHY_ZQ1PR0_ZLE_MODE_SHIFT 25 -#define DDR_PHY_ZQ1PR0_ZLE_MODE_MASK 0x06000000U +#define DDR_PHY_ZQ1PR0_ZLE_MODE_DEFVAL 0x000077BB +#define DDR_PHY_ZQ1PR0_ZLE_MODE_SHIFT 25 +#define DDR_PHY_ZQ1PR0_ZLE_MODE_MASK 0x06000000U -/*Termination adjustment*/ +/* +* Termination adjustment +*/ #undef DDR_PHY_ZQ1PR0_ODT_ADJUST_DEFVAL #undef DDR_PHY_ZQ1PR0_ODT_ADJUST_SHIFT #undef DDR_PHY_ZQ1PR0_ODT_ADJUST_MASK -#define DDR_PHY_ZQ1PR0_ODT_ADJUST_DEFVAL 0x000077BB -#define DDR_PHY_ZQ1PR0_ODT_ADJUST_SHIFT 22 -#define DDR_PHY_ZQ1PR0_ODT_ADJUST_MASK 0x01C00000U +#define DDR_PHY_ZQ1PR0_ODT_ADJUST_DEFVAL 0x000077BB +#define DDR_PHY_ZQ1PR0_ODT_ADJUST_SHIFT 22 +#define DDR_PHY_ZQ1PR0_ODT_ADJUST_MASK 0x01C00000U -/*Pulldown drive strength adjustment*/ +/* +* Pulldown drive strength adjustment +*/ #undef DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_DEFVAL #undef DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_SHIFT #undef DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_MASK -#define DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_DEFVAL 0x000077BB -#define DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_SHIFT 19 -#define DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_MASK 0x00380000U +#define DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_DEFVAL 0x000077BB +#define DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_SHIFT 19 +#define DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_MASK 0x00380000U -/*Pullup drive strength adjustment*/ +/* +* Pullup drive strength adjustment +*/ #undef DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_DEFVAL #undef DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_SHIFT #undef DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_MASK -#define DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_DEFVAL 0x000077BB -#define DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_SHIFT 16 -#define DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_MASK 0x00070000U +#define DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_DEFVAL 0x000077BB +#define DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_SHIFT 16 +#define DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_MASK 0x00070000U -/*DRAM Impedance Divide Ratio*/ +/* +* DRAM Impedance Divide Ratio +*/ #undef DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_DEFVAL #undef DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_SHIFT #undef DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_MASK -#define DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_DEFVAL 0x000077BB -#define DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_SHIFT 12 -#define DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_MASK 0x0000F000U +#define DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_DEFVAL 0x000077BB +#define DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_SHIFT 12 +#define DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_MASK 0x0000F000U -/*HOST Impedance Divide Ratio*/ +/* +* HOST Impedance Divide Ratio +*/ #undef DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_DEFVAL #undef DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_SHIFT #undef DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_MASK -#define DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_DEFVAL 0x000077BB -#define DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_SHIFT 8 -#define DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_MASK 0x00000F00U +#define DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_DEFVAL 0x000077BB +#define DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_SHIFT 8 +#define DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_MASK 0x00000F00U -/*Impedance Divide Ratio (pulldown drive calibration during asymmetric drive strength calibration)*/ +/* +* Impedance Divide Ratio (pulldown drive calibration during asymmetric dri + * ve strength calibration) +*/ #undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_DEFVAL #undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_SHIFT #undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_MASK -#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_DEFVAL 0x000077BB -#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_SHIFT 4 -#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_MASK 0x000000F0U +#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_DEFVAL 0x000077BB +#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_SHIFT 4 +#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_MASK 0x000000F0U -/*Impedance Divide Ratio (pullup drive calibration during asymmetric drive strength calibration)*/ +/* +* Impedance Divide Ratio (pullup drive calibration during asymmetric drive + * strength calibration) +*/ #undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_DEFVAL #undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_SHIFT #undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_MASK -#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_DEFVAL 0x000077BB -#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_SHIFT 0 -#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_MASK 0x0000000FU +#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_DEFVAL 0x000077BB +#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_SHIFT 0 +#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_MASK 0x0000000FU -/*Calibration Bypass*/ +/* +* Calibration Bypass +*/ #undef DDR_PHY_DX0GCR0_CALBYP_DEFVAL #undef DDR_PHY_DX0GCR0_CALBYP_SHIFT #undef DDR_PHY_DX0GCR0_CALBYP_MASK -#define DDR_PHY_DX0GCR0_CALBYP_DEFVAL 0x40200204 -#define DDR_PHY_DX0GCR0_CALBYP_SHIFT 31 -#define DDR_PHY_DX0GCR0_CALBYP_MASK 0x80000000U +#define DDR_PHY_DX0GCR0_CALBYP_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_CALBYP_SHIFT 31 +#define DDR_PHY_DX0GCR0_CALBYP_MASK 0x80000000U -/*Master Delay Line Enable*/ +/* +* Master Delay Line Enable +*/ #undef DDR_PHY_DX0GCR0_MDLEN_DEFVAL #undef DDR_PHY_DX0GCR0_MDLEN_SHIFT #undef DDR_PHY_DX0GCR0_MDLEN_MASK -#define DDR_PHY_DX0GCR0_MDLEN_DEFVAL 0x40200204 -#define DDR_PHY_DX0GCR0_MDLEN_SHIFT 30 -#define DDR_PHY_DX0GCR0_MDLEN_MASK 0x40000000U +#define DDR_PHY_DX0GCR0_MDLEN_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_MDLEN_SHIFT 30 +#define DDR_PHY_DX0GCR0_MDLEN_MASK 0x40000000U -/*Configurable ODT(TE) Phase Shift*/ +/* +* Configurable ODT(TE) Phase Shift +*/ #undef DDR_PHY_DX0GCR0_CODTSHFT_DEFVAL #undef DDR_PHY_DX0GCR0_CODTSHFT_SHIFT #undef DDR_PHY_DX0GCR0_CODTSHFT_MASK -#define DDR_PHY_DX0GCR0_CODTSHFT_DEFVAL 0x40200204 -#define DDR_PHY_DX0GCR0_CODTSHFT_SHIFT 28 -#define DDR_PHY_DX0GCR0_CODTSHFT_MASK 0x30000000U +#define DDR_PHY_DX0GCR0_CODTSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_CODTSHFT_SHIFT 28 +#define DDR_PHY_DX0GCR0_CODTSHFT_MASK 0x30000000U -/*DQS Duty Cycle Correction*/ +/* +* DQS Duty Cycle Correction +*/ #undef DDR_PHY_DX0GCR0_DQSDCC_DEFVAL #undef DDR_PHY_DX0GCR0_DQSDCC_SHIFT #undef DDR_PHY_DX0GCR0_DQSDCC_MASK -#define DDR_PHY_DX0GCR0_DQSDCC_DEFVAL 0x40200204 -#define DDR_PHY_DX0GCR0_DQSDCC_SHIFT 24 -#define DDR_PHY_DX0GCR0_DQSDCC_MASK 0x0F000000U +#define DDR_PHY_DX0GCR0_DQSDCC_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_DQSDCC_SHIFT 24 +#define DDR_PHY_DX0GCR0_DQSDCC_MASK 0x0F000000U -/*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/ +/* +* Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY +*/ #undef DDR_PHY_DX0GCR0_RDDLY_DEFVAL #undef DDR_PHY_DX0GCR0_RDDLY_SHIFT #undef DDR_PHY_DX0GCR0_RDDLY_MASK -#define DDR_PHY_DX0GCR0_RDDLY_DEFVAL 0x40200204 -#define DDR_PHY_DX0GCR0_RDDLY_SHIFT 20 -#define DDR_PHY_DX0GCR0_RDDLY_MASK 0x00F00000U +#define DDR_PHY_DX0GCR0_RDDLY_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_RDDLY_SHIFT 20 +#define DDR_PHY_DX0GCR0_RDDLY_MASK 0x00F00000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX0GCR0_RESERVED_19_14_DEFVAL #undef DDR_PHY_DX0GCR0_RESERVED_19_14_SHIFT #undef DDR_PHY_DX0GCR0_RESERVED_19_14_MASK -#define DDR_PHY_DX0GCR0_RESERVED_19_14_DEFVAL 0x40200204 -#define DDR_PHY_DX0GCR0_RESERVED_19_14_SHIFT 14 -#define DDR_PHY_DX0GCR0_RESERVED_19_14_MASK 0x000FC000U +#define DDR_PHY_DX0GCR0_RESERVED_19_14_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_RESERVED_19_14_SHIFT 14 +#define DDR_PHY_DX0GCR0_RESERVED_19_14_MASK 0x000FC000U -/*DQSNSE Power Down Receiver*/ +/* +* DQSNSE Power Down Receiver +*/ #undef DDR_PHY_DX0GCR0_DQSNSEPDR_DEFVAL #undef DDR_PHY_DX0GCR0_DQSNSEPDR_SHIFT #undef DDR_PHY_DX0GCR0_DQSNSEPDR_MASK -#define DDR_PHY_DX0GCR0_DQSNSEPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX0GCR0_DQSNSEPDR_SHIFT 13 -#define DDR_PHY_DX0GCR0_DQSNSEPDR_MASK 0x00002000U +#define DDR_PHY_DX0GCR0_DQSNSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_DQSNSEPDR_SHIFT 13 +#define DDR_PHY_DX0GCR0_DQSNSEPDR_MASK 0x00002000U -/*DQSSE Power Down Receiver*/ +/* +* DQSSE Power Down Receiver +*/ #undef DDR_PHY_DX0GCR0_DQSSEPDR_DEFVAL #undef DDR_PHY_DX0GCR0_DQSSEPDR_SHIFT #undef DDR_PHY_DX0GCR0_DQSSEPDR_MASK -#define DDR_PHY_DX0GCR0_DQSSEPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX0GCR0_DQSSEPDR_SHIFT 12 -#define DDR_PHY_DX0GCR0_DQSSEPDR_MASK 0x00001000U +#define DDR_PHY_DX0GCR0_DQSSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_DQSSEPDR_SHIFT 12 +#define DDR_PHY_DX0GCR0_DQSSEPDR_MASK 0x00001000U -/*RTT On Additive Latency*/ +/* +* RTT On Additive Latency +*/ #undef DDR_PHY_DX0GCR0_RTTOAL_DEFVAL #undef DDR_PHY_DX0GCR0_RTTOAL_SHIFT #undef DDR_PHY_DX0GCR0_RTTOAL_MASK -#define DDR_PHY_DX0GCR0_RTTOAL_DEFVAL 0x40200204 -#define DDR_PHY_DX0GCR0_RTTOAL_SHIFT 11 -#define DDR_PHY_DX0GCR0_RTTOAL_MASK 0x00000800U +#define DDR_PHY_DX0GCR0_RTTOAL_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_RTTOAL_SHIFT 11 +#define DDR_PHY_DX0GCR0_RTTOAL_MASK 0x00000800U -/*RTT Output Hold*/ +/* +* RTT Output Hold +*/ #undef DDR_PHY_DX0GCR0_RTTOH_DEFVAL #undef DDR_PHY_DX0GCR0_RTTOH_SHIFT #undef DDR_PHY_DX0GCR0_RTTOH_MASK -#define DDR_PHY_DX0GCR0_RTTOH_DEFVAL 0x40200204 -#define DDR_PHY_DX0GCR0_RTTOH_SHIFT 9 -#define DDR_PHY_DX0GCR0_RTTOH_MASK 0x00000600U +#define DDR_PHY_DX0GCR0_RTTOH_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_RTTOH_SHIFT 9 +#define DDR_PHY_DX0GCR0_RTTOH_MASK 0x00000600U -/*Configurable PDR Phase Shift*/ +/* +* Configurable PDR Phase Shift +*/ #undef DDR_PHY_DX0GCR0_CPDRSHFT_DEFVAL #undef DDR_PHY_DX0GCR0_CPDRSHFT_SHIFT #undef DDR_PHY_DX0GCR0_CPDRSHFT_MASK -#define DDR_PHY_DX0GCR0_CPDRSHFT_DEFVAL 0x40200204 -#define DDR_PHY_DX0GCR0_CPDRSHFT_SHIFT 7 -#define DDR_PHY_DX0GCR0_CPDRSHFT_MASK 0x00000180U +#define DDR_PHY_DX0GCR0_CPDRSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_CPDRSHFT_SHIFT 7 +#define DDR_PHY_DX0GCR0_CPDRSHFT_MASK 0x00000180U -/*DQSR Power Down*/ +/* +* DQSR Power Down +*/ #undef DDR_PHY_DX0GCR0_DQSRPD_DEFVAL #undef DDR_PHY_DX0GCR0_DQSRPD_SHIFT #undef DDR_PHY_DX0GCR0_DQSRPD_MASK -#define DDR_PHY_DX0GCR0_DQSRPD_DEFVAL 0x40200204 -#define DDR_PHY_DX0GCR0_DQSRPD_SHIFT 6 -#define DDR_PHY_DX0GCR0_DQSRPD_MASK 0x00000040U +#define DDR_PHY_DX0GCR0_DQSRPD_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_DQSRPD_SHIFT 6 +#define DDR_PHY_DX0GCR0_DQSRPD_MASK 0x00000040U -/*DQSG Power Down Receiver*/ +/* +* DQSG Power Down Receiver +*/ #undef DDR_PHY_DX0GCR0_DQSGPDR_DEFVAL #undef DDR_PHY_DX0GCR0_DQSGPDR_SHIFT #undef DDR_PHY_DX0GCR0_DQSGPDR_MASK -#define DDR_PHY_DX0GCR0_DQSGPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX0GCR0_DQSGPDR_SHIFT 5 -#define DDR_PHY_DX0GCR0_DQSGPDR_MASK 0x00000020U +#define DDR_PHY_DX0GCR0_DQSGPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_DQSGPDR_SHIFT 5 +#define DDR_PHY_DX0GCR0_DQSGPDR_MASK 0x00000020U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX0GCR0_RESERVED_4_DEFVAL #undef DDR_PHY_DX0GCR0_RESERVED_4_SHIFT #undef DDR_PHY_DX0GCR0_RESERVED_4_MASK -#define DDR_PHY_DX0GCR0_RESERVED_4_DEFVAL 0x40200204 -#define DDR_PHY_DX0GCR0_RESERVED_4_SHIFT 4 -#define DDR_PHY_DX0GCR0_RESERVED_4_MASK 0x00000010U +#define DDR_PHY_DX0GCR0_RESERVED_4_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_RESERVED_4_SHIFT 4 +#define DDR_PHY_DX0GCR0_RESERVED_4_MASK 0x00000010U -/*DQSG On-Die Termination*/ +/* +* DQSG On-Die Termination +*/ #undef DDR_PHY_DX0GCR0_DQSGODT_DEFVAL #undef DDR_PHY_DX0GCR0_DQSGODT_SHIFT #undef DDR_PHY_DX0GCR0_DQSGODT_MASK -#define DDR_PHY_DX0GCR0_DQSGODT_DEFVAL 0x40200204 -#define DDR_PHY_DX0GCR0_DQSGODT_SHIFT 3 -#define DDR_PHY_DX0GCR0_DQSGODT_MASK 0x00000008U +#define DDR_PHY_DX0GCR0_DQSGODT_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_DQSGODT_SHIFT 3 +#define DDR_PHY_DX0GCR0_DQSGODT_MASK 0x00000008U -/*DQSG Output Enable*/ +/* +* DQSG Output Enable +*/ #undef DDR_PHY_DX0GCR0_DQSGOE_DEFVAL #undef DDR_PHY_DX0GCR0_DQSGOE_SHIFT #undef DDR_PHY_DX0GCR0_DQSGOE_MASK -#define DDR_PHY_DX0GCR0_DQSGOE_DEFVAL 0x40200204 -#define DDR_PHY_DX0GCR0_DQSGOE_SHIFT 2 -#define DDR_PHY_DX0GCR0_DQSGOE_MASK 0x00000004U +#define DDR_PHY_DX0GCR0_DQSGOE_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_DQSGOE_SHIFT 2 +#define DDR_PHY_DX0GCR0_DQSGOE_MASK 0x00000004U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX0GCR0_RESERVED_1_0_DEFVAL #undef DDR_PHY_DX0GCR0_RESERVED_1_0_SHIFT #undef DDR_PHY_DX0GCR0_RESERVED_1_0_MASK -#define DDR_PHY_DX0GCR0_RESERVED_1_0_DEFVAL 0x40200204 -#define DDR_PHY_DX0GCR0_RESERVED_1_0_SHIFT 0 -#define DDR_PHY_DX0GCR0_RESERVED_1_0_MASK 0x00000003U +#define DDR_PHY_DX0GCR0_RESERVED_1_0_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_RESERVED_1_0_SHIFT 0 +#define DDR_PHY_DX0GCR0_RESERVED_1_0_MASK 0x00000003U -/*Byte lane VREF IOM (Used only by D4MU IOs)*/ +/* +* Byte lane VREF IOM (Used only by D4MU IOs) +*/ #undef DDR_PHY_DX0GCR4_RESERVED_31_29_DEFVAL #undef DDR_PHY_DX0GCR4_RESERVED_31_29_SHIFT #undef DDR_PHY_DX0GCR4_RESERVED_31_29_MASK -#define DDR_PHY_DX0GCR4_RESERVED_31_29_DEFVAL 0x0E00003C -#define DDR_PHY_DX0GCR4_RESERVED_31_29_SHIFT 29 -#define DDR_PHY_DX0GCR4_RESERVED_31_29_MASK 0xE0000000U +#define DDR_PHY_DX0GCR4_RESERVED_31_29_DEFVAL 0x0E00003C +#define DDR_PHY_DX0GCR4_RESERVED_31_29_SHIFT 29 +#define DDR_PHY_DX0GCR4_RESERVED_31_29_MASK 0xE0000000U -/*Byte Lane VREF Pad Enable*/ +/* +* Byte Lane VREF Pad Enable +*/ #undef DDR_PHY_DX0GCR4_DXREFPEN_DEFVAL #undef DDR_PHY_DX0GCR4_DXREFPEN_SHIFT #undef DDR_PHY_DX0GCR4_DXREFPEN_MASK -#define DDR_PHY_DX0GCR4_DXREFPEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX0GCR4_DXREFPEN_SHIFT 28 -#define DDR_PHY_DX0GCR4_DXREFPEN_MASK 0x10000000U +#define DDR_PHY_DX0GCR4_DXREFPEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX0GCR4_DXREFPEN_SHIFT 28 +#define DDR_PHY_DX0GCR4_DXREFPEN_MASK 0x10000000U -/*Byte Lane Internal VREF Enable*/ +/* +* Byte Lane Internal VREF Enable +*/ #undef DDR_PHY_DX0GCR4_DXREFEEN_DEFVAL #undef DDR_PHY_DX0GCR4_DXREFEEN_SHIFT #undef DDR_PHY_DX0GCR4_DXREFEEN_MASK -#define DDR_PHY_DX0GCR4_DXREFEEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX0GCR4_DXREFEEN_SHIFT 26 -#define DDR_PHY_DX0GCR4_DXREFEEN_MASK 0x0C000000U +#define DDR_PHY_DX0GCR4_DXREFEEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX0GCR4_DXREFEEN_SHIFT 26 +#define DDR_PHY_DX0GCR4_DXREFEEN_MASK 0x0C000000U -/*Byte Lane Single-End VREF Enable*/ +/* +* Byte Lane Single-End VREF Enable +*/ #undef DDR_PHY_DX0GCR4_DXREFSEN_DEFVAL #undef DDR_PHY_DX0GCR4_DXREFSEN_SHIFT #undef DDR_PHY_DX0GCR4_DXREFSEN_MASK -#define DDR_PHY_DX0GCR4_DXREFSEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX0GCR4_DXREFSEN_SHIFT 25 -#define DDR_PHY_DX0GCR4_DXREFSEN_MASK 0x02000000U +#define DDR_PHY_DX0GCR4_DXREFSEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX0GCR4_DXREFSEN_SHIFT 25 +#define DDR_PHY_DX0GCR4_DXREFSEN_MASK 0x02000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX0GCR4_RESERVED_24_DEFVAL #undef DDR_PHY_DX0GCR4_RESERVED_24_SHIFT #undef DDR_PHY_DX0GCR4_RESERVED_24_MASK -#define DDR_PHY_DX0GCR4_RESERVED_24_DEFVAL 0x0E00003C -#define DDR_PHY_DX0GCR4_RESERVED_24_SHIFT 24 -#define DDR_PHY_DX0GCR4_RESERVED_24_MASK 0x01000000U +#define DDR_PHY_DX0GCR4_RESERVED_24_DEFVAL 0x0E00003C +#define DDR_PHY_DX0GCR4_RESERVED_24_SHIFT 24 +#define DDR_PHY_DX0GCR4_RESERVED_24_MASK 0x01000000U -/*External VREF generator REFSEL range select*/ +/* +* External VREF generator REFSEL range select +*/ #undef DDR_PHY_DX0GCR4_DXREFESELRANGE_DEFVAL #undef DDR_PHY_DX0GCR4_DXREFESELRANGE_SHIFT #undef DDR_PHY_DX0GCR4_DXREFESELRANGE_MASK -#define DDR_PHY_DX0GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C -#define DDR_PHY_DX0GCR4_DXREFESELRANGE_SHIFT 23 -#define DDR_PHY_DX0GCR4_DXREFESELRANGE_MASK 0x00800000U +#define DDR_PHY_DX0GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX0GCR4_DXREFESELRANGE_SHIFT 23 +#define DDR_PHY_DX0GCR4_DXREFESELRANGE_MASK 0x00800000U -/*Byte Lane External VREF Select*/ +/* +* Byte Lane External VREF Select +*/ #undef DDR_PHY_DX0GCR4_DXREFESEL_DEFVAL #undef DDR_PHY_DX0GCR4_DXREFESEL_SHIFT #undef DDR_PHY_DX0GCR4_DXREFESEL_MASK -#define DDR_PHY_DX0GCR4_DXREFESEL_DEFVAL 0x0E00003C -#define DDR_PHY_DX0GCR4_DXREFESEL_SHIFT 16 -#define DDR_PHY_DX0GCR4_DXREFESEL_MASK 0x007F0000U +#define DDR_PHY_DX0GCR4_DXREFESEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX0GCR4_DXREFESEL_SHIFT 16 +#define DDR_PHY_DX0GCR4_DXREFESEL_MASK 0x007F0000U -/*Single ended VREF generator REFSEL range select*/ +/* +* Single ended VREF generator REFSEL range select +*/ #undef DDR_PHY_DX0GCR4_DXREFSSELRANGE_DEFVAL #undef DDR_PHY_DX0GCR4_DXREFSSELRANGE_SHIFT #undef DDR_PHY_DX0GCR4_DXREFSSELRANGE_MASK -#define DDR_PHY_DX0GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C -#define DDR_PHY_DX0GCR4_DXREFSSELRANGE_SHIFT 15 -#define DDR_PHY_DX0GCR4_DXREFSSELRANGE_MASK 0x00008000U +#define DDR_PHY_DX0GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX0GCR4_DXREFSSELRANGE_SHIFT 15 +#define DDR_PHY_DX0GCR4_DXREFSSELRANGE_MASK 0x00008000U -/*Byte Lane Single-End VREF Select*/ +/* +* Byte Lane Single-End VREF Select +*/ #undef DDR_PHY_DX0GCR4_DXREFSSEL_DEFVAL #undef DDR_PHY_DX0GCR4_DXREFSSEL_SHIFT #undef DDR_PHY_DX0GCR4_DXREFSSEL_MASK -#define DDR_PHY_DX0GCR4_DXREFSSEL_DEFVAL 0x0E00003C -#define DDR_PHY_DX0GCR4_DXREFSSEL_SHIFT 8 -#define DDR_PHY_DX0GCR4_DXREFSSEL_MASK 0x00007F00U +#define DDR_PHY_DX0GCR4_DXREFSSEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX0GCR4_DXREFSSEL_SHIFT 8 +#define DDR_PHY_DX0GCR4_DXREFSSEL_MASK 0x00007F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX0GCR4_RESERVED_7_6_DEFVAL #undef DDR_PHY_DX0GCR4_RESERVED_7_6_SHIFT #undef DDR_PHY_DX0GCR4_RESERVED_7_6_MASK -#define DDR_PHY_DX0GCR4_RESERVED_7_6_DEFVAL 0x0E00003C -#define DDR_PHY_DX0GCR4_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_DX0GCR4_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_DX0GCR4_RESERVED_7_6_DEFVAL 0x0E00003C +#define DDR_PHY_DX0GCR4_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX0GCR4_RESERVED_7_6_MASK 0x000000C0U -/*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/ +/* +* VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. +*/ #undef DDR_PHY_DX0GCR4_DXREFIEN_DEFVAL #undef DDR_PHY_DX0GCR4_DXREFIEN_SHIFT #undef DDR_PHY_DX0GCR4_DXREFIEN_MASK -#define DDR_PHY_DX0GCR4_DXREFIEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX0GCR4_DXREFIEN_SHIFT 2 -#define DDR_PHY_DX0GCR4_DXREFIEN_MASK 0x0000003CU +#define DDR_PHY_DX0GCR4_DXREFIEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX0GCR4_DXREFIEN_SHIFT 2 +#define DDR_PHY_DX0GCR4_DXREFIEN_MASK 0x0000003CU -/*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/ +/* +* VRMON control for DQ IO (Single Ended) buffers of a byte lane. +*/ #undef DDR_PHY_DX0GCR4_DXREFIMON_DEFVAL #undef DDR_PHY_DX0GCR4_DXREFIMON_SHIFT #undef DDR_PHY_DX0GCR4_DXREFIMON_MASK -#define DDR_PHY_DX0GCR4_DXREFIMON_DEFVAL 0x0E00003C -#define DDR_PHY_DX0GCR4_DXREFIMON_SHIFT 0 -#define DDR_PHY_DX0GCR4_DXREFIMON_MASK 0x00000003U +#define DDR_PHY_DX0GCR4_DXREFIMON_DEFVAL 0x0E00003C +#define DDR_PHY_DX0GCR4_DXREFIMON_SHIFT 0 +#define DDR_PHY_DX0GCR4_DXREFIMON_MASK 0x00000003U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX0GCR5_RESERVED_31_DEFVAL #undef DDR_PHY_DX0GCR5_RESERVED_31_SHIFT #undef DDR_PHY_DX0GCR5_RESERVED_31_MASK -#define DDR_PHY_DX0GCR5_RESERVED_31_DEFVAL 0x09090909 -#define DDR_PHY_DX0GCR5_RESERVED_31_SHIFT 31 -#define DDR_PHY_DX0GCR5_RESERVED_31_MASK 0x80000000U +#define DDR_PHY_DX0GCR5_RESERVED_31_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR5_RESERVED_31_SHIFT 31 +#define DDR_PHY_DX0GCR5_RESERVED_31_MASK 0x80000000U -/*Byte Lane internal VREF Select for Rank 3*/ +/* +* Byte Lane internal VREF Select for Rank 3 +*/ #undef DDR_PHY_DX0GCR5_DXREFISELR3_DEFVAL #undef DDR_PHY_DX0GCR5_DXREFISELR3_SHIFT #undef DDR_PHY_DX0GCR5_DXREFISELR3_MASK -#define DDR_PHY_DX0GCR5_DXREFISELR3_DEFVAL 0x09090909 -#define DDR_PHY_DX0GCR5_DXREFISELR3_SHIFT 24 -#define DDR_PHY_DX0GCR5_DXREFISELR3_MASK 0x7F000000U +#define DDR_PHY_DX0GCR5_DXREFISELR3_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR5_DXREFISELR3_SHIFT 24 +#define DDR_PHY_DX0GCR5_DXREFISELR3_MASK 0x7F000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX0GCR5_RESERVED_23_DEFVAL #undef DDR_PHY_DX0GCR5_RESERVED_23_SHIFT #undef DDR_PHY_DX0GCR5_RESERVED_23_MASK -#define DDR_PHY_DX0GCR5_RESERVED_23_DEFVAL 0x09090909 -#define DDR_PHY_DX0GCR5_RESERVED_23_SHIFT 23 -#define DDR_PHY_DX0GCR5_RESERVED_23_MASK 0x00800000U +#define DDR_PHY_DX0GCR5_RESERVED_23_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR5_RESERVED_23_SHIFT 23 +#define DDR_PHY_DX0GCR5_RESERVED_23_MASK 0x00800000U -/*Byte Lane internal VREF Select for Rank 2*/ +/* +* Byte Lane internal VREF Select for Rank 2 +*/ #undef DDR_PHY_DX0GCR5_DXREFISELR2_DEFVAL #undef DDR_PHY_DX0GCR5_DXREFISELR2_SHIFT #undef DDR_PHY_DX0GCR5_DXREFISELR2_MASK -#define DDR_PHY_DX0GCR5_DXREFISELR2_DEFVAL 0x09090909 -#define DDR_PHY_DX0GCR5_DXREFISELR2_SHIFT 16 -#define DDR_PHY_DX0GCR5_DXREFISELR2_MASK 0x007F0000U +#define DDR_PHY_DX0GCR5_DXREFISELR2_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR5_DXREFISELR2_SHIFT 16 +#define DDR_PHY_DX0GCR5_DXREFISELR2_MASK 0x007F0000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX0GCR5_RESERVED_15_DEFVAL #undef DDR_PHY_DX0GCR5_RESERVED_15_SHIFT #undef DDR_PHY_DX0GCR5_RESERVED_15_MASK -#define DDR_PHY_DX0GCR5_RESERVED_15_DEFVAL 0x09090909 -#define DDR_PHY_DX0GCR5_RESERVED_15_SHIFT 15 -#define DDR_PHY_DX0GCR5_RESERVED_15_MASK 0x00008000U +#define DDR_PHY_DX0GCR5_RESERVED_15_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR5_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX0GCR5_RESERVED_15_MASK 0x00008000U -/*Byte Lane internal VREF Select for Rank 1*/ +/* +* Byte Lane internal VREF Select for Rank 1 +*/ #undef DDR_PHY_DX0GCR5_DXREFISELR1_DEFVAL #undef DDR_PHY_DX0GCR5_DXREFISELR1_SHIFT #undef DDR_PHY_DX0GCR5_DXREFISELR1_MASK -#define DDR_PHY_DX0GCR5_DXREFISELR1_DEFVAL 0x09090909 -#define DDR_PHY_DX0GCR5_DXREFISELR1_SHIFT 8 -#define DDR_PHY_DX0GCR5_DXREFISELR1_MASK 0x00007F00U +#define DDR_PHY_DX0GCR5_DXREFISELR1_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR5_DXREFISELR1_SHIFT 8 +#define DDR_PHY_DX0GCR5_DXREFISELR1_MASK 0x00007F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX0GCR5_RESERVED_7_DEFVAL #undef DDR_PHY_DX0GCR5_RESERVED_7_SHIFT #undef DDR_PHY_DX0GCR5_RESERVED_7_MASK -#define DDR_PHY_DX0GCR5_RESERVED_7_DEFVAL 0x09090909 -#define DDR_PHY_DX0GCR5_RESERVED_7_SHIFT 7 -#define DDR_PHY_DX0GCR5_RESERVED_7_MASK 0x00000080U +#define DDR_PHY_DX0GCR5_RESERVED_7_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR5_RESERVED_7_SHIFT 7 +#define DDR_PHY_DX0GCR5_RESERVED_7_MASK 0x00000080U -/*Byte Lane internal VREF Select for Rank 0*/ +/* +* Byte Lane internal VREF Select for Rank 0 +*/ #undef DDR_PHY_DX0GCR5_DXREFISELR0_DEFVAL #undef DDR_PHY_DX0GCR5_DXREFISELR0_SHIFT #undef DDR_PHY_DX0GCR5_DXREFISELR0_MASK -#define DDR_PHY_DX0GCR5_DXREFISELR0_DEFVAL 0x09090909 -#define DDR_PHY_DX0GCR5_DXREFISELR0_SHIFT 0 -#define DDR_PHY_DX0GCR5_DXREFISELR0_MASK 0x0000007FU +#define DDR_PHY_DX0GCR5_DXREFISELR0_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR5_DXREFISELR0_SHIFT 0 +#define DDR_PHY_DX0GCR5_DXREFISELR0_MASK 0x0000007FU -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX0GCR6_RESERVED_31_30_DEFVAL #undef DDR_PHY_DX0GCR6_RESERVED_31_30_SHIFT #undef DDR_PHY_DX0GCR6_RESERVED_31_30_MASK -#define DDR_PHY_DX0GCR6_RESERVED_31_30_DEFVAL 0x09090909 -#define DDR_PHY_DX0GCR6_RESERVED_31_30_SHIFT 30 -#define DDR_PHY_DX0GCR6_RESERVED_31_30_MASK 0xC0000000U +#define DDR_PHY_DX0GCR6_RESERVED_31_30_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR6_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX0GCR6_RESERVED_31_30_MASK 0xC0000000U -/*DRAM DQ VREF Select for Rank3*/ +/* +* DRAM DQ VREF Select for Rank3 +*/ #undef DDR_PHY_DX0GCR6_DXDQVREFR3_DEFVAL #undef DDR_PHY_DX0GCR6_DXDQVREFR3_SHIFT #undef DDR_PHY_DX0GCR6_DXDQVREFR3_MASK -#define DDR_PHY_DX0GCR6_DXDQVREFR3_DEFVAL 0x09090909 -#define DDR_PHY_DX0GCR6_DXDQVREFR3_SHIFT 24 -#define DDR_PHY_DX0GCR6_DXDQVREFR3_MASK 0x3F000000U +#define DDR_PHY_DX0GCR6_DXDQVREFR3_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR6_DXDQVREFR3_SHIFT 24 +#define DDR_PHY_DX0GCR6_DXDQVREFR3_MASK 0x3F000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX0GCR6_RESERVED_23_22_DEFVAL #undef DDR_PHY_DX0GCR6_RESERVED_23_22_SHIFT #undef DDR_PHY_DX0GCR6_RESERVED_23_22_MASK -#define DDR_PHY_DX0GCR6_RESERVED_23_22_DEFVAL 0x09090909 -#define DDR_PHY_DX0GCR6_RESERVED_23_22_SHIFT 22 -#define DDR_PHY_DX0GCR6_RESERVED_23_22_MASK 0x00C00000U +#define DDR_PHY_DX0GCR6_RESERVED_23_22_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR6_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX0GCR6_RESERVED_23_22_MASK 0x00C00000U -/*DRAM DQ VREF Select for Rank2*/ +/* +* DRAM DQ VREF Select for Rank2 +*/ #undef DDR_PHY_DX0GCR6_DXDQVREFR2_DEFVAL #undef DDR_PHY_DX0GCR6_DXDQVREFR2_SHIFT #undef DDR_PHY_DX0GCR6_DXDQVREFR2_MASK -#define DDR_PHY_DX0GCR6_DXDQVREFR2_DEFVAL 0x09090909 -#define DDR_PHY_DX0GCR6_DXDQVREFR2_SHIFT 16 -#define DDR_PHY_DX0GCR6_DXDQVREFR2_MASK 0x003F0000U +#define DDR_PHY_DX0GCR6_DXDQVREFR2_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR6_DXDQVREFR2_SHIFT 16 +#define DDR_PHY_DX0GCR6_DXDQVREFR2_MASK 0x003F0000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX0GCR6_RESERVED_15_14_DEFVAL #undef DDR_PHY_DX0GCR6_RESERVED_15_14_SHIFT #undef DDR_PHY_DX0GCR6_RESERVED_15_14_MASK -#define DDR_PHY_DX0GCR6_RESERVED_15_14_DEFVAL 0x09090909 -#define DDR_PHY_DX0GCR6_RESERVED_15_14_SHIFT 14 -#define DDR_PHY_DX0GCR6_RESERVED_15_14_MASK 0x0000C000U +#define DDR_PHY_DX0GCR6_RESERVED_15_14_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR6_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_DX0GCR6_RESERVED_15_14_MASK 0x0000C000U -/*DRAM DQ VREF Select for Rank1*/ +/* +* DRAM DQ VREF Select for Rank1 +*/ #undef DDR_PHY_DX0GCR6_DXDQVREFR1_DEFVAL #undef DDR_PHY_DX0GCR6_DXDQVREFR1_SHIFT #undef DDR_PHY_DX0GCR6_DXDQVREFR1_MASK -#define DDR_PHY_DX0GCR6_DXDQVREFR1_DEFVAL 0x09090909 -#define DDR_PHY_DX0GCR6_DXDQVREFR1_SHIFT 8 -#define DDR_PHY_DX0GCR6_DXDQVREFR1_MASK 0x00003F00U +#define DDR_PHY_DX0GCR6_DXDQVREFR1_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR6_DXDQVREFR1_SHIFT 8 +#define DDR_PHY_DX0GCR6_DXDQVREFR1_MASK 0x00003F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX0GCR6_RESERVED_7_6_DEFVAL #undef DDR_PHY_DX0GCR6_RESERVED_7_6_SHIFT #undef DDR_PHY_DX0GCR6_RESERVED_7_6_MASK -#define DDR_PHY_DX0GCR6_RESERVED_7_6_DEFVAL 0x09090909 -#define DDR_PHY_DX0GCR6_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_DX0GCR6_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_DX0GCR6_RESERVED_7_6_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR6_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX0GCR6_RESERVED_7_6_MASK 0x000000C0U -/*DRAM DQ VREF Select for Rank0*/ +/* +* DRAM DQ VREF Select for Rank0 +*/ #undef DDR_PHY_DX0GCR6_DXDQVREFR0_DEFVAL #undef DDR_PHY_DX0GCR6_DXDQVREFR0_SHIFT #undef DDR_PHY_DX0GCR6_DXDQVREFR0_MASK -#define DDR_PHY_DX0GCR6_DXDQVREFR0_DEFVAL 0x09090909 -#define DDR_PHY_DX0GCR6_DXDQVREFR0_SHIFT 0 -#define DDR_PHY_DX0GCR6_DXDQVREFR0_MASK 0x0000003FU +#define DDR_PHY_DX0GCR6_DXDQVREFR0_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR6_DXDQVREFR0_SHIFT 0 +#define DDR_PHY_DX0GCR6_DXDQVREFR0_MASK 0x0000003FU -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX0LCDLR2_RESERVED_31_25_DEFVAL -#undef DDR_PHY_DX0LCDLR2_RESERVED_31_25_SHIFT -#undef DDR_PHY_DX0LCDLR2_RESERVED_31_25_MASK -#define DDR_PHY_DX0LCDLR2_RESERVED_31_25_DEFVAL 0x00000000 -#define DDR_PHY_DX0LCDLR2_RESERVED_31_25_SHIFT 25 -#define DDR_PHY_DX0LCDLR2_RESERVED_31_25_MASK 0xFE000000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX0LCDLR2_RESERVED_24_16_DEFVAL -#undef DDR_PHY_DX0LCDLR2_RESERVED_24_16_SHIFT -#undef DDR_PHY_DX0LCDLR2_RESERVED_24_16_MASK -#define DDR_PHY_DX0LCDLR2_RESERVED_24_16_DEFVAL 0x00000000 -#define DDR_PHY_DX0LCDLR2_RESERVED_24_16_SHIFT 16 -#define DDR_PHY_DX0LCDLR2_RESERVED_24_16_MASK 0x01FF0000U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX0LCDLR2_RESERVED_15_9_DEFVAL -#undef DDR_PHY_DX0LCDLR2_RESERVED_15_9_SHIFT -#undef DDR_PHY_DX0LCDLR2_RESERVED_15_9_MASK -#define DDR_PHY_DX0LCDLR2_RESERVED_15_9_DEFVAL 0x00000000 -#define DDR_PHY_DX0LCDLR2_RESERVED_15_9_SHIFT 9 -#define DDR_PHY_DX0LCDLR2_RESERVED_15_9_MASK 0x0000FE00U - -/*Read DQS Gating Delay*/ -#undef DDR_PHY_DX0LCDLR2_DQSGD_DEFVAL -#undef DDR_PHY_DX0LCDLR2_DQSGD_SHIFT -#undef DDR_PHY_DX0LCDLR2_DQSGD_MASK -#define DDR_PHY_DX0LCDLR2_DQSGD_DEFVAL 0x00000000 -#define DDR_PHY_DX0LCDLR2_DQSGD_SHIFT 0 -#define DDR_PHY_DX0LCDLR2_DQSGD_MASK 0x000001FFU - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX0GTR0_RESERVED_31_24_DEFVAL -#undef DDR_PHY_DX0GTR0_RESERVED_31_24_SHIFT -#undef DDR_PHY_DX0GTR0_RESERVED_31_24_MASK -#define DDR_PHY_DX0GTR0_RESERVED_31_24_DEFVAL 0x00020000 -#define DDR_PHY_DX0GTR0_RESERVED_31_24_SHIFT 27 -#define DDR_PHY_DX0GTR0_RESERVED_31_24_MASK 0xF8000000U - -/*DQ Write Path Latency Pipeline*/ -#undef DDR_PHY_DX0GTR0_WDQSL_DEFVAL -#undef DDR_PHY_DX0GTR0_WDQSL_SHIFT -#undef DDR_PHY_DX0GTR0_WDQSL_MASK -#define DDR_PHY_DX0GTR0_WDQSL_DEFVAL 0x00020000 -#define DDR_PHY_DX0GTR0_WDQSL_SHIFT 24 -#define DDR_PHY_DX0GTR0_WDQSL_MASK 0x07000000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX0GTR0_RESERVED_23_20_DEFVAL -#undef DDR_PHY_DX0GTR0_RESERVED_23_20_SHIFT -#undef DDR_PHY_DX0GTR0_RESERVED_23_20_MASK -#define DDR_PHY_DX0GTR0_RESERVED_23_20_DEFVAL 0x00020000 -#define DDR_PHY_DX0GTR0_RESERVED_23_20_SHIFT 20 -#define DDR_PHY_DX0GTR0_RESERVED_23_20_MASK 0x00F00000U - -/*Write Leveling System Latency*/ -#undef DDR_PHY_DX0GTR0_WLSL_DEFVAL -#undef DDR_PHY_DX0GTR0_WLSL_SHIFT -#undef DDR_PHY_DX0GTR0_WLSL_MASK -#define DDR_PHY_DX0GTR0_WLSL_DEFVAL 0x00020000 -#define DDR_PHY_DX0GTR0_WLSL_SHIFT 16 -#define DDR_PHY_DX0GTR0_WLSL_MASK 0x000F0000U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX0GTR0_RESERVED_15_13_DEFVAL -#undef DDR_PHY_DX0GTR0_RESERVED_15_13_SHIFT -#undef DDR_PHY_DX0GTR0_RESERVED_15_13_MASK -#define DDR_PHY_DX0GTR0_RESERVED_15_13_DEFVAL 0x00020000 -#define DDR_PHY_DX0GTR0_RESERVED_15_13_SHIFT 13 -#define DDR_PHY_DX0GTR0_RESERVED_15_13_MASK 0x0000E000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX0GTR0_RESERVED_12_8_DEFVAL -#undef DDR_PHY_DX0GTR0_RESERVED_12_8_SHIFT -#undef DDR_PHY_DX0GTR0_RESERVED_12_8_MASK -#define DDR_PHY_DX0GTR0_RESERVED_12_8_DEFVAL 0x00020000 -#define DDR_PHY_DX0GTR0_RESERVED_12_8_SHIFT 8 -#define DDR_PHY_DX0GTR0_RESERVED_12_8_MASK 0x00001F00U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX0GTR0_RESERVED_7_5_DEFVAL -#undef DDR_PHY_DX0GTR0_RESERVED_7_5_SHIFT -#undef DDR_PHY_DX0GTR0_RESERVED_7_5_MASK -#define DDR_PHY_DX0GTR0_RESERVED_7_5_DEFVAL 0x00020000 -#define DDR_PHY_DX0GTR0_RESERVED_7_5_SHIFT 5 -#define DDR_PHY_DX0GTR0_RESERVED_7_5_MASK 0x000000E0U - -/*DQS Gating System Latency*/ -#undef DDR_PHY_DX0GTR0_DGSL_DEFVAL -#undef DDR_PHY_DX0GTR0_DGSL_SHIFT -#undef DDR_PHY_DX0GTR0_DGSL_MASK -#define DDR_PHY_DX0GTR0_DGSL_DEFVAL 0x00020000 -#define DDR_PHY_DX0GTR0_DGSL_SHIFT 0 -#define DDR_PHY_DX0GTR0_DGSL_MASK 0x0000001FU - -/*Calibration Bypass*/ +/* +* Calibration Bypass +*/ #undef DDR_PHY_DX1GCR0_CALBYP_DEFVAL #undef DDR_PHY_DX1GCR0_CALBYP_SHIFT #undef DDR_PHY_DX1GCR0_CALBYP_MASK -#define DDR_PHY_DX1GCR0_CALBYP_DEFVAL 0x40200204 -#define DDR_PHY_DX1GCR0_CALBYP_SHIFT 31 -#define DDR_PHY_DX1GCR0_CALBYP_MASK 0x80000000U +#define DDR_PHY_DX1GCR0_CALBYP_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_CALBYP_SHIFT 31 +#define DDR_PHY_DX1GCR0_CALBYP_MASK 0x80000000U -/*Master Delay Line Enable*/ +/* +* Master Delay Line Enable +*/ #undef DDR_PHY_DX1GCR0_MDLEN_DEFVAL #undef DDR_PHY_DX1GCR0_MDLEN_SHIFT #undef DDR_PHY_DX1GCR0_MDLEN_MASK -#define DDR_PHY_DX1GCR0_MDLEN_DEFVAL 0x40200204 -#define DDR_PHY_DX1GCR0_MDLEN_SHIFT 30 -#define DDR_PHY_DX1GCR0_MDLEN_MASK 0x40000000U +#define DDR_PHY_DX1GCR0_MDLEN_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_MDLEN_SHIFT 30 +#define DDR_PHY_DX1GCR0_MDLEN_MASK 0x40000000U -/*Configurable ODT(TE) Phase Shift*/ +/* +* Configurable ODT(TE) Phase Shift +*/ #undef DDR_PHY_DX1GCR0_CODTSHFT_DEFVAL #undef DDR_PHY_DX1GCR0_CODTSHFT_SHIFT #undef DDR_PHY_DX1GCR0_CODTSHFT_MASK -#define DDR_PHY_DX1GCR0_CODTSHFT_DEFVAL 0x40200204 -#define DDR_PHY_DX1GCR0_CODTSHFT_SHIFT 28 -#define DDR_PHY_DX1GCR0_CODTSHFT_MASK 0x30000000U +#define DDR_PHY_DX1GCR0_CODTSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_CODTSHFT_SHIFT 28 +#define DDR_PHY_DX1GCR0_CODTSHFT_MASK 0x30000000U -/*DQS Duty Cycle Correction*/ +/* +* DQS Duty Cycle Correction +*/ #undef DDR_PHY_DX1GCR0_DQSDCC_DEFVAL #undef DDR_PHY_DX1GCR0_DQSDCC_SHIFT #undef DDR_PHY_DX1GCR0_DQSDCC_MASK -#define DDR_PHY_DX1GCR0_DQSDCC_DEFVAL 0x40200204 -#define DDR_PHY_DX1GCR0_DQSDCC_SHIFT 24 -#define DDR_PHY_DX1GCR0_DQSDCC_MASK 0x0F000000U +#define DDR_PHY_DX1GCR0_DQSDCC_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_DQSDCC_SHIFT 24 +#define DDR_PHY_DX1GCR0_DQSDCC_MASK 0x0F000000U -/*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/ +/* +* Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY +*/ #undef DDR_PHY_DX1GCR0_RDDLY_DEFVAL #undef DDR_PHY_DX1GCR0_RDDLY_SHIFT #undef DDR_PHY_DX1GCR0_RDDLY_MASK -#define DDR_PHY_DX1GCR0_RDDLY_DEFVAL 0x40200204 -#define DDR_PHY_DX1GCR0_RDDLY_SHIFT 20 -#define DDR_PHY_DX1GCR0_RDDLY_MASK 0x00F00000U +#define DDR_PHY_DX1GCR0_RDDLY_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_RDDLY_SHIFT 20 +#define DDR_PHY_DX1GCR0_RDDLY_MASK 0x00F00000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX1GCR0_RESERVED_19_14_DEFVAL #undef DDR_PHY_DX1GCR0_RESERVED_19_14_SHIFT #undef DDR_PHY_DX1GCR0_RESERVED_19_14_MASK -#define DDR_PHY_DX1GCR0_RESERVED_19_14_DEFVAL 0x40200204 -#define DDR_PHY_DX1GCR0_RESERVED_19_14_SHIFT 14 -#define DDR_PHY_DX1GCR0_RESERVED_19_14_MASK 0x000FC000U +#define DDR_PHY_DX1GCR0_RESERVED_19_14_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_RESERVED_19_14_SHIFT 14 +#define DDR_PHY_DX1GCR0_RESERVED_19_14_MASK 0x000FC000U -/*DQSNSE Power Down Receiver*/ +/* +* DQSNSE Power Down Receiver +*/ #undef DDR_PHY_DX1GCR0_DQSNSEPDR_DEFVAL #undef DDR_PHY_DX1GCR0_DQSNSEPDR_SHIFT #undef DDR_PHY_DX1GCR0_DQSNSEPDR_MASK -#define DDR_PHY_DX1GCR0_DQSNSEPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX1GCR0_DQSNSEPDR_SHIFT 13 -#define DDR_PHY_DX1GCR0_DQSNSEPDR_MASK 0x00002000U +#define DDR_PHY_DX1GCR0_DQSNSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_DQSNSEPDR_SHIFT 13 +#define DDR_PHY_DX1GCR0_DQSNSEPDR_MASK 0x00002000U -/*DQSSE Power Down Receiver*/ +/* +* DQSSE Power Down Receiver +*/ #undef DDR_PHY_DX1GCR0_DQSSEPDR_DEFVAL #undef DDR_PHY_DX1GCR0_DQSSEPDR_SHIFT #undef DDR_PHY_DX1GCR0_DQSSEPDR_MASK -#define DDR_PHY_DX1GCR0_DQSSEPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX1GCR0_DQSSEPDR_SHIFT 12 -#define DDR_PHY_DX1GCR0_DQSSEPDR_MASK 0x00001000U +#define DDR_PHY_DX1GCR0_DQSSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_DQSSEPDR_SHIFT 12 +#define DDR_PHY_DX1GCR0_DQSSEPDR_MASK 0x00001000U -/*RTT On Additive Latency*/ +/* +* RTT On Additive Latency +*/ #undef DDR_PHY_DX1GCR0_RTTOAL_DEFVAL #undef DDR_PHY_DX1GCR0_RTTOAL_SHIFT #undef DDR_PHY_DX1GCR0_RTTOAL_MASK -#define DDR_PHY_DX1GCR0_RTTOAL_DEFVAL 0x40200204 -#define DDR_PHY_DX1GCR0_RTTOAL_SHIFT 11 -#define DDR_PHY_DX1GCR0_RTTOAL_MASK 0x00000800U +#define DDR_PHY_DX1GCR0_RTTOAL_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_RTTOAL_SHIFT 11 +#define DDR_PHY_DX1GCR0_RTTOAL_MASK 0x00000800U -/*RTT Output Hold*/ +/* +* RTT Output Hold +*/ #undef DDR_PHY_DX1GCR0_RTTOH_DEFVAL #undef DDR_PHY_DX1GCR0_RTTOH_SHIFT #undef DDR_PHY_DX1GCR0_RTTOH_MASK -#define DDR_PHY_DX1GCR0_RTTOH_DEFVAL 0x40200204 -#define DDR_PHY_DX1GCR0_RTTOH_SHIFT 9 -#define DDR_PHY_DX1GCR0_RTTOH_MASK 0x00000600U +#define DDR_PHY_DX1GCR0_RTTOH_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_RTTOH_SHIFT 9 +#define DDR_PHY_DX1GCR0_RTTOH_MASK 0x00000600U -/*Configurable PDR Phase Shift*/ +/* +* Configurable PDR Phase Shift +*/ #undef DDR_PHY_DX1GCR0_CPDRSHFT_DEFVAL #undef DDR_PHY_DX1GCR0_CPDRSHFT_SHIFT #undef DDR_PHY_DX1GCR0_CPDRSHFT_MASK -#define DDR_PHY_DX1GCR0_CPDRSHFT_DEFVAL 0x40200204 -#define DDR_PHY_DX1GCR0_CPDRSHFT_SHIFT 7 -#define DDR_PHY_DX1GCR0_CPDRSHFT_MASK 0x00000180U +#define DDR_PHY_DX1GCR0_CPDRSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_CPDRSHFT_SHIFT 7 +#define DDR_PHY_DX1GCR0_CPDRSHFT_MASK 0x00000180U -/*DQSR Power Down*/ +/* +* DQSR Power Down +*/ #undef DDR_PHY_DX1GCR0_DQSRPD_DEFVAL #undef DDR_PHY_DX1GCR0_DQSRPD_SHIFT #undef DDR_PHY_DX1GCR0_DQSRPD_MASK -#define DDR_PHY_DX1GCR0_DQSRPD_DEFVAL 0x40200204 -#define DDR_PHY_DX1GCR0_DQSRPD_SHIFT 6 -#define DDR_PHY_DX1GCR0_DQSRPD_MASK 0x00000040U +#define DDR_PHY_DX1GCR0_DQSRPD_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_DQSRPD_SHIFT 6 +#define DDR_PHY_DX1GCR0_DQSRPD_MASK 0x00000040U -/*DQSG Power Down Receiver*/ +/* +* DQSG Power Down Receiver +*/ #undef DDR_PHY_DX1GCR0_DQSGPDR_DEFVAL #undef DDR_PHY_DX1GCR0_DQSGPDR_SHIFT #undef DDR_PHY_DX1GCR0_DQSGPDR_MASK -#define DDR_PHY_DX1GCR0_DQSGPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX1GCR0_DQSGPDR_SHIFT 5 -#define DDR_PHY_DX1GCR0_DQSGPDR_MASK 0x00000020U +#define DDR_PHY_DX1GCR0_DQSGPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_DQSGPDR_SHIFT 5 +#define DDR_PHY_DX1GCR0_DQSGPDR_MASK 0x00000020U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX1GCR0_RESERVED_4_DEFVAL #undef DDR_PHY_DX1GCR0_RESERVED_4_SHIFT #undef DDR_PHY_DX1GCR0_RESERVED_4_MASK -#define DDR_PHY_DX1GCR0_RESERVED_4_DEFVAL 0x40200204 -#define DDR_PHY_DX1GCR0_RESERVED_4_SHIFT 4 -#define DDR_PHY_DX1GCR0_RESERVED_4_MASK 0x00000010U +#define DDR_PHY_DX1GCR0_RESERVED_4_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_RESERVED_4_SHIFT 4 +#define DDR_PHY_DX1GCR0_RESERVED_4_MASK 0x00000010U -/*DQSG On-Die Termination*/ +/* +* DQSG On-Die Termination +*/ #undef DDR_PHY_DX1GCR0_DQSGODT_DEFVAL #undef DDR_PHY_DX1GCR0_DQSGODT_SHIFT #undef DDR_PHY_DX1GCR0_DQSGODT_MASK -#define DDR_PHY_DX1GCR0_DQSGODT_DEFVAL 0x40200204 -#define DDR_PHY_DX1GCR0_DQSGODT_SHIFT 3 -#define DDR_PHY_DX1GCR0_DQSGODT_MASK 0x00000008U +#define DDR_PHY_DX1GCR0_DQSGODT_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_DQSGODT_SHIFT 3 +#define DDR_PHY_DX1GCR0_DQSGODT_MASK 0x00000008U -/*DQSG Output Enable*/ +/* +* DQSG Output Enable +*/ #undef DDR_PHY_DX1GCR0_DQSGOE_DEFVAL #undef DDR_PHY_DX1GCR0_DQSGOE_SHIFT #undef DDR_PHY_DX1GCR0_DQSGOE_MASK -#define DDR_PHY_DX1GCR0_DQSGOE_DEFVAL 0x40200204 -#define DDR_PHY_DX1GCR0_DQSGOE_SHIFT 2 -#define DDR_PHY_DX1GCR0_DQSGOE_MASK 0x00000004U +#define DDR_PHY_DX1GCR0_DQSGOE_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_DQSGOE_SHIFT 2 +#define DDR_PHY_DX1GCR0_DQSGOE_MASK 0x00000004U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX1GCR0_RESERVED_1_0_DEFVAL #undef DDR_PHY_DX1GCR0_RESERVED_1_0_SHIFT #undef DDR_PHY_DX1GCR0_RESERVED_1_0_MASK -#define DDR_PHY_DX1GCR0_RESERVED_1_0_DEFVAL 0x40200204 -#define DDR_PHY_DX1GCR0_RESERVED_1_0_SHIFT 0 -#define DDR_PHY_DX1GCR0_RESERVED_1_0_MASK 0x00000003U +#define DDR_PHY_DX1GCR0_RESERVED_1_0_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_RESERVED_1_0_SHIFT 0 +#define DDR_PHY_DX1GCR0_RESERVED_1_0_MASK 0x00000003U -/*Byte lane VREF IOM (Used only by D4MU IOs)*/ +/* +* Byte lane VREF IOM (Used only by D4MU IOs) +*/ #undef DDR_PHY_DX1GCR4_RESERVED_31_29_DEFVAL #undef DDR_PHY_DX1GCR4_RESERVED_31_29_SHIFT #undef DDR_PHY_DX1GCR4_RESERVED_31_29_MASK -#define DDR_PHY_DX1GCR4_RESERVED_31_29_DEFVAL 0x0E00003C -#define DDR_PHY_DX1GCR4_RESERVED_31_29_SHIFT 29 -#define DDR_PHY_DX1GCR4_RESERVED_31_29_MASK 0xE0000000U +#define DDR_PHY_DX1GCR4_RESERVED_31_29_DEFVAL 0x0E00003C +#define DDR_PHY_DX1GCR4_RESERVED_31_29_SHIFT 29 +#define DDR_PHY_DX1GCR4_RESERVED_31_29_MASK 0xE0000000U -/*Byte Lane VREF Pad Enable*/ +/* +* Byte Lane VREF Pad Enable +*/ #undef DDR_PHY_DX1GCR4_DXREFPEN_DEFVAL #undef DDR_PHY_DX1GCR4_DXREFPEN_SHIFT #undef DDR_PHY_DX1GCR4_DXREFPEN_MASK -#define DDR_PHY_DX1GCR4_DXREFPEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX1GCR4_DXREFPEN_SHIFT 28 -#define DDR_PHY_DX1GCR4_DXREFPEN_MASK 0x10000000U +#define DDR_PHY_DX1GCR4_DXREFPEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX1GCR4_DXREFPEN_SHIFT 28 +#define DDR_PHY_DX1GCR4_DXREFPEN_MASK 0x10000000U -/*Byte Lane Internal VREF Enable*/ +/* +* Byte Lane Internal VREF Enable +*/ #undef DDR_PHY_DX1GCR4_DXREFEEN_DEFVAL #undef DDR_PHY_DX1GCR4_DXREFEEN_SHIFT #undef DDR_PHY_DX1GCR4_DXREFEEN_MASK -#define DDR_PHY_DX1GCR4_DXREFEEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX1GCR4_DXREFEEN_SHIFT 26 -#define DDR_PHY_DX1GCR4_DXREFEEN_MASK 0x0C000000U +#define DDR_PHY_DX1GCR4_DXREFEEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX1GCR4_DXREFEEN_SHIFT 26 +#define DDR_PHY_DX1GCR4_DXREFEEN_MASK 0x0C000000U -/*Byte Lane Single-End VREF Enable*/ +/* +* Byte Lane Single-End VREF Enable +*/ #undef DDR_PHY_DX1GCR4_DXREFSEN_DEFVAL #undef DDR_PHY_DX1GCR4_DXREFSEN_SHIFT #undef DDR_PHY_DX1GCR4_DXREFSEN_MASK -#define DDR_PHY_DX1GCR4_DXREFSEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX1GCR4_DXREFSEN_SHIFT 25 -#define DDR_PHY_DX1GCR4_DXREFSEN_MASK 0x02000000U +#define DDR_PHY_DX1GCR4_DXREFSEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX1GCR4_DXREFSEN_SHIFT 25 +#define DDR_PHY_DX1GCR4_DXREFSEN_MASK 0x02000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX1GCR4_RESERVED_24_DEFVAL #undef DDR_PHY_DX1GCR4_RESERVED_24_SHIFT #undef DDR_PHY_DX1GCR4_RESERVED_24_MASK -#define DDR_PHY_DX1GCR4_RESERVED_24_DEFVAL 0x0E00003C -#define DDR_PHY_DX1GCR4_RESERVED_24_SHIFT 24 -#define DDR_PHY_DX1GCR4_RESERVED_24_MASK 0x01000000U +#define DDR_PHY_DX1GCR4_RESERVED_24_DEFVAL 0x0E00003C +#define DDR_PHY_DX1GCR4_RESERVED_24_SHIFT 24 +#define DDR_PHY_DX1GCR4_RESERVED_24_MASK 0x01000000U -/*External VREF generator REFSEL range select*/ +/* +* External VREF generator REFSEL range select +*/ #undef DDR_PHY_DX1GCR4_DXREFESELRANGE_DEFVAL #undef DDR_PHY_DX1GCR4_DXREFESELRANGE_SHIFT #undef DDR_PHY_DX1GCR4_DXREFESELRANGE_MASK -#define DDR_PHY_DX1GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C -#define DDR_PHY_DX1GCR4_DXREFESELRANGE_SHIFT 23 -#define DDR_PHY_DX1GCR4_DXREFESELRANGE_MASK 0x00800000U +#define DDR_PHY_DX1GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX1GCR4_DXREFESELRANGE_SHIFT 23 +#define DDR_PHY_DX1GCR4_DXREFESELRANGE_MASK 0x00800000U -/*Byte Lane External VREF Select*/ +/* +* Byte Lane External VREF Select +*/ #undef DDR_PHY_DX1GCR4_DXREFESEL_DEFVAL #undef DDR_PHY_DX1GCR4_DXREFESEL_SHIFT #undef DDR_PHY_DX1GCR4_DXREFESEL_MASK -#define DDR_PHY_DX1GCR4_DXREFESEL_DEFVAL 0x0E00003C -#define DDR_PHY_DX1GCR4_DXREFESEL_SHIFT 16 -#define DDR_PHY_DX1GCR4_DXREFESEL_MASK 0x007F0000U +#define DDR_PHY_DX1GCR4_DXREFESEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX1GCR4_DXREFESEL_SHIFT 16 +#define DDR_PHY_DX1GCR4_DXREFESEL_MASK 0x007F0000U -/*Single ended VREF generator REFSEL range select*/ +/* +* Single ended VREF generator REFSEL range select +*/ #undef DDR_PHY_DX1GCR4_DXREFSSELRANGE_DEFVAL #undef DDR_PHY_DX1GCR4_DXREFSSELRANGE_SHIFT #undef DDR_PHY_DX1GCR4_DXREFSSELRANGE_MASK -#define DDR_PHY_DX1GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C -#define DDR_PHY_DX1GCR4_DXREFSSELRANGE_SHIFT 15 -#define DDR_PHY_DX1GCR4_DXREFSSELRANGE_MASK 0x00008000U +#define DDR_PHY_DX1GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX1GCR4_DXREFSSELRANGE_SHIFT 15 +#define DDR_PHY_DX1GCR4_DXREFSSELRANGE_MASK 0x00008000U -/*Byte Lane Single-End VREF Select*/ +/* +* Byte Lane Single-End VREF Select +*/ #undef DDR_PHY_DX1GCR4_DXREFSSEL_DEFVAL #undef DDR_PHY_DX1GCR4_DXREFSSEL_SHIFT #undef DDR_PHY_DX1GCR4_DXREFSSEL_MASK -#define DDR_PHY_DX1GCR4_DXREFSSEL_DEFVAL 0x0E00003C -#define DDR_PHY_DX1GCR4_DXREFSSEL_SHIFT 8 -#define DDR_PHY_DX1GCR4_DXREFSSEL_MASK 0x00007F00U +#define DDR_PHY_DX1GCR4_DXREFSSEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX1GCR4_DXREFSSEL_SHIFT 8 +#define DDR_PHY_DX1GCR4_DXREFSSEL_MASK 0x00007F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX1GCR4_RESERVED_7_6_DEFVAL #undef DDR_PHY_DX1GCR4_RESERVED_7_6_SHIFT #undef DDR_PHY_DX1GCR4_RESERVED_7_6_MASK -#define DDR_PHY_DX1GCR4_RESERVED_7_6_DEFVAL 0x0E00003C -#define DDR_PHY_DX1GCR4_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_DX1GCR4_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_DX1GCR4_RESERVED_7_6_DEFVAL 0x0E00003C +#define DDR_PHY_DX1GCR4_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX1GCR4_RESERVED_7_6_MASK 0x000000C0U -/*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/ +/* +* VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. +*/ #undef DDR_PHY_DX1GCR4_DXREFIEN_DEFVAL #undef DDR_PHY_DX1GCR4_DXREFIEN_SHIFT #undef DDR_PHY_DX1GCR4_DXREFIEN_MASK -#define DDR_PHY_DX1GCR4_DXREFIEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX1GCR4_DXREFIEN_SHIFT 2 -#define DDR_PHY_DX1GCR4_DXREFIEN_MASK 0x0000003CU +#define DDR_PHY_DX1GCR4_DXREFIEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX1GCR4_DXREFIEN_SHIFT 2 +#define DDR_PHY_DX1GCR4_DXREFIEN_MASK 0x0000003CU -/*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/ +/* +* VRMON control for DQ IO (Single Ended) buffers of a byte lane. +*/ #undef DDR_PHY_DX1GCR4_DXREFIMON_DEFVAL #undef DDR_PHY_DX1GCR4_DXREFIMON_SHIFT #undef DDR_PHY_DX1GCR4_DXREFIMON_MASK -#define DDR_PHY_DX1GCR4_DXREFIMON_DEFVAL 0x0E00003C -#define DDR_PHY_DX1GCR4_DXREFIMON_SHIFT 0 -#define DDR_PHY_DX1GCR4_DXREFIMON_MASK 0x00000003U +#define DDR_PHY_DX1GCR4_DXREFIMON_DEFVAL 0x0E00003C +#define DDR_PHY_DX1GCR4_DXREFIMON_SHIFT 0 +#define DDR_PHY_DX1GCR4_DXREFIMON_MASK 0x00000003U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX1GCR5_RESERVED_31_DEFVAL #undef DDR_PHY_DX1GCR5_RESERVED_31_SHIFT #undef DDR_PHY_DX1GCR5_RESERVED_31_MASK -#define DDR_PHY_DX1GCR5_RESERVED_31_DEFVAL 0x09090909 -#define DDR_PHY_DX1GCR5_RESERVED_31_SHIFT 31 -#define DDR_PHY_DX1GCR5_RESERVED_31_MASK 0x80000000U +#define DDR_PHY_DX1GCR5_RESERVED_31_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR5_RESERVED_31_SHIFT 31 +#define DDR_PHY_DX1GCR5_RESERVED_31_MASK 0x80000000U -/*Byte Lane internal VREF Select for Rank 3*/ +/* +* Byte Lane internal VREF Select for Rank 3 +*/ #undef DDR_PHY_DX1GCR5_DXREFISELR3_DEFVAL #undef DDR_PHY_DX1GCR5_DXREFISELR3_SHIFT #undef DDR_PHY_DX1GCR5_DXREFISELR3_MASK -#define DDR_PHY_DX1GCR5_DXREFISELR3_DEFVAL 0x09090909 -#define DDR_PHY_DX1GCR5_DXREFISELR3_SHIFT 24 -#define DDR_PHY_DX1GCR5_DXREFISELR3_MASK 0x7F000000U +#define DDR_PHY_DX1GCR5_DXREFISELR3_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR5_DXREFISELR3_SHIFT 24 +#define DDR_PHY_DX1GCR5_DXREFISELR3_MASK 0x7F000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX1GCR5_RESERVED_23_DEFVAL #undef DDR_PHY_DX1GCR5_RESERVED_23_SHIFT #undef DDR_PHY_DX1GCR5_RESERVED_23_MASK -#define DDR_PHY_DX1GCR5_RESERVED_23_DEFVAL 0x09090909 -#define DDR_PHY_DX1GCR5_RESERVED_23_SHIFT 23 -#define DDR_PHY_DX1GCR5_RESERVED_23_MASK 0x00800000U +#define DDR_PHY_DX1GCR5_RESERVED_23_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR5_RESERVED_23_SHIFT 23 +#define DDR_PHY_DX1GCR5_RESERVED_23_MASK 0x00800000U -/*Byte Lane internal VREF Select for Rank 2*/ +/* +* Byte Lane internal VREF Select for Rank 2 +*/ #undef DDR_PHY_DX1GCR5_DXREFISELR2_DEFVAL #undef DDR_PHY_DX1GCR5_DXREFISELR2_SHIFT #undef DDR_PHY_DX1GCR5_DXREFISELR2_MASK -#define DDR_PHY_DX1GCR5_DXREFISELR2_DEFVAL 0x09090909 -#define DDR_PHY_DX1GCR5_DXREFISELR2_SHIFT 16 -#define DDR_PHY_DX1GCR5_DXREFISELR2_MASK 0x007F0000U +#define DDR_PHY_DX1GCR5_DXREFISELR2_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR5_DXREFISELR2_SHIFT 16 +#define DDR_PHY_DX1GCR5_DXREFISELR2_MASK 0x007F0000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX1GCR5_RESERVED_15_DEFVAL #undef DDR_PHY_DX1GCR5_RESERVED_15_SHIFT #undef DDR_PHY_DX1GCR5_RESERVED_15_MASK -#define DDR_PHY_DX1GCR5_RESERVED_15_DEFVAL 0x09090909 -#define DDR_PHY_DX1GCR5_RESERVED_15_SHIFT 15 -#define DDR_PHY_DX1GCR5_RESERVED_15_MASK 0x00008000U +#define DDR_PHY_DX1GCR5_RESERVED_15_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR5_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX1GCR5_RESERVED_15_MASK 0x00008000U -/*Byte Lane internal VREF Select for Rank 1*/ +/* +* Byte Lane internal VREF Select for Rank 1 +*/ #undef DDR_PHY_DX1GCR5_DXREFISELR1_DEFVAL #undef DDR_PHY_DX1GCR5_DXREFISELR1_SHIFT #undef DDR_PHY_DX1GCR5_DXREFISELR1_MASK -#define DDR_PHY_DX1GCR5_DXREFISELR1_DEFVAL 0x09090909 -#define DDR_PHY_DX1GCR5_DXREFISELR1_SHIFT 8 -#define DDR_PHY_DX1GCR5_DXREFISELR1_MASK 0x00007F00U +#define DDR_PHY_DX1GCR5_DXREFISELR1_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR5_DXREFISELR1_SHIFT 8 +#define DDR_PHY_DX1GCR5_DXREFISELR1_MASK 0x00007F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX1GCR5_RESERVED_7_DEFVAL #undef DDR_PHY_DX1GCR5_RESERVED_7_SHIFT #undef DDR_PHY_DX1GCR5_RESERVED_7_MASK -#define DDR_PHY_DX1GCR5_RESERVED_7_DEFVAL 0x09090909 -#define DDR_PHY_DX1GCR5_RESERVED_7_SHIFT 7 -#define DDR_PHY_DX1GCR5_RESERVED_7_MASK 0x00000080U +#define DDR_PHY_DX1GCR5_RESERVED_7_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR5_RESERVED_7_SHIFT 7 +#define DDR_PHY_DX1GCR5_RESERVED_7_MASK 0x00000080U -/*Byte Lane internal VREF Select for Rank 0*/ +/* +* Byte Lane internal VREF Select for Rank 0 +*/ #undef DDR_PHY_DX1GCR5_DXREFISELR0_DEFVAL #undef DDR_PHY_DX1GCR5_DXREFISELR0_SHIFT #undef DDR_PHY_DX1GCR5_DXREFISELR0_MASK -#define DDR_PHY_DX1GCR5_DXREFISELR0_DEFVAL 0x09090909 -#define DDR_PHY_DX1GCR5_DXREFISELR0_SHIFT 0 -#define DDR_PHY_DX1GCR5_DXREFISELR0_MASK 0x0000007FU +#define DDR_PHY_DX1GCR5_DXREFISELR0_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR5_DXREFISELR0_SHIFT 0 +#define DDR_PHY_DX1GCR5_DXREFISELR0_MASK 0x0000007FU -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX1GCR6_RESERVED_31_30_DEFVAL #undef DDR_PHY_DX1GCR6_RESERVED_31_30_SHIFT #undef DDR_PHY_DX1GCR6_RESERVED_31_30_MASK -#define DDR_PHY_DX1GCR6_RESERVED_31_30_DEFVAL 0x09090909 -#define DDR_PHY_DX1GCR6_RESERVED_31_30_SHIFT 30 -#define DDR_PHY_DX1GCR6_RESERVED_31_30_MASK 0xC0000000U +#define DDR_PHY_DX1GCR6_RESERVED_31_30_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR6_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX1GCR6_RESERVED_31_30_MASK 0xC0000000U -/*DRAM DQ VREF Select for Rank3*/ +/* +* DRAM DQ VREF Select for Rank3 +*/ #undef DDR_PHY_DX1GCR6_DXDQVREFR3_DEFVAL #undef DDR_PHY_DX1GCR6_DXDQVREFR3_SHIFT #undef DDR_PHY_DX1GCR6_DXDQVREFR3_MASK -#define DDR_PHY_DX1GCR6_DXDQVREFR3_DEFVAL 0x09090909 -#define DDR_PHY_DX1GCR6_DXDQVREFR3_SHIFT 24 -#define DDR_PHY_DX1GCR6_DXDQVREFR3_MASK 0x3F000000U +#define DDR_PHY_DX1GCR6_DXDQVREFR3_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR6_DXDQVREFR3_SHIFT 24 +#define DDR_PHY_DX1GCR6_DXDQVREFR3_MASK 0x3F000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX1GCR6_RESERVED_23_22_DEFVAL #undef DDR_PHY_DX1GCR6_RESERVED_23_22_SHIFT #undef DDR_PHY_DX1GCR6_RESERVED_23_22_MASK -#define DDR_PHY_DX1GCR6_RESERVED_23_22_DEFVAL 0x09090909 -#define DDR_PHY_DX1GCR6_RESERVED_23_22_SHIFT 22 -#define DDR_PHY_DX1GCR6_RESERVED_23_22_MASK 0x00C00000U +#define DDR_PHY_DX1GCR6_RESERVED_23_22_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR6_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX1GCR6_RESERVED_23_22_MASK 0x00C00000U -/*DRAM DQ VREF Select for Rank2*/ +/* +* DRAM DQ VREF Select for Rank2 +*/ #undef DDR_PHY_DX1GCR6_DXDQVREFR2_DEFVAL #undef DDR_PHY_DX1GCR6_DXDQVREFR2_SHIFT #undef DDR_PHY_DX1GCR6_DXDQVREFR2_MASK -#define DDR_PHY_DX1GCR6_DXDQVREFR2_DEFVAL 0x09090909 -#define DDR_PHY_DX1GCR6_DXDQVREFR2_SHIFT 16 -#define DDR_PHY_DX1GCR6_DXDQVREFR2_MASK 0x003F0000U +#define DDR_PHY_DX1GCR6_DXDQVREFR2_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR6_DXDQVREFR2_SHIFT 16 +#define DDR_PHY_DX1GCR6_DXDQVREFR2_MASK 0x003F0000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX1GCR6_RESERVED_15_14_DEFVAL #undef DDR_PHY_DX1GCR6_RESERVED_15_14_SHIFT #undef DDR_PHY_DX1GCR6_RESERVED_15_14_MASK -#define DDR_PHY_DX1GCR6_RESERVED_15_14_DEFVAL 0x09090909 -#define DDR_PHY_DX1GCR6_RESERVED_15_14_SHIFT 14 -#define DDR_PHY_DX1GCR6_RESERVED_15_14_MASK 0x0000C000U +#define DDR_PHY_DX1GCR6_RESERVED_15_14_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR6_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_DX1GCR6_RESERVED_15_14_MASK 0x0000C000U -/*DRAM DQ VREF Select for Rank1*/ +/* +* DRAM DQ VREF Select for Rank1 +*/ #undef DDR_PHY_DX1GCR6_DXDQVREFR1_DEFVAL #undef DDR_PHY_DX1GCR6_DXDQVREFR1_SHIFT #undef DDR_PHY_DX1GCR6_DXDQVREFR1_MASK -#define DDR_PHY_DX1GCR6_DXDQVREFR1_DEFVAL 0x09090909 -#define DDR_PHY_DX1GCR6_DXDQVREFR1_SHIFT 8 -#define DDR_PHY_DX1GCR6_DXDQVREFR1_MASK 0x00003F00U +#define DDR_PHY_DX1GCR6_DXDQVREFR1_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR6_DXDQVREFR1_SHIFT 8 +#define DDR_PHY_DX1GCR6_DXDQVREFR1_MASK 0x00003F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX1GCR6_RESERVED_7_6_DEFVAL #undef DDR_PHY_DX1GCR6_RESERVED_7_6_SHIFT #undef DDR_PHY_DX1GCR6_RESERVED_7_6_MASK -#define DDR_PHY_DX1GCR6_RESERVED_7_6_DEFVAL 0x09090909 -#define DDR_PHY_DX1GCR6_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_DX1GCR6_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_DX1GCR6_RESERVED_7_6_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR6_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX1GCR6_RESERVED_7_6_MASK 0x000000C0U -/*DRAM DQ VREF Select for Rank0*/ +/* +* DRAM DQ VREF Select for Rank0 +*/ #undef DDR_PHY_DX1GCR6_DXDQVREFR0_DEFVAL #undef DDR_PHY_DX1GCR6_DXDQVREFR0_SHIFT #undef DDR_PHY_DX1GCR6_DXDQVREFR0_MASK -#define DDR_PHY_DX1GCR6_DXDQVREFR0_DEFVAL 0x09090909 -#define DDR_PHY_DX1GCR6_DXDQVREFR0_SHIFT 0 -#define DDR_PHY_DX1GCR6_DXDQVREFR0_MASK 0x0000003FU +#define DDR_PHY_DX1GCR6_DXDQVREFR0_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR6_DXDQVREFR0_SHIFT 0 +#define DDR_PHY_DX1GCR6_DXDQVREFR0_MASK 0x0000003FU -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX1LCDLR2_RESERVED_31_25_DEFVAL -#undef DDR_PHY_DX1LCDLR2_RESERVED_31_25_SHIFT -#undef DDR_PHY_DX1LCDLR2_RESERVED_31_25_MASK -#define DDR_PHY_DX1LCDLR2_RESERVED_31_25_DEFVAL 0x00000000 -#define DDR_PHY_DX1LCDLR2_RESERVED_31_25_SHIFT 25 -#define DDR_PHY_DX1LCDLR2_RESERVED_31_25_MASK 0xFE000000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX1LCDLR2_RESERVED_24_16_DEFVAL -#undef DDR_PHY_DX1LCDLR2_RESERVED_24_16_SHIFT -#undef DDR_PHY_DX1LCDLR2_RESERVED_24_16_MASK -#define DDR_PHY_DX1LCDLR2_RESERVED_24_16_DEFVAL 0x00000000 -#define DDR_PHY_DX1LCDLR2_RESERVED_24_16_SHIFT 16 -#define DDR_PHY_DX1LCDLR2_RESERVED_24_16_MASK 0x01FF0000U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX1LCDLR2_RESERVED_15_9_DEFVAL -#undef DDR_PHY_DX1LCDLR2_RESERVED_15_9_SHIFT -#undef DDR_PHY_DX1LCDLR2_RESERVED_15_9_MASK -#define DDR_PHY_DX1LCDLR2_RESERVED_15_9_DEFVAL 0x00000000 -#define DDR_PHY_DX1LCDLR2_RESERVED_15_9_SHIFT 9 -#define DDR_PHY_DX1LCDLR2_RESERVED_15_9_MASK 0x0000FE00U - -/*Read DQS Gating Delay*/ -#undef DDR_PHY_DX1LCDLR2_DQSGD_DEFVAL -#undef DDR_PHY_DX1LCDLR2_DQSGD_SHIFT -#undef DDR_PHY_DX1LCDLR2_DQSGD_MASK -#define DDR_PHY_DX1LCDLR2_DQSGD_DEFVAL 0x00000000 -#define DDR_PHY_DX1LCDLR2_DQSGD_SHIFT 0 -#define DDR_PHY_DX1LCDLR2_DQSGD_MASK 0x000001FFU - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX1GTR0_RESERVED_31_24_DEFVAL -#undef DDR_PHY_DX1GTR0_RESERVED_31_24_SHIFT -#undef DDR_PHY_DX1GTR0_RESERVED_31_24_MASK -#define DDR_PHY_DX1GTR0_RESERVED_31_24_DEFVAL 0x00020000 -#define DDR_PHY_DX1GTR0_RESERVED_31_24_SHIFT 27 -#define DDR_PHY_DX1GTR0_RESERVED_31_24_MASK 0xF8000000U - -/*DQ Write Path Latency Pipeline*/ -#undef DDR_PHY_DX1GTR0_WDQSL_DEFVAL -#undef DDR_PHY_DX1GTR0_WDQSL_SHIFT -#undef DDR_PHY_DX1GTR0_WDQSL_MASK -#define DDR_PHY_DX1GTR0_WDQSL_DEFVAL 0x00020000 -#define DDR_PHY_DX1GTR0_WDQSL_SHIFT 24 -#define DDR_PHY_DX1GTR0_WDQSL_MASK 0x07000000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX1GTR0_RESERVED_23_20_DEFVAL -#undef DDR_PHY_DX1GTR0_RESERVED_23_20_SHIFT -#undef DDR_PHY_DX1GTR0_RESERVED_23_20_MASK -#define DDR_PHY_DX1GTR0_RESERVED_23_20_DEFVAL 0x00020000 -#define DDR_PHY_DX1GTR0_RESERVED_23_20_SHIFT 20 -#define DDR_PHY_DX1GTR0_RESERVED_23_20_MASK 0x00F00000U - -/*Write Leveling System Latency*/ -#undef DDR_PHY_DX1GTR0_WLSL_DEFVAL -#undef DDR_PHY_DX1GTR0_WLSL_SHIFT -#undef DDR_PHY_DX1GTR0_WLSL_MASK -#define DDR_PHY_DX1GTR0_WLSL_DEFVAL 0x00020000 -#define DDR_PHY_DX1GTR0_WLSL_SHIFT 16 -#define DDR_PHY_DX1GTR0_WLSL_MASK 0x000F0000U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX1GTR0_RESERVED_15_13_DEFVAL -#undef DDR_PHY_DX1GTR0_RESERVED_15_13_SHIFT -#undef DDR_PHY_DX1GTR0_RESERVED_15_13_MASK -#define DDR_PHY_DX1GTR0_RESERVED_15_13_DEFVAL 0x00020000 -#define DDR_PHY_DX1GTR0_RESERVED_15_13_SHIFT 13 -#define DDR_PHY_DX1GTR0_RESERVED_15_13_MASK 0x0000E000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX1GTR0_RESERVED_12_8_DEFVAL -#undef DDR_PHY_DX1GTR0_RESERVED_12_8_SHIFT -#undef DDR_PHY_DX1GTR0_RESERVED_12_8_MASK -#define DDR_PHY_DX1GTR0_RESERVED_12_8_DEFVAL 0x00020000 -#define DDR_PHY_DX1GTR0_RESERVED_12_8_SHIFT 8 -#define DDR_PHY_DX1GTR0_RESERVED_12_8_MASK 0x00001F00U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX1GTR0_RESERVED_7_5_DEFVAL -#undef DDR_PHY_DX1GTR0_RESERVED_7_5_SHIFT -#undef DDR_PHY_DX1GTR0_RESERVED_7_5_MASK -#define DDR_PHY_DX1GTR0_RESERVED_7_5_DEFVAL 0x00020000 -#define DDR_PHY_DX1GTR0_RESERVED_7_5_SHIFT 5 -#define DDR_PHY_DX1GTR0_RESERVED_7_5_MASK 0x000000E0U - -/*DQS Gating System Latency*/ -#undef DDR_PHY_DX1GTR0_DGSL_DEFVAL -#undef DDR_PHY_DX1GTR0_DGSL_SHIFT -#undef DDR_PHY_DX1GTR0_DGSL_MASK -#define DDR_PHY_DX1GTR0_DGSL_DEFVAL 0x00020000 -#define DDR_PHY_DX1GTR0_DGSL_SHIFT 0 -#define DDR_PHY_DX1GTR0_DGSL_MASK 0x0000001FU - -/*Calibration Bypass*/ +/* +* Calibration Bypass +*/ #undef DDR_PHY_DX2GCR0_CALBYP_DEFVAL #undef DDR_PHY_DX2GCR0_CALBYP_SHIFT #undef DDR_PHY_DX2GCR0_CALBYP_MASK -#define DDR_PHY_DX2GCR0_CALBYP_DEFVAL 0x40200204 -#define DDR_PHY_DX2GCR0_CALBYP_SHIFT 31 -#define DDR_PHY_DX2GCR0_CALBYP_MASK 0x80000000U +#define DDR_PHY_DX2GCR0_CALBYP_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_CALBYP_SHIFT 31 +#define DDR_PHY_DX2GCR0_CALBYP_MASK 0x80000000U -/*Master Delay Line Enable*/ +/* +* Master Delay Line Enable +*/ #undef DDR_PHY_DX2GCR0_MDLEN_DEFVAL #undef DDR_PHY_DX2GCR0_MDLEN_SHIFT #undef DDR_PHY_DX2GCR0_MDLEN_MASK -#define DDR_PHY_DX2GCR0_MDLEN_DEFVAL 0x40200204 -#define DDR_PHY_DX2GCR0_MDLEN_SHIFT 30 -#define DDR_PHY_DX2GCR0_MDLEN_MASK 0x40000000U +#define DDR_PHY_DX2GCR0_MDLEN_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_MDLEN_SHIFT 30 +#define DDR_PHY_DX2GCR0_MDLEN_MASK 0x40000000U -/*Configurable ODT(TE) Phase Shift*/ +/* +* Configurable ODT(TE) Phase Shift +*/ #undef DDR_PHY_DX2GCR0_CODTSHFT_DEFVAL #undef DDR_PHY_DX2GCR0_CODTSHFT_SHIFT #undef DDR_PHY_DX2GCR0_CODTSHFT_MASK -#define DDR_PHY_DX2GCR0_CODTSHFT_DEFVAL 0x40200204 -#define DDR_PHY_DX2GCR0_CODTSHFT_SHIFT 28 -#define DDR_PHY_DX2GCR0_CODTSHFT_MASK 0x30000000U +#define DDR_PHY_DX2GCR0_CODTSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_CODTSHFT_SHIFT 28 +#define DDR_PHY_DX2GCR0_CODTSHFT_MASK 0x30000000U -/*DQS Duty Cycle Correction*/ +/* +* DQS Duty Cycle Correction +*/ #undef DDR_PHY_DX2GCR0_DQSDCC_DEFVAL #undef DDR_PHY_DX2GCR0_DQSDCC_SHIFT #undef DDR_PHY_DX2GCR0_DQSDCC_MASK -#define DDR_PHY_DX2GCR0_DQSDCC_DEFVAL 0x40200204 -#define DDR_PHY_DX2GCR0_DQSDCC_SHIFT 24 -#define DDR_PHY_DX2GCR0_DQSDCC_MASK 0x0F000000U +#define DDR_PHY_DX2GCR0_DQSDCC_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_DQSDCC_SHIFT 24 +#define DDR_PHY_DX2GCR0_DQSDCC_MASK 0x0F000000U -/*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/ +/* +* Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY +*/ #undef DDR_PHY_DX2GCR0_RDDLY_DEFVAL #undef DDR_PHY_DX2GCR0_RDDLY_SHIFT #undef DDR_PHY_DX2GCR0_RDDLY_MASK -#define DDR_PHY_DX2GCR0_RDDLY_DEFVAL 0x40200204 -#define DDR_PHY_DX2GCR0_RDDLY_SHIFT 20 -#define DDR_PHY_DX2GCR0_RDDLY_MASK 0x00F00000U +#define DDR_PHY_DX2GCR0_RDDLY_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_RDDLY_SHIFT 20 +#define DDR_PHY_DX2GCR0_RDDLY_MASK 0x00F00000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX2GCR0_RESERVED_19_14_DEFVAL #undef DDR_PHY_DX2GCR0_RESERVED_19_14_SHIFT #undef DDR_PHY_DX2GCR0_RESERVED_19_14_MASK -#define DDR_PHY_DX2GCR0_RESERVED_19_14_DEFVAL 0x40200204 -#define DDR_PHY_DX2GCR0_RESERVED_19_14_SHIFT 14 -#define DDR_PHY_DX2GCR0_RESERVED_19_14_MASK 0x000FC000U +#define DDR_PHY_DX2GCR0_RESERVED_19_14_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_RESERVED_19_14_SHIFT 14 +#define DDR_PHY_DX2GCR0_RESERVED_19_14_MASK 0x000FC000U -/*DQSNSE Power Down Receiver*/ +/* +* DQSNSE Power Down Receiver +*/ #undef DDR_PHY_DX2GCR0_DQSNSEPDR_DEFVAL #undef DDR_PHY_DX2GCR0_DQSNSEPDR_SHIFT #undef DDR_PHY_DX2GCR0_DQSNSEPDR_MASK -#define DDR_PHY_DX2GCR0_DQSNSEPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX2GCR0_DQSNSEPDR_SHIFT 13 -#define DDR_PHY_DX2GCR0_DQSNSEPDR_MASK 0x00002000U +#define DDR_PHY_DX2GCR0_DQSNSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_DQSNSEPDR_SHIFT 13 +#define DDR_PHY_DX2GCR0_DQSNSEPDR_MASK 0x00002000U -/*DQSSE Power Down Receiver*/ +/* +* DQSSE Power Down Receiver +*/ #undef DDR_PHY_DX2GCR0_DQSSEPDR_DEFVAL #undef DDR_PHY_DX2GCR0_DQSSEPDR_SHIFT #undef DDR_PHY_DX2GCR0_DQSSEPDR_MASK -#define DDR_PHY_DX2GCR0_DQSSEPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX2GCR0_DQSSEPDR_SHIFT 12 -#define DDR_PHY_DX2GCR0_DQSSEPDR_MASK 0x00001000U +#define DDR_PHY_DX2GCR0_DQSSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_DQSSEPDR_SHIFT 12 +#define DDR_PHY_DX2GCR0_DQSSEPDR_MASK 0x00001000U -/*RTT On Additive Latency*/ +/* +* RTT On Additive Latency +*/ #undef DDR_PHY_DX2GCR0_RTTOAL_DEFVAL #undef DDR_PHY_DX2GCR0_RTTOAL_SHIFT #undef DDR_PHY_DX2GCR0_RTTOAL_MASK -#define DDR_PHY_DX2GCR0_RTTOAL_DEFVAL 0x40200204 -#define DDR_PHY_DX2GCR0_RTTOAL_SHIFT 11 -#define DDR_PHY_DX2GCR0_RTTOAL_MASK 0x00000800U +#define DDR_PHY_DX2GCR0_RTTOAL_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_RTTOAL_SHIFT 11 +#define DDR_PHY_DX2GCR0_RTTOAL_MASK 0x00000800U -/*RTT Output Hold*/ +/* +* RTT Output Hold +*/ #undef DDR_PHY_DX2GCR0_RTTOH_DEFVAL #undef DDR_PHY_DX2GCR0_RTTOH_SHIFT #undef DDR_PHY_DX2GCR0_RTTOH_MASK -#define DDR_PHY_DX2GCR0_RTTOH_DEFVAL 0x40200204 -#define DDR_PHY_DX2GCR0_RTTOH_SHIFT 9 -#define DDR_PHY_DX2GCR0_RTTOH_MASK 0x00000600U +#define DDR_PHY_DX2GCR0_RTTOH_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_RTTOH_SHIFT 9 +#define DDR_PHY_DX2GCR0_RTTOH_MASK 0x00000600U -/*Configurable PDR Phase Shift*/ +/* +* Configurable PDR Phase Shift +*/ #undef DDR_PHY_DX2GCR0_CPDRSHFT_DEFVAL #undef DDR_PHY_DX2GCR0_CPDRSHFT_SHIFT #undef DDR_PHY_DX2GCR0_CPDRSHFT_MASK -#define DDR_PHY_DX2GCR0_CPDRSHFT_DEFVAL 0x40200204 -#define DDR_PHY_DX2GCR0_CPDRSHFT_SHIFT 7 -#define DDR_PHY_DX2GCR0_CPDRSHFT_MASK 0x00000180U +#define DDR_PHY_DX2GCR0_CPDRSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_CPDRSHFT_SHIFT 7 +#define DDR_PHY_DX2GCR0_CPDRSHFT_MASK 0x00000180U -/*DQSR Power Down*/ +/* +* DQSR Power Down +*/ #undef DDR_PHY_DX2GCR0_DQSRPD_DEFVAL #undef DDR_PHY_DX2GCR0_DQSRPD_SHIFT #undef DDR_PHY_DX2GCR0_DQSRPD_MASK -#define DDR_PHY_DX2GCR0_DQSRPD_DEFVAL 0x40200204 -#define DDR_PHY_DX2GCR0_DQSRPD_SHIFT 6 -#define DDR_PHY_DX2GCR0_DQSRPD_MASK 0x00000040U +#define DDR_PHY_DX2GCR0_DQSRPD_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_DQSRPD_SHIFT 6 +#define DDR_PHY_DX2GCR0_DQSRPD_MASK 0x00000040U -/*DQSG Power Down Receiver*/ +/* +* DQSG Power Down Receiver +*/ #undef DDR_PHY_DX2GCR0_DQSGPDR_DEFVAL #undef DDR_PHY_DX2GCR0_DQSGPDR_SHIFT #undef DDR_PHY_DX2GCR0_DQSGPDR_MASK -#define DDR_PHY_DX2GCR0_DQSGPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX2GCR0_DQSGPDR_SHIFT 5 -#define DDR_PHY_DX2GCR0_DQSGPDR_MASK 0x00000020U +#define DDR_PHY_DX2GCR0_DQSGPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_DQSGPDR_SHIFT 5 +#define DDR_PHY_DX2GCR0_DQSGPDR_MASK 0x00000020U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX2GCR0_RESERVED_4_DEFVAL #undef DDR_PHY_DX2GCR0_RESERVED_4_SHIFT #undef DDR_PHY_DX2GCR0_RESERVED_4_MASK -#define DDR_PHY_DX2GCR0_RESERVED_4_DEFVAL 0x40200204 -#define DDR_PHY_DX2GCR0_RESERVED_4_SHIFT 4 -#define DDR_PHY_DX2GCR0_RESERVED_4_MASK 0x00000010U +#define DDR_PHY_DX2GCR0_RESERVED_4_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_RESERVED_4_SHIFT 4 +#define DDR_PHY_DX2GCR0_RESERVED_4_MASK 0x00000010U -/*DQSG On-Die Termination*/ +/* +* DQSG On-Die Termination +*/ #undef DDR_PHY_DX2GCR0_DQSGODT_DEFVAL #undef DDR_PHY_DX2GCR0_DQSGODT_SHIFT #undef DDR_PHY_DX2GCR0_DQSGODT_MASK -#define DDR_PHY_DX2GCR0_DQSGODT_DEFVAL 0x40200204 -#define DDR_PHY_DX2GCR0_DQSGODT_SHIFT 3 -#define DDR_PHY_DX2GCR0_DQSGODT_MASK 0x00000008U +#define DDR_PHY_DX2GCR0_DQSGODT_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_DQSGODT_SHIFT 3 +#define DDR_PHY_DX2GCR0_DQSGODT_MASK 0x00000008U -/*DQSG Output Enable*/ +/* +* DQSG Output Enable +*/ #undef DDR_PHY_DX2GCR0_DQSGOE_DEFVAL #undef DDR_PHY_DX2GCR0_DQSGOE_SHIFT #undef DDR_PHY_DX2GCR0_DQSGOE_MASK -#define DDR_PHY_DX2GCR0_DQSGOE_DEFVAL 0x40200204 -#define DDR_PHY_DX2GCR0_DQSGOE_SHIFT 2 -#define DDR_PHY_DX2GCR0_DQSGOE_MASK 0x00000004U +#define DDR_PHY_DX2GCR0_DQSGOE_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_DQSGOE_SHIFT 2 +#define DDR_PHY_DX2GCR0_DQSGOE_MASK 0x00000004U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX2GCR0_RESERVED_1_0_DEFVAL #undef DDR_PHY_DX2GCR0_RESERVED_1_0_SHIFT #undef DDR_PHY_DX2GCR0_RESERVED_1_0_MASK -#define DDR_PHY_DX2GCR0_RESERVED_1_0_DEFVAL 0x40200204 -#define DDR_PHY_DX2GCR0_RESERVED_1_0_SHIFT 0 -#define DDR_PHY_DX2GCR0_RESERVED_1_0_MASK 0x00000003U +#define DDR_PHY_DX2GCR0_RESERVED_1_0_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_RESERVED_1_0_SHIFT 0 +#define DDR_PHY_DX2GCR0_RESERVED_1_0_MASK 0x00000003U -/*Enables the PDR mode for DQ[7:0]*/ +/* +* Enables the PDR mode for DQ[7:0] +*/ #undef DDR_PHY_DX2GCR1_DXPDRMODE_DEFVAL #undef DDR_PHY_DX2GCR1_DXPDRMODE_SHIFT #undef DDR_PHY_DX2GCR1_DXPDRMODE_MASK -#define DDR_PHY_DX2GCR1_DXPDRMODE_DEFVAL 0x00007FFF -#define DDR_PHY_DX2GCR1_DXPDRMODE_SHIFT 16 -#define DDR_PHY_DX2GCR1_DXPDRMODE_MASK 0xFFFF0000U +#define DDR_PHY_DX2GCR1_DXPDRMODE_DEFVAL 0x00007FFF +#define DDR_PHY_DX2GCR1_DXPDRMODE_SHIFT 16 +#define DDR_PHY_DX2GCR1_DXPDRMODE_MASK 0xFFFF0000U -/*Reserved. Returns zeroes on reads.*/ +/* +* Reserved. Returns zeroes on reads. +*/ #undef DDR_PHY_DX2GCR1_RESERVED_15_DEFVAL #undef DDR_PHY_DX2GCR1_RESERVED_15_SHIFT #undef DDR_PHY_DX2GCR1_RESERVED_15_MASK -#define DDR_PHY_DX2GCR1_RESERVED_15_DEFVAL 0x00007FFF -#define DDR_PHY_DX2GCR1_RESERVED_15_SHIFT 15 -#define DDR_PHY_DX2GCR1_RESERVED_15_MASK 0x00008000U +#define DDR_PHY_DX2GCR1_RESERVED_15_DEFVAL 0x00007FFF +#define DDR_PHY_DX2GCR1_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX2GCR1_RESERVED_15_MASK 0x00008000U -/*Select the delayed or non-delayed read data strobe #*/ +/* +* Select the delayed or non-delayed read data strobe # +*/ #undef DDR_PHY_DX2GCR1_QSNSEL_DEFVAL #undef DDR_PHY_DX2GCR1_QSNSEL_SHIFT #undef DDR_PHY_DX2GCR1_QSNSEL_MASK -#define DDR_PHY_DX2GCR1_QSNSEL_DEFVAL 0x00007FFF -#define DDR_PHY_DX2GCR1_QSNSEL_SHIFT 14 -#define DDR_PHY_DX2GCR1_QSNSEL_MASK 0x00004000U +#define DDR_PHY_DX2GCR1_QSNSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX2GCR1_QSNSEL_SHIFT 14 +#define DDR_PHY_DX2GCR1_QSNSEL_MASK 0x00004000U -/*Select the delayed or non-delayed read data strobe*/ +/* +* Select the delayed or non-delayed read data strobe +*/ #undef DDR_PHY_DX2GCR1_QSSEL_DEFVAL #undef DDR_PHY_DX2GCR1_QSSEL_SHIFT #undef DDR_PHY_DX2GCR1_QSSEL_MASK -#define DDR_PHY_DX2GCR1_QSSEL_DEFVAL 0x00007FFF -#define DDR_PHY_DX2GCR1_QSSEL_SHIFT 13 -#define DDR_PHY_DX2GCR1_QSSEL_MASK 0x00002000U +#define DDR_PHY_DX2GCR1_QSSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX2GCR1_QSSEL_SHIFT 13 +#define DDR_PHY_DX2GCR1_QSSEL_MASK 0x00002000U -/*Enables Read Data Strobe in a byte lane*/ +/* +* Enables Read Data Strobe in a byte lane +*/ #undef DDR_PHY_DX2GCR1_OEEN_DEFVAL #undef DDR_PHY_DX2GCR1_OEEN_SHIFT #undef DDR_PHY_DX2GCR1_OEEN_MASK -#define DDR_PHY_DX2GCR1_OEEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX2GCR1_OEEN_SHIFT 12 -#define DDR_PHY_DX2GCR1_OEEN_MASK 0x00001000U +#define DDR_PHY_DX2GCR1_OEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX2GCR1_OEEN_SHIFT 12 +#define DDR_PHY_DX2GCR1_OEEN_MASK 0x00001000U -/*Enables PDR in a byte lane*/ +/* +* Enables PDR in a byte lane +*/ #undef DDR_PHY_DX2GCR1_PDREN_DEFVAL #undef DDR_PHY_DX2GCR1_PDREN_SHIFT #undef DDR_PHY_DX2GCR1_PDREN_MASK -#define DDR_PHY_DX2GCR1_PDREN_DEFVAL 0x00007FFF -#define DDR_PHY_DX2GCR1_PDREN_SHIFT 11 -#define DDR_PHY_DX2GCR1_PDREN_MASK 0x00000800U +#define DDR_PHY_DX2GCR1_PDREN_DEFVAL 0x00007FFF +#define DDR_PHY_DX2GCR1_PDREN_SHIFT 11 +#define DDR_PHY_DX2GCR1_PDREN_MASK 0x00000800U -/*Enables ODT/TE in a byte lane*/ +/* +* Enables ODT/TE in a byte lane +*/ #undef DDR_PHY_DX2GCR1_TEEN_DEFVAL #undef DDR_PHY_DX2GCR1_TEEN_SHIFT #undef DDR_PHY_DX2GCR1_TEEN_MASK -#define DDR_PHY_DX2GCR1_TEEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX2GCR1_TEEN_SHIFT 10 -#define DDR_PHY_DX2GCR1_TEEN_MASK 0x00000400U +#define DDR_PHY_DX2GCR1_TEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX2GCR1_TEEN_SHIFT 10 +#define DDR_PHY_DX2GCR1_TEEN_MASK 0x00000400U -/*Enables Write Data strobe in a byte lane*/ +/* +* Enables Write Data strobe in a byte lane +*/ #undef DDR_PHY_DX2GCR1_DSEN_DEFVAL #undef DDR_PHY_DX2GCR1_DSEN_SHIFT #undef DDR_PHY_DX2GCR1_DSEN_MASK -#define DDR_PHY_DX2GCR1_DSEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX2GCR1_DSEN_SHIFT 9 -#define DDR_PHY_DX2GCR1_DSEN_MASK 0x00000200U +#define DDR_PHY_DX2GCR1_DSEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX2GCR1_DSEN_SHIFT 9 +#define DDR_PHY_DX2GCR1_DSEN_MASK 0x00000200U -/*Enables DM pin in a byte lane*/ +/* +* Enables DM pin in a byte lane +*/ #undef DDR_PHY_DX2GCR1_DMEN_DEFVAL #undef DDR_PHY_DX2GCR1_DMEN_SHIFT #undef DDR_PHY_DX2GCR1_DMEN_MASK -#define DDR_PHY_DX2GCR1_DMEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX2GCR1_DMEN_SHIFT 8 -#define DDR_PHY_DX2GCR1_DMEN_MASK 0x00000100U +#define DDR_PHY_DX2GCR1_DMEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX2GCR1_DMEN_SHIFT 8 +#define DDR_PHY_DX2GCR1_DMEN_MASK 0x00000100U -/*Enables DQ corresponding to each bit in a byte*/ +/* +* Enables DQ corresponding to each bit in a byte +*/ #undef DDR_PHY_DX2GCR1_DQEN_DEFVAL #undef DDR_PHY_DX2GCR1_DQEN_SHIFT #undef DDR_PHY_DX2GCR1_DQEN_MASK -#define DDR_PHY_DX2GCR1_DQEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX2GCR1_DQEN_SHIFT 0 -#define DDR_PHY_DX2GCR1_DQEN_MASK 0x000000FFU +#define DDR_PHY_DX2GCR1_DQEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX2GCR1_DQEN_SHIFT 0 +#define DDR_PHY_DX2GCR1_DQEN_MASK 0x000000FFU -/*Byte lane VREF IOM (Used only by D4MU IOs)*/ +/* +* Byte lane VREF IOM (Used only by D4MU IOs) +*/ #undef DDR_PHY_DX2GCR4_RESERVED_31_29_DEFVAL #undef DDR_PHY_DX2GCR4_RESERVED_31_29_SHIFT #undef DDR_PHY_DX2GCR4_RESERVED_31_29_MASK -#define DDR_PHY_DX2GCR4_RESERVED_31_29_DEFVAL 0x0E00003C -#define DDR_PHY_DX2GCR4_RESERVED_31_29_SHIFT 29 -#define DDR_PHY_DX2GCR4_RESERVED_31_29_MASK 0xE0000000U +#define DDR_PHY_DX2GCR4_RESERVED_31_29_DEFVAL 0x0E00003C +#define DDR_PHY_DX2GCR4_RESERVED_31_29_SHIFT 29 +#define DDR_PHY_DX2GCR4_RESERVED_31_29_MASK 0xE0000000U -/*Byte Lane VREF Pad Enable*/ +/* +* Byte Lane VREF Pad Enable +*/ #undef DDR_PHY_DX2GCR4_DXREFPEN_DEFVAL #undef DDR_PHY_DX2GCR4_DXREFPEN_SHIFT #undef DDR_PHY_DX2GCR4_DXREFPEN_MASK -#define DDR_PHY_DX2GCR4_DXREFPEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX2GCR4_DXREFPEN_SHIFT 28 -#define DDR_PHY_DX2GCR4_DXREFPEN_MASK 0x10000000U +#define DDR_PHY_DX2GCR4_DXREFPEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX2GCR4_DXREFPEN_SHIFT 28 +#define DDR_PHY_DX2GCR4_DXREFPEN_MASK 0x10000000U -/*Byte Lane Internal VREF Enable*/ +/* +* Byte Lane Internal VREF Enable +*/ #undef DDR_PHY_DX2GCR4_DXREFEEN_DEFVAL #undef DDR_PHY_DX2GCR4_DXREFEEN_SHIFT #undef DDR_PHY_DX2GCR4_DXREFEEN_MASK -#define DDR_PHY_DX2GCR4_DXREFEEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX2GCR4_DXREFEEN_SHIFT 26 -#define DDR_PHY_DX2GCR4_DXREFEEN_MASK 0x0C000000U +#define DDR_PHY_DX2GCR4_DXREFEEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX2GCR4_DXREFEEN_SHIFT 26 +#define DDR_PHY_DX2GCR4_DXREFEEN_MASK 0x0C000000U -/*Byte Lane Single-End VREF Enable*/ +/* +* Byte Lane Single-End VREF Enable +*/ #undef DDR_PHY_DX2GCR4_DXREFSEN_DEFVAL #undef DDR_PHY_DX2GCR4_DXREFSEN_SHIFT #undef DDR_PHY_DX2GCR4_DXREFSEN_MASK -#define DDR_PHY_DX2GCR4_DXREFSEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX2GCR4_DXREFSEN_SHIFT 25 -#define DDR_PHY_DX2GCR4_DXREFSEN_MASK 0x02000000U +#define DDR_PHY_DX2GCR4_DXREFSEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX2GCR4_DXREFSEN_SHIFT 25 +#define DDR_PHY_DX2GCR4_DXREFSEN_MASK 0x02000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX2GCR4_RESERVED_24_DEFVAL #undef DDR_PHY_DX2GCR4_RESERVED_24_SHIFT #undef DDR_PHY_DX2GCR4_RESERVED_24_MASK -#define DDR_PHY_DX2GCR4_RESERVED_24_DEFVAL 0x0E00003C -#define DDR_PHY_DX2GCR4_RESERVED_24_SHIFT 24 -#define DDR_PHY_DX2GCR4_RESERVED_24_MASK 0x01000000U +#define DDR_PHY_DX2GCR4_RESERVED_24_DEFVAL 0x0E00003C +#define DDR_PHY_DX2GCR4_RESERVED_24_SHIFT 24 +#define DDR_PHY_DX2GCR4_RESERVED_24_MASK 0x01000000U -/*External VREF generator REFSEL range select*/ +/* +* External VREF generator REFSEL range select +*/ #undef DDR_PHY_DX2GCR4_DXREFESELRANGE_DEFVAL #undef DDR_PHY_DX2GCR4_DXREFESELRANGE_SHIFT #undef DDR_PHY_DX2GCR4_DXREFESELRANGE_MASK -#define DDR_PHY_DX2GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C -#define DDR_PHY_DX2GCR4_DXREFESELRANGE_SHIFT 23 -#define DDR_PHY_DX2GCR4_DXREFESELRANGE_MASK 0x00800000U +#define DDR_PHY_DX2GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX2GCR4_DXREFESELRANGE_SHIFT 23 +#define DDR_PHY_DX2GCR4_DXREFESELRANGE_MASK 0x00800000U -/*Byte Lane External VREF Select*/ +/* +* Byte Lane External VREF Select +*/ #undef DDR_PHY_DX2GCR4_DXREFESEL_DEFVAL #undef DDR_PHY_DX2GCR4_DXREFESEL_SHIFT #undef DDR_PHY_DX2GCR4_DXREFESEL_MASK -#define DDR_PHY_DX2GCR4_DXREFESEL_DEFVAL 0x0E00003C -#define DDR_PHY_DX2GCR4_DXREFESEL_SHIFT 16 -#define DDR_PHY_DX2GCR4_DXREFESEL_MASK 0x007F0000U +#define DDR_PHY_DX2GCR4_DXREFESEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX2GCR4_DXREFESEL_SHIFT 16 +#define DDR_PHY_DX2GCR4_DXREFESEL_MASK 0x007F0000U -/*Single ended VREF generator REFSEL range select*/ +/* +* Single ended VREF generator REFSEL range select +*/ #undef DDR_PHY_DX2GCR4_DXREFSSELRANGE_DEFVAL #undef DDR_PHY_DX2GCR4_DXREFSSELRANGE_SHIFT #undef DDR_PHY_DX2GCR4_DXREFSSELRANGE_MASK -#define DDR_PHY_DX2GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C -#define DDR_PHY_DX2GCR4_DXREFSSELRANGE_SHIFT 15 -#define DDR_PHY_DX2GCR4_DXREFSSELRANGE_MASK 0x00008000U +#define DDR_PHY_DX2GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX2GCR4_DXREFSSELRANGE_SHIFT 15 +#define DDR_PHY_DX2GCR4_DXREFSSELRANGE_MASK 0x00008000U -/*Byte Lane Single-End VREF Select*/ +/* +* Byte Lane Single-End VREF Select +*/ #undef DDR_PHY_DX2GCR4_DXREFSSEL_DEFVAL #undef DDR_PHY_DX2GCR4_DXREFSSEL_SHIFT #undef DDR_PHY_DX2GCR4_DXREFSSEL_MASK -#define DDR_PHY_DX2GCR4_DXREFSSEL_DEFVAL 0x0E00003C -#define DDR_PHY_DX2GCR4_DXREFSSEL_SHIFT 8 -#define DDR_PHY_DX2GCR4_DXREFSSEL_MASK 0x00007F00U +#define DDR_PHY_DX2GCR4_DXREFSSEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX2GCR4_DXREFSSEL_SHIFT 8 +#define DDR_PHY_DX2GCR4_DXREFSSEL_MASK 0x00007F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX2GCR4_RESERVED_7_6_DEFVAL #undef DDR_PHY_DX2GCR4_RESERVED_7_6_SHIFT #undef DDR_PHY_DX2GCR4_RESERVED_7_6_MASK -#define DDR_PHY_DX2GCR4_RESERVED_7_6_DEFVAL 0x0E00003C -#define DDR_PHY_DX2GCR4_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_DX2GCR4_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_DX2GCR4_RESERVED_7_6_DEFVAL 0x0E00003C +#define DDR_PHY_DX2GCR4_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX2GCR4_RESERVED_7_6_MASK 0x000000C0U -/*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/ +/* +* VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. +*/ #undef DDR_PHY_DX2GCR4_DXREFIEN_DEFVAL #undef DDR_PHY_DX2GCR4_DXREFIEN_SHIFT #undef DDR_PHY_DX2GCR4_DXREFIEN_MASK -#define DDR_PHY_DX2GCR4_DXREFIEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX2GCR4_DXREFIEN_SHIFT 2 -#define DDR_PHY_DX2GCR4_DXREFIEN_MASK 0x0000003CU +#define DDR_PHY_DX2GCR4_DXREFIEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX2GCR4_DXREFIEN_SHIFT 2 +#define DDR_PHY_DX2GCR4_DXREFIEN_MASK 0x0000003CU -/*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/ +/* +* VRMON control for DQ IO (Single Ended) buffers of a byte lane. +*/ #undef DDR_PHY_DX2GCR4_DXREFIMON_DEFVAL #undef DDR_PHY_DX2GCR4_DXREFIMON_SHIFT #undef DDR_PHY_DX2GCR4_DXREFIMON_MASK -#define DDR_PHY_DX2GCR4_DXREFIMON_DEFVAL 0x0E00003C -#define DDR_PHY_DX2GCR4_DXREFIMON_SHIFT 0 -#define DDR_PHY_DX2GCR4_DXREFIMON_MASK 0x00000003U +#define DDR_PHY_DX2GCR4_DXREFIMON_DEFVAL 0x0E00003C +#define DDR_PHY_DX2GCR4_DXREFIMON_SHIFT 0 +#define DDR_PHY_DX2GCR4_DXREFIMON_MASK 0x00000003U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX2GCR5_RESERVED_31_DEFVAL #undef DDR_PHY_DX2GCR5_RESERVED_31_SHIFT #undef DDR_PHY_DX2GCR5_RESERVED_31_MASK -#define DDR_PHY_DX2GCR5_RESERVED_31_DEFVAL 0x09090909 -#define DDR_PHY_DX2GCR5_RESERVED_31_SHIFT 31 -#define DDR_PHY_DX2GCR5_RESERVED_31_MASK 0x80000000U +#define DDR_PHY_DX2GCR5_RESERVED_31_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR5_RESERVED_31_SHIFT 31 +#define DDR_PHY_DX2GCR5_RESERVED_31_MASK 0x80000000U -/*Byte Lane internal VREF Select for Rank 3*/ +/* +* Byte Lane internal VREF Select for Rank 3 +*/ #undef DDR_PHY_DX2GCR5_DXREFISELR3_DEFVAL #undef DDR_PHY_DX2GCR5_DXREFISELR3_SHIFT #undef DDR_PHY_DX2GCR5_DXREFISELR3_MASK -#define DDR_PHY_DX2GCR5_DXREFISELR3_DEFVAL 0x09090909 -#define DDR_PHY_DX2GCR5_DXREFISELR3_SHIFT 24 -#define DDR_PHY_DX2GCR5_DXREFISELR3_MASK 0x7F000000U +#define DDR_PHY_DX2GCR5_DXREFISELR3_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR5_DXREFISELR3_SHIFT 24 +#define DDR_PHY_DX2GCR5_DXREFISELR3_MASK 0x7F000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX2GCR5_RESERVED_23_DEFVAL #undef DDR_PHY_DX2GCR5_RESERVED_23_SHIFT #undef DDR_PHY_DX2GCR5_RESERVED_23_MASK -#define DDR_PHY_DX2GCR5_RESERVED_23_DEFVAL 0x09090909 -#define DDR_PHY_DX2GCR5_RESERVED_23_SHIFT 23 -#define DDR_PHY_DX2GCR5_RESERVED_23_MASK 0x00800000U +#define DDR_PHY_DX2GCR5_RESERVED_23_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR5_RESERVED_23_SHIFT 23 +#define DDR_PHY_DX2GCR5_RESERVED_23_MASK 0x00800000U -/*Byte Lane internal VREF Select for Rank 2*/ +/* +* Byte Lane internal VREF Select for Rank 2 +*/ #undef DDR_PHY_DX2GCR5_DXREFISELR2_DEFVAL #undef DDR_PHY_DX2GCR5_DXREFISELR2_SHIFT #undef DDR_PHY_DX2GCR5_DXREFISELR2_MASK -#define DDR_PHY_DX2GCR5_DXREFISELR2_DEFVAL 0x09090909 -#define DDR_PHY_DX2GCR5_DXREFISELR2_SHIFT 16 -#define DDR_PHY_DX2GCR5_DXREFISELR2_MASK 0x007F0000U +#define DDR_PHY_DX2GCR5_DXREFISELR2_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR5_DXREFISELR2_SHIFT 16 +#define DDR_PHY_DX2GCR5_DXREFISELR2_MASK 0x007F0000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX2GCR5_RESERVED_15_DEFVAL #undef DDR_PHY_DX2GCR5_RESERVED_15_SHIFT #undef DDR_PHY_DX2GCR5_RESERVED_15_MASK -#define DDR_PHY_DX2GCR5_RESERVED_15_DEFVAL 0x09090909 -#define DDR_PHY_DX2GCR5_RESERVED_15_SHIFT 15 -#define DDR_PHY_DX2GCR5_RESERVED_15_MASK 0x00008000U +#define DDR_PHY_DX2GCR5_RESERVED_15_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR5_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX2GCR5_RESERVED_15_MASK 0x00008000U -/*Byte Lane internal VREF Select for Rank 1*/ +/* +* Byte Lane internal VREF Select for Rank 1 +*/ #undef DDR_PHY_DX2GCR5_DXREFISELR1_DEFVAL #undef DDR_PHY_DX2GCR5_DXREFISELR1_SHIFT #undef DDR_PHY_DX2GCR5_DXREFISELR1_MASK -#define DDR_PHY_DX2GCR5_DXREFISELR1_DEFVAL 0x09090909 -#define DDR_PHY_DX2GCR5_DXREFISELR1_SHIFT 8 -#define DDR_PHY_DX2GCR5_DXREFISELR1_MASK 0x00007F00U +#define DDR_PHY_DX2GCR5_DXREFISELR1_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR5_DXREFISELR1_SHIFT 8 +#define DDR_PHY_DX2GCR5_DXREFISELR1_MASK 0x00007F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX2GCR5_RESERVED_7_DEFVAL #undef DDR_PHY_DX2GCR5_RESERVED_7_SHIFT #undef DDR_PHY_DX2GCR5_RESERVED_7_MASK -#define DDR_PHY_DX2GCR5_RESERVED_7_DEFVAL 0x09090909 -#define DDR_PHY_DX2GCR5_RESERVED_7_SHIFT 7 -#define DDR_PHY_DX2GCR5_RESERVED_7_MASK 0x00000080U +#define DDR_PHY_DX2GCR5_RESERVED_7_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR5_RESERVED_7_SHIFT 7 +#define DDR_PHY_DX2GCR5_RESERVED_7_MASK 0x00000080U -/*Byte Lane internal VREF Select for Rank 0*/ +/* +* Byte Lane internal VREF Select for Rank 0 +*/ #undef DDR_PHY_DX2GCR5_DXREFISELR0_DEFVAL #undef DDR_PHY_DX2GCR5_DXREFISELR0_SHIFT #undef DDR_PHY_DX2GCR5_DXREFISELR0_MASK -#define DDR_PHY_DX2GCR5_DXREFISELR0_DEFVAL 0x09090909 -#define DDR_PHY_DX2GCR5_DXREFISELR0_SHIFT 0 -#define DDR_PHY_DX2GCR5_DXREFISELR0_MASK 0x0000007FU +#define DDR_PHY_DX2GCR5_DXREFISELR0_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR5_DXREFISELR0_SHIFT 0 +#define DDR_PHY_DX2GCR5_DXREFISELR0_MASK 0x0000007FU -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX2GCR6_RESERVED_31_30_DEFVAL #undef DDR_PHY_DX2GCR6_RESERVED_31_30_SHIFT #undef DDR_PHY_DX2GCR6_RESERVED_31_30_MASK -#define DDR_PHY_DX2GCR6_RESERVED_31_30_DEFVAL 0x09090909 -#define DDR_PHY_DX2GCR6_RESERVED_31_30_SHIFT 30 -#define DDR_PHY_DX2GCR6_RESERVED_31_30_MASK 0xC0000000U +#define DDR_PHY_DX2GCR6_RESERVED_31_30_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR6_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX2GCR6_RESERVED_31_30_MASK 0xC0000000U -/*DRAM DQ VREF Select for Rank3*/ +/* +* DRAM DQ VREF Select for Rank3 +*/ #undef DDR_PHY_DX2GCR6_DXDQVREFR3_DEFVAL #undef DDR_PHY_DX2GCR6_DXDQVREFR3_SHIFT #undef DDR_PHY_DX2GCR6_DXDQVREFR3_MASK -#define DDR_PHY_DX2GCR6_DXDQVREFR3_DEFVAL 0x09090909 -#define DDR_PHY_DX2GCR6_DXDQVREFR3_SHIFT 24 -#define DDR_PHY_DX2GCR6_DXDQVREFR3_MASK 0x3F000000U +#define DDR_PHY_DX2GCR6_DXDQVREFR3_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR6_DXDQVREFR3_SHIFT 24 +#define DDR_PHY_DX2GCR6_DXDQVREFR3_MASK 0x3F000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX2GCR6_RESERVED_23_22_DEFVAL #undef DDR_PHY_DX2GCR6_RESERVED_23_22_SHIFT #undef DDR_PHY_DX2GCR6_RESERVED_23_22_MASK -#define DDR_PHY_DX2GCR6_RESERVED_23_22_DEFVAL 0x09090909 -#define DDR_PHY_DX2GCR6_RESERVED_23_22_SHIFT 22 -#define DDR_PHY_DX2GCR6_RESERVED_23_22_MASK 0x00C00000U +#define DDR_PHY_DX2GCR6_RESERVED_23_22_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR6_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX2GCR6_RESERVED_23_22_MASK 0x00C00000U -/*DRAM DQ VREF Select for Rank2*/ +/* +* DRAM DQ VREF Select for Rank2 +*/ #undef DDR_PHY_DX2GCR6_DXDQVREFR2_DEFVAL #undef DDR_PHY_DX2GCR6_DXDQVREFR2_SHIFT #undef DDR_PHY_DX2GCR6_DXDQVREFR2_MASK -#define DDR_PHY_DX2GCR6_DXDQVREFR2_DEFVAL 0x09090909 -#define DDR_PHY_DX2GCR6_DXDQVREFR2_SHIFT 16 -#define DDR_PHY_DX2GCR6_DXDQVREFR2_MASK 0x003F0000U +#define DDR_PHY_DX2GCR6_DXDQVREFR2_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR6_DXDQVREFR2_SHIFT 16 +#define DDR_PHY_DX2GCR6_DXDQVREFR2_MASK 0x003F0000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX2GCR6_RESERVED_15_14_DEFVAL #undef DDR_PHY_DX2GCR6_RESERVED_15_14_SHIFT #undef DDR_PHY_DX2GCR6_RESERVED_15_14_MASK -#define DDR_PHY_DX2GCR6_RESERVED_15_14_DEFVAL 0x09090909 -#define DDR_PHY_DX2GCR6_RESERVED_15_14_SHIFT 14 -#define DDR_PHY_DX2GCR6_RESERVED_15_14_MASK 0x0000C000U +#define DDR_PHY_DX2GCR6_RESERVED_15_14_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR6_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_DX2GCR6_RESERVED_15_14_MASK 0x0000C000U -/*DRAM DQ VREF Select for Rank1*/ +/* +* DRAM DQ VREF Select for Rank1 +*/ #undef DDR_PHY_DX2GCR6_DXDQVREFR1_DEFVAL #undef DDR_PHY_DX2GCR6_DXDQVREFR1_SHIFT #undef DDR_PHY_DX2GCR6_DXDQVREFR1_MASK -#define DDR_PHY_DX2GCR6_DXDQVREFR1_DEFVAL 0x09090909 -#define DDR_PHY_DX2GCR6_DXDQVREFR1_SHIFT 8 -#define DDR_PHY_DX2GCR6_DXDQVREFR1_MASK 0x00003F00U +#define DDR_PHY_DX2GCR6_DXDQVREFR1_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR6_DXDQVREFR1_SHIFT 8 +#define DDR_PHY_DX2GCR6_DXDQVREFR1_MASK 0x00003F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX2GCR6_RESERVED_7_6_DEFVAL #undef DDR_PHY_DX2GCR6_RESERVED_7_6_SHIFT #undef DDR_PHY_DX2GCR6_RESERVED_7_6_MASK -#define DDR_PHY_DX2GCR6_RESERVED_7_6_DEFVAL 0x09090909 -#define DDR_PHY_DX2GCR6_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_DX2GCR6_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_DX2GCR6_RESERVED_7_6_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR6_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX2GCR6_RESERVED_7_6_MASK 0x000000C0U -/*DRAM DQ VREF Select for Rank0*/ +/* +* DRAM DQ VREF Select for Rank0 +*/ #undef DDR_PHY_DX2GCR6_DXDQVREFR0_DEFVAL #undef DDR_PHY_DX2GCR6_DXDQVREFR0_SHIFT #undef DDR_PHY_DX2GCR6_DXDQVREFR0_MASK -#define DDR_PHY_DX2GCR6_DXDQVREFR0_DEFVAL 0x09090909 -#define DDR_PHY_DX2GCR6_DXDQVREFR0_SHIFT 0 -#define DDR_PHY_DX2GCR6_DXDQVREFR0_MASK 0x0000003FU +#define DDR_PHY_DX2GCR6_DXDQVREFR0_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR6_DXDQVREFR0_SHIFT 0 +#define DDR_PHY_DX2GCR6_DXDQVREFR0_MASK 0x0000003FU -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX2LCDLR2_RESERVED_31_25_DEFVAL -#undef DDR_PHY_DX2LCDLR2_RESERVED_31_25_SHIFT -#undef DDR_PHY_DX2LCDLR2_RESERVED_31_25_MASK -#define DDR_PHY_DX2LCDLR2_RESERVED_31_25_DEFVAL 0x00000000 -#define DDR_PHY_DX2LCDLR2_RESERVED_31_25_SHIFT 25 -#define DDR_PHY_DX2LCDLR2_RESERVED_31_25_MASK 0xFE000000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX2LCDLR2_RESERVED_24_16_DEFVAL -#undef DDR_PHY_DX2LCDLR2_RESERVED_24_16_SHIFT -#undef DDR_PHY_DX2LCDLR2_RESERVED_24_16_MASK -#define DDR_PHY_DX2LCDLR2_RESERVED_24_16_DEFVAL 0x00000000 -#define DDR_PHY_DX2LCDLR2_RESERVED_24_16_SHIFT 16 -#define DDR_PHY_DX2LCDLR2_RESERVED_24_16_MASK 0x01FF0000U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX2LCDLR2_RESERVED_15_9_DEFVAL -#undef DDR_PHY_DX2LCDLR2_RESERVED_15_9_SHIFT -#undef DDR_PHY_DX2LCDLR2_RESERVED_15_9_MASK -#define DDR_PHY_DX2LCDLR2_RESERVED_15_9_DEFVAL 0x00000000 -#define DDR_PHY_DX2LCDLR2_RESERVED_15_9_SHIFT 9 -#define DDR_PHY_DX2LCDLR2_RESERVED_15_9_MASK 0x0000FE00U - -/*Read DQS Gating Delay*/ -#undef DDR_PHY_DX2LCDLR2_DQSGD_DEFVAL -#undef DDR_PHY_DX2LCDLR2_DQSGD_SHIFT -#undef DDR_PHY_DX2LCDLR2_DQSGD_MASK -#define DDR_PHY_DX2LCDLR2_DQSGD_DEFVAL 0x00000000 -#define DDR_PHY_DX2LCDLR2_DQSGD_SHIFT 0 -#define DDR_PHY_DX2LCDLR2_DQSGD_MASK 0x000001FFU - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX2GTR0_RESERVED_31_24_DEFVAL -#undef DDR_PHY_DX2GTR0_RESERVED_31_24_SHIFT -#undef DDR_PHY_DX2GTR0_RESERVED_31_24_MASK -#define DDR_PHY_DX2GTR0_RESERVED_31_24_DEFVAL 0x00020000 -#define DDR_PHY_DX2GTR0_RESERVED_31_24_SHIFT 27 -#define DDR_PHY_DX2GTR0_RESERVED_31_24_MASK 0xF8000000U - -/*DQ Write Path Latency Pipeline*/ -#undef DDR_PHY_DX2GTR0_WDQSL_DEFVAL -#undef DDR_PHY_DX2GTR0_WDQSL_SHIFT -#undef DDR_PHY_DX2GTR0_WDQSL_MASK -#define DDR_PHY_DX2GTR0_WDQSL_DEFVAL 0x00020000 -#define DDR_PHY_DX2GTR0_WDQSL_SHIFT 24 -#define DDR_PHY_DX2GTR0_WDQSL_MASK 0x07000000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX2GTR0_RESERVED_23_20_DEFVAL -#undef DDR_PHY_DX2GTR0_RESERVED_23_20_SHIFT -#undef DDR_PHY_DX2GTR0_RESERVED_23_20_MASK -#define DDR_PHY_DX2GTR0_RESERVED_23_20_DEFVAL 0x00020000 -#define DDR_PHY_DX2GTR0_RESERVED_23_20_SHIFT 20 -#define DDR_PHY_DX2GTR0_RESERVED_23_20_MASK 0x00F00000U - -/*Write Leveling System Latency*/ -#undef DDR_PHY_DX2GTR0_WLSL_DEFVAL -#undef DDR_PHY_DX2GTR0_WLSL_SHIFT -#undef DDR_PHY_DX2GTR0_WLSL_MASK -#define DDR_PHY_DX2GTR0_WLSL_DEFVAL 0x00020000 -#define DDR_PHY_DX2GTR0_WLSL_SHIFT 16 -#define DDR_PHY_DX2GTR0_WLSL_MASK 0x000F0000U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX2GTR0_RESERVED_15_13_DEFVAL -#undef DDR_PHY_DX2GTR0_RESERVED_15_13_SHIFT -#undef DDR_PHY_DX2GTR0_RESERVED_15_13_MASK -#define DDR_PHY_DX2GTR0_RESERVED_15_13_DEFVAL 0x00020000 -#define DDR_PHY_DX2GTR0_RESERVED_15_13_SHIFT 13 -#define DDR_PHY_DX2GTR0_RESERVED_15_13_MASK 0x0000E000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX2GTR0_RESERVED_12_8_DEFVAL -#undef DDR_PHY_DX2GTR0_RESERVED_12_8_SHIFT -#undef DDR_PHY_DX2GTR0_RESERVED_12_8_MASK -#define DDR_PHY_DX2GTR0_RESERVED_12_8_DEFVAL 0x00020000 -#define DDR_PHY_DX2GTR0_RESERVED_12_8_SHIFT 8 -#define DDR_PHY_DX2GTR0_RESERVED_12_8_MASK 0x00001F00U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX2GTR0_RESERVED_7_5_DEFVAL -#undef DDR_PHY_DX2GTR0_RESERVED_7_5_SHIFT -#undef DDR_PHY_DX2GTR0_RESERVED_7_5_MASK -#define DDR_PHY_DX2GTR0_RESERVED_7_5_DEFVAL 0x00020000 -#define DDR_PHY_DX2GTR0_RESERVED_7_5_SHIFT 5 -#define DDR_PHY_DX2GTR0_RESERVED_7_5_MASK 0x000000E0U - -/*DQS Gating System Latency*/ -#undef DDR_PHY_DX2GTR0_DGSL_DEFVAL -#undef DDR_PHY_DX2GTR0_DGSL_SHIFT -#undef DDR_PHY_DX2GTR0_DGSL_MASK -#define DDR_PHY_DX2GTR0_DGSL_DEFVAL 0x00020000 -#define DDR_PHY_DX2GTR0_DGSL_SHIFT 0 -#define DDR_PHY_DX2GTR0_DGSL_MASK 0x0000001FU - -/*Calibration Bypass*/ +/* +* Calibration Bypass +*/ #undef DDR_PHY_DX3GCR0_CALBYP_DEFVAL #undef DDR_PHY_DX3GCR0_CALBYP_SHIFT #undef DDR_PHY_DX3GCR0_CALBYP_MASK -#define DDR_PHY_DX3GCR0_CALBYP_DEFVAL 0x40200204 -#define DDR_PHY_DX3GCR0_CALBYP_SHIFT 31 -#define DDR_PHY_DX3GCR0_CALBYP_MASK 0x80000000U +#define DDR_PHY_DX3GCR0_CALBYP_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_CALBYP_SHIFT 31 +#define DDR_PHY_DX3GCR0_CALBYP_MASK 0x80000000U -/*Master Delay Line Enable*/ +/* +* Master Delay Line Enable +*/ #undef DDR_PHY_DX3GCR0_MDLEN_DEFVAL #undef DDR_PHY_DX3GCR0_MDLEN_SHIFT #undef DDR_PHY_DX3GCR0_MDLEN_MASK -#define DDR_PHY_DX3GCR0_MDLEN_DEFVAL 0x40200204 -#define DDR_PHY_DX3GCR0_MDLEN_SHIFT 30 -#define DDR_PHY_DX3GCR0_MDLEN_MASK 0x40000000U +#define DDR_PHY_DX3GCR0_MDLEN_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_MDLEN_SHIFT 30 +#define DDR_PHY_DX3GCR0_MDLEN_MASK 0x40000000U -/*Configurable ODT(TE) Phase Shift*/ +/* +* Configurable ODT(TE) Phase Shift +*/ #undef DDR_PHY_DX3GCR0_CODTSHFT_DEFVAL #undef DDR_PHY_DX3GCR0_CODTSHFT_SHIFT #undef DDR_PHY_DX3GCR0_CODTSHFT_MASK -#define DDR_PHY_DX3GCR0_CODTSHFT_DEFVAL 0x40200204 -#define DDR_PHY_DX3GCR0_CODTSHFT_SHIFT 28 -#define DDR_PHY_DX3GCR0_CODTSHFT_MASK 0x30000000U +#define DDR_PHY_DX3GCR0_CODTSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_CODTSHFT_SHIFT 28 +#define DDR_PHY_DX3GCR0_CODTSHFT_MASK 0x30000000U -/*DQS Duty Cycle Correction*/ +/* +* DQS Duty Cycle Correction +*/ #undef DDR_PHY_DX3GCR0_DQSDCC_DEFVAL #undef DDR_PHY_DX3GCR0_DQSDCC_SHIFT #undef DDR_PHY_DX3GCR0_DQSDCC_MASK -#define DDR_PHY_DX3GCR0_DQSDCC_DEFVAL 0x40200204 -#define DDR_PHY_DX3GCR0_DQSDCC_SHIFT 24 -#define DDR_PHY_DX3GCR0_DQSDCC_MASK 0x0F000000U +#define DDR_PHY_DX3GCR0_DQSDCC_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_DQSDCC_SHIFT 24 +#define DDR_PHY_DX3GCR0_DQSDCC_MASK 0x0F000000U -/*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/ +/* +* Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY +*/ #undef DDR_PHY_DX3GCR0_RDDLY_DEFVAL #undef DDR_PHY_DX3GCR0_RDDLY_SHIFT #undef DDR_PHY_DX3GCR0_RDDLY_MASK -#define DDR_PHY_DX3GCR0_RDDLY_DEFVAL 0x40200204 -#define DDR_PHY_DX3GCR0_RDDLY_SHIFT 20 -#define DDR_PHY_DX3GCR0_RDDLY_MASK 0x00F00000U +#define DDR_PHY_DX3GCR0_RDDLY_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_RDDLY_SHIFT 20 +#define DDR_PHY_DX3GCR0_RDDLY_MASK 0x00F00000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX3GCR0_RESERVED_19_14_DEFVAL #undef DDR_PHY_DX3GCR0_RESERVED_19_14_SHIFT #undef DDR_PHY_DX3GCR0_RESERVED_19_14_MASK -#define DDR_PHY_DX3GCR0_RESERVED_19_14_DEFVAL 0x40200204 -#define DDR_PHY_DX3GCR0_RESERVED_19_14_SHIFT 14 -#define DDR_PHY_DX3GCR0_RESERVED_19_14_MASK 0x000FC000U +#define DDR_PHY_DX3GCR0_RESERVED_19_14_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_RESERVED_19_14_SHIFT 14 +#define DDR_PHY_DX3GCR0_RESERVED_19_14_MASK 0x000FC000U -/*DQSNSE Power Down Receiver*/ +/* +* DQSNSE Power Down Receiver +*/ #undef DDR_PHY_DX3GCR0_DQSNSEPDR_DEFVAL #undef DDR_PHY_DX3GCR0_DQSNSEPDR_SHIFT #undef DDR_PHY_DX3GCR0_DQSNSEPDR_MASK -#define DDR_PHY_DX3GCR0_DQSNSEPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX3GCR0_DQSNSEPDR_SHIFT 13 -#define DDR_PHY_DX3GCR0_DQSNSEPDR_MASK 0x00002000U +#define DDR_PHY_DX3GCR0_DQSNSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_DQSNSEPDR_SHIFT 13 +#define DDR_PHY_DX3GCR0_DQSNSEPDR_MASK 0x00002000U -/*DQSSE Power Down Receiver*/ +/* +* DQSSE Power Down Receiver +*/ #undef DDR_PHY_DX3GCR0_DQSSEPDR_DEFVAL #undef DDR_PHY_DX3GCR0_DQSSEPDR_SHIFT #undef DDR_PHY_DX3GCR0_DQSSEPDR_MASK -#define DDR_PHY_DX3GCR0_DQSSEPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX3GCR0_DQSSEPDR_SHIFT 12 -#define DDR_PHY_DX3GCR0_DQSSEPDR_MASK 0x00001000U +#define DDR_PHY_DX3GCR0_DQSSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_DQSSEPDR_SHIFT 12 +#define DDR_PHY_DX3GCR0_DQSSEPDR_MASK 0x00001000U -/*RTT On Additive Latency*/ +/* +* RTT On Additive Latency +*/ #undef DDR_PHY_DX3GCR0_RTTOAL_DEFVAL #undef DDR_PHY_DX3GCR0_RTTOAL_SHIFT #undef DDR_PHY_DX3GCR0_RTTOAL_MASK -#define DDR_PHY_DX3GCR0_RTTOAL_DEFVAL 0x40200204 -#define DDR_PHY_DX3GCR0_RTTOAL_SHIFT 11 -#define DDR_PHY_DX3GCR0_RTTOAL_MASK 0x00000800U +#define DDR_PHY_DX3GCR0_RTTOAL_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_RTTOAL_SHIFT 11 +#define DDR_PHY_DX3GCR0_RTTOAL_MASK 0x00000800U -/*RTT Output Hold*/ +/* +* RTT Output Hold +*/ #undef DDR_PHY_DX3GCR0_RTTOH_DEFVAL #undef DDR_PHY_DX3GCR0_RTTOH_SHIFT #undef DDR_PHY_DX3GCR0_RTTOH_MASK -#define DDR_PHY_DX3GCR0_RTTOH_DEFVAL 0x40200204 -#define DDR_PHY_DX3GCR0_RTTOH_SHIFT 9 -#define DDR_PHY_DX3GCR0_RTTOH_MASK 0x00000600U +#define DDR_PHY_DX3GCR0_RTTOH_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_RTTOH_SHIFT 9 +#define DDR_PHY_DX3GCR0_RTTOH_MASK 0x00000600U -/*Configurable PDR Phase Shift*/ +/* +* Configurable PDR Phase Shift +*/ #undef DDR_PHY_DX3GCR0_CPDRSHFT_DEFVAL #undef DDR_PHY_DX3GCR0_CPDRSHFT_SHIFT #undef DDR_PHY_DX3GCR0_CPDRSHFT_MASK -#define DDR_PHY_DX3GCR0_CPDRSHFT_DEFVAL 0x40200204 -#define DDR_PHY_DX3GCR0_CPDRSHFT_SHIFT 7 -#define DDR_PHY_DX3GCR0_CPDRSHFT_MASK 0x00000180U +#define DDR_PHY_DX3GCR0_CPDRSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_CPDRSHFT_SHIFT 7 +#define DDR_PHY_DX3GCR0_CPDRSHFT_MASK 0x00000180U -/*DQSR Power Down*/ +/* +* DQSR Power Down +*/ #undef DDR_PHY_DX3GCR0_DQSRPD_DEFVAL #undef DDR_PHY_DX3GCR0_DQSRPD_SHIFT #undef DDR_PHY_DX3GCR0_DQSRPD_MASK -#define DDR_PHY_DX3GCR0_DQSRPD_DEFVAL 0x40200204 -#define DDR_PHY_DX3GCR0_DQSRPD_SHIFT 6 -#define DDR_PHY_DX3GCR0_DQSRPD_MASK 0x00000040U +#define DDR_PHY_DX3GCR0_DQSRPD_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_DQSRPD_SHIFT 6 +#define DDR_PHY_DX3GCR0_DQSRPD_MASK 0x00000040U -/*DQSG Power Down Receiver*/ +/* +* DQSG Power Down Receiver +*/ #undef DDR_PHY_DX3GCR0_DQSGPDR_DEFVAL #undef DDR_PHY_DX3GCR0_DQSGPDR_SHIFT #undef DDR_PHY_DX3GCR0_DQSGPDR_MASK -#define DDR_PHY_DX3GCR0_DQSGPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX3GCR0_DQSGPDR_SHIFT 5 -#define DDR_PHY_DX3GCR0_DQSGPDR_MASK 0x00000020U +#define DDR_PHY_DX3GCR0_DQSGPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_DQSGPDR_SHIFT 5 +#define DDR_PHY_DX3GCR0_DQSGPDR_MASK 0x00000020U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX3GCR0_RESERVED_4_DEFVAL #undef DDR_PHY_DX3GCR0_RESERVED_4_SHIFT #undef DDR_PHY_DX3GCR0_RESERVED_4_MASK -#define DDR_PHY_DX3GCR0_RESERVED_4_DEFVAL 0x40200204 -#define DDR_PHY_DX3GCR0_RESERVED_4_SHIFT 4 -#define DDR_PHY_DX3GCR0_RESERVED_4_MASK 0x00000010U +#define DDR_PHY_DX3GCR0_RESERVED_4_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_RESERVED_4_SHIFT 4 +#define DDR_PHY_DX3GCR0_RESERVED_4_MASK 0x00000010U -/*DQSG On-Die Termination*/ +/* +* DQSG On-Die Termination +*/ #undef DDR_PHY_DX3GCR0_DQSGODT_DEFVAL #undef DDR_PHY_DX3GCR0_DQSGODT_SHIFT #undef DDR_PHY_DX3GCR0_DQSGODT_MASK -#define DDR_PHY_DX3GCR0_DQSGODT_DEFVAL 0x40200204 -#define DDR_PHY_DX3GCR0_DQSGODT_SHIFT 3 -#define DDR_PHY_DX3GCR0_DQSGODT_MASK 0x00000008U +#define DDR_PHY_DX3GCR0_DQSGODT_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_DQSGODT_SHIFT 3 +#define DDR_PHY_DX3GCR0_DQSGODT_MASK 0x00000008U -/*DQSG Output Enable*/ +/* +* DQSG Output Enable +*/ #undef DDR_PHY_DX3GCR0_DQSGOE_DEFVAL #undef DDR_PHY_DX3GCR0_DQSGOE_SHIFT #undef DDR_PHY_DX3GCR0_DQSGOE_MASK -#define DDR_PHY_DX3GCR0_DQSGOE_DEFVAL 0x40200204 -#define DDR_PHY_DX3GCR0_DQSGOE_SHIFT 2 -#define DDR_PHY_DX3GCR0_DQSGOE_MASK 0x00000004U +#define DDR_PHY_DX3GCR0_DQSGOE_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_DQSGOE_SHIFT 2 +#define DDR_PHY_DX3GCR0_DQSGOE_MASK 0x00000004U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX3GCR0_RESERVED_1_0_DEFVAL #undef DDR_PHY_DX3GCR0_RESERVED_1_0_SHIFT #undef DDR_PHY_DX3GCR0_RESERVED_1_0_MASK -#define DDR_PHY_DX3GCR0_RESERVED_1_0_DEFVAL 0x40200204 -#define DDR_PHY_DX3GCR0_RESERVED_1_0_SHIFT 0 -#define DDR_PHY_DX3GCR0_RESERVED_1_0_MASK 0x00000003U +#define DDR_PHY_DX3GCR0_RESERVED_1_0_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_RESERVED_1_0_SHIFT 0 +#define DDR_PHY_DX3GCR0_RESERVED_1_0_MASK 0x00000003U -/*Enables the PDR mode for DQ[7:0]*/ +/* +* Enables the PDR mode for DQ[7:0] +*/ #undef DDR_PHY_DX3GCR1_DXPDRMODE_DEFVAL #undef DDR_PHY_DX3GCR1_DXPDRMODE_SHIFT #undef DDR_PHY_DX3GCR1_DXPDRMODE_MASK -#define DDR_PHY_DX3GCR1_DXPDRMODE_DEFVAL 0x00007FFF -#define DDR_PHY_DX3GCR1_DXPDRMODE_SHIFT 16 -#define DDR_PHY_DX3GCR1_DXPDRMODE_MASK 0xFFFF0000U +#define DDR_PHY_DX3GCR1_DXPDRMODE_DEFVAL 0x00007FFF +#define DDR_PHY_DX3GCR1_DXPDRMODE_SHIFT 16 +#define DDR_PHY_DX3GCR1_DXPDRMODE_MASK 0xFFFF0000U -/*Reserved. Returns zeroes on reads.*/ +/* +* Reserved. Returns zeroes on reads. +*/ #undef DDR_PHY_DX3GCR1_RESERVED_15_DEFVAL #undef DDR_PHY_DX3GCR1_RESERVED_15_SHIFT #undef DDR_PHY_DX3GCR1_RESERVED_15_MASK -#define DDR_PHY_DX3GCR1_RESERVED_15_DEFVAL 0x00007FFF -#define DDR_PHY_DX3GCR1_RESERVED_15_SHIFT 15 -#define DDR_PHY_DX3GCR1_RESERVED_15_MASK 0x00008000U +#define DDR_PHY_DX3GCR1_RESERVED_15_DEFVAL 0x00007FFF +#define DDR_PHY_DX3GCR1_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX3GCR1_RESERVED_15_MASK 0x00008000U -/*Select the delayed or non-delayed read data strobe #*/ +/* +* Select the delayed or non-delayed read data strobe # +*/ #undef DDR_PHY_DX3GCR1_QSNSEL_DEFVAL #undef DDR_PHY_DX3GCR1_QSNSEL_SHIFT #undef DDR_PHY_DX3GCR1_QSNSEL_MASK -#define DDR_PHY_DX3GCR1_QSNSEL_DEFVAL 0x00007FFF -#define DDR_PHY_DX3GCR1_QSNSEL_SHIFT 14 -#define DDR_PHY_DX3GCR1_QSNSEL_MASK 0x00004000U +#define DDR_PHY_DX3GCR1_QSNSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX3GCR1_QSNSEL_SHIFT 14 +#define DDR_PHY_DX3GCR1_QSNSEL_MASK 0x00004000U -/*Select the delayed or non-delayed read data strobe*/ +/* +* Select the delayed or non-delayed read data strobe +*/ #undef DDR_PHY_DX3GCR1_QSSEL_DEFVAL #undef DDR_PHY_DX3GCR1_QSSEL_SHIFT #undef DDR_PHY_DX3GCR1_QSSEL_MASK -#define DDR_PHY_DX3GCR1_QSSEL_DEFVAL 0x00007FFF -#define DDR_PHY_DX3GCR1_QSSEL_SHIFT 13 -#define DDR_PHY_DX3GCR1_QSSEL_MASK 0x00002000U +#define DDR_PHY_DX3GCR1_QSSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX3GCR1_QSSEL_SHIFT 13 +#define DDR_PHY_DX3GCR1_QSSEL_MASK 0x00002000U -/*Enables Read Data Strobe in a byte lane*/ +/* +* Enables Read Data Strobe in a byte lane +*/ #undef DDR_PHY_DX3GCR1_OEEN_DEFVAL #undef DDR_PHY_DX3GCR1_OEEN_SHIFT #undef DDR_PHY_DX3GCR1_OEEN_MASK -#define DDR_PHY_DX3GCR1_OEEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX3GCR1_OEEN_SHIFT 12 -#define DDR_PHY_DX3GCR1_OEEN_MASK 0x00001000U +#define DDR_PHY_DX3GCR1_OEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX3GCR1_OEEN_SHIFT 12 +#define DDR_PHY_DX3GCR1_OEEN_MASK 0x00001000U -/*Enables PDR in a byte lane*/ +/* +* Enables PDR in a byte lane +*/ #undef DDR_PHY_DX3GCR1_PDREN_DEFVAL #undef DDR_PHY_DX3GCR1_PDREN_SHIFT #undef DDR_PHY_DX3GCR1_PDREN_MASK -#define DDR_PHY_DX3GCR1_PDREN_DEFVAL 0x00007FFF -#define DDR_PHY_DX3GCR1_PDREN_SHIFT 11 -#define DDR_PHY_DX3GCR1_PDREN_MASK 0x00000800U +#define DDR_PHY_DX3GCR1_PDREN_DEFVAL 0x00007FFF +#define DDR_PHY_DX3GCR1_PDREN_SHIFT 11 +#define DDR_PHY_DX3GCR1_PDREN_MASK 0x00000800U -/*Enables ODT/TE in a byte lane*/ +/* +* Enables ODT/TE in a byte lane +*/ #undef DDR_PHY_DX3GCR1_TEEN_DEFVAL #undef DDR_PHY_DX3GCR1_TEEN_SHIFT #undef DDR_PHY_DX3GCR1_TEEN_MASK -#define DDR_PHY_DX3GCR1_TEEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX3GCR1_TEEN_SHIFT 10 -#define DDR_PHY_DX3GCR1_TEEN_MASK 0x00000400U +#define DDR_PHY_DX3GCR1_TEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX3GCR1_TEEN_SHIFT 10 +#define DDR_PHY_DX3GCR1_TEEN_MASK 0x00000400U -/*Enables Write Data strobe in a byte lane*/ +/* +* Enables Write Data strobe in a byte lane +*/ #undef DDR_PHY_DX3GCR1_DSEN_DEFVAL #undef DDR_PHY_DX3GCR1_DSEN_SHIFT #undef DDR_PHY_DX3GCR1_DSEN_MASK -#define DDR_PHY_DX3GCR1_DSEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX3GCR1_DSEN_SHIFT 9 -#define DDR_PHY_DX3GCR1_DSEN_MASK 0x00000200U +#define DDR_PHY_DX3GCR1_DSEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX3GCR1_DSEN_SHIFT 9 +#define DDR_PHY_DX3GCR1_DSEN_MASK 0x00000200U -/*Enables DM pin in a byte lane*/ +/* +* Enables DM pin in a byte lane +*/ #undef DDR_PHY_DX3GCR1_DMEN_DEFVAL #undef DDR_PHY_DX3GCR1_DMEN_SHIFT #undef DDR_PHY_DX3GCR1_DMEN_MASK -#define DDR_PHY_DX3GCR1_DMEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX3GCR1_DMEN_SHIFT 8 -#define DDR_PHY_DX3GCR1_DMEN_MASK 0x00000100U +#define DDR_PHY_DX3GCR1_DMEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX3GCR1_DMEN_SHIFT 8 +#define DDR_PHY_DX3GCR1_DMEN_MASK 0x00000100U -/*Enables DQ corresponding to each bit in a byte*/ +/* +* Enables DQ corresponding to each bit in a byte +*/ #undef DDR_PHY_DX3GCR1_DQEN_DEFVAL #undef DDR_PHY_DX3GCR1_DQEN_SHIFT #undef DDR_PHY_DX3GCR1_DQEN_MASK -#define DDR_PHY_DX3GCR1_DQEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX3GCR1_DQEN_SHIFT 0 -#define DDR_PHY_DX3GCR1_DQEN_MASK 0x000000FFU +#define DDR_PHY_DX3GCR1_DQEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX3GCR1_DQEN_SHIFT 0 +#define DDR_PHY_DX3GCR1_DQEN_MASK 0x000000FFU -/*Byte lane VREF IOM (Used only by D4MU IOs)*/ +/* +* Byte lane VREF IOM (Used only by D4MU IOs) +*/ #undef DDR_PHY_DX3GCR4_RESERVED_31_29_DEFVAL #undef DDR_PHY_DX3GCR4_RESERVED_31_29_SHIFT #undef DDR_PHY_DX3GCR4_RESERVED_31_29_MASK -#define DDR_PHY_DX3GCR4_RESERVED_31_29_DEFVAL 0x0E00003C -#define DDR_PHY_DX3GCR4_RESERVED_31_29_SHIFT 29 -#define DDR_PHY_DX3GCR4_RESERVED_31_29_MASK 0xE0000000U +#define DDR_PHY_DX3GCR4_RESERVED_31_29_DEFVAL 0x0E00003C +#define DDR_PHY_DX3GCR4_RESERVED_31_29_SHIFT 29 +#define DDR_PHY_DX3GCR4_RESERVED_31_29_MASK 0xE0000000U -/*Byte Lane VREF Pad Enable*/ +/* +* Byte Lane VREF Pad Enable +*/ #undef DDR_PHY_DX3GCR4_DXREFPEN_DEFVAL #undef DDR_PHY_DX3GCR4_DXREFPEN_SHIFT #undef DDR_PHY_DX3GCR4_DXREFPEN_MASK -#define DDR_PHY_DX3GCR4_DXREFPEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX3GCR4_DXREFPEN_SHIFT 28 -#define DDR_PHY_DX3GCR4_DXREFPEN_MASK 0x10000000U +#define DDR_PHY_DX3GCR4_DXREFPEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX3GCR4_DXREFPEN_SHIFT 28 +#define DDR_PHY_DX3GCR4_DXREFPEN_MASK 0x10000000U -/*Byte Lane Internal VREF Enable*/ +/* +* Byte Lane Internal VREF Enable +*/ #undef DDR_PHY_DX3GCR4_DXREFEEN_DEFVAL #undef DDR_PHY_DX3GCR4_DXREFEEN_SHIFT #undef DDR_PHY_DX3GCR4_DXREFEEN_MASK -#define DDR_PHY_DX3GCR4_DXREFEEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX3GCR4_DXREFEEN_SHIFT 26 -#define DDR_PHY_DX3GCR4_DXREFEEN_MASK 0x0C000000U +#define DDR_PHY_DX3GCR4_DXREFEEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX3GCR4_DXREFEEN_SHIFT 26 +#define DDR_PHY_DX3GCR4_DXREFEEN_MASK 0x0C000000U -/*Byte Lane Single-End VREF Enable*/ +/* +* Byte Lane Single-End VREF Enable +*/ #undef DDR_PHY_DX3GCR4_DXREFSEN_DEFVAL #undef DDR_PHY_DX3GCR4_DXREFSEN_SHIFT #undef DDR_PHY_DX3GCR4_DXREFSEN_MASK -#define DDR_PHY_DX3GCR4_DXREFSEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX3GCR4_DXREFSEN_SHIFT 25 -#define DDR_PHY_DX3GCR4_DXREFSEN_MASK 0x02000000U +#define DDR_PHY_DX3GCR4_DXREFSEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX3GCR4_DXREFSEN_SHIFT 25 +#define DDR_PHY_DX3GCR4_DXREFSEN_MASK 0x02000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX3GCR4_RESERVED_24_DEFVAL #undef DDR_PHY_DX3GCR4_RESERVED_24_SHIFT #undef DDR_PHY_DX3GCR4_RESERVED_24_MASK -#define DDR_PHY_DX3GCR4_RESERVED_24_DEFVAL 0x0E00003C -#define DDR_PHY_DX3GCR4_RESERVED_24_SHIFT 24 -#define DDR_PHY_DX3GCR4_RESERVED_24_MASK 0x01000000U +#define DDR_PHY_DX3GCR4_RESERVED_24_DEFVAL 0x0E00003C +#define DDR_PHY_DX3GCR4_RESERVED_24_SHIFT 24 +#define DDR_PHY_DX3GCR4_RESERVED_24_MASK 0x01000000U -/*External VREF generator REFSEL range select*/ +/* +* External VREF generator REFSEL range select +*/ #undef DDR_PHY_DX3GCR4_DXREFESELRANGE_DEFVAL #undef DDR_PHY_DX3GCR4_DXREFESELRANGE_SHIFT #undef DDR_PHY_DX3GCR4_DXREFESELRANGE_MASK -#define DDR_PHY_DX3GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C -#define DDR_PHY_DX3GCR4_DXREFESELRANGE_SHIFT 23 -#define DDR_PHY_DX3GCR4_DXREFESELRANGE_MASK 0x00800000U +#define DDR_PHY_DX3GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX3GCR4_DXREFESELRANGE_SHIFT 23 +#define DDR_PHY_DX3GCR4_DXREFESELRANGE_MASK 0x00800000U -/*Byte Lane External VREF Select*/ +/* +* Byte Lane External VREF Select +*/ #undef DDR_PHY_DX3GCR4_DXREFESEL_DEFVAL #undef DDR_PHY_DX3GCR4_DXREFESEL_SHIFT #undef DDR_PHY_DX3GCR4_DXREFESEL_MASK -#define DDR_PHY_DX3GCR4_DXREFESEL_DEFVAL 0x0E00003C -#define DDR_PHY_DX3GCR4_DXREFESEL_SHIFT 16 -#define DDR_PHY_DX3GCR4_DXREFESEL_MASK 0x007F0000U +#define DDR_PHY_DX3GCR4_DXREFESEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX3GCR4_DXREFESEL_SHIFT 16 +#define DDR_PHY_DX3GCR4_DXREFESEL_MASK 0x007F0000U -/*Single ended VREF generator REFSEL range select*/ +/* +* Single ended VREF generator REFSEL range select +*/ #undef DDR_PHY_DX3GCR4_DXREFSSELRANGE_DEFVAL #undef DDR_PHY_DX3GCR4_DXREFSSELRANGE_SHIFT #undef DDR_PHY_DX3GCR4_DXREFSSELRANGE_MASK -#define DDR_PHY_DX3GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C -#define DDR_PHY_DX3GCR4_DXREFSSELRANGE_SHIFT 15 -#define DDR_PHY_DX3GCR4_DXREFSSELRANGE_MASK 0x00008000U +#define DDR_PHY_DX3GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX3GCR4_DXREFSSELRANGE_SHIFT 15 +#define DDR_PHY_DX3GCR4_DXREFSSELRANGE_MASK 0x00008000U -/*Byte Lane Single-End VREF Select*/ +/* +* Byte Lane Single-End VREF Select +*/ #undef DDR_PHY_DX3GCR4_DXREFSSEL_DEFVAL #undef DDR_PHY_DX3GCR4_DXREFSSEL_SHIFT #undef DDR_PHY_DX3GCR4_DXREFSSEL_MASK -#define DDR_PHY_DX3GCR4_DXREFSSEL_DEFVAL 0x0E00003C -#define DDR_PHY_DX3GCR4_DXREFSSEL_SHIFT 8 -#define DDR_PHY_DX3GCR4_DXREFSSEL_MASK 0x00007F00U +#define DDR_PHY_DX3GCR4_DXREFSSEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX3GCR4_DXREFSSEL_SHIFT 8 +#define DDR_PHY_DX3GCR4_DXREFSSEL_MASK 0x00007F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX3GCR4_RESERVED_7_6_DEFVAL #undef DDR_PHY_DX3GCR4_RESERVED_7_6_SHIFT #undef DDR_PHY_DX3GCR4_RESERVED_7_6_MASK -#define DDR_PHY_DX3GCR4_RESERVED_7_6_DEFVAL 0x0E00003C -#define DDR_PHY_DX3GCR4_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_DX3GCR4_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_DX3GCR4_RESERVED_7_6_DEFVAL 0x0E00003C +#define DDR_PHY_DX3GCR4_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX3GCR4_RESERVED_7_6_MASK 0x000000C0U -/*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/ +/* +* VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. +*/ #undef DDR_PHY_DX3GCR4_DXREFIEN_DEFVAL #undef DDR_PHY_DX3GCR4_DXREFIEN_SHIFT #undef DDR_PHY_DX3GCR4_DXREFIEN_MASK -#define DDR_PHY_DX3GCR4_DXREFIEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX3GCR4_DXREFIEN_SHIFT 2 -#define DDR_PHY_DX3GCR4_DXREFIEN_MASK 0x0000003CU +#define DDR_PHY_DX3GCR4_DXREFIEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX3GCR4_DXREFIEN_SHIFT 2 +#define DDR_PHY_DX3GCR4_DXREFIEN_MASK 0x0000003CU -/*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/ +/* +* VRMON control for DQ IO (Single Ended) buffers of a byte lane. +*/ #undef DDR_PHY_DX3GCR4_DXREFIMON_DEFVAL #undef DDR_PHY_DX3GCR4_DXREFIMON_SHIFT #undef DDR_PHY_DX3GCR4_DXREFIMON_MASK -#define DDR_PHY_DX3GCR4_DXREFIMON_DEFVAL 0x0E00003C -#define DDR_PHY_DX3GCR4_DXREFIMON_SHIFT 0 -#define DDR_PHY_DX3GCR4_DXREFIMON_MASK 0x00000003U +#define DDR_PHY_DX3GCR4_DXREFIMON_DEFVAL 0x0E00003C +#define DDR_PHY_DX3GCR4_DXREFIMON_SHIFT 0 +#define DDR_PHY_DX3GCR4_DXREFIMON_MASK 0x00000003U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX3GCR5_RESERVED_31_DEFVAL #undef DDR_PHY_DX3GCR5_RESERVED_31_SHIFT #undef DDR_PHY_DX3GCR5_RESERVED_31_MASK -#define DDR_PHY_DX3GCR5_RESERVED_31_DEFVAL 0x09090909 -#define DDR_PHY_DX3GCR5_RESERVED_31_SHIFT 31 -#define DDR_PHY_DX3GCR5_RESERVED_31_MASK 0x80000000U +#define DDR_PHY_DX3GCR5_RESERVED_31_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR5_RESERVED_31_SHIFT 31 +#define DDR_PHY_DX3GCR5_RESERVED_31_MASK 0x80000000U -/*Byte Lane internal VREF Select for Rank 3*/ +/* +* Byte Lane internal VREF Select for Rank 3 +*/ #undef DDR_PHY_DX3GCR5_DXREFISELR3_DEFVAL #undef DDR_PHY_DX3GCR5_DXREFISELR3_SHIFT #undef DDR_PHY_DX3GCR5_DXREFISELR3_MASK -#define DDR_PHY_DX3GCR5_DXREFISELR3_DEFVAL 0x09090909 -#define DDR_PHY_DX3GCR5_DXREFISELR3_SHIFT 24 -#define DDR_PHY_DX3GCR5_DXREFISELR3_MASK 0x7F000000U +#define DDR_PHY_DX3GCR5_DXREFISELR3_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR5_DXREFISELR3_SHIFT 24 +#define DDR_PHY_DX3GCR5_DXREFISELR3_MASK 0x7F000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX3GCR5_RESERVED_23_DEFVAL #undef DDR_PHY_DX3GCR5_RESERVED_23_SHIFT #undef DDR_PHY_DX3GCR5_RESERVED_23_MASK -#define DDR_PHY_DX3GCR5_RESERVED_23_DEFVAL 0x09090909 -#define DDR_PHY_DX3GCR5_RESERVED_23_SHIFT 23 -#define DDR_PHY_DX3GCR5_RESERVED_23_MASK 0x00800000U +#define DDR_PHY_DX3GCR5_RESERVED_23_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR5_RESERVED_23_SHIFT 23 +#define DDR_PHY_DX3GCR5_RESERVED_23_MASK 0x00800000U -/*Byte Lane internal VREF Select for Rank 2*/ +/* +* Byte Lane internal VREF Select for Rank 2 +*/ #undef DDR_PHY_DX3GCR5_DXREFISELR2_DEFVAL #undef DDR_PHY_DX3GCR5_DXREFISELR2_SHIFT #undef DDR_PHY_DX3GCR5_DXREFISELR2_MASK -#define DDR_PHY_DX3GCR5_DXREFISELR2_DEFVAL 0x09090909 -#define DDR_PHY_DX3GCR5_DXREFISELR2_SHIFT 16 -#define DDR_PHY_DX3GCR5_DXREFISELR2_MASK 0x007F0000U +#define DDR_PHY_DX3GCR5_DXREFISELR2_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR5_DXREFISELR2_SHIFT 16 +#define DDR_PHY_DX3GCR5_DXREFISELR2_MASK 0x007F0000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX3GCR5_RESERVED_15_DEFVAL #undef DDR_PHY_DX3GCR5_RESERVED_15_SHIFT #undef DDR_PHY_DX3GCR5_RESERVED_15_MASK -#define DDR_PHY_DX3GCR5_RESERVED_15_DEFVAL 0x09090909 -#define DDR_PHY_DX3GCR5_RESERVED_15_SHIFT 15 -#define DDR_PHY_DX3GCR5_RESERVED_15_MASK 0x00008000U +#define DDR_PHY_DX3GCR5_RESERVED_15_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR5_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX3GCR5_RESERVED_15_MASK 0x00008000U -/*Byte Lane internal VREF Select for Rank 1*/ +/* +* Byte Lane internal VREF Select for Rank 1 +*/ #undef DDR_PHY_DX3GCR5_DXREFISELR1_DEFVAL #undef DDR_PHY_DX3GCR5_DXREFISELR1_SHIFT #undef DDR_PHY_DX3GCR5_DXREFISELR1_MASK -#define DDR_PHY_DX3GCR5_DXREFISELR1_DEFVAL 0x09090909 -#define DDR_PHY_DX3GCR5_DXREFISELR1_SHIFT 8 -#define DDR_PHY_DX3GCR5_DXREFISELR1_MASK 0x00007F00U +#define DDR_PHY_DX3GCR5_DXREFISELR1_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR5_DXREFISELR1_SHIFT 8 +#define DDR_PHY_DX3GCR5_DXREFISELR1_MASK 0x00007F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX3GCR5_RESERVED_7_DEFVAL #undef DDR_PHY_DX3GCR5_RESERVED_7_SHIFT #undef DDR_PHY_DX3GCR5_RESERVED_7_MASK -#define DDR_PHY_DX3GCR5_RESERVED_7_DEFVAL 0x09090909 -#define DDR_PHY_DX3GCR5_RESERVED_7_SHIFT 7 -#define DDR_PHY_DX3GCR5_RESERVED_7_MASK 0x00000080U +#define DDR_PHY_DX3GCR5_RESERVED_7_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR5_RESERVED_7_SHIFT 7 +#define DDR_PHY_DX3GCR5_RESERVED_7_MASK 0x00000080U -/*Byte Lane internal VREF Select for Rank 0*/ +/* +* Byte Lane internal VREF Select for Rank 0 +*/ #undef DDR_PHY_DX3GCR5_DXREFISELR0_DEFVAL #undef DDR_PHY_DX3GCR5_DXREFISELR0_SHIFT #undef DDR_PHY_DX3GCR5_DXREFISELR0_MASK -#define DDR_PHY_DX3GCR5_DXREFISELR0_DEFVAL 0x09090909 -#define DDR_PHY_DX3GCR5_DXREFISELR0_SHIFT 0 -#define DDR_PHY_DX3GCR5_DXREFISELR0_MASK 0x0000007FU +#define DDR_PHY_DX3GCR5_DXREFISELR0_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR5_DXREFISELR0_SHIFT 0 +#define DDR_PHY_DX3GCR5_DXREFISELR0_MASK 0x0000007FU -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX3GCR6_RESERVED_31_30_DEFVAL #undef DDR_PHY_DX3GCR6_RESERVED_31_30_SHIFT #undef DDR_PHY_DX3GCR6_RESERVED_31_30_MASK -#define DDR_PHY_DX3GCR6_RESERVED_31_30_DEFVAL 0x09090909 -#define DDR_PHY_DX3GCR6_RESERVED_31_30_SHIFT 30 -#define DDR_PHY_DX3GCR6_RESERVED_31_30_MASK 0xC0000000U +#define DDR_PHY_DX3GCR6_RESERVED_31_30_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR6_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX3GCR6_RESERVED_31_30_MASK 0xC0000000U -/*DRAM DQ VREF Select for Rank3*/ +/* +* DRAM DQ VREF Select for Rank3 +*/ #undef DDR_PHY_DX3GCR6_DXDQVREFR3_DEFVAL #undef DDR_PHY_DX3GCR6_DXDQVREFR3_SHIFT #undef DDR_PHY_DX3GCR6_DXDQVREFR3_MASK -#define DDR_PHY_DX3GCR6_DXDQVREFR3_DEFVAL 0x09090909 -#define DDR_PHY_DX3GCR6_DXDQVREFR3_SHIFT 24 -#define DDR_PHY_DX3GCR6_DXDQVREFR3_MASK 0x3F000000U +#define DDR_PHY_DX3GCR6_DXDQVREFR3_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR6_DXDQVREFR3_SHIFT 24 +#define DDR_PHY_DX3GCR6_DXDQVREFR3_MASK 0x3F000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX3GCR6_RESERVED_23_22_DEFVAL #undef DDR_PHY_DX3GCR6_RESERVED_23_22_SHIFT #undef DDR_PHY_DX3GCR6_RESERVED_23_22_MASK -#define DDR_PHY_DX3GCR6_RESERVED_23_22_DEFVAL 0x09090909 -#define DDR_PHY_DX3GCR6_RESERVED_23_22_SHIFT 22 -#define DDR_PHY_DX3GCR6_RESERVED_23_22_MASK 0x00C00000U +#define DDR_PHY_DX3GCR6_RESERVED_23_22_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR6_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX3GCR6_RESERVED_23_22_MASK 0x00C00000U -/*DRAM DQ VREF Select for Rank2*/ +/* +* DRAM DQ VREF Select for Rank2 +*/ #undef DDR_PHY_DX3GCR6_DXDQVREFR2_DEFVAL #undef DDR_PHY_DX3GCR6_DXDQVREFR2_SHIFT #undef DDR_PHY_DX3GCR6_DXDQVREFR2_MASK -#define DDR_PHY_DX3GCR6_DXDQVREFR2_DEFVAL 0x09090909 -#define DDR_PHY_DX3GCR6_DXDQVREFR2_SHIFT 16 -#define DDR_PHY_DX3GCR6_DXDQVREFR2_MASK 0x003F0000U +#define DDR_PHY_DX3GCR6_DXDQVREFR2_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR6_DXDQVREFR2_SHIFT 16 +#define DDR_PHY_DX3GCR6_DXDQVREFR2_MASK 0x003F0000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX3GCR6_RESERVED_15_14_DEFVAL #undef DDR_PHY_DX3GCR6_RESERVED_15_14_SHIFT #undef DDR_PHY_DX3GCR6_RESERVED_15_14_MASK -#define DDR_PHY_DX3GCR6_RESERVED_15_14_DEFVAL 0x09090909 -#define DDR_PHY_DX3GCR6_RESERVED_15_14_SHIFT 14 -#define DDR_PHY_DX3GCR6_RESERVED_15_14_MASK 0x0000C000U +#define DDR_PHY_DX3GCR6_RESERVED_15_14_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR6_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_DX3GCR6_RESERVED_15_14_MASK 0x0000C000U -/*DRAM DQ VREF Select for Rank1*/ +/* +* DRAM DQ VREF Select for Rank1 +*/ #undef DDR_PHY_DX3GCR6_DXDQVREFR1_DEFVAL #undef DDR_PHY_DX3GCR6_DXDQVREFR1_SHIFT #undef DDR_PHY_DX3GCR6_DXDQVREFR1_MASK -#define DDR_PHY_DX3GCR6_DXDQVREFR1_DEFVAL 0x09090909 -#define DDR_PHY_DX3GCR6_DXDQVREFR1_SHIFT 8 -#define DDR_PHY_DX3GCR6_DXDQVREFR1_MASK 0x00003F00U +#define DDR_PHY_DX3GCR6_DXDQVREFR1_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR6_DXDQVREFR1_SHIFT 8 +#define DDR_PHY_DX3GCR6_DXDQVREFR1_MASK 0x00003F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX3GCR6_RESERVED_7_6_DEFVAL #undef DDR_PHY_DX3GCR6_RESERVED_7_6_SHIFT #undef DDR_PHY_DX3GCR6_RESERVED_7_6_MASK -#define DDR_PHY_DX3GCR6_RESERVED_7_6_DEFVAL 0x09090909 -#define DDR_PHY_DX3GCR6_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_DX3GCR6_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_DX3GCR6_RESERVED_7_6_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR6_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX3GCR6_RESERVED_7_6_MASK 0x000000C0U -/*DRAM DQ VREF Select for Rank0*/ +/* +* DRAM DQ VREF Select for Rank0 +*/ #undef DDR_PHY_DX3GCR6_DXDQVREFR0_DEFVAL #undef DDR_PHY_DX3GCR6_DXDQVREFR0_SHIFT #undef DDR_PHY_DX3GCR6_DXDQVREFR0_MASK -#define DDR_PHY_DX3GCR6_DXDQVREFR0_DEFVAL 0x09090909 -#define DDR_PHY_DX3GCR6_DXDQVREFR0_SHIFT 0 -#define DDR_PHY_DX3GCR6_DXDQVREFR0_MASK 0x0000003FU +#define DDR_PHY_DX3GCR6_DXDQVREFR0_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR6_DXDQVREFR0_SHIFT 0 +#define DDR_PHY_DX3GCR6_DXDQVREFR0_MASK 0x0000003FU -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX3LCDLR2_RESERVED_31_25_DEFVAL -#undef DDR_PHY_DX3LCDLR2_RESERVED_31_25_SHIFT -#undef DDR_PHY_DX3LCDLR2_RESERVED_31_25_MASK -#define DDR_PHY_DX3LCDLR2_RESERVED_31_25_DEFVAL 0x00000000 -#define DDR_PHY_DX3LCDLR2_RESERVED_31_25_SHIFT 25 -#define DDR_PHY_DX3LCDLR2_RESERVED_31_25_MASK 0xFE000000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX3LCDLR2_RESERVED_24_16_DEFVAL -#undef DDR_PHY_DX3LCDLR2_RESERVED_24_16_SHIFT -#undef DDR_PHY_DX3LCDLR2_RESERVED_24_16_MASK -#define DDR_PHY_DX3LCDLR2_RESERVED_24_16_DEFVAL 0x00000000 -#define DDR_PHY_DX3LCDLR2_RESERVED_24_16_SHIFT 16 -#define DDR_PHY_DX3LCDLR2_RESERVED_24_16_MASK 0x01FF0000U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX3LCDLR2_RESERVED_15_9_DEFVAL -#undef DDR_PHY_DX3LCDLR2_RESERVED_15_9_SHIFT -#undef DDR_PHY_DX3LCDLR2_RESERVED_15_9_MASK -#define DDR_PHY_DX3LCDLR2_RESERVED_15_9_DEFVAL 0x00000000 -#define DDR_PHY_DX3LCDLR2_RESERVED_15_9_SHIFT 9 -#define DDR_PHY_DX3LCDLR2_RESERVED_15_9_MASK 0x0000FE00U - -/*Read DQS Gating Delay*/ -#undef DDR_PHY_DX3LCDLR2_DQSGD_DEFVAL -#undef DDR_PHY_DX3LCDLR2_DQSGD_SHIFT -#undef DDR_PHY_DX3LCDLR2_DQSGD_MASK -#define DDR_PHY_DX3LCDLR2_DQSGD_DEFVAL 0x00000000 -#define DDR_PHY_DX3LCDLR2_DQSGD_SHIFT 0 -#define DDR_PHY_DX3LCDLR2_DQSGD_MASK 0x000001FFU - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX3GTR0_RESERVED_31_24_DEFVAL -#undef DDR_PHY_DX3GTR0_RESERVED_31_24_SHIFT -#undef DDR_PHY_DX3GTR0_RESERVED_31_24_MASK -#define DDR_PHY_DX3GTR0_RESERVED_31_24_DEFVAL 0x00020000 -#define DDR_PHY_DX3GTR0_RESERVED_31_24_SHIFT 27 -#define DDR_PHY_DX3GTR0_RESERVED_31_24_MASK 0xF8000000U - -/*DQ Write Path Latency Pipeline*/ -#undef DDR_PHY_DX3GTR0_WDQSL_DEFVAL -#undef DDR_PHY_DX3GTR0_WDQSL_SHIFT -#undef DDR_PHY_DX3GTR0_WDQSL_MASK -#define DDR_PHY_DX3GTR0_WDQSL_DEFVAL 0x00020000 -#define DDR_PHY_DX3GTR0_WDQSL_SHIFT 24 -#define DDR_PHY_DX3GTR0_WDQSL_MASK 0x07000000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX3GTR0_RESERVED_23_20_DEFVAL -#undef DDR_PHY_DX3GTR0_RESERVED_23_20_SHIFT -#undef DDR_PHY_DX3GTR0_RESERVED_23_20_MASK -#define DDR_PHY_DX3GTR0_RESERVED_23_20_DEFVAL 0x00020000 -#define DDR_PHY_DX3GTR0_RESERVED_23_20_SHIFT 20 -#define DDR_PHY_DX3GTR0_RESERVED_23_20_MASK 0x00F00000U - -/*Write Leveling System Latency*/ -#undef DDR_PHY_DX3GTR0_WLSL_DEFVAL -#undef DDR_PHY_DX3GTR0_WLSL_SHIFT -#undef DDR_PHY_DX3GTR0_WLSL_MASK -#define DDR_PHY_DX3GTR0_WLSL_DEFVAL 0x00020000 -#define DDR_PHY_DX3GTR0_WLSL_SHIFT 16 -#define DDR_PHY_DX3GTR0_WLSL_MASK 0x000F0000U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX3GTR0_RESERVED_15_13_DEFVAL -#undef DDR_PHY_DX3GTR0_RESERVED_15_13_SHIFT -#undef DDR_PHY_DX3GTR0_RESERVED_15_13_MASK -#define DDR_PHY_DX3GTR0_RESERVED_15_13_DEFVAL 0x00020000 -#define DDR_PHY_DX3GTR0_RESERVED_15_13_SHIFT 13 -#define DDR_PHY_DX3GTR0_RESERVED_15_13_MASK 0x0000E000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX3GTR0_RESERVED_12_8_DEFVAL -#undef DDR_PHY_DX3GTR0_RESERVED_12_8_SHIFT -#undef DDR_PHY_DX3GTR0_RESERVED_12_8_MASK -#define DDR_PHY_DX3GTR0_RESERVED_12_8_DEFVAL 0x00020000 -#define DDR_PHY_DX3GTR0_RESERVED_12_8_SHIFT 8 -#define DDR_PHY_DX3GTR0_RESERVED_12_8_MASK 0x00001F00U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX3GTR0_RESERVED_7_5_DEFVAL -#undef DDR_PHY_DX3GTR0_RESERVED_7_5_SHIFT -#undef DDR_PHY_DX3GTR0_RESERVED_7_5_MASK -#define DDR_PHY_DX3GTR0_RESERVED_7_5_DEFVAL 0x00020000 -#define DDR_PHY_DX3GTR0_RESERVED_7_5_SHIFT 5 -#define DDR_PHY_DX3GTR0_RESERVED_7_5_MASK 0x000000E0U - -/*DQS Gating System Latency*/ -#undef DDR_PHY_DX3GTR0_DGSL_DEFVAL -#undef DDR_PHY_DX3GTR0_DGSL_SHIFT -#undef DDR_PHY_DX3GTR0_DGSL_MASK -#define DDR_PHY_DX3GTR0_DGSL_DEFVAL 0x00020000 -#define DDR_PHY_DX3GTR0_DGSL_SHIFT 0 -#define DDR_PHY_DX3GTR0_DGSL_MASK 0x0000001FU - -/*Calibration Bypass*/ +/* +* Calibration Bypass +*/ #undef DDR_PHY_DX4GCR0_CALBYP_DEFVAL #undef DDR_PHY_DX4GCR0_CALBYP_SHIFT #undef DDR_PHY_DX4GCR0_CALBYP_MASK -#define DDR_PHY_DX4GCR0_CALBYP_DEFVAL 0x40200204 -#define DDR_PHY_DX4GCR0_CALBYP_SHIFT 31 -#define DDR_PHY_DX4GCR0_CALBYP_MASK 0x80000000U +#define DDR_PHY_DX4GCR0_CALBYP_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_CALBYP_SHIFT 31 +#define DDR_PHY_DX4GCR0_CALBYP_MASK 0x80000000U -/*Master Delay Line Enable*/ +/* +* Master Delay Line Enable +*/ #undef DDR_PHY_DX4GCR0_MDLEN_DEFVAL #undef DDR_PHY_DX4GCR0_MDLEN_SHIFT #undef DDR_PHY_DX4GCR0_MDLEN_MASK -#define DDR_PHY_DX4GCR0_MDLEN_DEFVAL 0x40200204 -#define DDR_PHY_DX4GCR0_MDLEN_SHIFT 30 -#define DDR_PHY_DX4GCR0_MDLEN_MASK 0x40000000U +#define DDR_PHY_DX4GCR0_MDLEN_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_MDLEN_SHIFT 30 +#define DDR_PHY_DX4GCR0_MDLEN_MASK 0x40000000U -/*Configurable ODT(TE) Phase Shift*/ +/* +* Configurable ODT(TE) Phase Shift +*/ #undef DDR_PHY_DX4GCR0_CODTSHFT_DEFVAL #undef DDR_PHY_DX4GCR0_CODTSHFT_SHIFT #undef DDR_PHY_DX4GCR0_CODTSHFT_MASK -#define DDR_PHY_DX4GCR0_CODTSHFT_DEFVAL 0x40200204 -#define DDR_PHY_DX4GCR0_CODTSHFT_SHIFT 28 -#define DDR_PHY_DX4GCR0_CODTSHFT_MASK 0x30000000U +#define DDR_PHY_DX4GCR0_CODTSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_CODTSHFT_SHIFT 28 +#define DDR_PHY_DX4GCR0_CODTSHFT_MASK 0x30000000U -/*DQS Duty Cycle Correction*/ +/* +* DQS Duty Cycle Correction +*/ #undef DDR_PHY_DX4GCR0_DQSDCC_DEFVAL #undef DDR_PHY_DX4GCR0_DQSDCC_SHIFT #undef DDR_PHY_DX4GCR0_DQSDCC_MASK -#define DDR_PHY_DX4GCR0_DQSDCC_DEFVAL 0x40200204 -#define DDR_PHY_DX4GCR0_DQSDCC_SHIFT 24 -#define DDR_PHY_DX4GCR0_DQSDCC_MASK 0x0F000000U +#define DDR_PHY_DX4GCR0_DQSDCC_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_DQSDCC_SHIFT 24 +#define DDR_PHY_DX4GCR0_DQSDCC_MASK 0x0F000000U -/*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/ +/* +* Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY +*/ #undef DDR_PHY_DX4GCR0_RDDLY_DEFVAL #undef DDR_PHY_DX4GCR0_RDDLY_SHIFT #undef DDR_PHY_DX4GCR0_RDDLY_MASK -#define DDR_PHY_DX4GCR0_RDDLY_DEFVAL 0x40200204 -#define DDR_PHY_DX4GCR0_RDDLY_SHIFT 20 -#define DDR_PHY_DX4GCR0_RDDLY_MASK 0x00F00000U +#define DDR_PHY_DX4GCR0_RDDLY_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_RDDLY_SHIFT 20 +#define DDR_PHY_DX4GCR0_RDDLY_MASK 0x00F00000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX4GCR0_RESERVED_19_14_DEFVAL #undef DDR_PHY_DX4GCR0_RESERVED_19_14_SHIFT #undef DDR_PHY_DX4GCR0_RESERVED_19_14_MASK -#define DDR_PHY_DX4GCR0_RESERVED_19_14_DEFVAL 0x40200204 -#define DDR_PHY_DX4GCR0_RESERVED_19_14_SHIFT 14 -#define DDR_PHY_DX4GCR0_RESERVED_19_14_MASK 0x000FC000U +#define DDR_PHY_DX4GCR0_RESERVED_19_14_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_RESERVED_19_14_SHIFT 14 +#define DDR_PHY_DX4GCR0_RESERVED_19_14_MASK 0x000FC000U -/*DQSNSE Power Down Receiver*/ +/* +* DQSNSE Power Down Receiver +*/ #undef DDR_PHY_DX4GCR0_DQSNSEPDR_DEFVAL #undef DDR_PHY_DX4GCR0_DQSNSEPDR_SHIFT #undef DDR_PHY_DX4GCR0_DQSNSEPDR_MASK -#define DDR_PHY_DX4GCR0_DQSNSEPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX4GCR0_DQSNSEPDR_SHIFT 13 -#define DDR_PHY_DX4GCR0_DQSNSEPDR_MASK 0x00002000U +#define DDR_PHY_DX4GCR0_DQSNSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_DQSNSEPDR_SHIFT 13 +#define DDR_PHY_DX4GCR0_DQSNSEPDR_MASK 0x00002000U -/*DQSSE Power Down Receiver*/ +/* +* DQSSE Power Down Receiver +*/ #undef DDR_PHY_DX4GCR0_DQSSEPDR_DEFVAL #undef DDR_PHY_DX4GCR0_DQSSEPDR_SHIFT #undef DDR_PHY_DX4GCR0_DQSSEPDR_MASK -#define DDR_PHY_DX4GCR0_DQSSEPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX4GCR0_DQSSEPDR_SHIFT 12 -#define DDR_PHY_DX4GCR0_DQSSEPDR_MASK 0x00001000U +#define DDR_PHY_DX4GCR0_DQSSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_DQSSEPDR_SHIFT 12 +#define DDR_PHY_DX4GCR0_DQSSEPDR_MASK 0x00001000U -/*RTT On Additive Latency*/ +/* +* RTT On Additive Latency +*/ #undef DDR_PHY_DX4GCR0_RTTOAL_DEFVAL #undef DDR_PHY_DX4GCR0_RTTOAL_SHIFT #undef DDR_PHY_DX4GCR0_RTTOAL_MASK -#define DDR_PHY_DX4GCR0_RTTOAL_DEFVAL 0x40200204 -#define DDR_PHY_DX4GCR0_RTTOAL_SHIFT 11 -#define DDR_PHY_DX4GCR0_RTTOAL_MASK 0x00000800U +#define DDR_PHY_DX4GCR0_RTTOAL_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_RTTOAL_SHIFT 11 +#define DDR_PHY_DX4GCR0_RTTOAL_MASK 0x00000800U -/*RTT Output Hold*/ +/* +* RTT Output Hold +*/ #undef DDR_PHY_DX4GCR0_RTTOH_DEFVAL #undef DDR_PHY_DX4GCR0_RTTOH_SHIFT #undef DDR_PHY_DX4GCR0_RTTOH_MASK -#define DDR_PHY_DX4GCR0_RTTOH_DEFVAL 0x40200204 -#define DDR_PHY_DX4GCR0_RTTOH_SHIFT 9 -#define DDR_PHY_DX4GCR0_RTTOH_MASK 0x00000600U +#define DDR_PHY_DX4GCR0_RTTOH_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_RTTOH_SHIFT 9 +#define DDR_PHY_DX4GCR0_RTTOH_MASK 0x00000600U -/*Configurable PDR Phase Shift*/ +/* +* Configurable PDR Phase Shift +*/ #undef DDR_PHY_DX4GCR0_CPDRSHFT_DEFVAL #undef DDR_PHY_DX4GCR0_CPDRSHFT_SHIFT #undef DDR_PHY_DX4GCR0_CPDRSHFT_MASK -#define DDR_PHY_DX4GCR0_CPDRSHFT_DEFVAL 0x40200204 -#define DDR_PHY_DX4GCR0_CPDRSHFT_SHIFT 7 -#define DDR_PHY_DX4GCR0_CPDRSHFT_MASK 0x00000180U +#define DDR_PHY_DX4GCR0_CPDRSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_CPDRSHFT_SHIFT 7 +#define DDR_PHY_DX4GCR0_CPDRSHFT_MASK 0x00000180U -/*DQSR Power Down*/ +/* +* DQSR Power Down +*/ #undef DDR_PHY_DX4GCR0_DQSRPD_DEFVAL #undef DDR_PHY_DX4GCR0_DQSRPD_SHIFT #undef DDR_PHY_DX4GCR0_DQSRPD_MASK -#define DDR_PHY_DX4GCR0_DQSRPD_DEFVAL 0x40200204 -#define DDR_PHY_DX4GCR0_DQSRPD_SHIFT 6 -#define DDR_PHY_DX4GCR0_DQSRPD_MASK 0x00000040U +#define DDR_PHY_DX4GCR0_DQSRPD_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_DQSRPD_SHIFT 6 +#define DDR_PHY_DX4GCR0_DQSRPD_MASK 0x00000040U -/*DQSG Power Down Receiver*/ +/* +* DQSG Power Down Receiver +*/ #undef DDR_PHY_DX4GCR0_DQSGPDR_DEFVAL #undef DDR_PHY_DX4GCR0_DQSGPDR_SHIFT #undef DDR_PHY_DX4GCR0_DQSGPDR_MASK -#define DDR_PHY_DX4GCR0_DQSGPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX4GCR0_DQSGPDR_SHIFT 5 -#define DDR_PHY_DX4GCR0_DQSGPDR_MASK 0x00000020U +#define DDR_PHY_DX4GCR0_DQSGPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_DQSGPDR_SHIFT 5 +#define DDR_PHY_DX4GCR0_DQSGPDR_MASK 0x00000020U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX4GCR0_RESERVED_4_DEFVAL #undef DDR_PHY_DX4GCR0_RESERVED_4_SHIFT #undef DDR_PHY_DX4GCR0_RESERVED_4_MASK -#define DDR_PHY_DX4GCR0_RESERVED_4_DEFVAL 0x40200204 -#define DDR_PHY_DX4GCR0_RESERVED_4_SHIFT 4 -#define DDR_PHY_DX4GCR0_RESERVED_4_MASK 0x00000010U +#define DDR_PHY_DX4GCR0_RESERVED_4_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_RESERVED_4_SHIFT 4 +#define DDR_PHY_DX4GCR0_RESERVED_4_MASK 0x00000010U -/*DQSG On-Die Termination*/ +/* +* DQSG On-Die Termination +*/ #undef DDR_PHY_DX4GCR0_DQSGODT_DEFVAL #undef DDR_PHY_DX4GCR0_DQSGODT_SHIFT #undef DDR_PHY_DX4GCR0_DQSGODT_MASK -#define DDR_PHY_DX4GCR0_DQSGODT_DEFVAL 0x40200204 -#define DDR_PHY_DX4GCR0_DQSGODT_SHIFT 3 -#define DDR_PHY_DX4GCR0_DQSGODT_MASK 0x00000008U +#define DDR_PHY_DX4GCR0_DQSGODT_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_DQSGODT_SHIFT 3 +#define DDR_PHY_DX4GCR0_DQSGODT_MASK 0x00000008U -/*DQSG Output Enable*/ +/* +* DQSG Output Enable +*/ #undef DDR_PHY_DX4GCR0_DQSGOE_DEFVAL #undef DDR_PHY_DX4GCR0_DQSGOE_SHIFT #undef DDR_PHY_DX4GCR0_DQSGOE_MASK -#define DDR_PHY_DX4GCR0_DQSGOE_DEFVAL 0x40200204 -#define DDR_PHY_DX4GCR0_DQSGOE_SHIFT 2 -#define DDR_PHY_DX4GCR0_DQSGOE_MASK 0x00000004U +#define DDR_PHY_DX4GCR0_DQSGOE_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_DQSGOE_SHIFT 2 +#define DDR_PHY_DX4GCR0_DQSGOE_MASK 0x00000004U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX4GCR0_RESERVED_1_0_DEFVAL #undef DDR_PHY_DX4GCR0_RESERVED_1_0_SHIFT #undef DDR_PHY_DX4GCR0_RESERVED_1_0_MASK -#define DDR_PHY_DX4GCR0_RESERVED_1_0_DEFVAL 0x40200204 -#define DDR_PHY_DX4GCR0_RESERVED_1_0_SHIFT 0 -#define DDR_PHY_DX4GCR0_RESERVED_1_0_MASK 0x00000003U +#define DDR_PHY_DX4GCR0_RESERVED_1_0_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_RESERVED_1_0_SHIFT 0 +#define DDR_PHY_DX4GCR0_RESERVED_1_0_MASK 0x00000003U -/*Enables the PDR mode for DQ[7:0]*/ +/* +* Enables the PDR mode for DQ[7:0] +*/ #undef DDR_PHY_DX4GCR1_DXPDRMODE_DEFVAL #undef DDR_PHY_DX4GCR1_DXPDRMODE_SHIFT #undef DDR_PHY_DX4GCR1_DXPDRMODE_MASK -#define DDR_PHY_DX4GCR1_DXPDRMODE_DEFVAL 0x00007FFF -#define DDR_PHY_DX4GCR1_DXPDRMODE_SHIFT 16 -#define DDR_PHY_DX4GCR1_DXPDRMODE_MASK 0xFFFF0000U +#define DDR_PHY_DX4GCR1_DXPDRMODE_DEFVAL 0x00007FFF +#define DDR_PHY_DX4GCR1_DXPDRMODE_SHIFT 16 +#define DDR_PHY_DX4GCR1_DXPDRMODE_MASK 0xFFFF0000U -/*Reserved. Returns zeroes on reads.*/ +/* +* Reserved. Returns zeroes on reads. +*/ #undef DDR_PHY_DX4GCR1_RESERVED_15_DEFVAL #undef DDR_PHY_DX4GCR1_RESERVED_15_SHIFT #undef DDR_PHY_DX4GCR1_RESERVED_15_MASK -#define DDR_PHY_DX4GCR1_RESERVED_15_DEFVAL 0x00007FFF -#define DDR_PHY_DX4GCR1_RESERVED_15_SHIFT 15 -#define DDR_PHY_DX4GCR1_RESERVED_15_MASK 0x00008000U +#define DDR_PHY_DX4GCR1_RESERVED_15_DEFVAL 0x00007FFF +#define DDR_PHY_DX4GCR1_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX4GCR1_RESERVED_15_MASK 0x00008000U -/*Select the delayed or non-delayed read data strobe #*/ +/* +* Select the delayed or non-delayed read data strobe # +*/ #undef DDR_PHY_DX4GCR1_QSNSEL_DEFVAL #undef DDR_PHY_DX4GCR1_QSNSEL_SHIFT #undef DDR_PHY_DX4GCR1_QSNSEL_MASK -#define DDR_PHY_DX4GCR1_QSNSEL_DEFVAL 0x00007FFF -#define DDR_PHY_DX4GCR1_QSNSEL_SHIFT 14 -#define DDR_PHY_DX4GCR1_QSNSEL_MASK 0x00004000U +#define DDR_PHY_DX4GCR1_QSNSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX4GCR1_QSNSEL_SHIFT 14 +#define DDR_PHY_DX4GCR1_QSNSEL_MASK 0x00004000U -/*Select the delayed or non-delayed read data strobe*/ +/* +* Select the delayed or non-delayed read data strobe +*/ #undef DDR_PHY_DX4GCR1_QSSEL_DEFVAL #undef DDR_PHY_DX4GCR1_QSSEL_SHIFT #undef DDR_PHY_DX4GCR1_QSSEL_MASK -#define DDR_PHY_DX4GCR1_QSSEL_DEFVAL 0x00007FFF -#define DDR_PHY_DX4GCR1_QSSEL_SHIFT 13 -#define DDR_PHY_DX4GCR1_QSSEL_MASK 0x00002000U +#define DDR_PHY_DX4GCR1_QSSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX4GCR1_QSSEL_SHIFT 13 +#define DDR_PHY_DX4GCR1_QSSEL_MASK 0x00002000U -/*Enables Read Data Strobe in a byte lane*/ +/* +* Enables Read Data Strobe in a byte lane +*/ #undef DDR_PHY_DX4GCR1_OEEN_DEFVAL #undef DDR_PHY_DX4GCR1_OEEN_SHIFT #undef DDR_PHY_DX4GCR1_OEEN_MASK -#define DDR_PHY_DX4GCR1_OEEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX4GCR1_OEEN_SHIFT 12 -#define DDR_PHY_DX4GCR1_OEEN_MASK 0x00001000U +#define DDR_PHY_DX4GCR1_OEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX4GCR1_OEEN_SHIFT 12 +#define DDR_PHY_DX4GCR1_OEEN_MASK 0x00001000U -/*Enables PDR in a byte lane*/ +/* +* Enables PDR in a byte lane +*/ #undef DDR_PHY_DX4GCR1_PDREN_DEFVAL #undef DDR_PHY_DX4GCR1_PDREN_SHIFT #undef DDR_PHY_DX4GCR1_PDREN_MASK -#define DDR_PHY_DX4GCR1_PDREN_DEFVAL 0x00007FFF -#define DDR_PHY_DX4GCR1_PDREN_SHIFT 11 -#define DDR_PHY_DX4GCR1_PDREN_MASK 0x00000800U +#define DDR_PHY_DX4GCR1_PDREN_DEFVAL 0x00007FFF +#define DDR_PHY_DX4GCR1_PDREN_SHIFT 11 +#define DDR_PHY_DX4GCR1_PDREN_MASK 0x00000800U -/*Enables ODT/TE in a byte lane*/ +/* +* Enables ODT/TE in a byte lane +*/ #undef DDR_PHY_DX4GCR1_TEEN_DEFVAL #undef DDR_PHY_DX4GCR1_TEEN_SHIFT #undef DDR_PHY_DX4GCR1_TEEN_MASK -#define DDR_PHY_DX4GCR1_TEEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX4GCR1_TEEN_SHIFT 10 -#define DDR_PHY_DX4GCR1_TEEN_MASK 0x00000400U +#define DDR_PHY_DX4GCR1_TEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX4GCR1_TEEN_SHIFT 10 +#define DDR_PHY_DX4GCR1_TEEN_MASK 0x00000400U -/*Enables Write Data strobe in a byte lane*/ +/* +* Enables Write Data strobe in a byte lane +*/ #undef DDR_PHY_DX4GCR1_DSEN_DEFVAL #undef DDR_PHY_DX4GCR1_DSEN_SHIFT #undef DDR_PHY_DX4GCR1_DSEN_MASK -#define DDR_PHY_DX4GCR1_DSEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX4GCR1_DSEN_SHIFT 9 -#define DDR_PHY_DX4GCR1_DSEN_MASK 0x00000200U +#define DDR_PHY_DX4GCR1_DSEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX4GCR1_DSEN_SHIFT 9 +#define DDR_PHY_DX4GCR1_DSEN_MASK 0x00000200U -/*Enables DM pin in a byte lane*/ +/* +* Enables DM pin in a byte lane +*/ #undef DDR_PHY_DX4GCR1_DMEN_DEFVAL #undef DDR_PHY_DX4GCR1_DMEN_SHIFT #undef DDR_PHY_DX4GCR1_DMEN_MASK -#define DDR_PHY_DX4GCR1_DMEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX4GCR1_DMEN_SHIFT 8 -#define DDR_PHY_DX4GCR1_DMEN_MASK 0x00000100U +#define DDR_PHY_DX4GCR1_DMEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX4GCR1_DMEN_SHIFT 8 +#define DDR_PHY_DX4GCR1_DMEN_MASK 0x00000100U -/*Enables DQ corresponding to each bit in a byte*/ +/* +* Enables DQ corresponding to each bit in a byte +*/ #undef DDR_PHY_DX4GCR1_DQEN_DEFVAL #undef DDR_PHY_DX4GCR1_DQEN_SHIFT #undef DDR_PHY_DX4GCR1_DQEN_MASK -#define DDR_PHY_DX4GCR1_DQEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX4GCR1_DQEN_SHIFT 0 -#define DDR_PHY_DX4GCR1_DQEN_MASK 0x000000FFU +#define DDR_PHY_DX4GCR1_DQEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX4GCR1_DQEN_SHIFT 0 +#define DDR_PHY_DX4GCR1_DQEN_MASK 0x000000FFU -/*Byte lane VREF IOM (Used only by D4MU IOs)*/ +/* +* Byte lane VREF IOM (Used only by D4MU IOs) +*/ #undef DDR_PHY_DX4GCR4_RESERVED_31_29_DEFVAL #undef DDR_PHY_DX4GCR4_RESERVED_31_29_SHIFT #undef DDR_PHY_DX4GCR4_RESERVED_31_29_MASK -#define DDR_PHY_DX4GCR4_RESERVED_31_29_DEFVAL 0x0E00003C -#define DDR_PHY_DX4GCR4_RESERVED_31_29_SHIFT 29 -#define DDR_PHY_DX4GCR4_RESERVED_31_29_MASK 0xE0000000U +#define DDR_PHY_DX4GCR4_RESERVED_31_29_DEFVAL 0x0E00003C +#define DDR_PHY_DX4GCR4_RESERVED_31_29_SHIFT 29 +#define DDR_PHY_DX4GCR4_RESERVED_31_29_MASK 0xE0000000U -/*Byte Lane VREF Pad Enable*/ +/* +* Byte Lane VREF Pad Enable +*/ #undef DDR_PHY_DX4GCR4_DXREFPEN_DEFVAL #undef DDR_PHY_DX4GCR4_DXREFPEN_SHIFT #undef DDR_PHY_DX4GCR4_DXREFPEN_MASK -#define DDR_PHY_DX4GCR4_DXREFPEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX4GCR4_DXREFPEN_SHIFT 28 -#define DDR_PHY_DX4GCR4_DXREFPEN_MASK 0x10000000U +#define DDR_PHY_DX4GCR4_DXREFPEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX4GCR4_DXREFPEN_SHIFT 28 +#define DDR_PHY_DX4GCR4_DXREFPEN_MASK 0x10000000U -/*Byte Lane Internal VREF Enable*/ +/* +* Byte Lane Internal VREF Enable +*/ #undef DDR_PHY_DX4GCR4_DXREFEEN_DEFVAL #undef DDR_PHY_DX4GCR4_DXREFEEN_SHIFT #undef DDR_PHY_DX4GCR4_DXREFEEN_MASK -#define DDR_PHY_DX4GCR4_DXREFEEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX4GCR4_DXREFEEN_SHIFT 26 -#define DDR_PHY_DX4GCR4_DXREFEEN_MASK 0x0C000000U +#define DDR_PHY_DX4GCR4_DXREFEEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX4GCR4_DXREFEEN_SHIFT 26 +#define DDR_PHY_DX4GCR4_DXREFEEN_MASK 0x0C000000U -/*Byte Lane Single-End VREF Enable*/ +/* +* Byte Lane Single-End VREF Enable +*/ #undef DDR_PHY_DX4GCR4_DXREFSEN_DEFVAL #undef DDR_PHY_DX4GCR4_DXREFSEN_SHIFT #undef DDR_PHY_DX4GCR4_DXREFSEN_MASK -#define DDR_PHY_DX4GCR4_DXREFSEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX4GCR4_DXREFSEN_SHIFT 25 -#define DDR_PHY_DX4GCR4_DXREFSEN_MASK 0x02000000U +#define DDR_PHY_DX4GCR4_DXREFSEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX4GCR4_DXREFSEN_SHIFT 25 +#define DDR_PHY_DX4GCR4_DXREFSEN_MASK 0x02000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX4GCR4_RESERVED_24_DEFVAL #undef DDR_PHY_DX4GCR4_RESERVED_24_SHIFT #undef DDR_PHY_DX4GCR4_RESERVED_24_MASK -#define DDR_PHY_DX4GCR4_RESERVED_24_DEFVAL 0x0E00003C -#define DDR_PHY_DX4GCR4_RESERVED_24_SHIFT 24 -#define DDR_PHY_DX4GCR4_RESERVED_24_MASK 0x01000000U +#define DDR_PHY_DX4GCR4_RESERVED_24_DEFVAL 0x0E00003C +#define DDR_PHY_DX4GCR4_RESERVED_24_SHIFT 24 +#define DDR_PHY_DX4GCR4_RESERVED_24_MASK 0x01000000U -/*External VREF generator REFSEL range select*/ +/* +* External VREF generator REFSEL range select +*/ #undef DDR_PHY_DX4GCR4_DXREFESELRANGE_DEFVAL #undef DDR_PHY_DX4GCR4_DXREFESELRANGE_SHIFT #undef DDR_PHY_DX4GCR4_DXREFESELRANGE_MASK -#define DDR_PHY_DX4GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C -#define DDR_PHY_DX4GCR4_DXREFESELRANGE_SHIFT 23 -#define DDR_PHY_DX4GCR4_DXREFESELRANGE_MASK 0x00800000U +#define DDR_PHY_DX4GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX4GCR4_DXREFESELRANGE_SHIFT 23 +#define DDR_PHY_DX4GCR4_DXREFESELRANGE_MASK 0x00800000U -/*Byte Lane External VREF Select*/ +/* +* Byte Lane External VREF Select +*/ #undef DDR_PHY_DX4GCR4_DXREFESEL_DEFVAL #undef DDR_PHY_DX4GCR4_DXREFESEL_SHIFT #undef DDR_PHY_DX4GCR4_DXREFESEL_MASK -#define DDR_PHY_DX4GCR4_DXREFESEL_DEFVAL 0x0E00003C -#define DDR_PHY_DX4GCR4_DXREFESEL_SHIFT 16 -#define DDR_PHY_DX4GCR4_DXREFESEL_MASK 0x007F0000U +#define DDR_PHY_DX4GCR4_DXREFESEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX4GCR4_DXREFESEL_SHIFT 16 +#define DDR_PHY_DX4GCR4_DXREFESEL_MASK 0x007F0000U -/*Single ended VREF generator REFSEL range select*/ +/* +* Single ended VREF generator REFSEL range select +*/ #undef DDR_PHY_DX4GCR4_DXREFSSELRANGE_DEFVAL #undef DDR_PHY_DX4GCR4_DXREFSSELRANGE_SHIFT #undef DDR_PHY_DX4GCR4_DXREFSSELRANGE_MASK -#define DDR_PHY_DX4GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C -#define DDR_PHY_DX4GCR4_DXREFSSELRANGE_SHIFT 15 -#define DDR_PHY_DX4GCR4_DXREFSSELRANGE_MASK 0x00008000U +#define DDR_PHY_DX4GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX4GCR4_DXREFSSELRANGE_SHIFT 15 +#define DDR_PHY_DX4GCR4_DXREFSSELRANGE_MASK 0x00008000U -/*Byte Lane Single-End VREF Select*/ +/* +* Byte Lane Single-End VREF Select +*/ #undef DDR_PHY_DX4GCR4_DXREFSSEL_DEFVAL #undef DDR_PHY_DX4GCR4_DXREFSSEL_SHIFT #undef DDR_PHY_DX4GCR4_DXREFSSEL_MASK -#define DDR_PHY_DX4GCR4_DXREFSSEL_DEFVAL 0x0E00003C -#define DDR_PHY_DX4GCR4_DXREFSSEL_SHIFT 8 -#define DDR_PHY_DX4GCR4_DXREFSSEL_MASK 0x00007F00U +#define DDR_PHY_DX4GCR4_DXREFSSEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX4GCR4_DXREFSSEL_SHIFT 8 +#define DDR_PHY_DX4GCR4_DXREFSSEL_MASK 0x00007F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX4GCR4_RESERVED_7_6_DEFVAL #undef DDR_PHY_DX4GCR4_RESERVED_7_6_SHIFT #undef DDR_PHY_DX4GCR4_RESERVED_7_6_MASK -#define DDR_PHY_DX4GCR4_RESERVED_7_6_DEFVAL 0x0E00003C -#define DDR_PHY_DX4GCR4_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_DX4GCR4_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_DX4GCR4_RESERVED_7_6_DEFVAL 0x0E00003C +#define DDR_PHY_DX4GCR4_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX4GCR4_RESERVED_7_6_MASK 0x000000C0U -/*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/ +/* +* VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. +*/ #undef DDR_PHY_DX4GCR4_DXREFIEN_DEFVAL #undef DDR_PHY_DX4GCR4_DXREFIEN_SHIFT #undef DDR_PHY_DX4GCR4_DXREFIEN_MASK -#define DDR_PHY_DX4GCR4_DXREFIEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX4GCR4_DXREFIEN_SHIFT 2 -#define DDR_PHY_DX4GCR4_DXREFIEN_MASK 0x0000003CU +#define DDR_PHY_DX4GCR4_DXREFIEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX4GCR4_DXREFIEN_SHIFT 2 +#define DDR_PHY_DX4GCR4_DXREFIEN_MASK 0x0000003CU -/*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/ +/* +* VRMON control for DQ IO (Single Ended) buffers of a byte lane. +*/ #undef DDR_PHY_DX4GCR4_DXREFIMON_DEFVAL #undef DDR_PHY_DX4GCR4_DXREFIMON_SHIFT #undef DDR_PHY_DX4GCR4_DXREFIMON_MASK -#define DDR_PHY_DX4GCR4_DXREFIMON_DEFVAL 0x0E00003C -#define DDR_PHY_DX4GCR4_DXREFIMON_SHIFT 0 -#define DDR_PHY_DX4GCR4_DXREFIMON_MASK 0x00000003U +#define DDR_PHY_DX4GCR4_DXREFIMON_DEFVAL 0x0E00003C +#define DDR_PHY_DX4GCR4_DXREFIMON_SHIFT 0 +#define DDR_PHY_DX4GCR4_DXREFIMON_MASK 0x00000003U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX4GCR5_RESERVED_31_DEFVAL #undef DDR_PHY_DX4GCR5_RESERVED_31_SHIFT #undef DDR_PHY_DX4GCR5_RESERVED_31_MASK -#define DDR_PHY_DX4GCR5_RESERVED_31_DEFVAL 0x09090909 -#define DDR_PHY_DX4GCR5_RESERVED_31_SHIFT 31 -#define DDR_PHY_DX4GCR5_RESERVED_31_MASK 0x80000000U +#define DDR_PHY_DX4GCR5_RESERVED_31_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR5_RESERVED_31_SHIFT 31 +#define DDR_PHY_DX4GCR5_RESERVED_31_MASK 0x80000000U -/*Byte Lane internal VREF Select for Rank 3*/ +/* +* Byte Lane internal VREF Select for Rank 3 +*/ #undef DDR_PHY_DX4GCR5_DXREFISELR3_DEFVAL #undef DDR_PHY_DX4GCR5_DXREFISELR3_SHIFT #undef DDR_PHY_DX4GCR5_DXREFISELR3_MASK -#define DDR_PHY_DX4GCR5_DXREFISELR3_DEFVAL 0x09090909 -#define DDR_PHY_DX4GCR5_DXREFISELR3_SHIFT 24 -#define DDR_PHY_DX4GCR5_DXREFISELR3_MASK 0x7F000000U +#define DDR_PHY_DX4GCR5_DXREFISELR3_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR5_DXREFISELR3_SHIFT 24 +#define DDR_PHY_DX4GCR5_DXREFISELR3_MASK 0x7F000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX4GCR5_RESERVED_23_DEFVAL #undef DDR_PHY_DX4GCR5_RESERVED_23_SHIFT #undef DDR_PHY_DX4GCR5_RESERVED_23_MASK -#define DDR_PHY_DX4GCR5_RESERVED_23_DEFVAL 0x09090909 -#define DDR_PHY_DX4GCR5_RESERVED_23_SHIFT 23 -#define DDR_PHY_DX4GCR5_RESERVED_23_MASK 0x00800000U +#define DDR_PHY_DX4GCR5_RESERVED_23_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR5_RESERVED_23_SHIFT 23 +#define DDR_PHY_DX4GCR5_RESERVED_23_MASK 0x00800000U -/*Byte Lane internal VREF Select for Rank 2*/ +/* +* Byte Lane internal VREF Select for Rank 2 +*/ #undef DDR_PHY_DX4GCR5_DXREFISELR2_DEFVAL #undef DDR_PHY_DX4GCR5_DXREFISELR2_SHIFT #undef DDR_PHY_DX4GCR5_DXREFISELR2_MASK -#define DDR_PHY_DX4GCR5_DXREFISELR2_DEFVAL 0x09090909 -#define DDR_PHY_DX4GCR5_DXREFISELR2_SHIFT 16 -#define DDR_PHY_DX4GCR5_DXREFISELR2_MASK 0x007F0000U +#define DDR_PHY_DX4GCR5_DXREFISELR2_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR5_DXREFISELR2_SHIFT 16 +#define DDR_PHY_DX4GCR5_DXREFISELR2_MASK 0x007F0000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX4GCR5_RESERVED_15_DEFVAL #undef DDR_PHY_DX4GCR5_RESERVED_15_SHIFT #undef DDR_PHY_DX4GCR5_RESERVED_15_MASK -#define DDR_PHY_DX4GCR5_RESERVED_15_DEFVAL 0x09090909 -#define DDR_PHY_DX4GCR5_RESERVED_15_SHIFT 15 -#define DDR_PHY_DX4GCR5_RESERVED_15_MASK 0x00008000U +#define DDR_PHY_DX4GCR5_RESERVED_15_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR5_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX4GCR5_RESERVED_15_MASK 0x00008000U -/*Byte Lane internal VREF Select for Rank 1*/ +/* +* Byte Lane internal VREF Select for Rank 1 +*/ #undef DDR_PHY_DX4GCR5_DXREFISELR1_DEFVAL #undef DDR_PHY_DX4GCR5_DXREFISELR1_SHIFT #undef DDR_PHY_DX4GCR5_DXREFISELR1_MASK -#define DDR_PHY_DX4GCR5_DXREFISELR1_DEFVAL 0x09090909 -#define DDR_PHY_DX4GCR5_DXREFISELR1_SHIFT 8 -#define DDR_PHY_DX4GCR5_DXREFISELR1_MASK 0x00007F00U +#define DDR_PHY_DX4GCR5_DXREFISELR1_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR5_DXREFISELR1_SHIFT 8 +#define DDR_PHY_DX4GCR5_DXREFISELR1_MASK 0x00007F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX4GCR5_RESERVED_7_DEFVAL #undef DDR_PHY_DX4GCR5_RESERVED_7_SHIFT #undef DDR_PHY_DX4GCR5_RESERVED_7_MASK -#define DDR_PHY_DX4GCR5_RESERVED_7_DEFVAL 0x09090909 -#define DDR_PHY_DX4GCR5_RESERVED_7_SHIFT 7 -#define DDR_PHY_DX4GCR5_RESERVED_7_MASK 0x00000080U +#define DDR_PHY_DX4GCR5_RESERVED_7_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR5_RESERVED_7_SHIFT 7 +#define DDR_PHY_DX4GCR5_RESERVED_7_MASK 0x00000080U -/*Byte Lane internal VREF Select for Rank 0*/ +/* +* Byte Lane internal VREF Select for Rank 0 +*/ #undef DDR_PHY_DX4GCR5_DXREFISELR0_DEFVAL #undef DDR_PHY_DX4GCR5_DXREFISELR0_SHIFT #undef DDR_PHY_DX4GCR5_DXREFISELR0_MASK -#define DDR_PHY_DX4GCR5_DXREFISELR0_DEFVAL 0x09090909 -#define DDR_PHY_DX4GCR5_DXREFISELR0_SHIFT 0 -#define DDR_PHY_DX4GCR5_DXREFISELR0_MASK 0x0000007FU +#define DDR_PHY_DX4GCR5_DXREFISELR0_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR5_DXREFISELR0_SHIFT 0 +#define DDR_PHY_DX4GCR5_DXREFISELR0_MASK 0x0000007FU -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX4GCR6_RESERVED_31_30_DEFVAL #undef DDR_PHY_DX4GCR6_RESERVED_31_30_SHIFT #undef DDR_PHY_DX4GCR6_RESERVED_31_30_MASK -#define DDR_PHY_DX4GCR6_RESERVED_31_30_DEFVAL 0x09090909 -#define DDR_PHY_DX4GCR6_RESERVED_31_30_SHIFT 30 -#define DDR_PHY_DX4GCR6_RESERVED_31_30_MASK 0xC0000000U +#define DDR_PHY_DX4GCR6_RESERVED_31_30_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR6_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX4GCR6_RESERVED_31_30_MASK 0xC0000000U -/*DRAM DQ VREF Select for Rank3*/ +/* +* DRAM DQ VREF Select for Rank3 +*/ #undef DDR_PHY_DX4GCR6_DXDQVREFR3_DEFVAL #undef DDR_PHY_DX4GCR6_DXDQVREFR3_SHIFT #undef DDR_PHY_DX4GCR6_DXDQVREFR3_MASK -#define DDR_PHY_DX4GCR6_DXDQVREFR3_DEFVAL 0x09090909 -#define DDR_PHY_DX4GCR6_DXDQVREFR3_SHIFT 24 -#define DDR_PHY_DX4GCR6_DXDQVREFR3_MASK 0x3F000000U +#define DDR_PHY_DX4GCR6_DXDQVREFR3_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR6_DXDQVREFR3_SHIFT 24 +#define DDR_PHY_DX4GCR6_DXDQVREFR3_MASK 0x3F000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX4GCR6_RESERVED_23_22_DEFVAL #undef DDR_PHY_DX4GCR6_RESERVED_23_22_SHIFT #undef DDR_PHY_DX4GCR6_RESERVED_23_22_MASK -#define DDR_PHY_DX4GCR6_RESERVED_23_22_DEFVAL 0x09090909 -#define DDR_PHY_DX4GCR6_RESERVED_23_22_SHIFT 22 -#define DDR_PHY_DX4GCR6_RESERVED_23_22_MASK 0x00C00000U +#define DDR_PHY_DX4GCR6_RESERVED_23_22_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR6_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX4GCR6_RESERVED_23_22_MASK 0x00C00000U -/*DRAM DQ VREF Select for Rank2*/ +/* +* DRAM DQ VREF Select for Rank2 +*/ #undef DDR_PHY_DX4GCR6_DXDQVREFR2_DEFVAL #undef DDR_PHY_DX4GCR6_DXDQVREFR2_SHIFT #undef DDR_PHY_DX4GCR6_DXDQVREFR2_MASK -#define DDR_PHY_DX4GCR6_DXDQVREFR2_DEFVAL 0x09090909 -#define DDR_PHY_DX4GCR6_DXDQVREFR2_SHIFT 16 -#define DDR_PHY_DX4GCR6_DXDQVREFR2_MASK 0x003F0000U +#define DDR_PHY_DX4GCR6_DXDQVREFR2_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR6_DXDQVREFR2_SHIFT 16 +#define DDR_PHY_DX4GCR6_DXDQVREFR2_MASK 0x003F0000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX4GCR6_RESERVED_15_14_DEFVAL #undef DDR_PHY_DX4GCR6_RESERVED_15_14_SHIFT #undef DDR_PHY_DX4GCR6_RESERVED_15_14_MASK -#define DDR_PHY_DX4GCR6_RESERVED_15_14_DEFVAL 0x09090909 -#define DDR_PHY_DX4GCR6_RESERVED_15_14_SHIFT 14 -#define DDR_PHY_DX4GCR6_RESERVED_15_14_MASK 0x0000C000U +#define DDR_PHY_DX4GCR6_RESERVED_15_14_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR6_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_DX4GCR6_RESERVED_15_14_MASK 0x0000C000U -/*DRAM DQ VREF Select for Rank1*/ +/* +* DRAM DQ VREF Select for Rank1 +*/ #undef DDR_PHY_DX4GCR6_DXDQVREFR1_DEFVAL #undef DDR_PHY_DX4GCR6_DXDQVREFR1_SHIFT #undef DDR_PHY_DX4GCR6_DXDQVREFR1_MASK -#define DDR_PHY_DX4GCR6_DXDQVREFR1_DEFVAL 0x09090909 -#define DDR_PHY_DX4GCR6_DXDQVREFR1_SHIFT 8 -#define DDR_PHY_DX4GCR6_DXDQVREFR1_MASK 0x00003F00U +#define DDR_PHY_DX4GCR6_DXDQVREFR1_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR6_DXDQVREFR1_SHIFT 8 +#define DDR_PHY_DX4GCR6_DXDQVREFR1_MASK 0x00003F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX4GCR6_RESERVED_7_6_DEFVAL #undef DDR_PHY_DX4GCR6_RESERVED_7_6_SHIFT #undef DDR_PHY_DX4GCR6_RESERVED_7_6_MASK -#define DDR_PHY_DX4GCR6_RESERVED_7_6_DEFVAL 0x09090909 -#define DDR_PHY_DX4GCR6_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_DX4GCR6_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_DX4GCR6_RESERVED_7_6_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR6_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX4GCR6_RESERVED_7_6_MASK 0x000000C0U -/*DRAM DQ VREF Select for Rank0*/ +/* +* DRAM DQ VREF Select for Rank0 +*/ #undef DDR_PHY_DX4GCR6_DXDQVREFR0_DEFVAL #undef DDR_PHY_DX4GCR6_DXDQVREFR0_SHIFT #undef DDR_PHY_DX4GCR6_DXDQVREFR0_MASK -#define DDR_PHY_DX4GCR6_DXDQVREFR0_DEFVAL 0x09090909 -#define DDR_PHY_DX4GCR6_DXDQVREFR0_SHIFT 0 -#define DDR_PHY_DX4GCR6_DXDQVREFR0_MASK 0x0000003FU +#define DDR_PHY_DX4GCR6_DXDQVREFR0_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR6_DXDQVREFR0_SHIFT 0 +#define DDR_PHY_DX4GCR6_DXDQVREFR0_MASK 0x0000003FU -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX4LCDLR2_RESERVED_31_25_DEFVAL -#undef DDR_PHY_DX4LCDLR2_RESERVED_31_25_SHIFT -#undef DDR_PHY_DX4LCDLR2_RESERVED_31_25_MASK -#define DDR_PHY_DX4LCDLR2_RESERVED_31_25_DEFVAL 0x00000000 -#define DDR_PHY_DX4LCDLR2_RESERVED_31_25_SHIFT 25 -#define DDR_PHY_DX4LCDLR2_RESERVED_31_25_MASK 0xFE000000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX4LCDLR2_RESERVED_24_16_DEFVAL -#undef DDR_PHY_DX4LCDLR2_RESERVED_24_16_SHIFT -#undef DDR_PHY_DX4LCDLR2_RESERVED_24_16_MASK -#define DDR_PHY_DX4LCDLR2_RESERVED_24_16_DEFVAL 0x00000000 -#define DDR_PHY_DX4LCDLR2_RESERVED_24_16_SHIFT 16 -#define DDR_PHY_DX4LCDLR2_RESERVED_24_16_MASK 0x01FF0000U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX4LCDLR2_RESERVED_15_9_DEFVAL -#undef DDR_PHY_DX4LCDLR2_RESERVED_15_9_SHIFT -#undef DDR_PHY_DX4LCDLR2_RESERVED_15_9_MASK -#define DDR_PHY_DX4LCDLR2_RESERVED_15_9_DEFVAL 0x00000000 -#define DDR_PHY_DX4LCDLR2_RESERVED_15_9_SHIFT 9 -#define DDR_PHY_DX4LCDLR2_RESERVED_15_9_MASK 0x0000FE00U - -/*Read DQS Gating Delay*/ -#undef DDR_PHY_DX4LCDLR2_DQSGD_DEFVAL -#undef DDR_PHY_DX4LCDLR2_DQSGD_SHIFT -#undef DDR_PHY_DX4LCDLR2_DQSGD_MASK -#define DDR_PHY_DX4LCDLR2_DQSGD_DEFVAL 0x00000000 -#define DDR_PHY_DX4LCDLR2_DQSGD_SHIFT 0 -#define DDR_PHY_DX4LCDLR2_DQSGD_MASK 0x000001FFU - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX4GTR0_RESERVED_31_24_DEFVAL -#undef DDR_PHY_DX4GTR0_RESERVED_31_24_SHIFT -#undef DDR_PHY_DX4GTR0_RESERVED_31_24_MASK -#define DDR_PHY_DX4GTR0_RESERVED_31_24_DEFVAL 0x00020000 -#define DDR_PHY_DX4GTR0_RESERVED_31_24_SHIFT 27 -#define DDR_PHY_DX4GTR0_RESERVED_31_24_MASK 0xF8000000U - -/*DQ Write Path Latency Pipeline*/ -#undef DDR_PHY_DX4GTR0_WDQSL_DEFVAL -#undef DDR_PHY_DX4GTR0_WDQSL_SHIFT -#undef DDR_PHY_DX4GTR0_WDQSL_MASK -#define DDR_PHY_DX4GTR0_WDQSL_DEFVAL 0x00020000 -#define DDR_PHY_DX4GTR0_WDQSL_SHIFT 24 -#define DDR_PHY_DX4GTR0_WDQSL_MASK 0x07000000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX4GTR0_RESERVED_23_20_DEFVAL -#undef DDR_PHY_DX4GTR0_RESERVED_23_20_SHIFT -#undef DDR_PHY_DX4GTR0_RESERVED_23_20_MASK -#define DDR_PHY_DX4GTR0_RESERVED_23_20_DEFVAL 0x00020000 -#define DDR_PHY_DX4GTR0_RESERVED_23_20_SHIFT 20 -#define DDR_PHY_DX4GTR0_RESERVED_23_20_MASK 0x00F00000U - -/*Write Leveling System Latency*/ -#undef DDR_PHY_DX4GTR0_WLSL_DEFVAL -#undef DDR_PHY_DX4GTR0_WLSL_SHIFT -#undef DDR_PHY_DX4GTR0_WLSL_MASK -#define DDR_PHY_DX4GTR0_WLSL_DEFVAL 0x00020000 -#define DDR_PHY_DX4GTR0_WLSL_SHIFT 16 -#define DDR_PHY_DX4GTR0_WLSL_MASK 0x000F0000U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX4GTR0_RESERVED_15_13_DEFVAL -#undef DDR_PHY_DX4GTR0_RESERVED_15_13_SHIFT -#undef DDR_PHY_DX4GTR0_RESERVED_15_13_MASK -#define DDR_PHY_DX4GTR0_RESERVED_15_13_DEFVAL 0x00020000 -#define DDR_PHY_DX4GTR0_RESERVED_15_13_SHIFT 13 -#define DDR_PHY_DX4GTR0_RESERVED_15_13_MASK 0x0000E000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX4GTR0_RESERVED_12_8_DEFVAL -#undef DDR_PHY_DX4GTR0_RESERVED_12_8_SHIFT -#undef DDR_PHY_DX4GTR0_RESERVED_12_8_MASK -#define DDR_PHY_DX4GTR0_RESERVED_12_8_DEFVAL 0x00020000 -#define DDR_PHY_DX4GTR0_RESERVED_12_8_SHIFT 8 -#define DDR_PHY_DX4GTR0_RESERVED_12_8_MASK 0x00001F00U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX4GTR0_RESERVED_7_5_DEFVAL -#undef DDR_PHY_DX4GTR0_RESERVED_7_5_SHIFT -#undef DDR_PHY_DX4GTR0_RESERVED_7_5_MASK -#define DDR_PHY_DX4GTR0_RESERVED_7_5_DEFVAL 0x00020000 -#define DDR_PHY_DX4GTR0_RESERVED_7_5_SHIFT 5 -#define DDR_PHY_DX4GTR0_RESERVED_7_5_MASK 0x000000E0U - -/*DQS Gating System Latency*/ -#undef DDR_PHY_DX4GTR0_DGSL_DEFVAL -#undef DDR_PHY_DX4GTR0_DGSL_SHIFT -#undef DDR_PHY_DX4GTR0_DGSL_MASK -#define DDR_PHY_DX4GTR0_DGSL_DEFVAL 0x00020000 -#define DDR_PHY_DX4GTR0_DGSL_SHIFT 0 -#define DDR_PHY_DX4GTR0_DGSL_MASK 0x0000001FU - -/*Calibration Bypass*/ +/* +* Calibration Bypass +*/ #undef DDR_PHY_DX5GCR0_CALBYP_DEFVAL #undef DDR_PHY_DX5GCR0_CALBYP_SHIFT #undef DDR_PHY_DX5GCR0_CALBYP_MASK -#define DDR_PHY_DX5GCR0_CALBYP_DEFVAL 0x40200204 -#define DDR_PHY_DX5GCR0_CALBYP_SHIFT 31 -#define DDR_PHY_DX5GCR0_CALBYP_MASK 0x80000000U +#define DDR_PHY_DX5GCR0_CALBYP_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_CALBYP_SHIFT 31 +#define DDR_PHY_DX5GCR0_CALBYP_MASK 0x80000000U -/*Master Delay Line Enable*/ +/* +* Master Delay Line Enable +*/ #undef DDR_PHY_DX5GCR0_MDLEN_DEFVAL #undef DDR_PHY_DX5GCR0_MDLEN_SHIFT #undef DDR_PHY_DX5GCR0_MDLEN_MASK -#define DDR_PHY_DX5GCR0_MDLEN_DEFVAL 0x40200204 -#define DDR_PHY_DX5GCR0_MDLEN_SHIFT 30 -#define DDR_PHY_DX5GCR0_MDLEN_MASK 0x40000000U +#define DDR_PHY_DX5GCR0_MDLEN_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_MDLEN_SHIFT 30 +#define DDR_PHY_DX5GCR0_MDLEN_MASK 0x40000000U -/*Configurable ODT(TE) Phase Shift*/ +/* +* Configurable ODT(TE) Phase Shift +*/ #undef DDR_PHY_DX5GCR0_CODTSHFT_DEFVAL #undef DDR_PHY_DX5GCR0_CODTSHFT_SHIFT #undef DDR_PHY_DX5GCR0_CODTSHFT_MASK -#define DDR_PHY_DX5GCR0_CODTSHFT_DEFVAL 0x40200204 -#define DDR_PHY_DX5GCR0_CODTSHFT_SHIFT 28 -#define DDR_PHY_DX5GCR0_CODTSHFT_MASK 0x30000000U +#define DDR_PHY_DX5GCR0_CODTSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_CODTSHFT_SHIFT 28 +#define DDR_PHY_DX5GCR0_CODTSHFT_MASK 0x30000000U -/*DQS Duty Cycle Correction*/ +/* +* DQS Duty Cycle Correction +*/ #undef DDR_PHY_DX5GCR0_DQSDCC_DEFVAL #undef DDR_PHY_DX5GCR0_DQSDCC_SHIFT #undef DDR_PHY_DX5GCR0_DQSDCC_MASK -#define DDR_PHY_DX5GCR0_DQSDCC_DEFVAL 0x40200204 -#define DDR_PHY_DX5GCR0_DQSDCC_SHIFT 24 -#define DDR_PHY_DX5GCR0_DQSDCC_MASK 0x0F000000U +#define DDR_PHY_DX5GCR0_DQSDCC_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_DQSDCC_SHIFT 24 +#define DDR_PHY_DX5GCR0_DQSDCC_MASK 0x0F000000U -/*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/ +/* +* Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY +*/ #undef DDR_PHY_DX5GCR0_RDDLY_DEFVAL #undef DDR_PHY_DX5GCR0_RDDLY_SHIFT #undef DDR_PHY_DX5GCR0_RDDLY_MASK -#define DDR_PHY_DX5GCR0_RDDLY_DEFVAL 0x40200204 -#define DDR_PHY_DX5GCR0_RDDLY_SHIFT 20 -#define DDR_PHY_DX5GCR0_RDDLY_MASK 0x00F00000U +#define DDR_PHY_DX5GCR0_RDDLY_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_RDDLY_SHIFT 20 +#define DDR_PHY_DX5GCR0_RDDLY_MASK 0x00F00000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX5GCR0_RESERVED_19_14_DEFVAL #undef DDR_PHY_DX5GCR0_RESERVED_19_14_SHIFT #undef DDR_PHY_DX5GCR0_RESERVED_19_14_MASK -#define DDR_PHY_DX5GCR0_RESERVED_19_14_DEFVAL 0x40200204 -#define DDR_PHY_DX5GCR0_RESERVED_19_14_SHIFT 14 -#define DDR_PHY_DX5GCR0_RESERVED_19_14_MASK 0x000FC000U +#define DDR_PHY_DX5GCR0_RESERVED_19_14_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_RESERVED_19_14_SHIFT 14 +#define DDR_PHY_DX5GCR0_RESERVED_19_14_MASK 0x000FC000U -/*DQSNSE Power Down Receiver*/ +/* +* DQSNSE Power Down Receiver +*/ #undef DDR_PHY_DX5GCR0_DQSNSEPDR_DEFVAL #undef DDR_PHY_DX5GCR0_DQSNSEPDR_SHIFT #undef DDR_PHY_DX5GCR0_DQSNSEPDR_MASK -#define DDR_PHY_DX5GCR0_DQSNSEPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX5GCR0_DQSNSEPDR_SHIFT 13 -#define DDR_PHY_DX5GCR0_DQSNSEPDR_MASK 0x00002000U +#define DDR_PHY_DX5GCR0_DQSNSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_DQSNSEPDR_SHIFT 13 +#define DDR_PHY_DX5GCR0_DQSNSEPDR_MASK 0x00002000U -/*DQSSE Power Down Receiver*/ +/* +* DQSSE Power Down Receiver +*/ #undef DDR_PHY_DX5GCR0_DQSSEPDR_DEFVAL #undef DDR_PHY_DX5GCR0_DQSSEPDR_SHIFT #undef DDR_PHY_DX5GCR0_DQSSEPDR_MASK -#define DDR_PHY_DX5GCR0_DQSSEPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX5GCR0_DQSSEPDR_SHIFT 12 -#define DDR_PHY_DX5GCR0_DQSSEPDR_MASK 0x00001000U +#define DDR_PHY_DX5GCR0_DQSSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_DQSSEPDR_SHIFT 12 +#define DDR_PHY_DX5GCR0_DQSSEPDR_MASK 0x00001000U -/*RTT On Additive Latency*/ +/* +* RTT On Additive Latency +*/ #undef DDR_PHY_DX5GCR0_RTTOAL_DEFVAL #undef DDR_PHY_DX5GCR0_RTTOAL_SHIFT #undef DDR_PHY_DX5GCR0_RTTOAL_MASK -#define DDR_PHY_DX5GCR0_RTTOAL_DEFVAL 0x40200204 -#define DDR_PHY_DX5GCR0_RTTOAL_SHIFT 11 -#define DDR_PHY_DX5GCR0_RTTOAL_MASK 0x00000800U +#define DDR_PHY_DX5GCR0_RTTOAL_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_RTTOAL_SHIFT 11 +#define DDR_PHY_DX5GCR0_RTTOAL_MASK 0x00000800U -/*RTT Output Hold*/ +/* +* RTT Output Hold +*/ #undef DDR_PHY_DX5GCR0_RTTOH_DEFVAL #undef DDR_PHY_DX5GCR0_RTTOH_SHIFT #undef DDR_PHY_DX5GCR0_RTTOH_MASK -#define DDR_PHY_DX5GCR0_RTTOH_DEFVAL 0x40200204 -#define DDR_PHY_DX5GCR0_RTTOH_SHIFT 9 -#define DDR_PHY_DX5GCR0_RTTOH_MASK 0x00000600U +#define DDR_PHY_DX5GCR0_RTTOH_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_RTTOH_SHIFT 9 +#define DDR_PHY_DX5GCR0_RTTOH_MASK 0x00000600U -/*Configurable PDR Phase Shift*/ +/* +* Configurable PDR Phase Shift +*/ #undef DDR_PHY_DX5GCR0_CPDRSHFT_DEFVAL #undef DDR_PHY_DX5GCR0_CPDRSHFT_SHIFT #undef DDR_PHY_DX5GCR0_CPDRSHFT_MASK -#define DDR_PHY_DX5GCR0_CPDRSHFT_DEFVAL 0x40200204 -#define DDR_PHY_DX5GCR0_CPDRSHFT_SHIFT 7 -#define DDR_PHY_DX5GCR0_CPDRSHFT_MASK 0x00000180U +#define DDR_PHY_DX5GCR0_CPDRSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_CPDRSHFT_SHIFT 7 +#define DDR_PHY_DX5GCR0_CPDRSHFT_MASK 0x00000180U -/*DQSR Power Down*/ +/* +* DQSR Power Down +*/ #undef DDR_PHY_DX5GCR0_DQSRPD_DEFVAL #undef DDR_PHY_DX5GCR0_DQSRPD_SHIFT #undef DDR_PHY_DX5GCR0_DQSRPD_MASK -#define DDR_PHY_DX5GCR0_DQSRPD_DEFVAL 0x40200204 -#define DDR_PHY_DX5GCR0_DQSRPD_SHIFT 6 -#define DDR_PHY_DX5GCR0_DQSRPD_MASK 0x00000040U +#define DDR_PHY_DX5GCR0_DQSRPD_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_DQSRPD_SHIFT 6 +#define DDR_PHY_DX5GCR0_DQSRPD_MASK 0x00000040U -/*DQSG Power Down Receiver*/ +/* +* DQSG Power Down Receiver +*/ #undef DDR_PHY_DX5GCR0_DQSGPDR_DEFVAL #undef DDR_PHY_DX5GCR0_DQSGPDR_SHIFT #undef DDR_PHY_DX5GCR0_DQSGPDR_MASK -#define DDR_PHY_DX5GCR0_DQSGPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX5GCR0_DQSGPDR_SHIFT 5 -#define DDR_PHY_DX5GCR0_DQSGPDR_MASK 0x00000020U +#define DDR_PHY_DX5GCR0_DQSGPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_DQSGPDR_SHIFT 5 +#define DDR_PHY_DX5GCR0_DQSGPDR_MASK 0x00000020U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX5GCR0_RESERVED_4_DEFVAL #undef DDR_PHY_DX5GCR0_RESERVED_4_SHIFT #undef DDR_PHY_DX5GCR0_RESERVED_4_MASK -#define DDR_PHY_DX5GCR0_RESERVED_4_DEFVAL 0x40200204 -#define DDR_PHY_DX5GCR0_RESERVED_4_SHIFT 4 -#define DDR_PHY_DX5GCR0_RESERVED_4_MASK 0x00000010U +#define DDR_PHY_DX5GCR0_RESERVED_4_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_RESERVED_4_SHIFT 4 +#define DDR_PHY_DX5GCR0_RESERVED_4_MASK 0x00000010U -/*DQSG On-Die Termination*/ +/* +* DQSG On-Die Termination +*/ #undef DDR_PHY_DX5GCR0_DQSGODT_DEFVAL #undef DDR_PHY_DX5GCR0_DQSGODT_SHIFT #undef DDR_PHY_DX5GCR0_DQSGODT_MASK -#define DDR_PHY_DX5GCR0_DQSGODT_DEFVAL 0x40200204 -#define DDR_PHY_DX5GCR0_DQSGODT_SHIFT 3 -#define DDR_PHY_DX5GCR0_DQSGODT_MASK 0x00000008U +#define DDR_PHY_DX5GCR0_DQSGODT_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_DQSGODT_SHIFT 3 +#define DDR_PHY_DX5GCR0_DQSGODT_MASK 0x00000008U -/*DQSG Output Enable*/ +/* +* DQSG Output Enable +*/ #undef DDR_PHY_DX5GCR0_DQSGOE_DEFVAL #undef DDR_PHY_DX5GCR0_DQSGOE_SHIFT #undef DDR_PHY_DX5GCR0_DQSGOE_MASK -#define DDR_PHY_DX5GCR0_DQSGOE_DEFVAL 0x40200204 -#define DDR_PHY_DX5GCR0_DQSGOE_SHIFT 2 -#define DDR_PHY_DX5GCR0_DQSGOE_MASK 0x00000004U +#define DDR_PHY_DX5GCR0_DQSGOE_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_DQSGOE_SHIFT 2 +#define DDR_PHY_DX5GCR0_DQSGOE_MASK 0x00000004U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX5GCR0_RESERVED_1_0_DEFVAL #undef DDR_PHY_DX5GCR0_RESERVED_1_0_SHIFT #undef DDR_PHY_DX5GCR0_RESERVED_1_0_MASK -#define DDR_PHY_DX5GCR0_RESERVED_1_0_DEFVAL 0x40200204 -#define DDR_PHY_DX5GCR0_RESERVED_1_0_SHIFT 0 -#define DDR_PHY_DX5GCR0_RESERVED_1_0_MASK 0x00000003U +#define DDR_PHY_DX5GCR0_RESERVED_1_0_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_RESERVED_1_0_SHIFT 0 +#define DDR_PHY_DX5GCR0_RESERVED_1_0_MASK 0x00000003U -/*Enables the PDR mode for DQ[7:0]*/ +/* +* Enables the PDR mode for DQ[7:0] +*/ #undef DDR_PHY_DX5GCR1_DXPDRMODE_DEFVAL #undef DDR_PHY_DX5GCR1_DXPDRMODE_SHIFT #undef DDR_PHY_DX5GCR1_DXPDRMODE_MASK -#define DDR_PHY_DX5GCR1_DXPDRMODE_DEFVAL 0x00007FFF -#define DDR_PHY_DX5GCR1_DXPDRMODE_SHIFT 16 -#define DDR_PHY_DX5GCR1_DXPDRMODE_MASK 0xFFFF0000U +#define DDR_PHY_DX5GCR1_DXPDRMODE_DEFVAL 0x00007FFF +#define DDR_PHY_DX5GCR1_DXPDRMODE_SHIFT 16 +#define DDR_PHY_DX5GCR1_DXPDRMODE_MASK 0xFFFF0000U -/*Reserved. Returns zeroes on reads.*/ +/* +* Reserved. Returns zeroes on reads. +*/ #undef DDR_PHY_DX5GCR1_RESERVED_15_DEFVAL #undef DDR_PHY_DX5GCR1_RESERVED_15_SHIFT #undef DDR_PHY_DX5GCR1_RESERVED_15_MASK -#define DDR_PHY_DX5GCR1_RESERVED_15_DEFVAL 0x00007FFF -#define DDR_PHY_DX5GCR1_RESERVED_15_SHIFT 15 -#define DDR_PHY_DX5GCR1_RESERVED_15_MASK 0x00008000U +#define DDR_PHY_DX5GCR1_RESERVED_15_DEFVAL 0x00007FFF +#define DDR_PHY_DX5GCR1_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX5GCR1_RESERVED_15_MASK 0x00008000U -/*Select the delayed or non-delayed read data strobe #*/ +/* +* Select the delayed or non-delayed read data strobe # +*/ #undef DDR_PHY_DX5GCR1_QSNSEL_DEFVAL #undef DDR_PHY_DX5GCR1_QSNSEL_SHIFT #undef DDR_PHY_DX5GCR1_QSNSEL_MASK -#define DDR_PHY_DX5GCR1_QSNSEL_DEFVAL 0x00007FFF -#define DDR_PHY_DX5GCR1_QSNSEL_SHIFT 14 -#define DDR_PHY_DX5GCR1_QSNSEL_MASK 0x00004000U +#define DDR_PHY_DX5GCR1_QSNSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX5GCR1_QSNSEL_SHIFT 14 +#define DDR_PHY_DX5GCR1_QSNSEL_MASK 0x00004000U -/*Select the delayed or non-delayed read data strobe*/ +/* +* Select the delayed or non-delayed read data strobe +*/ #undef DDR_PHY_DX5GCR1_QSSEL_DEFVAL #undef DDR_PHY_DX5GCR1_QSSEL_SHIFT #undef DDR_PHY_DX5GCR1_QSSEL_MASK -#define DDR_PHY_DX5GCR1_QSSEL_DEFVAL 0x00007FFF -#define DDR_PHY_DX5GCR1_QSSEL_SHIFT 13 -#define DDR_PHY_DX5GCR1_QSSEL_MASK 0x00002000U +#define DDR_PHY_DX5GCR1_QSSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX5GCR1_QSSEL_SHIFT 13 +#define DDR_PHY_DX5GCR1_QSSEL_MASK 0x00002000U -/*Enables Read Data Strobe in a byte lane*/ +/* +* Enables Read Data Strobe in a byte lane +*/ #undef DDR_PHY_DX5GCR1_OEEN_DEFVAL #undef DDR_PHY_DX5GCR1_OEEN_SHIFT #undef DDR_PHY_DX5GCR1_OEEN_MASK -#define DDR_PHY_DX5GCR1_OEEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX5GCR1_OEEN_SHIFT 12 -#define DDR_PHY_DX5GCR1_OEEN_MASK 0x00001000U +#define DDR_PHY_DX5GCR1_OEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX5GCR1_OEEN_SHIFT 12 +#define DDR_PHY_DX5GCR1_OEEN_MASK 0x00001000U -/*Enables PDR in a byte lane*/ +/* +* Enables PDR in a byte lane +*/ #undef DDR_PHY_DX5GCR1_PDREN_DEFVAL #undef DDR_PHY_DX5GCR1_PDREN_SHIFT #undef DDR_PHY_DX5GCR1_PDREN_MASK -#define DDR_PHY_DX5GCR1_PDREN_DEFVAL 0x00007FFF -#define DDR_PHY_DX5GCR1_PDREN_SHIFT 11 -#define DDR_PHY_DX5GCR1_PDREN_MASK 0x00000800U +#define DDR_PHY_DX5GCR1_PDREN_DEFVAL 0x00007FFF +#define DDR_PHY_DX5GCR1_PDREN_SHIFT 11 +#define DDR_PHY_DX5GCR1_PDREN_MASK 0x00000800U -/*Enables ODT/TE in a byte lane*/ +/* +* Enables ODT/TE in a byte lane +*/ #undef DDR_PHY_DX5GCR1_TEEN_DEFVAL #undef DDR_PHY_DX5GCR1_TEEN_SHIFT #undef DDR_PHY_DX5GCR1_TEEN_MASK -#define DDR_PHY_DX5GCR1_TEEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX5GCR1_TEEN_SHIFT 10 -#define DDR_PHY_DX5GCR1_TEEN_MASK 0x00000400U +#define DDR_PHY_DX5GCR1_TEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX5GCR1_TEEN_SHIFT 10 +#define DDR_PHY_DX5GCR1_TEEN_MASK 0x00000400U -/*Enables Write Data strobe in a byte lane*/ +/* +* Enables Write Data strobe in a byte lane +*/ #undef DDR_PHY_DX5GCR1_DSEN_DEFVAL #undef DDR_PHY_DX5GCR1_DSEN_SHIFT #undef DDR_PHY_DX5GCR1_DSEN_MASK -#define DDR_PHY_DX5GCR1_DSEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX5GCR1_DSEN_SHIFT 9 -#define DDR_PHY_DX5GCR1_DSEN_MASK 0x00000200U +#define DDR_PHY_DX5GCR1_DSEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX5GCR1_DSEN_SHIFT 9 +#define DDR_PHY_DX5GCR1_DSEN_MASK 0x00000200U -/*Enables DM pin in a byte lane*/ +/* +* Enables DM pin in a byte lane +*/ #undef DDR_PHY_DX5GCR1_DMEN_DEFVAL #undef DDR_PHY_DX5GCR1_DMEN_SHIFT #undef DDR_PHY_DX5GCR1_DMEN_MASK -#define DDR_PHY_DX5GCR1_DMEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX5GCR1_DMEN_SHIFT 8 -#define DDR_PHY_DX5GCR1_DMEN_MASK 0x00000100U +#define DDR_PHY_DX5GCR1_DMEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX5GCR1_DMEN_SHIFT 8 +#define DDR_PHY_DX5GCR1_DMEN_MASK 0x00000100U -/*Enables DQ corresponding to each bit in a byte*/ +/* +* Enables DQ corresponding to each bit in a byte +*/ #undef DDR_PHY_DX5GCR1_DQEN_DEFVAL #undef DDR_PHY_DX5GCR1_DQEN_SHIFT #undef DDR_PHY_DX5GCR1_DQEN_MASK -#define DDR_PHY_DX5GCR1_DQEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX5GCR1_DQEN_SHIFT 0 -#define DDR_PHY_DX5GCR1_DQEN_MASK 0x000000FFU +#define DDR_PHY_DX5GCR1_DQEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX5GCR1_DQEN_SHIFT 0 +#define DDR_PHY_DX5GCR1_DQEN_MASK 0x000000FFU -/*Byte lane VREF IOM (Used only by D4MU IOs)*/ +/* +* Byte lane VREF IOM (Used only by D4MU IOs) +*/ #undef DDR_PHY_DX5GCR4_RESERVED_31_29_DEFVAL #undef DDR_PHY_DX5GCR4_RESERVED_31_29_SHIFT #undef DDR_PHY_DX5GCR4_RESERVED_31_29_MASK -#define DDR_PHY_DX5GCR4_RESERVED_31_29_DEFVAL 0x0E00003C -#define DDR_PHY_DX5GCR4_RESERVED_31_29_SHIFT 29 -#define DDR_PHY_DX5GCR4_RESERVED_31_29_MASK 0xE0000000U +#define DDR_PHY_DX5GCR4_RESERVED_31_29_DEFVAL 0x0E00003C +#define DDR_PHY_DX5GCR4_RESERVED_31_29_SHIFT 29 +#define DDR_PHY_DX5GCR4_RESERVED_31_29_MASK 0xE0000000U -/*Byte Lane VREF Pad Enable*/ +/* +* Byte Lane VREF Pad Enable +*/ #undef DDR_PHY_DX5GCR4_DXREFPEN_DEFVAL #undef DDR_PHY_DX5GCR4_DXREFPEN_SHIFT #undef DDR_PHY_DX5GCR4_DXREFPEN_MASK -#define DDR_PHY_DX5GCR4_DXREFPEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX5GCR4_DXREFPEN_SHIFT 28 -#define DDR_PHY_DX5GCR4_DXREFPEN_MASK 0x10000000U +#define DDR_PHY_DX5GCR4_DXREFPEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX5GCR4_DXREFPEN_SHIFT 28 +#define DDR_PHY_DX5GCR4_DXREFPEN_MASK 0x10000000U -/*Byte Lane Internal VREF Enable*/ +/* +* Byte Lane Internal VREF Enable +*/ #undef DDR_PHY_DX5GCR4_DXREFEEN_DEFVAL #undef DDR_PHY_DX5GCR4_DXREFEEN_SHIFT #undef DDR_PHY_DX5GCR4_DXREFEEN_MASK -#define DDR_PHY_DX5GCR4_DXREFEEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX5GCR4_DXREFEEN_SHIFT 26 -#define DDR_PHY_DX5GCR4_DXREFEEN_MASK 0x0C000000U +#define DDR_PHY_DX5GCR4_DXREFEEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX5GCR4_DXREFEEN_SHIFT 26 +#define DDR_PHY_DX5GCR4_DXREFEEN_MASK 0x0C000000U -/*Byte Lane Single-End VREF Enable*/ +/* +* Byte Lane Single-End VREF Enable +*/ #undef DDR_PHY_DX5GCR4_DXREFSEN_DEFVAL #undef DDR_PHY_DX5GCR4_DXREFSEN_SHIFT #undef DDR_PHY_DX5GCR4_DXREFSEN_MASK -#define DDR_PHY_DX5GCR4_DXREFSEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX5GCR4_DXREFSEN_SHIFT 25 -#define DDR_PHY_DX5GCR4_DXREFSEN_MASK 0x02000000U +#define DDR_PHY_DX5GCR4_DXREFSEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX5GCR4_DXREFSEN_SHIFT 25 +#define DDR_PHY_DX5GCR4_DXREFSEN_MASK 0x02000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX5GCR4_RESERVED_24_DEFVAL #undef DDR_PHY_DX5GCR4_RESERVED_24_SHIFT #undef DDR_PHY_DX5GCR4_RESERVED_24_MASK -#define DDR_PHY_DX5GCR4_RESERVED_24_DEFVAL 0x0E00003C -#define DDR_PHY_DX5GCR4_RESERVED_24_SHIFT 24 -#define DDR_PHY_DX5GCR4_RESERVED_24_MASK 0x01000000U +#define DDR_PHY_DX5GCR4_RESERVED_24_DEFVAL 0x0E00003C +#define DDR_PHY_DX5GCR4_RESERVED_24_SHIFT 24 +#define DDR_PHY_DX5GCR4_RESERVED_24_MASK 0x01000000U -/*External VREF generator REFSEL range select*/ +/* +* External VREF generator REFSEL range select +*/ #undef DDR_PHY_DX5GCR4_DXREFESELRANGE_DEFVAL #undef DDR_PHY_DX5GCR4_DXREFESELRANGE_SHIFT #undef DDR_PHY_DX5GCR4_DXREFESELRANGE_MASK -#define DDR_PHY_DX5GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C -#define DDR_PHY_DX5GCR4_DXREFESELRANGE_SHIFT 23 -#define DDR_PHY_DX5GCR4_DXREFESELRANGE_MASK 0x00800000U +#define DDR_PHY_DX5GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX5GCR4_DXREFESELRANGE_SHIFT 23 +#define DDR_PHY_DX5GCR4_DXREFESELRANGE_MASK 0x00800000U -/*Byte Lane External VREF Select*/ +/* +* Byte Lane External VREF Select +*/ #undef DDR_PHY_DX5GCR4_DXREFESEL_DEFVAL #undef DDR_PHY_DX5GCR4_DXREFESEL_SHIFT #undef DDR_PHY_DX5GCR4_DXREFESEL_MASK -#define DDR_PHY_DX5GCR4_DXREFESEL_DEFVAL 0x0E00003C -#define DDR_PHY_DX5GCR4_DXREFESEL_SHIFT 16 -#define DDR_PHY_DX5GCR4_DXREFESEL_MASK 0x007F0000U +#define DDR_PHY_DX5GCR4_DXREFESEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX5GCR4_DXREFESEL_SHIFT 16 +#define DDR_PHY_DX5GCR4_DXREFESEL_MASK 0x007F0000U -/*Single ended VREF generator REFSEL range select*/ +/* +* Single ended VREF generator REFSEL range select +*/ #undef DDR_PHY_DX5GCR4_DXREFSSELRANGE_DEFVAL #undef DDR_PHY_DX5GCR4_DXREFSSELRANGE_SHIFT #undef DDR_PHY_DX5GCR4_DXREFSSELRANGE_MASK -#define DDR_PHY_DX5GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C -#define DDR_PHY_DX5GCR4_DXREFSSELRANGE_SHIFT 15 -#define DDR_PHY_DX5GCR4_DXREFSSELRANGE_MASK 0x00008000U +#define DDR_PHY_DX5GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX5GCR4_DXREFSSELRANGE_SHIFT 15 +#define DDR_PHY_DX5GCR4_DXREFSSELRANGE_MASK 0x00008000U -/*Byte Lane Single-End VREF Select*/ +/* +* Byte Lane Single-End VREF Select +*/ #undef DDR_PHY_DX5GCR4_DXREFSSEL_DEFVAL #undef DDR_PHY_DX5GCR4_DXREFSSEL_SHIFT #undef DDR_PHY_DX5GCR4_DXREFSSEL_MASK -#define DDR_PHY_DX5GCR4_DXREFSSEL_DEFVAL 0x0E00003C -#define DDR_PHY_DX5GCR4_DXREFSSEL_SHIFT 8 -#define DDR_PHY_DX5GCR4_DXREFSSEL_MASK 0x00007F00U +#define DDR_PHY_DX5GCR4_DXREFSSEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX5GCR4_DXREFSSEL_SHIFT 8 +#define DDR_PHY_DX5GCR4_DXREFSSEL_MASK 0x00007F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX5GCR4_RESERVED_7_6_DEFVAL #undef DDR_PHY_DX5GCR4_RESERVED_7_6_SHIFT #undef DDR_PHY_DX5GCR4_RESERVED_7_6_MASK -#define DDR_PHY_DX5GCR4_RESERVED_7_6_DEFVAL 0x0E00003C -#define DDR_PHY_DX5GCR4_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_DX5GCR4_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_DX5GCR4_RESERVED_7_6_DEFVAL 0x0E00003C +#define DDR_PHY_DX5GCR4_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX5GCR4_RESERVED_7_6_MASK 0x000000C0U -/*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/ +/* +* VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. +*/ #undef DDR_PHY_DX5GCR4_DXREFIEN_DEFVAL #undef DDR_PHY_DX5GCR4_DXREFIEN_SHIFT #undef DDR_PHY_DX5GCR4_DXREFIEN_MASK -#define DDR_PHY_DX5GCR4_DXREFIEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX5GCR4_DXREFIEN_SHIFT 2 -#define DDR_PHY_DX5GCR4_DXREFIEN_MASK 0x0000003CU +#define DDR_PHY_DX5GCR4_DXREFIEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX5GCR4_DXREFIEN_SHIFT 2 +#define DDR_PHY_DX5GCR4_DXREFIEN_MASK 0x0000003CU -/*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/ +/* +* VRMON control for DQ IO (Single Ended) buffers of a byte lane. +*/ #undef DDR_PHY_DX5GCR4_DXREFIMON_DEFVAL #undef DDR_PHY_DX5GCR4_DXREFIMON_SHIFT #undef DDR_PHY_DX5GCR4_DXREFIMON_MASK -#define DDR_PHY_DX5GCR4_DXREFIMON_DEFVAL 0x0E00003C -#define DDR_PHY_DX5GCR4_DXREFIMON_SHIFT 0 -#define DDR_PHY_DX5GCR4_DXREFIMON_MASK 0x00000003U +#define DDR_PHY_DX5GCR4_DXREFIMON_DEFVAL 0x0E00003C +#define DDR_PHY_DX5GCR4_DXREFIMON_SHIFT 0 +#define DDR_PHY_DX5GCR4_DXREFIMON_MASK 0x00000003U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX5GCR5_RESERVED_31_DEFVAL #undef DDR_PHY_DX5GCR5_RESERVED_31_SHIFT #undef DDR_PHY_DX5GCR5_RESERVED_31_MASK -#define DDR_PHY_DX5GCR5_RESERVED_31_DEFVAL 0x09090909 -#define DDR_PHY_DX5GCR5_RESERVED_31_SHIFT 31 -#define DDR_PHY_DX5GCR5_RESERVED_31_MASK 0x80000000U +#define DDR_PHY_DX5GCR5_RESERVED_31_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR5_RESERVED_31_SHIFT 31 +#define DDR_PHY_DX5GCR5_RESERVED_31_MASK 0x80000000U -/*Byte Lane internal VREF Select for Rank 3*/ +/* +* Byte Lane internal VREF Select for Rank 3 +*/ #undef DDR_PHY_DX5GCR5_DXREFISELR3_DEFVAL #undef DDR_PHY_DX5GCR5_DXREFISELR3_SHIFT #undef DDR_PHY_DX5GCR5_DXREFISELR3_MASK -#define DDR_PHY_DX5GCR5_DXREFISELR3_DEFVAL 0x09090909 -#define DDR_PHY_DX5GCR5_DXREFISELR3_SHIFT 24 -#define DDR_PHY_DX5GCR5_DXREFISELR3_MASK 0x7F000000U +#define DDR_PHY_DX5GCR5_DXREFISELR3_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR5_DXREFISELR3_SHIFT 24 +#define DDR_PHY_DX5GCR5_DXREFISELR3_MASK 0x7F000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX5GCR5_RESERVED_23_DEFVAL #undef DDR_PHY_DX5GCR5_RESERVED_23_SHIFT #undef DDR_PHY_DX5GCR5_RESERVED_23_MASK -#define DDR_PHY_DX5GCR5_RESERVED_23_DEFVAL 0x09090909 -#define DDR_PHY_DX5GCR5_RESERVED_23_SHIFT 23 -#define DDR_PHY_DX5GCR5_RESERVED_23_MASK 0x00800000U +#define DDR_PHY_DX5GCR5_RESERVED_23_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR5_RESERVED_23_SHIFT 23 +#define DDR_PHY_DX5GCR5_RESERVED_23_MASK 0x00800000U -/*Byte Lane internal VREF Select for Rank 2*/ +/* +* Byte Lane internal VREF Select for Rank 2 +*/ #undef DDR_PHY_DX5GCR5_DXREFISELR2_DEFVAL #undef DDR_PHY_DX5GCR5_DXREFISELR2_SHIFT #undef DDR_PHY_DX5GCR5_DXREFISELR2_MASK -#define DDR_PHY_DX5GCR5_DXREFISELR2_DEFVAL 0x09090909 -#define DDR_PHY_DX5GCR5_DXREFISELR2_SHIFT 16 -#define DDR_PHY_DX5GCR5_DXREFISELR2_MASK 0x007F0000U +#define DDR_PHY_DX5GCR5_DXREFISELR2_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR5_DXREFISELR2_SHIFT 16 +#define DDR_PHY_DX5GCR5_DXREFISELR2_MASK 0x007F0000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX5GCR5_RESERVED_15_DEFVAL #undef DDR_PHY_DX5GCR5_RESERVED_15_SHIFT #undef DDR_PHY_DX5GCR5_RESERVED_15_MASK -#define DDR_PHY_DX5GCR5_RESERVED_15_DEFVAL 0x09090909 -#define DDR_PHY_DX5GCR5_RESERVED_15_SHIFT 15 -#define DDR_PHY_DX5GCR5_RESERVED_15_MASK 0x00008000U +#define DDR_PHY_DX5GCR5_RESERVED_15_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR5_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX5GCR5_RESERVED_15_MASK 0x00008000U -/*Byte Lane internal VREF Select for Rank 1*/ +/* +* Byte Lane internal VREF Select for Rank 1 +*/ #undef DDR_PHY_DX5GCR5_DXREFISELR1_DEFVAL #undef DDR_PHY_DX5GCR5_DXREFISELR1_SHIFT #undef DDR_PHY_DX5GCR5_DXREFISELR1_MASK -#define DDR_PHY_DX5GCR5_DXREFISELR1_DEFVAL 0x09090909 -#define DDR_PHY_DX5GCR5_DXREFISELR1_SHIFT 8 -#define DDR_PHY_DX5GCR5_DXREFISELR1_MASK 0x00007F00U +#define DDR_PHY_DX5GCR5_DXREFISELR1_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR5_DXREFISELR1_SHIFT 8 +#define DDR_PHY_DX5GCR5_DXREFISELR1_MASK 0x00007F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX5GCR5_RESERVED_7_DEFVAL #undef DDR_PHY_DX5GCR5_RESERVED_7_SHIFT #undef DDR_PHY_DX5GCR5_RESERVED_7_MASK -#define DDR_PHY_DX5GCR5_RESERVED_7_DEFVAL 0x09090909 -#define DDR_PHY_DX5GCR5_RESERVED_7_SHIFT 7 -#define DDR_PHY_DX5GCR5_RESERVED_7_MASK 0x00000080U +#define DDR_PHY_DX5GCR5_RESERVED_7_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR5_RESERVED_7_SHIFT 7 +#define DDR_PHY_DX5GCR5_RESERVED_7_MASK 0x00000080U -/*Byte Lane internal VREF Select for Rank 0*/ +/* +* Byte Lane internal VREF Select for Rank 0 +*/ #undef DDR_PHY_DX5GCR5_DXREFISELR0_DEFVAL #undef DDR_PHY_DX5GCR5_DXREFISELR0_SHIFT #undef DDR_PHY_DX5GCR5_DXREFISELR0_MASK -#define DDR_PHY_DX5GCR5_DXREFISELR0_DEFVAL 0x09090909 -#define DDR_PHY_DX5GCR5_DXREFISELR0_SHIFT 0 -#define DDR_PHY_DX5GCR5_DXREFISELR0_MASK 0x0000007FU +#define DDR_PHY_DX5GCR5_DXREFISELR0_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR5_DXREFISELR0_SHIFT 0 +#define DDR_PHY_DX5GCR5_DXREFISELR0_MASK 0x0000007FU -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX5GCR6_RESERVED_31_30_DEFVAL #undef DDR_PHY_DX5GCR6_RESERVED_31_30_SHIFT #undef DDR_PHY_DX5GCR6_RESERVED_31_30_MASK -#define DDR_PHY_DX5GCR6_RESERVED_31_30_DEFVAL 0x09090909 -#define DDR_PHY_DX5GCR6_RESERVED_31_30_SHIFT 30 -#define DDR_PHY_DX5GCR6_RESERVED_31_30_MASK 0xC0000000U +#define DDR_PHY_DX5GCR6_RESERVED_31_30_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR6_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX5GCR6_RESERVED_31_30_MASK 0xC0000000U -/*DRAM DQ VREF Select for Rank3*/ +/* +* DRAM DQ VREF Select for Rank3 +*/ #undef DDR_PHY_DX5GCR6_DXDQVREFR3_DEFVAL #undef DDR_PHY_DX5GCR6_DXDQVREFR3_SHIFT #undef DDR_PHY_DX5GCR6_DXDQVREFR3_MASK -#define DDR_PHY_DX5GCR6_DXDQVREFR3_DEFVAL 0x09090909 -#define DDR_PHY_DX5GCR6_DXDQVREFR3_SHIFT 24 -#define DDR_PHY_DX5GCR6_DXDQVREFR3_MASK 0x3F000000U +#define DDR_PHY_DX5GCR6_DXDQVREFR3_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR6_DXDQVREFR3_SHIFT 24 +#define DDR_PHY_DX5GCR6_DXDQVREFR3_MASK 0x3F000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX5GCR6_RESERVED_23_22_DEFVAL #undef DDR_PHY_DX5GCR6_RESERVED_23_22_SHIFT #undef DDR_PHY_DX5GCR6_RESERVED_23_22_MASK -#define DDR_PHY_DX5GCR6_RESERVED_23_22_DEFVAL 0x09090909 -#define DDR_PHY_DX5GCR6_RESERVED_23_22_SHIFT 22 -#define DDR_PHY_DX5GCR6_RESERVED_23_22_MASK 0x00C00000U +#define DDR_PHY_DX5GCR6_RESERVED_23_22_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR6_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX5GCR6_RESERVED_23_22_MASK 0x00C00000U -/*DRAM DQ VREF Select for Rank2*/ +/* +* DRAM DQ VREF Select for Rank2 +*/ #undef DDR_PHY_DX5GCR6_DXDQVREFR2_DEFVAL #undef DDR_PHY_DX5GCR6_DXDQVREFR2_SHIFT #undef DDR_PHY_DX5GCR6_DXDQVREFR2_MASK -#define DDR_PHY_DX5GCR6_DXDQVREFR2_DEFVAL 0x09090909 -#define DDR_PHY_DX5GCR6_DXDQVREFR2_SHIFT 16 -#define DDR_PHY_DX5GCR6_DXDQVREFR2_MASK 0x003F0000U +#define DDR_PHY_DX5GCR6_DXDQVREFR2_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR6_DXDQVREFR2_SHIFT 16 +#define DDR_PHY_DX5GCR6_DXDQVREFR2_MASK 0x003F0000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX5GCR6_RESERVED_15_14_DEFVAL #undef DDR_PHY_DX5GCR6_RESERVED_15_14_SHIFT #undef DDR_PHY_DX5GCR6_RESERVED_15_14_MASK -#define DDR_PHY_DX5GCR6_RESERVED_15_14_DEFVAL 0x09090909 -#define DDR_PHY_DX5GCR6_RESERVED_15_14_SHIFT 14 -#define DDR_PHY_DX5GCR6_RESERVED_15_14_MASK 0x0000C000U +#define DDR_PHY_DX5GCR6_RESERVED_15_14_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR6_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_DX5GCR6_RESERVED_15_14_MASK 0x0000C000U -/*DRAM DQ VREF Select for Rank1*/ +/* +* DRAM DQ VREF Select for Rank1 +*/ #undef DDR_PHY_DX5GCR6_DXDQVREFR1_DEFVAL #undef DDR_PHY_DX5GCR6_DXDQVREFR1_SHIFT #undef DDR_PHY_DX5GCR6_DXDQVREFR1_MASK -#define DDR_PHY_DX5GCR6_DXDQVREFR1_DEFVAL 0x09090909 -#define DDR_PHY_DX5GCR6_DXDQVREFR1_SHIFT 8 -#define DDR_PHY_DX5GCR6_DXDQVREFR1_MASK 0x00003F00U +#define DDR_PHY_DX5GCR6_DXDQVREFR1_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR6_DXDQVREFR1_SHIFT 8 +#define DDR_PHY_DX5GCR6_DXDQVREFR1_MASK 0x00003F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX5GCR6_RESERVED_7_6_DEFVAL #undef DDR_PHY_DX5GCR6_RESERVED_7_6_SHIFT #undef DDR_PHY_DX5GCR6_RESERVED_7_6_MASK -#define DDR_PHY_DX5GCR6_RESERVED_7_6_DEFVAL 0x09090909 -#define DDR_PHY_DX5GCR6_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_DX5GCR6_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_DX5GCR6_RESERVED_7_6_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR6_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX5GCR6_RESERVED_7_6_MASK 0x000000C0U -/*DRAM DQ VREF Select for Rank0*/ +/* +* DRAM DQ VREF Select for Rank0 +*/ #undef DDR_PHY_DX5GCR6_DXDQVREFR0_DEFVAL #undef DDR_PHY_DX5GCR6_DXDQVREFR0_SHIFT #undef DDR_PHY_DX5GCR6_DXDQVREFR0_MASK -#define DDR_PHY_DX5GCR6_DXDQVREFR0_DEFVAL 0x09090909 -#define DDR_PHY_DX5GCR6_DXDQVREFR0_SHIFT 0 -#define DDR_PHY_DX5GCR6_DXDQVREFR0_MASK 0x0000003FU +#define DDR_PHY_DX5GCR6_DXDQVREFR0_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR6_DXDQVREFR0_SHIFT 0 +#define DDR_PHY_DX5GCR6_DXDQVREFR0_MASK 0x0000003FU -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX5LCDLR2_RESERVED_31_25_DEFVAL -#undef DDR_PHY_DX5LCDLR2_RESERVED_31_25_SHIFT -#undef DDR_PHY_DX5LCDLR2_RESERVED_31_25_MASK -#define DDR_PHY_DX5LCDLR2_RESERVED_31_25_DEFVAL 0x00000000 -#define DDR_PHY_DX5LCDLR2_RESERVED_31_25_SHIFT 25 -#define DDR_PHY_DX5LCDLR2_RESERVED_31_25_MASK 0xFE000000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX5LCDLR2_RESERVED_24_16_DEFVAL -#undef DDR_PHY_DX5LCDLR2_RESERVED_24_16_SHIFT -#undef DDR_PHY_DX5LCDLR2_RESERVED_24_16_MASK -#define DDR_PHY_DX5LCDLR2_RESERVED_24_16_DEFVAL 0x00000000 -#define DDR_PHY_DX5LCDLR2_RESERVED_24_16_SHIFT 16 -#define DDR_PHY_DX5LCDLR2_RESERVED_24_16_MASK 0x01FF0000U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX5LCDLR2_RESERVED_15_9_DEFVAL -#undef DDR_PHY_DX5LCDLR2_RESERVED_15_9_SHIFT -#undef DDR_PHY_DX5LCDLR2_RESERVED_15_9_MASK -#define DDR_PHY_DX5LCDLR2_RESERVED_15_9_DEFVAL 0x00000000 -#define DDR_PHY_DX5LCDLR2_RESERVED_15_9_SHIFT 9 -#define DDR_PHY_DX5LCDLR2_RESERVED_15_9_MASK 0x0000FE00U - -/*Read DQS Gating Delay*/ -#undef DDR_PHY_DX5LCDLR2_DQSGD_DEFVAL -#undef DDR_PHY_DX5LCDLR2_DQSGD_SHIFT -#undef DDR_PHY_DX5LCDLR2_DQSGD_MASK -#define DDR_PHY_DX5LCDLR2_DQSGD_DEFVAL 0x00000000 -#define DDR_PHY_DX5LCDLR2_DQSGD_SHIFT 0 -#define DDR_PHY_DX5LCDLR2_DQSGD_MASK 0x000001FFU - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX5GTR0_RESERVED_31_24_DEFVAL -#undef DDR_PHY_DX5GTR0_RESERVED_31_24_SHIFT -#undef DDR_PHY_DX5GTR0_RESERVED_31_24_MASK -#define DDR_PHY_DX5GTR0_RESERVED_31_24_DEFVAL 0x00020000 -#define DDR_PHY_DX5GTR0_RESERVED_31_24_SHIFT 27 -#define DDR_PHY_DX5GTR0_RESERVED_31_24_MASK 0xF8000000U - -/*DQ Write Path Latency Pipeline*/ -#undef DDR_PHY_DX5GTR0_WDQSL_DEFVAL -#undef DDR_PHY_DX5GTR0_WDQSL_SHIFT -#undef DDR_PHY_DX5GTR0_WDQSL_MASK -#define DDR_PHY_DX5GTR0_WDQSL_DEFVAL 0x00020000 -#define DDR_PHY_DX5GTR0_WDQSL_SHIFT 24 -#define DDR_PHY_DX5GTR0_WDQSL_MASK 0x07000000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX5GTR0_RESERVED_23_20_DEFVAL -#undef DDR_PHY_DX5GTR0_RESERVED_23_20_SHIFT -#undef DDR_PHY_DX5GTR0_RESERVED_23_20_MASK -#define DDR_PHY_DX5GTR0_RESERVED_23_20_DEFVAL 0x00020000 -#define DDR_PHY_DX5GTR0_RESERVED_23_20_SHIFT 20 -#define DDR_PHY_DX5GTR0_RESERVED_23_20_MASK 0x00F00000U - -/*Write Leveling System Latency*/ -#undef DDR_PHY_DX5GTR0_WLSL_DEFVAL -#undef DDR_PHY_DX5GTR0_WLSL_SHIFT -#undef DDR_PHY_DX5GTR0_WLSL_MASK -#define DDR_PHY_DX5GTR0_WLSL_DEFVAL 0x00020000 -#define DDR_PHY_DX5GTR0_WLSL_SHIFT 16 -#define DDR_PHY_DX5GTR0_WLSL_MASK 0x000F0000U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX5GTR0_RESERVED_15_13_DEFVAL -#undef DDR_PHY_DX5GTR0_RESERVED_15_13_SHIFT -#undef DDR_PHY_DX5GTR0_RESERVED_15_13_MASK -#define DDR_PHY_DX5GTR0_RESERVED_15_13_DEFVAL 0x00020000 -#define DDR_PHY_DX5GTR0_RESERVED_15_13_SHIFT 13 -#define DDR_PHY_DX5GTR0_RESERVED_15_13_MASK 0x0000E000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX5GTR0_RESERVED_12_8_DEFVAL -#undef DDR_PHY_DX5GTR0_RESERVED_12_8_SHIFT -#undef DDR_PHY_DX5GTR0_RESERVED_12_8_MASK -#define DDR_PHY_DX5GTR0_RESERVED_12_8_DEFVAL 0x00020000 -#define DDR_PHY_DX5GTR0_RESERVED_12_8_SHIFT 8 -#define DDR_PHY_DX5GTR0_RESERVED_12_8_MASK 0x00001F00U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX5GTR0_RESERVED_7_5_DEFVAL -#undef DDR_PHY_DX5GTR0_RESERVED_7_5_SHIFT -#undef DDR_PHY_DX5GTR0_RESERVED_7_5_MASK -#define DDR_PHY_DX5GTR0_RESERVED_7_5_DEFVAL 0x00020000 -#define DDR_PHY_DX5GTR0_RESERVED_7_5_SHIFT 5 -#define DDR_PHY_DX5GTR0_RESERVED_7_5_MASK 0x000000E0U - -/*DQS Gating System Latency*/ -#undef DDR_PHY_DX5GTR0_DGSL_DEFVAL -#undef DDR_PHY_DX5GTR0_DGSL_SHIFT -#undef DDR_PHY_DX5GTR0_DGSL_MASK -#define DDR_PHY_DX5GTR0_DGSL_DEFVAL 0x00020000 -#define DDR_PHY_DX5GTR0_DGSL_SHIFT 0 -#define DDR_PHY_DX5GTR0_DGSL_MASK 0x0000001FU - -/*Calibration Bypass*/ +/* +* Calibration Bypass +*/ #undef DDR_PHY_DX6GCR0_CALBYP_DEFVAL #undef DDR_PHY_DX6GCR0_CALBYP_SHIFT #undef DDR_PHY_DX6GCR0_CALBYP_MASK -#define DDR_PHY_DX6GCR0_CALBYP_DEFVAL 0x40200204 -#define DDR_PHY_DX6GCR0_CALBYP_SHIFT 31 -#define DDR_PHY_DX6GCR0_CALBYP_MASK 0x80000000U +#define DDR_PHY_DX6GCR0_CALBYP_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_CALBYP_SHIFT 31 +#define DDR_PHY_DX6GCR0_CALBYP_MASK 0x80000000U -/*Master Delay Line Enable*/ +/* +* Master Delay Line Enable +*/ #undef DDR_PHY_DX6GCR0_MDLEN_DEFVAL #undef DDR_PHY_DX6GCR0_MDLEN_SHIFT #undef DDR_PHY_DX6GCR0_MDLEN_MASK -#define DDR_PHY_DX6GCR0_MDLEN_DEFVAL 0x40200204 -#define DDR_PHY_DX6GCR0_MDLEN_SHIFT 30 -#define DDR_PHY_DX6GCR0_MDLEN_MASK 0x40000000U +#define DDR_PHY_DX6GCR0_MDLEN_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_MDLEN_SHIFT 30 +#define DDR_PHY_DX6GCR0_MDLEN_MASK 0x40000000U -/*Configurable ODT(TE) Phase Shift*/ +/* +* Configurable ODT(TE) Phase Shift +*/ #undef DDR_PHY_DX6GCR0_CODTSHFT_DEFVAL #undef DDR_PHY_DX6GCR0_CODTSHFT_SHIFT #undef DDR_PHY_DX6GCR0_CODTSHFT_MASK -#define DDR_PHY_DX6GCR0_CODTSHFT_DEFVAL 0x40200204 -#define DDR_PHY_DX6GCR0_CODTSHFT_SHIFT 28 -#define DDR_PHY_DX6GCR0_CODTSHFT_MASK 0x30000000U +#define DDR_PHY_DX6GCR0_CODTSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_CODTSHFT_SHIFT 28 +#define DDR_PHY_DX6GCR0_CODTSHFT_MASK 0x30000000U -/*DQS Duty Cycle Correction*/ +/* +* DQS Duty Cycle Correction +*/ #undef DDR_PHY_DX6GCR0_DQSDCC_DEFVAL #undef DDR_PHY_DX6GCR0_DQSDCC_SHIFT #undef DDR_PHY_DX6GCR0_DQSDCC_MASK -#define DDR_PHY_DX6GCR0_DQSDCC_DEFVAL 0x40200204 -#define DDR_PHY_DX6GCR0_DQSDCC_SHIFT 24 -#define DDR_PHY_DX6GCR0_DQSDCC_MASK 0x0F000000U +#define DDR_PHY_DX6GCR0_DQSDCC_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_DQSDCC_SHIFT 24 +#define DDR_PHY_DX6GCR0_DQSDCC_MASK 0x0F000000U -/*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/ +/* +* Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY +*/ #undef DDR_PHY_DX6GCR0_RDDLY_DEFVAL #undef DDR_PHY_DX6GCR0_RDDLY_SHIFT #undef DDR_PHY_DX6GCR0_RDDLY_MASK -#define DDR_PHY_DX6GCR0_RDDLY_DEFVAL 0x40200204 -#define DDR_PHY_DX6GCR0_RDDLY_SHIFT 20 -#define DDR_PHY_DX6GCR0_RDDLY_MASK 0x00F00000U +#define DDR_PHY_DX6GCR0_RDDLY_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_RDDLY_SHIFT 20 +#define DDR_PHY_DX6GCR0_RDDLY_MASK 0x00F00000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX6GCR0_RESERVED_19_14_DEFVAL #undef DDR_PHY_DX6GCR0_RESERVED_19_14_SHIFT #undef DDR_PHY_DX6GCR0_RESERVED_19_14_MASK -#define DDR_PHY_DX6GCR0_RESERVED_19_14_DEFVAL 0x40200204 -#define DDR_PHY_DX6GCR0_RESERVED_19_14_SHIFT 14 -#define DDR_PHY_DX6GCR0_RESERVED_19_14_MASK 0x000FC000U +#define DDR_PHY_DX6GCR0_RESERVED_19_14_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_RESERVED_19_14_SHIFT 14 +#define DDR_PHY_DX6GCR0_RESERVED_19_14_MASK 0x000FC000U -/*DQSNSE Power Down Receiver*/ +/* +* DQSNSE Power Down Receiver +*/ #undef DDR_PHY_DX6GCR0_DQSNSEPDR_DEFVAL #undef DDR_PHY_DX6GCR0_DQSNSEPDR_SHIFT #undef DDR_PHY_DX6GCR0_DQSNSEPDR_MASK -#define DDR_PHY_DX6GCR0_DQSNSEPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX6GCR0_DQSNSEPDR_SHIFT 13 -#define DDR_PHY_DX6GCR0_DQSNSEPDR_MASK 0x00002000U +#define DDR_PHY_DX6GCR0_DQSNSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_DQSNSEPDR_SHIFT 13 +#define DDR_PHY_DX6GCR0_DQSNSEPDR_MASK 0x00002000U -/*DQSSE Power Down Receiver*/ +/* +* DQSSE Power Down Receiver +*/ #undef DDR_PHY_DX6GCR0_DQSSEPDR_DEFVAL #undef DDR_PHY_DX6GCR0_DQSSEPDR_SHIFT #undef DDR_PHY_DX6GCR0_DQSSEPDR_MASK -#define DDR_PHY_DX6GCR0_DQSSEPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX6GCR0_DQSSEPDR_SHIFT 12 -#define DDR_PHY_DX6GCR0_DQSSEPDR_MASK 0x00001000U +#define DDR_PHY_DX6GCR0_DQSSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_DQSSEPDR_SHIFT 12 +#define DDR_PHY_DX6GCR0_DQSSEPDR_MASK 0x00001000U -/*RTT On Additive Latency*/ +/* +* RTT On Additive Latency +*/ #undef DDR_PHY_DX6GCR0_RTTOAL_DEFVAL #undef DDR_PHY_DX6GCR0_RTTOAL_SHIFT #undef DDR_PHY_DX6GCR0_RTTOAL_MASK -#define DDR_PHY_DX6GCR0_RTTOAL_DEFVAL 0x40200204 -#define DDR_PHY_DX6GCR0_RTTOAL_SHIFT 11 -#define DDR_PHY_DX6GCR0_RTTOAL_MASK 0x00000800U +#define DDR_PHY_DX6GCR0_RTTOAL_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_RTTOAL_SHIFT 11 +#define DDR_PHY_DX6GCR0_RTTOAL_MASK 0x00000800U -/*RTT Output Hold*/ +/* +* RTT Output Hold +*/ #undef DDR_PHY_DX6GCR0_RTTOH_DEFVAL #undef DDR_PHY_DX6GCR0_RTTOH_SHIFT #undef DDR_PHY_DX6GCR0_RTTOH_MASK -#define DDR_PHY_DX6GCR0_RTTOH_DEFVAL 0x40200204 -#define DDR_PHY_DX6GCR0_RTTOH_SHIFT 9 -#define DDR_PHY_DX6GCR0_RTTOH_MASK 0x00000600U +#define DDR_PHY_DX6GCR0_RTTOH_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_RTTOH_SHIFT 9 +#define DDR_PHY_DX6GCR0_RTTOH_MASK 0x00000600U -/*Configurable PDR Phase Shift*/ +/* +* Configurable PDR Phase Shift +*/ #undef DDR_PHY_DX6GCR0_CPDRSHFT_DEFVAL #undef DDR_PHY_DX6GCR0_CPDRSHFT_SHIFT #undef DDR_PHY_DX6GCR0_CPDRSHFT_MASK -#define DDR_PHY_DX6GCR0_CPDRSHFT_DEFVAL 0x40200204 -#define DDR_PHY_DX6GCR0_CPDRSHFT_SHIFT 7 -#define DDR_PHY_DX6GCR0_CPDRSHFT_MASK 0x00000180U +#define DDR_PHY_DX6GCR0_CPDRSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_CPDRSHFT_SHIFT 7 +#define DDR_PHY_DX6GCR0_CPDRSHFT_MASK 0x00000180U -/*DQSR Power Down*/ +/* +* DQSR Power Down +*/ #undef DDR_PHY_DX6GCR0_DQSRPD_DEFVAL #undef DDR_PHY_DX6GCR0_DQSRPD_SHIFT #undef DDR_PHY_DX6GCR0_DQSRPD_MASK -#define DDR_PHY_DX6GCR0_DQSRPD_DEFVAL 0x40200204 -#define DDR_PHY_DX6GCR0_DQSRPD_SHIFT 6 -#define DDR_PHY_DX6GCR0_DQSRPD_MASK 0x00000040U +#define DDR_PHY_DX6GCR0_DQSRPD_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_DQSRPD_SHIFT 6 +#define DDR_PHY_DX6GCR0_DQSRPD_MASK 0x00000040U -/*DQSG Power Down Receiver*/ +/* +* DQSG Power Down Receiver +*/ #undef DDR_PHY_DX6GCR0_DQSGPDR_DEFVAL #undef DDR_PHY_DX6GCR0_DQSGPDR_SHIFT #undef DDR_PHY_DX6GCR0_DQSGPDR_MASK -#define DDR_PHY_DX6GCR0_DQSGPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX6GCR0_DQSGPDR_SHIFT 5 -#define DDR_PHY_DX6GCR0_DQSGPDR_MASK 0x00000020U +#define DDR_PHY_DX6GCR0_DQSGPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_DQSGPDR_SHIFT 5 +#define DDR_PHY_DX6GCR0_DQSGPDR_MASK 0x00000020U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX6GCR0_RESERVED_4_DEFVAL #undef DDR_PHY_DX6GCR0_RESERVED_4_SHIFT #undef DDR_PHY_DX6GCR0_RESERVED_4_MASK -#define DDR_PHY_DX6GCR0_RESERVED_4_DEFVAL 0x40200204 -#define DDR_PHY_DX6GCR0_RESERVED_4_SHIFT 4 -#define DDR_PHY_DX6GCR0_RESERVED_4_MASK 0x00000010U +#define DDR_PHY_DX6GCR0_RESERVED_4_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_RESERVED_4_SHIFT 4 +#define DDR_PHY_DX6GCR0_RESERVED_4_MASK 0x00000010U -/*DQSG On-Die Termination*/ +/* +* DQSG On-Die Termination +*/ #undef DDR_PHY_DX6GCR0_DQSGODT_DEFVAL #undef DDR_PHY_DX6GCR0_DQSGODT_SHIFT #undef DDR_PHY_DX6GCR0_DQSGODT_MASK -#define DDR_PHY_DX6GCR0_DQSGODT_DEFVAL 0x40200204 -#define DDR_PHY_DX6GCR0_DQSGODT_SHIFT 3 -#define DDR_PHY_DX6GCR0_DQSGODT_MASK 0x00000008U +#define DDR_PHY_DX6GCR0_DQSGODT_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_DQSGODT_SHIFT 3 +#define DDR_PHY_DX6GCR0_DQSGODT_MASK 0x00000008U -/*DQSG Output Enable*/ +/* +* DQSG Output Enable +*/ #undef DDR_PHY_DX6GCR0_DQSGOE_DEFVAL #undef DDR_PHY_DX6GCR0_DQSGOE_SHIFT #undef DDR_PHY_DX6GCR0_DQSGOE_MASK -#define DDR_PHY_DX6GCR0_DQSGOE_DEFVAL 0x40200204 -#define DDR_PHY_DX6GCR0_DQSGOE_SHIFT 2 -#define DDR_PHY_DX6GCR0_DQSGOE_MASK 0x00000004U +#define DDR_PHY_DX6GCR0_DQSGOE_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_DQSGOE_SHIFT 2 +#define DDR_PHY_DX6GCR0_DQSGOE_MASK 0x00000004U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX6GCR0_RESERVED_1_0_DEFVAL #undef DDR_PHY_DX6GCR0_RESERVED_1_0_SHIFT #undef DDR_PHY_DX6GCR0_RESERVED_1_0_MASK -#define DDR_PHY_DX6GCR0_RESERVED_1_0_DEFVAL 0x40200204 -#define DDR_PHY_DX6GCR0_RESERVED_1_0_SHIFT 0 -#define DDR_PHY_DX6GCR0_RESERVED_1_0_MASK 0x00000003U +#define DDR_PHY_DX6GCR0_RESERVED_1_0_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_RESERVED_1_0_SHIFT 0 +#define DDR_PHY_DX6GCR0_RESERVED_1_0_MASK 0x00000003U -/*Enables the PDR mode for DQ[7:0]*/ +/* +* Enables the PDR mode for DQ[7:0] +*/ #undef DDR_PHY_DX6GCR1_DXPDRMODE_DEFVAL #undef DDR_PHY_DX6GCR1_DXPDRMODE_SHIFT #undef DDR_PHY_DX6GCR1_DXPDRMODE_MASK -#define DDR_PHY_DX6GCR1_DXPDRMODE_DEFVAL 0x00007FFF -#define DDR_PHY_DX6GCR1_DXPDRMODE_SHIFT 16 -#define DDR_PHY_DX6GCR1_DXPDRMODE_MASK 0xFFFF0000U +#define DDR_PHY_DX6GCR1_DXPDRMODE_DEFVAL 0x00007FFF +#define DDR_PHY_DX6GCR1_DXPDRMODE_SHIFT 16 +#define DDR_PHY_DX6GCR1_DXPDRMODE_MASK 0xFFFF0000U -/*Reserved. Returns zeroes on reads.*/ +/* +* Reserved. Returns zeroes on reads. +*/ #undef DDR_PHY_DX6GCR1_RESERVED_15_DEFVAL #undef DDR_PHY_DX6GCR1_RESERVED_15_SHIFT #undef DDR_PHY_DX6GCR1_RESERVED_15_MASK -#define DDR_PHY_DX6GCR1_RESERVED_15_DEFVAL 0x00007FFF -#define DDR_PHY_DX6GCR1_RESERVED_15_SHIFT 15 -#define DDR_PHY_DX6GCR1_RESERVED_15_MASK 0x00008000U +#define DDR_PHY_DX6GCR1_RESERVED_15_DEFVAL 0x00007FFF +#define DDR_PHY_DX6GCR1_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX6GCR1_RESERVED_15_MASK 0x00008000U -/*Select the delayed or non-delayed read data strobe #*/ +/* +* Select the delayed or non-delayed read data strobe # +*/ #undef DDR_PHY_DX6GCR1_QSNSEL_DEFVAL #undef DDR_PHY_DX6GCR1_QSNSEL_SHIFT #undef DDR_PHY_DX6GCR1_QSNSEL_MASK -#define DDR_PHY_DX6GCR1_QSNSEL_DEFVAL 0x00007FFF -#define DDR_PHY_DX6GCR1_QSNSEL_SHIFT 14 -#define DDR_PHY_DX6GCR1_QSNSEL_MASK 0x00004000U +#define DDR_PHY_DX6GCR1_QSNSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX6GCR1_QSNSEL_SHIFT 14 +#define DDR_PHY_DX6GCR1_QSNSEL_MASK 0x00004000U -/*Select the delayed or non-delayed read data strobe*/ +/* +* Select the delayed or non-delayed read data strobe +*/ #undef DDR_PHY_DX6GCR1_QSSEL_DEFVAL #undef DDR_PHY_DX6GCR1_QSSEL_SHIFT #undef DDR_PHY_DX6GCR1_QSSEL_MASK -#define DDR_PHY_DX6GCR1_QSSEL_DEFVAL 0x00007FFF -#define DDR_PHY_DX6GCR1_QSSEL_SHIFT 13 -#define DDR_PHY_DX6GCR1_QSSEL_MASK 0x00002000U +#define DDR_PHY_DX6GCR1_QSSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX6GCR1_QSSEL_SHIFT 13 +#define DDR_PHY_DX6GCR1_QSSEL_MASK 0x00002000U -/*Enables Read Data Strobe in a byte lane*/ +/* +* Enables Read Data Strobe in a byte lane +*/ #undef DDR_PHY_DX6GCR1_OEEN_DEFVAL #undef DDR_PHY_DX6GCR1_OEEN_SHIFT #undef DDR_PHY_DX6GCR1_OEEN_MASK -#define DDR_PHY_DX6GCR1_OEEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX6GCR1_OEEN_SHIFT 12 -#define DDR_PHY_DX6GCR1_OEEN_MASK 0x00001000U +#define DDR_PHY_DX6GCR1_OEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX6GCR1_OEEN_SHIFT 12 +#define DDR_PHY_DX6GCR1_OEEN_MASK 0x00001000U -/*Enables PDR in a byte lane*/ +/* +* Enables PDR in a byte lane +*/ #undef DDR_PHY_DX6GCR1_PDREN_DEFVAL #undef DDR_PHY_DX6GCR1_PDREN_SHIFT #undef DDR_PHY_DX6GCR1_PDREN_MASK -#define DDR_PHY_DX6GCR1_PDREN_DEFVAL 0x00007FFF -#define DDR_PHY_DX6GCR1_PDREN_SHIFT 11 -#define DDR_PHY_DX6GCR1_PDREN_MASK 0x00000800U +#define DDR_PHY_DX6GCR1_PDREN_DEFVAL 0x00007FFF +#define DDR_PHY_DX6GCR1_PDREN_SHIFT 11 +#define DDR_PHY_DX6GCR1_PDREN_MASK 0x00000800U -/*Enables ODT/TE in a byte lane*/ +/* +* Enables ODT/TE in a byte lane +*/ #undef DDR_PHY_DX6GCR1_TEEN_DEFVAL #undef DDR_PHY_DX6GCR1_TEEN_SHIFT #undef DDR_PHY_DX6GCR1_TEEN_MASK -#define DDR_PHY_DX6GCR1_TEEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX6GCR1_TEEN_SHIFT 10 -#define DDR_PHY_DX6GCR1_TEEN_MASK 0x00000400U +#define DDR_PHY_DX6GCR1_TEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX6GCR1_TEEN_SHIFT 10 +#define DDR_PHY_DX6GCR1_TEEN_MASK 0x00000400U -/*Enables Write Data strobe in a byte lane*/ +/* +* Enables Write Data strobe in a byte lane +*/ #undef DDR_PHY_DX6GCR1_DSEN_DEFVAL #undef DDR_PHY_DX6GCR1_DSEN_SHIFT #undef DDR_PHY_DX6GCR1_DSEN_MASK -#define DDR_PHY_DX6GCR1_DSEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX6GCR1_DSEN_SHIFT 9 -#define DDR_PHY_DX6GCR1_DSEN_MASK 0x00000200U +#define DDR_PHY_DX6GCR1_DSEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX6GCR1_DSEN_SHIFT 9 +#define DDR_PHY_DX6GCR1_DSEN_MASK 0x00000200U -/*Enables DM pin in a byte lane*/ +/* +* Enables DM pin in a byte lane +*/ #undef DDR_PHY_DX6GCR1_DMEN_DEFVAL #undef DDR_PHY_DX6GCR1_DMEN_SHIFT #undef DDR_PHY_DX6GCR1_DMEN_MASK -#define DDR_PHY_DX6GCR1_DMEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX6GCR1_DMEN_SHIFT 8 -#define DDR_PHY_DX6GCR1_DMEN_MASK 0x00000100U +#define DDR_PHY_DX6GCR1_DMEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX6GCR1_DMEN_SHIFT 8 +#define DDR_PHY_DX6GCR1_DMEN_MASK 0x00000100U -/*Enables DQ corresponding to each bit in a byte*/ +/* +* Enables DQ corresponding to each bit in a byte +*/ #undef DDR_PHY_DX6GCR1_DQEN_DEFVAL #undef DDR_PHY_DX6GCR1_DQEN_SHIFT #undef DDR_PHY_DX6GCR1_DQEN_MASK -#define DDR_PHY_DX6GCR1_DQEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX6GCR1_DQEN_SHIFT 0 -#define DDR_PHY_DX6GCR1_DQEN_MASK 0x000000FFU +#define DDR_PHY_DX6GCR1_DQEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX6GCR1_DQEN_SHIFT 0 +#define DDR_PHY_DX6GCR1_DQEN_MASK 0x000000FFU -/*Byte lane VREF IOM (Used only by D4MU IOs)*/ +/* +* Byte lane VREF IOM (Used only by D4MU IOs) +*/ #undef DDR_PHY_DX6GCR4_RESERVED_31_29_DEFVAL #undef DDR_PHY_DX6GCR4_RESERVED_31_29_SHIFT #undef DDR_PHY_DX6GCR4_RESERVED_31_29_MASK -#define DDR_PHY_DX6GCR4_RESERVED_31_29_DEFVAL 0x0E00003C -#define DDR_PHY_DX6GCR4_RESERVED_31_29_SHIFT 29 -#define DDR_PHY_DX6GCR4_RESERVED_31_29_MASK 0xE0000000U +#define DDR_PHY_DX6GCR4_RESERVED_31_29_DEFVAL 0x0E00003C +#define DDR_PHY_DX6GCR4_RESERVED_31_29_SHIFT 29 +#define DDR_PHY_DX6GCR4_RESERVED_31_29_MASK 0xE0000000U -/*Byte Lane VREF Pad Enable*/ +/* +* Byte Lane VREF Pad Enable +*/ #undef DDR_PHY_DX6GCR4_DXREFPEN_DEFVAL #undef DDR_PHY_DX6GCR4_DXREFPEN_SHIFT #undef DDR_PHY_DX6GCR4_DXREFPEN_MASK -#define DDR_PHY_DX6GCR4_DXREFPEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX6GCR4_DXREFPEN_SHIFT 28 -#define DDR_PHY_DX6GCR4_DXREFPEN_MASK 0x10000000U +#define DDR_PHY_DX6GCR4_DXREFPEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX6GCR4_DXREFPEN_SHIFT 28 +#define DDR_PHY_DX6GCR4_DXREFPEN_MASK 0x10000000U -/*Byte Lane Internal VREF Enable*/ +/* +* Byte Lane Internal VREF Enable +*/ #undef DDR_PHY_DX6GCR4_DXREFEEN_DEFVAL #undef DDR_PHY_DX6GCR4_DXREFEEN_SHIFT #undef DDR_PHY_DX6GCR4_DXREFEEN_MASK -#define DDR_PHY_DX6GCR4_DXREFEEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX6GCR4_DXREFEEN_SHIFT 26 -#define DDR_PHY_DX6GCR4_DXREFEEN_MASK 0x0C000000U +#define DDR_PHY_DX6GCR4_DXREFEEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX6GCR4_DXREFEEN_SHIFT 26 +#define DDR_PHY_DX6GCR4_DXREFEEN_MASK 0x0C000000U -/*Byte Lane Single-End VREF Enable*/ +/* +* Byte Lane Single-End VREF Enable +*/ #undef DDR_PHY_DX6GCR4_DXREFSEN_DEFVAL #undef DDR_PHY_DX6GCR4_DXREFSEN_SHIFT #undef DDR_PHY_DX6GCR4_DXREFSEN_MASK -#define DDR_PHY_DX6GCR4_DXREFSEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX6GCR4_DXREFSEN_SHIFT 25 -#define DDR_PHY_DX6GCR4_DXREFSEN_MASK 0x02000000U +#define DDR_PHY_DX6GCR4_DXREFSEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX6GCR4_DXREFSEN_SHIFT 25 +#define DDR_PHY_DX6GCR4_DXREFSEN_MASK 0x02000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX6GCR4_RESERVED_24_DEFVAL #undef DDR_PHY_DX6GCR4_RESERVED_24_SHIFT #undef DDR_PHY_DX6GCR4_RESERVED_24_MASK -#define DDR_PHY_DX6GCR4_RESERVED_24_DEFVAL 0x0E00003C -#define DDR_PHY_DX6GCR4_RESERVED_24_SHIFT 24 -#define DDR_PHY_DX6GCR4_RESERVED_24_MASK 0x01000000U +#define DDR_PHY_DX6GCR4_RESERVED_24_DEFVAL 0x0E00003C +#define DDR_PHY_DX6GCR4_RESERVED_24_SHIFT 24 +#define DDR_PHY_DX6GCR4_RESERVED_24_MASK 0x01000000U -/*External VREF generator REFSEL range select*/ +/* +* External VREF generator REFSEL range select +*/ #undef DDR_PHY_DX6GCR4_DXREFESELRANGE_DEFVAL #undef DDR_PHY_DX6GCR4_DXREFESELRANGE_SHIFT #undef DDR_PHY_DX6GCR4_DXREFESELRANGE_MASK -#define DDR_PHY_DX6GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C -#define DDR_PHY_DX6GCR4_DXREFESELRANGE_SHIFT 23 -#define DDR_PHY_DX6GCR4_DXREFESELRANGE_MASK 0x00800000U +#define DDR_PHY_DX6GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX6GCR4_DXREFESELRANGE_SHIFT 23 +#define DDR_PHY_DX6GCR4_DXREFESELRANGE_MASK 0x00800000U -/*Byte Lane External VREF Select*/ +/* +* Byte Lane External VREF Select +*/ #undef DDR_PHY_DX6GCR4_DXREFESEL_DEFVAL #undef DDR_PHY_DX6GCR4_DXREFESEL_SHIFT #undef DDR_PHY_DX6GCR4_DXREFESEL_MASK -#define DDR_PHY_DX6GCR4_DXREFESEL_DEFVAL 0x0E00003C -#define DDR_PHY_DX6GCR4_DXREFESEL_SHIFT 16 -#define DDR_PHY_DX6GCR4_DXREFESEL_MASK 0x007F0000U +#define DDR_PHY_DX6GCR4_DXREFESEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX6GCR4_DXREFESEL_SHIFT 16 +#define DDR_PHY_DX6GCR4_DXREFESEL_MASK 0x007F0000U -/*Single ended VREF generator REFSEL range select*/ +/* +* Single ended VREF generator REFSEL range select +*/ #undef DDR_PHY_DX6GCR4_DXREFSSELRANGE_DEFVAL #undef DDR_PHY_DX6GCR4_DXREFSSELRANGE_SHIFT #undef DDR_PHY_DX6GCR4_DXREFSSELRANGE_MASK -#define DDR_PHY_DX6GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C -#define DDR_PHY_DX6GCR4_DXREFSSELRANGE_SHIFT 15 -#define DDR_PHY_DX6GCR4_DXREFSSELRANGE_MASK 0x00008000U +#define DDR_PHY_DX6GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX6GCR4_DXREFSSELRANGE_SHIFT 15 +#define DDR_PHY_DX6GCR4_DXREFSSELRANGE_MASK 0x00008000U -/*Byte Lane Single-End VREF Select*/ +/* +* Byte Lane Single-End VREF Select +*/ #undef DDR_PHY_DX6GCR4_DXREFSSEL_DEFVAL #undef DDR_PHY_DX6GCR4_DXREFSSEL_SHIFT #undef DDR_PHY_DX6GCR4_DXREFSSEL_MASK -#define DDR_PHY_DX6GCR4_DXREFSSEL_DEFVAL 0x0E00003C -#define DDR_PHY_DX6GCR4_DXREFSSEL_SHIFT 8 -#define DDR_PHY_DX6GCR4_DXREFSSEL_MASK 0x00007F00U +#define DDR_PHY_DX6GCR4_DXREFSSEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX6GCR4_DXREFSSEL_SHIFT 8 +#define DDR_PHY_DX6GCR4_DXREFSSEL_MASK 0x00007F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX6GCR4_RESERVED_7_6_DEFVAL #undef DDR_PHY_DX6GCR4_RESERVED_7_6_SHIFT #undef DDR_PHY_DX6GCR4_RESERVED_7_6_MASK -#define DDR_PHY_DX6GCR4_RESERVED_7_6_DEFVAL 0x0E00003C -#define DDR_PHY_DX6GCR4_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_DX6GCR4_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_DX6GCR4_RESERVED_7_6_DEFVAL 0x0E00003C +#define DDR_PHY_DX6GCR4_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX6GCR4_RESERVED_7_6_MASK 0x000000C0U -/*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/ +/* +* VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. +*/ #undef DDR_PHY_DX6GCR4_DXREFIEN_DEFVAL #undef DDR_PHY_DX6GCR4_DXREFIEN_SHIFT #undef DDR_PHY_DX6GCR4_DXREFIEN_MASK -#define DDR_PHY_DX6GCR4_DXREFIEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX6GCR4_DXREFIEN_SHIFT 2 -#define DDR_PHY_DX6GCR4_DXREFIEN_MASK 0x0000003CU +#define DDR_PHY_DX6GCR4_DXREFIEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX6GCR4_DXREFIEN_SHIFT 2 +#define DDR_PHY_DX6GCR4_DXREFIEN_MASK 0x0000003CU -/*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/ +/* +* VRMON control for DQ IO (Single Ended) buffers of a byte lane. +*/ #undef DDR_PHY_DX6GCR4_DXREFIMON_DEFVAL #undef DDR_PHY_DX6GCR4_DXREFIMON_SHIFT #undef DDR_PHY_DX6GCR4_DXREFIMON_MASK -#define DDR_PHY_DX6GCR4_DXREFIMON_DEFVAL 0x0E00003C -#define DDR_PHY_DX6GCR4_DXREFIMON_SHIFT 0 -#define DDR_PHY_DX6GCR4_DXREFIMON_MASK 0x00000003U +#define DDR_PHY_DX6GCR4_DXREFIMON_DEFVAL 0x0E00003C +#define DDR_PHY_DX6GCR4_DXREFIMON_SHIFT 0 +#define DDR_PHY_DX6GCR4_DXREFIMON_MASK 0x00000003U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX6GCR5_RESERVED_31_DEFVAL #undef DDR_PHY_DX6GCR5_RESERVED_31_SHIFT #undef DDR_PHY_DX6GCR5_RESERVED_31_MASK -#define DDR_PHY_DX6GCR5_RESERVED_31_DEFVAL 0x09090909 -#define DDR_PHY_DX6GCR5_RESERVED_31_SHIFT 31 -#define DDR_PHY_DX6GCR5_RESERVED_31_MASK 0x80000000U +#define DDR_PHY_DX6GCR5_RESERVED_31_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR5_RESERVED_31_SHIFT 31 +#define DDR_PHY_DX6GCR5_RESERVED_31_MASK 0x80000000U -/*Byte Lane internal VREF Select for Rank 3*/ +/* +* Byte Lane internal VREF Select for Rank 3 +*/ #undef DDR_PHY_DX6GCR5_DXREFISELR3_DEFVAL #undef DDR_PHY_DX6GCR5_DXREFISELR3_SHIFT #undef DDR_PHY_DX6GCR5_DXREFISELR3_MASK -#define DDR_PHY_DX6GCR5_DXREFISELR3_DEFVAL 0x09090909 -#define DDR_PHY_DX6GCR5_DXREFISELR3_SHIFT 24 -#define DDR_PHY_DX6GCR5_DXREFISELR3_MASK 0x7F000000U +#define DDR_PHY_DX6GCR5_DXREFISELR3_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR5_DXREFISELR3_SHIFT 24 +#define DDR_PHY_DX6GCR5_DXREFISELR3_MASK 0x7F000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX6GCR5_RESERVED_23_DEFVAL #undef DDR_PHY_DX6GCR5_RESERVED_23_SHIFT #undef DDR_PHY_DX6GCR5_RESERVED_23_MASK -#define DDR_PHY_DX6GCR5_RESERVED_23_DEFVAL 0x09090909 -#define DDR_PHY_DX6GCR5_RESERVED_23_SHIFT 23 -#define DDR_PHY_DX6GCR5_RESERVED_23_MASK 0x00800000U +#define DDR_PHY_DX6GCR5_RESERVED_23_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR5_RESERVED_23_SHIFT 23 +#define DDR_PHY_DX6GCR5_RESERVED_23_MASK 0x00800000U -/*Byte Lane internal VREF Select for Rank 2*/ +/* +* Byte Lane internal VREF Select for Rank 2 +*/ #undef DDR_PHY_DX6GCR5_DXREFISELR2_DEFVAL #undef DDR_PHY_DX6GCR5_DXREFISELR2_SHIFT #undef DDR_PHY_DX6GCR5_DXREFISELR2_MASK -#define DDR_PHY_DX6GCR5_DXREFISELR2_DEFVAL 0x09090909 -#define DDR_PHY_DX6GCR5_DXREFISELR2_SHIFT 16 -#define DDR_PHY_DX6GCR5_DXREFISELR2_MASK 0x007F0000U +#define DDR_PHY_DX6GCR5_DXREFISELR2_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR5_DXREFISELR2_SHIFT 16 +#define DDR_PHY_DX6GCR5_DXREFISELR2_MASK 0x007F0000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX6GCR5_RESERVED_15_DEFVAL #undef DDR_PHY_DX6GCR5_RESERVED_15_SHIFT #undef DDR_PHY_DX6GCR5_RESERVED_15_MASK -#define DDR_PHY_DX6GCR5_RESERVED_15_DEFVAL 0x09090909 -#define DDR_PHY_DX6GCR5_RESERVED_15_SHIFT 15 -#define DDR_PHY_DX6GCR5_RESERVED_15_MASK 0x00008000U +#define DDR_PHY_DX6GCR5_RESERVED_15_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR5_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX6GCR5_RESERVED_15_MASK 0x00008000U -/*Byte Lane internal VREF Select for Rank 1*/ +/* +* Byte Lane internal VREF Select for Rank 1 +*/ #undef DDR_PHY_DX6GCR5_DXREFISELR1_DEFVAL #undef DDR_PHY_DX6GCR5_DXREFISELR1_SHIFT #undef DDR_PHY_DX6GCR5_DXREFISELR1_MASK -#define DDR_PHY_DX6GCR5_DXREFISELR1_DEFVAL 0x09090909 -#define DDR_PHY_DX6GCR5_DXREFISELR1_SHIFT 8 -#define DDR_PHY_DX6GCR5_DXREFISELR1_MASK 0x00007F00U +#define DDR_PHY_DX6GCR5_DXREFISELR1_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR5_DXREFISELR1_SHIFT 8 +#define DDR_PHY_DX6GCR5_DXREFISELR1_MASK 0x00007F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX6GCR5_RESERVED_7_DEFVAL #undef DDR_PHY_DX6GCR5_RESERVED_7_SHIFT #undef DDR_PHY_DX6GCR5_RESERVED_7_MASK -#define DDR_PHY_DX6GCR5_RESERVED_7_DEFVAL 0x09090909 -#define DDR_PHY_DX6GCR5_RESERVED_7_SHIFT 7 -#define DDR_PHY_DX6GCR5_RESERVED_7_MASK 0x00000080U +#define DDR_PHY_DX6GCR5_RESERVED_7_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR5_RESERVED_7_SHIFT 7 +#define DDR_PHY_DX6GCR5_RESERVED_7_MASK 0x00000080U -/*Byte Lane internal VREF Select for Rank 0*/ +/* +* Byte Lane internal VREF Select for Rank 0 +*/ #undef DDR_PHY_DX6GCR5_DXREFISELR0_DEFVAL #undef DDR_PHY_DX6GCR5_DXREFISELR0_SHIFT #undef DDR_PHY_DX6GCR5_DXREFISELR0_MASK -#define DDR_PHY_DX6GCR5_DXREFISELR0_DEFVAL 0x09090909 -#define DDR_PHY_DX6GCR5_DXREFISELR0_SHIFT 0 -#define DDR_PHY_DX6GCR5_DXREFISELR0_MASK 0x0000007FU +#define DDR_PHY_DX6GCR5_DXREFISELR0_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR5_DXREFISELR0_SHIFT 0 +#define DDR_PHY_DX6GCR5_DXREFISELR0_MASK 0x0000007FU -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX6GCR6_RESERVED_31_30_DEFVAL #undef DDR_PHY_DX6GCR6_RESERVED_31_30_SHIFT #undef DDR_PHY_DX6GCR6_RESERVED_31_30_MASK -#define DDR_PHY_DX6GCR6_RESERVED_31_30_DEFVAL 0x09090909 -#define DDR_PHY_DX6GCR6_RESERVED_31_30_SHIFT 30 -#define DDR_PHY_DX6GCR6_RESERVED_31_30_MASK 0xC0000000U +#define DDR_PHY_DX6GCR6_RESERVED_31_30_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR6_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX6GCR6_RESERVED_31_30_MASK 0xC0000000U -/*DRAM DQ VREF Select for Rank3*/ +/* +* DRAM DQ VREF Select for Rank3 +*/ #undef DDR_PHY_DX6GCR6_DXDQVREFR3_DEFVAL #undef DDR_PHY_DX6GCR6_DXDQVREFR3_SHIFT #undef DDR_PHY_DX6GCR6_DXDQVREFR3_MASK -#define DDR_PHY_DX6GCR6_DXDQVREFR3_DEFVAL 0x09090909 -#define DDR_PHY_DX6GCR6_DXDQVREFR3_SHIFT 24 -#define DDR_PHY_DX6GCR6_DXDQVREFR3_MASK 0x3F000000U +#define DDR_PHY_DX6GCR6_DXDQVREFR3_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR6_DXDQVREFR3_SHIFT 24 +#define DDR_PHY_DX6GCR6_DXDQVREFR3_MASK 0x3F000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX6GCR6_RESERVED_23_22_DEFVAL #undef DDR_PHY_DX6GCR6_RESERVED_23_22_SHIFT #undef DDR_PHY_DX6GCR6_RESERVED_23_22_MASK -#define DDR_PHY_DX6GCR6_RESERVED_23_22_DEFVAL 0x09090909 -#define DDR_PHY_DX6GCR6_RESERVED_23_22_SHIFT 22 -#define DDR_PHY_DX6GCR6_RESERVED_23_22_MASK 0x00C00000U +#define DDR_PHY_DX6GCR6_RESERVED_23_22_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR6_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX6GCR6_RESERVED_23_22_MASK 0x00C00000U -/*DRAM DQ VREF Select for Rank2*/ +/* +* DRAM DQ VREF Select for Rank2 +*/ #undef DDR_PHY_DX6GCR6_DXDQVREFR2_DEFVAL #undef DDR_PHY_DX6GCR6_DXDQVREFR2_SHIFT #undef DDR_PHY_DX6GCR6_DXDQVREFR2_MASK -#define DDR_PHY_DX6GCR6_DXDQVREFR2_DEFVAL 0x09090909 -#define DDR_PHY_DX6GCR6_DXDQVREFR2_SHIFT 16 -#define DDR_PHY_DX6GCR6_DXDQVREFR2_MASK 0x003F0000U +#define DDR_PHY_DX6GCR6_DXDQVREFR2_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR6_DXDQVREFR2_SHIFT 16 +#define DDR_PHY_DX6GCR6_DXDQVREFR2_MASK 0x003F0000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX6GCR6_RESERVED_15_14_DEFVAL #undef DDR_PHY_DX6GCR6_RESERVED_15_14_SHIFT #undef DDR_PHY_DX6GCR6_RESERVED_15_14_MASK -#define DDR_PHY_DX6GCR6_RESERVED_15_14_DEFVAL 0x09090909 -#define DDR_PHY_DX6GCR6_RESERVED_15_14_SHIFT 14 -#define DDR_PHY_DX6GCR6_RESERVED_15_14_MASK 0x0000C000U +#define DDR_PHY_DX6GCR6_RESERVED_15_14_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR6_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_DX6GCR6_RESERVED_15_14_MASK 0x0000C000U -/*DRAM DQ VREF Select for Rank1*/ +/* +* DRAM DQ VREF Select for Rank1 +*/ #undef DDR_PHY_DX6GCR6_DXDQVREFR1_DEFVAL #undef DDR_PHY_DX6GCR6_DXDQVREFR1_SHIFT #undef DDR_PHY_DX6GCR6_DXDQVREFR1_MASK -#define DDR_PHY_DX6GCR6_DXDQVREFR1_DEFVAL 0x09090909 -#define DDR_PHY_DX6GCR6_DXDQVREFR1_SHIFT 8 -#define DDR_PHY_DX6GCR6_DXDQVREFR1_MASK 0x00003F00U +#define DDR_PHY_DX6GCR6_DXDQVREFR1_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR6_DXDQVREFR1_SHIFT 8 +#define DDR_PHY_DX6GCR6_DXDQVREFR1_MASK 0x00003F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX6GCR6_RESERVED_7_6_DEFVAL #undef DDR_PHY_DX6GCR6_RESERVED_7_6_SHIFT #undef DDR_PHY_DX6GCR6_RESERVED_7_6_MASK -#define DDR_PHY_DX6GCR6_RESERVED_7_6_DEFVAL 0x09090909 -#define DDR_PHY_DX6GCR6_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_DX6GCR6_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_DX6GCR6_RESERVED_7_6_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR6_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX6GCR6_RESERVED_7_6_MASK 0x000000C0U -/*DRAM DQ VREF Select for Rank0*/ +/* +* DRAM DQ VREF Select for Rank0 +*/ #undef DDR_PHY_DX6GCR6_DXDQVREFR0_DEFVAL #undef DDR_PHY_DX6GCR6_DXDQVREFR0_SHIFT #undef DDR_PHY_DX6GCR6_DXDQVREFR0_MASK -#define DDR_PHY_DX6GCR6_DXDQVREFR0_DEFVAL 0x09090909 -#define DDR_PHY_DX6GCR6_DXDQVREFR0_SHIFT 0 -#define DDR_PHY_DX6GCR6_DXDQVREFR0_MASK 0x0000003FU +#define DDR_PHY_DX6GCR6_DXDQVREFR0_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR6_DXDQVREFR0_SHIFT 0 +#define DDR_PHY_DX6GCR6_DXDQVREFR0_MASK 0x0000003FU -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX6LCDLR2_RESERVED_31_25_DEFVAL -#undef DDR_PHY_DX6LCDLR2_RESERVED_31_25_SHIFT -#undef DDR_PHY_DX6LCDLR2_RESERVED_31_25_MASK -#define DDR_PHY_DX6LCDLR2_RESERVED_31_25_DEFVAL 0x00000000 -#define DDR_PHY_DX6LCDLR2_RESERVED_31_25_SHIFT 25 -#define DDR_PHY_DX6LCDLR2_RESERVED_31_25_MASK 0xFE000000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX6LCDLR2_RESERVED_24_16_DEFVAL -#undef DDR_PHY_DX6LCDLR2_RESERVED_24_16_SHIFT -#undef DDR_PHY_DX6LCDLR2_RESERVED_24_16_MASK -#define DDR_PHY_DX6LCDLR2_RESERVED_24_16_DEFVAL 0x00000000 -#define DDR_PHY_DX6LCDLR2_RESERVED_24_16_SHIFT 16 -#define DDR_PHY_DX6LCDLR2_RESERVED_24_16_MASK 0x01FF0000U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX6LCDLR2_RESERVED_15_9_DEFVAL -#undef DDR_PHY_DX6LCDLR2_RESERVED_15_9_SHIFT -#undef DDR_PHY_DX6LCDLR2_RESERVED_15_9_MASK -#define DDR_PHY_DX6LCDLR2_RESERVED_15_9_DEFVAL 0x00000000 -#define DDR_PHY_DX6LCDLR2_RESERVED_15_9_SHIFT 9 -#define DDR_PHY_DX6LCDLR2_RESERVED_15_9_MASK 0x0000FE00U - -/*Read DQS Gating Delay*/ -#undef DDR_PHY_DX6LCDLR2_DQSGD_DEFVAL -#undef DDR_PHY_DX6LCDLR2_DQSGD_SHIFT -#undef DDR_PHY_DX6LCDLR2_DQSGD_MASK -#define DDR_PHY_DX6LCDLR2_DQSGD_DEFVAL 0x00000000 -#define DDR_PHY_DX6LCDLR2_DQSGD_SHIFT 0 -#define DDR_PHY_DX6LCDLR2_DQSGD_MASK 0x000001FFU - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX6GTR0_RESERVED_31_24_DEFVAL -#undef DDR_PHY_DX6GTR0_RESERVED_31_24_SHIFT -#undef DDR_PHY_DX6GTR0_RESERVED_31_24_MASK -#define DDR_PHY_DX6GTR0_RESERVED_31_24_DEFVAL 0x00020000 -#define DDR_PHY_DX6GTR0_RESERVED_31_24_SHIFT 27 -#define DDR_PHY_DX6GTR0_RESERVED_31_24_MASK 0xF8000000U - -/*DQ Write Path Latency Pipeline*/ -#undef DDR_PHY_DX6GTR0_WDQSL_DEFVAL -#undef DDR_PHY_DX6GTR0_WDQSL_SHIFT -#undef DDR_PHY_DX6GTR0_WDQSL_MASK -#define DDR_PHY_DX6GTR0_WDQSL_DEFVAL 0x00020000 -#define DDR_PHY_DX6GTR0_WDQSL_SHIFT 24 -#define DDR_PHY_DX6GTR0_WDQSL_MASK 0x07000000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX6GTR0_RESERVED_23_20_DEFVAL -#undef DDR_PHY_DX6GTR0_RESERVED_23_20_SHIFT -#undef DDR_PHY_DX6GTR0_RESERVED_23_20_MASK -#define DDR_PHY_DX6GTR0_RESERVED_23_20_DEFVAL 0x00020000 -#define DDR_PHY_DX6GTR0_RESERVED_23_20_SHIFT 20 -#define DDR_PHY_DX6GTR0_RESERVED_23_20_MASK 0x00F00000U - -/*Write Leveling System Latency*/ -#undef DDR_PHY_DX6GTR0_WLSL_DEFVAL -#undef DDR_PHY_DX6GTR0_WLSL_SHIFT -#undef DDR_PHY_DX6GTR0_WLSL_MASK -#define DDR_PHY_DX6GTR0_WLSL_DEFVAL 0x00020000 -#define DDR_PHY_DX6GTR0_WLSL_SHIFT 16 -#define DDR_PHY_DX6GTR0_WLSL_MASK 0x000F0000U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX6GTR0_RESERVED_15_13_DEFVAL -#undef DDR_PHY_DX6GTR0_RESERVED_15_13_SHIFT -#undef DDR_PHY_DX6GTR0_RESERVED_15_13_MASK -#define DDR_PHY_DX6GTR0_RESERVED_15_13_DEFVAL 0x00020000 -#define DDR_PHY_DX6GTR0_RESERVED_15_13_SHIFT 13 -#define DDR_PHY_DX6GTR0_RESERVED_15_13_MASK 0x0000E000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX6GTR0_RESERVED_12_8_DEFVAL -#undef DDR_PHY_DX6GTR0_RESERVED_12_8_SHIFT -#undef DDR_PHY_DX6GTR0_RESERVED_12_8_MASK -#define DDR_PHY_DX6GTR0_RESERVED_12_8_DEFVAL 0x00020000 -#define DDR_PHY_DX6GTR0_RESERVED_12_8_SHIFT 8 -#define DDR_PHY_DX6GTR0_RESERVED_12_8_MASK 0x00001F00U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX6GTR0_RESERVED_7_5_DEFVAL -#undef DDR_PHY_DX6GTR0_RESERVED_7_5_SHIFT -#undef DDR_PHY_DX6GTR0_RESERVED_7_5_MASK -#define DDR_PHY_DX6GTR0_RESERVED_7_5_DEFVAL 0x00020000 -#define DDR_PHY_DX6GTR0_RESERVED_7_5_SHIFT 5 -#define DDR_PHY_DX6GTR0_RESERVED_7_5_MASK 0x000000E0U - -/*DQS Gating System Latency*/ -#undef DDR_PHY_DX6GTR0_DGSL_DEFVAL -#undef DDR_PHY_DX6GTR0_DGSL_SHIFT -#undef DDR_PHY_DX6GTR0_DGSL_MASK -#define DDR_PHY_DX6GTR0_DGSL_DEFVAL 0x00020000 -#define DDR_PHY_DX6GTR0_DGSL_SHIFT 0 -#define DDR_PHY_DX6GTR0_DGSL_MASK 0x0000001FU - -/*Calibration Bypass*/ +/* +* Calibration Bypass +*/ #undef DDR_PHY_DX7GCR0_CALBYP_DEFVAL #undef DDR_PHY_DX7GCR0_CALBYP_SHIFT #undef DDR_PHY_DX7GCR0_CALBYP_MASK -#define DDR_PHY_DX7GCR0_CALBYP_DEFVAL 0x40200204 -#define DDR_PHY_DX7GCR0_CALBYP_SHIFT 31 -#define DDR_PHY_DX7GCR0_CALBYP_MASK 0x80000000U +#define DDR_PHY_DX7GCR0_CALBYP_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_CALBYP_SHIFT 31 +#define DDR_PHY_DX7GCR0_CALBYP_MASK 0x80000000U -/*Master Delay Line Enable*/ +/* +* Master Delay Line Enable +*/ #undef DDR_PHY_DX7GCR0_MDLEN_DEFVAL #undef DDR_PHY_DX7GCR0_MDLEN_SHIFT #undef DDR_PHY_DX7GCR0_MDLEN_MASK -#define DDR_PHY_DX7GCR0_MDLEN_DEFVAL 0x40200204 -#define DDR_PHY_DX7GCR0_MDLEN_SHIFT 30 -#define DDR_PHY_DX7GCR0_MDLEN_MASK 0x40000000U +#define DDR_PHY_DX7GCR0_MDLEN_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_MDLEN_SHIFT 30 +#define DDR_PHY_DX7GCR0_MDLEN_MASK 0x40000000U -/*Configurable ODT(TE) Phase Shift*/ +/* +* Configurable ODT(TE) Phase Shift +*/ #undef DDR_PHY_DX7GCR0_CODTSHFT_DEFVAL #undef DDR_PHY_DX7GCR0_CODTSHFT_SHIFT #undef DDR_PHY_DX7GCR0_CODTSHFT_MASK -#define DDR_PHY_DX7GCR0_CODTSHFT_DEFVAL 0x40200204 -#define DDR_PHY_DX7GCR0_CODTSHFT_SHIFT 28 -#define DDR_PHY_DX7GCR0_CODTSHFT_MASK 0x30000000U +#define DDR_PHY_DX7GCR0_CODTSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_CODTSHFT_SHIFT 28 +#define DDR_PHY_DX7GCR0_CODTSHFT_MASK 0x30000000U -/*DQS Duty Cycle Correction*/ +/* +* DQS Duty Cycle Correction +*/ #undef DDR_PHY_DX7GCR0_DQSDCC_DEFVAL #undef DDR_PHY_DX7GCR0_DQSDCC_SHIFT #undef DDR_PHY_DX7GCR0_DQSDCC_MASK -#define DDR_PHY_DX7GCR0_DQSDCC_DEFVAL 0x40200204 -#define DDR_PHY_DX7GCR0_DQSDCC_SHIFT 24 -#define DDR_PHY_DX7GCR0_DQSDCC_MASK 0x0F000000U +#define DDR_PHY_DX7GCR0_DQSDCC_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_DQSDCC_SHIFT 24 +#define DDR_PHY_DX7GCR0_DQSDCC_MASK 0x0F000000U -/*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/ +/* +* Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY +*/ #undef DDR_PHY_DX7GCR0_RDDLY_DEFVAL #undef DDR_PHY_DX7GCR0_RDDLY_SHIFT #undef DDR_PHY_DX7GCR0_RDDLY_MASK -#define DDR_PHY_DX7GCR0_RDDLY_DEFVAL 0x40200204 -#define DDR_PHY_DX7GCR0_RDDLY_SHIFT 20 -#define DDR_PHY_DX7GCR0_RDDLY_MASK 0x00F00000U +#define DDR_PHY_DX7GCR0_RDDLY_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_RDDLY_SHIFT 20 +#define DDR_PHY_DX7GCR0_RDDLY_MASK 0x00F00000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX7GCR0_RESERVED_19_14_DEFVAL #undef DDR_PHY_DX7GCR0_RESERVED_19_14_SHIFT #undef DDR_PHY_DX7GCR0_RESERVED_19_14_MASK -#define DDR_PHY_DX7GCR0_RESERVED_19_14_DEFVAL 0x40200204 -#define DDR_PHY_DX7GCR0_RESERVED_19_14_SHIFT 14 -#define DDR_PHY_DX7GCR0_RESERVED_19_14_MASK 0x000FC000U +#define DDR_PHY_DX7GCR0_RESERVED_19_14_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_RESERVED_19_14_SHIFT 14 +#define DDR_PHY_DX7GCR0_RESERVED_19_14_MASK 0x000FC000U -/*DQSNSE Power Down Receiver*/ +/* +* DQSNSE Power Down Receiver +*/ #undef DDR_PHY_DX7GCR0_DQSNSEPDR_DEFVAL #undef DDR_PHY_DX7GCR0_DQSNSEPDR_SHIFT #undef DDR_PHY_DX7GCR0_DQSNSEPDR_MASK -#define DDR_PHY_DX7GCR0_DQSNSEPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX7GCR0_DQSNSEPDR_SHIFT 13 -#define DDR_PHY_DX7GCR0_DQSNSEPDR_MASK 0x00002000U +#define DDR_PHY_DX7GCR0_DQSNSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_DQSNSEPDR_SHIFT 13 +#define DDR_PHY_DX7GCR0_DQSNSEPDR_MASK 0x00002000U -/*DQSSE Power Down Receiver*/ +/* +* DQSSE Power Down Receiver +*/ #undef DDR_PHY_DX7GCR0_DQSSEPDR_DEFVAL #undef DDR_PHY_DX7GCR0_DQSSEPDR_SHIFT #undef DDR_PHY_DX7GCR0_DQSSEPDR_MASK -#define DDR_PHY_DX7GCR0_DQSSEPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX7GCR0_DQSSEPDR_SHIFT 12 -#define DDR_PHY_DX7GCR0_DQSSEPDR_MASK 0x00001000U +#define DDR_PHY_DX7GCR0_DQSSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_DQSSEPDR_SHIFT 12 +#define DDR_PHY_DX7GCR0_DQSSEPDR_MASK 0x00001000U -/*RTT On Additive Latency*/ +/* +* RTT On Additive Latency +*/ #undef DDR_PHY_DX7GCR0_RTTOAL_DEFVAL #undef DDR_PHY_DX7GCR0_RTTOAL_SHIFT #undef DDR_PHY_DX7GCR0_RTTOAL_MASK -#define DDR_PHY_DX7GCR0_RTTOAL_DEFVAL 0x40200204 -#define DDR_PHY_DX7GCR0_RTTOAL_SHIFT 11 -#define DDR_PHY_DX7GCR0_RTTOAL_MASK 0x00000800U +#define DDR_PHY_DX7GCR0_RTTOAL_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_RTTOAL_SHIFT 11 +#define DDR_PHY_DX7GCR0_RTTOAL_MASK 0x00000800U -/*RTT Output Hold*/ +/* +* RTT Output Hold +*/ #undef DDR_PHY_DX7GCR0_RTTOH_DEFVAL #undef DDR_PHY_DX7GCR0_RTTOH_SHIFT #undef DDR_PHY_DX7GCR0_RTTOH_MASK -#define DDR_PHY_DX7GCR0_RTTOH_DEFVAL 0x40200204 -#define DDR_PHY_DX7GCR0_RTTOH_SHIFT 9 -#define DDR_PHY_DX7GCR0_RTTOH_MASK 0x00000600U +#define DDR_PHY_DX7GCR0_RTTOH_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_RTTOH_SHIFT 9 +#define DDR_PHY_DX7GCR0_RTTOH_MASK 0x00000600U -/*Configurable PDR Phase Shift*/ +/* +* Configurable PDR Phase Shift +*/ #undef DDR_PHY_DX7GCR0_CPDRSHFT_DEFVAL #undef DDR_PHY_DX7GCR0_CPDRSHFT_SHIFT #undef DDR_PHY_DX7GCR0_CPDRSHFT_MASK -#define DDR_PHY_DX7GCR0_CPDRSHFT_DEFVAL 0x40200204 -#define DDR_PHY_DX7GCR0_CPDRSHFT_SHIFT 7 -#define DDR_PHY_DX7GCR0_CPDRSHFT_MASK 0x00000180U +#define DDR_PHY_DX7GCR0_CPDRSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_CPDRSHFT_SHIFT 7 +#define DDR_PHY_DX7GCR0_CPDRSHFT_MASK 0x00000180U -/*DQSR Power Down*/ +/* +* DQSR Power Down +*/ #undef DDR_PHY_DX7GCR0_DQSRPD_DEFVAL #undef DDR_PHY_DX7GCR0_DQSRPD_SHIFT #undef DDR_PHY_DX7GCR0_DQSRPD_MASK -#define DDR_PHY_DX7GCR0_DQSRPD_DEFVAL 0x40200204 -#define DDR_PHY_DX7GCR0_DQSRPD_SHIFT 6 -#define DDR_PHY_DX7GCR0_DQSRPD_MASK 0x00000040U +#define DDR_PHY_DX7GCR0_DQSRPD_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_DQSRPD_SHIFT 6 +#define DDR_PHY_DX7GCR0_DQSRPD_MASK 0x00000040U -/*DQSG Power Down Receiver*/ +/* +* DQSG Power Down Receiver +*/ #undef DDR_PHY_DX7GCR0_DQSGPDR_DEFVAL #undef DDR_PHY_DX7GCR0_DQSGPDR_SHIFT #undef DDR_PHY_DX7GCR0_DQSGPDR_MASK -#define DDR_PHY_DX7GCR0_DQSGPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX7GCR0_DQSGPDR_SHIFT 5 -#define DDR_PHY_DX7GCR0_DQSGPDR_MASK 0x00000020U +#define DDR_PHY_DX7GCR0_DQSGPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_DQSGPDR_SHIFT 5 +#define DDR_PHY_DX7GCR0_DQSGPDR_MASK 0x00000020U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX7GCR0_RESERVED_4_DEFVAL #undef DDR_PHY_DX7GCR0_RESERVED_4_SHIFT #undef DDR_PHY_DX7GCR0_RESERVED_4_MASK -#define DDR_PHY_DX7GCR0_RESERVED_4_DEFVAL 0x40200204 -#define DDR_PHY_DX7GCR0_RESERVED_4_SHIFT 4 -#define DDR_PHY_DX7GCR0_RESERVED_4_MASK 0x00000010U +#define DDR_PHY_DX7GCR0_RESERVED_4_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_RESERVED_4_SHIFT 4 +#define DDR_PHY_DX7GCR0_RESERVED_4_MASK 0x00000010U -/*DQSG On-Die Termination*/ +/* +* DQSG On-Die Termination +*/ #undef DDR_PHY_DX7GCR0_DQSGODT_DEFVAL #undef DDR_PHY_DX7GCR0_DQSGODT_SHIFT #undef DDR_PHY_DX7GCR0_DQSGODT_MASK -#define DDR_PHY_DX7GCR0_DQSGODT_DEFVAL 0x40200204 -#define DDR_PHY_DX7GCR0_DQSGODT_SHIFT 3 -#define DDR_PHY_DX7GCR0_DQSGODT_MASK 0x00000008U +#define DDR_PHY_DX7GCR0_DQSGODT_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_DQSGODT_SHIFT 3 +#define DDR_PHY_DX7GCR0_DQSGODT_MASK 0x00000008U -/*DQSG Output Enable*/ +/* +* DQSG Output Enable +*/ #undef DDR_PHY_DX7GCR0_DQSGOE_DEFVAL #undef DDR_PHY_DX7GCR0_DQSGOE_SHIFT #undef DDR_PHY_DX7GCR0_DQSGOE_MASK -#define DDR_PHY_DX7GCR0_DQSGOE_DEFVAL 0x40200204 -#define DDR_PHY_DX7GCR0_DQSGOE_SHIFT 2 -#define DDR_PHY_DX7GCR0_DQSGOE_MASK 0x00000004U +#define DDR_PHY_DX7GCR0_DQSGOE_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_DQSGOE_SHIFT 2 +#define DDR_PHY_DX7GCR0_DQSGOE_MASK 0x00000004U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX7GCR0_RESERVED_1_0_DEFVAL #undef DDR_PHY_DX7GCR0_RESERVED_1_0_SHIFT #undef DDR_PHY_DX7GCR0_RESERVED_1_0_MASK -#define DDR_PHY_DX7GCR0_RESERVED_1_0_DEFVAL 0x40200204 -#define DDR_PHY_DX7GCR0_RESERVED_1_0_SHIFT 0 -#define DDR_PHY_DX7GCR0_RESERVED_1_0_MASK 0x00000003U +#define DDR_PHY_DX7GCR0_RESERVED_1_0_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_RESERVED_1_0_SHIFT 0 +#define DDR_PHY_DX7GCR0_RESERVED_1_0_MASK 0x00000003U -/*Enables the PDR mode for DQ[7:0]*/ +/* +* Enables the PDR mode for DQ[7:0] +*/ #undef DDR_PHY_DX7GCR1_DXPDRMODE_DEFVAL #undef DDR_PHY_DX7GCR1_DXPDRMODE_SHIFT #undef DDR_PHY_DX7GCR1_DXPDRMODE_MASK -#define DDR_PHY_DX7GCR1_DXPDRMODE_DEFVAL 0x00007FFF -#define DDR_PHY_DX7GCR1_DXPDRMODE_SHIFT 16 -#define DDR_PHY_DX7GCR1_DXPDRMODE_MASK 0xFFFF0000U +#define DDR_PHY_DX7GCR1_DXPDRMODE_DEFVAL 0x00007FFF +#define DDR_PHY_DX7GCR1_DXPDRMODE_SHIFT 16 +#define DDR_PHY_DX7GCR1_DXPDRMODE_MASK 0xFFFF0000U -/*Reserved. Returns zeroes on reads.*/ +/* +* Reserved. Returns zeroes on reads. +*/ #undef DDR_PHY_DX7GCR1_RESERVED_15_DEFVAL #undef DDR_PHY_DX7GCR1_RESERVED_15_SHIFT #undef DDR_PHY_DX7GCR1_RESERVED_15_MASK -#define DDR_PHY_DX7GCR1_RESERVED_15_DEFVAL 0x00007FFF -#define DDR_PHY_DX7GCR1_RESERVED_15_SHIFT 15 -#define DDR_PHY_DX7GCR1_RESERVED_15_MASK 0x00008000U +#define DDR_PHY_DX7GCR1_RESERVED_15_DEFVAL 0x00007FFF +#define DDR_PHY_DX7GCR1_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX7GCR1_RESERVED_15_MASK 0x00008000U -/*Select the delayed or non-delayed read data strobe #*/ +/* +* Select the delayed or non-delayed read data strobe # +*/ #undef DDR_PHY_DX7GCR1_QSNSEL_DEFVAL #undef DDR_PHY_DX7GCR1_QSNSEL_SHIFT #undef DDR_PHY_DX7GCR1_QSNSEL_MASK -#define DDR_PHY_DX7GCR1_QSNSEL_DEFVAL 0x00007FFF -#define DDR_PHY_DX7GCR1_QSNSEL_SHIFT 14 -#define DDR_PHY_DX7GCR1_QSNSEL_MASK 0x00004000U +#define DDR_PHY_DX7GCR1_QSNSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX7GCR1_QSNSEL_SHIFT 14 +#define DDR_PHY_DX7GCR1_QSNSEL_MASK 0x00004000U -/*Select the delayed or non-delayed read data strobe*/ +/* +* Select the delayed or non-delayed read data strobe +*/ #undef DDR_PHY_DX7GCR1_QSSEL_DEFVAL #undef DDR_PHY_DX7GCR1_QSSEL_SHIFT #undef DDR_PHY_DX7GCR1_QSSEL_MASK -#define DDR_PHY_DX7GCR1_QSSEL_DEFVAL 0x00007FFF -#define DDR_PHY_DX7GCR1_QSSEL_SHIFT 13 -#define DDR_PHY_DX7GCR1_QSSEL_MASK 0x00002000U +#define DDR_PHY_DX7GCR1_QSSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX7GCR1_QSSEL_SHIFT 13 +#define DDR_PHY_DX7GCR1_QSSEL_MASK 0x00002000U -/*Enables Read Data Strobe in a byte lane*/ +/* +* Enables Read Data Strobe in a byte lane +*/ #undef DDR_PHY_DX7GCR1_OEEN_DEFVAL #undef DDR_PHY_DX7GCR1_OEEN_SHIFT #undef DDR_PHY_DX7GCR1_OEEN_MASK -#define DDR_PHY_DX7GCR1_OEEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX7GCR1_OEEN_SHIFT 12 -#define DDR_PHY_DX7GCR1_OEEN_MASK 0x00001000U +#define DDR_PHY_DX7GCR1_OEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX7GCR1_OEEN_SHIFT 12 +#define DDR_PHY_DX7GCR1_OEEN_MASK 0x00001000U -/*Enables PDR in a byte lane*/ +/* +* Enables PDR in a byte lane +*/ #undef DDR_PHY_DX7GCR1_PDREN_DEFVAL #undef DDR_PHY_DX7GCR1_PDREN_SHIFT #undef DDR_PHY_DX7GCR1_PDREN_MASK -#define DDR_PHY_DX7GCR1_PDREN_DEFVAL 0x00007FFF -#define DDR_PHY_DX7GCR1_PDREN_SHIFT 11 -#define DDR_PHY_DX7GCR1_PDREN_MASK 0x00000800U +#define DDR_PHY_DX7GCR1_PDREN_DEFVAL 0x00007FFF +#define DDR_PHY_DX7GCR1_PDREN_SHIFT 11 +#define DDR_PHY_DX7GCR1_PDREN_MASK 0x00000800U -/*Enables ODT/TE in a byte lane*/ +/* +* Enables ODT/TE in a byte lane +*/ #undef DDR_PHY_DX7GCR1_TEEN_DEFVAL #undef DDR_PHY_DX7GCR1_TEEN_SHIFT #undef DDR_PHY_DX7GCR1_TEEN_MASK -#define DDR_PHY_DX7GCR1_TEEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX7GCR1_TEEN_SHIFT 10 -#define DDR_PHY_DX7GCR1_TEEN_MASK 0x00000400U +#define DDR_PHY_DX7GCR1_TEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX7GCR1_TEEN_SHIFT 10 +#define DDR_PHY_DX7GCR1_TEEN_MASK 0x00000400U -/*Enables Write Data strobe in a byte lane*/ +/* +* Enables Write Data strobe in a byte lane +*/ #undef DDR_PHY_DX7GCR1_DSEN_DEFVAL #undef DDR_PHY_DX7GCR1_DSEN_SHIFT #undef DDR_PHY_DX7GCR1_DSEN_MASK -#define DDR_PHY_DX7GCR1_DSEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX7GCR1_DSEN_SHIFT 9 -#define DDR_PHY_DX7GCR1_DSEN_MASK 0x00000200U +#define DDR_PHY_DX7GCR1_DSEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX7GCR1_DSEN_SHIFT 9 +#define DDR_PHY_DX7GCR1_DSEN_MASK 0x00000200U -/*Enables DM pin in a byte lane*/ +/* +* Enables DM pin in a byte lane +*/ #undef DDR_PHY_DX7GCR1_DMEN_DEFVAL #undef DDR_PHY_DX7GCR1_DMEN_SHIFT #undef DDR_PHY_DX7GCR1_DMEN_MASK -#define DDR_PHY_DX7GCR1_DMEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX7GCR1_DMEN_SHIFT 8 -#define DDR_PHY_DX7GCR1_DMEN_MASK 0x00000100U +#define DDR_PHY_DX7GCR1_DMEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX7GCR1_DMEN_SHIFT 8 +#define DDR_PHY_DX7GCR1_DMEN_MASK 0x00000100U -/*Enables DQ corresponding to each bit in a byte*/ +/* +* Enables DQ corresponding to each bit in a byte +*/ #undef DDR_PHY_DX7GCR1_DQEN_DEFVAL #undef DDR_PHY_DX7GCR1_DQEN_SHIFT #undef DDR_PHY_DX7GCR1_DQEN_MASK -#define DDR_PHY_DX7GCR1_DQEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX7GCR1_DQEN_SHIFT 0 -#define DDR_PHY_DX7GCR1_DQEN_MASK 0x000000FFU +#define DDR_PHY_DX7GCR1_DQEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX7GCR1_DQEN_SHIFT 0 +#define DDR_PHY_DX7GCR1_DQEN_MASK 0x000000FFU -/*Byte lane VREF IOM (Used only by D4MU IOs)*/ +/* +* Byte lane VREF IOM (Used only by D4MU IOs) +*/ #undef DDR_PHY_DX7GCR4_RESERVED_31_29_DEFVAL #undef DDR_PHY_DX7GCR4_RESERVED_31_29_SHIFT #undef DDR_PHY_DX7GCR4_RESERVED_31_29_MASK -#define DDR_PHY_DX7GCR4_RESERVED_31_29_DEFVAL 0x0E00003C -#define DDR_PHY_DX7GCR4_RESERVED_31_29_SHIFT 29 -#define DDR_PHY_DX7GCR4_RESERVED_31_29_MASK 0xE0000000U +#define DDR_PHY_DX7GCR4_RESERVED_31_29_DEFVAL 0x0E00003C +#define DDR_PHY_DX7GCR4_RESERVED_31_29_SHIFT 29 +#define DDR_PHY_DX7GCR4_RESERVED_31_29_MASK 0xE0000000U -/*Byte Lane VREF Pad Enable*/ +/* +* Byte Lane VREF Pad Enable +*/ #undef DDR_PHY_DX7GCR4_DXREFPEN_DEFVAL #undef DDR_PHY_DX7GCR4_DXREFPEN_SHIFT #undef DDR_PHY_DX7GCR4_DXREFPEN_MASK -#define DDR_PHY_DX7GCR4_DXREFPEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX7GCR4_DXREFPEN_SHIFT 28 -#define DDR_PHY_DX7GCR4_DXREFPEN_MASK 0x10000000U +#define DDR_PHY_DX7GCR4_DXREFPEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX7GCR4_DXREFPEN_SHIFT 28 +#define DDR_PHY_DX7GCR4_DXREFPEN_MASK 0x10000000U -/*Byte Lane Internal VREF Enable*/ +/* +* Byte Lane Internal VREF Enable +*/ #undef DDR_PHY_DX7GCR4_DXREFEEN_DEFVAL #undef DDR_PHY_DX7GCR4_DXREFEEN_SHIFT #undef DDR_PHY_DX7GCR4_DXREFEEN_MASK -#define DDR_PHY_DX7GCR4_DXREFEEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX7GCR4_DXREFEEN_SHIFT 26 -#define DDR_PHY_DX7GCR4_DXREFEEN_MASK 0x0C000000U +#define DDR_PHY_DX7GCR4_DXREFEEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX7GCR4_DXREFEEN_SHIFT 26 +#define DDR_PHY_DX7GCR4_DXREFEEN_MASK 0x0C000000U -/*Byte Lane Single-End VREF Enable*/ +/* +* Byte Lane Single-End VREF Enable +*/ #undef DDR_PHY_DX7GCR4_DXREFSEN_DEFVAL #undef DDR_PHY_DX7GCR4_DXREFSEN_SHIFT #undef DDR_PHY_DX7GCR4_DXREFSEN_MASK -#define DDR_PHY_DX7GCR4_DXREFSEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX7GCR4_DXREFSEN_SHIFT 25 -#define DDR_PHY_DX7GCR4_DXREFSEN_MASK 0x02000000U +#define DDR_PHY_DX7GCR4_DXREFSEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX7GCR4_DXREFSEN_SHIFT 25 +#define DDR_PHY_DX7GCR4_DXREFSEN_MASK 0x02000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX7GCR4_RESERVED_24_DEFVAL #undef DDR_PHY_DX7GCR4_RESERVED_24_SHIFT #undef DDR_PHY_DX7GCR4_RESERVED_24_MASK -#define DDR_PHY_DX7GCR4_RESERVED_24_DEFVAL 0x0E00003C -#define DDR_PHY_DX7GCR4_RESERVED_24_SHIFT 24 -#define DDR_PHY_DX7GCR4_RESERVED_24_MASK 0x01000000U +#define DDR_PHY_DX7GCR4_RESERVED_24_DEFVAL 0x0E00003C +#define DDR_PHY_DX7GCR4_RESERVED_24_SHIFT 24 +#define DDR_PHY_DX7GCR4_RESERVED_24_MASK 0x01000000U -/*External VREF generator REFSEL range select*/ +/* +* External VREF generator REFSEL range select +*/ #undef DDR_PHY_DX7GCR4_DXREFESELRANGE_DEFVAL #undef DDR_PHY_DX7GCR4_DXREFESELRANGE_SHIFT #undef DDR_PHY_DX7GCR4_DXREFESELRANGE_MASK -#define DDR_PHY_DX7GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C -#define DDR_PHY_DX7GCR4_DXREFESELRANGE_SHIFT 23 -#define DDR_PHY_DX7GCR4_DXREFESELRANGE_MASK 0x00800000U +#define DDR_PHY_DX7GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX7GCR4_DXREFESELRANGE_SHIFT 23 +#define DDR_PHY_DX7GCR4_DXREFESELRANGE_MASK 0x00800000U -/*Byte Lane External VREF Select*/ +/* +* Byte Lane External VREF Select +*/ #undef DDR_PHY_DX7GCR4_DXREFESEL_DEFVAL #undef DDR_PHY_DX7GCR4_DXREFESEL_SHIFT #undef DDR_PHY_DX7GCR4_DXREFESEL_MASK -#define DDR_PHY_DX7GCR4_DXREFESEL_DEFVAL 0x0E00003C -#define DDR_PHY_DX7GCR4_DXREFESEL_SHIFT 16 -#define DDR_PHY_DX7GCR4_DXREFESEL_MASK 0x007F0000U +#define DDR_PHY_DX7GCR4_DXREFESEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX7GCR4_DXREFESEL_SHIFT 16 +#define DDR_PHY_DX7GCR4_DXREFESEL_MASK 0x007F0000U -/*Single ended VREF generator REFSEL range select*/ +/* +* Single ended VREF generator REFSEL range select +*/ #undef DDR_PHY_DX7GCR4_DXREFSSELRANGE_DEFVAL #undef DDR_PHY_DX7GCR4_DXREFSSELRANGE_SHIFT #undef DDR_PHY_DX7GCR4_DXREFSSELRANGE_MASK -#define DDR_PHY_DX7GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C -#define DDR_PHY_DX7GCR4_DXREFSSELRANGE_SHIFT 15 -#define DDR_PHY_DX7GCR4_DXREFSSELRANGE_MASK 0x00008000U +#define DDR_PHY_DX7GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX7GCR4_DXREFSSELRANGE_SHIFT 15 +#define DDR_PHY_DX7GCR4_DXREFSSELRANGE_MASK 0x00008000U -/*Byte Lane Single-End VREF Select*/ +/* +* Byte Lane Single-End VREF Select +*/ #undef DDR_PHY_DX7GCR4_DXREFSSEL_DEFVAL #undef DDR_PHY_DX7GCR4_DXREFSSEL_SHIFT #undef DDR_PHY_DX7GCR4_DXREFSSEL_MASK -#define DDR_PHY_DX7GCR4_DXREFSSEL_DEFVAL 0x0E00003C -#define DDR_PHY_DX7GCR4_DXREFSSEL_SHIFT 8 -#define DDR_PHY_DX7GCR4_DXREFSSEL_MASK 0x00007F00U +#define DDR_PHY_DX7GCR4_DXREFSSEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX7GCR4_DXREFSSEL_SHIFT 8 +#define DDR_PHY_DX7GCR4_DXREFSSEL_MASK 0x00007F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX7GCR4_RESERVED_7_6_DEFVAL #undef DDR_PHY_DX7GCR4_RESERVED_7_6_SHIFT #undef DDR_PHY_DX7GCR4_RESERVED_7_6_MASK -#define DDR_PHY_DX7GCR4_RESERVED_7_6_DEFVAL 0x0E00003C -#define DDR_PHY_DX7GCR4_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_DX7GCR4_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_DX7GCR4_RESERVED_7_6_DEFVAL 0x0E00003C +#define DDR_PHY_DX7GCR4_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX7GCR4_RESERVED_7_6_MASK 0x000000C0U -/*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/ +/* +* VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. +*/ #undef DDR_PHY_DX7GCR4_DXREFIEN_DEFVAL #undef DDR_PHY_DX7GCR4_DXREFIEN_SHIFT #undef DDR_PHY_DX7GCR4_DXREFIEN_MASK -#define DDR_PHY_DX7GCR4_DXREFIEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX7GCR4_DXREFIEN_SHIFT 2 -#define DDR_PHY_DX7GCR4_DXREFIEN_MASK 0x0000003CU +#define DDR_PHY_DX7GCR4_DXREFIEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX7GCR4_DXREFIEN_SHIFT 2 +#define DDR_PHY_DX7GCR4_DXREFIEN_MASK 0x0000003CU -/*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/ +/* +* VRMON control for DQ IO (Single Ended) buffers of a byte lane. +*/ #undef DDR_PHY_DX7GCR4_DXREFIMON_DEFVAL #undef DDR_PHY_DX7GCR4_DXREFIMON_SHIFT #undef DDR_PHY_DX7GCR4_DXREFIMON_MASK -#define DDR_PHY_DX7GCR4_DXREFIMON_DEFVAL 0x0E00003C -#define DDR_PHY_DX7GCR4_DXREFIMON_SHIFT 0 -#define DDR_PHY_DX7GCR4_DXREFIMON_MASK 0x00000003U +#define DDR_PHY_DX7GCR4_DXREFIMON_DEFVAL 0x0E00003C +#define DDR_PHY_DX7GCR4_DXREFIMON_SHIFT 0 +#define DDR_PHY_DX7GCR4_DXREFIMON_MASK 0x00000003U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX7GCR5_RESERVED_31_DEFVAL #undef DDR_PHY_DX7GCR5_RESERVED_31_SHIFT #undef DDR_PHY_DX7GCR5_RESERVED_31_MASK -#define DDR_PHY_DX7GCR5_RESERVED_31_DEFVAL 0x09090909 -#define DDR_PHY_DX7GCR5_RESERVED_31_SHIFT 31 -#define DDR_PHY_DX7GCR5_RESERVED_31_MASK 0x80000000U +#define DDR_PHY_DX7GCR5_RESERVED_31_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR5_RESERVED_31_SHIFT 31 +#define DDR_PHY_DX7GCR5_RESERVED_31_MASK 0x80000000U -/*Byte Lane internal VREF Select for Rank 3*/ +/* +* Byte Lane internal VREF Select for Rank 3 +*/ #undef DDR_PHY_DX7GCR5_DXREFISELR3_DEFVAL #undef DDR_PHY_DX7GCR5_DXREFISELR3_SHIFT #undef DDR_PHY_DX7GCR5_DXREFISELR3_MASK -#define DDR_PHY_DX7GCR5_DXREFISELR3_DEFVAL 0x09090909 -#define DDR_PHY_DX7GCR5_DXREFISELR3_SHIFT 24 -#define DDR_PHY_DX7GCR5_DXREFISELR3_MASK 0x7F000000U +#define DDR_PHY_DX7GCR5_DXREFISELR3_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR5_DXREFISELR3_SHIFT 24 +#define DDR_PHY_DX7GCR5_DXREFISELR3_MASK 0x7F000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX7GCR5_RESERVED_23_DEFVAL #undef DDR_PHY_DX7GCR5_RESERVED_23_SHIFT #undef DDR_PHY_DX7GCR5_RESERVED_23_MASK -#define DDR_PHY_DX7GCR5_RESERVED_23_DEFVAL 0x09090909 -#define DDR_PHY_DX7GCR5_RESERVED_23_SHIFT 23 -#define DDR_PHY_DX7GCR5_RESERVED_23_MASK 0x00800000U +#define DDR_PHY_DX7GCR5_RESERVED_23_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR5_RESERVED_23_SHIFT 23 +#define DDR_PHY_DX7GCR5_RESERVED_23_MASK 0x00800000U -/*Byte Lane internal VREF Select for Rank 2*/ +/* +* Byte Lane internal VREF Select for Rank 2 +*/ #undef DDR_PHY_DX7GCR5_DXREFISELR2_DEFVAL #undef DDR_PHY_DX7GCR5_DXREFISELR2_SHIFT #undef DDR_PHY_DX7GCR5_DXREFISELR2_MASK -#define DDR_PHY_DX7GCR5_DXREFISELR2_DEFVAL 0x09090909 -#define DDR_PHY_DX7GCR5_DXREFISELR2_SHIFT 16 -#define DDR_PHY_DX7GCR5_DXREFISELR2_MASK 0x007F0000U +#define DDR_PHY_DX7GCR5_DXREFISELR2_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR5_DXREFISELR2_SHIFT 16 +#define DDR_PHY_DX7GCR5_DXREFISELR2_MASK 0x007F0000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX7GCR5_RESERVED_15_DEFVAL #undef DDR_PHY_DX7GCR5_RESERVED_15_SHIFT #undef DDR_PHY_DX7GCR5_RESERVED_15_MASK -#define DDR_PHY_DX7GCR5_RESERVED_15_DEFVAL 0x09090909 -#define DDR_PHY_DX7GCR5_RESERVED_15_SHIFT 15 -#define DDR_PHY_DX7GCR5_RESERVED_15_MASK 0x00008000U +#define DDR_PHY_DX7GCR5_RESERVED_15_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR5_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX7GCR5_RESERVED_15_MASK 0x00008000U -/*Byte Lane internal VREF Select for Rank 1*/ +/* +* Byte Lane internal VREF Select for Rank 1 +*/ #undef DDR_PHY_DX7GCR5_DXREFISELR1_DEFVAL #undef DDR_PHY_DX7GCR5_DXREFISELR1_SHIFT #undef DDR_PHY_DX7GCR5_DXREFISELR1_MASK -#define DDR_PHY_DX7GCR5_DXREFISELR1_DEFVAL 0x09090909 -#define DDR_PHY_DX7GCR5_DXREFISELR1_SHIFT 8 -#define DDR_PHY_DX7GCR5_DXREFISELR1_MASK 0x00007F00U +#define DDR_PHY_DX7GCR5_DXREFISELR1_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR5_DXREFISELR1_SHIFT 8 +#define DDR_PHY_DX7GCR5_DXREFISELR1_MASK 0x00007F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX7GCR5_RESERVED_7_DEFVAL #undef DDR_PHY_DX7GCR5_RESERVED_7_SHIFT #undef DDR_PHY_DX7GCR5_RESERVED_7_MASK -#define DDR_PHY_DX7GCR5_RESERVED_7_DEFVAL 0x09090909 -#define DDR_PHY_DX7GCR5_RESERVED_7_SHIFT 7 -#define DDR_PHY_DX7GCR5_RESERVED_7_MASK 0x00000080U +#define DDR_PHY_DX7GCR5_RESERVED_7_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR5_RESERVED_7_SHIFT 7 +#define DDR_PHY_DX7GCR5_RESERVED_7_MASK 0x00000080U -/*Byte Lane internal VREF Select for Rank 0*/ +/* +* Byte Lane internal VREF Select for Rank 0 +*/ #undef DDR_PHY_DX7GCR5_DXREFISELR0_DEFVAL #undef DDR_PHY_DX7GCR5_DXREFISELR0_SHIFT #undef DDR_PHY_DX7GCR5_DXREFISELR0_MASK -#define DDR_PHY_DX7GCR5_DXREFISELR0_DEFVAL 0x09090909 -#define DDR_PHY_DX7GCR5_DXREFISELR0_SHIFT 0 -#define DDR_PHY_DX7GCR5_DXREFISELR0_MASK 0x0000007FU +#define DDR_PHY_DX7GCR5_DXREFISELR0_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR5_DXREFISELR0_SHIFT 0 +#define DDR_PHY_DX7GCR5_DXREFISELR0_MASK 0x0000007FU -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX7GCR6_RESERVED_31_30_DEFVAL #undef DDR_PHY_DX7GCR6_RESERVED_31_30_SHIFT #undef DDR_PHY_DX7GCR6_RESERVED_31_30_MASK -#define DDR_PHY_DX7GCR6_RESERVED_31_30_DEFVAL 0x09090909 -#define DDR_PHY_DX7GCR6_RESERVED_31_30_SHIFT 30 -#define DDR_PHY_DX7GCR6_RESERVED_31_30_MASK 0xC0000000U +#define DDR_PHY_DX7GCR6_RESERVED_31_30_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR6_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX7GCR6_RESERVED_31_30_MASK 0xC0000000U -/*DRAM DQ VREF Select for Rank3*/ +/* +* DRAM DQ VREF Select for Rank3 +*/ #undef DDR_PHY_DX7GCR6_DXDQVREFR3_DEFVAL #undef DDR_PHY_DX7GCR6_DXDQVREFR3_SHIFT #undef DDR_PHY_DX7GCR6_DXDQVREFR3_MASK -#define DDR_PHY_DX7GCR6_DXDQVREFR3_DEFVAL 0x09090909 -#define DDR_PHY_DX7GCR6_DXDQVREFR3_SHIFT 24 -#define DDR_PHY_DX7GCR6_DXDQVREFR3_MASK 0x3F000000U +#define DDR_PHY_DX7GCR6_DXDQVREFR3_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR6_DXDQVREFR3_SHIFT 24 +#define DDR_PHY_DX7GCR6_DXDQVREFR3_MASK 0x3F000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX7GCR6_RESERVED_23_22_DEFVAL #undef DDR_PHY_DX7GCR6_RESERVED_23_22_SHIFT #undef DDR_PHY_DX7GCR6_RESERVED_23_22_MASK -#define DDR_PHY_DX7GCR6_RESERVED_23_22_DEFVAL 0x09090909 -#define DDR_PHY_DX7GCR6_RESERVED_23_22_SHIFT 22 -#define DDR_PHY_DX7GCR6_RESERVED_23_22_MASK 0x00C00000U +#define DDR_PHY_DX7GCR6_RESERVED_23_22_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR6_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX7GCR6_RESERVED_23_22_MASK 0x00C00000U -/*DRAM DQ VREF Select for Rank2*/ +/* +* DRAM DQ VREF Select for Rank2 +*/ #undef DDR_PHY_DX7GCR6_DXDQVREFR2_DEFVAL #undef DDR_PHY_DX7GCR6_DXDQVREFR2_SHIFT #undef DDR_PHY_DX7GCR6_DXDQVREFR2_MASK -#define DDR_PHY_DX7GCR6_DXDQVREFR2_DEFVAL 0x09090909 -#define DDR_PHY_DX7GCR6_DXDQVREFR2_SHIFT 16 -#define DDR_PHY_DX7GCR6_DXDQVREFR2_MASK 0x003F0000U +#define DDR_PHY_DX7GCR6_DXDQVREFR2_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR6_DXDQVREFR2_SHIFT 16 +#define DDR_PHY_DX7GCR6_DXDQVREFR2_MASK 0x003F0000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX7GCR6_RESERVED_15_14_DEFVAL #undef DDR_PHY_DX7GCR6_RESERVED_15_14_SHIFT #undef DDR_PHY_DX7GCR6_RESERVED_15_14_MASK -#define DDR_PHY_DX7GCR6_RESERVED_15_14_DEFVAL 0x09090909 -#define DDR_PHY_DX7GCR6_RESERVED_15_14_SHIFT 14 -#define DDR_PHY_DX7GCR6_RESERVED_15_14_MASK 0x0000C000U +#define DDR_PHY_DX7GCR6_RESERVED_15_14_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR6_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_DX7GCR6_RESERVED_15_14_MASK 0x0000C000U -/*DRAM DQ VREF Select for Rank1*/ +/* +* DRAM DQ VREF Select for Rank1 +*/ #undef DDR_PHY_DX7GCR6_DXDQVREFR1_DEFVAL #undef DDR_PHY_DX7GCR6_DXDQVREFR1_SHIFT #undef DDR_PHY_DX7GCR6_DXDQVREFR1_MASK -#define DDR_PHY_DX7GCR6_DXDQVREFR1_DEFVAL 0x09090909 -#define DDR_PHY_DX7GCR6_DXDQVREFR1_SHIFT 8 -#define DDR_PHY_DX7GCR6_DXDQVREFR1_MASK 0x00003F00U +#define DDR_PHY_DX7GCR6_DXDQVREFR1_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR6_DXDQVREFR1_SHIFT 8 +#define DDR_PHY_DX7GCR6_DXDQVREFR1_MASK 0x00003F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX7GCR6_RESERVED_7_6_DEFVAL #undef DDR_PHY_DX7GCR6_RESERVED_7_6_SHIFT #undef DDR_PHY_DX7GCR6_RESERVED_7_6_MASK -#define DDR_PHY_DX7GCR6_RESERVED_7_6_DEFVAL 0x09090909 -#define DDR_PHY_DX7GCR6_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_DX7GCR6_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_DX7GCR6_RESERVED_7_6_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR6_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX7GCR6_RESERVED_7_6_MASK 0x000000C0U -/*DRAM DQ VREF Select for Rank0*/ +/* +* DRAM DQ VREF Select for Rank0 +*/ #undef DDR_PHY_DX7GCR6_DXDQVREFR0_DEFVAL #undef DDR_PHY_DX7GCR6_DXDQVREFR0_SHIFT #undef DDR_PHY_DX7GCR6_DXDQVREFR0_MASK -#define DDR_PHY_DX7GCR6_DXDQVREFR0_DEFVAL 0x09090909 -#define DDR_PHY_DX7GCR6_DXDQVREFR0_SHIFT 0 -#define DDR_PHY_DX7GCR6_DXDQVREFR0_MASK 0x0000003FU +#define DDR_PHY_DX7GCR6_DXDQVREFR0_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR6_DXDQVREFR0_SHIFT 0 +#define DDR_PHY_DX7GCR6_DXDQVREFR0_MASK 0x0000003FU -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX7LCDLR2_RESERVED_31_25_DEFVAL -#undef DDR_PHY_DX7LCDLR2_RESERVED_31_25_SHIFT -#undef DDR_PHY_DX7LCDLR2_RESERVED_31_25_MASK -#define DDR_PHY_DX7LCDLR2_RESERVED_31_25_DEFVAL 0x00000000 -#define DDR_PHY_DX7LCDLR2_RESERVED_31_25_SHIFT 25 -#define DDR_PHY_DX7LCDLR2_RESERVED_31_25_MASK 0xFE000000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX7LCDLR2_RESERVED_24_16_DEFVAL -#undef DDR_PHY_DX7LCDLR2_RESERVED_24_16_SHIFT -#undef DDR_PHY_DX7LCDLR2_RESERVED_24_16_MASK -#define DDR_PHY_DX7LCDLR2_RESERVED_24_16_DEFVAL 0x00000000 -#define DDR_PHY_DX7LCDLR2_RESERVED_24_16_SHIFT 16 -#define DDR_PHY_DX7LCDLR2_RESERVED_24_16_MASK 0x01FF0000U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX7LCDLR2_RESERVED_15_9_DEFVAL -#undef DDR_PHY_DX7LCDLR2_RESERVED_15_9_SHIFT -#undef DDR_PHY_DX7LCDLR2_RESERVED_15_9_MASK -#define DDR_PHY_DX7LCDLR2_RESERVED_15_9_DEFVAL 0x00000000 -#define DDR_PHY_DX7LCDLR2_RESERVED_15_9_SHIFT 9 -#define DDR_PHY_DX7LCDLR2_RESERVED_15_9_MASK 0x0000FE00U - -/*Read DQS Gating Delay*/ -#undef DDR_PHY_DX7LCDLR2_DQSGD_DEFVAL -#undef DDR_PHY_DX7LCDLR2_DQSGD_SHIFT -#undef DDR_PHY_DX7LCDLR2_DQSGD_MASK -#define DDR_PHY_DX7LCDLR2_DQSGD_DEFVAL 0x00000000 -#define DDR_PHY_DX7LCDLR2_DQSGD_SHIFT 0 -#define DDR_PHY_DX7LCDLR2_DQSGD_MASK 0x000001FFU - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX7GTR0_RESERVED_31_24_DEFVAL -#undef DDR_PHY_DX7GTR0_RESERVED_31_24_SHIFT -#undef DDR_PHY_DX7GTR0_RESERVED_31_24_MASK -#define DDR_PHY_DX7GTR0_RESERVED_31_24_DEFVAL 0x00020000 -#define DDR_PHY_DX7GTR0_RESERVED_31_24_SHIFT 27 -#define DDR_PHY_DX7GTR0_RESERVED_31_24_MASK 0xF8000000U - -/*DQ Write Path Latency Pipeline*/ -#undef DDR_PHY_DX7GTR0_WDQSL_DEFVAL -#undef DDR_PHY_DX7GTR0_WDQSL_SHIFT -#undef DDR_PHY_DX7GTR0_WDQSL_MASK -#define DDR_PHY_DX7GTR0_WDQSL_DEFVAL 0x00020000 -#define DDR_PHY_DX7GTR0_WDQSL_SHIFT 24 -#define DDR_PHY_DX7GTR0_WDQSL_MASK 0x07000000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX7GTR0_RESERVED_23_20_DEFVAL -#undef DDR_PHY_DX7GTR0_RESERVED_23_20_SHIFT -#undef DDR_PHY_DX7GTR0_RESERVED_23_20_MASK -#define DDR_PHY_DX7GTR0_RESERVED_23_20_DEFVAL 0x00020000 -#define DDR_PHY_DX7GTR0_RESERVED_23_20_SHIFT 20 -#define DDR_PHY_DX7GTR0_RESERVED_23_20_MASK 0x00F00000U - -/*Write Leveling System Latency*/ -#undef DDR_PHY_DX7GTR0_WLSL_DEFVAL -#undef DDR_PHY_DX7GTR0_WLSL_SHIFT -#undef DDR_PHY_DX7GTR0_WLSL_MASK -#define DDR_PHY_DX7GTR0_WLSL_DEFVAL 0x00020000 -#define DDR_PHY_DX7GTR0_WLSL_SHIFT 16 -#define DDR_PHY_DX7GTR0_WLSL_MASK 0x000F0000U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX7GTR0_RESERVED_15_13_DEFVAL -#undef DDR_PHY_DX7GTR0_RESERVED_15_13_SHIFT -#undef DDR_PHY_DX7GTR0_RESERVED_15_13_MASK -#define DDR_PHY_DX7GTR0_RESERVED_15_13_DEFVAL 0x00020000 -#define DDR_PHY_DX7GTR0_RESERVED_15_13_SHIFT 13 -#define DDR_PHY_DX7GTR0_RESERVED_15_13_MASK 0x0000E000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX7GTR0_RESERVED_12_8_DEFVAL -#undef DDR_PHY_DX7GTR0_RESERVED_12_8_SHIFT -#undef DDR_PHY_DX7GTR0_RESERVED_12_8_MASK -#define DDR_PHY_DX7GTR0_RESERVED_12_8_DEFVAL 0x00020000 -#define DDR_PHY_DX7GTR0_RESERVED_12_8_SHIFT 8 -#define DDR_PHY_DX7GTR0_RESERVED_12_8_MASK 0x00001F00U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX7GTR0_RESERVED_7_5_DEFVAL -#undef DDR_PHY_DX7GTR0_RESERVED_7_5_SHIFT -#undef DDR_PHY_DX7GTR0_RESERVED_7_5_MASK -#define DDR_PHY_DX7GTR0_RESERVED_7_5_DEFVAL 0x00020000 -#define DDR_PHY_DX7GTR0_RESERVED_7_5_SHIFT 5 -#define DDR_PHY_DX7GTR0_RESERVED_7_5_MASK 0x000000E0U - -/*DQS Gating System Latency*/ -#undef DDR_PHY_DX7GTR0_DGSL_DEFVAL -#undef DDR_PHY_DX7GTR0_DGSL_SHIFT -#undef DDR_PHY_DX7GTR0_DGSL_MASK -#define DDR_PHY_DX7GTR0_DGSL_DEFVAL 0x00020000 -#define DDR_PHY_DX7GTR0_DGSL_SHIFT 0 -#define DDR_PHY_DX7GTR0_DGSL_MASK 0x0000001FU - -/*Calibration Bypass*/ +/* +* Calibration Bypass +*/ #undef DDR_PHY_DX8GCR0_CALBYP_DEFVAL #undef DDR_PHY_DX8GCR0_CALBYP_SHIFT #undef DDR_PHY_DX8GCR0_CALBYP_MASK -#define DDR_PHY_DX8GCR0_CALBYP_DEFVAL 0x40200204 -#define DDR_PHY_DX8GCR0_CALBYP_SHIFT 31 -#define DDR_PHY_DX8GCR0_CALBYP_MASK 0x80000000U +#define DDR_PHY_DX8GCR0_CALBYP_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_CALBYP_SHIFT 31 +#define DDR_PHY_DX8GCR0_CALBYP_MASK 0x80000000U -/*Master Delay Line Enable*/ +/* +* Master Delay Line Enable +*/ #undef DDR_PHY_DX8GCR0_MDLEN_DEFVAL #undef DDR_PHY_DX8GCR0_MDLEN_SHIFT #undef DDR_PHY_DX8GCR0_MDLEN_MASK -#define DDR_PHY_DX8GCR0_MDLEN_DEFVAL 0x40200204 -#define DDR_PHY_DX8GCR0_MDLEN_SHIFT 30 -#define DDR_PHY_DX8GCR0_MDLEN_MASK 0x40000000U +#define DDR_PHY_DX8GCR0_MDLEN_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_MDLEN_SHIFT 30 +#define DDR_PHY_DX8GCR0_MDLEN_MASK 0x40000000U -/*Configurable ODT(TE) Phase Shift*/ +/* +* Configurable ODT(TE) Phase Shift +*/ #undef DDR_PHY_DX8GCR0_CODTSHFT_DEFVAL #undef DDR_PHY_DX8GCR0_CODTSHFT_SHIFT #undef DDR_PHY_DX8GCR0_CODTSHFT_MASK -#define DDR_PHY_DX8GCR0_CODTSHFT_DEFVAL 0x40200204 -#define DDR_PHY_DX8GCR0_CODTSHFT_SHIFT 28 -#define DDR_PHY_DX8GCR0_CODTSHFT_MASK 0x30000000U +#define DDR_PHY_DX8GCR0_CODTSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_CODTSHFT_SHIFT 28 +#define DDR_PHY_DX8GCR0_CODTSHFT_MASK 0x30000000U -/*DQS Duty Cycle Correction*/ +/* +* DQS Duty Cycle Correction +*/ #undef DDR_PHY_DX8GCR0_DQSDCC_DEFVAL #undef DDR_PHY_DX8GCR0_DQSDCC_SHIFT #undef DDR_PHY_DX8GCR0_DQSDCC_MASK -#define DDR_PHY_DX8GCR0_DQSDCC_DEFVAL 0x40200204 -#define DDR_PHY_DX8GCR0_DQSDCC_SHIFT 24 -#define DDR_PHY_DX8GCR0_DQSDCC_MASK 0x0F000000U +#define DDR_PHY_DX8GCR0_DQSDCC_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_DQSDCC_SHIFT 24 +#define DDR_PHY_DX8GCR0_DQSDCC_MASK 0x0F000000U -/*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/ +/* +* Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY +*/ #undef DDR_PHY_DX8GCR0_RDDLY_DEFVAL #undef DDR_PHY_DX8GCR0_RDDLY_SHIFT #undef DDR_PHY_DX8GCR0_RDDLY_MASK -#define DDR_PHY_DX8GCR0_RDDLY_DEFVAL 0x40200204 -#define DDR_PHY_DX8GCR0_RDDLY_SHIFT 20 -#define DDR_PHY_DX8GCR0_RDDLY_MASK 0x00F00000U +#define DDR_PHY_DX8GCR0_RDDLY_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_RDDLY_SHIFT 20 +#define DDR_PHY_DX8GCR0_RDDLY_MASK 0x00F00000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8GCR0_RESERVED_19_14_DEFVAL #undef DDR_PHY_DX8GCR0_RESERVED_19_14_SHIFT #undef DDR_PHY_DX8GCR0_RESERVED_19_14_MASK -#define DDR_PHY_DX8GCR0_RESERVED_19_14_DEFVAL 0x40200204 -#define DDR_PHY_DX8GCR0_RESERVED_19_14_SHIFT 14 -#define DDR_PHY_DX8GCR0_RESERVED_19_14_MASK 0x000FC000U +#define DDR_PHY_DX8GCR0_RESERVED_19_14_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_RESERVED_19_14_SHIFT 14 +#define DDR_PHY_DX8GCR0_RESERVED_19_14_MASK 0x000FC000U -/*DQSNSE Power Down Receiver*/ +/* +* DQSNSE Power Down Receiver +*/ #undef DDR_PHY_DX8GCR0_DQSNSEPDR_DEFVAL #undef DDR_PHY_DX8GCR0_DQSNSEPDR_SHIFT #undef DDR_PHY_DX8GCR0_DQSNSEPDR_MASK -#define DDR_PHY_DX8GCR0_DQSNSEPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX8GCR0_DQSNSEPDR_SHIFT 13 -#define DDR_PHY_DX8GCR0_DQSNSEPDR_MASK 0x00002000U +#define DDR_PHY_DX8GCR0_DQSNSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_DQSNSEPDR_SHIFT 13 +#define DDR_PHY_DX8GCR0_DQSNSEPDR_MASK 0x00002000U -/*DQSSE Power Down Receiver*/ +/* +* DQSSE Power Down Receiver +*/ #undef DDR_PHY_DX8GCR0_DQSSEPDR_DEFVAL #undef DDR_PHY_DX8GCR0_DQSSEPDR_SHIFT #undef DDR_PHY_DX8GCR0_DQSSEPDR_MASK -#define DDR_PHY_DX8GCR0_DQSSEPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX8GCR0_DQSSEPDR_SHIFT 12 -#define DDR_PHY_DX8GCR0_DQSSEPDR_MASK 0x00001000U +#define DDR_PHY_DX8GCR0_DQSSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_DQSSEPDR_SHIFT 12 +#define DDR_PHY_DX8GCR0_DQSSEPDR_MASK 0x00001000U -/*RTT On Additive Latency*/ +/* +* RTT On Additive Latency +*/ #undef DDR_PHY_DX8GCR0_RTTOAL_DEFVAL #undef DDR_PHY_DX8GCR0_RTTOAL_SHIFT #undef DDR_PHY_DX8GCR0_RTTOAL_MASK -#define DDR_PHY_DX8GCR0_RTTOAL_DEFVAL 0x40200204 -#define DDR_PHY_DX8GCR0_RTTOAL_SHIFT 11 -#define DDR_PHY_DX8GCR0_RTTOAL_MASK 0x00000800U +#define DDR_PHY_DX8GCR0_RTTOAL_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_RTTOAL_SHIFT 11 +#define DDR_PHY_DX8GCR0_RTTOAL_MASK 0x00000800U -/*RTT Output Hold*/ +/* +* RTT Output Hold +*/ #undef DDR_PHY_DX8GCR0_RTTOH_DEFVAL #undef DDR_PHY_DX8GCR0_RTTOH_SHIFT #undef DDR_PHY_DX8GCR0_RTTOH_MASK -#define DDR_PHY_DX8GCR0_RTTOH_DEFVAL 0x40200204 -#define DDR_PHY_DX8GCR0_RTTOH_SHIFT 9 -#define DDR_PHY_DX8GCR0_RTTOH_MASK 0x00000600U +#define DDR_PHY_DX8GCR0_RTTOH_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_RTTOH_SHIFT 9 +#define DDR_PHY_DX8GCR0_RTTOH_MASK 0x00000600U -/*Configurable PDR Phase Shift*/ +/* +* Configurable PDR Phase Shift +*/ #undef DDR_PHY_DX8GCR0_CPDRSHFT_DEFVAL #undef DDR_PHY_DX8GCR0_CPDRSHFT_SHIFT #undef DDR_PHY_DX8GCR0_CPDRSHFT_MASK -#define DDR_PHY_DX8GCR0_CPDRSHFT_DEFVAL 0x40200204 -#define DDR_PHY_DX8GCR0_CPDRSHFT_SHIFT 7 -#define DDR_PHY_DX8GCR0_CPDRSHFT_MASK 0x00000180U +#define DDR_PHY_DX8GCR0_CPDRSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_CPDRSHFT_SHIFT 7 +#define DDR_PHY_DX8GCR0_CPDRSHFT_MASK 0x00000180U -/*DQSR Power Down*/ +/* +* DQSR Power Down +*/ #undef DDR_PHY_DX8GCR0_DQSRPD_DEFVAL #undef DDR_PHY_DX8GCR0_DQSRPD_SHIFT #undef DDR_PHY_DX8GCR0_DQSRPD_MASK -#define DDR_PHY_DX8GCR0_DQSRPD_DEFVAL 0x40200204 -#define DDR_PHY_DX8GCR0_DQSRPD_SHIFT 6 -#define DDR_PHY_DX8GCR0_DQSRPD_MASK 0x00000040U +#define DDR_PHY_DX8GCR0_DQSRPD_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_DQSRPD_SHIFT 6 +#define DDR_PHY_DX8GCR0_DQSRPD_MASK 0x00000040U -/*DQSG Power Down Receiver*/ +/* +* DQSG Power Down Receiver +*/ #undef DDR_PHY_DX8GCR0_DQSGPDR_DEFVAL #undef DDR_PHY_DX8GCR0_DQSGPDR_SHIFT #undef DDR_PHY_DX8GCR0_DQSGPDR_MASK -#define DDR_PHY_DX8GCR0_DQSGPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX8GCR0_DQSGPDR_SHIFT 5 -#define DDR_PHY_DX8GCR0_DQSGPDR_MASK 0x00000020U +#define DDR_PHY_DX8GCR0_DQSGPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_DQSGPDR_SHIFT 5 +#define DDR_PHY_DX8GCR0_DQSGPDR_MASK 0x00000020U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8GCR0_RESERVED_4_DEFVAL #undef DDR_PHY_DX8GCR0_RESERVED_4_SHIFT #undef DDR_PHY_DX8GCR0_RESERVED_4_MASK -#define DDR_PHY_DX8GCR0_RESERVED_4_DEFVAL 0x40200204 -#define DDR_PHY_DX8GCR0_RESERVED_4_SHIFT 4 -#define DDR_PHY_DX8GCR0_RESERVED_4_MASK 0x00000010U +#define DDR_PHY_DX8GCR0_RESERVED_4_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_RESERVED_4_SHIFT 4 +#define DDR_PHY_DX8GCR0_RESERVED_4_MASK 0x00000010U -/*DQSG On-Die Termination*/ +/* +* DQSG On-Die Termination +*/ #undef DDR_PHY_DX8GCR0_DQSGODT_DEFVAL #undef DDR_PHY_DX8GCR0_DQSGODT_SHIFT #undef DDR_PHY_DX8GCR0_DQSGODT_MASK -#define DDR_PHY_DX8GCR0_DQSGODT_DEFVAL 0x40200204 -#define DDR_PHY_DX8GCR0_DQSGODT_SHIFT 3 -#define DDR_PHY_DX8GCR0_DQSGODT_MASK 0x00000008U +#define DDR_PHY_DX8GCR0_DQSGODT_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_DQSGODT_SHIFT 3 +#define DDR_PHY_DX8GCR0_DQSGODT_MASK 0x00000008U -/*DQSG Output Enable*/ +/* +* DQSG Output Enable +*/ #undef DDR_PHY_DX8GCR0_DQSGOE_DEFVAL #undef DDR_PHY_DX8GCR0_DQSGOE_SHIFT #undef DDR_PHY_DX8GCR0_DQSGOE_MASK -#define DDR_PHY_DX8GCR0_DQSGOE_DEFVAL 0x40200204 -#define DDR_PHY_DX8GCR0_DQSGOE_SHIFT 2 -#define DDR_PHY_DX8GCR0_DQSGOE_MASK 0x00000004U +#define DDR_PHY_DX8GCR0_DQSGOE_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_DQSGOE_SHIFT 2 +#define DDR_PHY_DX8GCR0_DQSGOE_MASK 0x00000004U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8GCR0_RESERVED_1_0_DEFVAL #undef DDR_PHY_DX8GCR0_RESERVED_1_0_SHIFT #undef DDR_PHY_DX8GCR0_RESERVED_1_0_MASK -#define DDR_PHY_DX8GCR0_RESERVED_1_0_DEFVAL 0x40200204 -#define DDR_PHY_DX8GCR0_RESERVED_1_0_SHIFT 0 -#define DDR_PHY_DX8GCR0_RESERVED_1_0_MASK 0x00000003U +#define DDR_PHY_DX8GCR0_RESERVED_1_0_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_RESERVED_1_0_SHIFT 0 +#define DDR_PHY_DX8GCR0_RESERVED_1_0_MASK 0x00000003U -/*Enables the PDR mode for DQ[7:0]*/ +/* +* Enables the PDR mode for DQ[7:0] +*/ #undef DDR_PHY_DX8GCR1_DXPDRMODE_DEFVAL #undef DDR_PHY_DX8GCR1_DXPDRMODE_SHIFT #undef DDR_PHY_DX8GCR1_DXPDRMODE_MASK -#define DDR_PHY_DX8GCR1_DXPDRMODE_DEFVAL 0x00007FFF -#define DDR_PHY_DX8GCR1_DXPDRMODE_SHIFT 16 -#define DDR_PHY_DX8GCR1_DXPDRMODE_MASK 0xFFFF0000U +#define DDR_PHY_DX8GCR1_DXPDRMODE_DEFVAL 0x00007FFF +#define DDR_PHY_DX8GCR1_DXPDRMODE_SHIFT 16 +#define DDR_PHY_DX8GCR1_DXPDRMODE_MASK 0xFFFF0000U -/*Reserved. Returns zeroes on reads.*/ +/* +* Reserved. Returns zeroes on reads. +*/ #undef DDR_PHY_DX8GCR1_RESERVED_15_DEFVAL #undef DDR_PHY_DX8GCR1_RESERVED_15_SHIFT #undef DDR_PHY_DX8GCR1_RESERVED_15_MASK -#define DDR_PHY_DX8GCR1_RESERVED_15_DEFVAL 0x00007FFF -#define DDR_PHY_DX8GCR1_RESERVED_15_SHIFT 15 -#define DDR_PHY_DX8GCR1_RESERVED_15_MASK 0x00008000U +#define DDR_PHY_DX8GCR1_RESERVED_15_DEFVAL 0x00007FFF +#define DDR_PHY_DX8GCR1_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX8GCR1_RESERVED_15_MASK 0x00008000U -/*Select the delayed or non-delayed read data strobe #*/ +/* +* Select the delayed or non-delayed read data strobe # +*/ #undef DDR_PHY_DX8GCR1_QSNSEL_DEFVAL #undef DDR_PHY_DX8GCR1_QSNSEL_SHIFT #undef DDR_PHY_DX8GCR1_QSNSEL_MASK -#define DDR_PHY_DX8GCR1_QSNSEL_DEFVAL 0x00007FFF -#define DDR_PHY_DX8GCR1_QSNSEL_SHIFT 14 -#define DDR_PHY_DX8GCR1_QSNSEL_MASK 0x00004000U +#define DDR_PHY_DX8GCR1_QSNSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX8GCR1_QSNSEL_SHIFT 14 +#define DDR_PHY_DX8GCR1_QSNSEL_MASK 0x00004000U -/*Select the delayed or non-delayed read data strobe*/ +/* +* Select the delayed or non-delayed read data strobe +*/ #undef DDR_PHY_DX8GCR1_QSSEL_DEFVAL #undef DDR_PHY_DX8GCR1_QSSEL_SHIFT #undef DDR_PHY_DX8GCR1_QSSEL_MASK -#define DDR_PHY_DX8GCR1_QSSEL_DEFVAL 0x00007FFF -#define DDR_PHY_DX8GCR1_QSSEL_SHIFT 13 -#define DDR_PHY_DX8GCR1_QSSEL_MASK 0x00002000U +#define DDR_PHY_DX8GCR1_QSSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX8GCR1_QSSEL_SHIFT 13 +#define DDR_PHY_DX8GCR1_QSSEL_MASK 0x00002000U -/*Enables Read Data Strobe in a byte lane*/ +/* +* Enables Read Data Strobe in a byte lane +*/ #undef DDR_PHY_DX8GCR1_OEEN_DEFVAL #undef DDR_PHY_DX8GCR1_OEEN_SHIFT #undef DDR_PHY_DX8GCR1_OEEN_MASK -#define DDR_PHY_DX8GCR1_OEEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX8GCR1_OEEN_SHIFT 12 -#define DDR_PHY_DX8GCR1_OEEN_MASK 0x00001000U +#define DDR_PHY_DX8GCR1_OEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX8GCR1_OEEN_SHIFT 12 +#define DDR_PHY_DX8GCR1_OEEN_MASK 0x00001000U -/*Enables PDR in a byte lane*/ +/* +* Enables PDR in a byte lane +*/ #undef DDR_PHY_DX8GCR1_PDREN_DEFVAL #undef DDR_PHY_DX8GCR1_PDREN_SHIFT #undef DDR_PHY_DX8GCR1_PDREN_MASK -#define DDR_PHY_DX8GCR1_PDREN_DEFVAL 0x00007FFF -#define DDR_PHY_DX8GCR1_PDREN_SHIFT 11 -#define DDR_PHY_DX8GCR1_PDREN_MASK 0x00000800U +#define DDR_PHY_DX8GCR1_PDREN_DEFVAL 0x00007FFF +#define DDR_PHY_DX8GCR1_PDREN_SHIFT 11 +#define DDR_PHY_DX8GCR1_PDREN_MASK 0x00000800U -/*Enables ODT/TE in a byte lane*/ +/* +* Enables ODT/TE in a byte lane +*/ #undef DDR_PHY_DX8GCR1_TEEN_DEFVAL #undef DDR_PHY_DX8GCR1_TEEN_SHIFT #undef DDR_PHY_DX8GCR1_TEEN_MASK -#define DDR_PHY_DX8GCR1_TEEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX8GCR1_TEEN_SHIFT 10 -#define DDR_PHY_DX8GCR1_TEEN_MASK 0x00000400U +#define DDR_PHY_DX8GCR1_TEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX8GCR1_TEEN_SHIFT 10 +#define DDR_PHY_DX8GCR1_TEEN_MASK 0x00000400U -/*Enables Write Data strobe in a byte lane*/ +/* +* Enables Write Data strobe in a byte lane +*/ #undef DDR_PHY_DX8GCR1_DSEN_DEFVAL #undef DDR_PHY_DX8GCR1_DSEN_SHIFT #undef DDR_PHY_DX8GCR1_DSEN_MASK -#define DDR_PHY_DX8GCR1_DSEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX8GCR1_DSEN_SHIFT 9 -#define DDR_PHY_DX8GCR1_DSEN_MASK 0x00000200U +#define DDR_PHY_DX8GCR1_DSEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX8GCR1_DSEN_SHIFT 9 +#define DDR_PHY_DX8GCR1_DSEN_MASK 0x00000200U -/*Enables DM pin in a byte lane*/ +/* +* Enables DM pin in a byte lane +*/ #undef DDR_PHY_DX8GCR1_DMEN_DEFVAL #undef DDR_PHY_DX8GCR1_DMEN_SHIFT #undef DDR_PHY_DX8GCR1_DMEN_MASK -#define DDR_PHY_DX8GCR1_DMEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX8GCR1_DMEN_SHIFT 8 -#define DDR_PHY_DX8GCR1_DMEN_MASK 0x00000100U +#define DDR_PHY_DX8GCR1_DMEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX8GCR1_DMEN_SHIFT 8 +#define DDR_PHY_DX8GCR1_DMEN_MASK 0x00000100U -/*Enables DQ corresponding to each bit in a byte*/ +/* +* Enables DQ corresponding to each bit in a byte +*/ #undef DDR_PHY_DX8GCR1_DQEN_DEFVAL #undef DDR_PHY_DX8GCR1_DQEN_SHIFT #undef DDR_PHY_DX8GCR1_DQEN_MASK -#define DDR_PHY_DX8GCR1_DQEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX8GCR1_DQEN_SHIFT 0 -#define DDR_PHY_DX8GCR1_DQEN_MASK 0x000000FFU +#define DDR_PHY_DX8GCR1_DQEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX8GCR1_DQEN_SHIFT 0 +#define DDR_PHY_DX8GCR1_DQEN_MASK 0x000000FFU -/*Byte lane VREF IOM (Used only by D4MU IOs)*/ +/* +* Byte lane VREF IOM (Used only by D4MU IOs) +*/ #undef DDR_PHY_DX8GCR4_RESERVED_31_29_DEFVAL #undef DDR_PHY_DX8GCR4_RESERVED_31_29_SHIFT #undef DDR_PHY_DX8GCR4_RESERVED_31_29_MASK -#define DDR_PHY_DX8GCR4_RESERVED_31_29_DEFVAL 0x0E00003C -#define DDR_PHY_DX8GCR4_RESERVED_31_29_SHIFT 29 -#define DDR_PHY_DX8GCR4_RESERVED_31_29_MASK 0xE0000000U +#define DDR_PHY_DX8GCR4_RESERVED_31_29_DEFVAL 0x0E00003C +#define DDR_PHY_DX8GCR4_RESERVED_31_29_SHIFT 29 +#define DDR_PHY_DX8GCR4_RESERVED_31_29_MASK 0xE0000000U -/*Byte Lane VREF Pad Enable*/ +/* +* Byte Lane VREF Pad Enable +*/ #undef DDR_PHY_DX8GCR4_DXREFPEN_DEFVAL #undef DDR_PHY_DX8GCR4_DXREFPEN_SHIFT #undef DDR_PHY_DX8GCR4_DXREFPEN_MASK -#define DDR_PHY_DX8GCR4_DXREFPEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX8GCR4_DXREFPEN_SHIFT 28 -#define DDR_PHY_DX8GCR4_DXREFPEN_MASK 0x10000000U +#define DDR_PHY_DX8GCR4_DXREFPEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX8GCR4_DXREFPEN_SHIFT 28 +#define DDR_PHY_DX8GCR4_DXREFPEN_MASK 0x10000000U -/*Byte Lane Internal VREF Enable*/ +/* +* Byte Lane Internal VREF Enable +*/ #undef DDR_PHY_DX8GCR4_DXREFEEN_DEFVAL #undef DDR_PHY_DX8GCR4_DXREFEEN_SHIFT #undef DDR_PHY_DX8GCR4_DXREFEEN_MASK -#define DDR_PHY_DX8GCR4_DXREFEEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX8GCR4_DXREFEEN_SHIFT 26 -#define DDR_PHY_DX8GCR4_DXREFEEN_MASK 0x0C000000U +#define DDR_PHY_DX8GCR4_DXREFEEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX8GCR4_DXREFEEN_SHIFT 26 +#define DDR_PHY_DX8GCR4_DXREFEEN_MASK 0x0C000000U -/*Byte Lane Single-End VREF Enable*/ +/* +* Byte Lane Single-End VREF Enable +*/ #undef DDR_PHY_DX8GCR4_DXREFSEN_DEFVAL #undef DDR_PHY_DX8GCR4_DXREFSEN_SHIFT #undef DDR_PHY_DX8GCR4_DXREFSEN_MASK -#define DDR_PHY_DX8GCR4_DXREFSEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX8GCR4_DXREFSEN_SHIFT 25 -#define DDR_PHY_DX8GCR4_DXREFSEN_MASK 0x02000000U +#define DDR_PHY_DX8GCR4_DXREFSEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX8GCR4_DXREFSEN_SHIFT 25 +#define DDR_PHY_DX8GCR4_DXREFSEN_MASK 0x02000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX8GCR4_RESERVED_24_DEFVAL #undef DDR_PHY_DX8GCR4_RESERVED_24_SHIFT #undef DDR_PHY_DX8GCR4_RESERVED_24_MASK -#define DDR_PHY_DX8GCR4_RESERVED_24_DEFVAL 0x0E00003C -#define DDR_PHY_DX8GCR4_RESERVED_24_SHIFT 24 -#define DDR_PHY_DX8GCR4_RESERVED_24_MASK 0x01000000U +#define DDR_PHY_DX8GCR4_RESERVED_24_DEFVAL 0x0E00003C +#define DDR_PHY_DX8GCR4_RESERVED_24_SHIFT 24 +#define DDR_PHY_DX8GCR4_RESERVED_24_MASK 0x01000000U -/*External VREF generator REFSEL range select*/ +/* +* External VREF generator REFSEL range select +*/ #undef DDR_PHY_DX8GCR4_DXREFESELRANGE_DEFVAL #undef DDR_PHY_DX8GCR4_DXREFESELRANGE_SHIFT #undef DDR_PHY_DX8GCR4_DXREFESELRANGE_MASK -#define DDR_PHY_DX8GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C -#define DDR_PHY_DX8GCR4_DXREFESELRANGE_SHIFT 23 -#define DDR_PHY_DX8GCR4_DXREFESELRANGE_MASK 0x00800000U +#define DDR_PHY_DX8GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX8GCR4_DXREFESELRANGE_SHIFT 23 +#define DDR_PHY_DX8GCR4_DXREFESELRANGE_MASK 0x00800000U -/*Byte Lane External VREF Select*/ +/* +* Byte Lane External VREF Select +*/ #undef DDR_PHY_DX8GCR4_DXREFESEL_DEFVAL #undef DDR_PHY_DX8GCR4_DXREFESEL_SHIFT #undef DDR_PHY_DX8GCR4_DXREFESEL_MASK -#define DDR_PHY_DX8GCR4_DXREFESEL_DEFVAL 0x0E00003C -#define DDR_PHY_DX8GCR4_DXREFESEL_SHIFT 16 -#define DDR_PHY_DX8GCR4_DXREFESEL_MASK 0x007F0000U +#define DDR_PHY_DX8GCR4_DXREFESEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX8GCR4_DXREFESEL_SHIFT 16 +#define DDR_PHY_DX8GCR4_DXREFESEL_MASK 0x007F0000U -/*Single ended VREF generator REFSEL range select*/ +/* +* Single ended VREF generator REFSEL range select +*/ #undef DDR_PHY_DX8GCR4_DXREFSSELRANGE_DEFVAL #undef DDR_PHY_DX8GCR4_DXREFSSELRANGE_SHIFT #undef DDR_PHY_DX8GCR4_DXREFSSELRANGE_MASK -#define DDR_PHY_DX8GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C -#define DDR_PHY_DX8GCR4_DXREFSSELRANGE_SHIFT 15 -#define DDR_PHY_DX8GCR4_DXREFSSELRANGE_MASK 0x00008000U +#define DDR_PHY_DX8GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX8GCR4_DXREFSSELRANGE_SHIFT 15 +#define DDR_PHY_DX8GCR4_DXREFSSELRANGE_MASK 0x00008000U -/*Byte Lane Single-End VREF Select*/ +/* +* Byte Lane Single-End VREF Select +*/ #undef DDR_PHY_DX8GCR4_DXREFSSEL_DEFVAL #undef DDR_PHY_DX8GCR4_DXREFSSEL_SHIFT #undef DDR_PHY_DX8GCR4_DXREFSSEL_MASK -#define DDR_PHY_DX8GCR4_DXREFSSEL_DEFVAL 0x0E00003C -#define DDR_PHY_DX8GCR4_DXREFSSEL_SHIFT 8 -#define DDR_PHY_DX8GCR4_DXREFSSEL_MASK 0x00007F00U +#define DDR_PHY_DX8GCR4_DXREFSSEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX8GCR4_DXREFSSEL_SHIFT 8 +#define DDR_PHY_DX8GCR4_DXREFSSEL_MASK 0x00007F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX8GCR4_RESERVED_7_6_DEFVAL #undef DDR_PHY_DX8GCR4_RESERVED_7_6_SHIFT #undef DDR_PHY_DX8GCR4_RESERVED_7_6_MASK -#define DDR_PHY_DX8GCR4_RESERVED_7_6_DEFVAL 0x0E00003C -#define DDR_PHY_DX8GCR4_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_DX8GCR4_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_DX8GCR4_RESERVED_7_6_DEFVAL 0x0E00003C +#define DDR_PHY_DX8GCR4_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX8GCR4_RESERVED_7_6_MASK 0x000000C0U -/*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/ +/* +* VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. +*/ #undef DDR_PHY_DX8GCR4_DXREFIEN_DEFVAL #undef DDR_PHY_DX8GCR4_DXREFIEN_SHIFT #undef DDR_PHY_DX8GCR4_DXREFIEN_MASK -#define DDR_PHY_DX8GCR4_DXREFIEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX8GCR4_DXREFIEN_SHIFT 2 -#define DDR_PHY_DX8GCR4_DXREFIEN_MASK 0x0000003CU +#define DDR_PHY_DX8GCR4_DXREFIEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX8GCR4_DXREFIEN_SHIFT 2 +#define DDR_PHY_DX8GCR4_DXREFIEN_MASK 0x0000003CU -/*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/ +/* +* VRMON control for DQ IO (Single Ended) buffers of a byte lane. +*/ #undef DDR_PHY_DX8GCR4_DXREFIMON_DEFVAL #undef DDR_PHY_DX8GCR4_DXREFIMON_SHIFT #undef DDR_PHY_DX8GCR4_DXREFIMON_MASK -#define DDR_PHY_DX8GCR4_DXREFIMON_DEFVAL 0x0E00003C -#define DDR_PHY_DX8GCR4_DXREFIMON_SHIFT 0 -#define DDR_PHY_DX8GCR4_DXREFIMON_MASK 0x00000003U +#define DDR_PHY_DX8GCR4_DXREFIMON_DEFVAL 0x0E00003C +#define DDR_PHY_DX8GCR4_DXREFIMON_SHIFT 0 +#define DDR_PHY_DX8GCR4_DXREFIMON_MASK 0x00000003U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX8GCR5_RESERVED_31_DEFVAL #undef DDR_PHY_DX8GCR5_RESERVED_31_SHIFT #undef DDR_PHY_DX8GCR5_RESERVED_31_MASK -#define DDR_PHY_DX8GCR5_RESERVED_31_DEFVAL 0x09090909 -#define DDR_PHY_DX8GCR5_RESERVED_31_SHIFT 31 -#define DDR_PHY_DX8GCR5_RESERVED_31_MASK 0x80000000U +#define DDR_PHY_DX8GCR5_RESERVED_31_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR5_RESERVED_31_SHIFT 31 +#define DDR_PHY_DX8GCR5_RESERVED_31_MASK 0x80000000U -/*Byte Lane internal VREF Select for Rank 3*/ +/* +* Byte Lane internal VREF Select for Rank 3 +*/ #undef DDR_PHY_DX8GCR5_DXREFISELR3_DEFVAL #undef DDR_PHY_DX8GCR5_DXREFISELR3_SHIFT #undef DDR_PHY_DX8GCR5_DXREFISELR3_MASK -#define DDR_PHY_DX8GCR5_DXREFISELR3_DEFVAL 0x09090909 -#define DDR_PHY_DX8GCR5_DXREFISELR3_SHIFT 24 -#define DDR_PHY_DX8GCR5_DXREFISELR3_MASK 0x7F000000U +#define DDR_PHY_DX8GCR5_DXREFISELR3_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR5_DXREFISELR3_SHIFT 24 +#define DDR_PHY_DX8GCR5_DXREFISELR3_MASK 0x7F000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX8GCR5_RESERVED_23_DEFVAL #undef DDR_PHY_DX8GCR5_RESERVED_23_SHIFT #undef DDR_PHY_DX8GCR5_RESERVED_23_MASK -#define DDR_PHY_DX8GCR5_RESERVED_23_DEFVAL 0x09090909 -#define DDR_PHY_DX8GCR5_RESERVED_23_SHIFT 23 -#define DDR_PHY_DX8GCR5_RESERVED_23_MASK 0x00800000U +#define DDR_PHY_DX8GCR5_RESERVED_23_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR5_RESERVED_23_SHIFT 23 +#define DDR_PHY_DX8GCR5_RESERVED_23_MASK 0x00800000U -/*Byte Lane internal VREF Select for Rank 2*/ +/* +* Byte Lane internal VREF Select for Rank 2 +*/ #undef DDR_PHY_DX8GCR5_DXREFISELR2_DEFVAL #undef DDR_PHY_DX8GCR5_DXREFISELR2_SHIFT #undef DDR_PHY_DX8GCR5_DXREFISELR2_MASK -#define DDR_PHY_DX8GCR5_DXREFISELR2_DEFVAL 0x09090909 -#define DDR_PHY_DX8GCR5_DXREFISELR2_SHIFT 16 -#define DDR_PHY_DX8GCR5_DXREFISELR2_MASK 0x007F0000U +#define DDR_PHY_DX8GCR5_DXREFISELR2_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR5_DXREFISELR2_SHIFT 16 +#define DDR_PHY_DX8GCR5_DXREFISELR2_MASK 0x007F0000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX8GCR5_RESERVED_15_DEFVAL #undef DDR_PHY_DX8GCR5_RESERVED_15_SHIFT #undef DDR_PHY_DX8GCR5_RESERVED_15_MASK -#define DDR_PHY_DX8GCR5_RESERVED_15_DEFVAL 0x09090909 -#define DDR_PHY_DX8GCR5_RESERVED_15_SHIFT 15 -#define DDR_PHY_DX8GCR5_RESERVED_15_MASK 0x00008000U +#define DDR_PHY_DX8GCR5_RESERVED_15_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR5_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX8GCR5_RESERVED_15_MASK 0x00008000U -/*Byte Lane internal VREF Select for Rank 1*/ +/* +* Byte Lane internal VREF Select for Rank 1 +*/ #undef DDR_PHY_DX8GCR5_DXREFISELR1_DEFVAL #undef DDR_PHY_DX8GCR5_DXREFISELR1_SHIFT #undef DDR_PHY_DX8GCR5_DXREFISELR1_MASK -#define DDR_PHY_DX8GCR5_DXREFISELR1_DEFVAL 0x09090909 -#define DDR_PHY_DX8GCR5_DXREFISELR1_SHIFT 8 -#define DDR_PHY_DX8GCR5_DXREFISELR1_MASK 0x00007F00U +#define DDR_PHY_DX8GCR5_DXREFISELR1_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR5_DXREFISELR1_SHIFT 8 +#define DDR_PHY_DX8GCR5_DXREFISELR1_MASK 0x00007F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX8GCR5_RESERVED_7_DEFVAL #undef DDR_PHY_DX8GCR5_RESERVED_7_SHIFT #undef DDR_PHY_DX8GCR5_RESERVED_7_MASK -#define DDR_PHY_DX8GCR5_RESERVED_7_DEFVAL 0x09090909 -#define DDR_PHY_DX8GCR5_RESERVED_7_SHIFT 7 -#define DDR_PHY_DX8GCR5_RESERVED_7_MASK 0x00000080U +#define DDR_PHY_DX8GCR5_RESERVED_7_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR5_RESERVED_7_SHIFT 7 +#define DDR_PHY_DX8GCR5_RESERVED_7_MASK 0x00000080U -/*Byte Lane internal VREF Select for Rank 0*/ +/* +* Byte Lane internal VREF Select for Rank 0 +*/ #undef DDR_PHY_DX8GCR5_DXREFISELR0_DEFVAL #undef DDR_PHY_DX8GCR5_DXREFISELR0_SHIFT #undef DDR_PHY_DX8GCR5_DXREFISELR0_MASK -#define DDR_PHY_DX8GCR5_DXREFISELR0_DEFVAL 0x09090909 -#define DDR_PHY_DX8GCR5_DXREFISELR0_SHIFT 0 -#define DDR_PHY_DX8GCR5_DXREFISELR0_MASK 0x0000007FU +#define DDR_PHY_DX8GCR5_DXREFISELR0_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR5_DXREFISELR0_SHIFT 0 +#define DDR_PHY_DX8GCR5_DXREFISELR0_MASK 0x0000007FU -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX8GCR6_RESERVED_31_30_DEFVAL #undef DDR_PHY_DX8GCR6_RESERVED_31_30_SHIFT #undef DDR_PHY_DX8GCR6_RESERVED_31_30_MASK -#define DDR_PHY_DX8GCR6_RESERVED_31_30_DEFVAL 0x09090909 -#define DDR_PHY_DX8GCR6_RESERVED_31_30_SHIFT 30 -#define DDR_PHY_DX8GCR6_RESERVED_31_30_MASK 0xC0000000U +#define DDR_PHY_DX8GCR6_RESERVED_31_30_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR6_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX8GCR6_RESERVED_31_30_MASK 0xC0000000U -/*DRAM DQ VREF Select for Rank3*/ +/* +* DRAM DQ VREF Select for Rank3 +*/ #undef DDR_PHY_DX8GCR6_DXDQVREFR3_DEFVAL #undef DDR_PHY_DX8GCR6_DXDQVREFR3_SHIFT #undef DDR_PHY_DX8GCR6_DXDQVREFR3_MASK -#define DDR_PHY_DX8GCR6_DXDQVREFR3_DEFVAL 0x09090909 -#define DDR_PHY_DX8GCR6_DXDQVREFR3_SHIFT 24 -#define DDR_PHY_DX8GCR6_DXDQVREFR3_MASK 0x3F000000U +#define DDR_PHY_DX8GCR6_DXDQVREFR3_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR6_DXDQVREFR3_SHIFT 24 +#define DDR_PHY_DX8GCR6_DXDQVREFR3_MASK 0x3F000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX8GCR6_RESERVED_23_22_DEFVAL #undef DDR_PHY_DX8GCR6_RESERVED_23_22_SHIFT #undef DDR_PHY_DX8GCR6_RESERVED_23_22_MASK -#define DDR_PHY_DX8GCR6_RESERVED_23_22_DEFVAL 0x09090909 -#define DDR_PHY_DX8GCR6_RESERVED_23_22_SHIFT 22 -#define DDR_PHY_DX8GCR6_RESERVED_23_22_MASK 0x00C00000U +#define DDR_PHY_DX8GCR6_RESERVED_23_22_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR6_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX8GCR6_RESERVED_23_22_MASK 0x00C00000U -/*DRAM DQ VREF Select for Rank2*/ +/* +* DRAM DQ VREF Select for Rank2 +*/ #undef DDR_PHY_DX8GCR6_DXDQVREFR2_DEFVAL #undef DDR_PHY_DX8GCR6_DXDQVREFR2_SHIFT #undef DDR_PHY_DX8GCR6_DXDQVREFR2_MASK -#define DDR_PHY_DX8GCR6_DXDQVREFR2_DEFVAL 0x09090909 -#define DDR_PHY_DX8GCR6_DXDQVREFR2_SHIFT 16 -#define DDR_PHY_DX8GCR6_DXDQVREFR2_MASK 0x003F0000U +#define DDR_PHY_DX8GCR6_DXDQVREFR2_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR6_DXDQVREFR2_SHIFT 16 +#define DDR_PHY_DX8GCR6_DXDQVREFR2_MASK 0x003F0000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX8GCR6_RESERVED_15_14_DEFVAL #undef DDR_PHY_DX8GCR6_RESERVED_15_14_SHIFT #undef DDR_PHY_DX8GCR6_RESERVED_15_14_MASK -#define DDR_PHY_DX8GCR6_RESERVED_15_14_DEFVAL 0x09090909 -#define DDR_PHY_DX8GCR6_RESERVED_15_14_SHIFT 14 -#define DDR_PHY_DX8GCR6_RESERVED_15_14_MASK 0x0000C000U +#define DDR_PHY_DX8GCR6_RESERVED_15_14_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR6_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_DX8GCR6_RESERVED_15_14_MASK 0x0000C000U -/*DRAM DQ VREF Select for Rank1*/ +/* +* DRAM DQ VREF Select for Rank1 +*/ #undef DDR_PHY_DX8GCR6_DXDQVREFR1_DEFVAL #undef DDR_PHY_DX8GCR6_DXDQVREFR1_SHIFT #undef DDR_PHY_DX8GCR6_DXDQVREFR1_MASK -#define DDR_PHY_DX8GCR6_DXDQVREFR1_DEFVAL 0x09090909 -#define DDR_PHY_DX8GCR6_DXDQVREFR1_SHIFT 8 -#define DDR_PHY_DX8GCR6_DXDQVREFR1_MASK 0x00003F00U +#define DDR_PHY_DX8GCR6_DXDQVREFR1_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR6_DXDQVREFR1_SHIFT 8 +#define DDR_PHY_DX8GCR6_DXDQVREFR1_MASK 0x00003F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX8GCR6_RESERVED_7_6_DEFVAL #undef DDR_PHY_DX8GCR6_RESERVED_7_6_SHIFT #undef DDR_PHY_DX8GCR6_RESERVED_7_6_MASK -#define DDR_PHY_DX8GCR6_RESERVED_7_6_DEFVAL 0x09090909 -#define DDR_PHY_DX8GCR6_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_DX8GCR6_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_DX8GCR6_RESERVED_7_6_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR6_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX8GCR6_RESERVED_7_6_MASK 0x000000C0U -/*DRAM DQ VREF Select for Rank0*/ +/* +* DRAM DQ VREF Select for Rank0 +*/ #undef DDR_PHY_DX8GCR6_DXDQVREFR0_DEFVAL #undef DDR_PHY_DX8GCR6_DXDQVREFR0_SHIFT #undef DDR_PHY_DX8GCR6_DXDQVREFR0_MASK -#define DDR_PHY_DX8GCR6_DXDQVREFR0_DEFVAL 0x09090909 -#define DDR_PHY_DX8GCR6_DXDQVREFR0_SHIFT 0 -#define DDR_PHY_DX8GCR6_DXDQVREFR0_MASK 0x0000003FU +#define DDR_PHY_DX8GCR6_DXDQVREFR0_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR6_DXDQVREFR0_SHIFT 0 +#define DDR_PHY_DX8GCR6_DXDQVREFR0_MASK 0x0000003FU -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX8LCDLR2_RESERVED_31_25_DEFVAL -#undef DDR_PHY_DX8LCDLR2_RESERVED_31_25_SHIFT -#undef DDR_PHY_DX8LCDLR2_RESERVED_31_25_MASK -#define DDR_PHY_DX8LCDLR2_RESERVED_31_25_DEFVAL 0x00000000 -#define DDR_PHY_DX8LCDLR2_RESERVED_31_25_SHIFT 25 -#define DDR_PHY_DX8LCDLR2_RESERVED_31_25_MASK 0xFE000000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX8LCDLR2_RESERVED_24_16_DEFVAL -#undef DDR_PHY_DX8LCDLR2_RESERVED_24_16_SHIFT -#undef DDR_PHY_DX8LCDLR2_RESERVED_24_16_MASK -#define DDR_PHY_DX8LCDLR2_RESERVED_24_16_DEFVAL 0x00000000 -#define DDR_PHY_DX8LCDLR2_RESERVED_24_16_SHIFT 16 -#define DDR_PHY_DX8LCDLR2_RESERVED_24_16_MASK 0x01FF0000U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX8LCDLR2_RESERVED_15_9_DEFVAL -#undef DDR_PHY_DX8LCDLR2_RESERVED_15_9_SHIFT -#undef DDR_PHY_DX8LCDLR2_RESERVED_15_9_MASK -#define DDR_PHY_DX8LCDLR2_RESERVED_15_9_DEFVAL 0x00000000 -#define DDR_PHY_DX8LCDLR2_RESERVED_15_9_SHIFT 9 -#define DDR_PHY_DX8LCDLR2_RESERVED_15_9_MASK 0x0000FE00U - -/*Read DQS Gating Delay*/ -#undef DDR_PHY_DX8LCDLR2_DQSGD_DEFVAL -#undef DDR_PHY_DX8LCDLR2_DQSGD_SHIFT -#undef DDR_PHY_DX8LCDLR2_DQSGD_MASK -#define DDR_PHY_DX8LCDLR2_DQSGD_DEFVAL 0x00000000 -#define DDR_PHY_DX8LCDLR2_DQSGD_SHIFT 0 -#define DDR_PHY_DX8LCDLR2_DQSGD_MASK 0x000001FFU - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX8GTR0_RESERVED_31_24_DEFVAL -#undef DDR_PHY_DX8GTR0_RESERVED_31_24_SHIFT -#undef DDR_PHY_DX8GTR0_RESERVED_31_24_MASK -#define DDR_PHY_DX8GTR0_RESERVED_31_24_DEFVAL 0x00020000 -#define DDR_PHY_DX8GTR0_RESERVED_31_24_SHIFT 27 -#define DDR_PHY_DX8GTR0_RESERVED_31_24_MASK 0xF8000000U - -/*DQ Write Path Latency Pipeline*/ -#undef DDR_PHY_DX8GTR0_WDQSL_DEFVAL -#undef DDR_PHY_DX8GTR0_WDQSL_SHIFT -#undef DDR_PHY_DX8GTR0_WDQSL_MASK -#define DDR_PHY_DX8GTR0_WDQSL_DEFVAL 0x00020000 -#define DDR_PHY_DX8GTR0_WDQSL_SHIFT 24 -#define DDR_PHY_DX8GTR0_WDQSL_MASK 0x07000000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX8GTR0_RESERVED_23_20_DEFVAL -#undef DDR_PHY_DX8GTR0_RESERVED_23_20_SHIFT -#undef DDR_PHY_DX8GTR0_RESERVED_23_20_MASK -#define DDR_PHY_DX8GTR0_RESERVED_23_20_DEFVAL 0x00020000 -#define DDR_PHY_DX8GTR0_RESERVED_23_20_SHIFT 20 -#define DDR_PHY_DX8GTR0_RESERVED_23_20_MASK 0x00F00000U - -/*Write Leveling System Latency*/ -#undef DDR_PHY_DX8GTR0_WLSL_DEFVAL -#undef DDR_PHY_DX8GTR0_WLSL_SHIFT -#undef DDR_PHY_DX8GTR0_WLSL_MASK -#define DDR_PHY_DX8GTR0_WLSL_DEFVAL 0x00020000 -#define DDR_PHY_DX8GTR0_WLSL_SHIFT 16 -#define DDR_PHY_DX8GTR0_WLSL_MASK 0x000F0000U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX8GTR0_RESERVED_15_13_DEFVAL -#undef DDR_PHY_DX8GTR0_RESERVED_15_13_SHIFT -#undef DDR_PHY_DX8GTR0_RESERVED_15_13_MASK -#define DDR_PHY_DX8GTR0_RESERVED_15_13_DEFVAL 0x00020000 -#define DDR_PHY_DX8GTR0_RESERVED_15_13_SHIFT 13 -#define DDR_PHY_DX8GTR0_RESERVED_15_13_MASK 0x0000E000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX8GTR0_RESERVED_12_8_DEFVAL -#undef DDR_PHY_DX8GTR0_RESERVED_12_8_SHIFT -#undef DDR_PHY_DX8GTR0_RESERVED_12_8_MASK -#define DDR_PHY_DX8GTR0_RESERVED_12_8_DEFVAL 0x00020000 -#define DDR_PHY_DX8GTR0_RESERVED_12_8_SHIFT 8 -#define DDR_PHY_DX8GTR0_RESERVED_12_8_MASK 0x00001F00U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX8GTR0_RESERVED_7_5_DEFVAL -#undef DDR_PHY_DX8GTR0_RESERVED_7_5_SHIFT -#undef DDR_PHY_DX8GTR0_RESERVED_7_5_MASK -#define DDR_PHY_DX8GTR0_RESERVED_7_5_DEFVAL 0x00020000 -#define DDR_PHY_DX8GTR0_RESERVED_7_5_SHIFT 5 -#define DDR_PHY_DX8GTR0_RESERVED_7_5_MASK 0x000000E0U - -/*DQS Gating System Latency*/ -#undef DDR_PHY_DX8GTR0_DGSL_DEFVAL -#undef DDR_PHY_DX8GTR0_DGSL_SHIFT -#undef DDR_PHY_DX8GTR0_DGSL_MASK -#define DDR_PHY_DX8GTR0_DGSL_DEFVAL 0x00020000 -#define DDR_PHY_DX8GTR0_DGSL_SHIFT 0 -#define DDR_PHY_DX8GTR0_DGSL_MASK 0x0000001FU - -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL0OSC_RESERVED_31_30_DEFVAL #undef DDR_PHY_DX8SL0OSC_RESERVED_31_30_SHIFT #undef DDR_PHY_DX8SL0OSC_RESERVED_31_30_MASK -#define DDR_PHY_DX8SL0OSC_RESERVED_31_30_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL0OSC_RESERVED_31_30_SHIFT 30 -#define DDR_PHY_DX8SL0OSC_RESERVED_31_30_MASK 0xC0000000U +#define DDR_PHY_DX8SL0OSC_RESERVED_31_30_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX8SL0OSC_RESERVED_31_30_MASK 0xC0000000U -/*Enable Clock Gating for DX ddr_clk*/ +/* +* Enable Clock Gating for DX ddr_clk +*/ #undef DDR_PHY_DX8SL0OSC_GATEDXRDCLK_DEFVAL #undef DDR_PHY_DX8SL0OSC_GATEDXRDCLK_SHIFT #undef DDR_PHY_DX8SL0OSC_GATEDXRDCLK_MASK -#define DDR_PHY_DX8SL0OSC_GATEDXRDCLK_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL0OSC_GATEDXRDCLK_SHIFT 28 -#define DDR_PHY_DX8SL0OSC_GATEDXRDCLK_MASK 0x30000000U +#define DDR_PHY_DX8SL0OSC_GATEDXRDCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_GATEDXRDCLK_SHIFT 28 +#define DDR_PHY_DX8SL0OSC_GATEDXRDCLK_MASK 0x30000000U -/*Enable Clock Gating for DX ctl_rd_clk*/ +/* +* Enable Clock Gating for DX ctl_rd_clk +*/ #undef DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_DEFVAL #undef DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_SHIFT #undef DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_MASK -#define DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_SHIFT 26 -#define DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_MASK 0x0C000000U +#define DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_SHIFT 26 +#define DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_MASK 0x0C000000U -/*Enable Clock Gating for DX ctl_clk*/ +/* +* Enable Clock Gating for DX ctl_clk +*/ #undef DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_DEFVAL #undef DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_SHIFT #undef DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_MASK -#define DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_SHIFT 24 -#define DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_MASK 0x03000000U +#define DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_SHIFT 24 +#define DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_MASK 0x03000000U -/*Selects the level to which clocks will be stalled when clock gating is enabled.*/ +/* +* Selects the level to which clocks will be stalled when clock gating is e + * nabled. +*/ #undef DDR_PHY_DX8SL0OSC_CLKLEVEL_DEFVAL #undef DDR_PHY_DX8SL0OSC_CLKLEVEL_SHIFT #undef DDR_PHY_DX8SL0OSC_CLKLEVEL_MASK -#define DDR_PHY_DX8SL0OSC_CLKLEVEL_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL0OSC_CLKLEVEL_SHIFT 22 -#define DDR_PHY_DX8SL0OSC_CLKLEVEL_MASK 0x00C00000U +#define DDR_PHY_DX8SL0OSC_CLKLEVEL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_CLKLEVEL_SHIFT 22 +#define DDR_PHY_DX8SL0OSC_CLKLEVEL_MASK 0x00C00000U -/*Loopback Mode*/ +/* +* Loopback Mode +*/ #undef DDR_PHY_DX8SL0OSC_LBMODE_DEFVAL #undef DDR_PHY_DX8SL0OSC_LBMODE_SHIFT #undef DDR_PHY_DX8SL0OSC_LBMODE_MASK -#define DDR_PHY_DX8SL0OSC_LBMODE_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL0OSC_LBMODE_SHIFT 21 -#define DDR_PHY_DX8SL0OSC_LBMODE_MASK 0x00200000U +#define DDR_PHY_DX8SL0OSC_LBMODE_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_LBMODE_SHIFT 21 +#define DDR_PHY_DX8SL0OSC_LBMODE_MASK 0x00200000U -/*Load GSDQS LCDL with 2x the calibrated GSDQSPRD value*/ +/* +* Load GSDQS LCDL with 2x the calibrated GSDQSPRD value +*/ #undef DDR_PHY_DX8SL0OSC_LBGSDQS_DEFVAL #undef DDR_PHY_DX8SL0OSC_LBGSDQS_SHIFT #undef DDR_PHY_DX8SL0OSC_LBGSDQS_MASK -#define DDR_PHY_DX8SL0OSC_LBGSDQS_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL0OSC_LBGSDQS_SHIFT 20 -#define DDR_PHY_DX8SL0OSC_LBGSDQS_MASK 0x00100000U +#define DDR_PHY_DX8SL0OSC_LBGSDQS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_LBGSDQS_SHIFT 20 +#define DDR_PHY_DX8SL0OSC_LBGSDQS_MASK 0x00100000U -/*Loopback DQS Gating*/ +/* +* Loopback DQS Gating +*/ #undef DDR_PHY_DX8SL0OSC_LBGDQS_DEFVAL #undef DDR_PHY_DX8SL0OSC_LBGDQS_SHIFT #undef DDR_PHY_DX8SL0OSC_LBGDQS_MASK -#define DDR_PHY_DX8SL0OSC_LBGDQS_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL0OSC_LBGDQS_SHIFT 18 -#define DDR_PHY_DX8SL0OSC_LBGDQS_MASK 0x000C0000U +#define DDR_PHY_DX8SL0OSC_LBGDQS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_LBGDQS_SHIFT 18 +#define DDR_PHY_DX8SL0OSC_LBGDQS_MASK 0x000C0000U -/*Loopback DQS Shift*/ +/* +* Loopback DQS Shift +*/ #undef DDR_PHY_DX8SL0OSC_LBDQSS_DEFVAL #undef DDR_PHY_DX8SL0OSC_LBDQSS_SHIFT #undef DDR_PHY_DX8SL0OSC_LBDQSS_MASK -#define DDR_PHY_DX8SL0OSC_LBDQSS_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL0OSC_LBDQSS_SHIFT 17 -#define DDR_PHY_DX8SL0OSC_LBDQSS_MASK 0x00020000U +#define DDR_PHY_DX8SL0OSC_LBDQSS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_LBDQSS_SHIFT 17 +#define DDR_PHY_DX8SL0OSC_LBDQSS_MASK 0x00020000U -/*PHY High-Speed Reset*/ +/* +* PHY High-Speed Reset +*/ #undef DDR_PHY_DX8SL0OSC_PHYHRST_DEFVAL #undef DDR_PHY_DX8SL0OSC_PHYHRST_SHIFT #undef DDR_PHY_DX8SL0OSC_PHYHRST_MASK -#define DDR_PHY_DX8SL0OSC_PHYHRST_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL0OSC_PHYHRST_SHIFT 16 -#define DDR_PHY_DX8SL0OSC_PHYHRST_MASK 0x00010000U +#define DDR_PHY_DX8SL0OSC_PHYHRST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_PHYHRST_SHIFT 16 +#define DDR_PHY_DX8SL0OSC_PHYHRST_MASK 0x00010000U -/*PHY FIFO Reset*/ +/* +* PHY FIFO Reset +*/ #undef DDR_PHY_DX8SL0OSC_PHYFRST_DEFVAL #undef DDR_PHY_DX8SL0OSC_PHYFRST_SHIFT #undef DDR_PHY_DX8SL0OSC_PHYFRST_MASK -#define DDR_PHY_DX8SL0OSC_PHYFRST_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL0OSC_PHYFRST_SHIFT 15 -#define DDR_PHY_DX8SL0OSC_PHYFRST_MASK 0x00008000U +#define DDR_PHY_DX8SL0OSC_PHYFRST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_PHYFRST_SHIFT 15 +#define DDR_PHY_DX8SL0OSC_PHYFRST_MASK 0x00008000U -/*Delay Line Test Start*/ +/* +* Delay Line Test Start +*/ #undef DDR_PHY_DX8SL0OSC_DLTST_DEFVAL #undef DDR_PHY_DX8SL0OSC_DLTST_SHIFT #undef DDR_PHY_DX8SL0OSC_DLTST_MASK -#define DDR_PHY_DX8SL0OSC_DLTST_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL0OSC_DLTST_SHIFT 14 -#define DDR_PHY_DX8SL0OSC_DLTST_MASK 0x00004000U +#define DDR_PHY_DX8SL0OSC_DLTST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_DLTST_SHIFT 14 +#define DDR_PHY_DX8SL0OSC_DLTST_MASK 0x00004000U -/*Delay Line Test Mode*/ +/* +* Delay Line Test Mode +*/ #undef DDR_PHY_DX8SL0OSC_DLTMODE_DEFVAL #undef DDR_PHY_DX8SL0OSC_DLTMODE_SHIFT #undef DDR_PHY_DX8SL0OSC_DLTMODE_MASK -#define DDR_PHY_DX8SL0OSC_DLTMODE_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL0OSC_DLTMODE_SHIFT 13 -#define DDR_PHY_DX8SL0OSC_DLTMODE_MASK 0x00002000U +#define DDR_PHY_DX8SL0OSC_DLTMODE_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_DLTMODE_SHIFT 13 +#define DDR_PHY_DX8SL0OSC_DLTMODE_MASK 0x00002000U -/*Reserved. Caution, do not write to this register field.*/ +/* +* Reserved. Caution, do not write to this register field. +*/ #undef DDR_PHY_DX8SL0OSC_RESERVED_12_11_DEFVAL #undef DDR_PHY_DX8SL0OSC_RESERVED_12_11_SHIFT #undef DDR_PHY_DX8SL0OSC_RESERVED_12_11_MASK -#define DDR_PHY_DX8SL0OSC_RESERVED_12_11_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL0OSC_RESERVED_12_11_SHIFT 11 -#define DDR_PHY_DX8SL0OSC_RESERVED_12_11_MASK 0x00001800U +#define DDR_PHY_DX8SL0OSC_RESERVED_12_11_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_RESERVED_12_11_SHIFT 11 +#define DDR_PHY_DX8SL0OSC_RESERVED_12_11_MASK 0x00001800U -/*Oscillator Mode Write-Data Delay Line Select*/ +/* +* Oscillator Mode Write-Data Delay Line Select +*/ #undef DDR_PHY_DX8SL0OSC_OSCWDDL_DEFVAL #undef DDR_PHY_DX8SL0OSC_OSCWDDL_SHIFT #undef DDR_PHY_DX8SL0OSC_OSCWDDL_MASK -#define DDR_PHY_DX8SL0OSC_OSCWDDL_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL0OSC_OSCWDDL_SHIFT 9 -#define DDR_PHY_DX8SL0OSC_OSCWDDL_MASK 0x00000600U +#define DDR_PHY_DX8SL0OSC_OSCWDDL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_OSCWDDL_SHIFT 9 +#define DDR_PHY_DX8SL0OSC_OSCWDDL_MASK 0x00000600U -/*Reserved. Caution, do not write to this register field.*/ +/* +* Reserved. Caution, do not write to this register field. +*/ #undef DDR_PHY_DX8SL0OSC_RESERVED_8_7_DEFVAL #undef DDR_PHY_DX8SL0OSC_RESERVED_8_7_SHIFT #undef DDR_PHY_DX8SL0OSC_RESERVED_8_7_MASK -#define DDR_PHY_DX8SL0OSC_RESERVED_8_7_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL0OSC_RESERVED_8_7_SHIFT 7 -#define DDR_PHY_DX8SL0OSC_RESERVED_8_7_MASK 0x00000180U +#define DDR_PHY_DX8SL0OSC_RESERVED_8_7_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_RESERVED_8_7_SHIFT 7 +#define DDR_PHY_DX8SL0OSC_RESERVED_8_7_MASK 0x00000180U -/*Oscillator Mode Write-Leveling Delay Line Select*/ +/* +* Oscillator Mode Write-Leveling Delay Line Select +*/ #undef DDR_PHY_DX8SL0OSC_OSCWDL_DEFVAL #undef DDR_PHY_DX8SL0OSC_OSCWDL_SHIFT #undef DDR_PHY_DX8SL0OSC_OSCWDL_MASK -#define DDR_PHY_DX8SL0OSC_OSCWDL_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL0OSC_OSCWDL_SHIFT 5 -#define DDR_PHY_DX8SL0OSC_OSCWDL_MASK 0x00000060U +#define DDR_PHY_DX8SL0OSC_OSCWDL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_OSCWDL_SHIFT 5 +#define DDR_PHY_DX8SL0OSC_OSCWDL_MASK 0x00000060U -/*Oscillator Mode Division*/ +/* +* Oscillator Mode Division +*/ #undef DDR_PHY_DX8SL0OSC_OSCDIV_DEFVAL #undef DDR_PHY_DX8SL0OSC_OSCDIV_SHIFT #undef DDR_PHY_DX8SL0OSC_OSCDIV_MASK -#define DDR_PHY_DX8SL0OSC_OSCDIV_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL0OSC_OSCDIV_SHIFT 1 -#define DDR_PHY_DX8SL0OSC_OSCDIV_MASK 0x0000001EU +#define DDR_PHY_DX8SL0OSC_OSCDIV_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_OSCDIV_SHIFT 1 +#define DDR_PHY_DX8SL0OSC_OSCDIV_MASK 0x0000001EU -/*Oscillator Enable*/ +/* +* Oscillator Enable +*/ #undef DDR_PHY_DX8SL0OSC_OSCEN_DEFVAL #undef DDR_PHY_DX8SL0OSC_OSCEN_SHIFT #undef DDR_PHY_DX8SL0OSC_OSCEN_MASK -#define DDR_PHY_DX8SL0OSC_OSCEN_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL0OSC_OSCEN_SHIFT 0 -#define DDR_PHY_DX8SL0OSC_OSCEN_MASK 0x00000001U +#define DDR_PHY_DX8SL0OSC_OSCEN_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_OSCEN_SHIFT 0 +#define DDR_PHY_DX8SL0OSC_OSCEN_MASK 0x00000001U -/*Reserved. Return zeroes on reads.*/ +/* +* PLL Bypass +*/ +#undef DDR_PHY_DX8SL0PLLCR0_PLLBYP_DEFVAL +#undef DDR_PHY_DX8SL0PLLCR0_PLLBYP_SHIFT +#undef DDR_PHY_DX8SL0PLLCR0_PLLBYP_MASK +#define DDR_PHY_DX8SL0PLLCR0_PLLBYP_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL0PLLCR0_PLLBYP_SHIFT 31 +#define DDR_PHY_DX8SL0PLLCR0_PLLBYP_MASK 0x80000000U + +/* +* PLL Reset +*/ +#undef DDR_PHY_DX8SL0PLLCR0_PLLRST_DEFVAL +#undef DDR_PHY_DX8SL0PLLCR0_PLLRST_SHIFT +#undef DDR_PHY_DX8SL0PLLCR0_PLLRST_MASK +#define DDR_PHY_DX8SL0PLLCR0_PLLRST_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL0PLLCR0_PLLRST_SHIFT 30 +#define DDR_PHY_DX8SL0PLLCR0_PLLRST_MASK 0x40000000U + +/* +* PLL Power Down +*/ +#undef DDR_PHY_DX8SL0PLLCR0_PLLPD_DEFVAL +#undef DDR_PHY_DX8SL0PLLCR0_PLLPD_SHIFT +#undef DDR_PHY_DX8SL0PLLCR0_PLLPD_MASK +#define DDR_PHY_DX8SL0PLLCR0_PLLPD_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL0PLLCR0_PLLPD_SHIFT 29 +#define DDR_PHY_DX8SL0PLLCR0_PLLPD_MASK 0x20000000U + +/* +* Reference Stop Mode +*/ +#undef DDR_PHY_DX8SL0PLLCR0_RSTOPM_DEFVAL +#undef DDR_PHY_DX8SL0PLLCR0_RSTOPM_SHIFT +#undef DDR_PHY_DX8SL0PLLCR0_RSTOPM_MASK +#define DDR_PHY_DX8SL0PLLCR0_RSTOPM_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL0PLLCR0_RSTOPM_SHIFT 28 +#define DDR_PHY_DX8SL0PLLCR0_RSTOPM_MASK 0x10000000U + +/* +* PLL Frequency Select +*/ +#undef DDR_PHY_DX8SL0PLLCR0_FRQSEL_DEFVAL +#undef DDR_PHY_DX8SL0PLLCR0_FRQSEL_SHIFT +#undef DDR_PHY_DX8SL0PLLCR0_FRQSEL_MASK +#define DDR_PHY_DX8SL0PLLCR0_FRQSEL_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL0PLLCR0_FRQSEL_SHIFT 24 +#define DDR_PHY_DX8SL0PLLCR0_FRQSEL_MASK 0x0F000000U + +/* +* Relock Mode +*/ +#undef DDR_PHY_DX8SL0PLLCR0_RLOCKM_DEFVAL +#undef DDR_PHY_DX8SL0PLLCR0_RLOCKM_SHIFT +#undef DDR_PHY_DX8SL0PLLCR0_RLOCKM_MASK +#define DDR_PHY_DX8SL0PLLCR0_RLOCKM_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL0PLLCR0_RLOCKM_SHIFT 23 +#define DDR_PHY_DX8SL0PLLCR0_RLOCKM_MASK 0x00800000U + +/* +* Charge Pump Proportional Current Control +*/ +#undef DDR_PHY_DX8SL0PLLCR0_CPPC_DEFVAL +#undef DDR_PHY_DX8SL0PLLCR0_CPPC_SHIFT +#undef DDR_PHY_DX8SL0PLLCR0_CPPC_MASK +#define DDR_PHY_DX8SL0PLLCR0_CPPC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL0PLLCR0_CPPC_SHIFT 17 +#define DDR_PHY_DX8SL0PLLCR0_CPPC_MASK 0x007E0000U + +/* +* Charge Pump Integrating Current Control +*/ +#undef DDR_PHY_DX8SL0PLLCR0_CPIC_DEFVAL +#undef DDR_PHY_DX8SL0PLLCR0_CPIC_SHIFT +#undef DDR_PHY_DX8SL0PLLCR0_CPIC_MASK +#define DDR_PHY_DX8SL0PLLCR0_CPIC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL0PLLCR0_CPIC_SHIFT 13 +#define DDR_PHY_DX8SL0PLLCR0_CPIC_MASK 0x0001E000U + +/* +* Gear Shift +*/ +#undef DDR_PHY_DX8SL0PLLCR0_GSHIFT_DEFVAL +#undef DDR_PHY_DX8SL0PLLCR0_GSHIFT_SHIFT +#undef DDR_PHY_DX8SL0PLLCR0_GSHIFT_MASK +#define DDR_PHY_DX8SL0PLLCR0_GSHIFT_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL0PLLCR0_GSHIFT_SHIFT 12 +#define DDR_PHY_DX8SL0PLLCR0_GSHIFT_MASK 0x00001000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL0PLLCR0_RESERVED_11_9_DEFVAL +#undef DDR_PHY_DX8SL0PLLCR0_RESERVED_11_9_SHIFT +#undef DDR_PHY_DX8SL0PLLCR0_RESERVED_11_9_MASK +#define DDR_PHY_DX8SL0PLLCR0_RESERVED_11_9_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL0PLLCR0_RESERVED_11_9_SHIFT 9 +#define DDR_PHY_DX8SL0PLLCR0_RESERVED_11_9_MASK 0x00000E00U + +/* +* Analog Test Enable (ATOEN) +*/ +#undef DDR_PHY_DX8SL0PLLCR0_ATOEN_DEFVAL +#undef DDR_PHY_DX8SL0PLLCR0_ATOEN_SHIFT +#undef DDR_PHY_DX8SL0PLLCR0_ATOEN_MASK +#define DDR_PHY_DX8SL0PLLCR0_ATOEN_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL0PLLCR0_ATOEN_SHIFT 8 +#define DDR_PHY_DX8SL0PLLCR0_ATOEN_MASK 0x00000100U + +/* +* Analog Test Control +*/ +#undef DDR_PHY_DX8SL0PLLCR0_ATC_DEFVAL +#undef DDR_PHY_DX8SL0PLLCR0_ATC_SHIFT +#undef DDR_PHY_DX8SL0PLLCR0_ATC_MASK +#define DDR_PHY_DX8SL0PLLCR0_ATC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL0PLLCR0_ATC_SHIFT 4 +#define DDR_PHY_DX8SL0PLLCR0_ATC_MASK 0x000000F0U + +/* +* Digital Test Control +*/ +#undef DDR_PHY_DX8SL0PLLCR0_DTC_DEFVAL +#undef DDR_PHY_DX8SL0PLLCR0_DTC_SHIFT +#undef DDR_PHY_DX8SL0PLLCR0_DTC_MASK +#define DDR_PHY_DX8SL0PLLCR0_DTC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL0PLLCR0_DTC_SHIFT 0 +#define DDR_PHY_DX8SL0PLLCR0_DTC_MASK 0x0000000FU + +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_DEFVAL #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_SHIFT #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_MASK -#define DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_SHIFT 25 -#define DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_MASK 0xFE000000U +#define DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_SHIFT 25 +#define DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_MASK 0xFE000000U -/*Read Path Rise-to-Rise Mode*/ +/* +* Read Path Rise-to-Rise Mode +*/ #undef DDR_PHY_DX8SL0DQSCTL_RRRMODE_DEFVAL #undef DDR_PHY_DX8SL0DQSCTL_RRRMODE_SHIFT #undef DDR_PHY_DX8SL0DQSCTL_RRRMODE_MASK -#define DDR_PHY_DX8SL0DQSCTL_RRRMODE_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL0DQSCTL_RRRMODE_SHIFT 24 -#define DDR_PHY_DX8SL0DQSCTL_RRRMODE_MASK 0x01000000U +#define DDR_PHY_DX8SL0DQSCTL_RRRMODE_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL0DQSCTL_RRRMODE_SHIFT 24 +#define DDR_PHY_DX8SL0DQSCTL_RRRMODE_MASK 0x01000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_DEFVAL #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_SHIFT #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_MASK -#define DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_SHIFT 22 -#define DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_MASK 0x00C00000U +#define DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_MASK 0x00C00000U -/*Write Path Rise-to-Rise Mode*/ +/* +* Write Path Rise-to-Rise Mode +*/ #undef DDR_PHY_DX8SL0DQSCTL_WRRMODE_DEFVAL #undef DDR_PHY_DX8SL0DQSCTL_WRRMODE_SHIFT #undef DDR_PHY_DX8SL0DQSCTL_WRRMODE_MASK -#define DDR_PHY_DX8SL0DQSCTL_WRRMODE_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL0DQSCTL_WRRMODE_SHIFT 21 -#define DDR_PHY_DX8SL0DQSCTL_WRRMODE_MASK 0x00200000U +#define DDR_PHY_DX8SL0DQSCTL_WRRMODE_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL0DQSCTL_WRRMODE_SHIFT 21 +#define DDR_PHY_DX8SL0DQSCTL_WRRMODE_MASK 0x00200000U -/*DQS Gate Extension*/ +/* +* DQS Gate Extension +*/ #undef DDR_PHY_DX8SL0DQSCTL_DQSGX_DEFVAL #undef DDR_PHY_DX8SL0DQSCTL_DQSGX_SHIFT #undef DDR_PHY_DX8SL0DQSCTL_DQSGX_MASK -#define DDR_PHY_DX8SL0DQSCTL_DQSGX_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL0DQSCTL_DQSGX_SHIFT 19 -#define DDR_PHY_DX8SL0DQSCTL_DQSGX_MASK 0x00180000U +#define DDR_PHY_DX8SL0DQSCTL_DQSGX_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL0DQSCTL_DQSGX_SHIFT 19 +#define DDR_PHY_DX8SL0DQSCTL_DQSGX_MASK 0x00180000U -/*Low Power PLL Power Down*/ +/* +* Low Power PLL Power Down +*/ #undef DDR_PHY_DX8SL0DQSCTL_LPPLLPD_DEFVAL #undef DDR_PHY_DX8SL0DQSCTL_LPPLLPD_SHIFT #undef DDR_PHY_DX8SL0DQSCTL_LPPLLPD_MASK -#define DDR_PHY_DX8SL0DQSCTL_LPPLLPD_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL0DQSCTL_LPPLLPD_SHIFT 18 -#define DDR_PHY_DX8SL0DQSCTL_LPPLLPD_MASK 0x00040000U +#define DDR_PHY_DX8SL0DQSCTL_LPPLLPD_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL0DQSCTL_LPPLLPD_SHIFT 18 +#define DDR_PHY_DX8SL0DQSCTL_LPPLLPD_MASK 0x00040000U -/*Low Power I/O Power Down*/ +/* +* Low Power I/O Power Down +*/ #undef DDR_PHY_DX8SL0DQSCTL_LPIOPD_DEFVAL #undef DDR_PHY_DX8SL0DQSCTL_LPIOPD_SHIFT #undef DDR_PHY_DX8SL0DQSCTL_LPIOPD_MASK -#define DDR_PHY_DX8SL0DQSCTL_LPIOPD_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL0DQSCTL_LPIOPD_SHIFT 17 -#define DDR_PHY_DX8SL0DQSCTL_LPIOPD_MASK 0x00020000U +#define DDR_PHY_DX8SL0DQSCTL_LPIOPD_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL0DQSCTL_LPIOPD_SHIFT 17 +#define DDR_PHY_DX8SL0DQSCTL_LPIOPD_MASK 0x00020000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_DEFVAL #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_SHIFT #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_MASK -#define DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_SHIFT 15 -#define DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_MASK 0x00018000U +#define DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_SHIFT 15 +#define DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_MASK 0x00018000U -/*QS Counter Enable*/ +/* +* QS Counter Enable +*/ #undef DDR_PHY_DX8SL0DQSCTL_QSCNTEN_DEFVAL #undef DDR_PHY_DX8SL0DQSCTL_QSCNTEN_SHIFT #undef DDR_PHY_DX8SL0DQSCTL_QSCNTEN_MASK -#define DDR_PHY_DX8SL0DQSCTL_QSCNTEN_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL0DQSCTL_QSCNTEN_SHIFT 14 -#define DDR_PHY_DX8SL0DQSCTL_QSCNTEN_MASK 0x00004000U +#define DDR_PHY_DX8SL0DQSCTL_QSCNTEN_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL0DQSCTL_QSCNTEN_SHIFT 14 +#define DDR_PHY_DX8SL0DQSCTL_QSCNTEN_MASK 0x00004000U -/*Unused DQ I/O Mode*/ +/* +* Unused DQ I/O Mode +*/ #undef DDR_PHY_DX8SL0DQSCTL_UDQIOM_DEFVAL #undef DDR_PHY_DX8SL0DQSCTL_UDQIOM_SHIFT #undef DDR_PHY_DX8SL0DQSCTL_UDQIOM_MASK -#define DDR_PHY_DX8SL0DQSCTL_UDQIOM_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL0DQSCTL_UDQIOM_SHIFT 13 -#define DDR_PHY_DX8SL0DQSCTL_UDQIOM_MASK 0x00002000U +#define DDR_PHY_DX8SL0DQSCTL_UDQIOM_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL0DQSCTL_UDQIOM_SHIFT 13 +#define DDR_PHY_DX8SL0DQSCTL_UDQIOM_MASK 0x00002000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_DEFVAL #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_SHIFT #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_MASK -#define DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_SHIFT 10 -#define DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_MASK 0x00001C00U +#define DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_SHIFT 10 +#define DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_MASK 0x00001C00U -/*Data Slew Rate*/ +/* +* Data Slew Rate +*/ #undef DDR_PHY_DX8SL0DQSCTL_DXSR_DEFVAL #undef DDR_PHY_DX8SL0DQSCTL_DXSR_SHIFT #undef DDR_PHY_DX8SL0DQSCTL_DXSR_MASK -#define DDR_PHY_DX8SL0DQSCTL_DXSR_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL0DQSCTL_DXSR_SHIFT 8 -#define DDR_PHY_DX8SL0DQSCTL_DXSR_MASK 0x00000300U +#define DDR_PHY_DX8SL0DQSCTL_DXSR_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL0DQSCTL_DXSR_SHIFT 8 +#define DDR_PHY_DX8SL0DQSCTL_DXSR_MASK 0x00000300U -/*DQS_N Resistor*/ +/* +* DQS_N Resistor +*/ #undef DDR_PHY_DX8SL0DQSCTL_DQSNRES_DEFVAL #undef DDR_PHY_DX8SL0DQSCTL_DQSNRES_SHIFT #undef DDR_PHY_DX8SL0DQSCTL_DQSNRES_MASK -#define DDR_PHY_DX8SL0DQSCTL_DQSNRES_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL0DQSCTL_DQSNRES_SHIFT 4 -#define DDR_PHY_DX8SL0DQSCTL_DQSNRES_MASK 0x000000F0U +#define DDR_PHY_DX8SL0DQSCTL_DQSNRES_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL0DQSCTL_DQSNRES_SHIFT 4 +#define DDR_PHY_DX8SL0DQSCTL_DQSNRES_MASK 0x000000F0U -/*DQS Resistor*/ +/* +* DQS Resistor +*/ #undef DDR_PHY_DX8SL0DQSCTL_DQSRES_DEFVAL #undef DDR_PHY_DX8SL0DQSCTL_DQSRES_SHIFT #undef DDR_PHY_DX8SL0DQSCTL_DQSRES_MASK -#define DDR_PHY_DX8SL0DQSCTL_DQSRES_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL0DQSCTL_DQSRES_SHIFT 0 -#define DDR_PHY_DX8SL0DQSCTL_DQSRES_MASK 0x0000000FU +#define DDR_PHY_DX8SL0DQSCTL_DQSRES_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL0DQSCTL_DQSRES_SHIFT 0 +#define DDR_PHY_DX8SL0DQSCTL_DQSRES_MASK 0x0000000FU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_DEFVAL #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_SHIFT #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_MASK -#define DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_SHIFT 24 -#define DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_MASK 0xFF000000U +#define DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_SHIFT 24 +#define DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_MASK 0xFF000000U -/*Configurable Read Data Enable*/ +/* +* Configurable Read Data Enable +*/ #undef DDR_PHY_DX8SL0DXCTL2_CRDEN_DEFVAL #undef DDR_PHY_DX8SL0DXCTL2_CRDEN_SHIFT #undef DDR_PHY_DX8SL0DXCTL2_CRDEN_MASK -#define DDR_PHY_DX8SL0DXCTL2_CRDEN_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL0DXCTL2_CRDEN_SHIFT 23 -#define DDR_PHY_DX8SL0DXCTL2_CRDEN_MASK 0x00800000U +#define DDR_PHY_DX8SL0DXCTL2_CRDEN_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_CRDEN_SHIFT 23 +#define DDR_PHY_DX8SL0DXCTL2_CRDEN_MASK 0x00800000U -/*OX Extension during Post-amble*/ +/* +* OX Extension during Post-amble +*/ #undef DDR_PHY_DX8SL0DXCTL2_POSOEX_DEFVAL #undef DDR_PHY_DX8SL0DXCTL2_POSOEX_SHIFT #undef DDR_PHY_DX8SL0DXCTL2_POSOEX_MASK -#define DDR_PHY_DX8SL0DXCTL2_POSOEX_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL0DXCTL2_POSOEX_SHIFT 20 -#define DDR_PHY_DX8SL0DXCTL2_POSOEX_MASK 0x00700000U +#define DDR_PHY_DX8SL0DXCTL2_POSOEX_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_POSOEX_SHIFT 20 +#define DDR_PHY_DX8SL0DXCTL2_POSOEX_MASK 0x00700000U -/*OE Extension during Pre-amble*/ +/* +* OE Extension during Pre-amble +*/ #undef DDR_PHY_DX8SL0DXCTL2_PREOEX_DEFVAL #undef DDR_PHY_DX8SL0DXCTL2_PREOEX_SHIFT #undef DDR_PHY_DX8SL0DXCTL2_PREOEX_MASK -#define DDR_PHY_DX8SL0DXCTL2_PREOEX_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL0DXCTL2_PREOEX_SHIFT 18 -#define DDR_PHY_DX8SL0DXCTL2_PREOEX_MASK 0x000C0000U +#define DDR_PHY_DX8SL0DXCTL2_PREOEX_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_PREOEX_SHIFT 18 +#define DDR_PHY_DX8SL0DXCTL2_PREOEX_MASK 0x000C0000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_17_DEFVAL #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_17_SHIFT #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_17_MASK -#define DDR_PHY_DX8SL0DXCTL2_RESERVED_17_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL0DXCTL2_RESERVED_17_SHIFT 17 -#define DDR_PHY_DX8SL0DXCTL2_RESERVED_17_MASK 0x00020000U +#define DDR_PHY_DX8SL0DXCTL2_RESERVED_17_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_RESERVED_17_SHIFT 17 +#define DDR_PHY_DX8SL0DXCTL2_RESERVED_17_MASK 0x00020000U -/*I/O Assisted Gate Select*/ +/* +* I/O Assisted Gate Select +*/ #undef DDR_PHY_DX8SL0DXCTL2_IOAG_DEFVAL #undef DDR_PHY_DX8SL0DXCTL2_IOAG_SHIFT #undef DDR_PHY_DX8SL0DXCTL2_IOAG_MASK -#define DDR_PHY_DX8SL0DXCTL2_IOAG_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL0DXCTL2_IOAG_SHIFT 16 -#define DDR_PHY_DX8SL0DXCTL2_IOAG_MASK 0x00010000U +#define DDR_PHY_DX8SL0DXCTL2_IOAG_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_IOAG_SHIFT 16 +#define DDR_PHY_DX8SL0DXCTL2_IOAG_MASK 0x00010000U -/*I/O Loopback Select*/ +/* +* I/O Loopback Select +*/ #undef DDR_PHY_DX8SL0DXCTL2_IOLB_DEFVAL #undef DDR_PHY_DX8SL0DXCTL2_IOLB_SHIFT #undef DDR_PHY_DX8SL0DXCTL2_IOLB_MASK -#define DDR_PHY_DX8SL0DXCTL2_IOLB_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL0DXCTL2_IOLB_SHIFT 15 -#define DDR_PHY_DX8SL0DXCTL2_IOLB_MASK 0x00008000U +#define DDR_PHY_DX8SL0DXCTL2_IOLB_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_IOLB_SHIFT 15 +#define DDR_PHY_DX8SL0DXCTL2_IOLB_MASK 0x00008000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_DEFVAL #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_SHIFT #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_MASK -#define DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_SHIFT 13 -#define DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_MASK 0x00006000U +#define DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_SHIFT 13 +#define DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_MASK 0x00006000U -/*Low Power Wakeup Threshold*/ +/* +* Low Power Wakeup Threshold +*/ #undef DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_DEFVAL #undef DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_SHIFT #undef DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_MASK -#define DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_SHIFT 9 -#define DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_MASK 0x00001E00U +#define DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_SHIFT 9 +#define DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_MASK 0x00001E00U -/*Read Data Bus Inversion Enable*/ +/* +* Read Data Bus Inversion Enable +*/ #undef DDR_PHY_DX8SL0DXCTL2_RDBI_DEFVAL #undef DDR_PHY_DX8SL0DXCTL2_RDBI_SHIFT #undef DDR_PHY_DX8SL0DXCTL2_RDBI_MASK -#define DDR_PHY_DX8SL0DXCTL2_RDBI_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL0DXCTL2_RDBI_SHIFT 8 -#define DDR_PHY_DX8SL0DXCTL2_RDBI_MASK 0x00000100U +#define DDR_PHY_DX8SL0DXCTL2_RDBI_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_RDBI_SHIFT 8 +#define DDR_PHY_DX8SL0DXCTL2_RDBI_MASK 0x00000100U -/*Write Data Bus Inversion Enable*/ +/* +* Write Data Bus Inversion Enable +*/ #undef DDR_PHY_DX8SL0DXCTL2_WDBI_DEFVAL #undef DDR_PHY_DX8SL0DXCTL2_WDBI_SHIFT #undef DDR_PHY_DX8SL0DXCTL2_WDBI_MASK -#define DDR_PHY_DX8SL0DXCTL2_WDBI_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL0DXCTL2_WDBI_SHIFT 7 -#define DDR_PHY_DX8SL0DXCTL2_WDBI_MASK 0x00000080U +#define DDR_PHY_DX8SL0DXCTL2_WDBI_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_WDBI_SHIFT 7 +#define DDR_PHY_DX8SL0DXCTL2_WDBI_MASK 0x00000080U -/*PUB Read FIFO Bypass*/ +/* +* PUB Read FIFO Bypass +*/ #undef DDR_PHY_DX8SL0DXCTL2_PRFBYP_DEFVAL #undef DDR_PHY_DX8SL0DXCTL2_PRFBYP_SHIFT #undef DDR_PHY_DX8SL0DXCTL2_PRFBYP_MASK -#define DDR_PHY_DX8SL0DXCTL2_PRFBYP_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL0DXCTL2_PRFBYP_SHIFT 6 -#define DDR_PHY_DX8SL0DXCTL2_PRFBYP_MASK 0x00000040U +#define DDR_PHY_DX8SL0DXCTL2_PRFBYP_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_PRFBYP_SHIFT 6 +#define DDR_PHY_DX8SL0DXCTL2_PRFBYP_MASK 0x00000040U -/*DATX8 Receive FIFO Read Mode*/ +/* +* DATX8 Receive FIFO Read Mode +*/ #undef DDR_PHY_DX8SL0DXCTL2_RDMODE_DEFVAL #undef DDR_PHY_DX8SL0DXCTL2_RDMODE_SHIFT #undef DDR_PHY_DX8SL0DXCTL2_RDMODE_MASK -#define DDR_PHY_DX8SL0DXCTL2_RDMODE_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL0DXCTL2_RDMODE_SHIFT 4 -#define DDR_PHY_DX8SL0DXCTL2_RDMODE_MASK 0x00000030U +#define DDR_PHY_DX8SL0DXCTL2_RDMODE_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_RDMODE_SHIFT 4 +#define DDR_PHY_DX8SL0DXCTL2_RDMODE_MASK 0x00000030U -/*Disables the Read FIFO Reset*/ +/* +* Disables the Read FIFO Reset +*/ #undef DDR_PHY_DX8SL0DXCTL2_DISRST_DEFVAL #undef DDR_PHY_DX8SL0DXCTL2_DISRST_SHIFT #undef DDR_PHY_DX8SL0DXCTL2_DISRST_MASK -#define DDR_PHY_DX8SL0DXCTL2_DISRST_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL0DXCTL2_DISRST_SHIFT 3 -#define DDR_PHY_DX8SL0DXCTL2_DISRST_MASK 0x00000008U +#define DDR_PHY_DX8SL0DXCTL2_DISRST_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_DISRST_SHIFT 3 +#define DDR_PHY_DX8SL0DXCTL2_DISRST_MASK 0x00000008U -/*Read DQS Gate I/O Loopback*/ +/* +* Read DQS Gate I/O Loopback +*/ #undef DDR_PHY_DX8SL0DXCTL2_DQSGLB_DEFVAL #undef DDR_PHY_DX8SL0DXCTL2_DQSGLB_SHIFT #undef DDR_PHY_DX8SL0DXCTL2_DQSGLB_MASK -#define DDR_PHY_DX8SL0DXCTL2_DQSGLB_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL0DXCTL2_DQSGLB_SHIFT 1 -#define DDR_PHY_DX8SL0DXCTL2_DQSGLB_MASK 0x00000006U +#define DDR_PHY_DX8SL0DXCTL2_DQSGLB_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_DQSGLB_SHIFT 1 +#define DDR_PHY_DX8SL0DXCTL2_DQSGLB_MASK 0x00000006U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_0_DEFVAL #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_0_SHIFT #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_0_MASK -#define DDR_PHY_DX8SL0DXCTL2_RESERVED_0_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL0DXCTL2_RESERVED_0_SHIFT 0 -#define DDR_PHY_DX8SL0DXCTL2_RESERVED_0_MASK 0x00000001U +#define DDR_PHY_DX8SL0DXCTL2_RESERVED_0_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_RESERVED_0_SHIFT 0 +#define DDR_PHY_DX8SL0DXCTL2_RESERVED_0_MASK 0x00000001U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL0IOCR_RESERVED_31_DEFVAL #undef DDR_PHY_DX8SL0IOCR_RESERVED_31_SHIFT #undef DDR_PHY_DX8SL0IOCR_RESERVED_31_MASK -#define DDR_PHY_DX8SL0IOCR_RESERVED_31_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL0IOCR_RESERVED_31_SHIFT 31 -#define DDR_PHY_DX8SL0IOCR_RESERVED_31_MASK 0x80000000U +#define DDR_PHY_DX8SL0IOCR_RESERVED_31_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL0IOCR_RESERVED_31_SHIFT 31 +#define DDR_PHY_DX8SL0IOCR_RESERVED_31_MASK 0x80000000U -/*PVREF_DAC REFSEL range select*/ +/* +* PVREF_DAC REFSEL range select +*/ #undef DDR_PHY_DX8SL0IOCR_DXDACRANGE_DEFVAL #undef DDR_PHY_DX8SL0IOCR_DXDACRANGE_SHIFT #undef DDR_PHY_DX8SL0IOCR_DXDACRANGE_MASK -#define DDR_PHY_DX8SL0IOCR_DXDACRANGE_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL0IOCR_DXDACRANGE_SHIFT 28 -#define DDR_PHY_DX8SL0IOCR_DXDACRANGE_MASK 0x70000000U +#define DDR_PHY_DX8SL0IOCR_DXDACRANGE_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL0IOCR_DXDACRANGE_SHIFT 28 +#define DDR_PHY_DX8SL0IOCR_DXDACRANGE_MASK 0x70000000U -/*IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring*/ +/* +* IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring +*/ #undef DDR_PHY_DX8SL0IOCR_DXVREFIOM_DEFVAL #undef DDR_PHY_DX8SL0IOCR_DXVREFIOM_SHIFT #undef DDR_PHY_DX8SL0IOCR_DXVREFIOM_MASK -#define DDR_PHY_DX8SL0IOCR_DXVREFIOM_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL0IOCR_DXVREFIOM_SHIFT 25 -#define DDR_PHY_DX8SL0IOCR_DXVREFIOM_MASK 0x0E000000U +#define DDR_PHY_DX8SL0IOCR_DXVREFIOM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL0IOCR_DXVREFIOM_SHIFT 25 +#define DDR_PHY_DX8SL0IOCR_DXVREFIOM_MASK 0x0E000000U -/*DX IO Mode*/ +/* +* DX IO Mode +*/ #undef DDR_PHY_DX8SL0IOCR_DXIOM_DEFVAL #undef DDR_PHY_DX8SL0IOCR_DXIOM_SHIFT #undef DDR_PHY_DX8SL0IOCR_DXIOM_MASK -#define DDR_PHY_DX8SL0IOCR_DXIOM_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL0IOCR_DXIOM_SHIFT 22 -#define DDR_PHY_DX8SL0IOCR_DXIOM_MASK 0x01C00000U +#define DDR_PHY_DX8SL0IOCR_DXIOM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL0IOCR_DXIOM_SHIFT 22 +#define DDR_PHY_DX8SL0IOCR_DXIOM_MASK 0x01C00000U -/*DX IO Transmitter Mode*/ +/* +* DX IO Transmitter Mode +*/ #undef DDR_PHY_DX8SL0IOCR_DXTXM_DEFVAL #undef DDR_PHY_DX8SL0IOCR_DXTXM_SHIFT #undef DDR_PHY_DX8SL0IOCR_DXTXM_MASK -#define DDR_PHY_DX8SL0IOCR_DXTXM_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL0IOCR_DXTXM_SHIFT 11 -#define DDR_PHY_DX8SL0IOCR_DXTXM_MASK 0x003FF800U +#define DDR_PHY_DX8SL0IOCR_DXTXM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL0IOCR_DXTXM_SHIFT 11 +#define DDR_PHY_DX8SL0IOCR_DXTXM_MASK 0x003FF800U -/*DX IO Receiver Mode*/ +/* +* DX IO Receiver Mode +*/ #undef DDR_PHY_DX8SL0IOCR_DXRXM_DEFVAL #undef DDR_PHY_DX8SL0IOCR_DXRXM_SHIFT #undef DDR_PHY_DX8SL0IOCR_DXRXM_MASK -#define DDR_PHY_DX8SL0IOCR_DXRXM_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL0IOCR_DXRXM_SHIFT 0 -#define DDR_PHY_DX8SL0IOCR_DXRXM_MASK 0x000007FFU +#define DDR_PHY_DX8SL0IOCR_DXRXM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL0IOCR_DXRXM_SHIFT 0 +#define DDR_PHY_DX8SL0IOCR_DXRXM_MASK 0x000007FFU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL1OSC_RESERVED_31_30_DEFVAL #undef DDR_PHY_DX8SL1OSC_RESERVED_31_30_SHIFT #undef DDR_PHY_DX8SL1OSC_RESERVED_31_30_MASK -#define DDR_PHY_DX8SL1OSC_RESERVED_31_30_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL1OSC_RESERVED_31_30_SHIFT 30 -#define DDR_PHY_DX8SL1OSC_RESERVED_31_30_MASK 0xC0000000U +#define DDR_PHY_DX8SL1OSC_RESERVED_31_30_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX8SL1OSC_RESERVED_31_30_MASK 0xC0000000U -/*Enable Clock Gating for DX ddr_clk*/ +/* +* Enable Clock Gating for DX ddr_clk +*/ #undef DDR_PHY_DX8SL1OSC_GATEDXRDCLK_DEFVAL #undef DDR_PHY_DX8SL1OSC_GATEDXRDCLK_SHIFT #undef DDR_PHY_DX8SL1OSC_GATEDXRDCLK_MASK -#define DDR_PHY_DX8SL1OSC_GATEDXRDCLK_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL1OSC_GATEDXRDCLK_SHIFT 28 -#define DDR_PHY_DX8SL1OSC_GATEDXRDCLK_MASK 0x30000000U +#define DDR_PHY_DX8SL1OSC_GATEDXRDCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_GATEDXRDCLK_SHIFT 28 +#define DDR_PHY_DX8SL1OSC_GATEDXRDCLK_MASK 0x30000000U -/*Enable Clock Gating for DX ctl_rd_clk*/ +/* +* Enable Clock Gating for DX ctl_rd_clk +*/ #undef DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_DEFVAL #undef DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_SHIFT #undef DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_MASK -#define DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_SHIFT 26 -#define DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_MASK 0x0C000000U +#define DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_SHIFT 26 +#define DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_MASK 0x0C000000U -/*Enable Clock Gating for DX ctl_clk*/ +/* +* Enable Clock Gating for DX ctl_clk +*/ #undef DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_DEFVAL #undef DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_SHIFT #undef DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_MASK -#define DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_SHIFT 24 -#define DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_MASK 0x03000000U +#define DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_SHIFT 24 +#define DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_MASK 0x03000000U -/*Selects the level to which clocks will be stalled when clock gating is enabled.*/ +/* +* Selects the level to which clocks will be stalled when clock gating is e + * nabled. +*/ #undef DDR_PHY_DX8SL1OSC_CLKLEVEL_DEFVAL #undef DDR_PHY_DX8SL1OSC_CLKLEVEL_SHIFT #undef DDR_PHY_DX8SL1OSC_CLKLEVEL_MASK -#define DDR_PHY_DX8SL1OSC_CLKLEVEL_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL1OSC_CLKLEVEL_SHIFT 22 -#define DDR_PHY_DX8SL1OSC_CLKLEVEL_MASK 0x00C00000U +#define DDR_PHY_DX8SL1OSC_CLKLEVEL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_CLKLEVEL_SHIFT 22 +#define DDR_PHY_DX8SL1OSC_CLKLEVEL_MASK 0x00C00000U -/*Loopback Mode*/ +/* +* Loopback Mode +*/ #undef DDR_PHY_DX8SL1OSC_LBMODE_DEFVAL #undef DDR_PHY_DX8SL1OSC_LBMODE_SHIFT #undef DDR_PHY_DX8SL1OSC_LBMODE_MASK -#define DDR_PHY_DX8SL1OSC_LBMODE_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL1OSC_LBMODE_SHIFT 21 -#define DDR_PHY_DX8SL1OSC_LBMODE_MASK 0x00200000U +#define DDR_PHY_DX8SL1OSC_LBMODE_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_LBMODE_SHIFT 21 +#define DDR_PHY_DX8SL1OSC_LBMODE_MASK 0x00200000U -/*Load GSDQS LCDL with 2x the calibrated GSDQSPRD value*/ +/* +* Load GSDQS LCDL with 2x the calibrated GSDQSPRD value +*/ #undef DDR_PHY_DX8SL1OSC_LBGSDQS_DEFVAL #undef DDR_PHY_DX8SL1OSC_LBGSDQS_SHIFT #undef DDR_PHY_DX8SL1OSC_LBGSDQS_MASK -#define DDR_PHY_DX8SL1OSC_LBGSDQS_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL1OSC_LBGSDQS_SHIFT 20 -#define DDR_PHY_DX8SL1OSC_LBGSDQS_MASK 0x00100000U +#define DDR_PHY_DX8SL1OSC_LBGSDQS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_LBGSDQS_SHIFT 20 +#define DDR_PHY_DX8SL1OSC_LBGSDQS_MASK 0x00100000U -/*Loopback DQS Gating*/ +/* +* Loopback DQS Gating +*/ #undef DDR_PHY_DX8SL1OSC_LBGDQS_DEFVAL #undef DDR_PHY_DX8SL1OSC_LBGDQS_SHIFT #undef DDR_PHY_DX8SL1OSC_LBGDQS_MASK -#define DDR_PHY_DX8SL1OSC_LBGDQS_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL1OSC_LBGDQS_SHIFT 18 -#define DDR_PHY_DX8SL1OSC_LBGDQS_MASK 0x000C0000U +#define DDR_PHY_DX8SL1OSC_LBGDQS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_LBGDQS_SHIFT 18 +#define DDR_PHY_DX8SL1OSC_LBGDQS_MASK 0x000C0000U -/*Loopback DQS Shift*/ +/* +* Loopback DQS Shift +*/ #undef DDR_PHY_DX8SL1OSC_LBDQSS_DEFVAL #undef DDR_PHY_DX8SL1OSC_LBDQSS_SHIFT #undef DDR_PHY_DX8SL1OSC_LBDQSS_MASK -#define DDR_PHY_DX8SL1OSC_LBDQSS_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL1OSC_LBDQSS_SHIFT 17 -#define DDR_PHY_DX8SL1OSC_LBDQSS_MASK 0x00020000U +#define DDR_PHY_DX8SL1OSC_LBDQSS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_LBDQSS_SHIFT 17 +#define DDR_PHY_DX8SL1OSC_LBDQSS_MASK 0x00020000U -/*PHY High-Speed Reset*/ +/* +* PHY High-Speed Reset +*/ #undef DDR_PHY_DX8SL1OSC_PHYHRST_DEFVAL #undef DDR_PHY_DX8SL1OSC_PHYHRST_SHIFT #undef DDR_PHY_DX8SL1OSC_PHYHRST_MASK -#define DDR_PHY_DX8SL1OSC_PHYHRST_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL1OSC_PHYHRST_SHIFT 16 -#define DDR_PHY_DX8SL1OSC_PHYHRST_MASK 0x00010000U +#define DDR_PHY_DX8SL1OSC_PHYHRST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_PHYHRST_SHIFT 16 +#define DDR_PHY_DX8SL1OSC_PHYHRST_MASK 0x00010000U -/*PHY FIFO Reset*/ +/* +* PHY FIFO Reset +*/ #undef DDR_PHY_DX8SL1OSC_PHYFRST_DEFVAL #undef DDR_PHY_DX8SL1OSC_PHYFRST_SHIFT #undef DDR_PHY_DX8SL1OSC_PHYFRST_MASK -#define DDR_PHY_DX8SL1OSC_PHYFRST_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL1OSC_PHYFRST_SHIFT 15 -#define DDR_PHY_DX8SL1OSC_PHYFRST_MASK 0x00008000U +#define DDR_PHY_DX8SL1OSC_PHYFRST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_PHYFRST_SHIFT 15 +#define DDR_PHY_DX8SL1OSC_PHYFRST_MASK 0x00008000U -/*Delay Line Test Start*/ +/* +* Delay Line Test Start +*/ #undef DDR_PHY_DX8SL1OSC_DLTST_DEFVAL #undef DDR_PHY_DX8SL1OSC_DLTST_SHIFT #undef DDR_PHY_DX8SL1OSC_DLTST_MASK -#define DDR_PHY_DX8SL1OSC_DLTST_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL1OSC_DLTST_SHIFT 14 -#define DDR_PHY_DX8SL1OSC_DLTST_MASK 0x00004000U +#define DDR_PHY_DX8SL1OSC_DLTST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_DLTST_SHIFT 14 +#define DDR_PHY_DX8SL1OSC_DLTST_MASK 0x00004000U -/*Delay Line Test Mode*/ +/* +* Delay Line Test Mode +*/ #undef DDR_PHY_DX8SL1OSC_DLTMODE_DEFVAL #undef DDR_PHY_DX8SL1OSC_DLTMODE_SHIFT #undef DDR_PHY_DX8SL1OSC_DLTMODE_MASK -#define DDR_PHY_DX8SL1OSC_DLTMODE_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL1OSC_DLTMODE_SHIFT 13 -#define DDR_PHY_DX8SL1OSC_DLTMODE_MASK 0x00002000U +#define DDR_PHY_DX8SL1OSC_DLTMODE_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_DLTMODE_SHIFT 13 +#define DDR_PHY_DX8SL1OSC_DLTMODE_MASK 0x00002000U -/*Reserved. Caution, do not write to this register field.*/ +/* +* Reserved. Caution, do not write to this register field. +*/ #undef DDR_PHY_DX8SL1OSC_RESERVED_12_11_DEFVAL #undef DDR_PHY_DX8SL1OSC_RESERVED_12_11_SHIFT #undef DDR_PHY_DX8SL1OSC_RESERVED_12_11_MASK -#define DDR_PHY_DX8SL1OSC_RESERVED_12_11_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL1OSC_RESERVED_12_11_SHIFT 11 -#define DDR_PHY_DX8SL1OSC_RESERVED_12_11_MASK 0x00001800U +#define DDR_PHY_DX8SL1OSC_RESERVED_12_11_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_RESERVED_12_11_SHIFT 11 +#define DDR_PHY_DX8SL1OSC_RESERVED_12_11_MASK 0x00001800U -/*Oscillator Mode Write-Data Delay Line Select*/ +/* +* Oscillator Mode Write-Data Delay Line Select +*/ #undef DDR_PHY_DX8SL1OSC_OSCWDDL_DEFVAL #undef DDR_PHY_DX8SL1OSC_OSCWDDL_SHIFT #undef DDR_PHY_DX8SL1OSC_OSCWDDL_MASK -#define DDR_PHY_DX8SL1OSC_OSCWDDL_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL1OSC_OSCWDDL_SHIFT 9 -#define DDR_PHY_DX8SL1OSC_OSCWDDL_MASK 0x00000600U +#define DDR_PHY_DX8SL1OSC_OSCWDDL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_OSCWDDL_SHIFT 9 +#define DDR_PHY_DX8SL1OSC_OSCWDDL_MASK 0x00000600U -/*Reserved. Caution, do not write to this register field.*/ +/* +* Reserved. Caution, do not write to this register field. +*/ #undef DDR_PHY_DX8SL1OSC_RESERVED_8_7_DEFVAL #undef DDR_PHY_DX8SL1OSC_RESERVED_8_7_SHIFT #undef DDR_PHY_DX8SL1OSC_RESERVED_8_7_MASK -#define DDR_PHY_DX8SL1OSC_RESERVED_8_7_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL1OSC_RESERVED_8_7_SHIFT 7 -#define DDR_PHY_DX8SL1OSC_RESERVED_8_7_MASK 0x00000180U +#define DDR_PHY_DX8SL1OSC_RESERVED_8_7_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_RESERVED_8_7_SHIFT 7 +#define DDR_PHY_DX8SL1OSC_RESERVED_8_7_MASK 0x00000180U -/*Oscillator Mode Write-Leveling Delay Line Select*/ +/* +* Oscillator Mode Write-Leveling Delay Line Select +*/ #undef DDR_PHY_DX8SL1OSC_OSCWDL_DEFVAL #undef DDR_PHY_DX8SL1OSC_OSCWDL_SHIFT #undef DDR_PHY_DX8SL1OSC_OSCWDL_MASK -#define DDR_PHY_DX8SL1OSC_OSCWDL_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL1OSC_OSCWDL_SHIFT 5 -#define DDR_PHY_DX8SL1OSC_OSCWDL_MASK 0x00000060U +#define DDR_PHY_DX8SL1OSC_OSCWDL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_OSCWDL_SHIFT 5 +#define DDR_PHY_DX8SL1OSC_OSCWDL_MASK 0x00000060U -/*Oscillator Mode Division*/ +/* +* Oscillator Mode Division +*/ #undef DDR_PHY_DX8SL1OSC_OSCDIV_DEFVAL #undef DDR_PHY_DX8SL1OSC_OSCDIV_SHIFT #undef DDR_PHY_DX8SL1OSC_OSCDIV_MASK -#define DDR_PHY_DX8SL1OSC_OSCDIV_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL1OSC_OSCDIV_SHIFT 1 -#define DDR_PHY_DX8SL1OSC_OSCDIV_MASK 0x0000001EU +#define DDR_PHY_DX8SL1OSC_OSCDIV_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_OSCDIV_SHIFT 1 +#define DDR_PHY_DX8SL1OSC_OSCDIV_MASK 0x0000001EU -/*Oscillator Enable*/ +/* +* Oscillator Enable +*/ #undef DDR_PHY_DX8SL1OSC_OSCEN_DEFVAL #undef DDR_PHY_DX8SL1OSC_OSCEN_SHIFT #undef DDR_PHY_DX8SL1OSC_OSCEN_MASK -#define DDR_PHY_DX8SL1OSC_OSCEN_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL1OSC_OSCEN_SHIFT 0 -#define DDR_PHY_DX8SL1OSC_OSCEN_MASK 0x00000001U +#define DDR_PHY_DX8SL1OSC_OSCEN_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_OSCEN_SHIFT 0 +#define DDR_PHY_DX8SL1OSC_OSCEN_MASK 0x00000001U -/*Reserved. Return zeroes on reads.*/ +/* +* PLL Bypass +*/ +#undef DDR_PHY_DX8SL1PLLCR0_PLLBYP_DEFVAL +#undef DDR_PHY_DX8SL1PLLCR0_PLLBYP_SHIFT +#undef DDR_PHY_DX8SL1PLLCR0_PLLBYP_MASK +#define DDR_PHY_DX8SL1PLLCR0_PLLBYP_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL1PLLCR0_PLLBYP_SHIFT 31 +#define DDR_PHY_DX8SL1PLLCR0_PLLBYP_MASK 0x80000000U + +/* +* PLL Reset +*/ +#undef DDR_PHY_DX8SL1PLLCR0_PLLRST_DEFVAL +#undef DDR_PHY_DX8SL1PLLCR0_PLLRST_SHIFT +#undef DDR_PHY_DX8SL1PLLCR0_PLLRST_MASK +#define DDR_PHY_DX8SL1PLLCR0_PLLRST_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL1PLLCR0_PLLRST_SHIFT 30 +#define DDR_PHY_DX8SL1PLLCR0_PLLRST_MASK 0x40000000U + +/* +* PLL Power Down +*/ +#undef DDR_PHY_DX8SL1PLLCR0_PLLPD_DEFVAL +#undef DDR_PHY_DX8SL1PLLCR0_PLLPD_SHIFT +#undef DDR_PHY_DX8SL1PLLCR0_PLLPD_MASK +#define DDR_PHY_DX8SL1PLLCR0_PLLPD_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL1PLLCR0_PLLPD_SHIFT 29 +#define DDR_PHY_DX8SL1PLLCR0_PLLPD_MASK 0x20000000U + +/* +* Reference Stop Mode +*/ +#undef DDR_PHY_DX8SL1PLLCR0_RSTOPM_DEFVAL +#undef DDR_PHY_DX8SL1PLLCR0_RSTOPM_SHIFT +#undef DDR_PHY_DX8SL1PLLCR0_RSTOPM_MASK +#define DDR_PHY_DX8SL1PLLCR0_RSTOPM_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL1PLLCR0_RSTOPM_SHIFT 28 +#define DDR_PHY_DX8SL1PLLCR0_RSTOPM_MASK 0x10000000U + +/* +* PLL Frequency Select +*/ +#undef DDR_PHY_DX8SL1PLLCR0_FRQSEL_DEFVAL +#undef DDR_PHY_DX8SL1PLLCR0_FRQSEL_SHIFT +#undef DDR_PHY_DX8SL1PLLCR0_FRQSEL_MASK +#define DDR_PHY_DX8SL1PLLCR0_FRQSEL_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL1PLLCR0_FRQSEL_SHIFT 24 +#define DDR_PHY_DX8SL1PLLCR0_FRQSEL_MASK 0x0F000000U + +/* +* Relock Mode +*/ +#undef DDR_PHY_DX8SL1PLLCR0_RLOCKM_DEFVAL +#undef DDR_PHY_DX8SL1PLLCR0_RLOCKM_SHIFT +#undef DDR_PHY_DX8SL1PLLCR0_RLOCKM_MASK +#define DDR_PHY_DX8SL1PLLCR0_RLOCKM_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL1PLLCR0_RLOCKM_SHIFT 23 +#define DDR_PHY_DX8SL1PLLCR0_RLOCKM_MASK 0x00800000U + +/* +* Charge Pump Proportional Current Control +*/ +#undef DDR_PHY_DX8SL1PLLCR0_CPPC_DEFVAL +#undef DDR_PHY_DX8SL1PLLCR0_CPPC_SHIFT +#undef DDR_PHY_DX8SL1PLLCR0_CPPC_MASK +#define DDR_PHY_DX8SL1PLLCR0_CPPC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL1PLLCR0_CPPC_SHIFT 17 +#define DDR_PHY_DX8SL1PLLCR0_CPPC_MASK 0x007E0000U + +/* +* Charge Pump Integrating Current Control +*/ +#undef DDR_PHY_DX8SL1PLLCR0_CPIC_DEFVAL +#undef DDR_PHY_DX8SL1PLLCR0_CPIC_SHIFT +#undef DDR_PHY_DX8SL1PLLCR0_CPIC_MASK +#define DDR_PHY_DX8SL1PLLCR0_CPIC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL1PLLCR0_CPIC_SHIFT 13 +#define DDR_PHY_DX8SL1PLLCR0_CPIC_MASK 0x0001E000U + +/* +* Gear Shift +*/ +#undef DDR_PHY_DX8SL1PLLCR0_GSHIFT_DEFVAL +#undef DDR_PHY_DX8SL1PLLCR0_GSHIFT_SHIFT +#undef DDR_PHY_DX8SL1PLLCR0_GSHIFT_MASK +#define DDR_PHY_DX8SL1PLLCR0_GSHIFT_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL1PLLCR0_GSHIFT_SHIFT 12 +#define DDR_PHY_DX8SL1PLLCR0_GSHIFT_MASK 0x00001000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL1PLLCR0_RESERVED_11_9_DEFVAL +#undef DDR_PHY_DX8SL1PLLCR0_RESERVED_11_9_SHIFT +#undef DDR_PHY_DX8SL1PLLCR0_RESERVED_11_9_MASK +#define DDR_PHY_DX8SL1PLLCR0_RESERVED_11_9_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL1PLLCR0_RESERVED_11_9_SHIFT 9 +#define DDR_PHY_DX8SL1PLLCR0_RESERVED_11_9_MASK 0x00000E00U + +/* +* Analog Test Enable (ATOEN) +*/ +#undef DDR_PHY_DX8SL1PLLCR0_ATOEN_DEFVAL +#undef DDR_PHY_DX8SL1PLLCR0_ATOEN_SHIFT +#undef DDR_PHY_DX8SL1PLLCR0_ATOEN_MASK +#define DDR_PHY_DX8SL1PLLCR0_ATOEN_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL1PLLCR0_ATOEN_SHIFT 8 +#define DDR_PHY_DX8SL1PLLCR0_ATOEN_MASK 0x00000100U + +/* +* Analog Test Control +*/ +#undef DDR_PHY_DX8SL1PLLCR0_ATC_DEFVAL +#undef DDR_PHY_DX8SL1PLLCR0_ATC_SHIFT +#undef DDR_PHY_DX8SL1PLLCR0_ATC_MASK +#define DDR_PHY_DX8SL1PLLCR0_ATC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL1PLLCR0_ATC_SHIFT 4 +#define DDR_PHY_DX8SL1PLLCR0_ATC_MASK 0x000000F0U + +/* +* Digital Test Control +*/ +#undef DDR_PHY_DX8SL1PLLCR0_DTC_DEFVAL +#undef DDR_PHY_DX8SL1PLLCR0_DTC_SHIFT +#undef DDR_PHY_DX8SL1PLLCR0_DTC_MASK +#define DDR_PHY_DX8SL1PLLCR0_DTC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL1PLLCR0_DTC_SHIFT 0 +#define DDR_PHY_DX8SL1PLLCR0_DTC_MASK 0x0000000FU + +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_DEFVAL #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_SHIFT #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_MASK -#define DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_SHIFT 25 -#define DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_MASK 0xFE000000U +#define DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_SHIFT 25 +#define DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_MASK 0xFE000000U -/*Read Path Rise-to-Rise Mode*/ +/* +* Read Path Rise-to-Rise Mode +*/ #undef DDR_PHY_DX8SL1DQSCTL_RRRMODE_DEFVAL #undef DDR_PHY_DX8SL1DQSCTL_RRRMODE_SHIFT #undef DDR_PHY_DX8SL1DQSCTL_RRRMODE_MASK -#define DDR_PHY_DX8SL1DQSCTL_RRRMODE_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL1DQSCTL_RRRMODE_SHIFT 24 -#define DDR_PHY_DX8SL1DQSCTL_RRRMODE_MASK 0x01000000U +#define DDR_PHY_DX8SL1DQSCTL_RRRMODE_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL1DQSCTL_RRRMODE_SHIFT 24 +#define DDR_PHY_DX8SL1DQSCTL_RRRMODE_MASK 0x01000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_DEFVAL #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_SHIFT #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_MASK -#define DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_SHIFT 22 -#define DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_MASK 0x00C00000U +#define DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_MASK 0x00C00000U -/*Write Path Rise-to-Rise Mode*/ +/* +* Write Path Rise-to-Rise Mode +*/ #undef DDR_PHY_DX8SL1DQSCTL_WRRMODE_DEFVAL #undef DDR_PHY_DX8SL1DQSCTL_WRRMODE_SHIFT #undef DDR_PHY_DX8SL1DQSCTL_WRRMODE_MASK -#define DDR_PHY_DX8SL1DQSCTL_WRRMODE_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL1DQSCTL_WRRMODE_SHIFT 21 -#define DDR_PHY_DX8SL1DQSCTL_WRRMODE_MASK 0x00200000U +#define DDR_PHY_DX8SL1DQSCTL_WRRMODE_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL1DQSCTL_WRRMODE_SHIFT 21 +#define DDR_PHY_DX8SL1DQSCTL_WRRMODE_MASK 0x00200000U -/*DQS Gate Extension*/ +/* +* DQS Gate Extension +*/ #undef DDR_PHY_DX8SL1DQSCTL_DQSGX_DEFVAL #undef DDR_PHY_DX8SL1DQSCTL_DQSGX_SHIFT #undef DDR_PHY_DX8SL1DQSCTL_DQSGX_MASK -#define DDR_PHY_DX8SL1DQSCTL_DQSGX_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL1DQSCTL_DQSGX_SHIFT 19 -#define DDR_PHY_DX8SL1DQSCTL_DQSGX_MASK 0x00180000U +#define DDR_PHY_DX8SL1DQSCTL_DQSGX_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL1DQSCTL_DQSGX_SHIFT 19 +#define DDR_PHY_DX8SL1DQSCTL_DQSGX_MASK 0x00180000U -/*Low Power PLL Power Down*/ +/* +* Low Power PLL Power Down +*/ #undef DDR_PHY_DX8SL1DQSCTL_LPPLLPD_DEFVAL #undef DDR_PHY_DX8SL1DQSCTL_LPPLLPD_SHIFT #undef DDR_PHY_DX8SL1DQSCTL_LPPLLPD_MASK -#define DDR_PHY_DX8SL1DQSCTL_LPPLLPD_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL1DQSCTL_LPPLLPD_SHIFT 18 -#define DDR_PHY_DX8SL1DQSCTL_LPPLLPD_MASK 0x00040000U +#define DDR_PHY_DX8SL1DQSCTL_LPPLLPD_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL1DQSCTL_LPPLLPD_SHIFT 18 +#define DDR_PHY_DX8SL1DQSCTL_LPPLLPD_MASK 0x00040000U -/*Low Power I/O Power Down*/ +/* +* Low Power I/O Power Down +*/ #undef DDR_PHY_DX8SL1DQSCTL_LPIOPD_DEFVAL #undef DDR_PHY_DX8SL1DQSCTL_LPIOPD_SHIFT #undef DDR_PHY_DX8SL1DQSCTL_LPIOPD_MASK -#define DDR_PHY_DX8SL1DQSCTL_LPIOPD_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL1DQSCTL_LPIOPD_SHIFT 17 -#define DDR_PHY_DX8SL1DQSCTL_LPIOPD_MASK 0x00020000U +#define DDR_PHY_DX8SL1DQSCTL_LPIOPD_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL1DQSCTL_LPIOPD_SHIFT 17 +#define DDR_PHY_DX8SL1DQSCTL_LPIOPD_MASK 0x00020000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_DEFVAL #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_SHIFT #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_MASK -#define DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_SHIFT 15 -#define DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_MASK 0x00018000U +#define DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_SHIFT 15 +#define DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_MASK 0x00018000U -/*QS Counter Enable*/ +/* +* QS Counter Enable +*/ #undef DDR_PHY_DX8SL1DQSCTL_QSCNTEN_DEFVAL #undef DDR_PHY_DX8SL1DQSCTL_QSCNTEN_SHIFT #undef DDR_PHY_DX8SL1DQSCTL_QSCNTEN_MASK -#define DDR_PHY_DX8SL1DQSCTL_QSCNTEN_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL1DQSCTL_QSCNTEN_SHIFT 14 -#define DDR_PHY_DX8SL1DQSCTL_QSCNTEN_MASK 0x00004000U +#define DDR_PHY_DX8SL1DQSCTL_QSCNTEN_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL1DQSCTL_QSCNTEN_SHIFT 14 +#define DDR_PHY_DX8SL1DQSCTL_QSCNTEN_MASK 0x00004000U -/*Unused DQ I/O Mode*/ +/* +* Unused DQ I/O Mode +*/ #undef DDR_PHY_DX8SL1DQSCTL_UDQIOM_DEFVAL #undef DDR_PHY_DX8SL1DQSCTL_UDQIOM_SHIFT #undef DDR_PHY_DX8SL1DQSCTL_UDQIOM_MASK -#define DDR_PHY_DX8SL1DQSCTL_UDQIOM_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL1DQSCTL_UDQIOM_SHIFT 13 -#define DDR_PHY_DX8SL1DQSCTL_UDQIOM_MASK 0x00002000U +#define DDR_PHY_DX8SL1DQSCTL_UDQIOM_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL1DQSCTL_UDQIOM_SHIFT 13 +#define DDR_PHY_DX8SL1DQSCTL_UDQIOM_MASK 0x00002000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_DEFVAL #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_SHIFT #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_MASK -#define DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_SHIFT 10 -#define DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_MASK 0x00001C00U +#define DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_SHIFT 10 +#define DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_MASK 0x00001C00U -/*Data Slew Rate*/ +/* +* Data Slew Rate +*/ #undef DDR_PHY_DX8SL1DQSCTL_DXSR_DEFVAL #undef DDR_PHY_DX8SL1DQSCTL_DXSR_SHIFT #undef DDR_PHY_DX8SL1DQSCTL_DXSR_MASK -#define DDR_PHY_DX8SL1DQSCTL_DXSR_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL1DQSCTL_DXSR_SHIFT 8 -#define DDR_PHY_DX8SL1DQSCTL_DXSR_MASK 0x00000300U +#define DDR_PHY_DX8SL1DQSCTL_DXSR_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL1DQSCTL_DXSR_SHIFT 8 +#define DDR_PHY_DX8SL1DQSCTL_DXSR_MASK 0x00000300U -/*DQS_N Resistor*/ +/* +* DQS_N Resistor +*/ #undef DDR_PHY_DX8SL1DQSCTL_DQSNRES_DEFVAL #undef DDR_PHY_DX8SL1DQSCTL_DQSNRES_SHIFT #undef DDR_PHY_DX8SL1DQSCTL_DQSNRES_MASK -#define DDR_PHY_DX8SL1DQSCTL_DQSNRES_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL1DQSCTL_DQSNRES_SHIFT 4 -#define DDR_PHY_DX8SL1DQSCTL_DQSNRES_MASK 0x000000F0U +#define DDR_PHY_DX8SL1DQSCTL_DQSNRES_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL1DQSCTL_DQSNRES_SHIFT 4 +#define DDR_PHY_DX8SL1DQSCTL_DQSNRES_MASK 0x000000F0U -/*DQS Resistor*/ +/* +* DQS Resistor +*/ #undef DDR_PHY_DX8SL1DQSCTL_DQSRES_DEFVAL #undef DDR_PHY_DX8SL1DQSCTL_DQSRES_SHIFT #undef DDR_PHY_DX8SL1DQSCTL_DQSRES_MASK -#define DDR_PHY_DX8SL1DQSCTL_DQSRES_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL1DQSCTL_DQSRES_SHIFT 0 -#define DDR_PHY_DX8SL1DQSCTL_DQSRES_MASK 0x0000000FU +#define DDR_PHY_DX8SL1DQSCTL_DQSRES_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL1DQSCTL_DQSRES_SHIFT 0 +#define DDR_PHY_DX8SL1DQSCTL_DQSRES_MASK 0x0000000FU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_DEFVAL #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_SHIFT #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_MASK -#define DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_SHIFT 24 -#define DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_MASK 0xFF000000U +#define DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_SHIFT 24 +#define DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_MASK 0xFF000000U -/*Configurable Read Data Enable*/ +/* +* Configurable Read Data Enable +*/ #undef DDR_PHY_DX8SL1DXCTL2_CRDEN_DEFVAL #undef DDR_PHY_DX8SL1DXCTL2_CRDEN_SHIFT #undef DDR_PHY_DX8SL1DXCTL2_CRDEN_MASK -#define DDR_PHY_DX8SL1DXCTL2_CRDEN_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL1DXCTL2_CRDEN_SHIFT 23 -#define DDR_PHY_DX8SL1DXCTL2_CRDEN_MASK 0x00800000U +#define DDR_PHY_DX8SL1DXCTL2_CRDEN_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_CRDEN_SHIFT 23 +#define DDR_PHY_DX8SL1DXCTL2_CRDEN_MASK 0x00800000U -/*OX Extension during Post-amble*/ +/* +* OX Extension during Post-amble +*/ #undef DDR_PHY_DX8SL1DXCTL2_POSOEX_DEFVAL #undef DDR_PHY_DX8SL1DXCTL2_POSOEX_SHIFT #undef DDR_PHY_DX8SL1DXCTL2_POSOEX_MASK -#define DDR_PHY_DX8SL1DXCTL2_POSOEX_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL1DXCTL2_POSOEX_SHIFT 20 -#define DDR_PHY_DX8SL1DXCTL2_POSOEX_MASK 0x00700000U +#define DDR_PHY_DX8SL1DXCTL2_POSOEX_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_POSOEX_SHIFT 20 +#define DDR_PHY_DX8SL1DXCTL2_POSOEX_MASK 0x00700000U -/*OE Extension during Pre-amble*/ +/* +* OE Extension during Pre-amble +*/ #undef DDR_PHY_DX8SL1DXCTL2_PREOEX_DEFVAL #undef DDR_PHY_DX8SL1DXCTL2_PREOEX_SHIFT #undef DDR_PHY_DX8SL1DXCTL2_PREOEX_MASK -#define DDR_PHY_DX8SL1DXCTL2_PREOEX_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL1DXCTL2_PREOEX_SHIFT 18 -#define DDR_PHY_DX8SL1DXCTL2_PREOEX_MASK 0x000C0000U +#define DDR_PHY_DX8SL1DXCTL2_PREOEX_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_PREOEX_SHIFT 18 +#define DDR_PHY_DX8SL1DXCTL2_PREOEX_MASK 0x000C0000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_17_DEFVAL #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_17_SHIFT #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_17_MASK -#define DDR_PHY_DX8SL1DXCTL2_RESERVED_17_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL1DXCTL2_RESERVED_17_SHIFT 17 -#define DDR_PHY_DX8SL1DXCTL2_RESERVED_17_MASK 0x00020000U +#define DDR_PHY_DX8SL1DXCTL2_RESERVED_17_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_RESERVED_17_SHIFT 17 +#define DDR_PHY_DX8SL1DXCTL2_RESERVED_17_MASK 0x00020000U -/*I/O Assisted Gate Select*/ +/* +* I/O Assisted Gate Select +*/ #undef DDR_PHY_DX8SL1DXCTL2_IOAG_DEFVAL #undef DDR_PHY_DX8SL1DXCTL2_IOAG_SHIFT #undef DDR_PHY_DX8SL1DXCTL2_IOAG_MASK -#define DDR_PHY_DX8SL1DXCTL2_IOAG_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL1DXCTL2_IOAG_SHIFT 16 -#define DDR_PHY_DX8SL1DXCTL2_IOAG_MASK 0x00010000U +#define DDR_PHY_DX8SL1DXCTL2_IOAG_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_IOAG_SHIFT 16 +#define DDR_PHY_DX8SL1DXCTL2_IOAG_MASK 0x00010000U -/*I/O Loopback Select*/ +/* +* I/O Loopback Select +*/ #undef DDR_PHY_DX8SL1DXCTL2_IOLB_DEFVAL #undef DDR_PHY_DX8SL1DXCTL2_IOLB_SHIFT #undef DDR_PHY_DX8SL1DXCTL2_IOLB_MASK -#define DDR_PHY_DX8SL1DXCTL2_IOLB_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL1DXCTL2_IOLB_SHIFT 15 -#define DDR_PHY_DX8SL1DXCTL2_IOLB_MASK 0x00008000U +#define DDR_PHY_DX8SL1DXCTL2_IOLB_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_IOLB_SHIFT 15 +#define DDR_PHY_DX8SL1DXCTL2_IOLB_MASK 0x00008000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_DEFVAL #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_SHIFT #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_MASK -#define DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_SHIFT 13 -#define DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_MASK 0x00006000U +#define DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_SHIFT 13 +#define DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_MASK 0x00006000U -/*Low Power Wakeup Threshold*/ +/* +* Low Power Wakeup Threshold +*/ #undef DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_DEFVAL #undef DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_SHIFT #undef DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_MASK -#define DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_SHIFT 9 -#define DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_MASK 0x00001E00U +#define DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_SHIFT 9 +#define DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_MASK 0x00001E00U -/*Read Data Bus Inversion Enable*/ +/* +* Read Data Bus Inversion Enable +*/ #undef DDR_PHY_DX8SL1DXCTL2_RDBI_DEFVAL #undef DDR_PHY_DX8SL1DXCTL2_RDBI_SHIFT #undef DDR_PHY_DX8SL1DXCTL2_RDBI_MASK -#define DDR_PHY_DX8SL1DXCTL2_RDBI_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL1DXCTL2_RDBI_SHIFT 8 -#define DDR_PHY_DX8SL1DXCTL2_RDBI_MASK 0x00000100U +#define DDR_PHY_DX8SL1DXCTL2_RDBI_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_RDBI_SHIFT 8 +#define DDR_PHY_DX8SL1DXCTL2_RDBI_MASK 0x00000100U -/*Write Data Bus Inversion Enable*/ +/* +* Write Data Bus Inversion Enable +*/ #undef DDR_PHY_DX8SL1DXCTL2_WDBI_DEFVAL #undef DDR_PHY_DX8SL1DXCTL2_WDBI_SHIFT #undef DDR_PHY_DX8SL1DXCTL2_WDBI_MASK -#define DDR_PHY_DX8SL1DXCTL2_WDBI_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL1DXCTL2_WDBI_SHIFT 7 -#define DDR_PHY_DX8SL1DXCTL2_WDBI_MASK 0x00000080U +#define DDR_PHY_DX8SL1DXCTL2_WDBI_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_WDBI_SHIFT 7 +#define DDR_PHY_DX8SL1DXCTL2_WDBI_MASK 0x00000080U -/*PUB Read FIFO Bypass*/ +/* +* PUB Read FIFO Bypass +*/ #undef DDR_PHY_DX8SL1DXCTL2_PRFBYP_DEFVAL #undef DDR_PHY_DX8SL1DXCTL2_PRFBYP_SHIFT #undef DDR_PHY_DX8SL1DXCTL2_PRFBYP_MASK -#define DDR_PHY_DX8SL1DXCTL2_PRFBYP_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL1DXCTL2_PRFBYP_SHIFT 6 -#define DDR_PHY_DX8SL1DXCTL2_PRFBYP_MASK 0x00000040U +#define DDR_PHY_DX8SL1DXCTL2_PRFBYP_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_PRFBYP_SHIFT 6 +#define DDR_PHY_DX8SL1DXCTL2_PRFBYP_MASK 0x00000040U -/*DATX8 Receive FIFO Read Mode*/ +/* +* DATX8 Receive FIFO Read Mode +*/ #undef DDR_PHY_DX8SL1DXCTL2_RDMODE_DEFVAL #undef DDR_PHY_DX8SL1DXCTL2_RDMODE_SHIFT #undef DDR_PHY_DX8SL1DXCTL2_RDMODE_MASK -#define DDR_PHY_DX8SL1DXCTL2_RDMODE_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL1DXCTL2_RDMODE_SHIFT 4 -#define DDR_PHY_DX8SL1DXCTL2_RDMODE_MASK 0x00000030U +#define DDR_PHY_DX8SL1DXCTL2_RDMODE_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_RDMODE_SHIFT 4 +#define DDR_PHY_DX8SL1DXCTL2_RDMODE_MASK 0x00000030U -/*Disables the Read FIFO Reset*/ +/* +* Disables the Read FIFO Reset +*/ #undef DDR_PHY_DX8SL1DXCTL2_DISRST_DEFVAL #undef DDR_PHY_DX8SL1DXCTL2_DISRST_SHIFT #undef DDR_PHY_DX8SL1DXCTL2_DISRST_MASK -#define DDR_PHY_DX8SL1DXCTL2_DISRST_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL1DXCTL2_DISRST_SHIFT 3 -#define DDR_PHY_DX8SL1DXCTL2_DISRST_MASK 0x00000008U +#define DDR_PHY_DX8SL1DXCTL2_DISRST_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_DISRST_SHIFT 3 +#define DDR_PHY_DX8SL1DXCTL2_DISRST_MASK 0x00000008U -/*Read DQS Gate I/O Loopback*/ +/* +* Read DQS Gate I/O Loopback +*/ #undef DDR_PHY_DX8SL1DXCTL2_DQSGLB_DEFVAL #undef DDR_PHY_DX8SL1DXCTL2_DQSGLB_SHIFT #undef DDR_PHY_DX8SL1DXCTL2_DQSGLB_MASK -#define DDR_PHY_DX8SL1DXCTL2_DQSGLB_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL1DXCTL2_DQSGLB_SHIFT 1 -#define DDR_PHY_DX8SL1DXCTL2_DQSGLB_MASK 0x00000006U +#define DDR_PHY_DX8SL1DXCTL2_DQSGLB_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_DQSGLB_SHIFT 1 +#define DDR_PHY_DX8SL1DXCTL2_DQSGLB_MASK 0x00000006U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_0_DEFVAL #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_0_SHIFT #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_0_MASK -#define DDR_PHY_DX8SL1DXCTL2_RESERVED_0_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL1DXCTL2_RESERVED_0_SHIFT 0 -#define DDR_PHY_DX8SL1DXCTL2_RESERVED_0_MASK 0x00000001U +#define DDR_PHY_DX8SL1DXCTL2_RESERVED_0_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_RESERVED_0_SHIFT 0 +#define DDR_PHY_DX8SL1DXCTL2_RESERVED_0_MASK 0x00000001U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL1IOCR_RESERVED_31_DEFVAL #undef DDR_PHY_DX8SL1IOCR_RESERVED_31_SHIFT #undef DDR_PHY_DX8SL1IOCR_RESERVED_31_MASK -#define DDR_PHY_DX8SL1IOCR_RESERVED_31_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL1IOCR_RESERVED_31_SHIFT 31 -#define DDR_PHY_DX8SL1IOCR_RESERVED_31_MASK 0x80000000U +#define DDR_PHY_DX8SL1IOCR_RESERVED_31_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL1IOCR_RESERVED_31_SHIFT 31 +#define DDR_PHY_DX8SL1IOCR_RESERVED_31_MASK 0x80000000U -/*PVREF_DAC REFSEL range select*/ +/* +* PVREF_DAC REFSEL range select +*/ #undef DDR_PHY_DX8SL1IOCR_DXDACRANGE_DEFVAL #undef DDR_PHY_DX8SL1IOCR_DXDACRANGE_SHIFT #undef DDR_PHY_DX8SL1IOCR_DXDACRANGE_MASK -#define DDR_PHY_DX8SL1IOCR_DXDACRANGE_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL1IOCR_DXDACRANGE_SHIFT 28 -#define DDR_PHY_DX8SL1IOCR_DXDACRANGE_MASK 0x70000000U +#define DDR_PHY_DX8SL1IOCR_DXDACRANGE_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL1IOCR_DXDACRANGE_SHIFT 28 +#define DDR_PHY_DX8SL1IOCR_DXDACRANGE_MASK 0x70000000U -/*IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring*/ +/* +* IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring +*/ #undef DDR_PHY_DX8SL1IOCR_DXVREFIOM_DEFVAL #undef DDR_PHY_DX8SL1IOCR_DXVREFIOM_SHIFT #undef DDR_PHY_DX8SL1IOCR_DXVREFIOM_MASK -#define DDR_PHY_DX8SL1IOCR_DXVREFIOM_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL1IOCR_DXVREFIOM_SHIFT 25 -#define DDR_PHY_DX8SL1IOCR_DXVREFIOM_MASK 0x0E000000U +#define DDR_PHY_DX8SL1IOCR_DXVREFIOM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL1IOCR_DXVREFIOM_SHIFT 25 +#define DDR_PHY_DX8SL1IOCR_DXVREFIOM_MASK 0x0E000000U -/*DX IO Mode*/ +/* +* DX IO Mode +*/ #undef DDR_PHY_DX8SL1IOCR_DXIOM_DEFVAL #undef DDR_PHY_DX8SL1IOCR_DXIOM_SHIFT #undef DDR_PHY_DX8SL1IOCR_DXIOM_MASK -#define DDR_PHY_DX8SL1IOCR_DXIOM_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL1IOCR_DXIOM_SHIFT 22 -#define DDR_PHY_DX8SL1IOCR_DXIOM_MASK 0x01C00000U +#define DDR_PHY_DX8SL1IOCR_DXIOM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL1IOCR_DXIOM_SHIFT 22 +#define DDR_PHY_DX8SL1IOCR_DXIOM_MASK 0x01C00000U -/*DX IO Transmitter Mode*/ +/* +* DX IO Transmitter Mode +*/ #undef DDR_PHY_DX8SL1IOCR_DXTXM_DEFVAL #undef DDR_PHY_DX8SL1IOCR_DXTXM_SHIFT #undef DDR_PHY_DX8SL1IOCR_DXTXM_MASK -#define DDR_PHY_DX8SL1IOCR_DXTXM_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL1IOCR_DXTXM_SHIFT 11 -#define DDR_PHY_DX8SL1IOCR_DXTXM_MASK 0x003FF800U +#define DDR_PHY_DX8SL1IOCR_DXTXM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL1IOCR_DXTXM_SHIFT 11 +#define DDR_PHY_DX8SL1IOCR_DXTXM_MASK 0x003FF800U -/*DX IO Receiver Mode*/ +/* +* DX IO Receiver Mode +*/ #undef DDR_PHY_DX8SL1IOCR_DXRXM_DEFVAL #undef DDR_PHY_DX8SL1IOCR_DXRXM_SHIFT #undef DDR_PHY_DX8SL1IOCR_DXRXM_MASK -#define DDR_PHY_DX8SL1IOCR_DXRXM_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL1IOCR_DXRXM_SHIFT 0 -#define DDR_PHY_DX8SL1IOCR_DXRXM_MASK 0x000007FFU +#define DDR_PHY_DX8SL1IOCR_DXRXM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL1IOCR_DXRXM_SHIFT 0 +#define DDR_PHY_DX8SL1IOCR_DXRXM_MASK 0x000007FFU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL2OSC_RESERVED_31_30_DEFVAL #undef DDR_PHY_DX8SL2OSC_RESERVED_31_30_SHIFT #undef DDR_PHY_DX8SL2OSC_RESERVED_31_30_MASK -#define DDR_PHY_DX8SL2OSC_RESERVED_31_30_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL2OSC_RESERVED_31_30_SHIFT 30 -#define DDR_PHY_DX8SL2OSC_RESERVED_31_30_MASK 0xC0000000U +#define DDR_PHY_DX8SL2OSC_RESERVED_31_30_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX8SL2OSC_RESERVED_31_30_MASK 0xC0000000U -/*Enable Clock Gating for DX ddr_clk*/ +/* +* Enable Clock Gating for DX ddr_clk +*/ #undef DDR_PHY_DX8SL2OSC_GATEDXRDCLK_DEFVAL #undef DDR_PHY_DX8SL2OSC_GATEDXRDCLK_SHIFT #undef DDR_PHY_DX8SL2OSC_GATEDXRDCLK_MASK -#define DDR_PHY_DX8SL2OSC_GATEDXRDCLK_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL2OSC_GATEDXRDCLK_SHIFT 28 -#define DDR_PHY_DX8SL2OSC_GATEDXRDCLK_MASK 0x30000000U +#define DDR_PHY_DX8SL2OSC_GATEDXRDCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_GATEDXRDCLK_SHIFT 28 +#define DDR_PHY_DX8SL2OSC_GATEDXRDCLK_MASK 0x30000000U -/*Enable Clock Gating for DX ctl_rd_clk*/ +/* +* Enable Clock Gating for DX ctl_rd_clk +*/ #undef DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_DEFVAL #undef DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_SHIFT #undef DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_MASK -#define DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_SHIFT 26 -#define DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_MASK 0x0C000000U +#define DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_SHIFT 26 +#define DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_MASK 0x0C000000U -/*Enable Clock Gating for DX ctl_clk*/ +/* +* Enable Clock Gating for DX ctl_clk +*/ #undef DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_DEFVAL #undef DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_SHIFT #undef DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_MASK -#define DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_SHIFT 24 -#define DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_MASK 0x03000000U +#define DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_SHIFT 24 +#define DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_MASK 0x03000000U -/*Selects the level to which clocks will be stalled when clock gating is enabled.*/ +/* +* Selects the level to which clocks will be stalled when clock gating is e + * nabled. +*/ #undef DDR_PHY_DX8SL2OSC_CLKLEVEL_DEFVAL #undef DDR_PHY_DX8SL2OSC_CLKLEVEL_SHIFT #undef DDR_PHY_DX8SL2OSC_CLKLEVEL_MASK -#define DDR_PHY_DX8SL2OSC_CLKLEVEL_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL2OSC_CLKLEVEL_SHIFT 22 -#define DDR_PHY_DX8SL2OSC_CLKLEVEL_MASK 0x00C00000U +#define DDR_PHY_DX8SL2OSC_CLKLEVEL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_CLKLEVEL_SHIFT 22 +#define DDR_PHY_DX8SL2OSC_CLKLEVEL_MASK 0x00C00000U -/*Loopback Mode*/ +/* +* Loopback Mode +*/ #undef DDR_PHY_DX8SL2OSC_LBMODE_DEFVAL #undef DDR_PHY_DX8SL2OSC_LBMODE_SHIFT #undef DDR_PHY_DX8SL2OSC_LBMODE_MASK -#define DDR_PHY_DX8SL2OSC_LBMODE_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL2OSC_LBMODE_SHIFT 21 -#define DDR_PHY_DX8SL2OSC_LBMODE_MASK 0x00200000U +#define DDR_PHY_DX8SL2OSC_LBMODE_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_LBMODE_SHIFT 21 +#define DDR_PHY_DX8SL2OSC_LBMODE_MASK 0x00200000U -/*Load GSDQS LCDL with 2x the calibrated GSDQSPRD value*/ +/* +* Load GSDQS LCDL with 2x the calibrated GSDQSPRD value +*/ #undef DDR_PHY_DX8SL2OSC_LBGSDQS_DEFVAL #undef DDR_PHY_DX8SL2OSC_LBGSDQS_SHIFT #undef DDR_PHY_DX8SL2OSC_LBGSDQS_MASK -#define DDR_PHY_DX8SL2OSC_LBGSDQS_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL2OSC_LBGSDQS_SHIFT 20 -#define DDR_PHY_DX8SL2OSC_LBGSDQS_MASK 0x00100000U +#define DDR_PHY_DX8SL2OSC_LBGSDQS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_LBGSDQS_SHIFT 20 +#define DDR_PHY_DX8SL2OSC_LBGSDQS_MASK 0x00100000U -/*Loopback DQS Gating*/ +/* +* Loopback DQS Gating +*/ #undef DDR_PHY_DX8SL2OSC_LBGDQS_DEFVAL #undef DDR_PHY_DX8SL2OSC_LBGDQS_SHIFT #undef DDR_PHY_DX8SL2OSC_LBGDQS_MASK -#define DDR_PHY_DX8SL2OSC_LBGDQS_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL2OSC_LBGDQS_SHIFT 18 -#define DDR_PHY_DX8SL2OSC_LBGDQS_MASK 0x000C0000U +#define DDR_PHY_DX8SL2OSC_LBGDQS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_LBGDQS_SHIFT 18 +#define DDR_PHY_DX8SL2OSC_LBGDQS_MASK 0x000C0000U -/*Loopback DQS Shift*/ +/* +* Loopback DQS Shift +*/ #undef DDR_PHY_DX8SL2OSC_LBDQSS_DEFVAL #undef DDR_PHY_DX8SL2OSC_LBDQSS_SHIFT #undef DDR_PHY_DX8SL2OSC_LBDQSS_MASK -#define DDR_PHY_DX8SL2OSC_LBDQSS_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL2OSC_LBDQSS_SHIFT 17 -#define DDR_PHY_DX8SL2OSC_LBDQSS_MASK 0x00020000U +#define DDR_PHY_DX8SL2OSC_LBDQSS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_LBDQSS_SHIFT 17 +#define DDR_PHY_DX8SL2OSC_LBDQSS_MASK 0x00020000U -/*PHY High-Speed Reset*/ +/* +* PHY High-Speed Reset +*/ #undef DDR_PHY_DX8SL2OSC_PHYHRST_DEFVAL #undef DDR_PHY_DX8SL2OSC_PHYHRST_SHIFT #undef DDR_PHY_DX8SL2OSC_PHYHRST_MASK -#define DDR_PHY_DX8SL2OSC_PHYHRST_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL2OSC_PHYHRST_SHIFT 16 -#define DDR_PHY_DX8SL2OSC_PHYHRST_MASK 0x00010000U +#define DDR_PHY_DX8SL2OSC_PHYHRST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_PHYHRST_SHIFT 16 +#define DDR_PHY_DX8SL2OSC_PHYHRST_MASK 0x00010000U -/*PHY FIFO Reset*/ +/* +* PHY FIFO Reset +*/ #undef DDR_PHY_DX8SL2OSC_PHYFRST_DEFVAL #undef DDR_PHY_DX8SL2OSC_PHYFRST_SHIFT #undef DDR_PHY_DX8SL2OSC_PHYFRST_MASK -#define DDR_PHY_DX8SL2OSC_PHYFRST_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL2OSC_PHYFRST_SHIFT 15 -#define DDR_PHY_DX8SL2OSC_PHYFRST_MASK 0x00008000U +#define DDR_PHY_DX8SL2OSC_PHYFRST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_PHYFRST_SHIFT 15 +#define DDR_PHY_DX8SL2OSC_PHYFRST_MASK 0x00008000U -/*Delay Line Test Start*/ +/* +* Delay Line Test Start +*/ #undef DDR_PHY_DX8SL2OSC_DLTST_DEFVAL #undef DDR_PHY_DX8SL2OSC_DLTST_SHIFT #undef DDR_PHY_DX8SL2OSC_DLTST_MASK -#define DDR_PHY_DX8SL2OSC_DLTST_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL2OSC_DLTST_SHIFT 14 -#define DDR_PHY_DX8SL2OSC_DLTST_MASK 0x00004000U +#define DDR_PHY_DX8SL2OSC_DLTST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_DLTST_SHIFT 14 +#define DDR_PHY_DX8SL2OSC_DLTST_MASK 0x00004000U -/*Delay Line Test Mode*/ +/* +* Delay Line Test Mode +*/ #undef DDR_PHY_DX8SL2OSC_DLTMODE_DEFVAL #undef DDR_PHY_DX8SL2OSC_DLTMODE_SHIFT #undef DDR_PHY_DX8SL2OSC_DLTMODE_MASK -#define DDR_PHY_DX8SL2OSC_DLTMODE_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL2OSC_DLTMODE_SHIFT 13 -#define DDR_PHY_DX8SL2OSC_DLTMODE_MASK 0x00002000U +#define DDR_PHY_DX8SL2OSC_DLTMODE_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_DLTMODE_SHIFT 13 +#define DDR_PHY_DX8SL2OSC_DLTMODE_MASK 0x00002000U -/*Reserved. Caution, do not write to this register field.*/ +/* +* Reserved. Caution, do not write to this register field. +*/ #undef DDR_PHY_DX8SL2OSC_RESERVED_12_11_DEFVAL #undef DDR_PHY_DX8SL2OSC_RESERVED_12_11_SHIFT #undef DDR_PHY_DX8SL2OSC_RESERVED_12_11_MASK -#define DDR_PHY_DX8SL2OSC_RESERVED_12_11_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL2OSC_RESERVED_12_11_SHIFT 11 -#define DDR_PHY_DX8SL2OSC_RESERVED_12_11_MASK 0x00001800U +#define DDR_PHY_DX8SL2OSC_RESERVED_12_11_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_RESERVED_12_11_SHIFT 11 +#define DDR_PHY_DX8SL2OSC_RESERVED_12_11_MASK 0x00001800U -/*Oscillator Mode Write-Data Delay Line Select*/ +/* +* Oscillator Mode Write-Data Delay Line Select +*/ #undef DDR_PHY_DX8SL2OSC_OSCWDDL_DEFVAL #undef DDR_PHY_DX8SL2OSC_OSCWDDL_SHIFT #undef DDR_PHY_DX8SL2OSC_OSCWDDL_MASK -#define DDR_PHY_DX8SL2OSC_OSCWDDL_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL2OSC_OSCWDDL_SHIFT 9 -#define DDR_PHY_DX8SL2OSC_OSCWDDL_MASK 0x00000600U +#define DDR_PHY_DX8SL2OSC_OSCWDDL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_OSCWDDL_SHIFT 9 +#define DDR_PHY_DX8SL2OSC_OSCWDDL_MASK 0x00000600U -/*Reserved. Caution, do not write to this register field.*/ +/* +* Reserved. Caution, do not write to this register field. +*/ #undef DDR_PHY_DX8SL2OSC_RESERVED_8_7_DEFVAL #undef DDR_PHY_DX8SL2OSC_RESERVED_8_7_SHIFT #undef DDR_PHY_DX8SL2OSC_RESERVED_8_7_MASK -#define DDR_PHY_DX8SL2OSC_RESERVED_8_7_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL2OSC_RESERVED_8_7_SHIFT 7 -#define DDR_PHY_DX8SL2OSC_RESERVED_8_7_MASK 0x00000180U +#define DDR_PHY_DX8SL2OSC_RESERVED_8_7_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_RESERVED_8_7_SHIFT 7 +#define DDR_PHY_DX8SL2OSC_RESERVED_8_7_MASK 0x00000180U -/*Oscillator Mode Write-Leveling Delay Line Select*/ +/* +* Oscillator Mode Write-Leveling Delay Line Select +*/ #undef DDR_PHY_DX8SL2OSC_OSCWDL_DEFVAL #undef DDR_PHY_DX8SL2OSC_OSCWDL_SHIFT #undef DDR_PHY_DX8SL2OSC_OSCWDL_MASK -#define DDR_PHY_DX8SL2OSC_OSCWDL_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL2OSC_OSCWDL_SHIFT 5 -#define DDR_PHY_DX8SL2OSC_OSCWDL_MASK 0x00000060U +#define DDR_PHY_DX8SL2OSC_OSCWDL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_OSCWDL_SHIFT 5 +#define DDR_PHY_DX8SL2OSC_OSCWDL_MASK 0x00000060U -/*Oscillator Mode Division*/ +/* +* Oscillator Mode Division +*/ #undef DDR_PHY_DX8SL2OSC_OSCDIV_DEFVAL #undef DDR_PHY_DX8SL2OSC_OSCDIV_SHIFT #undef DDR_PHY_DX8SL2OSC_OSCDIV_MASK -#define DDR_PHY_DX8SL2OSC_OSCDIV_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL2OSC_OSCDIV_SHIFT 1 -#define DDR_PHY_DX8SL2OSC_OSCDIV_MASK 0x0000001EU +#define DDR_PHY_DX8SL2OSC_OSCDIV_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_OSCDIV_SHIFT 1 +#define DDR_PHY_DX8SL2OSC_OSCDIV_MASK 0x0000001EU -/*Oscillator Enable*/ +/* +* Oscillator Enable +*/ #undef DDR_PHY_DX8SL2OSC_OSCEN_DEFVAL #undef DDR_PHY_DX8SL2OSC_OSCEN_SHIFT #undef DDR_PHY_DX8SL2OSC_OSCEN_MASK -#define DDR_PHY_DX8SL2OSC_OSCEN_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL2OSC_OSCEN_SHIFT 0 -#define DDR_PHY_DX8SL2OSC_OSCEN_MASK 0x00000001U +#define DDR_PHY_DX8SL2OSC_OSCEN_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_OSCEN_SHIFT 0 +#define DDR_PHY_DX8SL2OSC_OSCEN_MASK 0x00000001U -/*Reserved. Return zeroes on reads.*/ +/* +* PLL Bypass +*/ +#undef DDR_PHY_DX8SL2PLLCR0_PLLBYP_DEFVAL +#undef DDR_PHY_DX8SL2PLLCR0_PLLBYP_SHIFT +#undef DDR_PHY_DX8SL2PLLCR0_PLLBYP_MASK +#define DDR_PHY_DX8SL2PLLCR0_PLLBYP_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL2PLLCR0_PLLBYP_SHIFT 31 +#define DDR_PHY_DX8SL2PLLCR0_PLLBYP_MASK 0x80000000U + +/* +* PLL Reset +*/ +#undef DDR_PHY_DX8SL2PLLCR0_PLLRST_DEFVAL +#undef DDR_PHY_DX8SL2PLLCR0_PLLRST_SHIFT +#undef DDR_PHY_DX8SL2PLLCR0_PLLRST_MASK +#define DDR_PHY_DX8SL2PLLCR0_PLLRST_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL2PLLCR0_PLLRST_SHIFT 30 +#define DDR_PHY_DX8SL2PLLCR0_PLLRST_MASK 0x40000000U + +/* +* PLL Power Down +*/ +#undef DDR_PHY_DX8SL2PLLCR0_PLLPD_DEFVAL +#undef DDR_PHY_DX8SL2PLLCR0_PLLPD_SHIFT +#undef DDR_PHY_DX8SL2PLLCR0_PLLPD_MASK +#define DDR_PHY_DX8SL2PLLCR0_PLLPD_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL2PLLCR0_PLLPD_SHIFT 29 +#define DDR_PHY_DX8SL2PLLCR0_PLLPD_MASK 0x20000000U + +/* +* Reference Stop Mode +*/ +#undef DDR_PHY_DX8SL2PLLCR0_RSTOPM_DEFVAL +#undef DDR_PHY_DX8SL2PLLCR0_RSTOPM_SHIFT +#undef DDR_PHY_DX8SL2PLLCR0_RSTOPM_MASK +#define DDR_PHY_DX8SL2PLLCR0_RSTOPM_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL2PLLCR0_RSTOPM_SHIFT 28 +#define DDR_PHY_DX8SL2PLLCR0_RSTOPM_MASK 0x10000000U + +/* +* PLL Frequency Select +*/ +#undef DDR_PHY_DX8SL2PLLCR0_FRQSEL_DEFVAL +#undef DDR_PHY_DX8SL2PLLCR0_FRQSEL_SHIFT +#undef DDR_PHY_DX8SL2PLLCR0_FRQSEL_MASK +#define DDR_PHY_DX8SL2PLLCR0_FRQSEL_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL2PLLCR0_FRQSEL_SHIFT 24 +#define DDR_PHY_DX8SL2PLLCR0_FRQSEL_MASK 0x0F000000U + +/* +* Relock Mode +*/ +#undef DDR_PHY_DX8SL2PLLCR0_RLOCKM_DEFVAL +#undef DDR_PHY_DX8SL2PLLCR0_RLOCKM_SHIFT +#undef DDR_PHY_DX8SL2PLLCR0_RLOCKM_MASK +#define DDR_PHY_DX8SL2PLLCR0_RLOCKM_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL2PLLCR0_RLOCKM_SHIFT 23 +#define DDR_PHY_DX8SL2PLLCR0_RLOCKM_MASK 0x00800000U + +/* +* Charge Pump Proportional Current Control +*/ +#undef DDR_PHY_DX8SL2PLLCR0_CPPC_DEFVAL +#undef DDR_PHY_DX8SL2PLLCR0_CPPC_SHIFT +#undef DDR_PHY_DX8SL2PLLCR0_CPPC_MASK +#define DDR_PHY_DX8SL2PLLCR0_CPPC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL2PLLCR0_CPPC_SHIFT 17 +#define DDR_PHY_DX8SL2PLLCR0_CPPC_MASK 0x007E0000U + +/* +* Charge Pump Integrating Current Control +*/ +#undef DDR_PHY_DX8SL2PLLCR0_CPIC_DEFVAL +#undef DDR_PHY_DX8SL2PLLCR0_CPIC_SHIFT +#undef DDR_PHY_DX8SL2PLLCR0_CPIC_MASK +#define DDR_PHY_DX8SL2PLLCR0_CPIC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL2PLLCR0_CPIC_SHIFT 13 +#define DDR_PHY_DX8SL2PLLCR0_CPIC_MASK 0x0001E000U + +/* +* Gear Shift +*/ +#undef DDR_PHY_DX8SL2PLLCR0_GSHIFT_DEFVAL +#undef DDR_PHY_DX8SL2PLLCR0_GSHIFT_SHIFT +#undef DDR_PHY_DX8SL2PLLCR0_GSHIFT_MASK +#define DDR_PHY_DX8SL2PLLCR0_GSHIFT_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL2PLLCR0_GSHIFT_SHIFT 12 +#define DDR_PHY_DX8SL2PLLCR0_GSHIFT_MASK 0x00001000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL2PLLCR0_RESERVED_11_9_DEFVAL +#undef DDR_PHY_DX8SL2PLLCR0_RESERVED_11_9_SHIFT +#undef DDR_PHY_DX8SL2PLLCR0_RESERVED_11_9_MASK +#define DDR_PHY_DX8SL2PLLCR0_RESERVED_11_9_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL2PLLCR0_RESERVED_11_9_SHIFT 9 +#define DDR_PHY_DX8SL2PLLCR0_RESERVED_11_9_MASK 0x00000E00U + +/* +* Analog Test Enable (ATOEN) +*/ +#undef DDR_PHY_DX8SL2PLLCR0_ATOEN_DEFVAL +#undef DDR_PHY_DX8SL2PLLCR0_ATOEN_SHIFT +#undef DDR_PHY_DX8SL2PLLCR0_ATOEN_MASK +#define DDR_PHY_DX8SL2PLLCR0_ATOEN_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL2PLLCR0_ATOEN_SHIFT 8 +#define DDR_PHY_DX8SL2PLLCR0_ATOEN_MASK 0x00000100U + +/* +* Analog Test Control +*/ +#undef DDR_PHY_DX8SL2PLLCR0_ATC_DEFVAL +#undef DDR_PHY_DX8SL2PLLCR0_ATC_SHIFT +#undef DDR_PHY_DX8SL2PLLCR0_ATC_MASK +#define DDR_PHY_DX8SL2PLLCR0_ATC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL2PLLCR0_ATC_SHIFT 4 +#define DDR_PHY_DX8SL2PLLCR0_ATC_MASK 0x000000F0U + +/* +* Digital Test Control +*/ +#undef DDR_PHY_DX8SL2PLLCR0_DTC_DEFVAL +#undef DDR_PHY_DX8SL2PLLCR0_DTC_SHIFT +#undef DDR_PHY_DX8SL2PLLCR0_DTC_MASK +#define DDR_PHY_DX8SL2PLLCR0_DTC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL2PLLCR0_DTC_SHIFT 0 +#define DDR_PHY_DX8SL2PLLCR0_DTC_MASK 0x0000000FU + +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_DEFVAL #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_SHIFT #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_MASK -#define DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_SHIFT 25 -#define DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_MASK 0xFE000000U +#define DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_SHIFT 25 +#define DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_MASK 0xFE000000U -/*Read Path Rise-to-Rise Mode*/ +/* +* Read Path Rise-to-Rise Mode +*/ #undef DDR_PHY_DX8SL2DQSCTL_RRRMODE_DEFVAL #undef DDR_PHY_DX8SL2DQSCTL_RRRMODE_SHIFT #undef DDR_PHY_DX8SL2DQSCTL_RRRMODE_MASK -#define DDR_PHY_DX8SL2DQSCTL_RRRMODE_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL2DQSCTL_RRRMODE_SHIFT 24 -#define DDR_PHY_DX8SL2DQSCTL_RRRMODE_MASK 0x01000000U +#define DDR_PHY_DX8SL2DQSCTL_RRRMODE_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL2DQSCTL_RRRMODE_SHIFT 24 +#define DDR_PHY_DX8SL2DQSCTL_RRRMODE_MASK 0x01000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_DEFVAL #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_SHIFT #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_MASK -#define DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_SHIFT 22 -#define DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_MASK 0x00C00000U +#define DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_MASK 0x00C00000U -/*Write Path Rise-to-Rise Mode*/ +/* +* Write Path Rise-to-Rise Mode +*/ #undef DDR_PHY_DX8SL2DQSCTL_WRRMODE_DEFVAL #undef DDR_PHY_DX8SL2DQSCTL_WRRMODE_SHIFT #undef DDR_PHY_DX8SL2DQSCTL_WRRMODE_MASK -#define DDR_PHY_DX8SL2DQSCTL_WRRMODE_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL2DQSCTL_WRRMODE_SHIFT 21 -#define DDR_PHY_DX8SL2DQSCTL_WRRMODE_MASK 0x00200000U +#define DDR_PHY_DX8SL2DQSCTL_WRRMODE_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL2DQSCTL_WRRMODE_SHIFT 21 +#define DDR_PHY_DX8SL2DQSCTL_WRRMODE_MASK 0x00200000U -/*DQS Gate Extension*/ +/* +* DQS Gate Extension +*/ #undef DDR_PHY_DX8SL2DQSCTL_DQSGX_DEFVAL #undef DDR_PHY_DX8SL2DQSCTL_DQSGX_SHIFT #undef DDR_PHY_DX8SL2DQSCTL_DQSGX_MASK -#define DDR_PHY_DX8SL2DQSCTL_DQSGX_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL2DQSCTL_DQSGX_SHIFT 19 -#define DDR_PHY_DX8SL2DQSCTL_DQSGX_MASK 0x00180000U +#define DDR_PHY_DX8SL2DQSCTL_DQSGX_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL2DQSCTL_DQSGX_SHIFT 19 +#define DDR_PHY_DX8SL2DQSCTL_DQSGX_MASK 0x00180000U -/*Low Power PLL Power Down*/ +/* +* Low Power PLL Power Down +*/ #undef DDR_PHY_DX8SL2DQSCTL_LPPLLPD_DEFVAL #undef DDR_PHY_DX8SL2DQSCTL_LPPLLPD_SHIFT #undef DDR_PHY_DX8SL2DQSCTL_LPPLLPD_MASK -#define DDR_PHY_DX8SL2DQSCTL_LPPLLPD_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL2DQSCTL_LPPLLPD_SHIFT 18 -#define DDR_PHY_DX8SL2DQSCTL_LPPLLPD_MASK 0x00040000U +#define DDR_PHY_DX8SL2DQSCTL_LPPLLPD_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL2DQSCTL_LPPLLPD_SHIFT 18 +#define DDR_PHY_DX8SL2DQSCTL_LPPLLPD_MASK 0x00040000U -/*Low Power I/O Power Down*/ +/* +* Low Power I/O Power Down +*/ #undef DDR_PHY_DX8SL2DQSCTL_LPIOPD_DEFVAL #undef DDR_PHY_DX8SL2DQSCTL_LPIOPD_SHIFT #undef DDR_PHY_DX8SL2DQSCTL_LPIOPD_MASK -#define DDR_PHY_DX8SL2DQSCTL_LPIOPD_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL2DQSCTL_LPIOPD_SHIFT 17 -#define DDR_PHY_DX8SL2DQSCTL_LPIOPD_MASK 0x00020000U +#define DDR_PHY_DX8SL2DQSCTL_LPIOPD_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL2DQSCTL_LPIOPD_SHIFT 17 +#define DDR_PHY_DX8SL2DQSCTL_LPIOPD_MASK 0x00020000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_DEFVAL #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_SHIFT #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_MASK -#define DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_SHIFT 15 -#define DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_MASK 0x00018000U +#define DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_SHIFT 15 +#define DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_MASK 0x00018000U -/*QS Counter Enable*/ +/* +* QS Counter Enable +*/ #undef DDR_PHY_DX8SL2DQSCTL_QSCNTEN_DEFVAL #undef DDR_PHY_DX8SL2DQSCTL_QSCNTEN_SHIFT #undef DDR_PHY_DX8SL2DQSCTL_QSCNTEN_MASK -#define DDR_PHY_DX8SL2DQSCTL_QSCNTEN_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL2DQSCTL_QSCNTEN_SHIFT 14 -#define DDR_PHY_DX8SL2DQSCTL_QSCNTEN_MASK 0x00004000U +#define DDR_PHY_DX8SL2DQSCTL_QSCNTEN_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL2DQSCTL_QSCNTEN_SHIFT 14 +#define DDR_PHY_DX8SL2DQSCTL_QSCNTEN_MASK 0x00004000U -/*Unused DQ I/O Mode*/ +/* +* Unused DQ I/O Mode +*/ #undef DDR_PHY_DX8SL2DQSCTL_UDQIOM_DEFVAL #undef DDR_PHY_DX8SL2DQSCTL_UDQIOM_SHIFT #undef DDR_PHY_DX8SL2DQSCTL_UDQIOM_MASK -#define DDR_PHY_DX8SL2DQSCTL_UDQIOM_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL2DQSCTL_UDQIOM_SHIFT 13 -#define DDR_PHY_DX8SL2DQSCTL_UDQIOM_MASK 0x00002000U +#define DDR_PHY_DX8SL2DQSCTL_UDQIOM_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL2DQSCTL_UDQIOM_SHIFT 13 +#define DDR_PHY_DX8SL2DQSCTL_UDQIOM_MASK 0x00002000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_DEFVAL #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_SHIFT #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_MASK -#define DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_SHIFT 10 -#define DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_MASK 0x00001C00U +#define DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_SHIFT 10 +#define DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_MASK 0x00001C00U -/*Data Slew Rate*/ +/* +* Data Slew Rate +*/ #undef DDR_PHY_DX8SL2DQSCTL_DXSR_DEFVAL #undef DDR_PHY_DX8SL2DQSCTL_DXSR_SHIFT #undef DDR_PHY_DX8SL2DQSCTL_DXSR_MASK -#define DDR_PHY_DX8SL2DQSCTL_DXSR_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL2DQSCTL_DXSR_SHIFT 8 -#define DDR_PHY_DX8SL2DQSCTL_DXSR_MASK 0x00000300U +#define DDR_PHY_DX8SL2DQSCTL_DXSR_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL2DQSCTL_DXSR_SHIFT 8 +#define DDR_PHY_DX8SL2DQSCTL_DXSR_MASK 0x00000300U -/*DQS_N Resistor*/ +/* +* DQS_N Resistor +*/ #undef DDR_PHY_DX8SL2DQSCTL_DQSNRES_DEFVAL #undef DDR_PHY_DX8SL2DQSCTL_DQSNRES_SHIFT #undef DDR_PHY_DX8SL2DQSCTL_DQSNRES_MASK -#define DDR_PHY_DX8SL2DQSCTL_DQSNRES_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL2DQSCTL_DQSNRES_SHIFT 4 -#define DDR_PHY_DX8SL2DQSCTL_DQSNRES_MASK 0x000000F0U +#define DDR_PHY_DX8SL2DQSCTL_DQSNRES_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL2DQSCTL_DQSNRES_SHIFT 4 +#define DDR_PHY_DX8SL2DQSCTL_DQSNRES_MASK 0x000000F0U -/*DQS Resistor*/ +/* +* DQS Resistor +*/ #undef DDR_PHY_DX8SL2DQSCTL_DQSRES_DEFVAL #undef DDR_PHY_DX8SL2DQSCTL_DQSRES_SHIFT #undef DDR_PHY_DX8SL2DQSCTL_DQSRES_MASK -#define DDR_PHY_DX8SL2DQSCTL_DQSRES_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL2DQSCTL_DQSRES_SHIFT 0 -#define DDR_PHY_DX8SL2DQSCTL_DQSRES_MASK 0x0000000FU +#define DDR_PHY_DX8SL2DQSCTL_DQSRES_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL2DQSCTL_DQSRES_SHIFT 0 +#define DDR_PHY_DX8SL2DQSCTL_DQSRES_MASK 0x0000000FU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_DEFVAL #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_SHIFT #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_MASK -#define DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_SHIFT 24 -#define DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_MASK 0xFF000000U +#define DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_SHIFT 24 +#define DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_MASK 0xFF000000U -/*Configurable Read Data Enable*/ +/* +* Configurable Read Data Enable +*/ #undef DDR_PHY_DX8SL2DXCTL2_CRDEN_DEFVAL #undef DDR_PHY_DX8SL2DXCTL2_CRDEN_SHIFT #undef DDR_PHY_DX8SL2DXCTL2_CRDEN_MASK -#define DDR_PHY_DX8SL2DXCTL2_CRDEN_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL2DXCTL2_CRDEN_SHIFT 23 -#define DDR_PHY_DX8SL2DXCTL2_CRDEN_MASK 0x00800000U +#define DDR_PHY_DX8SL2DXCTL2_CRDEN_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_CRDEN_SHIFT 23 +#define DDR_PHY_DX8SL2DXCTL2_CRDEN_MASK 0x00800000U -/*OX Extension during Post-amble*/ +/* +* OX Extension during Post-amble +*/ #undef DDR_PHY_DX8SL2DXCTL2_POSOEX_DEFVAL #undef DDR_PHY_DX8SL2DXCTL2_POSOEX_SHIFT #undef DDR_PHY_DX8SL2DXCTL2_POSOEX_MASK -#define DDR_PHY_DX8SL2DXCTL2_POSOEX_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL2DXCTL2_POSOEX_SHIFT 20 -#define DDR_PHY_DX8SL2DXCTL2_POSOEX_MASK 0x00700000U +#define DDR_PHY_DX8SL2DXCTL2_POSOEX_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_POSOEX_SHIFT 20 +#define DDR_PHY_DX8SL2DXCTL2_POSOEX_MASK 0x00700000U -/*OE Extension during Pre-amble*/ +/* +* OE Extension during Pre-amble +*/ #undef DDR_PHY_DX8SL2DXCTL2_PREOEX_DEFVAL #undef DDR_PHY_DX8SL2DXCTL2_PREOEX_SHIFT #undef DDR_PHY_DX8SL2DXCTL2_PREOEX_MASK -#define DDR_PHY_DX8SL2DXCTL2_PREOEX_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL2DXCTL2_PREOEX_SHIFT 18 -#define DDR_PHY_DX8SL2DXCTL2_PREOEX_MASK 0x000C0000U +#define DDR_PHY_DX8SL2DXCTL2_PREOEX_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_PREOEX_SHIFT 18 +#define DDR_PHY_DX8SL2DXCTL2_PREOEX_MASK 0x000C0000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_17_DEFVAL #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_17_SHIFT #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_17_MASK -#define DDR_PHY_DX8SL2DXCTL2_RESERVED_17_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL2DXCTL2_RESERVED_17_SHIFT 17 -#define DDR_PHY_DX8SL2DXCTL2_RESERVED_17_MASK 0x00020000U +#define DDR_PHY_DX8SL2DXCTL2_RESERVED_17_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_RESERVED_17_SHIFT 17 +#define DDR_PHY_DX8SL2DXCTL2_RESERVED_17_MASK 0x00020000U -/*I/O Assisted Gate Select*/ +/* +* I/O Assisted Gate Select +*/ #undef DDR_PHY_DX8SL2DXCTL2_IOAG_DEFVAL #undef DDR_PHY_DX8SL2DXCTL2_IOAG_SHIFT #undef DDR_PHY_DX8SL2DXCTL2_IOAG_MASK -#define DDR_PHY_DX8SL2DXCTL2_IOAG_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL2DXCTL2_IOAG_SHIFT 16 -#define DDR_PHY_DX8SL2DXCTL2_IOAG_MASK 0x00010000U +#define DDR_PHY_DX8SL2DXCTL2_IOAG_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_IOAG_SHIFT 16 +#define DDR_PHY_DX8SL2DXCTL2_IOAG_MASK 0x00010000U -/*I/O Loopback Select*/ +/* +* I/O Loopback Select +*/ #undef DDR_PHY_DX8SL2DXCTL2_IOLB_DEFVAL #undef DDR_PHY_DX8SL2DXCTL2_IOLB_SHIFT #undef DDR_PHY_DX8SL2DXCTL2_IOLB_MASK -#define DDR_PHY_DX8SL2DXCTL2_IOLB_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL2DXCTL2_IOLB_SHIFT 15 -#define DDR_PHY_DX8SL2DXCTL2_IOLB_MASK 0x00008000U +#define DDR_PHY_DX8SL2DXCTL2_IOLB_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_IOLB_SHIFT 15 +#define DDR_PHY_DX8SL2DXCTL2_IOLB_MASK 0x00008000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_DEFVAL #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_SHIFT #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_MASK -#define DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_SHIFT 13 -#define DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_MASK 0x00006000U +#define DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_SHIFT 13 +#define DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_MASK 0x00006000U -/*Low Power Wakeup Threshold*/ +/* +* Low Power Wakeup Threshold +*/ #undef DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_DEFVAL #undef DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_SHIFT #undef DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_MASK -#define DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_SHIFT 9 -#define DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_MASK 0x00001E00U +#define DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_SHIFT 9 +#define DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_MASK 0x00001E00U -/*Read Data Bus Inversion Enable*/ +/* +* Read Data Bus Inversion Enable +*/ #undef DDR_PHY_DX8SL2DXCTL2_RDBI_DEFVAL #undef DDR_PHY_DX8SL2DXCTL2_RDBI_SHIFT #undef DDR_PHY_DX8SL2DXCTL2_RDBI_MASK -#define DDR_PHY_DX8SL2DXCTL2_RDBI_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL2DXCTL2_RDBI_SHIFT 8 -#define DDR_PHY_DX8SL2DXCTL2_RDBI_MASK 0x00000100U +#define DDR_PHY_DX8SL2DXCTL2_RDBI_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_RDBI_SHIFT 8 +#define DDR_PHY_DX8SL2DXCTL2_RDBI_MASK 0x00000100U -/*Write Data Bus Inversion Enable*/ +/* +* Write Data Bus Inversion Enable +*/ #undef DDR_PHY_DX8SL2DXCTL2_WDBI_DEFVAL #undef DDR_PHY_DX8SL2DXCTL2_WDBI_SHIFT #undef DDR_PHY_DX8SL2DXCTL2_WDBI_MASK -#define DDR_PHY_DX8SL2DXCTL2_WDBI_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL2DXCTL2_WDBI_SHIFT 7 -#define DDR_PHY_DX8SL2DXCTL2_WDBI_MASK 0x00000080U +#define DDR_PHY_DX8SL2DXCTL2_WDBI_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_WDBI_SHIFT 7 +#define DDR_PHY_DX8SL2DXCTL2_WDBI_MASK 0x00000080U -/*PUB Read FIFO Bypass*/ +/* +* PUB Read FIFO Bypass +*/ #undef DDR_PHY_DX8SL2DXCTL2_PRFBYP_DEFVAL #undef DDR_PHY_DX8SL2DXCTL2_PRFBYP_SHIFT #undef DDR_PHY_DX8SL2DXCTL2_PRFBYP_MASK -#define DDR_PHY_DX8SL2DXCTL2_PRFBYP_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL2DXCTL2_PRFBYP_SHIFT 6 -#define DDR_PHY_DX8SL2DXCTL2_PRFBYP_MASK 0x00000040U +#define DDR_PHY_DX8SL2DXCTL2_PRFBYP_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_PRFBYP_SHIFT 6 +#define DDR_PHY_DX8SL2DXCTL2_PRFBYP_MASK 0x00000040U -/*DATX8 Receive FIFO Read Mode*/ +/* +* DATX8 Receive FIFO Read Mode +*/ #undef DDR_PHY_DX8SL2DXCTL2_RDMODE_DEFVAL #undef DDR_PHY_DX8SL2DXCTL2_RDMODE_SHIFT #undef DDR_PHY_DX8SL2DXCTL2_RDMODE_MASK -#define DDR_PHY_DX8SL2DXCTL2_RDMODE_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL2DXCTL2_RDMODE_SHIFT 4 -#define DDR_PHY_DX8SL2DXCTL2_RDMODE_MASK 0x00000030U +#define DDR_PHY_DX8SL2DXCTL2_RDMODE_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_RDMODE_SHIFT 4 +#define DDR_PHY_DX8SL2DXCTL2_RDMODE_MASK 0x00000030U -/*Disables the Read FIFO Reset*/ +/* +* Disables the Read FIFO Reset +*/ #undef DDR_PHY_DX8SL2DXCTL2_DISRST_DEFVAL #undef DDR_PHY_DX8SL2DXCTL2_DISRST_SHIFT #undef DDR_PHY_DX8SL2DXCTL2_DISRST_MASK -#define DDR_PHY_DX8SL2DXCTL2_DISRST_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL2DXCTL2_DISRST_SHIFT 3 -#define DDR_PHY_DX8SL2DXCTL2_DISRST_MASK 0x00000008U +#define DDR_PHY_DX8SL2DXCTL2_DISRST_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_DISRST_SHIFT 3 +#define DDR_PHY_DX8SL2DXCTL2_DISRST_MASK 0x00000008U -/*Read DQS Gate I/O Loopback*/ +/* +* Read DQS Gate I/O Loopback +*/ #undef DDR_PHY_DX8SL2DXCTL2_DQSGLB_DEFVAL #undef DDR_PHY_DX8SL2DXCTL2_DQSGLB_SHIFT #undef DDR_PHY_DX8SL2DXCTL2_DQSGLB_MASK -#define DDR_PHY_DX8SL2DXCTL2_DQSGLB_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL2DXCTL2_DQSGLB_SHIFT 1 -#define DDR_PHY_DX8SL2DXCTL2_DQSGLB_MASK 0x00000006U +#define DDR_PHY_DX8SL2DXCTL2_DQSGLB_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_DQSGLB_SHIFT 1 +#define DDR_PHY_DX8SL2DXCTL2_DQSGLB_MASK 0x00000006U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_0_DEFVAL #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_0_SHIFT #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_0_MASK -#define DDR_PHY_DX8SL2DXCTL2_RESERVED_0_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL2DXCTL2_RESERVED_0_SHIFT 0 -#define DDR_PHY_DX8SL2DXCTL2_RESERVED_0_MASK 0x00000001U +#define DDR_PHY_DX8SL2DXCTL2_RESERVED_0_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_RESERVED_0_SHIFT 0 +#define DDR_PHY_DX8SL2DXCTL2_RESERVED_0_MASK 0x00000001U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL2IOCR_RESERVED_31_DEFVAL #undef DDR_PHY_DX8SL2IOCR_RESERVED_31_SHIFT #undef DDR_PHY_DX8SL2IOCR_RESERVED_31_MASK -#define DDR_PHY_DX8SL2IOCR_RESERVED_31_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL2IOCR_RESERVED_31_SHIFT 31 -#define DDR_PHY_DX8SL2IOCR_RESERVED_31_MASK 0x80000000U +#define DDR_PHY_DX8SL2IOCR_RESERVED_31_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL2IOCR_RESERVED_31_SHIFT 31 +#define DDR_PHY_DX8SL2IOCR_RESERVED_31_MASK 0x80000000U -/*PVREF_DAC REFSEL range select*/ +/* +* PVREF_DAC REFSEL range select +*/ #undef DDR_PHY_DX8SL2IOCR_DXDACRANGE_DEFVAL #undef DDR_PHY_DX8SL2IOCR_DXDACRANGE_SHIFT #undef DDR_PHY_DX8SL2IOCR_DXDACRANGE_MASK -#define DDR_PHY_DX8SL2IOCR_DXDACRANGE_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL2IOCR_DXDACRANGE_SHIFT 28 -#define DDR_PHY_DX8SL2IOCR_DXDACRANGE_MASK 0x70000000U +#define DDR_PHY_DX8SL2IOCR_DXDACRANGE_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL2IOCR_DXDACRANGE_SHIFT 28 +#define DDR_PHY_DX8SL2IOCR_DXDACRANGE_MASK 0x70000000U -/*IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring*/ +/* +* IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring +*/ #undef DDR_PHY_DX8SL2IOCR_DXVREFIOM_DEFVAL #undef DDR_PHY_DX8SL2IOCR_DXVREFIOM_SHIFT #undef DDR_PHY_DX8SL2IOCR_DXVREFIOM_MASK -#define DDR_PHY_DX8SL2IOCR_DXVREFIOM_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL2IOCR_DXVREFIOM_SHIFT 25 -#define DDR_PHY_DX8SL2IOCR_DXVREFIOM_MASK 0x0E000000U +#define DDR_PHY_DX8SL2IOCR_DXVREFIOM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL2IOCR_DXVREFIOM_SHIFT 25 +#define DDR_PHY_DX8SL2IOCR_DXVREFIOM_MASK 0x0E000000U -/*DX IO Mode*/ +/* +* DX IO Mode +*/ #undef DDR_PHY_DX8SL2IOCR_DXIOM_DEFVAL #undef DDR_PHY_DX8SL2IOCR_DXIOM_SHIFT #undef DDR_PHY_DX8SL2IOCR_DXIOM_MASK -#define DDR_PHY_DX8SL2IOCR_DXIOM_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL2IOCR_DXIOM_SHIFT 22 -#define DDR_PHY_DX8SL2IOCR_DXIOM_MASK 0x01C00000U +#define DDR_PHY_DX8SL2IOCR_DXIOM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL2IOCR_DXIOM_SHIFT 22 +#define DDR_PHY_DX8SL2IOCR_DXIOM_MASK 0x01C00000U -/*DX IO Transmitter Mode*/ +/* +* DX IO Transmitter Mode +*/ #undef DDR_PHY_DX8SL2IOCR_DXTXM_DEFVAL #undef DDR_PHY_DX8SL2IOCR_DXTXM_SHIFT #undef DDR_PHY_DX8SL2IOCR_DXTXM_MASK -#define DDR_PHY_DX8SL2IOCR_DXTXM_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL2IOCR_DXTXM_SHIFT 11 -#define DDR_PHY_DX8SL2IOCR_DXTXM_MASK 0x003FF800U +#define DDR_PHY_DX8SL2IOCR_DXTXM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL2IOCR_DXTXM_SHIFT 11 +#define DDR_PHY_DX8SL2IOCR_DXTXM_MASK 0x003FF800U -/*DX IO Receiver Mode*/ +/* +* DX IO Receiver Mode +*/ #undef DDR_PHY_DX8SL2IOCR_DXRXM_DEFVAL #undef DDR_PHY_DX8SL2IOCR_DXRXM_SHIFT #undef DDR_PHY_DX8SL2IOCR_DXRXM_MASK -#define DDR_PHY_DX8SL2IOCR_DXRXM_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL2IOCR_DXRXM_SHIFT 0 -#define DDR_PHY_DX8SL2IOCR_DXRXM_MASK 0x000007FFU +#define DDR_PHY_DX8SL2IOCR_DXRXM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL2IOCR_DXRXM_SHIFT 0 +#define DDR_PHY_DX8SL2IOCR_DXRXM_MASK 0x000007FFU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL3OSC_RESERVED_31_30_DEFVAL #undef DDR_PHY_DX8SL3OSC_RESERVED_31_30_SHIFT #undef DDR_PHY_DX8SL3OSC_RESERVED_31_30_MASK -#define DDR_PHY_DX8SL3OSC_RESERVED_31_30_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL3OSC_RESERVED_31_30_SHIFT 30 -#define DDR_PHY_DX8SL3OSC_RESERVED_31_30_MASK 0xC0000000U +#define DDR_PHY_DX8SL3OSC_RESERVED_31_30_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX8SL3OSC_RESERVED_31_30_MASK 0xC0000000U -/*Enable Clock Gating for DX ddr_clk*/ +/* +* Enable Clock Gating for DX ddr_clk +*/ #undef DDR_PHY_DX8SL3OSC_GATEDXRDCLK_DEFVAL #undef DDR_PHY_DX8SL3OSC_GATEDXRDCLK_SHIFT #undef DDR_PHY_DX8SL3OSC_GATEDXRDCLK_MASK -#define DDR_PHY_DX8SL3OSC_GATEDXRDCLK_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL3OSC_GATEDXRDCLK_SHIFT 28 -#define DDR_PHY_DX8SL3OSC_GATEDXRDCLK_MASK 0x30000000U +#define DDR_PHY_DX8SL3OSC_GATEDXRDCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_GATEDXRDCLK_SHIFT 28 +#define DDR_PHY_DX8SL3OSC_GATEDXRDCLK_MASK 0x30000000U -/*Enable Clock Gating for DX ctl_rd_clk*/ +/* +* Enable Clock Gating for DX ctl_rd_clk +*/ #undef DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_DEFVAL #undef DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_SHIFT #undef DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_MASK -#define DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_SHIFT 26 -#define DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_MASK 0x0C000000U +#define DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_SHIFT 26 +#define DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_MASK 0x0C000000U -/*Enable Clock Gating for DX ctl_clk*/ +/* +* Enable Clock Gating for DX ctl_clk +*/ #undef DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_DEFVAL #undef DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_SHIFT #undef DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_MASK -#define DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_SHIFT 24 -#define DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_MASK 0x03000000U +#define DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_SHIFT 24 +#define DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_MASK 0x03000000U -/*Selects the level to which clocks will be stalled when clock gating is enabled.*/ +/* +* Selects the level to which clocks will be stalled when clock gating is e + * nabled. +*/ #undef DDR_PHY_DX8SL3OSC_CLKLEVEL_DEFVAL #undef DDR_PHY_DX8SL3OSC_CLKLEVEL_SHIFT #undef DDR_PHY_DX8SL3OSC_CLKLEVEL_MASK -#define DDR_PHY_DX8SL3OSC_CLKLEVEL_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL3OSC_CLKLEVEL_SHIFT 22 -#define DDR_PHY_DX8SL3OSC_CLKLEVEL_MASK 0x00C00000U +#define DDR_PHY_DX8SL3OSC_CLKLEVEL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_CLKLEVEL_SHIFT 22 +#define DDR_PHY_DX8SL3OSC_CLKLEVEL_MASK 0x00C00000U -/*Loopback Mode*/ +/* +* Loopback Mode +*/ #undef DDR_PHY_DX8SL3OSC_LBMODE_DEFVAL #undef DDR_PHY_DX8SL3OSC_LBMODE_SHIFT #undef DDR_PHY_DX8SL3OSC_LBMODE_MASK -#define DDR_PHY_DX8SL3OSC_LBMODE_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL3OSC_LBMODE_SHIFT 21 -#define DDR_PHY_DX8SL3OSC_LBMODE_MASK 0x00200000U +#define DDR_PHY_DX8SL3OSC_LBMODE_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_LBMODE_SHIFT 21 +#define DDR_PHY_DX8SL3OSC_LBMODE_MASK 0x00200000U -/*Load GSDQS LCDL with 2x the calibrated GSDQSPRD value*/ +/* +* Load GSDQS LCDL with 2x the calibrated GSDQSPRD value +*/ #undef DDR_PHY_DX8SL3OSC_LBGSDQS_DEFVAL #undef DDR_PHY_DX8SL3OSC_LBGSDQS_SHIFT #undef DDR_PHY_DX8SL3OSC_LBGSDQS_MASK -#define DDR_PHY_DX8SL3OSC_LBGSDQS_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL3OSC_LBGSDQS_SHIFT 20 -#define DDR_PHY_DX8SL3OSC_LBGSDQS_MASK 0x00100000U +#define DDR_PHY_DX8SL3OSC_LBGSDQS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_LBGSDQS_SHIFT 20 +#define DDR_PHY_DX8SL3OSC_LBGSDQS_MASK 0x00100000U -/*Loopback DQS Gating*/ +/* +* Loopback DQS Gating +*/ #undef DDR_PHY_DX8SL3OSC_LBGDQS_DEFVAL #undef DDR_PHY_DX8SL3OSC_LBGDQS_SHIFT #undef DDR_PHY_DX8SL3OSC_LBGDQS_MASK -#define DDR_PHY_DX8SL3OSC_LBGDQS_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL3OSC_LBGDQS_SHIFT 18 -#define DDR_PHY_DX8SL3OSC_LBGDQS_MASK 0x000C0000U +#define DDR_PHY_DX8SL3OSC_LBGDQS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_LBGDQS_SHIFT 18 +#define DDR_PHY_DX8SL3OSC_LBGDQS_MASK 0x000C0000U -/*Loopback DQS Shift*/ +/* +* Loopback DQS Shift +*/ #undef DDR_PHY_DX8SL3OSC_LBDQSS_DEFVAL #undef DDR_PHY_DX8SL3OSC_LBDQSS_SHIFT #undef DDR_PHY_DX8SL3OSC_LBDQSS_MASK -#define DDR_PHY_DX8SL3OSC_LBDQSS_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL3OSC_LBDQSS_SHIFT 17 -#define DDR_PHY_DX8SL3OSC_LBDQSS_MASK 0x00020000U +#define DDR_PHY_DX8SL3OSC_LBDQSS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_LBDQSS_SHIFT 17 +#define DDR_PHY_DX8SL3OSC_LBDQSS_MASK 0x00020000U -/*PHY High-Speed Reset*/ +/* +* PHY High-Speed Reset +*/ #undef DDR_PHY_DX8SL3OSC_PHYHRST_DEFVAL #undef DDR_PHY_DX8SL3OSC_PHYHRST_SHIFT #undef DDR_PHY_DX8SL3OSC_PHYHRST_MASK -#define DDR_PHY_DX8SL3OSC_PHYHRST_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL3OSC_PHYHRST_SHIFT 16 -#define DDR_PHY_DX8SL3OSC_PHYHRST_MASK 0x00010000U +#define DDR_PHY_DX8SL3OSC_PHYHRST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_PHYHRST_SHIFT 16 +#define DDR_PHY_DX8SL3OSC_PHYHRST_MASK 0x00010000U -/*PHY FIFO Reset*/ +/* +* PHY FIFO Reset +*/ #undef DDR_PHY_DX8SL3OSC_PHYFRST_DEFVAL #undef DDR_PHY_DX8SL3OSC_PHYFRST_SHIFT #undef DDR_PHY_DX8SL3OSC_PHYFRST_MASK -#define DDR_PHY_DX8SL3OSC_PHYFRST_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL3OSC_PHYFRST_SHIFT 15 -#define DDR_PHY_DX8SL3OSC_PHYFRST_MASK 0x00008000U +#define DDR_PHY_DX8SL3OSC_PHYFRST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_PHYFRST_SHIFT 15 +#define DDR_PHY_DX8SL3OSC_PHYFRST_MASK 0x00008000U -/*Delay Line Test Start*/ +/* +* Delay Line Test Start +*/ #undef DDR_PHY_DX8SL3OSC_DLTST_DEFVAL #undef DDR_PHY_DX8SL3OSC_DLTST_SHIFT #undef DDR_PHY_DX8SL3OSC_DLTST_MASK -#define DDR_PHY_DX8SL3OSC_DLTST_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL3OSC_DLTST_SHIFT 14 -#define DDR_PHY_DX8SL3OSC_DLTST_MASK 0x00004000U +#define DDR_PHY_DX8SL3OSC_DLTST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_DLTST_SHIFT 14 +#define DDR_PHY_DX8SL3OSC_DLTST_MASK 0x00004000U -/*Delay Line Test Mode*/ +/* +* Delay Line Test Mode +*/ #undef DDR_PHY_DX8SL3OSC_DLTMODE_DEFVAL #undef DDR_PHY_DX8SL3OSC_DLTMODE_SHIFT #undef DDR_PHY_DX8SL3OSC_DLTMODE_MASK -#define DDR_PHY_DX8SL3OSC_DLTMODE_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL3OSC_DLTMODE_SHIFT 13 -#define DDR_PHY_DX8SL3OSC_DLTMODE_MASK 0x00002000U +#define DDR_PHY_DX8SL3OSC_DLTMODE_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_DLTMODE_SHIFT 13 +#define DDR_PHY_DX8SL3OSC_DLTMODE_MASK 0x00002000U -/*Reserved. Caution, do not write to this register field.*/ +/* +* Reserved. Caution, do not write to this register field. +*/ #undef DDR_PHY_DX8SL3OSC_RESERVED_12_11_DEFVAL #undef DDR_PHY_DX8SL3OSC_RESERVED_12_11_SHIFT #undef DDR_PHY_DX8SL3OSC_RESERVED_12_11_MASK -#define DDR_PHY_DX8SL3OSC_RESERVED_12_11_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL3OSC_RESERVED_12_11_SHIFT 11 -#define DDR_PHY_DX8SL3OSC_RESERVED_12_11_MASK 0x00001800U +#define DDR_PHY_DX8SL3OSC_RESERVED_12_11_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_RESERVED_12_11_SHIFT 11 +#define DDR_PHY_DX8SL3OSC_RESERVED_12_11_MASK 0x00001800U -/*Oscillator Mode Write-Data Delay Line Select*/ +/* +* Oscillator Mode Write-Data Delay Line Select +*/ #undef DDR_PHY_DX8SL3OSC_OSCWDDL_DEFVAL #undef DDR_PHY_DX8SL3OSC_OSCWDDL_SHIFT #undef DDR_PHY_DX8SL3OSC_OSCWDDL_MASK -#define DDR_PHY_DX8SL3OSC_OSCWDDL_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL3OSC_OSCWDDL_SHIFT 9 -#define DDR_PHY_DX8SL3OSC_OSCWDDL_MASK 0x00000600U +#define DDR_PHY_DX8SL3OSC_OSCWDDL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_OSCWDDL_SHIFT 9 +#define DDR_PHY_DX8SL3OSC_OSCWDDL_MASK 0x00000600U -/*Reserved. Caution, do not write to this register field.*/ +/* +* Reserved. Caution, do not write to this register field. +*/ #undef DDR_PHY_DX8SL3OSC_RESERVED_8_7_DEFVAL #undef DDR_PHY_DX8SL3OSC_RESERVED_8_7_SHIFT #undef DDR_PHY_DX8SL3OSC_RESERVED_8_7_MASK -#define DDR_PHY_DX8SL3OSC_RESERVED_8_7_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL3OSC_RESERVED_8_7_SHIFT 7 -#define DDR_PHY_DX8SL3OSC_RESERVED_8_7_MASK 0x00000180U +#define DDR_PHY_DX8SL3OSC_RESERVED_8_7_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_RESERVED_8_7_SHIFT 7 +#define DDR_PHY_DX8SL3OSC_RESERVED_8_7_MASK 0x00000180U -/*Oscillator Mode Write-Leveling Delay Line Select*/ +/* +* Oscillator Mode Write-Leveling Delay Line Select +*/ #undef DDR_PHY_DX8SL3OSC_OSCWDL_DEFVAL #undef DDR_PHY_DX8SL3OSC_OSCWDL_SHIFT #undef DDR_PHY_DX8SL3OSC_OSCWDL_MASK -#define DDR_PHY_DX8SL3OSC_OSCWDL_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL3OSC_OSCWDL_SHIFT 5 -#define DDR_PHY_DX8SL3OSC_OSCWDL_MASK 0x00000060U +#define DDR_PHY_DX8SL3OSC_OSCWDL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_OSCWDL_SHIFT 5 +#define DDR_PHY_DX8SL3OSC_OSCWDL_MASK 0x00000060U -/*Oscillator Mode Division*/ +/* +* Oscillator Mode Division +*/ #undef DDR_PHY_DX8SL3OSC_OSCDIV_DEFVAL #undef DDR_PHY_DX8SL3OSC_OSCDIV_SHIFT #undef DDR_PHY_DX8SL3OSC_OSCDIV_MASK -#define DDR_PHY_DX8SL3OSC_OSCDIV_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL3OSC_OSCDIV_SHIFT 1 -#define DDR_PHY_DX8SL3OSC_OSCDIV_MASK 0x0000001EU +#define DDR_PHY_DX8SL3OSC_OSCDIV_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_OSCDIV_SHIFT 1 +#define DDR_PHY_DX8SL3OSC_OSCDIV_MASK 0x0000001EU -/*Oscillator Enable*/ +/* +* Oscillator Enable +*/ #undef DDR_PHY_DX8SL3OSC_OSCEN_DEFVAL #undef DDR_PHY_DX8SL3OSC_OSCEN_SHIFT #undef DDR_PHY_DX8SL3OSC_OSCEN_MASK -#define DDR_PHY_DX8SL3OSC_OSCEN_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL3OSC_OSCEN_SHIFT 0 -#define DDR_PHY_DX8SL3OSC_OSCEN_MASK 0x00000001U +#define DDR_PHY_DX8SL3OSC_OSCEN_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_OSCEN_SHIFT 0 +#define DDR_PHY_DX8SL3OSC_OSCEN_MASK 0x00000001U -/*Reserved. Return zeroes on reads.*/ +/* +* PLL Bypass +*/ +#undef DDR_PHY_DX8SL3PLLCR0_PLLBYP_DEFVAL +#undef DDR_PHY_DX8SL3PLLCR0_PLLBYP_SHIFT +#undef DDR_PHY_DX8SL3PLLCR0_PLLBYP_MASK +#define DDR_PHY_DX8SL3PLLCR0_PLLBYP_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL3PLLCR0_PLLBYP_SHIFT 31 +#define DDR_PHY_DX8SL3PLLCR0_PLLBYP_MASK 0x80000000U + +/* +* PLL Reset +*/ +#undef DDR_PHY_DX8SL3PLLCR0_PLLRST_DEFVAL +#undef DDR_PHY_DX8SL3PLLCR0_PLLRST_SHIFT +#undef DDR_PHY_DX8SL3PLLCR0_PLLRST_MASK +#define DDR_PHY_DX8SL3PLLCR0_PLLRST_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL3PLLCR0_PLLRST_SHIFT 30 +#define DDR_PHY_DX8SL3PLLCR0_PLLRST_MASK 0x40000000U + +/* +* PLL Power Down +*/ +#undef DDR_PHY_DX8SL3PLLCR0_PLLPD_DEFVAL +#undef DDR_PHY_DX8SL3PLLCR0_PLLPD_SHIFT +#undef DDR_PHY_DX8SL3PLLCR0_PLLPD_MASK +#define DDR_PHY_DX8SL3PLLCR0_PLLPD_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL3PLLCR0_PLLPD_SHIFT 29 +#define DDR_PHY_DX8SL3PLLCR0_PLLPD_MASK 0x20000000U + +/* +* Reference Stop Mode +*/ +#undef DDR_PHY_DX8SL3PLLCR0_RSTOPM_DEFVAL +#undef DDR_PHY_DX8SL3PLLCR0_RSTOPM_SHIFT +#undef DDR_PHY_DX8SL3PLLCR0_RSTOPM_MASK +#define DDR_PHY_DX8SL3PLLCR0_RSTOPM_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL3PLLCR0_RSTOPM_SHIFT 28 +#define DDR_PHY_DX8SL3PLLCR0_RSTOPM_MASK 0x10000000U + +/* +* PLL Frequency Select +*/ +#undef DDR_PHY_DX8SL3PLLCR0_FRQSEL_DEFVAL +#undef DDR_PHY_DX8SL3PLLCR0_FRQSEL_SHIFT +#undef DDR_PHY_DX8SL3PLLCR0_FRQSEL_MASK +#define DDR_PHY_DX8SL3PLLCR0_FRQSEL_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL3PLLCR0_FRQSEL_SHIFT 24 +#define DDR_PHY_DX8SL3PLLCR0_FRQSEL_MASK 0x0F000000U + +/* +* Relock Mode +*/ +#undef DDR_PHY_DX8SL3PLLCR0_RLOCKM_DEFVAL +#undef DDR_PHY_DX8SL3PLLCR0_RLOCKM_SHIFT +#undef DDR_PHY_DX8SL3PLLCR0_RLOCKM_MASK +#define DDR_PHY_DX8SL3PLLCR0_RLOCKM_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL3PLLCR0_RLOCKM_SHIFT 23 +#define DDR_PHY_DX8SL3PLLCR0_RLOCKM_MASK 0x00800000U + +/* +* Charge Pump Proportional Current Control +*/ +#undef DDR_PHY_DX8SL3PLLCR0_CPPC_DEFVAL +#undef DDR_PHY_DX8SL3PLLCR0_CPPC_SHIFT +#undef DDR_PHY_DX8SL3PLLCR0_CPPC_MASK +#define DDR_PHY_DX8SL3PLLCR0_CPPC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL3PLLCR0_CPPC_SHIFT 17 +#define DDR_PHY_DX8SL3PLLCR0_CPPC_MASK 0x007E0000U + +/* +* Charge Pump Integrating Current Control +*/ +#undef DDR_PHY_DX8SL3PLLCR0_CPIC_DEFVAL +#undef DDR_PHY_DX8SL3PLLCR0_CPIC_SHIFT +#undef DDR_PHY_DX8SL3PLLCR0_CPIC_MASK +#define DDR_PHY_DX8SL3PLLCR0_CPIC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL3PLLCR0_CPIC_SHIFT 13 +#define DDR_PHY_DX8SL3PLLCR0_CPIC_MASK 0x0001E000U + +/* +* Gear Shift +*/ +#undef DDR_PHY_DX8SL3PLLCR0_GSHIFT_DEFVAL +#undef DDR_PHY_DX8SL3PLLCR0_GSHIFT_SHIFT +#undef DDR_PHY_DX8SL3PLLCR0_GSHIFT_MASK +#define DDR_PHY_DX8SL3PLLCR0_GSHIFT_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL3PLLCR0_GSHIFT_SHIFT 12 +#define DDR_PHY_DX8SL3PLLCR0_GSHIFT_MASK 0x00001000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL3PLLCR0_RESERVED_11_9_DEFVAL +#undef DDR_PHY_DX8SL3PLLCR0_RESERVED_11_9_SHIFT +#undef DDR_PHY_DX8SL3PLLCR0_RESERVED_11_9_MASK +#define DDR_PHY_DX8SL3PLLCR0_RESERVED_11_9_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL3PLLCR0_RESERVED_11_9_SHIFT 9 +#define DDR_PHY_DX8SL3PLLCR0_RESERVED_11_9_MASK 0x00000E00U + +/* +* Analog Test Enable (ATOEN) +*/ +#undef DDR_PHY_DX8SL3PLLCR0_ATOEN_DEFVAL +#undef DDR_PHY_DX8SL3PLLCR0_ATOEN_SHIFT +#undef DDR_PHY_DX8SL3PLLCR0_ATOEN_MASK +#define DDR_PHY_DX8SL3PLLCR0_ATOEN_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL3PLLCR0_ATOEN_SHIFT 8 +#define DDR_PHY_DX8SL3PLLCR0_ATOEN_MASK 0x00000100U + +/* +* Analog Test Control +*/ +#undef DDR_PHY_DX8SL3PLLCR0_ATC_DEFVAL +#undef DDR_PHY_DX8SL3PLLCR0_ATC_SHIFT +#undef DDR_PHY_DX8SL3PLLCR0_ATC_MASK +#define DDR_PHY_DX8SL3PLLCR0_ATC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL3PLLCR0_ATC_SHIFT 4 +#define DDR_PHY_DX8SL3PLLCR0_ATC_MASK 0x000000F0U + +/* +* Digital Test Control +*/ +#undef DDR_PHY_DX8SL3PLLCR0_DTC_DEFVAL +#undef DDR_PHY_DX8SL3PLLCR0_DTC_SHIFT +#undef DDR_PHY_DX8SL3PLLCR0_DTC_MASK +#define DDR_PHY_DX8SL3PLLCR0_DTC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL3PLLCR0_DTC_SHIFT 0 +#define DDR_PHY_DX8SL3PLLCR0_DTC_MASK 0x0000000FU + +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_DEFVAL #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_SHIFT #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_MASK -#define DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_SHIFT 25 -#define DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_MASK 0xFE000000U +#define DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_SHIFT 25 +#define DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_MASK 0xFE000000U -/*Read Path Rise-to-Rise Mode*/ +/* +* Read Path Rise-to-Rise Mode +*/ #undef DDR_PHY_DX8SL3DQSCTL_RRRMODE_DEFVAL #undef DDR_PHY_DX8SL3DQSCTL_RRRMODE_SHIFT #undef DDR_PHY_DX8SL3DQSCTL_RRRMODE_MASK -#define DDR_PHY_DX8SL3DQSCTL_RRRMODE_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL3DQSCTL_RRRMODE_SHIFT 24 -#define DDR_PHY_DX8SL3DQSCTL_RRRMODE_MASK 0x01000000U +#define DDR_PHY_DX8SL3DQSCTL_RRRMODE_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL3DQSCTL_RRRMODE_SHIFT 24 +#define DDR_PHY_DX8SL3DQSCTL_RRRMODE_MASK 0x01000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_DEFVAL #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_SHIFT #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_MASK -#define DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_SHIFT 22 -#define DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_MASK 0x00C00000U +#define DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_MASK 0x00C00000U -/*Write Path Rise-to-Rise Mode*/ +/* +* Write Path Rise-to-Rise Mode +*/ #undef DDR_PHY_DX8SL3DQSCTL_WRRMODE_DEFVAL #undef DDR_PHY_DX8SL3DQSCTL_WRRMODE_SHIFT #undef DDR_PHY_DX8SL3DQSCTL_WRRMODE_MASK -#define DDR_PHY_DX8SL3DQSCTL_WRRMODE_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL3DQSCTL_WRRMODE_SHIFT 21 -#define DDR_PHY_DX8SL3DQSCTL_WRRMODE_MASK 0x00200000U +#define DDR_PHY_DX8SL3DQSCTL_WRRMODE_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL3DQSCTL_WRRMODE_SHIFT 21 +#define DDR_PHY_DX8SL3DQSCTL_WRRMODE_MASK 0x00200000U -/*DQS Gate Extension*/ +/* +* DQS Gate Extension +*/ #undef DDR_PHY_DX8SL3DQSCTL_DQSGX_DEFVAL #undef DDR_PHY_DX8SL3DQSCTL_DQSGX_SHIFT #undef DDR_PHY_DX8SL3DQSCTL_DQSGX_MASK -#define DDR_PHY_DX8SL3DQSCTL_DQSGX_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL3DQSCTL_DQSGX_SHIFT 19 -#define DDR_PHY_DX8SL3DQSCTL_DQSGX_MASK 0x00180000U +#define DDR_PHY_DX8SL3DQSCTL_DQSGX_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL3DQSCTL_DQSGX_SHIFT 19 +#define DDR_PHY_DX8SL3DQSCTL_DQSGX_MASK 0x00180000U -/*Low Power PLL Power Down*/ +/* +* Low Power PLL Power Down +*/ #undef DDR_PHY_DX8SL3DQSCTL_LPPLLPD_DEFVAL #undef DDR_PHY_DX8SL3DQSCTL_LPPLLPD_SHIFT #undef DDR_PHY_DX8SL3DQSCTL_LPPLLPD_MASK -#define DDR_PHY_DX8SL3DQSCTL_LPPLLPD_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL3DQSCTL_LPPLLPD_SHIFT 18 -#define DDR_PHY_DX8SL3DQSCTL_LPPLLPD_MASK 0x00040000U +#define DDR_PHY_DX8SL3DQSCTL_LPPLLPD_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL3DQSCTL_LPPLLPD_SHIFT 18 +#define DDR_PHY_DX8SL3DQSCTL_LPPLLPD_MASK 0x00040000U -/*Low Power I/O Power Down*/ +/* +* Low Power I/O Power Down +*/ #undef DDR_PHY_DX8SL3DQSCTL_LPIOPD_DEFVAL #undef DDR_PHY_DX8SL3DQSCTL_LPIOPD_SHIFT #undef DDR_PHY_DX8SL3DQSCTL_LPIOPD_MASK -#define DDR_PHY_DX8SL3DQSCTL_LPIOPD_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL3DQSCTL_LPIOPD_SHIFT 17 -#define DDR_PHY_DX8SL3DQSCTL_LPIOPD_MASK 0x00020000U +#define DDR_PHY_DX8SL3DQSCTL_LPIOPD_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL3DQSCTL_LPIOPD_SHIFT 17 +#define DDR_PHY_DX8SL3DQSCTL_LPIOPD_MASK 0x00020000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_DEFVAL #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_SHIFT #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_MASK -#define DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_SHIFT 15 -#define DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_MASK 0x00018000U +#define DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_SHIFT 15 +#define DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_MASK 0x00018000U -/*QS Counter Enable*/ +/* +* QS Counter Enable +*/ #undef DDR_PHY_DX8SL3DQSCTL_QSCNTEN_DEFVAL #undef DDR_PHY_DX8SL3DQSCTL_QSCNTEN_SHIFT #undef DDR_PHY_DX8SL3DQSCTL_QSCNTEN_MASK -#define DDR_PHY_DX8SL3DQSCTL_QSCNTEN_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL3DQSCTL_QSCNTEN_SHIFT 14 -#define DDR_PHY_DX8SL3DQSCTL_QSCNTEN_MASK 0x00004000U +#define DDR_PHY_DX8SL3DQSCTL_QSCNTEN_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL3DQSCTL_QSCNTEN_SHIFT 14 +#define DDR_PHY_DX8SL3DQSCTL_QSCNTEN_MASK 0x00004000U -/*Unused DQ I/O Mode*/ +/* +* Unused DQ I/O Mode +*/ #undef DDR_PHY_DX8SL3DQSCTL_UDQIOM_DEFVAL #undef DDR_PHY_DX8SL3DQSCTL_UDQIOM_SHIFT #undef DDR_PHY_DX8SL3DQSCTL_UDQIOM_MASK -#define DDR_PHY_DX8SL3DQSCTL_UDQIOM_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL3DQSCTL_UDQIOM_SHIFT 13 -#define DDR_PHY_DX8SL3DQSCTL_UDQIOM_MASK 0x00002000U +#define DDR_PHY_DX8SL3DQSCTL_UDQIOM_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL3DQSCTL_UDQIOM_SHIFT 13 +#define DDR_PHY_DX8SL3DQSCTL_UDQIOM_MASK 0x00002000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_DEFVAL #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_SHIFT #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_MASK -#define DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_SHIFT 10 -#define DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_MASK 0x00001C00U +#define DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_SHIFT 10 +#define DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_MASK 0x00001C00U -/*Data Slew Rate*/ +/* +* Data Slew Rate +*/ #undef DDR_PHY_DX8SL3DQSCTL_DXSR_DEFVAL #undef DDR_PHY_DX8SL3DQSCTL_DXSR_SHIFT #undef DDR_PHY_DX8SL3DQSCTL_DXSR_MASK -#define DDR_PHY_DX8SL3DQSCTL_DXSR_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL3DQSCTL_DXSR_SHIFT 8 -#define DDR_PHY_DX8SL3DQSCTL_DXSR_MASK 0x00000300U +#define DDR_PHY_DX8SL3DQSCTL_DXSR_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL3DQSCTL_DXSR_SHIFT 8 +#define DDR_PHY_DX8SL3DQSCTL_DXSR_MASK 0x00000300U -/*DQS_N Resistor*/ +/* +* DQS_N Resistor +*/ #undef DDR_PHY_DX8SL3DQSCTL_DQSNRES_DEFVAL #undef DDR_PHY_DX8SL3DQSCTL_DQSNRES_SHIFT #undef DDR_PHY_DX8SL3DQSCTL_DQSNRES_MASK -#define DDR_PHY_DX8SL3DQSCTL_DQSNRES_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL3DQSCTL_DQSNRES_SHIFT 4 -#define DDR_PHY_DX8SL3DQSCTL_DQSNRES_MASK 0x000000F0U +#define DDR_PHY_DX8SL3DQSCTL_DQSNRES_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL3DQSCTL_DQSNRES_SHIFT 4 +#define DDR_PHY_DX8SL3DQSCTL_DQSNRES_MASK 0x000000F0U -/*DQS Resistor*/ +/* +* DQS Resistor +*/ #undef DDR_PHY_DX8SL3DQSCTL_DQSRES_DEFVAL #undef DDR_PHY_DX8SL3DQSCTL_DQSRES_SHIFT #undef DDR_PHY_DX8SL3DQSCTL_DQSRES_MASK -#define DDR_PHY_DX8SL3DQSCTL_DQSRES_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL3DQSCTL_DQSRES_SHIFT 0 -#define DDR_PHY_DX8SL3DQSCTL_DQSRES_MASK 0x0000000FU +#define DDR_PHY_DX8SL3DQSCTL_DQSRES_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL3DQSCTL_DQSRES_SHIFT 0 +#define DDR_PHY_DX8SL3DQSCTL_DQSRES_MASK 0x0000000FU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_DEFVAL #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_SHIFT #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_MASK -#define DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_SHIFT 24 -#define DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_MASK 0xFF000000U +#define DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_SHIFT 24 +#define DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_MASK 0xFF000000U -/*Configurable Read Data Enable*/ +/* +* Configurable Read Data Enable +*/ #undef DDR_PHY_DX8SL3DXCTL2_CRDEN_DEFVAL #undef DDR_PHY_DX8SL3DXCTL2_CRDEN_SHIFT #undef DDR_PHY_DX8SL3DXCTL2_CRDEN_MASK -#define DDR_PHY_DX8SL3DXCTL2_CRDEN_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL3DXCTL2_CRDEN_SHIFT 23 -#define DDR_PHY_DX8SL3DXCTL2_CRDEN_MASK 0x00800000U +#define DDR_PHY_DX8SL3DXCTL2_CRDEN_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_CRDEN_SHIFT 23 +#define DDR_PHY_DX8SL3DXCTL2_CRDEN_MASK 0x00800000U -/*OX Extension during Post-amble*/ +/* +* OX Extension during Post-amble +*/ #undef DDR_PHY_DX8SL3DXCTL2_POSOEX_DEFVAL #undef DDR_PHY_DX8SL3DXCTL2_POSOEX_SHIFT #undef DDR_PHY_DX8SL3DXCTL2_POSOEX_MASK -#define DDR_PHY_DX8SL3DXCTL2_POSOEX_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL3DXCTL2_POSOEX_SHIFT 20 -#define DDR_PHY_DX8SL3DXCTL2_POSOEX_MASK 0x00700000U +#define DDR_PHY_DX8SL3DXCTL2_POSOEX_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_POSOEX_SHIFT 20 +#define DDR_PHY_DX8SL3DXCTL2_POSOEX_MASK 0x00700000U -/*OE Extension during Pre-amble*/ +/* +* OE Extension during Pre-amble +*/ #undef DDR_PHY_DX8SL3DXCTL2_PREOEX_DEFVAL #undef DDR_PHY_DX8SL3DXCTL2_PREOEX_SHIFT #undef DDR_PHY_DX8SL3DXCTL2_PREOEX_MASK -#define DDR_PHY_DX8SL3DXCTL2_PREOEX_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL3DXCTL2_PREOEX_SHIFT 18 -#define DDR_PHY_DX8SL3DXCTL2_PREOEX_MASK 0x000C0000U +#define DDR_PHY_DX8SL3DXCTL2_PREOEX_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_PREOEX_SHIFT 18 +#define DDR_PHY_DX8SL3DXCTL2_PREOEX_MASK 0x000C0000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_17_DEFVAL #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_17_SHIFT #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_17_MASK -#define DDR_PHY_DX8SL3DXCTL2_RESERVED_17_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL3DXCTL2_RESERVED_17_SHIFT 17 -#define DDR_PHY_DX8SL3DXCTL2_RESERVED_17_MASK 0x00020000U +#define DDR_PHY_DX8SL3DXCTL2_RESERVED_17_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_RESERVED_17_SHIFT 17 +#define DDR_PHY_DX8SL3DXCTL2_RESERVED_17_MASK 0x00020000U -/*I/O Assisted Gate Select*/ +/* +* I/O Assisted Gate Select +*/ #undef DDR_PHY_DX8SL3DXCTL2_IOAG_DEFVAL #undef DDR_PHY_DX8SL3DXCTL2_IOAG_SHIFT #undef DDR_PHY_DX8SL3DXCTL2_IOAG_MASK -#define DDR_PHY_DX8SL3DXCTL2_IOAG_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL3DXCTL2_IOAG_SHIFT 16 -#define DDR_PHY_DX8SL3DXCTL2_IOAG_MASK 0x00010000U +#define DDR_PHY_DX8SL3DXCTL2_IOAG_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_IOAG_SHIFT 16 +#define DDR_PHY_DX8SL3DXCTL2_IOAG_MASK 0x00010000U -/*I/O Loopback Select*/ +/* +* I/O Loopback Select +*/ #undef DDR_PHY_DX8SL3DXCTL2_IOLB_DEFVAL #undef DDR_PHY_DX8SL3DXCTL2_IOLB_SHIFT #undef DDR_PHY_DX8SL3DXCTL2_IOLB_MASK -#define DDR_PHY_DX8SL3DXCTL2_IOLB_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL3DXCTL2_IOLB_SHIFT 15 -#define DDR_PHY_DX8SL3DXCTL2_IOLB_MASK 0x00008000U +#define DDR_PHY_DX8SL3DXCTL2_IOLB_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_IOLB_SHIFT 15 +#define DDR_PHY_DX8SL3DXCTL2_IOLB_MASK 0x00008000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_DEFVAL #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_SHIFT #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_MASK -#define DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_SHIFT 13 -#define DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_MASK 0x00006000U +#define DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_SHIFT 13 +#define DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_MASK 0x00006000U -/*Low Power Wakeup Threshold*/ +/* +* Low Power Wakeup Threshold +*/ #undef DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_DEFVAL #undef DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_SHIFT #undef DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_MASK -#define DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_SHIFT 9 -#define DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_MASK 0x00001E00U +#define DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_SHIFT 9 +#define DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_MASK 0x00001E00U -/*Read Data Bus Inversion Enable*/ +/* +* Read Data Bus Inversion Enable +*/ #undef DDR_PHY_DX8SL3DXCTL2_RDBI_DEFVAL #undef DDR_PHY_DX8SL3DXCTL2_RDBI_SHIFT #undef DDR_PHY_DX8SL3DXCTL2_RDBI_MASK -#define DDR_PHY_DX8SL3DXCTL2_RDBI_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL3DXCTL2_RDBI_SHIFT 8 -#define DDR_PHY_DX8SL3DXCTL2_RDBI_MASK 0x00000100U +#define DDR_PHY_DX8SL3DXCTL2_RDBI_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_RDBI_SHIFT 8 +#define DDR_PHY_DX8SL3DXCTL2_RDBI_MASK 0x00000100U -/*Write Data Bus Inversion Enable*/ +/* +* Write Data Bus Inversion Enable +*/ #undef DDR_PHY_DX8SL3DXCTL2_WDBI_DEFVAL #undef DDR_PHY_DX8SL3DXCTL2_WDBI_SHIFT #undef DDR_PHY_DX8SL3DXCTL2_WDBI_MASK -#define DDR_PHY_DX8SL3DXCTL2_WDBI_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL3DXCTL2_WDBI_SHIFT 7 -#define DDR_PHY_DX8SL3DXCTL2_WDBI_MASK 0x00000080U +#define DDR_PHY_DX8SL3DXCTL2_WDBI_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_WDBI_SHIFT 7 +#define DDR_PHY_DX8SL3DXCTL2_WDBI_MASK 0x00000080U -/*PUB Read FIFO Bypass*/ +/* +* PUB Read FIFO Bypass +*/ #undef DDR_PHY_DX8SL3DXCTL2_PRFBYP_DEFVAL #undef DDR_PHY_DX8SL3DXCTL2_PRFBYP_SHIFT #undef DDR_PHY_DX8SL3DXCTL2_PRFBYP_MASK -#define DDR_PHY_DX8SL3DXCTL2_PRFBYP_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL3DXCTL2_PRFBYP_SHIFT 6 -#define DDR_PHY_DX8SL3DXCTL2_PRFBYP_MASK 0x00000040U +#define DDR_PHY_DX8SL3DXCTL2_PRFBYP_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_PRFBYP_SHIFT 6 +#define DDR_PHY_DX8SL3DXCTL2_PRFBYP_MASK 0x00000040U -/*DATX8 Receive FIFO Read Mode*/ +/* +* DATX8 Receive FIFO Read Mode +*/ #undef DDR_PHY_DX8SL3DXCTL2_RDMODE_DEFVAL #undef DDR_PHY_DX8SL3DXCTL2_RDMODE_SHIFT #undef DDR_PHY_DX8SL3DXCTL2_RDMODE_MASK -#define DDR_PHY_DX8SL3DXCTL2_RDMODE_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL3DXCTL2_RDMODE_SHIFT 4 -#define DDR_PHY_DX8SL3DXCTL2_RDMODE_MASK 0x00000030U +#define DDR_PHY_DX8SL3DXCTL2_RDMODE_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_RDMODE_SHIFT 4 +#define DDR_PHY_DX8SL3DXCTL2_RDMODE_MASK 0x00000030U -/*Disables the Read FIFO Reset*/ +/* +* Disables the Read FIFO Reset +*/ #undef DDR_PHY_DX8SL3DXCTL2_DISRST_DEFVAL #undef DDR_PHY_DX8SL3DXCTL2_DISRST_SHIFT #undef DDR_PHY_DX8SL3DXCTL2_DISRST_MASK -#define DDR_PHY_DX8SL3DXCTL2_DISRST_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL3DXCTL2_DISRST_SHIFT 3 -#define DDR_PHY_DX8SL3DXCTL2_DISRST_MASK 0x00000008U +#define DDR_PHY_DX8SL3DXCTL2_DISRST_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_DISRST_SHIFT 3 +#define DDR_PHY_DX8SL3DXCTL2_DISRST_MASK 0x00000008U -/*Read DQS Gate I/O Loopback*/ +/* +* Read DQS Gate I/O Loopback +*/ #undef DDR_PHY_DX8SL3DXCTL2_DQSGLB_DEFVAL #undef DDR_PHY_DX8SL3DXCTL2_DQSGLB_SHIFT #undef DDR_PHY_DX8SL3DXCTL2_DQSGLB_MASK -#define DDR_PHY_DX8SL3DXCTL2_DQSGLB_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL3DXCTL2_DQSGLB_SHIFT 1 -#define DDR_PHY_DX8SL3DXCTL2_DQSGLB_MASK 0x00000006U +#define DDR_PHY_DX8SL3DXCTL2_DQSGLB_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_DQSGLB_SHIFT 1 +#define DDR_PHY_DX8SL3DXCTL2_DQSGLB_MASK 0x00000006U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_0_DEFVAL #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_0_SHIFT #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_0_MASK -#define DDR_PHY_DX8SL3DXCTL2_RESERVED_0_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL3DXCTL2_RESERVED_0_SHIFT 0 -#define DDR_PHY_DX8SL3DXCTL2_RESERVED_0_MASK 0x00000001U +#define DDR_PHY_DX8SL3DXCTL2_RESERVED_0_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_RESERVED_0_SHIFT 0 +#define DDR_PHY_DX8SL3DXCTL2_RESERVED_0_MASK 0x00000001U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL3IOCR_RESERVED_31_DEFVAL #undef DDR_PHY_DX8SL3IOCR_RESERVED_31_SHIFT #undef DDR_PHY_DX8SL3IOCR_RESERVED_31_MASK -#define DDR_PHY_DX8SL3IOCR_RESERVED_31_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL3IOCR_RESERVED_31_SHIFT 31 -#define DDR_PHY_DX8SL3IOCR_RESERVED_31_MASK 0x80000000U +#define DDR_PHY_DX8SL3IOCR_RESERVED_31_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL3IOCR_RESERVED_31_SHIFT 31 +#define DDR_PHY_DX8SL3IOCR_RESERVED_31_MASK 0x80000000U -/*PVREF_DAC REFSEL range select*/ +/* +* PVREF_DAC REFSEL range select +*/ #undef DDR_PHY_DX8SL3IOCR_DXDACRANGE_DEFVAL #undef DDR_PHY_DX8SL3IOCR_DXDACRANGE_SHIFT #undef DDR_PHY_DX8SL3IOCR_DXDACRANGE_MASK -#define DDR_PHY_DX8SL3IOCR_DXDACRANGE_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL3IOCR_DXDACRANGE_SHIFT 28 -#define DDR_PHY_DX8SL3IOCR_DXDACRANGE_MASK 0x70000000U +#define DDR_PHY_DX8SL3IOCR_DXDACRANGE_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL3IOCR_DXDACRANGE_SHIFT 28 +#define DDR_PHY_DX8SL3IOCR_DXDACRANGE_MASK 0x70000000U -/*IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring*/ +/* +* IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring +*/ #undef DDR_PHY_DX8SL3IOCR_DXVREFIOM_DEFVAL #undef DDR_PHY_DX8SL3IOCR_DXVREFIOM_SHIFT #undef DDR_PHY_DX8SL3IOCR_DXVREFIOM_MASK -#define DDR_PHY_DX8SL3IOCR_DXVREFIOM_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL3IOCR_DXVREFIOM_SHIFT 25 -#define DDR_PHY_DX8SL3IOCR_DXVREFIOM_MASK 0x0E000000U +#define DDR_PHY_DX8SL3IOCR_DXVREFIOM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL3IOCR_DXVREFIOM_SHIFT 25 +#define DDR_PHY_DX8SL3IOCR_DXVREFIOM_MASK 0x0E000000U -/*DX IO Mode*/ +/* +* DX IO Mode +*/ #undef DDR_PHY_DX8SL3IOCR_DXIOM_DEFVAL #undef DDR_PHY_DX8SL3IOCR_DXIOM_SHIFT #undef DDR_PHY_DX8SL3IOCR_DXIOM_MASK -#define DDR_PHY_DX8SL3IOCR_DXIOM_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL3IOCR_DXIOM_SHIFT 22 -#define DDR_PHY_DX8SL3IOCR_DXIOM_MASK 0x01C00000U +#define DDR_PHY_DX8SL3IOCR_DXIOM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL3IOCR_DXIOM_SHIFT 22 +#define DDR_PHY_DX8SL3IOCR_DXIOM_MASK 0x01C00000U -/*DX IO Transmitter Mode*/ +/* +* DX IO Transmitter Mode +*/ #undef DDR_PHY_DX8SL3IOCR_DXTXM_DEFVAL #undef DDR_PHY_DX8SL3IOCR_DXTXM_SHIFT #undef DDR_PHY_DX8SL3IOCR_DXTXM_MASK -#define DDR_PHY_DX8SL3IOCR_DXTXM_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL3IOCR_DXTXM_SHIFT 11 -#define DDR_PHY_DX8SL3IOCR_DXTXM_MASK 0x003FF800U +#define DDR_PHY_DX8SL3IOCR_DXTXM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL3IOCR_DXTXM_SHIFT 11 +#define DDR_PHY_DX8SL3IOCR_DXTXM_MASK 0x003FF800U -/*DX IO Receiver Mode*/ +/* +* DX IO Receiver Mode +*/ #undef DDR_PHY_DX8SL3IOCR_DXRXM_DEFVAL #undef DDR_PHY_DX8SL3IOCR_DXRXM_SHIFT #undef DDR_PHY_DX8SL3IOCR_DXRXM_MASK -#define DDR_PHY_DX8SL3IOCR_DXRXM_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL3IOCR_DXRXM_SHIFT 0 -#define DDR_PHY_DX8SL3IOCR_DXRXM_MASK 0x000007FFU +#define DDR_PHY_DX8SL3IOCR_DXRXM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL3IOCR_DXRXM_SHIFT 0 +#define DDR_PHY_DX8SL3IOCR_DXRXM_MASK 0x000007FFU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL4OSC_RESERVED_31_30_DEFVAL #undef DDR_PHY_DX8SL4OSC_RESERVED_31_30_SHIFT #undef DDR_PHY_DX8SL4OSC_RESERVED_31_30_MASK -#define DDR_PHY_DX8SL4OSC_RESERVED_31_30_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL4OSC_RESERVED_31_30_SHIFT 30 -#define DDR_PHY_DX8SL4OSC_RESERVED_31_30_MASK 0xC0000000U +#define DDR_PHY_DX8SL4OSC_RESERVED_31_30_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX8SL4OSC_RESERVED_31_30_MASK 0xC0000000U -/*Enable Clock Gating for DX ddr_clk*/ +/* +* Enable Clock Gating for DX ddr_clk +*/ #undef DDR_PHY_DX8SL4OSC_GATEDXRDCLK_DEFVAL #undef DDR_PHY_DX8SL4OSC_GATEDXRDCLK_SHIFT #undef DDR_PHY_DX8SL4OSC_GATEDXRDCLK_MASK -#define DDR_PHY_DX8SL4OSC_GATEDXRDCLK_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL4OSC_GATEDXRDCLK_SHIFT 28 -#define DDR_PHY_DX8SL4OSC_GATEDXRDCLK_MASK 0x30000000U +#define DDR_PHY_DX8SL4OSC_GATEDXRDCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_GATEDXRDCLK_SHIFT 28 +#define DDR_PHY_DX8SL4OSC_GATEDXRDCLK_MASK 0x30000000U -/*Enable Clock Gating for DX ctl_rd_clk*/ +/* +* Enable Clock Gating for DX ctl_rd_clk +*/ #undef DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_DEFVAL #undef DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_SHIFT #undef DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_MASK -#define DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_SHIFT 26 -#define DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_MASK 0x0C000000U +#define DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_SHIFT 26 +#define DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_MASK 0x0C000000U -/*Enable Clock Gating for DX ctl_clk*/ +/* +* Enable Clock Gating for DX ctl_clk +*/ #undef DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_DEFVAL #undef DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_SHIFT #undef DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_MASK -#define DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_SHIFT 24 -#define DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_MASK 0x03000000U +#define DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_SHIFT 24 +#define DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_MASK 0x03000000U -/*Selects the level to which clocks will be stalled when clock gating is enabled.*/ +/* +* Selects the level to which clocks will be stalled when clock gating is e + * nabled. +*/ #undef DDR_PHY_DX8SL4OSC_CLKLEVEL_DEFVAL #undef DDR_PHY_DX8SL4OSC_CLKLEVEL_SHIFT #undef DDR_PHY_DX8SL4OSC_CLKLEVEL_MASK -#define DDR_PHY_DX8SL4OSC_CLKLEVEL_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL4OSC_CLKLEVEL_SHIFT 22 -#define DDR_PHY_DX8SL4OSC_CLKLEVEL_MASK 0x00C00000U +#define DDR_PHY_DX8SL4OSC_CLKLEVEL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_CLKLEVEL_SHIFT 22 +#define DDR_PHY_DX8SL4OSC_CLKLEVEL_MASK 0x00C00000U -/*Loopback Mode*/ +/* +* Loopback Mode +*/ #undef DDR_PHY_DX8SL4OSC_LBMODE_DEFVAL #undef DDR_PHY_DX8SL4OSC_LBMODE_SHIFT #undef DDR_PHY_DX8SL4OSC_LBMODE_MASK -#define DDR_PHY_DX8SL4OSC_LBMODE_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL4OSC_LBMODE_SHIFT 21 -#define DDR_PHY_DX8SL4OSC_LBMODE_MASK 0x00200000U +#define DDR_PHY_DX8SL4OSC_LBMODE_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_LBMODE_SHIFT 21 +#define DDR_PHY_DX8SL4OSC_LBMODE_MASK 0x00200000U -/*Load GSDQS LCDL with 2x the calibrated GSDQSPRD value*/ +/* +* Load GSDQS LCDL with 2x the calibrated GSDQSPRD value +*/ #undef DDR_PHY_DX8SL4OSC_LBGSDQS_DEFVAL #undef DDR_PHY_DX8SL4OSC_LBGSDQS_SHIFT #undef DDR_PHY_DX8SL4OSC_LBGSDQS_MASK -#define DDR_PHY_DX8SL4OSC_LBGSDQS_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL4OSC_LBGSDQS_SHIFT 20 -#define DDR_PHY_DX8SL4OSC_LBGSDQS_MASK 0x00100000U +#define DDR_PHY_DX8SL4OSC_LBGSDQS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_LBGSDQS_SHIFT 20 +#define DDR_PHY_DX8SL4OSC_LBGSDQS_MASK 0x00100000U -/*Loopback DQS Gating*/ +/* +* Loopback DQS Gating +*/ #undef DDR_PHY_DX8SL4OSC_LBGDQS_DEFVAL #undef DDR_PHY_DX8SL4OSC_LBGDQS_SHIFT #undef DDR_PHY_DX8SL4OSC_LBGDQS_MASK -#define DDR_PHY_DX8SL4OSC_LBGDQS_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL4OSC_LBGDQS_SHIFT 18 -#define DDR_PHY_DX8SL4OSC_LBGDQS_MASK 0x000C0000U +#define DDR_PHY_DX8SL4OSC_LBGDQS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_LBGDQS_SHIFT 18 +#define DDR_PHY_DX8SL4OSC_LBGDQS_MASK 0x000C0000U -/*Loopback DQS Shift*/ +/* +* Loopback DQS Shift +*/ #undef DDR_PHY_DX8SL4OSC_LBDQSS_DEFVAL #undef DDR_PHY_DX8SL4OSC_LBDQSS_SHIFT #undef DDR_PHY_DX8SL4OSC_LBDQSS_MASK -#define DDR_PHY_DX8SL4OSC_LBDQSS_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL4OSC_LBDQSS_SHIFT 17 -#define DDR_PHY_DX8SL4OSC_LBDQSS_MASK 0x00020000U +#define DDR_PHY_DX8SL4OSC_LBDQSS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_LBDQSS_SHIFT 17 +#define DDR_PHY_DX8SL4OSC_LBDQSS_MASK 0x00020000U -/*PHY High-Speed Reset*/ +/* +* PHY High-Speed Reset +*/ #undef DDR_PHY_DX8SL4OSC_PHYHRST_DEFVAL #undef DDR_PHY_DX8SL4OSC_PHYHRST_SHIFT #undef DDR_PHY_DX8SL4OSC_PHYHRST_MASK -#define DDR_PHY_DX8SL4OSC_PHYHRST_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL4OSC_PHYHRST_SHIFT 16 -#define DDR_PHY_DX8SL4OSC_PHYHRST_MASK 0x00010000U +#define DDR_PHY_DX8SL4OSC_PHYHRST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_PHYHRST_SHIFT 16 +#define DDR_PHY_DX8SL4OSC_PHYHRST_MASK 0x00010000U -/*PHY FIFO Reset*/ +/* +* PHY FIFO Reset +*/ #undef DDR_PHY_DX8SL4OSC_PHYFRST_DEFVAL #undef DDR_PHY_DX8SL4OSC_PHYFRST_SHIFT #undef DDR_PHY_DX8SL4OSC_PHYFRST_MASK -#define DDR_PHY_DX8SL4OSC_PHYFRST_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL4OSC_PHYFRST_SHIFT 15 -#define DDR_PHY_DX8SL4OSC_PHYFRST_MASK 0x00008000U +#define DDR_PHY_DX8SL4OSC_PHYFRST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_PHYFRST_SHIFT 15 +#define DDR_PHY_DX8SL4OSC_PHYFRST_MASK 0x00008000U -/*Delay Line Test Start*/ +/* +* Delay Line Test Start +*/ #undef DDR_PHY_DX8SL4OSC_DLTST_DEFVAL #undef DDR_PHY_DX8SL4OSC_DLTST_SHIFT #undef DDR_PHY_DX8SL4OSC_DLTST_MASK -#define DDR_PHY_DX8SL4OSC_DLTST_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL4OSC_DLTST_SHIFT 14 -#define DDR_PHY_DX8SL4OSC_DLTST_MASK 0x00004000U +#define DDR_PHY_DX8SL4OSC_DLTST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_DLTST_SHIFT 14 +#define DDR_PHY_DX8SL4OSC_DLTST_MASK 0x00004000U -/*Delay Line Test Mode*/ +/* +* Delay Line Test Mode +*/ #undef DDR_PHY_DX8SL4OSC_DLTMODE_DEFVAL #undef DDR_PHY_DX8SL4OSC_DLTMODE_SHIFT #undef DDR_PHY_DX8SL4OSC_DLTMODE_MASK -#define DDR_PHY_DX8SL4OSC_DLTMODE_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL4OSC_DLTMODE_SHIFT 13 -#define DDR_PHY_DX8SL4OSC_DLTMODE_MASK 0x00002000U +#define DDR_PHY_DX8SL4OSC_DLTMODE_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_DLTMODE_SHIFT 13 +#define DDR_PHY_DX8SL4OSC_DLTMODE_MASK 0x00002000U -/*Reserved. Caution, do not write to this register field.*/ +/* +* Reserved. Caution, do not write to this register field. +*/ #undef DDR_PHY_DX8SL4OSC_RESERVED_12_11_DEFVAL #undef DDR_PHY_DX8SL4OSC_RESERVED_12_11_SHIFT #undef DDR_PHY_DX8SL4OSC_RESERVED_12_11_MASK -#define DDR_PHY_DX8SL4OSC_RESERVED_12_11_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL4OSC_RESERVED_12_11_SHIFT 11 -#define DDR_PHY_DX8SL4OSC_RESERVED_12_11_MASK 0x00001800U +#define DDR_PHY_DX8SL4OSC_RESERVED_12_11_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_RESERVED_12_11_SHIFT 11 +#define DDR_PHY_DX8SL4OSC_RESERVED_12_11_MASK 0x00001800U -/*Oscillator Mode Write-Data Delay Line Select*/ +/* +* Oscillator Mode Write-Data Delay Line Select +*/ #undef DDR_PHY_DX8SL4OSC_OSCWDDL_DEFVAL #undef DDR_PHY_DX8SL4OSC_OSCWDDL_SHIFT #undef DDR_PHY_DX8SL4OSC_OSCWDDL_MASK -#define DDR_PHY_DX8SL4OSC_OSCWDDL_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL4OSC_OSCWDDL_SHIFT 9 -#define DDR_PHY_DX8SL4OSC_OSCWDDL_MASK 0x00000600U +#define DDR_PHY_DX8SL4OSC_OSCWDDL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_OSCWDDL_SHIFT 9 +#define DDR_PHY_DX8SL4OSC_OSCWDDL_MASK 0x00000600U -/*Reserved. Caution, do not write to this register field.*/ +/* +* Reserved. Caution, do not write to this register field. +*/ #undef DDR_PHY_DX8SL4OSC_RESERVED_8_7_DEFVAL #undef DDR_PHY_DX8SL4OSC_RESERVED_8_7_SHIFT #undef DDR_PHY_DX8SL4OSC_RESERVED_8_7_MASK -#define DDR_PHY_DX8SL4OSC_RESERVED_8_7_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL4OSC_RESERVED_8_7_SHIFT 7 -#define DDR_PHY_DX8SL4OSC_RESERVED_8_7_MASK 0x00000180U +#define DDR_PHY_DX8SL4OSC_RESERVED_8_7_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_RESERVED_8_7_SHIFT 7 +#define DDR_PHY_DX8SL4OSC_RESERVED_8_7_MASK 0x00000180U -/*Oscillator Mode Write-Leveling Delay Line Select*/ +/* +* Oscillator Mode Write-Leveling Delay Line Select +*/ #undef DDR_PHY_DX8SL4OSC_OSCWDL_DEFVAL #undef DDR_PHY_DX8SL4OSC_OSCWDL_SHIFT #undef DDR_PHY_DX8SL4OSC_OSCWDL_MASK -#define DDR_PHY_DX8SL4OSC_OSCWDL_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL4OSC_OSCWDL_SHIFT 5 -#define DDR_PHY_DX8SL4OSC_OSCWDL_MASK 0x00000060U +#define DDR_PHY_DX8SL4OSC_OSCWDL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_OSCWDL_SHIFT 5 +#define DDR_PHY_DX8SL4OSC_OSCWDL_MASK 0x00000060U -/*Oscillator Mode Division*/ +/* +* Oscillator Mode Division +*/ #undef DDR_PHY_DX8SL4OSC_OSCDIV_DEFVAL #undef DDR_PHY_DX8SL4OSC_OSCDIV_SHIFT #undef DDR_PHY_DX8SL4OSC_OSCDIV_MASK -#define DDR_PHY_DX8SL4OSC_OSCDIV_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL4OSC_OSCDIV_SHIFT 1 -#define DDR_PHY_DX8SL4OSC_OSCDIV_MASK 0x0000001EU +#define DDR_PHY_DX8SL4OSC_OSCDIV_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_OSCDIV_SHIFT 1 +#define DDR_PHY_DX8SL4OSC_OSCDIV_MASK 0x0000001EU -/*Oscillator Enable*/ +/* +* Oscillator Enable +*/ #undef DDR_PHY_DX8SL4OSC_OSCEN_DEFVAL #undef DDR_PHY_DX8SL4OSC_OSCEN_SHIFT #undef DDR_PHY_DX8SL4OSC_OSCEN_MASK -#define DDR_PHY_DX8SL4OSC_OSCEN_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL4OSC_OSCEN_SHIFT 0 -#define DDR_PHY_DX8SL4OSC_OSCEN_MASK 0x00000001U +#define DDR_PHY_DX8SL4OSC_OSCEN_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_OSCEN_SHIFT 0 +#define DDR_PHY_DX8SL4OSC_OSCEN_MASK 0x00000001U -/*Reserved. Return zeroes on reads.*/ +/* +* PLL Bypass +*/ +#undef DDR_PHY_DX8SL4PLLCR0_PLLBYP_DEFVAL +#undef DDR_PHY_DX8SL4PLLCR0_PLLBYP_SHIFT +#undef DDR_PHY_DX8SL4PLLCR0_PLLBYP_MASK +#define DDR_PHY_DX8SL4PLLCR0_PLLBYP_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL4PLLCR0_PLLBYP_SHIFT 31 +#define DDR_PHY_DX8SL4PLLCR0_PLLBYP_MASK 0x80000000U + +/* +* PLL Reset +*/ +#undef DDR_PHY_DX8SL4PLLCR0_PLLRST_DEFVAL +#undef DDR_PHY_DX8SL4PLLCR0_PLLRST_SHIFT +#undef DDR_PHY_DX8SL4PLLCR0_PLLRST_MASK +#define DDR_PHY_DX8SL4PLLCR0_PLLRST_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL4PLLCR0_PLLRST_SHIFT 30 +#define DDR_PHY_DX8SL4PLLCR0_PLLRST_MASK 0x40000000U + +/* +* PLL Power Down +*/ +#undef DDR_PHY_DX8SL4PLLCR0_PLLPD_DEFVAL +#undef DDR_PHY_DX8SL4PLLCR0_PLLPD_SHIFT +#undef DDR_PHY_DX8SL4PLLCR0_PLLPD_MASK +#define DDR_PHY_DX8SL4PLLCR0_PLLPD_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL4PLLCR0_PLLPD_SHIFT 29 +#define DDR_PHY_DX8SL4PLLCR0_PLLPD_MASK 0x20000000U + +/* +* Reference Stop Mode +*/ +#undef DDR_PHY_DX8SL4PLLCR0_RSTOPM_DEFVAL +#undef DDR_PHY_DX8SL4PLLCR0_RSTOPM_SHIFT +#undef DDR_PHY_DX8SL4PLLCR0_RSTOPM_MASK +#define DDR_PHY_DX8SL4PLLCR0_RSTOPM_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL4PLLCR0_RSTOPM_SHIFT 28 +#define DDR_PHY_DX8SL4PLLCR0_RSTOPM_MASK 0x10000000U + +/* +* PLL Frequency Select +*/ +#undef DDR_PHY_DX8SL4PLLCR0_FRQSEL_DEFVAL +#undef DDR_PHY_DX8SL4PLLCR0_FRQSEL_SHIFT +#undef DDR_PHY_DX8SL4PLLCR0_FRQSEL_MASK +#define DDR_PHY_DX8SL4PLLCR0_FRQSEL_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL4PLLCR0_FRQSEL_SHIFT 24 +#define DDR_PHY_DX8SL4PLLCR0_FRQSEL_MASK 0x0F000000U + +/* +* Relock Mode +*/ +#undef DDR_PHY_DX8SL4PLLCR0_RLOCKM_DEFVAL +#undef DDR_PHY_DX8SL4PLLCR0_RLOCKM_SHIFT +#undef DDR_PHY_DX8SL4PLLCR0_RLOCKM_MASK +#define DDR_PHY_DX8SL4PLLCR0_RLOCKM_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL4PLLCR0_RLOCKM_SHIFT 23 +#define DDR_PHY_DX8SL4PLLCR0_RLOCKM_MASK 0x00800000U + +/* +* Charge Pump Proportional Current Control +*/ +#undef DDR_PHY_DX8SL4PLLCR0_CPPC_DEFVAL +#undef DDR_PHY_DX8SL4PLLCR0_CPPC_SHIFT +#undef DDR_PHY_DX8SL4PLLCR0_CPPC_MASK +#define DDR_PHY_DX8SL4PLLCR0_CPPC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL4PLLCR0_CPPC_SHIFT 17 +#define DDR_PHY_DX8SL4PLLCR0_CPPC_MASK 0x007E0000U + +/* +* Charge Pump Integrating Current Control +*/ +#undef DDR_PHY_DX8SL4PLLCR0_CPIC_DEFVAL +#undef DDR_PHY_DX8SL4PLLCR0_CPIC_SHIFT +#undef DDR_PHY_DX8SL4PLLCR0_CPIC_MASK +#define DDR_PHY_DX8SL4PLLCR0_CPIC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL4PLLCR0_CPIC_SHIFT 13 +#define DDR_PHY_DX8SL4PLLCR0_CPIC_MASK 0x0001E000U + +/* +* Gear Shift +*/ +#undef DDR_PHY_DX8SL4PLLCR0_GSHIFT_DEFVAL +#undef DDR_PHY_DX8SL4PLLCR0_GSHIFT_SHIFT +#undef DDR_PHY_DX8SL4PLLCR0_GSHIFT_MASK +#define DDR_PHY_DX8SL4PLLCR0_GSHIFT_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL4PLLCR0_GSHIFT_SHIFT 12 +#define DDR_PHY_DX8SL4PLLCR0_GSHIFT_MASK 0x00001000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL4PLLCR0_RESERVED_11_9_DEFVAL +#undef DDR_PHY_DX8SL4PLLCR0_RESERVED_11_9_SHIFT +#undef DDR_PHY_DX8SL4PLLCR0_RESERVED_11_9_MASK +#define DDR_PHY_DX8SL4PLLCR0_RESERVED_11_9_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL4PLLCR0_RESERVED_11_9_SHIFT 9 +#define DDR_PHY_DX8SL4PLLCR0_RESERVED_11_9_MASK 0x00000E00U + +/* +* Analog Test Enable (ATOEN) +*/ +#undef DDR_PHY_DX8SL4PLLCR0_ATOEN_DEFVAL +#undef DDR_PHY_DX8SL4PLLCR0_ATOEN_SHIFT +#undef DDR_PHY_DX8SL4PLLCR0_ATOEN_MASK +#define DDR_PHY_DX8SL4PLLCR0_ATOEN_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL4PLLCR0_ATOEN_SHIFT 8 +#define DDR_PHY_DX8SL4PLLCR0_ATOEN_MASK 0x00000100U + +/* +* Analog Test Control +*/ +#undef DDR_PHY_DX8SL4PLLCR0_ATC_DEFVAL +#undef DDR_PHY_DX8SL4PLLCR0_ATC_SHIFT +#undef DDR_PHY_DX8SL4PLLCR0_ATC_MASK +#define DDR_PHY_DX8SL4PLLCR0_ATC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL4PLLCR0_ATC_SHIFT 4 +#define DDR_PHY_DX8SL4PLLCR0_ATC_MASK 0x000000F0U + +/* +* Digital Test Control +*/ +#undef DDR_PHY_DX8SL4PLLCR0_DTC_DEFVAL +#undef DDR_PHY_DX8SL4PLLCR0_DTC_SHIFT +#undef DDR_PHY_DX8SL4PLLCR0_DTC_MASK +#define DDR_PHY_DX8SL4PLLCR0_DTC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL4PLLCR0_DTC_SHIFT 0 +#define DDR_PHY_DX8SL4PLLCR0_DTC_MASK 0x0000000FU + +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_DEFVAL #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_SHIFT #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_MASK -#define DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_SHIFT 25 -#define DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_MASK 0xFE000000U +#define DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_SHIFT 25 +#define DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_MASK 0xFE000000U -/*Read Path Rise-to-Rise Mode*/ +/* +* Read Path Rise-to-Rise Mode +*/ #undef DDR_PHY_DX8SL4DQSCTL_RRRMODE_DEFVAL #undef DDR_PHY_DX8SL4DQSCTL_RRRMODE_SHIFT #undef DDR_PHY_DX8SL4DQSCTL_RRRMODE_MASK -#define DDR_PHY_DX8SL4DQSCTL_RRRMODE_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL4DQSCTL_RRRMODE_SHIFT 24 -#define DDR_PHY_DX8SL4DQSCTL_RRRMODE_MASK 0x01000000U +#define DDR_PHY_DX8SL4DQSCTL_RRRMODE_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL4DQSCTL_RRRMODE_SHIFT 24 +#define DDR_PHY_DX8SL4DQSCTL_RRRMODE_MASK 0x01000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_DEFVAL #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_SHIFT #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_MASK -#define DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_SHIFT 22 -#define DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_MASK 0x00C00000U +#define DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_MASK 0x00C00000U -/*Write Path Rise-to-Rise Mode*/ +/* +* Write Path Rise-to-Rise Mode +*/ #undef DDR_PHY_DX8SL4DQSCTL_WRRMODE_DEFVAL #undef DDR_PHY_DX8SL4DQSCTL_WRRMODE_SHIFT #undef DDR_PHY_DX8SL4DQSCTL_WRRMODE_MASK -#define DDR_PHY_DX8SL4DQSCTL_WRRMODE_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL4DQSCTL_WRRMODE_SHIFT 21 -#define DDR_PHY_DX8SL4DQSCTL_WRRMODE_MASK 0x00200000U +#define DDR_PHY_DX8SL4DQSCTL_WRRMODE_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL4DQSCTL_WRRMODE_SHIFT 21 +#define DDR_PHY_DX8SL4DQSCTL_WRRMODE_MASK 0x00200000U -/*DQS Gate Extension*/ +/* +* DQS Gate Extension +*/ #undef DDR_PHY_DX8SL4DQSCTL_DQSGX_DEFVAL #undef DDR_PHY_DX8SL4DQSCTL_DQSGX_SHIFT #undef DDR_PHY_DX8SL4DQSCTL_DQSGX_MASK -#define DDR_PHY_DX8SL4DQSCTL_DQSGX_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL4DQSCTL_DQSGX_SHIFT 19 -#define DDR_PHY_DX8SL4DQSCTL_DQSGX_MASK 0x00180000U +#define DDR_PHY_DX8SL4DQSCTL_DQSGX_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL4DQSCTL_DQSGX_SHIFT 19 +#define DDR_PHY_DX8SL4DQSCTL_DQSGX_MASK 0x00180000U -/*Low Power PLL Power Down*/ +/* +* Low Power PLL Power Down +*/ #undef DDR_PHY_DX8SL4DQSCTL_LPPLLPD_DEFVAL #undef DDR_PHY_DX8SL4DQSCTL_LPPLLPD_SHIFT #undef DDR_PHY_DX8SL4DQSCTL_LPPLLPD_MASK -#define DDR_PHY_DX8SL4DQSCTL_LPPLLPD_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL4DQSCTL_LPPLLPD_SHIFT 18 -#define DDR_PHY_DX8SL4DQSCTL_LPPLLPD_MASK 0x00040000U +#define DDR_PHY_DX8SL4DQSCTL_LPPLLPD_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL4DQSCTL_LPPLLPD_SHIFT 18 +#define DDR_PHY_DX8SL4DQSCTL_LPPLLPD_MASK 0x00040000U -/*Low Power I/O Power Down*/ +/* +* Low Power I/O Power Down +*/ #undef DDR_PHY_DX8SL4DQSCTL_LPIOPD_DEFVAL #undef DDR_PHY_DX8SL4DQSCTL_LPIOPD_SHIFT #undef DDR_PHY_DX8SL4DQSCTL_LPIOPD_MASK -#define DDR_PHY_DX8SL4DQSCTL_LPIOPD_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL4DQSCTL_LPIOPD_SHIFT 17 -#define DDR_PHY_DX8SL4DQSCTL_LPIOPD_MASK 0x00020000U +#define DDR_PHY_DX8SL4DQSCTL_LPIOPD_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL4DQSCTL_LPIOPD_SHIFT 17 +#define DDR_PHY_DX8SL4DQSCTL_LPIOPD_MASK 0x00020000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_DEFVAL #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_SHIFT #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_MASK -#define DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_SHIFT 15 -#define DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_MASK 0x00018000U +#define DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_SHIFT 15 +#define DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_MASK 0x00018000U -/*QS Counter Enable*/ +/* +* QS Counter Enable +*/ #undef DDR_PHY_DX8SL4DQSCTL_QSCNTEN_DEFVAL #undef DDR_PHY_DX8SL4DQSCTL_QSCNTEN_SHIFT #undef DDR_PHY_DX8SL4DQSCTL_QSCNTEN_MASK -#define DDR_PHY_DX8SL4DQSCTL_QSCNTEN_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL4DQSCTL_QSCNTEN_SHIFT 14 -#define DDR_PHY_DX8SL4DQSCTL_QSCNTEN_MASK 0x00004000U +#define DDR_PHY_DX8SL4DQSCTL_QSCNTEN_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL4DQSCTL_QSCNTEN_SHIFT 14 +#define DDR_PHY_DX8SL4DQSCTL_QSCNTEN_MASK 0x00004000U -/*Unused DQ I/O Mode*/ +/* +* Unused DQ I/O Mode +*/ #undef DDR_PHY_DX8SL4DQSCTL_UDQIOM_DEFVAL #undef DDR_PHY_DX8SL4DQSCTL_UDQIOM_SHIFT #undef DDR_PHY_DX8SL4DQSCTL_UDQIOM_MASK -#define DDR_PHY_DX8SL4DQSCTL_UDQIOM_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL4DQSCTL_UDQIOM_SHIFT 13 -#define DDR_PHY_DX8SL4DQSCTL_UDQIOM_MASK 0x00002000U +#define DDR_PHY_DX8SL4DQSCTL_UDQIOM_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL4DQSCTL_UDQIOM_SHIFT 13 +#define DDR_PHY_DX8SL4DQSCTL_UDQIOM_MASK 0x00002000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_DEFVAL #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_SHIFT #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_MASK -#define DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_SHIFT 10 -#define DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_MASK 0x00001C00U +#define DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_SHIFT 10 +#define DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_MASK 0x00001C00U -/*Data Slew Rate*/ +/* +* Data Slew Rate +*/ #undef DDR_PHY_DX8SL4DQSCTL_DXSR_DEFVAL #undef DDR_PHY_DX8SL4DQSCTL_DXSR_SHIFT #undef DDR_PHY_DX8SL4DQSCTL_DXSR_MASK -#define DDR_PHY_DX8SL4DQSCTL_DXSR_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL4DQSCTL_DXSR_SHIFT 8 -#define DDR_PHY_DX8SL4DQSCTL_DXSR_MASK 0x00000300U +#define DDR_PHY_DX8SL4DQSCTL_DXSR_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL4DQSCTL_DXSR_SHIFT 8 +#define DDR_PHY_DX8SL4DQSCTL_DXSR_MASK 0x00000300U -/*DQS_N Resistor*/ +/* +* DQS_N Resistor +*/ #undef DDR_PHY_DX8SL4DQSCTL_DQSNRES_DEFVAL #undef DDR_PHY_DX8SL4DQSCTL_DQSNRES_SHIFT #undef DDR_PHY_DX8SL4DQSCTL_DQSNRES_MASK -#define DDR_PHY_DX8SL4DQSCTL_DQSNRES_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL4DQSCTL_DQSNRES_SHIFT 4 -#define DDR_PHY_DX8SL4DQSCTL_DQSNRES_MASK 0x000000F0U +#define DDR_PHY_DX8SL4DQSCTL_DQSNRES_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL4DQSCTL_DQSNRES_SHIFT 4 +#define DDR_PHY_DX8SL4DQSCTL_DQSNRES_MASK 0x000000F0U -/*DQS Resistor*/ +/* +* DQS Resistor +*/ #undef DDR_PHY_DX8SL4DQSCTL_DQSRES_DEFVAL #undef DDR_PHY_DX8SL4DQSCTL_DQSRES_SHIFT #undef DDR_PHY_DX8SL4DQSCTL_DQSRES_MASK -#define DDR_PHY_DX8SL4DQSCTL_DQSRES_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL4DQSCTL_DQSRES_SHIFT 0 -#define DDR_PHY_DX8SL4DQSCTL_DQSRES_MASK 0x0000000FU +#define DDR_PHY_DX8SL4DQSCTL_DQSRES_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL4DQSCTL_DQSRES_SHIFT 0 +#define DDR_PHY_DX8SL4DQSCTL_DQSRES_MASK 0x0000000FU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_DEFVAL #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_SHIFT #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_MASK -#define DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_SHIFT 24 -#define DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_MASK 0xFF000000U +#define DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_SHIFT 24 +#define DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_MASK 0xFF000000U -/*Configurable Read Data Enable*/ +/* +* Configurable Read Data Enable +*/ #undef DDR_PHY_DX8SL4DXCTL2_CRDEN_DEFVAL #undef DDR_PHY_DX8SL4DXCTL2_CRDEN_SHIFT #undef DDR_PHY_DX8SL4DXCTL2_CRDEN_MASK -#define DDR_PHY_DX8SL4DXCTL2_CRDEN_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL4DXCTL2_CRDEN_SHIFT 23 -#define DDR_PHY_DX8SL4DXCTL2_CRDEN_MASK 0x00800000U +#define DDR_PHY_DX8SL4DXCTL2_CRDEN_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_CRDEN_SHIFT 23 +#define DDR_PHY_DX8SL4DXCTL2_CRDEN_MASK 0x00800000U -/*OX Extension during Post-amble*/ +/* +* OX Extension during Post-amble +*/ #undef DDR_PHY_DX8SL4DXCTL2_POSOEX_DEFVAL #undef DDR_PHY_DX8SL4DXCTL2_POSOEX_SHIFT #undef DDR_PHY_DX8SL4DXCTL2_POSOEX_MASK -#define DDR_PHY_DX8SL4DXCTL2_POSOEX_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL4DXCTL2_POSOEX_SHIFT 20 -#define DDR_PHY_DX8SL4DXCTL2_POSOEX_MASK 0x00700000U +#define DDR_PHY_DX8SL4DXCTL2_POSOEX_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_POSOEX_SHIFT 20 +#define DDR_PHY_DX8SL4DXCTL2_POSOEX_MASK 0x00700000U -/*OE Extension during Pre-amble*/ +/* +* OE Extension during Pre-amble +*/ #undef DDR_PHY_DX8SL4DXCTL2_PREOEX_DEFVAL #undef DDR_PHY_DX8SL4DXCTL2_PREOEX_SHIFT #undef DDR_PHY_DX8SL4DXCTL2_PREOEX_MASK -#define DDR_PHY_DX8SL4DXCTL2_PREOEX_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL4DXCTL2_PREOEX_SHIFT 18 -#define DDR_PHY_DX8SL4DXCTL2_PREOEX_MASK 0x000C0000U +#define DDR_PHY_DX8SL4DXCTL2_PREOEX_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_PREOEX_SHIFT 18 +#define DDR_PHY_DX8SL4DXCTL2_PREOEX_MASK 0x000C0000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_17_DEFVAL #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_17_SHIFT #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_17_MASK -#define DDR_PHY_DX8SL4DXCTL2_RESERVED_17_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL4DXCTL2_RESERVED_17_SHIFT 17 -#define DDR_PHY_DX8SL4DXCTL2_RESERVED_17_MASK 0x00020000U +#define DDR_PHY_DX8SL4DXCTL2_RESERVED_17_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_RESERVED_17_SHIFT 17 +#define DDR_PHY_DX8SL4DXCTL2_RESERVED_17_MASK 0x00020000U -/*I/O Assisted Gate Select*/ +/* +* I/O Assisted Gate Select +*/ #undef DDR_PHY_DX8SL4DXCTL2_IOAG_DEFVAL #undef DDR_PHY_DX8SL4DXCTL2_IOAG_SHIFT #undef DDR_PHY_DX8SL4DXCTL2_IOAG_MASK -#define DDR_PHY_DX8SL4DXCTL2_IOAG_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL4DXCTL2_IOAG_SHIFT 16 -#define DDR_PHY_DX8SL4DXCTL2_IOAG_MASK 0x00010000U +#define DDR_PHY_DX8SL4DXCTL2_IOAG_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_IOAG_SHIFT 16 +#define DDR_PHY_DX8SL4DXCTL2_IOAG_MASK 0x00010000U -/*I/O Loopback Select*/ +/* +* I/O Loopback Select +*/ #undef DDR_PHY_DX8SL4DXCTL2_IOLB_DEFVAL #undef DDR_PHY_DX8SL4DXCTL2_IOLB_SHIFT #undef DDR_PHY_DX8SL4DXCTL2_IOLB_MASK -#define DDR_PHY_DX8SL4DXCTL2_IOLB_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL4DXCTL2_IOLB_SHIFT 15 -#define DDR_PHY_DX8SL4DXCTL2_IOLB_MASK 0x00008000U +#define DDR_PHY_DX8SL4DXCTL2_IOLB_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_IOLB_SHIFT 15 +#define DDR_PHY_DX8SL4DXCTL2_IOLB_MASK 0x00008000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_DEFVAL #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_SHIFT #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_MASK -#define DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_SHIFT 13 -#define DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_MASK 0x00006000U +#define DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_SHIFT 13 +#define DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_MASK 0x00006000U -/*Low Power Wakeup Threshold*/ +/* +* Low Power Wakeup Threshold +*/ #undef DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_DEFVAL #undef DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_SHIFT #undef DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_MASK -#define DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_SHIFT 9 -#define DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_MASK 0x00001E00U +#define DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_SHIFT 9 +#define DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_MASK 0x00001E00U -/*Read Data Bus Inversion Enable*/ +/* +* Read Data Bus Inversion Enable +*/ #undef DDR_PHY_DX8SL4DXCTL2_RDBI_DEFVAL #undef DDR_PHY_DX8SL4DXCTL2_RDBI_SHIFT #undef DDR_PHY_DX8SL4DXCTL2_RDBI_MASK -#define DDR_PHY_DX8SL4DXCTL2_RDBI_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL4DXCTL2_RDBI_SHIFT 8 -#define DDR_PHY_DX8SL4DXCTL2_RDBI_MASK 0x00000100U +#define DDR_PHY_DX8SL4DXCTL2_RDBI_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_RDBI_SHIFT 8 +#define DDR_PHY_DX8SL4DXCTL2_RDBI_MASK 0x00000100U -/*Write Data Bus Inversion Enable*/ +/* +* Write Data Bus Inversion Enable +*/ #undef DDR_PHY_DX8SL4DXCTL2_WDBI_DEFVAL #undef DDR_PHY_DX8SL4DXCTL2_WDBI_SHIFT #undef DDR_PHY_DX8SL4DXCTL2_WDBI_MASK -#define DDR_PHY_DX8SL4DXCTL2_WDBI_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL4DXCTL2_WDBI_SHIFT 7 -#define DDR_PHY_DX8SL4DXCTL2_WDBI_MASK 0x00000080U +#define DDR_PHY_DX8SL4DXCTL2_WDBI_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_WDBI_SHIFT 7 +#define DDR_PHY_DX8SL4DXCTL2_WDBI_MASK 0x00000080U -/*PUB Read FIFO Bypass*/ +/* +* PUB Read FIFO Bypass +*/ #undef DDR_PHY_DX8SL4DXCTL2_PRFBYP_DEFVAL #undef DDR_PHY_DX8SL4DXCTL2_PRFBYP_SHIFT #undef DDR_PHY_DX8SL4DXCTL2_PRFBYP_MASK -#define DDR_PHY_DX8SL4DXCTL2_PRFBYP_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL4DXCTL2_PRFBYP_SHIFT 6 -#define DDR_PHY_DX8SL4DXCTL2_PRFBYP_MASK 0x00000040U +#define DDR_PHY_DX8SL4DXCTL2_PRFBYP_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_PRFBYP_SHIFT 6 +#define DDR_PHY_DX8SL4DXCTL2_PRFBYP_MASK 0x00000040U -/*DATX8 Receive FIFO Read Mode*/ +/* +* DATX8 Receive FIFO Read Mode +*/ #undef DDR_PHY_DX8SL4DXCTL2_RDMODE_DEFVAL #undef DDR_PHY_DX8SL4DXCTL2_RDMODE_SHIFT #undef DDR_PHY_DX8SL4DXCTL2_RDMODE_MASK -#define DDR_PHY_DX8SL4DXCTL2_RDMODE_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL4DXCTL2_RDMODE_SHIFT 4 -#define DDR_PHY_DX8SL4DXCTL2_RDMODE_MASK 0x00000030U +#define DDR_PHY_DX8SL4DXCTL2_RDMODE_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_RDMODE_SHIFT 4 +#define DDR_PHY_DX8SL4DXCTL2_RDMODE_MASK 0x00000030U -/*Disables the Read FIFO Reset*/ +/* +* Disables the Read FIFO Reset +*/ #undef DDR_PHY_DX8SL4DXCTL2_DISRST_DEFVAL #undef DDR_PHY_DX8SL4DXCTL2_DISRST_SHIFT #undef DDR_PHY_DX8SL4DXCTL2_DISRST_MASK -#define DDR_PHY_DX8SL4DXCTL2_DISRST_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL4DXCTL2_DISRST_SHIFT 3 -#define DDR_PHY_DX8SL4DXCTL2_DISRST_MASK 0x00000008U +#define DDR_PHY_DX8SL4DXCTL2_DISRST_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_DISRST_SHIFT 3 +#define DDR_PHY_DX8SL4DXCTL2_DISRST_MASK 0x00000008U -/*Read DQS Gate I/O Loopback*/ +/* +* Read DQS Gate I/O Loopback +*/ #undef DDR_PHY_DX8SL4DXCTL2_DQSGLB_DEFVAL #undef DDR_PHY_DX8SL4DXCTL2_DQSGLB_SHIFT #undef DDR_PHY_DX8SL4DXCTL2_DQSGLB_MASK -#define DDR_PHY_DX8SL4DXCTL2_DQSGLB_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL4DXCTL2_DQSGLB_SHIFT 1 -#define DDR_PHY_DX8SL4DXCTL2_DQSGLB_MASK 0x00000006U +#define DDR_PHY_DX8SL4DXCTL2_DQSGLB_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_DQSGLB_SHIFT 1 +#define DDR_PHY_DX8SL4DXCTL2_DQSGLB_MASK 0x00000006U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_0_DEFVAL #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_0_SHIFT #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_0_MASK -#define DDR_PHY_DX8SL4DXCTL2_RESERVED_0_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL4DXCTL2_RESERVED_0_SHIFT 0 -#define DDR_PHY_DX8SL4DXCTL2_RESERVED_0_MASK 0x00000001U +#define DDR_PHY_DX8SL4DXCTL2_RESERVED_0_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_RESERVED_0_SHIFT 0 +#define DDR_PHY_DX8SL4DXCTL2_RESERVED_0_MASK 0x00000001U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL4IOCR_RESERVED_31_DEFVAL #undef DDR_PHY_DX8SL4IOCR_RESERVED_31_SHIFT #undef DDR_PHY_DX8SL4IOCR_RESERVED_31_MASK -#define DDR_PHY_DX8SL4IOCR_RESERVED_31_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL4IOCR_RESERVED_31_SHIFT 31 -#define DDR_PHY_DX8SL4IOCR_RESERVED_31_MASK 0x80000000U +#define DDR_PHY_DX8SL4IOCR_RESERVED_31_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL4IOCR_RESERVED_31_SHIFT 31 +#define DDR_PHY_DX8SL4IOCR_RESERVED_31_MASK 0x80000000U -/*PVREF_DAC REFSEL range select*/ +/* +* PVREF_DAC REFSEL range select +*/ #undef DDR_PHY_DX8SL4IOCR_DXDACRANGE_DEFVAL #undef DDR_PHY_DX8SL4IOCR_DXDACRANGE_SHIFT #undef DDR_PHY_DX8SL4IOCR_DXDACRANGE_MASK -#define DDR_PHY_DX8SL4IOCR_DXDACRANGE_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL4IOCR_DXDACRANGE_SHIFT 28 -#define DDR_PHY_DX8SL4IOCR_DXDACRANGE_MASK 0x70000000U +#define DDR_PHY_DX8SL4IOCR_DXDACRANGE_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL4IOCR_DXDACRANGE_SHIFT 28 +#define DDR_PHY_DX8SL4IOCR_DXDACRANGE_MASK 0x70000000U -/*IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring*/ +/* +* IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring +*/ #undef DDR_PHY_DX8SL4IOCR_DXVREFIOM_DEFVAL #undef DDR_PHY_DX8SL4IOCR_DXVREFIOM_SHIFT #undef DDR_PHY_DX8SL4IOCR_DXVREFIOM_MASK -#define DDR_PHY_DX8SL4IOCR_DXVREFIOM_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL4IOCR_DXVREFIOM_SHIFT 25 -#define DDR_PHY_DX8SL4IOCR_DXVREFIOM_MASK 0x0E000000U +#define DDR_PHY_DX8SL4IOCR_DXVREFIOM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL4IOCR_DXVREFIOM_SHIFT 25 +#define DDR_PHY_DX8SL4IOCR_DXVREFIOM_MASK 0x0E000000U -/*DX IO Mode*/ +/* +* DX IO Mode +*/ #undef DDR_PHY_DX8SL4IOCR_DXIOM_DEFVAL #undef DDR_PHY_DX8SL4IOCR_DXIOM_SHIFT #undef DDR_PHY_DX8SL4IOCR_DXIOM_MASK -#define DDR_PHY_DX8SL4IOCR_DXIOM_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL4IOCR_DXIOM_SHIFT 22 -#define DDR_PHY_DX8SL4IOCR_DXIOM_MASK 0x01C00000U +#define DDR_PHY_DX8SL4IOCR_DXIOM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL4IOCR_DXIOM_SHIFT 22 +#define DDR_PHY_DX8SL4IOCR_DXIOM_MASK 0x01C00000U -/*DX IO Transmitter Mode*/ +/* +* DX IO Transmitter Mode +*/ #undef DDR_PHY_DX8SL4IOCR_DXTXM_DEFVAL #undef DDR_PHY_DX8SL4IOCR_DXTXM_SHIFT #undef DDR_PHY_DX8SL4IOCR_DXTXM_MASK -#define DDR_PHY_DX8SL4IOCR_DXTXM_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL4IOCR_DXTXM_SHIFT 11 -#define DDR_PHY_DX8SL4IOCR_DXTXM_MASK 0x003FF800U +#define DDR_PHY_DX8SL4IOCR_DXTXM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL4IOCR_DXTXM_SHIFT 11 +#define DDR_PHY_DX8SL4IOCR_DXTXM_MASK 0x003FF800U -/*DX IO Receiver Mode*/ +/* +* DX IO Receiver Mode +*/ #undef DDR_PHY_DX8SL4IOCR_DXRXM_DEFVAL #undef DDR_PHY_DX8SL4IOCR_DXRXM_SHIFT #undef DDR_PHY_DX8SL4IOCR_DXRXM_MASK -#define DDR_PHY_DX8SL4IOCR_DXRXM_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL4IOCR_DXRXM_SHIFT 0 -#define DDR_PHY_DX8SL4IOCR_DXRXM_MASK 0x000007FFU +#define DDR_PHY_DX8SL4IOCR_DXRXM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL4IOCR_DXRXM_SHIFT 0 +#define DDR_PHY_DX8SL4IOCR_DXRXM_MASK 0x000007FFU -/*Reserved. Return zeroes on reads.*/ +/* +* PLL Bypass +*/ +#undef DDR_PHY_DX8SLBPLLCR0_PLLBYP_DEFVAL +#undef DDR_PHY_DX8SLBPLLCR0_PLLBYP_SHIFT +#undef DDR_PHY_DX8SLBPLLCR0_PLLBYP_MASK +#define DDR_PHY_DX8SLBPLLCR0_PLLBYP_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBPLLCR0_PLLBYP_SHIFT 31 +#define DDR_PHY_DX8SLBPLLCR0_PLLBYP_MASK 0x80000000U + +/* +* PLL Reset +*/ +#undef DDR_PHY_DX8SLBPLLCR0_PLLRST_DEFVAL +#undef DDR_PHY_DX8SLBPLLCR0_PLLRST_SHIFT +#undef DDR_PHY_DX8SLBPLLCR0_PLLRST_MASK +#define DDR_PHY_DX8SLBPLLCR0_PLLRST_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBPLLCR0_PLLRST_SHIFT 30 +#define DDR_PHY_DX8SLBPLLCR0_PLLRST_MASK 0x40000000U + +/* +* PLL Power Down +*/ +#undef DDR_PHY_DX8SLBPLLCR0_PLLPD_DEFVAL +#undef DDR_PHY_DX8SLBPLLCR0_PLLPD_SHIFT +#undef DDR_PHY_DX8SLBPLLCR0_PLLPD_MASK +#define DDR_PHY_DX8SLBPLLCR0_PLLPD_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBPLLCR0_PLLPD_SHIFT 29 +#define DDR_PHY_DX8SLBPLLCR0_PLLPD_MASK 0x20000000U + +/* +* Reference Stop Mode +*/ +#undef DDR_PHY_DX8SLBPLLCR0_RSTOPM_DEFVAL +#undef DDR_PHY_DX8SLBPLLCR0_RSTOPM_SHIFT +#undef DDR_PHY_DX8SLBPLLCR0_RSTOPM_MASK +#define DDR_PHY_DX8SLBPLLCR0_RSTOPM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBPLLCR0_RSTOPM_SHIFT 28 +#define DDR_PHY_DX8SLBPLLCR0_RSTOPM_MASK 0x10000000U + +/* +* PLL Frequency Select +*/ +#undef DDR_PHY_DX8SLBPLLCR0_FRQSEL_DEFVAL +#undef DDR_PHY_DX8SLBPLLCR0_FRQSEL_SHIFT +#undef DDR_PHY_DX8SLBPLLCR0_FRQSEL_MASK +#define DDR_PHY_DX8SLBPLLCR0_FRQSEL_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBPLLCR0_FRQSEL_SHIFT 24 +#define DDR_PHY_DX8SLBPLLCR0_FRQSEL_MASK 0x0F000000U + +/* +* Relock Mode +*/ +#undef DDR_PHY_DX8SLBPLLCR0_RLOCKM_DEFVAL +#undef DDR_PHY_DX8SLBPLLCR0_RLOCKM_SHIFT +#undef DDR_PHY_DX8SLBPLLCR0_RLOCKM_MASK +#define DDR_PHY_DX8SLBPLLCR0_RLOCKM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBPLLCR0_RLOCKM_SHIFT 23 +#define DDR_PHY_DX8SLBPLLCR0_RLOCKM_MASK 0x00800000U + +/* +* Charge Pump Proportional Current Control +*/ +#undef DDR_PHY_DX8SLBPLLCR0_CPPC_DEFVAL +#undef DDR_PHY_DX8SLBPLLCR0_CPPC_SHIFT +#undef DDR_PHY_DX8SLBPLLCR0_CPPC_MASK +#define DDR_PHY_DX8SLBPLLCR0_CPPC_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBPLLCR0_CPPC_SHIFT 17 +#define DDR_PHY_DX8SLBPLLCR0_CPPC_MASK 0x007E0000U + +/* +* Charge Pump Integrating Current Control +*/ +#undef DDR_PHY_DX8SLBPLLCR0_CPIC_DEFVAL +#undef DDR_PHY_DX8SLBPLLCR0_CPIC_SHIFT +#undef DDR_PHY_DX8SLBPLLCR0_CPIC_MASK +#define DDR_PHY_DX8SLBPLLCR0_CPIC_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBPLLCR0_CPIC_SHIFT 13 +#define DDR_PHY_DX8SLBPLLCR0_CPIC_MASK 0x0001E000U + +/* +* Gear Shift +*/ +#undef DDR_PHY_DX8SLBPLLCR0_GSHIFT_DEFVAL +#undef DDR_PHY_DX8SLBPLLCR0_GSHIFT_SHIFT +#undef DDR_PHY_DX8SLBPLLCR0_GSHIFT_MASK +#define DDR_PHY_DX8SLBPLLCR0_GSHIFT_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBPLLCR0_GSHIFT_SHIFT 12 +#define DDR_PHY_DX8SLBPLLCR0_GSHIFT_MASK 0x00001000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SLBPLLCR0_RESERVED_11_9_DEFVAL +#undef DDR_PHY_DX8SLBPLLCR0_RESERVED_11_9_SHIFT +#undef DDR_PHY_DX8SLBPLLCR0_RESERVED_11_9_MASK +#define DDR_PHY_DX8SLBPLLCR0_RESERVED_11_9_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBPLLCR0_RESERVED_11_9_SHIFT 9 +#define DDR_PHY_DX8SLBPLLCR0_RESERVED_11_9_MASK 0x00000E00U + +/* +* Analog Test Enable (ATOEN) +*/ +#undef DDR_PHY_DX8SLBPLLCR0_ATOEN_DEFVAL +#undef DDR_PHY_DX8SLBPLLCR0_ATOEN_SHIFT +#undef DDR_PHY_DX8SLBPLLCR0_ATOEN_MASK +#define DDR_PHY_DX8SLBPLLCR0_ATOEN_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBPLLCR0_ATOEN_SHIFT 8 +#define DDR_PHY_DX8SLBPLLCR0_ATOEN_MASK 0x00000100U + +/* +* Analog Test Control +*/ +#undef DDR_PHY_DX8SLBPLLCR0_ATC_DEFVAL +#undef DDR_PHY_DX8SLBPLLCR0_ATC_SHIFT +#undef DDR_PHY_DX8SLBPLLCR0_ATC_MASK +#define DDR_PHY_DX8SLBPLLCR0_ATC_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBPLLCR0_ATC_SHIFT 4 +#define DDR_PHY_DX8SLBPLLCR0_ATC_MASK 0x000000F0U + +/* +* Digital Test Control +*/ +#undef DDR_PHY_DX8SLBPLLCR0_DTC_DEFVAL +#undef DDR_PHY_DX8SLBPLLCR0_DTC_SHIFT +#undef DDR_PHY_DX8SLBPLLCR0_DTC_MASK +#define DDR_PHY_DX8SLBPLLCR0_DTC_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBPLLCR0_DTC_SHIFT 0 +#define DDR_PHY_DX8SLBPLLCR0_DTC_MASK 0x0000000FU + +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_DEFVAL #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_SHIFT #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_MASK -#define DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_DEFVAL 0x00000000 -#define DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_SHIFT 25 -#define DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_MASK 0xFE000000U +#define DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_SHIFT 25 +#define DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_MASK 0xFE000000U -/*Read Path Rise-to-Rise Mode*/ +/* +* Read Path Rise-to-Rise Mode +*/ #undef DDR_PHY_DX8SLBDQSCTL_RRRMODE_DEFVAL #undef DDR_PHY_DX8SLBDQSCTL_RRRMODE_SHIFT #undef DDR_PHY_DX8SLBDQSCTL_RRRMODE_MASK -#define DDR_PHY_DX8SLBDQSCTL_RRRMODE_DEFVAL 0x00000000 -#define DDR_PHY_DX8SLBDQSCTL_RRRMODE_SHIFT 24 -#define DDR_PHY_DX8SLBDQSCTL_RRRMODE_MASK 0x01000000U +#define DDR_PHY_DX8SLBDQSCTL_RRRMODE_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBDQSCTL_RRRMODE_SHIFT 24 +#define DDR_PHY_DX8SLBDQSCTL_RRRMODE_MASK 0x01000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_DEFVAL #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_SHIFT #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_MASK -#define DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_DEFVAL 0x00000000 -#define DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_SHIFT 22 -#define DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_MASK 0x00C00000U +#define DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_MASK 0x00C00000U -/*Write Path Rise-to-Rise Mode*/ +/* +* Write Path Rise-to-Rise Mode +*/ #undef DDR_PHY_DX8SLBDQSCTL_WRRMODE_DEFVAL #undef DDR_PHY_DX8SLBDQSCTL_WRRMODE_SHIFT #undef DDR_PHY_DX8SLBDQSCTL_WRRMODE_MASK -#define DDR_PHY_DX8SLBDQSCTL_WRRMODE_DEFVAL 0x00000000 -#define DDR_PHY_DX8SLBDQSCTL_WRRMODE_SHIFT 21 -#define DDR_PHY_DX8SLBDQSCTL_WRRMODE_MASK 0x00200000U +#define DDR_PHY_DX8SLBDQSCTL_WRRMODE_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBDQSCTL_WRRMODE_SHIFT 21 +#define DDR_PHY_DX8SLBDQSCTL_WRRMODE_MASK 0x00200000U -/*DQS Gate Extension*/ +/* +* DQS Gate Extension +*/ #undef DDR_PHY_DX8SLBDQSCTL_DQSGX_DEFVAL #undef DDR_PHY_DX8SLBDQSCTL_DQSGX_SHIFT #undef DDR_PHY_DX8SLBDQSCTL_DQSGX_MASK -#define DDR_PHY_DX8SLBDQSCTL_DQSGX_DEFVAL 0x00000000 -#define DDR_PHY_DX8SLBDQSCTL_DQSGX_SHIFT 19 -#define DDR_PHY_DX8SLBDQSCTL_DQSGX_MASK 0x00180000U +#define DDR_PHY_DX8SLBDQSCTL_DQSGX_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBDQSCTL_DQSGX_SHIFT 19 +#define DDR_PHY_DX8SLBDQSCTL_DQSGX_MASK 0x00180000U -/*Low Power PLL Power Down*/ +/* +* Low Power PLL Power Down +*/ #undef DDR_PHY_DX8SLBDQSCTL_LPPLLPD_DEFVAL #undef DDR_PHY_DX8SLBDQSCTL_LPPLLPD_SHIFT #undef DDR_PHY_DX8SLBDQSCTL_LPPLLPD_MASK -#define DDR_PHY_DX8SLBDQSCTL_LPPLLPD_DEFVAL 0x00000000 -#define DDR_PHY_DX8SLBDQSCTL_LPPLLPD_SHIFT 18 -#define DDR_PHY_DX8SLBDQSCTL_LPPLLPD_MASK 0x00040000U +#define DDR_PHY_DX8SLBDQSCTL_LPPLLPD_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBDQSCTL_LPPLLPD_SHIFT 18 +#define DDR_PHY_DX8SLBDQSCTL_LPPLLPD_MASK 0x00040000U -/*Low Power I/O Power Down*/ +/* +* Low Power I/O Power Down +*/ #undef DDR_PHY_DX8SLBDQSCTL_LPIOPD_DEFVAL #undef DDR_PHY_DX8SLBDQSCTL_LPIOPD_SHIFT #undef DDR_PHY_DX8SLBDQSCTL_LPIOPD_MASK -#define DDR_PHY_DX8SLBDQSCTL_LPIOPD_DEFVAL 0x00000000 -#define DDR_PHY_DX8SLBDQSCTL_LPIOPD_SHIFT 17 -#define DDR_PHY_DX8SLBDQSCTL_LPIOPD_MASK 0x00020000U +#define DDR_PHY_DX8SLBDQSCTL_LPIOPD_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBDQSCTL_LPIOPD_SHIFT 17 +#define DDR_PHY_DX8SLBDQSCTL_LPIOPD_MASK 0x00020000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_DEFVAL #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_SHIFT #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_MASK -#define DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_DEFVAL 0x00000000 -#define DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_SHIFT 15 -#define DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_MASK 0x00018000U +#define DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_SHIFT 15 +#define DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_MASK 0x00018000U -/*QS Counter Enable*/ +/* +* QS Counter Enable +*/ #undef DDR_PHY_DX8SLBDQSCTL_QSCNTEN_DEFVAL #undef DDR_PHY_DX8SLBDQSCTL_QSCNTEN_SHIFT #undef DDR_PHY_DX8SLBDQSCTL_QSCNTEN_MASK -#define DDR_PHY_DX8SLBDQSCTL_QSCNTEN_DEFVAL 0x00000000 -#define DDR_PHY_DX8SLBDQSCTL_QSCNTEN_SHIFT 14 -#define DDR_PHY_DX8SLBDQSCTL_QSCNTEN_MASK 0x00004000U +#define DDR_PHY_DX8SLBDQSCTL_QSCNTEN_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBDQSCTL_QSCNTEN_SHIFT 14 +#define DDR_PHY_DX8SLBDQSCTL_QSCNTEN_MASK 0x00004000U -/*Unused DQ I/O Mode*/ +/* +* Unused DQ I/O Mode +*/ #undef DDR_PHY_DX8SLBDQSCTL_UDQIOM_DEFVAL #undef DDR_PHY_DX8SLBDQSCTL_UDQIOM_SHIFT #undef DDR_PHY_DX8SLBDQSCTL_UDQIOM_MASK -#define DDR_PHY_DX8SLBDQSCTL_UDQIOM_DEFVAL 0x00000000 -#define DDR_PHY_DX8SLBDQSCTL_UDQIOM_SHIFT 13 -#define DDR_PHY_DX8SLBDQSCTL_UDQIOM_MASK 0x00002000U +#define DDR_PHY_DX8SLBDQSCTL_UDQIOM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBDQSCTL_UDQIOM_SHIFT 13 +#define DDR_PHY_DX8SLBDQSCTL_UDQIOM_MASK 0x00002000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_DEFVAL #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_SHIFT #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_MASK -#define DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_DEFVAL 0x00000000 -#define DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_SHIFT 10 -#define DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_MASK 0x00001C00U +#define DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_SHIFT 10 +#define DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_MASK 0x00001C00U -/*Data Slew Rate*/ +/* +* Data Slew Rate +*/ #undef DDR_PHY_DX8SLBDQSCTL_DXSR_DEFVAL #undef DDR_PHY_DX8SLBDQSCTL_DXSR_SHIFT #undef DDR_PHY_DX8SLBDQSCTL_DXSR_MASK -#define DDR_PHY_DX8SLBDQSCTL_DXSR_DEFVAL 0x00000000 -#define DDR_PHY_DX8SLBDQSCTL_DXSR_SHIFT 8 -#define DDR_PHY_DX8SLBDQSCTL_DXSR_MASK 0x00000300U +#define DDR_PHY_DX8SLBDQSCTL_DXSR_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBDQSCTL_DXSR_SHIFT 8 +#define DDR_PHY_DX8SLBDQSCTL_DXSR_MASK 0x00000300U -/*DQS# Resistor*/ +/* +* DQS# Resistor +*/ #undef DDR_PHY_DX8SLBDQSCTL_DQSNRES_DEFVAL #undef DDR_PHY_DX8SLBDQSCTL_DQSNRES_SHIFT #undef DDR_PHY_DX8SLBDQSCTL_DQSNRES_MASK -#define DDR_PHY_DX8SLBDQSCTL_DQSNRES_DEFVAL 0x00000000 -#define DDR_PHY_DX8SLBDQSCTL_DQSNRES_SHIFT 4 -#define DDR_PHY_DX8SLBDQSCTL_DQSNRES_MASK 0x000000F0U +#define DDR_PHY_DX8SLBDQSCTL_DQSNRES_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBDQSCTL_DQSNRES_SHIFT 4 +#define DDR_PHY_DX8SLBDQSCTL_DQSNRES_MASK 0x000000F0U -/*DQS Resistor*/ +/* +* DQS Resistor +*/ #undef DDR_PHY_DX8SLBDQSCTL_DQSRES_DEFVAL #undef DDR_PHY_DX8SLBDQSCTL_DQSRES_SHIFT #undef DDR_PHY_DX8SLBDQSCTL_DQSRES_MASK -#define DDR_PHY_DX8SLBDQSCTL_DQSRES_DEFVAL 0x00000000 -#define DDR_PHY_DX8SLBDQSCTL_DQSRES_SHIFT 0 -#define DDR_PHY_DX8SLBDQSCTL_DQSRES_MASK 0x0000000FU - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_PIR_RESERVED_31_DEFVAL -#undef DDR_PHY_PIR_RESERVED_31_SHIFT -#undef DDR_PHY_PIR_RESERVED_31_MASK -#define DDR_PHY_PIR_RESERVED_31_DEFVAL 0x00000000 -#define DDR_PHY_PIR_RESERVED_31_SHIFT 31 -#define DDR_PHY_PIR_RESERVED_31_MASK 0x80000000U - -/*Impedance Calibration Bypass*/ -#undef DDR_PHY_PIR_ZCALBYP_DEFVAL -#undef DDR_PHY_PIR_ZCALBYP_SHIFT -#undef DDR_PHY_PIR_ZCALBYP_MASK -#define DDR_PHY_PIR_ZCALBYP_DEFVAL 0x00000000 -#define DDR_PHY_PIR_ZCALBYP_SHIFT 30 -#define DDR_PHY_PIR_ZCALBYP_MASK 0x40000000U - -/*Digital Delay Line (DDL) Calibration Pause*/ -#undef DDR_PHY_PIR_DCALPSE_DEFVAL -#undef DDR_PHY_PIR_DCALPSE_SHIFT -#undef DDR_PHY_PIR_DCALPSE_MASK -#define DDR_PHY_PIR_DCALPSE_DEFVAL 0x00000000 -#define DDR_PHY_PIR_DCALPSE_SHIFT 29 -#define DDR_PHY_PIR_DCALPSE_MASK 0x20000000U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_PIR_RESERVED_28_21_DEFVAL -#undef DDR_PHY_PIR_RESERVED_28_21_SHIFT -#undef DDR_PHY_PIR_RESERVED_28_21_MASK -#define DDR_PHY_PIR_RESERVED_28_21_DEFVAL 0x00000000 -#define DDR_PHY_PIR_RESERVED_28_21_SHIFT 21 -#define DDR_PHY_PIR_RESERVED_28_21_MASK 0x1FE00000U - -/*Write DQS2DQ Training*/ -#undef DDR_PHY_PIR_DQS2DQ_DEFVAL -#undef DDR_PHY_PIR_DQS2DQ_SHIFT -#undef DDR_PHY_PIR_DQS2DQ_MASK -#define DDR_PHY_PIR_DQS2DQ_DEFVAL 0x00000000 -#define DDR_PHY_PIR_DQS2DQ_SHIFT 20 -#define DDR_PHY_PIR_DQS2DQ_MASK 0x00100000U - -/*RDIMM Initialization*/ -#undef DDR_PHY_PIR_RDIMMINIT_DEFVAL -#undef DDR_PHY_PIR_RDIMMINIT_SHIFT -#undef DDR_PHY_PIR_RDIMMINIT_MASK -#define DDR_PHY_PIR_RDIMMINIT_DEFVAL 0x00000000 -#define DDR_PHY_PIR_RDIMMINIT_SHIFT 19 -#define DDR_PHY_PIR_RDIMMINIT_MASK 0x00080000U - -/*Controller DRAM Initialization*/ -#undef DDR_PHY_PIR_CTLDINIT_DEFVAL -#undef DDR_PHY_PIR_CTLDINIT_SHIFT -#undef DDR_PHY_PIR_CTLDINIT_MASK -#define DDR_PHY_PIR_CTLDINIT_DEFVAL 0x00000000 -#define DDR_PHY_PIR_CTLDINIT_SHIFT 18 -#define DDR_PHY_PIR_CTLDINIT_MASK 0x00040000U - -/*VREF Training*/ -#undef DDR_PHY_PIR_VREF_DEFVAL -#undef DDR_PHY_PIR_VREF_SHIFT -#undef DDR_PHY_PIR_VREF_MASK -#define DDR_PHY_PIR_VREF_DEFVAL 0x00000000 -#define DDR_PHY_PIR_VREF_SHIFT 17 -#define DDR_PHY_PIR_VREF_MASK 0x00020000U - -/*Static Read Training*/ -#undef DDR_PHY_PIR_SRD_DEFVAL -#undef DDR_PHY_PIR_SRD_SHIFT -#undef DDR_PHY_PIR_SRD_MASK -#define DDR_PHY_PIR_SRD_DEFVAL 0x00000000 -#define DDR_PHY_PIR_SRD_SHIFT 16 -#define DDR_PHY_PIR_SRD_MASK 0x00010000U - -/*Write Data Eye Training*/ -#undef DDR_PHY_PIR_WREYE_DEFVAL -#undef DDR_PHY_PIR_WREYE_SHIFT -#undef DDR_PHY_PIR_WREYE_MASK -#define DDR_PHY_PIR_WREYE_DEFVAL 0x00000000 -#define DDR_PHY_PIR_WREYE_SHIFT 15 -#define DDR_PHY_PIR_WREYE_MASK 0x00008000U - -/*Read Data Eye Training*/ -#undef DDR_PHY_PIR_RDEYE_DEFVAL -#undef DDR_PHY_PIR_RDEYE_SHIFT -#undef DDR_PHY_PIR_RDEYE_MASK -#define DDR_PHY_PIR_RDEYE_DEFVAL 0x00000000 -#define DDR_PHY_PIR_RDEYE_SHIFT 14 -#define DDR_PHY_PIR_RDEYE_MASK 0x00004000U - -/*Write Data Bit Deskew*/ -#undef DDR_PHY_PIR_WRDSKW_DEFVAL -#undef DDR_PHY_PIR_WRDSKW_SHIFT -#undef DDR_PHY_PIR_WRDSKW_MASK -#define DDR_PHY_PIR_WRDSKW_DEFVAL 0x00000000 -#define DDR_PHY_PIR_WRDSKW_SHIFT 13 -#define DDR_PHY_PIR_WRDSKW_MASK 0x00002000U - -/*Read Data Bit Deskew*/ -#undef DDR_PHY_PIR_RDDSKW_DEFVAL -#undef DDR_PHY_PIR_RDDSKW_SHIFT -#undef DDR_PHY_PIR_RDDSKW_MASK -#define DDR_PHY_PIR_RDDSKW_DEFVAL 0x00000000 -#define DDR_PHY_PIR_RDDSKW_SHIFT 12 -#define DDR_PHY_PIR_RDDSKW_MASK 0x00001000U - -/*Write Leveling Adjust*/ -#undef DDR_PHY_PIR_WLADJ_DEFVAL -#undef DDR_PHY_PIR_WLADJ_SHIFT -#undef DDR_PHY_PIR_WLADJ_MASK -#define DDR_PHY_PIR_WLADJ_DEFVAL 0x00000000 -#define DDR_PHY_PIR_WLADJ_SHIFT 11 -#define DDR_PHY_PIR_WLADJ_MASK 0x00000800U - -/*Read DQS Gate Training*/ -#undef DDR_PHY_PIR_QSGATE_DEFVAL -#undef DDR_PHY_PIR_QSGATE_SHIFT -#undef DDR_PHY_PIR_QSGATE_MASK -#define DDR_PHY_PIR_QSGATE_DEFVAL 0x00000000 -#define DDR_PHY_PIR_QSGATE_SHIFT 10 -#define DDR_PHY_PIR_QSGATE_MASK 0x00000400U - -/*Write Leveling*/ -#undef DDR_PHY_PIR_WL_DEFVAL -#undef DDR_PHY_PIR_WL_SHIFT -#undef DDR_PHY_PIR_WL_MASK -#define DDR_PHY_PIR_WL_DEFVAL 0x00000000 -#define DDR_PHY_PIR_WL_SHIFT 9 -#define DDR_PHY_PIR_WL_MASK 0x00000200U - -/*DRAM Initialization*/ -#undef DDR_PHY_PIR_DRAMINIT_DEFVAL -#undef DDR_PHY_PIR_DRAMINIT_SHIFT -#undef DDR_PHY_PIR_DRAMINIT_MASK -#define DDR_PHY_PIR_DRAMINIT_DEFVAL 0x00000000 -#define DDR_PHY_PIR_DRAMINIT_SHIFT 8 -#define DDR_PHY_PIR_DRAMINIT_MASK 0x00000100U - -/*DRAM Reset (DDR3/DDR4/LPDDR4 Only)*/ -#undef DDR_PHY_PIR_DRAMRST_DEFVAL -#undef DDR_PHY_PIR_DRAMRST_SHIFT -#undef DDR_PHY_PIR_DRAMRST_MASK -#define DDR_PHY_PIR_DRAMRST_DEFVAL 0x00000000 -#define DDR_PHY_PIR_DRAMRST_SHIFT 7 -#define DDR_PHY_PIR_DRAMRST_MASK 0x00000080U - -/*PHY Reset*/ -#undef DDR_PHY_PIR_PHYRST_DEFVAL -#undef DDR_PHY_PIR_PHYRST_SHIFT -#undef DDR_PHY_PIR_PHYRST_MASK -#define DDR_PHY_PIR_PHYRST_DEFVAL 0x00000000 -#define DDR_PHY_PIR_PHYRST_SHIFT 6 -#define DDR_PHY_PIR_PHYRST_MASK 0x00000040U - -/*Digital Delay Line (DDL) Calibration*/ -#undef DDR_PHY_PIR_DCAL_DEFVAL -#undef DDR_PHY_PIR_DCAL_SHIFT -#undef DDR_PHY_PIR_DCAL_MASK -#define DDR_PHY_PIR_DCAL_DEFVAL 0x00000000 -#define DDR_PHY_PIR_DCAL_SHIFT 5 -#define DDR_PHY_PIR_DCAL_MASK 0x00000020U - -/*PLL Initialiazation*/ -#undef DDR_PHY_PIR_PLLINIT_DEFVAL -#undef DDR_PHY_PIR_PLLINIT_SHIFT -#undef DDR_PHY_PIR_PLLINIT_MASK -#define DDR_PHY_PIR_PLLINIT_DEFVAL 0x00000000 -#define DDR_PHY_PIR_PLLINIT_SHIFT 4 -#define DDR_PHY_PIR_PLLINIT_MASK 0x00000010U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_PIR_RESERVED_3_DEFVAL -#undef DDR_PHY_PIR_RESERVED_3_SHIFT -#undef DDR_PHY_PIR_RESERVED_3_MASK -#define DDR_PHY_PIR_RESERVED_3_DEFVAL 0x00000000 -#define DDR_PHY_PIR_RESERVED_3_SHIFT 3 -#define DDR_PHY_PIR_RESERVED_3_MASK 0x00000008U - -/*CA Training*/ -#undef DDR_PHY_PIR_CA_DEFVAL -#undef DDR_PHY_PIR_CA_SHIFT -#undef DDR_PHY_PIR_CA_MASK -#define DDR_PHY_PIR_CA_DEFVAL 0x00000000 -#define DDR_PHY_PIR_CA_SHIFT 2 -#define DDR_PHY_PIR_CA_MASK 0x00000004U - -/*Impedance Calibration*/ -#undef DDR_PHY_PIR_ZCAL_DEFVAL -#undef DDR_PHY_PIR_ZCAL_SHIFT -#undef DDR_PHY_PIR_ZCAL_MASK -#define DDR_PHY_PIR_ZCAL_DEFVAL 0x00000000 -#define DDR_PHY_PIR_ZCAL_SHIFT 1 -#define DDR_PHY_PIR_ZCAL_MASK 0x00000002U - -/*Initialization Trigger*/ -#undef DDR_PHY_PIR_INIT_DEFVAL -#undef DDR_PHY_PIR_INIT_SHIFT -#undef DDR_PHY_PIR_INIT_MASK -#define DDR_PHY_PIR_INIT_DEFVAL 0x00000000 -#define DDR_PHY_PIR_INIT_SHIFT 0 -#define DDR_PHY_PIR_INIT_MASK 0x00000001U +#define DDR_PHY_DX8SLBDQSCTL_DQSRES_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBDQSCTL_DQSRES_SHIFT 0 +#define DDR_PHY_DX8SLBDQSCTL_DQSRES_MASK 0x0000000FU #undef IOU_SLCR_MIO_PIN_0_OFFSET #define IOU_SLCR_MIO_PIN_0_OFFSET 0XFF180000 #undef IOU_SLCR_MIO_PIN_1_OFFSET @@ -17132,7308 +21605,9482 @@ #undef IOU_SLCR_MIO_LOOPBACK_OFFSET #define IOU_SLCR_MIO_LOOPBACK_OFFSET 0XFF180200 -/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out- (QSPI Clock)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out- + * (QSPI Clock) +*/ #undef IOU_SLCR_MIO_PIN_0_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_0_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_0_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_0_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_0_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_0_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_0_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_0_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_0_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_0_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_0_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_0_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_0_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_0_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_0_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_0_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_0_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_0_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[0]- (Test Scan Port) = test_scan, Outp - t, test_scan_out[0]- (Test Scan Port) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[0]- (Test Scan Port) = test_scan, Output, test_scan_out[0 + * ]- (Test Scan Port) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_0_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_0_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_0_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_0_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_0_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_0_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_0_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_0_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_0_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[0]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[0]- (GPIO bank 0) 1= can - , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa - ) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Cloc - ) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_ - lk- (Trace Port Clock)*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[0]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[0]- (GPIO bank 0) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG + * TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sc + * lk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Out + * put, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_c + * lk- (Trace Port Clock) +*/ #undef IOU_SLCR_MIO_PIN_0_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_0_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_0_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_0_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_0_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_0_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_0_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_0_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_0_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (QSPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Data - us)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (Q + * SPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Databus) +*/ #undef IOU_SLCR_MIO_PIN_1_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_1_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_1_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_1_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_1_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_1_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_1_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_1_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_1_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_1_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_1_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_1_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_1_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_1_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_1_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_1_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_1_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_1_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[1]- (Test Scan Port) = test_scan, Outp - t, test_scan_out[1]- (Test Scan Port) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[1]- (Test Scan Port) = test_scan, Output, test_scan_out[1 + * ]- (Test Scan Port) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_1_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_1_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_1_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_1_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_1_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_1_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_1_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_1_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_1_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[1]- (GPIO bank 0) 1= can - , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal - 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_o - t- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control - Signal)*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[1]- (GPIO bank 0) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG + * TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc3, Ou + * tput, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART + * receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control + * Signal) +*/ #undef IOU_SLCR_MIO_PIN_1_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_1_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_1_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_1_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_1_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_1_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_1_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_1_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_1_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI + * Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus) +*/ #undef IOU_SLCR_MIO_PIN_2_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_2_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_2_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_2_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_2_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_2_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_2_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_2_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_2_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_2_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_2_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_2_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_2_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_2_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_2_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_2_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_2_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_2_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[2]- (Test Scan Port) = test_scan, Outp - t, test_scan_out[2]- (Test Scan Port) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[2]- (Test Scan Port) = test_scan, Output, test_scan_out[2 + * ]- (Test Scan Port) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_2_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_2_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_2_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_2_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_2_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_2_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_2_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_2_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_2_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[2]- (GPIO bank 0) 1= can - , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal - 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc2, Input, ttc2_clk_in - (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[0]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[2]- (GPIO bank 0) 1= can0, Input, can0_phy_ + * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + * , Output, i2c0_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTAG + * TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc2, I + * nput, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver se + * rial input) 7= trace, Output, tracedq[0]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_2_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_2_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_2_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_2_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_2_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_2_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_2_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_2_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_2_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI + * Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus) +*/ #undef IOU_SLCR_MIO_PIN_3_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_3_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_3_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_3_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_3_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_3_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_3_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_3_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_3_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_3_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_3_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_3_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_3_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_3_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_3_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_3_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_3_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_3_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[3]- (Test Scan Port) = test_scan, Outp - t, test_scan_out[3]- (Test Scan Port) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[3]- (Test Scan Port) = test_scan, Output, test_scan_out[3 + * ]- (Test Scan Port) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_3_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_3_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_3_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_3_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_3_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_3_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_3_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_3_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_3_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[3]- (GPIO bank 0) 1= can - , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa - ) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0 - - (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial - output) 7= trace, Output, tracedq[1]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[3]- (GPIO bank 0) 1= can0, Output, can0_phy + * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + * 0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG + * TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output + * , spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- + * (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial + * output) 7= trace, Output, tracedq[1]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_3_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_3_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_3_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_3_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_3_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_3_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_3_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_3_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_3_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- (QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Data - us)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- ( + * QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Databus) +*/ #undef IOU_SLCR_MIO_PIN_4_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_4_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_4_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_4_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_4_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_4_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_4_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_4_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_4_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_4_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_4_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_4_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_4_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_4_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_4_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_4_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_4_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_4_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[4]- (Test Scan Port) = test_scan, Outp - t, test_scan_out[4]- (Test Scan Port) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[4]- (Test Scan Port) = test_scan, Output, test_scan_out[4 + * ]- (Test Scan Port) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_4_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_4_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_4_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_4_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_4_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_4_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_4_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_4_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_4_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[4]- (GPIO bank 0) 1= can - , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa - ) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_s - - (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, - utput, tracedq[2]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[4]- (GPIO bank 0) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Wa + * tch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi + * 0, Output, spi0_so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Cloc + * k) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, O + * utput, tracedq[2]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_4_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_4_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_4_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_4_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_4_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_4_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_4_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_4_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_4_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out- (QSPI Slave Select)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out- + * (QSPI Slave Select) +*/ #undef IOU_SLCR_MIO_PIN_5_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_5_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_5_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_5_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_5_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_5_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_5_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_5_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_5_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_5_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_5_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_5_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_5_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_5_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_5_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_5_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_5_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_5_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[5]- (Test Scan Port) = test_scan, Outp - t, test_scan_out[5]- (Test Scan Port) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[5]- (Test Scan Port) = test_scan, Output, test_scan_out[5 + * ]- (Test Scan Port) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_5_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_5_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_5_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_5_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_5_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_5_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_5_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_5_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_5_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[5]- (GPIO bank 0) 1= can - , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal - 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi0 - si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7 - trace, Output, tracedq[3]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[5]- (GPIO bank 0) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (W + * atch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= + * spi0, Input, spi0_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC + * Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= + * trace, Output, tracedq[3]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_5_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_5_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_5_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_5_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_5_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_5_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_5_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_5_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_5_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_clk_for_lpbk- (QSPI Clock to be fed-back)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_clk_for_l + * pbk- (QSPI Clock to be fed-back) +*/ #undef IOU_SLCR_MIO_PIN_6_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_6_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_6_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_6_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_6_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_6_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_6_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_6_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_6_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_6_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_6_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_6_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_6_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_6_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_6_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_6_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_6_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_6_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[6]- (Test Scan Port) = test_scan, Outp - t, test_scan_out[6]- (Test Scan Port) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[6]- (Test Scan Port) = test_scan, Output, test_scan_out[6 + * ]- (Test Scan Port) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_6_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_6_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_6_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_6_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_6_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_6_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_6_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_6_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_6_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[6]- (GPIO bank 0) 1= can - , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal - 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1 - sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, - Output, tracedq[4]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[6]- (GPIO bank 0) 1= can0, Input, can0_phy_ + * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + * , Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Wat + * ch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= s + * pi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TT + * C Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, + * Output, tracedq[4]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_6_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_6_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_6_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_6_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_6_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_6_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_6_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_6_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_6_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out_upper- (QSPI Slave Select upper)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out_ + * upper- (QSPI Slave Select upper) +*/ #undef IOU_SLCR_MIO_PIN_7_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_7_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_7_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_7_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_7_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_7_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_7_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_7_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_7_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_7_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_7_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_7_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_7_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_7_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_7_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_7_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_7_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_7_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[7]- (Test Scan Port) = test_scan, Outp - t, test_scan_out[7]- (Test Scan Port) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[7]- (Test Scan Port) = test_scan, Output, test_scan_out[7 + * ]- (Test Scan Port) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_7_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_7_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_7_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_7_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_7_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_7_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_7_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_7_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_7_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[7]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[7]- (GPIO bank 0) 1= can - , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa - ) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= - tc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, - racedq[5]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[7]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[7]- (GPIO bank 0) 1= can0, Output, can0_phy + * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + * 0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- ( + * Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Ma + * ster Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua + * 0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, t + * racedq[5]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_7_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_7_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_7_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_7_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_7_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_7_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_7_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_7_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_7_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[0]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe - [0]- (QSPI Upper Databus)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[0 + * ]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[0]- (QSPI Upper D + * atabus) +*/ #undef IOU_SLCR_MIO_PIN_8_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_8_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_8_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_8_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_8_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_8_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_8_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_8_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_8_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_8_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_8_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_8_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_8_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_8_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_8_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_8_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_8_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_8_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[8]- (Test Scan Port) = test_scan, Outp - t, test_scan_out[8]- (Test Scan Port) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[8]- (Test Scan Port) = test_scan, Output, test_scan_out[8 + * ]- (Test Scan Port) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_8_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_8_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_8_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_8_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_8_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_8_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_8_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_8_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_8_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[8]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[8]- (GPIO bank 0) 1= can - , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa - ) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc - , Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Tr - ce Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[8]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[8]- (GPIO bank 0) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Wa + * tch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Maste + * r Selects) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_ + * txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Tra + * ce Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_8_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_8_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_8_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_8_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_8_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_8_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_8_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_8_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_8_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[1]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe - [1]- (QSPI Upper Databus)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[1 + * ]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[1]- (QSPI Upper D + * atabus) +*/ #undef IOU_SLCR_MIO_PIN_9_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_9_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_9_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_9_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_9_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_9_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_9_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_9_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_9_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NAND chip enable)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NA + * ND chip enable) +*/ #undef IOU_SLCR_MIO_PIN_9_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_9_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_9_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_9_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_9_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_9_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_9_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_9_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_9_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[9]- (Test Scan Port) = test_scan, Outp - t, test_scan_out[9]- (Test Scan Port) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[9]- (Test Scan Port) = test_scan, Output, test_scan_out[9 + * ]- (Test Scan Port) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_9_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_9_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_9_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_9_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_9_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_9_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_9_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_9_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_9_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[9]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[9]- (GPIO bank 0) 1= can - , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal - 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, - utput, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (U - RT receiver serial input) 7= trace, Output, tracedq[7]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[9]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[9]- (GPIO bank 0) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (W + * atch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master S + * elects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc3, + * Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UA + * RT receiver serial input) 7= trace, Output, tracedq[7]- (Trace Port Data + * bus) +*/ #undef IOU_SLCR_MIO_PIN_9_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_9_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_9_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_9_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_9_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_9_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_9_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_9_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_9_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[2]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe - [2]- (QSPI Upper Databus)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[2 + * ]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[2]- (QSPI Upper D + * atabus) +*/ #undef IOU_SLCR_MIO_PIN_10_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_10_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_10_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_10_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_10_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_10_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_10_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_10_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_10_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (NAND Ready/Busy)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (N + * AND Ready/Busy) +*/ #undef IOU_SLCR_MIO_PIN_10_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_10_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_10_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_10_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_10_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_10_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_10_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_10_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_10_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[10]- (Test Scan Port) = test_scan, Out - ut, test_scan_out[10]- (Test Scan Port) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[10]- (Test Scan Port) = test_scan, Output, test_scan_out[ + * 10]- (Test Scan Port) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_10_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_10_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_10_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_10_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_10_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_10_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_10_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_10_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_10_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[10]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[10]- (GPIO bank 0) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_ - o- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outp - t, tracedq[8]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[10]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[10]- (GPIO bank 0) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= sp + * i1, Output, spi1_so- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clo + * ck) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outpu + * t, tracedq[8]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_10_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_10_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_10_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_10_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_10_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_10_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_10_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_10_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_10_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[3]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe - [3]- (QSPI Upper Databus)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[3 + * ]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[3]- (QSPI Upper D + * atabus) +*/ #undef IOU_SLCR_MIO_PIN_11_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_11_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_11_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_11_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_11_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_11_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_11_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_11_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_11_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (NAND Ready/Busy)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (N + * AND Ready/Busy) +*/ #undef IOU_SLCR_MIO_PIN_11_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_11_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_11_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_11_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_11_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_11_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_11_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_11_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_11_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[11]- (Test Scan Port) = test_scan, Out - ut, test_scan_out[11]- (Test Scan Port) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[11]- (Test Scan Port) = test_scan, Output, test_scan_out[ + * 11]- (Test Scan Port) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_11_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_11_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_11_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_11_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_11_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_11_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_11_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_11_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_11_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s - i1_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o - tput) 7= trace, Output, tracedq[9]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) + * 4= spi1, Input, spi1_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- ( + * TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial ou + * tput) 7= trace, Output, tracedq[9]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_11_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_11_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_11_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_11_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_11_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_11_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_11_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_11_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_11_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out_upper- (QSPI Upper Clock)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out_ + * upper- (QSPI Upper Clock) +*/ #undef IOU_SLCR_MIO_PIN_12_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_12_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_12_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_12_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_12_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_12_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_12_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_12_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_12_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NAND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe - */ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NA + * ND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe) +*/ #undef IOU_SLCR_MIO_PIN_12_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_12_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_12_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_12_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_12_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_12_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_12_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_12_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_12_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[12]- (Test Scan Port) = test_scan, Out - ut, test_scan_out[12]- (Test Scan Port) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[12]- (Test Scan Port) = test_scan, Output, test_scan_out[ + * 12]- (Test Scan Port) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_12_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_12_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_12_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_12_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_12_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_12_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_12_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_12_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_12_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[12]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[12]- (GPIO bank 0) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Cl - ck) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trac - dq[10]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[12]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[12]- (GPIO bank 0) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJT + * AG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_ + * sclk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, O + * utput, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace + * dq[10]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_12_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_12_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_12_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_12_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_12_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_12_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_12_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_12_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_12_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_13_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_13_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_13_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_13_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_13_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_13_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_13_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_13_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_13_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[0]- (NAND chip enable)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[0]- (NA + * ND chip enable) +*/ #undef IOU_SLCR_MIO_PIN_13_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_13_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_13_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_13_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_13_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_13_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_13_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_13_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_13_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8 - bit Data bus) 2= test_scan, Input, test_scan_in[13]- (Test Scan Port) = test_scan, Output, test_scan_out[13]- (Test Scan Port - 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[13]- (Test Scan Port) = test_scan, Output, + * test_scan_out[13]- (Test Scan Port) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_13_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_13_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_13_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_13_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_13_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_13_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_13_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_13_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_13_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[13]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[13]- (GPIO bank 0) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave - out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq[11]- (Trace Port Dat - bus)*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[13]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[13]- (GPIO bank 0) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTA + * G TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, + * Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UAR + * T receiver serial input) 7= trace, Output, tracedq[11]- (Trace Port Data + * bus) +*/ #undef IOU_SLCR_MIO_PIN_13_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_13_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_13_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_13_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_13_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_13_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_13_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_13_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_13_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_14_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_14_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_14_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_14_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_14_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_14_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_14_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_14_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_14_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_cle- (NAND Command Latch Enable)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_cle- (NAND + * Command Latch Enable) +*/ #undef IOU_SLCR_MIO_PIN_14_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_14_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_14_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_14_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_14_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_14_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_14_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_14_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_14_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8 - bit Data bus) 2= test_scan, Input, test_scan_in[14]- (Test Scan Port) = test_scan, Output, test_scan_out[14]- (Test Scan Port - 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[14]- (Test Scan Port) = test_scan, Output, + * test_scan_out[14]- (Test Scan Port) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_14_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_14_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_14_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_14_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_14_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_14_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_14_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_14_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_14_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, Input, ttc0_clk_ - n- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJT + * AG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, + * Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver + * serial input) 7= trace, Output, tracedq[12]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_14_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_14_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_14_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_14_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_14_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_14_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_14_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_14_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_14_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_15_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_15_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_15_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_15_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_15_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_15_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_15_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_15_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_15_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ale- (NAND Address Latch Enable)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ale- (NAND + * Address Latch Enable) +*/ #undef IOU_SLCR_MIO_PIN_15_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_15_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_15_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_15_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_15_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_15_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_15_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_15_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_15_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8 - bit Data bus) 2= test_scan, Input, test_scan_in[15]- (Test Scan Port) = test_scan, Output, test_scan_out[15]- (Test Scan Port - 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[15]- (Test Scan Port) = test_scan, Output, + * test_scan_out[15]- (Test Scan Port) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_15_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_15_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_15_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_15_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_15_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_15_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_15_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_15_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_15_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[15]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[15]- (GPIO bank 0) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out - 0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter seri - l output) 7= trace, Output, tracedq[13]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[15]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[15]- (GPIO bank 0) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJT + * AG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Outp + * ut, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_ou + * t- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter seria + * l output) 7= trace, Output, tracedq[13]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_15_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_15_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_15_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_15_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_15_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_15_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_15_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_15_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_15_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_16_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_16_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_16_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_16_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_16_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_16_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_16_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_16_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_16_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[0]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[0]- (NAND - ata Bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[0]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[0]- (NAND Data Bus) +*/ #undef IOU_SLCR_MIO_PIN_16_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_16_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_16_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_16_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_16_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_16_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_16_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_16_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_16_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8 - bit Data bus) 2= test_scan, Input, test_scan_in[16]- (Test Scan Port) = test_scan, Output, test_scan_out[16]- (Test Scan Port - 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[16]- (Test Scan Port) = test_scan, Output, + * test_scan_out[16]- (Test Scan Port) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_16_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_16_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_16_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_16_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_16_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_16_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_16_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_16_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_16_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[16]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[16]- (GPIO bank 0) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0 - so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace - Output, tracedq[14]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[16]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[16]- (GPIO bank 0) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= s + * pi0, Output, spi0_so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Cl + * ock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, + * Output, tracedq[14]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_16_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_16_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_16_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_16_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_16_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_16_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_16_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_16_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_16_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_17_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_17_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_17_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_17_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_17_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_17_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_17_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_17_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_17_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[1]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[1]- (NAND - ata Bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[1]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[1]- (NAND Data Bus) +*/ #undef IOU_SLCR_MIO_PIN_17_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_17_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_17_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_17_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_17_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_17_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_17_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_17_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_17_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8 - bit Data bus) 2= test_scan, Input, test_scan_in[17]- (Test Scan Port) = test_scan, Output, test_scan_out[17]- (Test Scan Port - 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[17]- (Test Scan Port) = test_scan, Output, + * test_scan_out[17]- (Test Scan Port) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_17_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_17_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_17_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_17_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_17_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_17_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_17_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_17_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_17_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[17]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[17]- (GPIO bank 0) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, sp - 0_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) - 7= trace, Output, tracedq[15]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[17]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[17]- (GPIO bank 0) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4 + * = spi0, Input, spi0_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (T + * TC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) + * 7= trace, Output, tracedq[15]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_17_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_17_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_17_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_17_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_17_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_17_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_17_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_17_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_17_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_18_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_18_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_18_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_18_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_18_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_18_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_18_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_18_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_18_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[2]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[2]- (NAND - ata Bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[2]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[2]- (NAND Data Bus) +*/ #undef IOU_SLCR_MIO_PIN_18_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_18_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_18_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_18_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_18_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_18_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_18_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_18_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_18_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8 - bit Data bus) 2= test_scan, Input, test_scan_in[18]- (Test Scan Port) = test_scan, Output, test_scan_out[18]- (Test Scan Port - 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[18]- (Test Scan Port) = test_scan, Output, + * test_scan_out[18]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU + * Ext Tamper) +*/ #undef IOU_SLCR_MIO_PIN_18_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_18_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_18_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_18_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_18_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_18_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_18_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_18_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_18_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[18]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[18]- (GPIO bank 0) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_ - o- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[18]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[18]- (GPIO bank 0) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= sp + * i1, Output, spi1_so- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clo + * ck) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used +*/ #undef IOU_SLCR_MIO_PIN_18_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_18_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_18_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_18_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_18_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_18_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_18_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_18_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_18_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_19_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_19_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_19_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_19_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_19_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_19_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_19_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_19_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_19_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[3]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[3]- (NAND - ata Bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[3]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[3]- (NAND Data Bus) +*/ #undef IOU_SLCR_MIO_PIN_19_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_19_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_19_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_19_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_19_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_19_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_19_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_19_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_19_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8 - bit Data bus) 2= test_scan, Input, test_scan_in[19]- (Test Scan Port) = test_scan, Output, test_scan_out[19]- (Test Scan Port - 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[19]- (Test Scan Port) = test_scan, Output, + * test_scan_out[19]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU + * Ext Tamper) +*/ #undef IOU_SLCR_MIO_PIN_19_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_19_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_19_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_19_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_19_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_19_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_19_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_19_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_19_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[19]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[19]- (GPIO bank 0) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5 - ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[19]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[19]- (GPIO bank 0) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI + * Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= + * ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used +*/ #undef IOU_SLCR_MIO_PIN_19_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_19_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_19_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_19_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_19_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_19_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_19_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_19_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_19_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_20_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_20_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_20_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_20_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_20_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_20_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_20_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_20_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_20_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[4]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[4]- (NAND - ata Bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[4]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[4]- (NAND Data Bus) +*/ #undef IOU_SLCR_MIO_PIN_20_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_20_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_20_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_20_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_20_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_20_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_20_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_20_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_20_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8 - bit Data bus) 2= test_scan, Input, test_scan_in[20]- (Test Scan Port) = test_scan, Output, test_scan_out[20]- (Test Scan Port - 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[20]- (Test Scan Port) = test_scan, Output, + * test_scan_out[20]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU + * Ext Tamper) +*/ #undef IOU_SLCR_MIO_PIN_20_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_20_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_20_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_20_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_20_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_20_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_20_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_20_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_20_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[20]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[20]- (GPIO bank 0) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= t - c1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Used*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[20]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[20]- (GPIO bank 0) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Mas + * ter Selects) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua + * 1_txd- (UART transmitter serial output) 7= Not Used +*/ #undef IOU_SLCR_MIO_PIN_20_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_20_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_20_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_20_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_20_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_20_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_20_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_20_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_20_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_21_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_21_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_21_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_21_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_21_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_21_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_21_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_21_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_21_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[5]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[5]- (NAND - ata Bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[5]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[5]- (NAND Data Bus) +*/ #undef IOU_SLCR_MIO_PIN_21_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_21_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_21_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_21_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_21_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_21_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_21_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_21_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_21_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Comman - Indicator) 2= test_scan, Input, test_scan_in[21]- (Test Scan Port) = test_scan, Output, test_scan_out[21]- (Test Scan Port) - = csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Com + * mand Indicator) = sd0, Output, sdio0_cmd_out- (Command Indicator) 2= tes + * t_scan, Input, test_scan_in[21]- (Test Scan Port) = test_scan, Output, t + * est_scan_out[21]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU E + * xt Tamper) +*/ #undef IOU_SLCR_MIO_PIN_21_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_21_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_21_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_21_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_21_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_21_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_21_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_21_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_21_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[21]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[21]- (GPIO bank 0) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1 - Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- - UART receiver serial input) 7= Not Used*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[21]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[21]- (GPIO bank 0) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master + * Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc + * 1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- ( + * UART receiver serial input) 7= Not Used +*/ #undef IOU_SLCR_MIO_PIN_21_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_21_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_21_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_21_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_21_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_21_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_21_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_21_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_21_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_22_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_22_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_22_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_22_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_22_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_22_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_22_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_22_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_22_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_we_b- (NAND Write Enable)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_we_b- (NAN + * D Write Enable) +*/ #undef IOU_SLCR_MIO_PIN_22_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_22_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_22_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_22_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_22_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_22_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_22_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_22_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_22_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= test_scan, Input, test_scan_in[22]- - (Test Scan Port) = test_scan, Output, test_scan_out[22]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- + * (SDSDIO clock) 2= test_scan, Input, test_scan_in[22]- (Test Scan Port) = + * test_scan, Output, test_scan_out[22]- (Test Scan Port) 3= csu, Input, c + * su_ext_tamper- (CSU Ext Tamper) +*/ #undef IOU_SLCR_MIO_PIN_22_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_22_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_22_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_22_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_22_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_22_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_22_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_22_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_22_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[22]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[22]- (GPIO bank 0) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, sp - 1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not - sed*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[22]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[22]- (GPIO bank 0) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= + * spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- ( + * TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not U + * sed +*/ #undef IOU_SLCR_MIO_PIN_22_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_22_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_22_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_22_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_22_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_22_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_22_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_22_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_22_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_23_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_23_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_23_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_23_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_23_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_23_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_23_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_23_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_23_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[6]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[6]- (NAND - ata Bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[6]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[6]- (NAND Data Bus) +*/ #undef IOU_SLCR_MIO_PIN_23_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_23_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_23_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_23_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_23_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_23_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_23_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_23_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_23_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= test_scan, Input, test_scan_in - 23]- (Test Scan Port) = test_scan, Output, test_scan_out[23]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper - */ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- + * (SD card bus power) 2= test_scan, Input, test_scan_in[23]- (Test Scan Po + * rt) = test_scan, Output, test_scan_out[23]- (Test Scan Port) 3= csu, Inp + * ut, csu_ext_tamper- (CSU Ext Tamper) +*/ #undef IOU_SLCR_MIO_PIN_23_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_23_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_23_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_23_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_23_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_23_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_23_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_23_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_23_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[23]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[23]- (GPIO bank 0) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s - i1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o - tput) 7= Not Used*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[23]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[23]- (GPIO bank 0) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) + * 4= spi1, Input, spi1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- ( + * TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial ou + * tput) 7= Not Used +*/ #undef IOU_SLCR_MIO_PIN_23_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_23_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_23_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_23_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_23_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_23_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_23_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_23_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_23_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_24_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_24_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_24_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_24_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_24_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_24_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_24_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_24_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_24_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[7]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[7]- (NAND - ata Bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[7]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[7]- (NAND Data Bus) +*/ #undef IOU_SLCR_MIO_PIN_24_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_24_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_24_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_24_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_24_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_24_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_24_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_24_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_24_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= test_scan, Input, test - scan_in[24]- (Test Scan Port) = test_scan, Output, test_scan_out[24]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ex - Tamper)*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD + * card detect from connector) 2= test_scan, Input, test_scan_in[24]- (Test + * Scan Port) = test_scan, Output, test_scan_out[24]- (Test Scan Port) 3= + * csu, Input, csu_ext_tamper- (CSU Ext Tamper) +*/ #undef IOU_SLCR_MIO_PIN_24_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_24_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_24_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_24_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_24_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_24_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_24_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_24_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_24_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[24]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[24]- (GPIO bank 0) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= Not Used 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, - Output, ua1_txd- (UART transmitter serial output) 7= Not Used*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[24]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[24]- (GPIO bank 0) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= Not Used 5= ttc3, Input, ttc3_clk_in- (T + * TC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= N + * ot Used +*/ #undef IOU_SLCR_MIO_PIN_24_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_24_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_24_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_24_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_24_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_24_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_24_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_24_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_24_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_25_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_25_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_25_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_25_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_25_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_25_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_25_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_25_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_25_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_re_n- (NAND Read Enable)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_re_n- (NAN + * D Read Enable) +*/ #undef IOU_SLCR_MIO_PIN_25_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_25_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_25_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_25_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_25_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_25_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_25_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_25_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_25_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= test_scan, Input, - test_scan_in[25]- (Test Scan Port) = test_scan, Output, test_scan_out[25]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (C - U Ext Tamper)*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD ca + * rd write protect from connector) 2= test_scan, Input, test_scan_in[25]- + * (Test Scan Port) = test_scan, Output, test_scan_out[25]- (Test Scan Port + * ) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper) +*/ #undef IOU_SLCR_MIO_PIN_25_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_25_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_25_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_25_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_25_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_25_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_25_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_25_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_25_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[25]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[25]- (GPIO bank 0) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= Not Used 5= ttc3, Output, ttc3_wave_out- (TTC Waveform - lock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[25]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[25]- (GPIO bank 0) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= Not Used 5= ttc3, Output, ttc3_wave_ou + * t- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial in + * put) 7= Not Used +*/ #undef IOU_SLCR_MIO_PIN_25_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_25_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_25_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_25_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_25_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_25_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_25_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_25_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_25_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_clk- (TX RGMII clock)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ + * clk- (TX RGMII clock) +*/ #undef IOU_SLCR_MIO_PIN_26_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_26_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_26_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_26_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_26_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_26_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_26_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_26_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_26_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NAND chip enable)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NA + * ND chip enable) +*/ #undef IOU_SLCR_MIO_PIN_26_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_26_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_26_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_26_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_26_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_26_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_26_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_26_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_26_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[0]- (PMU GPI) 2= test_scan, Input, test_scan_in[26]- (Test Sc - n Port) = test_scan, Output, test_scan_out[26]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[0]- (PMU + * GPI) 2= test_scan, Input, test_scan_in[26]- (Test Scan Port) = test_sca + * n, Output, test_scan_out[26]- (Test Scan Port) 3= csu, Input, csu_ext_ta + * mper- (CSU Ext Tamper) +*/ #undef IOU_SLCR_MIO_PIN_26_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_26_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_26_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_26_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_26_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_26_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_26_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_26_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_26_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[0]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[0]- (GPIO bank 1) 1= can - , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal - 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Clock - 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- - Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[0]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[0]- (GPIO bank 1) 1= can0, Input, can0_phy_ + * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + * , Output, i2c0_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG + * TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_scl + * k_out- (SPI Clock) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Inpu + * t, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- ( + * Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_26_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_26_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_26_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_26_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_26_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_26_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_26_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_26_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_26_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[0]- (TX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd + * [0]- (TX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_27_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_27_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_27_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_27_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_27_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_27_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_27_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_27_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_27_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (NAND Ready/Busy)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (N + * AND Ready/Busy) +*/ #undef IOU_SLCR_MIO_PIN_27_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_27_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_27_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_27_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_27_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_27_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_27_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_27_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_27_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[1]- (PMU GPI) 2= test_scan, Input, test_scan_in[27]- (Test Sc - n Port) = test_scan, Output, test_scan_out[27]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Outp - t, dp_aux_data_out- (Dp Aux Data)*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[1]- (PMU + * GPI) 2= test_scan, Input, test_scan_in[27]- (Test Scan Port) = test_sca + * n, Output, test_scan_out[27]- (Test Scan Port) 3= dpaux, Input, dp_aux_d + * ata_in- (Dp Aux Data) = dpaux, Output, dp_aux_data_out- (Dp Aux Data) +*/ #undef IOU_SLCR_MIO_PIN_27_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_27_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_27_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_27_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_27_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_27_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_27_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_27_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_27_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[1]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[1]- (GPIO bank 1) 1= can - , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa - ) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_ - ut- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port - atabus)*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[1]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[1]- (GPIO bank 1) 1= can0, Output, can0_phy + * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + * 0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG + * TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc2, O + * utput, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UAR + * T transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port D + * atabus) +*/ #undef IOU_SLCR_MIO_PIN_27_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_27_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_27_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_27_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_27_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_27_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_27_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_27_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_27_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[1]- (TX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd + * [1]- (TX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_28_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_28_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_28_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_28_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_28_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_28_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_28_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_28_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_28_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (NAND Ready/Busy)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (N + * AND Ready/Busy) +*/ #undef IOU_SLCR_MIO_PIN_28_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_28_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_28_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_28_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_28_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_28_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_28_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_28_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_28_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[2]- (PMU GPI) 2= test_scan, Input, test_scan_in[28]- (Test Sc - n Port) = test_scan, Output, test_scan_out[28]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[2]- (PMU + * GPI) 2= test_scan, Input, test_scan_in[28]- (Test Scan Port) = test_sca + * n, Output, test_scan_out[28]- (Test Scan Port) 3= dpaux, Input, dp_hot_p + * lug_detect- (Dp Aux Hot Plug) +*/ #undef IOU_SLCR_MIO_PIN_28_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_28_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_28_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_28_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_28_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_28_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_28_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_28_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_28_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[2]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[2]- (GPIO bank 1) 1= can - , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa - ) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc1, Input, ttc1_clk_i - - (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[2]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[2]- (GPIO bank 1) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTA + * G TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc1, + * Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitt + * er serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_28_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_28_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_28_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_28_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_28_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_28_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_28_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_28_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_28_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[2]- (TX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd + * [2]- (TX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_29_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_29_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_29_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_29_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_29_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_29_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_29_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_29_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_29_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + * PCIE Reset signal) +*/ #undef IOU_SLCR_MIO_PIN_29_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_29_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_29_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_29_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_29_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_29_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_29_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_29_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_29_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[3]- (PMU GPI) 2= test_scan, Input, test_scan_in[29]- (Test Sc - n Port) = test_scan, Output, test_scan_out[29]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Outp - t, dp_aux_data_out- (Dp Aux Data)*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[3]- (PMU + * GPI) 2= test_scan, Input, test_scan_in[29]- (Test Scan Port) = test_sca + * n, Output, test_scan_out[29]- (Test Scan Port) 3= dpaux, Input, dp_aux_d + * ata_in- (Dp Aux Data) = dpaux, Output, dp_aux_data_out- (Dp Aux Data) +*/ #undef IOU_SLCR_MIO_PIN_29_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_29_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_29_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_29_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_29_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_29_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_29_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_29_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_29_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[3]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[3]- (GPIO bank 1) 1= can - , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal - 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0] - (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial inpu - ) 7= trace, Output, tracedq[7]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[3]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[3]- (GPIO bank 1) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG + * TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, + * spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- + * (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input + * ) 7= trace, Output, tracedq[7]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_29_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_29_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_29_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_29_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_29_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_29_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_29_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_29_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_29_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[3]- (TX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd + * [3]- (TX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_30_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_30_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_30_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_30_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_30_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_30_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_30_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_30_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_30_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + * PCIE Reset signal) +*/ #undef IOU_SLCR_MIO_PIN_30_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_30_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_30_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_30_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_30_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_30_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_30_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_30_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_30_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[4]- (PMU GPI) 2= test_scan, Input, test_scan_in[30]- (Test Sc - n Port) = test_scan, Output, test_scan_out[30]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[4]- (PMU + * GPI) 2= test_scan, Input, test_scan_in[30]- (Test Scan Port) = test_sca + * n, Output, test_scan_out[30]- (Test Scan Port) 3= dpaux, Input, dp_hot_p + * lug_detect- (Dp Aux Hot Plug) +*/ #undef IOU_SLCR_MIO_PIN_30_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_30_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_30_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_30_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_30_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_30_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_30_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_30_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_30_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[4]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[4]- (GPIO bank 1) 1= can - , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal - 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_so - (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output - tracedq[8]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[4]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[4]- (GPIO bank 1) 1= can0, Input, can0_phy_ + * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + * , Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Wat + * ch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0 + * , Output, spi0_so- (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clock + * ) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, + * tracedq[8]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_30_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_30_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_30_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_30_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_30_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_30_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_30_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_30_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_30_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ctl- (TX RGMII control)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ + * ctl- (TX RGMII control) +*/ #undef IOU_SLCR_MIO_PIN_31_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_31_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_31_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_31_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_31_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_31_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_31_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_31_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_31_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + * PCIE Reset signal) +*/ #undef IOU_SLCR_MIO_PIN_31_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_31_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_31_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_31_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_31_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_31_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_31_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_31_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_31_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[5]- (PMU GPI) 2= test_scan, Input, test_scan_in[31]- (Test Sc - n Port) = test_scan, Output, test_scan_out[31]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[5]- (PMU + * GPI) 2= test_scan, Input, test_scan_in[31]- (Test Scan Port) = test_sca + * n, Output, test_scan_out[31]- (Test Scan Port) 3= csu, Input, csu_ext_ta + * mper- (CSU Ext Tamper) +*/ #undef IOU_SLCR_MIO_PIN_31_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_31_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_31_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_31_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_31_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_31_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_31_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_31_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_31_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[5]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[5]- (GPIO bank 1) 1= can - , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa - ) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi - _si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial out - ut) 7= trace, Output, tracedq[9]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[5]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[5]- (GPIO bank 1) 1= can0, Output, can0_phy + * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + * 0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- ( + * Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= + * spi0, Input, spi0_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TT + * C Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial outp + * ut) 7= trace, Output, tracedq[9]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_31_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_31_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_31_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_31_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_31_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_31_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_31_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_31_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_31_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_clk- (RX RGMII clock)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_c + * lk- (RX RGMII clock) +*/ #undef IOU_SLCR_MIO_PIN_32_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_32_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_32_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_32_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_32_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_32_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_32_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_32_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_32_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NAND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe - */ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NA + * ND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe) +*/ #undef IOU_SLCR_MIO_PIN_32_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_32_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_32_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_32_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_32_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_32_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_32_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_32_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_32_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[0]- (PMU GPI) 2= test_scan, Input, test_scan_in[32]- (Test S - an Port) = test_scan, Output, test_scan_out[32]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[0]- (PM + * U GPI) 2= test_scan, Input, test_scan_in[32]- (Test Scan Port) = test_sc + * an, Output, test_scan_out[32]- (Test Scan Port) 3= csu, Input, csu_ext_t + * amper- (CSU Ext Tamper) +*/ #undef IOU_SLCR_MIO_PIN_32_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_32_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_32_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_32_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_32_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_32_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_32_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_32_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_32_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[6]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[6]- (GPIO bank 1) 1= can - , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa - ) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi - _sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= - race, Output, tracedq[10]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[6]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[6]- (GPIO bank 1) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Wa + * tch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= + * spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (T + * TC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= t + * race, Output, tracedq[10]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_32_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_32_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_32_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_32_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_32_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_32_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_32_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_32_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_32_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[0]- (RX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[ + * 0]- (RX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_33_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_33_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_33_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_33_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_33_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_33_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_33_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_33_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_33_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + * PCIE Reset signal) +*/ #undef IOU_SLCR_MIO_PIN_33_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_33_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_33_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_33_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_33_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_33_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_33_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_33_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_33_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[1]- (PMU GPI) 2= test_scan, Input, test_scan_in[33]- (Test S - an Port) = test_scan, Output, test_scan_out[33]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[1]- (PM + * U GPI) 2= test_scan, Input, test_scan_in[33]- (Test Scan Port) = test_sc + * an, Output, test_scan_out[33]- (Test Scan Port) 3= csu, Input, csu_ext_t + * amper- (CSU Ext Tamper) +*/ #undef IOU_SLCR_MIO_PIN_33_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_33_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_33_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_33_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_33_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_33_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_33_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_33_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_33_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[7]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[7]- (GPIO bank 1) 1= can - , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal - 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= t - c3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, traced - [11]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[7]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[7]- (GPIO bank 1) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (W + * atch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Mas + * ter Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1 + * , Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq + * [11]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_33_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_33_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_33_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_33_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_33_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_33_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_33_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_33_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_33_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[1]- (RX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[ + * 1]- (RX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_34_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_34_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_34_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_34_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_34_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_34_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_34_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_34_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_34_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + * PCIE Reset signal) +*/ #undef IOU_SLCR_MIO_PIN_34_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_34_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_34_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_34_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_34_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_34_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_34_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_34_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_34_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[2]- (PMU GPI) 2= test_scan, Input, test_scan_in[34]- (Test S - an Port) = test_scan, Output, test_scan_out[34]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Out - ut, dp_aux_data_out- (Dp Aux Data)*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[2]- (PM + * U GPI) 2= test_scan, Input, test_scan_in[34]- (Test Scan Port) = test_sc + * an, Output, test_scan_out[34]- (Test Scan Port) 3= dpaux, Input, dp_aux_ + * data_in- (Dp Aux Data) = dpaux, Output, dp_aux_data_out- (Dp Aux Data) +*/ #undef IOU_SLCR_MIO_PIN_34_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_34_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_34_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_34_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_34_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_34_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_34_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_34_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_34_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[8]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[8]- (GPIO bank 1) 1= can - , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal - 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc2 - Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace P - rt Databus)*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[8]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[8]- (GPIO bank 1) 1= can0, Input, can0_phy_ + * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + * , Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Wat + * ch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master + * Selects) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rx + * d- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace Po + * rt Databus) +*/ #undef IOU_SLCR_MIO_PIN_34_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_34_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_34_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_34_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_34_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_34_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_34_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_34_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_34_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[2]- (RX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[ + * 2]- (RX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_35_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_35_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_35_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_35_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_35_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_35_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_35_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_35_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_35_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + * PCIE Reset signal) +*/ #undef IOU_SLCR_MIO_PIN_35_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_35_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_35_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_35_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_35_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_35_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_35_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_35_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_35_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[3]- (PMU GPI) 2= test_scan, Input, test_scan_in[35]- (Test S - an Port) = test_scan, Output, test_scan_out[35]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[3]- (PM + * U GPI) 2= test_scan, Input, test_scan_in[35]- (Test Scan Port) = test_sc + * an, Output, test_scan_out[35]- (Test Scan Port) 3= dpaux, Input, dp_hot_ + * plug_detect- (Dp Aux Hot Plug) +*/ #undef IOU_SLCR_MIO_PIN_35_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_35_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_35_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_35_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_35_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_35_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_35_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_35_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_35_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[9]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[9]- (GPIO bank 1) 1= can - , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa - ) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, - Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- - UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[9]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[9]- (GPIO bank 1) 1= can0, Output, can0_phy + * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + * 0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- ( + * Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master + * Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc2 + * , Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- ( + * UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace Po + * rt Databus) +*/ #undef IOU_SLCR_MIO_PIN_35_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_35_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_35_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_35_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_35_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_35_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_35_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_35_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_35_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[3]- (RX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[ + * 3]- (RX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_36_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_36_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_36_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_36_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_36_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_36_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_36_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_36_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_36_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + * PCIE Reset signal) +*/ #undef IOU_SLCR_MIO_PIN_36_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_36_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_36_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_36_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_36_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_36_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_36_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_36_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_36_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[4]- (PMU GPI) 2= test_scan, Input, test_scan_in[36]- (Test S - an Port) = test_scan, Output, test_scan_out[36]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Out - ut, dp_aux_data_out- (Dp Aux Data)*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[4]- (PM + * U GPI) 2= test_scan, Input, test_scan_in[36]- (Test Scan Port) = test_sc + * an, Output, test_scan_out[36]- (Test Scan Port) 3= dpaux, Input, dp_aux_ + * data_in- (Dp Aux Data) = dpaux, Output, dp_aux_data_out- (Dp Aux Data) +*/ #undef IOU_SLCR_MIO_PIN_36_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_36_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_36_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_36_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_36_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_36_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_36_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_36_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_36_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[10]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[10]- (GPIO bank 1) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1 - so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace - Output, tracedq[14]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[10]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[10]- (GPIO bank 1) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= s + * pi1, Output, spi1_so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Cl + * ock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, + * Output, tracedq[14]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_36_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_36_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_36_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_36_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_36_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_36_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_36_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_36_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_36_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_ctl- (RX RGMII control )*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_c + * tl- (RX RGMII control ) +*/ #undef IOU_SLCR_MIO_PIN_37_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_37_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_37_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_37_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_37_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_37_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_37_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_37_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_37_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + * PCIE Reset signal) +*/ #undef IOU_SLCR_MIO_PIN_37_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_37_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_37_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_37_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_37_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_37_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_37_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_37_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_37_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[5]- (PMU GPI) 2= test_scan, Input, test_scan_in[37]- (Test S - an Port) = test_scan, Output, test_scan_out[37]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[5]- (PM + * U GPI) 2= test_scan, Input, test_scan_in[37]- (Test Scan Port) = test_sc + * an, Output, test_scan_out[37]- (Test Scan Port) 3= dpaux, Input, dp_hot_ + * plug_detect- (Dp Aux Hot Plug) +*/ #undef IOU_SLCR_MIO_PIN_37_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_37_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_37_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_37_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_37_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_37_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_37_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_37_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_37_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[11]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[11]- (GPIO bank 1) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, sp - 1_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) - 7= trace, Output, tracedq[15]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[11]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[11]- (GPIO bank 1) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4 + * = spi1, Input, spi1_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (T + * TC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) + * 7= trace, Output, tracedq[15]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_37_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_37_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_37_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_37_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_37_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_37_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_37_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_37_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_37_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_clk- (TX RGMII clock)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ + * clk- (TX RGMII clock) +*/ #undef IOU_SLCR_MIO_PIN_38_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_38_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_38_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_38_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_38_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_38_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_38_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_38_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_38_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_38_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_38_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_38_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_38_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_38_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_38_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_38_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_38_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_38_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= Not Used 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- + * (SDSDIO clock) 2= Not Used 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_38_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_38_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_38_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_38_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_38_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_38_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_38_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_38_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_38_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[12]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[12]- (GPIO bank 1) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Clo - k) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, trace_clk- - (Trace Port Clock)*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[12]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[12]- (GPIO bank 1) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTA + * G TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_s + * clk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, In + * put, ua0_rxd- (UART receiver serial input) 7= trace, Output, trace_clk- + * (Trace Port Clock) +*/ #undef IOU_SLCR_MIO_PIN_38_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_38_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_38_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_38_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_38_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_38_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_38_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_38_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_38_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[0]- (TX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd + * [0]- (TX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_39_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_39_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_39_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_39_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_39_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_39_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_39_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_39_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_39_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_39_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_39_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_39_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_39_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_39_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_39_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_39_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_39_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_39_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= sd1, Input, sd1_data_i - [4]- (8-bit Data bus) = sd1, Output, sdio1_data_out[4]- (8-bit Data bus) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD + * card detect from connector) 2= sd1, Input, sd1_data_in[4]- (8-bit Data b + * us) = sd1, Output, sdio1_data_out[4]- (8-bit Data bus) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_39_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_39_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_39_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_39_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_39_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_39_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_39_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_39_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_39_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[13]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[13]- (GPIO bank 1) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc0, Output, ttc0_wav - _out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, trace_ctl- (Trace Port - Control Signal)*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[13]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[13]- (GPIO bank 1) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJT + * AG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc0, + * Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (U + * ART transmitter serial output) 7= trace, Output, trace_ctl- (Trace Port + * Control Signal) +*/ #undef IOU_SLCR_MIO_PIN_39_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_39_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_39_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_39_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_39_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_39_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_39_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_39_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_39_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[1]- (TX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd + * [1]- (TX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_40_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_40_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_40_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_40_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_40_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_40_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_40_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_40_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_40_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_40_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_40_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_40_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_40_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_40_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_40_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_40_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_40_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_40_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Comman - Indicator) 2= sd1, Input, sd1_data_in[5]- (8-bit Data bus) = sd1, Output, sdio1_data_out[5]- (8-bit Data bus) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Com + * mand Indicator) = sd0, Output, sdio0_cmd_out- (Command Indicator) 2= sd1 + * , Input, sd1_data_in[5]- (8-bit Data bus) = sd1, Output, sdio1_data_out[ + * 5]- (8-bit Data bus) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_40_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_40_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_40_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_40_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_40_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_40_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_40_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_40_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_40_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[14]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[14]- (GPIO bank 1) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc3, Input, ttc3_clk - in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[0]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[14]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[14]- (GPIO bank 1) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJ + * TAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc3 + * , Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmi + * tter serial output) 7= trace, Output, tracedq[0]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_40_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_40_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_40_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_40_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_40_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_40_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_40_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_40_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_40_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[2]- (TX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd + * [2]- (TX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_41_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_41_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_41_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_41_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_41_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_41_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_41_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_41_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_41_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_41_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_41_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_41_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_41_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_41_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_41_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_41_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_41_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_41_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8 - bit Data bus) 2= sd1, Input, sd1_data_in[6]- (8-bit Data bus) = sd1, Output, sdio1_data_out[6]- (8-bit Data bus) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[6]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[6]- (8-bit Data bus) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_41_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_41_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_41_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_41_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_41_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_41_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_41_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_41_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_41_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[15]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[15]- (GPIO bank 1) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[ - ]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial in - ut) 7= trace, Output, tracedq[1]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[15]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[15]- (GPIO bank 1) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTA + * G TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Outpu + * t, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out + * - (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial inp + * ut) 7= trace, Output, tracedq[1]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_41_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_41_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_41_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_41_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_41_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_41_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_41_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_41_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_41_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[3]- (TX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd + * [3]- (TX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_42_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_42_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_42_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_42_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_42_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_42_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_42_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_42_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_42_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_42_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_42_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_42_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_42_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_42_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_42_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_42_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_42_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_42_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8 - bit Data bus) 2= sd1, Input, sd1_data_in[7]- (8-bit Data bus) = sd1, Output, sdio1_data_out[7]- (8-bit Data bus) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[7]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[7]- (8-bit Data bus) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_42_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_42_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_42_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_42_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_42_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_42_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_42_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_42_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_42_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_ - o- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outp - t, tracedq[2]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= sp + * i0, Output, spi0_so- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clo + * ck) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outpu + * t, tracedq[2]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_42_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_42_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_42_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_42_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_42_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_42_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_42_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_42_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_42_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ctl- (TX RGMII control)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ + * ctl- (TX RGMII control) +*/ #undef IOU_SLCR_MIO_PIN_43_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_43_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_43_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_43_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_43_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_43_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_43_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_43_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_43_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_43_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_43_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_43_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_43_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_43_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_43_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_43_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_43_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_43_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8 - bit Data bus) 2= sd1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8-bit Data bus) 2= s + * d1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_43_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_43_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_43_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_43_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_43_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_43_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_43_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_43_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_43_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, s - i0_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o - tput) 7= trace, Output, tracedq[3]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) + * 4= spi0, Input, spi0_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- ( + * TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial ou + * tput) 7= trace, Output, tracedq[3]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_43_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_43_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_43_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_43_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_43_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_43_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_43_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_43_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_43_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_clk- (RX RGMII clock)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_c + * lk- (RX RGMII clock) +*/ #undef IOU_SLCR_MIO_PIN_44_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_44_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_44_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_44_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_44_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_44_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_44_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_44_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_44_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_44_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_44_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_44_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_44_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_44_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_44_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_44_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_44_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_44_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8 - bit Data bus) 2= sd1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8-bit Data bus) 2= s + * d1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_44_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_44_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_44_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_44_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_44_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_44_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_44_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_44_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_44_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[18]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[18]- (GPIO bank 1) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, s - i1_sclk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7 - Not Used*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[18]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[18]- (GPIO bank 1) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4 + * = spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- + * (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= + * Not Used +*/ #undef IOU_SLCR_MIO_PIN_44_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_44_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_44_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_44_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_44_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_44_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_44_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_44_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_44_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[0]- (RX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[ + * 0]- (RX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_45_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_45_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_45_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_45_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_45_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_45_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_45_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_45_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_45_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_45_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_45_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_45_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_45_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_45_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_45_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_45_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_45_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_45_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8 - bit Data bus) 2= sd1, Input, sdio1_cd_n- (SD card detect from connector) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8-bit Data bus) 2= s + * d1, Input, sdio1_cd_n- (SD card detect from connector) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_45_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_45_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_45_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_45_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_45_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_45_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_45_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_45_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_45_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[19]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[19]- (GPIO bank 1) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= - ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[19]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[19]- (GPIO bank 1) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI M + * aster Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= u + * a1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used +*/ #undef IOU_SLCR_MIO_PIN_45_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_45_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_45_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_45_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_45_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_45_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_45_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_45_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_45_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[1]- (RX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[ + * 1]- (RX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_46_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_46_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_46_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_46_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_46_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_46_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_46_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_46_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_46_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_46_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_46_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_46_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_46_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_46_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_46_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_46_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_46_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_46_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8 - bit Data bus) 2= sd1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_out[0]- (8-bit Data bus) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[0]- (8-bit Data bus) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_46_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_46_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_46_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_46_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_46_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_46_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_46_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_46_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_46_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= tt - 0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Mast + * er Selects) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_ + * rxd- (UART receiver serial input) 7= Not Used +*/ #undef IOU_SLCR_MIO_PIN_46_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_46_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_46_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_46_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_46_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_46_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_46_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_46_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_46_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[2]- (RX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[ + * 2]- (RX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_47_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_47_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_47_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_47_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_47_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_47_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_47_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_47_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_47_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_47_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_47_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_47_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_47_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_47_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_47_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_47_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_47_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_47_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8 - bit Data bus) 2= sd1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_out[1]- (8-bit Data bus) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[1]- (8-bit Data bus) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_47_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_47_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_47_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_47_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_47_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_47_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_47_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_47_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_47_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi - , Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd - (UART transmitter serial output) 7= Not Used*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Maste + * r Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= tt + * c0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- + * (UART transmitter serial output) 7= Not Used +*/ #undef IOU_SLCR_MIO_PIN_47_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_47_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_47_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_47_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_47_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_47_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_47_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_47_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_47_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[3]- (RX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[ + * 3]- (RX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_48_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_48_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_48_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_48_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_48_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_48_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_48_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_48_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_48_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_48_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_48_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_48_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_48_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_48_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_48_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_48_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_48_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_48_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8 - bit Data bus) 2= sd1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_out[2]- (8-bit Data bus) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[2]- (8-bit Data bus) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_48_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_48_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_48_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_48_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_48_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_48_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_48_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_48_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_48_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[22]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[22]- (GPIO bank 1) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1 - so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not U - ed*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[22]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[22]- (GPIO bank 1) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= s + * pi1, Output, spi1_so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Cl + * ock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Us + * ed +*/ #undef IOU_SLCR_MIO_PIN_48_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_48_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_48_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_48_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_48_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_48_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_48_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_48_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_48_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_ctl- (RX RGMII control )*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_c + * tl- (RX RGMII control ) +*/ #undef IOU_SLCR_MIO_PIN_49_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_49_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_49_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_49_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_49_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_49_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_49_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_49_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_49_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_49_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_49_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_49_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_49_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_49_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_49_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_49_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_49_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_49_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= sd1, Input, sd1_data_in[3]- (8 - bit Data bus) = sd1, Output, sdio1_data_out[3]- (8-bit Data bus) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- + * (SD card bus power) 2= sd1, Input, sd1_data_in[3]- (8-bit Data bus) = sd + * 1, Output, sdio1_data_out[3]- (8-bit Data bus) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_49_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_49_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_49_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_49_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_49_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_49_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_49_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_49_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_49_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[23]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[23]- (GPIO bank 1) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, sp - 1_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) - 7= Not Used*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[23]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[23]- (GPIO bank 1) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4 + * = spi1, Input, spi1_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (T + * TC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) + * 7= Not Used +*/ #undef IOU_SLCR_MIO_PIN_49_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_49_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_49_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_49_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_49_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_49_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_49_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_49_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_49_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- (TSU clock)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- + * (TSU clock) +*/ #undef IOU_SLCR_MIO_PIN_50_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_50_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_50_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_50_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_50_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_50_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_50_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_50_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_50_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_50_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_50_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_50_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_50_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_50_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_50_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_50_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_50_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_50_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= sd1, Input, sd1_c - d_in- (Command Indicator) = sd1, Output, sdio1_cmd_out- (Command Indicator) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD ca + * rd write protect from connector) 2= sd1, Input, sd1_cmd_in- (Command Ind + * icator) = sd1, Output, sdio1_cmd_out- (Command Indicator) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_50_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_50_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_50_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_50_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_50_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_50_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_50_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_50_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_50_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[24]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[24]- (GPIO bank 1) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= ttc2, Input, ttc2 - clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[24]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[24]- (GPIO bank 1) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= + * ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART rece + * iver serial input) 7= Not Used +*/ #undef IOU_SLCR_MIO_PIN_50_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_50_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_50_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_50_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_50_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_50_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_50_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_50_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_50_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- (TSU clock)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- + * (TSU clock) +*/ #undef IOU_SLCR_MIO_PIN_51_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_51_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_51_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_51_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_51_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_51_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_51_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_51_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_51_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_51_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_51_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_51_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_51_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_51_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_51_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_51_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_51_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_51_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Output, sdio1_clk_out- (SDSDIO clock) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Output, sdi + * o1_clk_out- (SDSDIO clock) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_51_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_51_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_51_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_51_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_51_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_51_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_51_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_51_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_51_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[25]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[25]- (GPIO bank 1) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= mdio1, Input, gem1_mdio_in- (MDIO Data) 4= mdio1, Outp - t, gem1_mdio_out- (MDIO Data) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter - serial output) 7= Not Used*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[25]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[25]- (GPIO bank 1) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= mdio1, Input, gem1_mdio_in- (MDIO Dat + * a) 4= mdio1, Output, gem1_mdio_out- (MDIO Data) 5= ttc2, Output, ttc2_wa + * ve_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter + * serial output) 7= Not Used +*/ #undef IOU_SLCR_MIO_PIN_51_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_51_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_51_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_51_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_51_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_51_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_51_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_51_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_51_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_clk- (TX RGMII clock)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_ + * clk- (TX RGMII clock) +*/ #undef IOU_SLCR_MIO_PIN_52_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_52_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_52_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_52_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_52_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_52_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_52_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_52_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_52_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_clk_in- (ULPI Clock)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_clk_i + * n- (ULPI Clock) +*/ #undef IOU_SLCR_MIO_PIN_52_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_52_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_52_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_52_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_52_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_52_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_52_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_52_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_52_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used +*/ #undef IOU_SLCR_MIO_PIN_52_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_52_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_52_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_52_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_52_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_52_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_52_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_52_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_52_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[0]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[0]- (GPIO bank 2) 1= can - , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa - ) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Cloc - ) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_ - lk- (Trace Port Clock)*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[0]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[0]- (GPIO bank 2) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG + * TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sc + * lk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Out + * put, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_c + * lk- (Trace Port Clock) +*/ #undef IOU_SLCR_MIO_PIN_52_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_52_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_52_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_52_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_52_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_52_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_52_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_52_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_52_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[0]- (TX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd + * [0]- (TX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_53_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_53_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_53_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_53_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_53_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_53_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_53_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_53_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_53_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_dir- (Data bus direction control)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_dir- + * (Data bus direction control) +*/ #undef IOU_SLCR_MIO_PIN_53_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_53_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_53_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_53_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_53_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_53_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_53_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_53_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_53_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used +*/ #undef IOU_SLCR_MIO_PIN_53_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_53_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_53_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_53_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_53_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_53_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_53_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_53_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_53_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[1]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[1]- (GPIO bank 2) 1= can - , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal - 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_o - t- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control - Signal)*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[1]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[1]- (GPIO bank 2) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG + * TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Ou + * tput, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART + * receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control + * Signal) +*/ #undef IOU_SLCR_MIO_PIN_53_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_53_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_53_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_53_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_53_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_53_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_53_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_53_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_53_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[1]- (TX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd + * [1]- (TX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_54_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_54_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_54_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_54_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_54_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_54_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_54_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_54_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_54_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[2]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_ - ata[2]- (ULPI data bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[2]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[2]- (ULPI data + * bus) +*/ #undef IOU_SLCR_MIO_PIN_54_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_54_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_54_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_54_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_54_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_54_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_54_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_54_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_54_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used +*/ #undef IOU_SLCR_MIO_PIN_54_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_54_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_54_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_54_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_54_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_54_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_54_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_54_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_54_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[2]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[2]- (GPIO bank 2) 1= can - , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal - 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, Input, ttc0_clk_in - (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[0]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[2]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[2]- (GPIO bank 2) 1= can0, Input, can0_phy_ + * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + * , Output, i2c0_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTAG + * TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, I + * nput, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver se + * rial input) 7= trace, Output, tracedq[0]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_54_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_54_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_54_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_54_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_54_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_54_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_54_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_54_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_54_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[2]- (TX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd + * [2]- (TX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_55_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_55_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_55_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_55_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_55_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_55_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_55_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_55_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_55_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_nxt- (Data flow control signal from the PHY)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_nxt- + * (Data flow control signal from the PHY) +*/ #undef IOU_SLCR_MIO_PIN_55_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_55_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_55_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_55_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_55_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_55_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_55_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_55_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_55_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used +*/ #undef IOU_SLCR_MIO_PIN_55_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_55_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_55_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_55_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_55_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_55_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_55_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_55_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_55_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[3]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[3]- (GPIO bank 2) 1= can - , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa - ) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0 - - (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial - output) 7= trace, Output, tracedq[1]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[3]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[3]- (GPIO bank 2) 1= can0, Output, can0_phy + * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + * 0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG + * TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output + * , spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- + * (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial + * output) 7= trace, Output, tracedq[1]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_55_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_55_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_55_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_55_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_55_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_55_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_55_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_55_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_55_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[3]- (TX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd + * [3]- (TX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_56_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_56_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_56_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_56_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_56_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_56_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_56_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_56_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_56_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[0]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_ - ata[0]- (ULPI data bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[0]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[0]- (ULPI data + * bus) +*/ #undef IOU_SLCR_MIO_PIN_56_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_56_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_56_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_56_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_56_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_56_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_56_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_56_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_56_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used +*/ #undef IOU_SLCR_MIO_PIN_56_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_56_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_56_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_56_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_56_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_56_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_56_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_56_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_56_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[4]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[4]- (GPIO bank 2) 1= can - , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa - ) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_s - - (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, - utput, tracedq[2]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[4]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[4]- (GPIO bank 2) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Wa + * tch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi + * 0, Output, spi0_so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Cloc + * k) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, O + * utput, tracedq[2]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_56_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_56_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_56_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_56_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_56_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_56_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_56_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_56_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_56_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_ctl- (TX RGMII control)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_ + * ctl- (TX RGMII control) +*/ #undef IOU_SLCR_MIO_PIN_57_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_57_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_57_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_57_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_57_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_57_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_57_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_57_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_57_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[1]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_ - ata[1]- (ULPI data bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[1]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[1]- (ULPI data + * bus) +*/ #undef IOU_SLCR_MIO_PIN_57_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_57_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_57_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_57_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_57_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_57_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_57_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_57_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_57_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used +*/ #undef IOU_SLCR_MIO_PIN_57_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_57_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_57_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_57_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_57_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_57_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_57_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_57_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_57_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[5]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[5]- (GPIO bank 2) 1= can - , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal - 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi0 - si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7 - trace, Output, tracedq[3]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[5]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[5]- (GPIO bank 2) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (W + * atch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= + * spi0, Input, spi0_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC + * Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= + * trace, Output, tracedq[3]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_57_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_57_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_57_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_57_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_57_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_57_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_57_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_57_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_57_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_clk- (RX RGMII clock)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_c + * lk- (RX RGMII clock) +*/ #undef IOU_SLCR_MIO_PIN_58_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_58_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_58_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_58_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_58_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_58_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_58_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_58_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_58_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Output, usb0_ulpi_stp- (Asserted to end or interrupt transfers)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Output, usb0_ulpi_stp- + * (Asserted to end or interrupt transfers) +*/ #undef IOU_SLCR_MIO_PIN_58_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_58_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_58_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_58_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_58_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_58_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_58_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_58_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_58_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used +*/ #undef IOU_SLCR_MIO_PIN_58_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_58_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_58_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_58_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_58_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_58_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_58_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_58_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_58_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[6]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[6]- (GPIO bank 2) 1= can - , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal - 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1_sclk_out- (SPI Clock - 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- - Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[6]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[6]- (GPIO bank 2) 1= can0, Input, can0_phy_ + * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + * , Output, i2c0_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG + * TCK) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1_scl + * k_out- (SPI Clock) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Inpu + * t, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- ( + * Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_58_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_58_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_58_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_58_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_58_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_58_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_58_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_58_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_58_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[0]- (RX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[ + * 0]- (RX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_59_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_59_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_59_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_59_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_59_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_59_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_59_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_59_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_59_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[3]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_ - ata[3]- (ULPI data bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[3]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[3]- (ULPI data + * bus) +*/ #undef IOU_SLCR_MIO_PIN_59_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_59_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_59_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_59_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_59_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_59_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_59_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_59_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_59_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used +*/ #undef IOU_SLCR_MIO_PIN_59_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_59_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_59_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_59_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_59_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_59_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_59_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_59_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_59_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[7]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[7]- (GPIO bank 2) 1= can - , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa - ) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_ - ut- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port - atabus)*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[7]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[7]- (GPIO bank 2) 1= can0, Output, can0_phy + * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + * 0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG + * TDI) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= ttc2, O + * utput, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UAR + * T transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port D + * atabus) +*/ #undef IOU_SLCR_MIO_PIN_59_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_59_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_59_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_59_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_59_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_59_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_59_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_59_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_59_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[1]- (RX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[ + * 1]- (RX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_60_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_60_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_60_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_60_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_60_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_60_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_60_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_60_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_60_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[4]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_ - ata[4]- (ULPI data bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[4]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[4]- (ULPI data + * bus) +*/ #undef IOU_SLCR_MIO_PIN_60_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_60_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_60_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_60_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_60_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_60_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_60_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_60_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_60_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used +*/ #undef IOU_SLCR_MIO_PIN_60_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_60_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_60_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_60_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_60_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_60_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_60_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_60_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_60_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[8]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[8]- (GPIO bank 2) 1= can - , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa - ) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc1, Input, ttc1_clk_i - - (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[8]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[8]- (GPIO bank 2) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTA + * G TDO) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc1, + * Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitt + * er serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_60_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_60_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_60_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_60_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_60_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_60_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_60_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_60_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_60_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[2]- (RX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[ + * 2]- (RX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_61_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_61_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_61_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_61_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_61_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_61_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_61_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_61_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_61_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[5]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_ - ata[5]- (ULPI data bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[5]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[5]- (ULPI data + * bus) +*/ #undef IOU_SLCR_MIO_PIN_61_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_61_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_61_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_61_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_61_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_61_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_61_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_61_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_61_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used +*/ #undef IOU_SLCR_MIO_PIN_61_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_61_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_61_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_61_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_61_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_61_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_61_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_61_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_61_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[9]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[9]- (GPIO bank 2) 1= can - , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal - 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, Output, spi1_n_ss_out[0] - (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial inpu - ) 7= trace, Output, tracedq[7]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[9]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[9]- (GPIO bank 2) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG + * TMS) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, Output, + * spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- + * (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input + * ) 7= trace, Output, tracedq[7]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_61_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_61_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_61_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_61_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_61_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_61_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_61_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_61_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_61_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[3]- (RX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[ + * 3]- (RX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_62_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_62_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_62_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_62_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_62_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_62_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_62_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_62_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_62_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[6]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_ - ata[6]- (ULPI data bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[6]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[6]- (ULPI data + * bus) +*/ #undef IOU_SLCR_MIO_PIN_62_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_62_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_62_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_62_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_62_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_62_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_62_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_62_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_62_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used +*/ #undef IOU_SLCR_MIO_PIN_62_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_62_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_62_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_62_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_62_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_62_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_62_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_62_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_62_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[10]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[10]- (GPIO bank 2) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_ - o- (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outp - t, tracedq[8]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[10]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[10]- (GPIO bank 2) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= sp + * i1, Output, spi1_so- (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clo + * ck) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outpu + * t, tracedq[8]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_62_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_62_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_62_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_62_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_62_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_62_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_62_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_62_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_62_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_ctl- (RX RGMII control )*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_c + * tl- (RX RGMII control ) +*/ #undef IOU_SLCR_MIO_PIN_63_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_63_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_63_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_63_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_63_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_63_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_63_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_63_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_63_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[7]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_ - ata[7]- (ULPI data bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[7]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[7]- (ULPI data + * bus) +*/ #undef IOU_SLCR_MIO_PIN_63_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_63_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_63_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_63_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_63_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_63_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_63_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_63_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_63_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used +*/ #undef IOU_SLCR_MIO_PIN_63_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_63_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_63_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_63_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_63_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_63_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_63_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_63_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_63_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[11]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[11]- (GPIO bank 2) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s - i1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o - tput) 7= trace, Output, tracedq[9]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[11]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[11]- (GPIO bank 2) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) + * 4= spi1, Input, spi1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- ( + * TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial ou + * tput) 7= trace, Output, tracedq[9]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_63_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_63_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_63_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_63_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_63_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_63_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_63_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_63_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_63_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_clk- (TX RGMII clock)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_ + * clk- (TX RGMII clock) +*/ #undef IOU_SLCR_MIO_PIN_64_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_64_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_64_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_64_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_64_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_64_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_64_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_64_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_64_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_clk_in- (ULPI Clock)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_clk_i + * n- (ULPI Clock) +*/ #undef IOU_SLCR_MIO_PIN_64_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_64_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_64_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_64_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_64_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_64_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_64_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_64_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_64_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= Not Used 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- + * (SDSDIO clock) 2= Not Used 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_64_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_64_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_64_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_64_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_64_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_64_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_64_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_64_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_64_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[12]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[12]- (GPIO bank 2) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, s - i0_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7 - trace, Output, tracedq[10]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[12]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[12]- (GPIO bank 2) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4 + * = spi0, Output, spi0_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- + * (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= + * trace, Output, tracedq[10]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_64_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_64_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_64_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_64_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_64_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_64_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_64_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_64_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_64_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[0]- (TX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd + * [0]- (TX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_65_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_65_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_65_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_65_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_65_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_65_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_65_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_65_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_65_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_dir- (Data bus direction control)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_dir- + * (Data bus direction control) +*/ #undef IOU_SLCR_MIO_PIN_65_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_65_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_65_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_65_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_65_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_65_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_65_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_65_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_65_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= Not Used 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD + * card detect from connector) 2= Not Used 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_65_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_65_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_65_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_65_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_65_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_65_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_65_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_65_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_65_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[13]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[13]- (GPIO bank 2) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= - ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trac - dq[11]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[13]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[13]- (GPIO bank 2) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi0, Output, spi0_n_ss_out[2]- (SPI M + * aster Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= u + * a1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trace + * dq[11]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_65_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_65_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_65_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_65_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_65_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_65_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_65_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_65_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_65_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[1]- (TX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd + * [1]- (TX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_66_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_66_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_66_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_66_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_66_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_66_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_66_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_66_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_66_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[2]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_ - ata[2]- (ULPI data bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[2]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[2]- (ULPI data + * bus) +*/ #undef IOU_SLCR_MIO_PIN_66_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_66_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_66_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_66_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_66_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_66_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_66_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_66_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_66_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Comman - Indicator) 2= Not Used 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Com + * mand Indicator) = sd0, Output, sdio0_cmd_out- (Command Indicator) 2= Not + * Used 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_66_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_66_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_66_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_66_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_66_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_66_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_66_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_66_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_66_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[14]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[14]- (GPIO bank 2) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= tt - 2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace - Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[14]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[14]- (GPIO bank 2) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Mast + * er Selects) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_ + * rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace + * Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_66_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_66_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_66_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_66_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_66_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_66_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_66_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_66_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_66_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[2]- (TX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd + * [2]- (TX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_67_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_67_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_67_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_67_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_67_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_67_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_67_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_67_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_67_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_nxt- (Data flow control signal from the PHY)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_nxt- + * (Data flow control signal from the PHY) +*/ #undef IOU_SLCR_MIO_PIN_67_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_67_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_67_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_67_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_67_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_67_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_67_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_67_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_67_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8 - bit Data bus) 2= Not Used 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8-bit Data bus) 2= N + * ot Used 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_67_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_67_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_67_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_67_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_67_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_67_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_67_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_67_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_67_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[15]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[15]- (GPIO bank 2) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi - , Output, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd - (UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[15]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[15]- (GPIO bank 2) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi0, Input, spi0_n_ss_in- (SPI Maste + * r Selects) 4= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 5= tt + * c2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- + * (UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace + * Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_67_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_67_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_67_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_67_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_67_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_67_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_67_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_67_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_67_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[3]- (TX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd + * [3]- (TX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_68_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_68_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_68_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_68_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_68_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_68_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_68_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_68_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_68_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[0]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_ - ata[0]- (ULPI data bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[0]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[0]- (ULPI data + * bus) +*/ #undef IOU_SLCR_MIO_PIN_68_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_68_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_68_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_68_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_68_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_68_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_68_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_68_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_68_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8 - bit Data bus) 2= Not Used 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8-bit Data bus) 2= N + * ot Used 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_68_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_68_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_68_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_68_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_68_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_68_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_68_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_68_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_68_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[16]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[16]- (GPIO bank 2) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0 - so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace - Output, tracedq[14]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[16]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[16]- (GPIO bank 2) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= s + * pi0, Output, spi0_so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Cl + * ock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, + * Output, tracedq[14]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_68_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_68_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_68_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_68_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_68_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_68_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_68_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_68_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_68_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_ctl- (TX RGMII control)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_ + * ctl- (TX RGMII control) +*/ #undef IOU_SLCR_MIO_PIN_69_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_69_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_69_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_69_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_69_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_69_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_69_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_69_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_69_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[1]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_ - ata[1]- (ULPI data bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[1]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[1]- (ULPI data + * bus) +*/ #undef IOU_SLCR_MIO_PIN_69_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_69_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_69_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_69_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_69_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_69_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_69_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_69_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_69_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8 - bit Data bus) 2= sd1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8-bit Data bus) 2= s + * d1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_69_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_69_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_69_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_69_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_69_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_69_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_69_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_69_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_69_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[17]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[17]- (GPIO bank 2) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, sp - 0_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) - 7= trace, Output, tracedq[15]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[17]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[17]- (GPIO bank 2) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4 + * = spi0, Input, spi0_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (T + * TC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) + * 7= trace, Output, tracedq[15]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_69_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_69_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_69_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_69_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_69_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_69_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_69_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_69_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_69_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_clk- (RX RGMII clock)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_c + * lk- (RX RGMII clock) +*/ #undef IOU_SLCR_MIO_PIN_70_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_70_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_70_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_70_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_70_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_70_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_70_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_70_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_70_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Output, usb1_ulpi_stp- (Asserted to end or interrupt transfers)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Output, usb1_ulpi_stp- + * (Asserted to end or interrupt transfers) +*/ #undef IOU_SLCR_MIO_PIN_70_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_70_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_70_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_70_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_70_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_70_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_70_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_70_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_70_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8 - bit Data bus) 2= sd1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8-bit Data bus) 2= s + * d1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_70_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_70_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_70_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_70_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_70_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_70_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_70_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_70_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_70_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[18]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[18]- (GPIO bank 2) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, sp - 1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not - sed*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[18]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[18]- (GPIO bank 2) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= + * spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- ( + * TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not U + * sed +*/ #undef IOU_SLCR_MIO_PIN_70_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_70_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_70_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_70_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_70_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_70_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_70_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_70_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_70_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[0]- (RX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[ + * 0]- (RX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_71_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_71_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_71_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_71_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_71_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_71_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_71_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_71_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_71_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[3]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_ - ata[3]- (ULPI data bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[3]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[3]- (ULPI data + * bus) +*/ #undef IOU_SLCR_MIO_PIN_71_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_71_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_71_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_71_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_71_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_71_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_71_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_71_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_71_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8 - bit Data bus) 2= sd1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_out[0]- (8-bit Data bus) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[0]- (8-bit Data bus) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_71_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_71_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_71_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_71_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_71_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_71_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_71_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_71_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_71_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[19]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[19]- (GPIO bank 2) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5 - ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[19]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[19]- (GPIO bank 2) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI + * Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= + * ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used +*/ #undef IOU_SLCR_MIO_PIN_71_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_71_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_71_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_71_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_71_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_71_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_71_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_71_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_71_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[1]- (RX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[ + * 1]- (RX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_72_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_72_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_72_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_72_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_72_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_72_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_72_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_72_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_72_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[4]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_ - ata[4]- (ULPI data bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[4]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[4]- (ULPI data + * bus) +*/ #undef IOU_SLCR_MIO_PIN_72_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_72_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_72_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_72_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_72_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_72_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_72_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_72_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_72_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8 - bit Data bus) 2= sd1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_out[1]- (8-bit Data bus) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[1]- (8-bit Data bus) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_72_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_72_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_72_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_72_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_72_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_72_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_72_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_72_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_72_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[20]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[20]- (GPIO bank 2) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= N - t Used 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Used*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[20]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[20]- (GPIO bank 2) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Mas + * ter Selects) 5= Not Used 6= ua1, Output, ua1_txd- (UART transmitter seri + * al output) 7= Not Used +*/ #undef IOU_SLCR_MIO_PIN_72_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_72_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_72_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_72_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_72_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_72_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_72_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_72_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_72_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[2]- (RX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[ + * 2]- (RX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_73_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_73_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_73_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_73_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_73_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_73_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_73_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_73_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_73_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_ - ata[5]- (ULPI data bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[5]- (ULPI data + * bus) +*/ #undef IOU_SLCR_MIO_PIN_73_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_73_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_73_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_73_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_73_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_73_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_73_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_73_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_73_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8 - bit Data bus) 2= sd1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_out[2]- (8-bit Data bus) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[2]- (8-bit Data bus) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_73_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_73_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_73_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_73_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_73_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_73_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_73_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_73_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_73_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[21]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[21]- (GPIO bank 2) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1 - Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= Not Used 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[21]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[21]- (GPIO bank 2) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master + * Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= Not + * Used 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used +*/ #undef IOU_SLCR_MIO_PIN_73_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_73_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_73_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_73_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_73_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_73_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_73_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_73_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_73_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[3]- (RX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[ + * 3]- (RX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_74_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_74_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_74_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_74_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_74_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_74_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_74_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_74_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_74_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[6]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_ - ata[6]- (ULPI data bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[6]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[6]- (ULPI data + * bus) +*/ #undef IOU_SLCR_MIO_PIN_74_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_74_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_74_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_74_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_74_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_74_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_74_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_74_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_74_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8 - bit Data bus) 2= sd1, Input, sd1_data_in[3]- (8-bit Data bus) = sd1, Output, sdio1_data_out[3]- (8-bit Data bus) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[3]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[3]- (8-bit Data bus) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_74_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_74_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_74_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_74_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_74_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_74_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_74_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_74_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_74_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[22]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[22]- (GPIO bank 2) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_ - o- (MISO signal) 5= Not Used 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[22]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[22]- (GPIO bank 2) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= sp + * i1, Output, spi1_so- (MISO signal) 5= Not Used 6= ua0, Input, ua0_rxd- ( + * UART receiver serial input) 7= Not Used +*/ #undef IOU_SLCR_MIO_PIN_74_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_74_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_74_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_74_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_74_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_74_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_74_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_74_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_74_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_ctl- (RX RGMII control )*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_c + * tl- (RX RGMII control ) +*/ #undef IOU_SLCR_MIO_PIN_75_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_75_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_75_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_75_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_75_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_75_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_75_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_75_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_75_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[7]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_ - ata[7]- (ULPI data bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[7]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[7]- (ULPI data + * bus) +*/ #undef IOU_SLCR_MIO_PIN_75_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_75_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_75_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_75_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_75_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_75_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_75_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_75_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_75_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= sd1, Input, sd1_cmd_in- (Comma - d Indicator) = sd1, Output, sdio1_cmd_out- (Command Indicator) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- + * (SD card bus power) 2= sd1, Input, sd1_cmd_in- (Command Indicator) = sd1 + * , Output, sdio1_cmd_out- (Command Indicator) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_75_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_75_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_75_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_75_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_75_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_75_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_75_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_75_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_75_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[23]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[23]- (GPIO bank 2) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s - i1_si- (MOSI signal) 5= Not Used 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[23]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[23]- (GPIO bank 2) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) + * 4= spi1, Input, spi1_si- (MOSI signal) 5= Not Used 6= ua0, Output, ua0_t + * xd- (UART transmitter serial output) 7= Not Used +*/ #undef IOU_SLCR_MIO_PIN_75_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_75_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_75_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_75_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_75_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_75_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_75_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_75_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_75_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_76_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_76_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_76_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_76_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_76_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_76_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_76_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_76_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_76_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_76_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_76_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_76_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_76_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_76_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_76_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_76_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_76_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_76_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= sd1, Output, sdio - _clk_out- (SDSDIO clock) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD ca + * rd write protect from connector) 2= sd1, Output, sdio1_clk_out- (SDSDIO + * clock) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_76_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_76_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_76_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_76_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_76_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_76_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_76_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_76_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_76_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[24]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[24]- (GPIO bank 2) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= mdio0, Output, gem0_mdc- (MDIO Clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= mdio2, Output, gem2_mdc- (MDIO Clock - 6= mdio3, Output, gem3_mdc- (MDIO Clock) 7= Not Used*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[24]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[24]- (GPIO bank 2) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= mdio0, Output, gem0_mdc- (MDI + * O Clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= mdio2, Output, gem2 + * _mdc- (MDIO Clock) 6= mdio3, Output, gem3_mdc- (MDIO Clock) 7= Not Used +*/ #undef IOU_SLCR_MIO_PIN_76_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_76_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_76_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_76_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_76_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_76_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_76_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_76_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_76_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_77_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_77_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_77_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_77_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_77_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_77_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_77_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_77_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_77_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_77_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_77_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_77_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_77_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_77_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_77_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_77_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_77_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_77_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Input, sdio1_cd_n- (SD card detect from connector) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Input, sdio + * 1_cd_n- (SD card detect from connector) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_77_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_77_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_77_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_77_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_77_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_77_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_77_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_77_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_77_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[25]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[25]- (GPIO bank 2) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= mdio0, Input, gem0_mdio_in- (MDIO Data) 3= mdio0, Output, gem0_mdio_out- (MDIO Data) 4= mdio1, Input, gem1_mdio_in- (MD - O Data) 4= mdio1, Output, gem1_mdio_out- (MDIO Data) 5= mdio2, Input, gem2_mdio_in- (MDIO Data) 5= mdio2, Output, gem2_mdio_o - t- (MDIO Data) 6= mdio3, Input, gem3_mdio_in- (MDIO Data) 6= mdio3, Output, gem3_mdio_out- (MDIO Data) 7= Not Used*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[25]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[25]- (GPIO bank 2) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= mdio0, Input, gem0_mdio_in- (M + * DIO Data) 3= mdio0, Output, gem0_mdio_out- (MDIO Data) 4= mdio1, Input, + * gem1_mdio_in- (MDIO Data) 4= mdio1, Output, gem1_mdio_out- (MDIO Data) 5 + * = mdio2, Input, gem2_mdio_in- (MDIO Data) 5= mdio2, Output, gem2_mdio_ou + * t- (MDIO Data) 6= mdio3, Input, gem3_mdio_in- (MDIO Data) 6= mdio3, Outp + * ut, gem3_mdio_out- (MDIO Data) 7= Not Used +*/ #undef IOU_SLCR_MIO_PIN_77_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_77_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_77_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_77_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_77_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_77_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_77_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_77_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_77_L3_SEL_MASK 0x000000E0U -/*Master Tri-state Enable for pin 0, active high*/ +/* +* Master Tri-state Enable for pin 0, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_SHIFT 0 -#define IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_MASK 0x00000001U +#define IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_SHIFT 0 +#define IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_MASK 0x00000001U -/*Master Tri-state Enable for pin 1, active high*/ +/* +* Master Tri-state Enable for pin 1, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_SHIFT 1 -#define IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_MASK 0x00000002U +#define IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_SHIFT 1 +#define IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_MASK 0x00000002U -/*Master Tri-state Enable for pin 2, active high*/ +/* +* Master Tri-state Enable for pin 2, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_SHIFT 2 -#define IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_MASK 0x00000004U +#define IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_SHIFT 2 +#define IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_MASK 0x00000004U -/*Master Tri-state Enable for pin 3, active high*/ +/* +* Master Tri-state Enable for pin 3, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_SHIFT 3 -#define IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_MASK 0x00000008U +#define IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_SHIFT 3 +#define IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_MASK 0x00000008U -/*Master Tri-state Enable for pin 4, active high*/ +/* +* Master Tri-state Enable for pin 4, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_SHIFT 4 -#define IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_MASK 0x00000010U +#define IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_SHIFT 4 +#define IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_MASK 0x00000010U -/*Master Tri-state Enable for pin 5, active high*/ +/* +* Master Tri-state Enable for pin 5, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_SHIFT 5 -#define IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_MASK 0x00000020U +#define IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_SHIFT 5 +#define IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_MASK 0x00000020U -/*Master Tri-state Enable for pin 6, active high*/ +/* +* Master Tri-state Enable for pin 6, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_SHIFT 6 -#define IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_MASK 0x00000040U +#define IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_SHIFT 6 +#define IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_MASK 0x00000040U -/*Master Tri-state Enable for pin 7, active high*/ +/* +* Master Tri-state Enable for pin 7, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_SHIFT 7 -#define IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_MASK 0x00000080U +#define IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_SHIFT 7 +#define IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_MASK 0x00000080U -/*Master Tri-state Enable for pin 8, active high*/ +/* +* Master Tri-state Enable for pin 8, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_SHIFT 8 -#define IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_MASK 0x00000100U +#define IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_SHIFT 8 +#define IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_MASK 0x00000100U -/*Master Tri-state Enable for pin 9, active high*/ +/* +* Master Tri-state Enable for pin 9, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_SHIFT 9 -#define IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_MASK 0x00000200U +#define IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_SHIFT 9 +#define IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_MASK 0x00000200U -/*Master Tri-state Enable for pin 10, active high*/ +/* +* Master Tri-state Enable for pin 10, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_SHIFT 10 -#define IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_MASK 0x00000400U +#define IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_SHIFT 10 +#define IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_MASK 0x00000400U -/*Master Tri-state Enable for pin 11, active high*/ +/* +* Master Tri-state Enable for pin 11, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_SHIFT 11 -#define IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_MASK 0x00000800U +#define IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_SHIFT 11 +#define IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_MASK 0x00000800U -/*Master Tri-state Enable for pin 12, active high*/ +/* +* Master Tri-state Enable for pin 12, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_SHIFT 12 -#define IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_MASK 0x00001000U +#define IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_SHIFT 12 +#define IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_MASK 0x00001000U -/*Master Tri-state Enable for pin 13, active high*/ +/* +* Master Tri-state Enable for pin 13, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_SHIFT 13 -#define IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_MASK 0x00002000U +#define IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_SHIFT 13 +#define IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_MASK 0x00002000U -/*Master Tri-state Enable for pin 14, active high*/ +/* +* Master Tri-state Enable for pin 14, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_SHIFT 14 -#define IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_MASK 0x00004000U +#define IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_SHIFT 14 +#define IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_MASK 0x00004000U -/*Master Tri-state Enable for pin 15, active high*/ +/* +* Master Tri-state Enable for pin 15, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_SHIFT 15 -#define IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_MASK 0x00008000U +#define IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_SHIFT 15 +#define IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_MASK 0x00008000U -/*Master Tri-state Enable for pin 16, active high*/ +/* +* Master Tri-state Enable for pin 16, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_SHIFT 16 -#define IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_MASK 0x00010000U +#define IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_SHIFT 16 +#define IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_MASK 0x00010000U -/*Master Tri-state Enable for pin 17, active high*/ +/* +* Master Tri-state Enable for pin 17, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_SHIFT 17 -#define IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_MASK 0x00020000U +#define IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_SHIFT 17 +#define IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_MASK 0x00020000U -/*Master Tri-state Enable for pin 18, active high*/ +/* +* Master Tri-state Enable for pin 18, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_SHIFT 18 -#define IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_MASK 0x00040000U +#define IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_SHIFT 18 +#define IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_MASK 0x00040000U -/*Master Tri-state Enable for pin 19, active high*/ +/* +* Master Tri-state Enable for pin 19, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_SHIFT 19 -#define IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_MASK 0x00080000U +#define IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_SHIFT 19 +#define IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_MASK 0x00080000U -/*Master Tri-state Enable for pin 20, active high*/ +/* +* Master Tri-state Enable for pin 20, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_SHIFT 20 -#define IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_MASK 0x00100000U +#define IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_SHIFT 20 +#define IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_MASK 0x00100000U -/*Master Tri-state Enable for pin 21, active high*/ +/* +* Master Tri-state Enable for pin 21, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_SHIFT 21 -#define IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_MASK 0x00200000U +#define IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_SHIFT 21 +#define IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_MASK 0x00200000U -/*Master Tri-state Enable for pin 22, active high*/ +/* +* Master Tri-state Enable for pin 22, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_SHIFT 22 -#define IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_MASK 0x00400000U +#define IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_SHIFT 22 +#define IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_MASK 0x00400000U -/*Master Tri-state Enable for pin 23, active high*/ +/* +* Master Tri-state Enable for pin 23, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_SHIFT 23 -#define IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_MASK 0x00800000U +#define IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_SHIFT 23 +#define IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_MASK 0x00800000U -/*Master Tri-state Enable for pin 24, active high*/ +/* +* Master Tri-state Enable for pin 24, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_SHIFT 24 -#define IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_MASK 0x01000000U +#define IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_SHIFT 24 +#define IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_MASK 0x01000000U -/*Master Tri-state Enable for pin 25, active high*/ +/* +* Master Tri-state Enable for pin 25, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_SHIFT 25 -#define IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_MASK 0x02000000U +#define IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_SHIFT 25 +#define IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_MASK 0x02000000U -/*Master Tri-state Enable for pin 26, active high*/ +/* +* Master Tri-state Enable for pin 26, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_SHIFT 26 -#define IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_MASK 0x04000000U +#define IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_SHIFT 26 +#define IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_MASK 0x04000000U -/*Master Tri-state Enable for pin 27, active high*/ +/* +* Master Tri-state Enable for pin 27, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_SHIFT 27 -#define IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_MASK 0x08000000U +#define IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_SHIFT 27 +#define IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_MASK 0x08000000U -/*Master Tri-state Enable for pin 28, active high*/ +/* +* Master Tri-state Enable for pin 28, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_SHIFT 28 -#define IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_MASK 0x10000000U +#define IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_SHIFT 28 +#define IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_MASK 0x10000000U -/*Master Tri-state Enable for pin 29, active high*/ +/* +* Master Tri-state Enable for pin 29, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_SHIFT 29 -#define IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_MASK 0x20000000U +#define IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_SHIFT 29 +#define IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_MASK 0x20000000U -/*Master Tri-state Enable for pin 30, active high*/ +/* +* Master Tri-state Enable for pin 30, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_SHIFT 30 -#define IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_MASK 0x40000000U +#define IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_SHIFT 30 +#define IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_MASK 0x40000000U -/*Master Tri-state Enable for pin 31, active high*/ +/* +* Master Tri-state Enable for pin 31, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_SHIFT 31 -#define IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_MASK 0x80000000U +#define IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_SHIFT 31 +#define IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_MASK 0x80000000U -/*Master Tri-state Enable for pin 32, active high*/ +/* +* Master Tri-state Enable for pin 32, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_SHIFT 0 -#define IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_MASK 0x00000001U +#define IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_SHIFT 0 +#define IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_MASK 0x00000001U -/*Master Tri-state Enable for pin 33, active high*/ +/* +* Master Tri-state Enable for pin 33, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_SHIFT 1 -#define IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_MASK 0x00000002U +#define IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_SHIFT 1 +#define IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_MASK 0x00000002U -/*Master Tri-state Enable for pin 34, active high*/ +/* +* Master Tri-state Enable for pin 34, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_SHIFT 2 -#define IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_MASK 0x00000004U +#define IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_SHIFT 2 +#define IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_MASK 0x00000004U -/*Master Tri-state Enable for pin 35, active high*/ +/* +* Master Tri-state Enable for pin 35, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_SHIFT 3 -#define IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_MASK 0x00000008U +#define IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_SHIFT 3 +#define IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_MASK 0x00000008U -/*Master Tri-state Enable for pin 36, active high*/ +/* +* Master Tri-state Enable for pin 36, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_SHIFT 4 -#define IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_MASK 0x00000010U +#define IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_SHIFT 4 +#define IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_MASK 0x00000010U -/*Master Tri-state Enable for pin 37, active high*/ +/* +* Master Tri-state Enable for pin 37, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_SHIFT 5 -#define IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_MASK 0x00000020U +#define IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_SHIFT 5 +#define IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_MASK 0x00000020U -/*Master Tri-state Enable for pin 38, active high*/ +/* +* Master Tri-state Enable for pin 38, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_SHIFT 6 -#define IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_MASK 0x00000040U +#define IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_SHIFT 6 +#define IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_MASK 0x00000040U -/*Master Tri-state Enable for pin 39, active high*/ +/* +* Master Tri-state Enable for pin 39, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_SHIFT 7 -#define IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_MASK 0x00000080U +#define IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_SHIFT 7 +#define IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_MASK 0x00000080U -/*Master Tri-state Enable for pin 40, active high*/ +/* +* Master Tri-state Enable for pin 40, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_SHIFT 8 -#define IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_MASK 0x00000100U +#define IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_SHIFT 8 +#define IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_MASK 0x00000100U -/*Master Tri-state Enable for pin 41, active high*/ +/* +* Master Tri-state Enable for pin 41, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_SHIFT 9 -#define IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_MASK 0x00000200U +#define IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_SHIFT 9 +#define IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_MASK 0x00000200U -/*Master Tri-state Enable for pin 42, active high*/ +/* +* Master Tri-state Enable for pin 42, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_SHIFT 10 -#define IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_MASK 0x00000400U +#define IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_SHIFT 10 +#define IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_MASK 0x00000400U -/*Master Tri-state Enable for pin 43, active high*/ +/* +* Master Tri-state Enable for pin 43, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_SHIFT 11 -#define IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_MASK 0x00000800U +#define IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_SHIFT 11 +#define IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_MASK 0x00000800U -/*Master Tri-state Enable for pin 44, active high*/ +/* +* Master Tri-state Enable for pin 44, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_SHIFT 12 -#define IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_MASK 0x00001000U +#define IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_SHIFT 12 +#define IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_MASK 0x00001000U -/*Master Tri-state Enable for pin 45, active high*/ +/* +* Master Tri-state Enable for pin 45, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_SHIFT 13 -#define IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_MASK 0x00002000U +#define IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_SHIFT 13 +#define IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_MASK 0x00002000U -/*Master Tri-state Enable for pin 46, active high*/ +/* +* Master Tri-state Enable for pin 46, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_SHIFT 14 -#define IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_MASK 0x00004000U +#define IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_SHIFT 14 +#define IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_MASK 0x00004000U -/*Master Tri-state Enable for pin 47, active high*/ +/* +* Master Tri-state Enable for pin 47, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_SHIFT 15 -#define IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_MASK 0x00008000U +#define IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_SHIFT 15 +#define IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_MASK 0x00008000U -/*Master Tri-state Enable for pin 48, active high*/ +/* +* Master Tri-state Enable for pin 48, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_SHIFT 16 -#define IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_MASK 0x00010000U +#define IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_SHIFT 16 +#define IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_MASK 0x00010000U -/*Master Tri-state Enable for pin 49, active high*/ +/* +* Master Tri-state Enable for pin 49, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_SHIFT 17 -#define IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_MASK 0x00020000U +#define IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_SHIFT 17 +#define IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_MASK 0x00020000U -/*Master Tri-state Enable for pin 50, active high*/ +/* +* Master Tri-state Enable for pin 50, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_SHIFT 18 -#define IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_MASK 0x00040000U +#define IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_SHIFT 18 +#define IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_MASK 0x00040000U -/*Master Tri-state Enable for pin 51, active high*/ +/* +* Master Tri-state Enable for pin 51, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_SHIFT 19 -#define IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_MASK 0x00080000U +#define IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_SHIFT 19 +#define IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_MASK 0x00080000U -/*Master Tri-state Enable for pin 52, active high*/ +/* +* Master Tri-state Enable for pin 52, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_SHIFT 20 -#define IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_MASK 0x00100000U +#define IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_SHIFT 20 +#define IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_MASK 0x00100000U -/*Master Tri-state Enable for pin 53, active high*/ +/* +* Master Tri-state Enable for pin 53, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_SHIFT 21 -#define IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_MASK 0x00200000U +#define IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_SHIFT 21 +#define IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_MASK 0x00200000U -/*Master Tri-state Enable for pin 54, active high*/ +/* +* Master Tri-state Enable for pin 54, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_SHIFT 22 -#define IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_MASK 0x00400000U +#define IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_SHIFT 22 +#define IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_MASK 0x00400000U -/*Master Tri-state Enable for pin 55, active high*/ +/* +* Master Tri-state Enable for pin 55, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_SHIFT 23 -#define IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_MASK 0x00800000U +#define IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_SHIFT 23 +#define IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_MASK 0x00800000U -/*Master Tri-state Enable for pin 56, active high*/ +/* +* Master Tri-state Enable for pin 56, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_SHIFT 24 -#define IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_MASK 0x01000000U +#define IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_SHIFT 24 +#define IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_MASK 0x01000000U -/*Master Tri-state Enable for pin 57, active high*/ +/* +* Master Tri-state Enable for pin 57, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_SHIFT 25 -#define IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_MASK 0x02000000U +#define IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_SHIFT 25 +#define IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_MASK 0x02000000U -/*Master Tri-state Enable for pin 58, active high*/ +/* +* Master Tri-state Enable for pin 58, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_SHIFT 26 -#define IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_MASK 0x04000000U +#define IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_SHIFT 26 +#define IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_MASK 0x04000000U -/*Master Tri-state Enable for pin 59, active high*/ +/* +* Master Tri-state Enable for pin 59, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_SHIFT 27 -#define IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_MASK 0x08000000U +#define IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_SHIFT 27 +#define IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_MASK 0x08000000U -/*Master Tri-state Enable for pin 60, active high*/ +/* +* Master Tri-state Enable for pin 60, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_SHIFT 28 -#define IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_MASK 0x10000000U +#define IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_SHIFT 28 +#define IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_MASK 0x10000000U -/*Master Tri-state Enable for pin 61, active high*/ +/* +* Master Tri-state Enable for pin 61, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_SHIFT 29 -#define IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_MASK 0x20000000U +#define IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_SHIFT 29 +#define IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_MASK 0x20000000U -/*Master Tri-state Enable for pin 62, active high*/ +/* +* Master Tri-state Enable for pin 62, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_SHIFT 30 -#define IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_MASK 0x40000000U +#define IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_SHIFT 30 +#define IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_MASK 0x40000000U -/*Master Tri-state Enable for pin 63, active high*/ +/* +* Master Tri-state Enable for pin 63, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_SHIFT 31 -#define IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_MASK 0x80000000U +#define IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_SHIFT 31 +#define IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_MASK 0x80000000U -/*Master Tri-state Enable for pin 64, active high*/ +/* +* Master Tri-state Enable for pin 64, active high +*/ #undef IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_DEFVAL 0x00003FFF -#define IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_SHIFT 0 -#define IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_MASK 0x00000001U +#define IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_DEFVAL 0x00003FFF +#define IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_SHIFT 0 +#define IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_MASK 0x00000001U -/*Master Tri-state Enable for pin 65, active high*/ +/* +* Master Tri-state Enable for pin 65, active high +*/ #undef IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_DEFVAL 0x00003FFF -#define IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_SHIFT 1 -#define IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_MASK 0x00000002U +#define IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_DEFVAL 0x00003FFF +#define IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_SHIFT 1 +#define IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_MASK 0x00000002U -/*Master Tri-state Enable for pin 66, active high*/ +/* +* Master Tri-state Enable for pin 66, active high +*/ #undef IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_DEFVAL 0x00003FFF -#define IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_SHIFT 2 -#define IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_MASK 0x00000004U +#define IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_DEFVAL 0x00003FFF +#define IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_SHIFT 2 +#define IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_MASK 0x00000004U -/*Master Tri-state Enable for pin 67, active high*/ +/* +* Master Tri-state Enable for pin 67, active high +*/ #undef IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_DEFVAL 0x00003FFF -#define IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_SHIFT 3 -#define IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_MASK 0x00000008U +#define IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_DEFVAL 0x00003FFF +#define IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_SHIFT 3 +#define IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_MASK 0x00000008U -/*Master Tri-state Enable for pin 68, active high*/ +/* +* Master Tri-state Enable for pin 68, active high +*/ #undef IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_DEFVAL 0x00003FFF -#define IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_SHIFT 4 -#define IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_MASK 0x00000010U +#define IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_DEFVAL 0x00003FFF +#define IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_SHIFT 4 +#define IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_MASK 0x00000010U -/*Master Tri-state Enable for pin 69, active high*/ +/* +* Master Tri-state Enable for pin 69, active high +*/ #undef IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_DEFVAL 0x00003FFF -#define IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_SHIFT 5 -#define IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_MASK 0x00000020U +#define IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_DEFVAL 0x00003FFF +#define IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_SHIFT 5 +#define IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_MASK 0x00000020U -/*Master Tri-state Enable for pin 70, active high*/ +/* +* Master Tri-state Enable for pin 70, active high +*/ #undef IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_DEFVAL 0x00003FFF -#define IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_SHIFT 6 -#define IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_MASK 0x00000040U +#define IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_DEFVAL 0x00003FFF +#define IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_SHIFT 6 +#define IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_MASK 0x00000040U -/*Master Tri-state Enable for pin 71, active high*/ +/* +* Master Tri-state Enable for pin 71, active high +*/ #undef IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_DEFVAL 0x00003FFF -#define IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_SHIFT 7 -#define IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_MASK 0x00000080U +#define IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_DEFVAL 0x00003FFF +#define IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_SHIFT 7 +#define IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_MASK 0x00000080U -/*Master Tri-state Enable for pin 72, active high*/ +/* +* Master Tri-state Enable for pin 72, active high +*/ #undef IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_DEFVAL 0x00003FFF -#define IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_SHIFT 8 -#define IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_MASK 0x00000100U +#define IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_DEFVAL 0x00003FFF +#define IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_SHIFT 8 +#define IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_MASK 0x00000100U -/*Master Tri-state Enable for pin 73, active high*/ +/* +* Master Tri-state Enable for pin 73, active high +*/ #undef IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_DEFVAL 0x00003FFF -#define IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_SHIFT 9 -#define IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_MASK 0x00000200U +#define IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_DEFVAL 0x00003FFF +#define IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_SHIFT 9 +#define IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_MASK 0x00000200U -/*Master Tri-state Enable for pin 74, active high*/ +/* +* Master Tri-state Enable for pin 74, active high +*/ #undef IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_DEFVAL 0x00003FFF -#define IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_SHIFT 10 -#define IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_MASK 0x00000400U +#define IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_DEFVAL 0x00003FFF +#define IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_SHIFT 10 +#define IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_MASK 0x00000400U -/*Master Tri-state Enable for pin 75, active high*/ +/* +* Master Tri-state Enable for pin 75, active high +*/ #undef IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_DEFVAL 0x00003FFF -#define IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_SHIFT 11 -#define IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_MASK 0x00000800U +#define IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_DEFVAL 0x00003FFF +#define IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_SHIFT 11 +#define IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_MASK 0x00000800U -/*Master Tri-state Enable for pin 76, active high*/ +/* +* Master Tri-state Enable for pin 76, active high +*/ #undef IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_DEFVAL 0x00003FFF -#define IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_SHIFT 12 -#define IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_MASK 0x00001000U +#define IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_DEFVAL 0x00003FFF +#define IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_SHIFT 12 +#define IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_MASK 0x00001000U -/*Master Tri-state Enable for pin 77, active high*/ +/* +* Master Tri-state Enable for pin 77, active high +*/ #undef IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_DEFVAL 0x00003FFF -#define IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_SHIFT 13 -#define IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_MASK 0x00002000U +#define IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_DEFVAL 0x00003FFF +#define IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_SHIFT 13 +#define IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_MASK 0x00002000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_SHIFT 0 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_MASK 0x00000001U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_MASK 0x00000001U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_SHIFT 1 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_MASK 0x00000002U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_MASK 0x00000002U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_SHIFT 2 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_MASK 0x00000004U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_MASK 0x00000004U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_SHIFT 3 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_MASK 0x00000008U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_MASK 0x00000008U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_SHIFT 4 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_MASK 0x00000010U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_MASK 0x00000010U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_SHIFT 5 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_MASK 0x00000020U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_MASK 0x00000020U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_SHIFT 6 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_MASK 0x00000040U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_MASK 0x00000040U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_SHIFT 7 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_MASK 0x00000080U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_MASK 0x00000080U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_SHIFT 8 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_MASK 0x00000100U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_MASK 0x00000100U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_SHIFT 9 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_MASK 0x00000200U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_MASK 0x00000200U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_SHIFT 10 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_MASK 0x00000400U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_MASK 0x00000400U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_SHIFT 11 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_MASK 0x00000800U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_MASK 0x00000800U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_SHIFT 12 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_MASK 0x00001000U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_MASK 0x00001000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_SHIFT 13 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_MASK 0x00002000U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_MASK 0x00002000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_SHIFT 14 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_MASK 0x00004000U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_MASK 0x00004000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_SHIFT 15 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_MASK 0x00008000U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_MASK 0x00008000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_SHIFT 16 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_MASK 0x00010000U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_MASK 0x00010000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_SHIFT 17 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_MASK 0x00020000U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_MASK 0x00020000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_SHIFT 18 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_MASK 0x00040000U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_MASK 0x00040000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_SHIFT 19 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_MASK 0x00080000U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_MASK 0x00080000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_SHIFT 20 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_MASK 0x00100000U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_MASK 0x00100000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_SHIFT 21 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_MASK 0x00200000U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_MASK 0x00200000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_SHIFT 22 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_MASK 0x00400000U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_MASK 0x00400000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_SHIFT 23 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_MASK 0x00800000U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_MASK 0x00800000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_SHIFT 24 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_MASK 0x01000000U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_MASK 0x01000000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_SHIFT 25 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_MASK 0x02000000U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_MASK 0x02000000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_SHIFT 0 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_MASK 0x00000001U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_MASK 0x00000001U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_SHIFT 1 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_MASK 0x00000002U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_MASK 0x00000002U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_SHIFT 2 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_MASK 0x00000004U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_MASK 0x00000004U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_SHIFT 3 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_MASK 0x00000008U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_MASK 0x00000008U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_SHIFT 4 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_MASK 0x00000010U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_MASK 0x00000010U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_SHIFT 5 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_MASK 0x00000020U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_MASK 0x00000020U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_SHIFT 6 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_MASK 0x00000040U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_MASK 0x00000040U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_SHIFT 7 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_MASK 0x00000080U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_MASK 0x00000080U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_SHIFT 8 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_MASK 0x00000100U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_MASK 0x00000100U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_SHIFT 9 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_MASK 0x00000200U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_MASK 0x00000200U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_SHIFT 10 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_MASK 0x00000400U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_MASK 0x00000400U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_SHIFT 11 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_MASK 0x00000800U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_MASK 0x00000800U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_SHIFT 12 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_MASK 0x00001000U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_MASK 0x00001000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_SHIFT 13 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_MASK 0x00002000U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_MASK 0x00002000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_SHIFT 14 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_MASK 0x00004000U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_MASK 0x00004000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_SHIFT 15 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_MASK 0x00008000U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_MASK 0x00008000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_SHIFT 16 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_MASK 0x00010000U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_MASK 0x00010000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_SHIFT 17 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_MASK 0x00020000U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_MASK 0x00020000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_SHIFT 18 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_MASK 0x00040000U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_MASK 0x00040000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_SHIFT 19 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_MASK 0x00080000U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_MASK 0x00080000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_SHIFT 20 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_MASK 0x00100000U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_MASK 0x00100000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_SHIFT 21 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_MASK 0x00200000U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_MASK 0x00200000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_SHIFT 22 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_MASK 0x00400000U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_MASK 0x00400000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_SHIFT 23 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_MASK 0x00800000U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_MASK 0x00800000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_SHIFT 24 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_MASK 0x01000000U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_MASK 0x01000000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_SHIFT 25 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_MASK 0x02000000U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_MASK 0x02000000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT 0 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK 0x00000001U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK 0x00000001U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT 1 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK 0x00000002U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK 0x00000002U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT 2 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK 0x00000004U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK 0x00000004U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT 3 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK 0x00000008U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK 0x00000008U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT 4 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK 0x00000010U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK 0x00000010U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT 5 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK 0x00000020U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK 0x00000020U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT 6 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK 0x00000040U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK 0x00000040U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT 7 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK 0x00000080U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK 0x00000080U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT 8 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK 0x00000100U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK 0x00000100U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT 9 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK 0x00000200U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK 0x00000200U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT 10 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK 0x00000400U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK 0x00000400U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT 11 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK 0x00000800U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK 0x00000800U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT 12 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK 0x00001000U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK 0x00001000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT 13 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK 0x00002000U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK 0x00002000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT 14 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK 0x00004000U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK 0x00004000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT 15 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK 0x00008000U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK 0x00008000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT 16 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK 0x00010000U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK 0x00010000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT 17 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK 0x00020000U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK 0x00020000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT 18 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK 0x00040000U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK 0x00040000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT 19 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK 0x00080000U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK 0x00080000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT 20 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK 0x00100000U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK 0x00100000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT 21 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK 0x00200000U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK 0x00200000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT 22 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK 0x00400000U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK 0x00400000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT 23 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK 0x00800000U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK 0x00800000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT 24 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK 0x01000000U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK 0x01000000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT 25 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK 0x02000000U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK 0x02000000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT 0 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK 0x00000001U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK 0x00000001U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT 1 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK 0x00000002U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK 0x00000002U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT 2 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK 0x00000004U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK 0x00000004U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT 3 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK 0x00000008U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK 0x00000008U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT 4 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK 0x00000010U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK 0x00000010U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT 5 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK 0x00000020U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK 0x00000020U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT 6 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK 0x00000040U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK 0x00000040U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT 7 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK 0x00000080U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK 0x00000080U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT 8 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK 0x00000100U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK 0x00000100U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT 9 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK 0x00000200U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK 0x00000200U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT 10 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK 0x00000400U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK 0x00000400U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT 11 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK 0x00000800U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK 0x00000800U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT 12 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK 0x00001000U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK 0x00001000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT 13 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK 0x00002000U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK 0x00002000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT 14 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK 0x00004000U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK 0x00004000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT 15 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK 0x00008000U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK 0x00008000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT 16 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK 0x00010000U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK 0x00010000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT 17 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK 0x00020000U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK 0x00020000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT 18 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK 0x00040000U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK 0x00040000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT 19 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK 0x00080000U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK 0x00080000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT 20 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK 0x00100000U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK 0x00100000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT 21 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK 0x00200000U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK 0x00200000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT 22 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK 0x00400000U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK 0x00400000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT 23 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK 0x00800000U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK 0x00800000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT 24 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK 0x01000000U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK 0x01000000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT 25 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK 0x02000000U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK 0x02000000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_SHIFT 0 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_MASK 0x00000001U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_MASK 0x00000001U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_SHIFT 1 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_MASK 0x00000002U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_MASK 0x00000002U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_SHIFT 2 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_MASK 0x00000004U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_MASK 0x00000004U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_SHIFT 3 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_MASK 0x00000008U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_MASK 0x00000008U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_SHIFT 4 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_MASK 0x00000010U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_MASK 0x00000010U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_SHIFT 5 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_MASK 0x00000020U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_MASK 0x00000020U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_SHIFT 6 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_MASK 0x00000040U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_MASK 0x00000040U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_SHIFT 7 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_MASK 0x00000080U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_MASK 0x00000080U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_SHIFT 8 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_MASK 0x00000100U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_MASK 0x00000100U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_SHIFT 9 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_MASK 0x00000200U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_MASK 0x00000200U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_SHIFT 10 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_MASK 0x00000400U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_MASK 0x00000400U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_SHIFT 11 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_MASK 0x00000800U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_MASK 0x00000800U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_SHIFT 12 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_MASK 0x00001000U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_MASK 0x00001000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_SHIFT 13 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_MASK 0x00002000U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_MASK 0x00002000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_SHIFT 14 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_MASK 0x00004000U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_MASK 0x00004000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_SHIFT 15 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_MASK 0x00008000U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_MASK 0x00008000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_SHIFT 16 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_MASK 0x00010000U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_MASK 0x00010000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_SHIFT 17 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_MASK 0x00020000U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_MASK 0x00020000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_SHIFT 18 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_MASK 0x00040000U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_MASK 0x00040000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_SHIFT 19 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_MASK 0x00080000U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_MASK 0x00080000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_SHIFT 20 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_MASK 0x00100000U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_MASK 0x00100000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_SHIFT 21 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_MASK 0x00200000U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_MASK 0x00200000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_SHIFT 22 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_MASK 0x00400000U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_MASK 0x00400000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_SHIFT 23 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_MASK 0x00800000U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_MASK 0x00800000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_SHIFT 24 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_MASK 0x01000000U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_MASK 0x01000000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_SHIFT 25 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_MASK 0x02000000U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_MASK 0x02000000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT 0 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK 0x00000001U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK 0x00000001U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT 1 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK 0x00000002U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK 0x00000002U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT 2 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK 0x00000004U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK 0x00000004U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT 3 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK 0x00000008U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK 0x00000008U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT 4 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK 0x00000010U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK 0x00000010U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT 5 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK 0x00000020U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK 0x00000020U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT 6 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK 0x00000040U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK 0x00000040U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT 7 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK 0x00000080U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK 0x00000080U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT 8 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK 0x00000100U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK 0x00000100U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT 9 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK 0x00000200U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK 0x00000200U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT 10 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK 0x00000400U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK 0x00000400U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT 11 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK 0x00000800U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK 0x00000800U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT 12 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK 0x00001000U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK 0x00001000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT 13 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK 0x00002000U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK 0x00002000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT 14 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK 0x00004000U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK 0x00004000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT 15 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK 0x00008000U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK 0x00008000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT 16 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK 0x00010000U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK 0x00010000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT 17 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK 0x00020000U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK 0x00020000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT 18 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK 0x00040000U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK 0x00040000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT 19 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK 0x00080000U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK 0x00080000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT 20 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK 0x00100000U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK 0x00100000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT 21 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK 0x00200000U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK 0x00200000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT 22 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK 0x00400000U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK 0x00400000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT 23 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK 0x00800000U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK 0x00800000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT 24 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK 0x01000000U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK 0x01000000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT 25 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK 0x02000000U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK 0x02000000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_SHIFT 0 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_MASK 0x00000001U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_MASK 0x00000001U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_SHIFT 1 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_MASK 0x00000002U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_MASK 0x00000002U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_SHIFT 2 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_MASK 0x00000004U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_MASK 0x00000004U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_SHIFT 3 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_MASK 0x00000008U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_MASK 0x00000008U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_SHIFT 4 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_MASK 0x00000010U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_MASK 0x00000010U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_SHIFT 5 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_MASK 0x00000020U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_MASK 0x00000020U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_SHIFT 6 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_MASK 0x00000040U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_MASK 0x00000040U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_SHIFT 7 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_MASK 0x00000080U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_MASK 0x00000080U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_SHIFT 8 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_MASK 0x00000100U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_MASK 0x00000100U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_SHIFT 9 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_MASK 0x00000200U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_MASK 0x00000200U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_SHIFT 10 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_MASK 0x00000400U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_MASK 0x00000400U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_SHIFT 11 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_MASK 0x00000800U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_MASK 0x00000800U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_SHIFT 12 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_MASK 0x00001000U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_MASK 0x00001000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_SHIFT 13 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_MASK 0x00002000U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_MASK 0x00002000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_SHIFT 14 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_MASK 0x00004000U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_MASK 0x00004000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_SHIFT 15 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_MASK 0x00008000U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_MASK 0x00008000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_SHIFT 16 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_MASK 0x00010000U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_MASK 0x00010000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_SHIFT 17 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_MASK 0x00020000U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_MASK 0x00020000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_SHIFT 18 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_MASK 0x00040000U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_MASK 0x00040000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_SHIFT 19 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_MASK 0x00080000U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_MASK 0x00080000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_SHIFT 20 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_MASK 0x00100000U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_MASK 0x00100000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_SHIFT 21 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_MASK 0x00200000U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_MASK 0x00200000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_SHIFT 22 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_MASK 0x00400000U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_MASK 0x00400000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_SHIFT 23 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_MASK 0x00800000U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_MASK 0x00800000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_SHIFT 24 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_MASK 0x01000000U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_MASK 0x01000000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_SHIFT 25 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_MASK 0x02000000U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_MASK 0x02000000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_SHIFT 0 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_MASK 0x00000001U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_MASK 0x00000001U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_SHIFT 1 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_MASK 0x00000002U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_MASK 0x00000002U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_SHIFT 2 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_MASK 0x00000004U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_MASK 0x00000004U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_SHIFT 3 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_MASK 0x00000008U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_MASK 0x00000008U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_SHIFT 4 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_MASK 0x00000010U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_MASK 0x00000010U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_SHIFT 5 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_MASK 0x00000020U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_MASK 0x00000020U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_SHIFT 6 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_MASK 0x00000040U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_MASK 0x00000040U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_SHIFT 7 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_MASK 0x00000080U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_MASK 0x00000080U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_SHIFT 8 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_MASK 0x00000100U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_MASK 0x00000100U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_SHIFT 9 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_MASK 0x00000200U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_MASK 0x00000200U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_SHIFT 10 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_MASK 0x00000400U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_MASK 0x00000400U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_SHIFT 11 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_MASK 0x00000800U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_MASK 0x00000800U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_SHIFT 12 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_MASK 0x00001000U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_MASK 0x00001000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_SHIFT 13 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_MASK 0x00002000U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_MASK 0x00002000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_SHIFT 14 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_MASK 0x00004000U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_MASK 0x00004000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_SHIFT 15 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_MASK 0x00008000U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_MASK 0x00008000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_SHIFT 16 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_MASK 0x00010000U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_MASK 0x00010000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_SHIFT 17 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_MASK 0x00020000U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_MASK 0x00020000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_SHIFT 18 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_MASK 0x00040000U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_MASK 0x00040000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_SHIFT 19 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_MASK 0x00080000U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_MASK 0x00080000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_SHIFT 20 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_MASK 0x00100000U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_MASK 0x00100000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_SHIFT 21 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_MASK 0x00200000U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_MASK 0x00200000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_SHIFT 22 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_MASK 0x00400000U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_MASK 0x00400000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_SHIFT 23 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_MASK 0x00800000U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_MASK 0x00800000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_SHIFT 24 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_MASK 0x01000000U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_MASK 0x01000000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_SHIFT 25 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_MASK 0x02000000U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_MASK 0x02000000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT 0 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK 0x00000001U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK 0x00000001U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT 1 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK 0x00000002U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK 0x00000002U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT 2 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK 0x00000004U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK 0x00000004U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT 3 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK 0x00000008U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK 0x00000008U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT 4 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK 0x00000010U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK 0x00000010U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT 5 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK 0x00000020U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK 0x00000020U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT 6 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK 0x00000040U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK 0x00000040U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT 7 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK 0x00000080U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK 0x00000080U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT 8 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK 0x00000100U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK 0x00000100U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT 9 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK 0x00000200U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK 0x00000200U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT 10 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK 0x00000400U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK 0x00000400U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT 11 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK 0x00000800U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK 0x00000800U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT 12 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK 0x00001000U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK 0x00001000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT 13 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK 0x00002000U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK 0x00002000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT 14 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK 0x00004000U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK 0x00004000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT 15 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK 0x00008000U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK 0x00008000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT 16 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK 0x00010000U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK 0x00010000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT 17 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK 0x00020000U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK 0x00020000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT 18 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK 0x00040000U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK 0x00040000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT 19 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK 0x00080000U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK 0x00080000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT 20 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK 0x00100000U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK 0x00100000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT 21 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK 0x00200000U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK 0x00200000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT 22 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK 0x00400000U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK 0x00400000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT 23 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK 0x00800000U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK 0x00800000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT 24 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK 0x01000000U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK 0x01000000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT 25 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK 0x02000000U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK 0x02000000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT 0 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK 0x00000001U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK 0x00000001U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT 1 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK 0x00000002U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK 0x00000002U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT 2 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK 0x00000004U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK 0x00000004U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT 3 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK 0x00000008U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK 0x00000008U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT 4 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK 0x00000010U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK 0x00000010U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT 5 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK 0x00000020U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK 0x00000020U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT 6 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK 0x00000040U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK 0x00000040U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT 7 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK 0x00000080U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK 0x00000080U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT 8 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK 0x00000100U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK 0x00000100U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT 9 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK 0x00000200U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK 0x00000200U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT 10 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK 0x00000400U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK 0x00000400U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT 11 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK 0x00000800U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK 0x00000800U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT 12 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK 0x00001000U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK 0x00001000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT 13 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK 0x00002000U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK 0x00002000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT 14 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK 0x00004000U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK 0x00004000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT 15 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK 0x00008000U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK 0x00008000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT 16 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK 0x00010000U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK 0x00010000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT 17 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK 0x00020000U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK 0x00020000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT 18 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK 0x00040000U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK 0x00040000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT 19 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK 0x00080000U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK 0x00080000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT 20 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK 0x00100000U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK 0x00100000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT 21 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK 0x00200000U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK 0x00200000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT 22 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK 0x00400000U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK 0x00400000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT 23 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK 0x00800000U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK 0x00800000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT 24 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK 0x01000000U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK 0x01000000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT 25 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK 0x02000000U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK 0x02000000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_SHIFT 12 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_MASK 0x00001000U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_SHIFT 12 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_MASK 0x00001000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_SHIFT 13 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_MASK 0x00002000U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_SHIFT 13 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_MASK 0x00002000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_SHIFT 14 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_MASK 0x00004000U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_SHIFT 14 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_MASK 0x00004000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_SHIFT 15 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_MASK 0x00008000U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_SHIFT 15 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_MASK 0x00008000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_SHIFT 16 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_MASK 0x00010000U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_SHIFT 16 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_MASK 0x00010000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_SHIFT 17 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_MASK 0x00020000U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_SHIFT 17 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_MASK 0x00020000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_SHIFT 18 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_MASK 0x00040000U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_SHIFT 18 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_MASK 0x00040000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_SHIFT 19 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_MASK 0x00080000U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_SHIFT 19 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_MASK 0x00080000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_SHIFT 20 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_MASK 0x00100000U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_SHIFT 20 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_MASK 0x00100000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_SHIFT 21 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_MASK 0x00200000U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_SHIFT 21 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_MASK 0x00200000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_SHIFT 22 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_MASK 0x00400000U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_SHIFT 22 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_MASK 0x00400000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_SHIFT 23 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_MASK 0x00800000U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_SHIFT 23 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_MASK 0x00800000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_SHIFT 24 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_MASK 0x01000000U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_SHIFT 24 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_MASK 0x01000000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_SHIFT 25 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_MASK 0x02000000U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_SHIFT 25 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_MASK 0x02000000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_SHIFT 0 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_MASK 0x00000001U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_SHIFT 0 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_MASK 0x00000001U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_SHIFT 1 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_MASK 0x00000002U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_SHIFT 1 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_MASK 0x00000002U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_SHIFT 2 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_MASK 0x00000004U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_SHIFT 2 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_MASK 0x00000004U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_SHIFT 3 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_MASK 0x00000008U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_SHIFT 3 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_MASK 0x00000008U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_SHIFT 4 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_MASK 0x00000010U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_SHIFT 4 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_MASK 0x00000010U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_SHIFT 5 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_MASK 0x00000020U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_SHIFT 5 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_MASK 0x00000020U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_SHIFT 6 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_MASK 0x00000040U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_SHIFT 6 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_MASK 0x00000040U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_SHIFT 7 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_MASK 0x00000080U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_SHIFT 7 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_MASK 0x00000080U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_SHIFT 8 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_MASK 0x00000100U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_SHIFT 8 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_MASK 0x00000100U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_SHIFT 9 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_MASK 0x00000200U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_SHIFT 9 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_MASK 0x00000200U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_SHIFT 10 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_MASK 0x00000400U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_SHIFT 10 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_MASK 0x00000400U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_SHIFT 11 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_MASK 0x00000800U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_SHIFT 11 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_MASK 0x00000800U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT 0 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK 0x00000001U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK 0x00000001U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT 1 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK 0x00000002U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK 0x00000002U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT 2 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK 0x00000004U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK 0x00000004U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT 3 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK 0x00000008U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK 0x00000008U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT 4 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK 0x00000010U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK 0x00000010U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT 5 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK 0x00000020U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK 0x00000020U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT 6 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK 0x00000040U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK 0x00000040U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT 7 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK 0x00000080U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK 0x00000080U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT 8 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK 0x00000100U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK 0x00000100U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT 9 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK 0x00000200U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK 0x00000200U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT 10 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK 0x00000400U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK 0x00000400U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT 11 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK 0x00000800U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK 0x00000800U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT 12 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK 0x00001000U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK 0x00001000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT 13 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK 0x00002000U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK 0x00002000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT 14 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK 0x00004000U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK 0x00004000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT 15 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK 0x00008000U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK 0x00008000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT 16 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK 0x00010000U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK 0x00010000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT 17 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK 0x00020000U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK 0x00020000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT 18 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK 0x00040000U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK 0x00040000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT 19 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK 0x00080000U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK 0x00080000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT 20 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK 0x00100000U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK 0x00100000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT 21 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK 0x00200000U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK 0x00200000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT 22 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK 0x00400000U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK 0x00400000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT 23 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK 0x00800000U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK 0x00800000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT 24 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK 0x01000000U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK 0x01000000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT 25 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK 0x02000000U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK 0x02000000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_SHIFT 0 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_MASK 0x00000001U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_MASK 0x00000001U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_SHIFT 1 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_MASK 0x00000002U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_MASK 0x00000002U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_SHIFT 2 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_MASK 0x00000004U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_MASK 0x00000004U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_SHIFT 3 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_MASK 0x00000008U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_MASK 0x00000008U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_SHIFT 4 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_MASK 0x00000010U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_MASK 0x00000010U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_SHIFT 5 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_MASK 0x00000020U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_MASK 0x00000020U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_SHIFT 6 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_MASK 0x00000040U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_MASK 0x00000040U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_SHIFT 7 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_MASK 0x00000080U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_MASK 0x00000080U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_SHIFT 8 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_MASK 0x00000100U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_MASK 0x00000100U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_SHIFT 9 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_MASK 0x00000200U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_MASK 0x00000200U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_SHIFT 10 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_MASK 0x00000400U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_MASK 0x00000400U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_SHIFT 11 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_MASK 0x00000800U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_MASK 0x00000800U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_SHIFT 12 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_MASK 0x00001000U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_MASK 0x00001000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_SHIFT 13 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_MASK 0x00002000U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_MASK 0x00002000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_SHIFT 14 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_MASK 0x00004000U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_MASK 0x00004000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_SHIFT 15 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_MASK 0x00008000U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_MASK 0x00008000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_SHIFT 16 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_MASK 0x00010000U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_MASK 0x00010000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_SHIFT 17 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_MASK 0x00020000U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_MASK 0x00020000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_SHIFT 18 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_MASK 0x00040000U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_MASK 0x00040000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_SHIFT 19 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_MASK 0x00080000U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_MASK 0x00080000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_SHIFT 20 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_MASK 0x00100000U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_MASK 0x00100000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_SHIFT 21 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_MASK 0x00200000U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_MASK 0x00200000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_SHIFT 22 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_MASK 0x00400000U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_MASK 0x00400000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_SHIFT 23 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_MASK 0x00800000U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_MASK 0x00800000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_SHIFT 24 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_MASK 0x01000000U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_MASK 0x01000000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_SHIFT 25 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_MASK 0x02000000U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_MASK 0x02000000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_SHIFT 0 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_MASK 0x00000001U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_MASK 0x00000001U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_SHIFT 1 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_MASK 0x00000002U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_MASK 0x00000002U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_SHIFT 2 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_MASK 0x00000004U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_MASK 0x00000004U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_SHIFT 3 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_MASK 0x00000008U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_MASK 0x00000008U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_SHIFT 4 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_MASK 0x00000010U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_MASK 0x00000010U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_SHIFT 5 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_MASK 0x00000020U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_MASK 0x00000020U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_SHIFT 6 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_MASK 0x00000040U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_MASK 0x00000040U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_SHIFT 7 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_MASK 0x00000080U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_MASK 0x00000080U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_SHIFT 8 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_MASK 0x00000100U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_MASK 0x00000100U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_SHIFT 9 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_MASK 0x00000200U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_MASK 0x00000200U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_SHIFT 10 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_MASK 0x00000400U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_MASK 0x00000400U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_SHIFT 11 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_MASK 0x00000800U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_MASK 0x00000800U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_SHIFT 12 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_MASK 0x00001000U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_MASK 0x00001000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_SHIFT 13 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_MASK 0x00002000U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_MASK 0x00002000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_SHIFT 14 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_MASK 0x00004000U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_MASK 0x00004000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_SHIFT 15 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_MASK 0x00008000U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_MASK 0x00008000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_SHIFT 16 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_MASK 0x00010000U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_MASK 0x00010000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_SHIFT 17 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_MASK 0x00020000U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_MASK 0x00020000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_SHIFT 18 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_MASK 0x00040000U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_MASK 0x00040000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_SHIFT 19 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_MASK 0x00080000U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_MASK 0x00080000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_SHIFT 20 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_MASK 0x00100000U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_MASK 0x00100000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_SHIFT 21 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_MASK 0x00200000U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_MASK 0x00200000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_SHIFT 22 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_MASK 0x00400000U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_MASK 0x00400000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_SHIFT 23 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_MASK 0x00800000U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_MASK 0x00800000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_SHIFT 24 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_MASK 0x01000000U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_MASK 0x01000000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_SHIFT 25 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_MASK 0x02000000U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_MASK 0x02000000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT 0 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK 0x00000001U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK 0x00000001U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT 1 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK 0x00000002U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK 0x00000002U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT 2 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK 0x00000004U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK 0x00000004U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT 3 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK 0x00000008U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK 0x00000008U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT 4 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK 0x00000010U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK 0x00000010U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT 5 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK 0x00000020U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK 0x00000020U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT 6 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK 0x00000040U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK 0x00000040U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT 7 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK 0x00000080U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK 0x00000080U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT 8 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK 0x00000100U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK 0x00000100U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT 9 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK 0x00000200U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK 0x00000200U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT 10 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK 0x00000400U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK 0x00000400U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT 11 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK 0x00000800U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK 0x00000800U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT 12 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK 0x00001000U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK 0x00001000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT 13 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK 0x00002000U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK 0x00002000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT 14 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK 0x00004000U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK 0x00004000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT 15 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK 0x00008000U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK 0x00008000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT 16 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK 0x00010000U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK 0x00010000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT 17 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK 0x00020000U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK 0x00020000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT 18 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK 0x00040000U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK 0x00040000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT 19 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK 0x00080000U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK 0x00080000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT 20 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK 0x00100000U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK 0x00100000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT 21 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK 0x00200000U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK 0x00200000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT 22 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK 0x00400000U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK 0x00400000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT 23 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK 0x00800000U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK 0x00800000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT 24 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK 0x01000000U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK 0x01000000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT 25 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK 0x02000000U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK 0x02000000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT 0 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK 0x00000001U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK 0x00000001U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT 1 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK 0x00000002U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK 0x00000002U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT 2 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK 0x00000004U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK 0x00000004U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT 3 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK 0x00000008U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK 0x00000008U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT 4 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK 0x00000010U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK 0x00000010U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT 5 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK 0x00000020U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK 0x00000020U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT 6 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK 0x00000040U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK 0x00000040U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT 7 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK 0x00000080U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK 0x00000080U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT 8 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK 0x00000100U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK 0x00000100U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT 9 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK 0x00000200U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK 0x00000200U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT 10 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK 0x00000400U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK 0x00000400U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT 11 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK 0x00000800U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK 0x00000800U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT 12 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK 0x00001000U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK 0x00001000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT 13 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK 0x00002000U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK 0x00002000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT 14 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK 0x00004000U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK 0x00004000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT 15 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK 0x00008000U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK 0x00008000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT 16 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK 0x00010000U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK 0x00010000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT 17 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK 0x00020000U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK 0x00020000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT 18 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK 0x00040000U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK 0x00040000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT 19 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK 0x00080000U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK 0x00080000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT 20 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK 0x00100000U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK 0x00100000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT 21 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK 0x00200000U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK 0x00200000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT 22 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK 0x00400000U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK 0x00400000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT 23 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK 0x00800000U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK 0x00800000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT 24 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK 0x01000000U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK 0x01000000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT 25 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK 0x02000000U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK 0x02000000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_SHIFT 0 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_MASK 0x00000001U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_MASK 0x00000001U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_SHIFT 1 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_MASK 0x00000002U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_MASK 0x00000002U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_SHIFT 2 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_MASK 0x00000004U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_MASK 0x00000004U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_SHIFT 3 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_MASK 0x00000008U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_MASK 0x00000008U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_SHIFT 4 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_MASK 0x00000010U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_MASK 0x00000010U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_SHIFT 5 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_MASK 0x00000020U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_MASK 0x00000020U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_SHIFT 6 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_MASK 0x00000040U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_MASK 0x00000040U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_SHIFT 7 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_MASK 0x00000080U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_MASK 0x00000080U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_SHIFT 8 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_MASK 0x00000100U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_MASK 0x00000100U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_SHIFT 9 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_MASK 0x00000200U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_MASK 0x00000200U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_SHIFT 10 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_MASK 0x00000400U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_MASK 0x00000400U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_SHIFT 11 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_MASK 0x00000800U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_MASK 0x00000800U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_SHIFT 12 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_MASK 0x00001000U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_MASK 0x00001000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_SHIFT 13 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_MASK 0x00002000U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_MASK 0x00002000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_SHIFT 14 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_MASK 0x00004000U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_MASK 0x00004000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_SHIFT 15 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_MASK 0x00008000U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_MASK 0x00008000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_SHIFT 16 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_MASK 0x00010000U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_MASK 0x00010000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_SHIFT 17 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_MASK 0x00020000U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_MASK 0x00020000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_SHIFT 18 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_MASK 0x00040000U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_MASK 0x00040000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_SHIFT 19 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_MASK 0x00080000U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_MASK 0x00080000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_SHIFT 20 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_MASK 0x00100000U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_MASK 0x00100000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_SHIFT 21 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_MASK 0x00200000U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_MASK 0x00200000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_SHIFT 22 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_MASK 0x00400000U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_MASK 0x00400000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_SHIFT 23 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_MASK 0x00800000U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_MASK 0x00800000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_SHIFT 24 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_MASK 0x01000000U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_MASK 0x01000000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_SHIFT 25 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_MASK 0x02000000U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_MASK 0x02000000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT 0 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK 0x00000001U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK 0x00000001U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT 1 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK 0x00000002U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK 0x00000002U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT 2 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK 0x00000004U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK 0x00000004U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT 3 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK 0x00000008U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK 0x00000008U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT 4 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK 0x00000010U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK 0x00000010U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT 5 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK 0x00000020U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK 0x00000020U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT 6 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK 0x00000040U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK 0x00000040U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT 7 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK 0x00000080U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK 0x00000080U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT 8 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK 0x00000100U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK 0x00000100U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT 9 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK 0x00000200U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK 0x00000200U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT 10 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK 0x00000400U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK 0x00000400U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT 11 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK 0x00000800U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK 0x00000800U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT 12 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK 0x00001000U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK 0x00001000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT 13 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK 0x00002000U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK 0x00002000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT 14 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK 0x00004000U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK 0x00004000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT 15 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK 0x00008000U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK 0x00008000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT 16 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK 0x00010000U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK 0x00010000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT 17 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK 0x00020000U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK 0x00020000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT 18 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK 0x00040000U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK 0x00040000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT 19 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK 0x00080000U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK 0x00080000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT 20 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK 0x00100000U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK 0x00100000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT 21 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK 0x00200000U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK 0x00200000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT 22 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK 0x00400000U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK 0x00400000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT 23 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK 0x00800000U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK 0x00800000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT 24 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK 0x01000000U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK 0x01000000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT 25 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK 0x02000000U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK 0x02000000U -/*I2C Loopback Control. 0 = Connect I2C inputs according to MIO mapping. 1 = Loop I2C 0 outputs to I2C 1 inputs, and I2C 1 outp - ts to I2C 0 inputs.*/ +/* +* I2C Loopback Control. 0 = Connect I2C inputs according to MIO mapping. 1 + * = Loop I2C 0 outputs to I2C 1 inputs, and I2C 1 outputs to I2C 0 inputs + * . +*/ #undef IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_DEFVAL #undef IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_SHIFT #undef IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_MASK -#define IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_SHIFT 3 -#define IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_MASK 0x00000008U +#define IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_SHIFT 3 +#define IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_MASK 0x00000008U -/*CAN Loopback Control. 0 = Connect CAN inputs according to MIO mapping. 1 = Loop CAN 0 Tx to CAN 1 Rx, and CAN 1 Tx to CAN 0 R - .*/ +/* +* CAN Loopback Control. 0 = Connect CAN inputs according to MIO mapping. 1 + * = Loop CAN 0 Tx to CAN 1 Rx, and CAN 1 Tx to CAN 0 Rx. +*/ #undef IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_DEFVAL #undef IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_SHIFT #undef IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_MASK -#define IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_SHIFT 2 -#define IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_MASK 0x00000004U +#define IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_SHIFT 2 +#define IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_MASK 0x00000004U -/*UART Loopback Control. 0 = Connect UART inputs according to MIO mapping. 1 = Loop UART 0 outputs to UART 1 inputs, and UART 1 - outputs to UART 0 inputs. RXD/TXD cross-connected. RTS/CTS cross-connected. DSR, DTR, DCD and RI not used.*/ +/* +* UART Loopback Control. 0 = Connect UART inputs according to MIO mapping. + * 1 = Loop UART 0 outputs to UART 1 inputs, and UART 1 outputs to UART 0 + * inputs. RXD/TXD cross-connected. RTS/CTS cross-connected. DSR, DTR, DCD + * and RI not used. +*/ #undef IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_DEFVAL #undef IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_SHIFT #undef IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_MASK -#define IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_SHIFT 1 -#define IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_MASK 0x00000002U +#define IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_SHIFT 1 +#define IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_MASK 0x00000002U -/*SPI Loopback Control. 0 = Connect SPI inputs according to MIO mapping. 1 = Loop SPI 0 outputs to SPI 1 inputs, and SPI 1 outp - ts to SPI 0 inputs. The other SPI core will appear on the LS Slave Select.*/ +/* +* SPI Loopback Control. 0 = Connect SPI inputs according to MIO mapping. 1 + * = Loop SPI 0 outputs to SPI 1 inputs, and SPI 1 outputs to SPI 0 inputs + * . The other SPI core will appear on the LS Slave Select. +*/ #undef IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_DEFVAL #undef IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_SHIFT #undef IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_MASK -#define IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_SHIFT 0 -#define IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_MASK 0x00000001U +#define IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_SHIFT 0 +#define IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_MASK 0x00000001U +#undef CRF_APB_RST_FPD_TOP_OFFSET +#define CRF_APB_RST_FPD_TOP_OFFSET 0XFD1A0100 #undef CRL_APB_RST_LPD_IOU2_OFFSET #define CRL_APB_RST_LPD_IOU2_OFFSET 0XFF5E0238 +#undef CRL_APB_RST_LPD_TOP_OFFSET +#define CRL_APB_RST_LPD_TOP_OFFSET 0XFF5E023C #undef CRL_APB_RST_LPD_IOU0_OFFSET #define CRL_APB_RST_LPD_IOU0_OFFSET 0XFF5E0230 #undef CRL_APB_RST_LPD_IOU2_OFFSET @@ -24442,8 +31089,10 @@ #define IOU_SLCR_IOU_TAPDLY_BYPASS_OFFSET 0XFF180390 #undef CRL_APB_RST_LPD_TOP_OFFSET #define CRL_APB_RST_LPD_TOP_OFFSET 0XFF5E023C -#undef CRF_APB_RST_FPD_TOP_OFFSET -#define CRF_APB_RST_FPD_TOP_OFFSET 0XFD1A0100 +#undef USB3_0_FPD_POWER_PRSNT_OFFSET +#define USB3_0_FPD_POWER_PRSNT_OFFSET 0XFF9D0080 +#undef USB3_0_FPD_PIPE_CLK_OFFSET +#define USB3_0_FPD_PIPE_CLK_OFFSET 0XFF9D007C #undef CRL_APB_RST_LPD_IOU2_OFFSET #define CRL_APB_RST_LPD_IOU2_OFFSET 0XFF5E0238 #undef IOU_SLCR_CTRL_REG_SD_OFFSET @@ -24452,6 +31101,8 @@ #define IOU_SLCR_SD_CONFIG_REG2_OFFSET 0XFF180320 #undef IOU_SLCR_SD_CONFIG_REG1_OFFSET #define IOU_SLCR_SD_CONFIG_REG1_OFFSET 0XFF18031C +#undef IOU_SLCR_SD_DLL_CTRL_OFFSET +#define IOU_SLCR_SD_DLL_CTRL_OFFSET 0XFF180358 #undef IOU_SLCR_SD_CONFIG_REG3_OFFSET #define IOU_SLCR_SD_CONFIG_REG3_OFFSET 0XFF180324 #undef CRL_APB_RST_LPD_IOU2_OFFSET @@ -24480,6 +31131,8 @@ #define UART1_CONTROL_REG0_OFFSET 0XFF010000 #undef UART1_MODE_REG0_OFFSET #define UART1_MODE_REG0_OFFSET 0XFF010004 +#undef CRL_APB_RST_LPD_IOU2_OFFSET +#define CRL_APB_RST_LPD_IOU2_OFFSET 0XFF5E0238 #undef LPD_SLCR_SECURE_SLCR_ADMA_OFFSET #define LPD_SLCR_SECURE_SLCR_ADMA_OFFSET 0XFF4B0024 #undef CSU_TAMPER_STATUS_OFFSET @@ -24492,782 +31145,1656 @@ #define IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_OFFSET 0XFF260020 #undef IOU_SCNTRS_COUNTER_CONTROL_REGISTER_OFFSET #define IOU_SCNTRS_COUNTER_CONTROL_REGISTER_OFFSET 0XFF260000 +#undef GPIO_DIRM_1_OFFSET +#define GPIO_DIRM_1_OFFSET 0XFF0A0244 +#undef GPIO_OEN_1_OFFSET +#define GPIO_OEN_1_OFFSET 0XFF0A0248 +#undef GPIO_MASK_DATA_1_LSW_OFFSET +#define GPIO_MASK_DATA_1_LSW_OFFSET 0XFF0A0008 +#undef GPIO_MASK_DATA_1_LSW_OFFSET +#define GPIO_MASK_DATA_1_LSW_OFFSET 0XFF0A0008 -/*Block level reset*/ -#undef CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_DEFVAL -#undef CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_SHIFT -#undef CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_MASK -#define CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_DEFVAL 0x0017FFFF -#define CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_SHIFT 20 -#define CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_MASK 0x00100000U - -/*GEM 3 reset*/ -#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL -#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT -#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK -#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL 0x0000000F -#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT 3 -#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK 0x00000008U - -/*Block level reset*/ -#undef CRL_APB_RST_LPD_IOU2_QSPI_RESET_DEFVAL -#undef CRL_APB_RST_LPD_IOU2_QSPI_RESET_SHIFT -#undef CRL_APB_RST_LPD_IOU2_QSPI_RESET_MASK -#define CRL_APB_RST_LPD_IOU2_QSPI_RESET_DEFVAL 0x0017FFFF -#define CRL_APB_RST_LPD_IOU2_QSPI_RESET_SHIFT 0 -#define CRL_APB_RST_LPD_IOU2_QSPI_RESET_MASK 0x00000001U - -/*0: Do not by pass the tap delays on the Rx clock signal of LQSPI 1: Bypass the Tap delay on the Rx clock signal of LQSPI*/ -#undef IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_DEFVAL -#undef IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_SHIFT -#undef IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_MASK -#define IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_DEFVAL 0x00000007 -#define IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_SHIFT 2 -#define IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_MASK 0x00000004U - -/*USB 0 reset for control registers*/ -#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL -#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT -#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK -#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL 0x00188FDF -#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT 10 -#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK 0x00000400U - -/*USB 0 sleep circuit reset*/ -#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL -#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT -#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK -#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL 0x00188FDF -#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT 8 -#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK 0x00000100U - -/*USB 0 reset*/ -#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL -#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT -#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK -#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL 0x00188FDF -#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT 6 -#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK 0x00000040U - -/*PCIE config reset*/ +/* +* PCIE config reset +*/ #undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL #undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT #undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK -#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL 0x000F9FFE -#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT 19 -#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK 0x00080000U +#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT 19 +#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK 0x00080000U -/*PCIE control block level reset*/ +/* +* PCIE control block level reset +*/ #undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL #undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT #undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK -#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL 0x000F9FFE -#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT 17 -#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK 0x00020000U +#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT 17 +#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK 0x00020000U -/*PCIE bridge block level reset (AXI interface)*/ +/* +* PCIE bridge block level reset (AXI interface) +*/ #undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL #undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT #undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK -#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL 0x000F9FFE -#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT 18 -#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK 0x00040000U +#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT 18 +#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK 0x00040000U -/*Display Port block level reset (includes DPDMA)*/ +/* +* Display Port block level reset (includes DPDMA) +*/ #undef CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL #undef CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT #undef CRF_APB_RST_FPD_TOP_DP_RESET_MASK -#define CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL 0x000F9FFE -#define CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT 16 -#define CRF_APB_RST_FPD_TOP_DP_RESET_MASK 0x00010000U +#define CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT 16 +#define CRF_APB_RST_FPD_TOP_DP_RESET_MASK 0x00010000U -/*FPD WDT reset*/ +/* +* FPD WDT reset +*/ #undef CRF_APB_RST_FPD_TOP_SWDT_RESET_DEFVAL #undef CRF_APB_RST_FPD_TOP_SWDT_RESET_SHIFT #undef CRF_APB_RST_FPD_TOP_SWDT_RESET_MASK -#define CRF_APB_RST_FPD_TOP_SWDT_RESET_DEFVAL 0x000F9FFE -#define CRF_APB_RST_FPD_TOP_SWDT_RESET_SHIFT 15 -#define CRF_APB_RST_FPD_TOP_SWDT_RESET_MASK 0x00008000U +#define CRF_APB_RST_FPD_TOP_SWDT_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_SWDT_RESET_SHIFT 15 +#define CRF_APB_RST_FPD_TOP_SWDT_RESET_MASK 0x00008000U -/*GDMA block level reset*/ +/* +* GDMA block level reset +*/ #undef CRF_APB_RST_FPD_TOP_GDMA_RESET_DEFVAL #undef CRF_APB_RST_FPD_TOP_GDMA_RESET_SHIFT #undef CRF_APB_RST_FPD_TOP_GDMA_RESET_MASK -#define CRF_APB_RST_FPD_TOP_GDMA_RESET_DEFVAL 0x000F9FFE -#define CRF_APB_RST_FPD_TOP_GDMA_RESET_SHIFT 6 -#define CRF_APB_RST_FPD_TOP_GDMA_RESET_MASK 0x00000040U +#define CRF_APB_RST_FPD_TOP_GDMA_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_GDMA_RESET_SHIFT 6 +#define CRF_APB_RST_FPD_TOP_GDMA_RESET_MASK 0x00000040U -/*Pixel Processor (submodule of GPU) block level reset*/ +/* +* Pixel Processor (submodule of GPU) block level reset +*/ #undef CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_DEFVAL #undef CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_SHIFT #undef CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_MASK -#define CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_DEFVAL 0x000F9FFE -#define CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_SHIFT 4 -#define CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_MASK 0x00000010U +#define CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_SHIFT 4 +#define CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_MASK 0x00000010U -/*Pixel Processor (submodule of GPU) block level reset*/ +/* +* Pixel Processor (submodule of GPU) block level reset +*/ #undef CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_DEFVAL #undef CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_SHIFT #undef CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_MASK -#define CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_DEFVAL 0x000F9FFE -#define CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_SHIFT 5 -#define CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_MASK 0x00000020U +#define CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_SHIFT 5 +#define CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_MASK 0x00000020U -/*GPU block level reset*/ +/* +* GPU block level reset +*/ #undef CRF_APB_RST_FPD_TOP_GPU_RESET_DEFVAL #undef CRF_APB_RST_FPD_TOP_GPU_RESET_SHIFT #undef CRF_APB_RST_FPD_TOP_GPU_RESET_MASK -#define CRF_APB_RST_FPD_TOP_GPU_RESET_DEFVAL 0x000F9FFE -#define CRF_APB_RST_FPD_TOP_GPU_RESET_SHIFT 3 -#define CRF_APB_RST_FPD_TOP_GPU_RESET_MASK 0x00000008U +#define CRF_APB_RST_FPD_TOP_GPU_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_GPU_RESET_SHIFT 3 +#define CRF_APB_RST_FPD_TOP_GPU_RESET_MASK 0x00000008U -/*GT block level reset*/ +/* +* GT block level reset +*/ #undef CRF_APB_RST_FPD_TOP_GT_RESET_DEFVAL #undef CRF_APB_RST_FPD_TOP_GT_RESET_SHIFT #undef CRF_APB_RST_FPD_TOP_GT_RESET_MASK -#define CRF_APB_RST_FPD_TOP_GT_RESET_DEFVAL 0x000F9FFE -#define CRF_APB_RST_FPD_TOP_GT_RESET_SHIFT 2 -#define CRF_APB_RST_FPD_TOP_GT_RESET_MASK 0x00000004U +#define CRF_APB_RST_FPD_TOP_GT_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_GT_RESET_SHIFT 2 +#define CRF_APB_RST_FPD_TOP_GT_RESET_MASK 0x00000004U -/*Sata block level reset*/ +/* +* Sata block level reset +*/ #undef CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL #undef CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT #undef CRF_APB_RST_FPD_TOP_SATA_RESET_MASK -#define CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL 0x000F9FFE -#define CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT 1 -#define CRF_APB_RST_FPD_TOP_SATA_RESET_MASK 0x00000002U +#define CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT 1 +#define CRF_APB_RST_FPD_TOP_SATA_RESET_MASK 0x00000002U -/*Block level reset*/ +/* +* Block level reset +*/ +#undef CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_DEFVAL +#undef CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_SHIFT +#undef CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_MASK +#define CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_SHIFT 20 +#define CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_MASK 0x00100000U + +/* +* Block level reset +*/ +#undef CRL_APB_RST_LPD_IOU2_IOU_CC_RESET_DEFVAL +#undef CRL_APB_RST_LPD_IOU2_IOU_CC_RESET_SHIFT +#undef CRL_APB_RST_LPD_IOU2_IOU_CC_RESET_MASK +#define CRL_APB_RST_LPD_IOU2_IOU_CC_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_IOU_CC_RESET_SHIFT 19 +#define CRL_APB_RST_LPD_IOU2_IOU_CC_RESET_MASK 0x00080000U + +/* +* Block level reset +*/ +#undef CRL_APB_RST_LPD_IOU2_ADMA_RESET_DEFVAL +#undef CRL_APB_RST_LPD_IOU2_ADMA_RESET_SHIFT +#undef CRL_APB_RST_LPD_IOU2_ADMA_RESET_MASK +#define CRL_APB_RST_LPD_IOU2_ADMA_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_ADMA_RESET_SHIFT 17 +#define CRL_APB_RST_LPD_IOU2_ADMA_RESET_MASK 0x00020000U + +/* +* Reset entire full power domain. +*/ +#undef CRL_APB_RST_LPD_TOP_FPD_RESET_DEFVAL +#undef CRL_APB_RST_LPD_TOP_FPD_RESET_SHIFT +#undef CRL_APB_RST_LPD_TOP_FPD_RESET_MASK +#define CRL_APB_RST_LPD_TOP_FPD_RESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_FPD_RESET_SHIFT 23 +#define CRL_APB_RST_LPD_TOP_FPD_RESET_MASK 0x00800000U + +/* +* LPD SWDT +*/ +#undef CRL_APB_RST_LPD_TOP_LPD_SWDT_RESET_DEFVAL +#undef CRL_APB_RST_LPD_TOP_LPD_SWDT_RESET_SHIFT +#undef CRL_APB_RST_LPD_TOP_LPD_SWDT_RESET_MASK +#define CRL_APB_RST_LPD_TOP_LPD_SWDT_RESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_LPD_SWDT_RESET_SHIFT 20 +#define CRL_APB_RST_LPD_TOP_LPD_SWDT_RESET_MASK 0x00100000U + +/* +* Sysmonitor reset +*/ +#undef CRL_APB_RST_LPD_TOP_SYSMON_RESET_DEFVAL +#undef CRL_APB_RST_LPD_TOP_SYSMON_RESET_SHIFT +#undef CRL_APB_RST_LPD_TOP_SYSMON_RESET_MASK +#define CRL_APB_RST_LPD_TOP_SYSMON_RESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_SYSMON_RESET_SHIFT 17 +#define CRL_APB_RST_LPD_TOP_SYSMON_RESET_MASK 0x00020000U + +/* +* Real Time Clock reset +*/ +#undef CRL_APB_RST_LPD_TOP_RTC_RESET_DEFVAL +#undef CRL_APB_RST_LPD_TOP_RTC_RESET_SHIFT +#undef CRL_APB_RST_LPD_TOP_RTC_RESET_MASK +#define CRL_APB_RST_LPD_TOP_RTC_RESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_RTC_RESET_SHIFT 16 +#define CRL_APB_RST_LPD_TOP_RTC_RESET_MASK 0x00010000U + +/* +* APM reset +*/ +#undef CRL_APB_RST_LPD_TOP_APM_RESET_DEFVAL +#undef CRL_APB_RST_LPD_TOP_APM_RESET_SHIFT +#undef CRL_APB_RST_LPD_TOP_APM_RESET_MASK +#define CRL_APB_RST_LPD_TOP_APM_RESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_APM_RESET_SHIFT 15 +#define CRL_APB_RST_LPD_TOP_APM_RESET_MASK 0x00008000U + +/* +* IPI reset +*/ +#undef CRL_APB_RST_LPD_TOP_IPI_RESET_DEFVAL +#undef CRL_APB_RST_LPD_TOP_IPI_RESET_SHIFT +#undef CRL_APB_RST_LPD_TOP_IPI_RESET_MASK +#define CRL_APB_RST_LPD_TOP_IPI_RESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_IPI_RESET_SHIFT 14 +#define CRL_APB_RST_LPD_TOP_IPI_RESET_MASK 0x00004000U + +/* +* reset entire RPU power island +*/ +#undef CRL_APB_RST_LPD_TOP_RPU_PGE_RESET_DEFVAL +#undef CRL_APB_RST_LPD_TOP_RPU_PGE_RESET_SHIFT +#undef CRL_APB_RST_LPD_TOP_RPU_PGE_RESET_MASK +#define CRL_APB_RST_LPD_TOP_RPU_PGE_RESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_RPU_PGE_RESET_SHIFT 4 +#define CRL_APB_RST_LPD_TOP_RPU_PGE_RESET_MASK 0x00000010U + +/* +* reset ocm +*/ +#undef CRL_APB_RST_LPD_TOP_OCM_RESET_DEFVAL +#undef CRL_APB_RST_LPD_TOP_OCM_RESET_SHIFT +#undef CRL_APB_RST_LPD_TOP_OCM_RESET_MASK +#define CRL_APB_RST_LPD_TOP_OCM_RESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_OCM_RESET_SHIFT 3 +#define CRL_APB_RST_LPD_TOP_OCM_RESET_MASK 0x00000008U + +/* +* GEM 3 reset +*/ +#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL +#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT +#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK +#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL 0x0000000F +#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT 3 +#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK 0x00000008U + +/* +* Block level reset +*/ +#undef CRL_APB_RST_LPD_IOU2_QSPI_RESET_DEFVAL +#undef CRL_APB_RST_LPD_IOU2_QSPI_RESET_SHIFT +#undef CRL_APB_RST_LPD_IOU2_QSPI_RESET_MASK +#define CRL_APB_RST_LPD_IOU2_QSPI_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_QSPI_RESET_SHIFT 0 +#define CRL_APB_RST_LPD_IOU2_QSPI_RESET_MASK 0x00000001U + +/* +* 0: Do not by pass the tap delays on the Rx clock signal of LQSPI 1: Bypa + * ss the Tap delay on the Rx clock signal of LQSPI +*/ +#undef IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_DEFVAL +#undef IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_SHIFT +#undef IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_MASK +#define IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_DEFVAL 0x00000007 +#define IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_SHIFT 2 +#define IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_MASK 0x00000004U + +/* +* USB 0 reset for control registers +*/ +#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL +#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT +#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK +#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT 10 +#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK 0x00000400U + +/* +* USB 0 sleep circuit reset +*/ +#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL +#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT +#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK +#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT 8 +#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK 0x00000100U + +/* +* USB 0 reset +*/ +#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL +#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT +#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK +#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT 6 +#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK 0x00000040U + +/* +* This bit is used to choose between PIPE power present and 1'b1 +*/ +#undef USB3_0_FPD_POWER_PRSNT_OPTION_DEFVAL +#undef USB3_0_FPD_POWER_PRSNT_OPTION_SHIFT +#undef USB3_0_FPD_POWER_PRSNT_OPTION_MASK +#define USB3_0_FPD_POWER_PRSNT_OPTION_DEFVAL +#define USB3_0_FPD_POWER_PRSNT_OPTION_SHIFT 0 +#define USB3_0_FPD_POWER_PRSNT_OPTION_MASK 0x00000001U + +/* +* This bit is used to choose between PIPE clock coming from SerDes and the + * suspend clk +*/ +#undef USB3_0_FPD_PIPE_CLK_OPTION_DEFVAL +#undef USB3_0_FPD_PIPE_CLK_OPTION_SHIFT +#undef USB3_0_FPD_PIPE_CLK_OPTION_MASK +#define USB3_0_FPD_PIPE_CLK_OPTION_DEFVAL +#define USB3_0_FPD_PIPE_CLK_OPTION_SHIFT 0 +#define USB3_0_FPD_PIPE_CLK_OPTION_MASK 0x00000001U + +/* +* Block level reset +*/ #undef CRL_APB_RST_LPD_IOU2_SDIO1_RESET_DEFVAL #undef CRL_APB_RST_LPD_IOU2_SDIO1_RESET_SHIFT #undef CRL_APB_RST_LPD_IOU2_SDIO1_RESET_MASK -#define CRL_APB_RST_LPD_IOU2_SDIO1_RESET_DEFVAL 0x0017FFFF -#define CRL_APB_RST_LPD_IOU2_SDIO1_RESET_SHIFT 6 -#define CRL_APB_RST_LPD_IOU2_SDIO1_RESET_MASK 0x00000040U +#define CRL_APB_RST_LPD_IOU2_SDIO1_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_SDIO1_RESET_SHIFT 6 +#define CRL_APB_RST_LPD_IOU2_SDIO1_RESET_MASK 0x00000040U -/*SD or eMMC selection on SDIO1 0: SD enabled 1: eMMC enabled*/ +/* +* SD or eMMC selection on SDIO1 0: SD enabled 1: eMMC enabled +*/ #undef IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_DEFVAL #undef IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_SHIFT #undef IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_MASK -#define IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_SHIFT 15 -#define IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_MASK 0x00008000U +#define IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_SHIFT 15 +#define IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_MASK 0x00008000U -/*Should be set based on the final product usage 00 - Removable SCard Slot 01 - Embedded Slot for One Device 10 - Shared Bus Sl - t 11 - Reserved*/ +/* +* Should be set based on the final product usage 00 - Removable SCard Slot + * 01 - Embedded Slot for One Device 10 - Shared Bus Slot 11 - Reserved +*/ #undef IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_DEFVAL #undef IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_SHIFT #undef IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_MASK -#define IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_DEFVAL 0x0FFC0FFC -#define IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_SHIFT 28 -#define IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_MASK 0x30000000U +#define IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_DEFVAL 0x0FFC0FFC +#define IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_SHIFT 28 +#define IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_MASK 0x30000000U -/*1.8V Support 1: 1.8V supported 0: 1.8V not supported support*/ +/* +* 1.8V Support 1: 1.8V supported 0: 1.8V not supported support +*/ #undef IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_DEFVAL #undef IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_SHIFT #undef IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_MASK -#define IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_DEFVAL 0x0FFC0FFC -#define IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_SHIFT 25 -#define IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_MASK 0x02000000U +#define IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_DEFVAL 0x0FFC0FFC +#define IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_SHIFT 25 +#define IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_MASK 0x02000000U -/*3.0V Support 1: 3.0V supported 0: 3.0V not supported support*/ +/* +* 3.0V Support 1: 3.0V supported 0: 3.0V not supported support +*/ #undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_DEFVAL #undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_SHIFT #undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_MASK -#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_DEFVAL 0x0FFC0FFC -#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_SHIFT 24 -#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_MASK 0x01000000U +#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_DEFVAL 0x0FFC0FFC +#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_SHIFT 24 +#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_MASK 0x01000000U -/*3.3V Support 1: 3.3V supported 0: 3.3V not supported support*/ +/* +* 3.3V Support 1: 3.3V supported 0: 3.3V not supported support +*/ #undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_DEFVAL #undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_SHIFT #undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_MASK -#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_DEFVAL 0x0FFC0FFC -#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_SHIFT 23 -#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_MASK 0x00800000U +#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_DEFVAL 0x0FFC0FFC +#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_SHIFT 23 +#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_MASK 0x00800000U -/*Base Clock Frequency for SD Clock. This is the frequency of the xin_clk.*/ +/* +* Base Clock Frequency for SD Clock. This is the frequency of the xin_clk. +*/ #undef IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_DEFVAL #undef IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_SHIFT #undef IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_MASK -#define IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_DEFVAL 0x32403240 -#define IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_SHIFT 23 -#define IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_MASK 0x7F800000U +#define IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_DEFVAL 0x32403240 +#define IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_SHIFT 23 +#define IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_MASK 0x7F800000U -/*This is the Timer Count for Re-Tuning Timer for Re-Tuning Mode 1 to 3. Setting to 4'b0 disables Re-Tuning Timer. 0h - Get inf - rmation via other source 1h = 1 seconds 2h = 2 seconds 3h = 4 seconds 4h = 8 seconds -- n = 2(n-1) seconds -- Bh = 1024 secon - s Fh - Ch = Reserved*/ +/* +* Configures the Number of Taps (Phases) of the rxclk_in that is supported + * . +*/ +#undef IOU_SLCR_SD_CONFIG_REG1_SD1_TUNIGCOUNT_DEFVAL +#undef IOU_SLCR_SD_CONFIG_REG1_SD1_TUNIGCOUNT_SHIFT +#undef IOU_SLCR_SD_CONFIG_REG1_SD1_TUNIGCOUNT_MASK +#define IOU_SLCR_SD_CONFIG_REG1_SD1_TUNIGCOUNT_DEFVAL 0x32403240 +#define IOU_SLCR_SD_CONFIG_REG1_SD1_TUNIGCOUNT_SHIFT 17 +#define IOU_SLCR_SD_CONFIG_REG1_SD1_TUNIGCOUNT_MASK 0x007E0000U + +/* +* Reserved. +*/ +#undef IOU_SLCR_SD_DLL_CTRL_RESERVED_DEFVAL +#undef IOU_SLCR_SD_DLL_CTRL_RESERVED_SHIFT +#undef IOU_SLCR_SD_DLL_CTRL_RESERVED_MASK +#define IOU_SLCR_SD_DLL_CTRL_RESERVED_DEFVAL 0x00080008 +#define IOU_SLCR_SD_DLL_CTRL_RESERVED_SHIFT 3 +#define IOU_SLCR_SD_DLL_CTRL_RESERVED_MASK 0x00000008U + +/* +* This is the Timer Count for Re-Tuning Timer for Re-Tuning Mode 1 to 3. S + * etting to 4'b0 disables Re-Tuning Timer. 0h - Get information via other + * source 1h = 1 seconds 2h = 2 seconds 3h = 4 seconds 4h = 8 seconds -- n + * = 2(n-1) seconds -- Bh = 1024 seconds Fh - Ch = Reserved +*/ #undef IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_DEFVAL #undef IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_SHIFT #undef IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_MASK -#define IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_DEFVAL 0x06070607 -#define IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_SHIFT 22 -#define IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_MASK 0x03C00000U +#define IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_DEFVAL 0x06070607 +#define IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_SHIFT 22 +#define IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_MASK 0x03C00000U -/*Block level reset*/ +/* +* Block level reset +*/ #undef CRL_APB_RST_LPD_IOU2_CAN1_RESET_DEFVAL #undef CRL_APB_RST_LPD_IOU2_CAN1_RESET_SHIFT #undef CRL_APB_RST_LPD_IOU2_CAN1_RESET_MASK -#define CRL_APB_RST_LPD_IOU2_CAN1_RESET_DEFVAL 0x0017FFFF -#define CRL_APB_RST_LPD_IOU2_CAN1_RESET_SHIFT 8 -#define CRL_APB_RST_LPD_IOU2_CAN1_RESET_MASK 0x00000100U +#define CRL_APB_RST_LPD_IOU2_CAN1_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_CAN1_RESET_SHIFT 8 +#define CRL_APB_RST_LPD_IOU2_CAN1_RESET_MASK 0x00000100U -/*Block level reset*/ +/* +* Block level reset +*/ #undef CRL_APB_RST_LPD_IOU2_I2C0_RESET_DEFVAL #undef CRL_APB_RST_LPD_IOU2_I2C0_RESET_SHIFT #undef CRL_APB_RST_LPD_IOU2_I2C0_RESET_MASK -#define CRL_APB_RST_LPD_IOU2_I2C0_RESET_DEFVAL 0x0017FFFF -#define CRL_APB_RST_LPD_IOU2_I2C0_RESET_SHIFT 9 -#define CRL_APB_RST_LPD_IOU2_I2C0_RESET_MASK 0x00000200U +#define CRL_APB_RST_LPD_IOU2_I2C0_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_I2C0_RESET_SHIFT 9 +#define CRL_APB_RST_LPD_IOU2_I2C0_RESET_MASK 0x00000200U -/*Block level reset*/ +/* +* Block level reset +*/ #undef CRL_APB_RST_LPD_IOU2_I2C1_RESET_DEFVAL #undef CRL_APB_RST_LPD_IOU2_I2C1_RESET_SHIFT #undef CRL_APB_RST_LPD_IOU2_I2C1_RESET_MASK -#define CRL_APB_RST_LPD_IOU2_I2C1_RESET_DEFVAL 0x0017FFFF -#define CRL_APB_RST_LPD_IOU2_I2C1_RESET_SHIFT 10 -#define CRL_APB_RST_LPD_IOU2_I2C1_RESET_MASK 0x00000400U +#define CRL_APB_RST_LPD_IOU2_I2C1_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_I2C1_RESET_SHIFT 10 +#define CRL_APB_RST_LPD_IOU2_I2C1_RESET_MASK 0x00000400U -/*Block level reset*/ +/* +* Block level reset +*/ #undef CRL_APB_RST_LPD_IOU2_SWDT_RESET_DEFVAL #undef CRL_APB_RST_LPD_IOU2_SWDT_RESET_SHIFT #undef CRL_APB_RST_LPD_IOU2_SWDT_RESET_MASK -#define CRL_APB_RST_LPD_IOU2_SWDT_RESET_DEFVAL 0x0017FFFF -#define CRL_APB_RST_LPD_IOU2_SWDT_RESET_SHIFT 15 -#define CRL_APB_RST_LPD_IOU2_SWDT_RESET_MASK 0x00008000U +#define CRL_APB_RST_LPD_IOU2_SWDT_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_SWDT_RESET_SHIFT 15 +#define CRL_APB_RST_LPD_IOU2_SWDT_RESET_MASK 0x00008000U -/*Block level reset*/ +/* +* Block level reset +*/ #undef CRL_APB_RST_LPD_IOU2_TTC0_RESET_DEFVAL #undef CRL_APB_RST_LPD_IOU2_TTC0_RESET_SHIFT #undef CRL_APB_RST_LPD_IOU2_TTC0_RESET_MASK -#define CRL_APB_RST_LPD_IOU2_TTC0_RESET_DEFVAL 0x0017FFFF -#define CRL_APB_RST_LPD_IOU2_TTC0_RESET_SHIFT 11 -#define CRL_APB_RST_LPD_IOU2_TTC0_RESET_MASK 0x00000800U +#define CRL_APB_RST_LPD_IOU2_TTC0_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_TTC0_RESET_SHIFT 11 +#define CRL_APB_RST_LPD_IOU2_TTC0_RESET_MASK 0x00000800U -/*Block level reset*/ +/* +* Block level reset +*/ #undef CRL_APB_RST_LPD_IOU2_TTC1_RESET_DEFVAL #undef CRL_APB_RST_LPD_IOU2_TTC1_RESET_SHIFT #undef CRL_APB_RST_LPD_IOU2_TTC1_RESET_MASK -#define CRL_APB_RST_LPD_IOU2_TTC1_RESET_DEFVAL 0x0017FFFF -#define CRL_APB_RST_LPD_IOU2_TTC1_RESET_SHIFT 12 -#define CRL_APB_RST_LPD_IOU2_TTC1_RESET_MASK 0x00001000U +#define CRL_APB_RST_LPD_IOU2_TTC1_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_TTC1_RESET_SHIFT 12 +#define CRL_APB_RST_LPD_IOU2_TTC1_RESET_MASK 0x00001000U -/*Block level reset*/ +/* +* Block level reset +*/ #undef CRL_APB_RST_LPD_IOU2_TTC2_RESET_DEFVAL #undef CRL_APB_RST_LPD_IOU2_TTC2_RESET_SHIFT #undef CRL_APB_RST_LPD_IOU2_TTC2_RESET_MASK -#define CRL_APB_RST_LPD_IOU2_TTC2_RESET_DEFVAL 0x0017FFFF -#define CRL_APB_RST_LPD_IOU2_TTC2_RESET_SHIFT 13 -#define CRL_APB_RST_LPD_IOU2_TTC2_RESET_MASK 0x00002000U +#define CRL_APB_RST_LPD_IOU2_TTC2_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_TTC2_RESET_SHIFT 13 +#define CRL_APB_RST_LPD_IOU2_TTC2_RESET_MASK 0x00002000U -/*Block level reset*/ +/* +* Block level reset +*/ #undef CRL_APB_RST_LPD_IOU2_TTC3_RESET_DEFVAL #undef CRL_APB_RST_LPD_IOU2_TTC3_RESET_SHIFT #undef CRL_APB_RST_LPD_IOU2_TTC3_RESET_MASK -#define CRL_APB_RST_LPD_IOU2_TTC3_RESET_DEFVAL 0x0017FFFF -#define CRL_APB_RST_LPD_IOU2_TTC3_RESET_SHIFT 14 -#define CRL_APB_RST_LPD_IOU2_TTC3_RESET_MASK 0x00004000U +#define CRL_APB_RST_LPD_IOU2_TTC3_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_TTC3_RESET_SHIFT 14 +#define CRL_APB_RST_LPD_IOU2_TTC3_RESET_MASK 0x00004000U -/*Block level reset*/ +/* +* Block level reset +*/ #undef CRL_APB_RST_LPD_IOU2_UART0_RESET_DEFVAL #undef CRL_APB_RST_LPD_IOU2_UART0_RESET_SHIFT #undef CRL_APB_RST_LPD_IOU2_UART0_RESET_MASK -#define CRL_APB_RST_LPD_IOU2_UART0_RESET_DEFVAL 0x0017FFFF -#define CRL_APB_RST_LPD_IOU2_UART0_RESET_SHIFT 1 -#define CRL_APB_RST_LPD_IOU2_UART0_RESET_MASK 0x00000002U +#define CRL_APB_RST_LPD_IOU2_UART0_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_UART0_RESET_SHIFT 1 +#define CRL_APB_RST_LPD_IOU2_UART0_RESET_MASK 0x00000002U -/*Block level reset*/ +/* +* Block level reset +*/ #undef CRL_APB_RST_LPD_IOU2_UART1_RESET_DEFVAL #undef CRL_APB_RST_LPD_IOU2_UART1_RESET_SHIFT #undef CRL_APB_RST_LPD_IOU2_UART1_RESET_MASK -#define CRL_APB_RST_LPD_IOU2_UART1_RESET_DEFVAL 0x0017FFFF -#define CRL_APB_RST_LPD_IOU2_UART1_RESET_SHIFT 2 -#define CRL_APB_RST_LPD_IOU2_UART1_RESET_MASK 0x00000004U +#define CRL_APB_RST_LPD_IOU2_UART1_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_UART1_RESET_SHIFT 2 +#define CRL_APB_RST_LPD_IOU2_UART1_RESET_MASK 0x00000004U -/*Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate*/ +/* +* Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate +*/ #undef UART0_BAUD_RATE_DIVIDER_REG0_BDIV_DEFVAL #undef UART0_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT #undef UART0_BAUD_RATE_DIVIDER_REG0_BDIV_MASK -#define UART0_BAUD_RATE_DIVIDER_REG0_BDIV_DEFVAL 0x0000000F -#define UART0_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT 0 -#define UART0_BAUD_RATE_DIVIDER_REG0_BDIV_MASK 0x000000FFU +#define UART0_BAUD_RATE_DIVIDER_REG0_BDIV_DEFVAL 0x0000000F +#define UART0_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT 0 +#define UART0_BAUD_RATE_DIVIDER_REG0_BDIV_MASK 0x000000FFU -/*Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample*/ +/* +* Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor + * bypass (baud_sample = sel_clk) 2 - 65535: baud_sample +*/ #undef UART0_BAUD_RATE_GEN_REG0_CD_DEFVAL #undef UART0_BAUD_RATE_GEN_REG0_CD_SHIFT #undef UART0_BAUD_RATE_GEN_REG0_CD_MASK -#define UART0_BAUD_RATE_GEN_REG0_CD_DEFVAL 0x0000028B -#define UART0_BAUD_RATE_GEN_REG0_CD_SHIFT 0 -#define UART0_BAUD_RATE_GEN_REG0_CD_MASK 0x0000FFFFU +#define UART0_BAUD_RATE_GEN_REG0_CD_DEFVAL 0x0000028B +#define UART0_BAUD_RATE_GEN_REG0_CD_SHIFT 0 +#define UART0_BAUD_RATE_GEN_REG0_CD_MASK 0x0000FFFFU -/*Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a - high level during 12 bit periods. It can be set regardless of the value of STTBRK.*/ +/* +* Stop transmitter break: 0: no affect 1: stop transmission of the break a + * fter a minimum of one character length and transmit a high level during + * 12 bit periods. It can be set regardless of the value of STTBRK. +*/ #undef UART0_CONTROL_REG0_STPBRK_DEFVAL #undef UART0_CONTROL_REG0_STPBRK_SHIFT #undef UART0_CONTROL_REG0_STPBRK_MASK -#define UART0_CONTROL_REG0_STPBRK_DEFVAL 0x00000128 -#define UART0_CONTROL_REG0_STPBRK_SHIFT 8 -#define UART0_CONTROL_REG0_STPBRK_MASK 0x00000100U +#define UART0_CONTROL_REG0_STPBRK_DEFVAL 0x00000128 +#define UART0_CONTROL_REG0_STPBRK_SHIFT 8 +#define UART0_CONTROL_REG0_STPBRK_MASK 0x00000100U -/*Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the - transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high.*/ +/* +* Start transmitter break: 0: no affect 1: start to transmit a break after + * the characters currently present in the FIFO and the transmit shift reg + * ister have been transmitted. It can only be set if STPBRK (Stop transmit + * ter break) is not high. +*/ #undef UART0_CONTROL_REG0_STTBRK_DEFVAL #undef UART0_CONTROL_REG0_STTBRK_SHIFT #undef UART0_CONTROL_REG0_STTBRK_MASK -#define UART0_CONTROL_REG0_STTBRK_DEFVAL 0x00000128 -#define UART0_CONTROL_REG0_STTBRK_SHIFT 7 -#define UART0_CONTROL_REG0_STTBRK_MASK 0x00000080U +#define UART0_CONTROL_REG0_STTBRK_DEFVAL 0x00000128 +#define UART0_CONTROL_REG0_STTBRK_SHIFT 7 +#define UART0_CONTROL_REG0_STTBRK_MASK 0x00000080U -/*Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has co - pleted.*/ +/* +* Restart receiver timeout counter: 1: receiver timeout counter is restart + * ed. This bit is self clearing once the restart has completed. +*/ #undef UART0_CONTROL_REG0_RSTTO_DEFVAL #undef UART0_CONTROL_REG0_RSTTO_SHIFT #undef UART0_CONTROL_REG0_RSTTO_MASK -#define UART0_CONTROL_REG0_RSTTO_DEFVAL 0x00000128 -#define UART0_CONTROL_REG0_RSTTO_SHIFT 6 -#define UART0_CONTROL_REG0_RSTTO_MASK 0x00000040U +#define UART0_CONTROL_REG0_RSTTO_DEFVAL 0x00000128 +#define UART0_CONTROL_REG0_RSTTO_SHIFT 6 +#define UART0_CONTROL_REG0_RSTTO_MASK 0x00000040U -/*Transmit disable: 0: enable transmitter 1: disable transmitter*/ +/* +* Transmit disable: 0: enable transmitter 1: disable transmitter +*/ #undef UART0_CONTROL_REG0_TXDIS_DEFVAL #undef UART0_CONTROL_REG0_TXDIS_SHIFT #undef UART0_CONTROL_REG0_TXDIS_MASK -#define UART0_CONTROL_REG0_TXDIS_DEFVAL 0x00000128 -#define UART0_CONTROL_REG0_TXDIS_SHIFT 5 -#define UART0_CONTROL_REG0_TXDIS_MASK 0x00000020U +#define UART0_CONTROL_REG0_TXDIS_DEFVAL 0x00000128 +#define UART0_CONTROL_REG0_TXDIS_SHIFT 5 +#define UART0_CONTROL_REG0_TXDIS_MASK 0x00000020U -/*Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0.*/ +/* +* Transmit enable: 0: disable transmitter 1: enable transmitter, provided + * the TXDIS field is set to 0. +*/ #undef UART0_CONTROL_REG0_TXEN_DEFVAL #undef UART0_CONTROL_REG0_TXEN_SHIFT #undef UART0_CONTROL_REG0_TXEN_MASK -#define UART0_CONTROL_REG0_TXEN_DEFVAL 0x00000128 -#define UART0_CONTROL_REG0_TXEN_SHIFT 4 -#define UART0_CONTROL_REG0_TXEN_MASK 0x00000010U +#define UART0_CONTROL_REG0_TXEN_DEFVAL 0x00000128 +#define UART0_CONTROL_REG0_TXEN_SHIFT 4 +#define UART0_CONTROL_REG0_TXEN_MASK 0x00000010U -/*Receive disable: 0: enable 1: disable, regardless of the value of RXEN*/ +/* +* Receive disable: 0: enable 1: disable, regardless of the value of RXEN +*/ #undef UART0_CONTROL_REG0_RXDIS_DEFVAL #undef UART0_CONTROL_REG0_RXDIS_SHIFT #undef UART0_CONTROL_REG0_RXDIS_MASK -#define UART0_CONTROL_REG0_RXDIS_DEFVAL 0x00000128 -#define UART0_CONTROL_REG0_RXDIS_SHIFT 3 -#define UART0_CONTROL_REG0_RXDIS_MASK 0x00000008U +#define UART0_CONTROL_REG0_RXDIS_DEFVAL 0x00000128 +#define UART0_CONTROL_REG0_RXDIS_SHIFT 3 +#define UART0_CONTROL_REG0_RXDIS_MASK 0x00000008U -/*Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero.*/ +/* +* Receive enable: 0: disable 1: enable When set to one, the receiver logic + * is enabled, provided the RXDIS field is set to zero. +*/ #undef UART0_CONTROL_REG0_RXEN_DEFVAL #undef UART0_CONTROL_REG0_RXEN_SHIFT #undef UART0_CONTROL_REG0_RXEN_MASK -#define UART0_CONTROL_REG0_RXEN_DEFVAL 0x00000128 -#define UART0_CONTROL_REG0_RXEN_SHIFT 2 -#define UART0_CONTROL_REG0_RXEN_MASK 0x00000004U +#define UART0_CONTROL_REG0_RXEN_DEFVAL 0x00000128 +#define UART0_CONTROL_REG0_RXEN_SHIFT 2 +#define UART0_CONTROL_REG0_RXEN_MASK 0x00000004U -/*Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded Thi - bit is self clearing once the reset has completed.*/ +/* +* Software reset for Tx data path: 0: no affect 1: transmitter logic is re + * set and all pending transmitter data is discarded This bit is self clear + * ing once the reset has completed. +*/ #undef UART0_CONTROL_REG0_TXRES_DEFVAL #undef UART0_CONTROL_REG0_TXRES_SHIFT #undef UART0_CONTROL_REG0_TXRES_MASK -#define UART0_CONTROL_REG0_TXRES_DEFVAL 0x00000128 -#define UART0_CONTROL_REG0_TXRES_SHIFT 1 -#define UART0_CONTROL_REG0_TXRES_MASK 0x00000002U +#define UART0_CONTROL_REG0_TXRES_DEFVAL 0x00000128 +#define UART0_CONTROL_REG0_TXRES_SHIFT 1 +#define UART0_CONTROL_REG0_TXRES_MASK 0x00000002U -/*Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit - is self clearing once the reset has completed.*/ +/* +* Software reset for Rx data path: 0: no affect 1: receiver logic is reset + * and all pending receiver data is discarded. This bit is self clearing o + * nce the reset has completed. +*/ #undef UART0_CONTROL_REG0_RXRES_DEFVAL #undef UART0_CONTROL_REG0_RXRES_SHIFT #undef UART0_CONTROL_REG0_RXRES_MASK -#define UART0_CONTROL_REG0_RXRES_DEFVAL 0x00000128 -#define UART0_CONTROL_REG0_RXRES_SHIFT 0 -#define UART0_CONTROL_REG0_RXRES_MASK 0x00000001U +#define UART0_CONTROL_REG0_RXRES_DEFVAL 0x00000128 +#define UART0_CONTROL_REG0_RXRES_SHIFT 0 +#define UART0_CONTROL_REG0_RXRES_MASK 0x00000001U -/*Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback*/ +/* +* Channel mode: Defines the mode of operation of the UART. 00: normal 01: + * automatic echo 10: local loopback 11: remote loopback +*/ #undef UART0_MODE_REG0_CHMODE_DEFVAL #undef UART0_MODE_REG0_CHMODE_SHIFT #undef UART0_MODE_REG0_CHMODE_MASK -#define UART0_MODE_REG0_CHMODE_DEFVAL 0x00000000 -#define UART0_MODE_REG0_CHMODE_SHIFT 8 -#define UART0_MODE_REG0_CHMODE_MASK 0x00000300U +#define UART0_MODE_REG0_CHMODE_DEFVAL 0x00000000 +#define UART0_MODE_REG0_CHMODE_SHIFT 8 +#define UART0_MODE_REG0_CHMODE_MASK 0x00000300U -/*Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5 - stop bits 10: 2 stop bits 11: reserved*/ +/* +* Number of stop bits: Defines the number of stop bits to detect on receiv + * e and to generate on transmit. 00: 1 stop bit 01: 1.5 stop bits 10: 2 st + * op bits 11: reserved +*/ #undef UART0_MODE_REG0_NBSTOP_DEFVAL #undef UART0_MODE_REG0_NBSTOP_SHIFT #undef UART0_MODE_REG0_NBSTOP_MASK -#define UART0_MODE_REG0_NBSTOP_DEFVAL 0x00000000 -#define UART0_MODE_REG0_NBSTOP_SHIFT 6 -#define UART0_MODE_REG0_NBSTOP_MASK 0x000000C0U +#define UART0_MODE_REG0_NBSTOP_DEFVAL 0x00000000 +#define UART0_MODE_REG0_NBSTOP_SHIFT 6 +#define UART0_MODE_REG0_NBSTOP_MASK 0x000000C0U -/*Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity - 01: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity*/ +/* +* Parity type select: Defines the expected parity to check on receive and + * the parity to generate on transmit. 000: even parity 001: odd parity 010 + * : forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no pari + * ty +*/ #undef UART0_MODE_REG0_PAR_DEFVAL #undef UART0_MODE_REG0_PAR_SHIFT #undef UART0_MODE_REG0_PAR_MASK -#define UART0_MODE_REG0_PAR_DEFVAL 0x00000000 -#define UART0_MODE_REG0_PAR_SHIFT 3 -#define UART0_MODE_REG0_PAR_MASK 0x00000038U +#define UART0_MODE_REG0_PAR_DEFVAL 0x00000000 +#define UART0_MODE_REG0_PAR_SHIFT 3 +#define UART0_MODE_REG0_PAR_MASK 0x00000038U -/*Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits*/ +/* +* Character length select: Defines the number of bits in each character. 1 + * 1: 6 bits 10: 7 bits 0x: 8 bits +*/ #undef UART0_MODE_REG0_CHRL_DEFVAL #undef UART0_MODE_REG0_CHRL_SHIFT #undef UART0_MODE_REG0_CHRL_MASK -#define UART0_MODE_REG0_CHRL_DEFVAL 0x00000000 -#define UART0_MODE_REG0_CHRL_SHIFT 1 -#define UART0_MODE_REG0_CHRL_MASK 0x00000006U +#define UART0_MODE_REG0_CHRL_DEFVAL 0x00000000 +#define UART0_MODE_REG0_CHRL_SHIFT 1 +#define UART0_MODE_REG0_CHRL_MASK 0x00000006U -/*Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock - source is uart_ref_clk 1: clock source is uart_ref_clk/8*/ +/* +* Clock source select: This field defines whether a pre-scalar of 8 is app + * lied to the baud rate generator input clock. 0: clock source is uart_ref + * _clk 1: clock source is uart_ref_clk/8 +*/ #undef UART0_MODE_REG0_CLKS_DEFVAL #undef UART0_MODE_REG0_CLKS_SHIFT #undef UART0_MODE_REG0_CLKS_MASK -#define UART0_MODE_REG0_CLKS_DEFVAL 0x00000000 -#define UART0_MODE_REG0_CLKS_SHIFT 0 -#define UART0_MODE_REG0_CLKS_MASK 0x00000001U +#define UART0_MODE_REG0_CLKS_DEFVAL 0x00000000 +#define UART0_MODE_REG0_CLKS_SHIFT 0 +#define UART0_MODE_REG0_CLKS_MASK 0x00000001U -/*Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate*/ +/* +* Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate +*/ #undef UART1_BAUD_RATE_DIVIDER_REG0_BDIV_DEFVAL #undef UART1_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT #undef UART1_BAUD_RATE_DIVIDER_REG0_BDIV_MASK -#define UART1_BAUD_RATE_DIVIDER_REG0_BDIV_DEFVAL 0x0000000F -#define UART1_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT 0 -#define UART1_BAUD_RATE_DIVIDER_REG0_BDIV_MASK 0x000000FFU +#define UART1_BAUD_RATE_DIVIDER_REG0_BDIV_DEFVAL 0x0000000F +#define UART1_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT 0 +#define UART1_BAUD_RATE_DIVIDER_REG0_BDIV_MASK 0x000000FFU -/*Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample*/ +/* +* Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor + * bypass (baud_sample = sel_clk) 2 - 65535: baud_sample +*/ #undef UART1_BAUD_RATE_GEN_REG0_CD_DEFVAL #undef UART1_BAUD_RATE_GEN_REG0_CD_SHIFT #undef UART1_BAUD_RATE_GEN_REG0_CD_MASK -#define UART1_BAUD_RATE_GEN_REG0_CD_DEFVAL 0x0000028B -#define UART1_BAUD_RATE_GEN_REG0_CD_SHIFT 0 -#define UART1_BAUD_RATE_GEN_REG0_CD_MASK 0x0000FFFFU +#define UART1_BAUD_RATE_GEN_REG0_CD_DEFVAL 0x0000028B +#define UART1_BAUD_RATE_GEN_REG0_CD_SHIFT 0 +#define UART1_BAUD_RATE_GEN_REG0_CD_MASK 0x0000FFFFU -/*Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a - high level during 12 bit periods. It can be set regardless of the value of STTBRK.*/ +/* +* Stop transmitter break: 0: no affect 1: stop transmission of the break a + * fter a minimum of one character length and transmit a high level during + * 12 bit periods. It can be set regardless of the value of STTBRK. +*/ #undef UART1_CONTROL_REG0_STPBRK_DEFVAL #undef UART1_CONTROL_REG0_STPBRK_SHIFT #undef UART1_CONTROL_REG0_STPBRK_MASK -#define UART1_CONTROL_REG0_STPBRK_DEFVAL 0x00000128 -#define UART1_CONTROL_REG0_STPBRK_SHIFT 8 -#define UART1_CONTROL_REG0_STPBRK_MASK 0x00000100U +#define UART1_CONTROL_REG0_STPBRK_DEFVAL 0x00000128 +#define UART1_CONTROL_REG0_STPBRK_SHIFT 8 +#define UART1_CONTROL_REG0_STPBRK_MASK 0x00000100U -/*Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the - transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high.*/ +/* +* Start transmitter break: 0: no affect 1: start to transmit a break after + * the characters currently present in the FIFO and the transmit shift reg + * ister have been transmitted. It can only be set if STPBRK (Stop transmit + * ter break) is not high. +*/ #undef UART1_CONTROL_REG0_STTBRK_DEFVAL #undef UART1_CONTROL_REG0_STTBRK_SHIFT #undef UART1_CONTROL_REG0_STTBRK_MASK -#define UART1_CONTROL_REG0_STTBRK_DEFVAL 0x00000128 -#define UART1_CONTROL_REG0_STTBRK_SHIFT 7 -#define UART1_CONTROL_REG0_STTBRK_MASK 0x00000080U +#define UART1_CONTROL_REG0_STTBRK_DEFVAL 0x00000128 +#define UART1_CONTROL_REG0_STTBRK_SHIFT 7 +#define UART1_CONTROL_REG0_STTBRK_MASK 0x00000080U -/*Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has co - pleted.*/ +/* +* Restart receiver timeout counter: 1: receiver timeout counter is restart + * ed. This bit is self clearing once the restart has completed. +*/ #undef UART1_CONTROL_REG0_RSTTO_DEFVAL #undef UART1_CONTROL_REG0_RSTTO_SHIFT #undef UART1_CONTROL_REG0_RSTTO_MASK -#define UART1_CONTROL_REG0_RSTTO_DEFVAL 0x00000128 -#define UART1_CONTROL_REG0_RSTTO_SHIFT 6 -#define UART1_CONTROL_REG0_RSTTO_MASK 0x00000040U +#define UART1_CONTROL_REG0_RSTTO_DEFVAL 0x00000128 +#define UART1_CONTROL_REG0_RSTTO_SHIFT 6 +#define UART1_CONTROL_REG0_RSTTO_MASK 0x00000040U -/*Transmit disable: 0: enable transmitter 1: disable transmitter*/ +/* +* Transmit disable: 0: enable transmitter 1: disable transmitter +*/ #undef UART1_CONTROL_REG0_TXDIS_DEFVAL #undef UART1_CONTROL_REG0_TXDIS_SHIFT #undef UART1_CONTROL_REG0_TXDIS_MASK -#define UART1_CONTROL_REG0_TXDIS_DEFVAL 0x00000128 -#define UART1_CONTROL_REG0_TXDIS_SHIFT 5 -#define UART1_CONTROL_REG0_TXDIS_MASK 0x00000020U +#define UART1_CONTROL_REG0_TXDIS_DEFVAL 0x00000128 +#define UART1_CONTROL_REG0_TXDIS_SHIFT 5 +#define UART1_CONTROL_REG0_TXDIS_MASK 0x00000020U -/*Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0.*/ +/* +* Transmit enable: 0: disable transmitter 1: enable transmitter, provided + * the TXDIS field is set to 0. +*/ #undef UART1_CONTROL_REG0_TXEN_DEFVAL #undef UART1_CONTROL_REG0_TXEN_SHIFT #undef UART1_CONTROL_REG0_TXEN_MASK -#define UART1_CONTROL_REG0_TXEN_DEFVAL 0x00000128 -#define UART1_CONTROL_REG0_TXEN_SHIFT 4 -#define UART1_CONTROL_REG0_TXEN_MASK 0x00000010U +#define UART1_CONTROL_REG0_TXEN_DEFVAL 0x00000128 +#define UART1_CONTROL_REG0_TXEN_SHIFT 4 +#define UART1_CONTROL_REG0_TXEN_MASK 0x00000010U -/*Receive disable: 0: enable 1: disable, regardless of the value of RXEN*/ +/* +* Receive disable: 0: enable 1: disable, regardless of the value of RXEN +*/ #undef UART1_CONTROL_REG0_RXDIS_DEFVAL #undef UART1_CONTROL_REG0_RXDIS_SHIFT #undef UART1_CONTROL_REG0_RXDIS_MASK -#define UART1_CONTROL_REG0_RXDIS_DEFVAL 0x00000128 -#define UART1_CONTROL_REG0_RXDIS_SHIFT 3 -#define UART1_CONTROL_REG0_RXDIS_MASK 0x00000008U +#define UART1_CONTROL_REG0_RXDIS_DEFVAL 0x00000128 +#define UART1_CONTROL_REG0_RXDIS_SHIFT 3 +#define UART1_CONTROL_REG0_RXDIS_MASK 0x00000008U -/*Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero.*/ +/* +* Receive enable: 0: disable 1: enable When set to one, the receiver logic + * is enabled, provided the RXDIS field is set to zero. +*/ #undef UART1_CONTROL_REG0_RXEN_DEFVAL #undef UART1_CONTROL_REG0_RXEN_SHIFT #undef UART1_CONTROL_REG0_RXEN_MASK -#define UART1_CONTROL_REG0_RXEN_DEFVAL 0x00000128 -#define UART1_CONTROL_REG0_RXEN_SHIFT 2 -#define UART1_CONTROL_REG0_RXEN_MASK 0x00000004U +#define UART1_CONTROL_REG0_RXEN_DEFVAL 0x00000128 +#define UART1_CONTROL_REG0_RXEN_SHIFT 2 +#define UART1_CONTROL_REG0_RXEN_MASK 0x00000004U -/*Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded Thi - bit is self clearing once the reset has completed.*/ +/* +* Software reset for Tx data path: 0: no affect 1: transmitter logic is re + * set and all pending transmitter data is discarded This bit is self clear + * ing once the reset has completed. +*/ #undef UART1_CONTROL_REG0_TXRES_DEFVAL #undef UART1_CONTROL_REG0_TXRES_SHIFT #undef UART1_CONTROL_REG0_TXRES_MASK -#define UART1_CONTROL_REG0_TXRES_DEFVAL 0x00000128 -#define UART1_CONTROL_REG0_TXRES_SHIFT 1 -#define UART1_CONTROL_REG0_TXRES_MASK 0x00000002U +#define UART1_CONTROL_REG0_TXRES_DEFVAL 0x00000128 +#define UART1_CONTROL_REG0_TXRES_SHIFT 1 +#define UART1_CONTROL_REG0_TXRES_MASK 0x00000002U -/*Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit - is self clearing once the reset has completed.*/ +/* +* Software reset for Rx data path: 0: no affect 1: receiver logic is reset + * and all pending receiver data is discarded. This bit is self clearing o + * nce the reset has completed. +*/ #undef UART1_CONTROL_REG0_RXRES_DEFVAL #undef UART1_CONTROL_REG0_RXRES_SHIFT #undef UART1_CONTROL_REG0_RXRES_MASK -#define UART1_CONTROL_REG0_RXRES_DEFVAL 0x00000128 -#define UART1_CONTROL_REG0_RXRES_SHIFT 0 -#define UART1_CONTROL_REG0_RXRES_MASK 0x00000001U +#define UART1_CONTROL_REG0_RXRES_DEFVAL 0x00000128 +#define UART1_CONTROL_REG0_RXRES_SHIFT 0 +#define UART1_CONTROL_REG0_RXRES_MASK 0x00000001U -/*Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback*/ +/* +* Channel mode: Defines the mode of operation of the UART. 00: normal 01: + * automatic echo 10: local loopback 11: remote loopback +*/ #undef UART1_MODE_REG0_CHMODE_DEFVAL #undef UART1_MODE_REG0_CHMODE_SHIFT #undef UART1_MODE_REG0_CHMODE_MASK -#define UART1_MODE_REG0_CHMODE_DEFVAL 0x00000000 -#define UART1_MODE_REG0_CHMODE_SHIFT 8 -#define UART1_MODE_REG0_CHMODE_MASK 0x00000300U +#define UART1_MODE_REG0_CHMODE_DEFVAL 0x00000000 +#define UART1_MODE_REG0_CHMODE_SHIFT 8 +#define UART1_MODE_REG0_CHMODE_MASK 0x00000300U -/*Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5 - stop bits 10: 2 stop bits 11: reserved*/ +/* +* Number of stop bits: Defines the number of stop bits to detect on receiv + * e and to generate on transmit. 00: 1 stop bit 01: 1.5 stop bits 10: 2 st + * op bits 11: reserved +*/ #undef UART1_MODE_REG0_NBSTOP_DEFVAL #undef UART1_MODE_REG0_NBSTOP_SHIFT #undef UART1_MODE_REG0_NBSTOP_MASK -#define UART1_MODE_REG0_NBSTOP_DEFVAL 0x00000000 -#define UART1_MODE_REG0_NBSTOP_SHIFT 6 -#define UART1_MODE_REG0_NBSTOP_MASK 0x000000C0U +#define UART1_MODE_REG0_NBSTOP_DEFVAL 0x00000000 +#define UART1_MODE_REG0_NBSTOP_SHIFT 6 +#define UART1_MODE_REG0_NBSTOP_MASK 0x000000C0U -/*Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity - 01: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity*/ +/* +* Parity type select: Defines the expected parity to check on receive and + * the parity to generate on transmit. 000: even parity 001: odd parity 010 + * : forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no pari + * ty +*/ #undef UART1_MODE_REG0_PAR_DEFVAL #undef UART1_MODE_REG0_PAR_SHIFT #undef UART1_MODE_REG0_PAR_MASK -#define UART1_MODE_REG0_PAR_DEFVAL 0x00000000 -#define UART1_MODE_REG0_PAR_SHIFT 3 -#define UART1_MODE_REG0_PAR_MASK 0x00000038U +#define UART1_MODE_REG0_PAR_DEFVAL 0x00000000 +#define UART1_MODE_REG0_PAR_SHIFT 3 +#define UART1_MODE_REG0_PAR_MASK 0x00000038U -/*Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits*/ +/* +* Character length select: Defines the number of bits in each character. 1 + * 1: 6 bits 10: 7 bits 0x: 8 bits +*/ #undef UART1_MODE_REG0_CHRL_DEFVAL #undef UART1_MODE_REG0_CHRL_SHIFT #undef UART1_MODE_REG0_CHRL_MASK -#define UART1_MODE_REG0_CHRL_DEFVAL 0x00000000 -#define UART1_MODE_REG0_CHRL_SHIFT 1 -#define UART1_MODE_REG0_CHRL_MASK 0x00000006U +#define UART1_MODE_REG0_CHRL_DEFVAL 0x00000000 +#define UART1_MODE_REG0_CHRL_SHIFT 1 +#define UART1_MODE_REG0_CHRL_MASK 0x00000006U -/*Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock - source is uart_ref_clk 1: clock source is uart_ref_clk/8*/ +/* +* Clock source select: This field defines whether a pre-scalar of 8 is app + * lied to the baud rate generator input clock. 0: clock source is uart_ref + * _clk 1: clock source is uart_ref_clk/8 +*/ #undef UART1_MODE_REG0_CLKS_DEFVAL #undef UART1_MODE_REG0_CLKS_SHIFT #undef UART1_MODE_REG0_CLKS_MASK -#define UART1_MODE_REG0_CLKS_DEFVAL 0x00000000 -#define UART1_MODE_REG0_CLKS_SHIFT 0 -#define UART1_MODE_REG0_CLKS_MASK 0x00000001U +#define UART1_MODE_REG0_CLKS_DEFVAL 0x00000000 +#define UART1_MODE_REG0_CLKS_SHIFT 0 +#define UART1_MODE_REG0_CLKS_MASK 0x00000001U -/*TrustZone Classification for ADMA*/ +/* +* Block level reset +*/ +#undef CRL_APB_RST_LPD_IOU2_GPIO_RESET_DEFVAL +#undef CRL_APB_RST_LPD_IOU2_GPIO_RESET_SHIFT +#undef CRL_APB_RST_LPD_IOU2_GPIO_RESET_MASK +#define CRL_APB_RST_LPD_IOU2_GPIO_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_GPIO_RESET_SHIFT 18 +#define CRL_APB_RST_LPD_IOU2_GPIO_RESET_MASK 0x00040000U + +/* +* TrustZone Classification for ADMA +*/ #undef LPD_SLCR_SECURE_SLCR_ADMA_TZ_DEFVAL #undef LPD_SLCR_SECURE_SLCR_ADMA_TZ_SHIFT #undef LPD_SLCR_SECURE_SLCR_ADMA_TZ_MASK -#define LPD_SLCR_SECURE_SLCR_ADMA_TZ_DEFVAL -#define LPD_SLCR_SECURE_SLCR_ADMA_TZ_SHIFT 0 -#define LPD_SLCR_SECURE_SLCR_ADMA_TZ_MASK 0x000000FFU +#define LPD_SLCR_SECURE_SLCR_ADMA_TZ_DEFVAL +#define LPD_SLCR_SECURE_SLCR_ADMA_TZ_SHIFT 0 +#define LPD_SLCR_SECURE_SLCR_ADMA_TZ_MASK 0x000000FFU -/*CSU regsiter*/ +/* +* CSU regsiter +*/ #undef CSU_TAMPER_STATUS_TAMPER_0_DEFVAL #undef CSU_TAMPER_STATUS_TAMPER_0_SHIFT #undef CSU_TAMPER_STATUS_TAMPER_0_MASK -#define CSU_TAMPER_STATUS_TAMPER_0_DEFVAL 0x00000000 -#define CSU_TAMPER_STATUS_TAMPER_0_SHIFT 0 -#define CSU_TAMPER_STATUS_TAMPER_0_MASK 0x00000001U +#define CSU_TAMPER_STATUS_TAMPER_0_DEFVAL 0x00000000 +#define CSU_TAMPER_STATUS_TAMPER_0_SHIFT 0 +#define CSU_TAMPER_STATUS_TAMPER_0_MASK 0x00000001U -/*External MIO*/ +/* +* External MIO +*/ #undef CSU_TAMPER_STATUS_TAMPER_1_DEFVAL #undef CSU_TAMPER_STATUS_TAMPER_1_SHIFT #undef CSU_TAMPER_STATUS_TAMPER_1_MASK -#define CSU_TAMPER_STATUS_TAMPER_1_DEFVAL 0x00000000 -#define CSU_TAMPER_STATUS_TAMPER_1_SHIFT 1 -#define CSU_TAMPER_STATUS_TAMPER_1_MASK 0x00000002U +#define CSU_TAMPER_STATUS_TAMPER_1_DEFVAL 0x00000000 +#define CSU_TAMPER_STATUS_TAMPER_1_SHIFT 1 +#define CSU_TAMPER_STATUS_TAMPER_1_MASK 0x00000002U -/*JTAG toggle detect*/ +/* +* JTAG toggle detect +*/ #undef CSU_TAMPER_STATUS_TAMPER_2_DEFVAL #undef CSU_TAMPER_STATUS_TAMPER_2_SHIFT #undef CSU_TAMPER_STATUS_TAMPER_2_MASK -#define CSU_TAMPER_STATUS_TAMPER_2_DEFVAL 0x00000000 -#define CSU_TAMPER_STATUS_TAMPER_2_SHIFT 2 -#define CSU_TAMPER_STATUS_TAMPER_2_MASK 0x00000004U +#define CSU_TAMPER_STATUS_TAMPER_2_DEFVAL 0x00000000 +#define CSU_TAMPER_STATUS_TAMPER_2_SHIFT 2 +#define CSU_TAMPER_STATUS_TAMPER_2_MASK 0x00000004U -/*PL SEU error*/ +/* +* PL SEU error +*/ #undef CSU_TAMPER_STATUS_TAMPER_3_DEFVAL #undef CSU_TAMPER_STATUS_TAMPER_3_SHIFT #undef CSU_TAMPER_STATUS_TAMPER_3_MASK -#define CSU_TAMPER_STATUS_TAMPER_3_DEFVAL 0x00000000 -#define CSU_TAMPER_STATUS_TAMPER_3_SHIFT 3 -#define CSU_TAMPER_STATUS_TAMPER_3_MASK 0x00000008U +#define CSU_TAMPER_STATUS_TAMPER_3_DEFVAL 0x00000000 +#define CSU_TAMPER_STATUS_TAMPER_3_SHIFT 3 +#define CSU_TAMPER_STATUS_TAMPER_3_MASK 0x00000008U -/*AMS over temperature alarm for LPD*/ +/* +* AMS over temperature alarm for LPD +*/ #undef CSU_TAMPER_STATUS_TAMPER_4_DEFVAL #undef CSU_TAMPER_STATUS_TAMPER_4_SHIFT #undef CSU_TAMPER_STATUS_TAMPER_4_MASK -#define CSU_TAMPER_STATUS_TAMPER_4_DEFVAL 0x00000000 -#define CSU_TAMPER_STATUS_TAMPER_4_SHIFT 4 -#define CSU_TAMPER_STATUS_TAMPER_4_MASK 0x00000010U +#define CSU_TAMPER_STATUS_TAMPER_4_DEFVAL 0x00000000 +#define CSU_TAMPER_STATUS_TAMPER_4_SHIFT 4 +#define CSU_TAMPER_STATUS_TAMPER_4_MASK 0x00000010U -/*AMS over temperature alarm for APU*/ +/* +* AMS over temperature alarm for APU +*/ #undef CSU_TAMPER_STATUS_TAMPER_5_DEFVAL #undef CSU_TAMPER_STATUS_TAMPER_5_SHIFT #undef CSU_TAMPER_STATUS_TAMPER_5_MASK -#define CSU_TAMPER_STATUS_TAMPER_5_DEFVAL 0x00000000 -#define CSU_TAMPER_STATUS_TAMPER_5_SHIFT 5 -#define CSU_TAMPER_STATUS_TAMPER_5_MASK 0x00000020U +#define CSU_TAMPER_STATUS_TAMPER_5_DEFVAL 0x00000000 +#define CSU_TAMPER_STATUS_TAMPER_5_SHIFT 5 +#define CSU_TAMPER_STATUS_TAMPER_5_MASK 0x00000020U -/*AMS voltage alarm for VCCPINT_FPD*/ +/* +* AMS voltage alarm for VCCPINT_FPD +*/ #undef CSU_TAMPER_STATUS_TAMPER_6_DEFVAL #undef CSU_TAMPER_STATUS_TAMPER_6_SHIFT #undef CSU_TAMPER_STATUS_TAMPER_6_MASK -#define CSU_TAMPER_STATUS_TAMPER_6_DEFVAL 0x00000000 -#define CSU_TAMPER_STATUS_TAMPER_6_SHIFT 6 -#define CSU_TAMPER_STATUS_TAMPER_6_MASK 0x00000040U +#define CSU_TAMPER_STATUS_TAMPER_6_DEFVAL 0x00000000 +#define CSU_TAMPER_STATUS_TAMPER_6_SHIFT 6 +#define CSU_TAMPER_STATUS_TAMPER_6_MASK 0x00000040U -/*AMS voltage alarm for VCCPINT_LPD*/ +/* +* AMS voltage alarm for VCCPINT_LPD +*/ #undef CSU_TAMPER_STATUS_TAMPER_7_DEFVAL #undef CSU_TAMPER_STATUS_TAMPER_7_SHIFT #undef CSU_TAMPER_STATUS_TAMPER_7_MASK -#define CSU_TAMPER_STATUS_TAMPER_7_DEFVAL 0x00000000 -#define CSU_TAMPER_STATUS_TAMPER_7_SHIFT 7 -#define CSU_TAMPER_STATUS_TAMPER_7_MASK 0x00000080U +#define CSU_TAMPER_STATUS_TAMPER_7_DEFVAL 0x00000000 +#define CSU_TAMPER_STATUS_TAMPER_7_SHIFT 7 +#define CSU_TAMPER_STATUS_TAMPER_7_MASK 0x00000080U -/*AMS voltage alarm for VCCPAUX*/ +/* +* AMS voltage alarm for VCCPAUX +*/ #undef CSU_TAMPER_STATUS_TAMPER_8_DEFVAL #undef CSU_TAMPER_STATUS_TAMPER_8_SHIFT #undef CSU_TAMPER_STATUS_TAMPER_8_MASK -#define CSU_TAMPER_STATUS_TAMPER_8_DEFVAL 0x00000000 -#define CSU_TAMPER_STATUS_TAMPER_8_SHIFT 8 -#define CSU_TAMPER_STATUS_TAMPER_8_MASK 0x00000100U +#define CSU_TAMPER_STATUS_TAMPER_8_DEFVAL 0x00000000 +#define CSU_TAMPER_STATUS_TAMPER_8_SHIFT 8 +#define CSU_TAMPER_STATUS_TAMPER_8_MASK 0x00000100U -/*AMS voltage alarm for DDRPHY*/ +/* +* AMS voltage alarm for DDRPHY +*/ #undef CSU_TAMPER_STATUS_TAMPER_9_DEFVAL #undef CSU_TAMPER_STATUS_TAMPER_9_SHIFT #undef CSU_TAMPER_STATUS_TAMPER_9_MASK -#define CSU_TAMPER_STATUS_TAMPER_9_DEFVAL 0x00000000 -#define CSU_TAMPER_STATUS_TAMPER_9_SHIFT 9 -#define CSU_TAMPER_STATUS_TAMPER_9_MASK 0x00000200U +#define CSU_TAMPER_STATUS_TAMPER_9_DEFVAL 0x00000000 +#define CSU_TAMPER_STATUS_TAMPER_9_SHIFT 9 +#define CSU_TAMPER_STATUS_TAMPER_9_MASK 0x00000200U -/*AMS voltage alarm for PSIO bank 0/1/2*/ +/* +* AMS voltage alarm for PSIO bank 0/1/2 +*/ #undef CSU_TAMPER_STATUS_TAMPER_10_DEFVAL #undef CSU_TAMPER_STATUS_TAMPER_10_SHIFT #undef CSU_TAMPER_STATUS_TAMPER_10_MASK -#define CSU_TAMPER_STATUS_TAMPER_10_DEFVAL 0x00000000 -#define CSU_TAMPER_STATUS_TAMPER_10_SHIFT 10 -#define CSU_TAMPER_STATUS_TAMPER_10_MASK 0x00000400U +#define CSU_TAMPER_STATUS_TAMPER_10_DEFVAL 0x00000000 +#define CSU_TAMPER_STATUS_TAMPER_10_SHIFT 10 +#define CSU_TAMPER_STATUS_TAMPER_10_MASK 0x00000400U -/*AMS voltage alarm for PSIO bank 3 (dedicated pins)*/ +/* +* AMS voltage alarm for PSIO bank 3 (dedicated pins) +*/ #undef CSU_TAMPER_STATUS_TAMPER_11_DEFVAL #undef CSU_TAMPER_STATUS_TAMPER_11_SHIFT #undef CSU_TAMPER_STATUS_TAMPER_11_MASK -#define CSU_TAMPER_STATUS_TAMPER_11_DEFVAL 0x00000000 -#define CSU_TAMPER_STATUS_TAMPER_11_SHIFT 11 -#define CSU_TAMPER_STATUS_TAMPER_11_MASK 0x00000800U +#define CSU_TAMPER_STATUS_TAMPER_11_DEFVAL 0x00000000 +#define CSU_TAMPER_STATUS_TAMPER_11_SHIFT 11 +#define CSU_TAMPER_STATUS_TAMPER_11_MASK 0x00000800U -/*AMS voltaage alarm for GT*/ +/* +* AMS voltaage alarm for GT +*/ #undef CSU_TAMPER_STATUS_TAMPER_12_DEFVAL #undef CSU_TAMPER_STATUS_TAMPER_12_SHIFT #undef CSU_TAMPER_STATUS_TAMPER_12_MASK -#define CSU_TAMPER_STATUS_TAMPER_12_DEFVAL 0x00000000 -#define CSU_TAMPER_STATUS_TAMPER_12_SHIFT 12 -#define CSU_TAMPER_STATUS_TAMPER_12_MASK 0x00001000U +#define CSU_TAMPER_STATUS_TAMPER_12_DEFVAL 0x00000000 +#define CSU_TAMPER_STATUS_TAMPER_12_SHIFT 12 +#define CSU_TAMPER_STATUS_TAMPER_12_MASK 0x00001000U -/*Set ACE outgoing AWQOS value*/ +/* +* Set ACE outgoing AWQOS value +*/ #undef APU_ACE_CTRL_AWQOS_DEFVAL #undef APU_ACE_CTRL_AWQOS_SHIFT #undef APU_ACE_CTRL_AWQOS_MASK -#define APU_ACE_CTRL_AWQOS_DEFVAL 0x000F000F -#define APU_ACE_CTRL_AWQOS_SHIFT 16 -#define APU_ACE_CTRL_AWQOS_MASK 0x000F0000U +#define APU_ACE_CTRL_AWQOS_DEFVAL 0x000F000F +#define APU_ACE_CTRL_AWQOS_SHIFT 16 +#define APU_ACE_CTRL_AWQOS_MASK 0x000F0000U -/*Set ACE outgoing ARQOS value*/ +/* +* Set ACE outgoing ARQOS value +*/ #undef APU_ACE_CTRL_ARQOS_DEFVAL #undef APU_ACE_CTRL_ARQOS_SHIFT #undef APU_ACE_CTRL_ARQOS_MASK -#define APU_ACE_CTRL_ARQOS_DEFVAL 0x000F000F -#define APU_ACE_CTRL_ARQOS_SHIFT 0 -#define APU_ACE_CTRL_ARQOS_MASK 0x0000000FU +#define APU_ACE_CTRL_ARQOS_DEFVAL 0x000F000F +#define APU_ACE_CTRL_ARQOS_SHIFT 0 +#define APU_ACE_CTRL_ARQOS_MASK 0x0000000FU -/*Enables the RTC. By writing a 0 to this bit, RTC will be powered off and the only module that potentially draws current from - he battery will be BBRAM. The value read through this bit does not necessarily reflect whether RTC is enabled or not. It is e - pected that RTC is enabled every time it is being configured. If RTC is not used in the design, FSBL will disable it by writi - g a 0 to this bit.*/ +/* +* Enables the RTC. By writing a 0 to this bit, RTC will be powered off and + * the only module that potentially draws current from the battery will be + * BBRAM. The value read through this bit does not necessarily reflect whe + * ther RTC is enabled or not. It is expected that RTC is enabled every tim + * e it is being configured. If RTC is not used in the design, FSBL will di + * sable it by writing a 0 to this bit. +*/ #undef RTC_CONTROL_BATTERY_DISABLE_DEFVAL #undef RTC_CONTROL_BATTERY_DISABLE_SHIFT #undef RTC_CONTROL_BATTERY_DISABLE_MASK -#define RTC_CONTROL_BATTERY_DISABLE_DEFVAL 0x01000000 -#define RTC_CONTROL_BATTERY_DISABLE_SHIFT 31 -#define RTC_CONTROL_BATTERY_DISABLE_MASK 0x80000000U +#define RTC_CONTROL_BATTERY_DISABLE_DEFVAL 0x01000000 +#define RTC_CONTROL_BATTERY_DISABLE_SHIFT 31 +#define RTC_CONTROL_BATTERY_DISABLE_MASK 0x80000000U -/*Frequency in number of ticks per second. Valid range from 10 MHz to 100 MHz.*/ +/* +* Frequency in number of ticks per second. Valid range from 10 MHz to 100 + * MHz. +*/ #undef IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_DEFVAL #undef IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_SHIFT #undef IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_MASK -#define IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_DEFVAL -#define IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_SHIFT 0 -#define IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_MASK 0xFFFFFFFFU +#define IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_DEFVAL +#define IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_SHIFT 0 +#define IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_MASK 0xFFFFFFFFU -/*Enable 0: The counter is disabled and not incrementing. 1: The counter is enabled and is incrementing.*/ +/* +* Enable 0: The counter is disabled and not incrementing. 1: The counter i + * s enabled and is incrementing. +*/ #undef IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_DEFVAL #undef IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_SHIFT #undef IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_MASK -#define IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_DEFVAL 0x00000000 -#define IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_SHIFT 0 -#define IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_MASK 0x00000001U -#undef LPD_XPPU_CFG_IEN_OFFSET -#define LPD_XPPU_CFG_IEN_OFFSET 0XFF980018 +#define IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_DEFVAL 0x00000000 +#define IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_SHIFT 0 +#define IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_MASK 0x00000001U -/*See Interuppt Status Register for details*/ -#undef LPD_XPPU_CFG_IEN_APER_PARITY_DEFVAL -#undef LPD_XPPU_CFG_IEN_APER_PARITY_SHIFT -#undef LPD_XPPU_CFG_IEN_APER_PARITY_MASK -#define LPD_XPPU_CFG_IEN_APER_PARITY_DEFVAL 0x00000000 -#define LPD_XPPU_CFG_IEN_APER_PARITY_SHIFT 7 -#define LPD_XPPU_CFG_IEN_APER_PARITY_MASK 0x00000080U +/* +* Operation is the same as DIRM_0[DIRECTION_0] +*/ +#undef GPIO_DIRM_1_DIRECTION_1_DEFVAL +#undef GPIO_DIRM_1_DIRECTION_1_SHIFT +#undef GPIO_DIRM_1_DIRECTION_1_MASK +#define GPIO_DIRM_1_DIRECTION_1_DEFVAL 0x00000000 +#define GPIO_DIRM_1_DIRECTION_1_SHIFT 0 +#define GPIO_DIRM_1_DIRECTION_1_MASK 0x03FFFFFFU -/*See Interuppt Status Register for details*/ -#undef LPD_XPPU_CFG_IEN_APER_TZ_DEFVAL -#undef LPD_XPPU_CFG_IEN_APER_TZ_SHIFT -#undef LPD_XPPU_CFG_IEN_APER_TZ_MASK -#define LPD_XPPU_CFG_IEN_APER_TZ_DEFVAL 0x00000000 -#define LPD_XPPU_CFG_IEN_APER_TZ_SHIFT 6 -#define LPD_XPPU_CFG_IEN_APER_TZ_MASK 0x00000040U +/* +* Operation is the same as OEN_0[OP_ENABLE_0] +*/ +#undef GPIO_OEN_1_OP_ENABLE_1_DEFVAL +#undef GPIO_OEN_1_OP_ENABLE_1_SHIFT +#undef GPIO_OEN_1_OP_ENABLE_1_MASK +#define GPIO_OEN_1_OP_ENABLE_1_DEFVAL 0x00000000 +#define GPIO_OEN_1_OP_ENABLE_1_SHIFT 0 +#define GPIO_OEN_1_OP_ENABLE_1_MASK 0x03FFFFFFU -/*See Interuppt Status Register for details*/ -#undef LPD_XPPU_CFG_IEN_APER_PERM_DEFVAL -#undef LPD_XPPU_CFG_IEN_APER_PERM_SHIFT -#undef LPD_XPPU_CFG_IEN_APER_PERM_MASK -#define LPD_XPPU_CFG_IEN_APER_PERM_DEFVAL 0x00000000 -#define LPD_XPPU_CFG_IEN_APER_PERM_SHIFT 5 -#define LPD_XPPU_CFG_IEN_APER_PERM_MASK 0x00000020U +/* +* Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW] +*/ +#undef GPIO_MASK_DATA_1_LSW_MASK_1_LSW_DEFVAL +#undef GPIO_MASK_DATA_1_LSW_MASK_1_LSW_SHIFT +#undef GPIO_MASK_DATA_1_LSW_MASK_1_LSW_MASK +#define GPIO_MASK_DATA_1_LSW_MASK_1_LSW_DEFVAL 0x00000000 +#define GPIO_MASK_DATA_1_LSW_MASK_1_LSW_SHIFT 16 +#define GPIO_MASK_DATA_1_LSW_MASK_1_LSW_MASK 0xFFFF0000U -/*See Interuppt Status Register for details*/ -#undef LPD_XPPU_CFG_IEN_MID_PARITY_DEFVAL -#undef LPD_XPPU_CFG_IEN_MID_PARITY_SHIFT -#undef LPD_XPPU_CFG_IEN_MID_PARITY_MASK -#define LPD_XPPU_CFG_IEN_MID_PARITY_DEFVAL 0x00000000 -#define LPD_XPPU_CFG_IEN_MID_PARITY_SHIFT 3 -#define LPD_XPPU_CFG_IEN_MID_PARITY_MASK 0x00000008U +/* +* Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW] +*/ +#undef GPIO_MASK_DATA_1_LSW_DATA_1_LSW_DEFVAL +#undef GPIO_MASK_DATA_1_LSW_DATA_1_LSW_SHIFT +#undef GPIO_MASK_DATA_1_LSW_DATA_1_LSW_MASK +#define GPIO_MASK_DATA_1_LSW_DATA_1_LSW_DEFVAL 0x00000000 +#define GPIO_MASK_DATA_1_LSW_DATA_1_LSW_SHIFT 0 +#define GPIO_MASK_DATA_1_LSW_DATA_1_LSW_MASK 0x0000FFFFU -/*See Interuppt Status Register for details*/ -#undef LPD_XPPU_CFG_IEN_MID_RO_DEFVAL -#undef LPD_XPPU_CFG_IEN_MID_RO_SHIFT -#undef LPD_XPPU_CFG_IEN_MID_RO_MASK -#define LPD_XPPU_CFG_IEN_MID_RO_DEFVAL 0x00000000 -#define LPD_XPPU_CFG_IEN_MID_RO_SHIFT 2 -#define LPD_XPPU_CFG_IEN_MID_RO_MASK 0x00000004U +/* +* Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW] +*/ +#undef GPIO_MASK_DATA_1_LSW_MASK_1_LSW_DEFVAL +#undef GPIO_MASK_DATA_1_LSW_MASK_1_LSW_SHIFT +#undef GPIO_MASK_DATA_1_LSW_MASK_1_LSW_MASK +#define GPIO_MASK_DATA_1_LSW_MASK_1_LSW_DEFVAL 0x00000000 +#define GPIO_MASK_DATA_1_LSW_MASK_1_LSW_SHIFT 16 +#define GPIO_MASK_DATA_1_LSW_MASK_1_LSW_MASK 0xFFFF0000U -/*See Interuppt Status Register for details*/ -#undef LPD_XPPU_CFG_IEN_MID_MISS_DEFVAL -#undef LPD_XPPU_CFG_IEN_MID_MISS_SHIFT -#undef LPD_XPPU_CFG_IEN_MID_MISS_MASK -#define LPD_XPPU_CFG_IEN_MID_MISS_DEFVAL 0x00000000 -#define LPD_XPPU_CFG_IEN_MID_MISS_SHIFT 1 -#define LPD_XPPU_CFG_IEN_MID_MISS_MASK 0x00000002U +/* +* Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW] +*/ +#undef GPIO_MASK_DATA_1_LSW_DATA_1_LSW_DEFVAL +#undef GPIO_MASK_DATA_1_LSW_DATA_1_LSW_SHIFT +#undef GPIO_MASK_DATA_1_LSW_DATA_1_LSW_MASK +#define GPIO_MASK_DATA_1_LSW_DATA_1_LSW_DEFVAL 0x00000000 +#define GPIO_MASK_DATA_1_LSW_DATA_1_LSW_SHIFT 0 +#define GPIO_MASK_DATA_1_LSW_DATA_1_LSW_MASK 0x0000FFFFU +#undef FPD_SLCR_SECURE_SLCR_DPDMA_OFFSET +#define FPD_SLCR_SECURE_SLCR_DPDMA_OFFSET 0XFD690040 +#undef FPD_SLCR_SECURE_SLCR_PCIE_OFFSET +#define FPD_SLCR_SECURE_SLCR_PCIE_OFFSET 0XFD690030 +#undef LPD_SLCR_SECURE_SLCR_USB_OFFSET +#define LPD_SLCR_SECURE_SLCR_USB_OFFSET 0XFF4B0034 +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_OFFSET +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_OFFSET 0XFF240004 +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET 0XFF240000 +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_OFFSET +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_OFFSET 0XFF240004 +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET 0XFF240000 +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET 0XFF240000 +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_OFFSET +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_OFFSET 0XFF240004 +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET 0XFF240000 +#undef LPD_SLCR_SECURE_SLCR_ADMA_OFFSET +#define LPD_SLCR_SECURE_SLCR_ADMA_OFFSET 0XFF4B0024 +#undef FPD_SLCR_SECURE_SLCR_GDMA_OFFSET +#define FPD_SLCR_SECURE_SLCR_GDMA_OFFSET 0XFD690050 -/*See Interuppt Status Register for details*/ -#undef LPD_XPPU_CFG_IEN_INV_APB_DEFVAL -#undef LPD_XPPU_CFG_IEN_INV_APB_SHIFT -#undef LPD_XPPU_CFG_IEN_INV_APB_MASK -#define LPD_XPPU_CFG_IEN_INV_APB_DEFVAL 0x00000000 -#define LPD_XPPU_CFG_IEN_INV_APB_SHIFT 0 -#define LPD_XPPU_CFG_IEN_INV_APB_MASK 0x00000001U +/* +* TrustZone classification for DisplayPort DMA +*/ +#undef FPD_SLCR_SECURE_SLCR_DPDMA_TZ_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_DPDMA_TZ_SHIFT +#undef FPD_SLCR_SECURE_SLCR_DPDMA_TZ_MASK +#define FPD_SLCR_SECURE_SLCR_DPDMA_TZ_DEFVAL 0x00000001 +#define FPD_SLCR_SECURE_SLCR_DPDMA_TZ_SHIFT 0 +#define FPD_SLCR_SECURE_SLCR_DPDMA_TZ_MASK 0x00000001U + +/* +* TrustZone classification for DMA Channel 0 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_0_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_0_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_0_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_0_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_0_SHIFT 21 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_0_MASK 0x00200000U + +/* +* TrustZone classification for DMA Channel 1 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_1_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_1_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_1_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_1_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_1_SHIFT 22 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_1_MASK 0x00400000U + +/* +* TrustZone classification for DMA Channel 2 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_2_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_2_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_2_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_2_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_2_SHIFT 23 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_2_MASK 0x00800000U + +/* +* TrustZone classification for DMA Channel 3 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_3_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_3_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_3_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_3_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_3_SHIFT 24 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_3_MASK 0x01000000U + +/* +* TrustZone classification for Ingress Address Translation 0 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_0_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_0_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_0_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_0_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_0_SHIFT 13 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_0_MASK 0x00002000U + +/* +* TrustZone classification for Ingress Address Translation 1 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_1_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_1_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_1_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_1_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_1_SHIFT 14 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_1_MASK 0x00004000U + +/* +* TrustZone classification for Ingress Address Translation 2 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_2_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_2_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_2_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_2_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_2_SHIFT 15 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_2_MASK 0x00008000U + +/* +* TrustZone classification for Ingress Address Translation 3 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_3_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_3_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_3_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_3_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_3_SHIFT 16 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_3_MASK 0x00010000U + +/* +* TrustZone classification for Ingress Address Translation 4 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_4_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_4_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_4_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_4_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_4_SHIFT 17 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_4_MASK 0x00020000U + +/* +* TrustZone classification for Ingress Address Translation 5 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_5_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_5_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_5_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_5_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_5_SHIFT 18 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_5_MASK 0x00040000U + +/* +* TrustZone classification for Ingress Address Translation 6 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_6_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_6_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_6_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_6_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_6_SHIFT 19 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_6_MASK 0x00080000U + +/* +* TrustZone classification for Ingress Address Translation 7 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_7_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_7_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_7_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_7_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_7_SHIFT 20 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_7_MASK 0x00100000U + +/* +* TrustZone classification for Egress Address Translation 0 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_0_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_0_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_0_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_0_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_0_SHIFT 5 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_0_MASK 0x00000020U + +/* +* TrustZone classification for Egress Address Translation 1 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_1_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_1_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_1_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_1_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_1_SHIFT 6 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_1_MASK 0x00000040U + +/* +* TrustZone classification for Egress Address Translation 2 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_2_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_2_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_2_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_2_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_2_SHIFT 7 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_2_MASK 0x00000080U + +/* +* TrustZone classification for Egress Address Translation 3 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_3_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_3_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_3_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_3_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_3_SHIFT 8 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_3_MASK 0x00000100U + +/* +* TrustZone classification for Egress Address Translation 4 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_4_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_4_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_4_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_4_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_4_SHIFT 9 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_4_MASK 0x00000200U + +/* +* TrustZone classification for Egress Address Translation 5 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_5_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_5_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_5_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_5_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_5_SHIFT 10 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_5_MASK 0x00000400U + +/* +* TrustZone classification for Egress Address Translation 6 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_6_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_6_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_6_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_6_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_6_SHIFT 11 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_6_MASK 0x00000800U + +/* +* TrustZone classification for Egress Address Translation 7 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_7_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_7_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_7_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_7_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_7_SHIFT 12 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_7_MASK 0x00001000U + +/* +* TrustZone classification for DMA Registers +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_REGS_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_REGS_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_REGS_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_REGS_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_REGS_SHIFT 4 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_REGS_MASK 0x00000010U + +/* +* TrustZone classification for MSIx Table +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_TABLE_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_TABLE_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_TABLE_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_TABLE_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_TABLE_SHIFT 2 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_TABLE_MASK 0x00000004U + +/* +* TrustZone classification for MSIx PBA +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_PBA_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_PBA_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_PBA_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_PBA_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_PBA_SHIFT 3 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_PBA_MASK 0x00000008U + +/* +* TrustZone classification for ECAM +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_ECAM_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_ECAM_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_ECAM_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_ECAM_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_ECAM_SHIFT 1 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_ECAM_MASK 0x00000002U + +/* +* TrustZone classification for Bridge Common Registers +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_BRIDGE_REGS_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_BRIDGE_REGS_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_BRIDGE_REGS_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_BRIDGE_REGS_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_BRIDGE_REGS_SHIFT 0 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_BRIDGE_REGS_MASK 0x00000001U + +/* +* TrustZone Classification for USB3_0 +*/ +#undef LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_0_DEFVAL +#undef LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_0_SHIFT +#undef LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_0_MASK +#define LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_0_DEFVAL 0x00000003 +#define LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_0_SHIFT 0 +#define LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_0_MASK 0x00000001U + +/* +* TrustZone Classification for USB3_1 +*/ +#undef LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_1_DEFVAL +#undef LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_1_SHIFT +#undef LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_1_MASK +#define LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_1_DEFVAL 0x00000003 +#define LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_1_SHIFT 1 +#define LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_1_MASK 0x00000002U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD0_AXI_ARPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD0_AXI_ARPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD0_AXI_ARPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD0_AXI_ARPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD0_AXI_ARPROT_SHIFT 16 +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD0_AXI_ARPROT_MASK 0x00070000U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD1_AXI_ARPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD1_AXI_ARPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD1_AXI_ARPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD1_AXI_ARPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD1_AXI_ARPROT_SHIFT 19 +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD1_AXI_ARPROT_MASK 0x00380000U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD0_AXI_AWPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD0_AXI_AWPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD0_AXI_AWPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD0_AXI_AWPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD0_AXI_AWPROT_SHIFT 16 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD0_AXI_AWPROT_MASK 0x00070000U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD1_AXI_AWPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD1_AXI_AWPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD1_AXI_AWPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD1_AXI_AWPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD1_AXI_AWPROT_SHIFT 19 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD1_AXI_AWPROT_MASK 0x00380000U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM0_AXI_ARPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM0_AXI_ARPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM0_AXI_ARPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM0_AXI_ARPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM0_AXI_ARPROT_SHIFT 0 +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM0_AXI_ARPROT_MASK 0x00000007U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM1_AXI_ARPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM1_AXI_ARPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM1_AXI_ARPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM1_AXI_ARPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM1_AXI_ARPROT_SHIFT 3 +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM1_AXI_ARPROT_MASK 0x00000038U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM2_AXI_ARPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM2_AXI_ARPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM2_AXI_ARPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM2_AXI_ARPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM2_AXI_ARPROT_SHIFT 6 +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM2_AXI_ARPROT_MASK 0x000001C0U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM3_AXI_ARPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM3_AXI_ARPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM3_AXI_ARPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM3_AXI_ARPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM3_AXI_ARPROT_SHIFT 9 +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM3_AXI_ARPROT_MASK 0x00000E00U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM0_AXI_AWPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM0_AXI_AWPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM0_AXI_AWPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM0_AXI_AWPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM0_AXI_AWPROT_SHIFT 0 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM0_AXI_AWPROT_MASK 0x00000007U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM1_AXI_AWPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM1_AXI_AWPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM1_AXI_AWPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM1_AXI_AWPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM1_AXI_AWPROT_SHIFT 3 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM1_AXI_AWPROT_MASK 0x00000038U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM2_AXI_AWPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM2_AXI_AWPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM2_AXI_AWPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM2_AXI_AWPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM2_AXI_AWPROT_SHIFT 6 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM2_AXI_AWPROT_MASK 0x000001C0U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM3_AXI_AWPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM3_AXI_AWPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM3_AXI_AWPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM3_AXI_AWPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM3_AXI_AWPROT_SHIFT 9 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM3_AXI_AWPROT_MASK 0x00000E00U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_QSPI_AXI_AWPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_QSPI_AXI_AWPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_QSPI_AXI_AWPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_QSPI_AXI_AWPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_QSPI_AXI_AWPROT_SHIFT 25 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_QSPI_AXI_AWPROT_MASK 0x0E000000U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_NAND_AXI_ARPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_NAND_AXI_ARPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_NAND_AXI_ARPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_NAND_AXI_ARPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_NAND_AXI_ARPROT_SHIFT 22 +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_NAND_AXI_ARPROT_MASK 0x01C00000U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_NAND_AXI_AWPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_NAND_AXI_AWPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_NAND_AXI_AWPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_NAND_AXI_AWPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_NAND_AXI_AWPROT_SHIFT 22 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_NAND_AXI_AWPROT_MASK 0x01C00000U + +/* +* TrustZone Classification for ADMA +*/ +#undef LPD_SLCR_SECURE_SLCR_ADMA_TZ_DEFVAL +#undef LPD_SLCR_SECURE_SLCR_ADMA_TZ_SHIFT +#undef LPD_SLCR_SECURE_SLCR_ADMA_TZ_MASK +#define LPD_SLCR_SECURE_SLCR_ADMA_TZ_DEFVAL +#define LPD_SLCR_SECURE_SLCR_ADMA_TZ_SHIFT 0 +#define LPD_SLCR_SECURE_SLCR_ADMA_TZ_MASK 0x000000FFU + +/* +* TrustZone Classification for GDMA +*/ +#undef FPD_SLCR_SECURE_SLCR_GDMA_TZ_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_GDMA_TZ_SHIFT +#undef FPD_SLCR_SECURE_SLCR_GDMA_TZ_MASK +#define FPD_SLCR_SECURE_SLCR_GDMA_TZ_DEFVAL +#define FPD_SLCR_SECURE_SLCR_GDMA_TZ_SHIFT 0 +#define FPD_SLCR_SECURE_SLCR_GDMA_TZ_MASK 0x000000FFU #undef SERDES_PLL_REF_SEL0_OFFSET #define SERDES_PLL_REF_SEL0_OFFSET 0XFD410000 #undef SERDES_PLL_REF_SEL1_OFFSET @@ -25332,8 +32859,6 @@ #define SERDES_L3_TM_DIG_6_OFFSET 0XFD40D06C #undef SERDES_L3_TX_DIG_TM_61_OFFSET #define SERDES_L3_TX_DIG_TM_61_OFFSET 0XFD40C0F4 -#undef SERDES_L3_TXPMA_ST_0_OFFSET -#define SERDES_L3_TXPMA_ST_0_OFFSET 0XFD40CB00 #undef SERDES_L0_TM_AUX_0_OFFSET #define SERDES_L0_TM_AUX_0_OFFSET 0XFD4010CC #undef SERDES_L2_TM_AUX_0_OFFSET @@ -25372,6 +32897,10 @@ #define SERDES_L0_TM_E_ILL8_OFFSET 0XFD401940 #undef SERDES_L0_TM_E_ILL9_OFFSET #define SERDES_L0_TM_E_ILL9_OFFSET 0XFD401944 +#undef SERDES_L0_TM_ILL13_OFFSET +#define SERDES_L0_TM_ILL13_OFFSET 0XFD401994 +#undef SERDES_L1_TM_ILL13_OFFSET +#define SERDES_L1_TM_ILL13_OFFSET 0XFD405994 #undef SERDES_L2_TM_MISC2_OFFSET #define SERDES_L2_TM_MISC2_OFFSET 0XFD40989C #undef SERDES_L2_TM_IQ_ILL1_OFFSET @@ -25398,6 +32927,8 @@ #define SERDES_L2_TM_E_ILL8_OFFSET 0XFD409940 #undef SERDES_L2_TM_E_ILL9_OFFSET #define SERDES_L2_TM_E_ILL9_OFFSET 0XFD409944 +#undef SERDES_L2_TM_ILL13_OFFSET +#define SERDES_L2_TM_ILL13_OFFSET 0XFD409994 #undef SERDES_L3_TM_MISC2_OFFSET #define SERDES_L3_TM_MISC2_OFFSET 0XFD40D89C #undef SERDES_L3_TM_IQ_ILL1_OFFSET @@ -25426,10 +32957,16 @@ #define SERDES_L3_TM_E_ILL8_OFFSET 0XFD40D940 #undef SERDES_L3_TM_E_ILL9_OFFSET #define SERDES_L3_TM_E_ILL9_OFFSET 0XFD40D944 -#undef SERDES_L0_TM_DIG_21_OFFSET -#define SERDES_L0_TM_DIG_21_OFFSET 0XFD4010A8 +#undef SERDES_L3_TM_ILL13_OFFSET +#define SERDES_L3_TM_ILL13_OFFSET 0XFD40D994 #undef SERDES_L0_TM_DIG_10_OFFSET #define SERDES_L0_TM_DIG_10_OFFSET 0XFD40107C +#undef SERDES_L1_TM_DIG_10_OFFSET +#define SERDES_L1_TM_DIG_10_OFFSET 0XFD40507C +#undef SERDES_L2_TM_DIG_10_OFFSET +#define SERDES_L2_TM_DIG_10_OFFSET 0XFD40907C +#undef SERDES_L3_TM_DIG_10_OFFSET +#define SERDES_L3_TM_DIG_10_OFFSET 0XFD40D07C #undef SERDES_L0_TM_RST_DLY_OFFSET #define SERDES_L0_TM_RST_DLY_OFFSET 0XFD4019A4 #undef SERDES_L0_TM_ANA_BYP_15_OFFSET @@ -25454,6 +32991,24 @@ #define SERDES_L3_TM_ANA_BYP_15_OFFSET 0XFD40D038 #undef SERDES_L3_TM_ANA_BYP_12_OFFSET #define SERDES_L3_TM_ANA_BYP_12_OFFSET 0XFD40D02C +#undef SERDES_L0_TM_MISC3_OFFSET +#define SERDES_L0_TM_MISC3_OFFSET 0XFD4019AC +#undef SERDES_L1_TM_MISC3_OFFSET +#define SERDES_L1_TM_MISC3_OFFSET 0XFD4059AC +#undef SERDES_L2_TM_MISC3_OFFSET +#define SERDES_L2_TM_MISC3_OFFSET 0XFD4099AC +#undef SERDES_L3_TM_MISC3_OFFSET +#define SERDES_L3_TM_MISC3_OFFSET 0XFD40D9AC +#undef SERDES_L0_TM_EQ11_OFFSET +#define SERDES_L0_TM_EQ11_OFFSET 0XFD401978 +#undef SERDES_L1_TM_EQ11_OFFSET +#define SERDES_L1_TM_EQ11_OFFSET 0XFD405978 +#undef SERDES_L2_TM_EQ11_OFFSET +#define SERDES_L2_TM_EQ11_OFFSET 0XFD409978 +#undef SERDES_L3_TM_EQ11_OFFSET +#define SERDES_L3_TM_EQ11_OFFSET 0XFD40D978 +#undef SIOU_ECO_0_OFFSET +#define SIOU_ECO_0_OFFSET 0XFD3D001C #undef SERDES_ICM_CFG0_OFFSET #define SERDES_ICM_CFG0_OFFSET 0XFD410010 #undef SERDES_ICM_CFG1_OFFSET @@ -25479,1055 +33034,1511 @@ #undef SERDES_L3_TX_ANA_TM_18_OFFSET #define SERDES_L3_TX_ANA_TM_18_OFFSET 0XFD40C048 -/*PLL0 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - - 4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135 - Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved*/ +/* +* PLL0 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 1 + * 2MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 24MHz, 0x8 - 26MHz, + * 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE + * - 108MHz, 0xF - 125MHz, 0x10 - 135MHz, 0x11 - 150 MHz. 0x12 to 0x1F - R + * eserved +*/ #undef SERDES_PLL_REF_SEL0_PLLREFSEL0_DEFVAL #undef SERDES_PLL_REF_SEL0_PLLREFSEL0_SHIFT #undef SERDES_PLL_REF_SEL0_PLLREFSEL0_MASK -#define SERDES_PLL_REF_SEL0_PLLREFSEL0_DEFVAL 0x0000000D -#define SERDES_PLL_REF_SEL0_PLLREFSEL0_SHIFT 0 -#define SERDES_PLL_REF_SEL0_PLLREFSEL0_MASK 0x0000001FU +#define SERDES_PLL_REF_SEL0_PLLREFSEL0_DEFVAL 0x0000000D +#define SERDES_PLL_REF_SEL0_PLLREFSEL0_SHIFT 0 +#define SERDES_PLL_REF_SEL0_PLLREFSEL0_MASK 0x0000001FU -/*PLL1 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - - 4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135 - Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved*/ +/* +* PLL1 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 1 + * 2MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 24MHz, 0x8 - 26MHz, + * 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE + * - 108MHz, 0xF - 125MHz, 0x10 - 135MHz, 0x11 - 150 MHz. 0x12 to 0x1F - R + * eserved +*/ #undef SERDES_PLL_REF_SEL1_PLLREFSEL1_DEFVAL #undef SERDES_PLL_REF_SEL1_PLLREFSEL1_SHIFT #undef SERDES_PLL_REF_SEL1_PLLREFSEL1_MASK -#define SERDES_PLL_REF_SEL1_PLLREFSEL1_DEFVAL 0x00000008 -#define SERDES_PLL_REF_SEL1_PLLREFSEL1_SHIFT 0 -#define SERDES_PLL_REF_SEL1_PLLREFSEL1_MASK 0x0000001FU +#define SERDES_PLL_REF_SEL1_PLLREFSEL1_DEFVAL 0x00000008 +#define SERDES_PLL_REF_SEL1_PLLREFSEL1_SHIFT 0 +#define SERDES_PLL_REF_SEL1_PLLREFSEL1_MASK 0x0000001FU -/*PLL2 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - - 4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135 - Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved*/ +/* +* PLL2 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 1 + * 2MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 24MHz, 0x8 - 26MHz, + * 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE + * - 108MHz, 0xF - 125MHz, 0x10 - 135MHz, 0x11 - 150 MHz. 0x12 to 0x1F - R + * eserved +*/ #undef SERDES_PLL_REF_SEL2_PLLREFSEL2_DEFVAL #undef SERDES_PLL_REF_SEL2_PLLREFSEL2_SHIFT #undef SERDES_PLL_REF_SEL2_PLLREFSEL2_MASK -#define SERDES_PLL_REF_SEL2_PLLREFSEL2_DEFVAL 0x0000000F -#define SERDES_PLL_REF_SEL2_PLLREFSEL2_SHIFT 0 -#define SERDES_PLL_REF_SEL2_PLLREFSEL2_MASK 0x0000001FU +#define SERDES_PLL_REF_SEL2_PLLREFSEL2_DEFVAL 0x0000000F +#define SERDES_PLL_REF_SEL2_PLLREFSEL2_SHIFT 0 +#define SERDES_PLL_REF_SEL2_PLLREFSEL2_MASK 0x0000001FU -/*PLL3 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - - 4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135 - Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved*/ +/* +* PLL3 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 1 + * 2MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 24MHz, 0x8 - 26MHz, + * 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE + * - 108MHz, 0xF - 125MHz, 0x10 - 135MHz, 0x11 - 150 MHz. 0x12 to 0x1F - R + * eserved +*/ #undef SERDES_PLL_REF_SEL3_PLLREFSEL3_DEFVAL #undef SERDES_PLL_REF_SEL3_PLLREFSEL3_SHIFT #undef SERDES_PLL_REF_SEL3_PLLREFSEL3_MASK -#define SERDES_PLL_REF_SEL3_PLLREFSEL3_DEFVAL 0x0000000E -#define SERDES_PLL_REF_SEL3_PLLREFSEL3_SHIFT 0 -#define SERDES_PLL_REF_SEL3_PLLREFSEL3_MASK 0x0000001FU +#define SERDES_PLL_REF_SEL3_PLLREFSEL3_DEFVAL 0x0000000E +#define SERDES_PLL_REF_SEL3_PLLREFSEL3_SHIFT 0 +#define SERDES_PLL_REF_SEL3_PLLREFSEL3_MASK 0x0000001FU -/*Sel of lane 0 ref clock local mux. Set to 1 to select lane 0 slicer output. Set to 0 to select lane0 ref clock mux output.*/ +/* +* Sel of lane 0 ref clock local mux. Set to 1 to select lane 0 slicer outp + * ut. Set to 0 to select lane0 ref clock mux output. +*/ #undef SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_DEFVAL #undef SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_SHIFT #undef SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_MASK -#define SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_DEFVAL 0x00000080 -#define SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_SHIFT 7 -#define SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_MASK 0x00000080U +#define SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_DEFVAL 0x00000080 +#define SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_SHIFT 7 +#define SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_MASK 0x00000080U -/*Sel of lane 1 ref clock local mux. Set to 1 to select lane 1 slicer output. Set to 0 to select lane1 ref clock mux output.*/ +/* +* Sel of lane 1 ref clock local mux. Set to 1 to select lane 1 slicer outp + * ut. Set to 0 to select lane1 ref clock mux output. +*/ #undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_DEFVAL #undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_SHIFT #undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_MASK -#define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_DEFVAL 0x00000080 -#define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_SHIFT 7 -#define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_MASK 0x00000080U +#define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_DEFVAL 0x00000080 +#define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_SHIFT 7 +#define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_MASK 0x00000080U -/*Bit 3 of lane 1 ref clock mux one hot sel. Set to 1 to select lane 3 slicer output from ref clock network*/ +/* +* Bit 3 of lane 1 ref clock mux one hot sel. Set to 1 to select lane 3 sli + * cer output from ref clock network +*/ #undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_DEFVAL #undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_SHIFT #undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_MASK -#define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_DEFVAL 0x00000080 -#define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_SHIFT 3 -#define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_MASK 0x00000008U +#define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_DEFVAL 0x00000080 +#define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_SHIFT 3 +#define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_MASK 0x00000008U -/*Sel of lane 2 ref clock local mux. Set to 1 to select lane 1 slicer output. Set to 0 to select lane2 ref clock mux output.*/ +/* +* Sel of lane 2 ref clock local mux. Set to 1 to select lane 1 slicer outp + * ut. Set to 0 to select lane2 ref clock mux output. +*/ #undef SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_DEFVAL #undef SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_SHIFT #undef SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_MASK -#define SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_DEFVAL 0x00000080 -#define SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_SHIFT 7 -#define SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_MASK 0x00000080U +#define SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_DEFVAL 0x00000080 +#define SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_SHIFT 7 +#define SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_MASK 0x00000080U -/*Sel of lane 3 ref clock local mux. Set to 1 to select lane 3 slicer output. Set to 0 to select lane3 ref clock mux output.*/ +/* +* Sel of lane 3 ref clock local mux. Set to 1 to select lane 3 slicer outp + * ut. Set to 0 to select lane3 ref clock mux output. +*/ #undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_DEFVAL #undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_SHIFT #undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_MASK -#define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_DEFVAL 0x00000080 -#define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_SHIFT 7 -#define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_MASK 0x00000080U +#define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_DEFVAL 0x00000080 +#define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_SHIFT 7 +#define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_MASK 0x00000080U -/*Bit 1 of lane 3 ref clock mux one hot sel. Set to 1 to select lane 1 slicer output from ref clock network*/ +/* +* Bit 1 of lane 3 ref clock mux one hot sel. Set to 1 to select lane 1 sli + * cer output from ref clock network +*/ #undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_DEFVAL #undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_SHIFT #undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_MASK -#define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_DEFVAL 0x00000080 -#define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_SHIFT 1 -#define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_MASK 0x00000002U +#define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_DEFVAL 0x00000080 +#define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_SHIFT 1 +#define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_MASK 0x00000002U -/*Enable/Disable coarse code satureation limiting logic*/ +/* +* Enable/Disable coarse code satureation limiting logic +*/ #undef SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_DEFVAL #undef SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_SHIFT #undef SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_MASK -#define SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_DEFVAL 0x00000000 -#define SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_SHIFT 4 -#define SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_MASK 0x00000010U +#define SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_DEFVAL 0x00000000 +#define SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_SHIFT 4 +#define SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_MASK 0x00000010U -/*Spread Spectrum No of Steps [7:0]*/ +/* +* Spread Spectrum No of Steps [7:0] +*/ #undef SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL #undef SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT #undef SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK -#define SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL 0x00000000 -#define SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT 0 -#define SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK 0x000000FFU +#define SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL 0x00000000 +#define SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT 0 +#define SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK 0x000000FFU -/*Spread Spectrum No of Steps [10:8]*/ +/* +* Spread Spectrum No of Steps [10:8] +*/ #undef SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL #undef SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT #undef SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK -#define SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL 0x00000000 -#define SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT 0 -#define SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK 0x00000007U +#define SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL 0x00000000 +#define SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT 0 +#define SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK 0x00000007U -/*Spread Spectrum No of Steps [7:0]*/ +/* +* Spread Spectrum No of Steps [7:0] +*/ #undef SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL #undef SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT #undef SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK -#define SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL 0x00000000 -#define SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT 0 -#define SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK 0x000000FFU +#define SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL 0x00000000 +#define SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT 0 +#define SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK 0x000000FFU -/*Spread Spectrum No of Steps [10:8]*/ +/* +* Spread Spectrum No of Steps [10:8] +*/ #undef SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL #undef SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT #undef SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK -#define SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL 0x00000000 -#define SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT 0 -#define SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK 0x00000007U +#define SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL 0x00000000 +#define SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT 0 +#define SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK 0x00000007U -/*Spread Spectrum No of Steps [7:0]*/ +/* +* Spread Spectrum No of Steps [7:0] +*/ #undef SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL #undef SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT #undef SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK -#define SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL 0x00000000 -#define SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT 0 -#define SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK 0x000000FFU +#define SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL 0x00000000 +#define SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT 0 +#define SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK 0x000000FFU -/*Spread Spectrum No of Steps [10:8]*/ +/* +* Spread Spectrum No of Steps [10:8] +*/ #undef SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL #undef SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT #undef SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK -#define SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL 0x00000000 -#define SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT 0 -#define SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK 0x00000007U +#define SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL 0x00000000 +#define SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT 0 +#define SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK 0x00000007U -/*Step Size for Spread Spectrum [7:0]*/ +/* +* Step Size for Spread Spectrum [7:0] +*/ #undef SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL #undef SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT #undef SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK -#define SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL 0x00000000 -#define SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT 0 -#define SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK 0x000000FFU +#define SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL 0x00000000 +#define SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT 0 +#define SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK 0x000000FFU -/*Step Size for Spread Spectrum [15:8]*/ +/* +* Step Size for Spread Spectrum [15:8] +*/ #undef SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL #undef SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT #undef SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK -#define SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL 0x00000000 -#define SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT 0 -#define SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK 0x000000FFU +#define SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL 0x00000000 +#define SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT 0 +#define SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK 0x000000FFU -/*Step Size for Spread Spectrum [23:16]*/ +/* +* Step Size for Spread Spectrum [23:16] +*/ #undef SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL #undef SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT #undef SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK -#define SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL 0x00000000 -#define SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT 0 -#define SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK 0x000000FFU +#define SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL 0x00000000 +#define SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT 0 +#define SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK 0x000000FFU -/*Step Size for Spread Spectrum [25:24]*/ +/* +* Step Size for Spread Spectrum [25:24] +*/ #undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL #undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT #undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK -#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL 0x00000000 -#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT 0 -#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK 0x00000003U +#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL 0x00000000 +#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT 0 +#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK 0x00000003U -/*Enable/Disable test mode force on SS step size*/ +/* +* Enable/Disable test mode force on SS step size +*/ #undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL #undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT #undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK -#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL 0x00000000 -#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT 4 -#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK 0x00000010U +#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL 0x00000000 +#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT 4 +#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK 0x00000010U -/*Enable/Disable test mode force on SS no of steps*/ +/* +* Enable/Disable test mode force on SS no of steps +*/ #undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL #undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT #undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK -#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL 0x00000000 -#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT 5 -#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK 0x00000020U +#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL 0x00000000 +#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT 5 +#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK 0x00000020U -/*Step Size for Spread Spectrum [7:0]*/ +/* +* Step Size for Spread Spectrum [7:0] +*/ #undef SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL #undef SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT #undef SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK -#define SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL 0x00000000 -#define SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT 0 -#define SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK 0x000000FFU +#define SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL 0x00000000 +#define SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT 0 +#define SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK 0x000000FFU -/*Step Size for Spread Spectrum [15:8]*/ +/* +* Step Size for Spread Spectrum [15:8] +*/ #undef SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL #undef SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT #undef SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK -#define SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL 0x00000000 -#define SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT 0 -#define SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK 0x000000FFU +#define SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL 0x00000000 +#define SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT 0 +#define SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK 0x000000FFU -/*Step Size for Spread Spectrum [23:16]*/ +/* +* Step Size for Spread Spectrum [23:16] +*/ #undef SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL #undef SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT #undef SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK -#define SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL 0x00000000 -#define SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT 0 -#define SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK 0x000000FFU +#define SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL 0x00000000 +#define SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT 0 +#define SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK 0x000000FFU -/*Step Size for Spread Spectrum [25:24]*/ +/* +* Step Size for Spread Spectrum [25:24] +*/ #undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL #undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT #undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK -#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL 0x00000000 -#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT 0 -#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK 0x00000003U +#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL 0x00000000 +#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT 0 +#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK 0x00000003U -/*Enable/Disable test mode force on SS step size*/ +/* +* Enable/Disable test mode force on SS step size +*/ #undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL #undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT #undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK -#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL 0x00000000 -#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT 4 -#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK 0x00000010U +#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL 0x00000000 +#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT 4 +#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK 0x00000010U -/*Enable/Disable test mode force on SS no of steps*/ +/* +* Enable/Disable test mode force on SS no of steps +*/ #undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL #undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT #undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK -#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL 0x00000000 -#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT 5 -#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK 0x00000020U +#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL 0x00000000 +#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT 5 +#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK 0x00000020U -/*Step Size for Spread Spectrum [7:0]*/ +/* +* Step Size for Spread Spectrum [7:0] +*/ #undef SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL #undef SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT #undef SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK -#define SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL 0x00000000 -#define SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT 0 -#define SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK 0x000000FFU +#define SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL 0x00000000 +#define SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT 0 +#define SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK 0x000000FFU -/*Step Size for Spread Spectrum [15:8]*/ +/* +* Step Size for Spread Spectrum [15:8] +*/ #undef SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL #undef SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT #undef SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK -#define SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL 0x00000000 -#define SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT 0 -#define SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK 0x000000FFU +#define SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL 0x00000000 +#define SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT 0 +#define SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK 0x000000FFU -/*Step Size for Spread Spectrum [23:16]*/ +/* +* Step Size for Spread Spectrum [23:16] +*/ #undef SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL #undef SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT #undef SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK -#define SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL 0x00000000 -#define SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT 0 -#define SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK 0x000000FFU +#define SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL 0x00000000 +#define SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT 0 +#define SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK 0x000000FFU -/*Step Size for Spread Spectrum [25:24]*/ +/* +* Step Size for Spread Spectrum [25:24] +*/ #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK -#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL 0x00000000 -#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT 0 -#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK 0x00000003U +#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL 0x00000000 +#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT 0 +#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK 0x00000003U -/*Enable/Disable test mode force on SS step size*/ +/* +* Enable/Disable test mode force on SS step size +*/ #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK -#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL 0x00000000 -#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT 4 -#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK 0x00000010U +#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL 0x00000000 +#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT 4 +#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK 0x00000010U -/*Enable/Disable test mode force on SS no of steps*/ +/* +* Enable/Disable test mode force on SS no of steps +*/ #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK -#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL 0x00000000 -#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT 5 -#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK 0x00000020U +#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL 0x00000000 +#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT 5 +#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK 0x00000020U -/*Enable test mode forcing on enable Spread Spectrum*/ +/* +* Enable test mode forcing on enable Spread Spectrum +*/ #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_DEFVAL #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_SHIFT #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_MASK -#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_DEFVAL 0x00000000 -#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_SHIFT 7 -#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_MASK 0x00000080U +#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_DEFVAL 0x00000000 +#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_SHIFT 7 +#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_MASK 0x00000080U -/*Bypass Descrambler*/ +/* +* Bypass Descrambler +*/ #undef SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_DEFVAL #undef SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_SHIFT #undef SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_MASK -#define SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_DEFVAL 0x00000000 -#define SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_SHIFT 1 -#define SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_MASK 0x00000002U +#define SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_DEFVAL 0x00000000 +#define SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_SHIFT 1 +#define SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_MASK 0x00000002U -/*Enable Bypass for <1> TM_DIG_CTRL_6*/ +/* +* Enable Bypass for <1> TM_DIG_CTRL_6 +*/ #undef SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_DEFVAL #undef SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_SHIFT #undef SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_MASK -#define SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_DEFVAL 0x00000000 -#define SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_SHIFT 0 -#define SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_MASK 0x00000001U +#define SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_DEFVAL 0x00000000 +#define SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_SHIFT 0 +#define SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_MASK 0x00000001U -/*Bypass scrambler signal*/ +/* +* Bypass scrambler signal +*/ #undef SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_DEFVAL #undef SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_SHIFT #undef SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_MASK -#define SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_DEFVAL 0x00000000 -#define SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_SHIFT 1 -#define SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_MASK 0x00000002U +#define SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_DEFVAL 0x00000000 +#define SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_SHIFT 1 +#define SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_MASK 0x00000002U -/*Enable/disable scrambler bypass signal*/ +/* +* Enable/disable scrambler bypass signal +*/ #undef SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_DEFVAL #undef SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_SHIFT #undef SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_MASK -#define SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_DEFVAL 0x00000000 -#define SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_SHIFT 0 -#define SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_MASK 0x00000001U +#define SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_DEFVAL 0x00000000 +#define SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_SHIFT 0 +#define SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_MASK 0x00000001U -/*Enable test mode force on fractional mode enable*/ +/* +* Enable test mode force on fractional mode enable +*/ #undef SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_DEFVAL #undef SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_SHIFT #undef SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_MASK -#define SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_DEFVAL 0x00000000 -#define SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_SHIFT 6 -#define SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_MASK 0x00000040U +#define SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_DEFVAL 0x00000000 +#define SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_SHIFT 6 +#define SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_MASK 0x00000040U -/*Bypass 8b10b decoder*/ +/* +* Bypass 8b10b decoder +*/ #undef SERDES_L3_TM_DIG_6_BYPASS_DECODER_DEFVAL #undef SERDES_L3_TM_DIG_6_BYPASS_DECODER_SHIFT #undef SERDES_L3_TM_DIG_6_BYPASS_DECODER_MASK -#define SERDES_L3_TM_DIG_6_BYPASS_DECODER_DEFVAL 0x00000000 -#define SERDES_L3_TM_DIG_6_BYPASS_DECODER_SHIFT 3 -#define SERDES_L3_TM_DIG_6_BYPASS_DECODER_MASK 0x00000008U +#define SERDES_L3_TM_DIG_6_BYPASS_DECODER_DEFVAL 0x00000000 +#define SERDES_L3_TM_DIG_6_BYPASS_DECODER_SHIFT 3 +#define SERDES_L3_TM_DIG_6_BYPASS_DECODER_MASK 0x00000008U -/*Enable Bypass for <3> TM_DIG_CTRL_6*/ +/* +* Enable Bypass for <3> TM_DIG_CTRL_6 +*/ #undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_DEFVAL #undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_SHIFT #undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_MASK -#define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_DEFVAL 0x00000000 -#define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_SHIFT 2 -#define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_MASK 0x00000004U +#define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_DEFVAL 0x00000000 +#define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_SHIFT 2 +#define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_MASK 0x00000004U -/*Bypass Descrambler*/ +/* +* Bypass Descrambler +*/ #undef SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_DEFVAL #undef SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_SHIFT #undef SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_MASK -#define SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_DEFVAL 0x00000000 -#define SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_SHIFT 1 -#define SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_MASK 0x00000002U +#define SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_DEFVAL 0x00000000 +#define SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_SHIFT 1 +#define SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_MASK 0x00000002U -/*Enable Bypass for <1> TM_DIG_CTRL_6*/ +/* +* Enable Bypass for <1> TM_DIG_CTRL_6 +*/ #undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_DEFVAL #undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_SHIFT #undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_MASK -#define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_DEFVAL 0x00000000 -#define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_SHIFT 0 -#define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_MASK 0x00000001U +#define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_DEFVAL 0x00000000 +#define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_SHIFT 0 +#define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_MASK 0x00000001U -/*Enable/disable encoder bypass signal*/ +/* +* Enable/disable encoder bypass signal +*/ #undef SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_DEFVAL #undef SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_SHIFT #undef SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_MASK -#define SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_DEFVAL 0x00000000 -#define SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_SHIFT 3 -#define SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_MASK 0x00000008U +#define SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_DEFVAL 0x00000000 +#define SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_SHIFT 3 +#define SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_MASK 0x00000008U -/*Bypass scrambler signal*/ +/* +* Bypass scrambler signal +*/ #undef SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_DEFVAL #undef SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_SHIFT #undef SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_MASK -#define SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_DEFVAL 0x00000000 -#define SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_SHIFT 1 -#define SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_MASK 0x00000002U +#define SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_DEFVAL 0x00000000 +#define SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_SHIFT 1 +#define SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_MASK 0x00000002U -/*Enable/disable scrambler bypass signal*/ +/* +* Enable/disable scrambler bypass signal +*/ #undef SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_DEFVAL #undef SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_SHIFT #undef SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_MASK -#define SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_DEFVAL 0x00000000 -#define SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_SHIFT 0 -#define SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_MASK 0x00000001U +#define SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_DEFVAL 0x00000000 +#define SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_SHIFT 0 +#define SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_MASK 0x00000001U -/*PHY Mode: 4'b000 - PCIe, 4'b001 - USB3, 4'b0010 - SATA, 4'b0100 - SGMII, 4'b0101 - DP, 4'b1000 - MPHY*/ -#undef SERDES_L3_TXPMA_ST_0_TX_PHY_MODE_DEFVAL -#undef SERDES_L3_TXPMA_ST_0_TX_PHY_MODE_SHIFT -#undef SERDES_L3_TXPMA_ST_0_TX_PHY_MODE_MASK -#define SERDES_L3_TXPMA_ST_0_TX_PHY_MODE_DEFVAL 0x00000001 -#define SERDES_L3_TXPMA_ST_0_TX_PHY_MODE_SHIFT 4 -#define SERDES_L3_TXPMA_ST_0_TX_PHY_MODE_MASK 0x000000F0U - -/*Spare- not used*/ +/* +* Spare- not used +*/ #undef SERDES_L0_TM_AUX_0_BIT_2_DEFVAL #undef SERDES_L0_TM_AUX_0_BIT_2_SHIFT #undef SERDES_L0_TM_AUX_0_BIT_2_MASK -#define SERDES_L0_TM_AUX_0_BIT_2_DEFVAL 0x00000000 -#define SERDES_L0_TM_AUX_0_BIT_2_SHIFT 5 -#define SERDES_L0_TM_AUX_0_BIT_2_MASK 0x00000020U +#define SERDES_L0_TM_AUX_0_BIT_2_DEFVAL 0x00000000 +#define SERDES_L0_TM_AUX_0_BIT_2_SHIFT 5 +#define SERDES_L0_TM_AUX_0_BIT_2_MASK 0x00000020U -/*Spare- not used*/ +/* +* Spare- not used +*/ #undef SERDES_L2_TM_AUX_0_BIT_2_DEFVAL #undef SERDES_L2_TM_AUX_0_BIT_2_SHIFT #undef SERDES_L2_TM_AUX_0_BIT_2_MASK -#define SERDES_L2_TM_AUX_0_BIT_2_DEFVAL 0x00000000 -#define SERDES_L2_TM_AUX_0_BIT_2_SHIFT 5 -#define SERDES_L2_TM_AUX_0_BIT_2_MASK 0x00000020U +#define SERDES_L2_TM_AUX_0_BIT_2_DEFVAL 0x00000000 +#define SERDES_L2_TM_AUX_0_BIT_2_SHIFT 5 +#define SERDES_L2_TM_AUX_0_BIT_2_MASK 0x00000020U -/*Enable Eye Surf*/ +/* +* Enable Eye Surf +*/ #undef SERDES_L0_TM_DIG_8_EYESURF_ENABLE_DEFVAL #undef SERDES_L0_TM_DIG_8_EYESURF_ENABLE_SHIFT #undef SERDES_L0_TM_DIG_8_EYESURF_ENABLE_MASK -#define SERDES_L0_TM_DIG_8_EYESURF_ENABLE_DEFVAL 0x00000000 -#define SERDES_L0_TM_DIG_8_EYESURF_ENABLE_SHIFT 4 -#define SERDES_L0_TM_DIG_8_EYESURF_ENABLE_MASK 0x00000010U +#define SERDES_L0_TM_DIG_8_EYESURF_ENABLE_DEFVAL 0x00000000 +#define SERDES_L0_TM_DIG_8_EYESURF_ENABLE_SHIFT 4 +#define SERDES_L0_TM_DIG_8_EYESURF_ENABLE_MASK 0x00000010U -/*Enable Eye Surf*/ +/* +* Enable Eye Surf +*/ #undef SERDES_L1_TM_DIG_8_EYESURF_ENABLE_DEFVAL #undef SERDES_L1_TM_DIG_8_EYESURF_ENABLE_SHIFT #undef SERDES_L1_TM_DIG_8_EYESURF_ENABLE_MASK -#define SERDES_L1_TM_DIG_8_EYESURF_ENABLE_DEFVAL 0x00000000 -#define SERDES_L1_TM_DIG_8_EYESURF_ENABLE_SHIFT 4 -#define SERDES_L1_TM_DIG_8_EYESURF_ENABLE_MASK 0x00000010U +#define SERDES_L1_TM_DIG_8_EYESURF_ENABLE_DEFVAL 0x00000000 +#define SERDES_L1_TM_DIG_8_EYESURF_ENABLE_SHIFT 4 +#define SERDES_L1_TM_DIG_8_EYESURF_ENABLE_MASK 0x00000010U -/*Enable Eye Surf*/ +/* +* Enable Eye Surf +*/ #undef SERDES_L2_TM_DIG_8_EYESURF_ENABLE_DEFVAL #undef SERDES_L2_TM_DIG_8_EYESURF_ENABLE_SHIFT #undef SERDES_L2_TM_DIG_8_EYESURF_ENABLE_MASK -#define SERDES_L2_TM_DIG_8_EYESURF_ENABLE_DEFVAL 0x00000000 -#define SERDES_L2_TM_DIG_8_EYESURF_ENABLE_SHIFT 4 -#define SERDES_L2_TM_DIG_8_EYESURF_ENABLE_MASK 0x00000010U +#define SERDES_L2_TM_DIG_8_EYESURF_ENABLE_DEFVAL 0x00000000 +#define SERDES_L2_TM_DIG_8_EYESURF_ENABLE_SHIFT 4 +#define SERDES_L2_TM_DIG_8_EYESURF_ENABLE_MASK 0x00000010U -/*Enable Eye Surf*/ +/* +* Enable Eye Surf +*/ #undef SERDES_L3_TM_DIG_8_EYESURF_ENABLE_DEFVAL #undef SERDES_L3_TM_DIG_8_EYESURF_ENABLE_SHIFT #undef SERDES_L3_TM_DIG_8_EYESURF_ENABLE_MASK -#define SERDES_L3_TM_DIG_8_EYESURF_ENABLE_DEFVAL 0x00000000 -#define SERDES_L3_TM_DIG_8_EYESURF_ENABLE_SHIFT 4 -#define SERDES_L3_TM_DIG_8_EYESURF_ENABLE_MASK 0x00000010U +#define SERDES_L3_TM_DIG_8_EYESURF_ENABLE_DEFVAL 0x00000000 +#define SERDES_L3_TM_DIG_8_EYESURF_ENABLE_SHIFT 4 +#define SERDES_L3_TM_DIG_8_EYESURF_ENABLE_MASK 0x00000010U -/*ILL calib counts BYPASSED with calcode bits*/ +/* +* ILL calib counts BYPASSED with calcode bits +*/ #undef SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL #undef SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT #undef SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK -#define SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL 0x00000000 -#define SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT 7 -#define SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK 0x00000080U +#define SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL 0x00000000 +#define SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT 7 +#define SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK 0x00000080U -/*IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS*/ +/* +* IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , + * USB3 : SS +*/ #undef SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL #undef SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT #undef SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK -#define SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL 0x00000000 -#define SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT 0 -#define SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK 0x000000FFU +#define SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL 0x00000000 +#define SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT 0 +#define SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK 0x000000FFU -/*IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2*/ +/* +* IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 +*/ #undef SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL #undef SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT #undef SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK -#define SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL 0x00000000 -#define SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT 0 -#define SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK 0x000000FFU +#define SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL 0x00000000 +#define SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT 0 +#define SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK 0x000000FFU -/*G1A pll ctr bypass value*/ +/* +* G1A pll ctr bypass value +*/ #undef SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL #undef SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT #undef SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK -#define SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL 0x00000000 -#define SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT 0 -#define SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK 0x000000FFU +#define SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL 0x00000000 +#define SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT 0 +#define SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK 0x000000FFU -/*E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS*/ +/* +* E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , U + * SB3 : SS +*/ #undef SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL #undef SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT #undef SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK -#define SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL 0x00000000 -#define SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT 0 -#define SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK 0x000000FFU +#define SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL 0x00000000 +#define SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT 0 +#define SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK 0x000000FFU -/*E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2*/ +/* +* E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 +*/ #undef SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL #undef SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT #undef SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK -#define SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL 0x00000000 -#define SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT 0 -#define SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK 0x000000FFU +#define SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL 0x00000000 +#define SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT 0 +#define SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK 0x000000FFU -/*IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3*/ +/* +* IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 +*/ #undef SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL #undef SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT #undef SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK -#define SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL 0x00000000 -#define SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT 0 -#define SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK 0x000000FFU +#define SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL 0x00000000 +#define SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT 0 +#define SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK 0x000000FFU -/*E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3*/ +/* +* E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 +*/ #undef SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL #undef SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT #undef SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK -#define SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL 0x00000000 -#define SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT 0 -#define SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK 0x000000FFU +#define SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL 0x00000000 +#define SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT 0 +#define SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK 0x000000FFU -/*ILL calibration code change wait time*/ +/* +* ILL calibration code change wait time +*/ #undef SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL #undef SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT #undef SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_MASK -#define SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL 0x00000002 -#define SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT 0 -#define SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_MASK 0x000000FFU +#define SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL 0x00000002 +#define SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT 0 +#define SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_MASK 0x000000FFU -/*IQ ILL polytrim bypass value*/ +/* +* IQ ILL polytrim bypass value +*/ #undef SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL #undef SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT #undef SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK -#define SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL 0x00000000 -#define SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT 0 -#define SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK 0x000000FFU +#define SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL 0x00000000 +#define SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT 0 +#define SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK 0x000000FFU -/*bypass IQ polytrim*/ +/* +* bypass IQ polytrim +*/ #undef SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL #undef SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT #undef SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK -#define SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL 0x00000000 -#define SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT 0 -#define SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK 0x00000001U +#define SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL 0x00000000 +#define SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT 0 +#define SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK 0x00000001U -/*E ILL polytrim bypass value*/ +/* +* E ILL polytrim bypass value +*/ #undef SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL #undef SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT #undef SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK -#define SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL 0x00000000 -#define SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT 0 -#define SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK 0x000000FFU +#define SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL 0x00000000 +#define SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT 0 +#define SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK 0x000000FFU -/*bypass E polytrim*/ +/* +* bypass E polytrim +*/ #undef SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL #undef SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT #undef SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK -#define SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL 0x00000000 -#define SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT 0 -#define SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK 0x00000001U +#define SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL 0x00000000 +#define SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT 0 +#define SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK 0x00000001U -/*ILL calib counts BYPASSED with calcode bits*/ +/* +* ILL cal idle val refcnt +*/ +#undef SERDES_L0_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_DEFVAL +#undef SERDES_L0_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_SHIFT +#undef SERDES_L0_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_MASK +#define SERDES_L0_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_DEFVAL 0x00000001 +#define SERDES_L0_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_SHIFT 0 +#define SERDES_L0_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_MASK 0x00000007U + +/* +* ILL cal idle val refcnt +*/ +#undef SERDES_L1_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_DEFVAL +#undef SERDES_L1_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_SHIFT +#undef SERDES_L1_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_MASK +#define SERDES_L1_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_DEFVAL 0x00000001 +#define SERDES_L1_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_SHIFT 0 +#define SERDES_L1_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_MASK 0x00000007U + +/* +* ILL calib counts BYPASSED with calcode bits +*/ #undef SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL #undef SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT #undef SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK -#define SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL 0x00000000 -#define SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT 7 -#define SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK 0x00000080U +#define SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL 0x00000000 +#define SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT 7 +#define SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK 0x00000080U -/*IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS*/ +/* +* IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , + * USB3 : SS +*/ #undef SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL #undef SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT #undef SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK -#define SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL 0x00000000 -#define SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT 0 -#define SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK 0x000000FFU +#define SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL 0x00000000 +#define SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT 0 +#define SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK 0x000000FFU -/*IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2*/ +/* +* IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 +*/ #undef SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL #undef SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT #undef SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK -#define SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL 0x00000000 -#define SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT 0 -#define SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK 0x000000FFU +#define SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL 0x00000000 +#define SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT 0 +#define SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK 0x000000FFU -/*G1A pll ctr bypass value*/ +/* +* G1A pll ctr bypass value +*/ #undef SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL #undef SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT #undef SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK -#define SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL 0x00000000 -#define SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT 0 -#define SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK 0x000000FFU +#define SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL 0x00000000 +#define SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT 0 +#define SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK 0x000000FFU -/*E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS*/ +/* +* E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , U + * SB3 : SS +*/ #undef SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL #undef SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT #undef SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK -#define SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL 0x00000000 -#define SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT 0 -#define SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK 0x000000FFU +#define SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL 0x00000000 +#define SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT 0 +#define SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK 0x000000FFU -/*E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2*/ +/* +* E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 +*/ #undef SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL #undef SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT #undef SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK -#define SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL 0x00000000 -#define SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT 0 -#define SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK 0x000000FFU +#define SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL 0x00000000 +#define SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT 0 +#define SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK 0x000000FFU -/*IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3*/ +/* +* IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 +*/ #undef SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL #undef SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT #undef SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK -#define SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL 0x00000000 -#define SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT 0 -#define SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK 0x000000FFU +#define SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL 0x00000000 +#define SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT 0 +#define SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK 0x000000FFU -/*E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3*/ +/* +* E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 +*/ #undef SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL #undef SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT #undef SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK -#define SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL 0x00000000 -#define SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT 0 -#define SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK 0x000000FFU +#define SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL 0x00000000 +#define SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT 0 +#define SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK 0x000000FFU -/*ILL calibration code change wait time*/ +/* +* ILL calibration code change wait time +*/ #undef SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL #undef SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT #undef SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_MASK -#define SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL 0x00000002 -#define SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT 0 -#define SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_MASK 0x000000FFU +#define SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL 0x00000002 +#define SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT 0 +#define SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_MASK 0x000000FFU -/*IQ ILL polytrim bypass value*/ +/* +* IQ ILL polytrim bypass value +*/ #undef SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL #undef SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT #undef SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK -#define SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL 0x00000000 -#define SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT 0 -#define SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK 0x000000FFU +#define SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL 0x00000000 +#define SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT 0 +#define SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK 0x000000FFU -/*bypass IQ polytrim*/ +/* +* bypass IQ polytrim +*/ #undef SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL #undef SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT #undef SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK -#define SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL 0x00000000 -#define SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT 0 -#define SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK 0x00000001U +#define SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL 0x00000000 +#define SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT 0 +#define SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK 0x00000001U -/*E ILL polytrim bypass value*/ +/* +* E ILL polytrim bypass value +*/ #undef SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL #undef SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT #undef SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK -#define SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL 0x00000000 -#define SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT 0 -#define SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK 0x000000FFU +#define SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL 0x00000000 +#define SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT 0 +#define SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK 0x000000FFU -/*bypass E polytrim*/ +/* +* bypass E polytrim +*/ #undef SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL #undef SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT #undef SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK -#define SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL 0x00000000 -#define SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT 0 -#define SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK 0x00000001U +#define SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL 0x00000000 +#define SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT 0 +#define SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK 0x00000001U -/*ILL calib counts BYPASSED with calcode bits*/ +/* +* ILL cal idle val refcnt +*/ +#undef SERDES_L2_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_DEFVAL +#undef SERDES_L2_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_SHIFT +#undef SERDES_L2_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_MASK +#define SERDES_L2_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_DEFVAL 0x00000001 +#define SERDES_L2_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_SHIFT 0 +#define SERDES_L2_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_MASK 0x00000007U + +/* +* ILL calib counts BYPASSED with calcode bits +*/ #undef SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL #undef SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT #undef SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK -#define SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL 0x00000000 -#define SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT 7 -#define SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK 0x00000080U +#define SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL 0x00000000 +#define SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT 7 +#define SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK 0x00000080U -/*IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS*/ +/* +* IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , + * USB3 : SS +*/ #undef SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL #undef SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT #undef SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK -#define SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL 0x00000000 -#define SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT 0 -#define SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK 0x000000FFU +#define SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL 0x00000000 +#define SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT 0 +#define SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK 0x000000FFU -/*IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2*/ +/* +* IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 +*/ #undef SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL #undef SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT #undef SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK -#define SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL 0x00000000 -#define SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT 0 -#define SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK 0x000000FFU +#define SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL 0x00000000 +#define SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT 0 +#define SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK 0x000000FFU -/*G1A pll ctr bypass value*/ +/* +* G1A pll ctr bypass value +*/ #undef SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL #undef SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT #undef SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK -#define SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL 0x00000000 -#define SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT 0 -#define SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK 0x000000FFU +#define SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL 0x00000000 +#define SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT 0 +#define SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK 0x000000FFU -/*E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS*/ +/* +* E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , U + * SB3 : SS +*/ #undef SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL #undef SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT #undef SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK -#define SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL 0x00000000 -#define SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT 0 -#define SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK 0x000000FFU +#define SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL 0x00000000 +#define SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT 0 +#define SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK 0x000000FFU -/*E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2*/ +/* +* E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 +*/ #undef SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL #undef SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT #undef SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK -#define SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL 0x00000000 -#define SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT 0 -#define SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK 0x000000FFU +#define SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL 0x00000000 +#define SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT 0 +#define SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK 0x000000FFU -/*G2A_PCIe1 PLL ctr bypass value*/ +/* +* G2A_PCIe1 PLL ctr bypass value +*/ #undef SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_DEFVAL #undef SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_SHIFT #undef SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_MASK -#define SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_DEFVAL 0x00000000 -#define SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_SHIFT 4 -#define SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_MASK 0x000000F0U +#define SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_DEFVAL 0x00000000 +#define SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_SHIFT 4 +#define SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_MASK 0x000000F0U -/*IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3*/ +/* +* IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 +*/ #undef SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL #undef SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT #undef SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK -#define SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL 0x00000000 -#define SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT 0 -#define SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK 0x000000FFU +#define SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL 0x00000000 +#define SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT 0 +#define SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK 0x000000FFU -/*E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3*/ +/* +* E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 +*/ #undef SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL #undef SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT #undef SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK -#define SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL 0x00000000 -#define SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT 0 -#define SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK 0x000000FFU +#define SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL 0x00000000 +#define SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT 0 +#define SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK 0x000000FFU -/*ILL calibration code change wait time*/ +/* +* ILL calibration code change wait time +*/ #undef SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL #undef SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT #undef SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_MASK -#define SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL 0x00000002 -#define SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT 0 -#define SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_MASK 0x000000FFU +#define SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL 0x00000002 +#define SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT 0 +#define SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_MASK 0x000000FFU -/*IQ ILL polytrim bypass value*/ +/* +* IQ ILL polytrim bypass value +*/ #undef SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL #undef SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT #undef SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK -#define SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL 0x00000000 -#define SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT 0 -#define SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK 0x000000FFU +#define SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL 0x00000000 +#define SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT 0 +#define SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK 0x000000FFU -/*bypass IQ polytrim*/ +/* +* bypass IQ polytrim +*/ #undef SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL #undef SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT #undef SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK -#define SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL 0x00000000 -#define SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT 0 -#define SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK 0x00000001U +#define SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL 0x00000000 +#define SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT 0 +#define SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK 0x00000001U -/*E ILL polytrim bypass value*/ +/* +* E ILL polytrim bypass value +*/ #undef SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL #undef SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT #undef SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK -#define SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL 0x00000000 -#define SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT 0 -#define SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK 0x000000FFU +#define SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL 0x00000000 +#define SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT 0 +#define SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK 0x000000FFU -/*bypass E polytrim*/ +/* +* bypass E polytrim +*/ #undef SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL #undef SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT #undef SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK -#define SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL 0x00000000 -#define SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT 0 -#define SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK 0x00000001U +#define SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL 0x00000000 +#define SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT 0 +#define SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK 0x00000001U -/*pre lock comma count threshold. 2'b 00 : 3, 2'b 01 : 5, 2'b 10 : 10, 2'b 11 : 20*/ -#undef SERDES_L0_TM_DIG_21_COMMA_PRE_LOCK_THRESH_DEFVAL -#undef SERDES_L0_TM_DIG_21_COMMA_PRE_LOCK_THRESH_SHIFT -#undef SERDES_L0_TM_DIG_21_COMMA_PRE_LOCK_THRESH_MASK -#define SERDES_L0_TM_DIG_21_COMMA_PRE_LOCK_THRESH_DEFVAL 0x00000000 -#define SERDES_L0_TM_DIG_21_COMMA_PRE_LOCK_THRESH_SHIFT 0 -#define SERDES_L0_TM_DIG_21_COMMA_PRE_LOCK_THRESH_MASK 0x00000003U +/* +* ILL cal idle val refcnt +*/ +#undef SERDES_L3_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_DEFVAL +#undef SERDES_L3_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_SHIFT +#undef SERDES_L3_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_MASK +#define SERDES_L3_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_DEFVAL 0x00000001 +#define SERDES_L3_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_SHIFT 0 +#define SERDES_L3_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_MASK 0x00000007U -/*CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001*/ +/* +* CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001 +*/ #undef SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL #undef SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT #undef SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK -#define SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL 0x00000001 -#define SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT 0 -#define SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK 0x0000000FU +#define SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL 0x00000001 +#define SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT 0 +#define SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK 0x0000000FU -/*Delay apb reset by specified amount*/ +/* +* CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001 +*/ +#undef SERDES_L1_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL +#undef SERDES_L1_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT +#undef SERDES_L1_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK +#define SERDES_L1_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL 0x00000001 +#define SERDES_L1_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT 0 +#define SERDES_L1_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK 0x0000000FU + +/* +* CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001 +*/ +#undef SERDES_L2_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL +#undef SERDES_L2_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT +#undef SERDES_L2_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK +#define SERDES_L2_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL 0x00000001 +#define SERDES_L2_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT 0 +#define SERDES_L2_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK 0x0000000FU + +/* +* CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001 +*/ +#undef SERDES_L3_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL +#undef SERDES_L3_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT +#undef SERDES_L3_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK +#define SERDES_L3_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL 0x00000001 +#define SERDES_L3_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT 0 +#define SERDES_L3_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK 0x0000000FU + +/* +* Delay apb reset by specified amount +*/ #undef SERDES_L0_TM_RST_DLY_APB_RST_DLY_DEFVAL #undef SERDES_L0_TM_RST_DLY_APB_RST_DLY_SHIFT #undef SERDES_L0_TM_RST_DLY_APB_RST_DLY_MASK -#define SERDES_L0_TM_RST_DLY_APB_RST_DLY_DEFVAL 0x00000000 -#define SERDES_L0_TM_RST_DLY_APB_RST_DLY_SHIFT 0 -#define SERDES_L0_TM_RST_DLY_APB_RST_DLY_MASK 0x000000FFU +#define SERDES_L0_TM_RST_DLY_APB_RST_DLY_DEFVAL 0x00000000 +#define SERDES_L0_TM_RST_DLY_APB_RST_DLY_SHIFT 0 +#define SERDES_L0_TM_RST_DLY_APB_RST_DLY_MASK 0x000000FFU -/*Enable Bypass for <7> of TM_ANA_BYPS_15*/ +/* +* Enable Bypass for <7> of TM_ANA_BYPS_15 +*/ #undef SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL #undef SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT #undef SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK -#define SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL 0x00000000 -#define SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT 6 -#define SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK 0x00000040U +#define SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL 0x00000000 +#define SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT 6 +#define SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK 0x00000040U -/*Enable Bypass for <7> of TM_ANA_BYPS_12*/ +/* +* Enable Bypass for <7> of TM_ANA_BYPS_12 +*/ #undef SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL #undef SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT #undef SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK -#define SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL 0x00000000 -#define SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT 6 -#define SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK 0x00000040U +#define SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL 0x00000000 +#define SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT 6 +#define SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK 0x00000040U -/*Delay apb reset by specified amount*/ +/* +* Delay apb reset by specified amount +*/ #undef SERDES_L1_TM_RST_DLY_APB_RST_DLY_DEFVAL #undef SERDES_L1_TM_RST_DLY_APB_RST_DLY_SHIFT #undef SERDES_L1_TM_RST_DLY_APB_RST_DLY_MASK -#define SERDES_L1_TM_RST_DLY_APB_RST_DLY_DEFVAL 0x00000000 -#define SERDES_L1_TM_RST_DLY_APB_RST_DLY_SHIFT 0 -#define SERDES_L1_TM_RST_DLY_APB_RST_DLY_MASK 0x000000FFU +#define SERDES_L1_TM_RST_DLY_APB_RST_DLY_DEFVAL 0x00000000 +#define SERDES_L1_TM_RST_DLY_APB_RST_DLY_SHIFT 0 +#define SERDES_L1_TM_RST_DLY_APB_RST_DLY_MASK 0x000000FFU -/*Enable Bypass for <7> of TM_ANA_BYPS_15*/ +/* +* Enable Bypass for <7> of TM_ANA_BYPS_15 +*/ #undef SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL #undef SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT #undef SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK -#define SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL 0x00000000 -#define SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT 6 -#define SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK 0x00000040U +#define SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL 0x00000000 +#define SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT 6 +#define SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK 0x00000040U -/*Enable Bypass for <7> of TM_ANA_BYPS_12*/ +/* +* Enable Bypass for <7> of TM_ANA_BYPS_12 +*/ #undef SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL #undef SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT #undef SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK -#define SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL 0x00000000 -#define SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT 6 -#define SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK 0x00000040U +#define SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL 0x00000000 +#define SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT 6 +#define SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK 0x00000040U -/*Delay apb reset by specified amount*/ +/* +* Delay apb reset by specified amount +*/ #undef SERDES_L2_TM_RST_DLY_APB_RST_DLY_DEFVAL #undef SERDES_L2_TM_RST_DLY_APB_RST_DLY_SHIFT #undef SERDES_L2_TM_RST_DLY_APB_RST_DLY_MASK -#define SERDES_L2_TM_RST_DLY_APB_RST_DLY_DEFVAL 0x00000000 -#define SERDES_L2_TM_RST_DLY_APB_RST_DLY_SHIFT 0 -#define SERDES_L2_TM_RST_DLY_APB_RST_DLY_MASK 0x000000FFU +#define SERDES_L2_TM_RST_DLY_APB_RST_DLY_DEFVAL 0x00000000 +#define SERDES_L2_TM_RST_DLY_APB_RST_DLY_SHIFT 0 +#define SERDES_L2_TM_RST_DLY_APB_RST_DLY_MASK 0x000000FFU -/*Enable Bypass for <7> of TM_ANA_BYPS_15*/ +/* +* Enable Bypass for <7> of TM_ANA_BYPS_15 +*/ #undef SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL #undef SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT #undef SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK -#define SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL 0x00000000 -#define SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT 6 -#define SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK 0x00000040U +#define SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL 0x00000000 +#define SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT 6 +#define SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK 0x00000040U -/*Enable Bypass for <7> of TM_ANA_BYPS_12*/ +/* +* Enable Bypass for <7> of TM_ANA_BYPS_12 +*/ #undef SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL #undef SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT #undef SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK -#define SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL 0x00000000 -#define SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT 6 -#define SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK 0x00000040U +#define SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL 0x00000000 +#define SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT 6 +#define SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK 0x00000040U -/*Delay apb reset by specified amount*/ +/* +* Delay apb reset by specified amount +*/ #undef SERDES_L3_TM_RST_DLY_APB_RST_DLY_DEFVAL #undef SERDES_L3_TM_RST_DLY_APB_RST_DLY_SHIFT #undef SERDES_L3_TM_RST_DLY_APB_RST_DLY_MASK -#define SERDES_L3_TM_RST_DLY_APB_RST_DLY_DEFVAL 0x00000000 -#define SERDES_L3_TM_RST_DLY_APB_RST_DLY_SHIFT 0 -#define SERDES_L3_TM_RST_DLY_APB_RST_DLY_MASK 0x000000FFU +#define SERDES_L3_TM_RST_DLY_APB_RST_DLY_DEFVAL 0x00000000 +#define SERDES_L3_TM_RST_DLY_APB_RST_DLY_SHIFT 0 +#define SERDES_L3_TM_RST_DLY_APB_RST_DLY_MASK 0x000000FFU -/*Enable Bypass for <7> of TM_ANA_BYPS_15*/ +/* +* Enable Bypass for <7> of TM_ANA_BYPS_15 +*/ #undef SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL #undef SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT #undef SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK -#define SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL 0x00000000 -#define SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT 6 -#define SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK 0x00000040U +#define SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL 0x00000000 +#define SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT 6 +#define SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK 0x00000040U -/*Enable Bypass for <7> of TM_ANA_BYPS_12*/ +/* +* Enable Bypass for <7> of TM_ANA_BYPS_12 +*/ #undef SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL #undef SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT #undef SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK -#define SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL 0x00000000 -#define SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT 6 -#define SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK 0x00000040U +#define SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL 0x00000000 +#define SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT 6 +#define SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK 0x00000040U -/*Controls UPHY Lane 0 protocol configuration. 0 - PowerDown, 1 - PCIe .0, 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII0, 6 - Unuse - , 7 - Unused*/ +/* +* CDR fast phase lock control +*/ +#undef SERDES_L0_TM_MISC3_CDR_EN_FPL_DEFVAL +#undef SERDES_L0_TM_MISC3_CDR_EN_FPL_SHIFT +#undef SERDES_L0_TM_MISC3_CDR_EN_FPL_MASK +#define SERDES_L0_TM_MISC3_CDR_EN_FPL_DEFVAL 0x00000003 +#define SERDES_L0_TM_MISC3_CDR_EN_FPL_SHIFT 1 +#define SERDES_L0_TM_MISC3_CDR_EN_FPL_MASK 0x00000002U + +/* +* CDR fast frequency lock control +*/ +#undef SERDES_L0_TM_MISC3_CDR_EN_FFL_DEFVAL +#undef SERDES_L0_TM_MISC3_CDR_EN_FFL_SHIFT +#undef SERDES_L0_TM_MISC3_CDR_EN_FFL_MASK +#define SERDES_L0_TM_MISC3_CDR_EN_FFL_DEFVAL 0x00000003 +#define SERDES_L0_TM_MISC3_CDR_EN_FFL_SHIFT 0 +#define SERDES_L0_TM_MISC3_CDR_EN_FFL_MASK 0x00000001U + +/* +* CDR fast phase lock control +*/ +#undef SERDES_L1_TM_MISC3_CDR_EN_FPL_DEFVAL +#undef SERDES_L1_TM_MISC3_CDR_EN_FPL_SHIFT +#undef SERDES_L1_TM_MISC3_CDR_EN_FPL_MASK +#define SERDES_L1_TM_MISC3_CDR_EN_FPL_DEFVAL 0x00000003 +#define SERDES_L1_TM_MISC3_CDR_EN_FPL_SHIFT 1 +#define SERDES_L1_TM_MISC3_CDR_EN_FPL_MASK 0x00000002U + +/* +* CDR fast frequency lock control +*/ +#undef SERDES_L1_TM_MISC3_CDR_EN_FFL_DEFVAL +#undef SERDES_L1_TM_MISC3_CDR_EN_FFL_SHIFT +#undef SERDES_L1_TM_MISC3_CDR_EN_FFL_MASK +#define SERDES_L1_TM_MISC3_CDR_EN_FFL_DEFVAL 0x00000003 +#define SERDES_L1_TM_MISC3_CDR_EN_FFL_SHIFT 0 +#define SERDES_L1_TM_MISC3_CDR_EN_FFL_MASK 0x00000001U + +/* +* CDR fast phase lock control +*/ +#undef SERDES_L2_TM_MISC3_CDR_EN_FPL_DEFVAL +#undef SERDES_L2_TM_MISC3_CDR_EN_FPL_SHIFT +#undef SERDES_L2_TM_MISC3_CDR_EN_FPL_MASK +#define SERDES_L2_TM_MISC3_CDR_EN_FPL_DEFVAL 0x00000003 +#define SERDES_L2_TM_MISC3_CDR_EN_FPL_SHIFT 1 +#define SERDES_L2_TM_MISC3_CDR_EN_FPL_MASK 0x00000002U + +/* +* CDR fast frequency lock control +*/ +#undef SERDES_L2_TM_MISC3_CDR_EN_FFL_DEFVAL +#undef SERDES_L2_TM_MISC3_CDR_EN_FFL_SHIFT +#undef SERDES_L2_TM_MISC3_CDR_EN_FFL_MASK +#define SERDES_L2_TM_MISC3_CDR_EN_FFL_DEFVAL 0x00000003 +#define SERDES_L2_TM_MISC3_CDR_EN_FFL_SHIFT 0 +#define SERDES_L2_TM_MISC3_CDR_EN_FFL_MASK 0x00000001U + +/* +* CDR fast phase lock control +*/ +#undef SERDES_L3_TM_MISC3_CDR_EN_FPL_DEFVAL +#undef SERDES_L3_TM_MISC3_CDR_EN_FPL_SHIFT +#undef SERDES_L3_TM_MISC3_CDR_EN_FPL_MASK +#define SERDES_L3_TM_MISC3_CDR_EN_FPL_DEFVAL 0x00000003 +#define SERDES_L3_TM_MISC3_CDR_EN_FPL_SHIFT 1 +#define SERDES_L3_TM_MISC3_CDR_EN_FPL_MASK 0x00000002U + +/* +* CDR fast frequency lock control +*/ +#undef SERDES_L3_TM_MISC3_CDR_EN_FFL_DEFVAL +#undef SERDES_L3_TM_MISC3_CDR_EN_FFL_SHIFT +#undef SERDES_L3_TM_MISC3_CDR_EN_FFL_MASK +#define SERDES_L3_TM_MISC3_CDR_EN_FFL_DEFVAL 0x00000003 +#define SERDES_L3_TM_MISC3_CDR_EN_FFL_SHIFT 0 +#define SERDES_L3_TM_MISC3_CDR_EN_FFL_MASK 0x00000001U + +/* +* Force EQ offset correction algo off if not forced on +*/ +#undef SERDES_L0_TM_EQ11_FORCE_EQ_OFFS_OFF_DEFVAL +#undef SERDES_L0_TM_EQ11_FORCE_EQ_OFFS_OFF_SHIFT +#undef SERDES_L0_TM_EQ11_FORCE_EQ_OFFS_OFF_MASK +#define SERDES_L0_TM_EQ11_FORCE_EQ_OFFS_OFF_DEFVAL 0x00000000 +#define SERDES_L0_TM_EQ11_FORCE_EQ_OFFS_OFF_SHIFT 4 +#define SERDES_L0_TM_EQ11_FORCE_EQ_OFFS_OFF_MASK 0x00000010U + +/* +* Force EQ offset correction algo off if not forced on +*/ +#undef SERDES_L1_TM_EQ11_FORCE_EQ_OFFS_OFF_DEFVAL +#undef SERDES_L1_TM_EQ11_FORCE_EQ_OFFS_OFF_SHIFT +#undef SERDES_L1_TM_EQ11_FORCE_EQ_OFFS_OFF_MASK +#define SERDES_L1_TM_EQ11_FORCE_EQ_OFFS_OFF_DEFVAL 0x00000000 +#define SERDES_L1_TM_EQ11_FORCE_EQ_OFFS_OFF_SHIFT 4 +#define SERDES_L1_TM_EQ11_FORCE_EQ_OFFS_OFF_MASK 0x00000010U + +/* +* Force EQ offset correction algo off if not forced on +*/ +#undef SERDES_L2_TM_EQ11_FORCE_EQ_OFFS_OFF_DEFVAL +#undef SERDES_L2_TM_EQ11_FORCE_EQ_OFFS_OFF_SHIFT +#undef SERDES_L2_TM_EQ11_FORCE_EQ_OFFS_OFF_MASK +#define SERDES_L2_TM_EQ11_FORCE_EQ_OFFS_OFF_DEFVAL 0x00000000 +#define SERDES_L2_TM_EQ11_FORCE_EQ_OFFS_OFF_SHIFT 4 +#define SERDES_L2_TM_EQ11_FORCE_EQ_OFFS_OFF_MASK 0x00000010U + +/* +* Force EQ offset correction algo off if not forced on +*/ +#undef SERDES_L3_TM_EQ11_FORCE_EQ_OFFS_OFF_DEFVAL +#undef SERDES_L3_TM_EQ11_FORCE_EQ_OFFS_OFF_SHIFT +#undef SERDES_L3_TM_EQ11_FORCE_EQ_OFFS_OFF_MASK +#define SERDES_L3_TM_EQ11_FORCE_EQ_OFFS_OFF_DEFVAL 0x00000000 +#define SERDES_L3_TM_EQ11_FORCE_EQ_OFFS_OFF_SHIFT 4 +#define SERDES_L3_TM_EQ11_FORCE_EQ_OFFS_OFF_MASK 0x00000010U + +/* +* For future use +*/ +#undef SIOU_ECO_0_FIELD_DEFVAL +#undef SIOU_ECO_0_FIELD_SHIFT +#undef SIOU_ECO_0_FIELD_MASK +#define SIOU_ECO_0_FIELD_DEFVAL +#define SIOU_ECO_0_FIELD_SHIFT 0 +#define SIOU_ECO_0_FIELD_MASK 0xFFFFFFFFU + +/* +* Controls UPHY Lane 0 protocol configuration. 0 - PowerDown, 1 - PCIe .0, + * 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII0, 6 - Unused, 7 - Unused +*/ #undef SERDES_ICM_CFG0_L0_ICM_CFG_DEFVAL #undef SERDES_ICM_CFG0_L0_ICM_CFG_SHIFT #undef SERDES_ICM_CFG0_L0_ICM_CFG_MASK -#define SERDES_ICM_CFG0_L0_ICM_CFG_DEFVAL 0x00000000 -#define SERDES_ICM_CFG0_L0_ICM_CFG_SHIFT 0 -#define SERDES_ICM_CFG0_L0_ICM_CFG_MASK 0x00000007U +#define SERDES_ICM_CFG0_L0_ICM_CFG_DEFVAL 0x00000000 +#define SERDES_ICM_CFG0_L0_ICM_CFG_SHIFT 0 +#define SERDES_ICM_CFG0_L0_ICM_CFG_MASK 0x00000007U -/*Controls UPHY Lane 1 protocol configuration. 0 - PowerDown, 1 - PCIe.1, 2 - Sata1, 3 - USB0, 4 - DP.0, 5 - SGMII1, 6 - Unused - 7 - Unused*/ +/* +* Controls UPHY Lane 1 protocol configuration. 0 - PowerDown, 1 - PCIe.1, + * 2 - Sata1, 3 - USB0, 4 - DP.0, 5 - SGMII1, 6 - Unused, 7 - Unused +*/ #undef SERDES_ICM_CFG0_L1_ICM_CFG_DEFVAL #undef SERDES_ICM_CFG0_L1_ICM_CFG_SHIFT #undef SERDES_ICM_CFG0_L1_ICM_CFG_MASK -#define SERDES_ICM_CFG0_L1_ICM_CFG_DEFVAL 0x00000000 -#define SERDES_ICM_CFG0_L1_ICM_CFG_SHIFT 4 -#define SERDES_ICM_CFG0_L1_ICM_CFG_MASK 0x00000070U +#define SERDES_ICM_CFG0_L1_ICM_CFG_DEFVAL 0x00000000 +#define SERDES_ICM_CFG0_L1_ICM_CFG_SHIFT 4 +#define SERDES_ICM_CFG0_L1_ICM_CFG_MASK 0x00000070U -/*Controls UPHY Lane 2 protocol configuration. 0 - PowerDown, 1 - PCIe.1, 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII2, 6 - Unused - 7 - Unused*/ +/* +* Controls UPHY Lane 2 protocol configuration. 0 - PowerDown, 1 - PCIe.1, + * 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII2, 6 - Unused, 7 - Unused +*/ #undef SERDES_ICM_CFG1_L2_ICM_CFG_DEFVAL #undef SERDES_ICM_CFG1_L2_ICM_CFG_SHIFT #undef SERDES_ICM_CFG1_L2_ICM_CFG_MASK -#define SERDES_ICM_CFG1_L2_ICM_CFG_DEFVAL 0x00000000 -#define SERDES_ICM_CFG1_L2_ICM_CFG_SHIFT 0 -#define SERDES_ICM_CFG1_L2_ICM_CFG_MASK 0x00000007U +#define SERDES_ICM_CFG1_L2_ICM_CFG_DEFVAL 0x00000000 +#define SERDES_ICM_CFG1_L2_ICM_CFG_SHIFT 0 +#define SERDES_ICM_CFG1_L2_ICM_CFG_MASK 0x00000007U -/*Controls UPHY Lane 3 protocol configuration. 0 - PowerDown, 1 - PCIe.3, 2 - Sata1, 3 - USB1, 4 - DP.0, 5 - SGMII3, 6 - Unused - 7 - Unused*/ +/* +* Controls UPHY Lane 3 protocol configuration. 0 - PowerDown, 1 - PCIe.3, + * 2 - Sata1, 3 - USB1, 4 - DP.0, 5 - SGMII3, 6 - Unused, 7 - Unused +*/ #undef SERDES_ICM_CFG1_L3_ICM_CFG_DEFVAL #undef SERDES_ICM_CFG1_L3_ICM_CFG_SHIFT #undef SERDES_ICM_CFG1_L3_ICM_CFG_MASK -#define SERDES_ICM_CFG1_L3_ICM_CFG_DEFVAL 0x00000000 -#define SERDES_ICM_CFG1_L3_ICM_CFG_SHIFT 4 -#define SERDES_ICM_CFG1_L3_ICM_CFG_MASK 0x00000070U +#define SERDES_ICM_CFG1_L3_ICM_CFG_DEFVAL 0x00000000 +#define SERDES_ICM_CFG1_L3_ICM_CFG_SHIFT 4 +#define SERDES_ICM_CFG1_L3_ICM_CFG_MASK 0x00000070U -/*Enable/disable DP post2 path*/ +/* +* Enable/disable DP post2 path +*/ #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_DEFVAL #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_SHIFT #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_MASK -#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_DEFVAL 0x00000000 -#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_SHIFT 5 -#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_MASK 0x00000020U +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_DEFVAL 0x00000000 +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_SHIFT 5 +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_MASK 0x00000020U -/*Override enable/disable of DP post2 path*/ +/* +* Override enable/disable of DP post2 path +*/ #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_DEFVAL #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_SHIFT #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_MASK -#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_DEFVAL 0x00000000 -#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_SHIFT 4 -#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_MASK 0x00000010U +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_DEFVAL 0x00000000 +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_SHIFT 4 +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_MASK 0x00000010U -/*Override enable/disable of DP post1 path*/ +/* +* Override enable/disable of DP post1 path +*/ #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_DEFVAL #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_SHIFT #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_MASK -#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_DEFVAL 0x00000000 -#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_SHIFT 2 -#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_MASK 0x00000004U +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_DEFVAL 0x00000000 +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_SHIFT 2 +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_MASK 0x00000004U -/*Enable/disable DP main path*/ +/* +* Enable/disable DP main path +*/ #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_DEFVAL #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_SHIFT #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_MASK -#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_DEFVAL 0x00000000 -#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_SHIFT 1 -#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_MASK 0x00000002U +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_DEFVAL 0x00000000 +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_SHIFT 1 +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_MASK 0x00000002U -/*Override enable/disable of DP main path*/ +/* +* Override enable/disable of DP main path +*/ #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_DEFVAL #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_SHIFT #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_MASK -#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_DEFVAL 0x00000000 -#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_SHIFT 0 -#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_MASK 0x00000001U +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_DEFVAL 0x00000000 +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_SHIFT 0 +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_MASK 0x00000001U -/*Test register force for enabling/disablign TX deemphasis bits <17:0>*/ +/* +* Test register force for enabling/disablign TX deemphasis bits <17:0> +*/ #undef SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_DEFVAL #undef SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT #undef SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK -#define SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_DEFVAL 0x00000000 -#define SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT 0 -#define SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK 0x00000001U +#define SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_DEFVAL 0x00000000 +#define SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT 0 +#define SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK 0x00000001U -/*Test register force for enabling/disablign TX deemphasis bits <17:0>*/ +/* +* Test register force for enabling/disablign TX deemphasis bits <17:0> +*/ #undef SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_DEFVAL #undef SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT #undef SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK -#define SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_DEFVAL 0x00000000 -#define SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT 0 -#define SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK 0x00000001U +#define SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_DEFVAL 0x00000000 +#define SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT 0 +#define SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK 0x00000001U -/*FPHL FSM accumulate cycles*/ +/* +* FPHL FSM accumulate cycles +*/ #undef SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_DEFVAL #undef SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_SHIFT #undef SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_MASK -#define SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_DEFVAL 0x00000000 -#define SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_SHIFT 5 -#define SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_MASK 0x000000E0U +#define SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_DEFVAL 0x00000000 +#define SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_SHIFT 5 +#define SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_MASK 0x000000E0U -/*FFL Phase0 int gain aka 2ol SD update rate*/ +/* +* FFL Phase0 int gain aka 2ol SD update rate +*/ #undef SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_DEFVAL #undef SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_SHIFT #undef SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_MASK -#define SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_DEFVAL 0x00000000 -#define SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_SHIFT 0 -#define SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_MASK 0x0000001FU +#define SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_DEFVAL 0x00000000 +#define SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_SHIFT 0 +#define SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_MASK 0x0000001FU -/*FFL Phase0 prop gain aka 1ol SD update rate*/ +/* +* FFL Phase0 prop gain aka 1ol SD update rate +*/ #undef SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_DEFVAL #undef SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_SHIFT #undef SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_MASK -#define SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_DEFVAL 0x00000000 -#define SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_SHIFT 0 -#define SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_MASK 0x0000001FU +#define SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_DEFVAL 0x00000000 +#define SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_SHIFT 0 +#define SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_MASK 0x0000001FU -/*EQ stg 2 controls BYPASSED*/ +/* +* EQ stg 2 controls BYPASSED +*/ #undef SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_DEFVAL #undef SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_SHIFT #undef SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_MASK -#define SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_DEFVAL 0x00000000 -#define SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_SHIFT 5 -#define SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_MASK 0x00000020U +#define SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_DEFVAL 0x00000000 +#define SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_SHIFT 5 +#define SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_MASK 0x00000020U -/*EQ STG2 RL PROG*/ +/* +* EQ STG2 RL PROG +*/ #undef SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_DEFVAL #undef SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_SHIFT #undef SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_MASK -#define SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_DEFVAL 0x00000000 -#define SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_SHIFT 0 -#define SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_MASK 0x00000003U +#define SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_DEFVAL 0x00000000 +#define SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_SHIFT 0 +#define SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_MASK 0x00000003U -/*EQ stg 2 preamp mode val*/ +/* +* EQ stg 2 preamp mode val +*/ #undef SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_DEFVAL #undef SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_SHIFT #undef SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_MASK -#define SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_DEFVAL 0x00000000 -#define SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_SHIFT 2 -#define SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_MASK 0x00000004U +#define SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_DEFVAL 0x00000000 +#define SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_SHIFT 2 +#define SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_MASK 0x00000004U -/*Margining factor value*/ +/* +* Margining factor value +*/ #undef SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_DEFVAL #undef SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_SHIFT #undef SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_MASK -#define SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_DEFVAL 0x00000000 -#define SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_SHIFT 0 -#define SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_MASK 0x0000001FU +#define SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_DEFVAL 0x00000000 +#define SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_SHIFT 0 +#define SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_MASK 0x0000001FU -/*pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-emphasis, Others: reserved*/ +/* +* pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-em + * phasis, Others: reserved +*/ #undef SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_DEFVAL #undef SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT #undef SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK -#define SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_DEFVAL 0x00000002 -#define SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT 0 -#define SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK 0x000000FFU +#define SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_DEFVAL 0x00000002 +#define SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT 0 +#define SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK 0x000000FFU -/*pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-emphasis, Others: reserved*/ +/* +* pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-em + * phasis, Others: reserved +*/ #undef SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_DEFVAL #undef SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT #undef SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK -#define SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_DEFVAL 0x00000002 -#define SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT 0 -#define SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK 0x000000FFU +#define SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_DEFVAL 0x00000002 +#define SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT 0 +#define SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK 0x000000FFU #undef CRL_APB_RST_LPD_TOP_OFFSET #define CRL_APB_RST_LPD_TOP_OFFSET 0XFF5E023C -#undef USB3_0_FPD_POWER_PRSNT_OFFSET -#define USB3_0_FPD_POWER_PRSNT_OFFSET 0XFF9D0080 -#undef USB3_0_FPD_PIPE_CLK_OFFSET -#define USB3_0_FPD_PIPE_CLK_OFFSET 0XFF9D007C #undef CRL_APB_RST_LPD_TOP_OFFSET #define CRL_APB_RST_LPD_TOP_OFFSET 0XFF5E023C #undef CRL_APB_RST_LPD_IOU0_OFFSET @@ -26548,6 +34559,10 @@ #define USB3_0_XHCI_GUSB2PHYCFG_OFFSET 0XFE20C200 #undef USB3_0_XHCI_GFLADJ_OFFSET #define USB3_0_XHCI_GFLADJ_OFFSET 0XFE20C630 +#undef USB3_0_XHCI_GUCTL1_OFFSET +#define USB3_0_XHCI_GUCTL1_OFFSET 0XFE20C11C +#undef USB3_0_XHCI_GUCTL_OFFSET +#define USB3_0_XHCI_GUCTL_OFFSET 0XFE20C12C #undef PCIE_ATTRIB_ATTR_25_OFFSET #define PCIE_ATTRIB_ATTR_25_OFFSET 0XFD480064 #undef PCIE_ATTRIB_ATTR_7_OFFSET @@ -26638,6 +34653,8 @@ #define PCIE_ATTRIB_ATTR_35_OFFSET 0XFD48008C #undef CRF_APB_RST_FPD_TOP_OFFSET #define CRF_APB_RST_FPD_TOP_OFFSET 0XFD1A0100 +#undef GPIO_MASK_DATA_1_LSW_OFFSET +#define GPIO_MASK_DATA_1_LSW_OFFSET 0XFF0A0008 #undef SATA_AHCI_VENDOR_PP2C_OFFSET #define SATA_AHCI_VENDOR_PP2C_OFFSET 0XFD0C00AC #undef SATA_AHCI_VENDOR_PP3C_OFFSET @@ -26647,1015 +34664,1462 @@ #undef SATA_AHCI_VENDOR_PP5C_OFFSET #define SATA_AHCI_VENDOR_PP5C_OFFSET 0XFD0C00B8 -/*USB 0 reset for control registers*/ +/* +* USB 0 reset for control registers +*/ #undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL #undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT #undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK -#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL 0x00188FDF -#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT 10 -#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK 0x00000400U +#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT 10 +#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK 0x00000400U -/*This bit is used to choose between PIPE power present and 1'b1*/ -#undef USB3_0_FPD_POWER_PRSNT_OPTION_DEFVAL -#undef USB3_0_FPD_POWER_PRSNT_OPTION_SHIFT -#undef USB3_0_FPD_POWER_PRSNT_OPTION_MASK -#define USB3_0_FPD_POWER_PRSNT_OPTION_DEFVAL -#define USB3_0_FPD_POWER_PRSNT_OPTION_SHIFT 0 -#define USB3_0_FPD_POWER_PRSNT_OPTION_MASK 0x00000001U - -/*This bit is used to choose between PIPE clock coming from SerDes and the suspend clk*/ -#undef USB3_0_FPD_PIPE_CLK_OPTION_DEFVAL -#undef USB3_0_FPD_PIPE_CLK_OPTION_SHIFT -#undef USB3_0_FPD_PIPE_CLK_OPTION_MASK -#define USB3_0_FPD_PIPE_CLK_OPTION_DEFVAL -#define USB3_0_FPD_PIPE_CLK_OPTION_SHIFT 0 -#define USB3_0_FPD_PIPE_CLK_OPTION_MASK 0x00000001U - -/*USB 0 sleep circuit reset*/ +/* +* USB 0 sleep circuit reset +*/ #undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL #undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT #undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK -#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL 0x00188FDF -#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT 8 -#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK 0x00000100U +#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT 8 +#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK 0x00000100U -/*USB 0 reset*/ +/* +* USB 0 reset +*/ #undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL #undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT #undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK -#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL 0x00188FDF -#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT 6 -#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK 0x00000040U +#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT 6 +#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK 0x00000040U -/*GEM 3 reset*/ +/* +* GEM 3 reset +*/ #undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL #undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT #undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK -#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL 0x0000000F -#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT 3 -#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK 0x00000008U +#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL 0x0000000F +#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT 3 +#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK 0x00000008U -/*Sata PM clock control select*/ +/* +* Sata PM clock control select +*/ #undef SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_DEFVAL #undef SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_SHIFT #undef SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_MASK -#define SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_DEFVAL -#define SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_SHIFT 0 -#define SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_MASK 0x00000003U +#define SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_DEFVAL +#define SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_SHIFT 0 +#define SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_MASK 0x00000003U -/*Sata block level reset*/ +/* +* Sata block level reset +*/ #undef CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL #undef CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT #undef CRF_APB_RST_FPD_TOP_SATA_RESET_MASK -#define CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL 0x000F9FFE -#define CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT 1 -#define CRF_APB_RST_FPD_TOP_SATA_RESET_MASK 0x00000002U +#define CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT 1 +#define CRF_APB_RST_FPD_TOP_SATA_RESET_MASK 0x00000002U -/*PCIE config reset*/ +/* +* PCIE config reset +*/ #undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL #undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT #undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK -#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL 0x000F9FFE -#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT 19 -#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK 0x00080000U +#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT 19 +#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK 0x00080000U -/*PCIE bridge block level reset (AXI interface)*/ +/* +* PCIE bridge block level reset (AXI interface) +*/ #undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL #undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT #undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK -#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL 0x000F9FFE -#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT 18 -#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK 0x00040000U +#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT 18 +#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK 0x00040000U -/*Display Port block level reset (includes DPDMA)*/ +/* +* Display Port block level reset (includes DPDMA) +*/ #undef CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL #undef CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT #undef CRF_APB_RST_FPD_TOP_DP_RESET_MASK -#define CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL 0x000F9FFE -#define CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT 16 -#define CRF_APB_RST_FPD_TOP_DP_RESET_MASK 0x00010000U +#define CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT 16 +#define CRF_APB_RST_FPD_TOP_DP_RESET_MASK 0x00010000U -/*Set to '1' to hold the GT in reset. Clear to release.*/ +/* +* Set to '1' to hold the GT in reset. Clear to release. +*/ #undef DP_DP_PHY_RESET_GT_RESET_DEFVAL #undef DP_DP_PHY_RESET_GT_RESET_SHIFT #undef DP_DP_PHY_RESET_GT_RESET_MASK -#define DP_DP_PHY_RESET_GT_RESET_DEFVAL 0x00010003 -#define DP_DP_PHY_RESET_GT_RESET_SHIFT 1 -#define DP_DP_PHY_RESET_GT_RESET_MASK 0x00000002U +#define DP_DP_PHY_RESET_GT_RESET_DEFVAL 0x00010003 +#define DP_DP_PHY_RESET_GT_RESET_SHIFT 1 +#define DP_DP_PHY_RESET_GT_RESET_MASK 0x00000002U -/*Two bits per lane. When set to 11, moves the GT to power down mode. When set to 00, GT will be in active state. bits [1:0] - - ane0 Bits [3:2] - lane 1*/ +/* +* Two bits per lane. When set to 11, moves the GT to power down mode. When + * set to 00, GT will be in active state. bits [1:0] - lane0 Bits [3:2] - + * lane 1 +*/ #undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_DEFVAL #undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT #undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK -#define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_DEFVAL 0x00000000 -#define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT 0 -#define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK 0x0000000FU +#define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_DEFVAL 0x00000000 +#define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT 0 +#define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK 0x0000000FU -/*USB 2.0 Turnaround Time (USBTrdTim) Sets the turnaround time in PHY clocks. Specifies the response time for a MAC request to - he Packet FIFO Controller (PFC) to fetch data from the DFIFO (SPRAM). The following are the required values for the minimum S - C bus frequency of 60 MHz. USB turnaround time is a critical certification criteria when using long cables and five hub level - . The required values for this field: - 4'h5: When the MAC interface is 16-bit UTMI+. - 4'h9: When the MAC interface is 8-bit - UTMI+/ULPI. If SoC bus clock is less than 60 MHz, and USB turnaround time is not critical, this field can be set to a larger - alue. Note: This field is valid only in device mode.*/ +/* +* USB 2.0 Turnaround Time (USBTrdTim) Sets the turnaround time in PHY cloc + * ks. Specifies the response time for a MAC request to the Packet FIFO Con + * troller (PFC) to fetch data from the DFIFO (SPRAM). The following are th + * e required values for the minimum SoC bus frequency of 60 MHz. USB turna + * round time is a critical certification criteria when using long cables a + * nd five hub levels. The required values for this field: - 4'h5: When the + * MAC interface is 16-bit UTMI+. - 4'h9: When the MAC interface is 8-bit + * UTMI+/ULPI. If SoC bus clock is less than 60 MHz, and USB turnaround tim + * e is not critical, this field can be set to a larger value. Note: This f + * ield is valid only in device mode. +*/ #undef USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_DEFVAL #undef USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_SHIFT #undef USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_MASK -#define USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_DEFVAL 0x00000000 -#define USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_SHIFT 10 -#define USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_MASK 0x00003C00U +#define USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_DEFVAL 0x00000000 +#define USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_SHIFT 10 +#define USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_MASK 0x00003C00U -/*Transceiver Delay: Enables a delay between the assertion of the UTMI/ULPI Transceiver Select signal (for HS) and the assertio - of the TxValid signal during a HS Chirp. When this bit is set to 1, a delay (of approximately 2.5 us) is introduced from the - time when the Transceiver Select is set to 2'b00 (HS) to the time the TxValid is driven to 0 for sending the chirp-K. This de - ay is required for some UTMI/ULPI PHYs. Note: - If you enable the hibernation feature when the device core comes out of power - off, you must re-initialize this bit with the appropriate value because the core does not save and restore this bit value dur - ng hibernation. - This bit is valid only in device mode.*/ +/* +* Transceiver Delay: Enables a delay between the assertion of the UTMI/ULP + * I Transceiver Select signal (for HS) and the assertion of the TxValid si + * gnal during a HS Chirp. When this bit is set to 1, a delay (of approxima + * tely 2.5 us) is introduced from the time when the Transceiver Select is + * set to 2'b00 (HS) to the time the TxValid is driven to 0 for sending the + * chirp-K. This delay is required for some UTMI/ULPI PHYs. Note: - If you + * enable the hibernation feature when the device core comes out of power- + * off, you must re-initialize this bit with the appropriate value because + * the core does not save and restore this bit value during hibernation. - + * This bit is valid only in device mode. +*/ #undef USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_DEFVAL #undef USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_SHIFT #undef USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_MASK -#define USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_DEFVAL 0x00000000 -#define USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_SHIFT 9 -#define USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_MASK 0x00000200U +#define USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_DEFVAL 0x00000000 +#define USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_SHIFT 9 +#define USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_MASK 0x00000200U -/*Enable utmi_sleep_n and utmi_l1_suspend_n (EnblSlpM) The application uses this bit to control utmi_sleep_n and utmi_l1_suspen - _n assertion to the PHY in the L1 state. - 1'b0: utmi_sleep_n and utmi_l1_suspend_n assertion from the core is not transferre - to the external PHY. - 1'b1: utmi_sleep_n and utmi_l1_suspend_n assertion from the core is transferred to the external PHY. - ote: This bit must be set high for Port0 if PHY is used. Note: In Device mode - Before issuing any device endpoint command wh - n operating in 2.0 speeds, disable this bit and enable it after the command completes. Without disabling this bit, if a comma - d is issued when the device is in L1 state and if mac2_clk (utmi_clk/ulpi_clk) is gated off, the command will not get complet - d.*/ +/* +* Enable utmi_sleep_n and utmi_l1_suspend_n (EnblSlpM) The application use + * s this bit to control utmi_sleep_n and utmi_l1_suspend_n assertion to th + * e PHY in the L1 state. - 1'b0: utmi_sleep_n and utmi_l1_suspend_n assert + * ion from the core is not transferred to the external PHY. - 1'b1: utmi_s + * leep_n and utmi_l1_suspend_n assertion from the core is transferred to t + * he external PHY. Note: This bit must be set high for Port0 if PHY is use + * d. Note: In Device mode - Before issuing any device endpoint command whe + * n operating in 2.0 speeds, disable this bit and enable it after the comm + * and completes. Without disabling this bit, if a command is issued when t + * he device is in L1 state and if mac2_clk (utmi_clk/ulpi_clk) is gated of + * f, the command will not get completed. +*/ #undef USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_DEFVAL #undef USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_SHIFT #undef USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_MASK -#define USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_DEFVAL 0x00000000 -#define USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_SHIFT 8 -#define USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_MASK 0x00000100U +#define USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_DEFVAL 0x00000000 +#define USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_SHIFT 8 +#define USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_MASK 0x00000100U -/*USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial Transceiver Select The application uses this bit to select a high-speed P - Y or a full-speed transceiver. - 1'b0: USB 2.0 high-speed UTMI+ or ULPI PHY. This bit is always 0, with Write Only access. - - 'b1: USB 1.1 full-speed serial transceiver. This bit is always 1, with Write Only access. If both interface types are selecte - in coreConsultant (that is, parameters' values are not zero), the application uses this bit to select the active interface i - active, with Read-Write bit access. Note: USB 1.1 full-serial transceiver is not supported. This bit always reads as 1'b0.*/ +/* +* USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial Transceiver Select T + * he application uses this bit to select a high-speed PHY or a full-speed + * transceiver. - 1'b0: USB 2.0 high-speed UTMI+ or ULPI PHY. This bit is a + * lways 0, with Write Only access. - 1'b1: USB 1.1 full-speed serial trans + * ceiver. This bit is always 1, with Write Only access. If both interface + * types are selected in coreConsultant (that is, parameters' values are no + * t zero), the application uses this bit to select the active interface is + * active, with Read-Write bit access. Note: USB 1.1 full-serial transceiv + * er is not supported. This bit always reads as 1'b0. +*/ #undef USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_DEFVAL #undef USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_SHIFT #undef USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_MASK -#define USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_DEFVAL 0x00000000 -#define USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_SHIFT 7 -#define USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_MASK 0x00000080U +#define USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_DEFVAL 0x00000000 +#define USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_SHIFT 7 +#define USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_MASK 0x00000080U -/*Full-Speed Serial Interface Select (FSIntf) The application uses this bit to select a unidirectional or bidirectional USB 1.1 - full-speed serial transceiver interface. - 1'b0: 6-pin unidirectional full-speed serial interface. This bit is set to 0 with - ead Only access. - 1'b1: 3-pin bidirectional full-speed serial interface. This bit is set to 0 with Read Only access. Note: U - B 1.1 full-speed serial interface is not supported. This bit always reads as 1'b0.*/ +/* +* Suspend USB2.0 HS/FS/LS PHY (SusPHY) When set, USB2.0 PHY enters Suspend + * mode if Suspend conditions are valid. For DRD/OTG configurations, it is + * recommended that this bit is set to 0 during coreConsultant configurati + * on. If it is set to 1, then the application must clear this bit after po + * wer-on reset. Application needs to set it to 1 after the core initializa + * tion completes. For all other configurations, this bit can be set to 1 d + * uring core configuration. Note: - In host mode, on reset, this bit is se + * t to 1. Software can override this bit after reset. - In device mode, be + * fore issuing any device endpoint command when operating in 2.0 speeds, d + * isable this bit and enable it after the command completes. If you issue + * a command without disabling this bit when the device is in L2 state and + * if mac2_clk (utmi_clk/ulpi_clk) is gated off, the command will not get c + * ompleted. +*/ +#undef USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_DEFVAL +#undef USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_SHIFT +#undef USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_MASK +#define USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_DEFVAL 0x00000000 +#define USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_SHIFT 6 +#define USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_MASK 0x00000040U + +/* +* Full-Speed Serial Interface Select (FSIntf) The application uses this bi + * t to select a unidirectional or bidirectional USB 1.1 full-speed serial + * transceiver interface. - 1'b0: 6-pin unidirectional full-speed serial in + * terface. This bit is set to 0 with Read Only access. - 1'b1: 3-pin bidir + * ectional full-speed serial interface. This bit is set to 0 with Read Onl + * y access. Note: USB 1.1 full-speed serial interface is not supported. Th + * is bit always reads as 1'b0. +*/ #undef USB3_0_XHCI_GUSB2PHYCFG_FSINTF_DEFVAL #undef USB3_0_XHCI_GUSB2PHYCFG_FSINTF_SHIFT #undef USB3_0_XHCI_GUSB2PHYCFG_FSINTF_MASK -#define USB3_0_XHCI_GUSB2PHYCFG_FSINTF_DEFVAL 0x00000000 -#define USB3_0_XHCI_GUSB2PHYCFG_FSINTF_SHIFT 5 -#define USB3_0_XHCI_GUSB2PHYCFG_FSINTF_MASK 0x00000020U +#define USB3_0_XHCI_GUSB2PHYCFG_FSINTF_DEFVAL 0x00000000 +#define USB3_0_XHCI_GUSB2PHYCFG_FSINTF_SHIFT 5 +#define USB3_0_XHCI_GUSB2PHYCFG_FSINTF_MASK 0x00000020U -/*ULPI or UTMI+ Select (ULPI_UTMI_Sel) The application uses this bit to select a UTMI+ or ULPI Interface. - 1'b0: UTMI+ Interfa - e - 1'b1: ULPI Interface This bit is writable only if UTMI+ and ULPI is specified for High-Speed PHY Interface(s) in coreCons - ltant configuration (DWC_USB3_HSPHY_INTERFACE = 3). Otherwise, this bit is read-only and the value depends on the interface s - lected through DWC_USB3_HSPHY_INTERFACE.*/ +/* +* ULPI or UTMI+ Select (ULPI_UTMI_Sel) The application uses this bit to se + * lect a UTMI+ or ULPI Interface. - 1'b0: UTMI+ Interface - 1'b1: ULPI Int + * erface This bit is writable only if UTMI+ and ULPI is specified for High + * -Speed PHY Interface(s) in coreConsultant configuration (DWC_USB3_HSPHY_ + * INTERFACE = 3). Otherwise, this bit is read-only and the value depends o + * n the interface selected through DWC_USB3_HSPHY_INTERFACE. +*/ #undef USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_DEFVAL #undef USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_SHIFT #undef USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_MASK -#define USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_DEFVAL 0x00000000 -#define USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_SHIFT 4 -#define USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_MASK 0x00000010U +#define USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_DEFVAL 0x00000000 +#define USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_SHIFT 4 +#define USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_MASK 0x00000010U -/*PHY Interface (PHYIf) If UTMI+ is selected, the application uses this bit to configure the core to support a UTMI+ PHY with a - 8- or 16-bit interface. - 1'b0: 8 bits - 1'b1: 16 bits ULPI Mode: 1'b0 Note: - All the enabled 2.0 ports must have the same - lock frequency as Port0 clock frequency (utmi_clk[0]). - The UTMI 8-bit and 16-bit modes cannot be used together for differen - ports at the same time (that is, all the ports must be in 8-bit mode, or all of them must be in 16-bit mode, at a time). - I - any of the USB 2.0 ports is selected as ULPI port for operation, then all the USB 2.0 ports must be operating at 60 MHz.*/ +/* +* PHY Interface (PHYIf) If UTMI+ is selected, the application uses this bi + * t to configure the core to support a UTMI+ PHY with an 8- or 16-bit inte + * rface. - 1'b0: 8 bits - 1'b1: 16 bits ULPI Mode: 1'b0 Note: - All the en + * abled 2.0 ports must have the same clock frequency as Port0 clock freque + * ncy (utmi_clk[0]). - The UTMI 8-bit and 16-bit modes cannot be used toge + * ther for different ports at the same time (that is, all the ports must b + * e in 8-bit mode, or all of them must be in 16-bit mode, at a time). - If + * any of the USB 2.0 ports is selected as ULPI port for operation, then a + * ll the USB 2.0 ports must be operating at 60 MHz. +*/ #undef USB3_0_XHCI_GUSB2PHYCFG_PHYIF_DEFVAL #undef USB3_0_XHCI_GUSB2PHYCFG_PHYIF_SHIFT #undef USB3_0_XHCI_GUSB2PHYCFG_PHYIF_MASK -#define USB3_0_XHCI_GUSB2PHYCFG_PHYIF_DEFVAL 0x00000000 -#define USB3_0_XHCI_GUSB2PHYCFG_PHYIF_SHIFT 3 -#define USB3_0_XHCI_GUSB2PHYCFG_PHYIF_MASK 0x00000008U +#define USB3_0_XHCI_GUSB2PHYCFG_PHYIF_DEFVAL 0x00000000 +#define USB3_0_XHCI_GUSB2PHYCFG_PHYIF_SHIFT 3 +#define USB3_0_XHCI_GUSB2PHYCFG_PHYIF_MASK 0x00000008U -/*HS/FS Timeout Calibration (TOutCal) The number of PHY clocks, as indicated by the application in this field, is multiplied by - a bit-time factor; this factor is added to the high-speed/full-speed interpacket timeout duration in the core to account for - dditional delays introduced by the PHY. This may be required, since the delay introduced by the PHY in generating the linesta - e condition may vary among PHYs. The USB standard timeout value for high-speed operation is 736 to 816 (inclusive) bit times. - The USB standard timeout value for full-speed operation is 16 to 18 (inclusive) bit times. The application must program this - ield based on the speed of connection. The number of bit times added per PHY clock are: High-speed operation: - One 30-MHz PH - clock = 16 bit times - One 60-MHz PHY clock = 8 bit times Full-speed operation: - One 30-MHz PHY clock = 0.4 bit times - One - 60-MHz PHY clock = 0.2 bit times - One 48-MHz PHY clock = 0.25 bit times*/ +/* +* HS/FS Timeout Calibration (TOutCal) The number of PHY clocks, as indicat + * ed by the application in this field, is multiplied by a bit-time factor; + * this factor is added to the high-speed/full-speed interpacket timeout d + * uration in the core to account for additional delays introduced by the P + * HY. This may be required, since the delay introduced by the PHY in gener + * ating the linestate condition may vary among PHYs. The USB standard time + * out value for high-speed operation is 736 to 816 (inclusive) bit times. + * The USB standard timeout value for full-speed operation is 16 to 18 (inc + * lusive) bit times. The application must program this field based on the + * speed of connection. The number of bit times added per PHY clock are: Hi + * gh-speed operation: - One 30-MHz PHY clock = 16 bit times - One 60-MHz P + * HY clock = 8 bit times Full-speed operation: - One 30-MHz PHY clock = 0. + * 4 bit times - One 60-MHz PHY clock = 0.2 bit times - One 48-MHz PHY cloc + * k = 0.25 bit times +*/ #undef USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_DEFVAL #undef USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_SHIFT #undef USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_MASK -#define USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_DEFVAL 0x00000000 -#define USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_SHIFT 0 -#define USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_MASK 0x00000007U +#define USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_DEFVAL 0x00000000 +#define USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_SHIFT 0 +#define USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_MASK 0x00000007U -/*This field indicates the frame length adjustment to be applied when SOF/ITP counter is running on the ref_clk. This register - alue is used to adjust the ITP interval when GCTL[SOFITPSYNC] is set to '1'; SOF and ITP interval when GLADJ.GFLADJ_REFCLK_LP - _SEL is set to '1'. This field must be programmed to a non-zero value only if GFLADJ_REFCLK_LPM_SEL is set to '1' or GCTL.SOF - TPSYNC is set to '1'. The value is derived as follows: FLADJ_REF_CLK_FLADJ=((125000/ref_clk_period_integer)-(125000/ref_clk_p - riod)) * ref_clk_period where - the ref_clk_period_integer is the integer value of the ref_clk period got by truncating the d - cimal (fractional) value that is programmed in the GUCTL.REF_CLK_PERIOD field. - the ref_clk_period is the ref_clk period inc - uding the fractional value. Examples: If the ref_clk is 24 MHz then - GUCTL.REF_CLK_PERIOD = 41 - GFLADJ.GLADJ_REFCLK_FLADJ = - ((125000/41)-(125000/41.6666))*41.6666 = 2032 (ignoring the fractional value) If the ref_clk is 48 MHz then - GUCTL.REF_CLK_P - RIOD = 20 - GFLADJ.GLADJ_REFCLK_FLADJ = ((125000/20)-(125000/20.8333))*20.8333 = 5208 (ignoring the fractional value)*/ +/* +* ULPI External VBUS Drive (ULPIExtVbusDrv) Selects supply source to drive + * 5V on VBUS, in the ULPI PHY. - 1'b0: PHY drives VBUS with internal char + * ge pump (default). - 1'b1: PHY drives VBUS with an external supply. (Onl + * y when RTL parameter DWC_USB3_HSPHY_INTERFACE = 2 or 3) +*/ +#undef USB3_0_XHCI_GUSB2PHYCFG_ULPIEXTVBUSDRV_DEFVAL +#undef USB3_0_XHCI_GUSB2PHYCFG_ULPIEXTVBUSDRV_SHIFT +#undef USB3_0_XHCI_GUSB2PHYCFG_ULPIEXTVBUSDRV_MASK +#define USB3_0_XHCI_GUSB2PHYCFG_ULPIEXTVBUSDRV_DEFVAL 0x00000000 +#define USB3_0_XHCI_GUSB2PHYCFG_ULPIEXTVBUSDRV_SHIFT 17 +#define USB3_0_XHCI_GUSB2PHYCFG_ULPIEXTVBUSDRV_MASK 0x00020000U + +/* +* This field indicates the frame length adjustment to be applied when SOF/ + * ITP counter is running on the ref_clk. This register value is used to ad + * just the ITP interval when GCTL[SOFITPSYNC] is set to '1'; SOF and ITP i + * nterval when GLADJ.GFLADJ_REFCLK_LPM_SEL is set to '1'. This field must + * be programmed to a non-zero value only if GFLADJ_REFCLK_LPM_SEL is set t + * o '1' or GCTL.SOFITPSYNC is set to '1'. The value is derived as follows: + * FLADJ_REF_CLK_FLADJ=((125000/ref_clk_period_integer)-(125000/ref_clk_pe + * riod)) * ref_clk_period where - the ref_clk_period_integer is the intege + * r value of the ref_clk period got by truncating the decimal (fractional) + * value that is programmed in the GUCTL.REF_CLK_PERIOD field. - the ref_c + * lk_period is the ref_clk period including the fractional value. Examples + * : If the ref_clk is 24 MHz then - GUCTL.REF_CLK_PERIOD = 41 - GFLADJ.GLA + * DJ_REFCLK_FLADJ = ((125000/41)-(125000/41.6666))*41.6666 = 2032 (ignorin + * g the fractional value) If the ref_clk is 48 MHz then - GUCTL.REF_CLK_PE + * RIOD = 20 - GFLADJ.GLADJ_REFCLK_FLADJ = ((125000/20)-(125000/20.8333))*2 + * 0.8333 = 5208 (ignoring the fractional value) +*/ #undef USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_DEFVAL #undef USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_SHIFT #undef USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_MASK -#define USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_DEFVAL 0x00000000 -#define USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_SHIFT 8 -#define USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_MASK 0x003FFF00U +#define USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_DEFVAL 0x00000000 +#define USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_SHIFT 8 +#define USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_MASK 0x003FFF00U -/*If TRUE Completion Timeout Disable is supported. This is required to be TRUE for Endpoint and either setting allowed for Root - ports. Drives Device Capability 2 [4]; EP=0x0001; RP=0x0001*/ +/* +* When this bit is set to '0', termsel, xcvrsel will become 0 during end o + * f resume while the opmode will become 0 once controller completes end of + * resume and enters U0 state (2 separate commandswill be issued). When th + * is bit is set to '1', all the termsel, xcvrsel, opmode becomes 0 during + * end of resume itself (only 1 command will be issued) +*/ +#undef USB3_0_XHCI_GUCTL1_RESUME_TERMSEL_XCVRSEL_UNIFY_DEFVAL +#undef USB3_0_XHCI_GUCTL1_RESUME_TERMSEL_XCVRSEL_UNIFY_SHIFT +#undef USB3_0_XHCI_GUCTL1_RESUME_TERMSEL_XCVRSEL_UNIFY_MASK +#define USB3_0_XHCI_GUCTL1_RESUME_TERMSEL_XCVRSEL_UNIFY_DEFVAL 0x00000000 +#define USB3_0_XHCI_GUCTL1_RESUME_TERMSEL_XCVRSEL_UNIFY_SHIFT 10 +#define USB3_0_XHCI_GUCTL1_RESUME_TERMSEL_XCVRSEL_UNIFY_MASK 0x00000400U + +/* +* Reserved +*/ +#undef USB3_0_XHCI_GUCTL1_RESERVED_9_DEFVAL +#undef USB3_0_XHCI_GUCTL1_RESERVED_9_SHIFT +#undef USB3_0_XHCI_GUCTL1_RESERVED_9_MASK +#define USB3_0_XHCI_GUCTL1_RESERVED_9_DEFVAL 0x00000000 +#define USB3_0_XHCI_GUCTL1_RESERVED_9_SHIFT 9 +#define USB3_0_XHCI_GUCTL1_RESERVED_9_MASK 0x00000200U + +/* +* Host IN Auto Retry (USBHstInAutoRetryEn) When set, this field enables th + * e Auto Retry feature. For IN transfers (non-isochronous) that encounter + * data packets with CRC errors or internal overrun scenarios, the auto ret + * ry feature causes the Host core to reply to the device with a non-termin + * ating retry ACK (that is, an ACK transaction packet with Retry = 1 and N + * umP != 0). If the Auto Retry feature is disabled (default), the core wil + * l respond with a terminating retry ACK (that is, an ACK transaction pack + * et with Retry = 1 and NumP = 0). - 1'b0: Auto Retry Disabled - 1'b1: Aut + * o Retry Enabled Note: This bit is also applicable to the device mode. +*/ +#undef USB3_0_XHCI_GUCTL_USBHSTINAUTORETRYEN_DEFVAL +#undef USB3_0_XHCI_GUCTL_USBHSTINAUTORETRYEN_SHIFT +#undef USB3_0_XHCI_GUCTL_USBHSTINAUTORETRYEN_MASK +#define USB3_0_XHCI_GUCTL_USBHSTINAUTORETRYEN_DEFVAL 0x00000000 +#define USB3_0_XHCI_GUCTL_USBHSTINAUTORETRYEN_SHIFT 14 +#define USB3_0_XHCI_GUCTL_USBHSTINAUTORETRYEN_MASK 0x00004000U + +/* +* If TRUE Completion Timeout Disable is supported. This is required to be + * TRUE for Endpoint and either setting allowed for Root ports. Drives Devi + * ce Capability 2 [4]; EP=0x0001; RP=0x0001 +*/ #undef PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_DEFVAL #undef PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_SHIFT #undef PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_MASK -#define PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_DEFVAL 0x00000905 -#define PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_SHIFT 9 -#define PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_MASK 0x00000200U +#define PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_DEFVAL 0x00000905 +#define PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_SHIFT 9 +#define PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_MASK 0x00000200U -/*Specifies mask/settings for Base Address Register (BAR) 0. If BAR is not to be implemented, set to 32'h00000000. Bits are def - ned as follows: Memory Space BAR [0] = Mem Space Indicator (set to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = - Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory a - erture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR1,BAR0\'7d to 1. IO Space BAR 0] = IO Space Indicator - set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o apert - re size in bytes.; EP=0x0004; RP=0x0000*/ +/* +* Specifies mask/settings for Base Address Register (BAR) 0. If BAR is not + * to be implemented, set to 32'h00000000. Bits are defined as follows: Me + * mory Space BAR [0] = Mem Space Indicator (set to 0) [2:1] = Type field ( + * 10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask + * for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to 1, w + * here 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63: + * n bits of \'7bBAR1,BAR0\'7d to 1. IO Space BAR 0] = IO Space Indicator ( + * set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of B + * AR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; + * EP=0x0004; RP=0x0000 +*/ #undef PCIE_ATTRIB_ATTR_7_ATTR_BAR0_DEFVAL #undef PCIE_ATTRIB_ATTR_7_ATTR_BAR0_SHIFT #undef PCIE_ATTRIB_ATTR_7_ATTR_BAR0_MASK -#define PCIE_ATTRIB_ATTR_7_ATTR_BAR0_DEFVAL -#define PCIE_ATTRIB_ATTR_7_ATTR_BAR0_SHIFT 0 -#define PCIE_ATTRIB_ATTR_7_ATTR_BAR0_MASK 0x0000FFFFU +#define PCIE_ATTRIB_ATTR_7_ATTR_BAR0_DEFVAL +#define PCIE_ATTRIB_ATTR_7_ATTR_BAR0_SHIFT 0 +#define PCIE_ATTRIB_ATTR_7_ATTR_BAR0_MASK 0x0000FFFFU -/*Specifies mask/settings for Base Address Register (BAR) 0. If BAR is not to be implemented, set to 32'h00000000. Bits are def - ned as follows: Memory Space BAR [0] = Mem Space Indicator (set to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = - Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory a - erture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR1,BAR0\'7d to 1. IO Space BAR 0] = IO Space Indicator - set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o apert - re size in bytes.; EP=0xFFF0; RP=0x0000*/ +/* +* Specifies mask/settings for Base Address Register (BAR) 0. If BAR is not + * to be implemented, set to 32'h00000000. Bits are defined as follows: Me + * mory Space BAR [0] = Mem Space Indicator (set to 0) [2:1] = Type field ( + * 10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask + * for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to 1, w + * here 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63: + * n bits of \'7bBAR1,BAR0\'7d to 1. IO Space BAR 0] = IO Space Indicator ( + * set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of B + * AR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; + * EP=0xFFF0; RP=0x0000 +*/ #undef PCIE_ATTRIB_ATTR_8_ATTR_BAR0_DEFVAL #undef PCIE_ATTRIB_ATTR_8_ATTR_BAR0_SHIFT #undef PCIE_ATTRIB_ATTR_8_ATTR_BAR0_MASK -#define PCIE_ATTRIB_ATTR_8_ATTR_BAR0_DEFVAL -#define PCIE_ATTRIB_ATTR_8_ATTR_BAR0_SHIFT 0 -#define PCIE_ATTRIB_ATTR_8_ATTR_BAR0_MASK 0x0000FFFFU +#define PCIE_ATTRIB_ATTR_8_ATTR_BAR0_DEFVAL +#define PCIE_ATTRIB_ATTR_8_ATTR_BAR0_SHIFT 0 +#define PCIE_ATTRIB_ATTR_8_ATTR_BAR0_MASK 0x0000FFFFU -/*Specifies mask/settings for Base Address Register (BAR) 1 if BAR0 is a 32-bit BAR, or the upper bits of \'7bBAR1,BAR0\'7d if - AR0 is a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR0 description if this functions as the uppe - bits of a 64-bit BAR. Bits are defined as follows: Memory Space BAR (not upper bits of BAR0) [0] = Mem Space Indicator (set - o 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if - 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of - '7bBAR2,BAR1\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable b - ts of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000*/ +/* +* Specifies mask/settings for Base Address Register (BAR) 1 if BAR0 is a 3 + * 2-bit BAR, or the upper bits of \'7bBAR1,BAR0\'7d if BAR0 is a 64-bit BA + * R. If BAR is not to be implemented, set to 32'h00000000. See BAR0 descri + * ption if this functions as the upper bits of a 64-bit BAR. Bits are defi + * ned as follows: Memory Space BAR (not upper bits of BAR0) [0] = Mem Spac + * e Indicator (set to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) + * [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if + * 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size + * in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR2,BAR1\'7d t + * o 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set + * to 0) [31:2] = Mask for writable bits of BAR; set uppermost 31:n bits t + * o 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000 +*/ #undef PCIE_ATTRIB_ATTR_9_ATTR_BAR1_DEFVAL #undef PCIE_ATTRIB_ATTR_9_ATTR_BAR1_SHIFT #undef PCIE_ATTRIB_ATTR_9_ATTR_BAR1_MASK -#define PCIE_ATTRIB_ATTR_9_ATTR_BAR1_DEFVAL -#define PCIE_ATTRIB_ATTR_9_ATTR_BAR1_SHIFT 0 -#define PCIE_ATTRIB_ATTR_9_ATTR_BAR1_MASK 0x0000FFFFU +#define PCIE_ATTRIB_ATTR_9_ATTR_BAR1_DEFVAL +#define PCIE_ATTRIB_ATTR_9_ATTR_BAR1_SHIFT 0 +#define PCIE_ATTRIB_ATTR_9_ATTR_BAR1_MASK 0x0000FFFFU -/*Specifies mask/settings for Base Address Register (BAR) 1 if BAR0 is a 32-bit BAR, or the upper bits of \'7bBAR1,BAR0\'7d if - AR0 is a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR0 description if this functions as the uppe - bits of a 64-bit BAR. Bits are defined as follows: Memory Space BAR (not upper bits of BAR0) [0] = Mem Space Indicator (set - o 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if - 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of - '7bBAR2,BAR1\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable b - ts of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000*/ +/* +* Specifies mask/settings for Base Address Register (BAR) 1 if BAR0 is a 3 + * 2-bit BAR, or the upper bits of \'7bBAR1,BAR0\'7d if BAR0 is a 64-bit BA + * R. If BAR is not to be implemented, set to 32'h00000000. See BAR0 descri + * ption if this functions as the upper bits of a 64-bit BAR. Bits are defi + * ned as follows: Memory Space BAR (not upper bits of BAR0) [0] = Mem Spac + * e Indicator (set to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) + * [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if + * 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size + * in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR2,BAR1\'7d t + * o 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set + * to 0) [31:2] = Mask for writable bits of BAR; set uppermost 31:n bits t + * o 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000 +*/ #undef PCIE_ATTRIB_ATTR_10_ATTR_BAR1_DEFVAL #undef PCIE_ATTRIB_ATTR_10_ATTR_BAR1_SHIFT #undef PCIE_ATTRIB_ATTR_10_ATTR_BAR1_MASK -#define PCIE_ATTRIB_ATTR_10_ATTR_BAR1_DEFVAL -#define PCIE_ATTRIB_ATTR_10_ATTR_BAR1_SHIFT 0 -#define PCIE_ATTRIB_ATTR_10_ATTR_BAR1_MASK 0x0000FFFFU +#define PCIE_ATTRIB_ATTR_10_ATTR_BAR1_DEFVAL +#define PCIE_ATTRIB_ATTR_10_ATTR_BAR1_SHIFT 0 +#define PCIE_ATTRIB_ATTR_10_ATTR_BAR1_MASK 0x0000FFFFU -/*For an endpoint, specifies mask/settings for Base Address Register (BAR) 2 if BAR1 is a 32-bit BAR, or the upper bits of \'7b - AR2,BAR1\'7d if BAR1 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR1 descri - tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to 00FF_FFFF. For an endpoin - , bits are defined as follows: Memory Space BAR (not upper bits of BAR1) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi - ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe - most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR3,BAR2\'7d to - . IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper - ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0x0004; RP=0xFFFF*/ +/* +* For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 2 if BAR1 is a 32-bit BAR, or the upper bits of \'7bBAR2,BAR1\'7d if BA + * R1 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR1 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root: This must be set to 00FF_FFF + * F. For an endpoint, bits are defined as follows: Memory Space BAR (not u + * pper bits of BAR1) [0] = Mem Space Indicator (set to 0) [2:1] = Type fie + * ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = M + * ask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to + * 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost + * 63:n bits of \'7bBAR3,BAR2\'7d to 1. IO Space BAR 0] = IO Space Indicat + * or (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits + * of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in byt + * es.; EP=0x0004; RP=0xFFFF +*/ #undef PCIE_ATTRIB_ATTR_11_ATTR_BAR2_DEFVAL #undef PCIE_ATTRIB_ATTR_11_ATTR_BAR2_SHIFT #undef PCIE_ATTRIB_ATTR_11_ATTR_BAR2_MASK -#define PCIE_ATTRIB_ATTR_11_ATTR_BAR2_DEFVAL -#define PCIE_ATTRIB_ATTR_11_ATTR_BAR2_SHIFT 0 -#define PCIE_ATTRIB_ATTR_11_ATTR_BAR2_MASK 0x0000FFFFU +#define PCIE_ATTRIB_ATTR_11_ATTR_BAR2_DEFVAL +#define PCIE_ATTRIB_ATTR_11_ATTR_BAR2_SHIFT 0 +#define PCIE_ATTRIB_ATTR_11_ATTR_BAR2_MASK 0x0000FFFFU -/*For an endpoint, specifies mask/settings for Base Address Register (BAR) 2 if BAR1 is a 32-bit BAR, or the upper bits of \'7b - AR2,BAR1\'7d if BAR1 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR1 descri - tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to 00FF_FFFF. For an endpoin - , bits are defined as follows: Memory Space BAR (not upper bits of BAR1) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi - ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe - most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR3,BAR2\'7d to - . IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper - ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFF0; RP=0x00FF*/ +/* +* For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 2 if BAR1 is a 32-bit BAR, or the upper bits of \'7bBAR2,BAR1\'7d if BA + * R1 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR1 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root: This must be set to 00FF_FFF + * F. For an endpoint, bits are defined as follows: Memory Space BAR (not u + * pper bits of BAR1) [0] = Mem Space Indicator (set to 0) [2:1] = Type fie + * ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = M + * ask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to + * 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost + * 63:n bits of \'7bBAR3,BAR2\'7d to 1. IO Space BAR 0] = IO Space Indicat + * or (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits + * of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in byt + * es.; EP=0xFFF0; RP=0x00FF +*/ #undef PCIE_ATTRIB_ATTR_12_ATTR_BAR2_DEFVAL #undef PCIE_ATTRIB_ATTR_12_ATTR_BAR2_SHIFT #undef PCIE_ATTRIB_ATTR_12_ATTR_BAR2_MASK -#define PCIE_ATTRIB_ATTR_12_ATTR_BAR2_DEFVAL -#define PCIE_ATTRIB_ATTR_12_ATTR_BAR2_SHIFT 0 -#define PCIE_ATTRIB_ATTR_12_ATTR_BAR2_MASK 0x0000FFFFU +#define PCIE_ATTRIB_ATTR_12_ATTR_BAR2_DEFVAL +#define PCIE_ATTRIB_ATTR_12_ATTR_BAR2_SHIFT 0 +#define PCIE_ATTRIB_ATTR_12_ATTR_BAR2_MASK 0x0000FFFFU -/*For an endpoint, specifies mask/settings for Base Address Register (BAR) 3 if BAR2 is a 32-bit BAR, or the upper bits of \'7b - AR3,BAR2\'7d if BAR2 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR2 descri - tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: FFFF_0000 = IO Limit/Bas - Registers not implemented FFFF_F0F0 = IO Limit/Base Registers use 16-bit decode FFFF_F1F1 = IO Limit/Base Registers use 32-b - t decode For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of BAR2) [0] = Mem Space Indicator (s - t to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; - if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits - f \'7bBAR4,BAR3\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writabl - bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000*/ +/* +* For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 3 if BAR2 is a 32-bit BAR, or the upper bits of \'7bBAR3,BAR2\'7d if BA + * R2 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR2 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root, this must be set to: FFFF_00 + * 00 = IO Limit/Base Registers not implemented FFFF_F0F0 = IO Limit/Base R + * egisters use 16-bit decode FFFF_F1F1 = IO Limit/Base Registers use 32-bi + * t decode For an endpoint, bits are defined as follows: Memory Space BAR + * (not upper bits of BAR2) [0] = Mem Space Indicator (set to 0) [2:1] = Ty + * pe field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31: + * 4] = Mask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bi + * ts to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set upp + * ermost 63:n bits of \'7bBAR4,BAR3\'7d to 1. IO Space BAR 0] = IO Space I + * ndicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable + * bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size + * in bytes.; EP=0xFFFF; RP=0x0000 +*/ #undef PCIE_ATTRIB_ATTR_13_ATTR_BAR3_DEFVAL #undef PCIE_ATTRIB_ATTR_13_ATTR_BAR3_SHIFT #undef PCIE_ATTRIB_ATTR_13_ATTR_BAR3_MASK -#define PCIE_ATTRIB_ATTR_13_ATTR_BAR3_DEFVAL -#define PCIE_ATTRIB_ATTR_13_ATTR_BAR3_SHIFT 0 -#define PCIE_ATTRIB_ATTR_13_ATTR_BAR3_MASK 0x0000FFFFU +#define PCIE_ATTRIB_ATTR_13_ATTR_BAR3_DEFVAL +#define PCIE_ATTRIB_ATTR_13_ATTR_BAR3_SHIFT 0 +#define PCIE_ATTRIB_ATTR_13_ATTR_BAR3_MASK 0x0000FFFFU -/*For an endpoint, specifies mask/settings for Base Address Register (BAR) 3 if BAR2 is a 32-bit BAR, or the upper bits of \'7b - AR3,BAR2\'7d if BAR2 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR2 descri - tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: FFFF_0000 = IO Limit/Bas - Registers not implemented FFFF_F0F0 = IO Limit/Base Registers use 16-bit decode FFFF_F1F1 = IO Limit/Base Registers use 32-b - t decode For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of BAR2) [0] = Mem Space Indicator (s - t to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; - if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits - f \'7bBAR4,BAR3\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writabl - bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0xFFFF*/ +/* +* For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 3 if BAR2 is a 32-bit BAR, or the upper bits of \'7bBAR3,BAR2\'7d if BA + * R2 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR2 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root, this must be set to: FFFF_00 + * 00 = IO Limit/Base Registers not implemented FFFF_F0F0 = IO Limit/Base R + * egisters use 16-bit decode FFFF_F1F1 = IO Limit/Base Registers use 32-bi + * t decode For an endpoint, bits are defined as follows: Memory Space BAR + * (not upper bits of BAR2) [0] = Mem Space Indicator (set to 0) [2:1] = Ty + * pe field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31: + * 4] = Mask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bi + * ts to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set upp + * ermost 63:n bits of \'7bBAR4,BAR3\'7d to 1. IO Space BAR 0] = IO Space I + * ndicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable + * bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size + * in bytes.; EP=0xFFFF; RP=0xFFFF +*/ #undef PCIE_ATTRIB_ATTR_14_ATTR_BAR3_DEFVAL #undef PCIE_ATTRIB_ATTR_14_ATTR_BAR3_SHIFT #undef PCIE_ATTRIB_ATTR_14_ATTR_BAR3_MASK -#define PCIE_ATTRIB_ATTR_14_ATTR_BAR3_DEFVAL -#define PCIE_ATTRIB_ATTR_14_ATTR_BAR3_SHIFT 0 -#define PCIE_ATTRIB_ATTR_14_ATTR_BAR3_MASK 0x0000FFFFU +#define PCIE_ATTRIB_ATTR_14_ATTR_BAR3_DEFVAL +#define PCIE_ATTRIB_ATTR_14_ATTR_BAR3_SHIFT 0 +#define PCIE_ATTRIB_ATTR_14_ATTR_BAR3_MASK 0x0000FFFFU -/*For an endpoint, specifies mask/settings for Base Address Register (BAR) 4 if BAR3 is a 32-bit BAR, or the upper bits of \'7b - AR4,BAR3\'7d if BAR3 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR3 descri - tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to FFF0_FFF0. For an endpoin - , bits are defined as follows: Memory Space BAR (not upper bits of BAR3) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi - ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe - most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR5,BAR4\'7d to - . IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper - ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0x0004; RP=0xFFF0*/ +/* +* For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 4 if BAR3 is a 32-bit BAR, or the upper bits of \'7bBAR4,BAR3\'7d if BA + * R3 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR3 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root: This must be set to FFF0_FFF + * 0. For an endpoint, bits are defined as follows: Memory Space BAR (not u + * pper bits of BAR3) [0] = Mem Space Indicator (set to 0) [2:1] = Type fie + * ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = M + * ask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to + * 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost + * 63:n bits of \'7bBAR5,BAR4\'7d to 1. IO Space BAR 0] = IO Space Indicat + * or (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits + * of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in byt + * es.; EP=0x0004; RP=0xFFF0 +*/ #undef PCIE_ATTRIB_ATTR_15_ATTR_BAR4_DEFVAL #undef PCIE_ATTRIB_ATTR_15_ATTR_BAR4_SHIFT #undef PCIE_ATTRIB_ATTR_15_ATTR_BAR4_MASK -#define PCIE_ATTRIB_ATTR_15_ATTR_BAR4_DEFVAL -#define PCIE_ATTRIB_ATTR_15_ATTR_BAR4_SHIFT 0 -#define PCIE_ATTRIB_ATTR_15_ATTR_BAR4_MASK 0x0000FFFFU +#define PCIE_ATTRIB_ATTR_15_ATTR_BAR4_DEFVAL +#define PCIE_ATTRIB_ATTR_15_ATTR_BAR4_SHIFT 0 +#define PCIE_ATTRIB_ATTR_15_ATTR_BAR4_MASK 0x0000FFFFU -/*For an endpoint, specifies mask/settings for Base Address Register (BAR) 4 if BAR3 is a 32-bit BAR, or the upper bits of \'7b - AR4,BAR3\'7d if BAR3 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR3 descri - tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to FFF0_FFF0. For an endpoin - , bits are defined as follows: Memory Space BAR (not upper bits of BAR3) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi - ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe - most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR5,BAR4\'7d to - . IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper - ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFF0; RP=0xFFF0*/ +/* +* For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 4 if BAR3 is a 32-bit BAR, or the upper bits of \'7bBAR4,BAR3\'7d if BA + * R3 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR3 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root: This must be set to FFF0_FFF + * 0. For an endpoint, bits are defined as follows: Memory Space BAR (not u + * pper bits of BAR3) [0] = Mem Space Indicator (set to 0) [2:1] = Type fie + * ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = M + * ask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to + * 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost + * 63:n bits of \'7bBAR5,BAR4\'7d to 1. IO Space BAR 0] = IO Space Indicat + * or (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits + * of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in byt + * es.; EP=0xFFF0; RP=0xFFF0 +*/ #undef PCIE_ATTRIB_ATTR_16_ATTR_BAR4_DEFVAL #undef PCIE_ATTRIB_ATTR_16_ATTR_BAR4_SHIFT #undef PCIE_ATTRIB_ATTR_16_ATTR_BAR4_MASK -#define PCIE_ATTRIB_ATTR_16_ATTR_BAR4_DEFVAL -#define PCIE_ATTRIB_ATTR_16_ATTR_BAR4_SHIFT 0 -#define PCIE_ATTRIB_ATTR_16_ATTR_BAR4_MASK 0x0000FFFFU +#define PCIE_ATTRIB_ATTR_16_ATTR_BAR4_DEFVAL +#define PCIE_ATTRIB_ATTR_16_ATTR_BAR4_SHIFT 0 +#define PCIE_ATTRIB_ATTR_16_ATTR_BAR4_MASK 0x0000FFFFU -/*For an endpoint, specifies mask/settings for Base Address Register (BAR) 5 if BAR4 is a 32-bit BAR, or the upper bits of \'7b - AR5,BAR4\'7d if BAR4 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR4 descri - tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: 0000_0000 = Prefetchable - Memory Limit/Base Registers not implemented FFF0_FFF0 = 32-bit Prefetchable Memory Limit/Base implemented FFF1_FFF1 = 64-bit - refetchable Memory Limit/Base implemented For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of B - R4) [0] = Mem Space Indicator (set to 0) [2:1] = Type field (00 for 32-bit; BAR5 cannot be lower part of a 64-bit BAR) [3] = - refetchable (0 or 1) [31:4] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=memory aperture size in - ytes. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set u - permost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0xFFF1*/ +/* +* For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 5 if BAR4 is a 32-bit BAR, or the upper bits of \'7bBAR5,BAR4\'7d if BA + * R4 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR4 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root, this must be set to: 0000_00 + * 00 = Prefetchable Memory Limit/Base Registers not implemented FFF0_FFF0 + * = 32-bit Prefetchable Memory Limit/Base implemented FFF1_FFF1 = 64-bit P + * refetchable Memory Limit/Base implemented For an endpoint, bits are defi + * ned as follows: Memory Space BAR (not upper bits of BAR4) [0] = Mem Spac + * e Indicator (set to 0) [2:1] = Type field (00 for 32-bit; BAR5 cannot be + * lower part of a 64-bit BAR) [3] = Prefetchable (0 or 1) [31:4] = Mask f + * or writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=memory + * aperture size in bytes. IO Space BAR 0] = IO Space Indicator (set to 1) + * [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set up + * permost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF + * ; RP=0xFFF1 +*/ #undef PCIE_ATTRIB_ATTR_17_ATTR_BAR5_DEFVAL #undef PCIE_ATTRIB_ATTR_17_ATTR_BAR5_SHIFT #undef PCIE_ATTRIB_ATTR_17_ATTR_BAR5_MASK -#define PCIE_ATTRIB_ATTR_17_ATTR_BAR5_DEFVAL -#define PCIE_ATTRIB_ATTR_17_ATTR_BAR5_SHIFT 0 -#define PCIE_ATTRIB_ATTR_17_ATTR_BAR5_MASK 0x0000FFFFU +#define PCIE_ATTRIB_ATTR_17_ATTR_BAR5_DEFVAL +#define PCIE_ATTRIB_ATTR_17_ATTR_BAR5_SHIFT 0 +#define PCIE_ATTRIB_ATTR_17_ATTR_BAR5_MASK 0x0000FFFFU -/*For an endpoint, specifies mask/settings for Base Address Register (BAR) 5 if BAR4 is a 32-bit BAR, or the upper bits of \'7b - AR5,BAR4\'7d if BAR4 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR4 descri - tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: 0000_0000 = Prefetchable - Memory Limit/Base Registers not implemented FFF0_FFF0 = 32-bit Prefetchable Memory Limit/Base implemented FFF1_FFF1 = 64-bit - refetchable Memory Limit/Base implemented For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of B - R4) [0] = Mem Space Indicator (set to 0) [2:1] = Type field (00 for 32-bit; BAR5 cannot be lower part of a 64-bit BAR) [3] = - refetchable (0 or 1) [31:4] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=memory aperture size in - ytes. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set u - permost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0xFFF1*/ +/* +* For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 5 if BAR4 is a 32-bit BAR, or the upper bits of \'7bBAR5,BAR4\'7d if BA + * R4 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR4 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root, this must be set to: 0000_00 + * 00 = Prefetchable Memory Limit/Base Registers not implemented FFF0_FFF0 + * = 32-bit Prefetchable Memory Limit/Base implemented FFF1_FFF1 = 64-bit P + * refetchable Memory Limit/Base implemented For an endpoint, bits are defi + * ned as follows: Memory Space BAR (not upper bits of BAR4) [0] = Mem Spac + * e Indicator (set to 0) [2:1] = Type field (00 for 32-bit; BAR5 cannot be + * lower part of a 64-bit BAR) [3] = Prefetchable (0 or 1) [31:4] = Mask f + * or writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=memory + * aperture size in bytes. IO Space BAR 0] = IO Space Indicator (set to 1) + * [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set up + * permost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF + * ; RP=0xFFF1 +*/ #undef PCIE_ATTRIB_ATTR_18_ATTR_BAR5_DEFVAL #undef PCIE_ATTRIB_ATTR_18_ATTR_BAR5_SHIFT #undef PCIE_ATTRIB_ATTR_18_ATTR_BAR5_MASK -#define PCIE_ATTRIB_ATTR_18_ATTR_BAR5_DEFVAL -#define PCIE_ATTRIB_ATTR_18_ATTR_BAR5_SHIFT 0 -#define PCIE_ATTRIB_ATTR_18_ATTR_BAR5_MASK 0x0000FFFFU +#define PCIE_ATTRIB_ATTR_18_ATTR_BAR5_DEFVAL +#define PCIE_ATTRIB_ATTR_18_ATTR_BAR5_SHIFT 0 +#define PCIE_ATTRIB_ATTR_18_ATTR_BAR5_MASK 0x0000FFFFU -/*Specifies maximum payload supported. Valid settings are: 0- 128 bytes, 1- 256 bytes, 2- 512 bytes, 3- 1024 bytes. Transferred - to the Device Capabilities register. The values: 4-2048 bytes, 5- 4096 bytes are not supported; EP=0x0001; RP=0x0001*/ +/* +* Specifies maximum payload supported. Valid settings are: 0- 128 bytes, 1 + * - 256 bytes, 2- 512 bytes, 3- 1024 bytes. Transferred to the Device Capa + * bilities register. The values: 4-2048 bytes, 5- 4096 bytes are not suppo + * rted; EP=0x0001; RP=0x0001 +*/ #undef PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_DEFVAL #undef PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_SHIFT #undef PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_MASK -#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_DEFVAL 0x00002138 -#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_SHIFT 8 -#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_MASK 0x00000700U +#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_DEFVAL 0x00002138 +#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_SHIFT 8 +#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_MASK 0x00000700U -/*Endpoint L1 Acceptable Latency. Records the latency that the endpoint can withstand on transitions from L1 state to L0 (if L1 - state supported). Valid settings are: 0h less than 1us, 1h 1 to 2us, 2h 2 to 4us, 3h 4 to 8us, 4h 8 to 16us, 5h 16 to 32us, 6 - 32 to 64us, 7h more than 64us. For Endpoints only. Must be 0h for other devices.; EP=0x0007; RP=0x0000*/ +/* +* Endpoint L1 Acceptable Latency. Records the latency that the endpoint ca + * n withstand on transitions from L1 state to L0 (if L1 state supported). + * Valid settings are: 0h less than 1us, 1h 1 to 2us, 2h 2 to 4us, 3h 4 to + * 8us, 4h 8 to 16us, 5h 16 to 32us, 6h 32 to 64us, 7h more than 64us. For + * Endpoints only. Must be 0h for other devices.; EP=0x0007; RP=0x0000 +*/ #undef PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_DEFVAL #undef PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_SHIFT #undef PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_MASK -#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_DEFVAL 0x00002138 -#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_SHIFT 3 -#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_MASK 0x00000038U +#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_DEFVAL 0x00002138 +#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_SHIFT 3 +#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_MASK 0x00000038U -/*Identifies the type of device/port as follows: 0000b PCI Express Endpoint device, 0001b Legacy PCI Express Endpoint device, 0 - 00b Root Port of PCI Express Root Complex, 0101b Upstream Port of PCI Express Switch, 0110b Downstream Port of PCI Express Sw - tch, 0111b PCIE Express to PCI/PCI-X Bridge, 1000b PCI/PCI-X to PCI Express Bridge. Transferred to PCI Express Capabilities r - gister. Must be consistent with IS_SWITCH and UPSTREAM_FACING settings.; EP=0x0000; RP=0x0004*/ +/* +* Identifies the type of device/port as follows: 0000b PCI Express Endpoin + * t device, 0001b Legacy PCI Express Endpoint device, 0100b Root Port of P + * CI Express Root Complex, 0101b Upstream Port of PCI Express Switch, 0110 + * b Downstream Port of PCI Express Switch, 0111b PCIE Express to PCI/PCI-X + * Bridge, 1000b PCI/PCI-X to PCI Express Bridge. Transferred to PCI Expre + * ss Capabilities register. Must be consistent with IS_SWITCH and UPSTREAM + * _FACING settings.; EP=0x0000; RP=0x0004 +*/ #undef PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_DEFVAL #undef PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_SHIFT #undef PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_MASK -#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_DEFVAL 0x00009C02 -#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_SHIFT 4 -#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_MASK 0x000000F0U +#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_DEFVAL 0x00009C02 +#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_SHIFT 4 +#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_MASK 0x000000F0U -/*PCIe Capability's Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capab - lity.; EP=0x009C; RP=0x0000*/ +/* +* PCIe Capability's Next Capability Offset pointer to the next item in the + * capabilities list, or 00h if this is the final capability.; EP=0x009C; + * RP=0x0000 +*/ #undef PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_DEFVAL #undef PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_SHIFT #undef PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_MASK -#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_DEFVAL 0x00009C02 -#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_SHIFT 8 -#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_MASK 0x0000FF00U +#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_DEFVAL 0x00009C02 +#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_SHIFT 8 +#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_MASK 0x0000FF00U -/*Number of credits that should be advertised for Completion data received on Virtual Channel 0. The bytes advertised must be l - ss than or equal to the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0172; RP=0x00CD*/ +/* +* Number of credits that should be advertised for Completion data received + * on Virtual Channel 0. The bytes advertised must be less than or equal t + * o the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0172; RP=0x00CD +*/ #undef PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_DEFVAL #undef PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_SHIFT #undef PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_MASK -#define PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_DEFVAL -#define PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_SHIFT 0 -#define PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_MASK 0x000007FFU +#define PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_DEFVAL +#define PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_SHIFT 0 +#define PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_MASK 0x000007FFU -/*Number of credits that should be advertised for Completion headers received on Virtual Channel 0. The sum of the posted, non - osted, and completion header credits must be <= 80; EP=0x0048; RP=0x0024*/ +/* +* Number of credits that should be advertised for Completion headers recei + * ved on Virtual Channel 0. The sum of the posted, non posted, and complet + * ion header credits must be <= 80; EP=0x0048; RP=0x0024 +*/ #undef PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_DEFVAL #undef PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_SHIFT #undef PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_MASK -#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_DEFVAL 0x00000248 -#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_SHIFT 0 -#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_MASK 0x0000007FU +#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_DEFVAL 0x00000248 +#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_SHIFT 0 +#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_MASK 0x0000007FU -/*Number of credits that should be advertised for Non-Posted headers received on Virtual Channel 0. The number of non posted da - a credits advertised by the block is equal to the number of non posted header credits. The sum of the posted, non posted, and - completion header credits must be <= 80; EP=0x0004; RP=0x000C*/ +/* +* Number of credits that should be advertised for Non-Posted headers recei + * ved on Virtual Channel 0. The number of non posted data credits advertis + * ed by the block is equal to the number of non posted header credits. The + * sum of the posted, non posted, and completion header credits must be <= + * 80; EP=0x0004; RP=0x000C +*/ #undef PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_DEFVAL #undef PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_SHIFT #undef PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_MASK -#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_DEFVAL 0x00000248 -#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_SHIFT 7 -#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_MASK 0x00003F80U +#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_DEFVAL 0x00000248 +#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_SHIFT 7 +#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_MASK 0x00003F80U -/*Number of credits that should be advertised for Non-Posted data received on Virtual Channel 0. The number of non posted data - redits advertised by the block is equal to two times the number of non posted header credits if atomic operations are support - d or is equal to the number of non posted header credits if atomic operations are not supported. The bytes advertised must be - less than or equal to the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0008; RP=0x0018*/ +/* +* Number of credits that should be advertised for Non-Posted data received + * on Virtual Channel 0. The number of non posted data credits advertised + * by the block is equal to two times the number of non posted header credi + * ts if atomic operations are supported or is equal to the number of non p + * osted header credits if atomic operations are not supported. The bytes a + * dvertised must be less than or equal to the bram bytes available. See VC + * 0_RX_RAM_LIMIT; EP=0x0008; RP=0x0018 +*/ #undef PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_DEFVAL #undef PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_SHIFT #undef PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_MASK -#define PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_DEFVAL -#define PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_SHIFT 0 -#define PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_MASK 0x000007FFU +#define PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_DEFVAL +#define PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_SHIFT 0 +#define PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_MASK 0x000007FFU -/*Number of credits that should be advertised for Posted data received on Virtual Channel 0. The bytes advertised must be less - han or equal to the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0020; RP=0x00B5*/ +/* +* Number of credits that should be advertised for Posted data received on + * Virtual Channel 0. The bytes advertised must be less than or equal to th + * e bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0020; RP=0x00B5 +*/ #undef PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_DEFVAL #undef PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_SHIFT #undef PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_MASK -#define PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_DEFVAL -#define PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_SHIFT 0 -#define PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_MASK 0x000007FFU +#define PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_DEFVAL +#define PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_SHIFT 0 +#define PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_MASK 0x000007FFU -/*Not currently in use. Invert ECRC generated by block when trn_tecrc_gen_n and trn_terrfwd_n are asserted.; EP=0x0000; RP=0x00 - 0*/ +/* +* Not currently in use. Invert ECRC generated by block when trn_tecrc_gen_ + * n and trn_terrfwd_n are asserted.; EP=0x0000; RP=0x0000 +*/ #undef PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_DEFVAL #undef PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_SHIFT #undef PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_MASK -#define PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_DEFVAL 0x00007E04 -#define PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_SHIFT 15 -#define PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_MASK 0x00008000U +#define PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_DEFVAL 0x00007E04 +#define PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_SHIFT 15 +#define PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_MASK 0x00008000U -/*Enables td bit clear and ECRC trim on received TLP's FALSE == don't trim TRUE == trim.; EP=0x0001; RP=0x0001*/ +/* +* Enables td bit clear and ECRC trim on received TLP's FALSE == don't trim + * TRUE == trim.; EP=0x0001; RP=0x0001 +*/ #undef PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_DEFVAL #undef PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_SHIFT #undef PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_MASK -#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_DEFVAL 0x00007E04 -#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_SHIFT 14 -#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_MASK 0x00004000U +#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_DEFVAL 0x00007E04 +#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_SHIFT 14 +#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_MASK 0x00004000U -/*Enables ECRC check on received TLP's 0 == don't check 1 == always check 3 == check if enabled by ECRC check enable bit of AER - cap structure; EP=0x0003; RP=0x0003*/ +/* +* Enables ECRC check on received TLP's 0 == don't check 1 == always check + * 3 == check if enabled by ECRC check enable bit of AER cap structure; EP= + * 0x0003; RP=0x0003 +*/ #undef PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_DEFVAL #undef PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_SHIFT #undef PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_MASK -#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_DEFVAL 0x00007E04 -#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_SHIFT 12 -#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_MASK 0x00003000U +#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_DEFVAL 0x00007E04 +#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_SHIFT 12 +#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_MASK 0x00003000U -/*Index of last packet buffer used by TX TLM (i.e. number of buffers - 1). Calculated from max payload size supported and the n - mber of brams configured for transmit; EP=0x001C; RP=0x001C*/ +/* +* Index of last packet buffer used by TX TLM (i.e. number of buffers - 1). + * Calculated from max payload size supported and the number of brams conf + * igured for transmit; EP=0x001C; RP=0x001C +*/ #undef PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_DEFVAL #undef PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_SHIFT #undef PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_MASK -#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_DEFVAL 0x00007E04 -#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_SHIFT 7 -#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_MASK 0x00000F80U +#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_DEFVAL 0x00007E04 +#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_SHIFT 7 +#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_MASK 0x00000F80U -/*Number of credits that should be advertised for Posted headers received on Virtual Channel 0. The sum of the posted, non post - d, and completion header credits must be <= 80; EP=0x0004; RP=0x0020*/ +/* +* Number of credits that should be advertised for Posted headers received + * on Virtual Channel 0. The sum of the posted, non posted, and completion + * header credits must be <= 80; EP=0x0004; RP=0x0020 +*/ #undef PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_DEFVAL #undef PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_SHIFT #undef PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_MASK -#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_DEFVAL 0x00007E04 -#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_SHIFT 0 -#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_MASK 0x0000007FU +#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_DEFVAL 0x00007E04 +#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_SHIFT 0 +#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_MASK 0x0000007FU -/*Specifies values to be transferred to Header Type register. Bit 7 should be set to '0' indicating single-function device. Bit - 0 identifies header as Type 0 or Type 1, with '0' indicating a Type 0 header.; EP=0x0000; RP=0x0001*/ +/* +* Specifies values to be transferred to Header Type register. Bit 7 should + * be set to '0' indicating single-function device. Bit 0 identifies heade + * r as Type 0 or Type 1, with '0' indicating a Type 0 header.; EP=0x0000; + * RP=0x0001 +*/ #undef PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_DEFVAL #undef PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_SHIFT #undef PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_MASK -#define PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_DEFVAL 0x00000100 -#define PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_SHIFT 0 -#define PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_MASK 0x000000FFU +#define PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_DEFVAL 0x00000100 +#define PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_SHIFT 0 +#define PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_MASK 0x000000FFU -/*PM Capability's Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capabil - ty.; EP=0x0048; RP=0x0060*/ +/* +* PM Capability's Next Capability Offset pointer to the next item in the c + * apabilities list, or 00h if this is the final capability.; EP=0x0048; RP + * =0x0060 +*/ #undef PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_DEFVAL #undef PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_SHIFT #undef PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_MASK -#define PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_DEFVAL 0x00003D48 -#define PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_SHIFT 0 -#define PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_MASK 0x000000FFU +#define PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_DEFVAL 0x00003D48 +#define PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_SHIFT 0 +#define PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_MASK 0x000000FFU -/*MSI Per-Vector Masking Capable. The value is transferred to the MSI Control Register[8]. When set, adds Mask and Pending Dwor - to Cap structure; EP=0x0000; RP=0x0000*/ +/* +* MSI Per-Vector Masking Capable. The value is transferred to the MSI Cont + * rol Register[8]. When set, adds Mask and Pending Dword to Cap structure; + * EP=0x0000; RP=0x0000 +*/ #undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_DEFVAL #undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_SHIFT #undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_MASK -#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_DEFVAL 0x00000160 -#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_SHIFT 9 -#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_MASK 0x00000200U +#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_DEFVAL 0x00000160 +#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_SHIFT 9 +#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_MASK 0x00000200U -/*Indicates that the MSI structures exists. If this is FALSE, then the MSI structure cannot be accessed via either the link or - he management port.; EP=0x0001; RP=0x0000*/ +/* +* Indicates that the MSI structures exists. If this is FALSE, then the MSI + * structure cannot be accessed via either the link or the management port + * .; EP=0x0001; RP=0x0000 +*/ #undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_DEFVAL #undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_SHIFT #undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_MASK -#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_DEFVAL 0x00000160 -#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_SHIFT 8 -#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_MASK 0x00000100U +#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_DEFVAL 0x00000160 +#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_SHIFT 8 +#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_MASK 0x00000100U -/*MSI Capability's Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capabi - ity.; EP=0x0060; RP=0x0000*/ +/* +* MSI Capability's Next Capability Offset pointer to the next item in the + * capabilities list, or 00h if this is the final capability.; EP=0x0060; R + * P=0x0000 +*/ #undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_DEFVAL #undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_SHIFT #undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_MASK -#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_DEFVAL 0x00000160 -#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_SHIFT 0 -#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_MASK 0x000000FFU +#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_DEFVAL 0x00000160 +#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_SHIFT 0 +#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_MASK 0x000000FFU -/*Indicates that the MSI structures exists. If this is FALSE, then the MSI structure cannot be accessed via either the link or - he management port.; EP=0x0001; RP=0x0000*/ +/* +* Indicates that the MSI structures exists. If this is FALSE, then the MSI + * structure cannot be accessed via either the link or the management port + * .; EP=0x0001; RP=0x0000 +*/ #undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_DEFVAL #undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_SHIFT #undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_MASK -#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_DEFVAL 0x00000160 -#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_SHIFT 8 -#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_MASK 0x00000100U +#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_DEFVAL 0x00000160 +#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_SHIFT 8 +#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_MASK 0x00000100U -/*Maximum Link Width. Valid settings are: 000001b x1, 000010b x2, 000100b x4, 001000b x8.; EP=0x0004; RP=0x0004*/ +/* +* Maximum Link Width. Valid settings are: 000001b x1, 000010b x2, 000100b + * x4, 001000b x8.; EP=0x0004; RP=0x0004 +*/ #undef PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_DEFVAL #undef PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_SHIFT #undef PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_MASK -#define PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_DEFVAL 0x00000104 -#define PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_SHIFT 0 -#define PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_MASK 0x0000003FU +#define PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_DEFVAL 0x00000104 +#define PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_SHIFT 0 +#define PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_MASK 0x0000003FU -/*Used by LTSSM to set Maximum Link Width. Valid settings are: 000001b [x1], 000010b [x2], 000100b [x4], 001000b [x8].; EP=0x00 - 4; RP=0x0004*/ +/* +* Used by LTSSM to set Maximum Link Width. Valid settings are: 000001b [x1 + * ], 000010b [x2], 000100b [x4], 001000b [x8].; EP=0x0004; RP=0x0004 +*/ #undef PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_DEFVAL #undef PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_SHIFT #undef PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_MASK -#define PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_DEFVAL 0x00000104 -#define PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_SHIFT 6 -#define PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_MASK 0x00000FC0U +#define PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_DEFVAL 0x00000104 +#define PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_SHIFT 6 +#define PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_MASK 0x00000FC0U -/*TRUE specifies upstream-facing port. FALSE specifies downstream-facing port.; EP=0x0001; RP=0x0000*/ +/* +* TRUE specifies upstream-facing port. FALSE specifies downstream-facing p + * ort.; EP=0x0001; RP=0x0000 +*/ #undef PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_DEFVAL #undef PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_SHIFT #undef PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_MASK -#define PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_DEFVAL 0x000000F0 -#define PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_SHIFT 6 -#define PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_MASK 0x00000040U +#define PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_DEFVAL 0x000000F0 +#define PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_SHIFT 6 +#define PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_MASK 0x00000040U -/*Enable the routing of message TLPs to the user through the TRN RX interface. A bit value of 1 enables routing of the message - LP to the user. Messages are always decoded by the message decoder. Bit 0 - ERR COR, Bit 1 - ERR NONFATAL, Bit 2 - ERR FATAL, - Bit 3 - INTA Bit 4 - INTB, Bit 5 - INTC, Bit 6 - INTD, Bit 7 PM_PME, Bit 8 - PME_TO_ACK, Bit 9 - unlock, Bit 10 PME_Turn_Off; - EP=0x0000; RP=0x07FF*/ +/* +* Enable the routing of message TLPs to the user through the TRN RX interf + * ace. A bit value of 1 enables routing of the message TLP to the user. Me + * ssages are always decoded by the message decoder. Bit 0 - ERR COR, Bit 1 + * - ERR NONFATAL, Bit 2 - ERR FATAL, Bit 3 - INTA Bit 4 - INTB, Bit 5 - I + * NTC, Bit 6 - INTD, Bit 7 PM_PME, Bit 8 - PME_TO_ACK, Bit 9 - unlock, Bit + * 10 PME_Turn_Off; EP=0x0000; RP=0x07FF +*/ #undef PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_DEFVAL #undef PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_SHIFT #undef PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_MASK -#define PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_DEFVAL 0x00000000 -#define PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_SHIFT 5 -#define PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_MASK 0x0000FFE0U +#define PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_DEFVAL 0x00000000 +#define PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_SHIFT 5 +#define PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_MASK 0x0000FFE0U -/*Disable BAR filtering. Does not change the behavior of the bar hit outputs; EP=0x0000; RP=0x0001*/ +/* +* Disable BAR filtering. Does not change the behavior of the bar hit outpu + * ts; EP=0x0000; RP=0x0001 +*/ #undef PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_DEFVAL #undef PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_SHIFT #undef PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_MASK -#define PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_DEFVAL 0x00000000 -#define PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_SHIFT 1 -#define PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_MASK 0x00000002U +#define PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_DEFVAL 0x00000000 +#define PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_SHIFT 1 +#define PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_MASK 0x00000002U -/*Link Bandwidth notification capability. Indicates support for the link bandwidth notification status and interrupt mechanism. - Required for Root.; EP=0x0000; RP=0x0001*/ +/* +* Link Bandwidth notification capability. Indicates support for the link b + * andwidth notification status and interrupt mechanism. Required for Root. + * ; EP=0x0000; RP=0x0001 +*/ #undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_DEFVAL #undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_SHIFT #undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_MASK -#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_DEFVAL 0x000009FF -#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_SHIFT 9 -#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_MASK 0x00000200U +#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_DEFVAL 0x000009FF +#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_SHIFT 9 +#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_MASK 0x00000200U -/*Sets the ASPM Optionality Compliance bit, to comply with the 2.1 ASPM Optionality ECN. Transferred to the Link Capabilities r - gister.; EP=0x0001; RP=0x0001*/ +/* +* Sets the ASPM Optionality Compliance bit, to comply with the 2.1 ASPM Op + * tionality ECN. Transferred to the Link Capabilities register.; EP=0x0001 + * ; RP=0x0001 +*/ #undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_DEFVAL #undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_SHIFT #undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_MASK -#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_DEFVAL 0x000009FF -#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_SHIFT 14 -#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_MASK 0x00004000U +#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_DEFVAL 0x000009FF +#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_SHIFT 14 +#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_MASK 0x00004000U -/*Enables the Replay Timer to use the user-defined LL_REPLAY_TIMEOUT value (or combined with the built-in value, depending on L - _REPLAY_TIMEOUT_FUNC). If FALSE, the built-in value is used.; EP=0x0000; RP=0x0000*/ +/* +* Enables the Replay Timer to use the user-defined LL_REPLAY_TIMEOUT value + * (or combined with the built-in value, depending on LL_REPLAY_TIMEOUT_FU + * NC). If FALSE, the built-in value is used.; EP=0x0000; RP=0x0000 +*/ #undef PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_DEFVAL #undef PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_SHIFT #undef PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_MASK -#define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_DEFVAL 0x00000000 -#define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_SHIFT 15 -#define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_MASK 0x00008000U +#define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_DEFVAL 0x00000000 +#define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_SHIFT 15 +#define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_MASK 0x00008000U -/*Sets a user-defined timeout for the Replay Timer to force cause the retransmission of unacknowledged TLPs; refer to LL_REPLAY - TIMEOUT_EN and LL_REPLAY_TIMEOUT_FUNC to see how this value is used. The unit for this attribute is in symbol times, which is - 4ns at GEN1 speeds and 2ns at GEN2.; EP=0x0000; RP=0x0000*/ +/* +* Sets a user-defined timeout for the Replay Timer to force cause the retr + * ansmission of unacknowledged TLPs; refer to LL_REPLAY_TIMEOUT_EN and LL_ + * REPLAY_TIMEOUT_FUNC to see how this value is used. The unit for this att + * ribute is in symbol times, which is 4ns at GEN1 speeds and 2ns at GEN2.; + * EP=0x0000; RP=0x0000 +*/ #undef PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_DEFVAL #undef PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_SHIFT #undef PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_MASK -#define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_DEFVAL 0x00000000 -#define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_SHIFT 0 -#define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_MASK 0x00007FFFU +#define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_DEFVAL 0x00000000 +#define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_SHIFT 0 +#define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_MASK 0x00007FFFU -/*Device ID for the the PCIe Cap Structure Device ID field*/ +/* +* Device ID for the the PCIe Cap Structure Device ID field +*/ #undef PCIE_ATTRIB_ID_CFG_DEV_ID_DEFVAL #undef PCIE_ATTRIB_ID_CFG_DEV_ID_SHIFT #undef PCIE_ATTRIB_ID_CFG_DEV_ID_MASK -#define PCIE_ATTRIB_ID_CFG_DEV_ID_DEFVAL 0x10EE7024 -#define PCIE_ATTRIB_ID_CFG_DEV_ID_SHIFT 0 -#define PCIE_ATTRIB_ID_CFG_DEV_ID_MASK 0x0000FFFFU +#define PCIE_ATTRIB_ID_CFG_DEV_ID_DEFVAL 0x10EE7024 +#define PCIE_ATTRIB_ID_CFG_DEV_ID_SHIFT 0 +#define PCIE_ATTRIB_ID_CFG_DEV_ID_MASK 0x0000FFFFU -/*Vendor ID for the PCIe Cap Structure Vendor ID field*/ +/* +* Vendor ID for the PCIe Cap Structure Vendor ID field +*/ #undef PCIE_ATTRIB_ID_CFG_VEND_ID_DEFVAL #undef PCIE_ATTRIB_ID_CFG_VEND_ID_SHIFT #undef PCIE_ATTRIB_ID_CFG_VEND_ID_MASK -#define PCIE_ATTRIB_ID_CFG_VEND_ID_DEFVAL 0x10EE7024 -#define PCIE_ATTRIB_ID_CFG_VEND_ID_SHIFT 16 -#define PCIE_ATTRIB_ID_CFG_VEND_ID_MASK 0xFFFF0000U +#define PCIE_ATTRIB_ID_CFG_VEND_ID_DEFVAL 0x10EE7024 +#define PCIE_ATTRIB_ID_CFG_VEND_ID_SHIFT 16 +#define PCIE_ATTRIB_ID_CFG_VEND_ID_MASK 0xFFFF0000U -/*Subsystem ID for the the PCIe Cap Structure Subsystem ID field*/ +/* +* Subsystem ID for the the PCIe Cap Structure Subsystem ID field +*/ #undef PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_DEFVAL #undef PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_SHIFT #undef PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_MASK -#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_DEFVAL 0x10EE0007 -#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_SHIFT 0 -#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_MASK 0x0000FFFFU +#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_DEFVAL 0x10EE0007 +#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_SHIFT 0 +#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_MASK 0x0000FFFFU -/*Subsystem Vendor ID for the PCIe Cap Structure Subsystem Vendor ID field*/ +/* +* Subsystem Vendor ID for the PCIe Cap Structure Subsystem Vendor ID field +*/ #undef PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_DEFVAL #undef PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_SHIFT #undef PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_MASK -#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_DEFVAL 0x10EE0007 -#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_SHIFT 16 -#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_MASK 0xFFFF0000U +#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_DEFVAL 0x10EE0007 +#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_SHIFT 16 +#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_MASK 0xFFFF0000U -/*Revision ID for the the PCIe Cap Structure*/ +/* +* Revision ID for the the PCIe Cap Structure +*/ #undef PCIE_ATTRIB_REV_ID_CFG_REV_ID_DEFVAL #undef PCIE_ATTRIB_REV_ID_CFG_REV_ID_SHIFT #undef PCIE_ATTRIB_REV_ID_CFG_REV_ID_MASK -#define PCIE_ATTRIB_REV_ID_CFG_REV_ID_DEFVAL -#define PCIE_ATTRIB_REV_ID_CFG_REV_ID_SHIFT 0 -#define PCIE_ATTRIB_REV_ID_CFG_REV_ID_MASK 0x000000FFU +#define PCIE_ATTRIB_REV_ID_CFG_REV_ID_DEFVAL +#define PCIE_ATTRIB_REV_ID_CFG_REV_ID_SHIFT 0 +#define PCIE_ATTRIB_REV_ID_CFG_REV_ID_MASK 0x000000FFU -/*Code identifying basic function, subclass and applicable programming interface. Transferred to the Class Code register.; EP=0 - 8000; RP=0x8000*/ +/* +* Code identifying basic function, subclass and applicable programming int + * erface. Transferred to the Class Code register.; EP=0x8000; RP=0x8000 +*/ #undef PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_DEFVAL #undef PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_SHIFT #undef PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_MASK -#define PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_DEFVAL -#define PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_SHIFT 0 -#define PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_MASK 0x0000FFFFU +#define PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_DEFVAL +#define PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_SHIFT 0 +#define PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_MASK 0x0000FFFFU -/*Code identifying basic function, subclass and applicable programming interface. Transferred to the Class Code register.; EP=0 - 0005; RP=0x0006*/ +/* +* Code identifying basic function, subclass and applicable programming int + * erface. Transferred to the Class Code register.; EP=0x0005; RP=0x0006 +*/ #undef PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_DEFVAL #undef PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_SHIFT #undef PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_MASK -#define PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_DEFVAL 0x00000905 -#define PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_SHIFT 0 -#define PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_MASK 0x000000FFU +#define PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_DEFVAL 0x00000905 +#define PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_SHIFT 0 +#define PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_MASK 0x000000FFU -/*INTX Interrupt Generation Capable. If FALSE, this will cause Command[10] to be hardwired to 0.; EP=0x0001; RP=0x0001*/ +/* +* INTX Interrupt Generation Capable. If FALSE, this will cause Command[10] + * to be hardwired to 0.; EP=0x0001; RP=0x0001 +*/ #undef PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_DEFVAL #undef PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_SHIFT #undef PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_MASK -#define PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_DEFVAL 0x00000905 -#define PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_SHIFT 8 -#define PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_MASK 0x00000100U +#define PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_DEFVAL 0x00000905 +#define PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_SHIFT 8 +#define PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_MASK 0x00000100U -/*Indicates that the AER structures exists. If this is FALSE, then the AER structure cannot be accessed via either the link or - he management port, and AER will be considered to not be present for error management tasks (such as what types of error mess - ges are sent if an error is detected).; EP=0x0001; RP=0x0001*/ +/* +* Indicates that the AER structures exists. If this is FALSE, then the AER + * structure cannot be accessed via either the link or the management port + * , and AER will be considered to not be present for error management task + * s (such as what types of error messages are sent if an error is detected + * ).; EP=0x0001; RP=0x0001 +*/ #undef PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_DEFVAL #undef PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_SHIFT #undef PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_MASK -#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_DEFVAL 0x00001000 -#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_SHIFT 12 -#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_MASK 0x00001000U +#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_DEFVAL 0x00001000 +#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_SHIFT 12 +#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_MASK 0x00001000U -/*Indicates that the AER structures exists. If this is FALSE, then the AER structure cannot be accessed via either the link or - he management port, and AER will be considered to not be present for error management tasks (such as what types of error mess - ges are sent if an error is detected).; EP=0x0001; RP=0x0001*/ +/* +* Indicates that the AER structures exists. If this is FALSE, then the AER + * structure cannot be accessed via either the link or the management port + * , and AER will be considered to not be present for error management task + * s (such as what types of error messages are sent if an error is detected + * ).; EP=0x0001; RP=0x0001 +*/ #undef PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_DEFVAL #undef PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_SHIFT #undef PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_MASK -#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_DEFVAL 0x00001000 -#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_SHIFT 12 -#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_MASK 0x00001000U +#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_DEFVAL 0x00001000 +#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_SHIFT 12 +#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_MASK 0x00001000U -/*VSEC's Next Capability Offset pointer to the next item in the capabilities list, or 000h if this is the final capability.; EP - 0x0140; RP=0x0140*/ +/* +* VSEC's Next Capability Offset pointer to the next item in the capabiliti + * es list, or 000h if this is the final capability.; EP=0x0140; RP=0x0140 +*/ #undef PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_DEFVAL #undef PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_SHIFT #undef PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_MASK -#define PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_DEFVAL 0x00002281 -#define PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_SHIFT 1 -#define PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_MASK 0x00001FFEU +#define PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_DEFVAL 0x00002281 +#define PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_SHIFT 1 +#define PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_MASK 0x00001FFEU -/*CRS SW Visibility. Indicates RC can return CRS to SW. Transferred to the Root Capabilities register.; EP=0x0000; RP=0x0000*/ +/* +* CRS SW Visibility. Indicates RC can return CRS to SW. Transferred to the + * Root Capabilities register.; EP=0x0000; RP=0x0000 +*/ #undef PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_DEFVAL #undef PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_SHIFT #undef PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_MASK -#define PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_DEFVAL 0x00000000 -#define PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_SHIFT 5 -#define PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_MASK 0x00000020U +#define PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_DEFVAL 0x00000000 +#define PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_SHIFT 5 +#define PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_MASK 0x00000020U -/*Indicates that the MSIX structures exists. If this is FALSE, then the MSIX structure cannot be accessed via either the link o - the management port.; EP=0x0001; RP=0x0000*/ +/* +* Indicates that the MSIX structures exists. If this is FALSE, then the MS + * IX structure cannot be accessed via either the link or the management po + * rt.; EP=0x0001; RP=0x0000 +*/ #undef PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_DEFVAL #undef PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_SHIFT #undef PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_MASK -#define PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_DEFVAL 0x00000100 -#define PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_SHIFT 8 -#define PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_MASK 0x00000100U +#define PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_DEFVAL 0x00000100 +#define PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_SHIFT 8 +#define PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_MASK 0x00000100U -/*MSI-X Table Size. This value is transferred to the MSI-X Message Control[10:0] field. Set to 0 if MSI-X is not enabled. Note - hat the core does not implement the table; that must be implemented in user logic.; EP=0x0003; RP=0x0000*/ +/* +* MSI-X Table Size. This value is transferred to the MSI-X Message Control + * [10:0] field. Set to 0 if MSI-X is not enabled. Note that the core does + * not implement the table; that must be implemented in user logic.; EP=0x0 + * 003; RP=0x0000 +*/ #undef PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_DEFVAL #undef PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_SHIFT #undef PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_MASK -#define PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_DEFVAL -#define PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_SHIFT 0 -#define PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_MASK 0x000007FFU +#define PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_DEFVAL +#define PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_SHIFT 0 +#define PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_MASK 0x000007FFU -/*MSI-X Table Offset. This value is transferred to the MSI-X Table Offset field. Set to 0 if MSI-X is not enabled.; EP=0x0001; - P=0x0000*/ +/* +* MSI-X Table Offset. This value is transferred to the MSI-X Table Offset + * field. Set to 0 if MSI-X is not enabled.; EP=0x0001; RP=0x0000 +*/ #undef PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_DEFVAL #undef PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_SHIFT #undef PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_MASK -#define PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_DEFVAL -#define PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_SHIFT 0 -#define PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_MASK 0x0000FFFFU +#define PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_DEFVAL +#define PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_SHIFT 0 +#define PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_MASK 0x0000FFFFU -/*MSI-X Table Offset. This value is transferred to the MSI-X Table Offset field. Set to 0 if MSI-X is not enabled.; EP=0x0000; - P=0x0000*/ +/* +* MSI-X Table Offset. This value is transferred to the MSI-X Table Offset + * field. Set to 0 if MSI-X is not enabled.; EP=0x0000; RP=0x0000 +*/ #undef PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_DEFVAL #undef PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_SHIFT #undef PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_MASK -#define PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_DEFVAL -#define PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_SHIFT 0 -#define PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_MASK 0x00001FFFU +#define PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_DEFVAL +#define PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_SHIFT 0 +#define PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_MASK 0x00001FFFU -/*MSI-X Pending Bit Array Offset This value is transferred to the MSI-X PBA Offset field. Set to 0 if MSI-X is not enabled.; EP - 0x0001; RP=0x0000*/ +/* +* MSI-X Pending Bit Array Offset This value is transferred to the MSI-X PB + * A Offset field. Set to 0 if MSI-X is not enabled.; EP=0x0001; RP=0x0000 +*/ #undef PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_DEFVAL #undef PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_SHIFT #undef PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_MASK -#define PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_DEFVAL -#define PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_SHIFT 0 -#define PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_MASK 0x0000FFFFU +#define PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_DEFVAL +#define PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_SHIFT 0 +#define PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_MASK 0x0000FFFFU -/*MSI-X Pending Bit Array Offset This value is transferred to the MSI-X PBA Offset field. Set to 0 if MSI-X is not enabled.; EP - 0x1000; RP=0x0000*/ +/* +* MSI-X Pending Bit Array Offset This value is transferred to the MSI-X PB + * A Offset field. Set to 0 if MSI-X is not enabled.; EP=0x1000; RP=0x0000 +*/ #undef PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_DEFVAL #undef PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_SHIFT #undef PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_MASK -#define PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_DEFVAL 0x00008000 -#define PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_SHIFT 3 -#define PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_MASK 0x0000FFF8U +#define PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_DEFVAL 0x00008000 +#define PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_SHIFT 3 +#define PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_MASK 0x0000FFF8U -/*DT837748 Enable*/ +/* +* DT837748 Enable +*/ #undef PCIE_ATTRIB_CB_CB1_DEFVAL #undef PCIE_ATTRIB_CB_CB1_SHIFT #undef PCIE_ATTRIB_CB_CB1_MASK -#define PCIE_ATTRIB_CB_CB1_DEFVAL 0x00000001 -#define PCIE_ATTRIB_CB_CB1_SHIFT 1 -#define PCIE_ATTRIB_CB_CB1_MASK 0x00000002U +#define PCIE_ATTRIB_CB_CB1_DEFVAL 0x00000001 +#define PCIE_ATTRIB_CB_CB1_SHIFT 1 +#define PCIE_ATTRIB_CB_CB1_MASK 0x00000002U -/*Active State PM Support. Indicates the level of active state power management supported by the selected PCI Express Link, enc - ded as follows: 0 Reserved, 1 L0s entry supported, 2 Reserved, 3 L0s and L1 entry supported.; EP=0x0001; RP=0x0001*/ +/* +* Active State PM Support. Indicates the level of active state power manag + * ement supported by the selected PCI Express Link, encoded as follows: 0 + * Reserved, 1 L0s entry supported, 2 Reserved, 3 L0s and L1 entry supporte + * d.; EP=0x0001; RP=0x0001 +*/ #undef PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_DEFVAL #undef PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_SHIFT #undef PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_MASK -#define PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_DEFVAL 0x00001FFD -#define PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_SHIFT 12 -#define PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_MASK 0x00003000U +#define PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_DEFVAL 0x00001FFD +#define PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_SHIFT 12 +#define PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_MASK 0x00003000U -/*PCIE control block level reset*/ +/* +* PCIE control block level reset +*/ #undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL #undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT #undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK -#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL 0x000F9FFE -#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT 17 -#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK 0x00020000U +#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT 17 +#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK 0x00020000U -/*Status Read value of PLL Lock*/ +/* +* Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW] +*/ +#undef GPIO_MASK_DATA_1_LSW_MASK_1_LSW_DEFVAL +#undef GPIO_MASK_DATA_1_LSW_MASK_1_LSW_SHIFT +#undef GPIO_MASK_DATA_1_LSW_MASK_1_LSW_MASK +#define GPIO_MASK_DATA_1_LSW_MASK_1_LSW_DEFVAL 0x00000000 +#define GPIO_MASK_DATA_1_LSW_MASK_1_LSW_SHIFT 16 +#define GPIO_MASK_DATA_1_LSW_MASK_1_LSW_MASK 0xFFFF0000U + +/* +* Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW] +*/ +#undef GPIO_MASK_DATA_1_LSW_DATA_1_LSW_DEFVAL +#undef GPIO_MASK_DATA_1_LSW_DATA_1_LSW_SHIFT +#undef GPIO_MASK_DATA_1_LSW_DATA_1_LSW_MASK +#define GPIO_MASK_DATA_1_LSW_DATA_1_LSW_DEFVAL 0x00000000 +#define GPIO_MASK_DATA_1_LSW_DATA_1_LSW_SHIFT 0 +#define GPIO_MASK_DATA_1_LSW_DATA_1_LSW_MASK 0x0000FFFFU + +/* +* Status Read value of PLL Lock +*/ #undef SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL #undef SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT #undef SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK -#define SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL 0x00000001 -#define SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT 4 -#define SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK 0x00000010U +#define SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL 0x00000001 +#define SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT 4 +#define SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK 0x00000010U #define SERDES_L0_PLL_STATUS_READ_1_OFFSET 0XFD4023E4 -/*Status Read value of PLL Lock*/ +/* +* Status Read value of PLL Lock +*/ #undef SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL #undef SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT #undef SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK -#define SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL 0x00000001 -#define SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT 4 -#define SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK 0x00000010U +#define SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL 0x00000001 +#define SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT 4 +#define SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK 0x00000010U #define SERDES_L1_PLL_STATUS_READ_1_OFFSET 0XFD4063E4 -/*Status Read value of PLL Lock*/ +/* +* Status Read value of PLL Lock +*/ #undef SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL #undef SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT #undef SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK -#define SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL 0x00000001 -#define SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT 4 -#define SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK 0x00000010U +#define SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL 0x00000001 +#define SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT 4 +#define SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK 0x00000010U #define SERDES_L2_PLL_STATUS_READ_1_OFFSET 0XFD40A3E4 -/*Status Read value of PLL Lock*/ +/* +* Status Read value of PLL Lock +*/ #undef SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL #undef SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT #undef SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK -#define SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL 0x00000001 -#define SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT 4 -#define SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK 0x00000010U +#define SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL 0x00000001 +#define SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT 4 +#define SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK 0x00000010U #define SERDES_L3_PLL_STATUS_READ_1_OFFSET 0XFD40E3E4 -/*CIBGMN: COMINIT Burst Gap Minimum.*/ +/* +* CIBGMN: COMINIT Burst Gap Minimum. +*/ #undef SATA_AHCI_VENDOR_PP2C_CIBGMN_DEFVAL #undef SATA_AHCI_VENDOR_PP2C_CIBGMN_SHIFT #undef SATA_AHCI_VENDOR_PP2C_CIBGMN_MASK -#define SATA_AHCI_VENDOR_PP2C_CIBGMN_DEFVAL 0x28184D1B -#define SATA_AHCI_VENDOR_PP2C_CIBGMN_SHIFT 0 -#define SATA_AHCI_VENDOR_PP2C_CIBGMN_MASK 0x000000FFU +#define SATA_AHCI_VENDOR_PP2C_CIBGMN_DEFVAL 0x28184D1B +#define SATA_AHCI_VENDOR_PP2C_CIBGMN_SHIFT 0 +#define SATA_AHCI_VENDOR_PP2C_CIBGMN_MASK 0x000000FFU -/*CIBGMX: COMINIT Burst Gap Maximum.*/ +/* +* CIBGMX: COMINIT Burst Gap Maximum. +*/ #undef SATA_AHCI_VENDOR_PP2C_CIBGMX_DEFVAL #undef SATA_AHCI_VENDOR_PP2C_CIBGMX_SHIFT #undef SATA_AHCI_VENDOR_PP2C_CIBGMX_MASK -#define SATA_AHCI_VENDOR_PP2C_CIBGMX_DEFVAL 0x28184D1B -#define SATA_AHCI_VENDOR_PP2C_CIBGMX_SHIFT 8 -#define SATA_AHCI_VENDOR_PP2C_CIBGMX_MASK 0x0000FF00U +#define SATA_AHCI_VENDOR_PP2C_CIBGMX_DEFVAL 0x28184D1B +#define SATA_AHCI_VENDOR_PP2C_CIBGMX_SHIFT 8 +#define SATA_AHCI_VENDOR_PP2C_CIBGMX_MASK 0x0000FF00U -/*CIBGN: COMINIT Burst Gap Nominal.*/ +/* +* CIBGN: COMINIT Burst Gap Nominal. +*/ #undef SATA_AHCI_VENDOR_PP2C_CIBGN_DEFVAL #undef SATA_AHCI_VENDOR_PP2C_CIBGN_SHIFT #undef SATA_AHCI_VENDOR_PP2C_CIBGN_MASK -#define SATA_AHCI_VENDOR_PP2C_CIBGN_DEFVAL 0x28184D1B -#define SATA_AHCI_VENDOR_PP2C_CIBGN_SHIFT 16 -#define SATA_AHCI_VENDOR_PP2C_CIBGN_MASK 0x00FF0000U +#define SATA_AHCI_VENDOR_PP2C_CIBGN_DEFVAL 0x28184D1B +#define SATA_AHCI_VENDOR_PP2C_CIBGN_SHIFT 16 +#define SATA_AHCI_VENDOR_PP2C_CIBGN_MASK 0x00FF0000U -/*CINMP: COMINIT Negate Minimum Period.*/ +/* +* CINMP: COMINIT Negate Minimum Period. +*/ #undef SATA_AHCI_VENDOR_PP2C_CINMP_DEFVAL #undef SATA_AHCI_VENDOR_PP2C_CINMP_SHIFT #undef SATA_AHCI_VENDOR_PP2C_CINMP_MASK -#define SATA_AHCI_VENDOR_PP2C_CINMP_DEFVAL 0x28184D1B -#define SATA_AHCI_VENDOR_PP2C_CINMP_SHIFT 24 -#define SATA_AHCI_VENDOR_PP2C_CINMP_MASK 0xFF000000U +#define SATA_AHCI_VENDOR_PP2C_CINMP_DEFVAL 0x28184D1B +#define SATA_AHCI_VENDOR_PP2C_CINMP_SHIFT 24 +#define SATA_AHCI_VENDOR_PP2C_CINMP_MASK 0xFF000000U -/*CWBGMN: COMWAKE Burst Gap Minimum.*/ +/* +* CWBGMN: COMWAKE Burst Gap Minimum. +*/ #undef SATA_AHCI_VENDOR_PP3C_CWBGMN_DEFVAL #undef SATA_AHCI_VENDOR_PP3C_CWBGMN_SHIFT #undef SATA_AHCI_VENDOR_PP3C_CWBGMN_MASK -#define SATA_AHCI_VENDOR_PP3C_CWBGMN_DEFVAL 0x0E081906 -#define SATA_AHCI_VENDOR_PP3C_CWBGMN_SHIFT 0 -#define SATA_AHCI_VENDOR_PP3C_CWBGMN_MASK 0x000000FFU +#define SATA_AHCI_VENDOR_PP3C_CWBGMN_DEFVAL 0x0E081906 +#define SATA_AHCI_VENDOR_PP3C_CWBGMN_SHIFT 0 +#define SATA_AHCI_VENDOR_PP3C_CWBGMN_MASK 0x000000FFU -/*CWBGMX: COMWAKE Burst Gap Maximum.*/ +/* +* CWBGMX: COMWAKE Burst Gap Maximum. +*/ #undef SATA_AHCI_VENDOR_PP3C_CWBGMX_DEFVAL #undef SATA_AHCI_VENDOR_PP3C_CWBGMX_SHIFT #undef SATA_AHCI_VENDOR_PP3C_CWBGMX_MASK -#define SATA_AHCI_VENDOR_PP3C_CWBGMX_DEFVAL 0x0E081906 -#define SATA_AHCI_VENDOR_PP3C_CWBGMX_SHIFT 8 -#define SATA_AHCI_VENDOR_PP3C_CWBGMX_MASK 0x0000FF00U +#define SATA_AHCI_VENDOR_PP3C_CWBGMX_DEFVAL 0x0E081906 +#define SATA_AHCI_VENDOR_PP3C_CWBGMX_SHIFT 8 +#define SATA_AHCI_VENDOR_PP3C_CWBGMX_MASK 0x0000FF00U -/*CWBGN: COMWAKE Burst Gap Nominal.*/ +/* +* CWBGN: COMWAKE Burst Gap Nominal. +*/ #undef SATA_AHCI_VENDOR_PP3C_CWBGN_DEFVAL #undef SATA_AHCI_VENDOR_PP3C_CWBGN_SHIFT #undef SATA_AHCI_VENDOR_PP3C_CWBGN_MASK -#define SATA_AHCI_VENDOR_PP3C_CWBGN_DEFVAL 0x0E081906 -#define SATA_AHCI_VENDOR_PP3C_CWBGN_SHIFT 16 -#define SATA_AHCI_VENDOR_PP3C_CWBGN_MASK 0x00FF0000U +#define SATA_AHCI_VENDOR_PP3C_CWBGN_DEFVAL 0x0E081906 +#define SATA_AHCI_VENDOR_PP3C_CWBGN_SHIFT 16 +#define SATA_AHCI_VENDOR_PP3C_CWBGN_MASK 0x00FF0000U -/*CWNMP: COMWAKE Negate Minimum Period.*/ +/* +* CWNMP: COMWAKE Negate Minimum Period. +*/ #undef SATA_AHCI_VENDOR_PP3C_CWNMP_DEFVAL #undef SATA_AHCI_VENDOR_PP3C_CWNMP_SHIFT #undef SATA_AHCI_VENDOR_PP3C_CWNMP_MASK -#define SATA_AHCI_VENDOR_PP3C_CWNMP_DEFVAL 0x0E081906 -#define SATA_AHCI_VENDOR_PP3C_CWNMP_SHIFT 24 -#define SATA_AHCI_VENDOR_PP3C_CWNMP_MASK 0xFF000000U +#define SATA_AHCI_VENDOR_PP3C_CWNMP_DEFVAL 0x0E081906 +#define SATA_AHCI_VENDOR_PP3C_CWNMP_SHIFT 24 +#define SATA_AHCI_VENDOR_PP3C_CWNMP_MASK 0xFF000000U -/*BMX: COM Burst Maximum.*/ +/* +* BMX: COM Burst Maximum. +*/ #undef SATA_AHCI_VENDOR_PP4C_BMX_DEFVAL #undef SATA_AHCI_VENDOR_PP4C_BMX_SHIFT #undef SATA_AHCI_VENDOR_PP4C_BMX_MASK -#define SATA_AHCI_VENDOR_PP4C_BMX_DEFVAL 0x064A0813 -#define SATA_AHCI_VENDOR_PP4C_BMX_SHIFT 0 -#define SATA_AHCI_VENDOR_PP4C_BMX_MASK 0x000000FFU +#define SATA_AHCI_VENDOR_PP4C_BMX_DEFVAL 0x064A0813 +#define SATA_AHCI_VENDOR_PP4C_BMX_SHIFT 0 +#define SATA_AHCI_VENDOR_PP4C_BMX_MASK 0x000000FFU -/*BNM: COM Burst Nominal.*/ +/* +* BNM: COM Burst Nominal. +*/ #undef SATA_AHCI_VENDOR_PP4C_BNM_DEFVAL #undef SATA_AHCI_VENDOR_PP4C_BNM_SHIFT #undef SATA_AHCI_VENDOR_PP4C_BNM_MASK -#define SATA_AHCI_VENDOR_PP4C_BNM_DEFVAL 0x064A0813 -#define SATA_AHCI_VENDOR_PP4C_BNM_SHIFT 8 -#define SATA_AHCI_VENDOR_PP4C_BNM_MASK 0x0000FF00U +#define SATA_AHCI_VENDOR_PP4C_BNM_DEFVAL 0x064A0813 +#define SATA_AHCI_VENDOR_PP4C_BNM_SHIFT 8 +#define SATA_AHCI_VENDOR_PP4C_BNM_MASK 0x0000FF00U -/*SFD: Signal Failure Detection, if the signal detection de-asserts for a time greater than this then the OOB detector will det - rmine this is a line idle and cause the PhyInit state machine to exit the Phy Ready State. A value of zero disables the Signa - Failure Detector. The value is based on the OOB Detector Clock typically (PMCLK Clock Period) * SFD giving a nominal time of - 500ns based on a 150MHz PMCLK.*/ +/* +* SFD: Signal Failure Detection, if the signal detection de-asserts for a + * time greater than this then the OOB detector will determine this is a li + * ne idle and cause the PhyInit state machine to exit the Phy Ready State. + * A value of zero disables the Signal Failure Detector. The value is base + * d on the OOB Detector Clock typically (PMCLK Clock Period) * SFD giving + * a nominal time of 500ns based on a 150MHz PMCLK. +*/ #undef SATA_AHCI_VENDOR_PP4C_SFD_DEFVAL #undef SATA_AHCI_VENDOR_PP4C_SFD_SHIFT #undef SATA_AHCI_VENDOR_PP4C_SFD_MASK -#define SATA_AHCI_VENDOR_PP4C_SFD_DEFVAL 0x064A0813 -#define SATA_AHCI_VENDOR_PP4C_SFD_SHIFT 16 -#define SATA_AHCI_VENDOR_PP4C_SFD_MASK 0x00FF0000U +#define SATA_AHCI_VENDOR_PP4C_SFD_DEFVAL 0x064A0813 +#define SATA_AHCI_VENDOR_PP4C_SFD_SHIFT 16 +#define SATA_AHCI_VENDOR_PP4C_SFD_MASK 0x00FF0000U -/*PTST: Partial to Slumber timer value, specific delay the controller should apply while in partial before entering slumber. Th - value is bases on the system clock divided by 128, total delay = (Sys Clock Period) * PTST * 128*/ +/* +* PTST: Partial to Slumber timer value, specific delay the controller shou + * ld apply while in partial before entering slumber. The value is bases on + * the system clock divided by 128, total delay = (Sys Clock Period) * PTS + * T * 128 +*/ #undef SATA_AHCI_VENDOR_PP4C_PTST_DEFVAL #undef SATA_AHCI_VENDOR_PP4C_PTST_SHIFT #undef SATA_AHCI_VENDOR_PP4C_PTST_MASK -#define SATA_AHCI_VENDOR_PP4C_PTST_DEFVAL 0x064A0813 -#define SATA_AHCI_VENDOR_PP4C_PTST_SHIFT 24 -#define SATA_AHCI_VENDOR_PP4C_PTST_MASK 0xFF000000U +#define SATA_AHCI_VENDOR_PP4C_PTST_DEFVAL 0x064A0813 +#define SATA_AHCI_VENDOR_PP4C_PTST_SHIFT 24 +#define SATA_AHCI_VENDOR_PP4C_PTST_MASK 0xFF000000U -/*RIT: Retry Interval Timer. The calculated value divided by two, the lower digit of precision is not needed.*/ +/* +* RIT: Retry Interval Timer. The calculated value divided by two, the lowe + * r digit of precision is not needed. +*/ #undef SATA_AHCI_VENDOR_PP5C_RIT_DEFVAL #undef SATA_AHCI_VENDOR_PP5C_RIT_SHIFT #undef SATA_AHCI_VENDOR_PP5C_RIT_MASK -#define SATA_AHCI_VENDOR_PP5C_RIT_DEFVAL 0x3FFC96A4 -#define SATA_AHCI_VENDOR_PP5C_RIT_SHIFT 0 -#define SATA_AHCI_VENDOR_PP5C_RIT_MASK 0x000FFFFFU +#define SATA_AHCI_VENDOR_PP5C_RIT_DEFVAL 0x3FFC96A4 +#define SATA_AHCI_VENDOR_PP5C_RIT_SHIFT 0 +#define SATA_AHCI_VENDOR_PP5C_RIT_MASK 0x000FFFFFU -/*RCT: Rate Change Timer, a value based on the 54.2us for which a SATA device will transmit at a fixed rate ALIGNp after OOB ha - completed, for a fast SERDES it is suggested that this value be 54.2us / 4*/ +/* +* RCT: Rate Change Timer, a value based on the 54.2us for which a SATA dev + * ice will transmit at a fixed rate ALIGNp after OOB has completed, for a + * fast SERDES it is suggested that this value be 54.2us / 4 +*/ #undef SATA_AHCI_VENDOR_PP5C_RCT_DEFVAL #undef SATA_AHCI_VENDOR_PP5C_RCT_SHIFT #undef SATA_AHCI_VENDOR_PP5C_RCT_MASK -#define SATA_AHCI_VENDOR_PP5C_RCT_DEFVAL 0x3FFC96A4 -#define SATA_AHCI_VENDOR_PP5C_RCT_SHIFT 20 -#define SATA_AHCI_VENDOR_PP5C_RCT_MASK 0xFFF00000U +#define SATA_AHCI_VENDOR_PP5C_RCT_DEFVAL 0x3FFC96A4 +#define SATA_AHCI_VENDOR_PP5C_RCT_SHIFT 20 +#define SATA_AHCI_VENDOR_PP5C_RCT_MASK 0xFFF00000U #undef CRL_APB_RST_LPD_TOP_OFFSET #define CRL_APB_RST_LPD_TOP_OFFSET 0XFF5E023C #undef CRL_APB_RST_LPD_IOU0_OFFSET @@ -27671,123 +36135,252 @@ #undef CRF_APB_RST_FPD_TOP_OFFSET #define CRF_APB_RST_FPD_TOP_OFFSET 0XFD1A0100 -/*USB 0 reset for control registers*/ +/* +* USB 0 reset for control registers +*/ #undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL #undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT #undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK -#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL 0x00188FDF -#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT 10 -#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK 0x00000400U +#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT 10 +#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK 0x00000400U -/*USB 0 sleep circuit reset*/ +/* +* USB 0 sleep circuit reset +*/ #undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL #undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT #undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK -#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL 0x00188FDF -#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT 8 -#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK 0x00000100U +#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT 8 +#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK 0x00000100U -/*USB 0 reset*/ +/* +* USB 0 reset +*/ #undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL #undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT #undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK -#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL 0x00188FDF -#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT 6 -#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK 0x00000040U +#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT 6 +#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK 0x00000040U -/*GEM 3 reset*/ +/* +* GEM 3 reset +*/ #undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL #undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT #undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK -#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL 0x0000000F -#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT 3 -#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK 0x00000008U +#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL 0x0000000F +#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT 3 +#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK 0x00000008U -/*Sata block level reset*/ +/* +* Sata block level reset +*/ #undef CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL #undef CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT #undef CRF_APB_RST_FPD_TOP_SATA_RESET_MASK -#define CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL 0x000F9FFE -#define CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT 1 -#define CRF_APB_RST_FPD_TOP_SATA_RESET_MASK 0x00000002U +#define CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT 1 +#define CRF_APB_RST_FPD_TOP_SATA_RESET_MASK 0x00000002U -/*PCIE config reset*/ +/* +* PCIE config reset +*/ #undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL #undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT #undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK -#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL 0x000F9FFE -#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT 19 -#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK 0x00080000U +#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT 19 +#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK 0x00080000U -/*PCIE control block level reset*/ +/* +* PCIE control block level reset +*/ #undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL #undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT #undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK -#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL 0x000F9FFE -#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT 17 -#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK 0x00020000U +#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT 17 +#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK 0x00020000U -/*PCIE bridge block level reset (AXI interface)*/ +/* +* PCIE bridge block level reset (AXI interface) +*/ #undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL #undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT #undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK -#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL 0x000F9FFE -#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT 18 -#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK 0x00040000U +#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT 18 +#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK 0x00040000U -/*Two bits per lane. When set to 11, moves the GT to power down mode. When set to 00, GT will be in active state. bits [1:0] - - ane0 Bits [3:2] - lane 1*/ +/* +* Two bits per lane. When set to 11, moves the GT to power down mode. When + * set to 00, GT will be in active state. bits [1:0] - lane0 Bits [3:2] - + * lane 1 +*/ #undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_DEFVAL #undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT #undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK -#define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_DEFVAL 0x00000000 -#define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT 0 -#define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK 0x0000000FU +#define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_DEFVAL 0x00000000 +#define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT 0 +#define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK 0x0000000FU -/*Set to '1' to hold the GT in reset. Clear to release.*/ +/* +* Set to '1' to hold the GT in reset. Clear to release. +*/ #undef DP_DP_PHY_RESET_GT_RESET_DEFVAL #undef DP_DP_PHY_RESET_GT_RESET_SHIFT #undef DP_DP_PHY_RESET_GT_RESET_MASK -#define DP_DP_PHY_RESET_GT_RESET_DEFVAL 0x00010003 -#define DP_DP_PHY_RESET_GT_RESET_SHIFT 1 -#define DP_DP_PHY_RESET_GT_RESET_MASK 0x00000002U +#define DP_DP_PHY_RESET_GT_RESET_DEFVAL 0x00010003 +#define DP_DP_PHY_RESET_GT_RESET_SHIFT 1 +#define DP_DP_PHY_RESET_GT_RESET_MASK 0x00000002U -/*Display Port block level reset (includes DPDMA)*/ +/* +* Display Port block level reset (includes DPDMA) +*/ #undef CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL #undef CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT #undef CRF_APB_RST_FPD_TOP_DP_RESET_MASK -#define CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL 0x000F9FFE -#define CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT 16 -#define CRF_APB_RST_FPD_TOP_DP_RESET_MASK 0x00010000U +#define CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT 16 +#define CRF_APB_RST_FPD_TOP_DP_RESET_MASK 0x00010000U #undef PMU_GLOBAL_REQ_PWRUP_INT_EN_OFFSET #define PMU_GLOBAL_REQ_PWRUP_INT_EN_OFFSET 0XFFD80118 #undef PMU_GLOBAL_REQ_PWRUP_TRIG_OFFSET #define PMU_GLOBAL_REQ_PWRUP_TRIG_OFFSET 0XFFD80120 -/*Power-up Request Interrupt Enable for PL*/ +/* +* Power-up Request Interrupt Enable for PL +*/ #undef PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_DEFVAL #undef PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_SHIFT #undef PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_MASK -#define PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_DEFVAL 0x00000000 -#define PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_SHIFT 23 -#define PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_MASK 0x00800000U +#define PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_DEFVAL 0x00000000 +#define PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_SHIFT 23 +#define PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_MASK 0x00800000U -/*Power-up Request Trigger for PL*/ +/* +* Power-up Request Trigger for PL +*/ #undef PMU_GLOBAL_REQ_PWRUP_TRIG_PL_DEFVAL #undef PMU_GLOBAL_REQ_PWRUP_TRIG_PL_SHIFT #undef PMU_GLOBAL_REQ_PWRUP_TRIG_PL_MASK -#define PMU_GLOBAL_REQ_PWRUP_TRIG_PL_DEFVAL 0x00000000 -#define PMU_GLOBAL_REQ_PWRUP_TRIG_PL_SHIFT 23 -#define PMU_GLOBAL_REQ_PWRUP_TRIG_PL_MASK 0x00800000U +#define PMU_GLOBAL_REQ_PWRUP_TRIG_PL_DEFVAL 0x00000000 +#define PMU_GLOBAL_REQ_PWRUP_TRIG_PL_SHIFT 23 +#define PMU_GLOBAL_REQ_PWRUP_TRIG_PL_MASK 0x00800000U -/*Power-up Request Status for PL*/ +/* +* Power-up Request Status for PL +*/ #undef PMU_GLOBAL_REQ_PWRUP_STATUS_PL_DEFVAL #undef PMU_GLOBAL_REQ_PWRUP_STATUS_PL_SHIFT #undef PMU_GLOBAL_REQ_PWRUP_STATUS_PL_MASK -#define PMU_GLOBAL_REQ_PWRUP_STATUS_PL_DEFVAL 0x00000000 -#define PMU_GLOBAL_REQ_PWRUP_STATUS_PL_SHIFT 23 -#define PMU_GLOBAL_REQ_PWRUP_STATUS_PL_MASK 0x00800000U +#define PMU_GLOBAL_REQ_PWRUP_STATUS_PL_DEFVAL 0x00000000 +#define PMU_GLOBAL_REQ_PWRUP_STATUS_PL_SHIFT 23 +#define PMU_GLOBAL_REQ_PWRUP_STATUS_PL_MASK 0x00800000U #define PMU_GLOBAL_REQ_PWRUP_STATUS_OFFSET 0XFFD80110 +#undef CRF_APB_RST_FPD_TOP_OFFSET +#define CRF_APB_RST_FPD_TOP_OFFSET 0XFD1A0100 +#undef CRL_APB_RST_LPD_TOP_OFFSET +#define CRL_APB_RST_LPD_TOP_OFFSET 0XFF5E023C +#undef FPD_SLCR_AFI_FS_OFFSET +#define FPD_SLCR_AFI_FS_OFFSET 0XFD615000 + +/* +* AF_FM0 block level reset +*/ +#undef CRF_APB_RST_FPD_TOP_AFI_FM0_RESET_DEFVAL +#undef CRF_APB_RST_FPD_TOP_AFI_FM0_RESET_SHIFT +#undef CRF_APB_RST_FPD_TOP_AFI_FM0_RESET_MASK +#define CRF_APB_RST_FPD_TOP_AFI_FM0_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_AFI_FM0_RESET_SHIFT 7 +#define CRF_APB_RST_FPD_TOP_AFI_FM0_RESET_MASK 0x00000080U + +/* +* AF_FM1 block level reset +*/ +#undef CRF_APB_RST_FPD_TOP_AFI_FM1_RESET_DEFVAL +#undef CRF_APB_RST_FPD_TOP_AFI_FM1_RESET_SHIFT +#undef CRF_APB_RST_FPD_TOP_AFI_FM1_RESET_MASK +#define CRF_APB_RST_FPD_TOP_AFI_FM1_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_AFI_FM1_RESET_SHIFT 8 +#define CRF_APB_RST_FPD_TOP_AFI_FM1_RESET_MASK 0x00000100U + +/* +* AF_FM2 block level reset +*/ +#undef CRF_APB_RST_FPD_TOP_AFI_FM2_RESET_DEFVAL +#undef CRF_APB_RST_FPD_TOP_AFI_FM2_RESET_SHIFT +#undef CRF_APB_RST_FPD_TOP_AFI_FM2_RESET_MASK +#define CRF_APB_RST_FPD_TOP_AFI_FM2_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_AFI_FM2_RESET_SHIFT 9 +#define CRF_APB_RST_FPD_TOP_AFI_FM2_RESET_MASK 0x00000200U + +/* +* AF_FM3 block level reset +*/ +#undef CRF_APB_RST_FPD_TOP_AFI_FM3_RESET_DEFVAL +#undef CRF_APB_RST_FPD_TOP_AFI_FM3_RESET_SHIFT +#undef CRF_APB_RST_FPD_TOP_AFI_FM3_RESET_MASK +#define CRF_APB_RST_FPD_TOP_AFI_FM3_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_AFI_FM3_RESET_SHIFT 10 +#define CRF_APB_RST_FPD_TOP_AFI_FM3_RESET_MASK 0x00000400U + +/* +* AF_FM4 block level reset +*/ +#undef CRF_APB_RST_FPD_TOP_AFI_FM4_RESET_DEFVAL +#undef CRF_APB_RST_FPD_TOP_AFI_FM4_RESET_SHIFT +#undef CRF_APB_RST_FPD_TOP_AFI_FM4_RESET_MASK +#define CRF_APB_RST_FPD_TOP_AFI_FM4_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_AFI_FM4_RESET_SHIFT 11 +#define CRF_APB_RST_FPD_TOP_AFI_FM4_RESET_MASK 0x00000800U + +/* +* AF_FM5 block level reset +*/ +#undef CRF_APB_RST_FPD_TOP_AFI_FM5_RESET_DEFVAL +#undef CRF_APB_RST_FPD_TOP_AFI_FM5_RESET_SHIFT +#undef CRF_APB_RST_FPD_TOP_AFI_FM5_RESET_MASK +#define CRF_APB_RST_FPD_TOP_AFI_FM5_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_AFI_FM5_RESET_SHIFT 12 +#define CRF_APB_RST_FPD_TOP_AFI_FM5_RESET_MASK 0x00001000U + +/* +* AFI FM 6 +*/ +#undef CRL_APB_RST_LPD_TOP_AFI_FM6_RESET_DEFVAL +#undef CRL_APB_RST_LPD_TOP_AFI_FM6_RESET_SHIFT +#undef CRL_APB_RST_LPD_TOP_AFI_FM6_RESET_MASK +#define CRL_APB_RST_LPD_TOP_AFI_FM6_RESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_AFI_FM6_RESET_SHIFT 19 +#define CRL_APB_RST_LPD_TOP_AFI_FM6_RESET_MASK 0x00080000U + +/* +* Select the 32/64/128-bit data width selection for the Slave 0 00: 32-bit + * AXI data width (default) 01: 64-bit AXI data width 10: 128-bit AXI data + * width 11: reserved +*/ +#undef FPD_SLCR_AFI_FS_DW_SS0_SEL_DEFVAL +#undef FPD_SLCR_AFI_FS_DW_SS0_SEL_SHIFT +#undef FPD_SLCR_AFI_FS_DW_SS0_SEL_MASK +#define FPD_SLCR_AFI_FS_DW_SS0_SEL_DEFVAL 0x00000A00 +#define FPD_SLCR_AFI_FS_DW_SS0_SEL_SHIFT 8 +#define FPD_SLCR_AFI_FS_DW_SS0_SEL_MASK 0x00000300U + +/* +* Select the 32/64/128-bit data width selection for the Slave 1 00: 32-bit + * AXI data width (default) 01: 64-bit AXI data width 10: 128-bit AXI data + * width 11: reserved +*/ +#undef FPD_SLCR_AFI_FS_DW_SS1_SEL_DEFVAL +#undef FPD_SLCR_AFI_FS_DW_SS1_SEL_SHIFT +#undef FPD_SLCR_AFI_FS_DW_SS1_SEL_MASK +#define FPD_SLCR_AFI_FS_DW_SS1_SEL_DEFVAL 0x00000A00 +#define FPD_SLCR_AFI_FS_DW_SS1_SEL_SHIFT 10 +#define FPD_SLCR_AFI_FS_DW_SS1_SEL_MASK 0x00000C00U #undef GPIO_MASK_DATA_5_MSW_OFFSET #define GPIO_MASK_DATA_5_MSW_OFFSET 0XFF0A002C #undef GPIO_DIRM_5_OFFSET @@ -27801,53 +36394,65 @@ #undef GPIO_DATA_5_OFFSET #define GPIO_DATA_5_OFFSET 0XFF0A0054 -/*Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW]*/ +/* +* Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW] +*/ #undef GPIO_MASK_DATA_5_MSW_MASK_5_MSW_DEFVAL #undef GPIO_MASK_DATA_5_MSW_MASK_5_MSW_SHIFT #undef GPIO_MASK_DATA_5_MSW_MASK_5_MSW_MASK -#define GPIO_MASK_DATA_5_MSW_MASK_5_MSW_DEFVAL 0x00000000 -#define GPIO_MASK_DATA_5_MSW_MASK_5_MSW_SHIFT 16 -#define GPIO_MASK_DATA_5_MSW_MASK_5_MSW_MASK 0xFFFF0000U +#define GPIO_MASK_DATA_5_MSW_MASK_5_MSW_DEFVAL 0x00000000 +#define GPIO_MASK_DATA_5_MSW_MASK_5_MSW_SHIFT 16 +#define GPIO_MASK_DATA_5_MSW_MASK_5_MSW_MASK 0xFFFF0000U -/*Operation is the same as DIRM_0[DIRECTION_0]*/ +/* +* Operation is the same as DIRM_0[DIRECTION_0] +*/ #undef GPIO_DIRM_5_DIRECTION_5_DEFVAL #undef GPIO_DIRM_5_DIRECTION_5_SHIFT #undef GPIO_DIRM_5_DIRECTION_5_MASK -#define GPIO_DIRM_5_DIRECTION_5_DEFVAL -#define GPIO_DIRM_5_DIRECTION_5_SHIFT 0 -#define GPIO_DIRM_5_DIRECTION_5_MASK 0xFFFFFFFFU +#define GPIO_DIRM_5_DIRECTION_5_DEFVAL +#define GPIO_DIRM_5_DIRECTION_5_SHIFT 0 +#define GPIO_DIRM_5_DIRECTION_5_MASK 0xFFFFFFFFU -/*Operation is the same as OEN_0[OP_ENABLE_0]*/ +/* +* Operation is the same as OEN_0[OP_ENABLE_0] +*/ #undef GPIO_OEN_5_OP_ENABLE_5_DEFVAL #undef GPIO_OEN_5_OP_ENABLE_5_SHIFT #undef GPIO_OEN_5_OP_ENABLE_5_MASK -#define GPIO_OEN_5_OP_ENABLE_5_DEFVAL -#define GPIO_OEN_5_OP_ENABLE_5_SHIFT 0 -#define GPIO_OEN_5_OP_ENABLE_5_MASK 0xFFFFFFFFU +#define GPIO_OEN_5_OP_ENABLE_5_DEFVAL +#define GPIO_OEN_5_OP_ENABLE_5_SHIFT 0 +#define GPIO_OEN_5_OP_ENABLE_5_MASK 0xFFFFFFFFU -/*Output Data*/ +/* +* Output Data +*/ #undef GPIO_DATA_5_DATA_5_DEFVAL #undef GPIO_DATA_5_DATA_5_SHIFT #undef GPIO_DATA_5_DATA_5_MASK -#define GPIO_DATA_5_DATA_5_DEFVAL -#define GPIO_DATA_5_DATA_5_SHIFT 0 -#define GPIO_DATA_5_DATA_5_MASK 0xFFFFFFFFU +#define GPIO_DATA_5_DATA_5_DEFVAL +#define GPIO_DATA_5_DATA_5_SHIFT 0 +#define GPIO_DATA_5_DATA_5_MASK 0xFFFFFFFFU -/*Output Data*/ +/* +* Output Data +*/ #undef GPIO_DATA_5_DATA_5_DEFVAL #undef GPIO_DATA_5_DATA_5_SHIFT #undef GPIO_DATA_5_DATA_5_MASK -#define GPIO_DATA_5_DATA_5_DEFVAL -#define GPIO_DATA_5_DATA_5_SHIFT 0 -#define GPIO_DATA_5_DATA_5_MASK 0xFFFFFFFFU +#define GPIO_DATA_5_DATA_5_DEFVAL +#define GPIO_DATA_5_DATA_5_SHIFT 0 +#define GPIO_DATA_5_DATA_5_MASK 0xFFFFFFFFU -/*Output Data*/ +/* +* Output Data +*/ #undef GPIO_DATA_5_DATA_5_DEFVAL #undef GPIO_DATA_5_DATA_5_SHIFT #undef GPIO_DATA_5_DATA_5_MASK -#define GPIO_DATA_5_DATA_5_DEFVAL -#define GPIO_DATA_5_DATA_5_SHIFT 0 -#define GPIO_DATA_5_DATA_5_MASK 0xFFFFFFFFU +#define GPIO_DATA_5_DATA_5_DEFVAL +#define GPIO_DATA_5_DATA_5_SHIFT 0 +#define GPIO_DATA_5_DATA_5_MASK 0xFFFFFFFFU #ifdef __cplusplus extern "C" { #endif @@ -27860,6 +36465,7 @@ extern "C" { int psu_ddr_protection(); int psu_lpd_protection(); int psu_protection_lock(); + unsigned long psu_ddr_qos_init_data(void); unsigned long psu_apply_master_tz(); #ifdef __cplusplus } diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init.tcl b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init.tcl index b6d9c0418..bcdd9de80 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init.tcl +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init.tcl @@ -11,7 +11,7 @@ set psu_pll_init_data { # Register : RPLL_CFG @ 0XFF5E0034

# PLL loop filter resistor control - # PSU_CRL_APB_RPLL_CFG_RES 0x2 + # PSU_CRL_APB_RPLL_CFG_RES 0xc # PLL charge pump control # PSU_CRL_APB_RPLL_CFG_CP 0x3 @@ -20,35 +20,39 @@ set psu_pll_init_data { # PSU_CRL_APB_RPLL_CFG_LFHF 0x3 # Lock circuit counter setting - # PSU_CRL_APB_RPLL_CFG_LOCK_CNT 0x258 + # PSU_CRL_APB_RPLL_CFG_LOCK_CNT 0x339 # Lock circuit configuration settings for lock windowsize # PSU_CRL_APB_RPLL_CFG_LOCK_DLY 0x3f # Helper data. Values are to be looked up in a table from Data Sheet - #(OFFSET, MASK, VALUE) (0XFF5E0034, 0xFE7FEDEFU ,0x7E4B0C62U) */ - mask_write 0XFF5E0034 0xFE7FEDEF 0x7E4B0C62 + #(OFFSET, MASK, VALUE) (0XFF5E0034, 0xFE7FEDEFU ,0x7E672C6CU) */ + mask_write 0XFF5E0034 0xFE7FEDEF 0x7E672C6C # : UPDATE FB_DIV # Register : RPLL_CTRL @ 0XFF5E0030

- # Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_ - # ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source + # Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i + # s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour + # ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source # PSU_CRL_APB_RPLL_CTRL_PRE_SRC 0x0 # The integer portion of the feedback divider to the PLL - # PSU_CRL_APB_RPLL_CTRL_FBDIV 0x48 + # PSU_CRL_APB_RPLL_CTRL_FBDIV 0x2d - # This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency + # This turns on the divide by 2 that is inside of the PLL. This does not c + # hange the VCO frequency, just the output frequency # PSU_CRL_APB_RPLL_CTRL_DIV2 0x1 # PLL Basic Control - #(OFFSET, MASK, VALUE) (0XFF5E0030, 0x00717F00U ,0x00014800U) */ - mask_write 0XFF5E0030 0x00717F00 0x00014800 + #(OFFSET, MASK, VALUE) (0XFF5E0030, 0x00717F00U ,0x00012D00U) */ + mask_write 0XFF5E0030 0x00717F00 0x00012D00 # : BY PASS PLL # Register : RPLL_CTRL @ 0XFF5E0030

- # Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - # cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.) + # Bypasses the PLL clock. The usable clock will be determined from the POS + # T_SRC field. (This signal may only be toggled after 4 cycles of the old + # clock and 4 cycles of the new clock. This is not usually an issue, but d + # esigners must be aware.) # PSU_CRL_APB_RPLL_CTRL_BYPASS 1 # PLL Basic Control @@ -57,7 +61,8 @@ set psu_pll_init_data { # : ASSERT RESET # Register : RPLL_CTRL @ 0XFF5E0030

- # Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS. + # Asserts Reset to the PLL. When asserting reset, the PLL must already be + # in BYPASS. # PSU_CRL_APB_RPLL_CTRL_RESET 1 # PLL Basic Control @@ -66,7 +71,8 @@ set psu_pll_init_data { # : DEASSERT RESET # Register : RPLL_CTRL @ 0XFF5E0030

- # Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS. + # Asserts Reset to the PLL. When asserting reset, the PLL must already be + # in BYPASS. # PSU_CRL_APB_RPLL_CTRL_RESET 0 # PLL Basic Control @@ -81,8 +87,10 @@ set psu_pll_init_data { # : REMOVE PLL BY PASS # Register : RPLL_CTRL @ 0XFF5E0030

- # Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - # cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.) + # Bypasses the PLL clock. The usable clock will be determined from the POS + # T_SRC field. (This signal may only be toggled after 4 cycles of the old + # clock and 4 cycles of the new clock. This is not usually an issue, but d + # esigners must be aware.) # PSU_CRL_APB_RPLL_CTRL_BYPASS 0 # PLL Basic Control @@ -91,66 +99,59 @@ set psu_pll_init_data { # Register : RPLL_TO_FPD_CTRL @ 0XFF5E0048

# Divisor value for this clock. - # PSU_CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0 0x3 + # PSU_CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0 0x2 - # Control for a clock that will be generated in the LPD, but used in the FPD as a clock source for the peripheral clock muxes. - #(OFFSET, MASK, VALUE) (0XFF5E0048, 0x00003F00U ,0x00000300U) */ - mask_write 0XFF5E0048 0x00003F00 0x00000300 + # Control for a clock that will be generated in the LPD, but used in the F + # PD as a clock source for the peripheral clock muxes. + #(OFFSET, MASK, VALUE) (0XFF5E0048, 0x00003F00U ,0x00000200U) */ + mask_write 0XFF5E0048 0x00003F00 0x00000200 # : RPLL FRAC CFG - # Register : RPLL_FRAC_CFG @ 0XFF5E0038

- - # Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona - # mode and uses DATA of this register for the fractional portion of the feedback divider. - # PSU_CRL_APB_RPLL_FRAC_CFG_ENABLED 0x0 - - # Fractional value for the Feedback value. - # PSU_CRL_APB_RPLL_FRAC_CFG_DATA 0x0 - - # Fractional control for the PLL - #(OFFSET, MASK, VALUE) (0XFF5E0038, 0x8000FFFFU ,0x00000000U) */ - mask_write 0XFF5E0038 0x8000FFFF 0x00000000 # : IOPLL INIT # Register : IOPLL_CFG @ 0XFF5E0024

# PLL loop filter resistor control - # PSU_CRL_APB_IOPLL_CFG_RES 0xc + # PSU_CRL_APB_IOPLL_CFG_RES 0x2 # PLL charge pump control - # PSU_CRL_APB_IOPLL_CFG_CP 0x3 + # PSU_CRL_APB_IOPLL_CFG_CP 0x4 # PLL loop filter high frequency capacitor control # PSU_CRL_APB_IOPLL_CFG_LFHF 0x3 # Lock circuit counter setting - # PSU_CRL_APB_IOPLL_CFG_LOCK_CNT 0x339 + # PSU_CRL_APB_IOPLL_CFG_LOCK_CNT 0x258 # Lock circuit configuration settings for lock windowsize # PSU_CRL_APB_IOPLL_CFG_LOCK_DLY 0x3f # Helper data. Values are to be looked up in a table from Data Sheet - #(OFFSET, MASK, VALUE) (0XFF5E0024, 0xFE7FEDEFU ,0x7E672C6CU) */ - mask_write 0XFF5E0024 0xFE7FEDEF 0x7E672C6C + #(OFFSET, MASK, VALUE) (0XFF5E0024, 0xFE7FEDEFU ,0x7E4B0C82U) */ + mask_write 0XFF5E0024 0xFE7FEDEF 0x7E4B0C82 # : UPDATE FB_DIV # Register : IOPLL_CTRL @ 0XFF5E0020

- # Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_ - # ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source + # Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i + # s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour + # ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source # PSU_CRL_APB_IOPLL_CTRL_PRE_SRC 0x0 # The integer portion of the feedback divider to the PLL - # PSU_CRL_APB_IOPLL_CTRL_FBDIV 0x2d + # PSU_CRL_APB_IOPLL_CTRL_FBDIV 0x5a - # This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency - # PSU_CRL_APB_IOPLL_CTRL_DIV2 0x0 + # This turns on the divide by 2 that is inside of the PLL. This does not c + # hange the VCO frequency, just the output frequency + # PSU_CRL_APB_IOPLL_CTRL_DIV2 0x1 # PLL Basic Control - #(OFFSET, MASK, VALUE) (0XFF5E0020, 0x00717F00U ,0x00002D00U) */ - mask_write 0XFF5E0020 0x00717F00 0x00002D00 + #(OFFSET, MASK, VALUE) (0XFF5E0020, 0x00717F00U ,0x00015A00U) */ + mask_write 0XFF5E0020 0x00717F00 0x00015A00 # : BY PASS PLL # Register : IOPLL_CTRL @ 0XFF5E0020

- # Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - # cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.) + # Bypasses the PLL clock. The usable clock will be determined from the POS + # T_SRC field. (This signal may only be toggled after 4 cycles of the old + # clock and 4 cycles of the new clock. This is not usually an issue, but d + # esigners must be aware.) # PSU_CRL_APB_IOPLL_CTRL_BYPASS 1 # PLL Basic Control @@ -159,7 +160,8 @@ set psu_pll_init_data { # : ASSERT RESET # Register : IOPLL_CTRL @ 0XFF5E0020

- # Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS. + # Asserts Reset to the PLL. When asserting reset, the PLL must already be + # in BYPASS. # PSU_CRL_APB_IOPLL_CTRL_RESET 1 # PLL Basic Control @@ -168,7 +170,8 @@ set psu_pll_init_data { # : DEASSERT RESET # Register : IOPLL_CTRL @ 0XFF5E0020

- # Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS. + # Asserts Reset to the PLL. When asserting reset, the PLL must already be + # in BYPASS. # PSU_CRL_APB_IOPLL_CTRL_RESET 0 # PLL Basic Control @@ -183,8 +186,10 @@ set psu_pll_init_data { # : REMOVE PLL BY PASS # Register : IOPLL_CTRL @ 0XFF5E0020

- # Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - # cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.) + # Bypasses the PLL clock. The usable clock will be determined from the POS + # T_SRC field. (This signal may only be toggled after 4 cycles of the old + # clock and 4 cycles of the new clock. This is not usually an issue, but d + # esigners must be aware.) # PSU_CRL_APB_IOPLL_CTRL_BYPASS 0 # PLL Basic Control @@ -195,22 +200,11 @@ set psu_pll_init_data { # Divisor value for this clock. # PSU_CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0 0x3 - # Control for a clock that will be generated in the LPD, but used in the FPD as a clock source for the peripheral clock muxes. + # Control for a clock that will be generated in the LPD, but used in the F + # PD as a clock source for the peripheral clock muxes. #(OFFSET, MASK, VALUE) (0XFF5E0044, 0x00003F00U ,0x00000300U) */ mask_write 0XFF5E0044 0x00003F00 0x00000300 # : IOPLL FRAC CFG - # Register : IOPLL_FRAC_CFG @ 0XFF5E0028

- - # Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona - # mode and uses DATA of this register for the fractional portion of the feedback divider. - # PSU_CRL_APB_IOPLL_FRAC_CFG_ENABLED 0x0 - - # Fractional value for the Feedback value. - # PSU_CRL_APB_IOPLL_FRAC_CFG_DATA 0x0 - - # Fractional control for the PLL - #(OFFSET, MASK, VALUE) (0XFF5E0028, 0x8000FFFFU ,0x00000000U) */ - mask_write 0XFF5E0028 0x8000FFFF 0x00000000 # : APU_PLL INIT # Register : APLL_CFG @ 0XFD1A0024

@@ -235,24 +229,28 @@ set psu_pll_init_data { # : UPDATE FB_DIV # Register : APLL_CTRL @ 0XFD1A0020

- # Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_ - # ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source + # Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i + # s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour + # ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source # PSU_CRF_APB_APLL_CTRL_PRE_SRC 0x0 # The integer portion of the feedback divider to the PLL - # PSU_CRF_APB_APLL_CTRL_FBDIV 0x42 + # PSU_CRF_APB_APLL_CTRL_FBDIV 0x48 - # This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency + # This turns on the divide by 2 that is inside of the PLL. This does not c + # hange the VCO frequency, just the output frequency # PSU_CRF_APB_APLL_CTRL_DIV2 0x1 # PLL Basic Control - #(OFFSET, MASK, VALUE) (0XFD1A0020, 0x00717F00U ,0x00014200U) */ - mask_write 0XFD1A0020 0x00717F00 0x00014200 + #(OFFSET, MASK, VALUE) (0XFD1A0020, 0x00717F00U ,0x00014800U) */ + mask_write 0XFD1A0020 0x00717F00 0x00014800 # : BY PASS PLL # Register : APLL_CTRL @ 0XFD1A0020

- # Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - # cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.) + # Bypasses the PLL clock. The usable clock will be determined from the POS + # T_SRC field. (This signal may only be toggled after 4 cycles of the old + # clock and 4 cycles of the new clock. This is not usually an issue, but d + # esigners must be aware.) # PSU_CRF_APB_APLL_CTRL_BYPASS 1 # PLL Basic Control @@ -261,7 +259,8 @@ set psu_pll_init_data { # : ASSERT RESET # Register : APLL_CTRL @ 0XFD1A0020

- # Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS. + # Asserts Reset to the PLL. When asserting reset, the PLL must already be + # in BYPASS. # PSU_CRF_APB_APLL_CTRL_RESET 1 # PLL Basic Control @@ -270,7 +269,8 @@ set psu_pll_init_data { # : DEASSERT RESET # Register : APLL_CTRL @ 0XFD1A0020

- # Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS. + # Asserts Reset to the PLL. When asserting reset, the PLL must already be + # in BYPASS. # PSU_CRF_APB_APLL_CTRL_RESET 0 # PLL Basic Control @@ -285,8 +285,10 @@ set psu_pll_init_data { # : REMOVE PLL BY PASS # Register : APLL_CTRL @ 0XFD1A0020

- # Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - # cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.) + # Bypasses the PLL clock. The usable clock will be determined from the POS + # T_SRC field. (This signal may only be toggled after 4 cycles of the old + # clock and 4 cycles of the new clock. This is not usually an issue, but d + # esigners must be aware.) # PSU_CRF_APB_APLL_CTRL_BYPASS 0 # PLL Basic Control @@ -297,22 +299,11 @@ set psu_pll_init_data { # Divisor value for this clock. # PSU_CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0 0x3 - # Control for a clock that will be generated in the FPD, but used in the LPD as a clock source for the peripheral clock muxes. + # Control for a clock that will be generated in the FPD, but used in the L + # PD as a clock source for the peripheral clock muxes. #(OFFSET, MASK, VALUE) (0XFD1A0048, 0x00003F00U ,0x00000300U) */ mask_write 0XFD1A0048 0x00003F00 0x00000300 # : APLL FRAC CFG - # Register : APLL_FRAC_CFG @ 0XFD1A0028

- - # Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona - # mode and uses DATA of this register for the fractional portion of the feedback divider. - # PSU_CRF_APB_APLL_FRAC_CFG_ENABLED 0x0 - - # Fractional value for the Feedback value. - # PSU_CRF_APB_APLL_FRAC_CFG_DATA 0x0 - - # Fractional control for the PLL - #(OFFSET, MASK, VALUE) (0XFD1A0028, 0x8000FFFFU ,0x00000000U) */ - mask_write 0XFD1A0028 0x8000FFFF 0x00000000 # : DDR_PLL INIT # Register : DPLL_CFG @ 0XFD1A0030

@@ -337,14 +328,16 @@ set psu_pll_init_data { # : UPDATE FB_DIV # Register : DPLL_CTRL @ 0XFD1A002C

- # Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_ - # ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source + # Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i + # s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour + # ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source # PSU_CRF_APB_DPLL_CTRL_PRE_SRC 0x0 # The integer portion of the feedback divider to the PLL # PSU_CRF_APB_DPLL_CTRL_FBDIV 0x40 - # This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency + # This turns on the divide by 2 that is inside of the PLL. This does not c + # hange the VCO frequency, just the output frequency # PSU_CRF_APB_DPLL_CTRL_DIV2 0x1 # PLL Basic Control @@ -353,8 +346,10 @@ set psu_pll_init_data { # : BY PASS PLL # Register : DPLL_CTRL @ 0XFD1A002C

- # Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - # cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.) + # Bypasses the PLL clock. The usable clock will be determined from the POS + # T_SRC field. (This signal may only be toggled after 4 cycles of the old + # clock and 4 cycles of the new clock. This is not usually an issue, but d + # esigners must be aware.) # PSU_CRF_APB_DPLL_CTRL_BYPASS 1 # PLL Basic Control @@ -363,7 +358,8 @@ set psu_pll_init_data { # : ASSERT RESET # Register : DPLL_CTRL @ 0XFD1A002C

- # Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS. + # Asserts Reset to the PLL. When asserting reset, the PLL must already be + # in BYPASS. # PSU_CRF_APB_DPLL_CTRL_RESET 1 # PLL Basic Control @@ -372,7 +368,8 @@ set psu_pll_init_data { # : DEASSERT RESET # Register : DPLL_CTRL @ 0XFD1A002C

- # Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS. + # Asserts Reset to the PLL. When asserting reset, the PLL must already be + # in BYPASS. # PSU_CRF_APB_DPLL_CTRL_RESET 0 # PLL Basic Control @@ -387,8 +384,10 @@ set psu_pll_init_data { # : REMOVE PLL BY PASS # Register : DPLL_CTRL @ 0XFD1A002C

- # Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - # cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.) + # Bypasses the PLL clock. The usable clock will be determined from the POS + # T_SRC field. (This signal may only be toggled after 4 cycles of the old + # clock and 4 cycles of the new clock. This is not usually an issue, but d + # esigners must be aware.) # PSU_CRF_APB_DPLL_CTRL_BYPASS 0 # PLL Basic Control @@ -397,24 +396,13 @@ set psu_pll_init_data { # Register : DPLL_TO_LPD_CTRL @ 0XFD1A004C

# Divisor value for this clock. - # PSU_CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0 0x3 + # PSU_CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0 0x2 - # Control for a clock that will be generated in the FPD, but used in the LPD as a clock source for the peripheral clock muxes. - #(OFFSET, MASK, VALUE) (0XFD1A004C, 0x00003F00U ,0x00000300U) */ - mask_write 0XFD1A004C 0x00003F00 0x00000300 + # Control for a clock that will be generated in the FPD, but used in the L + # PD as a clock source for the peripheral clock muxes. + #(OFFSET, MASK, VALUE) (0XFD1A004C, 0x00003F00U ,0x00000200U) */ + mask_write 0XFD1A004C 0x00003F00 0x00000200 # : DPLL FRAC CFG - # Register : DPLL_FRAC_CFG @ 0XFD1A0034

- - # Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona - # mode and uses DATA of this register for the fractional portion of the feedback divider. - # PSU_CRF_APB_DPLL_FRAC_CFG_ENABLED 0x0 - - # Fractional value for the Feedback value. - # PSU_CRF_APB_DPLL_FRAC_CFG_DATA 0x0 - - # Fractional control for the PLL - #(OFFSET, MASK, VALUE) (0XFD1A0034, 0x8000FFFFU ,0x00000000U) */ - mask_write 0XFD1A0034 0x8000FFFF 0x00000000 # : VIDEO_PLL INIT # Register : VPLL_CFG @ 0XFD1A003C

@@ -422,41 +410,45 @@ set psu_pll_init_data { # PSU_CRF_APB_VPLL_CFG_RES 0x2 # PLL charge pump control - # PSU_CRF_APB_VPLL_CFG_CP 0x3 + # PSU_CRF_APB_VPLL_CFG_CP 0x4 # PLL loop filter high frequency capacitor control # PSU_CRF_APB_VPLL_CFG_LFHF 0x3 # Lock circuit counter setting - # PSU_CRF_APB_VPLL_CFG_LOCK_CNT 0x28a + # PSU_CRF_APB_VPLL_CFG_LOCK_CNT 0x258 # Lock circuit configuration settings for lock windowsize # PSU_CRF_APB_VPLL_CFG_LOCK_DLY 0x3f # Helper data. Values are to be looked up in a table from Data Sheet - #(OFFSET, MASK, VALUE) (0XFD1A003C, 0xFE7FEDEFU ,0x7E514C62U) */ - mask_write 0XFD1A003C 0xFE7FEDEF 0x7E514C62 + #(OFFSET, MASK, VALUE) (0XFD1A003C, 0xFE7FEDEFU ,0x7E4B0C82U) */ + mask_write 0XFD1A003C 0xFE7FEDEF 0x7E4B0C82 # : UPDATE FB_DIV # Register : VPLL_CTRL @ 0XFD1A0038

- # Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_ - # ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source + # Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i + # s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour + # ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source # PSU_CRF_APB_VPLL_CTRL_PRE_SRC 0x0 # The integer portion of the feedback divider to the PLL - # PSU_CRF_APB_VPLL_CTRL_FBDIV 0x39 + # PSU_CRF_APB_VPLL_CTRL_FBDIV 0x5a - # This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency + # This turns on the divide by 2 that is inside of the PLL. This does not c + # hange the VCO frequency, just the output frequency # PSU_CRF_APB_VPLL_CTRL_DIV2 0x1 # PLL Basic Control - #(OFFSET, MASK, VALUE) (0XFD1A0038, 0x00717F00U ,0x00013900U) */ - mask_write 0XFD1A0038 0x00717F00 0x00013900 + #(OFFSET, MASK, VALUE) (0XFD1A0038, 0x00717F00U ,0x00015A00U) */ + mask_write 0XFD1A0038 0x00717F00 0x00015A00 # : BY PASS PLL # Register : VPLL_CTRL @ 0XFD1A0038

- # Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - # cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.) + # Bypasses the PLL clock. The usable clock will be determined from the POS + # T_SRC field. (This signal may only be toggled after 4 cycles of the old + # clock and 4 cycles of the new clock. This is not usually an issue, but d + # esigners must be aware.) # PSU_CRF_APB_VPLL_CTRL_BYPASS 1 # PLL Basic Control @@ -465,7 +457,8 @@ set psu_pll_init_data { # : ASSERT RESET # Register : VPLL_CTRL @ 0XFD1A0038

- # Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS. + # Asserts Reset to the PLL. When asserting reset, the PLL must already be + # in BYPASS. # PSU_CRF_APB_VPLL_CTRL_RESET 1 # PLL Basic Control @@ -474,7 +467,8 @@ set psu_pll_init_data { # : DEASSERT RESET # Register : VPLL_CTRL @ 0XFD1A0038

- # Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS. + # Asserts Reset to the PLL. When asserting reset, the PLL must already be + # in BYPASS. # PSU_CRF_APB_VPLL_CTRL_RESET 0 # PLL Basic Control @@ -489,8 +483,10 @@ set psu_pll_init_data { # : REMOVE PLL BY PASS # Register : VPLL_CTRL @ 0XFD1A0038

- # Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - # cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.) + # Bypasses the PLL clock. The usable clock will be determined from the POS + # T_SRC field. (This signal may only be toggled after 4 cycles of the old + # clock and 4 cycles of the new clock. This is not usually an issue, but d + # esigners must be aware.) # PSU_CRF_APB_VPLL_CTRL_BYPASS 0 # PLL Basic Control @@ -501,22 +497,11 @@ set psu_pll_init_data { # Divisor value for this clock. # PSU_CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0 0x3 - # Control for a clock that will be generated in the FPD, but used in the LPD as a clock source for the peripheral clock muxes. + # Control for a clock that will be generated in the FPD, but used in the L + # PD as a clock source for the peripheral clock muxes. #(OFFSET, MASK, VALUE) (0XFD1A0050, 0x00003F00U ,0x00000300U) */ mask_write 0XFD1A0050 0x00003F00 0x00000300 # : VIDEO FRAC CFG - # Register : VPLL_FRAC_CFG @ 0XFD1A0040

- - # Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona - # mode and uses DATA of this register for the fractional portion of the feedback divider. - # PSU_CRF_APB_VPLL_FRAC_CFG_ENABLED 0x1 - - # Fractional value for the Feedback value. - # PSU_CRF_APB_VPLL_FRAC_CFG_DATA 0x820c - - # Fractional control for the PLL - #(OFFSET, MASK, VALUE) (0XFD1A0040, 0x8000FFFFU ,0x8000820CU) */ - mask_write 0XFD1A0040 0x8000FFFF 0x8000820C } set psu_clock_init_data { @@ -535,13 +520,33 @@ set psu_clock_init_data { # 6 bit divider # PSU_CRL_APB_GEM3_REF_CTRL_DIVISOR0 0xc - # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - # clock. This is not usually an issue, but designers must be aware.) + # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + # ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + # usually an issue, but designers must be aware.) # PSU_CRL_APB_GEM3_REF_CTRL_SRCSEL 0x0 # This register controls this reference clock #(OFFSET, MASK, VALUE) (0XFF5E005C, 0x063F3F07U ,0x06010C00U) */ mask_write 0XFF5E005C 0x063F3F07 0x06010C00 + # Register : GEM_TSU_REF_CTRL @ 0XFF5E0100

+ + # 6 bit divider + # PSU_CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0 0x6 + + # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + # ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + # usually an issue, but designers must be aware.) + # PSU_CRL_APB_GEM_TSU_REF_CTRL_SRCSEL 0x0 + + # 6 bit divider + # PSU_CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1 0x1 + + # Clock active signal. Switch to 0 to disable the clock + # PSU_CRL_APB_GEM_TSU_REF_CTRL_CLKACT 0x1 + + # This register controls this reference clock + #(OFFSET, MASK, VALUE) (0XFF5E0100, 0x013F3F07U ,0x01010600U) */ + mask_write 0XFF5E0100 0x013F3F07 0x01010600 # Register : USB0_BUS_REF_CTRL @ 0XFF5E0060

# Clock active signal. Switch to 0 to disable the clock @@ -553,8 +558,9 @@ set psu_clock_init_data { # 6 bit divider # PSU_CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0 0x6 - # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - # clock. This is not usually an issue, but designers must be aware.) + # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + # ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + # usually an issue, but designers must be aware.) # PSU_CRL_APB_USB0_BUS_REF_CTRL_SRCSEL 0x0 # This register controls this reference clock @@ -566,18 +572,19 @@ set psu_clock_init_data { # PSU_CRL_APB_USB3_DUAL_REF_CTRL_CLKACT 0x1 # 6 bit divider - # PSU_CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1 0xf + # PSU_CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1 0x3 # 6 bit divider - # PSU_CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0 0x5 + # PSU_CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0 0x19 - # 000 = IOPLL; 010 = RPLL; 011 = DPLL. (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - # clock. This is not usually an issue, but designers must be aware.) + # 000 = IOPLL; 010 = RPLL; 011 = DPLL. (This signal may only be toggled af + # ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + # usually an issue, but designers must be aware.) # PSU_CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL 0x0 # This register controls this reference clock - #(OFFSET, MASK, VALUE) (0XFF5E004C, 0x023F3F07U ,0x020F0500U) */ - mask_write 0XFF5E004C 0x023F3F07 0x020F0500 + #(OFFSET, MASK, VALUE) (0XFF5E004C, 0x023F3F07U ,0x02031900U) */ + mask_write 0XFF5E004C 0x023F3F07 0x02031900 # Register : QSPI_REF_CTRL @ 0XFF5E0068

# Clock active signal. Switch to 0 to disable the clock @@ -589,8 +596,9 @@ set psu_clock_init_data { # 6 bit divider # PSU_CRL_APB_QSPI_REF_CTRL_DIVISOR0 0xc - # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - # clock. This is not usually an issue, but designers must be aware.) + # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + # ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + # usually an issue, but designers must be aware.) # PSU_CRL_APB_QSPI_REF_CTRL_SRCSEL 0x0 # This register controls this reference clock @@ -605,18 +613,20 @@ set psu_clock_init_data { # PSU_CRL_APB_SDIO1_REF_CTRL_DIVISOR1 0x1 # 6 bit divider - # PSU_CRL_APB_SDIO1_REF_CTRL_DIVISOR0 0x6 + # PSU_CRL_APB_SDIO1_REF_CTRL_DIVISOR0 0x8 - # 000 = IOPLL; 010 = RPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - # clock. This is not usually an issue, but designers must be aware.) - # PSU_CRL_APB_SDIO1_REF_CTRL_SRCSEL 0x2 + # 000 = IOPLL; 010 = RPLL; 011 = VPLL; (This signal may only be toggled af + # ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + # usually an issue, but designers must be aware.) + # PSU_CRL_APB_SDIO1_REF_CTRL_SRCSEL 0x0 # This register controls this reference clock - #(OFFSET, MASK, VALUE) (0XFF5E0070, 0x013F3F07U ,0x01010602U) */ - mask_write 0XFF5E0070 0x013F3F07 0x01010602 + #(OFFSET, MASK, VALUE) (0XFF5E0070, 0x013F3F07U ,0x01010800U) */ + mask_write 0XFF5E0070 0x013F3F07 0x01010800 # Register : SDIO_CLK_CTRL @ 0XFF18030C

- # MIO pad selection for sdio1_rx_clk (feedback clock from the PAD) 0: MIO [51] 1: MIO [76] + # MIO pad selection for sdio1_rx_clk (feedback clock from the PAD) 0: MIO + # [51] 1: MIO [76] # PSU_IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL 0 # SoC Debug Clock Control @@ -633,8 +643,9 @@ set psu_clock_init_data { # 6 bit divider # PSU_CRL_APB_UART0_REF_CTRL_DIVISOR0 0xf - # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - # clock. This is not usually an issue, but designers must be aware.) + # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + # ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + # usually an issue, but designers must be aware.) # PSU_CRL_APB_UART0_REF_CTRL_SRCSEL 0x0 # This register controls this reference clock @@ -651,8 +662,9 @@ set psu_clock_init_data { # 6 bit divider # PSU_CRL_APB_UART1_REF_CTRL_DIVISOR0 0xf - # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - # clock. This is not usually an issue, but designers must be aware.) + # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + # ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + # usually an issue, but designers must be aware.) # PSU_CRL_APB_UART1_REF_CTRL_SRCSEL 0x0 # This register controls this reference clock @@ -669,8 +681,9 @@ set psu_clock_init_data { # 6 bit divider # PSU_CRL_APB_I2C0_REF_CTRL_DIVISOR0 0xf - # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - # clock. This is not usually an issue, but designers must be aware.) + # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + # ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + # usually an issue, but designers must be aware.) # PSU_CRL_APB_I2C0_REF_CTRL_SRCSEL 0x0 # This register controls this reference clock @@ -687,8 +700,9 @@ set psu_clock_init_data { # 6 bit divider # PSU_CRL_APB_I2C1_REF_CTRL_DIVISOR0 0xf - # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - # clock. This is not usually an issue, but designers must be aware.) + # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + # ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + # usually an issue, but designers must be aware.) # PSU_CRL_APB_I2C1_REF_CTRL_SRCSEL 0x0 # This register controls this reference clock @@ -705,8 +719,9 @@ set psu_clock_init_data { # 6 bit divider # PSU_CRL_APB_CAN1_REF_CTRL_DIVISOR0 0xf - # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - # clock. This is not usually an issue, but designers must be aware.) + # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + # ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + # usually an issue, but designers must be aware.) # PSU_CRL_APB_CAN1_REF_CTRL_SRCSEL 0x0 # This register controls this reference clock @@ -714,15 +729,17 @@ set psu_clock_init_data { mask_write 0XFF5E0088 0x013F3F07 0x01010F00 # Register : CPU_R5_CTRL @ 0XFF5E0090

- # Turing this off will shut down the OCM, some parts of the APM, and prevent transactions going from the FPD to the LPD and cou - # d lead to system hang + # Turing this off will shut down the OCM, some parts of the APM, and preve + # nt transactions going from the FPD to the LPD and could lead to system h + # ang # PSU_CRL_APB_CPU_R5_CTRL_CLKACT 0x1 # 6 bit divider # PSU_CRL_APB_CPU_R5_CTRL_DIVISOR0 0x3 - # 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - # clock. This is not usually an issue, but designers must be aware.) + # 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + # ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + # usually an issue, but designers must be aware.) # PSU_CRL_APB_CPU_R5_CTRL_SRCSEL 0x2 # This register controls this reference clock @@ -736,8 +753,9 @@ set psu_clock_init_data { # 6 bit divider # PSU_CRL_APB_IOU_SWITCH_CTRL_DIVISOR0 0x6 - # 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - # clock. This is not usually an issue, but designers must be aware.) + # 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + # ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + # usually an issue, but designers must be aware.) # PSU_CRL_APB_IOU_SWITCH_CTRL_SRCSEL 0x2 # This register controls this reference clock @@ -749,15 +767,16 @@ set psu_clock_init_data { # PSU_CRL_APB_PCAP_CTRL_CLKACT 0x1 # 6 bit divider - # PSU_CRL_APB_PCAP_CTRL_DIVISOR0 0x6 + # PSU_CRL_APB_PCAP_CTRL_DIVISOR0 0x8 - # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - # clock. This is not usually an issue, but designers must be aware.) - # PSU_CRL_APB_PCAP_CTRL_SRCSEL 0x2 + # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + # ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + # usually an issue, but designers must be aware.) + # PSU_CRL_APB_PCAP_CTRL_SRCSEL 0x0 # This register controls this reference clock - #(OFFSET, MASK, VALUE) (0XFF5E00A4, 0x01003F07U ,0x01000602U) */ - mask_write 0XFF5E00A4 0x01003F07 0x01000602 + #(OFFSET, MASK, VALUE) (0XFF5E00A4, 0x01003F07U ,0x01000800U) */ + mask_write 0XFF5E00A4 0x01003F07 0x01000800 # Register : LPD_SWITCH_CTRL @ 0XFF5E00A8

# Clock active signal. Switch to 0 to disable the clock @@ -766,8 +785,9 @@ set psu_clock_init_data { # 6 bit divider # PSU_CRL_APB_LPD_SWITCH_CTRL_DIVISOR0 0x3 - # 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - # clock. This is not usually an issue, but designers must be aware.) + # 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + # ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + # usually an issue, but designers must be aware.) # PSU_CRL_APB_LPD_SWITCH_CTRL_SRCSEL 0x2 # This register controls this reference clock @@ -781,8 +801,9 @@ set psu_clock_init_data { # 6 bit divider # PSU_CRL_APB_LPD_LSBUS_CTRL_DIVISOR0 0xf - # 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - # clock. This is not usually an issue, but designers must be aware.) + # 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + # ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + # usually an issue, but designers must be aware.) # PSU_CRL_APB_LPD_LSBUS_CTRL_SRCSEL 0x2 # This register controls this reference clock @@ -796,8 +817,9 @@ set psu_clock_init_data { # 6 bit divider # PSU_CRL_APB_DBG_LPD_CTRL_DIVISOR0 0x6 - # 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - # clock. This is not usually an issue, but designers must be aware.) + # 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + # ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + # usually an issue, but designers must be aware.) # PSU_CRL_APB_DBG_LPD_CTRL_SRCSEL 0x2 # This register controls this reference clock @@ -811,8 +833,9 @@ set psu_clock_init_data { # 6 bit divider # PSU_CRL_APB_ADMA_REF_CTRL_DIVISOR0 0x3 - # 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - # clock. This is not usually an issue, but designers must be aware.) + # 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + # ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + # usually an issue, but designers must be aware.) # PSU_CRL_APB_ADMA_REF_CTRL_SRCSEL 0x2 # This register controls this reference clock @@ -829,89 +852,38 @@ set psu_clock_init_data { # 6 bit divider # PSU_CRL_APB_PL0_REF_CTRL_DIVISOR0 0xf - # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - # clock. This is not usually an issue, but designers must be aware.) + # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + # ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + # usually an issue, but designers must be aware.) # PSU_CRL_APB_PL0_REF_CTRL_SRCSEL 0x0 # This register controls this reference clock #(OFFSET, MASK, VALUE) (0XFF5E00C0, 0x013F3F07U ,0x01010F00U) */ mask_write 0XFF5E00C0 0x013F3F07 0x01010F00 - # Register : PL1_REF_CTRL @ 0XFF5E00C4

- - # Clock active signal. Switch to 0 to disable the clock - # PSU_CRL_APB_PL1_REF_CTRL_CLKACT 0x1 - - # 6 bit divider - # PSU_CRL_APB_PL1_REF_CTRL_DIVISOR1 0x4 - - # 6 bit divider - # PSU_CRL_APB_PL1_REF_CTRL_DIVISOR0 0xf - - # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - # clock. This is not usually an issue, but designers must be aware.) - # PSU_CRL_APB_PL1_REF_CTRL_SRCSEL 0x0 - - # This register controls this reference clock - #(OFFSET, MASK, VALUE) (0XFF5E00C4, 0x013F3F07U ,0x01040F00U) */ - mask_write 0XFF5E00C4 0x013F3F07 0x01040F00 - # Register : PL2_REF_CTRL @ 0XFF5E00C8

- - # Clock active signal. Switch to 0 to disable the clock - # PSU_CRL_APB_PL2_REF_CTRL_CLKACT 0x1 - - # 6 bit divider - # PSU_CRL_APB_PL2_REF_CTRL_DIVISOR1 0x1 - - # 6 bit divider - # PSU_CRL_APB_PL2_REF_CTRL_DIVISOR0 0x4 - - # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - # clock. This is not usually an issue, but designers must be aware.) - # PSU_CRL_APB_PL2_REF_CTRL_SRCSEL 0x2 - - # This register controls this reference clock - #(OFFSET, MASK, VALUE) (0XFF5E00C8, 0x013F3F07U ,0x01010402U) */ - mask_write 0XFF5E00C8 0x013F3F07 0x01010402 - # Register : PL3_REF_CTRL @ 0XFF5E00CC

- - # Clock active signal. Switch to 0 to disable the clock - # PSU_CRL_APB_PL3_REF_CTRL_CLKACT 0x1 - - # 6 bit divider - # PSU_CRL_APB_PL3_REF_CTRL_DIVISOR1 0x1 - - # 6 bit divider - # PSU_CRL_APB_PL3_REF_CTRL_DIVISOR0 0x3 - - # 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - # clock. This is not usually an issue, but designers must be aware.) - # PSU_CRL_APB_PL3_REF_CTRL_SRCSEL 0x2 - - # This register controls this reference clock - #(OFFSET, MASK, VALUE) (0XFF5E00CC, 0x013F3F07U ,0x01010302U) */ - mask_write 0XFF5E00CC 0x013F3F07 0x01010302 # Register : AMS_REF_CTRL @ 0XFF5E0108

# 6 bit divider # PSU_CRL_APB_AMS_REF_CTRL_DIVISOR1 0x1 # 6 bit divider - # PSU_CRL_APB_AMS_REF_CTRL_DIVISOR0 0x1d + # PSU_CRL_APB_AMS_REF_CTRL_DIVISOR0 0x1e - # 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - # clock. This is not usually an issue, but designers must be aware.) + # 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + # ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + # usually an issue, but designers must be aware.) # PSU_CRL_APB_AMS_REF_CTRL_SRCSEL 0x2 # Clock active signal. Switch to 0 to disable the clock # PSU_CRL_APB_AMS_REF_CTRL_CLKACT 0x1 # This register controls this reference clock - #(OFFSET, MASK, VALUE) (0XFF5E0108, 0x013F3F07U ,0x01011D02U) */ - mask_write 0XFF5E0108 0x013F3F07 0x01011D02 + #(OFFSET, MASK, VALUE) (0XFF5E0108, 0x013F3F07U ,0x01011E02U) */ + mask_write 0XFF5E0108 0x013F3F07 0x01011E02 # Register : DLL_REF_CTRL @ 0XFF5E0104

- # 000 = IOPLL; 001 = RPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This - # is not usually an issue, but designers must be aware.) + # 000 = IOPLL; 001 = RPLL; (This signal may only be toggled after 4 cycles + # of the old clock and 4 cycles of the new clock. This is not usually an + # issue, but designers must be aware.) # PSU_CRL_APB_DLL_REF_CTRL_SRCSEL 0 # This register controls this reference clock @@ -922,8 +894,9 @@ set psu_clock_init_data { # 6 bit divider # PSU_CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0 0xf - # 1XX = pss_ref_clk; 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and - # cycles of the new clock. This is not usually an issue, but designers must be aware.) + # 1XX = pss_ref_clk; 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may + # only be toggled after 4 cycles of the old clock and 4 cycles of the new + # clock. This is not usually an issue, but designers must be aware.) # PSU_CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL 0x0 # Clock active signal. Switch to 0 to disable the clock @@ -934,8 +907,9 @@ set psu_clock_init_data { mask_write 0XFF5E0128 0x01003F07 0x01000F00 # Register : SATA_REF_CTRL @ 0XFD1A00A0

- # 000 = IOPLL_TO_FPD; 010 = APLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of - # he new clock. This is not usually an issue, but designers must be aware.) + # 000 = IOPLL_TO_FPD; 010 = APLL; 011 = DPLL; (This signal may only be tog + # gled after 4 cycles of the old clock and 4 cycles of the new clock. This + # is not usually an issue, but designers must be aware.) # PSU_CRF_APB_SATA_REF_CTRL_SRCSEL 0x0 # Clock active signal. Switch to 0 to disable the clock @@ -949,8 +923,9 @@ set psu_clock_init_data { mask_write 0XFD1A00A0 0x01003F07 0x01000200 # Register : PCIE_REF_CTRL @ 0XFD1A00B4

- # 000 = IOPLL_TO_FPD; 010 = RPLL_TO_FPD; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cyc - # es of the new clock. This is not usually an issue, but designers must be aware.) + # 000 = IOPLL_TO_FPD; 010 = RPLL_TO_FPD; 011 = DPLL; (This signal may only + # be toggled after 4 cycles of the old clock and 4 cycles of the new cloc + # k. This is not usually an issue, but designers must be aware.) # PSU_CRF_APB_PCIE_REF_CTRL_SRCSEL 0x0 # Clock active signal. Switch to 0 to disable the clock @@ -968,95 +943,88 @@ set psu_clock_init_data { # PSU_CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1 0x1 # 6 bit divider - # PSU_CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0 0x3 + # PSU_CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0 0x5 - # 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (This signal may only be toggled after 4 cycles of the - # ld clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.) - # PSU_CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL 0x3 + # 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (T + # his signal may only be toggled after 4 cycles of the old clock and 4 cyc + # les of the new clock. This is not usually an issue, but designers must b + # e aware.) + # PSU_CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL 0x0 # Clock active signal. Switch to 0 to disable the clock # PSU_CRF_APB_DP_VIDEO_REF_CTRL_CLKACT 0x1 # This register controls this reference clock - #(OFFSET, MASK, VALUE) (0XFD1A0070, 0x013F3F07U ,0x01010303U) */ - mask_write 0XFD1A0070 0x013F3F07 0x01010303 + #(OFFSET, MASK, VALUE) (0XFD1A0070, 0x013F3F07U ,0x01010500U) */ + mask_write 0XFD1A0070 0x013F3F07 0x01010500 # Register : DP_AUDIO_REF_CTRL @ 0XFD1A0074

# 6 bit divider # PSU_CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1 0x1 # 6 bit divider - # PSU_CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0 0x27 + # PSU_CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0 0xf - # 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (This signal may only be toggled after 4 cycles of the - # ld clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.) - # PSU_CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL 0x0 + # 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (T + # his signal may only be toggled after 4 cycles of the old clock and 4 cyc + # les of the new clock. This is not usually an issue, but designers must b + # e aware.) + # PSU_CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL 0x3 # Clock active signal. Switch to 0 to disable the clock # PSU_CRF_APB_DP_AUDIO_REF_CTRL_CLKACT 0x1 # This register controls this reference clock - #(OFFSET, MASK, VALUE) (0XFD1A0074, 0x013F3F07U ,0x01012700U) */ - mask_write 0XFD1A0074 0x013F3F07 0x01012700 + #(OFFSET, MASK, VALUE) (0XFD1A0074, 0x013F3F07U ,0x01010F03U) */ + mask_write 0XFD1A0074 0x013F3F07 0x01010F03 # Register : DP_STC_REF_CTRL @ 0XFD1A007C

# 6 bit divider # PSU_CRF_APB_DP_STC_REF_CTRL_DIVISOR1 0x1 # 6 bit divider - # PSU_CRF_APB_DP_STC_REF_CTRL_DIVISOR0 0x11 + # PSU_CRF_APB_DP_STC_REF_CTRL_DIVISOR0 0xe - # 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of t - # e new clock. This is not usually an issue, but designers must be aware.) + # 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD; (This signal may only be togg + # led after 4 cycles of the old clock and 4 cycles of the new clock. This + # is not usually an issue, but designers must be aware.) # PSU_CRF_APB_DP_STC_REF_CTRL_SRCSEL 0x3 # Clock active signal. Switch to 0 to disable the clock # PSU_CRF_APB_DP_STC_REF_CTRL_CLKACT 0x1 # This register controls this reference clock - #(OFFSET, MASK, VALUE) (0XFD1A007C, 0x013F3F07U ,0x01011103U) */ - mask_write 0XFD1A007C 0x013F3F07 0x01011103 + #(OFFSET, MASK, VALUE) (0XFD1A007C, 0x013F3F07U ,0x01010E03U) */ + mask_write 0XFD1A007C 0x013F3F07 0x01010E03 # Register : ACPU_CTRL @ 0XFD1A0060

# 6 bit divider # PSU_CRF_APB_ACPU_CTRL_DIVISOR0 0x1 - # 000 = APLL; 010 = DPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - # lock. This is not usually an issue, but designers must be aware.) + # 000 = APLL; 010 = DPLL; 011 = VPLL; (This signal may only be toggled aft + # er 4 cycles of the old clock and 4 cycles of the new clock. This is not + # usually an issue, but designers must be aware.) # PSU_CRF_APB_ACPU_CTRL_SRCSEL 0x0 - # Clock active signal. Switch to 0 to disable the clock. For the half speed APU Clock + # Clock active signal. Switch to 0 to disable the clock. For the half spee + # d APU Clock # PSU_CRF_APB_ACPU_CTRL_CLKACT_HALF 0x1 - # Clock active signal. Switch to 0 to disable the clock. For the full speed ACPUX Clock. This will shut off the high speed cloc - # to the entire APU + # Clock active signal. Switch to 0 to disable the clock. For the full spee + # d ACPUX Clock. This will shut off the high speed clock to the entire APU # PSU_CRF_APB_ACPU_CTRL_CLKACT_FULL 0x1 # This register controls this reference clock #(OFFSET, MASK, VALUE) (0XFD1A0060, 0x03003F07U ,0x03000100U) */ mask_write 0XFD1A0060 0x03003F07 0x03000100 - # Register : DBG_TRACE_CTRL @ 0XFD1A0064

- - # 6 bit divider - # PSU_CRF_APB_DBG_TRACE_CTRL_DIVISOR0 0x2 - - # 000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of - # he new clock. This is not usually an issue, but designers must be aware.) - # PSU_CRF_APB_DBG_TRACE_CTRL_SRCSEL 0x0 - - # Clock active signal. Switch to 0 to disable the clock - # PSU_CRF_APB_DBG_TRACE_CTRL_CLKACT 0x1 - - # This register controls this reference clock - #(OFFSET, MASK, VALUE) (0XFD1A0064, 0x01003F07U ,0x01000200U) */ - mask_write 0XFD1A0064 0x01003F07 0x01000200 # Register : DBG_FPD_CTRL @ 0XFD1A0068

# 6 bit divider # PSU_CRF_APB_DBG_FPD_CTRL_DIVISOR0 0x2 - # 000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of - # he new clock. This is not usually an issue, but designers must be aware.) + # 000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be tog + # gled after 4 cycles of the old clock and 4 cycles of the new clock. This + # is not usually an issue, but designers must be aware.) # PSU_CRF_APB_DBG_FPD_CTRL_SRCSEL 0x0 # Clock active signal. Switch to 0 to disable the clock @@ -1070,8 +1038,9 @@ set psu_clock_init_data { # 6 bit divider # PSU_CRF_APB_DDR_CTRL_DIVISOR0 0x2 - # 000 = DPLL; 001 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This - # s not usually an issue, but designers must be aware.) + # 000 = DPLL; 001 = VPLL; (This signal may only be toggled after 4 cycles + # of the old clock and 4 cycles of the new clock. This is not usually an i + # ssue, but designers must be aware.) # PSU_CRF_APB_DDR_CTRL_SRCSEL 0x0 # This register controls this reference clock @@ -1082,17 +1051,21 @@ set psu_clock_init_data { # 6 bit divider # PSU_CRF_APB_GPU_REF_CTRL_DIVISOR0 0x1 - # 000 = IOPLL_TO_FPD; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of - # he new clock. This is not usually an issue, but designers must be aware.) + # 000 = IOPLL_TO_FPD; 010 = VPLL; 011 = DPLL; (This signal may only be tog + # gled after 4 cycles of the old clock and 4 cycles of the new clock. This + # is not usually an issue, but designers must be aware.) # PSU_CRF_APB_GPU_REF_CTRL_SRCSEL 0x0 - # Clock active signal. Switch to 0 to disable the clock, which will stop clock for GPU (and both Pixel Processors). + # Clock active signal. Switch to 0 to disable the clock, which will stop c + # lock for GPU (and both Pixel Processors). # PSU_CRF_APB_GPU_REF_CTRL_CLKACT 0x1 - # Clock active signal for Pixel Processor. Switch to 0 to disable the clock only to this Pixel Processor + # Clock active signal for Pixel Processor. Switch to 0 to disable the cloc + # k only to this Pixel Processor # PSU_CRF_APB_GPU_REF_CTRL_PP0_CLKACT 0x1 - # Clock active signal for Pixel Processor. Switch to 0 to disable the clock only to this Pixel Processor + # Clock active signal for Pixel Processor. Switch to 0 to disable the cloc + # k only to this Pixel Processor # PSU_CRF_APB_GPU_REF_CTRL_PP1_CLKACT 0x1 # This register controls this reference clock @@ -1103,8 +1076,9 @@ set psu_clock_init_data { # 6 bit divider # PSU_CRF_APB_GDMA_REF_CTRL_DIVISOR0 0x2 - # 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - # lock. This is not usually an issue, but designers must be aware.) + # 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled aft + # er 4 cycles of the old clock and 4 cycles of the new clock. This is not + # usually an issue, but designers must be aware.) # PSU_CRF_APB_GDMA_REF_CTRL_SRCSEL 0x0 # Clock active signal. Switch to 0 to disable the clock @@ -1118,8 +1092,9 @@ set psu_clock_init_data { # 6 bit divider # PSU_CRF_APB_DPDMA_REF_CTRL_DIVISOR0 0x2 - # 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - # lock. This is not usually an issue, but designers must be aware.) + # 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled aft + # er 4 cycles of the old clock and 4 cycles of the new clock. This is not + # usually an issue, but designers must be aware.) # PSU_CRF_APB_DPDMA_REF_CTRL_SRCSEL 0x0 # Clock active signal. Switch to 0 to disable the clock @@ -1133,23 +1108,25 @@ set psu_clock_init_data { # 6 bit divider # PSU_CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0 0x2 - # 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - # lock. This is not usually an issue, but designers must be aware.) - # PSU_CRF_APB_TOPSW_MAIN_CTRL_SRCSEL 0x2 + # 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled aft + # er 4 cycles of the old clock and 4 cycles of the new clock. This is not + # usually an issue, but designers must be aware.) + # PSU_CRF_APB_TOPSW_MAIN_CTRL_SRCSEL 0x3 # Clock active signal. Switch to 0 to disable the clock # PSU_CRF_APB_TOPSW_MAIN_CTRL_CLKACT 0x1 # This register controls this reference clock - #(OFFSET, MASK, VALUE) (0XFD1A00C0, 0x01003F07U ,0x01000202U) */ - mask_write 0XFD1A00C0 0x01003F07 0x01000202 + #(OFFSET, MASK, VALUE) (0XFD1A00C0, 0x01003F07U ,0x01000203U) */ + mask_write 0XFD1A00C0 0x01003F07 0x01000203 # Register : TOPSW_LSBUS_CTRL @ 0XFD1A00C4

# 6 bit divider # PSU_CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0 0x5 - # 000 = APLL; 010 = IOPLL_TO_FPD; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of - # he new clock. This is not usually an issue, but designers must be aware.) + # 000 = APLL; 010 = IOPLL_TO_FPD; 011 = DPLL; (This signal may only be tog + # gled after 4 cycles of the old clock and 4 cycles of the new clock. This + # is not usually an issue, but designers must be aware.) # PSU_CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL 0x2 # Clock active signal. Switch to 0 to disable the clock @@ -1163,8 +1140,9 @@ set psu_clock_init_data { # 6 bit divider # PSU_CRF_APB_DBG_TSTMP_CTRL_DIVISOR0 0x2 - # 000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of - # he new clock. This is not usually an issue, but designers must be aware.) + # 000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be tog + # gled after 4 cycles of the old clock and 4 cycles of the new clock. This + # is not usually an issue, but designers must be aware.) # PSU_CRF_APB_DBG_TSTMP_CTRL_SRCSEL 0x0 # This register controls this reference clock @@ -1172,20 +1150,24 @@ set psu_clock_init_data { mask_write 0XFD1A00F8 0x00003F07 0x00000200 # Register : IOU_TTC_APB_CLK @ 0XFF180380

- # 00" = Select the APB switch clock for the APB interface of TTC0'01" = Select the PLL ref clock for the APB interface of TTC0' - # 0" = Select the R5 clock for the APB interface of TTC0 + # 00" = Select the APB switch clock for the APB interface of TTC0'01" = Se + # lect the PLL ref clock for the APB interface of TTC0'10" = Select the R5 + # clock for the APB interface of TTC0 # PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL 0 - # 00" = Select the APB switch clock for the APB interface of TTC1'01" = Select the PLL ref clock for the APB interface of TTC1' - # 0" = Select the R5 clock for the APB interface of TTC1 + # 00" = Select the APB switch clock for the APB interface of TTC1'01" = Se + # lect the PLL ref clock for the APB interface of TTC1'10" = Select the R5 + # clock for the APB interface of TTC1 # PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL 0 - # 00" = Select the APB switch clock for the APB interface of TTC2'01" = Select the PLL ref clock for the APB interface of TTC2' - # 0" = Select the R5 clock for the APB interface of TTC2 + # 00" = Select the APB switch clock for the APB interface of TTC2'01" = Se + # lect the PLL ref clock for the APB interface of TTC2'10" = Select the R5 + # clock for the APB interface of TTC2 # PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL 0 - # 00" = Select the APB switch clock for the APB interface of TTC3'01" = Select the PLL ref clock for the APB interface of TTC3' - # 0" = Select the R5 clock for the APB interface of TTC3 + # 00" = Select the APB switch clock for the APB interface of TTC3'01" = Se + # lect the PLL ref clock for the APB interface of TTC3'10" = Select the R5 + # clock for the APB interface of TTC3 # PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL 0 # TTC APB clock select @@ -1193,7 +1175,8 @@ set psu_clock_init_data { mask_write 0XFF180380 0x000000FF 0x00000000 # Register : WDT_CLK_SEL @ 0XFD610100

- # System watchdog timer clock source selection: 0: Internal APB clock 1: External (PL clock via EMIO or Pinout clock via MIO) + # System watchdog timer clock source selection: 0: Internal APB clock 1: E + # xternal (PL clock via EMIO or Pinout clock via MIO) # PSU_FPD_SLCR_WDT_CLK_SEL_SELECT 0 # SWDT clock source select @@ -1201,8 +1184,8 @@ set psu_clock_init_data { mask_write 0XFD610100 0x00000001 0x00000000 # Register : WDT_CLK_SEL @ 0XFF180300

- # System watchdog timer clock source selection: 0: internal clock APB clock 1: external clock from PL via EMIO, or from pinout - # ia MIO + # System watchdog timer clock source selection: 0: internal clock APB cloc + # k 1: external clock from PL via EMIO, or from pinout via MIO # PSU_IOU_SLCR_WDT_CLK_SEL_SELECT 0 # SWDT clock source select @@ -1210,7 +1193,8 @@ set psu_clock_init_data { mask_write 0XFF180300 0x00000001 0x00000000 # Register : CSUPMU_WDT_CLK_SEL @ 0XFF410050

- # System watchdog timer clock source selection: 0: internal clock APB clock 1: external clock pss_ref_clk + # System watchdog timer clock source selection: 0: internal clock APB cloc + # k 1: external clock pss_ref_clk # PSU_LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT 0 # SWDT clock source select @@ -1231,72 +1215,90 @@ set psu_ddr_init_data { mask_write 0XFD1A0108 0x00000008 0x00000008 # Register : MSTR @ 0XFD070000

- # Indicates the configuration of the device used in the system. - 00 - x4 device - 01 - x8 device - 10 - x16 device - 11 - x32 - # evice + # Indicates the configuration of the device used in the system. - 00 - x4 + # device - 01 - x8 device - 10 - x16 device - 11 - x32 device # PSU_DDRC_MSTR_DEVICE_CONFIG 0x1 - # Choose which registers are used. - 0 - Original registers - 1 - Shadow registers + # Choose which registers are used. - 0 - Original registers - 1 - Shadow r + # egisters # PSU_DDRC_MSTR_FREQUENCY_MODE 0x0 - # Only present for multi-rank configurations. Each bit represents one rank. For two-rank configurations, only bits[25:24] are p - # esent. - 1 - populated - 0 - unpopulated LSB is the lowest rank number. For 2 ranks following combinations are legal: - 01 - - # ne rank - 11 - Two ranks - Others - Reserved. For 4 ranks following combinations are legal: - 0001 - One rank - 0011 - Two ra - # ks - 1111 - Four ranks + # Only present for multi-rank configurations. Each bit represents one rank + # . For two-rank configurations, only bits[25:24] are present. - 1 - popul + # ated - 0 - unpopulated LSB is the lowest rank number. For 2 ranks follow + # ing combinations are legal: - 01 - One rank - 11 - Two ranks - Others - + # Reserved. For 4 ranks following combinations are legal: - 0001 - One ran + # k - 0011 - Two ranks - 1111 - Four ranks # PSU_DDRC_MSTR_ACTIVE_RANKS 0x1 - # SDRAM burst length used: - 0001 - Burst length of 2 (only supported for mDDR) - 0010 - Burst length of 4 - 0100 - Burst lengt - # of 8 - 1000 - Burst length of 16 (only supported for mDDR, LPDDR2, and LPDDR4) All other values are reserved. This controls - # he burst size used to access the SDRAM. This must match the burst length mode register setting in the SDRAM. (For BC4/8 on-th - # -fly mode of DDR3 and DDR4, set this field to 0x0100) Burst length of 2 is not supported with AXI ports when MEMC_BURST_LENGT - # is 8. Burst length of 2 is only supported with MEMC_FREQ_RATIO = 1 + # SDRAM burst length used: - 0001 - Burst length of 2 (only supported for + # mDDR) - 0010 - Burst length of 4 - 0100 - Burst length of 8 - 1000 - Bur + # st length of 16 (only supported for mDDR, LPDDR2, and LPDDR4) All other + # values are reserved. This controls the burst size used to access the SDR + # AM. This must match the burst length mode register setting in the SDRAM. + # (For BC4/8 on-the-fly mode of DDR3 and DDR4, set this field to 0x0100) + # Burst length of 2 is not supported with AXI ports when MEMC_BURST_LENGTH + # is 8. Burst length of 2 is only supported with MEMC_FREQ_RATIO = 1 # PSU_DDRC_MSTR_BURST_RDWR 0x4 - # Set to 1 when the uMCTL2 and DRAM has to be put in DLL-off mode for low frequency operation. Set to 0 to put uMCTL2 and DRAM - # n DLL-on mode for normal frequency operation. If DDR4 CRC/parity retry is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), d - # l_off_mode is not supported, and this bit must be set to '0'. + # Set to 1 when the uMCTL2 and DRAM has to be put in DLL-off mode for low + # frequency operation. Set to 0 to put uMCTL2 and DRAM in DLL-on mode for + # normal frequency operation. If DDR4 CRC/parity retry is enabled (CRCPARC + # TL1.crc_parity_retry_enable = 1), dll_off_mode is not supported, and thi + # s bit must be set to '0'. # PSU_DDRC_MSTR_DLL_OFF_MODE 0x0 - # Selects proportion of DQ bus width that is used by the SDRAM - 00 - Full DQ bus width to SDRAM - 01 - Half DQ bus width to SD - # AM - 10 - Quarter DQ bus width to SDRAM - 11 - Reserved. Note that half bus width mode is only supported when the SDRAM bus w - # dth is a multiple of 16, and quarter bus width mode is only supported when the SDRAM bus width is a multiple of 32 and the co - # figuration parameter MEMC_QBUS_SUPPORT is set. Bus width refers to DQ bus width (excluding any ECC width). + # Selects proportion of DQ bus width that is used by the SDRAM - 00 - Full + # DQ bus width to SDRAM - 01 - Half DQ bus width to SDRAM - 10 - Quarter + # DQ bus width to SDRAM - 11 - Reserved. Note that half bus width mode is + # only supported when the SDRAM bus width is a multiple of 16, and quarter + # bus width mode is only supported when the SDRAM bus width is a multiple + # of 32 and the configuration parameter MEMC_QBUS_SUPPORT is set. Bus wid + # th refers to DQ bus width (excluding any ECC width). # PSU_DDRC_MSTR_DATA_BUS_WIDTH 0x0 - # 1 indicates put the DRAM in geardown mode (2N) and 0 indicates put the DRAM in normal mode (1N). This register can be changed - # only when the Controller is in self-refresh mode. This signal must be set the same value as MR3 bit A3. Note: Geardown mode - # s not supported if the configuration parameter MEMC_CMD_RTN2IDLE is set + # 1 indicates put the DRAM in geardown mode (2N) and 0 indicates put the D + # RAM in normal mode (1N). This register can be changed, only when the Con + # troller is in self-refresh mode. This signal must be set the same value + # as MR3 bit A3. Note: Geardown mode is not supported if the configuration + # parameter MEMC_CMD_RTN2IDLE is set # PSU_DDRC_MSTR_GEARDOWN_MODE 0x0 - # If 1, then uMCTL2 uses 2T timing. Otherwise, uses 1T timing. In 2T timing, all command signals (except chip select) are held - # or 2 clocks on the SDRAM bus. Chip select is asserted on the second cycle of the command Note: 2T timing is not supported in - # PDDR2/LPDDR3/LPDDR4 mode Note: 2T timing is not supported if the configuration parameter MEMC_CMD_RTN2IDLE is set Note: 2T ti - # ing is not supported in DDR4 geardown mode. + # If 1, then uMCTL2 uses 2T timing. Otherwise, uses 1T timing. In 2T timin + # g, all command signals (except chip select) are held for 2 clocks on the + # SDRAM bus. Chip select is asserted on the second cycle of the command N + # ote: 2T timing is not supported in LPDDR2/LPDDR3/LPDDR4 mode Note: 2T ti + # ming is not supported if the configuration parameter MEMC_CMD_RTN2IDLE i + # s set Note: 2T timing is not supported in DDR4 geardown mode. # PSU_DDRC_MSTR_EN_2T_TIMING_MODE 0x0 - # When set, enable burst-chop in DDR3/DDR4. Burst Chop for Reads is exercised only in HIF configurations (UMCTL2_INCL_ARB not s - # t) and if in full bus width mode (MSTR.data_bus_width = 00). Burst Chop for Writes is exercised only if Partial Writes enable - # (UMCTL2_PARTIAL_WR=1) and if CRC is disabled (CRCPARCTL1.crc_enable = 0). If DDR4 CRC/parity retry is enabled (CRCPARCTL1.cr - # _parity_retry_enable = 1), burst chop is not supported, and this bit must be set to '0' + # When set, enable burst-chop in DDR3/DDR4. Burst Chop for Reads is exerci + # sed only in HIF configurations (UMCTL2_INCL_ARB not set) and if in full + # bus width mode (MSTR.data_bus_width = 00). Burst Chop for Writes is exer + # cised only if Partial Writes enabled (UMCTL2_PARTIAL_WR=1) and if CRC is + # disabled (CRCPARCTL1.crc_enable = 0). If DDR4 CRC/parity retry is enabl + # ed (CRCPARCTL1.crc_parity_retry_enable = 1), burst chop is not supported + # , and this bit must be set to '0' # PSU_DDRC_MSTR_BURSTCHOP 0x0 - # Select LPDDR4 SDRAM - 1 - LPDDR4 SDRAM device in use. - 0 - non-LPDDR4 device in use Present only in designs configured to su - # port LPDDR4. + # Select LPDDR4 SDRAM - 1 - LPDDR4 SDRAM device in use. - 0 - non-LPDDR4 d + # evice in use Present only in designs configured to support LPDDR4. # PSU_DDRC_MSTR_LPDDR4 0x0 - # Select DDR4 SDRAM - 1 - DDR4 SDRAM device in use. - 0 - non-DDR4 device in use Present only in designs configured to support - # DR4. + # Select DDR4 SDRAM - 1 - DDR4 SDRAM device in use. - 0 - non-DDR4 device + # in use Present only in designs configured to support DDR4. # PSU_DDRC_MSTR_DDR4 0x1 - # Select LPDDR3 SDRAM - 1 - LPDDR3 SDRAM device in use. - 0 - non-LPDDR3 device in use Present only in designs configured to su - # port LPDDR3. + # Select LPDDR3 SDRAM - 1 - LPDDR3 SDRAM device in use. - 0 - non-LPDDR3 d + # evice in use Present only in designs configured to support LPDDR3. # PSU_DDRC_MSTR_LPDDR3 0x0 - # Select LPDDR2 SDRAM - 1 - LPDDR2 SDRAM device in use. - 0 - non-LPDDR2 device in use Present only in designs configured to su - # port LPDDR2. + # Select LPDDR2 SDRAM - 1 - LPDDR2 SDRAM device in use. - 0 - non-LPDDR2 d + # evice in use Present only in designs configured to support LPDDR2. # PSU_DDRC_MSTR_LPDDR2 0x0 - # Select DDR3 SDRAM - 1 - DDR3 SDRAM device in use - 0 - non-DDR3 SDRAM device in use Only present in designs that support DDR3 - # + # Select DDR3 SDRAM - 1 - DDR3 SDRAM device in use - 0 - non-DDR3 SDRAM de + # vice in use Only present in designs that support DDR3. # PSU_DDRC_MSTR_DDR3 0x0 # Master Register @@ -1304,74 +1306,97 @@ set psu_ddr_init_data { mask_write 0XFD070000 0xE30FBE3D 0x41040010 # Register : MRCTRL0 @ 0XFD070010

- # Setting this register bit to 1 triggers a mode register read or write operation. When the MR operation is complete, the uMCTL - # automatically clears this bit. The other register fields of this register must be written in a separate APB transaction, bef - # re setting this mr_wr bit. It is recommended NOT to set this signal if in Init, Deep power-down or MPSM operating modes. + # Setting this register bit to 1 triggers a mode register read or write op + # eration. When the MR operation is complete, the uMCTL2 automatically cle + # ars this bit. The other register fields of this register must be written + # in a separate APB transaction, before setting this mr_wr bit. It is rec + # ommended NOT to set this signal if in Init, Deep power-down or MPSM oper + # ating modes. # PSU_DDRC_MRCTRL0_MR_WR 0x0 - # Address of the mode register that is to be written to. - 0000 - MR0 - 0001 - MR1 - 0010 - MR2 - 0011 - MR3 - 0100 - MR4 - 010 - # - MR5 - 0110 - MR6 - 0111 - MR7 Don't Care for LPDDR2/LPDDR3/LPDDR4 (see MRCTRL1.mr_data for mode register addressing in LPD - # R2/LPDDR3/LPDDR4) This signal is also used for writing to control words of RDIMMs. In that case, it corresponds to the bank a - # dress bits sent to the RDIMM In case of DDR4, the bit[3:2] corresponds to the bank group bits. Therefore, the bit[3] as well - # s the bit[2:0] must be set to an appropriate value which is considered both the Address Mirroring of UDIMMs/RDIMMs and the Ou - # put Inversion of RDIMMs. + # Address of the mode register that is to be written to. - 0000 - MR0 - 00 + # 01 - MR1 - 0010 - MR2 - 0011 - MR3 - 0100 - MR4 - 0101 - MR5 - 0110 - MR + # 6 - 0111 - MR7 Don't Care for LPDDR2/LPDDR3/LPDDR4 (see MRCTRL1.mr_data + # for mode register addressing in LPDDR2/LPDDR3/LPDDR4) This signal is als + # o used for writing to control words of RDIMMs. In that case, it correspo + # nds to the bank address bits sent to the RDIMM In case of DDR4, the bit[ + # 3:2] corresponds to the bank group bits. Therefore, the bit[3] as well a + # s the bit[2:0] must be set to an appropriate value which is considered b + # oth the Address Mirroring of UDIMMs/RDIMMs and the Output Inversion of R + # DIMMs. # PSU_DDRC_MRCTRL0_MR_ADDR 0x0 - # Controls which rank is accessed by MRCTRL0.mr_wr. Normally, it is desired to access all ranks, so all bits should be set to 1 - # However, for multi-rank UDIMMs/RDIMMs which implement address mirroring, it may be necessary to access ranks individually. E - # amples (assume uMCTL2 is configured for 4 ranks): - 0x1 - select rank 0 only - 0x2 - select rank 1 only - 0x5 - select ranks - # and 2 - 0xA - select ranks 1 and 3 - 0xF - select ranks 0, 1, 2 and 3 + # Controls which rank is accessed by MRCTRL0.mr_wr. Normally, it is desire + # d to access all ranks, so all bits should be set to 1. However, for mult + # i-rank UDIMMs/RDIMMs which implement address mirroring, it may be necess + # ary to access ranks individually. Examples (assume uMCTL2 is configured + # for 4 ranks): - 0x1 - select rank 0 only - 0x2 - select rank 1 only - 0x + # 5 - select ranks 0 and 2 - 0xA - select ranks 1 and 3 - 0xF - select ran + # ks 0, 1, 2 and 3 # PSU_DDRC_MRCTRL0_MR_RANK 0x3 - # Indicates whether Software intervention is allowed via MRCTRL0/MRCTRL1 before automatic SDRAM initialization routine or not. - # or DDR4, this bit can be used to initialize the DDR4 RCD (MR7) before automatic SDRAM initialization. For LPDDR4, this bit ca - # be used to program additional mode registers before automatic SDRAM initialization if necessary. Note: This must be cleared - # o 0 after completing Software operation. Otherwise, SDRAM initialization routine will not re-start. - 0 - Software interventi - # n is not allowed - 1 - Software intervention is allowed + # Indicates whether Software intervention is allowed via MRCTRL0/MRCTRL1 b + # efore automatic SDRAM initialization routine or not. For DDR4, this bit + # can be used to initialize the DDR4 RCD (MR7) before automatic SDRAM init + # ialization. For LPDDR4, this bit can be used to program additional mode + # registers before automatic SDRAM initialization if necessary. Note: This + # must be cleared to 0 after completing Software operation. Otherwise, SD + # RAM initialization routine will not re-start. - 0 - Software interventio + # n is not allowed - 1 - Software intervention is allowed # PSU_DDRC_MRCTRL0_SW_INIT_INT 0x0 - # Indicates whether the mode register operation is MRS in PDA mode or not - 0 - MRS - 1 - MRS in Per DRAM Addressability mode + # Indicates whether the mode register operation is MRS in PDA mode or not + # - 0 - MRS - 1 - MRS in Per DRAM Addressability mode # PSU_DDRC_MRCTRL0_PDA_EN 0x0 - # Indicates whether the mode register operation is MRS or WR/RD for MPR (only supported for DDR4) - 0 - MRS - 1 - WR/RD for MPR + # Indicates whether the mode register operation is MRS or WR/RD for MPR (o + # nly supported for DDR4) - 0 - MRS - 1 - WR/RD for MPR # PSU_DDRC_MRCTRL0_MPR_EN 0x0 - # Indicates whether the mode register operation is read or write. Only used for LPDDR2/LPDDR3/LPDDR4/DDR4. - 0 - Write - 1 - Re - # d + # Indicates whether the mode register operation is read or write. Only use + # d for LPDDR2/LPDDR3/LPDDR4/DDR4. - 0 - Write - 1 - Read # PSU_DDRC_MRCTRL0_MR_TYPE 0x0 - # Mode Register Read/Write Control Register 0. Note: Do not enable more than one of the following fields simultaneously: - sw_i - # it_int - pda_en - mpr_en + # Mode Register Read/Write Control Register 0. Note: Do not enable more th + # an one of the following fields simultaneously: - sw_init_int - pda_en - + # mpr_en #(OFFSET, MASK, VALUE) (0XFD070010, 0x8000F03FU ,0x00000030U) */ mask_write 0XFD070010 0x8000F03F 0x00000030 # Register : DERATEEN @ 0XFD070020

- # Derate value of tRC for LPDDR4 - 0 - Derating uses +1. - 1 - Derating uses +2. - 2 - Derating uses +3. - 3 - Derating uses +4 - # Present only in designs configured to support LPDDR4. The required number of cycles for derating can be determined by dividi - # g 3.75ns by the core_ddrc_core_clk period, and rounding up the next integer. - # PSU_DDRC_DERATEEN_RC_DERATE_VALUE 0x3 + # Derate value of tRC for LPDDR4 - 0 - Derating uses +1. - 1 - Derating us + # es +2. - 2 - Derating uses +3. - 3 - Derating uses +4. Present only in d + # esigns configured to support LPDDR4. The required number of cycles for d + # erating can be determined by dividing 3.75ns by the core_ddrc_core_clk p + # eriod, and rounding up the next integer. + # PSU_DDRC_DERATEEN_RC_DERATE_VALUE 0x2 - # Derate byte Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4 Indicates which byte of the MRR data is used f - # r derating. The maximum valid value depends on MEMC_DRAM_TOTAL_DATA_WIDTH. + # Derate byte Present only in designs configured to support LPDDR2/LPDDR3/ + # LPDDR4 Indicates which byte of the MRR data is used for derating. The ma + # ximum valid value depends on MEMC_DRAM_TOTAL_DATA_WIDTH. # PSU_DDRC_DERATEEN_DERATE_BYTE 0x0 - # Derate value - 0 - Derating uses +1. - 1 - Derating uses +2. Present only in designs configured to support LPDDR2/LPDDR3/LPDD - # 4 Set to 0 for all LPDDR2 speed grades as derating value of +1.875 ns is less than a core_ddrc_core_clk period. Can be 0 or 1 - # for LPDDR3/LPDDR4, depending if +1.875 ns is less than a core_ddrc_core_clk period or not. + # Derate value - 0 - Derating uses +1. - 1 - Derating uses +2. Present onl + # y in designs configured to support LPDDR2/LPDDR3/LPDDR4 Set to 0 for all + # LPDDR2 speed grades as derating value of +1.875 ns is less than a core_ + # ddrc_core_clk period. Can be 0 or 1 for LPDDR3/LPDDR4, depending if +1.8 + # 75 ns is less than a core_ddrc_core_clk period or not. # PSU_DDRC_DERATEEN_DERATE_VALUE 0x0 - # Enables derating - 0 - Timing parameter derating is disabled - 1 - Timing parameter derating is enabled using MR4 read value. - # Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4 This field must be set to '0' for non-LPDDR2/LPDDR3/LPDDR4 - # mode. + # Enables derating - 0 - Timing parameter derating is disabled - 1 - Timin + # g parameter derating is enabled using MR4 read value. Present only in de + # signs configured to support LPDDR2/LPDDR3/LPDDR4 This field must be set + # to '0' for non-LPDDR2/LPDDR3/LPDDR4 mode. # PSU_DDRC_DERATEEN_DERATE_ENABLE 0x0 # Temperature Derate Enable Register - #(OFFSET, MASK, VALUE) (0XFD070020, 0x000003F3U ,0x00000300U) */ - mask_write 0XFD070020 0x000003F3 0x00000300 + #(OFFSET, MASK, VALUE) (0XFD070020, 0x000003F3U ,0x00000200U) */ + mask_write 0XFD070020 0x000003F3 0x00000200 # Register : DERATEINT @ 0XFD070024

- # Interval between two MR4 reads, used to derate the timing parameters. Present only in designs configured to support LPDDR2/LP - # DR3/LPDDR4. This register must not be set to zero + # Interval between two MR4 reads, used to derate the timing parameters. Pr + # esent only in designs configured to support LPDDR2/LPDDR3/LPDDR4. This r + # egister must not be set to zero # PSU_DDRC_DERATEINT_MR4_READ_INTERVAL 0x800000 # Temperature Derate Interval Register @@ -1379,41 +1404,57 @@ set psu_ddr_init_data { mask_write 0XFD070024 0xFFFFFFFF 0x00800000 # Register : PWRCTL @ 0XFD070030

- # Self refresh state is an intermediate state to enter to Self refresh power down state or exit Self refresh power down state f - # r LPDDR4. This register controls transition from the Self refresh state. - 1 - Prohibit transition from Self refresh state - - # - Allow transition from Self refresh state + # Self refresh state is an intermediate state to enter to Self refresh pow + # er down state or exit Self refresh power down state for LPDDR4. This reg + # ister controls transition from the Self refresh state. - 1 - Prohibit tr + # ansition from Self refresh state - 0 - Allow transition from Self refres + # h state # PSU_DDRC_PWRCTL_STAY_IN_SELFREF 0x0 - # A value of 1 to this register causes system to move to Self Refresh state immediately, as long as it is not in INIT or DPD/MP - # M operating_mode. This is referred to as Software Entry/Exit to Self Refresh. - 1 - Software Entry to Self Refresh - 0 - Soft - # are Exit from Self Refresh + # A value of 1 to this register causes system to move to Self Refresh stat + # e immediately, as long as it is not in INIT or DPD/MPSM operating_mode. + # This is referred to as Software Entry/Exit to Self Refresh. - 1 - Softwa + # re Entry to Self Refresh - 0 - Software Exit from Self Refresh # PSU_DDRC_PWRCTL_SELFREF_SW 0x0 - # When this is 1, the uMCTL2 puts the SDRAM into maximum power saving mode when the transaction store is empty. This register m - # st be reset to '0' to bring uMCTL2 out of maximum power saving mode. Present only in designs configured to support DDR4. For - # on-DDR4, this register should not be set to 1. Note that MPSM is not supported when using a DWC DDR PHY, if the PHY parameter - # DWC_AC_CS_USE is disabled, as the MPSM exit sequence requires the chip-select signal to toggle. FOR PERFORMANCE ONLY. + # When this is 1, the uMCTL2 puts the SDRAM into maximum power saving mode + # when the transaction store is empty. This register must be reset to '0' + # to bring uMCTL2 out of maximum power saving mode. Present only in desig + # ns configured to support DDR4. For non-DDR4, this register should not be + # set to 1. Note that MPSM is not supported when using a DWC DDR PHY, if + # the PHY parameter DWC_AC_CS_USE is disabled, as the MPSM exit sequence r + # equires the chip-select signal to toggle. FOR PERFORMANCE ONLY. # PSU_DDRC_PWRCTL_MPSM_EN 0x0 - # Enable the assertion of dfi_dram_clk_disable whenever a clock is not required by the SDRAM. If set to 0, dfi_dram_clk_disable - # is never asserted. Assertion of dfi_dram_clk_disable is as follows: In DDR2/DDR3, can only be asserted in Self Refresh. In DD - # 4, can be asserted in following: - in Self Refresh. - in Maximum Power Saving Mode In mDDR/LPDDR2/LPDDR3, can be asserted in - # ollowing: - in Self Refresh - in Power Down - in Deep Power Down - during Normal operation (Clock Stop) In LPDDR4, can be ass - # rted in following: - in Self Refresh Power Down - in Power Down - during Normal operation (Clock Stop) + # Enable the assertion of dfi_dram_clk_disable whenever a clock is not req + # uired by the SDRAM. If set to 0, dfi_dram_clk_disable is never asserted. + # Assertion of dfi_dram_clk_disable is as follows: In DDR2/DDR3, can only + # be asserted in Self Refresh. In DDR4, can be asserted in following: - i + # n Self Refresh. - in Maximum Power Saving Mode In mDDR/LPDDR2/LPDDR3, ca + # n be asserted in following: - in Self Refresh - in Power Down - in Deep + # Power Down - during Normal operation (Clock Stop) In LPDDR4, can be asse + # rted in following: - in Self Refresh Power Down - in Power Down - during + # Normal operation (Clock Stop) # PSU_DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE 0x0 - # When this is 1, uMCTL2 puts the SDRAM into deep power-down mode when the transaction store is empty. This register must be re - # et to '0' to bring uMCTL2 out of deep power-down mode. Controller performs automatic SDRAM initialization on deep power-down - # xit. Present only in designs configured to support mDDR or LPDDR2 or LPDDR3. For non-mDDR/non-LPDDR2/non-LPDDR3, this registe - # should not be set to 1. FOR PERFORMANCE ONLY. + # When this is 1, uMCTL2 puts the SDRAM into deep power-down mode when the + # transaction store is empty. This register must be reset to '0' to bring + # uMCTL2 out of deep power-down mode. Controller performs automatic SDRAM + # initialization on deep power-down exit. Present only in designs configu + # red to support mDDR or LPDDR2 or LPDDR3. For non-mDDR/non-LPDDR2/non-LPD + # DR3, this register should not be set to 1. FOR PERFORMANCE ONLY. # PSU_DDRC_PWRCTL_DEEPPOWERDOWN_EN 0x0 - # If true then the uMCTL2 goes into power-down after a programmable number of cycles 'maximum idle clocks before power down' (P - # RTMG.powerdown_to_x32). This register bit may be re-programmed during the course of normal operation. + # If true then the uMCTL2 goes into power-down after a programmable number + # of cycles 'maximum idle clocks before power down' (PWRTMG.powerdown_to_ + # x32). This register bit may be re-programmed during the course of normal + # operation. # PSU_DDRC_PWRCTL_POWERDOWN_EN 0x0 - # If true then the uMCTL2 puts the SDRAM into Self Refresh after a programmable number of cycles 'maximum idle clocks before Se - # f Refresh (PWRTMG.selfref_to_x32)'. This register bit may be re-programmed during the course of normal operation. + # If true then the uMCTL2 puts the SDRAM into Self Refresh after a program + # mable number of cycles 'maximum idle clocks before Self Refresh (PWRTMG. + # selfref_to_x32)'. This register bit may be re-programmed during the cour + # se of normal operation. # PSU_DDRC_PWRCTL_SELFREF_EN 0x0 # Low Power Control Register @@ -1421,17 +1462,22 @@ set psu_ddr_init_data { mask_write 0XFD070030 0x0000007F 0x00000000 # Register : PWRTMG @ 0XFD070034

- # After this many clocks of NOP or deselect the uMCTL2 automatically puts the SDRAM into Self Refresh. This must be enabled in - # he PWRCTL.selfref_en. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY. + # After this many clocks of NOP or deselect the uMCTL2 automatically puts + # the SDRAM into Self Refresh. This must be enabled in the PWRCTL.selfref_ + # en. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY. # PSU_DDRC_PWRTMG_SELFREF_TO_X32 0x40 - # Minimum deep power-down time. For mDDR, value from the JEDEC specification is 0 as mDDR exits from deep power-down mode immed - # ately after PWRCTL.deeppowerdown_en is de-asserted. For LPDDR2/LPDDR3, value from the JEDEC specification is 500us. Unit: Mul - # iples of 4096 clocks. Present only in designs configured to support mDDR, LPDDR2 or LPDDR3. FOR PERFORMANCE ONLY. + # Minimum deep power-down time. For mDDR, value from the JEDEC specificati + # on is 0 as mDDR exits from deep power-down mode immediately after PWRCTL + # .deeppowerdown_en is de-asserted. For LPDDR2/LPDDR3, value from the JEDE + # C specification is 500us. Unit: Multiples of 4096 clocks. Present only i + # n designs configured to support mDDR, LPDDR2 or LPDDR3. FOR PERFORMANCE + # ONLY. # PSU_DDRC_PWRTMG_T_DPD_X4096 0x84 - # After this many clocks of NOP or deselect the uMCTL2 automatically puts the SDRAM into power-down. This must be enabled in th - # PWRCTL.powerdown_en. Unit: Multiples of 32 clocks FOR PERFORMANCE ONLY. + # After this many clocks of NOP or deselect the uMCTL2 automatically puts + # the SDRAM into power-down. This must be enabled in the PWRCTL.powerdown_ + # en. Unit: Multiples of 32 clocks FOR PERFORMANCE ONLY. # PSU_DDRC_PWRTMG_POWERDOWN_TO_X32 0x10 # Low Power Timing Register @@ -1439,60 +1485,100 @@ set psu_ddr_init_data { mask_write 0XFD070034 0x00FFFF1F 0x00408410 # Register : RFSHCTL0 @ 0XFD070050

- # Threshold value in number of clock cycles before the critical refresh or page timer expires. A critical refresh is to be issu - # d before this threshold is reached. It is recommended that this not be changed from the default value, currently shown as 0x2 - # It must always be less than internally used t_rfc_nom_x32. Note that, in LPDDR2/LPDDR3/LPDDR4, internally used t_rfc_nom_x32 - # may be equal to RFSHTMG.t_rfc_nom_x32>>2 if derating is enabled (DERATEEN.derate_enable=1). Otherwise, internally used t_rfc_ - # om_x32 will be equal to RFSHTMG.t_rfc_nom_x32. Unit: Multiples of 32 clocks. + # Threshold value in number of clock cycles before the critical refresh or + # page timer expires. A critical refresh is to be issued before this thre + # shold is reached. It is recommended that this not be changed from the de + # fault value, currently shown as 0x2. It must always be less than interna + # lly used t_rfc_nom_x32. Note that, in LPDDR2/LPDDR3/LPDDR4, internally u + # sed t_rfc_nom_x32 may be equal to RFSHTMG.t_rfc_nom_x32>>2 if derating i + # s enabled (DERATEEN.derate_enable=1). Otherwise, internally used t_rfc_n + # om_x32 will be equal to RFSHTMG.t_rfc_nom_x32. Unit: Multiples of 32 clo + # cks. # PSU_DDRC_RFSHCTL0_REFRESH_MARGIN 0x2 - # If the refresh timer (tRFCnom, also known as tREFI) has expired at least once, but it has not expired (RFSHCTL0.refresh_burst - # 1) times yet, then a speculative refresh may be performed. A speculative refresh is a refresh performed at a time when refres - # would be useful, but before it is absolutely required. When the SDRAM bus is idle for a period of time determined by this RF - # HCTL0.refresh_to_x32 and the refresh timer has expired at least once since the last refresh, then a speculative refresh is pe - # formed. Speculative refreshes continues successively until there are no refreshes pending or until new reads or writes are is - # ued to the uMCTL2. FOR PERFORMANCE ONLY. + # If the refresh timer (tRFCnom, also known as tREFI) has expired at least + # once, but it has not expired (RFSHCTL0.refresh_burst+1) times yet, then + # a speculative refresh may be performed. A speculative refresh is a refr + # esh performed at a time when refresh would be useful, but before it is a + # bsolutely required. When the SDRAM bus is idle for a period of time dete + # rmined by this RFSHCTL0.refresh_to_x32 and the refresh timer has expired + # at least once since the last refresh, then a speculative refresh is per + # formed. Speculative refreshes continues successively until there are no + # refreshes pending or until new reads or writes are issued to the uMCTL2. + # FOR PERFORMANCE ONLY. # PSU_DDRC_RFSHCTL0_REFRESH_TO_X32 0x10 - # The programmed value + 1 is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the re - # reshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of re - # reshes. Therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for - # RFSHCTL.refresh_burst slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshe - # . - 0 - single refresh - 1 - burst-of-2 refresh - 7 - burst-of-8 refresh For information on burst refresh feature refer to se - # tion 3.9 of DDR2 JEDEC specification - JESD79-2F.pdf. For DDR2/3, the refresh is always per-rank and not per-bank. The rank r - # fresh can be accumulated over 8*tREFI cycles using the burst refresh feature. In DDR4 mode, according to Fine Granularity fea - # ure, 8 refreshes can be postponed in 1X mode, 16 refreshes in 2X mode and 32 refreshes in 4X mode. If using PHY-initiated upd - # tes, care must be taken in the setting of RFSHCTL0.refresh_burst, to ensure that tRFCmax is not violated due to a PHY-initiat - # d update occurring shortly before a refresh burst was due. In this situation, the refresh burst will be delayed until the PHY - # initiated update is complete. + # The programmed value + 1 is the number of refresh timeouts that is allow + # ed to accumulate before traffic is blocked and the refreshes are forced + # to execute. Closing pages to perform a refresh is a one-time penalty tha + # t must be paid for each group of refreshes. Therefore, performing refres + # hes in a burst reduces the per-refresh penalty of these page closings. H + # igher numbers for RFSHCTL.refresh_burst slightly increases utilization; + # lower numbers decreases the worst-case latency associated with refreshes + # . - 0 - single refresh - 1 - burst-of-2 refresh - 7 - burst-of-8 refresh + # For information on burst refresh feature refer to section 3.9 of DDR2 J + # EDEC specification - JESD79-2F.pdf. For DDR2/3, the refresh is always pe + # r-rank and not per-bank. The rank refresh can be accumulated over 8*tREF + # I cycles using the burst refresh feature. In DDR4 mode, according to Fin + # e Granularity feature, 8 refreshes can be postponed in 1X mode, 16 refre + # shes in 2X mode and 32 refreshes in 4X mode. If using PHY-initiated upda + # tes, care must be taken in the setting of RFSHCTL0.refresh_burst, to ens + # ure that tRFCmax is not violated due to a PHY-initiated update occurring + # shortly before a refresh burst was due. In this situation, the refresh + # burst will be delayed until the PHY-initiated update is complete. # PSU_DDRC_RFSHCTL0_REFRESH_BURST 0x0 - # - 1 - Per bank refresh; - 0 - All bank refresh. Per bank refresh allows traffic to flow to other banks. Per bank refresh is n - # t supported by all LPDDR2 devices but should be supported by all LPDDR3/LPDDR4 devices. Present only in designs configured to - # support LPDDR2/LPDDR3/LPDDR4 + # - 1 - Per bank refresh; - 0 - All bank refresh. Per bank refresh allows + # traffic to flow to other banks. Per bank refresh is not supported by all + # LPDDR2 devices but should be supported by all LPDDR3/LPDDR4 devices. Pr + # esent only in designs configured to support LPDDR2/LPDDR3/LPDDR4 # PSU_DDRC_RFSHCTL0_PER_BANK_REFRESH 0x0 # Refresh Control Register 0 #(OFFSET, MASK, VALUE) (0XFD070050, 0x00F1F1F4U ,0x00210000U) */ mask_write 0XFD070050 0x00F1F1F4 0x00210000 + # Register : RFSHCTL1 @ 0XFD070054

+ + # Refresh timer start for rank 1 (only present in multi-rank configuration + # s). This is useful in staggering the refreshes to multiple ranks to help + # traffic to proceed. This is explained in Refresh Controls section of ar + # chitecture chapter. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY. + # PSU_DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32 0x0 + + # Refresh timer start for rank 0 (only present in multi-rank configuration + # s). This is useful in staggering the refreshes to multiple ranks to help + # traffic to proceed. This is explained in Refresh Controls section of ar + # chitecture chapter. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY. + # PSU_DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32 0x0 + + # Refresh Control Register 1 + #(OFFSET, MASK, VALUE) (0XFD070054, 0x0FFF0FFFU ,0x00000000U) */ + mask_write 0XFD070054 0x0FFF0FFF 0x00000000 # Register : RFSHCTL3 @ 0XFD070060

- # Fine Granularity Refresh Mode - 000 - Fixed 1x (Normal mode) - 001 - Fixed 2x - 010 - Fixed 4x - 101 - Enable on the fly 2x ( - # ot supported) - 110 - Enable on the fly 4x (not supported) - Everything else - reserved Note: The on-the-fly modes is not sup - # orted in this version of the uMCTL2. Note: This must be set up while the Controller is in reset or while the Controller is in - # self-refresh mode. Changing this during normal operation is not allowed. Making this a dynamic register will be supported in - # uture version of the uMCTL2. + # Fine Granularity Refresh Mode - 000 - Fixed 1x (Normal mode) - 001 - Fix + # ed 2x - 010 - Fixed 4x - 101 - Enable on the fly 2x (not supported) - 11 + # 0 - Enable on the fly 4x (not supported) - Everything else - reserved No + # te: The on-the-fly modes is not supported in this version of the uMCTL2. + # Note: This must be set up while the Controller is in reset or while the + # Controller is in self-refresh mode. Changing this during normal operati + # on is not allowed. Making this a dynamic register will be supported in f + # uture version of the uMCTL2. # PSU_DDRC_RFSHCTL3_REFRESH_MODE 0x0 - # Toggle this signal (either from 0 to 1 or from 1 to 0) to indicate that the refresh register(s) have been updated. The value - # s automatically updated when exiting reset, so it does not need to be toggled initially. + # Toggle this signal (either from 0 to 1 or from 1 to 0) to indicate that + # the refresh register(s) have been updated. The value is automatically up + # dated when exiting reset, so it does not need to be toggled initially. # PSU_DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL 0x0 - # When '1', disable auto-refresh generated by the uMCTL2. When auto-refresh is disabled, the SoC core must generate refreshes u - # ing the registers reg_ddrc_rank0_refresh, reg_ddrc_rank1_refresh, reg_ddrc_rank2_refresh and reg_ddrc_rank3_refresh. When dis - # auto_refresh transitions from 0 to 1, any pending refreshes are immediately scheduled by the uMCTL2. If DDR4 CRC/parity retry - # is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), disable auto-refresh is not supported, and this bit must be set to '0'. - # his register field is changeable on the fly. + # When '1', disable auto-refresh generated by the uMCTL2. When auto-refres + # h is disabled, the SoC core must generate refreshes using the registers + # reg_ddrc_rank0_refresh, reg_ddrc_rank1_refresh, reg_ddrc_rank2_refresh a + # nd reg_ddrc_rank3_refresh. When dis_auto_refresh transitions from 0 to 1 + # , any pending refreshes are immediately scheduled by the uMCTL2. If DDR4 + # CRC/parity retry is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), d + # isable auto-refresh is not supported, and this bit must be set to '0'. T + # his register field is changeable on the fly. # PSU_DDRC_RFSHCTL3_DIS_AUTO_REFRESH 0x1 # Refresh Control Register 3 @@ -1500,38 +1586,51 @@ set psu_ddr_init_data { mask_write 0XFD070060 0x00000073 0x00000001 # Register : RFSHTMG @ 0XFD070064

- # tREFI: Average time interval between refreshes per rank (Specification: 7.8us for DDR2, DDR3 and DDR4. See JEDEC specificatio - # for mDDR, LPDDR2, LPDDR3 and LPDDR4). For LPDDR2/LPDDR3/LPDDR4: - if using all-bank refreshes (RFSHCTL0.per_bank_refresh = 0 - # , this register should be set to tREFIab - if using per-bank refreshes (RFSHCTL0.per_bank_refresh = 1), this register should - # e set to tREFIpb For configurations with MEMC_FREQ_RATIO=2, program this to (tREFI/2), no rounding up. In DDR4 mode, tREFI va - # ue is different depending on the refresh mode. The user should program the appropriate value from the spec based on the value - # programmed in the refresh mode register. Note that RFSHTMG.t_rfc_nom_x32 * 32 must be greater than RFSHTMG.t_rfc_min, and RFS - # TMG.t_rfc_nom_x32 must be greater than 0x1. Unit: Multiples of 32 clocks. - # PSU_DDRC_RFSHTMG_T_RFC_NOM_X32 0x82 + # tREFI: Average time interval between refreshes per rank (Specification: + # 7.8us for DDR2, DDR3 and DDR4. See JEDEC specification for mDDR, LPDDR2, + # LPDDR3 and LPDDR4). For LPDDR2/LPDDR3/LPDDR4: - if using all-bank refre + # shes (RFSHCTL0.per_bank_refresh = 0), this register should be set to tRE + # FIab - if using per-bank refreshes (RFSHCTL0.per_bank_refresh = 1), this + # register should be set to tREFIpb For configurations with MEMC_FREQ_RAT + # IO=2, program this to (tREFI/2), no rounding up. In DDR4 mode, tREFI val + # ue is different depending on the refresh mode. The user should program t + # he appropriate value from the spec based on the value programmed in the + # refresh mode register. Note that RFSHTMG.t_rfc_nom_x32 * 32 must be grea + # ter than RFSHTMG.t_rfc_min, and RFSHTMG.t_rfc_nom_x32 must be greater th + # an 0x1. Unit: Multiples of 32 clocks. + # PSU_DDRC_RFSHTMG_T_RFC_NOM_X32 0x81 - # Used only when LPDDR3 memory type is connected. Should only be changed when uMCTL2 is in reset. Specifies whether to use the - # REFBW parameter (required by some LPDDR3 devices which comply with earlier versions of the LPDDR3 JEDEC specification) or not - # - 0 - tREFBW parameter not used - 1 - tREFBW parameter used + # Used only when LPDDR3 memory type is connected. Should only be changed w + # hen uMCTL2 is in reset. Specifies whether to use the tREFBW parameter (r + # equired by some LPDDR3 devices which comply with earlier versions of the + # LPDDR3 JEDEC specification) or not: - 0 - tREFBW parameter not used - 1 + # - tREFBW parameter used # PSU_DDRC_RFSHTMG_LPDDR3_TREFBW_EN 0x1 - # tRFC (min): Minimum time from refresh to refresh or activate. For MEMC_FREQ_RATIO=1 configurations, t_rfc_min should be set t - # RoundUp(tRFCmin/tCK). For MEMC_FREQ_RATIO=2 configurations, t_rfc_min should be set to RoundUp(RoundUp(tRFCmin/tCK)/2). In L - # DDR2/LPDDR3/LPDDR4 mode: - if using all-bank refreshes, the tRFCmin value in the above equations is equal to tRFCab - if usin - # per-bank refreshes, the tRFCmin value in the above equations is equal to tRFCpb In DDR4 mode, the tRFCmin value in the above - # equations is different depending on the refresh mode (fixed 1X,2X,4X) and the device density. The user should program the app - # opriate value from the spec based on the 'refresh_mode' and the device density that is used. Unit: Clocks. + # tRFC (min): Minimum time from refresh to refresh or activate. For MEMC_F + # REQ_RATIO=1 configurations, t_rfc_min should be set to RoundUp(tRFCmin/t + # CK). For MEMC_FREQ_RATIO=2 configurations, t_rfc_min should be set to Ro + # undUp(RoundUp(tRFCmin/tCK)/2). In LPDDR2/LPDDR3/LPDDR4 mode: - if using + # all-bank refreshes, the tRFCmin value in the above equations is equal to + # tRFCab - if using per-bank refreshes, the tRFCmin value in the above eq + # uations is equal to tRFCpb In DDR4 mode, the tRFCmin value in the above + # equations is different depending on the refresh mode (fixed 1X,2X,4X) an + # d the device density. The user should program the appropriate value from + # the spec based on the 'refresh_mode' and the device density that is use + # d. Unit: Clocks. # PSU_DDRC_RFSHTMG_T_RFC_MIN 0x8b # Refresh Timing Register - #(OFFSET, MASK, VALUE) (0XFD070064, 0x0FFF83FFU ,0x0082808BU) */ - mask_write 0XFD070064 0x0FFF83FF 0x0082808B + #(OFFSET, MASK, VALUE) (0XFD070064, 0x0FFF83FFU ,0x0081808BU) */ + mask_write 0XFD070064 0x0FFF83FF 0x0081808B # Register : ECCCFG0 @ 0XFD070070

- # Disable ECC scrubs. Valid only when ECCCFG0.ecc_mode = 3'b100 and MEMC_USE_RMW is defined + # Disable ECC scrubs. Valid only when ECCCFG0.ecc_mode = 3'b100 and MEMC_U + # SE_RMW is defined # PSU_DDRC_ECCCFG0_DIS_SCRUB 0x1 - # ECC mode indicator - 000 - ECC disabled - 100 - ECC enabled - SEC/DED over 1 beat - all other settings are reserved for futur - # use + # ECC mode indicator - 000 - ECC disabled - 100 - ECC enabled - SEC/DED ov + # er 1 beat - all other settings are reserved for future use # PSU_DDRC_ECCCFG0_ECC_MODE 0x0 # ECC Configuration Register 0 @@ -1539,11 +1638,13 @@ set psu_ddr_init_data { mask_write 0XFD070070 0x00000017 0x00000010 # Register : ECCCFG1 @ 0XFD070074

- # Selects whether to poison 1 or 2 bits - if 0 -> 2-bit (uncorrectable) data poisoning, if 1 -> 1-bit (correctable) data poison - # ng, if ECCCFG1.data_poison_en=1 + # Selects whether to poison 1 or 2 bits - if 0 -> 2-bit (uncorrectable) da + # ta poisoning, if 1 -> 1-bit (correctable) data poisoning, if ECCCFG1.dat + # a_poison_en=1 # PSU_DDRC_ECCCFG1_DATA_POISON_BIT 0x0 - # Enable ECC data poisoning - introduces ECC errors on writes to address specified by the ECCPOISONADDR0/1 registers + # Enable ECC data poisoning - introduces ECC errors on writes to address s + # pecified by the ECCPOISONADDR0/1 registers # PSU_DDRC_ECCCFG1_DATA_POISON_EN 0x0 # ECC Configuration Register 1 @@ -1551,43 +1652,60 @@ set psu_ddr_init_data { mask_write 0XFD070074 0x00000003 0x00000000 # Register : CRCPARCTL1 @ 0XFD0700C4

- # The maximum number of DFI PHY clock cycles allowed from the assertion of the dfi_rddata_en signal to the assertion of each of - # the corresponding bits of the dfi_rddata_valid signal. This corresponds to the DFI timing parameter tphy_rdlat. Refer to PHY - # pecification for correct value. This value it only used for detecting read data timeout when DDR4 retry is enabled by CRCPARC - # L1.crc_parity_retry_enable=1. Maximum supported value: - 1:1 Frequency mode : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_ - # dlat < 'd114 - 1:2 Frequency mode ANDAND DFITMG0.dfi_rddata_use_sdr == 1 : CRCPARCTL1.dfi_t_phy_rdlat < 64 - 1:2 Frequency mo - # e ANDAND DFITMG0.dfi_rddata_use_sdr == 0 : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_rdlat < 'd114 Unit: DFI Clocks + # The maximum number of DFI PHY clock cycles allowed from the assertion of + # the dfi_rddata_en signal to the assertion of each of the corresponding + # bits of the dfi_rddata_valid signal. This corresponds to the DFI timing + # parameter tphy_rdlat. Refer to PHY specification for correct value. This + # value it only used for detecting read data timeout when DDR4 retry is e + # nabled by CRCPARCTL1.crc_parity_retry_enable=1. Maximum supported value: + # - 1:1 Frequency mode : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_r + # dlat < 'd114 - 1:2 Frequency mode ANDAND DFITMG0.dfi_rddata_use_sdr == 1 + # : CRCPARCTL1.dfi_t_phy_rdlat < 64 - 1:2 Frequency mode ANDAND DFITMG0.d + # fi_rddata_use_sdr == 0 : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_ + # rdlat < 'd114 Unit: DFI Clocks # PSU_DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT 0x10 - # After a Parity or CRC error is flagged on dfi_alert_n signal, the software has an option to read the mode registers in the DR - # M before the hardware begins the retry process - 1: Wait for software to read/write the mode registers before hardware begins - # the retry. After software is done with its operations, it will clear the alert interrupt register bit - 0: Hardware can begin - # the retry right away after the dfi_alert_n pulse goes away. The value on this register is valid only when retry is enabled (P - # RCTRL.crc_parity_retry_enable = 1) If this register is set to 1 and if the software doesn't clear the interrupt register afte - # handling the parity/CRC error, then the hardware will not begin the retry process and the system will hang. In the case of P - # rity/CRC error, there are two possibilities when the software doesn't reset MR5[4] to 0. - (i) If 'Persistent parity' mode re - # ister bit is NOT set: the commands sent during retry and normal operation are executed without parity checking. The value in - # he Parity error log register MPR Page 1 is valid. - (ii) If 'Persistent parity' mode register bit is SET: Parity checking is - # one for commands sent during retry and normal operation. If multiple errors occur before MR5[4] is cleared, the error log in - # PR Page 1 should be treated as 'Don't care'. + # After a Parity or CRC error is flagged on dfi_alert_n signal, the softwa + # re has an option to read the mode registers in the DRAM before the hardw + # are begins the retry process - 1: Wait for software to read/write the mo + # de registers before hardware begins the retry. After software is done wi + # th its operations, it will clear the alert interrupt register bit - 0: H + # ardware can begin the retry right away after the dfi_alert_n pulse goes + # away. The value on this register is valid only when retry is enabled (PA + # RCTRL.crc_parity_retry_enable = 1) If this register is set to 1 and if t + # he software doesn't clear the interrupt register after handling the pari + # ty/CRC error, then the hardware will not begin the retry process and the + # system will hang. In the case of Parity/CRC error, there are two possib + # ilities when the software doesn't reset MR5[4] to 0. - (i) If 'Persisten + # t parity' mode register bit is NOT set: the commands sent during retry a + # nd normal operation are executed without parity checking. The value in t + # he Parity error log register MPR Page 1 is valid. - (ii) If 'Persistent + # parity' mode register bit is SET: Parity checking is done for commands s + # ent during retry and normal operation. If multiple errors occur before M + # R5[4] is cleared, the error log in MPR Page 1 should be treated as 'Don' + # t care'. # PSU_DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW 0x1 - # - 1: Enable command retry mechanism in case of C/A Parity or CRC error - 0: Disable command retry mechanism when C/A Parity o - # CRC features are enabled. Note that retry functionality is not supported if burst chop is enabled (MSTR.burstchop = 1) and/o - # disable auto-refresh is enabled (RFSHCTL3.dis_auto_refresh = 1) + # - 1: Enable command retry mechanism in case of C/A Parity or CRC error - + # 0: Disable command retry mechanism when C/A Parity or CRC features are + # enabled. Note that retry functionality is not supported if burst chop is + # enabled (MSTR.burstchop = 1) and/or disable auto-refresh is enabled (RF + # SHCTL3.dis_auto_refresh = 1) # PSU_DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE 0x0 - # CRC Calculation setting register - 1: CRC includes DM signal - 0: CRC not includes DM signal Present only in designs configur - # d to support DDR4. + # CRC Calculation setting register - 1: CRC includes DM signal - 0: CRC no + # t includes DM signal Present only in designs configured to support DDR4. # PSU_DDRC_CRCPARCTL1_CRC_INC_DM 0x0 - # CRC enable Register - 1: Enable generation of CRC - 0: Disable generation of CRC The setting of this register should match th - # CRC mode register setting in the DRAM. + # CRC enable Register - 1: Enable generation of CRC - 0: Disable generatio + # n of CRC The setting of this register should match the CRC mode register + # setting in the DRAM. # PSU_DDRC_CRCPARCTL1_CRC_ENABLE 0x0 - # C/A Parity enable register - 1: Enable generation of C/A parity and detection of C/A parity error - 0: Disable generation of - # /A parity and disable detection of C/A parity error If RCD's parity error detection or SDRAM's parity detection is enabled, t - # is register should be 1. + # C/A Parity enable register - 1: Enable generation of C/A parity and dete + # ction of C/A parity error - 0: Disable generation of C/A parity and disa + # ble detection of C/A parity error If RCD's parity error detection or SDR + # AM's parity detection is enabled, this register should be 1. # PSU_DDRC_CRCPARCTL1_PARITY_ENABLE 0x0 # CRC Parity Control Register1 @@ -1595,35 +1713,53 @@ set psu_ddr_init_data { mask_write 0XFD0700C4 0x3F000391 0x10000200 # Register : CRCPARCTL2 @ 0XFD0700C8

- # Value from the DRAM spec indicating the maximum width of the dfi_alert_n pulse when a parity error occurs. Recommended values - # - tPAR_ALERT_PW.MAX For configurations with MEMC_FREQ_RATIO=2, program this to tPAR_ALERT_PW.MAX/2 and round up to next inte - # er value. Values of 0, 1 and 2 are illegal. This value must be greater than CRCPARCTL2.t_crc_alert_pw_max. + # Value from the DRAM spec indicating the maximum width of the dfi_alert_n + # pulse when a parity error occurs. Recommended values: - tPAR_ALERT_PW.M + # AX For configurations with MEMC_FREQ_RATIO=2, program this to tPAR_ALERT + # _PW.MAX/2 and round up to next integer value. Values of 0, 1 and 2 are i + # llegal. This value must be greater than CRCPARCTL2.t_crc_alert_pw_max. # PSU_DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX 0x40 - # Value from the DRAM spec indicating the maximum width of the dfi_alert_n pulse when a CRC error occurs. Recommended values: - - # tCRC_ALERT_PW.MAX For configurations with MEMC_FREQ_RATIO=2, program this to tCRC_ALERT_PW.MAX/2 and round up to next integer - # value. Values of 0, 1 and 2 are illegal. This value must be less than CRCPARCTL2.t_par_alert_pw_max. + # Value from the DRAM spec indicating the maximum width of the dfi_alert_n + # pulse when a CRC error occurs. Recommended values: - tCRC_ALERT_PW.MAX + # For configurations with MEMC_FREQ_RATIO=2, program this to tCRC_ALERT_PW + # .MAX/2 and round up to next integer value. Values of 0, 1 and 2 are ille + # gal. This value must be less than CRCPARCTL2.t_par_alert_pw_max. # PSU_DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX 0x5 - # Indicates the maximum duration in number of DRAM clock cycles for which a command should be held in the Command Retry FIFO be - # ore it is popped out. Every location in the Command Retry FIFO has an associated down counting timer that will use this regis - # er as the start value. The down counting starts when a command is loaded into the FIFO. The timer counts down every 4 DRAM cy - # les. When the counter reaches zero, the entry is popped from the FIFO. All the counters are frozen, if a C/A Parity or CRC er - # or occurs before the counter reaches zero. The counter is reset to 0, after all the commands in the FIFO are retried. Recomme - # ded(minimum) values: - Only C/A Parity is enabled. RoundUp((PHY Command Latency(DRAM CLK) + CAL + RDIMM delay + tPAR_ALERT_ON - # max + tPAR_UNKNOWN + PHY Alert Latency(DRAM CLK) + board delay) / 4) + 2 - Both C/A Parity and CRC is enabled/ Only CRC is en - # bled. RoundUp((PHY Command Latency(DRAM CLK) + CAL + RDIMM delay + WL + 5(BL10)+ tCRC_ALERT.max + PHY Alert Latency(DRAM CLK) - # + board delay) / 4) + 2 Note 1: All value (e.g. tPAR_ALERT_ON) should be in terms of DRAM Clock and round up Note 2: Board de - # ay(Command/Alert_n) should be considered. Note 3: Use the worst case(longer) value for PHY Latencies/Board delay Note 4: The - # ecommended values are minimum value to be set. For mode detail, See 'Calculation of FIFO Depth' section. Max value can be set - # to this register is defined below: - MEMC_BURST_LENGTH == 16 Full bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH- - # Full bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Half bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_D - # PTH-4 Half bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-6 Quarter bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CM - # _FIFO_DEPTH-8 Quarter bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-12 - MEMC_BURST_LENGTH != 16 Full bus Mode (C - # C=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-1 Full bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mo - # e (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Quarte - # bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-4 Quarter bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEP - # H-6 Values of 0, 1 and 2 are illegal. + # Indicates the maximum duration in number of DRAM clock cycles for which + # a command should be held in the Command Retry FIFO before it is popped o + # ut. Every location in the Command Retry FIFO has an associated down coun + # ting timer that will use this register as the start value. The down coun + # ting starts when a command is loaded into the FIFO. The timer counts dow + # n every 4 DRAM cycles. When the counter reaches zero, the entry is poppe + # d from the FIFO. All the counters are frozen, if a C/A Parity or CRC err + # or occurs before the counter reaches zero. The counter is reset to 0, af + # ter all the commands in the FIFO are retried. Recommended(minimum) value + # s: - Only C/A Parity is enabled. RoundUp((PHY Command Latency(DRAM CLK) + # + CAL + RDIMM delay + tPAR_ALERT_ON.max + tPAR_UNKNOWN + PHY Alert Laten + # cy(DRAM CLK) + board delay) / 4) + 2 - Both C/A Parity and CRC is enable + # d/ Only CRC is enabled. RoundUp((PHY Command Latency(DRAM CLK) + CAL + R + # DIMM delay + WL + 5(BL10)+ tCRC_ALERT.max + PHY Alert Latency(DRAM CLK) + # + board delay) / 4) + 2 Note 1: All value (e.g. tPAR_ALERT_ON) should be + # in terms of DRAM Clock and round up Note 2: Board delay(Command/Alert_n + # ) should be considered. Note 3: Use the worst case(longer) value for PHY + # Latencies/Board delay Note 4: The Recommended values are minimum value + # to be set. For mode detail, See 'Calculation of FIFO Depth' section. Max + # value can be set to this register is defined below: - MEMC_BURST_LENGTH + # == 16 Full bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 + # Full bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Half b + # us Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-4 Half bus Mod + # e (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-6 Quarter bus Mode (C + # RC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-8 Quarter bus Mode (CRC= + # ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-12 - MEMC_BURST_LENGTH != 16 + # Full bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-1 Full + # bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mod + # e (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mode (CRC + # =ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Quarter bus Mode (CRC=OFF + # ) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-4 Quarter bus Mode (CRC=ON) Ma + # x value = UMCTL2_RETRY_CMD_FIFO_DEPTH-6 Values of 0, 1 and 2 are illegal + # . # PSU_DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4 0x1f # CRC Parity Control Register2 @@ -1631,23 +1767,31 @@ set psu_ddr_init_data { mask_write 0XFD0700C8 0x01FF1F3F 0x0040051F # Register : INIT0 @ 0XFD0700D0

- # If lower bit is enabled the SDRAM initialization routine is skipped. The upper bit decides what state the controller starts u - # in when reset is removed - 00 - SDRAM Intialization routine is run after power-up - 01 - SDRAM Intialization routine is skip - # ed after power-up. Controller starts up in Normal Mode - 11 - SDRAM Intialization routine is skipped after power-up. Controll - # r starts up in Self-refresh Mode - 10 - SDRAM Intialization routine is run after power-up. Note: The only 2'b00 is supported - # or LPDDR4 in this version of the uMCTL2. + # If lower bit is enabled the SDRAM initialization routine is skipped. The + # upper bit decides what state the controller starts up in when reset is + # removed - 00 - SDRAM Intialization routine is run after power-up - 01 - + # SDRAM Intialization routine is skipped after power-up. Controller starts + # up in Normal Mode - 11 - SDRAM Intialization routine is skipped after p + # ower-up. Controller starts up in Self-refresh Mode - 10 - SDRAM Intializ + # ation routine is run after power-up. Note: The only 2'b00 is supported f + # or LPDDR4 in this version of the uMCTL2. # PSU_DDRC_INIT0_SKIP_DRAM_INIT 0x0 - # Cycles to wait after driving CKE high to start the SDRAM initialization sequence. Unit: 1024 clocks. DDR2 typically requires - # 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2/LPDDR3 typically requires this to be pr - # grammed for a delay of 200 us. LPDDR4 typically requires this to be programmed for a delay of 2 us. For configurations with M - # MC_FREQ_RATIO=2, program this to JEDEC spec value divided by 2, and round it up to next integer value. + # Cycles to wait after driving CKE high to start the SDRAM initialization + # sequence. Unit: 1024 clocks. DDR2 typically requires a 400 ns delay, req + # uiring this value to be programmed to 2 at all clock speeds. LPDDR2/LPDD + # R3 typically requires this to be programmed for a delay of 200 us. LPDDR + # 4 typically requires this to be programmed for a delay of 2 us. For conf + # igurations with MEMC_FREQ_RATIO=2, program this to JEDEC spec value divi + # ded by 2, and round it up to next integer value. # PSU_DDRC_INIT0_POST_CKE_X1024 0x2 - # Cycles to wait after reset before driving CKE high to start the SDRAM initialization sequence. Unit: 1024 clock cycles. DDR2 - # pecifications typically require this to be programmed for a delay of >= 200 us. LPDDR2/LPDDR3: tINIT1 of 100 ns (min) LPDDR4: - # tINIT3 of 2 ms (min) For configurations with MEMC_FREQ_RATIO=2, program this to JEDEC spec value divided by 2, and round it u - # to next integer value. + # Cycles to wait after reset before driving CKE high to start the SDRAM in + # itialization sequence. Unit: 1024 clock cycles. DDR2 specifications typi + # cally require this to be programmed for a delay of >= 200 us. LPDDR2/LPD + # DR3: tINIT1 of 100 ns (min) LPDDR4: tINIT3 of 2 ms (min) For configurati + # ons with MEMC_FREQ_RATIO=2, program this to JEDEC spec value divided by + # 2, and round it up to next integer value. # PSU_DDRC_INIT0_PRE_CKE_X1024 0x106 # SDRAM Initialization Register 0 @@ -1655,16 +1799,20 @@ set psu_ddr_init_data { mask_write 0XFD0700D0 0xC3FF0FFF 0x00020106 # Register : INIT1 @ 0XFD0700D4

- # Number of cycles to assert SDRAM reset signal during init sequence. This is only present for designs supporting DDR3, DDR4 or - # LPDDR4 devices. For use with a DDR PHY, this should be set to a minimum of 1 + # Number of cycles to assert SDRAM reset signal during init sequence. This + # is only present for designs supporting DDR3, DDR4 or LPDDR4 devices. Fo + # r use with a DDR PHY, this should be set to a minimum of 1 # PSU_DDRC_INIT1_DRAM_RSTN_X1024 0x2 - # Cycles to wait after completing the SDRAM initialization sequence before starting the dynamic scheduler. Unit: Counts of a gl - # bal timer that pulses every 32 clock cycles. There is no known specific requirement for this; it may be set to zero. + # Cycles to wait after completing the SDRAM initialization sequence before + # starting the dynamic scheduler. Unit: Counts of a global timer that pul + # ses every 32 clock cycles. There is no known specific requirement for th + # is; it may be set to zero. # PSU_DDRC_INIT1_FINAL_WAIT_X32 0x0 - # Wait period before driving the OCD complete command to SDRAM. Unit: Counts of a global timer that pulses every 32 clock cycle - # . There is no known specific requirement for this; it may be set to zero. + # Wait period before driving the OCD complete command to SDRAM. Unit: Coun + # ts of a global timer that pulses every 32 clock cycles. There is no know + # n specific requirement for this; it may be set to zero. # PSU_DDRC_INIT1_PRE_OCD_X32 0x0 # SDRAM Initialization Register 1 @@ -1672,11 +1820,13 @@ set psu_ddr_init_data { mask_write 0XFD0700D4 0x01FF7F0F 0x00020000 # Register : INIT2 @ 0XFD0700D8

- # Idle time after the reset command, tINIT4. Present only in designs configured to support LPDDR2. Unit: 32 clock cycles. + # Idle time after the reset command, tINIT4. Present only in designs confi + # gured to support LPDDR2. Unit: 32 clock cycles. # PSU_DDRC_INIT2_IDLE_AFTER_RESET_X32 0x23 - # Time to wait after the first CKE high, tINIT2. Present only in designs configured to support LPDDR2/LPDDR3. Unit: 1 clock cyc - # e. LPDDR2/LPDDR3 typically requires 5 x tCK delay. + # Time to wait after the first CKE high, tINIT2. Present only in designs c + # onfigured to support LPDDR2/LPDDR3. Unit: 1 clock cycle. LPDDR2/LPDDR3 t + # ypically requires 5 x tCK delay. # PSU_DDRC_INIT2_MIN_STABLE_CLOCK_X1 0x5 # SDRAM Initialization Register 2 @@ -1684,28 +1834,33 @@ set psu_ddr_init_data { mask_write 0XFD0700D8 0x0000FF0F 0x00002305 # Register : INIT3 @ 0XFD0700DC

- # DDR2: Value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The uMCTL2 sets this bit appropriately - # DDR3/DDR4: Value loaded into MR0 register. mDDR: Value to write to MR register. LPDDR2/LPDDR3/LPDDR4 - Value to write to MR1 - # register - # PSU_DDRC_INIT3_MR 0x930 + # DDR2: Value to write to MR register. Bit 8 is for DLL and the setting he + # re is ignored. The uMCTL2 sets this bit appropriately. DDR3/DDR4: Value + # loaded into MR0 register. mDDR: Value to write to MR register. LPDDR2/LP + # DDR3/LPDDR4 - Value to write to MR1 register + # PSU_DDRC_INIT3_MR 0x730 - # DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setting in this register is ignored. The uMCTL2 sets those - # bits appropriately. DDR3/DDR4: Value to write to MR1 register Set bit 7 to 0. If PHY-evaluation mode training is enabled, thi - # bit is set appropriately by the uMCTL2 during write leveling. mDDR: Value to write to EMR register. LPDDR2/LPDDR3/LPDDR4 - V - # lue to write to MR2 register + # DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setti + # ng in this register is ignored. The uMCTL2 sets those bits appropriately + # . DDR3/DDR4: Value to write to MR1 register Set bit 7 to 0. If PHY-evalu + # ation mode training is enabled, this bit is set appropriately by the uMC + # TL2 during write leveling. mDDR: Value to write to EMR register. LPDDR2/ + # LPDDR3/LPDDR4 - Value to write to MR2 register # PSU_DDRC_INIT3_EMR 0x301 # SDRAM Initialization Register 3 - #(OFFSET, MASK, VALUE) (0XFD0700DC, 0xFFFFFFFFU ,0x09300301U) */ - mask_write 0XFD0700DC 0xFFFFFFFF 0x09300301 + #(OFFSET, MASK, VALUE) (0XFD0700DC, 0xFFFFFFFFU ,0x07300301U) */ + mask_write 0XFD0700DC 0xFFFFFFFF 0x07300301 # Register : INIT4 @ 0XFD0700E0

- # DDR2: Value to write to EMR2 register. DDR3/DDR4: Value to write to MR2 register LPDDR2/LPDDR3/LPDDR4: Value to write to MR3 - # egister mDDR: Unused + # DDR2: Value to write to EMR2 register. DDR3/DDR4: Value to write to MR2 + # register LPDDR2/LPDDR3/LPDDR4: Value to write to MR3 register mDDR: Unus + # ed # PSU_DDRC_INIT4_EMR2 0x20 - # DDR2: Value to write to EMR3 register. DDR3/DDR4: Value to write to MR3 register mDDR/LPDDR2/LPDDR3: Unused LPDDR4: Value to - # rite to MR13 register + # DDR2: Value to write to EMR3 register. DDR3/DDR4: Value to write to MR3 + # register mDDR/LPDDR2/LPDDR3: Unused LPDDR4: Value to write to MR13 regis + # ter # PSU_DDRC_INIT4_EMR3 0x200 # SDRAM Initialization Register 4 @@ -1713,12 +1868,15 @@ set psu_ddr_init_data { mask_write 0XFD0700E0 0xFFFFFFFF 0x00200200 # Register : INIT5 @ 0XFD0700E4

- # ZQ initial calibration, tZQINIT. Present only in designs configured to support DDR3 or DDR4 or LPDDR2/LPDDR3. Unit: 32 clock - # ycles. DDR3 typically requires 512 clocks. DDR4 requires 1024 clocks. LPDDR2/LPDDR3 requires 1 us. + # ZQ initial calibration, tZQINIT. Present only in designs configured to s + # upport DDR3 or DDR4 or LPDDR2/LPDDR3. Unit: 32 clock cycles. DDR3 typica + # lly requires 512 clocks. DDR4 requires 1024 clocks. LPDDR2/LPDDR3 requir + # es 1 us. # PSU_DDRC_INIT5_DEV_ZQINIT_X32 0x21 - # Maximum duration of the auto initialization, tINIT5. Present only in designs configured to support LPDDR2/LPDDR3. LPDDR2/LPDD - # 3 typically requires 10 us. + # Maximum duration of the auto initialization, tINIT5. Present only in des + # igns configured to support LPDDR2/LPDDR3. LPDDR2/LPDDR3 typically requir + # es 10 us. # PSU_DDRC_INIT5_MAX_AUTO_INIT_X1024 0x4 # SDRAM Initialization Register 5 @@ -1726,10 +1884,12 @@ set psu_ddr_init_data { mask_write 0XFD0700E4 0x00FF03FF 0x00210004 # Register : INIT6 @ 0XFD0700E8

- # DDR4- Value to be loaded into SDRAM MR4 registers. Used in DDR4 designs only. + # DDR4- Value to be loaded into SDRAM MR4 registers. Used in DDR4 designs + # only. # PSU_DDRC_INIT6_MR4 0x0 - # DDR4- Value to be loaded into SDRAM MR5 registers. Used in DDR4 designs only. + # DDR4- Value to be loaded into SDRAM MR5 registers. Used in DDR4 designs + # only. # PSU_DDRC_INIT6_MR5 0x6c0 # SDRAM Initialization Register 6 @@ -1737,7 +1897,8 @@ set psu_ddr_init_data { mask_write 0XFD0700E8 0xFFFFFFFF 0x000006C0 # Register : INIT7 @ 0XFD0700EC

- # DDR4- Value to be loaded into SDRAM MR6 registers. Used in DDR4 designs only. + # DDR4- Value to be loaded into SDRAM MR6 registers. Used in DDR4 designs + # only. # PSU_DDRC_INIT7_MR6 0x819 # SDRAM Initialization Register 7 @@ -1745,50 +1906,73 @@ set psu_ddr_init_data { mask_write 0XFD0700EC 0xFFFF0000 0x08190000 # Register : DIMMCTL @ 0XFD0700F0

- # Disabling Address Mirroring for BG bits. When this is set to 1, BG0 and BG1 are NOT swapped even if Address Mirroring is enab - # ed. This will be required for DDR4 DIMMs with x16 devices. - 1 - BG0 and BG1 are NOT swapped. - 0 - BG0 and BG1 are swapped i - # address mirroring is enabled. + # Disabling Address Mirroring for BG bits. When this is set to 1, BG0 and + # BG1 are NOT swapped even if Address Mirroring is enabled. This will be r + # equired for DDR4 DIMMs with x16 devices. - 1 - BG0 and BG1 are NOT swapp + # ed. - 0 - BG0 and BG1 are swapped if address mirroring is enabled. # PSU_DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING 0x0 - # Enable for BG1 bit of MRS command. BG1 bit of the mode register address is specified as RFU (Reserved for Future Use) and mus - # be programmed to 0 during MRS. In case where DRAMs which do not have BG1 are attached and both the CA parity and the Output - # nversion are enabled, this must be set to 0, so that the calculation of CA parity will not include BG1 bit. Note: This has no - # effect on the address of any other memory accesses, or of software-driven mode register accesses. If address mirroring is ena - # led, this is applied to BG1 of even ranks and BG0 of odd ranks. - 1 - Enabled - 0 - Disabled + # Enable for BG1 bit of MRS command. BG1 bit of the mode register address + # is specified as RFU (Reserved for Future Use) and must be programmed to + # 0 during MRS. In case where DRAMs which do not have BG1 are attached and + # both the CA parity and the Output Inversion are enabled, this must be s + # et to 0, so that the calculation of CA parity will not include BG1 bit. + # Note: This has no effect on the address of any other memory accesses, or + # of software-driven mode register accesses. If address mirroring is enab + # led, this is applied to BG1 of even ranks and BG0 of odd ranks. - 1 - En + # abled - 0 - Disabled # PSU_DDRC_DIMMCTL_MRS_BG1_EN 0x1 - # Enable for A17 bit of MRS command. A17 bit of the mode register address is specified as RFU (Reserved for Future Use) and mus - # be programmed to 0 during MRS. In case where DRAMs which do not have A17 are attached and the Output Inversion are enabled, - # his must be set to 0, so that the calculation of CA parity will not include A17 bit. Note: This has no effect on the address - # f any other memory accesses, or of software-driven mode register accesses. - 1 - Enabled - 0 - Disabled + # Enable for A17 bit of MRS command. A17 bit of the mode register address + # is specified as RFU (Reserved for Future Use) and must be programmed to + # 0 during MRS. In case where DRAMs which do not have A17 are attached and + # the Output Inversion are enabled, this must be set to 0, so that the ca + # lculation of CA parity will not include A17 bit. Note: This has no effec + # t on the address of any other memory accesses, or of software-driven mod + # e register accesses. - 1 - Enabled - 0 - Disabled # PSU_DDRC_DIMMCTL_MRS_A17_EN 0x0 - # Output Inversion Enable (for DDR4 RDIMM implementations only). DDR4 RDIMM implements the Output Inversion feature by default, - # which means that the following address, bank address and bank group bits of B-side DRAMs are inverted: A3-A9, A11, A13, A17, - # A0-BA1, BG0-BG1. Setting this bit ensures that, for mode register accesses generated by the uMCTL2 during the automatic initi - # lization routine and enabling of a particular DDR4 feature, separate A-side and B-side mode register accesses are generated. - # or B-side mode register accesses, these bits are inverted within the uMCTL2 to compensate for this RDIMM inversion. Note: Thi - # has no effect on the address of any other memory accesses, or of software-driven mode register accesses. - 1 - Implement out - # ut inversion for B-side DRAMs. - 0 - Do not implement output inversion for B-side DRAMs. + # Output Inversion Enable (for DDR4 RDIMM implementations only). DDR4 RDIM + # M implements the Output Inversion feature by default, which means that t + # he following address, bank address and bank group bits of B-side DRAMs a + # re inverted: A3-A9, A11, A13, A17, BA0-BA1, BG0-BG1. Setting this bit en + # sures that, for mode register accesses generated by the uMCTL2 during th + # e automatic initialization routine and enabling of a particular DDR4 fea + # ture, separate A-side and B-side mode register accesses are generated. F + # or B-side mode register accesses, these bits are inverted within the uMC + # TL2 to compensate for this RDIMM inversion. Note: This has no effect on + # the address of any other memory accesses, or of software-driven mode reg + # ister accesses. - 1 - Implement output inversion for B-side DRAMs. - 0 - + # Do not implement output inversion for B-side DRAMs. # PSU_DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN 0x0 - # Address Mirroring Enable (for multi-rank UDIMM implementations and multi-rank DDR4 RDIMM implementations). Some UDIMMs and DD - # 4 RDIMMs implement address mirroring for odd ranks, which means that the following address, bank address and bank group bits - # re swapped: (A3, A4), (A5, A6), (A7, A8), (BA0, BA1) and also (A11, A13), (BG0, BG1) for the DDR4. Setting this bit ensures t - # at, for mode register accesses during the automatic initialization routine, these bits are swapped within the uMCTL2 to compe - # sate for this UDIMM/RDIMM swapping. In addition to the automatic initialization routine, in case of DDR4 UDIMM/RDIMM, they ar - # swapped during the automatic MRS access to enable/disable of a particular DDR4 feature. Note: This has no effect on the addr - # ss of any other memory accesses, or of software-driven mode register accesses. This is not supported for mDDR, LPDDR2, LPDDR3 - # or LPDDR4 SDRAMs. Note: In case of x16 DDR4 DIMMs, BG1 output of MRS for the odd ranks is same as BG0 because BG1 is invalid, - # hence dimm_dis_bg_mirroring register must be set to 1. - 1 - For odd ranks, implement address mirroring for MRS commands to d - # ring initialization and for any automatic DDR4 MRS commands (to be used if UDIMM/RDIMM implements address mirroring) - 0 - Do - # not implement address mirroring + # Address Mirroring Enable (for multi-rank UDIMM implementations and multi + # -rank DDR4 RDIMM implementations). Some UDIMMs and DDR4 RDIMMs implement + # address mirroring for odd ranks, which means that the following address + # , bank address and bank group bits are swapped: (A3, A4), (A5, A6), (A7, + # A8), (BA0, BA1) and also (A11, A13), (BG0, BG1) for the DDR4. Setting t + # his bit ensures that, for mode register accesses during the automatic in + # itialization routine, these bits are swapped within the uMCTL2 to compen + # sate for this UDIMM/RDIMM swapping. In addition to the automatic initial + # ization routine, in case of DDR4 UDIMM/RDIMM, they are swapped during th + # e automatic MRS access to enable/disable of a particular DDR4 feature. N + # ote: This has no effect on the address of any other memory accesses, or + # of software-driven mode register accesses. This is not supported for mDD + # R, LPDDR2, LPDDR3 or LPDDR4 SDRAMs. Note: In case of x16 DDR4 DIMMs, BG1 + # output of MRS for the odd ranks is same as BG0 because BG1 is invalid, + # hence dimm_dis_bg_mirroring register must be set to 1. - 1 - For odd ran + # ks, implement address mirroring for MRS commands to during initializatio + # n and for any automatic DDR4 MRS commands (to be used if UDIMM/RDIMM imp + # lements address mirroring) - 0 - Do not implement address mirroring # PSU_DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN 0x0 - # Staggering enable for multi-rank accesses (for multi-rank UDIMM and RDIMM implementations only). This is not supported for mD - # R, LPDDR2, LPDDR3 or LPDDR4 SDRAMs. Note: Even if this bit is set it does not take care of software driven MR commands (via M - # CTRL0/MRCTRL1), where software is responsible to send them to seperate ranks as appropriate. - 1 - (DDR4) Send MRS commands t - # each ranks seperately - 1 - (non-DDR4) Send all commands to even and odd ranks seperately - 0 - Do not stagger accesses + # Staggering enable for multi-rank accesses (for multi-rank UDIMM and RDIM + # M implementations only). This is not supported for mDDR, LPDDR2, LPDDR3 + # or LPDDR4 SDRAMs. Note: Even if this bit is set it does not take care of + # software driven MR commands (via MRCTRL0/MRCTRL1), where software is re + # sponsible to send them to seperate ranks as appropriate. - 1 - (DDR4) Se + # nd MRS commands to each ranks seperately - 1 - (non-DDR4) Send all comma + # nds to even and odd ranks seperately - 0 - Do not stagger accesses # PSU_DDRC_DIMMCTL_DIMM_STAGGER_CS_EN 0x0 # DIMM Control Register @@ -1796,38 +1980,56 @@ set psu_ddr_init_data { mask_write 0XFD0700F0 0x0000003F 0x00000010 # Register : RANKCTL @ 0XFD0700F4

- # Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecuti - # e writes to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This value should c - # nsider both PHY requirement and ODT requirement. - PHY requirement: tphy_wrcsgap + 1 (see PHY databook for value of tphy_wrcs - # ap) If CRC feature is enabled, should be increased by 1. If write preamble is set to 2tCK(DDR4/LPDDR4 only), should be increa - # ed by 1. If write postamble is set to 1.5tCK(LPDDR4 only), should be increased by 1. - ODT requirement: The value programmed - # n this register takes care of the ODT switch off timing requirement when switching ranks during writes. For LPDDR4, the requi - # ement is ODTLoff - ODTLon - BL/2 + 1 For configurations with MEMC_FREQ_RATIO=1, program this to the larger of PHY requirement - # or ODT requirement. For configurations with MEMC_FREQ_RATIO=2, program this to the larger value divided by two and round it u - # to the next integer. + # Only present for multi-rank configurations. Indicates the number of cloc + # ks of gap in data responses when performing consecutive writes to differ + # ent ranks. This is used to switch the delays in the PHY to match the ran + # k requirements. This value should consider both PHY requirement and ODT + # requirement. - PHY requirement: tphy_wrcsgap + 1 (see PHY databook for v + # alue of tphy_wrcsgap) If CRC feature is enabled, should be increased by + # 1. If write preamble is set to 2tCK(DDR4/LPDDR4 only), should be increas + # ed by 1. If write postamble is set to 1.5tCK(LPDDR4 only), should be inc + # reased by 1. - ODT requirement: The value programmed in this register ta + # kes care of the ODT switch off timing requirement when switching ranks d + # uring writes. For LPDDR4, the requirement is ODTLoff - ODTLon - BL/2 + 1 + # For configurations with MEMC_FREQ_RATIO=1, program this to the larger o + # f PHY requirement or ODT requirement. For configurations with MEMC_FREQ_ + # RATIO=2, program this to the larger value divided by two and round it up + # to the next integer. # PSU_DDRC_RANKCTL_DIFF_RANK_WR_GAP 0x6 - # Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecuti - # e reads to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This value should co - # sider both PHY requirement and ODT requirement. - PHY requirement: tphy_rdcsgap + 1 (see PHY databook for value of tphy_rdcsg - # p) If read preamble is set to 2tCK(DDR4/LPDDR4 only), should be increased by 1. If read postamble is set to 1.5tCK(LPDDR4 onl - # ), should be increased by 1. - ODT requirement: The value programmed in this register takes care of the ODT switch off timing - # requirement when switching ranks during reads. For configurations with MEMC_FREQ_RATIO=1, program this to the larger of PHY r - # quirement or ODT requirement. For configurations with MEMC_FREQ_RATIO=2, program this to the larger value divided by two and - # ound it up to the next integer. + # Only present for multi-rank configurations. Indicates the number of cloc + # ks of gap in data responses when performing consecutive reads to differe + # nt ranks. This is used to switch the delays in the PHY to match the rank + # requirements. This value should consider both PHY requirement and ODT r + # equirement. - PHY requirement: tphy_rdcsgap + 1 (see PHY databook for va + # lue of tphy_rdcsgap) If read preamble is set to 2tCK(DDR4/LPDDR4 only), + # should be increased by 1. If read postamble is set to 1.5tCK(LPDDR4 only + # ), should be increased by 1. - ODT requirement: The value programmed in + # this register takes care of the ODT switch off timing requirement when s + # witching ranks during reads. For configurations with MEMC_FREQ_RATIO=1, + # program this to the larger of PHY requirement or ODT requirement. For co + # nfigurations with MEMC_FREQ_RATIO=2, program this to the larger value di + # vided by two and round it up to the next integer. # PSU_DDRC_RANKCTL_DIFF_RANK_RD_GAP 0x6 - # Only present for multi-rank configurations. Background: Reads to the same rank can be performed back-to-back. Reads to differ - # nt ranks require additional gap dictated by the register RANKCTL.diff_rank_rd_gap. This is to avoid possible data bus content - # on as well as to give PHY enough time to switch the delay when changing ranks. The uMCTL2 arbitrates for bus access on a cycl - # -by-cycle basis; therefore after a read is scheduled, there are few clock cycles (determined by the value on RANKCTL.diff_ran - # _rd_gap register) in which only reads from the same rank are eligible to be scheduled. This prevents reads from other ranks f - # om having fair access to the data bus. This parameter represents the maximum number of reads that can be scheduled consecutiv - # ly to the same rank. After this number is reached, a delay equal to RANKCTL.diff_rank_rd_gap is inserted by the scheduler to - # llow all ranks a fair opportunity to be scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fair - # ess. This feature can be DISABLED by setting this register to 0. When set to 0, the Controller will stay on the same rank as - # ong as commands are available for it. Minimum programmable value is 0 (feature disabled) and maximum programmable value is 0x - # . FOR PERFORMANCE ONLY. + # Only present for multi-rank configurations. Background: Reads to the sam + # e rank can be performed back-to-back. Reads to different ranks require a + # dditional gap dictated by the register RANKCTL.diff_rank_rd_gap. This is + # to avoid possible data bus contention as well as to give PHY enough tim + # e to switch the delay when changing ranks. The uMCTL2 arbitrates for bus + # access on a cycle-by-cycle basis; therefore after a read is scheduled, + # there are few clock cycles (determined by the value on RANKCTL.diff_rank + # _rd_gap register) in which only reads from the same rank are eligible to + # be scheduled. This prevents reads from other ranks from having fair acc + # ess to the data bus. This parameter represents the maximum number of rea + # ds that can be scheduled consecutively to the same rank. After this numb + # er is reached, a delay equal to RANKCTL.diff_rank_rd_gap is inserted by + # the scheduler to allow all ranks a fair opportunity to be scheduled. Hig + # her numbers increase bandwidth utilization, lower numbers increase fairn + # ess. This feature can be DISABLED by setting this register to 0. When se + # t to 0, the Controller will stay on the same rank as long as commands ar + # e available for it. Minimum programmable value is 0 (feature disabled) a + # nd maximum programmable value is 0xF. FOR PERFORMANCE ONLY. # PSU_DDRC_RANKCTL_MAX_RANK_RD 0xf # Rank Control Register @@ -1835,110 +2037,155 @@ set psu_ddr_init_data { mask_write 0XFD0700F4 0x00000FFF 0x0000066F # Register : DRAMTMG0 @ 0XFD070100

- # Minimum time between write and precharge to same bank. Unit: Clocks Specifications: WL + BL/2 + tWR = approximately 8 cycles - # 15 ns = 14 clocks @400MHz and less for lower frequencies where: - WL = write latency - BL = burst length. This must match th - # value programmed in the BL bit of the mode register to the SDRAM. BST (burst terminate) is not supported at present. - tWR = - # Write recovery time. This comes directly from the SDRAM specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 for this - # arameter. For configurations with MEMC_FREQ_RATIO=2, 1T mode, divide the above value by 2. No rounding up. For configurations - # with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, divide the above value by 2 and round it up to the next integer value. + # Minimum time between write and precharge to same bank. Unit: Clocks Spec + # ifications: WL + BL/2 + tWR = approximately 8 cycles + 15 ns = 14 clocks + # @400MHz and less for lower frequencies where: - WL = write latency - BL + # = burst length. This must match the value programmed in the BL bit of t + # he mode register to the SDRAM. BST (burst terminate) is not supported at + # present. - tWR = Write recovery time. This comes directly from the SDRA + # M specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 for this p + # arameter. For configurations with MEMC_FREQ_RATIO=2, 1T mode, divide the + # above value by 2. No rounding up. For configurations with MEMC_FREQ_RAT + # IO=2, 2T mode or LPDDR4 mode, divide the above value by 2 and round it u + # p to the next integer value. # PSU_DDRC_DRAMTMG0_WR2PRE 0x11 - # tFAW Valid only when 8 or more banks(or banks x bank groups) are present. In 8-bank design, at most 4 banks must be activated - # in a rolling window of tFAW cycles. For configurations with MEMC_FREQ_RATIO=2, program this to (tFAW/2) and round up to next - # nteger value. In a 4-bank design, set this register to 0x1 independent of the MEMC_FREQ_RATIO configuration. Unit: Clocks - # PSU_DDRC_DRAMTMG0_T_FAW 0xc + # tFAW Valid only when 8 or more banks(or banks x bank groups) are present + # . In 8-bank design, at most 4 banks must be activated in a rolling windo + # w of tFAW cycles. For configurations with MEMC_FREQ_RATIO=2, program thi + # s to (tFAW/2) and round up to next integer value. In a 4-bank design, se + # t this register to 0x1 independent of the MEMC_FREQ_RATIO configuration. + # Unit: Clocks + # PSU_DDRC_DRAMTMG0_T_FAW 0x10 - # tRAS(max): Maximum time between activate and precharge to same bank. This is the maximum time that a page can be kept open Mi - # imum value of this register is 1. Zero is invalid. For configurations with MEMC_FREQ_RATIO=2, program this to (tRAS(max)-1)/2 - # No rounding up. Unit: Multiples of 1024 clocks. + # tRAS(max): Maximum time between activate and precharge to same bank. Thi + # s is the maximum time that a page can be kept open Minimum value of this + # register is 1. Zero is invalid. For configurations with MEMC_FREQ_RATIO + # =2, program this to (tRAS(max)-1)/2. No rounding up. Unit: Multiples of + # 1024 clocks. # PSU_DDRC_DRAMTMG0_T_RAS_MAX 0x24 - # tRAS(min): Minimum time between activate and precharge to the same bank. For configurations with MEMC_FREQ_RATIO=2, 1T mode, - # rogram this to tRAS(min)/2. No rounding up. For configurations with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, program this t - # (tRAS(min)/2) and round it up to the next integer value. Unit: Clocks + # tRAS(min): Minimum time between activate and precharge to the same bank. + # For configurations with MEMC_FREQ_RATIO=2, 1T mode, program this to tRA + # S(min)/2. No rounding up. For configurations with MEMC_FREQ_RATIO=2, 2T + # mode or LPDDR4 mode, program this to (tRAS(min)/2) and round it up to th + # e next integer value. Unit: Clocks # PSU_DDRC_DRAMTMG0_T_RAS_MIN 0x12 # SDRAM Timing Register 0 - #(OFFSET, MASK, VALUE) (0XFD070100, 0x7F3F7F3FU ,0x110C2412U) */ - mask_write 0XFD070100 0x7F3F7F3F 0x110C2412 + #(OFFSET, MASK, VALUE) (0XFD070100, 0x7F3F7F3FU ,0x11102412U) */ + mask_write 0XFD070100 0x7F3F7F3F 0x11102412 # Register : DRAMTMG1 @ 0XFD070104

- # tXP: Minimum time after power-down exit to any operation. For DDR3, this should be programmed to tXPDLL if slow powerdown exi - # is selected in MR0[12]. If C/A parity for DDR4 is used, set to (tXP+PL) instead. For configurations with MEMC_FREQ_RATIO=2, - # rogram this to (tXP/2) and round it up to the next integer value. Units: Clocks + # tXP: Minimum time after power-down exit to any operation. For DDR3, this + # should be programmed to tXPDLL if slow powerdown exit is selected in MR + # 0[12]. If C/A parity for DDR4 is used, set to (tXP+PL) instead. For conf + # igurations with MEMC_FREQ_RATIO=2, program this to (tXP/2) and round it + # up to the next integer value. Units: Clocks # PSU_DDRC_DRAMTMG1_T_XP 0x4 - # tRTP: Minimum time from read to precharge of same bank. - DDR2: tAL + BL/2 + max(tRTP, 2) - 2 - DDR3: tAL + max (tRTP, 4) - D - # R4: Max of following two equations: tAL + max (tRTP, 4) or, RL + BL/2 - tRP. - mDDR: BL/2 - LPDDR2: Depends on if it's LPDDR2 - # S2 or LPDDR2-S4: LPDDR2-S2: BL/2 + tRTP - 1. LPDDR2-S4: BL/2 + max(tRTP,2) - 2. - LPDDR3: BL/2 + max(tRTP,4) - 4 - LPDDR4: BL - # 2 + max(tRTP,8) - 8 For configurations with MEMC_FREQ_RATIO=2, 1T mode, divide the above value by 2. No rounding up. For conf - # gurations with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, divide the above value by 2 and round it up to the next integer val - # e. Unit: Clocks. + # tRTP: Minimum time from read to precharge of same bank. - DDR2: tAL + BL + # /2 + max(tRTP, 2) - 2 - DDR3: tAL + max (tRTP, 4) - DDR4: Max of followi + # ng two equations: tAL + max (tRTP, 4) or, RL + BL/2 - tRP. - mDDR: BL/2 + # - LPDDR2: Depends on if it's LPDDR2-S2 or LPDDR2-S4: LPDDR2-S2: BL/2 + t + # RTP - 1. LPDDR2-S4: BL/2 + max(tRTP,2) - 2. - LPDDR3: BL/2 + max(tRTP,4) + # - 4 - LPDDR4: BL/2 + max(tRTP,8) - 8 For configurations with MEMC_FREQ_ + # RATIO=2, 1T mode, divide the above value by 2. No rounding up. For confi + # gurations with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, divide the abo + # ve value by 2 and round it up to the next integer value. Unit: Clocks. # PSU_DDRC_DRAMTMG1_RD2PRE 0x4 - # tRC: Minimum time between activates to same bank. For configurations with MEMC_FREQ_RATIO=2, program this to (tRC/2) and roun - # up to next integer value. Unit: Clocks. - # PSU_DDRC_DRAMTMG1_T_RC 0x19 + # tRC: Minimum time between activates to same bank. For configurations wit + # h MEMC_FREQ_RATIO=2, program this to (tRC/2) and round up to next intege + # r value. Unit: Clocks. + # PSU_DDRC_DRAMTMG1_T_RC 0x1a # SDRAM Timing Register 1 - #(OFFSET, MASK, VALUE) (0XFD070104, 0x001F1F7FU ,0x00040419U) */ - mask_write 0XFD070104 0x001F1F7F 0x00040419 + #(OFFSET, MASK, VALUE) (0XFD070104, 0x001F1F7FU ,0x0004041AU) */ + mask_write 0XFD070104 0x001F1F7F 0x0004041A # Register : DRAMTMG2 @ 0XFD070108

- # Set to WL Time from write command to write data on SDRAM interface. This must be set to WL. For mDDR, it should normally be s - # t to 1. Note that, depending on the PHY, if using RDIMM, it may be necessary to use a value of WL + 1 to compensate for the e - # tra cycle of latency through the RDIMM For configurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above - # equation by 2, and round it up to next integer. This register field is not required for DDR2 and DDR3 (except if MEMC_TRAININ - # is set), as the DFI read and write latencies defined in DFITMG0 and DFITMG1 are sufficient for those protocols Unit: clocks + # Set to WL Time from write command to write data on SDRAM interface. This + # must be set to WL. For mDDR, it should normally be set to 1. Note that, + # depending on the PHY, if using RDIMM, it may be necessary to use a valu + # e of WL + 1 to compensate for the extra cycle of latency through the RDI + # MM For configurations with MEMC_FREQ_RATIO=2, divide the value calculate + # d using the above equation by 2, and round it up to next integer. This r + # egister field is not required for DDR2 and DDR3 (except if MEMC_TRAINING + # is set), as the DFI read and write latencies defined in DFITMG0 and DFI + # TMG1 are sufficient for those protocols Unit: clocks # PSU_DDRC_DRAMTMG2_WRITE_LATENCY 0x7 - # Set to RL Time from read command to read data on SDRAM interface. This must be set to RL. Note that, depending on the PHY, if - # using RDIMM, it mat be necessary to use a value of RL + 1 to compensate for the extra cycle of latency through the RDIMM For - # onfigurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next inte - # er. This register field is not required for DDR2 and DDR3 (except if MEMC_TRAINING is set), as the DFI read and write latenci - # s defined in DFITMG0 and DFITMG1 are sufficient for those protocols Unit: clocks + # Set to RL Time from read command to read data on SDRAM interface. This m + # ust be set to RL. Note that, depending on the PHY, if using RDIMM, it ma + # t be necessary to use a value of RL + 1 to compensate for the extra cycl + # e of latency through the RDIMM For configurations with MEMC_FREQ_RATIO=2 + # , divide the value calculated using the above equation by 2, and round i + # t up to next integer. This register field is not required for DDR2 and D + # DR3 (except if MEMC_TRAINING is set), as the DFI read and write latencie + # s defined in DFITMG0 and DFITMG1 are sufficient for those protocols Unit + # : clocks # PSU_DDRC_DRAMTMG2_READ_LATENCY 0x8 - # DDR2/3/mDDR: RL + BL/2 + 2 - WL DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL LPDDR2/LPDDR3: RL + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL - # PDDR4(DQ ODT is Disabled): RL + BL/2 + RU(tDQSCKmax/tCK) + WR_PREAMBLE + RD_POSTAMBLE - WL LPDDR4(DQ ODT is Enabled) : RL + B - # /2 + RU(tDQSCKmax/tCK) + RD_POSTAMBLE - ODTLon - RU(tODTon(min)/tCK) Minimum time from read command to write command. Include - # time for bus turnaround and all per-bank, per-rank, and global constraints. Unit: Clocks. Where: - WL = write latency - BL = - # urst length. This must match the value programmed in the BL bit of the mode register to the SDRAM - RL = read latency = CAS l - # tency - WR_PREAMBLE = write preamble. This is unique to DDR4 and LPDDR4. - RD_POSTAMBLE = read postamble. This is unique to L - # DDR4. For LPDDR2/LPDDR3/LPDDR4, if derating is enabled (DERATEEN.derate_enable=1), derated tDQSCKmax should be used. For conf - # gurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next integer. + # DDR2/3/mDDR: RL + BL/2 + 2 - WL DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL L + # PDDR2/LPDDR3: RL + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL LPDDR4(DQ ODT is Di + # sabled): RL + BL/2 + RU(tDQSCKmax/tCK) + WR_PREAMBLE + RD_POSTAMBLE - WL + # LPDDR4(DQ ODT is Enabled) : RL + BL/2 + RU(tDQSCKmax/tCK) + RD_POSTAMBL + # E - ODTLon - RU(tODTon(min)/tCK) Minimum time from read command to write + # command. Include time for bus turnaround and all per-bank, per-rank, an + # d global constraints. Unit: Clocks. Where: - WL = write latency - BL = b + # urst length. This must match the value programmed in the BL bit of the m + # ode register to the SDRAM - RL = read latency = CAS latency - WR_PREAMBL + # E = write preamble. This is unique to DDR4 and LPDDR4. - RD_POSTAMBLE = + # read postamble. This is unique to LPDDR4. For LPDDR2/LPDDR3/LPDDR4, if d + # erating is enabled (DERATEEN.derate_enable=1), derated tDQSCKmax should + # be used. For configurations with MEMC_FREQ_RATIO=2, divide the value cal + # culated using the above equation by 2, and round it up to next integer. # PSU_DDRC_DRAMTMG2_RD2WR 0x6 - # DDR4: CWL + PL + BL/2 + tWTR_L Others: CWL + BL/2 + tWTR In DDR4, minimum time from write command to read command for same ba - # k group. In others, minimum time from write command to read command. Includes time for bus turnaround, recovery times, and al - # per-bank, per-rank, and global constraints. Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity latency - BL = burs - # length. This must match the value programmed in the BL bit of the mode register to the SDRAM - tWTR_L = internal write to re - # d command delay for same bank group. This comes directly from the SDRAM specification. - tWTR = internal write to read comman - # delay. This comes directly from the SDRAM specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 operation. For configu - # ations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next integer. - # PSU_DDRC_DRAMTMG2_WR2RD 0xe + # DDR4: CWL + PL + BL/2 + tWTR_L Others: CWL + BL/2 + tWTR In DDR4, minimu + # m time from write command to read command for same bank group. In others + # , minimum time from write command to read command. Includes time for bus + # turnaround, recovery times, and all per-bank, per-rank, and global cons + # traints. Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity la + # tency - BL = burst length. This must match the value programmed in the B + # L bit of the mode register to the SDRAM - tWTR_L = internal write to rea + # d command delay for same bank group. This comes directly from the SDRAM + # specification. - tWTR = internal write to read command delay. This comes + # directly from the SDRAM specification. Add one extra cycle for LPDDR2/L + # PDDR3/LPDDR4 operation. For configurations with MEMC_FREQ_RATIO=2, divid + # e the value calculated using the above equation by 2, and round it up to + # next integer. + # PSU_DDRC_DRAMTMG2_WR2RD 0xd # SDRAM Timing Register 2 - #(OFFSET, MASK, VALUE) (0XFD070108, 0x3F3F3F3FU ,0x0708060EU) */ - mask_write 0XFD070108 0x3F3F3F3F 0x0708060E + #(OFFSET, MASK, VALUE) (0XFD070108, 0x3F3F3F3FU ,0x0708060DU) */ + mask_write 0XFD070108 0x3F3F3F3F 0x0708060D # Register : DRAMTMG3 @ 0XFD07010C

- # Time to wait after a mode register write or read (MRW or MRR). Present only in designs configured to support LPDDR2, LPDDR3 o - # LPDDR4. LPDDR2 typically requires value of 5. LPDDR3 typically requires value of 10. LPDDR4: Set this to the larger of tMRW - # nd tMRWCKEL. For LPDDR2, this register is used for the time from a MRW/MRR to all other commands. For LDPDR3, this register i - # used for the time from a MRW/MRR to a MRW/MRR. + # Time to wait after a mode register write or read (MRW or MRR). Present o + # nly in designs configured to support LPDDR2, LPDDR3 or LPDDR4. LPDDR2 ty + # pically requires value of 5. LPDDR3 typically requires value of 10. LPDD + # R4: Set this to the larger of tMRW and tMRWCKEL. For LPDDR2, this regist + # er is used for the time from a MRW/MRR to all other commands. For LDPDR3 + # , this register is used for the time from a MRW/MRR to a MRW/MRR. # PSU_DDRC_DRAMTMG3_T_MRW 0x5 - # tMRD: Cycles to wait after a mode register write or read. Depending on the connected SDRAM, tMRD represents: DDR2/mDDR: Time - # rom MRS to any command DDR3/4: Time from MRS to MRS command LPDDR2: not used LPDDR3/4: Time from MRS to non-MRS command For c - # nfigurations with MEMC_FREQ_RATIO=2, program this to (tMRD/2) and round it up to the next integer value. If C/A parity for DD - # 4 is used, set to tMRD_PAR(tMOD+PL) instead. + # tMRD: Cycles to wait after a mode register write or read. Depending on t + # he connected SDRAM, tMRD represents: DDR2/mDDR: Time from MRS to any com + # mand DDR3/4: Time from MRS to MRS command LPDDR2: not used LPDDR3/4: Tim + # e from MRS to non-MRS command For configurations with MEMC_FREQ_RATIO=2, + # program this to (tMRD/2) and round it up to the next integer value. If + # C/A parity for DDR4 is used, set to tMRD_PAR(tMOD+PL) instead. # PSU_DDRC_DRAMTMG3_T_MRD 0x4 - # tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode command and following non-load mode command. If C/A pari - # y for DDR4 is used, set to tMOD_PAR(tMOD+PL) instead. Set to tMOD if MEMC_FREQ_RATIO=1, or tMOD/2 (rounded up to next integer - # if MEMC_FREQ_RATIO=2. Note that if using RDIMM, depending on the PHY, it may be necessary to use a value of tMOD + 1 or (tMO - # + 1)/2 to compensate for the extra cycle of latency applied to mode register writes by the RDIMM chip. + # tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode com + # mand and following non-load mode command. If C/A parity for DDR4 is used + # , set to tMOD_PAR(tMOD+PL) instead. Set to tMOD if MEMC_FREQ_RATIO=1, or + # tMOD/2 (rounded up to next integer) if MEMC_FREQ_RATIO=2. Note that if + # using RDIMM, depending on the PHY, it may be necessary to use a value of + # tMOD + 1 or (tMOD + 1)/2 to compensate for the extra cycle of latency a + # pplied to mode register writes by the RDIMM chip. # PSU_DDRC_DRAMTMG3_T_MOD 0xc # SDRAM Timing Register 3 @@ -1946,24 +2193,32 @@ set psu_ddr_init_data { mask_write 0XFD07010C 0x3FF3F3FF 0x0050400C # Register : DRAMTMG4 @ 0XFD070110

- # tRCD - tAL: Minimum time from activate to read or write command to same bank. For configurations with MEMC_FREQ_RATIO=2, prog - # am this to ((tRCD - tAL)/2) and round it up to the next integer value. Minimum value allowed for this register is 1, which im - # lies minimum (tRCD - tAL) value to be 2 in configurations with MEMC_FREQ_RATIO=2. Unit: Clocks. + # tRCD - tAL: Minimum time from activate to read or write command to same + # bank. For configurations with MEMC_FREQ_RATIO=2, program this to ((tRCD + # - tAL)/2) and round it up to the next integer value. Minimum value allow + # ed for this register is 1, which implies minimum (tRCD - tAL) value to b + # e 2 in configurations with MEMC_FREQ_RATIO=2. Unit: Clocks. # PSU_DDRC_DRAMTMG4_T_RCD 0x8 - # DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank group. Others: tCCD: This is the minimum - # time between two reads or two writes. For configurations with MEMC_FREQ_RATIO=2, program this to (tCCD_L/2 or tCCD/2) and rou - # d it up to the next integer value. Unit: clocks. + # DDR4: tCCD_L: This is the minimum time between two reads or two writes f + # or same bank group. Others: tCCD: This is the minimum time between two r + # eads or two writes. For configurations with MEMC_FREQ_RATIO=2, program t + # his to (tCCD_L/2 or tCCD/2) and round it up to the next integer value. U + # nit: clocks. # PSU_DDRC_DRAMTMG4_T_CCD 0x3 - # DDR4: tRRD_L: Minimum time between activates from bank 'a' to bank 'b' for same bank group. Others: tRRD: Minimum time betwee - # activates from bank 'a' to bank 'b'For configurations with MEMC_FREQ_RATIO=2, program this to (tRRD_L/2 or tRRD/2) and round - # it up to the next integer value. Unit: Clocks. + # DDR4: tRRD_L: Minimum time between activates from bank 'a' to bank 'b' f + # or same bank group. Others: tRRD: Minimum time between activates from ba + # nk 'a' to bank 'b'For configurations with MEMC_FREQ_RATIO=2, program thi + # s to (tRRD_L/2 or tRRD/2) and round it up to the next integer value. Uni + # t: Clocks. # PSU_DDRC_DRAMTMG4_T_RRD 0x3 - # tRP: Minimum time from precharge to activate of same bank. For MEMC_FREQ_RATIO=1 configurations, t_rp should be set to RoundU - # (tRP/tCK). For MEMC_FREQ_RATIO=2 configurations, t_rp should be set to RoundDown(RoundUp(tRP/tCK)/2) + 1. For MEMC_FREQ_RATIO - # 2 configurations in LPDDR4, t_rp should be set to RoundUp(RoundUp(tRP/tCK)/2). Unit: Clocks. + # tRP: Minimum time from precharge to activate of same bank. For MEMC_FREQ + # _RATIO=1 configurations, t_rp should be set to RoundUp(tRP/tCK). For MEM + # C_FREQ_RATIO=2 configurations, t_rp should be set to RoundDown(RoundUp(t + # RP/tCK)/2) + 1. For MEMC_FREQ_RATIO=2 configurations in LPDDR4, t_rp sho + # uld be set to RoundUp(RoundUp(tRP/tCK)/2). Unit: Clocks. # PSU_DDRC_DRAMTMG4_T_RP 0x9 # SDRAM Timing Register 4 @@ -1971,28 +2226,36 @@ set psu_ddr_init_data { mask_write 0XFD070110 0x1F0F0F1F 0x08030309 # Register : DRAMTMG5 @ 0XFD070114

- # This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stab - # e time before SRX. Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEH - DDR2: 1 - DDR3: tCKSRX - DDR4: - # tCKSRX For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it up to next in - # eger. + # This is the time before Self Refresh Exit that CK is maintained as a val + # id clock before issuing SRX. Specifies the clock stable time before SRX. + # Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCK + # EH - DDR2: 1 - DDR3: tCKSRX - DDR4: tCKSRX For configurations with MEMC_ + # FREQ_RATIO=2, program this to recommended value divided by two and round + # it up to next integer. # PSU_DDRC_DRAMTMG5_T_CKSRX 0x6 - # This is the time after Self Refresh Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay afte - # SRE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL - DDR2: 1 - DDR3: max (10 ns, 5 tCK) - DDR4: - # ax (10 ns, 5 tCK) For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it up - # to next integer. + # This is the time after Self Refresh Down Entry that CK is maintained as + # a valid clock. Specifies the clock disable delay after SRE. Recommended + # settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL - DDR2: 1 + # - DDR3: max (10 ns, 5 tCK) - DDR4: max (10 ns, 5 tCK) For configurations + # with MEMC_FREQ_RATIO=2, program this to recommended value divided by tw + # o and round it up to next integer. # PSU_DDRC_DRAMTMG5_T_CKSRE 0x6 - # Minimum CKE low width for Self refresh or Self refresh power down entry to exit timing in memory clock cycles. Recommended se - # tings: - mDDR: tRFC - LPDDR2: tCKESR - LPDDR3: tCKESR - LPDDR4: max(tCKELPD, tSR) - DDR2: tCKE - DDR3: tCKE + 1 - DDR4: tCKE - # 1 For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it up to next intege - # . + # Minimum CKE low width for Self refresh or Self refresh power down entry + # to exit timing in memory clock cycles. Recommended settings: - mDDR: tRF + # C - LPDDR2: tCKESR - LPDDR3: tCKESR - LPDDR4: max(tCKELPD, tSR) - DDR2: + # tCKE - DDR3: tCKE + 1 - DDR4: tCKE + 1 For configurations with MEMC_FREQ + # _RATIO=2, program this to recommended value divided by two and round it + # up to next integer. # PSU_DDRC_DRAMTMG5_T_CKESR 0x4 - # Minimum number of cycles of CKE HIGH/LOW during power-down and self refresh. - LPDDR2/LPDDR3 mode: Set this to the larger of - # CKE or tCKESR - LPDDR4 mode: Set this to the larger of tCKE, tCKELPD or tSR. - Non-LPDDR2/non-LPDDR3/non-LPDDR4 designs: Set - # his to tCKE value. For configurations with MEMC_FREQ_RATIO=2, program this to (value described above)/2 and round it up to th - # next integer value. Unit: Clocks. + # Minimum number of cycles of CKE HIGH/LOW during power-down and self refr + # esh. - LPDDR2/LPDDR3 mode: Set this to the larger of tCKE or tCKESR - LP + # DDR4 mode: Set this to the larger of tCKE, tCKELPD or tSR. - Non-LPDDR2/ + # non-LPDDR3/non-LPDDR4 designs: Set this to tCKE value. For configuration + # s with MEMC_FREQ_RATIO=2, program this to (value described above)/2 and + # round it up to the next integer value. Unit: Clocks. # PSU_DDRC_DRAMTMG5_T_CKE 0x3 # SDRAM Timing Register 5 @@ -2000,22 +2263,29 @@ set psu_ddr_init_data { mask_write 0XFD070114 0x0F0F3F1F 0x06060403 # Register : DRAMTMG6 @ 0XFD070118

- # This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after - # PDE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 For configurations with MEMC_FREQ_RATIO=2, program this to recom - # ended value divided by two and round it up to next integer. This is only present for designs supporting mDDR or LPDDR2/LPDDR3 - # devices. + # This is the time after Deep Power Down Entry that CK is maintained as a + # valid clock. Specifies the clock disable delay after DPDE. Recommended s + # ettings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 For configurations with MEMC_ + # FREQ_RATIO=2, program this to recommended value divided by two and round + # it up to next integer. This is only present for designs supporting mDDR + # or LPDDR2/LPDDR3 devices. # PSU_DDRC_DRAMTMG6_T_CKDPDE 0x1 - # This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock - # table time before DPDX. Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 For configurations with MEMC_FREQ_RATIO=2, pr - # gram this to recommended value divided by two and round it up to next integer. This is only present for designs supporting mD - # R or LPDDR2 devices. + # This is the time before Deep Power Down Exit that CK is maintained as a + # valid clock before issuing DPDX. Specifies the clock stable time before + # DPDX. Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 For config + # urations with MEMC_FREQ_RATIO=2, program this to recommended value divid + # ed by two and round it up to next integer. This is only present for desi + # gns supporting mDDR or LPDDR2 devices. # PSU_DDRC_DRAMTMG6_T_CKDPDX 0x1 - # This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing Clock Stop Exit. Specifies the - # lock stable time before next command after Clock Stop Exit. Recommended settings: - mDDR: 1 - LPDDR2: tXP + 2 - LPDDR3: tXP + - # 2 - LPDDR4: tXP + 2 For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it - # p to next integer. This is only present for designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices. + # This is the time before Clock Stop Exit that CK is maintained as a valid + # clock before issuing Clock Stop Exit. Specifies the clock stable time b + # efore next command after Clock Stop Exit. Recommended settings: - mDDR: + # 1 - LPDDR2: tXP + 2 - LPDDR3: tXP + 2 - LPDDR4: tXP + 2 For configuratio + # ns with MEMC_FREQ_RATIO=2, program this to recommended value divided by + # two and round it up to next integer. This is only present for designs su + # pporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices. # PSU_DDRC_DRAMTMG6_T_CKCSX 0x4 # SDRAM Timing Register 6 @@ -2023,16 +2293,20 @@ set psu_ddr_init_data { mask_write 0XFD070118 0x0F0F000F 0x01010004 # Register : DRAMTMG7 @ 0XFD07011C

- # This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. - # ecommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL For configurations with MEMC_FREQ_RATIO=2, program t - # is to recommended value divided by two and round it up to next integer. This is only present for designs supporting mDDR or L - # DDR2/LPDDR3/LPDDR4 devices. + # This is the time after Power Down Entry that CK is maintained as a valid + # clock. Specifies the clock disable delay after PDE. Recommended setting + # s: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL For configuration + # s with MEMC_FREQ_RATIO=2, program this to recommended value divided by t + # wo and round it up to next integer. This is only present for designs sup + # porting mDDR or LPDDR2/LPDDR3/LPDDR4 devices. # PSU_DDRC_DRAMTMG7_T_CKPDE 0x6 - # This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable - # time before PDX. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: 2 For configurations with MEMC_FREQ_RATIO= - # , program this to recommended value divided by two and round it up to next integer. This is only present for designs supporti - # g mDDR or LPDDR2/LPDDR3/LPDDR4 devices. + # This is the time before Power Down Exit that CK is maintained as a valid + # clock before issuing PDX. Specifies the clock stable time before PDX. R + # ecommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: 2 For c + # onfigurations with MEMC_FREQ_RATIO=2, program this to recommended value + # divided by two and round it up to next integer. This is only present for + # designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices. # PSU_DDRC_DRAMTMG7_T_CKPDX 0x6 # SDRAM Timing Register 7 @@ -2040,50 +2314,64 @@ set psu_ddr_init_data { mask_write 0XFD07011C 0x00000F0F 0x00000606 # Register : DRAMTMG8 @ 0XFD070120

- # tXS_FAST: Exit Self Refresh to ZQCL, ZQCS and MRS (only CL, WR, RTP and Geardown mode). For configurations with MEMC_FREQ_RAT - # O=2, program this to the above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: Thi - # is applicable to only ZQCL/ZQCS commands. Note: Ensure this is less than or equal to t_xs_x32. - # PSU_DDRC_DRAMTMG8_T_XS_FAST_X32 0x4 + # tXS_FAST: Exit Self Refresh to ZQCL, ZQCS and MRS (only CL, WR, RTP and + # Geardown mode). For configurations with MEMC_FREQ_RATIO=2, program this + # to the above value divided by 2 and round up to next integer value. Unit + # : Multiples of 32 clocks. Note: This is applicable to only ZQCL/ZQCS com + # mands. Note: Ensure this is less than or equal to t_xs_x32. + # PSU_DDRC_DRAMTMG8_T_XS_FAST_X32 0x3 - # tXS_ABORT: Exit Self Refresh to commands not requiring a locked DLL in Self Refresh Abort. For configurations with MEMC_FREQ_ - # ATIO=2, program this to the above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: - # nsure this is less than or equal to t_xs_x32. - # PSU_DDRC_DRAMTMG8_T_XS_ABORT_X32 0x4 + # tXS_ABORT: Exit Self Refresh to commands not requiring a locked DLL in S + # elf Refresh Abort. For configurations with MEMC_FREQ_RATIO=2, program th + # is to the above value divided by 2 and round up to next integer value. U + # nit: Multiples of 32 clocks. Note: Ensure this is less than or equal to + # t_xs_x32. + # PSU_DDRC_DRAMTMG8_T_XS_ABORT_X32 0x3 - # tXSDLL: Exit Self Refresh to commands requiring a locked DLL. For configurations with MEMC_FREQ_RATIO=2, program this to the - # bove value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: Used only for DDR2, DDR3 and - # DR4 SDRAMs. + # tXSDLL: Exit Self Refresh to commands requiring a locked DLL. For config + # urations with MEMC_FREQ_RATIO=2, program this to the above value divided + # by 2 and round up to next integer value. Unit: Multiples of 32 clocks. + # Note: Used only for DDR2, DDR3 and DDR4 SDRAMs. # PSU_DDRC_DRAMTMG8_T_XS_DLL_X32 0xd - # tXS: Exit Self Refresh to commands not requiring a locked DLL. For configurations with MEMC_FREQ_RATIO=2, program this to the - # above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: Used only for DDR2, DDR3 and - # DDR4 SDRAMs. + # tXS: Exit Self Refresh to commands not requiring a locked DLL. For confi + # gurations with MEMC_FREQ_RATIO=2, program this to the above value divide + # d by 2 and round up to next integer value. Unit: Multiples of 32 clocks. + # Note: Used only for DDR2, DDR3 and DDR4 SDRAMs. # PSU_DDRC_DRAMTMG8_T_XS_X32 0x6 # SDRAM Timing Register 8 - #(OFFSET, MASK, VALUE) (0XFD070120, 0x7F7F7F7FU ,0x04040D06U) */ - mask_write 0XFD070120 0x7F7F7F7F 0x04040D06 + #(OFFSET, MASK, VALUE) (0XFD070120, 0x7F7F7F7FU ,0x03030D06U) */ + mask_write 0XFD070120 0x7F7F7F7F 0x03030D06 # Register : DRAMTMG9 @ 0XFD070124

- # DDR4 Write preamble mode - 0: 1tCK preamble - 1: 2tCK preamble Present only with MEMC_FREQ_RATIO=2 + # DDR4 Write preamble mode - 0: 1tCK preamble - 1: 2tCK preamble Present o + # nly with MEMC_FREQ_RATIO=2 # PSU_DDRC_DRAMTMG9_DDR4_WR_PREAMBLE 0x0 - # tCCD_S: This is the minimum time between two reads or two writes for different bank group. For bank switching (from bank 'a' - # o bank 'b'), the minimum time is this value + 1. For configurations with MEMC_FREQ_RATIO=2, program this to (tCCD_S/2) and ro - # nd it up to the next integer value. Present only in designs configured to support DDR4. Unit: clocks. + # tCCD_S: This is the minimum time between two reads or two writes for dif + # ferent bank group. For bank switching (from bank 'a' to bank 'b'), the m + # inimum time is this value + 1. For configurations with MEMC_FREQ_RATIO=2 + # , program this to (tCCD_S/2) and round it up to the next integer value. + # Present only in designs configured to support DDR4. Unit: clocks. # PSU_DDRC_DRAMTMG9_T_CCD_S 0x2 - # tRRD_S: Minimum time between activates from bank 'a' to bank 'b' for different bank group. For configurations with MEMC_FREQ_ - # ATIO=2, program this to (tRRD_S/2) and round it up to the next integer value. Present only in designs configured to support D - # R4. Unit: Clocks. + # tRRD_S: Minimum time between activates from bank 'a' to bank 'b' for dif + # ferent bank group. For configurations with MEMC_FREQ_RATIO=2, program th + # is to (tRRD_S/2) and round it up to the next integer value. Present only + # in designs configured to support DDR4. Unit: Clocks. # PSU_DDRC_DRAMTMG9_T_RRD_S 0x2 - # CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command for different bank group. Includes time for bus turn - # round, recovery times, and all per-bank, per-rank, and global constraints. Present only in designs configured to support DDR4 - # Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity latency - BL = burst length. This must match the value programm - # d in the BL bit of the mode register to the SDRAM - tWTR_S = internal write to read command delay for different bank group. T - # is comes directly from the SDRAM specification. For configurations with MEMC_FREQ_RATIO=2, divide the value calculated using - # he above equation by 2, and round it up to next integer. + # CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command + # for different bank group. Includes time for bus turnaround, recovery ti + # mes, and all per-bank, per-rank, and global constraints. Present only in + # designs configured to support DDR4. Unit: Clocks. Where: - CWL = CAS wr + # ite latency - PL = Parity latency - BL = burst length. This must match t + # he value programmed in the BL bit of the mode register to the SDRAM - tW + # TR_S = internal write to read command delay for different bank group. Th + # is comes directly from the SDRAM specification. For configurations with + # MEMC_FREQ_RATIO=2, divide the value calculated using the above equation + # by 2, and round it up to next integer. # PSU_DDRC_DRAMTMG9_WR2RD_S 0xb # SDRAM Timing Register 9 @@ -2091,39 +2379,48 @@ set psu_ddr_init_data { mask_write 0XFD070124 0x40070F3F 0x0002020B # Register : DRAMTMG11 @ 0XFD07012C

- # tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DLL. For configurations with MEMC_FREQ_RATIO=2, program - # this to (tXMPDLL/2) and round it up to the next integer value. Present only in designs configured to support DDR4. Unit: Mult - # ples of 32 clocks. - # PSU_DDRC_DRAMTMG11_POST_MPSM_GAP_X32 0x6f + # tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DL + # L. For configurations with MEMC_FREQ_RATIO=2, program this to (tXMPDLL/2 + # ) and round it up to the next integer value. Present only in designs con + # figured to support DDR4. Unit: Multiples of 32 clocks. + # PSU_DDRC_DRAMTMG11_POST_MPSM_GAP_X32 0x70 - # tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge. For configurations with MEMC_FREQ_RATIO=2, program this t - # RoundUp(tMPX_LH/2)+1. Present only in designs configured to support DDR4. Unit: clocks. + # tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge. For + # configurations with MEMC_FREQ_RATIO=2, program this to RoundUp(tMPX_LH/2 + # )+1. Present only in designs configured to support DDR4. Unit: clocks. # PSU_DDRC_DRAMTMG11_T_MPX_LH 0x7 - # tMPX_S: Minimum time CS setup time to CKE. For configurations with MEMC_FREQ_RATIO=2, program this to (tMPX_S/2) and round it - # up to the next integer value. Present only in designs configured to support DDR4. Unit: Clocks. + # tMPX_S: Minimum time CS setup time to CKE. For configurations with MEMC_ + # FREQ_RATIO=2, program this to (tMPX_S/2) and round it up to the next int + # eger value. Present only in designs configured to support DDR4. Unit: Cl + # ocks. # PSU_DDRC_DRAMTMG11_T_MPX_S 0x1 - # tCKMPE: Minimum valid clock requirement after MPSM entry. Present only in designs configured to support DDR4. Unit: Clocks. F - # r configurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next i - # teger. + # tCKMPE: Minimum valid clock requirement after MPSM entry. Present only i + # n designs configured to support DDR4. Unit: Clocks. For configurations w + # ith MEMC_FREQ_RATIO=2, divide the value calculated using the above equat + # ion by 2, and round it up to next integer. # PSU_DDRC_DRAMTMG11_T_CKMPE 0xe # SDRAM Timing Register 11 - #(OFFSET, MASK, VALUE) (0XFD07012C, 0x7F1F031FU ,0x6F07010EU) */ - mask_write 0XFD07012C 0x7F1F031F 0x6F07010E + #(OFFSET, MASK, VALUE) (0XFD07012C, 0x7F1F031FU ,0x7007010EU) */ + mask_write 0XFD07012C 0x7F1F031F 0x7007010E # Register : DRAMTMG12 @ 0XFD070130

- # tCMDCKE: Delay from valid command to CKE input LOW. Set this to the larger of tESCKE or tCMDCKE For configurations with MEMC_ - # REQ_RATIO=2, program this to (max(tESCKE, tCMDCKE)/2) and round it up to next integer value. + # tCMDCKE: Delay from valid command to CKE input LOW. Set this to the larg + # er of tESCKE or tCMDCKE For configurations with MEMC_FREQ_RATIO=2, progr + # am this to (max(tESCKE, tCMDCKE)/2) and round it up to next integer valu + # e. # PSU_DDRC_DRAMTMG12_T_CMDCKE 0x2 - # tCKEHCMD: Valid command requirement after CKE input HIGH. For configurations with MEMC_FREQ_RATIO=2, program this to (tCKEHCM - # /2) and round it up to next integer value. + # tCKEHCMD: Valid command requirement after CKE input HIGH. For configurat + # ions with MEMC_FREQ_RATIO=2, program this to (tCKEHCMD/2) and round it u + # p to next integer value. # PSU_DDRC_DRAMTMG12_T_CKEHCMD 0x6 - # tMRD_PDA: This is the Mode Register Set command cycle time in PDA mode. For configurations with MEMC_FREQ_RATIO=2, program th - # s to (tMRD_PDA/2) and round it up to next integer value. + # tMRD_PDA: This is the Mode Register Set command cycle time in PDA mode. + # For configurations with MEMC_FREQ_RATIO=2, program this to (tMRD_PDA/2) + # and round it up to next integer value. # PSU_DDRC_DRAMTMG12_T_MRD_PDA 0x8 # SDRAM Timing Register 12 @@ -2131,38 +2428,51 @@ set psu_ddr_init_data { mask_write 0XFD070130 0x00030F1F 0x00020608 # Register : ZQCTL0 @ 0XFD070180

- # - 1 - Disable uMCTL2 generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used instead to is - # ue ZQ calibration request from APB module. - 0 - Internally generate ZQCS/MPC(ZQ calibration) commands based on ZQCTL1.t_zq_s - # ort_interval_x1024. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. + # - 1 - Disable uMCTL2 generation of ZQCS/MPC(ZQ calibration) command. Reg + # ister DBGCMD.zq_calib_short can be used instead to issue ZQ calibration + # request from APB module. - 0 - Internally generate ZQCS/MPC(ZQ calibrati + # on) commands based on ZQCTL1.t_zq_short_interval_x1024. This is only pre + # sent for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. # PSU_DDRC_ZQCTL0_DIS_AUTO_ZQ 0x1 - # - 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable when run in DDR3 - # or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. - 0 - Enable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Power - # own exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. This is only present for designs suppo - # ting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. + # - 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refres + # h/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 + # or LPDDR3 or LPDDR4 mode. - 0 - Enable issuing of ZQCL/MPC(ZQ calibratio + # n) command at Self-Refresh/SR-Powerdown exit. Only applicable when run i + # n DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. This is only present + # for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. # PSU_DDRC_ZQCTL0_DIS_SRX_ZQCL 0x0 - # - 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are sent to one r - # nk at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to different ranks do not ov - # rlap. - 0 - ZQ resistor is not shared. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. + # - 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQC + # L/ZQCS/MPC(ZQ calibration) commands are sent to one rank at a time with + # tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that co + # mmands to different ranks do not overlap. - 0 - ZQ resistor is not share + # d. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR + # 3/LPDDR4 devices. # PSU_DDRC_ZQCTL0_ZQ_RESISTOR_SHARED 0x0 - # - 1 - Disable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode. - 0 - Enable - # ssuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode. This is only present for des - # gns supporting DDR4 devices. + # - 1 - Disable issuing of ZQCL command at Maximum Power Saving Mode exit. + # Only applicable when run in DDR4 mode. - 0 - Enable issuing of ZQCL com + # mand at Maximum Power Saving Mode exit. Only applicable when run in DDR4 + # mode. This is only present for designs supporting DDR4 devices. # PSU_DDRC_ZQCTL0_DIS_MPSMX_ZQCL 0x0 - # tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Number of cycles of NOP required after a ZQCL (ZQ calibrat - # on long)/MPC(ZQ Start) command is issued to SDRAM. For configurations with MEMC_FREQ_RATIO=2: DDR3/DDR4: program this to tZQo - # er/2 and round it up to the next integer value. LPDDR2/LPDDR3: program this to tZQCL/2 and round it up to the next integer va - # ue. LPDDR4: program this to tZQCAL/2 and round it up to the next integer value. Unit: Clock cycles. This is only present for - # esigns supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. + # tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Numbe + # r of cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ St + # art) command is issued to SDRAM. For configurations with MEMC_FREQ_RATIO + # =2: DDR3/DDR4: program this to tZQoper/2 and round it up to the next int + # eger value. LPDDR2/LPDDR3: program this to tZQCL/2 and round it up to th + # e next integer value. LPDDR4: program this to tZQCAL/2 and round it up t + # o the next integer value. Unit: Clock cycles. This is only present for d + # esigns supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. # PSU_DDRC_ZQCTL0_T_ZQ_LONG_NOP 0x100 - # tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of cycles of NOP required after a ZQCS (ZQ calibration short)/MPC - # ZQ Latch) command is issued to SDRAM. For configurations with MEMC_FREQ_RATIO=2, program this to tZQCS/2 and round it up to t - # e next integer value. Unit: Clock cycles. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devic - # s. + # tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of cycles of + # NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command + # is issued to SDRAM. For configurations with MEMC_FREQ_RATIO=2, program t + # his to tZQCS/2 and round it up to the next integer value. Unit: Clock cy + # cles. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LP + # DDR3/LPDDR4 devices. # PSU_DDRC_ZQCTL0_T_ZQ_SHORT_NOP 0x40 # ZQ Control Register 0 @@ -2170,53 +2480,70 @@ set psu_ddr_init_data { mask_write 0XFD070180 0xF7FF03FF 0x81000040 # Register : ZQCTL1 @ 0XFD070184

- # tZQReset: Number of cycles of NOP required after a ZQReset (ZQ calibration Reset) command is issued to SDRAM. For configurati - # ns with MEMC_FREQ_RATIO=2, program this to tZQReset/2 and round it up to the next integer value. Unit: Clock cycles. This is - # nly present for designs supporting LPDDR2/LPDDR3/LPDDR4 devices. + # tZQReset: Number of cycles of NOP required after a ZQReset (ZQ calibrati + # on Reset) command is issued to SDRAM. For configurations with MEMC_FREQ_ + # RATIO=2, program this to tZQReset/2 and round it up to the next integer + # value. Unit: Clock cycles. This is only present for designs supporting L + # PDDR2/LPDDR3/LPDDR4 devices. # PSU_DDRC_ZQCTL1_T_ZQ_RESET_NOP 0x20 - # Average interval to wait between automatically issuing ZQCS (ZQ calibration short)/MPC(ZQ calibration) commands to DDR3/DDR4/ - # PDDR2/LPDDR3/LPDDR4 devices. Meaningless, if ZQCTL0.dis_auto_zq=1. Unit: 1024 clock cycles. This is only present for designs - # upporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. - # PSU_DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024 0x19707 + # Average interval to wait between automatically issuing ZQCS (ZQ calibrat + # ion short)/MPC(ZQ calibration) commands to DDR3/DDR4/LPDDR2/LPDDR3/LPDDR + # 4 devices. Meaningless, if ZQCTL0.dis_auto_zq=1. Unit: 1024 clock cycles + # . This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3 + # /LPDDR4 devices. + # PSU_DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024 0x196dc # ZQ Control Register 1 - #(OFFSET, MASK, VALUE) (0XFD070184, 0x3FFFFFFFU ,0x02019707U) */ - mask_write 0XFD070184 0x3FFFFFFF 0x02019707 + #(OFFSET, MASK, VALUE) (0XFD070184, 0x3FFFFFFFU ,0x020196DCU) */ + mask_write 0XFD070184 0x3FFFFFFF 0x020196DC # Register : DFITMG0 @ 0XFD070190

- # Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signa - # s at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligne - # , this timing parameter should be rounded up to the next integer value. Note that if using RDIMM, it is necessary to incremen - # this parameter by RDIMM's extra cycle of latency in terms of DFI clock. + # Specifies the number of DFI clock cycles after an assertion or de-assert + # ion of the DFI control signals that the control signals at the PHY-DRAM + # interface reflect the assertion or de-assertion. If the DFI clock and th + # e memory clock are not phase-aligned, this timing parameter should be ro + # unded up to the next integer value. Note that if using RDIMM, it is nece + # ssary to increment this parameter by RDIMM's extra cycle of latency in t + # erms of DFI clock. # PSU_DDRC_DFITMG0_DFI_T_CTRL_DELAY 0x4 - # Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR or SDR values Selects whether value in DFITM - # 0.dfi_t_rddata_en is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles R - # fer to PHY specification for correct value. + # Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated u + # sing HDR or SDR values Selects whether value in DFITMG0.dfi_t_rddata_en + # is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles + # - 1 in terms of SDR clock cycles Refer to PHY specification for correct + # value. # PSU_DDRC_DFITMG0_DFI_RDDATA_USE_SDR 0x1 - # Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. Refer to PHY spe - # ification for correct value. This corresponds to the DFI parameter trddata_en. Note that, depending on the PHY, if using RDIM - # , it may be necessary to use the value (CL + 1) in the calculation of trddata_en. This is to compensate for the extra cycle o - # latency through the RDIMM. Unit: Clocks + # Time from the assertion of a read command on the DFI interface to the as + # sertion of the dfi_rddata_en signal. Refer to PHY specification for corr + # ect value. This corresponds to the DFI parameter trddata_en. Note that, + # depending on the PHY, if using RDIMM, it may be necessary to use the val + # ue (CL + 1) in the calculation of trddata_en. This is to compensate for + # the extra cycle of latency through the RDIMM. Unit: Clocks # PSU_DDRC_DFITMG0_DFI_T_RDDATA_EN 0xb - # Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using HDR or SDR values Selects whether value in DFITMG - # .dfi_tphy_wrlat is in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.dfi_tphy_wrdata is in terms of SDR or - # HDR clock cycles - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles Refer to PHY specification for correct val - # e. + # Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated us + # ing HDR or SDR values Selects whether value in DFITMG0.dfi_tphy_wrlat is + # in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.df + # i_tphy_wrdata is in terms of SDR or HDR clock cycles - 0 in terms of HDR + # clock cycles - 1 in terms of SDR clock cycles Refer to PHY specificatio + # n for correct value. # PSU_DDRC_DFITMG0_DFI_WRDATA_USE_SDR 0x1 - # Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on th - # dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. N - # te, max supported value is 8. Unit: Clocks + # Specifies the number of clock cycles between when dfi_wrdata_en is asser + # ted to when the associated write data is driven on the dfi_wrdata signal + # . This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY + # specification for correct value. Note, max supported value is 8. Unit: + # Clocks # PSU_DDRC_DFITMG0_DFI_TPHY_WRDATA 0x2 - # Write latency Number of clocks from the write command to write data enable (dfi_wrdata_en). This corresponds to the DFI timin - # parameter tphy_wrlat. Refer to PHY specification for correct value.Note that, depending on the PHY, if using RDIMM, it may b - # necessary to use the value (CL + 1) in the calculation of tphy_wrlat. This is to compensate for the extra cycle of latency t - # rough the RDIMM. + # Write latency Number of clocks from the write command to write data enab + # le (dfi_wrdata_en). This corresponds to the DFI timing parameter tphy_wr + # lat. Refer to PHY specification for correct value.Note that, depending o + # n the PHY, if using RDIMM, it may be necessary to use the value (CL + 1) + # in the calculation of tphy_wrlat. This is to compensate for the extra c + # ycle of latency through the RDIMM. # PSU_DDRC_DFITMG0_DFI_TPHY_WRLAT 0xb # DFI Timing Register 0 @@ -2224,31 +2551,40 @@ set psu_ddr_init_data { mask_write 0XFD070190 0x1FBFBF3F 0x048B820B # Register : DFITMG1 @ 0XFD070194

- # Specifies the number of DFI PHY clocks between when the dfi_cs signal is asserted and when the associated command is driven. - # his field is used for CAL mode, should be set to '0' or the value which matches the CAL mode register setting in the DRAM. If - # the PHY can add the latency for CAL mode, this should be set to '0'. Valid Range: 0, 3, 4, 5, 6, and 8 + # Specifies the number of DFI PHY clocks between when the dfi_cs signal is + # asserted and when the associated command is driven. This field is used + # for CAL mode, should be set to '0' or the value which matches the CAL mo + # de register setting in the DRAM. If the PHY can add the latency for CAL + # mode, this should be set to '0'. Valid Range: 0, 3, 4, 5, 6, and 8 # PSU_DDRC_DFITMG1_DFI_T_CMD_LAT 0x0 - # Specifies the number of DFI PHY clocks between when the dfi_cs signal is asserted and when the associated dfi_parity_in signa - # is driven. + # Specifies the number of DFI PHY clocks between when the dfi_cs signal is + # asserted and when the associated dfi_parity_in signal is driven. # PSU_DDRC_DFITMG1_DFI_T_PARIN_LAT 0x0 - # Specifies the number of DFI clocks between when the dfi_wrdata_en signal is asserted and when the corresponding write data tr - # nsfer is completed on the DRAM bus. This corresponds to the DFI timing parameter twrdata_delay. Refer to PHY specification fo - # correct value. For DFI 3.0 PHY, set to twrdata_delay, a new timing parameter introduced in DFI 3.0. For DFI 2.1 PHY, set to - # phy_wrdata + (delay of DFI write data to the DRAM). Value to be programmed is in terms of DFI clocks, not PHY clocks. In FREQ - # RATIO=2, divide PHY's value by 2 and round up to next integer. If using DFITMG0.dfi_wrdata_use_sdr=1, add 1 to the value. Uni - # : Clocks + # Specifies the number of DFI clocks between when the dfi_wrdata_en signal + # is asserted and when the corresponding write data transfer is completed + # on the DRAM bus. This corresponds to the DFI timing parameter twrdata_d + # elay. Refer to PHY specification for correct value. For DFI 3.0 PHY, set + # to twrdata_delay, a new timing parameter introduced in DFI 3.0. For DFI + # 2.1 PHY, set to tphy_wrdata + (delay of DFI write data to the DRAM). Va + # lue to be programmed is in terms of DFI clocks, not PHY clocks. In FREQ_ + # RATIO=2, divide PHY's value by 2 and round up to next integer. If using + # DFITMG0.dfi_wrdata_use_sdr=1, add 1 to the value. Unit: Clocks # PSU_DDRC_DFITMG1_DFI_T_WRDATA_DELAY 0x3 - # Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to - # he DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase - # ligned, this timing parameter should be rounded up to the next integer value. + # Specifies the number of DFI clock cycles from the assertion of the dfi_d + # ram_clk_disable signal on the DFI until the clock to the DRAM memory dev + # ices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock + # and the memory clock are not phase aligned, this timing parameter should + # be rounded up to the next integer value. # PSU_DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE 0x3 - # Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first - # alid rising edge of the clock to the DRAM memory devices, at the PHY-DRAM boundary. If the DFI clock and the memory clock are - # not phase aligned, this timing parameter should be rounded up to the next integer value. + # Specifies the number of DFI clock cycles from the de-assertion of the df + # i_dram_clk_disable signal on the DFI until the first valid rising edge o + # f the clock to the DRAM memory devices, at the PHY-DRAM boundary. If the + # DFI clock and the memory clock are not phase aligned, this timing param + # eter should be rounded up to the next integer value. # PSU_DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE 0x4 # DFI Timing Register 1 @@ -2256,37 +2592,48 @@ set psu_ddr_init_data { mask_write 0XFD070194 0xF31F0F0F 0x00030304 # Register : DFILPCFG0 @ 0XFD070198

- # Setting for DFI's tlp_resp time. Same value is used for both Power Down, Self Refresh, Deep Power Down and Maximum Power Savi - # g modes. DFI 2.1 specification onwards, recommends using a fixed value of 7 always. + # Setting for DFI's tlp_resp time. Same value is used for both Power Down, + # Self Refresh, Deep Power Down and Maximum Power Saving modes. DFI 2.1 s + # pecification onwards, recommends using a fixed value of 7 always. # PSU_DDRC_DFILPCFG0_DFI_TLP_RESP 0x7 - # Value to drive on dfi_lp_wakeup signal when Deep Power Down mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 - # cycles - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles - 0x7 - # - 2048 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0xD - - # 31072 cycles - 0xE - 262144 cycles - 0xF - Unlimited This is only present for designs supporting mDDR or LPDDR2/LPDDR3 device - # . + # Value to drive on dfi_lp_wakeup signal when Deep Power Down mode is ente + # red. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32 + # cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 5 + # 12 cycles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycles - + # 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 6553 + # 6 cycles - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited T + # his is only present for designs supporting mDDR or LPDDR2/LPDDR3 devices + # . # PSU_DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD 0x0 - # Enables DFI Low Power interface handshaking during Deep Power Down Entry/Exit. - 0 - Disabled - 1 - Enabled This is only pres - # nt for designs supporting mDDR or LPDDR2/LPDDR3 devices. + # Enables DFI Low Power interface handshaking during Deep Power Down Entry + # /Exit. - 0 - Disabled - 1 - Enabled This is only present for designs sup + # porting mDDR or LPDDR2/LPDDR3 devices. # PSU_DDRC_DFILPCFG0_DFI_LP_EN_DPD 0x0 - # Value to drive on dfi_lp_wakeup signal when Self Refresh mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cy - # les - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles - 0x7 - - # 048 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0xD - 131 - # 72 cycles - 0xE - 262144 cycles - 0xF - Unlimited + # Value to drive on dfi_lp_wakeup signal when Self Refresh mode is entered + # . Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32 cyc + # les - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 + # cycles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycles - 0x9 + # - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 c + # ycles - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited # PSU_DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR 0x0 - # Enables DFI Low Power interface handshaking during Self Refresh Entry/Exit. - 0 - Disabled - 1 - Enabled + # Enables DFI Low Power interface handshaking during Self Refresh Entry/Ex + # it. - 0 - Disabled - 1 - Enabled # PSU_DDRC_DFILPCFG0_DFI_LP_EN_SR 0x1 - # Value to drive on dfi_lp_wakeup signal when Power Down mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycl - # s - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles - 0x7 - 20 - # 8 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0xD - 13107 - # cycles - 0xE - 262144 cycles - 0xF - Unlimited + # Value to drive on dfi_lp_wakeup signal when Power Down mode is entered. + # Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32 cycle + # s - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cy + # cles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycles - 0x9 - + # 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cyc + # les - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited # PSU_DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD 0x0 - # Enables DFI Low Power interface handshaking during Power Down Entry/Exit. - 0 - Disabled - 1 - Enabled + # Enables DFI Low Power interface handshaking during Power Down Entry/Exit + # . - 0 - Disabled - 1 - Enabled # PSU_DDRC_DFILPCFG0_DFI_LP_EN_PD 0x1 # DFI Low Power Configuration Register 0 @@ -2294,48 +2641,88 @@ set psu_ddr_init_data { mask_write 0XFD070198 0x0FF1F1F1 0x07000101 # Register : DFILPCFG1 @ 0XFD07019C

- # Value to drive on dfi_lp_wakeup signal when Maximum Power Saving Mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - # - 16 cycles - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles - # 0x7 - 2048 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0 - # D - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited This is only present for designs supporting DDR4 devices. + # Value to drive on dfi_lp_wakeup signal when Maximum Power Saving Mode is + # entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 + # - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x + # 5 - 512 cycles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycl + # es - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - + # 65536 cycles - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimi + # ted This is only present for designs supporting DDR4 devices. # PSU_DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM 0x2 - # Enables DFI Low Power interface handshaking during Maximum Power Saving Mode Entry/Exit. - 0 - Disabled - 1 - Enabled This is - # only present for designs supporting DDR4 devices. + # Enables DFI Low Power interface handshaking during Maximum Power Saving + # Mode Entry/Exit. - 0 - Disabled - 1 - Enabled This is only present for d + # esigns supporting DDR4 devices. # PSU_DDRC_DFILPCFG1_DFI_LP_EN_MPSM 0x1 # DFI Low Power Configuration Register 1 #(OFFSET, MASK, VALUE) (0XFD07019C, 0x000000F1U ,0x00000021U) */ mask_write 0XFD07019C 0x000000F1 0x00000021 + # Register : DFIUPD0 @ 0XFD0701A0

+ + # When '1', disable the automatic dfi_ctrlupd_req generation by the uMCTL2 + # . The core must issue the dfi_ctrlupd_req signal using register reg_ddrc + # _ctrlupd. When '0', uMCTL2 issues dfi_ctrlupd_req periodically. + # PSU_DDRC_DFIUPD0_DIS_AUTO_CTRLUPD 0x0 + + # When '1', disable the automatic dfi_ctrlupd_req generation by the uMCTL2 + # following a self-refresh exit. The core must issue the dfi_ctrlupd_req + # signal using register reg_ddrc_ctrlupd. When '0', uMCTL2 issues a dfi_ct + # rlupd_req after exiting self-refresh. + # PSU_DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX 0x0 + + # Specifies the maximum number of clock cycles that the dfi_ctrlupd_req si + # gnal can assert. Lowest value to assign to this variable is 0x40. Unit: + # Clocks + # PSU_DDRC_DFIUPD0_DFI_T_CTRLUP_MAX 0x40 + + # Specifies the minimum number of clock cycles that the dfi_ctrlupd_req si + # gnal must be asserted. The uMCTL2 expects the PHY to respond within this + # time. If the PHY does not respond, the uMCTL2 will de-assert dfi_ctrlup + # d_req after dfi_t_ctrlup_min + 2 cycles. Lowest value to assign to this + # variable is 0x3. Unit: Clocks + # PSU_DDRC_DFIUPD0_DFI_T_CTRLUP_MIN 0x3 + + # DFI Update Register 0 + #(OFFSET, MASK, VALUE) (0XFD0701A0, 0xC3FF03FFU ,0x00400003U) */ + mask_write 0XFD0701A0 0xC3FF03FF 0x00400003 # Register : DFIUPD1 @ 0XFD0701A4

- # This is the minimum amount of time between uMCTL2 initiated DFI update requests (which is executed whenever the uMCTL2 is idl - # ). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the fir - # t read request when the uMCTL2 is idle. Unit: 1024 clocks + # This is the minimum amount of time between uMCTL2 initiated DFI update r + # equests (which is executed whenever the uMCTL2 is idle). Set this number + # higher to reduce the frequency of update requests, which can have a sma + # ll impact on the latency of the first read request when the uMCTL2 is id + # le. Unit: 1024 clocks # PSU_DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024 0x41 - # This is the maximum amount of time between uMCTL2 initiated DFI update requests. This timer resets with each update request; - # hen the timer expires dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd_ackx is received. PHY can use this - # idle time to recalibrate the delay lines to the DLLs. The DFI controller update is also used to reset PHY FIFO pointers in ca - # e of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. - # Note: Value programmed for DFIUPD1.dfi_t_ctrlupd_interval_max_x1024 must be greater than DFIUPD1.dfi_t_ctrlupd_interval_min_x - # 024. Unit: 1024 clocks - # PSU_DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024 0xe2 + # This is the maximum amount of time between uMCTL2 initiated DFI update r + # equests. This timer resets with each update request; when the timer expi + # res dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd + # _ackx is received. PHY can use this idle time to recalibrate the delay l + # ines to the DLLs. The DFI controller update is also used to reset PHY FI + # FO pointers in case of data capture errors. Updates are required to main + # tain calibration over PVT, but frequent updates may impact performance. + # Note: Value programmed for DFIUPD1.dfi_t_ctrlupd_interval_max_x1024 must + # be greater than DFIUPD1.dfi_t_ctrlupd_interval_min_x1024. Unit: 1024 cl + # ocks + # PSU_DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024 0xe1 # DFI Update Register 1 - #(OFFSET, MASK, VALUE) (0XFD0701A4, 0x00FF00FFU ,0x004100E2U) */ - mask_write 0XFD0701A4 0x00FF00FF 0x004100E2 + #(OFFSET, MASK, VALUE) (0XFD0701A4, 0x00FF00FFU ,0x004100E1U) */ + mask_write 0XFD0701A4 0x00FF00FF 0x004100E1 # Register : DFIMISC @ 0XFD0701B0

- # Defines polarity of dfi_wrdata_cs and dfi_rddata_cs signals. - 0: Signals are active low - 1: Signals are active high + # Defines polarity of dfi_wrdata_cs and dfi_rddata_cs signals. - 0: Signal + # s are active low - 1: Signals are active high # PSU_DDRC_DFIMISC_DFI_DATA_CS_POLARITY 0x0 - # DBI implemented in DDRC or PHY. - 0 - DDRC implements DBI functionality. - 1 - PHY implements DBI functionality. Present only - # in designs configured to support DDR4 and LPDDR4. + # DBI implemented in DDRC or PHY. - 0 - DDRC implements DBI functionality. + # - 1 - PHY implements DBI functionality. Present only in designs configu + # red to support DDR4 and LPDDR4. # PSU_DDRC_DFIMISC_PHY_DBI_MODE 0x0 - # PHY initialization complete enable signal. When asserted the dfi_init_complete signal can be used to trigger SDRAM initialisa - # ion + # PHY initialization complete enable signal. When asserted the dfi_init_co + # mplete signal can be used to trigger SDRAM initialisation # PSU_DDRC_DFIMISC_DFI_INIT_COMPLETE_EN 0x0 # DFI Miscellaneous Control Register @@ -2343,12 +2730,16 @@ set psu_ddr_init_data { mask_write 0XFD0701B0 0x00000007 0x00000000 # Register : DFITMG2 @ 0XFD0701B4

- # >Number of clocks between when a read command is sent on the DFI control interface and when the associated dfi_rddata_cs sign - # l is asserted. This corresponds to the DFI timing parameter tphy_rdcslat. Refer to PHY specification for correct value. + # >Number of clocks between when a read command is sent on the DFI control + # interface and when the associated dfi_rddata_cs signal is asserted. Thi + # s corresponds to the DFI timing parameter tphy_rdcslat. Refer to PHY spe + # cification for correct value. # PSU_DDRC_DFITMG2_DFI_TPHY_RDCSLAT 0x9 - # Number of clocks between when a write command is sent on the DFI control interface and when the associated dfi_wrdata_cs sign - # l is asserted. This corresponds to the DFI timing parameter tphy_wrcslat. Refer to PHY specification for correct value. + # Number of clocks between when a write command is sent on the DFI control + # interface and when the associated dfi_wrdata_cs signal is asserted. Thi + # s corresponds to the DFI timing parameter tphy_wrcslat. Refer to PHY spe + # cification for correct value. # PSU_DDRC_DFITMG2_DFI_TPHY_WRCSLAT 0x6 # DFI Timing Register 2 @@ -2356,17 +2747,23 @@ set psu_ddr_init_data { mask_write 0XFD0701B4 0x00003F3F 0x00000906 # Register : DBICTL @ 0XFD0701C0

- # Read DBI enable signal in DDRC. - 0 - Read DBI is disabled. - 1 - Read DBI is enabled. This signal must be set the same value - # as DRAM's mode register. - DDR4: MR5 bit A12. When x4 devices are used, this signal must be set to 0. - LPDDR4: MR3[6] + # Read DBI enable signal in DDRC. - 0 - Read DBI is disabled. - 1 - Read D + # BI is enabled. This signal must be set the same value as DRAM's mode reg + # ister. - DDR4: MR5 bit A12. When x4 devices are used, this signal must b + # e set to 0. - LPDDR4: MR3[6] # PSU_DDRC_DBICTL_RD_DBI_EN 0x0 - # Write DBI enable signal in DDRC. - 0 - Write DBI is disabled. - 1 - Write DBI is enabled. This signal must be set the same va - # ue as DRAM's mode register. - DDR4: MR5 bit A11. When x4 devices are used, this signal must be set to 0. - LPDDR4: MR3[7] + # Write DBI enable signal in DDRC. - 0 - Write DBI is disabled. - 1 - Writ + # e DBI is enabled. This signal must be set the same value as DRAM's mode + # register. - DDR4: MR5 bit A11. When x4 devices are used, this signal mus + # t be set to 0. - LPDDR4: MR3[7] # PSU_DDRC_DBICTL_WR_DBI_EN 0x0 - # DM enable signal in DDRC. - 0 - DM is disabled. - 1 - DM is enabled. This signal must be set the same logical value as DRAM's - # mode register. - DDR4: Set this to same value as MR5 bit A10. When x4 devices are used, this signal must be set to 0. - LPDDR - # : Set this to inverted value of MR13[5] which is opposite polarity from this signal + # DM enable signal in DDRC. - 0 - DM is disabled. - 1 - DM is enabled. Thi + # s signal must be set the same logical value as DRAM's mode register. - D + # DR4: Set this to same value as MR5 bit A10. When x4 devices are used, th + # is signal must be set to 0. - LPDDR4: Set this to inverted value of MR13 + # [5] which is opposite polarity from this signal # PSU_DDRC_DBICTL_DM_EN 0x1 # DM/DBI Control Register @@ -2374,8 +2771,10 @@ set psu_ddr_init_data { mask_write 0XFD0701C0 0x00000007 0x00000001 # Register : ADDRMAP0 @ 0XFD070200

- # Selects the HIF address bit used as rank address bit 0. Valid Range: 0 to 27, and 31 Internal Base: 6 The selected HIF addres - # bit is determined by adding the internal base to the value of this field. If set to 31, rank address bit 0 is set to 0. + # Selects the HIF address bit used as rank address bit 0. Valid Range: 0 t + # o 27, and 31 Internal Base: 6 The selected HIF address bit is determined + # by adding the internal base to the value of this field. If set to 31, r + # ank address bit 0 is set to 0. # PSU_DDRC_ADDRMAP0_ADDRMAP_CS_BIT0 0x1f # Address Map Register 0 @@ -2383,16 +2782,22 @@ set psu_ddr_init_data { mask_write 0XFD070200 0x0000001F 0x0000001F # Register : ADDRMAP1 @ 0XFD070204

- # Selects the HIF address bit used as bank address bit 2. Valid Range: 0 to 29 and 31 Internal Base: 4 The selected HIF address - # bit is determined by adding the internal base to the value of this field. If set to 31, bank address bit 2 is set to 0. + # Selects the HIF address bit used as bank address bit 2. Valid Range: 0 t + # o 29 and 31 Internal Base: 4 The selected HIF address bit is determined + # by adding the internal base to the value of this field. If set to 31, ba + # nk address bit 2 is set to 0. # PSU_DDRC_ADDRMAP1_ADDRMAP_BANK_B2 0x1f - # Selects the HIF address bits used as bank address bit 1. Valid Range: 0 to 30 Internal Base: 3 The selected HIF address bit f - # r each of the bank address bits is determined by adding the internal base to the value of this field. + # Selects the HIF address bits used as bank address bit 1. Valid Range: 0 + # to 30 Internal Base: 3 The selected HIF address bit for each of the bank + # address bits is determined by adding the internal base to the value of + # this field. # PSU_DDRC_ADDRMAP1_ADDRMAP_BANK_B1 0xa - # Selects the HIF address bits used as bank address bit 0. Valid Range: 0 to 30 Internal Base: 2 The selected HIF address bit f - # r each of the bank address bits is determined by adding the internal base to the value of this field. + # Selects the HIF address bits used as bank address bit 0. Valid Range: 0 + # to 30 Internal Base: 2 The selected HIF address bit for each of the bank + # address bits is determined by adding the internal base to the value of + # this field. # PSU_DDRC_ADDRMAP1_ADDRMAP_BANK_B0 0xa # Address Map Register 1 @@ -2400,29 +2805,41 @@ set psu_ddr_init_data { mask_write 0XFD070204 0x001F1F1F 0x001F0A0A # Register : ADDRMAP2 @ 0XFD070208

- # - Full bus width mode: Selects the HIF address bit used as column address bit 5. - Half bus width mode: Selects the HIF addre - # s bit used as column address bit 6. - Quarter bus width mode: Selects the HIF address bit used as column address bit 7 . Vali - # Range: 0 to 7, and 15 Internal Base: 5 The selected HIF address bit is determined by adding the internal base to the value o - # this field. If set to 15, this column address bit is set to 0. + # - Full bus width mode: Selects the HIF address bit used as column addres + # s bit 5. - Half bus width mode: Selects the HIF address bit used as colu + # mn address bit 6. - Quarter bus width mode: Selects the HIF address bit + # used as column address bit 7 . Valid Range: 0 to 7, and 15 Internal Base + # : 5 The selected HIF address bit is determined by adding the internal ba + # se to the value of this field. If set to 15, this column address bit is + # set to 0. # PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B5 0x0 - # - Full bus width mode: Selects the HIF address bit used as column address bit 4. - Half bus width mode: Selects the HIF addre - # s bit used as column address bit 5. - Quarter bus width mode: Selects the HIF address bit used as column address bit 6. Valid - # Range: 0 to 7, and 15 Internal Base: 4 The selected HIF address bit is determined by adding the internal base to the value of - # this field. If set to 15, this column address bit is set to 0. + # - Full bus width mode: Selects the HIF address bit used as column addres + # s bit 4. - Half bus width mode: Selects the HIF address bit used as colu + # mn address bit 5. - Quarter bus width mode: Selects the HIF address bit + # used as column address bit 6. Valid Range: 0 to 7, and 15 Internal Base: + # 4 The selected HIF address bit is determined by adding the internal bas + # e to the value of this field. If set to 15, this column address bit is s + # et to 0. # PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B4 0x0 - # - Full bus width mode: Selects the HIF address bit used as column address bit 3. - Half bus width mode: Selects the HIF addre - # s bit used as column address bit 4. - Quarter bus width mode: Selects the HIF address bit used as column address bit 5. Valid - # Range: 0 to 7 Internal Base: 3 The selected HIF address bit is determined by adding the internal base to the value of this fi - # ld. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=16, it is required to program this to 0, hence register does not exist i - # this case. + # - Full bus width mode: Selects the HIF address bit used as column addres + # s bit 3. - Half bus width mode: Selects the HIF address bit used as colu + # mn address bit 4. - Quarter bus width mode: Selects the HIF address bit + # used as column address bit 5. Valid Range: 0 to 7 Internal Base: 3 The s + # elected HIF address bit is determined by adding the internal base to the + # value of this field. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=1 + # 6, it is required to program this to 0, hence register does not exist in + # this case. # PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B3 0x0 - # - Full bus width mode: Selects the HIF address bit used as column address bit 2. - Half bus width mode: Selects the HIF addre - # s bit used as column address bit 3. - Quarter bus width mode: Selects the HIF address bit used as column address bit 4. Valid - # Range: 0 to 7 Internal Base: 2 The selected HIF address bit is determined by adding the internal base to the value of this fi - # ld. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=8 or 16, it is required to program this to 0. + # - Full bus width mode: Selects the HIF address bit used as column addres + # s bit 2. - Half bus width mode: Selects the HIF address bit used as colu + # mn address bit 3. - Quarter bus width mode: Selects the HIF address bit + # used as column address bit 4. Valid Range: 0 to 7 Internal Base: 2 The s + # elected HIF address bit is determined by adding the internal base to the + # value of this field. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=8 + # or 16, it is required to program this to 0. # PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B2 0x0 # Address Map Register 2 @@ -2430,34 +2847,48 @@ set psu_ddr_init_data { mask_write 0XFD070208 0x0F0F0F0F 0x00000000 # Register : ADDRMAP3 @ 0XFD07020C

- # - Full bus width mode: Selects the HIF address bit used as column address bit 9. - Half bus width mode: Selects the HIF addre - # s bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). - Quarter bus width mode: Selects the HIF address bit used as - # column address bit 13 (11 in LPDDR2/LPDDR3 mode). Valid Range: 0 to 7, and 15 Internal Base: 9 The selected HIF address bit i - # determined by adding the internal base to the value of this field. If set to 15, this column address bit is set to 0. Note: - # er JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source addr - # ss bit can be mapped to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus an - # hence column bit 10 is used. + # - Full bus width mode: Selects the HIF address bit used as column addres + # s bit 9. - Half bus width mode: Selects the HIF address bit used as colu + # mn address bit 11 (10 in LPDDR2/LPDDR3 mode). - Quarter bus width mode: + # Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/ + # LPDDR3 mode). Valid Range: 0 to 7, and 15 Internal Base: 9 The selected + # HIF address bit is determined by adding the internal base to the value o + # f this field. If set to 15, this column address bit is set to 0. Note: P + # er JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved fo + # r indicating auto-precharge, and hence no source address bit can be mapp + # ed to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit + # for auto-precharge in the CA bus and hence column bit 10 is used. # PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B9 0x0 - # - Full bus width mode: Selects the HIF address bit used as column address bit 8. - Half bus width mode: Selects the HIF addre - # s bit used as column address bit 9. - Quarter bus width mode: Selects the HIF address bit used as column address bit 11 (10 i - # LPDDR2/LPDDR3 mode). Valid Range: 0 to 7, and 15 Internal Base: 8 The selected HIF address bit is determined by adding the i - # ternal base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specif - # cation, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to col - # mn address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and hence column bit 10 is use - # . + # - Full bus width mode: Selects the HIF address bit used as column addres + # s bit 8. - Half bus width mode: Selects the HIF address bit used as colu + # mn address bit 9. - Quarter bus width mode: Selects the HIF address bit + # used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). Valid Range: 0 + # to 7, and 15 Internal Base: 8 The selected HIF address bit is determine + # d by adding the internal base to the value of this field. If set to 15, + # this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specifi + # cation, column address bit 10 is reserved for indicating auto-precharge, + # and hence no source address bit can be mapped to column address bit 10. + # In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA + # bus and hence column bit 10 is used. # PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B8 0x0 - # - Full bus width mode: Selects the HIF address bit used as column address bit 7. - Half bus width mode: Selects the HIF addre - # s bit used as column address bit 8. - Quarter bus width mode: Selects the HIF address bit used as column address bit 9. Valid - # Range: 0 to 7, and 15 Internal Base: 7 The selected HIF address bit is determined by adding the internal base to the value of - # this field. If set to 15, this column address bit is set to 0. + # - Full bus width mode: Selects the HIF address bit used as column addres + # s bit 7. - Half bus width mode: Selects the HIF address bit used as colu + # mn address bit 8. - Quarter bus width mode: Selects the HIF address bit + # used as column address bit 9. Valid Range: 0 to 7, and 15 Internal Base: + # 7 The selected HIF address bit is determined by adding the internal bas + # e to the value of this field. If set to 15, this column address bit is s + # et to 0. # PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B7 0x0 - # - Full bus width mode: Selects the HIF address bit used as column address bit 6. - Half bus width mode: Selects the HIF addre - # s bit used as column address bit 7. - Quarter bus width mode: Selects the HIF address bit used as column address bit 8. Valid - # Range: 0 to 7, and 15 Internal Base: 6 The selected HIF address bit is determined by adding the internal base to the value of - # this field. If set to 15, this column address bit is set to 0. + # - Full bus width mode: Selects the HIF address bit used as column addres + # s bit 6. - Half bus width mode: Selects the HIF address bit used as colu + # mn address bit 7. - Quarter bus width mode: Selects the HIF address bit + # used as column address bit 8. Valid Range: 0 to 7, and 15 Internal Base: + # 6 The selected HIF address bit is determined by adding the internal bas + # e to the value of this field. If set to 15, this column address bit is s + # et to 0. # PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B6 0x0 # Address Map Register 3 @@ -2465,21 +2896,30 @@ set psu_ddr_init_data { mask_write 0XFD07020C 0x0F0F0F0F 0x00000000 # Register : ADDRMAP4 @ 0XFD070210

- # - Full bus width mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode). - Half bus width - # mode: Unused. To make it unused, this should be tied to 4'hF. - Quarter bus width mode: Unused. To make it unused, this must - # e tied to 4'hF. Valid Range: 0 to 7, and 15 Internal Base: 11 The selected HIF address bit is determined by adding the intern - # l base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specificati - # n, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column a - # dress bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and hence column bit 10 is used. + # - Full bus width mode: Selects the HIF address bit used as column addres + # s bit 13 (11 in LPDDR2/LPDDR3 mode). - Half bus width mode: Unused. To m + # ake it unused, this should be tied to 4'hF. - Quarter bus width mode: Un + # used. To make it unused, this must be tied to 4'hF. Valid Range: 0 to 7, + # and 15 Internal Base: 11 The selected HIF address bit is determined by + # adding the internal base to the value of this field. If set to 15, this + # column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specificatio + # n, column address bit 10 is reserved for indicating auto-precharge, and + # hence no source address bit can be mapped to column address bit 10. In L + # PDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus + # and hence column bit 10 is used. # PSU_DDRC_ADDRMAP4_ADDRMAP_COL_B11 0xf - # - Full bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). - Half bus width - # mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode). - Quarter bus width mode: UNUSED. - # To make it unused, this must be tied to 4'hF. Valid Range: 0 to 7, and 15 Internal Base: 10 The selected HIF address bit is d - # termined by adding the internal base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per - # JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source address - # bit can be mapped to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and h - # nce column bit 10 is used. + # - Full bus width mode: Selects the HIF address bit used as column addres + # s bit 11 (10 in LPDDR2/LPDDR3 mode). - Half bus width mode: Selects the + # HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode) + # . - Quarter bus width mode: UNUSED. To make it unused, this must be tied + # to 4'hF. Valid Range: 0 to 7, and 15 Internal Base: 10 The selected HIF + # address bit is determined by adding the internal base to the value of t + # his field. If set to 15, this column address bit is set to 0. Note: Per + # JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for i + # ndicating auto-precharge, and hence no source address bit can be mapped + # to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for + # auto-precharge in the CA bus and hence column bit 10 is used. # PSU_DDRC_ADDRMAP4_ADDRMAP_COL_B10 0xf # Address Map Register 4 @@ -2487,22 +2927,31 @@ set psu_ddr_init_data { mask_write 0XFD070210 0x00000F0F 0x00000F0F # Register : ADDRMAP5 @ 0XFD070214

- # Selects the HIF address bit used as row address bit 11. Valid Range: 0 to 11, and 15 Internal Base: 17 The selected HIF addre - # s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 11 is set to 0. + # Selects the HIF address bit used as row address bit 11. Valid Range: 0 t + # o 11, and 15 Internal Base: 17 The selected HIF address bit is determine + # d by adding the internal base to the value of this field. If set to 15, + # row address bit 11 is set to 0. # PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B11 0x8 - # Selects the HIF address bits used as row address bits 2 to 10. Valid Range: 0 to 11, and 15 Internal Base: 8 (for row address - # bit 2), 9 (for row address bit 3), 10 (for row address bit 4) etc increasing to 16 (for row address bit 10) The selected HIF - # ddress bit for each of the row address bits is determined by adding the internal base to the value of this field. When value - # 5 is used the values of row address bits 2 to 10 are defined by registers ADDRMAP9, ADDRMAP10, ADDRMAP11. + # Selects the HIF address bits used as row address bits 2 to 10. Valid Ran + # ge: 0 to 11, and 15 Internal Base: 8 (for row address bit 2), 9 (for row + # address bit 3), 10 (for row address bit 4) etc increasing to 16 (for ro + # w address bit 10) The selected HIF address bit for each of the row addre + # ss bits is determined by adding the internal base to the value of this f + # ield. When value 15 is used the values of row address bits 2 to 10 are d + # efined by registers ADDRMAP9, ADDRMAP10, ADDRMAP11. # PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10 0xf - # Selects the HIF address bits used as row address bit 1. Valid Range: 0 to 11 Internal Base: 7 The selected HIF address bit fo - # each of the row address bits is determined by adding the internal base to the value of this field. + # Selects the HIF address bits used as row address bit 1. Valid Range: 0 t + # o 11 Internal Base: 7 The selected HIF address bit for each of the row a + # ddress bits is determined by adding the internal base to the value of th + # is field. # PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B1 0x8 - # Selects the HIF address bits used as row address bit 0. Valid Range: 0 to 11 Internal Base: 6 The selected HIF address bit fo - # each of the row address bits is determined by adding the internal base to the value of this field. + # Selects the HIF address bits used as row address bit 0. Valid Range: 0 t + # o 11 Internal Base: 6 The selected HIF address bit for each of the row a + # ddress bits is determined by adding the internal base to the value of th + # is field. # PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B0 0x8 # Address Map Register 5 @@ -2510,25 +2959,35 @@ set psu_ddr_init_data { mask_write 0XFD070214 0x0F0F0F0F 0x080F0808 # Register : ADDRMAP6 @ 0XFD070218

- # Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use. - 1 - LPDDR3 SDRAM 6Gb/12Gb device in use. Every address - # having row[14:13]==2'b11 is considered as invalid - 0 - non-LPDDR3 6Gb/12Gb device in use. All addresses are valid Present on - # y in designs configured to support LPDDR3. + # Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use. - 1 + # - LPDDR3 SDRAM 6Gb/12Gb device in use. Every address having row[14:13]= + # =2'b11 is considered as invalid - 0 - non-LPDDR3 6Gb/12Gb device in use. + # All addresses are valid Present only in designs configured to support L + # PDDR3. # PSU_DDRC_ADDRMAP6_LPDDR3_6GB_12GB 0x0 - # Selects the HIF address bit used as row address bit 15. Valid Range: 0 to 11, and 15 Internal Base: 21 The selected HIF addre - # s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 15 is set to 0. + # Selects the HIF address bit used as row address bit 15. Valid Range: 0 t + # o 11, and 15 Internal Base: 21 The selected HIF address bit is determine + # d by adding the internal base to the value of this field. If set to 15, + # row address bit 15 is set to 0. # PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B15 0xf - # Selects the HIF address bit used as row address bit 14. Valid Range: 0 to 11, and 15 Internal Base: 20 The selected HIF addre - # s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 14 is set to 0. + # Selects the HIF address bit used as row address bit 14. Valid Range: 0 t + # o 11, and 15 Internal Base: 20 The selected HIF address bit is determine + # d by adding the internal base to the value of this field. If set to 15, + # row address bit 14 is set to 0. # PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B14 0x8 - # Selects the HIF address bit used as row address bit 13. Valid Range: 0 to 11, and 15 Internal Base: 19 The selected HIF addre - # s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 13 is set to 0. + # Selects the HIF address bit used as row address bit 13. Valid Range: 0 t + # o 11, and 15 Internal Base: 19 The selected HIF address bit is determine + # d by adding the internal base to the value of this field. If set to 15, + # row address bit 13 is set to 0. # PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B13 0x8 - # Selects the HIF address bit used as row address bit 12. Valid Range: 0 to 11, and 15 Internal Base: 18 The selected HIF addre - # s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 12 is set to 0. + # Selects the HIF address bit used as row address bit 12. Valid Range: 0 t + # o 11, and 15 Internal Base: 18 The selected HIF address bit is determine + # d by adding the internal base to the value of this field. If set to 15, + # row address bit 12 is set to 0. # PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B12 0x8 # Address Map Register 6 @@ -2536,12 +2995,16 @@ set psu_ddr_init_data { mask_write 0XFD070218 0x8F0F0F0F 0x0F080808 # Register : ADDRMAP7 @ 0XFD07021C

- # Selects the HIF address bit used as row address bit 17. Valid Range: 0 to 10, and 15 Internal Base: 23 The selected HIF addre - # s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 17 is set to 0. + # Selects the HIF address bit used as row address bit 17. Valid Range: 0 t + # o 10, and 15 Internal Base: 23 The selected HIF address bit is determine + # d by adding the internal base to the value of this field. If set to 15, + # row address bit 17 is set to 0. # PSU_DDRC_ADDRMAP7_ADDRMAP_ROW_B17 0xf - # Selects the HIF address bit used as row address bit 16. Valid Range: 0 to 11, and 15 Internal Base: 22 The selected HIF addre - # s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 16 is set to 0. + # Selects the HIF address bit used as row address bit 16. Valid Range: 0 t + # o 11, and 15 Internal Base: 22 The selected HIF address bit is determine + # d by adding the internal base to the value of this field. If set to 15, + # row address bit 16 is set to 0. # PSU_DDRC_ADDRMAP7_ADDRMAP_ROW_B16 0xf # Address Map Register 7 @@ -2549,13 +3012,17 @@ set psu_ddr_init_data { mask_write 0XFD07021C 0x00000F0F 0x00000F0F # Register : ADDRMAP8 @ 0XFD070220

- # Selects the HIF address bits used as bank group address bit 1. Valid Range: 0 to 30, and 31 Internal Base: 3 The selected HIF - # address bit for each of the bank group address bits is determined by adding the internal base to the value of this field. If - # et to 31, bank group address bit 1 is set to 0. + # Selects the HIF address bits used as bank group address bit 1. Valid Ran + # ge: 0 to 30, and 31 Internal Base: 3 The selected HIF address bit for ea + # ch of the bank group address bits is determined by adding the internal b + # ase to the value of this field. If set to 31, bank group address bit 1 i + # s set to 0. # PSU_DDRC_ADDRMAP8_ADDRMAP_BG_B1 0x8 - # Selects the HIF address bits used as bank group address bit 0. Valid Range: 0 to 30 Internal Base: 2 The selected HIF address - # bit for each of the bank group address bits is determined by adding the internal base to the value of this field. + # Selects the HIF address bits used as bank group address bit 0. Valid Ran + # ge: 0 to 30 Internal Base: 2 The selected HIF address bit for each of th + # e bank group address bits is determined by adding the internal base to t + # he value of this field. # PSU_DDRC_ADDRMAP8_ADDRMAP_BG_B0 0x8 # Address Map Register 8 @@ -2563,24 +3030,32 @@ set psu_ddr_init_data { mask_write 0XFD070220 0x00001F1F 0x00000808 # Register : ADDRMAP9 @ 0XFD070224

- # Selects the HIF address bits used as row address bit 5. Valid Range: 0 to 11 Internal Base: 11 The selected HIF address bit f - # r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u - # ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15. + # Selects the HIF address bits used as row address bit 5. Valid Range: 0 t + # o 11 Internal Base: 11 The selected HIF address bit for each of the row + # address bits is determined by adding the internal base to the value of t + # his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + # _10 is set to value 15. # PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B5 0x8 - # Selects the HIF address bits used as row address bit 4. Valid Range: 0 to 11 Internal Base: 10 The selected HIF address bit f - # r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u - # ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15. + # Selects the HIF address bits used as row address bit 4. Valid Range: 0 t + # o 11 Internal Base: 10 The selected HIF address bit for each of the row + # address bits is determined by adding the internal base to the value of t + # his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + # _10 is set to value 15. # PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B4 0x8 - # Selects the HIF address bits used as row address bit 3. Valid Range: 0 to 11 Internal Base: 9 The selected HIF address bit fo - # each of the row address bits is determined by adding the internal base to the value of this field. This register field is us - # d only when ADDRMAP5.addrmap_row_b2_10 is set to value 15. + # Selects the HIF address bits used as row address bit 3. Valid Range: 0 t + # o 11 Internal Base: 9 The selected HIF address bit for each of the row a + # ddress bits is determined by adding the internal base to the value of th + # is field. This register field is used only when ADDRMAP5.addrmap_row_b2_ + # 10 is set to value 15. # PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B3 0x8 - # Selects the HIF address bits used as row address bit 2. Valid Range: 0 to 11 Internal Base: 8 The selected HIF address bit fo - # each of the row address bits is determined by adding the internal base to the value of this field. This register field is us - # d only when ADDRMAP5.addrmap_row_b2_10 is set to value 15. + # Selects the HIF address bits used as row address bit 2. Valid Range: 0 t + # o 11 Internal Base: 8 The selected HIF address bit for each of the row a + # ddress bits is determined by adding the internal base to the value of th + # is field. This register field is used only when ADDRMAP5.addrmap_row_b2_ + # 10 is set to value 15. # PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B2 0x8 # Address Map Register 9 @@ -2588,24 +3063,32 @@ set psu_ddr_init_data { mask_write 0XFD070224 0x0F0F0F0F 0x08080808 # Register : ADDRMAP10 @ 0XFD070228

- # Selects the HIF address bits used as row address bit 9. Valid Range: 0 to 11 Internal Base: 15 The selected HIF address bit f - # r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u - # ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15. + # Selects the HIF address bits used as row address bit 9. Valid Range: 0 t + # o 11 Internal Base: 15 The selected HIF address bit for each of the row + # address bits is determined by adding the internal base to the value of t + # his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + # _10 is set to value 15. # PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B9 0x8 - # Selects the HIF address bits used as row address bit 8. Valid Range: 0 to 11 Internal Base: 14 The selected HIF address bit f - # r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u - # ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15. + # Selects the HIF address bits used as row address bit 8. Valid Range: 0 t + # o 11 Internal Base: 14 The selected HIF address bit for each of the row + # address bits is determined by adding the internal base to the value of t + # his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + # _10 is set to value 15. # PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B8 0x8 - # Selects the HIF address bits used as row address bit 7. Valid Range: 0 to 11 Internal Base: 13 The selected HIF address bit f - # r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u - # ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15. + # Selects the HIF address bits used as row address bit 7. Valid Range: 0 t + # o 11 Internal Base: 13 The selected HIF address bit for each of the row + # address bits is determined by adding the internal base to the value of t + # his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + # _10 is set to value 15. # PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B7 0x8 - # Selects the HIF address bits used as row address bit 6. Valid Range: 0 to 11 Internal Base: 12 The selected HIF address bit f - # r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u - # ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15. + # Selects the HIF address bits used as row address bit 6. Valid Range: 0 t + # o 11 Internal Base: 12 The selected HIF address bit for each of the row + # address bits is determined by adding the internal base to the value of t + # his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + # _10 is set to value 15. # PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B6 0x8 # Address Map Register 10 @@ -2613,9 +3096,11 @@ set psu_ddr_init_data { mask_write 0XFD070228 0x0F0F0F0F 0x08080808 # Register : ADDRMAP11 @ 0XFD07022C

- # Selects the HIF address bits used as row address bit 10. Valid Range: 0 to 11 Internal Base: 16 The selected HIF address bit - # or each of the row address bits is determined by adding the internal base to the value of this field. This register field is - # sed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15. + # Selects the HIF address bits used as row address bit 10. Valid Range: 0 + # to 11 Internal Base: 16 The selected HIF address bit for each of the row + # address bits is determined by adding the internal base to the value of + # this field. This register field is used only when ADDRMAP5.addrmap_row_b + # 2_10 is set to value 15. # PSU_DDRC_ADDRMAP11_ADDRMAP_ROW_B10 0x8 # Address Map Register 11 @@ -2623,30 +3108,42 @@ set psu_ddr_init_data { mask_write 0XFD07022C 0x0000000F 0x00000008 # Register : ODTCFG @ 0XFD070240

- # Cycles to hold ODT for a write command. The minimum supported value is 2. Recommended values: DDR2: - BL8: 0x5 (DDR2-400/533/ - # 67), 0x6 (DDR2-800), 0x7 (DDR2-1066) - BL4: 0x3 (DDR2-400/533/667), 0x4 (DDR2-800), 0x5 (DDR2-1066) DDR3: - BL8: 0x6 DDR4: - - # L8: 5 + WR_PREAMBLE + CRC_MODE WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) CRC_MODE = 0 (not CRC mode), 1 - # CRC mode) LPDDR3: - BL8: 7 + RU(tODTon(max)/tCK) + # Cycles to hold ODT for a write command. The minimum supported value is 2 + # . Recommended values: DDR2: - BL8: 0x5 (DDR2-400/533/667), 0x6 (DDR2-800 + # ), 0x7 (DDR2-1066) - BL4: 0x3 (DDR2-400/533/667), 0x4 (DDR2-800), 0x5 (D + # DR2-1066) DDR3: - BL8: 0x6 DDR4: - BL8: 5 + WR_PREAMBLE + CRC_MODE WR_PR + # EAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) CRC_MODE = 0 ( + # not CRC mode), 1 (CRC mode) LPDDR3: - BL8: 7 + RU(tODTon(max)/tCK) # PSU_DDRC_ODTCFG_WR_ODT_HOLD 0x6 - # The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting must - # remain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: - CWL + AL - 3 (DDR2-400/533/ - # 67), CWL + AL - 4 (DDR2-800), CWL + AL - 5 (DDR2-1066) If (CWL + AL - 3 < 0), uMCTL2 does not support ODT for write operation - # DDR3: - 0x0 DDR4: - DFITMG1.dfi_t_cmd_lat (to adjust for CAL mode) LPDDR3: - WL - 1 - RU(tODTon(max)/tCK)) + # The delay, in clock cycles, from issuing a write command to setting ODT + # values associated with that command. ODT setting must remain constant fo + # r the entire time that DQS is driven by the uMCTL2. Recommended values: + # DDR2: - CWL + AL - 3 (DDR2-400/533/667), CWL + AL - 4 (DDR2-800), CWL + + # AL - 5 (DDR2-1066) If (CWL + AL - 3 < 0), uMCTL2 does not support ODT fo + # r write operation. DDR3: - 0x0 DDR4: - DFITMG1.dfi_t_cmd_lat (to adjust + # for CAL mode) LPDDR3: - WL - 1 - RU(tODTon(max)/tCK)) # PSU_DDRC_ODTCFG_WR_ODT_DELAY 0x0 - # Cycles to hold ODT for a read command. The minimum supported value is 2. Recommended values: DDR2: - BL8: 0x6 (not DDR2-1066) - # 0x7 (DDR2-1066) - BL4: 0x4 (not DDR2-1066), 0x5 (DDR2-1066) DDR3: - BL8 - 0x6 DDR4: - BL8: 5 + RD_PREAMBLE RD_PREAMBLE = 1 ( - # tCK write preamble), 2 (2tCK write preamble) LPDDR3: - BL8: 5 + RU(tDQSCK(max)/tCK) - RD(tDQSCK(min)/tCK) + RU(tODTon(max)/tC - # ) + # Cycles to hold ODT for a read command. The minimum supported value is 2. + # Recommended values: DDR2: - BL8: 0x6 (not DDR2-1066), 0x7 (DDR2-1066) - + # BL4: 0x4 (not DDR2-1066), 0x5 (DDR2-1066) DDR3: - BL8 - 0x6 DDR4: - BL8 + # : 5 + RD_PREAMBLE RD_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write p + # reamble) LPDDR3: - BL8: 5 + RU(tDQSCK(max)/tCK) - RD(tDQSCK(min)/tCK) + + # RU(tODTon(max)/tCK) # PSU_DDRC_ODTCFG_RD_ODT_HOLD 0x6 - # The delay, in clock cycles, from issuing a read command to setting ODT values associated with that command. ODT setting must - # emain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: - CL + AL - 4 (not DDR2-1066), - # CL + AL - 5 (DDR2-1066) If (CL + AL - 4 < 0), uMCTL2 does not support ODT for read operation. DDR3: - CL - CWL DDR4: - CL - C - # L - RD_PREAMBLE + WR_PREAMBLE + DFITMG1.dfi_t_cmd_lat (to adjust for CAL mode) WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK - # write preamble) RD_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) If (CL - CWL - RD_PREAMBLE + WR_PREAMBLE) < 0, - # uMCTL2 does not support ODT for read operation. LPDDR3: - RL + RD(tDQSCK(min)/tCK) - 1 - RU(tODTon(max)/tCK) + # The delay, in clock cycles, from issuing a read command to setting ODT v + # alues associated with that command. ODT setting must remain constant for + # the entire time that DQS is driven by the uMCTL2. Recommended values: D + # DR2: - CL + AL - 4 (not DDR2-1066), CL + AL - 5 (DDR2-1066) If (CL + AL + # - 4 < 0), uMCTL2 does not support ODT for read operation. DDR3: - CL - C + # WL DDR4: - CL - CWL - RD_PREAMBLE + WR_PREAMBLE + DFITMG1.dfi_t_cmd_lat + # (to adjust for CAL mode) WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK + # write preamble) RD_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write pre + # amble) If (CL - CWL - RD_PREAMBLE + WR_PREAMBLE) < 0, uMCTL2 does not su + # pport ODT for read operation. LPDDR3: - RL + RD(tDQSCK(min)/tCK) - 1 - R + # U(tODTon(max)/tCK) # PSU_DDRC_ODTCFG_RD_ODT_DELAY 0x0 # ODT Configuration Register @@ -2654,24 +3151,34 @@ set psu_ddr_init_data { mask_write 0XFD070240 0x0F1F0F7C 0x06000600 # Register : ODTMAP @ 0XFD070244

- # Indicates which remote ODTs must be turned on during a read from rank 1. Each rank has a remote ODT (in the SDRAM) which can - # e turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB - # etc. For each rank, set its bit to 1 to enable its ODT. Present only in configurations that have 2 or more ranks + # Indicates which remote ODTs must be turned on during a read from rank 1. + # Each rank has a remote ODT (in the SDRAM) which can be turned on by set + # ting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 i + # s controlled by bit next to the LSB, etc. For each rank, set its bit to + # 1 to enable its ODT. Present only in configurations that have 2 or more + # ranks # PSU_DDRC_ODTMAP_RANK1_RD_ODT 0x0 - # Indicates which remote ODTs must be turned on during a write to rank 1. Each rank has a remote ODT (in the SDRAM) which can b - # turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB, - # etc. For each rank, set its bit to 1 to enable its ODT. Present only in configurations that have 2 or more ranks + # Indicates which remote ODTs must be turned on during a write to rank 1. + # Each rank has a remote ODT (in the SDRAM) which can be turned on by sett + # ing the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is + # controlled by bit next to the LSB, etc. For each rank, set its bit to 1 + # to enable its ODT. Present only in configurations that have 2 or more r + # anks # PSU_DDRC_ODTMAP_RANK1_WR_ODT 0x0 - # Indicates which remote ODTs must be turned on during a read from rank 0. Each rank has a remote ODT (in the SDRAM) which can - # e turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB - # etc. For each rank, set its bit to 1 to enable its ODT. + # Indicates which remote ODTs must be turned on during a read from rank 0. + # Each rank has a remote ODT (in the SDRAM) which can be turned on by set + # ting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 i + # s controlled by bit next to the LSB, etc. For each rank, set its bit to + # 1 to enable its ODT. # PSU_DDRC_ODTMAP_RANK0_RD_ODT 0x0 - # Indicates which remote ODTs must be turned on during a write to rank 0. Each rank has a remote ODT (in the SDRAM) which can b - # turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB, - # etc. For each rank, set its bit to 1 to enable its ODT. + # Indicates which remote ODTs must be turned on during a write to rank 0. + # Each rank has a remote ODT (in the SDRAM) which can be turned on by sett + # ing the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is + # controlled by bit next to the LSB, etc. For each rank, set its bit to 1 + # to enable its ODT. # PSU_DDRC_ODTMAP_RANK0_WR_ODT 0x1 # ODT/Rank Map Register @@ -2679,41 +3186,57 @@ set psu_ddr_init_data { mask_write 0XFD070244 0x00003333 0x00000001 # Register : SCHED @ 0XFD070250

- # When the preferred transaction store is empty for these many clock cycles, switch to the alternate transaction store if it is - # non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write t - # ansaction store is the alternative store. When prefer write over read is set this is reversed. 0x0 is a legal value for this - # egister. When set to 0x0, the transaction store switching will happen immediately when the switching conditions become true. - # OR PERFORMANCE ONLY + # When the preferred transaction store is empty for these many clock cycle + # s, switch to the alternate transaction store if it is non-empty. The rea + # d transaction store (both high and low priority) is the default preferre + # d transaction store and the write transaction store is the alternative s + # tore. When prefer write over read is set this is reversed. 0x0 is a lega + # l value for this register. When set to 0x0, the transaction store switch + # ing will happen immediately when the switching conditions become true. F + # OR PERFORMANCE ONLY # PSU_DDRC_SCHED_RDWR_IDLE_GAP 0x1 # UNUSED # PSU_DDRC_SCHED_GO2CRITICAL_HYSTERESIS 0x0 - # Number of entries in the low priority transaction store is this value + 1. (MEMC_NO_OF_ENTRY - (SCHED.lpr_num_entries + 1)) i - # the number of entries available for the high priority transaction store. Setting this to maximum value allocates all entries - # to low priority transaction store. Setting this to 0 allocates 1 entry to low priority transaction store and the rest to high - # priority transaction store. Note: In ECC configurations, the numbers of write and low priority read credits issued is one les - # than in the non-ECC case. One entry each is reserved in the write and low-priority read CAMs for storing the RMW requests ar - # sing out of single bit error correction RMW operation. + # Number of entries in the low priority transaction store is this value + + # 1. (MEMC_NO_OF_ENTRY - (SCHED.lpr_num_entries + 1)) is the number of ent + # ries available for the high priority transaction store. Setting this to + # maximum value allocates all entries to low priority transaction store. S + # etting this to 0 allocates 1 entry to low priority transaction store and + # the rest to high priority transaction store. Note: In ECC configuration + # s, the numbers of write and low priority read credits issued is one less + # than in the non-ECC case. One entry each is reserved in the write and l + # ow-priority read CAMs for storing the RMW requests arising out of single + # bit error correction RMW operation. # PSU_DDRC_SCHED_LPR_NUM_ENTRIES 0x20 - # If true, bank is kept open only while there are page hit transactions available in the CAM to that bank. The last read or wri - # e command in the CAM with a bank and page hit will be executed with auto-precharge if SCHED1.pageclose_timer=0. Even if this - # egister set to 1 and SCHED1.pageclose_timer is set to 0, explicit precharge (and not auto-precharge) may be issued in some ca - # es where there is a mode switch between Write and Read or between LPR and HPR. The Read and Write commands that are executed - # s part of the ECC scrub requests are also executed without auto-precharge. If false, the bank remains open until there is a n - # ed to close it (to open a different page, or for page timeout or refresh timeout) - also known as open page policy. The open - # age policy can be overridden by setting the per-command-autopre bit on the HIF interface (hif_cmd_autopre). The pageclose fea - # ure provids a midway between Open and Close page policies. FOR PERFORMANCE ONLY. + # If true, bank is kept open only while there are page hit transactions av + # ailable in the CAM to that bank. The last read or write command in the C + # AM with a bank and page hit will be executed with auto-precharge if SCHE + # D1.pageclose_timer=0. Even if this register set to 1 and SCHED1.pageclos + # e_timer is set to 0, explicit precharge (and not auto-precharge) may be + # issued in some cases where there is a mode switch between Write and Read + # or between LPR and HPR. The Read and Write commands that are executed a + # s part of the ECC scrub requests are also executed without auto-precharg + # e. If false, the bank remains open until there is a need to close it (to + # open a different page, or for page timeout or refresh timeout) - also k + # nown as open page policy. The open page policy can be overridden by sett + # ing the per-command-autopre bit on the HIF interface (hif_cmd_autopre). + # The pageclose feature provids a midway between Open and Close page polic + # ies. FOR PERFORMANCE ONLY. # PSU_DDRC_SCHED_PAGECLOSE 0x0 # If set then the bank selector prefers writes over reads. FOR DEBUG ONLY. # PSU_DDRC_SCHED_PREFER_WRITE 0x0 - # Active low signal. When asserted ('0'), all incoming transactions are forced to low priority. This implies that all High Prio - # ity Read (HPR) and Variable Priority Read commands (VPR) will be treated as Low Priority Read (LPR) commands. On the write si - # e, all Variable Priority Write (VPW) commands will be treated as Normal Priority Write (NPW) commands. Forcing the incoming t - # ansactions to low priority implicitly turns off Bypass path for read commands. FOR PERFORMANCE ONLY. + # Active low signal. When asserted ('0'), all incoming transactions are fo + # rced to low priority. This implies that all High Priority Read (HPR) and + # Variable Priority Read commands (VPR) will be treated as Low Priority R + # ead (LPR) commands. On the write side, all Variable Priority Write (VPW) + # commands will be treated as Normal Priority Write (NPW) commands. Forci + # ng the incoming transactions to low priority implicitly turns off Bypass + # path for read commands. FOR PERFORMANCE ONLY. # PSU_DDRC_SCHED_FORCE_LOW_PRI_N 0x1 # Scheduler Control Register @@ -2721,13 +3244,16 @@ set psu_ddr_init_data { mask_write 0XFD070250 0x7FFF3F07 0x01002001 # Register : PERFLPR1 @ 0XFD070264

- # Number of transactions that are serviced once the LPR queue goes critical is the smaller of: - (a) This number - (b) Number o - # transactions available. Unit: Transaction. FOR PERFORMANCE ONLY. + # Number of transactions that are serviced once the LPR queue goes critica + # l is the smaller of: - (a) This number - (b) Number of transactions avai + # lable. Unit: Transaction. FOR PERFORMANCE ONLY. # PSU_DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH 0x8 - # Number of clocks that the LPR queue can be starved before it goes critical. The minimum valid functional value for this regis - # er is 0x1. Programming it to 0x0 will disable the starvation functionality; during normal operation, this function should not - # be disabled as it will cause excessive latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY. + # Number of clocks that the LPR queue can be starved before it goes critic + # al. The minimum valid functional value for this register is 0x1. Program + # ming it to 0x0 will disable the starvation functionality; during normal + # operation, this function should not be disabled as it will cause excessi + # ve latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY. # PSU_DDRC_PERFLPR1_LPR_MAX_STARVE 0x40 # Low Priority Read CAM Register 1 @@ -2735,24 +3261,126 @@ set psu_ddr_init_data { mask_write 0XFD070264 0xFF00FFFF 0x08000040 # Register : PERFWR1 @ 0XFD07026C

- # Number of transactions that are serviced once the WR queue goes critical is the smaller of: - (a) This number - (b) Number of - # transactions available. Unit: Transaction. FOR PERFORMANCE ONLY. + # Number of transactions that are serviced once the WR queue goes critical + # is the smaller of: - (a) This number - (b) Number of transactions avail + # able. Unit: Transaction. FOR PERFORMANCE ONLY. # PSU_DDRC_PERFWR1_W_XACT_RUN_LENGTH 0x8 - # Number of clocks that the WR queue can be starved before it goes critical. The minimum valid functional value for this regist - # r is 0x1. Programming it to 0x0 will disable the starvation functionality; during normal operation, this function should not - # e disabled as it will cause excessive latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY. + # Number of clocks that the WR queue can be starved before it goes critica + # l. The minimum valid functional value for this register is 0x1. Programm + # ing it to 0x0 will disable the starvation functionality; during normal o + # peration, this function should not be disabled as it will cause excessiv + # e latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY. # PSU_DDRC_PERFWR1_W_MAX_STARVE 0x40 # Write CAM Register 1 #(OFFSET, MASK, VALUE) (0XFD07026C, 0xFF00FFFFU ,0x08000040U) */ mask_write 0XFD07026C 0xFF00FFFF 0x08000040 + # Register : DQMAP0 @ 0XFD070280

+ + # DQ nibble map for DQ bits [12-15] Present only in designs configured to + # support DDR4. + # PSU_DDRC_DQMAP0_DQ_NIBBLE_MAP_12_15 0x0 + + # DQ nibble map for DQ bits [8-11] Present only in designs configured to s + # upport DDR4. + # PSU_DDRC_DQMAP0_DQ_NIBBLE_MAP_8_11 0x0 + + # DQ nibble map for DQ bits [4-7] Present only in designs configured to su + # pport DDR4. + # PSU_DDRC_DQMAP0_DQ_NIBBLE_MAP_4_7 0x0 + + # DQ nibble map for DQ bits [0-3] Present only in designs configured to su + # pport DDR4. + # PSU_DDRC_DQMAP0_DQ_NIBBLE_MAP_0_3 0x0 + + # DQ Map Register 0 + #(OFFSET, MASK, VALUE) (0XFD070280, 0xFFFFFFFFU ,0x00000000U) */ + mask_write 0XFD070280 0xFFFFFFFF 0x00000000 + # Register : DQMAP1 @ 0XFD070284

+ + # DQ nibble map for DQ bits [28-31] Present only in designs configured to + # support DDR4. + # PSU_DDRC_DQMAP1_DQ_NIBBLE_MAP_28_31 0x0 + + # DQ nibble map for DQ bits [24-27] Present only in designs configured to + # support DDR4. + # PSU_DDRC_DQMAP1_DQ_NIBBLE_MAP_24_27 0x0 + + # DQ nibble map for DQ bits [20-23] Present only in designs configured to + # support DDR4. + # PSU_DDRC_DQMAP1_DQ_NIBBLE_MAP_20_23 0x0 + + # DQ nibble map for DQ bits [16-19] Present only in designs configured to + # support DDR4. + # PSU_DDRC_DQMAP1_DQ_NIBBLE_MAP_16_19 0x0 + + # DQ Map Register 1 + #(OFFSET, MASK, VALUE) (0XFD070284, 0xFFFFFFFFU ,0x00000000U) */ + mask_write 0XFD070284 0xFFFFFFFF 0x00000000 + # Register : DQMAP2 @ 0XFD070288

+ + # DQ nibble map for DQ bits [44-47] Present only in designs configured to + # support DDR4. + # PSU_DDRC_DQMAP2_DQ_NIBBLE_MAP_44_47 0x0 + + # DQ nibble map for DQ bits [40-43] Present only in designs configured to + # support DDR4. + # PSU_DDRC_DQMAP2_DQ_NIBBLE_MAP_40_43 0x0 + + # DQ nibble map for DQ bits [36-39] Present only in designs configured to + # support DDR4. + # PSU_DDRC_DQMAP2_DQ_NIBBLE_MAP_36_39 0x0 + + # DQ nibble map for DQ bits [32-35] Present only in designs configured to + # support DDR4. + # PSU_DDRC_DQMAP2_DQ_NIBBLE_MAP_32_35 0x0 + + # DQ Map Register 2 + #(OFFSET, MASK, VALUE) (0XFD070288, 0xFFFFFFFFU ,0x00000000U) */ + mask_write 0XFD070288 0xFFFFFFFF 0x00000000 + # Register : DQMAP3 @ 0XFD07028C

+ + # DQ nibble map for DQ bits [60-63] Present only in designs configured to + # support DDR4. + # PSU_DDRC_DQMAP3_DQ_NIBBLE_MAP_60_63 0x0 + + # DQ nibble map for DQ bits [56-59] Present only in designs configured to + # support DDR4. + # PSU_DDRC_DQMAP3_DQ_NIBBLE_MAP_56_59 0x0 + + # DQ nibble map for DQ bits [52-55] Present only in designs configured to + # support DDR4. + # PSU_DDRC_DQMAP3_DQ_NIBBLE_MAP_52_55 0x0 + + # DQ nibble map for DQ bits [48-51] Present only in designs configured to + # support DDR4. + # PSU_DDRC_DQMAP3_DQ_NIBBLE_MAP_48_51 0x0 + + # DQ Map Register 3 + #(OFFSET, MASK, VALUE) (0XFD07028C, 0xFFFFFFFFU ,0x00000000U) */ + mask_write 0XFD07028C 0xFFFFFFFF 0x00000000 + # Register : DQMAP4 @ 0XFD070290

+ + # DQ nibble map for DIMM ECC check bits [4-7] Present only in designs conf + # igured to support DDR4. + # PSU_DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_4_7 0x0 + + # DQ nibble map for DIMM ECC check bits [0-3] Present only in designs conf + # igured to support DDR4. + # PSU_DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_0_3 0x0 + + # DQ Map Register 4 + #(OFFSET, MASK, VALUE) (0XFD070290, 0x0000FFFFU ,0x00000000U) */ + mask_write 0XFD070290 0x0000FFFF 0x00000000 # Register : DQMAP5 @ 0XFD070294

- # All even ranks have the same DQ mapping controled by DQMAP0-4 register as rank 0. This register provides DQ swap function for - # all odd ranks to support CRC feature. rank based DQ swapping is: swap bit 0 with 1, swap bit 2 with 3, swap bit 4 with 5 and - # wap bit 6 with 7. 1: Disable rank based DQ swapping 0: Enable rank based DQ swapping Present only in designs configured to su - # port DDR4. + # All even ranks have the same DQ mapping controled by DQMAP0-4 register a + # s rank 0. This register provides DQ swap function for all odd ranks to s + # upport CRC feature. rank based DQ swapping is: swap bit 0 with 1, swap b + # it 2 with 3, swap bit 4 with 5 and swap bit 6 with 7. 1: Disable rank ba + # sed DQ swapping 0: Enable rank based DQ swapping Present only in designs + # configured to support DDR4. # PSU_DDRC_DQMAP5_DIS_DQ_RANK_SWAP 0x1 # DQ Map Register 5 @@ -2760,9 +3388,12 @@ set psu_ddr_init_data { mask_write 0XFD070294 0x00000001 0x00000001 # Register : DBG0 @ 0XFD070300

- # When this is set to '0', auto-precharge is disabled for the flushed command in a collision case. Collision cases are write fo - # lowed by read to same address, read followed by write to same address, or write followed by write to same address with DBG0.d - # s_wc bit = 1 (where same address comparisons exclude the two address bits representing critical word). FOR DEBUG ONLY. + # When this is set to '0', auto-precharge is disabled for the flushed comm + # and in a collision case. Collision cases are write followed by read to s + # ame address, read followed by write to same address, or write followed b + # y write to same address with DBG0.dis_wc bit = 1 (where same address com + # parisons exclude the two address bits representing critical word). FOR D + # EBUG ONLY. # PSU_DDRC_DBG0_DIS_COLLISION_PAGE_OPT 0x0 # When 1, disable write combine. FOR DEBUG ONLY @@ -2773,34 +3404,47 @@ set psu_ddr_init_data { mask_write 0XFD070300 0x00000011 0x00000000 # Register : DBGCMD @ 0XFD07030C

- # Setting this register bit to 1 allows refresh and ZQCS commands to be triggered from hardware via the IOs ext_*. If set to 1, - # the fields DBGCMD.zq_calib_short and DBGCMD.rank*_refresh have no function, and are ignored by the uMCTL2 logic. Setting this - # register bit to 0 allows refresh and ZQCS to be triggered from software, via the fields DBGCMD.zq_calib_short and DBGCMD.rank - # _refresh. If set to 0, the hardware pins ext_* have no function, and are ignored by the uMCTL2 logic. This register is static - # and may only be changed when the DDRC reset signal, core_ddrc_rstn, is asserted (0). + # Setting this register bit to 1 allows refresh and ZQCS commands to be tr + # iggered from hardware via the IOs ext_*. If set to 1, the fields DBGCMD. + # zq_calib_short and DBGCMD.rank*_refresh have no function, and are ignore + # d by the uMCTL2 logic. Setting this register bit to 0 allows refresh and + # ZQCS to be triggered from software, via the fields DBGCMD.zq_calib_shor + # t and DBGCMD.rank*_refresh. If set to 0, the hardware pins ext_* have no + # function, and are ignored by the uMCTL2 logic. This register is static, + # and may only be changed when the DDRC reset signal, core_ddrc_rstn, is + # asserted (0). # PSU_DDRC_DBGCMD_HW_REF_ZQ_EN 0x0 - # Setting this register bit to 1 indicates to the uMCTL2 to issue a dfi_ctrlupd_req to the PHY. When this request is stored in - # he uMCTL2, the bit is automatically cleared. This operation must only be performed when DFIUPD0.dis_auto_ctrlupd=1. + # Setting this register bit to 1 indicates to the uMCTL2 to issue a dfi_ct + # rlupd_req to the PHY. When this request is stored in the uMCTL2, the bit + # is automatically cleared. This operation must only be performed when DF + # IUPD0.dis_auto_ctrlupd=1. # PSU_DDRC_DBGCMD_CTRLUPD 0x0 - # Setting this register bit to 1 indicates to the uMCTL2 to issue a ZQCS (ZQ calibration short)/MPC(ZQ calibration) command to - # he SDRAM. When this request is stored in the uMCTL2, the bit is automatically cleared. This operation can be performed only w - # en ZQCTL0.dis_auto_zq=1. It is recommended NOT to set this register bit if in Init operating mode. This register bit is ignor - # d when in Self-Refresh(except LPDDR4) and SR-Powerdown(LPDDR4) and Deep power-down operating modes and Maximum Power Saving M - # de. + # Setting this register bit to 1 indicates to the uMCTL2 to issue a ZQCS ( + # ZQ calibration short)/MPC(ZQ calibration) command to the SDRAM. When thi + # s request is stored in the uMCTL2, the bit is automatically cleared. Thi + # s operation can be performed only when ZQCTL0.dis_auto_zq=1. It is recom + # mended NOT to set this register bit if in Init operating mode. This regi + # ster bit is ignored when in Self-Refresh(except LPDDR4) and SR-Powerdown + # (LPDDR4) and Deep power-down operating modes and Maximum Power Saving Mo + # de. # PSU_DDRC_DBGCMD_ZQ_CALIB_SHORT 0x0 - # Setting this register bit to 1 indicates to the uMCTL2 to issue a refresh to rank 1. Writing to this bit causes DBGSTAT.rank1 - # refresh_busy to be set. When DBGSTAT.rank1_refresh_busy is cleared, the command has been stored in uMCTL2. This operation can - # be performed only when RFSHCTL3.dis_auto_refresh=1. It is recommended NOT to set this register bit if in Init or Deep power-d - # wn operating modes or Maximum Power Saving Mode. + # Setting this register bit to 1 indicates to the uMCTL2 to issue a refres + # h to rank 1. Writing to this bit causes DBGSTAT.rank1_refresh_busy to be + # set. When DBGSTAT.rank1_refresh_busy is cleared, the command has been s + # tored in uMCTL2. This operation can be performed only when RFSHCTL3.dis_ + # auto_refresh=1. It is recommended NOT to set this register bit if in Ini + # t or Deep power-down operating modes or Maximum Power Saving Mode. # PSU_DDRC_DBGCMD_RANK1_REFRESH 0x0 - # Setting this register bit to 1 indicates to the uMCTL2 to issue a refresh to rank 0. Writing to this bit causes DBGSTAT.rank0 - # refresh_busy to be set. When DBGSTAT.rank0_refresh_busy is cleared, the command has been stored in uMCTL2. This operation can - # be performed only when RFSHCTL3.dis_auto_refresh=1. It is recommended NOT to set this register bit if in Init or Deep power-d - # wn operating modes or Maximum Power Saving Mode. + # Setting this register bit to 1 indicates to the uMCTL2 to issue a refres + # h to rank 0. Writing to this bit causes DBGSTAT.rank0_refresh_busy to be + # set. When DBGSTAT.rank0_refresh_busy is cleared, the command has been s + # tored in uMCTL2. This operation can be performed only when RFSHCTL3.dis_ + # auto_refresh=1. It is recommended NOT to set this register bit if in Ini + # t or Deep power-down operating modes or Maximum Power Saving Mode. # PSU_DDRC_DBGCMD_RANK0_REFRESH 0x0 # Command Debug Register @@ -2808,8 +3452,9 @@ set psu_ddr_init_data { mask_write 0XFD07030C 0x80000033 0x00000000 # Register : SWCTL @ 0XFD070320

- # Enable quasi-dynamic register programming outside reset. Program register to 0 to enable quasi-dynamic programming. Set back - # egister to 1 once programming is done. + # Enable quasi-dynamic register programming outside reset. Program registe + # r to 0 to enable quasi-dynamic programming. Set back register to 1 once + # programming is done. # PSU_DDRC_SWCTL_SW_DONE 0x0 # Software register programming control enable @@ -2817,25 +3462,34 @@ set psu_ddr_init_data { mask_write 0XFD070320 0x00000001 0x00000000 # Register : PCCFG @ 0XFD070400

- # Burst length expansion mode. By default (i.e. bl_exp_mode==0) XPI expands every AXI burst into multiple HIF commands, using t - # e memory burst length as a unit. If set to 1, then XPI will use half of the memory burst length as a unit. This applies to bo - # h reads and writes. When MSTR.data_bus_width==00, setting bl_exp_mode to 1 has no effect. This can be used in cases where Par - # ial Writes is enabled (UMCTL2_PARTIAL_WR=1) and DBG0.dis_wc=1, in order to avoid or minimize t_ccd_l penalty in DDR4 and t_cc - # _mw penalty in LPDDR4. Note that if DBICTL.reg_ddrc_dm_en=0, functionality is not supported in the following cases: - UMCTL2_ - # ARTIAL_WR=0 - UMCTL2_PARTIAL_WR=1, MSTR.reg_ddrc_data_bus_width=01, MEMC_BURST_LENGTH=8 and MSTR.reg_ddrc_burst_rdwr=1000 (LP - # DR4 only) - UMCTL2_PARTIAL_WR=1, MSTR.reg_ddrc_data_bus_width=01, MEMC_BURST_LENGTH=4 and MSTR.reg_ddrc_burst_rdwr=0100 (DDR4 - # only), with either MSTR.reg_ddrc_burstchop=0 or CRCPARCTL1.reg_ddrc_crc_enable=1 Functionality is also not supported if Share - # -AC is enabled + # Burst length expansion mode. By default (i.e. bl_exp_mode==0) XPI expand + # s every AXI burst into multiple HIF commands, using the memory burst len + # gth as a unit. If set to 1, then XPI will use half of the memory burst l + # ength as a unit. This applies to both reads and writes. When MSTR.data_b + # us_width==00, setting bl_exp_mode to 1 has no effect. This can be used i + # n cases where Partial Writes is enabled (UMCTL2_PARTIAL_WR=1) and DBG0.d + # is_wc=1, in order to avoid or minimize t_ccd_l penalty in DDR4 and t_ccd + # _mw penalty in LPDDR4. Note that if DBICTL.reg_ddrc_dm_en=0, functionali + # ty is not supported in the following cases: - UMCTL2_PARTIAL_WR=0 - UMCT + # L2_PARTIAL_WR=1, MSTR.reg_ddrc_data_bus_width=01, MEMC_BURST_LENGTH=8 an + # d MSTR.reg_ddrc_burst_rdwr=1000 (LPDDR4 only) - UMCTL2_PARTIAL_WR=1, MST + # R.reg_ddrc_data_bus_width=01, MEMC_BURST_LENGTH=4 and MSTR.reg_ddrc_burs + # t_rdwr=0100 (DDR4 only), with either MSTR.reg_ddrc_burstchop=0 or CRCPAR + # CTL1.reg_ddrc_crc_enable=1 Functionality is also not supported if Shared + # -AC is enabled # PSU_DDRC_PCCFG_BL_EXP_MODE 0x0 - # Page match four limit. If set to 1, limits the number of consecutive same page DDRC transactions that can be granted by the P - # rt Arbiter to four when Page Match feature is enabled. If set to 0, there is no limit imposed on number of consecutive same p - # ge DDRC transactions. + # Page match four limit. If set to 1, limits the number of consecutive sam + # e page DDRC transactions that can be granted by the Port Arbiter to four + # when Page Match feature is enabled. If set to 0, there is no limit impo + # sed on number of consecutive same page DDRC transactions. # PSU_DDRC_PCCFG_PAGEMATCH_LIMIT 0x0 - # If set to 1 (enabled), sets co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals going to DDRC based - # n urgent input (awurgent, arurgent) coming from AXI master. If set to 0 (disabled), co_gs_go2critical_wr and co_gs_go2critica - # _lpr/co_gs_go2critical_hpr signals at DDRC are driven to 1b'0. + # If set to 1 (enabled), sets co_gs_go2critical_wr and co_gs_go2critical_l + # pr/co_gs_go2critical_hpr signals going to DDRC based on urgent input (aw + # urgent, arurgent) coming from AXI master. If set to 0 (disabled), co_gs_ + # go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals a + # t DDRC are driven to 1b'0. # PSU_DDRC_PCCFG_GO2CRITICAL_EN 0x1 # Port Common Configuration Register @@ -2843,30 +3497,41 @@ set psu_ddr_init_data { mask_write 0XFD070400 0x00000111 0x00000001 # Register : PCFGR_0 @ 0XFD070404

- # If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - # d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - # imit register. + # If set to 1, enables the Page Match feature. If enabled, once a requesti + # ng port is granted, the port is continued to be granted if the following + # immediate commands are to the same memory page (same bank and same row) + # . See also related PCCFG.pagematch_limit register. # PSU_DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN 0x0 - # If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por - # becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG. - # o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add - # ess handshaking (it is not associated with any particular command). + # If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + # bled and arurgent is asserted by the master, that port becomes the highe + # st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + # RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + # urgent signal can be asserted anytime and as long as required which is i + # ndependent of address handshaking (it is not associated with any particu + # lar command). # PSU_DDRC_PCFGR_0_RD_PORT_URGENT_EN 0x1 # If set to 1, enables aging function for the read channel of the port. # PSU_DDRC_PCFGR_0_RD_PORT_AGING_EN 0x0 - # Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g - # ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - # he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority - # will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre - # ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the - # aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st - # ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w - # ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D - # RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: - # he two LSBs of this register field are tied internally to 2'b00. + # Determines the initial load value of read aging counters. These counters + # will be parallel loaded after reset, or after each grant to the corresp + # onding port. The aging counters down-count every clock cycle where the p + # ort is requesting but not granted. The higher significant 5-bits of the + # read aging counter sets the priority of the read channel of a given port + # . Port's priority will increase as the higher significant 5-bits of the + # counter starts to decrease. When the aging counter becomes 0, the corres + # ponding port channel will have the highest priority level (timeout condi + # tion - Priority0). For multi-port configurations, the aging counters can + # not be used to set port priorities when external dynamic priority inputs + # (arqos) are enabled (timeout is still applicable). For single port conf + # igurations, the aging counters are only used when they timeout (become 0 + # ) to force read-write direction switching. In this case, external dynami + # c priority input, arqos (for reads only) can still be used to set the DD + # RC read priority (2 priority levels: low priority read - LPR, high prior + # ity read - HPR) on a command by command basis. Note: The two LSBs of thi + # s register field are tied internally to 2'b00. # PSU_DDRC_PCFGR_0_RD_PORT_PRIORITY 0xf # Port n Configuration Read Register @@ -2874,33 +3539,42 @@ set psu_ddr_init_data { mask_write 0XFD070404 0x000073FF 0x0000200F # Register : PCFGW_0 @ 0XFD070408

- # If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - # d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - # imit register. - # PSU_DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN 0x1 + # If set to 1, enables the Page Match feature. If enabled, once a requesti + # ng port is granted, the port is continued to be granted if the following + # immediate commands are to the same memory page (same bank and same row) + # . See also related PCCFG.pagematch_limit register. + # PSU_DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN 0x0 - # If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por - # becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register - # Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is - # not associated with any particular command). + # If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + # bled and awurgent is asserted by the master, that port becomes the highe + # st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + # ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + # serted anytime and as long as required which is independent of address h + # andshaking (it is not associated with any particular command). # PSU_DDRC_PCFGW_0_WR_PORT_URGENT_EN 0x1 # If set to 1, enables aging function for the write channel of the port. # PSU_DDRC_PCFGW_0_WR_PORT_AGING_EN 0x0 - # Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each - # rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - # The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port - # s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0 - # the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno - # be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For - # ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch - # ng. Note: The two LSBs of this register field are tied internally to 2'b00. + # Determines the initial load value of write aging counters. These counter + # s will be parallel loaded after reset, or after each grant to the corres + # ponding port. The aging counters down-count every clock cycle where the + # port is requesting but not granted. The higher significant 5-bits of the + # write aging counter sets the initial priority of the write channel of a + # given port. Port's priority will increase as the higher significant 5-b + # its of the counter starts to decrease. When the aging counter becomes 0, + # the corresponding port channel will have the highest priority level. Fo + # r multi-port configurations, the aging counters cannot be used to set po + # rt priorities when external dynamic priority inputs (awqos) are enabled + # (timeout is still applicable). For single port configurations, the aging + # counters are only used when they timeout (become 0) to force read-write + # direction switching. Note: The two LSBs of this register field are tied + # internally to 2'b00. # PSU_DDRC_PCFGW_0_WR_PORT_PRIORITY 0xf # Port n Configuration Write Register - #(OFFSET, MASK, VALUE) (0XFD070408, 0x000073FFU ,0x0000600FU) */ - mask_write 0XFD070408 0x000073FF 0x0000600F + #(OFFSET, MASK, VALUE) (0XFD070408, 0x000073FFU ,0x0000200FU) */ + mask_write 0XFD070408 0x000073FF 0x0000200F # Register : PCTRL_0 @ 0XFD070490

# Enables port n. @@ -2911,20 +3585,28 @@ set psu_ddr_init_data { mask_write 0XFD070490 0x00000001 0x00000001 # Register : PCFGQOS0_0 @ 0XFD070494

- # This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf - # gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is - # disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. + # This bitfield indicates the traffic class of region 1. Valid values are: + # 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + # maps to the blue address queue. In this case, valid values are 0: LPR a + # nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + # ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + # traffic. # PSU_DDRC_PCFGQOS0_0_RQOS_MAP_REGION1 0x2 - # This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi - # urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i - # disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. + # This bitfield indicates the traffic class of region 0. Valid values are: + # 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + # maps to the blue address queue. In this case, valid values are: 0: LPR + # and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + # affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + # traffic. # PSU_DDRC_PCFGQOS0_0_RQOS_MAP_REGION0 0x0 - # Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d - # al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio - # ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc - # values. + # Separation level1 indicating the end of region0 mapping; start of region + # 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + # (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + # lues are used directly as port priorities, where the higher the value co + # rresponds to higher port priority. All of the map_level* registers must + # be set to distinct values. # PSU_DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1 0xb # Port n Read QoS Configuration Register 0 @@ -2932,10 +3614,12 @@ set psu_ddr_init_data { mask_write 0XFD070494 0x0033000F 0x0020000B # Register : PCFGQOS1_0 @ 0XFD070498

- # Specifies the timeout value for transactions mapped to the red address queue. + # Specifies the timeout value for transactions mapped to the red address q + # ueue. # PSU_DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR 0x0 - # Specifies the timeout value for transactions mapped to the blue address queue. + # Specifies the timeout value for transactions mapped to the blue address + # queue. # PSU_DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB 0x0 # Port n Read QoS Configuration Register 1 @@ -2943,30 +3627,41 @@ set psu_ddr_init_data { mask_write 0XFD070498 0x07FF07FF 0x00000000 # Register : PCFGR_1 @ 0XFD0704B4

- # If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - # d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - # imit register. + # If set to 1, enables the Page Match feature. If enabled, once a requesti + # ng port is granted, the port is continued to be granted if the following + # immediate commands are to the same memory page (same bank and same row) + # . See also related PCCFG.pagematch_limit register. # PSU_DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN 0x0 - # If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por - # becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG. - # o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add - # ess handshaking (it is not associated with any particular command). + # If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + # bled and arurgent is asserted by the master, that port becomes the highe + # st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + # RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + # urgent signal can be asserted anytime and as long as required which is i + # ndependent of address handshaking (it is not associated with any particu + # lar command). # PSU_DDRC_PCFGR_1_RD_PORT_URGENT_EN 0x1 # If set to 1, enables aging function for the read channel of the port. # PSU_DDRC_PCFGR_1_RD_PORT_AGING_EN 0x0 - # Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g - # ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - # he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority - # will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre - # ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the - # aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st - # ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w - # ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D - # RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: - # he two LSBs of this register field are tied internally to 2'b00. + # Determines the initial load value of read aging counters. These counters + # will be parallel loaded after reset, or after each grant to the corresp + # onding port. The aging counters down-count every clock cycle where the p + # ort is requesting but not granted. The higher significant 5-bits of the + # read aging counter sets the priority of the read channel of a given port + # . Port's priority will increase as the higher significant 5-bits of the + # counter starts to decrease. When the aging counter becomes 0, the corres + # ponding port channel will have the highest priority level (timeout condi + # tion - Priority0). For multi-port configurations, the aging counters can + # not be used to set port priorities when external dynamic priority inputs + # (arqos) are enabled (timeout is still applicable). For single port conf + # igurations, the aging counters are only used when they timeout (become 0 + # ) to force read-write direction switching. In this case, external dynami + # c priority input, arqos (for reads only) can still be used to set the DD + # RC read priority (2 priority levels: low priority read - LPR, high prior + # ity read - HPR) on a command by command basis. Note: The two LSBs of thi + # s register field are tied internally to 2'b00. # PSU_DDRC_PCFGR_1_RD_PORT_PRIORITY 0xf # Port n Configuration Read Register @@ -2974,33 +3669,42 @@ set psu_ddr_init_data { mask_write 0XFD0704B4 0x000073FF 0x0000200F # Register : PCFGW_1 @ 0XFD0704B8

- # If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - # d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - # imit register. - # PSU_DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN 0x1 + # If set to 1, enables the Page Match feature. If enabled, once a requesti + # ng port is granted, the port is continued to be granted if the following + # immediate commands are to the same memory page (same bank and same row) + # . See also related PCCFG.pagematch_limit register. + # PSU_DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN 0x0 - # If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por - # becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register - # Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is - # not associated with any particular command). + # If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + # bled and awurgent is asserted by the master, that port becomes the highe + # st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + # ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + # serted anytime and as long as required which is independent of address h + # andshaking (it is not associated with any particular command). # PSU_DDRC_PCFGW_1_WR_PORT_URGENT_EN 0x1 # If set to 1, enables aging function for the write channel of the port. # PSU_DDRC_PCFGW_1_WR_PORT_AGING_EN 0x0 - # Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each - # rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - # The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port - # s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0 - # the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno - # be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For - # ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch - # ng. Note: The two LSBs of this register field are tied internally to 2'b00. + # Determines the initial load value of write aging counters. These counter + # s will be parallel loaded after reset, or after each grant to the corres + # ponding port. The aging counters down-count every clock cycle where the + # port is requesting but not granted. The higher significant 5-bits of the + # write aging counter sets the initial priority of the write channel of a + # given port. Port's priority will increase as the higher significant 5-b + # its of the counter starts to decrease. When the aging counter becomes 0, + # the corresponding port channel will have the highest priority level. Fo + # r multi-port configurations, the aging counters cannot be used to set po + # rt priorities when external dynamic priority inputs (awqos) are enabled + # (timeout is still applicable). For single port configurations, the aging + # counters are only used when they timeout (become 0) to force read-write + # direction switching. Note: The two LSBs of this register field are tied + # internally to 2'b00. # PSU_DDRC_PCFGW_1_WR_PORT_PRIORITY 0xf # Port n Configuration Write Register - #(OFFSET, MASK, VALUE) (0XFD0704B8, 0x000073FFU ,0x0000600FU) */ - mask_write 0XFD0704B8 0x000073FF 0x0000600F + #(OFFSET, MASK, VALUE) (0XFD0704B8, 0x000073FFU ,0x0000200FU) */ + mask_write 0XFD0704B8 0x000073FF 0x0000200F # Register : PCTRL_1 @ 0XFD070540

# Enables port n. @@ -3011,31 +3715,43 @@ set psu_ddr_init_data { mask_write 0XFD070540 0x00000001 0x00000001 # Register : PCFGQOS0_1 @ 0XFD070544

- # This bitfield indicates the traffic class of region2. For dual address queue configurations, region2 maps to the red address - # ueue. Valid values are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and traffic class of region2 - # s set to 1 (VPR), VPR traffic is aliased to LPR traffic. + # This bitfield indicates the traffic class of region2. For dual address q + # ueue configurations, region2 maps to the red address queue. Valid values + # are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN + # = 0) and traffic class of region2 is set to 1 (VPR), VPR traffic is ali + # ased to LPR traffic. # PSU_DDRC_PCFGQOS0_1_RQOS_MAP_REGION2 0x2 - # This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf - # gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is - # disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. + # This bitfield indicates the traffic class of region 1. Valid values are: + # 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + # maps to the blue address queue. In this case, valid values are 0: LPR a + # nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + # ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + # traffic. # PSU_DDRC_PCFGQOS0_1_RQOS_MAP_REGION1 0x0 - # This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi - # urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i - # disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. + # This bitfield indicates the traffic class of region 0. Valid values are: + # 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + # maps to the blue address queue. In this case, valid values are: 0: LPR + # and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + # affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + # traffic. # PSU_DDRC_PCFGQOS0_1_RQOS_MAP_REGION0 0x0 - # Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (le - # el1 + 1) to 14 which corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note that for PA, arqos values are used - # directly as port priorities, where the higher the value corresponds to higher port priority. All of the map_level* registers - # ust be set to distinct values. + # Separation level2 indicating the end of region1 mapping; start of region + # 1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 whi + # ch corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note + # that for PA, arqos values are used directly as port priorities, where t + # he higher the value corresponds to higher port priority. All of the map_ + # level* registers must be set to distinct values. # PSU_DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2 0xb - # Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d - # al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio - # ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc - # values. + # Separation level1 indicating the end of region0 mapping; start of region + # 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + # (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + # lues are used directly as port priorities, where the higher the value co + # rresponds to higher port priority. All of the map_level* registers must + # be set to distinct values. # PSU_DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1 0x3 # Port n Read QoS Configuration Register 0 @@ -3043,10 +3759,12 @@ set psu_ddr_init_data { mask_write 0XFD070544 0x03330F0F 0x02000B03 # Register : PCFGQOS1_1 @ 0XFD070548

- # Specifies the timeout value for transactions mapped to the red address queue. + # Specifies the timeout value for transactions mapped to the red address q + # ueue. # PSU_DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR 0x0 - # Specifies the timeout value for transactions mapped to the blue address queue. + # Specifies the timeout value for transactions mapped to the blue address + # queue. # PSU_DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB 0x0 # Port n Read QoS Configuration Register 1 @@ -3054,30 +3772,41 @@ set psu_ddr_init_data { mask_write 0XFD070548 0x07FF07FF 0x00000000 # Register : PCFGR_2 @ 0XFD070564

- # If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - # d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - # imit register. + # If set to 1, enables the Page Match feature. If enabled, once a requesti + # ng port is granted, the port is continued to be granted if the following + # immediate commands are to the same memory page (same bank and same row) + # . See also related PCCFG.pagematch_limit register. # PSU_DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN 0x0 - # If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por - # becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG. - # o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add - # ess handshaking (it is not associated with any particular command). + # If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + # bled and arurgent is asserted by the master, that port becomes the highe + # st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + # RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + # urgent signal can be asserted anytime and as long as required which is i + # ndependent of address handshaking (it is not associated with any particu + # lar command). # PSU_DDRC_PCFGR_2_RD_PORT_URGENT_EN 0x1 # If set to 1, enables aging function for the read channel of the port. # PSU_DDRC_PCFGR_2_RD_PORT_AGING_EN 0x0 - # Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g - # ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - # he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority - # will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre - # ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the - # aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st - # ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w - # ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D - # RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: - # he two LSBs of this register field are tied internally to 2'b00. + # Determines the initial load value of read aging counters. These counters + # will be parallel loaded after reset, or after each grant to the corresp + # onding port. The aging counters down-count every clock cycle where the p + # ort is requesting but not granted. The higher significant 5-bits of the + # read aging counter sets the priority of the read channel of a given port + # . Port's priority will increase as the higher significant 5-bits of the + # counter starts to decrease. When the aging counter becomes 0, the corres + # ponding port channel will have the highest priority level (timeout condi + # tion - Priority0). For multi-port configurations, the aging counters can + # not be used to set port priorities when external dynamic priority inputs + # (arqos) are enabled (timeout is still applicable). For single port conf + # igurations, the aging counters are only used when they timeout (become 0 + # ) to force read-write direction switching. In this case, external dynami + # c priority input, arqos (for reads only) can still be used to set the DD + # RC read priority (2 priority levels: low priority read - LPR, high prior + # ity read - HPR) on a command by command basis. Note: The two LSBs of thi + # s register field are tied internally to 2'b00. # PSU_DDRC_PCFGR_2_RD_PORT_PRIORITY 0xf # Port n Configuration Read Register @@ -3085,33 +3814,42 @@ set psu_ddr_init_data { mask_write 0XFD070564 0x000073FF 0x0000200F # Register : PCFGW_2 @ 0XFD070568

- # If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - # d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - # imit register. - # PSU_DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN 0x1 + # If set to 1, enables the Page Match feature. If enabled, once a requesti + # ng port is granted, the port is continued to be granted if the following + # immediate commands are to the same memory page (same bank and same row) + # . See also related PCCFG.pagematch_limit register. + # PSU_DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN 0x0 - # If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por - # becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register - # Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is - # not associated with any particular command). + # If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + # bled and awurgent is asserted by the master, that port becomes the highe + # st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + # ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + # serted anytime and as long as required which is independent of address h + # andshaking (it is not associated with any particular command). # PSU_DDRC_PCFGW_2_WR_PORT_URGENT_EN 0x1 # If set to 1, enables aging function for the write channel of the port. # PSU_DDRC_PCFGW_2_WR_PORT_AGING_EN 0x0 - # Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each - # rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - # The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port - # s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0 - # the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno - # be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For - # ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch - # ng. Note: The two LSBs of this register field are tied internally to 2'b00. + # Determines the initial load value of write aging counters. These counter + # s will be parallel loaded after reset, or after each grant to the corres + # ponding port. The aging counters down-count every clock cycle where the + # port is requesting but not granted. The higher significant 5-bits of the + # write aging counter sets the initial priority of the write channel of a + # given port. Port's priority will increase as the higher significant 5-b + # its of the counter starts to decrease. When the aging counter becomes 0, + # the corresponding port channel will have the highest priority level. Fo + # r multi-port configurations, the aging counters cannot be used to set po + # rt priorities when external dynamic priority inputs (awqos) are enabled + # (timeout is still applicable). For single port configurations, the aging + # counters are only used when they timeout (become 0) to force read-write + # direction switching. Note: The two LSBs of this register field are tied + # internally to 2'b00. # PSU_DDRC_PCFGW_2_WR_PORT_PRIORITY 0xf # Port n Configuration Write Register - #(OFFSET, MASK, VALUE) (0XFD070568, 0x000073FFU ,0x0000600FU) */ - mask_write 0XFD070568 0x000073FF 0x0000600F + #(OFFSET, MASK, VALUE) (0XFD070568, 0x000073FFU ,0x0000200FU) */ + mask_write 0XFD070568 0x000073FF 0x0000200F # Register : PCTRL_2 @ 0XFD0705F0

# Enables port n. @@ -3122,31 +3860,43 @@ set psu_ddr_init_data { mask_write 0XFD0705F0 0x00000001 0x00000001 # Register : PCFGQOS0_2 @ 0XFD0705F4

- # This bitfield indicates the traffic class of region2. For dual address queue configurations, region2 maps to the red address - # ueue. Valid values are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and traffic class of region2 - # s set to 1 (VPR), VPR traffic is aliased to LPR traffic. + # This bitfield indicates the traffic class of region2. For dual address q + # ueue configurations, region2 maps to the red address queue. Valid values + # are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN + # = 0) and traffic class of region2 is set to 1 (VPR), VPR traffic is ali + # ased to LPR traffic. # PSU_DDRC_PCFGQOS0_2_RQOS_MAP_REGION2 0x2 - # This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf - # gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is - # disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. + # This bitfield indicates the traffic class of region 1. Valid values are: + # 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + # maps to the blue address queue. In this case, valid values are 0: LPR a + # nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + # ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + # traffic. # PSU_DDRC_PCFGQOS0_2_RQOS_MAP_REGION1 0x0 - # This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi - # urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i - # disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. + # This bitfield indicates the traffic class of region 0. Valid values are: + # 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + # maps to the blue address queue. In this case, valid values are: 0: LPR + # and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + # affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + # traffic. # PSU_DDRC_PCFGQOS0_2_RQOS_MAP_REGION0 0x0 - # Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (le - # el1 + 1) to 14 which corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note that for PA, arqos values are used - # directly as port priorities, where the higher the value corresponds to higher port priority. All of the map_level* registers - # ust be set to distinct values. + # Separation level2 indicating the end of region1 mapping; start of region + # 1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 whi + # ch corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note + # that for PA, arqos values are used directly as port priorities, where t + # he higher the value corresponds to higher port priority. All of the map_ + # level* registers must be set to distinct values. # PSU_DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2 0xb - # Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d - # al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio - # ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc - # values. + # Separation level1 indicating the end of region0 mapping; start of region + # 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + # (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + # lues are used directly as port priorities, where the higher the value co + # rresponds to higher port priority. All of the map_level* registers must + # be set to distinct values. # PSU_DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1 0x3 # Port n Read QoS Configuration Register 0 @@ -3154,10 +3904,12 @@ set psu_ddr_init_data { mask_write 0XFD0705F4 0x03330F0F 0x02000B03 # Register : PCFGQOS1_2 @ 0XFD0705F8

- # Specifies the timeout value for transactions mapped to the red address queue. + # Specifies the timeout value for transactions mapped to the red address q + # ueue. # PSU_DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR 0x0 - # Specifies the timeout value for transactions mapped to the blue address queue. + # Specifies the timeout value for transactions mapped to the blue address + # queue. # PSU_DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB 0x0 # Port n Read QoS Configuration Register 1 @@ -3165,30 +3917,41 @@ set psu_ddr_init_data { mask_write 0XFD0705F8 0x07FF07FF 0x00000000 # Register : PCFGR_3 @ 0XFD070614

- # If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - # d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - # imit register. + # If set to 1, enables the Page Match feature. If enabled, once a requesti + # ng port is granted, the port is continued to be granted if the following + # immediate commands are to the same memory page (same bank and same row) + # . See also related PCCFG.pagematch_limit register. # PSU_DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN 0x0 - # If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por - # becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG. - # o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add - # ess handshaking (it is not associated with any particular command). + # If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + # bled and arurgent is asserted by the master, that port becomes the highe + # st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + # RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + # urgent signal can be asserted anytime and as long as required which is i + # ndependent of address handshaking (it is not associated with any particu + # lar command). # PSU_DDRC_PCFGR_3_RD_PORT_URGENT_EN 0x1 # If set to 1, enables aging function for the read channel of the port. # PSU_DDRC_PCFGR_3_RD_PORT_AGING_EN 0x0 - # Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g - # ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - # he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority - # will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre - # ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the - # aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st - # ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w - # ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D - # RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: - # he two LSBs of this register field are tied internally to 2'b00. + # Determines the initial load value of read aging counters. These counters + # will be parallel loaded after reset, or after each grant to the corresp + # onding port. The aging counters down-count every clock cycle where the p + # ort is requesting but not granted. The higher significant 5-bits of the + # read aging counter sets the priority of the read channel of a given port + # . Port's priority will increase as the higher significant 5-bits of the + # counter starts to decrease. When the aging counter becomes 0, the corres + # ponding port channel will have the highest priority level (timeout condi + # tion - Priority0). For multi-port configurations, the aging counters can + # not be used to set port priorities when external dynamic priority inputs + # (arqos) are enabled (timeout is still applicable). For single port conf + # igurations, the aging counters are only used when they timeout (become 0 + # ) to force read-write direction switching. In this case, external dynami + # c priority input, arqos (for reads only) can still be used to set the DD + # RC read priority (2 priority levels: low priority read - LPR, high prior + # ity read - HPR) on a command by command basis. Note: The two LSBs of thi + # s register field are tied internally to 2'b00. # PSU_DDRC_PCFGR_3_RD_PORT_PRIORITY 0xf # Port n Configuration Read Register @@ -3196,33 +3959,42 @@ set psu_ddr_init_data { mask_write 0XFD070614 0x000073FF 0x0000200F # Register : PCFGW_3 @ 0XFD070618

- # If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - # d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - # imit register. - # PSU_DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN 0x1 + # If set to 1, enables the Page Match feature. If enabled, once a requesti + # ng port is granted, the port is continued to be granted if the following + # immediate commands are to the same memory page (same bank and same row) + # . See also related PCCFG.pagematch_limit register. + # PSU_DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN 0x0 - # If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por - # becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register - # Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is - # not associated with any particular command). + # If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + # bled and awurgent is asserted by the master, that port becomes the highe + # st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + # ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + # serted anytime and as long as required which is independent of address h + # andshaking (it is not associated with any particular command). # PSU_DDRC_PCFGW_3_WR_PORT_URGENT_EN 0x1 # If set to 1, enables aging function for the write channel of the port. # PSU_DDRC_PCFGW_3_WR_PORT_AGING_EN 0x0 - # Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each - # rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - # The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port - # s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0 - # the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno - # be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For - # ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch - # ng. Note: The two LSBs of this register field are tied internally to 2'b00. + # Determines the initial load value of write aging counters. These counter + # s will be parallel loaded after reset, or after each grant to the corres + # ponding port. The aging counters down-count every clock cycle where the + # port is requesting but not granted. The higher significant 5-bits of the + # write aging counter sets the initial priority of the write channel of a + # given port. Port's priority will increase as the higher significant 5-b + # its of the counter starts to decrease. When the aging counter becomes 0, + # the corresponding port channel will have the highest priority level. Fo + # r multi-port configurations, the aging counters cannot be used to set po + # rt priorities when external dynamic priority inputs (awqos) are enabled + # (timeout is still applicable). For single port configurations, the aging + # counters are only used when they timeout (become 0) to force read-write + # direction switching. Note: The two LSBs of this register field are tied + # internally to 2'b00. # PSU_DDRC_PCFGW_3_WR_PORT_PRIORITY 0xf # Port n Configuration Write Register - #(OFFSET, MASK, VALUE) (0XFD070618, 0x000073FFU ,0x0000600FU) */ - mask_write 0XFD070618 0x000073FF 0x0000600F + #(OFFSET, MASK, VALUE) (0XFD070618, 0x000073FFU ,0x0000200FU) */ + mask_write 0XFD070618 0x000073FF 0x0000200F # Register : PCTRL_3 @ 0XFD0706A0

# Enables port n. @@ -3233,20 +4005,28 @@ set psu_ddr_init_data { mask_write 0XFD0706A0 0x00000001 0x00000001 # Register : PCFGQOS0_3 @ 0XFD0706A4

- # This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf - # gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is - # disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. + # This bitfield indicates the traffic class of region 1. Valid values are: + # 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + # maps to the blue address queue. In this case, valid values are 0: LPR a + # nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + # ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + # traffic. # PSU_DDRC_PCFGQOS0_3_RQOS_MAP_REGION1 0x1 - # This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi - # urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i - # disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. + # This bitfield indicates the traffic class of region 0. Valid values are: + # 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + # maps to the blue address queue. In this case, valid values are: 0: LPR + # and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + # affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + # traffic. # PSU_DDRC_PCFGQOS0_3_RQOS_MAP_REGION0 0x0 - # Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d - # al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio - # ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc - # values. + # Separation level1 indicating the end of region0 mapping; start of region + # 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + # (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + # lues are used directly as port priorities, where the higher the value co + # rresponds to higher port priority. All of the map_level* registers must + # be set to distinct values. # PSU_DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1 0x3 # Port n Read QoS Configuration Register 0 @@ -3254,10 +4034,12 @@ set psu_ddr_init_data { mask_write 0XFD0706A4 0x0033000F 0x00100003 # Register : PCFGQOS1_3 @ 0XFD0706A8

- # Specifies the timeout value for transactions mapped to the red address queue. + # Specifies the timeout value for transactions mapped to the red address q + # ueue. # PSU_DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR 0x0 - # Specifies the timeout value for transactions mapped to the blue address queue. + # Specifies the timeout value for transactions mapped to the blue address + # queue. # PSU_DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB 0x4f # Port n Read QoS Configuration Register 1 @@ -3265,17 +4047,22 @@ set psu_ddr_init_data { mask_write 0XFD0706A8 0x07FF07FF 0x0000004F # Register : PCFGWQOS0_3 @ 0XFD0706AC

- # This bitfield indicates the traffic class of region 1. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2 - # VPW_EN = 0) and traffic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW traffic. + # This bitfield indicates the traffic class of region 1. Valid values are: + # 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + # affic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW + # traffic. # PSU_DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1 0x1 - # This bitfield indicates the traffic class of region 0. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2 - # VPW_EN = 0) and traffic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW traffic. + # This bitfield indicates the traffic class of region 0. Valid values are: + # 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + # affic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW + # traffic. # PSU_DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0 0x0 - # Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 14 which c - # rresponds to awqos. Note that for PA, awqos values are used directly as port priorities, where the higher the value correspon - # s to higher port priority. + # Separation level indicating the end of region0 mapping; start of region0 + # is 0. Possible values for level1 are 0 to 14 which corresponds to awqos + # . Note that for PA, awqos values are used directly as port priorities, w + # here the higher the value corresponds to higher port priority. # PSU_DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL 0x3 # Port n Write QoS Configuration Register 0 @@ -3291,64 +4078,84 @@ set psu_ddr_init_data { mask_write 0XFD0706B0 0x000007FF 0x0000004F # Register : PCFGR_4 @ 0XFD0706C4

- # If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - # d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - # imit register. - # PSU_DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN 0x1 + # If set to 1, enables the Page Match feature. If enabled, once a requesti + # ng port is granted, the port is continued to be granted if the following + # immediate commands are to the same memory page (same bank and same row) + # . See also related PCCFG.pagematch_limit register. + # PSU_DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN 0x0 - # If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por - # becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG. - # o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add - # ess handshaking (it is not associated with any particular command). + # If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + # bled and arurgent is asserted by the master, that port becomes the highe + # st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + # RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + # urgent signal can be asserted anytime and as long as required which is i + # ndependent of address handshaking (it is not associated with any particu + # lar command). # PSU_DDRC_PCFGR_4_RD_PORT_URGENT_EN 0x1 # If set to 1, enables aging function for the read channel of the port. # PSU_DDRC_PCFGR_4_RD_PORT_AGING_EN 0x0 - # Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g - # ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - # he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority - # will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre - # ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the - # aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st - # ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w - # ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D - # RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: - # he two LSBs of this register field are tied internally to 2'b00. + # Determines the initial load value of read aging counters. These counters + # will be parallel loaded after reset, or after each grant to the corresp + # onding port. The aging counters down-count every clock cycle where the p + # ort is requesting but not granted. The higher significant 5-bits of the + # read aging counter sets the priority of the read channel of a given port + # . Port's priority will increase as the higher significant 5-bits of the + # counter starts to decrease. When the aging counter becomes 0, the corres + # ponding port channel will have the highest priority level (timeout condi + # tion - Priority0). For multi-port configurations, the aging counters can + # not be used to set port priorities when external dynamic priority inputs + # (arqos) are enabled (timeout is still applicable). For single port conf + # igurations, the aging counters are only used when they timeout (become 0 + # ) to force read-write direction switching. In this case, external dynami + # c priority input, arqos (for reads only) can still be used to set the DD + # RC read priority (2 priority levels: low priority read - LPR, high prior + # ity read - HPR) on a command by command basis. Note: The two LSBs of thi + # s register field are tied internally to 2'b00. # PSU_DDRC_PCFGR_4_RD_PORT_PRIORITY 0xf # Port n Configuration Read Register - #(OFFSET, MASK, VALUE) (0XFD0706C4, 0x000073FFU ,0x0000600FU) */ - mask_write 0XFD0706C4 0x000073FF 0x0000600F + #(OFFSET, MASK, VALUE) (0XFD0706C4, 0x000073FFU ,0x0000200FU) */ + mask_write 0XFD0706C4 0x000073FF 0x0000200F # Register : PCFGW_4 @ 0XFD0706C8

- # If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - # d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - # imit register. - # PSU_DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN 0x1 + # If set to 1, enables the Page Match feature. If enabled, once a requesti + # ng port is granted, the port is continued to be granted if the following + # immediate commands are to the same memory page (same bank and same row) + # . See also related PCCFG.pagematch_limit register. + # PSU_DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN 0x0 - # If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por - # becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register - # Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is - # not associated with any particular command). + # If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + # bled and awurgent is asserted by the master, that port becomes the highe + # st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + # ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + # serted anytime and as long as required which is independent of address h + # andshaking (it is not associated with any particular command). # PSU_DDRC_PCFGW_4_WR_PORT_URGENT_EN 0x1 # If set to 1, enables aging function for the write channel of the port. # PSU_DDRC_PCFGW_4_WR_PORT_AGING_EN 0x0 - # Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each - # rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - # The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port - # s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0 - # the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno - # be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For - # ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch - # ng. Note: The two LSBs of this register field are tied internally to 2'b00. + # Determines the initial load value of write aging counters. These counter + # s will be parallel loaded after reset, or after each grant to the corres + # ponding port. The aging counters down-count every clock cycle where the + # port is requesting but not granted. The higher significant 5-bits of the + # write aging counter sets the initial priority of the write channel of a + # given port. Port's priority will increase as the higher significant 5-b + # its of the counter starts to decrease. When the aging counter becomes 0, + # the corresponding port channel will have the highest priority level. Fo + # r multi-port configurations, the aging counters cannot be used to set po + # rt priorities when external dynamic priority inputs (awqos) are enabled + # (timeout is still applicable). For single port configurations, the aging + # counters are only used when they timeout (become 0) to force read-write + # direction switching. Note: The two LSBs of this register field are tied + # internally to 2'b00. # PSU_DDRC_PCFGW_4_WR_PORT_PRIORITY 0xf # Port n Configuration Write Register - #(OFFSET, MASK, VALUE) (0XFD0706C8, 0x000073FFU ,0x0000600FU) */ - mask_write 0XFD0706C8 0x000073FF 0x0000600F + #(OFFSET, MASK, VALUE) (0XFD0706C8, 0x000073FFU ,0x0000200FU) */ + mask_write 0XFD0706C8 0x000073FF 0x0000200F # Register : PCTRL_4 @ 0XFD070750

# Enables port n. @@ -3359,20 +4166,28 @@ set psu_ddr_init_data { mask_write 0XFD070750 0x00000001 0x00000001 # Register : PCFGQOS0_4 @ 0XFD070754

- # This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf - # gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is - # disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. + # This bitfield indicates the traffic class of region 1. Valid values are: + # 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + # maps to the blue address queue. In this case, valid values are 0: LPR a + # nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + # ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + # traffic. # PSU_DDRC_PCFGQOS0_4_RQOS_MAP_REGION1 0x1 - # This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi - # urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i - # disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. + # This bitfield indicates the traffic class of region 0. Valid values are: + # 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + # maps to the blue address queue. In this case, valid values are: 0: LPR + # and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + # affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + # traffic. # PSU_DDRC_PCFGQOS0_4_RQOS_MAP_REGION0 0x0 - # Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d - # al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio - # ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc - # values. + # Separation level1 indicating the end of region0 mapping; start of region + # 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + # (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + # lues are used directly as port priorities, where the higher the value co + # rresponds to higher port priority. All of the map_level* registers must + # be set to distinct values. # PSU_DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1 0x3 # Port n Read QoS Configuration Register 0 @@ -3380,10 +4195,12 @@ set psu_ddr_init_data { mask_write 0XFD070754 0x0033000F 0x00100003 # Register : PCFGQOS1_4 @ 0XFD070758

- # Specifies the timeout value for transactions mapped to the red address queue. + # Specifies the timeout value for transactions mapped to the red address q + # ueue. # PSU_DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR 0x0 - # Specifies the timeout value for transactions mapped to the blue address queue. + # Specifies the timeout value for transactions mapped to the blue address + # queue. # PSU_DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB 0x4f # Port n Read QoS Configuration Register 1 @@ -3391,17 +4208,22 @@ set psu_ddr_init_data { mask_write 0XFD070758 0x07FF07FF 0x0000004F # Register : PCFGWQOS0_4 @ 0XFD07075C

- # This bitfield indicates the traffic class of region 1. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2 - # VPW_EN = 0) and traffic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW traffic. + # This bitfield indicates the traffic class of region 1. Valid values are: + # 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + # affic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW + # traffic. # PSU_DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1 0x1 - # This bitfield indicates the traffic class of region 0. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2 - # VPW_EN = 0) and traffic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW traffic. + # This bitfield indicates the traffic class of region 0. Valid values are: + # 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + # affic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW + # traffic. # PSU_DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0 0x0 - # Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 14 which c - # rresponds to awqos. Note that for PA, awqos values are used directly as port priorities, where the higher the value correspon - # s to higher port priority. + # Separation level indicating the end of region0 mapping; start of region0 + # is 0. Possible values for level1 are 0 to 14 which corresponds to awqos + # . Note that for PA, awqos values are used directly as port priorities, w + # here the higher the value corresponds to higher port priority. # PSU_DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL 0x3 # Port n Write QoS Configuration Register 0 @@ -3417,30 +4239,41 @@ set psu_ddr_init_data { mask_write 0XFD070760 0x000007FF 0x0000004F # Register : PCFGR_5 @ 0XFD070774

- # If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - # d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - # imit register. + # If set to 1, enables the Page Match feature. If enabled, once a requesti + # ng port is granted, the port is continued to be granted if the following + # immediate commands are to the same memory page (same bank and same row) + # . See also related PCCFG.pagematch_limit register. # PSU_DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN 0x0 - # If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por - # becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG. - # o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add - # ess handshaking (it is not associated with any particular command). + # If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + # bled and arurgent is asserted by the master, that port becomes the highe + # st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + # RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + # urgent signal can be asserted anytime and as long as required which is i + # ndependent of address handshaking (it is not associated with any particu + # lar command). # PSU_DDRC_PCFGR_5_RD_PORT_URGENT_EN 0x1 # If set to 1, enables aging function for the read channel of the port. # PSU_DDRC_PCFGR_5_RD_PORT_AGING_EN 0x0 - # Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g - # ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - # he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority - # will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre - # ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the - # aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st - # ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w - # ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D - # RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: - # he two LSBs of this register field are tied internally to 2'b00. + # Determines the initial load value of read aging counters. These counters + # will be parallel loaded after reset, or after each grant to the corresp + # onding port. The aging counters down-count every clock cycle where the p + # ort is requesting but not granted. The higher significant 5-bits of the + # read aging counter sets the priority of the read channel of a given port + # . Port's priority will increase as the higher significant 5-bits of the + # counter starts to decrease. When the aging counter becomes 0, the corres + # ponding port channel will have the highest priority level (timeout condi + # tion - Priority0). For multi-port configurations, the aging counters can + # not be used to set port priorities when external dynamic priority inputs + # (arqos) are enabled (timeout is still applicable). For single port conf + # igurations, the aging counters are only used when they timeout (become 0 + # ) to force read-write direction switching. In this case, external dynami + # c priority input, arqos (for reads only) can still be used to set the DD + # RC read priority (2 priority levels: low priority read - LPR, high prior + # ity read - HPR) on a command by command basis. Note: The two LSBs of thi + # s register field are tied internally to 2'b00. # PSU_DDRC_PCFGR_5_RD_PORT_PRIORITY 0xf # Port n Configuration Read Register @@ -3448,33 +4281,42 @@ set psu_ddr_init_data { mask_write 0XFD070774 0x000073FF 0x0000200F # Register : PCFGW_5 @ 0XFD070778

- # If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - # d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - # imit register. - # PSU_DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN 0x1 + # If set to 1, enables the Page Match feature. If enabled, once a requesti + # ng port is granted, the port is continued to be granted if the following + # immediate commands are to the same memory page (same bank and same row) + # . See also related PCCFG.pagematch_limit register. + # PSU_DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN 0x0 - # If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por - # becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register - # Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is - # not associated with any particular command). + # If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + # bled and awurgent is asserted by the master, that port becomes the highe + # st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + # ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + # serted anytime and as long as required which is independent of address h + # andshaking (it is not associated with any particular command). # PSU_DDRC_PCFGW_5_WR_PORT_URGENT_EN 0x1 # If set to 1, enables aging function for the write channel of the port. # PSU_DDRC_PCFGW_5_WR_PORT_AGING_EN 0x0 - # Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each - # rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - # The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port - # s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0 - # the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno - # be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For - # ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch - # ng. Note: The two LSBs of this register field are tied internally to 2'b00. + # Determines the initial load value of write aging counters. These counter + # s will be parallel loaded after reset, or after each grant to the corres + # ponding port. The aging counters down-count every clock cycle where the + # port is requesting but not granted. The higher significant 5-bits of the + # write aging counter sets the initial priority of the write channel of a + # given port. Port's priority will increase as the higher significant 5-b + # its of the counter starts to decrease. When the aging counter becomes 0, + # the corresponding port channel will have the highest priority level. Fo + # r multi-port configurations, the aging counters cannot be used to set po + # rt priorities when external dynamic priority inputs (awqos) are enabled + # (timeout is still applicable). For single port configurations, the aging + # counters are only used when they timeout (become 0) to force read-write + # direction switching. Note: The two LSBs of this register field are tied + # internally to 2'b00. # PSU_DDRC_PCFGW_5_WR_PORT_PRIORITY 0xf # Port n Configuration Write Register - #(OFFSET, MASK, VALUE) (0XFD070778, 0x000073FFU ,0x0000600FU) */ - mask_write 0XFD070778 0x000073FF 0x0000600F + #(OFFSET, MASK, VALUE) (0XFD070778, 0x000073FFU ,0x0000200FU) */ + mask_write 0XFD070778 0x000073FF 0x0000200F # Register : PCTRL_5 @ 0XFD070800

# Enables port n. @@ -3485,20 +4327,28 @@ set psu_ddr_init_data { mask_write 0XFD070800 0x00000001 0x00000001 # Register : PCFGQOS0_5 @ 0XFD070804

- # This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf - # gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is - # disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. + # This bitfield indicates the traffic class of region 1. Valid values are: + # 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + # maps to the blue address queue. In this case, valid values are 0: LPR a + # nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + # ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + # traffic. # PSU_DDRC_PCFGQOS0_5_RQOS_MAP_REGION1 0x1 - # This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi - # urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i - # disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. + # This bitfield indicates the traffic class of region 0. Valid values are: + # 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + # maps to the blue address queue. In this case, valid values are: 0: LPR + # and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + # affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + # traffic. # PSU_DDRC_PCFGQOS0_5_RQOS_MAP_REGION0 0x0 - # Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d - # al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio - # ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc - # values. + # Separation level1 indicating the end of region0 mapping; start of region + # 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + # (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + # lues are used directly as port priorities, where the higher the value co + # rresponds to higher port priority. All of the map_level* registers must + # be set to distinct values. # PSU_DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1 0x3 # Port n Read QoS Configuration Register 0 @@ -3506,10 +4356,12 @@ set psu_ddr_init_data { mask_write 0XFD070804 0x0033000F 0x00100003 # Register : PCFGQOS1_5 @ 0XFD070808

- # Specifies the timeout value for transactions mapped to the red address queue. + # Specifies the timeout value for transactions mapped to the red address q + # ueue. # PSU_DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR 0x0 - # Specifies the timeout value for transactions mapped to the blue address queue. + # Specifies the timeout value for transactions mapped to the blue address + # queue. # PSU_DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB 0x4f # Port n Read QoS Configuration Register 1 @@ -3517,17 +4369,22 @@ set psu_ddr_init_data { mask_write 0XFD070808 0x07FF07FF 0x0000004F # Register : PCFGWQOS0_5 @ 0XFD07080C

- # This bitfield indicates the traffic class of region 1. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2 - # VPW_EN = 0) and traffic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW traffic. + # This bitfield indicates the traffic class of region 1. Valid values are: + # 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + # affic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW + # traffic. # PSU_DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1 0x1 - # This bitfield indicates the traffic class of region 0. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2 - # VPW_EN = 0) and traffic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW traffic. + # This bitfield indicates the traffic class of region 0. Valid values are: + # 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + # affic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW + # traffic. # PSU_DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0 0x0 - # Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 14 which c - # rresponds to awqos. Note that for PA, awqos values are used directly as port priorities, where the higher the value correspon - # s to higher port priority. + # Separation level indicating the end of region0 mapping; start of region0 + # is 0. Possible values for level1 are 0 to 14 which corresponds to awqos + # . Note that for PA, awqos values are used directly as port priorities, w + # here the higher the value corresponds to higher port priority. # PSU_DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL 0x3 # Port n Write QoS Configuration Register 0 @@ -3543,8 +4400,9 @@ set psu_ddr_init_data { mask_write 0XFD070810 0x000007FF 0x0000004F # Register : SARBASE0 @ 0XFD070F04

- # Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x] and araddr[UMCTL2_A_ADDRW-1:x] where x is determine - # by the minimum block size parameter UMCTL2_SARMINSIZE: (x=log2(block size)). + # Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x + # ] and araddr[UMCTL2_A_ADDRW-1:x] where x is determined by the minimum bl + # ock size parameter UMCTL2_SARMINSIZE: (x=log2(block size)). # PSU_DDRC_SARBASE0_BASE_ADDR 0x0 # SAR Base Address Register n @@ -3552,9 +4410,11 @@ set psu_ddr_init_data { mask_write 0XFD070F04 0x000001FF 0x00000000 # Register : SARSIZE0 @ 0XFD070F08

- # Number of blocks for address region n. This register determines the total size of the region in multiples of minimum block si - # e as specified by the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded as number of blocks = nblocks + 1. - # or example, if register is programmed to 0, region will have 1 block. + # Number of blocks for address region n. This register determines the tota + # l size of the region in multiples of minimum block size as specified by + # the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded + # as number of blocks = nblocks + 1. For example, if register is programme + # d to 0, region will have 1 block. # PSU_DDRC_SARSIZE0_NBLOCKS 0x0 # SAR Size Register n @@ -3562,8 +4422,9 @@ set psu_ddr_init_data { mask_write 0XFD070F08 0x000000FF 0x00000000 # Register : SARBASE1 @ 0XFD070F0C

- # Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x] and araddr[UMCTL2_A_ADDRW-1:x] where x is determine - # by the minimum block size parameter UMCTL2_SARMINSIZE: (x=log2(block size)). + # Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x + # ] and araddr[UMCTL2_A_ADDRW-1:x] where x is determined by the minimum bl + # ock size parameter UMCTL2_SARMINSIZE: (x=log2(block size)). # PSU_DDRC_SARBASE1_BASE_ADDR 0x10 # SAR Base Address Register n @@ -3571,9 +4432,11 @@ set psu_ddr_init_data { mask_write 0XFD070F0C 0x000001FF 0x00000010 # Register : SARSIZE1 @ 0XFD070F10

- # Number of blocks for address region n. This register determines the total size of the region in multiples of minimum block si - # e as specified by the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded as number of blocks = nblocks + 1. - # or example, if register is programmed to 0, region will have 1 block. + # Number of blocks for address region n. This register determines the tota + # l size of the region in multiples of minimum block size as specified by + # the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded + # as number of blocks = nblocks + 1. For example, if register is programme + # d to 0, region will have 1 block. # PSU_DDRC_SARSIZE1_NBLOCKS 0xf # SAR Size Register n @@ -3581,38 +4444,51 @@ set psu_ddr_init_data { mask_write 0XFD070F10 0x000000FF 0x0000000F # Register : DFITMG0_SHADOW @ 0XFD072190

- # Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signa - # s at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligne - # , this timing parameter should be rounded up to the next integer value. Note that if using RDIMM, it is necessary to incremen - # this parameter by RDIMM's extra cycle of latency in terms of DFI clock. + # Specifies the number of DFI clock cycles after an assertion or de-assert + # ion of the DFI control signals that the control signals at the PHY-DRAM + # interface reflect the assertion or de-assertion. If the DFI clock and th + # e memory clock are not phase-aligned, this timing parameter should be ro + # unded up to the next integer value. Note that if using RDIMM, it is nece + # ssary to increment this parameter by RDIMM's extra cycle of latency in t + # erms of DFI clock. # PSU_DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY 0x7 - # Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR or SDR values Selects whether value in DFITM - # 0.dfi_t_rddata_en is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles R - # fer to PHY specification for correct value. + # Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated u + # sing HDR or SDR values Selects whether value in DFITMG0.dfi_t_rddata_en + # is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles + # - 1 in terms of SDR clock cycles Refer to PHY specification for correct + # value. # PSU_DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR 0x1 - # Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. Refer to PHY spe - # ification for correct value. This corresponds to the DFI parameter trddata_en. Note that, depending on the PHY, if using RDIM - # , it may be necessary to use the value (CL + 1) in the calculation of trddata_en. This is to compensate for the extra cycle o - # latency through the RDIMM. Unit: Clocks + # Time from the assertion of a read command on the DFI interface to the as + # sertion of the dfi_rddata_en signal. Refer to PHY specification for corr + # ect value. This corresponds to the DFI parameter trddata_en. Note that, + # depending on the PHY, if using RDIMM, it may be necessary to use the val + # ue (CL + 1) in the calculation of trddata_en. This is to compensate for + # the extra cycle of latency through the RDIMM. Unit: Clocks # PSU_DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN 0x2 - # Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using HDR or SDR values Selects whether value in DFITMG - # .dfi_tphy_wrlat is in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.dfi_tphy_wrdata is in terms of SDR or - # HDR clock cycles - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles Refer to PHY specification for correct val - # e. + # Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated us + # ing HDR or SDR values Selects whether value in DFITMG0.dfi_tphy_wrlat is + # in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.df + # i_tphy_wrdata is in terms of SDR or HDR clock cycles - 0 in terms of HDR + # clock cycles - 1 in terms of SDR clock cycles Refer to PHY specificatio + # n for correct value. # PSU_DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR 0x1 - # Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on th - # dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. N - # te, max supported value is 8. Unit: Clocks + # Specifies the number of clock cycles between when dfi_wrdata_en is asser + # ted to when the associated write data is driven on the dfi_wrdata signal + # . This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY + # specification for correct value. Note, max supported value is 8. Unit: + # Clocks # PSU_DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA 0x0 - # Write latency Number of clocks from the write command to write data enable (dfi_wrdata_en). This corresponds to the DFI timin - # parameter tphy_wrlat. Refer to PHY specification for correct value.Note that, depending on the PHY, if using RDIMM, it may b - # necessary to use the value (CL + 1) in the calculation of tphy_wrlat. This is to compensate for the extra cycle of latency t - # rough the RDIMM. + # Write latency Number of clocks from the write command to write data enab + # le (dfi_wrdata_en). This corresponds to the DFI timing parameter tphy_wr + # lat. Refer to PHY specification for correct value.Note that, depending o + # n the PHY, if using RDIMM, it may be necessary to use the value (CL + 1) + # in the calculation of tphy_wrlat. This is to compensate for the extra c + # ycle of latency through the RDIMM. # PSU_DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT 0x2 # DFI Timing Shadow Register 0 @@ -3624,9 +4500,12 @@ set psu_ddr_init_data { # DDR block level reset inside of the DDR Sub System # PSU_CRF_APB_RST_DDR_SS_DDR_RESET 0X0 + # APM block level reset inside of the DDR Sub System + # PSU_CRF_APB_RST_DDR_SS_APM_RESET 0X0 + # DDR sub system block level reset - #(OFFSET, MASK, VALUE) (0XFD1A0108, 0x00000008U ,0x00000000U) */ - mask_write 0XFD1A0108 0x00000008 0x00000000 + #(OFFSET, MASK, VALUE) (0XFD1A0108, 0x0000000CU ,0x00000000U) */ + mask_write 0XFD1A0108 0x0000000C 0x00000000 # : DDR PHY # Register : PGCR0 @ 0XFD080010

@@ -3687,11 +4566,11 @@ set psu_ddr_init_data { # PSU_DDR_PHY_PGCR2_PLLFSMBYP 0x0 # Refresh Period - # PSU_DDR_PHY_PGCR2_TREFPRD 0x10028 + # PSU_DDR_PHY_PGCR2_TREFPRD 0x10010 # PHY General Configuration Register 2 - #(OFFSET, MASK, VALUE) (0XFD080018, 0xFFFFFFFFU ,0x00F10028U) */ - mask_write 0XFD080018 0xFFFFFFFF 0x00F10028 + #(OFFSET, MASK, VALUE) (0XFD080018, 0xFFFFFFFFU ,0x00F10010U) */ + mask_write 0XFD080018 0xFFFFFFFF 0x00F10010 # Register : PGCR3 @ 0XFD08001C

# CKN Enable @@ -3765,41 +4644,86 @@ set psu_ddr_init_data { # Register : PTR0 @ 0XFD080040

# PLL Power-Down Time - # PSU_DDR_PHY_PTR0_TPLLPD 0x2f0 + # PSU_DDR_PHY_PTR0_TPLLPD 0x56 # PLL Gear Shift Time - # PSU_DDR_PHY_PTR0_TPLLGS 0x60 + # PSU_DDR_PHY_PTR0_TPLLGS 0x2155 # PHY Reset Time # PSU_DDR_PHY_PTR0_TPHYRST 0x10 # PHY Timing Register 0 - #(OFFSET, MASK, VALUE) (0XFD080040, 0xFFFFFFFFU ,0x5E001810U) */ - mask_write 0XFD080040 0xFFFFFFFF 0x5E001810 + #(OFFSET, MASK, VALUE) (0XFD080040, 0xFFFFFFFFU ,0x0AC85550U) */ + mask_write 0XFD080040 0xFFFFFFFF 0x0AC85550 # Register : PTR1 @ 0XFD080044

# PLL Lock Time - # PSU_DDR_PHY_PTR1_TPLLLOCK 0x80 + # PSU_DDR_PHY_PTR1_TPLLLOCK 0x4141 # Reserved. Returns zeroes on reads. # PSU_DDR_PHY_PTR1_RESERVED_15_13 0x0 # PLL Reset Time - # PSU_DDR_PHY_PTR1_TPLLRST 0x5f0 + # PSU_DDR_PHY_PTR1_TPLLRST 0xaff # PHY Timing Register 1 - #(OFFSET, MASK, VALUE) (0XFD080044, 0xFFFFFFFFU ,0x008005F0U) */ - mask_write 0XFD080044 0xFFFFFFFF 0x008005F0 + #(OFFSET, MASK, VALUE) (0XFD080044, 0xFFFFFFFFU ,0x41410AFFU) */ + mask_write 0XFD080044 0xFFFFFFFF 0x41410AFF + # Register : PLLCR0 @ 0XFD080068

+ + # PLL Bypass + # PSU_DDR_PHY_PLLCR0_PLLBYP 0x0 + + # PLL Reset + # PSU_DDR_PHY_PLLCR0_PLLRST 0x0 + + # PLL Power Down + # PSU_DDR_PHY_PLLCR0_PLLPD 0x0 + + # Reference Stop Mode + # PSU_DDR_PHY_PLLCR0_RSTOPM 0x0 + + # PLL Frequency Select + # PSU_DDR_PHY_PLLCR0_FRQSEL 0x1 + + # Relock Mode + # PSU_DDR_PHY_PLLCR0_RLOCKM 0x0 + + # Charge Pump Proportional Current Control + # PSU_DDR_PHY_PLLCR0_CPPC 0x8 + + # Charge Pump Integrating Current Control + # PSU_DDR_PHY_PLLCR0_CPIC 0x0 + + # Gear Shift + # PSU_DDR_PHY_PLLCR0_GSHIFT 0x0 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_PLLCR0_RESERVED_11_9 0x0 + + # Analog Test Enable + # PSU_DDR_PHY_PLLCR0_ATOEN 0x0 + + # Analog Test Control + # PSU_DDR_PHY_PLLCR0_ATC 0x0 + + # Digital Test Control + # PSU_DDR_PHY_PLLCR0_DTC 0x0 + + # PLL Control Register 0 (Type B PLL Only) + #(OFFSET, MASK, VALUE) (0XFD080068, 0xFFFFFFFFU ,0x01100000U) */ + mask_write 0XFD080068 0xFFFFFFFF 0x01100000 # Register : DSGCR @ 0XFD080090

# Reserved. Return zeroes on reads. # PSU_DDR_PHY_DSGCR_RESERVED_31_28 0x0 - # When RDBI enabled, this bit is used to select RDBI CL calculation, if it is 1b1, calculation will use RDBICL, otherwise use d - # fault calculation. + # When RDBI enabled, this bit is used to select RDBI CL calculation, if it + # is 1b1, calculation will use RDBICL, otherwise use default calculation. # PSU_DDR_PHY_DSGCR_RDBICLSEL 0x0 - # When RDBI enabled, if RDBICLSEL is asserted, RDBI CL adjust using this value. + # When RDBI enabled, if RDBICLSEL is asserted, RDBI CL adjust using this v + # alue. # PSU_DDR_PHY_DSGCR_RDBICL 0x2 # PHY Impedance Update Enable @@ -3836,7 +4760,7 @@ set psu_ddr_init_data { # PSU_DDR_PHY_DSGCR_DTOODT 0x0 # PHY Update Acknowledge Delay - # PSU_DDR_PHY_DSGCR_PUAD 0x4 + # PSU_DDR_PHY_DSGCR_PUAD 0x5 # Controller Update Acknowledge Enable # PSU_DDR_PHY_DSGCR_CUAEN 0x1 @@ -3854,8 +4778,16 @@ set psu_ddr_init_data { # PSU_DDR_PHY_DSGCR_PUREN 0x1 # DDR System General Configuration Register - #(OFFSET, MASK, VALUE) (0XFD080090, 0xFFFFFFFFU ,0x02A04121U) */ - mask_write 0XFD080090 0xFFFFFFFF 0x02A04121 + #(OFFSET, MASK, VALUE) (0XFD080090, 0xFFFFFFFFU ,0x02A04161U) */ + mask_write 0XFD080090 0xFFFFFFFF 0x02A04161 + # Register : GPR0 @ 0XFD0800C0

+ + # General Purpose Register 0 + # PSU_DDR_PHY_GPR0_GPR0 0xd3 + + # General Purpose Register 0 + #(OFFSET, MASK, VALUE) (0XFD0800C0, 0xFFFFFFFFU ,0x000000D3U) */ + mask_write 0XFD0800C0 0xFFFFFFFF 0x000000D3 # Register : DCR @ 0XFD080100

# DDR4 Gear Down Timing. @@ -3921,30 +4853,31 @@ set psu_ddr_init_data { # PSU_DDR_PHY_DTPR0_RESERVED_7_5 0x0 # Internal read to precharge command delay - # PSU_DDR_PHY_DTPR0_TRTP 0x9 + # PSU_DDR_PHY_DTPR0_TRTP 0x8 # DRAM Timing Parameters Register 0 - #(OFFSET, MASK, VALUE) (0XFD080110, 0xFFFFFFFFU ,0x06240F09U) */ - mask_write 0XFD080110 0xFFFFFFFF 0x06240F09 + #(OFFSET, MASK, VALUE) (0XFD080110, 0xFFFFFFFFU ,0x06240F08U) */ + mask_write 0XFD080110 0xFFFFFFFF 0x06240F08 # Register : DTPR1 @ 0XFD080114

# Reserved. Return zeroes on reads. # PSU_DDR_PHY_DTPR1_RESERVED_31 0x0 - # Minimum delay from when write leveling mode is programmed to the first DQS/DQS# rising edge. + # Minimum delay from when write leveling mode is programmed to the first D + # QS/DQS# rising edge. # PSU_DDR_PHY_DTPR1_TWLMRD 0x28 # Reserved. Return zeroes on reads. # PSU_DDR_PHY_DTPR1_RESERVED_23 0x0 # 4-bank activate period - # PSU_DDR_PHY_DTPR1_TFAW 0x18 + # PSU_DDR_PHY_DTPR1_TFAW 0x20 # Reserved. Return zeroes on reads. # PSU_DDR_PHY_DTPR1_RESERVED_15_11 0x0 # Load mode update delay (DDR4 and DDR3 only) - # PSU_DDR_PHY_DTPR1_TMOD 0x7 + # PSU_DDR_PHY_DTPR1_TMOD 0x0 # Reserved. Return zeroes on reads. # PSU_DDR_PHY_DTPR1_RESERVED_7_5 0x0 @@ -3953,8 +4886,8 @@ set psu_ddr_init_data { # PSU_DDR_PHY_DTPR1_TMRD 0x8 # DRAM Timing Parameters Register 1 - #(OFFSET, MASK, VALUE) (0XFD080114, 0xFFFFFFFFU ,0x28180708U) */ - mask_write 0XFD080114 0xFFFFFFFF 0x28180708 + #(OFFSET, MASK, VALUE) (0XFD080114, 0xFFFFFFFFU ,0x28200008U) */ + mask_write 0XFD080114 0xFFFFFFFF 0x28200008 # Register : DTPR2 @ 0XFD080118

# Reserved. Return zeroes on reads. @@ -3973,17 +4906,17 @@ set psu_ddr_init_data { # PSU_DDR_PHY_DTPR2_RESERVED_23_20 0x0 # CKE minimum pulse width - # PSU_DDR_PHY_DTPR2_TCKE 0x8 + # PSU_DDR_PHY_DTPR2_TCKE 0x7 # Reserved. Return zeroes on reads. # PSU_DDR_PHY_DTPR2_RESERVED_15_10 0x0 # Self refresh exit delay - # PSU_DDR_PHY_DTPR2_TXS 0x200 + # PSU_DDR_PHY_DTPR2_TXS 0x300 # DRAM Timing Parameters Register 2 - #(OFFSET, MASK, VALUE) (0XFD080118, 0xFFFFFFFFU ,0x00080200U) */ - mask_write 0XFD080118 0xFFFFFFFF 0x00080200 + #(OFFSET, MASK, VALUE) (0XFD080118, 0xFFFFFFFFU ,0x00070300U) */ + mask_write 0XFD080118 0xFFFFFFFF 0x00070300 # Register : DTPR3 @ 0XFD08011C

# ODT turn-off delay extension @@ -4034,18 +4967,18 @@ set psu_ddr_init_data { # PSU_DDR_PHY_DTPR4_RESERVED_7_5 0x0 # Power down exit delay - # PSU_DDR_PHY_DTPR4_TXP 0x8 + # PSU_DDR_PHY_DTPR4_TXP 0x7 # DRAM Timing Parameters Register 4 - #(OFFSET, MASK, VALUE) (0XFD080120, 0xFFFFFFFFU ,0x01162B08U) */ - mask_write 0XFD080120 0xFFFFFFFF 0x01162B08 + #(OFFSET, MASK, VALUE) (0XFD080120, 0xFFFFFFFFU ,0x01162B07U) */ + mask_write 0XFD080120 0xFFFFFFFF 0x01162B07 # Register : DTPR5 @ 0XFD080124

# Reserved. Return zeroes on reads. # PSU_DDR_PHY_DTPR5_RESERVED_31_24 0x0 # Activate to activate command delay (same bank) - # PSU_DDR_PHY_DTPR5_TRC 0x32 + # PSU_DDR_PHY_DTPR5_TRC 0x33 # Reserved. Return zeroes on reads. # PSU_DDR_PHY_DTPR5_RESERVED_15 0x0 @@ -4057,11 +4990,11 @@ set psu_ddr_init_data { # PSU_DDR_PHY_DTPR5_RESERVED_7_5 0x0 # Internal write to read command delay - # PSU_DDR_PHY_DTPR5_TWTR 0x9 + # PSU_DDR_PHY_DTPR5_TWTR 0x8 # DRAM Timing Parameters Register 5 - #(OFFSET, MASK, VALUE) (0XFD080124, 0xFFFFFFFFU ,0x00320F09U) */ - mask_write 0XFD080124 0xFFFFFFFF 0x00320F09 + #(OFFSET, MASK, VALUE) (0XFD080124, 0xFFFFFFFFU ,0x00330F08U) */ + mask_write 0XFD080124 0xFFFFFFFF 0x00330F08 # Register : DTPR6 @ 0XFD080128

# PUB Write Latency Enable @@ -4193,15 +5126,18 @@ set psu_ddr_init_data { # DDR4/DDR3 Control Word 5 (CK Driver Characteristics Control Word) # PSU_DDR_PHY_RDIMMCR0_RC5 0x0 - # DDR4 Control Word 4 (ODT and CKE Signals Driver Characteristics Control Word) / DDR3 Control Word 4 (Control Signals Driver C - # aracteristics Control Word) + # DDR4 Control Word 4 (ODT and CKE Signals Driver Characteristics Control + # Word) / DDR3 Control Word 4 (Control Signals Driver Characteristics Cont + # rol Word) # PSU_DDR_PHY_RDIMMCR0_RC4 0x0 - # DDR4 Control Word 3 (CA and CS Signals Driver Characteristics Control Word) / DDR3 Control Word 3 (Command/Address Signals Dr - # ver Characteristrics Control Word) + # DDR4 Control Word 3 (CA and CS Signals Driver Characteristics Control Wo + # rd) / DDR3 Control Word 3 (Command/Address Signals Driver Characteristri + # cs Control Word) # PSU_DDR_PHY_RDIMMCR0_RC3 0x0 - # DDR4 Control Word 2 (Timing and IBT Control Word) / DDR3 Control Word 2 (Timing Control Word) + # DDR4 Control Word 2 (Timing and IBT Control Word) / DDR3 Control Word 2 + # (Timing Control Word) # PSU_DDR_PHY_RDIMMCR0_RC2 0x0 # DDR4/DDR3 Control Word 1 (Clock Driver Enable Control Word) @@ -4227,8 +5163,8 @@ set psu_ddr_init_data { # DDR4 Control Word 12 (Training Control Word) / DDR3 Reserved # PSU_DDR_PHY_RDIMMCR1_RC12 0x0 - # DDR4 Control Word 11 (Operating Voltage VDD and VREFCA Source Control Word) / DDR3 Control Word 11 (Operation Voltage VDD Con - # rol Word) + # DDR4 Control Word 11 (Operating Voltage VDD and VREFCA Source Control Wo + # rd) / DDR3 Control Word 11 (Operation Voltage VDD Control Word) # PSU_DDR_PHY_RDIMMCR1_RC11 0x0 # DDR4/DDR3 Control Word 10 (RDIMM Operating Speed Control Word) @@ -4237,8 +5173,8 @@ set psu_ddr_init_data { # DDR4/DDR3 Control Word 9 (Power Saving Settings Control Word) # PSU_DDR_PHY_RDIMMCR1_RC9 0x0 - # DDR4 Control Word 8 (Input/Output Configuration Control Word) / DDR3 Control Word 8 (Additional Input Bus Termination Setting - # Control Word) + # DDR4 Control Word 8 (Input/Output Configuration Control Word) / DDR3 Con + # trol Word 8 (Additional Input Bus Termination Setting Control Word) # PSU_DDR_PHY_RDIMMCR1_RC8 0x0 # RDIMM Control Register 1 @@ -4247,23 +5183,25 @@ set psu_ddr_init_data { # Register : MR0 @ 0XFD080180

# Reserved. Return zeroes on reads. - # PSU_DDR_PHY_MR0_RESERVED_31_8 0x8 + # PSU_DDR_PHY_MR0_RESERVED_31_8 0x6 # CA Terminating Rank # PSU_DDR_PHY_MR0_CATR 0x0 - # Reserved. These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0. + # Reserved. These are JEDEC reserved bits and are recommended by JEDEC to + # be programmed to 0x0. # PSU_DDR_PHY_MR0_RSVD_6_5 0x1 # Built-in Self-Test for RZQ # PSU_DDR_PHY_MR0_RZQI 0x2 - # Reserved. These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0. + # Reserved. These are JEDEC reserved bits and are recommended by JEDEC to + # be programmed to 0x0. # PSU_DDR_PHY_MR0_RSVD_2_0 0x0 # LPDDR4 Mode Register 0 - #(OFFSET, MASK, VALUE) (0XFD080180, 0xFFFFFFFFU ,0x00000830U) */ - mask_write 0XFD080180 0xFFFFFFFF 0x00000830 + #(OFFSET, MASK, VALUE) (0XFD080180, 0xFFFFFFFFU ,0x00000630U) */ + mask_write 0XFD080180 0xFFFFFFFF 0x00000630 # Register : MR1 @ 0XFD080184

# Reserved. Return zeroes on reads. @@ -4321,7 +5259,8 @@ set psu_ddr_init_data { # Pull-down Drive Strength # PSU_DDR_PHY_MR3_PDDS 0x0 - # These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0. + # These are JEDEC reserved bits and are recommended by JEDEC to be program + # med to 0x0. # PSU_DDR_PHY_MR3_RSVD 0x0 # Write Postamble Length @@ -4338,7 +5277,8 @@ set psu_ddr_init_data { # Reserved. Return zeroes on reads. # PSU_DDR_PHY_MR4_RESERVED_31_16 0x0 - # These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0. + # These are JEDEC reserved bits and are recommended by JEDEC to be program + # med to 0x0. # PSU_DDR_PHY_MR4_RSVD_15_13 0x0 # Write Preamble @@ -4356,7 +5296,8 @@ set psu_ddr_init_data { # CS to Command Latency Mode # PSU_DDR_PHY_MR4_CS2CMDL 0x0 - # These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0. + # These are JEDEC reserved bits and are recommended by JEDEC to be program + # med to 0x0. # PSU_DDR_PHY_MR4_RSVD1 0x0 # Internal VREF Monitor @@ -4371,7 +5312,8 @@ set psu_ddr_init_data { # Maximum Power Down Mode # PSU_DDR_PHY_MR4_MPDM 0x0 - # This is a JEDEC reserved bit and is recommended by JEDEC to be programmed to 0x0. + # This is a JEDEC reserved bit and is recommended by JEDEC to be programme + # d to 0x0. # PSU_DDR_PHY_MR4_RSVD_0 0x0 # DDR4 Mode Register 4 @@ -4382,7 +5324,8 @@ set psu_ddr_init_data { # Reserved. Return zeroes on reads. # PSU_DDR_PHY_MR5_RESERVED_31_16 0x0 - # These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0. + # These are JEDEC reserved bits and are recommended by JEDEC to be program + # med to 0x0. # PSU_DDR_PHY_MR5_RSVD 0x0 # Read DBI @@ -4420,13 +5363,15 @@ set psu_ddr_init_data { # Reserved. Return zeroes on reads. # PSU_DDR_PHY_MR6_RESERVED_31_16 0x0 - # These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0. + # These are JEDEC reserved bits and are recommended by JEDEC to be program + # med to 0x0. # PSU_DDR_PHY_MR6_RSVD_15_13 0x0 # CAS_n to CAS_n command delay for same bank group (tCCD_L) # PSU_DDR_PHY_MR6_TCCDL 0x2 - # These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0. + # These are JEDEC reserved bits and are recommended by JEDEC to be program + # med to 0x0. # PSU_DDR_PHY_MR6_RSVD_9_8 0x0 # VrefDQ Training Enable @@ -4446,7 +5391,8 @@ set psu_ddr_init_data { # Reserved. Return zeroes on reads. # PSU_DDR_PHY_MR11_RESERVED_31_8 0x0 - # These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0. + # These are JEDEC reserved bits and are recommended by JEDEC to be program + # med to 0x0. # PSU_DDR_PHY_MR11_RSVD 0x0 # Power Down Control @@ -4463,7 +5409,8 @@ set psu_ddr_init_data { # Reserved. Return zeroes on reads. # PSU_DDR_PHY_MR12_RESERVED_31_8 0x0 - # These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0. + # These are JEDEC reserved bits and are recommended by JEDEC to be program + # med to 0x0. # PSU_DDR_PHY_MR12_RSVD 0x0 # VREF_CA Range Select. @@ -4512,7 +5459,8 @@ set psu_ddr_init_data { # Reserved. Return zeroes on reads. # PSU_DDR_PHY_MR14_RESERVED_31_8 0x0 - # These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0. + # These are JEDEC reserved bits and are recommended by JEDEC to be program + # med to 0x0. # PSU_DDR_PHY_MR14_RSVD 0x0 # VREFDQ Range Selects. @@ -4529,7 +5477,8 @@ set psu_ddr_init_data { # Reserved. Return zeroes on reads. # PSU_DDR_PHY_MR22_RESERVED_31_8 0x0 - # These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0. + # These are JEDEC reserved bits and are recommended by JEDEC to be program + # med to 0x0. # PSU_DDR_PHY_MR22_RSVD 0x0 # CA ODT termination disable. @@ -4646,14 +5595,16 @@ set psu_ddr_init_data { # Reserved. Return zeroes on reads. # PSU_DDR_PHY_CATR0_RESERVED_31_21 0x0 - # Minimum time (in terms of number of dram clocks) between two consectuve CA calibration command + # Minimum time (in terms of number of dram clocks) between two consectuve + # CA calibration command # PSU_DDR_PHY_CATR0_CACD 0x14 # Reserved. Return zeroes on reads. # PSU_DDR_PHY_CATR0_RESERVED_15_13 0x0 - # Minimum time (in terms of number of dram clocks) PUB should wait before sampling the CA response after Calibration command ha - # been sent to the memory + # Minimum time (in terms of number of dram clocks) PUB should wait before + # sampling the CA response after Calibration command has been sent to the + # memory # PSU_DDR_PHY_CATR0_CAADR 0x10 # CA_1 Response Byte Lane 1 @@ -4665,6 +5616,48 @@ set psu_ddr_init_data { # CA Training Register 0 #(OFFSET, MASK, VALUE) (0XFD080240, 0xFFFFFFFFU ,0x00141054U) */ mask_write 0XFD080240 0xFFFFFFFF 0x00141054 + # Register : DQSDR0 @ 0XFD080250

+ + # Number of delay taps by which the DQS gate LCDL will be updated when DQS + # drift is detected + # PSU_DDR_PHY_DQSDR0_DFTDLY 0x0 + + # Drift Impedance Update + # PSU_DDR_PHY_DQSDR0_DFTZQUP 0x0 + + # Drift DDL Update + # PSU_DDR_PHY_DQSDR0_DFTDDLUP 0x0 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DQSDR0_RESERVED_25_22 0x0 + + # Drift Read Spacing + # PSU_DDR_PHY_DQSDR0_DFTRDSPC 0x0 + + # Drift Back-to-Back Reads + # PSU_DDR_PHY_DQSDR0_DFTB2BRD 0x8 + + # Drift Idle Reads + # PSU_DDR_PHY_DQSDR0_DFTIDLRD 0x8 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DQSDR0_RESERVED_11_8 0x0 + + # Gate Pulse Enable + # PSU_DDR_PHY_DQSDR0_DFTGPULSE 0x0 + + # DQS Drift Update Mode + # PSU_DDR_PHY_DQSDR0_DFTUPMODE 0x0 + + # DQS Drift Detection Mode + # PSU_DDR_PHY_DQSDR0_DFTDTMODE 0x0 + + # DQS Drift Detection Enable + # PSU_DDR_PHY_DQSDR0_DFTDTEN 0x0 + + # DQS Drift Register 0 + #(OFFSET, MASK, VALUE) (0XFD080250, 0xFFFFFFFFU ,0x00088000U) */ + mask_write 0XFD080250 0xFFFFFFFF 0x00088000 # Register : BISTLSR @ 0XFD080414

# LFSR seed for pseudo-random BIST patterns @@ -4727,7 +5720,8 @@ set psu_ddr_init_data { mask_write 0XFD080500 0xFFFFFFFF 0x30000028 # Register : ACIOCR2 @ 0XFD080508

- # Clock gating for glue logic inside CLKGEN and glue logic inside CONTROL slice + # Clock gating for glue logic inside CLKGEN and glue logic inside CONTROL + # slice # PSU_DDR_PHY_ACIOCR2_CLKGENCLKGATE 0x0 # Clock gating for Output Enable D slices [0] @@ -4842,14 +5836,15 @@ set psu_ddr_init_data { # PSU_DDR_PHY_IOVCR0_ACVREFISELRANGE 0x1 # REFSEL Control for internal AC IOs - # PSU_DDR_PHY_IOVCR0_ACVREFISEL 0x30 + # PSU_DDR_PHY_IOVCR0_ACVREFISEL 0x4e # IO VREF Control Register 0 - #(OFFSET, MASK, VALUE) (0XFD080520, 0xFFFFFFFFU ,0x0300B0B0U) */ - mask_write 0XFD080520 0xFFFFFFFF 0x0300B0B0 + #(OFFSET, MASK, VALUE) (0XFD080520, 0xFFFFFFFFU ,0x0300B0CEU) */ + mask_write 0XFD080520 0xFFFFFFFF 0x0300B0CE # Register : VTCR0 @ 0XFD080528

- # Number of ctl_clk required to meet (> 150ns) timing requirements during DRAM DQ VREF training + # Number of ctl_clk required to meet (> 150ns) timing requirements during + # DRAM DQ VREF training # PSU_DDR_PHY_VTCR0_TVREF 0x7 # DRM DQ VREF training Enable @@ -4881,7 +5876,8 @@ set psu_ddr_init_data { mask_write 0XFD080528 0xFFFFFFFF 0xF9032019 # Register : VTCR1 @ 0XFD08052C

- # Host VREF step size used during VREF training. The register value of N indicates step size of (N+1) + # Host VREF step size used during VREF training. The register value of N i + # ndicates step size of (N+1) # PSU_DDR_PHY_VTCR1_HVSS 0x0 # Reserved. Returns zeroes on reads. @@ -4905,7 +5901,8 @@ set psu_ddr_init_data { # Static Host Vref Rank Enable # PSU_DDR_PHY_VTCR1_SHREN 0x1 - # Number of ctl_clk required to meet (> 200ns) VREF Settling timing requirements during Host IO VREF training + # Number of ctl_clk required to meet (> 200ns) VREF Settling timing requir + # ements during Host IO VREF training # PSU_DDR_PHY_VTCR1_TVREFIO 0x7 # Eye LCDL Offset value for VREF training @@ -4934,13 +5931,15 @@ set psu_ddr_init_data { # Reserved. Return zeroes on reads. # PSU_DDR_PHY_ACBDLR1_RESERVED_23_22 0x0 - # Delay select for the BDL on Address A[16]. In DDR3 mode this pin is connected to WE. + # Delay select for the BDL on Address A[16]. In DDR3 mode this pin is conn + # ected to WE. # PSU_DDR_PHY_ACBDLR1_A16BD 0x0 # Reserved. Return zeroes on reads. # PSU_DDR_PHY_ACBDLR1_RESERVED_15_14 0x0 - # Delay select for the BDL on Address A[17]. When not in DDR4 modemode this pin is connected to CAS. + # Delay select for the BDL on Address A[17]. When not in DDR4 modemode thi + # s pin is connected to CAS. # PSU_DDR_PHY_ACBDLR1_A17BD 0x0 # Reserved. Return zeroes on reads. @@ -5109,7 +6108,7 @@ set psu_ddr_init_data { # PSU_DDR_PHY_ZQCR_PGWAIT_FRQB 0x11 # Programmable Wait for Frequency A - # PSU_DDR_PHY_ZQCR_PGWAIT_FRQA 0x11 + # PSU_DDR_PHY_ZQCR_PGWAIT_FRQA 0x15 # ZQ VREF Pad Enable # PSU_DDR_PHY_ZQCR_ZQREFPEN 0x0 @@ -5139,8 +6138,8 @@ set psu_ddr_init_data { # PSU_DDR_PHY_ZQCR_ZQPD 0x0 # ZQ Impedance Control Register - #(OFFSET, MASK, VALUE) (0XFD080680, 0xFFFFFFFFU ,0x008A2A58U) */ - mask_write 0XFD080680 0xFFFFFFFF 0x008A2A58 + #(OFFSET, MASK, VALUE) (0XFD080680, 0xFFFFFFFFU ,0x008AAA58U) */ + mask_write 0XFD080680 0xFFFFFFFF 0x008AAA58 # Register : ZQ0PR0 @ 0XFD080684

# Pull-down drive strength ZCTRL over-ride enable @@ -5158,7 +6157,8 @@ set psu_ddr_init_data { # Calibration segment bypass # PSU_DDR_PHY_ZQ0PR0_ZSEGBYP 0x0 - # VREF latch mode controls the mode in which the ZLE pin of the PVREF cell is driven by the PUB + # VREF latch mode controls the mode in which the ZLE pin of the PVREF cell + # is driven by the PUB # PSU_DDR_PHY_ZQ0PR0_ZLE_MODE 0x0 # Termination adjustment @@ -5174,17 +6174,19 @@ set psu_ddr_init_data { # PSU_DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT 0x7 # HOST Impedance Divide Ratio - # PSU_DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT 0x7 + # PSU_DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT 0x9 - # Impedance Divide Ratio (pulldown drive calibration during asymmetric drive strength calibration) + # Impedance Divide Ratio (pulldown drive calibration during asymmetric dri + # ve strength calibration) # PSU_DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD 0xd - # Impedance Divide Ratio (pullup drive calibration during asymmetric drive strength calibration) + # Impedance Divide Ratio (pullup drive calibration during asymmetric drive + # strength calibration) # PSU_DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU 0xd # ZQ n Impedance Control Program Register 0 - #(OFFSET, MASK, VALUE) (0XFD080684, 0xFFFFFFFFU ,0x000077DDU) */ - mask_write 0XFD080684 0xFFFFFFFF 0x000077DD + #(OFFSET, MASK, VALUE) (0XFD080684, 0xFFFFFFFFU ,0x000079DDU) */ + mask_write 0XFD080684 0xFFFFFFFF 0x000079DD # Register : ZQ0OR0 @ 0XFD080694

# Reserved. Return zeros on reads. @@ -5236,7 +6238,8 @@ set psu_ddr_init_data { # Calibration segment bypass # PSU_DDR_PHY_ZQ1PR0_ZSEGBYP 0x0 - # VREF latch mode controls the mode in which the ZLE pin of the PVREF cell is driven by the PUB + # VREF latch mode controls the mode in which the ZLE pin of the PVREF cell + # is driven by the PUB # PSU_DDR_PHY_ZQ1PR0_ZLE_MODE 0x0 # Termination adjustment @@ -5254,10 +6257,12 @@ set psu_ddr_init_data { # HOST Impedance Divide Ratio # PSU_DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT 0xb - # Impedance Divide Ratio (pulldown drive calibration during asymmetric drive strength calibration) + # Impedance Divide Ratio (pulldown drive calibration during asymmetric dri + # ve strength calibration) # PSU_DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD 0xd - # Impedance Divide Ratio (pullup drive calibration during asymmetric drive strength calibration) + # Impedance Divide Ratio (pullup drive calibration during asymmetric drive + # strength calibration) # PSU_DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU 0xb # ZQ n Impedance Control Program Register 0 @@ -5277,7 +6282,8 @@ set psu_ddr_init_data { # DQS Duty Cycle Correction # PSU_DDR_PHY_DX0GCR0_DQSDCC 0x0 - # Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY + # Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + # input for the respective bypte lane of the PHY # PSU_DDR_PHY_DX0GCR0_RDDLY 0x8 # Reserved. Return zeroes on reads. @@ -5378,17 +6384,17 @@ set psu_ddr_init_data { # PSU_DDR_PHY_DX0GCR5_RESERVED_15 0x0 # Byte Lane internal VREF Select for Rank 1 - # PSU_DDR_PHY_DX0GCR5_DXREFISELR1 0x4f + # PSU_DDR_PHY_DX0GCR5_DXREFISELR1 0x55 # Reserved. Returns zeros on reads. # PSU_DDR_PHY_DX0GCR5_RESERVED_7 0x0 # Byte Lane internal VREF Select for Rank 0 - # PSU_DDR_PHY_DX0GCR5_DXREFISELR0 0x4f + # PSU_DDR_PHY_DX0GCR5_DXREFISELR0 0x55 # DATX8 n General Configuration Register 5 - #(OFFSET, MASK, VALUE) (0XFD080714, 0xFFFFFFFFU ,0x09094F4FU) */ - mask_write 0XFD080714 0xFFFFFFFF 0x09094F4F + #(OFFSET, MASK, VALUE) (0XFD080714, 0xFFFFFFFFU ,0x09095555U) */ + mask_write 0XFD080714 0xFFFFFFFF 0x09095555 # Register : DX0GCR6 @ 0XFD080718

# Reserved. Returns zeros on reads. @@ -5418,52 +6424,6 @@ set psu_ddr_init_data { # DATX8 n General Configuration Register 6 #(OFFSET, MASK, VALUE) (0XFD080718, 0xFFFFFFFFU ,0x09092B2BU) */ mask_write 0XFD080718 0xFFFFFFFF 0x09092B2B - # Register : DX0LCDLR2 @ 0XFD080788

- - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX0LCDLR2_RESERVED_31_25 0x0 - - # Reserved. Caution, do not write to this register field. - # PSU_DDR_PHY_DX0LCDLR2_RESERVED_24_16 0x0 - - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX0LCDLR2_RESERVED_15_9 0x0 - - # Read DQS Gating Delay - # PSU_DDR_PHY_DX0LCDLR2_DQSGD 0x0 - - # DATX8 n Local Calibrated Delay Line Register 2 - #(OFFSET, MASK, VALUE) (0XFD080788, 0xFFFFFFFFU ,0x00000000U) */ - mask_write 0XFD080788 0xFFFFFFFF 0x00000000 - # Register : DX0GTR0 @ 0XFD0807C0

- - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX0GTR0_RESERVED_31_24 0x0 - - # DQ Write Path Latency Pipeline - # PSU_DDR_PHY_DX0GTR0_WDQSL 0x0 - - # Reserved. Caution, do not write to this register field. - # PSU_DDR_PHY_DX0GTR0_RESERVED_23_20 0x0 - - # Write Leveling System Latency - # PSU_DDR_PHY_DX0GTR0_WLSL 0x2 - - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX0GTR0_RESERVED_15_13 0x0 - - # Reserved. Caution, do not write to this register field. - # PSU_DDR_PHY_DX0GTR0_RESERVED_12_8 0x0 - - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX0GTR0_RESERVED_7_5 0x0 - - # DQS Gating System Latency - # PSU_DDR_PHY_DX0GTR0_DGSL 0x0 - - # DATX8 n General Timing Register 0 - #(OFFSET, MASK, VALUE) (0XFD0807C0, 0xFFFFFFFFU ,0x00020000U) */ - mask_write 0XFD0807C0 0xFFFFFFFF 0x00020000 # Register : DX1GCR0 @ 0XFD080800

# Calibration Bypass @@ -5478,7 +6438,8 @@ set psu_ddr_init_data { # DQS Duty Cycle Correction # PSU_DDR_PHY_DX1GCR0_DQSDCC 0x0 - # Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY + # Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + # input for the respective bypte lane of the PHY # PSU_DDR_PHY_DX1GCR0_RDDLY 0x8 # Reserved. Return zeroes on reads. @@ -5579,17 +6540,17 @@ set psu_ddr_init_data { # PSU_DDR_PHY_DX1GCR5_RESERVED_15 0x0 # Byte Lane internal VREF Select for Rank 1 - # PSU_DDR_PHY_DX1GCR5_DXREFISELR1 0x4f + # PSU_DDR_PHY_DX1GCR5_DXREFISELR1 0x55 # Reserved. Returns zeros on reads. # PSU_DDR_PHY_DX1GCR5_RESERVED_7 0x0 # Byte Lane internal VREF Select for Rank 0 - # PSU_DDR_PHY_DX1GCR5_DXREFISELR0 0x4f + # PSU_DDR_PHY_DX1GCR5_DXREFISELR0 0x55 # DATX8 n General Configuration Register 5 - #(OFFSET, MASK, VALUE) (0XFD080814, 0xFFFFFFFFU ,0x09094F4FU) */ - mask_write 0XFD080814 0xFFFFFFFF 0x09094F4F + #(OFFSET, MASK, VALUE) (0XFD080814, 0xFFFFFFFFU ,0x09095555U) */ + mask_write 0XFD080814 0xFFFFFFFF 0x09095555 # Register : DX1GCR6 @ 0XFD080818

# Reserved. Returns zeros on reads. @@ -5619,52 +6580,6 @@ set psu_ddr_init_data { # DATX8 n General Configuration Register 6 #(OFFSET, MASK, VALUE) (0XFD080818, 0xFFFFFFFFU ,0x09092B2BU) */ mask_write 0XFD080818 0xFFFFFFFF 0x09092B2B - # Register : DX1LCDLR2 @ 0XFD080888

- - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX1LCDLR2_RESERVED_31_25 0x0 - - # Reserved. Caution, do not write to this register field. - # PSU_DDR_PHY_DX1LCDLR2_RESERVED_24_16 0x0 - - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX1LCDLR2_RESERVED_15_9 0x0 - - # Read DQS Gating Delay - # PSU_DDR_PHY_DX1LCDLR2_DQSGD 0x0 - - # DATX8 n Local Calibrated Delay Line Register 2 - #(OFFSET, MASK, VALUE) (0XFD080888, 0xFFFFFFFFU ,0x00000000U) */ - mask_write 0XFD080888 0xFFFFFFFF 0x00000000 - # Register : DX1GTR0 @ 0XFD0808C0

- - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX1GTR0_RESERVED_31_24 0x0 - - # DQ Write Path Latency Pipeline - # PSU_DDR_PHY_DX1GTR0_WDQSL 0x0 - - # Reserved. Caution, do not write to this register field. - # PSU_DDR_PHY_DX1GTR0_RESERVED_23_20 0x0 - - # Write Leveling System Latency - # PSU_DDR_PHY_DX1GTR0_WLSL 0x2 - - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX1GTR0_RESERVED_15_13 0x0 - - # Reserved. Caution, do not write to this register field. - # PSU_DDR_PHY_DX1GTR0_RESERVED_12_8 0x0 - - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX1GTR0_RESERVED_7_5 0x0 - - # DQS Gating System Latency - # PSU_DDR_PHY_DX1GTR0_DGSL 0x0 - - # DATX8 n General Timing Register 0 - #(OFFSET, MASK, VALUE) (0XFD0808C0, 0xFFFFFFFFU ,0x00020000U) */ - mask_write 0XFD0808C0 0xFFFFFFFF 0x00020000 # Register : DX2GCR0 @ 0XFD080900

# Calibration Bypass @@ -5679,7 +6594,8 @@ set psu_ddr_init_data { # DQS Duty Cycle Correction # PSU_DDR_PHY_DX2GCR0_DQSDCC 0x0 - # Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY + # Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + # input for the respective bypte lane of the PHY # PSU_DDR_PHY_DX2GCR0_RDDLY 0x8 # Reserved. Return zeroes on reads. @@ -5815,17 +6731,17 @@ set psu_ddr_init_data { # PSU_DDR_PHY_DX2GCR5_RESERVED_15 0x0 # Byte Lane internal VREF Select for Rank 1 - # PSU_DDR_PHY_DX2GCR5_DXREFISELR1 0x4f + # PSU_DDR_PHY_DX2GCR5_DXREFISELR1 0x55 # Reserved. Returns zeros on reads. # PSU_DDR_PHY_DX2GCR5_RESERVED_7 0x0 # Byte Lane internal VREF Select for Rank 0 - # PSU_DDR_PHY_DX2GCR5_DXREFISELR0 0x4f + # PSU_DDR_PHY_DX2GCR5_DXREFISELR0 0x55 # DATX8 n General Configuration Register 5 - #(OFFSET, MASK, VALUE) (0XFD080914, 0xFFFFFFFFU ,0x09094F4FU) */ - mask_write 0XFD080914 0xFFFFFFFF 0x09094F4F + #(OFFSET, MASK, VALUE) (0XFD080914, 0xFFFFFFFFU ,0x09095555U) */ + mask_write 0XFD080914 0xFFFFFFFF 0x09095555 # Register : DX2GCR6 @ 0XFD080918

# Reserved. Returns zeros on reads. @@ -5855,52 +6771,6 @@ set psu_ddr_init_data { # DATX8 n General Configuration Register 6 #(OFFSET, MASK, VALUE) (0XFD080918, 0xFFFFFFFFU ,0x09092B2BU) */ mask_write 0XFD080918 0xFFFFFFFF 0x09092B2B - # Register : DX2LCDLR2 @ 0XFD080988

- - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX2LCDLR2_RESERVED_31_25 0x0 - - # Reserved. Caution, do not write to this register field. - # PSU_DDR_PHY_DX2LCDLR2_RESERVED_24_16 0x0 - - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX2LCDLR2_RESERVED_15_9 0x0 - - # Read DQS Gating Delay - # PSU_DDR_PHY_DX2LCDLR2_DQSGD 0x0 - - # DATX8 n Local Calibrated Delay Line Register 2 - #(OFFSET, MASK, VALUE) (0XFD080988, 0xFFFFFFFFU ,0x00000000U) */ - mask_write 0XFD080988 0xFFFFFFFF 0x00000000 - # Register : DX2GTR0 @ 0XFD0809C0

- - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX2GTR0_RESERVED_31_24 0x0 - - # DQ Write Path Latency Pipeline - # PSU_DDR_PHY_DX2GTR0_WDQSL 0x0 - - # Reserved. Caution, do not write to this register field. - # PSU_DDR_PHY_DX2GTR0_RESERVED_23_20 0x0 - - # Write Leveling System Latency - # PSU_DDR_PHY_DX2GTR0_WLSL 0x2 - - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX2GTR0_RESERVED_15_13 0x0 - - # Reserved. Caution, do not write to this register field. - # PSU_DDR_PHY_DX2GTR0_RESERVED_12_8 0x0 - - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX2GTR0_RESERVED_7_5 0x0 - - # DQS Gating System Latency - # PSU_DDR_PHY_DX2GTR0_DGSL 0x0 - - # DATX8 n General Timing Register 0 - #(OFFSET, MASK, VALUE) (0XFD0809C0, 0xFFFFFFFFU ,0x00020000U) */ - mask_write 0XFD0809C0 0xFFFFFFFF 0x00020000 # Register : DX3GCR0 @ 0XFD080A00

# Calibration Bypass @@ -5915,7 +6785,8 @@ set psu_ddr_init_data { # DQS Duty Cycle Correction # PSU_DDR_PHY_DX3GCR0_DQSDCC 0x0 - # Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY + # Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + # input for the respective bypte lane of the PHY # PSU_DDR_PHY_DX3GCR0_RDDLY 0x8 # Reserved. Return zeroes on reads. @@ -6051,17 +6922,17 @@ set psu_ddr_init_data { # PSU_DDR_PHY_DX3GCR5_RESERVED_15 0x0 # Byte Lane internal VREF Select for Rank 1 - # PSU_DDR_PHY_DX3GCR5_DXREFISELR1 0x4f + # PSU_DDR_PHY_DX3GCR5_DXREFISELR1 0x55 # Reserved. Returns zeros on reads. # PSU_DDR_PHY_DX3GCR5_RESERVED_7 0x0 # Byte Lane internal VREF Select for Rank 0 - # PSU_DDR_PHY_DX3GCR5_DXREFISELR0 0x4f + # PSU_DDR_PHY_DX3GCR5_DXREFISELR0 0x55 # DATX8 n General Configuration Register 5 - #(OFFSET, MASK, VALUE) (0XFD080A14, 0xFFFFFFFFU ,0x09094F4FU) */ - mask_write 0XFD080A14 0xFFFFFFFF 0x09094F4F + #(OFFSET, MASK, VALUE) (0XFD080A14, 0xFFFFFFFFU ,0x09095555U) */ + mask_write 0XFD080A14 0xFFFFFFFF 0x09095555 # Register : DX3GCR6 @ 0XFD080A18

# Reserved. Returns zeros on reads. @@ -6091,52 +6962,6 @@ set psu_ddr_init_data { # DATX8 n General Configuration Register 6 #(OFFSET, MASK, VALUE) (0XFD080A18, 0xFFFFFFFFU ,0x09092B2BU) */ mask_write 0XFD080A18 0xFFFFFFFF 0x09092B2B - # Register : DX3LCDLR2 @ 0XFD080A88

- - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX3LCDLR2_RESERVED_31_25 0x0 - - # Reserved. Caution, do not write to this register field. - # PSU_DDR_PHY_DX3LCDLR2_RESERVED_24_16 0x0 - - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX3LCDLR2_RESERVED_15_9 0x0 - - # Read DQS Gating Delay - # PSU_DDR_PHY_DX3LCDLR2_DQSGD 0x0 - - # DATX8 n Local Calibrated Delay Line Register 2 - #(OFFSET, MASK, VALUE) (0XFD080A88, 0xFFFFFFFFU ,0x00000000U) */ - mask_write 0XFD080A88 0xFFFFFFFF 0x00000000 - # Register : DX3GTR0 @ 0XFD080AC0

- - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX3GTR0_RESERVED_31_24 0x0 - - # DQ Write Path Latency Pipeline - # PSU_DDR_PHY_DX3GTR0_WDQSL 0x0 - - # Reserved. Caution, do not write to this register field. - # PSU_DDR_PHY_DX3GTR0_RESERVED_23_20 0x0 - - # Write Leveling System Latency - # PSU_DDR_PHY_DX3GTR0_WLSL 0x2 - - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX3GTR0_RESERVED_15_13 0x0 - - # Reserved. Caution, do not write to this register field. - # PSU_DDR_PHY_DX3GTR0_RESERVED_12_8 0x0 - - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX3GTR0_RESERVED_7_5 0x0 - - # DQS Gating System Latency - # PSU_DDR_PHY_DX3GTR0_DGSL 0x0 - - # DATX8 n General Timing Register 0 - #(OFFSET, MASK, VALUE) (0XFD080AC0, 0xFFFFFFFFU ,0x00020000U) */ - mask_write 0XFD080AC0 0xFFFFFFFF 0x00020000 # Register : DX4GCR0 @ 0XFD080B00

# Calibration Bypass @@ -6151,7 +6976,8 @@ set psu_ddr_init_data { # DQS Duty Cycle Correction # PSU_DDR_PHY_DX4GCR0_DQSDCC 0x0 - # Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY + # Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + # input for the respective bypte lane of the PHY # PSU_DDR_PHY_DX4GCR0_RDDLY 0x8 # Reserved. Return zeroes on reads. @@ -6287,17 +7113,17 @@ set psu_ddr_init_data { # PSU_DDR_PHY_DX4GCR5_RESERVED_15 0x0 # Byte Lane internal VREF Select for Rank 1 - # PSU_DDR_PHY_DX4GCR5_DXREFISELR1 0x4f + # PSU_DDR_PHY_DX4GCR5_DXREFISELR1 0x55 # Reserved. Returns zeros on reads. # PSU_DDR_PHY_DX4GCR5_RESERVED_7 0x0 # Byte Lane internal VREF Select for Rank 0 - # PSU_DDR_PHY_DX4GCR5_DXREFISELR0 0x4f + # PSU_DDR_PHY_DX4GCR5_DXREFISELR0 0x55 # DATX8 n General Configuration Register 5 - #(OFFSET, MASK, VALUE) (0XFD080B14, 0xFFFFFFFFU ,0x09094F4FU) */ - mask_write 0XFD080B14 0xFFFFFFFF 0x09094F4F + #(OFFSET, MASK, VALUE) (0XFD080B14, 0xFFFFFFFFU ,0x09095555U) */ + mask_write 0XFD080B14 0xFFFFFFFF 0x09095555 # Register : DX4GCR6 @ 0XFD080B18

# Reserved. Returns zeros on reads. @@ -6327,52 +7153,6 @@ set psu_ddr_init_data { # DATX8 n General Configuration Register 6 #(OFFSET, MASK, VALUE) (0XFD080B18, 0xFFFFFFFFU ,0x09092B2BU) */ mask_write 0XFD080B18 0xFFFFFFFF 0x09092B2B - # Register : DX4LCDLR2 @ 0XFD080B88

- - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX4LCDLR2_RESERVED_31_25 0x0 - - # Reserved. Caution, do not write to this register field. - # PSU_DDR_PHY_DX4LCDLR2_RESERVED_24_16 0x0 - - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX4LCDLR2_RESERVED_15_9 0x0 - - # Read DQS Gating Delay - # PSU_DDR_PHY_DX4LCDLR2_DQSGD 0x0 - - # DATX8 n Local Calibrated Delay Line Register 2 - #(OFFSET, MASK, VALUE) (0XFD080B88, 0xFFFFFFFFU ,0x00000000U) */ - mask_write 0XFD080B88 0xFFFFFFFF 0x00000000 - # Register : DX4GTR0 @ 0XFD080BC0

- - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX4GTR0_RESERVED_31_24 0x0 - - # DQ Write Path Latency Pipeline - # PSU_DDR_PHY_DX4GTR0_WDQSL 0x0 - - # Reserved. Caution, do not write to this register field. - # PSU_DDR_PHY_DX4GTR0_RESERVED_23_20 0x0 - - # Write Leveling System Latency - # PSU_DDR_PHY_DX4GTR0_WLSL 0x2 - - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX4GTR0_RESERVED_15_13 0x0 - - # Reserved. Caution, do not write to this register field. - # PSU_DDR_PHY_DX4GTR0_RESERVED_12_8 0x0 - - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX4GTR0_RESERVED_7_5 0x0 - - # DQS Gating System Latency - # PSU_DDR_PHY_DX4GTR0_DGSL 0x0 - - # DATX8 n General Timing Register 0 - #(OFFSET, MASK, VALUE) (0XFD080BC0, 0xFFFFFFFFU ,0x00020000U) */ - mask_write 0XFD080BC0 0xFFFFFFFF 0x00020000 # Register : DX5GCR0 @ 0XFD080C00

# Calibration Bypass @@ -6387,7 +7167,8 @@ set psu_ddr_init_data { # DQS Duty Cycle Correction # PSU_DDR_PHY_DX5GCR0_DQSDCC 0x0 - # Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY + # Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + # input for the respective bypte lane of the PHY # PSU_DDR_PHY_DX5GCR0_RDDLY 0x8 # Reserved. Return zeroes on reads. @@ -6523,17 +7304,17 @@ set psu_ddr_init_data { # PSU_DDR_PHY_DX5GCR5_RESERVED_15 0x0 # Byte Lane internal VREF Select for Rank 1 - # PSU_DDR_PHY_DX5GCR5_DXREFISELR1 0x4f + # PSU_DDR_PHY_DX5GCR5_DXREFISELR1 0x55 # Reserved. Returns zeros on reads. # PSU_DDR_PHY_DX5GCR5_RESERVED_7 0x0 # Byte Lane internal VREF Select for Rank 0 - # PSU_DDR_PHY_DX5GCR5_DXREFISELR0 0x4f + # PSU_DDR_PHY_DX5GCR5_DXREFISELR0 0x55 # DATX8 n General Configuration Register 5 - #(OFFSET, MASK, VALUE) (0XFD080C14, 0xFFFFFFFFU ,0x09094F4FU) */ - mask_write 0XFD080C14 0xFFFFFFFF 0x09094F4F + #(OFFSET, MASK, VALUE) (0XFD080C14, 0xFFFFFFFFU ,0x09095555U) */ + mask_write 0XFD080C14 0xFFFFFFFF 0x09095555 # Register : DX5GCR6 @ 0XFD080C18

# Reserved. Returns zeros on reads. @@ -6563,52 +7344,6 @@ set psu_ddr_init_data { # DATX8 n General Configuration Register 6 #(OFFSET, MASK, VALUE) (0XFD080C18, 0xFFFFFFFFU ,0x09092B2BU) */ mask_write 0XFD080C18 0xFFFFFFFF 0x09092B2B - # Register : DX5LCDLR2 @ 0XFD080C88

- - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX5LCDLR2_RESERVED_31_25 0x0 - - # Reserved. Caution, do not write to this register field. - # PSU_DDR_PHY_DX5LCDLR2_RESERVED_24_16 0x0 - - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX5LCDLR2_RESERVED_15_9 0x0 - - # Read DQS Gating Delay - # PSU_DDR_PHY_DX5LCDLR2_DQSGD 0x0 - - # DATX8 n Local Calibrated Delay Line Register 2 - #(OFFSET, MASK, VALUE) (0XFD080C88, 0xFFFFFFFFU ,0x00000000U) */ - mask_write 0XFD080C88 0xFFFFFFFF 0x00000000 - # Register : DX5GTR0 @ 0XFD080CC0

- - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX5GTR0_RESERVED_31_24 0x0 - - # DQ Write Path Latency Pipeline - # PSU_DDR_PHY_DX5GTR0_WDQSL 0x0 - - # Reserved. Caution, do not write to this register field. - # PSU_DDR_PHY_DX5GTR0_RESERVED_23_20 0x0 - - # Write Leveling System Latency - # PSU_DDR_PHY_DX5GTR0_WLSL 0x2 - - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX5GTR0_RESERVED_15_13 0x0 - - # Reserved. Caution, do not write to this register field. - # PSU_DDR_PHY_DX5GTR0_RESERVED_12_8 0x0 - - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX5GTR0_RESERVED_7_5 0x0 - - # DQS Gating System Latency - # PSU_DDR_PHY_DX5GTR0_DGSL 0x0 - - # DATX8 n General Timing Register 0 - #(OFFSET, MASK, VALUE) (0XFD080CC0, 0xFFFFFFFFU ,0x00020000U) */ - mask_write 0XFD080CC0 0xFFFFFFFF 0x00020000 # Register : DX6GCR0 @ 0XFD080D00

# Calibration Bypass @@ -6623,7 +7358,8 @@ set psu_ddr_init_data { # DQS Duty Cycle Correction # PSU_DDR_PHY_DX6GCR0_DQSDCC 0x0 - # Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY + # Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + # input for the respective bypte lane of the PHY # PSU_DDR_PHY_DX6GCR0_RDDLY 0x8 # Reserved. Return zeroes on reads. @@ -6759,17 +7495,17 @@ set psu_ddr_init_data { # PSU_DDR_PHY_DX6GCR5_RESERVED_15 0x0 # Byte Lane internal VREF Select for Rank 1 - # PSU_DDR_PHY_DX6GCR5_DXREFISELR1 0x4f + # PSU_DDR_PHY_DX6GCR5_DXREFISELR1 0x55 # Reserved. Returns zeros on reads. # PSU_DDR_PHY_DX6GCR5_RESERVED_7 0x0 # Byte Lane internal VREF Select for Rank 0 - # PSU_DDR_PHY_DX6GCR5_DXREFISELR0 0x4f + # PSU_DDR_PHY_DX6GCR5_DXREFISELR0 0x55 # DATX8 n General Configuration Register 5 - #(OFFSET, MASK, VALUE) (0XFD080D14, 0xFFFFFFFFU ,0x09094F4FU) */ - mask_write 0XFD080D14 0xFFFFFFFF 0x09094F4F + #(OFFSET, MASK, VALUE) (0XFD080D14, 0xFFFFFFFFU ,0x09095555U) */ + mask_write 0XFD080D14 0xFFFFFFFF 0x09095555 # Register : DX6GCR6 @ 0XFD080D18

# Reserved. Returns zeros on reads. @@ -6799,52 +7535,6 @@ set psu_ddr_init_data { # DATX8 n General Configuration Register 6 #(OFFSET, MASK, VALUE) (0XFD080D18, 0xFFFFFFFFU ,0x09092B2BU) */ mask_write 0XFD080D18 0xFFFFFFFF 0x09092B2B - # Register : DX6LCDLR2 @ 0XFD080D88

- - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX6LCDLR2_RESERVED_31_25 0x0 - - # Reserved. Caution, do not write to this register field. - # PSU_DDR_PHY_DX6LCDLR2_RESERVED_24_16 0x0 - - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX6LCDLR2_RESERVED_15_9 0x0 - - # Read DQS Gating Delay - # PSU_DDR_PHY_DX6LCDLR2_DQSGD 0x0 - - # DATX8 n Local Calibrated Delay Line Register 2 - #(OFFSET, MASK, VALUE) (0XFD080D88, 0xFFFFFFFFU ,0x00000000U) */ - mask_write 0XFD080D88 0xFFFFFFFF 0x00000000 - # Register : DX6GTR0 @ 0XFD080DC0

- - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX6GTR0_RESERVED_31_24 0x0 - - # DQ Write Path Latency Pipeline - # PSU_DDR_PHY_DX6GTR0_WDQSL 0x0 - - # Reserved. Caution, do not write to this register field. - # PSU_DDR_PHY_DX6GTR0_RESERVED_23_20 0x0 - - # Write Leveling System Latency - # PSU_DDR_PHY_DX6GTR0_WLSL 0x2 - - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX6GTR0_RESERVED_15_13 0x0 - - # Reserved. Caution, do not write to this register field. - # PSU_DDR_PHY_DX6GTR0_RESERVED_12_8 0x0 - - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX6GTR0_RESERVED_7_5 0x0 - - # DQS Gating System Latency - # PSU_DDR_PHY_DX6GTR0_DGSL 0x0 - - # DATX8 n General Timing Register 0 - #(OFFSET, MASK, VALUE) (0XFD080DC0, 0xFFFFFFFFU ,0x00020000U) */ - mask_write 0XFD080DC0 0xFFFFFFFF 0x00020000 # Register : DX7GCR0 @ 0XFD080E00

# Calibration Bypass @@ -6859,7 +7549,8 @@ set psu_ddr_init_data { # DQS Duty Cycle Correction # PSU_DDR_PHY_DX7GCR0_DQSDCC 0x0 - # Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY + # Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + # input for the respective bypte lane of the PHY # PSU_DDR_PHY_DX7GCR0_RDDLY 0x8 # Reserved. Return zeroes on reads. @@ -6995,17 +7686,17 @@ set psu_ddr_init_data { # PSU_DDR_PHY_DX7GCR5_RESERVED_15 0x0 # Byte Lane internal VREF Select for Rank 1 - # PSU_DDR_PHY_DX7GCR5_DXREFISELR1 0x4f + # PSU_DDR_PHY_DX7GCR5_DXREFISELR1 0x55 # Reserved. Returns zeros on reads. # PSU_DDR_PHY_DX7GCR5_RESERVED_7 0x0 # Byte Lane internal VREF Select for Rank 0 - # PSU_DDR_PHY_DX7GCR5_DXREFISELR0 0x4f + # PSU_DDR_PHY_DX7GCR5_DXREFISELR0 0x55 # DATX8 n General Configuration Register 5 - #(OFFSET, MASK, VALUE) (0XFD080E14, 0xFFFFFFFFU ,0x09094F4FU) */ - mask_write 0XFD080E14 0xFFFFFFFF 0x09094F4F + #(OFFSET, MASK, VALUE) (0XFD080E14, 0xFFFFFFFFU ,0x09095555U) */ + mask_write 0XFD080E14 0xFFFFFFFF 0x09095555 # Register : DX7GCR6 @ 0XFD080E18

# Reserved. Returns zeros on reads. @@ -7035,52 +7726,6 @@ set psu_ddr_init_data { # DATX8 n General Configuration Register 6 #(OFFSET, MASK, VALUE) (0XFD080E18, 0xFFFFFFFFU ,0x09092B2BU) */ mask_write 0XFD080E18 0xFFFFFFFF 0x09092B2B - # Register : DX7LCDLR2 @ 0XFD080E88

- - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX7LCDLR2_RESERVED_31_25 0x0 - - # Reserved. Caution, do not write to this register field. - # PSU_DDR_PHY_DX7LCDLR2_RESERVED_24_16 0x0 - - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX7LCDLR2_RESERVED_15_9 0x0 - - # Read DQS Gating Delay - # PSU_DDR_PHY_DX7LCDLR2_DQSGD 0xa - - # DATX8 n Local Calibrated Delay Line Register 2 - #(OFFSET, MASK, VALUE) (0XFD080E88, 0xFFFFFFFFU ,0x0000000AU) */ - mask_write 0XFD080E88 0xFFFFFFFF 0x0000000A - # Register : DX7GTR0 @ 0XFD080EC0

- - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX7GTR0_RESERVED_31_24 0x0 - - # DQ Write Path Latency Pipeline - # PSU_DDR_PHY_DX7GTR0_WDQSL 0x0 - - # Reserved. Caution, do not write to this register field. - # PSU_DDR_PHY_DX7GTR0_RESERVED_23_20 0x0 - - # Write Leveling System Latency - # PSU_DDR_PHY_DX7GTR0_WLSL 0x2 - - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX7GTR0_RESERVED_15_13 0x0 - - # Reserved. Caution, do not write to this register field. - # PSU_DDR_PHY_DX7GTR0_RESERVED_12_8 0x0 - - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX7GTR0_RESERVED_7_5 0x0 - - # DQS Gating System Latency - # PSU_DDR_PHY_DX7GTR0_DGSL 0x0 - - # DATX8 n General Timing Register 0 - #(OFFSET, MASK, VALUE) (0XFD080EC0, 0xFFFFFFFFU ,0x00020000U) */ - mask_write 0XFD080EC0 0xFFFFFFFF 0x00020000 # Register : DX8GCR0 @ 0XFD080F00

# Calibration Bypass @@ -7095,7 +7740,8 @@ set psu_ddr_init_data { # DQS Duty Cycle Correction # PSU_DDR_PHY_DX8GCR0_DQSDCC 0x0 - # Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY + # Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + # input for the respective bypte lane of the PHY # PSU_DDR_PHY_DX8GCR0_RDDLY 0x8 # Reserved. Return zeroes on reads. @@ -7231,17 +7877,17 @@ set psu_ddr_init_data { # PSU_DDR_PHY_DX8GCR5_RESERVED_15 0x0 # Byte Lane internal VREF Select for Rank 1 - # PSU_DDR_PHY_DX8GCR5_DXREFISELR1 0x4f + # PSU_DDR_PHY_DX8GCR5_DXREFISELR1 0x55 # Reserved. Returns zeros on reads. # PSU_DDR_PHY_DX8GCR5_RESERVED_7 0x0 # Byte Lane internal VREF Select for Rank 0 - # PSU_DDR_PHY_DX8GCR5_DXREFISELR0 0x4f + # PSU_DDR_PHY_DX8GCR5_DXREFISELR0 0x55 # DATX8 n General Configuration Register 5 - #(OFFSET, MASK, VALUE) (0XFD080F14, 0xFFFFFFFFU ,0x09094F4FU) */ - mask_write 0XFD080F14 0xFFFFFFFF 0x09094F4F + #(OFFSET, MASK, VALUE) (0XFD080F14, 0xFFFFFFFFU ,0x09095555U) */ + mask_write 0XFD080F14 0xFFFFFFFF 0x09095555 # Register : DX8GCR6 @ 0XFD080F18

# Reserved. Returns zeros on reads. @@ -7271,52 +7917,6 @@ set psu_ddr_init_data { # DATX8 n General Configuration Register 6 #(OFFSET, MASK, VALUE) (0XFD080F18, 0xFFFFFFFFU ,0x09092B2BU) */ mask_write 0XFD080F18 0xFFFFFFFF 0x09092B2B - # Register : DX8LCDLR2 @ 0XFD080F88

- - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX8LCDLR2_RESERVED_31_25 0x0 - - # Reserved. Caution, do not write to this register field. - # PSU_DDR_PHY_DX8LCDLR2_RESERVED_24_16 0x0 - - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX8LCDLR2_RESERVED_15_9 0x0 - - # Read DQS Gating Delay - # PSU_DDR_PHY_DX8LCDLR2_DQSGD 0x0 - - # DATX8 n Local Calibrated Delay Line Register 2 - #(OFFSET, MASK, VALUE) (0XFD080F88, 0xFFFFFFFFU ,0x00000000U) */ - mask_write 0XFD080F88 0xFFFFFFFF 0x00000000 - # Register : DX8GTR0 @ 0XFD080FC0

- - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX8GTR0_RESERVED_31_24 0x0 - - # DQ Write Path Latency Pipeline - # PSU_DDR_PHY_DX8GTR0_WDQSL 0x0 - - # Reserved. Caution, do not write to this register field. - # PSU_DDR_PHY_DX8GTR0_RESERVED_23_20 0x0 - - # Write Leveling System Latency - # PSU_DDR_PHY_DX8GTR0_WLSL 0x2 - - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX8GTR0_RESERVED_15_13 0x0 - - # Reserved. Caution, do not write to this register field. - # PSU_DDR_PHY_DX8GTR0_RESERVED_12_8 0x0 - - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_DX8GTR0_RESERVED_7_5 0x0 - - # DQS Gating System Latency - # PSU_DDR_PHY_DX8GTR0_DGSL 0x0 - - # DATX8 n General Timing Register 0 - #(OFFSET, MASK, VALUE) (0XFD080FC0, 0xFFFFFFFFU ,0x00020000U) */ - mask_write 0XFD080FC0 0xFFFFFFFF 0x00020000 # Register : DX8SL0OSC @ 0XFD081400

# Reserved. Return zeroes on reads. @@ -7331,7 +7931,8 @@ set psu_ddr_init_data { # Enable Clock Gating for DX ctl_clk # PSU_DDR_PHY_DX8SL0OSC_GATEDXCTLCLK 0x2 - # Selects the level to which clocks will be stalled when clock gating is enabled. + # Selects the level to which clocks will be stalled when clock gating is e + # nabled. # PSU_DDR_PHY_DX8SL0OSC_CLKLEVEL 0x0 # Loopback Mode @@ -7376,9 +7977,54 @@ set psu_ddr_init_data { # Oscillator Enable # PSU_DDR_PHY_DX8SL0OSC_OSCEN 0x0 - # DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register + # DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Lo + # opback, and Gated Clock Control Register #(OFFSET, MASK, VALUE) (0XFD081400, 0xFFFFFFFFU ,0x2A019FFEU) */ mask_write 0XFD081400 0xFFFFFFFF 0x2A019FFE + # Register : DX8SL0PLLCR0 @ 0XFD081404

+ + # PLL Bypass + # PSU_DDR_PHY_DX8SL0PLLCR0_PLLBYP 0x0 + + # PLL Reset + # PSU_DDR_PHY_DX8SL0PLLCR0_PLLRST 0x0 + + # PLL Power Down + # PSU_DDR_PHY_DX8SL0PLLCR0_PLLPD 0x0 + + # Reference Stop Mode + # PSU_DDR_PHY_DX8SL0PLLCR0_RSTOPM 0x0 + + # PLL Frequency Select + # PSU_DDR_PHY_DX8SL0PLLCR0_FRQSEL 0x1 + + # Relock Mode + # PSU_DDR_PHY_DX8SL0PLLCR0_RLOCKM 0x0 + + # Charge Pump Proportional Current Control + # PSU_DDR_PHY_DX8SL0PLLCR0_CPPC 0x8 + + # Charge Pump Integrating Current Control + # PSU_DDR_PHY_DX8SL0PLLCR0_CPIC 0x0 + + # Gear Shift + # PSU_DDR_PHY_DX8SL0PLLCR0_GSHIFT 0x0 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX8SL0PLLCR0_RESERVED_11_9 0x0 + + # Analog Test Enable (ATOEN) + # PSU_DDR_PHY_DX8SL0PLLCR0_ATOEN 0x0 + + # Analog Test Control + # PSU_DDR_PHY_DX8SL0PLLCR0_ATC 0x0 + + # Digital Test Control + # PSU_DDR_PHY_DX8SL0PLLCR0_DTC 0x0 + + # DAXT8 0-1 PLL Control Register 0 + #(OFFSET, MASK, VALUE) (0XFD081404, 0xFFFFFFFFU ,0x01100000U) */ + mask_write 0XFD081404 0xFFFFFFFF 0x01100000 # Register : DX8SL0DQSCTL @ 0XFD08141C

# Reserved. Return zeroes on reads. @@ -7516,7 +8162,8 @@ set psu_ddr_init_data { # Enable Clock Gating for DX ctl_clk # PSU_DDR_PHY_DX8SL1OSC_GATEDXCTLCLK 0x2 - # Selects the level to which clocks will be stalled when clock gating is enabled. + # Selects the level to which clocks will be stalled when clock gating is e + # nabled. # PSU_DDR_PHY_DX8SL1OSC_CLKLEVEL 0x0 # Loopback Mode @@ -7561,9 +8208,54 @@ set psu_ddr_init_data { # Oscillator Enable # PSU_DDR_PHY_DX8SL1OSC_OSCEN 0x0 - # DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register + # DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Lo + # opback, and Gated Clock Control Register #(OFFSET, MASK, VALUE) (0XFD081440, 0xFFFFFFFFU ,0x2A019FFEU) */ mask_write 0XFD081440 0xFFFFFFFF 0x2A019FFE + # Register : DX8SL1PLLCR0 @ 0XFD081444

+ + # PLL Bypass + # PSU_DDR_PHY_DX8SL1PLLCR0_PLLBYP 0x0 + + # PLL Reset + # PSU_DDR_PHY_DX8SL1PLLCR0_PLLRST 0x0 + + # PLL Power Down + # PSU_DDR_PHY_DX8SL1PLLCR0_PLLPD 0x0 + + # Reference Stop Mode + # PSU_DDR_PHY_DX8SL1PLLCR0_RSTOPM 0x0 + + # PLL Frequency Select + # PSU_DDR_PHY_DX8SL1PLLCR0_FRQSEL 0x1 + + # Relock Mode + # PSU_DDR_PHY_DX8SL1PLLCR0_RLOCKM 0x0 + + # Charge Pump Proportional Current Control + # PSU_DDR_PHY_DX8SL1PLLCR0_CPPC 0x8 + + # Charge Pump Integrating Current Control + # PSU_DDR_PHY_DX8SL1PLLCR0_CPIC 0x0 + + # Gear Shift + # PSU_DDR_PHY_DX8SL1PLLCR0_GSHIFT 0x0 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX8SL1PLLCR0_RESERVED_11_9 0x0 + + # Analog Test Enable (ATOEN) + # PSU_DDR_PHY_DX8SL1PLLCR0_ATOEN 0x0 + + # Analog Test Control + # PSU_DDR_PHY_DX8SL1PLLCR0_ATC 0x0 + + # Digital Test Control + # PSU_DDR_PHY_DX8SL1PLLCR0_DTC 0x0 + + # DAXT8 0-1 PLL Control Register 0 + #(OFFSET, MASK, VALUE) (0XFD081444, 0xFFFFFFFFU ,0x01100000U) */ + mask_write 0XFD081444 0xFFFFFFFF 0x01100000 # Register : DX8SL1DQSCTL @ 0XFD08145C

# Reserved. Return zeroes on reads. @@ -7701,7 +8393,8 @@ set psu_ddr_init_data { # Enable Clock Gating for DX ctl_clk # PSU_DDR_PHY_DX8SL2OSC_GATEDXCTLCLK 0x2 - # Selects the level to which clocks will be stalled when clock gating is enabled. + # Selects the level to which clocks will be stalled when clock gating is e + # nabled. # PSU_DDR_PHY_DX8SL2OSC_CLKLEVEL 0x0 # Loopback Mode @@ -7746,9 +8439,54 @@ set psu_ddr_init_data { # Oscillator Enable # PSU_DDR_PHY_DX8SL2OSC_OSCEN 0x0 - # DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register + # DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Lo + # opback, and Gated Clock Control Register #(OFFSET, MASK, VALUE) (0XFD081480, 0xFFFFFFFFU ,0x2A019FFEU) */ mask_write 0XFD081480 0xFFFFFFFF 0x2A019FFE + # Register : DX8SL2PLLCR0 @ 0XFD081484

+ + # PLL Bypass + # PSU_DDR_PHY_DX8SL2PLLCR0_PLLBYP 0x0 + + # PLL Reset + # PSU_DDR_PHY_DX8SL2PLLCR0_PLLRST 0x0 + + # PLL Power Down + # PSU_DDR_PHY_DX8SL2PLLCR0_PLLPD 0x0 + + # Reference Stop Mode + # PSU_DDR_PHY_DX8SL2PLLCR0_RSTOPM 0x0 + + # PLL Frequency Select + # PSU_DDR_PHY_DX8SL2PLLCR0_FRQSEL 0x1 + + # Relock Mode + # PSU_DDR_PHY_DX8SL2PLLCR0_RLOCKM 0x0 + + # Charge Pump Proportional Current Control + # PSU_DDR_PHY_DX8SL2PLLCR0_CPPC 0x8 + + # Charge Pump Integrating Current Control + # PSU_DDR_PHY_DX8SL2PLLCR0_CPIC 0x0 + + # Gear Shift + # PSU_DDR_PHY_DX8SL2PLLCR0_GSHIFT 0x0 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX8SL2PLLCR0_RESERVED_11_9 0x0 + + # Analog Test Enable (ATOEN) + # PSU_DDR_PHY_DX8SL2PLLCR0_ATOEN 0x0 + + # Analog Test Control + # PSU_DDR_PHY_DX8SL2PLLCR0_ATC 0x0 + + # Digital Test Control + # PSU_DDR_PHY_DX8SL2PLLCR0_DTC 0x0 + + # DAXT8 0-1 PLL Control Register 0 + #(OFFSET, MASK, VALUE) (0XFD081484, 0xFFFFFFFFU ,0x01100000U) */ + mask_write 0XFD081484 0xFFFFFFFF 0x01100000 # Register : DX8SL2DQSCTL @ 0XFD08149C

# Reserved. Return zeroes on reads. @@ -7886,7 +8624,8 @@ set psu_ddr_init_data { # Enable Clock Gating for DX ctl_clk # PSU_DDR_PHY_DX8SL3OSC_GATEDXCTLCLK 0x2 - # Selects the level to which clocks will be stalled when clock gating is enabled. + # Selects the level to which clocks will be stalled when clock gating is e + # nabled. # PSU_DDR_PHY_DX8SL3OSC_CLKLEVEL 0x0 # Loopback Mode @@ -7931,9 +8670,54 @@ set psu_ddr_init_data { # Oscillator Enable # PSU_DDR_PHY_DX8SL3OSC_OSCEN 0x0 - # DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register + # DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Lo + # opback, and Gated Clock Control Register #(OFFSET, MASK, VALUE) (0XFD0814C0, 0xFFFFFFFFU ,0x2A019FFEU) */ mask_write 0XFD0814C0 0xFFFFFFFF 0x2A019FFE + # Register : DX8SL3PLLCR0 @ 0XFD0814C4

+ + # PLL Bypass + # PSU_DDR_PHY_DX8SL3PLLCR0_PLLBYP 0x0 + + # PLL Reset + # PSU_DDR_PHY_DX8SL3PLLCR0_PLLRST 0x0 + + # PLL Power Down + # PSU_DDR_PHY_DX8SL3PLLCR0_PLLPD 0x0 + + # Reference Stop Mode + # PSU_DDR_PHY_DX8SL3PLLCR0_RSTOPM 0x0 + + # PLL Frequency Select + # PSU_DDR_PHY_DX8SL3PLLCR0_FRQSEL 0x1 + + # Relock Mode + # PSU_DDR_PHY_DX8SL3PLLCR0_RLOCKM 0x0 + + # Charge Pump Proportional Current Control + # PSU_DDR_PHY_DX8SL3PLLCR0_CPPC 0x8 + + # Charge Pump Integrating Current Control + # PSU_DDR_PHY_DX8SL3PLLCR0_CPIC 0x0 + + # Gear Shift + # PSU_DDR_PHY_DX8SL3PLLCR0_GSHIFT 0x0 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX8SL3PLLCR0_RESERVED_11_9 0x0 + + # Analog Test Enable (ATOEN) + # PSU_DDR_PHY_DX8SL3PLLCR0_ATOEN 0x0 + + # Analog Test Control + # PSU_DDR_PHY_DX8SL3PLLCR0_ATC 0x0 + + # Digital Test Control + # PSU_DDR_PHY_DX8SL3PLLCR0_DTC 0x0 + + # DAXT8 0-1 PLL Control Register 0 + #(OFFSET, MASK, VALUE) (0XFD0814C4, 0xFFFFFFFFU ,0x01100000U) */ + mask_write 0XFD0814C4 0xFFFFFFFF 0x01100000 # Register : DX8SL3DQSCTL @ 0XFD0814DC

# Reserved. Return zeroes on reads. @@ -8071,7 +8855,8 @@ set psu_ddr_init_data { # Enable Clock Gating for DX ctl_clk # PSU_DDR_PHY_DX8SL4OSC_GATEDXCTLCLK 0x2 - # Selects the level to which clocks will be stalled when clock gating is enabled. + # Selects the level to which clocks will be stalled when clock gating is e + # nabled. # PSU_DDR_PHY_DX8SL4OSC_CLKLEVEL 0x0 # Loopback Mode @@ -8116,9 +8901,54 @@ set psu_ddr_init_data { # Oscillator Enable # PSU_DDR_PHY_DX8SL4OSC_OSCEN 0x0 - # DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register + # DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Lo + # opback, and Gated Clock Control Register #(OFFSET, MASK, VALUE) (0XFD081500, 0xFFFFFFFFU ,0x2A019FFEU) */ mask_write 0XFD081500 0xFFFFFFFF 0x2A019FFE + # Register : DX8SL4PLLCR0 @ 0XFD081504

+ + # PLL Bypass + # PSU_DDR_PHY_DX8SL4PLLCR0_PLLBYP 0x0 + + # PLL Reset + # PSU_DDR_PHY_DX8SL4PLLCR0_PLLRST 0x0 + + # PLL Power Down + # PSU_DDR_PHY_DX8SL4PLLCR0_PLLPD 0x0 + + # Reference Stop Mode + # PSU_DDR_PHY_DX8SL4PLLCR0_RSTOPM 0x0 + + # PLL Frequency Select + # PSU_DDR_PHY_DX8SL4PLLCR0_FRQSEL 0x1 + + # Relock Mode + # PSU_DDR_PHY_DX8SL4PLLCR0_RLOCKM 0x0 + + # Charge Pump Proportional Current Control + # PSU_DDR_PHY_DX8SL4PLLCR0_CPPC 0x8 + + # Charge Pump Integrating Current Control + # PSU_DDR_PHY_DX8SL4PLLCR0_CPIC 0x0 + + # Gear Shift + # PSU_DDR_PHY_DX8SL4PLLCR0_GSHIFT 0x0 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX8SL4PLLCR0_RESERVED_11_9 0x0 + + # Analog Test Enable (ATOEN) + # PSU_DDR_PHY_DX8SL4PLLCR0_ATOEN 0x0 + + # Analog Test Control + # PSU_DDR_PHY_DX8SL4PLLCR0_ATC 0x0 + + # Digital Test Control + # PSU_DDR_PHY_DX8SL4PLLCR0_DTC 0x0 + + # DAXT8 0-1 PLL Control Register 0 + #(OFFSET, MASK, VALUE) (0XFD081504, 0xFFFFFFFFU ,0x01100000U) */ + mask_write 0XFD081504 0xFFFFFFFF 0x01100000 # Register : DX8SL4DQSCTL @ 0XFD08151C

# Reserved. Return zeroes on reads. @@ -8242,6 +9072,50 @@ set psu_ddr_init_data { # DATX8 0-1 I/O Configuration Register #(OFFSET, MASK, VALUE) (0XFD081530, 0xFFFFFFFFU ,0x70800000U) */ mask_write 0XFD081530 0xFFFFFFFF 0x70800000 + # Register : DX8SLbPLLCR0 @ 0XFD0817C4

+ + # PLL Bypass + # PSU_DDR_PHY_DX8SLBPLLCR0_PLLBYP 0x0 + + # PLL Reset + # PSU_DDR_PHY_DX8SLBPLLCR0_PLLRST 0x0 + + # PLL Power Down + # PSU_DDR_PHY_DX8SLBPLLCR0_PLLPD 0x0 + + # Reference Stop Mode + # PSU_DDR_PHY_DX8SLBPLLCR0_RSTOPM 0x0 + + # PLL Frequency Select + # PSU_DDR_PHY_DX8SLBPLLCR0_FRQSEL 0x1 + + # Relock Mode + # PSU_DDR_PHY_DX8SLBPLLCR0_RLOCKM 0x0 + + # Charge Pump Proportional Current Control + # PSU_DDR_PHY_DX8SLBPLLCR0_CPPC 0x8 + + # Charge Pump Integrating Current Control + # PSU_DDR_PHY_DX8SLBPLLCR0_CPIC 0x0 + + # Gear Shift + # PSU_DDR_PHY_DX8SLBPLLCR0_GSHIFT 0x0 + + # Reserved. Return zeroes on reads. + # PSU_DDR_PHY_DX8SLBPLLCR0_RESERVED_11_9 0x0 + + # Analog Test Enable (ATOEN) + # PSU_DDR_PHY_DX8SLBPLLCR0_ATOEN 0x0 + + # Analog Test Control + # PSU_DDR_PHY_DX8SLBPLLCR0_ATC 0x0 + + # Digital Test Control + # PSU_DDR_PHY_DX8SLBPLLCR0_DTC 0x0 + + # DAXT8 0-8 PLL Control Register 0 + #(OFFSET, MASK, VALUE) (0XFD0817C4, 0xFFFFFFFFU ,0x01100000U) */ + mask_write 0XFD0817C4 0xFFFFFFFF 0x01100000 # Register : DX8SLbDQSCTL @ 0XFD0817DC

# Reserved. Return zeroes on reads. @@ -8289,107 +9163,35 @@ set psu_ddr_init_data { # DATX8 0-8 DQS Control Register #(OFFSET, MASK, VALUE) (0XFD0817DC, 0xFFFFFFFFU ,0x012643C4U) */ mask_write 0XFD0817DC 0xFFFFFFFF 0x012643C4 - # Register : PIR @ 0XFD080004

+} - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_PIR_RESERVED_31 0x0 - - # Impedance Calibration Bypass - # PSU_DDR_PHY_PIR_ZCALBYP 0x0 - - # Digital Delay Line (DDL) Calibration Pause - # PSU_DDR_PHY_PIR_DCALPSE 0x0 - - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_PIR_RESERVED_28_21 0x0 - - # Write DQS2DQ Training - # PSU_DDR_PHY_PIR_DQS2DQ 0x0 - - # RDIMM Initialization - # PSU_DDR_PHY_PIR_RDIMMINIT 0x0 - - # Controller DRAM Initialization - # PSU_DDR_PHY_PIR_CTLDINIT 0x1 - - # VREF Training - # PSU_DDR_PHY_PIR_VREF 0x0 - - # Static Read Training - # PSU_DDR_PHY_PIR_SRD 0x0 - - # Write Data Eye Training - # PSU_DDR_PHY_PIR_WREYE 0x0 - - # Read Data Eye Training - # PSU_DDR_PHY_PIR_RDEYE 0x0 - - # Write Data Bit Deskew - # PSU_DDR_PHY_PIR_WRDSKW 0x0 - - # Read Data Bit Deskew - # PSU_DDR_PHY_PIR_RDDSKW 0x0 - - # Write Leveling Adjust - # PSU_DDR_PHY_PIR_WLADJ 0x0 - - # Read DQS Gate Training - # PSU_DDR_PHY_PIR_QSGATE 0x0 - - # Write Leveling - # PSU_DDR_PHY_PIR_WL 0x0 - - # DRAM Initialization - # PSU_DDR_PHY_PIR_DRAMINIT 0x0 - - # DRAM Reset (DDR3/DDR4/LPDDR4 Only) - # PSU_DDR_PHY_PIR_DRAMRST 0x0 - - # PHY Reset - # PSU_DDR_PHY_PIR_PHYRST 0x1 - - # Digital Delay Line (DDL) Calibration - # PSU_DDR_PHY_PIR_DCAL 0x1 - - # PLL Initialiazation - # PSU_DDR_PHY_PIR_PLLINIT 0x1 - - # Reserved. Return zeroes on reads. - # PSU_DDR_PHY_PIR_RESERVED_3 0x0 - - # CA Training - # PSU_DDR_PHY_PIR_CA 0x0 - - # Impedance Calibration - # PSU_DDR_PHY_PIR_ZCAL 0x1 - - # Initialization Trigger - # PSU_DDR_PHY_PIR_INIT 0x1 - - # PHY Initialization Register - #(OFFSET, MASK, VALUE) (0XFD080004, 0xFFFFFFFFU ,0x00040073U) */ - mask_write 0XFD080004 0xFFFFFFFF 0x00040073 +set psu_ddr_qos_init_data { } set psu_mio_init_data { # : MIO PROGRAMMING # Register : MIO_PIN_0 @ 0XFF180000

- # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out- (QSPI Clock) + # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out- + # (QSPI Clock) # PSU_IOU_SLCR_MIO_PIN_0_L0_SEL 1 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used # PSU_IOU_SLCR_MIO_PIN_0_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[0]- (Test Scan Port) = test_scan, Outp - # t, test_scan_out[0]- (Test Scan Port) 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + # , test_scan_in[0]- (Test Scan Port) = test_scan, Output, test_scan_out[0 + # ]- (Test Scan Port) 3= Not Used # PSU_IOU_SLCR_MIO_PIN_0_L2_SEL 0 - # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[0]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[0]- (GPIO bank 0) 1= can - # , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa - # ) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Cloc - # ) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_ - # lk- (Trace Port Clock) + # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[0]- (GPIO bank 0) 0= g + # pio0, Output, gpio_0_pin_out[0]- (GPIO bank 0) 1= can1, Output, can1_phy + # _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + # 1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG + # TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sc + # lk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Out + # put, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_c + # lk- (Trace Port Clock) # PSU_IOU_SLCR_MIO_PIN_0_L3_SEL 0 # Configures MIO Pin 0 peripheral interface mapping. S @@ -8397,22 +9199,26 @@ set psu_mio_init_data { mask_write 0XFF180000 0x000000FE 0x00000002 # Register : MIO_PIN_1 @ 0XFF180004

- # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (QSPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Data - # us) + # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (Q + # SPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Databus) # PSU_IOU_SLCR_MIO_PIN_1_L0_SEL 1 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used # PSU_IOU_SLCR_MIO_PIN_1_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[1]- (Test Scan Port) = test_scan, Outp - # t, test_scan_out[1]- (Test Scan Port) 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + # , test_scan_in[1]- (Test Scan Port) = test_scan, Output, test_scan_out[1 + # ]- (Test Scan Port) 3= Not Used # PSU_IOU_SLCR_MIO_PIN_1_L2_SEL 0 - # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[1]- (GPIO bank 0) 1= can - # , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal - # 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_o - # t- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control - # Signal) + # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0) 0= g + # pio0, Output, gpio_0_pin_out[1]- (GPIO bank 0) 1= can1, Input, can1_phy_ + # rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + # , Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG + # TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc3, Ou + # tput, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART + # receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control + # Signal) # PSU_IOU_SLCR_MIO_PIN_1_L3_SEL 0 # Configures MIO Pin 1 peripheral interface mapping @@ -8420,20 +9226,25 @@ set psu_mio_init_data { mask_write 0XFF180004 0x000000FE 0x00000002 # Register : MIO_PIN_2 @ 0XFF180008

- # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus) + # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI + # Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus) # PSU_IOU_SLCR_MIO_PIN_2_L0_SEL 1 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used # PSU_IOU_SLCR_MIO_PIN_2_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[2]- (Test Scan Port) = test_scan, Outp - # t, test_scan_out[2]- (Test Scan Port) 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + # , test_scan_in[2]- (Test Scan Port) = test_scan, Output, test_scan_out[2 + # ]- (Test Scan Port) 3= Not Used # PSU_IOU_SLCR_MIO_PIN_2_L2_SEL 0 - # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[2]- (GPIO bank 0) 1= can - # , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal - # 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc2, Input, ttc2_clk_in - # (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[0]- (Trace Port Databus) + # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0) 0= g + # pio0, Output, gpio_0_pin_out[2]- (GPIO bank 0) 1= can0, Input, can0_phy_ + # rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + # , Output, i2c0_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTAG + # TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc2, I + # nput, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver se + # rial input) 7= trace, Output, tracedq[0]- (Trace Port Databus) # PSU_IOU_SLCR_MIO_PIN_2_L3_SEL 0 # Configures MIO Pin 2 peripheral interface mapping @@ -8441,21 +9252,26 @@ set psu_mio_init_data { mask_write 0XFF180008 0x000000FE 0x00000002 # Register : MIO_PIN_3 @ 0XFF18000C

- # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus) + # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI + # Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus) # PSU_IOU_SLCR_MIO_PIN_3_L0_SEL 1 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used # PSU_IOU_SLCR_MIO_PIN_3_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[3]- (Test Scan Port) = test_scan, Outp - # t, test_scan_out[3]- (Test Scan Port) 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + # , test_scan_in[3]- (Test Scan Port) = test_scan, Output, test_scan_out[3 + # ]- (Test Scan Port) 3= Not Used # PSU_IOU_SLCR_MIO_PIN_3_L2_SEL 0 - # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[3]- (GPIO bank 0) 1= can - # , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa - # ) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0 - # - (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial - # output) 7= trace, Output, tracedq[1]- (Trace Port Databus) + # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0) 0= g + # pio0, Output, gpio_0_pin_out[3]- (GPIO bank 0) 1= can0, Output, can0_phy + # _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + # 0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG + # TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output + # , spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- + # (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial + # output) 7= trace, Output, tracedq[1]- (Trace Port Databus) # PSU_IOU_SLCR_MIO_PIN_3_L3_SEL 0 # Configures MIO Pin 3 peripheral interface mapping @@ -8463,22 +9279,26 @@ set psu_mio_init_data { mask_write 0XFF18000C 0x000000FE 0x00000002 # Register : MIO_PIN_4 @ 0XFF180010

- # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- (QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Data - # us) + # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- ( + # QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Databus) # PSU_IOU_SLCR_MIO_PIN_4_L0_SEL 1 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used # PSU_IOU_SLCR_MIO_PIN_4_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[4]- (Test Scan Port) = test_scan, Outp - # t, test_scan_out[4]- (Test Scan Port) 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + # , test_scan_in[4]- (Test Scan Port) = test_scan, Output, test_scan_out[4 + # ]- (Test Scan Port) 3= Not Used # PSU_IOU_SLCR_MIO_PIN_4_L2_SEL 0 - # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[4]- (GPIO bank 0) 1= can - # , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa - # ) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_s - # - (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, - # utput, tracedq[2]- (Trace Port Databus) + # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0) 0= g + # pio0, Output, gpio_0_pin_out[4]- (GPIO bank 0) 1= can1, Output, can1_phy + # _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + # 1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Wa + # tch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi + # 0, Output, spi0_so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Cloc + # k) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, O + # utput, tracedq[2]- (Trace Port Databus) # PSU_IOU_SLCR_MIO_PIN_4_L3_SEL 0 # Configures MIO Pin 4 peripheral interface mapping @@ -8486,21 +9306,26 @@ set psu_mio_init_data { mask_write 0XFF180010 0x000000FE 0x00000002 # Register : MIO_PIN_5 @ 0XFF180014

- # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out- (QSPI Slave Select) + # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out- + # (QSPI Slave Select) # PSU_IOU_SLCR_MIO_PIN_5_L0_SEL 1 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used # PSU_IOU_SLCR_MIO_PIN_5_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[5]- (Test Scan Port) = test_scan, Outp - # t, test_scan_out[5]- (Test Scan Port) 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + # , test_scan_in[5]- (Test Scan Port) = test_scan, Output, test_scan_out[5 + # ]- (Test Scan Port) 3= Not Used # PSU_IOU_SLCR_MIO_PIN_5_L2_SEL 0 - # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[5]- (GPIO bank 0) 1= can - # , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal - # 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi0 - # si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7 - # trace, Output, tracedq[3]- (Trace Port Databus) + # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0) 0= g + # pio0, Output, gpio_0_pin_out[5]- (GPIO bank 0) 1= can1, Input, can1_phy_ + # rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + # , Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (W + # atch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= + # spi0, Input, spi0_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC + # Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= + # trace, Output, tracedq[3]- (Trace Port Databus) # PSU_IOU_SLCR_MIO_PIN_5_L3_SEL 0 # Configures MIO Pin 5 peripheral interface mapping @@ -8508,21 +9333,26 @@ set psu_mio_init_data { mask_write 0XFF180014 0x000000FE 0x00000002 # Register : MIO_PIN_6 @ 0XFF180018

- # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_clk_for_lpbk- (QSPI Clock to be fed-back) + # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_clk_for_l + # pbk- (QSPI Clock to be fed-back) # PSU_IOU_SLCR_MIO_PIN_6_L0_SEL 1 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used # PSU_IOU_SLCR_MIO_PIN_6_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[6]- (Test Scan Port) = test_scan, Outp - # t, test_scan_out[6]- (Test Scan Port) 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + # , test_scan_in[6]- (Test Scan Port) = test_scan, Output, test_scan_out[6 + # ]- (Test Scan Port) 3= Not Used # PSU_IOU_SLCR_MIO_PIN_6_L2_SEL 0 - # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[6]- (GPIO bank 0) 1= can - # , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal - # 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1 - # sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, - # Output, tracedq[4]- (Trace Port Databus) + # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0) 0= g + # pio0, Output, gpio_0_pin_out[6]- (GPIO bank 0) 1= can0, Input, can0_phy_ + # rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + # , Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Wat + # ch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= s + # pi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TT + # C Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, + # Output, tracedq[4]- (Trace Port Databus) # PSU_IOU_SLCR_MIO_PIN_6_L3_SEL 0 # Configures MIO Pin 6 peripheral interface mapping @@ -8530,21 +9360,26 @@ set psu_mio_init_data { mask_write 0XFF180018 0x000000FE 0x00000002 # Register : MIO_PIN_7 @ 0XFF18001C

- # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out_upper- (QSPI Slave Select upper) + # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out_ + # upper- (QSPI Slave Select upper) # PSU_IOU_SLCR_MIO_PIN_7_L0_SEL 1 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used # PSU_IOU_SLCR_MIO_PIN_7_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[7]- (Test Scan Port) = test_scan, Outp - # t, test_scan_out[7]- (Test Scan Port) 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + # , test_scan_in[7]- (Test Scan Port) = test_scan, Output, test_scan_out[7 + # ]- (Test Scan Port) 3= Not Used # PSU_IOU_SLCR_MIO_PIN_7_L2_SEL 0 - # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[7]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[7]- (GPIO bank 0) 1= can - # , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa - # ) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= - # tc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, - # racedq[5]- (Trace Port Databus) + # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[7]- (GPIO bank 0) 0= g + # pio0, Output, gpio_0_pin_out[7]- (GPIO bank 0) 1= can0, Output, can0_phy + # _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + # 0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- ( + # Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Ma + # ster Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua + # 0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, t + # racedq[5]- (Trace Port Databus) # PSU_IOU_SLCR_MIO_PIN_7_L3_SEL 0 # Configures MIO Pin 7 peripheral interface mapping @@ -8552,22 +9387,27 @@ set psu_mio_init_data { mask_write 0XFF18001C 0x000000FE 0x00000002 # Register : MIO_PIN_8 @ 0XFF180020

- # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[0]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe - # [0]- (QSPI Upper Databus) + # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[0 + # ]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[0]- (QSPI Upper D + # atabus) # PSU_IOU_SLCR_MIO_PIN_8_L0_SEL 1 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used # PSU_IOU_SLCR_MIO_PIN_8_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[8]- (Test Scan Port) = test_scan, Outp - # t, test_scan_out[8]- (Test Scan Port) 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + # , test_scan_in[8]- (Test Scan Port) = test_scan, Output, test_scan_out[8 + # ]- (Test Scan Port) 3= Not Used # PSU_IOU_SLCR_MIO_PIN_8_L2_SEL 0 - # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[8]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[8]- (GPIO bank 0) 1= can - # , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa - # ) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc - # , Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Tr - # ce Port Databus) + # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[8]- (GPIO bank 0) 0= g + # pio0, Output, gpio_0_pin_out[8]- (GPIO bank 0) 1= can1, Output, can1_phy + # _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + # 1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Wa + # tch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Maste + # r Selects) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_ + # txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Tra + # ce Port Databus) # PSU_IOU_SLCR_MIO_PIN_8_L3_SEL 0 # Configures MIO Pin 8 peripheral interface mapping @@ -8575,22 +9415,29 @@ set psu_mio_init_data { mask_write 0XFF180020 0x000000FE 0x00000002 # Register : MIO_PIN_9 @ 0XFF180024

- # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[1]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe - # [1]- (QSPI Upper Databus) + # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[1 + # ]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[1]- (QSPI Upper D + # atabus) # PSU_IOU_SLCR_MIO_PIN_9_L0_SEL 1 - # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NAND chip enable) + # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NA + # ND chip enable) # PSU_IOU_SLCR_MIO_PIN_9_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[9]- (Test Scan Port) = test_scan, Outp - # t, test_scan_out[9]- (Test Scan Port) 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + # , test_scan_in[9]- (Test Scan Port) = test_scan, Output, test_scan_out[9 + # ]- (Test Scan Port) 3= Not Used # PSU_IOU_SLCR_MIO_PIN_9_L2_SEL 0 - # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[9]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[9]- (GPIO bank 0) 1= can - # , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal - # 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, - # utput, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (U - # RT receiver serial input) 7= trace, Output, tracedq[7]- (Trace Port Databus) + # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[9]- (GPIO bank 0) 0= g + # pio0, Output, gpio_0_pin_out[9]- (GPIO bank 0) 1= can1, Input, can1_phy_ + # rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + # , Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (W + # atch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master S + # elects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc3, + # Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UA + # RT receiver serial input) 7= trace, Output, tracedq[7]- (Trace Port Data + # bus) # PSU_IOU_SLCR_MIO_PIN_9_L3_SEL 0 # Configures MIO Pin 9 peripheral interface mapping @@ -8598,22 +9445,28 @@ set psu_mio_init_data { mask_write 0XFF180024 0x000000FE 0x00000002 # Register : MIO_PIN_10 @ 0XFF180028

- # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[2]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe - # [2]- (QSPI Upper Databus) + # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[2 + # ]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[2]- (QSPI Upper D + # atabus) # PSU_IOU_SLCR_MIO_PIN_10_L0_SEL 1 - # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (NAND Ready/Busy) + # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (N + # AND Ready/Busy) # PSU_IOU_SLCR_MIO_PIN_10_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[10]- (Test Scan Port) = test_scan, Out - # ut, test_scan_out[10]- (Test Scan Port) 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + # , test_scan_in[10]- (Test Scan Port) = test_scan, Output, test_scan_out[ + # 10]- (Test Scan Port) 3= Not Used # PSU_IOU_SLCR_MIO_PIN_10_L2_SEL 0 - # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[10]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[10]- (GPIO bank 0) 1= c - # n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - # l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_ - # o- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outp - # t, tracedq[8]- (Trace Port Databus) + # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[10]- (GPIO bank 0) 0= + # gpio0, Output, gpio_0_pin_out[10]- (GPIO bank 0) 1= can0, Input, can0_ph + # y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + # c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + # atch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= sp + # i1, Output, spi1_so- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clo + # ck) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outpu + # t, tracedq[8]- (Trace Port Databus) # PSU_IOU_SLCR_MIO_PIN_10_L3_SEL 0 # Configures MIO Pin 10 peripheral interface mapping @@ -8621,22 +9474,28 @@ set psu_mio_init_data { mask_write 0XFF180028 0x000000FE 0x00000002 # Register : MIO_PIN_11 @ 0XFF18002C

- # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[3]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe - # [3]- (QSPI Upper Databus) + # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[3 + # ]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[3]- (QSPI Upper D + # atabus) # PSU_IOU_SLCR_MIO_PIN_11_L0_SEL 1 - # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (NAND Ready/Busy) + # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (N + # AND Ready/Busy) # PSU_IOU_SLCR_MIO_PIN_11_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[11]- (Test Scan Port) = test_scan, Out - # ut, test_scan_out[11]- (Test Scan Port) 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + # , test_scan_in[11]- (Test Scan Port) = test_scan, Output, test_scan_out[ + # 11]- (Test Scan Port) 3= Not Used # PSU_IOU_SLCR_MIO_PIN_11_L2_SEL 0 - # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0) 1= c - # n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - # al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s - # i1_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o - # tput) 7= trace, Output, tracedq[9]- (Trace Port Databus) + # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0) 0= + # gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0) 1= can0, Output, can0_p + # hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + # 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + # (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) + # 4= spi1, Input, spi1_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- ( + # TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial ou + # tput) 7= trace, Output, tracedq[9]- (Trace Port Databus) # PSU_IOU_SLCR_MIO_PIN_11_L3_SEL 0 # Configures MIO Pin 11 peripheral interface mapping @@ -8644,22 +9503,27 @@ set psu_mio_init_data { mask_write 0XFF18002C 0x000000FE 0x00000002 # Register : MIO_PIN_12 @ 0XFF180030

- # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out_upper- (QSPI Upper Clock) + # Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out_ + # upper- (QSPI Upper Clock) # PSU_IOU_SLCR_MIO_PIN_12_L0_SEL 1 - # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NAND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe - # + # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NA + # ND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe) # PSU_IOU_SLCR_MIO_PIN_12_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[12]- (Test Scan Port) = test_scan, Out - # ut, test_scan_out[12]- (Test Scan Port) 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + # , test_scan_in[12]- (Test Scan Port) = test_scan, Output, test_scan_out[ + # 12]- (Test Scan Port) 3= Not Used # PSU_IOU_SLCR_MIO_PIN_12_L2_SEL 0 - # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[12]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[12]- (GPIO bank 0) 1= c - # n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - # al) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Cl - # ck) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trac - # dq[10]- (Trace Port Databus) + # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[12]- (GPIO bank 0) 0= + # gpio0, Output, gpio_0_pin_out[12]- (GPIO bank 0) 1= can1, Output, can1_p + # hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + # 2c1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJT + # AG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_ + # sclk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, O + # utput, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace + # dq[10]- (Trace Port Databus) # PSU_IOU_SLCR_MIO_PIN_12_L3_SEL 0 # Configures MIO Pin 12 peripheral interface mapping @@ -8670,19 +9534,24 @@ set psu_mio_init_data { # Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used # PSU_IOU_SLCR_MIO_PIN_13_L0_SEL 0 - # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[0]- (NAND chip enable) + # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[0]- (NA + # ND chip enable) # PSU_IOU_SLCR_MIO_PIN_13_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8 - # bit Data bus) 2= test_scan, Input, test_scan_in[13]- (Test Scan Port) = test_scan, Output, test_scan_out[13]- (Test Scan Port - # 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- + # (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8-bit Data bus) 2= t + # est_scan, Input, test_scan_in[13]- (Test Scan Port) = test_scan, Output, + # test_scan_out[13]- (Test Scan Port) 3= Not Used # PSU_IOU_SLCR_MIO_PIN_13_L2_SEL 0 - # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[13]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[13]- (GPIO bank 0) 1= c - # n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - # l) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave - # out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq[11]- (Trace Port Dat - # bus) + # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[13]- (GPIO bank 0) 0= + # gpio0, Output, gpio_0_pin_out[13]- (GPIO bank 0) 1= can1, Input, can1_ph + # y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + # c1, Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTA + # G TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, + # Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UAR + # T receiver serial input) 7= trace, Output, tracedq[11]- (Trace Port Data + # bus) # PSU_IOU_SLCR_MIO_PIN_13_L3_SEL 0 # Configures MIO Pin 13 peripheral interface mapping @@ -8693,18 +9562,23 @@ set psu_mio_init_data { # Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used # PSU_IOU_SLCR_MIO_PIN_14_L0_SEL 0 - # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_cle- (NAND Command Latch Enable) + # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_cle- (NAND + # Command Latch Enable) # PSU_IOU_SLCR_MIO_PIN_14_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8 - # bit Data bus) 2= test_scan, Input, test_scan_in[14]- (Test Scan Port) = test_scan, Output, test_scan_out[14]- (Test Scan Port - # 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- + # (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8-bit Data bus) 2= t + # est_scan, Input, test_scan_in[14]- (Test Scan Port) = test_scan, Output, + # test_scan_out[14]- (Test Scan Port) 3= Not Used # PSU_IOU_SLCR_MIO_PIN_14_L2_SEL 0 - # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0) 1= c - # n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - # l) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, Input, ttc0_clk_ - # n- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace Port Databus) + # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0) 0= + # gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0) 1= can0, Input, can0_ph + # y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + # c0, Output, i2c0_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJT + # AG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, + # Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver + # serial input) 7= trace, Output, tracedq[12]- (Trace Port Databus) # PSU_IOU_SLCR_MIO_PIN_14_L3_SEL 2 # Configures MIO Pin 14 peripheral interface mapping @@ -8715,19 +9589,24 @@ set psu_mio_init_data { # Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used # PSU_IOU_SLCR_MIO_PIN_15_L0_SEL 0 - # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ale- (NAND Address Latch Enable) + # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ale- (NAND + # Address Latch Enable) # PSU_IOU_SLCR_MIO_PIN_15_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8 - # bit Data bus) 2= test_scan, Input, test_scan_in[15]- (Test Scan Port) = test_scan, Output, test_scan_out[15]- (Test Scan Port - # 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- + # (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8-bit Data bus) 2= t + # est_scan, Input, test_scan_in[15]- (Test Scan Port) = test_scan, Output, + # test_scan_out[15]- (Test Scan Port) 3= Not Used # PSU_IOU_SLCR_MIO_PIN_15_L2_SEL 0 - # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[15]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[15]- (GPIO bank 0) 1= c - # n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - # al) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out - # 0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter seri - # l output) 7= trace, Output, tracedq[13]- (Trace Port Databus) + # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[15]- (GPIO bank 0) 0= + # gpio0, Output, gpio_0_pin_out[15]- (GPIO bank 0) 1= can0, Output, can0_p + # hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + # 2c0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJT + # AG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Outp + # ut, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_ou + # t- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter seria + # l output) 7= trace, Output, tracedq[13]- (Trace Port Databus) # PSU_IOU_SLCR_MIO_PIN_15_L3_SEL 2 # Configures MIO Pin 15 peripheral interface mapping @@ -8738,20 +9617,24 @@ set psu_mio_init_data { # Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used # PSU_IOU_SLCR_MIO_PIN_16_L0_SEL 0 - # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[0]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[0]- (NAND - # ata Bus) + # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[0]- ( + # NAND Data Bus) 1= nand, Output, nfc_dq_out[0]- (NAND Data Bus) # PSU_IOU_SLCR_MIO_PIN_16_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8 - # bit Data bus) 2= test_scan, Input, test_scan_in[16]- (Test Scan Port) = test_scan, Output, test_scan_out[16]- (Test Scan Port - # 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- + # (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8-bit Data bus) 2= t + # est_scan, Input, test_scan_in[16]- (Test Scan Port) = test_scan, Output, + # test_scan_out[16]- (Test Scan Port) 3= Not Used # PSU_IOU_SLCR_MIO_PIN_16_L2_SEL 0 - # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[16]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[16]- (GPIO bank 0) 1= c - # n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - # al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0 - # so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace - # Output, tracedq[14]- (Trace Port Databus) + # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[16]- (GPIO bank 0) 0= + # gpio0, Output, gpio_0_pin_out[16]- (GPIO bank 0) 1= can1, Output, can1_p + # hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + # 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + # Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= s + # pi0, Output, spi0_so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Cl + # ock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, + # Output, tracedq[14]- (Trace Port Databus) # PSU_IOU_SLCR_MIO_PIN_16_L3_SEL 2 # Configures MIO Pin 16 peripheral interface mapping @@ -8762,20 +9645,24 @@ set psu_mio_init_data { # Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used # PSU_IOU_SLCR_MIO_PIN_17_L0_SEL 0 - # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[1]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[1]- (NAND - # ata Bus) + # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[1]- ( + # NAND Data Bus) 1= nand, Output, nfc_dq_out[1]- (NAND Data Bus) # PSU_IOU_SLCR_MIO_PIN_17_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8 - # bit Data bus) 2= test_scan, Input, test_scan_in[17]- (Test Scan Port) = test_scan, Output, test_scan_out[17]- (Test Scan Port - # 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- + # (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8-bit Data bus) 2= t + # est_scan, Input, test_scan_in[17]- (Test Scan Port) = test_scan, Output, + # test_scan_out[17]- (Test Scan Port) 3= Not Used # PSU_IOU_SLCR_MIO_PIN_17_L2_SEL 0 - # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[17]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[17]- (GPIO bank 0) 1= c - # n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - # l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, sp - # 0_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) - # 7= trace, Output, tracedq[15]- (Trace Port Databus) + # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[17]- (GPIO bank 0) 0= + # gpio0, Output, gpio_0_pin_out[17]- (GPIO bank 0) 1= can1, Input, can1_ph + # y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + # c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + # (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4 + # = spi0, Input, spi0_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (T + # TC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) + # 7= trace, Output, tracedq[15]- (Trace Port Databus) # PSU_IOU_SLCR_MIO_PIN_17_L3_SEL 2 # Configures MIO Pin 17 peripheral interface mapping @@ -8786,19 +9673,24 @@ set psu_mio_init_data { # Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used # PSU_IOU_SLCR_MIO_PIN_18_L0_SEL 0 - # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[2]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[2]- (NAND - # ata Bus) + # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[2]- ( + # NAND Data Bus) 1= nand, Output, nfc_dq_out[2]- (NAND Data Bus) # PSU_IOU_SLCR_MIO_PIN_18_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8 - # bit Data bus) 2= test_scan, Input, test_scan_in[18]- (Test Scan Port) = test_scan, Output, test_scan_out[18]- (Test Scan Port - # 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper) + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- + # (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8-bit Data bus) 2= t + # est_scan, Input, test_scan_in[18]- (Test Scan Port) = test_scan, Output, + # test_scan_out[18]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU + # Ext Tamper) # PSU_IOU_SLCR_MIO_PIN_18_L2_SEL 0 - # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[18]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[18]- (GPIO bank 0) 1= c - # n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - # l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_ - # o- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used + # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[18]- (GPIO bank 0) 0= + # gpio0, Output, gpio_0_pin_out[18]- (GPIO bank 0) 1= can0, Input, can0_ph + # y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + # c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + # atch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= sp + # i1, Output, spi1_so- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clo + # ck) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used # PSU_IOU_SLCR_MIO_PIN_18_L3_SEL 6 # Configures MIO Pin 18 peripheral interface mapping @@ -8809,19 +9701,24 @@ set psu_mio_init_data { # Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used # PSU_IOU_SLCR_MIO_PIN_19_L0_SEL 0 - # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[3]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[3]- (NAND - # ata Bus) + # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[3]- ( + # NAND Data Bus) 1= nand, Output, nfc_dq_out[3]- (NAND Data Bus) # PSU_IOU_SLCR_MIO_PIN_19_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8 - # bit Data bus) 2= test_scan, Input, test_scan_in[19]- (Test Scan Port) = test_scan, Output, test_scan_out[19]- (Test Scan Port - # 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper) + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- + # (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8-bit Data bus) 2= t + # est_scan, Input, test_scan_in[19]- (Test Scan Port) = test_scan, Output, + # test_scan_out[19]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU + # Ext Tamper) # PSU_IOU_SLCR_MIO_PIN_19_L2_SEL 0 - # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[19]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[19]- (GPIO bank 0) 1= c - # n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - # al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5 - # ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used + # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[19]- (GPIO bank 0) 0= + # gpio0, Output, gpio_0_pin_out[19]- (GPIO bank 0) 1= can0, Output, can0_p + # hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + # 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + # (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI + # Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= + # ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used # PSU_IOU_SLCR_MIO_PIN_19_L3_SEL 6 # Configures MIO Pin 19 peripheral interface mapping @@ -8832,19 +9729,24 @@ set psu_mio_init_data { # Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used # PSU_IOU_SLCR_MIO_PIN_20_L0_SEL 0 - # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[4]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[4]- (NAND - # ata Bus) + # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[4]- ( + # NAND Data Bus) 1= nand, Output, nfc_dq_out[4]- (NAND Data Bus) # PSU_IOU_SLCR_MIO_PIN_20_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8 - # bit Data bus) 2= test_scan, Input, test_scan_in[20]- (Test Scan Port) = test_scan, Output, test_scan_out[20]- (Test Scan Port - # 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper) + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- + # (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8-bit Data bus) 2= t + # est_scan, Input, test_scan_in[20]- (Test Scan Port) = test_scan, Output, + # test_scan_out[20]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU + # Ext Tamper) # PSU_IOU_SLCR_MIO_PIN_20_L2_SEL 0 - # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[20]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[20]- (GPIO bank 0) 1= c - # n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - # al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= t - # c1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Used + # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[20]- (GPIO bank 0) 0= + # gpio0, Output, gpio_0_pin_out[20]- (GPIO bank 0) 1= can1, Output, can1_p + # hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + # 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + # Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Mas + # ter Selects) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua + # 1_txd- (UART transmitter serial output) 7= Not Used # PSU_IOU_SLCR_MIO_PIN_20_L3_SEL 6 # Configures MIO Pin 20 peripheral interface mapping @@ -8855,20 +9757,25 @@ set psu_mio_init_data { # Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used # PSU_IOU_SLCR_MIO_PIN_21_L0_SEL 0 - # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[5]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[5]- (NAND - # ata Bus) + # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[5]- ( + # NAND Data Bus) 1= nand, Output, nfc_dq_out[5]- (NAND Data Bus) # PSU_IOU_SLCR_MIO_PIN_21_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Comman - # Indicator) 2= test_scan, Input, test_scan_in[21]- (Test Scan Port) = test_scan, Output, test_scan_out[21]- (Test Scan Port) - # = csu, Input, csu_ext_tamper- (CSU Ext Tamper) + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Com + # mand Indicator) = sd0, Output, sdio0_cmd_out- (Command Indicator) 2= tes + # t_scan, Input, test_scan_in[21]- (Test Scan Port) = test_scan, Output, t + # est_scan_out[21]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU E + # xt Tamper) # PSU_IOU_SLCR_MIO_PIN_21_L2_SEL 0 - # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[21]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[21]- (GPIO bank 0) 1= c - # n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - # l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1 - # Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- - # UART receiver serial input) 7= Not Used + # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[21]- (GPIO bank 0) 0= + # gpio0, Output, gpio_0_pin_out[21]- (GPIO bank 0) 1= can1, Input, can1_ph + # y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + # c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + # (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master + # Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc + # 1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- ( + # UART receiver serial input) 7= Not Used # PSU_IOU_SLCR_MIO_PIN_21_L3_SEL 6 # Configures MIO Pin 21 peripheral interface mapping @@ -8879,18 +9786,24 @@ set psu_mio_init_data { # Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used # PSU_IOU_SLCR_MIO_PIN_22_L0_SEL 0 - # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_we_b- (NAND Write Enable) + # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_we_b- (NAN + # D Write Enable) # PSU_IOU_SLCR_MIO_PIN_22_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= test_scan, Input, test_scan_in[22]- - # (Test Scan Port) = test_scan, Output, test_scan_out[22]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper) + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- + # (SDSDIO clock) 2= test_scan, Input, test_scan_in[22]- (Test Scan Port) = + # test_scan, Output, test_scan_out[22]- (Test Scan Port) 3= csu, Input, c + # su_ext_tamper- (CSU Ext Tamper) # PSU_IOU_SLCR_MIO_PIN_22_L2_SEL 0 - # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[22]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[22]- (GPIO bank 0) 1= c - # n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - # l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, sp - # 1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not - # sed + # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[22]- (GPIO bank 0) 0= + # gpio0, Output, gpio_0_pin_out[22]- (GPIO bank 0) 1= can0, Input, can0_ph + # y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + # c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + # atch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= + # spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- ( + # TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not U + # sed # PSU_IOU_SLCR_MIO_PIN_22_L3_SEL 0 # Configures MIO Pin 22 peripheral interface mapping @@ -8901,20 +9814,24 @@ set psu_mio_init_data { # Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used # PSU_IOU_SLCR_MIO_PIN_23_L0_SEL 0 - # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[6]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[6]- (NAND - # ata Bus) + # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[6]- ( + # NAND Data Bus) 1= nand, Output, nfc_dq_out[6]- (NAND Data Bus) # PSU_IOU_SLCR_MIO_PIN_23_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= test_scan, Input, test_scan_in - # 23]- (Test Scan Port) = test_scan, Output, test_scan_out[23]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper - # + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- + # (SD card bus power) 2= test_scan, Input, test_scan_in[23]- (Test Scan Po + # rt) = test_scan, Output, test_scan_out[23]- (Test Scan Port) 3= csu, Inp + # ut, csu_ext_tamper- (CSU Ext Tamper) # PSU_IOU_SLCR_MIO_PIN_23_L2_SEL 0 - # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[23]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[23]- (GPIO bank 0) 1= c - # n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - # al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s - # i1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o - # tput) 7= Not Used + # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[23]- (GPIO bank 0) 0= + # gpio0, Output, gpio_0_pin_out[23]- (GPIO bank 0) 1= can0, Output, can0_p + # hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + # 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + # (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) + # 4= spi1, Input, spi1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- ( + # TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial ou + # tput) 7= Not Used # PSU_IOU_SLCR_MIO_PIN_23_L3_SEL 0 # Configures MIO Pin 23 peripheral interface mapping @@ -8925,19 +9842,23 @@ set psu_mio_init_data { # Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used # PSU_IOU_SLCR_MIO_PIN_24_L0_SEL 0 - # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[7]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[7]- (NAND - # ata Bus) + # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[7]- ( + # NAND Data Bus) 1= nand, Output, nfc_dq_out[7]- (NAND Data Bus) # PSU_IOU_SLCR_MIO_PIN_24_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= test_scan, Input, test - # scan_in[24]- (Test Scan Port) = test_scan, Output, test_scan_out[24]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ex - # Tamper) + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD + # card detect from connector) 2= test_scan, Input, test_scan_in[24]- (Test + # Scan Port) = test_scan, Output, test_scan_out[24]- (Test Scan Port) 3= + # csu, Input, csu_ext_tamper- (CSU Ext Tamper) # PSU_IOU_SLCR_MIO_PIN_24_L2_SEL 0 - # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[24]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[24]- (GPIO bank 0) 1= c - # n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - # al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= Not Used 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, - # Output, ua1_txd- (UART transmitter serial output) 7= Not Used + # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[24]- (GPIO bank 0) 0= + # gpio0, Output, gpio_0_pin_out[24]- (GPIO bank 0) 1= can1, Output, can1_p + # hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + # 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + # Watch Dog Timer Input clock) 4= Not Used 5= ttc3, Input, ttc3_clk_in- (T + # TC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= N + # ot Used # PSU_IOU_SLCR_MIO_PIN_24_L3_SEL 1 # Configures MIO Pin 24 peripheral interface mapping @@ -8948,18 +9869,23 @@ set psu_mio_init_data { # Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used # PSU_IOU_SLCR_MIO_PIN_25_L0_SEL 0 - # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_re_n- (NAND Read Enable) + # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_re_n- (NAN + # D Read Enable) # PSU_IOU_SLCR_MIO_PIN_25_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= test_scan, Input, - # test_scan_in[25]- (Test Scan Port) = test_scan, Output, test_scan_out[25]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (C - # U Ext Tamper) + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD ca + # rd write protect from connector) 2= test_scan, Input, test_scan_in[25]- + # (Test Scan Port) = test_scan, Output, test_scan_out[25]- (Test Scan Port + # ) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper) # PSU_IOU_SLCR_MIO_PIN_25_L2_SEL 0 - # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[25]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[25]- (GPIO bank 0) 1= c - # n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - # l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= Not Used 5= ttc3, Output, ttc3_wave_out- (TTC Waveform - # lock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used + # Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[25]- (GPIO bank 0) 0= + # gpio0, Output, gpio_0_pin_out[25]- (GPIO bank 0) 1= can1, Input, can1_ph + # y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + # c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + # (Watch Dog Timer Output clock) 4= Not Used 5= ttc3, Output, ttc3_wave_ou + # t- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial in + # put) 7= Not Used # PSU_IOU_SLCR_MIO_PIN_25_L3_SEL 1 # Configures MIO Pin 25 peripheral interface mapping @@ -8967,21 +9893,28 @@ set psu_mio_init_data { mask_write 0XFF180064 0x000000FE 0x00000020 # Register : MIO_PIN_26 @ 0XFF180068

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_clk- (TX RGMII clock) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ + # clk- (TX RGMII clock) # PSU_IOU_SLCR_MIO_PIN_26_L0_SEL 0 - # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NAND chip enable) + # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NA + # ND chip enable) # PSU_IOU_SLCR_MIO_PIN_26_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[0]- (PMU GPI) 2= test_scan, Input, test_scan_in[26]- (Test Sc - # n Port) = test_scan, Output, test_scan_out[26]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper) + # Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[0]- (PMU + # GPI) 2= test_scan, Input, test_scan_in[26]- (Test Scan Port) = test_sca + # n, Output, test_scan_out[26]- (Test Scan Port) 3= csu, Input, csu_ext_ta + # mper- (CSU Ext Tamper) # PSU_IOU_SLCR_MIO_PIN_26_L2_SEL 0 - # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[0]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[0]- (GPIO bank 1) 1= can - # , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal - # 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Clock - # 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- - # Trace Port Databus) + # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[0]- (GPIO bank 1) 0= g + # pio1, Output, gpio_1_pin_out[0]- (GPIO bank 1) 1= can0, Input, can0_phy_ + # rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + # , Output, i2c0_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG + # TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_scl + # k_out- (SPI Clock) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Inpu + # t, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- ( + # Trace Port Databus) # PSU_IOU_SLCR_MIO_PIN_26_L3_SEL 0 # Configures MIO Pin 26 peripheral interface mapping @@ -8989,22 +9922,28 @@ set psu_mio_init_data { mask_write 0XFF180068 0x000000FE 0x00000000 # Register : MIO_PIN_27 @ 0XFF18006C

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[0]- (TX RGMII data) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd + # [0]- (TX RGMII data) # PSU_IOU_SLCR_MIO_PIN_27_L0_SEL 0 - # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (NAND Ready/Busy) + # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (N + # AND Ready/Busy) # PSU_IOU_SLCR_MIO_PIN_27_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[1]- (PMU GPI) 2= test_scan, Input, test_scan_in[27]- (Test Sc - # n Port) = test_scan, Output, test_scan_out[27]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Outp - # t, dp_aux_data_out- (Dp Aux Data) + # Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[1]- (PMU + # GPI) 2= test_scan, Input, test_scan_in[27]- (Test Scan Port) = test_sca + # n, Output, test_scan_out[27]- (Test Scan Port) 3= dpaux, Input, dp_aux_d + # ata_in- (Dp Aux Data) = dpaux, Output, dp_aux_data_out- (Dp Aux Data) # PSU_IOU_SLCR_MIO_PIN_27_L2_SEL 3 - # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[1]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[1]- (GPIO bank 1) 1= can - # , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa - # ) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_ - # ut- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port - # atabus) + # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[1]- (GPIO bank 1) 0= g + # pio1, Output, gpio_1_pin_out[1]- (GPIO bank 1) 1= can0, Output, can0_phy + # _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + # 0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG + # TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc2, O + # utput, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UAR + # T transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port D + # atabus) # PSU_IOU_SLCR_MIO_PIN_27_L3_SEL 0 # Configures MIO Pin 27 peripheral interface mapping @@ -9012,20 +9951,27 @@ set psu_mio_init_data { mask_write 0XFF18006C 0x000000FE 0x00000018 # Register : MIO_PIN_28 @ 0XFF180070

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[1]- (TX RGMII data) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd + # [1]- (TX RGMII data) # PSU_IOU_SLCR_MIO_PIN_28_L0_SEL 0 - # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (NAND Ready/Busy) + # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (N + # AND Ready/Busy) # PSU_IOU_SLCR_MIO_PIN_28_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[2]- (PMU GPI) 2= test_scan, Input, test_scan_in[28]- (Test Sc - # n Port) = test_scan, Output, test_scan_out[28]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug) + # Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[2]- (PMU + # GPI) 2= test_scan, Input, test_scan_in[28]- (Test Scan Port) = test_sca + # n, Output, test_scan_out[28]- (Test Scan Port) 3= dpaux, Input, dp_hot_p + # lug_detect- (Dp Aux Hot Plug) # PSU_IOU_SLCR_MIO_PIN_28_L2_SEL 3 - # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[2]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[2]- (GPIO bank 1) 1= can - # , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa - # ) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc1, Input, ttc1_clk_i - # - (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus) + # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[2]- (GPIO bank 1) 0= g + # pio1, Output, gpio_1_pin_out[2]- (GPIO bank 1) 1= can1, Output, can1_phy + # _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + # 1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTA + # G TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc1, + # Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitt + # er serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus) # PSU_IOU_SLCR_MIO_PIN_28_L3_SEL 0 # Configures MIO Pin 28 peripheral interface mapping @@ -9033,22 +9979,28 @@ set psu_mio_init_data { mask_write 0XFF180070 0x000000FE 0x00000018 # Register : MIO_PIN_29 @ 0XFF180074

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[2]- (TX RGMII data) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd + # [2]- (TX RGMII data) # PSU_IOU_SLCR_MIO_PIN_29_L0_SEL 0 - # Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal) + # Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + # PCIE Reset signal) # PSU_IOU_SLCR_MIO_PIN_29_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[3]- (PMU GPI) 2= test_scan, Input, test_scan_in[29]- (Test Sc - # n Port) = test_scan, Output, test_scan_out[29]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Outp - # t, dp_aux_data_out- (Dp Aux Data) + # Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[3]- (PMU + # GPI) 2= test_scan, Input, test_scan_in[29]- (Test Scan Port) = test_sca + # n, Output, test_scan_out[29]- (Test Scan Port) 3= dpaux, Input, dp_aux_d + # ata_in- (Dp Aux Data) = dpaux, Output, dp_aux_data_out- (Dp Aux Data) # PSU_IOU_SLCR_MIO_PIN_29_L2_SEL 3 - # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[3]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[3]- (GPIO bank 1) 1= can - # , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal - # 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0] - # (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial inpu - # ) 7= trace, Output, tracedq[7]- (Trace Port Databus) + # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[3]- (GPIO bank 1) 0= g + # pio1, Output, gpio_1_pin_out[3]- (GPIO bank 1) 1= can1, Input, can1_phy_ + # rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + # , Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG + # TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, + # spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- + # (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input + # ) 7= trace, Output, tracedq[7]- (Trace Port Databus) # PSU_IOU_SLCR_MIO_PIN_29_L3_SEL 0 # Configures MIO Pin 29 peripheral interface mapping @@ -9056,21 +10008,28 @@ set psu_mio_init_data { mask_write 0XFF180074 0x000000FE 0x00000018 # Register : MIO_PIN_30 @ 0XFF180078

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[3]- (TX RGMII data) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd + # [3]- (TX RGMII data) # PSU_IOU_SLCR_MIO_PIN_30_L0_SEL 0 - # Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal) + # Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + # PCIE Reset signal) # PSU_IOU_SLCR_MIO_PIN_30_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[4]- (PMU GPI) 2= test_scan, Input, test_scan_in[30]- (Test Sc - # n Port) = test_scan, Output, test_scan_out[30]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug) + # Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[4]- (PMU + # GPI) 2= test_scan, Input, test_scan_in[30]- (Test Scan Port) = test_sca + # n, Output, test_scan_out[30]- (Test Scan Port) 3= dpaux, Input, dp_hot_p + # lug_detect- (Dp Aux Hot Plug) # PSU_IOU_SLCR_MIO_PIN_30_L2_SEL 3 - # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[4]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[4]- (GPIO bank 1) 1= can - # , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal - # 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_so - # (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output - # tracedq[8]- (Trace Port Databus) + # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[4]- (GPIO bank 1) 0= g + # pio1, Output, gpio_1_pin_out[4]- (GPIO bank 1) 1= can0, Input, can0_phy_ + # rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + # , Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Wat + # ch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0 + # , Output, spi0_so- (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clock + # ) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, + # tracedq[8]- (Trace Port Databus) # PSU_IOU_SLCR_MIO_PIN_30_L3_SEL 0 # Configures MIO Pin 30 peripheral interface mapping @@ -9078,21 +10037,28 @@ set psu_mio_init_data { mask_write 0XFF180078 0x000000FE 0x00000018 # Register : MIO_PIN_31 @ 0XFF18007C

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ctl- (TX RGMII control) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ + # ctl- (TX RGMII control) # PSU_IOU_SLCR_MIO_PIN_31_L0_SEL 0 - # Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal) + # Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + # PCIE Reset signal) # PSU_IOU_SLCR_MIO_PIN_31_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[5]- (PMU GPI) 2= test_scan, Input, test_scan_in[31]- (Test Sc - # n Port) = test_scan, Output, test_scan_out[31]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper) + # Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[5]- (PMU + # GPI) 2= test_scan, Input, test_scan_in[31]- (Test Scan Port) = test_sca + # n, Output, test_scan_out[31]- (Test Scan Port) 3= csu, Input, csu_ext_ta + # mper- (CSU Ext Tamper) # PSU_IOU_SLCR_MIO_PIN_31_L2_SEL 0 - # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[5]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[5]- (GPIO bank 1) 1= can - # , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa - # ) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi - # _si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial out - # ut) 7= trace, Output, tracedq[9]- (Trace Port Databus) + # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[5]- (GPIO bank 1) 0= g + # pio1, Output, gpio_1_pin_out[5]- (GPIO bank 1) 1= can0, Output, can0_phy + # _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + # 0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- ( + # Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= + # spi0, Input, spi0_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TT + # C Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial outp + # ut) 7= trace, Output, tracedq[9]- (Trace Port Databus) # PSU_IOU_SLCR_MIO_PIN_31_L3_SEL 0 # Configures MIO Pin 31 peripheral interface mapping @@ -9100,22 +10066,28 @@ set psu_mio_init_data { mask_write 0XFF18007C 0x000000FE 0x00000000 # Register : MIO_PIN_32 @ 0XFF180080

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_clk- (RX RGMII clock) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_c + # lk- (RX RGMII clock) # PSU_IOU_SLCR_MIO_PIN_32_L0_SEL 0 - # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NAND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe - # + # Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NA + # ND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe) # PSU_IOU_SLCR_MIO_PIN_32_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[0]- (PMU GPI) 2= test_scan, Input, test_scan_in[32]- (Test S - # an Port) = test_scan, Output, test_scan_out[32]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper) + # Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[0]- (PM + # U GPI) 2= test_scan, Input, test_scan_in[32]- (Test Scan Port) = test_sc + # an, Output, test_scan_out[32]- (Test Scan Port) 3= csu, Input, csu_ext_t + # amper- (CSU Ext Tamper) # PSU_IOU_SLCR_MIO_PIN_32_L2_SEL 1 - # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[6]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[6]- (GPIO bank 1) 1= can - # , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa - # ) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi - # _sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= - # race, Output, tracedq[10]- (Trace Port Databus) + # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[6]- (GPIO bank 1) 0= g + # pio1, Output, gpio_1_pin_out[6]- (GPIO bank 1) 1= can1, Output, can1_phy + # _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + # 1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Wa + # tch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= + # spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (T + # TC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= t + # race, Output, tracedq[10]- (Trace Port Databus) # PSU_IOU_SLCR_MIO_PIN_32_L3_SEL 0 # Configures MIO Pin 32 peripheral interface mapping @@ -9123,21 +10095,28 @@ set psu_mio_init_data { mask_write 0XFF180080 0x000000FE 0x00000008 # Register : MIO_PIN_33 @ 0XFF180084

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[0]- (RX RGMII data) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[ + # 0]- (RX RGMII data) # PSU_IOU_SLCR_MIO_PIN_33_L0_SEL 0 - # Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal) + # Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + # PCIE Reset signal) # PSU_IOU_SLCR_MIO_PIN_33_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[1]- (PMU GPI) 2= test_scan, Input, test_scan_in[33]- (Test S - # an Port) = test_scan, Output, test_scan_out[33]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper) + # Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[1]- (PM + # U GPI) 2= test_scan, Input, test_scan_in[33]- (Test Scan Port) = test_sc + # an, Output, test_scan_out[33]- (Test Scan Port) 3= csu, Input, csu_ext_t + # amper- (CSU Ext Tamper) # PSU_IOU_SLCR_MIO_PIN_33_L2_SEL 1 - # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[7]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[7]- (GPIO bank 1) 1= can - # , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal - # 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= t - # c3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, traced - # [11]- (Trace Port Databus) + # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[7]- (GPIO bank 1) 0= g + # pio1, Output, gpio_1_pin_out[7]- (GPIO bank 1) 1= can1, Input, can1_phy_ + # rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + # , Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (W + # atch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Mas + # ter Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1 + # , Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq + # [11]- (Trace Port Databus) # PSU_IOU_SLCR_MIO_PIN_33_L3_SEL 0 # Configures MIO Pin 33 peripheral interface mapping @@ -9145,22 +10124,28 @@ set psu_mio_init_data { mask_write 0XFF180084 0x000000FE 0x00000008 # Register : MIO_PIN_34 @ 0XFF180088

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[1]- (RX RGMII data) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[ + # 1]- (RX RGMII data) # PSU_IOU_SLCR_MIO_PIN_34_L0_SEL 0 - # Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal) + # Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + # PCIE Reset signal) # PSU_IOU_SLCR_MIO_PIN_34_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[2]- (PMU GPI) 2= test_scan, Input, test_scan_in[34]- (Test S - # an Port) = test_scan, Output, test_scan_out[34]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Out - # ut, dp_aux_data_out- (Dp Aux Data) + # Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[2]- (PM + # U GPI) 2= test_scan, Input, test_scan_in[34]- (Test Scan Port) = test_sc + # an, Output, test_scan_out[34]- (Test Scan Port) 3= dpaux, Input, dp_aux_ + # data_in- (Dp Aux Data) = dpaux, Output, dp_aux_data_out- (Dp Aux Data) # PSU_IOU_SLCR_MIO_PIN_34_L2_SEL 1 - # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[8]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[8]- (GPIO bank 1) 1= can - # , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal - # 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc2 - # Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace P - # rt Databus) + # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[8]- (GPIO bank 1) 0= g + # pio1, Output, gpio_1_pin_out[8]- (GPIO bank 1) 1= can0, Input, can0_phy_ + # rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + # , Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Wat + # ch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master + # Selects) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rx + # d- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace Po + # rt Databus) # PSU_IOU_SLCR_MIO_PIN_34_L3_SEL 0 # Configures MIO Pin 34 peripheral interface mapping @@ -9168,21 +10153,29 @@ set psu_mio_init_data { mask_write 0XFF180088 0x000000FE 0x00000008 # Register : MIO_PIN_35 @ 0XFF18008C

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[2]- (RX RGMII data) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[ + # 2]- (RX RGMII data) # PSU_IOU_SLCR_MIO_PIN_35_L0_SEL 0 - # Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal) + # Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + # PCIE Reset signal) # PSU_IOU_SLCR_MIO_PIN_35_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[3]- (PMU GPI) 2= test_scan, Input, test_scan_in[35]- (Test S - # an Port) = test_scan, Output, test_scan_out[35]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug) + # Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[3]- (PM + # U GPI) 2= test_scan, Input, test_scan_in[35]- (Test Scan Port) = test_sc + # an, Output, test_scan_out[35]- (Test Scan Port) 3= dpaux, Input, dp_hot_ + # plug_detect- (Dp Aux Hot Plug) # PSU_IOU_SLCR_MIO_PIN_35_L2_SEL 1 - # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[9]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[9]- (GPIO bank 1) 1= can - # , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa - # ) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, - # Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- - # UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace Port Databus) + # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[9]- (GPIO bank 1) 0= g + # pio1, Output, gpio_1_pin_out[9]- (GPIO bank 1) 1= can0, Output, can0_phy + # _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + # 0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- ( + # Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master + # Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc2 + # , Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- ( + # UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace Po + # rt Databus) # PSU_IOU_SLCR_MIO_PIN_35_L3_SEL 0 # Configures MIO Pin 35 peripheral interface mapping @@ -9190,22 +10183,28 @@ set psu_mio_init_data { mask_write 0XFF18008C 0x000000FE 0x00000008 # Register : MIO_PIN_36 @ 0XFF180090

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[3]- (RX RGMII data) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[ + # 3]- (RX RGMII data) # PSU_IOU_SLCR_MIO_PIN_36_L0_SEL 0 - # Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal) + # Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + # PCIE Reset signal) # PSU_IOU_SLCR_MIO_PIN_36_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[4]- (PMU GPI) 2= test_scan, Input, test_scan_in[36]- (Test S - # an Port) = test_scan, Output, test_scan_out[36]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Out - # ut, dp_aux_data_out- (Dp Aux Data) + # Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[4]- (PM + # U GPI) 2= test_scan, Input, test_scan_in[36]- (Test Scan Port) = test_sc + # an, Output, test_scan_out[36]- (Test Scan Port) 3= dpaux, Input, dp_aux_ + # data_in- (Dp Aux Data) = dpaux, Output, dp_aux_data_out- (Dp Aux Data) # PSU_IOU_SLCR_MIO_PIN_36_L2_SEL 1 - # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[10]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[10]- (GPIO bank 1) 1= c - # n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - # al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1 - # so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace - # Output, tracedq[14]- (Trace Port Databus) + # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[10]- (GPIO bank 1) 0= + # gpio1, Output, gpio_1_pin_out[10]- (GPIO bank 1) 1= can1, Output, can1_p + # hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + # 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + # Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= s + # pi1, Output, spi1_so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Cl + # ock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, + # Output, tracedq[14]- (Trace Port Databus) # PSU_IOU_SLCR_MIO_PIN_36_L3_SEL 0 # Configures MIO Pin 36 peripheral interface mapping @@ -9213,21 +10212,28 @@ set psu_mio_init_data { mask_write 0XFF180090 0x000000FE 0x00000008 # Register : MIO_PIN_37 @ 0XFF180094

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_ctl- (RX RGMII control ) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_c + # tl- (RX RGMII control ) # PSU_IOU_SLCR_MIO_PIN_37_L0_SEL 0 - # Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal) + # Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + # PCIE Reset signal) # PSU_IOU_SLCR_MIO_PIN_37_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[5]- (PMU GPI) 2= test_scan, Input, test_scan_in[37]- (Test S - # an Port) = test_scan, Output, test_scan_out[37]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug) + # Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[5]- (PM + # U GPI) 2= test_scan, Input, test_scan_in[37]- (Test Scan Port) = test_sc + # an, Output, test_scan_out[37]- (Test Scan Port) 3= dpaux, Input, dp_hot_ + # plug_detect- (Dp Aux Hot Plug) # PSU_IOU_SLCR_MIO_PIN_37_L2_SEL 1 - # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[11]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[11]- (GPIO bank 1) 1= c - # n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - # l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, sp - # 1_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) - # 7= trace, Output, tracedq[15]- (Trace Port Databus) + # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[11]- (GPIO bank 1) 0= + # gpio1, Output, gpio_1_pin_out[11]- (GPIO bank 1) 1= can1, Input, can1_ph + # y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + # c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + # (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4 + # = spi1, Input, spi1_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (T + # TC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) + # 7= trace, Output, tracedq[15]- (Trace Port Databus) # PSU_IOU_SLCR_MIO_PIN_37_L3_SEL 0 # Configures MIO Pin 37 peripheral interface mapping @@ -9235,20 +10241,25 @@ set psu_mio_init_data { mask_write 0XFF180094 0x000000FE 0x00000008 # Register : MIO_PIN_38 @ 0XFF180098

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_clk- (TX RGMII clock) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ + # clk- (TX RGMII clock) # PSU_IOU_SLCR_MIO_PIN_38_L0_SEL 0 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used # PSU_IOU_SLCR_MIO_PIN_38_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= Not Used 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- + # (SDSDIO clock) 2= Not Used 3= Not Used # PSU_IOU_SLCR_MIO_PIN_38_L2_SEL 0 - # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[12]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[12]- (GPIO bank 1) 1= c - # n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - # l) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Clo - # k) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, trace_clk- - # (Trace Port Clock) + # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[12]- (GPIO bank 1) 0= + # gpio1, Output, gpio_1_pin_out[12]- (GPIO bank 1) 1= can0, Input, can0_ph + # y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + # c0, Output, i2c0_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTA + # G TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_s + # clk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, In + # put, ua0_rxd- (UART receiver serial input) 7= trace, Output, trace_clk- + # (Trace Port Clock) # PSU_IOU_SLCR_MIO_PIN_38_L3_SEL 0 # Configures MIO Pin 38 peripheral interface mapping @@ -9256,130 +10267,163 @@ set psu_mio_init_data { mask_write 0XFF180098 0x000000FE 0x00000000 # Register : MIO_PIN_39 @ 0XFF18009C

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[0]- (TX RGMII data) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd + # [0]- (TX RGMII data) # PSU_IOU_SLCR_MIO_PIN_39_L0_SEL 0 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used # PSU_IOU_SLCR_MIO_PIN_39_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= sd1, Input, sd1_data_i - # [4]- (8-bit Data bus) = sd1, Output, sdio1_data_out[4]- (8-bit Data bus) 3= Not Used - # PSU_IOU_SLCR_MIO_PIN_39_L2_SEL 0 + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD + # card detect from connector) 2= sd1, Input, sd1_data_in[4]- (8-bit Data b + # us) = sd1, Output, sdio1_data_out[4]- (8-bit Data bus) 3= Not Used + # PSU_IOU_SLCR_MIO_PIN_39_L2_SEL 2 - # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[13]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[13]- (GPIO bank 1) 1= c - # n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - # al) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc0, Output, ttc0_wav - # _out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, trace_ctl- (Trace Port - # Control Signal) + # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[13]- (GPIO bank 1) 0= + # gpio1, Output, gpio_1_pin_out[13]- (GPIO bank 1) 1= can0, Output, can0_p + # hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + # 2c0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJT + # AG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc0, + # Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (U + # ART transmitter serial output) 7= trace, Output, trace_ctl- (Trace Port + # Control Signal) # PSU_IOU_SLCR_MIO_PIN_39_L3_SEL 0 # Configures MIO Pin 39 peripheral interface mapping - #(OFFSET, MASK, VALUE) (0XFF18009C, 0x000000FEU ,0x00000000U) */ - mask_write 0XFF18009C 0x000000FE 0x00000000 + #(OFFSET, MASK, VALUE) (0XFF18009C, 0x000000FEU ,0x00000010U) */ + mask_write 0XFF18009C 0x000000FE 0x00000010 # Register : MIO_PIN_40 @ 0XFF1800A0

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[1]- (TX RGMII data) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd + # [1]- (TX RGMII data) # PSU_IOU_SLCR_MIO_PIN_40_L0_SEL 0 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used # PSU_IOU_SLCR_MIO_PIN_40_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Comman - # Indicator) 2= sd1, Input, sd1_data_in[5]- (8-bit Data bus) = sd1, Output, sdio1_data_out[5]- (8-bit Data bus) 3= Not Used - # PSU_IOU_SLCR_MIO_PIN_40_L2_SEL 0 + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Com + # mand Indicator) = sd0, Output, sdio0_cmd_out- (Command Indicator) 2= sd1 + # , Input, sd1_data_in[5]- (8-bit Data bus) = sd1, Output, sdio1_data_out[ + # 5]- (8-bit Data bus) 3= Not Used + # PSU_IOU_SLCR_MIO_PIN_40_L2_SEL 2 - # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[14]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[14]- (GPIO bank 1) 1= c - # n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - # al) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc3, Input, ttc3_clk - # in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[0]- (Trace Port Databus) + # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[14]- (GPIO bank 1) 0= + # gpio1, Output, gpio_1_pin_out[14]- (GPIO bank 1) 1= can1, Output, can1_p + # hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + # 2c1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJ + # TAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc3 + # , Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmi + # tter serial output) 7= trace, Output, tracedq[0]- (Trace Port Databus) # PSU_IOU_SLCR_MIO_PIN_40_L3_SEL 0 # Configures MIO Pin 40 peripheral interface mapping - #(OFFSET, MASK, VALUE) (0XFF1800A0, 0x000000FEU ,0x00000000U) */ - mask_write 0XFF1800A0 0x000000FE 0x00000000 + #(OFFSET, MASK, VALUE) (0XFF1800A0, 0x000000FEU ,0x00000010U) */ + mask_write 0XFF1800A0 0x000000FE 0x00000010 # Register : MIO_PIN_41 @ 0XFF1800A4

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[2]- (TX RGMII data) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd + # [2]- (TX RGMII data) # PSU_IOU_SLCR_MIO_PIN_41_L0_SEL 0 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used # PSU_IOU_SLCR_MIO_PIN_41_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8 - # bit Data bus) 2= sd1, Input, sd1_data_in[6]- (8-bit Data bus) = sd1, Output, sdio1_data_out[6]- (8-bit Data bus) 3= Not Used - # PSU_IOU_SLCR_MIO_PIN_41_L2_SEL 0 + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- + # (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8-bit Data bus) 2= s + # d1, Input, sd1_data_in[6]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + # t[6]- (8-bit Data bus) 3= Not Used + # PSU_IOU_SLCR_MIO_PIN_41_L2_SEL 2 - # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[15]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[15]- (GPIO bank 1) 1= c - # n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - # l) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[ - # ]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial in - # ut) 7= trace, Output, tracedq[1]- (Trace Port Databus) + # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[15]- (GPIO bank 1) 0= + # gpio1, Output, gpio_1_pin_out[15]- (GPIO bank 1) 1= can1, Input, can1_ph + # y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + # c1, Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTA + # G TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Outpu + # t, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out + # - (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial inp + # ut) 7= trace, Output, tracedq[1]- (Trace Port Databus) # PSU_IOU_SLCR_MIO_PIN_41_L3_SEL 0 # Configures MIO Pin 41 peripheral interface mapping - #(OFFSET, MASK, VALUE) (0XFF1800A4, 0x000000FEU ,0x00000000U) */ - mask_write 0XFF1800A4 0x000000FE 0x00000000 + #(OFFSET, MASK, VALUE) (0XFF1800A4, 0x000000FEU ,0x00000010U) */ + mask_write 0XFF1800A4 0x000000FE 0x00000010 # Register : MIO_PIN_42 @ 0XFF1800A8

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[3]- (TX RGMII data) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd + # [3]- (TX RGMII data) # PSU_IOU_SLCR_MIO_PIN_42_L0_SEL 0 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used # PSU_IOU_SLCR_MIO_PIN_42_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8 - # bit Data bus) 2= sd1, Input, sd1_data_in[7]- (8-bit Data bus) = sd1, Output, sdio1_data_out[7]- (8-bit Data bus) 3= Not Used - # PSU_IOU_SLCR_MIO_PIN_42_L2_SEL 0 + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- + # (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8-bit Data bus) 2= s + # d1, Input, sd1_data_in[7]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + # t[7]- (8-bit Data bus) 3= Not Used + # PSU_IOU_SLCR_MIO_PIN_42_L2_SEL 2 - # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1) 1= c - # n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - # l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_ - # o- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outp - # t, tracedq[2]- (Trace Port Databus) + # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1) 0= + # gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1) 1= can0, Input, can0_ph + # y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + # c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + # atch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= sp + # i0, Output, spi0_so- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clo + # ck) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outpu + # t, tracedq[2]- (Trace Port Databus) # PSU_IOU_SLCR_MIO_PIN_42_L3_SEL 0 # Configures MIO Pin 42 peripheral interface mapping - #(OFFSET, MASK, VALUE) (0XFF1800A8, 0x000000FEU ,0x00000000U) */ - mask_write 0XFF1800A8 0x000000FE 0x00000000 + #(OFFSET, MASK, VALUE) (0XFF1800A8, 0x000000FEU ,0x00000010U) */ + mask_write 0XFF1800A8 0x000000FE 0x00000010 # Register : MIO_PIN_43 @ 0XFF1800AC

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ctl- (TX RGMII control) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ + # ctl- (TX RGMII control) # PSU_IOU_SLCR_MIO_PIN_43_L0_SEL 0 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used # PSU_IOU_SLCR_MIO_PIN_43_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8 - # bit Data bus) 2= sd1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used - # PSU_IOU_SLCR_MIO_PIN_43_L2_SEL 2 + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- + # (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8-bit Data bus) 2= s + # d1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used + # PSU_IOU_SLCR_MIO_PIN_43_L2_SEL 0 - # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1) 1= c - # n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - # al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, s - # i0_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o - # tput) 7= trace, Output, tracedq[3]- (Trace Port Databus) + # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1) 0= + # gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1) 1= can0, Output, can0_p + # hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + # 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + # (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) + # 4= spi0, Input, spi0_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- ( + # TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial ou + # tput) 7= trace, Output, tracedq[3]- (Trace Port Databus) # PSU_IOU_SLCR_MIO_PIN_43_L3_SEL 0 # Configures MIO Pin 43 peripheral interface mapping - #(OFFSET, MASK, VALUE) (0XFF1800AC, 0x000000FEU ,0x00000010U) */ - mask_write 0XFF1800AC 0x000000FE 0x00000010 + #(OFFSET, MASK, VALUE) (0XFF1800AC, 0x000000FEU ,0x00000000U) */ + mask_write 0XFF1800AC 0x000000FE 0x00000000 # Register : MIO_PIN_44 @ 0XFF1800B0

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_clk- (RX RGMII clock) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_c + # lk- (RX RGMII clock) # PSU_IOU_SLCR_MIO_PIN_44_L0_SEL 0 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used # PSU_IOU_SLCR_MIO_PIN_44_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8 - # bit Data bus) 2= sd1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- + # (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8-bit Data bus) 2= s + # d1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used # PSU_IOU_SLCR_MIO_PIN_44_L2_SEL 2 - # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[18]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[18]- (GPIO bank 1) 1= c - # n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - # al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, s - # i1_sclk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7 - # Not Used + # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[18]- (GPIO bank 1) 0= + # gpio1, Output, gpio_1_pin_out[18]- (GPIO bank 1) 1= can1, Output, can1_p + # hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + # 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + # Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4 + # = spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- + # (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= + # Not Used # PSU_IOU_SLCR_MIO_PIN_44_L3_SEL 0 # Configures MIO Pin 44 peripheral interface mapping @@ -9387,20 +10431,25 @@ set psu_mio_init_data { mask_write 0XFF1800B0 0x000000FE 0x00000010 # Register : MIO_PIN_45 @ 0XFF1800B4

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[0]- (RX RGMII data) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[ + # 0]- (RX RGMII data) # PSU_IOU_SLCR_MIO_PIN_45_L0_SEL 0 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used # PSU_IOU_SLCR_MIO_PIN_45_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8 - # bit Data bus) 2= sd1, Input, sdio1_cd_n- (SD card detect from connector) 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- + # (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8-bit Data bus) 2= s + # d1, Input, sdio1_cd_n- (SD card detect from connector) 3= Not Used # PSU_IOU_SLCR_MIO_PIN_45_L2_SEL 2 - # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[19]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[19]- (GPIO bank 1) 1= c - # n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - # l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= - # ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used + # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[19]- (GPIO bank 1) 0= + # gpio1, Output, gpio_1_pin_out[19]- (GPIO bank 1) 1= can1, Input, can1_ph + # y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + # c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + # (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI M + # aster Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= u + # a1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used # PSU_IOU_SLCR_MIO_PIN_45_L3_SEL 0 # Configures MIO Pin 45 peripheral interface mapping @@ -9408,20 +10457,26 @@ set psu_mio_init_data { mask_write 0XFF1800B4 0x000000FE 0x00000010 # Register : MIO_PIN_46 @ 0XFF1800B8

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[1]- (RX RGMII data) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[ + # 1]- (RX RGMII data) # PSU_IOU_SLCR_MIO_PIN_46_L0_SEL 0 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used # PSU_IOU_SLCR_MIO_PIN_46_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8 - # bit Data bus) 2= sd1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_out[0]- (8-bit Data bus) 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- + # (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8-bit Data bus) 2= s + # d1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + # t[0]- (8-bit Data bus) 3= Not Used # PSU_IOU_SLCR_MIO_PIN_46_L2_SEL 2 - # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1) 1= c - # n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - # l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= tt - # 0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used + # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1) 0= + # gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1) 1= can0, Input, can0_ph + # y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + # c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + # atch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Mast + # er Selects) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_ + # rxd- (UART receiver serial input) 7= Not Used # PSU_IOU_SLCR_MIO_PIN_46_L3_SEL 0 # Configures MIO Pin 46 peripheral interface mapping @@ -9429,21 +10484,27 @@ set psu_mio_init_data { mask_write 0XFF1800B8 0x000000FE 0x00000010 # Register : MIO_PIN_47 @ 0XFF1800BC

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[2]- (RX RGMII data) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[ + # 2]- (RX RGMII data) # PSU_IOU_SLCR_MIO_PIN_47_L0_SEL 0 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used # PSU_IOU_SLCR_MIO_PIN_47_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8 - # bit Data bus) 2= sd1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_out[1]- (8-bit Data bus) 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- + # (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8-bit Data bus) 2= s + # d1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + # t[1]- (8-bit Data bus) 3= Not Used # PSU_IOU_SLCR_MIO_PIN_47_L2_SEL 2 - # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1) 1= c - # n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - # al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi - # , Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd - # (UART transmitter serial output) 7= Not Used + # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1) 0= + # gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1) 1= can0, Output, can0_p + # hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + # 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + # (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Maste + # r Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= tt + # c0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- + # (UART transmitter serial output) 7= Not Used # PSU_IOU_SLCR_MIO_PIN_47_L3_SEL 0 # Configures MIO Pin 47 peripheral interface mapping @@ -9451,21 +10512,27 @@ set psu_mio_init_data { mask_write 0XFF1800BC 0x000000FE 0x00000010 # Register : MIO_PIN_48 @ 0XFF1800C0

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[3]- (RX RGMII data) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[ + # 3]- (RX RGMII data) # PSU_IOU_SLCR_MIO_PIN_48_L0_SEL 0 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used # PSU_IOU_SLCR_MIO_PIN_48_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8 - # bit Data bus) 2= sd1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_out[2]- (8-bit Data bus) 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- + # (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8-bit Data bus) 2= s + # d1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + # t[2]- (8-bit Data bus) 3= Not Used # PSU_IOU_SLCR_MIO_PIN_48_L2_SEL 2 - # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[22]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[22]- (GPIO bank 1) 1= c - # n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - # al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1 - # so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not U - # ed + # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[22]- (GPIO bank 1) 0= + # gpio1, Output, gpio_1_pin_out[22]- (GPIO bank 1) 1= can1, Output, can1_p + # hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + # 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + # Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= s + # pi1, Output, spi1_so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Cl + # ock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Us + # ed # PSU_IOU_SLCR_MIO_PIN_48_L3_SEL 0 # Configures MIO Pin 48 peripheral interface mapping @@ -9473,21 +10540,26 @@ set psu_mio_init_data { mask_write 0XFF1800C0 0x000000FE 0x00000010 # Register : MIO_PIN_49 @ 0XFF1800C4

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_ctl- (RX RGMII control ) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_c + # tl- (RX RGMII control ) # PSU_IOU_SLCR_MIO_PIN_49_L0_SEL 0 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used # PSU_IOU_SLCR_MIO_PIN_49_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= sd1, Input, sd1_data_in[3]- (8 - # bit Data bus) = sd1, Output, sdio1_data_out[3]- (8-bit Data bus) 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- + # (SD card bus power) 2= sd1, Input, sd1_data_in[3]- (8-bit Data bus) = sd + # 1, Output, sdio1_data_out[3]- (8-bit Data bus) 3= Not Used # PSU_IOU_SLCR_MIO_PIN_49_L2_SEL 2 - # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[23]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[23]- (GPIO bank 1) 1= c - # n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - # l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, sp - # 1_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) - # 7= Not Used + # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[23]- (GPIO bank 1) 0= + # gpio1, Output, gpio_1_pin_out[23]- (GPIO bank 1) 1= can1, Input, can1_ph + # y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + # c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + # (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4 + # = spi1, Input, spi1_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (T + # TC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) + # 7= Not Used # PSU_IOU_SLCR_MIO_PIN_49_L3_SEL 0 # Configures MIO Pin 49 peripheral interface mapping @@ -9495,20 +10567,25 @@ set psu_mio_init_data { mask_write 0XFF1800C4 0x000000FE 0x00000010 # Register : MIO_PIN_50 @ 0XFF1800C8

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- (TSU clock) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- + # (TSU clock) # PSU_IOU_SLCR_MIO_PIN_50_L0_SEL 0 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used # PSU_IOU_SLCR_MIO_PIN_50_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= sd1, Input, sd1_c - # d_in- (Command Indicator) = sd1, Output, sdio1_cmd_out- (Command Indicator) 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD ca + # rd write protect from connector) 2= sd1, Input, sd1_cmd_in- (Command Ind + # icator) = sd1, Output, sdio1_cmd_out- (Command Indicator) 3= Not Used # PSU_IOU_SLCR_MIO_PIN_50_L2_SEL 2 - # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[24]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[24]- (GPIO bank 1) 1= c - # n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - # l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= ttc2, Input, ttc2 - # clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used + # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[24]- (GPIO bank 1) 0= + # gpio1, Output, gpio_1_pin_out[24]- (GPIO bank 1) 1= can0, Input, can0_ph + # y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + # c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + # atch Dog Timer Input clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= + # ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART rece + # iver serial input) 7= Not Used # PSU_IOU_SLCR_MIO_PIN_50_L3_SEL 0 # Configures MIO Pin 50 peripheral interface mapping @@ -9516,20 +10593,25 @@ set psu_mio_init_data { mask_write 0XFF1800C8 0x000000FE 0x00000010 # Register : MIO_PIN_51 @ 0XFF1800CC

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- (TSU clock) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- + # (TSU clock) # PSU_IOU_SLCR_MIO_PIN_51_L0_SEL 0 # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used # PSU_IOU_SLCR_MIO_PIN_51_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Output, sdio1_clk_out- (SDSDIO clock) 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Output, sdi + # o1_clk_out- (SDSDIO clock) 3= Not Used # PSU_IOU_SLCR_MIO_PIN_51_L2_SEL 2 - # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[25]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[25]- (GPIO bank 1) 1= c - # n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - # al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= mdio1, Input, gem1_mdio_in- (MDIO Data) 4= mdio1, Outp - # t, gem1_mdio_out- (MDIO Data) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter - # serial output) 7= Not Used + # Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[25]- (GPIO bank 1) 0= + # gpio1, Output, gpio_1_pin_out[25]- (GPIO bank 1) 1= can0, Output, can0_p + # hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + # 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + # (Watch Dog Timer Output clock) 4= mdio1, Input, gem1_mdio_in- (MDIO Dat + # a) 4= mdio1, Output, gem1_mdio_out- (MDIO Data) 5= ttc2, Output, ttc2_wa + # ve_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter + # serial output) 7= Not Used # PSU_IOU_SLCR_MIO_PIN_51_L3_SEL 0 # Configures MIO Pin 51 peripheral interface mapping @@ -9537,20 +10619,26 @@ set psu_mio_init_data { mask_write 0XFF1800CC 0x000000FE 0x00000010 # Register : MIO_PIN_52 @ 0XFF1800D0

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_clk- (TX RGMII clock) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_ + # clk- (TX RGMII clock) # PSU_IOU_SLCR_MIO_PIN_52_L0_SEL 0 - # Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_clk_in- (ULPI Clock) + # Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_clk_i + # n- (ULPI Clock) # PSU_IOU_SLCR_MIO_PIN_52_L1_SEL 1 - # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + # Used # PSU_IOU_SLCR_MIO_PIN_52_L2_SEL 0 - # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[0]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[0]- (GPIO bank 2) 1= can - # , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa - # ) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Cloc - # ) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_ - # lk- (Trace Port Clock) + # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[0]- (GPIO bank 2) 0= g + # pio2, Output, gpio_2_pin_out[0]- (GPIO bank 2) 1= can1, Output, can1_phy + # _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + # 1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG + # TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sc + # lk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Out + # put, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_c + # lk- (Trace Port Clock) # PSU_IOU_SLCR_MIO_PIN_52_L3_SEL 0 # Configures MIO Pin 52 peripheral interface mapping @@ -9558,20 +10646,26 @@ set psu_mio_init_data { mask_write 0XFF1800D0 0x000000FE 0x00000004 # Register : MIO_PIN_53 @ 0XFF1800D4

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[0]- (TX RGMII data) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd + # [0]- (TX RGMII data) # PSU_IOU_SLCR_MIO_PIN_53_L0_SEL 0 - # Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_dir- (Data bus direction control) + # Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_dir- + # (Data bus direction control) # PSU_IOU_SLCR_MIO_PIN_53_L1_SEL 1 - # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + # Used # PSU_IOU_SLCR_MIO_PIN_53_L2_SEL 0 - # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[1]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[1]- (GPIO bank 2) 1= can - # , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal - # 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_o - # t- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control - # Signal) + # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[1]- (GPIO bank 2) 0= g + # pio2, Output, gpio_2_pin_out[1]- (GPIO bank 2) 1= can1, Input, can1_phy_ + # rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + # , Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG + # TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Ou + # tput, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART + # receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control + # Signal) # PSU_IOU_SLCR_MIO_PIN_53_L3_SEL 0 # Configures MIO Pin 53 peripheral interface mapping @@ -9579,20 +10673,26 @@ set psu_mio_init_data { mask_write 0XFF1800D4 0x000000FE 0x00000004 # Register : MIO_PIN_54 @ 0XFF1800D8

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[1]- (TX RGMII data) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd + # [1]- (TX RGMII data) # PSU_IOU_SLCR_MIO_PIN_54_L0_SEL 0 - # Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[2]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_ - # ata[2]- (ULPI data bus) + # Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + # ta[2]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[2]- (ULPI data + # bus) # PSU_IOU_SLCR_MIO_PIN_54_L1_SEL 1 - # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + # Used # PSU_IOU_SLCR_MIO_PIN_54_L2_SEL 0 - # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[2]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[2]- (GPIO bank 2) 1= can - # , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal - # 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, Input, ttc0_clk_in - # (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[0]- (Trace Port Databus) + # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[2]- (GPIO bank 2) 0= g + # pio2, Output, gpio_2_pin_out[2]- (GPIO bank 2) 1= can0, Input, can0_phy_ + # rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + # , Output, i2c0_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTAG + # TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, I + # nput, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver se + # rial input) 7= trace, Output, tracedq[0]- (Trace Port Databus) # PSU_IOU_SLCR_MIO_PIN_54_L3_SEL 0 # Configures MIO Pin 54 peripheral interface mapping @@ -9600,20 +10700,26 @@ set psu_mio_init_data { mask_write 0XFF1800D8 0x000000FE 0x00000004 # Register : MIO_PIN_55 @ 0XFF1800DC

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[2]- (TX RGMII data) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd + # [2]- (TX RGMII data) # PSU_IOU_SLCR_MIO_PIN_55_L0_SEL 0 - # Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_nxt- (Data flow control signal from the PHY) + # Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_nxt- + # (Data flow control signal from the PHY) # PSU_IOU_SLCR_MIO_PIN_55_L1_SEL 1 - # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + # Used # PSU_IOU_SLCR_MIO_PIN_55_L2_SEL 0 - # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[3]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[3]- (GPIO bank 2) 1= can - # , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa - # ) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0 - # - (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial - # output) 7= trace, Output, tracedq[1]- (Trace Port Databus) + # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[3]- (GPIO bank 2) 0= g + # pio2, Output, gpio_2_pin_out[3]- (GPIO bank 2) 1= can0, Output, can0_phy + # _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + # 0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG + # TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output + # , spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- + # (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial + # output) 7= trace, Output, tracedq[1]- (Trace Port Databus) # PSU_IOU_SLCR_MIO_PIN_55_L3_SEL 0 # Configures MIO Pin 55 peripheral interface mapping @@ -9621,21 +10727,27 @@ set psu_mio_init_data { mask_write 0XFF1800DC 0x000000FE 0x00000004 # Register : MIO_PIN_56 @ 0XFF1800E0

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[3]- (TX RGMII data) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd + # [3]- (TX RGMII data) # PSU_IOU_SLCR_MIO_PIN_56_L0_SEL 0 - # Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[0]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_ - # ata[0]- (ULPI data bus) + # Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + # ta[0]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[0]- (ULPI data + # bus) # PSU_IOU_SLCR_MIO_PIN_56_L1_SEL 1 - # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + # Used # PSU_IOU_SLCR_MIO_PIN_56_L2_SEL 0 - # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[4]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[4]- (GPIO bank 2) 1= can - # , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa - # ) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_s - # - (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, - # utput, tracedq[2]- (Trace Port Databus) + # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[4]- (GPIO bank 2) 0= g + # pio2, Output, gpio_2_pin_out[4]- (GPIO bank 2) 1= can1, Output, can1_phy + # _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + # 1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Wa + # tch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi + # 0, Output, spi0_so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Cloc + # k) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, O + # utput, tracedq[2]- (Trace Port Databus) # PSU_IOU_SLCR_MIO_PIN_56_L3_SEL 0 # Configures MIO Pin 56 peripheral interface mapping @@ -9643,21 +10755,27 @@ set psu_mio_init_data { mask_write 0XFF1800E0 0x000000FE 0x00000004 # Register : MIO_PIN_57 @ 0XFF1800E4

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_ctl- (TX RGMII control) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_ + # ctl- (TX RGMII control) # PSU_IOU_SLCR_MIO_PIN_57_L0_SEL 0 - # Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[1]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_ - # ata[1]- (ULPI data bus) + # Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + # ta[1]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[1]- (ULPI data + # bus) # PSU_IOU_SLCR_MIO_PIN_57_L1_SEL 1 - # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + # Used # PSU_IOU_SLCR_MIO_PIN_57_L2_SEL 0 - # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[5]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[5]- (GPIO bank 2) 1= can - # , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal - # 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi0 - # si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7 - # trace, Output, tracedq[3]- (Trace Port Databus) + # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[5]- (GPIO bank 2) 0= g + # pio2, Output, gpio_2_pin_out[5]- (GPIO bank 2) 1= can1, Input, can1_phy_ + # rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + # , Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (W + # atch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= + # spi0, Input, spi0_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC + # Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= + # trace, Output, tracedq[3]- (Trace Port Databus) # PSU_IOU_SLCR_MIO_PIN_57_L3_SEL 0 # Configures MIO Pin 57 peripheral interface mapping @@ -9665,20 +10783,26 @@ set psu_mio_init_data { mask_write 0XFF1800E4 0x000000FE 0x00000004 # Register : MIO_PIN_58 @ 0XFF1800E8

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_clk- (RX RGMII clock) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_c + # lk- (RX RGMII clock) # PSU_IOU_SLCR_MIO_PIN_58_L0_SEL 0 - # Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Output, usb0_ulpi_stp- (Asserted to end or interrupt transfers) + # Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Output, usb0_ulpi_stp- + # (Asserted to end or interrupt transfers) # PSU_IOU_SLCR_MIO_PIN_58_L1_SEL 1 - # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + # Used # PSU_IOU_SLCR_MIO_PIN_58_L2_SEL 0 - # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[6]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[6]- (GPIO bank 2) 1= can - # , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal - # 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1_sclk_out- (SPI Clock - # 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- - # Trace Port Databus) + # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[6]- (GPIO bank 2) 0= g + # pio2, Output, gpio_2_pin_out[6]- (GPIO bank 2) 1= can0, Input, can0_phy_ + # rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + # , Output, i2c0_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG + # TCK) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1_scl + # k_out- (SPI Clock) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Inpu + # t, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- ( + # Trace Port Databus) # PSU_IOU_SLCR_MIO_PIN_58_L3_SEL 0 # Configures MIO Pin 58 peripheral interface mapping @@ -9686,21 +10810,27 @@ set psu_mio_init_data { mask_write 0XFF1800E8 0x000000FE 0x00000004 # Register : MIO_PIN_59 @ 0XFF1800EC

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[0]- (RX RGMII data) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[ + # 0]- (RX RGMII data) # PSU_IOU_SLCR_MIO_PIN_59_L0_SEL 0 - # Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[3]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_ - # ata[3]- (ULPI data bus) + # Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + # ta[3]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[3]- (ULPI data + # bus) # PSU_IOU_SLCR_MIO_PIN_59_L1_SEL 1 - # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + # Used # PSU_IOU_SLCR_MIO_PIN_59_L2_SEL 0 - # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[7]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[7]- (GPIO bank 2) 1= can - # , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa - # ) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_ - # ut- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port - # atabus) + # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[7]- (GPIO bank 2) 0= g + # pio2, Output, gpio_2_pin_out[7]- (GPIO bank 2) 1= can0, Output, can0_phy + # _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + # 0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG + # TDI) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= ttc2, O + # utput, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UAR + # T transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port D + # atabus) # PSU_IOU_SLCR_MIO_PIN_59_L3_SEL 0 # Configures MIO Pin 59 peripheral interface mapping @@ -9708,20 +10838,26 @@ set psu_mio_init_data { mask_write 0XFF1800EC 0x000000FE 0x00000004 # Register : MIO_PIN_60 @ 0XFF1800F0

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[1]- (RX RGMII data) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[ + # 1]- (RX RGMII data) # PSU_IOU_SLCR_MIO_PIN_60_L0_SEL 0 - # Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[4]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_ - # ata[4]- (ULPI data bus) + # Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + # ta[4]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[4]- (ULPI data + # bus) # PSU_IOU_SLCR_MIO_PIN_60_L1_SEL 1 - # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + # Used # PSU_IOU_SLCR_MIO_PIN_60_L2_SEL 0 - # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[8]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[8]- (GPIO bank 2) 1= can - # , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa - # ) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc1, Input, ttc1_clk_i - # - (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus) + # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[8]- (GPIO bank 2) 0= g + # pio2, Output, gpio_2_pin_out[8]- (GPIO bank 2) 1= can1, Output, can1_phy + # _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + # 1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTA + # G TDO) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc1, + # Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitt + # er serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus) # PSU_IOU_SLCR_MIO_PIN_60_L3_SEL 0 # Configures MIO Pin 60 peripheral interface mapping @@ -9729,21 +10865,27 @@ set psu_mio_init_data { mask_write 0XFF1800F0 0x000000FE 0x00000004 # Register : MIO_PIN_61 @ 0XFF1800F4

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[2]- (RX RGMII data) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[ + # 2]- (RX RGMII data) # PSU_IOU_SLCR_MIO_PIN_61_L0_SEL 0 - # Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[5]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_ - # ata[5]- (ULPI data bus) + # Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + # ta[5]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[5]- (ULPI data + # bus) # PSU_IOU_SLCR_MIO_PIN_61_L1_SEL 1 - # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + # Used # PSU_IOU_SLCR_MIO_PIN_61_L2_SEL 0 - # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[9]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[9]- (GPIO bank 2) 1= can - # , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal - # 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, Output, spi1_n_ss_out[0] - # (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial inpu - # ) 7= trace, Output, tracedq[7]- (Trace Port Databus) + # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[9]- (GPIO bank 2) 0= g + # pio2, Output, gpio_2_pin_out[9]- (GPIO bank 2) 1= can1, Input, can1_phy_ + # rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + # , Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG + # TMS) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, Output, + # spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- + # (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input + # ) 7= trace, Output, tracedq[7]- (Trace Port Databus) # PSU_IOU_SLCR_MIO_PIN_61_L3_SEL 0 # Configures MIO Pin 61 peripheral interface mapping @@ -9751,21 +10893,27 @@ set psu_mio_init_data { mask_write 0XFF1800F4 0x000000FE 0x00000004 # Register : MIO_PIN_62 @ 0XFF1800F8

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[3]- (RX RGMII data) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[ + # 3]- (RX RGMII data) # PSU_IOU_SLCR_MIO_PIN_62_L0_SEL 0 - # Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[6]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_ - # ata[6]- (ULPI data bus) + # Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + # ta[6]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[6]- (ULPI data + # bus) # PSU_IOU_SLCR_MIO_PIN_62_L1_SEL 1 - # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + # Used # PSU_IOU_SLCR_MIO_PIN_62_L2_SEL 0 - # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[10]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[10]- (GPIO bank 2) 1= c - # n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - # l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_ - # o- (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outp - # t, tracedq[8]- (Trace Port Databus) + # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[10]- (GPIO bank 2) 0= + # gpio2, Output, gpio_2_pin_out[10]- (GPIO bank 2) 1= can0, Input, can0_ph + # y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + # c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + # atch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= sp + # i1, Output, spi1_so- (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clo + # ck) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outpu + # t, tracedq[8]- (Trace Port Databus) # PSU_IOU_SLCR_MIO_PIN_62_L3_SEL 0 # Configures MIO Pin 62 peripheral interface mapping @@ -9773,21 +10921,27 @@ set psu_mio_init_data { mask_write 0XFF1800F8 0x000000FE 0x00000004 # Register : MIO_PIN_63 @ 0XFF1800FC

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_ctl- (RX RGMII control ) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_c + # tl- (RX RGMII control ) # PSU_IOU_SLCR_MIO_PIN_63_L0_SEL 0 - # Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[7]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_ - # ata[7]- (ULPI data bus) + # Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + # ta[7]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[7]- (ULPI data + # bus) # PSU_IOU_SLCR_MIO_PIN_63_L1_SEL 1 - # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + # Used # PSU_IOU_SLCR_MIO_PIN_63_L2_SEL 0 - # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[11]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[11]- (GPIO bank 2) 1= c - # n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - # al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s - # i1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o - # tput) 7= trace, Output, tracedq[9]- (Trace Port Databus) + # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[11]- (GPIO bank 2) 0= + # gpio2, Output, gpio_2_pin_out[11]- (GPIO bank 2) 1= can0, Output, can0_p + # hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + # 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + # (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) + # 4= spi1, Input, spi1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- ( + # TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial ou + # tput) 7= trace, Output, tracedq[9]- (Trace Port Databus) # PSU_IOU_SLCR_MIO_PIN_63_L3_SEL 0 # Configures MIO Pin 63 peripheral interface mapping @@ -9795,20 +10949,26 @@ set psu_mio_init_data { mask_write 0XFF1800FC 0x000000FE 0x00000004 # Register : MIO_PIN_64 @ 0XFF180100

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_clk- (TX RGMII clock) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_ + # clk- (TX RGMII clock) # PSU_IOU_SLCR_MIO_PIN_64_L0_SEL 1 - # Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_clk_in- (ULPI Clock) + # Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_clk_i + # n- (ULPI Clock) # PSU_IOU_SLCR_MIO_PIN_64_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= Not Used 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- + # (SDSDIO clock) 2= Not Used 3= Not Used # PSU_IOU_SLCR_MIO_PIN_64_L2_SEL 0 - # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[12]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[12]- (GPIO bank 2) 1= c - # n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - # al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, s - # i0_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7 - # trace, Output, tracedq[10]- (Trace Port Databus) + # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[12]- (GPIO bank 2) 0= + # gpio2, Output, gpio_2_pin_out[12]- (GPIO bank 2) 1= can1, Output, can1_p + # hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + # 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + # Watch Dog Timer Input clock) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4 + # = spi0, Output, spi0_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- + # (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= + # trace, Output, tracedq[10]- (Trace Port Databus) # PSU_IOU_SLCR_MIO_PIN_64_L3_SEL 0 # Configures MIO Pin 64 peripheral interface mapping @@ -9816,20 +10976,26 @@ set psu_mio_init_data { mask_write 0XFF180100 0x000000FE 0x00000002 # Register : MIO_PIN_65 @ 0XFF180104

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[0]- (TX RGMII data) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd + # [0]- (TX RGMII data) # PSU_IOU_SLCR_MIO_PIN_65_L0_SEL 1 - # Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_dir- (Data bus direction control) + # Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_dir- + # (Data bus direction control) # PSU_IOU_SLCR_MIO_PIN_65_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= Not Used 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD + # card detect from connector) 2= Not Used 3= Not Used # PSU_IOU_SLCR_MIO_PIN_65_L2_SEL 0 - # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[13]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[13]- (GPIO bank 2) 1= c - # n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - # l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= - # ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trac - # dq[11]- (Trace Port Databus) + # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[13]- (GPIO bank 2) 0= + # gpio2, Output, gpio_2_pin_out[13]- (GPIO bank 2) 1= can1, Input, can1_ph + # y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + # c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + # (Watch Dog Timer Output clock) 4= spi0, Output, spi0_n_ss_out[2]- (SPI M + # aster Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= u + # a1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trace + # dq[11]- (Trace Port Databus) # PSU_IOU_SLCR_MIO_PIN_65_L3_SEL 0 # Configures MIO Pin 65 peripheral interface mapping @@ -9837,22 +11003,28 @@ set psu_mio_init_data { mask_write 0XFF180104 0x000000FE 0x00000002 # Register : MIO_PIN_66 @ 0XFF180108

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[1]- (TX RGMII data) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd + # [1]- (TX RGMII data) # PSU_IOU_SLCR_MIO_PIN_66_L0_SEL 1 - # Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[2]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_ - # ata[2]- (ULPI data bus) + # Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + # ta[2]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[2]- (ULPI data + # bus) # PSU_IOU_SLCR_MIO_PIN_66_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Comman - # Indicator) 2= Not Used 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Com + # mand Indicator) = sd0, Output, sdio0_cmd_out- (Command Indicator) 2= Not + # Used 3= Not Used # PSU_IOU_SLCR_MIO_PIN_66_L2_SEL 0 - # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[14]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[14]- (GPIO bank 2) 1= c - # n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - # l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= tt - # 2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace - # Port Databus) + # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[14]- (GPIO bank 2) 0= + # gpio2, Output, gpio_2_pin_out[14]- (GPIO bank 2) 1= can0, Input, can0_ph + # y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + # c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + # atch Dog Timer Input clock) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Mast + # er Selects) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_ + # rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace + # Port Databus) # PSU_IOU_SLCR_MIO_PIN_66_L3_SEL 0 # Configures MIO Pin 66 peripheral interface mapping @@ -9860,21 +11032,28 @@ set psu_mio_init_data { mask_write 0XFF180108 0x000000FE 0x00000002 # Register : MIO_PIN_67 @ 0XFF18010C

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[2]- (TX RGMII data) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd + # [2]- (TX RGMII data) # PSU_IOU_SLCR_MIO_PIN_67_L0_SEL 1 - # Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_nxt- (Data flow control signal from the PHY) + # Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_nxt- + # (Data flow control signal from the PHY) # PSU_IOU_SLCR_MIO_PIN_67_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8 - # bit Data bus) 2= Not Used 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- + # (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8-bit Data bus) 2= N + # ot Used 3= Not Used # PSU_IOU_SLCR_MIO_PIN_67_L2_SEL 0 - # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[15]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[15]- (GPIO bank 2) 1= c - # n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - # al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi - # , Output, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd - # (UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace Port Databus) + # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[15]- (GPIO bank 2) 0= + # gpio2, Output, gpio_2_pin_out[15]- (GPIO bank 2) 1= can0, Output, can0_p + # hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + # 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + # (Watch Dog Timer Output clock) 4= spi0, Input, spi0_n_ss_in- (SPI Maste + # r Selects) 4= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 5= tt + # c2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- + # (UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace + # Port Databus) # PSU_IOU_SLCR_MIO_PIN_67_L3_SEL 0 # Configures MIO Pin 67 peripheral interface mapping @@ -9882,22 +11061,28 @@ set psu_mio_init_data { mask_write 0XFF18010C 0x000000FE 0x00000002 # Register : MIO_PIN_68 @ 0XFF180110

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[3]- (TX RGMII data) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd + # [3]- (TX RGMII data) # PSU_IOU_SLCR_MIO_PIN_68_L0_SEL 1 - # Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[0]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_ - # ata[0]- (ULPI data bus) + # Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + # ta[0]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[0]- (ULPI data + # bus) # PSU_IOU_SLCR_MIO_PIN_68_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8 - # bit Data bus) 2= Not Used 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- + # (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8-bit Data bus) 2= N + # ot Used 3= Not Used # PSU_IOU_SLCR_MIO_PIN_68_L2_SEL 0 - # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[16]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[16]- (GPIO bank 2) 1= c - # n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - # al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0 - # so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace - # Output, tracedq[14]- (Trace Port Databus) + # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[16]- (GPIO bank 2) 0= + # gpio2, Output, gpio_2_pin_out[16]- (GPIO bank 2) 1= can1, Output, can1_p + # hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + # 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + # Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= s + # pi0, Output, spi0_so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Cl + # ock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, + # Output, tracedq[14]- (Trace Port Databus) # PSU_IOU_SLCR_MIO_PIN_68_L3_SEL 0 # Configures MIO Pin 68 peripheral interface mapping @@ -9905,22 +11090,28 @@ set psu_mio_init_data { mask_write 0XFF180110 0x000000FE 0x00000002 # Register : MIO_PIN_69 @ 0XFF180114

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_ctl- (TX RGMII control) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_ + # ctl- (TX RGMII control) # PSU_IOU_SLCR_MIO_PIN_69_L0_SEL 1 - # Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[1]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_ - # ata[1]- (ULPI data bus) + # Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + # ta[1]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[1]- (ULPI data + # bus) # PSU_IOU_SLCR_MIO_PIN_69_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8 - # bit Data bus) 2= sd1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- + # (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8-bit Data bus) 2= s + # d1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used # PSU_IOU_SLCR_MIO_PIN_69_L2_SEL 0 - # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[17]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[17]- (GPIO bank 2) 1= c - # n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - # l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, sp - # 0_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) - # 7= trace, Output, tracedq[15]- (Trace Port Databus) + # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[17]- (GPIO bank 2) 0= + # gpio2, Output, gpio_2_pin_out[17]- (GPIO bank 2) 1= can1, Input, can1_ph + # y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + # c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + # (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4 + # = spi0, Input, spi0_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (T + # TC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) + # 7= trace, Output, tracedq[15]- (Trace Port Databus) # PSU_IOU_SLCR_MIO_PIN_69_L3_SEL 0 # Configures MIO Pin 69 peripheral interface mapping @@ -9928,21 +11119,27 @@ set psu_mio_init_data { mask_write 0XFF180114 0x000000FE 0x00000002 # Register : MIO_PIN_70 @ 0XFF180118

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_clk- (RX RGMII clock) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_c + # lk- (RX RGMII clock) # PSU_IOU_SLCR_MIO_PIN_70_L0_SEL 1 - # Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Output, usb1_ulpi_stp- (Asserted to end or interrupt transfers) + # Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Output, usb1_ulpi_stp- + # (Asserted to end or interrupt transfers) # PSU_IOU_SLCR_MIO_PIN_70_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8 - # bit Data bus) 2= sd1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- + # (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8-bit Data bus) 2= s + # d1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used # PSU_IOU_SLCR_MIO_PIN_70_L2_SEL 0 - # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[18]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[18]- (GPIO bank 2) 1= c - # n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - # l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, sp - # 1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not - # sed + # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[18]- (GPIO bank 2) 0= + # gpio2, Output, gpio_2_pin_out[18]- (GPIO bank 2) 1= can0, Input, can0_ph + # y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + # c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + # atch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= + # spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- ( + # TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not U + # sed # PSU_IOU_SLCR_MIO_PIN_70_L3_SEL 0 # Configures MIO Pin 70 peripheral interface mapping @@ -9950,21 +11147,28 @@ set psu_mio_init_data { mask_write 0XFF180118 0x000000FE 0x00000002 # Register : MIO_PIN_71 @ 0XFF18011C

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[0]- (RX RGMII data) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[ + # 0]- (RX RGMII data) # PSU_IOU_SLCR_MIO_PIN_71_L0_SEL 1 - # Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[3]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_ - # ata[3]- (ULPI data bus) + # Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + # ta[3]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[3]- (ULPI data + # bus) # PSU_IOU_SLCR_MIO_PIN_71_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8 - # bit Data bus) 2= sd1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_out[0]- (8-bit Data bus) 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- + # (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8-bit Data bus) 2= s + # d1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + # t[0]- (8-bit Data bus) 3= Not Used # PSU_IOU_SLCR_MIO_PIN_71_L2_SEL 0 - # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[19]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[19]- (GPIO bank 2) 1= c - # n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - # al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5 - # ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used + # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[19]- (GPIO bank 2) 0= + # gpio2, Output, gpio_2_pin_out[19]- (GPIO bank 2) 1= can0, Output, can0_p + # hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + # 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + # (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI + # Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= + # ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used # PSU_IOU_SLCR_MIO_PIN_71_L3_SEL 0 # Configures MIO Pin 71 peripheral interface mapping @@ -9972,21 +11176,28 @@ set psu_mio_init_data { mask_write 0XFF18011C 0x000000FE 0x00000002 # Register : MIO_PIN_72 @ 0XFF180120

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[1]- (RX RGMII data) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[ + # 1]- (RX RGMII data) # PSU_IOU_SLCR_MIO_PIN_72_L0_SEL 1 - # Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[4]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_ - # ata[4]- (ULPI data bus) + # Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + # ta[4]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[4]- (ULPI data + # bus) # PSU_IOU_SLCR_MIO_PIN_72_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8 - # bit Data bus) 2= sd1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_out[1]- (8-bit Data bus) 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- + # (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8-bit Data bus) 2= s + # d1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + # t[1]- (8-bit Data bus) 3= Not Used # PSU_IOU_SLCR_MIO_PIN_72_L2_SEL 0 - # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[20]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[20]- (GPIO bank 2) 1= c - # n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - # al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= N - # t Used 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Used + # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[20]- (GPIO bank 2) 0= + # gpio2, Output, gpio_2_pin_out[20]- (GPIO bank 2) 1= can1, Output, can1_p + # hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + # 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + # Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Mas + # ter Selects) 5= Not Used 6= ua1, Output, ua1_txd- (UART transmitter seri + # al output) 7= Not Used # PSU_IOU_SLCR_MIO_PIN_72_L3_SEL 0 # Configures MIO Pin 72 peripheral interface mapping @@ -9994,21 +11205,28 @@ set psu_mio_init_data { mask_write 0XFF180120 0x000000FE 0x00000002 # Register : MIO_PIN_73 @ 0XFF180124

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[2]- (RX RGMII data) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[ + # 2]- (RX RGMII data) # PSU_IOU_SLCR_MIO_PIN_73_L0_SEL 1 - # Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_ - # ata[5]- (ULPI data bus) + # Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + # ta[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[5]- (ULPI data + # bus) # PSU_IOU_SLCR_MIO_PIN_73_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8 - # bit Data bus) 2= sd1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_out[2]- (8-bit Data bus) 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- + # (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8-bit Data bus) 2= s + # d1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + # t[2]- (8-bit Data bus) 3= Not Used # PSU_IOU_SLCR_MIO_PIN_73_L2_SEL 0 - # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[21]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[21]- (GPIO bank 2) 1= c - # n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - # l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1 - # Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= Not Used 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used + # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[21]- (GPIO bank 2) 0= + # gpio2, Output, gpio_2_pin_out[21]- (GPIO bank 2) 1= can1, Input, can1_ph + # y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + # c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + # (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master + # Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= Not + # Used 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used # PSU_IOU_SLCR_MIO_PIN_73_L3_SEL 0 # Configures MIO Pin 73 peripheral interface mapping @@ -10016,21 +11234,28 @@ set psu_mio_init_data { mask_write 0XFF180124 0x000000FE 0x00000002 # Register : MIO_PIN_74 @ 0XFF180128

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[3]- (RX RGMII data) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[ + # 3]- (RX RGMII data) # PSU_IOU_SLCR_MIO_PIN_74_L0_SEL 1 - # Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[6]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_ - # ata[6]- (ULPI data bus) + # Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + # ta[6]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[6]- (ULPI data + # bus) # PSU_IOU_SLCR_MIO_PIN_74_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8 - # bit Data bus) 2= sd1, Input, sd1_data_in[3]- (8-bit Data bus) = sd1, Output, sdio1_data_out[3]- (8-bit Data bus) 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- + # (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8-bit Data bus) 2= s + # d1, Input, sd1_data_in[3]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + # t[3]- (8-bit Data bus) 3= Not Used # PSU_IOU_SLCR_MIO_PIN_74_L2_SEL 0 - # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[22]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[22]- (GPIO bank 2) 1= c - # n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - # l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_ - # o- (MISO signal) 5= Not Used 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used + # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[22]- (GPIO bank 2) 0= + # gpio2, Output, gpio_2_pin_out[22]- (GPIO bank 2) 1= can0, Input, can0_ph + # y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + # c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + # atch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= sp + # i1, Output, spi1_so- (MISO signal) 5= Not Used 6= ua0, Input, ua0_rxd- ( + # UART receiver serial input) 7= Not Used # PSU_IOU_SLCR_MIO_PIN_74_L3_SEL 0 # Configures MIO Pin 74 peripheral interface mapping @@ -10038,21 +11263,27 @@ set psu_mio_init_data { mask_write 0XFF180128 0x000000FE 0x00000002 # Register : MIO_PIN_75 @ 0XFF18012C

- # Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_ctl- (RX RGMII control ) + # Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_c + # tl- (RX RGMII control ) # PSU_IOU_SLCR_MIO_PIN_75_L0_SEL 1 - # Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[7]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_ - # ata[7]- (ULPI data bus) + # Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + # ta[7]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[7]- (ULPI data + # bus) # PSU_IOU_SLCR_MIO_PIN_75_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= sd1, Input, sd1_cmd_in- (Comma - # d Indicator) = sd1, Output, sdio1_cmd_out- (Command Indicator) 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- + # (SD card bus power) 2= sd1, Input, sd1_cmd_in- (Command Indicator) = sd1 + # , Output, sdio1_cmd_out- (Command Indicator) 3= Not Used # PSU_IOU_SLCR_MIO_PIN_75_L2_SEL 0 - # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[23]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[23]- (GPIO bank 2) 1= c - # n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - # al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s - # i1_si- (MOSI signal) 5= Not Used 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used + # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[23]- (GPIO bank 2) 0= + # gpio2, Output, gpio_2_pin_out[23]- (GPIO bank 2) 1= can0, Output, can0_p + # hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + # 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + # (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) + # 4= spi1, Input, spi1_si- (MOSI signal) 5= Not Used 6= ua0, Output, ua0_t + # xd- (UART transmitter serial output) 7= Not Used # PSU_IOU_SLCR_MIO_PIN_75_L3_SEL 0 # Configures MIO Pin 75 peripheral interface mapping @@ -10066,14 +11297,17 @@ set psu_mio_init_data { # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used # PSU_IOU_SLCR_MIO_PIN_76_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= sd1, Output, sdio - # _clk_out- (SDSDIO clock) 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD ca + # rd write protect from connector) 2= sd1, Output, sdio1_clk_out- (SDSDIO + # clock) 3= Not Used # PSU_IOU_SLCR_MIO_PIN_76_L2_SEL 0 - # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[24]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[24]- (GPIO bank 2) 1= c - # n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - # al) 3= mdio0, Output, gem0_mdc- (MDIO Clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= mdio2, Output, gem2_mdc- (MDIO Clock - # 6= mdio3, Output, gem3_mdc- (MDIO Clock) 7= Not Used + # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[24]- (GPIO bank 2) 0= + # gpio2, Output, gpio_2_pin_out[24]- (GPIO bank 2) 1= can1, Output, can1_p + # hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + # 2c1, Output, i2c1_scl_out- (SCL signal) 3= mdio0, Output, gem0_mdc- (MDI + # O Clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= mdio2, Output, gem2 + # _mdc- (MDIO Clock) 6= mdio3, Output, gem3_mdc- (MDIO Clock) 7= Not Used # PSU_IOU_SLCR_MIO_PIN_76_L3_SEL 6 # Configures MIO Pin 76 peripheral interface mapping @@ -10087,14 +11321,19 @@ set psu_mio_init_data { # Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used # PSU_IOU_SLCR_MIO_PIN_77_L1_SEL 0 - # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Input, sdio1_cd_n- (SD card detect from connector) 3= Not Used + # Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Input, sdio + # 1_cd_n- (SD card detect from connector) 3= Not Used # PSU_IOU_SLCR_MIO_PIN_77_L2_SEL 0 - # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[25]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[25]- (GPIO bank 2) 1= c - # n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - # l) 3= mdio0, Input, gem0_mdio_in- (MDIO Data) 3= mdio0, Output, gem0_mdio_out- (MDIO Data) 4= mdio1, Input, gem1_mdio_in- (MD - # O Data) 4= mdio1, Output, gem1_mdio_out- (MDIO Data) 5= mdio2, Input, gem2_mdio_in- (MDIO Data) 5= mdio2, Output, gem2_mdio_o - # t- (MDIO Data) 6= mdio3, Input, gem3_mdio_in- (MDIO Data) 6= mdio3, Output, gem3_mdio_out- (MDIO Data) 7= Not Used + # Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[25]- (GPIO bank 2) 0= + # gpio2, Output, gpio_2_pin_out[25]- (GPIO bank 2) 1= can1, Input, can1_ph + # y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + # c1, Output, i2c1_sda_out- (SDA signal) 3= mdio0, Input, gem0_mdio_in- (M + # DIO Data) 3= mdio0, Output, gem0_mdio_out- (MDIO Data) 4= mdio1, Input, + # gem1_mdio_in- (MDIO Data) 4= mdio1, Output, gem1_mdio_out- (MDIO Data) 5 + # = mdio2, Input, gem2_mdio_in- (MDIO Data) 5= mdio2, Output, gem2_mdio_ou + # t- (MDIO Data) 6= mdio3, Input, gem3_mdio_in- (MDIO Data) 6= mdio3, Outp + # ut, gem3_mdio_out- (MDIO Data) 7= Not Used # PSU_IOU_SLCR_MIO_PIN_77_L3_SEL 6 # Configures MIO Pin 77 peripheral interface mapping @@ -10678,7 +11917,8 @@ set psu_mio_init_data { # Each bit applies to a single IO. Bit 0 for MIO[0]. # PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25 1 - # When mio_bank0_pull_enable is set, this selects pull up or pull down for MIO Bank 0 - control MIO[25:0] + # When mio_bank0_pull_enable is set, this selects pull up or pull down for + # MIO Bank 0 - control MIO[25:0] #(OFFSET, MASK, VALUE) (0XFF180144, 0x03FFFFFFU ,0x03FFFFFFU) */ mask_write 0XFF180144 0x03FFFFFF 0x03FFFFFF # Register : bank0_ctrl5 @ 0XFF180148

@@ -10761,7 +12001,8 @@ set psu_mio_init_data { # Each bit applies to a single IO. Bit 0 for MIO[0]. # PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25 1 - # When set, this enables mio_bank0_pullupdown to selects pull up or pull down for MIO Bank 0 - control MIO[25:0] + # When set, this enables mio_bank0_pullupdown to selects pull up or pull d + # own for MIO Bank 0 - control MIO[25:0] #(OFFSET, MASK, VALUE) (0XFF180148, 0x03FFFFFFU ,0x03FFFFFFU) */ mask_write 0XFF180148 0x03FFFFFF 0x03FFFFFF # Register : bank0_ctrl6 @ 0XFF18014C

@@ -11176,7 +12417,8 @@ set psu_mio_init_data { # Each bit applies to a single IO. Bit 0 for MIO[26]. # PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25 1 - # When mio_bank1_pull_enable is set, this selects pull up or pull down for MIO Bank 1 - control MIO[51:26] + # When mio_bank1_pull_enable is set, this selects pull up or pull down for + # MIO Bank 1 - control MIO[51:26] #(OFFSET, MASK, VALUE) (0XFF180160, 0x03FFFFFFU ,0x03FFFFFFU) */ mask_write 0XFF180160 0x03FFFFFF 0x03FFFFFF # Register : bank1_ctrl5 @ 0XFF180164

@@ -11259,7 +12501,8 @@ set psu_mio_init_data { # Each bit applies to a single IO. Bit 0 for MIO[26]. # PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25 1 - # When set, this enables mio_bank1_pullupdown to selects pull up or pull down for MIO Bank 1 - control MIO[51:26] + # When set, this enables mio_bank1_pullupdown to selects pull up or pull d + # own for MIO Bank 1 - control MIO[51:26] #(OFFSET, MASK, VALUE) (0XFF180164, 0x03FFFFFFU ,0x03FFFFFFU) */ mask_write 0XFF180164 0x03FFFFFF 0x03FFFFFF # Register : bank1_ctrl6 @ 0XFF180168

@@ -11674,7 +12917,8 @@ set psu_mio_init_data { # Each bit applies to a single IO. Bit 0 for MIO[52]. # PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25 1 - # When mio_bank2_pull_enable is set, this selects pull up or pull down for MIO Bank 2 - control MIO[77:52] + # When mio_bank2_pull_enable is set, this selects pull up or pull down for + # MIO Bank 2 - control MIO[77:52] #(OFFSET, MASK, VALUE) (0XFF18017C, 0x03FFFFFFU ,0x03FFFFFFU) */ mask_write 0XFF18017C 0x03FFFFFF 0x03FFFFFF # Register : bank2_ctrl5 @ 0XFF180180

@@ -11757,7 +13001,8 @@ set psu_mio_init_data { # Each bit applies to a single IO. Bit 0 for MIO[52]. # PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25 1 - # When set, this enables mio_bank2_pullupdown to selects pull up or pull down for MIO Bank 2 - control MIO[77:52] + # When set, this enables mio_bank2_pullupdown to selects pull up or pull d + # own for MIO Bank 2 - control MIO[77:52] #(OFFSET, MASK, VALUE) (0XFF180180, 0x03FFFFFFU ,0x03FFFFFFU) */ mask_write 0XFF180180 0x03FFFFFF 0x03FFFFFF # Register : bank2_ctrl6 @ 0XFF180184

@@ -11846,20 +13091,24 @@ set psu_mio_init_data { # : LOOPBACK # Register : MIO_LOOPBACK @ 0XFF180200

- # I2C Loopback Control. 0 = Connect I2C inputs according to MIO mapping. 1 = Loop I2C 0 outputs to I2C 1 inputs, and I2C 1 outp - # ts to I2C 0 inputs. + # I2C Loopback Control. 0 = Connect I2C inputs according to MIO mapping. 1 + # = Loop I2C 0 outputs to I2C 1 inputs, and I2C 1 outputs to I2C 0 inputs + # . # PSU_IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1 0 - # CAN Loopback Control. 0 = Connect CAN inputs according to MIO mapping. 1 = Loop CAN 0 Tx to CAN 1 Rx, and CAN 1 Tx to CAN 0 R - # . + # CAN Loopback Control. 0 = Connect CAN inputs according to MIO mapping. 1 + # = Loop CAN 0 Tx to CAN 1 Rx, and CAN 1 Tx to CAN 0 Rx. # PSU_IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1 0 - # UART Loopback Control. 0 = Connect UART inputs according to MIO mapping. 1 = Loop UART 0 outputs to UART 1 inputs, and UART 1 - # outputs to UART 0 inputs. RXD/TXD cross-connected. RTS/CTS cross-connected. DSR, DTR, DCD and RI not used. + # UART Loopback Control. 0 = Connect UART inputs according to MIO mapping. + # 1 = Loop UART 0 outputs to UART 1 inputs, and UART 1 outputs to UART 0 + # inputs. RXD/TXD cross-connected. RTS/CTS cross-connected. DSR, DTR, DCD + # and RI not used. # PSU_IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1 0 - # SPI Loopback Control. 0 = Connect SPI inputs according to MIO mapping. 1 = Loop SPI 0 outputs to SPI 1 inputs, and SPI 1 outp - # ts to SPI 0 inputs. The other SPI core will appear on the LS Slave Select. + # SPI Loopback Control. 0 = Connect SPI inputs according to MIO mapping. 1 + # = Loop SPI 0 outputs to SPI 1 inputs, and SPI 1 outputs to SPI 0 inputs + # . The other SPI core will appear on the LS Slave Select. # PSU_IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1 0 # Loopback function within MIO @@ -11868,59 +13117,7 @@ set psu_mio_init_data { } set psu_peripherals_init_data { - # : RESET BLOCKS - # : TIMESTAMP - # Register : RST_LPD_IOU2 @ 0XFF5E0238

- - # Block level reset - # PSU_CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET 0 - - # Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset. - #(OFFSET, MASK, VALUE) (0XFF5E0238, 0x00100000U ,0x00000000U) */ - mask_write 0XFF5E0238 0x00100000 0x00000000 - # : ENET - # Register : RST_LPD_IOU0 @ 0XFF5E0230

- - # GEM 3 reset - # PSU_CRL_APB_RST_LPD_IOU0_GEM3_RESET 0 - - # Software controlled reset for the GEMs - #(OFFSET, MASK, VALUE) (0XFF5E0230, 0x00000008U ,0x00000000U) */ - mask_write 0XFF5E0230 0x00000008 0x00000000 - # : QSPI - # Register : RST_LPD_IOU2 @ 0XFF5E0238

- - # Block level reset - # PSU_CRL_APB_RST_LPD_IOU2_QSPI_RESET 0 - - # Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset. - #(OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000001U ,0x00000000U) */ - mask_write 0XFF5E0238 0x00000001 0x00000000 - # : QSPI TAP DELAY - # Register : IOU_TAPDLY_BYPASS @ 0XFF180390

- - # 0: Do not by pass the tap delays on the Rx clock signal of LQSPI 1: Bypass the Tap delay on the Rx clock signal of LQSPI - # PSU_IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX 1 - - # IOU tap delay bypass for the LQSPI and NAND controllers - #(OFFSET, MASK, VALUE) (0XFF180390, 0x00000004U ,0x00000004U) */ - mask_write 0XFF180390 0x00000004 0x00000004 - # : NAND - # : USB - # Register : RST_LPD_TOP @ 0XFF5E023C

- - # USB 0 reset for control registers - # PSU_CRL_APB_RST_LPD_TOP_USB0_APB_RESET 0 - - # USB 0 sleep circuit reset - # PSU_CRL_APB_RST_LPD_TOP_USB0_HIBERRESET 0 - - # USB 0 reset - # PSU_CRL_APB_RST_LPD_TOP_USB0_CORERESET 0 - - # Software control register for the LPD block. - #(OFFSET, MASK, VALUE) (0XFF5E023C, 0x00000540U ,0x00000000U) */ - mask_write 0XFF5E023C 0x00000540 0x00000000 + # : COHERENCY # : FPD RESET # Register : RST_FPD_TOP @ 0XFD1A0100

@@ -11960,13 +13157,123 @@ set psu_peripherals_init_data { # FPD Block level software controlled reset #(OFFSET, MASK, VALUE) (0XFD1A0100, 0x000F807EU ,0x00000000U) */ mask_write 0XFD1A0100 0x000F807E 0x00000000 + # : RESET BLOCKS + # : TIMESTAMP + # Register : RST_LPD_IOU2 @ 0XFF5E0238

+ + # Block level reset + # PSU_CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET 0 + + # Block level reset + # PSU_CRL_APB_RST_LPD_IOU2_IOU_CC_RESET 0 + + # Block level reset + # PSU_CRL_APB_RST_LPD_IOU2_ADMA_RESET 0 + + # Software control register for the IOU block. Each bit will cause a singl + # erperipheral or part of the peripheral to be reset. + #(OFFSET, MASK, VALUE) (0XFF5E0238, 0x001A0000U ,0x00000000U) */ + mask_write 0XFF5E0238 0x001A0000 0x00000000 + # Register : RST_LPD_TOP @ 0XFF5E023C

+ + # Reset entire full power domain. + # PSU_CRL_APB_RST_LPD_TOP_FPD_RESET 0 + + # LPD SWDT + # PSU_CRL_APB_RST_LPD_TOP_LPD_SWDT_RESET 0 + + # Sysmonitor reset + # PSU_CRL_APB_RST_LPD_TOP_SYSMON_RESET 0 + + # Real Time Clock reset + # PSU_CRL_APB_RST_LPD_TOP_RTC_RESET 0 + + # APM reset + # PSU_CRL_APB_RST_LPD_TOP_APM_RESET 0 + + # IPI reset + # PSU_CRL_APB_RST_LPD_TOP_IPI_RESET 0 + + # reset entire RPU power island + # PSU_CRL_APB_RST_LPD_TOP_RPU_PGE_RESET 0 + + # reset ocm + # PSU_CRL_APB_RST_LPD_TOP_OCM_RESET 0 + + # Software control register for the LPD block. + #(OFFSET, MASK, VALUE) (0XFF5E023C, 0x0093C018U ,0x00000000U) */ + mask_write 0XFF5E023C 0x0093C018 0x00000000 + # : ENET + # Register : RST_LPD_IOU0 @ 0XFF5E0230

+ + # GEM 3 reset + # PSU_CRL_APB_RST_LPD_IOU0_GEM3_RESET 0 + + # Software controlled reset for the GEMs + #(OFFSET, MASK, VALUE) (0XFF5E0230, 0x00000008U ,0x00000000U) */ + mask_write 0XFF5E0230 0x00000008 0x00000000 + # : QSPI + # Register : RST_LPD_IOU2 @ 0XFF5E0238

+ + # Block level reset + # PSU_CRL_APB_RST_LPD_IOU2_QSPI_RESET 0 + + # Software control register for the IOU block. Each bit will cause a singl + # erperipheral or part of the peripheral to be reset. + #(OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000001U ,0x00000000U) */ + mask_write 0XFF5E0238 0x00000001 0x00000000 + # : QSPI TAP DELAY + # Register : IOU_TAPDLY_BYPASS @ 0XFF180390

+ + # 0: Do not by pass the tap delays on the Rx clock signal of LQSPI 1: Bypa + # ss the Tap delay on the Rx clock signal of LQSPI + # PSU_IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX 1 + + # IOU tap delay bypass for the LQSPI and NAND controllers + #(OFFSET, MASK, VALUE) (0XFF180390, 0x00000004U ,0x00000004U) */ + mask_write 0XFF180390 0x00000004 0x00000004 + # : NAND + # : USB + # Register : RST_LPD_TOP @ 0XFF5E023C

+ + # USB 0 reset for control registers + # PSU_CRL_APB_RST_LPD_TOP_USB0_APB_RESET 0 + + # USB 0 sleep circuit reset + # PSU_CRL_APB_RST_LPD_TOP_USB0_HIBERRESET 0 + + # USB 0 reset + # PSU_CRL_APB_RST_LPD_TOP_USB0_CORERESET 0 + + # Software control register for the LPD block. + #(OFFSET, MASK, VALUE) (0XFF5E023C, 0x00000540U ,0x00000000U) */ + mask_write 0XFF5E023C 0x00000540 0x00000000 + # : USB0 PIPE POWER PRESENT + # Register : fpd_power_prsnt @ 0XFF9D0080

+ + # This bit is used to choose between PIPE power present and 1'b1 + # PSU_USB3_0_FPD_POWER_PRSNT_OPTION 0X1 + + # fpd_power_prsnt + #(OFFSET, MASK, VALUE) (0XFF9D0080, 0x00000001U ,0x00000001U) */ + mask_write 0XFF9D0080 0x00000001 0x00000001 + # Register : fpd_pipe_clk @ 0XFF9D007C

+ + # This bit is used to choose between PIPE clock coming from SerDes and the + # suspend clk + # PSU_USB3_0_FPD_PIPE_CLK_OPTION 0x0 + + # fpd_pipe_clk + #(OFFSET, MASK, VALUE) (0XFF9D007C, 0x00000001U ,0x00000000U) */ + mask_write 0XFF9D007C 0x00000001 0x00000000 # : SD # Register : RST_LPD_IOU2 @ 0XFF5E0238

# Block level reset # PSU_CRL_APB_RST_LPD_IOU2_SDIO1_RESET 0 - # Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset. + # Software control register for the IOU block. Each bit will cause a singl + # erperipheral or part of the peripheral to be reset. #(OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000040U ,0x00000000U) */ mask_write 0XFF5E0238 0x00000040 0x00000000 # Register : CTRL_REG_SD @ 0XFF180310

@@ -11979,12 +13286,12 @@ set psu_peripherals_init_data { mask_write 0XFF180310 0x00008000 0x00000000 # Register : SD_CONFIG_REG2 @ 0XFF180320

- # Should be set based on the final product usage 00 - Removable SCard Slot 01 - Embedded Slot for One Device 10 - Shared Bus Sl - # t 11 - Reserved + # Should be set based on the final product usage 00 - Removable SCard Slot + # 01 - Embedded Slot for One Device 10 - Shared Bus Slot 11 - Reserved # PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE 0 # 1.8V Support 1: 1.8V supported 0: 1.8V not supported support - # PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V 0 + # PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V 1 # 3.0V Support 1: 3.0V supported 0: 3.0V not supported support # PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V 0 @@ -11993,23 +13300,36 @@ set psu_peripherals_init_data { # PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V 1 # SD Config Register 2 - #(OFFSET, MASK, VALUE) (0XFF180320, 0x33800000U ,0x00800000U) */ - mask_write 0XFF180320 0x33800000 0x00800000 + #(OFFSET, MASK, VALUE) (0XFF180320, 0x33800000U ,0x02800000U) */ + mask_write 0XFF180320 0x33800000 0x02800000 # : SD1 BASE CLOCK # Register : SD_CONFIG_REG1 @ 0XFF18031C

# Base Clock Frequency for SD Clock. This is the frequency of the xin_clk. - # PSU_IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK 0xc7 + # PSU_IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK 0xc8 + + # Configures the Number of Taps (Phases) of the rxclk_in that is supported + # . + # PSU_IOU_SLCR_SD_CONFIG_REG1_SD1_TUNIGCOUNT 0x28 # SD Config Register 1 - #(OFFSET, MASK, VALUE) (0XFF18031C, 0x7F800000U ,0x63800000U) */ - mask_write 0XFF18031C 0x7F800000 0x63800000 + #(OFFSET, MASK, VALUE) (0XFF18031C, 0x7FFE0000U ,0x64500000U) */ + mask_write 0XFF18031C 0x7FFE0000 0x64500000 + # Register : SD_DLL_CTRL @ 0XFF180358

+ + # Reserved. + # PSU_IOU_SLCR_SD_DLL_CTRL_RESERVED 1 + + # SDIO status register + #(OFFSET, MASK, VALUE) (0XFF180358, 0x00000008U ,0x00000008U) */ + mask_write 0XFF180358 0x00000008 0x00000008 # : SD1 RETUNER # Register : SD_CONFIG_REG3 @ 0XFF180324

- # This is the Timer Count for Re-Tuning Timer for Re-Tuning Mode 1 to 3. Setting to 4'b0 disables Re-Tuning Timer. 0h - Get inf - # rmation via other source 1h = 1 seconds 2h = 2 seconds 3h = 4 seconds 4h = 8 seconds -- n = 2(n-1) seconds -- Bh = 1024 secon - # s Fh - Ch = Reserved + # This is the Timer Count for Re-Tuning Timer for Re-Tuning Mode 1 to 3. S + # etting to 4'b0 disables Re-Tuning Timer. 0h - Get information via other + # source 1h = 1 seconds 2h = 2 seconds 3h = 4 seconds 4h = 8 seconds -- n + # = 2(n-1) seconds -- Bh = 1024 seconds Fh - Ch = Reserved # PSU_IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR 0X0 # SD Config Register 3 @@ -12021,7 +13341,8 @@ set psu_peripherals_init_data { # Block level reset # PSU_CRL_APB_RST_LPD_IOU2_CAN1_RESET 0 - # Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset. + # Software control register for the IOU block. Each bit will cause a singl + # erperipheral or part of the peripheral to be reset. #(OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000100U ,0x00000000U) */ mask_write 0XFF5E0238 0x00000100 0x00000000 # : I2C @@ -12033,7 +13354,8 @@ set psu_peripherals_init_data { # Block level reset # PSU_CRL_APB_RST_LPD_IOU2_I2C1_RESET 0 - # Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset. + # Software control register for the IOU block. Each bit will cause a singl + # erperipheral or part of the peripheral to be reset. #(OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000600U ,0x00000000U) */ mask_write 0XFF5E0238 0x00000600 0x00000000 # : SWDT @@ -12042,7 +13364,8 @@ set psu_peripherals_init_data { # Block level reset # PSU_CRL_APB_RST_LPD_IOU2_SWDT_RESET 0 - # Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset. + # Software control register for the IOU block. Each bit will cause a singl + # erperipheral or part of the peripheral to be reset. #(OFFSET, MASK, VALUE) (0XFF5E0238, 0x00008000U ,0x00000000U) */ mask_write 0XFF5E0238 0x00008000 0x00000000 # : SPI @@ -12061,7 +13384,8 @@ set psu_peripherals_init_data { # Block level reset # PSU_CRL_APB_RST_LPD_IOU2_TTC3_RESET 0 - # Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset. + # Software control register for the IOU block. Each bit will cause a singl + # erperipheral or part of the peripheral to be reset. #(OFFSET, MASK, VALUE) (0XFF5E0238, 0x00007800U ,0x00000000U) */ mask_write 0XFF5E0238 0x00007800 0x00000000 # : UART @@ -12073,7 +13397,8 @@ set psu_peripherals_init_data { # Block level reset # PSU_CRL_APB_RST_LPD_IOU2_UART1_RESET 0 - # Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset. + # Software control register for the IOU block. Each bit will cause a singl + # erperipheral or part of the peripheral to be reset. #(OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000006U ,0x00000000U) */ mask_write 0XFF5E0238 0x00000006 0x00000000 # : UART BAUD RATE @@ -12087,7 +13412,8 @@ set psu_peripherals_init_data { mask_write 0XFF000034 0x000000FF 0x00000005 # Register : Baud_rate_gen_reg0 @ 0XFF000018

- # Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample + # Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor + # bypass (baud_sample = sel_clk) 2 - 65535: baud_sample # PSU_UART0_BAUD_RATE_GEN_REG0_CD 0x8f # Baud Rate Generator Register. @@ -12095,36 +13421,43 @@ set psu_peripherals_init_data { mask_write 0XFF000018 0x0000FFFF 0x0000008F # Register : Control_reg0 @ 0XFF000000

- # Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a - # high level during 12 bit periods. It can be set regardless of the value of STTBRK. + # Stop transmitter break: 0: no affect 1: stop transmission of the break a + # fter a minimum of one character length and transmit a high level during + # 12 bit periods. It can be set regardless of the value of STTBRK. # PSU_UART0_CONTROL_REG0_STPBRK 0x0 - # Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the - # transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high. + # Start transmitter break: 0: no affect 1: start to transmit a break after + # the characters currently present in the FIFO and the transmit shift reg + # ister have been transmitted. It can only be set if STPBRK (Stop transmit + # ter break) is not high. # PSU_UART0_CONTROL_REG0_STTBRK 0x0 - # Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has co - # pleted. + # Restart receiver timeout counter: 1: receiver timeout counter is restart + # ed. This bit is self clearing once the restart has completed. # PSU_UART0_CONTROL_REG0_RSTTO 0x0 # Transmit disable: 0: enable transmitter 1: disable transmitter # PSU_UART0_CONTROL_REG0_TXDIS 0x0 - # Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0. + # Transmit enable: 0: disable transmitter 1: enable transmitter, provided + # the TXDIS field is set to 0. # PSU_UART0_CONTROL_REG0_TXEN 0x1 # Receive disable: 0: enable 1: disable, regardless of the value of RXEN # PSU_UART0_CONTROL_REG0_RXDIS 0x0 - # Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero. + # Receive enable: 0: disable 1: enable When set to one, the receiver logic + # is enabled, provided the RXDIS field is set to zero. # PSU_UART0_CONTROL_REG0_RXEN 0x1 - # Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded Thi - # bit is self clearing once the reset has completed. + # Software reset for Tx data path: 0: no affect 1: transmitter logic is re + # set and all pending transmitter data is discarded This bit is self clear + # ing once the reset has completed. # PSU_UART0_CONTROL_REG0_TXRES 0x1 - # Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit - # is self clearing once the reset has completed. + # Software reset for Rx data path: 0: no affect 1: receiver logic is reset + # and all pending receiver data is discarded. This bit is self clearing o + # nce the reset has completed. # PSU_UART0_CONTROL_REG0_RXRES 0x1 # UART Control Register @@ -12132,22 +13465,28 @@ set psu_peripherals_init_data { mask_write 0XFF000000 0x000001FF 0x00000017 # Register : mode_reg0 @ 0XFF000004

- # Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback + # Channel mode: Defines the mode of operation of the UART. 00: normal 01: + # automatic echo 10: local loopback 11: remote loopback # PSU_UART0_MODE_REG0_CHMODE 0x0 - # Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5 - # stop bits 10: 2 stop bits 11: reserved + # Number of stop bits: Defines the number of stop bits to detect on receiv + # e and to generate on transmit. 00: 1 stop bit 01: 1.5 stop bits 10: 2 st + # op bits 11: reserved # PSU_UART0_MODE_REG0_NBSTOP 0x0 - # Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity - # 01: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity + # Parity type select: Defines the expected parity to check on receive and + # the parity to generate on transmit. 000: even parity 001: odd parity 010 + # : forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no pari + # ty # PSU_UART0_MODE_REG0_PAR 0x4 - # Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits + # Character length select: Defines the number of bits in each character. 1 + # 1: 6 bits 10: 7 bits 0x: 8 bits # PSU_UART0_MODE_REG0_CHRL 0x0 - # Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock - # source is uart_ref_clk 1: clock source is uart_ref_clk/8 + # Clock source select: This field defines whether a pre-scalar of 8 is app + # lied to the baud rate generator input clock. 0: clock source is uart_ref + # _clk 1: clock source is uart_ref_clk/8 # PSU_UART0_MODE_REG0_CLKS 0x0 # UART Mode Register @@ -12163,7 +13502,8 @@ set psu_peripherals_init_data { mask_write 0XFF010034 0x000000FF 0x00000005 # Register : Baud_rate_gen_reg0 @ 0XFF010018

- # Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample + # Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor + # bypass (baud_sample = sel_clk) 2 - 65535: baud_sample # PSU_UART1_BAUD_RATE_GEN_REG0_CD 0x8f # Baud Rate Generator Register. @@ -12171,36 +13511,43 @@ set psu_peripherals_init_data { mask_write 0XFF010018 0x0000FFFF 0x0000008F # Register : Control_reg0 @ 0XFF010000

- # Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a - # high level during 12 bit periods. It can be set regardless of the value of STTBRK. + # Stop transmitter break: 0: no affect 1: stop transmission of the break a + # fter a minimum of one character length and transmit a high level during + # 12 bit periods. It can be set regardless of the value of STTBRK. # PSU_UART1_CONTROL_REG0_STPBRK 0x0 - # Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the - # transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high. + # Start transmitter break: 0: no affect 1: start to transmit a break after + # the characters currently present in the FIFO and the transmit shift reg + # ister have been transmitted. It can only be set if STPBRK (Stop transmit + # ter break) is not high. # PSU_UART1_CONTROL_REG0_STTBRK 0x0 - # Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has co - # pleted. + # Restart receiver timeout counter: 1: receiver timeout counter is restart + # ed. This bit is self clearing once the restart has completed. # PSU_UART1_CONTROL_REG0_RSTTO 0x0 # Transmit disable: 0: enable transmitter 1: disable transmitter # PSU_UART1_CONTROL_REG0_TXDIS 0x0 - # Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0. + # Transmit enable: 0: disable transmitter 1: enable transmitter, provided + # the TXDIS field is set to 0. # PSU_UART1_CONTROL_REG0_TXEN 0x1 # Receive disable: 0: enable 1: disable, regardless of the value of RXEN # PSU_UART1_CONTROL_REG0_RXDIS 0x0 - # Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero. + # Receive enable: 0: disable 1: enable When set to one, the receiver logic + # is enabled, provided the RXDIS field is set to zero. # PSU_UART1_CONTROL_REG0_RXEN 0x1 - # Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded Thi - # bit is self clearing once the reset has completed. + # Software reset for Tx data path: 0: no affect 1: transmitter logic is re + # set and all pending transmitter data is discarded This bit is self clear + # ing once the reset has completed. # PSU_UART1_CONTROL_REG0_TXRES 0x1 - # Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit - # is self clearing once the reset has completed. + # Software reset for Rx data path: 0: no affect 1: receiver logic is reset + # and all pending receiver data is discarded. This bit is self clearing o + # nce the reset has completed. # PSU_UART1_CONTROL_REG0_RXRES 0x1 # UART Control Register @@ -12208,28 +13555,43 @@ set psu_peripherals_init_data { mask_write 0XFF010000 0x000001FF 0x00000017 # Register : mode_reg0 @ 0XFF010004

- # Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback + # Channel mode: Defines the mode of operation of the UART. 00: normal 01: + # automatic echo 10: local loopback 11: remote loopback # PSU_UART1_MODE_REG0_CHMODE 0x0 - # Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5 - # stop bits 10: 2 stop bits 11: reserved + # Number of stop bits: Defines the number of stop bits to detect on receiv + # e and to generate on transmit. 00: 1 stop bit 01: 1.5 stop bits 10: 2 st + # op bits 11: reserved # PSU_UART1_MODE_REG0_NBSTOP 0x0 - # Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity - # 01: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity + # Parity type select: Defines the expected parity to check on receive and + # the parity to generate on transmit. 000: even parity 001: odd parity 010 + # : forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no pari + # ty # PSU_UART1_MODE_REG0_PAR 0x4 - # Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits + # Character length select: Defines the number of bits in each character. 1 + # 1: 6 bits 10: 7 bits 0x: 8 bits # PSU_UART1_MODE_REG0_CHRL 0x0 - # Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock - # source is uart_ref_clk 1: clock source is uart_ref_clk/8 + # Clock source select: This field defines whether a pre-scalar of 8 is app + # lied to the baud rate generator input clock. 0: clock source is uart_ref + # _clk 1: clock source is uart_ref_clk/8 # PSU_UART1_MODE_REG0_CLKS 0x0 # UART Mode Register #(OFFSET, MASK, VALUE) (0XFF010004, 0x000003FFU ,0x00000020U) */ mask_write 0XFF010004 0x000003FF 0x00000020 # : GPIO + # Register : RST_LPD_IOU2 @ 0XFF5E0238

+ + # Block level reset + # PSU_CRL_APB_RST_LPD_IOU2_GPIO_RESET 0 + + # Software control register for the IOU block. Each bit will cause a singl + # erperipheral or part of the peripheral to be reset. + #(OFFSET, MASK, VALUE) (0XFF5E0238, 0x00040000U ,0x00000000U) */ + mask_write 0XFF5E0238 0x00040000 0x00000000 # : ADMA TZ # Register : slcr_adma @ 0XFF4B0024

@@ -12286,7 +13648,6 @@ set psu_peripherals_init_data { #(OFFSET, MASK, VALUE) (0XFFCA5000, 0x00001FFFU ,0x00000000U) */ mask_write 0XFFCA5000 0x00001FFF 0x00000000 # : CSU TAMPER RESPONSE - # : AFIFM INTERFACE WIDTH # : CPU QOS DEFAULT # Register : ACE_CTRL @ 0XFD5C0060

@@ -12302,10 +13663,12 @@ set psu_peripherals_init_data { # : ENABLES RTC SWITCH TO BATTERY WHEN VCC_PSAUX IS NOT AVAILABLE # Register : CONTROL @ 0XFFA60040

- # Enables the RTC. By writing a 0 to this bit, RTC will be powered off and the only module that potentially draws current from - # he battery will be BBRAM. The value read through this bit does not necessarily reflect whether RTC is enabled or not. It is e - # pected that RTC is enabled every time it is being configured. If RTC is not used in the design, FSBL will disable it by writi - # g a 0 to this bit. + # Enables the RTC. By writing a 0 to this bit, RTC will be powered off and + # the only module that potentially draws current from the battery will be + # BBRAM. The value read through this bit does not necessarily reflect whe + # ther RTC is enabled or not. It is expected that RTC is enabled every tim + # e it is being configured. If RTC is not used in the design, FSBL will di + # sable it by writing a 0 to this bit. # PSU_RTC_CONTROL_BATTERY_DISABLE 0X1 # This register controls various functionalities within the RTC @@ -12314,22 +13677,89 @@ set psu_peripherals_init_data { # : TIMESTAMP COUNTER # Register : base_frequency_ID_register @ 0XFF260020

- # Frequency in number of ticks per second. Valid range from 10 MHz to 100 MHz. - # PSU_IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ 0x5f5e100 + # Frequency in number of ticks per second. Valid range from 10 MHz to 100 + # MHz. + # PSU_IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ 0x5f5b9f0 - # Program this register to match the clock frequency of the timestamp generator, in ticks per second. For example, for a 50 MHz - # clock, program 0x02FAF080. This register is not accessible to the read-only programming interface. - #(OFFSET, MASK, VALUE) (0XFF260020, 0xFFFFFFFFU ,0x05F5E100U) */ - mask_write 0XFF260020 0xFFFFFFFF 0x05F5E100 + # Program this register to match the clock frequency of the timestamp gene + # rator, in ticks per second. For example, for a 50 MHz clock, program 0x0 + # 2FAF080. This register is not accessible to the read-only programming in + # terface. + #(OFFSET, MASK, VALUE) (0XFF260020, 0xFFFFFFFFU ,0x05F5B9F0U) */ + mask_write 0XFF260020 0xFFFFFFFF 0x05F5B9F0 # Register : counter_control_register @ 0XFF260000

- # Enable 0: The counter is disabled and not incrementing. 1: The counter is enabled and is incrementing. + # Enable 0: The counter is disabled and not incrementing. 1: The counter i + # s enabled and is incrementing. # PSU_IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN 0x1 - # Controls the counter increments. This register is not accessible to the read-only programming interface. + # Controls the counter increments. This register is not accessible to the + # read-only programming interface. #(OFFSET, MASK, VALUE) (0XFF260000, 0x00000001U ,0x00000001U) */ mask_write 0XFF260000 0x00000001 0x00000001 # : TTC SRC SELECT + # : PCIE GPIO RESET + # : PCIE RESET + # : DIR MODE BANK 0 + # : DIR MODE BANK 1 + # Register : DIRM_1 @ 0XFF0A0244

+ + # Operation is the same as DIRM_0[DIRECTION_0] + # PSU_GPIO_DIRM_1_DIRECTION_1 0x20 + + # Direction mode (GPIO Bank1, MIO) + #(OFFSET, MASK, VALUE) (0XFF0A0244, 0x03FFFFFFU ,0x00000020U) */ + mask_write 0XFF0A0244 0x03FFFFFF 0x00000020 + # : DIR MODE BANK 2 + # : OUTPUT ENABLE BANK 0 + # : OUTPUT ENABLE BANK 1 + # Register : OEN_1 @ 0XFF0A0248

+ + # Operation is the same as OEN_0[OP_ENABLE_0] + # PSU_GPIO_OEN_1_OP_ENABLE_1 0x20 + + # Output enable (GPIO Bank1, MIO) + #(OFFSET, MASK, VALUE) (0XFF0A0248, 0x03FFFFFFU ,0x00000020U) */ + mask_write 0XFF0A0248 0x03FFFFFF 0x00000020 + # : OUTPUT ENABLE BANK 2 + # : MASK_DATA_0_LSW LOW BANK [15:0] + # : MASK_DATA_0_MSW LOW BANK [25:16] + # : MASK_DATA_1_LSW LOW BANK [41:26] + # Register : MASK_DATA_1_LSW @ 0XFF0A0008

+ + # Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW] + # PSU_GPIO_MASK_DATA_1_LSW_MASK_1_LSW 0xffdf + + # Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW] + # PSU_GPIO_MASK_DATA_1_LSW_DATA_1_LSW 0x20 + + # Maskable Output Data (GPIO Bank1, MIO, Lower 16bits) + #(OFFSET, MASK, VALUE) (0XFF0A0008, 0xFFFFFFFFU ,0xFFDF0020U) */ + mask_write 0XFF0A0008 0xFFFFFFFF 0xFFDF0020 + # : MASK_DATA_1_MSW HIGH BANK [51:42] + # : MASK_DATA_1_LSW HIGH BANK [67:52] + # : MASK_DATA_1_LSW HIGH BANK [77:68] + # : ADD 1 MS DELAY + mask_delay 0x00000000 1 + # : MASK_DATA_0_LSW LOW BANK [15:0] + # : MASK_DATA_0_MSW LOW BANK [25:16] + # : MASK_DATA_1_LSW LOW BANK [41:26] + # Register : MASK_DATA_1_LSW @ 0XFF0A0008

+ + # Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW] + # PSU_GPIO_MASK_DATA_1_LSW_MASK_1_LSW 0xffdf + + # Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW] + # PSU_GPIO_MASK_DATA_1_LSW_DATA_1_LSW 0x0 + + # Maskable Output Data (GPIO Bank1, MIO, Lower 16bits) + #(OFFSET, MASK, VALUE) (0XFF0A0008, 0xFFFFFFFFU ,0xFFDF0000U) */ + mask_write 0XFF0A0008 0xFFFFFFFF 0xFFDF0000 + # : MASK_DATA_1_MSW HIGH BANK [51:42] + # : MASK_DATA_1_LSW HIGH BANK [67:52] + # : MASK_DATA_1_LSW HIGH BANK [77:68] + # : ADD 5 MS DELAY + mask_delay 0x00000000 5 } set psu_post_config_data { @@ -12342,72 +13772,695 @@ set psu_peripherals_powerdwn_data { } set psu_lpd_xppu_data { - # : XPPU INTERRUPT ENABLE - # Register : IEN @ 0XFF980018

- - # See Interuppt Status Register for details - # PSU_LPD_XPPU_CFG_IEN_APER_PARITY 0X1 - - # See Interuppt Status Register for details - # PSU_LPD_XPPU_CFG_IEN_APER_TZ 0X1 - - # See Interuppt Status Register for details - # PSU_LPD_XPPU_CFG_IEN_APER_PERM 0X1 - - # See Interuppt Status Register for details - # PSU_LPD_XPPU_CFG_IEN_MID_PARITY 0X1 - - # See Interuppt Status Register for details - # PSU_LPD_XPPU_CFG_IEN_MID_RO 0X1 - - # See Interuppt Status Register for details - # PSU_LPD_XPPU_CFG_IEN_MID_MISS 0X1 - - # See Interuppt Status Register for details - # PSU_LPD_XPPU_CFG_IEN_INV_APB 0X1 - - # Interrupt Enable Register - #(OFFSET, MASK, VALUE) (0XFF980018, 0x000000EFU ,0x000000EFU) */ - mask_write 0XFF980018 0x000000EF 0x000000EF + # : MASTER ID LIST + # : APERTURE PERMISIION LIST + # : APERTURE NAME: UART0, START ADDRESS: FF000000, END ADDRESS: FF00FFFF + # : APERTURE NAME: UART1, START ADDRESS: FF010000, END ADDRESS: FF01FFFF + # : APERTURE NAME: I2C0, START ADDRESS: FF020000, END ADDRESS: FF02FFFF + # : APERTURE NAME: I2C1, START ADDRESS: FF030000, END ADDRESS: FF03FFFF + # : APERTURE NAME: SPI0, START ADDRESS: FF040000, END ADDRESS: FF04FFFF + # : APERTURE NAME: SPI1, START ADDRESS: FF050000, END ADDRESS: FF05FFFF + # : APERTURE NAME: CAN0, START ADDRESS: FF060000, END ADDRESS: FF06FFFF + # : APERTURE NAME: CAN1, START ADDRESS: FF070000, END ADDRESS: FF07FFFF + # : APERTURE NAME: RPU_UNUSED_12, START ADDRESS: FF080000, END ADDRESS: FF09FFFF + # : APERTURE NAME: RPU_UNUSED_12, START ADDRESS: FF080000, END ADDRESS: FF09FFFF + # : APERTURE NAME: GPIO, START ADDRESS: FF0A0000, END ADDRESS: FF0AFFFF + # : APERTURE NAME: GEM0, START ADDRESS: FF0B0000, END ADDRESS: FF0BFFFF + # : APERTURE NAME: GEM1, START ADDRESS: FF0C0000, END ADDRESS: FF0CFFFF + # : APERTURE NAME: GEM2, START ADDRESS: FF0D0000, END ADDRESS: FF0DFFFF + # : APERTURE NAME: GEM3, START ADDRESS: FF0E0000, END ADDRESS: FF0EFFFF + # : APERTURE NAME: QSPI, START ADDRESS: FF0F0000, END ADDRESS: FF0FFFFF + # : APERTURE NAME: NAND, START ADDRESS: FF100000, END ADDRESS: FF10FFFF + # : APERTURE NAME: TTC0, START ADDRESS: FF110000, END ADDRESS: FF11FFFF + # : APERTURE NAME: TTC1, START ADDRESS: FF120000, END ADDRESS: FF12FFFF + # : APERTURE NAME: TTC2, START ADDRESS: FF130000, END ADDRESS: FF13FFFF + # : APERTURE NAME: TTC3, START ADDRESS: FF140000, END ADDRESS: FF14FFFF + # : APERTURE NAME: SWDT, START ADDRESS: FF150000, END ADDRESS: FF15FFFF + # : APERTURE NAME: SD0, START ADDRESS: FF160000, END ADDRESS: FF16FFFF + # : APERTURE NAME: SD1, START ADDRESS: FF170000, END ADDRESS: FF17FFFF + # : APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + # : APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + # : APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + # : APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + # : APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + # : APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + # : APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + # : APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + # : APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + # : APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + # : APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + # : APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + # : APERTURE NAME: IOU_SECURE_SLCR, START ADDRESS: FF240000, END ADDRESS: FF24FFFF + # : APERTURE NAME: IOU_SCNTR, START ADDRESS: FF250000, END ADDRESS: FF25FFFF + # : APERTURE NAME: IOU_SCNTRS, START ADDRESS: FF260000, END ADDRESS: FF26FFFF + # : APERTURE NAME: RPU_UNUSED_11, START ADDRESS: FF270000, END ADDRESS: FF2AFFFF + # : APERTURE NAME: RPU_UNUSED_11, START ADDRESS: FF270000, END ADDRESS: FF2AFFFF + # : APERTURE NAME: RPU_UNUSED_11, START ADDRESS: FF270000, END ADDRESS: FF2AFFFF + # : APERTURE NAME: RPU_UNUSED_11, START ADDRESS: FF270000, END ADDRESS: FF2AFFFF + # : APERTURE NAME: LPD_UNUSED_14, START ADDRESS: FF2B0000, END ADDRESS: FF2FFFFF + # : APERTURE NAME: LPD_UNUSED_14, START ADDRESS: FF2B0000, END ADDRESS: FF2FFFFF + # : APERTURE NAME: LPD_UNUSED_14, START ADDRESS: FF2B0000, END ADDRESS: FF2FFFFF + # : APERTURE NAME: LPD_UNUSED_14, START ADDRESS: FF2B0000, END ADDRESS: FF2FFFFF + # : APERTURE NAME: LPD_UNUSED_14, START ADDRESS: FF2B0000, END ADDRESS: FF2FFFFF + # : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + # : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + # : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + # : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + # : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + # : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + # : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + # : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + # : APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF + # : APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF + # : APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF + # : APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF + # : APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF + # : APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF + # : APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF + # : APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF + # : APERTURE NAME: LPD_UNUSED_1, START ADDRESS: FF400000, END ADDRESS: FF40FFFF + # : APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + # : APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + # : APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + # : APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + # : APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + # : APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + # : APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + # : APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + # : APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + # : APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + # : APERTURE NAME: LPD_SLCR_SECURE, START ADDRESS: FF4B0000, END ADDRESS: FF4DFFFF + # : APERTURE NAME: LPD_SLCR_SECURE, START ADDRESS: FF4B0000, END ADDRESS: FF4DFFFF + # : APERTURE NAME: LPD_SLCR_SECURE, START ADDRESS: FF4B0000, END ADDRESS: FF4DFFFF + # : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF + # : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF + # : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF + # : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF + # : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF + # : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF + # : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF + # : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF + # : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF + # : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF + # : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF + # : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF + # : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF + # : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF + # : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF + # : APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DFFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + # : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF + # : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF + # : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF + # : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF + # : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF + # : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF + # : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF + # : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF + # : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF + # : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF + # : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF + # : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF + # : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF + # : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF + # : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF + # : APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95FFFF + # : APERTURE NAME: OCM_SLCR, START ADDRESS: FF960000, END ADDRESS: FF96FFFF + # : APERTURE NAME: LPD_UNUSED_4, START ADDRESS: FF970000, END ADDRESS: FF97FFFF + # : APERTURE NAME: LPD_XPPU, START ADDRESS: FF980000, END ADDRESS: FF99FFFF + # : APERTURE NAME: RPU, START ADDRESS: FF9A0000, END ADDRESS: FF9AFFFF + # : APERTURE NAME: AFIFM6, START ADDRESS: FF9B0000, END ADDRESS: FF9BFFFF + # : APERTURE NAME: LPD_XPPU_SINK, START ADDRESS: FF9C0000, END ADDRESS: FF9CFFFF + # : APERTURE NAME: USB3_0, START ADDRESS: FF9D0000, END ADDRESS: FF9DFFFF + # : APERTURE NAME: USB3_1, START ADDRESS: FF9E0000, END ADDRESS: FF9EFFFF + # : APERTURE NAME: LPD_UNUSED_5, START ADDRESS: FF9F0000, END ADDRESS: FF9FFFFF + # : APERTURE NAME: APM0, START ADDRESS: FFA00000, END ADDRESS: FFA0FFFF + # : APERTURE NAME: APM1, START ADDRESS: FFA10000, END ADDRESS: FFA1FFFF + # : APERTURE NAME: APM_INTC_IOU, START ADDRESS: FFA20000, END ADDRESS: FFA2FFFF + # : APERTURE NAME: APM_FPD_LPD, START ADDRESS: FFA30000, END ADDRESS: FFA3FFFF + # : APERTURE NAME: LPD_UNUSED_6, START ADDRESS: FFA40000, END ADDRESS: FFA4FFFF + # : APERTURE NAME: AMS, START ADDRESS: FFA50000, END ADDRESS: FFA5FFFF + # : APERTURE NAME: RTC, START ADDRESS: FFA60000, END ADDRESS: FFA6FFFF + # : APERTURE NAME: OCM_XMPU_CFG, START ADDRESS: FFA70000, END ADDRESS: FFA7FFFF + # : APERTURE NAME: ADMA_0, START ADDRESS: FFA80000, END ADDRESS: FFA8FFFF + # : APERTURE NAME: ADMA_1, START ADDRESS: FFA90000, END ADDRESS: FFA9FFFF + # : APERTURE NAME: ADMA_2, START ADDRESS: FFAA0000, END ADDRESS: FFAAFFFF + # : APERTURE NAME: ADMA_3, START ADDRESS: FFAB0000, END ADDRESS: FFABFFFF + # : APERTURE NAME: ADMA_4, START ADDRESS: FFAC0000, END ADDRESS: FFACFFFF + # : APERTURE NAME: ADMA_5, START ADDRESS: FFAD0000, END ADDRESS: FFADFFFF + # : APERTURE NAME: ADMA_6, START ADDRESS: FFAE0000, END ADDRESS: FFAEFFFF + # : APERTURE NAME: ADMA_7, START ADDRESS: FFAF0000, END ADDRESS: FFAFFFFF + # : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF + # : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF + # : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF + # : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF + # : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF + # : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF + # : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF + # : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF + # : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF + # : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF + # : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF + # : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF + # : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF + # : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF + # : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF + # : APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFFFFF + # : APERTURE NAME: CSU_ROM, START ADDRESS: FFC00000, END ADDRESS: FFC1FFFF + # : APERTURE NAME: CSU_ROM, START ADDRESS: FFC00000, END ADDRESS: FFC1FFFF + # : APERTURE NAME: CSU_LOCAL, START ADDRESS: FFC20000, END ADDRESS: FFC2FFFF + # : APERTURE NAME: PUF, START ADDRESS: FFC30000, END ADDRESS: FFC3FFFF + # : APERTURE NAME: CSU_RAM, START ADDRESS: FFC40000, END ADDRESS: FFC5FFFF + # : APERTURE NAME: CSU_RAM, START ADDRESS: FFC40000, END ADDRESS: FFC5FFFF + # : APERTURE NAME: CSU_IOMODULE, START ADDRESS: FFC60000, END ADDRESS: FFC7FFFF + # : APERTURE NAME: CSU_IOMODULE, START ADDRESS: FFC60000, END ADDRESS: FFC7FFFF + # : APERTURE NAME: CSUDMA, START ADDRESS: FFC80000, END ADDRESS: FFC9FFFF + # : APERTURE NAME: CSUDMA, START ADDRESS: FFC80000, END ADDRESS: FFC9FFFF + # : APERTURE NAME: CSU, START ADDRESS: FFCA0000, END ADDRESS: FFCAFFFF + # : APERTURE NAME: CSU_WDT, START ADDRESS: FFCB0000, END ADDRESS: FFCBFFFF + # : APERTURE NAME: EFUSE, START ADDRESS: FFCC0000, END ADDRESS: FFCCFFFF + # : APERTURE NAME: BBRAM, START ADDRESS: FFCD0000, END ADDRESS: FFCDFFFF + # : APERTURE NAME: RSA_CORE, START ADDRESS: FFCE0000, END ADDRESS: FFCEFFFF + # : APERTURE NAME: MBISTJTAG, START ADDRESS: FFCF0000, END ADDRESS: FFCFFFFF + # : APERTURE NAME: PMU_ROM, START ADDRESS: FFD00000, END ADDRESS: FFD3FFFF + # : APERTURE NAME: PMU_ROM, START ADDRESS: FFD00000, END ADDRESS: FFD3FFFF + # : APERTURE NAME: PMU_ROM, START ADDRESS: FFD00000, END ADDRESS: FFD3FFFF + # : APERTURE NAME: PMU_ROM, START ADDRESS: FFD00000, END ADDRESS: FFD3FFFF + # : APERTURE NAME: PMU_IOMODULE, START ADDRESS: FFD40000, END ADDRESS: FFD5FFFF + # : APERTURE NAME: PMU_IOMODULE, START ADDRESS: FFD40000, END ADDRESS: FFD5FFFF + # : APERTURE NAME: PMU_LOCAL, START ADDRESS: FFD60000, END ADDRESS: FFD7FFFF + # : APERTURE NAME: PMU_LOCAL, START ADDRESS: FFD60000, END ADDRESS: FFD7FFFF + # : APERTURE NAME: PMU_GLOBAL, START ADDRESS: FFD80000, END ADDRESS: FFDBFFFF + # : APERTURE NAME: PMU_GLOBAL, START ADDRESS: FFD80000, END ADDRESS: FFDBFFFF + # : APERTURE NAME: PMU_GLOBAL, START ADDRESS: FFD80000, END ADDRESS: FFDBFFFF + # : APERTURE NAME: PMU_GLOBAL, START ADDRESS: FFD80000, END ADDRESS: FFDBFFFF + # : APERTURE NAME: PMU_RAM, START ADDRESS: FFDC0000, END ADDRESS: FFDFFFFF + # : APERTURE NAME: PMU_RAM, START ADDRESS: FFDC0000, END ADDRESS: FFDFFFFF + # : APERTURE NAME: PMU_RAM, START ADDRESS: FFDC0000, END ADDRESS: FFDFFFFF + # : APERTURE NAME: PMU_RAM, START ADDRESS: FFDC0000, END ADDRESS: FFDFFFFF + # : APERTURE NAME: R5_0_ATCM, START ADDRESS: FFE00000, END ADDRESS: FFE0FFFF + # : APERTURE NAME: R5_0_ATCM_LOCKSTEP, START ADDRESS: FFE10000, END ADDRESS: FFE1FFFF + # : APERTURE NAME: R5_0_BTCM, START ADDRESS: FFE20000, END ADDRESS: FFE2FFFF + # : APERTURE NAME: R5_0_BTCM_LOCKSTEP, START ADDRESS: FFE30000, END ADDRESS: FFE3FFFF + # : APERTURE NAME: R5_0_INSTRUCTION_CACHE, START ADDRESS: FFE40000, END ADDRESS: FFE4FFFF + # : APERTURE NAME: R5_0_DATA_CACHE, START ADDRESS: FFE50000, END ADDRESS: FFE5FFFF + # : APERTURE NAME: LPD_UNUSED_8, START ADDRESS: FFE60000, END ADDRESS: FFE8FFFF + # : APERTURE NAME: LPD_UNUSED_8, START ADDRESS: FFE60000, END ADDRESS: FFE8FFFF + # : APERTURE NAME: LPD_UNUSED_8, START ADDRESS: FFE60000, END ADDRESS: FFE8FFFF + # : APERTURE NAME: R5_1_ATCM_, START ADDRESS: FFE90000, END ADDRESS: FFE9FFFF + # : APERTURE NAME: RPU_UNUSED_10, START ADDRESS: FFEA0000, END ADDRESS: FFEAFFFF + # : APERTURE NAME: R5_1_BTCM_, START ADDRESS: FFEB0000, END ADDRESS: FFEBFFFF + # : APERTURE NAME: R5_1_INSTRUCTION_CACHE, START ADDRESS: FFEC0000, END ADDRESS: FFECFFFF + # : APERTURE NAME: R5_1_DATA_CACHE, START ADDRESS: FFED0000, END ADDRESS: FFEDFFFF + # : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF + # : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF + # : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF + # : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF + # : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF + # : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF + # : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF + # : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF + # : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF + # : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF + # : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF + # : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF + # : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF + # : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF + # : APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBFFFF + # : APERTURE NAME: LPD_UNUSED_15, START ADDRESS: FFFD0000, END ADDRESS: FFFFFFFF + # : APERTURE NAME: LPD_UNUSED_15, START ADDRESS: FFFD0000, END ADDRESS: FFFFFFFF + # : APERTURE NAME: LPD_UNUSED_15, START ADDRESS: FFFD0000, END ADDRESS: FFFFFFFF + # : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + # : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + # : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + # : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + # : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + # : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + # : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + # : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + # : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + # : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + # : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + # : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + # : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + # : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + # : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + # : APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + # : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + # : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + # : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + # : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + # : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + # : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + # : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + # : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + # : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + # : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + # : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + # : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + # : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + # : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + # : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + # : APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + # : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + # : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + # : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + # : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + # : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + # : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + # : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + # : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + # : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + # : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + # : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + # : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + # : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + # : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + # : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + # : APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + # : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + # : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + # : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + # : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + # : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + # : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + # : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + # : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + # : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + # : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + # : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + # : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + # : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + # : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + # : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + # : APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + # : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + # : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + # : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + # : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + # : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + # : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + # : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + # : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + # : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + # : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + # : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + # : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + # : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + # : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + # : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + # : APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + # : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + # : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + # : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + # : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + # : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + # : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + # : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + # : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + # : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + # : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + # : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + # : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + # : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + # : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + # : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + # : APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + # : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + # : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + # : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + # : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + # : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + # : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + # : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + # : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + # : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + # : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + # : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + # : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + # : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + # : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + # : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + # : APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + # : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + # : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + # : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + # : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + # : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + # : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + # : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + # : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + # : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + # : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + # : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + # : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + # : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + # : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + # : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + # : APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + # : APERTURE NAME: IOU_GPV, START ADDRESS: FE000000, END ADDRESS: FE0FFFFF + # : APERTURE NAME: LPD_GPV, START ADDRESS: FE100000, END ADDRESS: FE1FFFFF + # : APERTURE NAME: USB3_0_XHCI, START ADDRESS: FE200000, END ADDRESS: FE2FFFFF + # : APERTURE NAME: USB3_1_XHCI, START ADDRESS: FE300000, END ADDRESS: FE3FFFFF + # : APERTURE NAME: LPD_UNUSED_13, START ADDRESS: FE400000, END ADDRESS: FE7FFFFF + # : APERTURE NAME: LPD_UNUSED_13, START ADDRESS: FE400000, END ADDRESS: FE7FFFFF + # : APERTURE NAME: LPD_UNUSED_13, START ADDRESS: FE400000, END ADDRESS: FE7FFFFF + # : APERTURE NAME: LPD_UNUSED_13, START ADDRESS: FE400000, END ADDRESS: FE7FFFFF + # : APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF + # : APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF + # : APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF + # : APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF + # : APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF + # : APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF + # : APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF + # : APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF + # : APERTURE NAME: QSPI_LINEAR_ADDRESS, START ADDRESS: C0000000, END ADDRESS: DFFFFFFF + # : XPPU CONTROL } set psu_ddr_xmpu0_data { + # : DDR XMPU0 } set psu_ddr_xmpu1_data { + # : DDR XMPU1 } set psu_ddr_xmpu2_data { + # : DDR XMPU2 } set psu_ddr_xmpu3_data { + # : DDR XMPU3 } set psu_ddr_xmpu4_data { + # : DDR XMPU4 } set psu_ddr_xmpu5_data { + # : DDR XMPU5 } set psu_ocm_xmpu_data { + # : OCM XMPU } set psu_fpd_xmpu_data { + # : FPD XMPU } set psu_protection_lock_data { + # : LOCKING PROTECTION MODULE + # : XPPU LOCK + # : APERTURE NAME: LPD_XPPU, START ADDRESS: FF980000, END ADDRESS: FF99FFFF + # : XMPU LOCK + # : LOCK OCM XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER + # : LOCK FPD XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER + # : LOCK DDR XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER + # : LOCK DDR XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER + # : LOCK DDR XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER + # : LOCK DDR XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER + # : LOCK DDR XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER + # : LOCK DDR XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER } set psu_apply_master_tz { # : RPU # : DP TZ + # Register : slcr_dpdma @ 0XFD690040

+ + # TrustZone classification for DisplayPort DMA + # PSU_FPD_SLCR_SECURE_SLCR_DPDMA_TZ 1 + + # DPDMA TrustZone Settings + #(OFFSET, MASK, VALUE) (0XFD690040, 0x00000001U ,0x00000001U) */ + mask_write 0XFD690040 0x00000001 0x00000001 # : SATA TZ # : PCIE TZ + # Register : slcr_pcie @ 0XFD690030

+ + # TrustZone classification for DMA Channel 0 + # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_0 1 + + # TrustZone classification for DMA Channel 1 + # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_1 1 + + # TrustZone classification for DMA Channel 2 + # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_2 1 + + # TrustZone classification for DMA Channel 3 + # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_3 1 + + # TrustZone classification for Ingress Address Translation 0 + # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_0 1 + + # TrustZone classification for Ingress Address Translation 1 + # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_1 1 + + # TrustZone classification for Ingress Address Translation 2 + # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_2 1 + + # TrustZone classification for Ingress Address Translation 3 + # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_3 1 + + # TrustZone classification for Ingress Address Translation 4 + # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_4 1 + + # TrustZone classification for Ingress Address Translation 5 + # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_5 1 + + # TrustZone classification for Ingress Address Translation 6 + # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_6 1 + + # TrustZone classification for Ingress Address Translation 7 + # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_7 1 + + # TrustZone classification for Egress Address Translation 0 + # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_0 1 + + # TrustZone classification for Egress Address Translation 1 + # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_1 1 + + # TrustZone classification for Egress Address Translation 2 + # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_2 1 + + # TrustZone classification for Egress Address Translation 3 + # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_3 1 + + # TrustZone classification for Egress Address Translation 4 + # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_4 1 + + # TrustZone classification for Egress Address Translation 5 + # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_5 1 + + # TrustZone classification for Egress Address Translation 6 + # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_6 1 + + # TrustZone classification for Egress Address Translation 7 + # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_7 1 + + # TrustZone classification for DMA Registers + # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_REGS 1 + + # TrustZone classification for MSIx Table + # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_TABLE 1 + + # TrustZone classification for MSIx PBA + # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_PBA 1 + + # TrustZone classification for ECAM + # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_ECAM 1 + + # TrustZone classification for Bridge Common Registers + # PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_BRIDGE_REGS 1 + + # PCIe TrustZone settings. This register may only be modified during bootu + # p (while PCIe block is disabled) + #(OFFSET, MASK, VALUE) (0XFD690030, 0x01FFFFFFU ,0x01FFFFFFU) */ + mask_write 0XFD690030 0x01FFFFFF 0x01FFFFFF # : USB TZ + # Register : slcr_usb @ 0XFF4B0034

+ + # TrustZone Classification for USB3_0 + # PSU_LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_0 1 + + # TrustZone Classification for USB3_1 + # PSU_LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_1 1 + + # USB3 TrustZone settings + #(OFFSET, MASK, VALUE) (0XFF4B0034, 0x00000003U ,0x00000003U) */ + mask_write 0XFF4B0034 0x00000003 0x00000003 # : SD TZ + # Register : IOU_AXI_RPRTCN @ 0XFF240004

+ + # AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + # 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + # ccess [2] = '1'' : Instruction access + # PSU_IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD0_AXI_ARPROT 2 + + # AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + # 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + # ccess [2] = '1'' : Instruction access + # PSU_IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD1_AXI_ARPROT 2 + + # AXI read protection type selection + #(OFFSET, MASK, VALUE) (0XFF240004, 0x003F0000U ,0x00120000U) */ + mask_write 0XFF240004 0x003F0000 0x00120000 + # Register : IOU_AXI_WPRTCN @ 0XFF240000

+ + # AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + # 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + # ccess [2] = '1'' : Instruction access + # PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD0_AXI_AWPROT 2 + + # AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + # 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + # ccess [2] = '1'' : Instruction access + # PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD1_AXI_AWPROT 2 + + # AXI write protection type selection + #(OFFSET, MASK, VALUE) (0XFF240000, 0x003F0000U ,0x00120000U) */ + mask_write 0XFF240000 0x003F0000 0x00120000 # : GEM TZ + # Register : IOU_AXI_RPRTCN @ 0XFF240004

+ + # AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + # 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + # ccess [2] = '1'' : Instruction access + # PSU_IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM0_AXI_ARPROT 2 + + # AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + # 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + # ccess [2] = '1'' : Instruction access + # PSU_IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM1_AXI_ARPROT 2 + + # AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + # 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + # ccess [2] = '1'' : Instruction access + # PSU_IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM2_AXI_ARPROT 2 + + # AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + # 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + # ccess [2] = '1'' : Instruction access + # PSU_IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM3_AXI_ARPROT 2 + + # AXI read protection type selection + #(OFFSET, MASK, VALUE) (0XFF240004, 0x00000FFFU ,0x00000492U) */ + mask_write 0XFF240004 0x00000FFF 0x00000492 + # Register : IOU_AXI_WPRTCN @ 0XFF240000

+ + # AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + # 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + # ccess [2] = '1'' : Instruction access + # PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM0_AXI_AWPROT 2 + + # AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + # 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + # ccess [2] = '1'' : Instruction access + # PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM1_AXI_AWPROT 2 + + # AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + # 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + # ccess [2] = '1'' : Instruction access + # PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM2_AXI_AWPROT 2 + + # AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + # 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + # ccess [2] = '1'' : Instruction access + # PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM3_AXI_AWPROT 2 + + # AXI write protection type selection + #(OFFSET, MASK, VALUE) (0XFF240000, 0x00000FFFU ,0x00000492U) */ + mask_write 0XFF240000 0x00000FFF 0x00000492 # : QSPI TZ + # Register : IOU_AXI_WPRTCN @ 0XFF240000

+ + # AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + # 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + # ccess [2] = '1'' : Instruction access + # PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_QSPI_AXI_AWPROT 2 + + # AXI write protection type selection + #(OFFSET, MASK, VALUE) (0XFF240000, 0x0E000000U ,0x04000000U) */ + mask_write 0XFF240000 0x0E000000 0x04000000 # : NAND TZ + # Register : IOU_AXI_RPRTCN @ 0XFF240004

+ + # AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + # 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + # ccess [2] = '1'' : Instruction access + # PSU_IOU_SECURE_SLCR_IOU_AXI_RPRTCN_NAND_AXI_ARPROT 2 + + # AXI read protection type selection + #(OFFSET, MASK, VALUE) (0XFF240004, 0x01C00000U ,0x00800000U) */ + mask_write 0XFF240004 0x01C00000 0x00800000 + # Register : IOU_AXI_WPRTCN @ 0XFF240000

+ + # AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + # 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + # ccess [2] = '1'' : Instruction access + # PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_NAND_AXI_AWPROT 2 + + # AXI write protection type selection + #(OFFSET, MASK, VALUE) (0XFF240000, 0x01C00000U ,0x00800000U) */ + mask_write 0XFF240000 0x01C00000 0x00800000 + # : DMA TZ + # Register : slcr_adma @ 0XFF4B0024

+ + # TrustZone Classification for ADMA + # PSU_LPD_SLCR_SECURE_SLCR_ADMA_TZ 0xFF + + # RPU TrustZone settings + #(OFFSET, MASK, VALUE) (0XFF4B0024, 0x000000FFU ,0x000000FFU) */ + mask_write 0XFF4B0024 0x000000FF 0x000000FF + # Register : slcr_gdma @ 0XFD690050

+ + # TrustZone Classification for GDMA + # PSU_FPD_SLCR_SECURE_SLCR_GDMA_TZ 0xFF + + # GDMA Trustzone Settings + #(OFFSET, MASK, VALUE) (0XFD690050, 0x000000FFU ,0x000000FFU) */ + mask_write 0XFD690050 0x000000FF 0x000000FF } set psu_serdes_init_data { @@ -12415,9 +14468,11 @@ set psu_serdes_init_data { # : GT REFERENCE CLOCK SOURCE SELECTION # Register : PLL_REF_SEL0 @ 0XFD410000

- # PLL0 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - - # 4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135 - # Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved + # PLL0 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 1 + # 2MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 24MHz, 0x8 - 26MHz, + # 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE + # - 108MHz, 0xF - 125MHz, 0x10 - 135MHz, 0x11 - 150 MHz. 0x12 to 0x1F - R + # eserved # PSU_SERDES_PLL_REF_SEL0_PLLREFSEL0 0xD # PLL0 Reference Selection Register @@ -12425,9 +14480,11 @@ set psu_serdes_init_data { mask_write 0XFD410000 0x0000001F 0x0000000D # Register : PLL_REF_SEL1 @ 0XFD410004

- # PLL1 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - - # 4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135 - # Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved + # PLL1 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 1 + # 2MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 24MHz, 0x8 - 26MHz, + # 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE + # - 108MHz, 0xF - 125MHz, 0x10 - 135MHz, 0x11 - 150 MHz. 0x12 to 0x1F - R + # eserved # PSU_SERDES_PLL_REF_SEL1_PLLREFSEL1 0x9 # PLL1 Reference Selection Register @@ -12435,9 +14492,11 @@ set psu_serdes_init_data { mask_write 0XFD410004 0x0000001F 0x00000009 # Register : PLL_REF_SEL2 @ 0XFD410008

- # PLL2 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - - # 4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135 - # Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved + # PLL2 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 1 + # 2MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 24MHz, 0x8 - 26MHz, + # 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE + # - 108MHz, 0xF - 125MHz, 0x10 - 135MHz, 0x11 - 150 MHz. 0x12 to 0x1F - R + # eserved # PSU_SERDES_PLL_REF_SEL2_PLLREFSEL2 0x8 # PLL2 Reference Selection Register @@ -12445,9 +14504,11 @@ set psu_serdes_init_data { mask_write 0XFD410008 0x0000001F 0x00000008 # Register : PLL_REF_SEL3 @ 0XFD41000C

- # PLL3 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - - # 4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135 - # Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved + # PLL3 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 1 + # 2MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 24MHz, 0x8 - 26MHz, + # 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE + # - 108MHz, 0xF - 125MHz, 0x10 - 135MHz, 0x11 - 150 MHz. 0x12 to 0x1F - R + # eserved # PSU_SERDES_PLL_REF_SEL3_PLLREFSEL3 0xF # PLL3 Reference Selection Register @@ -12456,7 +14517,8 @@ set psu_serdes_init_data { # : GT REFERENCE CLOCK FREQUENCY SELECTION # Register : L0_L0_REF_CLK_SEL @ 0XFD402860

- # Sel of lane 0 ref clock local mux. Set to 1 to select lane 0 slicer output. Set to 0 to select lane0 ref clock mux output. + # Sel of lane 0 ref clock local mux. Set to 1 to select lane 0 slicer outp + # ut. Set to 0 to select lane0 ref clock mux output. # PSU_SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL 0x1 # Lane0 Ref Clock Selection Register @@ -12464,10 +14526,12 @@ set psu_serdes_init_data { mask_write 0XFD402860 0x00000080 0x00000080 # Register : L0_L1_REF_CLK_SEL @ 0XFD402864

- # Sel of lane 1 ref clock local mux. Set to 1 to select lane 1 slicer output. Set to 0 to select lane1 ref clock mux output. + # Sel of lane 1 ref clock local mux. Set to 1 to select lane 1 slicer outp + # ut. Set to 0 to select lane1 ref clock mux output. # PSU_SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL 0x0 - # Bit 3 of lane 1 ref clock mux one hot sel. Set to 1 to select lane 3 slicer output from ref clock network + # Bit 3 of lane 1 ref clock mux one hot sel. Set to 1 to select lane 3 sli + # cer output from ref clock network # PSU_SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3 0x1 # Lane1 Ref Clock Selection Register @@ -12475,7 +14539,8 @@ set psu_serdes_init_data { mask_write 0XFD402864 0x00000088 0x00000008 # Register : L0_L2_REF_CLK_SEL @ 0XFD402868

- # Sel of lane 2 ref clock local mux. Set to 1 to select lane 1 slicer output. Set to 0 to select lane2 ref clock mux output. + # Sel of lane 2 ref clock local mux. Set to 1 to select lane 1 slicer outp + # ut. Set to 0 to select lane2 ref clock mux output. # PSU_SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL 0x1 # Lane2 Ref Clock Selection Register @@ -12483,10 +14548,12 @@ set psu_serdes_init_data { mask_write 0XFD402868 0x00000080 0x00000080 # Register : L0_L3_REF_CLK_SEL @ 0XFD40286C

- # Sel of lane 3 ref clock local mux. Set to 1 to select lane 3 slicer output. Set to 0 to select lane3 ref clock mux output. + # Sel of lane 3 ref clock local mux. Set to 1 to select lane 3 slicer outp + # ut. Set to 0 to select lane3 ref clock mux output. # PSU_SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL 0x0 - # Bit 1 of lane 3 ref clock mux one hot sel. Set to 1 to select lane 1 slicer output from ref clock network + # Bit 1 of lane 3 ref clock mux one hot sel. Set to 1 to select lane 1 sli + # cer output from ref clock network # PSU_SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1 0x1 # Lane3 Ref Clock Selection Register @@ -12693,7 +14760,8 @@ set psu_serdes_init_data { # Enable test mode force on fractional mode enable # PSU_SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC 0x1 - # Fractional feedback division control and fractional value for feedback division bits 26:24 + # Fractional feedback division control and fractional value for feedback d + # ivision bits 26:24 #(OFFSET, MASK, VALUE) (0XFD40E360, 0x00000040U ,0x00000040U) */ mask_write 0XFD40E360 0x00000040 0x00000040 # Register : L3_TM_DIG_6 @ 0XFD40D06C

@@ -12727,14 +14795,6 @@ set psu_serdes_init_data { # MPHY PLL Gear and bypass scrambler #(OFFSET, MASK, VALUE) (0XFD40C0F4, 0x0000000BU ,0x0000000BU) */ mask_write 0XFD40C0F4 0x0000000B 0x0000000B - # Register : L3_TXPMA_ST_0 @ 0XFD40CB00

- - # PHY Mode: 4'b000 - PCIe, 4'b001 - USB3, 4'b0010 - SATA, 4'b0100 - SGMII, 4'b0101 - DP, 4'b1000 - MPHY - # PSU_SERDES_L3_TXPMA_ST_0_TX_PHY_MODE 0x21 - - # Opmode Info - #(OFFSET, MASK, VALUE) (0XFD40CB00, 0x000000F0U ,0x000000F0U) */ - mask_write 0XFD40CB00 0x000000F0 0x000000F0 # : ENABLE CHICKEN BIT FOR PCIE AND USB # Register : L0_TM_AUX_0 @ 0XFD4010CC

@@ -12796,7 +14856,8 @@ set psu_serdes_init_data { mask_write 0XFD40189C 0x00000080 0x00000080 # Register : L0_TM_IQ_ILL1 @ 0XFD4018F8

- # IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS + # IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , + # USB3 : SS # PSU_SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0 0x64 # iqpi cal code @@ -12820,7 +14881,8 @@ set psu_serdes_init_data { mask_write 0XFD401990 0x000000FF 0x00000011 # Register : L0_TM_E_ILL1 @ 0XFD401924

- # E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS + # E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , U + # SB3 : SS # PSU_SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0 0x4 # epi cal code @@ -12890,6 +14952,22 @@ set psu_serdes_init_data { # enables for lf,constant gm trim and polytirm #(OFFSET, MASK, VALUE) (0XFD401944, 0x00000001U ,0x00000001U) */ mask_write 0XFD401944 0x00000001 0x00000001 + # Register : L0_TM_ILL13 @ 0XFD401994

+ + # ILL cal idle val refcnt + # PSU_SERDES_L0_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT 0x7 + + # ill cal idle value count + #(OFFSET, MASK, VALUE) (0XFD401994, 0x00000007U ,0x00000007U) */ + mask_write 0XFD401994 0x00000007 0x00000007 + # Register : L1_TM_ILL13 @ 0XFD405994

+ + # ILL cal idle val refcnt + # PSU_SERDES_L1_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT 0x7 + + # ill cal idle value count + #(OFFSET, MASK, VALUE) (0XFD405994, 0x00000007U ,0x00000007U) */ + mask_write 0XFD405994 0x00000007 0x00000007 # Register : L2_TM_MISC2 @ 0XFD40989C

# ILL calib counts BYPASSED with calcode bits @@ -12900,7 +14978,8 @@ set psu_serdes_init_data { mask_write 0XFD40989C 0x00000080 0x00000080 # Register : L2_TM_IQ_ILL1 @ 0XFD4098F8

- # IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS + # IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , + # USB3 : SS # PSU_SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0 0x1A # iqpi cal code @@ -12924,7 +15003,8 @@ set psu_serdes_init_data { mask_write 0XFD409990 0x000000FF 0x00000010 # Register : L2_TM_E_ILL1 @ 0XFD409924

- # E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS + # E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , U + # SB3 : SS # PSU_SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0 0xFE # epi cal code @@ -12994,6 +15074,14 @@ set psu_serdes_init_data { # enables for lf,constant gm trim and polytirm #(OFFSET, MASK, VALUE) (0XFD409944, 0x00000001U ,0x00000001U) */ mask_write 0XFD409944 0x00000001 0x00000001 + # Register : L2_TM_ILL13 @ 0XFD409994

+ + # ILL cal idle val refcnt + # PSU_SERDES_L2_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT 0x7 + + # ill cal idle value count + #(OFFSET, MASK, VALUE) (0XFD409994, 0x00000007U ,0x00000007U) */ + mask_write 0XFD409994 0x00000007 0x00000007 # Register : L3_TM_MISC2 @ 0XFD40D89C

# ILL calib counts BYPASSED with calcode bits @@ -13004,7 +15092,8 @@ set psu_serdes_init_data { mask_write 0XFD40D89C 0x00000080 0x00000080 # Register : L3_TM_IQ_ILL1 @ 0XFD40D8F8

- # IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS + # IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , + # USB3 : SS # PSU_SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0 0x7D # iqpi cal code @@ -13028,7 +15117,8 @@ set psu_serdes_init_data { mask_write 0XFD40D990 0x000000FF 0x00000001 # Register : L3_TM_E_ILL1 @ 0XFD40D924

- # E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS + # E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , U + # SB3 : SS # PSU_SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0 0x9C # epi cal code @@ -13106,23 +15196,47 @@ set psu_serdes_init_data { # enables for lf,constant gm trim and polytirm #(OFFSET, MASK, VALUE) (0XFD40D944, 0x00000001U ,0x00000001U) */ mask_write 0XFD40D944 0x00000001 0x00000001 + # Register : L3_TM_ILL13 @ 0XFD40D994

+ + # ILL cal idle val refcnt + # PSU_SERDES_L3_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT 0x7 + + # ill cal idle value count + #(OFFSET, MASK, VALUE) (0XFD40D994, 0x00000007U ,0x00000007U) */ + mask_write 0XFD40D994 0x00000007 0x00000007 # : SYMBOL LOCK AND WAIT - # Register : L0_TM_DIG_21 @ 0XFD4010A8

- - # pre lock comma count threshold. 2'b 00 : 3, 2'b 01 : 5, 2'b 10 : 10, 2'b 11 : 20 - # PSU_SERDES_L0_TM_DIG_21_COMMA_PRE_LOCK_THRESH 0x11 - - # Control symbol alignment locking - wait counts - #(OFFSET, MASK, VALUE) (0XFD4010A8, 0x00000003U ,0x00000003U) */ - mask_write 0XFD4010A8 0x00000003 0x00000003 # Register : L0_TM_DIG_10 @ 0XFD40107C

# CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001 - # PSU_SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME 0xF + # PSU_SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME 0x1 # test control for changing cdr lock wait time - #(OFFSET, MASK, VALUE) (0XFD40107C, 0x0000000FU ,0x0000000FU) */ - mask_write 0XFD40107C 0x0000000F 0x0000000F + #(OFFSET, MASK, VALUE) (0XFD40107C, 0x0000000FU ,0x00000001U) */ + mask_write 0XFD40107C 0x0000000F 0x00000001 + # Register : L1_TM_DIG_10 @ 0XFD40507C

+ + # CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001 + # PSU_SERDES_L1_TM_DIG_10_CDR_BIT_LOCK_TIME 0x1 + + # test control for changing cdr lock wait time + #(OFFSET, MASK, VALUE) (0XFD40507C, 0x0000000FU ,0x00000001U) */ + mask_write 0XFD40507C 0x0000000F 0x00000001 + # Register : L2_TM_DIG_10 @ 0XFD40907C

+ + # CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001 + # PSU_SERDES_L2_TM_DIG_10_CDR_BIT_LOCK_TIME 0x1 + + # test control for changing cdr lock wait time + #(OFFSET, MASK, VALUE) (0XFD40907C, 0x0000000FU ,0x00000001U) */ + mask_write 0XFD40907C 0x0000000F 0x00000001 + # Register : L3_TM_DIG_10 @ 0XFD40D07C

+ + # CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001 + # PSU_SERDES_L3_TM_DIG_10_CDR_BIT_LOCK_TIME 0x1 + + # test control for changing cdr lock wait time + #(OFFSET, MASK, VALUE) (0XFD40D07C, 0x0000000FU ,0x00000001U) */ + mask_write 0XFD40D07C 0x0000000F 0x00000001 # : SIOU SETTINGS FOR BYPASS CONTROL,HSRX-DIG # Register : L0_TM_RST_DLY @ 0XFD4019A4

@@ -13137,7 +15251,8 @@ set psu_serdes_init_data { # Enable Bypass for <7> of TM_ANA_BYPS_15 # PSU_SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE 0x1 - # Bypass control for pcs-pma interface. EQ supplies, main master supply and ps for samp c2c + # Bypass control for pcs-pma interface. EQ supplies, main master supply an + # d ps for samp c2c #(OFFSET, MASK, VALUE) (0XFD401038, 0x00000040U ,0x00000040U) */ mask_write 0XFD401038 0x00000040 0x00000040 # Register : L0_TM_ANA_BYP_12 @ 0XFD40102C

@@ -13145,7 +15260,8 @@ set psu_serdes_init_data { # Enable Bypass for <7> of TM_ANA_BYPS_12 # PSU_SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG 0x1 - # Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr enable controls + # Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr ena + # ble controls #(OFFSET, MASK, VALUE) (0XFD40102C, 0x00000040U ,0x00000040U) */ mask_write 0XFD40102C 0x00000040 0x00000040 # Register : L1_TM_RST_DLY @ 0XFD4059A4

@@ -13161,7 +15277,8 @@ set psu_serdes_init_data { # Enable Bypass for <7> of TM_ANA_BYPS_15 # PSU_SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE 0x1 - # Bypass control for pcs-pma interface. EQ supplies, main master supply and ps for samp c2c + # Bypass control for pcs-pma interface. EQ supplies, main master supply an + # d ps for samp c2c #(OFFSET, MASK, VALUE) (0XFD405038, 0x00000040U ,0x00000040U) */ mask_write 0XFD405038 0x00000040 0x00000040 # Register : L1_TM_ANA_BYP_12 @ 0XFD40502C

@@ -13169,7 +15286,8 @@ set psu_serdes_init_data { # Enable Bypass for <7> of TM_ANA_BYPS_12 # PSU_SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG 0x1 - # Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr enable controls + # Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr ena + # ble controls #(OFFSET, MASK, VALUE) (0XFD40502C, 0x00000040U ,0x00000040U) */ mask_write 0XFD40502C 0x00000040 0x00000040 # Register : L2_TM_RST_DLY @ 0XFD4099A4

@@ -13185,7 +15303,8 @@ set psu_serdes_init_data { # Enable Bypass for <7> of TM_ANA_BYPS_15 # PSU_SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE 0x1 - # Bypass control for pcs-pma interface. EQ supplies, main master supply and ps for samp c2c + # Bypass control for pcs-pma interface. EQ supplies, main master supply an + # d ps for samp c2c #(OFFSET, MASK, VALUE) (0XFD409038, 0x00000040U ,0x00000040U) */ mask_write 0XFD409038 0x00000040 0x00000040 # Register : L2_TM_ANA_BYP_12 @ 0XFD40902C

@@ -13193,7 +15312,8 @@ set psu_serdes_init_data { # Enable Bypass for <7> of TM_ANA_BYPS_12 # PSU_SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG 0x1 - # Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr enable controls + # Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr ena + # ble controls #(OFFSET, MASK, VALUE) (0XFD40902C, 0x00000040U ,0x00000040U) */ mask_write 0XFD40902C 0x00000040 0x00000040 # Register : L3_TM_RST_DLY @ 0XFD40D9A4

@@ -13209,7 +15329,8 @@ set psu_serdes_init_data { # Enable Bypass for <7> of TM_ANA_BYPS_15 # PSU_SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE 0x1 - # Bypass control for pcs-pma interface. EQ supplies, main master supply and ps for samp c2c + # Bypass control for pcs-pma interface. EQ supplies, main master supply an + # d ps for samp c2c #(OFFSET, MASK, VALUE) (0XFD40D038, 0x00000040U ,0x00000040U) */ mask_write 0XFD40D038 0x00000040 0x00000040 # Register : L3_TM_ANA_BYP_12 @ 0XFD40D02C

@@ -13217,18 +15338,106 @@ set psu_serdes_init_data { # Enable Bypass for <7> of TM_ANA_BYPS_12 # PSU_SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG 0x1 - # Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr enable controls + # Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr ena + # ble controls #(OFFSET, MASK, VALUE) (0XFD40D02C, 0x00000040U ,0x00000040U) */ mask_write 0XFD40D02C 0x00000040 0x00000040 + # : DISABLE FPL/FFL + # Register : L0_TM_MISC3 @ 0XFD4019AC

+ + # CDR fast phase lock control + # PSU_SERDES_L0_TM_MISC3_CDR_EN_FPL 0x0 + + # CDR fast frequency lock control + # PSU_SERDES_L0_TM_MISC3_CDR_EN_FFL 0x0 + + # debug bus selection bit, cdr fast phase and freq controls + #(OFFSET, MASK, VALUE) (0XFD4019AC, 0x00000003U ,0x00000000U) */ + mask_write 0XFD4019AC 0x00000003 0x00000000 + # Register : L1_TM_MISC3 @ 0XFD4059AC

+ + # CDR fast phase lock control + # PSU_SERDES_L1_TM_MISC3_CDR_EN_FPL 0x0 + + # CDR fast frequency lock control + # PSU_SERDES_L1_TM_MISC3_CDR_EN_FFL 0x0 + + # debug bus selection bit, cdr fast phase and freq controls + #(OFFSET, MASK, VALUE) (0XFD4059AC, 0x00000003U ,0x00000000U) */ + mask_write 0XFD4059AC 0x00000003 0x00000000 + # Register : L2_TM_MISC3 @ 0XFD4099AC

+ + # CDR fast phase lock control + # PSU_SERDES_L2_TM_MISC3_CDR_EN_FPL 0x0 + + # CDR fast frequency lock control + # PSU_SERDES_L2_TM_MISC3_CDR_EN_FFL 0x0 + + # debug bus selection bit, cdr fast phase and freq controls + #(OFFSET, MASK, VALUE) (0XFD4099AC, 0x00000003U ,0x00000000U) */ + mask_write 0XFD4099AC 0x00000003 0x00000000 + # Register : L3_TM_MISC3 @ 0XFD40D9AC

+ + # CDR fast phase lock control + # PSU_SERDES_L3_TM_MISC3_CDR_EN_FPL 0x0 + + # CDR fast frequency lock control + # PSU_SERDES_L3_TM_MISC3_CDR_EN_FFL 0x0 + + # debug bus selection bit, cdr fast phase and freq controls + #(OFFSET, MASK, VALUE) (0XFD40D9AC, 0x00000003U ,0x00000000U) */ + mask_write 0XFD40D9AC 0x00000003 0x00000000 + # : DISABLE DYNAMIC OFFSET CALIBRATION + # Register : L0_TM_EQ11 @ 0XFD401978

+ + # Force EQ offset correction algo off if not forced on + # PSU_SERDES_L0_TM_EQ11_FORCE_EQ_OFFS_OFF 0x1 + + # eq dynamic offset correction + #(OFFSET, MASK, VALUE) (0XFD401978, 0x00000010U ,0x00000010U) */ + mask_write 0XFD401978 0x00000010 0x00000010 + # Register : L1_TM_EQ11 @ 0XFD405978

+ + # Force EQ offset correction algo off if not forced on + # PSU_SERDES_L1_TM_EQ11_FORCE_EQ_OFFS_OFF 0x1 + + # eq dynamic offset correction + #(OFFSET, MASK, VALUE) (0XFD405978, 0x00000010U ,0x00000010U) */ + mask_write 0XFD405978 0x00000010 0x00000010 + # Register : L2_TM_EQ11 @ 0XFD409978

+ + # Force EQ offset correction algo off if not forced on + # PSU_SERDES_L2_TM_EQ11_FORCE_EQ_OFFS_OFF 0x1 + + # eq dynamic offset correction + #(OFFSET, MASK, VALUE) (0XFD409978, 0x00000010U ,0x00000010U) */ + mask_write 0XFD409978 0x00000010 0x00000010 + # Register : L3_TM_EQ11 @ 0XFD40D978

+ + # Force EQ offset correction algo off if not forced on + # PSU_SERDES_L3_TM_EQ11_FORCE_EQ_OFFS_OFF 0x1 + + # eq dynamic offset correction + #(OFFSET, MASK, VALUE) (0XFD40D978, 0x00000010U ,0x00000010U) */ + mask_write 0XFD40D978 0x00000010 0x00000010 + # : DISABLE ECO FOR PCIE + # Register : eco_0 @ 0XFD3D001C

+ + # For future use + # PSU_SIOU_ECO_0_FIELD 0x1 + + # ECO Register for future use + #(OFFSET, MASK, VALUE) (0XFD3D001C, 0xFFFFFFFFU ,0x00000001U) */ + mask_write 0XFD3D001C 0xFFFFFFFF 0x00000001 # : GT LANE SETTINGS # Register : ICM_CFG0 @ 0XFD410010

- # Controls UPHY Lane 0 protocol configuration. 0 - PowerDown, 1 - PCIe .0, 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII0, 6 - Unuse - # , 7 - Unused + # Controls UPHY Lane 0 protocol configuration. 0 - PowerDown, 1 - PCIe .0, + # 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII0, 6 - Unused, 7 - Unused # PSU_SERDES_ICM_CFG0_L0_ICM_CFG 1 - # Controls UPHY Lane 1 protocol configuration. 0 - PowerDown, 1 - PCIe.1, 2 - Sata1, 3 - USB0, 4 - DP.0, 5 - SGMII1, 6 - Unused - # 7 - Unused + # Controls UPHY Lane 1 protocol configuration. 0 - PowerDown, 1 - PCIe.1, + # 2 - Sata1, 3 - USB0, 4 - DP.0, 5 - SGMII1, 6 - Unused, 7 - Unused # PSU_SERDES_ICM_CFG0_L1_ICM_CFG 4 # ICM Configuration Register 0 @@ -13236,12 +15445,12 @@ set psu_serdes_init_data { mask_write 0XFD410010 0x00000077 0x00000041 # Register : ICM_CFG1 @ 0XFD410014

- # Controls UPHY Lane 2 protocol configuration. 0 - PowerDown, 1 - PCIe.1, 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII2, 6 - Unused - # 7 - Unused + # Controls UPHY Lane 2 protocol configuration. 0 - PowerDown, 1 - PCIe.1, + # 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII2, 6 - Unused, 7 - Unused # PSU_SERDES_ICM_CFG1_L2_ICM_CFG 3 - # Controls UPHY Lane 3 protocol configuration. 0 - PowerDown, 1 - PCIe.3, 2 - Sata1, 3 - USB1, 4 - DP.0, 5 - SGMII3, 6 - Unused - # 7 - Unused + # Controls UPHY Lane 3 protocol configuration. 0 - PowerDown, 1 - PCIe.3, + # 2 - Sata1, 3 - USB1, 4 - DP.0, 5 - SGMII3, 6 - Unused, 7 - Unused # PSU_SERDES_ICM_CFG1_L3_ICM_CFG 2 # ICM Configuration Register 1 @@ -13294,7 +15503,8 @@ set psu_serdes_init_data { # FFL Phase0 int gain aka 2ol SD update rate # PSU_SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN 0x6 - # Fast phase lock controls -- FSM accumulator cycle control and phase 0 int gain control. + # Fast phase lock controls -- FSM accumulator cycle control and phase 0 in + # t gain control. #(OFFSET, MASK, VALUE) (0XFD40DC14, 0x000000FFU ,0x000000E6U) */ mask_write 0XFD40DC14 0x000000FF 0x000000E6 # Register : L3_TM_CDR16 @ 0XFD40DC40

@@ -13336,7 +15546,8 @@ set psu_serdes_init_data { mask_write 0XFD404CC0 0x0000001F 0x00000000 # Register : L1_TX_ANA_TM_18 @ 0XFD404048

- # pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-emphasis, Others: reserved + # pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-em + # phasis, Others: reserved # PSU_SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0 0 # Override for PIPE TX de-emphasis @@ -13344,7 +15555,8 @@ set psu_serdes_init_data { mask_write 0XFD404048 0x000000FF 0x00000000 # Register : L3_TX_ANA_TM_18 @ 0XFD40C048

- # pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-emphasis, Others: reserved + # pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-em + # phasis, Others: reserved # PSU_SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0 0x1 # Override for PIPE TX de-emphasis @@ -13363,24 +15575,7 @@ set psu_resetout_init_data { # Software control register for the LPD block. #(OFFSET, MASK, VALUE) (0XFF5E023C, 0x00000400U ,0x00000000U) */ mask_write 0XFF5E023C 0x00000400 0x00000000 - # : USB0 PIPE POWER PRESENT - # Register : fpd_power_prsnt @ 0XFF9D0080

- - # This bit is used to choose between PIPE power present and 1'b1 - # PSU_USB3_0_FPD_POWER_PRSNT_OPTION 0X1 - - # fpd_power_prsnt - #(OFFSET, MASK, VALUE) (0XFF9D0080, 0x00000001U ,0x00000001U) */ - mask_write 0XFF9D0080 0x00000001 0x00000001 - # Register : fpd_pipe_clk @ 0XFF9D007C

- - # This bit is used to choose between PIPE clock coming from SerDes and the suspend clk - # PSU_USB3_0_FPD_PIPE_CLK_OPTION 0x0 - - # fpd_pipe_clk - #(OFFSET, MASK, VALUE) (0XFF9D007C, 0x00000001U ,0x00000000U) */ - mask_write 0XFF9D007C 0x00000001 0x00000000 - # : + # : HIBERREST # Register : RST_LPD_TOP @ 0XFF5E023C

# USB 0 sleep circuit reset @@ -13407,7 +15602,8 @@ set psu_resetout_init_data { # Sata PM clock control select # PSU_SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL 0x3 - # Misc Contorls for SATA.This register may only be modified during bootup (while SATA block is disabled) + # Misc Contorls for SATA.This register may only be modified during bootup + # (while SATA block is disabled) #(OFFSET, MASK, VALUE) (0XFD3D0100, 0x00000003U ,0x00000003U) */ mask_write 0XFD3D0100 0x00000003 0x00000003 # Register : RST_FPD_TOP @ 0XFD1A0100

@@ -13449,8 +15645,9 @@ set psu_resetout_init_data { mask_write 0XFD4A0200 0x00000002 0x00000000 # Register : DP_TX_PHY_POWER_DOWN @ 0XFD4A0238

- # Two bits per lane. When set to 11, moves the GT to power down mode. When set to 00, GT will be in active state. bits [1:0] - - # ane0 Bits [3:2] - lane 1 + # Two bits per lane. When set to 11, moves the GT to power down mode. When + # set to 00, GT will be in active state. bits [1:0] - lane0 Bits [3:2] - + # lane 1 # PSU_DP_DP_TX_PHY_POWER_DOWN_POWER_DWN 0X0 # Control PHY Power down @@ -13459,96 +15656,194 @@ set psu_resetout_init_data { # : USB0 GFLADJ # Register : GUSB2PHYCFG @ 0XFE20C200

- # USB 2.0 Turnaround Time (USBTrdTim) Sets the turnaround time in PHY clocks. Specifies the response time for a MAC request to - # he Packet FIFO Controller (PFC) to fetch data from the DFIFO (SPRAM). The following are the required values for the minimum S - # C bus frequency of 60 MHz. USB turnaround time is a critical certification criteria when using long cables and five hub level - # . The required values for this field: - 4'h5: When the MAC interface is 16-bit UTMI+. - 4'h9: When the MAC interface is 8-bit - # UTMI+/ULPI. If SoC bus clock is less than 60 MHz, and USB turnaround time is not critical, this field can be set to a larger - # alue. Note: This field is valid only in device mode. + # USB 2.0 Turnaround Time (USBTrdTim) Sets the turnaround time in PHY cloc + # ks. Specifies the response time for a MAC request to the Packet FIFO Con + # troller (PFC) to fetch data from the DFIFO (SPRAM). The following are th + # e required values for the minimum SoC bus frequency of 60 MHz. USB turna + # round time is a critical certification criteria when using long cables a + # nd five hub levels. The required values for this field: - 4'h5: When the + # MAC interface is 16-bit UTMI+. - 4'h9: When the MAC interface is 8-bit + # UTMI+/ULPI. If SoC bus clock is less than 60 MHz, and USB turnaround tim + # e is not critical, this field can be set to a larger value. Note: This f + # ield is valid only in device mode. # PSU_USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM 0x9 - # Transceiver Delay: Enables a delay between the assertion of the UTMI/ULPI Transceiver Select signal (for HS) and the assertio - # of the TxValid signal during a HS Chirp. When this bit is set to 1, a delay (of approximately 2.5 us) is introduced from the - # time when the Transceiver Select is set to 2'b00 (HS) to the time the TxValid is driven to 0 for sending the chirp-K. This de - # ay is required for some UTMI/ULPI PHYs. Note: - If you enable the hibernation feature when the device core comes out of power - # off, you must re-initialize this bit with the appropriate value because the core does not save and restore this bit value dur - # ng hibernation. - This bit is valid only in device mode. + # Transceiver Delay: Enables a delay between the assertion of the UTMI/ULP + # I Transceiver Select signal (for HS) and the assertion of the TxValid si + # gnal during a HS Chirp. When this bit is set to 1, a delay (of approxima + # tely 2.5 us) is introduced from the time when the Transceiver Select is + # set to 2'b00 (HS) to the time the TxValid is driven to 0 for sending the + # chirp-K. This delay is required for some UTMI/ULPI PHYs. Note: - If you + # enable the hibernation feature when the device core comes out of power- + # off, you must re-initialize this bit with the appropriate value because + # the core does not save and restore this bit value during hibernation. - + # This bit is valid only in device mode. # PSU_USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY 0x0 - # Enable utmi_sleep_n and utmi_l1_suspend_n (EnblSlpM) The application uses this bit to control utmi_sleep_n and utmi_l1_suspen - # _n assertion to the PHY in the L1 state. - 1'b0: utmi_sleep_n and utmi_l1_suspend_n assertion from the core is not transferre - # to the external PHY. - 1'b1: utmi_sleep_n and utmi_l1_suspend_n assertion from the core is transferred to the external PHY. - # ote: This bit must be set high for Port0 if PHY is used. Note: In Device mode - Before issuing any device endpoint command wh - # n operating in 2.0 speeds, disable this bit and enable it after the command completes. Without disabling this bit, if a comma - # d is issued when the device is in L1 state and if mac2_clk (utmi_clk/ulpi_clk) is gated off, the command will not get complet - # d. + # Enable utmi_sleep_n and utmi_l1_suspend_n (EnblSlpM) The application use + # s this bit to control utmi_sleep_n and utmi_l1_suspend_n assertion to th + # e PHY in the L1 state. - 1'b0: utmi_sleep_n and utmi_l1_suspend_n assert + # ion from the core is not transferred to the external PHY. - 1'b1: utmi_s + # leep_n and utmi_l1_suspend_n assertion from the core is transferred to t + # he external PHY. Note: This bit must be set high for Port0 if PHY is use + # d. Note: In Device mode - Before issuing any device endpoint command whe + # n operating in 2.0 speeds, disable this bit and enable it after the comm + # and completes. Without disabling this bit, if a command is issued when t + # he device is in L1 state and if mac2_clk (utmi_clk/ulpi_clk) is gated of + # f, the command will not get completed. # PSU_USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM 0x0 - # USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial Transceiver Select The application uses this bit to select a high-speed P - # Y or a full-speed transceiver. - 1'b0: USB 2.0 high-speed UTMI+ or ULPI PHY. This bit is always 0, with Write Only access. - - # 'b1: USB 1.1 full-speed serial transceiver. This bit is always 1, with Write Only access. If both interface types are selecte - # in coreConsultant (that is, parameters' values are not zero), the application uses this bit to select the active interface i - # active, with Read-Write bit access. Note: USB 1.1 full-serial transceiver is not supported. This bit always reads as 1'b0. + # USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial Transceiver Select T + # he application uses this bit to select a high-speed PHY or a full-speed + # transceiver. - 1'b0: USB 2.0 high-speed UTMI+ or ULPI PHY. This bit is a + # lways 0, with Write Only access. - 1'b1: USB 1.1 full-speed serial trans + # ceiver. This bit is always 1, with Write Only access. If both interface + # types are selected in coreConsultant (that is, parameters' values are no + # t zero), the application uses this bit to select the active interface is + # active, with Read-Write bit access. Note: USB 1.1 full-serial transceiv + # er is not supported. This bit always reads as 1'b0. # PSU_USB3_0_XHCI_GUSB2PHYCFG_PHYSEL 0x0 - # Full-Speed Serial Interface Select (FSIntf) The application uses this bit to select a unidirectional or bidirectional USB 1.1 - # full-speed serial transceiver interface. - 1'b0: 6-pin unidirectional full-speed serial interface. This bit is set to 0 with - # ead Only access. - 1'b1: 3-pin bidirectional full-speed serial interface. This bit is set to 0 with Read Only access. Note: U - # B 1.1 full-speed serial interface is not supported. This bit always reads as 1'b0. + # Suspend USB2.0 HS/FS/LS PHY (SusPHY) When set, USB2.0 PHY enters Suspend + # mode if Suspend conditions are valid. For DRD/OTG configurations, it is + # recommended that this bit is set to 0 during coreConsultant configurati + # on. If it is set to 1, then the application must clear this bit after po + # wer-on reset. Application needs to set it to 1 after the core initializa + # tion completes. For all other configurations, this bit can be set to 1 d + # uring core configuration. Note: - In host mode, on reset, this bit is se + # t to 1. Software can override this bit after reset. - In device mode, be + # fore issuing any device endpoint command when operating in 2.0 speeds, d + # isable this bit and enable it after the command completes. If you issue + # a command without disabling this bit when the device is in L2 state and + # if mac2_clk (utmi_clk/ulpi_clk) is gated off, the command will not get c + # ompleted. + # PSU_USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20 0x1 + + # Full-Speed Serial Interface Select (FSIntf) The application uses this bi + # t to select a unidirectional or bidirectional USB 1.1 full-speed serial + # transceiver interface. - 1'b0: 6-pin unidirectional full-speed serial in + # terface. This bit is set to 0 with Read Only access. - 1'b1: 3-pin bidir + # ectional full-speed serial interface. This bit is set to 0 with Read Onl + # y access. Note: USB 1.1 full-speed serial interface is not supported. Th + # is bit always reads as 1'b0. # PSU_USB3_0_XHCI_GUSB2PHYCFG_FSINTF 0x0 - # ULPI or UTMI+ Select (ULPI_UTMI_Sel) The application uses this bit to select a UTMI+ or ULPI Interface. - 1'b0: UTMI+ Interfa - # e - 1'b1: ULPI Interface This bit is writable only if UTMI+ and ULPI is specified for High-Speed PHY Interface(s) in coreCons - # ltant configuration (DWC_USB3_HSPHY_INTERFACE = 3). Otherwise, this bit is read-only and the value depends on the interface s - # lected through DWC_USB3_HSPHY_INTERFACE. + # ULPI or UTMI+ Select (ULPI_UTMI_Sel) The application uses this bit to se + # lect a UTMI+ or ULPI Interface. - 1'b0: UTMI+ Interface - 1'b1: ULPI Int + # erface This bit is writable only if UTMI+ and ULPI is specified for High + # -Speed PHY Interface(s) in coreConsultant configuration (DWC_USB3_HSPHY_ + # INTERFACE = 3). Otherwise, this bit is read-only and the value depends o + # n the interface selected through DWC_USB3_HSPHY_INTERFACE. # PSU_USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL 0x1 - # PHY Interface (PHYIf) If UTMI+ is selected, the application uses this bit to configure the core to support a UTMI+ PHY with a - # 8- or 16-bit interface. - 1'b0: 8 bits - 1'b1: 16 bits ULPI Mode: 1'b0 Note: - All the enabled 2.0 ports must have the same - # lock frequency as Port0 clock frequency (utmi_clk[0]). - The UTMI 8-bit and 16-bit modes cannot be used together for differen - # ports at the same time (that is, all the ports must be in 8-bit mode, or all of them must be in 16-bit mode, at a time). - I - # any of the USB 2.0 ports is selected as ULPI port for operation, then all the USB 2.0 ports must be operating at 60 MHz. + # PHY Interface (PHYIf) If UTMI+ is selected, the application uses this bi + # t to configure the core to support a UTMI+ PHY with an 8- or 16-bit inte + # rface. - 1'b0: 8 bits - 1'b1: 16 bits ULPI Mode: 1'b0 Note: - All the en + # abled 2.0 ports must have the same clock frequency as Port0 clock freque + # ncy (utmi_clk[0]). - The UTMI 8-bit and 16-bit modes cannot be used toge + # ther for different ports at the same time (that is, all the ports must b + # e in 8-bit mode, or all of them must be in 16-bit mode, at a time). - If + # any of the USB 2.0 ports is selected as ULPI port for operation, then a + # ll the USB 2.0 ports must be operating at 60 MHz. # PSU_USB3_0_XHCI_GUSB2PHYCFG_PHYIF 0x0 - # HS/FS Timeout Calibration (TOutCal) The number of PHY clocks, as indicated by the application in this field, is multiplied by - # a bit-time factor; this factor is added to the high-speed/full-speed interpacket timeout duration in the core to account for - # dditional delays introduced by the PHY. This may be required, since the delay introduced by the PHY in generating the linesta - # e condition may vary among PHYs. The USB standard timeout value for high-speed operation is 736 to 816 (inclusive) bit times. - # The USB standard timeout value for full-speed operation is 16 to 18 (inclusive) bit times. The application must program this - # ield based on the speed of connection. The number of bit times added per PHY clock are: High-speed operation: - One 30-MHz PH - # clock = 16 bit times - One 60-MHz PHY clock = 8 bit times Full-speed operation: - One 30-MHz PHY clock = 0.4 bit times - One - # 60-MHz PHY clock = 0.2 bit times - One 48-MHz PHY clock = 0.25 bit times + # HS/FS Timeout Calibration (TOutCal) The number of PHY clocks, as indicat + # ed by the application in this field, is multiplied by a bit-time factor; + # this factor is added to the high-speed/full-speed interpacket timeout d + # uration in the core to account for additional delays introduced by the P + # HY. This may be required, since the delay introduced by the PHY in gener + # ating the linestate condition may vary among PHYs. The USB standard time + # out value for high-speed operation is 736 to 816 (inclusive) bit times. + # The USB standard timeout value for full-speed operation is 16 to 18 (inc + # lusive) bit times. The application must program this field based on the + # speed of connection. The number of bit times added per PHY clock are: Hi + # gh-speed operation: - One 30-MHz PHY clock = 16 bit times - One 60-MHz P + # HY clock = 8 bit times Full-speed operation: - One 30-MHz PHY clock = 0. + # 4 bit times - One 60-MHz PHY clock = 0.2 bit times - One 48-MHz PHY cloc + # k = 0.25 bit times # PSU_USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL 0x7 - # Global USB2 PHY Configuration Register The application must program this register before starting any transactions on either - # he SoC bus or the USB. In Device-only configurations, only one register is needed. In Host mode, per-port registers are imple - # ented. - #(OFFSET, MASK, VALUE) (0XFE20C200, 0x00003FBFU ,0x00002417U) */ - mask_write 0XFE20C200 0x00003FBF 0x00002417 + # ULPI External VBUS Drive (ULPIExtVbusDrv) Selects supply source to drive + # 5V on VBUS, in the ULPI PHY. - 1'b0: PHY drives VBUS with internal char + # ge pump (default). - 1'b1: PHY drives VBUS with an external supply. (Onl + # y when RTL parameter DWC_USB3_HSPHY_INTERFACE = 2 or 3) + # PSU_USB3_0_XHCI_GUSB2PHYCFG_ULPIEXTVBUSDRV 0x1 + + # Global USB2 PHY Configuration Register The application must program this + # register before starting any transactions on either the SoC bus or the + # USB. In Device-only configurations, only one register is needed. In Host + # mode, per-port registers are implemented. + #(OFFSET, MASK, VALUE) (0XFE20C200, 0x00023FFFU ,0x00022457U) */ + mask_write 0XFE20C200 0x00023FFF 0x00022457 # Register : GFLADJ @ 0XFE20C630

- # This field indicates the frame length adjustment to be applied when SOF/ITP counter is running on the ref_clk. This register - # alue is used to adjust the ITP interval when GCTL[SOFITPSYNC] is set to '1'; SOF and ITP interval when GLADJ.GFLADJ_REFCLK_LP - # _SEL is set to '1'. This field must be programmed to a non-zero value only if GFLADJ_REFCLK_LPM_SEL is set to '1' or GCTL.SOF - # TPSYNC is set to '1'. The value is derived as follows: FLADJ_REF_CLK_FLADJ=((125000/ref_clk_period_integer)-(125000/ref_clk_p - # riod)) * ref_clk_period where - the ref_clk_period_integer is the integer value of the ref_clk period got by truncating the d - # cimal (fractional) value that is programmed in the GUCTL.REF_CLK_PERIOD field. - the ref_clk_period is the ref_clk period inc - # uding the fractional value. Examples: If the ref_clk is 24 MHz then - GUCTL.REF_CLK_PERIOD = 41 - GFLADJ.GLADJ_REFCLK_FLADJ = - # ((125000/41)-(125000/41.6666))*41.6666 = 2032 (ignoring the fractional value) If the ref_clk is 48 MHz then - GUCTL.REF_CLK_P - # RIOD = 20 - GFLADJ.GLADJ_REFCLK_FLADJ = ((125000/20)-(125000/20.8333))*20.8333 = 5208 (ignoring the fractional value) + # This field indicates the frame length adjustment to be applied when SOF/ + # ITP counter is running on the ref_clk. This register value is used to ad + # just the ITP interval when GCTL[SOFITPSYNC] is set to '1'; SOF and ITP i + # nterval when GLADJ.GFLADJ_REFCLK_LPM_SEL is set to '1'. This field must + # be programmed to a non-zero value only if GFLADJ_REFCLK_LPM_SEL is set t + # o '1' or GCTL.SOFITPSYNC is set to '1'. The value is derived as follows: + # FLADJ_REF_CLK_FLADJ=((125000/ref_clk_period_integer)-(125000/ref_clk_pe + # riod)) * ref_clk_period where - the ref_clk_period_integer is the intege + # r value of the ref_clk period got by truncating the decimal (fractional) + # value that is programmed in the GUCTL.REF_CLK_PERIOD field. - the ref_c + # lk_period is the ref_clk period including the fractional value. Examples + # : If the ref_clk is 24 MHz then - GUCTL.REF_CLK_PERIOD = 41 - GFLADJ.GLA + # DJ_REFCLK_FLADJ = ((125000/41)-(125000/41.6666))*41.6666 = 2032 (ignorin + # g the fractional value) If the ref_clk is 48 MHz then - GUCTL.REF_CLK_PE + # RIOD = 20 - GFLADJ.GLADJ_REFCLK_FLADJ = ((125000/20)-(125000/20.8333))*2 + # 0.8333 = 5208 (ignoring the fractional value) # PSU_USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ 0x0 - # Global Frame Length Adjustment Register This register provides options for the software to control the core behavior with res - # ect to SOF (Start of Frame) and ITP (Isochronous Timestamp Packet) timers and frame timer functionality. It provides an optio - # to override the fladj_30mhz_reg sideband signal. In addition, it enables running SOF or ITP frame timer counters completely - # rom the ref_clk. This facilitates hardware LPM in host mode with the SOF or ITP counters being run from the ref_clk signal. + # Global Frame Length Adjustment Register This register provides options f + # or the software to control the core behavior with respect to SOF (Start + # of Frame) and ITP (Isochronous Timestamp Packet) timers and frame timer + # functionality. It provides an option to override the fladj_30mhz_reg sid + # eband signal. In addition, it enables running SOF or ITP frame timer cou + # nters completely from the ref_clk. This facilitates hardware LPM in host + # mode with the SOF or ITP counters being run from the ref_clk signal. #(OFFSET, MASK, VALUE) (0XFE20C630, 0x003FFF00U ,0x00000000U) */ mask_write 0XFE20C630 0x003FFF00 0x00000000 + # Register : GUCTL1 @ 0XFE20C11C

+ + # When this bit is set to '0', termsel, xcvrsel will become 0 during end o + # f resume while the opmode will become 0 once controller completes end of + # resume and enters U0 state (2 separate commandswill be issued). When th + # is bit is set to '1', all the termsel, xcvrsel, opmode becomes 0 during + # end of resume itself (only 1 command will be issued) + # PSU_USB3_0_XHCI_GUCTL1_RESUME_TERMSEL_XCVRSEL_UNIFY 0x1 + + # Reserved + # PSU_USB3_0_XHCI_GUCTL1_RESERVED_9 0x1 + + # Global User Control Register 1 + #(OFFSET, MASK, VALUE) (0XFE20C11C, 0x00000600U ,0x00000600U) */ + mask_write 0XFE20C11C 0x00000600 0x00000600 + # Register : GUCTL @ 0XFE20C12C

+ + # Host IN Auto Retry (USBHstInAutoRetryEn) When set, this field enables th + # e Auto Retry feature. For IN transfers (non-isochronous) that encounter + # data packets with CRC errors or internal overrun scenarios, the auto ret + # ry feature causes the Host core to reply to the device with a non-termin + # ating retry ACK (that is, an ACK transaction packet with Retry = 1 and N + # umP != 0). If the Auto Retry feature is disabled (default), the core wil + # l respond with a terminating retry ACK (that is, an ACK transaction pack + # et with Retry = 1 and NumP = 0). - 1'b0: Auto Retry Disabled - 1'b1: Aut + # o Retry Enabled Note: This bit is also applicable to the device mode. + # PSU_USB3_0_XHCI_GUCTL_USBHSTINAUTORETRYEN 0x1 + + # Global User Control Register: This register provides a few options for t + # he software to control the core behavior in the Host mode. Most of the o + # ptions are used to improve host inter-operability with different devices + # . + #(OFFSET, MASK, VALUE) (0XFE20C12C, 0x00004000U ,0x00004000U) */ + mask_write 0XFE20C12C 0x00004000 0x00004000 # : UPDATING TWO PCIE REGISTERS DEFAULT VALUES, AS THESE REGISTERS HAVE INCORRECT RESET VALUES IN SILICON. # Register : ATTR_25 @ 0XFD480064

- # If TRUE Completion Timeout Disable is supported. This is required to be TRUE for Endpoint and either setting allowed for Root - # ports. Drives Device Capability 2 [4]; EP=0x0001; RP=0x0001 + # If TRUE Completion Timeout Disable is supported. This is required to be + # TRUE for Endpoint and either setting allowed for Root ports. Drives Devi + # ce Capability 2 [4]; EP=0x0001; RP=0x0001 # PSU_PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED 0X1 # ATTR_25 @@ -13557,12 +15852,16 @@ set psu_resetout_init_data { # : PCIE SETTINGS # Register : ATTR_7 @ 0XFD48001C

- # Specifies mask/settings for Base Address Register (BAR) 0. If BAR is not to be implemented, set to 32'h00000000. Bits are def - # ned as follows: Memory Space BAR [0] = Mem Space Indicator (set to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = - # Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory a - # erture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR1,BAR0\'7d to 1. IO Space BAR 0] = IO Space Indicator - # set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o apert - # re size in bytes.; EP=0x0004; RP=0x0000 + # Specifies mask/settings for Base Address Register (BAR) 0. If BAR is not + # to be implemented, set to 32'h00000000. Bits are defined as follows: Me + # mory Space BAR [0] = Mem Space Indicator (set to 0) [2:1] = Type field ( + # 10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask + # for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to 1, w + # here 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63: + # n bits of \'7bBAR1,BAR0\'7d to 1. IO Space BAR 0] = IO Space Indicator ( + # set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of B + # AR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; + # EP=0x0004; RP=0x0000 # PSU_PCIE_ATTRIB_ATTR_7_ATTR_BAR0 0x0 # ATTR_7 @@ -13570,12 +15869,16 @@ set psu_resetout_init_data { mask_write 0XFD48001C 0x0000FFFF 0x00000000 # Register : ATTR_8 @ 0XFD480020

- # Specifies mask/settings for Base Address Register (BAR) 0. If BAR is not to be implemented, set to 32'h00000000. Bits are def - # ned as follows: Memory Space BAR [0] = Mem Space Indicator (set to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = - # Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory a - # erture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR1,BAR0\'7d to 1. IO Space BAR 0] = IO Space Indicator - # set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o apert - # re size in bytes.; EP=0xFFF0; RP=0x0000 + # Specifies mask/settings for Base Address Register (BAR) 0. If BAR is not + # to be implemented, set to 32'h00000000. Bits are defined as follows: Me + # mory Space BAR [0] = Mem Space Indicator (set to 0) [2:1] = Type field ( + # 10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask + # for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to 1, w + # here 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63: + # n bits of \'7bBAR1,BAR0\'7d to 1. IO Space BAR 0] = IO Space Indicator ( + # set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of B + # AR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; + # EP=0xFFF0; RP=0x0000 # PSU_PCIE_ATTRIB_ATTR_8_ATTR_BAR0 0x0 # ATTR_8 @@ -13583,13 +15886,18 @@ set psu_resetout_init_data { mask_write 0XFD480020 0x0000FFFF 0x00000000 # Register : ATTR_9 @ 0XFD480024

- # Specifies mask/settings for Base Address Register (BAR) 1 if BAR0 is a 32-bit BAR, or the upper bits of \'7bBAR1,BAR0\'7d if - # AR0 is a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR0 description if this functions as the uppe - # bits of a 64-bit BAR. Bits are defined as follows: Memory Space BAR (not upper bits of BAR0) [0] = Mem Space Indicator (set - # o 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if - # 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of - # '7bBAR2,BAR1\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable b - # ts of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000 + # Specifies mask/settings for Base Address Register (BAR) 1 if BAR0 is a 3 + # 2-bit BAR, or the upper bits of \'7bBAR1,BAR0\'7d if BAR0 is a 64-bit BA + # R. If BAR is not to be implemented, set to 32'h00000000. See BAR0 descri + # ption if this functions as the upper bits of a 64-bit BAR. Bits are defi + # ned as follows: Memory Space BAR (not upper bits of BAR0) [0] = Mem Spac + # e Indicator (set to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) + # [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if + # 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size + # in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR2,BAR1\'7d t + # o 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set + # to 0) [31:2] = Mask for writable bits of BAR; set uppermost 31:n bits t + # o 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000 # PSU_PCIE_ATTRIB_ATTR_9_ATTR_BAR1 0x0 # ATTR_9 @@ -13597,13 +15905,18 @@ set psu_resetout_init_data { mask_write 0XFD480024 0x0000FFFF 0x00000000 # Register : ATTR_10 @ 0XFD480028

- # Specifies mask/settings for Base Address Register (BAR) 1 if BAR0 is a 32-bit BAR, or the upper bits of \'7bBAR1,BAR0\'7d if - # AR0 is a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR0 description if this functions as the uppe - # bits of a 64-bit BAR. Bits are defined as follows: Memory Space BAR (not upper bits of BAR0) [0] = Mem Space Indicator (set - # o 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if - # 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of - # '7bBAR2,BAR1\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable b - # ts of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000 + # Specifies mask/settings for Base Address Register (BAR) 1 if BAR0 is a 3 + # 2-bit BAR, or the upper bits of \'7bBAR1,BAR0\'7d if BAR0 is a 64-bit BA + # R. If BAR is not to be implemented, set to 32'h00000000. See BAR0 descri + # ption if this functions as the upper bits of a 64-bit BAR. Bits are defi + # ned as follows: Memory Space BAR (not upper bits of BAR0) [0] = Mem Spac + # e Indicator (set to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) + # [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if + # 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size + # in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR2,BAR1\'7d t + # o 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set + # to 0) [31:2] = Mask for writable bits of BAR; set uppermost 31:n bits t + # o 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000 # PSU_PCIE_ATTRIB_ATTR_10_ATTR_BAR1 0x0 # ATTR_10 @@ -13611,14 +15924,20 @@ set psu_resetout_init_data { mask_write 0XFD480028 0x0000FFFF 0x00000000 # Register : ATTR_11 @ 0XFD48002C

- # For an endpoint, specifies mask/settings for Base Address Register (BAR) 2 if BAR1 is a 32-bit BAR, or the upper bits of \'7b - # AR2,BAR1\'7d if BAR1 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR1 descri - # tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to 00FF_FFFF. For an endpoin - # , bits are defined as follows: Memory Space BAR (not upper bits of BAR1) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi - # ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe - # most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR3,BAR2\'7d to - # . IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper - # ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0x0004; RP=0xFFFF + # For an endpoint, specifies mask/settings for Base Address Register (BAR) + # 2 if BAR1 is a 32-bit BAR, or the upper bits of \'7bBAR2,BAR1\'7d if BA + # R1 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + # et to 32'h00000000. See BAR1 description if this functions as the upper + # bits of a 64-bit BAR. For a switch or root: This must be set to 00FF_FFF + # F. For an endpoint, bits are defined as follows: Memory Space BAR (not u + # pper bits of BAR1) [0] = Mem Space Indicator (set to 0) [2:1] = Type fie + # ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = M + # ask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to + # 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost + # 63:n bits of \'7bBAR3,BAR2\'7d to 1. IO Space BAR 0] = IO Space Indicat + # or (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits + # of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in byt + # es.; EP=0x0004; RP=0xFFFF # PSU_PCIE_ATTRIB_ATTR_11_ATTR_BAR2 0xFFFF # ATTR_11 @@ -13626,14 +15945,20 @@ set psu_resetout_init_data { mask_write 0XFD48002C 0x0000FFFF 0x0000FFFF # Register : ATTR_12 @ 0XFD480030

- # For an endpoint, specifies mask/settings for Base Address Register (BAR) 2 if BAR1 is a 32-bit BAR, or the upper bits of \'7b - # AR2,BAR1\'7d if BAR1 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR1 descri - # tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to 00FF_FFFF. For an endpoin - # , bits are defined as follows: Memory Space BAR (not upper bits of BAR1) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi - # ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe - # most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR3,BAR2\'7d to - # . IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper - # ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFF0; RP=0x00FF + # For an endpoint, specifies mask/settings for Base Address Register (BAR) + # 2 if BAR1 is a 32-bit BAR, or the upper bits of \'7bBAR2,BAR1\'7d if BA + # R1 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + # et to 32'h00000000. See BAR1 description if this functions as the upper + # bits of a 64-bit BAR. For a switch or root: This must be set to 00FF_FFF + # F. For an endpoint, bits are defined as follows: Memory Space BAR (not u + # pper bits of BAR1) [0] = Mem Space Indicator (set to 0) [2:1] = Type fie + # ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = M + # ask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to + # 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost + # 63:n bits of \'7bBAR3,BAR2\'7d to 1. IO Space BAR 0] = IO Space Indicat + # or (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits + # of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in byt + # es.; EP=0xFFF0; RP=0x00FF # PSU_PCIE_ATTRIB_ATTR_12_ATTR_BAR2 0xFF # ATTR_12 @@ -13641,15 +15966,22 @@ set psu_resetout_init_data { mask_write 0XFD480030 0x0000FFFF 0x000000FF # Register : ATTR_13 @ 0XFD480034

- # For an endpoint, specifies mask/settings for Base Address Register (BAR) 3 if BAR2 is a 32-bit BAR, or the upper bits of \'7b - # AR3,BAR2\'7d if BAR2 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR2 descri - # tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: FFFF_0000 = IO Limit/Bas - # Registers not implemented FFFF_F0F0 = IO Limit/Base Registers use 16-bit decode FFFF_F1F1 = IO Limit/Base Registers use 32-b - # t decode For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of BAR2) [0] = Mem Space Indicator (s - # t to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; - # if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits - # f \'7bBAR4,BAR3\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writabl - # bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000 + # For an endpoint, specifies mask/settings for Base Address Register (BAR) + # 3 if BAR2 is a 32-bit BAR, or the upper bits of \'7bBAR3,BAR2\'7d if BA + # R2 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + # et to 32'h00000000. See BAR2 description if this functions as the upper + # bits of a 64-bit BAR. For a switch or root, this must be set to: FFFF_00 + # 00 = IO Limit/Base Registers not implemented FFFF_F0F0 = IO Limit/Base R + # egisters use 16-bit decode FFFF_F1F1 = IO Limit/Base Registers use 32-bi + # t decode For an endpoint, bits are defined as follows: Memory Space BAR + # (not upper bits of BAR2) [0] = Mem Space Indicator (set to 0) [2:1] = Ty + # pe field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31: + # 4] = Mask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bi + # ts to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set upp + # ermost 63:n bits of \'7bBAR4,BAR3\'7d to 1. IO Space BAR 0] = IO Space I + # ndicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable + # bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size + # in bytes.; EP=0xFFFF; RP=0x0000 # PSU_PCIE_ATTRIB_ATTR_13_ATTR_BAR3 0x0 # ATTR_13 @@ -13657,15 +15989,22 @@ set psu_resetout_init_data { mask_write 0XFD480034 0x0000FFFF 0x00000000 # Register : ATTR_14 @ 0XFD480038

- # For an endpoint, specifies mask/settings for Base Address Register (BAR) 3 if BAR2 is a 32-bit BAR, or the upper bits of \'7b - # AR3,BAR2\'7d if BAR2 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR2 descri - # tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: FFFF_0000 = IO Limit/Bas - # Registers not implemented FFFF_F0F0 = IO Limit/Base Registers use 16-bit decode FFFF_F1F1 = IO Limit/Base Registers use 32-b - # t decode For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of BAR2) [0] = Mem Space Indicator (s - # t to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; - # if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits - # f \'7bBAR4,BAR3\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writabl - # bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0xFFFF + # For an endpoint, specifies mask/settings for Base Address Register (BAR) + # 3 if BAR2 is a 32-bit BAR, or the upper bits of \'7bBAR3,BAR2\'7d if BA + # R2 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + # et to 32'h00000000. See BAR2 description if this functions as the upper + # bits of a 64-bit BAR. For a switch or root, this must be set to: FFFF_00 + # 00 = IO Limit/Base Registers not implemented FFFF_F0F0 = IO Limit/Base R + # egisters use 16-bit decode FFFF_F1F1 = IO Limit/Base Registers use 32-bi + # t decode For an endpoint, bits are defined as follows: Memory Space BAR + # (not upper bits of BAR2) [0] = Mem Space Indicator (set to 0) [2:1] = Ty + # pe field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31: + # 4] = Mask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bi + # ts to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set upp + # ermost 63:n bits of \'7bBAR4,BAR3\'7d to 1. IO Space BAR 0] = IO Space I + # ndicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable + # bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size + # in bytes.; EP=0xFFFF; RP=0xFFFF # PSU_PCIE_ATTRIB_ATTR_14_ATTR_BAR3 0xFFFF # ATTR_14 @@ -13673,14 +16012,20 @@ set psu_resetout_init_data { mask_write 0XFD480038 0x0000FFFF 0x0000FFFF # Register : ATTR_15 @ 0XFD48003C

- # For an endpoint, specifies mask/settings for Base Address Register (BAR) 4 if BAR3 is a 32-bit BAR, or the upper bits of \'7b - # AR4,BAR3\'7d if BAR3 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR3 descri - # tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to FFF0_FFF0. For an endpoin - # , bits are defined as follows: Memory Space BAR (not upper bits of BAR3) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi - # ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe - # most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR5,BAR4\'7d to - # . IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper - # ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0x0004; RP=0xFFF0 + # For an endpoint, specifies mask/settings for Base Address Register (BAR) + # 4 if BAR3 is a 32-bit BAR, or the upper bits of \'7bBAR4,BAR3\'7d if BA + # R3 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + # et to 32'h00000000. See BAR3 description if this functions as the upper + # bits of a 64-bit BAR. For a switch or root: This must be set to FFF0_FFF + # 0. For an endpoint, bits are defined as follows: Memory Space BAR (not u + # pper bits of BAR3) [0] = Mem Space Indicator (set to 0) [2:1] = Type fie + # ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = M + # ask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to + # 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost + # 63:n bits of \'7bBAR5,BAR4\'7d to 1. IO Space BAR 0] = IO Space Indicat + # or (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits + # of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in byt + # es.; EP=0x0004; RP=0xFFF0 # PSU_PCIE_ATTRIB_ATTR_15_ATTR_BAR4 0xFFF0 # ATTR_15 @@ -13688,14 +16033,20 @@ set psu_resetout_init_data { mask_write 0XFD48003C 0x0000FFFF 0x0000FFF0 # Register : ATTR_16 @ 0XFD480040

- # For an endpoint, specifies mask/settings for Base Address Register (BAR) 4 if BAR3 is a 32-bit BAR, or the upper bits of \'7b - # AR4,BAR3\'7d if BAR3 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR3 descri - # tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to FFF0_FFF0. For an endpoin - # , bits are defined as follows: Memory Space BAR (not upper bits of BAR3) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi - # ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe - # most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR5,BAR4\'7d to - # . IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper - # ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFF0; RP=0xFFF0 + # For an endpoint, specifies mask/settings for Base Address Register (BAR) + # 4 if BAR3 is a 32-bit BAR, or the upper bits of \'7bBAR4,BAR3\'7d if BA + # R3 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + # et to 32'h00000000. See BAR3 description if this functions as the upper + # bits of a 64-bit BAR. For a switch or root: This must be set to FFF0_FFF + # 0. For an endpoint, bits are defined as follows: Memory Space BAR (not u + # pper bits of BAR3) [0] = Mem Space Indicator (set to 0) [2:1] = Type fie + # ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = M + # ask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to + # 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost + # 63:n bits of \'7bBAR5,BAR4\'7d to 1. IO Space BAR 0] = IO Space Indicat + # or (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits + # of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in byt + # es.; EP=0xFFF0; RP=0xFFF0 # PSU_PCIE_ATTRIB_ATTR_16_ATTR_BAR4 0xFFF0 # ATTR_16 @@ -13703,15 +16054,22 @@ set psu_resetout_init_data { mask_write 0XFD480040 0x0000FFFF 0x0000FFF0 # Register : ATTR_17 @ 0XFD480044

- # For an endpoint, specifies mask/settings for Base Address Register (BAR) 5 if BAR4 is a 32-bit BAR, or the upper bits of \'7b - # AR5,BAR4\'7d if BAR4 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR4 descri - # tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: 0000_0000 = Prefetchable - # Memory Limit/Base Registers not implemented FFF0_FFF0 = 32-bit Prefetchable Memory Limit/Base implemented FFF1_FFF1 = 64-bit - # refetchable Memory Limit/Base implemented For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of B - # R4) [0] = Mem Space Indicator (set to 0) [2:1] = Type field (00 for 32-bit; BAR5 cannot be lower part of a 64-bit BAR) [3] = - # refetchable (0 or 1) [31:4] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=memory aperture size in - # ytes. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set u - # permost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0xFFF1 + # For an endpoint, specifies mask/settings for Base Address Register (BAR) + # 5 if BAR4 is a 32-bit BAR, or the upper bits of \'7bBAR5,BAR4\'7d if BA + # R4 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + # et to 32'h00000000. See BAR4 description if this functions as the upper + # bits of a 64-bit BAR. For a switch or root, this must be set to: 0000_00 + # 00 = Prefetchable Memory Limit/Base Registers not implemented FFF0_FFF0 + # = 32-bit Prefetchable Memory Limit/Base implemented FFF1_FFF1 = 64-bit P + # refetchable Memory Limit/Base implemented For an endpoint, bits are defi + # ned as follows: Memory Space BAR (not upper bits of BAR4) [0] = Mem Spac + # e Indicator (set to 0) [2:1] = Type field (00 for 32-bit; BAR5 cannot be + # lower part of a 64-bit BAR) [3] = Prefetchable (0 or 1) [31:4] = Mask f + # or writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=memory + # aperture size in bytes. IO Space BAR 0] = IO Space Indicator (set to 1) + # [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set up + # permost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF + # ; RP=0xFFF1 # PSU_PCIE_ATTRIB_ATTR_17_ATTR_BAR5 0xFFF1 # ATTR_17 @@ -13719,15 +16077,22 @@ set psu_resetout_init_data { mask_write 0XFD480044 0x0000FFFF 0x0000FFF1 # Register : ATTR_18 @ 0XFD480048

- # For an endpoint, specifies mask/settings for Base Address Register (BAR) 5 if BAR4 is a 32-bit BAR, or the upper bits of \'7b - # AR5,BAR4\'7d if BAR4 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR4 descri - # tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: 0000_0000 = Prefetchable - # Memory Limit/Base Registers not implemented FFF0_FFF0 = 32-bit Prefetchable Memory Limit/Base implemented FFF1_FFF1 = 64-bit - # refetchable Memory Limit/Base implemented For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of B - # R4) [0] = Mem Space Indicator (set to 0) [2:1] = Type field (00 for 32-bit; BAR5 cannot be lower part of a 64-bit BAR) [3] = - # refetchable (0 or 1) [31:4] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=memory aperture size in - # ytes. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set u - # permost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0xFFF1 + # For an endpoint, specifies mask/settings for Base Address Register (BAR) + # 5 if BAR4 is a 32-bit BAR, or the upper bits of \'7bBAR5,BAR4\'7d if BA + # R4 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + # et to 32'h00000000. See BAR4 description if this functions as the upper + # bits of a 64-bit BAR. For a switch or root, this must be set to: 0000_00 + # 00 = Prefetchable Memory Limit/Base Registers not implemented FFF0_FFF0 + # = 32-bit Prefetchable Memory Limit/Base implemented FFF1_FFF1 = 64-bit P + # refetchable Memory Limit/Base implemented For an endpoint, bits are defi + # ned as follows: Memory Space BAR (not upper bits of BAR4) [0] = Mem Spac + # e Indicator (set to 0) [2:1] = Type field (00 for 32-bit; BAR5 cannot be + # lower part of a 64-bit BAR) [3] = Prefetchable (0 or 1) [31:4] = Mask f + # or writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=memory + # aperture size in bytes. IO Space BAR 0] = IO Space Indicator (set to 1) + # [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set up + # permost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF + # ; RP=0xFFF1 # PSU_PCIE_ATTRIB_ATTR_18_ATTR_BAR5 0xFFF1 # ATTR_18 @@ -13735,13 +16100,17 @@ set psu_resetout_init_data { mask_write 0XFD480048 0x0000FFFF 0x0000FFF1 # Register : ATTR_27 @ 0XFD48006C

- # Specifies maximum payload supported. Valid settings are: 0- 128 bytes, 1- 256 bytes, 2- 512 bytes, 3- 1024 bytes. Transferred - # to the Device Capabilities register. The values: 4-2048 bytes, 5- 4096 bytes are not supported; EP=0x0001; RP=0x0001 + # Specifies maximum payload supported. Valid settings are: 0- 128 bytes, 1 + # - 256 bytes, 2- 512 bytes, 3- 1024 bytes. Transferred to the Device Capa + # bilities register. The values: 4-2048 bytes, 5- 4096 bytes are not suppo + # rted; EP=0x0001; RP=0x0001 # PSU_PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED 1 - # Endpoint L1 Acceptable Latency. Records the latency that the endpoint can withstand on transitions from L1 state to L0 (if L1 - # state supported). Valid settings are: 0h less than 1us, 1h 1 to 2us, 2h 2 to 4us, 3h 4 to 8us, 4h 8 to 16us, 5h 16 to 32us, 6 - # 32 to 64us, 7h more than 64us. For Endpoints only. Must be 0h for other devices.; EP=0x0007; RP=0x0000 + # Endpoint L1 Acceptable Latency. Records the latency that the endpoint ca + # n withstand on transitions from L1 state to L0 (if L1 state supported). + # Valid settings are: 0h less than 1us, 1h 1 to 2us, 2h 2 to 4us, 3h 4 to + # 8us, 4h 8 to 16us, 5h 16 to 32us, 6h 32 to 64us, 7h more than 64us. For + # Endpoints only. Must be 0h for other devices.; EP=0x0007; RP=0x0000 # PSU_PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY 0x0 # ATTR_27 @@ -13749,14 +16118,18 @@ set psu_resetout_init_data { mask_write 0XFD48006C 0x00000738 0x00000100 # Register : ATTR_50 @ 0XFD4800C8

- # Identifies the type of device/port as follows: 0000b PCI Express Endpoint device, 0001b Legacy PCI Express Endpoint device, 0 - # 00b Root Port of PCI Express Root Complex, 0101b Upstream Port of PCI Express Switch, 0110b Downstream Port of PCI Express Sw - # tch, 0111b PCIE Express to PCI/PCI-X Bridge, 1000b PCI/PCI-X to PCI Express Bridge. Transferred to PCI Express Capabilities r - # gister. Must be consistent with IS_SWITCH and UPSTREAM_FACING settings.; EP=0x0000; RP=0x0004 + # Identifies the type of device/port as follows: 0000b PCI Express Endpoin + # t device, 0001b Legacy PCI Express Endpoint device, 0100b Root Port of P + # CI Express Root Complex, 0101b Upstream Port of PCI Express Switch, 0110 + # b Downstream Port of PCI Express Switch, 0111b PCIE Express to PCI/PCI-X + # Bridge, 1000b PCI/PCI-X to PCI Express Bridge. Transferred to PCI Expre + # ss Capabilities register. Must be consistent with IS_SWITCH and UPSTREAM + # _FACING settings.; EP=0x0000; RP=0x0004 # PSU_PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE 4 - # PCIe Capability's Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capab - # lity.; EP=0x009C; RP=0x0000 + # PCIe Capability's Next Capability Offset pointer to the next item in the + # capabilities list, or 00h if this is the final capability.; EP=0x009C; + # RP=0x0000 # PSU_PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR 0 # ATTR_50 @@ -13764,8 +16137,9 @@ set psu_resetout_init_data { mask_write 0XFD4800C8 0x0000FFF0 0x00000040 # Register : ATTR_105 @ 0XFD4801A4

- # Number of credits that should be advertised for Completion data received on Virtual Channel 0. The bytes advertised must be l - # ss than or equal to the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0172; RP=0x00CD + # Number of credits that should be advertised for Completion data received + # on Virtual Channel 0. The bytes advertised must be less than or equal t + # o the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0172; RP=0x00CD # PSU_PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD 0xCD # ATTR_105 @@ -13773,13 +16147,16 @@ set psu_resetout_init_data { mask_write 0XFD4801A4 0x000007FF 0x000000CD # Register : ATTR_106 @ 0XFD4801A8

- # Number of credits that should be advertised for Completion headers received on Virtual Channel 0. The sum of the posted, non - # osted, and completion header credits must be <= 80; EP=0x0048; RP=0x0024 + # Number of credits that should be advertised for Completion headers recei + # ved on Virtual Channel 0. The sum of the posted, non posted, and complet + # ion header credits must be <= 80; EP=0x0048; RP=0x0024 # PSU_PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH 0x24 - # Number of credits that should be advertised for Non-Posted headers received on Virtual Channel 0. The number of non posted da - # a credits advertised by the block is equal to the number of non posted header credits. The sum of the posted, non posted, and - # completion header credits must be <= 80; EP=0x0004; RP=0x000C + # Number of credits that should be advertised for Non-Posted headers recei + # ved on Virtual Channel 0. The number of non posted data credits advertis + # ed by the block is equal to the number of non posted header credits. The + # sum of the posted, non posted, and completion header credits must be <= + # 80; EP=0x0004; RP=0x000C # PSU_PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH 0xC # ATTR_106 @@ -13787,10 +16164,13 @@ set psu_resetout_init_data { mask_write 0XFD4801A8 0x00003FFF 0x00000624 # Register : ATTR_107 @ 0XFD4801AC

- # Number of credits that should be advertised for Non-Posted data received on Virtual Channel 0. The number of non posted data - # redits advertised by the block is equal to two times the number of non posted header credits if atomic operations are support - # d or is equal to the number of non posted header credits if atomic operations are not supported. The bytes advertised must be - # less than or equal to the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0008; RP=0x0018 + # Number of credits that should be advertised for Non-Posted data received + # on Virtual Channel 0. The number of non posted data credits advertised + # by the block is equal to two times the number of non posted header credi + # ts if atomic operations are supported or is equal to the number of non p + # osted header credits if atomic operations are not supported. The bytes a + # dvertised must be less than or equal to the bram bytes available. See VC + # 0_RX_RAM_LIMIT; EP=0x0008; RP=0x0018 # PSU_PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD 0x18 # ATTR_107 @@ -13798,8 +16178,9 @@ set psu_resetout_init_data { mask_write 0XFD4801AC 0x000007FF 0x00000018 # Register : ATTR_108 @ 0XFD4801B0

- # Number of credits that should be advertised for Posted data received on Virtual Channel 0. The bytes advertised must be less - # han or equal to the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0020; RP=0x00B5 + # Number of credits that should be advertised for Posted data received on + # Virtual Channel 0. The bytes advertised must be less than or equal to th + # e bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0020; RP=0x00B5 # PSU_PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD 0xB5 # ATTR_108 @@ -13807,23 +16188,27 @@ set psu_resetout_init_data { mask_write 0XFD4801B0 0x000007FF 0x000000B5 # Register : ATTR_109 @ 0XFD4801B4

- # Not currently in use. Invert ECRC generated by block when trn_tecrc_gen_n and trn_terrfwd_n are asserted.; EP=0x0000; RP=0x00 - # 0 + # Not currently in use. Invert ECRC generated by block when trn_tecrc_gen_ + # n and trn_terrfwd_n are asserted.; EP=0x0000; RP=0x0000 # PSU_PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV 0x0 - # Enables td bit clear and ECRC trim on received TLP's FALSE == don't trim TRUE == trim.; EP=0x0001; RP=0x0001 + # Enables td bit clear and ECRC trim on received TLP's FALSE == don't trim + # TRUE == trim.; EP=0x0001; RP=0x0001 # PSU_PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM 0x1 - # Enables ECRC check on received TLP's 0 == don't check 1 == always check 3 == check if enabled by ECRC check enable bit of AER - # cap structure; EP=0x0003; RP=0x0003 + # Enables ECRC check on received TLP's 0 == don't check 1 == always check + # 3 == check if enabled by ECRC check enable bit of AER cap structure; EP= + # 0x0003; RP=0x0003 # PSU_PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK 0x3 - # Index of last packet buffer used by TX TLM (i.e. number of buffers - 1). Calculated from max payload size supported and the n - # mber of brams configured for transmit; EP=0x001C; RP=0x001C + # Index of last packet buffer used by TX TLM (i.e. number of buffers - 1). + # Calculated from max payload size supported and the number of brams conf + # igured for transmit; EP=0x001C; RP=0x001C # PSU_PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET 0x1c - # Number of credits that should be advertised for Posted headers received on Virtual Channel 0. The sum of the posted, non post - # d, and completion header credits must be <= 80; EP=0x0004; RP=0x0020 + # Number of credits that should be advertised for Posted headers received + # on Virtual Channel 0. The sum of the posted, non posted, and completion + # header credits must be <= 80; EP=0x0004; RP=0x0020 # PSU_PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH 0x20 # ATTR_109 @@ -13831,8 +16216,10 @@ set psu_resetout_init_data { mask_write 0XFD4801B4 0x0000FFFF 0x00007E20 # Register : ATTR_34 @ 0XFD480088

- # Specifies values to be transferred to Header Type register. Bit 7 should be set to '0' indicating single-function device. Bit - # 0 identifies header as Type 0 or Type 1, with '0' indicating a Type 0 header.; EP=0x0000; RP=0x0001 + # Specifies values to be transferred to Header Type register. Bit 7 should + # be set to '0' indicating single-function device. Bit 0 identifies heade + # r as Type 0 or Type 1, with '0' indicating a Type 0 header.; EP=0x0000; + # RP=0x0001 # PSU_PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE 0x1 # ATTR_34 @@ -13840,8 +16227,9 @@ set psu_resetout_init_data { mask_write 0XFD480088 0x000000FF 0x00000001 # Register : ATTR_53 @ 0XFD4800D4

- # PM Capability's Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capabil - # ty.; EP=0x0048; RP=0x0060 + # PM Capability's Next Capability Offset pointer to the next item in the c + # apabilities list, or 00h if this is the final capability.; EP=0x0048; RP + # =0x0060 # PSU_PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR 0x60 # ATTR_53 @@ -13849,20 +16237,24 @@ set psu_resetout_init_data { mask_write 0XFD4800D4 0x000000FF 0x00000060 # Register : ATTR_41 @ 0XFD4800A4

- # MSI Per-Vector Masking Capable. The value is transferred to the MSI Control Register[8]. When set, adds Mask and Pending Dwor - # to Cap structure; EP=0x0000; RP=0x0000 + # MSI Per-Vector Masking Capable. The value is transferred to the MSI Cont + # rol Register[8]. When set, adds Mask and Pending Dword to Cap structure; + # EP=0x0000; RP=0x0000 # PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE 0x0 - # Indicates that the MSI structures exists. If this is FALSE, then the MSI structure cannot be accessed via either the link or - # he management port.; EP=0x0001; RP=0x0000 + # Indicates that the MSI structures exists. If this is FALSE, then the MSI + # structure cannot be accessed via either the link or the management port + # .; EP=0x0001; RP=0x0000 # PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON 0 - # MSI Capability's Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capabi - # ity.; EP=0x0060; RP=0x0000 + # MSI Capability's Next Capability Offset pointer to the next item in the + # capabilities list, or 00h if this is the final capability.; EP=0x0060; R + # P=0x0000 # PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR 0x0 - # Indicates that the MSI structures exists. If this is FALSE, then the MSI structure cannot be accessed via either the link or - # he management port.; EP=0x0001; RP=0x0000 + # Indicates that the MSI structures exists. If this is FALSE, then the MSI + # structure cannot be accessed via either the link or the management port + # .; EP=0x0001; RP=0x0000 # PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON 0 # ATTR_41 @@ -13870,11 +16262,12 @@ set psu_resetout_init_data { mask_write 0XFD4800A4 0x000003FF 0x00000000 # Register : ATTR_97 @ 0XFD480184

- # Maximum Link Width. Valid settings are: 000001b x1, 000010b x2, 000100b x4, 001000b x8.; EP=0x0004; RP=0x0004 + # Maximum Link Width. Valid settings are: 000001b x1, 000010b x2, 000100b + # x4, 001000b x8.; EP=0x0004; RP=0x0004 # PSU_PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH 0x1 - # Used by LTSSM to set Maximum Link Width. Valid settings are: 000001b [x1], 000010b [x2], 000100b [x4], 001000b [x8].; EP=0x00 - # 4; RP=0x0004 + # Used by LTSSM to set Maximum Link Width. Valid settings are: 000001b [x1 + # ], 000010b [x2], 000100b [x4], 001000b [x8].; EP=0x0004; RP=0x0004 # PSU_PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH 0x1 # ATTR_97 @@ -13882,7 +16275,8 @@ set psu_resetout_init_data { mask_write 0XFD480184 0x00000FFF 0x00000041 # Register : ATTR_100 @ 0XFD480190

- # TRUE specifies upstream-facing port. FALSE specifies downstream-facing port.; EP=0x0001; RP=0x0000 + # TRUE specifies upstream-facing port. FALSE specifies downstream-facing p + # ort.; EP=0x0001; RP=0x0000 # PSU_PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING 0x0 # ATTR_100 @@ -13890,13 +16284,16 @@ set psu_resetout_init_data { mask_write 0XFD480190 0x00000040 0x00000000 # Register : ATTR_101 @ 0XFD480194

- # Enable the routing of message TLPs to the user through the TRN RX interface. A bit value of 1 enables routing of the message - # LP to the user. Messages are always decoded by the message decoder. Bit 0 - ERR COR, Bit 1 - ERR NONFATAL, Bit 2 - ERR FATAL, - # Bit 3 - INTA Bit 4 - INTB, Bit 5 - INTC, Bit 6 - INTD, Bit 7 PM_PME, Bit 8 - PME_TO_ACK, Bit 9 - unlock, Bit 10 PME_Turn_Off; - # EP=0x0000; RP=0x07FF + # Enable the routing of message TLPs to the user through the TRN RX interf + # ace. A bit value of 1 enables routing of the message TLP to the user. Me + # ssages are always decoded by the message decoder. Bit 0 - ERR COR, Bit 1 + # - ERR NONFATAL, Bit 2 - ERR FATAL, Bit 3 - INTA Bit 4 - INTB, Bit 5 - I + # NTC, Bit 6 - INTD, Bit 7 PM_PME, Bit 8 - PME_TO_ACK, Bit 9 - unlock, Bit + # 10 PME_Turn_Off; EP=0x0000; RP=0x07FF # PSU_PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE 0x7FF - # Disable BAR filtering. Does not change the behavior of the bar hit outputs; EP=0x0000; RP=0x0001 + # Disable BAR filtering. Does not change the behavior of the bar hit outpu + # ts; EP=0x0000; RP=0x0001 # PSU_PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING 0x1 # ATTR_101 @@ -13904,12 +16301,14 @@ set psu_resetout_init_data { mask_write 0XFD480194 0x0000FFE2 0x0000FFE2 # Register : ATTR_37 @ 0XFD480094

- # Link Bandwidth notification capability. Indicates support for the link bandwidth notification status and interrupt mechanism. - # Required for Root.; EP=0x0000; RP=0x0001 + # Link Bandwidth notification capability. Indicates support for the link b + # andwidth notification status and interrupt mechanism. Required for Root. + # ; EP=0x0000; RP=0x0001 # PSU_PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP 0x1 - # Sets the ASPM Optionality Compliance bit, to comply with the 2.1 ASPM Optionality ECN. Transferred to the Link Capabilities r - # gister.; EP=0x0001; RP=0x0001 + # Sets the ASPM Optionality Compliance bit, to comply with the 2.1 ASPM Op + # tionality ECN. Transferred to the Link Capabilities register.; EP=0x0001 + # ; RP=0x0001 # PSU_PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY 0x1 # ATTR_37 @@ -13917,13 +16316,16 @@ set psu_resetout_init_data { mask_write 0XFD480094 0x00004200 0x00004200 # Register : ATTR_93 @ 0XFD480174

- # Enables the Replay Timer to use the user-defined LL_REPLAY_TIMEOUT value (or combined with the built-in value, depending on L - # _REPLAY_TIMEOUT_FUNC). If FALSE, the built-in value is used.; EP=0x0000; RP=0x0000 + # Enables the Replay Timer to use the user-defined LL_REPLAY_TIMEOUT value + # (or combined with the built-in value, depending on LL_REPLAY_TIMEOUT_FU + # NC). If FALSE, the built-in value is used.; EP=0x0000; RP=0x0000 # PSU_PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN 0x1 - # Sets a user-defined timeout for the Replay Timer to force cause the retransmission of unacknowledged TLPs; refer to LL_REPLAY - # TIMEOUT_EN and LL_REPLAY_TIMEOUT_FUNC to see how this value is used. The unit for this attribute is in symbol times, which is - # 4ns at GEN1 speeds and 2ns at GEN2.; EP=0x0000; RP=0x0000 + # Sets a user-defined timeout for the Replay Timer to force cause the retr + # ansmission of unacknowledged TLPs; refer to LL_REPLAY_TIMEOUT_EN and LL_ + # REPLAY_TIMEOUT_FUNC to see how this value is used. The unit for this att + # ribute is in symbol times, which is 4ns at GEN1 speeds and 2ns at GEN2.; + # EP=0x0000; RP=0x0000 # PSU_PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT 0x1000 # ATTR_93 @@ -13961,8 +16363,8 @@ set psu_resetout_init_data { mask_write 0XFD480208 0x000000FF 0x00000000 # Register : ATTR_24 @ 0XFD480060

- # Code identifying basic function, subclass and applicable programming interface. Transferred to the Class Code register.; EP=0 - # 8000; RP=0x8000 + # Code identifying basic function, subclass and applicable programming int + # erface. Transferred to the Class Code register.; EP=0x8000; RP=0x8000 # PSU_PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE 0x400 # ATTR_24 @@ -13970,11 +16372,12 @@ set psu_resetout_init_data { mask_write 0XFD480060 0x0000FFFF 0x00000400 # Register : ATTR_25 @ 0XFD480064

- # Code identifying basic function, subclass and applicable programming interface. Transferred to the Class Code register.; EP=0 - # 0005; RP=0x0006 + # Code identifying basic function, subclass and applicable programming int + # erface. Transferred to the Class Code register.; EP=0x0005; RP=0x0006 # PSU_PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE 0x6 - # INTX Interrupt Generation Capable. If FALSE, this will cause Command[10] to be hardwired to 0.; EP=0x0001; RP=0x0001 + # INTX Interrupt Generation Capable. If FALSE, this will cause Command[10] + # to be hardwired to 0.; EP=0x0001; RP=0x0001 # PSU_PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED 0 # ATTR_25 @@ -13982,14 +16385,18 @@ set psu_resetout_init_data { mask_write 0XFD480064 0x000001FF 0x00000006 # Register : ATTR_4 @ 0XFD480010

- # Indicates that the AER structures exists. If this is FALSE, then the AER structure cannot be accessed via either the link or - # he management port, and AER will be considered to not be present for error management tasks (such as what types of error mess - # ges are sent if an error is detected).; EP=0x0001; RP=0x0001 + # Indicates that the AER structures exists. If this is FALSE, then the AER + # structure cannot be accessed via either the link or the management port + # , and AER will be considered to not be present for error management task + # s (such as what types of error messages are sent if an error is detected + # ).; EP=0x0001; RP=0x0001 # PSU_PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON 0 - # Indicates that the AER structures exists. If this is FALSE, then the AER structure cannot be accessed via either the link or - # he management port, and AER will be considered to not be present for error management tasks (such as what types of error mess - # ges are sent if an error is detected).; EP=0x0001; RP=0x0001 + # Indicates that the AER structures exists. If this is FALSE, then the AER + # structure cannot be accessed via either the link or the management port + # , and AER will be considered to not be present for error management task + # s (such as what types of error messages are sent if an error is detected + # ).; EP=0x0001; RP=0x0001 # PSU_PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON 0 # ATTR_4 @@ -13997,8 +16404,8 @@ set psu_resetout_init_data { mask_write 0XFD480010 0x00001000 0x00000000 # Register : ATTR_89 @ 0XFD480164

- # VSEC's Next Capability Offset pointer to the next item in the capabilities list, or 000h if this is the final capability.; EP - # 0x0140; RP=0x0140 + # VSEC's Next Capability Offset pointer to the next item in the capabiliti + # es list, or 000h if this is the final capability.; EP=0x0140; RP=0x0140 # PSU_PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR 0 # ATTR_89 @@ -14006,7 +16413,8 @@ set psu_resetout_init_data { mask_write 0XFD480164 0x00001FFE 0x00000000 # Register : ATTR_79 @ 0XFD48013C

- # CRS SW Visibility. Indicates RC can return CRS to SW. Transferred to the Root Capabilities register.; EP=0x0000; RP=0x0000 + # CRS SW Visibility. Indicates RC can return CRS to SW. Transferred to the + # Root Capabilities register.; EP=0x0000; RP=0x0000 # PSU_PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY 1 # ATTR_79 @@ -14014,8 +16422,9 @@ set psu_resetout_init_data { mask_write 0XFD48013C 0x00000020 0x00000020 # Register : ATTR_43 @ 0XFD4800AC

- # Indicates that the MSIX structures exists. If this is FALSE, then the MSIX structure cannot be accessed via either the link o - # the management port.; EP=0x0001; RP=0x0000 + # Indicates that the MSIX structures exists. If this is FALSE, then the MS + # IX structure cannot be accessed via either the link or the management po + # rt.; EP=0x0001; RP=0x0000 # PSU_PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON 0 # ATTR_43 @@ -14023,8 +16432,10 @@ set psu_resetout_init_data { mask_write 0XFD4800AC 0x00000100 0x00000000 # Register : ATTR_48 @ 0XFD4800C0

- # MSI-X Table Size. This value is transferred to the MSI-X Message Control[10:0] field. Set to 0 if MSI-X is not enabled. Note - # hat the core does not implement the table; that must be implemented in user logic.; EP=0x0003; RP=0x0000 + # MSI-X Table Size. This value is transferred to the MSI-X Message Control + # [10:0] field. Set to 0 if MSI-X is not enabled. Note that the core does + # not implement the table; that must be implemented in user logic.; EP=0x0 + # 003; RP=0x0000 # PSU_PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE 0 # ATTR_48 @@ -14032,8 +16443,8 @@ set psu_resetout_init_data { mask_write 0XFD4800C0 0x000007FF 0x00000000 # Register : ATTR_46 @ 0XFD4800B8

- # MSI-X Table Offset. This value is transferred to the MSI-X Table Offset field. Set to 0 if MSI-X is not enabled.; EP=0x0001; - # P=0x0000 + # MSI-X Table Offset. This value is transferred to the MSI-X Table Offset + # field. Set to 0 if MSI-X is not enabled.; EP=0x0001; RP=0x0000 # PSU_PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET 0 # ATTR_46 @@ -14041,8 +16452,8 @@ set psu_resetout_init_data { mask_write 0XFD4800B8 0x0000FFFF 0x00000000 # Register : ATTR_47 @ 0XFD4800BC

- # MSI-X Table Offset. This value is transferred to the MSI-X Table Offset field. Set to 0 if MSI-X is not enabled.; EP=0x0000; - # P=0x0000 + # MSI-X Table Offset. This value is transferred to the MSI-X Table Offset + # field. Set to 0 if MSI-X is not enabled.; EP=0x0000; RP=0x0000 # PSU_PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET 0 # ATTR_47 @@ -14050,8 +16461,8 @@ set psu_resetout_init_data { mask_write 0XFD4800BC 0x00001FFF 0x00000000 # Register : ATTR_44 @ 0XFD4800B0

- # MSI-X Pending Bit Array Offset This value is transferred to the MSI-X PBA Offset field. Set to 0 if MSI-X is not enabled.; EP - # 0x0001; RP=0x0000 + # MSI-X Pending Bit Array Offset This value is transferred to the MSI-X PB + # A Offset field. Set to 0 if MSI-X is not enabled.; EP=0x0001; RP=0x0000 # PSU_PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET 0 # ATTR_44 @@ -14059,8 +16470,8 @@ set psu_resetout_init_data { mask_write 0XFD4800B0 0x0000FFFF 0x00000000 # Register : ATTR_45 @ 0XFD4800B4

- # MSI-X Pending Bit Array Offset This value is transferred to the MSI-X PBA Offset field. Set to 0 if MSI-X is not enabled.; EP - # 0x1000; RP=0x0000 + # MSI-X Pending Bit Array Offset This value is transferred to the MSI-X PB + # A Offset field. Set to 0 if MSI-X is not enabled.; EP=0x1000; RP=0x0000 # PSU_PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET 0 # ATTR_45 @@ -14076,8 +16487,10 @@ set psu_resetout_init_data { mask_write 0XFD48031C 0x00000002 0x00000000 # Register : ATTR_35 @ 0XFD48008C

- # Active State PM Support. Indicates the level of active state power management supported by the selected PCI Express Link, enc - # ded as follows: 0 Reserved, 1 L0s entry supported, 2 Reserved, 3 L0s and L1 entry supported.; EP=0x0001; RP=0x0001 + # Active State PM Support. Indicates the level of active state power manag + # ement supported by the selected PCI Express Link, encoded as follows: 0 + # Reserved, 1 L0s entry supported, 2 Reserved, 3 L0s and L1 entry supporte + # d.; EP=0x0001; RP=0x0001 # PSU_PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT 0x0 # ATTR_35 @@ -14092,6 +16505,24 @@ set psu_resetout_init_data { # FPD Block level software controlled reset #(OFFSET, MASK, VALUE) (0XFD1A0100, 0x00020000U ,0x00000000U) */ mask_write 0XFD1A0100 0x00020000 0x00000000 + # : PCIE GPIO RESET + # : MASK_DATA_0_LSW LOW BANK [15:0] + # : MASK_DATA_0_MSW LOW BANK [25:16] + # : MASK_DATA_1_LSW LOW BANK [41:26] + # Register : MASK_DATA_1_LSW @ 0XFF0A0008

+ + # Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW] + # PSU_GPIO_MASK_DATA_1_LSW_MASK_1_LSW 0xffdf + + # Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW] + # PSU_GPIO_MASK_DATA_1_LSW_DATA_1_LSW 0x20 + + # Maskable Output Data (GPIO Bank1, MIO, Lower 16bits) + #(OFFSET, MASK, VALUE) (0XFF0A0008, 0xFFFFFFFFU ,0xFFDF0020U) */ + mask_write 0XFF0A0008 0xFFFFFFFF 0xFFDF0020 + # : MASK_DATA_1_MSW HIGH BANK [51:42] + # : MASK_DATA_1_LSW HIGH BANK [67:52] + # : MASK_DATA_1_LSW HIGH BANK [77:68] # : CHECK PLL LOCK FOR LANE0 # Register : L0_PLL_STATUS_READ_1 @ 0XFD4023E4

@@ -14131,8 +16562,10 @@ set psu_resetout_init_data { # CINMP: COMINIT Negate Minimum Period. # PSU_SATA_AHCI_VENDOR_PP2C_CINMP 0x28 - # PP2C - Port Phy2Cfg Register. This register controls the configuration of the Phy Control OOB timing for the COMINIT paramete - # s for either Port 0 or Port 1. The Port configured is controlled by the value programmed into the Port Config Register. + # PP2C - Port Phy2Cfg Register. This register controls the configuration o + # f the Phy Control OOB timing for the COMINIT parameters for either Port + # 0 or Port 1. The Port configured is controlled by the value programmed i + # nto the Port Config Register. #(OFFSET, MASK, VALUE) (0XFD0C00AC, 0xFFFFFFFFU ,0x28184018U) */ mask_write 0XFD0C00AC 0xFFFFFFFF 0x28184018 # Register : PP3C @ 0XFD0C00B0

@@ -14149,8 +16582,10 @@ set psu_resetout_init_data { # CWNMP: COMWAKE Negate Minimum Period. # PSU_SATA_AHCI_VENDOR_PP3C_CWNMP 0x0E - # PP3C - Port Phy3CfgRegister. This register controls the configuration of the Phy Control OOB timing for the COMWAKE parameter - # for either Port 0 or Port 1. The Port configured is controlled by the value programmed into the Port Config Register. + # PP3C - Port Phy3CfgRegister. This register controls the configuration of + # the Phy Control OOB timing for the COMWAKE parameters for either Port 0 + # or Port 1. The Port configured is controlled by the value programmed in + # to the Port Config Register. #(OFFSET, MASK, VALUE) (0XFD0C00B0, 0xFFFFFFFFU ,0x0E081406U) */ mask_write 0XFD0C00B0 0xFFFFFFFF 0x0E081406 # Register : PP4C @ 0XFD0C00B4

@@ -14161,31 +16596,41 @@ set psu_resetout_init_data { # BNM: COM Burst Nominal. # PSU_SATA_AHCI_VENDOR_PP4C_BNM 0x08 - # SFD: Signal Failure Detection, if the signal detection de-asserts for a time greater than this then the OOB detector will det - # rmine this is a line idle and cause the PhyInit state machine to exit the Phy Ready State. A value of zero disables the Signa - # Failure Detector. The value is based on the OOB Detector Clock typically (PMCLK Clock Period) * SFD giving a nominal time of - # 500ns based on a 150MHz PMCLK. + # SFD: Signal Failure Detection, if the signal detection de-asserts for a + # time greater than this then the OOB detector will determine this is a li + # ne idle and cause the PhyInit state machine to exit the Phy Ready State. + # A value of zero disables the Signal Failure Detector. The value is base + # d on the OOB Detector Clock typically (PMCLK Clock Period) * SFD giving + # a nominal time of 500ns based on a 150MHz PMCLK. # PSU_SATA_AHCI_VENDOR_PP4C_SFD 0x4A - # PTST: Partial to Slumber timer value, specific delay the controller should apply while in partial before entering slumber. Th - # value is bases on the system clock divided by 128, total delay = (Sys Clock Period) * PTST * 128 + # PTST: Partial to Slumber timer value, specific delay the controller shou + # ld apply while in partial before entering slumber. The value is bases on + # the system clock divided by 128, total delay = (Sys Clock Period) * PTS + # T * 128 # PSU_SATA_AHCI_VENDOR_PP4C_PTST 0x06 - # PP4C - Port Phy4Cfg Register. This register controls the configuration of the Phy Control Burst timing for the COM parameters - # for either Port 0 or Port 1. The Port configured is controlled by the value programmed into the Port Config Register. + # PP4C - Port Phy4Cfg Register. This register controls the configuration o + # f the Phy Control Burst timing for the COM parameters for either Port 0 + # or Port 1. The Port configured is controlled by the value programmed int + # o the Port Config Register. #(OFFSET, MASK, VALUE) (0XFD0C00B4, 0xFFFFFFFFU ,0x064A0813U) */ mask_write 0XFD0C00B4 0xFFFFFFFF 0x064A0813 # Register : PP5C @ 0XFD0C00B8

- # RIT: Retry Interval Timer. The calculated value divided by two, the lower digit of precision is not needed. + # RIT: Retry Interval Timer. The calculated value divided by two, the lowe + # r digit of precision is not needed. # PSU_SATA_AHCI_VENDOR_PP5C_RIT 0xC96A4 - # RCT: Rate Change Timer, a value based on the 54.2us for which a SATA device will transmit at a fixed rate ALIGNp after OOB ha - # completed, for a fast SERDES it is suggested that this value be 54.2us / 4 + # RCT: Rate Change Timer, a value based on the 54.2us for which a SATA dev + # ice will transmit at a fixed rate ALIGNp after OOB has completed, for a + # fast SERDES it is suggested that this value be 54.2us / 4 # PSU_SATA_AHCI_VENDOR_PP5C_RCT 0x3FF - # PP5C - Port Phy5Cfg Register. This register controls the configuration of the Phy Control Retry Interval timing for either Po - # t 0 or Port 1. The Port configured is controlled by the value programmed into the Port Config Register. + # PP5C - Port Phy5Cfg Register. This register controls the configuration o + # f the Phy Control Retry Interval timing for either Port 0 or Port 1. The + # Port configured is controlled by the value programmed into the Port Con + # fig Register. #(OFFSET, MASK, VALUE) (0XFD0C00B8, 0xFFFFFFFFU ,0x3FFC96A4U) */ mask_write 0XFD0C00B8 0xFFFFFFFF 0x3FFC96A4 } @@ -14243,8 +16688,9 @@ set psu_resetin_init_data { # : PUTTING DP IN RESET # Register : DP_TX_PHY_POWER_DOWN @ 0XFD4A0238

- # Two bits per lane. When set to 11, moves the GT to power down mode. When set to 00, GT will be in active state. bits [1:0] - - # ane0 Bits [3:2] - lane 1 + # Two bits per lane. When set to 11, moves the GT to power down mode. When + # set to 00, GT will be in active state. bits [1:0] - lane0 Bits [3:2] - + # lane 1 # PSU_DP_DP_TX_PHY_POWER_DOWN_POWER_DWN 0XA # Control PHY Power down @@ -14275,7 +16721,8 @@ set psu_ps_pl_isolation_removal_data { # Power-up Request Interrupt Enable for PL # PSU_PMU_GLOBAL_REQ_PWRUP_INT_EN_PL 1 - # Power-up Request Interrupt Enable Register. Writing a 1 to this location will unmask the interrupt. + # Power-up Request Interrupt Enable Register. Writing a 1 to this location + # will unmask the interrupt. #(OFFSET, MASK, VALUE) (0XFFD80118, 0x00800000U ,0x00800000U) */ mask_write 0XFFD80118 0x00800000 0x00800000 # Register : REQ_PWRUP_TRIG @ 0XFFD80120

@@ -14283,7 +16730,8 @@ set psu_ps_pl_isolation_removal_data { # Power-up Request Trigger for PL # PSU_PMU_GLOBAL_REQ_PWRUP_TRIG_PL 1 - # Power-up Request Trigger Register. A write of one to this location will generate a power-up request to the PMU. + # Power-up Request Trigger Register. A write of one to this location will + # generate a power-up request to the PMU. #(OFFSET, MASK, VALUE) (0XFFD80120, 0x00800000U ,0x00800000U) */ mask_write 0XFFD80120 0x00800000 0x00800000 # : POLL ON PL POWER STATUS @@ -14294,6 +16742,58 @@ set psu_ps_pl_isolation_removal_data { mask_poll 0XFFD80110 0x00800000 0x00000000 } +set psu_afi_config { + # : AFI RESET + # Register : RST_FPD_TOP @ 0XFD1A0100

+ + # AF_FM0 block level reset + # PSU_CRF_APB_RST_FPD_TOP_AFI_FM0_RESET 0 + + # AF_FM1 block level reset + # PSU_CRF_APB_RST_FPD_TOP_AFI_FM1_RESET 0 + + # AF_FM2 block level reset + # PSU_CRF_APB_RST_FPD_TOP_AFI_FM2_RESET 0 + + # AF_FM3 block level reset + # PSU_CRF_APB_RST_FPD_TOP_AFI_FM3_RESET 0 + + # AF_FM4 block level reset + # PSU_CRF_APB_RST_FPD_TOP_AFI_FM4_RESET 0 + + # AF_FM5 block level reset + # PSU_CRF_APB_RST_FPD_TOP_AFI_FM5_RESET 0 + + # FPD Block level software controlled reset + #(OFFSET, MASK, VALUE) (0XFD1A0100, 0x00001F80U ,0x00000000U) */ + mask_write 0XFD1A0100 0x00001F80 0x00000000 + # Register : RST_LPD_TOP @ 0XFF5E023C

+ + # AFI FM 6 + # PSU_CRL_APB_RST_LPD_TOP_AFI_FM6_RESET 0 + + # Software control register for the LPD block. + #(OFFSET, MASK, VALUE) (0XFF5E023C, 0x00080000U ,0x00000000U) */ + mask_write 0XFF5E023C 0x00080000 0x00000000 + # : AFIFM INTERFACE WIDTH + # Register : afi_fs @ 0XFD615000

+ + # Select the 32/64/128-bit data width selection for the Slave 0 00: 32-bit + # AXI data width (default) 01: 64-bit AXI data width 10: 128-bit AXI data + # width 11: reserved + # PSU_FPD_SLCR_AFI_FS_DW_SS0_SEL 0x2 + + # Select the 32/64/128-bit data width selection for the Slave 1 00: 32-bit + # AXI data width (default) 01: 64-bit AXI data width 10: 128-bit AXI data + # width 11: reserved + # PSU_FPD_SLCR_AFI_FS_DW_SS1_SEL 0x2 + + # afi fs SLCR control register. This register is static and should not be + # modified during operation. + #(OFFSET, MASK, VALUE) (0XFD615000, 0x00000F00U ,0x00000A00U) */ + mask_write 0XFD615000 0x00000F00 0x00000A00 +} + set psu_ps_pl_reset_config_data { # : PS PL RESET SEQUENCE # : FABRIC RESET USING EMIO @@ -14366,6 +16866,7 @@ proc psu_init {} { variable psu_serdes_init_data variable psu_resetin_init_data variable psu_peripherals_powerdwn_data + variable psu_afi_config init_ps [subst {$psu_mio_init_data $psu_pll_init_data $psu_clock_init_data $psu_ddr_init_data }] psu_ddr_phybringup_data @@ -14374,6 +16875,7 @@ proc psu_init {} { init_ps [subst {$psu_serdes_init_data $psu_resetout_init_data }] init_peripheral init_ps [subst {$psu_peripherals_powerdwn_data }] + init_ps [subst {$psu_afi_config }] # restore original mode configparams force-mem-accesses $saved_mode } @@ -14409,7 +16911,7 @@ proc mask_poll { addr mask } { set curval "0x[string range [mrd -force $addr] end-8 end]" set maskedval [expr {$curval & $mask}] set count [ expr { $count + 1 } ] - if { $count == 100000000 } { + if { $count == 1000 } { puts "Timeout Reached. Mask poll failed at ADDRESS: $addr MASK: $mask" break } @@ -14424,48 +16926,195 @@ proc psu_mask_write { addr mask value } { mwr -force $addr $maskedval } +proc serdes_fixcal_code {} { + + set MaskStatus 1 + array set match_pmos_code {} + array set match_nmos_code {} + array set match_ical_code {} + array set match_rcal_code {} + set p_code 0 + set n_code 0 + set i_code 0 + set r_code 0 + set repeat_count 0 + set L3_TM_CALIB_DIG20 0 + set L3_TM_CALIB_DIG19 0 + set L3_TM_CALIB_DIG18 0 + set L3_TM_CALIB_DIG16 0 + set L3_TM_CALIB_DIG15 0 + set L3_TM_CALIB_DIG14 0 -proc serdes_fixcal_code {} { - #/* - # * L3_TM_CALIB_DIG19 - # */ - mask_write 0xFD40EC4C 0xFFFFFFFF 0x00000020 + set rdata 0 + + set rdata [mask_read 0XFD40289C 0xFFFFFFFF] + set rdata [expr $rdata & ~0x03 ] + set rdata [expr $rdata | 0x1] + mask_write 0XFD40289C 0xFFFFFFFF $rdata + #check supply good status before starting AFE sequencing + set count 1 + while 1 { + set rdata [mask_read 0xFD402B1C 0xFFFFFFFF] + set count [ expr { $count + 1 } ] + if { [expr $rdata & 0x0000000E] == 0x0000000E } { + break; + } + if { $count == 1000 } { + break; + } + } + + + for {set i 0} {$i<23 } {incr i } { + set match_pmos_code($i) 0; + set match_nmos_code($i) 0; + } + + for {set i 0} {$i<7} {incr i} { + set match_ical_code($i) 0; + set match_rcal_code($i) 0; + } + + while 1 { + #Clear ICM_CFG value + mask_write 0xFD410010 0xFFFFFFFF 0x00000000 + mask_write 0xFD410014 0xFFFFFFFF 0x00000000 + + #Set ICM_CFG value + #This will trigger recalibration of all stages + mask_write 0xFD410010 0xFFFFFFFF 0x00000001 + mask_write 0xFD410014 0xFFFFFFFF 0x00000000; + + #is calibration done? polling on L3_CALIB_DONE_STATUS + mask_poll 0xFD40EF14 0x2; + + #PMOS code + set p_code [mask_read 0xFD40EF18 0xFFFFFFFF]; + #NMOS code + set n_code [mask_read 0xFD40EF1C 0xFFFFFFFF]; + #ICAL code + set i_code [mask_read 0xFD40EF24 0xFFFFFFFF]; + #RX code + set r_code [mask_read 0xFD40EF28 0xFFFFFFFF]; + + + #xil_printf("#SERDES initialization VALUES NMOS = 0x%x, PMOS = 0x%x, ICAL = 0x%x, RCAL = 0x%x\n\r", p_code, n_code, i_code, r_code); + #PMOS code in acceptable range + if {($p_code >= 0x26) && ($p_code <= 0x3C)} { + set index [expr $p_code - 0x26] + set value $match_pmos_code($index) + incr value + set match_pmos_code($index) $value; + } + #NMOS code in acceptable range + if {($n_code >= 0x26) && ($n_code <= 0x3C)} { + set index [expr $n_code - 0x26] + set value $match_nmos_code($index) + incr value + set match_nmos_code($index) $value; + } + #PMOS code in acceptable range + if {($i_code >= 0xC) && ($i_code <= 0x12)} { + + set index [expr $i_code - 0xC] + set value $match_ical_code($index) + incr value + set match_ical_code($index) $value; + + } + #NMOS code in acceptable range + if {($r_code >= 0x6) && ($r_code <= 0xC)} { + set index [expr $r_code - 0x6] + set value $match_rcal_code($index) + incr value + set match_rcal_code($index) $value; + } + + incr repeat_count + if {$repeat_count > 10} { + break + } + } + + + #find the valid code which resulted in maximum times in 10 iterations + for {set i 0 } {$i < 23} {incr i} { - #/* - # * ICM_CFG0 - # */ - mask_write 0xFD410010 0xFFFFFFFF 0x00000001 + if {$match_pmos_code($i) >= $match_pmos_code(0) } { + set match_pmos_code(0) $match_pmos_code($i) + set p_code [expr 0x26 + $i] + } + if {$match_nmos_code($i) >= $match_nmos_code(0)} { + + set match_nmos_code(0) $match_nmos_code($i) + set n_code [expr 0x26 + $i]; + } + } - - #/* - # * is calibration done, polling on L3_CALIB_DONE_STATUS - # */ - mask_poll 0xFD40EF14 0x2 - - #unsigned int tmp_0_1; - set tmp_0_1 [mrd -force -value 0xFD400B0C] - set tmp_0_1 [expr {$tmp_0_1 & 0x3F}] - - set tmp_0_2 [expr {$tmp_0_1 & 0x7}] - set tmp_0_3 [expr {$tmp_0_1 & 0x38}] - - #Configure ICM for de-asserting CMN_Resetn - mask_write 0xFD410010 0xFFFFFFFF 0x00000000 - mask_write 0xFD410014 0xFFFFFFFF 0x00000000 - - set tmp_0_2_mod [expr {($tmp_0_2 << 1) | (0x1)}] - set tmp_0_2_mod [expr {$tmp_0_2_mod << 4}] - - set tmp_0_3 [expr {$tmp_0_3 >> 3}] - mask_write 0xFD40EC4C 0xFFFFFFFF $tmp_0_3 - - #L3_TM_CALIB_DIG18 - mask_write 0xFD40EC48 0xFFFFFFFF $tmp_0_2_mod + for {set $i 0} {$i<7} {incr i} { + if {$match_ical_code($i) >= $match_ical_code(0)} { + set match_ical_code(0) $match_ical_code($i) + set i_code [expr 0xC + $i] + } + if {$match_rcal_code($i) >= $match_rcal_code(0)} { + set match_rcal_code(0) $match_rcal_code($i) + set r_code [expr 0x6 + $i] + } + } + #xil_printf("#SERDES initialization PASSED NMOS = 0x%x, PMOS = 0x%x, ICAL = 0x%x, RCAL = 0x%x\n\r", p_code, n_code, i_code, r_code); + #L3_TM_CALIB_DIG20[3] PSW MSB Override + #L3_TM_CALIB_DIG20[2:0] PSW Code [4:2] + #read DIG20 + set L3_TM_CALIB_DIG20 [mask_read 0xFD40EC50 0xFFFFFFF0]; + set L3_TM_CALIB_DIG20 [expr $L3_TM_CALIB_DIG20 | 0x8 | (($p_code>>2)&0x7)] -} + #L3_TM_CALIB_DIG19[7:6] PSW Code [1:0] + #L3_TM_CALIB_DIG19[5] PSW Override + #L3_TM_CALIB_DIG19[2] NSW MSB Override + #L3_TM_CALIB_DIG19[1:0] NSW Code [4:3] + #read DIG19 + set L3_TM_CALIB_DIG19 [mask_read 0xFD40EC4C 0xFFFFFF18] + set L3_TM_CALIB_DIG19 [expr $L3_TM_CALIB_DIG19 | (($p_code&0x3)<<6) | 0x20 | 0x4 | (($n_code>>3)&0x3)] + #L3_TM_CALIB_DIG18[7:5] NSW Code [2:0] + #L3_TM_CALIB_DIG18[4] NSW Override + #read DIG18 + set L3_TM_CALIB_DIG18 [mask_read 0xFD40EC48 0xFFFFFF0F] + set L3_TM_CALIB_DIG18 [expr $L3_TM_CALIB_DIG18 | (($n_code&0x7)<<5) | 0x10] + + + #L3_TM_CALIB_DIG16[2:0] RX Code [3:1] + #read DIG16 + set L3_TM_CALIB_DIG16 [mask_read 0xFD40EC40 0xFFFFFFF8] + set L3_TM_CALIB_DIG16 [expr $L3_TM_CALIB_DIG16 | (($r_code>>1)&0x7)] + + #L3_TM_CALIB_DIG15[7] RX Code [0] + #L3_TM_CALIB_DIG15[6] RX CODE Override + #L3_TM_CALIB_DIG15[3] ICAL MSB Override + #L3_TM_CALIB_DIG15[2:0] ICAL Code [3:1] + #read DIG15 + set L3_TM_CALIB_DIG15 [mask_read 0xFD40EC3C 0xFFFFFF30] + set L3_TM_CALIB_DIG15 [expr $L3_TM_CALIB_DIG15 | (($r_code&0x1)<<7) | 0x40 | 0x8 | (($i_code>>1)&0x7)] + + #L3_TM_CALIB_DIG14[7] ICAL Code [0] + #L3_TM_CALIB_DIG14[6] ICAL Override + #read DIG14 + set L3_TM_CALIB_DIG14 [mask_read 0xFD40EC38 0xFFFFFF3F] + set L3_TM_CALIB_DIG14 [expr $L3_TM_CALIB_DIG14 | (($i_code&0x1)<<7) | 0x40] + + #Forces the calibration values + mask_write 0xFD40EC50 0xFFFFFFFF $L3_TM_CALIB_DIG20 + mask_write 0xFD40EC4C 0xFFFFFFFF $L3_TM_CALIB_DIG19 + mask_write 0xFD40EC48 0xFFFFFFFF $L3_TM_CALIB_DIG18 + mask_write 0xFD40EC40 0xFFFFFFFF $L3_TM_CALIB_DIG16 + mask_write 0xFD40EC3C 0xFFFFFFFF $L3_TM_CALIB_DIG15 + mask_write 0xFD40EC38 0xFFFFFFFF $L3_TM_CALIB_DIG14 + + + return $MaskStatus; + } proc serdes_enb_coarse_saturation {} { #/* # * Enable PLL Coarse Code saturation Logic @@ -14477,9 +17126,7 @@ proc serdes_enb_coarse_saturation {} { } - proc init_serdes {} { - serdes_fixcal_code serdes_enb_coarse_saturation @@ -14501,48 +17148,15 @@ proc poll { addr mask data} { } proc init_peripheral {} { - - # Release all resets in the IOU */ - mask_write 0xFF5E0230 0xFFFFFFFF 0x00000000 - mask_write 0xFF5E0234 0xFFFFFFFF 0x00000000 - mask_write 0xFF5E0238 0xFFFFFFFF 0x00000000 - - # Take LPD out of reset except R5 */ - set tmp_0_1 [mrd -force -value 0xFF5E023C] - set tmp_0_1 [expr {$tmp_0_1 & 0x7}] - mask_write 0xFF5E023C 0xFFFFFFFF $tmp_0_1 - - # Take most of FPD out of reset */ - mask_write 0XFD1A0100 0xFFFFFFFF 0x00000000 - - # Making DPDMA as secure - mask_write 0xFD690040 0x00000001 0x00000000 - # Making PCIe as secure - mask_write 0xFD690030 0x00000001 0x00000000 - +#SMMU_REG Interrrupt Enable: Followig register need to be written all the time to properly catch SMMU messages. + mask_write 0xFD5F0018 0x8000001F 0x8000001F } proc psu_init_xppu_aper_ram {} { - set APER_OFFSET 0xFF981000 - set i 0 - while { $i <= 400 } { - mask_write $APER_OFFSET 0xF80FFFFF 0x08080000 - set APER_OFFSET [ expr $APER_OFFSET + 4 ] - set APER_OFFSET "0x[format %08X [ expr $APER_OFFSET] ]" - set i [ expr { $i + 1 } ] - } } proc psu_lpd_protection {} { - set saved_mode [configparams force-mem-accesses] - configparams force-mem-accesses 1 - - psu_init_xppu_aper_ram; - variable psu_lpd_xppu_data - init_ps [subst {$psu_lpd_xppu_data }] - - configparams force-mem-accesses $saved_mode } proc psu_ddr_protection {} { @@ -14591,6 +17205,8 @@ proc psu_protection_lock {} { } proc psu_protection {} { + variable psu_apply_master_tz + init_ps [subst {$psu_apply_master_tz }] psu_ddr_protection psu_ocm_protection psu_fpd_protection @@ -14598,26 +17214,34 @@ proc psu_protection {} { } proc psu_ddr_phybringup_data {} { -set dpll_divisor [expr {(0x00003F00 & [mrd -force -value 0xFD1A0080]) >> 0x00000008 }] - psu_mask_write 0xFD1A0080 0x00003F00 0x00000500 - psu_mask_write 0xFD080028 0x00000001 0x00000001 -mwr -force 0xFD080004 0x00040003 -mask_poll 0xFD080030 0x00000001 - psu_mask_write 0xFD080684 0x06000000 0x02000000 - psu_mask_write 0xFD0806A4 0x06000000 0x02000000 - psu_mask_write 0xFD0806C4 0x06000000 0x02000000 - psu_mask_write 0xFD0806E4 0x06000000 0x02000000 - psu_mask_write 0xFD1A0080 0x3F00 [expr {($dpll_divisor << 8)}] -mwr -force 0xFD080004 0x40040071 -mask_poll 0xFD080030 0x00000001 -mwr -force 0xFD080004 0x40040001 -mask_poll 0xFD080030 0x00000001 +mwr -force 0xFD080004 0x00040073 poll 0xFD080030 0x0000000F 0x0000000F psu_mask_write 0xFD080004 0x00000001 0x00000001 #poll for PHY initialization to complete poll 0xFD080030 0x000000FF 0x0000001F + psu_mask_write 0xFD070010 0x00000008 0x00000008 + psu_mask_write 0xFD0701B0 0x00000001 0x00000001 + psu_mask_write 0xFD070010 0x00000030 0x00000010 + psu_mask_write 0xFD070010 0x00000001 0x00000000 + psu_mask_write 0xFD070010 0x0000F000 0x00006000 + psu_mask_write 0xFD070014 0x0003FFFF 0x00000819 + psu_mask_write 0xFD070010 0x80000000 0x80000000 +poll 0xFD070018 0x00000001 0 + psu_mask_write 0xFD070010 0x00000030 0x00000010 + psu_mask_write 0xFD070010 0x00000001 0x00000000 + psu_mask_write 0xFD070010 0x0000F000 0x00006000 + psu_mask_write 0xFD070014 0x0003FFFF 0x00000899 + psu_mask_write 0xFD070010 0x80000000 0x80000000 +poll 0xFD070018 0x00000001 0 + psu_mask_write 0xFD070010 0x00000030 0x00000010 + psu_mask_write 0xFD070010 0x00000001 0x00000000 + psu_mask_write 0xFD070010 0x0000F000 0x00006000 + psu_mask_write 0xFD070014 0x0003FFFF 0x00000819 + psu_mask_write 0xFD070010 0x80000000 0x80000000 +poll 0xFD070018 0x00000001 0 + psu_mask_write 0xFD070010 0x00000008 0x00000000 mwr -force 0xFD0701B0 0x00000001 mwr -force 0xFD070320 0x00000001 #//poll for DDR initialization to complete @@ -14646,31 +17270,29 @@ poll 0xFD080030 0x00000FFF 0x00000FFF # Run Vref training in static read mode mwr -force 0xFD080200 0x100091C7 -mwr -force 0xFD080018 0x00F01EF2 -mwr -force 0xFD08001C 0x55AA5498 -mwr -force 0xFD08142C 0x00041830 -mwr -force 0xFD08146C 0x00041830 -mwr -force 0xFD0814AC 0x00041830 -mwr -force 0xFD0814EC 0x00041830 -mwr -force 0xFD08152C 0x00041830 +mwr -force 0xFD080018 0x00F01EEF + psu_mask_write 0xFD08142C 0x00000030 0x00000030 + psu_mask_write 0xFD08146C 0x00000030 0x00000030 + psu_mask_write 0xFD0814AC 0x00000030 0x00000030 + psu_mask_write 0xFD0814EC 0x00000030 0x00000030 + psu_mask_write 0xFD08152C 0x00000030 0x00000030 psu_mask_write 0xFD080004 0xFFFFFFFF 0x00060001 #trigger VreFPHY training -poll 0xFD080030 0x00000C01 0x00000C01 +poll 0xFD080030 0x00004001 0x00004001 #//Poll PUB_PGSR0 for Trng complete mwr -force 0xFD080200 0x800091C7 -mwr -force 0xFD080018 0x00F12302 -mwr -force 0xFD08001C 0x55AA5480 -mwr -force 0xFD08142C 0x00041800 -mwr -force 0xFD08146C 0x00041800 -mwr -force 0xFD0814AC 0x00041800 -mwr -force 0xFD0814EC 0x00041800 -mwr -force 0xFD08152C 0x00041800 +mwr -force 0xFD080018 0x00F122E7 + psu_mask_write 0xFD08142C 0x00000030 0x00000000 + psu_mask_write 0xFD08146C 0x00000030 0x00000000 + psu_mask_write 0xFD0814AC 0x00000030 0x00000000 + psu_mask_write 0xFD0814EC 0x00000030 0x00000000 + psu_mask_write 0xFD08152C 0x00000030 0x00000000 psu_mask_write 0xFD080004 0xFFFFFFFF 0x0000C001 #trigger VreFPHY training -poll 0xFD080030 0x00004001 0x00004001 +poll 0xFD080030 0x00000C01 0x00000C01 #//Poll PUB_PGSR0 for Trng complete mwr -force 0xFD070180 0x01000040 diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init_gpl.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init_gpl.c index 8ed7cf1dc..d75ebacb3 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init_gpl.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init_gpl.c @@ -1,7 +1,7 @@ /****************************************************************************** * * Copyright (C) 2015 Xilinx, Inc. All rights reserved. -* +* * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or @@ -11,21103 +11,21793 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. -* +* * You should have received a copy of the GNU General Public License along * with this program; if not, see -* -* -******************************************************************************/ +* +* +******************************************************************************/ #include #include #include "psu_init_gpl.h" +#define DPLL_CFG_LOCK_DLY 63 +#define DPLL_CFG_LOCK_CNT 625 +#define DPLL_CFG_LFHF 3 +#define DPLL_CFG_CP 3 +#define DPLL_CFG_RES 2 -int mask_pollOnValue(u32 add , u32 mask, u32 value ); +static int mask_pollOnValue(u32 add, u32 mask, u32 value); -int mask_poll(u32 add , u32 mask ); +static int mask_poll(u32 add, u32 mask); -void mask_delay(u32 delay); +static void mask_delay(u32 delay); -u32 mask_read(u32 add , u32 mask ); +static u32 mask_read(u32 add, u32 mask); -static void PSU_Mask_Write (unsigned long offset, unsigned long mask, unsigned long val) +static void dpll_prog(int ddr_pll_fbdiv, int d_lock_dly, + int d_lock_cnt, int d_lfhf, int d_cp, int d_res); + +static +void PSU_Mask_Write(unsigned long offset, unsigned long mask, + unsigned long val) { unsigned long RegVal = 0x0; - RegVal = Xil_In32 (offset); + + RegVal = Xil_In32(offset); RegVal &= ~(mask); RegVal |= (val & mask); - Xil_Out32 (offset, RegVal); + Xil_Out32(offset, RegVal); } - void prog_reg (unsigned long addr, unsigned long mask, unsigned long shift, unsigned long value) { - int rdata =0; +static +void prog_reg(unsigned long addr, unsigned long mask, + unsigned long shift, + unsigned long value) +{ + int rdata = 0; + rdata = Xil_In32(addr); rdata = rdata & (~mask); rdata = rdata | (value << shift); - Xil_Out32(addr,rdata); - } - -unsigned long psu_pll_init_data() { - // : RPLL INIT - /*Register : RPLL_CFG @ 0XFF5E0034

- - PLL loop filter resistor control - PSU_CRL_APB_RPLL_CFG_RES 0x2 - - PLL charge pump control - PSU_CRL_APB_RPLL_CFG_CP 0x3 - - PLL loop filter high frequency capacitor control - PSU_CRL_APB_RPLL_CFG_LFHF 0x3 - - Lock circuit counter setting - PSU_CRL_APB_RPLL_CFG_LOCK_CNT 0x258 - - Lock circuit configuration settings for lock windowsize - PSU_CRL_APB_RPLL_CFG_LOCK_DLY 0x3f - - Helper data. Values are to be looked up in a table from Data Sheet - (OFFSET, MASK, VALUE) (0XFF5E0034, 0xFE7FEDEFU ,0x7E4B0C62U) - RegMask = (CRL_APB_RPLL_CFG_RES_MASK | CRL_APB_RPLL_CFG_CP_MASK | CRL_APB_RPLL_CFG_LFHF_MASK | CRL_APB_RPLL_CFG_LOCK_CNT_MASK | CRL_APB_RPLL_CFG_LOCK_DLY_MASK | 0 ); - - RegVal = ((0x00000002U << CRL_APB_RPLL_CFG_RES_SHIFT - | 0x00000003U << CRL_APB_RPLL_CFG_CP_SHIFT - | 0x00000003U << CRL_APB_RPLL_CFG_LFHF_SHIFT - | 0x00000258U << CRL_APB_RPLL_CFG_LOCK_CNT_SHIFT - | 0x0000003FU << CRL_APB_RPLL_CFG_LOCK_DLY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RPLL_CFG_OFFSET ,0xFE7FEDEFU ,0x7E4B0C62U); - /*############################################################################################################################ */ - - // : UPDATE FB_DIV - /*Register : RPLL_CTRL @ 0XFF5E0030

- - Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_ - ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source - PSU_CRL_APB_RPLL_CTRL_PRE_SRC 0x0 - - The integer portion of the feedback divider to the PLL - PSU_CRL_APB_RPLL_CTRL_FBDIV 0x48 - - This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency - PSU_CRL_APB_RPLL_CTRL_DIV2 0x1 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFF5E0030, 0x00717F00U ,0x00014800U) - RegMask = (CRL_APB_RPLL_CTRL_PRE_SRC_MASK | CRL_APB_RPLL_CTRL_FBDIV_MASK | CRL_APB_RPLL_CTRL_DIV2_MASK | 0 ); - - RegVal = ((0x00000000U << CRL_APB_RPLL_CTRL_PRE_SRC_SHIFT - | 0x00000048U << CRL_APB_RPLL_CTRL_FBDIV_SHIFT - | 0x00000001U << CRL_APB_RPLL_CTRL_DIV2_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RPLL_CTRL_OFFSET ,0x00717F00U ,0x00014800U); - /*############################################################################################################################ */ - - // : BY PASS PLL - /*Register : RPLL_CTRL @ 0XFF5E0030

- - Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_RPLL_CTRL_BYPASS 1 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFF5E0030, 0x00000008U ,0x00000008U) - RegMask = (CRL_APB_RPLL_CTRL_BYPASS_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_RPLL_CTRL_BYPASS_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RPLL_CTRL_OFFSET ,0x00000008U ,0x00000008U); - /*############################################################################################################################ */ - - // : ASSERT RESET - /*Register : RPLL_CTRL @ 0XFF5E0030

- - Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS. - PSU_CRL_APB_RPLL_CTRL_RESET 1 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFF5E0030, 0x00000001U ,0x00000001U) - RegMask = (CRL_APB_RPLL_CTRL_RESET_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_RPLL_CTRL_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RPLL_CTRL_OFFSET ,0x00000001U ,0x00000001U); - /*############################################################################################################################ */ - - // : DEASSERT RESET - /*Register : RPLL_CTRL @ 0XFF5E0030

- - Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS. - PSU_CRL_APB_RPLL_CTRL_RESET 0 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFF5E0030, 0x00000001U ,0x00000000U) - RegMask = (CRL_APB_RPLL_CTRL_RESET_MASK | 0 ); - - RegVal = ((0x00000000U << CRL_APB_RPLL_CTRL_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RPLL_CTRL_OFFSET ,0x00000001U ,0x00000000U); - /*############################################################################################################################ */ - - // : CHECK PLL STATUS - /*Register : PLL_STATUS @ 0XFF5E0040

- - RPLL is locked - PSU_CRL_APB_PLL_STATUS_RPLL_LOCK 1 - (OFFSET, MASK, VALUE) (0XFF5E0040, 0x00000002U ,0x00000002U) */ - mask_poll(CRL_APB_PLL_STATUS_OFFSET,0x00000002U); - - /*############################################################################################################################ */ - - // : REMOVE PLL BY PASS - /*Register : RPLL_CTRL @ 0XFF5E0030

- - Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_RPLL_CTRL_BYPASS 0 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFF5E0030, 0x00000008U ,0x00000000U) - RegMask = (CRL_APB_RPLL_CTRL_BYPASS_MASK | 0 ); - - RegVal = ((0x00000000U << CRL_APB_RPLL_CTRL_BYPASS_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RPLL_CTRL_OFFSET ,0x00000008U ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : RPLL_TO_FPD_CTRL @ 0XFF5E0048

- - Divisor value for this clock. - PSU_CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0 0x3 - - Control for a clock that will be generated in the LPD, but used in the FPD as a clock source for the peripheral clock muxes. - (OFFSET, MASK, VALUE) (0XFF5E0048, 0x00003F00U ,0x00000300U) - RegMask = (CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_MASK | 0 ); - - RegVal = ((0x00000003U << CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RPLL_TO_FPD_CTRL_OFFSET ,0x00003F00U ,0x00000300U); - /*############################################################################################################################ */ - - // : RPLL FRAC CFG - /*Register : RPLL_FRAC_CFG @ 0XFF5E0038

- - Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona - mode and uses DATA of this register for the fractional portion of the feedback divider. - PSU_CRL_APB_RPLL_FRAC_CFG_ENABLED 0x0 - - Fractional value for the Feedback value. - PSU_CRL_APB_RPLL_FRAC_CFG_DATA 0x0 - - Fractional control for the PLL - (OFFSET, MASK, VALUE) (0XFF5E0038, 0x8000FFFFU ,0x00000000U) - RegMask = (CRL_APB_RPLL_FRAC_CFG_ENABLED_MASK | CRL_APB_RPLL_FRAC_CFG_DATA_MASK | 0 ); - - RegVal = ((0x00000000U << CRL_APB_RPLL_FRAC_CFG_ENABLED_SHIFT - | 0x00000000U << CRL_APB_RPLL_FRAC_CFG_DATA_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RPLL_FRAC_CFG_OFFSET ,0x8000FFFFU ,0x00000000U); - /*############################################################################################################################ */ - - // : IOPLL INIT - /*Register : IOPLL_CFG @ 0XFF5E0024

- - PLL loop filter resistor control - PSU_CRL_APB_IOPLL_CFG_RES 0xc - - PLL charge pump control - PSU_CRL_APB_IOPLL_CFG_CP 0x3 - - PLL loop filter high frequency capacitor control - PSU_CRL_APB_IOPLL_CFG_LFHF 0x3 - - Lock circuit counter setting - PSU_CRL_APB_IOPLL_CFG_LOCK_CNT 0x339 - - Lock circuit configuration settings for lock windowsize - PSU_CRL_APB_IOPLL_CFG_LOCK_DLY 0x3f - - Helper data. Values are to be looked up in a table from Data Sheet - (OFFSET, MASK, VALUE) (0XFF5E0024, 0xFE7FEDEFU ,0x7E672C6CU) - RegMask = (CRL_APB_IOPLL_CFG_RES_MASK | CRL_APB_IOPLL_CFG_CP_MASK | CRL_APB_IOPLL_CFG_LFHF_MASK | CRL_APB_IOPLL_CFG_LOCK_CNT_MASK | CRL_APB_IOPLL_CFG_LOCK_DLY_MASK | 0 ); - - RegVal = ((0x0000000CU << CRL_APB_IOPLL_CFG_RES_SHIFT - | 0x00000003U << CRL_APB_IOPLL_CFG_CP_SHIFT - | 0x00000003U << CRL_APB_IOPLL_CFG_LFHF_SHIFT - | 0x00000339U << CRL_APB_IOPLL_CFG_LOCK_CNT_SHIFT - | 0x0000003FU << CRL_APB_IOPLL_CFG_LOCK_DLY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_IOPLL_CFG_OFFSET ,0xFE7FEDEFU ,0x7E672C6CU); - /*############################################################################################################################ */ - - // : UPDATE FB_DIV - /*Register : IOPLL_CTRL @ 0XFF5E0020

- - Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_ - ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source - PSU_CRL_APB_IOPLL_CTRL_PRE_SRC 0x0 - - The integer portion of the feedback divider to the PLL - PSU_CRL_APB_IOPLL_CTRL_FBDIV 0x2d - - This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency - PSU_CRL_APB_IOPLL_CTRL_DIV2 0x0 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFF5E0020, 0x00717F00U ,0x00002D00U) - RegMask = (CRL_APB_IOPLL_CTRL_PRE_SRC_MASK | CRL_APB_IOPLL_CTRL_FBDIV_MASK | CRL_APB_IOPLL_CTRL_DIV2_MASK | 0 ); - - RegVal = ((0x00000000U << CRL_APB_IOPLL_CTRL_PRE_SRC_SHIFT - | 0x0000002DU << CRL_APB_IOPLL_CTRL_FBDIV_SHIFT - | 0x00000000U << CRL_APB_IOPLL_CTRL_DIV2_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_IOPLL_CTRL_OFFSET ,0x00717F00U ,0x00002D00U); - /*############################################################################################################################ */ - - // : BY PASS PLL - /*Register : IOPLL_CTRL @ 0XFF5E0020

- - Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_IOPLL_CTRL_BYPASS 1 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFF5E0020, 0x00000008U ,0x00000008U) - RegMask = (CRL_APB_IOPLL_CTRL_BYPASS_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_IOPLL_CTRL_BYPASS_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_IOPLL_CTRL_OFFSET ,0x00000008U ,0x00000008U); - /*############################################################################################################################ */ - - // : ASSERT RESET - /*Register : IOPLL_CTRL @ 0XFF5E0020

- - Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS. - PSU_CRL_APB_IOPLL_CTRL_RESET 1 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFF5E0020, 0x00000001U ,0x00000001U) - RegMask = (CRL_APB_IOPLL_CTRL_RESET_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_IOPLL_CTRL_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_IOPLL_CTRL_OFFSET ,0x00000001U ,0x00000001U); - /*############################################################################################################################ */ - - // : DEASSERT RESET - /*Register : IOPLL_CTRL @ 0XFF5E0020

- - Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS. - PSU_CRL_APB_IOPLL_CTRL_RESET 0 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFF5E0020, 0x00000001U ,0x00000000U) - RegMask = (CRL_APB_IOPLL_CTRL_RESET_MASK | 0 ); - - RegVal = ((0x00000000U << CRL_APB_IOPLL_CTRL_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_IOPLL_CTRL_OFFSET ,0x00000001U ,0x00000000U); - /*############################################################################################################################ */ - - // : CHECK PLL STATUS - /*Register : PLL_STATUS @ 0XFF5E0040

- - IOPLL is locked - PSU_CRL_APB_PLL_STATUS_IOPLL_LOCK 1 - (OFFSET, MASK, VALUE) (0XFF5E0040, 0x00000001U ,0x00000001U) */ - mask_poll(CRL_APB_PLL_STATUS_OFFSET,0x00000001U); - - /*############################################################################################################################ */ - - // : REMOVE PLL BY PASS - /*Register : IOPLL_CTRL @ 0XFF5E0020

- - Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_IOPLL_CTRL_BYPASS 0 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFF5E0020, 0x00000008U ,0x00000000U) - RegMask = (CRL_APB_IOPLL_CTRL_BYPASS_MASK | 0 ); - - RegVal = ((0x00000000U << CRL_APB_IOPLL_CTRL_BYPASS_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_IOPLL_CTRL_OFFSET ,0x00000008U ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : IOPLL_TO_FPD_CTRL @ 0XFF5E0044

- - Divisor value for this clock. - PSU_CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0 0x3 - - Control for a clock that will be generated in the LPD, but used in the FPD as a clock source for the peripheral clock muxes. - (OFFSET, MASK, VALUE) (0XFF5E0044, 0x00003F00U ,0x00000300U) - RegMask = (CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_MASK | 0 ); - - RegVal = ((0x00000003U << CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_IOPLL_TO_FPD_CTRL_OFFSET ,0x00003F00U ,0x00000300U); - /*############################################################################################################################ */ - - // : IOPLL FRAC CFG - /*Register : IOPLL_FRAC_CFG @ 0XFF5E0028

- - Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona - mode and uses DATA of this register for the fractional portion of the feedback divider. - PSU_CRL_APB_IOPLL_FRAC_CFG_ENABLED 0x0 - - Fractional value for the Feedback value. - PSU_CRL_APB_IOPLL_FRAC_CFG_DATA 0x0 - - Fractional control for the PLL - (OFFSET, MASK, VALUE) (0XFF5E0028, 0x8000FFFFU ,0x00000000U) - RegMask = (CRL_APB_IOPLL_FRAC_CFG_ENABLED_MASK | CRL_APB_IOPLL_FRAC_CFG_DATA_MASK | 0 ); - - RegVal = ((0x00000000U << CRL_APB_IOPLL_FRAC_CFG_ENABLED_SHIFT - | 0x00000000U << CRL_APB_IOPLL_FRAC_CFG_DATA_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_IOPLL_FRAC_CFG_OFFSET ,0x8000FFFFU ,0x00000000U); - /*############################################################################################################################ */ - - // : APU_PLL INIT - /*Register : APLL_CFG @ 0XFD1A0024

- - PLL loop filter resistor control - PSU_CRF_APB_APLL_CFG_RES 0x2 - - PLL charge pump control - PSU_CRF_APB_APLL_CFG_CP 0x3 - - PLL loop filter high frequency capacitor control - PSU_CRF_APB_APLL_CFG_LFHF 0x3 - - Lock circuit counter setting - PSU_CRF_APB_APLL_CFG_LOCK_CNT 0x258 - - Lock circuit configuration settings for lock windowsize - PSU_CRF_APB_APLL_CFG_LOCK_DLY 0x3f - - Helper data. Values are to be looked up in a table from Data Sheet - (OFFSET, MASK, VALUE) (0XFD1A0024, 0xFE7FEDEFU ,0x7E4B0C62U) - RegMask = (CRF_APB_APLL_CFG_RES_MASK | CRF_APB_APLL_CFG_CP_MASK | CRF_APB_APLL_CFG_LFHF_MASK | CRF_APB_APLL_CFG_LOCK_CNT_MASK | CRF_APB_APLL_CFG_LOCK_DLY_MASK | 0 ); - - RegVal = ((0x00000002U << CRF_APB_APLL_CFG_RES_SHIFT - | 0x00000003U << CRF_APB_APLL_CFG_CP_SHIFT - | 0x00000003U << CRF_APB_APLL_CFG_LFHF_SHIFT - | 0x00000258U << CRF_APB_APLL_CFG_LOCK_CNT_SHIFT - | 0x0000003FU << CRF_APB_APLL_CFG_LOCK_DLY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_APLL_CFG_OFFSET ,0xFE7FEDEFU ,0x7E4B0C62U); - /*############################################################################################################################ */ - - // : UPDATE FB_DIV - /*Register : APLL_CTRL @ 0XFD1A0020

- - Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_ - ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source - PSU_CRF_APB_APLL_CTRL_PRE_SRC 0x0 - - The integer portion of the feedback divider to the PLL - PSU_CRF_APB_APLL_CTRL_FBDIV 0x42 - - This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency - PSU_CRF_APB_APLL_CTRL_DIV2 0x1 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFD1A0020, 0x00717F00U ,0x00014200U) - RegMask = (CRF_APB_APLL_CTRL_PRE_SRC_MASK | CRF_APB_APLL_CTRL_FBDIV_MASK | CRF_APB_APLL_CTRL_DIV2_MASK | 0 ); - - RegVal = ((0x00000000U << CRF_APB_APLL_CTRL_PRE_SRC_SHIFT - | 0x00000042U << CRF_APB_APLL_CTRL_FBDIV_SHIFT - | 0x00000001U << CRF_APB_APLL_CTRL_DIV2_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_APLL_CTRL_OFFSET ,0x00717F00U ,0x00014200U); - /*############################################################################################################################ */ - - // : BY PASS PLL - /*Register : APLL_CTRL @ 0XFD1A0020

- - Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.) - PSU_CRF_APB_APLL_CTRL_BYPASS 1 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFD1A0020, 0x00000008U ,0x00000008U) - RegMask = (CRF_APB_APLL_CTRL_BYPASS_MASK | 0 ); - - RegVal = ((0x00000001U << CRF_APB_APLL_CTRL_BYPASS_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_APLL_CTRL_OFFSET ,0x00000008U ,0x00000008U); - /*############################################################################################################################ */ - - // : ASSERT RESET - /*Register : APLL_CTRL @ 0XFD1A0020

- - Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS. - PSU_CRF_APB_APLL_CTRL_RESET 1 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFD1A0020, 0x00000001U ,0x00000001U) - RegMask = (CRF_APB_APLL_CTRL_RESET_MASK | 0 ); - - RegVal = ((0x00000001U << CRF_APB_APLL_CTRL_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_APLL_CTRL_OFFSET ,0x00000001U ,0x00000001U); - /*############################################################################################################################ */ - - // : DEASSERT RESET - /*Register : APLL_CTRL @ 0XFD1A0020

- - Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS. - PSU_CRF_APB_APLL_CTRL_RESET 0 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFD1A0020, 0x00000001U ,0x00000000U) - RegMask = (CRF_APB_APLL_CTRL_RESET_MASK | 0 ); - - RegVal = ((0x00000000U << CRF_APB_APLL_CTRL_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_APLL_CTRL_OFFSET ,0x00000001U ,0x00000000U); - /*############################################################################################################################ */ - - // : CHECK PLL STATUS - /*Register : PLL_STATUS @ 0XFD1A0044

- - APLL is locked - PSU_CRF_APB_PLL_STATUS_APLL_LOCK 1 - (OFFSET, MASK, VALUE) (0XFD1A0044, 0x00000001U ,0x00000001U) */ - mask_poll(CRF_APB_PLL_STATUS_OFFSET,0x00000001U); - - /*############################################################################################################################ */ - - // : REMOVE PLL BY PASS - /*Register : APLL_CTRL @ 0XFD1A0020

- - Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.) - PSU_CRF_APB_APLL_CTRL_BYPASS 0 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFD1A0020, 0x00000008U ,0x00000000U) - RegMask = (CRF_APB_APLL_CTRL_BYPASS_MASK | 0 ); - - RegVal = ((0x00000000U << CRF_APB_APLL_CTRL_BYPASS_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_APLL_CTRL_OFFSET ,0x00000008U ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : APLL_TO_LPD_CTRL @ 0XFD1A0048

- - Divisor value for this clock. - PSU_CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0 0x3 - - Control for a clock that will be generated in the FPD, but used in the LPD as a clock source for the peripheral clock muxes. - (OFFSET, MASK, VALUE) (0XFD1A0048, 0x00003F00U ,0x00000300U) - RegMask = (CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_MASK | 0 ); - - RegVal = ((0x00000003U << CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_APLL_TO_LPD_CTRL_OFFSET ,0x00003F00U ,0x00000300U); - /*############################################################################################################################ */ - - // : APLL FRAC CFG - /*Register : APLL_FRAC_CFG @ 0XFD1A0028

- - Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona - mode and uses DATA of this register for the fractional portion of the feedback divider. - PSU_CRF_APB_APLL_FRAC_CFG_ENABLED 0x0 - - Fractional value for the Feedback value. - PSU_CRF_APB_APLL_FRAC_CFG_DATA 0x0 - - Fractional control for the PLL - (OFFSET, MASK, VALUE) (0XFD1A0028, 0x8000FFFFU ,0x00000000U) - RegMask = (CRF_APB_APLL_FRAC_CFG_ENABLED_MASK | CRF_APB_APLL_FRAC_CFG_DATA_MASK | 0 ); - - RegVal = ((0x00000000U << CRF_APB_APLL_FRAC_CFG_ENABLED_SHIFT - | 0x00000000U << CRF_APB_APLL_FRAC_CFG_DATA_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_APLL_FRAC_CFG_OFFSET ,0x8000FFFFU ,0x00000000U); - /*############################################################################################################################ */ - - // : DDR_PLL INIT - /*Register : DPLL_CFG @ 0XFD1A0030

- - PLL loop filter resistor control - PSU_CRF_APB_DPLL_CFG_RES 0x2 - - PLL charge pump control - PSU_CRF_APB_DPLL_CFG_CP 0x3 - - PLL loop filter high frequency capacitor control - PSU_CRF_APB_DPLL_CFG_LFHF 0x3 - - Lock circuit counter setting - PSU_CRF_APB_DPLL_CFG_LOCK_CNT 0x258 - - Lock circuit configuration settings for lock windowsize - PSU_CRF_APB_DPLL_CFG_LOCK_DLY 0x3f - - Helper data. Values are to be looked up in a table from Data Sheet - (OFFSET, MASK, VALUE) (0XFD1A0030, 0xFE7FEDEFU ,0x7E4B0C62U) - RegMask = (CRF_APB_DPLL_CFG_RES_MASK | CRF_APB_DPLL_CFG_CP_MASK | CRF_APB_DPLL_CFG_LFHF_MASK | CRF_APB_DPLL_CFG_LOCK_CNT_MASK | CRF_APB_DPLL_CFG_LOCK_DLY_MASK | 0 ); - - RegVal = ((0x00000002U << CRF_APB_DPLL_CFG_RES_SHIFT - | 0x00000003U << CRF_APB_DPLL_CFG_CP_SHIFT - | 0x00000003U << CRF_APB_DPLL_CFG_LFHF_SHIFT - | 0x00000258U << CRF_APB_DPLL_CFG_LOCK_CNT_SHIFT - | 0x0000003FU << CRF_APB_DPLL_CFG_LOCK_DLY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_DPLL_CFG_OFFSET ,0xFE7FEDEFU ,0x7E4B0C62U); - /*############################################################################################################################ */ - - // : UPDATE FB_DIV - /*Register : DPLL_CTRL @ 0XFD1A002C

- - Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_ - ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source - PSU_CRF_APB_DPLL_CTRL_PRE_SRC 0x0 - - The integer portion of the feedback divider to the PLL - PSU_CRF_APB_DPLL_CTRL_FBDIV 0x40 - - This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency - PSU_CRF_APB_DPLL_CTRL_DIV2 0x1 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFD1A002C, 0x00717F00U ,0x00014000U) - RegMask = (CRF_APB_DPLL_CTRL_PRE_SRC_MASK | CRF_APB_DPLL_CTRL_FBDIV_MASK | CRF_APB_DPLL_CTRL_DIV2_MASK | 0 ); - - RegVal = ((0x00000000U << CRF_APB_DPLL_CTRL_PRE_SRC_SHIFT - | 0x00000040U << CRF_APB_DPLL_CTRL_FBDIV_SHIFT - | 0x00000001U << CRF_APB_DPLL_CTRL_DIV2_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_DPLL_CTRL_OFFSET ,0x00717F00U ,0x00014000U); - /*############################################################################################################################ */ - - // : BY PASS PLL - /*Register : DPLL_CTRL @ 0XFD1A002C

- - Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.) - PSU_CRF_APB_DPLL_CTRL_BYPASS 1 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFD1A002C, 0x00000008U ,0x00000008U) - RegMask = (CRF_APB_DPLL_CTRL_BYPASS_MASK | 0 ); - - RegVal = ((0x00000001U << CRF_APB_DPLL_CTRL_BYPASS_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_DPLL_CTRL_OFFSET ,0x00000008U ,0x00000008U); - /*############################################################################################################################ */ - - // : ASSERT RESET - /*Register : DPLL_CTRL @ 0XFD1A002C

- - Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS. - PSU_CRF_APB_DPLL_CTRL_RESET 1 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFD1A002C, 0x00000001U ,0x00000001U) - RegMask = (CRF_APB_DPLL_CTRL_RESET_MASK | 0 ); - - RegVal = ((0x00000001U << CRF_APB_DPLL_CTRL_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_DPLL_CTRL_OFFSET ,0x00000001U ,0x00000001U); - /*############################################################################################################################ */ - - // : DEASSERT RESET - /*Register : DPLL_CTRL @ 0XFD1A002C

- - Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS. - PSU_CRF_APB_DPLL_CTRL_RESET 0 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFD1A002C, 0x00000001U ,0x00000000U) - RegMask = (CRF_APB_DPLL_CTRL_RESET_MASK | 0 ); - - RegVal = ((0x00000000U << CRF_APB_DPLL_CTRL_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_DPLL_CTRL_OFFSET ,0x00000001U ,0x00000000U); - /*############################################################################################################################ */ - - // : CHECK PLL STATUS - /*Register : PLL_STATUS @ 0XFD1A0044

- - DPLL is locked - PSU_CRF_APB_PLL_STATUS_DPLL_LOCK 1 - (OFFSET, MASK, VALUE) (0XFD1A0044, 0x00000002U ,0x00000002U) */ - mask_poll(CRF_APB_PLL_STATUS_OFFSET,0x00000002U); - - /*############################################################################################################################ */ - - // : REMOVE PLL BY PASS - /*Register : DPLL_CTRL @ 0XFD1A002C

- - Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.) - PSU_CRF_APB_DPLL_CTRL_BYPASS 0 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFD1A002C, 0x00000008U ,0x00000000U) - RegMask = (CRF_APB_DPLL_CTRL_BYPASS_MASK | 0 ); - - RegVal = ((0x00000000U << CRF_APB_DPLL_CTRL_BYPASS_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_DPLL_CTRL_OFFSET ,0x00000008U ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : DPLL_TO_LPD_CTRL @ 0XFD1A004C

- - Divisor value for this clock. - PSU_CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0 0x3 - - Control for a clock that will be generated in the FPD, but used in the LPD as a clock source for the peripheral clock muxes. - (OFFSET, MASK, VALUE) (0XFD1A004C, 0x00003F00U ,0x00000300U) - RegMask = (CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_MASK | 0 ); - - RegVal = ((0x00000003U << CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_DPLL_TO_LPD_CTRL_OFFSET ,0x00003F00U ,0x00000300U); - /*############################################################################################################################ */ - - // : DPLL FRAC CFG - /*Register : DPLL_FRAC_CFG @ 0XFD1A0034

- - Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona - mode and uses DATA of this register for the fractional portion of the feedback divider. - PSU_CRF_APB_DPLL_FRAC_CFG_ENABLED 0x0 - - Fractional value for the Feedback value. - PSU_CRF_APB_DPLL_FRAC_CFG_DATA 0x0 - - Fractional control for the PLL - (OFFSET, MASK, VALUE) (0XFD1A0034, 0x8000FFFFU ,0x00000000U) - RegMask = (CRF_APB_DPLL_FRAC_CFG_ENABLED_MASK | CRF_APB_DPLL_FRAC_CFG_DATA_MASK | 0 ); - - RegVal = ((0x00000000U << CRF_APB_DPLL_FRAC_CFG_ENABLED_SHIFT - | 0x00000000U << CRF_APB_DPLL_FRAC_CFG_DATA_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_DPLL_FRAC_CFG_OFFSET ,0x8000FFFFU ,0x00000000U); - /*############################################################################################################################ */ - - // : VIDEO_PLL INIT - /*Register : VPLL_CFG @ 0XFD1A003C

- - PLL loop filter resistor control - PSU_CRF_APB_VPLL_CFG_RES 0x2 - - PLL charge pump control - PSU_CRF_APB_VPLL_CFG_CP 0x3 - - PLL loop filter high frequency capacitor control - PSU_CRF_APB_VPLL_CFG_LFHF 0x3 - - Lock circuit counter setting - PSU_CRF_APB_VPLL_CFG_LOCK_CNT 0x28a - - Lock circuit configuration settings for lock windowsize - PSU_CRF_APB_VPLL_CFG_LOCK_DLY 0x3f - - Helper data. Values are to be looked up in a table from Data Sheet - (OFFSET, MASK, VALUE) (0XFD1A003C, 0xFE7FEDEFU ,0x7E514C62U) - RegMask = (CRF_APB_VPLL_CFG_RES_MASK | CRF_APB_VPLL_CFG_CP_MASK | CRF_APB_VPLL_CFG_LFHF_MASK | CRF_APB_VPLL_CFG_LOCK_CNT_MASK | CRF_APB_VPLL_CFG_LOCK_DLY_MASK | 0 ); - - RegVal = ((0x00000002U << CRF_APB_VPLL_CFG_RES_SHIFT - | 0x00000003U << CRF_APB_VPLL_CFG_CP_SHIFT - | 0x00000003U << CRF_APB_VPLL_CFG_LFHF_SHIFT - | 0x0000028AU << CRF_APB_VPLL_CFG_LOCK_CNT_SHIFT - | 0x0000003FU << CRF_APB_VPLL_CFG_LOCK_DLY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_VPLL_CFG_OFFSET ,0xFE7FEDEFU ,0x7E514C62U); - /*############################################################################################################################ */ - - // : UPDATE FB_DIV - /*Register : VPLL_CTRL @ 0XFD1A0038

- - Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_ - ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source - PSU_CRF_APB_VPLL_CTRL_PRE_SRC 0x0 - - The integer portion of the feedback divider to the PLL - PSU_CRF_APB_VPLL_CTRL_FBDIV 0x39 - - This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency - PSU_CRF_APB_VPLL_CTRL_DIV2 0x1 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFD1A0038, 0x00717F00U ,0x00013900U) - RegMask = (CRF_APB_VPLL_CTRL_PRE_SRC_MASK | CRF_APB_VPLL_CTRL_FBDIV_MASK | CRF_APB_VPLL_CTRL_DIV2_MASK | 0 ); - - RegVal = ((0x00000000U << CRF_APB_VPLL_CTRL_PRE_SRC_SHIFT - | 0x00000039U << CRF_APB_VPLL_CTRL_FBDIV_SHIFT - | 0x00000001U << CRF_APB_VPLL_CTRL_DIV2_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_VPLL_CTRL_OFFSET ,0x00717F00U ,0x00013900U); - /*############################################################################################################################ */ - - // : BY PASS PLL - /*Register : VPLL_CTRL @ 0XFD1A0038

- - Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.) - PSU_CRF_APB_VPLL_CTRL_BYPASS 1 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFD1A0038, 0x00000008U ,0x00000008U) - RegMask = (CRF_APB_VPLL_CTRL_BYPASS_MASK | 0 ); - - RegVal = ((0x00000001U << CRF_APB_VPLL_CTRL_BYPASS_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_VPLL_CTRL_OFFSET ,0x00000008U ,0x00000008U); - /*############################################################################################################################ */ - - // : ASSERT RESET - /*Register : VPLL_CTRL @ 0XFD1A0038

- - Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS. - PSU_CRF_APB_VPLL_CTRL_RESET 1 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFD1A0038, 0x00000001U ,0x00000001U) - RegMask = (CRF_APB_VPLL_CTRL_RESET_MASK | 0 ); - - RegVal = ((0x00000001U << CRF_APB_VPLL_CTRL_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_VPLL_CTRL_OFFSET ,0x00000001U ,0x00000001U); - /*############################################################################################################################ */ - - // : DEASSERT RESET - /*Register : VPLL_CTRL @ 0XFD1A0038

- - Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS. - PSU_CRF_APB_VPLL_CTRL_RESET 0 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFD1A0038, 0x00000001U ,0x00000000U) - RegMask = (CRF_APB_VPLL_CTRL_RESET_MASK | 0 ); - - RegVal = ((0x00000000U << CRF_APB_VPLL_CTRL_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_VPLL_CTRL_OFFSET ,0x00000001U ,0x00000000U); - /*############################################################################################################################ */ - - // : CHECK PLL STATUS - /*Register : PLL_STATUS @ 0XFD1A0044

- - VPLL is locked - PSU_CRF_APB_PLL_STATUS_VPLL_LOCK 1 - (OFFSET, MASK, VALUE) (0XFD1A0044, 0x00000004U ,0x00000004U) */ - mask_poll(CRF_APB_PLL_STATUS_OFFSET,0x00000004U); - - /*############################################################################################################################ */ - - // : REMOVE PLL BY PASS - /*Register : VPLL_CTRL @ 0XFD1A0038

- - Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.) - PSU_CRF_APB_VPLL_CTRL_BYPASS 0 - - PLL Basic Control - (OFFSET, MASK, VALUE) (0XFD1A0038, 0x00000008U ,0x00000000U) - RegMask = (CRF_APB_VPLL_CTRL_BYPASS_MASK | 0 ); - - RegVal = ((0x00000000U << CRF_APB_VPLL_CTRL_BYPASS_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_VPLL_CTRL_OFFSET ,0x00000008U ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : VPLL_TO_LPD_CTRL @ 0XFD1A0050

- - Divisor value for this clock. - PSU_CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0 0x3 - - Control for a clock that will be generated in the FPD, but used in the LPD as a clock source for the peripheral clock muxes. - (OFFSET, MASK, VALUE) (0XFD1A0050, 0x00003F00U ,0x00000300U) - RegMask = (CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_MASK | 0 ); - - RegVal = ((0x00000003U << CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_VPLL_TO_LPD_CTRL_OFFSET ,0x00003F00U ,0x00000300U); - /*############################################################################################################################ */ - - // : VIDEO FRAC CFG - /*Register : VPLL_FRAC_CFG @ 0XFD1A0040

- - Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona - mode and uses DATA of this register for the fractional portion of the feedback divider. - PSU_CRF_APB_VPLL_FRAC_CFG_ENABLED 0x1 - - Fractional value for the Feedback value. - PSU_CRF_APB_VPLL_FRAC_CFG_DATA 0x820c - - Fractional control for the PLL - (OFFSET, MASK, VALUE) (0XFD1A0040, 0x8000FFFFU ,0x8000820CU) - RegMask = (CRF_APB_VPLL_FRAC_CFG_ENABLED_MASK | CRF_APB_VPLL_FRAC_CFG_DATA_MASK | 0 ); - - RegVal = ((0x00000001U << CRF_APB_VPLL_FRAC_CFG_ENABLED_SHIFT - | 0x0000820CU << CRF_APB_VPLL_FRAC_CFG_DATA_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_VPLL_FRAC_CFG_OFFSET ,0x8000FFFFU ,0x8000820CU); - /*############################################################################################################################ */ - - - return 1; + Xil_Out32(addr, rdata); + } + +unsigned long psu_pll_init_data(void) +{ + /* + * RPLL INIT + */ + /* + * Register : RPLL_CFG @ 0XFF5E0034 + + * PLL loop filter resistor control + * PSU_CRL_APB_RPLL_CFG_RES 0xc + + * PLL charge pump control + * PSU_CRL_APB_RPLL_CFG_CP 0x3 + + * PLL loop filter high frequency capacitor control + * PSU_CRL_APB_RPLL_CFG_LFHF 0x3 + + * Lock circuit counter setting + * PSU_CRL_APB_RPLL_CFG_LOCK_CNT 0x339 + + * Lock circuit configuration settings for lock windowsize + * PSU_CRL_APB_RPLL_CFG_LOCK_DLY 0x3f + + * Helper data. Values are to be looked up in a table from Data Sheet + * (OFFSET, MASK, VALUE) (0XFF5E0034, 0xFE7FEDEFU ,0x7E672C6CU) + */ + PSU_Mask_Write(CRL_APB_RPLL_CFG_OFFSET, 0xFE7FEDEFU, 0x7E672C6CU); +/*##################################################################### */ + + /* + * UPDATE FB_DIV + */ + /* + * Register : RPLL_CTRL @ 0XFF5E0030 + + * Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i + * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour + * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source + * PSU_CRL_APB_RPLL_CTRL_PRE_SRC 0x0 + + * The integer portion of the feedback divider to the PLL + * PSU_CRL_APB_RPLL_CTRL_FBDIV 0x2d + + * This turns on the divide by 2 that is inside of the PLL. This does not c + * hange the VCO frequency, just the output frequency + * PSU_CRL_APB_RPLL_CTRL_DIV2 0x1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFF5E0030, 0x00717F00U ,0x00012D00U) + */ + PSU_Mask_Write(CRL_APB_RPLL_CTRL_OFFSET, 0x00717F00U, 0x00012D00U); +/*##################################################################### */ + + /* + * BY PASS PLL + */ + /* + * Register : RPLL_CTRL @ 0XFF5E0030 + + * Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) + * PSU_CRL_APB_RPLL_CTRL_BYPASS 1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFF5E0030, 0x00000008U ,0x00000008U) + */ + PSU_Mask_Write(CRL_APB_RPLL_CTRL_OFFSET, 0x00000008U, 0x00000008U); +/*##################################################################### */ + + /* + * ASSERT RESET + */ + /* + * Register : RPLL_CTRL @ 0XFF5E0030 + + * Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. + * PSU_CRL_APB_RPLL_CTRL_RESET 1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFF5E0030, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(CRL_APB_RPLL_CTRL_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * DEASSERT RESET + */ + /* + * Register : RPLL_CTRL @ 0XFF5E0030 + + * Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. + * PSU_CRL_APB_RPLL_CTRL_RESET 0 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFF5E0030, 0x00000001U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RPLL_CTRL_OFFSET, 0x00000001U, 0x00000000U); +/*##################################################################### */ + + /* + * CHECK PLL STATUS + */ + /* + * Register : PLL_STATUS @ 0XFF5E0040 + + * RPLL is locked + * PSU_CRL_APB_PLL_STATUS_RPLL_LOCK 1 + * (OFFSET, MASK, VALUE) (0XFF5E0040, 0x00000002U ,0x00000002U) + */ + mask_poll(CRL_APB_PLL_STATUS_OFFSET, 0x00000002U); + +/*##################################################################### */ + + /* + * REMOVE PLL BY PASS + */ + /* + * Register : RPLL_CTRL @ 0XFF5E0030 + + * Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) + * PSU_CRL_APB_RPLL_CTRL_BYPASS 0 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFF5E0030, 0x00000008U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RPLL_CTRL_OFFSET, 0x00000008U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : RPLL_TO_FPD_CTRL @ 0XFF5E0048 + + * Divisor value for this clock. + * PSU_CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0 0x2 + + * Control for a clock that will be generated in the LPD, but used in the F + * PD as a clock source for the peripheral clock muxes. + * (OFFSET, MASK, VALUE) (0XFF5E0048, 0x00003F00U ,0x00000200U) + */ + PSU_Mask_Write(CRL_APB_RPLL_TO_FPD_CTRL_OFFSET, + 0x00003F00U, 0x00000200U); +/*##################################################################### */ + + /* + * RPLL FRAC CFG + */ + /* + * IOPLL INIT + */ + /* + * Register : IOPLL_CFG @ 0XFF5E0024 + + * PLL loop filter resistor control + * PSU_CRL_APB_IOPLL_CFG_RES 0x2 + + * PLL charge pump control + * PSU_CRL_APB_IOPLL_CFG_CP 0x4 + + * PLL loop filter high frequency capacitor control + * PSU_CRL_APB_IOPLL_CFG_LFHF 0x3 + + * Lock circuit counter setting + * PSU_CRL_APB_IOPLL_CFG_LOCK_CNT 0x258 + + * Lock circuit configuration settings for lock windowsize + * PSU_CRL_APB_IOPLL_CFG_LOCK_DLY 0x3f + + * Helper data. Values are to be looked up in a table from Data Sheet + * (OFFSET, MASK, VALUE) (0XFF5E0024, 0xFE7FEDEFU ,0x7E4B0C82U) + */ + PSU_Mask_Write(CRL_APB_IOPLL_CFG_OFFSET, 0xFE7FEDEFU, 0x7E4B0C82U); +/*##################################################################### */ + + /* + * UPDATE FB_DIV + */ + /* + * Register : IOPLL_CTRL @ 0XFF5E0020 + + * Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i + * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour + * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source + * PSU_CRL_APB_IOPLL_CTRL_PRE_SRC 0x0 + + * The integer portion of the feedback divider to the PLL + * PSU_CRL_APB_IOPLL_CTRL_FBDIV 0x5a + + * This turns on the divide by 2 that is inside of the PLL. This does not c + * hange the VCO frequency, just the output frequency + * PSU_CRL_APB_IOPLL_CTRL_DIV2 0x1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFF5E0020, 0x00717F00U ,0x00015A00U) + */ + PSU_Mask_Write(CRL_APB_IOPLL_CTRL_OFFSET, 0x00717F00U, 0x00015A00U); +/*##################################################################### */ + + /* + * BY PASS PLL + */ + /* + * Register : IOPLL_CTRL @ 0XFF5E0020 + + * Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) + * PSU_CRL_APB_IOPLL_CTRL_BYPASS 1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFF5E0020, 0x00000008U ,0x00000008U) + */ + PSU_Mask_Write(CRL_APB_IOPLL_CTRL_OFFSET, 0x00000008U, 0x00000008U); +/*##################################################################### */ + + /* + * ASSERT RESET + */ + /* + * Register : IOPLL_CTRL @ 0XFF5E0020 + + * Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. + * PSU_CRL_APB_IOPLL_CTRL_RESET 1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFF5E0020, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(CRL_APB_IOPLL_CTRL_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * DEASSERT RESET + */ + /* + * Register : IOPLL_CTRL @ 0XFF5E0020 + + * Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. + * PSU_CRL_APB_IOPLL_CTRL_RESET 0 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFF5E0020, 0x00000001U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_IOPLL_CTRL_OFFSET, 0x00000001U, 0x00000000U); +/*##################################################################### */ + + /* + * CHECK PLL STATUS + */ + /* + * Register : PLL_STATUS @ 0XFF5E0040 + + * IOPLL is locked + * PSU_CRL_APB_PLL_STATUS_IOPLL_LOCK 1 + * (OFFSET, MASK, VALUE) (0XFF5E0040, 0x00000001U ,0x00000001U) + */ + mask_poll(CRL_APB_PLL_STATUS_OFFSET, 0x00000001U); + +/*##################################################################### */ + + /* + * REMOVE PLL BY PASS + */ + /* + * Register : IOPLL_CTRL @ 0XFF5E0020 + + * Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) + * PSU_CRL_APB_IOPLL_CTRL_BYPASS 0 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFF5E0020, 0x00000008U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_IOPLL_CTRL_OFFSET, 0x00000008U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : IOPLL_TO_FPD_CTRL @ 0XFF5E0044 + + * Divisor value for this clock. + * PSU_CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0 0x3 + + * Control for a clock that will be generated in the LPD, but used in the F + * PD as a clock source for the peripheral clock muxes. + * (OFFSET, MASK, VALUE) (0XFF5E0044, 0x00003F00U ,0x00000300U) + */ + PSU_Mask_Write(CRL_APB_IOPLL_TO_FPD_CTRL_OFFSET, + 0x00003F00U, 0x00000300U); +/*##################################################################### */ + + /* + * IOPLL FRAC CFG + */ + /* + * APU_PLL INIT + */ + /* + * Register : APLL_CFG @ 0XFD1A0024 + + * PLL loop filter resistor control + * PSU_CRF_APB_APLL_CFG_RES 0x2 + + * PLL charge pump control + * PSU_CRF_APB_APLL_CFG_CP 0x3 + + * PLL loop filter high frequency capacitor control + * PSU_CRF_APB_APLL_CFG_LFHF 0x3 + + * Lock circuit counter setting + * PSU_CRF_APB_APLL_CFG_LOCK_CNT 0x258 + + * Lock circuit configuration settings for lock windowsize + * PSU_CRF_APB_APLL_CFG_LOCK_DLY 0x3f + + * Helper data. Values are to be looked up in a table from Data Sheet + * (OFFSET, MASK, VALUE) (0XFD1A0024, 0xFE7FEDEFU ,0x7E4B0C62U) + */ + PSU_Mask_Write(CRF_APB_APLL_CFG_OFFSET, 0xFE7FEDEFU, 0x7E4B0C62U); +/*##################################################################### */ + + /* + * UPDATE FB_DIV + */ + /* + * Register : APLL_CTRL @ 0XFD1A0020 + + * Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i + * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour + * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source + * PSU_CRF_APB_APLL_CTRL_PRE_SRC 0x0 + + * The integer portion of the feedback divider to the PLL + * PSU_CRF_APB_APLL_CTRL_FBDIV 0x48 + + * This turns on the divide by 2 that is inside of the PLL. This does not c + * hange the VCO frequency, just the output frequency + * PSU_CRF_APB_APLL_CTRL_DIV2 0x1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A0020, 0x00717F00U ,0x00014800U) + */ + PSU_Mask_Write(CRF_APB_APLL_CTRL_OFFSET, 0x00717F00U, 0x00014800U); +/*##################################################################### */ + + /* + * BY PASS PLL + */ + /* + * Register : APLL_CTRL @ 0XFD1A0020 + + * Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) + * PSU_CRF_APB_APLL_CTRL_BYPASS 1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A0020, 0x00000008U ,0x00000008U) + */ + PSU_Mask_Write(CRF_APB_APLL_CTRL_OFFSET, 0x00000008U, 0x00000008U); +/*##################################################################### */ + + /* + * ASSERT RESET + */ + /* + * Register : APLL_CTRL @ 0XFD1A0020 + + * Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. + * PSU_CRF_APB_APLL_CTRL_RESET 1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A0020, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(CRF_APB_APLL_CTRL_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * DEASSERT RESET + */ + /* + * Register : APLL_CTRL @ 0XFD1A0020 + + * Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. + * PSU_CRF_APB_APLL_CTRL_RESET 0 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A0020, 0x00000001U ,0x00000000U) + */ + PSU_Mask_Write(CRF_APB_APLL_CTRL_OFFSET, 0x00000001U, 0x00000000U); +/*##################################################################### */ + + /* + * CHECK PLL STATUS + */ + /* + * Register : PLL_STATUS @ 0XFD1A0044 + + * APLL is locked + * PSU_CRF_APB_PLL_STATUS_APLL_LOCK 1 + * (OFFSET, MASK, VALUE) (0XFD1A0044, 0x00000001U ,0x00000001U) + */ + mask_poll(CRF_APB_PLL_STATUS_OFFSET, 0x00000001U); + +/*##################################################################### */ + + /* + * REMOVE PLL BY PASS + */ + /* + * Register : APLL_CTRL @ 0XFD1A0020 + + * Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) + * PSU_CRF_APB_APLL_CTRL_BYPASS 0 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A0020, 0x00000008U ,0x00000000U) + */ + PSU_Mask_Write(CRF_APB_APLL_CTRL_OFFSET, 0x00000008U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : APLL_TO_LPD_CTRL @ 0XFD1A0048 + + * Divisor value for this clock. + * PSU_CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0 0x3 + + * Control for a clock that will be generated in the FPD, but used in the L + * PD as a clock source for the peripheral clock muxes. + * (OFFSET, MASK, VALUE) (0XFD1A0048, 0x00003F00U ,0x00000300U) + */ + PSU_Mask_Write(CRF_APB_APLL_TO_LPD_CTRL_OFFSET, + 0x00003F00U, 0x00000300U); +/*##################################################################### */ + + /* + * APLL FRAC CFG + */ + /* + * DDR_PLL INIT + */ + /* + * Register : DPLL_CFG @ 0XFD1A0030 + + * PLL loop filter resistor control + * PSU_CRF_APB_DPLL_CFG_RES 0x2 + + * PLL charge pump control + * PSU_CRF_APB_DPLL_CFG_CP 0x3 + + * PLL loop filter high frequency capacitor control + * PSU_CRF_APB_DPLL_CFG_LFHF 0x3 + + * Lock circuit counter setting + * PSU_CRF_APB_DPLL_CFG_LOCK_CNT 0x258 + + * Lock circuit configuration settings for lock windowsize + * PSU_CRF_APB_DPLL_CFG_LOCK_DLY 0x3f + + * Helper data. Values are to be looked up in a table from Data Sheet + * (OFFSET, MASK, VALUE) (0XFD1A0030, 0xFE7FEDEFU ,0x7E4B0C62U) + */ + PSU_Mask_Write(CRF_APB_DPLL_CFG_OFFSET, 0xFE7FEDEFU, 0x7E4B0C62U); +/*##################################################################### */ + + /* + * UPDATE FB_DIV + */ + /* + * Register : DPLL_CTRL @ 0XFD1A002C + + * Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i + * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour + * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source + * PSU_CRF_APB_DPLL_CTRL_PRE_SRC 0x0 + + * The integer portion of the feedback divider to the PLL + * PSU_CRF_APB_DPLL_CTRL_FBDIV 0x40 + + * This turns on the divide by 2 that is inside of the PLL. This does not c + * hange the VCO frequency, just the output frequency + * PSU_CRF_APB_DPLL_CTRL_DIV2 0x1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A002C, 0x00717F00U ,0x00014000U) + */ + PSU_Mask_Write(CRF_APB_DPLL_CTRL_OFFSET, 0x00717F00U, 0x00014000U); +/*##################################################################### */ + + /* + * BY PASS PLL + */ + /* + * Register : DPLL_CTRL @ 0XFD1A002C + + * Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) + * PSU_CRF_APB_DPLL_CTRL_BYPASS 1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A002C, 0x00000008U ,0x00000008U) + */ + PSU_Mask_Write(CRF_APB_DPLL_CTRL_OFFSET, 0x00000008U, 0x00000008U); +/*##################################################################### */ + + /* + * ASSERT RESET + */ + /* + * Register : DPLL_CTRL @ 0XFD1A002C + + * Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. + * PSU_CRF_APB_DPLL_CTRL_RESET 1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A002C, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(CRF_APB_DPLL_CTRL_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * DEASSERT RESET + */ + /* + * Register : DPLL_CTRL @ 0XFD1A002C + + * Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. + * PSU_CRF_APB_DPLL_CTRL_RESET 0 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A002C, 0x00000001U ,0x00000000U) + */ + PSU_Mask_Write(CRF_APB_DPLL_CTRL_OFFSET, 0x00000001U, 0x00000000U); +/*##################################################################### */ + + /* + * CHECK PLL STATUS + */ + /* + * Register : PLL_STATUS @ 0XFD1A0044 + + * DPLL is locked + * PSU_CRF_APB_PLL_STATUS_DPLL_LOCK 1 + * (OFFSET, MASK, VALUE) (0XFD1A0044, 0x00000002U ,0x00000002U) + */ + mask_poll(CRF_APB_PLL_STATUS_OFFSET, 0x00000002U); + +/*##################################################################### */ + + /* + * REMOVE PLL BY PASS + */ + /* + * Register : DPLL_CTRL @ 0XFD1A002C + + * Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) + * PSU_CRF_APB_DPLL_CTRL_BYPASS 0 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A002C, 0x00000008U ,0x00000000U) + */ + PSU_Mask_Write(CRF_APB_DPLL_CTRL_OFFSET, 0x00000008U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : DPLL_TO_LPD_CTRL @ 0XFD1A004C + + * Divisor value for this clock. + * PSU_CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0 0x2 + + * Control for a clock that will be generated in the FPD, but used in the L + * PD as a clock source for the peripheral clock muxes. + * (OFFSET, MASK, VALUE) (0XFD1A004C, 0x00003F00U ,0x00000200U) + */ + PSU_Mask_Write(CRF_APB_DPLL_TO_LPD_CTRL_OFFSET, + 0x00003F00U, 0x00000200U); +/*##################################################################### */ + + /* + * DPLL FRAC CFG + */ + /* + * VIDEO_PLL INIT + */ + /* + * Register : VPLL_CFG @ 0XFD1A003C + + * PLL loop filter resistor control + * PSU_CRF_APB_VPLL_CFG_RES 0x2 + + * PLL charge pump control + * PSU_CRF_APB_VPLL_CFG_CP 0x4 + + * PLL loop filter high frequency capacitor control + * PSU_CRF_APB_VPLL_CFG_LFHF 0x3 + + * Lock circuit counter setting + * PSU_CRF_APB_VPLL_CFG_LOCK_CNT 0x258 + + * Lock circuit configuration settings for lock windowsize + * PSU_CRF_APB_VPLL_CFG_LOCK_DLY 0x3f + + * Helper data. Values are to be looked up in a table from Data Sheet + * (OFFSET, MASK, VALUE) (0XFD1A003C, 0xFE7FEDEFU ,0x7E4B0C82U) + */ + PSU_Mask_Write(CRF_APB_VPLL_CFG_OFFSET, 0xFE7FEDEFU, 0x7E4B0C82U); +/*##################################################################### */ + + /* + * UPDATE FB_DIV + */ + /* + * Register : VPLL_CTRL @ 0XFD1A0038 + + * Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i + * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour + * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source + * PSU_CRF_APB_VPLL_CTRL_PRE_SRC 0x0 + + * The integer portion of the feedback divider to the PLL + * PSU_CRF_APB_VPLL_CTRL_FBDIV 0x5a + + * This turns on the divide by 2 that is inside of the PLL. This does not c + * hange the VCO frequency, just the output frequency + * PSU_CRF_APB_VPLL_CTRL_DIV2 0x1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A0038, 0x00717F00U ,0x00015A00U) + */ + PSU_Mask_Write(CRF_APB_VPLL_CTRL_OFFSET, 0x00717F00U, 0x00015A00U); +/*##################################################################### */ + + /* + * BY PASS PLL + */ + /* + * Register : VPLL_CTRL @ 0XFD1A0038 + + * Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) + * PSU_CRF_APB_VPLL_CTRL_BYPASS 1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A0038, 0x00000008U ,0x00000008U) + */ + PSU_Mask_Write(CRF_APB_VPLL_CTRL_OFFSET, 0x00000008U, 0x00000008U); +/*##################################################################### */ + + /* + * ASSERT RESET + */ + /* + * Register : VPLL_CTRL @ 0XFD1A0038 + + * Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. + * PSU_CRF_APB_VPLL_CTRL_RESET 1 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A0038, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(CRF_APB_VPLL_CTRL_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * DEASSERT RESET + */ + /* + * Register : VPLL_CTRL @ 0XFD1A0038 + + * Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. + * PSU_CRF_APB_VPLL_CTRL_RESET 0 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A0038, 0x00000001U ,0x00000000U) + */ + PSU_Mask_Write(CRF_APB_VPLL_CTRL_OFFSET, 0x00000001U, 0x00000000U); +/*##################################################################### */ + + /* + * CHECK PLL STATUS + */ + /* + * Register : PLL_STATUS @ 0XFD1A0044 + + * VPLL is locked + * PSU_CRF_APB_PLL_STATUS_VPLL_LOCK 1 + * (OFFSET, MASK, VALUE) (0XFD1A0044, 0x00000004U ,0x00000004U) + */ + mask_poll(CRF_APB_PLL_STATUS_OFFSET, 0x00000004U); + +/*##################################################################### */ + + /* + * REMOVE PLL BY PASS + */ + /* + * Register : VPLL_CTRL @ 0XFD1A0038 + + * Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) + * PSU_CRF_APB_VPLL_CTRL_BYPASS 0 + + * PLL Basic Control + * (OFFSET, MASK, VALUE) (0XFD1A0038, 0x00000008U ,0x00000000U) + */ + PSU_Mask_Write(CRF_APB_VPLL_CTRL_OFFSET, 0x00000008U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : VPLL_TO_LPD_CTRL @ 0XFD1A0050 + + * Divisor value for this clock. + * PSU_CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0 0x3 + + * Control for a clock that will be generated in the FPD, but used in the L + * PD as a clock source for the peripheral clock muxes. + * (OFFSET, MASK, VALUE) (0XFD1A0050, 0x00003F00U ,0x00000300U) + */ + PSU_Mask_Write(CRF_APB_VPLL_TO_LPD_CTRL_OFFSET, + 0x00003F00U, 0x00000300U); +/*##################################################################### */ + + /* + * VIDEO FRAC CFG + */ + + return 1; } -unsigned long psu_clock_init_data() { - // : CLOCK CONTROL SLCR REGISTER - /*Register : GEM3_REF_CTRL @ 0XFF5E005C

+unsigned long psu_clock_init_data(void) +{ + /* + * CLOCK CONTROL SLCR REGISTER + */ + /* + * Register : GEM3_REF_CTRL @ 0XFF5E005C + + * Clock active for the RX channel + * PSU_CRL_APB_GEM3_REF_CTRL_RX_CLKACT 0x1 - Clock active for the RX channel - PSU_CRL_APB_GEM3_REF_CTRL_RX_CLKACT 0x1 + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_GEM3_REF_CTRL_CLKACT 0x1 - Clock active signal. Switch to 0 to disable the clock - PSU_CRL_APB_GEM3_REF_CTRL_CLKACT 0x1 + * 6 bit divider + * PSU_CRL_APB_GEM3_REF_CTRL_DIVISOR1 0x1 - 6 bit divider - PSU_CRL_APB_GEM3_REF_CTRL_DIVISOR1 0x1 + * 6 bit divider + * PSU_CRL_APB_GEM3_REF_CTRL_DIVISOR0 0xc + + * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_GEM3_REF_CTRL_SRCSEL 0x0 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E005C, 0x063F3F07U ,0x06010C00U) + */ + PSU_Mask_Write(CRL_APB_GEM3_REF_CTRL_OFFSET, + 0x063F3F07U, 0x06010C00U); +/*##################################################################### */ + + /* + * Register : GEM_TSU_REF_CTRL @ 0XFF5E0100 - 6 bit divider - PSU_CRL_APB_GEM3_REF_CTRL_DIVISOR0 0xc + * 6 bit divider + * PSU_CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0 0x6 - 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_GEM3_REF_CTRL_SRCSEL 0x0 + * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_GEM_TSU_REF_CTRL_SRCSEL 0x0 - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E005C, 0x063F3F07U ,0x06010C00U) - RegMask = (CRL_APB_GEM3_REF_CTRL_RX_CLKACT_MASK | CRL_APB_GEM3_REF_CTRL_CLKACT_MASK | CRL_APB_GEM3_REF_CTRL_DIVISOR1_MASK | CRL_APB_GEM3_REF_CTRL_DIVISOR0_MASK | CRL_APB_GEM3_REF_CTRL_SRCSEL_MASK | 0 ); + * 6 bit divider + * PSU_CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1 0x1 - RegVal = ((0x00000001U << CRL_APB_GEM3_REF_CTRL_RX_CLKACT_SHIFT - | 0x00000001U << CRL_APB_GEM3_REF_CTRL_CLKACT_SHIFT - | 0x00000001U << CRL_APB_GEM3_REF_CTRL_DIVISOR1_SHIFT - | 0x0000000CU << CRL_APB_GEM3_REF_CTRL_DIVISOR0_SHIFT - | 0x00000000U << CRL_APB_GEM3_REF_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_GEM3_REF_CTRL_OFFSET ,0x063F3F07U ,0x06010C00U); - /*############################################################################################################################ */ + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_GEM_TSU_REF_CTRL_CLKACT 0x1 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E0100, 0x013F3F07U ,0x01010600U) + */ + PSU_Mask_Write(CRL_APB_GEM_TSU_REF_CTRL_OFFSET, + 0x013F3F07U, 0x01010600U); +/*##################################################################### */ + + /* + * Register : USB0_BUS_REF_CTRL @ 0XFF5E0060 - /*Register : USB0_BUS_REF_CTRL @ 0XFF5E0060

+ * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_USB0_BUS_REF_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1 0x1 + + * 6 bit divider + * PSU_CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0 0x6 + + * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_USB0_BUS_REF_CTRL_SRCSEL 0x0 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E0060, 0x023F3F07U ,0x02010600U) + */ + PSU_Mask_Write(CRL_APB_USB0_BUS_REF_CTRL_OFFSET, + 0x023F3F07U, 0x02010600U); +/*##################################################################### */ + + /* + * Register : USB3_DUAL_REF_CTRL @ 0XFF5E004C - Clock active signal. Switch to 0 to disable the clock - PSU_CRL_APB_USB0_BUS_REF_CTRL_CLKACT 0x1 + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_USB3_DUAL_REF_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1 0x3 + + * 6 bit divider + * PSU_CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0 0x19 + + * 000 = IOPLL; 010 = RPLL; 011 = DPLL. (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL 0x0 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E004C, 0x023F3F07U ,0x02031900U) + */ + PSU_Mask_Write(CRL_APB_USB3_DUAL_REF_CTRL_OFFSET, + 0x023F3F07U, 0x02031900U); +/*##################################################################### */ - 6 bit divider - PSU_CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1 0x1 + /* + * Register : QSPI_REF_CTRL @ 0XFF5E0068 - 6 bit divider - PSU_CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0 0x6 + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_QSPI_REF_CTRL_CLKACT 0x1 - 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_USB0_BUS_REF_CTRL_SRCSEL 0x0 + * 6 bit divider + * PSU_CRL_APB_QSPI_REF_CTRL_DIVISOR1 0x1 + + * 6 bit divider + * PSU_CRL_APB_QSPI_REF_CTRL_DIVISOR0 0xc + + * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_QSPI_REF_CTRL_SRCSEL 0x0 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E0068, 0x013F3F07U ,0x01010C00U) + */ + PSU_Mask_Write(CRL_APB_QSPI_REF_CTRL_OFFSET, + 0x013F3F07U, 0x01010C00U); +/*##################################################################### */ - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E0060, 0x023F3F07U ,0x02010600U) - RegMask = (CRL_APB_USB0_BUS_REF_CTRL_CLKACT_MASK | CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_MASK | CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_MASK | CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_MASK | 0 ); + /* + * Register : SDIO1_REF_CTRL @ 0XFF5E0070 - RegVal = ((0x00000001U << CRL_APB_USB0_BUS_REF_CTRL_CLKACT_SHIFT - | 0x00000001U << CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_SHIFT - | 0x00000006U << CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_SHIFT - | 0x00000000U << CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_USB0_BUS_REF_CTRL_OFFSET ,0x023F3F07U ,0x02010600U); - /*############################################################################################################################ */ + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_SDIO1_REF_CTRL_CLKACT 0x1 - /*Register : USB3_DUAL_REF_CTRL @ 0XFF5E004C

+ * 6 bit divider + * PSU_CRL_APB_SDIO1_REF_CTRL_DIVISOR1 0x1 + + * 6 bit divider + * PSU_CRL_APB_SDIO1_REF_CTRL_DIVISOR0 0x8 + + * 000 = IOPLL; 010 = RPLL; 011 = VPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_SDIO1_REF_CTRL_SRCSEL 0x0 - Clock active signal. Switch to 0 to disable the clock - PSU_CRL_APB_USB3_DUAL_REF_CTRL_CLKACT 0x1 + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E0070, 0x013F3F07U ,0x01010800U) + */ + PSU_Mask_Write(CRL_APB_SDIO1_REF_CTRL_OFFSET, + 0x013F3F07U, 0x01010800U); +/*##################################################################### */ - 6 bit divider - PSU_CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1 0xf + /* + * Register : SDIO_CLK_CTRL @ 0XFF18030C - 6 bit divider - PSU_CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0 0x5 + * MIO pad selection for sdio1_rx_clk (feedback clock from the PAD) 0: MIO + * [51] 1: MIO [76] + * PSU_IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL 0 - 000 = IOPLL; 010 = RPLL; 011 = DPLL. (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL 0x0 + * SoC Debug Clock Control + * (OFFSET, MASK, VALUE) (0XFF18030C, 0x00020000U ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_SDIO_CLK_CTRL_OFFSET, + 0x00020000U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : UART0_REF_CTRL @ 0XFF5E0074 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_UART0_REF_CTRL_CLKACT 0x1 - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E004C, 0x023F3F07U ,0x020F0500U) - RegMask = (CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_MASK | CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_MASK | CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_MASK | CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_MASK | 0 ); + * 6 bit divider + * PSU_CRL_APB_UART0_REF_CTRL_DIVISOR1 0x1 - RegVal = ((0x00000001U << CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_SHIFT - | 0x0000000FU << CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_SHIFT - | 0x00000005U << CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_SHIFT - | 0x00000000U << CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_USB3_DUAL_REF_CTRL_OFFSET ,0x023F3F07U ,0x020F0500U); - /*############################################################################################################################ */ + * 6 bit divider + * PSU_CRL_APB_UART0_REF_CTRL_DIVISOR0 0xf - /*Register : QSPI_REF_CTRL @ 0XFF5E0068

+ * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_UART0_REF_CTRL_SRCSEL 0x0 - Clock active signal. Switch to 0 to disable the clock - PSU_CRL_APB_QSPI_REF_CTRL_CLKACT 0x1 + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E0074, 0x013F3F07U ,0x01010F00U) + */ + PSU_Mask_Write(CRL_APB_UART0_REF_CTRL_OFFSET, + 0x013F3F07U, 0x01010F00U); +/*##################################################################### */ + + /* + * Register : UART1_REF_CTRL @ 0XFF5E0078 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_UART1_REF_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_UART1_REF_CTRL_DIVISOR1 0x1 + + * 6 bit divider + * PSU_CRL_APB_UART1_REF_CTRL_DIVISOR0 0xf - 6 bit divider - PSU_CRL_APB_QSPI_REF_CTRL_DIVISOR1 0x1 + * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_UART1_REF_CTRL_SRCSEL 0x0 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E0078, 0x013F3F07U ,0x01010F00U) + */ + PSU_Mask_Write(CRL_APB_UART1_REF_CTRL_OFFSET, + 0x013F3F07U, 0x01010F00U); +/*##################################################################### */ + + /* + * Register : I2C0_REF_CTRL @ 0XFF5E0120 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_I2C0_REF_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_I2C0_REF_CTRL_DIVISOR1 0x1 + + * 6 bit divider + * PSU_CRL_APB_I2C0_REF_CTRL_DIVISOR0 0xf + + * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_I2C0_REF_CTRL_SRCSEL 0x0 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E0120, 0x013F3F07U ,0x01010F00U) + */ + PSU_Mask_Write(CRL_APB_I2C0_REF_CTRL_OFFSET, + 0x013F3F07U, 0x01010F00U); +/*##################################################################### */ + + /* + * Register : I2C1_REF_CTRL @ 0XFF5E0124 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_I2C1_REF_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_I2C1_REF_CTRL_DIVISOR1 0x1 + + * 6 bit divider + * PSU_CRL_APB_I2C1_REF_CTRL_DIVISOR0 0xf + + * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_I2C1_REF_CTRL_SRCSEL 0x0 - 6 bit divider - PSU_CRL_APB_QSPI_REF_CTRL_DIVISOR0 0xc + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E0124, 0x013F3F07U ,0x01010F00U) + */ + PSU_Mask_Write(CRL_APB_I2C1_REF_CTRL_OFFSET, + 0x013F3F07U, 0x01010F00U); +/*##################################################################### */ + + /* + * Register : CAN1_REF_CTRL @ 0XFF5E0088 - 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_QSPI_REF_CTRL_SRCSEL 0x0 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E0068, 0x013F3F07U ,0x01010C00U) - RegMask = (CRL_APB_QSPI_REF_CTRL_CLKACT_MASK | CRL_APB_QSPI_REF_CTRL_DIVISOR1_MASK | CRL_APB_QSPI_REF_CTRL_DIVISOR0_MASK | CRL_APB_QSPI_REF_CTRL_SRCSEL_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_QSPI_REF_CTRL_CLKACT_SHIFT - | 0x00000001U << CRL_APB_QSPI_REF_CTRL_DIVISOR1_SHIFT - | 0x0000000CU << CRL_APB_QSPI_REF_CTRL_DIVISOR0_SHIFT - | 0x00000000U << CRL_APB_QSPI_REF_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_QSPI_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010C00U); - /*############################################################################################################################ */ - - /*Register : SDIO1_REF_CTRL @ 0XFF5E0070

- - Clock active signal. Switch to 0 to disable the clock - PSU_CRL_APB_SDIO1_REF_CTRL_CLKACT 0x1 - - 6 bit divider - PSU_CRL_APB_SDIO1_REF_CTRL_DIVISOR1 0x1 - - 6 bit divider - PSU_CRL_APB_SDIO1_REF_CTRL_DIVISOR0 0x6 - - 000 = IOPLL; 010 = RPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_SDIO1_REF_CTRL_SRCSEL 0x2 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E0070, 0x013F3F07U ,0x01010602U) - RegMask = (CRL_APB_SDIO1_REF_CTRL_CLKACT_MASK | CRL_APB_SDIO1_REF_CTRL_DIVISOR1_MASK | CRL_APB_SDIO1_REF_CTRL_DIVISOR0_MASK | CRL_APB_SDIO1_REF_CTRL_SRCSEL_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_SDIO1_REF_CTRL_CLKACT_SHIFT - | 0x00000001U << CRL_APB_SDIO1_REF_CTRL_DIVISOR1_SHIFT - | 0x00000006U << CRL_APB_SDIO1_REF_CTRL_DIVISOR0_SHIFT - | 0x00000002U << CRL_APB_SDIO1_REF_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_SDIO1_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010602U); - /*############################################################################################################################ */ - - /*Register : SDIO_CLK_CTRL @ 0XFF18030C

- - MIO pad selection for sdio1_rx_clk (feedback clock from the PAD) 0: MIO [51] 1: MIO [76] - PSU_IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL 0 - - SoC Debug Clock Control - (OFFSET, MASK, VALUE) (0XFF18030C, 0x00020000U ,0x00000000U) - RegMask = (IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_SDIO_CLK_CTRL_OFFSET ,0x00020000U ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : UART0_REF_CTRL @ 0XFF5E0074

- - Clock active signal. Switch to 0 to disable the clock - PSU_CRL_APB_UART0_REF_CTRL_CLKACT 0x1 - - 6 bit divider - PSU_CRL_APB_UART0_REF_CTRL_DIVISOR1 0x1 - - 6 bit divider - PSU_CRL_APB_UART0_REF_CTRL_DIVISOR0 0xf - - 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_UART0_REF_CTRL_SRCSEL 0x0 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E0074, 0x013F3F07U ,0x01010F00U) - RegMask = (CRL_APB_UART0_REF_CTRL_CLKACT_MASK | CRL_APB_UART0_REF_CTRL_DIVISOR1_MASK | CRL_APB_UART0_REF_CTRL_DIVISOR0_MASK | CRL_APB_UART0_REF_CTRL_SRCSEL_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_UART0_REF_CTRL_CLKACT_SHIFT - | 0x00000001U << CRL_APB_UART0_REF_CTRL_DIVISOR1_SHIFT - | 0x0000000FU << CRL_APB_UART0_REF_CTRL_DIVISOR0_SHIFT - | 0x00000000U << CRL_APB_UART0_REF_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_UART0_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010F00U); - /*############################################################################################################################ */ - - /*Register : UART1_REF_CTRL @ 0XFF5E0078

- - Clock active signal. Switch to 0 to disable the clock - PSU_CRL_APB_UART1_REF_CTRL_CLKACT 0x1 - - 6 bit divider - PSU_CRL_APB_UART1_REF_CTRL_DIVISOR1 0x1 - - 6 bit divider - PSU_CRL_APB_UART1_REF_CTRL_DIVISOR0 0xf - - 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_UART1_REF_CTRL_SRCSEL 0x0 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E0078, 0x013F3F07U ,0x01010F00U) - RegMask = (CRL_APB_UART1_REF_CTRL_CLKACT_MASK | CRL_APB_UART1_REF_CTRL_DIVISOR1_MASK | CRL_APB_UART1_REF_CTRL_DIVISOR0_MASK | CRL_APB_UART1_REF_CTRL_SRCSEL_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_UART1_REF_CTRL_CLKACT_SHIFT - | 0x00000001U << CRL_APB_UART1_REF_CTRL_DIVISOR1_SHIFT - | 0x0000000FU << CRL_APB_UART1_REF_CTRL_DIVISOR0_SHIFT - | 0x00000000U << CRL_APB_UART1_REF_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_UART1_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010F00U); - /*############################################################################################################################ */ - - /*Register : I2C0_REF_CTRL @ 0XFF5E0120

- - Clock active signal. Switch to 0 to disable the clock - PSU_CRL_APB_I2C0_REF_CTRL_CLKACT 0x1 - - 6 bit divider - PSU_CRL_APB_I2C0_REF_CTRL_DIVISOR1 0x1 - - 6 bit divider - PSU_CRL_APB_I2C0_REF_CTRL_DIVISOR0 0xf - - 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_I2C0_REF_CTRL_SRCSEL 0x0 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E0120, 0x013F3F07U ,0x01010F00U) - RegMask = (CRL_APB_I2C0_REF_CTRL_CLKACT_MASK | CRL_APB_I2C0_REF_CTRL_DIVISOR1_MASK | CRL_APB_I2C0_REF_CTRL_DIVISOR0_MASK | CRL_APB_I2C0_REF_CTRL_SRCSEL_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_I2C0_REF_CTRL_CLKACT_SHIFT - | 0x00000001U << CRL_APB_I2C0_REF_CTRL_DIVISOR1_SHIFT - | 0x0000000FU << CRL_APB_I2C0_REF_CTRL_DIVISOR0_SHIFT - | 0x00000000U << CRL_APB_I2C0_REF_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_I2C0_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010F00U); - /*############################################################################################################################ */ - - /*Register : I2C1_REF_CTRL @ 0XFF5E0124

- - Clock active signal. Switch to 0 to disable the clock - PSU_CRL_APB_I2C1_REF_CTRL_CLKACT 0x1 - - 6 bit divider - PSU_CRL_APB_I2C1_REF_CTRL_DIVISOR1 0x1 - - 6 bit divider - PSU_CRL_APB_I2C1_REF_CTRL_DIVISOR0 0xf - - 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_I2C1_REF_CTRL_SRCSEL 0x0 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E0124, 0x013F3F07U ,0x01010F00U) - RegMask = (CRL_APB_I2C1_REF_CTRL_CLKACT_MASK | CRL_APB_I2C1_REF_CTRL_DIVISOR1_MASK | CRL_APB_I2C1_REF_CTRL_DIVISOR0_MASK | CRL_APB_I2C1_REF_CTRL_SRCSEL_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_I2C1_REF_CTRL_CLKACT_SHIFT - | 0x00000001U << CRL_APB_I2C1_REF_CTRL_DIVISOR1_SHIFT - | 0x0000000FU << CRL_APB_I2C1_REF_CTRL_DIVISOR0_SHIFT - | 0x00000000U << CRL_APB_I2C1_REF_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_I2C1_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010F00U); - /*############################################################################################################################ */ - - /*Register : CAN1_REF_CTRL @ 0XFF5E0088

- - Clock active signal. Switch to 0 to disable the clock - PSU_CRL_APB_CAN1_REF_CTRL_CLKACT 0x1 - - 6 bit divider - PSU_CRL_APB_CAN1_REF_CTRL_DIVISOR1 0x1 - - 6 bit divider - PSU_CRL_APB_CAN1_REF_CTRL_DIVISOR0 0xf - - 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_CAN1_REF_CTRL_SRCSEL 0x0 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E0088, 0x013F3F07U ,0x01010F00U) - RegMask = (CRL_APB_CAN1_REF_CTRL_CLKACT_MASK | CRL_APB_CAN1_REF_CTRL_DIVISOR1_MASK | CRL_APB_CAN1_REF_CTRL_DIVISOR0_MASK | CRL_APB_CAN1_REF_CTRL_SRCSEL_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_CAN1_REF_CTRL_CLKACT_SHIFT - | 0x00000001U << CRL_APB_CAN1_REF_CTRL_DIVISOR1_SHIFT - | 0x0000000FU << CRL_APB_CAN1_REF_CTRL_DIVISOR0_SHIFT - | 0x00000000U << CRL_APB_CAN1_REF_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_CAN1_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010F00U); - /*############################################################################################################################ */ - - /*Register : CPU_R5_CTRL @ 0XFF5E0090

- - Turing this off will shut down the OCM, some parts of the APM, and prevent transactions going from the FPD to the LPD and cou - d lead to system hang - PSU_CRL_APB_CPU_R5_CTRL_CLKACT 0x1 - - 6 bit divider - PSU_CRL_APB_CPU_R5_CTRL_DIVISOR0 0x3 - - 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_CPU_R5_CTRL_SRCSEL 0x2 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E0090, 0x01003F07U ,0x01000302U) - RegMask = (CRL_APB_CPU_R5_CTRL_CLKACT_MASK | CRL_APB_CPU_R5_CTRL_DIVISOR0_MASK | CRL_APB_CPU_R5_CTRL_SRCSEL_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_CPU_R5_CTRL_CLKACT_SHIFT - | 0x00000003U << CRL_APB_CPU_R5_CTRL_DIVISOR0_SHIFT - | 0x00000002U << CRL_APB_CPU_R5_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_CPU_R5_CTRL_OFFSET ,0x01003F07U ,0x01000302U); - /*############################################################################################################################ */ - - /*Register : IOU_SWITCH_CTRL @ 0XFF5E009C

- - Clock active signal. Switch to 0 to disable the clock - PSU_CRL_APB_IOU_SWITCH_CTRL_CLKACT 0x1 - - 6 bit divider - PSU_CRL_APB_IOU_SWITCH_CTRL_DIVISOR0 0x6 - - 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_IOU_SWITCH_CTRL_SRCSEL 0x2 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E009C, 0x01003F07U ,0x01000602U) - RegMask = (CRL_APB_IOU_SWITCH_CTRL_CLKACT_MASK | CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_MASK | CRL_APB_IOU_SWITCH_CTRL_SRCSEL_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_IOU_SWITCH_CTRL_CLKACT_SHIFT - | 0x00000006U << CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_SHIFT - | 0x00000002U << CRL_APB_IOU_SWITCH_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_IOU_SWITCH_CTRL_OFFSET ,0x01003F07U ,0x01000602U); - /*############################################################################################################################ */ - - /*Register : PCAP_CTRL @ 0XFF5E00A4

- - Clock active signal. Switch to 0 to disable the clock - PSU_CRL_APB_PCAP_CTRL_CLKACT 0x1 - - 6 bit divider - PSU_CRL_APB_PCAP_CTRL_DIVISOR0 0x6 - - 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_PCAP_CTRL_SRCSEL 0x2 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E00A4, 0x01003F07U ,0x01000602U) - RegMask = (CRL_APB_PCAP_CTRL_CLKACT_MASK | CRL_APB_PCAP_CTRL_DIVISOR0_MASK | CRL_APB_PCAP_CTRL_SRCSEL_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_PCAP_CTRL_CLKACT_SHIFT - | 0x00000006U << CRL_APB_PCAP_CTRL_DIVISOR0_SHIFT - | 0x00000002U << CRL_APB_PCAP_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_PCAP_CTRL_OFFSET ,0x01003F07U ,0x01000602U); - /*############################################################################################################################ */ - - /*Register : LPD_SWITCH_CTRL @ 0XFF5E00A8

- - Clock active signal. Switch to 0 to disable the clock - PSU_CRL_APB_LPD_SWITCH_CTRL_CLKACT 0x1 - - 6 bit divider - PSU_CRL_APB_LPD_SWITCH_CTRL_DIVISOR0 0x3 - - 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_LPD_SWITCH_CTRL_SRCSEL 0x2 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E00A8, 0x01003F07U ,0x01000302U) - RegMask = (CRL_APB_LPD_SWITCH_CTRL_CLKACT_MASK | CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_MASK | CRL_APB_LPD_SWITCH_CTRL_SRCSEL_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_LPD_SWITCH_CTRL_CLKACT_SHIFT - | 0x00000003U << CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_SHIFT - | 0x00000002U << CRL_APB_LPD_SWITCH_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_LPD_SWITCH_CTRL_OFFSET ,0x01003F07U ,0x01000302U); - /*############################################################################################################################ */ - - /*Register : LPD_LSBUS_CTRL @ 0XFF5E00AC

- - Clock active signal. Switch to 0 to disable the clock - PSU_CRL_APB_LPD_LSBUS_CTRL_CLKACT 0x1 - - 6 bit divider - PSU_CRL_APB_LPD_LSBUS_CTRL_DIVISOR0 0xf - - 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_LPD_LSBUS_CTRL_SRCSEL 0x2 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E00AC, 0x01003F07U ,0x01000F02U) - RegMask = (CRL_APB_LPD_LSBUS_CTRL_CLKACT_MASK | CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_MASK | CRL_APB_LPD_LSBUS_CTRL_SRCSEL_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_LPD_LSBUS_CTRL_CLKACT_SHIFT - | 0x0000000FU << CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_SHIFT - | 0x00000002U << CRL_APB_LPD_LSBUS_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_LPD_LSBUS_CTRL_OFFSET ,0x01003F07U ,0x01000F02U); - /*############################################################################################################################ */ - - /*Register : DBG_LPD_CTRL @ 0XFF5E00B0

- - Clock active signal. Switch to 0 to disable the clock - PSU_CRL_APB_DBG_LPD_CTRL_CLKACT 0x1 - - 6 bit divider - PSU_CRL_APB_DBG_LPD_CTRL_DIVISOR0 0x6 - - 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_DBG_LPD_CTRL_SRCSEL 0x2 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E00B0, 0x01003F07U ,0x01000602U) - RegMask = (CRL_APB_DBG_LPD_CTRL_CLKACT_MASK | CRL_APB_DBG_LPD_CTRL_DIVISOR0_MASK | CRL_APB_DBG_LPD_CTRL_SRCSEL_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_DBG_LPD_CTRL_CLKACT_SHIFT - | 0x00000006U << CRL_APB_DBG_LPD_CTRL_DIVISOR0_SHIFT - | 0x00000002U << CRL_APB_DBG_LPD_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_DBG_LPD_CTRL_OFFSET ,0x01003F07U ,0x01000602U); - /*############################################################################################################################ */ - - /*Register : ADMA_REF_CTRL @ 0XFF5E00B8

- - Clock active signal. Switch to 0 to disable the clock - PSU_CRL_APB_ADMA_REF_CTRL_CLKACT 0x1 - - 6 bit divider - PSU_CRL_APB_ADMA_REF_CTRL_DIVISOR0 0x3 - - 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_ADMA_REF_CTRL_SRCSEL 0x2 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E00B8, 0x01003F07U ,0x01000302U) - RegMask = (CRL_APB_ADMA_REF_CTRL_CLKACT_MASK | CRL_APB_ADMA_REF_CTRL_DIVISOR0_MASK | CRL_APB_ADMA_REF_CTRL_SRCSEL_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_ADMA_REF_CTRL_CLKACT_SHIFT - | 0x00000003U << CRL_APB_ADMA_REF_CTRL_DIVISOR0_SHIFT - | 0x00000002U << CRL_APB_ADMA_REF_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_ADMA_REF_CTRL_OFFSET ,0x01003F07U ,0x01000302U); - /*############################################################################################################################ */ - - /*Register : PL0_REF_CTRL @ 0XFF5E00C0

- - Clock active signal. Switch to 0 to disable the clock - PSU_CRL_APB_PL0_REF_CTRL_CLKACT 0x1 - - 6 bit divider - PSU_CRL_APB_PL0_REF_CTRL_DIVISOR1 0x1 - - 6 bit divider - PSU_CRL_APB_PL0_REF_CTRL_DIVISOR0 0xf - - 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_PL0_REF_CTRL_SRCSEL 0x0 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E00C0, 0x013F3F07U ,0x01010F00U) - RegMask = (CRL_APB_PL0_REF_CTRL_CLKACT_MASK | CRL_APB_PL0_REF_CTRL_DIVISOR1_MASK | CRL_APB_PL0_REF_CTRL_DIVISOR0_MASK | CRL_APB_PL0_REF_CTRL_SRCSEL_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_PL0_REF_CTRL_CLKACT_SHIFT - | 0x00000001U << CRL_APB_PL0_REF_CTRL_DIVISOR1_SHIFT - | 0x0000000FU << CRL_APB_PL0_REF_CTRL_DIVISOR0_SHIFT - | 0x00000000U << CRL_APB_PL0_REF_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_PL0_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010F00U); - /*############################################################################################################################ */ - - /*Register : PL1_REF_CTRL @ 0XFF5E00C4

- - Clock active signal. Switch to 0 to disable the clock - PSU_CRL_APB_PL1_REF_CTRL_CLKACT 0x1 - - 6 bit divider - PSU_CRL_APB_PL1_REF_CTRL_DIVISOR1 0x4 - - 6 bit divider - PSU_CRL_APB_PL1_REF_CTRL_DIVISOR0 0xf - - 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_PL1_REF_CTRL_SRCSEL 0x0 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E00C4, 0x013F3F07U ,0x01040F00U) - RegMask = (CRL_APB_PL1_REF_CTRL_CLKACT_MASK | CRL_APB_PL1_REF_CTRL_DIVISOR1_MASK | CRL_APB_PL1_REF_CTRL_DIVISOR0_MASK | CRL_APB_PL1_REF_CTRL_SRCSEL_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_PL1_REF_CTRL_CLKACT_SHIFT - | 0x00000004U << CRL_APB_PL1_REF_CTRL_DIVISOR1_SHIFT - | 0x0000000FU << CRL_APB_PL1_REF_CTRL_DIVISOR0_SHIFT - | 0x00000000U << CRL_APB_PL1_REF_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_PL1_REF_CTRL_OFFSET ,0x013F3F07U ,0x01040F00U); - /*############################################################################################################################ */ - - /*Register : PL2_REF_CTRL @ 0XFF5E00C8

- - Clock active signal. Switch to 0 to disable the clock - PSU_CRL_APB_PL2_REF_CTRL_CLKACT 0x1 - - 6 bit divider - PSU_CRL_APB_PL2_REF_CTRL_DIVISOR1 0x1 - - 6 bit divider - PSU_CRL_APB_PL2_REF_CTRL_DIVISOR0 0x4 - - 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_PL2_REF_CTRL_SRCSEL 0x2 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E00C8, 0x013F3F07U ,0x01010402U) - RegMask = (CRL_APB_PL2_REF_CTRL_CLKACT_MASK | CRL_APB_PL2_REF_CTRL_DIVISOR1_MASK | CRL_APB_PL2_REF_CTRL_DIVISOR0_MASK | CRL_APB_PL2_REF_CTRL_SRCSEL_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_PL2_REF_CTRL_CLKACT_SHIFT - | 0x00000001U << CRL_APB_PL2_REF_CTRL_DIVISOR1_SHIFT - | 0x00000004U << CRL_APB_PL2_REF_CTRL_DIVISOR0_SHIFT - | 0x00000002U << CRL_APB_PL2_REF_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_PL2_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010402U); - /*############################################################################################################################ */ - - /*Register : PL3_REF_CTRL @ 0XFF5E00CC

- - Clock active signal. Switch to 0 to disable the clock - PSU_CRL_APB_PL3_REF_CTRL_CLKACT 0x1 - - 6 bit divider - PSU_CRL_APB_PL3_REF_CTRL_DIVISOR1 0x1 - - 6 bit divider - PSU_CRL_APB_PL3_REF_CTRL_DIVISOR0 0x3 - - 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_PL3_REF_CTRL_SRCSEL 0x2 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E00CC, 0x013F3F07U ,0x01010302U) - RegMask = (CRL_APB_PL3_REF_CTRL_CLKACT_MASK | CRL_APB_PL3_REF_CTRL_DIVISOR1_MASK | CRL_APB_PL3_REF_CTRL_DIVISOR0_MASK | CRL_APB_PL3_REF_CTRL_SRCSEL_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_PL3_REF_CTRL_CLKACT_SHIFT - | 0x00000001U << CRL_APB_PL3_REF_CTRL_DIVISOR1_SHIFT - | 0x00000003U << CRL_APB_PL3_REF_CTRL_DIVISOR0_SHIFT - | 0x00000002U << CRL_APB_PL3_REF_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_PL3_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010302U); - /*############################################################################################################################ */ - - /*Register : AMS_REF_CTRL @ 0XFF5E0108

- - 6 bit divider - PSU_CRL_APB_AMS_REF_CTRL_DIVISOR1 0x1 - - 6 bit divider - PSU_CRL_APB_AMS_REF_CTRL_DIVISOR0 0x1d - - 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_AMS_REF_CTRL_SRCSEL 0x2 - - Clock active signal. Switch to 0 to disable the clock - PSU_CRL_APB_AMS_REF_CTRL_CLKACT 0x1 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E0108, 0x013F3F07U ,0x01011D02U) - RegMask = (CRL_APB_AMS_REF_CTRL_DIVISOR1_MASK | CRL_APB_AMS_REF_CTRL_DIVISOR0_MASK | CRL_APB_AMS_REF_CTRL_SRCSEL_MASK | CRL_APB_AMS_REF_CTRL_CLKACT_MASK | 0 ); - - RegVal = ((0x00000001U << CRL_APB_AMS_REF_CTRL_DIVISOR1_SHIFT - | 0x0000001DU << CRL_APB_AMS_REF_CTRL_DIVISOR0_SHIFT - | 0x00000002U << CRL_APB_AMS_REF_CTRL_SRCSEL_SHIFT - | 0x00000001U << CRL_APB_AMS_REF_CTRL_CLKACT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_AMS_REF_CTRL_OFFSET ,0x013F3F07U ,0x01011D02U); - /*############################################################################################################################ */ - - /*Register : DLL_REF_CTRL @ 0XFF5E0104

- - 000 = IOPLL; 001 = RPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This - is not usually an issue, but designers must be aware.) - PSU_CRL_APB_DLL_REF_CTRL_SRCSEL 0 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E0104, 0x00000007U ,0x00000000U) - RegMask = (CRL_APB_DLL_REF_CTRL_SRCSEL_MASK | 0 ); - - RegVal = ((0x00000000U << CRL_APB_DLL_REF_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_DLL_REF_CTRL_OFFSET ,0x00000007U ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : TIMESTAMP_REF_CTRL @ 0XFF5E0128

- - 6 bit divider - PSU_CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0 0xf - - 1XX = pss_ref_clk; 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and - cycles of the new clock. This is not usually an issue, but designers must be aware.) - PSU_CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL 0x0 - - Clock active signal. Switch to 0 to disable the clock - PSU_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT 0x1 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFF5E0128, 0x01003F07U ,0x01000F00U) - RegMask = (CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_MASK | CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_MASK | CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_MASK | 0 ); - - RegVal = ((0x0000000FU << CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_SHIFT - | 0x00000000U << CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_SHIFT - | 0x00000001U << CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_TIMESTAMP_REF_CTRL_OFFSET ,0x01003F07U ,0x01000F00U); - /*############################################################################################################################ */ - - /*Register : SATA_REF_CTRL @ 0XFD1A00A0

- - 000 = IOPLL_TO_FPD; 010 = APLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of - he new clock. This is not usually an issue, but designers must be aware.) - PSU_CRF_APB_SATA_REF_CTRL_SRCSEL 0x0 - - Clock active signal. Switch to 0 to disable the clock - PSU_CRF_APB_SATA_REF_CTRL_CLKACT 0x1 - - 6 bit divider - PSU_CRF_APB_SATA_REF_CTRL_DIVISOR0 0x2 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFD1A00A0, 0x01003F07U ,0x01000200U) - RegMask = (CRF_APB_SATA_REF_CTRL_SRCSEL_MASK | CRF_APB_SATA_REF_CTRL_CLKACT_MASK | CRF_APB_SATA_REF_CTRL_DIVISOR0_MASK | 0 ); - - RegVal = ((0x00000000U << CRF_APB_SATA_REF_CTRL_SRCSEL_SHIFT - | 0x00000001U << CRF_APB_SATA_REF_CTRL_CLKACT_SHIFT - | 0x00000002U << CRF_APB_SATA_REF_CTRL_DIVISOR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_SATA_REF_CTRL_OFFSET ,0x01003F07U ,0x01000200U); - /*############################################################################################################################ */ - - /*Register : PCIE_REF_CTRL @ 0XFD1A00B4

- - 000 = IOPLL_TO_FPD; 010 = RPLL_TO_FPD; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cyc - es of the new clock. This is not usually an issue, but designers must be aware.) - PSU_CRF_APB_PCIE_REF_CTRL_SRCSEL 0x0 - - Clock active signal. Switch to 0 to disable the clock - PSU_CRF_APB_PCIE_REF_CTRL_CLKACT 0x1 - - 6 bit divider - PSU_CRF_APB_PCIE_REF_CTRL_DIVISOR0 0x2 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFD1A00B4, 0x01003F07U ,0x01000200U) - RegMask = (CRF_APB_PCIE_REF_CTRL_SRCSEL_MASK | CRF_APB_PCIE_REF_CTRL_CLKACT_MASK | CRF_APB_PCIE_REF_CTRL_DIVISOR0_MASK | 0 ); - - RegVal = ((0x00000000U << CRF_APB_PCIE_REF_CTRL_SRCSEL_SHIFT - | 0x00000001U << CRF_APB_PCIE_REF_CTRL_CLKACT_SHIFT - | 0x00000002U << CRF_APB_PCIE_REF_CTRL_DIVISOR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_PCIE_REF_CTRL_OFFSET ,0x01003F07U ,0x01000200U); - /*############################################################################################################################ */ - - /*Register : DP_VIDEO_REF_CTRL @ 0XFD1A0070

- - 6 bit divider - PSU_CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1 0x1 - - 6 bit divider - PSU_CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0 0x3 - - 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (This signal may only be toggled after 4 cycles of the - ld clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.) - PSU_CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL 0x3 - - Clock active signal. Switch to 0 to disable the clock - PSU_CRF_APB_DP_VIDEO_REF_CTRL_CLKACT 0x1 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFD1A0070, 0x013F3F07U ,0x01010303U) - RegMask = (CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_MASK | CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_MASK | CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_MASK | CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_MASK | 0 ); - - RegVal = ((0x00000001U << CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_SHIFT - | 0x00000003U << CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_SHIFT - | 0x00000003U << CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_SHIFT - | 0x00000001U << CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_DP_VIDEO_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010303U); - /*############################################################################################################################ */ - - /*Register : DP_AUDIO_REF_CTRL @ 0XFD1A0074

- - 6 bit divider - PSU_CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1 0x1 - - 6 bit divider - PSU_CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0 0x27 - - 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (This signal may only be toggled after 4 cycles of the - ld clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.) - PSU_CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL 0x0 - - Clock active signal. Switch to 0 to disable the clock - PSU_CRF_APB_DP_AUDIO_REF_CTRL_CLKACT 0x1 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFD1A0074, 0x013F3F07U ,0x01012700U) - RegMask = (CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_MASK | CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_MASK | CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_MASK | CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_MASK | 0 ); - - RegVal = ((0x00000001U << CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_SHIFT - | 0x00000027U << CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_SHIFT - | 0x00000000U << CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_SHIFT - | 0x00000001U << CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_DP_AUDIO_REF_CTRL_OFFSET ,0x013F3F07U ,0x01012700U); - /*############################################################################################################################ */ - - /*Register : DP_STC_REF_CTRL @ 0XFD1A007C

- - 6 bit divider - PSU_CRF_APB_DP_STC_REF_CTRL_DIVISOR1 0x1 - - 6 bit divider - PSU_CRF_APB_DP_STC_REF_CTRL_DIVISOR0 0x11 - - 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of t - e new clock. This is not usually an issue, but designers must be aware.) - PSU_CRF_APB_DP_STC_REF_CTRL_SRCSEL 0x3 - - Clock active signal. Switch to 0 to disable the clock - PSU_CRF_APB_DP_STC_REF_CTRL_CLKACT 0x1 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFD1A007C, 0x013F3F07U ,0x01011103U) - RegMask = (CRF_APB_DP_STC_REF_CTRL_DIVISOR1_MASK | CRF_APB_DP_STC_REF_CTRL_DIVISOR0_MASK | CRF_APB_DP_STC_REF_CTRL_SRCSEL_MASK | CRF_APB_DP_STC_REF_CTRL_CLKACT_MASK | 0 ); - - RegVal = ((0x00000001U << CRF_APB_DP_STC_REF_CTRL_DIVISOR1_SHIFT - | 0x00000011U << CRF_APB_DP_STC_REF_CTRL_DIVISOR0_SHIFT - | 0x00000003U << CRF_APB_DP_STC_REF_CTRL_SRCSEL_SHIFT - | 0x00000001U << CRF_APB_DP_STC_REF_CTRL_CLKACT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_DP_STC_REF_CTRL_OFFSET ,0x013F3F07U ,0x01011103U); - /*############################################################################################################################ */ - - /*Register : ACPU_CTRL @ 0XFD1A0060

- - 6 bit divider - PSU_CRF_APB_ACPU_CTRL_DIVISOR0 0x1 - - 000 = APLL; 010 = DPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - lock. This is not usually an issue, but designers must be aware.) - PSU_CRF_APB_ACPU_CTRL_SRCSEL 0x0 - - Clock active signal. Switch to 0 to disable the clock. For the half speed APU Clock - PSU_CRF_APB_ACPU_CTRL_CLKACT_HALF 0x1 - - Clock active signal. Switch to 0 to disable the clock. For the full speed ACPUX Clock. This will shut off the high speed cloc - to the entire APU - PSU_CRF_APB_ACPU_CTRL_CLKACT_FULL 0x1 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFD1A0060, 0x03003F07U ,0x03000100U) - RegMask = (CRF_APB_ACPU_CTRL_DIVISOR0_MASK | CRF_APB_ACPU_CTRL_SRCSEL_MASK | CRF_APB_ACPU_CTRL_CLKACT_HALF_MASK | CRF_APB_ACPU_CTRL_CLKACT_FULL_MASK | 0 ); - - RegVal = ((0x00000001U << CRF_APB_ACPU_CTRL_DIVISOR0_SHIFT - | 0x00000000U << CRF_APB_ACPU_CTRL_SRCSEL_SHIFT - | 0x00000001U << CRF_APB_ACPU_CTRL_CLKACT_HALF_SHIFT - | 0x00000001U << CRF_APB_ACPU_CTRL_CLKACT_FULL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_ACPU_CTRL_OFFSET ,0x03003F07U ,0x03000100U); - /*############################################################################################################################ */ - - /*Register : DBG_TRACE_CTRL @ 0XFD1A0064

- - 6 bit divider - PSU_CRF_APB_DBG_TRACE_CTRL_DIVISOR0 0x2 - - 000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of - he new clock. This is not usually an issue, but designers must be aware.) - PSU_CRF_APB_DBG_TRACE_CTRL_SRCSEL 0x0 - - Clock active signal. Switch to 0 to disable the clock - PSU_CRF_APB_DBG_TRACE_CTRL_CLKACT 0x1 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFD1A0064, 0x01003F07U ,0x01000200U) - RegMask = (CRF_APB_DBG_TRACE_CTRL_DIVISOR0_MASK | CRF_APB_DBG_TRACE_CTRL_SRCSEL_MASK | CRF_APB_DBG_TRACE_CTRL_CLKACT_MASK | 0 ); - - RegVal = ((0x00000002U << CRF_APB_DBG_TRACE_CTRL_DIVISOR0_SHIFT - | 0x00000000U << CRF_APB_DBG_TRACE_CTRL_SRCSEL_SHIFT - | 0x00000001U << CRF_APB_DBG_TRACE_CTRL_CLKACT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_DBG_TRACE_CTRL_OFFSET ,0x01003F07U ,0x01000200U); - /*############################################################################################################################ */ - - /*Register : DBG_FPD_CTRL @ 0XFD1A0068

- - 6 bit divider - PSU_CRF_APB_DBG_FPD_CTRL_DIVISOR0 0x2 - - 000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of - he new clock. This is not usually an issue, but designers must be aware.) - PSU_CRF_APB_DBG_FPD_CTRL_SRCSEL 0x0 - - Clock active signal. Switch to 0 to disable the clock - PSU_CRF_APB_DBG_FPD_CTRL_CLKACT 0x1 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFD1A0068, 0x01003F07U ,0x01000200U) - RegMask = (CRF_APB_DBG_FPD_CTRL_DIVISOR0_MASK | CRF_APB_DBG_FPD_CTRL_SRCSEL_MASK | CRF_APB_DBG_FPD_CTRL_CLKACT_MASK | 0 ); - - RegVal = ((0x00000002U << CRF_APB_DBG_FPD_CTRL_DIVISOR0_SHIFT - | 0x00000000U << CRF_APB_DBG_FPD_CTRL_SRCSEL_SHIFT - | 0x00000001U << CRF_APB_DBG_FPD_CTRL_CLKACT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_DBG_FPD_CTRL_OFFSET ,0x01003F07U ,0x01000200U); - /*############################################################################################################################ */ - - /*Register : DDR_CTRL @ 0XFD1A0080

- - 6 bit divider - PSU_CRF_APB_DDR_CTRL_DIVISOR0 0x2 - - 000 = DPLL; 001 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This - s not usually an issue, but designers must be aware.) - PSU_CRF_APB_DDR_CTRL_SRCSEL 0x0 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFD1A0080, 0x00003F07U ,0x00000200U) - RegMask = (CRF_APB_DDR_CTRL_DIVISOR0_MASK | CRF_APB_DDR_CTRL_SRCSEL_MASK | 0 ); - - RegVal = ((0x00000002U << CRF_APB_DDR_CTRL_DIVISOR0_SHIFT - | 0x00000000U << CRF_APB_DDR_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_DDR_CTRL_OFFSET ,0x00003F07U ,0x00000200U); - /*############################################################################################################################ */ - - /*Register : GPU_REF_CTRL @ 0XFD1A0084

- - 6 bit divider - PSU_CRF_APB_GPU_REF_CTRL_DIVISOR0 0x1 - - 000 = IOPLL_TO_FPD; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of - he new clock. This is not usually an issue, but designers must be aware.) - PSU_CRF_APB_GPU_REF_CTRL_SRCSEL 0x0 - - Clock active signal. Switch to 0 to disable the clock, which will stop clock for GPU (and both Pixel Processors). - PSU_CRF_APB_GPU_REF_CTRL_CLKACT 0x1 - - Clock active signal for Pixel Processor. Switch to 0 to disable the clock only to this Pixel Processor - PSU_CRF_APB_GPU_REF_CTRL_PP0_CLKACT 0x1 - - Clock active signal for Pixel Processor. Switch to 0 to disable the clock only to this Pixel Processor - PSU_CRF_APB_GPU_REF_CTRL_PP1_CLKACT 0x1 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFD1A0084, 0x07003F07U ,0x07000100U) - RegMask = (CRF_APB_GPU_REF_CTRL_DIVISOR0_MASK | CRF_APB_GPU_REF_CTRL_SRCSEL_MASK | CRF_APB_GPU_REF_CTRL_CLKACT_MASK | CRF_APB_GPU_REF_CTRL_PP0_CLKACT_MASK | CRF_APB_GPU_REF_CTRL_PP1_CLKACT_MASK | 0 ); - - RegVal = ((0x00000001U << CRF_APB_GPU_REF_CTRL_DIVISOR0_SHIFT - | 0x00000000U << CRF_APB_GPU_REF_CTRL_SRCSEL_SHIFT - | 0x00000001U << CRF_APB_GPU_REF_CTRL_CLKACT_SHIFT - | 0x00000001U << CRF_APB_GPU_REF_CTRL_PP0_CLKACT_SHIFT - | 0x00000001U << CRF_APB_GPU_REF_CTRL_PP1_CLKACT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_GPU_REF_CTRL_OFFSET ,0x07003F07U ,0x07000100U); - /*############################################################################################################################ */ - - /*Register : GDMA_REF_CTRL @ 0XFD1A00B8

- - 6 bit divider - PSU_CRF_APB_GDMA_REF_CTRL_DIVISOR0 0x2 - - 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - lock. This is not usually an issue, but designers must be aware.) - PSU_CRF_APB_GDMA_REF_CTRL_SRCSEL 0x0 - - Clock active signal. Switch to 0 to disable the clock - PSU_CRF_APB_GDMA_REF_CTRL_CLKACT 0x1 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFD1A00B8, 0x01003F07U ,0x01000200U) - RegMask = (CRF_APB_GDMA_REF_CTRL_DIVISOR0_MASK | CRF_APB_GDMA_REF_CTRL_SRCSEL_MASK | CRF_APB_GDMA_REF_CTRL_CLKACT_MASK | 0 ); - - RegVal = ((0x00000002U << CRF_APB_GDMA_REF_CTRL_DIVISOR0_SHIFT - | 0x00000000U << CRF_APB_GDMA_REF_CTRL_SRCSEL_SHIFT - | 0x00000001U << CRF_APB_GDMA_REF_CTRL_CLKACT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_GDMA_REF_CTRL_OFFSET ,0x01003F07U ,0x01000200U); - /*############################################################################################################################ */ - - /*Register : DPDMA_REF_CTRL @ 0XFD1A00BC

- - 6 bit divider - PSU_CRF_APB_DPDMA_REF_CTRL_DIVISOR0 0x2 - - 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - lock. This is not usually an issue, but designers must be aware.) - PSU_CRF_APB_DPDMA_REF_CTRL_SRCSEL 0x0 - - Clock active signal. Switch to 0 to disable the clock - PSU_CRF_APB_DPDMA_REF_CTRL_CLKACT 0x1 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFD1A00BC, 0x01003F07U ,0x01000200U) - RegMask = (CRF_APB_DPDMA_REF_CTRL_DIVISOR0_MASK | CRF_APB_DPDMA_REF_CTRL_SRCSEL_MASK | CRF_APB_DPDMA_REF_CTRL_CLKACT_MASK | 0 ); - - RegVal = ((0x00000002U << CRF_APB_DPDMA_REF_CTRL_DIVISOR0_SHIFT - | 0x00000000U << CRF_APB_DPDMA_REF_CTRL_SRCSEL_SHIFT - | 0x00000001U << CRF_APB_DPDMA_REF_CTRL_CLKACT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_DPDMA_REF_CTRL_OFFSET ,0x01003F07U ,0x01000200U); - /*############################################################################################################################ */ - - /*Register : TOPSW_MAIN_CTRL @ 0XFD1A00C0

- - 6 bit divider - PSU_CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0 0x2 - - 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - lock. This is not usually an issue, but designers must be aware.) - PSU_CRF_APB_TOPSW_MAIN_CTRL_SRCSEL 0x2 - - Clock active signal. Switch to 0 to disable the clock - PSU_CRF_APB_TOPSW_MAIN_CTRL_CLKACT 0x1 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFD1A00C0, 0x01003F07U ,0x01000202U) - RegMask = (CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_MASK | CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_MASK | CRF_APB_TOPSW_MAIN_CTRL_CLKACT_MASK | 0 ); - - RegVal = ((0x00000002U << CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_SHIFT - | 0x00000002U << CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_SHIFT - | 0x00000001U << CRF_APB_TOPSW_MAIN_CTRL_CLKACT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_TOPSW_MAIN_CTRL_OFFSET ,0x01003F07U ,0x01000202U); - /*############################################################################################################################ */ - - /*Register : TOPSW_LSBUS_CTRL @ 0XFD1A00C4

- - 6 bit divider - PSU_CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0 0x5 - - 000 = APLL; 010 = IOPLL_TO_FPD; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of - he new clock. This is not usually an issue, but designers must be aware.) - PSU_CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL 0x2 - - Clock active signal. Switch to 0 to disable the clock - PSU_CRF_APB_TOPSW_LSBUS_CTRL_CLKACT 0x1 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFD1A00C4, 0x01003F07U ,0x01000502U) - RegMask = (CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_MASK | CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_MASK | CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_MASK | 0 ); - - RegVal = ((0x00000005U << CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_SHIFT - | 0x00000002U << CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_SHIFT - | 0x00000001U << CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_TOPSW_LSBUS_CTRL_OFFSET ,0x01003F07U ,0x01000502U); - /*############################################################################################################################ */ - - /*Register : DBG_TSTMP_CTRL @ 0XFD1A00F8

- - 6 bit divider - PSU_CRF_APB_DBG_TSTMP_CTRL_DIVISOR0 0x2 - - 000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of - he new clock. This is not usually an issue, but designers must be aware.) - PSU_CRF_APB_DBG_TSTMP_CTRL_SRCSEL 0x0 - - This register controls this reference clock - (OFFSET, MASK, VALUE) (0XFD1A00F8, 0x00003F07U ,0x00000200U) - RegMask = (CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_MASK | CRF_APB_DBG_TSTMP_CTRL_SRCSEL_MASK | 0 ); - - RegVal = ((0x00000002U << CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_SHIFT - | 0x00000000U << CRF_APB_DBG_TSTMP_CTRL_SRCSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_DBG_TSTMP_CTRL_OFFSET ,0x00003F07U ,0x00000200U); - /*############################################################################################################################ */ - - /*Register : IOU_TTC_APB_CLK @ 0XFF180380

- - 00" = Select the APB switch clock for the APB interface of TTC0'01" = Select the PLL ref clock for the APB interface of TTC0' - 0" = Select the R5 clock for the APB interface of TTC0 - PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL 0 - - 00" = Select the APB switch clock for the APB interface of TTC1'01" = Select the PLL ref clock for the APB interface of TTC1' - 0" = Select the R5 clock for the APB interface of TTC1 - PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL 0 - - 00" = Select the APB switch clock for the APB interface of TTC2'01" = Select the PLL ref clock for the APB interface of TTC2' - 0" = Select the R5 clock for the APB interface of TTC2 - PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL 0 - - 00" = Select the APB switch clock for the APB interface of TTC3'01" = Select the PLL ref clock for the APB interface of TTC3' - 0" = Select the R5 clock for the APB interface of TTC3 - PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL 0 - - TTC APB clock select - (OFFSET, MASK, VALUE) (0XFF180380, 0x000000FFU ,0x00000000U) - RegMask = (IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_MASK | IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_MASK | IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_MASK | IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_IOU_TTC_APB_CLK_OFFSET ,0x000000FFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : WDT_CLK_SEL @ 0XFD610100

- - System watchdog timer clock source selection: 0: Internal APB clock 1: External (PL clock via EMIO or Pinout clock via MIO) - PSU_FPD_SLCR_WDT_CLK_SEL_SELECT 0 - - SWDT clock source select - (OFFSET, MASK, VALUE) (0XFD610100, 0x00000001U ,0x00000000U) - RegMask = (FPD_SLCR_WDT_CLK_SEL_SELECT_MASK | 0 ); - - RegVal = ((0x00000000U << FPD_SLCR_WDT_CLK_SEL_SELECT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (FPD_SLCR_WDT_CLK_SEL_OFFSET ,0x00000001U ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : WDT_CLK_SEL @ 0XFF180300

- - System watchdog timer clock source selection: 0: internal clock APB clock 1: external clock from PL via EMIO, or from pinout - ia MIO - PSU_IOU_SLCR_WDT_CLK_SEL_SELECT 0 - - SWDT clock source select - (OFFSET, MASK, VALUE) (0XFF180300, 0x00000001U ,0x00000000U) - RegMask = (IOU_SLCR_WDT_CLK_SEL_SELECT_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_WDT_CLK_SEL_SELECT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_WDT_CLK_SEL_OFFSET ,0x00000001U ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : CSUPMU_WDT_CLK_SEL @ 0XFF410050

- - System watchdog timer clock source selection: 0: internal clock APB clock 1: external clock pss_ref_clk - PSU_LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT 0 - - SWDT clock source select - (OFFSET, MASK, VALUE) (0XFF410050, 0x00000001U ,0x00000000U) - RegMask = (LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_MASK | 0 ); - - RegVal = ((0x00000000U << LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (LPD_SLCR_CSUPMU_WDT_CLK_SEL_OFFSET ,0x00000001U ,0x00000000U); - /*############################################################################################################################ */ - - - return 1; + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_CAN1_REF_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_CAN1_REF_CTRL_DIVISOR1 0x1 + + * 6 bit divider + * PSU_CRL_APB_CAN1_REF_CTRL_DIVISOR0 0xf + + * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_CAN1_REF_CTRL_SRCSEL 0x0 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E0088, 0x013F3F07U ,0x01010F00U) + */ + PSU_Mask_Write(CRL_APB_CAN1_REF_CTRL_OFFSET, + 0x013F3F07U, 0x01010F00U); +/*##################################################################### */ + + /* + * Register : CPU_R5_CTRL @ 0XFF5E0090 + + * Turing this off will shut down the OCM, some parts of the APM, and preve + * nt transactions going from the FPD to the LPD and could lead to system h + * ang + * PSU_CRL_APB_CPU_R5_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_CPU_R5_CTRL_DIVISOR0 0x3 + + * 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_CPU_R5_CTRL_SRCSEL 0x2 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E0090, 0x01003F07U ,0x01000302U) + */ + PSU_Mask_Write(CRL_APB_CPU_R5_CTRL_OFFSET, 0x01003F07U, 0x01000302U); +/*##################################################################### */ + + /* + * Register : IOU_SWITCH_CTRL @ 0XFF5E009C + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_IOU_SWITCH_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_IOU_SWITCH_CTRL_DIVISOR0 0x6 + + * 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_IOU_SWITCH_CTRL_SRCSEL 0x2 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E009C, 0x01003F07U ,0x01000602U) + */ + PSU_Mask_Write(CRL_APB_IOU_SWITCH_CTRL_OFFSET, + 0x01003F07U, 0x01000602U); +/*##################################################################### */ + + /* + * Register : PCAP_CTRL @ 0XFF5E00A4 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_PCAP_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_PCAP_CTRL_DIVISOR0 0x8 + + * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_PCAP_CTRL_SRCSEL 0x0 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E00A4, 0x01003F07U ,0x01000800U) + */ + PSU_Mask_Write(CRL_APB_PCAP_CTRL_OFFSET, 0x01003F07U, 0x01000800U); +/*##################################################################### */ + + /* + * Register : LPD_SWITCH_CTRL @ 0XFF5E00A8 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_LPD_SWITCH_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_LPD_SWITCH_CTRL_DIVISOR0 0x3 + + * 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_LPD_SWITCH_CTRL_SRCSEL 0x2 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E00A8, 0x01003F07U ,0x01000302U) + */ + PSU_Mask_Write(CRL_APB_LPD_SWITCH_CTRL_OFFSET, + 0x01003F07U, 0x01000302U); +/*##################################################################### */ + + /* + * Register : LPD_LSBUS_CTRL @ 0XFF5E00AC + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_LPD_LSBUS_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_LPD_LSBUS_CTRL_DIVISOR0 0xf + + * 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_LPD_LSBUS_CTRL_SRCSEL 0x2 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E00AC, 0x01003F07U ,0x01000F02U) + */ + PSU_Mask_Write(CRL_APB_LPD_LSBUS_CTRL_OFFSET, + 0x01003F07U, 0x01000F02U); +/*##################################################################### */ + + /* + * Register : DBG_LPD_CTRL @ 0XFF5E00B0 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_DBG_LPD_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_DBG_LPD_CTRL_DIVISOR0 0x6 + + * 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_DBG_LPD_CTRL_SRCSEL 0x2 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E00B0, 0x01003F07U ,0x01000602U) + */ + PSU_Mask_Write(CRL_APB_DBG_LPD_CTRL_OFFSET, + 0x01003F07U, 0x01000602U); +/*##################################################################### */ + + /* + * Register : ADMA_REF_CTRL @ 0XFF5E00B8 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_ADMA_REF_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_ADMA_REF_CTRL_DIVISOR0 0x3 + + * 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_ADMA_REF_CTRL_SRCSEL 0x2 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E00B8, 0x01003F07U ,0x01000302U) + */ + PSU_Mask_Write(CRL_APB_ADMA_REF_CTRL_OFFSET, + 0x01003F07U, 0x01000302U); +/*##################################################################### */ + + /* + * Register : PL0_REF_CTRL @ 0XFF5E00C0 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_PL0_REF_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRL_APB_PL0_REF_CTRL_DIVISOR1 0x1 + + * 6 bit divider + * PSU_CRL_APB_PL0_REF_CTRL_DIVISOR0 0xf + + * 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_PL0_REF_CTRL_SRCSEL 0x0 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E00C0, 0x013F3F07U ,0x01010F00U) + */ + PSU_Mask_Write(CRL_APB_PL0_REF_CTRL_OFFSET, + 0x013F3F07U, 0x01010F00U); +/*##################################################################### */ + + /* + * Register : AMS_REF_CTRL @ 0XFF5E0108 + + * 6 bit divider + * PSU_CRL_APB_AMS_REF_CTRL_DIVISOR1 0x1 + + * 6 bit divider + * PSU_CRL_APB_AMS_REF_CTRL_DIVISOR0 0x1e + + * 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRL_APB_AMS_REF_CTRL_SRCSEL 0x2 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_AMS_REF_CTRL_CLKACT 0x1 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E0108, 0x013F3F07U ,0x01011E02U) + */ + PSU_Mask_Write(CRL_APB_AMS_REF_CTRL_OFFSET, + 0x013F3F07U, 0x01011E02U); +/*##################################################################### */ + + /* + * Register : DLL_REF_CTRL @ 0XFF5E0104 + + * 000 = IOPLL; 001 = RPLL; (This signal may only be toggled after 4 cycles + * of the old clock and 4 cycles of the new clock. This is not usually an + * issue, but designers must be aware.) + * PSU_CRL_APB_DLL_REF_CTRL_SRCSEL 0 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E0104, 0x00000007U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_DLL_REF_CTRL_OFFSET, + 0x00000007U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : TIMESTAMP_REF_CTRL @ 0XFF5E0128 + + * 6 bit divider + * PSU_CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0 0xf + + * 1XX = pss_ref_clk; 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may + * only be toggled after 4 cycles of the old clock and 4 cycles of the new + * clock. This is not usually an issue, but designers must be aware.) + * PSU_CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL 0x0 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT 0x1 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFF5E0128, 0x01003F07U ,0x01000F00U) + */ + PSU_Mask_Write(CRL_APB_TIMESTAMP_REF_CTRL_OFFSET, + 0x01003F07U, 0x01000F00U); +/*##################################################################### */ + + /* + * Register : SATA_REF_CTRL @ 0XFD1A00A0 + + * 000 = IOPLL_TO_FPD; 010 = APLL; 011 = DPLL; (This signal may only be tog + * gled after 4 cycles of the old clock and 4 cycles of the new clock. This + * is not usually an issue, but designers must be aware.) + * PSU_CRF_APB_SATA_REF_CTRL_SRCSEL 0x0 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRF_APB_SATA_REF_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRF_APB_SATA_REF_CTRL_DIVISOR0 0x2 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFD1A00A0, 0x01003F07U ,0x01000200U) + */ + PSU_Mask_Write(CRF_APB_SATA_REF_CTRL_OFFSET, + 0x01003F07U, 0x01000200U); +/*##################################################################### */ + + /* + * Register : PCIE_REF_CTRL @ 0XFD1A00B4 + + * 000 = IOPLL_TO_FPD; 010 = RPLL_TO_FPD; 011 = DPLL; (This signal may only + * be toggled after 4 cycles of the old clock and 4 cycles of the new cloc + * k. This is not usually an issue, but designers must be aware.) + * PSU_CRF_APB_PCIE_REF_CTRL_SRCSEL 0x0 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRF_APB_PCIE_REF_CTRL_CLKACT 0x1 + + * 6 bit divider + * PSU_CRF_APB_PCIE_REF_CTRL_DIVISOR0 0x2 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFD1A00B4, 0x01003F07U ,0x01000200U) + */ + PSU_Mask_Write(CRF_APB_PCIE_REF_CTRL_OFFSET, + 0x01003F07U, 0x01000200U); +/*##################################################################### */ + + /* + * Register : DP_VIDEO_REF_CTRL @ 0XFD1A0070 + + * 6 bit divider + * PSU_CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1 0x1 + + * 6 bit divider + * PSU_CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0 0x5 + + * 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (T + * his signal may only be toggled after 4 cycles of the old clock and 4 cyc + * les of the new clock. This is not usually an issue, but designers must b + * e aware.) + * PSU_CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL 0x0 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRF_APB_DP_VIDEO_REF_CTRL_CLKACT 0x1 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFD1A0070, 0x013F3F07U ,0x01010500U) + */ + PSU_Mask_Write(CRF_APB_DP_VIDEO_REF_CTRL_OFFSET, + 0x013F3F07U, 0x01010500U); +/*##################################################################### */ + + /* + * Register : DP_AUDIO_REF_CTRL @ 0XFD1A0074 + + * 6 bit divider + * PSU_CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1 0x1 + + * 6 bit divider + * PSU_CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0 0xf + + * 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (T + * his signal may only be toggled after 4 cycles of the old clock and 4 cyc + * les of the new clock. This is not usually an issue, but designers must b + * e aware.) + * PSU_CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL 0x3 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRF_APB_DP_AUDIO_REF_CTRL_CLKACT 0x1 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFD1A0074, 0x013F3F07U ,0x01010F03U) + */ + PSU_Mask_Write(CRF_APB_DP_AUDIO_REF_CTRL_OFFSET, + 0x013F3F07U, 0x01010F03U); +/*##################################################################### */ + + /* + * Register : DP_STC_REF_CTRL @ 0XFD1A007C + + * 6 bit divider + * PSU_CRF_APB_DP_STC_REF_CTRL_DIVISOR1 0x1 + + * 6 bit divider + * PSU_CRF_APB_DP_STC_REF_CTRL_DIVISOR0 0xe + + * 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD; (This signal may only be togg + * led after 4 cycles of the old clock and 4 cycles of the new clock. This + * is not usually an issue, but designers must be aware.) + * PSU_CRF_APB_DP_STC_REF_CTRL_SRCSEL 0x3 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRF_APB_DP_STC_REF_CTRL_CLKACT 0x1 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFD1A007C, 0x013F3F07U ,0x01010E03U) + */ + PSU_Mask_Write(CRF_APB_DP_STC_REF_CTRL_OFFSET, + 0x013F3F07U, 0x01010E03U); +/*##################################################################### */ + + /* + * Register : ACPU_CTRL @ 0XFD1A0060 + + * 6 bit divider + * PSU_CRF_APB_ACPU_CTRL_DIVISOR0 0x1 + + * 000 = APLL; 010 = DPLL; 011 = VPLL; (This signal may only be toggled aft + * er 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRF_APB_ACPU_CTRL_SRCSEL 0x0 + + * Clock active signal. Switch to 0 to disable the clock. For the half spee + * d APU Clock + * PSU_CRF_APB_ACPU_CTRL_CLKACT_HALF 0x1 + + * Clock active signal. Switch to 0 to disable the clock. For the full spee + * d ACPUX Clock. This will shut off the high speed clock to the entire APU + * PSU_CRF_APB_ACPU_CTRL_CLKACT_FULL 0x1 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFD1A0060, 0x03003F07U ,0x03000100U) + */ + PSU_Mask_Write(CRF_APB_ACPU_CTRL_OFFSET, 0x03003F07U, 0x03000100U); +/*##################################################################### */ + + /* + * Register : DBG_FPD_CTRL @ 0XFD1A0068 + + * 6 bit divider + * PSU_CRF_APB_DBG_FPD_CTRL_DIVISOR0 0x2 + + * 000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be tog + * gled after 4 cycles of the old clock and 4 cycles of the new clock. This + * is not usually an issue, but designers must be aware.) + * PSU_CRF_APB_DBG_FPD_CTRL_SRCSEL 0x0 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRF_APB_DBG_FPD_CTRL_CLKACT 0x1 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFD1A0068, 0x01003F07U ,0x01000200U) + */ + PSU_Mask_Write(CRF_APB_DBG_FPD_CTRL_OFFSET, + 0x01003F07U, 0x01000200U); +/*##################################################################### */ + + /* + * Register : DDR_CTRL @ 0XFD1A0080 + + * 6 bit divider + * PSU_CRF_APB_DDR_CTRL_DIVISOR0 0x2 + + * 000 = DPLL; 001 = VPLL; (This signal may only be toggled after 4 cycles + * of the old clock and 4 cycles of the new clock. This is not usually an i + * ssue, but designers must be aware.) + * PSU_CRF_APB_DDR_CTRL_SRCSEL 0x0 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFD1A0080, 0x00003F07U ,0x00000200U) + */ + PSU_Mask_Write(CRF_APB_DDR_CTRL_OFFSET, 0x00003F07U, 0x00000200U); +/*##################################################################### */ + + /* + * Register : GPU_REF_CTRL @ 0XFD1A0084 + + * 6 bit divider + * PSU_CRF_APB_GPU_REF_CTRL_DIVISOR0 0x1 + + * 000 = IOPLL_TO_FPD; 010 = VPLL; 011 = DPLL; (This signal may only be tog + * gled after 4 cycles of the old clock and 4 cycles of the new clock. This + * is not usually an issue, but designers must be aware.) + * PSU_CRF_APB_GPU_REF_CTRL_SRCSEL 0x0 + + * Clock active signal. Switch to 0 to disable the clock, which will stop c + * lock for GPU (and both Pixel Processors). + * PSU_CRF_APB_GPU_REF_CTRL_CLKACT 0x1 + + * Clock active signal for Pixel Processor. Switch to 0 to disable the cloc + * k only to this Pixel Processor + * PSU_CRF_APB_GPU_REF_CTRL_PP0_CLKACT 0x1 + + * Clock active signal for Pixel Processor. Switch to 0 to disable the cloc + * k only to this Pixel Processor + * PSU_CRF_APB_GPU_REF_CTRL_PP1_CLKACT 0x1 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFD1A0084, 0x07003F07U ,0x07000100U) + */ + PSU_Mask_Write(CRF_APB_GPU_REF_CTRL_OFFSET, + 0x07003F07U, 0x07000100U); +/*##################################################################### */ + + /* + * Register : GDMA_REF_CTRL @ 0XFD1A00B8 + + * 6 bit divider + * PSU_CRF_APB_GDMA_REF_CTRL_DIVISOR0 0x2 + + * 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled aft + * er 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRF_APB_GDMA_REF_CTRL_SRCSEL 0x0 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRF_APB_GDMA_REF_CTRL_CLKACT 0x1 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFD1A00B8, 0x01003F07U ,0x01000200U) + */ + PSU_Mask_Write(CRF_APB_GDMA_REF_CTRL_OFFSET, + 0x01003F07U, 0x01000200U); +/*##################################################################### */ + + /* + * Register : DPDMA_REF_CTRL @ 0XFD1A00BC + + * 6 bit divider + * PSU_CRF_APB_DPDMA_REF_CTRL_DIVISOR0 0x2 + + * 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled aft + * er 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRF_APB_DPDMA_REF_CTRL_SRCSEL 0x0 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRF_APB_DPDMA_REF_CTRL_CLKACT 0x1 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFD1A00BC, 0x01003F07U ,0x01000200U) + */ + PSU_Mask_Write(CRF_APB_DPDMA_REF_CTRL_OFFSET, + 0x01003F07U, 0x01000200U); +/*##################################################################### */ + + /* + * Register : TOPSW_MAIN_CTRL @ 0XFD1A00C0 + + * 6 bit divider + * PSU_CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0 0x2 + + * 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled aft + * er 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) + * PSU_CRF_APB_TOPSW_MAIN_CTRL_SRCSEL 0x3 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRF_APB_TOPSW_MAIN_CTRL_CLKACT 0x1 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFD1A00C0, 0x01003F07U ,0x01000203U) + */ + PSU_Mask_Write(CRF_APB_TOPSW_MAIN_CTRL_OFFSET, + 0x01003F07U, 0x01000203U); +/*##################################################################### */ + + /* + * Register : TOPSW_LSBUS_CTRL @ 0XFD1A00C4 + + * 6 bit divider + * PSU_CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0 0x5 + + * 000 = APLL; 010 = IOPLL_TO_FPD; 011 = DPLL; (This signal may only be tog + * gled after 4 cycles of the old clock and 4 cycles of the new clock. This + * is not usually an issue, but designers must be aware.) + * PSU_CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL 0x2 + + * Clock active signal. Switch to 0 to disable the clock + * PSU_CRF_APB_TOPSW_LSBUS_CTRL_CLKACT 0x1 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFD1A00C4, 0x01003F07U ,0x01000502U) + */ + PSU_Mask_Write(CRF_APB_TOPSW_LSBUS_CTRL_OFFSET, + 0x01003F07U, 0x01000502U); +/*##################################################################### */ + + /* + * Register : DBG_TSTMP_CTRL @ 0XFD1A00F8 + + * 6 bit divider + * PSU_CRF_APB_DBG_TSTMP_CTRL_DIVISOR0 0x2 + + * 000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be tog + * gled after 4 cycles of the old clock and 4 cycles of the new clock. This + * is not usually an issue, but designers must be aware.) + * PSU_CRF_APB_DBG_TSTMP_CTRL_SRCSEL 0x0 + + * This register controls this reference clock + * (OFFSET, MASK, VALUE) (0XFD1A00F8, 0x00003F07U ,0x00000200U) + */ + PSU_Mask_Write(CRF_APB_DBG_TSTMP_CTRL_OFFSET, + 0x00003F07U, 0x00000200U); +/*##################################################################### */ + + /* + * Register : IOU_TTC_APB_CLK @ 0XFF180380 + + * 00" = Select the APB switch clock for the APB interface of TTC0'01" = Se + * lect the PLL ref clock for the APB interface of TTC0'10" = Select the R5 + * clock for the APB interface of TTC0 + * PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL 0 + + * 00" = Select the APB switch clock for the APB interface of TTC1'01" = Se + * lect the PLL ref clock for the APB interface of TTC1'10" = Select the R5 + * clock for the APB interface of TTC1 + * PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL 0 + + * 00" = Select the APB switch clock for the APB interface of TTC2'01" = Se + * lect the PLL ref clock for the APB interface of TTC2'10" = Select the R5 + * clock for the APB interface of TTC2 + * PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL 0 + + * 00" = Select the APB switch clock for the APB interface of TTC3'01" = Se + * lect the PLL ref clock for the APB interface of TTC3'10" = Select the R5 + * clock for the APB interface of TTC3 + * PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL 0 + + * TTC APB clock select + * (OFFSET, MASK, VALUE) (0XFF180380, 0x000000FFU ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_IOU_TTC_APB_CLK_OFFSET, + 0x000000FFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : WDT_CLK_SEL @ 0XFD610100 + + * System watchdog timer clock source selection: 0: Internal APB clock 1: E + * xternal (PL clock via EMIO or Pinout clock via MIO) + * PSU_FPD_SLCR_WDT_CLK_SEL_SELECT 0 + + * SWDT clock source select + * (OFFSET, MASK, VALUE) (0XFD610100, 0x00000001U ,0x00000000U) + */ + PSU_Mask_Write(FPD_SLCR_WDT_CLK_SEL_OFFSET, + 0x00000001U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : WDT_CLK_SEL @ 0XFF180300 + + * System watchdog timer clock source selection: 0: internal clock APB cloc + * k 1: external clock from PL via EMIO, or from pinout via MIO + * PSU_IOU_SLCR_WDT_CLK_SEL_SELECT 0 + + * SWDT clock source select + * (OFFSET, MASK, VALUE) (0XFF180300, 0x00000001U ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_WDT_CLK_SEL_OFFSET, + 0x00000001U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : CSUPMU_WDT_CLK_SEL @ 0XFF410050 + + * System watchdog timer clock source selection: 0: internal clock APB cloc + * k 1: external clock pss_ref_clk + * PSU_LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT 0 + + * SWDT clock source select + * (OFFSET, MASK, VALUE) (0XFF410050, 0x00000001U ,0x00000000U) + */ + PSU_Mask_Write(LPD_SLCR_CSUPMU_WDT_CLK_SEL_OFFSET, + 0x00000001U, 0x00000000U); +/*##################################################################### */ + + + return 1; } -unsigned long psu_ddr_init_data() { - // : DDR INITIALIZATION - // : DDR CONTROLLER RESET - /*Register : RST_DDR_SS @ 0XFD1A0108

- - DDR block level reset inside of the DDR Sub System - PSU_CRF_APB_RST_DDR_SS_DDR_RESET 0X1 - - DDR sub system block level reset - (OFFSET, MASK, VALUE) (0XFD1A0108, 0x00000008U ,0x00000008U) - RegMask = (CRF_APB_RST_DDR_SS_DDR_RESET_MASK | 0 ); - - RegVal = ((0x00000001U << CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_RST_DDR_SS_OFFSET ,0x00000008U ,0x00000008U); - /*############################################################################################################################ */ - - /*Register : MSTR @ 0XFD070000

- - Indicates the configuration of the device used in the system. - 00 - x4 device - 01 - x8 device - 10 - x16 device - 11 - x32 - evice - PSU_DDRC_MSTR_DEVICE_CONFIG 0x1 - - Choose which registers are used. - 0 - Original registers - 1 - Shadow registers - PSU_DDRC_MSTR_FREQUENCY_MODE 0x0 - - Only present for multi-rank configurations. Each bit represents one rank. For two-rank configurations, only bits[25:24] are p - esent. - 1 - populated - 0 - unpopulated LSB is the lowest rank number. For 2 ranks following combinations are legal: - 01 - - ne rank - 11 - Two ranks - Others - Reserved. For 4 ranks following combinations are legal: - 0001 - One rank - 0011 - Two ra - ks - 1111 - Four ranks - PSU_DDRC_MSTR_ACTIVE_RANKS 0x1 - - SDRAM burst length used: - 0001 - Burst length of 2 (only supported for mDDR) - 0010 - Burst length of 4 - 0100 - Burst lengt - of 8 - 1000 - Burst length of 16 (only supported for mDDR, LPDDR2, and LPDDR4) All other values are reserved. This controls - he burst size used to access the SDRAM. This must match the burst length mode register setting in the SDRAM. (For BC4/8 on-th - -fly mode of DDR3 and DDR4, set this field to 0x0100) Burst length of 2 is not supported with AXI ports when MEMC_BURST_LENGT - is 8. Burst length of 2 is only supported with MEMC_FREQ_RATIO = 1 - PSU_DDRC_MSTR_BURST_RDWR 0x4 - - Set to 1 when the uMCTL2 and DRAM has to be put in DLL-off mode for low frequency operation. Set to 0 to put uMCTL2 and DRAM - n DLL-on mode for normal frequency operation. If DDR4 CRC/parity retry is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), d - l_off_mode is not supported, and this bit must be set to '0'. - PSU_DDRC_MSTR_DLL_OFF_MODE 0x0 - - Selects proportion of DQ bus width that is used by the SDRAM - 00 - Full DQ bus width to SDRAM - 01 - Half DQ bus width to SD - AM - 10 - Quarter DQ bus width to SDRAM - 11 - Reserved. Note that half bus width mode is only supported when the SDRAM bus w - dth is a multiple of 16, and quarter bus width mode is only supported when the SDRAM bus width is a multiple of 32 and the co - figuration parameter MEMC_QBUS_SUPPORT is set. Bus width refers to DQ bus width (excluding any ECC width). - PSU_DDRC_MSTR_DATA_BUS_WIDTH 0x0 - - 1 indicates put the DRAM in geardown mode (2N) and 0 indicates put the DRAM in normal mode (1N). This register can be changed - only when the Controller is in self-refresh mode. This signal must be set the same value as MR3 bit A3. Note: Geardown mode - s not supported if the configuration parameter MEMC_CMD_RTN2IDLE is set - PSU_DDRC_MSTR_GEARDOWN_MODE 0x0 - - If 1, then uMCTL2 uses 2T timing. Otherwise, uses 1T timing. In 2T timing, all command signals (except chip select) are held - or 2 clocks on the SDRAM bus. Chip select is asserted on the second cycle of the command Note: 2T timing is not supported in - PDDR2/LPDDR3/LPDDR4 mode Note: 2T timing is not supported if the configuration parameter MEMC_CMD_RTN2IDLE is set Note: 2T ti - ing is not supported in DDR4 geardown mode. - PSU_DDRC_MSTR_EN_2T_TIMING_MODE 0x0 - - When set, enable burst-chop in DDR3/DDR4. Burst Chop for Reads is exercised only in HIF configurations (UMCTL2_INCL_ARB not s - t) and if in full bus width mode (MSTR.data_bus_width = 00). Burst Chop for Writes is exercised only if Partial Writes enable - (UMCTL2_PARTIAL_WR=1) and if CRC is disabled (CRCPARCTL1.crc_enable = 0). If DDR4 CRC/parity retry is enabled (CRCPARCTL1.cr - _parity_retry_enable = 1), burst chop is not supported, and this bit must be set to '0' - PSU_DDRC_MSTR_BURSTCHOP 0x0 - - Select LPDDR4 SDRAM - 1 - LPDDR4 SDRAM device in use. - 0 - non-LPDDR4 device in use Present only in designs configured to su - port LPDDR4. - PSU_DDRC_MSTR_LPDDR4 0x0 - - Select DDR4 SDRAM - 1 - DDR4 SDRAM device in use. - 0 - non-DDR4 device in use Present only in designs configured to support - DR4. - PSU_DDRC_MSTR_DDR4 0x1 - - Select LPDDR3 SDRAM - 1 - LPDDR3 SDRAM device in use. - 0 - non-LPDDR3 device in use Present only in designs configured to su - port LPDDR3. - PSU_DDRC_MSTR_LPDDR3 0x0 - - Select LPDDR2 SDRAM - 1 - LPDDR2 SDRAM device in use. - 0 - non-LPDDR2 device in use Present only in designs configured to su - port LPDDR2. - PSU_DDRC_MSTR_LPDDR2 0x0 - - Select DDR3 SDRAM - 1 - DDR3 SDRAM device in use - 0 - non-DDR3 SDRAM device in use Only present in designs that support DDR3 - - PSU_DDRC_MSTR_DDR3 0x0 - - Master Register - (OFFSET, MASK, VALUE) (0XFD070000, 0xE30FBE3DU ,0x41040010U) - RegMask = (DDRC_MSTR_DEVICE_CONFIG_MASK | DDRC_MSTR_FREQUENCY_MODE_MASK | DDRC_MSTR_ACTIVE_RANKS_MASK | DDRC_MSTR_BURST_RDWR_MASK | DDRC_MSTR_DLL_OFF_MODE_MASK | DDRC_MSTR_DATA_BUS_WIDTH_MASK | DDRC_MSTR_GEARDOWN_MODE_MASK | DDRC_MSTR_EN_2T_TIMING_MODE_MASK | DDRC_MSTR_BURSTCHOP_MASK | DDRC_MSTR_LPDDR4_MASK | DDRC_MSTR_DDR4_MASK | DDRC_MSTR_LPDDR3_MASK | DDRC_MSTR_LPDDR2_MASK | DDRC_MSTR_DDR3_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_MSTR_DEVICE_CONFIG_SHIFT - | 0x00000000U << DDRC_MSTR_FREQUENCY_MODE_SHIFT - | 0x00000001U << DDRC_MSTR_ACTIVE_RANKS_SHIFT - | 0x00000004U << DDRC_MSTR_BURST_RDWR_SHIFT - | 0x00000000U << DDRC_MSTR_DLL_OFF_MODE_SHIFT - | 0x00000000U << DDRC_MSTR_DATA_BUS_WIDTH_SHIFT - | 0x00000000U << DDRC_MSTR_GEARDOWN_MODE_SHIFT - | 0x00000000U << DDRC_MSTR_EN_2T_TIMING_MODE_SHIFT - | 0x00000000U << DDRC_MSTR_BURSTCHOP_SHIFT - | 0x00000000U << DDRC_MSTR_LPDDR4_SHIFT - | 0x00000001U << DDRC_MSTR_DDR4_SHIFT - | 0x00000000U << DDRC_MSTR_LPDDR3_SHIFT - | 0x00000000U << DDRC_MSTR_LPDDR2_SHIFT - | 0x00000000U << DDRC_MSTR_DDR3_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_MSTR_OFFSET ,0xE30FBE3DU ,0x41040010U); - /*############################################################################################################################ */ - - /*Register : MRCTRL0 @ 0XFD070010

- - Setting this register bit to 1 triggers a mode register read or write operation. When the MR operation is complete, the uMCTL - automatically clears this bit. The other register fields of this register must be written in a separate APB transaction, bef - re setting this mr_wr bit. It is recommended NOT to set this signal if in Init, Deep power-down or MPSM operating modes. - PSU_DDRC_MRCTRL0_MR_WR 0x0 - - Address of the mode register that is to be written to. - 0000 - MR0 - 0001 - MR1 - 0010 - MR2 - 0011 - MR3 - 0100 - MR4 - 010 - - MR5 - 0110 - MR6 - 0111 - MR7 Don't Care for LPDDR2/LPDDR3/LPDDR4 (see MRCTRL1.mr_data for mode register addressing in LPD - R2/LPDDR3/LPDDR4) This signal is also used for writing to control words of RDIMMs. In that case, it corresponds to the bank a - dress bits sent to the RDIMM In case of DDR4, the bit[3:2] corresponds to the bank group bits. Therefore, the bit[3] as well - s the bit[2:0] must be set to an appropriate value which is considered both the Address Mirroring of UDIMMs/RDIMMs and the Ou - put Inversion of RDIMMs. - PSU_DDRC_MRCTRL0_MR_ADDR 0x0 - - Controls which rank is accessed by MRCTRL0.mr_wr. Normally, it is desired to access all ranks, so all bits should be set to 1 - However, for multi-rank UDIMMs/RDIMMs which implement address mirroring, it may be necessary to access ranks individually. E - amples (assume uMCTL2 is configured for 4 ranks): - 0x1 - select rank 0 only - 0x2 - select rank 1 only - 0x5 - select ranks - and 2 - 0xA - select ranks 1 and 3 - 0xF - select ranks 0, 1, 2 and 3 - PSU_DDRC_MRCTRL0_MR_RANK 0x3 - - Indicates whether Software intervention is allowed via MRCTRL0/MRCTRL1 before automatic SDRAM initialization routine or not. - or DDR4, this bit can be used to initialize the DDR4 RCD (MR7) before automatic SDRAM initialization. For LPDDR4, this bit ca - be used to program additional mode registers before automatic SDRAM initialization if necessary. Note: This must be cleared - o 0 after completing Software operation. Otherwise, SDRAM initialization routine will not re-start. - 0 - Software interventi - n is not allowed - 1 - Software intervention is allowed - PSU_DDRC_MRCTRL0_SW_INIT_INT 0x0 - - Indicates whether the mode register operation is MRS in PDA mode or not - 0 - MRS - 1 - MRS in Per DRAM Addressability mode - PSU_DDRC_MRCTRL0_PDA_EN 0x0 - - Indicates whether the mode register operation is MRS or WR/RD for MPR (only supported for DDR4) - 0 - MRS - 1 - WR/RD for MPR - PSU_DDRC_MRCTRL0_MPR_EN 0x0 - - Indicates whether the mode register operation is read or write. Only used for LPDDR2/LPDDR3/LPDDR4/DDR4. - 0 - Write - 1 - Re - d - PSU_DDRC_MRCTRL0_MR_TYPE 0x0 - - Mode Register Read/Write Control Register 0. Note: Do not enable more than one of the following fields simultaneously: - sw_i - it_int - pda_en - mpr_en - (OFFSET, MASK, VALUE) (0XFD070010, 0x8000F03FU ,0x00000030U) - RegMask = (DDRC_MRCTRL0_MR_WR_MASK | DDRC_MRCTRL0_MR_ADDR_MASK | DDRC_MRCTRL0_MR_RANK_MASK | DDRC_MRCTRL0_SW_INIT_INT_MASK | DDRC_MRCTRL0_PDA_EN_MASK | DDRC_MRCTRL0_MPR_EN_MASK | DDRC_MRCTRL0_MR_TYPE_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_MRCTRL0_MR_WR_SHIFT - | 0x00000000U << DDRC_MRCTRL0_MR_ADDR_SHIFT - | 0x00000003U << DDRC_MRCTRL0_MR_RANK_SHIFT - | 0x00000000U << DDRC_MRCTRL0_SW_INIT_INT_SHIFT - | 0x00000000U << DDRC_MRCTRL0_PDA_EN_SHIFT - | 0x00000000U << DDRC_MRCTRL0_MPR_EN_SHIFT - | 0x00000000U << DDRC_MRCTRL0_MR_TYPE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_MRCTRL0_OFFSET ,0x8000F03FU ,0x00000030U); - /*############################################################################################################################ */ - - /*Register : DERATEEN @ 0XFD070020

- - Derate value of tRC for LPDDR4 - 0 - Derating uses +1. - 1 - Derating uses +2. - 2 - Derating uses +3. - 3 - Derating uses +4 - Present only in designs configured to support LPDDR4. The required number of cycles for derating can be determined by dividi - g 3.75ns by the core_ddrc_core_clk period, and rounding up the next integer. - PSU_DDRC_DERATEEN_RC_DERATE_VALUE 0x3 - - Derate byte Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4 Indicates which byte of the MRR data is used f - r derating. The maximum valid value depends on MEMC_DRAM_TOTAL_DATA_WIDTH. - PSU_DDRC_DERATEEN_DERATE_BYTE 0x0 - - Derate value - 0 - Derating uses +1. - 1 - Derating uses +2. Present only in designs configured to support LPDDR2/LPDDR3/LPDD - 4 Set to 0 for all LPDDR2 speed grades as derating value of +1.875 ns is less than a core_ddrc_core_clk period. Can be 0 or 1 - for LPDDR3/LPDDR4, depending if +1.875 ns is less than a core_ddrc_core_clk period or not. - PSU_DDRC_DERATEEN_DERATE_VALUE 0x0 - - Enables derating - 0 - Timing parameter derating is disabled - 1 - Timing parameter derating is enabled using MR4 read value. - Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4 This field must be set to '0' for non-LPDDR2/LPDDR3/LPDDR4 - mode. - PSU_DDRC_DERATEEN_DERATE_ENABLE 0x0 - - Temperature Derate Enable Register - (OFFSET, MASK, VALUE) (0XFD070020, 0x000003F3U ,0x00000300U) - RegMask = (DDRC_DERATEEN_RC_DERATE_VALUE_MASK | DDRC_DERATEEN_DERATE_BYTE_MASK | DDRC_DERATEEN_DERATE_VALUE_MASK | DDRC_DERATEEN_DERATE_ENABLE_MASK | 0 ); - - RegVal = ((0x00000003U << DDRC_DERATEEN_RC_DERATE_VALUE_SHIFT - | 0x00000000U << DDRC_DERATEEN_DERATE_BYTE_SHIFT - | 0x00000000U << DDRC_DERATEEN_DERATE_VALUE_SHIFT - | 0x00000000U << DDRC_DERATEEN_DERATE_ENABLE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DERATEEN_OFFSET ,0x000003F3U ,0x00000300U); - /*############################################################################################################################ */ - - /*Register : DERATEINT @ 0XFD070024

- - Interval between two MR4 reads, used to derate the timing parameters. Present only in designs configured to support LPDDR2/LP - DR3/LPDDR4. This register must not be set to zero - PSU_DDRC_DERATEINT_MR4_READ_INTERVAL 0x800000 - - Temperature Derate Interval Register - (OFFSET, MASK, VALUE) (0XFD070024, 0xFFFFFFFFU ,0x00800000U) - RegMask = (DDRC_DERATEINT_MR4_READ_INTERVAL_MASK | 0 ); - - RegVal = ((0x00800000U << DDRC_DERATEINT_MR4_READ_INTERVAL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DERATEINT_OFFSET ,0xFFFFFFFFU ,0x00800000U); - /*############################################################################################################################ */ - - /*Register : PWRCTL @ 0XFD070030

- - Self refresh state is an intermediate state to enter to Self refresh power down state or exit Self refresh power down state f - r LPDDR4. This register controls transition from the Self refresh state. - 1 - Prohibit transition from Self refresh state - - - Allow transition from Self refresh state - PSU_DDRC_PWRCTL_STAY_IN_SELFREF 0x0 - - A value of 1 to this register causes system to move to Self Refresh state immediately, as long as it is not in INIT or DPD/MP - M operating_mode. This is referred to as Software Entry/Exit to Self Refresh. - 1 - Software Entry to Self Refresh - 0 - Soft - are Exit from Self Refresh - PSU_DDRC_PWRCTL_SELFREF_SW 0x0 - - When this is 1, the uMCTL2 puts the SDRAM into maximum power saving mode when the transaction store is empty. This register m - st be reset to '0' to bring uMCTL2 out of maximum power saving mode. Present only in designs configured to support DDR4. For - on-DDR4, this register should not be set to 1. Note that MPSM is not supported when using a DWC DDR PHY, if the PHY parameter - DWC_AC_CS_USE is disabled, as the MPSM exit sequence requires the chip-select signal to toggle. FOR PERFORMANCE ONLY. - PSU_DDRC_PWRCTL_MPSM_EN 0x0 - - Enable the assertion of dfi_dram_clk_disable whenever a clock is not required by the SDRAM. If set to 0, dfi_dram_clk_disable - is never asserted. Assertion of dfi_dram_clk_disable is as follows: In DDR2/DDR3, can only be asserted in Self Refresh. In DD - 4, can be asserted in following: - in Self Refresh. - in Maximum Power Saving Mode In mDDR/LPDDR2/LPDDR3, can be asserted in - ollowing: - in Self Refresh - in Power Down - in Deep Power Down - during Normal operation (Clock Stop) In LPDDR4, can be ass - rted in following: - in Self Refresh Power Down - in Power Down - during Normal operation (Clock Stop) - PSU_DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE 0x0 - - When this is 1, uMCTL2 puts the SDRAM into deep power-down mode when the transaction store is empty. This register must be re - et to '0' to bring uMCTL2 out of deep power-down mode. Controller performs automatic SDRAM initialization on deep power-down - xit. Present only in designs configured to support mDDR or LPDDR2 or LPDDR3. For non-mDDR/non-LPDDR2/non-LPDDR3, this registe - should not be set to 1. FOR PERFORMANCE ONLY. - PSU_DDRC_PWRCTL_DEEPPOWERDOWN_EN 0x0 - - If true then the uMCTL2 goes into power-down after a programmable number of cycles 'maximum idle clocks before power down' (P - RTMG.powerdown_to_x32). This register bit may be re-programmed during the course of normal operation. - PSU_DDRC_PWRCTL_POWERDOWN_EN 0x0 - - If true then the uMCTL2 puts the SDRAM into Self Refresh after a programmable number of cycles 'maximum idle clocks before Se - f Refresh (PWRTMG.selfref_to_x32)'. This register bit may be re-programmed during the course of normal operation. - PSU_DDRC_PWRCTL_SELFREF_EN 0x0 - - Low Power Control Register - (OFFSET, MASK, VALUE) (0XFD070030, 0x0000007FU ,0x00000000U) - RegMask = (DDRC_PWRCTL_STAY_IN_SELFREF_MASK | DDRC_PWRCTL_SELFREF_SW_MASK | DDRC_PWRCTL_MPSM_EN_MASK | DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_MASK | DDRC_PWRCTL_DEEPPOWERDOWN_EN_MASK | DDRC_PWRCTL_POWERDOWN_EN_MASK | DDRC_PWRCTL_SELFREF_EN_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_PWRCTL_STAY_IN_SELFREF_SHIFT - | 0x00000000U << DDRC_PWRCTL_SELFREF_SW_SHIFT - | 0x00000000U << DDRC_PWRCTL_MPSM_EN_SHIFT - | 0x00000000U << DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_SHIFT - | 0x00000000U << DDRC_PWRCTL_DEEPPOWERDOWN_EN_SHIFT - | 0x00000000U << DDRC_PWRCTL_POWERDOWN_EN_SHIFT - | 0x00000000U << DDRC_PWRCTL_SELFREF_EN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PWRCTL_OFFSET ,0x0000007FU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : PWRTMG @ 0XFD070034

- - After this many clocks of NOP or deselect the uMCTL2 automatically puts the SDRAM into Self Refresh. This must be enabled in - he PWRCTL.selfref_en. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY. - PSU_DDRC_PWRTMG_SELFREF_TO_X32 0x40 - - Minimum deep power-down time. For mDDR, value from the JEDEC specification is 0 as mDDR exits from deep power-down mode immed - ately after PWRCTL.deeppowerdown_en is de-asserted. For LPDDR2/LPDDR3, value from the JEDEC specification is 500us. Unit: Mul - iples of 4096 clocks. Present only in designs configured to support mDDR, LPDDR2 or LPDDR3. FOR PERFORMANCE ONLY. - PSU_DDRC_PWRTMG_T_DPD_X4096 0x84 - - After this many clocks of NOP or deselect the uMCTL2 automatically puts the SDRAM into power-down. This must be enabled in th - PWRCTL.powerdown_en. Unit: Multiples of 32 clocks FOR PERFORMANCE ONLY. - PSU_DDRC_PWRTMG_POWERDOWN_TO_X32 0x10 - - Low Power Timing Register - (OFFSET, MASK, VALUE) (0XFD070034, 0x00FFFF1FU ,0x00408410U) - RegMask = (DDRC_PWRTMG_SELFREF_TO_X32_MASK | DDRC_PWRTMG_T_DPD_X4096_MASK | DDRC_PWRTMG_POWERDOWN_TO_X32_MASK | 0 ); - - RegVal = ((0x00000040U << DDRC_PWRTMG_SELFREF_TO_X32_SHIFT - | 0x00000084U << DDRC_PWRTMG_T_DPD_X4096_SHIFT - | 0x00000010U << DDRC_PWRTMG_POWERDOWN_TO_X32_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PWRTMG_OFFSET ,0x00FFFF1FU ,0x00408410U); - /*############################################################################################################################ */ - - /*Register : RFSHCTL0 @ 0XFD070050

- - Threshold value in number of clock cycles before the critical refresh or page timer expires. A critical refresh is to be issu - d before this threshold is reached. It is recommended that this not be changed from the default value, currently shown as 0x2 - It must always be less than internally used t_rfc_nom_x32. Note that, in LPDDR2/LPDDR3/LPDDR4, internally used t_rfc_nom_x32 - may be equal to RFSHTMG.t_rfc_nom_x32>>2 if derating is enabled (DERATEEN.derate_enable=1). Otherwise, internally used t_rfc_ - om_x32 will be equal to RFSHTMG.t_rfc_nom_x32. Unit: Multiples of 32 clocks. - PSU_DDRC_RFSHCTL0_REFRESH_MARGIN 0x2 - - If the refresh timer (tRFCnom, also known as tREFI) has expired at least once, but it has not expired (RFSHCTL0.refresh_burst - 1) times yet, then a speculative refresh may be performed. A speculative refresh is a refresh performed at a time when refres - would be useful, but before it is absolutely required. When the SDRAM bus is idle for a period of time determined by this RF - HCTL0.refresh_to_x32 and the refresh timer has expired at least once since the last refresh, then a speculative refresh is pe - formed. Speculative refreshes continues successively until there are no refreshes pending or until new reads or writes are is - ued to the uMCTL2. FOR PERFORMANCE ONLY. - PSU_DDRC_RFSHCTL0_REFRESH_TO_X32 0x10 - - The programmed value + 1 is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the re - reshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of re - reshes. Therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for - RFSHCTL.refresh_burst slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshe - . - 0 - single refresh - 1 - burst-of-2 refresh - 7 - burst-of-8 refresh For information on burst refresh feature refer to se - tion 3.9 of DDR2 JEDEC specification - JESD79-2F.pdf. For DDR2/3, the refresh is always per-rank and not per-bank. The rank r - fresh can be accumulated over 8*tREFI cycles using the burst refresh feature. In DDR4 mode, according to Fine Granularity fea - ure, 8 refreshes can be postponed in 1X mode, 16 refreshes in 2X mode and 32 refreshes in 4X mode. If using PHY-initiated upd - tes, care must be taken in the setting of RFSHCTL0.refresh_burst, to ensure that tRFCmax is not violated due to a PHY-initiat - d update occurring shortly before a refresh burst was due. In this situation, the refresh burst will be delayed until the PHY - initiated update is complete. - PSU_DDRC_RFSHCTL0_REFRESH_BURST 0x0 - - - 1 - Per bank refresh; - 0 - All bank refresh. Per bank refresh allows traffic to flow to other banks. Per bank refresh is n - t supported by all LPDDR2 devices but should be supported by all LPDDR3/LPDDR4 devices. Present only in designs configured to - support LPDDR2/LPDDR3/LPDDR4 - PSU_DDRC_RFSHCTL0_PER_BANK_REFRESH 0x0 - - Refresh Control Register 0 - (OFFSET, MASK, VALUE) (0XFD070050, 0x00F1F1F4U ,0x00210000U) - RegMask = (DDRC_RFSHCTL0_REFRESH_MARGIN_MASK | DDRC_RFSHCTL0_REFRESH_TO_X32_MASK | DDRC_RFSHCTL0_REFRESH_BURST_MASK | DDRC_RFSHCTL0_PER_BANK_REFRESH_MASK | 0 ); - - RegVal = ((0x00000002U << DDRC_RFSHCTL0_REFRESH_MARGIN_SHIFT - | 0x00000010U << DDRC_RFSHCTL0_REFRESH_TO_X32_SHIFT - | 0x00000000U << DDRC_RFSHCTL0_REFRESH_BURST_SHIFT - | 0x00000000U << DDRC_RFSHCTL0_PER_BANK_REFRESH_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_RFSHCTL0_OFFSET ,0x00F1F1F4U ,0x00210000U); - /*############################################################################################################################ */ - - /*Register : RFSHCTL3 @ 0XFD070060

- - Fine Granularity Refresh Mode - 000 - Fixed 1x (Normal mode) - 001 - Fixed 2x - 010 - Fixed 4x - 101 - Enable on the fly 2x ( - ot supported) - 110 - Enable on the fly 4x (not supported) - Everything else - reserved Note: The on-the-fly modes is not sup - orted in this version of the uMCTL2. Note: This must be set up while the Controller is in reset or while the Controller is in - self-refresh mode. Changing this during normal operation is not allowed. Making this a dynamic register will be supported in - uture version of the uMCTL2. - PSU_DDRC_RFSHCTL3_REFRESH_MODE 0x0 - - Toggle this signal (either from 0 to 1 or from 1 to 0) to indicate that the refresh register(s) have been updated. The value - s automatically updated when exiting reset, so it does not need to be toggled initially. - PSU_DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL 0x0 - - When '1', disable auto-refresh generated by the uMCTL2. When auto-refresh is disabled, the SoC core must generate refreshes u - ing the registers reg_ddrc_rank0_refresh, reg_ddrc_rank1_refresh, reg_ddrc_rank2_refresh and reg_ddrc_rank3_refresh. When dis - auto_refresh transitions from 0 to 1, any pending refreshes are immediately scheduled by the uMCTL2. If DDR4 CRC/parity retry - is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), disable auto-refresh is not supported, and this bit must be set to '0'. - his register field is changeable on the fly. - PSU_DDRC_RFSHCTL3_DIS_AUTO_REFRESH 0x1 - - Refresh Control Register 3 - (OFFSET, MASK, VALUE) (0XFD070060, 0x00000073U ,0x00000001U) - RegMask = (DDRC_RFSHCTL3_REFRESH_MODE_MASK | DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_MASK | DDRC_RFSHCTL3_DIS_AUTO_REFRESH_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_RFSHCTL3_REFRESH_MODE_SHIFT - | 0x00000000U << DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_SHIFT - | 0x00000001U << DDRC_RFSHCTL3_DIS_AUTO_REFRESH_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_RFSHCTL3_OFFSET ,0x00000073U ,0x00000001U); - /*############################################################################################################################ */ - - /*Register : RFSHTMG @ 0XFD070064

- - tREFI: Average time interval between refreshes per rank (Specification: 7.8us for DDR2, DDR3 and DDR4. See JEDEC specificatio - for mDDR, LPDDR2, LPDDR3 and LPDDR4). For LPDDR2/LPDDR3/LPDDR4: - if using all-bank refreshes (RFSHCTL0.per_bank_refresh = 0 - , this register should be set to tREFIab - if using per-bank refreshes (RFSHCTL0.per_bank_refresh = 1), this register should - e set to tREFIpb For configurations with MEMC_FREQ_RATIO=2, program this to (tREFI/2), no rounding up. In DDR4 mode, tREFI va - ue is different depending on the refresh mode. The user should program the appropriate value from the spec based on the value - programmed in the refresh mode register. Note that RFSHTMG.t_rfc_nom_x32 * 32 must be greater than RFSHTMG.t_rfc_min, and RFS - TMG.t_rfc_nom_x32 must be greater than 0x1. Unit: Multiples of 32 clocks. - PSU_DDRC_RFSHTMG_T_RFC_NOM_X32 0x82 - - Used only when LPDDR3 memory type is connected. Should only be changed when uMCTL2 is in reset. Specifies whether to use the - REFBW parameter (required by some LPDDR3 devices which comply with earlier versions of the LPDDR3 JEDEC specification) or not - - 0 - tREFBW parameter not used - 1 - tREFBW parameter used - PSU_DDRC_RFSHTMG_LPDDR3_TREFBW_EN 0x1 - - tRFC (min): Minimum time from refresh to refresh or activate. For MEMC_FREQ_RATIO=1 configurations, t_rfc_min should be set t - RoundUp(tRFCmin/tCK). For MEMC_FREQ_RATIO=2 configurations, t_rfc_min should be set to RoundUp(RoundUp(tRFCmin/tCK)/2). In L - DDR2/LPDDR3/LPDDR4 mode: - if using all-bank refreshes, the tRFCmin value in the above equations is equal to tRFCab - if usin - per-bank refreshes, the tRFCmin value in the above equations is equal to tRFCpb In DDR4 mode, the tRFCmin value in the above - equations is different depending on the refresh mode (fixed 1X,2X,4X) and the device density. The user should program the app - opriate value from the spec based on the 'refresh_mode' and the device density that is used. Unit: Clocks. - PSU_DDRC_RFSHTMG_T_RFC_MIN 0x8b - - Refresh Timing Register - (OFFSET, MASK, VALUE) (0XFD070064, 0x0FFF83FFU ,0x0082808BU) - RegMask = (DDRC_RFSHTMG_T_RFC_NOM_X32_MASK | DDRC_RFSHTMG_LPDDR3_TREFBW_EN_MASK | DDRC_RFSHTMG_T_RFC_MIN_MASK | 0 ); - - RegVal = ((0x00000082U << DDRC_RFSHTMG_T_RFC_NOM_X32_SHIFT - | 0x00000001U << DDRC_RFSHTMG_LPDDR3_TREFBW_EN_SHIFT - | 0x0000008BU << DDRC_RFSHTMG_T_RFC_MIN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_RFSHTMG_OFFSET ,0x0FFF83FFU ,0x0082808BU); - /*############################################################################################################################ */ - - /*Register : ECCCFG0 @ 0XFD070070

- - Disable ECC scrubs. Valid only when ECCCFG0.ecc_mode = 3'b100 and MEMC_USE_RMW is defined - PSU_DDRC_ECCCFG0_DIS_SCRUB 0x1 - - ECC mode indicator - 000 - ECC disabled - 100 - ECC enabled - SEC/DED over 1 beat - all other settings are reserved for futur - use - PSU_DDRC_ECCCFG0_ECC_MODE 0x0 - - ECC Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD070070, 0x00000017U ,0x00000010U) - RegMask = (DDRC_ECCCFG0_DIS_SCRUB_MASK | DDRC_ECCCFG0_ECC_MODE_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_ECCCFG0_DIS_SCRUB_SHIFT - | 0x00000000U << DDRC_ECCCFG0_ECC_MODE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_ECCCFG0_OFFSET ,0x00000017U ,0x00000010U); - /*############################################################################################################################ */ - - /*Register : ECCCFG1 @ 0XFD070074

- - Selects whether to poison 1 or 2 bits - if 0 -> 2-bit (uncorrectable) data poisoning, if 1 -> 1-bit (correctable) data poison - ng, if ECCCFG1.data_poison_en=1 - PSU_DDRC_ECCCFG1_DATA_POISON_BIT 0x0 - - Enable ECC data poisoning - introduces ECC errors on writes to address specified by the ECCPOISONADDR0/1 registers - PSU_DDRC_ECCCFG1_DATA_POISON_EN 0x0 - - ECC Configuration Register 1 - (OFFSET, MASK, VALUE) (0XFD070074, 0x00000003U ,0x00000000U) - RegMask = (DDRC_ECCCFG1_DATA_POISON_BIT_MASK | DDRC_ECCCFG1_DATA_POISON_EN_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_ECCCFG1_DATA_POISON_BIT_SHIFT - | 0x00000000U << DDRC_ECCCFG1_DATA_POISON_EN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_ECCCFG1_OFFSET ,0x00000003U ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : CRCPARCTL1 @ 0XFD0700C4

- - The maximum number of DFI PHY clock cycles allowed from the assertion of the dfi_rddata_en signal to the assertion of each of - the corresponding bits of the dfi_rddata_valid signal. This corresponds to the DFI timing parameter tphy_rdlat. Refer to PHY - pecification for correct value. This value it only used for detecting read data timeout when DDR4 retry is enabled by CRCPARC - L1.crc_parity_retry_enable=1. Maximum supported value: - 1:1 Frequency mode : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_ - dlat < 'd114 - 1:2 Frequency mode ANDAND DFITMG0.dfi_rddata_use_sdr == 1 : CRCPARCTL1.dfi_t_phy_rdlat < 64 - 1:2 Frequency mo - e ANDAND DFITMG0.dfi_rddata_use_sdr == 0 : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_rdlat < 'd114 Unit: DFI Clocks - PSU_DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT 0x10 - - After a Parity or CRC error is flagged on dfi_alert_n signal, the software has an option to read the mode registers in the DR - M before the hardware begins the retry process - 1: Wait for software to read/write the mode registers before hardware begins - the retry. After software is done with its operations, it will clear the alert interrupt register bit - 0: Hardware can begin - the retry right away after the dfi_alert_n pulse goes away. The value on this register is valid only when retry is enabled (P - RCTRL.crc_parity_retry_enable = 1) If this register is set to 1 and if the software doesn't clear the interrupt register afte - handling the parity/CRC error, then the hardware will not begin the retry process and the system will hang. In the case of P - rity/CRC error, there are two possibilities when the software doesn't reset MR5[4] to 0. - (i) If 'Persistent parity' mode re - ister bit is NOT set: the commands sent during retry and normal operation are executed without parity checking. The value in - he Parity error log register MPR Page 1 is valid. - (ii) If 'Persistent parity' mode register bit is SET: Parity checking is - one for commands sent during retry and normal operation. If multiple errors occur before MR5[4] is cleared, the error log in - PR Page 1 should be treated as 'Don't care'. - PSU_DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW 0x1 - - - 1: Enable command retry mechanism in case of C/A Parity or CRC error - 0: Disable command retry mechanism when C/A Parity o - CRC features are enabled. Note that retry functionality is not supported if burst chop is enabled (MSTR.burstchop = 1) and/o - disable auto-refresh is enabled (RFSHCTL3.dis_auto_refresh = 1) - PSU_DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE 0x0 - - CRC Calculation setting register - 1: CRC includes DM signal - 0: CRC not includes DM signal Present only in designs configur - d to support DDR4. - PSU_DDRC_CRCPARCTL1_CRC_INC_DM 0x0 - - CRC enable Register - 1: Enable generation of CRC - 0: Disable generation of CRC The setting of this register should match th - CRC mode register setting in the DRAM. - PSU_DDRC_CRCPARCTL1_CRC_ENABLE 0x0 - - C/A Parity enable register - 1: Enable generation of C/A parity and detection of C/A parity error - 0: Disable generation of - /A parity and disable detection of C/A parity error If RCD's parity error detection or SDRAM's parity detection is enabled, t - is register should be 1. - PSU_DDRC_CRCPARCTL1_PARITY_ENABLE 0x0 - - CRC Parity Control Register1 - (OFFSET, MASK, VALUE) (0XFD0700C4, 0x3F000391U ,0x10000200U) - RegMask = (DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_MASK | DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_MASK | DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_MASK | DDRC_CRCPARCTL1_CRC_INC_DM_MASK | DDRC_CRCPARCTL1_CRC_ENABLE_MASK | DDRC_CRCPARCTL1_PARITY_ENABLE_MASK | 0 ); - - RegVal = ((0x00000010U << DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_SHIFT - | 0x00000001U << DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_SHIFT - | 0x00000000U << DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_SHIFT - | 0x00000000U << DDRC_CRCPARCTL1_CRC_INC_DM_SHIFT - | 0x00000000U << DDRC_CRCPARCTL1_CRC_ENABLE_SHIFT - | 0x00000000U << DDRC_CRCPARCTL1_PARITY_ENABLE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_CRCPARCTL1_OFFSET ,0x3F000391U ,0x10000200U); - /*############################################################################################################################ */ - - /*Register : CRCPARCTL2 @ 0XFD0700C8

- - Value from the DRAM spec indicating the maximum width of the dfi_alert_n pulse when a parity error occurs. Recommended values - - tPAR_ALERT_PW.MAX For configurations with MEMC_FREQ_RATIO=2, program this to tPAR_ALERT_PW.MAX/2 and round up to next inte - er value. Values of 0, 1 and 2 are illegal. This value must be greater than CRCPARCTL2.t_crc_alert_pw_max. - PSU_DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX 0x40 - - Value from the DRAM spec indicating the maximum width of the dfi_alert_n pulse when a CRC error occurs. Recommended values: - - tCRC_ALERT_PW.MAX For configurations with MEMC_FREQ_RATIO=2, program this to tCRC_ALERT_PW.MAX/2 and round up to next integer - value. Values of 0, 1 and 2 are illegal. This value must be less than CRCPARCTL2.t_par_alert_pw_max. - PSU_DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX 0x5 - - Indicates the maximum duration in number of DRAM clock cycles for which a command should be held in the Command Retry FIFO be - ore it is popped out. Every location in the Command Retry FIFO has an associated down counting timer that will use this regis - er as the start value. The down counting starts when a command is loaded into the FIFO. The timer counts down every 4 DRAM cy - les. When the counter reaches zero, the entry is popped from the FIFO. All the counters are frozen, if a C/A Parity or CRC er - or occurs before the counter reaches zero. The counter is reset to 0, after all the commands in the FIFO are retried. Recomme - ded(minimum) values: - Only C/A Parity is enabled. RoundUp((PHY Command Latency(DRAM CLK) + CAL + RDIMM delay + tPAR_ALERT_ON - max + tPAR_UNKNOWN + PHY Alert Latency(DRAM CLK) + board delay) / 4) + 2 - Both C/A Parity and CRC is enabled/ Only CRC is en - bled. RoundUp((PHY Command Latency(DRAM CLK) + CAL + RDIMM delay + WL + 5(BL10)+ tCRC_ALERT.max + PHY Alert Latency(DRAM CLK) - + board delay) / 4) + 2 Note 1: All value (e.g. tPAR_ALERT_ON) should be in terms of DRAM Clock and round up Note 2: Board de - ay(Command/Alert_n) should be considered. Note 3: Use the worst case(longer) value for PHY Latencies/Board delay Note 4: The - ecommended values are minimum value to be set. For mode detail, See 'Calculation of FIFO Depth' section. Max value can be set - to this register is defined below: - MEMC_BURST_LENGTH == 16 Full bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH- - Full bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Half bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_D - PTH-4 Half bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-6 Quarter bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CM - _FIFO_DEPTH-8 Quarter bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-12 - MEMC_BURST_LENGTH != 16 Full bus Mode (C - C=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-1 Full bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mo - e (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Quarte - bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-4 Quarter bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEP - H-6 Values of 0, 1 and 2 are illegal. - PSU_DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4 0x1f - - CRC Parity Control Register2 - (OFFSET, MASK, VALUE) (0XFD0700C8, 0x01FF1F3FU ,0x0040051FU) - RegMask = (DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_MASK | DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_MASK | DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_MASK | 0 ); - - RegVal = ((0x00000040U << DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_SHIFT - | 0x00000005U << DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_SHIFT - | 0x0000001FU << DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_CRCPARCTL2_OFFSET ,0x01FF1F3FU ,0x0040051FU); - /*############################################################################################################################ */ - - /*Register : INIT0 @ 0XFD0700D0

- - If lower bit is enabled the SDRAM initialization routine is skipped. The upper bit decides what state the controller starts u - in when reset is removed - 00 - SDRAM Intialization routine is run after power-up - 01 - SDRAM Intialization routine is skip - ed after power-up. Controller starts up in Normal Mode - 11 - SDRAM Intialization routine is skipped after power-up. Controll - r starts up in Self-refresh Mode - 10 - SDRAM Intialization routine is run after power-up. Note: The only 2'b00 is supported - or LPDDR4 in this version of the uMCTL2. - PSU_DDRC_INIT0_SKIP_DRAM_INIT 0x0 - - Cycles to wait after driving CKE high to start the SDRAM initialization sequence. Unit: 1024 clocks. DDR2 typically requires - 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2/LPDDR3 typically requires this to be pr - grammed for a delay of 200 us. LPDDR4 typically requires this to be programmed for a delay of 2 us. For configurations with M - MC_FREQ_RATIO=2, program this to JEDEC spec value divided by 2, and round it up to next integer value. - PSU_DDRC_INIT0_POST_CKE_X1024 0x2 - - Cycles to wait after reset before driving CKE high to start the SDRAM initialization sequence. Unit: 1024 clock cycles. DDR2 - pecifications typically require this to be programmed for a delay of >= 200 us. LPDDR2/LPDDR3: tINIT1 of 100 ns (min) LPDDR4: - tINIT3 of 2 ms (min) For configurations with MEMC_FREQ_RATIO=2, program this to JEDEC spec value divided by 2, and round it u - to next integer value. - PSU_DDRC_INIT0_PRE_CKE_X1024 0x106 - - SDRAM Initialization Register 0 - (OFFSET, MASK, VALUE) (0XFD0700D0, 0xC3FF0FFFU ,0x00020106U) - RegMask = (DDRC_INIT0_SKIP_DRAM_INIT_MASK | DDRC_INIT0_POST_CKE_X1024_MASK | DDRC_INIT0_PRE_CKE_X1024_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_INIT0_SKIP_DRAM_INIT_SHIFT - | 0x00000002U << DDRC_INIT0_POST_CKE_X1024_SHIFT - | 0x00000106U << DDRC_INIT0_PRE_CKE_X1024_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_INIT0_OFFSET ,0xC3FF0FFFU ,0x00020106U); - /*############################################################################################################################ */ - - /*Register : INIT1 @ 0XFD0700D4

- - Number of cycles to assert SDRAM reset signal during init sequence. This is only present for designs supporting DDR3, DDR4 or - LPDDR4 devices. For use with a DDR PHY, this should be set to a minimum of 1 - PSU_DDRC_INIT1_DRAM_RSTN_X1024 0x2 - - Cycles to wait after completing the SDRAM initialization sequence before starting the dynamic scheduler. Unit: Counts of a gl - bal timer that pulses every 32 clock cycles. There is no known specific requirement for this; it may be set to zero. - PSU_DDRC_INIT1_FINAL_WAIT_X32 0x0 - - Wait period before driving the OCD complete command to SDRAM. Unit: Counts of a global timer that pulses every 32 clock cycle - . There is no known specific requirement for this; it may be set to zero. - PSU_DDRC_INIT1_PRE_OCD_X32 0x0 - - SDRAM Initialization Register 1 - (OFFSET, MASK, VALUE) (0XFD0700D4, 0x01FF7F0FU ,0x00020000U) - RegMask = (DDRC_INIT1_DRAM_RSTN_X1024_MASK | DDRC_INIT1_FINAL_WAIT_X32_MASK | DDRC_INIT1_PRE_OCD_X32_MASK | 0 ); - - RegVal = ((0x00000002U << DDRC_INIT1_DRAM_RSTN_X1024_SHIFT - | 0x00000000U << DDRC_INIT1_FINAL_WAIT_X32_SHIFT - | 0x00000000U << DDRC_INIT1_PRE_OCD_X32_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_INIT1_OFFSET ,0x01FF7F0FU ,0x00020000U); - /*############################################################################################################################ */ - - /*Register : INIT2 @ 0XFD0700D8

- - Idle time after the reset command, tINIT4. Present only in designs configured to support LPDDR2. Unit: 32 clock cycles. - PSU_DDRC_INIT2_IDLE_AFTER_RESET_X32 0x23 - - Time to wait after the first CKE high, tINIT2. Present only in designs configured to support LPDDR2/LPDDR3. Unit: 1 clock cyc - e. LPDDR2/LPDDR3 typically requires 5 x tCK delay. - PSU_DDRC_INIT2_MIN_STABLE_CLOCK_X1 0x5 - - SDRAM Initialization Register 2 - (OFFSET, MASK, VALUE) (0XFD0700D8, 0x0000FF0FU ,0x00002305U) - RegMask = (DDRC_INIT2_IDLE_AFTER_RESET_X32_MASK | DDRC_INIT2_MIN_STABLE_CLOCK_X1_MASK | 0 ); - - RegVal = ((0x00000023U << DDRC_INIT2_IDLE_AFTER_RESET_X32_SHIFT - | 0x00000005U << DDRC_INIT2_MIN_STABLE_CLOCK_X1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_INIT2_OFFSET ,0x0000FF0FU ,0x00002305U); - /*############################################################################################################################ */ - - /*Register : INIT3 @ 0XFD0700DC

- - DDR2: Value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The uMCTL2 sets this bit appropriately - DDR3/DDR4: Value loaded into MR0 register. mDDR: Value to write to MR register. LPDDR2/LPDDR3/LPDDR4 - Value to write to MR1 - register - PSU_DDRC_INIT3_MR 0x930 - - DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setting in this register is ignored. The uMCTL2 sets those - bits appropriately. DDR3/DDR4: Value to write to MR1 register Set bit 7 to 0. If PHY-evaluation mode training is enabled, thi - bit is set appropriately by the uMCTL2 during write leveling. mDDR: Value to write to EMR register. LPDDR2/LPDDR3/LPDDR4 - V - lue to write to MR2 register - PSU_DDRC_INIT3_EMR 0x301 - - SDRAM Initialization Register 3 - (OFFSET, MASK, VALUE) (0XFD0700DC, 0xFFFFFFFFU ,0x09300301U) - RegMask = (DDRC_INIT3_MR_MASK | DDRC_INIT3_EMR_MASK | 0 ); - - RegVal = ((0x00000930U << DDRC_INIT3_MR_SHIFT - | 0x00000301U << DDRC_INIT3_EMR_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_INIT3_OFFSET ,0xFFFFFFFFU ,0x09300301U); - /*############################################################################################################################ */ - - /*Register : INIT4 @ 0XFD0700E0

- - DDR2: Value to write to EMR2 register. DDR3/DDR4: Value to write to MR2 register LPDDR2/LPDDR3/LPDDR4: Value to write to MR3 - egister mDDR: Unused - PSU_DDRC_INIT4_EMR2 0x20 - - DDR2: Value to write to EMR3 register. DDR3/DDR4: Value to write to MR3 register mDDR/LPDDR2/LPDDR3: Unused LPDDR4: Value to - rite to MR13 register - PSU_DDRC_INIT4_EMR3 0x200 - - SDRAM Initialization Register 4 - (OFFSET, MASK, VALUE) (0XFD0700E0, 0xFFFFFFFFU ,0x00200200U) - RegMask = (DDRC_INIT4_EMR2_MASK | DDRC_INIT4_EMR3_MASK | 0 ); - - RegVal = ((0x00000020U << DDRC_INIT4_EMR2_SHIFT - | 0x00000200U << DDRC_INIT4_EMR3_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_INIT4_OFFSET ,0xFFFFFFFFU ,0x00200200U); - /*############################################################################################################################ */ - - /*Register : INIT5 @ 0XFD0700E4

- - ZQ initial calibration, tZQINIT. Present only in designs configured to support DDR3 or DDR4 or LPDDR2/LPDDR3. Unit: 32 clock - ycles. DDR3 typically requires 512 clocks. DDR4 requires 1024 clocks. LPDDR2/LPDDR3 requires 1 us. - PSU_DDRC_INIT5_DEV_ZQINIT_X32 0x21 - - Maximum duration of the auto initialization, tINIT5. Present only in designs configured to support LPDDR2/LPDDR3. LPDDR2/LPDD - 3 typically requires 10 us. - PSU_DDRC_INIT5_MAX_AUTO_INIT_X1024 0x4 - - SDRAM Initialization Register 5 - (OFFSET, MASK, VALUE) (0XFD0700E4, 0x00FF03FFU ,0x00210004U) - RegMask = (DDRC_INIT5_DEV_ZQINIT_X32_MASK | DDRC_INIT5_MAX_AUTO_INIT_X1024_MASK | 0 ); - - RegVal = ((0x00000021U << DDRC_INIT5_DEV_ZQINIT_X32_SHIFT - | 0x00000004U << DDRC_INIT5_MAX_AUTO_INIT_X1024_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_INIT5_OFFSET ,0x00FF03FFU ,0x00210004U); - /*############################################################################################################################ */ - - /*Register : INIT6 @ 0XFD0700E8

- - DDR4- Value to be loaded into SDRAM MR4 registers. Used in DDR4 designs only. - PSU_DDRC_INIT6_MR4 0x0 - - DDR4- Value to be loaded into SDRAM MR5 registers. Used in DDR4 designs only. - PSU_DDRC_INIT6_MR5 0x6c0 - - SDRAM Initialization Register 6 - (OFFSET, MASK, VALUE) (0XFD0700E8, 0xFFFFFFFFU ,0x000006C0U) - RegMask = (DDRC_INIT6_MR4_MASK | DDRC_INIT6_MR5_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_INIT6_MR4_SHIFT - | 0x000006C0U << DDRC_INIT6_MR5_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_INIT6_OFFSET ,0xFFFFFFFFU ,0x000006C0U); - /*############################################################################################################################ */ - - /*Register : INIT7 @ 0XFD0700EC

- - DDR4- Value to be loaded into SDRAM MR6 registers. Used in DDR4 designs only. - PSU_DDRC_INIT7_MR6 0x819 - - SDRAM Initialization Register 7 - (OFFSET, MASK, VALUE) (0XFD0700EC, 0xFFFF0000U ,0x08190000U) - RegMask = (DDRC_INIT7_MR6_MASK | 0 ); - - RegVal = ((0x00000819U << DDRC_INIT7_MR6_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_INIT7_OFFSET ,0xFFFF0000U ,0x08190000U); - /*############################################################################################################################ */ - - /*Register : DIMMCTL @ 0XFD0700F0

- - Disabling Address Mirroring for BG bits. When this is set to 1, BG0 and BG1 are NOT swapped even if Address Mirroring is enab - ed. This will be required for DDR4 DIMMs with x16 devices. - 1 - BG0 and BG1 are NOT swapped. - 0 - BG0 and BG1 are swapped i - address mirroring is enabled. - PSU_DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING 0x0 - - Enable for BG1 bit of MRS command. BG1 bit of the mode register address is specified as RFU (Reserved for Future Use) and mus - be programmed to 0 during MRS. In case where DRAMs which do not have BG1 are attached and both the CA parity and the Output - nversion are enabled, this must be set to 0, so that the calculation of CA parity will not include BG1 bit. Note: This has no - effect on the address of any other memory accesses, or of software-driven mode register accesses. If address mirroring is ena - led, this is applied to BG1 of even ranks and BG0 of odd ranks. - 1 - Enabled - 0 - Disabled - PSU_DDRC_DIMMCTL_MRS_BG1_EN 0x1 - - Enable for A17 bit of MRS command. A17 bit of the mode register address is specified as RFU (Reserved for Future Use) and mus - be programmed to 0 during MRS. In case where DRAMs which do not have A17 are attached and the Output Inversion are enabled, - his must be set to 0, so that the calculation of CA parity will not include A17 bit. Note: This has no effect on the address - f any other memory accesses, or of software-driven mode register accesses. - 1 - Enabled - 0 - Disabled - PSU_DDRC_DIMMCTL_MRS_A17_EN 0x0 - - Output Inversion Enable (for DDR4 RDIMM implementations only). DDR4 RDIMM implements the Output Inversion feature by default, - which means that the following address, bank address and bank group bits of B-side DRAMs are inverted: A3-A9, A11, A13, A17, - A0-BA1, BG0-BG1. Setting this bit ensures that, for mode register accesses generated by the uMCTL2 during the automatic initi - lization routine and enabling of a particular DDR4 feature, separate A-side and B-side mode register accesses are generated. - or B-side mode register accesses, these bits are inverted within the uMCTL2 to compensate for this RDIMM inversion. Note: Thi - has no effect on the address of any other memory accesses, or of software-driven mode register accesses. - 1 - Implement out - ut inversion for B-side DRAMs. - 0 - Do not implement output inversion for B-side DRAMs. - PSU_DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN 0x0 - - Address Mirroring Enable (for multi-rank UDIMM implementations and multi-rank DDR4 RDIMM implementations). Some UDIMMs and DD - 4 RDIMMs implement address mirroring for odd ranks, which means that the following address, bank address and bank group bits - re swapped: (A3, A4), (A5, A6), (A7, A8), (BA0, BA1) and also (A11, A13), (BG0, BG1) for the DDR4. Setting this bit ensures t - at, for mode register accesses during the automatic initialization routine, these bits are swapped within the uMCTL2 to compe - sate for this UDIMM/RDIMM swapping. In addition to the automatic initialization routine, in case of DDR4 UDIMM/RDIMM, they ar - swapped during the automatic MRS access to enable/disable of a particular DDR4 feature. Note: This has no effect on the addr - ss of any other memory accesses, or of software-driven mode register accesses. This is not supported for mDDR, LPDDR2, LPDDR3 - or LPDDR4 SDRAMs. Note: In case of x16 DDR4 DIMMs, BG1 output of MRS for the odd ranks is same as BG0 because BG1 is invalid, - hence dimm_dis_bg_mirroring register must be set to 1. - 1 - For odd ranks, implement address mirroring for MRS commands to d - ring initialization and for any automatic DDR4 MRS commands (to be used if UDIMM/RDIMM implements address mirroring) - 0 - Do - not implement address mirroring - PSU_DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN 0x0 - - Staggering enable for multi-rank accesses (for multi-rank UDIMM and RDIMM implementations only). This is not supported for mD - R, LPDDR2, LPDDR3 or LPDDR4 SDRAMs. Note: Even if this bit is set it does not take care of software driven MR commands (via M - CTRL0/MRCTRL1), where software is responsible to send them to seperate ranks as appropriate. - 1 - (DDR4) Send MRS commands t - each ranks seperately - 1 - (non-DDR4) Send all commands to even and odd ranks seperately - 0 - Do not stagger accesses - PSU_DDRC_DIMMCTL_DIMM_STAGGER_CS_EN 0x0 - - DIMM Control Register - (OFFSET, MASK, VALUE) (0XFD0700F0, 0x0000003FU ,0x00000010U) - RegMask = (DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_MASK | DDRC_DIMMCTL_MRS_BG1_EN_MASK | DDRC_DIMMCTL_MRS_A17_EN_MASK | DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_MASK | DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_MASK | DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_SHIFT - | 0x00000001U << DDRC_DIMMCTL_MRS_BG1_EN_SHIFT - | 0x00000000U << DDRC_DIMMCTL_MRS_A17_EN_SHIFT - | 0x00000000U << DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_SHIFT - | 0x00000000U << DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_SHIFT - | 0x00000000U << DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DIMMCTL_OFFSET ,0x0000003FU ,0x00000010U); - /*############################################################################################################################ */ - - /*Register : RANKCTL @ 0XFD0700F4

- - Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecuti - e writes to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This value should c - nsider both PHY requirement and ODT requirement. - PHY requirement: tphy_wrcsgap + 1 (see PHY databook for value of tphy_wrcs - ap) If CRC feature is enabled, should be increased by 1. If write preamble is set to 2tCK(DDR4/LPDDR4 only), should be increa - ed by 1. If write postamble is set to 1.5tCK(LPDDR4 only), should be increased by 1. - ODT requirement: The value programmed - n this register takes care of the ODT switch off timing requirement when switching ranks during writes. For LPDDR4, the requi - ement is ODTLoff - ODTLon - BL/2 + 1 For configurations with MEMC_FREQ_RATIO=1, program this to the larger of PHY requirement - or ODT requirement. For configurations with MEMC_FREQ_RATIO=2, program this to the larger value divided by two and round it u - to the next integer. - PSU_DDRC_RANKCTL_DIFF_RANK_WR_GAP 0x6 - - Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecuti - e reads to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This value should co - sider both PHY requirement and ODT requirement. - PHY requirement: tphy_rdcsgap + 1 (see PHY databook for value of tphy_rdcsg - p) If read preamble is set to 2tCK(DDR4/LPDDR4 only), should be increased by 1. If read postamble is set to 1.5tCK(LPDDR4 onl - ), should be increased by 1. - ODT requirement: The value programmed in this register takes care of the ODT switch off timing - requirement when switching ranks during reads. For configurations with MEMC_FREQ_RATIO=1, program this to the larger of PHY r - quirement or ODT requirement. For configurations with MEMC_FREQ_RATIO=2, program this to the larger value divided by two and - ound it up to the next integer. - PSU_DDRC_RANKCTL_DIFF_RANK_RD_GAP 0x6 - - Only present for multi-rank configurations. Background: Reads to the same rank can be performed back-to-back. Reads to differ - nt ranks require additional gap dictated by the register RANKCTL.diff_rank_rd_gap. This is to avoid possible data bus content - on as well as to give PHY enough time to switch the delay when changing ranks. The uMCTL2 arbitrates for bus access on a cycl - -by-cycle basis; therefore after a read is scheduled, there are few clock cycles (determined by the value on RANKCTL.diff_ran - _rd_gap register) in which only reads from the same rank are eligible to be scheduled. This prevents reads from other ranks f - om having fair access to the data bus. This parameter represents the maximum number of reads that can be scheduled consecutiv - ly to the same rank. After this number is reached, a delay equal to RANKCTL.diff_rank_rd_gap is inserted by the scheduler to - llow all ranks a fair opportunity to be scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fair - ess. This feature can be DISABLED by setting this register to 0. When set to 0, the Controller will stay on the same rank as - ong as commands are available for it. Minimum programmable value is 0 (feature disabled) and maximum programmable value is 0x - . FOR PERFORMANCE ONLY. - PSU_DDRC_RANKCTL_MAX_RANK_RD 0xf - - Rank Control Register - (OFFSET, MASK, VALUE) (0XFD0700F4, 0x00000FFFU ,0x0000066FU) - RegMask = (DDRC_RANKCTL_DIFF_RANK_WR_GAP_MASK | DDRC_RANKCTL_DIFF_RANK_RD_GAP_MASK | DDRC_RANKCTL_MAX_RANK_RD_MASK | 0 ); - - RegVal = ((0x00000006U << DDRC_RANKCTL_DIFF_RANK_WR_GAP_SHIFT - | 0x00000006U << DDRC_RANKCTL_DIFF_RANK_RD_GAP_SHIFT - | 0x0000000FU << DDRC_RANKCTL_MAX_RANK_RD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_RANKCTL_OFFSET ,0x00000FFFU ,0x0000066FU); - /*############################################################################################################################ */ - - /*Register : DRAMTMG0 @ 0XFD070100

- - Minimum time between write and precharge to same bank. Unit: Clocks Specifications: WL + BL/2 + tWR = approximately 8 cycles - 15 ns = 14 clocks @400MHz and less for lower frequencies where: - WL = write latency - BL = burst length. This must match th - value programmed in the BL bit of the mode register to the SDRAM. BST (burst terminate) is not supported at present. - tWR = - Write recovery time. This comes directly from the SDRAM specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 for this - arameter. For configurations with MEMC_FREQ_RATIO=2, 1T mode, divide the above value by 2. No rounding up. For configurations - with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, divide the above value by 2 and round it up to the next integer value. - PSU_DDRC_DRAMTMG0_WR2PRE 0x11 - - tFAW Valid only when 8 or more banks(or banks x bank groups) are present. In 8-bank design, at most 4 banks must be activated - in a rolling window of tFAW cycles. For configurations with MEMC_FREQ_RATIO=2, program this to (tFAW/2) and round up to next - nteger value. In a 4-bank design, set this register to 0x1 independent of the MEMC_FREQ_RATIO configuration. Unit: Clocks - PSU_DDRC_DRAMTMG0_T_FAW 0xc - - tRAS(max): Maximum time between activate and precharge to same bank. This is the maximum time that a page can be kept open Mi - imum value of this register is 1. Zero is invalid. For configurations with MEMC_FREQ_RATIO=2, program this to (tRAS(max)-1)/2 - No rounding up. Unit: Multiples of 1024 clocks. - PSU_DDRC_DRAMTMG0_T_RAS_MAX 0x24 - - tRAS(min): Minimum time between activate and precharge to the same bank. For configurations with MEMC_FREQ_RATIO=2, 1T mode, - rogram this to tRAS(min)/2. No rounding up. For configurations with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, program this t - (tRAS(min)/2) and round it up to the next integer value. Unit: Clocks - PSU_DDRC_DRAMTMG0_T_RAS_MIN 0x12 - - SDRAM Timing Register 0 - (OFFSET, MASK, VALUE) (0XFD070100, 0x7F3F7F3FU ,0x110C2412U) - RegMask = (DDRC_DRAMTMG0_WR2PRE_MASK | DDRC_DRAMTMG0_T_FAW_MASK | DDRC_DRAMTMG0_T_RAS_MAX_MASK | DDRC_DRAMTMG0_T_RAS_MIN_MASK | 0 ); - - RegVal = ((0x00000011U << DDRC_DRAMTMG0_WR2PRE_SHIFT - | 0x0000000CU << DDRC_DRAMTMG0_T_FAW_SHIFT - | 0x00000024U << DDRC_DRAMTMG0_T_RAS_MAX_SHIFT - | 0x00000012U << DDRC_DRAMTMG0_T_RAS_MIN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DRAMTMG0_OFFSET ,0x7F3F7F3FU ,0x110C2412U); - /*############################################################################################################################ */ - - /*Register : DRAMTMG1 @ 0XFD070104

- - tXP: Minimum time after power-down exit to any operation. For DDR3, this should be programmed to tXPDLL if slow powerdown exi - is selected in MR0[12]. If C/A parity for DDR4 is used, set to (tXP+PL) instead. For configurations with MEMC_FREQ_RATIO=2, - rogram this to (tXP/2) and round it up to the next integer value. Units: Clocks - PSU_DDRC_DRAMTMG1_T_XP 0x4 - - tRTP: Minimum time from read to precharge of same bank. - DDR2: tAL + BL/2 + max(tRTP, 2) - 2 - DDR3: tAL + max (tRTP, 4) - D - R4: Max of following two equations: tAL + max (tRTP, 4) or, RL + BL/2 - tRP. - mDDR: BL/2 - LPDDR2: Depends on if it's LPDDR2 - S2 or LPDDR2-S4: LPDDR2-S2: BL/2 + tRTP - 1. LPDDR2-S4: BL/2 + max(tRTP,2) - 2. - LPDDR3: BL/2 + max(tRTP,4) - 4 - LPDDR4: BL - 2 + max(tRTP,8) - 8 For configurations with MEMC_FREQ_RATIO=2, 1T mode, divide the above value by 2. No rounding up. For conf - gurations with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, divide the above value by 2 and round it up to the next integer val - e. Unit: Clocks. - PSU_DDRC_DRAMTMG1_RD2PRE 0x4 - - tRC: Minimum time between activates to same bank. For configurations with MEMC_FREQ_RATIO=2, program this to (tRC/2) and roun - up to next integer value. Unit: Clocks. - PSU_DDRC_DRAMTMG1_T_RC 0x19 - - SDRAM Timing Register 1 - (OFFSET, MASK, VALUE) (0XFD070104, 0x001F1F7FU ,0x00040419U) - RegMask = (DDRC_DRAMTMG1_T_XP_MASK | DDRC_DRAMTMG1_RD2PRE_MASK | DDRC_DRAMTMG1_T_RC_MASK | 0 ); - - RegVal = ((0x00000004U << DDRC_DRAMTMG1_T_XP_SHIFT - | 0x00000004U << DDRC_DRAMTMG1_RD2PRE_SHIFT - | 0x00000019U << DDRC_DRAMTMG1_T_RC_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DRAMTMG1_OFFSET ,0x001F1F7FU ,0x00040419U); - /*############################################################################################################################ */ - - /*Register : DRAMTMG2 @ 0XFD070108

- - Set to WL Time from write command to write data on SDRAM interface. This must be set to WL. For mDDR, it should normally be s - t to 1. Note that, depending on the PHY, if using RDIMM, it may be necessary to use a value of WL + 1 to compensate for the e - tra cycle of latency through the RDIMM For configurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above - equation by 2, and round it up to next integer. This register field is not required for DDR2 and DDR3 (except if MEMC_TRAININ - is set), as the DFI read and write latencies defined in DFITMG0 and DFITMG1 are sufficient for those protocols Unit: clocks - PSU_DDRC_DRAMTMG2_WRITE_LATENCY 0x7 - - Set to RL Time from read command to read data on SDRAM interface. This must be set to RL. Note that, depending on the PHY, if - using RDIMM, it mat be necessary to use a value of RL + 1 to compensate for the extra cycle of latency through the RDIMM For - onfigurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next inte - er. This register field is not required for DDR2 and DDR3 (except if MEMC_TRAINING is set), as the DFI read and write latenci - s defined in DFITMG0 and DFITMG1 are sufficient for those protocols Unit: clocks - PSU_DDRC_DRAMTMG2_READ_LATENCY 0x8 - - DDR2/3/mDDR: RL + BL/2 + 2 - WL DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL LPDDR2/LPDDR3: RL + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL - PDDR4(DQ ODT is Disabled): RL + BL/2 + RU(tDQSCKmax/tCK) + WR_PREAMBLE + RD_POSTAMBLE - WL LPDDR4(DQ ODT is Enabled) : RL + B - /2 + RU(tDQSCKmax/tCK) + RD_POSTAMBLE - ODTLon - RU(tODTon(min)/tCK) Minimum time from read command to write command. Include - time for bus turnaround and all per-bank, per-rank, and global constraints. Unit: Clocks. Where: - WL = write latency - BL = - urst length. This must match the value programmed in the BL bit of the mode register to the SDRAM - RL = read latency = CAS l - tency - WR_PREAMBLE = write preamble. This is unique to DDR4 and LPDDR4. - RD_POSTAMBLE = read postamble. This is unique to L - DDR4. For LPDDR2/LPDDR3/LPDDR4, if derating is enabled (DERATEEN.derate_enable=1), derated tDQSCKmax should be used. For conf - gurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next integer. - PSU_DDRC_DRAMTMG2_RD2WR 0x6 - - DDR4: CWL + PL + BL/2 + tWTR_L Others: CWL + BL/2 + tWTR In DDR4, minimum time from write command to read command for same ba - k group. In others, minimum time from write command to read command. Includes time for bus turnaround, recovery times, and al - per-bank, per-rank, and global constraints. Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity latency - BL = burs - length. This must match the value programmed in the BL bit of the mode register to the SDRAM - tWTR_L = internal write to re - d command delay for same bank group. This comes directly from the SDRAM specification. - tWTR = internal write to read comman - delay. This comes directly from the SDRAM specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 operation. For configu - ations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next integer. - PSU_DDRC_DRAMTMG2_WR2RD 0xe - - SDRAM Timing Register 2 - (OFFSET, MASK, VALUE) (0XFD070108, 0x3F3F3F3FU ,0x0708060EU) - RegMask = (DDRC_DRAMTMG2_WRITE_LATENCY_MASK | DDRC_DRAMTMG2_READ_LATENCY_MASK | DDRC_DRAMTMG2_RD2WR_MASK | DDRC_DRAMTMG2_WR2RD_MASK | 0 ); - - RegVal = ((0x00000007U << DDRC_DRAMTMG2_WRITE_LATENCY_SHIFT - | 0x00000008U << DDRC_DRAMTMG2_READ_LATENCY_SHIFT - | 0x00000006U << DDRC_DRAMTMG2_RD2WR_SHIFT - | 0x0000000EU << DDRC_DRAMTMG2_WR2RD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DRAMTMG2_OFFSET ,0x3F3F3F3FU ,0x0708060EU); - /*############################################################################################################################ */ - - /*Register : DRAMTMG3 @ 0XFD07010C

- - Time to wait after a mode register write or read (MRW or MRR). Present only in designs configured to support LPDDR2, LPDDR3 o - LPDDR4. LPDDR2 typically requires value of 5. LPDDR3 typically requires value of 10. LPDDR4: Set this to the larger of tMRW - nd tMRWCKEL. For LPDDR2, this register is used for the time from a MRW/MRR to all other commands. For LDPDR3, this register i - used for the time from a MRW/MRR to a MRW/MRR. - PSU_DDRC_DRAMTMG3_T_MRW 0x5 - - tMRD: Cycles to wait after a mode register write or read. Depending on the connected SDRAM, tMRD represents: DDR2/mDDR: Time - rom MRS to any command DDR3/4: Time from MRS to MRS command LPDDR2: not used LPDDR3/4: Time from MRS to non-MRS command For c - nfigurations with MEMC_FREQ_RATIO=2, program this to (tMRD/2) and round it up to the next integer value. If C/A parity for DD - 4 is used, set to tMRD_PAR(tMOD+PL) instead. - PSU_DDRC_DRAMTMG3_T_MRD 0x4 - - tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode command and following non-load mode command. If C/A pari - y for DDR4 is used, set to tMOD_PAR(tMOD+PL) instead. Set to tMOD if MEMC_FREQ_RATIO=1, or tMOD/2 (rounded up to next integer - if MEMC_FREQ_RATIO=2. Note that if using RDIMM, depending on the PHY, it may be necessary to use a value of tMOD + 1 or (tMO - + 1)/2 to compensate for the extra cycle of latency applied to mode register writes by the RDIMM chip. - PSU_DDRC_DRAMTMG3_T_MOD 0xc - - SDRAM Timing Register 3 - (OFFSET, MASK, VALUE) (0XFD07010C, 0x3FF3F3FFU ,0x0050400CU) - RegMask = (DDRC_DRAMTMG3_T_MRW_MASK | DDRC_DRAMTMG3_T_MRD_MASK | DDRC_DRAMTMG3_T_MOD_MASK | 0 ); - - RegVal = ((0x00000005U << DDRC_DRAMTMG3_T_MRW_SHIFT - | 0x00000004U << DDRC_DRAMTMG3_T_MRD_SHIFT - | 0x0000000CU << DDRC_DRAMTMG3_T_MOD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DRAMTMG3_OFFSET ,0x3FF3F3FFU ,0x0050400CU); - /*############################################################################################################################ */ - - /*Register : DRAMTMG4 @ 0XFD070110

- - tRCD - tAL: Minimum time from activate to read or write command to same bank. For configurations with MEMC_FREQ_RATIO=2, prog - am this to ((tRCD - tAL)/2) and round it up to the next integer value. Minimum value allowed for this register is 1, which im - lies minimum (tRCD - tAL) value to be 2 in configurations with MEMC_FREQ_RATIO=2. Unit: Clocks. - PSU_DDRC_DRAMTMG4_T_RCD 0x8 - - DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank group. Others: tCCD: This is the minimum - time between two reads or two writes. For configurations with MEMC_FREQ_RATIO=2, program this to (tCCD_L/2 or tCCD/2) and rou - d it up to the next integer value. Unit: clocks. - PSU_DDRC_DRAMTMG4_T_CCD 0x3 - - DDR4: tRRD_L: Minimum time between activates from bank 'a' to bank 'b' for same bank group. Others: tRRD: Minimum time betwee - activates from bank 'a' to bank 'b'For configurations with MEMC_FREQ_RATIO=2, program this to (tRRD_L/2 or tRRD/2) and round - it up to the next integer value. Unit: Clocks. - PSU_DDRC_DRAMTMG4_T_RRD 0x3 - - tRP: Minimum time from precharge to activate of same bank. For MEMC_FREQ_RATIO=1 configurations, t_rp should be set to RoundU - (tRP/tCK). For MEMC_FREQ_RATIO=2 configurations, t_rp should be set to RoundDown(RoundUp(tRP/tCK)/2) + 1. For MEMC_FREQ_RATIO - 2 configurations in LPDDR4, t_rp should be set to RoundUp(RoundUp(tRP/tCK)/2). Unit: Clocks. - PSU_DDRC_DRAMTMG4_T_RP 0x9 - - SDRAM Timing Register 4 - (OFFSET, MASK, VALUE) (0XFD070110, 0x1F0F0F1FU ,0x08030309U) - RegMask = (DDRC_DRAMTMG4_T_RCD_MASK | DDRC_DRAMTMG4_T_CCD_MASK | DDRC_DRAMTMG4_T_RRD_MASK | DDRC_DRAMTMG4_T_RP_MASK | 0 ); - - RegVal = ((0x00000008U << DDRC_DRAMTMG4_T_RCD_SHIFT - | 0x00000003U << DDRC_DRAMTMG4_T_CCD_SHIFT - | 0x00000003U << DDRC_DRAMTMG4_T_RRD_SHIFT - | 0x00000009U << DDRC_DRAMTMG4_T_RP_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DRAMTMG4_OFFSET ,0x1F0F0F1FU ,0x08030309U); - /*############################################################################################################################ */ - - /*Register : DRAMTMG5 @ 0XFD070114

- - This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stab - e time before SRX. Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEH - DDR2: 1 - DDR3: tCKSRX - DDR4: - tCKSRX For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it up to next in - eger. - PSU_DDRC_DRAMTMG5_T_CKSRX 0x6 - - This is the time after Self Refresh Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay afte - SRE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL - DDR2: 1 - DDR3: max (10 ns, 5 tCK) - DDR4: - ax (10 ns, 5 tCK) For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it up - to next integer. - PSU_DDRC_DRAMTMG5_T_CKSRE 0x6 - - Minimum CKE low width for Self refresh or Self refresh power down entry to exit timing in memory clock cycles. Recommended se - tings: - mDDR: tRFC - LPDDR2: tCKESR - LPDDR3: tCKESR - LPDDR4: max(tCKELPD, tSR) - DDR2: tCKE - DDR3: tCKE + 1 - DDR4: tCKE - 1 For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it up to next intege - . - PSU_DDRC_DRAMTMG5_T_CKESR 0x4 - - Minimum number of cycles of CKE HIGH/LOW during power-down and self refresh. - LPDDR2/LPDDR3 mode: Set this to the larger of - CKE or tCKESR - LPDDR4 mode: Set this to the larger of tCKE, tCKELPD or tSR. - Non-LPDDR2/non-LPDDR3/non-LPDDR4 designs: Set - his to tCKE value. For configurations with MEMC_FREQ_RATIO=2, program this to (value described above)/2 and round it up to th - next integer value. Unit: Clocks. - PSU_DDRC_DRAMTMG5_T_CKE 0x3 - - SDRAM Timing Register 5 - (OFFSET, MASK, VALUE) (0XFD070114, 0x0F0F3F1FU ,0x06060403U) - RegMask = (DDRC_DRAMTMG5_T_CKSRX_MASK | DDRC_DRAMTMG5_T_CKSRE_MASK | DDRC_DRAMTMG5_T_CKESR_MASK | DDRC_DRAMTMG5_T_CKE_MASK | 0 ); - - RegVal = ((0x00000006U << DDRC_DRAMTMG5_T_CKSRX_SHIFT - | 0x00000006U << DDRC_DRAMTMG5_T_CKSRE_SHIFT - | 0x00000004U << DDRC_DRAMTMG5_T_CKESR_SHIFT - | 0x00000003U << DDRC_DRAMTMG5_T_CKE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DRAMTMG5_OFFSET ,0x0F0F3F1FU ,0x06060403U); - /*############################################################################################################################ */ - - /*Register : DRAMTMG6 @ 0XFD070118

- - This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after - PDE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 For configurations with MEMC_FREQ_RATIO=2, program this to recom - ended value divided by two and round it up to next integer. This is only present for designs supporting mDDR or LPDDR2/LPDDR3 - devices. - PSU_DDRC_DRAMTMG6_T_CKDPDE 0x1 - - This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock - table time before DPDX. Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 For configurations with MEMC_FREQ_RATIO=2, pr - gram this to recommended value divided by two and round it up to next integer. This is only present for designs supporting mD - R or LPDDR2 devices. - PSU_DDRC_DRAMTMG6_T_CKDPDX 0x1 - - This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing Clock Stop Exit. Specifies the - lock stable time before next command after Clock Stop Exit. Recommended settings: - mDDR: 1 - LPDDR2: tXP + 2 - LPDDR3: tXP + - 2 - LPDDR4: tXP + 2 For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it - p to next integer. This is only present for designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices. - PSU_DDRC_DRAMTMG6_T_CKCSX 0x4 - - SDRAM Timing Register 6 - (OFFSET, MASK, VALUE) (0XFD070118, 0x0F0F000FU ,0x01010004U) - RegMask = (DDRC_DRAMTMG6_T_CKDPDE_MASK | DDRC_DRAMTMG6_T_CKDPDX_MASK | DDRC_DRAMTMG6_T_CKCSX_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_DRAMTMG6_T_CKDPDE_SHIFT - | 0x00000001U << DDRC_DRAMTMG6_T_CKDPDX_SHIFT - | 0x00000004U << DDRC_DRAMTMG6_T_CKCSX_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DRAMTMG6_OFFSET ,0x0F0F000FU ,0x01010004U); - /*############################################################################################################################ */ - - /*Register : DRAMTMG7 @ 0XFD07011C

- - This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. - ecommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL For configurations with MEMC_FREQ_RATIO=2, program t - is to recommended value divided by two and round it up to next integer. This is only present for designs supporting mDDR or L - DDR2/LPDDR3/LPDDR4 devices. - PSU_DDRC_DRAMTMG7_T_CKPDE 0x6 - - This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable - time before PDX. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: 2 For configurations with MEMC_FREQ_RATIO= - , program this to recommended value divided by two and round it up to next integer. This is only present for designs supporti - g mDDR or LPDDR2/LPDDR3/LPDDR4 devices. - PSU_DDRC_DRAMTMG7_T_CKPDX 0x6 - - SDRAM Timing Register 7 - (OFFSET, MASK, VALUE) (0XFD07011C, 0x00000F0FU ,0x00000606U) - RegMask = (DDRC_DRAMTMG7_T_CKPDE_MASK | DDRC_DRAMTMG7_T_CKPDX_MASK | 0 ); - - RegVal = ((0x00000006U << DDRC_DRAMTMG7_T_CKPDE_SHIFT - | 0x00000006U << DDRC_DRAMTMG7_T_CKPDX_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DRAMTMG7_OFFSET ,0x00000F0FU ,0x00000606U); - /*############################################################################################################################ */ - - /*Register : DRAMTMG8 @ 0XFD070120

- - tXS_FAST: Exit Self Refresh to ZQCL, ZQCS and MRS (only CL, WR, RTP and Geardown mode). For configurations with MEMC_FREQ_RAT - O=2, program this to the above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: Thi - is applicable to only ZQCL/ZQCS commands. Note: Ensure this is less than or equal to t_xs_x32. - PSU_DDRC_DRAMTMG8_T_XS_FAST_X32 0x4 - - tXS_ABORT: Exit Self Refresh to commands not requiring a locked DLL in Self Refresh Abort. For configurations with MEMC_FREQ_ - ATIO=2, program this to the above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: - nsure this is less than or equal to t_xs_x32. - PSU_DDRC_DRAMTMG8_T_XS_ABORT_X32 0x4 - - tXSDLL: Exit Self Refresh to commands requiring a locked DLL. For configurations with MEMC_FREQ_RATIO=2, program this to the - bove value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: Used only for DDR2, DDR3 and - DR4 SDRAMs. - PSU_DDRC_DRAMTMG8_T_XS_DLL_X32 0xd - - tXS: Exit Self Refresh to commands not requiring a locked DLL. For configurations with MEMC_FREQ_RATIO=2, program this to the - above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: Used only for DDR2, DDR3 and - DDR4 SDRAMs. - PSU_DDRC_DRAMTMG8_T_XS_X32 0x6 - - SDRAM Timing Register 8 - (OFFSET, MASK, VALUE) (0XFD070120, 0x7F7F7F7FU ,0x04040D06U) - RegMask = (DDRC_DRAMTMG8_T_XS_FAST_X32_MASK | DDRC_DRAMTMG8_T_XS_ABORT_X32_MASK | DDRC_DRAMTMG8_T_XS_DLL_X32_MASK | DDRC_DRAMTMG8_T_XS_X32_MASK | 0 ); - - RegVal = ((0x00000004U << DDRC_DRAMTMG8_T_XS_FAST_X32_SHIFT - | 0x00000004U << DDRC_DRAMTMG8_T_XS_ABORT_X32_SHIFT - | 0x0000000DU << DDRC_DRAMTMG8_T_XS_DLL_X32_SHIFT - | 0x00000006U << DDRC_DRAMTMG8_T_XS_X32_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DRAMTMG8_OFFSET ,0x7F7F7F7FU ,0x04040D06U); - /*############################################################################################################################ */ - - /*Register : DRAMTMG9 @ 0XFD070124

- - DDR4 Write preamble mode - 0: 1tCK preamble - 1: 2tCK preamble Present only with MEMC_FREQ_RATIO=2 - PSU_DDRC_DRAMTMG9_DDR4_WR_PREAMBLE 0x0 - - tCCD_S: This is the minimum time between two reads or two writes for different bank group. For bank switching (from bank 'a' - o bank 'b'), the minimum time is this value + 1. For configurations with MEMC_FREQ_RATIO=2, program this to (tCCD_S/2) and ro - nd it up to the next integer value. Present only in designs configured to support DDR4. Unit: clocks. - PSU_DDRC_DRAMTMG9_T_CCD_S 0x2 - - tRRD_S: Minimum time between activates from bank 'a' to bank 'b' for different bank group. For configurations with MEMC_FREQ_ - ATIO=2, program this to (tRRD_S/2) and round it up to the next integer value. Present only in designs configured to support D - R4. Unit: Clocks. - PSU_DDRC_DRAMTMG9_T_RRD_S 0x2 - - CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command for different bank group. Includes time for bus turn - round, recovery times, and all per-bank, per-rank, and global constraints. Present only in designs configured to support DDR4 - Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity latency - BL = burst length. This must match the value programm - d in the BL bit of the mode register to the SDRAM - tWTR_S = internal write to read command delay for different bank group. T - is comes directly from the SDRAM specification. For configurations with MEMC_FREQ_RATIO=2, divide the value calculated using - he above equation by 2, and round it up to next integer. - PSU_DDRC_DRAMTMG9_WR2RD_S 0xb - - SDRAM Timing Register 9 - (OFFSET, MASK, VALUE) (0XFD070124, 0x40070F3FU ,0x0002020BU) - RegMask = (DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_MASK | DDRC_DRAMTMG9_T_CCD_S_MASK | DDRC_DRAMTMG9_T_RRD_S_MASK | DDRC_DRAMTMG9_WR2RD_S_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_SHIFT - | 0x00000002U << DDRC_DRAMTMG9_T_CCD_S_SHIFT - | 0x00000002U << DDRC_DRAMTMG9_T_RRD_S_SHIFT - | 0x0000000BU << DDRC_DRAMTMG9_WR2RD_S_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DRAMTMG9_OFFSET ,0x40070F3FU ,0x0002020BU); - /*############################################################################################################################ */ - - /*Register : DRAMTMG11 @ 0XFD07012C

- - tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DLL. For configurations with MEMC_FREQ_RATIO=2, program - this to (tXMPDLL/2) and round it up to the next integer value. Present only in designs configured to support DDR4. Unit: Mult - ples of 32 clocks. - PSU_DDRC_DRAMTMG11_POST_MPSM_GAP_X32 0x6f - - tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge. For configurations with MEMC_FREQ_RATIO=2, program this t - RoundUp(tMPX_LH/2)+1. Present only in designs configured to support DDR4. Unit: clocks. - PSU_DDRC_DRAMTMG11_T_MPX_LH 0x7 - - tMPX_S: Minimum time CS setup time to CKE. For configurations with MEMC_FREQ_RATIO=2, program this to (tMPX_S/2) and round it - up to the next integer value. Present only in designs configured to support DDR4. Unit: Clocks. - PSU_DDRC_DRAMTMG11_T_MPX_S 0x1 - - tCKMPE: Minimum valid clock requirement after MPSM entry. Present only in designs configured to support DDR4. Unit: Clocks. F - r configurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next i - teger. - PSU_DDRC_DRAMTMG11_T_CKMPE 0xe - - SDRAM Timing Register 11 - (OFFSET, MASK, VALUE) (0XFD07012C, 0x7F1F031FU ,0x6F07010EU) - RegMask = (DDRC_DRAMTMG11_POST_MPSM_GAP_X32_MASK | DDRC_DRAMTMG11_T_MPX_LH_MASK | DDRC_DRAMTMG11_T_MPX_S_MASK | DDRC_DRAMTMG11_T_CKMPE_MASK | 0 ); - - RegVal = ((0x0000006FU << DDRC_DRAMTMG11_POST_MPSM_GAP_X32_SHIFT - | 0x00000007U << DDRC_DRAMTMG11_T_MPX_LH_SHIFT - | 0x00000001U << DDRC_DRAMTMG11_T_MPX_S_SHIFT - | 0x0000000EU << DDRC_DRAMTMG11_T_CKMPE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DRAMTMG11_OFFSET ,0x7F1F031FU ,0x6F07010EU); - /*############################################################################################################################ */ - - /*Register : DRAMTMG12 @ 0XFD070130

- - tCMDCKE: Delay from valid command to CKE input LOW. Set this to the larger of tESCKE or tCMDCKE For configurations with MEMC_ - REQ_RATIO=2, program this to (max(tESCKE, tCMDCKE)/2) and round it up to next integer value. - PSU_DDRC_DRAMTMG12_T_CMDCKE 0x2 - - tCKEHCMD: Valid command requirement after CKE input HIGH. For configurations with MEMC_FREQ_RATIO=2, program this to (tCKEHCM - /2) and round it up to next integer value. - PSU_DDRC_DRAMTMG12_T_CKEHCMD 0x6 - - tMRD_PDA: This is the Mode Register Set command cycle time in PDA mode. For configurations with MEMC_FREQ_RATIO=2, program th - s to (tMRD_PDA/2) and round it up to next integer value. - PSU_DDRC_DRAMTMG12_T_MRD_PDA 0x8 - - SDRAM Timing Register 12 - (OFFSET, MASK, VALUE) (0XFD070130, 0x00030F1FU ,0x00020608U) - RegMask = (DDRC_DRAMTMG12_T_CMDCKE_MASK | DDRC_DRAMTMG12_T_CKEHCMD_MASK | DDRC_DRAMTMG12_T_MRD_PDA_MASK | 0 ); - - RegVal = ((0x00000002U << DDRC_DRAMTMG12_T_CMDCKE_SHIFT - | 0x00000006U << DDRC_DRAMTMG12_T_CKEHCMD_SHIFT - | 0x00000008U << DDRC_DRAMTMG12_T_MRD_PDA_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DRAMTMG12_OFFSET ,0x00030F1FU ,0x00020608U); - /*############################################################################################################################ */ - - /*Register : ZQCTL0 @ 0XFD070180

- - - 1 - Disable uMCTL2 generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used instead to is - ue ZQ calibration request from APB module. - 0 - Internally generate ZQCS/MPC(ZQ calibration) commands based on ZQCTL1.t_zq_s - ort_interval_x1024. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. - PSU_DDRC_ZQCTL0_DIS_AUTO_ZQ 0x1 - - - 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable when run in DDR3 - or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. - 0 - Enable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Power - own exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. This is only present for designs suppo - ting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. - PSU_DDRC_ZQCTL0_DIS_SRX_ZQCL 0x0 - - - 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are sent to one r - nk at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to different ranks do not ov - rlap. - 0 - ZQ resistor is not shared. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. - PSU_DDRC_ZQCTL0_ZQ_RESISTOR_SHARED 0x0 - - - 1 - Disable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode. - 0 - Enable - ssuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode. This is only present for des - gns supporting DDR4 devices. - PSU_DDRC_ZQCTL0_DIS_MPSMX_ZQCL 0x0 - - tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Number of cycles of NOP required after a ZQCL (ZQ calibrat - on long)/MPC(ZQ Start) command is issued to SDRAM. For configurations with MEMC_FREQ_RATIO=2: DDR3/DDR4: program this to tZQo - er/2 and round it up to the next integer value. LPDDR2/LPDDR3: program this to tZQCL/2 and round it up to the next integer va - ue. LPDDR4: program this to tZQCAL/2 and round it up to the next integer value. Unit: Clock cycles. This is only present for - esigns supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. - PSU_DDRC_ZQCTL0_T_ZQ_LONG_NOP 0x100 - - tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of cycles of NOP required after a ZQCS (ZQ calibration short)/MPC - ZQ Latch) command is issued to SDRAM. For configurations with MEMC_FREQ_RATIO=2, program this to tZQCS/2 and round it up to t - e next integer value. Unit: Clock cycles. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devic - s. - PSU_DDRC_ZQCTL0_T_ZQ_SHORT_NOP 0x40 - - ZQ Control Register 0 - (OFFSET, MASK, VALUE) (0XFD070180, 0xF7FF03FFU ,0x81000040U) - RegMask = (DDRC_ZQCTL0_DIS_AUTO_ZQ_MASK | DDRC_ZQCTL0_DIS_SRX_ZQCL_MASK | DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_MASK | DDRC_ZQCTL0_DIS_MPSMX_ZQCL_MASK | DDRC_ZQCTL0_T_ZQ_LONG_NOP_MASK | DDRC_ZQCTL0_T_ZQ_SHORT_NOP_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_ZQCTL0_DIS_AUTO_ZQ_SHIFT - | 0x00000000U << DDRC_ZQCTL0_DIS_SRX_ZQCL_SHIFT - | 0x00000000U << DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_SHIFT - | 0x00000000U << DDRC_ZQCTL0_DIS_MPSMX_ZQCL_SHIFT - | 0x00000100U << DDRC_ZQCTL0_T_ZQ_LONG_NOP_SHIFT - | 0x00000040U << DDRC_ZQCTL0_T_ZQ_SHORT_NOP_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_ZQCTL0_OFFSET ,0xF7FF03FFU ,0x81000040U); - /*############################################################################################################################ */ - - /*Register : ZQCTL1 @ 0XFD070184

- - tZQReset: Number of cycles of NOP required after a ZQReset (ZQ calibration Reset) command is issued to SDRAM. For configurati - ns with MEMC_FREQ_RATIO=2, program this to tZQReset/2 and round it up to the next integer value. Unit: Clock cycles. This is - nly present for designs supporting LPDDR2/LPDDR3/LPDDR4 devices. - PSU_DDRC_ZQCTL1_T_ZQ_RESET_NOP 0x20 - - Average interval to wait between automatically issuing ZQCS (ZQ calibration short)/MPC(ZQ calibration) commands to DDR3/DDR4/ - PDDR2/LPDDR3/LPDDR4 devices. Meaningless, if ZQCTL0.dis_auto_zq=1. Unit: 1024 clock cycles. This is only present for designs - upporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. - PSU_DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024 0x19707 - - ZQ Control Register 1 - (OFFSET, MASK, VALUE) (0XFD070184, 0x3FFFFFFFU ,0x02019707U) - RegMask = (DDRC_ZQCTL1_T_ZQ_RESET_NOP_MASK | DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_MASK | 0 ); - - RegVal = ((0x00000020U << DDRC_ZQCTL1_T_ZQ_RESET_NOP_SHIFT - | 0x00019707U << DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_ZQCTL1_OFFSET ,0x3FFFFFFFU ,0x02019707U); - /*############################################################################################################################ */ - - /*Register : DFITMG0 @ 0XFD070190

- - Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signa - s at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligne - , this timing parameter should be rounded up to the next integer value. Note that if using RDIMM, it is necessary to incremen - this parameter by RDIMM's extra cycle of latency in terms of DFI clock. - PSU_DDRC_DFITMG0_DFI_T_CTRL_DELAY 0x4 - - Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR or SDR values Selects whether value in DFITM - 0.dfi_t_rddata_en is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles R - fer to PHY specification for correct value. - PSU_DDRC_DFITMG0_DFI_RDDATA_USE_SDR 0x1 - - Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. Refer to PHY spe - ification for correct value. This corresponds to the DFI parameter trddata_en. Note that, depending on the PHY, if using RDIM - , it may be necessary to use the value (CL + 1) in the calculation of trddata_en. This is to compensate for the extra cycle o - latency through the RDIMM. Unit: Clocks - PSU_DDRC_DFITMG0_DFI_T_RDDATA_EN 0xb - - Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using HDR or SDR values Selects whether value in DFITMG - .dfi_tphy_wrlat is in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.dfi_tphy_wrdata is in terms of SDR or - HDR clock cycles - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles Refer to PHY specification for correct val - e. - PSU_DDRC_DFITMG0_DFI_WRDATA_USE_SDR 0x1 - - Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on th - dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. N - te, max supported value is 8. Unit: Clocks - PSU_DDRC_DFITMG0_DFI_TPHY_WRDATA 0x2 - - Write latency Number of clocks from the write command to write data enable (dfi_wrdata_en). This corresponds to the DFI timin - parameter tphy_wrlat. Refer to PHY specification for correct value.Note that, depending on the PHY, if using RDIMM, it may b - necessary to use the value (CL + 1) in the calculation of tphy_wrlat. This is to compensate for the extra cycle of latency t - rough the RDIMM. - PSU_DDRC_DFITMG0_DFI_TPHY_WRLAT 0xb - - DFI Timing Register 0 - (OFFSET, MASK, VALUE) (0XFD070190, 0x1FBFBF3FU ,0x048B820BU) - RegMask = (DDRC_DFITMG0_DFI_T_CTRL_DELAY_MASK | DDRC_DFITMG0_DFI_RDDATA_USE_SDR_MASK | DDRC_DFITMG0_DFI_T_RDDATA_EN_MASK | DDRC_DFITMG0_DFI_WRDATA_USE_SDR_MASK | DDRC_DFITMG0_DFI_TPHY_WRDATA_MASK | DDRC_DFITMG0_DFI_TPHY_WRLAT_MASK | 0 ); - - RegVal = ((0x00000004U << DDRC_DFITMG0_DFI_T_CTRL_DELAY_SHIFT - | 0x00000001U << DDRC_DFITMG0_DFI_RDDATA_USE_SDR_SHIFT - | 0x0000000BU << DDRC_DFITMG0_DFI_T_RDDATA_EN_SHIFT - | 0x00000001U << DDRC_DFITMG0_DFI_WRDATA_USE_SDR_SHIFT - | 0x00000002U << DDRC_DFITMG0_DFI_TPHY_WRDATA_SHIFT - | 0x0000000BU << DDRC_DFITMG0_DFI_TPHY_WRLAT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DFITMG0_OFFSET ,0x1FBFBF3FU ,0x048B820BU); - /*############################################################################################################################ */ - - /*Register : DFITMG1 @ 0XFD070194

- - Specifies the number of DFI PHY clocks between when the dfi_cs signal is asserted and when the associated command is driven. - his field is used for CAL mode, should be set to '0' or the value which matches the CAL mode register setting in the DRAM. If - the PHY can add the latency for CAL mode, this should be set to '0'. Valid Range: 0, 3, 4, 5, 6, and 8 - PSU_DDRC_DFITMG1_DFI_T_CMD_LAT 0x0 - - Specifies the number of DFI PHY clocks between when the dfi_cs signal is asserted and when the associated dfi_parity_in signa - is driven. - PSU_DDRC_DFITMG1_DFI_T_PARIN_LAT 0x0 - - Specifies the number of DFI clocks between when the dfi_wrdata_en signal is asserted and when the corresponding write data tr - nsfer is completed on the DRAM bus. This corresponds to the DFI timing parameter twrdata_delay. Refer to PHY specification fo - correct value. For DFI 3.0 PHY, set to twrdata_delay, a new timing parameter introduced in DFI 3.0. For DFI 2.1 PHY, set to - phy_wrdata + (delay of DFI write data to the DRAM). Value to be programmed is in terms of DFI clocks, not PHY clocks. In FREQ - RATIO=2, divide PHY's value by 2 and round up to next integer. If using DFITMG0.dfi_wrdata_use_sdr=1, add 1 to the value. Uni - : Clocks - PSU_DDRC_DFITMG1_DFI_T_WRDATA_DELAY 0x3 - - Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to - he DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase - ligned, this timing parameter should be rounded up to the next integer value. - PSU_DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE 0x3 - - Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first - alid rising edge of the clock to the DRAM memory devices, at the PHY-DRAM boundary. If the DFI clock and the memory clock are - not phase aligned, this timing parameter should be rounded up to the next integer value. - PSU_DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE 0x4 - - DFI Timing Register 1 - (OFFSET, MASK, VALUE) (0XFD070194, 0xF31F0F0FU ,0x00030304U) - RegMask = (DDRC_DFITMG1_DFI_T_CMD_LAT_MASK | DDRC_DFITMG1_DFI_T_PARIN_LAT_MASK | DDRC_DFITMG1_DFI_T_WRDATA_DELAY_MASK | DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_MASK | DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_DFITMG1_DFI_T_CMD_LAT_SHIFT - | 0x00000000U << DDRC_DFITMG1_DFI_T_PARIN_LAT_SHIFT - | 0x00000003U << DDRC_DFITMG1_DFI_T_WRDATA_DELAY_SHIFT - | 0x00000003U << DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_SHIFT - | 0x00000004U << DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DFITMG1_OFFSET ,0xF31F0F0FU ,0x00030304U); - /*############################################################################################################################ */ - - /*Register : DFILPCFG0 @ 0XFD070198

- - Setting for DFI's tlp_resp time. Same value is used for both Power Down, Self Refresh, Deep Power Down and Maximum Power Savi - g modes. DFI 2.1 specification onwards, recommends using a fixed value of 7 always. - PSU_DDRC_DFILPCFG0_DFI_TLP_RESP 0x7 - - Value to drive on dfi_lp_wakeup signal when Deep Power Down mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 - cycles - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles - 0x7 - - 2048 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0xD - - 31072 cycles - 0xE - 262144 cycles - 0xF - Unlimited This is only present for designs supporting mDDR or LPDDR2/LPDDR3 device - . - PSU_DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD 0x0 - - Enables DFI Low Power interface handshaking during Deep Power Down Entry/Exit. - 0 - Disabled - 1 - Enabled This is only pres - nt for designs supporting mDDR or LPDDR2/LPDDR3 devices. - PSU_DDRC_DFILPCFG0_DFI_LP_EN_DPD 0x0 - - Value to drive on dfi_lp_wakeup signal when Self Refresh mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cy - les - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles - 0x7 - - 048 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0xD - 131 - 72 cycles - 0xE - 262144 cycles - 0xF - Unlimited - PSU_DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR 0x0 - - Enables DFI Low Power interface handshaking during Self Refresh Entry/Exit. - 0 - Disabled - 1 - Enabled - PSU_DDRC_DFILPCFG0_DFI_LP_EN_SR 0x1 - - Value to drive on dfi_lp_wakeup signal when Power Down mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycl - s - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles - 0x7 - 20 - 8 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0xD - 13107 - cycles - 0xE - 262144 cycles - 0xF - Unlimited - PSU_DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD 0x0 - - Enables DFI Low Power interface handshaking during Power Down Entry/Exit. - 0 - Disabled - 1 - Enabled - PSU_DDRC_DFILPCFG0_DFI_LP_EN_PD 0x1 - - DFI Low Power Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD070198, 0x0FF1F1F1U ,0x07000101U) - RegMask = (DDRC_DFILPCFG0_DFI_TLP_RESP_MASK | DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_MASK | DDRC_DFILPCFG0_DFI_LP_EN_DPD_MASK | DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_MASK | DDRC_DFILPCFG0_DFI_LP_EN_SR_MASK | DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_MASK | DDRC_DFILPCFG0_DFI_LP_EN_PD_MASK | 0 ); - - RegVal = ((0x00000007U << DDRC_DFILPCFG0_DFI_TLP_RESP_SHIFT - | 0x00000000U << DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_SHIFT - | 0x00000000U << DDRC_DFILPCFG0_DFI_LP_EN_DPD_SHIFT - | 0x00000000U << DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_SHIFT - | 0x00000001U << DDRC_DFILPCFG0_DFI_LP_EN_SR_SHIFT - | 0x00000000U << DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_SHIFT - | 0x00000001U << DDRC_DFILPCFG0_DFI_LP_EN_PD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DFILPCFG0_OFFSET ,0x0FF1F1F1U ,0x07000101U); - /*############################################################################################################################ */ - - /*Register : DFILPCFG1 @ 0XFD07019C

- - Value to drive on dfi_lp_wakeup signal when Maximum Power Saving Mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - - 16 cycles - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0 - D - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited This is only present for designs supporting DDR4 devices. - PSU_DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM 0x2 - - Enables DFI Low Power interface handshaking during Maximum Power Saving Mode Entry/Exit. - 0 - Disabled - 1 - Enabled This is - only present for designs supporting DDR4 devices. - PSU_DDRC_DFILPCFG1_DFI_LP_EN_MPSM 0x1 - - DFI Low Power Configuration Register 1 - (OFFSET, MASK, VALUE) (0XFD07019C, 0x000000F1U ,0x00000021U) - RegMask = (DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_MASK | DDRC_DFILPCFG1_DFI_LP_EN_MPSM_MASK | 0 ); - - RegVal = ((0x00000002U << DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_SHIFT - | 0x00000001U << DDRC_DFILPCFG1_DFI_LP_EN_MPSM_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DFILPCFG1_OFFSET ,0x000000F1U ,0x00000021U); - /*############################################################################################################################ */ - - /*Register : DFIUPD1 @ 0XFD0701A4

- - This is the minimum amount of time between uMCTL2 initiated DFI update requests (which is executed whenever the uMCTL2 is idl - ). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the fir - t read request when the uMCTL2 is idle. Unit: 1024 clocks - PSU_DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024 0x41 - - This is the maximum amount of time between uMCTL2 initiated DFI update requests. This timer resets with each update request; - hen the timer expires dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd_ackx is received. PHY can use this - idle time to recalibrate the delay lines to the DLLs. The DFI controller update is also used to reset PHY FIFO pointers in ca - e of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. - Note: Value programmed for DFIUPD1.dfi_t_ctrlupd_interval_max_x1024 must be greater than DFIUPD1.dfi_t_ctrlupd_interval_min_x - 024. Unit: 1024 clocks - PSU_DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024 0xe2 - - DFI Update Register 1 - (OFFSET, MASK, VALUE) (0XFD0701A4, 0x00FF00FFU ,0x004100E2U) - RegMask = (DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_MASK | DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_MASK | 0 ); - - RegVal = ((0x00000041U << DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_SHIFT - | 0x000000E2U << DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DFIUPD1_OFFSET ,0x00FF00FFU ,0x004100E2U); - /*############################################################################################################################ */ - - /*Register : DFIMISC @ 0XFD0701B0

- - Defines polarity of dfi_wrdata_cs and dfi_rddata_cs signals. - 0: Signals are active low - 1: Signals are active high - PSU_DDRC_DFIMISC_DFI_DATA_CS_POLARITY 0x0 - - DBI implemented in DDRC or PHY. - 0 - DDRC implements DBI functionality. - 1 - PHY implements DBI functionality. Present only - in designs configured to support DDR4 and LPDDR4. - PSU_DDRC_DFIMISC_PHY_DBI_MODE 0x0 - - PHY initialization complete enable signal. When asserted the dfi_init_complete signal can be used to trigger SDRAM initialisa - ion - PSU_DDRC_DFIMISC_DFI_INIT_COMPLETE_EN 0x0 - - DFI Miscellaneous Control Register - (OFFSET, MASK, VALUE) (0XFD0701B0, 0x00000007U ,0x00000000U) - RegMask = (DDRC_DFIMISC_DFI_DATA_CS_POLARITY_MASK | DDRC_DFIMISC_PHY_DBI_MODE_MASK | DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_DFIMISC_DFI_DATA_CS_POLARITY_SHIFT - | 0x00000000U << DDRC_DFIMISC_PHY_DBI_MODE_SHIFT - | 0x00000000U << DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DFIMISC_OFFSET ,0x00000007U ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : DFITMG2 @ 0XFD0701B4

- - >Number of clocks between when a read command is sent on the DFI control interface and when the associated dfi_rddata_cs sign - l is asserted. This corresponds to the DFI timing parameter tphy_rdcslat. Refer to PHY specification for correct value. - PSU_DDRC_DFITMG2_DFI_TPHY_RDCSLAT 0x9 - - Number of clocks between when a write command is sent on the DFI control interface and when the associated dfi_wrdata_cs sign - l is asserted. This corresponds to the DFI timing parameter tphy_wrcslat. Refer to PHY specification for correct value. - PSU_DDRC_DFITMG2_DFI_TPHY_WRCSLAT 0x6 - - DFI Timing Register 2 - (OFFSET, MASK, VALUE) (0XFD0701B4, 0x00003F3FU ,0x00000906U) - RegMask = (DDRC_DFITMG2_DFI_TPHY_RDCSLAT_MASK | DDRC_DFITMG2_DFI_TPHY_WRCSLAT_MASK | 0 ); - - RegVal = ((0x00000009U << DDRC_DFITMG2_DFI_TPHY_RDCSLAT_SHIFT - | 0x00000006U << DDRC_DFITMG2_DFI_TPHY_WRCSLAT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DFITMG2_OFFSET ,0x00003F3FU ,0x00000906U); - /*############################################################################################################################ */ - - /*Register : DBICTL @ 0XFD0701C0

- - Read DBI enable signal in DDRC. - 0 - Read DBI is disabled. - 1 - Read DBI is enabled. This signal must be set the same value - as DRAM's mode register. - DDR4: MR5 bit A12. When x4 devices are used, this signal must be set to 0. - LPDDR4: MR3[6] - PSU_DDRC_DBICTL_RD_DBI_EN 0x0 - - Write DBI enable signal in DDRC. - 0 - Write DBI is disabled. - 1 - Write DBI is enabled. This signal must be set the same va - ue as DRAM's mode register. - DDR4: MR5 bit A11. When x4 devices are used, this signal must be set to 0. - LPDDR4: MR3[7] - PSU_DDRC_DBICTL_WR_DBI_EN 0x0 - - DM enable signal in DDRC. - 0 - DM is disabled. - 1 - DM is enabled. This signal must be set the same logical value as DRAM's - mode register. - DDR4: Set this to same value as MR5 bit A10. When x4 devices are used, this signal must be set to 0. - LPDDR - : Set this to inverted value of MR13[5] which is opposite polarity from this signal - PSU_DDRC_DBICTL_DM_EN 0x1 - - DM/DBI Control Register - (OFFSET, MASK, VALUE) (0XFD0701C0, 0x00000007U ,0x00000001U) - RegMask = (DDRC_DBICTL_RD_DBI_EN_MASK | DDRC_DBICTL_WR_DBI_EN_MASK | DDRC_DBICTL_DM_EN_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_DBICTL_RD_DBI_EN_SHIFT - | 0x00000000U << DDRC_DBICTL_WR_DBI_EN_SHIFT - | 0x00000001U << DDRC_DBICTL_DM_EN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DBICTL_OFFSET ,0x00000007U ,0x00000001U); - /*############################################################################################################################ */ - - /*Register : ADDRMAP0 @ 0XFD070200

- - Selects the HIF address bit used as rank address bit 0. Valid Range: 0 to 27, and 31 Internal Base: 6 The selected HIF addres - bit is determined by adding the internal base to the value of this field. If set to 31, rank address bit 0 is set to 0. - PSU_DDRC_ADDRMAP0_ADDRMAP_CS_BIT0 0x1f - - Address Map Register 0 - (OFFSET, MASK, VALUE) (0XFD070200, 0x0000001FU ,0x0000001FU) - RegMask = (DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_MASK | 0 ); - - RegVal = ((0x0000001FU << DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_ADDRMAP0_OFFSET ,0x0000001FU ,0x0000001FU); - /*############################################################################################################################ */ - - /*Register : ADDRMAP1 @ 0XFD070204

- - Selects the HIF address bit used as bank address bit 2. Valid Range: 0 to 29 and 31 Internal Base: 4 The selected HIF address - bit is determined by adding the internal base to the value of this field. If set to 31, bank address bit 2 is set to 0. - PSU_DDRC_ADDRMAP1_ADDRMAP_BANK_B2 0x1f - - Selects the HIF address bits used as bank address bit 1. Valid Range: 0 to 30 Internal Base: 3 The selected HIF address bit f - r each of the bank address bits is determined by adding the internal base to the value of this field. - PSU_DDRC_ADDRMAP1_ADDRMAP_BANK_B1 0xa - - Selects the HIF address bits used as bank address bit 0. Valid Range: 0 to 30 Internal Base: 2 The selected HIF address bit f - r each of the bank address bits is determined by adding the internal base to the value of this field. - PSU_DDRC_ADDRMAP1_ADDRMAP_BANK_B0 0xa - - Address Map Register 1 - (OFFSET, MASK, VALUE) (0XFD070204, 0x001F1F1FU ,0x001F0A0AU) - RegMask = (DDRC_ADDRMAP1_ADDRMAP_BANK_B2_MASK | DDRC_ADDRMAP1_ADDRMAP_BANK_B1_MASK | DDRC_ADDRMAP1_ADDRMAP_BANK_B0_MASK | 0 ); - - RegVal = ((0x0000001FU << DDRC_ADDRMAP1_ADDRMAP_BANK_B2_SHIFT - | 0x0000000AU << DDRC_ADDRMAP1_ADDRMAP_BANK_B1_SHIFT - | 0x0000000AU << DDRC_ADDRMAP1_ADDRMAP_BANK_B0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_ADDRMAP1_OFFSET ,0x001F1F1FU ,0x001F0A0AU); - /*############################################################################################################################ */ - - /*Register : ADDRMAP2 @ 0XFD070208

- - - Full bus width mode: Selects the HIF address bit used as column address bit 5. - Half bus width mode: Selects the HIF addre - s bit used as column address bit 6. - Quarter bus width mode: Selects the HIF address bit used as column address bit 7 . Vali - Range: 0 to 7, and 15 Internal Base: 5 The selected HIF address bit is determined by adding the internal base to the value o - this field. If set to 15, this column address bit is set to 0. - PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B5 0x0 - - - Full bus width mode: Selects the HIF address bit used as column address bit 4. - Half bus width mode: Selects the HIF addre - s bit used as column address bit 5. - Quarter bus width mode: Selects the HIF address bit used as column address bit 6. Valid - Range: 0 to 7, and 15 Internal Base: 4 The selected HIF address bit is determined by adding the internal base to the value of - this field. If set to 15, this column address bit is set to 0. - PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B4 0x0 - - - Full bus width mode: Selects the HIF address bit used as column address bit 3. - Half bus width mode: Selects the HIF addre - s bit used as column address bit 4. - Quarter bus width mode: Selects the HIF address bit used as column address bit 5. Valid - Range: 0 to 7 Internal Base: 3 The selected HIF address bit is determined by adding the internal base to the value of this fi - ld. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=16, it is required to program this to 0, hence register does not exist i - this case. - PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B3 0x0 - - - Full bus width mode: Selects the HIF address bit used as column address bit 2. - Half bus width mode: Selects the HIF addre - s bit used as column address bit 3. - Quarter bus width mode: Selects the HIF address bit used as column address bit 4. Valid - Range: 0 to 7 Internal Base: 2 The selected HIF address bit is determined by adding the internal base to the value of this fi - ld. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=8 or 16, it is required to program this to 0. - PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B2 0x0 - - Address Map Register 2 - (OFFSET, MASK, VALUE) (0XFD070208, 0x0F0F0F0FU ,0x00000000U) - RegMask = (DDRC_ADDRMAP2_ADDRMAP_COL_B5_MASK | DDRC_ADDRMAP2_ADDRMAP_COL_B4_MASK | DDRC_ADDRMAP2_ADDRMAP_COL_B3_MASK | DDRC_ADDRMAP2_ADDRMAP_COL_B2_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_ADDRMAP2_ADDRMAP_COL_B5_SHIFT - | 0x00000000U << DDRC_ADDRMAP2_ADDRMAP_COL_B4_SHIFT - | 0x00000000U << DDRC_ADDRMAP2_ADDRMAP_COL_B3_SHIFT - | 0x00000000U << DDRC_ADDRMAP2_ADDRMAP_COL_B2_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_ADDRMAP2_OFFSET ,0x0F0F0F0FU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : ADDRMAP3 @ 0XFD07020C

- - - Full bus width mode: Selects the HIF address bit used as column address bit 9. - Half bus width mode: Selects the HIF addre - s bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). - Quarter bus width mode: Selects the HIF address bit used as - column address bit 13 (11 in LPDDR2/LPDDR3 mode). Valid Range: 0 to 7, and 15 Internal Base: 9 The selected HIF address bit i - determined by adding the internal base to the value of this field. If set to 15, this column address bit is set to 0. Note: - er JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source addr - ss bit can be mapped to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus an - hence column bit 10 is used. - PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B9 0x0 - - - Full bus width mode: Selects the HIF address bit used as column address bit 8. - Half bus width mode: Selects the HIF addre - s bit used as column address bit 9. - Quarter bus width mode: Selects the HIF address bit used as column address bit 11 (10 i - LPDDR2/LPDDR3 mode). Valid Range: 0 to 7, and 15 Internal Base: 8 The selected HIF address bit is determined by adding the i - ternal base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specif - cation, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to col - mn address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and hence column bit 10 is use - . - PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B8 0x0 - - - Full bus width mode: Selects the HIF address bit used as column address bit 7. - Half bus width mode: Selects the HIF addre - s bit used as column address bit 8. - Quarter bus width mode: Selects the HIF address bit used as column address bit 9. Valid - Range: 0 to 7, and 15 Internal Base: 7 The selected HIF address bit is determined by adding the internal base to the value of - this field. If set to 15, this column address bit is set to 0. - PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B7 0x0 - - - Full bus width mode: Selects the HIF address bit used as column address bit 6. - Half bus width mode: Selects the HIF addre - s bit used as column address bit 7. - Quarter bus width mode: Selects the HIF address bit used as column address bit 8. Valid - Range: 0 to 7, and 15 Internal Base: 6 The selected HIF address bit is determined by adding the internal base to the value of - this field. If set to 15, this column address bit is set to 0. - PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B6 0x0 - - Address Map Register 3 - (OFFSET, MASK, VALUE) (0XFD07020C, 0x0F0F0F0FU ,0x00000000U) - RegMask = (DDRC_ADDRMAP3_ADDRMAP_COL_B9_MASK | DDRC_ADDRMAP3_ADDRMAP_COL_B8_MASK | DDRC_ADDRMAP3_ADDRMAP_COL_B7_MASK | DDRC_ADDRMAP3_ADDRMAP_COL_B6_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_ADDRMAP3_ADDRMAP_COL_B9_SHIFT - | 0x00000000U << DDRC_ADDRMAP3_ADDRMAP_COL_B8_SHIFT - | 0x00000000U << DDRC_ADDRMAP3_ADDRMAP_COL_B7_SHIFT - | 0x00000000U << DDRC_ADDRMAP3_ADDRMAP_COL_B6_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_ADDRMAP3_OFFSET ,0x0F0F0F0FU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : ADDRMAP4 @ 0XFD070210

- - - Full bus width mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode). - Half bus width - mode: Unused. To make it unused, this should be tied to 4'hF. - Quarter bus width mode: Unused. To make it unused, this must - e tied to 4'hF. Valid Range: 0 to 7, and 15 Internal Base: 11 The selected HIF address bit is determined by adding the intern - l base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specificati - n, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column a - dress bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and hence column bit 10 is used. - PSU_DDRC_ADDRMAP4_ADDRMAP_COL_B11 0xf - - - Full bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). - Half bus width - mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode). - Quarter bus width mode: UNUSED. - To make it unused, this must be tied to 4'hF. Valid Range: 0 to 7, and 15 Internal Base: 10 The selected HIF address bit is d - termined by adding the internal base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per - JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source address - bit can be mapped to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and h - nce column bit 10 is used. - PSU_DDRC_ADDRMAP4_ADDRMAP_COL_B10 0xf - - Address Map Register 4 - (OFFSET, MASK, VALUE) (0XFD070210, 0x00000F0FU ,0x00000F0FU) - RegMask = (DDRC_ADDRMAP4_ADDRMAP_COL_B11_MASK | DDRC_ADDRMAP4_ADDRMAP_COL_B10_MASK | 0 ); - - RegVal = ((0x0000000FU << DDRC_ADDRMAP4_ADDRMAP_COL_B11_SHIFT - | 0x0000000FU << DDRC_ADDRMAP4_ADDRMAP_COL_B10_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_ADDRMAP4_OFFSET ,0x00000F0FU ,0x00000F0FU); - /*############################################################################################################################ */ - - /*Register : ADDRMAP5 @ 0XFD070214

- - Selects the HIF address bit used as row address bit 11. Valid Range: 0 to 11, and 15 Internal Base: 17 The selected HIF addre - s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 11 is set to 0. - PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B11 0x8 - - Selects the HIF address bits used as row address bits 2 to 10. Valid Range: 0 to 11, and 15 Internal Base: 8 (for row address - bit 2), 9 (for row address bit 3), 10 (for row address bit 4) etc increasing to 16 (for row address bit 10) The selected HIF - ddress bit for each of the row address bits is determined by adding the internal base to the value of this field. When value - 5 is used the values of row address bits 2 to 10 are defined by registers ADDRMAP9, ADDRMAP10, ADDRMAP11. - PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10 0xf - - Selects the HIF address bits used as row address bit 1. Valid Range: 0 to 11 Internal Base: 7 The selected HIF address bit fo - each of the row address bits is determined by adding the internal base to the value of this field. - PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B1 0x8 - - Selects the HIF address bits used as row address bit 0. Valid Range: 0 to 11 Internal Base: 6 The selected HIF address bit fo - each of the row address bits is determined by adding the internal base to the value of this field. - PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B0 0x8 - - Address Map Register 5 - (OFFSET, MASK, VALUE) (0XFD070214, 0x0F0F0F0FU ,0x080F0808U) - RegMask = (DDRC_ADDRMAP5_ADDRMAP_ROW_B11_MASK | DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_MASK | DDRC_ADDRMAP5_ADDRMAP_ROW_B1_MASK | DDRC_ADDRMAP5_ADDRMAP_ROW_B0_MASK | 0 ); - - RegVal = ((0x00000008U << DDRC_ADDRMAP5_ADDRMAP_ROW_B11_SHIFT - | 0x0000000FU << DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_SHIFT - | 0x00000008U << DDRC_ADDRMAP5_ADDRMAP_ROW_B1_SHIFT - | 0x00000008U << DDRC_ADDRMAP5_ADDRMAP_ROW_B0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_ADDRMAP5_OFFSET ,0x0F0F0F0FU ,0x080F0808U); - /*############################################################################################################################ */ - - /*Register : ADDRMAP6 @ 0XFD070218

- - Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use. - 1 - LPDDR3 SDRAM 6Gb/12Gb device in use. Every address - having row[14:13]==2'b11 is considered as invalid - 0 - non-LPDDR3 6Gb/12Gb device in use. All addresses are valid Present on - y in designs configured to support LPDDR3. - PSU_DDRC_ADDRMAP6_LPDDR3_6GB_12GB 0x0 - - Selects the HIF address bit used as row address bit 15. Valid Range: 0 to 11, and 15 Internal Base: 21 The selected HIF addre - s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 15 is set to 0. - PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B15 0xf - - Selects the HIF address bit used as row address bit 14. Valid Range: 0 to 11, and 15 Internal Base: 20 The selected HIF addre - s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 14 is set to 0. - PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B14 0x8 - - Selects the HIF address bit used as row address bit 13. Valid Range: 0 to 11, and 15 Internal Base: 19 The selected HIF addre - s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 13 is set to 0. - PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B13 0x8 - - Selects the HIF address bit used as row address bit 12. Valid Range: 0 to 11, and 15 Internal Base: 18 The selected HIF addre - s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 12 is set to 0. - PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B12 0x8 - - Address Map Register 6 - (OFFSET, MASK, VALUE) (0XFD070218, 0x8F0F0F0FU ,0x0F080808U) - RegMask = (DDRC_ADDRMAP6_LPDDR3_6GB_12GB_MASK | DDRC_ADDRMAP6_ADDRMAP_ROW_B15_MASK | DDRC_ADDRMAP6_ADDRMAP_ROW_B14_MASK | DDRC_ADDRMAP6_ADDRMAP_ROW_B13_MASK | DDRC_ADDRMAP6_ADDRMAP_ROW_B12_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_ADDRMAP6_LPDDR3_6GB_12GB_SHIFT - | 0x0000000FU << DDRC_ADDRMAP6_ADDRMAP_ROW_B15_SHIFT - | 0x00000008U << DDRC_ADDRMAP6_ADDRMAP_ROW_B14_SHIFT - | 0x00000008U << DDRC_ADDRMAP6_ADDRMAP_ROW_B13_SHIFT - | 0x00000008U << DDRC_ADDRMAP6_ADDRMAP_ROW_B12_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_ADDRMAP6_OFFSET ,0x8F0F0F0FU ,0x0F080808U); - /*############################################################################################################################ */ - - /*Register : ADDRMAP7 @ 0XFD07021C

- - Selects the HIF address bit used as row address bit 17. Valid Range: 0 to 10, and 15 Internal Base: 23 The selected HIF addre - s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 17 is set to 0. - PSU_DDRC_ADDRMAP7_ADDRMAP_ROW_B17 0xf - - Selects the HIF address bit used as row address bit 16. Valid Range: 0 to 11, and 15 Internal Base: 22 The selected HIF addre - s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 16 is set to 0. - PSU_DDRC_ADDRMAP7_ADDRMAP_ROW_B16 0xf - - Address Map Register 7 - (OFFSET, MASK, VALUE) (0XFD07021C, 0x00000F0FU ,0x00000F0FU) - RegMask = (DDRC_ADDRMAP7_ADDRMAP_ROW_B17_MASK | DDRC_ADDRMAP7_ADDRMAP_ROW_B16_MASK | 0 ); - - RegVal = ((0x0000000FU << DDRC_ADDRMAP7_ADDRMAP_ROW_B17_SHIFT - | 0x0000000FU << DDRC_ADDRMAP7_ADDRMAP_ROW_B16_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_ADDRMAP7_OFFSET ,0x00000F0FU ,0x00000F0FU); - /*############################################################################################################################ */ - - /*Register : ADDRMAP8 @ 0XFD070220

- - Selects the HIF address bits used as bank group address bit 1. Valid Range: 0 to 30, and 31 Internal Base: 3 The selected HIF - address bit for each of the bank group address bits is determined by adding the internal base to the value of this field. If - et to 31, bank group address bit 1 is set to 0. - PSU_DDRC_ADDRMAP8_ADDRMAP_BG_B1 0x8 - - Selects the HIF address bits used as bank group address bit 0. Valid Range: 0 to 30 Internal Base: 2 The selected HIF address - bit for each of the bank group address bits is determined by adding the internal base to the value of this field. - PSU_DDRC_ADDRMAP8_ADDRMAP_BG_B0 0x8 - - Address Map Register 8 - (OFFSET, MASK, VALUE) (0XFD070220, 0x00001F1FU ,0x00000808U) - RegMask = (DDRC_ADDRMAP8_ADDRMAP_BG_B1_MASK | DDRC_ADDRMAP8_ADDRMAP_BG_B0_MASK | 0 ); - - RegVal = ((0x00000008U << DDRC_ADDRMAP8_ADDRMAP_BG_B1_SHIFT - | 0x00000008U << DDRC_ADDRMAP8_ADDRMAP_BG_B0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_ADDRMAP8_OFFSET ,0x00001F1FU ,0x00000808U); - /*############################################################################################################################ */ - - /*Register : ADDRMAP9 @ 0XFD070224

- - Selects the HIF address bits used as row address bit 5. Valid Range: 0 to 11 Internal Base: 11 The selected HIF address bit f - r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u - ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15. - PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B5 0x8 - - Selects the HIF address bits used as row address bit 4. Valid Range: 0 to 11 Internal Base: 10 The selected HIF address bit f - r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u - ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15. - PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B4 0x8 - - Selects the HIF address bits used as row address bit 3. Valid Range: 0 to 11 Internal Base: 9 The selected HIF address bit fo - each of the row address bits is determined by adding the internal base to the value of this field. This register field is us - d only when ADDRMAP5.addrmap_row_b2_10 is set to value 15. - PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B3 0x8 - - Selects the HIF address bits used as row address bit 2. Valid Range: 0 to 11 Internal Base: 8 The selected HIF address bit fo - each of the row address bits is determined by adding the internal base to the value of this field. This register field is us - d only when ADDRMAP5.addrmap_row_b2_10 is set to value 15. - PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B2 0x8 - - Address Map Register 9 - (OFFSET, MASK, VALUE) (0XFD070224, 0x0F0F0F0FU ,0x08080808U) - RegMask = (DDRC_ADDRMAP9_ADDRMAP_ROW_B5_MASK | DDRC_ADDRMAP9_ADDRMAP_ROW_B4_MASK | DDRC_ADDRMAP9_ADDRMAP_ROW_B3_MASK | DDRC_ADDRMAP9_ADDRMAP_ROW_B2_MASK | 0 ); - - RegVal = ((0x00000008U << DDRC_ADDRMAP9_ADDRMAP_ROW_B5_SHIFT - | 0x00000008U << DDRC_ADDRMAP9_ADDRMAP_ROW_B4_SHIFT - | 0x00000008U << DDRC_ADDRMAP9_ADDRMAP_ROW_B3_SHIFT - | 0x00000008U << DDRC_ADDRMAP9_ADDRMAP_ROW_B2_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_ADDRMAP9_OFFSET ,0x0F0F0F0FU ,0x08080808U); - /*############################################################################################################################ */ - - /*Register : ADDRMAP10 @ 0XFD070228

- - Selects the HIF address bits used as row address bit 9. Valid Range: 0 to 11 Internal Base: 15 The selected HIF address bit f - r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u - ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15. - PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B9 0x8 - - Selects the HIF address bits used as row address bit 8. Valid Range: 0 to 11 Internal Base: 14 The selected HIF address bit f - r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u - ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15. - PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B8 0x8 - - Selects the HIF address bits used as row address bit 7. Valid Range: 0 to 11 Internal Base: 13 The selected HIF address bit f - r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u - ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15. - PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B7 0x8 - - Selects the HIF address bits used as row address bit 6. Valid Range: 0 to 11 Internal Base: 12 The selected HIF address bit f - r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u - ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15. - PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B6 0x8 - - Address Map Register 10 - (OFFSET, MASK, VALUE) (0XFD070228, 0x0F0F0F0FU ,0x08080808U) - RegMask = (DDRC_ADDRMAP10_ADDRMAP_ROW_B9_MASK | DDRC_ADDRMAP10_ADDRMAP_ROW_B8_MASK | DDRC_ADDRMAP10_ADDRMAP_ROW_B7_MASK | DDRC_ADDRMAP10_ADDRMAP_ROW_B6_MASK | 0 ); - - RegVal = ((0x00000008U << DDRC_ADDRMAP10_ADDRMAP_ROW_B9_SHIFT - | 0x00000008U << DDRC_ADDRMAP10_ADDRMAP_ROW_B8_SHIFT - | 0x00000008U << DDRC_ADDRMAP10_ADDRMAP_ROW_B7_SHIFT - | 0x00000008U << DDRC_ADDRMAP10_ADDRMAP_ROW_B6_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_ADDRMAP10_OFFSET ,0x0F0F0F0FU ,0x08080808U); - /*############################################################################################################################ */ - - /*Register : ADDRMAP11 @ 0XFD07022C

- - Selects the HIF address bits used as row address bit 10. Valid Range: 0 to 11 Internal Base: 16 The selected HIF address bit - or each of the row address bits is determined by adding the internal base to the value of this field. This register field is - sed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15. - PSU_DDRC_ADDRMAP11_ADDRMAP_ROW_B10 0x8 - - Address Map Register 11 - (OFFSET, MASK, VALUE) (0XFD07022C, 0x0000000FU ,0x00000008U) - RegMask = (DDRC_ADDRMAP11_ADDRMAP_ROW_B10_MASK | 0 ); - - RegVal = ((0x00000008U << DDRC_ADDRMAP11_ADDRMAP_ROW_B10_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_ADDRMAP11_OFFSET ,0x0000000FU ,0x00000008U); - /*############################################################################################################################ */ - - /*Register : ODTCFG @ 0XFD070240

- - Cycles to hold ODT for a write command. The minimum supported value is 2. Recommended values: DDR2: - BL8: 0x5 (DDR2-400/533/ - 67), 0x6 (DDR2-800), 0x7 (DDR2-1066) - BL4: 0x3 (DDR2-400/533/667), 0x4 (DDR2-800), 0x5 (DDR2-1066) DDR3: - BL8: 0x6 DDR4: - - L8: 5 + WR_PREAMBLE + CRC_MODE WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) CRC_MODE = 0 (not CRC mode), 1 - CRC mode) LPDDR3: - BL8: 7 + RU(tODTon(max)/tCK) - PSU_DDRC_ODTCFG_WR_ODT_HOLD 0x6 - - The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting must - remain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: - CWL + AL - 3 (DDR2-400/533/ - 67), CWL + AL - 4 (DDR2-800), CWL + AL - 5 (DDR2-1066) If (CWL + AL - 3 < 0), uMCTL2 does not support ODT for write operation - DDR3: - 0x0 DDR4: - DFITMG1.dfi_t_cmd_lat (to adjust for CAL mode) LPDDR3: - WL - 1 - RU(tODTon(max)/tCK)) - PSU_DDRC_ODTCFG_WR_ODT_DELAY 0x0 - - Cycles to hold ODT for a read command. The minimum supported value is 2. Recommended values: DDR2: - BL8: 0x6 (not DDR2-1066) - 0x7 (DDR2-1066) - BL4: 0x4 (not DDR2-1066), 0x5 (DDR2-1066) DDR3: - BL8 - 0x6 DDR4: - BL8: 5 + RD_PREAMBLE RD_PREAMBLE = 1 ( - tCK write preamble), 2 (2tCK write preamble) LPDDR3: - BL8: 5 + RU(tDQSCK(max)/tCK) - RD(tDQSCK(min)/tCK) + RU(tODTon(max)/tC - ) - PSU_DDRC_ODTCFG_RD_ODT_HOLD 0x6 - - The delay, in clock cycles, from issuing a read command to setting ODT values associated with that command. ODT setting must - emain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: - CL + AL - 4 (not DDR2-1066), - CL + AL - 5 (DDR2-1066) If (CL + AL - 4 < 0), uMCTL2 does not support ODT for read operation. DDR3: - CL - CWL DDR4: - CL - C - L - RD_PREAMBLE + WR_PREAMBLE + DFITMG1.dfi_t_cmd_lat (to adjust for CAL mode) WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK - write preamble) RD_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) If (CL - CWL - RD_PREAMBLE + WR_PREAMBLE) < 0, - uMCTL2 does not support ODT for read operation. LPDDR3: - RL + RD(tDQSCK(min)/tCK) - 1 - RU(tODTon(max)/tCK) - PSU_DDRC_ODTCFG_RD_ODT_DELAY 0x0 - - ODT Configuration Register - (OFFSET, MASK, VALUE) (0XFD070240, 0x0F1F0F7CU ,0x06000600U) - RegMask = (DDRC_ODTCFG_WR_ODT_HOLD_MASK | DDRC_ODTCFG_WR_ODT_DELAY_MASK | DDRC_ODTCFG_RD_ODT_HOLD_MASK | DDRC_ODTCFG_RD_ODT_DELAY_MASK | 0 ); - - RegVal = ((0x00000006U << DDRC_ODTCFG_WR_ODT_HOLD_SHIFT - | 0x00000000U << DDRC_ODTCFG_WR_ODT_DELAY_SHIFT - | 0x00000006U << DDRC_ODTCFG_RD_ODT_HOLD_SHIFT - | 0x00000000U << DDRC_ODTCFG_RD_ODT_DELAY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_ODTCFG_OFFSET ,0x0F1F0F7CU ,0x06000600U); - /*############################################################################################################################ */ - - /*Register : ODTMAP @ 0XFD070244

- - Indicates which remote ODTs must be turned on during a read from rank 1. Each rank has a remote ODT (in the SDRAM) which can - e turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB - etc. For each rank, set its bit to 1 to enable its ODT. Present only in configurations that have 2 or more ranks - PSU_DDRC_ODTMAP_RANK1_RD_ODT 0x0 - - Indicates which remote ODTs must be turned on during a write to rank 1. Each rank has a remote ODT (in the SDRAM) which can b - turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB, - etc. For each rank, set its bit to 1 to enable its ODT. Present only in configurations that have 2 or more ranks - PSU_DDRC_ODTMAP_RANK1_WR_ODT 0x0 - - Indicates which remote ODTs must be turned on during a read from rank 0. Each rank has a remote ODT (in the SDRAM) which can - e turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB - etc. For each rank, set its bit to 1 to enable its ODT. - PSU_DDRC_ODTMAP_RANK0_RD_ODT 0x0 - - Indicates which remote ODTs must be turned on during a write to rank 0. Each rank has a remote ODT (in the SDRAM) which can b - turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB, - etc. For each rank, set its bit to 1 to enable its ODT. - PSU_DDRC_ODTMAP_RANK0_WR_ODT 0x1 - - ODT/Rank Map Register - (OFFSET, MASK, VALUE) (0XFD070244, 0x00003333U ,0x00000001U) - RegMask = (DDRC_ODTMAP_RANK1_RD_ODT_MASK | DDRC_ODTMAP_RANK1_WR_ODT_MASK | DDRC_ODTMAP_RANK0_RD_ODT_MASK | DDRC_ODTMAP_RANK0_WR_ODT_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_ODTMAP_RANK1_RD_ODT_SHIFT - | 0x00000000U << DDRC_ODTMAP_RANK1_WR_ODT_SHIFT - | 0x00000000U << DDRC_ODTMAP_RANK0_RD_ODT_SHIFT - | 0x00000001U << DDRC_ODTMAP_RANK0_WR_ODT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_ODTMAP_OFFSET ,0x00003333U ,0x00000001U); - /*############################################################################################################################ */ - - /*Register : SCHED @ 0XFD070250

- - When the preferred transaction store is empty for these many clock cycles, switch to the alternate transaction store if it is - non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write t - ansaction store is the alternative store. When prefer write over read is set this is reversed. 0x0 is a legal value for this - egister. When set to 0x0, the transaction store switching will happen immediately when the switching conditions become true. - OR PERFORMANCE ONLY - PSU_DDRC_SCHED_RDWR_IDLE_GAP 0x1 - - UNUSED - PSU_DDRC_SCHED_GO2CRITICAL_HYSTERESIS 0x0 - - Number of entries in the low priority transaction store is this value + 1. (MEMC_NO_OF_ENTRY - (SCHED.lpr_num_entries + 1)) i - the number of entries available for the high priority transaction store. Setting this to maximum value allocates all entries - to low priority transaction store. Setting this to 0 allocates 1 entry to low priority transaction store and the rest to high - priority transaction store. Note: In ECC configurations, the numbers of write and low priority read credits issued is one les - than in the non-ECC case. One entry each is reserved in the write and low-priority read CAMs for storing the RMW requests ar - sing out of single bit error correction RMW operation. - PSU_DDRC_SCHED_LPR_NUM_ENTRIES 0x20 - - If true, bank is kept open only while there are page hit transactions available in the CAM to that bank. The last read or wri - e command in the CAM with a bank and page hit will be executed with auto-precharge if SCHED1.pageclose_timer=0. Even if this - egister set to 1 and SCHED1.pageclose_timer is set to 0, explicit precharge (and not auto-precharge) may be issued in some ca - es where there is a mode switch between Write and Read or between LPR and HPR. The Read and Write commands that are executed - s part of the ECC scrub requests are also executed without auto-precharge. If false, the bank remains open until there is a n - ed to close it (to open a different page, or for page timeout or refresh timeout) - also known as open page policy. The open - age policy can be overridden by setting the per-command-autopre bit on the HIF interface (hif_cmd_autopre). The pageclose fea - ure provids a midway between Open and Close page policies. FOR PERFORMANCE ONLY. - PSU_DDRC_SCHED_PAGECLOSE 0x0 - - If set then the bank selector prefers writes over reads. FOR DEBUG ONLY. - PSU_DDRC_SCHED_PREFER_WRITE 0x0 - - Active low signal. When asserted ('0'), all incoming transactions are forced to low priority. This implies that all High Prio - ity Read (HPR) and Variable Priority Read commands (VPR) will be treated as Low Priority Read (LPR) commands. On the write si - e, all Variable Priority Write (VPW) commands will be treated as Normal Priority Write (NPW) commands. Forcing the incoming t - ansactions to low priority implicitly turns off Bypass path for read commands. FOR PERFORMANCE ONLY. - PSU_DDRC_SCHED_FORCE_LOW_PRI_N 0x1 - - Scheduler Control Register - (OFFSET, MASK, VALUE) (0XFD070250, 0x7FFF3F07U ,0x01002001U) - RegMask = (DDRC_SCHED_RDWR_IDLE_GAP_MASK | DDRC_SCHED_GO2CRITICAL_HYSTERESIS_MASK | DDRC_SCHED_LPR_NUM_ENTRIES_MASK | DDRC_SCHED_PAGECLOSE_MASK | DDRC_SCHED_PREFER_WRITE_MASK | DDRC_SCHED_FORCE_LOW_PRI_N_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_SCHED_RDWR_IDLE_GAP_SHIFT - | 0x00000000U << DDRC_SCHED_GO2CRITICAL_HYSTERESIS_SHIFT - | 0x00000020U << DDRC_SCHED_LPR_NUM_ENTRIES_SHIFT - | 0x00000000U << DDRC_SCHED_PAGECLOSE_SHIFT - | 0x00000000U << DDRC_SCHED_PREFER_WRITE_SHIFT - | 0x00000001U << DDRC_SCHED_FORCE_LOW_PRI_N_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_SCHED_OFFSET ,0x7FFF3F07U ,0x01002001U); - /*############################################################################################################################ */ - - /*Register : PERFLPR1 @ 0XFD070264

- - Number of transactions that are serviced once the LPR queue goes critical is the smaller of: - (a) This number - (b) Number o - transactions available. Unit: Transaction. FOR PERFORMANCE ONLY. - PSU_DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH 0x8 - - Number of clocks that the LPR queue can be starved before it goes critical. The minimum valid functional value for this regis - er is 0x1. Programming it to 0x0 will disable the starvation functionality; during normal operation, this function should not - be disabled as it will cause excessive latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY. - PSU_DDRC_PERFLPR1_LPR_MAX_STARVE 0x40 - - Low Priority Read CAM Register 1 - (OFFSET, MASK, VALUE) (0XFD070264, 0xFF00FFFFU ,0x08000040U) - RegMask = (DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_MASK | DDRC_PERFLPR1_LPR_MAX_STARVE_MASK | 0 ); - - RegVal = ((0x00000008U << DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_SHIFT - | 0x00000040U << DDRC_PERFLPR1_LPR_MAX_STARVE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PERFLPR1_OFFSET ,0xFF00FFFFU ,0x08000040U); - /*############################################################################################################################ */ - - /*Register : PERFWR1 @ 0XFD07026C

- - Number of transactions that are serviced once the WR queue goes critical is the smaller of: - (a) This number - (b) Number of - transactions available. Unit: Transaction. FOR PERFORMANCE ONLY. - PSU_DDRC_PERFWR1_W_XACT_RUN_LENGTH 0x8 - - Number of clocks that the WR queue can be starved before it goes critical. The minimum valid functional value for this regist - r is 0x1. Programming it to 0x0 will disable the starvation functionality; during normal operation, this function should not - e disabled as it will cause excessive latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY. - PSU_DDRC_PERFWR1_W_MAX_STARVE 0x40 - - Write CAM Register 1 - (OFFSET, MASK, VALUE) (0XFD07026C, 0xFF00FFFFU ,0x08000040U) - RegMask = (DDRC_PERFWR1_W_XACT_RUN_LENGTH_MASK | DDRC_PERFWR1_W_MAX_STARVE_MASK | 0 ); - - RegVal = ((0x00000008U << DDRC_PERFWR1_W_XACT_RUN_LENGTH_SHIFT - | 0x00000040U << DDRC_PERFWR1_W_MAX_STARVE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PERFWR1_OFFSET ,0xFF00FFFFU ,0x08000040U); - /*############################################################################################################################ */ - - /*Register : DQMAP5 @ 0XFD070294

- - All even ranks have the same DQ mapping controled by DQMAP0-4 register as rank 0. This register provides DQ swap function for - all odd ranks to support CRC feature. rank based DQ swapping is: swap bit 0 with 1, swap bit 2 with 3, swap bit 4 with 5 and - wap bit 6 with 7. 1: Disable rank based DQ swapping 0: Enable rank based DQ swapping Present only in designs configured to su - port DDR4. - PSU_DDRC_DQMAP5_DIS_DQ_RANK_SWAP 0x1 - - DQ Map Register 5 - (OFFSET, MASK, VALUE) (0XFD070294, 0x00000001U ,0x00000001U) - RegMask = (DDRC_DQMAP5_DIS_DQ_RANK_SWAP_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_DQMAP5_DIS_DQ_RANK_SWAP_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DQMAP5_OFFSET ,0x00000001U ,0x00000001U); - /*############################################################################################################################ */ - - /*Register : DBG0 @ 0XFD070300

- - When this is set to '0', auto-precharge is disabled for the flushed command in a collision case. Collision cases are write fo - lowed by read to same address, read followed by write to same address, or write followed by write to same address with DBG0.d - s_wc bit = 1 (where same address comparisons exclude the two address bits representing critical word). FOR DEBUG ONLY. - PSU_DDRC_DBG0_DIS_COLLISION_PAGE_OPT 0x0 - - When 1, disable write combine. FOR DEBUG ONLY - PSU_DDRC_DBG0_DIS_WC 0x0 - - Debug Register 0 - (OFFSET, MASK, VALUE) (0XFD070300, 0x00000011U ,0x00000000U) - RegMask = (DDRC_DBG0_DIS_COLLISION_PAGE_OPT_MASK | DDRC_DBG0_DIS_WC_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_DBG0_DIS_COLLISION_PAGE_OPT_SHIFT - | 0x00000000U << DDRC_DBG0_DIS_WC_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DBG0_OFFSET ,0x00000011U ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : DBGCMD @ 0XFD07030C

- - Setting this register bit to 1 allows refresh and ZQCS commands to be triggered from hardware via the IOs ext_*. If set to 1, - the fields DBGCMD.zq_calib_short and DBGCMD.rank*_refresh have no function, and are ignored by the uMCTL2 logic. Setting this - register bit to 0 allows refresh and ZQCS to be triggered from software, via the fields DBGCMD.zq_calib_short and DBGCMD.rank - _refresh. If set to 0, the hardware pins ext_* have no function, and are ignored by the uMCTL2 logic. This register is static - and may only be changed when the DDRC reset signal, core_ddrc_rstn, is asserted (0). - PSU_DDRC_DBGCMD_HW_REF_ZQ_EN 0x0 - - Setting this register bit to 1 indicates to the uMCTL2 to issue a dfi_ctrlupd_req to the PHY. When this request is stored in - he uMCTL2, the bit is automatically cleared. This operation must only be performed when DFIUPD0.dis_auto_ctrlupd=1. - PSU_DDRC_DBGCMD_CTRLUPD 0x0 - - Setting this register bit to 1 indicates to the uMCTL2 to issue a ZQCS (ZQ calibration short)/MPC(ZQ calibration) command to - he SDRAM. When this request is stored in the uMCTL2, the bit is automatically cleared. This operation can be performed only w - en ZQCTL0.dis_auto_zq=1. It is recommended NOT to set this register bit if in Init operating mode. This register bit is ignor - d when in Self-Refresh(except LPDDR4) and SR-Powerdown(LPDDR4) and Deep power-down operating modes and Maximum Power Saving M - de. - PSU_DDRC_DBGCMD_ZQ_CALIB_SHORT 0x0 - - Setting this register bit to 1 indicates to the uMCTL2 to issue a refresh to rank 1. Writing to this bit causes DBGSTAT.rank1 - refresh_busy to be set. When DBGSTAT.rank1_refresh_busy is cleared, the command has been stored in uMCTL2. This operation can - be performed only when RFSHCTL3.dis_auto_refresh=1. It is recommended NOT to set this register bit if in Init or Deep power-d - wn operating modes or Maximum Power Saving Mode. - PSU_DDRC_DBGCMD_RANK1_REFRESH 0x0 - - Setting this register bit to 1 indicates to the uMCTL2 to issue a refresh to rank 0. Writing to this bit causes DBGSTAT.rank0 - refresh_busy to be set. When DBGSTAT.rank0_refresh_busy is cleared, the command has been stored in uMCTL2. This operation can - be performed only when RFSHCTL3.dis_auto_refresh=1. It is recommended NOT to set this register bit if in Init or Deep power-d - wn operating modes or Maximum Power Saving Mode. - PSU_DDRC_DBGCMD_RANK0_REFRESH 0x0 - - Command Debug Register - (OFFSET, MASK, VALUE) (0XFD07030C, 0x80000033U ,0x00000000U) - RegMask = (DDRC_DBGCMD_HW_REF_ZQ_EN_MASK | DDRC_DBGCMD_CTRLUPD_MASK | DDRC_DBGCMD_ZQ_CALIB_SHORT_MASK | DDRC_DBGCMD_RANK1_REFRESH_MASK | DDRC_DBGCMD_RANK0_REFRESH_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_DBGCMD_HW_REF_ZQ_EN_SHIFT - | 0x00000000U << DDRC_DBGCMD_CTRLUPD_SHIFT - | 0x00000000U << DDRC_DBGCMD_ZQ_CALIB_SHORT_SHIFT - | 0x00000000U << DDRC_DBGCMD_RANK1_REFRESH_SHIFT - | 0x00000000U << DDRC_DBGCMD_RANK0_REFRESH_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DBGCMD_OFFSET ,0x80000033U ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : SWCTL @ 0XFD070320

- - Enable quasi-dynamic register programming outside reset. Program register to 0 to enable quasi-dynamic programming. Set back - egister to 1 once programming is done. - PSU_DDRC_SWCTL_SW_DONE 0x0 - - Software register programming control enable - (OFFSET, MASK, VALUE) (0XFD070320, 0x00000001U ,0x00000000U) - RegMask = (DDRC_SWCTL_SW_DONE_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_SWCTL_SW_DONE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_SWCTL_OFFSET ,0x00000001U ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : PCCFG @ 0XFD070400

- - Burst length expansion mode. By default (i.e. bl_exp_mode==0) XPI expands every AXI burst into multiple HIF commands, using t - e memory burst length as a unit. If set to 1, then XPI will use half of the memory burst length as a unit. This applies to bo - h reads and writes. When MSTR.data_bus_width==00, setting bl_exp_mode to 1 has no effect. This can be used in cases where Par - ial Writes is enabled (UMCTL2_PARTIAL_WR=1) and DBG0.dis_wc=1, in order to avoid or minimize t_ccd_l penalty in DDR4 and t_cc - _mw penalty in LPDDR4. Note that if DBICTL.reg_ddrc_dm_en=0, functionality is not supported in the following cases: - UMCTL2_ - ARTIAL_WR=0 - UMCTL2_PARTIAL_WR=1, MSTR.reg_ddrc_data_bus_width=01, MEMC_BURST_LENGTH=8 and MSTR.reg_ddrc_burst_rdwr=1000 (LP - DR4 only) - UMCTL2_PARTIAL_WR=1, MSTR.reg_ddrc_data_bus_width=01, MEMC_BURST_LENGTH=4 and MSTR.reg_ddrc_burst_rdwr=0100 (DDR4 - only), with either MSTR.reg_ddrc_burstchop=0 or CRCPARCTL1.reg_ddrc_crc_enable=1 Functionality is also not supported if Share - -AC is enabled - PSU_DDRC_PCCFG_BL_EXP_MODE 0x0 - - Page match four limit. If set to 1, limits the number of consecutive same page DDRC transactions that can be granted by the P - rt Arbiter to four when Page Match feature is enabled. If set to 0, there is no limit imposed on number of consecutive same p - ge DDRC transactions. - PSU_DDRC_PCCFG_PAGEMATCH_LIMIT 0x0 - - If set to 1 (enabled), sets co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals going to DDRC based - n urgent input (awurgent, arurgent) coming from AXI master. If set to 0 (disabled), co_gs_go2critical_wr and co_gs_go2critica - _lpr/co_gs_go2critical_hpr signals at DDRC are driven to 1b'0. - PSU_DDRC_PCCFG_GO2CRITICAL_EN 0x1 - - Port Common Configuration Register - (OFFSET, MASK, VALUE) (0XFD070400, 0x00000111U ,0x00000001U) - RegMask = (DDRC_PCCFG_BL_EXP_MODE_MASK | DDRC_PCCFG_PAGEMATCH_LIMIT_MASK | DDRC_PCCFG_GO2CRITICAL_EN_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_PCCFG_BL_EXP_MODE_SHIFT - | 0x00000000U << DDRC_PCCFG_PAGEMATCH_LIMIT_SHIFT - | 0x00000001U << DDRC_PCCFG_GO2CRITICAL_EN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCCFG_OFFSET ,0x00000111U ,0x00000001U); - /*############################################################################################################################ */ - - /*Register : PCFGR_0 @ 0XFD070404

- - If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register. - PSU_DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN 0x0 - - If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG. - o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add - ess handshaking (it is not associated with any particular command). - PSU_DDRC_PCFGR_0_RD_PORT_URGENT_EN 0x1 - - If set to 1, enables aging function for the read channel of the port. - PSU_DDRC_PCFGR_0_RD_PORT_AGING_EN 0x0 - - Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g - ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority - will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre - ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the - aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st - ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w - ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D - RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: - he two LSBs of this register field are tied internally to 2'b00. - PSU_DDRC_PCFGR_0_RD_PORT_PRIORITY 0xf - - Port n Configuration Read Register - (OFFSET, MASK, VALUE) (0XFD070404, 0x000073FFU ,0x0000200FU) - RegMask = (DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGR_0_RD_PORT_URGENT_EN_MASK | DDRC_PCFGR_0_RD_PORT_AGING_EN_MASK | DDRC_PCFGR_0_RD_PORT_PRIORITY_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_SHIFT - | 0x00000001U << DDRC_PCFGR_0_RD_PORT_URGENT_EN_SHIFT - | 0x00000000U << DDRC_PCFGR_0_RD_PORT_AGING_EN_SHIFT - | 0x0000000FU << DDRC_PCFGR_0_RD_PORT_PRIORITY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGR_0_OFFSET ,0x000073FFU ,0x0000200FU); - /*############################################################################################################################ */ - - /*Register : PCFGW_0 @ 0XFD070408

- - If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register. - PSU_DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN 0x1 - - If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register - Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is - not associated with any particular command). - PSU_DDRC_PCFGW_0_WR_PORT_URGENT_EN 0x1 - - If set to 1, enables aging function for the write channel of the port. - PSU_DDRC_PCFGW_0_WR_PORT_AGING_EN 0x0 - - Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each - rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port - s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0 - the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno - be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For - ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch - ng. Note: The two LSBs of this register field are tied internally to 2'b00. - PSU_DDRC_PCFGW_0_WR_PORT_PRIORITY 0xf - - Port n Configuration Write Register - (OFFSET, MASK, VALUE) (0XFD070408, 0x000073FFU ,0x0000600FU) - RegMask = (DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGW_0_WR_PORT_URGENT_EN_MASK | DDRC_PCFGW_0_WR_PORT_AGING_EN_MASK | DDRC_PCFGW_0_WR_PORT_PRIORITY_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_SHIFT - | 0x00000001U << DDRC_PCFGW_0_WR_PORT_URGENT_EN_SHIFT - | 0x00000000U << DDRC_PCFGW_0_WR_PORT_AGING_EN_SHIFT - | 0x0000000FU << DDRC_PCFGW_0_WR_PORT_PRIORITY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGW_0_OFFSET ,0x000073FFU ,0x0000600FU); - /*############################################################################################################################ */ - - /*Register : PCTRL_0 @ 0XFD070490

- - Enables port n. - PSU_DDRC_PCTRL_0_PORT_EN 0x1 - - Port n Control Register - (OFFSET, MASK, VALUE) (0XFD070490, 0x00000001U ,0x00000001U) - RegMask = (DDRC_PCTRL_0_PORT_EN_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_PCTRL_0_PORT_EN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCTRL_0_OFFSET ,0x00000001U ,0x00000001U); - /*############################################################################################################################ */ - - /*Register : PCFGQOS0_0 @ 0XFD070494

- - This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf - gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is - disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. - PSU_DDRC_PCFGQOS0_0_RQOS_MAP_REGION1 0x2 - - This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi - urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i - disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. - PSU_DDRC_PCFGQOS0_0_RQOS_MAP_REGION0 0x0 - - Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d - al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio - ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc - values. - PSU_DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1 0xb - - Port n Read QoS Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD070494, 0x0033000FU ,0x0020000BU) - RegMask = (DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_MASK | DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_MASK | DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_MASK | 0 ); - - RegVal = ((0x00000002U << DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_SHIFT - | 0x00000000U << DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_SHIFT - | 0x0000000BU << DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGQOS0_0_OFFSET ,0x0033000FU ,0x0020000BU); - /*############################################################################################################################ */ - - /*Register : PCFGQOS1_0 @ 0XFD070498

- - Specifies the timeout value for transactions mapped to the red address queue. - PSU_DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR 0x0 - - Specifies the timeout value for transactions mapped to the blue address queue. - PSU_DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB 0x0 - - Port n Read QoS Configuration Register 1 - (OFFSET, MASK, VALUE) (0XFD070498, 0x07FF07FFU ,0x00000000U) - RegMask = (DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_MASK | DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_SHIFT - | 0x00000000U << DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGQOS1_0_OFFSET ,0x07FF07FFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : PCFGR_1 @ 0XFD0704B4

- - If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register. - PSU_DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN 0x0 - - If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG. - o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add - ess handshaking (it is not associated with any particular command). - PSU_DDRC_PCFGR_1_RD_PORT_URGENT_EN 0x1 - - If set to 1, enables aging function for the read channel of the port. - PSU_DDRC_PCFGR_1_RD_PORT_AGING_EN 0x0 - - Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g - ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority - will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre - ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the - aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st - ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w - ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D - RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: - he two LSBs of this register field are tied internally to 2'b00. - PSU_DDRC_PCFGR_1_RD_PORT_PRIORITY 0xf - - Port n Configuration Read Register - (OFFSET, MASK, VALUE) (0XFD0704B4, 0x000073FFU ,0x0000200FU) - RegMask = (DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGR_1_RD_PORT_URGENT_EN_MASK | DDRC_PCFGR_1_RD_PORT_AGING_EN_MASK | DDRC_PCFGR_1_RD_PORT_PRIORITY_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_SHIFT - | 0x00000001U << DDRC_PCFGR_1_RD_PORT_URGENT_EN_SHIFT - | 0x00000000U << DDRC_PCFGR_1_RD_PORT_AGING_EN_SHIFT - | 0x0000000FU << DDRC_PCFGR_1_RD_PORT_PRIORITY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGR_1_OFFSET ,0x000073FFU ,0x0000200FU); - /*############################################################################################################################ */ - - /*Register : PCFGW_1 @ 0XFD0704B8

- - If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register. - PSU_DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN 0x1 - - If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register - Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is - not associated with any particular command). - PSU_DDRC_PCFGW_1_WR_PORT_URGENT_EN 0x1 - - If set to 1, enables aging function for the write channel of the port. - PSU_DDRC_PCFGW_1_WR_PORT_AGING_EN 0x0 - - Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each - rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port - s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0 - the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno - be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For - ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch - ng. Note: The two LSBs of this register field are tied internally to 2'b00. - PSU_DDRC_PCFGW_1_WR_PORT_PRIORITY 0xf - - Port n Configuration Write Register - (OFFSET, MASK, VALUE) (0XFD0704B8, 0x000073FFU ,0x0000600FU) - RegMask = (DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGW_1_WR_PORT_URGENT_EN_MASK | DDRC_PCFGW_1_WR_PORT_AGING_EN_MASK | DDRC_PCFGW_1_WR_PORT_PRIORITY_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_SHIFT - | 0x00000001U << DDRC_PCFGW_1_WR_PORT_URGENT_EN_SHIFT - | 0x00000000U << DDRC_PCFGW_1_WR_PORT_AGING_EN_SHIFT - | 0x0000000FU << DDRC_PCFGW_1_WR_PORT_PRIORITY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGW_1_OFFSET ,0x000073FFU ,0x0000600FU); - /*############################################################################################################################ */ - - /*Register : PCTRL_1 @ 0XFD070540

- - Enables port n. - PSU_DDRC_PCTRL_1_PORT_EN 0x1 - - Port n Control Register - (OFFSET, MASK, VALUE) (0XFD070540, 0x00000001U ,0x00000001U) - RegMask = (DDRC_PCTRL_1_PORT_EN_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_PCTRL_1_PORT_EN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCTRL_1_OFFSET ,0x00000001U ,0x00000001U); - /*############################################################################################################################ */ - - /*Register : PCFGQOS0_1 @ 0XFD070544

- - This bitfield indicates the traffic class of region2. For dual address queue configurations, region2 maps to the red address - ueue. Valid values are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and traffic class of region2 - s set to 1 (VPR), VPR traffic is aliased to LPR traffic. - PSU_DDRC_PCFGQOS0_1_RQOS_MAP_REGION2 0x2 - - This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf - gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is - disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. - PSU_DDRC_PCFGQOS0_1_RQOS_MAP_REGION1 0x0 - - This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi - urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i - disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. - PSU_DDRC_PCFGQOS0_1_RQOS_MAP_REGION0 0x0 - - Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (le - el1 + 1) to 14 which corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note that for PA, arqos values are used - directly as port priorities, where the higher the value corresponds to higher port priority. All of the map_level* registers - ust be set to distinct values. - PSU_DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2 0xb - - Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d - al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio - ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc - values. - PSU_DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1 0x3 - - Port n Read QoS Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD070544, 0x03330F0FU ,0x02000B03U) - RegMask = (DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_MASK | DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_MASK | DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_MASK | DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_MASK | DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_MASK | 0 ); - - RegVal = ((0x00000002U << DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_SHIFT - | 0x00000000U << DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_SHIFT - | 0x00000000U << DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_SHIFT - | 0x0000000BU << DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_SHIFT - | 0x00000003U << DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGQOS0_1_OFFSET ,0x03330F0FU ,0x02000B03U); - /*############################################################################################################################ */ - - /*Register : PCFGQOS1_1 @ 0XFD070548

- - Specifies the timeout value for transactions mapped to the red address queue. - PSU_DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR 0x0 - - Specifies the timeout value for transactions mapped to the blue address queue. - PSU_DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB 0x0 - - Port n Read QoS Configuration Register 1 - (OFFSET, MASK, VALUE) (0XFD070548, 0x07FF07FFU ,0x00000000U) - RegMask = (DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_MASK | DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_SHIFT - | 0x00000000U << DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGQOS1_1_OFFSET ,0x07FF07FFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : PCFGR_2 @ 0XFD070564

- - If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register. - PSU_DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN 0x0 - - If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG. - o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add - ess handshaking (it is not associated with any particular command). - PSU_DDRC_PCFGR_2_RD_PORT_URGENT_EN 0x1 - - If set to 1, enables aging function for the read channel of the port. - PSU_DDRC_PCFGR_2_RD_PORT_AGING_EN 0x0 - - Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g - ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority - will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre - ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the - aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st - ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w - ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D - RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: - he two LSBs of this register field are tied internally to 2'b00. - PSU_DDRC_PCFGR_2_RD_PORT_PRIORITY 0xf - - Port n Configuration Read Register - (OFFSET, MASK, VALUE) (0XFD070564, 0x000073FFU ,0x0000200FU) - RegMask = (DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGR_2_RD_PORT_URGENT_EN_MASK | DDRC_PCFGR_2_RD_PORT_AGING_EN_MASK | DDRC_PCFGR_2_RD_PORT_PRIORITY_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_SHIFT - | 0x00000001U << DDRC_PCFGR_2_RD_PORT_URGENT_EN_SHIFT - | 0x00000000U << DDRC_PCFGR_2_RD_PORT_AGING_EN_SHIFT - | 0x0000000FU << DDRC_PCFGR_2_RD_PORT_PRIORITY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGR_2_OFFSET ,0x000073FFU ,0x0000200FU); - /*############################################################################################################################ */ - - /*Register : PCFGW_2 @ 0XFD070568

- - If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register. - PSU_DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN 0x1 - - If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register - Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is - not associated with any particular command). - PSU_DDRC_PCFGW_2_WR_PORT_URGENT_EN 0x1 - - If set to 1, enables aging function for the write channel of the port. - PSU_DDRC_PCFGW_2_WR_PORT_AGING_EN 0x0 - - Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each - rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port - s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0 - the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno - be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For - ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch - ng. Note: The two LSBs of this register field are tied internally to 2'b00. - PSU_DDRC_PCFGW_2_WR_PORT_PRIORITY 0xf - - Port n Configuration Write Register - (OFFSET, MASK, VALUE) (0XFD070568, 0x000073FFU ,0x0000600FU) - RegMask = (DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGW_2_WR_PORT_URGENT_EN_MASK | DDRC_PCFGW_2_WR_PORT_AGING_EN_MASK | DDRC_PCFGW_2_WR_PORT_PRIORITY_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_SHIFT - | 0x00000001U << DDRC_PCFGW_2_WR_PORT_URGENT_EN_SHIFT - | 0x00000000U << DDRC_PCFGW_2_WR_PORT_AGING_EN_SHIFT - | 0x0000000FU << DDRC_PCFGW_2_WR_PORT_PRIORITY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGW_2_OFFSET ,0x000073FFU ,0x0000600FU); - /*############################################################################################################################ */ - - /*Register : PCTRL_2 @ 0XFD0705F0

- - Enables port n. - PSU_DDRC_PCTRL_2_PORT_EN 0x1 - - Port n Control Register - (OFFSET, MASK, VALUE) (0XFD0705F0, 0x00000001U ,0x00000001U) - RegMask = (DDRC_PCTRL_2_PORT_EN_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_PCTRL_2_PORT_EN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCTRL_2_OFFSET ,0x00000001U ,0x00000001U); - /*############################################################################################################################ */ - - /*Register : PCFGQOS0_2 @ 0XFD0705F4

- - This bitfield indicates the traffic class of region2. For dual address queue configurations, region2 maps to the red address - ueue. Valid values are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and traffic class of region2 - s set to 1 (VPR), VPR traffic is aliased to LPR traffic. - PSU_DDRC_PCFGQOS0_2_RQOS_MAP_REGION2 0x2 - - This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf - gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is - disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. - PSU_DDRC_PCFGQOS0_2_RQOS_MAP_REGION1 0x0 - - This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi - urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i - disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. - PSU_DDRC_PCFGQOS0_2_RQOS_MAP_REGION0 0x0 - - Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (le - el1 + 1) to 14 which corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note that for PA, arqos values are used - directly as port priorities, where the higher the value corresponds to higher port priority. All of the map_level* registers - ust be set to distinct values. - PSU_DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2 0xb - - Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d - al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio - ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc - values. - PSU_DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1 0x3 - - Port n Read QoS Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD0705F4, 0x03330F0FU ,0x02000B03U) - RegMask = (DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_MASK | DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_MASK | DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_MASK | DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_MASK | DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_MASK | 0 ); - - RegVal = ((0x00000002U << DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_SHIFT - | 0x00000000U << DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_SHIFT - | 0x00000000U << DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_SHIFT - | 0x0000000BU << DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_SHIFT - | 0x00000003U << DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGQOS0_2_OFFSET ,0x03330F0FU ,0x02000B03U); - /*############################################################################################################################ */ - - /*Register : PCFGQOS1_2 @ 0XFD0705F8

- - Specifies the timeout value for transactions mapped to the red address queue. - PSU_DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR 0x0 - - Specifies the timeout value for transactions mapped to the blue address queue. - PSU_DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB 0x0 - - Port n Read QoS Configuration Register 1 - (OFFSET, MASK, VALUE) (0XFD0705F8, 0x07FF07FFU ,0x00000000U) - RegMask = (DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_MASK | DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_SHIFT - | 0x00000000U << DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGQOS1_2_OFFSET ,0x07FF07FFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : PCFGR_3 @ 0XFD070614

- - If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register. - PSU_DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN 0x0 - - If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG. - o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add - ess handshaking (it is not associated with any particular command). - PSU_DDRC_PCFGR_3_RD_PORT_URGENT_EN 0x1 - - If set to 1, enables aging function for the read channel of the port. - PSU_DDRC_PCFGR_3_RD_PORT_AGING_EN 0x0 - - Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g - ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority - will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre - ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the - aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st - ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w - ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D - RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: - he two LSBs of this register field are tied internally to 2'b00. - PSU_DDRC_PCFGR_3_RD_PORT_PRIORITY 0xf - - Port n Configuration Read Register - (OFFSET, MASK, VALUE) (0XFD070614, 0x000073FFU ,0x0000200FU) - RegMask = (DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGR_3_RD_PORT_URGENT_EN_MASK | DDRC_PCFGR_3_RD_PORT_AGING_EN_MASK | DDRC_PCFGR_3_RD_PORT_PRIORITY_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_SHIFT - | 0x00000001U << DDRC_PCFGR_3_RD_PORT_URGENT_EN_SHIFT - | 0x00000000U << DDRC_PCFGR_3_RD_PORT_AGING_EN_SHIFT - | 0x0000000FU << DDRC_PCFGR_3_RD_PORT_PRIORITY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGR_3_OFFSET ,0x000073FFU ,0x0000200FU); - /*############################################################################################################################ */ - - /*Register : PCFGW_3 @ 0XFD070618

- - If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register. - PSU_DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN 0x1 - - If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register - Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is - not associated with any particular command). - PSU_DDRC_PCFGW_3_WR_PORT_URGENT_EN 0x1 - - If set to 1, enables aging function for the write channel of the port. - PSU_DDRC_PCFGW_3_WR_PORT_AGING_EN 0x0 - - Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each - rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port - s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0 - the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno - be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For - ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch - ng. Note: The two LSBs of this register field are tied internally to 2'b00. - PSU_DDRC_PCFGW_3_WR_PORT_PRIORITY 0xf - - Port n Configuration Write Register - (OFFSET, MASK, VALUE) (0XFD070618, 0x000073FFU ,0x0000600FU) - RegMask = (DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGW_3_WR_PORT_URGENT_EN_MASK | DDRC_PCFGW_3_WR_PORT_AGING_EN_MASK | DDRC_PCFGW_3_WR_PORT_PRIORITY_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_SHIFT - | 0x00000001U << DDRC_PCFGW_3_WR_PORT_URGENT_EN_SHIFT - | 0x00000000U << DDRC_PCFGW_3_WR_PORT_AGING_EN_SHIFT - | 0x0000000FU << DDRC_PCFGW_3_WR_PORT_PRIORITY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGW_3_OFFSET ,0x000073FFU ,0x0000600FU); - /*############################################################################################################################ */ - - /*Register : PCTRL_3 @ 0XFD0706A0

- - Enables port n. - PSU_DDRC_PCTRL_3_PORT_EN 0x1 - - Port n Control Register - (OFFSET, MASK, VALUE) (0XFD0706A0, 0x00000001U ,0x00000001U) - RegMask = (DDRC_PCTRL_3_PORT_EN_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_PCTRL_3_PORT_EN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCTRL_3_OFFSET ,0x00000001U ,0x00000001U); - /*############################################################################################################################ */ - - /*Register : PCFGQOS0_3 @ 0XFD0706A4

- - This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf - gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is - disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. - PSU_DDRC_PCFGQOS0_3_RQOS_MAP_REGION1 0x1 - - This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi - urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i - disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. - PSU_DDRC_PCFGQOS0_3_RQOS_MAP_REGION0 0x0 - - Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d - al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio - ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc - values. - PSU_DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1 0x3 - - Port n Read QoS Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD0706A4, 0x0033000FU ,0x00100003U) - RegMask = (DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_MASK | DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_MASK | DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_SHIFT - | 0x00000000U << DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_SHIFT - | 0x00000003U << DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGQOS0_3_OFFSET ,0x0033000FU ,0x00100003U); - /*############################################################################################################################ */ - - /*Register : PCFGQOS1_3 @ 0XFD0706A8

- - Specifies the timeout value for transactions mapped to the red address queue. - PSU_DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR 0x0 - - Specifies the timeout value for transactions mapped to the blue address queue. - PSU_DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB 0x4f - - Port n Read QoS Configuration Register 1 - (OFFSET, MASK, VALUE) (0XFD0706A8, 0x07FF07FFU ,0x0000004FU) - RegMask = (DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_MASK | DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_SHIFT - | 0x0000004FU << DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGQOS1_3_OFFSET ,0x07FF07FFU ,0x0000004FU); - /*############################################################################################################################ */ - - /*Register : PCFGWQOS0_3 @ 0XFD0706AC

- - This bitfield indicates the traffic class of region 1. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2 - VPW_EN = 0) and traffic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW traffic. - PSU_DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1 0x1 - - This bitfield indicates the traffic class of region 0. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2 - VPW_EN = 0) and traffic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW traffic. - PSU_DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0 0x0 - - Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 14 which c - rresponds to awqos. Note that for PA, awqos values are used directly as port priorities, where the higher the value correspon - s to higher port priority. - PSU_DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL 0x3 - - Port n Write QoS Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD0706AC, 0x0033000FU ,0x00100003U) - RegMask = (DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_MASK | DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_MASK | DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_SHIFT - | 0x00000000U << DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_SHIFT - | 0x00000003U << DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGWQOS0_3_OFFSET ,0x0033000FU ,0x00100003U); - /*############################################################################################################################ */ - - /*Register : PCFGWQOS1_3 @ 0XFD0706B0

- - Specifies the timeout value for write transactions. - PSU_DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT 0x4f - - Port n Write QoS Configuration Register 1 - (OFFSET, MASK, VALUE) (0XFD0706B0, 0x000007FFU ,0x0000004FU) - RegMask = (DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_MASK | 0 ); - - RegVal = ((0x0000004FU << DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGWQOS1_3_OFFSET ,0x000007FFU ,0x0000004FU); - /*############################################################################################################################ */ - - /*Register : PCFGR_4 @ 0XFD0706C4

- - If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register. - PSU_DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN 0x1 - - If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG. - o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add - ess handshaking (it is not associated with any particular command). - PSU_DDRC_PCFGR_4_RD_PORT_URGENT_EN 0x1 - - If set to 1, enables aging function for the read channel of the port. - PSU_DDRC_PCFGR_4_RD_PORT_AGING_EN 0x0 - - Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g - ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority - will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre - ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the - aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st - ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w - ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D - RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: - he two LSBs of this register field are tied internally to 2'b00. - PSU_DDRC_PCFGR_4_RD_PORT_PRIORITY 0xf - - Port n Configuration Read Register - (OFFSET, MASK, VALUE) (0XFD0706C4, 0x000073FFU ,0x0000600FU) - RegMask = (DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGR_4_RD_PORT_URGENT_EN_MASK | DDRC_PCFGR_4_RD_PORT_AGING_EN_MASK | DDRC_PCFGR_4_RD_PORT_PRIORITY_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_SHIFT - | 0x00000001U << DDRC_PCFGR_4_RD_PORT_URGENT_EN_SHIFT - | 0x00000000U << DDRC_PCFGR_4_RD_PORT_AGING_EN_SHIFT - | 0x0000000FU << DDRC_PCFGR_4_RD_PORT_PRIORITY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGR_4_OFFSET ,0x000073FFU ,0x0000600FU); - /*############################################################################################################################ */ - - /*Register : PCFGW_4 @ 0XFD0706C8

- - If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register. - PSU_DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN 0x1 - - If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register - Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is - not associated with any particular command). - PSU_DDRC_PCFGW_4_WR_PORT_URGENT_EN 0x1 - - If set to 1, enables aging function for the write channel of the port. - PSU_DDRC_PCFGW_4_WR_PORT_AGING_EN 0x0 - - Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each - rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port - s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0 - the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno - be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For - ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch - ng. Note: The two LSBs of this register field are tied internally to 2'b00. - PSU_DDRC_PCFGW_4_WR_PORT_PRIORITY 0xf - - Port n Configuration Write Register - (OFFSET, MASK, VALUE) (0XFD0706C8, 0x000073FFU ,0x0000600FU) - RegMask = (DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGW_4_WR_PORT_URGENT_EN_MASK | DDRC_PCFGW_4_WR_PORT_AGING_EN_MASK | DDRC_PCFGW_4_WR_PORT_PRIORITY_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_SHIFT - | 0x00000001U << DDRC_PCFGW_4_WR_PORT_URGENT_EN_SHIFT - | 0x00000000U << DDRC_PCFGW_4_WR_PORT_AGING_EN_SHIFT - | 0x0000000FU << DDRC_PCFGW_4_WR_PORT_PRIORITY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGW_4_OFFSET ,0x000073FFU ,0x0000600FU); - /*############################################################################################################################ */ - - /*Register : PCTRL_4 @ 0XFD070750

- - Enables port n. - PSU_DDRC_PCTRL_4_PORT_EN 0x1 - - Port n Control Register - (OFFSET, MASK, VALUE) (0XFD070750, 0x00000001U ,0x00000001U) - RegMask = (DDRC_PCTRL_4_PORT_EN_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_PCTRL_4_PORT_EN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCTRL_4_OFFSET ,0x00000001U ,0x00000001U); - /*############################################################################################################################ */ - - /*Register : PCFGQOS0_4 @ 0XFD070754

- - This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf - gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is - disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. - PSU_DDRC_PCFGQOS0_4_RQOS_MAP_REGION1 0x1 - - This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi - urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i - disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. - PSU_DDRC_PCFGQOS0_4_RQOS_MAP_REGION0 0x0 - - Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d - al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio - ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc - values. - PSU_DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1 0x3 - - Port n Read QoS Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD070754, 0x0033000FU ,0x00100003U) - RegMask = (DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_MASK | DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_MASK | DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_SHIFT - | 0x00000000U << DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_SHIFT - | 0x00000003U << DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGQOS0_4_OFFSET ,0x0033000FU ,0x00100003U); - /*############################################################################################################################ */ - - /*Register : PCFGQOS1_4 @ 0XFD070758

- - Specifies the timeout value for transactions mapped to the red address queue. - PSU_DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR 0x0 - - Specifies the timeout value for transactions mapped to the blue address queue. - PSU_DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB 0x4f - - Port n Read QoS Configuration Register 1 - (OFFSET, MASK, VALUE) (0XFD070758, 0x07FF07FFU ,0x0000004FU) - RegMask = (DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_MASK | DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_SHIFT - | 0x0000004FU << DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGQOS1_4_OFFSET ,0x07FF07FFU ,0x0000004FU); - /*############################################################################################################################ */ - - /*Register : PCFGWQOS0_4 @ 0XFD07075C

- - This bitfield indicates the traffic class of region 1. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2 - VPW_EN = 0) and traffic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW traffic. - PSU_DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1 0x1 - - This bitfield indicates the traffic class of region 0. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2 - VPW_EN = 0) and traffic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW traffic. - PSU_DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0 0x0 - - Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 14 which c - rresponds to awqos. Note that for PA, awqos values are used directly as port priorities, where the higher the value correspon - s to higher port priority. - PSU_DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL 0x3 - - Port n Write QoS Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD07075C, 0x0033000FU ,0x00100003U) - RegMask = (DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_MASK | DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_MASK | DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_SHIFT - | 0x00000000U << DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_SHIFT - | 0x00000003U << DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGWQOS0_4_OFFSET ,0x0033000FU ,0x00100003U); - /*############################################################################################################################ */ - - /*Register : PCFGWQOS1_4 @ 0XFD070760

- - Specifies the timeout value for write transactions. - PSU_DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT 0x4f - - Port n Write QoS Configuration Register 1 - (OFFSET, MASK, VALUE) (0XFD070760, 0x000007FFU ,0x0000004FU) - RegMask = (DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_MASK | 0 ); - - RegVal = ((0x0000004FU << DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGWQOS1_4_OFFSET ,0x000007FFU ,0x0000004FU); - /*############################################################################################################################ */ - - /*Register : PCFGR_5 @ 0XFD070774

- - If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register. - PSU_DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN 0x0 - - If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG. - o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add - ess handshaking (it is not associated with any particular command). - PSU_DDRC_PCFGR_5_RD_PORT_URGENT_EN 0x1 - - If set to 1, enables aging function for the read channel of the port. - PSU_DDRC_PCFGR_5_RD_PORT_AGING_EN 0x0 - - Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g - ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority - will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre - ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the - aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st - ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w - ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D - RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: - he two LSBs of this register field are tied internally to 2'b00. - PSU_DDRC_PCFGR_5_RD_PORT_PRIORITY 0xf - - Port n Configuration Read Register - (OFFSET, MASK, VALUE) (0XFD070774, 0x000073FFU ,0x0000200FU) - RegMask = (DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGR_5_RD_PORT_URGENT_EN_MASK | DDRC_PCFGR_5_RD_PORT_AGING_EN_MASK | DDRC_PCFGR_5_RD_PORT_PRIORITY_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_SHIFT - | 0x00000001U << DDRC_PCFGR_5_RD_PORT_URGENT_EN_SHIFT - | 0x00000000U << DDRC_PCFGR_5_RD_PORT_AGING_EN_SHIFT - | 0x0000000FU << DDRC_PCFGR_5_RD_PORT_PRIORITY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGR_5_OFFSET ,0x000073FFU ,0x0000200FU); - /*############################################################################################################################ */ - - /*Register : PCFGW_5 @ 0XFD070778

- - If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register. - PSU_DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN 0x1 - - If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register - Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is - not associated with any particular command). - PSU_DDRC_PCFGW_5_WR_PORT_URGENT_EN 0x1 - - If set to 1, enables aging function for the write channel of the port. - PSU_DDRC_PCFGW_5_WR_PORT_AGING_EN 0x0 - - Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each - rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port - s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0 - the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno - be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For - ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch - ng. Note: The two LSBs of this register field are tied internally to 2'b00. - PSU_DDRC_PCFGW_5_WR_PORT_PRIORITY 0xf - - Port n Configuration Write Register - (OFFSET, MASK, VALUE) (0XFD070778, 0x000073FFU ,0x0000600FU) - RegMask = (DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGW_5_WR_PORT_URGENT_EN_MASK | DDRC_PCFGW_5_WR_PORT_AGING_EN_MASK | DDRC_PCFGW_5_WR_PORT_PRIORITY_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_SHIFT - | 0x00000001U << DDRC_PCFGW_5_WR_PORT_URGENT_EN_SHIFT - | 0x00000000U << DDRC_PCFGW_5_WR_PORT_AGING_EN_SHIFT - | 0x0000000FU << DDRC_PCFGW_5_WR_PORT_PRIORITY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGW_5_OFFSET ,0x000073FFU ,0x0000600FU); - /*############################################################################################################################ */ - - /*Register : PCTRL_5 @ 0XFD070800

- - Enables port n. - PSU_DDRC_PCTRL_5_PORT_EN 0x1 - - Port n Control Register - (OFFSET, MASK, VALUE) (0XFD070800, 0x00000001U ,0x00000001U) - RegMask = (DDRC_PCTRL_5_PORT_EN_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_PCTRL_5_PORT_EN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCTRL_5_OFFSET ,0x00000001U ,0x00000001U); - /*############################################################################################################################ */ - - /*Register : PCFGQOS0_5 @ 0XFD070804

- - This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf - gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is - disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. - PSU_DDRC_PCFGQOS0_5_RQOS_MAP_REGION1 0x1 - - This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi - urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i - disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic. - PSU_DDRC_PCFGQOS0_5_RQOS_MAP_REGION0 0x0 - - Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d - al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio - ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc - values. - PSU_DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1 0x3 - - Port n Read QoS Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD070804, 0x0033000FU ,0x00100003U) - RegMask = (DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_MASK | DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_MASK | DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_SHIFT - | 0x00000000U << DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_SHIFT - | 0x00000003U << DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGQOS0_5_OFFSET ,0x0033000FU ,0x00100003U); - /*############################################################################################################################ */ - - /*Register : PCFGQOS1_5 @ 0XFD070808

- - Specifies the timeout value for transactions mapped to the red address queue. - PSU_DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR 0x0 - - Specifies the timeout value for transactions mapped to the blue address queue. - PSU_DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB 0x4f - - Port n Read QoS Configuration Register 1 - (OFFSET, MASK, VALUE) (0XFD070808, 0x07FF07FFU ,0x0000004FU) - RegMask = (DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_MASK | DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_SHIFT - | 0x0000004FU << DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGQOS1_5_OFFSET ,0x07FF07FFU ,0x0000004FU); - /*############################################################################################################################ */ - - /*Register : PCFGWQOS0_5 @ 0XFD07080C

- - This bitfield indicates the traffic class of region 1. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2 - VPW_EN = 0) and traffic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW traffic. - PSU_DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1 0x1 - - This bitfield indicates the traffic class of region 0. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2 - VPW_EN = 0) and traffic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW traffic. - PSU_DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0 0x0 - - Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 14 which c - rresponds to awqos. Note that for PA, awqos values are used directly as port priorities, where the higher the value correspon - s to higher port priority. - PSU_DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL 0x3 - - Port n Write QoS Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD07080C, 0x0033000FU ,0x00100003U) - RegMask = (DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_MASK | DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_MASK | DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_MASK | 0 ); - - RegVal = ((0x00000001U << DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_SHIFT - | 0x00000000U << DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_SHIFT - | 0x00000003U << DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGWQOS0_5_OFFSET ,0x0033000FU ,0x00100003U); - /*############################################################################################################################ */ - - /*Register : PCFGWQOS1_5 @ 0XFD070810

- - Specifies the timeout value for write transactions. - PSU_DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT 0x4f - - Port n Write QoS Configuration Register 1 - (OFFSET, MASK, VALUE) (0XFD070810, 0x000007FFU ,0x0000004FU) - RegMask = (DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_MASK | 0 ); - - RegVal = ((0x0000004FU << DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_PCFGWQOS1_5_OFFSET ,0x000007FFU ,0x0000004FU); - /*############################################################################################################################ */ - - /*Register : SARBASE0 @ 0XFD070F04

- - Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x] and araddr[UMCTL2_A_ADDRW-1:x] where x is determine - by the minimum block size parameter UMCTL2_SARMINSIZE: (x=log2(block size)). - PSU_DDRC_SARBASE0_BASE_ADDR 0x0 - - SAR Base Address Register n - (OFFSET, MASK, VALUE) (0XFD070F04, 0x000001FFU ,0x00000000U) - RegMask = (DDRC_SARBASE0_BASE_ADDR_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_SARBASE0_BASE_ADDR_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_SARBASE0_OFFSET ,0x000001FFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : SARSIZE0 @ 0XFD070F08

- - Number of blocks for address region n. This register determines the total size of the region in multiples of minimum block si - e as specified by the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded as number of blocks = nblocks + 1. - or example, if register is programmed to 0, region will have 1 block. - PSU_DDRC_SARSIZE0_NBLOCKS 0x0 - - SAR Size Register n - (OFFSET, MASK, VALUE) (0XFD070F08, 0x000000FFU ,0x00000000U) - RegMask = (DDRC_SARSIZE0_NBLOCKS_MASK | 0 ); - - RegVal = ((0x00000000U << DDRC_SARSIZE0_NBLOCKS_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_SARSIZE0_OFFSET ,0x000000FFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : SARBASE1 @ 0XFD070F0C

- - Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x] and araddr[UMCTL2_A_ADDRW-1:x] where x is determine - by the minimum block size parameter UMCTL2_SARMINSIZE: (x=log2(block size)). - PSU_DDRC_SARBASE1_BASE_ADDR 0x10 - - SAR Base Address Register n - (OFFSET, MASK, VALUE) (0XFD070F0C, 0x000001FFU ,0x00000010U) - RegMask = (DDRC_SARBASE1_BASE_ADDR_MASK | 0 ); - - RegVal = ((0x00000010U << DDRC_SARBASE1_BASE_ADDR_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_SARBASE1_OFFSET ,0x000001FFU ,0x00000010U); - /*############################################################################################################################ */ - - /*Register : SARSIZE1 @ 0XFD070F10

- - Number of blocks for address region n. This register determines the total size of the region in multiples of minimum block si - e as specified by the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded as number of blocks = nblocks + 1. - or example, if register is programmed to 0, region will have 1 block. - PSU_DDRC_SARSIZE1_NBLOCKS 0xf - - SAR Size Register n - (OFFSET, MASK, VALUE) (0XFD070F10, 0x000000FFU ,0x0000000FU) - RegMask = (DDRC_SARSIZE1_NBLOCKS_MASK | 0 ); +unsigned long psu_ddr_init_data(void) +{ + /* + * DDR INITIALIZATION + */ + /* + * DDR CONTROLLER RESET + */ + /* + * Register : RST_DDR_SS @ 0XFD1A0108 + + * DDR block level reset inside of the DDR Sub System + * PSU_CRF_APB_RST_DDR_SS_DDR_RESET 0X1 + + * DDR sub system block level reset + * (OFFSET, MASK, VALUE) (0XFD1A0108, 0x00000008U ,0x00000008U) + */ + PSU_Mask_Write(CRF_APB_RST_DDR_SS_OFFSET, 0x00000008U, 0x00000008U); +/*##################################################################### */ + + /* + * Register : MSTR @ 0XFD070000 + + * Indicates the configuration of the device used in the system. - 00 - x4 + * device - 01 - x8 device - 10 - x16 device - 11 - x32 device + * PSU_DDRC_MSTR_DEVICE_CONFIG 0x1 + + * Choose which registers are used. - 0 - Original registers - 1 - Shadow r + * egisters + * PSU_DDRC_MSTR_FREQUENCY_MODE 0x0 + + * Only present for multi-rank configurations. Each bit represents one rank + * . For two-rank configurations, only bits[25:24] are present. - 1 - popul + * ated - 0 - unpopulated LSB is the lowest rank number. For 2 ranks follow + * ing combinations are legal: - 01 - One rank - 11 - Two ranks - Others - + * Reserved. For 4 ranks following combinations are legal: - 0001 - One ran + * k - 0011 - Two ranks - 1111 - Four ranks + * PSU_DDRC_MSTR_ACTIVE_RANKS 0x1 + + * SDRAM burst length used: - 0001 - Burst length of 2 (only supported for + * mDDR) - 0010 - Burst length of 4 - 0100 - Burst length of 8 - 1000 - Bur + * st length of 16 (only supported for mDDR, LPDDR2, and LPDDR4) All other + * values are reserved. This controls the burst size used to access the SDR + * AM. This must match the burst length mode register setting in the SDRAM. + * (For BC4/8 on-the-fly mode of DDR3 and DDR4, set this field to 0x0100) + * Burst length of 2 is not supported with AXI ports when MEMC_BURST_LENGTH + * is 8. Burst length of 2 is only supported with MEMC_FREQ_RATIO = 1 + * PSU_DDRC_MSTR_BURST_RDWR 0x4 + + * Set to 1 when the uMCTL2 and DRAM has to be put in DLL-off mode for low + * frequency operation. Set to 0 to put uMCTL2 and DRAM in DLL-on mode for + * normal frequency operation. If DDR4 CRC/parity retry is enabled (CRCPARC + * TL1.crc_parity_retry_enable = 1), dll_off_mode is not supported, and thi + * s bit must be set to '0'. + * PSU_DDRC_MSTR_DLL_OFF_MODE 0x0 + + * Selects proportion of DQ bus width that is used by the SDRAM - 00 - Full + * DQ bus width to SDRAM - 01 - Half DQ bus width to SDRAM - 10 - Quarter + * DQ bus width to SDRAM - 11 - Reserved. Note that half bus width mode is + * only supported when the SDRAM bus width is a multiple of 16, and quarter + * bus width mode is only supported when the SDRAM bus width is a multiple + * of 32 and the configuration parameter MEMC_QBUS_SUPPORT is set. Bus wid + * th refers to DQ bus width (excluding any ECC width). + * PSU_DDRC_MSTR_DATA_BUS_WIDTH 0x0 + + * 1 indicates put the DRAM in geardown mode (2N) and 0 indicates put the D + * RAM in normal mode (1N). This register can be changed, only when the Con + * troller is in self-refresh mode. This signal must be set the same value + * as MR3 bit A3. Note: Geardown mode is not supported if the configuration + * parameter MEMC_CMD_RTN2IDLE is set + * PSU_DDRC_MSTR_GEARDOWN_MODE 0x0 + + * If 1, then uMCTL2 uses 2T timing. Otherwise, uses 1T timing. In 2T timin + * g, all command signals (except chip select) are held for 2 clocks on the + * SDRAM bus. Chip select is asserted on the second cycle of the command N + * ote: 2T timing is not supported in LPDDR2/LPDDR3/LPDDR4 mode Note: 2T ti + * ming is not supported if the configuration parameter MEMC_CMD_RTN2IDLE i + * s set Note: 2T timing is not supported in DDR4 geardown mode. + * PSU_DDRC_MSTR_EN_2T_TIMING_MODE 0x0 + + * When set, enable burst-chop in DDR3/DDR4. Burst Chop for Reads is exerci + * sed only in HIF configurations (UMCTL2_INCL_ARB not set) and if in full + * bus width mode (MSTR.data_bus_width = 00). Burst Chop for Writes is exer + * cised only if Partial Writes enabled (UMCTL2_PARTIAL_WR=1) and if CRC is + * disabled (CRCPARCTL1.crc_enable = 0). If DDR4 CRC/parity retry is enabl + * ed (CRCPARCTL1.crc_parity_retry_enable = 1), burst chop is not supported + * , and this bit must be set to '0' + * PSU_DDRC_MSTR_BURSTCHOP 0x0 + + * Select LPDDR4 SDRAM - 1 - LPDDR4 SDRAM device in use. - 0 - non-LPDDR4 d + * evice in use Present only in designs configured to support LPDDR4. + * PSU_DDRC_MSTR_LPDDR4 0x0 + + * Select DDR4 SDRAM - 1 - DDR4 SDRAM device in use. - 0 - non-DDR4 device + * in use Present only in designs configured to support DDR4. + * PSU_DDRC_MSTR_DDR4 0x1 + + * Select LPDDR3 SDRAM - 1 - LPDDR3 SDRAM device in use. - 0 - non-LPDDR3 d + * evice in use Present only in designs configured to support LPDDR3. + * PSU_DDRC_MSTR_LPDDR3 0x0 + + * Select LPDDR2 SDRAM - 1 - LPDDR2 SDRAM device in use. - 0 - non-LPDDR2 d + * evice in use Present only in designs configured to support LPDDR2. + * PSU_DDRC_MSTR_LPDDR2 0x0 + + * Select DDR3 SDRAM - 1 - DDR3 SDRAM device in use - 0 - non-DDR3 SDRAM de + * vice in use Only present in designs that support DDR3. + * PSU_DDRC_MSTR_DDR3 0x0 + + * Master Register + * (OFFSET, MASK, VALUE) (0XFD070000, 0xE30FBE3DU ,0x41040010U) + */ + PSU_Mask_Write(DDRC_MSTR_OFFSET, 0xE30FBE3DU, 0x41040010U); +/*##################################################################### */ + + /* + * Register : MRCTRL0 @ 0XFD070010 + + * Setting this register bit to 1 triggers a mode register read or write op + * eration. When the MR operation is complete, the uMCTL2 automatically cle + * ars this bit. The other register fields of this register must be written + * in a separate APB transaction, before setting this mr_wr bit. It is rec + * ommended NOT to set this signal if in Init, Deep power-down or MPSM oper + * ating modes. + * PSU_DDRC_MRCTRL0_MR_WR 0x0 + + * Address of the mode register that is to be written to. - 0000 - MR0 - 00 + * 01 - MR1 - 0010 - MR2 - 0011 - MR3 - 0100 - MR4 - 0101 - MR5 - 0110 - MR + * 6 - 0111 - MR7 Don't Care for LPDDR2/LPDDR3/LPDDR4 (see MRCTRL1.mr_data + * for mode register addressing in LPDDR2/LPDDR3/LPDDR4) This signal is als + * o used for writing to control words of RDIMMs. In that case, it correspo + * nds to the bank address bits sent to the RDIMM In case of DDR4, the bit[ + * 3:2] corresponds to the bank group bits. Therefore, the bit[3] as well a + * s the bit[2:0] must be set to an appropriate value which is considered b + * oth the Address Mirroring of UDIMMs/RDIMMs and the Output Inversion of R + * DIMMs. + * PSU_DDRC_MRCTRL0_MR_ADDR 0x0 + + * Controls which rank is accessed by MRCTRL0.mr_wr. Normally, it is desire + * d to access all ranks, so all bits should be set to 1. However, for mult + * i-rank UDIMMs/RDIMMs which implement address mirroring, it may be necess + * ary to access ranks individually. Examples (assume uMCTL2 is configured + * for 4 ranks): - 0x1 - select rank 0 only - 0x2 - select rank 1 only - 0x + * 5 - select ranks 0 and 2 - 0xA - select ranks 1 and 3 - 0xF - select ran + * ks 0, 1, 2 and 3 + * PSU_DDRC_MRCTRL0_MR_RANK 0x3 + + * Indicates whether Software intervention is allowed via MRCTRL0/MRCTRL1 b + * efore automatic SDRAM initialization routine or not. For DDR4, this bit + * can be used to initialize the DDR4 RCD (MR7) before automatic SDRAM init + * ialization. For LPDDR4, this bit can be used to program additional mode + * registers before automatic SDRAM initialization if necessary. Note: This + * must be cleared to 0 after completing Software operation. Otherwise, SD + * RAM initialization routine will not re-start. - 0 - Software interventio + * n is not allowed - 1 - Software intervention is allowed + * PSU_DDRC_MRCTRL0_SW_INIT_INT 0x0 + + * Indicates whether the mode register operation is MRS in PDA mode or not + * - 0 - MRS - 1 - MRS in Per DRAM Addressability mode + * PSU_DDRC_MRCTRL0_PDA_EN 0x0 + + * Indicates whether the mode register operation is MRS or WR/RD for MPR (o + * nly supported for DDR4) - 0 - MRS - 1 - WR/RD for MPR + * PSU_DDRC_MRCTRL0_MPR_EN 0x0 + + * Indicates whether the mode register operation is read or write. Only use + * d for LPDDR2/LPDDR3/LPDDR4/DDR4. - 0 - Write - 1 - Read + * PSU_DDRC_MRCTRL0_MR_TYPE 0x0 + + * Mode Register Read/Write Control Register 0. Note: Do not enable more th + * an one of the following fields simultaneously: - sw_init_int - pda_en - + * mpr_en + * (OFFSET, MASK, VALUE) (0XFD070010, 0x8000F03FU ,0x00000030U) + */ + PSU_Mask_Write(DDRC_MRCTRL0_OFFSET, 0x8000F03FU, 0x00000030U); +/*##################################################################### */ + + /* + * Register : DERATEEN @ 0XFD070020 + + * Derate value of tRC for LPDDR4 - 0 - Derating uses +1. - 1 - Derating us + * es +2. - 2 - Derating uses +3. - 3 - Derating uses +4. Present only in d + * esigns configured to support LPDDR4. The required number of cycles for d + * erating can be determined by dividing 3.75ns by the core_ddrc_core_clk p + * eriod, and rounding up the next integer. + * PSU_DDRC_DERATEEN_RC_DERATE_VALUE 0x2 + + * Derate byte Present only in designs configured to support LPDDR2/LPDDR3/ + * LPDDR4 Indicates which byte of the MRR data is used for derating. The ma + * ximum valid value depends on MEMC_DRAM_TOTAL_DATA_WIDTH. + * PSU_DDRC_DERATEEN_DERATE_BYTE 0x0 + + * Derate value - 0 - Derating uses +1. - 1 - Derating uses +2. Present onl + * y in designs configured to support LPDDR2/LPDDR3/LPDDR4 Set to 0 for all + * LPDDR2 speed grades as derating value of +1.875 ns is less than a core_ + * ddrc_core_clk period. Can be 0 or 1 for LPDDR3/LPDDR4, depending if +1.8 + * 75 ns is less than a core_ddrc_core_clk period or not. + * PSU_DDRC_DERATEEN_DERATE_VALUE 0x0 + + * Enables derating - 0 - Timing parameter derating is disabled - 1 - Timin + * g parameter derating is enabled using MR4 read value. Present only in de + * signs configured to support LPDDR2/LPDDR3/LPDDR4 This field must be set + * to '0' for non-LPDDR2/LPDDR3/LPDDR4 mode. + * PSU_DDRC_DERATEEN_DERATE_ENABLE 0x0 + + * Temperature Derate Enable Register + * (OFFSET, MASK, VALUE) (0XFD070020, 0x000003F3U ,0x00000200U) + */ + PSU_Mask_Write(DDRC_DERATEEN_OFFSET, 0x000003F3U, 0x00000200U); +/*##################################################################### */ + + /* + * Register : DERATEINT @ 0XFD070024 + + * Interval between two MR4 reads, used to derate the timing parameters. Pr + * esent only in designs configured to support LPDDR2/LPDDR3/LPDDR4. This r + * egister must not be set to zero + * PSU_DDRC_DERATEINT_MR4_READ_INTERVAL 0x800000 + + * Temperature Derate Interval Register + * (OFFSET, MASK, VALUE) (0XFD070024, 0xFFFFFFFFU ,0x00800000U) + */ + PSU_Mask_Write(DDRC_DERATEINT_OFFSET, 0xFFFFFFFFU, 0x00800000U); +/*##################################################################### */ + + /* + * Register : PWRCTL @ 0XFD070030 + + * Self refresh state is an intermediate state to enter to Self refresh pow + * er down state or exit Self refresh power down state for LPDDR4. This reg + * ister controls transition from the Self refresh state. - 1 - Prohibit tr + * ansition from Self refresh state - 0 - Allow transition from Self refres + * h state + * PSU_DDRC_PWRCTL_STAY_IN_SELFREF 0x0 + + * A value of 1 to this register causes system to move to Self Refresh stat + * e immediately, as long as it is not in INIT or DPD/MPSM operating_mode. + * This is referred to as Software Entry/Exit to Self Refresh. - 1 - Softwa + * re Entry to Self Refresh - 0 - Software Exit from Self Refresh + * PSU_DDRC_PWRCTL_SELFREF_SW 0x0 + + * When this is 1, the uMCTL2 puts the SDRAM into maximum power saving mode + * when the transaction store is empty. This register must be reset to '0' + * to bring uMCTL2 out of maximum power saving mode. Present only in desig + * ns configured to support DDR4. For non-DDR4, this register should not be + * set to 1. Note that MPSM is not supported when using a DWC DDR PHY, if + * the PHY parameter DWC_AC_CS_USE is disabled, as the MPSM exit sequence r + * equires the chip-select signal to toggle. FOR PERFORMANCE ONLY. + * PSU_DDRC_PWRCTL_MPSM_EN 0x0 + + * Enable the assertion of dfi_dram_clk_disable whenever a clock is not req + * uired by the SDRAM. If set to 0, dfi_dram_clk_disable is never asserted. + * Assertion of dfi_dram_clk_disable is as follows: In DDR2/DDR3, can only + * be asserted in Self Refresh. In DDR4, can be asserted in following: - i + * n Self Refresh. - in Maximum Power Saving Mode In mDDR/LPDDR2/LPDDR3, ca + * n be asserted in following: - in Self Refresh - in Power Down - in Deep + * Power Down - during Normal operation (Clock Stop) In LPDDR4, can be asse + * rted in following: - in Self Refresh Power Down - in Power Down - during + * Normal operation (Clock Stop) + * PSU_DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE 0x0 + + * When this is 1, uMCTL2 puts the SDRAM into deep power-down mode when the + * transaction store is empty. This register must be reset to '0' to bring + * uMCTL2 out of deep power-down mode. Controller performs automatic SDRAM + * initialization on deep power-down exit. Present only in designs configu + * red to support mDDR or LPDDR2 or LPDDR3. For non-mDDR/non-LPDDR2/non-LPD + * DR3, this register should not be set to 1. FOR PERFORMANCE ONLY. + * PSU_DDRC_PWRCTL_DEEPPOWERDOWN_EN 0x0 + + * If true then the uMCTL2 goes into power-down after a programmable number + * of cycles 'maximum idle clocks before power down' (PWRTMG.powerdown_to_ + * x32). This register bit may be re-programmed during the course of normal + * operation. + * PSU_DDRC_PWRCTL_POWERDOWN_EN 0x0 + + * If true then the uMCTL2 puts the SDRAM into Self Refresh after a program + * mable number of cycles 'maximum idle clocks before Self Refresh (PWRTMG. + * selfref_to_x32)'. This register bit may be re-programmed during the cour + * se of normal operation. + * PSU_DDRC_PWRCTL_SELFREF_EN 0x0 + + * Low Power Control Register + * (OFFSET, MASK, VALUE) (0XFD070030, 0x0000007FU ,0x00000000U) + */ + PSU_Mask_Write(DDRC_PWRCTL_OFFSET, 0x0000007FU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : PWRTMG @ 0XFD070034 + + * After this many clocks of NOP or deselect the uMCTL2 automatically puts + * the SDRAM into Self Refresh. This must be enabled in the PWRCTL.selfref_ + * en. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY. + * PSU_DDRC_PWRTMG_SELFREF_TO_X32 0x40 + + * Minimum deep power-down time. For mDDR, value from the JEDEC specificati + * on is 0 as mDDR exits from deep power-down mode immediately after PWRCTL + * .deeppowerdown_en is de-asserted. For LPDDR2/LPDDR3, value from the JEDE + * C specification is 500us. Unit: Multiples of 4096 clocks. Present only i + * n designs configured to support mDDR, LPDDR2 or LPDDR3. FOR PERFORMANCE + * ONLY. + * PSU_DDRC_PWRTMG_T_DPD_X4096 0x84 + + * After this many clocks of NOP or deselect the uMCTL2 automatically puts + * the SDRAM into power-down. This must be enabled in the PWRCTL.powerdown_ + * en. Unit: Multiples of 32 clocks FOR PERFORMANCE ONLY. + * PSU_DDRC_PWRTMG_POWERDOWN_TO_X32 0x10 + + * Low Power Timing Register + * (OFFSET, MASK, VALUE) (0XFD070034, 0x00FFFF1FU ,0x00408410U) + */ + PSU_Mask_Write(DDRC_PWRTMG_OFFSET, 0x00FFFF1FU, 0x00408410U); +/*##################################################################### */ + + /* + * Register : RFSHCTL0 @ 0XFD070050 + + * Threshold value in number of clock cycles before the critical refresh or + * page timer expires. A critical refresh is to be issued before this thre + * shold is reached. It is recommended that this not be changed from the de + * fault value, currently shown as 0x2. It must always be less than interna + * lly used t_rfc_nom_x32. Note that, in LPDDR2/LPDDR3/LPDDR4, internally u + * sed t_rfc_nom_x32 may be equal to RFSHTMG.t_rfc_nom_x32>>2 if derating i + * s enabled (DERATEEN.derate_enable=1). Otherwise, internally used t_rfc_n + * om_x32 will be equal to RFSHTMG.t_rfc_nom_x32. Unit: Multiples of 32 clo + * cks. + * PSU_DDRC_RFSHCTL0_REFRESH_MARGIN 0x2 + + * If the refresh timer (tRFCnom, also known as tREFI) has expired at least + * once, but it has not expired (RFSHCTL0.refresh_burst+1) times yet, then + * a speculative refresh may be performed. A speculative refresh is a refr + * esh performed at a time when refresh would be useful, but before it is a + * bsolutely required. When the SDRAM bus is idle for a period of time dete + * rmined by this RFSHCTL0.refresh_to_x32 and the refresh timer has expired + * at least once since the last refresh, then a speculative refresh is per + * formed. Speculative refreshes continues successively until there are no + * refreshes pending or until new reads or writes are issued to the uMCTL2. + * FOR PERFORMANCE ONLY. + * PSU_DDRC_RFSHCTL0_REFRESH_TO_X32 0x10 + + * The programmed value + 1 is the number of refresh timeouts that is allow + * ed to accumulate before traffic is blocked and the refreshes are forced + * to execute. Closing pages to perform a refresh is a one-time penalty tha + * t must be paid for each group of refreshes. Therefore, performing refres + * hes in a burst reduces the per-refresh penalty of these page closings. H + * igher numbers for RFSHCTL.refresh_burst slightly increases utilization; + * lower numbers decreases the worst-case latency associated with refreshes + * . - 0 - single refresh - 1 - burst-of-2 refresh - 7 - burst-of-8 refresh + * For information on burst refresh feature refer to section 3.9 of DDR2 J + * EDEC specification - JESD79-2F.pdf. For DDR2/3, the refresh is always pe + * r-rank and not per-bank. The rank refresh can be accumulated over 8*tREF + * I cycles using the burst refresh feature. In DDR4 mode, according to Fin + * e Granularity feature, 8 refreshes can be postponed in 1X mode, 16 refre + * shes in 2X mode and 32 refreshes in 4X mode. If using PHY-initiated upda + * tes, care must be taken in the setting of RFSHCTL0.refresh_burst, to ens + * ure that tRFCmax is not violated due to a PHY-initiated update occurring + * shortly before a refresh burst was due. In this situation, the refresh + * burst will be delayed until the PHY-initiated update is complete. + * PSU_DDRC_RFSHCTL0_REFRESH_BURST 0x0 + + * - 1 - Per bank refresh; - 0 - All bank refresh. Per bank refresh allows + * traffic to flow to other banks. Per bank refresh is not supported by all + * LPDDR2 devices but should be supported by all LPDDR3/LPDDR4 devices. Pr + * esent only in designs configured to support LPDDR2/LPDDR3/LPDDR4 + * PSU_DDRC_RFSHCTL0_PER_BANK_REFRESH 0x0 + + * Refresh Control Register 0 + * (OFFSET, MASK, VALUE) (0XFD070050, 0x00F1F1F4U ,0x00210000U) + */ + PSU_Mask_Write(DDRC_RFSHCTL0_OFFSET, 0x00F1F1F4U, 0x00210000U); +/*##################################################################### */ + + /* + * Register : RFSHCTL1 @ 0XFD070054 + + * Refresh timer start for rank 1 (only present in multi-rank configuration + * s). This is useful in staggering the refreshes to multiple ranks to help + * traffic to proceed. This is explained in Refresh Controls section of ar + * chitecture chapter. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY. + * PSU_DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32 0x0 + + * Refresh timer start for rank 0 (only present in multi-rank configuration + * s). This is useful in staggering the refreshes to multiple ranks to help + * traffic to proceed. This is explained in Refresh Controls section of ar + * chitecture chapter. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY. + * PSU_DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32 0x0 + + * Refresh Control Register 1 + * (OFFSET, MASK, VALUE) (0XFD070054, 0x0FFF0FFFU ,0x00000000U) + */ + PSU_Mask_Write(DDRC_RFSHCTL1_OFFSET, 0x0FFF0FFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : RFSHCTL3 @ 0XFD070060 + + * Fine Granularity Refresh Mode - 000 - Fixed 1x (Normal mode) - 001 - Fix + * ed 2x - 010 - Fixed 4x - 101 - Enable on the fly 2x (not supported) - 11 + * 0 - Enable on the fly 4x (not supported) - Everything else - reserved No + * te: The on-the-fly modes is not supported in this version of the uMCTL2. + * Note: This must be set up while the Controller is in reset or while the + * Controller is in self-refresh mode. Changing this during normal operati + * on is not allowed. Making this a dynamic register will be supported in f + * uture version of the uMCTL2. + * PSU_DDRC_RFSHCTL3_REFRESH_MODE 0x0 + + * Toggle this signal (either from 0 to 1 or from 1 to 0) to indicate that + * the refresh register(s) have been updated. The value is automatically up + * dated when exiting reset, so it does not need to be toggled initially. + * PSU_DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL 0x0 + + * When '1', disable auto-refresh generated by the uMCTL2. When auto-refres + * h is disabled, the SoC core must generate refreshes using the registers + * reg_ddrc_rank0_refresh, reg_ddrc_rank1_refresh, reg_ddrc_rank2_refresh a + * nd reg_ddrc_rank3_refresh. When dis_auto_refresh transitions from 0 to 1 + * , any pending refreshes are immediately scheduled by the uMCTL2. If DDR4 + * CRC/parity retry is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), d + * isable auto-refresh is not supported, and this bit must be set to '0'. T + * his register field is changeable on the fly. + * PSU_DDRC_RFSHCTL3_DIS_AUTO_REFRESH 0x1 + + * Refresh Control Register 3 + * (OFFSET, MASK, VALUE) (0XFD070060, 0x00000073U ,0x00000001U) + */ + PSU_Mask_Write(DDRC_RFSHCTL3_OFFSET, 0x00000073U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : RFSHTMG @ 0XFD070064 + + * tREFI: Average time interval between refreshes per rank (Specification: + * 7.8us for DDR2, DDR3 and DDR4. See JEDEC specification for mDDR, LPDDR2, + * LPDDR3 and LPDDR4). For LPDDR2/LPDDR3/LPDDR4: - if using all-bank refre + * shes (RFSHCTL0.per_bank_refresh = 0), this register should be set to tRE + * FIab - if using per-bank refreshes (RFSHCTL0.per_bank_refresh = 1), this + * register should be set to tREFIpb For configurations with MEMC_FREQ_RAT + * IO=2, program this to (tREFI/2), no rounding up. In DDR4 mode, tREFI val + * ue is different depending on the refresh mode. The user should program t + * he appropriate value from the spec based on the value programmed in the + * refresh mode register. Note that RFSHTMG.t_rfc_nom_x32 * 32 must be grea + * ter than RFSHTMG.t_rfc_min, and RFSHTMG.t_rfc_nom_x32 must be greater th + * an 0x1. Unit: Multiples of 32 clocks. + * PSU_DDRC_RFSHTMG_T_RFC_NOM_X32 0x81 + + * Used only when LPDDR3 memory type is connected. Should only be changed w + * hen uMCTL2 is in reset. Specifies whether to use the tREFBW parameter (r + * equired by some LPDDR3 devices which comply with earlier versions of the + * LPDDR3 JEDEC specification) or not: - 0 - tREFBW parameter not used - 1 + * - tREFBW parameter used + * PSU_DDRC_RFSHTMG_LPDDR3_TREFBW_EN 0x1 + + * tRFC (min): Minimum time from refresh to refresh or activate. For MEMC_F + * REQ_RATIO=1 configurations, t_rfc_min should be set to RoundUp(tRFCmin/t + * CK). For MEMC_FREQ_RATIO=2 configurations, t_rfc_min should be set to Ro + * undUp(RoundUp(tRFCmin/tCK)/2). In LPDDR2/LPDDR3/LPDDR4 mode: - if using + * all-bank refreshes, the tRFCmin value in the above equations is equal to + * tRFCab - if using per-bank refreshes, the tRFCmin value in the above eq + * uations is equal to tRFCpb In DDR4 mode, the tRFCmin value in the above + * equations is different depending on the refresh mode (fixed 1X,2X,4X) an + * d the device density. The user should program the appropriate value from + * the spec based on the 'refresh_mode' and the device density that is use + * d. Unit: Clocks. + * PSU_DDRC_RFSHTMG_T_RFC_MIN 0x8b + + * Refresh Timing Register + * (OFFSET, MASK, VALUE) (0XFD070064, 0x0FFF83FFU ,0x0081808BU) + */ + PSU_Mask_Write(DDRC_RFSHTMG_OFFSET, 0x0FFF83FFU, 0x0081808BU); +/*##################################################################### */ + + /* + * Register : ECCCFG0 @ 0XFD070070 + + * Disable ECC scrubs. Valid only when ECCCFG0.ecc_mode = 3'b100 and MEMC_U + * SE_RMW is defined + * PSU_DDRC_ECCCFG0_DIS_SCRUB 0x1 + + * ECC mode indicator - 000 - ECC disabled - 100 - ECC enabled - SEC/DED ov + * er 1 beat - all other settings are reserved for future use + * PSU_DDRC_ECCCFG0_ECC_MODE 0x0 + + * ECC Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD070070, 0x00000017U ,0x00000010U) + */ + PSU_Mask_Write(DDRC_ECCCFG0_OFFSET, 0x00000017U, 0x00000010U); +/*##################################################################### */ + + /* + * Register : ECCCFG1 @ 0XFD070074 + + * Selects whether to poison 1 or 2 bits - if 0 -> 2-bit (uncorrectable) da + * ta poisoning, if 1 -> 1-bit (correctable) data poisoning, if ECCCFG1.dat + * a_poison_en=1 + * PSU_DDRC_ECCCFG1_DATA_POISON_BIT 0x0 + + * Enable ECC data poisoning - introduces ECC errors on writes to address s + * pecified by the ECCPOISONADDR0/1 registers + * PSU_DDRC_ECCCFG1_DATA_POISON_EN 0x0 + + * ECC Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD070074, 0x00000003U ,0x00000000U) + */ + PSU_Mask_Write(DDRC_ECCCFG1_OFFSET, 0x00000003U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : CRCPARCTL1 @ 0XFD0700C4 + + * The maximum number of DFI PHY clock cycles allowed from the assertion of + * the dfi_rddata_en signal to the assertion of each of the corresponding + * bits of the dfi_rddata_valid signal. This corresponds to the DFI timing + * parameter tphy_rdlat. Refer to PHY specification for correct value. This + * value it only used for detecting read data timeout when DDR4 retry is e + * nabled by CRCPARCTL1.crc_parity_retry_enable=1. Maximum supported value: + * - 1:1 Frequency mode : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_r + * dlat < 'd114 - 1:2 Frequency mode ANDAND DFITMG0.dfi_rddata_use_sdr == 1 + * : CRCPARCTL1.dfi_t_phy_rdlat < 64 - 1:2 Frequency mode ANDAND DFITMG0.d + * fi_rddata_use_sdr == 0 : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_ + * rdlat < 'd114 Unit: DFI Clocks + * PSU_DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT 0x10 + + * After a Parity or CRC error is flagged on dfi_alert_n signal, the softwa + * re has an option to read the mode registers in the DRAM before the hardw + * are begins the retry process - 1: Wait for software to read/write the mo + * de registers before hardware begins the retry. After software is done wi + * th its operations, it will clear the alert interrupt register bit - 0: H + * ardware can begin the retry right away after the dfi_alert_n pulse goes + * away. The value on this register is valid only when retry is enabled (PA + * RCTRL.crc_parity_retry_enable = 1) If this register is set to 1 and if t + * he software doesn't clear the interrupt register after handling the pari + * ty/CRC error, then the hardware will not begin the retry process and the + * system will hang. In the case of Parity/CRC error, there are two possib + * ilities when the software doesn't reset MR5[4] to 0. - (i) If 'Persisten + * t parity' mode register bit is NOT set: the commands sent during retry a + * nd normal operation are executed without parity checking. The value in t + * he Parity error log register MPR Page 1 is valid. - (ii) If 'Persistent + * parity' mode register bit is SET: Parity checking is done for commands s + * ent during retry and normal operation. If multiple errors occur before M + * R5[4] is cleared, the error log in MPR Page 1 should be treated as 'Don' + * t care'. + * PSU_DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW 0x1 + + * - 1: Enable command retry mechanism in case of C/A Parity or CRC error - + * 0: Disable command retry mechanism when C/A Parity or CRC features are + * enabled. Note that retry functionality is not supported if burst chop is + * enabled (MSTR.burstchop = 1) and/or disable auto-refresh is enabled (RF + * SHCTL3.dis_auto_refresh = 1) + * PSU_DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE 0x0 + + * CRC Calculation setting register - 1: CRC includes DM signal - 0: CRC no + * t includes DM signal Present only in designs configured to support DDR4. + * PSU_DDRC_CRCPARCTL1_CRC_INC_DM 0x0 + + * CRC enable Register - 1: Enable generation of CRC - 0: Disable generatio + * n of CRC The setting of this register should match the CRC mode register + * setting in the DRAM. + * PSU_DDRC_CRCPARCTL1_CRC_ENABLE 0x0 + + * C/A Parity enable register - 1: Enable generation of C/A parity and dete + * ction of C/A parity error - 0: Disable generation of C/A parity and disa + * ble detection of C/A parity error If RCD's parity error detection or SDR + * AM's parity detection is enabled, this register should be 1. + * PSU_DDRC_CRCPARCTL1_PARITY_ENABLE 0x0 + + * CRC Parity Control Register1 + * (OFFSET, MASK, VALUE) (0XFD0700C4, 0x3F000391U ,0x10000200U) + */ + PSU_Mask_Write(DDRC_CRCPARCTL1_OFFSET, 0x3F000391U, 0x10000200U); +/*##################################################################### */ + + /* + * Register : CRCPARCTL2 @ 0XFD0700C8 + + * Value from the DRAM spec indicating the maximum width of the dfi_alert_n + * pulse when a parity error occurs. Recommended values: - tPAR_ALERT_PW.M + * AX For configurations with MEMC_FREQ_RATIO=2, program this to tPAR_ALERT + * _PW.MAX/2 and round up to next integer value. Values of 0, 1 and 2 are i + * llegal. This value must be greater than CRCPARCTL2.t_crc_alert_pw_max. + * PSU_DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX 0x40 + + * Value from the DRAM spec indicating the maximum width of the dfi_alert_n + * pulse when a CRC error occurs. Recommended values: - tCRC_ALERT_PW.MAX + * For configurations with MEMC_FREQ_RATIO=2, program this to tCRC_ALERT_PW + * .MAX/2 and round up to next integer value. Values of 0, 1 and 2 are ille + * gal. This value must be less than CRCPARCTL2.t_par_alert_pw_max. + * PSU_DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX 0x5 + + * Indicates the maximum duration in number of DRAM clock cycles for which + * a command should be held in the Command Retry FIFO before it is popped o + * ut. Every location in the Command Retry FIFO has an associated down coun + * ting timer that will use this register as the start value. The down coun + * ting starts when a command is loaded into the FIFO. The timer counts dow + * n every 4 DRAM cycles. When the counter reaches zero, the entry is poppe + * d from the FIFO. All the counters are frozen, if a C/A Parity or CRC err + * or occurs before the counter reaches zero. The counter is reset to 0, af + * ter all the commands in the FIFO are retried. Recommended(minimum) value + * s: - Only C/A Parity is enabled. RoundUp((PHY Command Latency(DRAM CLK) + * + CAL + RDIMM delay + tPAR_ALERT_ON.max + tPAR_UNKNOWN + PHY Alert Laten + * cy(DRAM CLK) + board delay) / 4) + 2 - Both C/A Parity and CRC is enable + * d/ Only CRC is enabled. RoundUp((PHY Command Latency(DRAM CLK) + CAL + R + * DIMM delay + WL + 5(BL10)+ tCRC_ALERT.max + PHY Alert Latency(DRAM CLK) + * + board delay) / 4) + 2 Note 1: All value (e.g. tPAR_ALERT_ON) should be + * in terms of DRAM Clock and round up Note 2: Board delay(Command/Alert_n + * ) should be considered. Note 3: Use the worst case(longer) value for PHY + * Latencies/Board delay Note 4: The Recommended values are minimum value + * to be set. For mode detail, See 'Calculation of FIFO Depth' section. Max + * value can be set to this register is defined below: - MEMC_BURST_LENGTH + * == 16 Full bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 + * Full bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Half b + * us Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-4 Half bus Mod + * e (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-6 Quarter bus Mode (C + * RC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-8 Quarter bus Mode (CRC= + * ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-12 - MEMC_BURST_LENGTH != 16 + * Full bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-1 Full + * bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mod + * e (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mode (CRC + * =ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Quarter bus Mode (CRC=OFF + * ) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-4 Quarter bus Mode (CRC=ON) Ma + * x value = UMCTL2_RETRY_CMD_FIFO_DEPTH-6 Values of 0, 1 and 2 are illegal + * . + * PSU_DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4 0x1f + + * CRC Parity Control Register2 + * (OFFSET, MASK, VALUE) (0XFD0700C8, 0x01FF1F3FU ,0x0040051FU) + */ + PSU_Mask_Write(DDRC_CRCPARCTL2_OFFSET, 0x01FF1F3FU, 0x0040051FU); +/*##################################################################### */ + + /* + * Register : INIT0 @ 0XFD0700D0 + + * If lower bit is enabled the SDRAM initialization routine is skipped. The + * upper bit decides what state the controller starts up in when reset is + * removed - 00 - SDRAM Intialization routine is run after power-up - 01 - + * SDRAM Intialization routine is skipped after power-up. Controller starts + * up in Normal Mode - 11 - SDRAM Intialization routine is skipped after p + * ower-up. Controller starts up in Self-refresh Mode - 10 - SDRAM Intializ + * ation routine is run after power-up. Note: The only 2'b00 is supported f + * or LPDDR4 in this version of the uMCTL2. + * PSU_DDRC_INIT0_SKIP_DRAM_INIT 0x0 + + * Cycles to wait after driving CKE high to start the SDRAM initialization + * sequence. Unit: 1024 clocks. DDR2 typically requires a 400 ns delay, req + * uiring this value to be programmed to 2 at all clock speeds. LPDDR2/LPDD + * R3 typically requires this to be programmed for a delay of 200 us. LPDDR + * 4 typically requires this to be programmed for a delay of 2 us. For conf + * igurations with MEMC_FREQ_RATIO=2, program this to JEDEC spec value divi + * ded by 2, and round it up to next integer value. + * PSU_DDRC_INIT0_POST_CKE_X1024 0x2 + + * Cycles to wait after reset before driving CKE high to start the SDRAM in + * itialization sequence. Unit: 1024 clock cycles. DDR2 specifications typi + * cally require this to be programmed for a delay of >= 200 us. LPDDR2/LPD + * DR3: tINIT1 of 100 ns (min) LPDDR4: tINIT3 of 2 ms (min) For configurati + * ons with MEMC_FREQ_RATIO=2, program this to JEDEC spec value divided by + * 2, and round it up to next integer value. + * PSU_DDRC_INIT0_PRE_CKE_X1024 0x106 + + * SDRAM Initialization Register 0 + * (OFFSET, MASK, VALUE) (0XFD0700D0, 0xC3FF0FFFU ,0x00020106U) + */ + PSU_Mask_Write(DDRC_INIT0_OFFSET, 0xC3FF0FFFU, 0x00020106U); +/*##################################################################### */ + + /* + * Register : INIT1 @ 0XFD0700D4 + + * Number of cycles to assert SDRAM reset signal during init sequence. This + * is only present for designs supporting DDR3, DDR4 or LPDDR4 devices. Fo + * r use with a DDR PHY, this should be set to a minimum of 1 + * PSU_DDRC_INIT1_DRAM_RSTN_X1024 0x2 + + * Cycles to wait after completing the SDRAM initialization sequence before + * starting the dynamic scheduler. Unit: Counts of a global timer that pul + * ses every 32 clock cycles. There is no known specific requirement for th + * is; it may be set to zero. + * PSU_DDRC_INIT1_FINAL_WAIT_X32 0x0 + + * Wait period before driving the OCD complete command to SDRAM. Unit: Coun + * ts of a global timer that pulses every 32 clock cycles. There is no know + * n specific requirement for this; it may be set to zero. + * PSU_DDRC_INIT1_PRE_OCD_X32 0x0 + + * SDRAM Initialization Register 1 + * (OFFSET, MASK, VALUE) (0XFD0700D4, 0x01FF7F0FU ,0x00020000U) + */ + PSU_Mask_Write(DDRC_INIT1_OFFSET, 0x01FF7F0FU, 0x00020000U); +/*##################################################################### */ + + /* + * Register : INIT2 @ 0XFD0700D8 + + * Idle time after the reset command, tINIT4. Present only in designs confi + * gured to support LPDDR2. Unit: 32 clock cycles. + * PSU_DDRC_INIT2_IDLE_AFTER_RESET_X32 0x23 + + * Time to wait after the first CKE high, tINIT2. Present only in designs c + * onfigured to support LPDDR2/LPDDR3. Unit: 1 clock cycle. LPDDR2/LPDDR3 t + * ypically requires 5 x tCK delay. + * PSU_DDRC_INIT2_MIN_STABLE_CLOCK_X1 0x5 + + * SDRAM Initialization Register 2 + * (OFFSET, MASK, VALUE) (0XFD0700D8, 0x0000FF0FU ,0x00002305U) + */ + PSU_Mask_Write(DDRC_INIT2_OFFSET, 0x0000FF0FU, 0x00002305U); +/*##################################################################### */ + + /* + * Register : INIT3 @ 0XFD0700DC + + * DDR2: Value to write to MR register. Bit 8 is for DLL and the setting he + * re is ignored. The uMCTL2 sets this bit appropriately. DDR3/DDR4: Value + * loaded into MR0 register. mDDR: Value to write to MR register. LPDDR2/LP + * DDR3/LPDDR4 - Value to write to MR1 register + * PSU_DDRC_INIT3_MR 0x730 + + * DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setti + * ng in this register is ignored. The uMCTL2 sets those bits appropriately + * . DDR3/DDR4: Value to write to MR1 register Set bit 7 to 0. If PHY-evalu + * ation mode training is enabled, this bit is set appropriately by the uMC + * TL2 during write leveling. mDDR: Value to write to EMR register. LPDDR2/ + * LPDDR3/LPDDR4 - Value to write to MR2 register + * PSU_DDRC_INIT3_EMR 0x301 + + * SDRAM Initialization Register 3 + * (OFFSET, MASK, VALUE) (0XFD0700DC, 0xFFFFFFFFU ,0x07300301U) + */ + PSU_Mask_Write(DDRC_INIT3_OFFSET, 0xFFFFFFFFU, 0x07300301U); +/*##################################################################### */ + + /* + * Register : INIT4 @ 0XFD0700E0 + + * DDR2: Value to write to EMR2 register. DDR3/DDR4: Value to write to MR2 + * register LPDDR2/LPDDR3/LPDDR4: Value to write to MR3 register mDDR: Unus + * ed + * PSU_DDRC_INIT4_EMR2 0x20 + + * DDR2: Value to write to EMR3 register. DDR3/DDR4: Value to write to MR3 + * register mDDR/LPDDR2/LPDDR3: Unused LPDDR4: Value to write to MR13 regis + * ter + * PSU_DDRC_INIT4_EMR3 0x200 + + * SDRAM Initialization Register 4 + * (OFFSET, MASK, VALUE) (0XFD0700E0, 0xFFFFFFFFU ,0x00200200U) + */ + PSU_Mask_Write(DDRC_INIT4_OFFSET, 0xFFFFFFFFU, 0x00200200U); +/*##################################################################### */ + + /* + * Register : INIT5 @ 0XFD0700E4 + + * ZQ initial calibration, tZQINIT. Present only in designs configured to s + * upport DDR3 or DDR4 or LPDDR2/LPDDR3. Unit: 32 clock cycles. DDR3 typica + * lly requires 512 clocks. DDR4 requires 1024 clocks. LPDDR2/LPDDR3 requir + * es 1 us. + * PSU_DDRC_INIT5_DEV_ZQINIT_X32 0x21 + + * Maximum duration of the auto initialization, tINIT5. Present only in des + * igns configured to support LPDDR2/LPDDR3. LPDDR2/LPDDR3 typically requir + * es 10 us. + * PSU_DDRC_INIT5_MAX_AUTO_INIT_X1024 0x4 + + * SDRAM Initialization Register 5 + * (OFFSET, MASK, VALUE) (0XFD0700E4, 0x00FF03FFU ,0x00210004U) + */ + PSU_Mask_Write(DDRC_INIT5_OFFSET, 0x00FF03FFU, 0x00210004U); +/*##################################################################### */ + + /* + * Register : INIT6 @ 0XFD0700E8 + + * DDR4- Value to be loaded into SDRAM MR4 registers. Used in DDR4 designs + * only. + * PSU_DDRC_INIT6_MR4 0x0 + + * DDR4- Value to be loaded into SDRAM MR5 registers. Used in DDR4 designs + * only. + * PSU_DDRC_INIT6_MR5 0x6c0 + + * SDRAM Initialization Register 6 + * (OFFSET, MASK, VALUE) (0XFD0700E8, 0xFFFFFFFFU ,0x000006C0U) + */ + PSU_Mask_Write(DDRC_INIT6_OFFSET, 0xFFFFFFFFU, 0x000006C0U); +/*##################################################################### */ + + /* + * Register : INIT7 @ 0XFD0700EC + + * DDR4- Value to be loaded into SDRAM MR6 registers. Used in DDR4 designs + * only. + * PSU_DDRC_INIT7_MR6 0x819 + + * SDRAM Initialization Register 7 + * (OFFSET, MASK, VALUE) (0XFD0700EC, 0xFFFF0000U ,0x08190000U) + */ + PSU_Mask_Write(DDRC_INIT7_OFFSET, 0xFFFF0000U, 0x08190000U); +/*##################################################################### */ + + /* + * Register : DIMMCTL @ 0XFD0700F0 + + * Disabling Address Mirroring for BG bits. When this is set to 1, BG0 and + * BG1 are NOT swapped even if Address Mirroring is enabled. This will be r + * equired for DDR4 DIMMs with x16 devices. - 1 - BG0 and BG1 are NOT swapp + * ed. - 0 - BG0 and BG1 are swapped if address mirroring is enabled. + * PSU_DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING 0x0 + + * Enable for BG1 bit of MRS command. BG1 bit of the mode register address + * is specified as RFU (Reserved for Future Use) and must be programmed to + * 0 during MRS. In case where DRAMs which do not have BG1 are attached and + * both the CA parity and the Output Inversion are enabled, this must be s + * et to 0, so that the calculation of CA parity will not include BG1 bit. + * Note: This has no effect on the address of any other memory accesses, or + * of software-driven mode register accesses. If address mirroring is enab + * led, this is applied to BG1 of even ranks and BG0 of odd ranks. - 1 - En + * abled - 0 - Disabled + * PSU_DDRC_DIMMCTL_MRS_BG1_EN 0x1 + + * Enable for A17 bit of MRS command. A17 bit of the mode register address + * is specified as RFU (Reserved for Future Use) and must be programmed to + * 0 during MRS. In case where DRAMs which do not have A17 are attached and + * the Output Inversion are enabled, this must be set to 0, so that the ca + * lculation of CA parity will not include A17 bit. Note: This has no effec + * t on the address of any other memory accesses, or of software-driven mod + * e register accesses. - 1 - Enabled - 0 - Disabled + * PSU_DDRC_DIMMCTL_MRS_A17_EN 0x0 + + * Output Inversion Enable (for DDR4 RDIMM implementations only). DDR4 RDIM + * M implements the Output Inversion feature by default, which means that t + * he following address, bank address and bank group bits of B-side DRAMs a + * re inverted: A3-A9, A11, A13, A17, BA0-BA1, BG0-BG1. Setting this bit en + * sures that, for mode register accesses generated by the uMCTL2 during th + * e automatic initialization routine and enabling of a particular DDR4 fea + * ture, separate A-side and B-side mode register accesses are generated. F + * or B-side mode register accesses, these bits are inverted within the uMC + * TL2 to compensate for this RDIMM inversion. Note: This has no effect on + * the address of any other memory accesses, or of software-driven mode reg + * ister accesses. - 1 - Implement output inversion for B-side DRAMs. - 0 - + * Do not implement output inversion for B-side DRAMs. + * PSU_DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN 0x0 + + * Address Mirroring Enable (for multi-rank UDIMM implementations and multi + * -rank DDR4 RDIMM implementations). Some UDIMMs and DDR4 RDIMMs implement + * address mirroring for odd ranks, which means that the following address + * , bank address and bank group bits are swapped: (A3, A4), (A5, A6), (A7, + * A8), (BA0, BA1) and also (A11, A13), (BG0, BG1) for the DDR4. Setting t + * his bit ensures that, for mode register accesses during the automatic in + * itialization routine, these bits are swapped within the uMCTL2 to compen + * sate for this UDIMM/RDIMM swapping. In addition to the automatic initial + * ization routine, in case of DDR4 UDIMM/RDIMM, they are swapped during th + * e automatic MRS access to enable/disable of a particular DDR4 feature. N + * ote: This has no effect on the address of any other memory accesses, or + * of software-driven mode register accesses. This is not supported for mDD + * R, LPDDR2, LPDDR3 or LPDDR4 SDRAMs. Note: In case of x16 DDR4 DIMMs, BG1 + * output of MRS for the odd ranks is same as BG0 because BG1 is invalid, + * hence dimm_dis_bg_mirroring register must be set to 1. - 1 - For odd ran + * ks, implement address mirroring for MRS commands to during initializatio + * n and for any automatic DDR4 MRS commands (to be used if UDIMM/RDIMM imp + * lements address mirroring) - 0 - Do not implement address mirroring + * PSU_DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN 0x0 + + * Staggering enable for multi-rank accesses (for multi-rank UDIMM and RDIM + * M implementations only). This is not supported for mDDR, LPDDR2, LPDDR3 + * or LPDDR4 SDRAMs. Note: Even if this bit is set it does not take care of + * software driven MR commands (via MRCTRL0/MRCTRL1), where software is re + * sponsible to send them to seperate ranks as appropriate. - 1 - (DDR4) Se + * nd MRS commands to each ranks seperately - 1 - (non-DDR4) Send all comma + * nds to even and odd ranks seperately - 0 - Do not stagger accesses + * PSU_DDRC_DIMMCTL_DIMM_STAGGER_CS_EN 0x0 + + * DIMM Control Register + * (OFFSET, MASK, VALUE) (0XFD0700F0, 0x0000003FU ,0x00000010U) + */ + PSU_Mask_Write(DDRC_DIMMCTL_OFFSET, 0x0000003FU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : RANKCTL @ 0XFD0700F4 + + * Only present for multi-rank configurations. Indicates the number of cloc + * ks of gap in data responses when performing consecutive writes to differ + * ent ranks. This is used to switch the delays in the PHY to match the ran + * k requirements. This value should consider both PHY requirement and ODT + * requirement. - PHY requirement: tphy_wrcsgap + 1 (see PHY databook for v + * alue of tphy_wrcsgap) If CRC feature is enabled, should be increased by + * 1. If write preamble is set to 2tCK(DDR4/LPDDR4 only), should be increas + * ed by 1. If write postamble is set to 1.5tCK(LPDDR4 only), should be inc + * reased by 1. - ODT requirement: The value programmed in this register ta + * kes care of the ODT switch off timing requirement when switching ranks d + * uring writes. For LPDDR4, the requirement is ODTLoff - ODTLon - BL/2 + 1 + * For configurations with MEMC_FREQ_RATIO=1, program this to the larger o + * f PHY requirement or ODT requirement. For configurations with MEMC_FREQ_ + * RATIO=2, program this to the larger value divided by two and round it up + * to the next integer. + * PSU_DDRC_RANKCTL_DIFF_RANK_WR_GAP 0x6 + + * Only present for multi-rank configurations. Indicates the number of cloc + * ks of gap in data responses when performing consecutive reads to differe + * nt ranks. This is used to switch the delays in the PHY to match the rank + * requirements. This value should consider both PHY requirement and ODT r + * equirement. - PHY requirement: tphy_rdcsgap + 1 (see PHY databook for va + * lue of tphy_rdcsgap) If read preamble is set to 2tCK(DDR4/LPDDR4 only), + * should be increased by 1. If read postamble is set to 1.5tCK(LPDDR4 only + * ), should be increased by 1. - ODT requirement: The value programmed in + * this register takes care of the ODT switch off timing requirement when s + * witching ranks during reads. For configurations with MEMC_FREQ_RATIO=1, + * program this to the larger of PHY requirement or ODT requirement. For co + * nfigurations with MEMC_FREQ_RATIO=2, program this to the larger value di + * vided by two and round it up to the next integer. + * PSU_DDRC_RANKCTL_DIFF_RANK_RD_GAP 0x6 + + * Only present for multi-rank configurations. Background: Reads to the sam + * e rank can be performed back-to-back. Reads to different ranks require a + * dditional gap dictated by the register RANKCTL.diff_rank_rd_gap. This is + * to avoid possible data bus contention as well as to give PHY enough tim + * e to switch the delay when changing ranks. The uMCTL2 arbitrates for bus + * access on a cycle-by-cycle basis; therefore after a read is scheduled, + * there are few clock cycles (determined by the value on RANKCTL.diff_rank + * _rd_gap register) in which only reads from the same rank are eligible to + * be scheduled. This prevents reads from other ranks from having fair acc + * ess to the data bus. This parameter represents the maximum number of rea + * ds that can be scheduled consecutively to the same rank. After this numb + * er is reached, a delay equal to RANKCTL.diff_rank_rd_gap is inserted by + * the scheduler to allow all ranks a fair opportunity to be scheduled. Hig + * her numbers increase bandwidth utilization, lower numbers increase fairn + * ess. This feature can be DISABLED by setting this register to 0. When se + * t to 0, the Controller will stay on the same rank as long as commands ar + * e available for it. Minimum programmable value is 0 (feature disabled) a + * nd maximum programmable value is 0xF. FOR PERFORMANCE ONLY. + * PSU_DDRC_RANKCTL_MAX_RANK_RD 0xf + + * Rank Control Register + * (OFFSET, MASK, VALUE) (0XFD0700F4, 0x00000FFFU ,0x0000066FU) + */ + PSU_Mask_Write(DDRC_RANKCTL_OFFSET, 0x00000FFFU, 0x0000066FU); +/*##################################################################### */ + + /* + * Register : DRAMTMG0 @ 0XFD070100 + + * Minimum time between write and precharge to same bank. Unit: Clocks Spec + * ifications: WL + BL/2 + tWR = approximately 8 cycles + 15 ns = 14 clocks + * @400MHz and less for lower frequencies where: - WL = write latency - BL + * = burst length. This must match the value programmed in the BL bit of t + * he mode register to the SDRAM. BST (burst terminate) is not supported at + * present. - tWR = Write recovery time. This comes directly from the SDRA + * M specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 for this p + * arameter. For configurations with MEMC_FREQ_RATIO=2, 1T mode, divide the + * above value by 2. No rounding up. For configurations with MEMC_FREQ_RAT + * IO=2, 2T mode or LPDDR4 mode, divide the above value by 2 and round it u + * p to the next integer value. + * PSU_DDRC_DRAMTMG0_WR2PRE 0x11 + + * tFAW Valid only when 8 or more banks(or banks x bank groups) are present + * . In 8-bank design, at most 4 banks must be activated in a rolling windo + * w of tFAW cycles. For configurations with MEMC_FREQ_RATIO=2, program thi + * s to (tFAW/2) and round up to next integer value. In a 4-bank design, se + * t this register to 0x1 independent of the MEMC_FREQ_RATIO configuration. + * Unit: Clocks + * PSU_DDRC_DRAMTMG0_T_FAW 0x10 + + * tRAS(max): Maximum time between activate and precharge to same bank. Thi + * s is the maximum time that a page can be kept open Minimum value of this + * register is 1. Zero is invalid. For configurations with MEMC_FREQ_RATIO + * =2, program this to (tRAS(max)-1)/2. No rounding up. Unit: Multiples of + * 1024 clocks. + * PSU_DDRC_DRAMTMG0_T_RAS_MAX 0x24 + + * tRAS(min): Minimum time between activate and precharge to the same bank. + * For configurations with MEMC_FREQ_RATIO=2, 1T mode, program this to tRA + * S(min)/2. No rounding up. For configurations with MEMC_FREQ_RATIO=2, 2T + * mode or LPDDR4 mode, program this to (tRAS(min)/2) and round it up to th + * e next integer value. Unit: Clocks + * PSU_DDRC_DRAMTMG0_T_RAS_MIN 0x12 + + * SDRAM Timing Register 0 + * (OFFSET, MASK, VALUE) (0XFD070100, 0x7F3F7F3FU ,0x11102412U) + */ + PSU_Mask_Write(DDRC_DRAMTMG0_OFFSET, 0x7F3F7F3FU, 0x11102412U); +/*##################################################################### */ + + /* + * Register : DRAMTMG1 @ 0XFD070104 + + * tXP: Minimum time after power-down exit to any operation. For DDR3, this + * should be programmed to tXPDLL if slow powerdown exit is selected in MR + * 0[12]. If C/A parity for DDR4 is used, set to (tXP+PL) instead. For conf + * igurations with MEMC_FREQ_RATIO=2, program this to (tXP/2) and round it + * up to the next integer value. Units: Clocks + * PSU_DDRC_DRAMTMG1_T_XP 0x4 + + * tRTP: Minimum time from read to precharge of same bank. - DDR2: tAL + BL + * /2 + max(tRTP, 2) - 2 - DDR3: tAL + max (tRTP, 4) - DDR4: Max of followi + * ng two equations: tAL + max (tRTP, 4) or, RL + BL/2 - tRP. - mDDR: BL/2 + * - LPDDR2: Depends on if it's LPDDR2-S2 or LPDDR2-S4: LPDDR2-S2: BL/2 + t + * RTP - 1. LPDDR2-S4: BL/2 + max(tRTP,2) - 2. - LPDDR3: BL/2 + max(tRTP,4) + * - 4 - LPDDR4: BL/2 + max(tRTP,8) - 8 For configurations with MEMC_FREQ_ + * RATIO=2, 1T mode, divide the above value by 2. No rounding up. For confi + * gurations with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, divide the abo + * ve value by 2 and round it up to the next integer value. Unit: Clocks. + * PSU_DDRC_DRAMTMG1_RD2PRE 0x4 + + * tRC: Minimum time between activates to same bank. For configurations wit + * h MEMC_FREQ_RATIO=2, program this to (tRC/2) and round up to next intege + * r value. Unit: Clocks. + * PSU_DDRC_DRAMTMG1_T_RC 0x1a + + * SDRAM Timing Register 1 + * (OFFSET, MASK, VALUE) (0XFD070104, 0x001F1F7FU ,0x0004041AU) + */ + PSU_Mask_Write(DDRC_DRAMTMG1_OFFSET, 0x001F1F7FU, 0x0004041AU); +/*##################################################################### */ + + /* + * Register : DRAMTMG2 @ 0XFD070108 + + * Set to WL Time from write command to write data on SDRAM interface. This + * must be set to WL. For mDDR, it should normally be set to 1. Note that, + * depending on the PHY, if using RDIMM, it may be necessary to use a valu + * e of WL + 1 to compensate for the extra cycle of latency through the RDI + * MM For configurations with MEMC_FREQ_RATIO=2, divide the value calculate + * d using the above equation by 2, and round it up to next integer. This r + * egister field is not required for DDR2 and DDR3 (except if MEMC_TRAINING + * is set), as the DFI read and write latencies defined in DFITMG0 and DFI + * TMG1 are sufficient for those protocols Unit: clocks + * PSU_DDRC_DRAMTMG2_WRITE_LATENCY 0x7 + + * Set to RL Time from read command to read data on SDRAM interface. This m + * ust be set to RL. Note that, depending on the PHY, if using RDIMM, it ma + * t be necessary to use a value of RL + 1 to compensate for the extra cycl + * e of latency through the RDIMM For configurations with MEMC_FREQ_RATIO=2 + * , divide the value calculated using the above equation by 2, and round i + * t up to next integer. This register field is not required for DDR2 and D + * DR3 (except if MEMC_TRAINING is set), as the DFI read and write latencie + * s defined in DFITMG0 and DFITMG1 are sufficient for those protocols Unit + * : clocks + * PSU_DDRC_DRAMTMG2_READ_LATENCY 0x8 + + * DDR2/3/mDDR: RL + BL/2 + 2 - WL DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL L + * PDDR2/LPDDR3: RL + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL LPDDR4(DQ ODT is Di + * sabled): RL + BL/2 + RU(tDQSCKmax/tCK) + WR_PREAMBLE + RD_POSTAMBLE - WL + * LPDDR4(DQ ODT is Enabled) : RL + BL/2 + RU(tDQSCKmax/tCK) + RD_POSTAMBL + * E - ODTLon - RU(tODTon(min)/tCK) Minimum time from read command to write + * command. Include time for bus turnaround and all per-bank, per-rank, an + * d global constraints. Unit: Clocks. Where: - WL = write latency - BL = b + * urst length. This must match the value programmed in the BL bit of the m + * ode register to the SDRAM - RL = read latency = CAS latency - WR_PREAMBL + * E = write preamble. This is unique to DDR4 and LPDDR4. - RD_POSTAMBLE = + * read postamble. This is unique to LPDDR4. For LPDDR2/LPDDR3/LPDDR4, if d + * erating is enabled (DERATEEN.derate_enable=1), derated tDQSCKmax should + * be used. For configurations with MEMC_FREQ_RATIO=2, divide the value cal + * culated using the above equation by 2, and round it up to next integer. + * PSU_DDRC_DRAMTMG2_RD2WR 0x6 + + * DDR4: CWL + PL + BL/2 + tWTR_L Others: CWL + BL/2 + tWTR In DDR4, minimu + * m time from write command to read command for same bank group. In others + * , minimum time from write command to read command. Includes time for bus + * turnaround, recovery times, and all per-bank, per-rank, and global cons + * traints. Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity la + * tency - BL = burst length. This must match the value programmed in the B + * L bit of the mode register to the SDRAM - tWTR_L = internal write to rea + * d command delay for same bank group. This comes directly from the SDRAM + * specification. - tWTR = internal write to read command delay. This comes + * directly from the SDRAM specification. Add one extra cycle for LPDDR2/L + * PDDR3/LPDDR4 operation. For configurations with MEMC_FREQ_RATIO=2, divid + * e the value calculated using the above equation by 2, and round it up to + * next integer. + * PSU_DDRC_DRAMTMG2_WR2RD 0xd + + * SDRAM Timing Register 2 + * (OFFSET, MASK, VALUE) (0XFD070108, 0x3F3F3F3FU ,0x0708060DU) + */ + PSU_Mask_Write(DDRC_DRAMTMG2_OFFSET, 0x3F3F3F3FU, 0x0708060DU); +/*##################################################################### */ + + /* + * Register : DRAMTMG3 @ 0XFD07010C + + * Time to wait after a mode register write or read (MRW or MRR). Present o + * nly in designs configured to support LPDDR2, LPDDR3 or LPDDR4. LPDDR2 ty + * pically requires value of 5. LPDDR3 typically requires value of 10. LPDD + * R4: Set this to the larger of tMRW and tMRWCKEL. For LPDDR2, this regist + * er is used for the time from a MRW/MRR to all other commands. For LDPDR3 + * , this register is used for the time from a MRW/MRR to a MRW/MRR. + * PSU_DDRC_DRAMTMG3_T_MRW 0x5 + + * tMRD: Cycles to wait after a mode register write or read. Depending on t + * he connected SDRAM, tMRD represents: DDR2/mDDR: Time from MRS to any com + * mand DDR3/4: Time from MRS to MRS command LPDDR2: not used LPDDR3/4: Tim + * e from MRS to non-MRS command For configurations with MEMC_FREQ_RATIO=2, + * program this to (tMRD/2) and round it up to the next integer value. If + * C/A parity for DDR4 is used, set to tMRD_PAR(tMOD+PL) instead. + * PSU_DDRC_DRAMTMG3_T_MRD 0x4 + + * tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode com + * mand and following non-load mode command. If C/A parity for DDR4 is used + * , set to tMOD_PAR(tMOD+PL) instead. Set to tMOD if MEMC_FREQ_RATIO=1, or + * tMOD/2 (rounded up to next integer) if MEMC_FREQ_RATIO=2. Note that if + * using RDIMM, depending on the PHY, it may be necessary to use a value of + * tMOD + 1 or (tMOD + 1)/2 to compensate for the extra cycle of latency a + * pplied to mode register writes by the RDIMM chip. + * PSU_DDRC_DRAMTMG3_T_MOD 0xc + + * SDRAM Timing Register 3 + * (OFFSET, MASK, VALUE) (0XFD07010C, 0x3FF3F3FFU ,0x0050400CU) + */ + PSU_Mask_Write(DDRC_DRAMTMG3_OFFSET, 0x3FF3F3FFU, 0x0050400CU); +/*##################################################################### */ + + /* + * Register : DRAMTMG4 @ 0XFD070110 + + * tRCD - tAL: Minimum time from activate to read or write command to same + * bank. For configurations with MEMC_FREQ_RATIO=2, program this to ((tRCD + * - tAL)/2) and round it up to the next integer value. Minimum value allow + * ed for this register is 1, which implies minimum (tRCD - tAL) value to b + * e 2 in configurations with MEMC_FREQ_RATIO=2. Unit: Clocks. + * PSU_DDRC_DRAMTMG4_T_RCD 0x8 + + * DDR4: tCCD_L: This is the minimum time between two reads or two writes f + * or same bank group. Others: tCCD: This is the minimum time between two r + * eads or two writes. For configurations with MEMC_FREQ_RATIO=2, program t + * his to (tCCD_L/2 or tCCD/2) and round it up to the next integer value. U + * nit: clocks. + * PSU_DDRC_DRAMTMG4_T_CCD 0x3 + + * DDR4: tRRD_L: Minimum time between activates from bank 'a' to bank 'b' f + * or same bank group. Others: tRRD: Minimum time between activates from ba + * nk 'a' to bank 'b'For configurations with MEMC_FREQ_RATIO=2, program thi + * s to (tRRD_L/2 or tRRD/2) and round it up to the next integer value. Uni + * t: Clocks. + * PSU_DDRC_DRAMTMG4_T_RRD 0x3 + + * tRP: Minimum time from precharge to activate of same bank. For MEMC_FREQ + * _RATIO=1 configurations, t_rp should be set to RoundUp(tRP/tCK). For MEM + * C_FREQ_RATIO=2 configurations, t_rp should be set to RoundDown(RoundUp(t + * RP/tCK)/2) + 1. For MEMC_FREQ_RATIO=2 configurations in LPDDR4, t_rp sho + * uld be set to RoundUp(RoundUp(tRP/tCK)/2). Unit: Clocks. + * PSU_DDRC_DRAMTMG4_T_RP 0x9 + + * SDRAM Timing Register 4 + * (OFFSET, MASK, VALUE) (0XFD070110, 0x1F0F0F1FU ,0x08030309U) + */ + PSU_Mask_Write(DDRC_DRAMTMG4_OFFSET, 0x1F0F0F1FU, 0x08030309U); +/*##################################################################### */ + + /* + * Register : DRAMTMG5 @ 0XFD070114 + + * This is the time before Self Refresh Exit that CK is maintained as a val + * id clock before issuing SRX. Specifies the clock stable time before SRX. + * Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCK + * EH - DDR2: 1 - DDR3: tCKSRX - DDR4: tCKSRX For configurations with MEMC_ + * FREQ_RATIO=2, program this to recommended value divided by two and round + * it up to next integer. + * PSU_DDRC_DRAMTMG5_T_CKSRX 0x6 + + * This is the time after Self Refresh Down Entry that CK is maintained as + * a valid clock. Specifies the clock disable delay after SRE. Recommended + * settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL - DDR2: 1 + * - DDR3: max (10 ns, 5 tCK) - DDR4: max (10 ns, 5 tCK) For configurations + * with MEMC_FREQ_RATIO=2, program this to recommended value divided by tw + * o and round it up to next integer. + * PSU_DDRC_DRAMTMG5_T_CKSRE 0x6 + + * Minimum CKE low width for Self refresh or Self refresh power down entry + * to exit timing in memory clock cycles. Recommended settings: - mDDR: tRF + * C - LPDDR2: tCKESR - LPDDR3: tCKESR - LPDDR4: max(tCKELPD, tSR) - DDR2: + * tCKE - DDR3: tCKE + 1 - DDR4: tCKE + 1 For configurations with MEMC_FREQ + * _RATIO=2, program this to recommended value divided by two and round it + * up to next integer. + * PSU_DDRC_DRAMTMG5_T_CKESR 0x4 + + * Minimum number of cycles of CKE HIGH/LOW during power-down and self refr + * esh. - LPDDR2/LPDDR3 mode: Set this to the larger of tCKE or tCKESR - LP + * DDR4 mode: Set this to the larger of tCKE, tCKELPD or tSR. - Non-LPDDR2/ + * non-LPDDR3/non-LPDDR4 designs: Set this to tCKE value. For configuration + * s with MEMC_FREQ_RATIO=2, program this to (value described above)/2 and + * round it up to the next integer value. Unit: Clocks. + * PSU_DDRC_DRAMTMG5_T_CKE 0x3 + + * SDRAM Timing Register 5 + * (OFFSET, MASK, VALUE) (0XFD070114, 0x0F0F3F1FU ,0x06060403U) + */ + PSU_Mask_Write(DDRC_DRAMTMG5_OFFSET, 0x0F0F3F1FU, 0x06060403U); +/*##################################################################### */ + + /* + * Register : DRAMTMG6 @ 0XFD070118 + + * This is the time after Deep Power Down Entry that CK is maintained as a + * valid clock. Specifies the clock disable delay after DPDE. Recommended s + * ettings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 For configurations with MEMC_ + * FREQ_RATIO=2, program this to recommended value divided by two and round + * it up to next integer. This is only present for designs supporting mDDR + * or LPDDR2/LPDDR3 devices. + * PSU_DDRC_DRAMTMG6_T_CKDPDE 0x1 + + * This is the time before Deep Power Down Exit that CK is maintained as a + * valid clock before issuing DPDX. Specifies the clock stable time before + * DPDX. Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 For config + * urations with MEMC_FREQ_RATIO=2, program this to recommended value divid + * ed by two and round it up to next integer. This is only present for desi + * gns supporting mDDR or LPDDR2 devices. + * PSU_DDRC_DRAMTMG6_T_CKDPDX 0x1 + + * This is the time before Clock Stop Exit that CK is maintained as a valid + * clock before issuing Clock Stop Exit. Specifies the clock stable time b + * efore next command after Clock Stop Exit. Recommended settings: - mDDR: + * 1 - LPDDR2: tXP + 2 - LPDDR3: tXP + 2 - LPDDR4: tXP + 2 For configuratio + * ns with MEMC_FREQ_RATIO=2, program this to recommended value divided by + * two and round it up to next integer. This is only present for designs su + * pporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices. + * PSU_DDRC_DRAMTMG6_T_CKCSX 0x4 + + * SDRAM Timing Register 6 + * (OFFSET, MASK, VALUE) (0XFD070118, 0x0F0F000FU ,0x01010004U) + */ + PSU_Mask_Write(DDRC_DRAMTMG6_OFFSET, 0x0F0F000FU, 0x01010004U); +/*##################################################################### */ + + /* + * Register : DRAMTMG7 @ 0XFD07011C + + * This is the time after Power Down Entry that CK is maintained as a valid + * clock. Specifies the clock disable delay after PDE. Recommended setting + * s: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL For configuration + * s with MEMC_FREQ_RATIO=2, program this to recommended value divided by t + * wo and round it up to next integer. This is only present for designs sup + * porting mDDR or LPDDR2/LPDDR3/LPDDR4 devices. + * PSU_DDRC_DRAMTMG7_T_CKPDE 0x6 + + * This is the time before Power Down Exit that CK is maintained as a valid + * clock before issuing PDX. Specifies the clock stable time before PDX. R + * ecommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: 2 For c + * onfigurations with MEMC_FREQ_RATIO=2, program this to recommended value + * divided by two and round it up to next integer. This is only present for + * designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices. + * PSU_DDRC_DRAMTMG7_T_CKPDX 0x6 + + * SDRAM Timing Register 7 + * (OFFSET, MASK, VALUE) (0XFD07011C, 0x00000F0FU ,0x00000606U) + */ + PSU_Mask_Write(DDRC_DRAMTMG7_OFFSET, 0x00000F0FU, 0x00000606U); +/*##################################################################### */ + + /* + * Register : DRAMTMG8 @ 0XFD070120 + + * tXS_FAST: Exit Self Refresh to ZQCL, ZQCS and MRS (only CL, WR, RTP and + * Geardown mode). For configurations with MEMC_FREQ_RATIO=2, program this + * to the above value divided by 2 and round up to next integer value. Unit + * : Multiples of 32 clocks. Note: This is applicable to only ZQCL/ZQCS com + * mands. Note: Ensure this is less than or equal to t_xs_x32. + * PSU_DDRC_DRAMTMG8_T_XS_FAST_X32 0x3 + + * tXS_ABORT: Exit Self Refresh to commands not requiring a locked DLL in S + * elf Refresh Abort. For configurations with MEMC_FREQ_RATIO=2, program th + * is to the above value divided by 2 and round up to next integer value. U + * nit: Multiples of 32 clocks. Note: Ensure this is less than or equal to + * t_xs_x32. + * PSU_DDRC_DRAMTMG8_T_XS_ABORT_X32 0x3 + + * tXSDLL: Exit Self Refresh to commands requiring a locked DLL. For config + * urations with MEMC_FREQ_RATIO=2, program this to the above value divided + * by 2 and round up to next integer value. Unit: Multiples of 32 clocks. + * Note: Used only for DDR2, DDR3 and DDR4 SDRAMs. + * PSU_DDRC_DRAMTMG8_T_XS_DLL_X32 0xd + + * tXS: Exit Self Refresh to commands not requiring a locked DLL. For confi + * gurations with MEMC_FREQ_RATIO=2, program this to the above value divide + * d by 2 and round up to next integer value. Unit: Multiples of 32 clocks. + * Note: Used only for DDR2, DDR3 and DDR4 SDRAMs. + * PSU_DDRC_DRAMTMG8_T_XS_X32 0x6 + + * SDRAM Timing Register 8 + * (OFFSET, MASK, VALUE) (0XFD070120, 0x7F7F7F7FU ,0x03030D06U) + */ + PSU_Mask_Write(DDRC_DRAMTMG8_OFFSET, 0x7F7F7F7FU, 0x03030D06U); +/*##################################################################### */ + + /* + * Register : DRAMTMG9 @ 0XFD070124 + + * DDR4 Write preamble mode - 0: 1tCK preamble - 1: 2tCK preamble Present o + * nly with MEMC_FREQ_RATIO=2 + * PSU_DDRC_DRAMTMG9_DDR4_WR_PREAMBLE 0x0 + + * tCCD_S: This is the minimum time between two reads or two writes for dif + * ferent bank group. For bank switching (from bank 'a' to bank 'b'), the m + * inimum time is this value + 1. For configurations with MEMC_FREQ_RATIO=2 + * , program this to (tCCD_S/2) and round it up to the next integer value. + * Present only in designs configured to support DDR4. Unit: clocks. + * PSU_DDRC_DRAMTMG9_T_CCD_S 0x2 + + * tRRD_S: Minimum time between activates from bank 'a' to bank 'b' for dif + * ferent bank group. For configurations with MEMC_FREQ_RATIO=2, program th + * is to (tRRD_S/2) and round it up to the next integer value. Present only + * in designs configured to support DDR4. Unit: Clocks. + * PSU_DDRC_DRAMTMG9_T_RRD_S 0x2 + + * CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command + * for different bank group. Includes time for bus turnaround, recovery ti + * mes, and all per-bank, per-rank, and global constraints. Present only in + * designs configured to support DDR4. Unit: Clocks. Where: - CWL = CAS wr + * ite latency - PL = Parity latency - BL = burst length. This must match t + * he value programmed in the BL bit of the mode register to the SDRAM - tW + * TR_S = internal write to read command delay for different bank group. Th + * is comes directly from the SDRAM specification. For configurations with + * MEMC_FREQ_RATIO=2, divide the value calculated using the above equation + * by 2, and round it up to next integer. + * PSU_DDRC_DRAMTMG9_WR2RD_S 0xb + + * SDRAM Timing Register 9 + * (OFFSET, MASK, VALUE) (0XFD070124, 0x40070F3FU ,0x0002020BU) + */ + PSU_Mask_Write(DDRC_DRAMTMG9_OFFSET, 0x40070F3FU, 0x0002020BU); +/*##################################################################### */ + + /* + * Register : DRAMTMG11 @ 0XFD07012C + + * tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DL + * L. For configurations with MEMC_FREQ_RATIO=2, program this to (tXMPDLL/2 + * ) and round it up to the next integer value. Present only in designs con + * figured to support DDR4. Unit: Multiples of 32 clocks. + * PSU_DDRC_DRAMTMG11_POST_MPSM_GAP_X32 0x70 + + * tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge. For + * configurations with MEMC_FREQ_RATIO=2, program this to RoundUp(tMPX_LH/2 + * )+1. Present only in designs configured to support DDR4. Unit: clocks. + * PSU_DDRC_DRAMTMG11_T_MPX_LH 0x7 + + * tMPX_S: Minimum time CS setup time to CKE. For configurations with MEMC_ + * FREQ_RATIO=2, program this to (tMPX_S/2) and round it up to the next int + * eger value. Present only in designs configured to support DDR4. Unit: Cl + * ocks. + * PSU_DDRC_DRAMTMG11_T_MPX_S 0x1 + + * tCKMPE: Minimum valid clock requirement after MPSM entry. Present only i + * n designs configured to support DDR4. Unit: Clocks. For configurations w + * ith MEMC_FREQ_RATIO=2, divide the value calculated using the above equat + * ion by 2, and round it up to next integer. + * PSU_DDRC_DRAMTMG11_T_CKMPE 0xe + + * SDRAM Timing Register 11 + * (OFFSET, MASK, VALUE) (0XFD07012C, 0x7F1F031FU ,0x7007010EU) + */ + PSU_Mask_Write(DDRC_DRAMTMG11_OFFSET, 0x7F1F031FU, 0x7007010EU); +/*##################################################################### */ + + /* + * Register : DRAMTMG12 @ 0XFD070130 + + * tCMDCKE: Delay from valid command to CKE input LOW. Set this to the larg + * er of tESCKE or tCMDCKE For configurations with MEMC_FREQ_RATIO=2, progr + * am this to (max(tESCKE, tCMDCKE)/2) and round it up to next integer valu + * e. + * PSU_DDRC_DRAMTMG12_T_CMDCKE 0x2 + + * tCKEHCMD: Valid command requirement after CKE input HIGH. For configurat + * ions with MEMC_FREQ_RATIO=2, program this to (tCKEHCMD/2) and round it u + * p to next integer value. + * PSU_DDRC_DRAMTMG12_T_CKEHCMD 0x6 + + * tMRD_PDA: This is the Mode Register Set command cycle time in PDA mode. + * For configurations with MEMC_FREQ_RATIO=2, program this to (tMRD_PDA/2) + * and round it up to next integer value. + * PSU_DDRC_DRAMTMG12_T_MRD_PDA 0x8 + + * SDRAM Timing Register 12 + * (OFFSET, MASK, VALUE) (0XFD070130, 0x00030F1FU ,0x00020608U) + */ + PSU_Mask_Write(DDRC_DRAMTMG12_OFFSET, 0x00030F1FU, 0x00020608U); +/*##################################################################### */ + + /* + * Register : ZQCTL0 @ 0XFD070180 + + * - 1 - Disable uMCTL2 generation of ZQCS/MPC(ZQ calibration) command. Reg + * ister DBGCMD.zq_calib_short can be used instead to issue ZQ calibration + * request from APB module. - 0 - Internally generate ZQCS/MPC(ZQ calibrati + * on) commands based on ZQCTL1.t_zq_short_interval_x1024. This is only pre + * sent for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. + * PSU_DDRC_ZQCTL0_DIS_AUTO_ZQ 0x1 + + * - 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refres + * h/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 + * or LPDDR3 or LPDDR4 mode. - 0 - Enable issuing of ZQCL/MPC(ZQ calibratio + * n) command at Self-Refresh/SR-Powerdown exit. Only applicable when run i + * n DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. This is only present + * for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. + * PSU_DDRC_ZQCTL0_DIS_SRX_ZQCL 0x0 + + * - 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQC + * L/ZQCS/MPC(ZQ calibration) commands are sent to one rank at a time with + * tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that co + * mmands to different ranks do not overlap. - 0 - ZQ resistor is not share + * d. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR + * 3/LPDDR4 devices. + * PSU_DDRC_ZQCTL0_ZQ_RESISTOR_SHARED 0x0 + + * - 1 - Disable issuing of ZQCL command at Maximum Power Saving Mode exit. + * Only applicable when run in DDR4 mode. - 0 - Enable issuing of ZQCL com + * mand at Maximum Power Saving Mode exit. Only applicable when run in DDR4 + * mode. This is only present for designs supporting DDR4 devices. + * PSU_DDRC_ZQCTL0_DIS_MPSMX_ZQCL 0x0 + + * tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Numbe + * r of cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ St + * art) command is issued to SDRAM. For configurations with MEMC_FREQ_RATIO + * =2: DDR3/DDR4: program this to tZQoper/2 and round it up to the next int + * eger value. LPDDR2/LPDDR3: program this to tZQCL/2 and round it up to th + * e next integer value. LPDDR4: program this to tZQCAL/2 and round it up t + * o the next integer value. Unit: Clock cycles. This is only present for d + * esigns supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. + * PSU_DDRC_ZQCTL0_T_ZQ_LONG_NOP 0x100 + + * tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of cycles of + * NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command + * is issued to SDRAM. For configurations with MEMC_FREQ_RATIO=2, program t + * his to tZQCS/2 and round it up to the next integer value. Unit: Clock cy + * cles. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LP + * DDR3/LPDDR4 devices. + * PSU_DDRC_ZQCTL0_T_ZQ_SHORT_NOP 0x40 + + * ZQ Control Register 0 + * (OFFSET, MASK, VALUE) (0XFD070180, 0xF7FF03FFU ,0x81000040U) + */ + PSU_Mask_Write(DDRC_ZQCTL0_OFFSET, 0xF7FF03FFU, 0x81000040U); +/*##################################################################### */ + + /* + * Register : ZQCTL1 @ 0XFD070184 + + * tZQReset: Number of cycles of NOP required after a ZQReset (ZQ calibrati + * on Reset) command is issued to SDRAM. For configurations with MEMC_FREQ_ + * RATIO=2, program this to tZQReset/2 and round it up to the next integer + * value. Unit: Clock cycles. This is only present for designs supporting L + * PDDR2/LPDDR3/LPDDR4 devices. + * PSU_DDRC_ZQCTL1_T_ZQ_RESET_NOP 0x20 + + * Average interval to wait between automatically issuing ZQCS (ZQ calibrat + * ion short)/MPC(ZQ calibration) commands to DDR3/DDR4/LPDDR2/LPDDR3/LPDDR + * 4 devices. Meaningless, if ZQCTL0.dis_auto_zq=1. Unit: 1024 clock cycles + * . This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3 + * /LPDDR4 devices. + * PSU_DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024 0x196dc + + * ZQ Control Register 1 + * (OFFSET, MASK, VALUE) (0XFD070184, 0x3FFFFFFFU ,0x020196DCU) + */ + PSU_Mask_Write(DDRC_ZQCTL1_OFFSET, 0x3FFFFFFFU, 0x020196DCU); +/*##################################################################### */ + + /* + * Register : DFITMG0 @ 0XFD070190 + + * Specifies the number of DFI clock cycles after an assertion or de-assert + * ion of the DFI control signals that the control signals at the PHY-DRAM + * interface reflect the assertion or de-assertion. If the DFI clock and th + * e memory clock are not phase-aligned, this timing parameter should be ro + * unded up to the next integer value. Note that if using RDIMM, it is nece + * ssary to increment this parameter by RDIMM's extra cycle of latency in t + * erms of DFI clock. + * PSU_DDRC_DFITMG0_DFI_T_CTRL_DELAY 0x4 + + * Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated u + * sing HDR or SDR values Selects whether value in DFITMG0.dfi_t_rddata_en + * is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles + * - 1 in terms of SDR clock cycles Refer to PHY specification for correct + * value. + * PSU_DDRC_DFITMG0_DFI_RDDATA_USE_SDR 0x1 + + * Time from the assertion of a read command on the DFI interface to the as + * sertion of the dfi_rddata_en signal. Refer to PHY specification for corr + * ect value. This corresponds to the DFI parameter trddata_en. Note that, + * depending on the PHY, if using RDIMM, it may be necessary to use the val + * ue (CL + 1) in the calculation of trddata_en. This is to compensate for + * the extra cycle of latency through the RDIMM. Unit: Clocks + * PSU_DDRC_DFITMG0_DFI_T_RDDATA_EN 0xb + + * Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated us + * ing HDR or SDR values Selects whether value in DFITMG0.dfi_tphy_wrlat is + * in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.df + * i_tphy_wrdata is in terms of SDR or HDR clock cycles - 0 in terms of HDR + * clock cycles - 1 in terms of SDR clock cycles Refer to PHY specificatio + * n for correct value. + * PSU_DDRC_DFITMG0_DFI_WRDATA_USE_SDR 0x1 + + * Specifies the number of clock cycles between when dfi_wrdata_en is asser + * ted to when the associated write data is driven on the dfi_wrdata signal + * . This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY + * specification for correct value. Note, max supported value is 8. Unit: + * Clocks + * PSU_DDRC_DFITMG0_DFI_TPHY_WRDATA 0x2 + + * Write latency Number of clocks from the write command to write data enab + * le (dfi_wrdata_en). This corresponds to the DFI timing parameter tphy_wr + * lat. Refer to PHY specification for correct value.Note that, depending o + * n the PHY, if using RDIMM, it may be necessary to use the value (CL + 1) + * in the calculation of tphy_wrlat. This is to compensate for the extra c + * ycle of latency through the RDIMM. + * PSU_DDRC_DFITMG0_DFI_TPHY_WRLAT 0xb + + * DFI Timing Register 0 + * (OFFSET, MASK, VALUE) (0XFD070190, 0x1FBFBF3FU ,0x048B820BU) + */ + PSU_Mask_Write(DDRC_DFITMG0_OFFSET, 0x1FBFBF3FU, 0x048B820BU); +/*##################################################################### */ + + /* + * Register : DFITMG1 @ 0XFD070194 + + * Specifies the number of DFI PHY clocks between when the dfi_cs signal is + * asserted and when the associated command is driven. This field is used + * for CAL mode, should be set to '0' or the value which matches the CAL mo + * de register setting in the DRAM. If the PHY can add the latency for CAL + * mode, this should be set to '0'. Valid Range: 0, 3, 4, 5, 6, and 8 + * PSU_DDRC_DFITMG1_DFI_T_CMD_LAT 0x0 + + * Specifies the number of DFI PHY clocks between when the dfi_cs signal is + * asserted and when the associated dfi_parity_in signal is driven. + * PSU_DDRC_DFITMG1_DFI_T_PARIN_LAT 0x0 + + * Specifies the number of DFI clocks between when the dfi_wrdata_en signal + * is asserted and when the corresponding write data transfer is completed + * on the DRAM bus. This corresponds to the DFI timing parameter twrdata_d + * elay. Refer to PHY specification for correct value. For DFI 3.0 PHY, set + * to twrdata_delay, a new timing parameter introduced in DFI 3.0. For DFI + * 2.1 PHY, set to tphy_wrdata + (delay of DFI write data to the DRAM). Va + * lue to be programmed is in terms of DFI clocks, not PHY clocks. In FREQ_ + * RATIO=2, divide PHY's value by 2 and round up to next integer. If using + * DFITMG0.dfi_wrdata_use_sdr=1, add 1 to the value. Unit: Clocks + * PSU_DDRC_DFITMG1_DFI_T_WRDATA_DELAY 0x3 + + * Specifies the number of DFI clock cycles from the assertion of the dfi_d + * ram_clk_disable signal on the DFI until the clock to the DRAM memory dev + * ices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock + * and the memory clock are not phase aligned, this timing parameter should + * be rounded up to the next integer value. + * PSU_DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE 0x3 + + * Specifies the number of DFI clock cycles from the de-assertion of the df + * i_dram_clk_disable signal on the DFI until the first valid rising edge o + * f the clock to the DRAM memory devices, at the PHY-DRAM boundary. If the + * DFI clock and the memory clock are not phase aligned, this timing param + * eter should be rounded up to the next integer value. + * PSU_DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE 0x4 + + * DFI Timing Register 1 + * (OFFSET, MASK, VALUE) (0XFD070194, 0xF31F0F0FU ,0x00030304U) + */ + PSU_Mask_Write(DDRC_DFITMG1_OFFSET, 0xF31F0F0FU, 0x00030304U); +/*##################################################################### */ + + /* + * Register : DFILPCFG0 @ 0XFD070198 + + * Setting for DFI's tlp_resp time. Same value is used for both Power Down, + * Self Refresh, Deep Power Down and Maximum Power Saving modes. DFI 2.1 s + * pecification onwards, recommends using a fixed value of 7 always. + * PSU_DDRC_DFILPCFG0_DFI_TLP_RESP 0x7 + + * Value to drive on dfi_lp_wakeup signal when Deep Power Down mode is ente + * red. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32 + * cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 5 + * 12 cycles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycles - + * 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 6553 + * 6 cycles - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited T + * his is only present for designs supporting mDDR or LPDDR2/LPDDR3 devices + * . + * PSU_DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD 0x0 + + * Enables DFI Low Power interface handshaking during Deep Power Down Entry + * /Exit. - 0 - Disabled - 1 - Enabled This is only present for designs sup + * porting mDDR or LPDDR2/LPDDR3 devices. + * PSU_DDRC_DFILPCFG0_DFI_LP_EN_DPD 0x0 + + * Value to drive on dfi_lp_wakeup signal when Self Refresh mode is entered + * . Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32 cyc + * les - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 + * cycles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycles - 0x9 + * - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 c + * ycles - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited + * PSU_DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR 0x0 + + * Enables DFI Low Power interface handshaking during Self Refresh Entry/Ex + * it. - 0 - Disabled - 1 - Enabled + * PSU_DDRC_DFILPCFG0_DFI_LP_EN_SR 0x1 + + * Value to drive on dfi_lp_wakeup signal when Power Down mode is entered. + * Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32 cycle + * s - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cy + * cles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycles - 0x9 - + * 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cyc + * les - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited + * PSU_DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD 0x0 + + * Enables DFI Low Power interface handshaking during Power Down Entry/Exit + * . - 0 - Disabled - 1 - Enabled + * PSU_DDRC_DFILPCFG0_DFI_LP_EN_PD 0x1 + + * DFI Low Power Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD070198, 0x0FF1F1F1U ,0x07000101U) + */ + PSU_Mask_Write(DDRC_DFILPCFG0_OFFSET, 0x0FF1F1F1U, 0x07000101U); +/*##################################################################### */ + + /* + * Register : DFILPCFG1 @ 0XFD07019C + + * Value to drive on dfi_lp_wakeup signal when Maximum Power Saving Mode is + * entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 + * - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x + * 5 - 512 cycles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycl + * es - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - + * 65536 cycles - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimi + * ted This is only present for designs supporting DDR4 devices. + * PSU_DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM 0x2 + + * Enables DFI Low Power interface handshaking during Maximum Power Saving + * Mode Entry/Exit. - 0 - Disabled - 1 - Enabled This is only present for d + * esigns supporting DDR4 devices. + * PSU_DDRC_DFILPCFG1_DFI_LP_EN_MPSM 0x1 + + * DFI Low Power Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD07019C, 0x000000F1U ,0x00000021U) + */ + PSU_Mask_Write(DDRC_DFILPCFG1_OFFSET, 0x000000F1U, 0x00000021U); +/*##################################################################### */ + + /* + * Register : DFIUPD0 @ 0XFD0701A0 + + * When '1', disable the automatic dfi_ctrlupd_req generation by the uMCTL2 + * . The core must issue the dfi_ctrlupd_req signal using register reg_ddrc + * _ctrlupd. When '0', uMCTL2 issues dfi_ctrlupd_req periodically. + * PSU_DDRC_DFIUPD0_DIS_AUTO_CTRLUPD 0x0 + + * When '1', disable the automatic dfi_ctrlupd_req generation by the uMCTL2 + * following a self-refresh exit. The core must issue the dfi_ctrlupd_req + * signal using register reg_ddrc_ctrlupd. When '0', uMCTL2 issues a dfi_ct + * rlupd_req after exiting self-refresh. + * PSU_DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX 0x0 + + * Specifies the maximum number of clock cycles that the dfi_ctrlupd_req si + * gnal can assert. Lowest value to assign to this variable is 0x40. Unit: + * Clocks + * PSU_DDRC_DFIUPD0_DFI_T_CTRLUP_MAX 0x40 + + * Specifies the minimum number of clock cycles that the dfi_ctrlupd_req si + * gnal must be asserted. The uMCTL2 expects the PHY to respond within this + * time. If the PHY does not respond, the uMCTL2 will de-assert dfi_ctrlup + * d_req after dfi_t_ctrlup_min + 2 cycles. Lowest value to assign to this + * variable is 0x3. Unit: Clocks + * PSU_DDRC_DFIUPD0_DFI_T_CTRLUP_MIN 0x3 + + * DFI Update Register 0 + * (OFFSET, MASK, VALUE) (0XFD0701A0, 0xC3FF03FFU ,0x00400003U) + */ + PSU_Mask_Write(DDRC_DFIUPD0_OFFSET, 0xC3FF03FFU, 0x00400003U); +/*##################################################################### */ + + /* + * Register : DFIUPD1 @ 0XFD0701A4 + + * This is the minimum amount of time between uMCTL2 initiated DFI update r + * equests (which is executed whenever the uMCTL2 is idle). Set this number + * higher to reduce the frequency of update requests, which can have a sma + * ll impact on the latency of the first read request when the uMCTL2 is id + * le. Unit: 1024 clocks + * PSU_DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024 0x41 + + * This is the maximum amount of time between uMCTL2 initiated DFI update r + * equests. This timer resets with each update request; when the timer expi + * res dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd + * _ackx is received. PHY can use this idle time to recalibrate the delay l + * ines to the DLLs. The DFI controller update is also used to reset PHY FI + * FO pointers in case of data capture errors. Updates are required to main + * tain calibration over PVT, but frequent updates may impact performance. + * Note: Value programmed for DFIUPD1.dfi_t_ctrlupd_interval_max_x1024 must + * be greater than DFIUPD1.dfi_t_ctrlupd_interval_min_x1024. Unit: 1024 cl + * ocks + * PSU_DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024 0xe1 + + * DFI Update Register 1 + * (OFFSET, MASK, VALUE) (0XFD0701A4, 0x00FF00FFU ,0x004100E1U) + */ + PSU_Mask_Write(DDRC_DFIUPD1_OFFSET, 0x00FF00FFU, 0x004100E1U); +/*##################################################################### */ + + /* + * Register : DFIMISC @ 0XFD0701B0 + + * Defines polarity of dfi_wrdata_cs and dfi_rddata_cs signals. - 0: Signal + * s are active low - 1: Signals are active high + * PSU_DDRC_DFIMISC_DFI_DATA_CS_POLARITY 0x0 + + * DBI implemented in DDRC or PHY. - 0 - DDRC implements DBI functionality. + * - 1 - PHY implements DBI functionality. Present only in designs configu + * red to support DDR4 and LPDDR4. + * PSU_DDRC_DFIMISC_PHY_DBI_MODE 0x0 + + * PHY initialization complete enable signal. When asserted the dfi_init_co + * mplete signal can be used to trigger SDRAM initialisation + * PSU_DDRC_DFIMISC_DFI_INIT_COMPLETE_EN 0x0 + + * DFI Miscellaneous Control Register + * (OFFSET, MASK, VALUE) (0XFD0701B0, 0x00000007U ,0x00000000U) + */ + PSU_Mask_Write(DDRC_DFIMISC_OFFSET, 0x00000007U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : DFITMG2 @ 0XFD0701B4 + + * >Number of clocks between when a read command is sent on the DFI control + * interface and when the associated dfi_rddata_cs signal is asserted. Thi + * s corresponds to the DFI timing parameter tphy_rdcslat. Refer to PHY spe + * cification for correct value. + * PSU_DDRC_DFITMG2_DFI_TPHY_RDCSLAT 0x9 + + * Number of clocks between when a write command is sent on the DFI control + * interface and when the associated dfi_wrdata_cs signal is asserted. Thi + * s corresponds to the DFI timing parameter tphy_wrcslat. Refer to PHY spe + * cification for correct value. + * PSU_DDRC_DFITMG2_DFI_TPHY_WRCSLAT 0x6 + + * DFI Timing Register 2 + * (OFFSET, MASK, VALUE) (0XFD0701B4, 0x00003F3FU ,0x00000906U) + */ + PSU_Mask_Write(DDRC_DFITMG2_OFFSET, 0x00003F3FU, 0x00000906U); +/*##################################################################### */ + + /* + * Register : DBICTL @ 0XFD0701C0 + + * Read DBI enable signal in DDRC. - 0 - Read DBI is disabled. - 1 - Read D + * BI is enabled. This signal must be set the same value as DRAM's mode reg + * ister. - DDR4: MR5 bit A12. When x4 devices are used, this signal must b + * e set to 0. - LPDDR4: MR3[6] + * PSU_DDRC_DBICTL_RD_DBI_EN 0x0 + + * Write DBI enable signal in DDRC. - 0 - Write DBI is disabled. - 1 - Writ + * e DBI is enabled. This signal must be set the same value as DRAM's mode + * register. - DDR4: MR5 bit A11. When x4 devices are used, this signal mus + * t be set to 0. - LPDDR4: MR3[7] + * PSU_DDRC_DBICTL_WR_DBI_EN 0x0 + + * DM enable signal in DDRC. - 0 - DM is disabled. - 1 - DM is enabled. Thi + * s signal must be set the same logical value as DRAM's mode register. - D + * DR4: Set this to same value as MR5 bit A10. When x4 devices are used, th + * is signal must be set to 0. - LPDDR4: Set this to inverted value of MR13 + * [5] which is opposite polarity from this signal + * PSU_DDRC_DBICTL_DM_EN 0x1 + + * DM/DBI Control Register + * (OFFSET, MASK, VALUE) (0XFD0701C0, 0x00000007U ,0x00000001U) + */ + PSU_Mask_Write(DDRC_DBICTL_OFFSET, 0x00000007U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : ADDRMAP0 @ 0XFD070200 + + * Selects the HIF address bit used as rank address bit 0. Valid Range: 0 t + * o 27, and 31 Internal Base: 6 The selected HIF address bit is determined + * by adding the internal base to the value of this field. If set to 31, r + * ank address bit 0 is set to 0. + * PSU_DDRC_ADDRMAP0_ADDRMAP_CS_BIT0 0x1f + + * Address Map Register 0 + * (OFFSET, MASK, VALUE) (0XFD070200, 0x0000001FU ,0x0000001FU) + */ + PSU_Mask_Write(DDRC_ADDRMAP0_OFFSET, 0x0000001FU, 0x0000001FU); +/*##################################################################### */ + + /* + * Register : ADDRMAP1 @ 0XFD070204 + + * Selects the HIF address bit used as bank address bit 2. Valid Range: 0 t + * o 29 and 31 Internal Base: 4 The selected HIF address bit is determined + * by adding the internal base to the value of this field. If set to 31, ba + * nk address bit 2 is set to 0. + * PSU_DDRC_ADDRMAP1_ADDRMAP_BANK_B2 0x1f + + * Selects the HIF address bits used as bank address bit 1. Valid Range: 0 + * to 30 Internal Base: 3 The selected HIF address bit for each of the bank + * address bits is determined by adding the internal base to the value of + * this field. + * PSU_DDRC_ADDRMAP1_ADDRMAP_BANK_B1 0xa + + * Selects the HIF address bits used as bank address bit 0. Valid Range: 0 + * to 30 Internal Base: 2 The selected HIF address bit for each of the bank + * address bits is determined by adding the internal base to the value of + * this field. + * PSU_DDRC_ADDRMAP1_ADDRMAP_BANK_B0 0xa + + * Address Map Register 1 + * (OFFSET, MASK, VALUE) (0XFD070204, 0x001F1F1FU ,0x001F0A0AU) + */ + PSU_Mask_Write(DDRC_ADDRMAP1_OFFSET, 0x001F1F1FU, 0x001F0A0AU); +/*##################################################################### */ + + /* + * Register : ADDRMAP2 @ 0XFD070208 + + * - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 5. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 6. - Quarter bus width mode: Selects the HIF address bit + * used as column address bit 7 . Valid Range: 0 to 7, and 15 Internal Base + * : 5 The selected HIF address bit is determined by adding the internal ba + * se to the value of this field. If set to 15, this column address bit is + * set to 0. + * PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B5 0x0 + + * - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 4. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 5. - Quarter bus width mode: Selects the HIF address bit + * used as column address bit 6. Valid Range: 0 to 7, and 15 Internal Base: + * 4 The selected HIF address bit is determined by adding the internal bas + * e to the value of this field. If set to 15, this column address bit is s + * et to 0. + * PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B4 0x0 + + * - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 3. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 4. - Quarter bus width mode: Selects the HIF address bit + * used as column address bit 5. Valid Range: 0 to 7 Internal Base: 3 The s + * elected HIF address bit is determined by adding the internal base to the + * value of this field. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=1 + * 6, it is required to program this to 0, hence register does not exist in + * this case. + * PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B3 0x0 + + * - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 2. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 3. - Quarter bus width mode: Selects the HIF address bit + * used as column address bit 4. Valid Range: 0 to 7 Internal Base: 2 The s + * elected HIF address bit is determined by adding the internal base to the + * value of this field. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=8 + * or 16, it is required to program this to 0. + * PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B2 0x0 + + * Address Map Register 2 + * (OFFSET, MASK, VALUE) (0XFD070208, 0x0F0F0F0FU ,0x00000000U) + */ + PSU_Mask_Write(DDRC_ADDRMAP2_OFFSET, 0x0F0F0F0FU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ADDRMAP3 @ 0XFD07020C + + * - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 9. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 11 (10 in LPDDR2/LPDDR3 mode). - Quarter bus width mode: + * Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/ + * LPDDR3 mode). Valid Range: 0 to 7, and 15 Internal Base: 9 The selected + * HIF address bit is determined by adding the internal base to the value o + * f this field. If set to 15, this column address bit is set to 0. Note: P + * er JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved fo + * r indicating auto-precharge, and hence no source address bit can be mapp + * ed to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit + * for auto-precharge in the CA bus and hence column bit 10 is used. + * PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B9 0x0 + + * - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 8. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 9. - Quarter bus width mode: Selects the HIF address bit + * used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). Valid Range: 0 + * to 7, and 15 Internal Base: 8 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specifi + * cation, column address bit 10 is reserved for indicating auto-precharge, + * and hence no source address bit can be mapped to column address bit 10. + * In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA + * bus and hence column bit 10 is used. + * PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B8 0x0 + + * - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 7. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 8. - Quarter bus width mode: Selects the HIF address bit + * used as column address bit 9. Valid Range: 0 to 7, and 15 Internal Base: + * 7 The selected HIF address bit is determined by adding the internal bas + * e to the value of this field. If set to 15, this column address bit is s + * et to 0. + * PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B7 0x0 + + * - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 6. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 7. - Quarter bus width mode: Selects the HIF address bit + * used as column address bit 8. Valid Range: 0 to 7, and 15 Internal Base: + * 6 The selected HIF address bit is determined by adding the internal bas + * e to the value of this field. If set to 15, this column address bit is s + * et to 0. + * PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B6 0x0 + + * Address Map Register 3 + * (OFFSET, MASK, VALUE) (0XFD07020C, 0x0F0F0F0FU ,0x00000000U) + */ + PSU_Mask_Write(DDRC_ADDRMAP3_OFFSET, 0x0F0F0F0FU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ADDRMAP4 @ 0XFD070210 + + * - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 13 (11 in LPDDR2/LPDDR3 mode). - Half bus width mode: Unused. To m + * ake it unused, this should be tied to 4'hF. - Quarter bus width mode: Un + * used. To make it unused, this must be tied to 4'hF. Valid Range: 0 to 7, + * and 15 Internal Base: 11 The selected HIF address bit is determined by + * adding the internal base to the value of this field. If set to 15, this + * column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specificatio + * n, column address bit 10 is reserved for indicating auto-precharge, and + * hence no source address bit can be mapped to column address bit 10. In L + * PDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus + * and hence column bit 10 is used. + * PSU_DDRC_ADDRMAP4_ADDRMAP_COL_B11 0xf + + * - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 11 (10 in LPDDR2/LPDDR3 mode). - Half bus width mode: Selects the + * HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode) + * . - Quarter bus width mode: UNUSED. To make it unused, this must be tied + * to 4'hF. Valid Range: 0 to 7, and 15 Internal Base: 10 The selected HIF + * address bit is determined by adding the internal base to the value of t + * his field. If set to 15, this column address bit is set to 0. Note: Per + * JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for i + * ndicating auto-precharge, and hence no source address bit can be mapped + * to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for + * auto-precharge in the CA bus and hence column bit 10 is used. + * PSU_DDRC_ADDRMAP4_ADDRMAP_COL_B10 0xf + + * Address Map Register 4 + * (OFFSET, MASK, VALUE) (0XFD070210, 0x00000F0FU ,0x00000F0FU) + */ + PSU_Mask_Write(DDRC_ADDRMAP4_OFFSET, 0x00000F0FU, 0x00000F0FU); +/*##################################################################### */ + + /* + * Register : ADDRMAP5 @ 0XFD070214 + + * Selects the HIF address bit used as row address bit 11. Valid Range: 0 t + * o 11, and 15 Internal Base: 17 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * row address bit 11 is set to 0. + * PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B11 0x8 + + * Selects the HIF address bits used as row address bits 2 to 10. Valid Ran + * ge: 0 to 11, and 15 Internal Base: 8 (for row address bit 2), 9 (for row + * address bit 3), 10 (for row address bit 4) etc increasing to 16 (for ro + * w address bit 10) The selected HIF address bit for each of the row addre + * ss bits is determined by adding the internal base to the value of this f + * ield. When value 15 is used the values of row address bits 2 to 10 are d + * efined by registers ADDRMAP9, ADDRMAP10, ADDRMAP11. + * PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10 0xf + + * Selects the HIF address bits used as row address bit 1. Valid Range: 0 t + * o 11 Internal Base: 7 The selected HIF address bit for each of the row a + * ddress bits is determined by adding the internal base to the value of th + * is field. + * PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B1 0x8 + + * Selects the HIF address bits used as row address bit 0. Valid Range: 0 t + * o 11 Internal Base: 6 The selected HIF address bit for each of the row a + * ddress bits is determined by adding the internal base to the value of th + * is field. + * PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B0 0x8 + + * Address Map Register 5 + * (OFFSET, MASK, VALUE) (0XFD070214, 0x0F0F0F0FU ,0x080F0808U) + */ + PSU_Mask_Write(DDRC_ADDRMAP5_OFFSET, 0x0F0F0F0FU, 0x080F0808U); +/*##################################################################### */ + + /* + * Register : ADDRMAP6 @ 0XFD070218 + + * Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use. - 1 + * - LPDDR3 SDRAM 6Gb/12Gb device in use. Every address having row[14:13]= + * =2'b11 is considered as invalid - 0 - non-LPDDR3 6Gb/12Gb device in use. + * All addresses are valid Present only in designs configured to support L + * PDDR3. + * PSU_DDRC_ADDRMAP6_LPDDR3_6GB_12GB 0x0 + + * Selects the HIF address bit used as row address bit 15. Valid Range: 0 t + * o 11, and 15 Internal Base: 21 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * row address bit 15 is set to 0. + * PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B15 0xf + + * Selects the HIF address bit used as row address bit 14. Valid Range: 0 t + * o 11, and 15 Internal Base: 20 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * row address bit 14 is set to 0. + * PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B14 0x8 + + * Selects the HIF address bit used as row address bit 13. Valid Range: 0 t + * o 11, and 15 Internal Base: 19 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * row address bit 13 is set to 0. + * PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B13 0x8 + + * Selects the HIF address bit used as row address bit 12. Valid Range: 0 t + * o 11, and 15 Internal Base: 18 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * row address bit 12 is set to 0. + * PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B12 0x8 + + * Address Map Register 6 + * (OFFSET, MASK, VALUE) (0XFD070218, 0x8F0F0F0FU ,0x0F080808U) + */ + PSU_Mask_Write(DDRC_ADDRMAP6_OFFSET, 0x8F0F0F0FU, 0x0F080808U); +/*##################################################################### */ + + /* + * Register : ADDRMAP7 @ 0XFD07021C + + * Selects the HIF address bit used as row address bit 17. Valid Range: 0 t + * o 10, and 15 Internal Base: 23 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * row address bit 17 is set to 0. + * PSU_DDRC_ADDRMAP7_ADDRMAP_ROW_B17 0xf + + * Selects the HIF address bit used as row address bit 16. Valid Range: 0 t + * o 11, and 15 Internal Base: 22 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * row address bit 16 is set to 0. + * PSU_DDRC_ADDRMAP7_ADDRMAP_ROW_B16 0xf + + * Address Map Register 7 + * (OFFSET, MASK, VALUE) (0XFD07021C, 0x00000F0FU ,0x00000F0FU) + */ + PSU_Mask_Write(DDRC_ADDRMAP7_OFFSET, 0x00000F0FU, 0x00000F0FU); +/*##################################################################### */ + + /* + * Register : ADDRMAP8 @ 0XFD070220 + + * Selects the HIF address bits used as bank group address bit 1. Valid Ran + * ge: 0 to 30, and 31 Internal Base: 3 The selected HIF address bit for ea + * ch of the bank group address bits is determined by adding the internal b + * ase to the value of this field. If set to 31, bank group address bit 1 i + * s set to 0. + * PSU_DDRC_ADDRMAP8_ADDRMAP_BG_B1 0x8 + + * Selects the HIF address bits used as bank group address bit 0. Valid Ran + * ge: 0 to 30 Internal Base: 2 The selected HIF address bit for each of th + * e bank group address bits is determined by adding the internal base to t + * he value of this field. + * PSU_DDRC_ADDRMAP8_ADDRMAP_BG_B0 0x8 + + * Address Map Register 8 + * (OFFSET, MASK, VALUE) (0XFD070220, 0x00001F1FU ,0x00000808U) + */ + PSU_Mask_Write(DDRC_ADDRMAP8_OFFSET, 0x00001F1FU, 0x00000808U); +/*##################################################################### */ + + /* + * Register : ADDRMAP9 @ 0XFD070224 + + * Selects the HIF address bits used as row address bit 5. Valid Range: 0 t + * o 11 Internal Base: 11 The selected HIF address bit for each of the row + * address bits is determined by adding the internal base to the value of t + * his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + * _10 is set to value 15. + * PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B5 0x8 + + * Selects the HIF address bits used as row address bit 4. Valid Range: 0 t + * o 11 Internal Base: 10 The selected HIF address bit for each of the row + * address bits is determined by adding the internal base to the value of t + * his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + * _10 is set to value 15. + * PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B4 0x8 + + * Selects the HIF address bits used as row address bit 3. Valid Range: 0 t + * o 11 Internal Base: 9 The selected HIF address bit for each of the row a + * ddress bits is determined by adding the internal base to the value of th + * is field. This register field is used only when ADDRMAP5.addrmap_row_b2_ + * 10 is set to value 15. + * PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B3 0x8 + + * Selects the HIF address bits used as row address bit 2. Valid Range: 0 t + * o 11 Internal Base: 8 The selected HIF address bit for each of the row a + * ddress bits is determined by adding the internal base to the value of th + * is field. This register field is used only when ADDRMAP5.addrmap_row_b2_ + * 10 is set to value 15. + * PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B2 0x8 + + * Address Map Register 9 + * (OFFSET, MASK, VALUE) (0XFD070224, 0x0F0F0F0FU ,0x08080808U) + */ + PSU_Mask_Write(DDRC_ADDRMAP9_OFFSET, 0x0F0F0F0FU, 0x08080808U); +/*##################################################################### */ + + /* + * Register : ADDRMAP10 @ 0XFD070228 + + * Selects the HIF address bits used as row address bit 9. Valid Range: 0 t + * o 11 Internal Base: 15 The selected HIF address bit for each of the row + * address bits is determined by adding the internal base to the value of t + * his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + * _10 is set to value 15. + * PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B9 0x8 + + * Selects the HIF address bits used as row address bit 8. Valid Range: 0 t + * o 11 Internal Base: 14 The selected HIF address bit for each of the row + * address bits is determined by adding the internal base to the value of t + * his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + * _10 is set to value 15. + * PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B8 0x8 + + * Selects the HIF address bits used as row address bit 7. Valid Range: 0 t + * o 11 Internal Base: 13 The selected HIF address bit for each of the row + * address bits is determined by adding the internal base to the value of t + * his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + * _10 is set to value 15. + * PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B7 0x8 + + * Selects the HIF address bits used as row address bit 6. Valid Range: 0 t + * o 11 Internal Base: 12 The selected HIF address bit for each of the row + * address bits is determined by adding the internal base to the value of t + * his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + * _10 is set to value 15. + * PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B6 0x8 + + * Address Map Register 10 + * (OFFSET, MASK, VALUE) (0XFD070228, 0x0F0F0F0FU ,0x08080808U) + */ + PSU_Mask_Write(DDRC_ADDRMAP10_OFFSET, 0x0F0F0F0FU, 0x08080808U); +/*##################################################################### */ + + /* + * Register : ADDRMAP11 @ 0XFD07022C + + * Selects the HIF address bits used as row address bit 10. Valid Range: 0 + * to 11 Internal Base: 16 The selected HIF address bit for each of the row + * address bits is determined by adding the internal base to the value of + * this field. This register field is used only when ADDRMAP5.addrmap_row_b + * 2_10 is set to value 15. + * PSU_DDRC_ADDRMAP11_ADDRMAP_ROW_B10 0x8 + + * Address Map Register 11 + * (OFFSET, MASK, VALUE) (0XFD07022C, 0x0000000FU ,0x00000008U) + */ + PSU_Mask_Write(DDRC_ADDRMAP11_OFFSET, 0x0000000FU, 0x00000008U); +/*##################################################################### */ + + /* + * Register : ODTCFG @ 0XFD070240 + + * Cycles to hold ODT for a write command. The minimum supported value is 2 + * . Recommended values: DDR2: - BL8: 0x5 (DDR2-400/533/667), 0x6 (DDR2-800 + * ), 0x7 (DDR2-1066) - BL4: 0x3 (DDR2-400/533/667), 0x4 (DDR2-800), 0x5 (D + * DR2-1066) DDR3: - BL8: 0x6 DDR4: - BL8: 5 + WR_PREAMBLE + CRC_MODE WR_PR + * EAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) CRC_MODE = 0 ( + * not CRC mode), 1 (CRC mode) LPDDR3: - BL8: 7 + RU(tODTon(max)/tCK) + * PSU_DDRC_ODTCFG_WR_ODT_HOLD 0x6 + + * The delay, in clock cycles, from issuing a write command to setting ODT + * values associated with that command. ODT setting must remain constant fo + * r the entire time that DQS is driven by the uMCTL2. Recommended values: + * DDR2: - CWL + AL - 3 (DDR2-400/533/667), CWL + AL - 4 (DDR2-800), CWL + + * AL - 5 (DDR2-1066) If (CWL + AL - 3 < 0), uMCTL2 does not support ODT fo + * r write operation. DDR3: - 0x0 DDR4: - DFITMG1.dfi_t_cmd_lat (to adjust + * for CAL mode) LPDDR3: - WL - 1 - RU(tODTon(max)/tCK)) + * PSU_DDRC_ODTCFG_WR_ODT_DELAY 0x0 + + * Cycles to hold ODT for a read command. The minimum supported value is 2. + * Recommended values: DDR2: - BL8: 0x6 (not DDR2-1066), 0x7 (DDR2-1066) - + * BL4: 0x4 (not DDR2-1066), 0x5 (DDR2-1066) DDR3: - BL8 - 0x6 DDR4: - BL8 + * : 5 + RD_PREAMBLE RD_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write p + * reamble) LPDDR3: - BL8: 5 + RU(tDQSCK(max)/tCK) - RD(tDQSCK(min)/tCK) + + * RU(tODTon(max)/tCK) + * PSU_DDRC_ODTCFG_RD_ODT_HOLD 0x6 + + * The delay, in clock cycles, from issuing a read command to setting ODT v + * alues associated with that command. ODT setting must remain constant for + * the entire time that DQS is driven by the uMCTL2. Recommended values: D + * DR2: - CL + AL - 4 (not DDR2-1066), CL + AL - 5 (DDR2-1066) If (CL + AL + * - 4 < 0), uMCTL2 does not support ODT for read operation. DDR3: - CL - C + * WL DDR4: - CL - CWL - RD_PREAMBLE + WR_PREAMBLE + DFITMG1.dfi_t_cmd_lat + * (to adjust for CAL mode) WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK + * write preamble) RD_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write pre + * amble) If (CL - CWL - RD_PREAMBLE + WR_PREAMBLE) < 0, uMCTL2 does not su + * pport ODT for read operation. LPDDR3: - RL + RD(tDQSCK(min)/tCK) - 1 - R + * U(tODTon(max)/tCK) + * PSU_DDRC_ODTCFG_RD_ODT_DELAY 0x0 + + * ODT Configuration Register + * (OFFSET, MASK, VALUE) (0XFD070240, 0x0F1F0F7CU ,0x06000600U) + */ + PSU_Mask_Write(DDRC_ODTCFG_OFFSET, 0x0F1F0F7CU, 0x06000600U); +/*##################################################################### */ + + /* + * Register : ODTMAP @ 0XFD070244 + + * Indicates which remote ODTs must be turned on during a read from rank 1. + * Each rank has a remote ODT (in the SDRAM) which can be turned on by set + * ting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 i + * s controlled by bit next to the LSB, etc. For each rank, set its bit to + * 1 to enable its ODT. Present only in configurations that have 2 or more + * ranks + * PSU_DDRC_ODTMAP_RANK1_RD_ODT 0x0 + + * Indicates which remote ODTs must be turned on during a write to rank 1. + * Each rank has a remote ODT (in the SDRAM) which can be turned on by sett + * ing the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is + * controlled by bit next to the LSB, etc. For each rank, set its bit to 1 + * to enable its ODT. Present only in configurations that have 2 or more r + * anks + * PSU_DDRC_ODTMAP_RANK1_WR_ODT 0x0 + + * Indicates which remote ODTs must be turned on during a read from rank 0. + * Each rank has a remote ODT (in the SDRAM) which can be turned on by set + * ting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 i + * s controlled by bit next to the LSB, etc. For each rank, set its bit to + * 1 to enable its ODT. + * PSU_DDRC_ODTMAP_RANK0_RD_ODT 0x0 + + * Indicates which remote ODTs must be turned on during a write to rank 0. + * Each rank has a remote ODT (in the SDRAM) which can be turned on by sett + * ing the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is + * controlled by bit next to the LSB, etc. For each rank, set its bit to 1 + * to enable its ODT. + * PSU_DDRC_ODTMAP_RANK0_WR_ODT 0x1 + + * ODT/Rank Map Register + * (OFFSET, MASK, VALUE) (0XFD070244, 0x00003333U ,0x00000001U) + */ + PSU_Mask_Write(DDRC_ODTMAP_OFFSET, 0x00003333U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : SCHED @ 0XFD070250 + + * When the preferred transaction store is empty for these many clock cycle + * s, switch to the alternate transaction store if it is non-empty. The rea + * d transaction store (both high and low priority) is the default preferre + * d transaction store and the write transaction store is the alternative s + * tore. When prefer write over read is set this is reversed. 0x0 is a lega + * l value for this register. When set to 0x0, the transaction store switch + * ing will happen immediately when the switching conditions become true. F + * OR PERFORMANCE ONLY + * PSU_DDRC_SCHED_RDWR_IDLE_GAP 0x1 + + * UNUSED + * PSU_DDRC_SCHED_GO2CRITICAL_HYSTERESIS 0x0 + + * Number of entries in the low priority transaction store is this value + + * 1. (MEMC_NO_OF_ENTRY - (SCHED.lpr_num_entries + 1)) is the number of ent + * ries available for the high priority transaction store. Setting this to + * maximum value allocates all entries to low priority transaction store. S + * etting this to 0 allocates 1 entry to low priority transaction store and + * the rest to high priority transaction store. Note: In ECC configuration + * s, the numbers of write and low priority read credits issued is one less + * than in the non-ECC case. One entry each is reserved in the write and l + * ow-priority read CAMs for storing the RMW requests arising out of single + * bit error correction RMW operation. + * PSU_DDRC_SCHED_LPR_NUM_ENTRIES 0x20 + + * If true, bank is kept open only while there are page hit transactions av + * ailable in the CAM to that bank. The last read or write command in the C + * AM with a bank and page hit will be executed with auto-precharge if SCHE + * D1.pageclose_timer=0. Even if this register set to 1 and SCHED1.pageclos + * e_timer is set to 0, explicit precharge (and not auto-precharge) may be + * issued in some cases where there is a mode switch between Write and Read + * or between LPR and HPR. The Read and Write commands that are executed a + * s part of the ECC scrub requests are also executed without auto-precharg + * e. If false, the bank remains open until there is a need to close it (to + * open a different page, or for page timeout or refresh timeout) - also k + * nown as open page policy. The open page policy can be overridden by sett + * ing the per-command-autopre bit on the HIF interface (hif_cmd_autopre). + * The pageclose feature provids a midway between Open and Close page polic + * ies. FOR PERFORMANCE ONLY. + * PSU_DDRC_SCHED_PAGECLOSE 0x0 + + * If set then the bank selector prefers writes over reads. FOR DEBUG ONLY. + * PSU_DDRC_SCHED_PREFER_WRITE 0x0 + + * Active low signal. When asserted ('0'), all incoming transactions are fo + * rced to low priority. This implies that all High Priority Read (HPR) and + * Variable Priority Read commands (VPR) will be treated as Low Priority R + * ead (LPR) commands. On the write side, all Variable Priority Write (VPW) + * commands will be treated as Normal Priority Write (NPW) commands. Forci + * ng the incoming transactions to low priority implicitly turns off Bypass + * path for read commands. FOR PERFORMANCE ONLY. + * PSU_DDRC_SCHED_FORCE_LOW_PRI_N 0x1 + + * Scheduler Control Register + * (OFFSET, MASK, VALUE) (0XFD070250, 0x7FFF3F07U ,0x01002001U) + */ + PSU_Mask_Write(DDRC_SCHED_OFFSET, 0x7FFF3F07U, 0x01002001U); +/*##################################################################### */ + + /* + * Register : PERFLPR1 @ 0XFD070264 + + * Number of transactions that are serviced once the LPR queue goes critica + * l is the smaller of: - (a) This number - (b) Number of transactions avai + * lable. Unit: Transaction. FOR PERFORMANCE ONLY. + * PSU_DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH 0x8 + + * Number of clocks that the LPR queue can be starved before it goes critic + * al. The minimum valid functional value for this register is 0x1. Program + * ming it to 0x0 will disable the starvation functionality; during normal + * operation, this function should not be disabled as it will cause excessi + * ve latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY. + * PSU_DDRC_PERFLPR1_LPR_MAX_STARVE 0x40 + + * Low Priority Read CAM Register 1 + * (OFFSET, MASK, VALUE) (0XFD070264, 0xFF00FFFFU ,0x08000040U) + */ + PSU_Mask_Write(DDRC_PERFLPR1_OFFSET, 0xFF00FFFFU, 0x08000040U); +/*##################################################################### */ + + /* + * Register : PERFWR1 @ 0XFD07026C + + * Number of transactions that are serviced once the WR queue goes critical + * is the smaller of: - (a) This number - (b) Number of transactions avail + * able. Unit: Transaction. FOR PERFORMANCE ONLY. + * PSU_DDRC_PERFWR1_W_XACT_RUN_LENGTH 0x8 + + * Number of clocks that the WR queue can be starved before it goes critica + * l. The minimum valid functional value for this register is 0x1. Programm + * ing it to 0x0 will disable the starvation functionality; during normal o + * peration, this function should not be disabled as it will cause excessiv + * e latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY. + * PSU_DDRC_PERFWR1_W_MAX_STARVE 0x40 + + * Write CAM Register 1 + * (OFFSET, MASK, VALUE) (0XFD07026C, 0xFF00FFFFU ,0x08000040U) + */ + PSU_Mask_Write(DDRC_PERFWR1_OFFSET, 0xFF00FFFFU, 0x08000040U); +/*##################################################################### */ + + /* + * Register : DQMAP0 @ 0XFD070280 + + * DQ nibble map for DQ bits [12-15] Present only in designs configured to + * support DDR4. + * PSU_DDRC_DQMAP0_DQ_NIBBLE_MAP_12_15 0x0 + + * DQ nibble map for DQ bits [8-11] Present only in designs configured to s + * upport DDR4. + * PSU_DDRC_DQMAP0_DQ_NIBBLE_MAP_8_11 0x0 + + * DQ nibble map for DQ bits [4-7] Present only in designs configured to su + * pport DDR4. + * PSU_DDRC_DQMAP0_DQ_NIBBLE_MAP_4_7 0x0 + + * DQ nibble map for DQ bits [0-3] Present only in designs configured to su + * pport DDR4. + * PSU_DDRC_DQMAP0_DQ_NIBBLE_MAP_0_3 0x0 + + * DQ Map Register 0 + * (OFFSET, MASK, VALUE) (0XFD070280, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDRC_DQMAP0_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : DQMAP1 @ 0XFD070284 + + * DQ nibble map for DQ bits [28-31] Present only in designs configured to + * support DDR4. + * PSU_DDRC_DQMAP1_DQ_NIBBLE_MAP_28_31 0x0 + + * DQ nibble map for DQ bits [24-27] Present only in designs configured to + * support DDR4. + * PSU_DDRC_DQMAP1_DQ_NIBBLE_MAP_24_27 0x0 + + * DQ nibble map for DQ bits [20-23] Present only in designs configured to + * support DDR4. + * PSU_DDRC_DQMAP1_DQ_NIBBLE_MAP_20_23 0x0 + + * DQ nibble map for DQ bits [16-19] Present only in designs configured to + * support DDR4. + * PSU_DDRC_DQMAP1_DQ_NIBBLE_MAP_16_19 0x0 + + * DQ Map Register 1 + * (OFFSET, MASK, VALUE) (0XFD070284, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDRC_DQMAP1_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : DQMAP2 @ 0XFD070288 + + * DQ nibble map for DQ bits [44-47] Present only in designs configured to + * support DDR4. + * PSU_DDRC_DQMAP2_DQ_NIBBLE_MAP_44_47 0x0 + + * DQ nibble map for DQ bits [40-43] Present only in designs configured to + * support DDR4. + * PSU_DDRC_DQMAP2_DQ_NIBBLE_MAP_40_43 0x0 + + * DQ nibble map for DQ bits [36-39] Present only in designs configured to + * support DDR4. + * PSU_DDRC_DQMAP2_DQ_NIBBLE_MAP_36_39 0x0 + + * DQ nibble map for DQ bits [32-35] Present only in designs configured to + * support DDR4. + * PSU_DDRC_DQMAP2_DQ_NIBBLE_MAP_32_35 0x0 + + * DQ Map Register 2 + * (OFFSET, MASK, VALUE) (0XFD070288, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDRC_DQMAP2_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : DQMAP3 @ 0XFD07028C + + * DQ nibble map for DQ bits [60-63] Present only in designs configured to + * support DDR4. + * PSU_DDRC_DQMAP3_DQ_NIBBLE_MAP_60_63 0x0 + + * DQ nibble map for DQ bits [56-59] Present only in designs configured to + * support DDR4. + * PSU_DDRC_DQMAP3_DQ_NIBBLE_MAP_56_59 0x0 + + * DQ nibble map for DQ bits [52-55] Present only in designs configured to + * support DDR4. + * PSU_DDRC_DQMAP3_DQ_NIBBLE_MAP_52_55 0x0 + + * DQ nibble map for DQ bits [48-51] Present only in designs configured to + * support DDR4. + * PSU_DDRC_DQMAP3_DQ_NIBBLE_MAP_48_51 0x0 + + * DQ Map Register 3 + * (OFFSET, MASK, VALUE) (0XFD07028C, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDRC_DQMAP3_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : DQMAP4 @ 0XFD070290 + + * DQ nibble map for DIMM ECC check bits [4-7] Present only in designs conf + * igured to support DDR4. + * PSU_DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_4_7 0x0 + + * DQ nibble map for DIMM ECC check bits [0-3] Present only in designs conf + * igured to support DDR4. + * PSU_DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_0_3 0x0 + + * DQ Map Register 4 + * (OFFSET, MASK, VALUE) (0XFD070290, 0x0000FFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDRC_DQMAP4_OFFSET, 0x0000FFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : DQMAP5 @ 0XFD070294 + + * All even ranks have the same DQ mapping controled by DQMAP0-4 register a + * s rank 0. This register provides DQ swap function for all odd ranks to s + * upport CRC feature. rank based DQ swapping is: swap bit 0 with 1, swap b + * it 2 with 3, swap bit 4 with 5 and swap bit 6 with 7. 1: Disable rank ba + * sed DQ swapping 0: Enable rank based DQ swapping Present only in designs + * configured to support DDR4. + * PSU_DDRC_DQMAP5_DIS_DQ_RANK_SWAP 0x1 + + * DQ Map Register 5 + * (OFFSET, MASK, VALUE) (0XFD070294, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(DDRC_DQMAP5_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : DBG0 @ 0XFD070300 + + * When this is set to '0', auto-precharge is disabled for the flushed comm + * and in a collision case. Collision cases are write followed by read to s + * ame address, read followed by write to same address, or write followed b + * y write to same address with DBG0.dis_wc bit = 1 (where same address com + * parisons exclude the two address bits representing critical word). FOR D + * EBUG ONLY. + * PSU_DDRC_DBG0_DIS_COLLISION_PAGE_OPT 0x0 + + * When 1, disable write combine. FOR DEBUG ONLY + * PSU_DDRC_DBG0_DIS_WC 0x0 + + * Debug Register 0 + * (OFFSET, MASK, VALUE) (0XFD070300, 0x00000011U ,0x00000000U) + */ + PSU_Mask_Write(DDRC_DBG0_OFFSET, 0x00000011U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : DBGCMD @ 0XFD07030C + + * Setting this register bit to 1 allows refresh and ZQCS commands to be tr + * iggered from hardware via the IOs ext_*. If set to 1, the fields DBGCMD. + * zq_calib_short and DBGCMD.rank*_refresh have no function, and are ignore + * d by the uMCTL2 logic. Setting this register bit to 0 allows refresh and + * ZQCS to be triggered from software, via the fields DBGCMD.zq_calib_shor + * t and DBGCMD.rank*_refresh. If set to 0, the hardware pins ext_* have no + * function, and are ignored by the uMCTL2 logic. This register is static, + * and may only be changed when the DDRC reset signal, core_ddrc_rstn, is + * asserted (0). + * PSU_DDRC_DBGCMD_HW_REF_ZQ_EN 0x0 + + * Setting this register bit to 1 indicates to the uMCTL2 to issue a dfi_ct + * rlupd_req to the PHY. When this request is stored in the uMCTL2, the bit + * is automatically cleared. This operation must only be performed when DF + * IUPD0.dis_auto_ctrlupd=1. + * PSU_DDRC_DBGCMD_CTRLUPD 0x0 + + * Setting this register bit to 1 indicates to the uMCTL2 to issue a ZQCS ( + * ZQ calibration short)/MPC(ZQ calibration) command to the SDRAM. When thi + * s request is stored in the uMCTL2, the bit is automatically cleared. Thi + * s operation can be performed only when ZQCTL0.dis_auto_zq=1. It is recom + * mended NOT to set this register bit if in Init operating mode. This regi + * ster bit is ignored when in Self-Refresh(except LPDDR4) and SR-Powerdown + * (LPDDR4) and Deep power-down operating modes and Maximum Power Saving Mo + * de. + * PSU_DDRC_DBGCMD_ZQ_CALIB_SHORT 0x0 + + * Setting this register bit to 1 indicates to the uMCTL2 to issue a refres + * h to rank 1. Writing to this bit causes DBGSTAT.rank1_refresh_busy to be + * set. When DBGSTAT.rank1_refresh_busy is cleared, the command has been s + * tored in uMCTL2. This operation can be performed only when RFSHCTL3.dis_ + * auto_refresh=1. It is recommended NOT to set this register bit if in Ini + * t or Deep power-down operating modes or Maximum Power Saving Mode. + * PSU_DDRC_DBGCMD_RANK1_REFRESH 0x0 + + * Setting this register bit to 1 indicates to the uMCTL2 to issue a refres + * h to rank 0. Writing to this bit causes DBGSTAT.rank0_refresh_busy to be + * set. When DBGSTAT.rank0_refresh_busy is cleared, the command has been s + * tored in uMCTL2. This operation can be performed only when RFSHCTL3.dis_ + * auto_refresh=1. It is recommended NOT to set this register bit if in Ini + * t or Deep power-down operating modes or Maximum Power Saving Mode. + * PSU_DDRC_DBGCMD_RANK0_REFRESH 0x0 + + * Command Debug Register + * (OFFSET, MASK, VALUE) (0XFD07030C, 0x80000033U ,0x00000000U) + */ + PSU_Mask_Write(DDRC_DBGCMD_OFFSET, 0x80000033U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : SWCTL @ 0XFD070320 + + * Enable quasi-dynamic register programming outside reset. Program registe + * r to 0 to enable quasi-dynamic programming. Set back register to 1 once + * programming is done. + * PSU_DDRC_SWCTL_SW_DONE 0x0 + + * Software register programming control enable + * (OFFSET, MASK, VALUE) (0XFD070320, 0x00000001U ,0x00000000U) + */ + PSU_Mask_Write(DDRC_SWCTL_OFFSET, 0x00000001U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : PCCFG @ 0XFD070400 + + * Burst length expansion mode. By default (i.e. bl_exp_mode==0) XPI expand + * s every AXI burst into multiple HIF commands, using the memory burst len + * gth as a unit. If set to 1, then XPI will use half of the memory burst l + * ength as a unit. This applies to both reads and writes. When MSTR.data_b + * us_width==00, setting bl_exp_mode to 1 has no effect. This can be used i + * n cases where Partial Writes is enabled (UMCTL2_PARTIAL_WR=1) and DBG0.d + * is_wc=1, in order to avoid or minimize t_ccd_l penalty in DDR4 and t_ccd + * _mw penalty in LPDDR4. Note that if DBICTL.reg_ddrc_dm_en=0, functionali + * ty is not supported in the following cases: - UMCTL2_PARTIAL_WR=0 - UMCT + * L2_PARTIAL_WR=1, MSTR.reg_ddrc_data_bus_width=01, MEMC_BURST_LENGTH=8 an + * d MSTR.reg_ddrc_burst_rdwr=1000 (LPDDR4 only) - UMCTL2_PARTIAL_WR=1, MST + * R.reg_ddrc_data_bus_width=01, MEMC_BURST_LENGTH=4 and MSTR.reg_ddrc_burs + * t_rdwr=0100 (DDR4 only), with either MSTR.reg_ddrc_burstchop=0 or CRCPAR + * CTL1.reg_ddrc_crc_enable=1 Functionality is also not supported if Shared + * -AC is enabled + * PSU_DDRC_PCCFG_BL_EXP_MODE 0x0 + + * Page match four limit. If set to 1, limits the number of consecutive sam + * e page DDRC transactions that can be granted by the Port Arbiter to four + * when Page Match feature is enabled. If set to 0, there is no limit impo + * sed on number of consecutive same page DDRC transactions. + * PSU_DDRC_PCCFG_PAGEMATCH_LIMIT 0x0 + + * If set to 1 (enabled), sets co_gs_go2critical_wr and co_gs_go2critical_l + * pr/co_gs_go2critical_hpr signals going to DDRC based on urgent input (aw + * urgent, arurgent) coming from AXI master. If set to 0 (disabled), co_gs_ + * go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals a + * t DDRC are driven to 1b'0. + * PSU_DDRC_PCCFG_GO2CRITICAL_EN 0x1 + + * Port Common Configuration Register + * (OFFSET, MASK, VALUE) (0XFD070400, 0x00000111U ,0x00000001U) + */ + PSU_Mask_Write(DDRC_PCCFG_OFFSET, 0x00000111U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : PCFGR_0 @ 0XFD070404 + + * If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. + * PSU_DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN 0x0 + + * If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + * bled and arurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + * urgent signal can be asserted anytime and as long as required which is i + * ndependent of address handshaking (it is not associated with any particu + * lar command). + * PSU_DDRC_PCFGR_0_RD_PORT_URGENT_EN 0x1 + + * If set to 1, enables aging function for the read channel of the port. + * PSU_DDRC_PCFGR_0_RD_PORT_AGING_EN 0x0 + + * Determines the initial load value of read aging counters. These counters + * will be parallel loaded after reset, or after each grant to the corresp + * onding port. The aging counters down-count every clock cycle where the p + * ort is requesting but not granted. The higher significant 5-bits of the + * read aging counter sets the priority of the read channel of a given port + * . Port's priority will increase as the higher significant 5-bits of the + * counter starts to decrease. When the aging counter becomes 0, the corres + * ponding port channel will have the highest priority level (timeout condi + * tion - Priority0). For multi-port configurations, the aging counters can + * not be used to set port priorities when external dynamic priority inputs + * (arqos) are enabled (timeout is still applicable). For single port conf + * igurations, the aging counters are only used when they timeout (become 0 + * ) to force read-write direction switching. In this case, external dynami + * c priority input, arqos (for reads only) can still be used to set the DD + * RC read priority (2 priority levels: low priority read - LPR, high prior + * ity read - HPR) on a command by command basis. Note: The two LSBs of thi + * s register field are tied internally to 2'b00. + * PSU_DDRC_PCFGR_0_RD_PORT_PRIORITY 0xf + + * Port n Configuration Read Register + * (OFFSET, MASK, VALUE) (0XFD070404, 0x000073FFU ,0x0000200FU) + */ + PSU_Mask_Write(DDRC_PCFGR_0_OFFSET, 0x000073FFU, 0x0000200FU); +/*##################################################################### */ + + /* + * Register : PCFGW_0 @ 0XFD070408 + + * If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. + * PSU_DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN 0x0 + + * If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + * bled and awurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + * serted anytime and as long as required which is independent of address h + * andshaking (it is not associated with any particular command). + * PSU_DDRC_PCFGW_0_WR_PORT_URGENT_EN 0x1 + + * If set to 1, enables aging function for the write channel of the port. + * PSU_DDRC_PCFGW_0_WR_PORT_AGING_EN 0x0 + + * Determines the initial load value of write aging counters. These counter + * s will be parallel loaded after reset, or after each grant to the corres + * ponding port. The aging counters down-count every clock cycle where the + * port is requesting but not granted. The higher significant 5-bits of the + * write aging counter sets the initial priority of the write channel of a + * given port. Port's priority will increase as the higher significant 5-b + * its of the counter starts to decrease. When the aging counter becomes 0, + * the corresponding port channel will have the highest priority level. Fo + * r multi-port configurations, the aging counters cannot be used to set po + * rt priorities when external dynamic priority inputs (awqos) are enabled + * (timeout is still applicable). For single port configurations, the aging + * counters are only used when they timeout (become 0) to force read-write + * direction switching. Note: The two LSBs of this register field are tied + * internally to 2'b00. + * PSU_DDRC_PCFGW_0_WR_PORT_PRIORITY 0xf + + * Port n Configuration Write Register + * (OFFSET, MASK, VALUE) (0XFD070408, 0x000073FFU ,0x0000200FU) + */ + PSU_Mask_Write(DDRC_PCFGW_0_OFFSET, 0x000073FFU, 0x0000200FU); +/*##################################################################### */ + + /* + * Register : PCTRL_0 @ 0XFD070490 + + * Enables port n. + * PSU_DDRC_PCTRL_0_PORT_EN 0x1 + + * Port n Control Register + * (OFFSET, MASK, VALUE) (0XFD070490, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(DDRC_PCTRL_0_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : PCFGQOS0_0 @ 0XFD070494 + + * This bitfield indicates the traffic class of region 1. Valid values are: + * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + * maps to the blue address queue. In this case, valid values are 0: LPR a + * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. + * PSU_DDRC_PCFGQOS0_0_RQOS_MAP_REGION1 0x2 + + * This bitfield indicates the traffic class of region 0. Valid values are: + * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + * maps to the blue address queue. In this case, valid values are: 0: LPR + * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. + * PSU_DDRC_PCFGQOS0_0_RQOS_MAP_REGION0 0x0 + + * Separation level1 indicating the end of region0 mapping; start of region + * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + * lues are used directly as port priorities, where the higher the value co + * rresponds to higher port priority. All of the map_level* registers must + * be set to distinct values. + * PSU_DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1 0xb + + * Port n Read QoS Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD070494, 0x0033000FU ,0x0020000BU) + */ + PSU_Mask_Write(DDRC_PCFGQOS0_0_OFFSET, 0x0033000FU, 0x0020000BU); +/*##################################################################### */ + + /* + * Register : PCFGQOS1_0 @ 0XFD070498 + + * Specifies the timeout value for transactions mapped to the red address q + * ueue. + * PSU_DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR 0x0 + + * Specifies the timeout value for transactions mapped to the blue address + * queue. + * PSU_DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB 0x0 + + * Port n Read QoS Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD070498, 0x07FF07FFU ,0x00000000U) + */ + PSU_Mask_Write(DDRC_PCFGQOS1_0_OFFSET, 0x07FF07FFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : PCFGR_1 @ 0XFD0704B4 + + * If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. + * PSU_DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN 0x0 + + * If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + * bled and arurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + * urgent signal can be asserted anytime and as long as required which is i + * ndependent of address handshaking (it is not associated with any particu + * lar command). + * PSU_DDRC_PCFGR_1_RD_PORT_URGENT_EN 0x1 + + * If set to 1, enables aging function for the read channel of the port. + * PSU_DDRC_PCFGR_1_RD_PORT_AGING_EN 0x0 + + * Determines the initial load value of read aging counters. These counters + * will be parallel loaded after reset, or after each grant to the corresp + * onding port. The aging counters down-count every clock cycle where the p + * ort is requesting but not granted. The higher significant 5-bits of the + * read aging counter sets the priority of the read channel of a given port + * . Port's priority will increase as the higher significant 5-bits of the + * counter starts to decrease. When the aging counter becomes 0, the corres + * ponding port channel will have the highest priority level (timeout condi + * tion - Priority0). For multi-port configurations, the aging counters can + * not be used to set port priorities when external dynamic priority inputs + * (arqos) are enabled (timeout is still applicable). For single port conf + * igurations, the aging counters are only used when they timeout (become 0 + * ) to force read-write direction switching. In this case, external dynami + * c priority input, arqos (for reads only) can still be used to set the DD + * RC read priority (2 priority levels: low priority read - LPR, high prior + * ity read - HPR) on a command by command basis. Note: The two LSBs of thi + * s register field are tied internally to 2'b00. + * PSU_DDRC_PCFGR_1_RD_PORT_PRIORITY 0xf + + * Port n Configuration Read Register + * (OFFSET, MASK, VALUE) (0XFD0704B4, 0x000073FFU ,0x0000200FU) + */ + PSU_Mask_Write(DDRC_PCFGR_1_OFFSET, 0x000073FFU, 0x0000200FU); +/*##################################################################### */ + + /* + * Register : PCFGW_1 @ 0XFD0704B8 + + * If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. + * PSU_DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN 0x0 + + * If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + * bled and awurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + * serted anytime and as long as required which is independent of address h + * andshaking (it is not associated with any particular command). + * PSU_DDRC_PCFGW_1_WR_PORT_URGENT_EN 0x1 + + * If set to 1, enables aging function for the write channel of the port. + * PSU_DDRC_PCFGW_1_WR_PORT_AGING_EN 0x0 + + * Determines the initial load value of write aging counters. These counter + * s will be parallel loaded after reset, or after each grant to the corres + * ponding port. The aging counters down-count every clock cycle where the + * port is requesting but not granted. The higher significant 5-bits of the + * write aging counter sets the initial priority of the write channel of a + * given port. Port's priority will increase as the higher significant 5-b + * its of the counter starts to decrease. When the aging counter becomes 0, + * the corresponding port channel will have the highest priority level. Fo + * r multi-port configurations, the aging counters cannot be used to set po + * rt priorities when external dynamic priority inputs (awqos) are enabled + * (timeout is still applicable). For single port configurations, the aging + * counters are only used when they timeout (become 0) to force read-write + * direction switching. Note: The two LSBs of this register field are tied + * internally to 2'b00. + * PSU_DDRC_PCFGW_1_WR_PORT_PRIORITY 0xf + + * Port n Configuration Write Register + * (OFFSET, MASK, VALUE) (0XFD0704B8, 0x000073FFU ,0x0000200FU) + */ + PSU_Mask_Write(DDRC_PCFGW_1_OFFSET, 0x000073FFU, 0x0000200FU); +/*##################################################################### */ + + /* + * Register : PCTRL_1 @ 0XFD070540 + + * Enables port n. + * PSU_DDRC_PCTRL_1_PORT_EN 0x1 + + * Port n Control Register + * (OFFSET, MASK, VALUE) (0XFD070540, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(DDRC_PCTRL_1_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : PCFGQOS0_1 @ 0XFD070544 + + * This bitfield indicates the traffic class of region2. For dual address q + * ueue configurations, region2 maps to the red address queue. Valid values + * are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN + * = 0) and traffic class of region2 is set to 1 (VPR), VPR traffic is ali + * ased to LPR traffic. + * PSU_DDRC_PCFGQOS0_1_RQOS_MAP_REGION2 0x2 + + * This bitfield indicates the traffic class of region 1. Valid values are: + * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + * maps to the blue address queue. In this case, valid values are 0: LPR a + * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. + * PSU_DDRC_PCFGQOS0_1_RQOS_MAP_REGION1 0x0 + + * This bitfield indicates the traffic class of region 0. Valid values are: + * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + * maps to the blue address queue. In this case, valid values are: 0: LPR + * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. + * PSU_DDRC_PCFGQOS0_1_RQOS_MAP_REGION0 0x0 + + * Separation level2 indicating the end of region1 mapping; start of region + * 1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 whi + * ch corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note + * that for PA, arqos values are used directly as port priorities, where t + * he higher the value corresponds to higher port priority. All of the map_ + * level* registers must be set to distinct values. + * PSU_DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2 0xb + + * Separation level1 indicating the end of region0 mapping; start of region + * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + * lues are used directly as port priorities, where the higher the value co + * rresponds to higher port priority. All of the map_level* registers must + * be set to distinct values. + * PSU_DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1 0x3 + + * Port n Read QoS Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD070544, 0x03330F0FU ,0x02000B03U) + */ + PSU_Mask_Write(DDRC_PCFGQOS0_1_OFFSET, 0x03330F0FU, 0x02000B03U); +/*##################################################################### */ + + /* + * Register : PCFGQOS1_1 @ 0XFD070548 + + * Specifies the timeout value for transactions mapped to the red address q + * ueue. + * PSU_DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR 0x0 + + * Specifies the timeout value for transactions mapped to the blue address + * queue. + * PSU_DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB 0x0 + + * Port n Read QoS Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD070548, 0x07FF07FFU ,0x00000000U) + */ + PSU_Mask_Write(DDRC_PCFGQOS1_1_OFFSET, 0x07FF07FFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : PCFGR_2 @ 0XFD070564 + + * If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. + * PSU_DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN 0x0 + + * If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + * bled and arurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + * urgent signal can be asserted anytime and as long as required which is i + * ndependent of address handshaking (it is not associated with any particu + * lar command). + * PSU_DDRC_PCFGR_2_RD_PORT_URGENT_EN 0x1 + + * If set to 1, enables aging function for the read channel of the port. + * PSU_DDRC_PCFGR_2_RD_PORT_AGING_EN 0x0 + + * Determines the initial load value of read aging counters. These counters + * will be parallel loaded after reset, or after each grant to the corresp + * onding port. The aging counters down-count every clock cycle where the p + * ort is requesting but not granted. The higher significant 5-bits of the + * read aging counter sets the priority of the read channel of a given port + * . Port's priority will increase as the higher significant 5-bits of the + * counter starts to decrease. When the aging counter becomes 0, the corres + * ponding port channel will have the highest priority level (timeout condi + * tion - Priority0). For multi-port configurations, the aging counters can + * not be used to set port priorities when external dynamic priority inputs + * (arqos) are enabled (timeout is still applicable). For single port conf + * igurations, the aging counters are only used when they timeout (become 0 + * ) to force read-write direction switching. In this case, external dynami + * c priority input, arqos (for reads only) can still be used to set the DD + * RC read priority (2 priority levels: low priority read - LPR, high prior + * ity read - HPR) on a command by command basis. Note: The two LSBs of thi + * s register field are tied internally to 2'b00. + * PSU_DDRC_PCFGR_2_RD_PORT_PRIORITY 0xf + + * Port n Configuration Read Register + * (OFFSET, MASK, VALUE) (0XFD070564, 0x000073FFU ,0x0000200FU) + */ + PSU_Mask_Write(DDRC_PCFGR_2_OFFSET, 0x000073FFU, 0x0000200FU); +/*##################################################################### */ + + /* + * Register : PCFGW_2 @ 0XFD070568 + + * If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. + * PSU_DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN 0x0 + + * If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + * bled and awurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + * serted anytime and as long as required which is independent of address h + * andshaking (it is not associated with any particular command). + * PSU_DDRC_PCFGW_2_WR_PORT_URGENT_EN 0x1 + + * If set to 1, enables aging function for the write channel of the port. + * PSU_DDRC_PCFGW_2_WR_PORT_AGING_EN 0x0 + + * Determines the initial load value of write aging counters. These counter + * s will be parallel loaded after reset, or after each grant to the corres + * ponding port. The aging counters down-count every clock cycle where the + * port is requesting but not granted. The higher significant 5-bits of the + * write aging counter sets the initial priority of the write channel of a + * given port. Port's priority will increase as the higher significant 5-b + * its of the counter starts to decrease. When the aging counter becomes 0, + * the corresponding port channel will have the highest priority level. Fo + * r multi-port configurations, the aging counters cannot be used to set po + * rt priorities when external dynamic priority inputs (awqos) are enabled + * (timeout is still applicable). For single port configurations, the aging + * counters are only used when they timeout (become 0) to force read-write + * direction switching. Note: The two LSBs of this register field are tied + * internally to 2'b00. + * PSU_DDRC_PCFGW_2_WR_PORT_PRIORITY 0xf + + * Port n Configuration Write Register + * (OFFSET, MASK, VALUE) (0XFD070568, 0x000073FFU ,0x0000200FU) + */ + PSU_Mask_Write(DDRC_PCFGW_2_OFFSET, 0x000073FFU, 0x0000200FU); +/*##################################################################### */ + + /* + * Register : PCTRL_2 @ 0XFD0705F0 + + * Enables port n. + * PSU_DDRC_PCTRL_2_PORT_EN 0x1 + + * Port n Control Register + * (OFFSET, MASK, VALUE) (0XFD0705F0, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(DDRC_PCTRL_2_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : PCFGQOS0_2 @ 0XFD0705F4 + + * This bitfield indicates the traffic class of region2. For dual address q + * ueue configurations, region2 maps to the red address queue. Valid values + * are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN + * = 0) and traffic class of region2 is set to 1 (VPR), VPR traffic is ali + * ased to LPR traffic. + * PSU_DDRC_PCFGQOS0_2_RQOS_MAP_REGION2 0x2 + + * This bitfield indicates the traffic class of region 1. Valid values are: + * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + * maps to the blue address queue. In this case, valid values are 0: LPR a + * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. + * PSU_DDRC_PCFGQOS0_2_RQOS_MAP_REGION1 0x0 + + * This bitfield indicates the traffic class of region 0. Valid values are: + * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + * maps to the blue address queue. In this case, valid values are: 0: LPR + * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. + * PSU_DDRC_PCFGQOS0_2_RQOS_MAP_REGION0 0x0 + + * Separation level2 indicating the end of region1 mapping; start of region + * 1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 whi + * ch corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note + * that for PA, arqos values are used directly as port priorities, where t + * he higher the value corresponds to higher port priority. All of the map_ + * level* registers must be set to distinct values. + * PSU_DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2 0xb + + * Separation level1 indicating the end of region0 mapping; start of region + * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + * lues are used directly as port priorities, where the higher the value co + * rresponds to higher port priority. All of the map_level* registers must + * be set to distinct values. + * PSU_DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1 0x3 + + * Port n Read QoS Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD0705F4, 0x03330F0FU ,0x02000B03U) + */ + PSU_Mask_Write(DDRC_PCFGQOS0_2_OFFSET, 0x03330F0FU, 0x02000B03U); +/*##################################################################### */ + + /* + * Register : PCFGQOS1_2 @ 0XFD0705F8 + + * Specifies the timeout value for transactions mapped to the red address q + * ueue. + * PSU_DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR 0x0 + + * Specifies the timeout value for transactions mapped to the blue address + * queue. + * PSU_DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB 0x0 + + * Port n Read QoS Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD0705F8, 0x07FF07FFU ,0x00000000U) + */ + PSU_Mask_Write(DDRC_PCFGQOS1_2_OFFSET, 0x07FF07FFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : PCFGR_3 @ 0XFD070614 + + * If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. + * PSU_DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN 0x0 + + * If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + * bled and arurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + * urgent signal can be asserted anytime and as long as required which is i + * ndependent of address handshaking (it is not associated with any particu + * lar command). + * PSU_DDRC_PCFGR_3_RD_PORT_URGENT_EN 0x1 + + * If set to 1, enables aging function for the read channel of the port. + * PSU_DDRC_PCFGR_3_RD_PORT_AGING_EN 0x0 + + * Determines the initial load value of read aging counters. These counters + * will be parallel loaded after reset, or after each grant to the corresp + * onding port. The aging counters down-count every clock cycle where the p + * ort is requesting but not granted. The higher significant 5-bits of the + * read aging counter sets the priority of the read channel of a given port + * . Port's priority will increase as the higher significant 5-bits of the + * counter starts to decrease. When the aging counter becomes 0, the corres + * ponding port channel will have the highest priority level (timeout condi + * tion - Priority0). For multi-port configurations, the aging counters can + * not be used to set port priorities when external dynamic priority inputs + * (arqos) are enabled (timeout is still applicable). For single port conf + * igurations, the aging counters are only used when they timeout (become 0 + * ) to force read-write direction switching. In this case, external dynami + * c priority input, arqos (for reads only) can still be used to set the DD + * RC read priority (2 priority levels: low priority read - LPR, high prior + * ity read - HPR) on a command by command basis. Note: The two LSBs of thi + * s register field are tied internally to 2'b00. + * PSU_DDRC_PCFGR_3_RD_PORT_PRIORITY 0xf + + * Port n Configuration Read Register + * (OFFSET, MASK, VALUE) (0XFD070614, 0x000073FFU ,0x0000200FU) + */ + PSU_Mask_Write(DDRC_PCFGR_3_OFFSET, 0x000073FFU, 0x0000200FU); +/*##################################################################### */ + + /* + * Register : PCFGW_3 @ 0XFD070618 + + * If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. + * PSU_DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN 0x0 + + * If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + * bled and awurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + * serted anytime and as long as required which is independent of address h + * andshaking (it is not associated with any particular command). + * PSU_DDRC_PCFGW_3_WR_PORT_URGENT_EN 0x1 + + * If set to 1, enables aging function for the write channel of the port. + * PSU_DDRC_PCFGW_3_WR_PORT_AGING_EN 0x0 + + * Determines the initial load value of write aging counters. These counter + * s will be parallel loaded after reset, or after each grant to the corres + * ponding port. The aging counters down-count every clock cycle where the + * port is requesting but not granted. The higher significant 5-bits of the + * write aging counter sets the initial priority of the write channel of a + * given port. Port's priority will increase as the higher significant 5-b + * its of the counter starts to decrease. When the aging counter becomes 0, + * the corresponding port channel will have the highest priority level. Fo + * r multi-port configurations, the aging counters cannot be used to set po + * rt priorities when external dynamic priority inputs (awqos) are enabled + * (timeout is still applicable). For single port configurations, the aging + * counters are only used when they timeout (become 0) to force read-write + * direction switching. Note: The two LSBs of this register field are tied + * internally to 2'b00. + * PSU_DDRC_PCFGW_3_WR_PORT_PRIORITY 0xf + + * Port n Configuration Write Register + * (OFFSET, MASK, VALUE) (0XFD070618, 0x000073FFU ,0x0000200FU) + */ + PSU_Mask_Write(DDRC_PCFGW_3_OFFSET, 0x000073FFU, 0x0000200FU); +/*##################################################################### */ + + /* + * Register : PCTRL_3 @ 0XFD0706A0 + + * Enables port n. + * PSU_DDRC_PCTRL_3_PORT_EN 0x1 + + * Port n Control Register + * (OFFSET, MASK, VALUE) (0XFD0706A0, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(DDRC_PCTRL_3_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : PCFGQOS0_3 @ 0XFD0706A4 + + * This bitfield indicates the traffic class of region 1. Valid values are: + * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + * maps to the blue address queue. In this case, valid values are 0: LPR a + * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. + * PSU_DDRC_PCFGQOS0_3_RQOS_MAP_REGION1 0x1 + + * This bitfield indicates the traffic class of region 0. Valid values are: + * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + * maps to the blue address queue. In this case, valid values are: 0: LPR + * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. + * PSU_DDRC_PCFGQOS0_3_RQOS_MAP_REGION0 0x0 + + * Separation level1 indicating the end of region0 mapping; start of region + * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + * lues are used directly as port priorities, where the higher the value co + * rresponds to higher port priority. All of the map_level* registers must + * be set to distinct values. + * PSU_DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1 0x3 + + * Port n Read QoS Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD0706A4, 0x0033000FU ,0x00100003U) + */ + PSU_Mask_Write(DDRC_PCFGQOS0_3_OFFSET, 0x0033000FU, 0x00100003U); +/*##################################################################### */ + + /* + * Register : PCFGQOS1_3 @ 0XFD0706A8 + + * Specifies the timeout value for transactions mapped to the red address q + * ueue. + * PSU_DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR 0x0 + + * Specifies the timeout value for transactions mapped to the blue address + * queue. + * PSU_DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB 0x4f + + * Port n Read QoS Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD0706A8, 0x07FF07FFU ,0x0000004FU) + */ + PSU_Mask_Write(DDRC_PCFGQOS1_3_OFFSET, 0x07FF07FFU, 0x0000004FU); +/*##################################################################### */ + + /* + * Register : PCFGWQOS0_3 @ 0XFD0706AC + + * This bitfield indicates the traffic class of region 1. Valid values are: + * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + * affic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW + * traffic. + * PSU_DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1 0x1 + + * This bitfield indicates the traffic class of region 0. Valid values are: + * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + * affic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW + * traffic. + * PSU_DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0 0x0 + + * Separation level indicating the end of region0 mapping; start of region0 + * is 0. Possible values for level1 are 0 to 14 which corresponds to awqos + * . Note that for PA, awqos values are used directly as port priorities, w + * here the higher the value corresponds to higher port priority. + * PSU_DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL 0x3 + + * Port n Write QoS Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD0706AC, 0x0033000FU ,0x00100003U) + */ + PSU_Mask_Write(DDRC_PCFGWQOS0_3_OFFSET, 0x0033000FU, 0x00100003U); +/*##################################################################### */ + + /* + * Register : PCFGWQOS1_3 @ 0XFD0706B0 + + * Specifies the timeout value for write transactions. + * PSU_DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT 0x4f + + * Port n Write QoS Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD0706B0, 0x000007FFU ,0x0000004FU) + */ + PSU_Mask_Write(DDRC_PCFGWQOS1_3_OFFSET, 0x000007FFU, 0x0000004FU); +/*##################################################################### */ + + /* + * Register : PCFGR_4 @ 0XFD0706C4 + + * If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. + * PSU_DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN 0x0 + + * If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + * bled and arurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + * urgent signal can be asserted anytime and as long as required which is i + * ndependent of address handshaking (it is not associated with any particu + * lar command). + * PSU_DDRC_PCFGR_4_RD_PORT_URGENT_EN 0x1 + + * If set to 1, enables aging function for the read channel of the port. + * PSU_DDRC_PCFGR_4_RD_PORT_AGING_EN 0x0 + + * Determines the initial load value of read aging counters. These counters + * will be parallel loaded after reset, or after each grant to the corresp + * onding port. The aging counters down-count every clock cycle where the p + * ort is requesting but not granted. The higher significant 5-bits of the + * read aging counter sets the priority of the read channel of a given port + * . Port's priority will increase as the higher significant 5-bits of the + * counter starts to decrease. When the aging counter becomes 0, the corres + * ponding port channel will have the highest priority level (timeout condi + * tion - Priority0). For multi-port configurations, the aging counters can + * not be used to set port priorities when external dynamic priority inputs + * (arqos) are enabled (timeout is still applicable). For single port conf + * igurations, the aging counters are only used when they timeout (become 0 + * ) to force read-write direction switching. In this case, external dynami + * c priority input, arqos (for reads only) can still be used to set the DD + * RC read priority (2 priority levels: low priority read - LPR, high prior + * ity read - HPR) on a command by command basis. Note: The two LSBs of thi + * s register field are tied internally to 2'b00. + * PSU_DDRC_PCFGR_4_RD_PORT_PRIORITY 0xf + + * Port n Configuration Read Register + * (OFFSET, MASK, VALUE) (0XFD0706C4, 0x000073FFU ,0x0000200FU) + */ + PSU_Mask_Write(DDRC_PCFGR_4_OFFSET, 0x000073FFU, 0x0000200FU); +/*##################################################################### */ + + /* + * Register : PCFGW_4 @ 0XFD0706C8 + + * If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. + * PSU_DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN 0x0 + + * If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + * bled and awurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + * serted anytime and as long as required which is independent of address h + * andshaking (it is not associated with any particular command). + * PSU_DDRC_PCFGW_4_WR_PORT_URGENT_EN 0x1 + + * If set to 1, enables aging function for the write channel of the port. + * PSU_DDRC_PCFGW_4_WR_PORT_AGING_EN 0x0 + + * Determines the initial load value of write aging counters. These counter + * s will be parallel loaded after reset, or after each grant to the corres + * ponding port. The aging counters down-count every clock cycle where the + * port is requesting but not granted. The higher significant 5-bits of the + * write aging counter sets the initial priority of the write channel of a + * given port. Port's priority will increase as the higher significant 5-b + * its of the counter starts to decrease. When the aging counter becomes 0, + * the corresponding port channel will have the highest priority level. Fo + * r multi-port configurations, the aging counters cannot be used to set po + * rt priorities when external dynamic priority inputs (awqos) are enabled + * (timeout is still applicable). For single port configurations, the aging + * counters are only used when they timeout (become 0) to force read-write + * direction switching. Note: The two LSBs of this register field are tied + * internally to 2'b00. + * PSU_DDRC_PCFGW_4_WR_PORT_PRIORITY 0xf + + * Port n Configuration Write Register + * (OFFSET, MASK, VALUE) (0XFD0706C8, 0x000073FFU ,0x0000200FU) + */ + PSU_Mask_Write(DDRC_PCFGW_4_OFFSET, 0x000073FFU, 0x0000200FU); +/*##################################################################### */ + + /* + * Register : PCTRL_4 @ 0XFD070750 + + * Enables port n. + * PSU_DDRC_PCTRL_4_PORT_EN 0x1 + + * Port n Control Register + * (OFFSET, MASK, VALUE) (0XFD070750, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(DDRC_PCTRL_4_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : PCFGQOS0_4 @ 0XFD070754 + + * This bitfield indicates the traffic class of region 1. Valid values are: + * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + * maps to the blue address queue. In this case, valid values are 0: LPR a + * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. + * PSU_DDRC_PCFGQOS0_4_RQOS_MAP_REGION1 0x1 + + * This bitfield indicates the traffic class of region 0. Valid values are: + * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + * maps to the blue address queue. In this case, valid values are: 0: LPR + * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. + * PSU_DDRC_PCFGQOS0_4_RQOS_MAP_REGION0 0x0 + + * Separation level1 indicating the end of region0 mapping; start of region + * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + * lues are used directly as port priorities, where the higher the value co + * rresponds to higher port priority. All of the map_level* registers must + * be set to distinct values. + * PSU_DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1 0x3 + + * Port n Read QoS Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD070754, 0x0033000FU ,0x00100003U) + */ + PSU_Mask_Write(DDRC_PCFGQOS0_4_OFFSET, 0x0033000FU, 0x00100003U); +/*##################################################################### */ + + /* + * Register : PCFGQOS1_4 @ 0XFD070758 + + * Specifies the timeout value for transactions mapped to the red address q + * ueue. + * PSU_DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR 0x0 + + * Specifies the timeout value for transactions mapped to the blue address + * queue. + * PSU_DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB 0x4f + + * Port n Read QoS Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD070758, 0x07FF07FFU ,0x0000004FU) + */ + PSU_Mask_Write(DDRC_PCFGQOS1_4_OFFSET, 0x07FF07FFU, 0x0000004FU); +/*##################################################################### */ + + /* + * Register : PCFGWQOS0_4 @ 0XFD07075C + + * This bitfield indicates the traffic class of region 1. Valid values are: + * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + * affic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW + * traffic. + * PSU_DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1 0x1 + + * This bitfield indicates the traffic class of region 0. Valid values are: + * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + * affic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW + * traffic. + * PSU_DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0 0x0 + + * Separation level indicating the end of region0 mapping; start of region0 + * is 0. Possible values for level1 are 0 to 14 which corresponds to awqos + * . Note that for PA, awqos values are used directly as port priorities, w + * here the higher the value corresponds to higher port priority. + * PSU_DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL 0x3 + + * Port n Write QoS Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD07075C, 0x0033000FU ,0x00100003U) + */ + PSU_Mask_Write(DDRC_PCFGWQOS0_4_OFFSET, 0x0033000FU, 0x00100003U); +/*##################################################################### */ + + /* + * Register : PCFGWQOS1_4 @ 0XFD070760 + + * Specifies the timeout value for write transactions. + * PSU_DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT 0x4f + + * Port n Write QoS Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD070760, 0x000007FFU ,0x0000004FU) + */ + PSU_Mask_Write(DDRC_PCFGWQOS1_4_OFFSET, 0x000007FFU, 0x0000004FU); +/*##################################################################### */ + + /* + * Register : PCFGR_5 @ 0XFD070774 + + * If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. + * PSU_DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN 0x0 + + * If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + * bled and arurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + * urgent signal can be asserted anytime and as long as required which is i + * ndependent of address handshaking (it is not associated with any particu + * lar command). + * PSU_DDRC_PCFGR_5_RD_PORT_URGENT_EN 0x1 + + * If set to 1, enables aging function for the read channel of the port. + * PSU_DDRC_PCFGR_5_RD_PORT_AGING_EN 0x0 + + * Determines the initial load value of read aging counters. These counters + * will be parallel loaded after reset, or after each grant to the corresp + * onding port. The aging counters down-count every clock cycle where the p + * ort is requesting but not granted. The higher significant 5-bits of the + * read aging counter sets the priority of the read channel of a given port + * . Port's priority will increase as the higher significant 5-bits of the + * counter starts to decrease. When the aging counter becomes 0, the corres + * ponding port channel will have the highest priority level (timeout condi + * tion - Priority0). For multi-port configurations, the aging counters can + * not be used to set port priorities when external dynamic priority inputs + * (arqos) are enabled (timeout is still applicable). For single port conf + * igurations, the aging counters are only used when they timeout (become 0 + * ) to force read-write direction switching. In this case, external dynami + * c priority input, arqos (for reads only) can still be used to set the DD + * RC read priority (2 priority levels: low priority read - LPR, high prior + * ity read - HPR) on a command by command basis. Note: The two LSBs of thi + * s register field are tied internally to 2'b00. + * PSU_DDRC_PCFGR_5_RD_PORT_PRIORITY 0xf + + * Port n Configuration Read Register + * (OFFSET, MASK, VALUE) (0XFD070774, 0x000073FFU ,0x0000200FU) + */ + PSU_Mask_Write(DDRC_PCFGR_5_OFFSET, 0x000073FFU, 0x0000200FU); +/*##################################################################### */ + + /* + * Register : PCFGW_5 @ 0XFD070778 + + * If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. + * PSU_DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN 0x0 + + * If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + * bled and awurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + * serted anytime and as long as required which is independent of address h + * andshaking (it is not associated with any particular command). + * PSU_DDRC_PCFGW_5_WR_PORT_URGENT_EN 0x1 + + * If set to 1, enables aging function for the write channel of the port. + * PSU_DDRC_PCFGW_5_WR_PORT_AGING_EN 0x0 + + * Determines the initial load value of write aging counters. These counter + * s will be parallel loaded after reset, or after each grant to the corres + * ponding port. The aging counters down-count every clock cycle where the + * port is requesting but not granted. The higher significant 5-bits of the + * write aging counter sets the initial priority of the write channel of a + * given port. Port's priority will increase as the higher significant 5-b + * its of the counter starts to decrease. When the aging counter becomes 0, + * the corresponding port channel will have the highest priority level. Fo + * r multi-port configurations, the aging counters cannot be used to set po + * rt priorities when external dynamic priority inputs (awqos) are enabled + * (timeout is still applicable). For single port configurations, the aging + * counters are only used when they timeout (become 0) to force read-write + * direction switching. Note: The two LSBs of this register field are tied + * internally to 2'b00. + * PSU_DDRC_PCFGW_5_WR_PORT_PRIORITY 0xf + + * Port n Configuration Write Register + * (OFFSET, MASK, VALUE) (0XFD070778, 0x000073FFU ,0x0000200FU) + */ + PSU_Mask_Write(DDRC_PCFGW_5_OFFSET, 0x000073FFU, 0x0000200FU); +/*##################################################################### */ + + /* + * Register : PCTRL_5 @ 0XFD070800 + + * Enables port n. + * PSU_DDRC_PCTRL_5_PORT_EN 0x1 + + * Port n Control Register + * (OFFSET, MASK, VALUE) (0XFD070800, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(DDRC_PCTRL_5_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : PCFGQOS0_5 @ 0XFD070804 + + * This bitfield indicates the traffic class of region 1. Valid values are: + * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + * maps to the blue address queue. In this case, valid values are 0: LPR a + * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. + * PSU_DDRC_PCFGQOS0_5_RQOS_MAP_REGION1 0x1 + + * This bitfield indicates the traffic class of region 0. Valid values are: + * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + * maps to the blue address queue. In this case, valid values are: 0: LPR + * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. + * PSU_DDRC_PCFGQOS0_5_RQOS_MAP_REGION0 0x0 + + * Separation level1 indicating the end of region0 mapping; start of region + * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + * lues are used directly as port priorities, where the higher the value co + * rresponds to higher port priority. All of the map_level* registers must + * be set to distinct values. + * PSU_DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1 0x3 + + * Port n Read QoS Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD070804, 0x0033000FU ,0x00100003U) + */ + PSU_Mask_Write(DDRC_PCFGQOS0_5_OFFSET, 0x0033000FU, 0x00100003U); +/*##################################################################### */ + + /* + * Register : PCFGQOS1_5 @ 0XFD070808 + + * Specifies the timeout value for transactions mapped to the red address q + * ueue. + * PSU_DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR 0x0 + + * Specifies the timeout value for transactions mapped to the blue address + * queue. + * PSU_DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB 0x4f + + * Port n Read QoS Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD070808, 0x07FF07FFU ,0x0000004FU) + */ + PSU_Mask_Write(DDRC_PCFGQOS1_5_OFFSET, 0x07FF07FFU, 0x0000004FU); +/*##################################################################### */ + + /* + * Register : PCFGWQOS0_5 @ 0XFD07080C + + * This bitfield indicates the traffic class of region 1. Valid values are: + * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + * affic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW + * traffic. + * PSU_DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1 0x1 + + * This bitfield indicates the traffic class of region 0. Valid values are: + * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + * affic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW + * traffic. + * PSU_DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0 0x0 + + * Separation level indicating the end of region0 mapping; start of region0 + * is 0. Possible values for level1 are 0 to 14 which corresponds to awqos + * . Note that for PA, awqos values are used directly as port priorities, w + * here the higher the value corresponds to higher port priority. + * PSU_DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL 0x3 + + * Port n Write QoS Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD07080C, 0x0033000FU ,0x00100003U) + */ + PSU_Mask_Write(DDRC_PCFGWQOS0_5_OFFSET, 0x0033000FU, 0x00100003U); +/*##################################################################### */ + + /* + * Register : PCFGWQOS1_5 @ 0XFD070810 + + * Specifies the timeout value for write transactions. + * PSU_DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT 0x4f + + * Port n Write QoS Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD070810, 0x000007FFU ,0x0000004FU) + */ + PSU_Mask_Write(DDRC_PCFGWQOS1_5_OFFSET, 0x000007FFU, 0x0000004FU); +/*##################################################################### */ + + /* + * Register : SARBASE0 @ 0XFD070F04 + + * Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x + * ] and araddr[UMCTL2_A_ADDRW-1:x] where x is determined by the minimum bl + * ock size parameter UMCTL2_SARMINSIZE: (x=log2(block size)). + * PSU_DDRC_SARBASE0_BASE_ADDR 0x0 + + * SAR Base Address Register n + * (OFFSET, MASK, VALUE) (0XFD070F04, 0x000001FFU ,0x00000000U) + */ + PSU_Mask_Write(DDRC_SARBASE0_OFFSET, 0x000001FFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : SARSIZE0 @ 0XFD070F08 + + * Number of blocks for address region n. This register determines the tota + * l size of the region in multiples of minimum block size as specified by + * the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded + * as number of blocks = nblocks + 1. For example, if register is programme + * d to 0, region will have 1 block. + * PSU_DDRC_SARSIZE0_NBLOCKS 0x0 + + * SAR Size Register n + * (OFFSET, MASK, VALUE) (0XFD070F08, 0x000000FFU ,0x00000000U) + */ + PSU_Mask_Write(DDRC_SARSIZE0_OFFSET, 0x000000FFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : SARBASE1 @ 0XFD070F0C + + * Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x + * ] and araddr[UMCTL2_A_ADDRW-1:x] where x is determined by the minimum bl + * ock size parameter UMCTL2_SARMINSIZE: (x=log2(block size)). + * PSU_DDRC_SARBASE1_BASE_ADDR 0x10 + + * SAR Base Address Register n + * (OFFSET, MASK, VALUE) (0XFD070F0C, 0x000001FFU ,0x00000010U) + */ + PSU_Mask_Write(DDRC_SARBASE1_OFFSET, 0x000001FFU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : SARSIZE1 @ 0XFD070F10 + + * Number of blocks for address region n. This register determines the tota + * l size of the region in multiples of minimum block size as specified by + * the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded + * as number of blocks = nblocks + 1. For example, if register is programme + * d to 0, region will have 1 block. + * PSU_DDRC_SARSIZE1_NBLOCKS 0xf + + * SAR Size Register n + * (OFFSET, MASK, VALUE) (0XFD070F10, 0x000000FFU ,0x0000000FU) + */ + PSU_Mask_Write(DDRC_SARSIZE1_OFFSET, 0x000000FFU, 0x0000000FU); +/*##################################################################### */ + + /* + * Register : DFITMG0_SHADOW @ 0XFD072190 + + * Specifies the number of DFI clock cycles after an assertion or de-assert + * ion of the DFI control signals that the control signals at the PHY-DRAM + * interface reflect the assertion or de-assertion. If the DFI clock and th + * e memory clock are not phase-aligned, this timing parameter should be ro + * unded up to the next integer value. Note that if using RDIMM, it is nece + * ssary to increment this parameter by RDIMM's extra cycle of latency in t + * erms of DFI clock. + * PSU_DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY 0x7 + + * Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated u + * sing HDR or SDR values Selects whether value in DFITMG0.dfi_t_rddata_en + * is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles + * - 1 in terms of SDR clock cycles Refer to PHY specification for correct + * value. + * PSU_DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR 0x1 + + * Time from the assertion of a read command on the DFI interface to the as + * sertion of the dfi_rddata_en signal. Refer to PHY specification for corr + * ect value. This corresponds to the DFI parameter trddata_en. Note that, + * depending on the PHY, if using RDIMM, it may be necessary to use the val + * ue (CL + 1) in the calculation of trddata_en. This is to compensate for + * the extra cycle of latency through the RDIMM. Unit: Clocks + * PSU_DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN 0x2 + + * Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated us + * ing HDR or SDR values Selects whether value in DFITMG0.dfi_tphy_wrlat is + * in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.df + * i_tphy_wrdata is in terms of SDR or HDR clock cycles - 0 in terms of HDR + * clock cycles - 1 in terms of SDR clock cycles Refer to PHY specificatio + * n for correct value. + * PSU_DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR 0x1 + + * Specifies the number of clock cycles between when dfi_wrdata_en is asser + * ted to when the associated write data is driven on the dfi_wrdata signal + * . This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY + * specification for correct value. Note, max supported value is 8. Unit: + * Clocks + * PSU_DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA 0x0 + + * Write latency Number of clocks from the write command to write data enab + * le (dfi_wrdata_en). This corresponds to the DFI timing parameter tphy_wr + * lat. Refer to PHY specification for correct value.Note that, depending o + * n the PHY, if using RDIMM, it may be necessary to use the value (CL + 1) + * in the calculation of tphy_wrlat. This is to compensate for the extra c + * ycle of latency through the RDIMM. + * PSU_DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT 0x2 + + * DFI Timing Shadow Register 0 + * (OFFSET, MASK, VALUE) (0XFD072190, 0x1FBFBF3FU ,0x07828002U) + */ + PSU_Mask_Write(DDRC_DFITMG0_SHADOW_OFFSET, 0x1FBFBF3FU, 0x07828002U); +/*##################################################################### */ + + /* + * DDR CONTROLLER RESET + */ + /* + * Register : RST_DDR_SS @ 0XFD1A0108 + + * DDR block level reset inside of the DDR Sub System + * PSU_CRF_APB_RST_DDR_SS_DDR_RESET 0X0 + + * APM block level reset inside of the DDR Sub System + * PSU_CRF_APB_RST_DDR_SS_APM_RESET 0X0 + + * DDR sub system block level reset + * (OFFSET, MASK, VALUE) (0XFD1A0108, 0x0000000CU ,0x00000000U) + */ + PSU_Mask_Write(CRF_APB_RST_DDR_SS_OFFSET, 0x0000000CU, 0x00000000U); +/*##################################################################### */ + + /* + * DDR PHY + */ + /* + * Register : PGCR0 @ 0XFD080010 + + * Address Copy + * PSU_DDR_PHY_PGCR0_ADCP 0x0 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_PGCR0_RESERVED_30_27 0x0 + + * PHY FIFO Reset + * PSU_DDR_PHY_PGCR0_PHYFRST 0x1 + + * Oscillator Mode Address/Command Delay Line Select + * PSU_DDR_PHY_PGCR0_OSCACDL 0x3 + + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_PGCR0_RESERVED_23_19 0x0 + + * Digital Test Output Select + * PSU_DDR_PHY_PGCR0_DTOSEL 0x0 - RegVal = ((0x0000000FU << DDRC_SARSIZE1_NBLOCKS_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_SARSIZE1_OFFSET ,0x000000FFU ,0x0000000FU); - /*############################################################################################################################ */ + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_PGCR0_RESERVED_13 0x0 - /*Register : DFITMG0_SHADOW @ 0XFD072190

+ * Oscillator Mode Division + * PSU_DDR_PHY_PGCR0_OSCDIV 0xf - Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signa - s at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligne - , this timing parameter should be rounded up to the next integer value. Note that if using RDIMM, it is necessary to incremen - this parameter by RDIMM's extra cycle of latency in terms of DFI clock. - PSU_DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY 0x7 - - Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR or SDR values Selects whether value in DFITM - 0.dfi_t_rddata_en is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles R - fer to PHY specification for correct value. - PSU_DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR 0x1 - - Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. Refer to PHY spe - ification for correct value. This corresponds to the DFI parameter trddata_en. Note that, depending on the PHY, if using RDIM - , it may be necessary to use the value (CL + 1) in the calculation of trddata_en. This is to compensate for the extra cycle o - latency through the RDIMM. Unit: Clocks - PSU_DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN 0x2 - - Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using HDR or SDR values Selects whether value in DFITMG - .dfi_tphy_wrlat is in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.dfi_tphy_wrdata is in terms of SDR or - HDR clock cycles - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles Refer to PHY specification for correct val - e. - PSU_DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR 0x1 - - Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on th - dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. N - te, max supported value is 8. Unit: Clocks - PSU_DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA 0x0 - - Write latency Number of clocks from the write command to write data enable (dfi_wrdata_en). This corresponds to the DFI timin - parameter tphy_wrlat. Refer to PHY specification for correct value.Note that, depending on the PHY, if using RDIMM, it may b - necessary to use the value (CL + 1) in the calculation of tphy_wrlat. This is to compensate for the extra cycle of latency t - rough the RDIMM. - PSU_DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT 0x2 + * Oscillator Enable + * PSU_DDR_PHY_PGCR0_OSCEN 0x0 - DFI Timing Shadow Register 0 - (OFFSET, MASK, VALUE) (0XFD072190, 0x1FBFBF3FU ,0x07828002U) - RegMask = (DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_MASK | DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_MASK | DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_MASK | DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_MASK | DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_MASK | DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_MASK | 0 ); + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_PGCR0_RESERVED_7_0 0x0 - RegVal = ((0x00000007U << DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_SHIFT - | 0x00000001U << DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_SHIFT - | 0x00000002U << DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_SHIFT - | 0x00000001U << DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_SHIFT - | 0x00000000U << DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_SHIFT - | 0x00000002U << DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDRC_DFITMG0_SHADOW_OFFSET ,0x1FBFBF3FU ,0x07828002U); - /*############################################################################################################################ */ - - // : DDR CONTROLLER RESET - /*Register : RST_DDR_SS @ 0XFD1A0108

- - DDR block level reset inside of the DDR Sub System - PSU_CRF_APB_RST_DDR_SS_DDR_RESET 0X0 - - DDR sub system block level reset - (OFFSET, MASK, VALUE) (0XFD1A0108, 0x00000008U ,0x00000000U) - RegMask = (CRF_APB_RST_DDR_SS_DDR_RESET_MASK | 0 ); - - RegVal = ((0x00000000U << CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_RST_DDR_SS_OFFSET ,0x00000008U ,0x00000000U); - /*############################################################################################################################ */ - - // : DDR PHY - /*Register : PGCR0 @ 0XFD080010

- - Address Copy - PSU_DDR_PHY_PGCR0_ADCP 0x0 - - Reserved. Returns zeroes on reads. - PSU_DDR_PHY_PGCR0_RESERVED_30_27 0x0 - - PHY FIFO Reset - PSU_DDR_PHY_PGCR0_PHYFRST 0x1 - - Oscillator Mode Address/Command Delay Line Select - PSU_DDR_PHY_PGCR0_OSCACDL 0x3 - - Reserved. Returns zeroes on reads. - PSU_DDR_PHY_PGCR0_RESERVED_23_19 0x0 + * PHY General Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD080010, 0xFFFFFFFFU ,0x07001E00U) + */ + PSU_Mask_Write(DDR_PHY_PGCR0_OFFSET, 0xFFFFFFFFU, 0x07001E00U); +/*##################################################################### */ - Digital Test Output Select - PSU_DDR_PHY_PGCR0_DTOSEL 0x0 + /* + * Register : PGCR2 @ 0XFD080018 - Reserved. Returns zeroes on reads. - PSU_DDR_PHY_PGCR0_RESERVED_13 0x0 + * Clear Training Status Registers + * PSU_DDR_PHY_PGCR2_CLRTSTAT 0x0 - Oscillator Mode Division - PSU_DDR_PHY_PGCR0_OSCDIV 0xf + * Clear Impedance Calibration + * PSU_DDR_PHY_PGCR2_CLRZCAL 0x0 - Oscillator Enable - PSU_DDR_PHY_PGCR0_OSCEN 0x0 + * Clear Parity Error + * PSU_DDR_PHY_PGCR2_CLRPERR 0x0 - Reserved. Returns zeroes on reads. - PSU_DDR_PHY_PGCR0_RESERVED_7_0 0x0 + * Initialization Complete Pin Configuration + * PSU_DDR_PHY_PGCR2_ICPC 0x0 - PHY General Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD080010, 0xFFFFFFFFU ,0x07001E00U) - RegMask = (DDR_PHY_PGCR0_ADCP_MASK | DDR_PHY_PGCR0_RESERVED_30_27_MASK | DDR_PHY_PGCR0_PHYFRST_MASK | DDR_PHY_PGCR0_OSCACDL_MASK | DDR_PHY_PGCR0_RESERVED_23_19_MASK | DDR_PHY_PGCR0_DTOSEL_MASK | DDR_PHY_PGCR0_RESERVED_13_MASK | DDR_PHY_PGCR0_OSCDIV_MASK | DDR_PHY_PGCR0_OSCEN_MASK | DDR_PHY_PGCR0_RESERVED_7_0_MASK | 0 ); + * Data Training PUB Mode Exit Timer + * PSU_DDR_PHY_PGCR2_DTPMXTMR 0xf - RegVal = ((0x00000000U << DDR_PHY_PGCR0_ADCP_SHIFT - | 0x00000000U << DDR_PHY_PGCR0_RESERVED_30_27_SHIFT - | 0x00000001U << DDR_PHY_PGCR0_PHYFRST_SHIFT - | 0x00000003U << DDR_PHY_PGCR0_OSCACDL_SHIFT - | 0x00000000U << DDR_PHY_PGCR0_RESERVED_23_19_SHIFT - | 0x00000000U << DDR_PHY_PGCR0_DTOSEL_SHIFT - | 0x00000000U << DDR_PHY_PGCR0_RESERVED_13_SHIFT - | 0x0000000FU << DDR_PHY_PGCR0_OSCDIV_SHIFT - | 0x00000000U << DDR_PHY_PGCR0_OSCEN_SHIFT - | 0x00000000U << DDR_PHY_PGCR0_RESERVED_7_0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_PGCR0_OFFSET ,0xFFFFFFFFU ,0x07001E00U); - /*############################################################################################################################ */ - - /*Register : PGCR2 @ 0XFD080018

+ * Initialization Bypass + * PSU_DDR_PHY_PGCR2_INITFSMBYP 0x0 - Clear Training Status Registers - PSU_DDR_PHY_PGCR2_CLRTSTAT 0x0 + * PLL FSM Bypass + * PSU_DDR_PHY_PGCR2_PLLFSMBYP 0x0 - Clear Impedance Calibration - PSU_DDR_PHY_PGCR2_CLRZCAL 0x0 + * Refresh Period + * PSU_DDR_PHY_PGCR2_TREFPRD 0x10010 - Clear Parity Error - PSU_DDR_PHY_PGCR2_CLRPERR 0x0 + * PHY General Configuration Register 2 + * (OFFSET, MASK, VALUE) (0XFD080018, 0xFFFFFFFFU ,0x00F10010U) + */ + PSU_Mask_Write(DDR_PHY_PGCR2_OFFSET, 0xFFFFFFFFU, 0x00F10010U); +/*##################################################################### */ - Initialization Complete Pin Configuration - PSU_DDR_PHY_PGCR2_ICPC 0x0 + /* + * Register : PGCR3 @ 0XFD08001C - Data Training PUB Mode Exit Timer - PSU_DDR_PHY_PGCR2_DTPMXTMR 0xf + * CKN Enable + * PSU_DDR_PHY_PGCR3_CKNEN 0x55 - Initialization Bypass - PSU_DDR_PHY_PGCR2_INITFSMBYP 0x0 + * CK Enable + * PSU_DDR_PHY_PGCR3_CKEN 0xaa - PLL FSM Bypass - PSU_DDR_PHY_PGCR2_PLLFSMBYP 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_PGCR3_RESERVED_15 0x0 - Refresh Period - PSU_DDR_PHY_PGCR2_TREFPRD 0x10028 + * Enable Clock Gating for AC [0] ctl_rd_clk + * PSU_DDR_PHY_PGCR3_GATEACRDCLK 0x2 - PHY General Configuration Register 2 - (OFFSET, MASK, VALUE) (0XFD080018, 0xFFFFFFFFU ,0x00F10028U) - RegMask = (DDR_PHY_PGCR2_CLRTSTAT_MASK | DDR_PHY_PGCR2_CLRZCAL_MASK | DDR_PHY_PGCR2_CLRPERR_MASK | DDR_PHY_PGCR2_ICPC_MASK | DDR_PHY_PGCR2_DTPMXTMR_MASK | DDR_PHY_PGCR2_INITFSMBYP_MASK | DDR_PHY_PGCR2_PLLFSMBYP_MASK | DDR_PHY_PGCR2_TREFPRD_MASK | 0 ); + * Enable Clock Gating for AC [0] ddr_clk + * PSU_DDR_PHY_PGCR3_GATEACDDRCLK 0x2 - RegVal = ((0x00000000U << DDR_PHY_PGCR2_CLRTSTAT_SHIFT - | 0x00000000U << DDR_PHY_PGCR2_CLRZCAL_SHIFT - | 0x00000000U << DDR_PHY_PGCR2_CLRPERR_SHIFT - | 0x00000000U << DDR_PHY_PGCR2_ICPC_SHIFT - | 0x0000000FU << DDR_PHY_PGCR2_DTPMXTMR_SHIFT - | 0x00000000U << DDR_PHY_PGCR2_INITFSMBYP_SHIFT - | 0x00000000U << DDR_PHY_PGCR2_PLLFSMBYP_SHIFT - | 0x00010028U << DDR_PHY_PGCR2_TREFPRD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_PGCR2_OFFSET ,0xFFFFFFFFU ,0x00F10028U); - /*############################################################################################################################ */ + * Enable Clock Gating for AC [0] ctl_clk + * PSU_DDR_PHY_PGCR3_GATEACCTLCLK 0x2 - /*Register : PGCR3 @ 0XFD08001C

+ * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_PGCR3_RESERVED_8 0x0 - CKN Enable - PSU_DDR_PHY_PGCR3_CKNEN 0x55 + * Controls DDL Bypass Modes + * PSU_DDR_PHY_PGCR3_DDLBYPMODE 0x2 - CK Enable - PSU_DDR_PHY_PGCR3_CKEN 0xaa + * IO Loop-Back Select + * PSU_DDR_PHY_PGCR3_IOLB 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_PGCR3_RESERVED_15 0x0 + * AC Receive FIFO Read Mode + * PSU_DDR_PHY_PGCR3_RDMODE 0x0 - Enable Clock Gating for AC [0] ctl_rd_clk - PSU_DDR_PHY_PGCR3_GATEACRDCLK 0x2 + * Read FIFO Reset Disable + * PSU_DDR_PHY_PGCR3_DISRST 0x0 - Enable Clock Gating for AC [0] ddr_clk - PSU_DDR_PHY_PGCR3_GATEACDDRCLK 0x2 + * Clock Level when Clock Gating + * PSU_DDR_PHY_PGCR3_CLKLEVEL 0x0 - Enable Clock Gating for AC [0] ctl_clk - PSU_DDR_PHY_PGCR3_GATEACCTLCLK 0x2 + * PHY General Configuration Register 3 + * (OFFSET, MASK, VALUE) (0XFD08001C, 0xFFFFFFFFU ,0x55AA5480U) + */ + PSU_Mask_Write(DDR_PHY_PGCR3_OFFSET, 0xFFFFFFFFU, 0x55AA5480U); +/*##################################################################### */ - Reserved. Return zeroes on reads. - PSU_DDR_PHY_PGCR3_RESERVED_8 0x0 + /* + * Register : PGCR5 @ 0XFD080024 - Controls DDL Bypass Modes - PSU_DDR_PHY_PGCR3_DDLBYPMODE 0x2 + * Frequency B Ratio Term + * PSU_DDR_PHY_PGCR5_FRQBT 0x1 - IO Loop-Back Select - PSU_DDR_PHY_PGCR3_IOLB 0x0 + * Frequency A Ratio Term + * PSU_DDR_PHY_PGCR5_FRQAT 0x1 - AC Receive FIFO Read Mode - PSU_DDR_PHY_PGCR3_RDMODE 0x0 + * DFI Disconnect Time Period + * PSU_DDR_PHY_PGCR5_DISCNPERIOD 0x0 - Read FIFO Reset Disable - PSU_DDR_PHY_PGCR3_DISRST 0x0 + * Receiver bias core side control + * PSU_DDR_PHY_PGCR5_VREF_RBCTRL 0xf - Clock Level when Clock Gating - PSU_DDR_PHY_PGCR3_CLKLEVEL 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_PGCR5_RESERVED_3 0x0 - PHY General Configuration Register 3 - (OFFSET, MASK, VALUE) (0XFD08001C, 0xFFFFFFFFU ,0x55AA5480U) - RegMask = (DDR_PHY_PGCR3_CKNEN_MASK | DDR_PHY_PGCR3_CKEN_MASK | DDR_PHY_PGCR3_RESERVED_15_MASK | DDR_PHY_PGCR3_GATEACRDCLK_MASK | DDR_PHY_PGCR3_GATEACDDRCLK_MASK | DDR_PHY_PGCR3_GATEACCTLCLK_MASK | DDR_PHY_PGCR3_RESERVED_8_MASK | DDR_PHY_PGCR3_DDLBYPMODE_MASK | DDR_PHY_PGCR3_IOLB_MASK | DDR_PHY_PGCR3_RDMODE_MASK | DDR_PHY_PGCR3_DISRST_MASK | DDR_PHY_PGCR3_CLKLEVEL_MASK | 0 ); + * Internal VREF generator REFSEL ragne select + * PSU_DDR_PHY_PGCR5_DXREFISELRANGE 0x1 - RegVal = ((0x00000055U << DDR_PHY_PGCR3_CKNEN_SHIFT - | 0x000000AAU << DDR_PHY_PGCR3_CKEN_SHIFT - | 0x00000000U << DDR_PHY_PGCR3_RESERVED_15_SHIFT - | 0x00000002U << DDR_PHY_PGCR3_GATEACRDCLK_SHIFT - | 0x00000002U << DDR_PHY_PGCR3_GATEACDDRCLK_SHIFT - | 0x00000002U << DDR_PHY_PGCR3_GATEACCTLCLK_SHIFT - | 0x00000000U << DDR_PHY_PGCR3_RESERVED_8_SHIFT - | 0x00000002U << DDR_PHY_PGCR3_DDLBYPMODE_SHIFT - | 0x00000000U << DDR_PHY_PGCR3_IOLB_SHIFT - | 0x00000000U << DDR_PHY_PGCR3_RDMODE_SHIFT - | 0x00000000U << DDR_PHY_PGCR3_DISRST_SHIFT - | 0x00000000U << DDR_PHY_PGCR3_CLKLEVEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_PGCR3_OFFSET ,0xFFFFFFFFU ,0x55AA5480U); - /*############################################################################################################################ */ + * DDL Page Read Write select + * PSU_DDR_PHY_PGCR5_DDLPGACT 0x0 - /*Register : PGCR5 @ 0XFD080024

+ * DDL Page Read Write select + * PSU_DDR_PHY_PGCR5_DDLPGRW 0x0 - Frequency B Ratio Term - PSU_DDR_PHY_PGCR5_FRQBT 0x1 + * PHY General Configuration Register 5 + * (OFFSET, MASK, VALUE) (0XFD080024, 0xFFFFFFFFU ,0x010100F4U) + */ + PSU_Mask_Write(DDR_PHY_PGCR5_OFFSET, 0xFFFFFFFFU, 0x010100F4U); +/*##################################################################### */ - Frequency A Ratio Term - PSU_DDR_PHY_PGCR5_FRQAT 0x1 + /* + * Register : PTR0 @ 0XFD080040 - DFI Disconnect Time Period - PSU_DDR_PHY_PGCR5_DISCNPERIOD 0x0 + * PLL Power-Down Time + * PSU_DDR_PHY_PTR0_TPLLPD 0x56 - Receiver bias core side control - PSU_DDR_PHY_PGCR5_VREF_RBCTRL 0xf + * PLL Gear Shift Time + * PSU_DDR_PHY_PTR0_TPLLGS 0x2155 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_PGCR5_RESERVED_3 0x0 + * PHY Reset Time + * PSU_DDR_PHY_PTR0_TPHYRST 0x10 - Internal VREF generator REFSEL ragne select - PSU_DDR_PHY_PGCR5_DXREFISELRANGE 0x1 + * PHY Timing Register 0 + * (OFFSET, MASK, VALUE) (0XFD080040, 0xFFFFFFFFU ,0x0AC85550U) + */ + PSU_Mask_Write(DDR_PHY_PTR0_OFFSET, 0xFFFFFFFFU, 0x0AC85550U); +/*##################################################################### */ - DDL Page Read Write select - PSU_DDR_PHY_PGCR5_DDLPGACT 0x0 + /* + * Register : PTR1 @ 0XFD080044 - DDL Page Read Write select - PSU_DDR_PHY_PGCR5_DDLPGRW 0x0 + * PLL Lock Time + * PSU_DDR_PHY_PTR1_TPLLLOCK 0x4141 - PHY General Configuration Register 5 - (OFFSET, MASK, VALUE) (0XFD080024, 0xFFFFFFFFU ,0x010100F4U) - RegMask = (DDR_PHY_PGCR5_FRQBT_MASK | DDR_PHY_PGCR5_FRQAT_MASK | DDR_PHY_PGCR5_DISCNPERIOD_MASK | DDR_PHY_PGCR5_VREF_RBCTRL_MASK | DDR_PHY_PGCR5_RESERVED_3_MASK | DDR_PHY_PGCR5_DXREFISELRANGE_MASK | DDR_PHY_PGCR5_DDLPGACT_MASK | DDR_PHY_PGCR5_DDLPGRW_MASK | 0 ); + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_PTR1_RESERVED_15_13 0x0 - RegVal = ((0x00000001U << DDR_PHY_PGCR5_FRQBT_SHIFT - | 0x00000001U << DDR_PHY_PGCR5_FRQAT_SHIFT - | 0x00000000U << DDR_PHY_PGCR5_DISCNPERIOD_SHIFT - | 0x0000000FU << DDR_PHY_PGCR5_VREF_RBCTRL_SHIFT - | 0x00000000U << DDR_PHY_PGCR5_RESERVED_3_SHIFT - | 0x00000001U << DDR_PHY_PGCR5_DXREFISELRANGE_SHIFT - | 0x00000000U << DDR_PHY_PGCR5_DDLPGACT_SHIFT - | 0x00000000U << DDR_PHY_PGCR5_DDLPGRW_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_PGCR5_OFFSET ,0xFFFFFFFFU ,0x010100F4U); - /*############################################################################################################################ */ + * PLL Reset Time + * PSU_DDR_PHY_PTR1_TPLLRST 0xaff - /*Register : PTR0 @ 0XFD080040

+ * PHY Timing Register 1 + * (OFFSET, MASK, VALUE) (0XFD080044, 0xFFFFFFFFU ,0x41410AFFU) + */ + PSU_Mask_Write(DDR_PHY_PTR1_OFFSET, 0xFFFFFFFFU, 0x41410AFFU); +/*##################################################################### */ - PLL Power-Down Time - PSU_DDR_PHY_PTR0_TPLLPD 0x2f0 + /* + * Register : PLLCR0 @ 0XFD080068 - PLL Gear Shift Time - PSU_DDR_PHY_PTR0_TPLLGS 0x60 + * PLL Bypass + * PSU_DDR_PHY_PLLCR0_PLLBYP 0x0 - PHY Reset Time - PSU_DDR_PHY_PTR0_TPHYRST 0x10 + * PLL Reset + * PSU_DDR_PHY_PLLCR0_PLLRST 0x0 - PHY Timing Register 0 - (OFFSET, MASK, VALUE) (0XFD080040, 0xFFFFFFFFU ,0x5E001810U) - RegMask = (DDR_PHY_PTR0_TPLLPD_MASK | DDR_PHY_PTR0_TPLLGS_MASK | DDR_PHY_PTR0_TPHYRST_MASK | 0 ); + * PLL Power Down + * PSU_DDR_PHY_PLLCR0_PLLPD 0x0 - RegVal = ((0x000002F0U << DDR_PHY_PTR0_TPLLPD_SHIFT - | 0x00000060U << DDR_PHY_PTR0_TPLLGS_SHIFT - | 0x00000010U << DDR_PHY_PTR0_TPHYRST_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_PTR0_OFFSET ,0xFFFFFFFFU ,0x5E001810U); - /*############################################################################################################################ */ + * Reference Stop Mode + * PSU_DDR_PHY_PLLCR0_RSTOPM 0x0 - /*Register : PTR1 @ 0XFD080044

+ * PLL Frequency Select + * PSU_DDR_PHY_PLLCR0_FRQSEL 0x1 - PLL Lock Time - PSU_DDR_PHY_PTR1_TPLLLOCK 0x80 + * Relock Mode + * PSU_DDR_PHY_PLLCR0_RLOCKM 0x0 - Reserved. Returns zeroes on reads. - PSU_DDR_PHY_PTR1_RESERVED_15_13 0x0 + * Charge Pump Proportional Current Control + * PSU_DDR_PHY_PLLCR0_CPPC 0x8 - PLL Reset Time - PSU_DDR_PHY_PTR1_TPLLRST 0x5f0 - - PHY Timing Register 1 - (OFFSET, MASK, VALUE) (0XFD080044, 0xFFFFFFFFU ,0x008005F0U) - RegMask = (DDR_PHY_PTR1_TPLLLOCK_MASK | DDR_PHY_PTR1_RESERVED_15_13_MASK | DDR_PHY_PTR1_TPLLRST_MASK | 0 ); + * Charge Pump Integrating Current Control + * PSU_DDR_PHY_PLLCR0_CPIC 0x0 - RegVal = ((0x00000080U << DDR_PHY_PTR1_TPLLLOCK_SHIFT - | 0x00000000U << DDR_PHY_PTR1_RESERVED_15_13_SHIFT - | 0x000005F0U << DDR_PHY_PTR1_TPLLRST_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_PTR1_OFFSET ,0xFFFFFFFFU ,0x008005F0U); - /*############################################################################################################################ */ + * Gear Shift + * PSU_DDR_PHY_PLLCR0_GSHIFT 0x0 - /*Register : DSGCR @ 0XFD080090

+ * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_PLLCR0_RESERVED_11_9 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DSGCR_RESERVED_31_28 0x0 + * Analog Test Enable + * PSU_DDR_PHY_PLLCR0_ATOEN 0x0 - When RDBI enabled, this bit is used to select RDBI CL calculation, if it is 1b1, calculation will use RDBICL, otherwise use d - fault calculation. - PSU_DDR_PHY_DSGCR_RDBICLSEL 0x0 + * Analog Test Control + * PSU_DDR_PHY_PLLCR0_ATC 0x0 - When RDBI enabled, if RDBICLSEL is asserted, RDBI CL adjust using this value. - PSU_DDR_PHY_DSGCR_RDBICL 0x2 + * Digital Test Control + * PSU_DDR_PHY_PLLCR0_DTC 0x0 - PHY Impedance Update Enable - PSU_DDR_PHY_DSGCR_PHYZUEN 0x1 + * PLL Control Register 0 (Type B PLL Only) + * (OFFSET, MASK, VALUE) (0XFD080068, 0xFFFFFFFFU ,0x01100000U) + */ + PSU_Mask_Write(DDR_PHY_PLLCR0_OFFSET, 0xFFFFFFFFU, 0x01100000U); +/*##################################################################### */ - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DSGCR_RESERVED_22 0x0 + /* + * Register : DSGCR @ 0XFD080090 - SDRAM Reset Output Enable - PSU_DDR_PHY_DSGCR_RSTOE 0x1 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DSGCR_RESERVED_31_28 0x0 - Single Data Rate Mode - PSU_DDR_PHY_DSGCR_SDRMODE 0x0 + * When RDBI enabled, this bit is used to select RDBI CL calculation, if it + * is 1b1, calculation will use RDBICL, otherwise use default calculation. + * PSU_DDR_PHY_DSGCR_RDBICLSEL 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DSGCR_RESERVED_18 0x0 + * When RDBI enabled, if RDBICLSEL is asserted, RDBI CL adjust using this v + * alue. + * PSU_DDR_PHY_DSGCR_RDBICL 0x2 - ATO Analog Test Enable - PSU_DDR_PHY_DSGCR_ATOAE 0x0 + * PHY Impedance Update Enable + * PSU_DDR_PHY_DSGCR_PHYZUEN 0x1 - DTO Output Enable - PSU_DDR_PHY_DSGCR_DTOOE 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DSGCR_RESERVED_22 0x0 - DTO I/O Mode - PSU_DDR_PHY_DSGCR_DTOIOM 0x0 + * SDRAM Reset Output Enable + * PSU_DDR_PHY_DSGCR_RSTOE 0x1 - DTO Power Down Receiver - PSU_DDR_PHY_DSGCR_DTOPDR 0x1 + * Single Data Rate Mode + * PSU_DDR_PHY_DSGCR_SDRMODE 0x0 - Reserved. Return zeroes on reads - PSU_DDR_PHY_DSGCR_RESERVED_13 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DSGCR_RESERVED_18 0x0 - DTO On-Die Termination - PSU_DDR_PHY_DSGCR_DTOODT 0x0 + * ATO Analog Test Enable + * PSU_DDR_PHY_DSGCR_ATOAE 0x0 - PHY Update Acknowledge Delay - PSU_DDR_PHY_DSGCR_PUAD 0x4 + * DTO Output Enable + * PSU_DDR_PHY_DSGCR_DTOOE 0x0 - Controller Update Acknowledge Enable - PSU_DDR_PHY_DSGCR_CUAEN 0x1 + * DTO I/O Mode + * PSU_DDR_PHY_DSGCR_DTOIOM 0x0 - Reserved. Return zeroes on reads - PSU_DDR_PHY_DSGCR_RESERVED_4_3 0x0 + * DTO Power Down Receiver + * PSU_DDR_PHY_DSGCR_DTOPDR 0x1 - Controller Impedance Update Enable - PSU_DDR_PHY_DSGCR_CTLZUEN 0x0 + * Reserved. Return zeroes on reads + * PSU_DDR_PHY_DSGCR_RESERVED_13 0x0 - Reserved. Return zeroes on reads - PSU_DDR_PHY_DSGCR_RESERVED_1 0x0 + * DTO On-Die Termination + * PSU_DDR_PHY_DSGCR_DTOODT 0x0 - PHY Update Request Enable - PSU_DDR_PHY_DSGCR_PUREN 0x1 + * PHY Update Acknowledge Delay + * PSU_DDR_PHY_DSGCR_PUAD 0x5 - DDR System General Configuration Register - (OFFSET, MASK, VALUE) (0XFD080090, 0xFFFFFFFFU ,0x02A04121U) - RegMask = (DDR_PHY_DSGCR_RESERVED_31_28_MASK | DDR_PHY_DSGCR_RDBICLSEL_MASK | DDR_PHY_DSGCR_RDBICL_MASK | DDR_PHY_DSGCR_PHYZUEN_MASK | DDR_PHY_DSGCR_RESERVED_22_MASK | DDR_PHY_DSGCR_RSTOE_MASK | DDR_PHY_DSGCR_SDRMODE_MASK | DDR_PHY_DSGCR_RESERVED_18_MASK | DDR_PHY_DSGCR_ATOAE_MASK | DDR_PHY_DSGCR_DTOOE_MASK | DDR_PHY_DSGCR_DTOIOM_MASK | DDR_PHY_DSGCR_DTOPDR_MASK | DDR_PHY_DSGCR_RESERVED_13_MASK | DDR_PHY_DSGCR_DTOODT_MASK | DDR_PHY_DSGCR_PUAD_MASK | DDR_PHY_DSGCR_CUAEN_MASK | DDR_PHY_DSGCR_RESERVED_4_3_MASK | DDR_PHY_DSGCR_CTLZUEN_MASK | DDR_PHY_DSGCR_RESERVED_1_MASK | DDR_PHY_DSGCR_PUREN_MASK | 0 ); + * Controller Update Acknowledge Enable + * PSU_DDR_PHY_DSGCR_CUAEN 0x1 - RegVal = ((0x00000000U << DDR_PHY_DSGCR_RESERVED_31_28_SHIFT - | 0x00000000U << DDR_PHY_DSGCR_RDBICLSEL_SHIFT - | 0x00000002U << DDR_PHY_DSGCR_RDBICL_SHIFT - | 0x00000001U << DDR_PHY_DSGCR_PHYZUEN_SHIFT - | 0x00000000U << DDR_PHY_DSGCR_RESERVED_22_SHIFT - | 0x00000001U << DDR_PHY_DSGCR_RSTOE_SHIFT - | 0x00000000U << DDR_PHY_DSGCR_SDRMODE_SHIFT - | 0x00000000U << DDR_PHY_DSGCR_RESERVED_18_SHIFT - | 0x00000000U << DDR_PHY_DSGCR_ATOAE_SHIFT - | 0x00000000U << DDR_PHY_DSGCR_DTOOE_SHIFT - | 0x00000000U << DDR_PHY_DSGCR_DTOIOM_SHIFT - | 0x00000001U << DDR_PHY_DSGCR_DTOPDR_SHIFT - | 0x00000000U << DDR_PHY_DSGCR_RESERVED_13_SHIFT - | 0x00000000U << DDR_PHY_DSGCR_DTOODT_SHIFT - | 0x00000004U << DDR_PHY_DSGCR_PUAD_SHIFT - | 0x00000001U << DDR_PHY_DSGCR_CUAEN_SHIFT - | 0x00000000U << DDR_PHY_DSGCR_RESERVED_4_3_SHIFT - | 0x00000000U << DDR_PHY_DSGCR_CTLZUEN_SHIFT - | 0x00000000U << DDR_PHY_DSGCR_RESERVED_1_SHIFT - | 0x00000001U << DDR_PHY_DSGCR_PUREN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DSGCR_OFFSET ,0xFFFFFFFFU ,0x02A04121U); - /*############################################################################################################################ */ + * Reserved. Return zeroes on reads + * PSU_DDR_PHY_DSGCR_RESERVED_4_3 0x0 - /*Register : DCR @ 0XFD080100

+ * Controller Impedance Update Enable + * PSU_DDR_PHY_DSGCR_CTLZUEN 0x0 - DDR4 Gear Down Timing. - PSU_DDR_PHY_DCR_GEARDN 0x0 + * Reserved. Return zeroes on reads + * PSU_DDR_PHY_DSGCR_RESERVED_1 0x0 - Un-used Bank Group - PSU_DDR_PHY_DCR_UBG 0x0 + * PHY Update Request Enable + * PSU_DDR_PHY_DSGCR_PUREN 0x1 - Un-buffered DIMM Address Mirroring - PSU_DDR_PHY_DCR_UDIMM 0x0 + * DDR System General Configuration Register + * (OFFSET, MASK, VALUE) (0XFD080090, 0xFFFFFFFFU ,0x02A04161U) + */ + PSU_Mask_Write(DDR_PHY_DSGCR_OFFSET, 0xFFFFFFFFU, 0x02A04161U); +/*##################################################################### */ - DDR 2T Timing - PSU_DDR_PHY_DCR_DDR2T 0x0 + /* + * Register : GPR0 @ 0XFD0800C0 - No Simultaneous Rank Access - PSU_DDR_PHY_DCR_NOSRA 0x1 + * General Purpose Register 0 + * PSU_DDR_PHY_GPR0_GPR0 0xd3 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DCR_RESERVED_26_18 0x0 + * General Purpose Register 0 + * (OFFSET, MASK, VALUE) (0XFD0800C0, 0xFFFFFFFFU ,0x000000D3U) + */ + PSU_Mask_Write(DDR_PHY_GPR0_OFFSET, 0xFFFFFFFFU, 0x000000D3U); +/*##################################################################### */ - Byte Mask - PSU_DDR_PHY_DCR_BYTEMASK 0x1 + /* + * Register : DCR @ 0XFD080100 - DDR Type - PSU_DDR_PHY_DCR_DDRTYPE 0x0 + * DDR4 Gear Down Timing. + * PSU_DDR_PHY_DCR_GEARDN 0x0 - Multi-Purpose Register (MPR) DQ (DDR3 Only) - PSU_DDR_PHY_DCR_MPRDQ 0x0 + * Un-used Bank Group + * PSU_DDR_PHY_DCR_UBG 0x0 - Primary DQ (DDR3 Only) - PSU_DDR_PHY_DCR_PDQ 0x0 + * Un-buffered DIMM Address Mirroring + * PSU_DDR_PHY_DCR_UDIMM 0x0 - DDR 8-Bank - PSU_DDR_PHY_DCR_DDR8BNK 0x1 + * DDR 2T Timing + * PSU_DDR_PHY_DCR_DDR2T 0x0 - DDR Mode - PSU_DDR_PHY_DCR_DDRMD 0x4 + * No Simultaneous Rank Access + * PSU_DDR_PHY_DCR_NOSRA 0x1 - DRAM Configuration Register - (OFFSET, MASK, VALUE) (0XFD080100, 0xFFFFFFFFU ,0x0800040CU) - RegMask = (DDR_PHY_DCR_GEARDN_MASK | DDR_PHY_DCR_UBG_MASK | DDR_PHY_DCR_UDIMM_MASK | DDR_PHY_DCR_DDR2T_MASK | DDR_PHY_DCR_NOSRA_MASK | DDR_PHY_DCR_RESERVED_26_18_MASK | DDR_PHY_DCR_BYTEMASK_MASK | DDR_PHY_DCR_DDRTYPE_MASK | DDR_PHY_DCR_MPRDQ_MASK | DDR_PHY_DCR_PDQ_MASK | DDR_PHY_DCR_DDR8BNK_MASK | DDR_PHY_DCR_DDRMD_MASK | 0 ); + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DCR_RESERVED_26_18 0x0 - RegVal = ((0x00000000U << DDR_PHY_DCR_GEARDN_SHIFT - | 0x00000000U << DDR_PHY_DCR_UBG_SHIFT - | 0x00000000U << DDR_PHY_DCR_UDIMM_SHIFT - | 0x00000000U << DDR_PHY_DCR_DDR2T_SHIFT - | 0x00000001U << DDR_PHY_DCR_NOSRA_SHIFT - | 0x00000000U << DDR_PHY_DCR_RESERVED_26_18_SHIFT - | 0x00000001U << DDR_PHY_DCR_BYTEMASK_SHIFT - | 0x00000000U << DDR_PHY_DCR_DDRTYPE_SHIFT - | 0x00000000U << DDR_PHY_DCR_MPRDQ_SHIFT - | 0x00000000U << DDR_PHY_DCR_PDQ_SHIFT - | 0x00000001U << DDR_PHY_DCR_DDR8BNK_SHIFT - | 0x00000004U << DDR_PHY_DCR_DDRMD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DCR_OFFSET ,0xFFFFFFFFU ,0x0800040CU); - /*############################################################################################################################ */ - - /*Register : DTPR0 @ 0XFD080110

+ * Byte Mask + * PSU_DDR_PHY_DCR_BYTEMASK 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR0_RESERVED_31_29 0x0 + * DDR Type + * PSU_DDR_PHY_DCR_DDRTYPE 0x0 - Activate to activate command delay (different banks) - PSU_DDR_PHY_DTPR0_TRRD 0x6 + * Multi-Purpose Register (MPR) DQ (DDR3 Only) + * PSU_DDR_PHY_DCR_MPRDQ 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR0_RESERVED_23 0x0 + * Primary DQ (DDR3 Only) + * PSU_DDR_PHY_DCR_PDQ 0x0 - Activate to precharge command delay - PSU_DDR_PHY_DTPR0_TRAS 0x24 + * DDR 8-Bank + * PSU_DDR_PHY_DCR_DDR8BNK 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR0_RESERVED_15 0x0 - - Precharge command period - PSU_DDR_PHY_DTPR0_TRP 0xf - - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR0_RESERVED_7_5 0x0 - - Internal read to precharge command delay - PSU_DDR_PHY_DTPR0_TRTP 0x9 - - DRAM Timing Parameters Register 0 - (OFFSET, MASK, VALUE) (0XFD080110, 0xFFFFFFFFU ,0x06240F09U) - RegMask = (DDR_PHY_DTPR0_RESERVED_31_29_MASK | DDR_PHY_DTPR0_TRRD_MASK | DDR_PHY_DTPR0_RESERVED_23_MASK | DDR_PHY_DTPR0_TRAS_MASK | DDR_PHY_DTPR0_RESERVED_15_MASK | DDR_PHY_DTPR0_TRP_MASK | DDR_PHY_DTPR0_RESERVED_7_5_MASK | DDR_PHY_DTPR0_TRTP_MASK | 0 ); + * DDR Mode + * PSU_DDR_PHY_DCR_DDRMD 0x4 - RegVal = ((0x00000000U << DDR_PHY_DTPR0_RESERVED_31_29_SHIFT - | 0x00000006U << DDR_PHY_DTPR0_TRRD_SHIFT - | 0x00000000U << DDR_PHY_DTPR0_RESERVED_23_SHIFT - | 0x00000024U << DDR_PHY_DTPR0_TRAS_SHIFT - | 0x00000000U << DDR_PHY_DTPR0_RESERVED_15_SHIFT - | 0x0000000FU << DDR_PHY_DTPR0_TRP_SHIFT - | 0x00000000U << DDR_PHY_DTPR0_RESERVED_7_5_SHIFT - | 0x00000009U << DDR_PHY_DTPR0_TRTP_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DTPR0_OFFSET ,0xFFFFFFFFU ,0x06240F09U); - /*############################################################################################################################ */ + * DRAM Configuration Register + * (OFFSET, MASK, VALUE) (0XFD080100, 0xFFFFFFFFU ,0x0800040CU) + */ + PSU_Mask_Write(DDR_PHY_DCR_OFFSET, 0xFFFFFFFFU, 0x0800040CU); +/*##################################################################### */ - /*Register : DTPR1 @ 0XFD080114

+ /* + * Register : DTPR0 @ 0XFD080110 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR1_RESERVED_31 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR0_RESERVED_31_29 0x0 - Minimum delay from when write leveling mode is programmed to the first DQS/DQS# rising edge. - PSU_DDR_PHY_DTPR1_TWLMRD 0x28 + * Activate to activate command delay (different banks) + * PSU_DDR_PHY_DTPR0_TRRD 0x6 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR1_RESERVED_23 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR0_RESERVED_23 0x0 - 4-bank activate period - PSU_DDR_PHY_DTPR1_TFAW 0x18 + * Activate to precharge command delay + * PSU_DDR_PHY_DTPR0_TRAS 0x24 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR1_RESERVED_15_11 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR0_RESERVED_15 0x0 - Load mode update delay (DDR4 and DDR3 only) - PSU_DDR_PHY_DTPR1_TMOD 0x7 + * Precharge command period + * PSU_DDR_PHY_DTPR0_TRP 0xf - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR1_RESERVED_7_5 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR0_RESERVED_7_5 0x0 - Load mode cycle time - PSU_DDR_PHY_DTPR1_TMRD 0x8 + * Internal read to precharge command delay + * PSU_DDR_PHY_DTPR0_TRTP 0x8 - DRAM Timing Parameters Register 1 - (OFFSET, MASK, VALUE) (0XFD080114, 0xFFFFFFFFU ,0x28180708U) - RegMask = (DDR_PHY_DTPR1_RESERVED_31_MASK | DDR_PHY_DTPR1_TWLMRD_MASK | DDR_PHY_DTPR1_RESERVED_23_MASK | DDR_PHY_DTPR1_TFAW_MASK | DDR_PHY_DTPR1_RESERVED_15_11_MASK | DDR_PHY_DTPR1_TMOD_MASK | DDR_PHY_DTPR1_RESERVED_7_5_MASK | DDR_PHY_DTPR1_TMRD_MASK | 0 ); + * DRAM Timing Parameters Register 0 + * (OFFSET, MASK, VALUE) (0XFD080110, 0xFFFFFFFFU ,0x06240F08U) + */ + PSU_Mask_Write(DDR_PHY_DTPR0_OFFSET, 0xFFFFFFFFU, 0x06240F08U); +/*##################################################################### */ - RegVal = ((0x00000000U << DDR_PHY_DTPR1_RESERVED_31_SHIFT - | 0x00000028U << DDR_PHY_DTPR1_TWLMRD_SHIFT - | 0x00000000U << DDR_PHY_DTPR1_RESERVED_23_SHIFT - | 0x00000018U << DDR_PHY_DTPR1_TFAW_SHIFT - | 0x00000000U << DDR_PHY_DTPR1_RESERVED_15_11_SHIFT - | 0x00000007U << DDR_PHY_DTPR1_TMOD_SHIFT - | 0x00000000U << DDR_PHY_DTPR1_RESERVED_7_5_SHIFT - | 0x00000008U << DDR_PHY_DTPR1_TMRD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DTPR1_OFFSET ,0xFFFFFFFFU ,0x28180708U); - /*############################################################################################################################ */ + /* + * Register : DTPR1 @ 0XFD080114 - /*Register : DTPR2 @ 0XFD080118

+ * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR1_RESERVED_31 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR2_RESERVED_31_29 0x0 + * Minimum delay from when write leveling mode is programmed to the first D + * QS/DQS# rising edge. + * PSU_DDR_PHY_DTPR1_TWLMRD 0x28 - Read to Write command delay. Valid values are - PSU_DDR_PHY_DTPR2_TRTW 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR1_RESERVED_23 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR2_RESERVED_27_25 0x0 + * 4-bank activate period + * PSU_DDR_PHY_DTPR1_TFAW 0x20 - Read to ODT delay (DDR3 only) - PSU_DDR_PHY_DTPR2_TRTODT 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR1_RESERVED_15_11 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR2_RESERVED_23_20 0x0 + * Load mode update delay (DDR4 and DDR3 only) + * PSU_DDR_PHY_DTPR1_TMOD 0x0 - CKE minimum pulse width - PSU_DDR_PHY_DTPR2_TCKE 0x8 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR1_RESERVED_7_5 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR2_RESERVED_15_10 0x0 + * Load mode cycle time + * PSU_DDR_PHY_DTPR1_TMRD 0x8 - Self refresh exit delay - PSU_DDR_PHY_DTPR2_TXS 0x200 + * DRAM Timing Parameters Register 1 + * (OFFSET, MASK, VALUE) (0XFD080114, 0xFFFFFFFFU ,0x28200008U) + */ + PSU_Mask_Write(DDR_PHY_DTPR1_OFFSET, 0xFFFFFFFFU, 0x28200008U); +/*##################################################################### */ - DRAM Timing Parameters Register 2 - (OFFSET, MASK, VALUE) (0XFD080118, 0xFFFFFFFFU ,0x00080200U) - RegMask = (DDR_PHY_DTPR2_RESERVED_31_29_MASK | DDR_PHY_DTPR2_TRTW_MASK | DDR_PHY_DTPR2_RESERVED_27_25_MASK | DDR_PHY_DTPR2_TRTODT_MASK | DDR_PHY_DTPR2_RESERVED_23_20_MASK | DDR_PHY_DTPR2_TCKE_MASK | DDR_PHY_DTPR2_RESERVED_15_10_MASK | DDR_PHY_DTPR2_TXS_MASK | 0 ); + /* + * Register : DTPR2 @ 0XFD080118 - RegVal = ((0x00000000U << DDR_PHY_DTPR2_RESERVED_31_29_SHIFT - | 0x00000000U << DDR_PHY_DTPR2_TRTW_SHIFT - | 0x00000000U << DDR_PHY_DTPR2_RESERVED_27_25_SHIFT - | 0x00000000U << DDR_PHY_DTPR2_TRTODT_SHIFT - | 0x00000000U << DDR_PHY_DTPR2_RESERVED_23_20_SHIFT - | 0x00000008U << DDR_PHY_DTPR2_TCKE_SHIFT - | 0x00000000U << DDR_PHY_DTPR2_RESERVED_15_10_SHIFT - | 0x00000200U << DDR_PHY_DTPR2_TXS_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DTPR2_OFFSET ,0xFFFFFFFFU ,0x00080200U); - /*############################################################################################################################ */ + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR2_RESERVED_31_29 0x0 - /*Register : DTPR3 @ 0XFD08011C

+ * Read to Write command delay. Valid values are + * PSU_DDR_PHY_DTPR2_TRTW 0x0 - ODT turn-off delay extension - PSU_DDR_PHY_DTPR3_TOFDX 0x4 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR2_RESERVED_27_25 0x0 - Read to read and write to write command delay - PSU_DDR_PHY_DTPR3_TCCD 0x0 + * Read to ODT delay (DDR3 only) + * PSU_DDR_PHY_DTPR2_TRTODT 0x0 - DLL locking time - PSU_DDR_PHY_DTPR3_TDLLK 0x300 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR2_RESERVED_23_20 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR3_RESERVED_15_12 0x0 + * CKE minimum pulse width + * PSU_DDR_PHY_DTPR2_TCKE 0x7 - Maximum DQS output access time from CK/CK# (LPDDR2/3 only) - PSU_DDR_PHY_DTPR3_TDQSCKMAX 0x8 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR2_RESERVED_15_10 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR3_RESERVED_7_3 0x0 + * Self refresh exit delay + * PSU_DDR_PHY_DTPR2_TXS 0x300 - DQS output access time from CK/CK# (LPDDR2/3 only) - PSU_DDR_PHY_DTPR3_TDQSCK 0x0 + * DRAM Timing Parameters Register 2 + * (OFFSET, MASK, VALUE) (0XFD080118, 0xFFFFFFFFU ,0x00070300U) + */ + PSU_Mask_Write(DDR_PHY_DTPR2_OFFSET, 0xFFFFFFFFU, 0x00070300U); +/*##################################################################### */ - DRAM Timing Parameters Register 3 - (OFFSET, MASK, VALUE) (0XFD08011C, 0xFFFFFFFFU ,0x83000800U) - RegMask = (DDR_PHY_DTPR3_TOFDX_MASK | DDR_PHY_DTPR3_TCCD_MASK | DDR_PHY_DTPR3_TDLLK_MASK | DDR_PHY_DTPR3_RESERVED_15_12_MASK | DDR_PHY_DTPR3_TDQSCKMAX_MASK | DDR_PHY_DTPR3_RESERVED_7_3_MASK | DDR_PHY_DTPR3_TDQSCK_MASK | 0 ); + /* + * Register : DTPR3 @ 0XFD08011C - RegVal = ((0x00000004U << DDR_PHY_DTPR3_TOFDX_SHIFT - | 0x00000000U << DDR_PHY_DTPR3_TCCD_SHIFT - | 0x00000300U << DDR_PHY_DTPR3_TDLLK_SHIFT - | 0x00000000U << DDR_PHY_DTPR3_RESERVED_15_12_SHIFT - | 0x00000008U << DDR_PHY_DTPR3_TDQSCKMAX_SHIFT - | 0x00000000U << DDR_PHY_DTPR3_RESERVED_7_3_SHIFT - | 0x00000000U << DDR_PHY_DTPR3_TDQSCK_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DTPR3_OFFSET ,0xFFFFFFFFU ,0x83000800U); - /*############################################################################################################################ */ + * ODT turn-off delay extension + * PSU_DDR_PHY_DTPR3_TOFDX 0x4 - /*Register : DTPR4 @ 0XFD080120

+ * Read to read and write to write command delay + * PSU_DDR_PHY_DTPR3_TCCD 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR4_RESERVED_31_30 0x0 + * DLL locking time + * PSU_DDR_PHY_DTPR3_TDLLK 0x300 - ODT turn-on/turn-off delays (DDR2 only) - PSU_DDR_PHY_DTPR4_TAOND_TAOFD 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR3_RESERVED_15_12 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR4_RESERVED_27_26 0x0 + * Maximum DQS output access time from CK/CK# (LPDDR2/3 only) + * PSU_DDR_PHY_DTPR3_TDQSCKMAX 0x8 - Refresh-to-Refresh - PSU_DDR_PHY_DTPR4_TRFC 0x116 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR3_RESERVED_7_3 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR4_RESERVED_15_14 0x0 + * DQS output access time from CK/CK# (LPDDR2/3 only) + * PSU_DDR_PHY_DTPR3_TDQSCK 0x0 - Write leveling output delay - PSU_DDR_PHY_DTPR4_TWLO 0x2b + * DRAM Timing Parameters Register 3 + * (OFFSET, MASK, VALUE) (0XFD08011C, 0xFFFFFFFFU ,0x83000800U) + */ + PSU_Mask_Write(DDR_PHY_DTPR3_OFFSET, 0xFFFFFFFFU, 0x83000800U); +/*##################################################################### */ - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR4_RESERVED_7_5 0x0 + /* + * Register : DTPR4 @ 0XFD080120 - Power down exit delay - PSU_DDR_PHY_DTPR4_TXP 0x8 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR4_RESERVED_31_30 0x0 - DRAM Timing Parameters Register 4 - (OFFSET, MASK, VALUE) (0XFD080120, 0xFFFFFFFFU ,0x01162B08U) - RegMask = (DDR_PHY_DTPR4_RESERVED_31_30_MASK | DDR_PHY_DTPR4_TAOND_TAOFD_MASK | DDR_PHY_DTPR4_RESERVED_27_26_MASK | DDR_PHY_DTPR4_TRFC_MASK | DDR_PHY_DTPR4_RESERVED_15_14_MASK | DDR_PHY_DTPR4_TWLO_MASK | DDR_PHY_DTPR4_RESERVED_7_5_MASK | DDR_PHY_DTPR4_TXP_MASK | 0 ); + * ODT turn-on/turn-off delays (DDR2 only) + * PSU_DDR_PHY_DTPR4_TAOND_TAOFD 0x0 - RegVal = ((0x00000000U << DDR_PHY_DTPR4_RESERVED_31_30_SHIFT - | 0x00000000U << DDR_PHY_DTPR4_TAOND_TAOFD_SHIFT - | 0x00000000U << DDR_PHY_DTPR4_RESERVED_27_26_SHIFT - | 0x00000116U << DDR_PHY_DTPR4_TRFC_SHIFT - | 0x00000000U << DDR_PHY_DTPR4_RESERVED_15_14_SHIFT - | 0x0000002BU << DDR_PHY_DTPR4_TWLO_SHIFT - | 0x00000000U << DDR_PHY_DTPR4_RESERVED_7_5_SHIFT - | 0x00000008U << DDR_PHY_DTPR4_TXP_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DTPR4_OFFSET ,0xFFFFFFFFU ,0x01162B08U); - /*############################################################################################################################ */ + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR4_RESERVED_27_26 0x0 - /*Register : DTPR5 @ 0XFD080124

+ * Refresh-to-Refresh + * PSU_DDR_PHY_DTPR4_TRFC 0x116 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR5_RESERVED_31_24 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR4_RESERVED_15_14 0x0 - Activate to activate command delay (same bank) - PSU_DDR_PHY_DTPR5_TRC 0x32 + * Write leveling output delay + * PSU_DDR_PHY_DTPR4_TWLO 0x2b - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR5_RESERVED_15 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR4_RESERVED_7_5 0x0 - Activate to read or write delay - PSU_DDR_PHY_DTPR5_TRCD 0xf + * Power down exit delay + * PSU_DDR_PHY_DTPR4_TXP 0x7 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR5_RESERVED_7_5 0x0 + * DRAM Timing Parameters Register 4 + * (OFFSET, MASK, VALUE) (0XFD080120, 0xFFFFFFFFU ,0x01162B07U) + */ + PSU_Mask_Write(DDR_PHY_DTPR4_OFFSET, 0xFFFFFFFFU, 0x01162B07U); +/*##################################################################### */ - Internal write to read command delay - PSU_DDR_PHY_DTPR5_TWTR 0x9 + /* + * Register : DTPR5 @ 0XFD080124 - DRAM Timing Parameters Register 5 - (OFFSET, MASK, VALUE) (0XFD080124, 0xFFFFFFFFU ,0x00320F09U) - RegMask = (DDR_PHY_DTPR5_RESERVED_31_24_MASK | DDR_PHY_DTPR5_TRC_MASK | DDR_PHY_DTPR5_RESERVED_15_MASK | DDR_PHY_DTPR5_TRCD_MASK | DDR_PHY_DTPR5_RESERVED_7_5_MASK | DDR_PHY_DTPR5_TWTR_MASK | 0 ); + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR5_RESERVED_31_24 0x0 - RegVal = ((0x00000000U << DDR_PHY_DTPR5_RESERVED_31_24_SHIFT - | 0x00000032U << DDR_PHY_DTPR5_TRC_SHIFT - | 0x00000000U << DDR_PHY_DTPR5_RESERVED_15_SHIFT - | 0x0000000FU << DDR_PHY_DTPR5_TRCD_SHIFT - | 0x00000000U << DDR_PHY_DTPR5_RESERVED_7_5_SHIFT - | 0x00000009U << DDR_PHY_DTPR5_TWTR_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DTPR5_OFFSET ,0xFFFFFFFFU ,0x00320F09U); - /*############################################################################################################################ */ + * Activate to activate command delay (same bank) + * PSU_DDR_PHY_DTPR5_TRC 0x33 - /*Register : DTPR6 @ 0XFD080128

+ * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR5_RESERVED_15 0x0 - PUB Write Latency Enable - PSU_DDR_PHY_DTPR6_PUBWLEN 0x0 + * Activate to read or write delay + * PSU_DDR_PHY_DTPR5_TRCD 0xf - PUB Read Latency Enable - PSU_DDR_PHY_DTPR6_PUBRLEN 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR5_RESERVED_7_5 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR6_RESERVED_29_14 0x0 + * Internal write to read command delay + * PSU_DDR_PHY_DTPR5_TWTR 0x8 - Write Latency - PSU_DDR_PHY_DTPR6_PUBWL 0xe + * DRAM Timing Parameters Register 5 + * (OFFSET, MASK, VALUE) (0XFD080124, 0xFFFFFFFFU ,0x00330F08U) + */ + PSU_Mask_Write(DDR_PHY_DTPR5_OFFSET, 0xFFFFFFFFU, 0x00330F08U); +/*##################################################################### */ - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTPR6_RESERVED_7_6 0x0 + /* + * Register : DTPR6 @ 0XFD080128 - Read Latency - PSU_DDR_PHY_DTPR6_PUBRL 0xf + * PUB Write Latency Enable + * PSU_DDR_PHY_DTPR6_PUBWLEN 0x0 - DRAM Timing Parameters Register 6 - (OFFSET, MASK, VALUE) (0XFD080128, 0xFFFFFFFFU ,0x00000E0FU) - RegMask = (DDR_PHY_DTPR6_PUBWLEN_MASK | DDR_PHY_DTPR6_PUBRLEN_MASK | DDR_PHY_DTPR6_RESERVED_29_14_MASK | DDR_PHY_DTPR6_PUBWL_MASK | DDR_PHY_DTPR6_RESERVED_7_6_MASK | DDR_PHY_DTPR6_PUBRL_MASK | 0 ); + * PUB Read Latency Enable + * PSU_DDR_PHY_DTPR6_PUBRLEN 0x0 - RegVal = ((0x00000000U << DDR_PHY_DTPR6_PUBWLEN_SHIFT - | 0x00000000U << DDR_PHY_DTPR6_PUBRLEN_SHIFT - | 0x00000000U << DDR_PHY_DTPR6_RESERVED_29_14_SHIFT - | 0x0000000EU << DDR_PHY_DTPR6_PUBWL_SHIFT - | 0x00000000U << DDR_PHY_DTPR6_RESERVED_7_6_SHIFT - | 0x0000000FU << DDR_PHY_DTPR6_PUBRL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DTPR6_OFFSET ,0xFFFFFFFFU ,0x00000E0FU); - /*############################################################################################################################ */ + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR6_RESERVED_29_14 0x0 - /*Register : RDIMMGCR0 @ 0XFD080140

+ * Write Latency + * PSU_DDR_PHY_DTPR6_PUBWL 0xe - Reserved. Return zeroes on reads. - PSU_DDR_PHY_RDIMMGCR0_RESERVED_31 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTPR6_RESERVED_7_6 0x0 - RDMIMM Quad CS Enable - PSU_DDR_PHY_RDIMMGCR0_QCSEN 0x0 + * Read Latency + * PSU_DDR_PHY_DTPR6_PUBRL 0xf - Reserved. Return zeroes on reads. - PSU_DDR_PHY_RDIMMGCR0_RESERVED_29_28 0x0 + * DRAM Timing Parameters Register 6 + * (OFFSET, MASK, VALUE) (0XFD080128, 0xFFFFFFFFU ,0x00000E0FU) + */ + PSU_Mask_Write(DDR_PHY_DTPR6_OFFSET, 0xFFFFFFFFU, 0x00000E0FU); +/*##################################################################### */ - RDIMM Outputs I/O Mode - PSU_DDR_PHY_RDIMMGCR0_RDIMMIOM 0x1 + /* + * Register : RDIMMGCR0 @ 0XFD080140 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_RDIMMGCR0_RESERVED_26_24 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_RDIMMGCR0_RESERVED_31 0x0 - ERROUT# Output Enable - PSU_DDR_PHY_RDIMMGCR0_ERROUTOE 0x0 + * RDMIMM Quad CS Enable + * PSU_DDR_PHY_RDIMMGCR0_QCSEN 0x0 - ERROUT# I/O Mode - PSU_DDR_PHY_RDIMMGCR0_ERROUTIOM 0x1 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_RDIMMGCR0_RESERVED_29_28 0x0 - ERROUT# Power Down Receiver - PSU_DDR_PHY_RDIMMGCR0_ERROUTPDR 0x0 + * RDIMM Outputs I/O Mode + * PSU_DDR_PHY_RDIMMGCR0_RDIMMIOM 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_RDIMMGCR0_RESERVED_20 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_RDIMMGCR0_RESERVED_26_24 0x0 - ERROUT# On-Die Termination - PSU_DDR_PHY_RDIMMGCR0_ERROUTODT 0x0 + * ERROUT# Output Enable + * PSU_DDR_PHY_RDIMMGCR0_ERROUTOE 0x0 - Load Reduced DIMM - PSU_DDR_PHY_RDIMMGCR0_LRDIMM 0x0 + * ERROUT# I/O Mode + * PSU_DDR_PHY_RDIMMGCR0_ERROUTIOM 0x1 - PAR_IN I/O Mode - PSU_DDR_PHY_RDIMMGCR0_PARINIOM 0x0 + * ERROUT# Power Down Receiver + * PSU_DDR_PHY_RDIMMGCR0_ERROUTPDR 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_RDIMMGCR0_RESERVED_16_8 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_RDIMMGCR0_RESERVED_20 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD 0x0 + * ERROUT# On-Die Termination + * PSU_DDR_PHY_RDIMMGCR0_ERROUTODT 0x0 - Rank Mirror Enable. - PSU_DDR_PHY_RDIMMGCR0_RNKMRREN 0x2 + * Load Reduced DIMM + * PSU_DDR_PHY_RDIMMGCR0_LRDIMM 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_RDIMMGCR0_RESERVED_3 0x0 + * PAR_IN I/O Mode + * PSU_DDR_PHY_RDIMMGCR0_PARINIOM 0x0 - Stop on Parity Error - PSU_DDR_PHY_RDIMMGCR0_SOPERR 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_RDIMMGCR0_RESERVED_16_8 0x0 - Parity Error No Registering - PSU_DDR_PHY_RDIMMGCR0_ERRNOREG 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD 0x0 - Registered DIMM - PSU_DDR_PHY_RDIMMGCR0_RDIMM 0x0 + * Rank Mirror Enable. + * PSU_DDR_PHY_RDIMMGCR0_RNKMRREN 0x2 - RDIMM General Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD080140, 0xFFFFFFFFU ,0x08400020U) - RegMask = (DDR_PHY_RDIMMGCR0_RESERVED_31_MASK | DDR_PHY_RDIMMGCR0_QCSEN_MASK | DDR_PHY_RDIMMGCR0_RESERVED_29_28_MASK | DDR_PHY_RDIMMGCR0_RDIMMIOM_MASK | DDR_PHY_RDIMMGCR0_RESERVED_26_24_MASK | DDR_PHY_RDIMMGCR0_ERROUTOE_MASK | DDR_PHY_RDIMMGCR0_ERROUTIOM_MASK | DDR_PHY_RDIMMGCR0_ERROUTPDR_MASK | DDR_PHY_RDIMMGCR0_RESERVED_20_MASK | DDR_PHY_RDIMMGCR0_ERROUTODT_MASK | DDR_PHY_RDIMMGCR0_LRDIMM_MASK | DDR_PHY_RDIMMGCR0_PARINIOM_MASK | DDR_PHY_RDIMMGCR0_RESERVED_16_8_MASK | DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_MASK | DDR_PHY_RDIMMGCR0_RNKMRREN_MASK | DDR_PHY_RDIMMGCR0_RESERVED_3_MASK | DDR_PHY_RDIMMGCR0_SOPERR_MASK | DDR_PHY_RDIMMGCR0_ERRNOREG_MASK | DDR_PHY_RDIMMGCR0_RDIMM_MASK | 0 ); + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_RDIMMGCR0_RESERVED_3 0x0 - RegVal = ((0x00000000U << DDR_PHY_RDIMMGCR0_RESERVED_31_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR0_QCSEN_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR0_RESERVED_29_28_SHIFT - | 0x00000001U << DDR_PHY_RDIMMGCR0_RDIMMIOM_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR0_RESERVED_26_24_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR0_ERROUTOE_SHIFT - | 0x00000001U << DDR_PHY_RDIMMGCR0_ERROUTIOM_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR0_ERROUTPDR_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR0_RESERVED_20_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR0_ERROUTODT_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR0_LRDIMM_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR0_PARINIOM_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR0_RESERVED_16_8_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_SHIFT - | 0x00000002U << DDR_PHY_RDIMMGCR0_RNKMRREN_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR0_RESERVED_3_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR0_SOPERR_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR0_ERRNOREG_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR0_RDIMM_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_RDIMMGCR0_OFFSET ,0xFFFFFFFFU ,0x08400020U); - /*############################################################################################################################ */ + * Stop on Parity Error + * PSU_DDR_PHY_RDIMMGCR0_SOPERR 0x0 - /*Register : RDIMMGCR1 @ 0XFD080144

+ * Parity Error No Registering + * PSU_DDR_PHY_RDIMMGCR0_ERRNOREG 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_RDIMMGCR1_RESERVED_31_29 0x0 + * Registered DIMM + * PSU_DDR_PHY_RDIMMGCR0_RDIMM 0x0 - Address [17] B-side Inversion Disable - PSU_DDR_PHY_RDIMMGCR1_A17BID 0x0 + * RDIMM General Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD080140, 0xFFFFFFFFU ,0x08400020U) + */ + PSU_Mask_Write(DDR_PHY_RDIMMGCR0_OFFSET, 0xFFFFFFFFU, 0x08400020U); +/*##################################################################### */ - Reserved. Return zeroes on reads. - PSU_DDR_PHY_RDIMMGCR1_RESERVED_27 0x0 + /* + * Register : RDIMMGCR1 @ 0XFD080144 - Command word to command word programming delay - PSU_DDR_PHY_RDIMMGCR1_TBCMRD_L2 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_RDIMMGCR1_RESERVED_31_29 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_RDIMMGCR1_RESERVED_23 0x0 + * Address [17] B-side Inversion Disable + * PSU_DDR_PHY_RDIMMGCR1_A17BID 0x0 - Command word to command word programming delay - PSU_DDR_PHY_RDIMMGCR1_TBCMRD_L 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_RDIMMGCR1_RESERVED_27 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_RDIMMGCR1_RESERVED_19 0x0 + * Command word to command word programming delay + * PSU_DDR_PHY_RDIMMGCR1_TBCMRD_L2 0x0 - Command word to command word programming delay - PSU_DDR_PHY_RDIMMGCR1_TBCMRD 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_RDIMMGCR1_RESERVED_23 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_RDIMMGCR1_RESERVED_15_14 0x0 + * Command word to command word programming delay + * PSU_DDR_PHY_RDIMMGCR1_TBCMRD_L 0x0 - Stabilization time - PSU_DDR_PHY_RDIMMGCR1_TBCSTAB 0xc80 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_RDIMMGCR1_RESERVED_19 0x0 - RDIMM General Configuration Register 1 - (OFFSET, MASK, VALUE) (0XFD080144, 0xFFFFFFFFU ,0x00000C80U) - RegMask = (DDR_PHY_RDIMMGCR1_RESERVED_31_29_MASK | DDR_PHY_RDIMMGCR1_A17BID_MASK | DDR_PHY_RDIMMGCR1_RESERVED_27_MASK | DDR_PHY_RDIMMGCR1_TBCMRD_L2_MASK | DDR_PHY_RDIMMGCR1_RESERVED_23_MASK | DDR_PHY_RDIMMGCR1_TBCMRD_L_MASK | DDR_PHY_RDIMMGCR1_RESERVED_19_MASK | DDR_PHY_RDIMMGCR1_TBCMRD_MASK | DDR_PHY_RDIMMGCR1_RESERVED_15_14_MASK | DDR_PHY_RDIMMGCR1_TBCSTAB_MASK | 0 ); - - RegVal = ((0x00000000U << DDR_PHY_RDIMMGCR1_RESERVED_31_29_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR1_A17BID_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR1_RESERVED_27_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR1_TBCMRD_L2_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR1_RESERVED_23_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR1_TBCMRD_L_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR1_RESERVED_19_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR1_TBCMRD_SHIFT - | 0x00000000U << DDR_PHY_RDIMMGCR1_RESERVED_15_14_SHIFT - | 0x00000C80U << DDR_PHY_RDIMMGCR1_TBCSTAB_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_RDIMMGCR1_OFFSET ,0xFFFFFFFFU ,0x00000C80U); - /*############################################################################################################################ */ - - /*Register : RDIMMCR0 @ 0XFD080150

+ * Command word to command word programming delay + * PSU_DDR_PHY_RDIMMGCR1_TBCMRD 0x0 - DDR4/DDR3 Control Word 7 - PSU_DDR_PHY_RDIMMCR0_RC7 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_RDIMMGCR1_RESERVED_15_14 0x0 - DDR4 Control Word 6 (Comman space Control Word) / DDR3 Reserved - PSU_DDR_PHY_RDIMMCR0_RC6 0x0 - - DDR4/DDR3 Control Word 5 (CK Driver Characteristics Control Word) - PSU_DDR_PHY_RDIMMCR0_RC5 0x0 - - DDR4 Control Word 4 (ODT and CKE Signals Driver Characteristics Control Word) / DDR3 Control Word 4 (Control Signals Driver C - aracteristics Control Word) - PSU_DDR_PHY_RDIMMCR0_RC4 0x0 - - DDR4 Control Word 3 (CA and CS Signals Driver Characteristics Control Word) / DDR3 Control Word 3 (Command/Address Signals Dr - ver Characteristrics Control Word) - PSU_DDR_PHY_RDIMMCR0_RC3 0x0 - - DDR4 Control Word 2 (Timing and IBT Control Word) / DDR3 Control Word 2 (Timing Control Word) - PSU_DDR_PHY_RDIMMCR0_RC2 0x0 - - DDR4/DDR3 Control Word 1 (Clock Driver Enable Control Word) - PSU_DDR_PHY_RDIMMCR0_RC1 0x0 - - DDR4/DDR3 Control Word 0 (Global Features Control Word) - PSU_DDR_PHY_RDIMMCR0_RC0 0x0 - - RDIMM Control Register 0 - (OFFSET, MASK, VALUE) (0XFD080150, 0xFFFFFFFFU ,0x00000000U) - RegMask = (DDR_PHY_RDIMMCR0_RC7_MASK | DDR_PHY_RDIMMCR0_RC6_MASK | DDR_PHY_RDIMMCR0_RC5_MASK | DDR_PHY_RDIMMCR0_RC4_MASK | DDR_PHY_RDIMMCR0_RC3_MASK | DDR_PHY_RDIMMCR0_RC2_MASK | DDR_PHY_RDIMMCR0_RC1_MASK | DDR_PHY_RDIMMCR0_RC0_MASK | 0 ); - - RegVal = ((0x00000000U << DDR_PHY_RDIMMCR0_RC7_SHIFT - | 0x00000000U << DDR_PHY_RDIMMCR0_RC6_SHIFT - | 0x00000000U << DDR_PHY_RDIMMCR0_RC5_SHIFT - | 0x00000000U << DDR_PHY_RDIMMCR0_RC4_SHIFT - | 0x00000000U << DDR_PHY_RDIMMCR0_RC3_SHIFT - | 0x00000000U << DDR_PHY_RDIMMCR0_RC2_SHIFT - | 0x00000000U << DDR_PHY_RDIMMCR0_RC1_SHIFT - | 0x00000000U << DDR_PHY_RDIMMCR0_RC0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_RDIMMCR0_OFFSET ,0xFFFFFFFFU ,0x00000000U); - /*############################################################################################################################ */ + * Stabilization time + * PSU_DDR_PHY_RDIMMGCR1_TBCSTAB 0xc80 - /*Register : RDIMMCR1 @ 0XFD080154

+ * RDIMM General Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD080144, 0xFFFFFFFFU ,0x00000C80U) + */ + PSU_Mask_Write(DDR_PHY_RDIMMGCR1_OFFSET, 0xFFFFFFFFU, 0x00000C80U); +/*##################################################################### */ - Control Word 15 - PSU_DDR_PHY_RDIMMCR1_RC15 0x0 + /* + * Register : RDIMMCR0 @ 0XFD080150 - DDR4 Control Word 14 (Parity Control Word) / DDR3 Reserved - PSU_DDR_PHY_RDIMMCR1_RC14 0x0 + * DDR4/DDR3 Control Word 7 + * PSU_DDR_PHY_RDIMMCR0_RC7 0x0 - DDR4 Control Word 13 (DIMM Configuration Control Word) / DDR3 Reserved - PSU_DDR_PHY_RDIMMCR1_RC13 0x0 + * DDR4 Control Word 6 (Comman space Control Word) / DDR3 Reserved + * PSU_DDR_PHY_RDIMMCR0_RC6 0x0 - DDR4 Control Word 12 (Training Control Word) / DDR3 Reserved - PSU_DDR_PHY_RDIMMCR1_RC12 0x0 + * DDR4/DDR3 Control Word 5 (CK Driver Characteristics Control Word) + * PSU_DDR_PHY_RDIMMCR0_RC5 0x0 - DDR4 Control Word 11 (Operating Voltage VDD and VREFCA Source Control Word) / DDR3 Control Word 11 (Operation Voltage VDD Con - rol Word) - PSU_DDR_PHY_RDIMMCR1_RC11 0x0 + * DDR4 Control Word 4 (ODT and CKE Signals Driver Characteristics Control + * Word) / DDR3 Control Word 4 (Control Signals Driver Characteristics Cont + * rol Word) + * PSU_DDR_PHY_RDIMMCR0_RC4 0x0 - DDR4/DDR3 Control Word 10 (RDIMM Operating Speed Control Word) - PSU_DDR_PHY_RDIMMCR1_RC10 0x2 + * DDR4 Control Word 3 (CA and CS Signals Driver Characteristics Control Wo + * rd) / DDR3 Control Word 3 (Command/Address Signals Driver Characteristri + * cs Control Word) + * PSU_DDR_PHY_RDIMMCR0_RC3 0x0 - DDR4/DDR3 Control Word 9 (Power Saving Settings Control Word) - PSU_DDR_PHY_RDIMMCR1_RC9 0x0 + * DDR4 Control Word 2 (Timing and IBT Control Word) / DDR3 Control Word 2 + * (Timing Control Word) + * PSU_DDR_PHY_RDIMMCR0_RC2 0x0 - DDR4 Control Word 8 (Input/Output Configuration Control Word) / DDR3 Control Word 8 (Additional Input Bus Termination Setting - Control Word) - PSU_DDR_PHY_RDIMMCR1_RC8 0x0 + * DDR4/DDR3 Control Word 1 (Clock Driver Enable Control Word) + * PSU_DDR_PHY_RDIMMCR0_RC1 0x0 - RDIMM Control Register 1 - (OFFSET, MASK, VALUE) (0XFD080154, 0xFFFFFFFFU ,0x00000200U) - RegMask = (DDR_PHY_RDIMMCR1_RC15_MASK | DDR_PHY_RDIMMCR1_RC14_MASK | DDR_PHY_RDIMMCR1_RC13_MASK | DDR_PHY_RDIMMCR1_RC12_MASK | DDR_PHY_RDIMMCR1_RC11_MASK | DDR_PHY_RDIMMCR1_RC10_MASK | DDR_PHY_RDIMMCR1_RC9_MASK | DDR_PHY_RDIMMCR1_RC8_MASK | 0 ); + * DDR4/DDR3 Control Word 0 (Global Features Control Word) + * PSU_DDR_PHY_RDIMMCR0_RC0 0x0 - RegVal = ((0x00000000U << DDR_PHY_RDIMMCR1_RC15_SHIFT - | 0x00000000U << DDR_PHY_RDIMMCR1_RC14_SHIFT - | 0x00000000U << DDR_PHY_RDIMMCR1_RC13_SHIFT - | 0x00000000U << DDR_PHY_RDIMMCR1_RC12_SHIFT - | 0x00000000U << DDR_PHY_RDIMMCR1_RC11_SHIFT - | 0x00000002U << DDR_PHY_RDIMMCR1_RC10_SHIFT - | 0x00000000U << DDR_PHY_RDIMMCR1_RC9_SHIFT - | 0x00000000U << DDR_PHY_RDIMMCR1_RC8_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_RDIMMCR1_OFFSET ,0xFFFFFFFFU ,0x00000200U); - /*############################################################################################################################ */ + * RDIMM Control Register 0 + * (OFFSET, MASK, VALUE) (0XFD080150, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDR_PHY_RDIMMCR0_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ - /*Register : MR0 @ 0XFD080180

+ /* + * Register : RDIMMCR1 @ 0XFD080154 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_MR0_RESERVED_31_8 0x8 + * Control Word 15 + * PSU_DDR_PHY_RDIMMCR1_RC15 0x0 - CA Terminating Rank - PSU_DDR_PHY_MR0_CATR 0x0 + * DDR4 Control Word 14 (Parity Control Word) / DDR3 Reserved + * PSU_DDR_PHY_RDIMMCR1_RC14 0x0 - Reserved. These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0. - PSU_DDR_PHY_MR0_RSVD_6_5 0x1 + * DDR4 Control Word 13 (DIMM Configuration Control Word) / DDR3 Reserved + * PSU_DDR_PHY_RDIMMCR1_RC13 0x0 - Built-in Self-Test for RZQ - PSU_DDR_PHY_MR0_RZQI 0x2 + * DDR4 Control Word 12 (Training Control Word) / DDR3 Reserved + * PSU_DDR_PHY_RDIMMCR1_RC12 0x0 - Reserved. These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0. - PSU_DDR_PHY_MR0_RSVD_2_0 0x0 + * DDR4 Control Word 11 (Operating Voltage VDD and VREFCA Source Control Wo + * rd) / DDR3 Control Word 11 (Operation Voltage VDD Control Word) + * PSU_DDR_PHY_RDIMMCR1_RC11 0x0 - LPDDR4 Mode Register 0 - (OFFSET, MASK, VALUE) (0XFD080180, 0xFFFFFFFFU ,0x00000830U) - RegMask = (DDR_PHY_MR0_RESERVED_31_8_MASK | DDR_PHY_MR0_CATR_MASK | DDR_PHY_MR0_RSVD_6_5_MASK | DDR_PHY_MR0_RZQI_MASK | DDR_PHY_MR0_RSVD_2_0_MASK | 0 ); + * DDR4/DDR3 Control Word 10 (RDIMM Operating Speed Control Word) + * PSU_DDR_PHY_RDIMMCR1_RC10 0x2 - RegVal = ((0x00000008U << DDR_PHY_MR0_RESERVED_31_8_SHIFT - | 0x00000000U << DDR_PHY_MR0_CATR_SHIFT - | 0x00000001U << DDR_PHY_MR0_RSVD_6_5_SHIFT - | 0x00000002U << DDR_PHY_MR0_RZQI_SHIFT - | 0x00000000U << DDR_PHY_MR0_RSVD_2_0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_MR0_OFFSET ,0xFFFFFFFFU ,0x00000830U); - /*############################################################################################################################ */ + * DDR4/DDR3 Control Word 9 (Power Saving Settings Control Word) + * PSU_DDR_PHY_RDIMMCR1_RC9 0x0 - /*Register : MR1 @ 0XFD080184

+ * DDR4 Control Word 8 (Input/Output Configuration Control Word) / DDR3 Con + * trol Word 8 (Additional Input Bus Termination Setting Control Word) + * PSU_DDR_PHY_RDIMMCR1_RC8 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_MR1_RESERVED_31_8 0x3 + * RDIMM Control Register 1 + * (OFFSET, MASK, VALUE) (0XFD080154, 0xFFFFFFFFU ,0x00000200U) + */ + PSU_Mask_Write(DDR_PHY_RDIMMCR1_OFFSET, 0xFFFFFFFFU, 0x00000200U); +/*##################################################################### */ - Read Postamble Length - PSU_DDR_PHY_MR1_RDPST 0x0 + /* + * Register : MR0 @ 0XFD080180 - Write-recovery for auto-precharge command - PSU_DDR_PHY_MR1_NWR 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_MR0_RESERVED_31_8 0x6 - Read Preamble Length - PSU_DDR_PHY_MR1_RDPRE 0x0 + * CA Terminating Rank + * PSU_DDR_PHY_MR0_CATR 0x0 - Write Preamble Length - PSU_DDR_PHY_MR1_WRPRE 0x0 + * Reserved. These are JEDEC reserved bits and are recommended by JEDEC to + * be programmed to 0x0. + * PSU_DDR_PHY_MR0_RSVD_6_5 0x1 - Burst Length - PSU_DDR_PHY_MR1_BL 0x1 + * Built-in Self-Test for RZQ + * PSU_DDR_PHY_MR0_RZQI 0x2 - LPDDR4 Mode Register 1 - (OFFSET, MASK, VALUE) (0XFD080184, 0xFFFFFFFFU ,0x00000301U) - RegMask = (DDR_PHY_MR1_RESERVED_31_8_MASK | DDR_PHY_MR1_RDPST_MASK | DDR_PHY_MR1_NWR_MASK | DDR_PHY_MR1_RDPRE_MASK | DDR_PHY_MR1_WRPRE_MASK | DDR_PHY_MR1_BL_MASK | 0 ); + * Reserved. These are JEDEC reserved bits and are recommended by JEDEC to + * be programmed to 0x0. + * PSU_DDR_PHY_MR0_RSVD_2_0 0x0 - RegVal = ((0x00000003U << DDR_PHY_MR1_RESERVED_31_8_SHIFT - | 0x00000000U << DDR_PHY_MR1_RDPST_SHIFT - | 0x00000000U << DDR_PHY_MR1_NWR_SHIFT - | 0x00000000U << DDR_PHY_MR1_RDPRE_SHIFT - | 0x00000000U << DDR_PHY_MR1_WRPRE_SHIFT - | 0x00000001U << DDR_PHY_MR1_BL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_MR1_OFFSET ,0xFFFFFFFFU ,0x00000301U); - /*############################################################################################################################ */ + * LPDDR4 Mode Register 0 + * (OFFSET, MASK, VALUE) (0XFD080180, 0xFFFFFFFFU ,0x00000630U) + */ + PSU_Mask_Write(DDR_PHY_MR0_OFFSET, 0xFFFFFFFFU, 0x00000630U); +/*##################################################################### */ - /*Register : MR2 @ 0XFD080188

+ /* + * Register : MR1 @ 0XFD080184 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_MR2_RESERVED_31_8 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_MR1_RESERVED_31_8 0x3 - Write Leveling - PSU_DDR_PHY_MR2_WRL 0x0 + * Read Postamble Length + * PSU_DDR_PHY_MR1_RDPST 0x0 - Write Latency Set - PSU_DDR_PHY_MR2_WLS 0x0 + * Write-recovery for auto-precharge command + * PSU_DDR_PHY_MR1_NWR 0x0 - Write Latency - PSU_DDR_PHY_MR2_WL 0x4 + * Read Preamble Length + * PSU_DDR_PHY_MR1_RDPRE 0x0 - Read Latency - PSU_DDR_PHY_MR2_RL 0x0 + * Write Preamble Length + * PSU_DDR_PHY_MR1_WRPRE 0x0 - LPDDR4 Mode Register 2 - (OFFSET, MASK, VALUE) (0XFD080188, 0xFFFFFFFFU ,0x00000020U) - RegMask = (DDR_PHY_MR2_RESERVED_31_8_MASK | DDR_PHY_MR2_WRL_MASK | DDR_PHY_MR2_WLS_MASK | DDR_PHY_MR2_WL_MASK | DDR_PHY_MR2_RL_MASK | 0 ); + * Burst Length + * PSU_DDR_PHY_MR1_BL 0x1 - RegVal = ((0x00000000U << DDR_PHY_MR2_RESERVED_31_8_SHIFT - | 0x00000000U << DDR_PHY_MR2_WRL_SHIFT - | 0x00000000U << DDR_PHY_MR2_WLS_SHIFT - | 0x00000004U << DDR_PHY_MR2_WL_SHIFT - | 0x00000000U << DDR_PHY_MR2_RL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_MR2_OFFSET ,0xFFFFFFFFU ,0x00000020U); - /*############################################################################################################################ */ + * LPDDR4 Mode Register 1 + * (OFFSET, MASK, VALUE) (0XFD080184, 0xFFFFFFFFU ,0x00000301U) + */ + PSU_Mask_Write(DDR_PHY_MR1_OFFSET, 0xFFFFFFFFU, 0x00000301U); +/*##################################################################### */ - /*Register : MR3 @ 0XFD08018C

+ /* + * Register : MR2 @ 0XFD080188 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_MR3_RESERVED_31_8 0x2 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_MR2_RESERVED_31_8 0x0 - DBI-Write Enable - PSU_DDR_PHY_MR3_DBIWR 0x0 + * Write Leveling + * PSU_DDR_PHY_MR2_WRL 0x0 - DBI-Read Enable - PSU_DDR_PHY_MR3_DBIRD 0x0 + * Write Latency Set + * PSU_DDR_PHY_MR2_WLS 0x0 - Pull-down Drive Strength - PSU_DDR_PHY_MR3_PDDS 0x0 + * Write Latency + * PSU_DDR_PHY_MR2_WL 0x4 - These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0. - PSU_DDR_PHY_MR3_RSVD 0x0 + * Read Latency + * PSU_DDR_PHY_MR2_RL 0x0 - Write Postamble Length - PSU_DDR_PHY_MR3_WRPST 0x0 + * LPDDR4 Mode Register 2 + * (OFFSET, MASK, VALUE) (0XFD080188, 0xFFFFFFFFU ,0x00000020U) + */ + PSU_Mask_Write(DDR_PHY_MR2_OFFSET, 0xFFFFFFFFU, 0x00000020U); +/*##################################################################### */ - Pull-up Calibration Point - PSU_DDR_PHY_MR3_PUCAL 0x0 + /* + * Register : MR3 @ 0XFD08018C - LPDDR4 Mode Register 3 - (OFFSET, MASK, VALUE) (0XFD08018C, 0xFFFFFFFFU ,0x00000200U) - RegMask = (DDR_PHY_MR3_RESERVED_31_8_MASK | DDR_PHY_MR3_DBIWR_MASK | DDR_PHY_MR3_DBIRD_MASK | DDR_PHY_MR3_PDDS_MASK | DDR_PHY_MR3_RSVD_MASK | DDR_PHY_MR3_WRPST_MASK | DDR_PHY_MR3_PUCAL_MASK | 0 ); + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_MR3_RESERVED_31_8 0x2 - RegVal = ((0x00000002U << DDR_PHY_MR3_RESERVED_31_8_SHIFT - | 0x00000000U << DDR_PHY_MR3_DBIWR_SHIFT - | 0x00000000U << DDR_PHY_MR3_DBIRD_SHIFT - | 0x00000000U << DDR_PHY_MR3_PDDS_SHIFT - | 0x00000000U << DDR_PHY_MR3_RSVD_SHIFT - | 0x00000000U << DDR_PHY_MR3_WRPST_SHIFT - | 0x00000000U << DDR_PHY_MR3_PUCAL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_MR3_OFFSET ,0xFFFFFFFFU ,0x00000200U); - /*############################################################################################################################ */ + * DBI-Write Enable + * PSU_DDR_PHY_MR3_DBIWR 0x0 - /*Register : MR4 @ 0XFD080190

+ * DBI-Read Enable + * PSU_DDR_PHY_MR3_DBIRD 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_MR4_RESERVED_31_16 0x0 + * Pull-down Drive Strength + * PSU_DDR_PHY_MR3_PDDS 0x0 - These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0. - PSU_DDR_PHY_MR4_RSVD_15_13 0x0 + * These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. + * PSU_DDR_PHY_MR3_RSVD 0x0 - Write Preamble - PSU_DDR_PHY_MR4_WRP 0x0 + * Write Postamble Length + * PSU_DDR_PHY_MR3_WRPST 0x0 - Read Preamble - PSU_DDR_PHY_MR4_RDP 0x0 + * Pull-up Calibration Point + * PSU_DDR_PHY_MR3_PUCAL 0x0 - Read Preamble Training Mode - PSU_DDR_PHY_MR4_RPTM 0x0 + * LPDDR4 Mode Register 3 + * (OFFSET, MASK, VALUE) (0XFD08018C, 0xFFFFFFFFU ,0x00000200U) + */ + PSU_Mask_Write(DDR_PHY_MR3_OFFSET, 0xFFFFFFFFU, 0x00000200U); +/*##################################################################### */ - Self Refresh Abort - PSU_DDR_PHY_MR4_SRA 0x0 + /* + * Register : MR4 @ 0XFD080190 - CS to Command Latency Mode - PSU_DDR_PHY_MR4_CS2CMDL 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_MR4_RESERVED_31_16 0x0 - These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0. - PSU_DDR_PHY_MR4_RSVD1 0x0 + * These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. + * PSU_DDR_PHY_MR4_RSVD_15_13 0x0 - Internal VREF Monitor - PSU_DDR_PHY_MR4_IVM 0x0 + * Write Preamble + * PSU_DDR_PHY_MR4_WRP 0x0 - Temperature Controlled Refresh Mode - PSU_DDR_PHY_MR4_TCRM 0x0 + * Read Preamble + * PSU_DDR_PHY_MR4_RDP 0x0 - Temperature Controlled Refresh Range - PSU_DDR_PHY_MR4_TCRR 0x0 + * Read Preamble Training Mode + * PSU_DDR_PHY_MR4_RPTM 0x0 - Maximum Power Down Mode - PSU_DDR_PHY_MR4_MPDM 0x0 + * Self Refresh Abort + * PSU_DDR_PHY_MR4_SRA 0x0 - This is a JEDEC reserved bit and is recommended by JEDEC to be programmed to 0x0. - PSU_DDR_PHY_MR4_RSVD_0 0x0 + * CS to Command Latency Mode + * PSU_DDR_PHY_MR4_CS2CMDL 0x0 - DDR4 Mode Register 4 - (OFFSET, MASK, VALUE) (0XFD080190, 0xFFFFFFFFU ,0x00000000U) - RegMask = (DDR_PHY_MR4_RESERVED_31_16_MASK | DDR_PHY_MR4_RSVD_15_13_MASK | DDR_PHY_MR4_WRP_MASK | DDR_PHY_MR4_RDP_MASK | DDR_PHY_MR4_RPTM_MASK | DDR_PHY_MR4_SRA_MASK | DDR_PHY_MR4_CS2CMDL_MASK | DDR_PHY_MR4_RSVD1_MASK | DDR_PHY_MR4_IVM_MASK | DDR_PHY_MR4_TCRM_MASK | DDR_PHY_MR4_TCRR_MASK | DDR_PHY_MR4_MPDM_MASK | DDR_PHY_MR4_RSVD_0_MASK | 0 ); + * These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. + * PSU_DDR_PHY_MR4_RSVD1 0x0 - RegVal = ((0x00000000U << DDR_PHY_MR4_RESERVED_31_16_SHIFT - | 0x00000000U << DDR_PHY_MR4_RSVD_15_13_SHIFT - | 0x00000000U << DDR_PHY_MR4_WRP_SHIFT - | 0x00000000U << DDR_PHY_MR4_RDP_SHIFT - | 0x00000000U << DDR_PHY_MR4_RPTM_SHIFT - | 0x00000000U << DDR_PHY_MR4_SRA_SHIFT - | 0x00000000U << DDR_PHY_MR4_CS2CMDL_SHIFT - | 0x00000000U << DDR_PHY_MR4_RSVD1_SHIFT - | 0x00000000U << DDR_PHY_MR4_IVM_SHIFT - | 0x00000000U << DDR_PHY_MR4_TCRM_SHIFT - | 0x00000000U << DDR_PHY_MR4_TCRR_SHIFT - | 0x00000000U << DDR_PHY_MR4_MPDM_SHIFT - | 0x00000000U << DDR_PHY_MR4_RSVD_0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_MR4_OFFSET ,0xFFFFFFFFU ,0x00000000U); - /*############################################################################################################################ */ + * Internal VREF Monitor + * PSU_DDR_PHY_MR4_IVM 0x0 - /*Register : MR5 @ 0XFD080194

+ * Temperature Controlled Refresh Mode + * PSU_DDR_PHY_MR4_TCRM 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_MR5_RESERVED_31_16 0x0 + * Temperature Controlled Refresh Range + * PSU_DDR_PHY_MR4_TCRR 0x0 - These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0. - PSU_DDR_PHY_MR5_RSVD 0x0 + * Maximum Power Down Mode + * PSU_DDR_PHY_MR4_MPDM 0x0 - Read DBI - PSU_DDR_PHY_MR5_RDBI 0x0 + * This is a JEDEC reserved bit and is recommended by JEDEC to be programme + * d to 0x0. + * PSU_DDR_PHY_MR4_RSVD_0 0x0 - Write DBI - PSU_DDR_PHY_MR5_WDBI 0x0 + * DDR4 Mode Register 4 + * (OFFSET, MASK, VALUE) (0XFD080190, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDR_PHY_MR4_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ - Data Mask - PSU_DDR_PHY_MR5_DM 0x1 + /* + * Register : MR5 @ 0XFD080194 - CA Parity Persistent Error - PSU_DDR_PHY_MR5_CAPPE 0x1 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_MR5_RESERVED_31_16 0x0 - RTT_PARK - PSU_DDR_PHY_MR5_RTTPARK 0x3 + * These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. + * PSU_DDR_PHY_MR5_RSVD 0x0 - ODT Input Buffer during Power Down mode - PSU_DDR_PHY_MR5_ODTIBPD 0x0 + * Read DBI + * PSU_DDR_PHY_MR5_RDBI 0x0 - C/A Parity Error Status - PSU_DDR_PHY_MR5_CAPES 0x0 + * Write DBI + * PSU_DDR_PHY_MR5_WDBI 0x0 - CRC Error Clear - PSU_DDR_PHY_MR5_CRCEC 0x0 + * Data Mask + * PSU_DDR_PHY_MR5_DM 0x1 - C/A Parity Latency Mode - PSU_DDR_PHY_MR5_CAPM 0x0 + * CA Parity Persistent Error + * PSU_DDR_PHY_MR5_CAPPE 0x1 - DDR4 Mode Register 5 - (OFFSET, MASK, VALUE) (0XFD080194, 0xFFFFFFFFU ,0x000006C0U) - RegMask = (DDR_PHY_MR5_RESERVED_31_16_MASK | DDR_PHY_MR5_RSVD_MASK | DDR_PHY_MR5_RDBI_MASK | DDR_PHY_MR5_WDBI_MASK | DDR_PHY_MR5_DM_MASK | DDR_PHY_MR5_CAPPE_MASK | DDR_PHY_MR5_RTTPARK_MASK | DDR_PHY_MR5_ODTIBPD_MASK | DDR_PHY_MR5_CAPES_MASK | DDR_PHY_MR5_CRCEC_MASK | DDR_PHY_MR5_CAPM_MASK | 0 ); + * RTT_PARK + * PSU_DDR_PHY_MR5_RTTPARK 0x3 - RegVal = ((0x00000000U << DDR_PHY_MR5_RESERVED_31_16_SHIFT - | 0x00000000U << DDR_PHY_MR5_RSVD_SHIFT - | 0x00000000U << DDR_PHY_MR5_RDBI_SHIFT - | 0x00000000U << DDR_PHY_MR5_WDBI_SHIFT - | 0x00000001U << DDR_PHY_MR5_DM_SHIFT - | 0x00000001U << DDR_PHY_MR5_CAPPE_SHIFT - | 0x00000003U << DDR_PHY_MR5_RTTPARK_SHIFT - | 0x00000000U << DDR_PHY_MR5_ODTIBPD_SHIFT - | 0x00000000U << DDR_PHY_MR5_CAPES_SHIFT - | 0x00000000U << DDR_PHY_MR5_CRCEC_SHIFT - | 0x00000000U << DDR_PHY_MR5_CAPM_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_MR5_OFFSET ,0xFFFFFFFFU ,0x000006C0U); - /*############################################################################################################################ */ + * ODT Input Buffer during Power Down mode + * PSU_DDR_PHY_MR5_ODTIBPD 0x0 - /*Register : MR6 @ 0XFD080198

+ * C/A Parity Error Status + * PSU_DDR_PHY_MR5_CAPES 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_MR6_RESERVED_31_16 0x0 + * CRC Error Clear + * PSU_DDR_PHY_MR5_CRCEC 0x0 - These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0. - PSU_DDR_PHY_MR6_RSVD_15_13 0x0 + * C/A Parity Latency Mode + * PSU_DDR_PHY_MR5_CAPM 0x0 - CAS_n to CAS_n command delay for same bank group (tCCD_L) - PSU_DDR_PHY_MR6_TCCDL 0x2 + * DDR4 Mode Register 5 + * (OFFSET, MASK, VALUE) (0XFD080194, 0xFFFFFFFFU ,0x000006C0U) + */ + PSU_Mask_Write(DDR_PHY_MR5_OFFSET, 0xFFFFFFFFU, 0x000006C0U); +/*##################################################################### */ - These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0. - PSU_DDR_PHY_MR6_RSVD_9_8 0x0 + /* + * Register : MR6 @ 0XFD080198 - VrefDQ Training Enable - PSU_DDR_PHY_MR6_VDDQTEN 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_MR6_RESERVED_31_16 0x0 - VrefDQ Training Range - PSU_DDR_PHY_MR6_VDQTRG 0x0 + * These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. + * PSU_DDR_PHY_MR6_RSVD_15_13 0x0 - VrefDQ Training Values - PSU_DDR_PHY_MR6_VDQTVAL 0x19 + * CAS_n to CAS_n command delay for same bank group (tCCD_L) + * PSU_DDR_PHY_MR6_TCCDL 0x2 - DDR4 Mode Register 6 - (OFFSET, MASK, VALUE) (0XFD080198, 0xFFFFFFFFU ,0x00000819U) - RegMask = (DDR_PHY_MR6_RESERVED_31_16_MASK | DDR_PHY_MR6_RSVD_15_13_MASK | DDR_PHY_MR6_TCCDL_MASK | DDR_PHY_MR6_RSVD_9_8_MASK | DDR_PHY_MR6_VDDQTEN_MASK | DDR_PHY_MR6_VDQTRG_MASK | DDR_PHY_MR6_VDQTVAL_MASK | 0 ); + * These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. + * PSU_DDR_PHY_MR6_RSVD_9_8 0x0 - RegVal = ((0x00000000U << DDR_PHY_MR6_RESERVED_31_16_SHIFT - | 0x00000000U << DDR_PHY_MR6_RSVD_15_13_SHIFT - | 0x00000002U << DDR_PHY_MR6_TCCDL_SHIFT - | 0x00000000U << DDR_PHY_MR6_RSVD_9_8_SHIFT - | 0x00000000U << DDR_PHY_MR6_VDDQTEN_SHIFT - | 0x00000000U << DDR_PHY_MR6_VDQTRG_SHIFT - | 0x00000019U << DDR_PHY_MR6_VDQTVAL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_MR6_OFFSET ,0xFFFFFFFFU ,0x00000819U); - /*############################################################################################################################ */ + * VrefDQ Training Enable + * PSU_DDR_PHY_MR6_VDDQTEN 0x0 - /*Register : MR11 @ 0XFD0801AC

+ * VrefDQ Training Range + * PSU_DDR_PHY_MR6_VDQTRG 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_MR11_RESERVED_31_8 0x0 + * VrefDQ Training Values + * PSU_DDR_PHY_MR6_VDQTVAL 0x19 - These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0. - PSU_DDR_PHY_MR11_RSVD 0x0 + * DDR4 Mode Register 6 + * (OFFSET, MASK, VALUE) (0XFD080198, 0xFFFFFFFFU ,0x00000819U) + */ + PSU_Mask_Write(DDR_PHY_MR6_OFFSET, 0xFFFFFFFFU, 0x00000819U); +/*##################################################################### */ - Power Down Control - PSU_DDR_PHY_MR11_PDCTL 0x0 + /* + * Register : MR11 @ 0XFD0801AC - DQ Bus Receiver On-Die-Termination - PSU_DDR_PHY_MR11_DQODT 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_MR11_RESERVED_31_8 0x0 - LPDDR4 Mode Register 11 - (OFFSET, MASK, VALUE) (0XFD0801AC, 0xFFFFFFFFU ,0x00000000U) - RegMask = (DDR_PHY_MR11_RESERVED_31_8_MASK | DDR_PHY_MR11_RSVD_MASK | DDR_PHY_MR11_PDCTL_MASK | DDR_PHY_MR11_DQODT_MASK | 0 ); + * These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. + * PSU_DDR_PHY_MR11_RSVD 0x0 - RegVal = ((0x00000000U << DDR_PHY_MR11_RESERVED_31_8_SHIFT - | 0x00000000U << DDR_PHY_MR11_RSVD_SHIFT - | 0x00000000U << DDR_PHY_MR11_PDCTL_SHIFT - | 0x00000000U << DDR_PHY_MR11_DQODT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_MR11_OFFSET ,0xFFFFFFFFU ,0x00000000U); - /*############################################################################################################################ */ + * Power Down Control + * PSU_DDR_PHY_MR11_PDCTL 0x0 - /*Register : MR12 @ 0XFD0801B0

+ * DQ Bus Receiver On-Die-Termination + * PSU_DDR_PHY_MR11_DQODT 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_MR12_RESERVED_31_8 0x0 + * LPDDR4 Mode Register 11 + * (OFFSET, MASK, VALUE) (0XFD0801AC, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDR_PHY_MR11_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ - These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0. - PSU_DDR_PHY_MR12_RSVD 0x0 + /* + * Register : MR12 @ 0XFD0801B0 - VREF_CA Range Select. - PSU_DDR_PHY_MR12_VR_CA 0x1 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_MR12_RESERVED_31_8 0x0 - Controls the VREF(ca) levels for Frequency-Set-Point[1:0]. - PSU_DDR_PHY_MR12_VREF_CA 0xd + * These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. + * PSU_DDR_PHY_MR12_RSVD 0x0 - LPDDR4 Mode Register 12 - (OFFSET, MASK, VALUE) (0XFD0801B0, 0xFFFFFFFFU ,0x0000004DU) - RegMask = (DDR_PHY_MR12_RESERVED_31_8_MASK | DDR_PHY_MR12_RSVD_MASK | DDR_PHY_MR12_VR_CA_MASK | DDR_PHY_MR12_VREF_CA_MASK | 0 ); + * VREF_CA Range Select. + * PSU_DDR_PHY_MR12_VR_CA 0x1 - RegVal = ((0x00000000U << DDR_PHY_MR12_RESERVED_31_8_SHIFT - | 0x00000000U << DDR_PHY_MR12_RSVD_SHIFT - | 0x00000001U << DDR_PHY_MR12_VR_CA_SHIFT - | 0x0000000DU << DDR_PHY_MR12_VREF_CA_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_MR12_OFFSET ,0xFFFFFFFFU ,0x0000004DU); - /*############################################################################################################################ */ + * Controls the VREF(ca) levels for Frequency-Set-Point[1:0]. + * PSU_DDR_PHY_MR12_VREF_CA 0xd - /*Register : MR13 @ 0XFD0801B4

+ * LPDDR4 Mode Register 12 + * (OFFSET, MASK, VALUE) (0XFD0801B0, 0xFFFFFFFFU ,0x0000004DU) + */ + PSU_Mask_Write(DDR_PHY_MR12_OFFSET, 0xFFFFFFFFU, 0x0000004DU); +/*##################################################################### */ - Reserved. Return zeroes on reads. - PSU_DDR_PHY_MR13_RESERVED_31_8 0x0 + /* + * Register : MR13 @ 0XFD0801B4 - Frequency Set Point Operation Mode - PSU_DDR_PHY_MR13_FSPOP 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_MR13_RESERVED_31_8 0x0 - Frequency Set Point Write Enable - PSU_DDR_PHY_MR13_FSPWR 0x0 + * Frequency Set Point Operation Mode + * PSU_DDR_PHY_MR13_FSPOP 0x0 - Data Mask Enable - PSU_DDR_PHY_MR13_DMD 0x0 + * Frequency Set Point Write Enable + * PSU_DDR_PHY_MR13_FSPWR 0x0 - Refresh Rate Option - PSU_DDR_PHY_MR13_RRO 0x0 + * Data Mask Enable + * PSU_DDR_PHY_MR13_DMD 0x0 - VREF Current Generator - PSU_DDR_PHY_MR13_VRCG 0x1 + * Refresh Rate Option + * PSU_DDR_PHY_MR13_RRO 0x0 - VREF Output - PSU_DDR_PHY_MR13_VRO 0x0 + * VREF Current Generator + * PSU_DDR_PHY_MR13_VRCG 0x1 - Read Preamble Training Mode - PSU_DDR_PHY_MR13_RPT 0x0 + * VREF Output + * PSU_DDR_PHY_MR13_VRO 0x0 - Command Bus Training - PSU_DDR_PHY_MR13_CBT 0x0 + * Read Preamble Training Mode + * PSU_DDR_PHY_MR13_RPT 0x0 - LPDDR4 Mode Register 13 - (OFFSET, MASK, VALUE) (0XFD0801B4, 0xFFFFFFFFU ,0x00000008U) - RegMask = (DDR_PHY_MR13_RESERVED_31_8_MASK | DDR_PHY_MR13_FSPOP_MASK | DDR_PHY_MR13_FSPWR_MASK | DDR_PHY_MR13_DMD_MASK | DDR_PHY_MR13_RRO_MASK | DDR_PHY_MR13_VRCG_MASK | DDR_PHY_MR13_VRO_MASK | DDR_PHY_MR13_RPT_MASK | DDR_PHY_MR13_CBT_MASK | 0 ); + * Command Bus Training + * PSU_DDR_PHY_MR13_CBT 0x0 - RegVal = ((0x00000000U << DDR_PHY_MR13_RESERVED_31_8_SHIFT - | 0x00000000U << DDR_PHY_MR13_FSPOP_SHIFT - | 0x00000000U << DDR_PHY_MR13_FSPWR_SHIFT - | 0x00000000U << DDR_PHY_MR13_DMD_SHIFT - | 0x00000000U << DDR_PHY_MR13_RRO_SHIFT - | 0x00000001U << DDR_PHY_MR13_VRCG_SHIFT - | 0x00000000U << DDR_PHY_MR13_VRO_SHIFT - | 0x00000000U << DDR_PHY_MR13_RPT_SHIFT - | 0x00000000U << DDR_PHY_MR13_CBT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_MR13_OFFSET ,0xFFFFFFFFU ,0x00000008U); - /*############################################################################################################################ */ + * LPDDR4 Mode Register 13 + * (OFFSET, MASK, VALUE) (0XFD0801B4, 0xFFFFFFFFU ,0x00000008U) + */ + PSU_Mask_Write(DDR_PHY_MR13_OFFSET, 0xFFFFFFFFU, 0x00000008U); +/*##################################################################### */ - /*Register : MR14 @ 0XFD0801B8

+ /* + * Register : MR14 @ 0XFD0801B8 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_MR14_RESERVED_31_8 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_MR14_RESERVED_31_8 0x0 - These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0. - PSU_DDR_PHY_MR14_RSVD 0x0 + * These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. + * PSU_DDR_PHY_MR14_RSVD 0x0 - VREFDQ Range Selects. - PSU_DDR_PHY_MR14_VR_DQ 0x1 + * VREFDQ Range Selects. + * PSU_DDR_PHY_MR14_VR_DQ 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_MR14_VREF_DQ 0xd + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_MR14_VREF_DQ 0xd - LPDDR4 Mode Register 14 - (OFFSET, MASK, VALUE) (0XFD0801B8, 0xFFFFFFFFU ,0x0000004DU) - RegMask = (DDR_PHY_MR14_RESERVED_31_8_MASK | DDR_PHY_MR14_RSVD_MASK | DDR_PHY_MR14_VR_DQ_MASK | DDR_PHY_MR14_VREF_DQ_MASK | 0 ); + * LPDDR4 Mode Register 14 + * (OFFSET, MASK, VALUE) (0XFD0801B8, 0xFFFFFFFFU ,0x0000004DU) + */ + PSU_Mask_Write(DDR_PHY_MR14_OFFSET, 0xFFFFFFFFU, 0x0000004DU); +/*##################################################################### */ - RegVal = ((0x00000000U << DDR_PHY_MR14_RESERVED_31_8_SHIFT - | 0x00000000U << DDR_PHY_MR14_RSVD_SHIFT - | 0x00000001U << DDR_PHY_MR14_VR_DQ_SHIFT - | 0x0000000DU << DDR_PHY_MR14_VREF_DQ_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_MR14_OFFSET ,0xFFFFFFFFU ,0x0000004DU); - /*############################################################################################################################ */ + /* + * Register : MR22 @ 0XFD0801D8 - /*Register : MR22 @ 0XFD0801D8

+ * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_MR22_RESERVED_31_8 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_MR22_RESERVED_31_8 0x0 + * These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. + * PSU_DDR_PHY_MR22_RSVD 0x0 - These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0. - PSU_DDR_PHY_MR22_RSVD 0x0 + * CA ODT termination disable. + * PSU_DDR_PHY_MR22_ODTD_CA 0x0 - CA ODT termination disable. - PSU_DDR_PHY_MR22_ODTD_CA 0x0 + * ODT CS override. + * PSU_DDR_PHY_MR22_ODTE_CS 0x0 - ODT CS override. - PSU_DDR_PHY_MR22_ODTE_CS 0x0 + * ODT CK override. + * PSU_DDR_PHY_MR22_ODTE_CK 0x0 - ODT CK override. - PSU_DDR_PHY_MR22_ODTE_CK 0x0 + * Controller ODT value for VOH calibration. + * PSU_DDR_PHY_MR22_CODT 0x0 - Controller ODT value for VOH calibration. - PSU_DDR_PHY_MR22_CODT 0x0 + * LPDDR4 Mode Register 22 + * (OFFSET, MASK, VALUE) (0XFD0801D8, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDR_PHY_MR22_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ - LPDDR4 Mode Register 22 - (OFFSET, MASK, VALUE) (0XFD0801D8, 0xFFFFFFFFU ,0x00000000U) - RegMask = (DDR_PHY_MR22_RESERVED_31_8_MASK | DDR_PHY_MR22_RSVD_MASK | DDR_PHY_MR22_ODTD_CA_MASK | DDR_PHY_MR22_ODTE_CS_MASK | DDR_PHY_MR22_ODTE_CK_MASK | DDR_PHY_MR22_CODT_MASK | 0 ); + /* + * Register : DTCR0 @ 0XFD080200 - RegVal = ((0x00000000U << DDR_PHY_MR22_RESERVED_31_8_SHIFT - | 0x00000000U << DDR_PHY_MR22_RSVD_SHIFT - | 0x00000000U << DDR_PHY_MR22_ODTD_CA_SHIFT - | 0x00000000U << DDR_PHY_MR22_ODTE_CS_SHIFT - | 0x00000000U << DDR_PHY_MR22_ODTE_CK_SHIFT - | 0x00000000U << DDR_PHY_MR22_CODT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_MR22_OFFSET ,0xFFFFFFFFU ,0x00000000U); - /*############################################################################################################################ */ + * Refresh During Training + * PSU_DDR_PHY_DTCR0_RFSHDT 0x8 - /*Register : DTCR0 @ 0XFD080200

+ * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTCR0_RESERVED_27_26 0x0 - Refresh During Training - PSU_DDR_PHY_DTCR0_RFSHDT 0x8 + * Data Training Debug Rank Select + * PSU_DDR_PHY_DTCR0_DTDRS 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTCR0_RESERVED_27_26 0x0 + * Data Training with Early/Extended Gate + * PSU_DDR_PHY_DTCR0_DTEXG 0x0 - Data Training Debug Rank Select - PSU_DDR_PHY_DTCR0_DTDRS 0x0 + * Data Training Extended Write DQS + * PSU_DDR_PHY_DTCR0_DTEXD 0x0 - Data Training with Early/Extended Gate - PSU_DDR_PHY_DTCR0_DTEXG 0x0 + * Data Training Debug Step + * PSU_DDR_PHY_DTCR0_DTDSTP 0x0 - Data Training Extended Write DQS - PSU_DDR_PHY_DTCR0_DTEXD 0x0 + * Data Training Debug Enable + * PSU_DDR_PHY_DTCR0_DTDEN 0x0 - Data Training Debug Step - PSU_DDR_PHY_DTCR0_DTDSTP 0x0 + * Data Training Debug Byte Select + * PSU_DDR_PHY_DTCR0_DTDBS 0x0 - Data Training Debug Enable - PSU_DDR_PHY_DTCR0_DTDEN 0x0 + * Data Training read DBI deskewing configuration + * PSU_DDR_PHY_DTCR0_DTRDBITR 0x2 - Data Training Debug Byte Select - PSU_DDR_PHY_DTCR0_DTDBS 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTCR0_RESERVED_13 0x0 - Data Training read DBI deskewing configuration - PSU_DDR_PHY_DTCR0_DTRDBITR 0x2 + * Data Training Write Bit Deskew Data Mask + * PSU_DDR_PHY_DTCR0_DTWBDDM 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTCR0_RESERVED_13 0x0 + * Refreshes Issued During Entry to Training + * PSU_DDR_PHY_DTCR0_RFSHEN 0x1 - Data Training Write Bit Deskew Data Mask - PSU_DDR_PHY_DTCR0_DTWBDDM 0x1 + * Data Training Compare Data + * PSU_DDR_PHY_DTCR0_DTCMPD 0x1 - Refreshes Issued During Entry to Training - PSU_DDR_PHY_DTCR0_RFSHEN 0x1 + * Data Training Using MPR + * PSU_DDR_PHY_DTCR0_DTMPR 0x1 - Data Training Compare Data - PSU_DDR_PHY_DTCR0_DTCMPD 0x1 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTCR0_RESERVED_5_4 0x0 - Data Training Using MPR - PSU_DDR_PHY_DTCR0_DTMPR 0x1 + * Data Training Repeat Number + * PSU_DDR_PHY_DTCR0_DTRPTN 0x7 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTCR0_RESERVED_5_4 0x0 + * Data Training Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD080200, 0xFFFFFFFFU ,0x800091C7U) + */ + PSU_Mask_Write(DDR_PHY_DTCR0_OFFSET, 0xFFFFFFFFU, 0x800091C7U); +/*##################################################################### */ - Data Training Repeat Number - PSU_DDR_PHY_DTCR0_DTRPTN 0x7 + /* + * Register : DTCR1 @ 0XFD080204 - Data Training Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD080200, 0xFFFFFFFFU ,0x800091C7U) - RegMask = (DDR_PHY_DTCR0_RFSHDT_MASK | DDR_PHY_DTCR0_RESERVED_27_26_MASK | DDR_PHY_DTCR0_DTDRS_MASK | DDR_PHY_DTCR0_DTEXG_MASK | DDR_PHY_DTCR0_DTEXD_MASK | DDR_PHY_DTCR0_DTDSTP_MASK | DDR_PHY_DTCR0_DTDEN_MASK | DDR_PHY_DTCR0_DTDBS_MASK | DDR_PHY_DTCR0_DTRDBITR_MASK | DDR_PHY_DTCR0_RESERVED_13_MASK | DDR_PHY_DTCR0_DTWBDDM_MASK | DDR_PHY_DTCR0_RFSHEN_MASK | DDR_PHY_DTCR0_DTCMPD_MASK | DDR_PHY_DTCR0_DTMPR_MASK | DDR_PHY_DTCR0_RESERVED_5_4_MASK | DDR_PHY_DTCR0_DTRPTN_MASK | 0 ); + * Rank Enable. + * PSU_DDR_PHY_DTCR1_RANKEN_RSVD 0x0 - RegVal = ((0x00000008U << DDR_PHY_DTCR0_RFSHDT_SHIFT - | 0x00000000U << DDR_PHY_DTCR0_RESERVED_27_26_SHIFT - | 0x00000000U << DDR_PHY_DTCR0_DTDRS_SHIFT - | 0x00000000U << DDR_PHY_DTCR0_DTEXG_SHIFT - | 0x00000000U << DDR_PHY_DTCR0_DTEXD_SHIFT - | 0x00000000U << DDR_PHY_DTCR0_DTDSTP_SHIFT - | 0x00000000U << DDR_PHY_DTCR0_DTDEN_SHIFT - | 0x00000000U << DDR_PHY_DTCR0_DTDBS_SHIFT - | 0x00000002U << DDR_PHY_DTCR0_DTRDBITR_SHIFT - | 0x00000000U << DDR_PHY_DTCR0_RESERVED_13_SHIFT - | 0x00000001U << DDR_PHY_DTCR0_DTWBDDM_SHIFT - | 0x00000001U << DDR_PHY_DTCR0_RFSHEN_SHIFT - | 0x00000001U << DDR_PHY_DTCR0_DTCMPD_SHIFT - | 0x00000001U << DDR_PHY_DTCR0_DTMPR_SHIFT - | 0x00000000U << DDR_PHY_DTCR0_RESERVED_5_4_SHIFT - | 0x00000007U << DDR_PHY_DTCR0_DTRPTN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DTCR0_OFFSET ,0xFFFFFFFFU ,0x800091C7U); - /*############################################################################################################################ */ + * Rank Enable. + * PSU_DDR_PHY_DTCR1_RANKEN 0x1 - /*Register : DTCR1 @ 0XFD080204

+ * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTCR1_RESERVED_15_14 0x0 - Rank Enable. - PSU_DDR_PHY_DTCR1_RANKEN_RSVD 0x0 + * Data Training Rank + * PSU_DDR_PHY_DTCR1_DTRANK 0x0 - Rank Enable. - PSU_DDR_PHY_DTCR1_RANKEN 0x1 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTCR1_RESERVED_11 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTCR1_RESERVED_15_14 0x0 + * Read Leveling Gate Sampling Difference + * PSU_DDR_PHY_DTCR1_RDLVLGDIFF 0x2 - Data Training Rank - PSU_DDR_PHY_DTCR1_DTRANK 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTCR1_RESERVED_7 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTCR1_RESERVED_11 0x0 + * Read Leveling Gate Shift + * PSU_DDR_PHY_DTCR1_RDLVLGS 0x3 - Read Leveling Gate Sampling Difference - PSU_DDR_PHY_DTCR1_RDLVLGDIFF 0x2 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DTCR1_RESERVED_3 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTCR1_RESERVED_7 0x0 + * Read Preamble Training enable + * PSU_DDR_PHY_DTCR1_RDPRMVL_TRN 0x1 - Read Leveling Gate Shift - PSU_DDR_PHY_DTCR1_RDLVLGS 0x3 + * Read Leveling Enable + * PSU_DDR_PHY_DTCR1_RDLVLEN 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DTCR1_RESERVED_3 0x0 + * Basic Gate Training Enable + * PSU_DDR_PHY_DTCR1_BSTEN 0x0 - Read Preamble Training enable - PSU_DDR_PHY_DTCR1_RDPRMVL_TRN 0x1 + * Data Training Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD080204, 0xFFFFFFFFU ,0x00010236U) + */ + PSU_Mask_Write(DDR_PHY_DTCR1_OFFSET, 0xFFFFFFFFU, 0x00010236U); +/*##################################################################### */ - Read Leveling Enable - PSU_DDR_PHY_DTCR1_RDLVLEN 0x1 + /* + * Register : CATR0 @ 0XFD080240 - Basic Gate Training Enable - PSU_DDR_PHY_DTCR1_BSTEN 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_CATR0_RESERVED_31_21 0x0 - Data Training Configuration Register 1 - (OFFSET, MASK, VALUE) (0XFD080204, 0xFFFFFFFFU ,0x00010236U) - RegMask = (DDR_PHY_DTCR1_RANKEN_RSVD_MASK | DDR_PHY_DTCR1_RANKEN_MASK | DDR_PHY_DTCR1_RESERVED_15_14_MASK | DDR_PHY_DTCR1_DTRANK_MASK | DDR_PHY_DTCR1_RESERVED_11_MASK | DDR_PHY_DTCR1_RDLVLGDIFF_MASK | DDR_PHY_DTCR1_RESERVED_7_MASK | DDR_PHY_DTCR1_RDLVLGS_MASK | DDR_PHY_DTCR1_RESERVED_3_MASK | DDR_PHY_DTCR1_RDPRMVL_TRN_MASK | DDR_PHY_DTCR1_RDLVLEN_MASK | DDR_PHY_DTCR1_BSTEN_MASK | 0 ); + * Minimum time (in terms of number of dram clocks) between two consectuve + * CA calibration command + * PSU_DDR_PHY_CATR0_CACD 0x14 - RegVal = ((0x00000000U << DDR_PHY_DTCR1_RANKEN_RSVD_SHIFT - | 0x00000001U << DDR_PHY_DTCR1_RANKEN_SHIFT - | 0x00000000U << DDR_PHY_DTCR1_RESERVED_15_14_SHIFT - | 0x00000000U << DDR_PHY_DTCR1_DTRANK_SHIFT - | 0x00000000U << DDR_PHY_DTCR1_RESERVED_11_SHIFT - | 0x00000002U << DDR_PHY_DTCR1_RDLVLGDIFF_SHIFT - | 0x00000000U << DDR_PHY_DTCR1_RESERVED_7_SHIFT - | 0x00000003U << DDR_PHY_DTCR1_RDLVLGS_SHIFT - | 0x00000000U << DDR_PHY_DTCR1_RESERVED_3_SHIFT - | 0x00000001U << DDR_PHY_DTCR1_RDPRMVL_TRN_SHIFT - | 0x00000001U << DDR_PHY_DTCR1_RDLVLEN_SHIFT - | 0x00000000U << DDR_PHY_DTCR1_BSTEN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DTCR1_OFFSET ,0xFFFFFFFFU ,0x00010236U); - /*############################################################################################################################ */ + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_CATR0_RESERVED_15_13 0x0 - /*Register : CATR0 @ 0XFD080240

+ * Minimum time (in terms of number of dram clocks) PUB should wait before + * sampling the CA response after Calibration command has been sent to the + * memory + * PSU_DDR_PHY_CATR0_CAADR 0x10 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_CATR0_RESERVED_31_21 0x0 + * CA_1 Response Byte Lane 1 + * PSU_DDR_PHY_CATR0_CA1BYTE1 0x5 - Minimum time (in terms of number of dram clocks) between two consectuve CA calibration command - PSU_DDR_PHY_CATR0_CACD 0x14 + * CA_1 Response Byte Lane 0 + * PSU_DDR_PHY_CATR0_CA1BYTE0 0x4 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_CATR0_RESERVED_15_13 0x0 + * CA Training Register 0 + * (OFFSET, MASK, VALUE) (0XFD080240, 0xFFFFFFFFU ,0x00141054U) + */ + PSU_Mask_Write(DDR_PHY_CATR0_OFFSET, 0xFFFFFFFFU, 0x00141054U); +/*##################################################################### */ - Minimum time (in terms of number of dram clocks) PUB should wait before sampling the CA response after Calibration command ha - been sent to the memory - PSU_DDR_PHY_CATR0_CAADR 0x10 + /* + * Register : DQSDR0 @ 0XFD080250 - CA_1 Response Byte Lane 1 - PSU_DDR_PHY_CATR0_CA1BYTE1 0x5 + * Number of delay taps by which the DQS gate LCDL will be updated when DQS + * drift is detected + * PSU_DDR_PHY_DQSDR0_DFTDLY 0x0 - CA_1 Response Byte Lane 0 - PSU_DDR_PHY_CATR0_CA1BYTE0 0x4 - - CA Training Register 0 - (OFFSET, MASK, VALUE) (0XFD080240, 0xFFFFFFFFU ,0x00141054U) - RegMask = (DDR_PHY_CATR0_RESERVED_31_21_MASK | DDR_PHY_CATR0_CACD_MASK | DDR_PHY_CATR0_RESERVED_15_13_MASK | DDR_PHY_CATR0_CAADR_MASK | DDR_PHY_CATR0_CA1BYTE1_MASK | DDR_PHY_CATR0_CA1BYTE0_MASK | 0 ); - - RegVal = ((0x00000000U << DDR_PHY_CATR0_RESERVED_31_21_SHIFT - | 0x00000014U << DDR_PHY_CATR0_CACD_SHIFT - | 0x00000000U << DDR_PHY_CATR0_RESERVED_15_13_SHIFT - | 0x00000010U << DDR_PHY_CATR0_CAADR_SHIFT - | 0x00000005U << DDR_PHY_CATR0_CA1BYTE1_SHIFT - | 0x00000004U << DDR_PHY_CATR0_CA1BYTE0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_CATR0_OFFSET ,0xFFFFFFFFU ,0x00141054U); - /*############################################################################################################################ */ + * Drift Impedance Update + * PSU_DDR_PHY_DQSDR0_DFTZQUP 0x0 - /*Register : BISTLSR @ 0XFD080414

+ * Drift DDL Update + * PSU_DDR_PHY_DQSDR0_DFTDDLUP 0x0 - LFSR seed for pseudo-random BIST patterns - PSU_DDR_PHY_BISTLSR_SEED 0x12341000 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DQSDR0_RESERVED_25_22 0x0 - BIST LFSR Seed Register - (OFFSET, MASK, VALUE) (0XFD080414, 0xFFFFFFFFU ,0x12341000U) - RegMask = (DDR_PHY_BISTLSR_SEED_MASK | 0 ); + * Drift Read Spacing + * PSU_DDR_PHY_DQSDR0_DFTRDSPC 0x0 - RegVal = ((0x12341000U << DDR_PHY_BISTLSR_SEED_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_BISTLSR_OFFSET ,0xFFFFFFFFU ,0x12341000U); - /*############################################################################################################################ */ + * Drift Back-to-Back Reads + * PSU_DDR_PHY_DQSDR0_DFTB2BRD 0x8 - /*Register : RIOCR5 @ 0XFD0804F4

+ * Drift Idle Reads + * PSU_DDR_PHY_DQSDR0_DFTIDLRD 0x8 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_RIOCR5_RESERVED_31_16 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DQSDR0_RESERVED_11_8 0x0 - Reserved. Return zeros on reads. - PSU_DDR_PHY_RIOCR5_ODTOEMODE_RSVD 0x0 + * Gate Pulse Enable + * PSU_DDR_PHY_DQSDR0_DFTGPULSE 0x0 - SDRAM On-die Termination Output Enable (OE) Mode Selection. - PSU_DDR_PHY_RIOCR5_ODTOEMODE 0x5 + * DQS Drift Update Mode + * PSU_DDR_PHY_DQSDR0_DFTUPMODE 0x0 - Rank I/O Configuration Register 5 - (OFFSET, MASK, VALUE) (0XFD0804F4, 0xFFFFFFFFU ,0x00000005U) - RegMask = (DDR_PHY_RIOCR5_RESERVED_31_16_MASK | DDR_PHY_RIOCR5_ODTOEMODE_RSVD_MASK | DDR_PHY_RIOCR5_ODTOEMODE_MASK | 0 ); + * DQS Drift Detection Mode + * PSU_DDR_PHY_DQSDR0_DFTDTMODE 0x0 - RegVal = ((0x00000000U << DDR_PHY_RIOCR5_RESERVED_31_16_SHIFT - | 0x00000000U << DDR_PHY_RIOCR5_ODTOEMODE_RSVD_SHIFT - | 0x00000005U << DDR_PHY_RIOCR5_ODTOEMODE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_RIOCR5_OFFSET ,0xFFFFFFFFU ,0x00000005U); - /*############################################################################################################################ */ + * DQS Drift Detection Enable + * PSU_DDR_PHY_DQSDR0_DFTDTEN 0x0 - /*Register : ACIOCR0 @ 0XFD080500

+ * DQS Drift Register 0 + * (OFFSET, MASK, VALUE) (0XFD080250, 0xFFFFFFFFU ,0x00088000U) + */ + PSU_Mask_Write(DDR_PHY_DQSDR0_OFFSET, 0xFFFFFFFFU, 0x00088000U); +/*##################################################################### */ - Address/Command Slew Rate (D3F I/O Only) - PSU_DDR_PHY_ACIOCR0_ACSR 0x0 + /* + * Register : BISTLSR @ 0XFD080414 - SDRAM Reset I/O Mode - PSU_DDR_PHY_ACIOCR0_RSTIOM 0x1 + * LFSR seed for pseudo-random BIST patterns + * PSU_DDR_PHY_BISTLSR_SEED 0x12341000 - SDRAM Reset Power Down Receiver - PSU_DDR_PHY_ACIOCR0_RSTPDR 0x1 + * BIST LFSR Seed Register + * (OFFSET, MASK, VALUE) (0XFD080414, 0xFFFFFFFFU ,0x12341000U) + */ + PSU_Mask_Write(DDR_PHY_BISTLSR_OFFSET, 0xFFFFFFFFU, 0x12341000U); +/*##################################################################### */ - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACIOCR0_RESERVED_27 0x0 + /* + * Register : RIOCR5 @ 0XFD0804F4 - SDRAM Reset On-Die Termination - PSU_DDR_PHY_ACIOCR0_RSTODT 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_RIOCR5_RESERVED_31_16 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACIOCR0_RESERVED_25_10 0x0 + * Reserved. Return zeros on reads. + * PSU_DDR_PHY_RIOCR5_ODTOEMODE_RSVD 0x0 - CK Duty Cycle Correction - PSU_DDR_PHY_ACIOCR0_CKDCC 0x0 + * SDRAM On-die Termination Output Enable (OE) Mode Selection. + * PSU_DDR_PHY_RIOCR5_ODTOEMODE 0x5 - AC Power Down Receiver Mode - PSU_DDR_PHY_ACIOCR0_ACPDRMODE 0x2 + * Rank I/O Configuration Register 5 + * (OFFSET, MASK, VALUE) (0XFD0804F4, 0xFFFFFFFFU ,0x00000005U) + */ + PSU_Mask_Write(DDR_PHY_RIOCR5_OFFSET, 0xFFFFFFFFU, 0x00000005U); +/*##################################################################### */ - AC On-die Termination Mode - PSU_DDR_PHY_ACIOCR0_ACODTMODE 0x2 + /* + * Register : ACIOCR0 @ 0XFD080500 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACIOCR0_RESERVED_1 0x0 + * Address/Command Slew Rate (D3F I/O Only) + * PSU_DDR_PHY_ACIOCR0_ACSR 0x0 - Control delayed or non-delayed clock to CS_N/ODT?CKE AC slices. - PSU_DDR_PHY_ACIOCR0_ACRANKCLKSEL 0x0 + * SDRAM Reset I/O Mode + * PSU_DDR_PHY_ACIOCR0_RSTIOM 0x1 - AC I/O Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD080500, 0xFFFFFFFFU ,0x30000028U) - RegMask = (DDR_PHY_ACIOCR0_ACSR_MASK | DDR_PHY_ACIOCR0_RSTIOM_MASK | DDR_PHY_ACIOCR0_RSTPDR_MASK | DDR_PHY_ACIOCR0_RESERVED_27_MASK | DDR_PHY_ACIOCR0_RSTODT_MASK | DDR_PHY_ACIOCR0_RESERVED_25_10_MASK | DDR_PHY_ACIOCR0_CKDCC_MASK | DDR_PHY_ACIOCR0_ACPDRMODE_MASK | DDR_PHY_ACIOCR0_ACODTMODE_MASK | DDR_PHY_ACIOCR0_RESERVED_1_MASK | DDR_PHY_ACIOCR0_ACRANKCLKSEL_MASK | 0 ); + * SDRAM Reset Power Down Receiver + * PSU_DDR_PHY_ACIOCR0_RSTPDR 0x1 - RegVal = ((0x00000000U << DDR_PHY_ACIOCR0_ACSR_SHIFT - | 0x00000001U << DDR_PHY_ACIOCR0_RSTIOM_SHIFT - | 0x00000001U << DDR_PHY_ACIOCR0_RSTPDR_SHIFT - | 0x00000000U << DDR_PHY_ACIOCR0_RESERVED_27_SHIFT - | 0x00000000U << DDR_PHY_ACIOCR0_RSTODT_SHIFT - | 0x00000000U << DDR_PHY_ACIOCR0_RESERVED_25_10_SHIFT - | 0x00000000U << DDR_PHY_ACIOCR0_CKDCC_SHIFT - | 0x00000002U << DDR_PHY_ACIOCR0_ACPDRMODE_SHIFT - | 0x00000002U << DDR_PHY_ACIOCR0_ACODTMODE_SHIFT - | 0x00000000U << DDR_PHY_ACIOCR0_RESERVED_1_SHIFT - | 0x00000000U << DDR_PHY_ACIOCR0_ACRANKCLKSEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_ACIOCR0_OFFSET ,0xFFFFFFFFU ,0x30000028U); - /*############################################################################################################################ */ + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACIOCR0_RESERVED_27 0x0 - /*Register : ACIOCR2 @ 0XFD080508

+ * SDRAM Reset On-Die Termination + * PSU_DDR_PHY_ACIOCR0_RSTODT 0x0 - Clock gating for glue logic inside CLKGEN and glue logic inside CONTROL slice - PSU_DDR_PHY_ACIOCR2_CLKGENCLKGATE 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACIOCR0_RESERVED_25_10 0x0 - Clock gating for Output Enable D slices [0] - PSU_DDR_PHY_ACIOCR2_ACOECLKGATE0 0x0 + * CK Duty Cycle Correction + * PSU_DDR_PHY_ACIOCR0_CKDCC 0x0 - Clock gating for Power Down Receiver D slices [0] - PSU_DDR_PHY_ACIOCR2_ACPDRCLKGATE0 0x0 + * AC Power Down Receiver Mode + * PSU_DDR_PHY_ACIOCR0_ACPDRMODE 0x2 - Clock gating for Termination Enable D slices [0] - PSU_DDR_PHY_ACIOCR2_ACTECLKGATE0 0x0 + * AC On-die Termination Mode + * PSU_DDR_PHY_ACIOCR0_ACODTMODE 0x2 - Clock gating for CK# D slices [1:0] - PSU_DDR_PHY_ACIOCR2_CKNCLKGATE0 0x2 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACIOCR0_RESERVED_1 0x0 - Clock gating for CK D slices [1:0] - PSU_DDR_PHY_ACIOCR2_CKCLKGATE0 0x2 + * Control delayed or non-delayed clock to CS_N/ODT?CKE AC slices. + * PSU_DDR_PHY_ACIOCR0_ACRANKCLKSEL 0x0 - Clock gating for AC D slices [23:0] - PSU_DDR_PHY_ACIOCR2_ACCLKGATE0 0x0 + * AC I/O Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD080500, 0xFFFFFFFFU ,0x30000028U) + */ + PSU_Mask_Write(DDR_PHY_ACIOCR0_OFFSET, 0xFFFFFFFFU, 0x30000028U); +/*##################################################################### */ - AC I/O Configuration Register 2 - (OFFSET, MASK, VALUE) (0XFD080508, 0xFFFFFFFFU ,0x0A000000U) - RegMask = (DDR_PHY_ACIOCR2_CLKGENCLKGATE_MASK | DDR_PHY_ACIOCR2_ACOECLKGATE0_MASK | DDR_PHY_ACIOCR2_ACPDRCLKGATE0_MASK | DDR_PHY_ACIOCR2_ACTECLKGATE0_MASK | DDR_PHY_ACIOCR2_CKNCLKGATE0_MASK | DDR_PHY_ACIOCR2_CKCLKGATE0_MASK | DDR_PHY_ACIOCR2_ACCLKGATE0_MASK | 0 ); + /* + * Register : ACIOCR2 @ 0XFD080508 - RegVal = ((0x00000000U << DDR_PHY_ACIOCR2_CLKGENCLKGATE_SHIFT - | 0x00000000U << DDR_PHY_ACIOCR2_ACOECLKGATE0_SHIFT - | 0x00000000U << DDR_PHY_ACIOCR2_ACPDRCLKGATE0_SHIFT - | 0x00000000U << DDR_PHY_ACIOCR2_ACTECLKGATE0_SHIFT - | 0x00000002U << DDR_PHY_ACIOCR2_CKNCLKGATE0_SHIFT - | 0x00000002U << DDR_PHY_ACIOCR2_CKCLKGATE0_SHIFT - | 0x00000000U << DDR_PHY_ACIOCR2_ACCLKGATE0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_ACIOCR2_OFFSET ,0xFFFFFFFFU ,0x0A000000U); - /*############################################################################################################################ */ + * Clock gating for glue logic inside CLKGEN and glue logic inside CONTROL + * slice + * PSU_DDR_PHY_ACIOCR2_CLKGENCLKGATE 0x0 - /*Register : ACIOCR3 @ 0XFD08050C

+ * Clock gating for Output Enable D slices [0] + * PSU_DDR_PHY_ACIOCR2_ACOECLKGATE0 0x0 - SDRAM Parity Output Enable (OE) Mode Selection - PSU_DDR_PHY_ACIOCR3_PAROEMODE 0x0 + * Clock gating for Power Down Receiver D slices [0] + * PSU_DDR_PHY_ACIOCR2_ACPDRCLKGATE0 0x0 - SDRAM Bank Group Output Enable (OE) Mode Selection - PSU_DDR_PHY_ACIOCR3_BGOEMODE 0x0 + * Clock gating for Termination Enable D slices [0] + * PSU_DDR_PHY_ACIOCR2_ACTECLKGATE0 0x0 - SDRAM Bank Address Output Enable (OE) Mode Selection - PSU_DDR_PHY_ACIOCR3_BAOEMODE 0x0 + * Clock gating for CK# D slices [1:0] + * PSU_DDR_PHY_ACIOCR2_CKNCLKGATE0 0x2 - SDRAM A[17] Output Enable (OE) Mode Selection - PSU_DDR_PHY_ACIOCR3_A17OEMODE 0x0 + * Clock gating for CK D slices [1:0] + * PSU_DDR_PHY_ACIOCR2_CKCLKGATE0 0x2 - SDRAM A[16] / RAS_n Output Enable (OE) Mode Selection - PSU_DDR_PHY_ACIOCR3_A16OEMODE 0x0 + * Clock gating for AC D slices [23:0] + * PSU_DDR_PHY_ACIOCR2_ACCLKGATE0 0x0 - SDRAM ACT_n Output Enable (OE) Mode Selection (DDR4 only) - PSU_DDR_PHY_ACIOCR3_ACTOEMODE 0x0 + * AC I/O Configuration Register 2 + * (OFFSET, MASK, VALUE) (0XFD080508, 0xFFFFFFFFU ,0x0A000000U) + */ + PSU_Mask_Write(DDR_PHY_ACIOCR2_OFFSET, 0xFFFFFFFFU, 0x0A000000U); +/*##################################################################### */ - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACIOCR3_RESERVED_15_8 0x0 + /* + * Register : ACIOCR3 @ 0XFD08050C - Reserved. Return zeros on reads. - PSU_DDR_PHY_ACIOCR3_CKOEMODE_RSVD 0x0 + * SDRAM Parity Output Enable (OE) Mode Selection + * PSU_DDR_PHY_ACIOCR3_PAROEMODE 0x0 - SDRAM CK Output Enable (OE) Mode Selection. - PSU_DDR_PHY_ACIOCR3_CKOEMODE 0x9 + * SDRAM Bank Group Output Enable (OE) Mode Selection + * PSU_DDR_PHY_ACIOCR3_BGOEMODE 0x0 - AC I/O Configuration Register 3 - (OFFSET, MASK, VALUE) (0XFD08050C, 0xFFFFFFFFU ,0x00000009U) - RegMask = (DDR_PHY_ACIOCR3_PAROEMODE_MASK | DDR_PHY_ACIOCR3_BGOEMODE_MASK | DDR_PHY_ACIOCR3_BAOEMODE_MASK | DDR_PHY_ACIOCR3_A17OEMODE_MASK | DDR_PHY_ACIOCR3_A16OEMODE_MASK | DDR_PHY_ACIOCR3_ACTOEMODE_MASK | DDR_PHY_ACIOCR3_RESERVED_15_8_MASK | DDR_PHY_ACIOCR3_CKOEMODE_RSVD_MASK | DDR_PHY_ACIOCR3_CKOEMODE_MASK | 0 ); + * SDRAM Bank Address Output Enable (OE) Mode Selection + * PSU_DDR_PHY_ACIOCR3_BAOEMODE 0x0 - RegVal = ((0x00000000U << DDR_PHY_ACIOCR3_PAROEMODE_SHIFT - | 0x00000000U << DDR_PHY_ACIOCR3_BGOEMODE_SHIFT - | 0x00000000U << DDR_PHY_ACIOCR3_BAOEMODE_SHIFT - | 0x00000000U << DDR_PHY_ACIOCR3_A17OEMODE_SHIFT - | 0x00000000U << DDR_PHY_ACIOCR3_A16OEMODE_SHIFT - | 0x00000000U << DDR_PHY_ACIOCR3_ACTOEMODE_SHIFT - | 0x00000000U << DDR_PHY_ACIOCR3_RESERVED_15_8_SHIFT - | 0x00000000U << DDR_PHY_ACIOCR3_CKOEMODE_RSVD_SHIFT - | 0x00000009U << DDR_PHY_ACIOCR3_CKOEMODE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_ACIOCR3_OFFSET ,0xFFFFFFFFU ,0x00000009U); - /*############################################################################################################################ */ + * SDRAM A[17] Output Enable (OE) Mode Selection + * PSU_DDR_PHY_ACIOCR3_A17OEMODE 0x0 - /*Register : ACIOCR4 @ 0XFD080510

+ * SDRAM A[16] / RAS_n Output Enable (OE) Mode Selection + * PSU_DDR_PHY_ACIOCR3_A16OEMODE 0x0 - Clock gating for AC LB slices and loopback read valid slices - PSU_DDR_PHY_ACIOCR4_LBCLKGATE 0x0 + * SDRAM ACT_n Output Enable (OE) Mode Selection (DDR4 only) + * PSU_DDR_PHY_ACIOCR3_ACTOEMODE 0x0 - Clock gating for Output Enable D slices [1] - PSU_DDR_PHY_ACIOCR4_ACOECLKGATE1 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACIOCR3_RESERVED_15_8 0x0 - Clock gating for Power Down Receiver D slices [1] - PSU_DDR_PHY_ACIOCR4_ACPDRCLKGATE1 0x0 + * Reserved. Return zeros on reads. + * PSU_DDR_PHY_ACIOCR3_CKOEMODE_RSVD 0x0 - Clock gating for Termination Enable D slices [1] - PSU_DDR_PHY_ACIOCR4_ACTECLKGATE1 0x0 + * SDRAM CK Output Enable (OE) Mode Selection. + * PSU_DDR_PHY_ACIOCR3_CKOEMODE 0x9 - Clock gating for CK# D slices [3:2] - PSU_DDR_PHY_ACIOCR4_CKNCLKGATE1 0x2 + * AC I/O Configuration Register 3 + * (OFFSET, MASK, VALUE) (0XFD08050C, 0xFFFFFFFFU ,0x00000009U) + */ + PSU_Mask_Write(DDR_PHY_ACIOCR3_OFFSET, 0xFFFFFFFFU, 0x00000009U); +/*##################################################################### */ - Clock gating for CK D slices [3:2] - PSU_DDR_PHY_ACIOCR4_CKCLKGATE1 0x2 + /* + * Register : ACIOCR4 @ 0XFD080510 - Clock gating for AC D slices [47:24] - PSU_DDR_PHY_ACIOCR4_ACCLKGATE1 0x0 + * Clock gating for AC LB slices and loopback read valid slices + * PSU_DDR_PHY_ACIOCR4_LBCLKGATE 0x0 - AC I/O Configuration Register 4 - (OFFSET, MASK, VALUE) (0XFD080510, 0xFFFFFFFFU ,0x0A000000U) - RegMask = (DDR_PHY_ACIOCR4_LBCLKGATE_MASK | DDR_PHY_ACIOCR4_ACOECLKGATE1_MASK | DDR_PHY_ACIOCR4_ACPDRCLKGATE1_MASK | DDR_PHY_ACIOCR4_ACTECLKGATE1_MASK | DDR_PHY_ACIOCR4_CKNCLKGATE1_MASK | DDR_PHY_ACIOCR4_CKCLKGATE1_MASK | DDR_PHY_ACIOCR4_ACCLKGATE1_MASK | 0 ); + * Clock gating for Output Enable D slices [1] + * PSU_DDR_PHY_ACIOCR4_ACOECLKGATE1 0x0 - RegVal = ((0x00000000U << DDR_PHY_ACIOCR4_LBCLKGATE_SHIFT - | 0x00000000U << DDR_PHY_ACIOCR4_ACOECLKGATE1_SHIFT - | 0x00000000U << DDR_PHY_ACIOCR4_ACPDRCLKGATE1_SHIFT - | 0x00000000U << DDR_PHY_ACIOCR4_ACTECLKGATE1_SHIFT - | 0x00000002U << DDR_PHY_ACIOCR4_CKNCLKGATE1_SHIFT - | 0x00000002U << DDR_PHY_ACIOCR4_CKCLKGATE1_SHIFT - | 0x00000000U << DDR_PHY_ACIOCR4_ACCLKGATE1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_ACIOCR4_OFFSET ,0xFFFFFFFFU ,0x0A000000U); - /*############################################################################################################################ */ + * Clock gating for Power Down Receiver D slices [1] + * PSU_DDR_PHY_ACIOCR4_ACPDRCLKGATE1 0x0 - /*Register : IOVCR0 @ 0XFD080520

+ * Clock gating for Termination Enable D slices [1] + * PSU_DDR_PHY_ACIOCR4_ACTECLKGATE1 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_IOVCR0_RESERVED_31_29 0x0 + * Clock gating for CK# D slices [3:2] + * PSU_DDR_PHY_ACIOCR4_CKNCLKGATE1 0x2 - Address/command lane VREF Pad Enable - PSU_DDR_PHY_IOVCR0_ACREFPEN 0x0 + * Clock gating for CK D slices [3:2] + * PSU_DDR_PHY_ACIOCR4_CKCLKGATE1 0x2 - Address/command lane Internal VREF Enable - PSU_DDR_PHY_IOVCR0_ACREFEEN 0x0 + * Clock gating for AC D slices [47:24] + * PSU_DDR_PHY_ACIOCR4_ACCLKGATE1 0x0 - Address/command lane Single-End VREF Enable - PSU_DDR_PHY_IOVCR0_ACREFSEN 0x1 + * AC I/O Configuration Register 4 + * (OFFSET, MASK, VALUE) (0XFD080510, 0xFFFFFFFFU ,0x0A000000U) + */ + PSU_Mask_Write(DDR_PHY_ACIOCR4_OFFSET, 0xFFFFFFFFU, 0x0A000000U); +/*##################################################################### */ - Address/command lane Internal VREF Enable - PSU_DDR_PHY_IOVCR0_ACREFIEN 0x1 + /* + * Register : IOVCR0 @ 0XFD080520 - External VREF generato REFSEL range select - PSU_DDR_PHY_IOVCR0_ACREFESELRANGE 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_IOVCR0_RESERVED_31_29 0x0 - Address/command lane External VREF Select - PSU_DDR_PHY_IOVCR0_ACREFESEL 0x0 + * Address/command lane VREF Pad Enable + * PSU_DDR_PHY_IOVCR0_ACREFPEN 0x0 - Single ended VREF generator REFSEL range select - PSU_DDR_PHY_IOVCR0_ACREFSSELRANGE 0x1 + * Address/command lane Internal VREF Enable + * PSU_DDR_PHY_IOVCR0_ACREFEEN 0x0 - Address/command lane Single-End VREF Select - PSU_DDR_PHY_IOVCR0_ACREFSSEL 0x30 + * Address/command lane Single-End VREF Enable + * PSU_DDR_PHY_IOVCR0_ACREFSEN 0x1 - Internal VREF generator REFSEL ragne select - PSU_DDR_PHY_IOVCR0_ACVREFISELRANGE 0x1 + * Address/command lane Internal VREF Enable + * PSU_DDR_PHY_IOVCR0_ACREFIEN 0x1 - REFSEL Control for internal AC IOs - PSU_DDR_PHY_IOVCR0_ACVREFISEL 0x30 + * External VREF generato REFSEL range select + * PSU_DDR_PHY_IOVCR0_ACREFESELRANGE 0x0 - IO VREF Control Register 0 - (OFFSET, MASK, VALUE) (0XFD080520, 0xFFFFFFFFU ,0x0300B0B0U) - RegMask = (DDR_PHY_IOVCR0_RESERVED_31_29_MASK | DDR_PHY_IOVCR0_ACREFPEN_MASK | DDR_PHY_IOVCR0_ACREFEEN_MASK | DDR_PHY_IOVCR0_ACREFSEN_MASK | DDR_PHY_IOVCR0_ACREFIEN_MASK | DDR_PHY_IOVCR0_ACREFESELRANGE_MASK | DDR_PHY_IOVCR0_ACREFESEL_MASK | DDR_PHY_IOVCR0_ACREFSSELRANGE_MASK | DDR_PHY_IOVCR0_ACREFSSEL_MASK | DDR_PHY_IOVCR0_ACVREFISELRANGE_MASK | DDR_PHY_IOVCR0_ACVREFISEL_MASK | 0 ); + * Address/command lane External VREF Select + * PSU_DDR_PHY_IOVCR0_ACREFESEL 0x0 - RegVal = ((0x00000000U << DDR_PHY_IOVCR0_RESERVED_31_29_SHIFT - | 0x00000000U << DDR_PHY_IOVCR0_ACREFPEN_SHIFT - | 0x00000000U << DDR_PHY_IOVCR0_ACREFEEN_SHIFT - | 0x00000001U << DDR_PHY_IOVCR0_ACREFSEN_SHIFT - | 0x00000001U << DDR_PHY_IOVCR0_ACREFIEN_SHIFT - | 0x00000000U << DDR_PHY_IOVCR0_ACREFESELRANGE_SHIFT - | 0x00000000U << DDR_PHY_IOVCR0_ACREFESEL_SHIFT - | 0x00000001U << DDR_PHY_IOVCR0_ACREFSSELRANGE_SHIFT - | 0x00000030U << DDR_PHY_IOVCR0_ACREFSSEL_SHIFT - | 0x00000001U << DDR_PHY_IOVCR0_ACVREFISELRANGE_SHIFT - | 0x00000030U << DDR_PHY_IOVCR0_ACVREFISEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_IOVCR0_OFFSET ,0xFFFFFFFFU ,0x0300B0B0U); - /*############################################################################################################################ */ + * Single ended VREF generator REFSEL range select + * PSU_DDR_PHY_IOVCR0_ACREFSSELRANGE 0x1 - /*Register : VTCR0 @ 0XFD080528

+ * Address/command lane Single-End VREF Select + * PSU_DDR_PHY_IOVCR0_ACREFSSEL 0x30 - Number of ctl_clk required to meet (> 150ns) timing requirements during DRAM DQ VREF training - PSU_DDR_PHY_VTCR0_TVREF 0x7 + * Internal VREF generator REFSEL ragne select + * PSU_DDR_PHY_IOVCR0_ACVREFISELRANGE 0x1 - DRM DQ VREF training Enable - PSU_DDR_PHY_VTCR0_DVEN 0x1 + * REFSEL Control for internal AC IOs + * PSU_DDR_PHY_IOVCR0_ACVREFISEL 0x4e - Per Device Addressability Enable - PSU_DDR_PHY_VTCR0_PDAEN 0x1 + * IO VREF Control Register 0 + * (OFFSET, MASK, VALUE) (0XFD080520, 0xFFFFFFFFU ,0x0300B0CEU) + */ + PSU_Mask_Write(DDR_PHY_IOVCR0_OFFSET, 0xFFFFFFFFU, 0x0300B0CEU); +/*##################################################################### */ - Reserved. Returns zeroes on reads. - PSU_DDR_PHY_VTCR0_RESERVED_26 0x0 + /* + * Register : VTCR0 @ 0XFD080528 - VREF Word Count - PSU_DDR_PHY_VTCR0_VWCR 0x4 + * Number of ctl_clk required to meet (> 150ns) timing requirements during + * DRAM DQ VREF training + * PSU_DDR_PHY_VTCR0_TVREF 0x7 - DRAM DQ VREF step size used during DRAM VREF training - PSU_DDR_PHY_VTCR0_DVSS 0x0 + * DRM DQ VREF training Enable + * PSU_DDR_PHY_VTCR0_DVEN 0x1 - Maximum VREF limit value used during DRAM VREF training - PSU_DDR_PHY_VTCR0_DVMAX 0x32 + * Per Device Addressability Enable + * PSU_DDR_PHY_VTCR0_PDAEN 0x1 - Minimum VREF limit value used during DRAM VREF training - PSU_DDR_PHY_VTCR0_DVMIN 0x0 + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_VTCR0_RESERVED_26 0x0 - Initial DRAM DQ VREF value used during DRAM VREF training - PSU_DDR_PHY_VTCR0_DVINIT 0x19 + * VREF Word Count + * PSU_DDR_PHY_VTCR0_VWCR 0x4 - VREF Training Control Register 0 - (OFFSET, MASK, VALUE) (0XFD080528, 0xFFFFFFFFU ,0xF9032019U) - RegMask = (DDR_PHY_VTCR0_TVREF_MASK | DDR_PHY_VTCR0_DVEN_MASK | DDR_PHY_VTCR0_PDAEN_MASK | DDR_PHY_VTCR0_RESERVED_26_MASK | DDR_PHY_VTCR0_VWCR_MASK | DDR_PHY_VTCR0_DVSS_MASK | DDR_PHY_VTCR0_DVMAX_MASK | DDR_PHY_VTCR0_DVMIN_MASK | DDR_PHY_VTCR0_DVINIT_MASK | 0 ); + * DRAM DQ VREF step size used during DRAM VREF training + * PSU_DDR_PHY_VTCR0_DVSS 0x0 - RegVal = ((0x00000007U << DDR_PHY_VTCR0_TVREF_SHIFT - | 0x00000001U << DDR_PHY_VTCR0_DVEN_SHIFT - | 0x00000001U << DDR_PHY_VTCR0_PDAEN_SHIFT - | 0x00000000U << DDR_PHY_VTCR0_RESERVED_26_SHIFT - | 0x00000004U << DDR_PHY_VTCR0_VWCR_SHIFT - | 0x00000000U << DDR_PHY_VTCR0_DVSS_SHIFT - | 0x00000032U << DDR_PHY_VTCR0_DVMAX_SHIFT - | 0x00000000U << DDR_PHY_VTCR0_DVMIN_SHIFT - | 0x00000019U << DDR_PHY_VTCR0_DVINIT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_VTCR0_OFFSET ,0xFFFFFFFFU ,0xF9032019U); - /*############################################################################################################################ */ + * Maximum VREF limit value used during DRAM VREF training + * PSU_DDR_PHY_VTCR0_DVMAX 0x32 - /*Register : VTCR1 @ 0XFD08052C

+ * Minimum VREF limit value used during DRAM VREF training + * PSU_DDR_PHY_VTCR0_DVMIN 0x0 - Host VREF step size used during VREF training. The register value of N indicates step size of (N+1) - PSU_DDR_PHY_VTCR1_HVSS 0x0 + * Initial DRAM DQ VREF value used during DRAM VREF training + * PSU_DDR_PHY_VTCR0_DVINIT 0x19 - Reserved. Returns zeroes on reads. - PSU_DDR_PHY_VTCR1_RESERVED_27 0x0 + * VREF Training Control Register 0 + * (OFFSET, MASK, VALUE) (0XFD080528, 0xFFFFFFFFU ,0xF9032019U) + */ + PSU_Mask_Write(DDR_PHY_VTCR0_OFFSET, 0xFFFFFFFFU, 0xF9032019U); +/*##################################################################### */ - Maximum VREF limit value used during DRAM VREF training. - PSU_DDR_PHY_VTCR1_HVMAX 0x7f + /* + * Register : VTCR1 @ 0XFD08052C - Reserved. Returns zeroes on reads. - PSU_DDR_PHY_VTCR1_RESERVED_19 0x0 + * Host VREF step size used during VREF training. The register value of N i + * ndicates step size of (N+1) + * PSU_DDR_PHY_VTCR1_HVSS 0x0 - Minimum VREF limit value used during DRAM VREF training. - PSU_DDR_PHY_VTCR1_HVMIN 0x0 + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_VTCR1_RESERVED_27 0x0 - Reserved. Returns zeroes on reads. - PSU_DDR_PHY_VTCR1_RESERVED_11 0x0 + * Maximum VREF limit value used during DRAM VREF training. + * PSU_DDR_PHY_VTCR1_HVMAX 0x7f - Static Host Vref Rank Value - PSU_DDR_PHY_VTCR1_SHRNK 0x0 + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_VTCR1_RESERVED_19 0x0 - Static Host Vref Rank Enable - PSU_DDR_PHY_VTCR1_SHREN 0x1 + * Minimum VREF limit value used during DRAM VREF training. + * PSU_DDR_PHY_VTCR1_HVMIN 0x0 - Number of ctl_clk required to meet (> 200ns) VREF Settling timing requirements during Host IO VREF training - PSU_DDR_PHY_VTCR1_TVREFIO 0x7 + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_VTCR1_RESERVED_11 0x0 - Eye LCDL Offset value for VREF training - PSU_DDR_PHY_VTCR1_EOFF 0x0 + * Static Host Vref Rank Value + * PSU_DDR_PHY_VTCR1_SHRNK 0x0 - Number of LCDL Eye points for which VREF training is repeated - PSU_DDR_PHY_VTCR1_ENUM 0x0 + * Static Host Vref Rank Enable + * PSU_DDR_PHY_VTCR1_SHREN 0x1 - HOST (IO) internal VREF training Enable - PSU_DDR_PHY_VTCR1_HVEN 0x1 + * Number of ctl_clk required to meet (> 200ns) VREF Settling timing requir + * ements during Host IO VREF training + * PSU_DDR_PHY_VTCR1_TVREFIO 0x7 - Host IO Type Control - PSU_DDR_PHY_VTCR1_HVIO 0x1 + * Eye LCDL Offset value for VREF training + * PSU_DDR_PHY_VTCR1_EOFF 0x0 - VREF Training Control Register 1 - (OFFSET, MASK, VALUE) (0XFD08052C, 0xFFFFFFFFU ,0x07F001E3U) - RegMask = (DDR_PHY_VTCR1_HVSS_MASK | DDR_PHY_VTCR1_RESERVED_27_MASK | DDR_PHY_VTCR1_HVMAX_MASK | DDR_PHY_VTCR1_RESERVED_19_MASK | DDR_PHY_VTCR1_HVMIN_MASK | DDR_PHY_VTCR1_RESERVED_11_MASK | DDR_PHY_VTCR1_SHRNK_MASK | DDR_PHY_VTCR1_SHREN_MASK | DDR_PHY_VTCR1_TVREFIO_MASK | DDR_PHY_VTCR1_EOFF_MASK | DDR_PHY_VTCR1_ENUM_MASK | DDR_PHY_VTCR1_HVEN_MASK | DDR_PHY_VTCR1_HVIO_MASK | 0 ); + * Number of LCDL Eye points for which VREF training is repeated + * PSU_DDR_PHY_VTCR1_ENUM 0x0 - RegVal = ((0x00000000U << DDR_PHY_VTCR1_HVSS_SHIFT - | 0x00000000U << DDR_PHY_VTCR1_RESERVED_27_SHIFT - | 0x0000007FU << DDR_PHY_VTCR1_HVMAX_SHIFT - | 0x00000000U << DDR_PHY_VTCR1_RESERVED_19_SHIFT - | 0x00000000U << DDR_PHY_VTCR1_HVMIN_SHIFT - | 0x00000000U << DDR_PHY_VTCR1_RESERVED_11_SHIFT - | 0x00000000U << DDR_PHY_VTCR1_SHRNK_SHIFT - | 0x00000001U << DDR_PHY_VTCR1_SHREN_SHIFT - | 0x00000007U << DDR_PHY_VTCR1_TVREFIO_SHIFT - | 0x00000000U << DDR_PHY_VTCR1_EOFF_SHIFT - | 0x00000000U << DDR_PHY_VTCR1_ENUM_SHIFT - | 0x00000001U << DDR_PHY_VTCR1_HVEN_SHIFT - | 0x00000001U << DDR_PHY_VTCR1_HVIO_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_VTCR1_OFFSET ,0xFFFFFFFFU ,0x07F001E3U); - /*############################################################################################################################ */ + * HOST (IO) internal VREF training Enable + * PSU_DDR_PHY_VTCR1_HVEN 0x1 - /*Register : ACBDLR1 @ 0XFD080544

+ * Host IO Type Control + * PSU_DDR_PHY_VTCR1_HVIO 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR1_RESERVED_31_30 0x0 + * VREF Training Control Register 1 + * (OFFSET, MASK, VALUE) (0XFD08052C, 0xFFFFFFFFU ,0x07F001E3U) + */ + PSU_Mask_Write(DDR_PHY_VTCR1_OFFSET, 0xFFFFFFFFU, 0x07F001E3U); +/*##################################################################### */ - Delay select for the BDL on Parity. - PSU_DDR_PHY_ACBDLR1_PARBD 0x0 + /* + * Register : ACBDLR1 @ 0XFD080544 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR1_RESERVED_23_22 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR1_RESERVED_31_30 0x0 - Delay select for the BDL on Address A[16]. In DDR3 mode this pin is connected to WE. - PSU_DDR_PHY_ACBDLR1_A16BD 0x0 + * Delay select for the BDL on Parity. + * PSU_DDR_PHY_ACBDLR1_PARBD 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR1_RESERVED_15_14 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR1_RESERVED_23_22 0x0 - Delay select for the BDL on Address A[17]. When not in DDR4 modemode this pin is connected to CAS. - PSU_DDR_PHY_ACBDLR1_A17BD 0x0 + * Delay select for the BDL on Address A[16]. In DDR3 mode this pin is conn + * ected to WE. + * PSU_DDR_PHY_ACBDLR1_A16BD 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR1_RESERVED_7_6 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR1_RESERVED_15_14 0x0 - Delay select for the BDL on ACTN. - PSU_DDR_PHY_ACBDLR1_ACTBD 0x0 + * Delay select for the BDL on Address A[17]. When not in DDR4 modemode thi + * s pin is connected to CAS. + * PSU_DDR_PHY_ACBDLR1_A17BD 0x0 - AC Bit Delay Line Register 1 - (OFFSET, MASK, VALUE) (0XFD080544, 0xFFFFFFFFU ,0x00000000U) - RegMask = (DDR_PHY_ACBDLR1_RESERVED_31_30_MASK | DDR_PHY_ACBDLR1_PARBD_MASK | DDR_PHY_ACBDLR1_RESERVED_23_22_MASK | DDR_PHY_ACBDLR1_A16BD_MASK | DDR_PHY_ACBDLR1_RESERVED_15_14_MASK | DDR_PHY_ACBDLR1_A17BD_MASK | DDR_PHY_ACBDLR1_RESERVED_7_6_MASK | DDR_PHY_ACBDLR1_ACTBD_MASK | 0 ); + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR1_RESERVED_7_6 0x0 - RegVal = ((0x00000000U << DDR_PHY_ACBDLR1_RESERVED_31_30_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR1_PARBD_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR1_RESERVED_23_22_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR1_A16BD_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR1_RESERVED_15_14_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR1_A17BD_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR1_RESERVED_7_6_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR1_ACTBD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_ACBDLR1_OFFSET ,0xFFFFFFFFU ,0x00000000U); - /*############################################################################################################################ */ + * Delay select for the BDL on ACTN. + * PSU_DDR_PHY_ACBDLR1_ACTBD 0x0 - /*Register : ACBDLR2 @ 0XFD080548

+ * AC Bit Delay Line Register 1 + * (OFFSET, MASK, VALUE) (0XFD080544, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDR_PHY_ACBDLR1_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR2_RESERVED_31_30 0x0 + /* + * Register : ACBDLR2 @ 0XFD080548 - Delay select for the BDL on BG[1]. - PSU_DDR_PHY_ACBDLR2_BG1BD 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR2_RESERVED_31_30 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR2_RESERVED_23_22 0x0 + * Delay select for the BDL on BG[1]. + * PSU_DDR_PHY_ACBDLR2_BG1BD 0x0 - Delay select for the BDL on BG[0]. - PSU_DDR_PHY_ACBDLR2_BG0BD 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR2_RESERVED_23_22 0x0 - Reser.ved Return zeroes on reads. - PSU_DDR_PHY_ACBDLR2_RESERVED_15_14 0x0 + * Delay select for the BDL on BG[0]. + * PSU_DDR_PHY_ACBDLR2_BG0BD 0x0 - Delay select for the BDL on BA[1]. - PSU_DDR_PHY_ACBDLR2_BA1BD 0x0 + * Reser.ved Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR2_RESERVED_15_14 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR2_RESERVED_7_6 0x0 + * Delay select for the BDL on BA[1]. + * PSU_DDR_PHY_ACBDLR2_BA1BD 0x0 - Delay select for the BDL on BA[0]. - PSU_DDR_PHY_ACBDLR2_BA0BD 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR2_RESERVED_7_6 0x0 - AC Bit Delay Line Register 2 - (OFFSET, MASK, VALUE) (0XFD080548, 0xFFFFFFFFU ,0x00000000U) - RegMask = (DDR_PHY_ACBDLR2_RESERVED_31_30_MASK | DDR_PHY_ACBDLR2_BG1BD_MASK | DDR_PHY_ACBDLR2_RESERVED_23_22_MASK | DDR_PHY_ACBDLR2_BG0BD_MASK | DDR_PHY_ACBDLR2_RESERVED_15_14_MASK | DDR_PHY_ACBDLR2_BA1BD_MASK | DDR_PHY_ACBDLR2_RESERVED_7_6_MASK | DDR_PHY_ACBDLR2_BA0BD_MASK | 0 ); + * Delay select for the BDL on BA[0]. + * PSU_DDR_PHY_ACBDLR2_BA0BD 0x0 - RegVal = ((0x00000000U << DDR_PHY_ACBDLR2_RESERVED_31_30_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR2_BG1BD_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR2_RESERVED_23_22_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR2_BG0BD_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR2_RESERVED_15_14_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR2_BA1BD_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR2_RESERVED_7_6_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR2_BA0BD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_ACBDLR2_OFFSET ,0xFFFFFFFFU ,0x00000000U); - /*############################################################################################################################ */ + * AC Bit Delay Line Register 2 + * (OFFSET, MASK, VALUE) (0XFD080548, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDR_PHY_ACBDLR2_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ - /*Register : ACBDLR6 @ 0XFD080558

+ /* + * Register : ACBDLR6 @ 0XFD080558 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR6_RESERVED_31_30 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR6_RESERVED_31_30 0x0 - Delay select for the BDL on Address A[3]. - PSU_DDR_PHY_ACBDLR6_A03BD 0x0 + * Delay select for the BDL on Address A[3]. + * PSU_DDR_PHY_ACBDLR6_A03BD 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR6_RESERVED_23_22 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR6_RESERVED_23_22 0x0 - Delay select for the BDL on Address A[2]. - PSU_DDR_PHY_ACBDLR6_A02BD 0x0 + * Delay select for the BDL on Address A[2]. + * PSU_DDR_PHY_ACBDLR6_A02BD 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR6_RESERVED_15_14 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR6_RESERVED_15_14 0x0 - Delay select for the BDL on Address A[1]. - PSU_DDR_PHY_ACBDLR6_A01BD 0x0 + * Delay select for the BDL on Address A[1]. + * PSU_DDR_PHY_ACBDLR6_A01BD 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR6_RESERVED_7_6 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR6_RESERVED_7_6 0x0 - Delay select for the BDL on Address A[0]. - PSU_DDR_PHY_ACBDLR6_A00BD 0x0 + * Delay select for the BDL on Address A[0]. + * PSU_DDR_PHY_ACBDLR6_A00BD 0x0 - AC Bit Delay Line Register 6 - (OFFSET, MASK, VALUE) (0XFD080558, 0xFFFFFFFFU ,0x00000000U) - RegMask = (DDR_PHY_ACBDLR6_RESERVED_31_30_MASK | DDR_PHY_ACBDLR6_A03BD_MASK | DDR_PHY_ACBDLR6_RESERVED_23_22_MASK | DDR_PHY_ACBDLR6_A02BD_MASK | DDR_PHY_ACBDLR6_RESERVED_15_14_MASK | DDR_PHY_ACBDLR6_A01BD_MASK | DDR_PHY_ACBDLR6_RESERVED_7_6_MASK | DDR_PHY_ACBDLR6_A00BD_MASK | 0 ); + * AC Bit Delay Line Register 6 + * (OFFSET, MASK, VALUE) (0XFD080558, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDR_PHY_ACBDLR6_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ - RegVal = ((0x00000000U << DDR_PHY_ACBDLR6_RESERVED_31_30_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR6_A03BD_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR6_RESERVED_23_22_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR6_A02BD_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR6_RESERVED_15_14_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR6_A01BD_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR6_RESERVED_7_6_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR6_A00BD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_ACBDLR6_OFFSET ,0xFFFFFFFFU ,0x00000000U); - /*############################################################################################################################ */ + /* + * Register : ACBDLR7 @ 0XFD08055C - /*Register : ACBDLR7 @ 0XFD08055C

+ * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR7_RESERVED_31_30 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR7_RESERVED_31_30 0x0 + * Delay select for the BDL on Address A[7]. + * PSU_DDR_PHY_ACBDLR7_A07BD 0x0 - Delay select for the BDL on Address A[7]. - PSU_DDR_PHY_ACBDLR7_A07BD 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR7_RESERVED_23_22 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR7_RESERVED_23_22 0x0 + * Delay select for the BDL on Address A[6]. + * PSU_DDR_PHY_ACBDLR7_A06BD 0x0 - Delay select for the BDL on Address A[6]. - PSU_DDR_PHY_ACBDLR7_A06BD 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR7_RESERVED_15_14 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR7_RESERVED_15_14 0x0 + * Delay select for the BDL on Address A[5]. + * PSU_DDR_PHY_ACBDLR7_A05BD 0x0 - Delay select for the BDL on Address A[5]. - PSU_DDR_PHY_ACBDLR7_A05BD 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR7_RESERVED_7_6 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR7_RESERVED_7_6 0x0 + * Delay select for the BDL on Address A[4]. + * PSU_DDR_PHY_ACBDLR7_A04BD 0x0 - Delay select for the BDL on Address A[4]. - PSU_DDR_PHY_ACBDLR7_A04BD 0x0 + * AC Bit Delay Line Register 7 + * (OFFSET, MASK, VALUE) (0XFD08055C, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDR_PHY_ACBDLR7_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ - AC Bit Delay Line Register 7 - (OFFSET, MASK, VALUE) (0XFD08055C, 0xFFFFFFFFU ,0x00000000U) - RegMask = (DDR_PHY_ACBDLR7_RESERVED_31_30_MASK | DDR_PHY_ACBDLR7_A07BD_MASK | DDR_PHY_ACBDLR7_RESERVED_23_22_MASK | DDR_PHY_ACBDLR7_A06BD_MASK | DDR_PHY_ACBDLR7_RESERVED_15_14_MASK | DDR_PHY_ACBDLR7_A05BD_MASK | DDR_PHY_ACBDLR7_RESERVED_7_6_MASK | DDR_PHY_ACBDLR7_A04BD_MASK | 0 ); + /* + * Register : ACBDLR8 @ 0XFD080560 - RegVal = ((0x00000000U << DDR_PHY_ACBDLR7_RESERVED_31_30_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR7_A07BD_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR7_RESERVED_23_22_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR7_A06BD_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR7_RESERVED_15_14_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR7_A05BD_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR7_RESERVED_7_6_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR7_A04BD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_ACBDLR7_OFFSET ,0xFFFFFFFFU ,0x00000000U); - /*############################################################################################################################ */ + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR8_RESERVED_31_30 0x0 - /*Register : ACBDLR8 @ 0XFD080560

+ * Delay select for the BDL on Address A[11]. + * PSU_DDR_PHY_ACBDLR8_A11BD 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR8_RESERVED_31_30 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR8_RESERVED_23_22 0x0 - Delay select for the BDL on Address A[11]. - PSU_DDR_PHY_ACBDLR8_A11BD 0x0 + * Delay select for the BDL on Address A[10]. + * PSU_DDR_PHY_ACBDLR8_A10BD 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR8_RESERVED_23_22 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR8_RESERVED_15_14 0x0 - Delay select for the BDL on Address A[10]. - PSU_DDR_PHY_ACBDLR8_A10BD 0x0 + * Delay select for the BDL on Address A[9]. + * PSU_DDR_PHY_ACBDLR8_A09BD 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR8_RESERVED_15_14 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR8_RESERVED_7_6 0x0 - Delay select for the BDL on Address A[9]. - PSU_DDR_PHY_ACBDLR8_A09BD 0x0 + * Delay select for the BDL on Address A[8]. + * PSU_DDR_PHY_ACBDLR8_A08BD 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR8_RESERVED_7_6 0x0 + * AC Bit Delay Line Register 8 + * (OFFSET, MASK, VALUE) (0XFD080560, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDR_PHY_ACBDLR8_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ - Delay select for the BDL on Address A[8]. - PSU_DDR_PHY_ACBDLR8_A08BD 0x0 + /* + * Register : ACBDLR9 @ 0XFD080564 - AC Bit Delay Line Register 8 - (OFFSET, MASK, VALUE) (0XFD080560, 0xFFFFFFFFU ,0x00000000U) - RegMask = (DDR_PHY_ACBDLR8_RESERVED_31_30_MASK | DDR_PHY_ACBDLR8_A11BD_MASK | DDR_PHY_ACBDLR8_RESERVED_23_22_MASK | DDR_PHY_ACBDLR8_A10BD_MASK | DDR_PHY_ACBDLR8_RESERVED_15_14_MASK | DDR_PHY_ACBDLR8_A09BD_MASK | DDR_PHY_ACBDLR8_RESERVED_7_6_MASK | DDR_PHY_ACBDLR8_A08BD_MASK | 0 ); + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR9_RESERVED_31_30 0x0 - RegVal = ((0x00000000U << DDR_PHY_ACBDLR8_RESERVED_31_30_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR8_A11BD_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR8_RESERVED_23_22_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR8_A10BD_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR8_RESERVED_15_14_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR8_A09BD_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR8_RESERVED_7_6_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR8_A08BD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_ACBDLR8_OFFSET ,0xFFFFFFFFU ,0x00000000U); - /*############################################################################################################################ */ + * Delay select for the BDL on Address A[15]. + * PSU_DDR_PHY_ACBDLR9_A15BD 0x0 - /*Register : ACBDLR9 @ 0XFD080564

+ * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR9_RESERVED_23_22 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR9_RESERVED_31_30 0x0 + * Delay select for the BDL on Address A[14]. + * PSU_DDR_PHY_ACBDLR9_A14BD 0x0 - Delay select for the BDL on Address A[15]. - PSU_DDR_PHY_ACBDLR9_A15BD 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR9_RESERVED_15_14 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR9_RESERVED_23_22 0x0 + * Delay select for the BDL on Address A[13]. + * PSU_DDR_PHY_ACBDLR9_A13BD 0x0 - Delay select for the BDL on Address A[14]. - PSU_DDR_PHY_ACBDLR9_A14BD 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ACBDLR9_RESERVED_7_6 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR9_RESERVED_15_14 0x0 + * Delay select for the BDL on Address A[12]. + * PSU_DDR_PHY_ACBDLR9_A12BD 0x0 - Delay select for the BDL on Address A[13]. - PSU_DDR_PHY_ACBDLR9_A13BD 0x0 + * AC Bit Delay Line Register 9 + * (OFFSET, MASK, VALUE) (0XFD080564, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(DDR_PHY_ACBDLR9_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ACBDLR9_RESERVED_7_6 0x0 + /* + * Register : ZQCR @ 0XFD080680 - Delay select for the BDL on Address A[12]. - PSU_DDR_PHY_ACBDLR9_A12BD 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_ZQCR_RESERVED_31_26 0x0 - AC Bit Delay Line Register 9 - (OFFSET, MASK, VALUE) (0XFD080564, 0xFFFFFFFFU ,0x00000000U) - RegMask = (DDR_PHY_ACBDLR9_RESERVED_31_30_MASK | DDR_PHY_ACBDLR9_A15BD_MASK | DDR_PHY_ACBDLR9_RESERVED_23_22_MASK | DDR_PHY_ACBDLR9_A14BD_MASK | DDR_PHY_ACBDLR9_RESERVED_15_14_MASK | DDR_PHY_ACBDLR9_A13BD_MASK | DDR_PHY_ACBDLR9_RESERVED_7_6_MASK | DDR_PHY_ACBDLR9_A12BD_MASK | 0 ); + * ZQ VREF Range + * PSU_DDR_PHY_ZQCR_ZQREFISELRANGE 0x0 - RegVal = ((0x00000000U << DDR_PHY_ACBDLR9_RESERVED_31_30_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR9_A15BD_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR9_RESERVED_23_22_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR9_A14BD_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR9_RESERVED_15_14_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR9_A13BD_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR9_RESERVED_7_6_SHIFT - | 0x00000000U << DDR_PHY_ACBDLR9_A12BD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_ACBDLR9_OFFSET ,0xFFFFFFFFU ,0x00000000U); - /*############################################################################################################################ */ + * Programmable Wait for Frequency B + * PSU_DDR_PHY_ZQCR_PGWAIT_FRQB 0x11 - /*Register : ZQCR @ 0XFD080680

+ * Programmable Wait for Frequency A + * PSU_DDR_PHY_ZQCR_PGWAIT_FRQA 0x15 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_ZQCR_RESERVED_31_26 0x0 + * ZQ VREF Pad Enable + * PSU_DDR_PHY_ZQCR_ZQREFPEN 0x0 - ZQ VREF Range - PSU_DDR_PHY_ZQCR_ZQREFISELRANGE 0x0 + * ZQ Internal VREF Enable + * PSU_DDR_PHY_ZQCR_ZQREFIEN 0x1 - Programmable Wait for Frequency B - PSU_DDR_PHY_ZQCR_PGWAIT_FRQB 0x11 + * Choice of termination mode + * PSU_DDR_PHY_ZQCR_ODT_MODE 0x1 - Programmable Wait for Frequency A - PSU_DDR_PHY_ZQCR_PGWAIT_FRQA 0x11 + * Force ZCAL VT update + * PSU_DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE 0x0 - ZQ VREF Pad Enable - PSU_DDR_PHY_ZQCR_ZQREFPEN 0x0 + * IO VT Drift Limit + * PSU_DDR_PHY_ZQCR_IODLMT 0x2 - ZQ Internal VREF Enable - PSU_DDR_PHY_ZQCR_ZQREFIEN 0x1 + * Averaging algorithm enable, if set, enables averaging algorithm + * PSU_DDR_PHY_ZQCR_AVGEN 0x1 - Choice of termination mode - PSU_DDR_PHY_ZQCR_ODT_MODE 0x1 + * Maximum number of averaging rounds to be used by averaging algorithm + * PSU_DDR_PHY_ZQCR_AVGMAX 0x2 - Force ZCAL VT update - PSU_DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE 0x0 + * ZQ Calibration Type + * PSU_DDR_PHY_ZQCR_ZCALT 0x0 - IO VT Drift Limit - PSU_DDR_PHY_ZQCR_IODLMT 0x2 + * ZQ Power Down + * PSU_DDR_PHY_ZQCR_ZQPD 0x0 - Averaging algorithm enable, if set, enables averaging algorithm - PSU_DDR_PHY_ZQCR_AVGEN 0x1 + * ZQ Impedance Control Register + * (OFFSET, MASK, VALUE) (0XFD080680, 0xFFFFFFFFU ,0x008AAA58U) + */ + PSU_Mask_Write(DDR_PHY_ZQCR_OFFSET, 0xFFFFFFFFU, 0x008AAA58U); +/*##################################################################### */ - Maximum number of averaging rounds to be used by averaging algorithm - PSU_DDR_PHY_ZQCR_AVGMAX 0x2 + /* + * Register : ZQ0PR0 @ 0XFD080684 - ZQ Calibration Type - PSU_DDR_PHY_ZQCR_ZCALT 0x0 + * Pull-down drive strength ZCTRL over-ride enable + * PSU_DDR_PHY_ZQ0PR0_PD_DRV_ZDEN 0x0 - ZQ Power Down - PSU_DDR_PHY_ZQCR_ZQPD 0x0 + * Pull-up drive strength ZCTRL over-ride enable + * PSU_DDR_PHY_ZQ0PR0_PU_DRV_ZDEN 0x0 - ZQ Impedance Control Register - (OFFSET, MASK, VALUE) (0XFD080680, 0xFFFFFFFFU ,0x008A2A58U) - RegMask = (DDR_PHY_ZQCR_RESERVED_31_26_MASK | DDR_PHY_ZQCR_ZQREFISELRANGE_MASK | DDR_PHY_ZQCR_PGWAIT_FRQB_MASK | DDR_PHY_ZQCR_PGWAIT_FRQA_MASK | DDR_PHY_ZQCR_ZQREFPEN_MASK | DDR_PHY_ZQCR_ZQREFIEN_MASK | DDR_PHY_ZQCR_ODT_MODE_MASK | DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_MASK | DDR_PHY_ZQCR_IODLMT_MASK | DDR_PHY_ZQCR_AVGEN_MASK | DDR_PHY_ZQCR_AVGMAX_MASK | DDR_PHY_ZQCR_ZCALT_MASK | DDR_PHY_ZQCR_ZQPD_MASK | 0 ); + * Pull-down termination ZCTRL over-ride enable + * PSU_DDR_PHY_ZQ0PR0_PD_ODT_ZDEN 0x0 - RegVal = ((0x00000000U << DDR_PHY_ZQCR_RESERVED_31_26_SHIFT - | 0x00000000U << DDR_PHY_ZQCR_ZQREFISELRANGE_SHIFT - | 0x00000011U << DDR_PHY_ZQCR_PGWAIT_FRQB_SHIFT - | 0x00000011U << DDR_PHY_ZQCR_PGWAIT_FRQA_SHIFT - | 0x00000000U << DDR_PHY_ZQCR_ZQREFPEN_SHIFT - | 0x00000001U << DDR_PHY_ZQCR_ZQREFIEN_SHIFT - | 0x00000001U << DDR_PHY_ZQCR_ODT_MODE_SHIFT - | 0x00000000U << DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_SHIFT - | 0x00000002U << DDR_PHY_ZQCR_IODLMT_SHIFT - | 0x00000001U << DDR_PHY_ZQCR_AVGEN_SHIFT - | 0x00000002U << DDR_PHY_ZQCR_AVGMAX_SHIFT - | 0x00000000U << DDR_PHY_ZQCR_ZCALT_SHIFT - | 0x00000000U << DDR_PHY_ZQCR_ZQPD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_ZQCR_OFFSET ,0xFFFFFFFFU ,0x008A2A58U); - /*############################################################################################################################ */ + * Pull-up termination ZCTRL over-ride enable + * PSU_DDR_PHY_ZQ0PR0_PU_ODT_ZDEN 0x0 - /*Register : ZQ0PR0 @ 0XFD080684

+ * Calibration segment bypass + * PSU_DDR_PHY_ZQ0PR0_ZSEGBYP 0x0 - Pull-down drive strength ZCTRL over-ride enable - PSU_DDR_PHY_ZQ0PR0_PD_DRV_ZDEN 0x0 + * VREF latch mode controls the mode in which the ZLE pin of the PVREF cell + * is driven by the PUB + * PSU_DDR_PHY_ZQ0PR0_ZLE_MODE 0x0 - Pull-up drive strength ZCTRL over-ride enable - PSU_DDR_PHY_ZQ0PR0_PU_DRV_ZDEN 0x0 + * Termination adjustment + * PSU_DDR_PHY_ZQ0PR0_ODT_ADJUST 0x0 - Pull-down termination ZCTRL over-ride enable - PSU_DDR_PHY_ZQ0PR0_PD_ODT_ZDEN 0x0 + * Pulldown drive strength adjustment + * PSU_DDR_PHY_ZQ0PR0_PD_DRV_ADJUST 0x0 - Pull-up termination ZCTRL over-ride enable - PSU_DDR_PHY_ZQ0PR0_PU_ODT_ZDEN 0x0 + * Pullup drive strength adjustment + * PSU_DDR_PHY_ZQ0PR0_PU_DRV_ADJUST 0x0 - Calibration segment bypass - PSU_DDR_PHY_ZQ0PR0_ZSEGBYP 0x0 + * DRAM Impedance Divide Ratio + * PSU_DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT 0x7 - VREF latch mode controls the mode in which the ZLE pin of the PVREF cell is driven by the PUB - PSU_DDR_PHY_ZQ0PR0_ZLE_MODE 0x0 + * HOST Impedance Divide Ratio + * PSU_DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT 0x9 - Termination adjustment - PSU_DDR_PHY_ZQ0PR0_ODT_ADJUST 0x0 + * Impedance Divide Ratio (pulldown drive calibration during asymmetric dri + * ve strength calibration) + * PSU_DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD 0xd - Pulldown drive strength adjustment - PSU_DDR_PHY_ZQ0PR0_PD_DRV_ADJUST 0x0 + * Impedance Divide Ratio (pullup drive calibration during asymmetric drive + * strength calibration) + * PSU_DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU 0xd - Pullup drive strength adjustment - PSU_DDR_PHY_ZQ0PR0_PU_DRV_ADJUST 0x0 + * ZQ n Impedance Control Program Register 0 + * (OFFSET, MASK, VALUE) (0XFD080684, 0xFFFFFFFFU ,0x000079DDU) + */ + PSU_Mask_Write(DDR_PHY_ZQ0PR0_OFFSET, 0xFFFFFFFFU, 0x000079DDU); +/*##################################################################### */ - DRAM Impedance Divide Ratio - PSU_DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT 0x7 + /* + * Register : ZQ0OR0 @ 0XFD080694 - HOST Impedance Divide Ratio - PSU_DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT 0x7 + * Reserved. Return zeros on reads. + * PSU_DDR_PHY_ZQ0OR0_RESERVED_31_26 0x0 - Impedance Divide Ratio (pulldown drive calibration during asymmetric drive strength calibration) - PSU_DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD 0xd + * Override value for the pull-up output impedance + * PSU_DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD 0x1e1 - Impedance Divide Ratio (pullup drive calibration during asymmetric drive strength calibration) - PSU_DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU 0xd + * Reserved. Return zeros on reads. + * PSU_DDR_PHY_ZQ0OR0_RESERVED_15_10 0x0 - ZQ n Impedance Control Program Register 0 - (OFFSET, MASK, VALUE) (0XFD080684, 0xFFFFFFFFU ,0x000077DDU) - RegMask = (DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_MASK | DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_MASK | DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_MASK | DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_MASK | DDR_PHY_ZQ0PR0_ZSEGBYP_MASK | DDR_PHY_ZQ0PR0_ZLE_MODE_MASK | DDR_PHY_ZQ0PR0_ODT_ADJUST_MASK | DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_MASK | DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_MASK | DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_MASK | DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_MASK | DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_MASK | DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_MASK | 0 ); + * Override value for the pull-down output impedance + * PSU_DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD 0x210 - RegVal = ((0x00000000U << DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_SHIFT - | 0x00000000U << DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_SHIFT - | 0x00000000U << DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_SHIFT - | 0x00000000U << DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_SHIFT - | 0x00000000U << DDR_PHY_ZQ0PR0_ZSEGBYP_SHIFT - | 0x00000000U << DDR_PHY_ZQ0PR0_ZLE_MODE_SHIFT - | 0x00000000U << DDR_PHY_ZQ0PR0_ODT_ADJUST_SHIFT - | 0x00000000U << DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_SHIFT - | 0x00000000U << DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_SHIFT - | 0x00000007U << DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_SHIFT - | 0x00000007U << DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_SHIFT - | 0x0000000DU << DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_SHIFT - | 0x0000000DU << DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_ZQ0PR0_OFFSET ,0xFFFFFFFFU ,0x000077DDU); - /*############################################################################################################################ */ + * ZQ n Impedance Control Override Data Register 0 + * (OFFSET, MASK, VALUE) (0XFD080694, 0xFFFFFFFFU ,0x01E10210U) + */ + PSU_Mask_Write(DDR_PHY_ZQ0OR0_OFFSET, 0xFFFFFFFFU, 0x01E10210U); +/*##################################################################### */ - /*Register : ZQ0OR0 @ 0XFD080694

+ /* + * Register : ZQ0OR1 @ 0XFD080698 - Reserved. Return zeros on reads. - PSU_DDR_PHY_ZQ0OR0_RESERVED_31_26 0x0 + * Reserved. Return zeros on reads. + * PSU_DDR_PHY_ZQ0OR1_RESERVED_31_26 0x0 - Override value for the pull-up output impedance - PSU_DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD 0x1e1 + * Override value for the pull-up termination + * PSU_DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD 0x1e1 - Reserved. Return zeros on reads. - PSU_DDR_PHY_ZQ0OR0_RESERVED_15_10 0x0 + * Reserved. Return zeros on reads. + * PSU_DDR_PHY_ZQ0OR1_RESERVED_15_10 0x0 - Override value for the pull-down output impedance - PSU_DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD 0x210 + * Override value for the pull-down termination + * PSU_DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD 0x0 - ZQ n Impedance Control Override Data Register 0 - (OFFSET, MASK, VALUE) (0XFD080694, 0xFFFFFFFFU ,0x01E10210U) - RegMask = (DDR_PHY_ZQ0OR0_RESERVED_31_26_MASK | DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_MASK | DDR_PHY_ZQ0OR0_RESERVED_15_10_MASK | DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_MASK | 0 ); - - RegVal = ((0x00000000U << DDR_PHY_ZQ0OR0_RESERVED_31_26_SHIFT - | 0x000001E1U << DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_SHIFT - | 0x00000000U << DDR_PHY_ZQ0OR0_RESERVED_15_10_SHIFT - | 0x00000210U << DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_ZQ0OR0_OFFSET ,0xFFFFFFFFU ,0x01E10210U); - /*############################################################################################################################ */ + * ZQ n Impedance Control Override Data Register 1 + * (OFFSET, MASK, VALUE) (0XFD080698, 0xFFFFFFFFU ,0x01E10000U) + */ + PSU_Mask_Write(DDR_PHY_ZQ0OR1_OFFSET, 0xFFFFFFFFU, 0x01E10000U); +/*##################################################################### */ - /*Register : ZQ0OR1 @ 0XFD080698

+ /* + * Register : ZQ1PR0 @ 0XFD0806A4 - Reserved. Return zeros on reads. - PSU_DDR_PHY_ZQ0OR1_RESERVED_31_26 0x0 + * Pull-down drive strength ZCTRL over-ride enable + * PSU_DDR_PHY_ZQ1PR0_PD_DRV_ZDEN 0x0 - Override value for the pull-up termination - PSU_DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD 0x1e1 + * Pull-up drive strength ZCTRL over-ride enable + * PSU_DDR_PHY_ZQ1PR0_PU_DRV_ZDEN 0x0 - Reserved. Return zeros on reads. - PSU_DDR_PHY_ZQ0OR1_RESERVED_15_10 0x0 + * Pull-down termination ZCTRL over-ride enable + * PSU_DDR_PHY_ZQ1PR0_PD_ODT_ZDEN 0x0 - Override value for the pull-down termination - PSU_DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD 0x0 + * Pull-up termination ZCTRL over-ride enable + * PSU_DDR_PHY_ZQ1PR0_PU_ODT_ZDEN 0x0 - ZQ n Impedance Control Override Data Register 1 - (OFFSET, MASK, VALUE) (0XFD080698, 0xFFFFFFFFU ,0x01E10000U) - RegMask = (DDR_PHY_ZQ0OR1_RESERVED_31_26_MASK | DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_MASK | DDR_PHY_ZQ0OR1_RESERVED_15_10_MASK | DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_MASK | 0 ); + * Calibration segment bypass + * PSU_DDR_PHY_ZQ1PR0_ZSEGBYP 0x0 - RegVal = ((0x00000000U << DDR_PHY_ZQ0OR1_RESERVED_31_26_SHIFT - | 0x000001E1U << DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_SHIFT - | 0x00000000U << DDR_PHY_ZQ0OR1_RESERVED_15_10_SHIFT - | 0x00000000U << DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_ZQ0OR1_OFFSET ,0xFFFFFFFFU ,0x01E10000U); - /*############################################################################################################################ */ + * VREF latch mode controls the mode in which the ZLE pin of the PVREF cell + * is driven by the PUB + * PSU_DDR_PHY_ZQ1PR0_ZLE_MODE 0x0 - /*Register : ZQ1PR0 @ 0XFD0806A4

+ * Termination adjustment + * PSU_DDR_PHY_ZQ1PR0_ODT_ADJUST 0x0 - Pull-down drive strength ZCTRL over-ride enable - PSU_DDR_PHY_ZQ1PR0_PD_DRV_ZDEN 0x0 + * Pulldown drive strength adjustment + * PSU_DDR_PHY_ZQ1PR0_PD_DRV_ADJUST 0x1 - Pull-up drive strength ZCTRL over-ride enable - PSU_DDR_PHY_ZQ1PR0_PU_DRV_ZDEN 0x0 + * Pullup drive strength adjustment + * PSU_DDR_PHY_ZQ1PR0_PU_DRV_ADJUST 0x0 - Pull-down termination ZCTRL over-ride enable - PSU_DDR_PHY_ZQ1PR0_PD_ODT_ZDEN 0x0 + * DRAM Impedance Divide Ratio + * PSU_DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT 0x7 - Pull-up termination ZCTRL over-ride enable - PSU_DDR_PHY_ZQ1PR0_PU_ODT_ZDEN 0x0 + * HOST Impedance Divide Ratio + * PSU_DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT 0xb - Calibration segment bypass - PSU_DDR_PHY_ZQ1PR0_ZSEGBYP 0x0 + * Impedance Divide Ratio (pulldown drive calibration during asymmetric dri + * ve strength calibration) + * PSU_DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD 0xd - VREF latch mode controls the mode in which the ZLE pin of the PVREF cell is driven by the PUB - PSU_DDR_PHY_ZQ1PR0_ZLE_MODE 0x0 + * Impedance Divide Ratio (pullup drive calibration during asymmetric drive + * strength calibration) + * PSU_DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU 0xb - Termination adjustment - PSU_DDR_PHY_ZQ1PR0_ODT_ADJUST 0x0 + * ZQ n Impedance Control Program Register 0 + * (OFFSET, MASK, VALUE) (0XFD0806A4, 0xFFFFFFFFU ,0x00087BDBU) + */ + PSU_Mask_Write(DDR_PHY_ZQ1PR0_OFFSET, 0xFFFFFFFFU, 0x00087BDBU); +/*##################################################################### */ - Pulldown drive strength adjustment - PSU_DDR_PHY_ZQ1PR0_PD_DRV_ADJUST 0x1 + /* + * Register : DX0GCR0 @ 0XFD080700 - Pullup drive strength adjustment - PSU_DDR_PHY_ZQ1PR0_PU_DRV_ADJUST 0x0 + * Calibration Bypass + * PSU_DDR_PHY_DX0GCR0_CALBYP 0x0 - DRAM Impedance Divide Ratio - PSU_DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT 0x7 + * Master Delay Line Enable + * PSU_DDR_PHY_DX0GCR0_MDLEN 0x1 - HOST Impedance Divide Ratio - PSU_DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT 0xb + * Configurable ODT(TE) Phase Shift + * PSU_DDR_PHY_DX0GCR0_CODTSHFT 0x0 - Impedance Divide Ratio (pulldown drive calibration during asymmetric drive strength calibration) - PSU_DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD 0xd + * DQS Duty Cycle Correction + * PSU_DDR_PHY_DX0GCR0_DQSDCC 0x0 - Impedance Divide Ratio (pullup drive calibration during asymmetric drive strength calibration) - PSU_DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU 0xb + * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY + * PSU_DDR_PHY_DX0GCR0_RDDLY 0x8 - ZQ n Impedance Control Program Register 0 - (OFFSET, MASK, VALUE) (0XFD0806A4, 0xFFFFFFFFU ,0x00087BDBU) - RegMask = (DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_MASK | DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_MASK | DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_MASK | DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_MASK | DDR_PHY_ZQ1PR0_ZSEGBYP_MASK | DDR_PHY_ZQ1PR0_ZLE_MODE_MASK | DDR_PHY_ZQ1PR0_ODT_ADJUST_MASK | DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_MASK | DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_MASK | DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_MASK | DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_MASK | DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_MASK | DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_MASK | 0 ); + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX0GCR0_RESERVED_19_14 0x0 - RegVal = ((0x00000000U << DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_SHIFT - | 0x00000000U << DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_SHIFT - | 0x00000000U << DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_SHIFT - | 0x00000000U << DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_SHIFT - | 0x00000000U << DDR_PHY_ZQ1PR0_ZSEGBYP_SHIFT - | 0x00000000U << DDR_PHY_ZQ1PR0_ZLE_MODE_SHIFT - | 0x00000000U << DDR_PHY_ZQ1PR0_ODT_ADJUST_SHIFT - | 0x00000001U << DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_SHIFT - | 0x00000000U << DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_SHIFT - | 0x00000007U << DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_SHIFT - | 0x0000000BU << DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_SHIFT - | 0x0000000DU << DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_SHIFT - | 0x0000000BU << DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_ZQ1PR0_OFFSET ,0xFFFFFFFFU ,0x00087BDBU); - /*############################################################################################################################ */ + * DQSNSE Power Down Receiver + * PSU_DDR_PHY_DX0GCR0_DQSNSEPDR 0x0 - /*Register : DX0GCR0 @ 0XFD080700

+ * DQSSE Power Down Receiver + * PSU_DDR_PHY_DX0GCR0_DQSSEPDR 0x0 - Calibration Bypass - PSU_DDR_PHY_DX0GCR0_CALBYP 0x0 + * RTT On Additive Latency + * PSU_DDR_PHY_DX0GCR0_RTTOAL 0x0 - Master Delay Line Enable - PSU_DDR_PHY_DX0GCR0_MDLEN 0x1 + * RTT Output Hold + * PSU_DDR_PHY_DX0GCR0_RTTOH 0x3 - Configurable ODT(TE) Phase Shift - PSU_DDR_PHY_DX0GCR0_CODTSHFT 0x0 + * Configurable PDR Phase Shift + * PSU_DDR_PHY_DX0GCR0_CPDRSHFT 0x0 - DQS Duty Cycle Correction - PSU_DDR_PHY_DX0GCR0_DQSDCC 0x0 + * DQSR Power Down + * PSU_DDR_PHY_DX0GCR0_DQSRPD 0x0 - Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY - PSU_DDR_PHY_DX0GCR0_RDDLY 0x8 + * DQSG Power Down Receiver + * PSU_DDR_PHY_DX0GCR0_DQSGPDR 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX0GCR0_RESERVED_19_14 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX0GCR0_RESERVED_4 0x0 - DQSNSE Power Down Receiver - PSU_DDR_PHY_DX0GCR0_DQSNSEPDR 0x0 + * DQSG On-Die Termination + * PSU_DDR_PHY_DX0GCR0_DQSGODT 0x0 - DQSSE Power Down Receiver - PSU_DDR_PHY_DX0GCR0_DQSSEPDR 0x0 + * DQSG Output Enable + * PSU_DDR_PHY_DX0GCR0_DQSGOE 0x1 - RTT On Additive Latency - PSU_DDR_PHY_DX0GCR0_RTTOAL 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX0GCR0_RESERVED_1_0 0x0 - RTT Output Hold - PSU_DDR_PHY_DX0GCR0_RTTOH 0x3 + * DATX8 n General Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD080700, 0xFFFFFFFFU ,0x40800604U) + */ + PSU_Mask_Write(DDR_PHY_DX0GCR0_OFFSET, 0xFFFFFFFFU, 0x40800604U); +/*##################################################################### */ - Configurable PDR Phase Shift - PSU_DDR_PHY_DX0GCR0_CPDRSHFT 0x0 + /* + * Register : DX0GCR4 @ 0XFD080710 - DQSR Power Down - PSU_DDR_PHY_DX0GCR0_DQSRPD 0x0 + * Byte lane VREF IOM (Used only by D4MU IOs) + * PSU_DDR_PHY_DX0GCR4_RESERVED_31_29 0x0 - DQSG Power Down Receiver - PSU_DDR_PHY_DX0GCR0_DQSGPDR 0x0 + * Byte Lane VREF Pad Enable + * PSU_DDR_PHY_DX0GCR4_DXREFPEN 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX0GCR0_RESERVED_4 0x0 + * Byte Lane Internal VREF Enable + * PSU_DDR_PHY_DX0GCR4_DXREFEEN 0x3 - DQSG On-Die Termination - PSU_DDR_PHY_DX0GCR0_DQSGODT 0x0 + * Byte Lane Single-End VREF Enable + * PSU_DDR_PHY_DX0GCR4_DXREFSEN 0x1 - DQSG Output Enable - PSU_DDR_PHY_DX0GCR0_DQSGOE 0x1 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX0GCR4_RESERVED_24 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX0GCR0_RESERVED_1_0 0x0 + * External VREF generator REFSEL range select + * PSU_DDR_PHY_DX0GCR4_DXREFESELRANGE 0x0 - DATX8 n General Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD080700, 0xFFFFFFFFU ,0x40800604U) - RegMask = (DDR_PHY_DX0GCR0_CALBYP_MASK | DDR_PHY_DX0GCR0_MDLEN_MASK | DDR_PHY_DX0GCR0_CODTSHFT_MASK | DDR_PHY_DX0GCR0_DQSDCC_MASK | DDR_PHY_DX0GCR0_RDDLY_MASK | DDR_PHY_DX0GCR0_RESERVED_19_14_MASK | DDR_PHY_DX0GCR0_DQSNSEPDR_MASK | DDR_PHY_DX0GCR0_DQSSEPDR_MASK | DDR_PHY_DX0GCR0_RTTOAL_MASK | DDR_PHY_DX0GCR0_RTTOH_MASK | DDR_PHY_DX0GCR0_CPDRSHFT_MASK | DDR_PHY_DX0GCR0_DQSRPD_MASK | DDR_PHY_DX0GCR0_DQSGPDR_MASK | DDR_PHY_DX0GCR0_RESERVED_4_MASK | DDR_PHY_DX0GCR0_DQSGODT_MASK | DDR_PHY_DX0GCR0_DQSGOE_MASK | DDR_PHY_DX0GCR0_RESERVED_1_0_MASK | 0 ); + * Byte Lane External VREF Select + * PSU_DDR_PHY_DX0GCR4_DXREFESEL 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX0GCR0_CALBYP_SHIFT - | 0x00000001U << DDR_PHY_DX0GCR0_MDLEN_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR0_CODTSHFT_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR0_DQSDCC_SHIFT - | 0x00000008U << DDR_PHY_DX0GCR0_RDDLY_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR0_RESERVED_19_14_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR0_DQSNSEPDR_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR0_DQSSEPDR_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR0_RTTOAL_SHIFT - | 0x00000003U << DDR_PHY_DX0GCR0_RTTOH_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR0_CPDRSHFT_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR0_DQSRPD_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR0_DQSGPDR_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR0_RESERVED_4_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR0_DQSGODT_SHIFT - | 0x00000001U << DDR_PHY_DX0GCR0_DQSGOE_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR0_RESERVED_1_0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX0GCR0_OFFSET ,0xFFFFFFFFU ,0x40800604U); - /*############################################################################################################################ */ - - /*Register : DX0GCR4 @ 0XFD080710

- - Byte lane VREF IOM (Used only by D4MU IOs) - PSU_DDR_PHY_DX0GCR4_RESERVED_31_29 0x0 + * Single ended VREF generator REFSEL range select + * PSU_DDR_PHY_DX0GCR4_DXREFSSELRANGE 0x1 - Byte Lane VREF Pad Enable - PSU_DDR_PHY_DX0GCR4_DXREFPEN 0x0 + * Byte Lane Single-End VREF Select + * PSU_DDR_PHY_DX0GCR4_DXREFSSEL 0x30 - Byte Lane Internal VREF Enable - PSU_DDR_PHY_DX0GCR4_DXREFEEN 0x3 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX0GCR4_RESERVED_7_6 0x0 - Byte Lane Single-End VREF Enable - PSU_DDR_PHY_DX0GCR4_DXREFSEN 0x1 + * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX0GCR4_DXREFIEN 0xf - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX0GCR4_RESERVED_24 0x0 + * VRMON control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX0GCR4_DXREFIMON 0x0 - External VREF generator REFSEL range select - PSU_DDR_PHY_DX0GCR4_DXREFESELRANGE 0x0 + * DATX8 n General Configuration Register 4 + * (OFFSET, MASK, VALUE) (0XFD080710, 0xFFFFFFFFU ,0x0E00B03CU) + */ + PSU_Mask_Write(DDR_PHY_DX0GCR4_OFFSET, 0xFFFFFFFFU, 0x0E00B03CU); +/*##################################################################### */ - Byte Lane External VREF Select - PSU_DDR_PHY_DX0GCR4_DXREFESEL 0x0 + /* + * Register : DX0GCR5 @ 0XFD080714 - Single ended VREF generator REFSEL range select - PSU_DDR_PHY_DX0GCR4_DXREFSSELRANGE 0x1 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX0GCR5_RESERVED_31 0x0 - Byte Lane Single-End VREF Select - PSU_DDR_PHY_DX0GCR4_DXREFSSEL 0x30 + * Byte Lane internal VREF Select for Rank 3 + * PSU_DDR_PHY_DX0GCR5_DXREFISELR3 0x9 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX0GCR4_RESERVED_7_6 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX0GCR5_RESERVED_23 0x0 - VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. - PSU_DDR_PHY_DX0GCR4_DXREFIEN 0xf + * Byte Lane internal VREF Select for Rank 2 + * PSU_DDR_PHY_DX0GCR5_DXREFISELR2 0x9 - VRMON control for DQ IO (Single Ended) buffers of a byte lane. - PSU_DDR_PHY_DX0GCR4_DXREFIMON 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX0GCR5_RESERVED_15 0x0 - DATX8 n General Configuration Register 4 - (OFFSET, MASK, VALUE) (0XFD080710, 0xFFFFFFFFU ,0x0E00B03CU) - RegMask = (DDR_PHY_DX0GCR4_RESERVED_31_29_MASK | DDR_PHY_DX0GCR4_DXREFPEN_MASK | DDR_PHY_DX0GCR4_DXREFEEN_MASK | DDR_PHY_DX0GCR4_DXREFSEN_MASK | DDR_PHY_DX0GCR4_RESERVED_24_MASK | DDR_PHY_DX0GCR4_DXREFESELRANGE_MASK | DDR_PHY_DX0GCR4_DXREFESEL_MASK | DDR_PHY_DX0GCR4_DXREFSSELRANGE_MASK | DDR_PHY_DX0GCR4_DXREFSSEL_MASK | DDR_PHY_DX0GCR4_RESERVED_7_6_MASK | DDR_PHY_DX0GCR4_DXREFIEN_MASK | DDR_PHY_DX0GCR4_DXREFIMON_MASK | 0 ); + * Byte Lane internal VREF Select for Rank 1 + * PSU_DDR_PHY_DX0GCR5_DXREFISELR1 0x55 - RegVal = ((0x00000000U << DDR_PHY_DX0GCR4_RESERVED_31_29_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR4_DXREFPEN_SHIFT - | 0x00000003U << DDR_PHY_DX0GCR4_DXREFEEN_SHIFT - | 0x00000001U << DDR_PHY_DX0GCR4_DXREFSEN_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR4_RESERVED_24_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR4_DXREFESELRANGE_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR4_DXREFESEL_SHIFT - | 0x00000001U << DDR_PHY_DX0GCR4_DXREFSSELRANGE_SHIFT - | 0x00000030U << DDR_PHY_DX0GCR4_DXREFSSEL_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR4_RESERVED_7_6_SHIFT - | 0x0000000FU << DDR_PHY_DX0GCR4_DXREFIEN_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR4_DXREFIMON_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX0GCR4_OFFSET ,0xFFFFFFFFU ,0x0E00B03CU); - /*############################################################################################################################ */ + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX0GCR5_RESERVED_7 0x0 - /*Register : DX0GCR5 @ 0XFD080714

+ * Byte Lane internal VREF Select for Rank 0 + * PSU_DDR_PHY_DX0GCR5_DXREFISELR0 0x55 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX0GCR5_RESERVED_31 0x0 + * DATX8 n General Configuration Register 5 + * (OFFSET, MASK, VALUE) (0XFD080714, 0xFFFFFFFFU ,0x09095555U) + */ + PSU_Mask_Write(DDR_PHY_DX0GCR5_OFFSET, 0xFFFFFFFFU, 0x09095555U); +/*##################################################################### */ - Byte Lane internal VREF Select for Rank 3 - PSU_DDR_PHY_DX0GCR5_DXREFISELR3 0x9 - - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX0GCR5_RESERVED_23 0x0 - - Byte Lane internal VREF Select for Rank 2 - PSU_DDR_PHY_DX0GCR5_DXREFISELR2 0x9 - - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX0GCR5_RESERVED_15 0x0 - - Byte Lane internal VREF Select for Rank 1 - PSU_DDR_PHY_DX0GCR5_DXREFISELR1 0x4f - - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX0GCR5_RESERVED_7 0x0 - - Byte Lane internal VREF Select for Rank 0 - PSU_DDR_PHY_DX0GCR5_DXREFISELR0 0x4f + /* + * Register : DX0GCR6 @ 0XFD080718 - DATX8 n General Configuration Register 5 - (OFFSET, MASK, VALUE) (0XFD080714, 0xFFFFFFFFU ,0x09094F4FU) - RegMask = (DDR_PHY_DX0GCR5_RESERVED_31_MASK | DDR_PHY_DX0GCR5_DXREFISELR3_MASK | DDR_PHY_DX0GCR5_RESERVED_23_MASK | DDR_PHY_DX0GCR5_DXREFISELR2_MASK | DDR_PHY_DX0GCR5_RESERVED_15_MASK | DDR_PHY_DX0GCR5_DXREFISELR1_MASK | DDR_PHY_DX0GCR5_RESERVED_7_MASK | DDR_PHY_DX0GCR5_DXREFISELR0_MASK | 0 ); + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX0GCR6_RESERVED_31_30 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX0GCR5_RESERVED_31_SHIFT - | 0x00000009U << DDR_PHY_DX0GCR5_DXREFISELR3_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR5_RESERVED_23_SHIFT - | 0x00000009U << DDR_PHY_DX0GCR5_DXREFISELR2_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR5_RESERVED_15_SHIFT - | 0x0000004FU << DDR_PHY_DX0GCR5_DXREFISELR1_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR5_RESERVED_7_SHIFT - | 0x0000004FU << DDR_PHY_DX0GCR5_DXREFISELR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX0GCR5_OFFSET ,0xFFFFFFFFU ,0x09094F4FU); - /*############################################################################################################################ */ + * DRAM DQ VREF Select for Rank3 + * PSU_DDR_PHY_DX0GCR6_DXDQVREFR3 0x9 - /*Register : DX0GCR6 @ 0XFD080718

+ * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX0GCR6_RESERVED_23_22 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX0GCR6_RESERVED_31_30 0x0 + * DRAM DQ VREF Select for Rank2 + * PSU_DDR_PHY_DX0GCR6_DXDQVREFR2 0x9 - DRAM DQ VREF Select for Rank3 - PSU_DDR_PHY_DX0GCR6_DXDQVREFR3 0x9 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX0GCR6_RESERVED_15_14 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX0GCR6_RESERVED_23_22 0x0 + * DRAM DQ VREF Select for Rank1 + * PSU_DDR_PHY_DX0GCR6_DXDQVREFR1 0x2b - DRAM DQ VREF Select for Rank2 - PSU_DDR_PHY_DX0GCR6_DXDQVREFR2 0x9 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX0GCR6_RESERVED_7_6 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX0GCR6_RESERVED_15_14 0x0 + * DRAM DQ VREF Select for Rank0 + * PSU_DDR_PHY_DX0GCR6_DXDQVREFR0 0x2b - DRAM DQ VREF Select for Rank1 - PSU_DDR_PHY_DX0GCR6_DXDQVREFR1 0x2b + * DATX8 n General Configuration Register 6 + * (OFFSET, MASK, VALUE) (0XFD080718, 0xFFFFFFFFU ,0x09092B2BU) + */ + PSU_Mask_Write(DDR_PHY_DX0GCR6_OFFSET, 0xFFFFFFFFU, 0x09092B2BU); +/*##################################################################### */ - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX0GCR6_RESERVED_7_6 0x0 + /* + * Register : DX1GCR0 @ 0XFD080800 - DRAM DQ VREF Select for Rank0 - PSU_DDR_PHY_DX0GCR6_DXDQVREFR0 0x2b + * Calibration Bypass + * PSU_DDR_PHY_DX1GCR0_CALBYP 0x0 - DATX8 n General Configuration Register 6 - (OFFSET, MASK, VALUE) (0XFD080718, 0xFFFFFFFFU ,0x09092B2BU) - RegMask = (DDR_PHY_DX0GCR6_RESERVED_31_30_MASK | DDR_PHY_DX0GCR6_DXDQVREFR3_MASK | DDR_PHY_DX0GCR6_RESERVED_23_22_MASK | DDR_PHY_DX0GCR6_DXDQVREFR2_MASK | DDR_PHY_DX0GCR6_RESERVED_15_14_MASK | DDR_PHY_DX0GCR6_DXDQVREFR1_MASK | DDR_PHY_DX0GCR6_RESERVED_7_6_MASK | DDR_PHY_DX0GCR6_DXDQVREFR0_MASK | 0 ); + * Master Delay Line Enable + * PSU_DDR_PHY_DX1GCR0_MDLEN 0x1 - RegVal = ((0x00000000U << DDR_PHY_DX0GCR6_RESERVED_31_30_SHIFT - | 0x00000009U << DDR_PHY_DX0GCR6_DXDQVREFR3_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR6_RESERVED_23_22_SHIFT - | 0x00000009U << DDR_PHY_DX0GCR6_DXDQVREFR2_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR6_RESERVED_15_14_SHIFT - | 0x0000002BU << DDR_PHY_DX0GCR6_DXDQVREFR1_SHIFT - | 0x00000000U << DDR_PHY_DX0GCR6_RESERVED_7_6_SHIFT - | 0x0000002BU << DDR_PHY_DX0GCR6_DXDQVREFR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX0GCR6_OFFSET ,0xFFFFFFFFU ,0x09092B2BU); - /*############################################################################################################################ */ + * Configurable ODT(TE) Phase Shift + * PSU_DDR_PHY_DX1GCR0_CODTSHFT 0x0 - /*Register : DX0LCDLR2 @ 0XFD080788

+ * DQS Duty Cycle Correction + * PSU_DDR_PHY_DX1GCR0_DQSDCC 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX0LCDLR2_RESERVED_31_25 0x0 + * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY + * PSU_DDR_PHY_DX1GCR0_RDDLY 0x8 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX0LCDLR2_RESERVED_24_16 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX1GCR0_RESERVED_19_14 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX0LCDLR2_RESERVED_15_9 0x0 + * DQSNSE Power Down Receiver + * PSU_DDR_PHY_DX1GCR0_DQSNSEPDR 0x0 - Read DQS Gating Delay - PSU_DDR_PHY_DX0LCDLR2_DQSGD 0x0 + * DQSSE Power Down Receiver + * PSU_DDR_PHY_DX1GCR0_DQSSEPDR 0x0 - DATX8 n Local Calibrated Delay Line Register 2 - (OFFSET, MASK, VALUE) (0XFD080788, 0xFFFFFFFFU ,0x00000000U) - RegMask = (DDR_PHY_DX0LCDLR2_RESERVED_31_25_MASK | DDR_PHY_DX0LCDLR2_RESERVED_24_16_MASK | DDR_PHY_DX0LCDLR2_RESERVED_15_9_MASK | DDR_PHY_DX0LCDLR2_DQSGD_MASK | 0 ); + * RTT On Additive Latency + * PSU_DDR_PHY_DX1GCR0_RTTOAL 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX0LCDLR2_RESERVED_31_25_SHIFT - | 0x00000000U << DDR_PHY_DX0LCDLR2_RESERVED_24_16_SHIFT - | 0x00000000U << DDR_PHY_DX0LCDLR2_RESERVED_15_9_SHIFT - | 0x00000000U << DDR_PHY_DX0LCDLR2_DQSGD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX0LCDLR2_OFFSET ,0xFFFFFFFFU ,0x00000000U); - /*############################################################################################################################ */ + * RTT Output Hold + * PSU_DDR_PHY_DX1GCR0_RTTOH 0x3 - /*Register : DX0GTR0 @ 0XFD0807C0

+ * Configurable PDR Phase Shift + * PSU_DDR_PHY_DX1GCR0_CPDRSHFT 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX0GTR0_RESERVED_31_24 0x0 + * DQSR Power Down + * PSU_DDR_PHY_DX1GCR0_DQSRPD 0x0 - DQ Write Path Latency Pipeline - PSU_DDR_PHY_DX0GTR0_WDQSL 0x0 + * DQSG Power Down Receiver + * PSU_DDR_PHY_DX1GCR0_DQSGPDR 0x0 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX0GTR0_RESERVED_23_20 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX1GCR0_RESERVED_4 0x0 - Write Leveling System Latency - PSU_DDR_PHY_DX0GTR0_WLSL 0x2 + * DQSG On-Die Termination + * PSU_DDR_PHY_DX1GCR0_DQSGODT 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX0GTR0_RESERVED_15_13 0x0 + * DQSG Output Enable + * PSU_DDR_PHY_DX1GCR0_DQSGOE 0x1 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX0GTR0_RESERVED_12_8 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX1GCR0_RESERVED_1_0 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX0GTR0_RESERVED_7_5 0x0 + * DATX8 n General Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD080800, 0xFFFFFFFFU ,0x40800604U) + */ + PSU_Mask_Write(DDR_PHY_DX1GCR0_OFFSET, 0xFFFFFFFFU, 0x40800604U); +/*##################################################################### */ - DQS Gating System Latency - PSU_DDR_PHY_DX0GTR0_DGSL 0x0 + /* + * Register : DX1GCR4 @ 0XFD080810 - DATX8 n General Timing Register 0 - (OFFSET, MASK, VALUE) (0XFD0807C0, 0xFFFFFFFFU ,0x00020000U) - RegMask = (DDR_PHY_DX0GTR0_RESERVED_31_24_MASK | DDR_PHY_DX0GTR0_WDQSL_MASK | DDR_PHY_DX0GTR0_RESERVED_23_20_MASK | DDR_PHY_DX0GTR0_WLSL_MASK | DDR_PHY_DX0GTR0_RESERVED_15_13_MASK | DDR_PHY_DX0GTR0_RESERVED_12_8_MASK | DDR_PHY_DX0GTR0_RESERVED_7_5_MASK | DDR_PHY_DX0GTR0_DGSL_MASK | 0 ); + * Byte lane VREF IOM (Used only by D4MU IOs) + * PSU_DDR_PHY_DX1GCR4_RESERVED_31_29 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX0GTR0_RESERVED_31_24_SHIFT - | 0x00000000U << DDR_PHY_DX0GTR0_WDQSL_SHIFT - | 0x00000000U << DDR_PHY_DX0GTR0_RESERVED_23_20_SHIFT - | 0x00000002U << DDR_PHY_DX0GTR0_WLSL_SHIFT - | 0x00000000U << DDR_PHY_DX0GTR0_RESERVED_15_13_SHIFT - | 0x00000000U << DDR_PHY_DX0GTR0_RESERVED_12_8_SHIFT - | 0x00000000U << DDR_PHY_DX0GTR0_RESERVED_7_5_SHIFT - | 0x00000000U << DDR_PHY_DX0GTR0_DGSL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX0GTR0_OFFSET ,0xFFFFFFFFU ,0x00020000U); - /*############################################################################################################################ */ + * Byte Lane VREF Pad Enable + * PSU_DDR_PHY_DX1GCR4_DXREFPEN 0x0 - /*Register : DX1GCR0 @ 0XFD080800

+ * Byte Lane Internal VREF Enable + * PSU_DDR_PHY_DX1GCR4_DXREFEEN 0x3 - Calibration Bypass - PSU_DDR_PHY_DX1GCR0_CALBYP 0x0 + * Byte Lane Single-End VREF Enable + * PSU_DDR_PHY_DX1GCR4_DXREFSEN 0x1 - Master Delay Line Enable - PSU_DDR_PHY_DX1GCR0_MDLEN 0x1 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX1GCR4_RESERVED_24 0x0 - Configurable ODT(TE) Phase Shift - PSU_DDR_PHY_DX1GCR0_CODTSHFT 0x0 + * External VREF generator REFSEL range select + * PSU_DDR_PHY_DX1GCR4_DXREFESELRANGE 0x0 - DQS Duty Cycle Correction - PSU_DDR_PHY_DX1GCR0_DQSDCC 0x0 + * Byte Lane External VREF Select + * PSU_DDR_PHY_DX1GCR4_DXREFESEL 0x0 - Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY - PSU_DDR_PHY_DX1GCR0_RDDLY 0x8 + * Single ended VREF generator REFSEL range select + * PSU_DDR_PHY_DX1GCR4_DXREFSSELRANGE 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX1GCR0_RESERVED_19_14 0x0 + * Byte Lane Single-End VREF Select + * PSU_DDR_PHY_DX1GCR4_DXREFSSEL 0x30 - DQSNSE Power Down Receiver - PSU_DDR_PHY_DX1GCR0_DQSNSEPDR 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX1GCR4_RESERVED_7_6 0x0 - DQSSE Power Down Receiver - PSU_DDR_PHY_DX1GCR0_DQSSEPDR 0x0 + * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX1GCR4_DXREFIEN 0xf - RTT On Additive Latency - PSU_DDR_PHY_DX1GCR0_RTTOAL 0x0 + * VRMON control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX1GCR4_DXREFIMON 0x0 - RTT Output Hold - PSU_DDR_PHY_DX1GCR0_RTTOH 0x3 + * DATX8 n General Configuration Register 4 + * (OFFSET, MASK, VALUE) (0XFD080810, 0xFFFFFFFFU ,0x0E00B03CU) + */ + PSU_Mask_Write(DDR_PHY_DX1GCR4_OFFSET, 0xFFFFFFFFU, 0x0E00B03CU); +/*##################################################################### */ - Configurable PDR Phase Shift - PSU_DDR_PHY_DX1GCR0_CPDRSHFT 0x0 + /* + * Register : DX1GCR5 @ 0XFD080814 - DQSR Power Down - PSU_DDR_PHY_DX1GCR0_DQSRPD 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX1GCR5_RESERVED_31 0x0 - DQSG Power Down Receiver - PSU_DDR_PHY_DX1GCR0_DQSGPDR 0x0 + * Byte Lane internal VREF Select for Rank 3 + * PSU_DDR_PHY_DX1GCR5_DXREFISELR3 0x9 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX1GCR0_RESERVED_4 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX1GCR5_RESERVED_23 0x0 - DQSG On-Die Termination - PSU_DDR_PHY_DX1GCR0_DQSGODT 0x0 + * Byte Lane internal VREF Select for Rank 2 + * PSU_DDR_PHY_DX1GCR5_DXREFISELR2 0x9 - DQSG Output Enable - PSU_DDR_PHY_DX1GCR0_DQSGOE 0x1 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX1GCR5_RESERVED_15 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX1GCR0_RESERVED_1_0 0x0 + * Byte Lane internal VREF Select for Rank 1 + * PSU_DDR_PHY_DX1GCR5_DXREFISELR1 0x55 - DATX8 n General Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD080800, 0xFFFFFFFFU ,0x40800604U) - RegMask = (DDR_PHY_DX1GCR0_CALBYP_MASK | DDR_PHY_DX1GCR0_MDLEN_MASK | DDR_PHY_DX1GCR0_CODTSHFT_MASK | DDR_PHY_DX1GCR0_DQSDCC_MASK | DDR_PHY_DX1GCR0_RDDLY_MASK | DDR_PHY_DX1GCR0_RESERVED_19_14_MASK | DDR_PHY_DX1GCR0_DQSNSEPDR_MASK | DDR_PHY_DX1GCR0_DQSSEPDR_MASK | DDR_PHY_DX1GCR0_RTTOAL_MASK | DDR_PHY_DX1GCR0_RTTOH_MASK | DDR_PHY_DX1GCR0_CPDRSHFT_MASK | DDR_PHY_DX1GCR0_DQSRPD_MASK | DDR_PHY_DX1GCR0_DQSGPDR_MASK | DDR_PHY_DX1GCR0_RESERVED_4_MASK | DDR_PHY_DX1GCR0_DQSGODT_MASK | DDR_PHY_DX1GCR0_DQSGOE_MASK | DDR_PHY_DX1GCR0_RESERVED_1_0_MASK | 0 ); + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX1GCR5_RESERVED_7 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX1GCR0_CALBYP_SHIFT - | 0x00000001U << DDR_PHY_DX1GCR0_MDLEN_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR0_CODTSHFT_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR0_DQSDCC_SHIFT - | 0x00000008U << DDR_PHY_DX1GCR0_RDDLY_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR0_RESERVED_19_14_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR0_DQSNSEPDR_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR0_DQSSEPDR_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR0_RTTOAL_SHIFT - | 0x00000003U << DDR_PHY_DX1GCR0_RTTOH_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR0_CPDRSHFT_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR0_DQSRPD_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR0_DQSGPDR_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR0_RESERVED_4_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR0_DQSGODT_SHIFT - | 0x00000001U << DDR_PHY_DX1GCR0_DQSGOE_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR0_RESERVED_1_0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX1GCR0_OFFSET ,0xFFFFFFFFU ,0x40800604U); - /*############################################################################################################################ */ + * Byte Lane internal VREF Select for Rank 0 + * PSU_DDR_PHY_DX1GCR5_DXREFISELR0 0x55 - /*Register : DX1GCR4 @ 0XFD080810

+ * DATX8 n General Configuration Register 5 + * (OFFSET, MASK, VALUE) (0XFD080814, 0xFFFFFFFFU ,0x09095555U) + */ + PSU_Mask_Write(DDR_PHY_DX1GCR5_OFFSET, 0xFFFFFFFFU, 0x09095555U); +/*##################################################################### */ - Byte lane VREF IOM (Used only by D4MU IOs) - PSU_DDR_PHY_DX1GCR4_RESERVED_31_29 0x0 + /* + * Register : DX1GCR6 @ 0XFD080818 - Byte Lane VREF Pad Enable - PSU_DDR_PHY_DX1GCR4_DXREFPEN 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX1GCR6_RESERVED_31_30 0x0 - Byte Lane Internal VREF Enable - PSU_DDR_PHY_DX1GCR4_DXREFEEN 0x3 + * DRAM DQ VREF Select for Rank3 + * PSU_DDR_PHY_DX1GCR6_DXDQVREFR3 0x9 - Byte Lane Single-End VREF Enable - PSU_DDR_PHY_DX1GCR4_DXREFSEN 0x1 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX1GCR6_RESERVED_23_22 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX1GCR4_RESERVED_24 0x0 + * DRAM DQ VREF Select for Rank2 + * PSU_DDR_PHY_DX1GCR6_DXDQVREFR2 0x9 - External VREF generator REFSEL range select - PSU_DDR_PHY_DX1GCR4_DXREFESELRANGE 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX1GCR6_RESERVED_15_14 0x0 - Byte Lane External VREF Select - PSU_DDR_PHY_DX1GCR4_DXREFESEL 0x0 + * DRAM DQ VREF Select for Rank1 + * PSU_DDR_PHY_DX1GCR6_DXDQVREFR1 0x2b - Single ended VREF generator REFSEL range select - PSU_DDR_PHY_DX1GCR4_DXREFSSELRANGE 0x1 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX1GCR6_RESERVED_7_6 0x0 - Byte Lane Single-End VREF Select - PSU_DDR_PHY_DX1GCR4_DXREFSSEL 0x30 + * DRAM DQ VREF Select for Rank0 + * PSU_DDR_PHY_DX1GCR6_DXDQVREFR0 0x2b - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX1GCR4_RESERVED_7_6 0x0 + * DATX8 n General Configuration Register 6 + * (OFFSET, MASK, VALUE) (0XFD080818, 0xFFFFFFFFU ,0x09092B2BU) + */ + PSU_Mask_Write(DDR_PHY_DX1GCR6_OFFSET, 0xFFFFFFFFU, 0x09092B2BU); +/*##################################################################### */ - VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. - PSU_DDR_PHY_DX1GCR4_DXREFIEN 0xf + /* + * Register : DX2GCR0 @ 0XFD080900 - VRMON control for DQ IO (Single Ended) buffers of a byte lane. - PSU_DDR_PHY_DX1GCR4_DXREFIMON 0x0 + * Calibration Bypass + * PSU_DDR_PHY_DX2GCR0_CALBYP 0x0 - DATX8 n General Configuration Register 4 - (OFFSET, MASK, VALUE) (0XFD080810, 0xFFFFFFFFU ,0x0E00B03CU) - RegMask = (DDR_PHY_DX1GCR4_RESERVED_31_29_MASK | DDR_PHY_DX1GCR4_DXREFPEN_MASK | DDR_PHY_DX1GCR4_DXREFEEN_MASK | DDR_PHY_DX1GCR4_DXREFSEN_MASK | DDR_PHY_DX1GCR4_RESERVED_24_MASK | DDR_PHY_DX1GCR4_DXREFESELRANGE_MASK | DDR_PHY_DX1GCR4_DXREFESEL_MASK | DDR_PHY_DX1GCR4_DXREFSSELRANGE_MASK | DDR_PHY_DX1GCR4_DXREFSSEL_MASK | DDR_PHY_DX1GCR4_RESERVED_7_6_MASK | DDR_PHY_DX1GCR4_DXREFIEN_MASK | DDR_PHY_DX1GCR4_DXREFIMON_MASK | 0 ); + * Master Delay Line Enable + * PSU_DDR_PHY_DX2GCR0_MDLEN 0x1 - RegVal = ((0x00000000U << DDR_PHY_DX1GCR4_RESERVED_31_29_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR4_DXREFPEN_SHIFT - | 0x00000003U << DDR_PHY_DX1GCR4_DXREFEEN_SHIFT - | 0x00000001U << DDR_PHY_DX1GCR4_DXREFSEN_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR4_RESERVED_24_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR4_DXREFESELRANGE_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR4_DXREFESEL_SHIFT - | 0x00000001U << DDR_PHY_DX1GCR4_DXREFSSELRANGE_SHIFT - | 0x00000030U << DDR_PHY_DX1GCR4_DXREFSSEL_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR4_RESERVED_7_6_SHIFT - | 0x0000000FU << DDR_PHY_DX1GCR4_DXREFIEN_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR4_DXREFIMON_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX1GCR4_OFFSET ,0xFFFFFFFFU ,0x0E00B03CU); - /*############################################################################################################################ */ + * Configurable ODT(TE) Phase Shift + * PSU_DDR_PHY_DX2GCR0_CODTSHFT 0x0 - /*Register : DX1GCR5 @ 0XFD080814

+ * DQS Duty Cycle Correction + * PSU_DDR_PHY_DX2GCR0_DQSDCC 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX1GCR5_RESERVED_31 0x0 + * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY + * PSU_DDR_PHY_DX2GCR0_RDDLY 0x8 - Byte Lane internal VREF Select for Rank 3 - PSU_DDR_PHY_DX1GCR5_DXREFISELR3 0x9 - - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX1GCR5_RESERVED_23 0x0 - - Byte Lane internal VREF Select for Rank 2 - PSU_DDR_PHY_DX1GCR5_DXREFISELR2 0x9 - - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX1GCR5_RESERVED_15 0x0 - - Byte Lane internal VREF Select for Rank 1 - PSU_DDR_PHY_DX1GCR5_DXREFISELR1 0x4f - - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX1GCR5_RESERVED_7 0x0 - - Byte Lane internal VREF Select for Rank 0 - PSU_DDR_PHY_DX1GCR5_DXREFISELR0 0x4f + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX2GCR0_RESERVED_19_14 0x0 - DATX8 n General Configuration Register 5 - (OFFSET, MASK, VALUE) (0XFD080814, 0xFFFFFFFFU ,0x09094F4FU) - RegMask = (DDR_PHY_DX1GCR5_RESERVED_31_MASK | DDR_PHY_DX1GCR5_DXREFISELR3_MASK | DDR_PHY_DX1GCR5_RESERVED_23_MASK | DDR_PHY_DX1GCR5_DXREFISELR2_MASK | DDR_PHY_DX1GCR5_RESERVED_15_MASK | DDR_PHY_DX1GCR5_DXREFISELR1_MASK | DDR_PHY_DX1GCR5_RESERVED_7_MASK | DDR_PHY_DX1GCR5_DXREFISELR0_MASK | 0 ); + * DQSNSE Power Down Receiver + * PSU_DDR_PHY_DX2GCR0_DQSNSEPDR 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX1GCR5_RESERVED_31_SHIFT - | 0x00000009U << DDR_PHY_DX1GCR5_DXREFISELR3_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR5_RESERVED_23_SHIFT - | 0x00000009U << DDR_PHY_DX1GCR5_DXREFISELR2_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR5_RESERVED_15_SHIFT - | 0x0000004FU << DDR_PHY_DX1GCR5_DXREFISELR1_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR5_RESERVED_7_SHIFT - | 0x0000004FU << DDR_PHY_DX1GCR5_DXREFISELR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX1GCR5_OFFSET ,0xFFFFFFFFU ,0x09094F4FU); - /*############################################################################################################################ */ + * DQSSE Power Down Receiver + * PSU_DDR_PHY_DX2GCR0_DQSSEPDR 0x0 - /*Register : DX1GCR6 @ 0XFD080818

+ * RTT On Additive Latency + * PSU_DDR_PHY_DX2GCR0_RTTOAL 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX1GCR6_RESERVED_31_30 0x0 + * RTT Output Hold + * PSU_DDR_PHY_DX2GCR0_RTTOH 0x3 - DRAM DQ VREF Select for Rank3 - PSU_DDR_PHY_DX1GCR6_DXDQVREFR3 0x9 + * Configurable PDR Phase Shift + * PSU_DDR_PHY_DX2GCR0_CPDRSHFT 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX1GCR6_RESERVED_23_22 0x0 + * DQSR Power Down + * PSU_DDR_PHY_DX2GCR0_DQSRPD 0x0 - DRAM DQ VREF Select for Rank2 - PSU_DDR_PHY_DX1GCR6_DXDQVREFR2 0x9 + * DQSG Power Down Receiver + * PSU_DDR_PHY_DX2GCR0_DQSGPDR 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX1GCR6_RESERVED_15_14 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX2GCR0_RESERVED_4 0x0 - DRAM DQ VREF Select for Rank1 - PSU_DDR_PHY_DX1GCR6_DXDQVREFR1 0x2b + * DQSG On-Die Termination + * PSU_DDR_PHY_DX2GCR0_DQSGODT 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX1GCR6_RESERVED_7_6 0x0 + * DQSG Output Enable + * PSU_DDR_PHY_DX2GCR0_DQSGOE 0x1 - DRAM DQ VREF Select for Rank0 - PSU_DDR_PHY_DX1GCR6_DXDQVREFR0 0x2b + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX2GCR0_RESERVED_1_0 0x0 - DATX8 n General Configuration Register 6 - (OFFSET, MASK, VALUE) (0XFD080818, 0xFFFFFFFFU ,0x09092B2BU) - RegMask = (DDR_PHY_DX1GCR6_RESERVED_31_30_MASK | DDR_PHY_DX1GCR6_DXDQVREFR3_MASK | DDR_PHY_DX1GCR6_RESERVED_23_22_MASK | DDR_PHY_DX1GCR6_DXDQVREFR2_MASK | DDR_PHY_DX1GCR6_RESERVED_15_14_MASK | DDR_PHY_DX1GCR6_DXDQVREFR1_MASK | DDR_PHY_DX1GCR6_RESERVED_7_6_MASK | DDR_PHY_DX1GCR6_DXDQVREFR0_MASK | 0 ); + * DATX8 n General Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD080900, 0xFFFFFFFFU ,0x40800604U) + */ + PSU_Mask_Write(DDR_PHY_DX2GCR0_OFFSET, 0xFFFFFFFFU, 0x40800604U); +/*##################################################################### */ - RegVal = ((0x00000000U << DDR_PHY_DX1GCR6_RESERVED_31_30_SHIFT - | 0x00000009U << DDR_PHY_DX1GCR6_DXDQVREFR3_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR6_RESERVED_23_22_SHIFT - | 0x00000009U << DDR_PHY_DX1GCR6_DXDQVREFR2_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR6_RESERVED_15_14_SHIFT - | 0x0000002BU << DDR_PHY_DX1GCR6_DXDQVREFR1_SHIFT - | 0x00000000U << DDR_PHY_DX1GCR6_RESERVED_7_6_SHIFT - | 0x0000002BU << DDR_PHY_DX1GCR6_DXDQVREFR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX1GCR6_OFFSET ,0xFFFFFFFFU ,0x09092B2BU); - /*############################################################################################################################ */ + /* + * Register : DX2GCR1 @ 0XFD080904 - /*Register : DX1LCDLR2 @ 0XFD080888

+ * Enables the PDR mode for DQ[7:0] + * PSU_DDR_PHY_DX2GCR1_DXPDRMODE 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX1LCDLR2_RESERVED_31_25 0x0 + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX2GCR1_RESERVED_15 0x0 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX1LCDLR2_RESERVED_24_16 0x0 + * Select the delayed or non-delayed read data strobe # + * PSU_DDR_PHY_DX2GCR1_QSNSEL 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX1LCDLR2_RESERVED_15_9 0x0 + * Select the delayed or non-delayed read data strobe + * PSU_DDR_PHY_DX2GCR1_QSSEL 0x1 - Read DQS Gating Delay - PSU_DDR_PHY_DX1LCDLR2_DQSGD 0x0 + * Enables Read Data Strobe in a byte lane + * PSU_DDR_PHY_DX2GCR1_OEEN 0x1 - DATX8 n Local Calibrated Delay Line Register 2 - (OFFSET, MASK, VALUE) (0XFD080888, 0xFFFFFFFFU ,0x00000000U) - RegMask = (DDR_PHY_DX1LCDLR2_RESERVED_31_25_MASK | DDR_PHY_DX1LCDLR2_RESERVED_24_16_MASK | DDR_PHY_DX1LCDLR2_RESERVED_15_9_MASK | DDR_PHY_DX1LCDLR2_DQSGD_MASK | 0 ); + * Enables PDR in a byte lane + * PSU_DDR_PHY_DX2GCR1_PDREN 0x1 - RegVal = ((0x00000000U << DDR_PHY_DX1LCDLR2_RESERVED_31_25_SHIFT - | 0x00000000U << DDR_PHY_DX1LCDLR2_RESERVED_24_16_SHIFT - | 0x00000000U << DDR_PHY_DX1LCDLR2_RESERVED_15_9_SHIFT - | 0x00000000U << DDR_PHY_DX1LCDLR2_DQSGD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX1LCDLR2_OFFSET ,0xFFFFFFFFU ,0x00000000U); - /*############################################################################################################################ */ + * Enables ODT/TE in a byte lane + * PSU_DDR_PHY_DX2GCR1_TEEN 0x1 - /*Register : DX1GTR0 @ 0XFD0808C0

+ * Enables Write Data strobe in a byte lane + * PSU_DDR_PHY_DX2GCR1_DSEN 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX1GTR0_RESERVED_31_24 0x0 + * Enables DM pin in a byte lane + * PSU_DDR_PHY_DX2GCR1_DMEN 0x1 - DQ Write Path Latency Pipeline - PSU_DDR_PHY_DX1GTR0_WDQSL 0x0 + * Enables DQ corresponding to each bit in a byte + * PSU_DDR_PHY_DX2GCR1_DQEN 0xff - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX1GTR0_RESERVED_23_20 0x0 + * DATX8 n General Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD080904, 0xFFFFFFFFU ,0x00007FFFU) + */ + PSU_Mask_Write(DDR_PHY_DX2GCR1_OFFSET, 0xFFFFFFFFU, 0x00007FFFU); +/*##################################################################### */ - Write Leveling System Latency - PSU_DDR_PHY_DX1GTR0_WLSL 0x2 + /* + * Register : DX2GCR4 @ 0XFD080910 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX1GTR0_RESERVED_15_13 0x0 + * Byte lane VREF IOM (Used only by D4MU IOs) + * PSU_DDR_PHY_DX2GCR4_RESERVED_31_29 0x0 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX1GTR0_RESERVED_12_8 0x0 + * Byte Lane VREF Pad Enable + * PSU_DDR_PHY_DX2GCR4_DXREFPEN 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX1GTR0_RESERVED_7_5 0x0 + * Byte Lane Internal VREF Enable + * PSU_DDR_PHY_DX2GCR4_DXREFEEN 0x3 - DQS Gating System Latency - PSU_DDR_PHY_DX1GTR0_DGSL 0x0 + * Byte Lane Single-End VREF Enable + * PSU_DDR_PHY_DX2GCR4_DXREFSEN 0x1 - DATX8 n General Timing Register 0 - (OFFSET, MASK, VALUE) (0XFD0808C0, 0xFFFFFFFFU ,0x00020000U) - RegMask = (DDR_PHY_DX1GTR0_RESERVED_31_24_MASK | DDR_PHY_DX1GTR0_WDQSL_MASK | DDR_PHY_DX1GTR0_RESERVED_23_20_MASK | DDR_PHY_DX1GTR0_WLSL_MASK | DDR_PHY_DX1GTR0_RESERVED_15_13_MASK | DDR_PHY_DX1GTR0_RESERVED_12_8_MASK | DDR_PHY_DX1GTR0_RESERVED_7_5_MASK | DDR_PHY_DX1GTR0_DGSL_MASK | 0 ); + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX2GCR4_RESERVED_24 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX1GTR0_RESERVED_31_24_SHIFT - | 0x00000000U << DDR_PHY_DX1GTR0_WDQSL_SHIFT - | 0x00000000U << DDR_PHY_DX1GTR0_RESERVED_23_20_SHIFT - | 0x00000002U << DDR_PHY_DX1GTR0_WLSL_SHIFT - | 0x00000000U << DDR_PHY_DX1GTR0_RESERVED_15_13_SHIFT - | 0x00000000U << DDR_PHY_DX1GTR0_RESERVED_12_8_SHIFT - | 0x00000000U << DDR_PHY_DX1GTR0_RESERVED_7_5_SHIFT - | 0x00000000U << DDR_PHY_DX1GTR0_DGSL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX1GTR0_OFFSET ,0xFFFFFFFFU ,0x00020000U); - /*############################################################################################################################ */ + * External VREF generator REFSEL range select + * PSU_DDR_PHY_DX2GCR4_DXREFESELRANGE 0x0 - /*Register : DX2GCR0 @ 0XFD080900

+ * Byte Lane External VREF Select + * PSU_DDR_PHY_DX2GCR4_DXREFESEL 0x0 - Calibration Bypass - PSU_DDR_PHY_DX2GCR0_CALBYP 0x0 + * Single ended VREF generator REFSEL range select + * PSU_DDR_PHY_DX2GCR4_DXREFSSELRANGE 0x1 - Master Delay Line Enable - PSU_DDR_PHY_DX2GCR0_MDLEN 0x1 + * Byte Lane Single-End VREF Select + * PSU_DDR_PHY_DX2GCR4_DXREFSSEL 0x30 - Configurable ODT(TE) Phase Shift - PSU_DDR_PHY_DX2GCR0_CODTSHFT 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX2GCR4_RESERVED_7_6 0x0 - DQS Duty Cycle Correction - PSU_DDR_PHY_DX2GCR0_DQSDCC 0x0 + * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX2GCR4_DXREFIEN 0xf - Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY - PSU_DDR_PHY_DX2GCR0_RDDLY 0x8 + * VRMON control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX2GCR4_DXREFIMON 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX2GCR0_RESERVED_19_14 0x0 + * DATX8 n General Configuration Register 4 + * (OFFSET, MASK, VALUE) (0XFD080910, 0xFFFFFFFFU ,0x0E00B03CU) + */ + PSU_Mask_Write(DDR_PHY_DX2GCR4_OFFSET, 0xFFFFFFFFU, 0x0E00B03CU); +/*##################################################################### */ - DQSNSE Power Down Receiver - PSU_DDR_PHY_DX2GCR0_DQSNSEPDR 0x0 + /* + * Register : DX2GCR5 @ 0XFD080914 - DQSSE Power Down Receiver - PSU_DDR_PHY_DX2GCR0_DQSSEPDR 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX2GCR5_RESERVED_31 0x0 - RTT On Additive Latency - PSU_DDR_PHY_DX2GCR0_RTTOAL 0x0 + * Byte Lane internal VREF Select for Rank 3 + * PSU_DDR_PHY_DX2GCR5_DXREFISELR3 0x9 - RTT Output Hold - PSU_DDR_PHY_DX2GCR0_RTTOH 0x3 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX2GCR5_RESERVED_23 0x0 - Configurable PDR Phase Shift - PSU_DDR_PHY_DX2GCR0_CPDRSHFT 0x0 + * Byte Lane internal VREF Select for Rank 2 + * PSU_DDR_PHY_DX2GCR5_DXREFISELR2 0x9 - DQSR Power Down - PSU_DDR_PHY_DX2GCR0_DQSRPD 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX2GCR5_RESERVED_15 0x0 - DQSG Power Down Receiver - PSU_DDR_PHY_DX2GCR0_DQSGPDR 0x0 + * Byte Lane internal VREF Select for Rank 1 + * PSU_DDR_PHY_DX2GCR5_DXREFISELR1 0x55 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX2GCR0_RESERVED_4 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX2GCR5_RESERVED_7 0x0 - DQSG On-Die Termination - PSU_DDR_PHY_DX2GCR0_DQSGODT 0x0 + * Byte Lane internal VREF Select for Rank 0 + * PSU_DDR_PHY_DX2GCR5_DXREFISELR0 0x55 - DQSG Output Enable - PSU_DDR_PHY_DX2GCR0_DQSGOE 0x1 + * DATX8 n General Configuration Register 5 + * (OFFSET, MASK, VALUE) (0XFD080914, 0xFFFFFFFFU ,0x09095555U) + */ + PSU_Mask_Write(DDR_PHY_DX2GCR5_OFFSET, 0xFFFFFFFFU, 0x09095555U); +/*##################################################################### */ - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX2GCR0_RESERVED_1_0 0x0 + /* + * Register : DX2GCR6 @ 0XFD080918 - DATX8 n General Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD080900, 0xFFFFFFFFU ,0x40800604U) - RegMask = (DDR_PHY_DX2GCR0_CALBYP_MASK | DDR_PHY_DX2GCR0_MDLEN_MASK | DDR_PHY_DX2GCR0_CODTSHFT_MASK | DDR_PHY_DX2GCR0_DQSDCC_MASK | DDR_PHY_DX2GCR0_RDDLY_MASK | DDR_PHY_DX2GCR0_RESERVED_19_14_MASK | DDR_PHY_DX2GCR0_DQSNSEPDR_MASK | DDR_PHY_DX2GCR0_DQSSEPDR_MASK | DDR_PHY_DX2GCR0_RTTOAL_MASK | DDR_PHY_DX2GCR0_RTTOH_MASK | DDR_PHY_DX2GCR0_CPDRSHFT_MASK | DDR_PHY_DX2GCR0_DQSRPD_MASK | DDR_PHY_DX2GCR0_DQSGPDR_MASK | DDR_PHY_DX2GCR0_RESERVED_4_MASK | DDR_PHY_DX2GCR0_DQSGODT_MASK | DDR_PHY_DX2GCR0_DQSGOE_MASK | DDR_PHY_DX2GCR0_RESERVED_1_0_MASK | 0 ); + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX2GCR6_RESERVED_31_30 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX2GCR0_CALBYP_SHIFT - | 0x00000001U << DDR_PHY_DX2GCR0_MDLEN_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR0_CODTSHFT_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR0_DQSDCC_SHIFT - | 0x00000008U << DDR_PHY_DX2GCR0_RDDLY_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR0_RESERVED_19_14_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR0_DQSNSEPDR_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR0_DQSSEPDR_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR0_RTTOAL_SHIFT - | 0x00000003U << DDR_PHY_DX2GCR0_RTTOH_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR0_CPDRSHFT_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR0_DQSRPD_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR0_DQSGPDR_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR0_RESERVED_4_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR0_DQSGODT_SHIFT - | 0x00000001U << DDR_PHY_DX2GCR0_DQSGOE_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR0_RESERVED_1_0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX2GCR0_OFFSET ,0xFFFFFFFFU ,0x40800604U); - /*############################################################################################################################ */ + * DRAM DQ VREF Select for Rank3 + * PSU_DDR_PHY_DX2GCR6_DXDQVREFR3 0x9 - /*Register : DX2GCR1 @ 0XFD080904

+ * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX2GCR6_RESERVED_23_22 0x0 - Enables the PDR mode for DQ[7:0] - PSU_DDR_PHY_DX2GCR1_DXPDRMODE 0x0 + * DRAM DQ VREF Select for Rank2 + * PSU_DDR_PHY_DX2GCR6_DXDQVREFR2 0x9 - Reserved. Returns zeroes on reads. - PSU_DDR_PHY_DX2GCR1_RESERVED_15 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX2GCR6_RESERVED_15_14 0x0 - Select the delayed or non-delayed read data strobe # - PSU_DDR_PHY_DX2GCR1_QSNSEL 0x1 + * DRAM DQ VREF Select for Rank1 + * PSU_DDR_PHY_DX2GCR6_DXDQVREFR1 0x2b - Select the delayed or non-delayed read data strobe - PSU_DDR_PHY_DX2GCR1_QSSEL 0x1 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX2GCR6_RESERVED_7_6 0x0 - Enables Read Data Strobe in a byte lane - PSU_DDR_PHY_DX2GCR1_OEEN 0x1 + * DRAM DQ VREF Select for Rank0 + * PSU_DDR_PHY_DX2GCR6_DXDQVREFR0 0x2b - Enables PDR in a byte lane - PSU_DDR_PHY_DX2GCR1_PDREN 0x1 + * DATX8 n General Configuration Register 6 + * (OFFSET, MASK, VALUE) (0XFD080918, 0xFFFFFFFFU ,0x09092B2BU) + */ + PSU_Mask_Write(DDR_PHY_DX2GCR6_OFFSET, 0xFFFFFFFFU, 0x09092B2BU); +/*##################################################################### */ - Enables ODT/TE in a byte lane - PSU_DDR_PHY_DX2GCR1_TEEN 0x1 + /* + * Register : DX3GCR0 @ 0XFD080A00 - Enables Write Data strobe in a byte lane - PSU_DDR_PHY_DX2GCR1_DSEN 0x1 + * Calibration Bypass + * PSU_DDR_PHY_DX3GCR0_CALBYP 0x0 - Enables DM pin in a byte lane - PSU_DDR_PHY_DX2GCR1_DMEN 0x1 + * Master Delay Line Enable + * PSU_DDR_PHY_DX3GCR0_MDLEN 0x1 - Enables DQ corresponding to each bit in a byte - PSU_DDR_PHY_DX2GCR1_DQEN 0xff + * Configurable ODT(TE) Phase Shift + * PSU_DDR_PHY_DX3GCR0_CODTSHFT 0x0 - DATX8 n General Configuration Register 1 - (OFFSET, MASK, VALUE) (0XFD080904, 0xFFFFFFFFU ,0x00007FFFU) - RegMask = (DDR_PHY_DX2GCR1_DXPDRMODE_MASK | DDR_PHY_DX2GCR1_RESERVED_15_MASK | DDR_PHY_DX2GCR1_QSNSEL_MASK | DDR_PHY_DX2GCR1_QSSEL_MASK | DDR_PHY_DX2GCR1_OEEN_MASK | DDR_PHY_DX2GCR1_PDREN_MASK | DDR_PHY_DX2GCR1_TEEN_MASK | DDR_PHY_DX2GCR1_DSEN_MASK | DDR_PHY_DX2GCR1_DMEN_MASK | DDR_PHY_DX2GCR1_DQEN_MASK | 0 ); + * DQS Duty Cycle Correction + * PSU_DDR_PHY_DX3GCR0_DQSDCC 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX2GCR1_DXPDRMODE_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR1_RESERVED_15_SHIFT - | 0x00000001U << DDR_PHY_DX2GCR1_QSNSEL_SHIFT - | 0x00000001U << DDR_PHY_DX2GCR1_QSSEL_SHIFT - | 0x00000001U << DDR_PHY_DX2GCR1_OEEN_SHIFT - | 0x00000001U << DDR_PHY_DX2GCR1_PDREN_SHIFT - | 0x00000001U << DDR_PHY_DX2GCR1_TEEN_SHIFT - | 0x00000001U << DDR_PHY_DX2GCR1_DSEN_SHIFT - | 0x00000001U << DDR_PHY_DX2GCR1_DMEN_SHIFT - | 0x000000FFU << DDR_PHY_DX2GCR1_DQEN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX2GCR1_OFFSET ,0xFFFFFFFFU ,0x00007FFFU); - /*############################################################################################################################ */ + * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY + * PSU_DDR_PHY_DX3GCR0_RDDLY 0x8 - /*Register : DX2GCR4 @ 0XFD080910

+ * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX3GCR0_RESERVED_19_14 0x0 - Byte lane VREF IOM (Used only by D4MU IOs) - PSU_DDR_PHY_DX2GCR4_RESERVED_31_29 0x0 + * DQSNSE Power Down Receiver + * PSU_DDR_PHY_DX3GCR0_DQSNSEPDR 0x0 - Byte Lane VREF Pad Enable - PSU_DDR_PHY_DX2GCR4_DXREFPEN 0x0 + * DQSSE Power Down Receiver + * PSU_DDR_PHY_DX3GCR0_DQSSEPDR 0x0 - Byte Lane Internal VREF Enable - PSU_DDR_PHY_DX2GCR4_DXREFEEN 0x3 + * RTT On Additive Latency + * PSU_DDR_PHY_DX3GCR0_RTTOAL 0x0 - Byte Lane Single-End VREF Enable - PSU_DDR_PHY_DX2GCR4_DXREFSEN 0x1 + * RTT Output Hold + * PSU_DDR_PHY_DX3GCR0_RTTOH 0x3 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX2GCR4_RESERVED_24 0x0 + * Configurable PDR Phase Shift + * PSU_DDR_PHY_DX3GCR0_CPDRSHFT 0x0 - External VREF generator REFSEL range select - PSU_DDR_PHY_DX2GCR4_DXREFESELRANGE 0x0 + * DQSR Power Down + * PSU_DDR_PHY_DX3GCR0_DQSRPD 0x0 - Byte Lane External VREF Select - PSU_DDR_PHY_DX2GCR4_DXREFESEL 0x0 + * DQSG Power Down Receiver + * PSU_DDR_PHY_DX3GCR0_DQSGPDR 0x0 - Single ended VREF generator REFSEL range select - PSU_DDR_PHY_DX2GCR4_DXREFSSELRANGE 0x1 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX3GCR0_RESERVED_4 0x0 - Byte Lane Single-End VREF Select - PSU_DDR_PHY_DX2GCR4_DXREFSSEL 0x30 + * DQSG On-Die Termination + * PSU_DDR_PHY_DX3GCR0_DQSGODT 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX2GCR4_RESERVED_7_6 0x0 + * DQSG Output Enable + * PSU_DDR_PHY_DX3GCR0_DQSGOE 0x1 - VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. - PSU_DDR_PHY_DX2GCR4_DXREFIEN 0xf + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX3GCR0_RESERVED_1_0 0x0 - VRMON control for DQ IO (Single Ended) buffers of a byte lane. - PSU_DDR_PHY_DX2GCR4_DXREFIMON 0x0 + * DATX8 n General Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD080A00, 0xFFFFFFFFU ,0x40800604U) + */ + PSU_Mask_Write(DDR_PHY_DX3GCR0_OFFSET, 0xFFFFFFFFU, 0x40800604U); +/*##################################################################### */ - DATX8 n General Configuration Register 4 - (OFFSET, MASK, VALUE) (0XFD080910, 0xFFFFFFFFU ,0x0E00B03CU) - RegMask = (DDR_PHY_DX2GCR4_RESERVED_31_29_MASK | DDR_PHY_DX2GCR4_DXREFPEN_MASK | DDR_PHY_DX2GCR4_DXREFEEN_MASK | DDR_PHY_DX2GCR4_DXREFSEN_MASK | DDR_PHY_DX2GCR4_RESERVED_24_MASK | DDR_PHY_DX2GCR4_DXREFESELRANGE_MASK | DDR_PHY_DX2GCR4_DXREFESEL_MASK | DDR_PHY_DX2GCR4_DXREFSSELRANGE_MASK | DDR_PHY_DX2GCR4_DXREFSSEL_MASK | DDR_PHY_DX2GCR4_RESERVED_7_6_MASK | DDR_PHY_DX2GCR4_DXREFIEN_MASK | DDR_PHY_DX2GCR4_DXREFIMON_MASK | 0 ); + /* + * Register : DX3GCR1 @ 0XFD080A04 - RegVal = ((0x00000000U << DDR_PHY_DX2GCR4_RESERVED_31_29_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR4_DXREFPEN_SHIFT - | 0x00000003U << DDR_PHY_DX2GCR4_DXREFEEN_SHIFT - | 0x00000001U << DDR_PHY_DX2GCR4_DXREFSEN_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR4_RESERVED_24_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR4_DXREFESELRANGE_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR4_DXREFESEL_SHIFT - | 0x00000001U << DDR_PHY_DX2GCR4_DXREFSSELRANGE_SHIFT - | 0x00000030U << DDR_PHY_DX2GCR4_DXREFSSEL_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR4_RESERVED_7_6_SHIFT - | 0x0000000FU << DDR_PHY_DX2GCR4_DXREFIEN_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR4_DXREFIMON_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX2GCR4_OFFSET ,0xFFFFFFFFU ,0x0E00B03CU); - /*############################################################################################################################ */ + * Enables the PDR mode for DQ[7:0] + * PSU_DDR_PHY_DX3GCR1_DXPDRMODE 0x0 - /*Register : DX2GCR5 @ 0XFD080914

+ * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX3GCR1_RESERVED_15 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX2GCR5_RESERVED_31 0x0 + * Select the delayed or non-delayed read data strobe # + * PSU_DDR_PHY_DX3GCR1_QSNSEL 0x1 - Byte Lane internal VREF Select for Rank 3 - PSU_DDR_PHY_DX2GCR5_DXREFISELR3 0x9 + * Select the delayed or non-delayed read data strobe + * PSU_DDR_PHY_DX3GCR1_QSSEL 0x1 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX2GCR5_RESERVED_23 0x0 + * Enables Read Data Strobe in a byte lane + * PSU_DDR_PHY_DX3GCR1_OEEN 0x1 - Byte Lane internal VREF Select for Rank 2 - PSU_DDR_PHY_DX2GCR5_DXREFISELR2 0x9 + * Enables PDR in a byte lane + * PSU_DDR_PHY_DX3GCR1_PDREN 0x1 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX2GCR5_RESERVED_15 0x0 + * Enables ODT/TE in a byte lane + * PSU_DDR_PHY_DX3GCR1_TEEN 0x1 - Byte Lane internal VREF Select for Rank 1 - PSU_DDR_PHY_DX2GCR5_DXREFISELR1 0x4f + * Enables Write Data strobe in a byte lane + * PSU_DDR_PHY_DX3GCR1_DSEN 0x1 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX2GCR5_RESERVED_7 0x0 + * Enables DM pin in a byte lane + * PSU_DDR_PHY_DX3GCR1_DMEN 0x1 - Byte Lane internal VREF Select for Rank 0 - PSU_DDR_PHY_DX2GCR5_DXREFISELR0 0x4f + * Enables DQ corresponding to each bit in a byte + * PSU_DDR_PHY_DX3GCR1_DQEN 0xff - DATX8 n General Configuration Register 5 - (OFFSET, MASK, VALUE) (0XFD080914, 0xFFFFFFFFU ,0x09094F4FU) - RegMask = (DDR_PHY_DX2GCR5_RESERVED_31_MASK | DDR_PHY_DX2GCR5_DXREFISELR3_MASK | DDR_PHY_DX2GCR5_RESERVED_23_MASK | DDR_PHY_DX2GCR5_DXREFISELR2_MASK | DDR_PHY_DX2GCR5_RESERVED_15_MASK | DDR_PHY_DX2GCR5_DXREFISELR1_MASK | DDR_PHY_DX2GCR5_RESERVED_7_MASK | DDR_PHY_DX2GCR5_DXREFISELR0_MASK | 0 ); + * DATX8 n General Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD080A04, 0xFFFFFFFFU ,0x00007FFFU) + */ + PSU_Mask_Write(DDR_PHY_DX3GCR1_OFFSET, 0xFFFFFFFFU, 0x00007FFFU); +/*##################################################################### */ - RegVal = ((0x00000000U << DDR_PHY_DX2GCR5_RESERVED_31_SHIFT - | 0x00000009U << DDR_PHY_DX2GCR5_DXREFISELR3_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR5_RESERVED_23_SHIFT - | 0x00000009U << DDR_PHY_DX2GCR5_DXREFISELR2_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR5_RESERVED_15_SHIFT - | 0x0000004FU << DDR_PHY_DX2GCR5_DXREFISELR1_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR5_RESERVED_7_SHIFT - | 0x0000004FU << DDR_PHY_DX2GCR5_DXREFISELR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX2GCR5_OFFSET ,0xFFFFFFFFU ,0x09094F4FU); - /*############################################################################################################################ */ + /* + * Register : DX3GCR4 @ 0XFD080A10 - /*Register : DX2GCR6 @ 0XFD080918

+ * Byte lane VREF IOM (Used only by D4MU IOs) + * PSU_DDR_PHY_DX3GCR4_RESERVED_31_29 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX2GCR6_RESERVED_31_30 0x0 + * Byte Lane VREF Pad Enable + * PSU_DDR_PHY_DX3GCR4_DXREFPEN 0x0 - DRAM DQ VREF Select for Rank3 - PSU_DDR_PHY_DX2GCR6_DXDQVREFR3 0x9 + * Byte Lane Internal VREF Enable + * PSU_DDR_PHY_DX3GCR4_DXREFEEN 0x3 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX2GCR6_RESERVED_23_22 0x0 + * Byte Lane Single-End VREF Enable + * PSU_DDR_PHY_DX3GCR4_DXREFSEN 0x1 - DRAM DQ VREF Select for Rank2 - PSU_DDR_PHY_DX2GCR6_DXDQVREFR2 0x9 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX3GCR4_RESERVED_24 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX2GCR6_RESERVED_15_14 0x0 + * External VREF generator REFSEL range select + * PSU_DDR_PHY_DX3GCR4_DXREFESELRANGE 0x0 - DRAM DQ VREF Select for Rank1 - PSU_DDR_PHY_DX2GCR6_DXDQVREFR1 0x2b + * Byte Lane External VREF Select + * PSU_DDR_PHY_DX3GCR4_DXREFESEL 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX2GCR6_RESERVED_7_6 0x0 + * Single ended VREF generator REFSEL range select + * PSU_DDR_PHY_DX3GCR4_DXREFSSELRANGE 0x1 - DRAM DQ VREF Select for Rank0 - PSU_DDR_PHY_DX2GCR6_DXDQVREFR0 0x2b + * Byte Lane Single-End VREF Select + * PSU_DDR_PHY_DX3GCR4_DXREFSSEL 0x30 - DATX8 n General Configuration Register 6 - (OFFSET, MASK, VALUE) (0XFD080918, 0xFFFFFFFFU ,0x09092B2BU) - RegMask = (DDR_PHY_DX2GCR6_RESERVED_31_30_MASK | DDR_PHY_DX2GCR6_DXDQVREFR3_MASK | DDR_PHY_DX2GCR6_RESERVED_23_22_MASK | DDR_PHY_DX2GCR6_DXDQVREFR2_MASK | DDR_PHY_DX2GCR6_RESERVED_15_14_MASK | DDR_PHY_DX2GCR6_DXDQVREFR1_MASK | DDR_PHY_DX2GCR6_RESERVED_7_6_MASK | DDR_PHY_DX2GCR6_DXDQVREFR0_MASK | 0 ); + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX3GCR4_RESERVED_7_6 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX2GCR6_RESERVED_31_30_SHIFT - | 0x00000009U << DDR_PHY_DX2GCR6_DXDQVREFR3_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR6_RESERVED_23_22_SHIFT - | 0x00000009U << DDR_PHY_DX2GCR6_DXDQVREFR2_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR6_RESERVED_15_14_SHIFT - | 0x0000002BU << DDR_PHY_DX2GCR6_DXDQVREFR1_SHIFT - | 0x00000000U << DDR_PHY_DX2GCR6_RESERVED_7_6_SHIFT - | 0x0000002BU << DDR_PHY_DX2GCR6_DXDQVREFR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX2GCR6_OFFSET ,0xFFFFFFFFU ,0x09092B2BU); - /*############################################################################################################################ */ + * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX3GCR4_DXREFIEN 0xf - /*Register : DX2LCDLR2 @ 0XFD080988

+ * VRMON control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX3GCR4_DXREFIMON 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX2LCDLR2_RESERVED_31_25 0x0 + * DATX8 n General Configuration Register 4 + * (OFFSET, MASK, VALUE) (0XFD080A10, 0xFFFFFFFFU ,0x0E00B03CU) + */ + PSU_Mask_Write(DDR_PHY_DX3GCR4_OFFSET, 0xFFFFFFFFU, 0x0E00B03CU); +/*##################################################################### */ - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX2LCDLR2_RESERVED_24_16 0x0 + /* + * Register : DX3GCR5 @ 0XFD080A14 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX2LCDLR2_RESERVED_15_9 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX3GCR5_RESERVED_31 0x0 - Read DQS Gating Delay - PSU_DDR_PHY_DX2LCDLR2_DQSGD 0x0 + * Byte Lane internal VREF Select for Rank 3 + * PSU_DDR_PHY_DX3GCR5_DXREFISELR3 0x9 - DATX8 n Local Calibrated Delay Line Register 2 - (OFFSET, MASK, VALUE) (0XFD080988, 0xFFFFFFFFU ,0x00000000U) - RegMask = (DDR_PHY_DX2LCDLR2_RESERVED_31_25_MASK | DDR_PHY_DX2LCDLR2_RESERVED_24_16_MASK | DDR_PHY_DX2LCDLR2_RESERVED_15_9_MASK | DDR_PHY_DX2LCDLR2_DQSGD_MASK | 0 ); + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX3GCR5_RESERVED_23 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX2LCDLR2_RESERVED_31_25_SHIFT - | 0x00000000U << DDR_PHY_DX2LCDLR2_RESERVED_24_16_SHIFT - | 0x00000000U << DDR_PHY_DX2LCDLR2_RESERVED_15_9_SHIFT - | 0x00000000U << DDR_PHY_DX2LCDLR2_DQSGD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX2LCDLR2_OFFSET ,0xFFFFFFFFU ,0x00000000U); - /*############################################################################################################################ */ + * Byte Lane internal VREF Select for Rank 2 + * PSU_DDR_PHY_DX3GCR5_DXREFISELR2 0x9 - /*Register : DX2GTR0 @ 0XFD0809C0

+ * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX3GCR5_RESERVED_15 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX2GTR0_RESERVED_31_24 0x0 + * Byte Lane internal VREF Select for Rank 1 + * PSU_DDR_PHY_DX3GCR5_DXREFISELR1 0x55 - DQ Write Path Latency Pipeline - PSU_DDR_PHY_DX2GTR0_WDQSL 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX3GCR5_RESERVED_7 0x0 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX2GTR0_RESERVED_23_20 0x0 + * Byte Lane internal VREF Select for Rank 0 + * PSU_DDR_PHY_DX3GCR5_DXREFISELR0 0x55 - Write Leveling System Latency - PSU_DDR_PHY_DX2GTR0_WLSL 0x2 + * DATX8 n General Configuration Register 5 + * (OFFSET, MASK, VALUE) (0XFD080A14, 0xFFFFFFFFU ,0x09095555U) + */ + PSU_Mask_Write(DDR_PHY_DX3GCR5_OFFSET, 0xFFFFFFFFU, 0x09095555U); +/*##################################################################### */ - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX2GTR0_RESERVED_15_13 0x0 + /* + * Register : DX3GCR6 @ 0XFD080A18 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX2GTR0_RESERVED_12_8 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX3GCR6_RESERVED_31_30 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX2GTR0_RESERVED_7_5 0x0 + * DRAM DQ VREF Select for Rank3 + * PSU_DDR_PHY_DX3GCR6_DXDQVREFR3 0x9 - DQS Gating System Latency - PSU_DDR_PHY_DX2GTR0_DGSL 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX3GCR6_RESERVED_23_22 0x0 - DATX8 n General Timing Register 0 - (OFFSET, MASK, VALUE) (0XFD0809C0, 0xFFFFFFFFU ,0x00020000U) - RegMask = (DDR_PHY_DX2GTR0_RESERVED_31_24_MASK | DDR_PHY_DX2GTR0_WDQSL_MASK | DDR_PHY_DX2GTR0_RESERVED_23_20_MASK | DDR_PHY_DX2GTR0_WLSL_MASK | DDR_PHY_DX2GTR0_RESERVED_15_13_MASK | DDR_PHY_DX2GTR0_RESERVED_12_8_MASK | DDR_PHY_DX2GTR0_RESERVED_7_5_MASK | DDR_PHY_DX2GTR0_DGSL_MASK | 0 ); + * DRAM DQ VREF Select for Rank2 + * PSU_DDR_PHY_DX3GCR6_DXDQVREFR2 0x9 - RegVal = ((0x00000000U << DDR_PHY_DX2GTR0_RESERVED_31_24_SHIFT - | 0x00000000U << DDR_PHY_DX2GTR0_WDQSL_SHIFT - | 0x00000000U << DDR_PHY_DX2GTR0_RESERVED_23_20_SHIFT - | 0x00000002U << DDR_PHY_DX2GTR0_WLSL_SHIFT - | 0x00000000U << DDR_PHY_DX2GTR0_RESERVED_15_13_SHIFT - | 0x00000000U << DDR_PHY_DX2GTR0_RESERVED_12_8_SHIFT - | 0x00000000U << DDR_PHY_DX2GTR0_RESERVED_7_5_SHIFT - | 0x00000000U << DDR_PHY_DX2GTR0_DGSL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX2GTR0_OFFSET ,0xFFFFFFFFU ,0x00020000U); - /*############################################################################################################################ */ + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX3GCR6_RESERVED_15_14 0x0 - /*Register : DX3GCR0 @ 0XFD080A00

+ * DRAM DQ VREF Select for Rank1 + * PSU_DDR_PHY_DX3GCR6_DXDQVREFR1 0x2b - Calibration Bypass - PSU_DDR_PHY_DX3GCR0_CALBYP 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX3GCR6_RESERVED_7_6 0x0 - Master Delay Line Enable - PSU_DDR_PHY_DX3GCR0_MDLEN 0x1 + * DRAM DQ VREF Select for Rank0 + * PSU_DDR_PHY_DX3GCR6_DXDQVREFR0 0x2b - Configurable ODT(TE) Phase Shift - PSU_DDR_PHY_DX3GCR0_CODTSHFT 0x0 + * DATX8 n General Configuration Register 6 + * (OFFSET, MASK, VALUE) (0XFD080A18, 0xFFFFFFFFU ,0x09092B2BU) + */ + PSU_Mask_Write(DDR_PHY_DX3GCR6_OFFSET, 0xFFFFFFFFU, 0x09092B2BU); +/*##################################################################### */ - DQS Duty Cycle Correction - PSU_DDR_PHY_DX3GCR0_DQSDCC 0x0 + /* + * Register : DX4GCR0 @ 0XFD080B00 - Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY - PSU_DDR_PHY_DX3GCR0_RDDLY 0x8 + * Calibration Bypass + * PSU_DDR_PHY_DX4GCR0_CALBYP 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX3GCR0_RESERVED_19_14 0x0 + * Master Delay Line Enable + * PSU_DDR_PHY_DX4GCR0_MDLEN 0x1 - DQSNSE Power Down Receiver - PSU_DDR_PHY_DX3GCR0_DQSNSEPDR 0x0 + * Configurable ODT(TE) Phase Shift + * PSU_DDR_PHY_DX4GCR0_CODTSHFT 0x0 - DQSSE Power Down Receiver - PSU_DDR_PHY_DX3GCR0_DQSSEPDR 0x0 + * DQS Duty Cycle Correction + * PSU_DDR_PHY_DX4GCR0_DQSDCC 0x0 - RTT On Additive Latency - PSU_DDR_PHY_DX3GCR0_RTTOAL 0x0 + * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY + * PSU_DDR_PHY_DX4GCR0_RDDLY 0x8 - RTT Output Hold - PSU_DDR_PHY_DX3GCR0_RTTOH 0x3 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX4GCR0_RESERVED_19_14 0x0 - Configurable PDR Phase Shift - PSU_DDR_PHY_DX3GCR0_CPDRSHFT 0x0 + * DQSNSE Power Down Receiver + * PSU_DDR_PHY_DX4GCR0_DQSNSEPDR 0x0 - DQSR Power Down - PSU_DDR_PHY_DX3GCR0_DQSRPD 0x0 + * DQSSE Power Down Receiver + * PSU_DDR_PHY_DX4GCR0_DQSSEPDR 0x0 - DQSG Power Down Receiver - PSU_DDR_PHY_DX3GCR0_DQSGPDR 0x0 + * RTT On Additive Latency + * PSU_DDR_PHY_DX4GCR0_RTTOAL 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX3GCR0_RESERVED_4 0x0 + * RTT Output Hold + * PSU_DDR_PHY_DX4GCR0_RTTOH 0x3 - DQSG On-Die Termination - PSU_DDR_PHY_DX3GCR0_DQSGODT 0x0 + * Configurable PDR Phase Shift + * PSU_DDR_PHY_DX4GCR0_CPDRSHFT 0x0 - DQSG Output Enable - PSU_DDR_PHY_DX3GCR0_DQSGOE 0x1 + * DQSR Power Down + * PSU_DDR_PHY_DX4GCR0_DQSRPD 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX3GCR0_RESERVED_1_0 0x0 + * DQSG Power Down Receiver + * PSU_DDR_PHY_DX4GCR0_DQSGPDR 0x0 - DATX8 n General Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD080A00, 0xFFFFFFFFU ,0x40800604U) - RegMask = (DDR_PHY_DX3GCR0_CALBYP_MASK | DDR_PHY_DX3GCR0_MDLEN_MASK | DDR_PHY_DX3GCR0_CODTSHFT_MASK | DDR_PHY_DX3GCR0_DQSDCC_MASK | DDR_PHY_DX3GCR0_RDDLY_MASK | DDR_PHY_DX3GCR0_RESERVED_19_14_MASK | DDR_PHY_DX3GCR0_DQSNSEPDR_MASK | DDR_PHY_DX3GCR0_DQSSEPDR_MASK | DDR_PHY_DX3GCR0_RTTOAL_MASK | DDR_PHY_DX3GCR0_RTTOH_MASK | DDR_PHY_DX3GCR0_CPDRSHFT_MASK | DDR_PHY_DX3GCR0_DQSRPD_MASK | DDR_PHY_DX3GCR0_DQSGPDR_MASK | DDR_PHY_DX3GCR0_RESERVED_4_MASK | DDR_PHY_DX3GCR0_DQSGODT_MASK | DDR_PHY_DX3GCR0_DQSGOE_MASK | DDR_PHY_DX3GCR0_RESERVED_1_0_MASK | 0 ); + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX4GCR0_RESERVED_4 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX3GCR0_CALBYP_SHIFT - | 0x00000001U << DDR_PHY_DX3GCR0_MDLEN_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR0_CODTSHFT_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR0_DQSDCC_SHIFT - | 0x00000008U << DDR_PHY_DX3GCR0_RDDLY_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR0_RESERVED_19_14_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR0_DQSNSEPDR_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR0_DQSSEPDR_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR0_RTTOAL_SHIFT - | 0x00000003U << DDR_PHY_DX3GCR0_RTTOH_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR0_CPDRSHFT_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR0_DQSRPD_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR0_DQSGPDR_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR0_RESERVED_4_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR0_DQSGODT_SHIFT - | 0x00000001U << DDR_PHY_DX3GCR0_DQSGOE_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR0_RESERVED_1_0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX3GCR0_OFFSET ,0xFFFFFFFFU ,0x40800604U); - /*############################################################################################################################ */ + * DQSG On-Die Termination + * PSU_DDR_PHY_DX4GCR0_DQSGODT 0x0 - /*Register : DX3GCR1 @ 0XFD080A04

+ * DQSG Output Enable + * PSU_DDR_PHY_DX4GCR0_DQSGOE 0x1 - Enables the PDR mode for DQ[7:0] - PSU_DDR_PHY_DX3GCR1_DXPDRMODE 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX4GCR0_RESERVED_1_0 0x0 - Reserved. Returns zeroes on reads. - PSU_DDR_PHY_DX3GCR1_RESERVED_15 0x0 + * DATX8 n General Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD080B00, 0xFFFFFFFFU ,0x40800604U) + */ + PSU_Mask_Write(DDR_PHY_DX4GCR0_OFFSET, 0xFFFFFFFFU, 0x40800604U); +/*##################################################################### */ - Select the delayed or non-delayed read data strobe # - PSU_DDR_PHY_DX3GCR1_QSNSEL 0x1 + /* + * Register : DX4GCR1 @ 0XFD080B04 - Select the delayed or non-delayed read data strobe - PSU_DDR_PHY_DX3GCR1_QSSEL 0x1 + * Enables the PDR mode for DQ[7:0] + * PSU_DDR_PHY_DX4GCR1_DXPDRMODE 0x0 - Enables Read Data Strobe in a byte lane - PSU_DDR_PHY_DX3GCR1_OEEN 0x1 + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX4GCR1_RESERVED_15 0x0 - Enables PDR in a byte lane - PSU_DDR_PHY_DX3GCR1_PDREN 0x1 + * Select the delayed or non-delayed read data strobe # + * PSU_DDR_PHY_DX4GCR1_QSNSEL 0x1 - Enables ODT/TE in a byte lane - PSU_DDR_PHY_DX3GCR1_TEEN 0x1 + * Select the delayed or non-delayed read data strobe + * PSU_DDR_PHY_DX4GCR1_QSSEL 0x1 - Enables Write Data strobe in a byte lane - PSU_DDR_PHY_DX3GCR1_DSEN 0x1 + * Enables Read Data Strobe in a byte lane + * PSU_DDR_PHY_DX4GCR1_OEEN 0x1 - Enables DM pin in a byte lane - PSU_DDR_PHY_DX3GCR1_DMEN 0x1 + * Enables PDR in a byte lane + * PSU_DDR_PHY_DX4GCR1_PDREN 0x1 - Enables DQ corresponding to each bit in a byte - PSU_DDR_PHY_DX3GCR1_DQEN 0xff + * Enables ODT/TE in a byte lane + * PSU_DDR_PHY_DX4GCR1_TEEN 0x1 - DATX8 n General Configuration Register 1 - (OFFSET, MASK, VALUE) (0XFD080A04, 0xFFFFFFFFU ,0x00007FFFU) - RegMask = (DDR_PHY_DX3GCR1_DXPDRMODE_MASK | DDR_PHY_DX3GCR1_RESERVED_15_MASK | DDR_PHY_DX3GCR1_QSNSEL_MASK | DDR_PHY_DX3GCR1_QSSEL_MASK | DDR_PHY_DX3GCR1_OEEN_MASK | DDR_PHY_DX3GCR1_PDREN_MASK | DDR_PHY_DX3GCR1_TEEN_MASK | DDR_PHY_DX3GCR1_DSEN_MASK | DDR_PHY_DX3GCR1_DMEN_MASK | DDR_PHY_DX3GCR1_DQEN_MASK | 0 ); + * Enables Write Data strobe in a byte lane + * PSU_DDR_PHY_DX4GCR1_DSEN 0x1 - RegVal = ((0x00000000U << DDR_PHY_DX3GCR1_DXPDRMODE_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR1_RESERVED_15_SHIFT - | 0x00000001U << DDR_PHY_DX3GCR1_QSNSEL_SHIFT - | 0x00000001U << DDR_PHY_DX3GCR1_QSSEL_SHIFT - | 0x00000001U << DDR_PHY_DX3GCR1_OEEN_SHIFT - | 0x00000001U << DDR_PHY_DX3GCR1_PDREN_SHIFT - | 0x00000001U << DDR_PHY_DX3GCR1_TEEN_SHIFT - | 0x00000001U << DDR_PHY_DX3GCR1_DSEN_SHIFT - | 0x00000001U << DDR_PHY_DX3GCR1_DMEN_SHIFT - | 0x000000FFU << DDR_PHY_DX3GCR1_DQEN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX3GCR1_OFFSET ,0xFFFFFFFFU ,0x00007FFFU); - /*############################################################################################################################ */ + * Enables DM pin in a byte lane + * PSU_DDR_PHY_DX4GCR1_DMEN 0x1 - /*Register : DX3GCR4 @ 0XFD080A10

+ * Enables DQ corresponding to each bit in a byte + * PSU_DDR_PHY_DX4GCR1_DQEN 0xff - Byte lane VREF IOM (Used only by D4MU IOs) - PSU_DDR_PHY_DX3GCR4_RESERVED_31_29 0x0 + * DATX8 n General Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD080B04, 0xFFFFFFFFU ,0x00007FFFU) + */ + PSU_Mask_Write(DDR_PHY_DX4GCR1_OFFSET, 0xFFFFFFFFU, 0x00007FFFU); +/*##################################################################### */ - Byte Lane VREF Pad Enable - PSU_DDR_PHY_DX3GCR4_DXREFPEN 0x0 + /* + * Register : DX4GCR4 @ 0XFD080B10 - Byte Lane Internal VREF Enable - PSU_DDR_PHY_DX3GCR4_DXREFEEN 0x3 + * Byte lane VREF IOM (Used only by D4MU IOs) + * PSU_DDR_PHY_DX4GCR4_RESERVED_31_29 0x0 - Byte Lane Single-End VREF Enable - PSU_DDR_PHY_DX3GCR4_DXREFSEN 0x1 + * Byte Lane VREF Pad Enable + * PSU_DDR_PHY_DX4GCR4_DXREFPEN 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX3GCR4_RESERVED_24 0x0 + * Byte Lane Internal VREF Enable + * PSU_DDR_PHY_DX4GCR4_DXREFEEN 0x3 - External VREF generator REFSEL range select - PSU_DDR_PHY_DX3GCR4_DXREFESELRANGE 0x0 + * Byte Lane Single-End VREF Enable + * PSU_DDR_PHY_DX4GCR4_DXREFSEN 0x1 - Byte Lane External VREF Select - PSU_DDR_PHY_DX3GCR4_DXREFESEL 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX4GCR4_RESERVED_24 0x0 - Single ended VREF generator REFSEL range select - PSU_DDR_PHY_DX3GCR4_DXREFSSELRANGE 0x1 + * External VREF generator REFSEL range select + * PSU_DDR_PHY_DX4GCR4_DXREFESELRANGE 0x0 - Byte Lane Single-End VREF Select - PSU_DDR_PHY_DX3GCR4_DXREFSSEL 0x30 + * Byte Lane External VREF Select + * PSU_DDR_PHY_DX4GCR4_DXREFESEL 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX3GCR4_RESERVED_7_6 0x0 + * Single ended VREF generator REFSEL range select + * PSU_DDR_PHY_DX4GCR4_DXREFSSELRANGE 0x1 - VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. - PSU_DDR_PHY_DX3GCR4_DXREFIEN 0xf + * Byte Lane Single-End VREF Select + * PSU_DDR_PHY_DX4GCR4_DXREFSSEL 0x30 - VRMON control for DQ IO (Single Ended) buffers of a byte lane. - PSU_DDR_PHY_DX3GCR4_DXREFIMON 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX4GCR4_RESERVED_7_6 0x0 - DATX8 n General Configuration Register 4 - (OFFSET, MASK, VALUE) (0XFD080A10, 0xFFFFFFFFU ,0x0E00B03CU) - RegMask = (DDR_PHY_DX3GCR4_RESERVED_31_29_MASK | DDR_PHY_DX3GCR4_DXREFPEN_MASK | DDR_PHY_DX3GCR4_DXREFEEN_MASK | DDR_PHY_DX3GCR4_DXREFSEN_MASK | DDR_PHY_DX3GCR4_RESERVED_24_MASK | DDR_PHY_DX3GCR4_DXREFESELRANGE_MASK | DDR_PHY_DX3GCR4_DXREFESEL_MASK | DDR_PHY_DX3GCR4_DXREFSSELRANGE_MASK | DDR_PHY_DX3GCR4_DXREFSSEL_MASK | DDR_PHY_DX3GCR4_RESERVED_7_6_MASK | DDR_PHY_DX3GCR4_DXREFIEN_MASK | DDR_PHY_DX3GCR4_DXREFIMON_MASK | 0 ); + * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX4GCR4_DXREFIEN 0xf - RegVal = ((0x00000000U << DDR_PHY_DX3GCR4_RESERVED_31_29_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR4_DXREFPEN_SHIFT - | 0x00000003U << DDR_PHY_DX3GCR4_DXREFEEN_SHIFT - | 0x00000001U << DDR_PHY_DX3GCR4_DXREFSEN_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR4_RESERVED_24_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR4_DXREFESELRANGE_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR4_DXREFESEL_SHIFT - | 0x00000001U << DDR_PHY_DX3GCR4_DXREFSSELRANGE_SHIFT - | 0x00000030U << DDR_PHY_DX3GCR4_DXREFSSEL_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR4_RESERVED_7_6_SHIFT - | 0x0000000FU << DDR_PHY_DX3GCR4_DXREFIEN_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR4_DXREFIMON_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX3GCR4_OFFSET ,0xFFFFFFFFU ,0x0E00B03CU); - /*############################################################################################################################ */ + * VRMON control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX4GCR4_DXREFIMON 0x0 - /*Register : DX3GCR5 @ 0XFD080A14

+ * DATX8 n General Configuration Register 4 + * (OFFSET, MASK, VALUE) (0XFD080B10, 0xFFFFFFFFU ,0x0E00B03CU) + */ + PSU_Mask_Write(DDR_PHY_DX4GCR4_OFFSET, 0xFFFFFFFFU, 0x0E00B03CU); +/*##################################################################### */ - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX3GCR5_RESERVED_31 0x0 + /* + * Register : DX4GCR5 @ 0XFD080B14 - Byte Lane internal VREF Select for Rank 3 - PSU_DDR_PHY_DX3GCR5_DXREFISELR3 0x9 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX4GCR5_RESERVED_31 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX3GCR5_RESERVED_23 0x0 + * Byte Lane internal VREF Select for Rank 3 + * PSU_DDR_PHY_DX4GCR5_DXREFISELR3 0x9 - Byte Lane internal VREF Select for Rank 2 - PSU_DDR_PHY_DX3GCR5_DXREFISELR2 0x9 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX4GCR5_RESERVED_23 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX3GCR5_RESERVED_15 0x0 + * Byte Lane internal VREF Select for Rank 2 + * PSU_DDR_PHY_DX4GCR5_DXREFISELR2 0x9 - Byte Lane internal VREF Select for Rank 1 - PSU_DDR_PHY_DX3GCR5_DXREFISELR1 0x4f + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX4GCR5_RESERVED_15 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX3GCR5_RESERVED_7 0x0 + * Byte Lane internal VREF Select for Rank 1 + * PSU_DDR_PHY_DX4GCR5_DXREFISELR1 0x55 - Byte Lane internal VREF Select for Rank 0 - PSU_DDR_PHY_DX3GCR5_DXREFISELR0 0x4f + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX4GCR5_RESERVED_7 0x0 - DATX8 n General Configuration Register 5 - (OFFSET, MASK, VALUE) (0XFD080A14, 0xFFFFFFFFU ,0x09094F4FU) - RegMask = (DDR_PHY_DX3GCR5_RESERVED_31_MASK | DDR_PHY_DX3GCR5_DXREFISELR3_MASK | DDR_PHY_DX3GCR5_RESERVED_23_MASK | DDR_PHY_DX3GCR5_DXREFISELR2_MASK | DDR_PHY_DX3GCR5_RESERVED_15_MASK | DDR_PHY_DX3GCR5_DXREFISELR1_MASK | DDR_PHY_DX3GCR5_RESERVED_7_MASK | DDR_PHY_DX3GCR5_DXREFISELR0_MASK | 0 ); + * Byte Lane internal VREF Select for Rank 0 + * PSU_DDR_PHY_DX4GCR5_DXREFISELR0 0x55 - RegVal = ((0x00000000U << DDR_PHY_DX3GCR5_RESERVED_31_SHIFT - | 0x00000009U << DDR_PHY_DX3GCR5_DXREFISELR3_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR5_RESERVED_23_SHIFT - | 0x00000009U << DDR_PHY_DX3GCR5_DXREFISELR2_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR5_RESERVED_15_SHIFT - | 0x0000004FU << DDR_PHY_DX3GCR5_DXREFISELR1_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR5_RESERVED_7_SHIFT - | 0x0000004FU << DDR_PHY_DX3GCR5_DXREFISELR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX3GCR5_OFFSET ,0xFFFFFFFFU ,0x09094F4FU); - /*############################################################################################################################ */ + * DATX8 n General Configuration Register 5 + * (OFFSET, MASK, VALUE) (0XFD080B14, 0xFFFFFFFFU ,0x09095555U) + */ + PSU_Mask_Write(DDR_PHY_DX4GCR5_OFFSET, 0xFFFFFFFFU, 0x09095555U); +/*##################################################################### */ - /*Register : DX3GCR6 @ 0XFD080A18

+ /* + * Register : DX4GCR6 @ 0XFD080B18 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX3GCR6_RESERVED_31_30 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX4GCR6_RESERVED_31_30 0x0 - DRAM DQ VREF Select for Rank3 - PSU_DDR_PHY_DX3GCR6_DXDQVREFR3 0x9 + * DRAM DQ VREF Select for Rank3 + * PSU_DDR_PHY_DX4GCR6_DXDQVREFR3 0x9 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX3GCR6_RESERVED_23_22 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX4GCR6_RESERVED_23_22 0x0 - DRAM DQ VREF Select for Rank2 - PSU_DDR_PHY_DX3GCR6_DXDQVREFR2 0x9 + * DRAM DQ VREF Select for Rank2 + * PSU_DDR_PHY_DX4GCR6_DXDQVREFR2 0x9 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX3GCR6_RESERVED_15_14 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX4GCR6_RESERVED_15_14 0x0 - DRAM DQ VREF Select for Rank1 - PSU_DDR_PHY_DX3GCR6_DXDQVREFR1 0x2b + * DRAM DQ VREF Select for Rank1 + * PSU_DDR_PHY_DX4GCR6_DXDQVREFR1 0x2b - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX3GCR6_RESERVED_7_6 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX4GCR6_RESERVED_7_6 0x0 - DRAM DQ VREF Select for Rank0 - PSU_DDR_PHY_DX3GCR6_DXDQVREFR0 0x2b + * DRAM DQ VREF Select for Rank0 + * PSU_DDR_PHY_DX4GCR6_DXDQVREFR0 0x2b - DATX8 n General Configuration Register 6 - (OFFSET, MASK, VALUE) (0XFD080A18, 0xFFFFFFFFU ,0x09092B2BU) - RegMask = (DDR_PHY_DX3GCR6_RESERVED_31_30_MASK | DDR_PHY_DX3GCR6_DXDQVREFR3_MASK | DDR_PHY_DX3GCR6_RESERVED_23_22_MASK | DDR_PHY_DX3GCR6_DXDQVREFR2_MASK | DDR_PHY_DX3GCR6_RESERVED_15_14_MASK | DDR_PHY_DX3GCR6_DXDQVREFR1_MASK | DDR_PHY_DX3GCR6_RESERVED_7_6_MASK | DDR_PHY_DX3GCR6_DXDQVREFR0_MASK | 0 ); + * DATX8 n General Configuration Register 6 + * (OFFSET, MASK, VALUE) (0XFD080B18, 0xFFFFFFFFU ,0x09092B2BU) + */ + PSU_Mask_Write(DDR_PHY_DX4GCR6_OFFSET, 0xFFFFFFFFU, 0x09092B2BU); +/*##################################################################### */ - RegVal = ((0x00000000U << DDR_PHY_DX3GCR6_RESERVED_31_30_SHIFT - | 0x00000009U << DDR_PHY_DX3GCR6_DXDQVREFR3_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR6_RESERVED_23_22_SHIFT - | 0x00000009U << DDR_PHY_DX3GCR6_DXDQVREFR2_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR6_RESERVED_15_14_SHIFT - | 0x0000002BU << DDR_PHY_DX3GCR6_DXDQVREFR1_SHIFT - | 0x00000000U << DDR_PHY_DX3GCR6_RESERVED_7_6_SHIFT - | 0x0000002BU << DDR_PHY_DX3GCR6_DXDQVREFR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX3GCR6_OFFSET ,0xFFFFFFFFU ,0x09092B2BU); - /*############################################################################################################################ */ + /* + * Register : DX5GCR0 @ 0XFD080C00 - /*Register : DX3LCDLR2 @ 0XFD080A88

+ * Calibration Bypass + * PSU_DDR_PHY_DX5GCR0_CALBYP 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX3LCDLR2_RESERVED_31_25 0x0 + * Master Delay Line Enable + * PSU_DDR_PHY_DX5GCR0_MDLEN 0x1 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX3LCDLR2_RESERVED_24_16 0x0 + * Configurable ODT(TE) Phase Shift + * PSU_DDR_PHY_DX5GCR0_CODTSHFT 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX3LCDLR2_RESERVED_15_9 0x0 + * DQS Duty Cycle Correction + * PSU_DDR_PHY_DX5GCR0_DQSDCC 0x0 - Read DQS Gating Delay - PSU_DDR_PHY_DX3LCDLR2_DQSGD 0x0 + * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY + * PSU_DDR_PHY_DX5GCR0_RDDLY 0x8 - DATX8 n Local Calibrated Delay Line Register 2 - (OFFSET, MASK, VALUE) (0XFD080A88, 0xFFFFFFFFU ,0x00000000U) - RegMask = (DDR_PHY_DX3LCDLR2_RESERVED_31_25_MASK | DDR_PHY_DX3LCDLR2_RESERVED_24_16_MASK | DDR_PHY_DX3LCDLR2_RESERVED_15_9_MASK | DDR_PHY_DX3LCDLR2_DQSGD_MASK | 0 ); + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX5GCR0_RESERVED_19_14 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX3LCDLR2_RESERVED_31_25_SHIFT - | 0x00000000U << DDR_PHY_DX3LCDLR2_RESERVED_24_16_SHIFT - | 0x00000000U << DDR_PHY_DX3LCDLR2_RESERVED_15_9_SHIFT - | 0x00000000U << DDR_PHY_DX3LCDLR2_DQSGD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX3LCDLR2_OFFSET ,0xFFFFFFFFU ,0x00000000U); - /*############################################################################################################################ */ + * DQSNSE Power Down Receiver + * PSU_DDR_PHY_DX5GCR0_DQSNSEPDR 0x0 - /*Register : DX3GTR0 @ 0XFD080AC0

+ * DQSSE Power Down Receiver + * PSU_DDR_PHY_DX5GCR0_DQSSEPDR 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX3GTR0_RESERVED_31_24 0x0 + * RTT On Additive Latency + * PSU_DDR_PHY_DX5GCR0_RTTOAL 0x0 - DQ Write Path Latency Pipeline - PSU_DDR_PHY_DX3GTR0_WDQSL 0x0 + * RTT Output Hold + * PSU_DDR_PHY_DX5GCR0_RTTOH 0x3 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX3GTR0_RESERVED_23_20 0x0 + * Configurable PDR Phase Shift + * PSU_DDR_PHY_DX5GCR0_CPDRSHFT 0x0 - Write Leveling System Latency - PSU_DDR_PHY_DX3GTR0_WLSL 0x2 + * DQSR Power Down + * PSU_DDR_PHY_DX5GCR0_DQSRPD 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX3GTR0_RESERVED_15_13 0x0 + * DQSG Power Down Receiver + * PSU_DDR_PHY_DX5GCR0_DQSGPDR 0x0 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX3GTR0_RESERVED_12_8 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX5GCR0_RESERVED_4 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX3GTR0_RESERVED_7_5 0x0 + * DQSG On-Die Termination + * PSU_DDR_PHY_DX5GCR0_DQSGODT 0x0 - DQS Gating System Latency - PSU_DDR_PHY_DX3GTR0_DGSL 0x0 + * DQSG Output Enable + * PSU_DDR_PHY_DX5GCR0_DQSGOE 0x1 - DATX8 n General Timing Register 0 - (OFFSET, MASK, VALUE) (0XFD080AC0, 0xFFFFFFFFU ,0x00020000U) - RegMask = (DDR_PHY_DX3GTR0_RESERVED_31_24_MASK | DDR_PHY_DX3GTR0_WDQSL_MASK | DDR_PHY_DX3GTR0_RESERVED_23_20_MASK | DDR_PHY_DX3GTR0_WLSL_MASK | DDR_PHY_DX3GTR0_RESERVED_15_13_MASK | DDR_PHY_DX3GTR0_RESERVED_12_8_MASK | DDR_PHY_DX3GTR0_RESERVED_7_5_MASK | DDR_PHY_DX3GTR0_DGSL_MASK | 0 ); + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX5GCR0_RESERVED_1_0 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX3GTR0_RESERVED_31_24_SHIFT - | 0x00000000U << DDR_PHY_DX3GTR0_WDQSL_SHIFT - | 0x00000000U << DDR_PHY_DX3GTR0_RESERVED_23_20_SHIFT - | 0x00000002U << DDR_PHY_DX3GTR0_WLSL_SHIFT - | 0x00000000U << DDR_PHY_DX3GTR0_RESERVED_15_13_SHIFT - | 0x00000000U << DDR_PHY_DX3GTR0_RESERVED_12_8_SHIFT - | 0x00000000U << DDR_PHY_DX3GTR0_RESERVED_7_5_SHIFT - | 0x00000000U << DDR_PHY_DX3GTR0_DGSL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX3GTR0_OFFSET ,0xFFFFFFFFU ,0x00020000U); - /*############################################################################################################################ */ + * DATX8 n General Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD080C00, 0xFFFFFFFFU ,0x40800604U) + */ + PSU_Mask_Write(DDR_PHY_DX5GCR0_OFFSET, 0xFFFFFFFFU, 0x40800604U); +/*##################################################################### */ - /*Register : DX4GCR0 @ 0XFD080B00

+ /* + * Register : DX5GCR1 @ 0XFD080C04 - Calibration Bypass - PSU_DDR_PHY_DX4GCR0_CALBYP 0x0 + * Enables the PDR mode for DQ[7:0] + * PSU_DDR_PHY_DX5GCR1_DXPDRMODE 0x0 - Master Delay Line Enable - PSU_DDR_PHY_DX4GCR0_MDLEN 0x1 + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX5GCR1_RESERVED_15 0x0 - Configurable ODT(TE) Phase Shift - PSU_DDR_PHY_DX4GCR0_CODTSHFT 0x0 + * Select the delayed or non-delayed read data strobe # + * PSU_DDR_PHY_DX5GCR1_QSNSEL 0x1 - DQS Duty Cycle Correction - PSU_DDR_PHY_DX4GCR0_DQSDCC 0x0 + * Select the delayed or non-delayed read data strobe + * PSU_DDR_PHY_DX5GCR1_QSSEL 0x1 - Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY - PSU_DDR_PHY_DX4GCR0_RDDLY 0x8 + * Enables Read Data Strobe in a byte lane + * PSU_DDR_PHY_DX5GCR1_OEEN 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX4GCR0_RESERVED_19_14 0x0 + * Enables PDR in a byte lane + * PSU_DDR_PHY_DX5GCR1_PDREN 0x1 - DQSNSE Power Down Receiver - PSU_DDR_PHY_DX4GCR0_DQSNSEPDR 0x0 + * Enables ODT/TE in a byte lane + * PSU_DDR_PHY_DX5GCR1_TEEN 0x1 - DQSSE Power Down Receiver - PSU_DDR_PHY_DX4GCR0_DQSSEPDR 0x0 + * Enables Write Data strobe in a byte lane + * PSU_DDR_PHY_DX5GCR1_DSEN 0x1 - RTT On Additive Latency - PSU_DDR_PHY_DX4GCR0_RTTOAL 0x0 + * Enables DM pin in a byte lane + * PSU_DDR_PHY_DX5GCR1_DMEN 0x1 - RTT Output Hold - PSU_DDR_PHY_DX4GCR0_RTTOH 0x3 + * Enables DQ corresponding to each bit in a byte + * PSU_DDR_PHY_DX5GCR1_DQEN 0xff - Configurable PDR Phase Shift - PSU_DDR_PHY_DX4GCR0_CPDRSHFT 0x0 + * DATX8 n General Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD080C04, 0xFFFFFFFFU ,0x00007FFFU) + */ + PSU_Mask_Write(DDR_PHY_DX5GCR1_OFFSET, 0xFFFFFFFFU, 0x00007FFFU); +/*##################################################################### */ - DQSR Power Down - PSU_DDR_PHY_DX4GCR0_DQSRPD 0x0 + /* + * Register : DX5GCR4 @ 0XFD080C10 - DQSG Power Down Receiver - PSU_DDR_PHY_DX4GCR0_DQSGPDR 0x0 + * Byte lane VREF IOM (Used only by D4MU IOs) + * PSU_DDR_PHY_DX5GCR4_RESERVED_31_29 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX4GCR0_RESERVED_4 0x0 + * Byte Lane VREF Pad Enable + * PSU_DDR_PHY_DX5GCR4_DXREFPEN 0x0 - DQSG On-Die Termination - PSU_DDR_PHY_DX4GCR0_DQSGODT 0x0 + * Byte Lane Internal VREF Enable + * PSU_DDR_PHY_DX5GCR4_DXREFEEN 0x3 - DQSG Output Enable - PSU_DDR_PHY_DX4GCR0_DQSGOE 0x1 + * Byte Lane Single-End VREF Enable + * PSU_DDR_PHY_DX5GCR4_DXREFSEN 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX4GCR0_RESERVED_1_0 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX5GCR4_RESERVED_24 0x0 - DATX8 n General Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD080B00, 0xFFFFFFFFU ,0x40800604U) - RegMask = (DDR_PHY_DX4GCR0_CALBYP_MASK | DDR_PHY_DX4GCR0_MDLEN_MASK | DDR_PHY_DX4GCR0_CODTSHFT_MASK | DDR_PHY_DX4GCR0_DQSDCC_MASK | DDR_PHY_DX4GCR0_RDDLY_MASK | DDR_PHY_DX4GCR0_RESERVED_19_14_MASK | DDR_PHY_DX4GCR0_DQSNSEPDR_MASK | DDR_PHY_DX4GCR0_DQSSEPDR_MASK | DDR_PHY_DX4GCR0_RTTOAL_MASK | DDR_PHY_DX4GCR0_RTTOH_MASK | DDR_PHY_DX4GCR0_CPDRSHFT_MASK | DDR_PHY_DX4GCR0_DQSRPD_MASK | DDR_PHY_DX4GCR0_DQSGPDR_MASK | DDR_PHY_DX4GCR0_RESERVED_4_MASK | DDR_PHY_DX4GCR0_DQSGODT_MASK | DDR_PHY_DX4GCR0_DQSGOE_MASK | DDR_PHY_DX4GCR0_RESERVED_1_0_MASK | 0 ); + * External VREF generator REFSEL range select + * PSU_DDR_PHY_DX5GCR4_DXREFESELRANGE 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX4GCR0_CALBYP_SHIFT - | 0x00000001U << DDR_PHY_DX4GCR0_MDLEN_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR0_CODTSHFT_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR0_DQSDCC_SHIFT - | 0x00000008U << DDR_PHY_DX4GCR0_RDDLY_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR0_RESERVED_19_14_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR0_DQSNSEPDR_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR0_DQSSEPDR_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR0_RTTOAL_SHIFT - | 0x00000003U << DDR_PHY_DX4GCR0_RTTOH_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR0_CPDRSHFT_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR0_DQSRPD_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR0_DQSGPDR_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR0_RESERVED_4_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR0_DQSGODT_SHIFT - | 0x00000001U << DDR_PHY_DX4GCR0_DQSGOE_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR0_RESERVED_1_0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX4GCR0_OFFSET ,0xFFFFFFFFU ,0x40800604U); - /*############################################################################################################################ */ + * Byte Lane External VREF Select + * PSU_DDR_PHY_DX5GCR4_DXREFESEL 0x0 - /*Register : DX4GCR1 @ 0XFD080B04

+ * Single ended VREF generator REFSEL range select + * PSU_DDR_PHY_DX5GCR4_DXREFSSELRANGE 0x1 - Enables the PDR mode for DQ[7:0] - PSU_DDR_PHY_DX4GCR1_DXPDRMODE 0x0 + * Byte Lane Single-End VREF Select + * PSU_DDR_PHY_DX5GCR4_DXREFSSEL 0x30 - Reserved. Returns zeroes on reads. - PSU_DDR_PHY_DX4GCR1_RESERVED_15 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX5GCR4_RESERVED_7_6 0x0 - Select the delayed or non-delayed read data strobe # - PSU_DDR_PHY_DX4GCR1_QSNSEL 0x1 + * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX5GCR4_DXREFIEN 0xf - Select the delayed or non-delayed read data strobe - PSU_DDR_PHY_DX4GCR1_QSSEL 0x1 + * VRMON control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX5GCR4_DXREFIMON 0x0 - Enables Read Data Strobe in a byte lane - PSU_DDR_PHY_DX4GCR1_OEEN 0x1 + * DATX8 n General Configuration Register 4 + * (OFFSET, MASK, VALUE) (0XFD080C10, 0xFFFFFFFFU ,0x0E00B03CU) + */ + PSU_Mask_Write(DDR_PHY_DX5GCR4_OFFSET, 0xFFFFFFFFU, 0x0E00B03CU); +/*##################################################################### */ - Enables PDR in a byte lane - PSU_DDR_PHY_DX4GCR1_PDREN 0x1 + /* + * Register : DX5GCR5 @ 0XFD080C14 - Enables ODT/TE in a byte lane - PSU_DDR_PHY_DX4GCR1_TEEN 0x1 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX5GCR5_RESERVED_31 0x0 - Enables Write Data strobe in a byte lane - PSU_DDR_PHY_DX4GCR1_DSEN 0x1 + * Byte Lane internal VREF Select for Rank 3 + * PSU_DDR_PHY_DX5GCR5_DXREFISELR3 0x9 - Enables DM pin in a byte lane - PSU_DDR_PHY_DX4GCR1_DMEN 0x1 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX5GCR5_RESERVED_23 0x0 - Enables DQ corresponding to each bit in a byte - PSU_DDR_PHY_DX4GCR1_DQEN 0xff + * Byte Lane internal VREF Select for Rank 2 + * PSU_DDR_PHY_DX5GCR5_DXREFISELR2 0x9 - DATX8 n General Configuration Register 1 - (OFFSET, MASK, VALUE) (0XFD080B04, 0xFFFFFFFFU ,0x00007FFFU) - RegMask = (DDR_PHY_DX4GCR1_DXPDRMODE_MASK | DDR_PHY_DX4GCR1_RESERVED_15_MASK | DDR_PHY_DX4GCR1_QSNSEL_MASK | DDR_PHY_DX4GCR1_QSSEL_MASK | DDR_PHY_DX4GCR1_OEEN_MASK | DDR_PHY_DX4GCR1_PDREN_MASK | DDR_PHY_DX4GCR1_TEEN_MASK | DDR_PHY_DX4GCR1_DSEN_MASK | DDR_PHY_DX4GCR1_DMEN_MASK | DDR_PHY_DX4GCR1_DQEN_MASK | 0 ); + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX5GCR5_RESERVED_15 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX4GCR1_DXPDRMODE_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR1_RESERVED_15_SHIFT - | 0x00000001U << DDR_PHY_DX4GCR1_QSNSEL_SHIFT - | 0x00000001U << DDR_PHY_DX4GCR1_QSSEL_SHIFT - | 0x00000001U << DDR_PHY_DX4GCR1_OEEN_SHIFT - | 0x00000001U << DDR_PHY_DX4GCR1_PDREN_SHIFT - | 0x00000001U << DDR_PHY_DX4GCR1_TEEN_SHIFT - | 0x00000001U << DDR_PHY_DX4GCR1_DSEN_SHIFT - | 0x00000001U << DDR_PHY_DX4GCR1_DMEN_SHIFT - | 0x000000FFU << DDR_PHY_DX4GCR1_DQEN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX4GCR1_OFFSET ,0xFFFFFFFFU ,0x00007FFFU); - /*############################################################################################################################ */ + * Byte Lane internal VREF Select for Rank 1 + * PSU_DDR_PHY_DX5GCR5_DXREFISELR1 0x55 - /*Register : DX4GCR4 @ 0XFD080B10

+ * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX5GCR5_RESERVED_7 0x0 - Byte lane VREF IOM (Used only by D4MU IOs) - PSU_DDR_PHY_DX4GCR4_RESERVED_31_29 0x0 + * Byte Lane internal VREF Select for Rank 0 + * PSU_DDR_PHY_DX5GCR5_DXREFISELR0 0x55 - Byte Lane VREF Pad Enable - PSU_DDR_PHY_DX4GCR4_DXREFPEN 0x0 + * DATX8 n General Configuration Register 5 + * (OFFSET, MASK, VALUE) (0XFD080C14, 0xFFFFFFFFU ,0x09095555U) + */ + PSU_Mask_Write(DDR_PHY_DX5GCR5_OFFSET, 0xFFFFFFFFU, 0x09095555U); +/*##################################################################### */ - Byte Lane Internal VREF Enable - PSU_DDR_PHY_DX4GCR4_DXREFEEN 0x3 + /* + * Register : DX5GCR6 @ 0XFD080C18 - Byte Lane Single-End VREF Enable - PSU_DDR_PHY_DX4GCR4_DXREFSEN 0x1 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX5GCR6_RESERVED_31_30 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX4GCR4_RESERVED_24 0x0 + * DRAM DQ VREF Select for Rank3 + * PSU_DDR_PHY_DX5GCR6_DXDQVREFR3 0x9 - External VREF generator REFSEL range select - PSU_DDR_PHY_DX4GCR4_DXREFESELRANGE 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX5GCR6_RESERVED_23_22 0x0 - Byte Lane External VREF Select - PSU_DDR_PHY_DX4GCR4_DXREFESEL 0x0 + * DRAM DQ VREF Select for Rank2 + * PSU_DDR_PHY_DX5GCR6_DXDQVREFR2 0x9 - Single ended VREF generator REFSEL range select - PSU_DDR_PHY_DX4GCR4_DXREFSSELRANGE 0x1 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX5GCR6_RESERVED_15_14 0x0 - Byte Lane Single-End VREF Select - PSU_DDR_PHY_DX4GCR4_DXREFSSEL 0x30 + * DRAM DQ VREF Select for Rank1 + * PSU_DDR_PHY_DX5GCR6_DXDQVREFR1 0x2b - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX4GCR4_RESERVED_7_6 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX5GCR6_RESERVED_7_6 0x0 - VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. - PSU_DDR_PHY_DX4GCR4_DXREFIEN 0xf + * DRAM DQ VREF Select for Rank0 + * PSU_DDR_PHY_DX5GCR6_DXDQVREFR0 0x2b - VRMON control for DQ IO (Single Ended) buffers of a byte lane. - PSU_DDR_PHY_DX4GCR4_DXREFIMON 0x0 + * DATX8 n General Configuration Register 6 + * (OFFSET, MASK, VALUE) (0XFD080C18, 0xFFFFFFFFU ,0x09092B2BU) + */ + PSU_Mask_Write(DDR_PHY_DX5GCR6_OFFSET, 0xFFFFFFFFU, 0x09092B2BU); +/*##################################################################### */ - DATX8 n General Configuration Register 4 - (OFFSET, MASK, VALUE) (0XFD080B10, 0xFFFFFFFFU ,0x0E00B03CU) - RegMask = (DDR_PHY_DX4GCR4_RESERVED_31_29_MASK | DDR_PHY_DX4GCR4_DXREFPEN_MASK | DDR_PHY_DX4GCR4_DXREFEEN_MASK | DDR_PHY_DX4GCR4_DXREFSEN_MASK | DDR_PHY_DX4GCR4_RESERVED_24_MASK | DDR_PHY_DX4GCR4_DXREFESELRANGE_MASK | DDR_PHY_DX4GCR4_DXREFESEL_MASK | DDR_PHY_DX4GCR4_DXREFSSELRANGE_MASK | DDR_PHY_DX4GCR4_DXREFSSEL_MASK | DDR_PHY_DX4GCR4_RESERVED_7_6_MASK | DDR_PHY_DX4GCR4_DXREFIEN_MASK | DDR_PHY_DX4GCR4_DXREFIMON_MASK | 0 ); + /* + * Register : DX6GCR0 @ 0XFD080D00 - RegVal = ((0x00000000U << DDR_PHY_DX4GCR4_RESERVED_31_29_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR4_DXREFPEN_SHIFT - | 0x00000003U << DDR_PHY_DX4GCR4_DXREFEEN_SHIFT - | 0x00000001U << DDR_PHY_DX4GCR4_DXREFSEN_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR4_RESERVED_24_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR4_DXREFESELRANGE_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR4_DXREFESEL_SHIFT - | 0x00000001U << DDR_PHY_DX4GCR4_DXREFSSELRANGE_SHIFT - | 0x00000030U << DDR_PHY_DX4GCR4_DXREFSSEL_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR4_RESERVED_7_6_SHIFT - | 0x0000000FU << DDR_PHY_DX4GCR4_DXREFIEN_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR4_DXREFIMON_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX4GCR4_OFFSET ,0xFFFFFFFFU ,0x0E00B03CU); - /*############################################################################################################################ */ + * Calibration Bypass + * PSU_DDR_PHY_DX6GCR0_CALBYP 0x0 - /*Register : DX4GCR5 @ 0XFD080B14

+ * Master Delay Line Enable + * PSU_DDR_PHY_DX6GCR0_MDLEN 0x1 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX4GCR5_RESERVED_31 0x0 + * Configurable ODT(TE) Phase Shift + * PSU_DDR_PHY_DX6GCR0_CODTSHFT 0x0 - Byte Lane internal VREF Select for Rank 3 - PSU_DDR_PHY_DX4GCR5_DXREFISELR3 0x9 + * DQS Duty Cycle Correction + * PSU_DDR_PHY_DX6GCR0_DQSDCC 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX4GCR5_RESERVED_23 0x0 + * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY + * PSU_DDR_PHY_DX6GCR0_RDDLY 0x8 - Byte Lane internal VREF Select for Rank 2 - PSU_DDR_PHY_DX4GCR5_DXREFISELR2 0x9 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX6GCR0_RESERVED_19_14 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX4GCR5_RESERVED_15 0x0 + * DQSNSE Power Down Receiver + * PSU_DDR_PHY_DX6GCR0_DQSNSEPDR 0x0 - Byte Lane internal VREF Select for Rank 1 - PSU_DDR_PHY_DX4GCR5_DXREFISELR1 0x4f + * DQSSE Power Down Receiver + * PSU_DDR_PHY_DX6GCR0_DQSSEPDR 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX4GCR5_RESERVED_7 0x0 + * RTT On Additive Latency + * PSU_DDR_PHY_DX6GCR0_RTTOAL 0x0 - Byte Lane internal VREF Select for Rank 0 - PSU_DDR_PHY_DX4GCR5_DXREFISELR0 0x4f + * RTT Output Hold + * PSU_DDR_PHY_DX6GCR0_RTTOH 0x3 - DATX8 n General Configuration Register 5 - (OFFSET, MASK, VALUE) (0XFD080B14, 0xFFFFFFFFU ,0x09094F4FU) - RegMask = (DDR_PHY_DX4GCR5_RESERVED_31_MASK | DDR_PHY_DX4GCR5_DXREFISELR3_MASK | DDR_PHY_DX4GCR5_RESERVED_23_MASK | DDR_PHY_DX4GCR5_DXREFISELR2_MASK | DDR_PHY_DX4GCR5_RESERVED_15_MASK | DDR_PHY_DX4GCR5_DXREFISELR1_MASK | DDR_PHY_DX4GCR5_RESERVED_7_MASK | DDR_PHY_DX4GCR5_DXREFISELR0_MASK | 0 ); + * Configurable PDR Phase Shift + * PSU_DDR_PHY_DX6GCR0_CPDRSHFT 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX4GCR5_RESERVED_31_SHIFT - | 0x00000009U << DDR_PHY_DX4GCR5_DXREFISELR3_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR5_RESERVED_23_SHIFT - | 0x00000009U << DDR_PHY_DX4GCR5_DXREFISELR2_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR5_RESERVED_15_SHIFT - | 0x0000004FU << DDR_PHY_DX4GCR5_DXREFISELR1_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR5_RESERVED_7_SHIFT - | 0x0000004FU << DDR_PHY_DX4GCR5_DXREFISELR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX4GCR5_OFFSET ,0xFFFFFFFFU ,0x09094F4FU); - /*############################################################################################################################ */ + * DQSR Power Down + * PSU_DDR_PHY_DX6GCR0_DQSRPD 0x0 - /*Register : DX4GCR6 @ 0XFD080B18

+ * DQSG Power Down Receiver + * PSU_DDR_PHY_DX6GCR0_DQSGPDR 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX4GCR6_RESERVED_31_30 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX6GCR0_RESERVED_4 0x0 - DRAM DQ VREF Select for Rank3 - PSU_DDR_PHY_DX4GCR6_DXDQVREFR3 0x9 + * DQSG On-Die Termination + * PSU_DDR_PHY_DX6GCR0_DQSGODT 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX4GCR6_RESERVED_23_22 0x0 + * DQSG Output Enable + * PSU_DDR_PHY_DX6GCR0_DQSGOE 0x1 - DRAM DQ VREF Select for Rank2 - PSU_DDR_PHY_DX4GCR6_DXDQVREFR2 0x9 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX6GCR0_RESERVED_1_0 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX4GCR6_RESERVED_15_14 0x0 + * DATX8 n General Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD080D00, 0xFFFFFFFFU ,0x40800604U) + */ + PSU_Mask_Write(DDR_PHY_DX6GCR0_OFFSET, 0xFFFFFFFFU, 0x40800604U); +/*##################################################################### */ - DRAM DQ VREF Select for Rank1 - PSU_DDR_PHY_DX4GCR6_DXDQVREFR1 0x2b + /* + * Register : DX6GCR1 @ 0XFD080D04 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX4GCR6_RESERVED_7_6 0x0 + * Enables the PDR mode for DQ[7:0] + * PSU_DDR_PHY_DX6GCR1_DXPDRMODE 0x0 - DRAM DQ VREF Select for Rank0 - PSU_DDR_PHY_DX4GCR6_DXDQVREFR0 0x2b + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX6GCR1_RESERVED_15 0x0 - DATX8 n General Configuration Register 6 - (OFFSET, MASK, VALUE) (0XFD080B18, 0xFFFFFFFFU ,0x09092B2BU) - RegMask = (DDR_PHY_DX4GCR6_RESERVED_31_30_MASK | DDR_PHY_DX4GCR6_DXDQVREFR3_MASK | DDR_PHY_DX4GCR6_RESERVED_23_22_MASK | DDR_PHY_DX4GCR6_DXDQVREFR2_MASK | DDR_PHY_DX4GCR6_RESERVED_15_14_MASK | DDR_PHY_DX4GCR6_DXDQVREFR1_MASK | DDR_PHY_DX4GCR6_RESERVED_7_6_MASK | DDR_PHY_DX4GCR6_DXDQVREFR0_MASK | 0 ); + * Select the delayed or non-delayed read data strobe # + * PSU_DDR_PHY_DX6GCR1_QSNSEL 0x1 - RegVal = ((0x00000000U << DDR_PHY_DX4GCR6_RESERVED_31_30_SHIFT - | 0x00000009U << DDR_PHY_DX4GCR6_DXDQVREFR3_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR6_RESERVED_23_22_SHIFT - | 0x00000009U << DDR_PHY_DX4GCR6_DXDQVREFR2_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR6_RESERVED_15_14_SHIFT - | 0x0000002BU << DDR_PHY_DX4GCR6_DXDQVREFR1_SHIFT - | 0x00000000U << DDR_PHY_DX4GCR6_RESERVED_7_6_SHIFT - | 0x0000002BU << DDR_PHY_DX4GCR6_DXDQVREFR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX4GCR6_OFFSET ,0xFFFFFFFFU ,0x09092B2BU); - /*############################################################################################################################ */ + * Select the delayed or non-delayed read data strobe + * PSU_DDR_PHY_DX6GCR1_QSSEL 0x1 - /*Register : DX4LCDLR2 @ 0XFD080B88

+ * Enables Read Data Strobe in a byte lane + * PSU_DDR_PHY_DX6GCR1_OEEN 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX4LCDLR2_RESERVED_31_25 0x0 + * Enables PDR in a byte lane + * PSU_DDR_PHY_DX6GCR1_PDREN 0x1 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX4LCDLR2_RESERVED_24_16 0x0 + * Enables ODT/TE in a byte lane + * PSU_DDR_PHY_DX6GCR1_TEEN 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX4LCDLR2_RESERVED_15_9 0x0 + * Enables Write Data strobe in a byte lane + * PSU_DDR_PHY_DX6GCR1_DSEN 0x1 - Read DQS Gating Delay - PSU_DDR_PHY_DX4LCDLR2_DQSGD 0x0 + * Enables DM pin in a byte lane + * PSU_DDR_PHY_DX6GCR1_DMEN 0x1 - DATX8 n Local Calibrated Delay Line Register 2 - (OFFSET, MASK, VALUE) (0XFD080B88, 0xFFFFFFFFU ,0x00000000U) - RegMask = (DDR_PHY_DX4LCDLR2_RESERVED_31_25_MASK | DDR_PHY_DX4LCDLR2_RESERVED_24_16_MASK | DDR_PHY_DX4LCDLR2_RESERVED_15_9_MASK | DDR_PHY_DX4LCDLR2_DQSGD_MASK | 0 ); + * Enables DQ corresponding to each bit in a byte + * PSU_DDR_PHY_DX6GCR1_DQEN 0xff - RegVal = ((0x00000000U << DDR_PHY_DX4LCDLR2_RESERVED_31_25_SHIFT - | 0x00000000U << DDR_PHY_DX4LCDLR2_RESERVED_24_16_SHIFT - | 0x00000000U << DDR_PHY_DX4LCDLR2_RESERVED_15_9_SHIFT - | 0x00000000U << DDR_PHY_DX4LCDLR2_DQSGD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX4LCDLR2_OFFSET ,0xFFFFFFFFU ,0x00000000U); - /*############################################################################################################################ */ + * DATX8 n General Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD080D04, 0xFFFFFFFFU ,0x00007FFFU) + */ + PSU_Mask_Write(DDR_PHY_DX6GCR1_OFFSET, 0xFFFFFFFFU, 0x00007FFFU); +/*##################################################################### */ - /*Register : DX4GTR0 @ 0XFD080BC0

+ /* + * Register : DX6GCR4 @ 0XFD080D10 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX4GTR0_RESERVED_31_24 0x0 + * Byte lane VREF IOM (Used only by D4MU IOs) + * PSU_DDR_PHY_DX6GCR4_RESERVED_31_29 0x0 - DQ Write Path Latency Pipeline - PSU_DDR_PHY_DX4GTR0_WDQSL 0x0 + * Byte Lane VREF Pad Enable + * PSU_DDR_PHY_DX6GCR4_DXREFPEN 0x0 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX4GTR0_RESERVED_23_20 0x0 + * Byte Lane Internal VREF Enable + * PSU_DDR_PHY_DX6GCR4_DXREFEEN 0x3 - Write Leveling System Latency - PSU_DDR_PHY_DX4GTR0_WLSL 0x2 + * Byte Lane Single-End VREF Enable + * PSU_DDR_PHY_DX6GCR4_DXREFSEN 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX4GTR0_RESERVED_15_13 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX6GCR4_RESERVED_24 0x0 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX4GTR0_RESERVED_12_8 0x0 + * External VREF generator REFSEL range select + * PSU_DDR_PHY_DX6GCR4_DXREFESELRANGE 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX4GTR0_RESERVED_7_5 0x0 + * Byte Lane External VREF Select + * PSU_DDR_PHY_DX6GCR4_DXREFESEL 0x0 - DQS Gating System Latency - PSU_DDR_PHY_DX4GTR0_DGSL 0x0 + * Single ended VREF generator REFSEL range select + * PSU_DDR_PHY_DX6GCR4_DXREFSSELRANGE 0x1 - DATX8 n General Timing Register 0 - (OFFSET, MASK, VALUE) (0XFD080BC0, 0xFFFFFFFFU ,0x00020000U) - RegMask = (DDR_PHY_DX4GTR0_RESERVED_31_24_MASK | DDR_PHY_DX4GTR0_WDQSL_MASK | DDR_PHY_DX4GTR0_RESERVED_23_20_MASK | DDR_PHY_DX4GTR0_WLSL_MASK | DDR_PHY_DX4GTR0_RESERVED_15_13_MASK | DDR_PHY_DX4GTR0_RESERVED_12_8_MASK | DDR_PHY_DX4GTR0_RESERVED_7_5_MASK | DDR_PHY_DX4GTR0_DGSL_MASK | 0 ); + * Byte Lane Single-End VREF Select + * PSU_DDR_PHY_DX6GCR4_DXREFSSEL 0x30 - RegVal = ((0x00000000U << DDR_PHY_DX4GTR0_RESERVED_31_24_SHIFT - | 0x00000000U << DDR_PHY_DX4GTR0_WDQSL_SHIFT - | 0x00000000U << DDR_PHY_DX4GTR0_RESERVED_23_20_SHIFT - | 0x00000002U << DDR_PHY_DX4GTR0_WLSL_SHIFT - | 0x00000000U << DDR_PHY_DX4GTR0_RESERVED_15_13_SHIFT - | 0x00000000U << DDR_PHY_DX4GTR0_RESERVED_12_8_SHIFT - | 0x00000000U << DDR_PHY_DX4GTR0_RESERVED_7_5_SHIFT - | 0x00000000U << DDR_PHY_DX4GTR0_DGSL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX4GTR0_OFFSET ,0xFFFFFFFFU ,0x00020000U); - /*############################################################################################################################ */ + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX6GCR4_RESERVED_7_6 0x0 - /*Register : DX5GCR0 @ 0XFD080C00

+ * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX6GCR4_DXREFIEN 0xf - Calibration Bypass - PSU_DDR_PHY_DX5GCR0_CALBYP 0x0 + * VRMON control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX6GCR4_DXREFIMON 0x0 - Master Delay Line Enable - PSU_DDR_PHY_DX5GCR0_MDLEN 0x1 + * DATX8 n General Configuration Register 4 + * (OFFSET, MASK, VALUE) (0XFD080D10, 0xFFFFFFFFU ,0x0E00B03CU) + */ + PSU_Mask_Write(DDR_PHY_DX6GCR4_OFFSET, 0xFFFFFFFFU, 0x0E00B03CU); +/*##################################################################### */ - Configurable ODT(TE) Phase Shift - PSU_DDR_PHY_DX5GCR0_CODTSHFT 0x0 + /* + * Register : DX6GCR5 @ 0XFD080D14 - DQS Duty Cycle Correction - PSU_DDR_PHY_DX5GCR0_DQSDCC 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX6GCR5_RESERVED_31 0x0 - Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY - PSU_DDR_PHY_DX5GCR0_RDDLY 0x8 + * Byte Lane internal VREF Select for Rank 3 + * PSU_DDR_PHY_DX6GCR5_DXREFISELR3 0x9 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX5GCR0_RESERVED_19_14 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX6GCR5_RESERVED_23 0x0 - DQSNSE Power Down Receiver - PSU_DDR_PHY_DX5GCR0_DQSNSEPDR 0x0 + * Byte Lane internal VREF Select for Rank 2 + * PSU_DDR_PHY_DX6GCR5_DXREFISELR2 0x9 - DQSSE Power Down Receiver - PSU_DDR_PHY_DX5GCR0_DQSSEPDR 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX6GCR5_RESERVED_15 0x0 - RTT On Additive Latency - PSU_DDR_PHY_DX5GCR0_RTTOAL 0x0 + * Byte Lane internal VREF Select for Rank 1 + * PSU_DDR_PHY_DX6GCR5_DXREFISELR1 0x55 - RTT Output Hold - PSU_DDR_PHY_DX5GCR0_RTTOH 0x3 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX6GCR5_RESERVED_7 0x0 - Configurable PDR Phase Shift - PSU_DDR_PHY_DX5GCR0_CPDRSHFT 0x0 + * Byte Lane internal VREF Select for Rank 0 + * PSU_DDR_PHY_DX6GCR5_DXREFISELR0 0x55 - DQSR Power Down - PSU_DDR_PHY_DX5GCR0_DQSRPD 0x0 + * DATX8 n General Configuration Register 5 + * (OFFSET, MASK, VALUE) (0XFD080D14, 0xFFFFFFFFU ,0x09095555U) + */ + PSU_Mask_Write(DDR_PHY_DX6GCR5_OFFSET, 0xFFFFFFFFU, 0x09095555U); +/*##################################################################### */ - DQSG Power Down Receiver - PSU_DDR_PHY_DX5GCR0_DQSGPDR 0x0 + /* + * Register : DX6GCR6 @ 0XFD080D18 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX5GCR0_RESERVED_4 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX6GCR6_RESERVED_31_30 0x0 - DQSG On-Die Termination - PSU_DDR_PHY_DX5GCR0_DQSGODT 0x0 + * DRAM DQ VREF Select for Rank3 + * PSU_DDR_PHY_DX6GCR6_DXDQVREFR3 0x9 - DQSG Output Enable - PSU_DDR_PHY_DX5GCR0_DQSGOE 0x1 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX6GCR6_RESERVED_23_22 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX5GCR0_RESERVED_1_0 0x0 + * DRAM DQ VREF Select for Rank2 + * PSU_DDR_PHY_DX6GCR6_DXDQVREFR2 0x9 - DATX8 n General Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD080C00, 0xFFFFFFFFU ,0x40800604U) - RegMask = (DDR_PHY_DX5GCR0_CALBYP_MASK | DDR_PHY_DX5GCR0_MDLEN_MASK | DDR_PHY_DX5GCR0_CODTSHFT_MASK | DDR_PHY_DX5GCR0_DQSDCC_MASK | DDR_PHY_DX5GCR0_RDDLY_MASK | DDR_PHY_DX5GCR0_RESERVED_19_14_MASK | DDR_PHY_DX5GCR0_DQSNSEPDR_MASK | DDR_PHY_DX5GCR0_DQSSEPDR_MASK | DDR_PHY_DX5GCR0_RTTOAL_MASK | DDR_PHY_DX5GCR0_RTTOH_MASK | DDR_PHY_DX5GCR0_CPDRSHFT_MASK | DDR_PHY_DX5GCR0_DQSRPD_MASK | DDR_PHY_DX5GCR0_DQSGPDR_MASK | DDR_PHY_DX5GCR0_RESERVED_4_MASK | DDR_PHY_DX5GCR0_DQSGODT_MASK | DDR_PHY_DX5GCR0_DQSGOE_MASK | DDR_PHY_DX5GCR0_RESERVED_1_0_MASK | 0 ); + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX6GCR6_RESERVED_15_14 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX5GCR0_CALBYP_SHIFT - | 0x00000001U << DDR_PHY_DX5GCR0_MDLEN_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR0_CODTSHFT_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR0_DQSDCC_SHIFT - | 0x00000008U << DDR_PHY_DX5GCR0_RDDLY_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR0_RESERVED_19_14_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR0_DQSNSEPDR_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR0_DQSSEPDR_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR0_RTTOAL_SHIFT - | 0x00000003U << DDR_PHY_DX5GCR0_RTTOH_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR0_CPDRSHFT_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR0_DQSRPD_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR0_DQSGPDR_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR0_RESERVED_4_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR0_DQSGODT_SHIFT - | 0x00000001U << DDR_PHY_DX5GCR0_DQSGOE_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR0_RESERVED_1_0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX5GCR0_OFFSET ,0xFFFFFFFFU ,0x40800604U); - /*############################################################################################################################ */ + * DRAM DQ VREF Select for Rank1 + * PSU_DDR_PHY_DX6GCR6_DXDQVREFR1 0x2b - /*Register : DX5GCR1 @ 0XFD080C04

+ * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX6GCR6_RESERVED_7_6 0x0 - Enables the PDR mode for DQ[7:0] - PSU_DDR_PHY_DX5GCR1_DXPDRMODE 0x0 + * DRAM DQ VREF Select for Rank0 + * PSU_DDR_PHY_DX6GCR6_DXDQVREFR0 0x2b - Reserved. Returns zeroes on reads. - PSU_DDR_PHY_DX5GCR1_RESERVED_15 0x0 + * DATX8 n General Configuration Register 6 + * (OFFSET, MASK, VALUE) (0XFD080D18, 0xFFFFFFFFU ,0x09092B2BU) + */ + PSU_Mask_Write(DDR_PHY_DX6GCR6_OFFSET, 0xFFFFFFFFU, 0x09092B2BU); +/*##################################################################### */ - Select the delayed or non-delayed read data strobe # - PSU_DDR_PHY_DX5GCR1_QSNSEL 0x1 + /* + * Register : DX7GCR0 @ 0XFD080E00 - Select the delayed or non-delayed read data strobe - PSU_DDR_PHY_DX5GCR1_QSSEL 0x1 + * Calibration Bypass + * PSU_DDR_PHY_DX7GCR0_CALBYP 0x0 - Enables Read Data Strobe in a byte lane - PSU_DDR_PHY_DX5GCR1_OEEN 0x1 + * Master Delay Line Enable + * PSU_DDR_PHY_DX7GCR0_MDLEN 0x1 - Enables PDR in a byte lane - PSU_DDR_PHY_DX5GCR1_PDREN 0x1 + * Configurable ODT(TE) Phase Shift + * PSU_DDR_PHY_DX7GCR0_CODTSHFT 0x0 - Enables ODT/TE in a byte lane - PSU_DDR_PHY_DX5GCR1_TEEN 0x1 + * DQS Duty Cycle Correction + * PSU_DDR_PHY_DX7GCR0_DQSDCC 0x0 - Enables Write Data strobe in a byte lane - PSU_DDR_PHY_DX5GCR1_DSEN 0x1 + * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY + * PSU_DDR_PHY_DX7GCR0_RDDLY 0x8 - Enables DM pin in a byte lane - PSU_DDR_PHY_DX5GCR1_DMEN 0x1 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX7GCR0_RESERVED_19_14 0x0 - Enables DQ corresponding to each bit in a byte - PSU_DDR_PHY_DX5GCR1_DQEN 0xff + * DQSNSE Power Down Receiver + * PSU_DDR_PHY_DX7GCR0_DQSNSEPDR 0x0 - DATX8 n General Configuration Register 1 - (OFFSET, MASK, VALUE) (0XFD080C04, 0xFFFFFFFFU ,0x00007FFFU) - RegMask = (DDR_PHY_DX5GCR1_DXPDRMODE_MASK | DDR_PHY_DX5GCR1_RESERVED_15_MASK | DDR_PHY_DX5GCR1_QSNSEL_MASK | DDR_PHY_DX5GCR1_QSSEL_MASK | DDR_PHY_DX5GCR1_OEEN_MASK | DDR_PHY_DX5GCR1_PDREN_MASK | DDR_PHY_DX5GCR1_TEEN_MASK | DDR_PHY_DX5GCR1_DSEN_MASK | DDR_PHY_DX5GCR1_DMEN_MASK | DDR_PHY_DX5GCR1_DQEN_MASK | 0 ); + * DQSSE Power Down Receiver + * PSU_DDR_PHY_DX7GCR0_DQSSEPDR 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX5GCR1_DXPDRMODE_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR1_RESERVED_15_SHIFT - | 0x00000001U << DDR_PHY_DX5GCR1_QSNSEL_SHIFT - | 0x00000001U << DDR_PHY_DX5GCR1_QSSEL_SHIFT - | 0x00000001U << DDR_PHY_DX5GCR1_OEEN_SHIFT - | 0x00000001U << DDR_PHY_DX5GCR1_PDREN_SHIFT - | 0x00000001U << DDR_PHY_DX5GCR1_TEEN_SHIFT - | 0x00000001U << DDR_PHY_DX5GCR1_DSEN_SHIFT - | 0x00000001U << DDR_PHY_DX5GCR1_DMEN_SHIFT - | 0x000000FFU << DDR_PHY_DX5GCR1_DQEN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX5GCR1_OFFSET ,0xFFFFFFFFU ,0x00007FFFU); - /*############################################################################################################################ */ + * RTT On Additive Latency + * PSU_DDR_PHY_DX7GCR0_RTTOAL 0x0 - /*Register : DX5GCR4 @ 0XFD080C10

+ * RTT Output Hold + * PSU_DDR_PHY_DX7GCR0_RTTOH 0x3 - Byte lane VREF IOM (Used only by D4MU IOs) - PSU_DDR_PHY_DX5GCR4_RESERVED_31_29 0x0 + * Configurable PDR Phase Shift + * PSU_DDR_PHY_DX7GCR0_CPDRSHFT 0x0 - Byte Lane VREF Pad Enable - PSU_DDR_PHY_DX5GCR4_DXREFPEN 0x0 + * DQSR Power Down + * PSU_DDR_PHY_DX7GCR0_DQSRPD 0x0 - Byte Lane Internal VREF Enable - PSU_DDR_PHY_DX5GCR4_DXREFEEN 0x3 + * DQSG Power Down Receiver + * PSU_DDR_PHY_DX7GCR0_DQSGPDR 0x0 - Byte Lane Single-End VREF Enable - PSU_DDR_PHY_DX5GCR4_DXREFSEN 0x1 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX7GCR0_RESERVED_4 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX5GCR4_RESERVED_24 0x0 + * DQSG On-Die Termination + * PSU_DDR_PHY_DX7GCR0_DQSGODT 0x0 - External VREF generator REFSEL range select - PSU_DDR_PHY_DX5GCR4_DXREFESELRANGE 0x0 + * DQSG Output Enable + * PSU_DDR_PHY_DX7GCR0_DQSGOE 0x1 - Byte Lane External VREF Select - PSU_DDR_PHY_DX5GCR4_DXREFESEL 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX7GCR0_RESERVED_1_0 0x0 - Single ended VREF generator REFSEL range select - PSU_DDR_PHY_DX5GCR4_DXREFSSELRANGE 0x1 + * DATX8 n General Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD080E00, 0xFFFFFFFFU ,0x40800604U) + */ + PSU_Mask_Write(DDR_PHY_DX7GCR0_OFFSET, 0xFFFFFFFFU, 0x40800604U); +/*##################################################################### */ - Byte Lane Single-End VREF Select - PSU_DDR_PHY_DX5GCR4_DXREFSSEL 0x30 + /* + * Register : DX7GCR1 @ 0XFD080E04 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX5GCR4_RESERVED_7_6 0x0 + * Enables the PDR mode for DQ[7:0] + * PSU_DDR_PHY_DX7GCR1_DXPDRMODE 0x0 - VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. - PSU_DDR_PHY_DX5GCR4_DXREFIEN 0xf + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX7GCR1_RESERVED_15 0x0 - VRMON control for DQ IO (Single Ended) buffers of a byte lane. - PSU_DDR_PHY_DX5GCR4_DXREFIMON 0x0 + * Select the delayed or non-delayed read data strobe # + * PSU_DDR_PHY_DX7GCR1_QSNSEL 0x1 - DATX8 n General Configuration Register 4 - (OFFSET, MASK, VALUE) (0XFD080C10, 0xFFFFFFFFU ,0x0E00B03CU) - RegMask = (DDR_PHY_DX5GCR4_RESERVED_31_29_MASK | DDR_PHY_DX5GCR4_DXREFPEN_MASK | DDR_PHY_DX5GCR4_DXREFEEN_MASK | DDR_PHY_DX5GCR4_DXREFSEN_MASK | DDR_PHY_DX5GCR4_RESERVED_24_MASK | DDR_PHY_DX5GCR4_DXREFESELRANGE_MASK | DDR_PHY_DX5GCR4_DXREFESEL_MASK | DDR_PHY_DX5GCR4_DXREFSSELRANGE_MASK | DDR_PHY_DX5GCR4_DXREFSSEL_MASK | DDR_PHY_DX5GCR4_RESERVED_7_6_MASK | DDR_PHY_DX5GCR4_DXREFIEN_MASK | DDR_PHY_DX5GCR4_DXREFIMON_MASK | 0 ); + * Select the delayed or non-delayed read data strobe + * PSU_DDR_PHY_DX7GCR1_QSSEL 0x1 - RegVal = ((0x00000000U << DDR_PHY_DX5GCR4_RESERVED_31_29_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR4_DXREFPEN_SHIFT - | 0x00000003U << DDR_PHY_DX5GCR4_DXREFEEN_SHIFT - | 0x00000001U << DDR_PHY_DX5GCR4_DXREFSEN_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR4_RESERVED_24_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR4_DXREFESELRANGE_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR4_DXREFESEL_SHIFT - | 0x00000001U << DDR_PHY_DX5GCR4_DXREFSSELRANGE_SHIFT - | 0x00000030U << DDR_PHY_DX5GCR4_DXREFSSEL_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR4_RESERVED_7_6_SHIFT - | 0x0000000FU << DDR_PHY_DX5GCR4_DXREFIEN_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR4_DXREFIMON_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX5GCR4_OFFSET ,0xFFFFFFFFU ,0x0E00B03CU); - /*############################################################################################################################ */ + * Enables Read Data Strobe in a byte lane + * PSU_DDR_PHY_DX7GCR1_OEEN 0x1 - /*Register : DX5GCR5 @ 0XFD080C14

+ * Enables PDR in a byte lane + * PSU_DDR_PHY_DX7GCR1_PDREN 0x1 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX5GCR5_RESERVED_31 0x0 + * Enables ODT/TE in a byte lane + * PSU_DDR_PHY_DX7GCR1_TEEN 0x1 - Byte Lane internal VREF Select for Rank 3 - PSU_DDR_PHY_DX5GCR5_DXREFISELR3 0x9 + * Enables Write Data strobe in a byte lane + * PSU_DDR_PHY_DX7GCR1_DSEN 0x1 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX5GCR5_RESERVED_23 0x0 + * Enables DM pin in a byte lane + * PSU_DDR_PHY_DX7GCR1_DMEN 0x1 - Byte Lane internal VREF Select for Rank 2 - PSU_DDR_PHY_DX5GCR5_DXREFISELR2 0x9 + * Enables DQ corresponding to each bit in a byte + * PSU_DDR_PHY_DX7GCR1_DQEN 0xff - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX5GCR5_RESERVED_15 0x0 + * DATX8 n General Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD080E04, 0xFFFFFFFFU ,0x00007FFFU) + */ + PSU_Mask_Write(DDR_PHY_DX7GCR1_OFFSET, 0xFFFFFFFFU, 0x00007FFFU); +/*##################################################################### */ - Byte Lane internal VREF Select for Rank 1 - PSU_DDR_PHY_DX5GCR5_DXREFISELR1 0x4f + /* + * Register : DX7GCR4 @ 0XFD080E10 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX5GCR5_RESERVED_7 0x0 + * Byte lane VREF IOM (Used only by D4MU IOs) + * PSU_DDR_PHY_DX7GCR4_RESERVED_31_29 0x0 - Byte Lane internal VREF Select for Rank 0 - PSU_DDR_PHY_DX5GCR5_DXREFISELR0 0x4f + * Byte Lane VREF Pad Enable + * PSU_DDR_PHY_DX7GCR4_DXREFPEN 0x0 - DATX8 n General Configuration Register 5 - (OFFSET, MASK, VALUE) (0XFD080C14, 0xFFFFFFFFU ,0x09094F4FU) - RegMask = (DDR_PHY_DX5GCR5_RESERVED_31_MASK | DDR_PHY_DX5GCR5_DXREFISELR3_MASK | DDR_PHY_DX5GCR5_RESERVED_23_MASK | DDR_PHY_DX5GCR5_DXREFISELR2_MASK | DDR_PHY_DX5GCR5_RESERVED_15_MASK | DDR_PHY_DX5GCR5_DXREFISELR1_MASK | DDR_PHY_DX5GCR5_RESERVED_7_MASK | DDR_PHY_DX5GCR5_DXREFISELR0_MASK | 0 ); + * Byte Lane Internal VREF Enable + * PSU_DDR_PHY_DX7GCR4_DXREFEEN 0x3 - RegVal = ((0x00000000U << DDR_PHY_DX5GCR5_RESERVED_31_SHIFT - | 0x00000009U << DDR_PHY_DX5GCR5_DXREFISELR3_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR5_RESERVED_23_SHIFT - | 0x00000009U << DDR_PHY_DX5GCR5_DXREFISELR2_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR5_RESERVED_15_SHIFT - | 0x0000004FU << DDR_PHY_DX5GCR5_DXREFISELR1_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR5_RESERVED_7_SHIFT - | 0x0000004FU << DDR_PHY_DX5GCR5_DXREFISELR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX5GCR5_OFFSET ,0xFFFFFFFFU ,0x09094F4FU); - /*############################################################################################################################ */ + * Byte Lane Single-End VREF Enable + * PSU_DDR_PHY_DX7GCR4_DXREFSEN 0x1 - /*Register : DX5GCR6 @ 0XFD080C18

+ * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX7GCR4_RESERVED_24 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX5GCR6_RESERVED_31_30 0x0 + * External VREF generator REFSEL range select + * PSU_DDR_PHY_DX7GCR4_DXREFESELRANGE 0x0 - DRAM DQ VREF Select for Rank3 - PSU_DDR_PHY_DX5GCR6_DXDQVREFR3 0x9 + * Byte Lane External VREF Select + * PSU_DDR_PHY_DX7GCR4_DXREFESEL 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX5GCR6_RESERVED_23_22 0x0 + * Single ended VREF generator REFSEL range select + * PSU_DDR_PHY_DX7GCR4_DXREFSSELRANGE 0x1 - DRAM DQ VREF Select for Rank2 - PSU_DDR_PHY_DX5GCR6_DXDQVREFR2 0x9 + * Byte Lane Single-End VREF Select + * PSU_DDR_PHY_DX7GCR4_DXREFSSEL 0x30 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX5GCR6_RESERVED_15_14 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX7GCR4_RESERVED_7_6 0x0 - DRAM DQ VREF Select for Rank1 - PSU_DDR_PHY_DX5GCR6_DXDQVREFR1 0x2b + * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX7GCR4_DXREFIEN 0xf - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX5GCR6_RESERVED_7_6 0x0 + * VRMON control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX7GCR4_DXREFIMON 0x0 - DRAM DQ VREF Select for Rank0 - PSU_DDR_PHY_DX5GCR6_DXDQVREFR0 0x2b + * DATX8 n General Configuration Register 4 + * (OFFSET, MASK, VALUE) (0XFD080E10, 0xFFFFFFFFU ,0x0E00B03CU) + */ + PSU_Mask_Write(DDR_PHY_DX7GCR4_OFFSET, 0xFFFFFFFFU, 0x0E00B03CU); +/*##################################################################### */ - DATX8 n General Configuration Register 6 - (OFFSET, MASK, VALUE) (0XFD080C18, 0xFFFFFFFFU ,0x09092B2BU) - RegMask = (DDR_PHY_DX5GCR6_RESERVED_31_30_MASK | DDR_PHY_DX5GCR6_DXDQVREFR3_MASK | DDR_PHY_DX5GCR6_RESERVED_23_22_MASK | DDR_PHY_DX5GCR6_DXDQVREFR2_MASK | DDR_PHY_DX5GCR6_RESERVED_15_14_MASK | DDR_PHY_DX5GCR6_DXDQVREFR1_MASK | DDR_PHY_DX5GCR6_RESERVED_7_6_MASK | DDR_PHY_DX5GCR6_DXDQVREFR0_MASK | 0 ); + /* + * Register : DX7GCR5 @ 0XFD080E14 - RegVal = ((0x00000000U << DDR_PHY_DX5GCR6_RESERVED_31_30_SHIFT - | 0x00000009U << DDR_PHY_DX5GCR6_DXDQVREFR3_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR6_RESERVED_23_22_SHIFT - | 0x00000009U << DDR_PHY_DX5GCR6_DXDQVREFR2_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR6_RESERVED_15_14_SHIFT - | 0x0000002BU << DDR_PHY_DX5GCR6_DXDQVREFR1_SHIFT - | 0x00000000U << DDR_PHY_DX5GCR6_RESERVED_7_6_SHIFT - | 0x0000002BU << DDR_PHY_DX5GCR6_DXDQVREFR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX5GCR6_OFFSET ,0xFFFFFFFFU ,0x09092B2BU); - /*############################################################################################################################ */ + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX7GCR5_RESERVED_31 0x0 - /*Register : DX5LCDLR2 @ 0XFD080C88

+ * Byte Lane internal VREF Select for Rank 3 + * PSU_DDR_PHY_DX7GCR5_DXREFISELR3 0x9 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX5LCDLR2_RESERVED_31_25 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX7GCR5_RESERVED_23 0x0 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX5LCDLR2_RESERVED_24_16 0x0 + * Byte Lane internal VREF Select for Rank 2 + * PSU_DDR_PHY_DX7GCR5_DXREFISELR2 0x9 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX5LCDLR2_RESERVED_15_9 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX7GCR5_RESERVED_15 0x0 - Read DQS Gating Delay - PSU_DDR_PHY_DX5LCDLR2_DQSGD 0x0 + * Byte Lane internal VREF Select for Rank 1 + * PSU_DDR_PHY_DX7GCR5_DXREFISELR1 0x55 - DATX8 n Local Calibrated Delay Line Register 2 - (OFFSET, MASK, VALUE) (0XFD080C88, 0xFFFFFFFFU ,0x00000000U) - RegMask = (DDR_PHY_DX5LCDLR2_RESERVED_31_25_MASK | DDR_PHY_DX5LCDLR2_RESERVED_24_16_MASK | DDR_PHY_DX5LCDLR2_RESERVED_15_9_MASK | DDR_PHY_DX5LCDLR2_DQSGD_MASK | 0 ); + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX7GCR5_RESERVED_7 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX5LCDLR2_RESERVED_31_25_SHIFT - | 0x00000000U << DDR_PHY_DX5LCDLR2_RESERVED_24_16_SHIFT - | 0x00000000U << DDR_PHY_DX5LCDLR2_RESERVED_15_9_SHIFT - | 0x00000000U << DDR_PHY_DX5LCDLR2_DQSGD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX5LCDLR2_OFFSET ,0xFFFFFFFFU ,0x00000000U); - /*############################################################################################################################ */ + * Byte Lane internal VREF Select for Rank 0 + * PSU_DDR_PHY_DX7GCR5_DXREFISELR0 0x55 - /*Register : DX5GTR0 @ 0XFD080CC0

+ * DATX8 n General Configuration Register 5 + * (OFFSET, MASK, VALUE) (0XFD080E14, 0xFFFFFFFFU ,0x09095555U) + */ + PSU_Mask_Write(DDR_PHY_DX7GCR5_OFFSET, 0xFFFFFFFFU, 0x09095555U); +/*##################################################################### */ - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX5GTR0_RESERVED_31_24 0x0 + /* + * Register : DX7GCR6 @ 0XFD080E18 - DQ Write Path Latency Pipeline - PSU_DDR_PHY_DX5GTR0_WDQSL 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX7GCR6_RESERVED_31_30 0x0 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX5GTR0_RESERVED_23_20 0x0 + * DRAM DQ VREF Select for Rank3 + * PSU_DDR_PHY_DX7GCR6_DXDQVREFR3 0x9 - Write Leveling System Latency - PSU_DDR_PHY_DX5GTR0_WLSL 0x2 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX7GCR6_RESERVED_23_22 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX5GTR0_RESERVED_15_13 0x0 + * DRAM DQ VREF Select for Rank2 + * PSU_DDR_PHY_DX7GCR6_DXDQVREFR2 0x9 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX5GTR0_RESERVED_12_8 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX7GCR6_RESERVED_15_14 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX5GTR0_RESERVED_7_5 0x0 + * DRAM DQ VREF Select for Rank1 + * PSU_DDR_PHY_DX7GCR6_DXDQVREFR1 0x2b - DQS Gating System Latency - PSU_DDR_PHY_DX5GTR0_DGSL 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX7GCR6_RESERVED_7_6 0x0 - DATX8 n General Timing Register 0 - (OFFSET, MASK, VALUE) (0XFD080CC0, 0xFFFFFFFFU ,0x00020000U) - RegMask = (DDR_PHY_DX5GTR0_RESERVED_31_24_MASK | DDR_PHY_DX5GTR0_WDQSL_MASK | DDR_PHY_DX5GTR0_RESERVED_23_20_MASK | DDR_PHY_DX5GTR0_WLSL_MASK | DDR_PHY_DX5GTR0_RESERVED_15_13_MASK | DDR_PHY_DX5GTR0_RESERVED_12_8_MASK | DDR_PHY_DX5GTR0_RESERVED_7_5_MASK | DDR_PHY_DX5GTR0_DGSL_MASK | 0 ); + * DRAM DQ VREF Select for Rank0 + * PSU_DDR_PHY_DX7GCR6_DXDQVREFR0 0x2b - RegVal = ((0x00000000U << DDR_PHY_DX5GTR0_RESERVED_31_24_SHIFT - | 0x00000000U << DDR_PHY_DX5GTR0_WDQSL_SHIFT - | 0x00000000U << DDR_PHY_DX5GTR0_RESERVED_23_20_SHIFT - | 0x00000002U << DDR_PHY_DX5GTR0_WLSL_SHIFT - | 0x00000000U << DDR_PHY_DX5GTR0_RESERVED_15_13_SHIFT - | 0x00000000U << DDR_PHY_DX5GTR0_RESERVED_12_8_SHIFT - | 0x00000000U << DDR_PHY_DX5GTR0_RESERVED_7_5_SHIFT - | 0x00000000U << DDR_PHY_DX5GTR0_DGSL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX5GTR0_OFFSET ,0xFFFFFFFFU ,0x00020000U); - /*############################################################################################################################ */ + * DATX8 n General Configuration Register 6 + * (OFFSET, MASK, VALUE) (0XFD080E18, 0xFFFFFFFFU ,0x09092B2BU) + */ + PSU_Mask_Write(DDR_PHY_DX7GCR6_OFFSET, 0xFFFFFFFFU, 0x09092B2BU); +/*##################################################################### */ - /*Register : DX6GCR0 @ 0XFD080D00

+ /* + * Register : DX8GCR0 @ 0XFD080F00 - Calibration Bypass - PSU_DDR_PHY_DX6GCR0_CALBYP 0x0 + * Calibration Bypass + * PSU_DDR_PHY_DX8GCR0_CALBYP 0x0 - Master Delay Line Enable - PSU_DDR_PHY_DX6GCR0_MDLEN 0x1 + * Master Delay Line Enable + * PSU_DDR_PHY_DX8GCR0_MDLEN 0x1 - Configurable ODT(TE) Phase Shift - PSU_DDR_PHY_DX6GCR0_CODTSHFT 0x0 + * Configurable ODT(TE) Phase Shift + * PSU_DDR_PHY_DX8GCR0_CODTSHFT 0x0 - DQS Duty Cycle Correction - PSU_DDR_PHY_DX6GCR0_DQSDCC 0x0 + * DQS Duty Cycle Correction + * PSU_DDR_PHY_DX8GCR0_DQSDCC 0x0 - Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY - PSU_DDR_PHY_DX6GCR0_RDDLY 0x8 + * Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY + * PSU_DDR_PHY_DX8GCR0_RDDLY 0x8 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX6GCR0_RESERVED_19_14 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8GCR0_RESERVED_19_14 0x0 - DQSNSE Power Down Receiver - PSU_DDR_PHY_DX6GCR0_DQSNSEPDR 0x0 + * DQSNSE Power Down Receiver + * PSU_DDR_PHY_DX8GCR0_DQSNSEPDR 0x0 - DQSSE Power Down Receiver - PSU_DDR_PHY_DX6GCR0_DQSSEPDR 0x0 + * DQSSE Power Down Receiver + * PSU_DDR_PHY_DX8GCR0_DQSSEPDR 0x0 - RTT On Additive Latency - PSU_DDR_PHY_DX6GCR0_RTTOAL 0x0 + * RTT On Additive Latency + * PSU_DDR_PHY_DX8GCR0_RTTOAL 0x0 - RTT Output Hold - PSU_DDR_PHY_DX6GCR0_RTTOH 0x3 + * RTT Output Hold + * PSU_DDR_PHY_DX8GCR0_RTTOH 0x3 - Configurable PDR Phase Shift - PSU_DDR_PHY_DX6GCR0_CPDRSHFT 0x0 + * Configurable PDR Phase Shift + * PSU_DDR_PHY_DX8GCR0_CPDRSHFT 0x0 - DQSR Power Down - PSU_DDR_PHY_DX6GCR0_DQSRPD 0x0 + * DQSR Power Down + * PSU_DDR_PHY_DX8GCR0_DQSRPD 0x0 - DQSG Power Down Receiver - PSU_DDR_PHY_DX6GCR0_DQSGPDR 0x0 + * DQSG Power Down Receiver + * PSU_DDR_PHY_DX8GCR0_DQSGPDR 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX6GCR0_RESERVED_4 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8GCR0_RESERVED_4 0x0 - DQSG On-Die Termination - PSU_DDR_PHY_DX6GCR0_DQSGODT 0x0 + * DQSG On-Die Termination + * PSU_DDR_PHY_DX8GCR0_DQSGODT 0x0 - DQSG Output Enable - PSU_DDR_PHY_DX6GCR0_DQSGOE 0x1 + * DQSG Output Enable + * PSU_DDR_PHY_DX8GCR0_DQSGOE 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX6GCR0_RESERVED_1_0 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8GCR0_RESERVED_1_0 0x0 - DATX8 n General Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD080D00, 0xFFFFFFFFU ,0x40800604U) - RegMask = (DDR_PHY_DX6GCR0_CALBYP_MASK | DDR_PHY_DX6GCR0_MDLEN_MASK | DDR_PHY_DX6GCR0_CODTSHFT_MASK | DDR_PHY_DX6GCR0_DQSDCC_MASK | DDR_PHY_DX6GCR0_RDDLY_MASK | DDR_PHY_DX6GCR0_RESERVED_19_14_MASK | DDR_PHY_DX6GCR0_DQSNSEPDR_MASK | DDR_PHY_DX6GCR0_DQSSEPDR_MASK | DDR_PHY_DX6GCR0_RTTOAL_MASK | DDR_PHY_DX6GCR0_RTTOH_MASK | DDR_PHY_DX6GCR0_CPDRSHFT_MASK | DDR_PHY_DX6GCR0_DQSRPD_MASK | DDR_PHY_DX6GCR0_DQSGPDR_MASK | DDR_PHY_DX6GCR0_RESERVED_4_MASK | DDR_PHY_DX6GCR0_DQSGODT_MASK | DDR_PHY_DX6GCR0_DQSGOE_MASK | DDR_PHY_DX6GCR0_RESERVED_1_0_MASK | 0 ); + * DATX8 n General Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD080F00, 0xFFFFFFFFU ,0x40800624U) + */ + PSU_Mask_Write(DDR_PHY_DX8GCR0_OFFSET, 0xFFFFFFFFU, 0x40800624U); +/*##################################################################### */ - RegVal = ((0x00000000U << DDR_PHY_DX6GCR0_CALBYP_SHIFT - | 0x00000001U << DDR_PHY_DX6GCR0_MDLEN_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR0_CODTSHFT_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR0_DQSDCC_SHIFT - | 0x00000008U << DDR_PHY_DX6GCR0_RDDLY_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR0_RESERVED_19_14_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR0_DQSNSEPDR_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR0_DQSSEPDR_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR0_RTTOAL_SHIFT - | 0x00000003U << DDR_PHY_DX6GCR0_RTTOH_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR0_CPDRSHFT_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR0_DQSRPD_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR0_DQSGPDR_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR0_RESERVED_4_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR0_DQSGODT_SHIFT - | 0x00000001U << DDR_PHY_DX6GCR0_DQSGOE_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR0_RESERVED_1_0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX6GCR0_OFFSET ,0xFFFFFFFFU ,0x40800604U); - /*############################################################################################################################ */ + /* + * Register : DX8GCR1 @ 0XFD080F04 - /*Register : DX6GCR1 @ 0XFD080D04

+ * Enables the PDR mode for DQ[7:0] + * PSU_DDR_PHY_DX8GCR1_DXPDRMODE 0x0 - Enables the PDR mode for DQ[7:0] - PSU_DDR_PHY_DX6GCR1_DXPDRMODE 0x0 + * Reserved. Returns zeroes on reads. + * PSU_DDR_PHY_DX8GCR1_RESERVED_15 0x0 - Reserved. Returns zeroes on reads. - PSU_DDR_PHY_DX6GCR1_RESERVED_15 0x0 + * Select the delayed or non-delayed read data strobe # + * PSU_DDR_PHY_DX8GCR1_QSNSEL 0x1 - Select the delayed or non-delayed read data strobe # - PSU_DDR_PHY_DX6GCR1_QSNSEL 0x1 + * Select the delayed or non-delayed read data strobe + * PSU_DDR_PHY_DX8GCR1_QSSEL 0x1 - Select the delayed or non-delayed read data strobe - PSU_DDR_PHY_DX6GCR1_QSSEL 0x1 + * Enables Read Data Strobe in a byte lane + * PSU_DDR_PHY_DX8GCR1_OEEN 0x1 - Enables Read Data Strobe in a byte lane - PSU_DDR_PHY_DX6GCR1_OEEN 0x1 + * Enables PDR in a byte lane + * PSU_DDR_PHY_DX8GCR1_PDREN 0x1 - Enables PDR in a byte lane - PSU_DDR_PHY_DX6GCR1_PDREN 0x1 + * Enables ODT/TE in a byte lane + * PSU_DDR_PHY_DX8GCR1_TEEN 0x1 - Enables ODT/TE in a byte lane - PSU_DDR_PHY_DX6GCR1_TEEN 0x1 + * Enables Write Data strobe in a byte lane + * PSU_DDR_PHY_DX8GCR1_DSEN 0x1 - Enables Write Data strobe in a byte lane - PSU_DDR_PHY_DX6GCR1_DSEN 0x1 + * Enables DM pin in a byte lane + * PSU_DDR_PHY_DX8GCR1_DMEN 0x1 - Enables DM pin in a byte lane - PSU_DDR_PHY_DX6GCR1_DMEN 0x1 + * Enables DQ corresponding to each bit in a byte + * PSU_DDR_PHY_DX8GCR1_DQEN 0x0 - Enables DQ corresponding to each bit in a byte - PSU_DDR_PHY_DX6GCR1_DQEN 0xff + * DATX8 n General Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD080F04, 0xFFFFFFFFU ,0x00007F00U) + */ + PSU_Mask_Write(DDR_PHY_DX8GCR1_OFFSET, 0xFFFFFFFFU, 0x00007F00U); +/*##################################################################### */ - DATX8 n General Configuration Register 1 - (OFFSET, MASK, VALUE) (0XFD080D04, 0xFFFFFFFFU ,0x00007FFFU) - RegMask = (DDR_PHY_DX6GCR1_DXPDRMODE_MASK | DDR_PHY_DX6GCR1_RESERVED_15_MASK | DDR_PHY_DX6GCR1_QSNSEL_MASK | DDR_PHY_DX6GCR1_QSSEL_MASK | DDR_PHY_DX6GCR1_OEEN_MASK | DDR_PHY_DX6GCR1_PDREN_MASK | DDR_PHY_DX6GCR1_TEEN_MASK | DDR_PHY_DX6GCR1_DSEN_MASK | DDR_PHY_DX6GCR1_DMEN_MASK | DDR_PHY_DX6GCR1_DQEN_MASK | 0 ); + /* + * Register : DX8GCR4 @ 0XFD080F10 - RegVal = ((0x00000000U << DDR_PHY_DX6GCR1_DXPDRMODE_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR1_RESERVED_15_SHIFT - | 0x00000001U << DDR_PHY_DX6GCR1_QSNSEL_SHIFT - | 0x00000001U << DDR_PHY_DX6GCR1_QSSEL_SHIFT - | 0x00000001U << DDR_PHY_DX6GCR1_OEEN_SHIFT - | 0x00000001U << DDR_PHY_DX6GCR1_PDREN_SHIFT - | 0x00000001U << DDR_PHY_DX6GCR1_TEEN_SHIFT - | 0x00000001U << DDR_PHY_DX6GCR1_DSEN_SHIFT - | 0x00000001U << DDR_PHY_DX6GCR1_DMEN_SHIFT - | 0x000000FFU << DDR_PHY_DX6GCR1_DQEN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX6GCR1_OFFSET ,0xFFFFFFFFU ,0x00007FFFU); - /*############################################################################################################################ */ + * Byte lane VREF IOM (Used only by D4MU IOs) + * PSU_DDR_PHY_DX8GCR4_RESERVED_31_29 0x0 - /*Register : DX6GCR4 @ 0XFD080D10

+ * Byte Lane VREF Pad Enable + * PSU_DDR_PHY_DX8GCR4_DXREFPEN 0x0 - Byte lane VREF IOM (Used only by D4MU IOs) - PSU_DDR_PHY_DX6GCR4_RESERVED_31_29 0x0 + * Byte Lane Internal VREF Enable + * PSU_DDR_PHY_DX8GCR4_DXREFEEN 0x3 - Byte Lane VREF Pad Enable - PSU_DDR_PHY_DX6GCR4_DXREFPEN 0x0 + * Byte Lane Single-End VREF Enable + * PSU_DDR_PHY_DX8GCR4_DXREFSEN 0x1 - Byte Lane Internal VREF Enable - PSU_DDR_PHY_DX6GCR4_DXREFEEN 0x3 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX8GCR4_RESERVED_24 0x0 - Byte Lane Single-End VREF Enable - PSU_DDR_PHY_DX6GCR4_DXREFSEN 0x1 + * External VREF generator REFSEL range select + * PSU_DDR_PHY_DX8GCR4_DXREFESELRANGE 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX6GCR4_RESERVED_24 0x0 + * Byte Lane External VREF Select + * PSU_DDR_PHY_DX8GCR4_DXREFESEL 0x0 - External VREF generator REFSEL range select - PSU_DDR_PHY_DX6GCR4_DXREFESELRANGE 0x0 + * Single ended VREF generator REFSEL range select + * PSU_DDR_PHY_DX8GCR4_DXREFSSELRANGE 0x1 - Byte Lane External VREF Select - PSU_DDR_PHY_DX6GCR4_DXREFESEL 0x0 + * Byte Lane Single-End VREF Select + * PSU_DDR_PHY_DX8GCR4_DXREFSSEL 0x30 - Single ended VREF generator REFSEL range select - PSU_DDR_PHY_DX6GCR4_DXREFSSELRANGE 0x1 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX8GCR4_RESERVED_7_6 0x0 - Byte Lane Single-End VREF Select - PSU_DDR_PHY_DX6GCR4_DXREFSSEL 0x30 + * VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX8GCR4_DXREFIEN 0xf - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX6GCR4_RESERVED_7_6 0x0 + * VRMON control for DQ IO (Single Ended) buffers of a byte lane. + * PSU_DDR_PHY_DX8GCR4_DXREFIMON 0x0 - VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. - PSU_DDR_PHY_DX6GCR4_DXREFIEN 0xf + * DATX8 n General Configuration Register 4 + * (OFFSET, MASK, VALUE) (0XFD080F10, 0xFFFFFFFFU ,0x0E00B03CU) + */ + PSU_Mask_Write(DDR_PHY_DX8GCR4_OFFSET, 0xFFFFFFFFU, 0x0E00B03CU); +/*##################################################################### */ - VRMON control for DQ IO (Single Ended) buffers of a byte lane. - PSU_DDR_PHY_DX6GCR4_DXREFIMON 0x0 + /* + * Register : DX8GCR5 @ 0XFD080F14 - DATX8 n General Configuration Register 4 - (OFFSET, MASK, VALUE) (0XFD080D10, 0xFFFFFFFFU ,0x0E00B03CU) - RegMask = (DDR_PHY_DX6GCR4_RESERVED_31_29_MASK | DDR_PHY_DX6GCR4_DXREFPEN_MASK | DDR_PHY_DX6GCR4_DXREFEEN_MASK | DDR_PHY_DX6GCR4_DXREFSEN_MASK | DDR_PHY_DX6GCR4_RESERVED_24_MASK | DDR_PHY_DX6GCR4_DXREFESELRANGE_MASK | DDR_PHY_DX6GCR4_DXREFESEL_MASK | DDR_PHY_DX6GCR4_DXREFSSELRANGE_MASK | DDR_PHY_DX6GCR4_DXREFSSEL_MASK | DDR_PHY_DX6GCR4_RESERVED_7_6_MASK | DDR_PHY_DX6GCR4_DXREFIEN_MASK | DDR_PHY_DX6GCR4_DXREFIMON_MASK | 0 ); + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX8GCR5_RESERVED_31 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX6GCR4_RESERVED_31_29_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR4_DXREFPEN_SHIFT - | 0x00000003U << DDR_PHY_DX6GCR4_DXREFEEN_SHIFT - | 0x00000001U << DDR_PHY_DX6GCR4_DXREFSEN_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR4_RESERVED_24_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR4_DXREFESELRANGE_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR4_DXREFESEL_SHIFT - | 0x00000001U << DDR_PHY_DX6GCR4_DXREFSSELRANGE_SHIFT - | 0x00000030U << DDR_PHY_DX6GCR4_DXREFSSEL_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR4_RESERVED_7_6_SHIFT - | 0x0000000FU << DDR_PHY_DX6GCR4_DXREFIEN_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR4_DXREFIMON_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX6GCR4_OFFSET ,0xFFFFFFFFU ,0x0E00B03CU); - /*############################################################################################################################ */ + * Byte Lane internal VREF Select for Rank 3 + * PSU_DDR_PHY_DX8GCR5_DXREFISELR3 0x9 - /*Register : DX6GCR5 @ 0XFD080D14

+ * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX8GCR5_RESERVED_23 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX6GCR5_RESERVED_31 0x0 + * Byte Lane internal VREF Select for Rank 2 + * PSU_DDR_PHY_DX8GCR5_DXREFISELR2 0x9 - Byte Lane internal VREF Select for Rank 3 - PSU_DDR_PHY_DX6GCR5_DXREFISELR3 0x9 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX8GCR5_RESERVED_15 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX6GCR5_RESERVED_23 0x0 + * Byte Lane internal VREF Select for Rank 1 + * PSU_DDR_PHY_DX8GCR5_DXREFISELR1 0x55 - Byte Lane internal VREF Select for Rank 2 - PSU_DDR_PHY_DX6GCR5_DXREFISELR2 0x9 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX8GCR5_RESERVED_7 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX6GCR5_RESERVED_15 0x0 + * Byte Lane internal VREF Select for Rank 0 + * PSU_DDR_PHY_DX8GCR5_DXREFISELR0 0x55 - Byte Lane internal VREF Select for Rank 1 - PSU_DDR_PHY_DX6GCR5_DXREFISELR1 0x4f + * DATX8 n General Configuration Register 5 + * (OFFSET, MASK, VALUE) (0XFD080F14, 0xFFFFFFFFU ,0x09095555U) + */ + PSU_Mask_Write(DDR_PHY_DX8GCR5_OFFSET, 0xFFFFFFFFU, 0x09095555U); +/*##################################################################### */ - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX6GCR5_RESERVED_7 0x0 + /* + * Register : DX8GCR6 @ 0XFD080F18 - Byte Lane internal VREF Select for Rank 0 - PSU_DDR_PHY_DX6GCR5_DXREFISELR0 0x4f + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX8GCR6_RESERVED_31_30 0x0 - DATX8 n General Configuration Register 5 - (OFFSET, MASK, VALUE) (0XFD080D14, 0xFFFFFFFFU ,0x09094F4FU) - RegMask = (DDR_PHY_DX6GCR5_RESERVED_31_MASK | DDR_PHY_DX6GCR5_DXREFISELR3_MASK | DDR_PHY_DX6GCR5_RESERVED_23_MASK | DDR_PHY_DX6GCR5_DXREFISELR2_MASK | DDR_PHY_DX6GCR5_RESERVED_15_MASK | DDR_PHY_DX6GCR5_DXREFISELR1_MASK | DDR_PHY_DX6GCR5_RESERVED_7_MASK | DDR_PHY_DX6GCR5_DXREFISELR0_MASK | 0 ); + * DRAM DQ VREF Select for Rank3 + * PSU_DDR_PHY_DX8GCR6_DXDQVREFR3 0x9 - RegVal = ((0x00000000U << DDR_PHY_DX6GCR5_RESERVED_31_SHIFT - | 0x00000009U << DDR_PHY_DX6GCR5_DXREFISELR3_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR5_RESERVED_23_SHIFT - | 0x00000009U << DDR_PHY_DX6GCR5_DXREFISELR2_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR5_RESERVED_15_SHIFT - | 0x0000004FU << DDR_PHY_DX6GCR5_DXREFISELR1_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR5_RESERVED_7_SHIFT - | 0x0000004FU << DDR_PHY_DX6GCR5_DXREFISELR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX6GCR5_OFFSET ,0xFFFFFFFFU ,0x09094F4FU); - /*############################################################################################################################ */ + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX8GCR6_RESERVED_23_22 0x0 - /*Register : DX6GCR6 @ 0XFD080D18

+ * DRAM DQ VREF Select for Rank2 + * PSU_DDR_PHY_DX8GCR6_DXDQVREFR2 0x9 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX6GCR6_RESERVED_31_30 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX8GCR6_RESERVED_15_14 0x0 - DRAM DQ VREF Select for Rank3 - PSU_DDR_PHY_DX6GCR6_DXDQVREFR3 0x9 + * DRAM DQ VREF Select for Rank1 + * PSU_DDR_PHY_DX8GCR6_DXDQVREFR1 0x2b - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX6GCR6_RESERVED_23_22 0x0 + * Reserved. Returns zeros on reads. + * PSU_DDR_PHY_DX8GCR6_RESERVED_7_6 0x0 - DRAM DQ VREF Select for Rank2 - PSU_DDR_PHY_DX6GCR6_DXDQVREFR2 0x9 + * DRAM DQ VREF Select for Rank0 + * PSU_DDR_PHY_DX8GCR6_DXDQVREFR0 0x2b - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX6GCR6_RESERVED_15_14 0x0 + * DATX8 n General Configuration Register 6 + * (OFFSET, MASK, VALUE) (0XFD080F18, 0xFFFFFFFFU ,0x09092B2BU) + */ + PSU_Mask_Write(DDR_PHY_DX8GCR6_OFFSET, 0xFFFFFFFFU, 0x09092B2BU); +/*##################################################################### */ - DRAM DQ VREF Select for Rank1 - PSU_DDR_PHY_DX6GCR6_DXDQVREFR1 0x2b + /* + * Register : DX8SL0OSC @ 0XFD081400 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX6GCR6_RESERVED_7_6 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL0OSC_RESERVED_31_30 0x0 - DRAM DQ VREF Select for Rank0 - PSU_DDR_PHY_DX6GCR6_DXDQVREFR0 0x2b + * Enable Clock Gating for DX ddr_clk + * PSU_DDR_PHY_DX8SL0OSC_GATEDXRDCLK 0x2 - DATX8 n General Configuration Register 6 - (OFFSET, MASK, VALUE) (0XFD080D18, 0xFFFFFFFFU ,0x09092B2BU) - RegMask = (DDR_PHY_DX6GCR6_RESERVED_31_30_MASK | DDR_PHY_DX6GCR6_DXDQVREFR3_MASK | DDR_PHY_DX6GCR6_RESERVED_23_22_MASK | DDR_PHY_DX6GCR6_DXDQVREFR2_MASK | DDR_PHY_DX6GCR6_RESERVED_15_14_MASK | DDR_PHY_DX6GCR6_DXDQVREFR1_MASK | DDR_PHY_DX6GCR6_RESERVED_7_6_MASK | DDR_PHY_DX6GCR6_DXDQVREFR0_MASK | 0 ); + * Enable Clock Gating for DX ctl_rd_clk + * PSU_DDR_PHY_DX8SL0OSC_GATEDXDDRCLK 0x2 - RegVal = ((0x00000000U << DDR_PHY_DX6GCR6_RESERVED_31_30_SHIFT - | 0x00000009U << DDR_PHY_DX6GCR6_DXDQVREFR3_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR6_RESERVED_23_22_SHIFT - | 0x00000009U << DDR_PHY_DX6GCR6_DXDQVREFR2_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR6_RESERVED_15_14_SHIFT - | 0x0000002BU << DDR_PHY_DX6GCR6_DXDQVREFR1_SHIFT - | 0x00000000U << DDR_PHY_DX6GCR6_RESERVED_7_6_SHIFT - | 0x0000002BU << DDR_PHY_DX6GCR6_DXDQVREFR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX6GCR6_OFFSET ,0xFFFFFFFFU ,0x09092B2BU); - /*############################################################################################################################ */ + * Enable Clock Gating for DX ctl_clk + * PSU_DDR_PHY_DX8SL0OSC_GATEDXCTLCLK 0x2 - /*Register : DX6LCDLR2 @ 0XFD080D88

+ * Selects the level to which clocks will be stalled when clock gating is e + * nabled. + * PSU_DDR_PHY_DX8SL0OSC_CLKLEVEL 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX6LCDLR2_RESERVED_31_25 0x0 + * Loopback Mode + * PSU_DDR_PHY_DX8SL0OSC_LBMODE 0x0 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX6LCDLR2_RESERVED_24_16 0x0 + * Load GSDQS LCDL with 2x the calibrated GSDQSPRD value + * PSU_DDR_PHY_DX8SL0OSC_LBGSDQS 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX6LCDLR2_RESERVED_15_9 0x0 + * Loopback DQS Gating + * PSU_DDR_PHY_DX8SL0OSC_LBGDQS 0x0 - Read DQS Gating Delay - PSU_DDR_PHY_DX6LCDLR2_DQSGD 0x0 + * Loopback DQS Shift + * PSU_DDR_PHY_DX8SL0OSC_LBDQSS 0x0 - DATX8 n Local Calibrated Delay Line Register 2 - (OFFSET, MASK, VALUE) (0XFD080D88, 0xFFFFFFFFU ,0x00000000U) - RegMask = (DDR_PHY_DX6LCDLR2_RESERVED_31_25_MASK | DDR_PHY_DX6LCDLR2_RESERVED_24_16_MASK | DDR_PHY_DX6LCDLR2_RESERVED_15_9_MASK | DDR_PHY_DX6LCDLR2_DQSGD_MASK | 0 ); + * PHY High-Speed Reset + * PSU_DDR_PHY_DX8SL0OSC_PHYHRST 0x1 - RegVal = ((0x00000000U << DDR_PHY_DX6LCDLR2_RESERVED_31_25_SHIFT - | 0x00000000U << DDR_PHY_DX6LCDLR2_RESERVED_24_16_SHIFT - | 0x00000000U << DDR_PHY_DX6LCDLR2_RESERVED_15_9_SHIFT - | 0x00000000U << DDR_PHY_DX6LCDLR2_DQSGD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX6LCDLR2_OFFSET ,0xFFFFFFFFU ,0x00000000U); - /*############################################################################################################################ */ + * PHY FIFO Reset + * PSU_DDR_PHY_DX8SL0OSC_PHYFRST 0x1 - /*Register : DX6GTR0 @ 0XFD080DC0

+ * Delay Line Test Start + * PSU_DDR_PHY_DX8SL0OSC_DLTST 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX6GTR0_RESERVED_31_24 0x0 + * Delay Line Test Mode + * PSU_DDR_PHY_DX8SL0OSC_DLTMODE 0x0 - DQ Write Path Latency Pipeline - PSU_DDR_PHY_DX6GTR0_WDQSL 0x0 + * Reserved. Caution, do not write to this register field. + * PSU_DDR_PHY_DX8SL0OSC_RESERVED_12_11 0x3 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX6GTR0_RESERVED_23_20 0x0 + * Oscillator Mode Write-Data Delay Line Select + * PSU_DDR_PHY_DX8SL0OSC_OSCWDDL 0x3 - Write Leveling System Latency - PSU_DDR_PHY_DX6GTR0_WLSL 0x2 + * Reserved. Caution, do not write to this register field. + * PSU_DDR_PHY_DX8SL0OSC_RESERVED_8_7 0x3 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX6GTR0_RESERVED_15_13 0x0 + * Oscillator Mode Write-Leveling Delay Line Select + * PSU_DDR_PHY_DX8SL0OSC_OSCWDL 0x3 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX6GTR0_RESERVED_12_8 0x0 + * Oscillator Mode Division + * PSU_DDR_PHY_DX8SL0OSC_OSCDIV 0xf - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX6GTR0_RESERVED_7_5 0x0 + * Oscillator Enable + * PSU_DDR_PHY_DX8SL0OSC_OSCEN 0x0 - DQS Gating System Latency - PSU_DDR_PHY_DX6GTR0_DGSL 0x0 + * DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Lo + * opback, and Gated Clock Control Register + * (OFFSET, MASK, VALUE) (0XFD081400, 0xFFFFFFFFU ,0x2A019FFEU) + */ + PSU_Mask_Write(DDR_PHY_DX8SL0OSC_OFFSET, 0xFFFFFFFFU, 0x2A019FFEU); +/*##################################################################### */ - DATX8 n General Timing Register 0 - (OFFSET, MASK, VALUE) (0XFD080DC0, 0xFFFFFFFFU ,0x00020000U) - RegMask = (DDR_PHY_DX6GTR0_RESERVED_31_24_MASK | DDR_PHY_DX6GTR0_WDQSL_MASK | DDR_PHY_DX6GTR0_RESERVED_23_20_MASK | DDR_PHY_DX6GTR0_WLSL_MASK | DDR_PHY_DX6GTR0_RESERVED_15_13_MASK | DDR_PHY_DX6GTR0_RESERVED_12_8_MASK | DDR_PHY_DX6GTR0_RESERVED_7_5_MASK | DDR_PHY_DX6GTR0_DGSL_MASK | 0 ); + /* + * Register : DX8SL0PLLCR0 @ 0XFD081404 - RegVal = ((0x00000000U << DDR_PHY_DX6GTR0_RESERVED_31_24_SHIFT - | 0x00000000U << DDR_PHY_DX6GTR0_WDQSL_SHIFT - | 0x00000000U << DDR_PHY_DX6GTR0_RESERVED_23_20_SHIFT - | 0x00000002U << DDR_PHY_DX6GTR0_WLSL_SHIFT - | 0x00000000U << DDR_PHY_DX6GTR0_RESERVED_15_13_SHIFT - | 0x00000000U << DDR_PHY_DX6GTR0_RESERVED_12_8_SHIFT - | 0x00000000U << DDR_PHY_DX6GTR0_RESERVED_7_5_SHIFT - | 0x00000000U << DDR_PHY_DX6GTR0_DGSL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX6GTR0_OFFSET ,0xFFFFFFFFU ,0x00020000U); - /*############################################################################################################################ */ + * PLL Bypass + * PSU_DDR_PHY_DX8SL0PLLCR0_PLLBYP 0x0 - /*Register : DX7GCR0 @ 0XFD080E00

+ * PLL Reset + * PSU_DDR_PHY_DX8SL0PLLCR0_PLLRST 0x0 - Calibration Bypass - PSU_DDR_PHY_DX7GCR0_CALBYP 0x0 + * PLL Power Down + * PSU_DDR_PHY_DX8SL0PLLCR0_PLLPD 0x0 - Master Delay Line Enable - PSU_DDR_PHY_DX7GCR0_MDLEN 0x1 + * Reference Stop Mode + * PSU_DDR_PHY_DX8SL0PLLCR0_RSTOPM 0x0 - Configurable ODT(TE) Phase Shift - PSU_DDR_PHY_DX7GCR0_CODTSHFT 0x0 + * PLL Frequency Select + * PSU_DDR_PHY_DX8SL0PLLCR0_FRQSEL 0x1 - DQS Duty Cycle Correction - PSU_DDR_PHY_DX7GCR0_DQSDCC 0x0 + * Relock Mode + * PSU_DDR_PHY_DX8SL0PLLCR0_RLOCKM 0x0 - Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY - PSU_DDR_PHY_DX7GCR0_RDDLY 0x8 + * Charge Pump Proportional Current Control + * PSU_DDR_PHY_DX8SL0PLLCR0_CPPC 0x8 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX7GCR0_RESERVED_19_14 0x0 + * Charge Pump Integrating Current Control + * PSU_DDR_PHY_DX8SL0PLLCR0_CPIC 0x0 - DQSNSE Power Down Receiver - PSU_DDR_PHY_DX7GCR0_DQSNSEPDR 0x0 + * Gear Shift + * PSU_DDR_PHY_DX8SL0PLLCR0_GSHIFT 0x0 - DQSSE Power Down Receiver - PSU_DDR_PHY_DX7GCR0_DQSSEPDR 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL0PLLCR0_RESERVED_11_9 0x0 - RTT On Additive Latency - PSU_DDR_PHY_DX7GCR0_RTTOAL 0x0 + * Analog Test Enable (ATOEN) + * PSU_DDR_PHY_DX8SL0PLLCR0_ATOEN 0x0 - RTT Output Hold - PSU_DDR_PHY_DX7GCR0_RTTOH 0x3 + * Analog Test Control + * PSU_DDR_PHY_DX8SL0PLLCR0_ATC 0x0 - Configurable PDR Phase Shift - PSU_DDR_PHY_DX7GCR0_CPDRSHFT 0x0 + * Digital Test Control + * PSU_DDR_PHY_DX8SL0PLLCR0_DTC 0x0 - DQSR Power Down - PSU_DDR_PHY_DX7GCR0_DQSRPD 0x0 + * DAXT8 0-1 PLL Control Register 0 + * (OFFSET, MASK, VALUE) (0XFD081404, 0xFFFFFFFFU ,0x01100000U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL0PLLCR0_OFFSET, + 0xFFFFFFFFU, 0x01100000U); +/*##################################################################### */ - DQSG Power Down Receiver - PSU_DDR_PHY_DX7GCR0_DQSGPDR 0x0 + /* + * Register : DX8SL0DQSCTL @ 0XFD08141C - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX7GCR0_RESERVED_4 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25 0x0 - DQSG On-Die Termination - PSU_DDR_PHY_DX7GCR0_DQSGODT 0x0 + * Read Path Rise-to-Rise Mode + * PSU_DDR_PHY_DX8SL0DQSCTL_RRRMODE 0x1 - DQSG Output Enable - PSU_DDR_PHY_DX7GCR0_DQSGOE 0x1 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX7GCR0_RESERVED_1_0 0x0 + * Write Path Rise-to-Rise Mode + * PSU_DDR_PHY_DX8SL0DQSCTL_WRRMODE 0x1 - DATX8 n General Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD080E00, 0xFFFFFFFFU ,0x40800604U) - RegMask = (DDR_PHY_DX7GCR0_CALBYP_MASK | DDR_PHY_DX7GCR0_MDLEN_MASK | DDR_PHY_DX7GCR0_CODTSHFT_MASK | DDR_PHY_DX7GCR0_DQSDCC_MASK | DDR_PHY_DX7GCR0_RDDLY_MASK | DDR_PHY_DX7GCR0_RESERVED_19_14_MASK | DDR_PHY_DX7GCR0_DQSNSEPDR_MASK | DDR_PHY_DX7GCR0_DQSSEPDR_MASK | DDR_PHY_DX7GCR0_RTTOAL_MASK | DDR_PHY_DX7GCR0_RTTOH_MASK | DDR_PHY_DX7GCR0_CPDRSHFT_MASK | DDR_PHY_DX7GCR0_DQSRPD_MASK | DDR_PHY_DX7GCR0_DQSGPDR_MASK | DDR_PHY_DX7GCR0_RESERVED_4_MASK | DDR_PHY_DX7GCR0_DQSGODT_MASK | DDR_PHY_DX7GCR0_DQSGOE_MASK | DDR_PHY_DX7GCR0_RESERVED_1_0_MASK | 0 ); + * DQS Gate Extension + * PSU_DDR_PHY_DX8SL0DQSCTL_DQSGX 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX7GCR0_CALBYP_SHIFT - | 0x00000001U << DDR_PHY_DX7GCR0_MDLEN_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR0_CODTSHFT_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR0_DQSDCC_SHIFT - | 0x00000008U << DDR_PHY_DX7GCR0_RDDLY_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR0_RESERVED_19_14_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR0_DQSNSEPDR_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR0_DQSSEPDR_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR0_RTTOAL_SHIFT - | 0x00000003U << DDR_PHY_DX7GCR0_RTTOH_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR0_CPDRSHFT_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR0_DQSRPD_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR0_DQSGPDR_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR0_RESERVED_4_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR0_DQSGODT_SHIFT - | 0x00000001U << DDR_PHY_DX7GCR0_DQSGOE_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR0_RESERVED_1_0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX7GCR0_OFFSET ,0xFFFFFFFFU ,0x40800604U); - /*############################################################################################################################ */ + * Low Power PLL Power Down + * PSU_DDR_PHY_DX8SL0DQSCTL_LPPLLPD 0x1 - /*Register : DX7GCR1 @ 0XFD080E04

+ * Low Power I/O Power Down + * PSU_DDR_PHY_DX8SL0DQSCTL_LPIOPD 0x1 - Enables the PDR mode for DQ[7:0] - PSU_DDR_PHY_DX7GCR1_DXPDRMODE 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15 0x0 - Reserved. Returns zeroes on reads. - PSU_DDR_PHY_DX7GCR1_RESERVED_15 0x0 + * QS Counter Enable + * PSU_DDR_PHY_DX8SL0DQSCTL_QSCNTEN 0x1 - Select the delayed or non-delayed read data strobe # - PSU_DDR_PHY_DX7GCR1_QSNSEL 0x1 + * Unused DQ I/O Mode + * PSU_DDR_PHY_DX8SL0DQSCTL_UDQIOM 0x0 - Select the delayed or non-delayed read data strobe - PSU_DDR_PHY_DX7GCR1_QSSEL 0x1 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10 0x0 - Enables Read Data Strobe in a byte lane - PSU_DDR_PHY_DX7GCR1_OEEN 0x1 + * Data Slew Rate + * PSU_DDR_PHY_DX8SL0DQSCTL_DXSR 0x3 - Enables PDR in a byte lane - PSU_DDR_PHY_DX7GCR1_PDREN 0x1 + * DQS_N Resistor + * PSU_DDR_PHY_DX8SL0DQSCTL_DQSNRES 0x0 - Enables ODT/TE in a byte lane - PSU_DDR_PHY_DX7GCR1_TEEN 0x1 + * DQS Resistor + * PSU_DDR_PHY_DX8SL0DQSCTL_DQSRES 0x0 - Enables Write Data strobe in a byte lane - PSU_DDR_PHY_DX7GCR1_DSEN 0x1 + * DATX8 0-1 DQS Control Register + * (OFFSET, MASK, VALUE) (0XFD08141C, 0xFFFFFFFFU ,0x01264300U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL0DQSCTL_OFFSET, + 0xFFFFFFFFU, 0x01264300U); +/*##################################################################### */ - Enables DM pin in a byte lane - PSU_DDR_PHY_DX7GCR1_DMEN 0x1 + /* + * Register : DX8SL0DXCTL2 @ 0XFD08142C - Enables DQ corresponding to each bit in a byte - PSU_DDR_PHY_DX7GCR1_DQEN 0xff + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24 0x0 - DATX8 n General Configuration Register 1 - (OFFSET, MASK, VALUE) (0XFD080E04, 0xFFFFFFFFU ,0x00007FFFU) - RegMask = (DDR_PHY_DX7GCR1_DXPDRMODE_MASK | DDR_PHY_DX7GCR1_RESERVED_15_MASK | DDR_PHY_DX7GCR1_QSNSEL_MASK | DDR_PHY_DX7GCR1_QSSEL_MASK | DDR_PHY_DX7GCR1_OEEN_MASK | DDR_PHY_DX7GCR1_PDREN_MASK | DDR_PHY_DX7GCR1_TEEN_MASK | DDR_PHY_DX7GCR1_DSEN_MASK | DDR_PHY_DX7GCR1_DMEN_MASK | DDR_PHY_DX7GCR1_DQEN_MASK | 0 ); + * Configurable Read Data Enable + * PSU_DDR_PHY_DX8SL0DXCTL2_CRDEN 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX7GCR1_DXPDRMODE_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR1_RESERVED_15_SHIFT - | 0x00000001U << DDR_PHY_DX7GCR1_QSNSEL_SHIFT - | 0x00000001U << DDR_PHY_DX7GCR1_QSSEL_SHIFT - | 0x00000001U << DDR_PHY_DX7GCR1_OEEN_SHIFT - | 0x00000001U << DDR_PHY_DX7GCR1_PDREN_SHIFT - | 0x00000001U << DDR_PHY_DX7GCR1_TEEN_SHIFT - | 0x00000001U << DDR_PHY_DX7GCR1_DSEN_SHIFT - | 0x00000001U << DDR_PHY_DX7GCR1_DMEN_SHIFT - | 0x000000FFU << DDR_PHY_DX7GCR1_DQEN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX7GCR1_OFFSET ,0xFFFFFFFFU ,0x00007FFFU); - /*############################################################################################################################ */ + * OX Extension during Post-amble + * PSU_DDR_PHY_DX8SL0DXCTL2_POSOEX 0x0 - /*Register : DX7GCR4 @ 0XFD080E10

+ * OE Extension during Pre-amble + * PSU_DDR_PHY_DX8SL0DXCTL2_PREOEX 0x1 - Byte lane VREF IOM (Used only by D4MU IOs) - PSU_DDR_PHY_DX7GCR4_RESERVED_31_29 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_17 0x0 - Byte Lane VREF Pad Enable - PSU_DDR_PHY_DX7GCR4_DXREFPEN 0x0 + * I/O Assisted Gate Select + * PSU_DDR_PHY_DX8SL0DXCTL2_IOAG 0x0 - Byte Lane Internal VREF Enable - PSU_DDR_PHY_DX7GCR4_DXREFEEN 0x3 + * I/O Loopback Select + * PSU_DDR_PHY_DX8SL0DXCTL2_IOLB 0x0 - Byte Lane Single-End VREF Enable - PSU_DDR_PHY_DX7GCR4_DXREFSEN 0x1 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX7GCR4_RESERVED_24 0x0 + * Low Power Wakeup Threshold + * PSU_DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH 0xc - External VREF generator REFSEL range select - PSU_DDR_PHY_DX7GCR4_DXREFESELRANGE 0x0 + * Read Data Bus Inversion Enable + * PSU_DDR_PHY_DX8SL0DXCTL2_RDBI 0x0 - Byte Lane External VREF Select - PSU_DDR_PHY_DX7GCR4_DXREFESEL 0x0 + * Write Data Bus Inversion Enable + * PSU_DDR_PHY_DX8SL0DXCTL2_WDBI 0x0 - Single ended VREF generator REFSEL range select - PSU_DDR_PHY_DX7GCR4_DXREFSSELRANGE 0x1 + * PUB Read FIFO Bypass + * PSU_DDR_PHY_DX8SL0DXCTL2_PRFBYP 0x0 - Byte Lane Single-End VREF Select - PSU_DDR_PHY_DX7GCR4_DXREFSSEL 0x30 + * DATX8 Receive FIFO Read Mode + * PSU_DDR_PHY_DX8SL0DXCTL2_RDMODE 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX7GCR4_RESERVED_7_6 0x0 + * Disables the Read FIFO Reset + * PSU_DDR_PHY_DX8SL0DXCTL2_DISRST 0x0 - VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. - PSU_DDR_PHY_DX7GCR4_DXREFIEN 0xf + * Read DQS Gate I/O Loopback + * PSU_DDR_PHY_DX8SL0DXCTL2_DQSGLB 0x0 - VRMON control for DQ IO (Single Ended) buffers of a byte lane. - PSU_DDR_PHY_DX7GCR4_DXREFIMON 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_0 0x0 - DATX8 n General Configuration Register 4 - (OFFSET, MASK, VALUE) (0XFD080E10, 0xFFFFFFFFU ,0x0E00B03CU) - RegMask = (DDR_PHY_DX7GCR4_RESERVED_31_29_MASK | DDR_PHY_DX7GCR4_DXREFPEN_MASK | DDR_PHY_DX7GCR4_DXREFEEN_MASK | DDR_PHY_DX7GCR4_DXREFSEN_MASK | DDR_PHY_DX7GCR4_RESERVED_24_MASK | DDR_PHY_DX7GCR4_DXREFESELRANGE_MASK | DDR_PHY_DX7GCR4_DXREFESEL_MASK | DDR_PHY_DX7GCR4_DXREFSSELRANGE_MASK | DDR_PHY_DX7GCR4_DXREFSSEL_MASK | DDR_PHY_DX7GCR4_RESERVED_7_6_MASK | DDR_PHY_DX7GCR4_DXREFIEN_MASK | DDR_PHY_DX7GCR4_DXREFIMON_MASK | 0 ); + * DATX8 0-1 DX Control Register 2 + * (OFFSET, MASK, VALUE) (0XFD08142C, 0xFFFFFFFFU ,0x00041800U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL0DXCTL2_OFFSET, + 0xFFFFFFFFU, 0x00041800U); +/*##################################################################### */ - RegVal = ((0x00000000U << DDR_PHY_DX7GCR4_RESERVED_31_29_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR4_DXREFPEN_SHIFT - | 0x00000003U << DDR_PHY_DX7GCR4_DXREFEEN_SHIFT - | 0x00000001U << DDR_PHY_DX7GCR4_DXREFSEN_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR4_RESERVED_24_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR4_DXREFESELRANGE_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR4_DXREFESEL_SHIFT - | 0x00000001U << DDR_PHY_DX7GCR4_DXREFSSELRANGE_SHIFT - | 0x00000030U << DDR_PHY_DX7GCR4_DXREFSSEL_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR4_RESERVED_7_6_SHIFT - | 0x0000000FU << DDR_PHY_DX7GCR4_DXREFIEN_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR4_DXREFIMON_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX7GCR4_OFFSET ,0xFFFFFFFFU ,0x0E00B03CU); - /*############################################################################################################################ */ + /* + * Register : DX8SL0IOCR @ 0XFD081430 - /*Register : DX7GCR5 @ 0XFD080E14

+ * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL0IOCR_RESERVED_31 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX7GCR5_RESERVED_31 0x0 + * PVREF_DAC REFSEL range select + * PSU_DDR_PHY_DX8SL0IOCR_DXDACRANGE 0x7 - Byte Lane internal VREF Select for Rank 3 - PSU_DDR_PHY_DX7GCR5_DXREFISELR3 0x9 + * IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring + * PSU_DDR_PHY_DX8SL0IOCR_DXVREFIOM 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX7GCR5_RESERVED_23 0x0 + * DX IO Mode + * PSU_DDR_PHY_DX8SL0IOCR_DXIOM 0x2 - Byte Lane internal VREF Select for Rank 2 - PSU_DDR_PHY_DX7GCR5_DXREFISELR2 0x9 + * DX IO Transmitter Mode + * PSU_DDR_PHY_DX8SL0IOCR_DXTXM 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX7GCR5_RESERVED_15 0x0 + * DX IO Receiver Mode + * PSU_DDR_PHY_DX8SL0IOCR_DXRXM 0x0 - Byte Lane internal VREF Select for Rank 1 - PSU_DDR_PHY_DX7GCR5_DXREFISELR1 0x4f + * DATX8 0-1 I/O Configuration Register + * (OFFSET, MASK, VALUE) (0XFD081430, 0xFFFFFFFFU ,0x70800000U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL0IOCR_OFFSET, 0xFFFFFFFFU, 0x70800000U); +/*##################################################################### */ - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX7GCR5_RESERVED_7 0x0 + /* + * Register : DX8SL1OSC @ 0XFD081440 - Byte Lane internal VREF Select for Rank 0 - PSU_DDR_PHY_DX7GCR5_DXREFISELR0 0x4f + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL1OSC_RESERVED_31_30 0x0 - DATX8 n General Configuration Register 5 - (OFFSET, MASK, VALUE) (0XFD080E14, 0xFFFFFFFFU ,0x09094F4FU) - RegMask = (DDR_PHY_DX7GCR5_RESERVED_31_MASK | DDR_PHY_DX7GCR5_DXREFISELR3_MASK | DDR_PHY_DX7GCR5_RESERVED_23_MASK | DDR_PHY_DX7GCR5_DXREFISELR2_MASK | DDR_PHY_DX7GCR5_RESERVED_15_MASK | DDR_PHY_DX7GCR5_DXREFISELR1_MASK | DDR_PHY_DX7GCR5_RESERVED_7_MASK | DDR_PHY_DX7GCR5_DXREFISELR0_MASK | 0 ); + * Enable Clock Gating for DX ddr_clk + * PSU_DDR_PHY_DX8SL1OSC_GATEDXRDCLK 0x2 - RegVal = ((0x00000000U << DDR_PHY_DX7GCR5_RESERVED_31_SHIFT - | 0x00000009U << DDR_PHY_DX7GCR5_DXREFISELR3_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR5_RESERVED_23_SHIFT - | 0x00000009U << DDR_PHY_DX7GCR5_DXREFISELR2_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR5_RESERVED_15_SHIFT - | 0x0000004FU << DDR_PHY_DX7GCR5_DXREFISELR1_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR5_RESERVED_7_SHIFT - | 0x0000004FU << DDR_PHY_DX7GCR5_DXREFISELR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX7GCR5_OFFSET ,0xFFFFFFFFU ,0x09094F4FU); - /*############################################################################################################################ */ + * Enable Clock Gating for DX ctl_rd_clk + * PSU_DDR_PHY_DX8SL1OSC_GATEDXDDRCLK 0x2 - /*Register : DX7GCR6 @ 0XFD080E18

+ * Enable Clock Gating for DX ctl_clk + * PSU_DDR_PHY_DX8SL1OSC_GATEDXCTLCLK 0x2 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX7GCR6_RESERVED_31_30 0x0 + * Selects the level to which clocks will be stalled when clock gating is e + * nabled. + * PSU_DDR_PHY_DX8SL1OSC_CLKLEVEL 0x0 - DRAM DQ VREF Select for Rank3 - PSU_DDR_PHY_DX7GCR6_DXDQVREFR3 0x9 + * Loopback Mode + * PSU_DDR_PHY_DX8SL1OSC_LBMODE 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX7GCR6_RESERVED_23_22 0x0 + * Load GSDQS LCDL with 2x the calibrated GSDQSPRD value + * PSU_DDR_PHY_DX8SL1OSC_LBGSDQS 0x0 - DRAM DQ VREF Select for Rank2 - PSU_DDR_PHY_DX7GCR6_DXDQVREFR2 0x9 + * Loopback DQS Gating + * PSU_DDR_PHY_DX8SL1OSC_LBGDQS 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX7GCR6_RESERVED_15_14 0x0 + * Loopback DQS Shift + * PSU_DDR_PHY_DX8SL1OSC_LBDQSS 0x0 - DRAM DQ VREF Select for Rank1 - PSU_DDR_PHY_DX7GCR6_DXDQVREFR1 0x2b + * PHY High-Speed Reset + * PSU_DDR_PHY_DX8SL1OSC_PHYHRST 0x1 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX7GCR6_RESERVED_7_6 0x0 + * PHY FIFO Reset + * PSU_DDR_PHY_DX8SL1OSC_PHYFRST 0x1 - DRAM DQ VREF Select for Rank0 - PSU_DDR_PHY_DX7GCR6_DXDQVREFR0 0x2b + * Delay Line Test Start + * PSU_DDR_PHY_DX8SL1OSC_DLTST 0x0 - DATX8 n General Configuration Register 6 - (OFFSET, MASK, VALUE) (0XFD080E18, 0xFFFFFFFFU ,0x09092B2BU) - RegMask = (DDR_PHY_DX7GCR6_RESERVED_31_30_MASK | DDR_PHY_DX7GCR6_DXDQVREFR3_MASK | DDR_PHY_DX7GCR6_RESERVED_23_22_MASK | DDR_PHY_DX7GCR6_DXDQVREFR2_MASK | DDR_PHY_DX7GCR6_RESERVED_15_14_MASK | DDR_PHY_DX7GCR6_DXDQVREFR1_MASK | DDR_PHY_DX7GCR6_RESERVED_7_6_MASK | DDR_PHY_DX7GCR6_DXDQVREFR0_MASK | 0 ); + * Delay Line Test Mode + * PSU_DDR_PHY_DX8SL1OSC_DLTMODE 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX7GCR6_RESERVED_31_30_SHIFT - | 0x00000009U << DDR_PHY_DX7GCR6_DXDQVREFR3_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR6_RESERVED_23_22_SHIFT - | 0x00000009U << DDR_PHY_DX7GCR6_DXDQVREFR2_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR6_RESERVED_15_14_SHIFT - | 0x0000002BU << DDR_PHY_DX7GCR6_DXDQVREFR1_SHIFT - | 0x00000000U << DDR_PHY_DX7GCR6_RESERVED_7_6_SHIFT - | 0x0000002BU << DDR_PHY_DX7GCR6_DXDQVREFR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX7GCR6_OFFSET ,0xFFFFFFFFU ,0x09092B2BU); - /*############################################################################################################################ */ + * Reserved. Caution, do not write to this register field. + * PSU_DDR_PHY_DX8SL1OSC_RESERVED_12_11 0x3 - /*Register : DX7LCDLR2 @ 0XFD080E88

+ * Oscillator Mode Write-Data Delay Line Select + * PSU_DDR_PHY_DX8SL1OSC_OSCWDDL 0x3 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX7LCDLR2_RESERVED_31_25 0x0 + * Reserved. Caution, do not write to this register field. + * PSU_DDR_PHY_DX8SL1OSC_RESERVED_8_7 0x3 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX7LCDLR2_RESERVED_24_16 0x0 + * Oscillator Mode Write-Leveling Delay Line Select + * PSU_DDR_PHY_DX8SL1OSC_OSCWDL 0x3 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX7LCDLR2_RESERVED_15_9 0x0 + * Oscillator Mode Division + * PSU_DDR_PHY_DX8SL1OSC_OSCDIV 0xf - Read DQS Gating Delay - PSU_DDR_PHY_DX7LCDLR2_DQSGD 0xa + * Oscillator Enable + * PSU_DDR_PHY_DX8SL1OSC_OSCEN 0x0 - DATX8 n Local Calibrated Delay Line Register 2 - (OFFSET, MASK, VALUE) (0XFD080E88, 0xFFFFFFFFU ,0x0000000AU) - RegMask = (DDR_PHY_DX7LCDLR2_RESERVED_31_25_MASK | DDR_PHY_DX7LCDLR2_RESERVED_24_16_MASK | DDR_PHY_DX7LCDLR2_RESERVED_15_9_MASK | DDR_PHY_DX7LCDLR2_DQSGD_MASK | 0 ); + * DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Lo + * opback, and Gated Clock Control Register + * (OFFSET, MASK, VALUE) (0XFD081440, 0xFFFFFFFFU ,0x2A019FFEU) + */ + PSU_Mask_Write(DDR_PHY_DX8SL1OSC_OFFSET, 0xFFFFFFFFU, 0x2A019FFEU); +/*##################################################################### */ - RegVal = ((0x00000000U << DDR_PHY_DX7LCDLR2_RESERVED_31_25_SHIFT - | 0x00000000U << DDR_PHY_DX7LCDLR2_RESERVED_24_16_SHIFT - | 0x00000000U << DDR_PHY_DX7LCDLR2_RESERVED_15_9_SHIFT - | 0x0000000AU << DDR_PHY_DX7LCDLR2_DQSGD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX7LCDLR2_OFFSET ,0xFFFFFFFFU ,0x0000000AU); - /*############################################################################################################################ */ + /* + * Register : DX8SL1PLLCR0 @ 0XFD081444 - /*Register : DX7GTR0 @ 0XFD080EC0

+ * PLL Bypass + * PSU_DDR_PHY_DX8SL1PLLCR0_PLLBYP 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX7GTR0_RESERVED_31_24 0x0 + * PLL Reset + * PSU_DDR_PHY_DX8SL1PLLCR0_PLLRST 0x0 - DQ Write Path Latency Pipeline - PSU_DDR_PHY_DX7GTR0_WDQSL 0x0 + * PLL Power Down + * PSU_DDR_PHY_DX8SL1PLLCR0_PLLPD 0x0 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX7GTR0_RESERVED_23_20 0x0 + * Reference Stop Mode + * PSU_DDR_PHY_DX8SL1PLLCR0_RSTOPM 0x0 - Write Leveling System Latency - PSU_DDR_PHY_DX7GTR0_WLSL 0x2 + * PLL Frequency Select + * PSU_DDR_PHY_DX8SL1PLLCR0_FRQSEL 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX7GTR0_RESERVED_15_13 0x0 + * Relock Mode + * PSU_DDR_PHY_DX8SL1PLLCR0_RLOCKM 0x0 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX7GTR0_RESERVED_12_8 0x0 + * Charge Pump Proportional Current Control + * PSU_DDR_PHY_DX8SL1PLLCR0_CPPC 0x8 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX7GTR0_RESERVED_7_5 0x0 + * Charge Pump Integrating Current Control + * PSU_DDR_PHY_DX8SL1PLLCR0_CPIC 0x0 - DQS Gating System Latency - PSU_DDR_PHY_DX7GTR0_DGSL 0x0 + * Gear Shift + * PSU_DDR_PHY_DX8SL1PLLCR0_GSHIFT 0x0 - DATX8 n General Timing Register 0 - (OFFSET, MASK, VALUE) (0XFD080EC0, 0xFFFFFFFFU ,0x00020000U) - RegMask = (DDR_PHY_DX7GTR0_RESERVED_31_24_MASK | DDR_PHY_DX7GTR0_WDQSL_MASK | DDR_PHY_DX7GTR0_RESERVED_23_20_MASK | DDR_PHY_DX7GTR0_WLSL_MASK | DDR_PHY_DX7GTR0_RESERVED_15_13_MASK | DDR_PHY_DX7GTR0_RESERVED_12_8_MASK | DDR_PHY_DX7GTR0_RESERVED_7_5_MASK | DDR_PHY_DX7GTR0_DGSL_MASK | 0 ); + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL1PLLCR0_RESERVED_11_9 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX7GTR0_RESERVED_31_24_SHIFT - | 0x00000000U << DDR_PHY_DX7GTR0_WDQSL_SHIFT - | 0x00000000U << DDR_PHY_DX7GTR0_RESERVED_23_20_SHIFT - | 0x00000002U << DDR_PHY_DX7GTR0_WLSL_SHIFT - | 0x00000000U << DDR_PHY_DX7GTR0_RESERVED_15_13_SHIFT - | 0x00000000U << DDR_PHY_DX7GTR0_RESERVED_12_8_SHIFT - | 0x00000000U << DDR_PHY_DX7GTR0_RESERVED_7_5_SHIFT - | 0x00000000U << DDR_PHY_DX7GTR0_DGSL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX7GTR0_OFFSET ,0xFFFFFFFFU ,0x00020000U); - /*############################################################################################################################ */ + * Analog Test Enable (ATOEN) + * PSU_DDR_PHY_DX8SL1PLLCR0_ATOEN 0x0 - /*Register : DX8GCR0 @ 0XFD080F00

+ * Analog Test Control + * PSU_DDR_PHY_DX8SL1PLLCR0_ATC 0x0 - Calibration Bypass - PSU_DDR_PHY_DX8GCR0_CALBYP 0x0 + * Digital Test Control + * PSU_DDR_PHY_DX8SL1PLLCR0_DTC 0x0 - Master Delay Line Enable - PSU_DDR_PHY_DX8GCR0_MDLEN 0x1 + * DAXT8 0-1 PLL Control Register 0 + * (OFFSET, MASK, VALUE) (0XFD081444, 0xFFFFFFFFU ,0x01100000U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL1PLLCR0_OFFSET, + 0xFFFFFFFFU, 0x01100000U); +/*##################################################################### */ - Configurable ODT(TE) Phase Shift - PSU_DDR_PHY_DX8GCR0_CODTSHFT 0x0 + /* + * Register : DX8SL1DQSCTL @ 0XFD08145C - DQS Duty Cycle Correction - PSU_DDR_PHY_DX8GCR0_DQSDCC 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25 0x0 - Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY - PSU_DDR_PHY_DX8GCR0_RDDLY 0x8 + * Read Path Rise-to-Rise Mode + * PSU_DDR_PHY_DX8SL1DQSCTL_RRRMODE 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8GCR0_RESERVED_19_14 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22 0x0 - DQSNSE Power Down Receiver - PSU_DDR_PHY_DX8GCR0_DQSNSEPDR 0x0 + * Write Path Rise-to-Rise Mode + * PSU_DDR_PHY_DX8SL1DQSCTL_WRRMODE 0x1 - DQSSE Power Down Receiver - PSU_DDR_PHY_DX8GCR0_DQSSEPDR 0x0 + * DQS Gate Extension + * PSU_DDR_PHY_DX8SL1DQSCTL_DQSGX 0x0 - RTT On Additive Latency - PSU_DDR_PHY_DX8GCR0_RTTOAL 0x0 + * Low Power PLL Power Down + * PSU_DDR_PHY_DX8SL1DQSCTL_LPPLLPD 0x1 - RTT Output Hold - PSU_DDR_PHY_DX8GCR0_RTTOH 0x3 + * Low Power I/O Power Down + * PSU_DDR_PHY_DX8SL1DQSCTL_LPIOPD 0x1 - Configurable PDR Phase Shift - PSU_DDR_PHY_DX8GCR0_CPDRSHFT 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15 0x0 - DQSR Power Down - PSU_DDR_PHY_DX8GCR0_DQSRPD 0x0 + * QS Counter Enable + * PSU_DDR_PHY_DX8SL1DQSCTL_QSCNTEN 0x1 - DQSG Power Down Receiver - PSU_DDR_PHY_DX8GCR0_DQSGPDR 0x1 + * Unused DQ I/O Mode + * PSU_DDR_PHY_DX8SL1DQSCTL_UDQIOM 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8GCR0_RESERVED_4 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10 0x0 - DQSG On-Die Termination - PSU_DDR_PHY_DX8GCR0_DQSGODT 0x0 + * Data Slew Rate + * PSU_DDR_PHY_DX8SL1DQSCTL_DXSR 0x3 - DQSG Output Enable - PSU_DDR_PHY_DX8GCR0_DQSGOE 0x1 + * DQS_N Resistor + * PSU_DDR_PHY_DX8SL1DQSCTL_DQSNRES 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8GCR0_RESERVED_1_0 0x0 + * DQS Resistor + * PSU_DDR_PHY_DX8SL1DQSCTL_DQSRES 0x0 - DATX8 n General Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD080F00, 0xFFFFFFFFU ,0x40800624U) - RegMask = (DDR_PHY_DX8GCR0_CALBYP_MASK | DDR_PHY_DX8GCR0_MDLEN_MASK | DDR_PHY_DX8GCR0_CODTSHFT_MASK | DDR_PHY_DX8GCR0_DQSDCC_MASK | DDR_PHY_DX8GCR0_RDDLY_MASK | DDR_PHY_DX8GCR0_RESERVED_19_14_MASK | DDR_PHY_DX8GCR0_DQSNSEPDR_MASK | DDR_PHY_DX8GCR0_DQSSEPDR_MASK | DDR_PHY_DX8GCR0_RTTOAL_MASK | DDR_PHY_DX8GCR0_RTTOH_MASK | DDR_PHY_DX8GCR0_CPDRSHFT_MASK | DDR_PHY_DX8GCR0_DQSRPD_MASK | DDR_PHY_DX8GCR0_DQSGPDR_MASK | DDR_PHY_DX8GCR0_RESERVED_4_MASK | DDR_PHY_DX8GCR0_DQSGODT_MASK | DDR_PHY_DX8GCR0_DQSGOE_MASK | DDR_PHY_DX8GCR0_RESERVED_1_0_MASK | 0 ); + * DATX8 0-1 DQS Control Register + * (OFFSET, MASK, VALUE) (0XFD08145C, 0xFFFFFFFFU ,0x01264300U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL1DQSCTL_OFFSET, + 0xFFFFFFFFU, 0x01264300U); +/*##################################################################### */ - RegVal = ((0x00000000U << DDR_PHY_DX8GCR0_CALBYP_SHIFT - | 0x00000001U << DDR_PHY_DX8GCR0_MDLEN_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR0_CODTSHFT_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR0_DQSDCC_SHIFT - | 0x00000008U << DDR_PHY_DX8GCR0_RDDLY_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR0_RESERVED_19_14_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR0_DQSNSEPDR_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR0_DQSSEPDR_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR0_RTTOAL_SHIFT - | 0x00000003U << DDR_PHY_DX8GCR0_RTTOH_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR0_CPDRSHFT_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR0_DQSRPD_SHIFT - | 0x00000001U << DDR_PHY_DX8GCR0_DQSGPDR_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR0_RESERVED_4_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR0_DQSGODT_SHIFT - | 0x00000001U << DDR_PHY_DX8GCR0_DQSGOE_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR0_RESERVED_1_0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8GCR0_OFFSET ,0xFFFFFFFFU ,0x40800624U); - /*############################################################################################################################ */ + /* + * Register : DX8SL1DXCTL2 @ 0XFD08146C - /*Register : DX8GCR1 @ 0XFD080F04

+ * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24 0x0 - Enables the PDR mode for DQ[7:0] - PSU_DDR_PHY_DX8GCR1_DXPDRMODE 0x0 + * Configurable Read Data Enable + * PSU_DDR_PHY_DX8SL1DXCTL2_CRDEN 0x0 - Reserved. Returns zeroes on reads. - PSU_DDR_PHY_DX8GCR1_RESERVED_15 0x0 + * OX Extension during Post-amble + * PSU_DDR_PHY_DX8SL1DXCTL2_POSOEX 0x0 - Select the delayed or non-delayed read data strobe # - PSU_DDR_PHY_DX8GCR1_QSNSEL 0x1 + * OE Extension during Pre-amble + * PSU_DDR_PHY_DX8SL1DXCTL2_PREOEX 0x1 - Select the delayed or non-delayed read data strobe - PSU_DDR_PHY_DX8GCR1_QSSEL 0x1 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_17 0x0 - Enables Read Data Strobe in a byte lane - PSU_DDR_PHY_DX8GCR1_OEEN 0x1 + * I/O Assisted Gate Select + * PSU_DDR_PHY_DX8SL1DXCTL2_IOAG 0x0 - Enables PDR in a byte lane - PSU_DDR_PHY_DX8GCR1_PDREN 0x1 + * I/O Loopback Select + * PSU_DDR_PHY_DX8SL1DXCTL2_IOLB 0x0 - Enables ODT/TE in a byte lane - PSU_DDR_PHY_DX8GCR1_TEEN 0x1 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13 0x0 - Enables Write Data strobe in a byte lane - PSU_DDR_PHY_DX8GCR1_DSEN 0x1 + * Low Power Wakeup Threshold + * PSU_DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH 0xc - Enables DM pin in a byte lane - PSU_DDR_PHY_DX8GCR1_DMEN 0x1 + * Read Data Bus Inversion Enable + * PSU_DDR_PHY_DX8SL1DXCTL2_RDBI 0x0 - Enables DQ corresponding to each bit in a byte - PSU_DDR_PHY_DX8GCR1_DQEN 0x0 + * Write Data Bus Inversion Enable + * PSU_DDR_PHY_DX8SL1DXCTL2_WDBI 0x0 - DATX8 n General Configuration Register 1 - (OFFSET, MASK, VALUE) (0XFD080F04, 0xFFFFFFFFU ,0x00007F00U) - RegMask = (DDR_PHY_DX8GCR1_DXPDRMODE_MASK | DDR_PHY_DX8GCR1_RESERVED_15_MASK | DDR_PHY_DX8GCR1_QSNSEL_MASK | DDR_PHY_DX8GCR1_QSSEL_MASK | DDR_PHY_DX8GCR1_OEEN_MASK | DDR_PHY_DX8GCR1_PDREN_MASK | DDR_PHY_DX8GCR1_TEEN_MASK | DDR_PHY_DX8GCR1_DSEN_MASK | DDR_PHY_DX8GCR1_DMEN_MASK | DDR_PHY_DX8GCR1_DQEN_MASK | 0 ); + * PUB Read FIFO Bypass + * PSU_DDR_PHY_DX8SL1DXCTL2_PRFBYP 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX8GCR1_DXPDRMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR1_RESERVED_15_SHIFT - | 0x00000001U << DDR_PHY_DX8GCR1_QSNSEL_SHIFT - | 0x00000001U << DDR_PHY_DX8GCR1_QSSEL_SHIFT - | 0x00000001U << DDR_PHY_DX8GCR1_OEEN_SHIFT - | 0x00000001U << DDR_PHY_DX8GCR1_PDREN_SHIFT - | 0x00000001U << DDR_PHY_DX8GCR1_TEEN_SHIFT - | 0x00000001U << DDR_PHY_DX8GCR1_DSEN_SHIFT - | 0x00000001U << DDR_PHY_DX8GCR1_DMEN_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR1_DQEN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8GCR1_OFFSET ,0xFFFFFFFFU ,0x00007F00U); - /*############################################################################################################################ */ + * DATX8 Receive FIFO Read Mode + * PSU_DDR_PHY_DX8SL1DXCTL2_RDMODE 0x0 - /*Register : DX8GCR4 @ 0XFD080F10

+ * Disables the Read FIFO Reset + * PSU_DDR_PHY_DX8SL1DXCTL2_DISRST 0x0 - Byte lane VREF IOM (Used only by D4MU IOs) - PSU_DDR_PHY_DX8GCR4_RESERVED_31_29 0x0 + * Read DQS Gate I/O Loopback + * PSU_DDR_PHY_DX8SL1DXCTL2_DQSGLB 0x0 - Byte Lane VREF Pad Enable - PSU_DDR_PHY_DX8GCR4_DXREFPEN 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_0 0x0 - Byte Lane Internal VREF Enable - PSU_DDR_PHY_DX8GCR4_DXREFEEN 0x3 + * DATX8 0-1 DX Control Register 2 + * (OFFSET, MASK, VALUE) (0XFD08146C, 0xFFFFFFFFU ,0x00041800U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL1DXCTL2_OFFSET, + 0xFFFFFFFFU, 0x00041800U); +/*##################################################################### */ - Byte Lane Single-End VREF Enable - PSU_DDR_PHY_DX8GCR4_DXREFSEN 0x1 + /* + * Register : DX8SL1IOCR @ 0XFD081470 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX8GCR4_RESERVED_24 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL1IOCR_RESERVED_31 0x0 - External VREF generator REFSEL range select - PSU_DDR_PHY_DX8GCR4_DXREFESELRANGE 0x0 + * PVREF_DAC REFSEL range select + * PSU_DDR_PHY_DX8SL1IOCR_DXDACRANGE 0x7 - Byte Lane External VREF Select - PSU_DDR_PHY_DX8GCR4_DXREFESEL 0x0 + * IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring + * PSU_DDR_PHY_DX8SL1IOCR_DXVREFIOM 0x0 - Single ended VREF generator REFSEL range select - PSU_DDR_PHY_DX8GCR4_DXREFSSELRANGE 0x1 + * DX IO Mode + * PSU_DDR_PHY_DX8SL1IOCR_DXIOM 0x2 - Byte Lane Single-End VREF Select - PSU_DDR_PHY_DX8GCR4_DXREFSSEL 0x30 + * DX IO Transmitter Mode + * PSU_DDR_PHY_DX8SL1IOCR_DXTXM 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX8GCR4_RESERVED_7_6 0x0 + * DX IO Receiver Mode + * PSU_DDR_PHY_DX8SL1IOCR_DXRXM 0x0 - VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. - PSU_DDR_PHY_DX8GCR4_DXREFIEN 0xf + * DATX8 0-1 I/O Configuration Register + * (OFFSET, MASK, VALUE) (0XFD081470, 0xFFFFFFFFU ,0x70800000U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL1IOCR_OFFSET, 0xFFFFFFFFU, 0x70800000U); +/*##################################################################### */ - VRMON control for DQ IO (Single Ended) buffers of a byte lane. - PSU_DDR_PHY_DX8GCR4_DXREFIMON 0x0 + /* + * Register : DX8SL2OSC @ 0XFD081480 - DATX8 n General Configuration Register 4 - (OFFSET, MASK, VALUE) (0XFD080F10, 0xFFFFFFFFU ,0x0E00B03CU) - RegMask = (DDR_PHY_DX8GCR4_RESERVED_31_29_MASK | DDR_PHY_DX8GCR4_DXREFPEN_MASK | DDR_PHY_DX8GCR4_DXREFEEN_MASK | DDR_PHY_DX8GCR4_DXREFSEN_MASK | DDR_PHY_DX8GCR4_RESERVED_24_MASK | DDR_PHY_DX8GCR4_DXREFESELRANGE_MASK | DDR_PHY_DX8GCR4_DXREFESEL_MASK | DDR_PHY_DX8GCR4_DXREFSSELRANGE_MASK | DDR_PHY_DX8GCR4_DXREFSSEL_MASK | DDR_PHY_DX8GCR4_RESERVED_7_6_MASK | DDR_PHY_DX8GCR4_DXREFIEN_MASK | DDR_PHY_DX8GCR4_DXREFIMON_MASK | 0 ); + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL2OSC_RESERVED_31_30 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX8GCR4_RESERVED_31_29_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR4_DXREFPEN_SHIFT - | 0x00000003U << DDR_PHY_DX8GCR4_DXREFEEN_SHIFT - | 0x00000001U << DDR_PHY_DX8GCR4_DXREFSEN_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR4_RESERVED_24_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR4_DXREFESELRANGE_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR4_DXREFESEL_SHIFT - | 0x00000001U << DDR_PHY_DX8GCR4_DXREFSSELRANGE_SHIFT - | 0x00000030U << DDR_PHY_DX8GCR4_DXREFSSEL_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR4_RESERVED_7_6_SHIFT - | 0x0000000FU << DDR_PHY_DX8GCR4_DXREFIEN_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR4_DXREFIMON_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8GCR4_OFFSET ,0xFFFFFFFFU ,0x0E00B03CU); - /*############################################################################################################################ */ + * Enable Clock Gating for DX ddr_clk + * PSU_DDR_PHY_DX8SL2OSC_GATEDXRDCLK 0x2 - /*Register : DX8GCR5 @ 0XFD080F14

+ * Enable Clock Gating for DX ctl_rd_clk + * PSU_DDR_PHY_DX8SL2OSC_GATEDXDDRCLK 0x2 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX8GCR5_RESERVED_31 0x0 + * Enable Clock Gating for DX ctl_clk + * PSU_DDR_PHY_DX8SL2OSC_GATEDXCTLCLK 0x2 - Byte Lane internal VREF Select for Rank 3 - PSU_DDR_PHY_DX8GCR5_DXREFISELR3 0x9 + * Selects the level to which clocks will be stalled when clock gating is e + * nabled. + * PSU_DDR_PHY_DX8SL2OSC_CLKLEVEL 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX8GCR5_RESERVED_23 0x0 + * Loopback Mode + * PSU_DDR_PHY_DX8SL2OSC_LBMODE 0x0 - Byte Lane internal VREF Select for Rank 2 - PSU_DDR_PHY_DX8GCR5_DXREFISELR2 0x9 + * Load GSDQS LCDL with 2x the calibrated GSDQSPRD value + * PSU_DDR_PHY_DX8SL2OSC_LBGSDQS 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX8GCR5_RESERVED_15 0x0 + * Loopback DQS Gating + * PSU_DDR_PHY_DX8SL2OSC_LBGDQS 0x0 - Byte Lane internal VREF Select for Rank 1 - PSU_DDR_PHY_DX8GCR5_DXREFISELR1 0x4f + * Loopback DQS Shift + * PSU_DDR_PHY_DX8SL2OSC_LBDQSS 0x0 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX8GCR5_RESERVED_7 0x0 + * PHY High-Speed Reset + * PSU_DDR_PHY_DX8SL2OSC_PHYHRST 0x1 - Byte Lane internal VREF Select for Rank 0 - PSU_DDR_PHY_DX8GCR5_DXREFISELR0 0x4f + * PHY FIFO Reset + * PSU_DDR_PHY_DX8SL2OSC_PHYFRST 0x1 - DATX8 n General Configuration Register 5 - (OFFSET, MASK, VALUE) (0XFD080F14, 0xFFFFFFFFU ,0x09094F4FU) - RegMask = (DDR_PHY_DX8GCR5_RESERVED_31_MASK | DDR_PHY_DX8GCR5_DXREFISELR3_MASK | DDR_PHY_DX8GCR5_RESERVED_23_MASK | DDR_PHY_DX8GCR5_DXREFISELR2_MASK | DDR_PHY_DX8GCR5_RESERVED_15_MASK | DDR_PHY_DX8GCR5_DXREFISELR1_MASK | DDR_PHY_DX8GCR5_RESERVED_7_MASK | DDR_PHY_DX8GCR5_DXREFISELR0_MASK | 0 ); + * Delay Line Test Start + * PSU_DDR_PHY_DX8SL2OSC_DLTST 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX8GCR5_RESERVED_31_SHIFT - | 0x00000009U << DDR_PHY_DX8GCR5_DXREFISELR3_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR5_RESERVED_23_SHIFT - | 0x00000009U << DDR_PHY_DX8GCR5_DXREFISELR2_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR5_RESERVED_15_SHIFT - | 0x0000004FU << DDR_PHY_DX8GCR5_DXREFISELR1_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR5_RESERVED_7_SHIFT - | 0x0000004FU << DDR_PHY_DX8GCR5_DXREFISELR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8GCR5_OFFSET ,0xFFFFFFFFU ,0x09094F4FU); - /*############################################################################################################################ */ + * Delay Line Test Mode + * PSU_DDR_PHY_DX8SL2OSC_DLTMODE 0x0 - /*Register : DX8GCR6 @ 0XFD080F18

+ * Reserved. Caution, do not write to this register field. + * PSU_DDR_PHY_DX8SL2OSC_RESERVED_12_11 0x3 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX8GCR6_RESERVED_31_30 0x0 + * Oscillator Mode Write-Data Delay Line Select + * PSU_DDR_PHY_DX8SL2OSC_OSCWDDL 0x3 - DRAM DQ VREF Select for Rank3 - PSU_DDR_PHY_DX8GCR6_DXDQVREFR3 0x9 + * Reserved. Caution, do not write to this register field. + * PSU_DDR_PHY_DX8SL2OSC_RESERVED_8_7 0x3 - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX8GCR6_RESERVED_23_22 0x0 + * Oscillator Mode Write-Leveling Delay Line Select + * PSU_DDR_PHY_DX8SL2OSC_OSCWDL 0x3 - DRAM DQ VREF Select for Rank2 - PSU_DDR_PHY_DX8GCR6_DXDQVREFR2 0x9 + * Oscillator Mode Division + * PSU_DDR_PHY_DX8SL2OSC_OSCDIV 0xf - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX8GCR6_RESERVED_15_14 0x0 + * Oscillator Enable + * PSU_DDR_PHY_DX8SL2OSC_OSCEN 0x0 - DRAM DQ VREF Select for Rank1 - PSU_DDR_PHY_DX8GCR6_DXDQVREFR1 0x2b + * DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Lo + * opback, and Gated Clock Control Register + * (OFFSET, MASK, VALUE) (0XFD081480, 0xFFFFFFFFU ,0x2A019FFEU) + */ + PSU_Mask_Write(DDR_PHY_DX8SL2OSC_OFFSET, 0xFFFFFFFFU, 0x2A019FFEU); +/*##################################################################### */ - Reserved. Returns zeros on reads. - PSU_DDR_PHY_DX8GCR6_RESERVED_7_6 0x0 + /* + * Register : DX8SL2PLLCR0 @ 0XFD081484 - DRAM DQ VREF Select for Rank0 - PSU_DDR_PHY_DX8GCR6_DXDQVREFR0 0x2b + * PLL Bypass + * PSU_DDR_PHY_DX8SL2PLLCR0_PLLBYP 0x0 - DATX8 n General Configuration Register 6 - (OFFSET, MASK, VALUE) (0XFD080F18, 0xFFFFFFFFU ,0x09092B2BU) - RegMask = (DDR_PHY_DX8GCR6_RESERVED_31_30_MASK | DDR_PHY_DX8GCR6_DXDQVREFR3_MASK | DDR_PHY_DX8GCR6_RESERVED_23_22_MASK | DDR_PHY_DX8GCR6_DXDQVREFR2_MASK | DDR_PHY_DX8GCR6_RESERVED_15_14_MASK | DDR_PHY_DX8GCR6_DXDQVREFR1_MASK | DDR_PHY_DX8GCR6_RESERVED_7_6_MASK | DDR_PHY_DX8GCR6_DXDQVREFR0_MASK | 0 ); + * PLL Reset + * PSU_DDR_PHY_DX8SL2PLLCR0_PLLRST 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX8GCR6_RESERVED_31_30_SHIFT - | 0x00000009U << DDR_PHY_DX8GCR6_DXDQVREFR3_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR6_RESERVED_23_22_SHIFT - | 0x00000009U << DDR_PHY_DX8GCR6_DXDQVREFR2_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR6_RESERVED_15_14_SHIFT - | 0x0000002BU << DDR_PHY_DX8GCR6_DXDQVREFR1_SHIFT - | 0x00000000U << DDR_PHY_DX8GCR6_RESERVED_7_6_SHIFT - | 0x0000002BU << DDR_PHY_DX8GCR6_DXDQVREFR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8GCR6_OFFSET ,0xFFFFFFFFU ,0x09092B2BU); - /*############################################################################################################################ */ + * PLL Power Down + * PSU_DDR_PHY_DX8SL2PLLCR0_PLLPD 0x0 - /*Register : DX8LCDLR2 @ 0XFD080F88

+ * Reference Stop Mode + * PSU_DDR_PHY_DX8SL2PLLCR0_RSTOPM 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8LCDLR2_RESERVED_31_25 0x0 + * PLL Frequency Select + * PSU_DDR_PHY_DX8SL2PLLCR0_FRQSEL 0x1 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX8LCDLR2_RESERVED_24_16 0x0 + * Relock Mode + * PSU_DDR_PHY_DX8SL2PLLCR0_RLOCKM 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8LCDLR2_RESERVED_15_9 0x0 + * Charge Pump Proportional Current Control + * PSU_DDR_PHY_DX8SL2PLLCR0_CPPC 0x8 - Read DQS Gating Delay - PSU_DDR_PHY_DX8LCDLR2_DQSGD 0x0 + * Charge Pump Integrating Current Control + * PSU_DDR_PHY_DX8SL2PLLCR0_CPIC 0x0 - DATX8 n Local Calibrated Delay Line Register 2 - (OFFSET, MASK, VALUE) (0XFD080F88, 0xFFFFFFFFU ,0x00000000U) - RegMask = (DDR_PHY_DX8LCDLR2_RESERVED_31_25_MASK | DDR_PHY_DX8LCDLR2_RESERVED_24_16_MASK | DDR_PHY_DX8LCDLR2_RESERVED_15_9_MASK | DDR_PHY_DX8LCDLR2_DQSGD_MASK | 0 ); + * Gear Shift + * PSU_DDR_PHY_DX8SL2PLLCR0_GSHIFT 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX8LCDLR2_RESERVED_31_25_SHIFT - | 0x00000000U << DDR_PHY_DX8LCDLR2_RESERVED_24_16_SHIFT - | 0x00000000U << DDR_PHY_DX8LCDLR2_RESERVED_15_9_SHIFT - | 0x00000000U << DDR_PHY_DX8LCDLR2_DQSGD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8LCDLR2_OFFSET ,0xFFFFFFFFU ,0x00000000U); - /*############################################################################################################################ */ + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL2PLLCR0_RESERVED_11_9 0x0 - /*Register : DX8GTR0 @ 0XFD080FC0

+ * Analog Test Enable (ATOEN) + * PSU_DDR_PHY_DX8SL2PLLCR0_ATOEN 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8GTR0_RESERVED_31_24 0x0 + * Analog Test Control + * PSU_DDR_PHY_DX8SL2PLLCR0_ATC 0x0 - DQ Write Path Latency Pipeline - PSU_DDR_PHY_DX8GTR0_WDQSL 0x0 + * Digital Test Control + * PSU_DDR_PHY_DX8SL2PLLCR0_DTC 0x0 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX8GTR0_RESERVED_23_20 0x0 + * DAXT8 0-1 PLL Control Register 0 + * (OFFSET, MASK, VALUE) (0XFD081484, 0xFFFFFFFFU ,0x01100000U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL2PLLCR0_OFFSET, + 0xFFFFFFFFU, 0x01100000U); +/*##################################################################### */ - Write Leveling System Latency - PSU_DDR_PHY_DX8GTR0_WLSL 0x2 + /* + * Register : DX8SL2DQSCTL @ 0XFD08149C - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8GTR0_RESERVED_15_13 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25 0x0 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX8GTR0_RESERVED_12_8 0x0 + * Read Path Rise-to-Rise Mode + * PSU_DDR_PHY_DX8SL2DQSCTL_RRRMODE 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8GTR0_RESERVED_7_5 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22 0x0 - DQS Gating System Latency - PSU_DDR_PHY_DX8GTR0_DGSL 0x0 + * Write Path Rise-to-Rise Mode + * PSU_DDR_PHY_DX8SL2DQSCTL_WRRMODE 0x1 - DATX8 n General Timing Register 0 - (OFFSET, MASK, VALUE) (0XFD080FC0, 0xFFFFFFFFU ,0x00020000U) - RegMask = (DDR_PHY_DX8GTR0_RESERVED_31_24_MASK | DDR_PHY_DX8GTR0_WDQSL_MASK | DDR_PHY_DX8GTR0_RESERVED_23_20_MASK | DDR_PHY_DX8GTR0_WLSL_MASK | DDR_PHY_DX8GTR0_RESERVED_15_13_MASK | DDR_PHY_DX8GTR0_RESERVED_12_8_MASK | DDR_PHY_DX8GTR0_RESERVED_7_5_MASK | DDR_PHY_DX8GTR0_DGSL_MASK | 0 ); + * DQS Gate Extension + * PSU_DDR_PHY_DX8SL2DQSCTL_DQSGX 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX8GTR0_RESERVED_31_24_SHIFT - | 0x00000000U << DDR_PHY_DX8GTR0_WDQSL_SHIFT - | 0x00000000U << DDR_PHY_DX8GTR0_RESERVED_23_20_SHIFT - | 0x00000002U << DDR_PHY_DX8GTR0_WLSL_SHIFT - | 0x00000000U << DDR_PHY_DX8GTR0_RESERVED_15_13_SHIFT - | 0x00000000U << DDR_PHY_DX8GTR0_RESERVED_12_8_SHIFT - | 0x00000000U << DDR_PHY_DX8GTR0_RESERVED_7_5_SHIFT - | 0x00000000U << DDR_PHY_DX8GTR0_DGSL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8GTR0_OFFSET ,0xFFFFFFFFU ,0x00020000U); - /*############################################################################################################################ */ + * Low Power PLL Power Down + * PSU_DDR_PHY_DX8SL2DQSCTL_LPPLLPD 0x1 - /*Register : DX8SL0OSC @ 0XFD081400

+ * Low Power I/O Power Down + * PSU_DDR_PHY_DX8SL2DQSCTL_LPIOPD 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL0OSC_RESERVED_31_30 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15 0x0 - Enable Clock Gating for DX ddr_clk - PSU_DDR_PHY_DX8SL0OSC_GATEDXRDCLK 0x2 + * QS Counter Enable + * PSU_DDR_PHY_DX8SL2DQSCTL_QSCNTEN 0x1 - Enable Clock Gating for DX ctl_rd_clk - PSU_DDR_PHY_DX8SL0OSC_GATEDXDDRCLK 0x2 + * Unused DQ I/O Mode + * PSU_DDR_PHY_DX8SL2DQSCTL_UDQIOM 0x0 - Enable Clock Gating for DX ctl_clk - PSU_DDR_PHY_DX8SL0OSC_GATEDXCTLCLK 0x2 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10 0x0 - Selects the level to which clocks will be stalled when clock gating is enabled. - PSU_DDR_PHY_DX8SL0OSC_CLKLEVEL 0x0 + * Data Slew Rate + * PSU_DDR_PHY_DX8SL2DQSCTL_DXSR 0x3 - Loopback Mode - PSU_DDR_PHY_DX8SL0OSC_LBMODE 0x0 + * DQS_N Resistor + * PSU_DDR_PHY_DX8SL2DQSCTL_DQSNRES 0x0 - Load GSDQS LCDL with 2x the calibrated GSDQSPRD value - PSU_DDR_PHY_DX8SL0OSC_LBGSDQS 0x0 + * DQS Resistor + * PSU_DDR_PHY_DX8SL2DQSCTL_DQSRES 0x0 - Loopback DQS Gating - PSU_DDR_PHY_DX8SL0OSC_LBGDQS 0x0 + * DATX8 0-1 DQS Control Register + * (OFFSET, MASK, VALUE) (0XFD08149C, 0xFFFFFFFFU ,0x01264300U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL2DQSCTL_OFFSET, + 0xFFFFFFFFU, 0x01264300U); +/*##################################################################### */ - Loopback DQS Shift - PSU_DDR_PHY_DX8SL0OSC_LBDQSS 0x0 + /* + * Register : DX8SL2DXCTL2 @ 0XFD0814AC - PHY High-Speed Reset - PSU_DDR_PHY_DX8SL0OSC_PHYHRST 0x1 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24 0x0 - PHY FIFO Reset - PSU_DDR_PHY_DX8SL0OSC_PHYFRST 0x1 + * Configurable Read Data Enable + * PSU_DDR_PHY_DX8SL2DXCTL2_CRDEN 0x0 - Delay Line Test Start - PSU_DDR_PHY_DX8SL0OSC_DLTST 0x0 + * OX Extension during Post-amble + * PSU_DDR_PHY_DX8SL2DXCTL2_POSOEX 0x0 - Delay Line Test Mode - PSU_DDR_PHY_DX8SL0OSC_DLTMODE 0x0 + * OE Extension during Pre-amble + * PSU_DDR_PHY_DX8SL2DXCTL2_PREOEX 0x1 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX8SL0OSC_RESERVED_12_11 0x3 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_17 0x0 - Oscillator Mode Write-Data Delay Line Select - PSU_DDR_PHY_DX8SL0OSC_OSCWDDL 0x3 + * I/O Assisted Gate Select + * PSU_DDR_PHY_DX8SL2DXCTL2_IOAG 0x0 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX8SL0OSC_RESERVED_8_7 0x3 + * I/O Loopback Select + * PSU_DDR_PHY_DX8SL2DXCTL2_IOLB 0x0 - Oscillator Mode Write-Leveling Delay Line Select - PSU_DDR_PHY_DX8SL0OSC_OSCWDL 0x3 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13 0x0 - Oscillator Mode Division - PSU_DDR_PHY_DX8SL0OSC_OSCDIV 0xf + * Low Power Wakeup Threshold + * PSU_DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH 0xc - Oscillator Enable - PSU_DDR_PHY_DX8SL0OSC_OSCEN 0x0 + * Read Data Bus Inversion Enable + * PSU_DDR_PHY_DX8SL2DXCTL2_RDBI 0x0 - DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register - (OFFSET, MASK, VALUE) (0XFD081400, 0xFFFFFFFFU ,0x2A019FFEU) - RegMask = (DDR_PHY_DX8SL0OSC_RESERVED_31_30_MASK | DDR_PHY_DX8SL0OSC_GATEDXRDCLK_MASK | DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_MASK | DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_MASK | DDR_PHY_DX8SL0OSC_CLKLEVEL_MASK | DDR_PHY_DX8SL0OSC_LBMODE_MASK | DDR_PHY_DX8SL0OSC_LBGSDQS_MASK | DDR_PHY_DX8SL0OSC_LBGDQS_MASK | DDR_PHY_DX8SL0OSC_LBDQSS_MASK | DDR_PHY_DX8SL0OSC_PHYHRST_MASK | DDR_PHY_DX8SL0OSC_PHYFRST_MASK | DDR_PHY_DX8SL0OSC_DLTST_MASK | DDR_PHY_DX8SL0OSC_DLTMODE_MASK | DDR_PHY_DX8SL0OSC_RESERVED_12_11_MASK | DDR_PHY_DX8SL0OSC_OSCWDDL_MASK | DDR_PHY_DX8SL0OSC_RESERVED_8_7_MASK | DDR_PHY_DX8SL0OSC_OSCWDL_MASK | DDR_PHY_DX8SL0OSC_OSCDIV_MASK | DDR_PHY_DX8SL0OSC_OSCEN_MASK | 0 ); + * Write Data Bus Inversion Enable + * PSU_DDR_PHY_DX8SL2DXCTL2_WDBI 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX8SL0OSC_RESERVED_31_30_SHIFT - | 0x00000002U << DDR_PHY_DX8SL0OSC_GATEDXRDCLK_SHIFT - | 0x00000002U << DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_SHIFT - | 0x00000002U << DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0OSC_CLKLEVEL_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0OSC_LBMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0OSC_LBGSDQS_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0OSC_LBGDQS_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0OSC_LBDQSS_SHIFT - | 0x00000001U << DDR_PHY_DX8SL0OSC_PHYHRST_SHIFT - | 0x00000001U << DDR_PHY_DX8SL0OSC_PHYFRST_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0OSC_DLTST_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0OSC_DLTMODE_SHIFT - | 0x00000003U << DDR_PHY_DX8SL0OSC_RESERVED_12_11_SHIFT - | 0x00000003U << DDR_PHY_DX8SL0OSC_OSCWDDL_SHIFT - | 0x00000003U << DDR_PHY_DX8SL0OSC_RESERVED_8_7_SHIFT - | 0x00000003U << DDR_PHY_DX8SL0OSC_OSCWDL_SHIFT - | 0x0000000FU << DDR_PHY_DX8SL0OSC_OSCDIV_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0OSC_OSCEN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8SL0OSC_OFFSET ,0xFFFFFFFFU ,0x2A019FFEU); - /*############################################################################################################################ */ + * PUB Read FIFO Bypass + * PSU_DDR_PHY_DX8SL2DXCTL2_PRFBYP 0x0 - /*Register : DX8SL0DQSCTL @ 0XFD08141C

+ * DATX8 Receive FIFO Read Mode + * PSU_DDR_PHY_DX8SL2DXCTL2_RDMODE 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25 0x0 + * Disables the Read FIFO Reset + * PSU_DDR_PHY_DX8SL2DXCTL2_DISRST 0x0 - Read Path Rise-to-Rise Mode - PSU_DDR_PHY_DX8SL0DQSCTL_RRRMODE 0x1 + * Read DQS Gate I/O Loopback + * PSU_DDR_PHY_DX8SL2DXCTL2_DQSGLB 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_0 0x0 - Write Path Rise-to-Rise Mode - PSU_DDR_PHY_DX8SL0DQSCTL_WRRMODE 0x1 + * DATX8 0-1 DX Control Register 2 + * (OFFSET, MASK, VALUE) (0XFD0814AC, 0xFFFFFFFFU ,0x00041800U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL2DXCTL2_OFFSET, + 0xFFFFFFFFU, 0x00041800U); +/*##################################################################### */ - DQS Gate Extension - PSU_DDR_PHY_DX8SL0DQSCTL_DQSGX 0x0 + /* + * Register : DX8SL2IOCR @ 0XFD0814B0 - Low Power PLL Power Down - PSU_DDR_PHY_DX8SL0DQSCTL_LPPLLPD 0x1 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL2IOCR_RESERVED_31 0x0 - Low Power I/O Power Down - PSU_DDR_PHY_DX8SL0DQSCTL_LPIOPD 0x1 + * PVREF_DAC REFSEL range select + * PSU_DDR_PHY_DX8SL2IOCR_DXDACRANGE 0x7 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15 0x0 + * IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring + * PSU_DDR_PHY_DX8SL2IOCR_DXVREFIOM 0x0 - QS Counter Enable - PSU_DDR_PHY_DX8SL0DQSCTL_QSCNTEN 0x1 + * DX IO Mode + * PSU_DDR_PHY_DX8SL2IOCR_DXIOM 0x2 - Unused DQ I/O Mode - PSU_DDR_PHY_DX8SL0DQSCTL_UDQIOM 0x0 + * DX IO Transmitter Mode + * PSU_DDR_PHY_DX8SL2IOCR_DXTXM 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10 0x0 + * DX IO Receiver Mode + * PSU_DDR_PHY_DX8SL2IOCR_DXRXM 0x0 - Data Slew Rate - PSU_DDR_PHY_DX8SL0DQSCTL_DXSR 0x3 - - DQS_N Resistor - PSU_DDR_PHY_DX8SL0DQSCTL_DQSNRES 0x0 - - DQS Resistor - PSU_DDR_PHY_DX8SL0DQSCTL_DQSRES 0x0 - - DATX8 0-1 DQS Control Register - (OFFSET, MASK, VALUE) (0XFD08141C, 0xFFFFFFFFU ,0x01264300U) - RegMask = (DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_MASK | DDR_PHY_DX8SL0DQSCTL_RRRMODE_MASK | DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_MASK | DDR_PHY_DX8SL0DQSCTL_WRRMODE_MASK | DDR_PHY_DX8SL0DQSCTL_DQSGX_MASK | DDR_PHY_DX8SL0DQSCTL_LPPLLPD_MASK | DDR_PHY_DX8SL0DQSCTL_LPIOPD_MASK | DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_MASK | DDR_PHY_DX8SL0DQSCTL_QSCNTEN_MASK | DDR_PHY_DX8SL0DQSCTL_UDQIOM_MASK | DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_MASK | DDR_PHY_DX8SL0DQSCTL_DXSR_MASK | DDR_PHY_DX8SL0DQSCTL_DQSNRES_MASK | DDR_PHY_DX8SL0DQSCTL_DQSRES_MASK | 0 ); + * DATX8 0-1 I/O Configuration Register + * (OFFSET, MASK, VALUE) (0XFD0814B0, 0xFFFFFFFFU ,0x70800000U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL2IOCR_OFFSET, 0xFFFFFFFFU, 0x70800000U); +/*##################################################################### */ - RegVal = ((0x00000000U << DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_SHIFT - | 0x00000001U << DDR_PHY_DX8SL0DQSCTL_RRRMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_SHIFT - | 0x00000001U << DDR_PHY_DX8SL0DQSCTL_WRRMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0DQSCTL_DQSGX_SHIFT - | 0x00000001U << DDR_PHY_DX8SL0DQSCTL_LPPLLPD_SHIFT - | 0x00000001U << DDR_PHY_DX8SL0DQSCTL_LPIOPD_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_SHIFT - | 0x00000001U << DDR_PHY_DX8SL0DQSCTL_QSCNTEN_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0DQSCTL_UDQIOM_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_SHIFT - | 0x00000003U << DDR_PHY_DX8SL0DQSCTL_DXSR_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0DQSCTL_DQSNRES_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0DQSCTL_DQSRES_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8SL0DQSCTL_OFFSET ,0xFFFFFFFFU ,0x01264300U); - /*############################################################################################################################ */ - - /*Register : DX8SL0DXCTL2 @ 0XFD08142C

- - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24 0x0 - - Configurable Read Data Enable - PSU_DDR_PHY_DX8SL0DXCTL2_CRDEN 0x0 - - OX Extension during Post-amble - PSU_DDR_PHY_DX8SL0DXCTL2_POSOEX 0x0 - - OE Extension during Pre-amble - PSU_DDR_PHY_DX8SL0DXCTL2_PREOEX 0x1 - - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_17 0x0 - - I/O Assisted Gate Select - PSU_DDR_PHY_DX8SL0DXCTL2_IOAG 0x0 + /* + * Register : DX8SL3OSC @ 0XFD0814C0 - I/O Loopback Select - PSU_DDR_PHY_DX8SL0DXCTL2_IOLB 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL3OSC_RESERVED_31_30 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13 0x0 + * Enable Clock Gating for DX ddr_clk + * PSU_DDR_PHY_DX8SL3OSC_GATEDXRDCLK 0x2 - Low Power Wakeup Threshold - PSU_DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH 0xc + * Enable Clock Gating for DX ctl_rd_clk + * PSU_DDR_PHY_DX8SL3OSC_GATEDXDDRCLK 0x2 - Read Data Bus Inversion Enable - PSU_DDR_PHY_DX8SL0DXCTL2_RDBI 0x0 + * Enable Clock Gating for DX ctl_clk + * PSU_DDR_PHY_DX8SL3OSC_GATEDXCTLCLK 0x2 - Write Data Bus Inversion Enable - PSU_DDR_PHY_DX8SL0DXCTL2_WDBI 0x0 + * Selects the level to which clocks will be stalled when clock gating is e + * nabled. + * PSU_DDR_PHY_DX8SL3OSC_CLKLEVEL 0x0 - PUB Read FIFO Bypass - PSU_DDR_PHY_DX8SL0DXCTL2_PRFBYP 0x0 + * Loopback Mode + * PSU_DDR_PHY_DX8SL3OSC_LBMODE 0x0 - DATX8 Receive FIFO Read Mode - PSU_DDR_PHY_DX8SL0DXCTL2_RDMODE 0x0 + * Load GSDQS LCDL with 2x the calibrated GSDQSPRD value + * PSU_DDR_PHY_DX8SL3OSC_LBGSDQS 0x0 - Disables the Read FIFO Reset - PSU_DDR_PHY_DX8SL0DXCTL2_DISRST 0x0 + * Loopback DQS Gating + * PSU_DDR_PHY_DX8SL3OSC_LBGDQS 0x0 - Read DQS Gate I/O Loopback - PSU_DDR_PHY_DX8SL0DXCTL2_DQSGLB 0x0 + * Loopback DQS Shift + * PSU_DDR_PHY_DX8SL3OSC_LBDQSS 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_0 0x0 + * PHY High-Speed Reset + * PSU_DDR_PHY_DX8SL3OSC_PHYHRST 0x1 - DATX8 0-1 DX Control Register 2 - (OFFSET, MASK, VALUE) (0XFD08142C, 0xFFFFFFFFU ,0x00041800U) - RegMask = (DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_MASK | DDR_PHY_DX8SL0DXCTL2_CRDEN_MASK | DDR_PHY_DX8SL0DXCTL2_POSOEX_MASK | DDR_PHY_DX8SL0DXCTL2_PREOEX_MASK | DDR_PHY_DX8SL0DXCTL2_RESERVED_17_MASK | DDR_PHY_DX8SL0DXCTL2_IOAG_MASK | DDR_PHY_DX8SL0DXCTL2_IOLB_MASK | DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_MASK | DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_MASK | DDR_PHY_DX8SL0DXCTL2_RDBI_MASK | DDR_PHY_DX8SL0DXCTL2_WDBI_MASK | DDR_PHY_DX8SL0DXCTL2_PRFBYP_MASK | DDR_PHY_DX8SL0DXCTL2_RDMODE_MASK | DDR_PHY_DX8SL0DXCTL2_DISRST_MASK | DDR_PHY_DX8SL0DXCTL2_DQSGLB_MASK | DDR_PHY_DX8SL0DXCTL2_RESERVED_0_MASK | 0 ); + * PHY FIFO Reset + * PSU_DDR_PHY_DX8SL3OSC_PHYFRST 0x1 - RegVal = ((0x00000000U << DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_CRDEN_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_POSOEX_SHIFT - | 0x00000001U << DDR_PHY_DX8SL0DXCTL2_PREOEX_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_RESERVED_17_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_IOAG_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_IOLB_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_SHIFT - | 0x0000000CU << DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_RDBI_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_WDBI_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_PRFBYP_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_RDMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_DISRST_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_DQSGLB_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0DXCTL2_RESERVED_0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8SL0DXCTL2_OFFSET ,0xFFFFFFFFU ,0x00041800U); - /*############################################################################################################################ */ + * Delay Line Test Start + * PSU_DDR_PHY_DX8SL3OSC_DLTST 0x0 - /*Register : DX8SL0IOCR @ 0XFD081430

+ * Delay Line Test Mode + * PSU_DDR_PHY_DX8SL3OSC_DLTMODE 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL0IOCR_RESERVED_31 0x0 + * Reserved. Caution, do not write to this register field. + * PSU_DDR_PHY_DX8SL3OSC_RESERVED_12_11 0x3 - PVREF_DAC REFSEL range select - PSU_DDR_PHY_DX8SL0IOCR_DXDACRANGE 0x7 + * Oscillator Mode Write-Data Delay Line Select + * PSU_DDR_PHY_DX8SL3OSC_OSCWDDL 0x3 - IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring - PSU_DDR_PHY_DX8SL0IOCR_DXVREFIOM 0x0 + * Reserved. Caution, do not write to this register field. + * PSU_DDR_PHY_DX8SL3OSC_RESERVED_8_7 0x3 - DX IO Mode - PSU_DDR_PHY_DX8SL0IOCR_DXIOM 0x2 + * Oscillator Mode Write-Leveling Delay Line Select + * PSU_DDR_PHY_DX8SL3OSC_OSCWDL 0x3 - DX IO Transmitter Mode - PSU_DDR_PHY_DX8SL0IOCR_DXTXM 0x0 + * Oscillator Mode Division + * PSU_DDR_PHY_DX8SL3OSC_OSCDIV 0xf - DX IO Receiver Mode - PSU_DDR_PHY_DX8SL0IOCR_DXRXM 0x0 + * Oscillator Enable + * PSU_DDR_PHY_DX8SL3OSC_OSCEN 0x0 - DATX8 0-1 I/O Configuration Register - (OFFSET, MASK, VALUE) (0XFD081430, 0xFFFFFFFFU ,0x70800000U) - RegMask = (DDR_PHY_DX8SL0IOCR_RESERVED_31_MASK | DDR_PHY_DX8SL0IOCR_DXDACRANGE_MASK | DDR_PHY_DX8SL0IOCR_DXVREFIOM_MASK | DDR_PHY_DX8SL0IOCR_DXIOM_MASK | DDR_PHY_DX8SL0IOCR_DXTXM_MASK | DDR_PHY_DX8SL0IOCR_DXRXM_MASK | 0 ); + * DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Lo + * opback, and Gated Clock Control Register + * (OFFSET, MASK, VALUE) (0XFD0814C0, 0xFFFFFFFFU ,0x2A019FFEU) + */ + PSU_Mask_Write(DDR_PHY_DX8SL3OSC_OFFSET, 0xFFFFFFFFU, 0x2A019FFEU); +/*##################################################################### */ - RegVal = ((0x00000000U << DDR_PHY_DX8SL0IOCR_RESERVED_31_SHIFT - | 0x00000007U << DDR_PHY_DX8SL0IOCR_DXDACRANGE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0IOCR_DXVREFIOM_SHIFT - | 0x00000002U << DDR_PHY_DX8SL0IOCR_DXIOM_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0IOCR_DXTXM_SHIFT - | 0x00000000U << DDR_PHY_DX8SL0IOCR_DXRXM_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8SL0IOCR_OFFSET ,0xFFFFFFFFU ,0x70800000U); - /*############################################################################################################################ */ + /* + * Register : DX8SL3PLLCR0 @ 0XFD0814C4 - /*Register : DX8SL1OSC @ 0XFD081440

+ * PLL Bypass + * PSU_DDR_PHY_DX8SL3PLLCR0_PLLBYP 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL1OSC_RESERVED_31_30 0x0 + * PLL Reset + * PSU_DDR_PHY_DX8SL3PLLCR0_PLLRST 0x0 - Enable Clock Gating for DX ddr_clk - PSU_DDR_PHY_DX8SL1OSC_GATEDXRDCLK 0x2 + * PLL Power Down + * PSU_DDR_PHY_DX8SL3PLLCR0_PLLPD 0x0 - Enable Clock Gating for DX ctl_rd_clk - PSU_DDR_PHY_DX8SL1OSC_GATEDXDDRCLK 0x2 + * Reference Stop Mode + * PSU_DDR_PHY_DX8SL3PLLCR0_RSTOPM 0x0 - Enable Clock Gating for DX ctl_clk - PSU_DDR_PHY_DX8SL1OSC_GATEDXCTLCLK 0x2 + * PLL Frequency Select + * PSU_DDR_PHY_DX8SL3PLLCR0_FRQSEL 0x1 - Selects the level to which clocks will be stalled when clock gating is enabled. - PSU_DDR_PHY_DX8SL1OSC_CLKLEVEL 0x0 + * Relock Mode + * PSU_DDR_PHY_DX8SL3PLLCR0_RLOCKM 0x0 - Loopback Mode - PSU_DDR_PHY_DX8SL1OSC_LBMODE 0x0 + * Charge Pump Proportional Current Control + * PSU_DDR_PHY_DX8SL3PLLCR0_CPPC 0x8 - Load GSDQS LCDL with 2x the calibrated GSDQSPRD value - PSU_DDR_PHY_DX8SL1OSC_LBGSDQS 0x0 + * Charge Pump Integrating Current Control + * PSU_DDR_PHY_DX8SL3PLLCR0_CPIC 0x0 - Loopback DQS Gating - PSU_DDR_PHY_DX8SL1OSC_LBGDQS 0x0 + * Gear Shift + * PSU_DDR_PHY_DX8SL3PLLCR0_GSHIFT 0x0 - Loopback DQS Shift - PSU_DDR_PHY_DX8SL1OSC_LBDQSS 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL3PLLCR0_RESERVED_11_9 0x0 - PHY High-Speed Reset - PSU_DDR_PHY_DX8SL1OSC_PHYHRST 0x1 + * Analog Test Enable (ATOEN) + * PSU_DDR_PHY_DX8SL3PLLCR0_ATOEN 0x0 - PHY FIFO Reset - PSU_DDR_PHY_DX8SL1OSC_PHYFRST 0x1 + * Analog Test Control + * PSU_DDR_PHY_DX8SL3PLLCR0_ATC 0x0 - Delay Line Test Start - PSU_DDR_PHY_DX8SL1OSC_DLTST 0x0 + * Digital Test Control + * PSU_DDR_PHY_DX8SL3PLLCR0_DTC 0x0 - Delay Line Test Mode - PSU_DDR_PHY_DX8SL1OSC_DLTMODE 0x0 + * DAXT8 0-1 PLL Control Register 0 + * (OFFSET, MASK, VALUE) (0XFD0814C4, 0xFFFFFFFFU ,0x01100000U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL3PLLCR0_OFFSET, + 0xFFFFFFFFU, 0x01100000U); +/*##################################################################### */ - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX8SL1OSC_RESERVED_12_11 0x3 - - Oscillator Mode Write-Data Delay Line Select - PSU_DDR_PHY_DX8SL1OSC_OSCWDDL 0x3 - - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX8SL1OSC_RESERVED_8_7 0x3 - - Oscillator Mode Write-Leveling Delay Line Select - PSU_DDR_PHY_DX8SL1OSC_OSCWDL 0x3 - - Oscillator Mode Division - PSU_DDR_PHY_DX8SL1OSC_OSCDIV 0xf + /* + * Register : DX8SL3DQSCTL @ 0XFD0814DC - Oscillator Enable - PSU_DDR_PHY_DX8SL1OSC_OSCEN 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25 0x0 - DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register - (OFFSET, MASK, VALUE) (0XFD081440, 0xFFFFFFFFU ,0x2A019FFEU) - RegMask = (DDR_PHY_DX8SL1OSC_RESERVED_31_30_MASK | DDR_PHY_DX8SL1OSC_GATEDXRDCLK_MASK | DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_MASK | DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_MASK | DDR_PHY_DX8SL1OSC_CLKLEVEL_MASK | DDR_PHY_DX8SL1OSC_LBMODE_MASK | DDR_PHY_DX8SL1OSC_LBGSDQS_MASK | DDR_PHY_DX8SL1OSC_LBGDQS_MASK | DDR_PHY_DX8SL1OSC_LBDQSS_MASK | DDR_PHY_DX8SL1OSC_PHYHRST_MASK | DDR_PHY_DX8SL1OSC_PHYFRST_MASK | DDR_PHY_DX8SL1OSC_DLTST_MASK | DDR_PHY_DX8SL1OSC_DLTMODE_MASK | DDR_PHY_DX8SL1OSC_RESERVED_12_11_MASK | DDR_PHY_DX8SL1OSC_OSCWDDL_MASK | DDR_PHY_DX8SL1OSC_RESERVED_8_7_MASK | DDR_PHY_DX8SL1OSC_OSCWDL_MASK | DDR_PHY_DX8SL1OSC_OSCDIV_MASK | DDR_PHY_DX8SL1OSC_OSCEN_MASK | 0 ); + * Read Path Rise-to-Rise Mode + * PSU_DDR_PHY_DX8SL3DQSCTL_RRRMODE 0x1 - RegVal = ((0x00000000U << DDR_PHY_DX8SL1OSC_RESERVED_31_30_SHIFT - | 0x00000002U << DDR_PHY_DX8SL1OSC_GATEDXRDCLK_SHIFT - | 0x00000002U << DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_SHIFT - | 0x00000002U << DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1OSC_CLKLEVEL_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1OSC_LBMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1OSC_LBGSDQS_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1OSC_LBGDQS_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1OSC_LBDQSS_SHIFT - | 0x00000001U << DDR_PHY_DX8SL1OSC_PHYHRST_SHIFT - | 0x00000001U << DDR_PHY_DX8SL1OSC_PHYFRST_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1OSC_DLTST_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1OSC_DLTMODE_SHIFT - | 0x00000003U << DDR_PHY_DX8SL1OSC_RESERVED_12_11_SHIFT - | 0x00000003U << DDR_PHY_DX8SL1OSC_OSCWDDL_SHIFT - | 0x00000003U << DDR_PHY_DX8SL1OSC_RESERVED_8_7_SHIFT - | 0x00000003U << DDR_PHY_DX8SL1OSC_OSCWDL_SHIFT - | 0x0000000FU << DDR_PHY_DX8SL1OSC_OSCDIV_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1OSC_OSCEN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8SL1OSC_OFFSET ,0xFFFFFFFFU ,0x2A019FFEU); - /*############################################################################################################################ */ + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22 0x0 - /*Register : DX8SL1DQSCTL @ 0XFD08145C

+ * Write Path Rise-to-Rise Mode + * PSU_DDR_PHY_DX8SL3DQSCTL_WRRMODE 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25 0x0 + * DQS Gate Extension + * PSU_DDR_PHY_DX8SL3DQSCTL_DQSGX 0x0 - Read Path Rise-to-Rise Mode - PSU_DDR_PHY_DX8SL1DQSCTL_RRRMODE 0x1 + * Low Power PLL Power Down + * PSU_DDR_PHY_DX8SL3DQSCTL_LPPLLPD 0x1 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22 0x0 + * Low Power I/O Power Down + * PSU_DDR_PHY_DX8SL3DQSCTL_LPIOPD 0x1 - Write Path Rise-to-Rise Mode - PSU_DDR_PHY_DX8SL1DQSCTL_WRRMODE 0x1 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15 0x0 - DQS Gate Extension - PSU_DDR_PHY_DX8SL1DQSCTL_DQSGX 0x0 + * QS Counter Enable + * PSU_DDR_PHY_DX8SL3DQSCTL_QSCNTEN 0x1 - Low Power PLL Power Down - PSU_DDR_PHY_DX8SL1DQSCTL_LPPLLPD 0x1 + * Unused DQ I/O Mode + * PSU_DDR_PHY_DX8SL3DQSCTL_UDQIOM 0x0 - Low Power I/O Power Down - PSU_DDR_PHY_DX8SL1DQSCTL_LPIOPD 0x1 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15 0x0 + * Data Slew Rate + * PSU_DDR_PHY_DX8SL3DQSCTL_DXSR 0x3 - QS Counter Enable - PSU_DDR_PHY_DX8SL1DQSCTL_QSCNTEN 0x1 + * DQS_N Resistor + * PSU_DDR_PHY_DX8SL3DQSCTL_DQSNRES 0x0 - Unused DQ I/O Mode - PSU_DDR_PHY_DX8SL1DQSCTL_UDQIOM 0x0 + * DQS Resistor + * PSU_DDR_PHY_DX8SL3DQSCTL_DQSRES 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10 0x0 + * DATX8 0-1 DQS Control Register + * (OFFSET, MASK, VALUE) (0XFD0814DC, 0xFFFFFFFFU ,0x01264300U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL3DQSCTL_OFFSET, + 0xFFFFFFFFU, 0x01264300U); +/*##################################################################### */ - Data Slew Rate - PSU_DDR_PHY_DX8SL1DQSCTL_DXSR 0x3 - - DQS_N Resistor - PSU_DDR_PHY_DX8SL1DQSCTL_DQSNRES 0x0 - - DQS Resistor - PSU_DDR_PHY_DX8SL1DQSCTL_DQSRES 0x0 - - DATX8 0-1 DQS Control Register - (OFFSET, MASK, VALUE) (0XFD08145C, 0xFFFFFFFFU ,0x01264300U) - RegMask = (DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_MASK | DDR_PHY_DX8SL1DQSCTL_RRRMODE_MASK | DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_MASK | DDR_PHY_DX8SL1DQSCTL_WRRMODE_MASK | DDR_PHY_DX8SL1DQSCTL_DQSGX_MASK | DDR_PHY_DX8SL1DQSCTL_LPPLLPD_MASK | DDR_PHY_DX8SL1DQSCTL_LPIOPD_MASK | DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_MASK | DDR_PHY_DX8SL1DQSCTL_QSCNTEN_MASK | DDR_PHY_DX8SL1DQSCTL_UDQIOM_MASK | DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_MASK | DDR_PHY_DX8SL1DQSCTL_DXSR_MASK | DDR_PHY_DX8SL1DQSCTL_DQSNRES_MASK | DDR_PHY_DX8SL1DQSCTL_DQSRES_MASK | 0 ); + /* + * Register : DX8SL3DXCTL2 @ 0XFD0814EC - RegVal = ((0x00000000U << DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_SHIFT - | 0x00000001U << DDR_PHY_DX8SL1DQSCTL_RRRMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_SHIFT - | 0x00000001U << DDR_PHY_DX8SL1DQSCTL_WRRMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1DQSCTL_DQSGX_SHIFT - | 0x00000001U << DDR_PHY_DX8SL1DQSCTL_LPPLLPD_SHIFT - | 0x00000001U << DDR_PHY_DX8SL1DQSCTL_LPIOPD_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_SHIFT - | 0x00000001U << DDR_PHY_DX8SL1DQSCTL_QSCNTEN_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1DQSCTL_UDQIOM_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_SHIFT - | 0x00000003U << DDR_PHY_DX8SL1DQSCTL_DXSR_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1DQSCTL_DQSNRES_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1DQSCTL_DQSRES_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8SL1DQSCTL_OFFSET ,0xFFFFFFFFU ,0x01264300U); - /*############################################################################################################################ */ - - /*Register : DX8SL1DXCTL2 @ 0XFD08146C

- - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24 0x0 - - Configurable Read Data Enable - PSU_DDR_PHY_DX8SL1DXCTL2_CRDEN 0x0 - - OX Extension during Post-amble - PSU_DDR_PHY_DX8SL1DXCTL2_POSOEX 0x0 - - OE Extension during Pre-amble - PSU_DDR_PHY_DX8SL1DXCTL2_PREOEX 0x1 - - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_17 0x0 - - I/O Assisted Gate Select - PSU_DDR_PHY_DX8SL1DXCTL2_IOAG 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24 0x0 - I/O Loopback Select - PSU_DDR_PHY_DX8SL1DXCTL2_IOLB 0x0 + * Configurable Read Data Enable + * PSU_DDR_PHY_DX8SL3DXCTL2_CRDEN 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13 0x0 + * OX Extension during Post-amble + * PSU_DDR_PHY_DX8SL3DXCTL2_POSOEX 0x0 - Low Power Wakeup Threshold - PSU_DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH 0xc + * OE Extension during Pre-amble + * PSU_DDR_PHY_DX8SL3DXCTL2_PREOEX 0x1 - Read Data Bus Inversion Enable - PSU_DDR_PHY_DX8SL1DXCTL2_RDBI 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_17 0x0 - Write Data Bus Inversion Enable - PSU_DDR_PHY_DX8SL1DXCTL2_WDBI 0x0 + * I/O Assisted Gate Select + * PSU_DDR_PHY_DX8SL3DXCTL2_IOAG 0x0 - PUB Read FIFO Bypass - PSU_DDR_PHY_DX8SL1DXCTL2_PRFBYP 0x0 + * I/O Loopback Select + * PSU_DDR_PHY_DX8SL3DXCTL2_IOLB 0x0 - DATX8 Receive FIFO Read Mode - PSU_DDR_PHY_DX8SL1DXCTL2_RDMODE 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13 0x0 - Disables the Read FIFO Reset - PSU_DDR_PHY_DX8SL1DXCTL2_DISRST 0x0 + * Low Power Wakeup Threshold + * PSU_DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH 0xc - Read DQS Gate I/O Loopback - PSU_DDR_PHY_DX8SL1DXCTL2_DQSGLB 0x0 + * Read Data Bus Inversion Enable + * PSU_DDR_PHY_DX8SL3DXCTL2_RDBI 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_0 0x0 + * Write Data Bus Inversion Enable + * PSU_DDR_PHY_DX8SL3DXCTL2_WDBI 0x0 - DATX8 0-1 DX Control Register 2 - (OFFSET, MASK, VALUE) (0XFD08146C, 0xFFFFFFFFU ,0x00041800U) - RegMask = (DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_MASK | DDR_PHY_DX8SL1DXCTL2_CRDEN_MASK | DDR_PHY_DX8SL1DXCTL2_POSOEX_MASK | DDR_PHY_DX8SL1DXCTL2_PREOEX_MASK | DDR_PHY_DX8SL1DXCTL2_RESERVED_17_MASK | DDR_PHY_DX8SL1DXCTL2_IOAG_MASK | DDR_PHY_DX8SL1DXCTL2_IOLB_MASK | DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_MASK | DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_MASK | DDR_PHY_DX8SL1DXCTL2_RDBI_MASK | DDR_PHY_DX8SL1DXCTL2_WDBI_MASK | DDR_PHY_DX8SL1DXCTL2_PRFBYP_MASK | DDR_PHY_DX8SL1DXCTL2_RDMODE_MASK | DDR_PHY_DX8SL1DXCTL2_DISRST_MASK | DDR_PHY_DX8SL1DXCTL2_DQSGLB_MASK | DDR_PHY_DX8SL1DXCTL2_RESERVED_0_MASK | 0 ); + * PUB Read FIFO Bypass + * PSU_DDR_PHY_DX8SL3DXCTL2_PRFBYP 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_CRDEN_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_POSOEX_SHIFT - | 0x00000001U << DDR_PHY_DX8SL1DXCTL2_PREOEX_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_RESERVED_17_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_IOAG_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_IOLB_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_SHIFT - | 0x0000000CU << DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_RDBI_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_WDBI_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_PRFBYP_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_RDMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_DISRST_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_DQSGLB_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1DXCTL2_RESERVED_0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8SL1DXCTL2_OFFSET ,0xFFFFFFFFU ,0x00041800U); - /*############################################################################################################################ */ + * DATX8 Receive FIFO Read Mode + * PSU_DDR_PHY_DX8SL3DXCTL2_RDMODE 0x0 - /*Register : DX8SL1IOCR @ 0XFD081470

+ * Disables the Read FIFO Reset + * PSU_DDR_PHY_DX8SL3DXCTL2_DISRST 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL1IOCR_RESERVED_31 0x0 + * Read DQS Gate I/O Loopback + * PSU_DDR_PHY_DX8SL3DXCTL2_DQSGLB 0x0 - PVREF_DAC REFSEL range select - PSU_DDR_PHY_DX8SL1IOCR_DXDACRANGE 0x7 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_0 0x0 - IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring - PSU_DDR_PHY_DX8SL1IOCR_DXVREFIOM 0x0 + * DATX8 0-1 DX Control Register 2 + * (OFFSET, MASK, VALUE) (0XFD0814EC, 0xFFFFFFFFU ,0x00041800U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL3DXCTL2_OFFSET, + 0xFFFFFFFFU, 0x00041800U); +/*##################################################################### */ - DX IO Mode - PSU_DDR_PHY_DX8SL1IOCR_DXIOM 0x2 + /* + * Register : DX8SL3IOCR @ 0XFD0814F0 - DX IO Transmitter Mode - PSU_DDR_PHY_DX8SL1IOCR_DXTXM 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL3IOCR_RESERVED_31 0x0 - DX IO Receiver Mode - PSU_DDR_PHY_DX8SL1IOCR_DXRXM 0x0 + * PVREF_DAC REFSEL range select + * PSU_DDR_PHY_DX8SL3IOCR_DXDACRANGE 0x7 - DATX8 0-1 I/O Configuration Register - (OFFSET, MASK, VALUE) (0XFD081470, 0xFFFFFFFFU ,0x70800000U) - RegMask = (DDR_PHY_DX8SL1IOCR_RESERVED_31_MASK | DDR_PHY_DX8SL1IOCR_DXDACRANGE_MASK | DDR_PHY_DX8SL1IOCR_DXVREFIOM_MASK | DDR_PHY_DX8SL1IOCR_DXIOM_MASK | DDR_PHY_DX8SL1IOCR_DXTXM_MASK | DDR_PHY_DX8SL1IOCR_DXRXM_MASK | 0 ); + * IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring + * PSU_DDR_PHY_DX8SL3IOCR_DXVREFIOM 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX8SL1IOCR_RESERVED_31_SHIFT - | 0x00000007U << DDR_PHY_DX8SL1IOCR_DXDACRANGE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1IOCR_DXVREFIOM_SHIFT - | 0x00000002U << DDR_PHY_DX8SL1IOCR_DXIOM_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1IOCR_DXTXM_SHIFT - | 0x00000000U << DDR_PHY_DX8SL1IOCR_DXRXM_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8SL1IOCR_OFFSET ,0xFFFFFFFFU ,0x70800000U); - /*############################################################################################################################ */ + * DX IO Mode + * PSU_DDR_PHY_DX8SL3IOCR_DXIOM 0x2 - /*Register : DX8SL2OSC @ 0XFD081480

+ * DX IO Transmitter Mode + * PSU_DDR_PHY_DX8SL3IOCR_DXTXM 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL2OSC_RESERVED_31_30 0x0 + * DX IO Receiver Mode + * PSU_DDR_PHY_DX8SL3IOCR_DXRXM 0x0 - Enable Clock Gating for DX ddr_clk - PSU_DDR_PHY_DX8SL2OSC_GATEDXRDCLK 0x2 + * DATX8 0-1 I/O Configuration Register + * (OFFSET, MASK, VALUE) (0XFD0814F0, 0xFFFFFFFFU ,0x70800000U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL3IOCR_OFFSET, 0xFFFFFFFFU, 0x70800000U); +/*##################################################################### */ - Enable Clock Gating for DX ctl_rd_clk - PSU_DDR_PHY_DX8SL2OSC_GATEDXDDRCLK 0x2 + /* + * Register : DX8SL4OSC @ 0XFD081500 - Enable Clock Gating for DX ctl_clk - PSU_DDR_PHY_DX8SL2OSC_GATEDXCTLCLK 0x2 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL4OSC_RESERVED_31_30 0x0 - Selects the level to which clocks will be stalled when clock gating is enabled. - PSU_DDR_PHY_DX8SL2OSC_CLKLEVEL 0x0 + * Enable Clock Gating for DX ddr_clk + * PSU_DDR_PHY_DX8SL4OSC_GATEDXRDCLK 0x2 - Loopback Mode - PSU_DDR_PHY_DX8SL2OSC_LBMODE 0x0 + * Enable Clock Gating for DX ctl_rd_clk + * PSU_DDR_PHY_DX8SL4OSC_GATEDXDDRCLK 0x2 - Load GSDQS LCDL with 2x the calibrated GSDQSPRD value - PSU_DDR_PHY_DX8SL2OSC_LBGSDQS 0x0 + * Enable Clock Gating for DX ctl_clk + * PSU_DDR_PHY_DX8SL4OSC_GATEDXCTLCLK 0x2 - Loopback DQS Gating - PSU_DDR_PHY_DX8SL2OSC_LBGDQS 0x0 + * Selects the level to which clocks will be stalled when clock gating is e + * nabled. + * PSU_DDR_PHY_DX8SL4OSC_CLKLEVEL 0x0 - Loopback DQS Shift - PSU_DDR_PHY_DX8SL2OSC_LBDQSS 0x0 + * Loopback Mode + * PSU_DDR_PHY_DX8SL4OSC_LBMODE 0x0 - PHY High-Speed Reset - PSU_DDR_PHY_DX8SL2OSC_PHYHRST 0x1 + * Load GSDQS LCDL with 2x the calibrated GSDQSPRD value + * PSU_DDR_PHY_DX8SL4OSC_LBGSDQS 0x0 - PHY FIFO Reset - PSU_DDR_PHY_DX8SL2OSC_PHYFRST 0x1 + * Loopback DQS Gating + * PSU_DDR_PHY_DX8SL4OSC_LBGDQS 0x0 - Delay Line Test Start - PSU_DDR_PHY_DX8SL2OSC_DLTST 0x0 + * Loopback DQS Shift + * PSU_DDR_PHY_DX8SL4OSC_LBDQSS 0x0 - Delay Line Test Mode - PSU_DDR_PHY_DX8SL2OSC_DLTMODE 0x0 + * PHY High-Speed Reset + * PSU_DDR_PHY_DX8SL4OSC_PHYHRST 0x1 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX8SL2OSC_RESERVED_12_11 0x3 - - Oscillator Mode Write-Data Delay Line Select - PSU_DDR_PHY_DX8SL2OSC_OSCWDDL 0x3 - - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX8SL2OSC_RESERVED_8_7 0x3 - - Oscillator Mode Write-Leveling Delay Line Select - PSU_DDR_PHY_DX8SL2OSC_OSCWDL 0x3 - - Oscillator Mode Division - PSU_DDR_PHY_DX8SL2OSC_OSCDIV 0xf + * PHY FIFO Reset + * PSU_DDR_PHY_DX8SL4OSC_PHYFRST 0x1 - Oscillator Enable - PSU_DDR_PHY_DX8SL2OSC_OSCEN 0x0 + * Delay Line Test Start + * PSU_DDR_PHY_DX8SL4OSC_DLTST 0x0 - DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register - (OFFSET, MASK, VALUE) (0XFD081480, 0xFFFFFFFFU ,0x2A019FFEU) - RegMask = (DDR_PHY_DX8SL2OSC_RESERVED_31_30_MASK | DDR_PHY_DX8SL2OSC_GATEDXRDCLK_MASK | DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_MASK | DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_MASK | DDR_PHY_DX8SL2OSC_CLKLEVEL_MASK | DDR_PHY_DX8SL2OSC_LBMODE_MASK | DDR_PHY_DX8SL2OSC_LBGSDQS_MASK | DDR_PHY_DX8SL2OSC_LBGDQS_MASK | DDR_PHY_DX8SL2OSC_LBDQSS_MASK | DDR_PHY_DX8SL2OSC_PHYHRST_MASK | DDR_PHY_DX8SL2OSC_PHYFRST_MASK | DDR_PHY_DX8SL2OSC_DLTST_MASK | DDR_PHY_DX8SL2OSC_DLTMODE_MASK | DDR_PHY_DX8SL2OSC_RESERVED_12_11_MASK | DDR_PHY_DX8SL2OSC_OSCWDDL_MASK | DDR_PHY_DX8SL2OSC_RESERVED_8_7_MASK | DDR_PHY_DX8SL2OSC_OSCWDL_MASK | DDR_PHY_DX8SL2OSC_OSCDIV_MASK | DDR_PHY_DX8SL2OSC_OSCEN_MASK | 0 ); + * Delay Line Test Mode + * PSU_DDR_PHY_DX8SL4OSC_DLTMODE 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX8SL2OSC_RESERVED_31_30_SHIFT - | 0x00000002U << DDR_PHY_DX8SL2OSC_GATEDXRDCLK_SHIFT - | 0x00000002U << DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_SHIFT - | 0x00000002U << DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2OSC_CLKLEVEL_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2OSC_LBMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2OSC_LBGSDQS_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2OSC_LBGDQS_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2OSC_LBDQSS_SHIFT - | 0x00000001U << DDR_PHY_DX8SL2OSC_PHYHRST_SHIFT - | 0x00000001U << DDR_PHY_DX8SL2OSC_PHYFRST_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2OSC_DLTST_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2OSC_DLTMODE_SHIFT - | 0x00000003U << DDR_PHY_DX8SL2OSC_RESERVED_12_11_SHIFT - | 0x00000003U << DDR_PHY_DX8SL2OSC_OSCWDDL_SHIFT - | 0x00000003U << DDR_PHY_DX8SL2OSC_RESERVED_8_7_SHIFT - | 0x00000003U << DDR_PHY_DX8SL2OSC_OSCWDL_SHIFT - | 0x0000000FU << DDR_PHY_DX8SL2OSC_OSCDIV_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2OSC_OSCEN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8SL2OSC_OFFSET ,0xFFFFFFFFU ,0x2A019FFEU); - /*############################################################################################################################ */ + * Reserved. Caution, do not write to this register field. + * PSU_DDR_PHY_DX8SL4OSC_RESERVED_12_11 0x3 - /*Register : DX8SL2DQSCTL @ 0XFD08149C

+ * Oscillator Mode Write-Data Delay Line Select + * PSU_DDR_PHY_DX8SL4OSC_OSCWDDL 0x3 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25 0x0 + * Reserved. Caution, do not write to this register field. + * PSU_DDR_PHY_DX8SL4OSC_RESERVED_8_7 0x3 - Read Path Rise-to-Rise Mode - PSU_DDR_PHY_DX8SL2DQSCTL_RRRMODE 0x1 + * Oscillator Mode Write-Leveling Delay Line Select + * PSU_DDR_PHY_DX8SL4OSC_OSCWDL 0x3 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22 0x0 + * Oscillator Mode Division + * PSU_DDR_PHY_DX8SL4OSC_OSCDIV 0xf - Write Path Rise-to-Rise Mode - PSU_DDR_PHY_DX8SL2DQSCTL_WRRMODE 0x1 + * Oscillator Enable + * PSU_DDR_PHY_DX8SL4OSC_OSCEN 0x0 - DQS Gate Extension - PSU_DDR_PHY_DX8SL2DQSCTL_DQSGX 0x0 + * DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Lo + * opback, and Gated Clock Control Register + * (OFFSET, MASK, VALUE) (0XFD081500, 0xFFFFFFFFU ,0x2A019FFEU) + */ + PSU_Mask_Write(DDR_PHY_DX8SL4OSC_OFFSET, 0xFFFFFFFFU, 0x2A019FFEU); +/*##################################################################### */ - Low Power PLL Power Down - PSU_DDR_PHY_DX8SL2DQSCTL_LPPLLPD 0x1 + /* + * Register : DX8SL4PLLCR0 @ 0XFD081504 - Low Power I/O Power Down - PSU_DDR_PHY_DX8SL2DQSCTL_LPIOPD 0x1 + * PLL Bypass + * PSU_DDR_PHY_DX8SL4PLLCR0_PLLBYP 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15 0x0 + * PLL Reset + * PSU_DDR_PHY_DX8SL4PLLCR0_PLLRST 0x0 - QS Counter Enable - PSU_DDR_PHY_DX8SL2DQSCTL_QSCNTEN 0x1 + * PLL Power Down + * PSU_DDR_PHY_DX8SL4PLLCR0_PLLPD 0x0 - Unused DQ I/O Mode - PSU_DDR_PHY_DX8SL2DQSCTL_UDQIOM 0x0 + * Reference Stop Mode + * PSU_DDR_PHY_DX8SL4PLLCR0_RSTOPM 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10 0x0 + * PLL Frequency Select + * PSU_DDR_PHY_DX8SL4PLLCR0_FRQSEL 0x1 - Data Slew Rate - PSU_DDR_PHY_DX8SL2DQSCTL_DXSR 0x3 - - DQS_N Resistor - PSU_DDR_PHY_DX8SL2DQSCTL_DQSNRES 0x0 - - DQS Resistor - PSU_DDR_PHY_DX8SL2DQSCTL_DQSRES 0x0 - - DATX8 0-1 DQS Control Register - (OFFSET, MASK, VALUE) (0XFD08149C, 0xFFFFFFFFU ,0x01264300U) - RegMask = (DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_MASK | DDR_PHY_DX8SL2DQSCTL_RRRMODE_MASK | DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_MASK | DDR_PHY_DX8SL2DQSCTL_WRRMODE_MASK | DDR_PHY_DX8SL2DQSCTL_DQSGX_MASK | DDR_PHY_DX8SL2DQSCTL_LPPLLPD_MASK | DDR_PHY_DX8SL2DQSCTL_LPIOPD_MASK | DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_MASK | DDR_PHY_DX8SL2DQSCTL_QSCNTEN_MASK | DDR_PHY_DX8SL2DQSCTL_UDQIOM_MASK | DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_MASK | DDR_PHY_DX8SL2DQSCTL_DXSR_MASK | DDR_PHY_DX8SL2DQSCTL_DQSNRES_MASK | DDR_PHY_DX8SL2DQSCTL_DQSRES_MASK | 0 ); + * Relock Mode + * PSU_DDR_PHY_DX8SL4PLLCR0_RLOCKM 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_SHIFT - | 0x00000001U << DDR_PHY_DX8SL2DQSCTL_RRRMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_SHIFT - | 0x00000001U << DDR_PHY_DX8SL2DQSCTL_WRRMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2DQSCTL_DQSGX_SHIFT - | 0x00000001U << DDR_PHY_DX8SL2DQSCTL_LPPLLPD_SHIFT - | 0x00000001U << DDR_PHY_DX8SL2DQSCTL_LPIOPD_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_SHIFT - | 0x00000001U << DDR_PHY_DX8SL2DQSCTL_QSCNTEN_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2DQSCTL_UDQIOM_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_SHIFT - | 0x00000003U << DDR_PHY_DX8SL2DQSCTL_DXSR_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2DQSCTL_DQSNRES_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2DQSCTL_DQSRES_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8SL2DQSCTL_OFFSET ,0xFFFFFFFFU ,0x01264300U); - /*############################################################################################################################ */ - - /*Register : DX8SL2DXCTL2 @ 0XFD0814AC

- - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24 0x0 - - Configurable Read Data Enable - PSU_DDR_PHY_DX8SL2DXCTL2_CRDEN 0x0 - - OX Extension during Post-amble - PSU_DDR_PHY_DX8SL2DXCTL2_POSOEX 0x0 - - OE Extension during Pre-amble - PSU_DDR_PHY_DX8SL2DXCTL2_PREOEX 0x1 - - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_17 0x0 - - I/O Assisted Gate Select - PSU_DDR_PHY_DX8SL2DXCTL2_IOAG 0x0 + * Charge Pump Proportional Current Control + * PSU_DDR_PHY_DX8SL4PLLCR0_CPPC 0x8 - I/O Loopback Select - PSU_DDR_PHY_DX8SL2DXCTL2_IOLB 0x0 + * Charge Pump Integrating Current Control + * PSU_DDR_PHY_DX8SL4PLLCR0_CPIC 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13 0x0 + * Gear Shift + * PSU_DDR_PHY_DX8SL4PLLCR0_GSHIFT 0x0 - Low Power Wakeup Threshold - PSU_DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH 0xc + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL4PLLCR0_RESERVED_11_9 0x0 - Read Data Bus Inversion Enable - PSU_DDR_PHY_DX8SL2DXCTL2_RDBI 0x0 + * Analog Test Enable (ATOEN) + * PSU_DDR_PHY_DX8SL4PLLCR0_ATOEN 0x0 - Write Data Bus Inversion Enable - PSU_DDR_PHY_DX8SL2DXCTL2_WDBI 0x0 + * Analog Test Control + * PSU_DDR_PHY_DX8SL4PLLCR0_ATC 0x0 - PUB Read FIFO Bypass - PSU_DDR_PHY_DX8SL2DXCTL2_PRFBYP 0x0 + * Digital Test Control + * PSU_DDR_PHY_DX8SL4PLLCR0_DTC 0x0 - DATX8 Receive FIFO Read Mode - PSU_DDR_PHY_DX8SL2DXCTL2_RDMODE 0x0 + * DAXT8 0-1 PLL Control Register 0 + * (OFFSET, MASK, VALUE) (0XFD081504, 0xFFFFFFFFU ,0x01100000U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL4PLLCR0_OFFSET, + 0xFFFFFFFFU, 0x01100000U); +/*##################################################################### */ - Disables the Read FIFO Reset - PSU_DDR_PHY_DX8SL2DXCTL2_DISRST 0x0 + /* + * Register : DX8SL4DQSCTL @ 0XFD08151C - Read DQS Gate I/O Loopback - PSU_DDR_PHY_DX8SL2DXCTL2_DQSGLB 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_0 0x0 + * Read Path Rise-to-Rise Mode + * PSU_DDR_PHY_DX8SL4DQSCTL_RRRMODE 0x1 - DATX8 0-1 DX Control Register 2 - (OFFSET, MASK, VALUE) (0XFD0814AC, 0xFFFFFFFFU ,0x00041800U) - RegMask = (DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_MASK | DDR_PHY_DX8SL2DXCTL2_CRDEN_MASK | DDR_PHY_DX8SL2DXCTL2_POSOEX_MASK | DDR_PHY_DX8SL2DXCTL2_PREOEX_MASK | DDR_PHY_DX8SL2DXCTL2_RESERVED_17_MASK | DDR_PHY_DX8SL2DXCTL2_IOAG_MASK | DDR_PHY_DX8SL2DXCTL2_IOLB_MASK | DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_MASK | DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_MASK | DDR_PHY_DX8SL2DXCTL2_RDBI_MASK | DDR_PHY_DX8SL2DXCTL2_WDBI_MASK | DDR_PHY_DX8SL2DXCTL2_PRFBYP_MASK | DDR_PHY_DX8SL2DXCTL2_RDMODE_MASK | DDR_PHY_DX8SL2DXCTL2_DISRST_MASK | DDR_PHY_DX8SL2DXCTL2_DQSGLB_MASK | DDR_PHY_DX8SL2DXCTL2_RESERVED_0_MASK | 0 ); + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_CRDEN_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_POSOEX_SHIFT - | 0x00000001U << DDR_PHY_DX8SL2DXCTL2_PREOEX_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_RESERVED_17_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_IOAG_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_IOLB_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_SHIFT - | 0x0000000CU << DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_RDBI_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_WDBI_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_PRFBYP_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_RDMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_DISRST_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_DQSGLB_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2DXCTL2_RESERVED_0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8SL2DXCTL2_OFFSET ,0xFFFFFFFFU ,0x00041800U); - /*############################################################################################################################ */ + * Write Path Rise-to-Rise Mode + * PSU_DDR_PHY_DX8SL4DQSCTL_WRRMODE 0x1 - /*Register : DX8SL2IOCR @ 0XFD0814B0

+ * DQS Gate Extension + * PSU_DDR_PHY_DX8SL4DQSCTL_DQSGX 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL2IOCR_RESERVED_31 0x0 + * Low Power PLL Power Down + * PSU_DDR_PHY_DX8SL4DQSCTL_LPPLLPD 0x1 - PVREF_DAC REFSEL range select - PSU_DDR_PHY_DX8SL2IOCR_DXDACRANGE 0x7 + * Low Power I/O Power Down + * PSU_DDR_PHY_DX8SL4DQSCTL_LPIOPD 0x1 - IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring - PSU_DDR_PHY_DX8SL2IOCR_DXVREFIOM 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15 0x0 - DX IO Mode - PSU_DDR_PHY_DX8SL2IOCR_DXIOM 0x2 + * QS Counter Enable + * PSU_DDR_PHY_DX8SL4DQSCTL_QSCNTEN 0x1 - DX IO Transmitter Mode - PSU_DDR_PHY_DX8SL2IOCR_DXTXM 0x0 + * Unused DQ I/O Mode + * PSU_DDR_PHY_DX8SL4DQSCTL_UDQIOM 0x0 - DX IO Receiver Mode - PSU_DDR_PHY_DX8SL2IOCR_DXRXM 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10 0x0 - DATX8 0-1 I/O Configuration Register - (OFFSET, MASK, VALUE) (0XFD0814B0, 0xFFFFFFFFU ,0x70800000U) - RegMask = (DDR_PHY_DX8SL2IOCR_RESERVED_31_MASK | DDR_PHY_DX8SL2IOCR_DXDACRANGE_MASK | DDR_PHY_DX8SL2IOCR_DXVREFIOM_MASK | DDR_PHY_DX8SL2IOCR_DXIOM_MASK | DDR_PHY_DX8SL2IOCR_DXTXM_MASK | DDR_PHY_DX8SL2IOCR_DXRXM_MASK | 0 ); + * Data Slew Rate + * PSU_DDR_PHY_DX8SL4DQSCTL_DXSR 0x3 - RegVal = ((0x00000000U << DDR_PHY_DX8SL2IOCR_RESERVED_31_SHIFT - | 0x00000007U << DDR_PHY_DX8SL2IOCR_DXDACRANGE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2IOCR_DXVREFIOM_SHIFT - | 0x00000002U << DDR_PHY_DX8SL2IOCR_DXIOM_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2IOCR_DXTXM_SHIFT - | 0x00000000U << DDR_PHY_DX8SL2IOCR_DXRXM_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8SL2IOCR_OFFSET ,0xFFFFFFFFU ,0x70800000U); - /*############################################################################################################################ */ + * DQS_N Resistor + * PSU_DDR_PHY_DX8SL4DQSCTL_DQSNRES 0x0 - /*Register : DX8SL3OSC @ 0XFD0814C0

+ * DQS Resistor + * PSU_DDR_PHY_DX8SL4DQSCTL_DQSRES 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL3OSC_RESERVED_31_30 0x0 + * DATX8 0-1 DQS Control Register + * (OFFSET, MASK, VALUE) (0XFD08151C, 0xFFFFFFFFU ,0x01264300U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL4DQSCTL_OFFSET, + 0xFFFFFFFFU, 0x01264300U); +/*##################################################################### */ - Enable Clock Gating for DX ddr_clk - PSU_DDR_PHY_DX8SL3OSC_GATEDXRDCLK 0x2 + /* + * Register : DX8SL4DXCTL2 @ 0XFD08152C - Enable Clock Gating for DX ctl_rd_clk - PSU_DDR_PHY_DX8SL3OSC_GATEDXDDRCLK 0x2 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24 0x0 - Enable Clock Gating for DX ctl_clk - PSU_DDR_PHY_DX8SL3OSC_GATEDXCTLCLK 0x2 + * Configurable Read Data Enable + * PSU_DDR_PHY_DX8SL4DXCTL2_CRDEN 0x0 - Selects the level to which clocks will be stalled when clock gating is enabled. - PSU_DDR_PHY_DX8SL3OSC_CLKLEVEL 0x0 + * OX Extension during Post-amble + * PSU_DDR_PHY_DX8SL4DXCTL2_POSOEX 0x0 - Loopback Mode - PSU_DDR_PHY_DX8SL3OSC_LBMODE 0x0 + * OE Extension during Pre-amble + * PSU_DDR_PHY_DX8SL4DXCTL2_PREOEX 0x1 - Load GSDQS LCDL with 2x the calibrated GSDQSPRD value - PSU_DDR_PHY_DX8SL3OSC_LBGSDQS 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_17 0x0 - Loopback DQS Gating - PSU_DDR_PHY_DX8SL3OSC_LBGDQS 0x0 + * I/O Assisted Gate Select + * PSU_DDR_PHY_DX8SL4DXCTL2_IOAG 0x0 - Loopback DQS Shift - PSU_DDR_PHY_DX8SL3OSC_LBDQSS 0x0 + * I/O Loopback Select + * PSU_DDR_PHY_DX8SL4DXCTL2_IOLB 0x0 - PHY High-Speed Reset - PSU_DDR_PHY_DX8SL3OSC_PHYHRST 0x1 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13 0x0 - PHY FIFO Reset - PSU_DDR_PHY_DX8SL3OSC_PHYFRST 0x1 + * Low Power Wakeup Threshold + * PSU_DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH 0xc - Delay Line Test Start - PSU_DDR_PHY_DX8SL3OSC_DLTST 0x0 + * Read Data Bus Inversion Enable + * PSU_DDR_PHY_DX8SL4DXCTL2_RDBI 0x0 - Delay Line Test Mode - PSU_DDR_PHY_DX8SL3OSC_DLTMODE 0x0 + * Write Data Bus Inversion Enable + * PSU_DDR_PHY_DX8SL4DXCTL2_WDBI 0x0 - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX8SL3OSC_RESERVED_12_11 0x3 - - Oscillator Mode Write-Data Delay Line Select - PSU_DDR_PHY_DX8SL3OSC_OSCWDDL 0x3 - - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX8SL3OSC_RESERVED_8_7 0x3 - - Oscillator Mode Write-Leveling Delay Line Select - PSU_DDR_PHY_DX8SL3OSC_OSCWDL 0x3 - - Oscillator Mode Division - PSU_DDR_PHY_DX8SL3OSC_OSCDIV 0xf + * PUB Read FIFO Bypass + * PSU_DDR_PHY_DX8SL4DXCTL2_PRFBYP 0x0 - Oscillator Enable - PSU_DDR_PHY_DX8SL3OSC_OSCEN 0x0 + * DATX8 Receive FIFO Read Mode + * PSU_DDR_PHY_DX8SL4DXCTL2_RDMODE 0x0 - DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register - (OFFSET, MASK, VALUE) (0XFD0814C0, 0xFFFFFFFFU ,0x2A019FFEU) - RegMask = (DDR_PHY_DX8SL3OSC_RESERVED_31_30_MASK | DDR_PHY_DX8SL3OSC_GATEDXRDCLK_MASK | DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_MASK | DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_MASK | DDR_PHY_DX8SL3OSC_CLKLEVEL_MASK | DDR_PHY_DX8SL3OSC_LBMODE_MASK | DDR_PHY_DX8SL3OSC_LBGSDQS_MASK | DDR_PHY_DX8SL3OSC_LBGDQS_MASK | DDR_PHY_DX8SL3OSC_LBDQSS_MASK | DDR_PHY_DX8SL3OSC_PHYHRST_MASK | DDR_PHY_DX8SL3OSC_PHYFRST_MASK | DDR_PHY_DX8SL3OSC_DLTST_MASK | DDR_PHY_DX8SL3OSC_DLTMODE_MASK | DDR_PHY_DX8SL3OSC_RESERVED_12_11_MASK | DDR_PHY_DX8SL3OSC_OSCWDDL_MASK | DDR_PHY_DX8SL3OSC_RESERVED_8_7_MASK | DDR_PHY_DX8SL3OSC_OSCWDL_MASK | DDR_PHY_DX8SL3OSC_OSCDIV_MASK | DDR_PHY_DX8SL3OSC_OSCEN_MASK | 0 ); + * Disables the Read FIFO Reset + * PSU_DDR_PHY_DX8SL4DXCTL2_DISRST 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX8SL3OSC_RESERVED_31_30_SHIFT - | 0x00000002U << DDR_PHY_DX8SL3OSC_GATEDXRDCLK_SHIFT - | 0x00000002U << DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_SHIFT - | 0x00000002U << DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3OSC_CLKLEVEL_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3OSC_LBMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3OSC_LBGSDQS_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3OSC_LBGDQS_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3OSC_LBDQSS_SHIFT - | 0x00000001U << DDR_PHY_DX8SL3OSC_PHYHRST_SHIFT - | 0x00000001U << DDR_PHY_DX8SL3OSC_PHYFRST_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3OSC_DLTST_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3OSC_DLTMODE_SHIFT - | 0x00000003U << DDR_PHY_DX8SL3OSC_RESERVED_12_11_SHIFT - | 0x00000003U << DDR_PHY_DX8SL3OSC_OSCWDDL_SHIFT - | 0x00000003U << DDR_PHY_DX8SL3OSC_RESERVED_8_7_SHIFT - | 0x00000003U << DDR_PHY_DX8SL3OSC_OSCWDL_SHIFT - | 0x0000000FU << DDR_PHY_DX8SL3OSC_OSCDIV_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3OSC_OSCEN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8SL3OSC_OFFSET ,0xFFFFFFFFU ,0x2A019FFEU); - /*############################################################################################################################ */ + * Read DQS Gate I/O Loopback + * PSU_DDR_PHY_DX8SL4DXCTL2_DQSGLB 0x0 - /*Register : DX8SL3DQSCTL @ 0XFD0814DC

+ * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_0 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25 0x0 + * DATX8 0-1 DX Control Register 2 + * (OFFSET, MASK, VALUE) (0XFD08152C, 0xFFFFFFFFU ,0x00041800U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL4DXCTL2_OFFSET, + 0xFFFFFFFFU, 0x00041800U); +/*##################################################################### */ - Read Path Rise-to-Rise Mode - PSU_DDR_PHY_DX8SL3DQSCTL_RRRMODE 0x1 + /* + * Register : DX8SL4IOCR @ 0XFD081530 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SL4IOCR_RESERVED_31 0x0 - Write Path Rise-to-Rise Mode - PSU_DDR_PHY_DX8SL3DQSCTL_WRRMODE 0x1 + * PVREF_DAC REFSEL range select + * PSU_DDR_PHY_DX8SL4IOCR_DXDACRANGE 0x7 - DQS Gate Extension - PSU_DDR_PHY_DX8SL3DQSCTL_DQSGX 0x0 + * IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring + * PSU_DDR_PHY_DX8SL4IOCR_DXVREFIOM 0x0 - Low Power PLL Power Down - PSU_DDR_PHY_DX8SL3DQSCTL_LPPLLPD 0x1 + * DX IO Mode + * PSU_DDR_PHY_DX8SL4IOCR_DXIOM 0x2 - Low Power I/O Power Down - PSU_DDR_PHY_DX8SL3DQSCTL_LPIOPD 0x1 + * DX IO Transmitter Mode + * PSU_DDR_PHY_DX8SL4IOCR_DXTXM 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15 0x0 + * DX IO Receiver Mode + * PSU_DDR_PHY_DX8SL4IOCR_DXRXM 0x0 - QS Counter Enable - PSU_DDR_PHY_DX8SL3DQSCTL_QSCNTEN 0x1 + * DATX8 0-1 I/O Configuration Register + * (OFFSET, MASK, VALUE) (0XFD081530, 0xFFFFFFFFU ,0x70800000U) + */ + PSU_Mask_Write(DDR_PHY_DX8SL4IOCR_OFFSET, 0xFFFFFFFFU, 0x70800000U); +/*##################################################################### */ - Unused DQ I/O Mode - PSU_DDR_PHY_DX8SL3DQSCTL_UDQIOM 0x0 + /* + * Register : DX8SLbPLLCR0 @ 0XFD0817C4 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10 0x0 + * PLL Bypass + * PSU_DDR_PHY_DX8SLBPLLCR0_PLLBYP 0x0 - Data Slew Rate - PSU_DDR_PHY_DX8SL3DQSCTL_DXSR 0x3 - - DQS_N Resistor - PSU_DDR_PHY_DX8SL3DQSCTL_DQSNRES 0x0 - - DQS Resistor - PSU_DDR_PHY_DX8SL3DQSCTL_DQSRES 0x0 - - DATX8 0-1 DQS Control Register - (OFFSET, MASK, VALUE) (0XFD0814DC, 0xFFFFFFFFU ,0x01264300U) - RegMask = (DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_MASK | DDR_PHY_DX8SL3DQSCTL_RRRMODE_MASK | DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_MASK | DDR_PHY_DX8SL3DQSCTL_WRRMODE_MASK | DDR_PHY_DX8SL3DQSCTL_DQSGX_MASK | DDR_PHY_DX8SL3DQSCTL_LPPLLPD_MASK | DDR_PHY_DX8SL3DQSCTL_LPIOPD_MASK | DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_MASK | DDR_PHY_DX8SL3DQSCTL_QSCNTEN_MASK | DDR_PHY_DX8SL3DQSCTL_UDQIOM_MASK | DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_MASK | DDR_PHY_DX8SL3DQSCTL_DXSR_MASK | DDR_PHY_DX8SL3DQSCTL_DQSNRES_MASK | DDR_PHY_DX8SL3DQSCTL_DQSRES_MASK | 0 ); + * PLL Reset + * PSU_DDR_PHY_DX8SLBPLLCR0_PLLRST 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_SHIFT - | 0x00000001U << DDR_PHY_DX8SL3DQSCTL_RRRMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_SHIFT - | 0x00000001U << DDR_PHY_DX8SL3DQSCTL_WRRMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3DQSCTL_DQSGX_SHIFT - | 0x00000001U << DDR_PHY_DX8SL3DQSCTL_LPPLLPD_SHIFT - | 0x00000001U << DDR_PHY_DX8SL3DQSCTL_LPIOPD_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_SHIFT - | 0x00000001U << DDR_PHY_DX8SL3DQSCTL_QSCNTEN_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3DQSCTL_UDQIOM_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_SHIFT - | 0x00000003U << DDR_PHY_DX8SL3DQSCTL_DXSR_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3DQSCTL_DQSNRES_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3DQSCTL_DQSRES_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8SL3DQSCTL_OFFSET ,0xFFFFFFFFU ,0x01264300U); - /*############################################################################################################################ */ - - /*Register : DX8SL3DXCTL2 @ 0XFD0814EC

- - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24 0x0 - - Configurable Read Data Enable - PSU_DDR_PHY_DX8SL3DXCTL2_CRDEN 0x0 - - OX Extension during Post-amble - PSU_DDR_PHY_DX8SL3DXCTL2_POSOEX 0x0 - - OE Extension during Pre-amble - PSU_DDR_PHY_DX8SL3DXCTL2_PREOEX 0x1 - - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_17 0x0 - - I/O Assisted Gate Select - PSU_DDR_PHY_DX8SL3DXCTL2_IOAG 0x0 + * PLL Power Down + * PSU_DDR_PHY_DX8SLBPLLCR0_PLLPD 0x0 - I/O Loopback Select - PSU_DDR_PHY_DX8SL3DXCTL2_IOLB 0x0 + * Reference Stop Mode + * PSU_DDR_PHY_DX8SLBPLLCR0_RSTOPM 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13 0x0 + * PLL Frequency Select + * PSU_DDR_PHY_DX8SLBPLLCR0_FRQSEL 0x1 - Low Power Wakeup Threshold - PSU_DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH 0xc + * Relock Mode + * PSU_DDR_PHY_DX8SLBPLLCR0_RLOCKM 0x0 - Read Data Bus Inversion Enable - PSU_DDR_PHY_DX8SL3DXCTL2_RDBI 0x0 + * Charge Pump Proportional Current Control + * PSU_DDR_PHY_DX8SLBPLLCR0_CPPC 0x8 - Write Data Bus Inversion Enable - PSU_DDR_PHY_DX8SL3DXCTL2_WDBI 0x0 + * Charge Pump Integrating Current Control + * PSU_DDR_PHY_DX8SLBPLLCR0_CPIC 0x0 - PUB Read FIFO Bypass - PSU_DDR_PHY_DX8SL3DXCTL2_PRFBYP 0x0 + * Gear Shift + * PSU_DDR_PHY_DX8SLBPLLCR0_GSHIFT 0x0 - DATX8 Receive FIFO Read Mode - PSU_DDR_PHY_DX8SL3DXCTL2_RDMODE 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SLBPLLCR0_RESERVED_11_9 0x0 - Disables the Read FIFO Reset - PSU_DDR_PHY_DX8SL3DXCTL2_DISRST 0x0 + * Analog Test Enable (ATOEN) + * PSU_DDR_PHY_DX8SLBPLLCR0_ATOEN 0x0 - Read DQS Gate I/O Loopback - PSU_DDR_PHY_DX8SL3DXCTL2_DQSGLB 0x0 + * Analog Test Control + * PSU_DDR_PHY_DX8SLBPLLCR0_ATC 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_0 0x0 + * Digital Test Control + * PSU_DDR_PHY_DX8SLBPLLCR0_DTC 0x0 - DATX8 0-1 DX Control Register 2 - (OFFSET, MASK, VALUE) (0XFD0814EC, 0xFFFFFFFFU ,0x00041800U) - RegMask = (DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_MASK | DDR_PHY_DX8SL3DXCTL2_CRDEN_MASK | DDR_PHY_DX8SL3DXCTL2_POSOEX_MASK | DDR_PHY_DX8SL3DXCTL2_PREOEX_MASK | DDR_PHY_DX8SL3DXCTL2_RESERVED_17_MASK | DDR_PHY_DX8SL3DXCTL2_IOAG_MASK | DDR_PHY_DX8SL3DXCTL2_IOLB_MASK | DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_MASK | DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_MASK | DDR_PHY_DX8SL3DXCTL2_RDBI_MASK | DDR_PHY_DX8SL3DXCTL2_WDBI_MASK | DDR_PHY_DX8SL3DXCTL2_PRFBYP_MASK | DDR_PHY_DX8SL3DXCTL2_RDMODE_MASK | DDR_PHY_DX8SL3DXCTL2_DISRST_MASK | DDR_PHY_DX8SL3DXCTL2_DQSGLB_MASK | DDR_PHY_DX8SL3DXCTL2_RESERVED_0_MASK | 0 ); + * DAXT8 0-8 PLL Control Register 0 + * (OFFSET, MASK, VALUE) (0XFD0817C4, 0xFFFFFFFFU ,0x01100000U) + */ + PSU_Mask_Write(DDR_PHY_DX8SLBPLLCR0_OFFSET, + 0xFFFFFFFFU, 0x01100000U); +/*##################################################################### */ - RegVal = ((0x00000000U << DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_CRDEN_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_POSOEX_SHIFT - | 0x00000001U << DDR_PHY_DX8SL3DXCTL2_PREOEX_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_RESERVED_17_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_IOAG_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_IOLB_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_SHIFT - | 0x0000000CU << DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_RDBI_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_WDBI_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_PRFBYP_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_RDMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_DISRST_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_DQSGLB_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3DXCTL2_RESERVED_0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8SL3DXCTL2_OFFSET ,0xFFFFFFFFU ,0x00041800U); - /*############################################################################################################################ */ + /* + * Register : DX8SLbDQSCTL @ 0XFD0817DC - /*Register : DX8SL3IOCR @ 0XFD0814F0

+ * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL3IOCR_RESERVED_31 0x0 + * Read Path Rise-to-Rise Mode + * PSU_DDR_PHY_DX8SLBDQSCTL_RRRMODE 0x1 - PVREF_DAC REFSEL range select - PSU_DDR_PHY_DX8SL3IOCR_DXDACRANGE 0x7 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22 0x0 - IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring - PSU_DDR_PHY_DX8SL3IOCR_DXVREFIOM 0x0 + * Write Path Rise-to-Rise Mode + * PSU_DDR_PHY_DX8SLBDQSCTL_WRRMODE 0x1 - DX IO Mode - PSU_DDR_PHY_DX8SL3IOCR_DXIOM 0x2 + * DQS Gate Extension + * PSU_DDR_PHY_DX8SLBDQSCTL_DQSGX 0x0 - DX IO Transmitter Mode - PSU_DDR_PHY_DX8SL3IOCR_DXTXM 0x0 + * Low Power PLL Power Down + * PSU_DDR_PHY_DX8SLBDQSCTL_LPPLLPD 0x1 - DX IO Receiver Mode - PSU_DDR_PHY_DX8SL3IOCR_DXRXM 0x0 + * Low Power I/O Power Down + * PSU_DDR_PHY_DX8SLBDQSCTL_LPIOPD 0x1 - DATX8 0-1 I/O Configuration Register - (OFFSET, MASK, VALUE) (0XFD0814F0, 0xFFFFFFFFU ,0x70800000U) - RegMask = (DDR_PHY_DX8SL3IOCR_RESERVED_31_MASK | DDR_PHY_DX8SL3IOCR_DXDACRANGE_MASK | DDR_PHY_DX8SL3IOCR_DXVREFIOM_MASK | DDR_PHY_DX8SL3IOCR_DXIOM_MASK | DDR_PHY_DX8SL3IOCR_DXTXM_MASK | DDR_PHY_DX8SL3IOCR_DXRXM_MASK | 0 ); + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15 0x0 - RegVal = ((0x00000000U << DDR_PHY_DX8SL3IOCR_RESERVED_31_SHIFT - | 0x00000007U << DDR_PHY_DX8SL3IOCR_DXDACRANGE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3IOCR_DXVREFIOM_SHIFT - | 0x00000002U << DDR_PHY_DX8SL3IOCR_DXIOM_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3IOCR_DXTXM_SHIFT - | 0x00000000U << DDR_PHY_DX8SL3IOCR_DXRXM_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8SL3IOCR_OFFSET ,0xFFFFFFFFU ,0x70800000U); - /*############################################################################################################################ */ + * QS Counter Enable + * PSU_DDR_PHY_DX8SLBDQSCTL_QSCNTEN 0x1 - /*Register : DX8SL4OSC @ 0XFD081500

+ * Unused DQ I/O Mode + * PSU_DDR_PHY_DX8SLBDQSCTL_UDQIOM 0x0 - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL4OSC_RESERVED_31_30 0x0 + * Reserved. Return zeroes on reads. + * PSU_DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10 0x0 - Enable Clock Gating for DX ddr_clk - PSU_DDR_PHY_DX8SL4OSC_GATEDXRDCLK 0x2 + * Data Slew Rate + * PSU_DDR_PHY_DX8SLBDQSCTL_DXSR 0x3 - Enable Clock Gating for DX ctl_rd_clk - PSU_DDR_PHY_DX8SL4OSC_GATEDXDDRCLK 0x2 + * DQS# Resistor + * PSU_DDR_PHY_DX8SLBDQSCTL_DQSNRES 0xc - Enable Clock Gating for DX ctl_clk - PSU_DDR_PHY_DX8SL4OSC_GATEDXCTLCLK 0x2 + * DQS Resistor + * PSU_DDR_PHY_DX8SLBDQSCTL_DQSRES 0x4 - Selects the level to which clocks will be stalled when clock gating is enabled. - PSU_DDR_PHY_DX8SL4OSC_CLKLEVEL 0x0 + * DATX8 0-8 DQS Control Register + * (OFFSET, MASK, VALUE) (0XFD0817DC, 0xFFFFFFFFU ,0x012643C4U) + */ + PSU_Mask_Write(DDR_PHY_DX8SLBDQSCTL_OFFSET, + 0xFFFFFFFFU, 0x012643C4U); +/*##################################################################### */ - Loopback Mode - PSU_DDR_PHY_DX8SL4OSC_LBMODE 0x0 - Load GSDQS LCDL with 2x the calibrated GSDQSPRD value - PSU_DDR_PHY_DX8SL4OSC_LBGSDQS 0x0 - - Loopback DQS Gating - PSU_DDR_PHY_DX8SL4OSC_LBGDQS 0x0 - - Loopback DQS Shift - PSU_DDR_PHY_DX8SL4OSC_LBDQSS 0x0 - - PHY High-Speed Reset - PSU_DDR_PHY_DX8SL4OSC_PHYHRST 0x1 - - PHY FIFO Reset - PSU_DDR_PHY_DX8SL4OSC_PHYFRST 0x1 - - Delay Line Test Start - PSU_DDR_PHY_DX8SL4OSC_DLTST 0x0 - - Delay Line Test Mode - PSU_DDR_PHY_DX8SL4OSC_DLTMODE 0x0 - - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX8SL4OSC_RESERVED_12_11 0x3 - - Oscillator Mode Write-Data Delay Line Select - PSU_DDR_PHY_DX8SL4OSC_OSCWDDL 0x3 - - Reserved. Caution, do not write to this register field. - PSU_DDR_PHY_DX8SL4OSC_RESERVED_8_7 0x3 - - Oscillator Mode Write-Leveling Delay Line Select - PSU_DDR_PHY_DX8SL4OSC_OSCWDL 0x3 - - Oscillator Mode Division - PSU_DDR_PHY_DX8SL4OSC_OSCDIV 0xf - - Oscillator Enable - PSU_DDR_PHY_DX8SL4OSC_OSCEN 0x0 - - DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register - (OFFSET, MASK, VALUE) (0XFD081500, 0xFFFFFFFFU ,0x2A019FFEU) - RegMask = (DDR_PHY_DX8SL4OSC_RESERVED_31_30_MASK | DDR_PHY_DX8SL4OSC_GATEDXRDCLK_MASK | DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_MASK | DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_MASK | DDR_PHY_DX8SL4OSC_CLKLEVEL_MASK | DDR_PHY_DX8SL4OSC_LBMODE_MASK | DDR_PHY_DX8SL4OSC_LBGSDQS_MASK | DDR_PHY_DX8SL4OSC_LBGDQS_MASK | DDR_PHY_DX8SL4OSC_LBDQSS_MASK | DDR_PHY_DX8SL4OSC_PHYHRST_MASK | DDR_PHY_DX8SL4OSC_PHYFRST_MASK | DDR_PHY_DX8SL4OSC_DLTST_MASK | DDR_PHY_DX8SL4OSC_DLTMODE_MASK | DDR_PHY_DX8SL4OSC_RESERVED_12_11_MASK | DDR_PHY_DX8SL4OSC_OSCWDDL_MASK | DDR_PHY_DX8SL4OSC_RESERVED_8_7_MASK | DDR_PHY_DX8SL4OSC_OSCWDL_MASK | DDR_PHY_DX8SL4OSC_OSCDIV_MASK | DDR_PHY_DX8SL4OSC_OSCEN_MASK | 0 ); - - RegVal = ((0x00000000U << DDR_PHY_DX8SL4OSC_RESERVED_31_30_SHIFT - | 0x00000002U << DDR_PHY_DX8SL4OSC_GATEDXRDCLK_SHIFT - | 0x00000002U << DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_SHIFT - | 0x00000002U << DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4OSC_CLKLEVEL_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4OSC_LBMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4OSC_LBGSDQS_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4OSC_LBGDQS_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4OSC_LBDQSS_SHIFT - | 0x00000001U << DDR_PHY_DX8SL4OSC_PHYHRST_SHIFT - | 0x00000001U << DDR_PHY_DX8SL4OSC_PHYFRST_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4OSC_DLTST_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4OSC_DLTMODE_SHIFT - | 0x00000003U << DDR_PHY_DX8SL4OSC_RESERVED_12_11_SHIFT - | 0x00000003U << DDR_PHY_DX8SL4OSC_OSCWDDL_SHIFT - | 0x00000003U << DDR_PHY_DX8SL4OSC_RESERVED_8_7_SHIFT - | 0x00000003U << DDR_PHY_DX8SL4OSC_OSCWDL_SHIFT - | 0x0000000FU << DDR_PHY_DX8SL4OSC_OSCDIV_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4OSC_OSCEN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8SL4OSC_OFFSET ,0xFFFFFFFFU ,0x2A019FFEU); - /*############################################################################################################################ */ - - /*Register : DX8SL4DQSCTL @ 0XFD08151C

- - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25 0x0 - - Read Path Rise-to-Rise Mode - PSU_DDR_PHY_DX8SL4DQSCTL_RRRMODE 0x1 - - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22 0x0 - - Write Path Rise-to-Rise Mode - PSU_DDR_PHY_DX8SL4DQSCTL_WRRMODE 0x1 - - DQS Gate Extension - PSU_DDR_PHY_DX8SL4DQSCTL_DQSGX 0x0 - - Low Power PLL Power Down - PSU_DDR_PHY_DX8SL4DQSCTL_LPPLLPD 0x1 - - Low Power I/O Power Down - PSU_DDR_PHY_DX8SL4DQSCTL_LPIOPD 0x1 - - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15 0x0 - - QS Counter Enable - PSU_DDR_PHY_DX8SL4DQSCTL_QSCNTEN 0x1 - - Unused DQ I/O Mode - PSU_DDR_PHY_DX8SL4DQSCTL_UDQIOM 0x0 - - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10 0x0 - - Data Slew Rate - PSU_DDR_PHY_DX8SL4DQSCTL_DXSR 0x3 - - DQS_N Resistor - PSU_DDR_PHY_DX8SL4DQSCTL_DQSNRES 0x0 - - DQS Resistor - PSU_DDR_PHY_DX8SL4DQSCTL_DQSRES 0x0 - - DATX8 0-1 DQS Control Register - (OFFSET, MASK, VALUE) (0XFD08151C, 0xFFFFFFFFU ,0x01264300U) - RegMask = (DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_MASK | DDR_PHY_DX8SL4DQSCTL_RRRMODE_MASK | DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_MASK | DDR_PHY_DX8SL4DQSCTL_WRRMODE_MASK | DDR_PHY_DX8SL4DQSCTL_DQSGX_MASK | DDR_PHY_DX8SL4DQSCTL_LPPLLPD_MASK | DDR_PHY_DX8SL4DQSCTL_LPIOPD_MASK | DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_MASK | DDR_PHY_DX8SL4DQSCTL_QSCNTEN_MASK | DDR_PHY_DX8SL4DQSCTL_UDQIOM_MASK | DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_MASK | DDR_PHY_DX8SL4DQSCTL_DXSR_MASK | DDR_PHY_DX8SL4DQSCTL_DQSNRES_MASK | DDR_PHY_DX8SL4DQSCTL_DQSRES_MASK | 0 ); - - RegVal = ((0x00000000U << DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_SHIFT - | 0x00000001U << DDR_PHY_DX8SL4DQSCTL_RRRMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_SHIFT - | 0x00000001U << DDR_PHY_DX8SL4DQSCTL_WRRMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4DQSCTL_DQSGX_SHIFT - | 0x00000001U << DDR_PHY_DX8SL4DQSCTL_LPPLLPD_SHIFT - | 0x00000001U << DDR_PHY_DX8SL4DQSCTL_LPIOPD_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_SHIFT - | 0x00000001U << DDR_PHY_DX8SL4DQSCTL_QSCNTEN_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4DQSCTL_UDQIOM_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_SHIFT - | 0x00000003U << DDR_PHY_DX8SL4DQSCTL_DXSR_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4DQSCTL_DQSNRES_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4DQSCTL_DQSRES_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8SL4DQSCTL_OFFSET ,0xFFFFFFFFU ,0x01264300U); - /*############################################################################################################################ */ - - /*Register : DX8SL4DXCTL2 @ 0XFD08152C

- - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24 0x0 - - Configurable Read Data Enable - PSU_DDR_PHY_DX8SL4DXCTL2_CRDEN 0x0 - - OX Extension during Post-amble - PSU_DDR_PHY_DX8SL4DXCTL2_POSOEX 0x0 - - OE Extension during Pre-amble - PSU_DDR_PHY_DX8SL4DXCTL2_PREOEX 0x1 - - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_17 0x0 - - I/O Assisted Gate Select - PSU_DDR_PHY_DX8SL4DXCTL2_IOAG 0x0 - - I/O Loopback Select - PSU_DDR_PHY_DX8SL4DXCTL2_IOLB 0x0 - - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13 0x0 - - Low Power Wakeup Threshold - PSU_DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH 0xc - - Read Data Bus Inversion Enable - PSU_DDR_PHY_DX8SL4DXCTL2_RDBI 0x0 - - Write Data Bus Inversion Enable - PSU_DDR_PHY_DX8SL4DXCTL2_WDBI 0x0 - - PUB Read FIFO Bypass - PSU_DDR_PHY_DX8SL4DXCTL2_PRFBYP 0x0 - - DATX8 Receive FIFO Read Mode - PSU_DDR_PHY_DX8SL4DXCTL2_RDMODE 0x0 - - Disables the Read FIFO Reset - PSU_DDR_PHY_DX8SL4DXCTL2_DISRST 0x0 - - Read DQS Gate I/O Loopback - PSU_DDR_PHY_DX8SL4DXCTL2_DQSGLB 0x0 - - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_0 0x0 - - DATX8 0-1 DX Control Register 2 - (OFFSET, MASK, VALUE) (0XFD08152C, 0xFFFFFFFFU ,0x00041800U) - RegMask = (DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_MASK | DDR_PHY_DX8SL4DXCTL2_CRDEN_MASK | DDR_PHY_DX8SL4DXCTL2_POSOEX_MASK | DDR_PHY_DX8SL4DXCTL2_PREOEX_MASK | DDR_PHY_DX8SL4DXCTL2_RESERVED_17_MASK | DDR_PHY_DX8SL4DXCTL2_IOAG_MASK | DDR_PHY_DX8SL4DXCTL2_IOLB_MASK | DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_MASK | DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_MASK | DDR_PHY_DX8SL4DXCTL2_RDBI_MASK | DDR_PHY_DX8SL4DXCTL2_WDBI_MASK | DDR_PHY_DX8SL4DXCTL2_PRFBYP_MASK | DDR_PHY_DX8SL4DXCTL2_RDMODE_MASK | DDR_PHY_DX8SL4DXCTL2_DISRST_MASK | DDR_PHY_DX8SL4DXCTL2_DQSGLB_MASK | DDR_PHY_DX8SL4DXCTL2_RESERVED_0_MASK | 0 ); - - RegVal = ((0x00000000U << DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_CRDEN_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_POSOEX_SHIFT - | 0x00000001U << DDR_PHY_DX8SL4DXCTL2_PREOEX_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_RESERVED_17_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_IOAG_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_IOLB_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_SHIFT - | 0x0000000CU << DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_RDBI_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_WDBI_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_PRFBYP_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_RDMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_DISRST_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_DQSGLB_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4DXCTL2_RESERVED_0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8SL4DXCTL2_OFFSET ,0xFFFFFFFFU ,0x00041800U); - /*############################################################################################################################ */ - - /*Register : DX8SL4IOCR @ 0XFD081530

- - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SL4IOCR_RESERVED_31 0x0 - - PVREF_DAC REFSEL range select - PSU_DDR_PHY_DX8SL4IOCR_DXDACRANGE 0x7 - - IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring - PSU_DDR_PHY_DX8SL4IOCR_DXVREFIOM 0x0 - - DX IO Mode - PSU_DDR_PHY_DX8SL4IOCR_DXIOM 0x2 - - DX IO Transmitter Mode - PSU_DDR_PHY_DX8SL4IOCR_DXTXM 0x0 - - DX IO Receiver Mode - PSU_DDR_PHY_DX8SL4IOCR_DXRXM 0x0 - - DATX8 0-1 I/O Configuration Register - (OFFSET, MASK, VALUE) (0XFD081530, 0xFFFFFFFFU ,0x70800000U) - RegMask = (DDR_PHY_DX8SL4IOCR_RESERVED_31_MASK | DDR_PHY_DX8SL4IOCR_DXDACRANGE_MASK | DDR_PHY_DX8SL4IOCR_DXVREFIOM_MASK | DDR_PHY_DX8SL4IOCR_DXIOM_MASK | DDR_PHY_DX8SL4IOCR_DXTXM_MASK | DDR_PHY_DX8SL4IOCR_DXRXM_MASK | 0 ); - - RegVal = ((0x00000000U << DDR_PHY_DX8SL4IOCR_RESERVED_31_SHIFT - | 0x00000007U << DDR_PHY_DX8SL4IOCR_DXDACRANGE_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4IOCR_DXVREFIOM_SHIFT - | 0x00000002U << DDR_PHY_DX8SL4IOCR_DXIOM_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4IOCR_DXTXM_SHIFT - | 0x00000000U << DDR_PHY_DX8SL4IOCR_DXRXM_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8SL4IOCR_OFFSET ,0xFFFFFFFFU ,0x70800000U); - /*############################################################################################################################ */ - - /*Register : DX8SLbDQSCTL @ 0XFD0817DC

- - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25 0x0 - - Read Path Rise-to-Rise Mode - PSU_DDR_PHY_DX8SLBDQSCTL_RRRMODE 0x1 - - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22 0x0 - - Write Path Rise-to-Rise Mode - PSU_DDR_PHY_DX8SLBDQSCTL_WRRMODE 0x1 - - DQS Gate Extension - PSU_DDR_PHY_DX8SLBDQSCTL_DQSGX 0x0 - - Low Power PLL Power Down - PSU_DDR_PHY_DX8SLBDQSCTL_LPPLLPD 0x1 - - Low Power I/O Power Down - PSU_DDR_PHY_DX8SLBDQSCTL_LPIOPD 0x1 - - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15 0x0 - - QS Counter Enable - PSU_DDR_PHY_DX8SLBDQSCTL_QSCNTEN 0x1 - - Unused DQ I/O Mode - PSU_DDR_PHY_DX8SLBDQSCTL_UDQIOM 0x0 - - Reserved. Return zeroes on reads. - PSU_DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10 0x0 - - Data Slew Rate - PSU_DDR_PHY_DX8SLBDQSCTL_DXSR 0x3 - - DQS# Resistor - PSU_DDR_PHY_DX8SLBDQSCTL_DQSNRES 0xc - - DQS Resistor - PSU_DDR_PHY_DX8SLBDQSCTL_DQSRES 0x4 - - DATX8 0-8 DQS Control Register - (OFFSET, MASK, VALUE) (0XFD0817DC, 0xFFFFFFFFU ,0x012643C4U) - RegMask = (DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_MASK | DDR_PHY_DX8SLBDQSCTL_RRRMODE_MASK | DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_MASK | DDR_PHY_DX8SLBDQSCTL_WRRMODE_MASK | DDR_PHY_DX8SLBDQSCTL_DQSGX_MASK | DDR_PHY_DX8SLBDQSCTL_LPPLLPD_MASK | DDR_PHY_DX8SLBDQSCTL_LPIOPD_MASK | DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_MASK | DDR_PHY_DX8SLBDQSCTL_QSCNTEN_MASK | DDR_PHY_DX8SLBDQSCTL_UDQIOM_MASK | DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_MASK | DDR_PHY_DX8SLBDQSCTL_DXSR_MASK | DDR_PHY_DX8SLBDQSCTL_DQSNRES_MASK | DDR_PHY_DX8SLBDQSCTL_DQSRES_MASK | 0 ); - - RegVal = ((0x00000000U << DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_SHIFT - | 0x00000001U << DDR_PHY_DX8SLBDQSCTL_RRRMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_SHIFT - | 0x00000001U << DDR_PHY_DX8SLBDQSCTL_WRRMODE_SHIFT - | 0x00000000U << DDR_PHY_DX8SLBDQSCTL_DQSGX_SHIFT - | 0x00000001U << DDR_PHY_DX8SLBDQSCTL_LPPLLPD_SHIFT - | 0x00000001U << DDR_PHY_DX8SLBDQSCTL_LPIOPD_SHIFT - | 0x00000000U << DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_SHIFT - | 0x00000001U << DDR_PHY_DX8SLBDQSCTL_QSCNTEN_SHIFT - | 0x00000000U << DDR_PHY_DX8SLBDQSCTL_UDQIOM_SHIFT - | 0x00000000U << DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_SHIFT - | 0x00000003U << DDR_PHY_DX8SLBDQSCTL_DXSR_SHIFT - | 0x0000000CU << DDR_PHY_DX8SLBDQSCTL_DQSNRES_SHIFT - | 0x00000004U << DDR_PHY_DX8SLBDQSCTL_DQSRES_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_DX8SLBDQSCTL_OFFSET ,0xFFFFFFFFU ,0x012643C4U); - /*############################################################################################################################ */ - - /*Register : PIR @ 0XFD080004

- - Reserved. Return zeroes on reads. - PSU_DDR_PHY_PIR_RESERVED_31 0x0 - - Impedance Calibration Bypass - PSU_DDR_PHY_PIR_ZCALBYP 0x0 - - Digital Delay Line (DDL) Calibration Pause - PSU_DDR_PHY_PIR_DCALPSE 0x0 - - Reserved. Return zeroes on reads. - PSU_DDR_PHY_PIR_RESERVED_28_21 0x0 - - Write DQS2DQ Training - PSU_DDR_PHY_PIR_DQS2DQ 0x0 - - RDIMM Initialization - PSU_DDR_PHY_PIR_RDIMMINIT 0x0 - - Controller DRAM Initialization - PSU_DDR_PHY_PIR_CTLDINIT 0x1 - - VREF Training - PSU_DDR_PHY_PIR_VREF 0x0 - - Static Read Training - PSU_DDR_PHY_PIR_SRD 0x0 - - Write Data Eye Training - PSU_DDR_PHY_PIR_WREYE 0x0 - - Read Data Eye Training - PSU_DDR_PHY_PIR_RDEYE 0x0 - - Write Data Bit Deskew - PSU_DDR_PHY_PIR_WRDSKW 0x0 - - Read Data Bit Deskew - PSU_DDR_PHY_PIR_RDDSKW 0x0 - - Write Leveling Adjust - PSU_DDR_PHY_PIR_WLADJ 0x0 - - Read DQS Gate Training - PSU_DDR_PHY_PIR_QSGATE 0x0 - - Write Leveling - PSU_DDR_PHY_PIR_WL 0x0 - - DRAM Initialization - PSU_DDR_PHY_PIR_DRAMINIT 0x0 - - DRAM Reset (DDR3/DDR4/LPDDR4 Only) - PSU_DDR_PHY_PIR_DRAMRST 0x0 - - PHY Reset - PSU_DDR_PHY_PIR_PHYRST 0x1 - - Digital Delay Line (DDL) Calibration - PSU_DDR_PHY_PIR_DCAL 0x1 - - PLL Initialiazation - PSU_DDR_PHY_PIR_PLLINIT 0x1 - - Reserved. Return zeroes on reads. - PSU_DDR_PHY_PIR_RESERVED_3 0x0 - - CA Training - PSU_DDR_PHY_PIR_CA 0x0 - - Impedance Calibration - PSU_DDR_PHY_PIR_ZCAL 0x1 - - Initialization Trigger - PSU_DDR_PHY_PIR_INIT 0x1 - - PHY Initialization Register - (OFFSET, MASK, VALUE) (0XFD080004, 0xFFFFFFFFU ,0x00040073U) - RegMask = (DDR_PHY_PIR_RESERVED_31_MASK | DDR_PHY_PIR_ZCALBYP_MASK | DDR_PHY_PIR_DCALPSE_MASK | DDR_PHY_PIR_RESERVED_28_21_MASK | DDR_PHY_PIR_DQS2DQ_MASK | DDR_PHY_PIR_RDIMMINIT_MASK | DDR_PHY_PIR_CTLDINIT_MASK | DDR_PHY_PIR_VREF_MASK | DDR_PHY_PIR_SRD_MASK | DDR_PHY_PIR_WREYE_MASK | DDR_PHY_PIR_RDEYE_MASK | DDR_PHY_PIR_WRDSKW_MASK | DDR_PHY_PIR_RDDSKW_MASK | DDR_PHY_PIR_WLADJ_MASK | DDR_PHY_PIR_QSGATE_MASK | DDR_PHY_PIR_WL_MASK | DDR_PHY_PIR_DRAMINIT_MASK | DDR_PHY_PIR_DRAMRST_MASK | DDR_PHY_PIR_PHYRST_MASK | DDR_PHY_PIR_DCAL_MASK | DDR_PHY_PIR_PLLINIT_MASK | DDR_PHY_PIR_RESERVED_3_MASK | DDR_PHY_PIR_CA_MASK | DDR_PHY_PIR_ZCAL_MASK | DDR_PHY_PIR_INIT_MASK | 0 ); - - RegVal = ((0x00000000U << DDR_PHY_PIR_RESERVED_31_SHIFT - | 0x00000000U << DDR_PHY_PIR_ZCALBYP_SHIFT - | 0x00000000U << DDR_PHY_PIR_DCALPSE_SHIFT - | 0x00000000U << DDR_PHY_PIR_RESERVED_28_21_SHIFT - | 0x00000000U << DDR_PHY_PIR_DQS2DQ_SHIFT - | 0x00000000U << DDR_PHY_PIR_RDIMMINIT_SHIFT - | 0x00000001U << DDR_PHY_PIR_CTLDINIT_SHIFT - | 0x00000000U << DDR_PHY_PIR_VREF_SHIFT - | 0x00000000U << DDR_PHY_PIR_SRD_SHIFT - | 0x00000000U << DDR_PHY_PIR_WREYE_SHIFT - | 0x00000000U << DDR_PHY_PIR_RDEYE_SHIFT - | 0x00000000U << DDR_PHY_PIR_WRDSKW_SHIFT - | 0x00000000U << DDR_PHY_PIR_RDDSKW_SHIFT - | 0x00000000U << DDR_PHY_PIR_WLADJ_SHIFT - | 0x00000000U << DDR_PHY_PIR_QSGATE_SHIFT - | 0x00000000U << DDR_PHY_PIR_WL_SHIFT - | 0x00000000U << DDR_PHY_PIR_DRAMINIT_SHIFT - | 0x00000000U << DDR_PHY_PIR_DRAMRST_SHIFT - | 0x00000001U << DDR_PHY_PIR_PHYRST_SHIFT - | 0x00000001U << DDR_PHY_PIR_DCAL_SHIFT - | 0x00000001U << DDR_PHY_PIR_PLLINIT_SHIFT - | 0x00000000U << DDR_PHY_PIR_RESERVED_3_SHIFT - | 0x00000000U << DDR_PHY_PIR_CA_SHIFT - | 0x00000001U << DDR_PHY_PIR_ZCAL_SHIFT - | 0x00000001U << DDR_PHY_PIR_INIT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DDR_PHY_PIR_OFFSET ,0xFFFFFFFFU ,0x00040073U); - /*############################################################################################################################ */ - - - return 1; + return 1; } -unsigned long psu_mio_init_data() { - // : MIO PROGRAMMING - /*Register : MIO_PIN_0 @ 0XFF180000

+unsigned long psu_ddr_qos_init_data(void) +{ - Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out- (QSPI Clock) - PSU_IOU_SLCR_MIO_PIN_0_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_0_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[0]- (Test Scan Port) = test_scan, Outp - t, test_scan_out[0]- (Test Scan Port) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_0_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[0]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[0]- (GPIO bank 0) 1= can - , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa - ) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Cloc - ) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_ - lk- (Trace Port Clock) - PSU_IOU_SLCR_MIO_PIN_0_L3_SEL 0 - - Configures MIO Pin 0 peripheral interface mapping. S - (OFFSET, MASK, VALUE) (0XFF180000, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_0_L0_SEL_MASK | IOU_SLCR_MIO_PIN_0_L1_SEL_MASK | IOU_SLCR_MIO_PIN_0_L2_SEL_MASK | IOU_SLCR_MIO_PIN_0_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_0_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_0_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_0_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_0_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_0_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_1 @ 0XFF180004

- - Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (QSPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Data - us) - PSU_IOU_SLCR_MIO_PIN_1_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_1_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[1]- (Test Scan Port) = test_scan, Outp - t, test_scan_out[1]- (Test Scan Port) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_1_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[1]- (GPIO bank 0) 1= can - , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal - 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_o - t- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control - Signal) - PSU_IOU_SLCR_MIO_PIN_1_L3_SEL 0 - - Configures MIO Pin 1 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180004, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_1_L0_SEL_MASK | IOU_SLCR_MIO_PIN_1_L1_SEL_MASK | IOU_SLCR_MIO_PIN_1_L2_SEL_MASK | IOU_SLCR_MIO_PIN_1_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_1_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_1_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_1_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_1_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_1_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_2 @ 0XFF180008

- - Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus) - PSU_IOU_SLCR_MIO_PIN_2_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_2_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[2]- (Test Scan Port) = test_scan, Outp - t, test_scan_out[2]- (Test Scan Port) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_2_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[2]- (GPIO bank 0) 1= can - , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal - 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc2, Input, ttc2_clk_in - (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[0]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_2_L3_SEL 0 - - Configures MIO Pin 2 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180008, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_2_L0_SEL_MASK | IOU_SLCR_MIO_PIN_2_L1_SEL_MASK | IOU_SLCR_MIO_PIN_2_L2_SEL_MASK | IOU_SLCR_MIO_PIN_2_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_2_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_2_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_2_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_2_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_2_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_3 @ 0XFF18000C

- - Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus) - PSU_IOU_SLCR_MIO_PIN_3_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_3_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[3]- (Test Scan Port) = test_scan, Outp - t, test_scan_out[3]- (Test Scan Port) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_3_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[3]- (GPIO bank 0) 1= can - , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa - ) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0 - - (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial - output) 7= trace, Output, tracedq[1]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_3_L3_SEL 0 - - Configures MIO Pin 3 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF18000C, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_3_L0_SEL_MASK | IOU_SLCR_MIO_PIN_3_L1_SEL_MASK | IOU_SLCR_MIO_PIN_3_L2_SEL_MASK | IOU_SLCR_MIO_PIN_3_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_3_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_3_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_3_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_3_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_3_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_4 @ 0XFF180010

- - Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- (QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Data - us) - PSU_IOU_SLCR_MIO_PIN_4_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_4_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[4]- (Test Scan Port) = test_scan, Outp - t, test_scan_out[4]- (Test Scan Port) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_4_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[4]- (GPIO bank 0) 1= can - , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa - ) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_s - - (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, - utput, tracedq[2]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_4_L3_SEL 0 - - Configures MIO Pin 4 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180010, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_4_L0_SEL_MASK | IOU_SLCR_MIO_PIN_4_L1_SEL_MASK | IOU_SLCR_MIO_PIN_4_L2_SEL_MASK | IOU_SLCR_MIO_PIN_4_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_4_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_4_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_4_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_4_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_4_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_5 @ 0XFF180014

- - Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out- (QSPI Slave Select) - PSU_IOU_SLCR_MIO_PIN_5_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_5_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[5]- (Test Scan Port) = test_scan, Outp - t, test_scan_out[5]- (Test Scan Port) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_5_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[5]- (GPIO bank 0) 1= can - , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal - 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi0 - si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7 - trace, Output, tracedq[3]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_5_L3_SEL 0 - - Configures MIO Pin 5 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180014, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_5_L0_SEL_MASK | IOU_SLCR_MIO_PIN_5_L1_SEL_MASK | IOU_SLCR_MIO_PIN_5_L2_SEL_MASK | IOU_SLCR_MIO_PIN_5_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_5_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_5_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_5_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_5_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_5_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_6 @ 0XFF180018

- - Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_clk_for_lpbk- (QSPI Clock to be fed-back) - PSU_IOU_SLCR_MIO_PIN_6_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_6_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[6]- (Test Scan Port) = test_scan, Outp - t, test_scan_out[6]- (Test Scan Port) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_6_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[6]- (GPIO bank 0) 1= can - , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal - 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1 - sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, - Output, tracedq[4]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_6_L3_SEL 0 - - Configures MIO Pin 6 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180018, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_6_L0_SEL_MASK | IOU_SLCR_MIO_PIN_6_L1_SEL_MASK | IOU_SLCR_MIO_PIN_6_L2_SEL_MASK | IOU_SLCR_MIO_PIN_6_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_6_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_6_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_6_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_6_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_6_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_7 @ 0XFF18001C

- - Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out_upper- (QSPI Slave Select upper) - PSU_IOU_SLCR_MIO_PIN_7_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_7_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[7]- (Test Scan Port) = test_scan, Outp - t, test_scan_out[7]- (Test Scan Port) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_7_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[7]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[7]- (GPIO bank 0) 1= can - , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa - ) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= - tc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, - racedq[5]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_7_L3_SEL 0 - - Configures MIO Pin 7 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF18001C, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_7_L0_SEL_MASK | IOU_SLCR_MIO_PIN_7_L1_SEL_MASK | IOU_SLCR_MIO_PIN_7_L2_SEL_MASK | IOU_SLCR_MIO_PIN_7_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_7_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_7_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_7_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_7_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_7_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_8 @ 0XFF180020

- - Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[0]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe - [0]- (QSPI Upper Databus) - PSU_IOU_SLCR_MIO_PIN_8_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_8_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[8]- (Test Scan Port) = test_scan, Outp - t, test_scan_out[8]- (Test Scan Port) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_8_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[8]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[8]- (GPIO bank 0) 1= can - , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa - ) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc - , Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Tr - ce Port Databus) - PSU_IOU_SLCR_MIO_PIN_8_L3_SEL 0 - - Configures MIO Pin 8 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180020, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_8_L0_SEL_MASK | IOU_SLCR_MIO_PIN_8_L1_SEL_MASK | IOU_SLCR_MIO_PIN_8_L2_SEL_MASK | IOU_SLCR_MIO_PIN_8_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_8_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_8_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_8_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_8_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_8_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_9 @ 0XFF180024

- - Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[1]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe - [1]- (QSPI Upper Databus) - PSU_IOU_SLCR_MIO_PIN_9_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NAND chip enable) - PSU_IOU_SLCR_MIO_PIN_9_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[9]- (Test Scan Port) = test_scan, Outp - t, test_scan_out[9]- (Test Scan Port) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_9_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[9]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[9]- (GPIO bank 0) 1= can - , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal - 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, - utput, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (U - RT receiver serial input) 7= trace, Output, tracedq[7]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_9_L3_SEL 0 - - Configures MIO Pin 9 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180024, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_9_L0_SEL_MASK | IOU_SLCR_MIO_PIN_9_L1_SEL_MASK | IOU_SLCR_MIO_PIN_9_L2_SEL_MASK | IOU_SLCR_MIO_PIN_9_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_9_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_9_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_9_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_9_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_9_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_10 @ 0XFF180028

- - Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[2]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe - [2]- (QSPI Upper Databus) - PSU_IOU_SLCR_MIO_PIN_10_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (NAND Ready/Busy) - PSU_IOU_SLCR_MIO_PIN_10_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[10]- (Test Scan Port) = test_scan, Out - ut, test_scan_out[10]- (Test Scan Port) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_10_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[10]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[10]- (GPIO bank 0) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_ - o- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outp - t, tracedq[8]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_10_L3_SEL 0 - - Configures MIO Pin 10 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180028, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_10_L0_SEL_MASK | IOU_SLCR_MIO_PIN_10_L1_SEL_MASK | IOU_SLCR_MIO_PIN_10_L2_SEL_MASK | IOU_SLCR_MIO_PIN_10_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_10_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_10_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_10_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_10_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_10_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_11 @ 0XFF18002C

- - Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[3]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe - [3]- (QSPI Upper Databus) - PSU_IOU_SLCR_MIO_PIN_11_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (NAND Ready/Busy) - PSU_IOU_SLCR_MIO_PIN_11_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[11]- (Test Scan Port) = test_scan, Out - ut, test_scan_out[11]- (Test Scan Port) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_11_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s - i1_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o - tput) 7= trace, Output, tracedq[9]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_11_L3_SEL 0 - - Configures MIO Pin 11 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF18002C, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_11_L0_SEL_MASK | IOU_SLCR_MIO_PIN_11_L1_SEL_MASK | IOU_SLCR_MIO_PIN_11_L2_SEL_MASK | IOU_SLCR_MIO_PIN_11_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_11_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_11_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_11_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_11_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_11_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_12 @ 0XFF180030

- - Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out_upper- (QSPI Upper Clock) - PSU_IOU_SLCR_MIO_PIN_12_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NAND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe - - PSU_IOU_SLCR_MIO_PIN_12_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[12]- (Test Scan Port) = test_scan, Out - ut, test_scan_out[12]- (Test Scan Port) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_12_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[12]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[12]- (GPIO bank 0) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Cl - ck) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trac - dq[10]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_12_L3_SEL 0 - - Configures MIO Pin 12 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180030, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_12_L0_SEL_MASK | IOU_SLCR_MIO_PIN_12_L1_SEL_MASK | IOU_SLCR_MIO_PIN_12_L2_SEL_MASK | IOU_SLCR_MIO_PIN_12_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_12_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_12_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_12_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_12_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_12_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_13 @ 0XFF180034

- - Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_13_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[0]- (NAND chip enable) - PSU_IOU_SLCR_MIO_PIN_13_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8 - bit Data bus) 2= test_scan, Input, test_scan_in[13]- (Test Scan Port) = test_scan, Output, test_scan_out[13]- (Test Scan Port - 3= Not Used - PSU_IOU_SLCR_MIO_PIN_13_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[13]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[13]- (GPIO bank 0) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave - out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq[11]- (Trace Port Dat - bus) - PSU_IOU_SLCR_MIO_PIN_13_L3_SEL 0 - - Configures MIO Pin 13 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180034, 0x000000FEU ,0x00000000U) - RegMask = (IOU_SLCR_MIO_PIN_13_L0_SEL_MASK | IOU_SLCR_MIO_PIN_13_L1_SEL_MASK | IOU_SLCR_MIO_PIN_13_L2_SEL_MASK | IOU_SLCR_MIO_PIN_13_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_13_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_13_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_13_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_13_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_13_OFFSET ,0x000000FEU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_14 @ 0XFF180038

- - Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_14_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_cle- (NAND Command Latch Enable) - PSU_IOU_SLCR_MIO_PIN_14_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8 - bit Data bus) 2= test_scan, Input, test_scan_in[14]- (Test Scan Port) = test_scan, Output, test_scan_out[14]- (Test Scan Port - 3= Not Used - PSU_IOU_SLCR_MIO_PIN_14_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, Input, ttc0_clk_ - n- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_14_L3_SEL 2 - - Configures MIO Pin 14 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180038, 0x000000FEU ,0x00000040U) - RegMask = (IOU_SLCR_MIO_PIN_14_L0_SEL_MASK | IOU_SLCR_MIO_PIN_14_L1_SEL_MASK | IOU_SLCR_MIO_PIN_14_L2_SEL_MASK | IOU_SLCR_MIO_PIN_14_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_14_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_14_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_14_L2_SEL_SHIFT - | 0x00000002U << IOU_SLCR_MIO_PIN_14_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_14_OFFSET ,0x000000FEU ,0x00000040U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_15 @ 0XFF18003C

- - Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_15_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ale- (NAND Address Latch Enable) - PSU_IOU_SLCR_MIO_PIN_15_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8 - bit Data bus) 2= test_scan, Input, test_scan_in[15]- (Test Scan Port) = test_scan, Output, test_scan_out[15]- (Test Scan Port - 3= Not Used - PSU_IOU_SLCR_MIO_PIN_15_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[15]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[15]- (GPIO bank 0) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out - 0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter seri - l output) 7= trace, Output, tracedq[13]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_15_L3_SEL 2 - - Configures MIO Pin 15 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF18003C, 0x000000FEU ,0x00000040U) - RegMask = (IOU_SLCR_MIO_PIN_15_L0_SEL_MASK | IOU_SLCR_MIO_PIN_15_L1_SEL_MASK | IOU_SLCR_MIO_PIN_15_L2_SEL_MASK | IOU_SLCR_MIO_PIN_15_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_15_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_15_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_15_L2_SEL_SHIFT - | 0x00000002U << IOU_SLCR_MIO_PIN_15_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_15_OFFSET ,0x000000FEU ,0x00000040U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_16 @ 0XFF180040

- - Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_16_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[0]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[0]- (NAND - ata Bus) - PSU_IOU_SLCR_MIO_PIN_16_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8 - bit Data bus) 2= test_scan, Input, test_scan_in[16]- (Test Scan Port) = test_scan, Output, test_scan_out[16]- (Test Scan Port - 3= Not Used - PSU_IOU_SLCR_MIO_PIN_16_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[16]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[16]- (GPIO bank 0) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0 - so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace - Output, tracedq[14]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_16_L3_SEL 2 - - Configures MIO Pin 16 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180040, 0x000000FEU ,0x00000040U) - RegMask = (IOU_SLCR_MIO_PIN_16_L0_SEL_MASK | IOU_SLCR_MIO_PIN_16_L1_SEL_MASK | IOU_SLCR_MIO_PIN_16_L2_SEL_MASK | IOU_SLCR_MIO_PIN_16_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_16_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_16_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_16_L2_SEL_SHIFT - | 0x00000002U << IOU_SLCR_MIO_PIN_16_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_16_OFFSET ,0x000000FEU ,0x00000040U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_17 @ 0XFF180044

- - Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_17_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[1]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[1]- (NAND - ata Bus) - PSU_IOU_SLCR_MIO_PIN_17_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8 - bit Data bus) 2= test_scan, Input, test_scan_in[17]- (Test Scan Port) = test_scan, Output, test_scan_out[17]- (Test Scan Port - 3= Not Used - PSU_IOU_SLCR_MIO_PIN_17_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[17]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[17]- (GPIO bank 0) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, sp - 0_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) - 7= trace, Output, tracedq[15]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_17_L3_SEL 2 - - Configures MIO Pin 17 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180044, 0x000000FEU ,0x00000040U) - RegMask = (IOU_SLCR_MIO_PIN_17_L0_SEL_MASK | IOU_SLCR_MIO_PIN_17_L1_SEL_MASK | IOU_SLCR_MIO_PIN_17_L2_SEL_MASK | IOU_SLCR_MIO_PIN_17_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_17_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_17_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_17_L2_SEL_SHIFT - | 0x00000002U << IOU_SLCR_MIO_PIN_17_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_17_OFFSET ,0x000000FEU ,0x00000040U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_18 @ 0XFF180048

- - Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_18_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[2]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[2]- (NAND - ata Bus) - PSU_IOU_SLCR_MIO_PIN_18_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8 - bit Data bus) 2= test_scan, Input, test_scan_in[18]- (Test Scan Port) = test_scan, Output, test_scan_out[18]- (Test Scan Port - 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper) - PSU_IOU_SLCR_MIO_PIN_18_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[18]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[18]- (GPIO bank 0) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_ - o- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used - PSU_IOU_SLCR_MIO_PIN_18_L3_SEL 6 - - Configures MIO Pin 18 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180048, 0x000000FEU ,0x000000C0U) - RegMask = (IOU_SLCR_MIO_PIN_18_L0_SEL_MASK | IOU_SLCR_MIO_PIN_18_L1_SEL_MASK | IOU_SLCR_MIO_PIN_18_L2_SEL_MASK | IOU_SLCR_MIO_PIN_18_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_18_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_18_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_18_L2_SEL_SHIFT - | 0x00000006U << IOU_SLCR_MIO_PIN_18_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_18_OFFSET ,0x000000FEU ,0x000000C0U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_19 @ 0XFF18004C

- - Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_19_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[3]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[3]- (NAND - ata Bus) - PSU_IOU_SLCR_MIO_PIN_19_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8 - bit Data bus) 2= test_scan, Input, test_scan_in[19]- (Test Scan Port) = test_scan, Output, test_scan_out[19]- (Test Scan Port - 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper) - PSU_IOU_SLCR_MIO_PIN_19_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[19]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[19]- (GPIO bank 0) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5 - ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used - PSU_IOU_SLCR_MIO_PIN_19_L3_SEL 6 - - Configures MIO Pin 19 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF18004C, 0x000000FEU ,0x000000C0U) - RegMask = (IOU_SLCR_MIO_PIN_19_L0_SEL_MASK | IOU_SLCR_MIO_PIN_19_L1_SEL_MASK | IOU_SLCR_MIO_PIN_19_L2_SEL_MASK | IOU_SLCR_MIO_PIN_19_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_19_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_19_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_19_L2_SEL_SHIFT - | 0x00000006U << IOU_SLCR_MIO_PIN_19_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_19_OFFSET ,0x000000FEU ,0x000000C0U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_20 @ 0XFF180050

- - Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_20_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[4]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[4]- (NAND - ata Bus) - PSU_IOU_SLCR_MIO_PIN_20_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8 - bit Data bus) 2= test_scan, Input, test_scan_in[20]- (Test Scan Port) = test_scan, Output, test_scan_out[20]- (Test Scan Port - 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper) - PSU_IOU_SLCR_MIO_PIN_20_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[20]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[20]- (GPIO bank 0) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= t - c1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Used - PSU_IOU_SLCR_MIO_PIN_20_L3_SEL 6 - - Configures MIO Pin 20 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180050, 0x000000FEU ,0x000000C0U) - RegMask = (IOU_SLCR_MIO_PIN_20_L0_SEL_MASK | IOU_SLCR_MIO_PIN_20_L1_SEL_MASK | IOU_SLCR_MIO_PIN_20_L2_SEL_MASK | IOU_SLCR_MIO_PIN_20_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_20_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_20_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_20_L2_SEL_SHIFT - | 0x00000006U << IOU_SLCR_MIO_PIN_20_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_20_OFFSET ,0x000000FEU ,0x000000C0U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_21 @ 0XFF180054

- - Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_21_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[5]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[5]- (NAND - ata Bus) - PSU_IOU_SLCR_MIO_PIN_21_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Comman - Indicator) 2= test_scan, Input, test_scan_in[21]- (Test Scan Port) = test_scan, Output, test_scan_out[21]- (Test Scan Port) - = csu, Input, csu_ext_tamper- (CSU Ext Tamper) - PSU_IOU_SLCR_MIO_PIN_21_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[21]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[21]- (GPIO bank 0) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1 - Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- - UART receiver serial input) 7= Not Used - PSU_IOU_SLCR_MIO_PIN_21_L3_SEL 6 - - Configures MIO Pin 21 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180054, 0x000000FEU ,0x000000C0U) - RegMask = (IOU_SLCR_MIO_PIN_21_L0_SEL_MASK | IOU_SLCR_MIO_PIN_21_L1_SEL_MASK | IOU_SLCR_MIO_PIN_21_L2_SEL_MASK | IOU_SLCR_MIO_PIN_21_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_21_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_21_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_21_L2_SEL_SHIFT - | 0x00000006U << IOU_SLCR_MIO_PIN_21_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_21_OFFSET ,0x000000FEU ,0x000000C0U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_22 @ 0XFF180058

- - Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_22_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_we_b- (NAND Write Enable) - PSU_IOU_SLCR_MIO_PIN_22_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= test_scan, Input, test_scan_in[22]- - (Test Scan Port) = test_scan, Output, test_scan_out[22]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper) - PSU_IOU_SLCR_MIO_PIN_22_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[22]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[22]- (GPIO bank 0) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, sp - 1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not - sed - PSU_IOU_SLCR_MIO_PIN_22_L3_SEL 0 - - Configures MIO Pin 22 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180058, 0x000000FEU ,0x00000000U) - RegMask = (IOU_SLCR_MIO_PIN_22_L0_SEL_MASK | IOU_SLCR_MIO_PIN_22_L1_SEL_MASK | IOU_SLCR_MIO_PIN_22_L2_SEL_MASK | IOU_SLCR_MIO_PIN_22_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_22_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_22_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_22_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_22_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_22_OFFSET ,0x000000FEU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_23 @ 0XFF18005C

- - Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_23_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[6]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[6]- (NAND - ata Bus) - PSU_IOU_SLCR_MIO_PIN_23_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= test_scan, Input, test_scan_in - 23]- (Test Scan Port) = test_scan, Output, test_scan_out[23]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper - - PSU_IOU_SLCR_MIO_PIN_23_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[23]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[23]- (GPIO bank 0) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s - i1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o - tput) 7= Not Used - PSU_IOU_SLCR_MIO_PIN_23_L3_SEL 0 - - Configures MIO Pin 23 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF18005C, 0x000000FEU ,0x00000000U) - RegMask = (IOU_SLCR_MIO_PIN_23_L0_SEL_MASK | IOU_SLCR_MIO_PIN_23_L1_SEL_MASK | IOU_SLCR_MIO_PIN_23_L2_SEL_MASK | IOU_SLCR_MIO_PIN_23_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_23_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_23_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_23_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_23_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_23_OFFSET ,0x000000FEU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_24 @ 0XFF180060

- - Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_24_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[7]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[7]- (NAND - ata Bus) - PSU_IOU_SLCR_MIO_PIN_24_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= test_scan, Input, test - scan_in[24]- (Test Scan Port) = test_scan, Output, test_scan_out[24]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ex - Tamper) - PSU_IOU_SLCR_MIO_PIN_24_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[24]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[24]- (GPIO bank 0) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= Not Used 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, - Output, ua1_txd- (UART transmitter serial output) 7= Not Used - PSU_IOU_SLCR_MIO_PIN_24_L3_SEL 1 - - Configures MIO Pin 24 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180060, 0x000000FEU ,0x00000020U) - RegMask = (IOU_SLCR_MIO_PIN_24_L0_SEL_MASK | IOU_SLCR_MIO_PIN_24_L1_SEL_MASK | IOU_SLCR_MIO_PIN_24_L2_SEL_MASK | IOU_SLCR_MIO_PIN_24_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_24_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_24_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_24_L2_SEL_SHIFT - | 0x00000001U << IOU_SLCR_MIO_PIN_24_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_24_OFFSET ,0x000000FEU ,0x00000020U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_25 @ 0XFF180064

- - Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_25_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_re_n- (NAND Read Enable) - PSU_IOU_SLCR_MIO_PIN_25_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= test_scan, Input, - test_scan_in[25]- (Test Scan Port) = test_scan, Output, test_scan_out[25]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (C - U Ext Tamper) - PSU_IOU_SLCR_MIO_PIN_25_L2_SEL 0 - - Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[25]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[25]- (GPIO bank 0) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= Not Used 5= ttc3, Output, ttc3_wave_out- (TTC Waveform - lock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used - PSU_IOU_SLCR_MIO_PIN_25_L3_SEL 1 - - Configures MIO Pin 25 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180064, 0x000000FEU ,0x00000020U) - RegMask = (IOU_SLCR_MIO_PIN_25_L0_SEL_MASK | IOU_SLCR_MIO_PIN_25_L1_SEL_MASK | IOU_SLCR_MIO_PIN_25_L2_SEL_MASK | IOU_SLCR_MIO_PIN_25_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_25_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_25_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_25_L2_SEL_SHIFT - | 0x00000001U << IOU_SLCR_MIO_PIN_25_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_25_OFFSET ,0x000000FEU ,0x00000020U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_26 @ 0XFF180068

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_clk- (TX RGMII clock) - PSU_IOU_SLCR_MIO_PIN_26_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NAND chip enable) - PSU_IOU_SLCR_MIO_PIN_26_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[0]- (PMU GPI) 2= test_scan, Input, test_scan_in[26]- (Test Sc - n Port) = test_scan, Output, test_scan_out[26]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper) - PSU_IOU_SLCR_MIO_PIN_26_L2_SEL 0 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[0]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[0]- (GPIO bank 1) 1= can - , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal - 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Clock - 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- - Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_26_L3_SEL 0 - - Configures MIO Pin 26 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180068, 0x000000FEU ,0x00000000U) - RegMask = (IOU_SLCR_MIO_PIN_26_L0_SEL_MASK | IOU_SLCR_MIO_PIN_26_L1_SEL_MASK | IOU_SLCR_MIO_PIN_26_L2_SEL_MASK | IOU_SLCR_MIO_PIN_26_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_26_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_26_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_26_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_26_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_26_OFFSET ,0x000000FEU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_27 @ 0XFF18006C

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[0]- (TX RGMII data) - PSU_IOU_SLCR_MIO_PIN_27_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (NAND Ready/Busy) - PSU_IOU_SLCR_MIO_PIN_27_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[1]- (PMU GPI) 2= test_scan, Input, test_scan_in[27]- (Test Sc - n Port) = test_scan, Output, test_scan_out[27]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Outp - t, dp_aux_data_out- (Dp Aux Data) - PSU_IOU_SLCR_MIO_PIN_27_L2_SEL 3 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[1]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[1]- (GPIO bank 1) 1= can - , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa - ) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_ - ut- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port - atabus) - PSU_IOU_SLCR_MIO_PIN_27_L3_SEL 0 - - Configures MIO Pin 27 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF18006C, 0x000000FEU ,0x00000018U) - RegMask = (IOU_SLCR_MIO_PIN_27_L0_SEL_MASK | IOU_SLCR_MIO_PIN_27_L1_SEL_MASK | IOU_SLCR_MIO_PIN_27_L2_SEL_MASK | IOU_SLCR_MIO_PIN_27_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_27_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_27_L1_SEL_SHIFT - | 0x00000003U << IOU_SLCR_MIO_PIN_27_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_27_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_27_OFFSET ,0x000000FEU ,0x00000018U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_28 @ 0XFF180070

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[1]- (TX RGMII data) - PSU_IOU_SLCR_MIO_PIN_28_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (NAND Ready/Busy) - PSU_IOU_SLCR_MIO_PIN_28_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[2]- (PMU GPI) 2= test_scan, Input, test_scan_in[28]- (Test Sc - n Port) = test_scan, Output, test_scan_out[28]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug) - PSU_IOU_SLCR_MIO_PIN_28_L2_SEL 3 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[2]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[2]- (GPIO bank 1) 1= can - , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa - ) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc1, Input, ttc1_clk_i - - (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_28_L3_SEL 0 - - Configures MIO Pin 28 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180070, 0x000000FEU ,0x00000018U) - RegMask = (IOU_SLCR_MIO_PIN_28_L0_SEL_MASK | IOU_SLCR_MIO_PIN_28_L1_SEL_MASK | IOU_SLCR_MIO_PIN_28_L2_SEL_MASK | IOU_SLCR_MIO_PIN_28_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_28_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_28_L1_SEL_SHIFT - | 0x00000003U << IOU_SLCR_MIO_PIN_28_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_28_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_28_OFFSET ,0x000000FEU ,0x00000018U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_29 @ 0XFF180074

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[2]- (TX RGMII data) - PSU_IOU_SLCR_MIO_PIN_29_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal) - PSU_IOU_SLCR_MIO_PIN_29_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[3]- (PMU GPI) 2= test_scan, Input, test_scan_in[29]- (Test Sc - n Port) = test_scan, Output, test_scan_out[29]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Outp - t, dp_aux_data_out- (Dp Aux Data) - PSU_IOU_SLCR_MIO_PIN_29_L2_SEL 3 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[3]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[3]- (GPIO bank 1) 1= can - , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal - 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0] - (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial inpu - ) 7= trace, Output, tracedq[7]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_29_L3_SEL 0 - - Configures MIO Pin 29 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180074, 0x000000FEU ,0x00000018U) - RegMask = (IOU_SLCR_MIO_PIN_29_L0_SEL_MASK | IOU_SLCR_MIO_PIN_29_L1_SEL_MASK | IOU_SLCR_MIO_PIN_29_L2_SEL_MASK | IOU_SLCR_MIO_PIN_29_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_29_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_29_L1_SEL_SHIFT - | 0x00000003U << IOU_SLCR_MIO_PIN_29_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_29_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_29_OFFSET ,0x000000FEU ,0x00000018U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_30 @ 0XFF180078

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[3]- (TX RGMII data) - PSU_IOU_SLCR_MIO_PIN_30_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal) - PSU_IOU_SLCR_MIO_PIN_30_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[4]- (PMU GPI) 2= test_scan, Input, test_scan_in[30]- (Test Sc - n Port) = test_scan, Output, test_scan_out[30]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug) - PSU_IOU_SLCR_MIO_PIN_30_L2_SEL 3 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[4]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[4]- (GPIO bank 1) 1= can - , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal - 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_so - (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output - tracedq[8]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_30_L3_SEL 0 - - Configures MIO Pin 30 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180078, 0x000000FEU ,0x00000018U) - RegMask = (IOU_SLCR_MIO_PIN_30_L0_SEL_MASK | IOU_SLCR_MIO_PIN_30_L1_SEL_MASK | IOU_SLCR_MIO_PIN_30_L2_SEL_MASK | IOU_SLCR_MIO_PIN_30_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_30_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_30_L1_SEL_SHIFT - | 0x00000003U << IOU_SLCR_MIO_PIN_30_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_30_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_30_OFFSET ,0x000000FEU ,0x00000018U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_31 @ 0XFF18007C

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ctl- (TX RGMII control) - PSU_IOU_SLCR_MIO_PIN_31_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal) - PSU_IOU_SLCR_MIO_PIN_31_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[5]- (PMU GPI) 2= test_scan, Input, test_scan_in[31]- (Test Sc - n Port) = test_scan, Output, test_scan_out[31]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper) - PSU_IOU_SLCR_MIO_PIN_31_L2_SEL 0 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[5]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[5]- (GPIO bank 1) 1= can - , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa - ) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi - _si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial out - ut) 7= trace, Output, tracedq[9]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_31_L3_SEL 0 - - Configures MIO Pin 31 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF18007C, 0x000000FEU ,0x00000000U) - RegMask = (IOU_SLCR_MIO_PIN_31_L0_SEL_MASK | IOU_SLCR_MIO_PIN_31_L1_SEL_MASK | IOU_SLCR_MIO_PIN_31_L2_SEL_MASK | IOU_SLCR_MIO_PIN_31_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_31_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_31_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_31_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_31_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_31_OFFSET ,0x000000FEU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_32 @ 0XFF180080

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_clk- (RX RGMII clock) - PSU_IOU_SLCR_MIO_PIN_32_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NAND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe - - PSU_IOU_SLCR_MIO_PIN_32_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[0]- (PMU GPI) 2= test_scan, Input, test_scan_in[32]- (Test S - an Port) = test_scan, Output, test_scan_out[32]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper) - PSU_IOU_SLCR_MIO_PIN_32_L2_SEL 1 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[6]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[6]- (GPIO bank 1) 1= can - , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa - ) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi - _sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= - race, Output, tracedq[10]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_32_L3_SEL 0 - - Configures MIO Pin 32 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180080, 0x000000FEU ,0x00000008U) - RegMask = (IOU_SLCR_MIO_PIN_32_L0_SEL_MASK | IOU_SLCR_MIO_PIN_32_L1_SEL_MASK | IOU_SLCR_MIO_PIN_32_L2_SEL_MASK | IOU_SLCR_MIO_PIN_32_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_32_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_32_L1_SEL_SHIFT - | 0x00000001U << IOU_SLCR_MIO_PIN_32_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_32_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_32_OFFSET ,0x000000FEU ,0x00000008U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_33 @ 0XFF180084

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[0]- (RX RGMII data) - PSU_IOU_SLCR_MIO_PIN_33_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal) - PSU_IOU_SLCR_MIO_PIN_33_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[1]- (PMU GPI) 2= test_scan, Input, test_scan_in[33]- (Test S - an Port) = test_scan, Output, test_scan_out[33]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper) - PSU_IOU_SLCR_MIO_PIN_33_L2_SEL 1 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[7]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[7]- (GPIO bank 1) 1= can - , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal - 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= t - c3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, traced - [11]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_33_L3_SEL 0 - - Configures MIO Pin 33 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180084, 0x000000FEU ,0x00000008U) - RegMask = (IOU_SLCR_MIO_PIN_33_L0_SEL_MASK | IOU_SLCR_MIO_PIN_33_L1_SEL_MASK | IOU_SLCR_MIO_PIN_33_L2_SEL_MASK | IOU_SLCR_MIO_PIN_33_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_33_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_33_L1_SEL_SHIFT - | 0x00000001U << IOU_SLCR_MIO_PIN_33_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_33_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_33_OFFSET ,0x000000FEU ,0x00000008U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_34 @ 0XFF180088

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[1]- (RX RGMII data) - PSU_IOU_SLCR_MIO_PIN_34_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal) - PSU_IOU_SLCR_MIO_PIN_34_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[2]- (PMU GPI) 2= test_scan, Input, test_scan_in[34]- (Test S - an Port) = test_scan, Output, test_scan_out[34]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Out - ut, dp_aux_data_out- (Dp Aux Data) - PSU_IOU_SLCR_MIO_PIN_34_L2_SEL 1 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[8]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[8]- (GPIO bank 1) 1= can - , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal - 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc2 - Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace P - rt Databus) - PSU_IOU_SLCR_MIO_PIN_34_L3_SEL 0 - - Configures MIO Pin 34 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180088, 0x000000FEU ,0x00000008U) - RegMask = (IOU_SLCR_MIO_PIN_34_L0_SEL_MASK | IOU_SLCR_MIO_PIN_34_L1_SEL_MASK | IOU_SLCR_MIO_PIN_34_L2_SEL_MASK | IOU_SLCR_MIO_PIN_34_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_34_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_34_L1_SEL_SHIFT - | 0x00000001U << IOU_SLCR_MIO_PIN_34_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_34_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_34_OFFSET ,0x000000FEU ,0x00000008U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_35 @ 0XFF18008C

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[2]- (RX RGMII data) - PSU_IOU_SLCR_MIO_PIN_35_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal) - PSU_IOU_SLCR_MIO_PIN_35_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[3]- (PMU GPI) 2= test_scan, Input, test_scan_in[35]- (Test S - an Port) = test_scan, Output, test_scan_out[35]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug) - PSU_IOU_SLCR_MIO_PIN_35_L2_SEL 1 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[9]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[9]- (GPIO bank 1) 1= can - , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa - ) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, - Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- - UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_35_L3_SEL 0 - - Configures MIO Pin 35 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF18008C, 0x000000FEU ,0x00000008U) - RegMask = (IOU_SLCR_MIO_PIN_35_L0_SEL_MASK | IOU_SLCR_MIO_PIN_35_L1_SEL_MASK | IOU_SLCR_MIO_PIN_35_L2_SEL_MASK | IOU_SLCR_MIO_PIN_35_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_35_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_35_L1_SEL_SHIFT - | 0x00000001U << IOU_SLCR_MIO_PIN_35_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_35_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_35_OFFSET ,0x000000FEU ,0x00000008U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_36 @ 0XFF180090

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[3]- (RX RGMII data) - PSU_IOU_SLCR_MIO_PIN_36_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal) - PSU_IOU_SLCR_MIO_PIN_36_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[4]- (PMU GPI) 2= test_scan, Input, test_scan_in[36]- (Test S - an Port) = test_scan, Output, test_scan_out[36]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Out - ut, dp_aux_data_out- (Dp Aux Data) - PSU_IOU_SLCR_MIO_PIN_36_L2_SEL 1 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[10]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[10]- (GPIO bank 1) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1 - so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace - Output, tracedq[14]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_36_L3_SEL 0 - - Configures MIO Pin 36 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180090, 0x000000FEU ,0x00000008U) - RegMask = (IOU_SLCR_MIO_PIN_36_L0_SEL_MASK | IOU_SLCR_MIO_PIN_36_L1_SEL_MASK | IOU_SLCR_MIO_PIN_36_L2_SEL_MASK | IOU_SLCR_MIO_PIN_36_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_36_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_36_L1_SEL_SHIFT - | 0x00000001U << IOU_SLCR_MIO_PIN_36_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_36_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_36_OFFSET ,0x000000FEU ,0x00000008U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_37 @ 0XFF180094

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_ctl- (RX RGMII control ) - PSU_IOU_SLCR_MIO_PIN_37_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal) - PSU_IOU_SLCR_MIO_PIN_37_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[5]- (PMU GPI) 2= test_scan, Input, test_scan_in[37]- (Test S - an Port) = test_scan, Output, test_scan_out[37]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug) - PSU_IOU_SLCR_MIO_PIN_37_L2_SEL 1 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[11]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[11]- (GPIO bank 1) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, sp - 1_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) - 7= trace, Output, tracedq[15]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_37_L3_SEL 0 - - Configures MIO Pin 37 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180094, 0x000000FEU ,0x00000008U) - RegMask = (IOU_SLCR_MIO_PIN_37_L0_SEL_MASK | IOU_SLCR_MIO_PIN_37_L1_SEL_MASK | IOU_SLCR_MIO_PIN_37_L2_SEL_MASK | IOU_SLCR_MIO_PIN_37_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_37_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_37_L1_SEL_SHIFT - | 0x00000001U << IOU_SLCR_MIO_PIN_37_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_37_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_37_OFFSET ,0x000000FEU ,0x00000008U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_38 @ 0XFF180098

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_clk- (TX RGMII clock) - PSU_IOU_SLCR_MIO_PIN_38_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_38_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= Not Used 3= Not Used - PSU_IOU_SLCR_MIO_PIN_38_L2_SEL 0 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[12]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[12]- (GPIO bank 1) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Clo - k) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, trace_clk- - (Trace Port Clock) - PSU_IOU_SLCR_MIO_PIN_38_L3_SEL 0 - - Configures MIO Pin 38 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180098, 0x000000FEU ,0x00000000U) - RegMask = (IOU_SLCR_MIO_PIN_38_L0_SEL_MASK | IOU_SLCR_MIO_PIN_38_L1_SEL_MASK | IOU_SLCR_MIO_PIN_38_L2_SEL_MASK | IOU_SLCR_MIO_PIN_38_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_38_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_38_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_38_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_38_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_38_OFFSET ,0x000000FEU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_39 @ 0XFF18009C

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[0]- (TX RGMII data) - PSU_IOU_SLCR_MIO_PIN_39_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_39_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= sd1, Input, sd1_data_i - [4]- (8-bit Data bus) = sd1, Output, sdio1_data_out[4]- (8-bit Data bus) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_39_L2_SEL 0 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[13]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[13]- (GPIO bank 1) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc0, Output, ttc0_wav - _out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, trace_ctl- (Trace Port - Control Signal) - PSU_IOU_SLCR_MIO_PIN_39_L3_SEL 0 - - Configures MIO Pin 39 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF18009C, 0x000000FEU ,0x00000000U) - RegMask = (IOU_SLCR_MIO_PIN_39_L0_SEL_MASK | IOU_SLCR_MIO_PIN_39_L1_SEL_MASK | IOU_SLCR_MIO_PIN_39_L2_SEL_MASK | IOU_SLCR_MIO_PIN_39_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_39_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_39_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_39_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_39_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_39_OFFSET ,0x000000FEU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_40 @ 0XFF1800A0

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[1]- (TX RGMII data) - PSU_IOU_SLCR_MIO_PIN_40_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_40_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Comman - Indicator) 2= sd1, Input, sd1_data_in[5]- (8-bit Data bus) = sd1, Output, sdio1_data_out[5]- (8-bit Data bus) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_40_L2_SEL 0 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[14]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[14]- (GPIO bank 1) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc3, Input, ttc3_clk - in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[0]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_40_L3_SEL 0 - - Configures MIO Pin 40 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800A0, 0x000000FEU ,0x00000000U) - RegMask = (IOU_SLCR_MIO_PIN_40_L0_SEL_MASK | IOU_SLCR_MIO_PIN_40_L1_SEL_MASK | IOU_SLCR_MIO_PIN_40_L2_SEL_MASK | IOU_SLCR_MIO_PIN_40_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_40_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_40_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_40_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_40_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_40_OFFSET ,0x000000FEU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_41 @ 0XFF1800A4

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[2]- (TX RGMII data) - PSU_IOU_SLCR_MIO_PIN_41_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_41_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8 - bit Data bus) 2= sd1, Input, sd1_data_in[6]- (8-bit Data bus) = sd1, Output, sdio1_data_out[6]- (8-bit Data bus) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_41_L2_SEL 0 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[15]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[15]- (GPIO bank 1) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[ - ]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial in - ut) 7= trace, Output, tracedq[1]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_41_L3_SEL 0 - - Configures MIO Pin 41 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800A4, 0x000000FEU ,0x00000000U) - RegMask = (IOU_SLCR_MIO_PIN_41_L0_SEL_MASK | IOU_SLCR_MIO_PIN_41_L1_SEL_MASK | IOU_SLCR_MIO_PIN_41_L2_SEL_MASK | IOU_SLCR_MIO_PIN_41_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_41_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_41_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_41_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_41_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_41_OFFSET ,0x000000FEU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_42 @ 0XFF1800A8

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[3]- (TX RGMII data) - PSU_IOU_SLCR_MIO_PIN_42_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_42_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8 - bit Data bus) 2= sd1, Input, sd1_data_in[7]- (8-bit Data bus) = sd1, Output, sdio1_data_out[7]- (8-bit Data bus) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_42_L2_SEL 0 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_ - o- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outp - t, tracedq[2]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_42_L3_SEL 0 - - Configures MIO Pin 42 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800A8, 0x000000FEU ,0x00000000U) - RegMask = (IOU_SLCR_MIO_PIN_42_L0_SEL_MASK | IOU_SLCR_MIO_PIN_42_L1_SEL_MASK | IOU_SLCR_MIO_PIN_42_L2_SEL_MASK | IOU_SLCR_MIO_PIN_42_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_42_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_42_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_42_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_42_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_42_OFFSET ,0x000000FEU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_43 @ 0XFF1800AC

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ctl- (TX RGMII control) - PSU_IOU_SLCR_MIO_PIN_43_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_43_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8 - bit Data bus) 2= sd1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_43_L2_SEL 2 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, s - i0_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o - tput) 7= trace, Output, tracedq[3]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_43_L3_SEL 0 - - Configures MIO Pin 43 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800AC, 0x000000FEU ,0x00000010U) - RegMask = (IOU_SLCR_MIO_PIN_43_L0_SEL_MASK | IOU_SLCR_MIO_PIN_43_L1_SEL_MASK | IOU_SLCR_MIO_PIN_43_L2_SEL_MASK | IOU_SLCR_MIO_PIN_43_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_43_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_43_L1_SEL_SHIFT - | 0x00000002U << IOU_SLCR_MIO_PIN_43_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_43_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_43_OFFSET ,0x000000FEU ,0x00000010U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_44 @ 0XFF1800B0

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_clk- (RX RGMII clock) - PSU_IOU_SLCR_MIO_PIN_44_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_44_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8 - bit Data bus) 2= sd1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_44_L2_SEL 2 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[18]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[18]- (GPIO bank 1) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, s - i1_sclk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7 - Not Used - PSU_IOU_SLCR_MIO_PIN_44_L3_SEL 0 - - Configures MIO Pin 44 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800B0, 0x000000FEU ,0x00000010U) - RegMask = (IOU_SLCR_MIO_PIN_44_L0_SEL_MASK | IOU_SLCR_MIO_PIN_44_L1_SEL_MASK | IOU_SLCR_MIO_PIN_44_L2_SEL_MASK | IOU_SLCR_MIO_PIN_44_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_44_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_44_L1_SEL_SHIFT - | 0x00000002U << IOU_SLCR_MIO_PIN_44_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_44_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_44_OFFSET ,0x000000FEU ,0x00000010U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_45 @ 0XFF1800B4

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[0]- (RX RGMII data) - PSU_IOU_SLCR_MIO_PIN_45_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_45_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8 - bit Data bus) 2= sd1, Input, sdio1_cd_n- (SD card detect from connector) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_45_L2_SEL 2 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[19]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[19]- (GPIO bank 1) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= - ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used - PSU_IOU_SLCR_MIO_PIN_45_L3_SEL 0 - - Configures MIO Pin 45 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800B4, 0x000000FEU ,0x00000010U) - RegMask = (IOU_SLCR_MIO_PIN_45_L0_SEL_MASK | IOU_SLCR_MIO_PIN_45_L1_SEL_MASK | IOU_SLCR_MIO_PIN_45_L2_SEL_MASK | IOU_SLCR_MIO_PIN_45_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_45_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_45_L1_SEL_SHIFT - | 0x00000002U << IOU_SLCR_MIO_PIN_45_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_45_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_45_OFFSET ,0x000000FEU ,0x00000010U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_46 @ 0XFF1800B8

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[1]- (RX RGMII data) - PSU_IOU_SLCR_MIO_PIN_46_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_46_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8 - bit Data bus) 2= sd1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_out[0]- (8-bit Data bus) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_46_L2_SEL 2 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= tt - 0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used - PSU_IOU_SLCR_MIO_PIN_46_L3_SEL 0 - - Configures MIO Pin 46 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800B8, 0x000000FEU ,0x00000010U) - RegMask = (IOU_SLCR_MIO_PIN_46_L0_SEL_MASK | IOU_SLCR_MIO_PIN_46_L1_SEL_MASK | IOU_SLCR_MIO_PIN_46_L2_SEL_MASK | IOU_SLCR_MIO_PIN_46_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_46_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_46_L1_SEL_SHIFT - | 0x00000002U << IOU_SLCR_MIO_PIN_46_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_46_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_46_OFFSET ,0x000000FEU ,0x00000010U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_47 @ 0XFF1800BC

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[2]- (RX RGMII data) - PSU_IOU_SLCR_MIO_PIN_47_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_47_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8 - bit Data bus) 2= sd1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_out[1]- (8-bit Data bus) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_47_L2_SEL 2 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi - , Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd - (UART transmitter serial output) 7= Not Used - PSU_IOU_SLCR_MIO_PIN_47_L3_SEL 0 - - Configures MIO Pin 47 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800BC, 0x000000FEU ,0x00000010U) - RegMask = (IOU_SLCR_MIO_PIN_47_L0_SEL_MASK | IOU_SLCR_MIO_PIN_47_L1_SEL_MASK | IOU_SLCR_MIO_PIN_47_L2_SEL_MASK | IOU_SLCR_MIO_PIN_47_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_47_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_47_L1_SEL_SHIFT - | 0x00000002U << IOU_SLCR_MIO_PIN_47_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_47_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_47_OFFSET ,0x000000FEU ,0x00000010U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_48 @ 0XFF1800C0

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[3]- (RX RGMII data) - PSU_IOU_SLCR_MIO_PIN_48_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_48_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8 - bit Data bus) 2= sd1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_out[2]- (8-bit Data bus) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_48_L2_SEL 2 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[22]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[22]- (GPIO bank 1) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1 - so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not U - ed - PSU_IOU_SLCR_MIO_PIN_48_L3_SEL 0 - - Configures MIO Pin 48 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800C0, 0x000000FEU ,0x00000010U) - RegMask = (IOU_SLCR_MIO_PIN_48_L0_SEL_MASK | IOU_SLCR_MIO_PIN_48_L1_SEL_MASK | IOU_SLCR_MIO_PIN_48_L2_SEL_MASK | IOU_SLCR_MIO_PIN_48_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_48_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_48_L1_SEL_SHIFT - | 0x00000002U << IOU_SLCR_MIO_PIN_48_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_48_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_48_OFFSET ,0x000000FEU ,0x00000010U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_49 @ 0XFF1800C4

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_ctl- (RX RGMII control ) - PSU_IOU_SLCR_MIO_PIN_49_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_49_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= sd1, Input, sd1_data_in[3]- (8 - bit Data bus) = sd1, Output, sdio1_data_out[3]- (8-bit Data bus) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_49_L2_SEL 2 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[23]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[23]- (GPIO bank 1) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, sp - 1_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) - 7= Not Used - PSU_IOU_SLCR_MIO_PIN_49_L3_SEL 0 - - Configures MIO Pin 49 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800C4, 0x000000FEU ,0x00000010U) - RegMask = (IOU_SLCR_MIO_PIN_49_L0_SEL_MASK | IOU_SLCR_MIO_PIN_49_L1_SEL_MASK | IOU_SLCR_MIO_PIN_49_L2_SEL_MASK | IOU_SLCR_MIO_PIN_49_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_49_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_49_L1_SEL_SHIFT - | 0x00000002U << IOU_SLCR_MIO_PIN_49_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_49_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_49_OFFSET ,0x000000FEU ,0x00000010U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_50 @ 0XFF1800C8

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- (TSU clock) - PSU_IOU_SLCR_MIO_PIN_50_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_50_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= sd1, Input, sd1_c - d_in- (Command Indicator) = sd1, Output, sdio1_cmd_out- (Command Indicator) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_50_L2_SEL 2 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[24]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[24]- (GPIO bank 1) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= ttc2, Input, ttc2 - clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used - PSU_IOU_SLCR_MIO_PIN_50_L3_SEL 0 - - Configures MIO Pin 50 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800C8, 0x000000FEU ,0x00000010U) - RegMask = (IOU_SLCR_MIO_PIN_50_L0_SEL_MASK | IOU_SLCR_MIO_PIN_50_L1_SEL_MASK | IOU_SLCR_MIO_PIN_50_L2_SEL_MASK | IOU_SLCR_MIO_PIN_50_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_50_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_50_L1_SEL_SHIFT - | 0x00000002U << IOU_SLCR_MIO_PIN_50_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_50_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_50_OFFSET ,0x000000FEU ,0x00000010U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_51 @ 0XFF1800CC

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- (TSU clock) - PSU_IOU_SLCR_MIO_PIN_51_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_51_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Output, sdio1_clk_out- (SDSDIO clock) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_51_L2_SEL 2 - - Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[25]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[25]- (GPIO bank 1) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= mdio1, Input, gem1_mdio_in- (MDIO Data) 4= mdio1, Outp - t, gem1_mdio_out- (MDIO Data) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter - serial output) 7= Not Used - PSU_IOU_SLCR_MIO_PIN_51_L3_SEL 0 - - Configures MIO Pin 51 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800CC, 0x000000FEU ,0x00000010U) - RegMask = (IOU_SLCR_MIO_PIN_51_L0_SEL_MASK | IOU_SLCR_MIO_PIN_51_L1_SEL_MASK | IOU_SLCR_MIO_PIN_51_L2_SEL_MASK | IOU_SLCR_MIO_PIN_51_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_51_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_51_L1_SEL_SHIFT - | 0x00000002U << IOU_SLCR_MIO_PIN_51_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_51_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_51_OFFSET ,0x000000FEU ,0x00000010U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_52 @ 0XFF1800D0

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_clk- (TX RGMII clock) - PSU_IOU_SLCR_MIO_PIN_52_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_clk_in- (ULPI Clock) - PSU_IOU_SLCR_MIO_PIN_52_L1_SEL 1 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used - PSU_IOU_SLCR_MIO_PIN_52_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[0]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[0]- (GPIO bank 2) 1= can - , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa - ) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Cloc - ) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_ - lk- (Trace Port Clock) - PSU_IOU_SLCR_MIO_PIN_52_L3_SEL 0 - - Configures MIO Pin 52 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800D0, 0x000000FEU ,0x00000004U) - RegMask = (IOU_SLCR_MIO_PIN_52_L0_SEL_MASK | IOU_SLCR_MIO_PIN_52_L1_SEL_MASK | IOU_SLCR_MIO_PIN_52_L2_SEL_MASK | IOU_SLCR_MIO_PIN_52_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_52_L0_SEL_SHIFT - | 0x00000001U << IOU_SLCR_MIO_PIN_52_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_52_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_52_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_52_OFFSET ,0x000000FEU ,0x00000004U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_53 @ 0XFF1800D4

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[0]- (TX RGMII data) - PSU_IOU_SLCR_MIO_PIN_53_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_dir- (Data bus direction control) - PSU_IOU_SLCR_MIO_PIN_53_L1_SEL 1 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used - PSU_IOU_SLCR_MIO_PIN_53_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[1]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[1]- (GPIO bank 2) 1= can - , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal - 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_o - t- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control - Signal) - PSU_IOU_SLCR_MIO_PIN_53_L3_SEL 0 - - Configures MIO Pin 53 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800D4, 0x000000FEU ,0x00000004U) - RegMask = (IOU_SLCR_MIO_PIN_53_L0_SEL_MASK | IOU_SLCR_MIO_PIN_53_L1_SEL_MASK | IOU_SLCR_MIO_PIN_53_L2_SEL_MASK | IOU_SLCR_MIO_PIN_53_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_53_L0_SEL_SHIFT - | 0x00000001U << IOU_SLCR_MIO_PIN_53_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_53_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_53_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_53_OFFSET ,0x000000FEU ,0x00000004U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_54 @ 0XFF1800D8

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[1]- (TX RGMII data) - PSU_IOU_SLCR_MIO_PIN_54_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[2]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_ - ata[2]- (ULPI data bus) - PSU_IOU_SLCR_MIO_PIN_54_L1_SEL 1 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used - PSU_IOU_SLCR_MIO_PIN_54_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[2]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[2]- (GPIO bank 2) 1= can - , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal - 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, Input, ttc0_clk_in - (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[0]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_54_L3_SEL 0 - - Configures MIO Pin 54 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800D8, 0x000000FEU ,0x00000004U) - RegMask = (IOU_SLCR_MIO_PIN_54_L0_SEL_MASK | IOU_SLCR_MIO_PIN_54_L1_SEL_MASK | IOU_SLCR_MIO_PIN_54_L2_SEL_MASK | IOU_SLCR_MIO_PIN_54_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_54_L0_SEL_SHIFT - | 0x00000001U << IOU_SLCR_MIO_PIN_54_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_54_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_54_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_54_OFFSET ,0x000000FEU ,0x00000004U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_55 @ 0XFF1800DC

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[2]- (TX RGMII data) - PSU_IOU_SLCR_MIO_PIN_55_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_nxt- (Data flow control signal from the PHY) - PSU_IOU_SLCR_MIO_PIN_55_L1_SEL 1 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used - PSU_IOU_SLCR_MIO_PIN_55_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[3]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[3]- (GPIO bank 2) 1= can - , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa - ) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0 - - (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial - output) 7= trace, Output, tracedq[1]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_55_L3_SEL 0 - - Configures MIO Pin 55 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800DC, 0x000000FEU ,0x00000004U) - RegMask = (IOU_SLCR_MIO_PIN_55_L0_SEL_MASK | IOU_SLCR_MIO_PIN_55_L1_SEL_MASK | IOU_SLCR_MIO_PIN_55_L2_SEL_MASK | IOU_SLCR_MIO_PIN_55_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_55_L0_SEL_SHIFT - | 0x00000001U << IOU_SLCR_MIO_PIN_55_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_55_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_55_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_55_OFFSET ,0x000000FEU ,0x00000004U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_56 @ 0XFF1800E0

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[3]- (TX RGMII data) - PSU_IOU_SLCR_MIO_PIN_56_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[0]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_ - ata[0]- (ULPI data bus) - PSU_IOU_SLCR_MIO_PIN_56_L1_SEL 1 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used - PSU_IOU_SLCR_MIO_PIN_56_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[4]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[4]- (GPIO bank 2) 1= can - , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa - ) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_s - - (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, - utput, tracedq[2]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_56_L3_SEL 0 - - Configures MIO Pin 56 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800E0, 0x000000FEU ,0x00000004U) - RegMask = (IOU_SLCR_MIO_PIN_56_L0_SEL_MASK | IOU_SLCR_MIO_PIN_56_L1_SEL_MASK | IOU_SLCR_MIO_PIN_56_L2_SEL_MASK | IOU_SLCR_MIO_PIN_56_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_56_L0_SEL_SHIFT - | 0x00000001U << IOU_SLCR_MIO_PIN_56_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_56_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_56_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_56_OFFSET ,0x000000FEU ,0x00000004U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_57 @ 0XFF1800E4

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_ctl- (TX RGMII control) - PSU_IOU_SLCR_MIO_PIN_57_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[1]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_ - ata[1]- (ULPI data bus) - PSU_IOU_SLCR_MIO_PIN_57_L1_SEL 1 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used - PSU_IOU_SLCR_MIO_PIN_57_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[5]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[5]- (GPIO bank 2) 1= can - , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal - 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi0 - si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7 - trace, Output, tracedq[3]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_57_L3_SEL 0 - - Configures MIO Pin 57 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800E4, 0x000000FEU ,0x00000004U) - RegMask = (IOU_SLCR_MIO_PIN_57_L0_SEL_MASK | IOU_SLCR_MIO_PIN_57_L1_SEL_MASK | IOU_SLCR_MIO_PIN_57_L2_SEL_MASK | IOU_SLCR_MIO_PIN_57_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_57_L0_SEL_SHIFT - | 0x00000001U << IOU_SLCR_MIO_PIN_57_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_57_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_57_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_57_OFFSET ,0x000000FEU ,0x00000004U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_58 @ 0XFF1800E8

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_clk- (RX RGMII clock) - PSU_IOU_SLCR_MIO_PIN_58_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Output, usb0_ulpi_stp- (Asserted to end or interrupt transfers) - PSU_IOU_SLCR_MIO_PIN_58_L1_SEL 1 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used - PSU_IOU_SLCR_MIO_PIN_58_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[6]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[6]- (GPIO bank 2) 1= can - , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal - 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1_sclk_out- (SPI Clock - 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- - Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_58_L3_SEL 0 - - Configures MIO Pin 58 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800E8, 0x000000FEU ,0x00000004U) - RegMask = (IOU_SLCR_MIO_PIN_58_L0_SEL_MASK | IOU_SLCR_MIO_PIN_58_L1_SEL_MASK | IOU_SLCR_MIO_PIN_58_L2_SEL_MASK | IOU_SLCR_MIO_PIN_58_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_58_L0_SEL_SHIFT - | 0x00000001U << IOU_SLCR_MIO_PIN_58_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_58_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_58_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_58_OFFSET ,0x000000FEU ,0x00000004U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_59 @ 0XFF1800EC

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[0]- (RX RGMII data) - PSU_IOU_SLCR_MIO_PIN_59_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[3]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_ - ata[3]- (ULPI data bus) - PSU_IOU_SLCR_MIO_PIN_59_L1_SEL 1 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used - PSU_IOU_SLCR_MIO_PIN_59_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[7]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[7]- (GPIO bank 2) 1= can - , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa - ) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_ - ut- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port - atabus) - PSU_IOU_SLCR_MIO_PIN_59_L3_SEL 0 - - Configures MIO Pin 59 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800EC, 0x000000FEU ,0x00000004U) - RegMask = (IOU_SLCR_MIO_PIN_59_L0_SEL_MASK | IOU_SLCR_MIO_PIN_59_L1_SEL_MASK | IOU_SLCR_MIO_PIN_59_L2_SEL_MASK | IOU_SLCR_MIO_PIN_59_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_59_L0_SEL_SHIFT - | 0x00000001U << IOU_SLCR_MIO_PIN_59_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_59_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_59_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_59_OFFSET ,0x000000FEU ,0x00000004U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_60 @ 0XFF1800F0

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[1]- (RX RGMII data) - PSU_IOU_SLCR_MIO_PIN_60_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[4]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_ - ata[4]- (ULPI data bus) - PSU_IOU_SLCR_MIO_PIN_60_L1_SEL 1 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used - PSU_IOU_SLCR_MIO_PIN_60_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[8]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[8]- (GPIO bank 2) 1= can - , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa - ) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc1, Input, ttc1_clk_i - - (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_60_L3_SEL 0 - - Configures MIO Pin 60 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800F0, 0x000000FEU ,0x00000004U) - RegMask = (IOU_SLCR_MIO_PIN_60_L0_SEL_MASK | IOU_SLCR_MIO_PIN_60_L1_SEL_MASK | IOU_SLCR_MIO_PIN_60_L2_SEL_MASK | IOU_SLCR_MIO_PIN_60_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_60_L0_SEL_SHIFT - | 0x00000001U << IOU_SLCR_MIO_PIN_60_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_60_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_60_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_60_OFFSET ,0x000000FEU ,0x00000004U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_61 @ 0XFF1800F4

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[2]- (RX RGMII data) - PSU_IOU_SLCR_MIO_PIN_61_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[5]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_ - ata[5]- (ULPI data bus) - PSU_IOU_SLCR_MIO_PIN_61_L1_SEL 1 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used - PSU_IOU_SLCR_MIO_PIN_61_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[9]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[9]- (GPIO bank 2) 1= can - , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal - 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, Output, spi1_n_ss_out[0] - (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial inpu - ) 7= trace, Output, tracedq[7]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_61_L3_SEL 0 - - Configures MIO Pin 61 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800F4, 0x000000FEU ,0x00000004U) - RegMask = (IOU_SLCR_MIO_PIN_61_L0_SEL_MASK | IOU_SLCR_MIO_PIN_61_L1_SEL_MASK | IOU_SLCR_MIO_PIN_61_L2_SEL_MASK | IOU_SLCR_MIO_PIN_61_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_61_L0_SEL_SHIFT - | 0x00000001U << IOU_SLCR_MIO_PIN_61_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_61_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_61_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_61_OFFSET ,0x000000FEU ,0x00000004U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_62 @ 0XFF1800F8

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[3]- (RX RGMII data) - PSU_IOU_SLCR_MIO_PIN_62_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[6]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_ - ata[6]- (ULPI data bus) - PSU_IOU_SLCR_MIO_PIN_62_L1_SEL 1 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used - PSU_IOU_SLCR_MIO_PIN_62_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[10]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[10]- (GPIO bank 2) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_ - o- (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outp - t, tracedq[8]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_62_L3_SEL 0 - - Configures MIO Pin 62 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800F8, 0x000000FEU ,0x00000004U) - RegMask = (IOU_SLCR_MIO_PIN_62_L0_SEL_MASK | IOU_SLCR_MIO_PIN_62_L1_SEL_MASK | IOU_SLCR_MIO_PIN_62_L2_SEL_MASK | IOU_SLCR_MIO_PIN_62_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_62_L0_SEL_SHIFT - | 0x00000001U << IOU_SLCR_MIO_PIN_62_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_62_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_62_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_62_OFFSET ,0x000000FEU ,0x00000004U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_63 @ 0XFF1800FC

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_ctl- (RX RGMII control ) - PSU_IOU_SLCR_MIO_PIN_63_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[7]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_ - ata[7]- (ULPI data bus) - PSU_IOU_SLCR_MIO_PIN_63_L1_SEL 1 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used - PSU_IOU_SLCR_MIO_PIN_63_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[11]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[11]- (GPIO bank 2) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s - i1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o - tput) 7= trace, Output, tracedq[9]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_63_L3_SEL 0 - - Configures MIO Pin 63 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF1800FC, 0x000000FEU ,0x00000004U) - RegMask = (IOU_SLCR_MIO_PIN_63_L0_SEL_MASK | IOU_SLCR_MIO_PIN_63_L1_SEL_MASK | IOU_SLCR_MIO_PIN_63_L2_SEL_MASK | IOU_SLCR_MIO_PIN_63_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_63_L0_SEL_SHIFT - | 0x00000001U << IOU_SLCR_MIO_PIN_63_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_63_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_63_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_63_OFFSET ,0x000000FEU ,0x00000004U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_64 @ 0XFF180100

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_clk- (TX RGMII clock) - PSU_IOU_SLCR_MIO_PIN_64_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_clk_in- (ULPI Clock) - PSU_IOU_SLCR_MIO_PIN_64_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= Not Used 3= Not Used - PSU_IOU_SLCR_MIO_PIN_64_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[12]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[12]- (GPIO bank 2) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, s - i0_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7 - trace, Output, tracedq[10]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_64_L3_SEL 0 - - Configures MIO Pin 64 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180100, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_64_L0_SEL_MASK | IOU_SLCR_MIO_PIN_64_L1_SEL_MASK | IOU_SLCR_MIO_PIN_64_L2_SEL_MASK | IOU_SLCR_MIO_PIN_64_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_64_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_64_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_64_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_64_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_64_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_65 @ 0XFF180104

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[0]- (TX RGMII data) - PSU_IOU_SLCR_MIO_PIN_65_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_dir- (Data bus direction control) - PSU_IOU_SLCR_MIO_PIN_65_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= Not Used 3= Not Used - PSU_IOU_SLCR_MIO_PIN_65_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[13]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[13]- (GPIO bank 2) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= - ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trac - dq[11]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_65_L3_SEL 0 - - Configures MIO Pin 65 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180104, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_65_L0_SEL_MASK | IOU_SLCR_MIO_PIN_65_L1_SEL_MASK | IOU_SLCR_MIO_PIN_65_L2_SEL_MASK | IOU_SLCR_MIO_PIN_65_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_65_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_65_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_65_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_65_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_65_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_66 @ 0XFF180108

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[1]- (TX RGMII data) - PSU_IOU_SLCR_MIO_PIN_66_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[2]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_ - ata[2]- (ULPI data bus) - PSU_IOU_SLCR_MIO_PIN_66_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Comman - Indicator) 2= Not Used 3= Not Used - PSU_IOU_SLCR_MIO_PIN_66_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[14]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[14]- (GPIO bank 2) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= tt - 2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace - Port Databus) - PSU_IOU_SLCR_MIO_PIN_66_L3_SEL 0 - - Configures MIO Pin 66 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180108, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_66_L0_SEL_MASK | IOU_SLCR_MIO_PIN_66_L1_SEL_MASK | IOU_SLCR_MIO_PIN_66_L2_SEL_MASK | IOU_SLCR_MIO_PIN_66_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_66_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_66_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_66_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_66_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_66_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_67 @ 0XFF18010C

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[2]- (TX RGMII data) - PSU_IOU_SLCR_MIO_PIN_67_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_nxt- (Data flow control signal from the PHY) - PSU_IOU_SLCR_MIO_PIN_67_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8 - bit Data bus) 2= Not Used 3= Not Used - PSU_IOU_SLCR_MIO_PIN_67_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[15]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[15]- (GPIO bank 2) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi - , Output, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd - (UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_67_L3_SEL 0 - - Configures MIO Pin 67 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF18010C, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_67_L0_SEL_MASK | IOU_SLCR_MIO_PIN_67_L1_SEL_MASK | IOU_SLCR_MIO_PIN_67_L2_SEL_MASK | IOU_SLCR_MIO_PIN_67_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_67_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_67_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_67_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_67_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_67_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_68 @ 0XFF180110

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[3]- (TX RGMII data) - PSU_IOU_SLCR_MIO_PIN_68_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[0]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_ - ata[0]- (ULPI data bus) - PSU_IOU_SLCR_MIO_PIN_68_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8 - bit Data bus) 2= Not Used 3= Not Used - PSU_IOU_SLCR_MIO_PIN_68_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[16]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[16]- (GPIO bank 2) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0 - so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace - Output, tracedq[14]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_68_L3_SEL 0 - - Configures MIO Pin 68 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180110, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_68_L0_SEL_MASK | IOU_SLCR_MIO_PIN_68_L1_SEL_MASK | IOU_SLCR_MIO_PIN_68_L2_SEL_MASK | IOU_SLCR_MIO_PIN_68_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_68_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_68_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_68_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_68_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_68_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_69 @ 0XFF180114

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_ctl- (TX RGMII control) - PSU_IOU_SLCR_MIO_PIN_69_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[1]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_ - ata[1]- (ULPI data bus) - PSU_IOU_SLCR_MIO_PIN_69_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8 - bit Data bus) 2= sd1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_69_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[17]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[17]- (GPIO bank 2) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, sp - 0_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) - 7= trace, Output, tracedq[15]- (Trace Port Databus) - PSU_IOU_SLCR_MIO_PIN_69_L3_SEL 0 - - Configures MIO Pin 69 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180114, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_69_L0_SEL_MASK | IOU_SLCR_MIO_PIN_69_L1_SEL_MASK | IOU_SLCR_MIO_PIN_69_L2_SEL_MASK | IOU_SLCR_MIO_PIN_69_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_69_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_69_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_69_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_69_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_69_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_70 @ 0XFF180118

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_clk- (RX RGMII clock) - PSU_IOU_SLCR_MIO_PIN_70_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Output, usb1_ulpi_stp- (Asserted to end or interrupt transfers) - PSU_IOU_SLCR_MIO_PIN_70_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8 - bit Data bus) 2= sd1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_70_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[18]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[18]- (GPIO bank 2) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, sp - 1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not - sed - PSU_IOU_SLCR_MIO_PIN_70_L3_SEL 0 - - Configures MIO Pin 70 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180118, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_70_L0_SEL_MASK | IOU_SLCR_MIO_PIN_70_L1_SEL_MASK | IOU_SLCR_MIO_PIN_70_L2_SEL_MASK | IOU_SLCR_MIO_PIN_70_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_70_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_70_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_70_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_70_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_70_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_71 @ 0XFF18011C

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[0]- (RX RGMII data) - PSU_IOU_SLCR_MIO_PIN_71_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[3]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_ - ata[3]- (ULPI data bus) - PSU_IOU_SLCR_MIO_PIN_71_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8 - bit Data bus) 2= sd1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_out[0]- (8-bit Data bus) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_71_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[19]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[19]- (GPIO bank 2) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5 - ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used - PSU_IOU_SLCR_MIO_PIN_71_L3_SEL 0 - - Configures MIO Pin 71 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF18011C, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_71_L0_SEL_MASK | IOU_SLCR_MIO_PIN_71_L1_SEL_MASK | IOU_SLCR_MIO_PIN_71_L2_SEL_MASK | IOU_SLCR_MIO_PIN_71_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_71_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_71_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_71_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_71_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_71_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_72 @ 0XFF180120

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[1]- (RX RGMII data) - PSU_IOU_SLCR_MIO_PIN_72_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[4]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_ - ata[4]- (ULPI data bus) - PSU_IOU_SLCR_MIO_PIN_72_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8 - bit Data bus) 2= sd1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_out[1]- (8-bit Data bus) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_72_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[20]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[20]- (GPIO bank 2) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= N - t Used 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Used - PSU_IOU_SLCR_MIO_PIN_72_L3_SEL 0 - - Configures MIO Pin 72 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180120, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_72_L0_SEL_MASK | IOU_SLCR_MIO_PIN_72_L1_SEL_MASK | IOU_SLCR_MIO_PIN_72_L2_SEL_MASK | IOU_SLCR_MIO_PIN_72_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_72_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_72_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_72_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_72_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_72_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_73 @ 0XFF180124

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[2]- (RX RGMII data) - PSU_IOU_SLCR_MIO_PIN_73_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_ - ata[5]- (ULPI data bus) - PSU_IOU_SLCR_MIO_PIN_73_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8 - bit Data bus) 2= sd1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_out[2]- (8-bit Data bus) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_73_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[21]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[21]- (GPIO bank 2) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1 - Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= Not Used 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used - PSU_IOU_SLCR_MIO_PIN_73_L3_SEL 0 - - Configures MIO Pin 73 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180124, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_73_L0_SEL_MASK | IOU_SLCR_MIO_PIN_73_L1_SEL_MASK | IOU_SLCR_MIO_PIN_73_L2_SEL_MASK | IOU_SLCR_MIO_PIN_73_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_73_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_73_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_73_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_73_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_73_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_74 @ 0XFF180128

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[3]- (RX RGMII data) - PSU_IOU_SLCR_MIO_PIN_74_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[6]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_ - ata[6]- (ULPI data bus) - PSU_IOU_SLCR_MIO_PIN_74_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8 - bit Data bus) 2= sd1, Input, sd1_data_in[3]- (8-bit Data bus) = sd1, Output, sdio1_data_out[3]- (8-bit Data bus) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_74_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[22]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[22]- (GPIO bank 2) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_ - o- (MISO signal) 5= Not Used 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used - PSU_IOU_SLCR_MIO_PIN_74_L3_SEL 0 - - Configures MIO Pin 74 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180128, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_74_L0_SEL_MASK | IOU_SLCR_MIO_PIN_74_L1_SEL_MASK | IOU_SLCR_MIO_PIN_74_L2_SEL_MASK | IOU_SLCR_MIO_PIN_74_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_74_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_74_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_74_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_74_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_74_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_75 @ 0XFF18012C

- - Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_ctl- (RX RGMII control ) - PSU_IOU_SLCR_MIO_PIN_75_L0_SEL 1 - - Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[7]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_ - ata[7]- (ULPI data bus) - PSU_IOU_SLCR_MIO_PIN_75_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= sd1, Input, sd1_cmd_in- (Comma - d Indicator) = sd1, Output, sdio1_cmd_out- (Command Indicator) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_75_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[23]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[23]- (GPIO bank 2) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s - i1_si- (MOSI signal) 5= Not Used 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used - PSU_IOU_SLCR_MIO_PIN_75_L3_SEL 0 - - Configures MIO Pin 75 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF18012C, 0x000000FEU ,0x00000002U) - RegMask = (IOU_SLCR_MIO_PIN_75_L0_SEL_MASK | IOU_SLCR_MIO_PIN_75_L1_SEL_MASK | IOU_SLCR_MIO_PIN_75_L2_SEL_MASK | IOU_SLCR_MIO_PIN_75_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_75_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_75_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_75_L2_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_75_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_75_OFFSET ,0x000000FEU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_76 @ 0XFF180130

- - Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_76_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_76_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= sd1, Output, sdio - _clk_out- (SDSDIO clock) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_76_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[24]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[24]- (GPIO bank 2) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= mdio0, Output, gem0_mdc- (MDIO Clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= mdio2, Output, gem2_mdc- (MDIO Clock - 6= mdio3, Output, gem3_mdc- (MDIO Clock) 7= Not Used - PSU_IOU_SLCR_MIO_PIN_76_L3_SEL 6 - - Configures MIO Pin 76 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180130, 0x000000FEU ,0x000000C0U) - RegMask = (IOU_SLCR_MIO_PIN_76_L0_SEL_MASK | IOU_SLCR_MIO_PIN_76_L1_SEL_MASK | IOU_SLCR_MIO_PIN_76_L2_SEL_MASK | IOU_SLCR_MIO_PIN_76_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_76_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_76_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_76_L2_SEL_SHIFT - | 0x00000006U << IOU_SLCR_MIO_PIN_76_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_76_OFFSET ,0x000000FEU ,0x000000C0U); - /*############################################################################################################################ */ - - /*Register : MIO_PIN_77 @ 0XFF180134

- - Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_77_L0_SEL 0 - - Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used - PSU_IOU_SLCR_MIO_PIN_77_L1_SEL 0 - - Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Input, sdio1_cd_n- (SD card detect from connector) 3= Not Used - PSU_IOU_SLCR_MIO_PIN_77_L2_SEL 0 - - Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[25]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[25]- (GPIO bank 2) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= mdio0, Input, gem0_mdio_in- (MDIO Data) 3= mdio0, Output, gem0_mdio_out- (MDIO Data) 4= mdio1, Input, gem1_mdio_in- (MD - O Data) 4= mdio1, Output, gem1_mdio_out- (MDIO Data) 5= mdio2, Input, gem2_mdio_in- (MDIO Data) 5= mdio2, Output, gem2_mdio_o - t- (MDIO Data) 6= mdio3, Input, gem3_mdio_in- (MDIO Data) 6= mdio3, Output, gem3_mdio_out- (MDIO Data) 7= Not Used - PSU_IOU_SLCR_MIO_PIN_77_L3_SEL 6 - - Configures MIO Pin 77 peripheral interface mapping - (OFFSET, MASK, VALUE) (0XFF180134, 0x000000FEU ,0x000000C0U) - RegMask = (IOU_SLCR_MIO_PIN_77_L0_SEL_MASK | IOU_SLCR_MIO_PIN_77_L1_SEL_MASK | IOU_SLCR_MIO_PIN_77_L2_SEL_MASK | IOU_SLCR_MIO_PIN_77_L3_SEL_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_77_L0_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_77_L1_SEL_SHIFT - | 0x00000000U << IOU_SLCR_MIO_PIN_77_L2_SEL_SHIFT - | 0x00000006U << IOU_SLCR_MIO_PIN_77_L3_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_PIN_77_OFFSET ,0x000000FEU ,0x000000C0U); - /*############################################################################################################################ */ - - /*Register : MIO_MST_TRI0 @ 0XFF180204

- - Master Tri-state Enable for pin 0, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI 0 - - Master Tri-state Enable for pin 1, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI 0 - - Master Tri-state Enable for pin 2, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI 0 - - Master Tri-state Enable for pin 3, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI 0 - - Master Tri-state Enable for pin 4, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI 0 - - Master Tri-state Enable for pin 5, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI 0 - - Master Tri-state Enable for pin 6, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI 0 - - Master Tri-state Enable for pin 7, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI 0 - - Master Tri-state Enable for pin 8, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI 0 - - Master Tri-state Enable for pin 9, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI 0 - - Master Tri-state Enable for pin 10, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI 0 - - Master Tri-state Enable for pin 11, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI 0 - - Master Tri-state Enable for pin 12, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI 0 - - Master Tri-state Enable for pin 13, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI 0 - - Master Tri-state Enable for pin 14, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI 0 - - Master Tri-state Enable for pin 15, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI 0 - - Master Tri-state Enable for pin 16, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI 0 - - Master Tri-state Enable for pin 17, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI 0 - - Master Tri-state Enable for pin 18, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI 1 - - Master Tri-state Enable for pin 19, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI 0 - - Master Tri-state Enable for pin 20, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI 0 - - Master Tri-state Enable for pin 21, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI 1 - - Master Tri-state Enable for pin 22, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI 0 - - Master Tri-state Enable for pin 23, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI 0 - - Master Tri-state Enable for pin 24, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI 0 - - Master Tri-state Enable for pin 25, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI 1 - - Master Tri-state Enable for pin 26, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI 0 - - Master Tri-state Enable for pin 27, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI 0 - - Master Tri-state Enable for pin 28, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI 1 - - Master Tri-state Enable for pin 29, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI 0 - - Master Tri-state Enable for pin 30, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI 1 - - Master Tri-state Enable for pin 31, active high - PSU_IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI 0 - - MIO pin Tri-state Enables, 31:0 - (OFFSET, MASK, VALUE) (0XFF180204, 0xFFFFFFFFU ,0x52240000U) - RegMask = (IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_SHIFT - | 0x00000001U << IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_SHIFT - | 0x00000001U << IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_SHIFT - | 0x00000001U << IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_SHIFT - | 0x00000001U << IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_SHIFT - | 0x00000001U << IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_MST_TRI0_OFFSET ,0xFFFFFFFFU ,0x52240000U); - /*############################################################################################################################ */ - - /*Register : MIO_MST_TRI1 @ 0XFF180208

- - Master Tri-state Enable for pin 32, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI 0 - - Master Tri-state Enable for pin 33, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI 0 - - Master Tri-state Enable for pin 34, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI 0 - - Master Tri-state Enable for pin 35, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI 0 - - Master Tri-state Enable for pin 36, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI 0 - - Master Tri-state Enable for pin 37, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI 0 - - Master Tri-state Enable for pin 38, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI 0 - - Master Tri-state Enable for pin 39, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI 0 - - Master Tri-state Enable for pin 40, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI 0 - - Master Tri-state Enable for pin 41, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI 0 - - Master Tri-state Enable for pin 42, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI 0 - - Master Tri-state Enable for pin 43, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI 0 - - Master Tri-state Enable for pin 44, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI 1 - - Master Tri-state Enable for pin 45, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI 1 - - Master Tri-state Enable for pin 46, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI 0 - - Master Tri-state Enable for pin 47, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI 0 - - Master Tri-state Enable for pin 48, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI 0 - - Master Tri-state Enable for pin 49, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI 0 - - Master Tri-state Enable for pin 50, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI 0 - - Master Tri-state Enable for pin 51, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI 0 - - Master Tri-state Enable for pin 52, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI 1 - - Master Tri-state Enable for pin 53, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI 1 - - Master Tri-state Enable for pin 54, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI 0 - - Master Tri-state Enable for pin 55, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI 1 - - Master Tri-state Enable for pin 56, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI 0 - - Master Tri-state Enable for pin 57, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI 0 - - Master Tri-state Enable for pin 58, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI 0 - - Master Tri-state Enable for pin 59, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI 0 - - Master Tri-state Enable for pin 60, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI 0 - - Master Tri-state Enable for pin 61, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI 0 - - Master Tri-state Enable for pin 62, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI 0 - - Master Tri-state Enable for pin 63, active high - PSU_IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI 0 - - MIO pin Tri-state Enables, 63:32 - (OFFSET, MASK, VALUE) (0XFF180208, 0xFFFFFFFFU ,0x00B03000U) - RegMask = (IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_SHIFT - | 0x00000001U << IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_SHIFT - | 0x00000001U << IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_SHIFT - | 0x00000001U << IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_SHIFT - | 0x00000001U << IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_SHIFT - | 0x00000001U << IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_MST_TRI1_OFFSET ,0xFFFFFFFFU ,0x00B03000U); - /*############################################################################################################################ */ - - /*Register : MIO_MST_TRI2 @ 0XFF18020C

- - Master Tri-state Enable for pin 64, active high - PSU_IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI 0 - - Master Tri-state Enable for pin 65, active high - PSU_IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI 0 - - Master Tri-state Enable for pin 66, active high - PSU_IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI 0 - - Master Tri-state Enable for pin 67, active high - PSU_IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI 0 - - Master Tri-state Enable for pin 68, active high - PSU_IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI 0 - - Master Tri-state Enable for pin 69, active high - PSU_IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI 0 - - Master Tri-state Enable for pin 70, active high - PSU_IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI 1 - - Master Tri-state Enable for pin 71, active high - PSU_IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI 1 - - Master Tri-state Enable for pin 72, active high - PSU_IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI 1 - - Master Tri-state Enable for pin 73, active high - PSU_IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI 1 - - Master Tri-state Enable for pin 74, active high - PSU_IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI 1 - - Master Tri-state Enable for pin 75, active high - PSU_IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI 1 - - Master Tri-state Enable for pin 76, active high - PSU_IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI 0 - - Master Tri-state Enable for pin 77, active high - PSU_IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI 0 - - MIO pin Tri-state Enables, 77:64 - (OFFSET, MASK, VALUE) (0XFF18020C, 0x00003FFFU ,0x00000FC0U) - RegMask = (IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_SHIFT - | 0x00000001U << IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_SHIFT - | 0x00000001U << IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_SHIFT - | 0x00000001U << IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_SHIFT - | 0x00000001U << IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_SHIFT - | 0x00000001U << IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_SHIFT - | 0x00000001U << IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_SHIFT - | 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_MST_TRI2_OFFSET ,0x00003FFFU ,0x00000FC0U); - /*############################################################################################################################ */ - - /*Register : bank0_ctrl0 @ 0XFF180138

- - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25 1 - - Drive0 control to MIO Bank 0 - control MIO[25:0] - (OFFSET, MASK, VALUE) (0XFF180138, 0x03FFFFFFU ,0x03FFFFFFU) - RegMask = (IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_BANK0_CTRL0_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU); - /*############################################################################################################################ */ - - /*Register : bank0_ctrl1 @ 0XFF18013C

- - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25 1 - - Drive1 control to MIO Bank 0 - control MIO[25:0] - (OFFSET, MASK, VALUE) (0XFF18013C, 0x03FFFFFFU ,0x03FFFFFFU) - RegMask = (IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_BANK0_CTRL1_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU); - /*############################################################################################################################ */ - - /*Register : bank0_ctrl3 @ 0XFF180140

- - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25 0 - - Selects either Schmitt or CMOS input for MIO Bank 0 - control MIO[25:0] - (OFFSET, MASK, VALUE) (0XFF180140, 0x03FFFFFFU ,0x00000000U) - RegMask = (IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_BANK0_CTRL3_OFFSET ,0x03FFFFFFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : bank0_ctrl4 @ 0XFF180144

- - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25 1 - - When mio_bank0_pull_enable is set, this selects pull up or pull down for MIO Bank 0 - control MIO[25:0] - (OFFSET, MASK, VALUE) (0XFF180144, 0x03FFFFFFU ,0x03FFFFFFU) - RegMask = (IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_BANK0_CTRL4_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU); - /*############################################################################################################################ */ - - /*Register : bank0_ctrl5 @ 0XFF180148

- - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24 1 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25 1 - - When set, this enables mio_bank0_pullupdown to selects pull up or pull down for MIO Bank 0 - control MIO[25:0] - (OFFSET, MASK, VALUE) (0XFF180148, 0x03FFFFFFU ,0x03FFFFFFU) - RegMask = (IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_SHIFT - | 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_BANK0_CTRL5_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU); - /*############################################################################################################################ */ - - /*Register : bank0_ctrl6 @ 0XFF18014C

- - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24 0 - - Each bit applies to a single IO. Bit 0 for MIO[0]. - PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25 0 - - Slew rate control to MIO Bank 0 - control MIO[25:0] - (OFFSET, MASK, VALUE) (0XFF18014C, 0x03FFFFFFU ,0x00000000U) - RegMask = (IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT - | 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_BANK0_CTRL6_OFFSET ,0x03FFFFFFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : bank1_ctrl0 @ 0XFF180154

- - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25 1 - - Drive0 control to MIO Bank 1 - control MIO[51:26] - (OFFSET, MASK, VALUE) (0XFF180154, 0x03FFFFFFU ,0x03FFFFFFU) - RegMask = (IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_BANK1_CTRL0_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU); - /*############################################################################################################################ */ - - /*Register : bank1_ctrl1 @ 0XFF180158

- - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25 1 - - Drive1 control to MIO Bank 1 - control MIO[51:26] - (OFFSET, MASK, VALUE) (0XFF180158, 0x03FFFFFFU ,0x03FFFFFFU) - RegMask = (IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_BANK1_CTRL1_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU); - /*############################################################################################################################ */ - - /*Register : bank1_ctrl3 @ 0XFF18015C

- - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25 0 - - Selects either Schmitt or CMOS input for MIO Bank 1 - control MIO[51:26] - (OFFSET, MASK, VALUE) (0XFF18015C, 0x03FFFFFFU ,0x00000000U) - RegMask = (IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_BANK1_CTRL3_OFFSET ,0x03FFFFFFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : bank1_ctrl4 @ 0XFF180160

- - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25 1 - - When mio_bank1_pull_enable is set, this selects pull up or pull down for MIO Bank 1 - control MIO[51:26] - (OFFSET, MASK, VALUE) (0XFF180160, 0x03FFFFFFU ,0x03FFFFFFU) - RegMask = (IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_BANK1_CTRL4_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU); - /*############################################################################################################################ */ - - /*Register : bank1_ctrl5 @ 0XFF180164

- - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24 1 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25 1 - - When set, this enables mio_bank1_pullupdown to selects pull up or pull down for MIO Bank 1 - control MIO[51:26] - (OFFSET, MASK, VALUE) (0XFF180164, 0x03FFFFFFU ,0x03FFFFFFU) - RegMask = (IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_SHIFT - | 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_BANK1_CTRL5_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU); - /*############################################################################################################################ */ - - /*Register : bank1_ctrl6 @ 0XFF180168

- - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24 0 - - Each bit applies to a single IO. Bit 0 for MIO[26]. - PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25 0 - - Slew rate control to MIO Bank 1 - control MIO[51:26] - (OFFSET, MASK, VALUE) (0XFF180168, 0x03FFFFFFU ,0x00000000U) - RegMask = (IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT - | 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_BANK1_CTRL6_OFFSET ,0x03FFFFFFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : bank2_ctrl0 @ 0XFF180170

- - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25 1 - - Drive0 control to MIO Bank 2 - control MIO[77:52] - (OFFSET, MASK, VALUE) (0XFF180170, 0x03FFFFFFU ,0x03FFFFFFU) - RegMask = (IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_BANK2_CTRL0_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU); - /*############################################################################################################################ */ - - /*Register : bank2_ctrl1 @ 0XFF180174

- - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25 1 - - Drive1 control to MIO Bank 2 - control MIO[77:52] - (OFFSET, MASK, VALUE) (0XFF180174, 0x03FFFFFFU ,0x03FFFFFFU) - RegMask = (IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_BANK2_CTRL1_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU); - /*############################################################################################################################ */ - - /*Register : bank2_ctrl3 @ 0XFF180178

- - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25 0 - - Selects either Schmitt or CMOS input for MIO Bank 2 - control MIO[77:52] - (OFFSET, MASK, VALUE) (0XFF180178, 0x03FFFFFFU ,0x00000000U) - RegMask = (IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_BANK2_CTRL3_OFFSET ,0x03FFFFFFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : bank2_ctrl4 @ 0XFF18017C

- - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25 1 - - When mio_bank2_pull_enable is set, this selects pull up or pull down for MIO Bank 2 - control MIO[77:52] - (OFFSET, MASK, VALUE) (0XFF18017C, 0x03FFFFFFU ,0x03FFFFFFU) - RegMask = (IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_BANK2_CTRL4_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU); - /*############################################################################################################################ */ - - /*Register : bank2_ctrl5 @ 0XFF180180

- - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24 1 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25 1 - - When set, this enables mio_bank2_pullupdown to selects pull up or pull down for MIO Bank 2 - control MIO[77:52] - (OFFSET, MASK, VALUE) (0XFF180180, 0x03FFFFFFU ,0x03FFFFFFU) - RegMask = (IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_SHIFT - | 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_BANK2_CTRL5_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU); - /*############################################################################################################################ */ - - /*Register : bank2_ctrl6 @ 0XFF180184

- - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24 0 - - Each bit applies to a single IO. Bit 0 for MIO[52]. - PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25 0 - - Slew rate control to MIO Bank 2 - control MIO[77:52] - (OFFSET, MASK, VALUE) (0XFF180184, 0x03FFFFFFU ,0x00000000U) - RegMask = (IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT - | 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_BANK2_CTRL6_OFFSET ,0x03FFFFFFU ,0x00000000U); - /*############################################################################################################################ */ - - // : LOOPBACK - /*Register : MIO_LOOPBACK @ 0XFF180200

- - I2C Loopback Control. 0 = Connect I2C inputs according to MIO mapping. 1 = Loop I2C 0 outputs to I2C 1 inputs, and I2C 1 outp - ts to I2C 0 inputs. - PSU_IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1 0 - - CAN Loopback Control. 0 = Connect CAN inputs according to MIO mapping. 1 = Loop CAN 0 Tx to CAN 1 Rx, and CAN 1 Tx to CAN 0 R - . - PSU_IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1 0 - - UART Loopback Control. 0 = Connect UART inputs according to MIO mapping. 1 = Loop UART 0 outputs to UART 1 inputs, and UART 1 - outputs to UART 0 inputs. RXD/TXD cross-connected. RTS/CTS cross-connected. DSR, DTR, DCD and RI not used. - PSU_IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1 0 - - SPI Loopback Control. 0 = Connect SPI inputs according to MIO mapping. 1 = Loop SPI 0 outputs to SPI 1 inputs, and SPI 1 outp - ts to SPI 0 inputs. The other SPI core will appear on the LS Slave Select. - PSU_IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1 0 - - Loopback function within MIO - (OFFSET, MASK, VALUE) (0XFF180200, 0x0000000FU ,0x00000000U) - RegMask = (IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_MASK | IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_MASK | IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_MASK | IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_SHIFT - | 0x00000000U << IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_SHIFT - | 0x00000000U << IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_SHIFT - | 0x00000000U << IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_MIO_LOOPBACK_OFFSET ,0x0000000FU ,0x00000000U); - /*############################################################################################################################ */ - - - return 1; + return 1; } -unsigned long psu_peripherals_init_data() { - // : RESET BLOCKS - // : TIMESTAMP - /*Register : RST_LPD_IOU2 @ 0XFF5E0238

+unsigned long psu_mio_init_data(void) +{ + /* + * MIO PROGRAMMING + */ + /* + * Register : MIO_PIN_0 @ 0XFF180000 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out- + * (QSPI Clock) + * PSU_IOU_SLCR_MIO_PIN_0_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_0_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[0]- (Test Scan Port) = test_scan, Output, test_scan_out[0 + * ]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_0_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[0]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[0]- (GPIO bank 0) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG + * TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sc + * lk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Out + * put, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_c + * lk- (Trace Port Clock) + * PSU_IOU_SLCR_MIO_PIN_0_L3_SEL 0 + + * Configures MIO Pin 0 peripheral interface mapping. S + * (OFFSET, MASK, VALUE) (0XFF180000, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_0_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_1 @ 0XFF180004 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (Q + * SPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Databus) + * PSU_IOU_SLCR_MIO_PIN_1_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_1_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[1]- (Test Scan Port) = test_scan, Output, test_scan_out[1 + * ]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_1_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[1]- (GPIO bank 0) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG + * TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc3, Ou + * tput, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART + * receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control + * Signal) + * PSU_IOU_SLCR_MIO_PIN_1_L3_SEL 0 + + * Configures MIO Pin 1 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180004, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_1_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_2 @ 0XFF180008 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI + * Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus) + * PSU_IOU_SLCR_MIO_PIN_2_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_2_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[2]- (Test Scan Port) = test_scan, Output, test_scan_out[2 + * ]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_2_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[2]- (GPIO bank 0) 1= can0, Input, can0_phy_ + * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + * , Output, i2c0_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTAG + * TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc2, I + * nput, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver se + * rial input) 7= trace, Output, tracedq[0]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_2_L3_SEL 0 + + * Configures MIO Pin 2 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180008, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_2_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_3 @ 0XFF18000C + + * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI + * Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus) + * PSU_IOU_SLCR_MIO_PIN_3_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_3_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[3]- (Test Scan Port) = test_scan, Output, test_scan_out[3 + * ]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_3_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[3]- (GPIO bank 0) 1= can0, Output, can0_phy + * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + * 0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG + * TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output + * , spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- + * (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial + * output) 7= trace, Output, tracedq[1]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_3_L3_SEL 0 + + * Configures MIO Pin 3 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF18000C, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_3_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_4 @ 0XFF180010 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- ( + * QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Databus) + * PSU_IOU_SLCR_MIO_PIN_4_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_4_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[4]- (Test Scan Port) = test_scan, Output, test_scan_out[4 + * ]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_4_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[4]- (GPIO bank 0) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Wa + * tch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi + * 0, Output, spi0_so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Cloc + * k) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, O + * utput, tracedq[2]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_4_L3_SEL 0 + + * Configures MIO Pin 4 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180010, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_4_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_5 @ 0XFF180014 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out- + * (QSPI Slave Select) + * PSU_IOU_SLCR_MIO_PIN_5_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_5_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[5]- (Test Scan Port) = test_scan, Output, test_scan_out[5 + * ]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_5_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[5]- (GPIO bank 0) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (W + * atch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= + * spi0, Input, spi0_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC + * Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= + * trace, Output, tracedq[3]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_5_L3_SEL 0 + + * Configures MIO Pin 5 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180014, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_5_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_6 @ 0XFF180018 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_clk_for_l + * pbk- (QSPI Clock to be fed-back) + * PSU_IOU_SLCR_MIO_PIN_6_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_6_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[6]- (Test Scan Port) = test_scan, Output, test_scan_out[6 + * ]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_6_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[6]- (GPIO bank 0) 1= can0, Input, can0_phy_ + * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + * , Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Wat + * ch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= s + * pi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TT + * C Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, + * Output, tracedq[4]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_6_L3_SEL 0 + + * Configures MIO Pin 6 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180018, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_6_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_7 @ 0XFF18001C + + * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out_ + * upper- (QSPI Slave Select upper) + * PSU_IOU_SLCR_MIO_PIN_7_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_7_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[7]- (Test Scan Port) = test_scan, Output, test_scan_out[7 + * ]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_7_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[7]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[7]- (GPIO bank 0) 1= can0, Output, can0_phy + * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + * 0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- ( + * Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Ma + * ster Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua + * 0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, t + * racedq[5]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_7_L3_SEL 0 + + * Configures MIO Pin 7 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF18001C, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_7_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_8 @ 0XFF180020 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[0 + * ]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[0]- (QSPI Upper D + * atabus) + * PSU_IOU_SLCR_MIO_PIN_8_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_8_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[8]- (Test Scan Port) = test_scan, Output, test_scan_out[8 + * ]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_8_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[8]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[8]- (GPIO bank 0) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Wa + * tch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Maste + * r Selects) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_ + * txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Tra + * ce Port Databus) + * PSU_IOU_SLCR_MIO_PIN_8_L3_SEL 0 + + * Configures MIO Pin 8 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180020, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_8_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_9 @ 0XFF180024 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[1 + * ]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[1]- (QSPI Upper D + * atabus) + * PSU_IOU_SLCR_MIO_PIN_9_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NA + * ND chip enable) + * PSU_IOU_SLCR_MIO_PIN_9_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[9]- (Test Scan Port) = test_scan, Output, test_scan_out[9 + * ]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_9_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[9]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[9]- (GPIO bank 0) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (W + * atch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master S + * elects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc3, + * Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UA + * RT receiver serial input) 7= trace, Output, tracedq[7]- (Trace Port Data + * bus) + * PSU_IOU_SLCR_MIO_PIN_9_L3_SEL 0 + + * Configures MIO Pin 9 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180024, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_9_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_10 @ 0XFF180028 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[2 + * ]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[2]- (QSPI Upper D + * atabus) + * PSU_IOU_SLCR_MIO_PIN_10_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (N + * AND Ready/Busy) + * PSU_IOU_SLCR_MIO_PIN_10_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[10]- (Test Scan Port) = test_scan, Output, test_scan_out[ + * 10]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_10_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[10]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[10]- (GPIO bank 0) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= sp + * i1, Output, spi1_so- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clo + * ck) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outpu + * t, tracedq[8]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_10_L3_SEL 0 + + * Configures MIO Pin 10 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180028, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_10_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_11 @ 0XFF18002C + + * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[3 + * ]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[3]- (QSPI Upper D + * atabus) + * PSU_IOU_SLCR_MIO_PIN_11_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (N + * AND Ready/Busy) + * PSU_IOU_SLCR_MIO_PIN_11_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[11]- (Test Scan Port) = test_scan, Output, test_scan_out[ + * 11]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_11_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) + * 4= spi1, Input, spi1_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- ( + * TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial ou + * tput) 7= trace, Output, tracedq[9]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_11_L3_SEL 0 + + * Configures MIO Pin 11 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF18002C, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_11_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_12 @ 0XFF180030 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out_ + * upper- (QSPI Upper Clock) + * PSU_IOU_SLCR_MIO_PIN_12_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NA + * ND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe) + * PSU_IOU_SLCR_MIO_PIN_12_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[12]- (Test Scan Port) = test_scan, Output, test_scan_out[ + * 12]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_12_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[12]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[12]- (GPIO bank 0) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJT + * AG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_ + * sclk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, O + * utput, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace + * dq[10]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_12_L3_SEL 0 + + * Configures MIO Pin 12 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180030, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_12_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_13 @ 0XFF180034 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_13_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[0]- (NA + * ND chip enable) + * PSU_IOU_SLCR_MIO_PIN_13_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[13]- (Test Scan Port) = test_scan, Output, + * test_scan_out[13]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_13_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[13]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[13]- (GPIO bank 0) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTA + * G TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, + * Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UAR + * T receiver serial input) 7= trace, Output, tracedq[11]- (Trace Port Data + * bus) + * PSU_IOU_SLCR_MIO_PIN_13_L3_SEL 0 + + * Configures MIO Pin 13 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180034, 0x000000FEU ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_13_OFFSET, 0x000000FEU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_14 @ 0XFF180038 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_14_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_cle- (NAND + * Command Latch Enable) + * PSU_IOU_SLCR_MIO_PIN_14_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[14]- (Test Scan Port) = test_scan, Output, + * test_scan_out[14]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_14_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJT + * AG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, + * Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver + * serial input) 7= trace, Output, tracedq[12]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_14_L3_SEL 2 + + * Configures MIO Pin 14 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180038, 0x000000FEU ,0x00000040U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_14_OFFSET, 0x000000FEU, 0x00000040U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_15 @ 0XFF18003C + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_15_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ale- (NAND + * Address Latch Enable) + * PSU_IOU_SLCR_MIO_PIN_15_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[15]- (Test Scan Port) = test_scan, Output, + * test_scan_out[15]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_15_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[15]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[15]- (GPIO bank 0) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJT + * AG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Outp + * ut, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_ou + * t- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter seria + * l output) 7= trace, Output, tracedq[13]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_15_L3_SEL 2 + + * Configures MIO Pin 15 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF18003C, 0x000000FEU ,0x00000040U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_15_OFFSET, 0x000000FEU, 0x00000040U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_16 @ 0XFF180040 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_16_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[0]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[0]- (NAND Data Bus) + * PSU_IOU_SLCR_MIO_PIN_16_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[16]- (Test Scan Port) = test_scan, Output, + * test_scan_out[16]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_16_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[16]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[16]- (GPIO bank 0) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= s + * pi0, Output, spi0_so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Cl + * ock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, + * Output, tracedq[14]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_16_L3_SEL 2 + + * Configures MIO Pin 16 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180040, 0x000000FEU ,0x00000040U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_16_OFFSET, 0x000000FEU, 0x00000040U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_17 @ 0XFF180044 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_17_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[1]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[1]- (NAND Data Bus) + * PSU_IOU_SLCR_MIO_PIN_17_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[17]- (Test Scan Port) = test_scan, Output, + * test_scan_out[17]- (Test Scan Port) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_17_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[17]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[17]- (GPIO bank 0) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4 + * = spi0, Input, spi0_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (T + * TC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) + * 7= trace, Output, tracedq[15]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_17_L3_SEL 2 + + * Configures MIO Pin 17 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180044, 0x000000FEU ,0x00000040U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_17_OFFSET, 0x000000FEU, 0x00000040U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_18 @ 0XFF180048 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_18_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[2]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[2]- (NAND Data Bus) + * PSU_IOU_SLCR_MIO_PIN_18_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[18]- (Test Scan Port) = test_scan, Output, + * test_scan_out[18]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU + * Ext Tamper) + * PSU_IOU_SLCR_MIO_PIN_18_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[18]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[18]- (GPIO bank 0) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= sp + * i1, Output, spi1_so- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clo + * ck) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_18_L3_SEL 6 + + * Configures MIO Pin 18 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180048, 0x000000FEU ,0x000000C0U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_18_OFFSET, 0x000000FEU, 0x000000C0U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_19 @ 0XFF18004C + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_19_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[3]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[3]- (NAND Data Bus) + * PSU_IOU_SLCR_MIO_PIN_19_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[19]- (Test Scan Port) = test_scan, Output, + * test_scan_out[19]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU + * Ext Tamper) + * PSU_IOU_SLCR_MIO_PIN_19_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[19]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[19]- (GPIO bank 0) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI + * Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= + * ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_19_L3_SEL 6 + + * Configures MIO Pin 19 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF18004C, 0x000000FEU ,0x000000C0U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_19_OFFSET, 0x000000FEU, 0x000000C0U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_20 @ 0XFF180050 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_20_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[4]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[4]- (NAND Data Bus) + * PSU_IOU_SLCR_MIO_PIN_20_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[20]- (Test Scan Port) = test_scan, Output, + * test_scan_out[20]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU + * Ext Tamper) + * PSU_IOU_SLCR_MIO_PIN_20_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[20]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[20]- (GPIO bank 0) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Mas + * ter Selects) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua + * 1_txd- (UART transmitter serial output) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_20_L3_SEL 6 + + * Configures MIO Pin 20 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180050, 0x000000FEU ,0x000000C0U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_20_OFFSET, 0x000000FEU, 0x000000C0U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_21 @ 0XFF180054 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_21_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[5]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[5]- (NAND Data Bus) + * PSU_IOU_SLCR_MIO_PIN_21_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Com + * mand Indicator) = sd0, Output, sdio0_cmd_out- (Command Indicator) 2= tes + * t_scan, Input, test_scan_in[21]- (Test Scan Port) = test_scan, Output, t + * est_scan_out[21]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU E + * xt Tamper) + * PSU_IOU_SLCR_MIO_PIN_21_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[21]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[21]- (GPIO bank 0) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master + * Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc + * 1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- ( + * UART receiver serial input) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_21_L3_SEL 6 + + * Configures MIO Pin 21 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180054, 0x000000FEU ,0x000000C0U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_21_OFFSET, 0x000000FEU, 0x000000C0U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_22 @ 0XFF180058 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_22_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_we_b- (NAN + * D Write Enable) + * PSU_IOU_SLCR_MIO_PIN_22_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- + * (SDSDIO clock) 2= test_scan, Input, test_scan_in[22]- (Test Scan Port) = + * test_scan, Output, test_scan_out[22]- (Test Scan Port) 3= csu, Input, c + * su_ext_tamper- (CSU Ext Tamper) + * PSU_IOU_SLCR_MIO_PIN_22_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[22]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[22]- (GPIO bank 0) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= + * spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- ( + * TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not U + * sed + * PSU_IOU_SLCR_MIO_PIN_22_L3_SEL 0 + + * Configures MIO Pin 22 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180058, 0x000000FEU ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_22_OFFSET, 0x000000FEU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_23 @ 0XFF18005C + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_23_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[6]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[6]- (NAND Data Bus) + * PSU_IOU_SLCR_MIO_PIN_23_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- + * (SD card bus power) 2= test_scan, Input, test_scan_in[23]- (Test Scan Po + * rt) = test_scan, Output, test_scan_out[23]- (Test Scan Port) 3= csu, Inp + * ut, csu_ext_tamper- (CSU Ext Tamper) + * PSU_IOU_SLCR_MIO_PIN_23_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[23]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[23]- (GPIO bank 0) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) + * 4= spi1, Input, spi1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- ( + * TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial ou + * tput) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_23_L3_SEL 0 + + * Configures MIO Pin 23 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF18005C, 0x000000FEU ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_23_OFFSET, 0x000000FEU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_24 @ 0XFF180060 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_24_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[7]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[7]- (NAND Data Bus) + * PSU_IOU_SLCR_MIO_PIN_24_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD + * card detect from connector) 2= test_scan, Input, test_scan_in[24]- (Test + * Scan Port) = test_scan, Output, test_scan_out[24]- (Test Scan Port) 3= + * csu, Input, csu_ext_tamper- (CSU Ext Tamper) + * PSU_IOU_SLCR_MIO_PIN_24_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[24]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[24]- (GPIO bank 0) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= Not Used 5= ttc3, Input, ttc3_clk_in- (T + * TC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= N + * ot Used + * PSU_IOU_SLCR_MIO_PIN_24_L3_SEL 1 + + * Configures MIO Pin 24 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180060, 0x000000FEU ,0x00000020U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_24_OFFSET, 0x000000FEU, 0x00000020U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_25 @ 0XFF180064 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_25_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_re_n- (NAN + * D Read Enable) + * PSU_IOU_SLCR_MIO_PIN_25_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD ca + * rd write protect from connector) 2= test_scan, Input, test_scan_in[25]- + * (Test Scan Port) = test_scan, Output, test_scan_out[25]- (Test Scan Port + * ) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper) + * PSU_IOU_SLCR_MIO_PIN_25_L2_SEL 0 + + * Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[25]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[25]- (GPIO bank 0) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= Not Used 5= ttc3, Output, ttc3_wave_ou + * t- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial in + * put) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_25_L3_SEL 1 + + * Configures MIO Pin 25 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180064, 0x000000FEU ,0x00000020U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_25_OFFSET, 0x000000FEU, 0x00000020U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_26 @ 0XFF180068 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ + * clk- (TX RGMII clock) + * PSU_IOU_SLCR_MIO_PIN_26_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NA + * ND chip enable) + * PSU_IOU_SLCR_MIO_PIN_26_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[0]- (PMU + * GPI) 2= test_scan, Input, test_scan_in[26]- (Test Scan Port) = test_sca + * n, Output, test_scan_out[26]- (Test Scan Port) 3= csu, Input, csu_ext_ta + * mper- (CSU Ext Tamper) + * PSU_IOU_SLCR_MIO_PIN_26_L2_SEL 0 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[0]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[0]- (GPIO bank 1) 1= can0, Input, can0_phy_ + * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + * , Output, i2c0_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG + * TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_scl + * k_out- (SPI Clock) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Inpu + * t, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- ( + * Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_26_L3_SEL 0 + + * Configures MIO Pin 26 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180068, 0x000000FEU ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_26_OFFSET, 0x000000FEU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_27 @ 0XFF18006C + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd + * [0]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_27_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (N + * AND Ready/Busy) + * PSU_IOU_SLCR_MIO_PIN_27_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[1]- (PMU + * GPI) 2= test_scan, Input, test_scan_in[27]- (Test Scan Port) = test_sca + * n, Output, test_scan_out[27]- (Test Scan Port) 3= dpaux, Input, dp_aux_d + * ata_in- (Dp Aux Data) = dpaux, Output, dp_aux_data_out- (Dp Aux Data) + * PSU_IOU_SLCR_MIO_PIN_27_L2_SEL 3 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[1]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[1]- (GPIO bank 1) 1= can0, Output, can0_phy + * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + * 0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG + * TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc2, O + * utput, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UAR + * T transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port D + * atabus) + * PSU_IOU_SLCR_MIO_PIN_27_L3_SEL 0 + + * Configures MIO Pin 27 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF18006C, 0x000000FEU ,0x00000018U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_27_OFFSET, 0x000000FEU, 0x00000018U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_28 @ 0XFF180070 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd + * [1]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_28_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (N + * AND Ready/Busy) + * PSU_IOU_SLCR_MIO_PIN_28_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[2]- (PMU + * GPI) 2= test_scan, Input, test_scan_in[28]- (Test Scan Port) = test_sca + * n, Output, test_scan_out[28]- (Test Scan Port) 3= dpaux, Input, dp_hot_p + * lug_detect- (Dp Aux Hot Plug) + * PSU_IOU_SLCR_MIO_PIN_28_L2_SEL 3 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[2]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[2]- (GPIO bank 1) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTA + * G TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc1, + * Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitt + * er serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_28_L3_SEL 0 + + * Configures MIO Pin 28 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180070, 0x000000FEU ,0x00000018U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_28_OFFSET, 0x000000FEU, 0x00000018U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_29 @ 0XFF180074 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd + * [2]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_29_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + * PCIE Reset signal) + * PSU_IOU_SLCR_MIO_PIN_29_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[3]- (PMU + * GPI) 2= test_scan, Input, test_scan_in[29]- (Test Scan Port) = test_sca + * n, Output, test_scan_out[29]- (Test Scan Port) 3= dpaux, Input, dp_aux_d + * ata_in- (Dp Aux Data) = dpaux, Output, dp_aux_data_out- (Dp Aux Data) + * PSU_IOU_SLCR_MIO_PIN_29_L2_SEL 3 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[3]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[3]- (GPIO bank 1) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG + * TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, + * spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- + * (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input + * ) 7= trace, Output, tracedq[7]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_29_L3_SEL 0 + + * Configures MIO Pin 29 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180074, 0x000000FEU ,0x00000018U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_29_OFFSET, 0x000000FEU, 0x00000018U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_30 @ 0XFF180078 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd + * [3]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_30_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + * PCIE Reset signal) + * PSU_IOU_SLCR_MIO_PIN_30_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[4]- (PMU + * GPI) 2= test_scan, Input, test_scan_in[30]- (Test Scan Port) = test_sca + * n, Output, test_scan_out[30]- (Test Scan Port) 3= dpaux, Input, dp_hot_p + * lug_detect- (Dp Aux Hot Plug) + * PSU_IOU_SLCR_MIO_PIN_30_L2_SEL 3 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[4]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[4]- (GPIO bank 1) 1= can0, Input, can0_phy_ + * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + * , Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Wat + * ch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0 + * , Output, spi0_so- (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clock + * ) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, + * tracedq[8]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_30_L3_SEL 0 + + * Configures MIO Pin 30 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180078, 0x000000FEU ,0x00000018U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_30_OFFSET, 0x000000FEU, 0x00000018U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_31 @ 0XFF18007C + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ + * ctl- (TX RGMII control) + * PSU_IOU_SLCR_MIO_PIN_31_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + * PCIE Reset signal) + * PSU_IOU_SLCR_MIO_PIN_31_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[5]- (PMU + * GPI) 2= test_scan, Input, test_scan_in[31]- (Test Scan Port) = test_sca + * n, Output, test_scan_out[31]- (Test Scan Port) 3= csu, Input, csu_ext_ta + * mper- (CSU Ext Tamper) + * PSU_IOU_SLCR_MIO_PIN_31_L2_SEL 0 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[5]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[5]- (GPIO bank 1) 1= can0, Output, can0_phy + * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + * 0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- ( + * Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= + * spi0, Input, spi0_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TT + * C Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial outp + * ut) 7= trace, Output, tracedq[9]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_31_L3_SEL 0 + + * Configures MIO Pin 31 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF18007C, 0x000000FEU ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_31_OFFSET, 0x000000FEU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_32 @ 0XFF180080 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_c + * lk- (RX RGMII clock) + * PSU_IOU_SLCR_MIO_PIN_32_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NA + * ND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe) + * PSU_IOU_SLCR_MIO_PIN_32_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[0]- (PM + * U GPI) 2= test_scan, Input, test_scan_in[32]- (Test Scan Port) = test_sc + * an, Output, test_scan_out[32]- (Test Scan Port) 3= csu, Input, csu_ext_t + * amper- (CSU Ext Tamper) + * PSU_IOU_SLCR_MIO_PIN_32_L2_SEL 1 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[6]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[6]- (GPIO bank 1) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Wa + * tch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= + * spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (T + * TC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= t + * race, Output, tracedq[10]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_32_L3_SEL 0 + + * Configures MIO Pin 32 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180080, 0x000000FEU ,0x00000008U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_32_OFFSET, 0x000000FEU, 0x00000008U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_33 @ 0XFF180084 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[ + * 0]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_33_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + * PCIE Reset signal) + * PSU_IOU_SLCR_MIO_PIN_33_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[1]- (PM + * U GPI) 2= test_scan, Input, test_scan_in[33]- (Test Scan Port) = test_sc + * an, Output, test_scan_out[33]- (Test Scan Port) 3= csu, Input, csu_ext_t + * amper- (CSU Ext Tamper) + * PSU_IOU_SLCR_MIO_PIN_33_L2_SEL 1 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[7]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[7]- (GPIO bank 1) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (W + * atch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Mas + * ter Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1 + * , Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq + * [11]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_33_L3_SEL 0 + + * Configures MIO Pin 33 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180084, 0x000000FEU ,0x00000008U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_33_OFFSET, 0x000000FEU, 0x00000008U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_34 @ 0XFF180088 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[ + * 1]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_34_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + * PCIE Reset signal) + * PSU_IOU_SLCR_MIO_PIN_34_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[2]- (PM + * U GPI) 2= test_scan, Input, test_scan_in[34]- (Test Scan Port) = test_sc + * an, Output, test_scan_out[34]- (Test Scan Port) 3= dpaux, Input, dp_aux_ + * data_in- (Dp Aux Data) = dpaux, Output, dp_aux_data_out- (Dp Aux Data) + * PSU_IOU_SLCR_MIO_PIN_34_L2_SEL 1 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[8]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[8]- (GPIO bank 1) 1= can0, Input, can0_phy_ + * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + * , Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Wat + * ch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master + * Selects) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rx + * d- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace Po + * rt Databus) + * PSU_IOU_SLCR_MIO_PIN_34_L3_SEL 0 + + * Configures MIO Pin 34 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180088, 0x000000FEU ,0x00000008U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_34_OFFSET, 0x000000FEU, 0x00000008U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_35 @ 0XFF18008C + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[ + * 2]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_35_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + * PCIE Reset signal) + * PSU_IOU_SLCR_MIO_PIN_35_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[3]- (PM + * U GPI) 2= test_scan, Input, test_scan_in[35]- (Test Scan Port) = test_sc + * an, Output, test_scan_out[35]- (Test Scan Port) 3= dpaux, Input, dp_hot_ + * plug_detect- (Dp Aux Hot Plug) + * PSU_IOU_SLCR_MIO_PIN_35_L2_SEL 1 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[9]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[9]- (GPIO bank 1) 1= can0, Output, can0_phy + * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + * 0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- ( + * Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master + * Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc2 + * , Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- ( + * UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace Po + * rt Databus) + * PSU_IOU_SLCR_MIO_PIN_35_L3_SEL 0 + + * Configures MIO Pin 35 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF18008C, 0x000000FEU ,0x00000008U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_35_OFFSET, 0x000000FEU, 0x00000008U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_36 @ 0XFF180090 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[ + * 3]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_36_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + * PCIE Reset signal) + * PSU_IOU_SLCR_MIO_PIN_36_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[4]- (PM + * U GPI) 2= test_scan, Input, test_scan_in[36]- (Test Scan Port) = test_sc + * an, Output, test_scan_out[36]- (Test Scan Port) 3= dpaux, Input, dp_aux_ + * data_in- (Dp Aux Data) = dpaux, Output, dp_aux_data_out- (Dp Aux Data) + * PSU_IOU_SLCR_MIO_PIN_36_L2_SEL 1 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[10]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[10]- (GPIO bank 1) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= s + * pi1, Output, spi1_so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Cl + * ock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, + * Output, tracedq[14]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_36_L3_SEL 0 + + * Configures MIO Pin 36 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180090, 0x000000FEU ,0x00000008U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_36_OFFSET, 0x000000FEU, 0x00000008U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_37 @ 0XFF180094 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_c + * tl- (RX RGMII control ) + * PSU_IOU_SLCR_MIO_PIN_37_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + * PCIE Reset signal) + * PSU_IOU_SLCR_MIO_PIN_37_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[5]- (PM + * U GPI) 2= test_scan, Input, test_scan_in[37]- (Test Scan Port) = test_sc + * an, Output, test_scan_out[37]- (Test Scan Port) 3= dpaux, Input, dp_hot_ + * plug_detect- (Dp Aux Hot Plug) + * PSU_IOU_SLCR_MIO_PIN_37_L2_SEL 1 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[11]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[11]- (GPIO bank 1) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4 + * = spi1, Input, spi1_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (T + * TC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) + * 7= trace, Output, tracedq[15]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_37_L3_SEL 0 + + * Configures MIO Pin 37 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180094, 0x000000FEU ,0x00000008U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_37_OFFSET, 0x000000FEU, 0x00000008U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_38 @ 0XFF180098 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ + * clk- (TX RGMII clock) + * PSU_IOU_SLCR_MIO_PIN_38_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_38_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- + * (SDSDIO clock) 2= Not Used 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_38_L2_SEL 0 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[12]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[12]- (GPIO bank 1) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTA + * G TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_s + * clk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, In + * put, ua0_rxd- (UART receiver serial input) 7= trace, Output, trace_clk- + * (Trace Port Clock) + * PSU_IOU_SLCR_MIO_PIN_38_L3_SEL 0 + + * Configures MIO Pin 38 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180098, 0x000000FEU ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_38_OFFSET, 0x000000FEU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_39 @ 0XFF18009C + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd + * [0]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_39_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_39_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD + * card detect from connector) 2= sd1, Input, sd1_data_in[4]- (8-bit Data b + * us) = sd1, Output, sdio1_data_out[4]- (8-bit Data bus) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_39_L2_SEL 2 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[13]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[13]- (GPIO bank 1) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJT + * AG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc0, + * Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (U + * ART transmitter serial output) 7= trace, Output, trace_ctl- (Trace Port + * Control Signal) + * PSU_IOU_SLCR_MIO_PIN_39_L3_SEL 0 + + * Configures MIO Pin 39 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF18009C, 0x000000FEU ,0x00000010U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_39_OFFSET, 0x000000FEU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_40 @ 0XFF1800A0 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd + * [1]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_40_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_40_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Com + * mand Indicator) = sd0, Output, sdio0_cmd_out- (Command Indicator) 2= sd1 + * , Input, sd1_data_in[5]- (8-bit Data bus) = sd1, Output, sdio1_data_out[ + * 5]- (8-bit Data bus) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_40_L2_SEL 2 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[14]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[14]- (GPIO bank 1) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJ + * TAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc3 + * , Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmi + * tter serial output) 7= trace, Output, tracedq[0]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_40_L3_SEL 0 + + * Configures MIO Pin 40 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800A0, 0x000000FEU ,0x00000010U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_40_OFFSET, 0x000000FEU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_41 @ 0XFF1800A4 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd + * [2]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_41_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_41_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[6]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[6]- (8-bit Data bus) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_41_L2_SEL 2 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[15]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[15]- (GPIO bank 1) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTA + * G TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Outpu + * t, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out + * - (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial inp + * ut) 7= trace, Output, tracedq[1]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_41_L3_SEL 0 + + * Configures MIO Pin 41 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800A4, 0x000000FEU ,0x00000010U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_41_OFFSET, 0x000000FEU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_42 @ 0XFF1800A8 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd + * [3]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_42_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_42_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[7]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[7]- (8-bit Data bus) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_42_L2_SEL 2 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= sp + * i0, Output, spi0_so- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clo + * ck) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outpu + * t, tracedq[2]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_42_L3_SEL 0 + + * Configures MIO Pin 42 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800A8, 0x000000FEU ,0x00000010U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_42_OFFSET, 0x000000FEU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_43 @ 0XFF1800AC + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ + * ctl- (TX RGMII control) + * PSU_IOU_SLCR_MIO_PIN_43_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_43_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8-bit Data bus) 2= s + * d1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_43_L2_SEL 0 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) + * 4= spi0, Input, spi0_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- ( + * TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial ou + * tput) 7= trace, Output, tracedq[3]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_43_L3_SEL 0 + + * Configures MIO Pin 43 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800AC, 0x000000FEU ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_43_OFFSET, 0x000000FEU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_44 @ 0XFF1800B0 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_c + * lk- (RX RGMII clock) + * PSU_IOU_SLCR_MIO_PIN_44_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_44_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8-bit Data bus) 2= s + * d1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_44_L2_SEL 2 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[18]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[18]- (GPIO bank 1) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4 + * = spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- + * (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= + * Not Used + * PSU_IOU_SLCR_MIO_PIN_44_L3_SEL 0 + + * Configures MIO Pin 44 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800B0, 0x000000FEU ,0x00000010U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_44_OFFSET, 0x000000FEU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_45 @ 0XFF1800B4 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[ + * 0]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_45_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_45_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8-bit Data bus) 2= s + * d1, Input, sdio1_cd_n- (SD card detect from connector) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_45_L2_SEL 2 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[19]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[19]- (GPIO bank 1) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI M + * aster Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= u + * a1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_45_L3_SEL 0 + + * Configures MIO Pin 45 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800B4, 0x000000FEU ,0x00000010U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_45_OFFSET, 0x000000FEU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_46 @ 0XFF1800B8 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[ + * 1]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_46_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_46_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[0]- (8-bit Data bus) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_46_L2_SEL 2 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Mast + * er Selects) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_ + * rxd- (UART receiver serial input) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_46_L3_SEL 0 + + * Configures MIO Pin 46 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800B8, 0x000000FEU ,0x00000010U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_46_OFFSET, 0x000000FEU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_47 @ 0XFF1800BC + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[ + * 2]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_47_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_47_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[1]- (8-bit Data bus) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_47_L2_SEL 2 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Maste + * r Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= tt + * c0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- + * (UART transmitter serial output) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_47_L3_SEL 0 + + * Configures MIO Pin 47 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800BC, 0x000000FEU ,0x00000010U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_47_OFFSET, 0x000000FEU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_48 @ 0XFF1800C0 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[ + * 3]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_48_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_48_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[2]- (8-bit Data bus) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_48_L2_SEL 2 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[22]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[22]- (GPIO bank 1) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= s + * pi1, Output, spi1_so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Cl + * ock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Us + * ed + * PSU_IOU_SLCR_MIO_PIN_48_L3_SEL 0 + + * Configures MIO Pin 48 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800C0, 0x000000FEU ,0x00000010U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_48_OFFSET, 0x000000FEU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_49 @ 0XFF1800C4 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_c + * tl- (RX RGMII control ) + * PSU_IOU_SLCR_MIO_PIN_49_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_49_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- + * (SD card bus power) 2= sd1, Input, sd1_data_in[3]- (8-bit Data bus) = sd + * 1, Output, sdio1_data_out[3]- (8-bit Data bus) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_49_L2_SEL 2 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[23]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[23]- (GPIO bank 1) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4 + * = spi1, Input, spi1_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (T + * TC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) + * 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_49_L3_SEL 0 + + * Configures MIO Pin 49 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800C4, 0x000000FEU ,0x00000010U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_49_OFFSET, 0x000000FEU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_50 @ 0XFF1800C8 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- + * (TSU clock) + * PSU_IOU_SLCR_MIO_PIN_50_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_50_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD ca + * rd write protect from connector) 2= sd1, Input, sd1_cmd_in- (Command Ind + * icator) = sd1, Output, sdio1_cmd_out- (Command Indicator) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_50_L2_SEL 2 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[24]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[24]- (GPIO bank 1) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= + * ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART rece + * iver serial input) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_50_L3_SEL 0 + + * Configures MIO Pin 50 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800C8, 0x000000FEU ,0x00000010U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_50_OFFSET, 0x000000FEU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_51 @ 0XFF1800CC + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- + * (TSU clock) + * PSU_IOU_SLCR_MIO_PIN_51_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_51_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Output, sdi + * o1_clk_out- (SDSDIO clock) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_51_L2_SEL 2 + + * Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[25]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[25]- (GPIO bank 1) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= mdio1, Input, gem1_mdio_in- (MDIO Dat + * a) 4= mdio1, Output, gem1_mdio_out- (MDIO Data) 5= ttc2, Output, ttc2_wa + * ve_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter + * serial output) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_51_L3_SEL 0 + + * Configures MIO Pin 51 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800CC, 0x000000FEU ,0x00000010U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_51_OFFSET, 0x000000FEU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_52 @ 0XFF1800D0 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_ + * clk- (TX RGMII clock) + * PSU_IOU_SLCR_MIO_PIN_52_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_clk_i + * n- (ULPI Clock) + * PSU_IOU_SLCR_MIO_PIN_52_L1_SEL 1 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used + * PSU_IOU_SLCR_MIO_PIN_52_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[0]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[0]- (GPIO bank 2) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG + * TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sc + * lk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Out + * put, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_c + * lk- (Trace Port Clock) + * PSU_IOU_SLCR_MIO_PIN_52_L3_SEL 0 + + * Configures MIO Pin 52 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800D0, 0x000000FEU ,0x00000004U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_52_OFFSET, 0x000000FEU, 0x00000004U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_53 @ 0XFF1800D4 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd + * [0]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_53_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_dir- + * (Data bus direction control) + * PSU_IOU_SLCR_MIO_PIN_53_L1_SEL 1 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used + * PSU_IOU_SLCR_MIO_PIN_53_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[1]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[1]- (GPIO bank 2) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG + * TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Ou + * tput, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART + * receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control + * Signal) + * PSU_IOU_SLCR_MIO_PIN_53_L3_SEL 0 + + * Configures MIO Pin 53 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800D4, 0x000000FEU ,0x00000004U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_53_OFFSET, 0x000000FEU, 0x00000004U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_54 @ 0XFF1800D8 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd + * [1]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_54_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[2]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[2]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_54_L1_SEL 1 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used + * PSU_IOU_SLCR_MIO_PIN_54_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[2]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[2]- (GPIO bank 2) 1= can0, Input, can0_phy_ + * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + * , Output, i2c0_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTAG + * TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, I + * nput, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver se + * rial input) 7= trace, Output, tracedq[0]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_54_L3_SEL 0 + + * Configures MIO Pin 54 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800D8, 0x000000FEU ,0x00000004U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_54_OFFSET, 0x000000FEU, 0x00000004U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_55 @ 0XFF1800DC + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd + * [2]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_55_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_nxt- + * (Data flow control signal from the PHY) + * PSU_IOU_SLCR_MIO_PIN_55_L1_SEL 1 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used + * PSU_IOU_SLCR_MIO_PIN_55_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[3]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[3]- (GPIO bank 2) 1= can0, Output, can0_phy + * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + * 0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG + * TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output + * , spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- + * (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial + * output) 7= trace, Output, tracedq[1]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_55_L3_SEL 0 + + * Configures MIO Pin 55 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800DC, 0x000000FEU ,0x00000004U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_55_OFFSET, 0x000000FEU, 0x00000004U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_56 @ 0XFF1800E0 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd + * [3]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_56_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[0]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[0]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_56_L1_SEL 1 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used + * PSU_IOU_SLCR_MIO_PIN_56_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[4]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[4]- (GPIO bank 2) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Wa + * tch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi + * 0, Output, spi0_so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Cloc + * k) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, O + * utput, tracedq[2]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_56_L3_SEL 0 + + * Configures MIO Pin 56 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800E0, 0x000000FEU ,0x00000004U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_56_OFFSET, 0x000000FEU, 0x00000004U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_57 @ 0XFF1800E4 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_ + * ctl- (TX RGMII control) + * PSU_IOU_SLCR_MIO_PIN_57_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[1]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[1]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_57_L1_SEL 1 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used + * PSU_IOU_SLCR_MIO_PIN_57_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[5]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[5]- (GPIO bank 2) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (W + * atch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= + * spi0, Input, spi0_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC + * Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= + * trace, Output, tracedq[3]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_57_L3_SEL 0 + + * Configures MIO Pin 57 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800E4, 0x000000FEU ,0x00000004U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_57_OFFSET, 0x000000FEU, 0x00000004U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_58 @ 0XFF1800E8 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_c + * lk- (RX RGMII clock) + * PSU_IOU_SLCR_MIO_PIN_58_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Output, usb0_ulpi_stp- + * (Asserted to end or interrupt transfers) + * PSU_IOU_SLCR_MIO_PIN_58_L1_SEL 1 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used + * PSU_IOU_SLCR_MIO_PIN_58_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[6]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[6]- (GPIO bank 2) 1= can0, Input, can0_phy_ + * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + * , Output, i2c0_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG + * TCK) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1_scl + * k_out- (SPI Clock) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Inpu + * t, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- ( + * Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_58_L3_SEL 0 + + * Configures MIO Pin 58 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800E8, 0x000000FEU ,0x00000004U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_58_OFFSET, 0x000000FEU, 0x00000004U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_59 @ 0XFF1800EC + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[ + * 0]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_59_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[3]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[3]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_59_L1_SEL 1 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used + * PSU_IOU_SLCR_MIO_PIN_59_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[7]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[7]- (GPIO bank 2) 1= can0, Output, can0_phy + * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + * 0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG + * TDI) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= ttc2, O + * utput, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UAR + * T transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port D + * atabus) + * PSU_IOU_SLCR_MIO_PIN_59_L3_SEL 0 + + * Configures MIO Pin 59 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800EC, 0x000000FEU ,0x00000004U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_59_OFFSET, 0x000000FEU, 0x00000004U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_60 @ 0XFF1800F0 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[ + * 1]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_60_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[4]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[4]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_60_L1_SEL 1 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used + * PSU_IOU_SLCR_MIO_PIN_60_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[8]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[8]- (GPIO bank 2) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTA + * G TDO) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc1, + * Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitt + * er serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_60_L3_SEL 0 + + * Configures MIO Pin 60 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800F0, 0x000000FEU ,0x00000004U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_60_OFFSET, 0x000000FEU, 0x00000004U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_61 @ 0XFF1800F4 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[ + * 2]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_61_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[5]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[5]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_61_L1_SEL 1 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used + * PSU_IOU_SLCR_MIO_PIN_61_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[9]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[9]- (GPIO bank 2) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG + * TMS) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, Output, + * spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- + * (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input + * ) 7= trace, Output, tracedq[7]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_61_L3_SEL 0 + + * Configures MIO Pin 61 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800F4, 0x000000FEU ,0x00000004U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_61_OFFSET, 0x000000FEU, 0x00000004U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_62 @ 0XFF1800F8 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[ + * 3]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_62_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[6]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[6]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_62_L1_SEL 1 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used + * PSU_IOU_SLCR_MIO_PIN_62_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[10]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[10]- (GPIO bank 2) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= sp + * i1, Output, spi1_so- (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clo + * ck) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outpu + * t, tracedq[8]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_62_L3_SEL 0 + + * Configures MIO Pin 62 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800F8, 0x000000FEU ,0x00000004U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_62_OFFSET, 0x000000FEU, 0x00000004U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_63 @ 0XFF1800FC + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_c + * tl- (RX RGMII control ) + * PSU_IOU_SLCR_MIO_PIN_63_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[7]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[7]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_63_L1_SEL 1 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used + * PSU_IOU_SLCR_MIO_PIN_63_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[11]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[11]- (GPIO bank 2) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) + * 4= spi1, Input, spi1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- ( + * TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial ou + * tput) 7= trace, Output, tracedq[9]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_63_L3_SEL 0 + + * Configures MIO Pin 63 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF1800FC, 0x000000FEU ,0x00000004U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_63_OFFSET, 0x000000FEU, 0x00000004U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_64 @ 0XFF180100 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_ + * clk- (TX RGMII clock) + * PSU_IOU_SLCR_MIO_PIN_64_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_clk_i + * n- (ULPI Clock) + * PSU_IOU_SLCR_MIO_PIN_64_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- + * (SDSDIO clock) 2= Not Used 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_64_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[12]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[12]- (GPIO bank 2) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4 + * = spi0, Output, spi0_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- + * (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= + * trace, Output, tracedq[10]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_64_L3_SEL 0 + + * Configures MIO Pin 64 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180100, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_64_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_65 @ 0XFF180104 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd + * [0]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_65_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_dir- + * (Data bus direction control) + * PSU_IOU_SLCR_MIO_PIN_65_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD + * card detect from connector) 2= Not Used 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_65_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[13]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[13]- (GPIO bank 2) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi0, Output, spi0_n_ss_out[2]- (SPI M + * aster Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= u + * a1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trace + * dq[11]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_65_L3_SEL 0 + + * Configures MIO Pin 65 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180104, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_65_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_66 @ 0XFF180108 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd + * [1]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_66_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[2]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[2]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_66_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Com + * mand Indicator) = sd0, Output, sdio0_cmd_out- (Command Indicator) 2= Not + * Used 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_66_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[14]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[14]- (GPIO bank 2) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Mast + * er Selects) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_ + * rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace + * Port Databus) + * PSU_IOU_SLCR_MIO_PIN_66_L3_SEL 0 + + * Configures MIO Pin 66 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180108, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_66_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_67 @ 0XFF18010C + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd + * [2]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_67_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_nxt- + * (Data flow control signal from the PHY) + * PSU_IOU_SLCR_MIO_PIN_67_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8-bit Data bus) 2= N + * ot Used 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_67_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[15]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[15]- (GPIO bank 2) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi0, Input, spi0_n_ss_in- (SPI Maste + * r Selects) 4= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 5= tt + * c2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- + * (UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace + * Port Databus) + * PSU_IOU_SLCR_MIO_PIN_67_L3_SEL 0 + + * Configures MIO Pin 67 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF18010C, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_67_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_68 @ 0XFF180110 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd + * [3]- (TX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_68_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[0]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[0]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_68_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8-bit Data bus) 2= N + * ot Used 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_68_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[16]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[16]- (GPIO bank 2) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= s + * pi0, Output, spi0_so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Cl + * ock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, + * Output, tracedq[14]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_68_L3_SEL 0 + + * Configures MIO Pin 68 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180110, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_68_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_69 @ 0XFF180114 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_ + * ctl- (TX RGMII control) + * PSU_IOU_SLCR_MIO_PIN_69_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[1]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[1]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_69_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8-bit Data bus) 2= s + * d1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_69_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[17]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[17]- (GPIO bank 2) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4 + * = spi0, Input, spi0_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (T + * TC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) + * 7= trace, Output, tracedq[15]- (Trace Port Databus) + * PSU_IOU_SLCR_MIO_PIN_69_L3_SEL 0 + + * Configures MIO Pin 69 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180114, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_69_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_70 @ 0XFF180118 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_c + * lk- (RX RGMII clock) + * PSU_IOU_SLCR_MIO_PIN_70_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Output, usb1_ulpi_stp- + * (Asserted to end or interrupt transfers) + * PSU_IOU_SLCR_MIO_PIN_70_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8-bit Data bus) 2= s + * d1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_70_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[18]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[18]- (GPIO bank 2) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= + * spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- ( + * TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not U + * sed + * PSU_IOU_SLCR_MIO_PIN_70_L3_SEL 0 + + * Configures MIO Pin 70 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180118, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_70_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_71 @ 0XFF18011C + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[ + * 0]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_71_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[3]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[3]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_71_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[0]- (8-bit Data bus) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_71_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[19]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[19]- (GPIO bank 2) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI + * Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= + * ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_71_L3_SEL 0 + + * Configures MIO Pin 71 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF18011C, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_71_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_72 @ 0XFF180120 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[ + * 1]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_72_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[4]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[4]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_72_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[1]- (8-bit Data bus) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_72_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[20]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[20]- (GPIO bank 2) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Mas + * ter Selects) 5= Not Used 6= ua1, Output, ua1_txd- (UART transmitter seri + * al output) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_72_L3_SEL 0 + + * Configures MIO Pin 72 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180120, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_72_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_73 @ 0XFF180124 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[ + * 2]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_73_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[5]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_73_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[2]- (8-bit Data bus) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_73_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[21]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[21]- (GPIO bank 2) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master + * Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= Not + * Used 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_73_L3_SEL 0 + + * Configures MIO Pin 73 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180124, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_73_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_74 @ 0XFF180128 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[ + * 3]- (RX RGMII data) + * PSU_IOU_SLCR_MIO_PIN_74_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[6]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[6]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_74_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[3]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[3]- (8-bit Data bus) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_74_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[22]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[22]- (GPIO bank 2) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= sp + * i1, Output, spi1_so- (MISO signal) 5= Not Used 6= ua0, Input, ua0_rxd- ( + * UART receiver serial input) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_74_L3_SEL 0 + + * Configures MIO Pin 74 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180128, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_74_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_75 @ 0XFF18012C + + * Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_c + * tl- (RX RGMII control ) + * PSU_IOU_SLCR_MIO_PIN_75_L0_SEL 1 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[7]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[7]- (ULPI data + * bus) + * PSU_IOU_SLCR_MIO_PIN_75_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- + * (SD card bus power) 2= sd1, Input, sd1_cmd_in- (Command Indicator) = sd1 + * , Output, sdio1_cmd_out- (Command Indicator) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_75_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[23]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[23]- (GPIO bank 2) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) + * 4= spi1, Input, spi1_si- (MOSI signal) 5= Not Used 6= ua0, Output, ua0_t + * xd- (UART transmitter serial output) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_75_L3_SEL 0 + + * Configures MIO Pin 75 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF18012C, 0x000000FEU ,0x00000002U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_75_OFFSET, 0x000000FEU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_76 @ 0XFF180130 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_76_L0_SEL 0 + + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_76_L1_SEL 0 + + * Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD ca + * rd write protect from connector) 2= sd1, Output, sdio1_clk_out- (SDSDIO + * clock) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_76_L2_SEL 0 + + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[24]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[24]- (GPIO bank 2) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= mdio0, Output, gem0_mdc- (MDI + * O Clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= mdio2, Output, gem2 + * _mdc- (MDIO Clock) 6= mdio3, Output, gem3_mdc- (MDIO Clock) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_76_L3_SEL 6 + + * Configures MIO Pin 76 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180130, 0x000000FEU ,0x000000C0U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_76_OFFSET, 0x000000FEU, 0x000000C0U); +/*##################################################################### */ + + /* + * Register : MIO_PIN_77 @ 0XFF180134 + + * Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_77_L0_SEL 0 - Block level reset - PSU_CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET 0 + * Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used + * PSU_IOU_SLCR_MIO_PIN_77_L1_SEL 0 - Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset. - (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00100000U ,0x00000000U) - RegMask = (CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_MASK | 0 ); + * Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Input, sdio + * 1_cd_n- (SD card detect from connector) 3= Not Used + * PSU_IOU_SLCR_MIO_PIN_77_L2_SEL 0 - RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RST_LPD_IOU2_OFFSET ,0x00100000U ,0x00000000U); - /*############################################################################################################################ */ + * Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[25]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[25]- (GPIO bank 2) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= mdio0, Input, gem0_mdio_in- (M + * DIO Data) 3= mdio0, Output, gem0_mdio_out- (MDIO Data) 4= mdio1, Input, + * gem1_mdio_in- (MDIO Data) 4= mdio1, Output, gem1_mdio_out- (MDIO Data) 5 + * = mdio2, Input, gem2_mdio_in- (MDIO Data) 5= mdio2, Output, gem2_mdio_ou + * t- (MDIO Data) 6= mdio3, Input, gem3_mdio_in- (MDIO Data) 6= mdio3, Outp + * ut, gem3_mdio_out- (MDIO Data) 7= Not Used + * PSU_IOU_SLCR_MIO_PIN_77_L3_SEL 6 - // : ENET - /*Register : RST_LPD_IOU0 @ 0XFF5E0230

+ * Configures MIO Pin 77 peripheral interface mapping + * (OFFSET, MASK, VALUE) (0XFF180134, 0x000000FEU ,0x000000C0U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_PIN_77_OFFSET, 0x000000FEU, 0x000000C0U); +/*##################################################################### */ - GEM 3 reset - PSU_CRL_APB_RST_LPD_IOU0_GEM3_RESET 0 + /* + * Register : MIO_MST_TRI0 @ 0XFF180204 - Software controlled reset for the GEMs - (OFFSET, MASK, VALUE) (0XFF5E0230, 0x00000008U ,0x00000000U) - RegMask = (CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK | 0 ); + * Master Tri-state Enable for pin 0, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI 0 - RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RST_LPD_IOU0_OFFSET ,0x00000008U ,0x00000000U); - /*############################################################################################################################ */ + * Master Tri-state Enable for pin 1, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI 0 - // : QSPI - /*Register : RST_LPD_IOU2 @ 0XFF5E0238

+ * Master Tri-state Enable for pin 2, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI 0 - Block level reset - PSU_CRL_APB_RST_LPD_IOU2_QSPI_RESET 0 + * Master Tri-state Enable for pin 3, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI 0 - Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset. - (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000001U ,0x00000000U) - RegMask = (CRL_APB_RST_LPD_IOU2_QSPI_RESET_MASK | 0 ); + * Master Tri-state Enable for pin 4, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI 0 - RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU2_QSPI_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RST_LPD_IOU2_OFFSET ,0x00000001U ,0x00000000U); - /*############################################################################################################################ */ + * Master Tri-state Enable for pin 5, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI 0 - // : QSPI TAP DELAY - /*Register : IOU_TAPDLY_BYPASS @ 0XFF180390

+ * Master Tri-state Enable for pin 6, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI 0 - 0: Do not by pass the tap delays on the Rx clock signal of LQSPI 1: Bypass the Tap delay on the Rx clock signal of LQSPI - PSU_IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX 1 + * Master Tri-state Enable for pin 7, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI 0 - IOU tap delay bypass for the LQSPI and NAND controllers - (OFFSET, MASK, VALUE) (0XFF180390, 0x00000004U ,0x00000004U) - RegMask = (IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_MASK | 0 ); + * Master Tri-state Enable for pin 8, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI 0 - RegVal = ((0x00000001U << IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_IOU_TAPDLY_BYPASS_OFFSET ,0x00000004U ,0x00000004U); - /*############################################################################################################################ */ + * Master Tri-state Enable for pin 9, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI 0 - // : NAND - // : USB - /*Register : RST_LPD_TOP @ 0XFF5E023C

+ * Master Tri-state Enable for pin 10, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI 0 - USB 0 reset for control registers - PSU_CRL_APB_RST_LPD_TOP_USB0_APB_RESET 0 + * Master Tri-state Enable for pin 11, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI 0 - USB 0 sleep circuit reset - PSU_CRL_APB_RST_LPD_TOP_USB0_HIBERRESET 0 + * Master Tri-state Enable for pin 12, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI 0 - USB 0 reset - PSU_CRL_APB_RST_LPD_TOP_USB0_CORERESET 0 + * Master Tri-state Enable for pin 13, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI 0 - Software control register for the LPD block. - (OFFSET, MASK, VALUE) (0XFF5E023C, 0x00000540U ,0x00000000U) - RegMask = (CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK | CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK | CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK | 0 ); + * Master Tri-state Enable for pin 14, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI 0 - RegVal = ((0x00000000U << CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT - | 0x00000000U << CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT - | 0x00000000U << CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RST_LPD_TOP_OFFSET ,0x00000540U ,0x00000000U); - /*############################################################################################################################ */ + * Master Tri-state Enable for pin 15, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI 0 - // : FPD RESET - /*Register : RST_FPD_TOP @ 0XFD1A0100

+ * Master Tri-state Enable for pin 16, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI 0 - PCIE config reset - PSU_CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET 0 + * Master Tri-state Enable for pin 17, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI 0 - PCIE control block level reset - PSU_CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET 0 + * Master Tri-state Enable for pin 18, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI 1 - PCIE bridge block level reset (AXI interface) - PSU_CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET 0 + * Master Tri-state Enable for pin 19, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI 0 - Display Port block level reset (includes DPDMA) - PSU_CRF_APB_RST_FPD_TOP_DP_RESET 0 + * Master Tri-state Enable for pin 20, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI 0 - FPD WDT reset - PSU_CRF_APB_RST_FPD_TOP_SWDT_RESET 0 + * Master Tri-state Enable for pin 21, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI 1 - GDMA block level reset - PSU_CRF_APB_RST_FPD_TOP_GDMA_RESET 0 + * Master Tri-state Enable for pin 22, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI 0 - Pixel Processor (submodule of GPU) block level reset - PSU_CRF_APB_RST_FPD_TOP_GPU_PP0_RESET 0 + * Master Tri-state Enable for pin 23, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI 0 - Pixel Processor (submodule of GPU) block level reset - PSU_CRF_APB_RST_FPD_TOP_GPU_PP1_RESET 0 + * Master Tri-state Enable for pin 24, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI 0 - GPU block level reset - PSU_CRF_APB_RST_FPD_TOP_GPU_RESET 0 + * Master Tri-state Enable for pin 25, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI 1 - GT block level reset - PSU_CRF_APB_RST_FPD_TOP_GT_RESET 0 + * Master Tri-state Enable for pin 26, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI 0 - Sata block level reset - PSU_CRF_APB_RST_FPD_TOP_SATA_RESET 0 + * Master Tri-state Enable for pin 27, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI 0 - FPD Block level software controlled reset - (OFFSET, MASK, VALUE) (0XFD1A0100, 0x000F807EU ,0x00000000U) - RegMask = (CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK | CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK | CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK | CRF_APB_RST_FPD_TOP_DP_RESET_MASK | CRF_APB_RST_FPD_TOP_SWDT_RESET_MASK | CRF_APB_RST_FPD_TOP_GDMA_RESET_MASK | CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_MASK | CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_MASK | CRF_APB_RST_FPD_TOP_GPU_RESET_MASK | CRF_APB_RST_FPD_TOP_GT_RESET_MASK | CRF_APB_RST_FPD_TOP_SATA_RESET_MASK | 0 ); + * Master Tri-state Enable for pin 28, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI 1 - RegVal = ((0x00000000U << CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT - | 0x00000000U << CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT - | 0x00000000U << CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT - | 0x00000000U << CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT - | 0x00000000U << CRF_APB_RST_FPD_TOP_SWDT_RESET_SHIFT - | 0x00000000U << CRF_APB_RST_FPD_TOP_GDMA_RESET_SHIFT - | 0x00000000U << CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_SHIFT - | 0x00000000U << CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_SHIFT - | 0x00000000U << CRF_APB_RST_FPD_TOP_GPU_RESET_SHIFT - | 0x00000000U << CRF_APB_RST_FPD_TOP_GT_RESET_SHIFT - | 0x00000000U << CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_RST_FPD_TOP_OFFSET ,0x000F807EU ,0x00000000U); - /*############################################################################################################################ */ + * Master Tri-state Enable for pin 29, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI 0 - // : SD - /*Register : RST_LPD_IOU2 @ 0XFF5E0238

+ * Master Tri-state Enable for pin 30, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI 1 - Block level reset - PSU_CRL_APB_RST_LPD_IOU2_SDIO1_RESET 0 + * Master Tri-state Enable for pin 31, active high + * PSU_IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI 0 - Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset. - (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000040U ,0x00000000U) - RegMask = (CRL_APB_RST_LPD_IOU2_SDIO1_RESET_MASK | 0 ); + * MIO pin Tri-state Enables, 31:0 + * (OFFSET, MASK, VALUE) (0XFF180204, 0xFFFFFFFFU ,0x52240000U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_MST_TRI0_OFFSET, + 0xFFFFFFFFU, 0x52240000U); +/*##################################################################### */ - RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU2_SDIO1_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RST_LPD_IOU2_OFFSET ,0x00000040U ,0x00000000U); - /*############################################################################################################################ */ + /* + * Register : MIO_MST_TRI1 @ 0XFF180208 - /*Register : CTRL_REG_SD @ 0XFF180310

+ * Master Tri-state Enable for pin 32, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI 0 - SD or eMMC selection on SDIO1 0: SD enabled 1: eMMC enabled - PSU_IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL 0 + * Master Tri-state Enable for pin 33, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI 0 - SD eMMC selection - (OFFSET, MASK, VALUE) (0XFF180310, 0x00008000U ,0x00000000U) - RegMask = (IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_MASK | 0 ); + * Master Tri-state Enable for pin 34, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI 0 - RegVal = ((0x00000000U << IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_CTRL_REG_SD_OFFSET ,0x00008000U ,0x00000000U); - /*############################################################################################################################ */ + * Master Tri-state Enable for pin 35, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI 0 - /*Register : SD_CONFIG_REG2 @ 0XFF180320

+ * Master Tri-state Enable for pin 36, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI 0 - Should be set based on the final product usage 00 - Removable SCard Slot 01 - Embedded Slot for One Device 10 - Shared Bus Sl - t 11 - Reserved - PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE 0 + * Master Tri-state Enable for pin 37, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI 0 - 1.8V Support 1: 1.8V supported 0: 1.8V not supported support - PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V 0 + * Master Tri-state Enable for pin 38, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI 0 - 3.0V Support 1: 3.0V supported 0: 3.0V not supported support - PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V 0 + * Master Tri-state Enable for pin 39, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI 0 - 3.3V Support 1: 3.3V supported 0: 3.3V not supported support - PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V 1 + * Master Tri-state Enable for pin 40, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI 0 - SD Config Register 2 - (OFFSET, MASK, VALUE) (0XFF180320, 0x33800000U ,0x00800000U) - RegMask = (IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_MASK | IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_MASK | IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_MASK | IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_MASK | 0 ); + * Master Tri-state Enable for pin 41, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI 0 - RegVal = ((0x00000000U << IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_SHIFT - | 0x00000000U << IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_SHIFT - | 0x00000000U << IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_SHIFT - | 0x00000001U << IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_SD_CONFIG_REG2_OFFSET ,0x33800000U ,0x00800000U); - /*############################################################################################################################ */ + * Master Tri-state Enable for pin 42, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI 0 - // : SD1 BASE CLOCK - /*Register : SD_CONFIG_REG1 @ 0XFF18031C

+ * Master Tri-state Enable for pin 43, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI 0 - Base Clock Frequency for SD Clock. This is the frequency of the xin_clk. - PSU_IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK 0xc7 + * Master Tri-state Enable for pin 44, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI 1 - SD Config Register 1 - (OFFSET, MASK, VALUE) (0XFF18031C, 0x7F800000U ,0x63800000U) - RegMask = (IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_MASK | 0 ); + * Master Tri-state Enable for pin 45, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI 1 - RegVal = ((0x000000C7U << IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_SD_CONFIG_REG1_OFFSET ,0x7F800000U ,0x63800000U); - /*############################################################################################################################ */ + * Master Tri-state Enable for pin 46, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI 0 - // : SD1 RETUNER - /*Register : SD_CONFIG_REG3 @ 0XFF180324

+ * Master Tri-state Enable for pin 47, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI 0 - This is the Timer Count for Re-Tuning Timer for Re-Tuning Mode 1 to 3. Setting to 4'b0 disables Re-Tuning Timer. 0h - Get inf - rmation via other source 1h = 1 seconds 2h = 2 seconds 3h = 4 seconds 4h = 8 seconds -- n = 2(n-1) seconds -- Bh = 1024 secon - s Fh - Ch = Reserved - PSU_IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR 0X0 + * Master Tri-state Enable for pin 48, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI 0 - SD Config Register 3 - (OFFSET, MASK, VALUE) (0XFF180324, 0x03C00000U ,0x00000000U) - RegMask = (IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_MASK | 0 ); - - RegVal = ((0x00000000U << IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SLCR_SD_CONFIG_REG3_OFFSET ,0x03C00000U ,0x00000000U); - /*############################################################################################################################ */ + * Master Tri-state Enable for pin 49, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI 0 - // : CAN - /*Register : RST_LPD_IOU2 @ 0XFF5E0238

+ * Master Tri-state Enable for pin 50, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI 0 - Block level reset - PSU_CRL_APB_RST_LPD_IOU2_CAN1_RESET 0 + * Master Tri-state Enable for pin 51, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI 0 - Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset. - (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000100U ,0x00000000U) - RegMask = (CRL_APB_RST_LPD_IOU2_CAN1_RESET_MASK | 0 ); + * Master Tri-state Enable for pin 52, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI 1 - RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU2_CAN1_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RST_LPD_IOU2_OFFSET ,0x00000100U ,0x00000000U); - /*############################################################################################################################ */ + * Master Tri-state Enable for pin 53, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI 1 - // : I2C - /*Register : RST_LPD_IOU2 @ 0XFF5E0238

+ * Master Tri-state Enable for pin 54, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI 0 - Block level reset - PSU_CRL_APB_RST_LPD_IOU2_I2C0_RESET 0 + * Master Tri-state Enable for pin 55, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI 1 - Block level reset - PSU_CRL_APB_RST_LPD_IOU2_I2C1_RESET 0 + * Master Tri-state Enable for pin 56, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI 0 - Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset. - (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000600U ,0x00000000U) - RegMask = (CRL_APB_RST_LPD_IOU2_I2C0_RESET_MASK | CRL_APB_RST_LPD_IOU2_I2C1_RESET_MASK | 0 ); + * Master Tri-state Enable for pin 57, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI 0 - RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU2_I2C0_RESET_SHIFT - | 0x00000000U << CRL_APB_RST_LPD_IOU2_I2C1_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RST_LPD_IOU2_OFFSET ,0x00000600U ,0x00000000U); - /*############################################################################################################################ */ + * Master Tri-state Enable for pin 58, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI 0 - // : SWDT - /*Register : RST_LPD_IOU2 @ 0XFF5E0238

+ * Master Tri-state Enable for pin 59, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI 0 - Block level reset - PSU_CRL_APB_RST_LPD_IOU2_SWDT_RESET 0 + * Master Tri-state Enable for pin 60, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI 0 - Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset. - (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00008000U ,0x00000000U) - RegMask = (CRL_APB_RST_LPD_IOU2_SWDT_RESET_MASK | 0 ); + * Master Tri-state Enable for pin 61, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI 0 - RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU2_SWDT_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RST_LPD_IOU2_OFFSET ,0x00008000U ,0x00000000U); - /*############################################################################################################################ */ + * Master Tri-state Enable for pin 62, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI 0 - // : SPI - // : TTC - /*Register : RST_LPD_IOU2 @ 0XFF5E0238

+ * Master Tri-state Enable for pin 63, active high + * PSU_IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI 0 - Block level reset - PSU_CRL_APB_RST_LPD_IOU2_TTC0_RESET 0 + * MIO pin Tri-state Enables, 63:32 + * (OFFSET, MASK, VALUE) (0XFF180208, 0xFFFFFFFFU ,0x00B03000U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_MST_TRI1_OFFSET, + 0xFFFFFFFFU, 0x00B03000U); +/*##################################################################### */ - Block level reset - PSU_CRL_APB_RST_LPD_IOU2_TTC1_RESET 0 + /* + * Register : MIO_MST_TRI2 @ 0XFF18020C - Block level reset - PSU_CRL_APB_RST_LPD_IOU2_TTC2_RESET 0 + * Master Tri-state Enable for pin 64, active high + * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI 0 - Block level reset - PSU_CRL_APB_RST_LPD_IOU2_TTC3_RESET 0 + * Master Tri-state Enable for pin 65, active high + * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI 0 - Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset. - (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00007800U ,0x00000000U) - RegMask = (CRL_APB_RST_LPD_IOU2_TTC0_RESET_MASK | CRL_APB_RST_LPD_IOU2_TTC1_RESET_MASK | CRL_APB_RST_LPD_IOU2_TTC2_RESET_MASK | CRL_APB_RST_LPD_IOU2_TTC3_RESET_MASK | 0 ); + * Master Tri-state Enable for pin 66, active high + * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI 0 - RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU2_TTC0_RESET_SHIFT - | 0x00000000U << CRL_APB_RST_LPD_IOU2_TTC1_RESET_SHIFT - | 0x00000000U << CRL_APB_RST_LPD_IOU2_TTC2_RESET_SHIFT - | 0x00000000U << CRL_APB_RST_LPD_IOU2_TTC3_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RST_LPD_IOU2_OFFSET ,0x00007800U ,0x00000000U); - /*############################################################################################################################ */ + * Master Tri-state Enable for pin 67, active high + * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI 0 - // : UART - /*Register : RST_LPD_IOU2 @ 0XFF5E0238

+ * Master Tri-state Enable for pin 68, active high + * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI 0 - Block level reset - PSU_CRL_APB_RST_LPD_IOU2_UART0_RESET 0 + * Master Tri-state Enable for pin 69, active high + * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI 0 - Block level reset - PSU_CRL_APB_RST_LPD_IOU2_UART1_RESET 0 + * Master Tri-state Enable for pin 70, active high + * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI 1 - Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset. - (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000006U ,0x00000000U) - RegMask = (CRL_APB_RST_LPD_IOU2_UART0_RESET_MASK | CRL_APB_RST_LPD_IOU2_UART1_RESET_MASK | 0 ); + * Master Tri-state Enable for pin 71, active high + * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI 1 - RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU2_UART0_RESET_SHIFT - | 0x00000000U << CRL_APB_RST_LPD_IOU2_UART1_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RST_LPD_IOU2_OFFSET ,0x00000006U ,0x00000000U); - /*############################################################################################################################ */ + * Master Tri-state Enable for pin 72, active high + * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI 1 - // : UART BAUD RATE - /*Register : Baud_rate_divider_reg0 @ 0XFF000034

+ * Master Tri-state Enable for pin 73, active high + * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI 1 - Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate - PSU_UART0_BAUD_RATE_DIVIDER_REG0_BDIV 0x5 + * Master Tri-state Enable for pin 74, active high + * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI 1 - Baud Rate Divider Register - (OFFSET, MASK, VALUE) (0XFF000034, 0x000000FFU ,0x00000005U) - RegMask = (UART0_BAUD_RATE_DIVIDER_REG0_BDIV_MASK | 0 ); + * Master Tri-state Enable for pin 75, active high + * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI 1 - RegVal = ((0x00000005U << UART0_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (UART0_BAUD_RATE_DIVIDER_REG0_OFFSET ,0x000000FFU ,0x00000005U); - /*############################################################################################################################ */ + * Master Tri-state Enable for pin 76, active high + * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI 0 - /*Register : Baud_rate_gen_reg0 @ 0XFF000018

+ * Master Tri-state Enable for pin 77, active high + * PSU_IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI 0 - Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample - PSU_UART0_BAUD_RATE_GEN_REG0_CD 0x8f + * MIO pin Tri-state Enables, 77:64 + * (OFFSET, MASK, VALUE) (0XFF18020C, 0x00003FFFU ,0x00000FC0U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_MST_TRI2_OFFSET, + 0x00003FFFU, 0x00000FC0U); +/*##################################################################### */ - Baud Rate Generator Register. - (OFFSET, MASK, VALUE) (0XFF000018, 0x0000FFFFU ,0x0000008FU) - RegMask = (UART0_BAUD_RATE_GEN_REG0_CD_MASK | 0 ); + /* + * Register : bank0_ctrl0 @ 0XFF180138 - RegVal = ((0x0000008FU << UART0_BAUD_RATE_GEN_REG0_CD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (UART0_BAUD_RATE_GEN_REG0_OFFSET ,0x0000FFFFU ,0x0000008FU); - /*############################################################################################################################ */ + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0 1 - /*Register : Control_reg0 @ 0XFF000000

+ * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1 1 - Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a - high level during 12 bit periods. It can be set regardless of the value of STTBRK. - PSU_UART0_CONTROL_REG0_STPBRK 0x0 + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2 1 - Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the - transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high. - PSU_UART0_CONTROL_REG0_STTBRK 0x0 + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3 1 - Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has co - pleted. - PSU_UART0_CONTROL_REG0_RSTTO 0x0 + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4 1 - Transmit disable: 0: enable transmitter 1: disable transmitter - PSU_UART0_CONTROL_REG0_TXDIS 0x0 + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5 1 - Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0. - PSU_UART0_CONTROL_REG0_TXEN 0x1 + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6 1 - Receive disable: 0: enable 1: disable, regardless of the value of RXEN - PSU_UART0_CONTROL_REG0_RXDIS 0x0 + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7 1 - Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero. - PSU_UART0_CONTROL_REG0_RXEN 0x1 + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8 1 - Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded Thi - bit is self clearing once the reset has completed. - PSU_UART0_CONTROL_REG0_TXRES 0x1 + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9 1 - Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit - is self clearing once the reset has completed. - PSU_UART0_CONTROL_REG0_RXRES 0x1 + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10 1 - UART Control Register - (OFFSET, MASK, VALUE) (0XFF000000, 0x000001FFU ,0x00000017U) - RegMask = (UART0_CONTROL_REG0_STPBRK_MASK | UART0_CONTROL_REG0_STTBRK_MASK | UART0_CONTROL_REG0_RSTTO_MASK | UART0_CONTROL_REG0_TXDIS_MASK | UART0_CONTROL_REG0_TXEN_MASK | UART0_CONTROL_REG0_RXDIS_MASK | UART0_CONTROL_REG0_RXEN_MASK | UART0_CONTROL_REG0_TXRES_MASK | UART0_CONTROL_REG0_RXRES_MASK | 0 ); + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11 1 - RegVal = ((0x00000000U << UART0_CONTROL_REG0_STPBRK_SHIFT - | 0x00000000U << UART0_CONTROL_REG0_STTBRK_SHIFT - | 0x00000000U << UART0_CONTROL_REG0_RSTTO_SHIFT - | 0x00000000U << UART0_CONTROL_REG0_TXDIS_SHIFT - | 0x00000001U << UART0_CONTROL_REG0_TXEN_SHIFT - | 0x00000000U << UART0_CONTROL_REG0_RXDIS_SHIFT - | 0x00000001U << UART0_CONTROL_REG0_RXEN_SHIFT - | 0x00000001U << UART0_CONTROL_REG0_TXRES_SHIFT - | 0x00000001U << UART0_CONTROL_REG0_RXRES_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (UART0_CONTROL_REG0_OFFSET ,0x000001FFU ,0x00000017U); - /*############################################################################################################################ */ + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12 1 - /*Register : mode_reg0 @ 0XFF000004

+ * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13 1 - Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback - PSU_UART0_MODE_REG0_CHMODE 0x0 + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14 1 - Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5 - stop bits 10: 2 stop bits 11: reserved - PSU_UART0_MODE_REG0_NBSTOP 0x0 + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15 1 - Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity - 01: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity - PSU_UART0_MODE_REG0_PAR 0x4 + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16 1 - Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits - PSU_UART0_MODE_REG0_CHRL 0x0 + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17 1 - Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock - source is uart_ref_clk 1: clock source is uart_ref_clk/8 - PSU_UART0_MODE_REG0_CLKS 0x0 + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18 1 - UART Mode Register - (OFFSET, MASK, VALUE) (0XFF000004, 0x000003FFU ,0x00000020U) - RegMask = (UART0_MODE_REG0_CHMODE_MASK | UART0_MODE_REG0_NBSTOP_MASK | UART0_MODE_REG0_PAR_MASK | UART0_MODE_REG0_CHRL_MASK | UART0_MODE_REG0_CLKS_MASK | 0 ); + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19 1 - RegVal = ((0x00000000U << UART0_MODE_REG0_CHMODE_SHIFT - | 0x00000000U << UART0_MODE_REG0_NBSTOP_SHIFT - | 0x00000004U << UART0_MODE_REG0_PAR_SHIFT - | 0x00000000U << UART0_MODE_REG0_CHRL_SHIFT - | 0x00000000U << UART0_MODE_REG0_CLKS_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (UART0_MODE_REG0_OFFSET ,0x000003FFU ,0x00000020U); - /*############################################################################################################################ */ + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20 1 - /*Register : Baud_rate_divider_reg0 @ 0XFF010034

+ * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21 1 - Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate - PSU_UART1_BAUD_RATE_DIVIDER_REG0_BDIV 0x5 + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22 1 - Baud Rate Divider Register - (OFFSET, MASK, VALUE) (0XFF010034, 0x000000FFU ,0x00000005U) - RegMask = (UART1_BAUD_RATE_DIVIDER_REG0_BDIV_MASK | 0 ); - - RegVal = ((0x00000005U << UART1_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (UART1_BAUD_RATE_DIVIDER_REG0_OFFSET ,0x000000FFU ,0x00000005U); - /*############################################################################################################################ */ - - /*Register : Baud_rate_gen_reg0 @ 0XFF010018

+ * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23 1 - Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample - PSU_UART1_BAUD_RATE_GEN_REG0_CD 0x8f - - Baud Rate Generator Register. - (OFFSET, MASK, VALUE) (0XFF010018, 0x0000FFFFU ,0x0000008FU) - RegMask = (UART1_BAUD_RATE_GEN_REG0_CD_MASK | 0 ); - - RegVal = ((0x0000008FU << UART1_BAUD_RATE_GEN_REG0_CD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (UART1_BAUD_RATE_GEN_REG0_OFFSET ,0x0000FFFFU ,0x0000008FU); - /*############################################################################################################################ */ - - /*Register : Control_reg0 @ 0XFF010000

- - Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a - high level during 12 bit periods. It can be set regardless of the value of STTBRK. - PSU_UART1_CONTROL_REG0_STPBRK 0x0 - - Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the - transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high. - PSU_UART1_CONTROL_REG0_STTBRK 0x0 - - Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has co - pleted. - PSU_UART1_CONTROL_REG0_RSTTO 0x0 - - Transmit disable: 0: enable transmitter 1: disable transmitter - PSU_UART1_CONTROL_REG0_TXDIS 0x0 - - Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0. - PSU_UART1_CONTROL_REG0_TXEN 0x1 - - Receive disable: 0: enable 1: disable, regardless of the value of RXEN - PSU_UART1_CONTROL_REG0_RXDIS 0x0 - - Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero. - PSU_UART1_CONTROL_REG0_RXEN 0x1 + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24 1 - Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded Thi - bit is self clearing once the reset has completed. - PSU_UART1_CONTROL_REG0_TXRES 0x1 + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25 1 - Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit - is self clearing once the reset has completed. - PSU_UART1_CONTROL_REG0_RXRES 0x1 + * Drive0 control to MIO Bank 0 - control MIO[25:0] + * (OFFSET, MASK, VALUE) (0XFF180138, 0x03FFFFFFU ,0x03FFFFFFU) + */ + PSU_Mask_Write(IOU_SLCR_BANK0_CTRL0_OFFSET, + 0x03FFFFFFU, 0x03FFFFFFU); +/*##################################################################### */ - UART Control Register - (OFFSET, MASK, VALUE) (0XFF010000, 0x000001FFU ,0x00000017U) - RegMask = (UART1_CONTROL_REG0_STPBRK_MASK | UART1_CONTROL_REG0_STTBRK_MASK | UART1_CONTROL_REG0_RSTTO_MASK | UART1_CONTROL_REG0_TXDIS_MASK | UART1_CONTROL_REG0_TXEN_MASK | UART1_CONTROL_REG0_RXDIS_MASK | UART1_CONTROL_REG0_RXEN_MASK | UART1_CONTROL_REG0_TXRES_MASK | UART1_CONTROL_REG0_RXRES_MASK | 0 ); + /* + * Register : bank0_ctrl1 @ 0XFF18013C - RegVal = ((0x00000000U << UART1_CONTROL_REG0_STPBRK_SHIFT - | 0x00000000U << UART1_CONTROL_REG0_STTBRK_SHIFT - | 0x00000000U << UART1_CONTROL_REG0_RSTTO_SHIFT - | 0x00000000U << UART1_CONTROL_REG0_TXDIS_SHIFT - | 0x00000001U << UART1_CONTROL_REG0_TXEN_SHIFT - | 0x00000000U << UART1_CONTROL_REG0_RXDIS_SHIFT - | 0x00000001U << UART1_CONTROL_REG0_RXEN_SHIFT - | 0x00000001U << UART1_CONTROL_REG0_TXRES_SHIFT - | 0x00000001U << UART1_CONTROL_REG0_RXRES_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (UART1_CONTROL_REG0_OFFSET ,0x000001FFU ,0x00000017U); - /*############################################################################################################################ */ + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0 1 - /*Register : mode_reg0 @ 0XFF010004

+ * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1 1 - Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback - PSU_UART1_MODE_REG0_CHMODE 0x0 + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2 1 - Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5 - stop bits 10: 2 stop bits 11: reserved - PSU_UART1_MODE_REG0_NBSTOP 0x0 - - Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity - 01: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity - PSU_UART1_MODE_REG0_PAR 0x4 - - Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits - PSU_UART1_MODE_REG0_CHRL 0x0 - - Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock - source is uart_ref_clk 1: clock source is uart_ref_clk/8 - PSU_UART1_MODE_REG0_CLKS 0x0 + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3 1 - UART Mode Register - (OFFSET, MASK, VALUE) (0XFF010004, 0x000003FFU ,0x00000020U) - RegMask = (UART1_MODE_REG0_CHMODE_MASK | UART1_MODE_REG0_NBSTOP_MASK | UART1_MODE_REG0_PAR_MASK | UART1_MODE_REG0_CHRL_MASK | UART1_MODE_REG0_CLKS_MASK | 0 ); + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4 1 - RegVal = ((0x00000000U << UART1_MODE_REG0_CHMODE_SHIFT - | 0x00000000U << UART1_MODE_REG0_NBSTOP_SHIFT - | 0x00000004U << UART1_MODE_REG0_PAR_SHIFT - | 0x00000000U << UART1_MODE_REG0_CHRL_SHIFT - | 0x00000000U << UART1_MODE_REG0_CLKS_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (UART1_MODE_REG0_OFFSET ,0x000003FFU ,0x00000020U); - /*############################################################################################################################ */ - - // : GPIO - // : ADMA TZ - /*Register : slcr_adma @ 0XFF4B0024

+ * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5 1 - TrustZone Classification for ADMA - PSU_LPD_SLCR_SECURE_SLCR_ADMA_TZ 0XFF - - RPU TrustZone settings - (OFFSET, MASK, VALUE) (0XFF4B0024, 0x000000FFU ,0x000000FFU) - RegMask = (LPD_SLCR_SECURE_SLCR_ADMA_TZ_MASK | 0 ); - - RegVal = ((0x000000FFU << LPD_SLCR_SECURE_SLCR_ADMA_TZ_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (LPD_SLCR_SECURE_SLCR_ADMA_OFFSET ,0x000000FFU ,0x000000FFU); - /*############################################################################################################################ */ - - // : CSU TAMPERING - // : CSU TAMPER STATUS - /*Register : tamper_status @ 0XFFCA5000

- - CSU regsiter - PSU_CSU_TAMPER_STATUS_TAMPER_0 0 - - External MIO - PSU_CSU_TAMPER_STATUS_TAMPER_1 0 - - JTAG toggle detect - PSU_CSU_TAMPER_STATUS_TAMPER_2 0 - - PL SEU error - PSU_CSU_TAMPER_STATUS_TAMPER_3 0 - - AMS over temperature alarm for LPD - PSU_CSU_TAMPER_STATUS_TAMPER_4 0 - - AMS over temperature alarm for APU - PSU_CSU_TAMPER_STATUS_TAMPER_5 0 - - AMS voltage alarm for VCCPINT_FPD - PSU_CSU_TAMPER_STATUS_TAMPER_6 0 - - AMS voltage alarm for VCCPINT_LPD - PSU_CSU_TAMPER_STATUS_TAMPER_7 0 - - AMS voltage alarm for VCCPAUX - PSU_CSU_TAMPER_STATUS_TAMPER_8 0 - - AMS voltage alarm for DDRPHY - PSU_CSU_TAMPER_STATUS_TAMPER_9 0 - - AMS voltage alarm for PSIO bank 0/1/2 - PSU_CSU_TAMPER_STATUS_TAMPER_10 0 - - AMS voltage alarm for PSIO bank 3 (dedicated pins) - PSU_CSU_TAMPER_STATUS_TAMPER_11 0 - - AMS voltaage alarm for GT - PSU_CSU_TAMPER_STATUS_TAMPER_12 0 - - Tamper Response Status - (OFFSET, MASK, VALUE) (0XFFCA5000, 0x00001FFFU ,0x00000000U) - RegMask = (CSU_TAMPER_STATUS_TAMPER_0_MASK | CSU_TAMPER_STATUS_TAMPER_1_MASK | CSU_TAMPER_STATUS_TAMPER_2_MASK | CSU_TAMPER_STATUS_TAMPER_3_MASK | CSU_TAMPER_STATUS_TAMPER_4_MASK | CSU_TAMPER_STATUS_TAMPER_5_MASK | CSU_TAMPER_STATUS_TAMPER_6_MASK | CSU_TAMPER_STATUS_TAMPER_7_MASK | CSU_TAMPER_STATUS_TAMPER_8_MASK | CSU_TAMPER_STATUS_TAMPER_9_MASK | CSU_TAMPER_STATUS_TAMPER_10_MASK | CSU_TAMPER_STATUS_TAMPER_11_MASK | CSU_TAMPER_STATUS_TAMPER_12_MASK | 0 ); + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6 1 - RegVal = ((0x00000000U << CSU_TAMPER_STATUS_TAMPER_0_SHIFT - | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_1_SHIFT - | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_2_SHIFT - | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_3_SHIFT - | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_4_SHIFT - | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_5_SHIFT - | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_6_SHIFT - | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_7_SHIFT - | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_8_SHIFT - | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_9_SHIFT - | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_10_SHIFT - | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_11_SHIFT - | 0x00000000U << CSU_TAMPER_STATUS_TAMPER_12_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CSU_TAMPER_STATUS_OFFSET ,0x00001FFFU ,0x00000000U); - /*############################################################################################################################ */ + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7 1 - // : CSU TAMPER RESPONSE - // : AFIFM INTERFACE WIDTH - // : CPU QOS DEFAULT - /*Register : ACE_CTRL @ 0XFD5C0060

- - Set ACE outgoing AWQOS value - PSU_APU_ACE_CTRL_AWQOS 0X0 - - Set ACE outgoing ARQOS value - PSU_APU_ACE_CTRL_ARQOS 0X0 + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8 1 - ACE Control Register - (OFFSET, MASK, VALUE) (0XFD5C0060, 0x000F000FU ,0x00000000U) - RegMask = (APU_ACE_CTRL_AWQOS_MASK | APU_ACE_CTRL_ARQOS_MASK | 0 ); + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9 1 - RegVal = ((0x00000000U << APU_ACE_CTRL_AWQOS_SHIFT - | 0x00000000U << APU_ACE_CTRL_ARQOS_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (APU_ACE_CTRL_OFFSET ,0x000F000FU ,0x00000000U); - /*############################################################################################################################ */ + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10 1 - // : ENABLES RTC SWITCH TO BATTERY WHEN VCC_PSAUX IS NOT AVAILABLE - /*Register : CONTROL @ 0XFFA60040

+ * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11 1 - Enables the RTC. By writing a 0 to this bit, RTC will be powered off and the only module that potentially draws current from - he battery will be BBRAM. The value read through this bit does not necessarily reflect whether RTC is enabled or not. It is e - pected that RTC is enabled every time it is being configured. If RTC is not used in the design, FSBL will disable it by writi - g a 0 to this bit. - PSU_RTC_CONTROL_BATTERY_DISABLE 0X1 + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12 1 - This register controls various functionalities within the RTC - (OFFSET, MASK, VALUE) (0XFFA60040, 0x80000000U ,0x80000000U) - RegMask = (RTC_CONTROL_BATTERY_DISABLE_MASK | 0 ); + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13 1 - RegVal = ((0x00000001U << RTC_CONTROL_BATTERY_DISABLE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (RTC_CONTROL_OFFSET ,0x80000000U ,0x80000000U); - /*############################################################################################################################ */ + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14 1 - // : TIMESTAMP COUNTER - /*Register : base_frequency_ID_register @ 0XFF260020

+ * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15 1 - Frequency in number of ticks per second. Valid range from 10 MHz to 100 MHz. - PSU_IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ 0x5f5e100 + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16 1 - Program this register to match the clock frequency of the timestamp generator, in ticks per second. For example, for a 50 MHz - clock, program 0x02FAF080. This register is not accessible to the read-only programming interface. - (OFFSET, MASK, VALUE) (0XFF260020, 0xFFFFFFFFU ,0x05F5E100U) - RegMask = (IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_MASK | 0 ); + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17 1 - RegVal = ((0x05F5E100U << IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_OFFSET ,0xFFFFFFFFU ,0x05F5E100U); - /*############################################################################################################################ */ + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18 1 - /*Register : counter_control_register @ 0XFF260000

- - Enable 0: The counter is disabled and not incrementing. 1: The counter is enabled and is incrementing. - PSU_IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN 0x1 - - Controls the counter increments. This register is not accessible to the read-only programming interface. - (OFFSET, MASK, VALUE) (0XFF260000, 0x00000001U ,0x00000001U) - RegMask = (IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_MASK | 0 ); - - RegVal = ((0x00000001U << IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (IOU_SCNTRS_COUNTER_CONTROL_REGISTER_OFFSET ,0x00000001U ,0x00000001U); - /*############################################################################################################################ */ - - // : TTC SRC SELECT - - return 1; + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25 1 + + * Drive1 control to MIO Bank 0 - control MIO[25:0] + * (OFFSET, MASK, VALUE) (0XFF18013C, 0x03FFFFFFU ,0x03FFFFFFU) + */ + PSU_Mask_Write(IOU_SLCR_BANK0_CTRL1_OFFSET, + 0x03FFFFFFU, 0x03FFFFFFU); +/*##################################################################### */ + + /* + * Register : bank0_ctrl3 @ 0XFF180140 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25 0 + + * Selects either Schmitt or CMOS input for MIO Bank 0 - control MIO[25:0] + * (OFFSET, MASK, VALUE) (0XFF180140, 0x03FFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_BANK0_CTRL3_OFFSET, + 0x03FFFFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : bank0_ctrl4 @ 0XFF180144 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25 1 + + * When mio_bank0_pull_enable is set, this selects pull up or pull down for + * MIO Bank 0 - control MIO[25:0] + * (OFFSET, MASK, VALUE) (0XFF180144, 0x03FFFFFFU ,0x03FFFFFFU) + */ + PSU_Mask_Write(IOU_SLCR_BANK0_CTRL4_OFFSET, + 0x03FFFFFFU, 0x03FFFFFFU); +/*##################################################################### */ + + /* + * Register : bank0_ctrl5 @ 0XFF180148 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24 1 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25 1 + + * When set, this enables mio_bank0_pullupdown to selects pull up or pull d + * own for MIO Bank 0 - control MIO[25:0] + * (OFFSET, MASK, VALUE) (0XFF180148, 0x03FFFFFFU ,0x03FFFFFFU) + */ + PSU_Mask_Write(IOU_SLCR_BANK0_CTRL5_OFFSET, + 0x03FFFFFFU, 0x03FFFFFFU); +/*##################################################################### */ + + /* + * Register : bank0_ctrl6 @ 0XFF18014C + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24 0 + + * Each bit applies to a single IO. Bit 0 for MIO[0]. + * PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25 0 + + * Slew rate control to MIO Bank 0 - control MIO[25:0] + * (OFFSET, MASK, VALUE) (0XFF18014C, 0x03FFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_BANK0_CTRL6_OFFSET, + 0x03FFFFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : bank1_ctrl0 @ 0XFF180154 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25 1 + + * Drive0 control to MIO Bank 1 - control MIO[51:26] + * (OFFSET, MASK, VALUE) (0XFF180154, 0x03FFFFFFU ,0x03FFFFFFU) + */ + PSU_Mask_Write(IOU_SLCR_BANK1_CTRL0_OFFSET, + 0x03FFFFFFU, 0x03FFFFFFU); +/*##################################################################### */ + + /* + * Register : bank1_ctrl1 @ 0XFF180158 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25 1 + + * Drive1 control to MIO Bank 1 - control MIO[51:26] + * (OFFSET, MASK, VALUE) (0XFF180158, 0x03FFFFFFU ,0x03FFFFFFU) + */ + PSU_Mask_Write(IOU_SLCR_BANK1_CTRL1_OFFSET, + 0x03FFFFFFU, 0x03FFFFFFU); +/*##################################################################### */ + + /* + * Register : bank1_ctrl3 @ 0XFF18015C + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25 0 + + * Selects either Schmitt or CMOS input for MIO Bank 1 - control MIO[51:26] + * (OFFSET, MASK, VALUE) (0XFF18015C, 0x03FFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_BANK1_CTRL3_OFFSET, + 0x03FFFFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : bank1_ctrl4 @ 0XFF180160 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25 1 + + * When mio_bank1_pull_enable is set, this selects pull up or pull down for + * MIO Bank 1 - control MIO[51:26] + * (OFFSET, MASK, VALUE) (0XFF180160, 0x03FFFFFFU ,0x03FFFFFFU) + */ + PSU_Mask_Write(IOU_SLCR_BANK1_CTRL4_OFFSET, + 0x03FFFFFFU, 0x03FFFFFFU); +/*##################################################################### */ + + /* + * Register : bank1_ctrl5 @ 0XFF180164 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24 1 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25 1 + + * When set, this enables mio_bank1_pullupdown to selects pull up or pull d + * own for MIO Bank 1 - control MIO[51:26] + * (OFFSET, MASK, VALUE) (0XFF180164, 0x03FFFFFFU ,0x03FFFFFFU) + */ + PSU_Mask_Write(IOU_SLCR_BANK1_CTRL5_OFFSET, + 0x03FFFFFFU, 0x03FFFFFFU); +/*##################################################################### */ + + /* + * Register : bank1_ctrl6 @ 0XFF180168 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24 0 + + * Each bit applies to a single IO. Bit 0 for MIO[26]. + * PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25 0 + + * Slew rate control to MIO Bank 1 - control MIO[51:26] + * (OFFSET, MASK, VALUE) (0XFF180168, 0x03FFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_BANK1_CTRL6_OFFSET, + 0x03FFFFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : bank2_ctrl0 @ 0XFF180170 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25 1 + + * Drive0 control to MIO Bank 2 - control MIO[77:52] + * (OFFSET, MASK, VALUE) (0XFF180170, 0x03FFFFFFU ,0x03FFFFFFU) + */ + PSU_Mask_Write(IOU_SLCR_BANK2_CTRL0_OFFSET, + 0x03FFFFFFU, 0x03FFFFFFU); +/*##################################################################### */ + + /* + * Register : bank2_ctrl1 @ 0XFF180174 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25 1 + + * Drive1 control to MIO Bank 2 - control MIO[77:52] + * (OFFSET, MASK, VALUE) (0XFF180174, 0x03FFFFFFU ,0x03FFFFFFU) + */ + PSU_Mask_Write(IOU_SLCR_BANK2_CTRL1_OFFSET, + 0x03FFFFFFU, 0x03FFFFFFU); +/*##################################################################### */ + + /* + * Register : bank2_ctrl3 @ 0XFF180178 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25 0 + + * Selects either Schmitt or CMOS input for MIO Bank 2 - control MIO[77:52] + * (OFFSET, MASK, VALUE) (0XFF180178, 0x03FFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_BANK2_CTRL3_OFFSET, + 0x03FFFFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : bank2_ctrl4 @ 0XFF18017C + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25 1 + + * When mio_bank2_pull_enable is set, this selects pull up or pull down for + * MIO Bank 2 - control MIO[77:52] + * (OFFSET, MASK, VALUE) (0XFF18017C, 0x03FFFFFFU ,0x03FFFFFFU) + */ + PSU_Mask_Write(IOU_SLCR_BANK2_CTRL4_OFFSET, + 0x03FFFFFFU, 0x03FFFFFFU); +/*##################################################################### */ + + /* + * Register : bank2_ctrl5 @ 0XFF180180 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24 1 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25 1 + + * When set, this enables mio_bank2_pullupdown to selects pull up or pull d + * own for MIO Bank 2 - control MIO[77:52] + * (OFFSET, MASK, VALUE) (0XFF180180, 0x03FFFFFFU ,0x03FFFFFFU) + */ + PSU_Mask_Write(IOU_SLCR_BANK2_CTRL5_OFFSET, + 0x03FFFFFFU, 0x03FFFFFFU); +/*##################################################################### */ + + /* + * Register : bank2_ctrl6 @ 0XFF180184 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24 0 + + * Each bit applies to a single IO. Bit 0 for MIO[52]. + * PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25 0 + + * Slew rate control to MIO Bank 2 - control MIO[77:52] + * (OFFSET, MASK, VALUE) (0XFF180184, 0x03FFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_BANK2_CTRL6_OFFSET, + 0x03FFFFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * LOOPBACK + */ + /* + * Register : MIO_LOOPBACK @ 0XFF180200 + + * I2C Loopback Control. 0 = Connect I2C inputs according to MIO mapping. 1 + * = Loop I2C 0 outputs to I2C 1 inputs, and I2C 1 outputs to I2C 0 inputs + * . + * PSU_IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1 0 + + * CAN Loopback Control. 0 = Connect CAN inputs according to MIO mapping. 1 + * = Loop CAN 0 Tx to CAN 1 Rx, and CAN 1 Tx to CAN 0 Rx. + * PSU_IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1 0 + + * UART Loopback Control. 0 = Connect UART inputs according to MIO mapping. + * 1 = Loop UART 0 outputs to UART 1 inputs, and UART 1 outputs to UART 0 + * inputs. RXD/TXD cross-connected. RTS/CTS cross-connected. DSR, DTR, DCD + * and RI not used. + * PSU_IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1 0 + + * SPI Loopback Control. 0 = Connect SPI inputs according to MIO mapping. 1 + * = Loop SPI 0 outputs to SPI 1 inputs, and SPI 1 outputs to SPI 0 inputs + * . The other SPI core will appear on the LS Slave Select. + * PSU_IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1 0 + + * Loopback function within MIO + * (OFFSET, MASK, VALUE) (0XFF180200, 0x0000000FU ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_MIO_LOOPBACK_OFFSET, + 0x0000000FU, 0x00000000U); +/*##################################################################### */ + + + return 1; } -unsigned long psu_post_config_data() { - // : POST_CONFIG +unsigned long psu_peripherals_init_data(void) +{ + /* + * COHERENCY + */ + /* + * FPD RESET + */ + /* + * Register : RST_FPD_TOP @ 0XFD1A0100 - return 1; + * PCIE config reset + * PSU_CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET 0 + + * PCIE control block level reset + * PSU_CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET 0 + + * PCIE bridge block level reset (AXI interface) + * PSU_CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET 0 + + * Display Port block level reset (includes DPDMA) + * PSU_CRF_APB_RST_FPD_TOP_DP_RESET 0 + + * FPD WDT reset + * PSU_CRF_APB_RST_FPD_TOP_SWDT_RESET 0 + + * GDMA block level reset + * PSU_CRF_APB_RST_FPD_TOP_GDMA_RESET 0 + + * Pixel Processor (submodule of GPU) block level reset + * PSU_CRF_APB_RST_FPD_TOP_GPU_PP0_RESET 0 + + * Pixel Processor (submodule of GPU) block level reset + * PSU_CRF_APB_RST_FPD_TOP_GPU_PP1_RESET 0 + + * GPU block level reset + * PSU_CRF_APB_RST_FPD_TOP_GPU_RESET 0 + + * GT block level reset + * PSU_CRF_APB_RST_FPD_TOP_GT_RESET 0 + + * Sata block level reset + * PSU_CRF_APB_RST_FPD_TOP_SATA_RESET 0 + + * FPD Block level software controlled reset + * (OFFSET, MASK, VALUE) (0XFD1A0100, 0x000F807EU ,0x00000000U) + */ + PSU_Mask_Write(CRF_APB_RST_FPD_TOP_OFFSET, 0x000F807EU, 0x00000000U); +/*##################################################################### */ + + /* + * RESET BLOCKS + */ + /* + * TIMESTAMP + */ + /* + * Register : RST_LPD_IOU2 @ 0XFF5E0238 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET 0 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_IOU_CC_RESET 0 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_ADMA_RESET 0 + + * Software control register for the IOU block. Each bit will cause a singl + * erperipheral or part of the peripheral to be reset. + * (OFFSET, MASK, VALUE) (0XFF5E0238, 0x001A0000U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_IOU2_OFFSET, + 0x001A0000U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : RST_LPD_TOP @ 0XFF5E023C + + * Reset entire full power domain. + * PSU_CRL_APB_RST_LPD_TOP_FPD_RESET 0 + + * LPD SWDT + * PSU_CRL_APB_RST_LPD_TOP_LPD_SWDT_RESET 0 + + * Sysmonitor reset + * PSU_CRL_APB_RST_LPD_TOP_SYSMON_RESET 0 + + * Real Time Clock reset + * PSU_CRL_APB_RST_LPD_TOP_RTC_RESET 0 + + * APM reset + * PSU_CRL_APB_RST_LPD_TOP_APM_RESET 0 + + * IPI reset + * PSU_CRL_APB_RST_LPD_TOP_IPI_RESET 0 + + * reset entire RPU power island + * PSU_CRL_APB_RST_LPD_TOP_RPU_PGE_RESET 0 + + * reset ocm + * PSU_CRL_APB_RST_LPD_TOP_OCM_RESET 0 + + * Software control register for the LPD block. + * (OFFSET, MASK, VALUE) (0XFF5E023C, 0x0093C018U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_TOP_OFFSET, 0x0093C018U, 0x00000000U); +/*##################################################################### */ + + /* + * ENET + */ + /* + * Register : RST_LPD_IOU0 @ 0XFF5E0230 + + * GEM 3 reset + * PSU_CRL_APB_RST_LPD_IOU0_GEM3_RESET 0 + + * Software controlled reset for the GEMs + * (OFFSET, MASK, VALUE) (0XFF5E0230, 0x00000008U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_IOU0_OFFSET, + 0x00000008U, 0x00000000U); +/*##################################################################### */ + + /* + * QSPI + */ + /* + * Register : RST_LPD_IOU2 @ 0XFF5E0238 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_QSPI_RESET 0 + + * Software control register for the IOU block. Each bit will cause a singl + * erperipheral or part of the peripheral to be reset. + * (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000001U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_IOU2_OFFSET, + 0x00000001U, 0x00000000U); +/*##################################################################### */ + + /* + * QSPI TAP DELAY + */ + /* + * Register : IOU_TAPDLY_BYPASS @ 0XFF180390 + + * 0: Do not by pass the tap delays on the Rx clock signal of LQSPI 1: Bypa + * ss the Tap delay on the Rx clock signal of LQSPI + * PSU_IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX 1 + + * IOU tap delay bypass for the LQSPI and NAND controllers + * (OFFSET, MASK, VALUE) (0XFF180390, 0x00000004U ,0x00000004U) + */ + PSU_Mask_Write(IOU_SLCR_IOU_TAPDLY_BYPASS_OFFSET, + 0x00000004U, 0x00000004U); +/*##################################################################### */ + + /* + * NAND + */ + /* + * USB + */ + /* + * Register : RST_LPD_TOP @ 0XFF5E023C + + * USB 0 reset for control registers + * PSU_CRL_APB_RST_LPD_TOP_USB0_APB_RESET 0 + + * USB 0 sleep circuit reset + * PSU_CRL_APB_RST_LPD_TOP_USB0_HIBERRESET 0 + + * USB 0 reset + * PSU_CRL_APB_RST_LPD_TOP_USB0_CORERESET 0 + + * Software control register for the LPD block. + * (OFFSET, MASK, VALUE) (0XFF5E023C, 0x00000540U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_TOP_OFFSET, 0x00000540U, 0x00000000U); +/*##################################################################### */ + + /* + * USB0 PIPE POWER PRESENT + */ + /* + * Register : fpd_power_prsnt @ 0XFF9D0080 + + * This bit is used to choose between PIPE power present and 1'b1 + * PSU_USB3_0_FPD_POWER_PRSNT_OPTION 0X1 + + * fpd_power_prsnt + * (OFFSET, MASK, VALUE) (0XFF9D0080, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(USB3_0_FPD_POWER_PRSNT_OFFSET, + 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : fpd_pipe_clk @ 0XFF9D007C + + * This bit is used to choose between PIPE clock coming from SerDes and the + * suspend clk + * PSU_USB3_0_FPD_PIPE_CLK_OPTION 0x0 + + * fpd_pipe_clk + * (OFFSET, MASK, VALUE) (0XFF9D007C, 0x00000001U ,0x00000000U) + */ + PSU_Mask_Write(USB3_0_FPD_PIPE_CLK_OFFSET, 0x00000001U, 0x00000000U); +/*##################################################################### */ + + /* + * SD + */ + /* + * Register : RST_LPD_IOU2 @ 0XFF5E0238 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_SDIO1_RESET 0 + + * Software control register for the IOU block. Each bit will cause a singl + * erperipheral or part of the peripheral to be reset. + * (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000040U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_IOU2_OFFSET, + 0x00000040U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : CTRL_REG_SD @ 0XFF180310 + + * SD or eMMC selection on SDIO1 0: SD enabled 1: eMMC enabled + * PSU_IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL 0 + + * SD eMMC selection + * (OFFSET, MASK, VALUE) (0XFF180310, 0x00008000U ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_CTRL_REG_SD_OFFSET, + 0x00008000U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : SD_CONFIG_REG2 @ 0XFF180320 + + * Should be set based on the final product usage 00 - Removable SCard Slot + * 01 - Embedded Slot for One Device 10 - Shared Bus Slot 11 - Reserved + * PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE 0 + + * 1.8V Support 1: 1.8V supported 0: 1.8V not supported support + * PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V 1 + + * 3.0V Support 1: 3.0V supported 0: 3.0V not supported support + * PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V 0 + + * 3.3V Support 1: 3.3V supported 0: 3.3V not supported support + * PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V 1 + + * SD Config Register 2 + * (OFFSET, MASK, VALUE) (0XFF180320, 0x33800000U ,0x02800000U) + */ + PSU_Mask_Write(IOU_SLCR_SD_CONFIG_REG2_OFFSET, + 0x33800000U, 0x02800000U); +/*##################################################################### */ + + /* + * SD1 BASE CLOCK + */ + /* + * Register : SD_CONFIG_REG1 @ 0XFF18031C + + * Base Clock Frequency for SD Clock. This is the frequency of the xin_clk. + * PSU_IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK 0xc8 + + * Configures the Number of Taps (Phases) of the rxclk_in that is supported + * . + * PSU_IOU_SLCR_SD_CONFIG_REG1_SD1_TUNIGCOUNT 0x28 + + * SD Config Register 1 + * (OFFSET, MASK, VALUE) (0XFF18031C, 0x7FFE0000U ,0x64500000U) + */ + PSU_Mask_Write(IOU_SLCR_SD_CONFIG_REG1_OFFSET, + 0x7FFE0000U, 0x64500000U); +/*##################################################################### */ + + /* + * Register : SD_DLL_CTRL @ 0XFF180358 + + * Reserved. + * PSU_IOU_SLCR_SD_DLL_CTRL_RESERVED 1 + + * SDIO status register + * (OFFSET, MASK, VALUE) (0XFF180358, 0x00000008U ,0x00000008U) + */ + PSU_Mask_Write(IOU_SLCR_SD_DLL_CTRL_OFFSET, + 0x00000008U, 0x00000008U); +/*##################################################################### */ + + /* + * SD1 RETUNER + */ + /* + * Register : SD_CONFIG_REG3 @ 0XFF180324 + + * This is the Timer Count for Re-Tuning Timer for Re-Tuning Mode 1 to 3. S + * etting to 4'b0 disables Re-Tuning Timer. 0h - Get information via other + * source 1h = 1 seconds 2h = 2 seconds 3h = 4 seconds 4h = 8 seconds -- n + * = 2(n-1) seconds -- Bh = 1024 seconds Fh - Ch = Reserved + * PSU_IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR 0X0 + + * SD Config Register 3 + * (OFFSET, MASK, VALUE) (0XFF180324, 0x03C00000U ,0x00000000U) + */ + PSU_Mask_Write(IOU_SLCR_SD_CONFIG_REG3_OFFSET, + 0x03C00000U, 0x00000000U); +/*##################################################################### */ + + /* + * CAN + */ + /* + * Register : RST_LPD_IOU2 @ 0XFF5E0238 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_CAN1_RESET 0 + + * Software control register for the IOU block. Each bit will cause a singl + * erperipheral or part of the peripheral to be reset. + * (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000100U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_IOU2_OFFSET, + 0x00000100U, 0x00000000U); +/*##################################################################### */ + + /* + * I2C + */ + /* + * Register : RST_LPD_IOU2 @ 0XFF5E0238 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_I2C0_RESET 0 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_I2C1_RESET 0 + + * Software control register for the IOU block. Each bit will cause a singl + * erperipheral or part of the peripheral to be reset. + * (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000600U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_IOU2_OFFSET, + 0x00000600U, 0x00000000U); +/*##################################################################### */ + + /* + * SWDT + */ + /* + * Register : RST_LPD_IOU2 @ 0XFF5E0238 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_SWDT_RESET 0 + + * Software control register for the IOU block. Each bit will cause a singl + * erperipheral or part of the peripheral to be reset. + * (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00008000U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_IOU2_OFFSET, + 0x00008000U, 0x00000000U); +/*##################################################################### */ + + /* + * SPI + */ + /* + * TTC + */ + /* + * Register : RST_LPD_IOU2 @ 0XFF5E0238 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_TTC0_RESET 0 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_TTC1_RESET 0 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_TTC2_RESET 0 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_TTC3_RESET 0 + + * Software control register for the IOU block. Each bit will cause a singl + * erperipheral or part of the peripheral to be reset. + * (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00007800U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_IOU2_OFFSET, + 0x00007800U, 0x00000000U); +/*##################################################################### */ + + /* + * UART + */ + /* + * Register : RST_LPD_IOU2 @ 0XFF5E0238 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_UART0_RESET 0 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_UART1_RESET 0 + + * Software control register for the IOU block. Each bit will cause a singl + * erperipheral or part of the peripheral to be reset. + * (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00000006U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_IOU2_OFFSET, + 0x00000006U, 0x00000000U); +/*##################################################################### */ + + /* + * UART BAUD RATE + */ + /* + * Register : Baud_rate_divider_reg0 @ 0XFF000034 + + * Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate + * PSU_UART0_BAUD_RATE_DIVIDER_REG0_BDIV 0x5 + + * Baud Rate Divider Register + * (OFFSET, MASK, VALUE) (0XFF000034, 0x000000FFU ,0x00000005U) + */ + PSU_Mask_Write(UART0_BAUD_RATE_DIVIDER_REG0_OFFSET, + 0x000000FFU, 0x00000005U); +/*##################################################################### */ + + /* + * Register : Baud_rate_gen_reg0 @ 0XFF000018 + + * Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor + * bypass (baud_sample = sel_clk) 2 - 65535: baud_sample + * PSU_UART0_BAUD_RATE_GEN_REG0_CD 0x8f + + * Baud Rate Generator Register. + * (OFFSET, MASK, VALUE) (0XFF000018, 0x0000FFFFU ,0x0000008FU) + */ + PSU_Mask_Write(UART0_BAUD_RATE_GEN_REG0_OFFSET, + 0x0000FFFFU, 0x0000008FU); +/*##################################################################### */ + + /* + * Register : Control_reg0 @ 0XFF000000 + + * Stop transmitter break: 0: no affect 1: stop transmission of the break a + * fter a minimum of one character length and transmit a high level during + * 12 bit periods. It can be set regardless of the value of STTBRK. + * PSU_UART0_CONTROL_REG0_STPBRK 0x0 + + * Start transmitter break: 0: no affect 1: start to transmit a break after + * the characters currently present in the FIFO and the transmit shift reg + * ister have been transmitted. It can only be set if STPBRK (Stop transmit + * ter break) is not high. + * PSU_UART0_CONTROL_REG0_STTBRK 0x0 + + * Restart receiver timeout counter: 1: receiver timeout counter is restart + * ed. This bit is self clearing once the restart has completed. + * PSU_UART0_CONTROL_REG0_RSTTO 0x0 + + * Transmit disable: 0: enable transmitter 1: disable transmitter + * PSU_UART0_CONTROL_REG0_TXDIS 0x0 + + * Transmit enable: 0: disable transmitter 1: enable transmitter, provided + * the TXDIS field is set to 0. + * PSU_UART0_CONTROL_REG0_TXEN 0x1 + + * Receive disable: 0: enable 1: disable, regardless of the value of RXEN + * PSU_UART0_CONTROL_REG0_RXDIS 0x0 + + * Receive enable: 0: disable 1: enable When set to one, the receiver logic + * is enabled, provided the RXDIS field is set to zero. + * PSU_UART0_CONTROL_REG0_RXEN 0x1 + + * Software reset for Tx data path: 0: no affect 1: transmitter logic is re + * set and all pending transmitter data is discarded This bit is self clear + * ing once the reset has completed. + * PSU_UART0_CONTROL_REG0_TXRES 0x1 + + * Software reset for Rx data path: 0: no affect 1: receiver logic is reset + * and all pending receiver data is discarded. This bit is self clearing o + * nce the reset has completed. + * PSU_UART0_CONTROL_REG0_RXRES 0x1 + + * UART Control Register + * (OFFSET, MASK, VALUE) (0XFF000000, 0x000001FFU ,0x00000017U) + */ + PSU_Mask_Write(UART0_CONTROL_REG0_OFFSET, 0x000001FFU, 0x00000017U); +/*##################################################################### */ + + /* + * Register : mode_reg0 @ 0XFF000004 + + * Channel mode: Defines the mode of operation of the UART. 00: normal 01: + * automatic echo 10: local loopback 11: remote loopback + * PSU_UART0_MODE_REG0_CHMODE 0x0 + + * Number of stop bits: Defines the number of stop bits to detect on receiv + * e and to generate on transmit. 00: 1 stop bit 01: 1.5 stop bits 10: 2 st + * op bits 11: reserved + * PSU_UART0_MODE_REG0_NBSTOP 0x0 + + * Parity type select: Defines the expected parity to check on receive and + * the parity to generate on transmit. 000: even parity 001: odd parity 010 + * : forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no pari + * ty + * PSU_UART0_MODE_REG0_PAR 0x4 + + * Character length select: Defines the number of bits in each character. 1 + * 1: 6 bits 10: 7 bits 0x: 8 bits + * PSU_UART0_MODE_REG0_CHRL 0x0 + + * Clock source select: This field defines whether a pre-scalar of 8 is app + * lied to the baud rate generator input clock. 0: clock source is uart_ref + * _clk 1: clock source is uart_ref_clk/8 + * PSU_UART0_MODE_REG0_CLKS 0x0 + + * UART Mode Register + * (OFFSET, MASK, VALUE) (0XFF000004, 0x000003FFU ,0x00000020U) + */ + PSU_Mask_Write(UART0_MODE_REG0_OFFSET, 0x000003FFU, 0x00000020U); +/*##################################################################### */ + + /* + * Register : Baud_rate_divider_reg0 @ 0XFF010034 + + * Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate + * PSU_UART1_BAUD_RATE_DIVIDER_REG0_BDIV 0x5 + + * Baud Rate Divider Register + * (OFFSET, MASK, VALUE) (0XFF010034, 0x000000FFU ,0x00000005U) + */ + PSU_Mask_Write(UART1_BAUD_RATE_DIVIDER_REG0_OFFSET, + 0x000000FFU, 0x00000005U); +/*##################################################################### */ + + /* + * Register : Baud_rate_gen_reg0 @ 0XFF010018 + + * Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor + * bypass (baud_sample = sel_clk) 2 - 65535: baud_sample + * PSU_UART1_BAUD_RATE_GEN_REG0_CD 0x8f + + * Baud Rate Generator Register. + * (OFFSET, MASK, VALUE) (0XFF010018, 0x0000FFFFU ,0x0000008FU) + */ + PSU_Mask_Write(UART1_BAUD_RATE_GEN_REG0_OFFSET, + 0x0000FFFFU, 0x0000008FU); +/*##################################################################### */ + + /* + * Register : Control_reg0 @ 0XFF010000 + + * Stop transmitter break: 0: no affect 1: stop transmission of the break a + * fter a minimum of one character length and transmit a high level during + * 12 bit periods. It can be set regardless of the value of STTBRK. + * PSU_UART1_CONTROL_REG0_STPBRK 0x0 + + * Start transmitter break: 0: no affect 1: start to transmit a break after + * the characters currently present in the FIFO and the transmit shift reg + * ister have been transmitted. It can only be set if STPBRK (Stop transmit + * ter break) is not high. + * PSU_UART1_CONTROL_REG0_STTBRK 0x0 + + * Restart receiver timeout counter: 1: receiver timeout counter is restart + * ed. This bit is self clearing once the restart has completed. + * PSU_UART1_CONTROL_REG0_RSTTO 0x0 + + * Transmit disable: 0: enable transmitter 1: disable transmitter + * PSU_UART1_CONTROL_REG0_TXDIS 0x0 + + * Transmit enable: 0: disable transmitter 1: enable transmitter, provided + * the TXDIS field is set to 0. + * PSU_UART1_CONTROL_REG0_TXEN 0x1 + + * Receive disable: 0: enable 1: disable, regardless of the value of RXEN + * PSU_UART1_CONTROL_REG0_RXDIS 0x0 + + * Receive enable: 0: disable 1: enable When set to one, the receiver logic + * is enabled, provided the RXDIS field is set to zero. + * PSU_UART1_CONTROL_REG0_RXEN 0x1 + + * Software reset for Tx data path: 0: no affect 1: transmitter logic is re + * set and all pending transmitter data is discarded This bit is self clear + * ing once the reset has completed. + * PSU_UART1_CONTROL_REG0_TXRES 0x1 + + * Software reset for Rx data path: 0: no affect 1: receiver logic is reset + * and all pending receiver data is discarded. This bit is self clearing o + * nce the reset has completed. + * PSU_UART1_CONTROL_REG0_RXRES 0x1 + + * UART Control Register + * (OFFSET, MASK, VALUE) (0XFF010000, 0x000001FFU ,0x00000017U) + */ + PSU_Mask_Write(UART1_CONTROL_REG0_OFFSET, 0x000001FFU, 0x00000017U); +/*##################################################################### */ + + /* + * Register : mode_reg0 @ 0XFF010004 + + * Channel mode: Defines the mode of operation of the UART. 00: normal 01: + * automatic echo 10: local loopback 11: remote loopback + * PSU_UART1_MODE_REG0_CHMODE 0x0 + + * Number of stop bits: Defines the number of stop bits to detect on receiv + * e and to generate on transmit. 00: 1 stop bit 01: 1.5 stop bits 10: 2 st + * op bits 11: reserved + * PSU_UART1_MODE_REG0_NBSTOP 0x0 + + * Parity type select: Defines the expected parity to check on receive and + * the parity to generate on transmit. 000: even parity 001: odd parity 010 + * : forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no pari + * ty + * PSU_UART1_MODE_REG0_PAR 0x4 + + * Character length select: Defines the number of bits in each character. 1 + * 1: 6 bits 10: 7 bits 0x: 8 bits + * PSU_UART1_MODE_REG0_CHRL 0x0 + + * Clock source select: This field defines whether a pre-scalar of 8 is app + * lied to the baud rate generator input clock. 0: clock source is uart_ref + * _clk 1: clock source is uart_ref_clk/8 + * PSU_UART1_MODE_REG0_CLKS 0x0 + + * UART Mode Register + * (OFFSET, MASK, VALUE) (0XFF010004, 0x000003FFU ,0x00000020U) + */ + PSU_Mask_Write(UART1_MODE_REG0_OFFSET, 0x000003FFU, 0x00000020U); +/*##################################################################### */ + + /* + * GPIO + */ + /* + * Register : RST_LPD_IOU2 @ 0XFF5E0238 + + * Block level reset + * PSU_CRL_APB_RST_LPD_IOU2_GPIO_RESET 0 + + * Software control register for the IOU block. Each bit will cause a singl + * erperipheral or part of the peripheral to be reset. + * (OFFSET, MASK, VALUE) (0XFF5E0238, 0x00040000U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_IOU2_OFFSET, + 0x00040000U, 0x00000000U); +/*##################################################################### */ + + /* + * ADMA TZ + */ + /* + * Register : slcr_adma @ 0XFF4B0024 + + * TrustZone Classification for ADMA + * PSU_LPD_SLCR_SECURE_SLCR_ADMA_TZ 0XFF + + * RPU TrustZone settings + * (OFFSET, MASK, VALUE) (0XFF4B0024, 0x000000FFU ,0x000000FFU) + */ + PSU_Mask_Write(LPD_SLCR_SECURE_SLCR_ADMA_OFFSET, + 0x000000FFU, 0x000000FFU); +/*##################################################################### */ + + /* + * CSU TAMPERING + */ + /* + * CSU TAMPER STATUS + */ + /* + * Register : tamper_status @ 0XFFCA5000 + + * CSU regsiter + * PSU_CSU_TAMPER_STATUS_TAMPER_0 0 + + * External MIO + * PSU_CSU_TAMPER_STATUS_TAMPER_1 0 + + * JTAG toggle detect + * PSU_CSU_TAMPER_STATUS_TAMPER_2 0 + + * PL SEU error + * PSU_CSU_TAMPER_STATUS_TAMPER_3 0 + + * AMS over temperature alarm for LPD + * PSU_CSU_TAMPER_STATUS_TAMPER_4 0 + + * AMS over temperature alarm for APU + * PSU_CSU_TAMPER_STATUS_TAMPER_5 0 + + * AMS voltage alarm for VCCPINT_FPD + * PSU_CSU_TAMPER_STATUS_TAMPER_6 0 + + * AMS voltage alarm for VCCPINT_LPD + * PSU_CSU_TAMPER_STATUS_TAMPER_7 0 + + * AMS voltage alarm for VCCPAUX + * PSU_CSU_TAMPER_STATUS_TAMPER_8 0 + + * AMS voltage alarm for DDRPHY + * PSU_CSU_TAMPER_STATUS_TAMPER_9 0 + + * AMS voltage alarm for PSIO bank 0/1/2 + * PSU_CSU_TAMPER_STATUS_TAMPER_10 0 + + * AMS voltage alarm for PSIO bank 3 (dedicated pins) + * PSU_CSU_TAMPER_STATUS_TAMPER_11 0 + + * AMS voltaage alarm for GT + * PSU_CSU_TAMPER_STATUS_TAMPER_12 0 + + * Tamper Response Status + * (OFFSET, MASK, VALUE) (0XFFCA5000, 0x00001FFFU ,0x00000000U) + */ + PSU_Mask_Write(CSU_TAMPER_STATUS_OFFSET, 0x00001FFFU, 0x00000000U); +/*##################################################################### */ + + /* + * CSU TAMPER RESPONSE + */ + /* + * CPU QOS DEFAULT + */ + /* + * Register : ACE_CTRL @ 0XFD5C0060 + + * Set ACE outgoing AWQOS value + * PSU_APU_ACE_CTRL_AWQOS 0X0 + + * Set ACE outgoing ARQOS value + * PSU_APU_ACE_CTRL_ARQOS 0X0 + + * ACE Control Register + * (OFFSET, MASK, VALUE) (0XFD5C0060, 0x000F000FU ,0x00000000U) + */ + PSU_Mask_Write(APU_ACE_CTRL_OFFSET, 0x000F000FU, 0x00000000U); +/*##################################################################### */ + + /* + * ENABLES RTC SWITCH TO BATTERY WHEN VCC_PSAUX IS NOT AVAILABLE + */ + /* + * Register : CONTROL @ 0XFFA60040 + + * Enables the RTC. By writing a 0 to this bit, RTC will be powered off and + * the only module that potentially draws current from the battery will be + * BBRAM. The value read through this bit does not necessarily reflect whe + * ther RTC is enabled or not. It is expected that RTC is enabled every tim + * e it is being configured. If RTC is not used in the design, FSBL will di + * sable it by writing a 0 to this bit. + * PSU_RTC_CONTROL_BATTERY_DISABLE 0X1 + + * This register controls various functionalities within the RTC + * (OFFSET, MASK, VALUE) (0XFFA60040, 0x80000000U ,0x80000000U) + */ + PSU_Mask_Write(RTC_CONTROL_OFFSET, 0x80000000U, 0x80000000U); +/*##################################################################### */ + + /* + * TIMESTAMP COUNTER + */ + /* + * Register : base_frequency_ID_register @ 0XFF260020 + + * Frequency in number of ticks per second. Valid range from 10 MHz to 100 + * MHz. + * PSU_IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ 0x5f5b9f0 + + * Program this register to match the clock frequency of the timestamp gene + * rator, in ticks per second. For example, for a 50 MHz clock, program 0x0 + * 2FAF080. This register is not accessible to the read-only programming in + * terface. + * (OFFSET, MASK, VALUE) (0XFF260020, 0xFFFFFFFFU ,0x05F5B9F0U) + */ + PSU_Mask_Write(IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_OFFSET, + 0xFFFFFFFFU, 0x05F5B9F0U); +/*##################################################################### */ + + /* + * Register : counter_control_register @ 0XFF260000 + + * Enable 0: The counter is disabled and not incrementing. 1: The counter i + * s enabled and is incrementing. + * PSU_IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN 0x1 + + * Controls the counter increments. This register is not accessible to the + * read-only programming interface. + * (OFFSET, MASK, VALUE) (0XFF260000, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(IOU_SCNTRS_COUNTER_CONTROL_REGISTER_OFFSET, + 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * TTC SRC SELECT + */ + /* + * PCIE GPIO RESET + */ + /* + * PCIE RESET + */ + /* + * DIR MODE BANK 0 + */ + /* + * DIR MODE BANK 1 + */ + /* + * Register : DIRM_1 @ 0XFF0A0244 + + * Operation is the same as DIRM_0[DIRECTION_0] + * PSU_GPIO_DIRM_1_DIRECTION_1 0x20 + + * Direction mode (GPIO Bank1, MIO) + * (OFFSET, MASK, VALUE) (0XFF0A0244, 0x03FFFFFFU ,0x00000020U) + */ + PSU_Mask_Write(GPIO_DIRM_1_OFFSET, 0x03FFFFFFU, 0x00000020U); +/*##################################################################### */ + + /* + * DIR MODE BANK 2 + */ + /* + * OUTPUT ENABLE BANK 0 + */ + /* + * OUTPUT ENABLE BANK 1 + */ + /* + * Register : OEN_1 @ 0XFF0A0248 + + * Operation is the same as OEN_0[OP_ENABLE_0] + * PSU_GPIO_OEN_1_OP_ENABLE_1 0x20 + + * Output enable (GPIO Bank1, MIO) + * (OFFSET, MASK, VALUE) (0XFF0A0248, 0x03FFFFFFU ,0x00000020U) + */ + PSU_Mask_Write(GPIO_OEN_1_OFFSET, 0x03FFFFFFU, 0x00000020U); +/*##################################################################### */ + + /* + * OUTPUT ENABLE BANK 2 + */ + /* + * MASK_DATA_0_LSW LOW BANK [15:0] + */ + /* + * MASK_DATA_0_MSW LOW BANK [25:16] + */ + /* + * MASK_DATA_1_LSW LOW BANK [41:26] + */ + /* + * Register : MASK_DATA_1_LSW @ 0XFF0A0008 + + * Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW] + * PSU_GPIO_MASK_DATA_1_LSW_MASK_1_LSW 0xffdf + + * Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW] + * PSU_GPIO_MASK_DATA_1_LSW_DATA_1_LSW 0x20 + + * Maskable Output Data (GPIO Bank1, MIO, Lower 16bits) + * (OFFSET, MASK, VALUE) (0XFF0A0008, 0xFFFFFFFFU ,0xFFDF0020U) + */ + PSU_Mask_Write(GPIO_MASK_DATA_1_LSW_OFFSET, + 0xFFFFFFFFU, 0xFFDF0020U); +/*##################################################################### */ + + /* + * MASK_DATA_1_MSW HIGH BANK [51:42] + */ + /* + * MASK_DATA_1_LSW HIGH BANK [67:52] + */ + /* + * MASK_DATA_1_LSW HIGH BANK [77:68] + */ + /* + * ADD 1 MS DELAY + */ + mask_delay(1); + +/*##################################################################### */ + + /* + * MASK_DATA_0_LSW LOW BANK [15:0] + */ + /* + * MASK_DATA_0_MSW LOW BANK [25:16] + */ + /* + * MASK_DATA_1_LSW LOW BANK [41:26] + */ + /* + * Register : MASK_DATA_1_LSW @ 0XFF0A0008 + + * Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW] + * PSU_GPIO_MASK_DATA_1_LSW_MASK_1_LSW 0xffdf + + * Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW] + * PSU_GPIO_MASK_DATA_1_LSW_DATA_1_LSW 0x0 + + * Maskable Output Data (GPIO Bank1, MIO, Lower 16bits) + * (OFFSET, MASK, VALUE) (0XFF0A0008, 0xFFFFFFFFU ,0xFFDF0000U) + */ + PSU_Mask_Write(GPIO_MASK_DATA_1_LSW_OFFSET, + 0xFFFFFFFFU, 0xFFDF0000U); +/*##################################################################### */ + + /* + * MASK_DATA_1_MSW HIGH BANK [51:42] + */ + /* + * MASK_DATA_1_LSW HIGH BANK [67:52] + */ + /* + * MASK_DATA_1_LSW HIGH BANK [77:68] + */ + /* + * ADD 5 MS DELAY + */ + mask_delay(5); + +/*##################################################################### */ + + + return 1; } -unsigned long psu_peripherals_powerdwn_data() { - // : POWER DOWN REQUEST INTERRUPT ENABLE - // : POWER DOWN TRIGGER +unsigned long psu_post_config_data(void) +{ + /* + * POST_CONFIG + */ - return 1; + return 1; } -unsigned long psu_lpd_xppu_data() { - // : XPPU INTERRUPT ENABLE - /*Register : IEN @ 0XFF980018

+unsigned long psu_peripherals_powerdwn_data(void) +{ + /* + * POWER DOWN REQUEST INTERRUPT ENABLE + */ + /* + * POWER DOWN TRIGGER + */ - See Interuppt Status Register for details - PSU_LPD_XPPU_CFG_IEN_APER_PARITY 0X1 - - See Interuppt Status Register for details - PSU_LPD_XPPU_CFG_IEN_APER_TZ 0X1 - - See Interuppt Status Register for details - PSU_LPD_XPPU_CFG_IEN_APER_PERM 0X1 - - See Interuppt Status Register for details - PSU_LPD_XPPU_CFG_IEN_MID_PARITY 0X1 - - See Interuppt Status Register for details - PSU_LPD_XPPU_CFG_IEN_MID_RO 0X1 - - See Interuppt Status Register for details - PSU_LPD_XPPU_CFG_IEN_MID_MISS 0X1 - - See Interuppt Status Register for details - PSU_LPD_XPPU_CFG_IEN_INV_APB 0X1 - - Interrupt Enable Register - (OFFSET, MASK, VALUE) (0XFF980018, 0x000000EFU ,0x000000EFU) - RegMask = (LPD_XPPU_CFG_IEN_APER_PARITY_MASK | LPD_XPPU_CFG_IEN_APER_TZ_MASK | LPD_XPPU_CFG_IEN_APER_PERM_MASK | LPD_XPPU_CFG_IEN_MID_PARITY_MASK | LPD_XPPU_CFG_IEN_MID_RO_MASK | LPD_XPPU_CFG_IEN_MID_MISS_MASK | LPD_XPPU_CFG_IEN_INV_APB_MASK | 0 ); - - RegVal = ((0x00000001U << LPD_XPPU_CFG_IEN_APER_PARITY_SHIFT - | 0x00000001U << LPD_XPPU_CFG_IEN_APER_TZ_SHIFT - | 0x00000001U << LPD_XPPU_CFG_IEN_APER_PERM_SHIFT - | 0x00000001U << LPD_XPPU_CFG_IEN_MID_PARITY_SHIFT - | 0x00000001U << LPD_XPPU_CFG_IEN_MID_RO_SHIFT - | 0x00000001U << LPD_XPPU_CFG_IEN_MID_MISS_SHIFT - | 0x00000001U << LPD_XPPU_CFG_IEN_INV_APB_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (LPD_XPPU_CFG_IEN_OFFSET ,0x000000EFU ,0x000000EFU); - /*############################################################################################################################ */ - - - return 1; + return 1; } -unsigned long psu_ddr_xmpu0_data() { +unsigned long psu_lpd_xppu_data(void) +{ + /* + * MASTER ID LIST + */ + /* + * APERTURE PERMISIION LIST + */ + /* + * APERTURE NAME: UART0, START ADDRESS: FF000000, END ADDRESS: FF00FFFF + */ + /* + * APERTURE NAME: UART1, START ADDRESS: FF010000, END ADDRESS: FF01FFFF + */ + /* + * APERTURE NAME: I2C0, START ADDRESS: FF020000, END ADDRESS: FF02FFFF + */ + /* + * APERTURE NAME: I2C1, START ADDRESS: FF030000, END ADDRESS: FF03FFFF + */ + /* + * APERTURE NAME: SPI0, START ADDRESS: FF040000, END ADDRESS: FF04FFFF + */ + /* + * APERTURE NAME: SPI1, START ADDRESS: FF050000, END ADDRESS: FF05FFFF + */ + /* + * APERTURE NAME: CAN0, START ADDRESS: FF060000, END ADDRESS: FF06FFFF + */ + /* + * APERTURE NAME: CAN1, START ADDRESS: FF070000, END ADDRESS: FF07FFFF + */ + /* + * APERTURE NAME: RPU_UNUSED_12, START ADDRESS: FF080000, END ADDRESS: FF09 + * FFFF + */ + /* + * APERTURE NAME: RPU_UNUSED_12, START ADDRESS: FF080000, END ADDRESS: FF09 + * FFFF + */ + /* + * APERTURE NAME: GPIO, START ADDRESS: FF0A0000, END ADDRESS: FF0AFFFF + */ + /* + * APERTURE NAME: GEM0, START ADDRESS: FF0B0000, END ADDRESS: FF0BFFFF + */ + /* + * APERTURE NAME: GEM1, START ADDRESS: FF0C0000, END ADDRESS: FF0CFFFF + */ + /* + * APERTURE NAME: GEM2, START ADDRESS: FF0D0000, END ADDRESS: FF0DFFFF + */ + /* + * APERTURE NAME: GEM3, START ADDRESS: FF0E0000, END ADDRESS: FF0EFFFF + */ + /* + * APERTURE NAME: QSPI, START ADDRESS: FF0F0000, END ADDRESS: FF0FFFFF + */ + /* + * APERTURE NAME: NAND, START ADDRESS: FF100000, END ADDRESS: FF10FFFF + */ + /* + * APERTURE NAME: TTC0, START ADDRESS: FF110000, END ADDRESS: FF11FFFF + */ + /* + * APERTURE NAME: TTC1, START ADDRESS: FF120000, END ADDRESS: FF12FFFF + */ + /* + * APERTURE NAME: TTC2, START ADDRESS: FF130000, END ADDRESS: FF13FFFF + */ + /* + * APERTURE NAME: TTC3, START ADDRESS: FF140000, END ADDRESS: FF14FFFF + */ + /* + * APERTURE NAME: SWDT, START ADDRESS: FF150000, END ADDRESS: FF15FFFF + */ + /* + * APERTURE NAME: SD0, START ADDRESS: FF160000, END ADDRESS: FF16FFFF + */ + /* + * APERTURE NAME: SD1, START ADDRESS: FF170000, END ADDRESS: FF17FFFF + */ + /* + * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + */ + /* + * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + */ + /* + * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + */ + /* + * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + */ + /* + * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + */ + /* + * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + */ + /* + * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + */ + /* + * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + */ + /* + * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + */ + /* + * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + */ + /* + * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + */ + /* + * APERTURE NAME: IOU_SLCR, START ADDRESS: FF180000, END ADDRESS: FF23FFFF + */ + /* + * APERTURE NAME: IOU_SECURE_SLCR, START ADDRESS: FF240000, END ADDRESS: FF + * 24FFFF + */ + /* + * APERTURE NAME: IOU_SCNTR, START ADDRESS: FF250000, END ADDRESS: FF25FFFF + */ + /* + * APERTURE NAME: IOU_SCNTRS, START ADDRESS: FF260000, END ADDRESS: FF26FFF + * F + */ + /* + * APERTURE NAME: RPU_UNUSED_11, START ADDRESS: FF270000, END ADDRESS: FF2A + * FFFF + */ + /* + * APERTURE NAME: RPU_UNUSED_11, START ADDRESS: FF270000, END ADDRESS: FF2A + * FFFF + */ + /* + * APERTURE NAME: RPU_UNUSED_11, START ADDRESS: FF270000, END ADDRESS: FF2A + * FFFF + */ + /* + * APERTURE NAME: RPU_UNUSED_11, START ADDRESS: FF270000, END ADDRESS: FF2A + * FFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_14, START ADDRESS: FF2B0000, END ADDRESS: FF2F + * FFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_14, START ADDRESS: FF2B0000, END ADDRESS: FF2F + * FFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_14, START ADDRESS: FF2B0000, END ADDRESS: FF2F + * FFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_14, START ADDRESS: FF2B0000, END ADDRESS: FF2F + * FFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_14, START ADDRESS: FF2B0000, END ADDRESS: FF2F + * FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF + */ + /* + * APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF + */ + /* + * APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF + */ + /* + * APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF + */ + /* + * APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF + */ + /* + * APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF + */ + /* + * APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF + */ + /* + * APERTURE NAME: IPI_CTRL, START ADDRESS: FF380000, END ADDRESS: FF3FFFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_1, START ADDRESS: FF400000, END ADDRESS: FF40F + * FFF + */ + /* + * APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + */ + /* + * APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + */ + /* + * APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + */ + /* + * APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + */ + /* + * APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + */ + /* + * APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + */ + /* + * APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + */ + /* + * APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + */ + /* + * APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + */ + /* + * APERTURE NAME: LPD_SLCR, START ADDRESS: FF410000, END ADDRESS: FF4AFFFF + */ + /* + * APERTURE NAME: LPD_SLCR_SECURE, START ADDRESS: FF4B0000, END ADDRESS: FF + * 4DFFFF + */ + /* + * APERTURE NAME: LPD_SLCR_SECURE, START ADDRESS: FF4B0000, END ADDRESS: FF + * 4DFFFF + */ + /* + * APERTURE NAME: LPD_SLCR_SECURE, START ADDRESS: FF4B0000, END ADDRESS: FF + * 4DFFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_2, START ADDRESS: FF4E0000, END ADDRESS: FF5DF + * FFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: CRL_APB, START ADDRESS: FF5E0000, END ADDRESS: FF85FFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_3, START ADDRESS: FF860000, END ADDRESS: FF95F + * FFF + */ + /* + * APERTURE NAME: OCM_SLCR, START ADDRESS: FF960000, END ADDRESS: FF96FFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_4, START ADDRESS: FF970000, END ADDRESS: FF97F + * FFF + */ + /* + * APERTURE NAME: LPD_XPPU, START ADDRESS: FF980000, END ADDRESS: FF99FFFF + */ + /* + * APERTURE NAME: RPU, START ADDRESS: FF9A0000, END ADDRESS: FF9AFFFF + */ + /* + * APERTURE NAME: AFIFM6, START ADDRESS: FF9B0000, END ADDRESS: FF9BFFFF + */ + /* + * APERTURE NAME: LPD_XPPU_SINK, START ADDRESS: FF9C0000, END ADDRESS: FF9C + * FFFF + */ + /* + * APERTURE NAME: USB3_0, START ADDRESS: FF9D0000, END ADDRESS: FF9DFFFF + */ + /* + * APERTURE NAME: USB3_1, START ADDRESS: FF9E0000, END ADDRESS: FF9EFFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_5, START ADDRESS: FF9F0000, END ADDRESS: FF9FF + * FFF + */ + /* + * APERTURE NAME: APM0, START ADDRESS: FFA00000, END ADDRESS: FFA0FFFF + */ + /* + * APERTURE NAME: APM1, START ADDRESS: FFA10000, END ADDRESS: FFA1FFFF + */ + /* + * APERTURE NAME: APM_INTC_IOU, START ADDRESS: FFA20000, END ADDRESS: FFA2F + * FFF + */ + /* + * APERTURE NAME: APM_FPD_LPD, START ADDRESS: FFA30000, END ADDRESS: FFA3FF + * FF + */ + /* + * APERTURE NAME: LPD_UNUSED_6, START ADDRESS: FFA40000, END ADDRESS: FFA4F + * FFF + */ + /* + * APERTURE NAME: AMS, START ADDRESS: FFA50000, END ADDRESS: FFA5FFFF + */ + /* + * APERTURE NAME: RTC, START ADDRESS: FFA60000, END ADDRESS: FFA6FFFF + */ + /* + * APERTURE NAME: OCM_XMPU_CFG, START ADDRESS: FFA70000, END ADDRESS: FFA7F + * FFF + */ + /* + * APERTURE NAME: ADMA_0, START ADDRESS: FFA80000, END ADDRESS: FFA8FFFF + */ + /* + * APERTURE NAME: ADMA_1, START ADDRESS: FFA90000, END ADDRESS: FFA9FFFF + */ + /* + * APERTURE NAME: ADMA_2, START ADDRESS: FFAA0000, END ADDRESS: FFAAFFFF + */ + /* + * APERTURE NAME: ADMA_3, START ADDRESS: FFAB0000, END ADDRESS: FFABFFFF + */ + /* + * APERTURE NAME: ADMA_4, START ADDRESS: FFAC0000, END ADDRESS: FFACFFFF + */ + /* + * APERTURE NAME: ADMA_5, START ADDRESS: FFAD0000, END ADDRESS: FFADFFFF + */ + /* + * APERTURE NAME: ADMA_6, START ADDRESS: FFAE0000, END ADDRESS: FFAEFFFF + */ + /* + * APERTURE NAME: ADMA_7, START ADDRESS: FFAF0000, END ADDRESS: FFAFFFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_7, START ADDRESS: FFB00000, END ADDRESS: FFBFF + * FFF + */ + /* + * APERTURE NAME: CSU_ROM, START ADDRESS: FFC00000, END ADDRESS: FFC1FFFF + */ + /* + * APERTURE NAME: CSU_ROM, START ADDRESS: FFC00000, END ADDRESS: FFC1FFFF + */ + /* + * APERTURE NAME: CSU_LOCAL, START ADDRESS: FFC20000, END ADDRESS: FFC2FFFF + */ + /* + * APERTURE NAME: PUF, START ADDRESS: FFC30000, END ADDRESS: FFC3FFFF + */ + /* + * APERTURE NAME: CSU_RAM, START ADDRESS: FFC40000, END ADDRESS: FFC5FFFF + */ + /* + * APERTURE NAME: CSU_RAM, START ADDRESS: FFC40000, END ADDRESS: FFC5FFFF + */ + /* + * APERTURE NAME: CSU_IOMODULE, START ADDRESS: FFC60000, END ADDRESS: FFC7F + * FFF + */ + /* + * APERTURE NAME: CSU_IOMODULE, START ADDRESS: FFC60000, END ADDRESS: FFC7F + * FFF + */ + /* + * APERTURE NAME: CSUDMA, START ADDRESS: FFC80000, END ADDRESS: FFC9FFFF + */ + /* + * APERTURE NAME: CSUDMA, START ADDRESS: FFC80000, END ADDRESS: FFC9FFFF + */ + /* + * APERTURE NAME: CSU, START ADDRESS: FFCA0000, END ADDRESS: FFCAFFFF + */ + /* + * APERTURE NAME: CSU_WDT, START ADDRESS: FFCB0000, END ADDRESS: FFCBFFFF + */ + /* + * APERTURE NAME: EFUSE, START ADDRESS: FFCC0000, END ADDRESS: FFCCFFFF + */ + /* + * APERTURE NAME: BBRAM, START ADDRESS: FFCD0000, END ADDRESS: FFCDFFFF + */ + /* + * APERTURE NAME: RSA_CORE, START ADDRESS: FFCE0000, END ADDRESS: FFCEFFFF + */ + /* + * APERTURE NAME: MBISTJTAG, START ADDRESS: FFCF0000, END ADDRESS: FFCFFFFF + */ + /* + * APERTURE NAME: PMU_ROM, START ADDRESS: FFD00000, END ADDRESS: FFD3FFFF + */ + /* + * APERTURE NAME: PMU_ROM, START ADDRESS: FFD00000, END ADDRESS: FFD3FFFF + */ + /* + * APERTURE NAME: PMU_ROM, START ADDRESS: FFD00000, END ADDRESS: FFD3FFFF + */ + /* + * APERTURE NAME: PMU_ROM, START ADDRESS: FFD00000, END ADDRESS: FFD3FFFF + */ + /* + * APERTURE NAME: PMU_IOMODULE, START ADDRESS: FFD40000, END ADDRESS: FFD5F + * FFF + */ + /* + * APERTURE NAME: PMU_IOMODULE, START ADDRESS: FFD40000, END ADDRESS: FFD5F + * FFF + */ + /* + * APERTURE NAME: PMU_LOCAL, START ADDRESS: FFD60000, END ADDRESS: FFD7FFFF + */ + /* + * APERTURE NAME: PMU_LOCAL, START ADDRESS: FFD60000, END ADDRESS: FFD7FFFF + */ + /* + * APERTURE NAME: PMU_GLOBAL, START ADDRESS: FFD80000, END ADDRESS: FFDBFFF + * F + */ + /* + * APERTURE NAME: PMU_GLOBAL, START ADDRESS: FFD80000, END ADDRESS: FFDBFFF + * F + */ + /* + * APERTURE NAME: PMU_GLOBAL, START ADDRESS: FFD80000, END ADDRESS: FFDBFFF + * F + */ + /* + * APERTURE NAME: PMU_GLOBAL, START ADDRESS: FFD80000, END ADDRESS: FFDBFFF + * F + */ + /* + * APERTURE NAME: PMU_RAM, START ADDRESS: FFDC0000, END ADDRESS: FFDFFFFF + */ + /* + * APERTURE NAME: PMU_RAM, START ADDRESS: FFDC0000, END ADDRESS: FFDFFFFF + */ + /* + * APERTURE NAME: PMU_RAM, START ADDRESS: FFDC0000, END ADDRESS: FFDFFFFF + */ + /* + * APERTURE NAME: PMU_RAM, START ADDRESS: FFDC0000, END ADDRESS: FFDFFFFF + */ + /* + * APERTURE NAME: R5_0_ATCM, START ADDRESS: FFE00000, END ADDRESS: FFE0FFFF + */ + /* + * APERTURE NAME: R5_0_ATCM_LOCKSTEP, START ADDRESS: FFE10000, END ADDRESS: + * FFE1FFFF + */ + /* + * APERTURE NAME: R5_0_BTCM, START ADDRESS: FFE20000, END ADDRESS: FFE2FFFF + */ + /* + * APERTURE NAME: R5_0_BTCM_LOCKSTEP, START ADDRESS: FFE30000, END ADDRESS: + * FFE3FFFF + */ + /* + * APERTURE NAME: R5_0_INSTRUCTION_CACHE, START ADDRESS: FFE40000, END ADDR + * ESS: FFE4FFFF + */ + /* + * APERTURE NAME: R5_0_DATA_CACHE, START ADDRESS: FFE50000, END ADDRESS: FF + * E5FFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_8, START ADDRESS: FFE60000, END ADDRESS: FFE8F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_8, START ADDRESS: FFE60000, END ADDRESS: FFE8F + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_8, START ADDRESS: FFE60000, END ADDRESS: FFE8F + * FFF + */ + /* + * APERTURE NAME: R5_1_ATCM_, START ADDRESS: FFE90000, END ADDRESS: FFE9FFF + * F + */ + /* + * APERTURE NAME: RPU_UNUSED_10, START ADDRESS: FFEA0000, END ADDRESS: FFEA + * FFFF + */ + /* + * APERTURE NAME: R5_1_BTCM_, START ADDRESS: FFEB0000, END ADDRESS: FFEBFFF + * F + */ + /* + * APERTURE NAME: R5_1_INSTRUCTION_CACHE, START ADDRESS: FFEC0000, END ADDR + * ESS: FFECFFFF + */ + /* + * APERTURE NAME: R5_1_DATA_CACHE, START ADDRESS: FFED0000, END ADDRESS: FF + * EDFFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_9, START ADDRESS: FFEE0000, END ADDRESS: FFFBF + * FFF + */ + /* + * APERTURE NAME: LPD_UNUSED_15, START ADDRESS: FFFD0000, END ADDRESS: FFFF + * FFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_15, START ADDRESS: FFFD0000, END ADDRESS: FFFF + * FFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_15, START ADDRESS: FFFD0000, END ADDRESS: FFFF + * FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_1, START ADDRESS: FF310000, END ADDRESS: FF31FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_2, START ADDRESS: FF320000, END ADDRESS: FF32FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_0, START ADDRESS: FF300000, END ADDRESS: FF30FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_7, START ADDRESS: FF340000, END ADDRESS: FF34FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_8, START ADDRESS: FF350000, END ADDRESS: FF35FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_9, START ADDRESS: FF360000, END ADDRESS: FF36FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_10, START ADDRESS: FF370000, END ADDRESS: FF37FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IPI_PMU, START ADDRESS: FF330000, END ADDRESS: FF33FFFF + */ + /* + * APERTURE NAME: IOU_GPV, START ADDRESS: FE000000, END ADDRESS: FE0FFFFF + */ + /* + * APERTURE NAME: LPD_GPV, START ADDRESS: FE100000, END ADDRESS: FE1FFFFF + */ + /* + * APERTURE NAME: USB3_0_XHCI, START ADDRESS: FE200000, END ADDRESS: FE2FFF + * FF + */ + /* + * APERTURE NAME: USB3_1_XHCI, START ADDRESS: FE300000, END ADDRESS: FE3FFF + * FF + */ + /* + * APERTURE NAME: LPD_UNUSED_13, START ADDRESS: FE400000, END ADDRESS: FE7F + * FFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_13, START ADDRESS: FE400000, END ADDRESS: FE7F + * FFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_13, START ADDRESS: FE400000, END ADDRESS: FE7F + * FFFF + */ + /* + * APERTURE NAME: LPD_UNUSED_13, START ADDRESS: FE400000, END ADDRESS: FE7F + * FFFF + */ + /* + * APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF + */ + /* + * APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF + */ + /* + * APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF + */ + /* + * APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF + */ + /* + * APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF + */ + /* + * APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF + */ + /* + * APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF + */ + /* + * APERTURE NAME: CORESIGHT, START ADDRESS: FE800000, END ADDRESS: FEFFFFFF + */ + /* + * APERTURE NAME: QSPI_LINEAR_ADDRESS, START ADDRESS: C0000000, END ADDRESS + * : DFFFFFFF + */ + /* + * XPPU CONTROL + */ - return 1; + return 1; } -unsigned long psu_ddr_xmpu1_data() { +unsigned long psu_ddr_xmpu0_data(void) +{ + /* + * DDR XMPU0 + */ - return 1; + return 1; } -unsigned long psu_ddr_xmpu2_data() { +unsigned long psu_ddr_xmpu1_data(void) +{ + /* + * DDR XMPU1 + */ - return 1; + return 1; } -unsigned long psu_ddr_xmpu3_data() { +unsigned long psu_ddr_xmpu2_data(void) +{ + /* + * DDR XMPU2 + */ - return 1; + return 1; } -unsigned long psu_ddr_xmpu4_data() { +unsigned long psu_ddr_xmpu3_data(void) +{ + /* + * DDR XMPU3 + */ - return 1; + return 1; } -unsigned long psu_ddr_xmpu5_data() { +unsigned long psu_ddr_xmpu4_data(void) +{ + /* + * DDR XMPU4 + */ - return 1; + return 1; } -unsigned long psu_ocm_xmpu_data() { +unsigned long psu_ddr_xmpu5_data(void) +{ + /* + * DDR XMPU5 + */ - return 1; + return 1; } -unsigned long psu_fpd_xmpu_data() { +unsigned long psu_ocm_xmpu_data(void) +{ + /* + * OCM XMPU + */ - return 1; + return 1; } -unsigned long psu_protection_lock_data() { +unsigned long psu_fpd_xmpu_data(void) +{ + /* + * FPD XMPU + */ - return 1; + return 1; } -unsigned long psu_apply_master_tz() { - // : RPU - // : DP TZ - // : SATA TZ - // : PCIE TZ - // : USB TZ - // : SD TZ - // : GEM TZ - // : QSPI TZ - // : NAND TZ +unsigned long psu_protection_lock_data(void) +{ + /* + * LOCKING PROTECTION MODULE + */ + /* + * XPPU LOCK + */ + /* + * APERTURE NAME: LPD_XPPU, START ADDRESS: FF980000, END ADDRESS: FF99FFFF + */ + /* + * XMPU LOCK + */ + /* + * LOCK OCM XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER + */ + /* + * LOCK FPD XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER + */ + /* + * LOCK DDR XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER + */ + /* + * LOCK DDR XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER + */ + /* + * LOCK DDR XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER + */ + /* + * LOCK DDR XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER + */ + /* + * LOCK DDR XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER + */ + /* + * LOCK DDR XMPU ONLY IF IT IS NOT PROTECTED BY ANY MASTER + */ - return 1; + return 1; } -unsigned long psu_serdes_init_data() { - // : SERDES INITIALIZATION - // : GT REFERENCE CLOCK SOURCE SELECTION - /*Register : PLL_REF_SEL0 @ 0XFD410000

+unsigned long psu_apply_master_tz(void) +{ + /* + * RPU + */ + /* + * DP TZ + */ + /* + * Register : slcr_dpdma @ 0XFD690040 - PLL0 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - - 4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135 - Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved - PSU_SERDES_PLL_REF_SEL0_PLLREFSEL0 0xD + * TrustZone classification for DisplayPort DMA + * PSU_FPD_SLCR_SECURE_SLCR_DPDMA_TZ 1 - PLL0 Reference Selection Register - (OFFSET, MASK, VALUE) (0XFD410000, 0x0000001FU ,0x0000000DU) - RegMask = (SERDES_PLL_REF_SEL0_PLLREFSEL0_MASK | 0 ); + * DPDMA TrustZone Settings + * (OFFSET, MASK, VALUE) (0XFD690040, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(FPD_SLCR_SECURE_SLCR_DPDMA_OFFSET, + 0x00000001U, 0x00000001U); +/*##################################################################### */ - RegVal = ((0x0000000DU << SERDES_PLL_REF_SEL0_PLLREFSEL0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_PLL_REF_SEL0_OFFSET ,0x0000001FU ,0x0000000DU); - /*############################################################################################################################ */ + /* + * SATA TZ + */ + /* + * PCIE TZ + */ + /* + * Register : slcr_pcie @ 0XFD690030 - /*Register : PLL_REF_SEL1 @ 0XFD410004

+ * TrustZone classification for DMA Channel 0 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_0 1 - PLL1 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - - 4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135 - Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved - PSU_SERDES_PLL_REF_SEL1_PLLREFSEL1 0x9 + * TrustZone classification for DMA Channel 1 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_1 1 - PLL1 Reference Selection Register - (OFFSET, MASK, VALUE) (0XFD410004, 0x0000001FU ,0x00000009U) - RegMask = (SERDES_PLL_REF_SEL1_PLLREFSEL1_MASK | 0 ); + * TrustZone classification for DMA Channel 2 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_2 1 - RegVal = ((0x00000009U << SERDES_PLL_REF_SEL1_PLLREFSEL1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_PLL_REF_SEL1_OFFSET ,0x0000001FU ,0x00000009U); - /*############################################################################################################################ */ + * TrustZone classification for DMA Channel 3 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_3 1 - /*Register : PLL_REF_SEL2 @ 0XFD410008

+ * TrustZone classification for Ingress Address Translation 0 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_0 1 - PLL2 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - - 4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135 - Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved - PSU_SERDES_PLL_REF_SEL2_PLLREFSEL2 0x8 + * TrustZone classification for Ingress Address Translation 1 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_1 1 - PLL2 Reference Selection Register - (OFFSET, MASK, VALUE) (0XFD410008, 0x0000001FU ,0x00000008U) - RegMask = (SERDES_PLL_REF_SEL2_PLLREFSEL2_MASK | 0 ); + * TrustZone classification for Ingress Address Translation 2 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_2 1 - RegVal = ((0x00000008U << SERDES_PLL_REF_SEL2_PLLREFSEL2_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_PLL_REF_SEL2_OFFSET ,0x0000001FU ,0x00000008U); - /*############################################################################################################################ */ + * TrustZone classification for Ingress Address Translation 3 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_3 1 + + * TrustZone classification for Ingress Address Translation 4 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_4 1 + + * TrustZone classification for Ingress Address Translation 5 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_5 1 + + * TrustZone classification for Ingress Address Translation 6 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_6 1 - /*Register : PLL_REF_SEL3 @ 0XFD41000C

- - PLL3 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - - 4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135 - Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved - PSU_SERDES_PLL_REF_SEL3_PLLREFSEL3 0xF - - PLL3 Reference Selection Register - (OFFSET, MASK, VALUE) (0XFD41000C, 0x0000001FU ,0x0000000FU) - RegMask = (SERDES_PLL_REF_SEL3_PLLREFSEL3_MASK | 0 ); - - RegVal = ((0x0000000FU << SERDES_PLL_REF_SEL3_PLLREFSEL3_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_PLL_REF_SEL3_OFFSET ,0x0000001FU ,0x0000000FU); - /*############################################################################################################################ */ - - // : GT REFERENCE CLOCK FREQUENCY SELECTION - /*Register : L0_L0_REF_CLK_SEL @ 0XFD402860

- - Sel of lane 0 ref clock local mux. Set to 1 to select lane 0 slicer output. Set to 0 to select lane0 ref clock mux output. - PSU_SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL 0x1 - - Lane0 Ref Clock Selection Register - (OFFSET, MASK, VALUE) (0XFD402860, 0x00000080U ,0x00000080U) - RegMask = (SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_L0_REF_CLK_SEL_OFFSET ,0x00000080U ,0x00000080U); - /*############################################################################################################################ */ - - /*Register : L0_L1_REF_CLK_SEL @ 0XFD402864

- - Sel of lane 1 ref clock local mux. Set to 1 to select lane 1 slicer output. Set to 0 to select lane1 ref clock mux output. - PSU_SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL 0x0 - - Bit 3 of lane 1 ref clock mux one hot sel. Set to 1 to select lane 3 slicer output from ref clock network - PSU_SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3 0x1 - - Lane1 Ref Clock Selection Register - (OFFSET, MASK, VALUE) (0XFD402864, 0x00000088U ,0x00000008U) - RegMask = (SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_MASK | SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_MASK | 0 ); - - RegVal = ((0x00000000U << SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_SHIFT - | 0x00000001U << SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_L1_REF_CLK_SEL_OFFSET ,0x00000088U ,0x00000008U); - /*############################################################################################################################ */ - - /*Register : L0_L2_REF_CLK_SEL @ 0XFD402868

- - Sel of lane 2 ref clock local mux. Set to 1 to select lane 1 slicer output. Set to 0 to select lane2 ref clock mux output. - PSU_SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL 0x1 - - Lane2 Ref Clock Selection Register - (OFFSET, MASK, VALUE) (0XFD402868, 0x00000080U ,0x00000080U) - RegMask = (SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_L2_REF_CLK_SEL_OFFSET ,0x00000080U ,0x00000080U); - /*############################################################################################################################ */ - - /*Register : L0_L3_REF_CLK_SEL @ 0XFD40286C

- - Sel of lane 3 ref clock local mux. Set to 1 to select lane 3 slicer output. Set to 0 to select lane3 ref clock mux output. - PSU_SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL 0x0 - - Bit 1 of lane 3 ref clock mux one hot sel. Set to 1 to select lane 1 slicer output from ref clock network - PSU_SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1 0x1 - - Lane3 Ref Clock Selection Register - (OFFSET, MASK, VALUE) (0XFD40286C, 0x00000082U ,0x00000002U) - RegMask = (SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_MASK | SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_MASK | 0 ); - - RegVal = ((0x00000000U << SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_SHIFT - | 0x00000001U << SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_L3_REF_CLK_SEL_OFFSET ,0x00000082U ,0x00000002U); - /*############################################################################################################################ */ - - // : ENABLE SPREAD SPECTRUM - /*Register : L2_TM_PLL_DIG_37 @ 0XFD40A094

- - Enable/Disable coarse code satureation limiting logic - PSU_SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION 0x1 - - Test mode register 37 - (OFFSET, MASK, VALUE) (0XFD40A094, 0x00000010U ,0x00000010U) - RegMask = (SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_TM_PLL_DIG_37_OFFSET ,0x00000010U ,0x00000010U); - /*############################################################################################################################ */ - - /*Register : L2_PLL_SS_STEPS_0_LSB @ 0XFD40A368

- - Spread Spectrum No of Steps [7:0] - PSU_SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB 0x38 - - Spread Spectrum No of Steps bits 7:0 - (OFFSET, MASK, VALUE) (0XFD40A368, 0x000000FFU ,0x00000038U) - RegMask = (SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK | 0 ); - - RegVal = ((0x00000038U << SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_PLL_SS_STEPS_0_LSB_OFFSET ,0x000000FFU ,0x00000038U); - /*############################################################################################################################ */ - - /*Register : L2_PLL_SS_STEPS_1_MSB @ 0XFD40A36C

- - Spread Spectrum No of Steps [10:8] - PSU_SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB 0x03 - - Spread Spectrum No of Steps bits 10:8 - (OFFSET, MASK, VALUE) (0XFD40A36C, 0x00000007U ,0x00000003U) - RegMask = (SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK | 0 ); - - RegVal = ((0x00000003U << SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_PLL_SS_STEPS_1_MSB_OFFSET ,0x00000007U ,0x00000003U); - /*############################################################################################################################ */ - - /*Register : L3_PLL_SS_STEPS_0_LSB @ 0XFD40E368

- - Spread Spectrum No of Steps [7:0] - PSU_SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB 0xE0 - - Spread Spectrum No of Steps bits 7:0 - (OFFSET, MASK, VALUE) (0XFD40E368, 0x000000FFU ,0x000000E0U) - RegMask = (SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK | 0 ); - - RegVal = ((0x000000E0U << SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_PLL_SS_STEPS_0_LSB_OFFSET ,0x000000FFU ,0x000000E0U); - /*############################################################################################################################ */ - - /*Register : L3_PLL_SS_STEPS_1_MSB @ 0XFD40E36C

- - Spread Spectrum No of Steps [10:8] - PSU_SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB 0x3 - - Spread Spectrum No of Steps bits 10:8 - (OFFSET, MASK, VALUE) (0XFD40E36C, 0x00000007U ,0x00000003U) - RegMask = (SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK | 0 ); - - RegVal = ((0x00000003U << SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_PLL_SS_STEPS_1_MSB_OFFSET ,0x00000007U ,0x00000003U); - /*############################################################################################################################ */ - - /*Register : L1_PLL_SS_STEPS_0_LSB @ 0XFD406368

- - Spread Spectrum No of Steps [7:0] - PSU_SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB 0x58 - - Spread Spectrum No of Steps bits 7:0 - (OFFSET, MASK, VALUE) (0XFD406368, 0x000000FFU ,0x00000058U) - RegMask = (SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK | 0 ); - - RegVal = ((0x00000058U << SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L1_PLL_SS_STEPS_0_LSB_OFFSET ,0x000000FFU ,0x00000058U); - /*############################################################################################################################ */ - - /*Register : L1_PLL_SS_STEPS_1_MSB @ 0XFD40636C

- - Spread Spectrum No of Steps [10:8] - PSU_SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB 0x3 - - Spread Spectrum No of Steps bits 10:8 - (OFFSET, MASK, VALUE) (0XFD40636C, 0x00000007U ,0x00000003U) - RegMask = (SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK | 0 ); - - RegVal = ((0x00000003U << SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L1_PLL_SS_STEPS_1_MSB_OFFSET ,0x00000007U ,0x00000003U); - /*############################################################################################################################ */ - - /*Register : L1_PLL_SS_STEP_SIZE_0_LSB @ 0XFD406370

- - Step Size for Spread Spectrum [7:0] - PSU_SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB 0x7C - - Step Size for Spread Spectrum LSB - (OFFSET, MASK, VALUE) (0XFD406370, 0x000000FFU ,0x0000007CU) - RegMask = (SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK | 0 ); - - RegVal = ((0x0000007CU << SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_OFFSET ,0x000000FFU ,0x0000007CU); - /*############################################################################################################################ */ - - /*Register : L1_PLL_SS_STEP_SIZE_1 @ 0XFD406374

- - Step Size for Spread Spectrum [15:8] - PSU_SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1 0x33 - - Step Size for Spread Spectrum 1 - (OFFSET, MASK, VALUE) (0XFD406374, 0x000000FFU ,0x00000033U) - RegMask = (SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK | 0 ); - - RegVal = ((0x00000033U << SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L1_PLL_SS_STEP_SIZE_1_OFFSET ,0x000000FFU ,0x00000033U); - /*############################################################################################################################ */ - - /*Register : L1_PLL_SS_STEP_SIZE_2 @ 0XFD406378

- - Step Size for Spread Spectrum [23:16] - PSU_SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2 0x2 - - Step Size for Spread Spectrum 2 - (OFFSET, MASK, VALUE) (0XFD406378, 0x000000FFU ,0x00000002U) - RegMask = (SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK | 0 ); - - RegVal = ((0x00000002U << SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L1_PLL_SS_STEP_SIZE_2_OFFSET ,0x000000FFU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : L1_PLL_SS_STEP_SIZE_3_MSB @ 0XFD40637C

- - Step Size for Spread Spectrum [25:24] - PSU_SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB 0x0 - - Enable/Disable test mode force on SS step size - PSU_SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE 0x1 - - Enable/Disable test mode force on SS no of steps - PSU_SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS 0x1 - - Enable force on enable Spread Spectrum - (OFFSET, MASK, VALUE) (0XFD40637C, 0x00000033U ,0x00000030U) - RegMask = (SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK | SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK | SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK | 0 ); - - RegVal = ((0x00000000U << SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT - | 0x00000001U << SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT - | 0x00000001U << SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_OFFSET ,0x00000033U ,0x00000030U); - /*############################################################################################################################ */ - - /*Register : L2_PLL_SS_STEP_SIZE_0_LSB @ 0XFD40A370

- - Step Size for Spread Spectrum [7:0] - PSU_SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB 0xF4 - - Step Size for Spread Spectrum LSB - (OFFSET, MASK, VALUE) (0XFD40A370, 0x000000FFU ,0x000000F4U) - RegMask = (SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK | 0 ); - - RegVal = ((0x000000F4U << SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_OFFSET ,0x000000FFU ,0x000000F4U); - /*############################################################################################################################ */ - - /*Register : L2_PLL_SS_STEP_SIZE_1 @ 0XFD40A374

- - Step Size for Spread Spectrum [15:8] - PSU_SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1 0x31 - - Step Size for Spread Spectrum 1 - (OFFSET, MASK, VALUE) (0XFD40A374, 0x000000FFU ,0x00000031U) - RegMask = (SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK | 0 ); - - RegVal = ((0x00000031U << SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_PLL_SS_STEP_SIZE_1_OFFSET ,0x000000FFU ,0x00000031U); - /*############################################################################################################################ */ - - /*Register : L2_PLL_SS_STEP_SIZE_2 @ 0XFD40A378

- - Step Size for Spread Spectrum [23:16] - PSU_SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2 0x2 - - Step Size for Spread Spectrum 2 - (OFFSET, MASK, VALUE) (0XFD40A378, 0x000000FFU ,0x00000002U) - RegMask = (SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK | 0 ); - - RegVal = ((0x00000002U << SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_PLL_SS_STEP_SIZE_2_OFFSET ,0x000000FFU ,0x00000002U); - /*############################################################################################################################ */ - - /*Register : L2_PLL_SS_STEP_SIZE_3_MSB @ 0XFD40A37C

- - Step Size for Spread Spectrum [25:24] - PSU_SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB 0x0 - - Enable/Disable test mode force on SS step size - PSU_SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE 0x1 - - Enable/Disable test mode force on SS no of steps - PSU_SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS 0x1 - - Enable force on enable Spread Spectrum - (OFFSET, MASK, VALUE) (0XFD40A37C, 0x00000033U ,0x00000030U) - RegMask = (SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK | SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK | SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK | 0 ); - - RegVal = ((0x00000000U << SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT - | 0x00000001U << SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT - | 0x00000001U << SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_OFFSET ,0x00000033U ,0x00000030U); - /*############################################################################################################################ */ - - /*Register : L3_PLL_SS_STEP_SIZE_0_LSB @ 0XFD40E370

- - Step Size for Spread Spectrum [7:0] - PSU_SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB 0xC9 - - Step Size for Spread Spectrum LSB - (OFFSET, MASK, VALUE) (0XFD40E370, 0x000000FFU ,0x000000C9U) - RegMask = (SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK | 0 ); - - RegVal = ((0x000000C9U << SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_OFFSET ,0x000000FFU ,0x000000C9U); - /*############################################################################################################################ */ - - /*Register : L3_PLL_SS_STEP_SIZE_1 @ 0XFD40E374

- - Step Size for Spread Spectrum [15:8] - PSU_SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1 0xD2 - - Step Size for Spread Spectrum 1 - (OFFSET, MASK, VALUE) (0XFD40E374, 0x000000FFU ,0x000000D2U) - RegMask = (SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK | 0 ); - - RegVal = ((0x000000D2U << SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_PLL_SS_STEP_SIZE_1_OFFSET ,0x000000FFU ,0x000000D2U); - /*############################################################################################################################ */ - - /*Register : L3_PLL_SS_STEP_SIZE_2 @ 0XFD40E378

- - Step Size for Spread Spectrum [23:16] - PSU_SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2 0x1 - - Step Size for Spread Spectrum 2 - (OFFSET, MASK, VALUE) (0XFD40E378, 0x000000FFU ,0x00000001U) - RegMask = (SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_PLL_SS_STEP_SIZE_2_OFFSET ,0x000000FFU ,0x00000001U); - /*############################################################################################################################ */ - - /*Register : L3_PLL_SS_STEP_SIZE_3_MSB @ 0XFD40E37C

- - Step Size for Spread Spectrum [25:24] - PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB 0x0 - - Enable/Disable test mode force on SS step size - PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE 0x1 - - Enable/Disable test mode force on SS no of steps - PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS 0x1 - - Enable test mode forcing on enable Spread Spectrum - PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS 0x1 - - Enable force on enable Spread Spectrum - (OFFSET, MASK, VALUE) (0XFD40E37C, 0x000000B3U ,0x000000B0U) - RegMask = (SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK | SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK | SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK | SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_MASK | 0 ); - - RegVal = ((0x00000000U << SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT - | 0x00000001U << SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT - | 0x00000001U << SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT - | 0x00000001U << SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_OFFSET ,0x000000B3U ,0x000000B0U); - /*############################################################################################################################ */ - - /*Register : L2_TM_DIG_6 @ 0XFD40906C

- - Bypass Descrambler - PSU_SERDES_L2_TM_DIG_6_BYPASS_DESCRAM 0x1 - - Enable Bypass for <1> TM_DIG_CTRL_6 - PSU_SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM 0x1 - - Data path test modes in decoder and descram - (OFFSET, MASK, VALUE) (0XFD40906C, 0x00000003U ,0x00000003U) - RegMask = (SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_MASK | SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_SHIFT - | 0x00000001U << SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_TM_DIG_6_OFFSET ,0x00000003U ,0x00000003U); - /*############################################################################################################################ */ - - /*Register : L2_TX_DIG_TM_61 @ 0XFD4080F4

- - Bypass scrambler signal - PSU_SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM 0x1 - - Enable/disable scrambler bypass signal - PSU_SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM 0x1 - - MPHY PLL Gear and bypass scrambler - (OFFSET, MASK, VALUE) (0XFD4080F4, 0x00000003U ,0x00000003U) - RegMask = (SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_MASK | SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_SHIFT - | 0x00000001U << SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_TX_DIG_TM_61_OFFSET ,0x00000003U ,0x00000003U); - /*############################################################################################################################ */ - - /*Register : L3_PLL_FBDIV_FRAC_3_MSB @ 0XFD40E360

- - Enable test mode force on fractional mode enable - PSU_SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC 0x1 - - Fractional feedback division control and fractional value for feedback division bits 26:24 - (OFFSET, MASK, VALUE) (0XFD40E360, 0x00000040U ,0x00000040U) - RegMask = (SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_PLL_FBDIV_FRAC_3_MSB_OFFSET ,0x00000040U ,0x00000040U); - /*############################################################################################################################ */ - - /*Register : L3_TM_DIG_6 @ 0XFD40D06C

- - Bypass 8b10b decoder - PSU_SERDES_L3_TM_DIG_6_BYPASS_DECODER 0x1 - - Enable Bypass for <3> TM_DIG_CTRL_6 - PSU_SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC 0x1 - - Bypass Descrambler - PSU_SERDES_L3_TM_DIG_6_BYPASS_DESCRAM 0x1 - - Enable Bypass for <1> TM_DIG_CTRL_6 - PSU_SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM 0x1 - - Data path test modes in decoder and descram - (OFFSET, MASK, VALUE) (0XFD40D06C, 0x0000000FU ,0x0000000FU) - RegMask = (SERDES_L3_TM_DIG_6_BYPASS_DECODER_MASK | SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_MASK | SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_MASK | SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L3_TM_DIG_6_BYPASS_DECODER_SHIFT - | 0x00000001U << SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_SHIFT - | 0x00000001U << SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_SHIFT - | 0x00000001U << SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_DIG_6_OFFSET ,0x0000000FU ,0x0000000FU); - /*############################################################################################################################ */ - - /*Register : L3_TX_DIG_TM_61 @ 0XFD40C0F4

- - Enable/disable encoder bypass signal - PSU_SERDES_L3_TX_DIG_TM_61_BYPASS_ENC 0x1 - - Bypass scrambler signal - PSU_SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM 0x1 - - Enable/disable scrambler bypass signal - PSU_SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM 0x1 - - MPHY PLL Gear and bypass scrambler - (OFFSET, MASK, VALUE) (0XFD40C0F4, 0x0000000BU ,0x0000000BU) - RegMask = (SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_MASK | SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_MASK | SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_SHIFT - | 0x00000001U << SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_SHIFT - | 0x00000001U << SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TX_DIG_TM_61_OFFSET ,0x0000000BU ,0x0000000BU); - /*############################################################################################################################ */ - - /*Register : L3_TXPMA_ST_0 @ 0XFD40CB00

- - PHY Mode: 4'b000 - PCIe, 4'b001 - USB3, 4'b0010 - SATA, 4'b0100 - SGMII, 4'b0101 - DP, 4'b1000 - MPHY - PSU_SERDES_L3_TXPMA_ST_0_TX_PHY_MODE 0x21 - - Opmode Info - (OFFSET, MASK, VALUE) (0XFD40CB00, 0x000000F0U ,0x000000F0U) - RegMask = (SERDES_L3_TXPMA_ST_0_TX_PHY_MODE_MASK | 0 ); - - RegVal = ((0x00000021U << SERDES_L3_TXPMA_ST_0_TX_PHY_MODE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TXPMA_ST_0_OFFSET ,0x000000F0U ,0x000000F0U); - /*############################################################################################################################ */ - - // : ENABLE CHICKEN BIT FOR PCIE AND USB - /*Register : L0_TM_AUX_0 @ 0XFD4010CC

- - Spare- not used - PSU_SERDES_L0_TM_AUX_0_BIT_2 1 - - Spare registers - (OFFSET, MASK, VALUE) (0XFD4010CC, 0x00000020U ,0x00000020U) - RegMask = (SERDES_L0_TM_AUX_0_BIT_2_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L0_TM_AUX_0_BIT_2_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_TM_AUX_0_OFFSET ,0x00000020U ,0x00000020U); - /*############################################################################################################################ */ - - /*Register : L2_TM_AUX_0 @ 0XFD4090CC

- - Spare- not used - PSU_SERDES_L2_TM_AUX_0_BIT_2 1 - - Spare registers - (OFFSET, MASK, VALUE) (0XFD4090CC, 0x00000020U ,0x00000020U) - RegMask = (SERDES_L2_TM_AUX_0_BIT_2_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L2_TM_AUX_0_BIT_2_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_TM_AUX_0_OFFSET ,0x00000020U ,0x00000020U); - /*############################################################################################################################ */ - - // : ENABLING EYE SURF - /*Register : L0_TM_DIG_8 @ 0XFD401074

- - Enable Eye Surf - PSU_SERDES_L0_TM_DIG_8_EYESURF_ENABLE 0x1 - - Test modes for Elastic buffer and enabling Eye Surf - (OFFSET, MASK, VALUE) (0XFD401074, 0x00000010U ,0x00000010U) - RegMask = (SERDES_L0_TM_DIG_8_EYESURF_ENABLE_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L0_TM_DIG_8_EYESURF_ENABLE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_TM_DIG_8_OFFSET ,0x00000010U ,0x00000010U); - /*############################################################################################################################ */ - - /*Register : L1_TM_DIG_8 @ 0XFD405074

- - Enable Eye Surf - PSU_SERDES_L1_TM_DIG_8_EYESURF_ENABLE 0x1 - - Test modes for Elastic buffer and enabling Eye Surf - (OFFSET, MASK, VALUE) (0XFD405074, 0x00000010U ,0x00000010U) - RegMask = (SERDES_L1_TM_DIG_8_EYESURF_ENABLE_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L1_TM_DIG_8_EYESURF_ENABLE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L1_TM_DIG_8_OFFSET ,0x00000010U ,0x00000010U); - /*############################################################################################################################ */ - - /*Register : L2_TM_DIG_8 @ 0XFD409074

- - Enable Eye Surf - PSU_SERDES_L2_TM_DIG_8_EYESURF_ENABLE 0x1 - - Test modes for Elastic buffer and enabling Eye Surf - (OFFSET, MASK, VALUE) (0XFD409074, 0x00000010U ,0x00000010U) - RegMask = (SERDES_L2_TM_DIG_8_EYESURF_ENABLE_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L2_TM_DIG_8_EYESURF_ENABLE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_TM_DIG_8_OFFSET ,0x00000010U ,0x00000010U); - /*############################################################################################################################ */ - - /*Register : L3_TM_DIG_8 @ 0XFD40D074

- - Enable Eye Surf - PSU_SERDES_L3_TM_DIG_8_EYESURF_ENABLE 0x1 - - Test modes for Elastic buffer and enabling Eye Surf - (OFFSET, MASK, VALUE) (0XFD40D074, 0x00000010U ,0x00000010U) - RegMask = (SERDES_L3_TM_DIG_8_EYESURF_ENABLE_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L3_TM_DIG_8_EYESURF_ENABLE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_DIG_8_OFFSET ,0x00000010U ,0x00000010U); - /*############################################################################################################################ */ - - // : ILL SETTINGS FOR GAIN AND LOCK SETTINGS - /*Register : L0_TM_MISC2 @ 0XFD40189C

- - ILL calib counts BYPASSED with calcode bits - PSU_SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS 0x1 - - sampler cal - (OFFSET, MASK, VALUE) (0XFD40189C, 0x00000080U ,0x00000080U) - RegMask = (SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_TM_MISC2_OFFSET ,0x00000080U ,0x00000080U); - /*############################################################################################################################ */ - - /*Register : L0_TM_IQ_ILL1 @ 0XFD4018F8

- - IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS - PSU_SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0 0x64 - - iqpi cal code - (OFFSET, MASK, VALUE) (0XFD4018F8, 0x000000FFU ,0x00000064U) - RegMask = (SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK | 0 ); - - RegVal = ((0x00000064U << SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_TM_IQ_ILL1_OFFSET ,0x000000FFU ,0x00000064U); - /*############################################################################################################################ */ - - /*Register : L0_TM_IQ_ILL2 @ 0XFD4018FC

- - IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 - PSU_SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1 0x64 - - iqpi cal code - (OFFSET, MASK, VALUE) (0XFD4018FC, 0x000000FFU ,0x00000064U) - RegMask = (SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK | 0 ); - - RegVal = ((0x00000064U << SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_TM_IQ_ILL2_OFFSET ,0x000000FFU ,0x00000064U); - /*############################################################################################################################ */ - - /*Register : L0_TM_ILL12 @ 0XFD401990

- - G1A pll ctr bypass value - PSU_SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL 0x11 - - ill pll counter values - (OFFSET, MASK, VALUE) (0XFD401990, 0x000000FFU ,0x00000011U) - RegMask = (SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK | 0 ); - - RegVal = ((0x00000011U << SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_TM_ILL12_OFFSET ,0x000000FFU ,0x00000011U); - /*############################################################################################################################ */ - - /*Register : L0_TM_E_ILL1 @ 0XFD401924

- - E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS - PSU_SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0 0x4 - - epi cal code - (OFFSET, MASK, VALUE) (0XFD401924, 0x000000FFU ,0x00000004U) - RegMask = (SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK | 0 ); - - RegVal = ((0x00000004U << SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_TM_E_ILL1_OFFSET ,0x000000FFU ,0x00000004U); - /*############################################################################################################################ */ - - /*Register : L0_TM_E_ILL2 @ 0XFD401928

- - E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 - PSU_SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1 0xFE - - epi cal code - (OFFSET, MASK, VALUE) (0XFD401928, 0x000000FFU ,0x000000FEU) - RegMask = (SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK | 0 ); - - RegVal = ((0x000000FEU << SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_TM_E_ILL2_OFFSET ,0x000000FFU ,0x000000FEU); - /*############################################################################################################################ */ - - /*Register : L0_TM_IQ_ILL3 @ 0XFD401900

- - IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 - PSU_SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2 0x64 - - iqpi cal code - (OFFSET, MASK, VALUE) (0XFD401900, 0x000000FFU ,0x00000064U) - RegMask = (SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK | 0 ); - - RegVal = ((0x00000064U << SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_TM_IQ_ILL3_OFFSET ,0x000000FFU ,0x00000064U); - /*############################################################################################################################ */ - - /*Register : L0_TM_E_ILL3 @ 0XFD40192C

- - E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 - PSU_SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2 0x0 - - epi cal code - (OFFSET, MASK, VALUE) (0XFD40192C, 0x000000FFU ,0x00000000U) - RegMask = (SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK | 0 ); - - RegVal = ((0x00000000U << SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_TM_E_ILL3_OFFSET ,0x000000FFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : L0_TM_ILL8 @ 0XFD401980

- - ILL calibration code change wait time - PSU_SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT 0xFF - - ILL cal routine control - (OFFSET, MASK, VALUE) (0XFD401980, 0x000000FFU ,0x000000FFU) - RegMask = (SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_MASK | 0 ); - - RegVal = ((0x000000FFU << SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_TM_ILL8_OFFSET ,0x000000FFU ,0x000000FFU); - /*############################################################################################################################ */ - - /*Register : L0_TM_IQ_ILL8 @ 0XFD401914

- - IQ ILL polytrim bypass value - PSU_SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL 0xF7 - - iqpi polytrim - (OFFSET, MASK, VALUE) (0XFD401914, 0x000000FFU ,0x000000F7U) - RegMask = (SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK | 0 ); - - RegVal = ((0x000000F7U << SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_TM_IQ_ILL8_OFFSET ,0x000000FFU ,0x000000F7U); - /*############################################################################################################################ */ - - /*Register : L0_TM_IQ_ILL9 @ 0XFD401918

- - bypass IQ polytrim - PSU_SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM 0x1 - - enables for lf,constant gm trim and polytirm - (OFFSET, MASK, VALUE) (0XFD401918, 0x00000001U ,0x00000001U) - RegMask = (SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_TM_IQ_ILL9_OFFSET ,0x00000001U ,0x00000001U); - /*############################################################################################################################ */ - - /*Register : L0_TM_E_ILL8 @ 0XFD401940

- - E ILL polytrim bypass value - PSU_SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL 0xF7 - - epi polytrim - (OFFSET, MASK, VALUE) (0XFD401940, 0x000000FFU ,0x000000F7U) - RegMask = (SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK | 0 ); - - RegVal = ((0x000000F7U << SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_TM_E_ILL8_OFFSET ,0x000000FFU ,0x000000F7U); - /*############################################################################################################################ */ - - /*Register : L0_TM_E_ILL9 @ 0XFD401944

- - bypass E polytrim - PSU_SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM 0x1 - - enables for lf,constant gm trim and polytirm - (OFFSET, MASK, VALUE) (0XFD401944, 0x00000001U ,0x00000001U) - RegMask = (SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_TM_E_ILL9_OFFSET ,0x00000001U ,0x00000001U); - /*############################################################################################################################ */ - - /*Register : L2_TM_MISC2 @ 0XFD40989C

- - ILL calib counts BYPASSED with calcode bits - PSU_SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS 0x1 - - sampler cal - (OFFSET, MASK, VALUE) (0XFD40989C, 0x00000080U ,0x00000080U) - RegMask = (SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_TM_MISC2_OFFSET ,0x00000080U ,0x00000080U); - /*############################################################################################################################ */ - - /*Register : L2_TM_IQ_ILL1 @ 0XFD4098F8

- - IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS - PSU_SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0 0x1A - - iqpi cal code - (OFFSET, MASK, VALUE) (0XFD4098F8, 0x000000FFU ,0x0000001AU) - RegMask = (SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK | 0 ); - - RegVal = ((0x0000001AU << SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_TM_IQ_ILL1_OFFSET ,0x000000FFU ,0x0000001AU); - /*############################################################################################################################ */ - - /*Register : L2_TM_IQ_ILL2 @ 0XFD4098FC

- - IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 - PSU_SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1 0x1A - - iqpi cal code - (OFFSET, MASK, VALUE) (0XFD4098FC, 0x000000FFU ,0x0000001AU) - RegMask = (SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK | 0 ); - - RegVal = ((0x0000001AU << SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_TM_IQ_ILL2_OFFSET ,0x000000FFU ,0x0000001AU); - /*############################################################################################################################ */ - - /*Register : L2_TM_ILL12 @ 0XFD409990

- - G1A pll ctr bypass value - PSU_SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL 0x10 - - ill pll counter values - (OFFSET, MASK, VALUE) (0XFD409990, 0x000000FFU ,0x00000010U) - RegMask = (SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK | 0 ); - - RegVal = ((0x00000010U << SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_TM_ILL12_OFFSET ,0x000000FFU ,0x00000010U); - /*############################################################################################################################ */ - - /*Register : L2_TM_E_ILL1 @ 0XFD409924

- - E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS - PSU_SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0 0xFE - - epi cal code - (OFFSET, MASK, VALUE) (0XFD409924, 0x000000FFU ,0x000000FEU) - RegMask = (SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK | 0 ); - - RegVal = ((0x000000FEU << SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_TM_E_ILL1_OFFSET ,0x000000FFU ,0x000000FEU); - /*############################################################################################################################ */ - - /*Register : L2_TM_E_ILL2 @ 0XFD409928

- - E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 - PSU_SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1 0x0 - - epi cal code - (OFFSET, MASK, VALUE) (0XFD409928, 0x000000FFU ,0x00000000U) - RegMask = (SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK | 0 ); - - RegVal = ((0x00000000U << SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_TM_E_ILL2_OFFSET ,0x000000FFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : L2_TM_IQ_ILL3 @ 0XFD409900

- - IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 - PSU_SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2 0x1A - - iqpi cal code - (OFFSET, MASK, VALUE) (0XFD409900, 0x000000FFU ,0x0000001AU) - RegMask = (SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK | 0 ); - - RegVal = ((0x0000001AU << SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_TM_IQ_ILL3_OFFSET ,0x000000FFU ,0x0000001AU); - /*############################################################################################################################ */ - - /*Register : L2_TM_E_ILL3 @ 0XFD40992C

- - E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 - PSU_SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2 0x0 - - epi cal code - (OFFSET, MASK, VALUE) (0XFD40992C, 0x000000FFU ,0x00000000U) - RegMask = (SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK | 0 ); - - RegVal = ((0x00000000U << SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_TM_E_ILL3_OFFSET ,0x000000FFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : L2_TM_ILL8 @ 0XFD409980

- - ILL calibration code change wait time - PSU_SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT 0xFF - - ILL cal routine control - (OFFSET, MASK, VALUE) (0XFD409980, 0x000000FFU ,0x000000FFU) - RegMask = (SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_MASK | 0 ); - - RegVal = ((0x000000FFU << SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_TM_ILL8_OFFSET ,0x000000FFU ,0x000000FFU); - /*############################################################################################################################ */ - - /*Register : L2_TM_IQ_ILL8 @ 0XFD409914

- - IQ ILL polytrim bypass value - PSU_SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL 0xF7 - - iqpi polytrim - (OFFSET, MASK, VALUE) (0XFD409914, 0x000000FFU ,0x000000F7U) - RegMask = (SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK | 0 ); - - RegVal = ((0x000000F7U << SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_TM_IQ_ILL8_OFFSET ,0x000000FFU ,0x000000F7U); - /*############################################################################################################################ */ - - /*Register : L2_TM_IQ_ILL9 @ 0XFD409918

- - bypass IQ polytrim - PSU_SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM 0x1 - - enables for lf,constant gm trim and polytirm - (OFFSET, MASK, VALUE) (0XFD409918, 0x00000001U ,0x00000001U) - RegMask = (SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_TM_IQ_ILL9_OFFSET ,0x00000001U ,0x00000001U); - /*############################################################################################################################ */ - - /*Register : L2_TM_E_ILL8 @ 0XFD409940

- - E ILL polytrim bypass value - PSU_SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL 0xF7 - - epi polytrim - (OFFSET, MASK, VALUE) (0XFD409940, 0x000000FFU ,0x000000F7U) - RegMask = (SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK | 0 ); - - RegVal = ((0x000000F7U << SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_TM_E_ILL8_OFFSET ,0x000000FFU ,0x000000F7U); - /*############################################################################################################################ */ - - /*Register : L2_TM_E_ILL9 @ 0XFD409944

- - bypass E polytrim - PSU_SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM 0x1 - - enables for lf,constant gm trim and polytirm - (OFFSET, MASK, VALUE) (0XFD409944, 0x00000001U ,0x00000001U) - RegMask = (SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_TM_E_ILL9_OFFSET ,0x00000001U ,0x00000001U); - /*############################################################################################################################ */ - - /*Register : L3_TM_MISC2 @ 0XFD40D89C

- - ILL calib counts BYPASSED with calcode bits - PSU_SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS 0x1 - - sampler cal - (OFFSET, MASK, VALUE) (0XFD40D89C, 0x00000080U ,0x00000080U) - RegMask = (SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_MISC2_OFFSET ,0x00000080U ,0x00000080U); - /*############################################################################################################################ */ - - /*Register : L3_TM_IQ_ILL1 @ 0XFD40D8F8

- - IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS - PSU_SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0 0x7D - - iqpi cal code - (OFFSET, MASK, VALUE) (0XFD40D8F8, 0x000000FFU ,0x0000007DU) - RegMask = (SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK | 0 ); - - RegVal = ((0x0000007DU << SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_IQ_ILL1_OFFSET ,0x000000FFU ,0x0000007DU); - /*############################################################################################################################ */ - - /*Register : L3_TM_IQ_ILL2 @ 0XFD40D8FC

- - IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 - PSU_SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1 0x7D - - iqpi cal code - (OFFSET, MASK, VALUE) (0XFD40D8FC, 0x000000FFU ,0x0000007DU) - RegMask = (SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK | 0 ); - - RegVal = ((0x0000007DU << SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_IQ_ILL2_OFFSET ,0x000000FFU ,0x0000007DU); - /*############################################################################################################################ */ - - /*Register : L3_TM_ILL12 @ 0XFD40D990

- - G1A pll ctr bypass value - PSU_SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL 0x1 - - ill pll counter values - (OFFSET, MASK, VALUE) (0XFD40D990, 0x000000FFU ,0x00000001U) - RegMask = (SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_ILL12_OFFSET ,0x000000FFU ,0x00000001U); - /*############################################################################################################################ */ - - /*Register : L3_TM_E_ILL1 @ 0XFD40D924

- - E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS - PSU_SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0 0x9C - - epi cal code - (OFFSET, MASK, VALUE) (0XFD40D924, 0x000000FFU ,0x0000009CU) - RegMask = (SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK | 0 ); - - RegVal = ((0x0000009CU << SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_E_ILL1_OFFSET ,0x000000FFU ,0x0000009CU); - /*############################################################################################################################ */ - - /*Register : L3_TM_E_ILL2 @ 0XFD40D928

- - E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 - PSU_SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1 0x39 - - epi cal code - (OFFSET, MASK, VALUE) (0XFD40D928, 0x000000FFU ,0x00000039U) - RegMask = (SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK | 0 ); - - RegVal = ((0x00000039U << SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_E_ILL2_OFFSET ,0x000000FFU ,0x00000039U); - /*############################################################################################################################ */ - - /*Register : L3_TM_ILL11 @ 0XFD40D98C

- - G2A_PCIe1 PLL ctr bypass value - PSU_SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL 0x2 - - ill pll counter values - (OFFSET, MASK, VALUE) (0XFD40D98C, 0x000000F0U ,0x00000020U) - RegMask = (SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_MASK | 0 ); - - RegVal = ((0x00000002U << SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_ILL11_OFFSET ,0x000000F0U ,0x00000020U); - /*############################################################################################################################ */ - - /*Register : L3_TM_IQ_ILL3 @ 0XFD40D900

- - IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 - PSU_SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2 0x7D - - iqpi cal code - (OFFSET, MASK, VALUE) (0XFD40D900, 0x000000FFU ,0x0000007DU) - RegMask = (SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK | 0 ); - - RegVal = ((0x0000007DU << SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_IQ_ILL3_OFFSET ,0x000000FFU ,0x0000007DU); - /*############################################################################################################################ */ - - /*Register : L3_TM_E_ILL3 @ 0XFD40D92C

- - E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 - PSU_SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2 0x64 - - epi cal code - (OFFSET, MASK, VALUE) (0XFD40D92C, 0x000000FFU ,0x00000064U) - RegMask = (SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK | 0 ); - - RegVal = ((0x00000064U << SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_E_ILL3_OFFSET ,0x000000FFU ,0x00000064U); - /*############################################################################################################################ */ - - /*Register : L3_TM_ILL8 @ 0XFD40D980

- - ILL calibration code change wait time - PSU_SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT 0xFF - - ILL cal routine control - (OFFSET, MASK, VALUE) (0XFD40D980, 0x000000FFU ,0x000000FFU) - RegMask = (SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_MASK | 0 ); - - RegVal = ((0x000000FFU << SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_ILL8_OFFSET ,0x000000FFU ,0x000000FFU); - /*############################################################################################################################ */ - - /*Register : L3_TM_IQ_ILL8 @ 0XFD40D914

- - IQ ILL polytrim bypass value - PSU_SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL 0xF7 - - iqpi polytrim - (OFFSET, MASK, VALUE) (0XFD40D914, 0x000000FFU ,0x000000F7U) - RegMask = (SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK | 0 ); - - RegVal = ((0x000000F7U << SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_IQ_ILL8_OFFSET ,0x000000FFU ,0x000000F7U); - /*############################################################################################################################ */ - - /*Register : L3_TM_IQ_ILL9 @ 0XFD40D918

- - bypass IQ polytrim - PSU_SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM 0x1 - - enables for lf,constant gm trim and polytirm - (OFFSET, MASK, VALUE) (0XFD40D918, 0x00000001U ,0x00000001U) - RegMask = (SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_IQ_ILL9_OFFSET ,0x00000001U ,0x00000001U); - /*############################################################################################################################ */ - - /*Register : L3_TM_E_ILL8 @ 0XFD40D940

- - E ILL polytrim bypass value - PSU_SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL 0xF7 - - epi polytrim - (OFFSET, MASK, VALUE) (0XFD40D940, 0x000000FFU ,0x000000F7U) - RegMask = (SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK | 0 ); - - RegVal = ((0x000000F7U << SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_E_ILL8_OFFSET ,0x000000FFU ,0x000000F7U); - /*############################################################################################################################ */ - - /*Register : L3_TM_E_ILL9 @ 0XFD40D944

- - bypass E polytrim - PSU_SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM 0x1 - - enables for lf,constant gm trim and polytirm - (OFFSET, MASK, VALUE) (0XFD40D944, 0x00000001U ,0x00000001U) - RegMask = (SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_E_ILL9_OFFSET ,0x00000001U ,0x00000001U); - /*############################################################################################################################ */ - - // : SYMBOL LOCK AND WAIT - /*Register : L0_TM_DIG_21 @ 0XFD4010A8

- - pre lock comma count threshold. 2'b 00 : 3, 2'b 01 : 5, 2'b 10 : 10, 2'b 11 : 20 - PSU_SERDES_L0_TM_DIG_21_COMMA_PRE_LOCK_THRESH 0x11 - - Control symbol alignment locking - wait counts - (OFFSET, MASK, VALUE) (0XFD4010A8, 0x00000003U ,0x00000003U) - RegMask = (SERDES_L0_TM_DIG_21_COMMA_PRE_LOCK_THRESH_MASK | 0 ); - - RegVal = ((0x00000011U << SERDES_L0_TM_DIG_21_COMMA_PRE_LOCK_THRESH_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_TM_DIG_21_OFFSET ,0x00000003U ,0x00000003U); - /*############################################################################################################################ */ - - /*Register : L0_TM_DIG_10 @ 0XFD40107C

- - CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001 - PSU_SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME 0xF - - test control for changing cdr lock wait time - (OFFSET, MASK, VALUE) (0XFD40107C, 0x0000000FU ,0x0000000FU) - RegMask = (SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK | 0 ); - - RegVal = ((0x0000000FU << SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_TM_DIG_10_OFFSET ,0x0000000FU ,0x0000000FU); - /*############################################################################################################################ */ - - // : SIOU SETTINGS FOR BYPASS CONTROL,HSRX-DIG - /*Register : L0_TM_RST_DLY @ 0XFD4019A4

- - Delay apb reset by specified amount - PSU_SERDES_L0_TM_RST_DLY_APB_RST_DLY 0xFF - - reset delay for apb reset w.r.t pso of hsrx - (OFFSET, MASK, VALUE) (0XFD4019A4, 0x000000FFU ,0x000000FFU) - RegMask = (SERDES_L0_TM_RST_DLY_APB_RST_DLY_MASK | 0 ); - - RegVal = ((0x000000FFU << SERDES_L0_TM_RST_DLY_APB_RST_DLY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_TM_RST_DLY_OFFSET ,0x000000FFU ,0x000000FFU); - /*############################################################################################################################ */ - - /*Register : L0_TM_ANA_BYP_15 @ 0XFD401038

- - Enable Bypass for <7> of TM_ANA_BYPS_15 - PSU_SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE 0x1 - - Bypass control for pcs-pma interface. EQ supplies, main master supply and ps for samp c2c - (OFFSET, MASK, VALUE) (0XFD401038, 0x00000040U ,0x00000040U) - RegMask = (SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_TM_ANA_BYP_15_OFFSET ,0x00000040U ,0x00000040U); - /*############################################################################################################################ */ - - /*Register : L0_TM_ANA_BYP_12 @ 0XFD40102C

- - Enable Bypass for <7> of TM_ANA_BYPS_12 - PSU_SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG 0x1 - - Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr enable controls - (OFFSET, MASK, VALUE) (0XFD40102C, 0x00000040U ,0x00000040U) - RegMask = (SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L0_TM_ANA_BYP_12_OFFSET ,0x00000040U ,0x00000040U); - /*############################################################################################################################ */ - - /*Register : L1_TM_RST_DLY @ 0XFD4059A4

- - Delay apb reset by specified amount - PSU_SERDES_L1_TM_RST_DLY_APB_RST_DLY 0xFF - - reset delay for apb reset w.r.t pso of hsrx - (OFFSET, MASK, VALUE) (0XFD4059A4, 0x000000FFU ,0x000000FFU) - RegMask = (SERDES_L1_TM_RST_DLY_APB_RST_DLY_MASK | 0 ); - - RegVal = ((0x000000FFU << SERDES_L1_TM_RST_DLY_APB_RST_DLY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L1_TM_RST_DLY_OFFSET ,0x000000FFU ,0x000000FFU); - /*############################################################################################################################ */ - - /*Register : L1_TM_ANA_BYP_15 @ 0XFD405038

- - Enable Bypass for <7> of TM_ANA_BYPS_15 - PSU_SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE 0x1 - - Bypass control for pcs-pma interface. EQ supplies, main master supply and ps for samp c2c - (OFFSET, MASK, VALUE) (0XFD405038, 0x00000040U ,0x00000040U) - RegMask = (SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L1_TM_ANA_BYP_15_OFFSET ,0x00000040U ,0x00000040U); - /*############################################################################################################################ */ - - /*Register : L1_TM_ANA_BYP_12 @ 0XFD40502C

- - Enable Bypass for <7> of TM_ANA_BYPS_12 - PSU_SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG 0x1 - - Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr enable controls - (OFFSET, MASK, VALUE) (0XFD40502C, 0x00000040U ,0x00000040U) - RegMask = (SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L1_TM_ANA_BYP_12_OFFSET ,0x00000040U ,0x00000040U); - /*############################################################################################################################ */ - - /*Register : L2_TM_RST_DLY @ 0XFD4099A4

- - Delay apb reset by specified amount - PSU_SERDES_L2_TM_RST_DLY_APB_RST_DLY 0xFF - - reset delay for apb reset w.r.t pso of hsrx - (OFFSET, MASK, VALUE) (0XFD4099A4, 0x000000FFU ,0x000000FFU) - RegMask = (SERDES_L2_TM_RST_DLY_APB_RST_DLY_MASK | 0 ); - - RegVal = ((0x000000FFU << SERDES_L2_TM_RST_DLY_APB_RST_DLY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_TM_RST_DLY_OFFSET ,0x000000FFU ,0x000000FFU); - /*############################################################################################################################ */ - - /*Register : L2_TM_ANA_BYP_15 @ 0XFD409038

- - Enable Bypass for <7> of TM_ANA_BYPS_15 - PSU_SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE 0x1 - - Bypass control for pcs-pma interface. EQ supplies, main master supply and ps for samp c2c - (OFFSET, MASK, VALUE) (0XFD409038, 0x00000040U ,0x00000040U) - RegMask = (SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_TM_ANA_BYP_15_OFFSET ,0x00000040U ,0x00000040U); - /*############################################################################################################################ */ - - /*Register : L2_TM_ANA_BYP_12 @ 0XFD40902C

- - Enable Bypass for <7> of TM_ANA_BYPS_12 - PSU_SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG 0x1 - - Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr enable controls - (OFFSET, MASK, VALUE) (0XFD40902C, 0x00000040U ,0x00000040U) - RegMask = (SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L2_TM_ANA_BYP_12_OFFSET ,0x00000040U ,0x00000040U); - /*############################################################################################################################ */ - - /*Register : L3_TM_RST_DLY @ 0XFD40D9A4

- - Delay apb reset by specified amount - PSU_SERDES_L3_TM_RST_DLY_APB_RST_DLY 0xFF - - reset delay for apb reset w.r.t pso of hsrx - (OFFSET, MASK, VALUE) (0XFD40D9A4, 0x000000FFU ,0x000000FFU) - RegMask = (SERDES_L3_TM_RST_DLY_APB_RST_DLY_MASK | 0 ); - - RegVal = ((0x000000FFU << SERDES_L3_TM_RST_DLY_APB_RST_DLY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_RST_DLY_OFFSET ,0x000000FFU ,0x000000FFU); - /*############################################################################################################################ */ - - /*Register : L3_TM_ANA_BYP_15 @ 0XFD40D038

- - Enable Bypass for <7> of TM_ANA_BYPS_15 - PSU_SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE 0x1 - - Bypass control for pcs-pma interface. EQ supplies, main master supply and ps for samp c2c - (OFFSET, MASK, VALUE) (0XFD40D038, 0x00000040U ,0x00000040U) - RegMask = (SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_ANA_BYP_15_OFFSET ,0x00000040U ,0x00000040U); - /*############################################################################################################################ */ - - /*Register : L3_TM_ANA_BYP_12 @ 0XFD40D02C

- - Enable Bypass for <7> of TM_ANA_BYPS_12 - PSU_SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG 0x1 - - Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr enable controls - (OFFSET, MASK, VALUE) (0XFD40D02C, 0x00000040U ,0x00000040U) - RegMask = (SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_ANA_BYP_12_OFFSET ,0x00000040U ,0x00000040U); - /*############################################################################################################################ */ - - // : GT LANE SETTINGS - /*Register : ICM_CFG0 @ 0XFD410010

- - Controls UPHY Lane 0 protocol configuration. 0 - PowerDown, 1 - PCIe .0, 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII0, 6 - Unuse - , 7 - Unused - PSU_SERDES_ICM_CFG0_L0_ICM_CFG 1 - - Controls UPHY Lane 1 protocol configuration. 0 - PowerDown, 1 - PCIe.1, 2 - Sata1, 3 - USB0, 4 - DP.0, 5 - SGMII1, 6 - Unused - 7 - Unused - PSU_SERDES_ICM_CFG0_L1_ICM_CFG 4 - - ICM Configuration Register 0 - (OFFSET, MASK, VALUE) (0XFD410010, 0x00000077U ,0x00000041U) - RegMask = (SERDES_ICM_CFG0_L0_ICM_CFG_MASK | SERDES_ICM_CFG0_L1_ICM_CFG_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_ICM_CFG0_L0_ICM_CFG_SHIFT - | 0x00000004U << SERDES_ICM_CFG0_L1_ICM_CFG_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_ICM_CFG0_OFFSET ,0x00000077U ,0x00000041U); - /*############################################################################################################################ */ - - /*Register : ICM_CFG1 @ 0XFD410014

- - Controls UPHY Lane 2 protocol configuration. 0 - PowerDown, 1 - PCIe.1, 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII2, 6 - Unused - 7 - Unused - PSU_SERDES_ICM_CFG1_L2_ICM_CFG 3 - - Controls UPHY Lane 3 protocol configuration. 0 - PowerDown, 1 - PCIe.3, 2 - Sata1, 3 - USB1, 4 - DP.0, 5 - SGMII3, 6 - Unused - 7 - Unused - PSU_SERDES_ICM_CFG1_L3_ICM_CFG 2 - - ICM Configuration Register 1 - (OFFSET, MASK, VALUE) (0XFD410014, 0x00000077U ,0x00000023U) - RegMask = (SERDES_ICM_CFG1_L2_ICM_CFG_MASK | SERDES_ICM_CFG1_L3_ICM_CFG_MASK | 0 ); - - RegVal = ((0x00000003U << SERDES_ICM_CFG1_L2_ICM_CFG_SHIFT - | 0x00000002U << SERDES_ICM_CFG1_L3_ICM_CFG_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_ICM_CFG1_OFFSET ,0x00000077U ,0x00000023U); - /*############################################################################################################################ */ - - // : CHECKING PLL LOCK - // : ENABLE SERIAL DATA MUX DEEMPH - /*Register : L1_TXPMD_TM_45 @ 0XFD404CB4

- - Enable/disable DP post2 path - PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH 0x1 - - Override enable/disable of DP post2 path - PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH 0x1 - - Override enable/disable of DP post1 path - PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH 0x1 - - Enable/disable DP main path - PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH 0x1 - - Override enable/disable of DP main path - PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH 0x1 - - Post or pre or main DP path selection - (OFFSET, MASK, VALUE) (0XFD404CB4, 0x00000037U ,0x00000037U) - RegMask = (SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_MASK | SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_MASK | SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_MASK | SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_MASK | SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_SHIFT - | 0x00000001U << SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_SHIFT - | 0x00000001U << SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_SHIFT - | 0x00000001U << SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_SHIFT - | 0x00000001U << SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L1_TXPMD_TM_45_OFFSET ,0x00000037U ,0x00000037U); - /*############################################################################################################################ */ - - /*Register : L1_TX_ANA_TM_118 @ 0XFD4041D8

- - Test register force for enabling/disablign TX deemphasis bits <17:0> - PSU_SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0 0x1 - - Enable Override of TX deemphasis - (OFFSET, MASK, VALUE) (0XFD4041D8, 0x00000001U ,0x00000001U) - RegMask = (SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L1_TX_ANA_TM_118_OFFSET ,0x00000001U ,0x00000001U); - /*############################################################################################################################ */ - - /*Register : L3_TX_ANA_TM_118 @ 0XFD40C1D8

- - Test register force for enabling/disablign TX deemphasis bits <17:0> - PSU_SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0 0x1 - - Enable Override of TX deemphasis - (OFFSET, MASK, VALUE) (0XFD40C1D8, 0x00000001U ,0x00000001U) - RegMask = (SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TX_ANA_TM_118_OFFSET ,0x00000001U ,0x00000001U); - /*############################################################################################################################ */ - - // : CDR AND RX EQUALIZATION SETTINGS - /*Register : L3_TM_CDR5 @ 0XFD40DC14

- - FPHL FSM accumulate cycles - PSU_SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES 0x7 - - FFL Phase0 int gain aka 2ol SD update rate - PSU_SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN 0x6 - - Fast phase lock controls -- FSM accumulator cycle control and phase 0 int gain control. - (OFFSET, MASK, VALUE) (0XFD40DC14, 0x000000FFU ,0x000000E6U) - RegMask = (SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_MASK | SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_MASK | 0 ); - - RegVal = ((0x00000007U << SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_SHIFT - | 0x00000006U << SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_CDR5_OFFSET ,0x000000FFU ,0x000000E6U); - /*############################################################################################################################ */ - - /*Register : L3_TM_CDR16 @ 0XFD40DC40

- - FFL Phase0 prop gain aka 1ol SD update rate - PSU_SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN 0xC - - Fast phase lock controls -- phase 0 prop gain - (OFFSET, MASK, VALUE) (0XFD40DC40, 0x0000001FU ,0x0000000CU) - RegMask = (SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_MASK | 0 ); - - RegVal = ((0x0000000CU << SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_CDR16_OFFSET ,0x0000001FU ,0x0000000CU); - /*############################################################################################################################ */ - - /*Register : L3_TM_EQ0 @ 0XFD40D94C

- - EQ stg 2 controls BYPASSED - PSU_SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP 1 - - eq stg1 and stg2 controls - (OFFSET, MASK, VALUE) (0XFD40D94C, 0x00000020U ,0x00000020U) - RegMask = (SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_EQ0_OFFSET ,0x00000020U ,0x00000020U); - /*############################################################################################################################ */ - - /*Register : L3_TM_EQ1 @ 0XFD40D950

- - EQ STG2 RL PROG - PSU_SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG 0x2 - - EQ stg 2 preamp mode val - PSU_SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL 0x1 - - eq stg1 and stg2 controls - (OFFSET, MASK, VALUE) (0XFD40D950, 0x00000007U ,0x00000006U) - RegMask = (SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_MASK | SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_MASK | 0 ); - - RegVal = ((0x00000002U << SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_SHIFT - | 0x00000001U << SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TM_EQ1_OFFSET ,0x00000007U ,0x00000006U); - /*############################################################################################################################ */ - - // : GEM SERDES SETTINGS - // : ENABLE PRE EMPHAIS AND VOLTAGE SWING - /*Register : L1_TXPMD_TM_48 @ 0XFD404CC0

- - Margining factor value - PSU_SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR 0 - - Margining factor - (OFFSET, MASK, VALUE) (0XFD404CC0, 0x0000001FU ,0x00000000U) - RegMask = (SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_MASK | 0 ); - - RegVal = ((0x00000000U << SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L1_TXPMD_TM_48_OFFSET ,0x0000001FU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : L1_TX_ANA_TM_18 @ 0XFD404048

- - pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-emphasis, Others: reserved - PSU_SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0 0 - - Override for PIPE TX de-emphasis - (OFFSET, MASK, VALUE) (0XFD404048, 0x000000FFU ,0x00000000U) - RegMask = (SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK | 0 ); - - RegVal = ((0x00000000U << SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L1_TX_ANA_TM_18_OFFSET ,0x000000FFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : L3_TX_ANA_TM_18 @ 0XFD40C048

- - pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-emphasis, Others: reserved - PSU_SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0 0x1 - - Override for PIPE TX de-emphasis - (OFFSET, MASK, VALUE) (0XFD40C048, 0x000000FFU ,0x00000001U) - RegMask = (SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK | 0 ); - - RegVal = ((0x00000001U << SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SERDES_L3_TX_ANA_TM_18_OFFSET ,0x000000FFU ,0x00000001U); - /*############################################################################################################################ */ - - - return 1; + * TrustZone classification for Ingress Address Translation 7 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_7 1 + + * TrustZone classification for Egress Address Translation 0 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_0 1 + + * TrustZone classification for Egress Address Translation 1 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_1 1 + + * TrustZone classification for Egress Address Translation 2 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_2 1 + + * TrustZone classification for Egress Address Translation 3 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_3 1 + + * TrustZone classification for Egress Address Translation 4 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_4 1 + + * TrustZone classification for Egress Address Translation 5 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_5 1 + + * TrustZone classification for Egress Address Translation 6 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_6 1 + + * TrustZone classification for Egress Address Translation 7 + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_7 1 + + * TrustZone classification for DMA Registers + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_REGS 1 + + * TrustZone classification for MSIx Table + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_TABLE 1 + + * TrustZone classification for MSIx PBA + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_PBA 1 + + * TrustZone classification for ECAM + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_ECAM 1 + + * TrustZone classification for Bridge Common Registers + * PSU_FPD_SLCR_SECURE_SLCR_PCIE_TZ_BRIDGE_REGS 1 + + * PCIe TrustZone settings. This register may only be modified during bootu + * p (while PCIe block is disabled) + * (OFFSET, MASK, VALUE) (0XFD690030, 0x01FFFFFFU ,0x01FFFFFFU) + */ + PSU_Mask_Write(FPD_SLCR_SECURE_SLCR_PCIE_OFFSET, + 0x01FFFFFFU, 0x01FFFFFFU); +/*##################################################################### */ + + /* + * USB TZ + */ + /* + * Register : slcr_usb @ 0XFF4B0034 + + * TrustZone Classification for USB3_0 + * PSU_LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_0 1 + + * TrustZone Classification for USB3_1 + * PSU_LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_1 1 + + * USB3 TrustZone settings + * (OFFSET, MASK, VALUE) (0XFF4B0034, 0x00000003U ,0x00000003U) + */ + PSU_Mask_Write(LPD_SLCR_SECURE_SLCR_USB_OFFSET, + 0x00000003U, 0x00000003U); +/*##################################################################### */ + + /* + * SD TZ + */ + /* + * Register : IOU_AXI_RPRTCN @ 0XFF240004 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD0_AXI_ARPROT 2 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD1_AXI_ARPROT 2 + + * AXI read protection type selection + * (OFFSET, MASK, VALUE) (0XFF240004, 0x003F0000U ,0x00120000U) + */ + PSU_Mask_Write(IOU_SECURE_SLCR_IOU_AXI_RPRTCN_OFFSET, + 0x003F0000U, 0x00120000U); +/*##################################################################### */ + + /* + * Register : IOU_AXI_WPRTCN @ 0XFF240000 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD0_AXI_AWPROT 2 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD1_AXI_AWPROT 2 + + * AXI write protection type selection + * (OFFSET, MASK, VALUE) (0XFF240000, 0x003F0000U ,0x00120000U) + */ + PSU_Mask_Write(IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET, + 0x003F0000U, 0x00120000U); +/*##################################################################### */ + + /* + * GEM TZ + */ + /* + * Register : IOU_AXI_RPRTCN @ 0XFF240004 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM0_AXI_ARPROT 2 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM1_AXI_ARPROT 2 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM2_AXI_ARPROT 2 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM3_AXI_ARPROT 2 + + * AXI read protection type selection + * (OFFSET, MASK, VALUE) (0XFF240004, 0x00000FFFU ,0x00000492U) + */ + PSU_Mask_Write(IOU_SECURE_SLCR_IOU_AXI_RPRTCN_OFFSET, + 0x00000FFFU, 0x00000492U); +/*##################################################################### */ + + /* + * Register : IOU_AXI_WPRTCN @ 0XFF240000 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM0_AXI_AWPROT 2 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM1_AXI_AWPROT 2 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM2_AXI_AWPROT 2 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM3_AXI_AWPROT 2 + + * AXI write protection type selection + * (OFFSET, MASK, VALUE) (0XFF240000, 0x00000FFFU ,0x00000492U) + */ + PSU_Mask_Write(IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET, + 0x00000FFFU, 0x00000492U); +/*##################################################################### */ + + /* + * QSPI TZ + */ + /* + * Register : IOU_AXI_WPRTCN @ 0XFF240000 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_QSPI_AXI_AWPROT 2 + + * AXI write protection type selection + * (OFFSET, MASK, VALUE) (0XFF240000, 0x0E000000U ,0x04000000U) + */ + PSU_Mask_Write(IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET, + 0x0E000000U, 0x04000000U); +/*##################################################################### */ + + /* + * NAND TZ + */ + /* + * Register : IOU_AXI_RPRTCN @ 0XFF240004 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_RPRTCN_NAND_AXI_ARPROT 2 + + * AXI read protection type selection + * (OFFSET, MASK, VALUE) (0XFF240004, 0x01C00000U ,0x00800000U) + */ + PSU_Mask_Write(IOU_SECURE_SLCR_IOU_AXI_RPRTCN_OFFSET, + 0x01C00000U, 0x00800000U); +/*##################################################################### */ + + /* + * Register : IOU_AXI_WPRTCN @ 0XFF240000 + + * AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access + * PSU_IOU_SECURE_SLCR_IOU_AXI_WPRTCN_NAND_AXI_AWPROT 2 + + * AXI write protection type selection + * (OFFSET, MASK, VALUE) (0XFF240000, 0x01C00000U ,0x00800000U) + */ + PSU_Mask_Write(IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET, + 0x01C00000U, 0x00800000U); +/*##################################################################### */ + + /* + * DMA TZ + */ + /* + * Register : slcr_adma @ 0XFF4B0024 + + * TrustZone Classification for ADMA + * PSU_LPD_SLCR_SECURE_SLCR_ADMA_TZ 0xFF + + * RPU TrustZone settings + * (OFFSET, MASK, VALUE) (0XFF4B0024, 0x000000FFU ,0x000000FFU) + */ + PSU_Mask_Write(LPD_SLCR_SECURE_SLCR_ADMA_OFFSET, + 0x000000FFU, 0x000000FFU); +/*##################################################################### */ + + /* + * Register : slcr_gdma @ 0XFD690050 + + * TrustZone Classification for GDMA + * PSU_FPD_SLCR_SECURE_SLCR_GDMA_TZ 0xFF + + * GDMA Trustzone Settings + * (OFFSET, MASK, VALUE) (0XFD690050, 0x000000FFU ,0x000000FFU) + */ + PSU_Mask_Write(FPD_SLCR_SECURE_SLCR_GDMA_OFFSET, + 0x000000FFU, 0x000000FFU); +/*##################################################################### */ + + + return 1; } -unsigned long psu_resetout_init_data() { - // : TAKING SERDES PERIPHERAL OUT OF RESET RESET - // : PUTTING USB0 IN RESET - /*Register : RST_LPD_TOP @ 0XFF5E023C

+unsigned long psu_serdes_init_data(void) +{ + /* + * SERDES INITIALIZATION + */ + /* + * GT REFERENCE CLOCK SOURCE SELECTION + */ + /* + * Register : PLL_REF_SEL0 @ 0XFD410000 + + * PLL0 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 1 + * 2MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 24MHz, 0x8 - 26MHz, + * 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE + * - 108MHz, 0xF - 125MHz, 0x10 - 135MHz, 0x11 - 150 MHz. 0x12 to 0x1F - R + * eserved + * PSU_SERDES_PLL_REF_SEL0_PLLREFSEL0 0xD + + * PLL0 Reference Selection Register + * (OFFSET, MASK, VALUE) (0XFD410000, 0x0000001FU ,0x0000000DU) + */ + PSU_Mask_Write(SERDES_PLL_REF_SEL0_OFFSET, 0x0000001FU, 0x0000000DU); +/*##################################################################### */ + + /* + * Register : PLL_REF_SEL1 @ 0XFD410004 + + * PLL1 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 1 + * 2MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 24MHz, 0x8 - 26MHz, + * 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE + * - 108MHz, 0xF - 125MHz, 0x10 - 135MHz, 0x11 - 150 MHz. 0x12 to 0x1F - R + * eserved + * PSU_SERDES_PLL_REF_SEL1_PLLREFSEL1 0x9 + + * PLL1 Reference Selection Register + * (OFFSET, MASK, VALUE) (0XFD410004, 0x0000001FU ,0x00000009U) + */ + PSU_Mask_Write(SERDES_PLL_REF_SEL1_OFFSET, 0x0000001FU, 0x00000009U); +/*##################################################################### */ + + /* + * Register : PLL_REF_SEL2 @ 0XFD410008 + + * PLL2 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 1 + * 2MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 24MHz, 0x8 - 26MHz, + * 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE + * - 108MHz, 0xF - 125MHz, 0x10 - 135MHz, 0x11 - 150 MHz. 0x12 to 0x1F - R + * eserved + * PSU_SERDES_PLL_REF_SEL2_PLLREFSEL2 0x8 + + * PLL2 Reference Selection Register + * (OFFSET, MASK, VALUE) (0XFD410008, 0x0000001FU ,0x00000008U) + */ + PSU_Mask_Write(SERDES_PLL_REF_SEL2_OFFSET, 0x0000001FU, 0x00000008U); +/*##################################################################### */ + + /* + * Register : PLL_REF_SEL3 @ 0XFD41000C + + * PLL3 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 1 + * 2MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 24MHz, 0x8 - 26MHz, + * 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE + * - 108MHz, 0xF - 125MHz, 0x10 - 135MHz, 0x11 - 150 MHz. 0x12 to 0x1F - R + * eserved + * PSU_SERDES_PLL_REF_SEL3_PLLREFSEL3 0xF + + * PLL3 Reference Selection Register + * (OFFSET, MASK, VALUE) (0XFD41000C, 0x0000001FU ,0x0000000FU) + */ + PSU_Mask_Write(SERDES_PLL_REF_SEL3_OFFSET, 0x0000001FU, 0x0000000FU); +/*##################################################################### */ + + /* + * GT REFERENCE CLOCK FREQUENCY SELECTION + */ + /* + * Register : L0_L0_REF_CLK_SEL @ 0XFD402860 + + * Sel of lane 0 ref clock local mux. Set to 1 to select lane 0 slicer outp + * ut. Set to 0 to select lane0 ref clock mux output. + * PSU_SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL 0x1 + + * Lane0 Ref Clock Selection Register + * (OFFSET, MASK, VALUE) (0XFD402860, 0x00000080U ,0x00000080U) + */ + PSU_Mask_Write(SERDES_L0_L0_REF_CLK_SEL_OFFSET, + 0x00000080U, 0x00000080U); +/*##################################################################### */ + + /* + * Register : L0_L1_REF_CLK_SEL @ 0XFD402864 + + * Sel of lane 1 ref clock local mux. Set to 1 to select lane 1 slicer outp + * ut. Set to 0 to select lane1 ref clock mux output. + * PSU_SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL 0x0 + + * Bit 3 of lane 1 ref clock mux one hot sel. Set to 1 to select lane 3 sli + * cer output from ref clock network + * PSU_SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3 0x1 + + * Lane1 Ref Clock Selection Register + * (OFFSET, MASK, VALUE) (0XFD402864, 0x00000088U ,0x00000008U) + */ + PSU_Mask_Write(SERDES_L0_L1_REF_CLK_SEL_OFFSET, + 0x00000088U, 0x00000008U); +/*##################################################################### */ + + /* + * Register : L0_L2_REF_CLK_SEL @ 0XFD402868 + + * Sel of lane 2 ref clock local mux. Set to 1 to select lane 1 slicer outp + * ut. Set to 0 to select lane2 ref clock mux output. + * PSU_SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL 0x1 + + * Lane2 Ref Clock Selection Register + * (OFFSET, MASK, VALUE) (0XFD402868, 0x00000080U ,0x00000080U) + */ + PSU_Mask_Write(SERDES_L0_L2_REF_CLK_SEL_OFFSET, + 0x00000080U, 0x00000080U); +/*##################################################################### */ + + /* + * Register : L0_L3_REF_CLK_SEL @ 0XFD40286C + + * Sel of lane 3 ref clock local mux. Set to 1 to select lane 3 slicer outp + * ut. Set to 0 to select lane3 ref clock mux output. + * PSU_SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL 0x0 + + * Bit 1 of lane 3 ref clock mux one hot sel. Set to 1 to select lane 1 sli + * cer output from ref clock network + * PSU_SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1 0x1 + + * Lane3 Ref Clock Selection Register + * (OFFSET, MASK, VALUE) (0XFD40286C, 0x00000082U ,0x00000002U) + */ + PSU_Mask_Write(SERDES_L0_L3_REF_CLK_SEL_OFFSET, + 0x00000082U, 0x00000002U); +/*##################################################################### */ + + /* + * ENABLE SPREAD SPECTRUM + */ + /* + * Register : L2_TM_PLL_DIG_37 @ 0XFD40A094 + + * Enable/Disable coarse code satureation limiting logic + * PSU_SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION 0x1 + + * Test mode register 37 + * (OFFSET, MASK, VALUE) (0XFD40A094, 0x00000010U ,0x00000010U) + */ + PSU_Mask_Write(SERDES_L2_TM_PLL_DIG_37_OFFSET, + 0x00000010U, 0x00000010U); +/*##################################################################### */ + + /* + * Register : L2_PLL_SS_STEPS_0_LSB @ 0XFD40A368 + + * Spread Spectrum No of Steps [7:0] + * PSU_SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB 0x38 + + * Spread Spectrum No of Steps bits 7:0 + * (OFFSET, MASK, VALUE) (0XFD40A368, 0x000000FFU ,0x00000038U) + */ + PSU_Mask_Write(SERDES_L2_PLL_SS_STEPS_0_LSB_OFFSET, + 0x000000FFU, 0x00000038U); +/*##################################################################### */ + + /* + * Register : L2_PLL_SS_STEPS_1_MSB @ 0XFD40A36C + + * Spread Spectrum No of Steps [10:8] + * PSU_SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB 0x03 + + * Spread Spectrum No of Steps bits 10:8 + * (OFFSET, MASK, VALUE) (0XFD40A36C, 0x00000007U ,0x00000003U) + */ + PSU_Mask_Write(SERDES_L2_PLL_SS_STEPS_1_MSB_OFFSET, + 0x00000007U, 0x00000003U); +/*##################################################################### */ + + /* + * Register : L3_PLL_SS_STEPS_0_LSB @ 0XFD40E368 + + * Spread Spectrum No of Steps [7:0] + * PSU_SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB 0xE0 + + * Spread Spectrum No of Steps bits 7:0 + * (OFFSET, MASK, VALUE) (0XFD40E368, 0x000000FFU ,0x000000E0U) + */ + PSU_Mask_Write(SERDES_L3_PLL_SS_STEPS_0_LSB_OFFSET, + 0x000000FFU, 0x000000E0U); +/*##################################################################### */ + + /* + * Register : L3_PLL_SS_STEPS_1_MSB @ 0XFD40E36C + + * Spread Spectrum No of Steps [10:8] + * PSU_SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB 0x3 + + * Spread Spectrum No of Steps bits 10:8 + * (OFFSET, MASK, VALUE) (0XFD40E36C, 0x00000007U ,0x00000003U) + */ + PSU_Mask_Write(SERDES_L3_PLL_SS_STEPS_1_MSB_OFFSET, + 0x00000007U, 0x00000003U); +/*##################################################################### */ + + /* + * Register : L1_PLL_SS_STEPS_0_LSB @ 0XFD406368 + + * Spread Spectrum No of Steps [7:0] + * PSU_SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB 0x58 + + * Spread Spectrum No of Steps bits 7:0 + * (OFFSET, MASK, VALUE) (0XFD406368, 0x000000FFU ,0x00000058U) + */ + PSU_Mask_Write(SERDES_L1_PLL_SS_STEPS_0_LSB_OFFSET, + 0x000000FFU, 0x00000058U); +/*##################################################################### */ + + /* + * Register : L1_PLL_SS_STEPS_1_MSB @ 0XFD40636C + + * Spread Spectrum No of Steps [10:8] + * PSU_SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB 0x3 + + * Spread Spectrum No of Steps bits 10:8 + * (OFFSET, MASK, VALUE) (0XFD40636C, 0x00000007U ,0x00000003U) + */ + PSU_Mask_Write(SERDES_L1_PLL_SS_STEPS_1_MSB_OFFSET, + 0x00000007U, 0x00000003U); +/*##################################################################### */ + + /* + * Register : L1_PLL_SS_STEP_SIZE_0_LSB @ 0XFD406370 + + * Step Size for Spread Spectrum [7:0] + * PSU_SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB 0x7C + + * Step Size for Spread Spectrum LSB + * (OFFSET, MASK, VALUE) (0XFD406370, 0x000000FFU ,0x0000007CU) + */ + PSU_Mask_Write(SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_OFFSET, + 0x000000FFU, 0x0000007CU); +/*##################################################################### */ + + /* + * Register : L1_PLL_SS_STEP_SIZE_1 @ 0XFD406374 + + * Step Size for Spread Spectrum [15:8] + * PSU_SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1 0x33 + + * Step Size for Spread Spectrum 1 + * (OFFSET, MASK, VALUE) (0XFD406374, 0x000000FFU ,0x00000033U) + */ + PSU_Mask_Write(SERDES_L1_PLL_SS_STEP_SIZE_1_OFFSET, + 0x000000FFU, 0x00000033U); +/*##################################################################### */ + + /* + * Register : L1_PLL_SS_STEP_SIZE_2 @ 0XFD406378 + + * Step Size for Spread Spectrum [23:16] + * PSU_SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2 0x2 + + * Step Size for Spread Spectrum 2 + * (OFFSET, MASK, VALUE) (0XFD406378, 0x000000FFU ,0x00000002U) + */ + PSU_Mask_Write(SERDES_L1_PLL_SS_STEP_SIZE_2_OFFSET, + 0x000000FFU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : L1_PLL_SS_STEP_SIZE_3_MSB @ 0XFD40637C + + * Step Size for Spread Spectrum [25:24] + * PSU_SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB 0x0 + + * Enable/Disable test mode force on SS step size + * PSU_SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE 0x1 + + * Enable/Disable test mode force on SS no of steps + * PSU_SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS 0x1 + + * Enable force on enable Spread Spectrum + * (OFFSET, MASK, VALUE) (0XFD40637C, 0x00000033U ,0x00000030U) + */ + PSU_Mask_Write(SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_OFFSET, + 0x00000033U, 0x00000030U); +/*##################################################################### */ + + /* + * Register : L2_PLL_SS_STEP_SIZE_0_LSB @ 0XFD40A370 + + * Step Size for Spread Spectrum [7:0] + * PSU_SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB 0xF4 + + * Step Size for Spread Spectrum LSB + * (OFFSET, MASK, VALUE) (0XFD40A370, 0x000000FFU ,0x000000F4U) + */ + PSU_Mask_Write(SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_OFFSET, + 0x000000FFU, 0x000000F4U); +/*##################################################################### */ + + /* + * Register : L2_PLL_SS_STEP_SIZE_1 @ 0XFD40A374 + + * Step Size for Spread Spectrum [15:8] + * PSU_SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1 0x31 + + * Step Size for Spread Spectrum 1 + * (OFFSET, MASK, VALUE) (0XFD40A374, 0x000000FFU ,0x00000031U) + */ + PSU_Mask_Write(SERDES_L2_PLL_SS_STEP_SIZE_1_OFFSET, + 0x000000FFU, 0x00000031U); +/*##################################################################### */ + + /* + * Register : L2_PLL_SS_STEP_SIZE_2 @ 0XFD40A378 - USB 0 reset for control registers - PSU_CRL_APB_RST_LPD_TOP_USB0_APB_RESET 0X0 + * Step Size for Spread Spectrum [23:16] + * PSU_SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2 0x2 + + * Step Size for Spread Spectrum 2 + * (OFFSET, MASK, VALUE) (0XFD40A378, 0x000000FFU ,0x00000002U) + */ + PSU_Mask_Write(SERDES_L2_PLL_SS_STEP_SIZE_2_OFFSET, + 0x000000FFU, 0x00000002U); +/*##################################################################### */ + + /* + * Register : L2_PLL_SS_STEP_SIZE_3_MSB @ 0XFD40A37C - Software control register for the LPD block. - (OFFSET, MASK, VALUE) (0XFF5E023C, 0x00000400U ,0x00000000U) - RegMask = (CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK | 0 ); + * Step Size for Spread Spectrum [25:24] + * PSU_SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB 0x0 - RegVal = ((0x00000000U << CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RST_LPD_TOP_OFFSET ,0x00000400U ,0x00000000U); - /*############################################################################################################################ */ + * Enable/Disable test mode force on SS step size + * PSU_SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE 0x1 + + * Enable/Disable test mode force on SS no of steps + * PSU_SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS 0x1 + + * Enable force on enable Spread Spectrum + * (OFFSET, MASK, VALUE) (0XFD40A37C, 0x00000033U ,0x00000030U) + */ + PSU_Mask_Write(SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_OFFSET, + 0x00000033U, 0x00000030U); +/*##################################################################### */ - // : USB0 PIPE POWER PRESENT - /*Register : fpd_power_prsnt @ 0XFF9D0080

+ /* + * Register : L3_PLL_SS_STEP_SIZE_0_LSB @ 0XFD40E370 + + * Step Size for Spread Spectrum [7:0] + * PSU_SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB 0xC9 + + * Step Size for Spread Spectrum LSB + * (OFFSET, MASK, VALUE) (0XFD40E370, 0x000000FFU ,0x000000C9U) + */ + PSU_Mask_Write(SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_OFFSET, + 0x000000FFU, 0x000000C9U); +/*##################################################################### */ - This bit is used to choose between PIPE power present and 1'b1 - PSU_USB3_0_FPD_POWER_PRSNT_OPTION 0X1 + /* + * Register : L3_PLL_SS_STEP_SIZE_1 @ 0XFD40E374 - fpd_power_prsnt - (OFFSET, MASK, VALUE) (0XFF9D0080, 0x00000001U ,0x00000001U) - RegMask = (USB3_0_FPD_POWER_PRSNT_OPTION_MASK | 0 ); + * Step Size for Spread Spectrum [15:8] + * PSU_SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1 0xD2 - RegVal = ((0x00000001U << USB3_0_FPD_POWER_PRSNT_OPTION_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (USB3_0_FPD_POWER_PRSNT_OFFSET ,0x00000001U ,0x00000001U); - /*############################################################################################################################ */ + * Step Size for Spread Spectrum 1 + * (OFFSET, MASK, VALUE) (0XFD40E374, 0x000000FFU ,0x000000D2U) + */ + PSU_Mask_Write(SERDES_L3_PLL_SS_STEP_SIZE_1_OFFSET, + 0x000000FFU, 0x000000D2U); +/*##################################################################### */ - /*Register : fpd_pipe_clk @ 0XFF9D007C

+ /* + * Register : L3_PLL_SS_STEP_SIZE_2 @ 0XFD40E378 - This bit is used to choose between PIPE clock coming from SerDes and the suspend clk - PSU_USB3_0_FPD_PIPE_CLK_OPTION 0x0 + * Step Size for Spread Spectrum [23:16] + * PSU_SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2 0x1 - fpd_pipe_clk - (OFFSET, MASK, VALUE) (0XFF9D007C, 0x00000001U ,0x00000000U) - RegMask = (USB3_0_FPD_PIPE_CLK_OPTION_MASK | 0 ); + * Step Size for Spread Spectrum 2 + * (OFFSET, MASK, VALUE) (0XFD40E378, 0x000000FFU ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L3_PLL_SS_STEP_SIZE_2_OFFSET, + 0x000000FFU, 0x00000001U); +/*##################################################################### */ - RegVal = ((0x00000000U << USB3_0_FPD_PIPE_CLK_OPTION_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (USB3_0_FPD_PIPE_CLK_OFFSET ,0x00000001U ,0x00000000U); - /*############################################################################################################################ */ + /* + * Register : L3_PLL_SS_STEP_SIZE_3_MSB @ 0XFD40E37C - // : - /*Register : RST_LPD_TOP @ 0XFF5E023C

+ * Step Size for Spread Spectrum [25:24] + * PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB 0x0 - USB 0 sleep circuit reset - PSU_CRL_APB_RST_LPD_TOP_USB0_HIBERRESET 0X0 + * Enable/Disable test mode force on SS step size + * PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE 0x1 - USB 0 reset - PSU_CRL_APB_RST_LPD_TOP_USB0_CORERESET 0X0 + * Enable/Disable test mode force on SS no of steps + * PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS 0x1 + + * Enable test mode forcing on enable Spread Spectrum + * PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS 0x1 - Software control register for the LPD block. - (OFFSET, MASK, VALUE) (0XFF5E023C, 0x00000140U ,0x00000000U) - RegMask = (CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK | CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK | 0 ); + * Enable force on enable Spread Spectrum + * (OFFSET, MASK, VALUE) (0XFD40E37C, 0x000000B3U ,0x000000B0U) + */ + PSU_Mask_Write(SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_OFFSET, + 0x000000B3U, 0x000000B0U); +/*##################################################################### */ - RegVal = ((0x00000000U << CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT - | 0x00000000U << CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RST_LPD_TOP_OFFSET ,0x00000140U ,0x00000000U); - /*############################################################################################################################ */ + /* + * Register : L2_TM_DIG_6 @ 0XFD40906C - // : PUTTING GEM0 IN RESET - /*Register : RST_LPD_IOU0 @ 0XFF5E0230

+ * Bypass Descrambler + * PSU_SERDES_L2_TM_DIG_6_BYPASS_DESCRAM 0x1 - GEM 3 reset - PSU_CRL_APB_RST_LPD_IOU0_GEM3_RESET 0X0 + * Enable Bypass for <1> TM_DIG_CTRL_6 + * PSU_SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM 0x1 - Software controlled reset for the GEMs - (OFFSET, MASK, VALUE) (0XFF5E0230, 0x00000008U ,0x00000000U) - RegMask = (CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK | 0 ); + * Data path test modes in decoder and descram + * (OFFSET, MASK, VALUE) (0XFD40906C, 0x00000003U ,0x00000003U) + */ + PSU_Mask_Write(SERDES_L2_TM_DIG_6_OFFSET, 0x00000003U, 0x00000003U); +/*##################################################################### */ + + /* + * Register : L2_TX_DIG_TM_61 @ 0XFD4080F4 - RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RST_LPD_IOU0_OFFSET ,0x00000008U ,0x00000000U); - /*############################################################################################################################ */ + * Bypass scrambler signal + * PSU_SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM 0x1 - // : PUTTING SATA IN RESET - /*Register : sata_misc_ctrl @ 0XFD3D0100

+ * Enable/disable scrambler bypass signal + * PSU_SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM 0x1 + + * MPHY PLL Gear and bypass scrambler + * (OFFSET, MASK, VALUE) (0XFD4080F4, 0x00000003U ,0x00000003U) + */ + PSU_Mask_Write(SERDES_L2_TX_DIG_TM_61_OFFSET, + 0x00000003U, 0x00000003U); +/*##################################################################### */ + + /* + * Register : L3_PLL_FBDIV_FRAC_3_MSB @ 0XFD40E360 + + * Enable test mode force on fractional mode enable + * PSU_SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC 0x1 + + * Fractional feedback division control and fractional value for feedback d + * ivision bits 26:24 + * (OFFSET, MASK, VALUE) (0XFD40E360, 0x00000040U ,0x00000040U) + */ + PSU_Mask_Write(SERDES_L3_PLL_FBDIV_FRAC_3_MSB_OFFSET, + 0x00000040U, 0x00000040U); +/*##################################################################### */ - Sata PM clock control select - PSU_SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL 0x3 + /* + * Register : L3_TM_DIG_6 @ 0XFD40D06C + + * Bypass 8b10b decoder + * PSU_SERDES_L3_TM_DIG_6_BYPASS_DECODER 0x1 - Misc Contorls for SATA.This register may only be modified during bootup (while SATA block is disabled) - (OFFSET, MASK, VALUE) (0XFD3D0100, 0x00000003U ,0x00000003U) - RegMask = (SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_MASK | 0 ); + * Enable Bypass for <3> TM_DIG_CTRL_6 + * PSU_SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC 0x1 - RegVal = ((0x00000003U << SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SIOU_SATA_MISC_CTRL_OFFSET ,0x00000003U ,0x00000003U); - /*############################################################################################################################ */ + * Bypass Descrambler + * PSU_SERDES_L3_TM_DIG_6_BYPASS_DESCRAM 0x1 - /*Register : RST_FPD_TOP @ 0XFD1A0100

+ * Enable Bypass for <1> TM_DIG_CTRL_6 + * PSU_SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM 0x1 + + * Data path test modes in decoder and descram + * (OFFSET, MASK, VALUE) (0XFD40D06C, 0x0000000FU ,0x0000000FU) + */ + PSU_Mask_Write(SERDES_L3_TM_DIG_6_OFFSET, 0x0000000FU, 0x0000000FU); +/*##################################################################### */ + + /* + * Register : L3_TX_DIG_TM_61 @ 0XFD40C0F4 + + * Enable/disable encoder bypass signal + * PSU_SERDES_L3_TX_DIG_TM_61_BYPASS_ENC 0x1 + + * Bypass scrambler signal + * PSU_SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM 0x1 + + * Enable/disable scrambler bypass signal + * PSU_SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM 0x1 - Sata block level reset - PSU_CRF_APB_RST_FPD_TOP_SATA_RESET 0X0 - - FPD Block level software controlled reset - (OFFSET, MASK, VALUE) (0XFD1A0100, 0x00000002U ,0x00000000U) - RegMask = (CRF_APB_RST_FPD_TOP_SATA_RESET_MASK | 0 ); - - RegVal = ((0x00000000U << CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_RST_FPD_TOP_OFFSET ,0x00000002U ,0x00000000U); - /*############################################################################################################################ */ - - // : PUTTING PCIE CFG AND BRIDGE IN RESET - /*Register : RST_FPD_TOP @ 0XFD1A0100

- - PCIE config reset - PSU_CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET 0X0 - - PCIE bridge block level reset (AXI interface) - PSU_CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET 0X0 - - FPD Block level software controlled reset - (OFFSET, MASK, VALUE) (0XFD1A0100, 0x000C0000U ,0x00000000U) - RegMask = (CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK | CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK | 0 ); - - RegVal = ((0x00000000U << CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT - | 0x00000000U << CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_RST_FPD_TOP_OFFSET ,0x000C0000U ,0x00000000U); - /*############################################################################################################################ */ - - // : PUTTING DP IN RESET - /*Register : RST_FPD_TOP @ 0XFD1A0100

- - Display Port block level reset (includes DPDMA) - PSU_CRF_APB_RST_FPD_TOP_DP_RESET 0X0 - - FPD Block level software controlled reset - (OFFSET, MASK, VALUE) (0XFD1A0100, 0x00010000U ,0x00000000U) - RegMask = (CRF_APB_RST_FPD_TOP_DP_RESET_MASK | 0 ); - - RegVal = ((0x00000000U << CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_RST_FPD_TOP_OFFSET ,0x00010000U ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : DP_PHY_RESET @ 0XFD4A0200

- - Set to '1' to hold the GT in reset. Clear to release. - PSU_DP_DP_PHY_RESET_GT_RESET 0X0 - - Reset the transmitter PHY. - (OFFSET, MASK, VALUE) (0XFD4A0200, 0x00000002U ,0x00000000U) - RegMask = (DP_DP_PHY_RESET_GT_RESET_MASK | 0 ); - - RegVal = ((0x00000000U << DP_DP_PHY_RESET_GT_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DP_DP_PHY_RESET_OFFSET ,0x00000002U ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : DP_TX_PHY_POWER_DOWN @ 0XFD4A0238

- - Two bits per lane. When set to 11, moves the GT to power down mode. When set to 00, GT will be in active state. bits [1:0] - - ane0 Bits [3:2] - lane 1 - PSU_DP_DP_TX_PHY_POWER_DOWN_POWER_DWN 0X0 - - Control PHY Power down - (OFFSET, MASK, VALUE) (0XFD4A0238, 0x0000000FU ,0x00000000U) - RegMask = (DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK | 0 ); - - RegVal = ((0x00000000U << DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DP_DP_TX_PHY_POWER_DOWN_OFFSET ,0x0000000FU ,0x00000000U); - /*############################################################################################################################ */ - - // : USB0 GFLADJ - /*Register : GUSB2PHYCFG @ 0XFE20C200

- - USB 2.0 Turnaround Time (USBTrdTim) Sets the turnaround time in PHY clocks. Specifies the response time for a MAC request to - he Packet FIFO Controller (PFC) to fetch data from the DFIFO (SPRAM). The following are the required values for the minimum S - C bus frequency of 60 MHz. USB turnaround time is a critical certification criteria when using long cables and five hub level - . The required values for this field: - 4'h5: When the MAC interface is 16-bit UTMI+. - 4'h9: When the MAC interface is 8-bit - UTMI+/ULPI. If SoC bus clock is less than 60 MHz, and USB turnaround time is not critical, this field can be set to a larger - alue. Note: This field is valid only in device mode. - PSU_USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM 0x9 - - Transceiver Delay: Enables a delay between the assertion of the UTMI/ULPI Transceiver Select signal (for HS) and the assertio - of the TxValid signal during a HS Chirp. When this bit is set to 1, a delay (of approximately 2.5 us) is introduced from the - time when the Transceiver Select is set to 2'b00 (HS) to the time the TxValid is driven to 0 for sending the chirp-K. This de - ay is required for some UTMI/ULPI PHYs. Note: - If you enable the hibernation feature when the device core comes out of power - off, you must re-initialize this bit with the appropriate value because the core does not save and restore this bit value dur - ng hibernation. - This bit is valid only in device mode. - PSU_USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY 0x0 - - Enable utmi_sleep_n and utmi_l1_suspend_n (EnblSlpM) The application uses this bit to control utmi_sleep_n and utmi_l1_suspen - _n assertion to the PHY in the L1 state. - 1'b0: utmi_sleep_n and utmi_l1_suspend_n assertion from the core is not transferre - to the external PHY. - 1'b1: utmi_sleep_n and utmi_l1_suspend_n assertion from the core is transferred to the external PHY. - ote: This bit must be set high for Port0 if PHY is used. Note: In Device mode - Before issuing any device endpoint command wh - n operating in 2.0 speeds, disable this bit and enable it after the command completes. Without disabling this bit, if a comma - d is issued when the device is in L1 state and if mac2_clk (utmi_clk/ulpi_clk) is gated off, the command will not get complet - d. - PSU_USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM 0x0 - - USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial Transceiver Select The application uses this bit to select a high-speed P - Y or a full-speed transceiver. - 1'b0: USB 2.0 high-speed UTMI+ or ULPI PHY. This bit is always 0, with Write Only access. - - 'b1: USB 1.1 full-speed serial transceiver. This bit is always 1, with Write Only access. If both interface types are selecte - in coreConsultant (that is, parameters' values are not zero), the application uses this bit to select the active interface i - active, with Read-Write bit access. Note: USB 1.1 full-serial transceiver is not supported. This bit always reads as 1'b0. - PSU_USB3_0_XHCI_GUSB2PHYCFG_PHYSEL 0x0 - - Full-Speed Serial Interface Select (FSIntf) The application uses this bit to select a unidirectional or bidirectional USB 1.1 - full-speed serial transceiver interface. - 1'b0: 6-pin unidirectional full-speed serial interface. This bit is set to 0 with - ead Only access. - 1'b1: 3-pin bidirectional full-speed serial interface. This bit is set to 0 with Read Only access. Note: U - B 1.1 full-speed serial interface is not supported. This bit always reads as 1'b0. - PSU_USB3_0_XHCI_GUSB2PHYCFG_FSINTF 0x0 - - ULPI or UTMI+ Select (ULPI_UTMI_Sel) The application uses this bit to select a UTMI+ or ULPI Interface. - 1'b0: UTMI+ Interfa - e - 1'b1: ULPI Interface This bit is writable only if UTMI+ and ULPI is specified for High-Speed PHY Interface(s) in coreCons - ltant configuration (DWC_USB3_HSPHY_INTERFACE = 3). Otherwise, this bit is read-only and the value depends on the interface s - lected through DWC_USB3_HSPHY_INTERFACE. - PSU_USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL 0x1 - - PHY Interface (PHYIf) If UTMI+ is selected, the application uses this bit to configure the core to support a UTMI+ PHY with a - 8- or 16-bit interface. - 1'b0: 8 bits - 1'b1: 16 bits ULPI Mode: 1'b0 Note: - All the enabled 2.0 ports must have the same - lock frequency as Port0 clock frequency (utmi_clk[0]). - The UTMI 8-bit and 16-bit modes cannot be used together for differen - ports at the same time (that is, all the ports must be in 8-bit mode, or all of them must be in 16-bit mode, at a time). - I - any of the USB 2.0 ports is selected as ULPI port for operation, then all the USB 2.0 ports must be operating at 60 MHz. - PSU_USB3_0_XHCI_GUSB2PHYCFG_PHYIF 0x0 - - HS/FS Timeout Calibration (TOutCal) The number of PHY clocks, as indicated by the application in this field, is multiplied by - a bit-time factor; this factor is added to the high-speed/full-speed interpacket timeout duration in the core to account for - dditional delays introduced by the PHY. This may be required, since the delay introduced by the PHY in generating the linesta - e condition may vary among PHYs. The USB standard timeout value for high-speed operation is 736 to 816 (inclusive) bit times. - The USB standard timeout value for full-speed operation is 16 to 18 (inclusive) bit times. The application must program this - ield based on the speed of connection. The number of bit times added per PHY clock are: High-speed operation: - One 30-MHz PH - clock = 16 bit times - One 60-MHz PHY clock = 8 bit times Full-speed operation: - One 30-MHz PHY clock = 0.4 bit times - One - 60-MHz PHY clock = 0.2 bit times - One 48-MHz PHY clock = 0.25 bit times - PSU_USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL 0x7 - - Global USB2 PHY Configuration Register The application must program this register before starting any transactions on either - he SoC bus or the USB. In Device-only configurations, only one register is needed. In Host mode, per-port registers are imple - ented. - (OFFSET, MASK, VALUE) (0XFE20C200, 0x00003FBFU ,0x00002417U) - RegMask = (USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_MASK | USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_MASK | USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_MASK | USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_MASK | USB3_0_XHCI_GUSB2PHYCFG_FSINTF_MASK | USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_MASK | USB3_0_XHCI_GUSB2PHYCFG_PHYIF_MASK | USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_MASK | 0 ); - - RegVal = ((0x00000009U << USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_SHIFT - | 0x00000000U << USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_SHIFT - | 0x00000000U << USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_SHIFT - | 0x00000000U << USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_SHIFT - | 0x00000000U << USB3_0_XHCI_GUSB2PHYCFG_FSINTF_SHIFT - | 0x00000001U << USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_SHIFT - | 0x00000000U << USB3_0_XHCI_GUSB2PHYCFG_PHYIF_SHIFT - | 0x00000007U << USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (USB3_0_XHCI_GUSB2PHYCFG_OFFSET ,0x00003FBFU ,0x00002417U); - /*############################################################################################################################ */ - - /*Register : GFLADJ @ 0XFE20C630

- - This field indicates the frame length adjustment to be applied when SOF/ITP counter is running on the ref_clk. This register - alue is used to adjust the ITP interval when GCTL[SOFITPSYNC] is set to '1'; SOF and ITP interval when GLADJ.GFLADJ_REFCLK_LP - _SEL is set to '1'. This field must be programmed to a non-zero value only if GFLADJ_REFCLK_LPM_SEL is set to '1' or GCTL.SOF - TPSYNC is set to '1'. The value is derived as follows: FLADJ_REF_CLK_FLADJ=((125000/ref_clk_period_integer)-(125000/ref_clk_p - riod)) * ref_clk_period where - the ref_clk_period_integer is the integer value of the ref_clk period got by truncating the d - cimal (fractional) value that is programmed in the GUCTL.REF_CLK_PERIOD field. - the ref_clk_period is the ref_clk period inc - uding the fractional value. Examples: If the ref_clk is 24 MHz then - GUCTL.REF_CLK_PERIOD = 41 - GFLADJ.GLADJ_REFCLK_FLADJ = - ((125000/41)-(125000/41.6666))*41.6666 = 2032 (ignoring the fractional value) If the ref_clk is 48 MHz then - GUCTL.REF_CLK_P - RIOD = 20 - GFLADJ.GLADJ_REFCLK_FLADJ = ((125000/20)-(125000/20.8333))*20.8333 = 5208 (ignoring the fractional value) - PSU_USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ 0x0 - - Global Frame Length Adjustment Register This register provides options for the software to control the core behavior with res - ect to SOF (Start of Frame) and ITP (Isochronous Timestamp Packet) timers and frame timer functionality. It provides an optio - to override the fladj_30mhz_reg sideband signal. In addition, it enables running SOF or ITP frame timer counters completely - rom the ref_clk. This facilitates hardware LPM in host mode with the SOF or ITP counters being run from the ref_clk signal. - (OFFSET, MASK, VALUE) (0XFE20C630, 0x003FFF00U ,0x00000000U) - RegMask = (USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_MASK | 0 ); - - RegVal = ((0x00000000U << USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (USB3_0_XHCI_GFLADJ_OFFSET ,0x003FFF00U ,0x00000000U); - /*############################################################################################################################ */ - - // : UPDATING TWO PCIE REGISTERS DEFAULT VALUES, AS THESE REGISTERS HAVE INCORRECT RESET VALUES IN SILICON. - /*Register : ATTR_25 @ 0XFD480064

- - If TRUE Completion Timeout Disable is supported. This is required to be TRUE for Endpoint and either setting allowed for Root - ports. Drives Device Capability 2 [4]; EP=0x0001; RP=0x0001 - PSU_PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED 0X1 - - ATTR_25 - (OFFSET, MASK, VALUE) (0XFD480064, 0x00000200U ,0x00000200U) - RegMask = (PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_MASK | 0 ); - - RegVal = ((0x00000001U << PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_25_OFFSET ,0x00000200U ,0x00000200U); - /*############################################################################################################################ */ - - // : PCIE SETTINGS - /*Register : ATTR_7 @ 0XFD48001C

- - Specifies mask/settings for Base Address Register (BAR) 0. If BAR is not to be implemented, set to 32'h00000000. Bits are def - ned as follows: Memory Space BAR [0] = Mem Space Indicator (set to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = - Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory a - erture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR1,BAR0\'7d to 1. IO Space BAR 0] = IO Space Indicator - set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o apert - re size in bytes.; EP=0x0004; RP=0x0000 - PSU_PCIE_ATTRIB_ATTR_7_ATTR_BAR0 0x0 - - ATTR_7 - (OFFSET, MASK, VALUE) (0XFD48001C, 0x0000FFFFU ,0x00000000U) - RegMask = (PCIE_ATTRIB_ATTR_7_ATTR_BAR0_MASK | 0 ); - - RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_7_ATTR_BAR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_7_OFFSET ,0x0000FFFFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : ATTR_8 @ 0XFD480020

- - Specifies mask/settings for Base Address Register (BAR) 0. If BAR is not to be implemented, set to 32'h00000000. Bits are def - ned as follows: Memory Space BAR [0] = Mem Space Indicator (set to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = - Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory a - erture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR1,BAR0\'7d to 1. IO Space BAR 0] = IO Space Indicator - set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o apert - re size in bytes.; EP=0xFFF0; RP=0x0000 - PSU_PCIE_ATTRIB_ATTR_8_ATTR_BAR0 0x0 - - ATTR_8 - (OFFSET, MASK, VALUE) (0XFD480020, 0x0000FFFFU ,0x00000000U) - RegMask = (PCIE_ATTRIB_ATTR_8_ATTR_BAR0_MASK | 0 ); - - RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_8_ATTR_BAR0_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_8_OFFSET ,0x0000FFFFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : ATTR_9 @ 0XFD480024

- - Specifies mask/settings for Base Address Register (BAR) 1 if BAR0 is a 32-bit BAR, or the upper bits of \'7bBAR1,BAR0\'7d if - AR0 is a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR0 description if this functions as the uppe - bits of a 64-bit BAR. Bits are defined as follows: Memory Space BAR (not upper bits of BAR0) [0] = Mem Space Indicator (set - o 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if - 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of - '7bBAR2,BAR1\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable b - ts of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000 - PSU_PCIE_ATTRIB_ATTR_9_ATTR_BAR1 0x0 - - ATTR_9 - (OFFSET, MASK, VALUE) (0XFD480024, 0x0000FFFFU ,0x00000000U) - RegMask = (PCIE_ATTRIB_ATTR_9_ATTR_BAR1_MASK | 0 ); - - RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_9_ATTR_BAR1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_9_OFFSET ,0x0000FFFFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : ATTR_10 @ 0XFD480028

- - Specifies mask/settings for Base Address Register (BAR) 1 if BAR0 is a 32-bit BAR, or the upper bits of \'7bBAR1,BAR0\'7d if - AR0 is a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR0 description if this functions as the uppe - bits of a 64-bit BAR. Bits are defined as follows: Memory Space BAR (not upper bits of BAR0) [0] = Mem Space Indicator (set - o 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if - 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of - '7bBAR2,BAR1\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable b - ts of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000 - PSU_PCIE_ATTRIB_ATTR_10_ATTR_BAR1 0x0 - - ATTR_10 - (OFFSET, MASK, VALUE) (0XFD480028, 0x0000FFFFU ,0x00000000U) - RegMask = (PCIE_ATTRIB_ATTR_10_ATTR_BAR1_MASK | 0 ); - - RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_10_ATTR_BAR1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_10_OFFSET ,0x0000FFFFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : ATTR_11 @ 0XFD48002C

- - For an endpoint, specifies mask/settings for Base Address Register (BAR) 2 if BAR1 is a 32-bit BAR, or the upper bits of \'7b - AR2,BAR1\'7d if BAR1 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR1 descri - tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to 00FF_FFFF. For an endpoin - , bits are defined as follows: Memory Space BAR (not upper bits of BAR1) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi - ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe - most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR3,BAR2\'7d to - . IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper - ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0x0004; RP=0xFFFF - PSU_PCIE_ATTRIB_ATTR_11_ATTR_BAR2 0xFFFF - - ATTR_11 - (OFFSET, MASK, VALUE) (0XFD48002C, 0x0000FFFFU ,0x0000FFFFU) - RegMask = (PCIE_ATTRIB_ATTR_11_ATTR_BAR2_MASK | 0 ); - - RegVal = ((0x0000FFFFU << PCIE_ATTRIB_ATTR_11_ATTR_BAR2_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_11_OFFSET ,0x0000FFFFU ,0x0000FFFFU); - /*############################################################################################################################ */ - - /*Register : ATTR_12 @ 0XFD480030

- - For an endpoint, specifies mask/settings for Base Address Register (BAR) 2 if BAR1 is a 32-bit BAR, or the upper bits of \'7b - AR2,BAR1\'7d if BAR1 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR1 descri - tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to 00FF_FFFF. For an endpoin - , bits are defined as follows: Memory Space BAR (not upper bits of BAR1) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi - ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe - most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR3,BAR2\'7d to - . IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper - ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFF0; RP=0x00FF - PSU_PCIE_ATTRIB_ATTR_12_ATTR_BAR2 0xFF - - ATTR_12 - (OFFSET, MASK, VALUE) (0XFD480030, 0x0000FFFFU ,0x000000FFU) - RegMask = (PCIE_ATTRIB_ATTR_12_ATTR_BAR2_MASK | 0 ); - - RegVal = ((0x000000FFU << PCIE_ATTRIB_ATTR_12_ATTR_BAR2_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_12_OFFSET ,0x0000FFFFU ,0x000000FFU); - /*############################################################################################################################ */ - - /*Register : ATTR_13 @ 0XFD480034

- - For an endpoint, specifies mask/settings for Base Address Register (BAR) 3 if BAR2 is a 32-bit BAR, or the upper bits of \'7b - AR3,BAR2\'7d if BAR2 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR2 descri - tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: FFFF_0000 = IO Limit/Bas - Registers not implemented FFFF_F0F0 = IO Limit/Base Registers use 16-bit decode FFFF_F1F1 = IO Limit/Base Registers use 32-b - t decode For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of BAR2) [0] = Mem Space Indicator (s - t to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; - if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits - f \'7bBAR4,BAR3\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writabl - bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000 - PSU_PCIE_ATTRIB_ATTR_13_ATTR_BAR3 0x0 - - ATTR_13 - (OFFSET, MASK, VALUE) (0XFD480034, 0x0000FFFFU ,0x00000000U) - RegMask = (PCIE_ATTRIB_ATTR_13_ATTR_BAR3_MASK | 0 ); - - RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_13_ATTR_BAR3_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_13_OFFSET ,0x0000FFFFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : ATTR_14 @ 0XFD480038

- - For an endpoint, specifies mask/settings for Base Address Register (BAR) 3 if BAR2 is a 32-bit BAR, or the upper bits of \'7b - AR3,BAR2\'7d if BAR2 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR2 descri - tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: FFFF_0000 = IO Limit/Bas - Registers not implemented FFFF_F0F0 = IO Limit/Base Registers use 16-bit decode FFFF_F1F1 = IO Limit/Base Registers use 32-b - t decode For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of BAR2) [0] = Mem Space Indicator (s - t to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; - if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits - f \'7bBAR4,BAR3\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writabl - bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0xFFFF - PSU_PCIE_ATTRIB_ATTR_14_ATTR_BAR3 0xFFFF - - ATTR_14 - (OFFSET, MASK, VALUE) (0XFD480038, 0x0000FFFFU ,0x0000FFFFU) - RegMask = (PCIE_ATTRIB_ATTR_14_ATTR_BAR3_MASK | 0 ); - - RegVal = ((0x0000FFFFU << PCIE_ATTRIB_ATTR_14_ATTR_BAR3_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_14_OFFSET ,0x0000FFFFU ,0x0000FFFFU); - /*############################################################################################################################ */ - - /*Register : ATTR_15 @ 0XFD48003C

- - For an endpoint, specifies mask/settings for Base Address Register (BAR) 4 if BAR3 is a 32-bit BAR, or the upper bits of \'7b - AR4,BAR3\'7d if BAR3 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR3 descri - tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to FFF0_FFF0. For an endpoin - , bits are defined as follows: Memory Space BAR (not upper bits of BAR3) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi - ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe - most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR5,BAR4\'7d to - . IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper - ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0x0004; RP=0xFFF0 - PSU_PCIE_ATTRIB_ATTR_15_ATTR_BAR4 0xFFF0 - - ATTR_15 - (OFFSET, MASK, VALUE) (0XFD48003C, 0x0000FFFFU ,0x0000FFF0U) - RegMask = (PCIE_ATTRIB_ATTR_15_ATTR_BAR4_MASK | 0 ); - - RegVal = ((0x0000FFF0U << PCIE_ATTRIB_ATTR_15_ATTR_BAR4_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_15_OFFSET ,0x0000FFFFU ,0x0000FFF0U); - /*############################################################################################################################ */ - - /*Register : ATTR_16 @ 0XFD480040

- - For an endpoint, specifies mask/settings for Base Address Register (BAR) 4 if BAR3 is a 32-bit BAR, or the upper bits of \'7b - AR4,BAR3\'7d if BAR3 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR3 descri - tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to FFF0_FFF0. For an endpoin - , bits are defined as follows: Memory Space BAR (not upper bits of BAR3) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi - ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe - most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR5,BAR4\'7d to - . IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper - ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFF0; RP=0xFFF0 - PSU_PCIE_ATTRIB_ATTR_16_ATTR_BAR4 0xFFF0 - - ATTR_16 - (OFFSET, MASK, VALUE) (0XFD480040, 0x0000FFFFU ,0x0000FFF0U) - RegMask = (PCIE_ATTRIB_ATTR_16_ATTR_BAR4_MASK | 0 ); - - RegVal = ((0x0000FFF0U << PCIE_ATTRIB_ATTR_16_ATTR_BAR4_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_16_OFFSET ,0x0000FFFFU ,0x0000FFF0U); - /*############################################################################################################################ */ - - /*Register : ATTR_17 @ 0XFD480044

- - For an endpoint, specifies mask/settings for Base Address Register (BAR) 5 if BAR4 is a 32-bit BAR, or the upper bits of \'7b - AR5,BAR4\'7d if BAR4 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR4 descri - tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: 0000_0000 = Prefetchable - Memory Limit/Base Registers not implemented FFF0_FFF0 = 32-bit Prefetchable Memory Limit/Base implemented FFF1_FFF1 = 64-bit - refetchable Memory Limit/Base implemented For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of B - R4) [0] = Mem Space Indicator (set to 0) [2:1] = Type field (00 for 32-bit; BAR5 cannot be lower part of a 64-bit BAR) [3] = - refetchable (0 or 1) [31:4] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=memory aperture size in - ytes. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set u - permost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0xFFF1 - PSU_PCIE_ATTRIB_ATTR_17_ATTR_BAR5 0xFFF1 - - ATTR_17 - (OFFSET, MASK, VALUE) (0XFD480044, 0x0000FFFFU ,0x0000FFF1U) - RegMask = (PCIE_ATTRIB_ATTR_17_ATTR_BAR5_MASK | 0 ); - - RegVal = ((0x0000FFF1U << PCIE_ATTRIB_ATTR_17_ATTR_BAR5_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_17_OFFSET ,0x0000FFFFU ,0x0000FFF1U); - /*############################################################################################################################ */ - - /*Register : ATTR_18 @ 0XFD480048

- - For an endpoint, specifies mask/settings for Base Address Register (BAR) 5 if BAR4 is a 32-bit BAR, or the upper bits of \'7b - AR5,BAR4\'7d if BAR4 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR4 descri - tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: 0000_0000 = Prefetchable - Memory Limit/Base Registers not implemented FFF0_FFF0 = 32-bit Prefetchable Memory Limit/Base implemented FFF1_FFF1 = 64-bit - refetchable Memory Limit/Base implemented For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of B - R4) [0] = Mem Space Indicator (set to 0) [2:1] = Type field (00 for 32-bit; BAR5 cannot be lower part of a 64-bit BAR) [3] = - refetchable (0 or 1) [31:4] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=memory aperture size in - ytes. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set u - permost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0xFFF1 - PSU_PCIE_ATTRIB_ATTR_18_ATTR_BAR5 0xFFF1 - - ATTR_18 - (OFFSET, MASK, VALUE) (0XFD480048, 0x0000FFFFU ,0x0000FFF1U) - RegMask = (PCIE_ATTRIB_ATTR_18_ATTR_BAR5_MASK | 0 ); - - RegVal = ((0x0000FFF1U << PCIE_ATTRIB_ATTR_18_ATTR_BAR5_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_18_OFFSET ,0x0000FFFFU ,0x0000FFF1U); - /*############################################################################################################################ */ - - /*Register : ATTR_27 @ 0XFD48006C

- - Specifies maximum payload supported. Valid settings are: 0- 128 bytes, 1- 256 bytes, 2- 512 bytes, 3- 1024 bytes. Transferred - to the Device Capabilities register. The values: 4-2048 bytes, 5- 4096 bytes are not supported; EP=0x0001; RP=0x0001 - PSU_PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED 1 - - Endpoint L1 Acceptable Latency. Records the latency that the endpoint can withstand on transitions from L1 state to L0 (if L1 - state supported). Valid settings are: 0h less than 1us, 1h 1 to 2us, 2h 2 to 4us, 3h 4 to 8us, 4h 8 to 16us, 5h 16 to 32us, 6 - 32 to 64us, 7h more than 64us. For Endpoints only. Must be 0h for other devices.; EP=0x0007; RP=0x0000 - PSU_PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY 0x0 - - ATTR_27 - (OFFSET, MASK, VALUE) (0XFD48006C, 0x00000738U ,0x00000100U) - RegMask = (PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_MASK | PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_MASK | 0 ); - - RegVal = ((0x00000001U << PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_SHIFT - | 0x00000000U << PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_27_OFFSET ,0x00000738U ,0x00000100U); - /*############################################################################################################################ */ - - /*Register : ATTR_50 @ 0XFD4800C8

- - Identifies the type of device/port as follows: 0000b PCI Express Endpoint device, 0001b Legacy PCI Express Endpoint device, 0 - 00b Root Port of PCI Express Root Complex, 0101b Upstream Port of PCI Express Switch, 0110b Downstream Port of PCI Express Sw - tch, 0111b PCIE Express to PCI/PCI-X Bridge, 1000b PCI/PCI-X to PCI Express Bridge. Transferred to PCI Express Capabilities r - gister. Must be consistent with IS_SWITCH and UPSTREAM_FACING settings.; EP=0x0000; RP=0x0004 - PSU_PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE 4 - - PCIe Capability's Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capab - lity.; EP=0x009C; RP=0x0000 - PSU_PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR 0 - - ATTR_50 - (OFFSET, MASK, VALUE) (0XFD4800C8, 0x0000FFF0U ,0x00000040U) - RegMask = (PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_MASK | PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_MASK | 0 ); - - RegVal = ((0x00000004U << PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_SHIFT - | 0x00000000U << PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_50_OFFSET ,0x0000FFF0U ,0x00000040U); - /*############################################################################################################################ */ - - /*Register : ATTR_105 @ 0XFD4801A4

- - Number of credits that should be advertised for Completion data received on Virtual Channel 0. The bytes advertised must be l - ss than or equal to the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0172; RP=0x00CD - PSU_PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD 0xCD - - ATTR_105 - (OFFSET, MASK, VALUE) (0XFD4801A4, 0x000007FFU ,0x000000CDU) - RegMask = (PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_MASK | 0 ); - - RegVal = ((0x000000CDU << PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_105_OFFSET ,0x000007FFU ,0x000000CDU); - /*############################################################################################################################ */ - - /*Register : ATTR_106 @ 0XFD4801A8

- - Number of credits that should be advertised for Completion headers received on Virtual Channel 0. The sum of the posted, non - osted, and completion header credits must be <= 80; EP=0x0048; RP=0x0024 - PSU_PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH 0x24 - - Number of credits that should be advertised for Non-Posted headers received on Virtual Channel 0. The number of non posted da - a credits advertised by the block is equal to the number of non posted header credits. The sum of the posted, non posted, and - completion header credits must be <= 80; EP=0x0004; RP=0x000C - PSU_PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH 0xC - - ATTR_106 - (OFFSET, MASK, VALUE) (0XFD4801A8, 0x00003FFFU ,0x00000624U) - RegMask = (PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_MASK | PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_MASK | 0 ); - - RegVal = ((0x00000024U << PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_SHIFT - | 0x0000000CU << PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_106_OFFSET ,0x00003FFFU ,0x00000624U); - /*############################################################################################################################ */ - - /*Register : ATTR_107 @ 0XFD4801AC

- - Number of credits that should be advertised for Non-Posted data received on Virtual Channel 0. The number of non posted data - redits advertised by the block is equal to two times the number of non posted header credits if atomic operations are support - d or is equal to the number of non posted header credits if atomic operations are not supported. The bytes advertised must be - less than or equal to the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0008; RP=0x0018 - PSU_PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD 0x18 - - ATTR_107 - (OFFSET, MASK, VALUE) (0XFD4801AC, 0x000007FFU ,0x00000018U) - RegMask = (PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_MASK | 0 ); - - RegVal = ((0x00000018U << PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_107_OFFSET ,0x000007FFU ,0x00000018U); - /*############################################################################################################################ */ - - /*Register : ATTR_108 @ 0XFD4801B0

- - Number of credits that should be advertised for Posted data received on Virtual Channel 0. The bytes advertised must be less - han or equal to the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0020; RP=0x00B5 - PSU_PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD 0xB5 - - ATTR_108 - (OFFSET, MASK, VALUE) (0XFD4801B0, 0x000007FFU ,0x000000B5U) - RegMask = (PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_MASK | 0 ); - - RegVal = ((0x000000B5U << PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_108_OFFSET ,0x000007FFU ,0x000000B5U); - /*############################################################################################################################ */ - - /*Register : ATTR_109 @ 0XFD4801B4

- - Not currently in use. Invert ECRC generated by block when trn_tecrc_gen_n and trn_terrfwd_n are asserted.; EP=0x0000; RP=0x00 - 0 - PSU_PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV 0x0 - - Enables td bit clear and ECRC trim on received TLP's FALSE == don't trim TRUE == trim.; EP=0x0001; RP=0x0001 - PSU_PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM 0x1 - - Enables ECRC check on received TLP's 0 == don't check 1 == always check 3 == check if enabled by ECRC check enable bit of AER - cap structure; EP=0x0003; RP=0x0003 - PSU_PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK 0x3 - - Index of last packet buffer used by TX TLM (i.e. number of buffers - 1). Calculated from max payload size supported and the n - mber of brams configured for transmit; EP=0x001C; RP=0x001C - PSU_PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET 0x1c - - Number of credits that should be advertised for Posted headers received on Virtual Channel 0. The sum of the posted, non post - d, and completion header credits must be <= 80; EP=0x0004; RP=0x0020 - PSU_PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH 0x20 - - ATTR_109 - (OFFSET, MASK, VALUE) (0XFD4801B4, 0x0000FFFFU ,0x00007E20U) - RegMask = (PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_MASK | PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_MASK | PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_MASK | PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_MASK | PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_MASK | 0 ); - - RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_SHIFT - | 0x00000001U << PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_SHIFT - | 0x00000003U << PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_SHIFT - | 0x0000001CU << PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_SHIFT - | 0x00000020U << PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_109_OFFSET ,0x0000FFFFU ,0x00007E20U); - /*############################################################################################################################ */ - - /*Register : ATTR_34 @ 0XFD480088

- - Specifies values to be transferred to Header Type register. Bit 7 should be set to '0' indicating single-function device. Bit - 0 identifies header as Type 0 or Type 1, with '0' indicating a Type 0 header.; EP=0x0000; RP=0x0001 - PSU_PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE 0x1 - - ATTR_34 - (OFFSET, MASK, VALUE) (0XFD480088, 0x000000FFU ,0x00000001U) - RegMask = (PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_MASK | 0 ); - - RegVal = ((0x00000001U << PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_34_OFFSET ,0x000000FFU ,0x00000001U); - /*############################################################################################################################ */ - - /*Register : ATTR_53 @ 0XFD4800D4

- - PM Capability's Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capabil - ty.; EP=0x0048; RP=0x0060 - PSU_PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR 0x60 - - ATTR_53 - (OFFSET, MASK, VALUE) (0XFD4800D4, 0x000000FFU ,0x00000060U) - RegMask = (PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_MASK | 0 ); - - RegVal = ((0x00000060U << PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_53_OFFSET ,0x000000FFU ,0x00000060U); - /*############################################################################################################################ */ - - /*Register : ATTR_41 @ 0XFD4800A4

- - MSI Per-Vector Masking Capable. The value is transferred to the MSI Control Register[8]. When set, adds Mask and Pending Dwor - to Cap structure; EP=0x0000; RP=0x0000 - PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE 0x0 - - Indicates that the MSI structures exists. If this is FALSE, then the MSI structure cannot be accessed via either the link or - he management port.; EP=0x0001; RP=0x0000 - PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON 0 - - MSI Capability's Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capabi - ity.; EP=0x0060; RP=0x0000 - PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR 0x0 - - Indicates that the MSI structures exists. If this is FALSE, then the MSI structure cannot be accessed via either the link or - he management port.; EP=0x0001; RP=0x0000 - PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON 0 - - ATTR_41 - (OFFSET, MASK, VALUE) (0XFD4800A4, 0x000003FFU ,0x00000000U) - RegMask = (PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_MASK | PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_MASK | PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_MASK | PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_MASK | 0 ); - - RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_SHIFT - | 0x00000000U << PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_SHIFT - | 0x00000000U << PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_SHIFT - | 0x00000000U << PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_41_OFFSET ,0x000003FFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : ATTR_97 @ 0XFD480184

- - Maximum Link Width. Valid settings are: 000001b x1, 000010b x2, 000100b x4, 001000b x8.; EP=0x0004; RP=0x0004 - PSU_PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH 0x1 - - Used by LTSSM to set Maximum Link Width. Valid settings are: 000001b [x1], 000010b [x2], 000100b [x4], 001000b [x8].; EP=0x00 - 4; RP=0x0004 - PSU_PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH 0x1 - - ATTR_97 - (OFFSET, MASK, VALUE) (0XFD480184, 0x00000FFFU ,0x00000041U) - RegMask = (PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_MASK | PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_MASK | 0 ); - - RegVal = ((0x00000001U << PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_SHIFT - | 0x00000001U << PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_97_OFFSET ,0x00000FFFU ,0x00000041U); - /*############################################################################################################################ */ - - /*Register : ATTR_100 @ 0XFD480190

- - TRUE specifies upstream-facing port. FALSE specifies downstream-facing port.; EP=0x0001; RP=0x0000 - PSU_PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING 0x0 - - ATTR_100 - (OFFSET, MASK, VALUE) (0XFD480190, 0x00000040U ,0x00000000U) - RegMask = (PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_MASK | 0 ); - - RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_100_OFFSET ,0x00000040U ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : ATTR_101 @ 0XFD480194

- - Enable the routing of message TLPs to the user through the TRN RX interface. A bit value of 1 enables routing of the message - LP to the user. Messages are always decoded by the message decoder. Bit 0 - ERR COR, Bit 1 - ERR NONFATAL, Bit 2 - ERR FATAL, - Bit 3 - INTA Bit 4 - INTB, Bit 5 - INTC, Bit 6 - INTD, Bit 7 PM_PME, Bit 8 - PME_TO_ACK, Bit 9 - unlock, Bit 10 PME_Turn_Off; - EP=0x0000; RP=0x07FF - PSU_PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE 0x7FF - - Disable BAR filtering. Does not change the behavior of the bar hit outputs; EP=0x0000; RP=0x0001 - PSU_PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING 0x1 - - ATTR_101 - (OFFSET, MASK, VALUE) (0XFD480194, 0x0000FFE2U ,0x0000FFE2U) - RegMask = (PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_MASK | PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_MASK | 0 ); - - RegVal = ((0x000007FFU << PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_SHIFT - | 0x00000001U << PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_101_OFFSET ,0x0000FFE2U ,0x0000FFE2U); - /*############################################################################################################################ */ - - /*Register : ATTR_37 @ 0XFD480094

- - Link Bandwidth notification capability. Indicates support for the link bandwidth notification status and interrupt mechanism. - Required for Root.; EP=0x0000; RP=0x0001 - PSU_PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP 0x1 - - Sets the ASPM Optionality Compliance bit, to comply with the 2.1 ASPM Optionality ECN. Transferred to the Link Capabilities r - gister.; EP=0x0001; RP=0x0001 - PSU_PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY 0x1 - - ATTR_37 - (OFFSET, MASK, VALUE) (0XFD480094, 0x00004200U ,0x00004200U) - RegMask = (PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_MASK | PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_MASK | 0 ); - - RegVal = ((0x00000001U << PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_SHIFT - | 0x00000001U << PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_37_OFFSET ,0x00004200U ,0x00004200U); - /*############################################################################################################################ */ - - /*Register : ATTR_93 @ 0XFD480174

- - Enables the Replay Timer to use the user-defined LL_REPLAY_TIMEOUT value (or combined with the built-in value, depending on L - _REPLAY_TIMEOUT_FUNC). If FALSE, the built-in value is used.; EP=0x0000; RP=0x0000 - PSU_PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN 0x1 - - Sets a user-defined timeout for the Replay Timer to force cause the retransmission of unacknowledged TLPs; refer to LL_REPLAY - TIMEOUT_EN and LL_REPLAY_TIMEOUT_FUNC to see how this value is used. The unit for this attribute is in symbol times, which is - 4ns at GEN1 speeds and 2ns at GEN2.; EP=0x0000; RP=0x0000 - PSU_PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT 0x1000 - - ATTR_93 - (OFFSET, MASK, VALUE) (0XFD480174, 0x0000FFFFU ,0x00009000U) - RegMask = (PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_MASK | PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_MASK | 0 ); - - RegVal = ((0x00000001U << PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_SHIFT - | 0x00001000U << PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_93_OFFSET ,0x0000FFFFU ,0x00009000U); - /*############################################################################################################################ */ - - /*Register : ID @ 0XFD480200

- - Device ID for the the PCIe Cap Structure Device ID field - PSU_PCIE_ATTRIB_ID_CFG_DEV_ID 0xd021 - - Vendor ID for the PCIe Cap Structure Vendor ID field - PSU_PCIE_ATTRIB_ID_CFG_VEND_ID 0x10ee - - ID - (OFFSET, MASK, VALUE) (0XFD480200, 0xFFFFFFFFU ,0x10EED021U) - RegMask = (PCIE_ATTRIB_ID_CFG_DEV_ID_MASK | PCIE_ATTRIB_ID_CFG_VEND_ID_MASK | 0 ); - - RegVal = ((0x0000D021U << PCIE_ATTRIB_ID_CFG_DEV_ID_SHIFT - | 0x000010EEU << PCIE_ATTRIB_ID_CFG_VEND_ID_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ID_OFFSET ,0xFFFFFFFFU ,0x10EED021U); - /*############################################################################################################################ */ - - /*Register : SUBSYS_ID @ 0XFD480204

- - Subsystem ID for the the PCIe Cap Structure Subsystem ID field - PSU_PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID 0x7 - - Subsystem Vendor ID for the PCIe Cap Structure Subsystem Vendor ID field - PSU_PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID 0x10ee - - SUBSYS_ID - (OFFSET, MASK, VALUE) (0XFD480204, 0xFFFFFFFFU ,0x10EE0007U) - RegMask = (PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_MASK | PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_MASK | 0 ); - - RegVal = ((0x00000007U << PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_SHIFT - | 0x000010EEU << PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_SUBSYS_ID_OFFSET ,0xFFFFFFFFU ,0x10EE0007U); - /*############################################################################################################################ */ - - /*Register : REV_ID @ 0XFD480208

- - Revision ID for the the PCIe Cap Structure - PSU_PCIE_ATTRIB_REV_ID_CFG_REV_ID 0x0 - - REV_ID - (OFFSET, MASK, VALUE) (0XFD480208, 0x000000FFU ,0x00000000U) - RegMask = (PCIE_ATTRIB_REV_ID_CFG_REV_ID_MASK | 0 ); - - RegVal = ((0x00000000U << PCIE_ATTRIB_REV_ID_CFG_REV_ID_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_REV_ID_OFFSET ,0x000000FFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : ATTR_24 @ 0XFD480060

- - Code identifying basic function, subclass and applicable programming interface. Transferred to the Class Code register.; EP=0 - 8000; RP=0x8000 - PSU_PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE 0x400 - - ATTR_24 - (OFFSET, MASK, VALUE) (0XFD480060, 0x0000FFFFU ,0x00000400U) - RegMask = (PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_MASK | 0 ); - - RegVal = ((0x00000400U << PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_24_OFFSET ,0x0000FFFFU ,0x00000400U); - /*############################################################################################################################ */ - - /*Register : ATTR_25 @ 0XFD480064

- - Code identifying basic function, subclass and applicable programming interface. Transferred to the Class Code register.; EP=0 - 0005; RP=0x0006 - PSU_PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE 0x6 - - INTX Interrupt Generation Capable. If FALSE, this will cause Command[10] to be hardwired to 0.; EP=0x0001; RP=0x0001 - PSU_PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED 0 - - ATTR_25 - (OFFSET, MASK, VALUE) (0XFD480064, 0x000001FFU ,0x00000006U) - RegMask = (PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_MASK | PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_MASK | 0 ); - - RegVal = ((0x00000006U << PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_SHIFT - | 0x00000000U << PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_25_OFFSET ,0x000001FFU ,0x00000006U); - /*############################################################################################################################ */ - - /*Register : ATTR_4 @ 0XFD480010

- - Indicates that the AER structures exists. If this is FALSE, then the AER structure cannot be accessed via either the link or - he management port, and AER will be considered to not be present for error management tasks (such as what types of error mess - ges are sent if an error is detected).; EP=0x0001; RP=0x0001 - PSU_PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON 0 - - Indicates that the AER structures exists. If this is FALSE, then the AER structure cannot be accessed via either the link or - he management port, and AER will be considered to not be present for error management tasks (such as what types of error mess - ges are sent if an error is detected).; EP=0x0001; RP=0x0001 - PSU_PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON 0 - - ATTR_4 - (OFFSET, MASK, VALUE) (0XFD480010, 0x00001000U ,0x00000000U) - RegMask = (PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_MASK | PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_MASK | 0 ); - - RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_SHIFT - | 0x00000000U << PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_4_OFFSET ,0x00001000U ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : ATTR_89 @ 0XFD480164

- - VSEC's Next Capability Offset pointer to the next item in the capabilities list, or 000h if this is the final capability.; EP - 0x0140; RP=0x0140 - PSU_PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR 0 - - ATTR_89 - (OFFSET, MASK, VALUE) (0XFD480164, 0x00001FFEU ,0x00000000U) - RegMask = (PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_MASK | 0 ); - - RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_89_OFFSET ,0x00001FFEU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : ATTR_79 @ 0XFD48013C

- - CRS SW Visibility. Indicates RC can return CRS to SW. Transferred to the Root Capabilities register.; EP=0x0000; RP=0x0000 - PSU_PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY 1 - - ATTR_79 - (OFFSET, MASK, VALUE) (0XFD48013C, 0x00000020U ,0x00000020U) - RegMask = (PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_MASK | 0 ); - - RegVal = ((0x00000001U << PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_79_OFFSET ,0x00000020U ,0x00000020U); - /*############################################################################################################################ */ - - /*Register : ATTR_43 @ 0XFD4800AC

- - Indicates that the MSIX structures exists. If this is FALSE, then the MSIX structure cannot be accessed via either the link o - the management port.; EP=0x0001; RP=0x0000 - PSU_PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON 0 - - ATTR_43 - (OFFSET, MASK, VALUE) (0XFD4800AC, 0x00000100U ,0x00000000U) - RegMask = (PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_MASK | 0 ); - - RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_43_OFFSET ,0x00000100U ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : ATTR_48 @ 0XFD4800C0

- - MSI-X Table Size. This value is transferred to the MSI-X Message Control[10:0] field. Set to 0 if MSI-X is not enabled. Note - hat the core does not implement the table; that must be implemented in user logic.; EP=0x0003; RP=0x0000 - PSU_PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE 0 - - ATTR_48 - (OFFSET, MASK, VALUE) (0XFD4800C0, 0x000007FFU ,0x00000000U) - RegMask = (PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_MASK | 0 ); - - RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_48_OFFSET ,0x000007FFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : ATTR_46 @ 0XFD4800B8

- - MSI-X Table Offset. This value is transferred to the MSI-X Table Offset field. Set to 0 if MSI-X is not enabled.; EP=0x0001; - P=0x0000 - PSU_PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET 0 - - ATTR_46 - (OFFSET, MASK, VALUE) (0XFD4800B8, 0x0000FFFFU ,0x00000000U) - RegMask = (PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_MASK | 0 ); - - RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_46_OFFSET ,0x0000FFFFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : ATTR_47 @ 0XFD4800BC

- - MSI-X Table Offset. This value is transferred to the MSI-X Table Offset field. Set to 0 if MSI-X is not enabled.; EP=0x0000; - P=0x0000 - PSU_PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET 0 - - ATTR_47 - (OFFSET, MASK, VALUE) (0XFD4800BC, 0x00001FFFU ,0x00000000U) - RegMask = (PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_MASK | 0 ); - - RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_47_OFFSET ,0x00001FFFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : ATTR_44 @ 0XFD4800B0

- - MSI-X Pending Bit Array Offset This value is transferred to the MSI-X PBA Offset field. Set to 0 if MSI-X is not enabled.; EP - 0x0001; RP=0x0000 - PSU_PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET 0 - - ATTR_44 - (OFFSET, MASK, VALUE) (0XFD4800B0, 0x0000FFFFU ,0x00000000U) - RegMask = (PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_MASK | 0 ); - - RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_44_OFFSET ,0x0000FFFFU ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : ATTR_45 @ 0XFD4800B4

- - MSI-X Pending Bit Array Offset This value is transferred to the MSI-X PBA Offset field. Set to 0 if MSI-X is not enabled.; EP - 0x1000; RP=0x0000 - PSU_PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET 0 - - ATTR_45 - (OFFSET, MASK, VALUE) (0XFD4800B4, 0x0000FFF8U ,0x00000000U) - RegMask = (PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_MASK | 0 ); - - RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_45_OFFSET ,0x0000FFF8U ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : CB @ 0XFD48031C

- - DT837748 Enable - PSU_PCIE_ATTRIB_CB_CB1 0x0 - - ECO Register 1 - (OFFSET, MASK, VALUE) (0XFD48031C, 0x00000002U ,0x00000000U) - RegMask = (PCIE_ATTRIB_CB_CB1_MASK | 0 ); - - RegVal = ((0x00000000U << PCIE_ATTRIB_CB_CB1_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_CB_OFFSET ,0x00000002U ,0x00000000U); - /*############################################################################################################################ */ - - /*Register : ATTR_35 @ 0XFD48008C

- - Active State PM Support. Indicates the level of active state power management supported by the selected PCI Express Link, enc - ded as follows: 0 Reserved, 1 L0s entry supported, 2 Reserved, 3 L0s and L1 entry supported.; EP=0x0001; RP=0x0001 - PSU_PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT 0x0 - - ATTR_35 - (OFFSET, MASK, VALUE) (0XFD48008C, 0x00003000U ,0x00000000U) - RegMask = (PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_MASK | 0 ); - - RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PCIE_ATTRIB_ATTR_35_OFFSET ,0x00003000U ,0x00000000U); - /*############################################################################################################################ */ - - // : PUTTING PCIE CONTROL IN RESET - /*Register : RST_FPD_TOP @ 0XFD1A0100

- - PCIE control block level reset - PSU_CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET 0X0 - - FPD Block level software controlled reset - (OFFSET, MASK, VALUE) (0XFD1A0100, 0x00020000U ,0x00000000U) - RegMask = (CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK | 0 ); - - RegVal = ((0x00000000U << CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_RST_FPD_TOP_OFFSET ,0x00020000U ,0x00000000U); - /*############################################################################################################################ */ - - // : CHECK PLL LOCK FOR LANE0 - /*Register : L0_PLL_STATUS_READ_1 @ 0XFD4023E4

- - Status Read value of PLL Lock - PSU_SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1 - (OFFSET, MASK, VALUE) (0XFD4023E4, 0x00000010U ,0x00000010U) */ - mask_poll(SERDES_L0_PLL_STATUS_READ_1_OFFSET,0x00000010U); - - /*############################################################################################################################ */ - - // : CHECK PLL LOCK FOR LANE1 - /*Register : L1_PLL_STATUS_READ_1 @ 0XFD4063E4

- - Status Read value of PLL Lock - PSU_SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1 - (OFFSET, MASK, VALUE) (0XFD4063E4, 0x00000010U ,0x00000010U) */ - mask_poll(SERDES_L1_PLL_STATUS_READ_1_OFFSET,0x00000010U); - - /*############################################################################################################################ */ - - // : CHECK PLL LOCK FOR LANE2 - /*Register : L2_PLL_STATUS_READ_1 @ 0XFD40A3E4

- - Status Read value of PLL Lock - PSU_SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1 - (OFFSET, MASK, VALUE) (0XFD40A3E4, 0x00000010U ,0x00000010U) */ - mask_poll(SERDES_L2_PLL_STATUS_READ_1_OFFSET,0x00000010U); - - /*############################################################################################################################ */ - - // : CHECK PLL LOCK FOR LANE3 - /*Register : L3_PLL_STATUS_READ_1 @ 0XFD40E3E4

- - Status Read value of PLL Lock - PSU_SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1 - (OFFSET, MASK, VALUE) (0XFD40E3E4, 0x00000010U ,0x00000010U) */ - mask_poll(SERDES_L3_PLL_STATUS_READ_1_OFFSET,0x00000010U); - - /*############################################################################################################################ */ - - // : SATA AHCI VENDOR SETTING - /*Register : PP2C @ 0XFD0C00AC

- - CIBGMN: COMINIT Burst Gap Minimum. - PSU_SATA_AHCI_VENDOR_PP2C_CIBGMN 0x18 - - CIBGMX: COMINIT Burst Gap Maximum. - PSU_SATA_AHCI_VENDOR_PP2C_CIBGMX 0x40 - - CIBGN: COMINIT Burst Gap Nominal. - PSU_SATA_AHCI_VENDOR_PP2C_CIBGN 0x18 - - CINMP: COMINIT Negate Minimum Period. - PSU_SATA_AHCI_VENDOR_PP2C_CINMP 0x28 - - PP2C - Port Phy2Cfg Register. This register controls the configuration of the Phy Control OOB timing for the COMINIT paramete - s for either Port 0 or Port 1. The Port configured is controlled by the value programmed into the Port Config Register. - (OFFSET, MASK, VALUE) (0XFD0C00AC, 0xFFFFFFFFU ,0x28184018U) - RegMask = (SATA_AHCI_VENDOR_PP2C_CIBGMN_MASK | SATA_AHCI_VENDOR_PP2C_CIBGMX_MASK | SATA_AHCI_VENDOR_PP2C_CIBGN_MASK | SATA_AHCI_VENDOR_PP2C_CINMP_MASK | 0 ); - - RegVal = ((0x00000018U << SATA_AHCI_VENDOR_PP2C_CIBGMN_SHIFT - | 0x00000040U << SATA_AHCI_VENDOR_PP2C_CIBGMX_SHIFT - | 0x00000018U << SATA_AHCI_VENDOR_PP2C_CIBGN_SHIFT - | 0x00000028U << SATA_AHCI_VENDOR_PP2C_CINMP_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SATA_AHCI_VENDOR_PP2C_OFFSET ,0xFFFFFFFFU ,0x28184018U); - /*############################################################################################################################ */ - - /*Register : PP3C @ 0XFD0C00B0

- - CWBGMN: COMWAKE Burst Gap Minimum. - PSU_SATA_AHCI_VENDOR_PP3C_CWBGMN 0x06 - - CWBGMX: COMWAKE Burst Gap Maximum. - PSU_SATA_AHCI_VENDOR_PP3C_CWBGMX 0x14 - - CWBGN: COMWAKE Burst Gap Nominal. - PSU_SATA_AHCI_VENDOR_PP3C_CWBGN 0x08 - - CWNMP: COMWAKE Negate Minimum Period. - PSU_SATA_AHCI_VENDOR_PP3C_CWNMP 0x0E - - PP3C - Port Phy3CfgRegister. This register controls the configuration of the Phy Control OOB timing for the COMWAKE parameter - for either Port 0 or Port 1. The Port configured is controlled by the value programmed into the Port Config Register. - (OFFSET, MASK, VALUE) (0XFD0C00B0, 0xFFFFFFFFU ,0x0E081406U) - RegMask = (SATA_AHCI_VENDOR_PP3C_CWBGMN_MASK | SATA_AHCI_VENDOR_PP3C_CWBGMX_MASK | SATA_AHCI_VENDOR_PP3C_CWBGN_MASK | SATA_AHCI_VENDOR_PP3C_CWNMP_MASK | 0 ); - - RegVal = ((0x00000006U << SATA_AHCI_VENDOR_PP3C_CWBGMN_SHIFT - | 0x00000014U << SATA_AHCI_VENDOR_PP3C_CWBGMX_SHIFT - | 0x00000008U << SATA_AHCI_VENDOR_PP3C_CWBGN_SHIFT - | 0x0000000EU << SATA_AHCI_VENDOR_PP3C_CWNMP_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SATA_AHCI_VENDOR_PP3C_OFFSET ,0xFFFFFFFFU ,0x0E081406U); - /*############################################################################################################################ */ - - /*Register : PP4C @ 0XFD0C00B4

- - BMX: COM Burst Maximum. - PSU_SATA_AHCI_VENDOR_PP4C_BMX 0x13 - - BNM: COM Burst Nominal. - PSU_SATA_AHCI_VENDOR_PP4C_BNM 0x08 - - SFD: Signal Failure Detection, if the signal detection de-asserts for a time greater than this then the OOB detector will det - rmine this is a line idle and cause the PhyInit state machine to exit the Phy Ready State. A value of zero disables the Signa - Failure Detector. The value is based on the OOB Detector Clock typically (PMCLK Clock Period) * SFD giving a nominal time of - 500ns based on a 150MHz PMCLK. - PSU_SATA_AHCI_VENDOR_PP4C_SFD 0x4A - - PTST: Partial to Slumber timer value, specific delay the controller should apply while in partial before entering slumber. Th - value is bases on the system clock divided by 128, total delay = (Sys Clock Period) * PTST * 128 - PSU_SATA_AHCI_VENDOR_PP4C_PTST 0x06 - - PP4C - Port Phy4Cfg Register. This register controls the configuration of the Phy Control Burst timing for the COM parameters - for either Port 0 or Port 1. The Port configured is controlled by the value programmed into the Port Config Register. - (OFFSET, MASK, VALUE) (0XFD0C00B4, 0xFFFFFFFFU ,0x064A0813U) - RegMask = (SATA_AHCI_VENDOR_PP4C_BMX_MASK | SATA_AHCI_VENDOR_PP4C_BNM_MASK | SATA_AHCI_VENDOR_PP4C_SFD_MASK | SATA_AHCI_VENDOR_PP4C_PTST_MASK | 0 ); - - RegVal = ((0x00000013U << SATA_AHCI_VENDOR_PP4C_BMX_SHIFT - | 0x00000008U << SATA_AHCI_VENDOR_PP4C_BNM_SHIFT - | 0x0000004AU << SATA_AHCI_VENDOR_PP4C_SFD_SHIFT - | 0x00000006U << SATA_AHCI_VENDOR_PP4C_PTST_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SATA_AHCI_VENDOR_PP4C_OFFSET ,0xFFFFFFFFU ,0x064A0813U); - /*############################################################################################################################ */ - - /*Register : PP5C @ 0XFD0C00B8

- - RIT: Retry Interval Timer. The calculated value divided by two, the lower digit of precision is not needed. - PSU_SATA_AHCI_VENDOR_PP5C_RIT 0xC96A4 - - RCT: Rate Change Timer, a value based on the 54.2us for which a SATA device will transmit at a fixed rate ALIGNp after OOB ha - completed, for a fast SERDES it is suggested that this value be 54.2us / 4 - PSU_SATA_AHCI_VENDOR_PP5C_RCT 0x3FF - - PP5C - Port Phy5Cfg Register. This register controls the configuration of the Phy Control Retry Interval timing for either Po - t 0 or Port 1. The Port configured is controlled by the value programmed into the Port Config Register. - (OFFSET, MASK, VALUE) (0XFD0C00B8, 0xFFFFFFFFU ,0x3FFC96A4U) - RegMask = (SATA_AHCI_VENDOR_PP5C_RIT_MASK | SATA_AHCI_VENDOR_PP5C_RCT_MASK | 0 ); - - RegVal = ((0x000C96A4U << SATA_AHCI_VENDOR_PP5C_RIT_SHIFT - | 0x000003FFU << SATA_AHCI_VENDOR_PP5C_RCT_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (SATA_AHCI_VENDOR_PP5C_OFFSET ,0xFFFFFFFFU ,0x3FFC96A4U); - /*############################################################################################################################ */ - - - return 1; + * MPHY PLL Gear and bypass scrambler + * (OFFSET, MASK, VALUE) (0XFD40C0F4, 0x0000000BU ,0x0000000BU) + */ + PSU_Mask_Write(SERDES_L3_TX_DIG_TM_61_OFFSET, + 0x0000000BU, 0x0000000BU); +/*##################################################################### */ + + /* + * ENABLE CHICKEN BIT FOR PCIE AND USB + */ + /* + * Register : L0_TM_AUX_0 @ 0XFD4010CC + + * Spare- not used + * PSU_SERDES_L0_TM_AUX_0_BIT_2 1 + + * Spare registers + * (OFFSET, MASK, VALUE) (0XFD4010CC, 0x00000020U ,0x00000020U) + */ + PSU_Mask_Write(SERDES_L0_TM_AUX_0_OFFSET, 0x00000020U, 0x00000020U); +/*##################################################################### */ + + /* + * Register : L2_TM_AUX_0 @ 0XFD4090CC + + * Spare- not used + * PSU_SERDES_L2_TM_AUX_0_BIT_2 1 + + * Spare registers + * (OFFSET, MASK, VALUE) (0XFD4090CC, 0x00000020U ,0x00000020U) + */ + PSU_Mask_Write(SERDES_L2_TM_AUX_0_OFFSET, 0x00000020U, 0x00000020U); +/*##################################################################### */ + + /* + * ENABLING EYE SURF + */ + /* + * Register : L0_TM_DIG_8 @ 0XFD401074 + + * Enable Eye Surf + * PSU_SERDES_L0_TM_DIG_8_EYESURF_ENABLE 0x1 + + * Test modes for Elastic buffer and enabling Eye Surf + * (OFFSET, MASK, VALUE) (0XFD401074, 0x00000010U ,0x00000010U) + */ + PSU_Mask_Write(SERDES_L0_TM_DIG_8_OFFSET, 0x00000010U, 0x00000010U); +/*##################################################################### */ + + /* + * Register : L1_TM_DIG_8 @ 0XFD405074 + + * Enable Eye Surf + * PSU_SERDES_L1_TM_DIG_8_EYESURF_ENABLE 0x1 + + * Test modes for Elastic buffer and enabling Eye Surf + * (OFFSET, MASK, VALUE) (0XFD405074, 0x00000010U ,0x00000010U) + */ + PSU_Mask_Write(SERDES_L1_TM_DIG_8_OFFSET, 0x00000010U, 0x00000010U); +/*##################################################################### */ + + /* + * Register : L2_TM_DIG_8 @ 0XFD409074 + + * Enable Eye Surf + * PSU_SERDES_L2_TM_DIG_8_EYESURF_ENABLE 0x1 + + * Test modes for Elastic buffer and enabling Eye Surf + * (OFFSET, MASK, VALUE) (0XFD409074, 0x00000010U ,0x00000010U) + */ + PSU_Mask_Write(SERDES_L2_TM_DIG_8_OFFSET, 0x00000010U, 0x00000010U); +/*##################################################################### */ + + /* + * Register : L3_TM_DIG_8 @ 0XFD40D074 + + * Enable Eye Surf + * PSU_SERDES_L3_TM_DIG_8_EYESURF_ENABLE 0x1 + + * Test modes for Elastic buffer and enabling Eye Surf + * (OFFSET, MASK, VALUE) (0XFD40D074, 0x00000010U ,0x00000010U) + */ + PSU_Mask_Write(SERDES_L3_TM_DIG_8_OFFSET, 0x00000010U, 0x00000010U); +/*##################################################################### */ + + /* + * ILL SETTINGS FOR GAIN AND LOCK SETTINGS + */ + /* + * Register : L0_TM_MISC2 @ 0XFD40189C + + * ILL calib counts BYPASSED with calcode bits + * PSU_SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS 0x1 + + * sampler cal + * (OFFSET, MASK, VALUE) (0XFD40189C, 0x00000080U ,0x00000080U) + */ + PSU_Mask_Write(SERDES_L0_TM_MISC2_OFFSET, 0x00000080U, 0x00000080U); +/*##################################################################### */ + + /* + * Register : L0_TM_IQ_ILL1 @ 0XFD4018F8 + + * IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , + * USB3 : SS + * PSU_SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0 0x64 + + * iqpi cal code + * (OFFSET, MASK, VALUE) (0XFD4018F8, 0x000000FFU ,0x00000064U) + */ + PSU_Mask_Write(SERDES_L0_TM_IQ_ILL1_OFFSET, + 0x000000FFU, 0x00000064U); +/*##################################################################### */ + + /* + * Register : L0_TM_IQ_ILL2 @ 0XFD4018FC + + * IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 + * PSU_SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1 0x64 + + * iqpi cal code + * (OFFSET, MASK, VALUE) (0XFD4018FC, 0x000000FFU ,0x00000064U) + */ + PSU_Mask_Write(SERDES_L0_TM_IQ_ILL2_OFFSET, + 0x000000FFU, 0x00000064U); +/*##################################################################### */ + + /* + * Register : L0_TM_ILL12 @ 0XFD401990 + + * G1A pll ctr bypass value + * PSU_SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL 0x11 + + * ill pll counter values + * (OFFSET, MASK, VALUE) (0XFD401990, 0x000000FFU ,0x00000011U) + */ + PSU_Mask_Write(SERDES_L0_TM_ILL12_OFFSET, 0x000000FFU, 0x00000011U); +/*##################################################################### */ + + /* + * Register : L0_TM_E_ILL1 @ 0XFD401924 + + * E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , U + * SB3 : SS + * PSU_SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0 0x4 + + * epi cal code + * (OFFSET, MASK, VALUE) (0XFD401924, 0x000000FFU ,0x00000004U) + */ + PSU_Mask_Write(SERDES_L0_TM_E_ILL1_OFFSET, 0x000000FFU, 0x00000004U); +/*##################################################################### */ + + /* + * Register : L0_TM_E_ILL2 @ 0XFD401928 + + * E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 + * PSU_SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1 0xFE + + * epi cal code + * (OFFSET, MASK, VALUE) (0XFD401928, 0x000000FFU ,0x000000FEU) + */ + PSU_Mask_Write(SERDES_L0_TM_E_ILL2_OFFSET, 0x000000FFU, 0x000000FEU); +/*##################################################################### */ + + /* + * Register : L0_TM_IQ_ILL3 @ 0XFD401900 + + * IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 + * PSU_SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2 0x64 + + * iqpi cal code + * (OFFSET, MASK, VALUE) (0XFD401900, 0x000000FFU ,0x00000064U) + */ + PSU_Mask_Write(SERDES_L0_TM_IQ_ILL3_OFFSET, + 0x000000FFU, 0x00000064U); +/*##################################################################### */ + + /* + * Register : L0_TM_E_ILL3 @ 0XFD40192C + + * E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 + * PSU_SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2 0x0 + + * epi cal code + * (OFFSET, MASK, VALUE) (0XFD40192C, 0x000000FFU ,0x00000000U) + */ + PSU_Mask_Write(SERDES_L0_TM_E_ILL3_OFFSET, 0x000000FFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : L0_TM_ILL8 @ 0XFD401980 + + * ILL calibration code change wait time + * PSU_SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT 0xFF + + * ILL cal routine control + * (OFFSET, MASK, VALUE) (0XFD401980, 0x000000FFU ,0x000000FFU) + */ + PSU_Mask_Write(SERDES_L0_TM_ILL8_OFFSET, 0x000000FFU, 0x000000FFU); +/*##################################################################### */ + + /* + * Register : L0_TM_IQ_ILL8 @ 0XFD401914 + + * IQ ILL polytrim bypass value + * PSU_SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL 0xF7 + + * iqpi polytrim + * (OFFSET, MASK, VALUE) (0XFD401914, 0x000000FFU ,0x000000F7U) + */ + PSU_Mask_Write(SERDES_L0_TM_IQ_ILL8_OFFSET, + 0x000000FFU, 0x000000F7U); +/*##################################################################### */ + + /* + * Register : L0_TM_IQ_ILL9 @ 0XFD401918 + + * bypass IQ polytrim + * PSU_SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM 0x1 + + * enables for lf,constant gm trim and polytirm + * (OFFSET, MASK, VALUE) (0XFD401918, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L0_TM_IQ_ILL9_OFFSET, + 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : L0_TM_E_ILL8 @ 0XFD401940 + + * E ILL polytrim bypass value + * PSU_SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL 0xF7 + + * epi polytrim + * (OFFSET, MASK, VALUE) (0XFD401940, 0x000000FFU ,0x000000F7U) + */ + PSU_Mask_Write(SERDES_L0_TM_E_ILL8_OFFSET, 0x000000FFU, 0x000000F7U); +/*##################################################################### */ + + /* + * Register : L0_TM_E_ILL9 @ 0XFD401944 + + * bypass E polytrim + * PSU_SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM 0x1 + + * enables for lf,constant gm trim and polytirm + * (OFFSET, MASK, VALUE) (0XFD401944, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L0_TM_E_ILL9_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : L0_TM_ILL13 @ 0XFD401994 + + * ILL cal idle val refcnt + * PSU_SERDES_L0_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT 0x7 + + * ill cal idle value count + * (OFFSET, MASK, VALUE) (0XFD401994, 0x00000007U ,0x00000007U) + */ + PSU_Mask_Write(SERDES_L0_TM_ILL13_OFFSET, 0x00000007U, 0x00000007U); +/*##################################################################### */ + + /* + * Register : L1_TM_ILL13 @ 0XFD405994 + + * ILL cal idle val refcnt + * PSU_SERDES_L1_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT 0x7 + + * ill cal idle value count + * (OFFSET, MASK, VALUE) (0XFD405994, 0x00000007U ,0x00000007U) + */ + PSU_Mask_Write(SERDES_L1_TM_ILL13_OFFSET, 0x00000007U, 0x00000007U); +/*##################################################################### */ + + /* + * Register : L2_TM_MISC2 @ 0XFD40989C + + * ILL calib counts BYPASSED with calcode bits + * PSU_SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS 0x1 + + * sampler cal + * (OFFSET, MASK, VALUE) (0XFD40989C, 0x00000080U ,0x00000080U) + */ + PSU_Mask_Write(SERDES_L2_TM_MISC2_OFFSET, 0x00000080U, 0x00000080U); +/*##################################################################### */ + + /* + * Register : L2_TM_IQ_ILL1 @ 0XFD4098F8 + + * IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , + * USB3 : SS + * PSU_SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0 0x1A + + * iqpi cal code + * (OFFSET, MASK, VALUE) (0XFD4098F8, 0x000000FFU ,0x0000001AU) + */ + PSU_Mask_Write(SERDES_L2_TM_IQ_ILL1_OFFSET, + 0x000000FFU, 0x0000001AU); +/*##################################################################### */ + + /* + * Register : L2_TM_IQ_ILL2 @ 0XFD4098FC + + * IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 + * PSU_SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1 0x1A + + * iqpi cal code + * (OFFSET, MASK, VALUE) (0XFD4098FC, 0x000000FFU ,0x0000001AU) + */ + PSU_Mask_Write(SERDES_L2_TM_IQ_ILL2_OFFSET, + 0x000000FFU, 0x0000001AU); +/*##################################################################### */ + + /* + * Register : L2_TM_ILL12 @ 0XFD409990 + + * G1A pll ctr bypass value + * PSU_SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL 0x10 + + * ill pll counter values + * (OFFSET, MASK, VALUE) (0XFD409990, 0x000000FFU ,0x00000010U) + */ + PSU_Mask_Write(SERDES_L2_TM_ILL12_OFFSET, 0x000000FFU, 0x00000010U); +/*##################################################################### */ + + /* + * Register : L2_TM_E_ILL1 @ 0XFD409924 + + * E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , U + * SB3 : SS + * PSU_SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0 0xFE + + * epi cal code + * (OFFSET, MASK, VALUE) (0XFD409924, 0x000000FFU ,0x000000FEU) + */ + PSU_Mask_Write(SERDES_L2_TM_E_ILL1_OFFSET, 0x000000FFU, 0x000000FEU); +/*##################################################################### */ + + /* + * Register : L2_TM_E_ILL2 @ 0XFD409928 + + * E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 + * PSU_SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1 0x0 + + * epi cal code + * (OFFSET, MASK, VALUE) (0XFD409928, 0x000000FFU ,0x00000000U) + */ + PSU_Mask_Write(SERDES_L2_TM_E_ILL2_OFFSET, 0x000000FFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : L2_TM_IQ_ILL3 @ 0XFD409900 + + * IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 + * PSU_SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2 0x1A + + * iqpi cal code + * (OFFSET, MASK, VALUE) (0XFD409900, 0x000000FFU ,0x0000001AU) + */ + PSU_Mask_Write(SERDES_L2_TM_IQ_ILL3_OFFSET, + 0x000000FFU, 0x0000001AU); +/*##################################################################### */ + + /* + * Register : L2_TM_E_ILL3 @ 0XFD40992C + + * E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 + * PSU_SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2 0x0 + + * epi cal code + * (OFFSET, MASK, VALUE) (0XFD40992C, 0x000000FFU ,0x00000000U) + */ + PSU_Mask_Write(SERDES_L2_TM_E_ILL3_OFFSET, 0x000000FFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : L2_TM_ILL8 @ 0XFD409980 + + * ILL calibration code change wait time + * PSU_SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT 0xFF + + * ILL cal routine control + * (OFFSET, MASK, VALUE) (0XFD409980, 0x000000FFU ,0x000000FFU) + */ + PSU_Mask_Write(SERDES_L2_TM_ILL8_OFFSET, 0x000000FFU, 0x000000FFU); +/*##################################################################### */ + + /* + * Register : L2_TM_IQ_ILL8 @ 0XFD409914 + + * IQ ILL polytrim bypass value + * PSU_SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL 0xF7 + + * iqpi polytrim + * (OFFSET, MASK, VALUE) (0XFD409914, 0x000000FFU ,0x000000F7U) + */ + PSU_Mask_Write(SERDES_L2_TM_IQ_ILL8_OFFSET, + 0x000000FFU, 0x000000F7U); +/*##################################################################### */ + + /* + * Register : L2_TM_IQ_ILL9 @ 0XFD409918 + + * bypass IQ polytrim + * PSU_SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM 0x1 + + * enables for lf,constant gm trim and polytirm + * (OFFSET, MASK, VALUE) (0XFD409918, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L2_TM_IQ_ILL9_OFFSET, + 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : L2_TM_E_ILL8 @ 0XFD409940 + + * E ILL polytrim bypass value + * PSU_SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL 0xF7 + + * epi polytrim + * (OFFSET, MASK, VALUE) (0XFD409940, 0x000000FFU ,0x000000F7U) + */ + PSU_Mask_Write(SERDES_L2_TM_E_ILL8_OFFSET, 0x000000FFU, 0x000000F7U); +/*##################################################################### */ + + /* + * Register : L2_TM_E_ILL9 @ 0XFD409944 + + * bypass E polytrim + * PSU_SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM 0x1 + + * enables for lf,constant gm trim and polytirm + * (OFFSET, MASK, VALUE) (0XFD409944, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L2_TM_E_ILL9_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : L2_TM_ILL13 @ 0XFD409994 + + * ILL cal idle val refcnt + * PSU_SERDES_L2_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT 0x7 + + * ill cal idle value count + * (OFFSET, MASK, VALUE) (0XFD409994, 0x00000007U ,0x00000007U) + */ + PSU_Mask_Write(SERDES_L2_TM_ILL13_OFFSET, 0x00000007U, 0x00000007U); +/*##################################################################### */ + + /* + * Register : L3_TM_MISC2 @ 0XFD40D89C + + * ILL calib counts BYPASSED with calcode bits + * PSU_SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS 0x1 + + * sampler cal + * (OFFSET, MASK, VALUE) (0XFD40D89C, 0x00000080U ,0x00000080U) + */ + PSU_Mask_Write(SERDES_L3_TM_MISC2_OFFSET, 0x00000080U, 0x00000080U); +/*##################################################################### */ + + /* + * Register : L3_TM_IQ_ILL1 @ 0XFD40D8F8 + + * IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , + * USB3 : SS + * PSU_SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0 0x7D + + * iqpi cal code + * (OFFSET, MASK, VALUE) (0XFD40D8F8, 0x000000FFU ,0x0000007DU) + */ + PSU_Mask_Write(SERDES_L3_TM_IQ_ILL1_OFFSET, + 0x000000FFU, 0x0000007DU); +/*##################################################################### */ + + /* + * Register : L3_TM_IQ_ILL2 @ 0XFD40D8FC + + * IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 + * PSU_SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1 0x7D + + * iqpi cal code + * (OFFSET, MASK, VALUE) (0XFD40D8FC, 0x000000FFU ,0x0000007DU) + */ + PSU_Mask_Write(SERDES_L3_TM_IQ_ILL2_OFFSET, + 0x000000FFU, 0x0000007DU); +/*##################################################################### */ + + /* + * Register : L3_TM_ILL12 @ 0XFD40D990 + + * G1A pll ctr bypass value + * PSU_SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL 0x1 + + * ill pll counter values + * (OFFSET, MASK, VALUE) (0XFD40D990, 0x000000FFU ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L3_TM_ILL12_OFFSET, 0x000000FFU, 0x00000001U); +/*##################################################################### */ + + /* + * Register : L3_TM_E_ILL1 @ 0XFD40D924 + + * E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , U + * SB3 : SS + * PSU_SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0 0x9C + + * epi cal code + * (OFFSET, MASK, VALUE) (0XFD40D924, 0x000000FFU ,0x0000009CU) + */ + PSU_Mask_Write(SERDES_L3_TM_E_ILL1_OFFSET, 0x000000FFU, 0x0000009CU); +/*##################################################################### */ + + /* + * Register : L3_TM_E_ILL2 @ 0XFD40D928 + + * E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 + * PSU_SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1 0x39 + + * epi cal code + * (OFFSET, MASK, VALUE) (0XFD40D928, 0x000000FFU ,0x00000039U) + */ + PSU_Mask_Write(SERDES_L3_TM_E_ILL2_OFFSET, 0x000000FFU, 0x00000039U); +/*##################################################################### */ + + /* + * Register : L3_TM_ILL11 @ 0XFD40D98C + + * G2A_PCIe1 PLL ctr bypass value + * PSU_SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL 0x2 + + * ill pll counter values + * (OFFSET, MASK, VALUE) (0XFD40D98C, 0x000000F0U ,0x00000020U) + */ + PSU_Mask_Write(SERDES_L3_TM_ILL11_OFFSET, 0x000000F0U, 0x00000020U); +/*##################################################################### */ + + /* + * Register : L3_TM_IQ_ILL3 @ 0XFD40D900 + + * IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 + * PSU_SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2 0x7D + + * iqpi cal code + * (OFFSET, MASK, VALUE) (0XFD40D900, 0x000000FFU ,0x0000007DU) + */ + PSU_Mask_Write(SERDES_L3_TM_IQ_ILL3_OFFSET, + 0x000000FFU, 0x0000007DU); +/*##################################################################### */ + + /* + * Register : L3_TM_E_ILL3 @ 0XFD40D92C + + * E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 + * PSU_SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2 0x64 + + * epi cal code + * (OFFSET, MASK, VALUE) (0XFD40D92C, 0x000000FFU ,0x00000064U) + */ + PSU_Mask_Write(SERDES_L3_TM_E_ILL3_OFFSET, 0x000000FFU, 0x00000064U); +/*##################################################################### */ + + /* + * Register : L3_TM_ILL8 @ 0XFD40D980 + + * ILL calibration code change wait time + * PSU_SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT 0xFF + + * ILL cal routine control + * (OFFSET, MASK, VALUE) (0XFD40D980, 0x000000FFU ,0x000000FFU) + */ + PSU_Mask_Write(SERDES_L3_TM_ILL8_OFFSET, 0x000000FFU, 0x000000FFU); +/*##################################################################### */ + + /* + * Register : L3_TM_IQ_ILL8 @ 0XFD40D914 + + * IQ ILL polytrim bypass value + * PSU_SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL 0xF7 + + * iqpi polytrim + * (OFFSET, MASK, VALUE) (0XFD40D914, 0x000000FFU ,0x000000F7U) + */ + PSU_Mask_Write(SERDES_L3_TM_IQ_ILL8_OFFSET, + 0x000000FFU, 0x000000F7U); +/*##################################################################### */ + + /* + * Register : L3_TM_IQ_ILL9 @ 0XFD40D918 + + * bypass IQ polytrim + * PSU_SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM 0x1 + + * enables for lf,constant gm trim and polytirm + * (OFFSET, MASK, VALUE) (0XFD40D918, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L3_TM_IQ_ILL9_OFFSET, + 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : L3_TM_E_ILL8 @ 0XFD40D940 + + * E ILL polytrim bypass value + * PSU_SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL 0xF7 + + * epi polytrim + * (OFFSET, MASK, VALUE) (0XFD40D940, 0x000000FFU ,0x000000F7U) + */ + PSU_Mask_Write(SERDES_L3_TM_E_ILL8_OFFSET, 0x000000FFU, 0x000000F7U); +/*##################################################################### */ + + /* + * Register : L3_TM_E_ILL9 @ 0XFD40D944 + + * bypass E polytrim + * PSU_SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM 0x1 + + * enables for lf,constant gm trim and polytirm + * (OFFSET, MASK, VALUE) (0XFD40D944, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L3_TM_E_ILL9_OFFSET, 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : L3_TM_ILL13 @ 0XFD40D994 + + * ILL cal idle val refcnt + * PSU_SERDES_L3_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT 0x7 + + * ill cal idle value count + * (OFFSET, MASK, VALUE) (0XFD40D994, 0x00000007U ,0x00000007U) + */ + PSU_Mask_Write(SERDES_L3_TM_ILL13_OFFSET, 0x00000007U, 0x00000007U); +/*##################################################################### */ + + /* + * SYMBOL LOCK AND WAIT + */ + /* + * Register : L0_TM_DIG_10 @ 0XFD40107C + + * CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001 + * PSU_SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME 0x1 + + * test control for changing cdr lock wait time + * (OFFSET, MASK, VALUE) (0XFD40107C, 0x0000000FU ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L0_TM_DIG_10_OFFSET, 0x0000000FU, 0x00000001U); +/*##################################################################### */ + + /* + * Register : L1_TM_DIG_10 @ 0XFD40507C + + * CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001 + * PSU_SERDES_L1_TM_DIG_10_CDR_BIT_LOCK_TIME 0x1 + + * test control for changing cdr lock wait time + * (OFFSET, MASK, VALUE) (0XFD40507C, 0x0000000FU ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L1_TM_DIG_10_OFFSET, 0x0000000FU, 0x00000001U); +/*##################################################################### */ + + /* + * Register : L2_TM_DIG_10 @ 0XFD40907C + + * CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001 + * PSU_SERDES_L2_TM_DIG_10_CDR_BIT_LOCK_TIME 0x1 + + * test control for changing cdr lock wait time + * (OFFSET, MASK, VALUE) (0XFD40907C, 0x0000000FU ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L2_TM_DIG_10_OFFSET, 0x0000000FU, 0x00000001U); +/*##################################################################### */ + + /* + * Register : L3_TM_DIG_10 @ 0XFD40D07C + + * CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001 + * PSU_SERDES_L3_TM_DIG_10_CDR_BIT_LOCK_TIME 0x1 + + * test control for changing cdr lock wait time + * (OFFSET, MASK, VALUE) (0XFD40D07C, 0x0000000FU ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L3_TM_DIG_10_OFFSET, 0x0000000FU, 0x00000001U); +/*##################################################################### */ + + /* + * SIOU SETTINGS FOR BYPASS CONTROL,HSRX-DIG + */ + /* + * Register : L0_TM_RST_DLY @ 0XFD4019A4 + + * Delay apb reset by specified amount + * PSU_SERDES_L0_TM_RST_DLY_APB_RST_DLY 0xFF + + * reset delay for apb reset w.r.t pso of hsrx + * (OFFSET, MASK, VALUE) (0XFD4019A4, 0x000000FFU ,0x000000FFU) + */ + PSU_Mask_Write(SERDES_L0_TM_RST_DLY_OFFSET, + 0x000000FFU, 0x000000FFU); +/*##################################################################### */ + + /* + * Register : L0_TM_ANA_BYP_15 @ 0XFD401038 + + * Enable Bypass for <7> of TM_ANA_BYPS_15 + * PSU_SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE 0x1 + + * Bypass control for pcs-pma interface. EQ supplies, main master supply an + * d ps for samp c2c + * (OFFSET, MASK, VALUE) (0XFD401038, 0x00000040U ,0x00000040U) + */ + PSU_Mask_Write(SERDES_L0_TM_ANA_BYP_15_OFFSET, + 0x00000040U, 0x00000040U); +/*##################################################################### */ + + /* + * Register : L0_TM_ANA_BYP_12 @ 0XFD40102C + + * Enable Bypass for <7> of TM_ANA_BYPS_12 + * PSU_SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG 0x1 + + * Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr ena + * ble controls + * (OFFSET, MASK, VALUE) (0XFD40102C, 0x00000040U ,0x00000040U) + */ + PSU_Mask_Write(SERDES_L0_TM_ANA_BYP_12_OFFSET, + 0x00000040U, 0x00000040U); +/*##################################################################### */ + + /* + * Register : L1_TM_RST_DLY @ 0XFD4059A4 + + * Delay apb reset by specified amount + * PSU_SERDES_L1_TM_RST_DLY_APB_RST_DLY 0xFF + + * reset delay for apb reset w.r.t pso of hsrx + * (OFFSET, MASK, VALUE) (0XFD4059A4, 0x000000FFU ,0x000000FFU) + */ + PSU_Mask_Write(SERDES_L1_TM_RST_DLY_OFFSET, + 0x000000FFU, 0x000000FFU); +/*##################################################################### */ + + /* + * Register : L1_TM_ANA_BYP_15 @ 0XFD405038 + + * Enable Bypass for <7> of TM_ANA_BYPS_15 + * PSU_SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE 0x1 + + * Bypass control for pcs-pma interface. EQ supplies, main master supply an + * d ps for samp c2c + * (OFFSET, MASK, VALUE) (0XFD405038, 0x00000040U ,0x00000040U) + */ + PSU_Mask_Write(SERDES_L1_TM_ANA_BYP_15_OFFSET, + 0x00000040U, 0x00000040U); +/*##################################################################### */ + + /* + * Register : L1_TM_ANA_BYP_12 @ 0XFD40502C + + * Enable Bypass for <7> of TM_ANA_BYPS_12 + * PSU_SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG 0x1 + + * Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr ena + * ble controls + * (OFFSET, MASK, VALUE) (0XFD40502C, 0x00000040U ,0x00000040U) + */ + PSU_Mask_Write(SERDES_L1_TM_ANA_BYP_12_OFFSET, + 0x00000040U, 0x00000040U); +/*##################################################################### */ + + /* + * Register : L2_TM_RST_DLY @ 0XFD4099A4 + + * Delay apb reset by specified amount + * PSU_SERDES_L2_TM_RST_DLY_APB_RST_DLY 0xFF + + * reset delay for apb reset w.r.t pso of hsrx + * (OFFSET, MASK, VALUE) (0XFD4099A4, 0x000000FFU ,0x000000FFU) + */ + PSU_Mask_Write(SERDES_L2_TM_RST_DLY_OFFSET, + 0x000000FFU, 0x000000FFU); +/*##################################################################### */ + + /* + * Register : L2_TM_ANA_BYP_15 @ 0XFD409038 + + * Enable Bypass for <7> of TM_ANA_BYPS_15 + * PSU_SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE 0x1 + + * Bypass control for pcs-pma interface. EQ supplies, main master supply an + * d ps for samp c2c + * (OFFSET, MASK, VALUE) (0XFD409038, 0x00000040U ,0x00000040U) + */ + PSU_Mask_Write(SERDES_L2_TM_ANA_BYP_15_OFFSET, + 0x00000040U, 0x00000040U); +/*##################################################################### */ + + /* + * Register : L2_TM_ANA_BYP_12 @ 0XFD40902C + + * Enable Bypass for <7> of TM_ANA_BYPS_12 + * PSU_SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG 0x1 + + * Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr ena + * ble controls + * (OFFSET, MASK, VALUE) (0XFD40902C, 0x00000040U ,0x00000040U) + */ + PSU_Mask_Write(SERDES_L2_TM_ANA_BYP_12_OFFSET, + 0x00000040U, 0x00000040U); +/*##################################################################### */ + + /* + * Register : L3_TM_RST_DLY @ 0XFD40D9A4 + + * Delay apb reset by specified amount + * PSU_SERDES_L3_TM_RST_DLY_APB_RST_DLY 0xFF + + * reset delay for apb reset w.r.t pso of hsrx + * (OFFSET, MASK, VALUE) (0XFD40D9A4, 0x000000FFU ,0x000000FFU) + */ + PSU_Mask_Write(SERDES_L3_TM_RST_DLY_OFFSET, + 0x000000FFU, 0x000000FFU); +/*##################################################################### */ + + /* + * Register : L3_TM_ANA_BYP_15 @ 0XFD40D038 + + * Enable Bypass for <7> of TM_ANA_BYPS_15 + * PSU_SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE 0x1 + + * Bypass control for pcs-pma interface. EQ supplies, main master supply an + * d ps for samp c2c + * (OFFSET, MASK, VALUE) (0XFD40D038, 0x00000040U ,0x00000040U) + */ + PSU_Mask_Write(SERDES_L3_TM_ANA_BYP_15_OFFSET, + 0x00000040U, 0x00000040U); +/*##################################################################### */ + + /* + * Register : L3_TM_ANA_BYP_12 @ 0XFD40D02C + + * Enable Bypass for <7> of TM_ANA_BYPS_12 + * PSU_SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG 0x1 + + * Bypass control for pcs-pma interface. Hsrx supply, hsrx des, and cdr ena + * ble controls + * (OFFSET, MASK, VALUE) (0XFD40D02C, 0x00000040U ,0x00000040U) + */ + PSU_Mask_Write(SERDES_L3_TM_ANA_BYP_12_OFFSET, + 0x00000040U, 0x00000040U); +/*##################################################################### */ + + /* + * DISABLE FPL/FFL + */ + /* + * Register : L0_TM_MISC3 @ 0XFD4019AC + + * CDR fast phase lock control + * PSU_SERDES_L0_TM_MISC3_CDR_EN_FPL 0x0 + + * CDR fast frequency lock control + * PSU_SERDES_L0_TM_MISC3_CDR_EN_FFL 0x0 + + * debug bus selection bit, cdr fast phase and freq controls + * (OFFSET, MASK, VALUE) (0XFD4019AC, 0x00000003U ,0x00000000U) + */ + PSU_Mask_Write(SERDES_L0_TM_MISC3_OFFSET, 0x00000003U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : L1_TM_MISC3 @ 0XFD4059AC + + * CDR fast phase lock control + * PSU_SERDES_L1_TM_MISC3_CDR_EN_FPL 0x0 + + * CDR fast frequency lock control + * PSU_SERDES_L1_TM_MISC3_CDR_EN_FFL 0x0 + + * debug bus selection bit, cdr fast phase and freq controls + * (OFFSET, MASK, VALUE) (0XFD4059AC, 0x00000003U ,0x00000000U) + */ + PSU_Mask_Write(SERDES_L1_TM_MISC3_OFFSET, 0x00000003U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : L2_TM_MISC3 @ 0XFD4099AC + + * CDR fast phase lock control + * PSU_SERDES_L2_TM_MISC3_CDR_EN_FPL 0x0 + + * CDR fast frequency lock control + * PSU_SERDES_L2_TM_MISC3_CDR_EN_FFL 0x0 + + * debug bus selection bit, cdr fast phase and freq controls + * (OFFSET, MASK, VALUE) (0XFD4099AC, 0x00000003U ,0x00000000U) + */ + PSU_Mask_Write(SERDES_L2_TM_MISC3_OFFSET, 0x00000003U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : L3_TM_MISC3 @ 0XFD40D9AC + + * CDR fast phase lock control + * PSU_SERDES_L3_TM_MISC3_CDR_EN_FPL 0x0 + + * CDR fast frequency lock control + * PSU_SERDES_L3_TM_MISC3_CDR_EN_FFL 0x0 + + * debug bus selection bit, cdr fast phase and freq controls + * (OFFSET, MASK, VALUE) (0XFD40D9AC, 0x00000003U ,0x00000000U) + */ + PSU_Mask_Write(SERDES_L3_TM_MISC3_OFFSET, 0x00000003U, 0x00000000U); +/*##################################################################### */ + + /* + * DISABLE DYNAMIC OFFSET CALIBRATION + */ + /* + * Register : L0_TM_EQ11 @ 0XFD401978 + + * Force EQ offset correction algo off if not forced on + * PSU_SERDES_L0_TM_EQ11_FORCE_EQ_OFFS_OFF 0x1 + + * eq dynamic offset correction + * (OFFSET, MASK, VALUE) (0XFD401978, 0x00000010U ,0x00000010U) + */ + PSU_Mask_Write(SERDES_L0_TM_EQ11_OFFSET, 0x00000010U, 0x00000010U); +/*##################################################################### */ + + /* + * Register : L1_TM_EQ11 @ 0XFD405978 + + * Force EQ offset correction algo off if not forced on + * PSU_SERDES_L1_TM_EQ11_FORCE_EQ_OFFS_OFF 0x1 + + * eq dynamic offset correction + * (OFFSET, MASK, VALUE) (0XFD405978, 0x00000010U ,0x00000010U) + */ + PSU_Mask_Write(SERDES_L1_TM_EQ11_OFFSET, 0x00000010U, 0x00000010U); +/*##################################################################### */ + + /* + * Register : L2_TM_EQ11 @ 0XFD409978 + + * Force EQ offset correction algo off if not forced on + * PSU_SERDES_L2_TM_EQ11_FORCE_EQ_OFFS_OFF 0x1 + + * eq dynamic offset correction + * (OFFSET, MASK, VALUE) (0XFD409978, 0x00000010U ,0x00000010U) + */ + PSU_Mask_Write(SERDES_L2_TM_EQ11_OFFSET, 0x00000010U, 0x00000010U); +/*##################################################################### */ + + /* + * Register : L3_TM_EQ11 @ 0XFD40D978 + + * Force EQ offset correction algo off if not forced on + * PSU_SERDES_L3_TM_EQ11_FORCE_EQ_OFFS_OFF 0x1 + + * eq dynamic offset correction + * (OFFSET, MASK, VALUE) (0XFD40D978, 0x00000010U ,0x00000010U) + */ + PSU_Mask_Write(SERDES_L3_TM_EQ11_OFFSET, 0x00000010U, 0x00000010U); +/*##################################################################### */ + + /* + * DISABLE ECO FOR PCIE + */ + /* + * Register : eco_0 @ 0XFD3D001C + + * For future use + * PSU_SIOU_ECO_0_FIELD 0x1 + + * ECO Register for future use + * (OFFSET, MASK, VALUE) (0XFD3D001C, 0xFFFFFFFFU ,0x00000001U) + */ + PSU_Mask_Write(SIOU_ECO_0_OFFSET, 0xFFFFFFFFU, 0x00000001U); +/*##################################################################### */ + + /* + * GT LANE SETTINGS + */ + /* + * Register : ICM_CFG0 @ 0XFD410010 + + * Controls UPHY Lane 0 protocol configuration. 0 - PowerDown, 1 - PCIe .0, + * 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII0, 6 - Unused, 7 - Unused + * PSU_SERDES_ICM_CFG0_L0_ICM_CFG 1 + + * Controls UPHY Lane 1 protocol configuration. 0 - PowerDown, 1 - PCIe.1, + * 2 - Sata1, 3 - USB0, 4 - DP.0, 5 - SGMII1, 6 - Unused, 7 - Unused + * PSU_SERDES_ICM_CFG0_L1_ICM_CFG 4 + + * ICM Configuration Register 0 + * (OFFSET, MASK, VALUE) (0XFD410010, 0x00000077U ,0x00000041U) + */ + PSU_Mask_Write(SERDES_ICM_CFG0_OFFSET, 0x00000077U, 0x00000041U); +/*##################################################################### */ + + /* + * Register : ICM_CFG1 @ 0XFD410014 + + * Controls UPHY Lane 2 protocol configuration. 0 - PowerDown, 1 - PCIe.1, + * 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII2, 6 - Unused, 7 - Unused + * PSU_SERDES_ICM_CFG1_L2_ICM_CFG 3 + + * Controls UPHY Lane 3 protocol configuration. 0 - PowerDown, 1 - PCIe.3, + * 2 - Sata1, 3 - USB1, 4 - DP.0, 5 - SGMII3, 6 - Unused, 7 - Unused + * PSU_SERDES_ICM_CFG1_L3_ICM_CFG 2 + + * ICM Configuration Register 1 + * (OFFSET, MASK, VALUE) (0XFD410014, 0x00000077U ,0x00000023U) + */ + PSU_Mask_Write(SERDES_ICM_CFG1_OFFSET, 0x00000077U, 0x00000023U); +/*##################################################################### */ + + /* + * CHECKING PLL LOCK + */ + /* + * ENABLE SERIAL DATA MUX DEEMPH + */ + /* + * Register : L1_TXPMD_TM_45 @ 0XFD404CB4 + + * Enable/disable DP post2 path + * PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH 0x1 + + * Override enable/disable of DP post2 path + * PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH 0x1 + + * Override enable/disable of DP post1 path + * PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH 0x1 + + * Enable/disable DP main path + * PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH 0x1 + + * Override enable/disable of DP main path + * PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH 0x1 + + * Post or pre or main DP path selection + * (OFFSET, MASK, VALUE) (0XFD404CB4, 0x00000037U ,0x00000037U) + */ + PSU_Mask_Write(SERDES_L1_TXPMD_TM_45_OFFSET, + 0x00000037U, 0x00000037U); +/*##################################################################### */ + + /* + * Register : L1_TX_ANA_TM_118 @ 0XFD4041D8 + + * Test register force for enabling/disablign TX deemphasis bits <17:0> + * PSU_SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0 0x1 + + * Enable Override of TX deemphasis + * (OFFSET, MASK, VALUE) (0XFD4041D8, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L1_TX_ANA_TM_118_OFFSET, + 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * Register : L3_TX_ANA_TM_118 @ 0XFD40C1D8 + + * Test register force for enabling/disablign TX deemphasis bits <17:0> + * PSU_SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0 0x1 + + * Enable Override of TX deemphasis + * (OFFSET, MASK, VALUE) (0XFD40C1D8, 0x00000001U ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L3_TX_ANA_TM_118_OFFSET, + 0x00000001U, 0x00000001U); +/*##################################################################### */ + + /* + * CDR AND RX EQUALIZATION SETTINGS + */ + /* + * Register : L3_TM_CDR5 @ 0XFD40DC14 + + * FPHL FSM accumulate cycles + * PSU_SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES 0x7 + + * FFL Phase0 int gain aka 2ol SD update rate + * PSU_SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN 0x6 + + * Fast phase lock controls -- FSM accumulator cycle control and phase 0 in + * t gain control. + * (OFFSET, MASK, VALUE) (0XFD40DC14, 0x000000FFU ,0x000000E6U) + */ + PSU_Mask_Write(SERDES_L3_TM_CDR5_OFFSET, 0x000000FFU, 0x000000E6U); +/*##################################################################### */ + + /* + * Register : L3_TM_CDR16 @ 0XFD40DC40 + + * FFL Phase0 prop gain aka 1ol SD update rate + * PSU_SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN 0xC + + * Fast phase lock controls -- phase 0 prop gain + * (OFFSET, MASK, VALUE) (0XFD40DC40, 0x0000001FU ,0x0000000CU) + */ + PSU_Mask_Write(SERDES_L3_TM_CDR16_OFFSET, 0x0000001FU, 0x0000000CU); +/*##################################################################### */ + + /* + * Register : L3_TM_EQ0 @ 0XFD40D94C + + * EQ stg 2 controls BYPASSED + * PSU_SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP 1 + + * eq stg1 and stg2 controls + * (OFFSET, MASK, VALUE) (0XFD40D94C, 0x00000020U ,0x00000020U) + */ + PSU_Mask_Write(SERDES_L3_TM_EQ0_OFFSET, 0x00000020U, 0x00000020U); +/*##################################################################### */ + + /* + * Register : L3_TM_EQ1 @ 0XFD40D950 + + * EQ STG2 RL PROG + * PSU_SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG 0x2 + + * EQ stg 2 preamp mode val + * PSU_SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL 0x1 + + * eq stg1 and stg2 controls + * (OFFSET, MASK, VALUE) (0XFD40D950, 0x00000007U ,0x00000006U) + */ + PSU_Mask_Write(SERDES_L3_TM_EQ1_OFFSET, 0x00000007U, 0x00000006U); +/*##################################################################### */ + + /* + * GEM SERDES SETTINGS + */ + /* + * ENABLE PRE EMPHAIS AND VOLTAGE SWING + */ + /* + * Register : L1_TXPMD_TM_48 @ 0XFD404CC0 + + * Margining factor value + * PSU_SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR 0 + + * Margining factor + * (OFFSET, MASK, VALUE) (0XFD404CC0, 0x0000001FU ,0x00000000U) + */ + PSU_Mask_Write(SERDES_L1_TXPMD_TM_48_OFFSET, + 0x0000001FU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : L1_TX_ANA_TM_18 @ 0XFD404048 + + * pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-em + * phasis, Others: reserved + * PSU_SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0 0 + + * Override for PIPE TX de-emphasis + * (OFFSET, MASK, VALUE) (0XFD404048, 0x000000FFU ,0x00000000U) + */ + PSU_Mask_Write(SERDES_L1_TX_ANA_TM_18_OFFSET, + 0x000000FFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : L3_TX_ANA_TM_18 @ 0XFD40C048 + + * pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-em + * phasis, Others: reserved + * PSU_SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0 0x1 + + * Override for PIPE TX de-emphasis + * (OFFSET, MASK, VALUE) (0XFD40C048, 0x000000FFU ,0x00000001U) + */ + PSU_Mask_Write(SERDES_L3_TX_ANA_TM_18_OFFSET, + 0x000000FFU, 0x00000001U); +/*##################################################################### */ + + + return 1; } -unsigned long psu_resetin_init_data() { - // : PUTTING SERDES PERIPHERAL IN RESET - // : PUTTING USB0 IN RESET - /*Register : RST_LPD_TOP @ 0XFF5E023C

+unsigned long psu_resetout_init_data(void) +{ + /* + * TAKING SERDES PERIPHERAL OUT OF RESET RESET + */ + /* + * PUTTING USB0 IN RESET + */ + /* + * Register : RST_LPD_TOP @ 0XFF5E023C - USB 0 reset for control registers - PSU_CRL_APB_RST_LPD_TOP_USB0_APB_RESET 0X1 + * USB 0 reset for control registers + * PSU_CRL_APB_RST_LPD_TOP_USB0_APB_RESET 0X0 - USB 0 sleep circuit reset - PSU_CRL_APB_RST_LPD_TOP_USB0_HIBERRESET 0X1 + * Software control register for the LPD block. + * (OFFSET, MASK, VALUE) (0XFF5E023C, 0x00000400U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_TOP_OFFSET, 0x00000400U, 0x00000000U); +/*##################################################################### */ - USB 0 reset - PSU_CRL_APB_RST_LPD_TOP_USB0_CORERESET 0X1 + /* + * HIBERREST + */ + /* + * Register : RST_LPD_TOP @ 0XFF5E023C - Software control register for the LPD block. - (OFFSET, MASK, VALUE) (0XFF5E023C, 0x00000540U ,0x00000540U) - RegMask = (CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK | CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK | CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK | 0 ); + * USB 0 sleep circuit reset + * PSU_CRL_APB_RST_LPD_TOP_USB0_HIBERRESET 0X0 - RegVal = ((0x00000001U << CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT - | 0x00000001U << CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT - | 0x00000001U << CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RST_LPD_TOP_OFFSET ,0x00000540U ,0x00000540U); - /*############################################################################################################################ */ + * USB 0 reset + * PSU_CRL_APB_RST_LPD_TOP_USB0_CORERESET 0X0 - // : PUTTING GEM0 IN RESET - /*Register : RST_LPD_IOU0 @ 0XFF5E0230

+ * Software control register for the LPD block. + * (OFFSET, MASK, VALUE) (0XFF5E023C, 0x00000140U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_TOP_OFFSET, 0x00000140U, 0x00000000U); +/*##################################################################### */ - GEM 3 reset - PSU_CRL_APB_RST_LPD_IOU0_GEM3_RESET 0X1 + /* + * PUTTING GEM0 IN RESET + */ + /* + * Register : RST_LPD_IOU0 @ 0XFF5E0230 - Software controlled reset for the GEMs - (OFFSET, MASK, VALUE) (0XFF5E0230, 0x00000008U ,0x00000008U) - RegMask = (CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK | 0 ); + * GEM 3 reset + * PSU_CRL_APB_RST_LPD_IOU0_GEM3_RESET 0X0 - RegVal = ((0x00000001U << CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRL_APB_RST_LPD_IOU0_OFFSET ,0x00000008U ,0x00000008U); - /*############################################################################################################################ */ + * Software controlled reset for the GEMs + * (OFFSET, MASK, VALUE) (0XFF5E0230, 0x00000008U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_IOU0_OFFSET, + 0x00000008U, 0x00000000U); +/*##################################################################### */ - // : PUTTING SATA IN RESET - /*Register : RST_FPD_TOP @ 0XFD1A0100

+ /* + * PUTTING SATA IN RESET + */ + /* + * Register : sata_misc_ctrl @ 0XFD3D0100 - Sata block level reset - PSU_CRF_APB_RST_FPD_TOP_SATA_RESET 0X1 + * Sata PM clock control select + * PSU_SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL 0x3 - FPD Block level software controlled reset - (OFFSET, MASK, VALUE) (0XFD1A0100, 0x00000002U ,0x00000002U) - RegMask = (CRF_APB_RST_FPD_TOP_SATA_RESET_MASK | 0 ); + * Misc Contorls for SATA.This register may only be modified during bootup + * (while SATA block is disabled) + * (OFFSET, MASK, VALUE) (0XFD3D0100, 0x00000003U ,0x00000003U) + */ + PSU_Mask_Write(SIOU_SATA_MISC_CTRL_OFFSET, 0x00000003U, 0x00000003U); +/*##################################################################### */ - RegVal = ((0x00000001U << CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_RST_FPD_TOP_OFFSET ,0x00000002U ,0x00000002U); - /*############################################################################################################################ */ + /* + * Register : RST_FPD_TOP @ 0XFD1A0100 - // : PUTTING PCIE IN RESET - /*Register : RST_FPD_TOP @ 0XFD1A0100

+ * Sata block level reset + * PSU_CRF_APB_RST_FPD_TOP_SATA_RESET 0X0 - PCIE config reset - PSU_CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET 0X1 + * FPD Block level software controlled reset + * (OFFSET, MASK, VALUE) (0XFD1A0100, 0x00000002U ,0x00000000U) + */ + PSU_Mask_Write(CRF_APB_RST_FPD_TOP_OFFSET, 0x00000002U, 0x00000000U); +/*##################################################################### */ - PCIE control block level reset - PSU_CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET 0X1 + /* + * PUTTING PCIE CFG AND BRIDGE IN RESET + */ + /* + * Register : RST_FPD_TOP @ 0XFD1A0100 - PCIE bridge block level reset (AXI interface) - PSU_CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET 0X1 + * PCIE config reset + * PSU_CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET 0X0 - FPD Block level software controlled reset - (OFFSET, MASK, VALUE) (0XFD1A0100, 0x000E0000U ,0x000E0000U) - RegMask = (CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK | CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK | CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK | 0 ); + * PCIE bridge block level reset (AXI interface) + * PSU_CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET 0X0 - RegVal = ((0x00000001U << CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT - | 0x00000001U << CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT - | 0x00000001U << CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_RST_FPD_TOP_OFFSET ,0x000E0000U ,0x000E0000U); - /*############################################################################################################################ */ + * FPD Block level software controlled reset + * (OFFSET, MASK, VALUE) (0XFD1A0100, 0x000C0000U ,0x00000000U) + */ + PSU_Mask_Write(CRF_APB_RST_FPD_TOP_OFFSET, 0x000C0000U, 0x00000000U); +/*##################################################################### */ - // : PUTTING DP IN RESET - /*Register : DP_TX_PHY_POWER_DOWN @ 0XFD4A0238

+ /* + * PUTTING DP IN RESET + */ + /* + * Register : RST_FPD_TOP @ 0XFD1A0100 - Two bits per lane. When set to 11, moves the GT to power down mode. When set to 00, GT will be in active state. bits [1:0] - - ane0 Bits [3:2] - lane 1 - PSU_DP_DP_TX_PHY_POWER_DOWN_POWER_DWN 0XA + * Display Port block level reset (includes DPDMA) + * PSU_CRF_APB_RST_FPD_TOP_DP_RESET 0X0 - Control PHY Power down - (OFFSET, MASK, VALUE) (0XFD4A0238, 0x0000000FU ,0x0000000AU) - RegMask = (DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK | 0 ); + * FPD Block level software controlled reset + * (OFFSET, MASK, VALUE) (0XFD1A0100, 0x00010000U ,0x00000000U) + */ + PSU_Mask_Write(CRF_APB_RST_FPD_TOP_OFFSET, 0x00010000U, 0x00000000U); +/*##################################################################### */ - RegVal = ((0x0000000AU << DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DP_DP_TX_PHY_POWER_DOWN_OFFSET ,0x0000000FU ,0x0000000AU); - /*############################################################################################################################ */ + /* + * Register : DP_PHY_RESET @ 0XFD4A0200 - /*Register : DP_PHY_RESET @ 0XFD4A0200

+ * Set to '1' to hold the GT in reset. Clear to release. + * PSU_DP_DP_PHY_RESET_GT_RESET 0X0 - Set to '1' to hold the GT in reset. Clear to release. - PSU_DP_DP_PHY_RESET_GT_RESET 0X1 + * Reset the transmitter PHY. + * (OFFSET, MASK, VALUE) (0XFD4A0200, 0x00000002U ,0x00000000U) + */ + PSU_Mask_Write(DP_DP_PHY_RESET_OFFSET, 0x00000002U, 0x00000000U); +/*##################################################################### */ - Reset the transmitter PHY. - (OFFSET, MASK, VALUE) (0XFD4A0200, 0x00000002U ,0x00000002U) - RegMask = (DP_DP_PHY_RESET_GT_RESET_MASK | 0 ); + /* + * Register : DP_TX_PHY_POWER_DOWN @ 0XFD4A0238 - RegVal = ((0x00000001U << DP_DP_PHY_RESET_GT_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (DP_DP_PHY_RESET_OFFSET ,0x00000002U ,0x00000002U); - /*############################################################################################################################ */ + * Two bits per lane. When set to 11, moves the GT to power down mode. When + * set to 00, GT will be in active state. bits [1:0] - lane0 Bits [3:2] - + * lane 1 + * PSU_DP_DP_TX_PHY_POWER_DOWN_POWER_DWN 0X0 - /*Register : RST_FPD_TOP @ 0XFD1A0100

+ * Control PHY Power down + * (OFFSET, MASK, VALUE) (0XFD4A0238, 0x0000000FU ,0x00000000U) + */ + PSU_Mask_Write(DP_DP_TX_PHY_POWER_DOWN_OFFSET, + 0x0000000FU, 0x00000000U); +/*##################################################################### */ - Display Port block level reset (includes DPDMA) - PSU_CRF_APB_RST_FPD_TOP_DP_RESET 0X1 + /* + * USB0 GFLADJ + */ + /* + * Register : GUSB2PHYCFG @ 0XFE20C200 - FPD Block level software controlled reset - (OFFSET, MASK, VALUE) (0XFD1A0100, 0x00010000U ,0x00010000U) - RegMask = (CRF_APB_RST_FPD_TOP_DP_RESET_MASK | 0 ); + * USB 2.0 Turnaround Time (USBTrdTim) Sets the turnaround time in PHY cloc + * ks. Specifies the response time for a MAC request to the Packet FIFO Con + * troller (PFC) to fetch data from the DFIFO (SPRAM). The following are th + * e required values for the minimum SoC bus frequency of 60 MHz. USB turna + * round time is a critical certification criteria when using long cables a + * nd five hub levels. The required values for this field: - 4'h5: When the + * MAC interface is 16-bit UTMI+. - 4'h9: When the MAC interface is 8-bit + * UTMI+/ULPI. If SoC bus clock is less than 60 MHz, and USB turnaround tim + * e is not critical, this field can be set to a larger value. Note: This f + * ield is valid only in device mode. + * PSU_USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM 0x9 - RegVal = ((0x00000001U << CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (CRF_APB_RST_FPD_TOP_OFFSET ,0x00010000U ,0x00010000U); - /*############################################################################################################################ */ + * Transceiver Delay: Enables a delay between the assertion of the UTMI/ULP + * I Transceiver Select signal (for HS) and the assertion of the TxValid si + * gnal during a HS Chirp. When this bit is set to 1, a delay (of approxima + * tely 2.5 us) is introduced from the time when the Transceiver Select is + * set to 2'b00 (HS) to the time the TxValid is driven to 0 for sending the + * chirp-K. This delay is required for some UTMI/ULPI PHYs. Note: - If you + * enable the hibernation feature when the device core comes out of power- + * off, you must re-initialize this bit with the appropriate value because + * the core does not save and restore this bit value during hibernation. - + * This bit is valid only in device mode. + * PSU_USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY 0x0 + + * Enable utmi_sleep_n and utmi_l1_suspend_n (EnblSlpM) The application use + * s this bit to control utmi_sleep_n and utmi_l1_suspend_n assertion to th + * e PHY in the L1 state. - 1'b0: utmi_sleep_n and utmi_l1_suspend_n assert + * ion from the core is not transferred to the external PHY. - 1'b1: utmi_s + * leep_n and utmi_l1_suspend_n assertion from the core is transferred to t + * he external PHY. Note: This bit must be set high for Port0 if PHY is use + * d. Note: In Device mode - Before issuing any device endpoint command whe + * n operating in 2.0 speeds, disable this bit and enable it after the comm + * and completes. Without disabling this bit, if a command is issued when t + * he device is in L1 state and if mac2_clk (utmi_clk/ulpi_clk) is gated of + * f, the command will not get completed. + * PSU_USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM 0x0 + + * USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial Transceiver Select T + * he application uses this bit to select a high-speed PHY or a full-speed + * transceiver. - 1'b0: USB 2.0 high-speed UTMI+ or ULPI PHY. This bit is a + * lways 0, with Write Only access. - 1'b1: USB 1.1 full-speed serial trans + * ceiver. This bit is always 1, with Write Only access. If both interface + * types are selected in coreConsultant (that is, parameters' values are no + * t zero), the application uses this bit to select the active interface is + * active, with Read-Write bit access. Note: USB 1.1 full-serial transceiv + * er is not supported. This bit always reads as 1'b0. + * PSU_USB3_0_XHCI_GUSB2PHYCFG_PHYSEL 0x0 + + * Suspend USB2.0 HS/FS/LS PHY (SusPHY) When set, USB2.0 PHY enters Suspend + * mode if Suspend conditions are valid. For DRD/OTG configurations, it is + * recommended that this bit is set to 0 during coreConsultant configurati + * on. If it is set to 1, then the application must clear this bit after po + * wer-on reset. Application needs to set it to 1 after the core initializa + * tion completes. For all other configurations, this bit can be set to 1 d + * uring core configuration. Note: - In host mode, on reset, this bit is se + * t to 1. Software can override this bit after reset. - In device mode, be + * fore issuing any device endpoint command when operating in 2.0 speeds, d + * isable this bit and enable it after the command completes. If you issue + * a command without disabling this bit when the device is in L2 state and + * if mac2_clk (utmi_clk/ulpi_clk) is gated off, the command will not get c + * ompleted. + * PSU_USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20 0x1 + + * Full-Speed Serial Interface Select (FSIntf) The application uses this bi + * t to select a unidirectional or bidirectional USB 1.1 full-speed serial + * transceiver interface. - 1'b0: 6-pin unidirectional full-speed serial in + * terface. This bit is set to 0 with Read Only access. - 1'b1: 3-pin bidir + * ectional full-speed serial interface. This bit is set to 0 with Read Onl + * y access. Note: USB 1.1 full-speed serial interface is not supported. Th + * is bit always reads as 1'b0. + * PSU_USB3_0_XHCI_GUSB2PHYCFG_FSINTF 0x0 + + * ULPI or UTMI+ Select (ULPI_UTMI_Sel) The application uses this bit to se + * lect a UTMI+ or ULPI Interface. - 1'b0: UTMI+ Interface - 1'b1: ULPI Int + * erface This bit is writable only if UTMI+ and ULPI is specified for High + * -Speed PHY Interface(s) in coreConsultant configuration (DWC_USB3_HSPHY_ + * INTERFACE = 3). Otherwise, this bit is read-only and the value depends o + * n the interface selected through DWC_USB3_HSPHY_INTERFACE. + * PSU_USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL 0x1 + + * PHY Interface (PHYIf) If UTMI+ is selected, the application uses this bi + * t to configure the core to support a UTMI+ PHY with an 8- or 16-bit inte + * rface. - 1'b0: 8 bits - 1'b1: 16 bits ULPI Mode: 1'b0 Note: - All the en + * abled 2.0 ports must have the same clock frequency as Port0 clock freque + * ncy (utmi_clk[0]). - The UTMI 8-bit and 16-bit modes cannot be used toge + * ther for different ports at the same time (that is, all the ports must b + * e in 8-bit mode, or all of them must be in 16-bit mode, at a time). - If + * any of the USB 2.0 ports is selected as ULPI port for operation, then a + * ll the USB 2.0 ports must be operating at 60 MHz. + * PSU_USB3_0_XHCI_GUSB2PHYCFG_PHYIF 0x0 + + * HS/FS Timeout Calibration (TOutCal) The number of PHY clocks, as indicat + * ed by the application in this field, is multiplied by a bit-time factor; + * this factor is added to the high-speed/full-speed interpacket timeout d + * uration in the core to account for additional delays introduced by the P + * HY. This may be required, since the delay introduced by the PHY in gener + * ating the linestate condition may vary among PHYs. The USB standard time + * out value for high-speed operation is 736 to 816 (inclusive) bit times. + * The USB standard timeout value for full-speed operation is 16 to 18 (inc + * lusive) bit times. The application must program this field based on the + * speed of connection. The number of bit times added per PHY clock are: Hi + * gh-speed operation: - One 30-MHz PHY clock = 16 bit times - One 60-MHz P + * HY clock = 8 bit times Full-speed operation: - One 30-MHz PHY clock = 0. + * 4 bit times - One 60-MHz PHY clock = 0.2 bit times - One 48-MHz PHY cloc + * k = 0.25 bit times + * PSU_USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL 0x7 + + * ULPI External VBUS Drive (ULPIExtVbusDrv) Selects supply source to drive + * 5V on VBUS, in the ULPI PHY. - 1'b0: PHY drives VBUS with internal char + * ge pump (default). - 1'b1: PHY drives VBUS with an external supply. (Onl + * y when RTL parameter DWC_USB3_HSPHY_INTERFACE = 2 or 3) + * PSU_USB3_0_XHCI_GUSB2PHYCFG_ULPIEXTVBUSDRV 0x1 + + * Global USB2 PHY Configuration Register The application must program this + * register before starting any transactions on either the SoC bus or the + * USB. In Device-only configurations, only one register is needed. In Host + * mode, per-port registers are implemented. + * (OFFSET, MASK, VALUE) (0XFE20C200, 0x00023FFFU ,0x00022457U) + */ + PSU_Mask_Write(USB3_0_XHCI_GUSB2PHYCFG_OFFSET, + 0x00023FFFU, 0x00022457U); +/*##################################################################### */ + + /* + * Register : GFLADJ @ 0XFE20C630 + + * This field indicates the frame length adjustment to be applied when SOF/ + * ITP counter is running on the ref_clk. This register value is used to ad + * just the ITP interval when GCTL[SOFITPSYNC] is set to '1'; SOF and ITP i + * nterval when GLADJ.GFLADJ_REFCLK_LPM_SEL is set to '1'. This field must + * be programmed to a non-zero value only if GFLADJ_REFCLK_LPM_SEL is set t + * o '1' or GCTL.SOFITPSYNC is set to '1'. The value is derived as follows: + * FLADJ_REF_CLK_FLADJ=((125000/ref_clk_period_integer)-(125000/ref_clk_pe + * riod)) * ref_clk_period where - the ref_clk_period_integer is the intege + * r value of the ref_clk period got by truncating the decimal (fractional) + * value that is programmed in the GUCTL.REF_CLK_PERIOD field. - the ref_c + * lk_period is the ref_clk period including the fractional value. Examples + * : If the ref_clk is 24 MHz then - GUCTL.REF_CLK_PERIOD = 41 - GFLADJ.GLA + * DJ_REFCLK_FLADJ = ((125000/41)-(125000/41.6666))*41.6666 = 2032 (ignorin + * g the fractional value) If the ref_clk is 48 MHz then - GUCTL.REF_CLK_PE + * RIOD = 20 - GFLADJ.GLADJ_REFCLK_FLADJ = ((125000/20)-(125000/20.8333))*2 + * 0.8333 = 5208 (ignoring the fractional value) + * PSU_USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ 0x0 + + * Global Frame Length Adjustment Register This register provides options f + * or the software to control the core behavior with respect to SOF (Start + * of Frame) and ITP (Isochronous Timestamp Packet) timers and frame timer + * functionality. It provides an option to override the fladj_30mhz_reg sid + * eband signal. In addition, it enables running SOF or ITP frame timer cou + * nters completely from the ref_clk. This facilitates hardware LPM in host + * mode with the SOF or ITP counters being run from the ref_clk signal. + * (OFFSET, MASK, VALUE) (0XFE20C630, 0x003FFF00U ,0x00000000U) + */ + PSU_Mask_Write(USB3_0_XHCI_GFLADJ_OFFSET, 0x003FFF00U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : GUCTL1 @ 0XFE20C11C + + * When this bit is set to '0', termsel, xcvrsel will become 0 during end o + * f resume while the opmode will become 0 once controller completes end of + * resume and enters U0 state (2 separate commandswill be issued). When th + * is bit is set to '1', all the termsel, xcvrsel, opmode becomes 0 during + * end of resume itself (only 1 command will be issued) + * PSU_USB3_0_XHCI_GUCTL1_RESUME_TERMSEL_XCVRSEL_UNIFY 0x1 + + * Reserved + * PSU_USB3_0_XHCI_GUCTL1_RESERVED_9 0x1 + + * Global User Control Register 1 + * (OFFSET, MASK, VALUE) (0XFE20C11C, 0x00000600U ,0x00000600U) + */ + PSU_Mask_Write(USB3_0_XHCI_GUCTL1_OFFSET, 0x00000600U, 0x00000600U); +/*##################################################################### */ + + /* + * Register : GUCTL @ 0XFE20C12C + + * Host IN Auto Retry (USBHstInAutoRetryEn) When set, this field enables th + * e Auto Retry feature. For IN transfers (non-isochronous) that encounter + * data packets with CRC errors or internal overrun scenarios, the auto ret + * ry feature causes the Host core to reply to the device with a non-termin + * ating retry ACK (that is, an ACK transaction packet with Retry = 1 and N + * umP != 0). If the Auto Retry feature is disabled (default), the core wil + * l respond with a terminating retry ACK (that is, an ACK transaction pack + * et with Retry = 1 and NumP = 0). - 1'b0: Auto Retry Disabled - 1'b1: Aut + * o Retry Enabled Note: This bit is also applicable to the device mode. + * PSU_USB3_0_XHCI_GUCTL_USBHSTINAUTORETRYEN 0x1 + + * Global User Control Register: This register provides a few options for t + * he software to control the core behavior in the Host mode. Most of the o + * ptions are used to improve host inter-operability with different devices + * . + * (OFFSET, MASK, VALUE) (0XFE20C12C, 0x00004000U ,0x00004000U) + */ + PSU_Mask_Write(USB3_0_XHCI_GUCTL_OFFSET, 0x00004000U, 0x00004000U); +/*##################################################################### */ + + /* + * UPDATING TWO PCIE REGISTERS DEFAULT VALUES, AS THESE REGISTERS HAVE INCO + * RRECT RESET VALUES IN SILICON. + */ + /* + * Register : ATTR_25 @ 0XFD480064 + + * If TRUE Completion Timeout Disable is supported. This is required to be + * TRUE for Endpoint and either setting allowed for Root ports. Drives Devi + * ce Capability 2 [4]; EP=0x0001; RP=0x0001 + * PSU_PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED 0X1 + + * ATTR_25 + * (OFFSET, MASK, VALUE) (0XFD480064, 0x00000200U ,0x00000200U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_25_OFFSET, 0x00000200U, 0x00000200U); +/*##################################################################### */ + + /* + * PCIE SETTINGS + */ + /* + * Register : ATTR_7 @ 0XFD48001C + + * Specifies mask/settings for Base Address Register (BAR) 0. If BAR is not + * to be implemented, set to 32'h00000000. Bits are defined as follows: Me + * mory Space BAR [0] = Mem Space Indicator (set to 0) [2:1] = Type field ( + * 10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask + * for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to 1, w + * here 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63: + * n bits of \'7bBAR1,BAR0\'7d to 1. IO Space BAR 0] = IO Space Indicator ( + * set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of B + * AR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; + * EP=0x0004; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_7_ATTR_BAR0 0x0 + + * ATTR_7 + * (OFFSET, MASK, VALUE) (0XFD48001C, 0x0000FFFFU ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_7_OFFSET, 0x0000FFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_8 @ 0XFD480020 + + * Specifies mask/settings for Base Address Register (BAR) 0. If BAR is not + * to be implemented, set to 32'h00000000. Bits are defined as follows: Me + * mory Space BAR [0] = Mem Space Indicator (set to 0) [2:1] = Type field ( + * 10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask + * for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to 1, w + * here 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63: + * n bits of \'7bBAR1,BAR0\'7d to 1. IO Space BAR 0] = IO Space Indicator ( + * set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of B + * AR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; + * EP=0xFFF0; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_8_ATTR_BAR0 0x0 + + * ATTR_8 + * (OFFSET, MASK, VALUE) (0XFD480020, 0x0000FFFFU ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_8_OFFSET, 0x0000FFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_9 @ 0XFD480024 + + * Specifies mask/settings for Base Address Register (BAR) 1 if BAR0 is a 3 + * 2-bit BAR, or the upper bits of \'7bBAR1,BAR0\'7d if BAR0 is a 64-bit BA + * R. If BAR is not to be implemented, set to 32'h00000000. See BAR0 descri + * ption if this functions as the upper bits of a 64-bit BAR. Bits are defi + * ned as follows: Memory Space BAR (not upper bits of BAR0) [0] = Mem Spac + * e Indicator (set to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) + * [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if + * 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size + * in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR2,BAR1\'7d t + * o 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set + * to 0) [31:2] = Mask for writable bits of BAR; set uppermost 31:n bits t + * o 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_9_ATTR_BAR1 0x0 + + * ATTR_9 + * (OFFSET, MASK, VALUE) (0XFD480024, 0x0000FFFFU ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_9_OFFSET, 0x0000FFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_10 @ 0XFD480028 + + * Specifies mask/settings for Base Address Register (BAR) 1 if BAR0 is a 3 + * 2-bit BAR, or the upper bits of \'7bBAR1,BAR0\'7d if BAR0 is a 64-bit BA + * R. If BAR is not to be implemented, set to 32'h00000000. See BAR0 descri + * ption if this functions as the upper bits of a 64-bit BAR. Bits are defi + * ned as follows: Memory Space BAR (not upper bits of BAR0) [0] = Mem Spac + * e Indicator (set to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) + * [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if + * 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size + * in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR2,BAR1\'7d t + * o 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set + * to 0) [31:2] = Mask for writable bits of BAR; set uppermost 31:n bits t + * o 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_10_ATTR_BAR1 0x0 + + * ATTR_10 + * (OFFSET, MASK, VALUE) (0XFD480028, 0x0000FFFFU ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_10_OFFSET, 0x0000FFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_11 @ 0XFD48002C + + * For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 2 if BAR1 is a 32-bit BAR, or the upper bits of \'7bBAR2,BAR1\'7d if BA + * R1 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR1 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root: This must be set to 00FF_FFF + * F. For an endpoint, bits are defined as follows: Memory Space BAR (not u + * pper bits of BAR1) [0] = Mem Space Indicator (set to 0) [2:1] = Type fie + * ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = M + * ask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to + * 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost + * 63:n bits of \'7bBAR3,BAR2\'7d to 1. IO Space BAR 0] = IO Space Indicat + * or (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits + * of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in byt + * es.; EP=0x0004; RP=0xFFFF + * PSU_PCIE_ATTRIB_ATTR_11_ATTR_BAR2 0xFFFF + + * ATTR_11 + * (OFFSET, MASK, VALUE) (0XFD48002C, 0x0000FFFFU ,0x0000FFFFU) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_11_OFFSET, 0x0000FFFFU, 0x0000FFFFU); +/*##################################################################### */ + + /* + * Register : ATTR_12 @ 0XFD480030 + + * For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 2 if BAR1 is a 32-bit BAR, or the upper bits of \'7bBAR2,BAR1\'7d if BA + * R1 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR1 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root: This must be set to 00FF_FFF + * F. For an endpoint, bits are defined as follows: Memory Space BAR (not u + * pper bits of BAR1) [0] = Mem Space Indicator (set to 0) [2:1] = Type fie + * ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = M + * ask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to + * 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost + * 63:n bits of \'7bBAR3,BAR2\'7d to 1. IO Space BAR 0] = IO Space Indicat + * or (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits + * of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in byt + * es.; EP=0xFFF0; RP=0x00FF + * PSU_PCIE_ATTRIB_ATTR_12_ATTR_BAR2 0xFF + + * ATTR_12 + * (OFFSET, MASK, VALUE) (0XFD480030, 0x0000FFFFU ,0x000000FFU) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_12_OFFSET, 0x0000FFFFU, 0x000000FFU); +/*##################################################################### */ + + /* + * Register : ATTR_13 @ 0XFD480034 + + * For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 3 if BAR2 is a 32-bit BAR, or the upper bits of \'7bBAR3,BAR2\'7d if BA + * R2 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR2 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root, this must be set to: FFFF_00 + * 00 = IO Limit/Base Registers not implemented FFFF_F0F0 = IO Limit/Base R + * egisters use 16-bit decode FFFF_F1F1 = IO Limit/Base Registers use 32-bi + * t decode For an endpoint, bits are defined as follows: Memory Space BAR + * (not upper bits of BAR2) [0] = Mem Space Indicator (set to 0) [2:1] = Ty + * pe field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31: + * 4] = Mask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bi + * ts to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set upp + * ermost 63:n bits of \'7bBAR4,BAR3\'7d to 1. IO Space BAR 0] = IO Space I + * ndicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable + * bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size + * in bytes.; EP=0xFFFF; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_13_ATTR_BAR3 0x0 + + * ATTR_13 + * (OFFSET, MASK, VALUE) (0XFD480034, 0x0000FFFFU ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_13_OFFSET, 0x0000FFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_14 @ 0XFD480038 + + * For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 3 if BAR2 is a 32-bit BAR, or the upper bits of \'7bBAR3,BAR2\'7d if BA + * R2 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR2 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root, this must be set to: FFFF_00 + * 00 = IO Limit/Base Registers not implemented FFFF_F0F0 = IO Limit/Base R + * egisters use 16-bit decode FFFF_F1F1 = IO Limit/Base Registers use 32-bi + * t decode For an endpoint, bits are defined as follows: Memory Space BAR + * (not upper bits of BAR2) [0] = Mem Space Indicator (set to 0) [2:1] = Ty + * pe field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31: + * 4] = Mask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bi + * ts to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set upp + * ermost 63:n bits of \'7bBAR4,BAR3\'7d to 1. IO Space BAR 0] = IO Space I + * ndicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable + * bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size + * in bytes.; EP=0xFFFF; RP=0xFFFF + * PSU_PCIE_ATTRIB_ATTR_14_ATTR_BAR3 0xFFFF + + * ATTR_14 + * (OFFSET, MASK, VALUE) (0XFD480038, 0x0000FFFFU ,0x0000FFFFU) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_14_OFFSET, 0x0000FFFFU, 0x0000FFFFU); +/*##################################################################### */ + + /* + * Register : ATTR_15 @ 0XFD48003C + + * For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 4 if BAR3 is a 32-bit BAR, or the upper bits of \'7bBAR4,BAR3\'7d if BA + * R3 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR3 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root: This must be set to FFF0_FFF + * 0. For an endpoint, bits are defined as follows: Memory Space BAR (not u + * pper bits of BAR3) [0] = Mem Space Indicator (set to 0) [2:1] = Type fie + * ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = M + * ask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to + * 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost + * 63:n bits of \'7bBAR5,BAR4\'7d to 1. IO Space BAR 0] = IO Space Indicat + * or (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits + * of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in byt + * es.; EP=0x0004; RP=0xFFF0 + * PSU_PCIE_ATTRIB_ATTR_15_ATTR_BAR4 0xFFF0 + + * ATTR_15 + * (OFFSET, MASK, VALUE) (0XFD48003C, 0x0000FFFFU ,0x0000FFF0U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_15_OFFSET, 0x0000FFFFU, 0x0000FFF0U); +/*##################################################################### */ + + /* + * Register : ATTR_16 @ 0XFD480040 + + * For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 4 if BAR3 is a 32-bit BAR, or the upper bits of \'7bBAR4,BAR3\'7d if BA + * R3 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR3 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root: This must be set to FFF0_FFF + * 0. For an endpoint, bits are defined as follows: Memory Space BAR (not u + * pper bits of BAR3) [0] = Mem Space Indicator (set to 0) [2:1] = Type fie + * ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = M + * ask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to + * 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost + * 63:n bits of \'7bBAR5,BAR4\'7d to 1. IO Space BAR 0] = IO Space Indicat + * or (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits + * of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in byt + * es.; EP=0xFFF0; RP=0xFFF0 + * PSU_PCIE_ATTRIB_ATTR_16_ATTR_BAR4 0xFFF0 + + * ATTR_16 + * (OFFSET, MASK, VALUE) (0XFD480040, 0x0000FFFFU ,0x0000FFF0U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_16_OFFSET, 0x0000FFFFU, 0x0000FFF0U); +/*##################################################################### */ + + /* + * Register : ATTR_17 @ 0XFD480044 + + * For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 5 if BAR4 is a 32-bit BAR, or the upper bits of \'7bBAR5,BAR4\'7d if BA + * R4 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR4 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root, this must be set to: 0000_00 + * 00 = Prefetchable Memory Limit/Base Registers not implemented FFF0_FFF0 + * = 32-bit Prefetchable Memory Limit/Base implemented FFF1_FFF1 = 64-bit P + * refetchable Memory Limit/Base implemented For an endpoint, bits are defi + * ned as follows: Memory Space BAR (not upper bits of BAR4) [0] = Mem Spac + * e Indicator (set to 0) [2:1] = Type field (00 for 32-bit; BAR5 cannot be + * lower part of a 64-bit BAR) [3] = Prefetchable (0 or 1) [31:4] = Mask f + * or writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=memory + * aperture size in bytes. IO Space BAR 0] = IO Space Indicator (set to 1) + * [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set up + * permost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF + * ; RP=0xFFF1 + * PSU_PCIE_ATTRIB_ATTR_17_ATTR_BAR5 0xFFF1 + + * ATTR_17 + * (OFFSET, MASK, VALUE) (0XFD480044, 0x0000FFFFU ,0x0000FFF1U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_17_OFFSET, 0x0000FFFFU, 0x0000FFF1U); +/*##################################################################### */ + + /* + * Register : ATTR_18 @ 0XFD480048 + + * For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 5 if BAR4 is a 32-bit BAR, or the upper bits of \'7bBAR5,BAR4\'7d if BA + * R4 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR4 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root, this must be set to: 0000_00 + * 00 = Prefetchable Memory Limit/Base Registers not implemented FFF0_FFF0 + * = 32-bit Prefetchable Memory Limit/Base implemented FFF1_FFF1 = 64-bit P + * refetchable Memory Limit/Base implemented For an endpoint, bits are defi + * ned as follows: Memory Space BAR (not upper bits of BAR4) [0] = Mem Spac + * e Indicator (set to 0) [2:1] = Type field (00 for 32-bit; BAR5 cannot be + * lower part of a 64-bit BAR) [3] = Prefetchable (0 or 1) [31:4] = Mask f + * or writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=memory + * aperture size in bytes. IO Space BAR 0] = IO Space Indicator (set to 1) + * [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set up + * permost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF + * ; RP=0xFFF1 + * PSU_PCIE_ATTRIB_ATTR_18_ATTR_BAR5 0xFFF1 + + * ATTR_18 + * (OFFSET, MASK, VALUE) (0XFD480048, 0x0000FFFFU ,0x0000FFF1U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_18_OFFSET, 0x0000FFFFU, 0x0000FFF1U); +/*##################################################################### */ + + /* + * Register : ATTR_27 @ 0XFD48006C + + * Specifies maximum payload supported. Valid settings are: 0- 128 bytes, 1 + * - 256 bytes, 2- 512 bytes, 3- 1024 bytes. Transferred to the Device Capa + * bilities register. The values: 4-2048 bytes, 5- 4096 bytes are not suppo + * rted; EP=0x0001; RP=0x0001 + * PSU_PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED 1 + + * Endpoint L1 Acceptable Latency. Records the latency that the endpoint ca + * n withstand on transitions from L1 state to L0 (if L1 state supported). + * Valid settings are: 0h less than 1us, 1h 1 to 2us, 2h 2 to 4us, 3h 4 to + * 8us, 4h 8 to 16us, 5h 16 to 32us, 6h 32 to 64us, 7h more than 64us. For + * Endpoints only. Must be 0h for other devices.; EP=0x0007; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY 0x0 + + * ATTR_27 + * (OFFSET, MASK, VALUE) (0XFD48006C, 0x00000738U ,0x00000100U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_27_OFFSET, 0x00000738U, 0x00000100U); +/*##################################################################### */ + + /* + * Register : ATTR_50 @ 0XFD4800C8 + + * Identifies the type of device/port as follows: 0000b PCI Express Endpoin + * t device, 0001b Legacy PCI Express Endpoint device, 0100b Root Port of P + * CI Express Root Complex, 0101b Upstream Port of PCI Express Switch, 0110 + * b Downstream Port of PCI Express Switch, 0111b PCIE Express to PCI/PCI-X + * Bridge, 1000b PCI/PCI-X to PCI Express Bridge. Transferred to PCI Expre + * ss Capabilities register. Must be consistent with IS_SWITCH and UPSTREAM + * _FACING settings.; EP=0x0000; RP=0x0004 + * PSU_PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE 4 + + * PCIe Capability's Next Capability Offset pointer to the next item in the + * capabilities list, or 00h if this is the final capability.; EP=0x009C; + * RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR 0 + + * ATTR_50 + * (OFFSET, MASK, VALUE) (0XFD4800C8, 0x0000FFF0U ,0x00000040U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_50_OFFSET, 0x0000FFF0U, 0x00000040U); +/*##################################################################### */ + + /* + * Register : ATTR_105 @ 0XFD4801A4 + + * Number of credits that should be advertised for Completion data received + * on Virtual Channel 0. The bytes advertised must be less than or equal t + * o the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0172; RP=0x00CD + * PSU_PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD 0xCD + + * ATTR_105 + * (OFFSET, MASK, VALUE) (0XFD4801A4, 0x000007FFU ,0x000000CDU) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_105_OFFSET, + 0x000007FFU, 0x000000CDU); +/*##################################################################### */ + + /* + * Register : ATTR_106 @ 0XFD4801A8 + + * Number of credits that should be advertised for Completion headers recei + * ved on Virtual Channel 0. The sum of the posted, non posted, and complet + * ion header credits must be <= 80; EP=0x0048; RP=0x0024 + * PSU_PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH 0x24 + + * Number of credits that should be advertised for Non-Posted headers recei + * ved on Virtual Channel 0. The number of non posted data credits advertis + * ed by the block is equal to the number of non posted header credits. The + * sum of the posted, non posted, and completion header credits must be <= + * 80; EP=0x0004; RP=0x000C + * PSU_PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH 0xC + + * ATTR_106 + * (OFFSET, MASK, VALUE) (0XFD4801A8, 0x00003FFFU ,0x00000624U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_106_OFFSET, + 0x00003FFFU, 0x00000624U); +/*##################################################################### */ + + /* + * Register : ATTR_107 @ 0XFD4801AC + + * Number of credits that should be advertised for Non-Posted data received + * on Virtual Channel 0. The number of non posted data credits advertised + * by the block is equal to two times the number of non posted header credi + * ts if atomic operations are supported or is equal to the number of non p + * osted header credits if atomic operations are not supported. The bytes a + * dvertised must be less than or equal to the bram bytes available. See VC + * 0_RX_RAM_LIMIT; EP=0x0008; RP=0x0018 + * PSU_PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD 0x18 + + * ATTR_107 + * (OFFSET, MASK, VALUE) (0XFD4801AC, 0x000007FFU ,0x00000018U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_107_OFFSET, + 0x000007FFU, 0x00000018U); +/*##################################################################### */ + + /* + * Register : ATTR_108 @ 0XFD4801B0 + + * Number of credits that should be advertised for Posted data received on + * Virtual Channel 0. The bytes advertised must be less than or equal to th + * e bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0020; RP=0x00B5 + * PSU_PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD 0xB5 + + * ATTR_108 + * (OFFSET, MASK, VALUE) (0XFD4801B0, 0x000007FFU ,0x000000B5U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_108_OFFSET, + 0x000007FFU, 0x000000B5U); +/*##################################################################### */ + + /* + * Register : ATTR_109 @ 0XFD4801B4 + + * Not currently in use. Invert ECRC generated by block when trn_tecrc_gen_ + * n and trn_terrfwd_n are asserted.; EP=0x0000; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV 0x0 + + * Enables td bit clear and ECRC trim on received TLP's FALSE == don't trim + * TRUE == trim.; EP=0x0001; RP=0x0001 + * PSU_PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM 0x1 + + * Enables ECRC check on received TLP's 0 == don't check 1 == always check + * 3 == check if enabled by ECRC check enable bit of AER cap structure; EP= + * 0x0003; RP=0x0003 + * PSU_PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK 0x3 + + * Index of last packet buffer used by TX TLM (i.e. number of buffers - 1). + * Calculated from max payload size supported and the number of brams conf + * igured for transmit; EP=0x001C; RP=0x001C + * PSU_PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET 0x1c + + * Number of credits that should be advertised for Posted headers received + * on Virtual Channel 0. The sum of the posted, non posted, and completion + * header credits must be <= 80; EP=0x0004; RP=0x0020 + * PSU_PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH 0x20 + + * ATTR_109 + * (OFFSET, MASK, VALUE) (0XFD4801B4, 0x0000FFFFU ,0x00007E20U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_109_OFFSET, + 0x0000FFFFU, 0x00007E20U); +/*##################################################################### */ + + /* + * Register : ATTR_34 @ 0XFD480088 + + * Specifies values to be transferred to Header Type register. Bit 7 should + * be set to '0' indicating single-function device. Bit 0 identifies heade + * r as Type 0 or Type 1, with '0' indicating a Type 0 header.; EP=0x0000; + * RP=0x0001 + * PSU_PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE 0x1 + + * ATTR_34 + * (OFFSET, MASK, VALUE) (0XFD480088, 0x000000FFU ,0x00000001U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_34_OFFSET, 0x000000FFU, 0x00000001U); +/*##################################################################### */ + + /* + * Register : ATTR_53 @ 0XFD4800D4 + + * PM Capability's Next Capability Offset pointer to the next item in the c + * apabilities list, or 00h if this is the final capability.; EP=0x0048; RP + * =0x0060 + * PSU_PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR 0x60 + + * ATTR_53 + * (OFFSET, MASK, VALUE) (0XFD4800D4, 0x000000FFU ,0x00000060U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_53_OFFSET, 0x000000FFU, 0x00000060U); +/*##################################################################### */ + + /* + * Register : ATTR_41 @ 0XFD4800A4 + + * MSI Per-Vector Masking Capable. The value is transferred to the MSI Cont + * rol Register[8]. When set, adds Mask and Pending Dword to Cap structure; + * EP=0x0000; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE 0x0 + + * Indicates that the MSI structures exists. If this is FALSE, then the MSI + * structure cannot be accessed via either the link or the management port + * .; EP=0x0001; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON 0 + + * MSI Capability's Next Capability Offset pointer to the next item in the + * capabilities list, or 00h if this is the final capability.; EP=0x0060; R + * P=0x0000 + * PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR 0x0 + + * Indicates that the MSI structures exists. If this is FALSE, then the MSI + * structure cannot be accessed via either the link or the management port + * .; EP=0x0001; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON 0 + + * ATTR_41 + * (OFFSET, MASK, VALUE) (0XFD4800A4, 0x000003FFU ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_41_OFFSET, 0x000003FFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_97 @ 0XFD480184 + + * Maximum Link Width. Valid settings are: 000001b x1, 000010b x2, 000100b + * x4, 001000b x8.; EP=0x0004; RP=0x0004 + * PSU_PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH 0x1 + + * Used by LTSSM to set Maximum Link Width. Valid settings are: 000001b [x1 + * ], 000010b [x2], 000100b [x4], 001000b [x8].; EP=0x0004; RP=0x0004 + * PSU_PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH 0x1 + + * ATTR_97 + * (OFFSET, MASK, VALUE) (0XFD480184, 0x00000FFFU ,0x00000041U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_97_OFFSET, 0x00000FFFU, 0x00000041U); +/*##################################################################### */ + + /* + * Register : ATTR_100 @ 0XFD480190 + + * TRUE specifies upstream-facing port. FALSE specifies downstream-facing p + * ort.; EP=0x0001; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING 0x0 + + * ATTR_100 + * (OFFSET, MASK, VALUE) (0XFD480190, 0x00000040U ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_100_OFFSET, + 0x00000040U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_101 @ 0XFD480194 + + * Enable the routing of message TLPs to the user through the TRN RX interf + * ace. A bit value of 1 enables routing of the message TLP to the user. Me + * ssages are always decoded by the message decoder. Bit 0 - ERR COR, Bit 1 + * - ERR NONFATAL, Bit 2 - ERR FATAL, Bit 3 - INTA Bit 4 - INTB, Bit 5 - I + * NTC, Bit 6 - INTD, Bit 7 PM_PME, Bit 8 - PME_TO_ACK, Bit 9 - unlock, Bit + * 10 PME_Turn_Off; EP=0x0000; RP=0x07FF + * PSU_PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE 0x7FF + + * Disable BAR filtering. Does not change the behavior of the bar hit outpu + * ts; EP=0x0000; RP=0x0001 + * PSU_PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING 0x1 + + * ATTR_101 + * (OFFSET, MASK, VALUE) (0XFD480194, 0x0000FFE2U ,0x0000FFE2U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_101_OFFSET, + 0x0000FFE2U, 0x0000FFE2U); +/*##################################################################### */ + + /* + * Register : ATTR_37 @ 0XFD480094 + + * Link Bandwidth notification capability. Indicates support for the link b + * andwidth notification status and interrupt mechanism. Required for Root. + * ; EP=0x0000; RP=0x0001 + * PSU_PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP 0x1 + + * Sets the ASPM Optionality Compliance bit, to comply with the 2.1 ASPM Op + * tionality ECN. Transferred to the Link Capabilities register.; EP=0x0001 + * ; RP=0x0001 + * PSU_PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY 0x1 + + * ATTR_37 + * (OFFSET, MASK, VALUE) (0XFD480094, 0x00004200U ,0x00004200U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_37_OFFSET, 0x00004200U, 0x00004200U); +/*##################################################################### */ + + /* + * Register : ATTR_93 @ 0XFD480174 + + * Enables the Replay Timer to use the user-defined LL_REPLAY_TIMEOUT value + * (or combined with the built-in value, depending on LL_REPLAY_TIMEOUT_FU + * NC). If FALSE, the built-in value is used.; EP=0x0000; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN 0x1 + + * Sets a user-defined timeout for the Replay Timer to force cause the retr + * ansmission of unacknowledged TLPs; refer to LL_REPLAY_TIMEOUT_EN and LL_ + * REPLAY_TIMEOUT_FUNC to see how this value is used. The unit for this att + * ribute is in symbol times, which is 4ns at GEN1 speeds and 2ns at GEN2.; + * EP=0x0000; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT 0x1000 + + * ATTR_93 + * (OFFSET, MASK, VALUE) (0XFD480174, 0x0000FFFFU ,0x00009000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_93_OFFSET, 0x0000FFFFU, 0x00009000U); +/*##################################################################### */ + + /* + * Register : ID @ 0XFD480200 + + * Device ID for the the PCIe Cap Structure Device ID field + * PSU_PCIE_ATTRIB_ID_CFG_DEV_ID 0xd021 + + * Vendor ID for the PCIe Cap Structure Vendor ID field + * PSU_PCIE_ATTRIB_ID_CFG_VEND_ID 0x10ee + + * ID + * (OFFSET, MASK, VALUE) (0XFD480200, 0xFFFFFFFFU ,0x10EED021U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ID_OFFSET, 0xFFFFFFFFU, 0x10EED021U); +/*##################################################################### */ + + /* + * Register : SUBSYS_ID @ 0XFD480204 + + * Subsystem ID for the the PCIe Cap Structure Subsystem ID field + * PSU_PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID 0x7 + + * Subsystem Vendor ID for the PCIe Cap Structure Subsystem Vendor ID field + * PSU_PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID 0x10ee + + * SUBSYS_ID + * (OFFSET, MASK, VALUE) (0XFD480204, 0xFFFFFFFFU ,0x10EE0007U) + */ + PSU_Mask_Write(PCIE_ATTRIB_SUBSYS_ID_OFFSET, + 0xFFFFFFFFU, 0x10EE0007U); +/*##################################################################### */ + + /* + * Register : REV_ID @ 0XFD480208 + + * Revision ID for the the PCIe Cap Structure + * PSU_PCIE_ATTRIB_REV_ID_CFG_REV_ID 0x0 + + * REV_ID + * (OFFSET, MASK, VALUE) (0XFD480208, 0x000000FFU ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_REV_ID_OFFSET, 0x000000FFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_24 @ 0XFD480060 + + * Code identifying basic function, subclass and applicable programming int + * erface. Transferred to the Class Code register.; EP=0x8000; RP=0x8000 + * PSU_PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE 0x400 + + * ATTR_24 + * (OFFSET, MASK, VALUE) (0XFD480060, 0x0000FFFFU ,0x00000400U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_24_OFFSET, 0x0000FFFFU, 0x00000400U); +/*##################################################################### */ + + /* + * Register : ATTR_25 @ 0XFD480064 + + * Code identifying basic function, subclass and applicable programming int + * erface. Transferred to the Class Code register.; EP=0x0005; RP=0x0006 + * PSU_PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE 0x6 + + * INTX Interrupt Generation Capable. If FALSE, this will cause Command[10] + * to be hardwired to 0.; EP=0x0001; RP=0x0001 + * PSU_PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED 0 + + * ATTR_25 + * (OFFSET, MASK, VALUE) (0XFD480064, 0x000001FFU ,0x00000006U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_25_OFFSET, 0x000001FFU, 0x00000006U); +/*##################################################################### */ + + /* + * Register : ATTR_4 @ 0XFD480010 + + * Indicates that the AER structures exists. If this is FALSE, then the AER + * structure cannot be accessed via either the link or the management port + * , and AER will be considered to not be present for error management task + * s (such as what types of error messages are sent if an error is detected + * ).; EP=0x0001; RP=0x0001 + * PSU_PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON 0 + + * Indicates that the AER structures exists. If this is FALSE, then the AER + * structure cannot be accessed via either the link or the management port + * , and AER will be considered to not be present for error management task + * s (such as what types of error messages are sent if an error is detected + * ).; EP=0x0001; RP=0x0001 + * PSU_PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON 0 + + * ATTR_4 + * (OFFSET, MASK, VALUE) (0XFD480010, 0x00001000U ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_4_OFFSET, 0x00001000U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_89 @ 0XFD480164 + + * VSEC's Next Capability Offset pointer to the next item in the capabiliti + * es list, or 000h if this is the final capability.; EP=0x0140; RP=0x0140 + * PSU_PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR 0 + + * ATTR_89 + * (OFFSET, MASK, VALUE) (0XFD480164, 0x00001FFEU ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_89_OFFSET, 0x00001FFEU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_79 @ 0XFD48013C + + * CRS SW Visibility. Indicates RC can return CRS to SW. Transferred to the + * Root Capabilities register.; EP=0x0000; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY 1 + + * ATTR_79 + * (OFFSET, MASK, VALUE) (0XFD48013C, 0x00000020U ,0x00000020U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_79_OFFSET, 0x00000020U, 0x00000020U); +/*##################################################################### */ + + /* + * Register : ATTR_43 @ 0XFD4800AC + + * Indicates that the MSIX structures exists. If this is FALSE, then the MS + * IX structure cannot be accessed via either the link or the management po + * rt.; EP=0x0001; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON 0 + + * ATTR_43 + * (OFFSET, MASK, VALUE) (0XFD4800AC, 0x00000100U ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_43_OFFSET, 0x00000100U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_48 @ 0XFD4800C0 + + * MSI-X Table Size. This value is transferred to the MSI-X Message Control + * [10:0] field. Set to 0 if MSI-X is not enabled. Note that the core does + * not implement the table; that must be implemented in user logic.; EP=0x0 + * 003; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE 0 + + * ATTR_48 + * (OFFSET, MASK, VALUE) (0XFD4800C0, 0x000007FFU ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_48_OFFSET, 0x000007FFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_46 @ 0XFD4800B8 + + * MSI-X Table Offset. This value is transferred to the MSI-X Table Offset + * field. Set to 0 if MSI-X is not enabled.; EP=0x0001; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET 0 + + * ATTR_46 + * (OFFSET, MASK, VALUE) (0XFD4800B8, 0x0000FFFFU ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_46_OFFSET, 0x0000FFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_47 @ 0XFD4800BC + + * MSI-X Table Offset. This value is transferred to the MSI-X Table Offset + * field. Set to 0 if MSI-X is not enabled.; EP=0x0000; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET 0 + + * ATTR_47 + * (OFFSET, MASK, VALUE) (0XFD4800BC, 0x00001FFFU ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_47_OFFSET, 0x00001FFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_44 @ 0XFD4800B0 + + * MSI-X Pending Bit Array Offset This value is transferred to the MSI-X PB + * A Offset field. Set to 0 if MSI-X is not enabled.; EP=0x0001; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET 0 + + * ATTR_44 + * (OFFSET, MASK, VALUE) (0XFD4800B0, 0x0000FFFFU ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_44_OFFSET, 0x0000FFFFU, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_45 @ 0XFD4800B4 + + * MSI-X Pending Bit Array Offset This value is transferred to the MSI-X PB + * A Offset field. Set to 0 if MSI-X is not enabled.; EP=0x1000; RP=0x0000 + * PSU_PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET 0 + + * ATTR_45 + * (OFFSET, MASK, VALUE) (0XFD4800B4, 0x0000FFF8U ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_45_OFFSET, 0x0000FFF8U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : CB @ 0XFD48031C + + * DT837748 Enable + * PSU_PCIE_ATTRIB_CB_CB1 0x0 + + * ECO Register 1 + * (OFFSET, MASK, VALUE) (0XFD48031C, 0x00000002U ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_CB_OFFSET, 0x00000002U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : ATTR_35 @ 0XFD48008C + + * Active State PM Support. Indicates the level of active state power manag + * ement supported by the selected PCI Express Link, encoded as follows: 0 + * Reserved, 1 L0s entry supported, 2 Reserved, 3 L0s and L1 entry supporte + * d.; EP=0x0001; RP=0x0001 + * PSU_PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT 0x0 + + * ATTR_35 + * (OFFSET, MASK, VALUE) (0XFD48008C, 0x00003000U ,0x00000000U) + */ + PSU_Mask_Write(PCIE_ATTRIB_ATTR_35_OFFSET, 0x00003000U, 0x00000000U); +/*##################################################################### */ + + /* + * PUTTING PCIE CONTROL IN RESET + */ + /* + * Register : RST_FPD_TOP @ 0XFD1A0100 + + * PCIE control block level reset + * PSU_CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET 0X0 + + * FPD Block level software controlled reset + * (OFFSET, MASK, VALUE) (0XFD1A0100, 0x00020000U ,0x00000000U) + */ + PSU_Mask_Write(CRF_APB_RST_FPD_TOP_OFFSET, 0x00020000U, 0x00000000U); +/*##################################################################### */ + + /* + * PCIE GPIO RESET + */ + /* + * MASK_DATA_0_LSW LOW BANK [15:0] + */ + /* + * MASK_DATA_0_MSW LOW BANK [25:16] + */ + /* + * MASK_DATA_1_LSW LOW BANK [41:26] + */ + /* + * Register : MASK_DATA_1_LSW @ 0XFF0A0008 + + * Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW] + * PSU_GPIO_MASK_DATA_1_LSW_MASK_1_LSW 0xffdf + + * Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW] + * PSU_GPIO_MASK_DATA_1_LSW_DATA_1_LSW 0x20 + + * Maskable Output Data (GPIO Bank1, MIO, Lower 16bits) + * (OFFSET, MASK, VALUE) (0XFF0A0008, 0xFFFFFFFFU ,0xFFDF0020U) + */ + PSU_Mask_Write(GPIO_MASK_DATA_1_LSW_OFFSET, + 0xFFFFFFFFU, 0xFFDF0020U); +/*##################################################################### */ + + /* + * MASK_DATA_1_MSW HIGH BANK [51:42] + */ + /* + * MASK_DATA_1_LSW HIGH BANK [67:52] + */ + /* + * MASK_DATA_1_LSW HIGH BANK [77:68] + */ + /* + * CHECK PLL LOCK FOR LANE0 + */ + /* + * Register : L0_PLL_STATUS_READ_1 @ 0XFD4023E4 + + * Status Read value of PLL Lock + * PSU_SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1 + * (OFFSET, MASK, VALUE) (0XFD4023E4, 0x00000010U ,0x00000010U) + */ + mask_poll(SERDES_L0_PLL_STATUS_READ_1_OFFSET, 0x00000010U); + +/*##################################################################### */ + + /* + * CHECK PLL LOCK FOR LANE1 + */ + /* + * Register : L1_PLL_STATUS_READ_1 @ 0XFD4063E4 + + * Status Read value of PLL Lock + * PSU_SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1 + * (OFFSET, MASK, VALUE) (0XFD4063E4, 0x00000010U ,0x00000010U) + */ + mask_poll(SERDES_L1_PLL_STATUS_READ_1_OFFSET, 0x00000010U); + +/*##################################################################### */ + + /* + * CHECK PLL LOCK FOR LANE2 + */ + /* + * Register : L2_PLL_STATUS_READ_1 @ 0XFD40A3E4 + + * Status Read value of PLL Lock + * PSU_SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1 + * (OFFSET, MASK, VALUE) (0XFD40A3E4, 0x00000010U ,0x00000010U) + */ + mask_poll(SERDES_L2_PLL_STATUS_READ_1_OFFSET, 0x00000010U); + +/*##################################################################### */ + + /* + * CHECK PLL LOCK FOR LANE3 + */ + /* + * Register : L3_PLL_STATUS_READ_1 @ 0XFD40E3E4 + + * Status Read value of PLL Lock + * PSU_SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ 1 + * (OFFSET, MASK, VALUE) (0XFD40E3E4, 0x00000010U ,0x00000010U) + */ + mask_poll(SERDES_L3_PLL_STATUS_READ_1_OFFSET, 0x00000010U); + +/*##################################################################### */ + + /* + * SATA AHCI VENDOR SETTING + */ + /* + * Register : PP2C @ 0XFD0C00AC + + * CIBGMN: COMINIT Burst Gap Minimum. + * PSU_SATA_AHCI_VENDOR_PP2C_CIBGMN 0x18 + + * CIBGMX: COMINIT Burst Gap Maximum. + * PSU_SATA_AHCI_VENDOR_PP2C_CIBGMX 0x40 + + * CIBGN: COMINIT Burst Gap Nominal. + * PSU_SATA_AHCI_VENDOR_PP2C_CIBGN 0x18 + + * CINMP: COMINIT Negate Minimum Period. + * PSU_SATA_AHCI_VENDOR_PP2C_CINMP 0x28 + + * PP2C - Port Phy2Cfg Register. This register controls the configuration o + * f the Phy Control OOB timing for the COMINIT parameters for either Port + * 0 or Port 1. The Port configured is controlled by the value programmed i + * nto the Port Config Register. + * (OFFSET, MASK, VALUE) (0XFD0C00AC, 0xFFFFFFFFU ,0x28184018U) + */ + PSU_Mask_Write(SATA_AHCI_VENDOR_PP2C_OFFSET, + 0xFFFFFFFFU, 0x28184018U); +/*##################################################################### */ + + /* + * Register : PP3C @ 0XFD0C00B0 + + * CWBGMN: COMWAKE Burst Gap Minimum. + * PSU_SATA_AHCI_VENDOR_PP3C_CWBGMN 0x06 + + * CWBGMX: COMWAKE Burst Gap Maximum. + * PSU_SATA_AHCI_VENDOR_PP3C_CWBGMX 0x14 + + * CWBGN: COMWAKE Burst Gap Nominal. + * PSU_SATA_AHCI_VENDOR_PP3C_CWBGN 0x08 + + * CWNMP: COMWAKE Negate Minimum Period. + * PSU_SATA_AHCI_VENDOR_PP3C_CWNMP 0x0E + + * PP3C - Port Phy3CfgRegister. This register controls the configuration of + * the Phy Control OOB timing for the COMWAKE parameters for either Port 0 + * or Port 1. The Port configured is controlled by the value programmed in + * to the Port Config Register. + * (OFFSET, MASK, VALUE) (0XFD0C00B0, 0xFFFFFFFFU ,0x0E081406U) + */ + PSU_Mask_Write(SATA_AHCI_VENDOR_PP3C_OFFSET, + 0xFFFFFFFFU, 0x0E081406U); +/*##################################################################### */ + + /* + * Register : PP4C @ 0XFD0C00B4 + + * BMX: COM Burst Maximum. + * PSU_SATA_AHCI_VENDOR_PP4C_BMX 0x13 + + * BNM: COM Burst Nominal. + * PSU_SATA_AHCI_VENDOR_PP4C_BNM 0x08 + + * SFD: Signal Failure Detection, if the signal detection de-asserts for a + * time greater than this then the OOB detector will determine this is a li + * ne idle and cause the PhyInit state machine to exit the Phy Ready State. + * A value of zero disables the Signal Failure Detector. The value is base + * d on the OOB Detector Clock typically (PMCLK Clock Period) * SFD giving + * a nominal time of 500ns based on a 150MHz PMCLK. + * PSU_SATA_AHCI_VENDOR_PP4C_SFD 0x4A + + * PTST: Partial to Slumber timer value, specific delay the controller shou + * ld apply while in partial before entering slumber. The value is bases on + * the system clock divided by 128, total delay = (Sys Clock Period) * PTS + * T * 128 + * PSU_SATA_AHCI_VENDOR_PP4C_PTST 0x06 + + * PP4C - Port Phy4Cfg Register. This register controls the configuration o + * f the Phy Control Burst timing for the COM parameters for either Port 0 + * or Port 1. The Port configured is controlled by the value programmed int + * o the Port Config Register. + * (OFFSET, MASK, VALUE) (0XFD0C00B4, 0xFFFFFFFFU ,0x064A0813U) + */ + PSU_Mask_Write(SATA_AHCI_VENDOR_PP4C_OFFSET, + 0xFFFFFFFFU, 0x064A0813U); +/*##################################################################### */ + + /* + * Register : PP5C @ 0XFD0C00B8 + + * RIT: Retry Interval Timer. The calculated value divided by two, the lowe + * r digit of precision is not needed. + * PSU_SATA_AHCI_VENDOR_PP5C_RIT 0xC96A4 + + * RCT: Rate Change Timer, a value based on the 54.2us for which a SATA dev + * ice will transmit at a fixed rate ALIGNp after OOB has completed, for a + * fast SERDES it is suggested that this value be 54.2us / 4 + * PSU_SATA_AHCI_VENDOR_PP5C_RCT 0x3FF + + * PP5C - Port Phy5Cfg Register. This register controls the configuration o + * f the Phy Control Retry Interval timing for either Port 0 or Port 1. The + * Port configured is controlled by the value programmed into the Port Con + * fig Register. + * (OFFSET, MASK, VALUE) (0XFD0C00B8, 0xFFFFFFFFU ,0x3FFC96A4U) + */ + PSU_Mask_Write(SATA_AHCI_VENDOR_PP5C_OFFSET, + 0xFFFFFFFFU, 0x3FFC96A4U); +/*##################################################################### */ - return 1; + return 1; } -unsigned long psu_ps_pl_isolation_removal_data() { - // : PS-PL POWER UP REQUEST - /*Register : REQ_PWRUP_INT_EN @ 0XFFD80118

+unsigned long psu_resetin_init_data(void) +{ + /* + * PUTTING SERDES PERIPHERAL IN RESET + */ + /* + * PUTTING USB0 IN RESET + */ + /* + * Register : RST_LPD_TOP @ 0XFF5E023C - Power-up Request Interrupt Enable for PL - PSU_PMU_GLOBAL_REQ_PWRUP_INT_EN_PL 1 + * USB 0 reset for control registers + * PSU_CRL_APB_RST_LPD_TOP_USB0_APB_RESET 0X1 - Power-up Request Interrupt Enable Register. Writing a 1 to this location will unmask the interrupt. - (OFFSET, MASK, VALUE) (0XFFD80118, 0x00800000U ,0x00800000U) - RegMask = (PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_MASK | 0 ); + * USB 0 sleep circuit reset + * PSU_CRL_APB_RST_LPD_TOP_USB0_HIBERRESET 0X1 - RegVal = ((0x00000001U << PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PMU_GLOBAL_REQ_PWRUP_INT_EN_OFFSET ,0x00800000U ,0x00800000U); - /*############################################################################################################################ */ + * USB 0 reset + * PSU_CRL_APB_RST_LPD_TOP_USB0_CORERESET 0X1 - /*Register : REQ_PWRUP_TRIG @ 0XFFD80120

+ * Software control register for the LPD block. + * (OFFSET, MASK, VALUE) (0XFF5E023C, 0x00000540U ,0x00000540U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_TOP_OFFSET, 0x00000540U, 0x00000540U); +/*##################################################################### */ - Power-up Request Trigger for PL - PSU_PMU_GLOBAL_REQ_PWRUP_TRIG_PL 1 + /* + * PUTTING GEM0 IN RESET + */ + /* + * Register : RST_LPD_IOU0 @ 0XFF5E0230 - Power-up Request Trigger Register. A write of one to this location will generate a power-up request to the PMU. - (OFFSET, MASK, VALUE) (0XFFD80120, 0x00800000U ,0x00800000U) - RegMask = (PMU_GLOBAL_REQ_PWRUP_TRIG_PL_MASK | 0 ); + * GEM 3 reset + * PSU_CRL_APB_RST_LPD_IOU0_GEM3_RESET 0X1 - RegVal = ((0x00000001U << PMU_GLOBAL_REQ_PWRUP_TRIG_PL_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (PMU_GLOBAL_REQ_PWRUP_TRIG_OFFSET ,0x00800000U ,0x00800000U); - /*############################################################################################################################ */ + * Software controlled reset for the GEMs + * (OFFSET, MASK, VALUE) (0XFF5E0230, 0x00000008U ,0x00000008U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_IOU0_OFFSET, + 0x00000008U, 0x00000008U); +/*##################################################################### */ - // : POLL ON PL POWER STATUS - /*Register : REQ_PWRUP_STATUS @ 0XFFD80110

+ /* + * PUTTING SATA IN RESET + */ + /* + * Register : RST_FPD_TOP @ 0XFD1A0100 - Power-up Request Status for PL - PSU_PMU_GLOBAL_REQ_PWRUP_STATUS_PL 1 - (OFFSET, MASK, VALUE) (0XFFD80110, 0x00800000U ,0x00000000U) */ - mask_pollOnValue(PMU_GLOBAL_REQ_PWRUP_STATUS_OFFSET,0x00800000U,0x00000000U); + * Sata block level reset + * PSU_CRF_APB_RST_FPD_TOP_SATA_RESET 0X1 - /*############################################################################################################################ */ + * FPD Block level software controlled reset + * (OFFSET, MASK, VALUE) (0XFD1A0100, 0x00000002U ,0x00000002U) + */ + PSU_Mask_Write(CRF_APB_RST_FPD_TOP_OFFSET, 0x00000002U, 0x00000002U); +/*##################################################################### */ + + /* + * PUTTING PCIE IN RESET + */ + /* + * Register : RST_FPD_TOP @ 0XFD1A0100 + + * PCIE config reset + * PSU_CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET 0X1 + + * PCIE control block level reset + * PSU_CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET 0X1 + + * PCIE bridge block level reset (AXI interface) + * PSU_CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET 0X1 + + * FPD Block level software controlled reset + * (OFFSET, MASK, VALUE) (0XFD1A0100, 0x000E0000U ,0x000E0000U) + */ + PSU_Mask_Write(CRF_APB_RST_FPD_TOP_OFFSET, 0x000E0000U, 0x000E0000U); +/*##################################################################### */ + + /* + * PUTTING DP IN RESET + */ + /* + * Register : DP_TX_PHY_POWER_DOWN @ 0XFD4A0238 + + * Two bits per lane. When set to 11, moves the GT to power down mode. When + * set to 00, GT will be in active state. bits [1:0] - lane0 Bits [3:2] - + * lane 1 + * PSU_DP_DP_TX_PHY_POWER_DOWN_POWER_DWN 0XA + + * Control PHY Power down + * (OFFSET, MASK, VALUE) (0XFD4A0238, 0x0000000FU ,0x0000000AU) + */ + PSU_Mask_Write(DP_DP_TX_PHY_POWER_DOWN_OFFSET, + 0x0000000FU, 0x0000000AU); +/*##################################################################### */ + + /* + * Register : DP_PHY_RESET @ 0XFD4A0200 + + * Set to '1' to hold the GT in reset. Clear to release. + * PSU_DP_DP_PHY_RESET_GT_RESET 0X1 + + * Reset the transmitter PHY. + * (OFFSET, MASK, VALUE) (0XFD4A0200, 0x00000002U ,0x00000002U) + */ + PSU_Mask_Write(DP_DP_PHY_RESET_OFFSET, 0x00000002U, 0x00000002U); +/*##################################################################### */ + + /* + * Register : RST_FPD_TOP @ 0XFD1A0100 + + * Display Port block level reset (includes DPDMA) + * PSU_CRF_APB_RST_FPD_TOP_DP_RESET 0X1 + + * FPD Block level software controlled reset + * (OFFSET, MASK, VALUE) (0XFD1A0100, 0x00010000U ,0x00010000U) + */ + PSU_Mask_Write(CRF_APB_RST_FPD_TOP_OFFSET, 0x00010000U, 0x00010000U); +/*##################################################################### */ - return 1; + return 1; } -unsigned long psu_ps_pl_reset_config_data() { - // : PS PL RESET SEQUENCE - // : FABRIC RESET USING EMIO - /*Register : MASK_DATA_5_MSW @ 0XFF0A002C

+unsigned long psu_ps_pl_isolation_removal_data(void) +{ + /* + * PS-PL POWER UP REQUEST + */ + /* + * Register : REQ_PWRUP_INT_EN @ 0XFFD80118 - Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW] - PSU_GPIO_MASK_DATA_5_MSW_MASK_5_MSW 0x8000 + * Power-up Request Interrupt Enable for PL + * PSU_PMU_GLOBAL_REQ_PWRUP_INT_EN_PL 1 - Maskable Output Data (GPIO Bank5, EMIO, Upper 16bits) - (OFFSET, MASK, VALUE) (0XFF0A002C, 0xFFFF0000U ,0x80000000U) - RegMask = (GPIO_MASK_DATA_5_MSW_MASK_5_MSW_MASK | 0 ); + * Power-up Request Interrupt Enable Register. Writing a 1 to this location + * will unmask the interrupt. + * (OFFSET, MASK, VALUE) (0XFFD80118, 0x00800000U ,0x00800000U) + */ + PSU_Mask_Write(PMU_GLOBAL_REQ_PWRUP_INT_EN_OFFSET, + 0x00800000U, 0x00800000U); +/*##################################################################### */ - RegVal = ((0x00008000U << GPIO_MASK_DATA_5_MSW_MASK_5_MSW_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (GPIO_MASK_DATA_5_MSW_OFFSET ,0xFFFF0000U ,0x80000000U); - /*############################################################################################################################ */ + /* + * Register : REQ_PWRUP_TRIG @ 0XFFD80120 - /*Register : DIRM_5 @ 0XFF0A0344

+ * Power-up Request Trigger for PL + * PSU_PMU_GLOBAL_REQ_PWRUP_TRIG_PL 1 - Operation is the same as DIRM_0[DIRECTION_0] - PSU_GPIO_DIRM_5_DIRECTION_5 0x80000000 + * Power-up Request Trigger Register. A write of one to this location will + * generate a power-up request to the PMU. + * (OFFSET, MASK, VALUE) (0XFFD80120, 0x00800000U ,0x00800000U) + */ + PSU_Mask_Write(PMU_GLOBAL_REQ_PWRUP_TRIG_OFFSET, + 0x00800000U, 0x00800000U); +/*##################################################################### */ - Direction mode (GPIO Bank5, EMIO) - (OFFSET, MASK, VALUE) (0XFF0A0344, 0xFFFFFFFFU ,0x80000000U) - RegMask = (GPIO_DIRM_5_DIRECTION_5_MASK | 0 ); + /* + * POLL ON PL POWER STATUS + */ + /* + * Register : REQ_PWRUP_STATUS @ 0XFFD80110 - RegVal = ((0x80000000U << GPIO_DIRM_5_DIRECTION_5_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (GPIO_DIRM_5_OFFSET ,0xFFFFFFFFU ,0x80000000U); - /*############################################################################################################################ */ + * Power-up Request Status for PL + * PSU_PMU_GLOBAL_REQ_PWRUP_STATUS_PL 1 + * (OFFSET, MASK, VALUE) (0XFFD80110, 0x00800000U ,0x00000000U) + */ + mask_pollOnValue(PMU_GLOBAL_REQ_PWRUP_STATUS_OFFSET, + 0x00800000U, 0x00000000U); - /*Register : OEN_5 @ 0XFF0A0348

+/*##################################################################### */ - Operation is the same as OEN_0[OP_ENABLE_0] - PSU_GPIO_OEN_5_OP_ENABLE_5 0x80000000 - Output enable (GPIO Bank5, EMIO) - (OFFSET, MASK, VALUE) (0XFF0A0348, 0xFFFFFFFFU ,0x80000000U) - RegMask = (GPIO_OEN_5_OP_ENABLE_5_MASK | 0 ); + return 1; +} +unsigned long psu_afi_config(void) +{ + /* + * AFI RESET + */ + /* + * Register : RST_FPD_TOP @ 0XFD1A0100 - RegVal = ((0x80000000U << GPIO_OEN_5_OP_ENABLE_5_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (GPIO_OEN_5_OFFSET ,0xFFFFFFFFU ,0x80000000U); - /*############################################################################################################################ */ + * AF_FM0 block level reset + * PSU_CRF_APB_RST_FPD_TOP_AFI_FM0_RESET 0 - /*Register : DATA_5 @ 0XFF0A0054

+ * AF_FM1 block level reset + * PSU_CRF_APB_RST_FPD_TOP_AFI_FM1_RESET 0 - Output Data - PSU_GPIO_DATA_5_DATA_5 0x80000000 + * AF_FM2 block level reset + * PSU_CRF_APB_RST_FPD_TOP_AFI_FM2_RESET 0 - Output Data (GPIO Bank5, EMIO) - (OFFSET, MASK, VALUE) (0XFF0A0054, 0xFFFFFFFFU ,0x80000000U) - RegMask = (GPIO_DATA_5_DATA_5_MASK | 0 ); + * AF_FM3 block level reset + * PSU_CRF_APB_RST_FPD_TOP_AFI_FM3_RESET 0 - RegVal = ((0x80000000U << GPIO_DATA_5_DATA_5_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (GPIO_DATA_5_OFFSET ,0xFFFFFFFFU ,0x80000000U); - /*############################################################################################################################ */ + * AF_FM4 block level reset + * PSU_CRF_APB_RST_FPD_TOP_AFI_FM4_RESET 0 + + * AF_FM5 block level reset + * PSU_CRF_APB_RST_FPD_TOP_AFI_FM5_RESET 0 + + * FPD Block level software controlled reset + * (OFFSET, MASK, VALUE) (0XFD1A0100, 0x00001F80U ,0x00000000U) + */ + PSU_Mask_Write(CRF_APB_RST_FPD_TOP_OFFSET, 0x00001F80U, 0x00000000U); +/*##################################################################### */ + + /* + * Register : RST_LPD_TOP @ 0XFF5E023C + + * AFI FM 6 + * PSU_CRL_APB_RST_LPD_TOP_AFI_FM6_RESET 0 + + * Software control register for the LPD block. + * (OFFSET, MASK, VALUE) (0XFF5E023C, 0x00080000U ,0x00000000U) + */ + PSU_Mask_Write(CRL_APB_RST_LPD_TOP_OFFSET, 0x00080000U, 0x00000000U); +/*##################################################################### */ + + /* + * AFIFM INTERFACE WIDTH + */ + /* + * Register : afi_fs @ 0XFD615000 + + * Select the 32/64/128-bit data width selection for the Slave 0 00: 32-bit + * AXI data width (default) 01: 64-bit AXI data width 10: 128-bit AXI data + * width 11: reserved + * PSU_FPD_SLCR_AFI_FS_DW_SS0_SEL 0x2 + + * Select the 32/64/128-bit data width selection for the Slave 1 00: 32-bit + * AXI data width (default) 01: 64-bit AXI data width 10: 128-bit AXI data + * width 11: reserved + * PSU_FPD_SLCR_AFI_FS_DW_SS1_SEL 0x2 + + * afi fs SLCR control register. This register is static and should not be + * modified during operation. + * (OFFSET, MASK, VALUE) (0XFD615000, 0x00000F00U ,0x00000A00U) + */ + PSU_Mask_Write(FPD_SLCR_AFI_FS_OFFSET, 0x00000F00U, 0x00000A00U); +/*##################################################################### */ + + + return 1; +} +unsigned long psu_ps_pl_reset_config_data(void) +{ + /* + * PS PL RESET SEQUENCE + */ + /* + * FABRIC RESET USING EMIO + */ + /* + * Register : MASK_DATA_5_MSW @ 0XFF0A002C + + * Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW] + * PSU_GPIO_MASK_DATA_5_MSW_MASK_5_MSW 0x8000 + + * Maskable Output Data (GPIO Bank5, EMIO, Upper 16bits) + * (OFFSET, MASK, VALUE) (0XFF0A002C, 0xFFFF0000U ,0x80000000U) + */ + PSU_Mask_Write(GPIO_MASK_DATA_5_MSW_OFFSET, + 0xFFFF0000U, 0x80000000U); +/*##################################################################### */ + + /* + * Register : DIRM_5 @ 0XFF0A0344 + + * Operation is the same as DIRM_0[DIRECTION_0] + * PSU_GPIO_DIRM_5_DIRECTION_5 0x80000000 + + * Direction mode (GPIO Bank5, EMIO) + * (OFFSET, MASK, VALUE) (0XFF0A0344, 0xFFFFFFFFU ,0x80000000U) + */ + PSU_Mask_Write(GPIO_DIRM_5_OFFSET, 0xFFFFFFFFU, 0x80000000U); +/*##################################################################### */ + + /* + * Register : OEN_5 @ 0XFF0A0348 + + * Operation is the same as OEN_0[OP_ENABLE_0] + * PSU_GPIO_OEN_5_OP_ENABLE_5 0x80000000 + + * Output enable (GPIO Bank5, EMIO) + * (OFFSET, MASK, VALUE) (0XFF0A0348, 0xFFFFFFFFU ,0x80000000U) + */ + PSU_Mask_Write(GPIO_OEN_5_OFFSET, 0xFFFFFFFFU, 0x80000000U); +/*##################################################################### */ + + /* + * Register : DATA_5 @ 0XFF0A0054 + + * Output Data + * PSU_GPIO_DATA_5_DATA_5 0x80000000 + + * Output Data (GPIO Bank5, EMIO) + * (OFFSET, MASK, VALUE) (0XFF0A0054, 0xFFFFFFFFU ,0x80000000U) + */ + PSU_Mask_Write(GPIO_DATA_5_OFFSET, 0xFFFFFFFFU, 0x80000000U); +/*##################################################################### */ mask_delay(1); - /*############################################################################################################################ */ +/*##################################################################### */ - // : FABRIC RESET USING DATA_5 TOGGLE - /*Register : DATA_5 @ 0XFF0A0054

+ /* + * FABRIC RESET USING DATA_5 TOGGLE + */ + /* + * Register : DATA_5 @ 0XFF0A0054 - Output Data - PSU_GPIO_DATA_5_DATA_5 0X00000000 + * Output Data + * PSU_GPIO_DATA_5_DATA_5 0X00000000 - Output Data (GPIO Bank5, EMIO) - (OFFSET, MASK, VALUE) (0XFF0A0054, 0xFFFFFFFFU ,0x00000000U) - RegMask = (GPIO_DATA_5_DATA_5_MASK | 0 ); - - RegVal = ((0x00000000U << GPIO_DATA_5_DATA_5_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (GPIO_DATA_5_OFFSET ,0xFFFFFFFFU ,0x00000000U); - /*############################################################################################################################ */ + * Output Data (GPIO Bank5, EMIO) + * (OFFSET, MASK, VALUE) (0XFF0A0054, 0xFFFFFFFFU ,0x00000000U) + */ + PSU_Mask_Write(GPIO_DATA_5_OFFSET, 0xFFFFFFFFU, 0x00000000U); +/*##################################################################### */ mask_delay(1); - /*############################################################################################################################ */ +/*##################################################################### */ - // : FABRIC RESET USING DATA_5 TOGGLE - /*Register : DATA_5 @ 0XFF0A0054

+ /* + * FABRIC RESET USING DATA_5 TOGGLE + */ + /* + * Register : DATA_5 @ 0XFF0A0054 - Output Data - PSU_GPIO_DATA_5_DATA_5 0x80000000 + * Output Data + * PSU_GPIO_DATA_5_DATA_5 0x80000000 - Output Data (GPIO Bank5, EMIO) - (OFFSET, MASK, VALUE) (0XFF0A0054, 0xFFFFFFFFU ,0x80000000U) - RegMask = (GPIO_DATA_5_DATA_5_MASK | 0 ); - - RegVal = ((0x80000000U << GPIO_DATA_5_DATA_5_SHIFT - | 0 ) & RegMask); */ - PSU_Mask_Write (GPIO_DATA_5_OFFSET ,0xFFFFFFFFU ,0x80000000U); - /*############################################################################################################################ */ + * Output Data (GPIO Bank5, EMIO) + * (OFFSET, MASK, VALUE) (0XFF0A0054, 0xFFFFFFFFU ,0x80000000U) + */ + PSU_Mask_Write(GPIO_DATA_5_OFFSET, 0xFFFFFFFFU, 0x80000000U); +/*##################################################################### */ - return 1; + return 1; } -unsigned long psu_ddr_phybringup_data() { +unsigned long psu_ddr_phybringup_data(void) +{ + + + unsigned int regval = 0; + + unsigned int pll_retry = 10; + + unsigned int pll_locked = 0; + + + while ((pll_retry > 0) && (!pll_locked)) { + + Xil_Out32(0xFD080004, 0x00040010);/*PIR*/ + Xil_Out32(0xFD080004, 0x00040011);/*PIR*/ + + while ((Xil_In32(0xFD080030) & 0x1) != 1) { + /*****TODO*****/ + + /*TIMEOUT poll mechanism need to be inserted in this block*/ + + } + + + pll_locked = (Xil_In32(0xFD080030) & 0x80000000) + >> 31;/*PGSR0*/ + pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000) + >> 16;/*DX0GSR0*/ + pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000) + >> 16;/*DX2GSR0*/ + pll_locked &= (Xil_In32(0xFD080BE0) & 0x10000) + >> 16;/*DX4GSR0*/ + pll_locked &= (Xil_In32(0xFD080DE0) & 0x10000) + >> 16;/*DX6GSR0*/ + pll_retry--; + } + Xil_Out32(0xFD0800C0, Xil_In32(0xFD0800C0) | + (pll_retry << 16));/*GPR0*/ + Xil_Out32(0xFD080004U, 0x00040063U); + /* PHY BRINGUP SEQ */ + while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU) { + /*****TODO*****/ + + /*TIMEOUT poll mechanism need to be inserted in this block*/ + + } + + prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U); + /* poll for PHY initialization to complete */ + while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU) { + /*****TODO*****/ + + /*TIMEOUT poll mechanism need to be inserted in this block*/ + + } - unsigned int regval = 0; - int dpll_divisor; - dpll_divisor = (Xil_In32(0xFD1A0080U) & 0x00003F00U) >> 0x00000008U; - prog_reg (0xFD1A0080U, 0x00003F00U, 0x00000008U, 0x00000005U); - prog_reg (0xFD080028U, 0x00000001U, 0x00000000U, 0x00000001U); - Xil_Out32(0xFD080004U, 0x00040003U); - while ((Xil_In32(0xFD080030U) & 0x00000001U) != 0x00000001U); - prog_reg (0xFD080684U, 0x06000000U, 0x00000019U, 0x00000001U); - prog_reg (0xFD0806A4U, 0x06000000U, 0x00000019U, 0x00000001U); - prog_reg (0xFD0806C4U, 0x06000000U, 0x00000019U, 0x00000001U); - prog_reg (0xFD0806E4U, 0x06000000U, 0x00000019U, 0x00000001U); - prog_reg (0xFD1A0080, 0x3F00, 0x8, dpll_divisor); - Xil_Out32(0xFD080004U, 0x40040071U); - while ((Xil_In32(0xFD080030U) & 0x00000001U) != 0x00000001U); - Xil_Out32(0xFD080004U, 0x40040001U); - while ((Xil_In32(0xFD080030U) & 0x00000001U) != 0x00000001U); - // PHY BRINGUP SEQ - while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU); - prog_reg (0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U); - //poll for PHY initialization to complete - while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU); - Xil_Out32(0xFD0701B0U, 0x00000001U); Xil_Out32(0xFD070320U, 0x00000001U); - while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U); - prog_reg (0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U); - Xil_Out32(0xFD080004, 0x0004FE01); //PUB_PIR - regval = Xil_In32(0xFD080030); //PUB_PGSR0 - while(regval != 0x80000FFF){ - regval = Xil_In32(0xFD080030); //PUB_PGSR0 - } + while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U) { + /*****TODO*****/ - - // Run Vref training in static read mode + /*TIMEOUT poll mechanism need to be inserted in this block*/ + + } + + prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U); + Xil_Out32(0xFD080004, 0x0004FE01); /*PUB_PIR*/ + regval = Xil_In32(0xFD080030); /*PUB_PGSR0*/ + while (regval != 0x80000FFF) + regval = Xil_In32(0xFD080030); /*PUB_PGSR0*/ + +/* Run Vref training in static read mode*/ Xil_Out32(0xFD080200U, 0x100091C7U); - Xil_Out32(0xFD080018U, 0x00F01EF2U); - Xil_Out32(0xFD08001CU, 0x55AA5498U); - Xil_Out32(0xFD08142CU, 0x00041830U); - Xil_Out32(0xFD08146CU, 0x00041830U); - Xil_Out32(0xFD0814ACU, 0x00041830U); - Xil_Out32(0xFD0814ECU, 0x00041830U); - Xil_Out32(0xFD08152CU, 0x00041830U); - + Xil_Out32(0xFD080018U, 0x00F01EEFU); + prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000003U); + prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000003U); + prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000003U); - Xil_Out32(0xFD080004, 0x00060001); //PUB_PIR - regval = Xil_In32(0xFD080030); //PUB_PGSR0 - while((regval & 0x80004001) != 0x80004001){ - regval = Xil_In32(0xFD080030); //PUB_PGSR0 - } - // Vref training is complete, disabling static read mode + Xil_Out32(0xFD080004, 0x00060001); /*PUB_PIR*/ + regval = Xil_In32(0xFD080030); /*PUB_PGSR0*/ + while ((regval & 0x80004001) != 0x80004001) { + /*PUB_PGSR0*/ + regval = Xil_In32(0xFD080030); + } + + prog_reg(0xFD08001CU, 0x00000018U, 0x00000003U, 0x00000000U); + prog_reg(0xFD08142CU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD08146CU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD0814ACU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD0814ECU, 0x00000030U, 0x00000004U, 0x00000000U); + prog_reg(0xFD08152CU, 0x00000030U, 0x00000004U, 0x00000000U); +/*Vref training is complete, disabling static read mode*/ Xil_Out32(0xFD080200U, 0x800091C7U); - Xil_Out32(0xFD080018U, 0x00F12302U); - Xil_Out32(0xFD08001CU, 0x55AA5480U); - Xil_Out32(0xFD08142CU, 0x00041800U); - Xil_Out32(0xFD08146CU, 0x00041800U); - Xil_Out32(0xFD0814ACU, 0x00041800U); - Xil_Out32(0xFD0814ECU, 0x00041800U); - Xil_Out32(0xFD08152CU, 0x00041800U); - + Xil_Out32(0xFD080018U, 0x00F122E7U); - Xil_Out32(0xFD080004, 0x0000C001); //PUB_PIR - regval = Xil_In32(0xFD080030); //PUB_PGSR0 - while((regval & 0x80000C01) != 0x80000C01){ - regval = Xil_In32(0xFD080030); //PUB_PGSR0 - } + + Xil_Out32(0xFD080004, 0x0000C001); /*PUB_PIR*/ + regval = Xil_In32(0xFD080030); /*PUB_PGSR0*/ + while ((regval & 0x80000C01) != 0x80000C01) { + /*PUB_PGSR0*/ + regval = Xil_In32(0xFD080030); + } Xil_Out32(0xFD070180U, 0x01000040U); Xil_Out32(0xFD070060U, 0x00000000U); - prog_reg (0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U); + prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U); -return 1; +return 1; } /** * CRL_APB Base Address */ #define CRL_APB_BASEADDR 0XFF5E0000U -#define CRL_APB_RST_LPD_IOU0 ( ( CRL_APB_BASEADDR ) + 0X00000230U ) -#define CRL_APB_RST_LPD_IOU1 ( ( CRL_APB_BASEADDR ) + 0X00000234U ) -#define CRL_APB_RST_LPD_IOU2 ( ( CRL_APB_BASEADDR ) + 0X00000238U ) -#define CRL_APB_RST_LPD_TOP ( ( CRL_APB_BASEADDR ) + 0X0000023CU ) -#define CRL_APB_IOU_SWITCH_CTRL ( ( CRL_APB_BASEADDR ) + 0X0000009CU ) +#define CRL_APB_RST_LPD_IOU0 ((CRL_APB_BASEADDR) + 0X00000230U) +#define CRL_APB_RST_LPD_IOU1 ((CRL_APB_BASEADDR) + 0X00000234U) +#define CRL_APB_RST_LPD_IOU2 ((CRL_APB_BASEADDR) + 0X00000238U) +#define CRL_APB_RST_LPD_TOP ((CRL_APB_BASEADDR) + 0X0000023CU) +#define CRL_APB_IOU_SWITCH_CTRL ((CRL_APB_BASEADDR) + 0X0000009CU) /** * CRF_APB Base Address */ #define CRF_APB_BASEADDR 0XFD1A0000U -#define CRF_APB_RST_FPD_TOP ( ( CRF_APB_BASEADDR ) + 0X00000100U ) -#define CRF_APB_GPU_REF_CTRL ( ( CRF_APB_BASEADDR ) + 0X00000084U ) -#define CRF_APB_RST_DDR_SS ( ( CRF_APB_BASEADDR ) + 0X00000108U ) +#define CRF_APB_RST_FPD_TOP ((CRF_APB_BASEADDR) + 0X00000100U) +#define CRF_APB_GPU_REF_CTRL ((CRF_APB_BASEADDR) + 0X00000084U) +#define CRF_APB_RST_DDR_SS ((CRF_APB_BASEADDR) + 0X00000108U) #define PSU_MASK_POLL_TIME 1100000 +/** + * * Register: CRF_APB_DPLL_CTRL + */ +#define CRF_APB_DPLL_CTRL ((CRF_APB_BASEADDR) + 0X0000002C) -int mask_pollOnValue(u32 add , u32 mask, u32 value ) { - volatile u32 *addr = (volatile u32*)(unsigned long) add; + +#define CRF_APB_DPLL_CTRL_DIV2_SHIFT 16 +#define CRF_APB_DPLL_CTRL_DIV2_WIDTH 1 + +#define CRF_APB_DPLL_CTRL_FBDIV_SHIFT 8 +#define CRF_APB_DPLL_CTRL_FBDIV_WIDTH 7 + +#define CRF_APB_DPLL_CTRL_BYPASS_SHIFT 3 +#define CRF_APB_DPLL_CTRL_BYPASS_WIDTH 1 + +#define CRF_APB_DPLL_CTRL_RESET_SHIFT 0 +#define CRF_APB_DPLL_CTRL_RESET_WIDTH 1 + +/** + * * Register: CRF_APB_DPLL_CFG + */ +#define CRF_APB_DPLL_CFG ((CRF_APB_BASEADDR) + 0X00000030) + +#define CRF_APB_DPLL_CFG_LOCK_DLY_SHIFT 25 +#define CRF_APB_DPLL_CFG_LOCK_DLY_WIDTH 7 + +#define CRF_APB_DPLL_CFG_LOCK_CNT_SHIFT 13 +#define CRF_APB_DPLL_CFG_LOCK_CNT_WIDTH 10 + +#define CRF_APB_DPLL_CFG_LFHF_SHIFT 10 +#define CRF_APB_DPLL_CFG_LFHF_WIDTH 2 + +#define CRF_APB_DPLL_CFG_CP_SHIFT 5 +#define CRF_APB_DPLL_CFG_CP_WIDTH 4 + +#define CRF_APB_DPLL_CFG_RES_SHIFT 0 +#define CRF_APB_DPLL_CFG_RES_WIDTH 4 + +/** + * Register: CRF_APB_PLL_STATUS + */ +#define CRF_APB_PLL_STATUS ((CRF_APB_BASEADDR) + 0X00000044) + + +static int mask_pollOnValue(u32 add, u32 mask, u32 value) +{ + volatile u32 *addr = (volatile u32 *)(unsigned long) add; int i = 0; - while ((*addr & mask)!= value) { - if (i == PSU_MASK_POLL_TIME) { + + while ((*addr & mask) != value) { + if (i == PSU_MASK_POLL_TIME) return 0; - } i++; } - return 1; - //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr); + return 1; } -int mask_poll(u32 add , u32 mask) { - volatile u32 *addr = (volatile u32*)(unsigned long) add; +static int mask_poll(u32 add, u32 mask) +{ + volatile u32 *addr = (volatile u32 *)(unsigned long) add; int i = 0; + while (!(*addr & mask)) { - if (i == PSU_MASK_POLL_TIME) { + if (i == PSU_MASK_POLL_TIME) return 0; - } i++; } - return 1; - //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr); + return 1; } -void mask_delay(u32 delay) { - usleep (delay); +static void mask_delay(u32 delay) +{ + usleep(delay); } -u32 mask_read(u32 add , u32 mask ) { - volatile u32 *addr = (volatile u32*)(unsigned long) add; - u32 val = (*addr & mask); - //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val); - return val; +static u32 mask_read(u32 add, u32 mask) +{ + volatile u32 *addr = (volatile u32 *)(unsigned long) add; + u32 val = (*addr & mask); + return val; } +static void dpll_prog(int ddr_pll_fbdiv, int d_lock_dly, int d_lock_cnt, + int d_lfhf, int d_cp, int d_res) { -//Following SERDES programming sequences that a user need to follow to work around the known limitation with SERDES. -//These sequences should done before STEP 1 and STEP 2 as described in previous section. These programming steps are -//required for current silicon version and are likely to undergo further changes with subsequent silicon versions. + unsigned int pll_ctrl_regval; + unsigned int pll_status_regval; + + pll_ctrl_regval = Xil_In32(CRF_APB_DPLL_CTRL); + pll_ctrl_regval = pll_ctrl_regval & (~CRF_APB_DPLL_CTRL_DIV2_MASK); + pll_ctrl_regval = pll_ctrl_regval | (1 << CRF_APB_DPLL_CTRL_DIV2_SHIFT); + Xil_Out32(CRF_APB_DPLL_CTRL, pll_ctrl_regval); + + pll_ctrl_regval = Xil_In32(CRF_APB_DPLL_CFG); + pll_ctrl_regval = pll_ctrl_regval & (~CRF_APB_DPLL_CFG_LOCK_DLY_MASK); + pll_ctrl_regval = pll_ctrl_regval | + (d_lock_dly << CRF_APB_DPLL_CFG_LOCK_DLY_SHIFT); + Xil_Out32(CRF_APB_DPLL_CFG, pll_ctrl_regval); + + pll_ctrl_regval = Xil_In32(CRF_APB_DPLL_CFG); + pll_ctrl_regval = pll_ctrl_regval & (~CRF_APB_DPLL_CFG_LOCK_CNT_MASK); + pll_ctrl_regval = pll_ctrl_regval | + (d_lock_cnt << CRF_APB_DPLL_CFG_LOCK_CNT_SHIFT); + Xil_Out32(CRF_APB_DPLL_CFG, pll_ctrl_regval); + + pll_ctrl_regval = Xil_In32(CRF_APB_DPLL_CFG); + pll_ctrl_regval = pll_ctrl_regval & (~CRF_APB_DPLL_CFG_LFHF_MASK); + pll_ctrl_regval = pll_ctrl_regval | + (d_lfhf << CRF_APB_DPLL_CFG_LFHF_SHIFT); + Xil_Out32(CRF_APB_DPLL_CFG, pll_ctrl_regval); + + pll_ctrl_regval = Xil_In32(CRF_APB_DPLL_CFG); + pll_ctrl_regval = pll_ctrl_regval & (~CRF_APB_DPLL_CFG_CP_MASK); + pll_ctrl_regval = pll_ctrl_regval | + (d_cp << CRF_APB_DPLL_CFG_CP_SHIFT); + Xil_Out32(CRF_APB_DPLL_CFG, pll_ctrl_regval); + + pll_ctrl_regval = Xil_In32(CRF_APB_DPLL_CFG); + pll_ctrl_regval = pll_ctrl_regval & (~CRF_APB_DPLL_CFG_RES_MASK); + pll_ctrl_regval = pll_ctrl_regval | + (d_res << CRF_APB_DPLL_CFG_RES_SHIFT); + Xil_Out32(CRF_APB_DPLL_CFG, pll_ctrl_regval); + + pll_ctrl_regval = Xil_In32(CRF_APB_DPLL_CTRL); + pll_ctrl_regval = pll_ctrl_regval & (~CRF_APB_DPLL_CTRL_FBDIV_MASK); + pll_ctrl_regval = pll_ctrl_regval | + (ddr_pll_fbdiv << CRF_APB_DPLL_CTRL_FBDIV_SHIFT); + Xil_Out32(CRF_APB_DPLL_CTRL, pll_ctrl_regval); + + /*Setting PLL BYPASS*/ + pll_ctrl_regval = Xil_In32(CRF_APB_DPLL_CTRL); + pll_ctrl_regval = pll_ctrl_regval & (~CRF_APB_DPLL_CTRL_BYPASS_MASK); + pll_ctrl_regval = pll_ctrl_regval | + (1 << CRF_APB_DPLL_CTRL_BYPASS_SHIFT); + Xil_Out32(CRF_APB_DPLL_CTRL, pll_ctrl_regval); + + /*Setting PLL RESET*/ + pll_ctrl_regval = Xil_In32(CRF_APB_DPLL_CTRL); + pll_ctrl_regval = pll_ctrl_regval & (~CRF_APB_DPLL_CTRL_RESET_MASK); + pll_ctrl_regval = pll_ctrl_regval | + (1 << CRF_APB_DPLL_CTRL_RESET_SHIFT); + Xil_Out32(CRF_APB_DPLL_CTRL, pll_ctrl_regval); + + /*Clearing PLL RESET*/ + pll_ctrl_regval = Xil_In32(CRF_APB_DPLL_CTRL); + pll_ctrl_regval = pll_ctrl_regval & (~CRF_APB_DPLL_CTRL_RESET_MASK); + pll_ctrl_regval = pll_ctrl_regval | + (0 << CRF_APB_DPLL_CTRL_RESET_SHIFT); + Xil_Out32(CRF_APB_DPLL_CTRL, pll_ctrl_regval); + + /*Checking PLL lock*/ + pll_status_regval = 0x00000000; + while ((pll_status_regval & CRF_APB_PLL_STATUS_DPLL_LOCK_MASK) != + CRF_APB_PLL_STATUS_DPLL_LOCK_MASK) + pll_status_regval = Xil_In32(CRF_APB_PLL_STATUS); -int serdes_fixcal_code() { + + /*Clearing PLL BYPASS*/ + pll_ctrl_regval = Xil_In32(CRF_APB_DPLL_CTRL); + pll_ctrl_regval = pll_ctrl_regval & (~CRF_APB_DPLL_CTRL_BYPASS_MASK); + pll_ctrl_regval = pll_ctrl_regval | + (0 << CRF_APB_DPLL_CTRL_BYPASS_SHIFT); + Xil_Out32(CRF_APB_DPLL_CTRL, pll_ctrl_regval); + +} + +/*Following SERDES programming sequences that a user need to follow to work + * around the known limitation with SERDES. These sequences should done + * before STEP 1 and STEP 2 as described in previous section. These + * programming steps are *required for current silicon version and are + * likely to undergo further changes with subsequent silicon versions. + */ + + +static int serdes_enb_coarse_saturation(void) +{ + /*Enable PLL Coarse Code saturation Logic*/ + Xil_Out32(0xFD402094, 0x00000010); + Xil_Out32(0xFD406094, 0x00000010); + Xil_Out32(0xFD40A094, 0x00000010); + Xil_Out32(0xFD40E094, 0x00000010); + return 1; +} + +int serdes_fixcal_code(void) +{ int MaskStatus = 1; - // L3_TM_CALIB_DIG19 - Xil_Out32(0xFD40EC4C,0x00000020); - //ICM_CFG0 - Xil_Out32(0xFD410010,0x00000001); + unsigned int rdata = 0; + + /*The valid codes are from 0x26 to 0x3C. + *There are 23 valid codes in total. + */ + /*Each element of array stands for count of occurence of valid code.*/ + unsigned int match_pmos_code[23]; + /*Each element of array stands for count of occurence of valid code.*/ + /*The valid codes are from 0xC to 0x12. + *There are 7 valid codes in total. + */ + unsigned int match_nmos_code[23]; + /*Each element of array stands for count of occurence of valid code.*/ + /*The valid codes are from 0x6 to 0xC. + * There are 7 valid codes in total. + */ + unsigned int match_ical_code[7]; + /*Each element of array stands for count of occurence of valid code.*/ + unsigned int match_rcal_code[7]; - //is calibration done, polling on L3_CALIB_DONE_STATUS - MaskStatus = mask_poll(0xFD40EF14, 0x2); - - if (MaskStatus == 0) - { - xil_printf("SERDES initialization timed out\n\r"); - } - - unsigned int tmp_0_1; - tmp_0_1 = mask_read(0xFD400B0C, 0x3F); - - unsigned int tmp_0_2 = tmp_0_1 & (0x7); - unsigned int tmp_0_3 = tmp_0_1 & (0x38); - //Configure ICM for de-asserting CMN_Resetn - Xil_Out32(0xFD410010,0x00000000); - Xil_Out32(0xFD410014,0x00000000); - - unsigned int tmp_0_2_mod = (tmp_0_2 <<1) | (0x1); - tmp_0_2_mod = (tmp_0_2_mod <<4); - - tmp_0_3 = tmp_0_3 >>3; - Xil_Out32(0xFD40EC4C,tmp_0_3); + unsigned int p_code = 0; + unsigned int n_code = 0; + unsigned int i_code = 0; + unsigned int r_code = 0; + unsigned int repeat_count = 0; + unsigned int L3_TM_CALIB_DIG20 = 0; + unsigned int L3_TM_CALIB_DIG19 = 0; + unsigned int L3_TM_CALIB_DIG18 = 0; + unsigned int L3_TM_CALIB_DIG16 = 0; + unsigned int L3_TM_CALIB_DIG15 = 0; + unsigned int L3_TM_CALIB_DIG14 = 0; - //L3_TM_CALIB_DIG18 - Xil_Out32(0xFD40EC48,tmp_0_2_mod); - return MaskStatus; + int i = 0; + rdata = Xil_In32(0XFD40289C); + rdata = rdata & ~0x03; + rdata = rdata | 0x1; + Xil_Out32(0XFD40289C, rdata); + // check supply good status before starting AFE sequencing + int count = 0; + do + { + if (count == PSU_MASK_POLL_TIME) + break; + rdata = Xil_In32(0xFD402B1C); + count++; + }while((rdata&0x0000000E) !=0x0000000E); + + for (i = 0; i < 23; i++) { + match_pmos_code[i] = 0; + match_nmos_code[i] = 0; + } + for (i = 0; i < 7; i++) { + match_ical_code[i] = 0; + match_rcal_code[i] = 0; + } + + + do { + /*Clear ICM_CFG value*/ + Xil_Out32(0xFD410010, 0x00000000); + Xil_Out32(0xFD410014, 0x00000000); + + /*Set ICM_CFG value*/ + /*This will trigger recalibration of all stages*/ + Xil_Out32(0xFD410010, 0x00000001); + Xil_Out32(0xFD410014, 0x00000000); + + /*is calibration done? polling on L3_CALIB_DONE_STATUS*/ + MaskStatus = mask_poll(0xFD40EF14, 0x2); + if (MaskStatus == 0) { + /*failure here is because of calibration done timeout*/ + xil_printf("#SERDES initialization timed out\n\r"); + return MaskStatus; + } + + p_code = mask_read(0xFD40EF18, 0xFFFFFFFF);/*PMOS code*/ + n_code = mask_read(0xFD40EF1C, 0xFFFFFFFF);/*NMOS code*/ + /*m_code = mask_read(0xFD40EF20, 0xFFFFFFFF)*/;/*MPHY code*/ + i_code = mask_read(0xFD40EF24, 0xFFFFFFFF);/*ICAL code*/ + r_code = mask_read(0xFD40EF28, 0xFFFFFFFF);/*RX code*/ + /*u_code = mask_read(0xFD40EF2C, 0xFFFFFFFF)*/;/*USB2 code*/ + + /*PMOS code in acceptable range*/ + if ((p_code >= 0x26) && (p_code <= 0x3C)) + match_pmos_code[p_code - 0x26] += 1; + + /*NMOS code in acceptable range*/ + if ((n_code >= 0x26) && (n_code <= 0x3C)) + match_nmos_code[n_code - 0x26] += 1; + + /*PMOS code in acceptable range*/ + if ((i_code >= 0xC) && (i_code <= 0x12)) + match_ical_code[i_code - 0xC] += 1; + + /*NMOS code in acceptable range*/ + if ((r_code >= 0x6) && (r_code <= 0xC)) + match_rcal_code[r_code - 0x6] += 1; + + + } while (repeat_count++ < 10); + + /*find the valid code which resulted in maximum times in 10 iterations*/ + for (i = 0; i < 23; i++) { + if (match_pmos_code[i] >= match_pmos_code[0]) { + match_pmos_code[0] = match_pmos_code[i]; + p_code = 0x26 + i; + } + if (match_nmos_code[i] >= match_nmos_code[0]) { + match_nmos_code[0] = match_nmos_code[i]; + n_code = 0x26 + i; + } + } + + for (i = 0; i < 7; i++) { + if (match_ical_code[i] >= match_ical_code[0]) { + match_ical_code[0] = match_ical_code[i]; + i_code = 0xC + i; + } + if (match_rcal_code[i] >= match_rcal_code[0]) { + match_rcal_code[0] = match_rcal_code[i]; + r_code = 0x6 + i; + } + } + /*L3_TM_CALIB_DIG20[3] PSW MSB Override*/ + /*L3_TM_CALIB_DIG20[2:0] PSW Code [4:2]*/ + L3_TM_CALIB_DIG20 = mask_read(0xFD40EC50, 0xFFFFFFF0);/*read DIG20*/ + L3_TM_CALIB_DIG20 = L3_TM_CALIB_DIG20 | 0x8 | ((p_code >> 2) & 0x7); + + + /*L3_TM_CALIB_DIG19[7:6] PSW Code [1:0]*/ + /*L3_TM_CALIB_DIG19[5] PSW Override*/ + /*L3_TM_CALIB_DIG19[2] NSW MSB Override*/ + /*L3_TM_CALIB_DIG19[1:0] NSW Code [4:3]*/ + L3_TM_CALIB_DIG19 = mask_read(0xFD40EC4C, 0xFFFFFF18);/*read DIG19*/ + L3_TM_CALIB_DIG19 = L3_TM_CALIB_DIG19 | ((p_code & 0x3) << 6) + | 0x20 | 0x4 | ((n_code >> 3) & 0x3); + + /*L3_TM_CALIB_DIG18[7:5] NSW Code [2:0]*/ + /*L3_TM_CALIB_DIG18[4] NSW Override*/ + L3_TM_CALIB_DIG18 = mask_read(0xFD40EC48, 0xFFFFFF0F);/*read DIG18*/ + L3_TM_CALIB_DIG18 = L3_TM_CALIB_DIG18 | ((n_code & 0x7) << 5) | 0x10; + + + /*L3_TM_CALIB_DIG16[2:0] RX Code [3:1]*/ + L3_TM_CALIB_DIG16 = mask_read(0xFD40EC40, 0xFFFFFFF8);/*read DIG16*/ + L3_TM_CALIB_DIG16 = L3_TM_CALIB_DIG16 | ((r_code >> 1) & 0x7); + + /*L3_TM_CALIB_DIG15[7] RX Code [0]*/ + /*L3_TM_CALIB_DIG15[6] RX CODE Override*/ + /*L3_TM_CALIB_DIG15[3] ICAL MSB Override*/ + /*L3_TM_CALIB_DIG15[2:0] ICAL Code [3:1]*/ + L3_TM_CALIB_DIG15 = mask_read(0xFD40EC3C, 0xFFFFFF30);/*read DIG15*/ + L3_TM_CALIB_DIG15 = L3_TM_CALIB_DIG15 | ((r_code & 0x1) << 7) + | 0x40 | 0x8 | ((i_code >> 1) & 0x7); + + /*L3_TM_CALIB_DIG14[7] ICAL Code [0]*/ + /*L3_TM_CALIB_DIG14[6] ICAL Override*/ + L3_TM_CALIB_DIG14 = mask_read(0xFD40EC38, 0xFFFFFF3F);/*read DIG14*/ + L3_TM_CALIB_DIG14 = L3_TM_CALIB_DIG14 | ((i_code & 0x1) << 7) | 0x40; + + /*Forces the calibration values*/ + Xil_Out32(0xFD40EC50, L3_TM_CALIB_DIG20); + Xil_Out32(0xFD40EC4C, L3_TM_CALIB_DIG19); + Xil_Out32(0xFD40EC48, L3_TM_CALIB_DIG18); + Xil_Out32(0xFD40EC40, L3_TM_CALIB_DIG16); + Xil_Out32(0xFD40EC3C, L3_TM_CALIB_DIG15); + Xil_Out32(0xFD40EC38, L3_TM_CALIB_DIG14); + return MaskStatus; } - -int serdes_enb_coarse_saturation() { - //Enable PLL Coarse Code saturation Logic - Xil_Out32(0xFD402094,0x00000010); - Xil_Out32(0xFD406094,0x00000010); - Xil_Out32(0xFD40A094,0x00000010); - Xil_Out32(0xFD40E094,0x00000010); - return 1; -} - -int init_serdes() { +static int init_serdes(void) +{ int status = 1; + status &= psu_resetin_init_data(); status &= serdes_fixcal_code(); status &= serdes_enb_coarse_saturation(); - status &= psu_serdes_init_data(); + status &= psu_serdes_init_data(); status &= psu_resetout_init_data(); return status; } - - - - -void init_peripheral() +static void init_peripheral(void) { - unsigned int RegValue; - - /* Turn on IOU Clock */ - //Xil_Out32( CRL_APB_IOU_SWITCH_CTRL, 0x01001500); - - /* Release all resets in the IOU */ - Xil_Out32( CRL_APB_RST_LPD_IOU0, 0x00000000); - Xil_Out32( CRL_APB_RST_LPD_IOU1, 0x00000000); - Xil_Out32( CRL_APB_RST_LPD_IOU2, 0x00000000); - - /* Activate GPU clocks */ - //Xil_Out32(CRF_APB_GPU_REF_CTRL, 0x07001500); - - /* Take LPD out of reset except R5 */ - RegValue = Xil_In32(CRL_APB_RST_LPD_TOP); - RegValue &= 0x7; - Xil_Out32( CRL_APB_RST_LPD_TOP, RegValue); - - /* Take most of FPD out of reset */ - Xil_Out32( CRF_APB_RST_FPD_TOP, 0x00000000); - - /* Making DPDMA as secure */ - unsigned int tmp_regval; - tmp_regval = Xil_In32(0xFD690040); - tmp_regval &= ~0x00000001; - Xil_Out32(0xFD690040, tmp_regval); - - /* Making PCIe as secure */ - tmp_regval = Xil_In32(0xFD690030); - tmp_regval &= ~0x00000001; - Xil_Out32(0xFD690030, tmp_regval); +/*SMMU_REG Interrrupt Enable: Followig register need to be written all the time to properly catch SMMU messages.*/ + PSU_Mask_Write(0xFD5F0018, 0x8000001FU, 0x8000001FU); } -int psu_init_xppu_aper_ram() { - unsigned long APER_OFFSET = 0xFF981000; - int i = 0; - for (; i <= 400; i++) { - PSU_Mask_Write (APER_OFFSET ,0xF80FFFFFU ,0x08080000U); - APER_OFFSET = APER_OFFSET + 0x4; - } +static int psu_init_xppu_aper_ram(void) +{ return 0; } -int psu_lpd_protection() { - psu_init_xppu_aper_ram(); - psu_lpd_xppu_data(); - return 0; +int psu_lpd_protection(void) +{ + psu_init_xppu_aper_ram(); + return 0; } -int psu_ddr_protection() { - psu_ddr_xmpu0_data(); - psu_ddr_xmpu1_data(); - psu_ddr_xmpu2_data(); - psu_ddr_xmpu3_data(); - psu_ddr_xmpu4_data(); - psu_ddr_xmpu5_data(); - return 0; +int psu_ddr_protection(void) +{ + psu_ddr_xmpu0_data(); + psu_ddr_xmpu1_data(); + psu_ddr_xmpu2_data(); + psu_ddr_xmpu3_data(); + psu_ddr_xmpu4_data(); + psu_ddr_xmpu5_data(); + return 0; } -int psu_ocm_protection() { - psu_ocm_xmpu_data(); - return 0; +int psu_ocm_protection(void) +{ + psu_ocm_xmpu_data(); + return 0; } -int psu_fpd_protection() { - psu_fpd_xmpu_data(); - return 0; +int psu_fpd_protection(void) +{ + psu_fpd_xmpu_data(); + return 0; } -int psu_protection_lock() { - psu_protection_lock_data(); - return 0; +int psu_protection_lock(void) +{ + psu_protection_lock_data(); + return 0; } -int psu_protection() { - psu_ddr_protection(); - psu_ocm_protection(); - psu_fpd_protection(); - psu_lpd_protection(); - return 0; +int psu_protection(void) +{ + psu_apply_master_tz(); + psu_ddr_protection(); + psu_ocm_protection(); + psu_fpd_protection(); + psu_lpd_protection(); + return 0; } - - int -psu_init() +psu_init(void) { - int status = 1; - status &= psu_mio_init_data (); - status &= psu_pll_init_data (); - status &= psu_clock_init_data (); - - status &= psu_ddr_init_data (); - status &= psu_ddr_phybringup_data (); - status &= psu_peripherals_init_data (); + int status = 1; + status &= psu_mio_init_data(); + status &= psu_pll_init_data(); + status &= psu_clock_init_data(); + status &= psu_ddr_init_data(); + status &= psu_ddr_phybringup_data(); + status &= psu_peripherals_init_data(); status &= init_serdes(); - init_peripheral (); + init_peripheral(); - status &= psu_peripherals_powerdwn_data (); - - if (status == 0) { + status &= psu_peripherals_powerdwn_data(); + status &= psu_afi_config(); + psu_ddr_qos_init_data(); + + if (status == 0) return 1; - } return 0; } diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init_gpl.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init_gpl.h index 0fb578181..7feed7d35 100644 --- a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init_gpl.h +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init_gpl.h @@ -16,13 +16,13 @@ * with this program; if not, see * * -******************************************************************************/ +******************************************************************************/ /****************************************************************************/ /** * * @file psu_init_gpl.h * -* This file is automatically generated +* This file is automatically generated * *****************************************************************************/ @@ -41,8 +41,6 @@ #define CRL_APB_RPLL_CTRL_OFFSET 0XFF5E0030 #undef CRL_APB_RPLL_TO_FPD_CTRL_OFFSET #define CRL_APB_RPLL_TO_FPD_CTRL_OFFSET 0XFF5E0048 -#undef CRL_APB_RPLL_FRAC_CFG_OFFSET -#define CRL_APB_RPLL_FRAC_CFG_OFFSET 0XFF5E0038 #undef CRL_APB_IOPLL_CFG_OFFSET #define CRL_APB_IOPLL_CFG_OFFSET 0XFF5E0024 #undef CRL_APB_IOPLL_CTRL_OFFSET @@ -57,8 +55,6 @@ #define CRL_APB_IOPLL_CTRL_OFFSET 0XFF5E0020 #undef CRL_APB_IOPLL_TO_FPD_CTRL_OFFSET #define CRL_APB_IOPLL_TO_FPD_CTRL_OFFSET 0XFF5E0044 -#undef CRL_APB_IOPLL_FRAC_CFG_OFFSET -#define CRL_APB_IOPLL_FRAC_CFG_OFFSET 0XFF5E0028 #undef CRF_APB_APLL_CFG_OFFSET #define CRF_APB_APLL_CFG_OFFSET 0XFD1A0024 #undef CRF_APB_APLL_CTRL_OFFSET @@ -73,8 +69,6 @@ #define CRF_APB_APLL_CTRL_OFFSET 0XFD1A0020 #undef CRF_APB_APLL_TO_LPD_CTRL_OFFSET #define CRF_APB_APLL_TO_LPD_CTRL_OFFSET 0XFD1A0048 -#undef CRF_APB_APLL_FRAC_CFG_OFFSET -#define CRF_APB_APLL_FRAC_CFG_OFFSET 0XFD1A0028 #undef CRF_APB_DPLL_CFG_OFFSET #define CRF_APB_DPLL_CFG_OFFSET 0XFD1A0030 #undef CRF_APB_DPLL_CTRL_OFFSET @@ -89,8 +83,6 @@ #define CRF_APB_DPLL_CTRL_OFFSET 0XFD1A002C #undef CRF_APB_DPLL_TO_LPD_CTRL_OFFSET #define CRF_APB_DPLL_TO_LPD_CTRL_OFFSET 0XFD1A004C -#undef CRF_APB_DPLL_FRAC_CFG_OFFSET -#define CRF_APB_DPLL_FRAC_CFG_OFFSET 0XFD1A0034 #undef CRF_APB_VPLL_CFG_OFFSET #define CRF_APB_VPLL_CFG_OFFSET 0XFD1A003C #undef CRF_APB_VPLL_CTRL_OFFSET @@ -105,675 +97,770 @@ #define CRF_APB_VPLL_CTRL_OFFSET 0XFD1A0038 #undef CRF_APB_VPLL_TO_LPD_CTRL_OFFSET #define CRF_APB_VPLL_TO_LPD_CTRL_OFFSET 0XFD1A0050 -#undef CRF_APB_VPLL_FRAC_CFG_OFFSET -#define CRF_APB_VPLL_FRAC_CFG_OFFSET 0XFD1A0040 -/*PLL loop filter resistor control*/ +/* +* PLL loop filter resistor control +*/ #undef CRL_APB_RPLL_CFG_RES_DEFVAL #undef CRL_APB_RPLL_CFG_RES_SHIFT #undef CRL_APB_RPLL_CFG_RES_MASK -#define CRL_APB_RPLL_CFG_RES_DEFVAL 0x00000000 -#define CRL_APB_RPLL_CFG_RES_SHIFT 0 -#define CRL_APB_RPLL_CFG_RES_MASK 0x0000000FU +#define CRL_APB_RPLL_CFG_RES_DEFVAL 0x00000000 +#define CRL_APB_RPLL_CFG_RES_SHIFT 0 +#define CRL_APB_RPLL_CFG_RES_MASK 0x0000000FU -/*PLL charge pump control*/ +/* +* PLL charge pump control +*/ #undef CRL_APB_RPLL_CFG_CP_DEFVAL #undef CRL_APB_RPLL_CFG_CP_SHIFT #undef CRL_APB_RPLL_CFG_CP_MASK -#define CRL_APB_RPLL_CFG_CP_DEFVAL 0x00000000 -#define CRL_APB_RPLL_CFG_CP_SHIFT 5 -#define CRL_APB_RPLL_CFG_CP_MASK 0x000001E0U +#define CRL_APB_RPLL_CFG_CP_DEFVAL 0x00000000 +#define CRL_APB_RPLL_CFG_CP_SHIFT 5 +#define CRL_APB_RPLL_CFG_CP_MASK 0x000001E0U -/*PLL loop filter high frequency capacitor control*/ +/* +* PLL loop filter high frequency capacitor control +*/ #undef CRL_APB_RPLL_CFG_LFHF_DEFVAL #undef CRL_APB_RPLL_CFG_LFHF_SHIFT #undef CRL_APB_RPLL_CFG_LFHF_MASK -#define CRL_APB_RPLL_CFG_LFHF_DEFVAL 0x00000000 -#define CRL_APB_RPLL_CFG_LFHF_SHIFT 10 -#define CRL_APB_RPLL_CFG_LFHF_MASK 0x00000C00U +#define CRL_APB_RPLL_CFG_LFHF_DEFVAL 0x00000000 +#define CRL_APB_RPLL_CFG_LFHF_SHIFT 10 +#define CRL_APB_RPLL_CFG_LFHF_MASK 0x00000C00U -/*Lock circuit counter setting*/ +/* +* Lock circuit counter setting +*/ #undef CRL_APB_RPLL_CFG_LOCK_CNT_DEFVAL #undef CRL_APB_RPLL_CFG_LOCK_CNT_SHIFT #undef CRL_APB_RPLL_CFG_LOCK_CNT_MASK -#define CRL_APB_RPLL_CFG_LOCK_CNT_DEFVAL 0x00000000 -#define CRL_APB_RPLL_CFG_LOCK_CNT_SHIFT 13 -#define CRL_APB_RPLL_CFG_LOCK_CNT_MASK 0x007FE000U +#define CRL_APB_RPLL_CFG_LOCK_CNT_DEFVAL 0x00000000 +#define CRL_APB_RPLL_CFG_LOCK_CNT_SHIFT 13 +#define CRL_APB_RPLL_CFG_LOCK_CNT_MASK 0x007FE000U -/*Lock circuit configuration settings for lock windowsize*/ +/* +* Lock circuit configuration settings for lock windowsize +*/ #undef CRL_APB_RPLL_CFG_LOCK_DLY_DEFVAL #undef CRL_APB_RPLL_CFG_LOCK_DLY_SHIFT #undef CRL_APB_RPLL_CFG_LOCK_DLY_MASK -#define CRL_APB_RPLL_CFG_LOCK_DLY_DEFVAL 0x00000000 -#define CRL_APB_RPLL_CFG_LOCK_DLY_SHIFT 25 -#define CRL_APB_RPLL_CFG_LOCK_DLY_MASK 0xFE000000U +#define CRL_APB_RPLL_CFG_LOCK_DLY_DEFVAL 0x00000000 +#define CRL_APB_RPLL_CFG_LOCK_DLY_SHIFT 25 +#define CRL_APB_RPLL_CFG_LOCK_DLY_MASK 0xFE000000U -/*Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_ - ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source*/ +/* +* Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i + * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour + * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source +*/ #undef CRL_APB_RPLL_CTRL_PRE_SRC_DEFVAL #undef CRL_APB_RPLL_CTRL_PRE_SRC_SHIFT #undef CRL_APB_RPLL_CTRL_PRE_SRC_MASK -#define CRL_APB_RPLL_CTRL_PRE_SRC_DEFVAL 0x00012C09 -#define CRL_APB_RPLL_CTRL_PRE_SRC_SHIFT 20 -#define CRL_APB_RPLL_CTRL_PRE_SRC_MASK 0x00700000U +#define CRL_APB_RPLL_CTRL_PRE_SRC_DEFVAL 0x00012C09 +#define CRL_APB_RPLL_CTRL_PRE_SRC_SHIFT 20 +#define CRL_APB_RPLL_CTRL_PRE_SRC_MASK 0x00700000U -/*The integer portion of the feedback divider to the PLL*/ +/* +* The integer portion of the feedback divider to the PLL +*/ #undef CRL_APB_RPLL_CTRL_FBDIV_DEFVAL #undef CRL_APB_RPLL_CTRL_FBDIV_SHIFT #undef CRL_APB_RPLL_CTRL_FBDIV_MASK -#define CRL_APB_RPLL_CTRL_FBDIV_DEFVAL 0x00012C09 -#define CRL_APB_RPLL_CTRL_FBDIV_SHIFT 8 -#define CRL_APB_RPLL_CTRL_FBDIV_MASK 0x00007F00U +#define CRL_APB_RPLL_CTRL_FBDIV_DEFVAL 0x00012C09 +#define CRL_APB_RPLL_CTRL_FBDIV_SHIFT 8 +#define CRL_APB_RPLL_CTRL_FBDIV_MASK 0x00007F00U -/*This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency*/ +/* +* This turns on the divide by 2 that is inside of the PLL. This does not c + * hange the VCO frequency, just the output frequency +*/ #undef CRL_APB_RPLL_CTRL_DIV2_DEFVAL #undef CRL_APB_RPLL_CTRL_DIV2_SHIFT #undef CRL_APB_RPLL_CTRL_DIV2_MASK -#define CRL_APB_RPLL_CTRL_DIV2_DEFVAL 0x00012C09 -#define CRL_APB_RPLL_CTRL_DIV2_SHIFT 16 -#define CRL_APB_RPLL_CTRL_DIV2_MASK 0x00010000U +#define CRL_APB_RPLL_CTRL_DIV2_DEFVAL 0x00012C09 +#define CRL_APB_RPLL_CTRL_DIV2_SHIFT 16 +#define CRL_APB_RPLL_CTRL_DIV2_MASK 0x00010000U -/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/ +/* +* Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) +*/ #undef CRL_APB_RPLL_CTRL_BYPASS_DEFVAL #undef CRL_APB_RPLL_CTRL_BYPASS_SHIFT #undef CRL_APB_RPLL_CTRL_BYPASS_MASK -#define CRL_APB_RPLL_CTRL_BYPASS_DEFVAL 0x00012C09 -#define CRL_APB_RPLL_CTRL_BYPASS_SHIFT 3 -#define CRL_APB_RPLL_CTRL_BYPASS_MASK 0x00000008U +#define CRL_APB_RPLL_CTRL_BYPASS_DEFVAL 0x00012C09 +#define CRL_APB_RPLL_CTRL_BYPASS_SHIFT 3 +#define CRL_APB_RPLL_CTRL_BYPASS_MASK 0x00000008U -/*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/ +/* +* Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. +*/ #undef CRL_APB_RPLL_CTRL_RESET_DEFVAL #undef CRL_APB_RPLL_CTRL_RESET_SHIFT #undef CRL_APB_RPLL_CTRL_RESET_MASK -#define CRL_APB_RPLL_CTRL_RESET_DEFVAL 0x00012C09 -#define CRL_APB_RPLL_CTRL_RESET_SHIFT 0 -#define CRL_APB_RPLL_CTRL_RESET_MASK 0x00000001U +#define CRL_APB_RPLL_CTRL_RESET_DEFVAL 0x00012C09 +#define CRL_APB_RPLL_CTRL_RESET_SHIFT 0 +#define CRL_APB_RPLL_CTRL_RESET_MASK 0x00000001U -/*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/ +/* +* Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. +*/ #undef CRL_APB_RPLL_CTRL_RESET_DEFVAL #undef CRL_APB_RPLL_CTRL_RESET_SHIFT #undef CRL_APB_RPLL_CTRL_RESET_MASK -#define CRL_APB_RPLL_CTRL_RESET_DEFVAL 0x00012C09 -#define CRL_APB_RPLL_CTRL_RESET_SHIFT 0 -#define CRL_APB_RPLL_CTRL_RESET_MASK 0x00000001U +#define CRL_APB_RPLL_CTRL_RESET_DEFVAL 0x00012C09 +#define CRL_APB_RPLL_CTRL_RESET_SHIFT 0 +#define CRL_APB_RPLL_CTRL_RESET_MASK 0x00000001U -/*RPLL is locked*/ +/* +* RPLL is locked +*/ #undef CRL_APB_PLL_STATUS_RPLL_LOCK_DEFVAL #undef CRL_APB_PLL_STATUS_RPLL_LOCK_SHIFT #undef CRL_APB_PLL_STATUS_RPLL_LOCK_MASK -#define CRL_APB_PLL_STATUS_RPLL_LOCK_DEFVAL 0x00000018 -#define CRL_APB_PLL_STATUS_RPLL_LOCK_SHIFT 1 -#define CRL_APB_PLL_STATUS_RPLL_LOCK_MASK 0x00000002U +#define CRL_APB_PLL_STATUS_RPLL_LOCK_DEFVAL 0x00000018 +#define CRL_APB_PLL_STATUS_RPLL_LOCK_SHIFT 1 +#define CRL_APB_PLL_STATUS_RPLL_LOCK_MASK 0x00000002U #define CRL_APB_PLL_STATUS_OFFSET 0XFF5E0040 -/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/ +/* +* Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) +*/ #undef CRL_APB_RPLL_CTRL_BYPASS_DEFVAL #undef CRL_APB_RPLL_CTRL_BYPASS_SHIFT #undef CRL_APB_RPLL_CTRL_BYPASS_MASK -#define CRL_APB_RPLL_CTRL_BYPASS_DEFVAL 0x00012C09 -#define CRL_APB_RPLL_CTRL_BYPASS_SHIFT 3 -#define CRL_APB_RPLL_CTRL_BYPASS_MASK 0x00000008U +#define CRL_APB_RPLL_CTRL_BYPASS_DEFVAL 0x00012C09 +#define CRL_APB_RPLL_CTRL_BYPASS_SHIFT 3 +#define CRL_APB_RPLL_CTRL_BYPASS_MASK 0x00000008U -/*Divisor value for this clock.*/ +/* +* Divisor value for this clock. +*/ #undef CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL #undef CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_SHIFT #undef CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_MASK -#define CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL 0x00000400 -#define CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL 0x00000400 +#define CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_MASK 0x00003F00U -/*Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona - mode and uses DATA of this register for the fractional portion of the feedback divider.*/ -#undef CRL_APB_RPLL_FRAC_CFG_ENABLED_DEFVAL -#undef CRL_APB_RPLL_FRAC_CFG_ENABLED_SHIFT -#undef CRL_APB_RPLL_FRAC_CFG_ENABLED_MASK -#define CRL_APB_RPLL_FRAC_CFG_ENABLED_DEFVAL 0x00000000 -#define CRL_APB_RPLL_FRAC_CFG_ENABLED_SHIFT 31 -#define CRL_APB_RPLL_FRAC_CFG_ENABLED_MASK 0x80000000U - -/*Fractional value for the Feedback value.*/ -#undef CRL_APB_RPLL_FRAC_CFG_DATA_DEFVAL -#undef CRL_APB_RPLL_FRAC_CFG_DATA_SHIFT -#undef CRL_APB_RPLL_FRAC_CFG_DATA_MASK -#define CRL_APB_RPLL_FRAC_CFG_DATA_DEFVAL 0x00000000 -#define CRL_APB_RPLL_FRAC_CFG_DATA_SHIFT 0 -#define CRL_APB_RPLL_FRAC_CFG_DATA_MASK 0x0000FFFFU - -/*PLL loop filter resistor control*/ +/* +* PLL loop filter resistor control +*/ #undef CRL_APB_IOPLL_CFG_RES_DEFVAL #undef CRL_APB_IOPLL_CFG_RES_SHIFT #undef CRL_APB_IOPLL_CFG_RES_MASK -#define CRL_APB_IOPLL_CFG_RES_DEFVAL 0x00000000 -#define CRL_APB_IOPLL_CFG_RES_SHIFT 0 -#define CRL_APB_IOPLL_CFG_RES_MASK 0x0000000FU +#define CRL_APB_IOPLL_CFG_RES_DEFVAL 0x00000000 +#define CRL_APB_IOPLL_CFG_RES_SHIFT 0 +#define CRL_APB_IOPLL_CFG_RES_MASK 0x0000000FU -/*PLL charge pump control*/ +/* +* PLL charge pump control +*/ #undef CRL_APB_IOPLL_CFG_CP_DEFVAL #undef CRL_APB_IOPLL_CFG_CP_SHIFT #undef CRL_APB_IOPLL_CFG_CP_MASK -#define CRL_APB_IOPLL_CFG_CP_DEFVAL 0x00000000 -#define CRL_APB_IOPLL_CFG_CP_SHIFT 5 -#define CRL_APB_IOPLL_CFG_CP_MASK 0x000001E0U +#define CRL_APB_IOPLL_CFG_CP_DEFVAL 0x00000000 +#define CRL_APB_IOPLL_CFG_CP_SHIFT 5 +#define CRL_APB_IOPLL_CFG_CP_MASK 0x000001E0U -/*PLL loop filter high frequency capacitor control*/ +/* +* PLL loop filter high frequency capacitor control +*/ #undef CRL_APB_IOPLL_CFG_LFHF_DEFVAL #undef CRL_APB_IOPLL_CFG_LFHF_SHIFT #undef CRL_APB_IOPLL_CFG_LFHF_MASK -#define CRL_APB_IOPLL_CFG_LFHF_DEFVAL 0x00000000 -#define CRL_APB_IOPLL_CFG_LFHF_SHIFT 10 -#define CRL_APB_IOPLL_CFG_LFHF_MASK 0x00000C00U +#define CRL_APB_IOPLL_CFG_LFHF_DEFVAL 0x00000000 +#define CRL_APB_IOPLL_CFG_LFHF_SHIFT 10 +#define CRL_APB_IOPLL_CFG_LFHF_MASK 0x00000C00U -/*Lock circuit counter setting*/ +/* +* Lock circuit counter setting +*/ #undef CRL_APB_IOPLL_CFG_LOCK_CNT_DEFVAL #undef CRL_APB_IOPLL_CFG_LOCK_CNT_SHIFT #undef CRL_APB_IOPLL_CFG_LOCK_CNT_MASK -#define CRL_APB_IOPLL_CFG_LOCK_CNT_DEFVAL 0x00000000 -#define CRL_APB_IOPLL_CFG_LOCK_CNT_SHIFT 13 -#define CRL_APB_IOPLL_CFG_LOCK_CNT_MASK 0x007FE000U +#define CRL_APB_IOPLL_CFG_LOCK_CNT_DEFVAL 0x00000000 +#define CRL_APB_IOPLL_CFG_LOCK_CNT_SHIFT 13 +#define CRL_APB_IOPLL_CFG_LOCK_CNT_MASK 0x007FE000U -/*Lock circuit configuration settings for lock windowsize*/ +/* +* Lock circuit configuration settings for lock windowsize +*/ #undef CRL_APB_IOPLL_CFG_LOCK_DLY_DEFVAL #undef CRL_APB_IOPLL_CFG_LOCK_DLY_SHIFT #undef CRL_APB_IOPLL_CFG_LOCK_DLY_MASK -#define CRL_APB_IOPLL_CFG_LOCK_DLY_DEFVAL 0x00000000 -#define CRL_APB_IOPLL_CFG_LOCK_DLY_SHIFT 25 -#define CRL_APB_IOPLL_CFG_LOCK_DLY_MASK 0xFE000000U +#define CRL_APB_IOPLL_CFG_LOCK_DLY_DEFVAL 0x00000000 +#define CRL_APB_IOPLL_CFG_LOCK_DLY_SHIFT 25 +#define CRL_APB_IOPLL_CFG_LOCK_DLY_MASK 0xFE000000U -/*Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_ - ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source*/ +/* +* Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i + * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour + * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source +*/ #undef CRL_APB_IOPLL_CTRL_PRE_SRC_DEFVAL #undef CRL_APB_IOPLL_CTRL_PRE_SRC_SHIFT #undef CRL_APB_IOPLL_CTRL_PRE_SRC_MASK -#define CRL_APB_IOPLL_CTRL_PRE_SRC_DEFVAL 0x00012C09 -#define CRL_APB_IOPLL_CTRL_PRE_SRC_SHIFT 20 -#define CRL_APB_IOPLL_CTRL_PRE_SRC_MASK 0x00700000U +#define CRL_APB_IOPLL_CTRL_PRE_SRC_DEFVAL 0x00012C09 +#define CRL_APB_IOPLL_CTRL_PRE_SRC_SHIFT 20 +#define CRL_APB_IOPLL_CTRL_PRE_SRC_MASK 0x00700000U -/*The integer portion of the feedback divider to the PLL*/ +/* +* The integer portion of the feedback divider to the PLL +*/ #undef CRL_APB_IOPLL_CTRL_FBDIV_DEFVAL #undef CRL_APB_IOPLL_CTRL_FBDIV_SHIFT #undef CRL_APB_IOPLL_CTRL_FBDIV_MASK -#define CRL_APB_IOPLL_CTRL_FBDIV_DEFVAL 0x00012C09 -#define CRL_APB_IOPLL_CTRL_FBDIV_SHIFT 8 -#define CRL_APB_IOPLL_CTRL_FBDIV_MASK 0x00007F00U +#define CRL_APB_IOPLL_CTRL_FBDIV_DEFVAL 0x00012C09 +#define CRL_APB_IOPLL_CTRL_FBDIV_SHIFT 8 +#define CRL_APB_IOPLL_CTRL_FBDIV_MASK 0x00007F00U -/*This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency*/ +/* +* This turns on the divide by 2 that is inside of the PLL. This does not c + * hange the VCO frequency, just the output frequency +*/ #undef CRL_APB_IOPLL_CTRL_DIV2_DEFVAL #undef CRL_APB_IOPLL_CTRL_DIV2_SHIFT #undef CRL_APB_IOPLL_CTRL_DIV2_MASK -#define CRL_APB_IOPLL_CTRL_DIV2_DEFVAL 0x00012C09 -#define CRL_APB_IOPLL_CTRL_DIV2_SHIFT 16 -#define CRL_APB_IOPLL_CTRL_DIV2_MASK 0x00010000U +#define CRL_APB_IOPLL_CTRL_DIV2_DEFVAL 0x00012C09 +#define CRL_APB_IOPLL_CTRL_DIV2_SHIFT 16 +#define CRL_APB_IOPLL_CTRL_DIV2_MASK 0x00010000U -/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/ +/* +* Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) +*/ #undef CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL #undef CRL_APB_IOPLL_CTRL_BYPASS_SHIFT #undef CRL_APB_IOPLL_CTRL_BYPASS_MASK -#define CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL 0x00012C09 -#define CRL_APB_IOPLL_CTRL_BYPASS_SHIFT 3 -#define CRL_APB_IOPLL_CTRL_BYPASS_MASK 0x00000008U +#define CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL 0x00012C09 +#define CRL_APB_IOPLL_CTRL_BYPASS_SHIFT 3 +#define CRL_APB_IOPLL_CTRL_BYPASS_MASK 0x00000008U -/*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/ +/* +* Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. +*/ #undef CRL_APB_IOPLL_CTRL_RESET_DEFVAL #undef CRL_APB_IOPLL_CTRL_RESET_SHIFT #undef CRL_APB_IOPLL_CTRL_RESET_MASK -#define CRL_APB_IOPLL_CTRL_RESET_DEFVAL 0x00012C09 -#define CRL_APB_IOPLL_CTRL_RESET_SHIFT 0 -#define CRL_APB_IOPLL_CTRL_RESET_MASK 0x00000001U +#define CRL_APB_IOPLL_CTRL_RESET_DEFVAL 0x00012C09 +#define CRL_APB_IOPLL_CTRL_RESET_SHIFT 0 +#define CRL_APB_IOPLL_CTRL_RESET_MASK 0x00000001U -/*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/ +/* +* Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. +*/ #undef CRL_APB_IOPLL_CTRL_RESET_DEFVAL #undef CRL_APB_IOPLL_CTRL_RESET_SHIFT #undef CRL_APB_IOPLL_CTRL_RESET_MASK -#define CRL_APB_IOPLL_CTRL_RESET_DEFVAL 0x00012C09 -#define CRL_APB_IOPLL_CTRL_RESET_SHIFT 0 -#define CRL_APB_IOPLL_CTRL_RESET_MASK 0x00000001U +#define CRL_APB_IOPLL_CTRL_RESET_DEFVAL 0x00012C09 +#define CRL_APB_IOPLL_CTRL_RESET_SHIFT 0 +#define CRL_APB_IOPLL_CTRL_RESET_MASK 0x00000001U -/*IOPLL is locked*/ +/* +* IOPLL is locked +*/ #undef CRL_APB_PLL_STATUS_IOPLL_LOCK_DEFVAL #undef CRL_APB_PLL_STATUS_IOPLL_LOCK_SHIFT #undef CRL_APB_PLL_STATUS_IOPLL_LOCK_MASK -#define CRL_APB_PLL_STATUS_IOPLL_LOCK_DEFVAL 0x00000018 -#define CRL_APB_PLL_STATUS_IOPLL_LOCK_SHIFT 0 -#define CRL_APB_PLL_STATUS_IOPLL_LOCK_MASK 0x00000001U +#define CRL_APB_PLL_STATUS_IOPLL_LOCK_DEFVAL 0x00000018 +#define CRL_APB_PLL_STATUS_IOPLL_LOCK_SHIFT 0 +#define CRL_APB_PLL_STATUS_IOPLL_LOCK_MASK 0x00000001U #define CRL_APB_PLL_STATUS_OFFSET 0XFF5E0040 -/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/ +/* +* Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) +*/ #undef CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL #undef CRL_APB_IOPLL_CTRL_BYPASS_SHIFT #undef CRL_APB_IOPLL_CTRL_BYPASS_MASK -#define CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL 0x00012C09 -#define CRL_APB_IOPLL_CTRL_BYPASS_SHIFT 3 -#define CRL_APB_IOPLL_CTRL_BYPASS_MASK 0x00000008U +#define CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL 0x00012C09 +#define CRL_APB_IOPLL_CTRL_BYPASS_SHIFT 3 +#define CRL_APB_IOPLL_CTRL_BYPASS_MASK 0x00000008U -/*Divisor value for this clock.*/ +/* +* Divisor value for this clock. +*/ #undef CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL #undef CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_SHIFT #undef CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_MASK -#define CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL 0x00000400 -#define CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL 0x00000400 +#define CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_MASK 0x00003F00U -/*Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona - mode and uses DATA of this register for the fractional portion of the feedback divider.*/ -#undef CRL_APB_IOPLL_FRAC_CFG_ENABLED_DEFVAL -#undef CRL_APB_IOPLL_FRAC_CFG_ENABLED_SHIFT -#undef CRL_APB_IOPLL_FRAC_CFG_ENABLED_MASK -#define CRL_APB_IOPLL_FRAC_CFG_ENABLED_DEFVAL 0x00000000 -#define CRL_APB_IOPLL_FRAC_CFG_ENABLED_SHIFT 31 -#define CRL_APB_IOPLL_FRAC_CFG_ENABLED_MASK 0x80000000U - -/*Fractional value for the Feedback value.*/ -#undef CRL_APB_IOPLL_FRAC_CFG_DATA_DEFVAL -#undef CRL_APB_IOPLL_FRAC_CFG_DATA_SHIFT -#undef CRL_APB_IOPLL_FRAC_CFG_DATA_MASK -#define CRL_APB_IOPLL_FRAC_CFG_DATA_DEFVAL 0x00000000 -#define CRL_APB_IOPLL_FRAC_CFG_DATA_SHIFT 0 -#define CRL_APB_IOPLL_FRAC_CFG_DATA_MASK 0x0000FFFFU - -/*PLL loop filter resistor control*/ +/* +* PLL loop filter resistor control +*/ #undef CRF_APB_APLL_CFG_RES_DEFVAL #undef CRF_APB_APLL_CFG_RES_SHIFT #undef CRF_APB_APLL_CFG_RES_MASK -#define CRF_APB_APLL_CFG_RES_DEFVAL 0x00000000 -#define CRF_APB_APLL_CFG_RES_SHIFT 0 -#define CRF_APB_APLL_CFG_RES_MASK 0x0000000FU +#define CRF_APB_APLL_CFG_RES_DEFVAL 0x00000000 +#define CRF_APB_APLL_CFG_RES_SHIFT 0 +#define CRF_APB_APLL_CFG_RES_MASK 0x0000000FU -/*PLL charge pump control*/ +/* +* PLL charge pump control +*/ #undef CRF_APB_APLL_CFG_CP_DEFVAL #undef CRF_APB_APLL_CFG_CP_SHIFT #undef CRF_APB_APLL_CFG_CP_MASK -#define CRF_APB_APLL_CFG_CP_DEFVAL 0x00000000 -#define CRF_APB_APLL_CFG_CP_SHIFT 5 -#define CRF_APB_APLL_CFG_CP_MASK 0x000001E0U +#define CRF_APB_APLL_CFG_CP_DEFVAL 0x00000000 +#define CRF_APB_APLL_CFG_CP_SHIFT 5 +#define CRF_APB_APLL_CFG_CP_MASK 0x000001E0U -/*PLL loop filter high frequency capacitor control*/ +/* +* PLL loop filter high frequency capacitor control +*/ #undef CRF_APB_APLL_CFG_LFHF_DEFVAL #undef CRF_APB_APLL_CFG_LFHF_SHIFT #undef CRF_APB_APLL_CFG_LFHF_MASK -#define CRF_APB_APLL_CFG_LFHF_DEFVAL 0x00000000 -#define CRF_APB_APLL_CFG_LFHF_SHIFT 10 -#define CRF_APB_APLL_CFG_LFHF_MASK 0x00000C00U +#define CRF_APB_APLL_CFG_LFHF_DEFVAL 0x00000000 +#define CRF_APB_APLL_CFG_LFHF_SHIFT 10 +#define CRF_APB_APLL_CFG_LFHF_MASK 0x00000C00U -/*Lock circuit counter setting*/ +/* +* Lock circuit counter setting +*/ #undef CRF_APB_APLL_CFG_LOCK_CNT_DEFVAL #undef CRF_APB_APLL_CFG_LOCK_CNT_SHIFT #undef CRF_APB_APLL_CFG_LOCK_CNT_MASK -#define CRF_APB_APLL_CFG_LOCK_CNT_DEFVAL 0x00000000 -#define CRF_APB_APLL_CFG_LOCK_CNT_SHIFT 13 -#define CRF_APB_APLL_CFG_LOCK_CNT_MASK 0x007FE000U +#define CRF_APB_APLL_CFG_LOCK_CNT_DEFVAL 0x00000000 +#define CRF_APB_APLL_CFG_LOCK_CNT_SHIFT 13 +#define CRF_APB_APLL_CFG_LOCK_CNT_MASK 0x007FE000U -/*Lock circuit configuration settings for lock windowsize*/ +/* +* Lock circuit configuration settings for lock windowsize +*/ #undef CRF_APB_APLL_CFG_LOCK_DLY_DEFVAL #undef CRF_APB_APLL_CFG_LOCK_DLY_SHIFT #undef CRF_APB_APLL_CFG_LOCK_DLY_MASK -#define CRF_APB_APLL_CFG_LOCK_DLY_DEFVAL 0x00000000 -#define CRF_APB_APLL_CFG_LOCK_DLY_SHIFT 25 -#define CRF_APB_APLL_CFG_LOCK_DLY_MASK 0xFE000000U +#define CRF_APB_APLL_CFG_LOCK_DLY_DEFVAL 0x00000000 +#define CRF_APB_APLL_CFG_LOCK_DLY_SHIFT 25 +#define CRF_APB_APLL_CFG_LOCK_DLY_MASK 0xFE000000U -/*Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_ - ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source*/ +/* +* Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i + * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour + * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source +*/ #undef CRF_APB_APLL_CTRL_PRE_SRC_DEFVAL #undef CRF_APB_APLL_CTRL_PRE_SRC_SHIFT #undef CRF_APB_APLL_CTRL_PRE_SRC_MASK -#define CRF_APB_APLL_CTRL_PRE_SRC_DEFVAL 0x00012C09 -#define CRF_APB_APLL_CTRL_PRE_SRC_SHIFT 20 -#define CRF_APB_APLL_CTRL_PRE_SRC_MASK 0x00700000U +#define CRF_APB_APLL_CTRL_PRE_SRC_DEFVAL 0x00012C09 +#define CRF_APB_APLL_CTRL_PRE_SRC_SHIFT 20 +#define CRF_APB_APLL_CTRL_PRE_SRC_MASK 0x00700000U -/*The integer portion of the feedback divider to the PLL*/ +/* +* The integer portion of the feedback divider to the PLL +*/ #undef CRF_APB_APLL_CTRL_FBDIV_DEFVAL #undef CRF_APB_APLL_CTRL_FBDIV_SHIFT #undef CRF_APB_APLL_CTRL_FBDIV_MASK -#define CRF_APB_APLL_CTRL_FBDIV_DEFVAL 0x00012C09 -#define CRF_APB_APLL_CTRL_FBDIV_SHIFT 8 -#define CRF_APB_APLL_CTRL_FBDIV_MASK 0x00007F00U +#define CRF_APB_APLL_CTRL_FBDIV_DEFVAL 0x00012C09 +#define CRF_APB_APLL_CTRL_FBDIV_SHIFT 8 +#define CRF_APB_APLL_CTRL_FBDIV_MASK 0x00007F00U -/*This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency*/ +/* +* This turns on the divide by 2 that is inside of the PLL. This does not c + * hange the VCO frequency, just the output frequency +*/ #undef CRF_APB_APLL_CTRL_DIV2_DEFVAL #undef CRF_APB_APLL_CTRL_DIV2_SHIFT #undef CRF_APB_APLL_CTRL_DIV2_MASK -#define CRF_APB_APLL_CTRL_DIV2_DEFVAL 0x00012C09 -#define CRF_APB_APLL_CTRL_DIV2_SHIFT 16 -#define CRF_APB_APLL_CTRL_DIV2_MASK 0x00010000U +#define CRF_APB_APLL_CTRL_DIV2_DEFVAL 0x00012C09 +#define CRF_APB_APLL_CTRL_DIV2_SHIFT 16 +#define CRF_APB_APLL_CTRL_DIV2_MASK 0x00010000U -/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/ +/* +* Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) +*/ #undef CRF_APB_APLL_CTRL_BYPASS_DEFVAL #undef CRF_APB_APLL_CTRL_BYPASS_SHIFT #undef CRF_APB_APLL_CTRL_BYPASS_MASK -#define CRF_APB_APLL_CTRL_BYPASS_DEFVAL 0x00012C09 -#define CRF_APB_APLL_CTRL_BYPASS_SHIFT 3 -#define CRF_APB_APLL_CTRL_BYPASS_MASK 0x00000008U +#define CRF_APB_APLL_CTRL_BYPASS_DEFVAL 0x00012C09 +#define CRF_APB_APLL_CTRL_BYPASS_SHIFT 3 +#define CRF_APB_APLL_CTRL_BYPASS_MASK 0x00000008U -/*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/ +/* +* Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. +*/ #undef CRF_APB_APLL_CTRL_RESET_DEFVAL #undef CRF_APB_APLL_CTRL_RESET_SHIFT #undef CRF_APB_APLL_CTRL_RESET_MASK -#define CRF_APB_APLL_CTRL_RESET_DEFVAL 0x00012C09 -#define CRF_APB_APLL_CTRL_RESET_SHIFT 0 -#define CRF_APB_APLL_CTRL_RESET_MASK 0x00000001U +#define CRF_APB_APLL_CTRL_RESET_DEFVAL 0x00012C09 +#define CRF_APB_APLL_CTRL_RESET_SHIFT 0 +#define CRF_APB_APLL_CTRL_RESET_MASK 0x00000001U -/*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/ +/* +* Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. +*/ #undef CRF_APB_APLL_CTRL_RESET_DEFVAL #undef CRF_APB_APLL_CTRL_RESET_SHIFT #undef CRF_APB_APLL_CTRL_RESET_MASK -#define CRF_APB_APLL_CTRL_RESET_DEFVAL 0x00012C09 -#define CRF_APB_APLL_CTRL_RESET_SHIFT 0 -#define CRF_APB_APLL_CTRL_RESET_MASK 0x00000001U +#define CRF_APB_APLL_CTRL_RESET_DEFVAL 0x00012C09 +#define CRF_APB_APLL_CTRL_RESET_SHIFT 0 +#define CRF_APB_APLL_CTRL_RESET_MASK 0x00000001U -/*APLL is locked*/ +/* +* APLL is locked +*/ #undef CRF_APB_PLL_STATUS_APLL_LOCK_DEFVAL #undef CRF_APB_PLL_STATUS_APLL_LOCK_SHIFT #undef CRF_APB_PLL_STATUS_APLL_LOCK_MASK -#define CRF_APB_PLL_STATUS_APLL_LOCK_DEFVAL 0x00000038 -#define CRF_APB_PLL_STATUS_APLL_LOCK_SHIFT 0 -#define CRF_APB_PLL_STATUS_APLL_LOCK_MASK 0x00000001U +#define CRF_APB_PLL_STATUS_APLL_LOCK_DEFVAL 0x00000038 +#define CRF_APB_PLL_STATUS_APLL_LOCK_SHIFT 0 +#define CRF_APB_PLL_STATUS_APLL_LOCK_MASK 0x00000001U #define CRF_APB_PLL_STATUS_OFFSET 0XFD1A0044 -/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/ +/* +* Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) +*/ #undef CRF_APB_APLL_CTRL_BYPASS_DEFVAL #undef CRF_APB_APLL_CTRL_BYPASS_SHIFT #undef CRF_APB_APLL_CTRL_BYPASS_MASK -#define CRF_APB_APLL_CTRL_BYPASS_DEFVAL 0x00012C09 -#define CRF_APB_APLL_CTRL_BYPASS_SHIFT 3 -#define CRF_APB_APLL_CTRL_BYPASS_MASK 0x00000008U +#define CRF_APB_APLL_CTRL_BYPASS_DEFVAL 0x00012C09 +#define CRF_APB_APLL_CTRL_BYPASS_SHIFT 3 +#define CRF_APB_APLL_CTRL_BYPASS_MASK 0x00000008U -/*Divisor value for this clock.*/ +/* +* Divisor value for this clock. +*/ #undef CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_DEFVAL #undef CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_SHIFT #undef CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_MASK -#define CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_DEFVAL 0x00000400 -#define CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_SHIFT 8 -#define CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_DEFVAL 0x00000400 +#define CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_MASK 0x00003F00U -/*Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona - mode and uses DATA of this register for the fractional portion of the feedback divider.*/ -#undef CRF_APB_APLL_FRAC_CFG_ENABLED_DEFVAL -#undef CRF_APB_APLL_FRAC_CFG_ENABLED_SHIFT -#undef CRF_APB_APLL_FRAC_CFG_ENABLED_MASK -#define CRF_APB_APLL_FRAC_CFG_ENABLED_DEFVAL 0x00000000 -#define CRF_APB_APLL_FRAC_CFG_ENABLED_SHIFT 31 -#define CRF_APB_APLL_FRAC_CFG_ENABLED_MASK 0x80000000U - -/*Fractional value for the Feedback value.*/ -#undef CRF_APB_APLL_FRAC_CFG_DATA_DEFVAL -#undef CRF_APB_APLL_FRAC_CFG_DATA_SHIFT -#undef CRF_APB_APLL_FRAC_CFG_DATA_MASK -#define CRF_APB_APLL_FRAC_CFG_DATA_DEFVAL 0x00000000 -#define CRF_APB_APLL_FRAC_CFG_DATA_SHIFT 0 -#define CRF_APB_APLL_FRAC_CFG_DATA_MASK 0x0000FFFFU - -/*PLL loop filter resistor control*/ +/* +* PLL loop filter resistor control +*/ #undef CRF_APB_DPLL_CFG_RES_DEFVAL #undef CRF_APB_DPLL_CFG_RES_SHIFT #undef CRF_APB_DPLL_CFG_RES_MASK -#define CRF_APB_DPLL_CFG_RES_DEFVAL 0x00000000 -#define CRF_APB_DPLL_CFG_RES_SHIFT 0 -#define CRF_APB_DPLL_CFG_RES_MASK 0x0000000FU +#define CRF_APB_DPLL_CFG_RES_DEFVAL 0x00000000 +#define CRF_APB_DPLL_CFG_RES_SHIFT 0 +#define CRF_APB_DPLL_CFG_RES_MASK 0x0000000FU -/*PLL charge pump control*/ +/* +* PLL charge pump control +*/ #undef CRF_APB_DPLL_CFG_CP_DEFVAL #undef CRF_APB_DPLL_CFG_CP_SHIFT #undef CRF_APB_DPLL_CFG_CP_MASK -#define CRF_APB_DPLL_CFG_CP_DEFVAL 0x00000000 -#define CRF_APB_DPLL_CFG_CP_SHIFT 5 -#define CRF_APB_DPLL_CFG_CP_MASK 0x000001E0U +#define CRF_APB_DPLL_CFG_CP_DEFVAL 0x00000000 +#define CRF_APB_DPLL_CFG_CP_SHIFT 5 +#define CRF_APB_DPLL_CFG_CP_MASK 0x000001E0U -/*PLL loop filter high frequency capacitor control*/ +/* +* PLL loop filter high frequency capacitor control +*/ #undef CRF_APB_DPLL_CFG_LFHF_DEFVAL #undef CRF_APB_DPLL_CFG_LFHF_SHIFT #undef CRF_APB_DPLL_CFG_LFHF_MASK -#define CRF_APB_DPLL_CFG_LFHF_DEFVAL 0x00000000 -#define CRF_APB_DPLL_CFG_LFHF_SHIFT 10 -#define CRF_APB_DPLL_CFG_LFHF_MASK 0x00000C00U +#define CRF_APB_DPLL_CFG_LFHF_DEFVAL 0x00000000 +#define CRF_APB_DPLL_CFG_LFHF_SHIFT 10 +#define CRF_APB_DPLL_CFG_LFHF_MASK 0x00000C00U -/*Lock circuit counter setting*/ +/* +* Lock circuit counter setting +*/ #undef CRF_APB_DPLL_CFG_LOCK_CNT_DEFVAL #undef CRF_APB_DPLL_CFG_LOCK_CNT_SHIFT #undef CRF_APB_DPLL_CFG_LOCK_CNT_MASK -#define CRF_APB_DPLL_CFG_LOCK_CNT_DEFVAL 0x00000000 -#define CRF_APB_DPLL_CFG_LOCK_CNT_SHIFT 13 -#define CRF_APB_DPLL_CFG_LOCK_CNT_MASK 0x007FE000U +#define CRF_APB_DPLL_CFG_LOCK_CNT_DEFVAL 0x00000000 +#define CRF_APB_DPLL_CFG_LOCK_CNT_SHIFT 13 +#define CRF_APB_DPLL_CFG_LOCK_CNT_MASK 0x007FE000U -/*Lock circuit configuration settings for lock windowsize*/ +/* +* Lock circuit configuration settings for lock windowsize +*/ #undef CRF_APB_DPLL_CFG_LOCK_DLY_DEFVAL #undef CRF_APB_DPLL_CFG_LOCK_DLY_SHIFT #undef CRF_APB_DPLL_CFG_LOCK_DLY_MASK -#define CRF_APB_DPLL_CFG_LOCK_DLY_DEFVAL 0x00000000 -#define CRF_APB_DPLL_CFG_LOCK_DLY_SHIFT 25 -#define CRF_APB_DPLL_CFG_LOCK_DLY_MASK 0xFE000000U +#define CRF_APB_DPLL_CFG_LOCK_DLY_DEFVAL 0x00000000 +#define CRF_APB_DPLL_CFG_LOCK_DLY_SHIFT 25 +#define CRF_APB_DPLL_CFG_LOCK_DLY_MASK 0xFE000000U -/*Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_ - ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source*/ +/* +* Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i + * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour + * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source +*/ #undef CRF_APB_DPLL_CTRL_PRE_SRC_DEFVAL #undef CRF_APB_DPLL_CTRL_PRE_SRC_SHIFT #undef CRF_APB_DPLL_CTRL_PRE_SRC_MASK -#define CRF_APB_DPLL_CTRL_PRE_SRC_DEFVAL 0x00002C09 -#define CRF_APB_DPLL_CTRL_PRE_SRC_SHIFT 20 -#define CRF_APB_DPLL_CTRL_PRE_SRC_MASK 0x00700000U +#define CRF_APB_DPLL_CTRL_PRE_SRC_DEFVAL 0x00002C09 +#define CRF_APB_DPLL_CTRL_PRE_SRC_SHIFT 20 +#define CRF_APB_DPLL_CTRL_PRE_SRC_MASK 0x00700000U -/*The integer portion of the feedback divider to the PLL*/ +/* +* The integer portion of the feedback divider to the PLL +*/ #undef CRF_APB_DPLL_CTRL_FBDIV_DEFVAL #undef CRF_APB_DPLL_CTRL_FBDIV_SHIFT #undef CRF_APB_DPLL_CTRL_FBDIV_MASK -#define CRF_APB_DPLL_CTRL_FBDIV_DEFVAL 0x00002C09 -#define CRF_APB_DPLL_CTRL_FBDIV_SHIFT 8 -#define CRF_APB_DPLL_CTRL_FBDIV_MASK 0x00007F00U +#define CRF_APB_DPLL_CTRL_FBDIV_DEFVAL 0x00002C09 +#define CRF_APB_DPLL_CTRL_FBDIV_SHIFT 8 +#define CRF_APB_DPLL_CTRL_FBDIV_MASK 0x00007F00U -/*This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency*/ +/* +* This turns on the divide by 2 that is inside of the PLL. This does not c + * hange the VCO frequency, just the output frequency +*/ #undef CRF_APB_DPLL_CTRL_DIV2_DEFVAL #undef CRF_APB_DPLL_CTRL_DIV2_SHIFT #undef CRF_APB_DPLL_CTRL_DIV2_MASK -#define CRF_APB_DPLL_CTRL_DIV2_DEFVAL 0x00002C09 -#define CRF_APB_DPLL_CTRL_DIV2_SHIFT 16 -#define CRF_APB_DPLL_CTRL_DIV2_MASK 0x00010000U +#define CRF_APB_DPLL_CTRL_DIV2_DEFVAL 0x00002C09 +#define CRF_APB_DPLL_CTRL_DIV2_SHIFT 16 +#define CRF_APB_DPLL_CTRL_DIV2_MASK 0x00010000U -/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/ +/* +* Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) +*/ #undef CRF_APB_DPLL_CTRL_BYPASS_DEFVAL #undef CRF_APB_DPLL_CTRL_BYPASS_SHIFT #undef CRF_APB_DPLL_CTRL_BYPASS_MASK -#define CRF_APB_DPLL_CTRL_BYPASS_DEFVAL 0x00002C09 -#define CRF_APB_DPLL_CTRL_BYPASS_SHIFT 3 -#define CRF_APB_DPLL_CTRL_BYPASS_MASK 0x00000008U +#define CRF_APB_DPLL_CTRL_BYPASS_DEFVAL 0x00002C09 +#define CRF_APB_DPLL_CTRL_BYPASS_SHIFT 3 +#define CRF_APB_DPLL_CTRL_BYPASS_MASK 0x00000008U -/*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/ +/* +* Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. +*/ #undef CRF_APB_DPLL_CTRL_RESET_DEFVAL #undef CRF_APB_DPLL_CTRL_RESET_SHIFT #undef CRF_APB_DPLL_CTRL_RESET_MASK -#define CRF_APB_DPLL_CTRL_RESET_DEFVAL 0x00002C09 -#define CRF_APB_DPLL_CTRL_RESET_SHIFT 0 -#define CRF_APB_DPLL_CTRL_RESET_MASK 0x00000001U +#define CRF_APB_DPLL_CTRL_RESET_DEFVAL 0x00002C09 +#define CRF_APB_DPLL_CTRL_RESET_SHIFT 0 +#define CRF_APB_DPLL_CTRL_RESET_MASK 0x00000001U -/*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/ +/* +* Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. +*/ #undef CRF_APB_DPLL_CTRL_RESET_DEFVAL #undef CRF_APB_DPLL_CTRL_RESET_SHIFT #undef CRF_APB_DPLL_CTRL_RESET_MASK -#define CRF_APB_DPLL_CTRL_RESET_DEFVAL 0x00002C09 -#define CRF_APB_DPLL_CTRL_RESET_SHIFT 0 -#define CRF_APB_DPLL_CTRL_RESET_MASK 0x00000001U +#define CRF_APB_DPLL_CTRL_RESET_DEFVAL 0x00002C09 +#define CRF_APB_DPLL_CTRL_RESET_SHIFT 0 +#define CRF_APB_DPLL_CTRL_RESET_MASK 0x00000001U -/*DPLL is locked*/ +/* +* DPLL is locked +*/ #undef CRF_APB_PLL_STATUS_DPLL_LOCK_DEFVAL #undef CRF_APB_PLL_STATUS_DPLL_LOCK_SHIFT #undef CRF_APB_PLL_STATUS_DPLL_LOCK_MASK -#define CRF_APB_PLL_STATUS_DPLL_LOCK_DEFVAL 0x00000038 -#define CRF_APB_PLL_STATUS_DPLL_LOCK_SHIFT 1 -#define CRF_APB_PLL_STATUS_DPLL_LOCK_MASK 0x00000002U +#define CRF_APB_PLL_STATUS_DPLL_LOCK_DEFVAL 0x00000038 +#define CRF_APB_PLL_STATUS_DPLL_LOCK_SHIFT 1 +#define CRF_APB_PLL_STATUS_DPLL_LOCK_MASK 0x00000002U #define CRF_APB_PLL_STATUS_OFFSET 0XFD1A0044 -/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/ +/* +* Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) +*/ #undef CRF_APB_DPLL_CTRL_BYPASS_DEFVAL #undef CRF_APB_DPLL_CTRL_BYPASS_SHIFT #undef CRF_APB_DPLL_CTRL_BYPASS_MASK -#define CRF_APB_DPLL_CTRL_BYPASS_DEFVAL 0x00002C09 -#define CRF_APB_DPLL_CTRL_BYPASS_SHIFT 3 -#define CRF_APB_DPLL_CTRL_BYPASS_MASK 0x00000008U +#define CRF_APB_DPLL_CTRL_BYPASS_DEFVAL 0x00002C09 +#define CRF_APB_DPLL_CTRL_BYPASS_SHIFT 3 +#define CRF_APB_DPLL_CTRL_BYPASS_MASK 0x00000008U -/*Divisor value for this clock.*/ +/* +* Divisor value for this clock. +*/ #undef CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL #undef CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_SHIFT #undef CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_MASK -#define CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL 0x00000400 -#define CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_SHIFT 8 -#define CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL 0x00000400 +#define CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_MASK 0x00003F00U -/*Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona - mode and uses DATA of this register for the fractional portion of the feedback divider.*/ -#undef CRF_APB_DPLL_FRAC_CFG_ENABLED_DEFVAL -#undef CRF_APB_DPLL_FRAC_CFG_ENABLED_SHIFT -#undef CRF_APB_DPLL_FRAC_CFG_ENABLED_MASK -#define CRF_APB_DPLL_FRAC_CFG_ENABLED_DEFVAL 0x00000000 -#define CRF_APB_DPLL_FRAC_CFG_ENABLED_SHIFT 31 -#define CRF_APB_DPLL_FRAC_CFG_ENABLED_MASK 0x80000000U - -/*Fractional value for the Feedback value.*/ -#undef CRF_APB_DPLL_FRAC_CFG_DATA_DEFVAL -#undef CRF_APB_DPLL_FRAC_CFG_DATA_SHIFT -#undef CRF_APB_DPLL_FRAC_CFG_DATA_MASK -#define CRF_APB_DPLL_FRAC_CFG_DATA_DEFVAL 0x00000000 -#define CRF_APB_DPLL_FRAC_CFG_DATA_SHIFT 0 -#define CRF_APB_DPLL_FRAC_CFG_DATA_MASK 0x0000FFFFU - -/*PLL loop filter resistor control*/ +/* +* PLL loop filter resistor control +*/ #undef CRF_APB_VPLL_CFG_RES_DEFVAL #undef CRF_APB_VPLL_CFG_RES_SHIFT #undef CRF_APB_VPLL_CFG_RES_MASK -#define CRF_APB_VPLL_CFG_RES_DEFVAL 0x00000000 -#define CRF_APB_VPLL_CFG_RES_SHIFT 0 -#define CRF_APB_VPLL_CFG_RES_MASK 0x0000000FU +#define CRF_APB_VPLL_CFG_RES_DEFVAL 0x00000000 +#define CRF_APB_VPLL_CFG_RES_SHIFT 0 +#define CRF_APB_VPLL_CFG_RES_MASK 0x0000000FU -/*PLL charge pump control*/ +/* +* PLL charge pump control +*/ #undef CRF_APB_VPLL_CFG_CP_DEFVAL #undef CRF_APB_VPLL_CFG_CP_SHIFT #undef CRF_APB_VPLL_CFG_CP_MASK -#define CRF_APB_VPLL_CFG_CP_DEFVAL 0x00000000 -#define CRF_APB_VPLL_CFG_CP_SHIFT 5 -#define CRF_APB_VPLL_CFG_CP_MASK 0x000001E0U +#define CRF_APB_VPLL_CFG_CP_DEFVAL 0x00000000 +#define CRF_APB_VPLL_CFG_CP_SHIFT 5 +#define CRF_APB_VPLL_CFG_CP_MASK 0x000001E0U -/*PLL loop filter high frequency capacitor control*/ +/* +* PLL loop filter high frequency capacitor control +*/ #undef CRF_APB_VPLL_CFG_LFHF_DEFVAL #undef CRF_APB_VPLL_CFG_LFHF_SHIFT #undef CRF_APB_VPLL_CFG_LFHF_MASK -#define CRF_APB_VPLL_CFG_LFHF_DEFVAL 0x00000000 -#define CRF_APB_VPLL_CFG_LFHF_SHIFT 10 -#define CRF_APB_VPLL_CFG_LFHF_MASK 0x00000C00U +#define CRF_APB_VPLL_CFG_LFHF_DEFVAL 0x00000000 +#define CRF_APB_VPLL_CFG_LFHF_SHIFT 10 +#define CRF_APB_VPLL_CFG_LFHF_MASK 0x00000C00U -/*Lock circuit counter setting*/ +/* +* Lock circuit counter setting +*/ #undef CRF_APB_VPLL_CFG_LOCK_CNT_DEFVAL #undef CRF_APB_VPLL_CFG_LOCK_CNT_SHIFT #undef CRF_APB_VPLL_CFG_LOCK_CNT_MASK -#define CRF_APB_VPLL_CFG_LOCK_CNT_DEFVAL 0x00000000 -#define CRF_APB_VPLL_CFG_LOCK_CNT_SHIFT 13 -#define CRF_APB_VPLL_CFG_LOCK_CNT_MASK 0x007FE000U +#define CRF_APB_VPLL_CFG_LOCK_CNT_DEFVAL 0x00000000 +#define CRF_APB_VPLL_CFG_LOCK_CNT_SHIFT 13 +#define CRF_APB_VPLL_CFG_LOCK_CNT_MASK 0x007FE000U -/*Lock circuit configuration settings for lock windowsize*/ +/* +* Lock circuit configuration settings for lock windowsize +*/ #undef CRF_APB_VPLL_CFG_LOCK_DLY_DEFVAL #undef CRF_APB_VPLL_CFG_LOCK_DLY_SHIFT #undef CRF_APB_VPLL_CFG_LOCK_DLY_MASK -#define CRF_APB_VPLL_CFG_LOCK_DLY_DEFVAL 0x00000000 -#define CRF_APB_VPLL_CFG_LOCK_DLY_SHIFT 25 -#define CRF_APB_VPLL_CFG_LOCK_DLY_MASK 0xFE000000U +#define CRF_APB_VPLL_CFG_LOCK_DLY_DEFVAL 0x00000000 +#define CRF_APB_VPLL_CFG_LOCK_DLY_SHIFT 25 +#define CRF_APB_VPLL_CFG_LOCK_DLY_MASK 0xFE000000U -/*Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_ - ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source*/ +/* +* Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk i + * s the source 100 video clk is the source 101 pss_alt_ref_clk is the sour + * ce 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source +*/ #undef CRF_APB_VPLL_CTRL_PRE_SRC_DEFVAL #undef CRF_APB_VPLL_CTRL_PRE_SRC_SHIFT #undef CRF_APB_VPLL_CTRL_PRE_SRC_MASK -#define CRF_APB_VPLL_CTRL_PRE_SRC_DEFVAL 0x00012809 -#define CRF_APB_VPLL_CTRL_PRE_SRC_SHIFT 20 -#define CRF_APB_VPLL_CTRL_PRE_SRC_MASK 0x00700000U +#define CRF_APB_VPLL_CTRL_PRE_SRC_DEFVAL 0x00012809 +#define CRF_APB_VPLL_CTRL_PRE_SRC_SHIFT 20 +#define CRF_APB_VPLL_CTRL_PRE_SRC_MASK 0x00700000U -/*The integer portion of the feedback divider to the PLL*/ +/* +* The integer portion of the feedback divider to the PLL +*/ #undef CRF_APB_VPLL_CTRL_FBDIV_DEFVAL #undef CRF_APB_VPLL_CTRL_FBDIV_SHIFT #undef CRF_APB_VPLL_CTRL_FBDIV_MASK -#define CRF_APB_VPLL_CTRL_FBDIV_DEFVAL 0x00012809 -#define CRF_APB_VPLL_CTRL_FBDIV_SHIFT 8 -#define CRF_APB_VPLL_CTRL_FBDIV_MASK 0x00007F00U +#define CRF_APB_VPLL_CTRL_FBDIV_DEFVAL 0x00012809 +#define CRF_APB_VPLL_CTRL_FBDIV_SHIFT 8 +#define CRF_APB_VPLL_CTRL_FBDIV_MASK 0x00007F00U -/*This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency*/ +/* +* This turns on the divide by 2 that is inside of the PLL. This does not c + * hange the VCO frequency, just the output frequency +*/ #undef CRF_APB_VPLL_CTRL_DIV2_DEFVAL #undef CRF_APB_VPLL_CTRL_DIV2_SHIFT #undef CRF_APB_VPLL_CTRL_DIV2_MASK -#define CRF_APB_VPLL_CTRL_DIV2_DEFVAL 0x00012809 -#define CRF_APB_VPLL_CTRL_DIV2_SHIFT 16 -#define CRF_APB_VPLL_CTRL_DIV2_MASK 0x00010000U +#define CRF_APB_VPLL_CTRL_DIV2_DEFVAL 0x00012809 +#define CRF_APB_VPLL_CTRL_DIV2_SHIFT 16 +#define CRF_APB_VPLL_CTRL_DIV2_MASK 0x00010000U -/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/ +/* +* Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) +*/ #undef CRF_APB_VPLL_CTRL_BYPASS_DEFVAL #undef CRF_APB_VPLL_CTRL_BYPASS_SHIFT #undef CRF_APB_VPLL_CTRL_BYPASS_MASK -#define CRF_APB_VPLL_CTRL_BYPASS_DEFVAL 0x00012809 -#define CRF_APB_VPLL_CTRL_BYPASS_SHIFT 3 -#define CRF_APB_VPLL_CTRL_BYPASS_MASK 0x00000008U +#define CRF_APB_VPLL_CTRL_BYPASS_DEFVAL 0x00012809 +#define CRF_APB_VPLL_CTRL_BYPASS_SHIFT 3 +#define CRF_APB_VPLL_CTRL_BYPASS_MASK 0x00000008U -/*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/ +/* +* Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. +*/ #undef CRF_APB_VPLL_CTRL_RESET_DEFVAL #undef CRF_APB_VPLL_CTRL_RESET_SHIFT #undef CRF_APB_VPLL_CTRL_RESET_MASK -#define CRF_APB_VPLL_CTRL_RESET_DEFVAL 0x00012809 -#define CRF_APB_VPLL_CTRL_RESET_SHIFT 0 -#define CRF_APB_VPLL_CTRL_RESET_MASK 0x00000001U +#define CRF_APB_VPLL_CTRL_RESET_DEFVAL 0x00012809 +#define CRF_APB_VPLL_CTRL_RESET_SHIFT 0 +#define CRF_APB_VPLL_CTRL_RESET_MASK 0x00000001U -/*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/ +/* +* Asserts Reset to the PLL. When asserting reset, the PLL must already be + * in BYPASS. +*/ #undef CRF_APB_VPLL_CTRL_RESET_DEFVAL #undef CRF_APB_VPLL_CTRL_RESET_SHIFT #undef CRF_APB_VPLL_CTRL_RESET_MASK -#define CRF_APB_VPLL_CTRL_RESET_DEFVAL 0x00012809 -#define CRF_APB_VPLL_CTRL_RESET_SHIFT 0 -#define CRF_APB_VPLL_CTRL_RESET_MASK 0x00000001U +#define CRF_APB_VPLL_CTRL_RESET_DEFVAL 0x00012809 +#define CRF_APB_VPLL_CTRL_RESET_SHIFT 0 +#define CRF_APB_VPLL_CTRL_RESET_MASK 0x00000001U -/*VPLL is locked*/ +/* +* VPLL is locked +*/ #undef CRF_APB_PLL_STATUS_VPLL_LOCK_DEFVAL #undef CRF_APB_PLL_STATUS_VPLL_LOCK_SHIFT #undef CRF_APB_PLL_STATUS_VPLL_LOCK_MASK -#define CRF_APB_PLL_STATUS_VPLL_LOCK_DEFVAL 0x00000038 -#define CRF_APB_PLL_STATUS_VPLL_LOCK_SHIFT 2 -#define CRF_APB_PLL_STATUS_VPLL_LOCK_MASK 0x00000004U +#define CRF_APB_PLL_STATUS_VPLL_LOCK_DEFVAL 0x00000038 +#define CRF_APB_PLL_STATUS_VPLL_LOCK_SHIFT 2 +#define CRF_APB_PLL_STATUS_VPLL_LOCK_MASK 0x00000004U #define CRF_APB_PLL_STATUS_OFFSET 0XFD1A0044 -/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4 - cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/ +/* +* Bypasses the PLL clock. The usable clock will be determined from the POS + * T_SRC field. (This signal may only be toggled after 4 cycles of the old + * clock and 4 cycles of the new clock. This is not usually an issue, but d + * esigners must be aware.) +*/ #undef CRF_APB_VPLL_CTRL_BYPASS_DEFVAL #undef CRF_APB_VPLL_CTRL_BYPASS_SHIFT #undef CRF_APB_VPLL_CTRL_BYPASS_MASK -#define CRF_APB_VPLL_CTRL_BYPASS_DEFVAL 0x00012809 -#define CRF_APB_VPLL_CTRL_BYPASS_SHIFT 3 -#define CRF_APB_VPLL_CTRL_BYPASS_MASK 0x00000008U +#define CRF_APB_VPLL_CTRL_BYPASS_DEFVAL 0x00012809 +#define CRF_APB_VPLL_CTRL_BYPASS_SHIFT 3 +#define CRF_APB_VPLL_CTRL_BYPASS_MASK 0x00000008U -/*Divisor value for this clock.*/ +/* +* Divisor value for this clock. +*/ #undef CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL #undef CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_SHIFT #undef CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_MASK -#define CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL 0x00000400 -#define CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_SHIFT 8 -#define CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_MASK 0x00003F00U - -/*Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona - mode and uses DATA of this register for the fractional portion of the feedback divider.*/ -#undef CRF_APB_VPLL_FRAC_CFG_ENABLED_DEFVAL -#undef CRF_APB_VPLL_FRAC_CFG_ENABLED_SHIFT -#undef CRF_APB_VPLL_FRAC_CFG_ENABLED_MASK -#define CRF_APB_VPLL_FRAC_CFG_ENABLED_DEFVAL 0x00000000 -#define CRF_APB_VPLL_FRAC_CFG_ENABLED_SHIFT 31 -#define CRF_APB_VPLL_FRAC_CFG_ENABLED_MASK 0x80000000U - -/*Fractional value for the Feedback value.*/ -#undef CRF_APB_VPLL_FRAC_CFG_DATA_DEFVAL -#undef CRF_APB_VPLL_FRAC_CFG_DATA_SHIFT -#undef CRF_APB_VPLL_FRAC_CFG_DATA_MASK -#define CRF_APB_VPLL_FRAC_CFG_DATA_DEFVAL 0x00000000 -#define CRF_APB_VPLL_FRAC_CFG_DATA_SHIFT 0 -#define CRF_APB_VPLL_FRAC_CFG_DATA_MASK 0x0000FFFFU +#define CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL 0x00000400 +#define CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_MASK 0x00003F00U #undef CRL_APB_GEM3_REF_CTRL_OFFSET #define CRL_APB_GEM3_REF_CTRL_OFFSET 0XFF5E005C +#undef CRL_APB_GEM_TSU_REF_CTRL_OFFSET +#define CRL_APB_GEM_TSU_REF_CTRL_OFFSET 0XFF5E0100 #undef CRL_APB_USB0_BUS_REF_CTRL_OFFSET #define CRL_APB_USB0_BUS_REF_CTRL_OFFSET 0XFF5E0060 #undef CRL_APB_USB3_DUAL_REF_CTRL_OFFSET @@ -810,12 +897,6 @@ #define CRL_APB_ADMA_REF_CTRL_OFFSET 0XFF5E00B8 #undef CRL_APB_PL0_REF_CTRL_OFFSET #define CRL_APB_PL0_REF_CTRL_OFFSET 0XFF5E00C0 -#undef CRL_APB_PL1_REF_CTRL_OFFSET -#define CRL_APB_PL1_REF_CTRL_OFFSET 0XFF5E00C4 -#undef CRL_APB_PL2_REF_CTRL_OFFSET -#define CRL_APB_PL2_REF_CTRL_OFFSET 0XFF5E00C8 -#undef CRL_APB_PL3_REF_CTRL_OFFSET -#define CRL_APB_PL3_REF_CTRL_OFFSET 0XFF5E00CC #undef CRL_APB_AMS_REF_CTRL_OFFSET #define CRL_APB_AMS_REF_CTRL_OFFSET 0XFF5E0108 #undef CRL_APB_DLL_REF_CTRL_OFFSET @@ -834,8 +915,6 @@ #define CRF_APB_DP_STC_REF_CTRL_OFFSET 0XFD1A007C #undef CRF_APB_ACPU_CTRL_OFFSET #define CRF_APB_ACPU_CTRL_OFFSET 0XFD1A0060 -#undef CRF_APB_DBG_TRACE_CTRL_OFFSET -#define CRF_APB_DBG_TRACE_CTRL_OFFSET 0XFD1A0064 #undef CRF_APB_DBG_FPD_CTRL_OFFSET #define CRF_APB_DBG_FPD_CTRL_OFFSET 0XFD1A0068 #undef CRF_APB_DDR_CTRL_OFFSET @@ -861,1195 +940,1418 @@ #undef LPD_SLCR_CSUPMU_WDT_CLK_SEL_OFFSET #define LPD_SLCR_CSUPMU_WDT_CLK_SEL_OFFSET 0XFF410050 -/*Clock active for the RX channel*/ +/* +* Clock active for the RX channel +*/ #undef CRL_APB_GEM3_REF_CTRL_RX_CLKACT_DEFVAL #undef CRL_APB_GEM3_REF_CTRL_RX_CLKACT_SHIFT #undef CRL_APB_GEM3_REF_CTRL_RX_CLKACT_MASK -#define CRL_APB_GEM3_REF_CTRL_RX_CLKACT_DEFVAL 0x00002500 -#define CRL_APB_GEM3_REF_CTRL_RX_CLKACT_SHIFT 26 -#define CRL_APB_GEM3_REF_CTRL_RX_CLKACT_MASK 0x04000000U +#define CRL_APB_GEM3_REF_CTRL_RX_CLKACT_DEFVAL 0x00002500 +#define CRL_APB_GEM3_REF_CTRL_RX_CLKACT_SHIFT 26 +#define CRL_APB_GEM3_REF_CTRL_RX_CLKACT_MASK 0x04000000U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRL_APB_GEM3_REF_CTRL_CLKACT_DEFVAL #undef CRL_APB_GEM3_REF_CTRL_CLKACT_SHIFT #undef CRL_APB_GEM3_REF_CTRL_CLKACT_MASK -#define CRL_APB_GEM3_REF_CTRL_CLKACT_DEFVAL 0x00002500 -#define CRL_APB_GEM3_REF_CTRL_CLKACT_SHIFT 25 -#define CRL_APB_GEM3_REF_CTRL_CLKACT_MASK 0x02000000U +#define CRL_APB_GEM3_REF_CTRL_CLKACT_DEFVAL 0x00002500 +#define CRL_APB_GEM3_REF_CTRL_CLKACT_SHIFT 25 +#define CRL_APB_GEM3_REF_CTRL_CLKACT_MASK 0x02000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_GEM3_REF_CTRL_DIVISOR1_DEFVAL #undef CRL_APB_GEM3_REF_CTRL_DIVISOR1_SHIFT #undef CRL_APB_GEM3_REF_CTRL_DIVISOR1_MASK -#define CRL_APB_GEM3_REF_CTRL_DIVISOR1_DEFVAL 0x00002500 -#define CRL_APB_GEM3_REF_CTRL_DIVISOR1_SHIFT 16 -#define CRL_APB_GEM3_REF_CTRL_DIVISOR1_MASK 0x003F0000U +#define CRL_APB_GEM3_REF_CTRL_DIVISOR1_DEFVAL 0x00002500 +#define CRL_APB_GEM3_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_GEM3_REF_CTRL_DIVISOR1_MASK 0x003F0000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_GEM3_REF_CTRL_DIVISOR0_DEFVAL #undef CRL_APB_GEM3_REF_CTRL_DIVISOR0_SHIFT #undef CRL_APB_GEM3_REF_CTRL_DIVISOR0_MASK -#define CRL_APB_GEM3_REF_CTRL_DIVISOR0_DEFVAL 0x00002500 -#define CRL_APB_GEM3_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_GEM3_REF_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRL_APB_GEM3_REF_CTRL_DIVISOR0_DEFVAL 0x00002500 +#define CRL_APB_GEM3_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_GEM3_REF_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRL_APB_GEM3_REF_CTRL_SRCSEL_DEFVAL #undef CRL_APB_GEM3_REF_CTRL_SRCSEL_SHIFT #undef CRL_APB_GEM3_REF_CTRL_SRCSEL_MASK -#define CRL_APB_GEM3_REF_CTRL_SRCSEL_DEFVAL 0x00002500 -#define CRL_APB_GEM3_REF_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_GEM3_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRL_APB_GEM3_REF_CTRL_SRCSEL_DEFVAL 0x00002500 +#define CRL_APB_GEM3_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_GEM3_REF_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* 6 bit divider +*/ +#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_DEFVAL +#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_SHIFT +#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_MASK +#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_DEFVAL 0x00051000 +#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_MASK 0x00003F00U + +/* +* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ +#undef CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_DEFVAL +#undef CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_SHIFT +#undef CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_MASK +#define CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_DEFVAL 0x00051000 +#define CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_MASK 0x00000007U + +/* +* 6 bit divider +*/ +#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_DEFVAL +#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_SHIFT +#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_MASK +#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_DEFVAL 0x00051000 +#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_MASK 0x003F0000U + +/* +* Clock active signal. Switch to 0 to disable the clock +*/ +#undef CRL_APB_GEM_TSU_REF_CTRL_CLKACT_DEFVAL +#undef CRL_APB_GEM_TSU_REF_CTRL_CLKACT_SHIFT +#undef CRL_APB_GEM_TSU_REF_CTRL_CLKACT_MASK +#define CRL_APB_GEM_TSU_REF_CTRL_CLKACT_DEFVAL 0x00051000 +#define CRL_APB_GEM_TSU_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_GEM_TSU_REF_CTRL_CLKACT_MASK 0x01000000U + +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRL_APB_USB0_BUS_REF_CTRL_CLKACT_DEFVAL #undef CRL_APB_USB0_BUS_REF_CTRL_CLKACT_SHIFT #undef CRL_APB_USB0_BUS_REF_CTRL_CLKACT_MASK -#define CRL_APB_USB0_BUS_REF_CTRL_CLKACT_DEFVAL 0x00052000 -#define CRL_APB_USB0_BUS_REF_CTRL_CLKACT_SHIFT 25 -#define CRL_APB_USB0_BUS_REF_CTRL_CLKACT_MASK 0x02000000U +#define CRL_APB_USB0_BUS_REF_CTRL_CLKACT_DEFVAL 0x00052000 +#define CRL_APB_USB0_BUS_REF_CTRL_CLKACT_SHIFT 25 +#define CRL_APB_USB0_BUS_REF_CTRL_CLKACT_MASK 0x02000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_DEFVAL #undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_SHIFT #undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_MASK -#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_DEFVAL 0x00052000 -#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_SHIFT 16 -#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_MASK 0x003F0000U +#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_DEFVAL 0x00052000 +#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_MASK 0x003F0000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_DEFVAL #undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_SHIFT #undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_MASK -#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_DEFVAL 0x00052000 -#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_DEFVAL 0x00052000 +#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_DEFVAL #undef CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_SHIFT #undef CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_MASK -#define CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_DEFVAL 0x00052000 -#define CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_DEFVAL 0x00052000 +#define CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_DEFVAL #undef CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_SHIFT #undef CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_MASK -#define CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_DEFVAL 0x00052000 -#define CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_SHIFT 25 -#define CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_MASK 0x02000000U +#define CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_DEFVAL 0x00052000 +#define CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_SHIFT 25 +#define CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_MASK 0x02000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_DEFVAL #undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_SHIFT #undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_MASK -#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_DEFVAL 0x00052000 -#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_SHIFT 16 -#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_MASK 0x003F0000U +#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_DEFVAL 0x00052000 +#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_MASK 0x003F0000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_DEFVAL #undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_SHIFT #undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_MASK -#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_DEFVAL 0x00052000 -#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_DEFVAL 0x00052000 +#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = IOPLL; 010 = RPLL; 011 = DPLL. (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = IOPLL; 010 = RPLL; 011 = DPLL. (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_DEFVAL #undef CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_SHIFT #undef CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_MASK -#define CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_DEFVAL 0x00052000 -#define CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_DEFVAL 0x00052000 +#define CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRL_APB_QSPI_REF_CTRL_CLKACT_DEFVAL #undef CRL_APB_QSPI_REF_CTRL_CLKACT_SHIFT #undef CRL_APB_QSPI_REF_CTRL_CLKACT_MASK -#define CRL_APB_QSPI_REF_CTRL_CLKACT_DEFVAL 0x01000800 -#define CRL_APB_QSPI_REF_CTRL_CLKACT_SHIFT 24 -#define CRL_APB_QSPI_REF_CTRL_CLKACT_MASK 0x01000000U +#define CRL_APB_QSPI_REF_CTRL_CLKACT_DEFVAL 0x01000800 +#define CRL_APB_QSPI_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_QSPI_REF_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_QSPI_REF_CTRL_DIVISOR1_DEFVAL #undef CRL_APB_QSPI_REF_CTRL_DIVISOR1_SHIFT #undef CRL_APB_QSPI_REF_CTRL_DIVISOR1_MASK -#define CRL_APB_QSPI_REF_CTRL_DIVISOR1_DEFVAL 0x01000800 -#define CRL_APB_QSPI_REF_CTRL_DIVISOR1_SHIFT 16 -#define CRL_APB_QSPI_REF_CTRL_DIVISOR1_MASK 0x003F0000U +#define CRL_APB_QSPI_REF_CTRL_DIVISOR1_DEFVAL 0x01000800 +#define CRL_APB_QSPI_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_QSPI_REF_CTRL_DIVISOR1_MASK 0x003F0000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_QSPI_REF_CTRL_DIVISOR0_DEFVAL #undef CRL_APB_QSPI_REF_CTRL_DIVISOR0_SHIFT #undef CRL_APB_QSPI_REF_CTRL_DIVISOR0_MASK -#define CRL_APB_QSPI_REF_CTRL_DIVISOR0_DEFVAL 0x01000800 -#define CRL_APB_QSPI_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_QSPI_REF_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRL_APB_QSPI_REF_CTRL_DIVISOR0_DEFVAL 0x01000800 +#define CRL_APB_QSPI_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_QSPI_REF_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRL_APB_QSPI_REF_CTRL_SRCSEL_DEFVAL #undef CRL_APB_QSPI_REF_CTRL_SRCSEL_SHIFT #undef CRL_APB_QSPI_REF_CTRL_SRCSEL_MASK -#define CRL_APB_QSPI_REF_CTRL_SRCSEL_DEFVAL 0x01000800 -#define CRL_APB_QSPI_REF_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_QSPI_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRL_APB_QSPI_REF_CTRL_SRCSEL_DEFVAL 0x01000800 +#define CRL_APB_QSPI_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_QSPI_REF_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRL_APB_SDIO1_REF_CTRL_CLKACT_DEFVAL #undef CRL_APB_SDIO1_REF_CTRL_CLKACT_SHIFT #undef CRL_APB_SDIO1_REF_CTRL_CLKACT_MASK -#define CRL_APB_SDIO1_REF_CTRL_CLKACT_DEFVAL 0x01000F00 -#define CRL_APB_SDIO1_REF_CTRL_CLKACT_SHIFT 24 -#define CRL_APB_SDIO1_REF_CTRL_CLKACT_MASK 0x01000000U +#define CRL_APB_SDIO1_REF_CTRL_CLKACT_DEFVAL 0x01000F00 +#define CRL_APB_SDIO1_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_SDIO1_REF_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_SDIO1_REF_CTRL_DIVISOR1_DEFVAL #undef CRL_APB_SDIO1_REF_CTRL_DIVISOR1_SHIFT #undef CRL_APB_SDIO1_REF_CTRL_DIVISOR1_MASK -#define CRL_APB_SDIO1_REF_CTRL_DIVISOR1_DEFVAL 0x01000F00 -#define CRL_APB_SDIO1_REF_CTRL_DIVISOR1_SHIFT 16 -#define CRL_APB_SDIO1_REF_CTRL_DIVISOR1_MASK 0x003F0000U +#define CRL_APB_SDIO1_REF_CTRL_DIVISOR1_DEFVAL 0x01000F00 +#define CRL_APB_SDIO1_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_SDIO1_REF_CTRL_DIVISOR1_MASK 0x003F0000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_SDIO1_REF_CTRL_DIVISOR0_DEFVAL #undef CRL_APB_SDIO1_REF_CTRL_DIVISOR0_SHIFT #undef CRL_APB_SDIO1_REF_CTRL_DIVISOR0_MASK -#define CRL_APB_SDIO1_REF_CTRL_DIVISOR0_DEFVAL 0x01000F00 -#define CRL_APB_SDIO1_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_SDIO1_REF_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRL_APB_SDIO1_REF_CTRL_DIVISOR0_DEFVAL 0x01000F00 +#define CRL_APB_SDIO1_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_SDIO1_REF_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = IOPLL; 010 = RPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = IOPLL; 010 = RPLL; 011 = VPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRL_APB_SDIO1_REF_CTRL_SRCSEL_DEFVAL #undef CRL_APB_SDIO1_REF_CTRL_SRCSEL_SHIFT #undef CRL_APB_SDIO1_REF_CTRL_SRCSEL_MASK -#define CRL_APB_SDIO1_REF_CTRL_SRCSEL_DEFVAL 0x01000F00 -#define CRL_APB_SDIO1_REF_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_SDIO1_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRL_APB_SDIO1_REF_CTRL_SRCSEL_DEFVAL 0x01000F00 +#define CRL_APB_SDIO1_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_SDIO1_REF_CTRL_SRCSEL_MASK 0x00000007U -/*MIO pad selection for sdio1_rx_clk (feedback clock from the PAD) 0: MIO [51] 1: MIO [76]*/ +/* +* MIO pad selection for sdio1_rx_clk (feedback clock from the PAD) 0: MIO + * [51] 1: MIO [76] +*/ #undef IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_DEFVAL #undef IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_SHIFT #undef IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_MASK -#define IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_SHIFT 17 -#define IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_MASK 0x00020000U +#define IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_SHIFT 17 +#define IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_MASK 0x00020000U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRL_APB_UART0_REF_CTRL_CLKACT_DEFVAL #undef CRL_APB_UART0_REF_CTRL_CLKACT_SHIFT #undef CRL_APB_UART0_REF_CTRL_CLKACT_MASK -#define CRL_APB_UART0_REF_CTRL_CLKACT_DEFVAL 0x01001800 -#define CRL_APB_UART0_REF_CTRL_CLKACT_SHIFT 24 -#define CRL_APB_UART0_REF_CTRL_CLKACT_MASK 0x01000000U +#define CRL_APB_UART0_REF_CTRL_CLKACT_DEFVAL 0x01001800 +#define CRL_APB_UART0_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_UART0_REF_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_UART0_REF_CTRL_DIVISOR1_DEFVAL #undef CRL_APB_UART0_REF_CTRL_DIVISOR1_SHIFT #undef CRL_APB_UART0_REF_CTRL_DIVISOR1_MASK -#define CRL_APB_UART0_REF_CTRL_DIVISOR1_DEFVAL 0x01001800 -#define CRL_APB_UART0_REF_CTRL_DIVISOR1_SHIFT 16 -#define CRL_APB_UART0_REF_CTRL_DIVISOR1_MASK 0x003F0000U +#define CRL_APB_UART0_REF_CTRL_DIVISOR1_DEFVAL 0x01001800 +#define CRL_APB_UART0_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_UART0_REF_CTRL_DIVISOR1_MASK 0x003F0000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_UART0_REF_CTRL_DIVISOR0_DEFVAL #undef CRL_APB_UART0_REF_CTRL_DIVISOR0_SHIFT #undef CRL_APB_UART0_REF_CTRL_DIVISOR0_MASK -#define CRL_APB_UART0_REF_CTRL_DIVISOR0_DEFVAL 0x01001800 -#define CRL_APB_UART0_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_UART0_REF_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRL_APB_UART0_REF_CTRL_DIVISOR0_DEFVAL 0x01001800 +#define CRL_APB_UART0_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_UART0_REF_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRL_APB_UART0_REF_CTRL_SRCSEL_DEFVAL #undef CRL_APB_UART0_REF_CTRL_SRCSEL_SHIFT #undef CRL_APB_UART0_REF_CTRL_SRCSEL_MASK -#define CRL_APB_UART0_REF_CTRL_SRCSEL_DEFVAL 0x01001800 -#define CRL_APB_UART0_REF_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_UART0_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRL_APB_UART0_REF_CTRL_SRCSEL_DEFVAL 0x01001800 +#define CRL_APB_UART0_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_UART0_REF_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRL_APB_UART1_REF_CTRL_CLKACT_DEFVAL #undef CRL_APB_UART1_REF_CTRL_CLKACT_SHIFT #undef CRL_APB_UART1_REF_CTRL_CLKACT_MASK -#define CRL_APB_UART1_REF_CTRL_CLKACT_DEFVAL 0x01001800 -#define CRL_APB_UART1_REF_CTRL_CLKACT_SHIFT 24 -#define CRL_APB_UART1_REF_CTRL_CLKACT_MASK 0x01000000U +#define CRL_APB_UART1_REF_CTRL_CLKACT_DEFVAL 0x01001800 +#define CRL_APB_UART1_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_UART1_REF_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_UART1_REF_CTRL_DIVISOR1_DEFVAL #undef CRL_APB_UART1_REF_CTRL_DIVISOR1_SHIFT #undef CRL_APB_UART1_REF_CTRL_DIVISOR1_MASK -#define CRL_APB_UART1_REF_CTRL_DIVISOR1_DEFVAL 0x01001800 -#define CRL_APB_UART1_REF_CTRL_DIVISOR1_SHIFT 16 -#define CRL_APB_UART1_REF_CTRL_DIVISOR1_MASK 0x003F0000U +#define CRL_APB_UART1_REF_CTRL_DIVISOR1_DEFVAL 0x01001800 +#define CRL_APB_UART1_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_UART1_REF_CTRL_DIVISOR1_MASK 0x003F0000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_UART1_REF_CTRL_DIVISOR0_DEFVAL #undef CRL_APB_UART1_REF_CTRL_DIVISOR0_SHIFT #undef CRL_APB_UART1_REF_CTRL_DIVISOR0_MASK -#define CRL_APB_UART1_REF_CTRL_DIVISOR0_DEFVAL 0x01001800 -#define CRL_APB_UART1_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_UART1_REF_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRL_APB_UART1_REF_CTRL_DIVISOR0_DEFVAL 0x01001800 +#define CRL_APB_UART1_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_UART1_REF_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRL_APB_UART1_REF_CTRL_SRCSEL_DEFVAL #undef CRL_APB_UART1_REF_CTRL_SRCSEL_SHIFT #undef CRL_APB_UART1_REF_CTRL_SRCSEL_MASK -#define CRL_APB_UART1_REF_CTRL_SRCSEL_DEFVAL 0x01001800 -#define CRL_APB_UART1_REF_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_UART1_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRL_APB_UART1_REF_CTRL_SRCSEL_DEFVAL 0x01001800 +#define CRL_APB_UART1_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_UART1_REF_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRL_APB_I2C0_REF_CTRL_CLKACT_DEFVAL #undef CRL_APB_I2C0_REF_CTRL_CLKACT_SHIFT #undef CRL_APB_I2C0_REF_CTRL_CLKACT_MASK -#define CRL_APB_I2C0_REF_CTRL_CLKACT_DEFVAL 0x01000500 -#define CRL_APB_I2C0_REF_CTRL_CLKACT_SHIFT 24 -#define CRL_APB_I2C0_REF_CTRL_CLKACT_MASK 0x01000000U +#define CRL_APB_I2C0_REF_CTRL_CLKACT_DEFVAL 0x01000500 +#define CRL_APB_I2C0_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_I2C0_REF_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_I2C0_REF_CTRL_DIVISOR1_DEFVAL #undef CRL_APB_I2C0_REF_CTRL_DIVISOR1_SHIFT #undef CRL_APB_I2C0_REF_CTRL_DIVISOR1_MASK -#define CRL_APB_I2C0_REF_CTRL_DIVISOR1_DEFVAL 0x01000500 -#define CRL_APB_I2C0_REF_CTRL_DIVISOR1_SHIFT 16 -#define CRL_APB_I2C0_REF_CTRL_DIVISOR1_MASK 0x003F0000U +#define CRL_APB_I2C0_REF_CTRL_DIVISOR1_DEFVAL 0x01000500 +#define CRL_APB_I2C0_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_I2C0_REF_CTRL_DIVISOR1_MASK 0x003F0000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_I2C0_REF_CTRL_DIVISOR0_DEFVAL #undef CRL_APB_I2C0_REF_CTRL_DIVISOR0_SHIFT #undef CRL_APB_I2C0_REF_CTRL_DIVISOR0_MASK -#define CRL_APB_I2C0_REF_CTRL_DIVISOR0_DEFVAL 0x01000500 -#define CRL_APB_I2C0_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_I2C0_REF_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRL_APB_I2C0_REF_CTRL_DIVISOR0_DEFVAL 0x01000500 +#define CRL_APB_I2C0_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_I2C0_REF_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRL_APB_I2C0_REF_CTRL_SRCSEL_DEFVAL #undef CRL_APB_I2C0_REF_CTRL_SRCSEL_SHIFT #undef CRL_APB_I2C0_REF_CTRL_SRCSEL_MASK -#define CRL_APB_I2C0_REF_CTRL_SRCSEL_DEFVAL 0x01000500 -#define CRL_APB_I2C0_REF_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_I2C0_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRL_APB_I2C0_REF_CTRL_SRCSEL_DEFVAL 0x01000500 +#define CRL_APB_I2C0_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_I2C0_REF_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRL_APB_I2C1_REF_CTRL_CLKACT_DEFVAL #undef CRL_APB_I2C1_REF_CTRL_CLKACT_SHIFT #undef CRL_APB_I2C1_REF_CTRL_CLKACT_MASK -#define CRL_APB_I2C1_REF_CTRL_CLKACT_DEFVAL 0x01000500 -#define CRL_APB_I2C1_REF_CTRL_CLKACT_SHIFT 24 -#define CRL_APB_I2C1_REF_CTRL_CLKACT_MASK 0x01000000U +#define CRL_APB_I2C1_REF_CTRL_CLKACT_DEFVAL 0x01000500 +#define CRL_APB_I2C1_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_I2C1_REF_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_I2C1_REF_CTRL_DIVISOR1_DEFVAL #undef CRL_APB_I2C1_REF_CTRL_DIVISOR1_SHIFT #undef CRL_APB_I2C1_REF_CTRL_DIVISOR1_MASK -#define CRL_APB_I2C1_REF_CTRL_DIVISOR1_DEFVAL 0x01000500 -#define CRL_APB_I2C1_REF_CTRL_DIVISOR1_SHIFT 16 -#define CRL_APB_I2C1_REF_CTRL_DIVISOR1_MASK 0x003F0000U +#define CRL_APB_I2C1_REF_CTRL_DIVISOR1_DEFVAL 0x01000500 +#define CRL_APB_I2C1_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_I2C1_REF_CTRL_DIVISOR1_MASK 0x003F0000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_I2C1_REF_CTRL_DIVISOR0_DEFVAL #undef CRL_APB_I2C1_REF_CTRL_DIVISOR0_SHIFT #undef CRL_APB_I2C1_REF_CTRL_DIVISOR0_MASK -#define CRL_APB_I2C1_REF_CTRL_DIVISOR0_DEFVAL 0x01000500 -#define CRL_APB_I2C1_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_I2C1_REF_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRL_APB_I2C1_REF_CTRL_DIVISOR0_DEFVAL 0x01000500 +#define CRL_APB_I2C1_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_I2C1_REF_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRL_APB_I2C1_REF_CTRL_SRCSEL_DEFVAL #undef CRL_APB_I2C1_REF_CTRL_SRCSEL_SHIFT #undef CRL_APB_I2C1_REF_CTRL_SRCSEL_MASK -#define CRL_APB_I2C1_REF_CTRL_SRCSEL_DEFVAL 0x01000500 -#define CRL_APB_I2C1_REF_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_I2C1_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRL_APB_I2C1_REF_CTRL_SRCSEL_DEFVAL 0x01000500 +#define CRL_APB_I2C1_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_I2C1_REF_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRL_APB_CAN1_REF_CTRL_CLKACT_DEFVAL #undef CRL_APB_CAN1_REF_CTRL_CLKACT_SHIFT #undef CRL_APB_CAN1_REF_CTRL_CLKACT_MASK -#define CRL_APB_CAN1_REF_CTRL_CLKACT_DEFVAL 0x01001800 -#define CRL_APB_CAN1_REF_CTRL_CLKACT_SHIFT 24 -#define CRL_APB_CAN1_REF_CTRL_CLKACT_MASK 0x01000000U +#define CRL_APB_CAN1_REF_CTRL_CLKACT_DEFVAL 0x01001800 +#define CRL_APB_CAN1_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_CAN1_REF_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_CAN1_REF_CTRL_DIVISOR1_DEFVAL #undef CRL_APB_CAN1_REF_CTRL_DIVISOR1_SHIFT #undef CRL_APB_CAN1_REF_CTRL_DIVISOR1_MASK -#define CRL_APB_CAN1_REF_CTRL_DIVISOR1_DEFVAL 0x01001800 -#define CRL_APB_CAN1_REF_CTRL_DIVISOR1_SHIFT 16 -#define CRL_APB_CAN1_REF_CTRL_DIVISOR1_MASK 0x003F0000U +#define CRL_APB_CAN1_REF_CTRL_DIVISOR1_DEFVAL 0x01001800 +#define CRL_APB_CAN1_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_CAN1_REF_CTRL_DIVISOR1_MASK 0x003F0000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_CAN1_REF_CTRL_DIVISOR0_DEFVAL #undef CRL_APB_CAN1_REF_CTRL_DIVISOR0_SHIFT #undef CRL_APB_CAN1_REF_CTRL_DIVISOR0_MASK -#define CRL_APB_CAN1_REF_CTRL_DIVISOR0_DEFVAL 0x01001800 -#define CRL_APB_CAN1_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_CAN1_REF_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRL_APB_CAN1_REF_CTRL_DIVISOR0_DEFVAL 0x01001800 +#define CRL_APB_CAN1_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_CAN1_REF_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRL_APB_CAN1_REF_CTRL_SRCSEL_DEFVAL #undef CRL_APB_CAN1_REF_CTRL_SRCSEL_SHIFT #undef CRL_APB_CAN1_REF_CTRL_SRCSEL_MASK -#define CRL_APB_CAN1_REF_CTRL_SRCSEL_DEFVAL 0x01001800 -#define CRL_APB_CAN1_REF_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_CAN1_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRL_APB_CAN1_REF_CTRL_SRCSEL_DEFVAL 0x01001800 +#define CRL_APB_CAN1_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_CAN1_REF_CTRL_SRCSEL_MASK 0x00000007U -/*Turing this off will shut down the OCM, some parts of the APM, and prevent transactions going from the FPD to the LPD and cou - d lead to system hang*/ +/* +* Turing this off will shut down the OCM, some parts of the APM, and preve + * nt transactions going from the FPD to the LPD and could lead to system h + * ang +*/ #undef CRL_APB_CPU_R5_CTRL_CLKACT_DEFVAL #undef CRL_APB_CPU_R5_CTRL_CLKACT_SHIFT #undef CRL_APB_CPU_R5_CTRL_CLKACT_MASK -#define CRL_APB_CPU_R5_CTRL_CLKACT_DEFVAL 0x03000600 -#define CRL_APB_CPU_R5_CTRL_CLKACT_SHIFT 24 -#define CRL_APB_CPU_R5_CTRL_CLKACT_MASK 0x01000000U +#define CRL_APB_CPU_R5_CTRL_CLKACT_DEFVAL 0x03000600 +#define CRL_APB_CPU_R5_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_CPU_R5_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_CPU_R5_CTRL_DIVISOR0_DEFVAL #undef CRL_APB_CPU_R5_CTRL_DIVISOR0_SHIFT #undef CRL_APB_CPU_R5_CTRL_DIVISOR0_MASK -#define CRL_APB_CPU_R5_CTRL_DIVISOR0_DEFVAL 0x03000600 -#define CRL_APB_CPU_R5_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_CPU_R5_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRL_APB_CPU_R5_CTRL_DIVISOR0_DEFVAL 0x03000600 +#define CRL_APB_CPU_R5_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_CPU_R5_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRL_APB_CPU_R5_CTRL_SRCSEL_DEFVAL #undef CRL_APB_CPU_R5_CTRL_SRCSEL_SHIFT #undef CRL_APB_CPU_R5_CTRL_SRCSEL_MASK -#define CRL_APB_CPU_R5_CTRL_SRCSEL_DEFVAL 0x03000600 -#define CRL_APB_CPU_R5_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_CPU_R5_CTRL_SRCSEL_MASK 0x00000007U +#define CRL_APB_CPU_R5_CTRL_SRCSEL_DEFVAL 0x03000600 +#define CRL_APB_CPU_R5_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_CPU_R5_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRL_APB_IOU_SWITCH_CTRL_CLKACT_DEFVAL #undef CRL_APB_IOU_SWITCH_CTRL_CLKACT_SHIFT #undef CRL_APB_IOU_SWITCH_CTRL_CLKACT_MASK -#define CRL_APB_IOU_SWITCH_CTRL_CLKACT_DEFVAL 0x00001500 -#define CRL_APB_IOU_SWITCH_CTRL_CLKACT_SHIFT 24 -#define CRL_APB_IOU_SWITCH_CTRL_CLKACT_MASK 0x01000000U +#define CRL_APB_IOU_SWITCH_CTRL_CLKACT_DEFVAL 0x00001500 +#define CRL_APB_IOU_SWITCH_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_IOU_SWITCH_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_DEFVAL #undef CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_SHIFT #undef CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_MASK -#define CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_DEFVAL 0x00001500 -#define CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_DEFVAL 0x00001500 +#define CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRL_APB_IOU_SWITCH_CTRL_SRCSEL_DEFVAL #undef CRL_APB_IOU_SWITCH_CTRL_SRCSEL_SHIFT #undef CRL_APB_IOU_SWITCH_CTRL_SRCSEL_MASK -#define CRL_APB_IOU_SWITCH_CTRL_SRCSEL_DEFVAL 0x00001500 -#define CRL_APB_IOU_SWITCH_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_IOU_SWITCH_CTRL_SRCSEL_MASK 0x00000007U +#define CRL_APB_IOU_SWITCH_CTRL_SRCSEL_DEFVAL 0x00001500 +#define CRL_APB_IOU_SWITCH_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_IOU_SWITCH_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRL_APB_PCAP_CTRL_CLKACT_DEFVAL #undef CRL_APB_PCAP_CTRL_CLKACT_SHIFT #undef CRL_APB_PCAP_CTRL_CLKACT_MASK -#define CRL_APB_PCAP_CTRL_CLKACT_DEFVAL 0x00001500 -#define CRL_APB_PCAP_CTRL_CLKACT_SHIFT 24 -#define CRL_APB_PCAP_CTRL_CLKACT_MASK 0x01000000U +#define CRL_APB_PCAP_CTRL_CLKACT_DEFVAL 0x00001500 +#define CRL_APB_PCAP_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_PCAP_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_PCAP_CTRL_DIVISOR0_DEFVAL #undef CRL_APB_PCAP_CTRL_DIVISOR0_SHIFT #undef CRL_APB_PCAP_CTRL_DIVISOR0_MASK -#define CRL_APB_PCAP_CTRL_DIVISOR0_DEFVAL 0x00001500 -#define CRL_APB_PCAP_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_PCAP_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRL_APB_PCAP_CTRL_DIVISOR0_DEFVAL 0x00001500 +#define CRL_APB_PCAP_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_PCAP_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRL_APB_PCAP_CTRL_SRCSEL_DEFVAL #undef CRL_APB_PCAP_CTRL_SRCSEL_SHIFT #undef CRL_APB_PCAP_CTRL_SRCSEL_MASK -#define CRL_APB_PCAP_CTRL_SRCSEL_DEFVAL 0x00001500 -#define CRL_APB_PCAP_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_PCAP_CTRL_SRCSEL_MASK 0x00000007U +#define CRL_APB_PCAP_CTRL_SRCSEL_DEFVAL 0x00001500 +#define CRL_APB_PCAP_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_PCAP_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRL_APB_LPD_SWITCH_CTRL_CLKACT_DEFVAL #undef CRL_APB_LPD_SWITCH_CTRL_CLKACT_SHIFT #undef CRL_APB_LPD_SWITCH_CTRL_CLKACT_MASK -#define CRL_APB_LPD_SWITCH_CTRL_CLKACT_DEFVAL 0x01000500 -#define CRL_APB_LPD_SWITCH_CTRL_CLKACT_SHIFT 24 -#define CRL_APB_LPD_SWITCH_CTRL_CLKACT_MASK 0x01000000U +#define CRL_APB_LPD_SWITCH_CTRL_CLKACT_DEFVAL 0x01000500 +#define CRL_APB_LPD_SWITCH_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_LPD_SWITCH_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_DEFVAL #undef CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_SHIFT #undef CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_MASK -#define CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_DEFVAL 0x01000500 -#define CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_DEFVAL 0x01000500 +#define CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRL_APB_LPD_SWITCH_CTRL_SRCSEL_DEFVAL #undef CRL_APB_LPD_SWITCH_CTRL_SRCSEL_SHIFT #undef CRL_APB_LPD_SWITCH_CTRL_SRCSEL_MASK -#define CRL_APB_LPD_SWITCH_CTRL_SRCSEL_DEFVAL 0x01000500 -#define CRL_APB_LPD_SWITCH_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_LPD_SWITCH_CTRL_SRCSEL_MASK 0x00000007U +#define CRL_APB_LPD_SWITCH_CTRL_SRCSEL_DEFVAL 0x01000500 +#define CRL_APB_LPD_SWITCH_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_LPD_SWITCH_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRL_APB_LPD_LSBUS_CTRL_CLKACT_DEFVAL #undef CRL_APB_LPD_LSBUS_CTRL_CLKACT_SHIFT #undef CRL_APB_LPD_LSBUS_CTRL_CLKACT_MASK -#define CRL_APB_LPD_LSBUS_CTRL_CLKACT_DEFVAL 0x01001800 -#define CRL_APB_LPD_LSBUS_CTRL_CLKACT_SHIFT 24 -#define CRL_APB_LPD_LSBUS_CTRL_CLKACT_MASK 0x01000000U +#define CRL_APB_LPD_LSBUS_CTRL_CLKACT_DEFVAL 0x01001800 +#define CRL_APB_LPD_LSBUS_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_LPD_LSBUS_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_DEFVAL #undef CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_SHIFT #undef CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_MASK -#define CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_DEFVAL 0x01001800 -#define CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_DEFVAL 0x01001800 +#define CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRL_APB_LPD_LSBUS_CTRL_SRCSEL_DEFVAL #undef CRL_APB_LPD_LSBUS_CTRL_SRCSEL_SHIFT #undef CRL_APB_LPD_LSBUS_CTRL_SRCSEL_MASK -#define CRL_APB_LPD_LSBUS_CTRL_SRCSEL_DEFVAL 0x01001800 -#define CRL_APB_LPD_LSBUS_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_LPD_LSBUS_CTRL_SRCSEL_MASK 0x00000007U +#define CRL_APB_LPD_LSBUS_CTRL_SRCSEL_DEFVAL 0x01001800 +#define CRL_APB_LPD_LSBUS_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_LPD_LSBUS_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRL_APB_DBG_LPD_CTRL_CLKACT_DEFVAL #undef CRL_APB_DBG_LPD_CTRL_CLKACT_SHIFT #undef CRL_APB_DBG_LPD_CTRL_CLKACT_MASK -#define CRL_APB_DBG_LPD_CTRL_CLKACT_DEFVAL 0x01002000 -#define CRL_APB_DBG_LPD_CTRL_CLKACT_SHIFT 24 -#define CRL_APB_DBG_LPD_CTRL_CLKACT_MASK 0x01000000U +#define CRL_APB_DBG_LPD_CTRL_CLKACT_DEFVAL 0x01002000 +#define CRL_APB_DBG_LPD_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_DBG_LPD_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_DBG_LPD_CTRL_DIVISOR0_DEFVAL #undef CRL_APB_DBG_LPD_CTRL_DIVISOR0_SHIFT #undef CRL_APB_DBG_LPD_CTRL_DIVISOR0_MASK -#define CRL_APB_DBG_LPD_CTRL_DIVISOR0_DEFVAL 0x01002000 -#define CRL_APB_DBG_LPD_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_DBG_LPD_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRL_APB_DBG_LPD_CTRL_DIVISOR0_DEFVAL 0x01002000 +#define CRL_APB_DBG_LPD_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_DBG_LPD_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRL_APB_DBG_LPD_CTRL_SRCSEL_DEFVAL #undef CRL_APB_DBG_LPD_CTRL_SRCSEL_SHIFT #undef CRL_APB_DBG_LPD_CTRL_SRCSEL_MASK -#define CRL_APB_DBG_LPD_CTRL_SRCSEL_DEFVAL 0x01002000 -#define CRL_APB_DBG_LPD_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_DBG_LPD_CTRL_SRCSEL_MASK 0x00000007U +#define CRL_APB_DBG_LPD_CTRL_SRCSEL_DEFVAL 0x01002000 +#define CRL_APB_DBG_LPD_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_DBG_LPD_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRL_APB_ADMA_REF_CTRL_CLKACT_DEFVAL #undef CRL_APB_ADMA_REF_CTRL_CLKACT_SHIFT #undef CRL_APB_ADMA_REF_CTRL_CLKACT_MASK -#define CRL_APB_ADMA_REF_CTRL_CLKACT_DEFVAL 0x00002000 -#define CRL_APB_ADMA_REF_CTRL_CLKACT_SHIFT 24 -#define CRL_APB_ADMA_REF_CTRL_CLKACT_MASK 0x01000000U +#define CRL_APB_ADMA_REF_CTRL_CLKACT_DEFVAL 0x00002000 +#define CRL_APB_ADMA_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_ADMA_REF_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_ADMA_REF_CTRL_DIVISOR0_DEFVAL #undef CRL_APB_ADMA_REF_CTRL_DIVISOR0_SHIFT #undef CRL_APB_ADMA_REF_CTRL_DIVISOR0_MASK -#define CRL_APB_ADMA_REF_CTRL_DIVISOR0_DEFVAL 0x00002000 -#define CRL_APB_ADMA_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_ADMA_REF_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRL_APB_ADMA_REF_CTRL_DIVISOR0_DEFVAL 0x00002000 +#define CRL_APB_ADMA_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_ADMA_REF_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRL_APB_ADMA_REF_CTRL_SRCSEL_DEFVAL #undef CRL_APB_ADMA_REF_CTRL_SRCSEL_SHIFT #undef CRL_APB_ADMA_REF_CTRL_SRCSEL_MASK -#define CRL_APB_ADMA_REF_CTRL_SRCSEL_DEFVAL 0x00002000 -#define CRL_APB_ADMA_REF_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_ADMA_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRL_APB_ADMA_REF_CTRL_SRCSEL_DEFVAL 0x00002000 +#define CRL_APB_ADMA_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_ADMA_REF_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRL_APB_PL0_REF_CTRL_CLKACT_DEFVAL #undef CRL_APB_PL0_REF_CTRL_CLKACT_SHIFT #undef CRL_APB_PL0_REF_CTRL_CLKACT_MASK -#define CRL_APB_PL0_REF_CTRL_CLKACT_DEFVAL 0x00052000 -#define CRL_APB_PL0_REF_CTRL_CLKACT_SHIFT 24 -#define CRL_APB_PL0_REF_CTRL_CLKACT_MASK 0x01000000U +#define CRL_APB_PL0_REF_CTRL_CLKACT_DEFVAL 0x00052000 +#define CRL_APB_PL0_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_PL0_REF_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_PL0_REF_CTRL_DIVISOR1_DEFVAL #undef CRL_APB_PL0_REF_CTRL_DIVISOR1_SHIFT #undef CRL_APB_PL0_REF_CTRL_DIVISOR1_MASK -#define CRL_APB_PL0_REF_CTRL_DIVISOR1_DEFVAL 0x00052000 -#define CRL_APB_PL0_REF_CTRL_DIVISOR1_SHIFT 16 -#define CRL_APB_PL0_REF_CTRL_DIVISOR1_MASK 0x003F0000U +#define CRL_APB_PL0_REF_CTRL_DIVISOR1_DEFVAL 0x00052000 +#define CRL_APB_PL0_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_PL0_REF_CTRL_DIVISOR1_MASK 0x003F0000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_PL0_REF_CTRL_DIVISOR0_DEFVAL #undef CRL_APB_PL0_REF_CTRL_DIVISOR0_SHIFT #undef CRL_APB_PL0_REF_CTRL_DIVISOR0_MASK -#define CRL_APB_PL0_REF_CTRL_DIVISOR0_DEFVAL 0x00052000 -#define CRL_APB_PL0_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_PL0_REF_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRL_APB_PL0_REF_CTRL_DIVISOR0_DEFVAL 0x00052000 +#define CRL_APB_PL0_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_PL0_REF_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRL_APB_PL0_REF_CTRL_SRCSEL_DEFVAL #undef CRL_APB_PL0_REF_CTRL_SRCSEL_SHIFT #undef CRL_APB_PL0_REF_CTRL_SRCSEL_MASK -#define CRL_APB_PL0_REF_CTRL_SRCSEL_DEFVAL 0x00052000 -#define CRL_APB_PL0_REF_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_PL0_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRL_APB_PL0_REF_CTRL_SRCSEL_DEFVAL 0x00052000 +#define CRL_APB_PL0_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_PL0_REF_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ -#undef CRL_APB_PL1_REF_CTRL_CLKACT_DEFVAL -#undef CRL_APB_PL1_REF_CTRL_CLKACT_SHIFT -#undef CRL_APB_PL1_REF_CTRL_CLKACT_MASK -#define CRL_APB_PL1_REF_CTRL_CLKACT_DEFVAL 0x00052000 -#define CRL_APB_PL1_REF_CTRL_CLKACT_SHIFT 24 -#define CRL_APB_PL1_REF_CTRL_CLKACT_MASK 0x01000000U - -/*6 bit divider*/ -#undef CRL_APB_PL1_REF_CTRL_DIVISOR1_DEFVAL -#undef CRL_APB_PL1_REF_CTRL_DIVISOR1_SHIFT -#undef CRL_APB_PL1_REF_CTRL_DIVISOR1_MASK -#define CRL_APB_PL1_REF_CTRL_DIVISOR1_DEFVAL 0x00052000 -#define CRL_APB_PL1_REF_CTRL_DIVISOR1_SHIFT 16 -#define CRL_APB_PL1_REF_CTRL_DIVISOR1_MASK 0x003F0000U - -/*6 bit divider*/ -#undef CRL_APB_PL1_REF_CTRL_DIVISOR0_DEFVAL -#undef CRL_APB_PL1_REF_CTRL_DIVISOR0_SHIFT -#undef CRL_APB_PL1_REF_CTRL_DIVISOR0_MASK -#define CRL_APB_PL1_REF_CTRL_DIVISOR0_DEFVAL 0x00052000 -#define CRL_APB_PL1_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_PL1_REF_CTRL_DIVISOR0_MASK 0x00003F00U - -/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.)*/ -#undef CRL_APB_PL1_REF_CTRL_SRCSEL_DEFVAL -#undef CRL_APB_PL1_REF_CTRL_SRCSEL_SHIFT -#undef CRL_APB_PL1_REF_CTRL_SRCSEL_MASK -#define CRL_APB_PL1_REF_CTRL_SRCSEL_DEFVAL 0x00052000 -#define CRL_APB_PL1_REF_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_PL1_REF_CTRL_SRCSEL_MASK 0x00000007U - -/*Clock active signal. Switch to 0 to disable the clock*/ -#undef CRL_APB_PL2_REF_CTRL_CLKACT_DEFVAL -#undef CRL_APB_PL2_REF_CTRL_CLKACT_SHIFT -#undef CRL_APB_PL2_REF_CTRL_CLKACT_MASK -#define CRL_APB_PL2_REF_CTRL_CLKACT_DEFVAL 0x00052000 -#define CRL_APB_PL2_REF_CTRL_CLKACT_SHIFT 24 -#define CRL_APB_PL2_REF_CTRL_CLKACT_MASK 0x01000000U - -/*6 bit divider*/ -#undef CRL_APB_PL2_REF_CTRL_DIVISOR1_DEFVAL -#undef CRL_APB_PL2_REF_CTRL_DIVISOR1_SHIFT -#undef CRL_APB_PL2_REF_CTRL_DIVISOR1_MASK -#define CRL_APB_PL2_REF_CTRL_DIVISOR1_DEFVAL 0x00052000 -#define CRL_APB_PL2_REF_CTRL_DIVISOR1_SHIFT 16 -#define CRL_APB_PL2_REF_CTRL_DIVISOR1_MASK 0x003F0000U - -/*6 bit divider*/ -#undef CRL_APB_PL2_REF_CTRL_DIVISOR0_DEFVAL -#undef CRL_APB_PL2_REF_CTRL_DIVISOR0_SHIFT -#undef CRL_APB_PL2_REF_CTRL_DIVISOR0_MASK -#define CRL_APB_PL2_REF_CTRL_DIVISOR0_DEFVAL 0x00052000 -#define CRL_APB_PL2_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_PL2_REF_CTRL_DIVISOR0_MASK 0x00003F00U - -/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.)*/ -#undef CRL_APB_PL2_REF_CTRL_SRCSEL_DEFVAL -#undef CRL_APB_PL2_REF_CTRL_SRCSEL_SHIFT -#undef CRL_APB_PL2_REF_CTRL_SRCSEL_MASK -#define CRL_APB_PL2_REF_CTRL_SRCSEL_DEFVAL 0x00052000 -#define CRL_APB_PL2_REF_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_PL2_REF_CTRL_SRCSEL_MASK 0x00000007U - -/*Clock active signal. Switch to 0 to disable the clock*/ -#undef CRL_APB_PL3_REF_CTRL_CLKACT_DEFVAL -#undef CRL_APB_PL3_REF_CTRL_CLKACT_SHIFT -#undef CRL_APB_PL3_REF_CTRL_CLKACT_MASK -#define CRL_APB_PL3_REF_CTRL_CLKACT_DEFVAL 0x00052000 -#define CRL_APB_PL3_REF_CTRL_CLKACT_SHIFT 24 -#define CRL_APB_PL3_REF_CTRL_CLKACT_MASK 0x01000000U - -/*6 bit divider*/ -#undef CRL_APB_PL3_REF_CTRL_DIVISOR1_DEFVAL -#undef CRL_APB_PL3_REF_CTRL_DIVISOR1_SHIFT -#undef CRL_APB_PL3_REF_CTRL_DIVISOR1_MASK -#define CRL_APB_PL3_REF_CTRL_DIVISOR1_DEFVAL 0x00052000 -#define CRL_APB_PL3_REF_CTRL_DIVISOR1_SHIFT 16 -#define CRL_APB_PL3_REF_CTRL_DIVISOR1_MASK 0x003F0000U - -/*6 bit divider*/ -#undef CRL_APB_PL3_REF_CTRL_DIVISOR0_DEFVAL -#undef CRL_APB_PL3_REF_CTRL_DIVISOR0_SHIFT -#undef CRL_APB_PL3_REF_CTRL_DIVISOR0_MASK -#define CRL_APB_PL3_REF_CTRL_DIVISOR0_DEFVAL 0x00052000 -#define CRL_APB_PL3_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_PL3_REF_CTRL_DIVISOR0_MASK 0x00003F00U - -/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.)*/ -#undef CRL_APB_PL3_REF_CTRL_SRCSEL_DEFVAL -#undef CRL_APB_PL3_REF_CTRL_SRCSEL_SHIFT -#undef CRL_APB_PL3_REF_CTRL_SRCSEL_MASK -#define CRL_APB_PL3_REF_CTRL_SRCSEL_DEFVAL 0x00052000 -#define CRL_APB_PL3_REF_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_PL3_REF_CTRL_SRCSEL_MASK 0x00000007U - -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_AMS_REF_CTRL_DIVISOR1_DEFVAL #undef CRL_APB_AMS_REF_CTRL_DIVISOR1_SHIFT #undef CRL_APB_AMS_REF_CTRL_DIVISOR1_MASK -#define CRL_APB_AMS_REF_CTRL_DIVISOR1_DEFVAL 0x01001800 -#define CRL_APB_AMS_REF_CTRL_DIVISOR1_SHIFT 16 -#define CRL_APB_AMS_REF_CTRL_DIVISOR1_MASK 0x003F0000U +#define CRL_APB_AMS_REF_CTRL_DIVISOR1_DEFVAL 0x01001800 +#define CRL_APB_AMS_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRL_APB_AMS_REF_CTRL_DIVISOR1_MASK 0x003F0000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_AMS_REF_CTRL_DIVISOR0_DEFVAL #undef CRL_APB_AMS_REF_CTRL_DIVISOR0_SHIFT #undef CRL_APB_AMS_REF_CTRL_DIVISOR0_MASK -#define CRL_APB_AMS_REF_CTRL_DIVISOR0_DEFVAL 0x01001800 -#define CRL_APB_AMS_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_AMS_REF_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRL_APB_AMS_REF_CTRL_DIVISOR0_DEFVAL 0x01001800 +#define CRL_APB_AMS_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_AMS_REF_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled af + * ter 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRL_APB_AMS_REF_CTRL_SRCSEL_DEFVAL #undef CRL_APB_AMS_REF_CTRL_SRCSEL_SHIFT #undef CRL_APB_AMS_REF_CTRL_SRCSEL_MASK -#define CRL_APB_AMS_REF_CTRL_SRCSEL_DEFVAL 0x01001800 -#define CRL_APB_AMS_REF_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_AMS_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRL_APB_AMS_REF_CTRL_SRCSEL_DEFVAL 0x01001800 +#define CRL_APB_AMS_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_AMS_REF_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRL_APB_AMS_REF_CTRL_CLKACT_DEFVAL #undef CRL_APB_AMS_REF_CTRL_CLKACT_SHIFT #undef CRL_APB_AMS_REF_CTRL_CLKACT_MASK -#define CRL_APB_AMS_REF_CTRL_CLKACT_DEFVAL 0x01001800 -#define CRL_APB_AMS_REF_CTRL_CLKACT_SHIFT 24 -#define CRL_APB_AMS_REF_CTRL_CLKACT_MASK 0x01000000U +#define CRL_APB_AMS_REF_CTRL_CLKACT_DEFVAL 0x01001800 +#define CRL_APB_AMS_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_AMS_REF_CTRL_CLKACT_MASK 0x01000000U -/*000 = IOPLL; 001 = RPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This - is not usually an issue, but designers must be aware.)*/ +/* +* 000 = IOPLL; 001 = RPLL; (This signal may only be toggled after 4 cycles + * of the old clock and 4 cycles of the new clock. This is not usually an + * issue, but designers must be aware.) +*/ #undef CRL_APB_DLL_REF_CTRL_SRCSEL_DEFVAL #undef CRL_APB_DLL_REF_CTRL_SRCSEL_SHIFT #undef CRL_APB_DLL_REF_CTRL_SRCSEL_MASK -#define CRL_APB_DLL_REF_CTRL_SRCSEL_DEFVAL 0x00000000 -#define CRL_APB_DLL_REF_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_DLL_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRL_APB_DLL_REF_CTRL_SRCSEL_DEFVAL 0x00000000 +#define CRL_APB_DLL_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_DLL_REF_CTRL_SRCSEL_MASK 0x00000007U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_DEFVAL #undef CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_SHIFT #undef CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_MASK -#define CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_DEFVAL 0x00001800 -#define CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_DEFVAL 0x00001800 +#define CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_MASK 0x00003F00U -/*1XX = pss_ref_clk; 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and - cycles of the new clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 1XX = pss_ref_clk; 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may + * only be toggled after 4 cycles of the old clock and 4 cycles of the new + * clock. This is not usually an issue, but designers must be aware.) +*/ #undef CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_DEFVAL #undef CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_SHIFT #undef CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_MASK -#define CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_DEFVAL 0x00001800 -#define CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_SHIFT 0 -#define CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_DEFVAL 0x00001800 +#define CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_SHIFT 0 +#define CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_DEFVAL #undef CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_SHIFT #undef CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_MASK -#define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_DEFVAL 0x00001800 -#define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_SHIFT 24 -#define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_MASK 0x01000000U +#define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_DEFVAL 0x00001800 +#define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_SHIFT 24 +#define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_MASK 0x01000000U -/*000 = IOPLL_TO_FPD; 010 = APLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of - he new clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = IOPLL_TO_FPD; 010 = APLL; 011 = DPLL; (This signal may only be tog + * gled after 4 cycles of the old clock and 4 cycles of the new clock. This + * is not usually an issue, but designers must be aware.) +*/ #undef CRF_APB_SATA_REF_CTRL_SRCSEL_DEFVAL #undef CRF_APB_SATA_REF_CTRL_SRCSEL_SHIFT #undef CRF_APB_SATA_REF_CTRL_SRCSEL_MASK -#define CRF_APB_SATA_REF_CTRL_SRCSEL_DEFVAL 0x01001600 -#define CRF_APB_SATA_REF_CTRL_SRCSEL_SHIFT 0 -#define CRF_APB_SATA_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRF_APB_SATA_REF_CTRL_SRCSEL_DEFVAL 0x01001600 +#define CRF_APB_SATA_REF_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_SATA_REF_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRF_APB_SATA_REF_CTRL_CLKACT_DEFVAL #undef CRF_APB_SATA_REF_CTRL_CLKACT_SHIFT #undef CRF_APB_SATA_REF_CTRL_CLKACT_MASK -#define CRF_APB_SATA_REF_CTRL_CLKACT_DEFVAL 0x01001600 -#define CRF_APB_SATA_REF_CTRL_CLKACT_SHIFT 24 -#define CRF_APB_SATA_REF_CTRL_CLKACT_MASK 0x01000000U +#define CRF_APB_SATA_REF_CTRL_CLKACT_DEFVAL 0x01001600 +#define CRF_APB_SATA_REF_CTRL_CLKACT_SHIFT 24 +#define CRF_APB_SATA_REF_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRF_APB_SATA_REF_CTRL_DIVISOR0_DEFVAL #undef CRF_APB_SATA_REF_CTRL_DIVISOR0_SHIFT #undef CRF_APB_SATA_REF_CTRL_DIVISOR0_MASK -#define CRF_APB_SATA_REF_CTRL_DIVISOR0_DEFVAL 0x01001600 -#define CRF_APB_SATA_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRF_APB_SATA_REF_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRF_APB_SATA_REF_CTRL_DIVISOR0_DEFVAL 0x01001600 +#define CRF_APB_SATA_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_SATA_REF_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = IOPLL_TO_FPD; 010 = RPLL_TO_FPD; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cyc - es of the new clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = IOPLL_TO_FPD; 010 = RPLL_TO_FPD; 011 = DPLL; (This signal may only + * be toggled after 4 cycles of the old clock and 4 cycles of the new cloc + * k. This is not usually an issue, but designers must be aware.) +*/ #undef CRF_APB_PCIE_REF_CTRL_SRCSEL_DEFVAL #undef CRF_APB_PCIE_REF_CTRL_SRCSEL_SHIFT #undef CRF_APB_PCIE_REF_CTRL_SRCSEL_MASK -#define CRF_APB_PCIE_REF_CTRL_SRCSEL_DEFVAL 0x00001500 -#define CRF_APB_PCIE_REF_CTRL_SRCSEL_SHIFT 0 -#define CRF_APB_PCIE_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRF_APB_PCIE_REF_CTRL_SRCSEL_DEFVAL 0x00001500 +#define CRF_APB_PCIE_REF_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_PCIE_REF_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRF_APB_PCIE_REF_CTRL_CLKACT_DEFVAL #undef CRF_APB_PCIE_REF_CTRL_CLKACT_SHIFT #undef CRF_APB_PCIE_REF_CTRL_CLKACT_MASK -#define CRF_APB_PCIE_REF_CTRL_CLKACT_DEFVAL 0x00001500 -#define CRF_APB_PCIE_REF_CTRL_CLKACT_SHIFT 24 -#define CRF_APB_PCIE_REF_CTRL_CLKACT_MASK 0x01000000U +#define CRF_APB_PCIE_REF_CTRL_CLKACT_DEFVAL 0x00001500 +#define CRF_APB_PCIE_REF_CTRL_CLKACT_SHIFT 24 +#define CRF_APB_PCIE_REF_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRF_APB_PCIE_REF_CTRL_DIVISOR0_DEFVAL #undef CRF_APB_PCIE_REF_CTRL_DIVISOR0_SHIFT #undef CRF_APB_PCIE_REF_CTRL_DIVISOR0_MASK -#define CRF_APB_PCIE_REF_CTRL_DIVISOR0_DEFVAL 0x00001500 -#define CRF_APB_PCIE_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRF_APB_PCIE_REF_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRF_APB_PCIE_REF_CTRL_DIVISOR0_DEFVAL 0x00001500 +#define CRF_APB_PCIE_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_PCIE_REF_CTRL_DIVISOR0_MASK 0x00003F00U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_DEFVAL #undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_SHIFT #undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_MASK -#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_DEFVAL 0x01002300 -#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_SHIFT 16 -#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_MASK 0x003F0000U +#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_DEFVAL 0x01002300 +#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_MASK 0x003F0000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_DEFVAL #undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_SHIFT #undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_MASK -#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_DEFVAL 0x01002300 -#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_DEFVAL 0x01002300 +#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (This signal may only be toggled after 4 cycles of the - ld clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (T + * his signal may only be toggled after 4 cycles of the old clock and 4 cyc + * les of the new clock. This is not usually an issue, but designers must b + * e aware.) +*/ #undef CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_DEFVAL #undef CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_SHIFT #undef CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_MASK -#define CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_DEFVAL 0x01002300 -#define CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_SHIFT 0 -#define CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_DEFVAL 0x01002300 +#define CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_DEFVAL #undef CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_SHIFT #undef CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_MASK -#define CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_DEFVAL 0x01002300 -#define CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_SHIFT 24 -#define CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_MASK 0x01000000U +#define CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_DEFVAL 0x01002300 +#define CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_SHIFT 24 +#define CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_DEFVAL #undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_SHIFT #undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_MASK -#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_DEFVAL 0x01032300 -#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_SHIFT 16 -#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_MASK 0x003F0000U +#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_DEFVAL 0x01032300 +#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_MASK 0x003F0000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_DEFVAL #undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_SHIFT #undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_MASK -#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_DEFVAL 0x01032300 -#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_DEFVAL 0x01032300 +#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (This signal may only be toggled after 4 cycles of the - ld clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (T + * his signal may only be toggled after 4 cycles of the old clock and 4 cyc + * les of the new clock. This is not usually an issue, but designers must b + * e aware.) +*/ #undef CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_DEFVAL #undef CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_SHIFT #undef CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_MASK -#define CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_DEFVAL 0x01032300 -#define CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_SHIFT 0 -#define CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_DEFVAL 0x01032300 +#define CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_DEFVAL #undef CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_SHIFT #undef CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_MASK -#define CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_DEFVAL 0x01032300 -#define CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_SHIFT 24 -#define CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_MASK 0x01000000U +#define CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_DEFVAL 0x01032300 +#define CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_SHIFT 24 +#define CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRF_APB_DP_STC_REF_CTRL_DIVISOR1_DEFVAL #undef CRF_APB_DP_STC_REF_CTRL_DIVISOR1_SHIFT #undef CRF_APB_DP_STC_REF_CTRL_DIVISOR1_MASK -#define CRF_APB_DP_STC_REF_CTRL_DIVISOR1_DEFVAL 0x01203200 -#define CRF_APB_DP_STC_REF_CTRL_DIVISOR1_SHIFT 16 -#define CRF_APB_DP_STC_REF_CTRL_DIVISOR1_MASK 0x003F0000U +#define CRF_APB_DP_STC_REF_CTRL_DIVISOR1_DEFVAL 0x01203200 +#define CRF_APB_DP_STC_REF_CTRL_DIVISOR1_SHIFT 16 +#define CRF_APB_DP_STC_REF_CTRL_DIVISOR1_MASK 0x003F0000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRF_APB_DP_STC_REF_CTRL_DIVISOR0_DEFVAL #undef CRF_APB_DP_STC_REF_CTRL_DIVISOR0_SHIFT #undef CRF_APB_DP_STC_REF_CTRL_DIVISOR0_MASK -#define CRF_APB_DP_STC_REF_CTRL_DIVISOR0_DEFVAL 0x01203200 -#define CRF_APB_DP_STC_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRF_APB_DP_STC_REF_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRF_APB_DP_STC_REF_CTRL_DIVISOR0_DEFVAL 0x01203200 +#define CRF_APB_DP_STC_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_DP_STC_REF_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of t - e new clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD; (This signal may only be togg + * led after 4 cycles of the old clock and 4 cycles of the new clock. This + * is not usually an issue, but designers must be aware.) +*/ #undef CRF_APB_DP_STC_REF_CTRL_SRCSEL_DEFVAL #undef CRF_APB_DP_STC_REF_CTRL_SRCSEL_SHIFT #undef CRF_APB_DP_STC_REF_CTRL_SRCSEL_MASK -#define CRF_APB_DP_STC_REF_CTRL_SRCSEL_DEFVAL 0x01203200 -#define CRF_APB_DP_STC_REF_CTRL_SRCSEL_SHIFT 0 -#define CRF_APB_DP_STC_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRF_APB_DP_STC_REF_CTRL_SRCSEL_DEFVAL 0x01203200 +#define CRF_APB_DP_STC_REF_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_DP_STC_REF_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRF_APB_DP_STC_REF_CTRL_CLKACT_DEFVAL #undef CRF_APB_DP_STC_REF_CTRL_CLKACT_SHIFT #undef CRF_APB_DP_STC_REF_CTRL_CLKACT_MASK -#define CRF_APB_DP_STC_REF_CTRL_CLKACT_DEFVAL 0x01203200 -#define CRF_APB_DP_STC_REF_CTRL_CLKACT_SHIFT 24 -#define CRF_APB_DP_STC_REF_CTRL_CLKACT_MASK 0x01000000U +#define CRF_APB_DP_STC_REF_CTRL_CLKACT_DEFVAL 0x01203200 +#define CRF_APB_DP_STC_REF_CTRL_CLKACT_SHIFT 24 +#define CRF_APB_DP_STC_REF_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRF_APB_ACPU_CTRL_DIVISOR0_DEFVAL #undef CRF_APB_ACPU_CTRL_DIVISOR0_SHIFT #undef CRF_APB_ACPU_CTRL_DIVISOR0_MASK -#define CRF_APB_ACPU_CTRL_DIVISOR0_DEFVAL 0x03000400 -#define CRF_APB_ACPU_CTRL_DIVISOR0_SHIFT 8 -#define CRF_APB_ACPU_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRF_APB_ACPU_CTRL_DIVISOR0_DEFVAL 0x03000400 +#define CRF_APB_ACPU_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_ACPU_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = APLL; 010 = DPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - lock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = APLL; 010 = DPLL; 011 = VPLL; (This signal may only be toggled aft + * er 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRF_APB_ACPU_CTRL_SRCSEL_DEFVAL #undef CRF_APB_ACPU_CTRL_SRCSEL_SHIFT #undef CRF_APB_ACPU_CTRL_SRCSEL_MASK -#define CRF_APB_ACPU_CTRL_SRCSEL_DEFVAL 0x03000400 -#define CRF_APB_ACPU_CTRL_SRCSEL_SHIFT 0 -#define CRF_APB_ACPU_CTRL_SRCSEL_MASK 0x00000007U +#define CRF_APB_ACPU_CTRL_SRCSEL_DEFVAL 0x03000400 +#define CRF_APB_ACPU_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_ACPU_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock. For the half speed APU Clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock. For the half spee + * d APU Clock +*/ #undef CRF_APB_ACPU_CTRL_CLKACT_HALF_DEFVAL #undef CRF_APB_ACPU_CTRL_CLKACT_HALF_SHIFT #undef CRF_APB_ACPU_CTRL_CLKACT_HALF_MASK -#define CRF_APB_ACPU_CTRL_CLKACT_HALF_DEFVAL 0x03000400 -#define CRF_APB_ACPU_CTRL_CLKACT_HALF_SHIFT 25 -#define CRF_APB_ACPU_CTRL_CLKACT_HALF_MASK 0x02000000U +#define CRF_APB_ACPU_CTRL_CLKACT_HALF_DEFVAL 0x03000400 +#define CRF_APB_ACPU_CTRL_CLKACT_HALF_SHIFT 25 +#define CRF_APB_ACPU_CTRL_CLKACT_HALF_MASK 0x02000000U -/*Clock active signal. Switch to 0 to disable the clock. For the full speed ACPUX Clock. This will shut off the high speed cloc - to the entire APU*/ +/* +* Clock active signal. Switch to 0 to disable the clock. For the full spee + * d ACPUX Clock. This will shut off the high speed clock to the entire APU +*/ #undef CRF_APB_ACPU_CTRL_CLKACT_FULL_DEFVAL #undef CRF_APB_ACPU_CTRL_CLKACT_FULL_SHIFT #undef CRF_APB_ACPU_CTRL_CLKACT_FULL_MASK -#define CRF_APB_ACPU_CTRL_CLKACT_FULL_DEFVAL 0x03000400 -#define CRF_APB_ACPU_CTRL_CLKACT_FULL_SHIFT 24 -#define CRF_APB_ACPU_CTRL_CLKACT_FULL_MASK 0x01000000U +#define CRF_APB_ACPU_CTRL_CLKACT_FULL_DEFVAL 0x03000400 +#define CRF_APB_ACPU_CTRL_CLKACT_FULL_SHIFT 24 +#define CRF_APB_ACPU_CTRL_CLKACT_FULL_MASK 0x01000000U -/*6 bit divider*/ -#undef CRF_APB_DBG_TRACE_CTRL_DIVISOR0_DEFVAL -#undef CRF_APB_DBG_TRACE_CTRL_DIVISOR0_SHIFT -#undef CRF_APB_DBG_TRACE_CTRL_DIVISOR0_MASK -#define CRF_APB_DBG_TRACE_CTRL_DIVISOR0_DEFVAL 0x00002500 -#define CRF_APB_DBG_TRACE_CTRL_DIVISOR0_SHIFT 8 -#define CRF_APB_DBG_TRACE_CTRL_DIVISOR0_MASK 0x00003F00U - -/*000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of - he new clock. This is not usually an issue, but designers must be aware.)*/ -#undef CRF_APB_DBG_TRACE_CTRL_SRCSEL_DEFVAL -#undef CRF_APB_DBG_TRACE_CTRL_SRCSEL_SHIFT -#undef CRF_APB_DBG_TRACE_CTRL_SRCSEL_MASK -#define CRF_APB_DBG_TRACE_CTRL_SRCSEL_DEFVAL 0x00002500 -#define CRF_APB_DBG_TRACE_CTRL_SRCSEL_SHIFT 0 -#define CRF_APB_DBG_TRACE_CTRL_SRCSEL_MASK 0x00000007U - -/*Clock active signal. Switch to 0 to disable the clock*/ -#undef CRF_APB_DBG_TRACE_CTRL_CLKACT_DEFVAL -#undef CRF_APB_DBG_TRACE_CTRL_CLKACT_SHIFT -#undef CRF_APB_DBG_TRACE_CTRL_CLKACT_MASK -#define CRF_APB_DBG_TRACE_CTRL_CLKACT_DEFVAL 0x00002500 -#define CRF_APB_DBG_TRACE_CTRL_CLKACT_SHIFT 24 -#define CRF_APB_DBG_TRACE_CTRL_CLKACT_MASK 0x01000000U - -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRF_APB_DBG_FPD_CTRL_DIVISOR0_DEFVAL #undef CRF_APB_DBG_FPD_CTRL_DIVISOR0_SHIFT #undef CRF_APB_DBG_FPD_CTRL_DIVISOR0_MASK -#define CRF_APB_DBG_FPD_CTRL_DIVISOR0_DEFVAL 0x01002500 -#define CRF_APB_DBG_FPD_CTRL_DIVISOR0_SHIFT 8 -#define CRF_APB_DBG_FPD_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRF_APB_DBG_FPD_CTRL_DIVISOR0_DEFVAL 0x01002500 +#define CRF_APB_DBG_FPD_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_DBG_FPD_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of - he new clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be tog + * gled after 4 cycles of the old clock and 4 cycles of the new clock. This + * is not usually an issue, but designers must be aware.) +*/ #undef CRF_APB_DBG_FPD_CTRL_SRCSEL_DEFVAL #undef CRF_APB_DBG_FPD_CTRL_SRCSEL_SHIFT #undef CRF_APB_DBG_FPD_CTRL_SRCSEL_MASK -#define CRF_APB_DBG_FPD_CTRL_SRCSEL_DEFVAL 0x01002500 -#define CRF_APB_DBG_FPD_CTRL_SRCSEL_SHIFT 0 -#define CRF_APB_DBG_FPD_CTRL_SRCSEL_MASK 0x00000007U +#define CRF_APB_DBG_FPD_CTRL_SRCSEL_DEFVAL 0x01002500 +#define CRF_APB_DBG_FPD_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_DBG_FPD_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRF_APB_DBG_FPD_CTRL_CLKACT_DEFVAL #undef CRF_APB_DBG_FPD_CTRL_CLKACT_SHIFT #undef CRF_APB_DBG_FPD_CTRL_CLKACT_MASK -#define CRF_APB_DBG_FPD_CTRL_CLKACT_DEFVAL 0x01002500 -#define CRF_APB_DBG_FPD_CTRL_CLKACT_SHIFT 24 -#define CRF_APB_DBG_FPD_CTRL_CLKACT_MASK 0x01000000U +#define CRF_APB_DBG_FPD_CTRL_CLKACT_DEFVAL 0x01002500 +#define CRF_APB_DBG_FPD_CTRL_CLKACT_SHIFT 24 +#define CRF_APB_DBG_FPD_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRF_APB_DDR_CTRL_DIVISOR0_DEFVAL #undef CRF_APB_DDR_CTRL_DIVISOR0_SHIFT #undef CRF_APB_DDR_CTRL_DIVISOR0_MASK -#define CRF_APB_DDR_CTRL_DIVISOR0_DEFVAL 0x01000500 -#define CRF_APB_DDR_CTRL_DIVISOR0_SHIFT 8 -#define CRF_APB_DDR_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRF_APB_DDR_CTRL_DIVISOR0_DEFVAL 0x01000500 +#define CRF_APB_DDR_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_DDR_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = DPLL; 001 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This - s not usually an issue, but designers must be aware.)*/ +/* +* 000 = DPLL; 001 = VPLL; (This signal may only be toggled after 4 cycles + * of the old clock and 4 cycles of the new clock. This is not usually an i + * ssue, but designers must be aware.) +*/ #undef CRF_APB_DDR_CTRL_SRCSEL_DEFVAL #undef CRF_APB_DDR_CTRL_SRCSEL_SHIFT #undef CRF_APB_DDR_CTRL_SRCSEL_MASK -#define CRF_APB_DDR_CTRL_SRCSEL_DEFVAL 0x01000500 -#define CRF_APB_DDR_CTRL_SRCSEL_SHIFT 0 -#define CRF_APB_DDR_CTRL_SRCSEL_MASK 0x00000007U +#define CRF_APB_DDR_CTRL_SRCSEL_DEFVAL 0x01000500 +#define CRF_APB_DDR_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_DDR_CTRL_SRCSEL_MASK 0x00000007U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRF_APB_GPU_REF_CTRL_DIVISOR0_DEFVAL #undef CRF_APB_GPU_REF_CTRL_DIVISOR0_SHIFT #undef CRF_APB_GPU_REF_CTRL_DIVISOR0_MASK -#define CRF_APB_GPU_REF_CTRL_DIVISOR0_DEFVAL 0x00001500 -#define CRF_APB_GPU_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRF_APB_GPU_REF_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRF_APB_GPU_REF_CTRL_DIVISOR0_DEFVAL 0x00001500 +#define CRF_APB_GPU_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_GPU_REF_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = IOPLL_TO_FPD; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of - he new clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = IOPLL_TO_FPD; 010 = VPLL; 011 = DPLL; (This signal may only be tog + * gled after 4 cycles of the old clock and 4 cycles of the new clock. This + * is not usually an issue, but designers must be aware.) +*/ #undef CRF_APB_GPU_REF_CTRL_SRCSEL_DEFVAL #undef CRF_APB_GPU_REF_CTRL_SRCSEL_SHIFT #undef CRF_APB_GPU_REF_CTRL_SRCSEL_MASK -#define CRF_APB_GPU_REF_CTRL_SRCSEL_DEFVAL 0x00001500 -#define CRF_APB_GPU_REF_CTRL_SRCSEL_SHIFT 0 -#define CRF_APB_GPU_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRF_APB_GPU_REF_CTRL_SRCSEL_DEFVAL 0x00001500 +#define CRF_APB_GPU_REF_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_GPU_REF_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock, which will stop clock for GPU (and both Pixel Processors).*/ +/* +* Clock active signal. Switch to 0 to disable the clock, which will stop c + * lock for GPU (and both Pixel Processors). +*/ #undef CRF_APB_GPU_REF_CTRL_CLKACT_DEFVAL #undef CRF_APB_GPU_REF_CTRL_CLKACT_SHIFT #undef CRF_APB_GPU_REF_CTRL_CLKACT_MASK -#define CRF_APB_GPU_REF_CTRL_CLKACT_DEFVAL 0x00001500 -#define CRF_APB_GPU_REF_CTRL_CLKACT_SHIFT 24 -#define CRF_APB_GPU_REF_CTRL_CLKACT_MASK 0x01000000U +#define CRF_APB_GPU_REF_CTRL_CLKACT_DEFVAL 0x00001500 +#define CRF_APB_GPU_REF_CTRL_CLKACT_SHIFT 24 +#define CRF_APB_GPU_REF_CTRL_CLKACT_MASK 0x01000000U -/*Clock active signal for Pixel Processor. Switch to 0 to disable the clock only to this Pixel Processor*/ +/* +* Clock active signal for Pixel Processor. Switch to 0 to disable the cloc + * k only to this Pixel Processor +*/ #undef CRF_APB_GPU_REF_CTRL_PP0_CLKACT_DEFVAL #undef CRF_APB_GPU_REF_CTRL_PP0_CLKACT_SHIFT #undef CRF_APB_GPU_REF_CTRL_PP0_CLKACT_MASK -#define CRF_APB_GPU_REF_CTRL_PP0_CLKACT_DEFVAL 0x00001500 -#define CRF_APB_GPU_REF_CTRL_PP0_CLKACT_SHIFT 25 -#define CRF_APB_GPU_REF_CTRL_PP0_CLKACT_MASK 0x02000000U +#define CRF_APB_GPU_REF_CTRL_PP0_CLKACT_DEFVAL 0x00001500 +#define CRF_APB_GPU_REF_CTRL_PP0_CLKACT_SHIFT 25 +#define CRF_APB_GPU_REF_CTRL_PP0_CLKACT_MASK 0x02000000U -/*Clock active signal for Pixel Processor. Switch to 0 to disable the clock only to this Pixel Processor*/ +/* +* Clock active signal for Pixel Processor. Switch to 0 to disable the cloc + * k only to this Pixel Processor +*/ #undef CRF_APB_GPU_REF_CTRL_PP1_CLKACT_DEFVAL #undef CRF_APB_GPU_REF_CTRL_PP1_CLKACT_SHIFT #undef CRF_APB_GPU_REF_CTRL_PP1_CLKACT_MASK -#define CRF_APB_GPU_REF_CTRL_PP1_CLKACT_DEFVAL 0x00001500 -#define CRF_APB_GPU_REF_CTRL_PP1_CLKACT_SHIFT 26 -#define CRF_APB_GPU_REF_CTRL_PP1_CLKACT_MASK 0x04000000U +#define CRF_APB_GPU_REF_CTRL_PP1_CLKACT_DEFVAL 0x00001500 +#define CRF_APB_GPU_REF_CTRL_PP1_CLKACT_SHIFT 26 +#define CRF_APB_GPU_REF_CTRL_PP1_CLKACT_MASK 0x04000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRF_APB_GDMA_REF_CTRL_DIVISOR0_DEFVAL #undef CRF_APB_GDMA_REF_CTRL_DIVISOR0_SHIFT #undef CRF_APB_GDMA_REF_CTRL_DIVISOR0_MASK -#define CRF_APB_GDMA_REF_CTRL_DIVISOR0_DEFVAL 0x01000500 -#define CRF_APB_GDMA_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRF_APB_GDMA_REF_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRF_APB_GDMA_REF_CTRL_DIVISOR0_DEFVAL 0x01000500 +#define CRF_APB_GDMA_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_GDMA_REF_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - lock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled aft + * er 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRF_APB_GDMA_REF_CTRL_SRCSEL_DEFVAL #undef CRF_APB_GDMA_REF_CTRL_SRCSEL_SHIFT #undef CRF_APB_GDMA_REF_CTRL_SRCSEL_MASK -#define CRF_APB_GDMA_REF_CTRL_SRCSEL_DEFVAL 0x01000500 -#define CRF_APB_GDMA_REF_CTRL_SRCSEL_SHIFT 0 -#define CRF_APB_GDMA_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRF_APB_GDMA_REF_CTRL_SRCSEL_DEFVAL 0x01000500 +#define CRF_APB_GDMA_REF_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_GDMA_REF_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRF_APB_GDMA_REF_CTRL_CLKACT_DEFVAL #undef CRF_APB_GDMA_REF_CTRL_CLKACT_SHIFT #undef CRF_APB_GDMA_REF_CTRL_CLKACT_MASK -#define CRF_APB_GDMA_REF_CTRL_CLKACT_DEFVAL 0x01000500 -#define CRF_APB_GDMA_REF_CTRL_CLKACT_SHIFT 24 -#define CRF_APB_GDMA_REF_CTRL_CLKACT_MASK 0x01000000U +#define CRF_APB_GDMA_REF_CTRL_CLKACT_DEFVAL 0x01000500 +#define CRF_APB_GDMA_REF_CTRL_CLKACT_SHIFT 24 +#define CRF_APB_GDMA_REF_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRF_APB_DPDMA_REF_CTRL_DIVISOR0_DEFVAL #undef CRF_APB_DPDMA_REF_CTRL_DIVISOR0_SHIFT #undef CRF_APB_DPDMA_REF_CTRL_DIVISOR0_MASK -#define CRF_APB_DPDMA_REF_CTRL_DIVISOR0_DEFVAL 0x01000500 -#define CRF_APB_DPDMA_REF_CTRL_DIVISOR0_SHIFT 8 -#define CRF_APB_DPDMA_REF_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRF_APB_DPDMA_REF_CTRL_DIVISOR0_DEFVAL 0x01000500 +#define CRF_APB_DPDMA_REF_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_DPDMA_REF_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - lock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled aft + * er 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRF_APB_DPDMA_REF_CTRL_SRCSEL_DEFVAL #undef CRF_APB_DPDMA_REF_CTRL_SRCSEL_SHIFT #undef CRF_APB_DPDMA_REF_CTRL_SRCSEL_MASK -#define CRF_APB_DPDMA_REF_CTRL_SRCSEL_DEFVAL 0x01000500 -#define CRF_APB_DPDMA_REF_CTRL_SRCSEL_SHIFT 0 -#define CRF_APB_DPDMA_REF_CTRL_SRCSEL_MASK 0x00000007U +#define CRF_APB_DPDMA_REF_CTRL_SRCSEL_DEFVAL 0x01000500 +#define CRF_APB_DPDMA_REF_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_DPDMA_REF_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRF_APB_DPDMA_REF_CTRL_CLKACT_DEFVAL #undef CRF_APB_DPDMA_REF_CTRL_CLKACT_SHIFT #undef CRF_APB_DPDMA_REF_CTRL_CLKACT_MASK -#define CRF_APB_DPDMA_REF_CTRL_CLKACT_DEFVAL 0x01000500 -#define CRF_APB_DPDMA_REF_CTRL_CLKACT_SHIFT 24 -#define CRF_APB_DPDMA_REF_CTRL_CLKACT_MASK 0x01000000U +#define CRF_APB_DPDMA_REF_CTRL_CLKACT_DEFVAL 0x01000500 +#define CRF_APB_DPDMA_REF_CTRL_CLKACT_SHIFT 24 +#define CRF_APB_DPDMA_REF_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_DEFVAL #undef CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_SHIFT #undef CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_MASK -#define CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_DEFVAL 0x01000400 -#define CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_SHIFT 8 -#define CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_DEFVAL 0x01000400 +#define CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new - lock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled aft + * er 4 cycles of the old clock and 4 cycles of the new clock. This is not + * usually an issue, but designers must be aware.) +*/ #undef CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_DEFVAL #undef CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_SHIFT #undef CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_MASK -#define CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_DEFVAL 0x01000400 -#define CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_SHIFT 0 -#define CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_MASK 0x00000007U +#define CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_DEFVAL 0x01000400 +#define CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRF_APB_TOPSW_MAIN_CTRL_CLKACT_DEFVAL #undef CRF_APB_TOPSW_MAIN_CTRL_CLKACT_SHIFT #undef CRF_APB_TOPSW_MAIN_CTRL_CLKACT_MASK -#define CRF_APB_TOPSW_MAIN_CTRL_CLKACT_DEFVAL 0x01000400 -#define CRF_APB_TOPSW_MAIN_CTRL_CLKACT_SHIFT 24 -#define CRF_APB_TOPSW_MAIN_CTRL_CLKACT_MASK 0x01000000U +#define CRF_APB_TOPSW_MAIN_CTRL_CLKACT_DEFVAL 0x01000400 +#define CRF_APB_TOPSW_MAIN_CTRL_CLKACT_SHIFT 24 +#define CRF_APB_TOPSW_MAIN_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_DEFVAL #undef CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_SHIFT #undef CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_MASK -#define CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_DEFVAL 0x01000800 -#define CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_SHIFT 8 -#define CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_DEFVAL 0x01000800 +#define CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = APLL; 010 = IOPLL_TO_FPD; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of - he new clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = APLL; 010 = IOPLL_TO_FPD; 011 = DPLL; (This signal may only be tog + * gled after 4 cycles of the old clock and 4 cycles of the new clock. This + * is not usually an issue, but designers must be aware.) +*/ #undef CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_DEFVAL #undef CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_SHIFT #undef CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_MASK -#define CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_DEFVAL 0x01000800 -#define CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_SHIFT 0 -#define CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_MASK 0x00000007U +#define CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_DEFVAL 0x01000800 +#define CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_MASK 0x00000007U -/*Clock active signal. Switch to 0 to disable the clock*/ +/* +* Clock active signal. Switch to 0 to disable the clock +*/ #undef CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_DEFVAL #undef CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_SHIFT #undef CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_MASK -#define CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_DEFVAL 0x01000800 -#define CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_SHIFT 24 -#define CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_MASK 0x01000000U +#define CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_DEFVAL 0x01000800 +#define CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_SHIFT 24 +#define CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_MASK 0x01000000U -/*6 bit divider*/ +/* +* 6 bit divider +*/ #undef CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_DEFVAL #undef CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_SHIFT #undef CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_MASK -#define CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_DEFVAL 0x00000A00 -#define CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_SHIFT 8 -#define CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_MASK 0x00003F00U +#define CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_DEFVAL 0x00000A00 +#define CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_SHIFT 8 +#define CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_MASK 0x00003F00U -/*000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of - he new clock. This is not usually an issue, but designers must be aware.)*/ +/* +* 000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be tog + * gled after 4 cycles of the old clock and 4 cycles of the new clock. This + * is not usually an issue, but designers must be aware.) +*/ #undef CRF_APB_DBG_TSTMP_CTRL_SRCSEL_DEFVAL #undef CRF_APB_DBG_TSTMP_CTRL_SRCSEL_SHIFT #undef CRF_APB_DBG_TSTMP_CTRL_SRCSEL_MASK -#define CRF_APB_DBG_TSTMP_CTRL_SRCSEL_DEFVAL 0x00000A00 -#define CRF_APB_DBG_TSTMP_CTRL_SRCSEL_SHIFT 0 -#define CRF_APB_DBG_TSTMP_CTRL_SRCSEL_MASK 0x00000007U +#define CRF_APB_DBG_TSTMP_CTRL_SRCSEL_DEFVAL 0x00000A00 +#define CRF_APB_DBG_TSTMP_CTRL_SRCSEL_SHIFT 0 +#define CRF_APB_DBG_TSTMP_CTRL_SRCSEL_MASK 0x00000007U -/*00" = Select the APB switch clock for the APB interface of TTC0'01" = Select the PLL ref clock for the APB interface of TTC0' - 0" = Select the R5 clock for the APB interface of TTC0*/ +/* +* 00" = Select the APB switch clock for the APB interface of TTC0'01" = Se + * lect the PLL ref clock for the APB interface of TTC0'10" = Select the R5 + * clock for the APB interface of TTC0 +*/ #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_DEFVAL #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_SHIFT #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_MASK -#define IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_SHIFT 0 -#define IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_MASK 0x00000003U +#define IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_SHIFT 0 +#define IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_MASK 0x00000003U -/*00" = Select the APB switch clock for the APB interface of TTC1'01" = Select the PLL ref clock for the APB interface of TTC1' - 0" = Select the R5 clock for the APB interface of TTC1*/ +/* +* 00" = Select the APB switch clock for the APB interface of TTC1'01" = Se + * lect the PLL ref clock for the APB interface of TTC1'10" = Select the R5 + * clock for the APB interface of TTC1 +*/ #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_DEFVAL #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_SHIFT #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_MASK -#define IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_SHIFT 2 -#define IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_MASK 0x0000000CU +#define IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_SHIFT 2 +#define IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_MASK 0x0000000CU -/*00" = Select the APB switch clock for the APB interface of TTC2'01" = Select the PLL ref clock for the APB interface of TTC2' - 0" = Select the R5 clock for the APB interface of TTC2*/ +/* +* 00" = Select the APB switch clock for the APB interface of TTC2'01" = Se + * lect the PLL ref clock for the APB interface of TTC2'10" = Select the R5 + * clock for the APB interface of TTC2 +*/ #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_DEFVAL #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_SHIFT #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_MASK -#define IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_SHIFT 4 -#define IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_MASK 0x00000030U +#define IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_SHIFT 4 +#define IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_MASK 0x00000030U -/*00" = Select the APB switch clock for the APB interface of TTC3'01" = Select the PLL ref clock for the APB interface of TTC3' - 0" = Select the R5 clock for the APB interface of TTC3*/ +/* +* 00" = Select the APB switch clock for the APB interface of TTC3'01" = Se + * lect the PLL ref clock for the APB interface of TTC3'10" = Select the R5 + * clock for the APB interface of TTC3 +*/ #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_DEFVAL #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_SHIFT #undef IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_MASK -#define IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_SHIFT 6 -#define IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_MASK 0x000000C0U +#define IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_SHIFT 6 +#define IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_MASK 0x000000C0U -/*System watchdog timer clock source selection: 0: Internal APB clock 1: External (PL clock via EMIO or Pinout clock via MIO)*/ +/* +* System watchdog timer clock source selection: 0: Internal APB clock 1: E + * xternal (PL clock via EMIO or Pinout clock via MIO) +*/ #undef FPD_SLCR_WDT_CLK_SEL_SELECT_DEFVAL #undef FPD_SLCR_WDT_CLK_SEL_SELECT_SHIFT #undef FPD_SLCR_WDT_CLK_SEL_SELECT_MASK -#define FPD_SLCR_WDT_CLK_SEL_SELECT_DEFVAL 0x00000000 -#define FPD_SLCR_WDT_CLK_SEL_SELECT_SHIFT 0 -#define FPD_SLCR_WDT_CLK_SEL_SELECT_MASK 0x00000001U +#define FPD_SLCR_WDT_CLK_SEL_SELECT_DEFVAL 0x00000000 +#define FPD_SLCR_WDT_CLK_SEL_SELECT_SHIFT 0 +#define FPD_SLCR_WDT_CLK_SEL_SELECT_MASK 0x00000001U -/*System watchdog timer clock source selection: 0: internal clock APB clock 1: external clock from PL via EMIO, or from pinout - ia MIO*/ +/* +* System watchdog timer clock source selection: 0: internal clock APB cloc + * k 1: external clock from PL via EMIO, or from pinout via MIO +*/ #undef IOU_SLCR_WDT_CLK_SEL_SELECT_DEFVAL #undef IOU_SLCR_WDT_CLK_SEL_SELECT_SHIFT #undef IOU_SLCR_WDT_CLK_SEL_SELECT_MASK -#define IOU_SLCR_WDT_CLK_SEL_SELECT_DEFVAL 0x00000000 -#define IOU_SLCR_WDT_CLK_SEL_SELECT_SHIFT 0 -#define IOU_SLCR_WDT_CLK_SEL_SELECT_MASK 0x00000001U +#define IOU_SLCR_WDT_CLK_SEL_SELECT_DEFVAL 0x00000000 +#define IOU_SLCR_WDT_CLK_SEL_SELECT_SHIFT 0 +#define IOU_SLCR_WDT_CLK_SEL_SELECT_MASK 0x00000001U -/*System watchdog timer clock source selection: 0: internal clock APB clock 1: external clock pss_ref_clk*/ +/* +* System watchdog timer clock source selection: 0: internal clock APB cloc + * k 1: external clock pss_ref_clk +*/ #undef LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_DEFVAL #undef LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_SHIFT #undef LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_MASK -#define LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_DEFVAL 0x00000000 -#define LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_SHIFT 0 -#define LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_MASK 0x00000001U +#define LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_DEFVAL 0x00000000 +#define LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_SHIFT 0 +#define LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_MASK 0x00000001U #undef CRF_APB_RST_DDR_SS_OFFSET #define CRF_APB_RST_DDR_SS_OFFSET 0XFD1A0108 #undef DDRC_MSTR_OFFSET @@ -2066,6 +2368,8 @@ #define DDRC_PWRTMG_OFFSET 0XFD070034 #undef DDRC_RFSHCTL0_OFFSET #define DDRC_RFSHCTL0_OFFSET 0XFD070050 +#undef DDRC_RFSHCTL1_OFFSET +#define DDRC_RFSHCTL1_OFFSET 0XFD070054 #undef DDRC_RFSHCTL3_OFFSET #define DDRC_RFSHCTL3_OFFSET 0XFD070060 #undef DDRC_RFSHTMG_OFFSET @@ -2134,6 +2438,8 @@ #define DDRC_DFILPCFG0_OFFSET 0XFD070198 #undef DDRC_DFILPCFG1_OFFSET #define DDRC_DFILPCFG1_OFFSET 0XFD07019C +#undef DDRC_DFIUPD0_OFFSET +#define DDRC_DFIUPD0_OFFSET 0XFD0701A0 #undef DDRC_DFIUPD1_OFFSET #define DDRC_DFIUPD1_OFFSET 0XFD0701A4 #undef DDRC_DFIMISC_OFFSET @@ -2176,6 +2482,16 @@ #define DDRC_PERFLPR1_OFFSET 0XFD070264 #undef DDRC_PERFWR1_OFFSET #define DDRC_PERFWR1_OFFSET 0XFD07026C +#undef DDRC_DQMAP0_OFFSET +#define DDRC_DQMAP0_OFFSET 0XFD070280 +#undef DDRC_DQMAP1_OFFSET +#define DDRC_DQMAP1_OFFSET 0XFD070284 +#undef DDRC_DQMAP2_OFFSET +#define DDRC_DQMAP2_OFFSET 0XFD070288 +#undef DDRC_DQMAP3_OFFSET +#define DDRC_DQMAP3_OFFSET 0XFD07028C +#undef DDRC_DQMAP4_OFFSET +#define DDRC_DQMAP4_OFFSET 0XFD070290 #undef DDRC_DQMAP5_OFFSET #define DDRC_DQMAP5_OFFSET 0XFD070294 #undef DDRC_DBG0_OFFSET @@ -2282,8 +2598,12 @@ #define DDR_PHY_PTR0_OFFSET 0XFD080040 #undef DDR_PHY_PTR1_OFFSET #define DDR_PHY_PTR1_OFFSET 0XFD080044 +#undef DDR_PHY_PLLCR0_OFFSET +#define DDR_PHY_PLLCR0_OFFSET 0XFD080068 #undef DDR_PHY_DSGCR_OFFSET #define DDR_PHY_DSGCR_OFFSET 0XFD080090 +#undef DDR_PHY_GPR0_OFFSET +#define DDR_PHY_GPR0_OFFSET 0XFD0800C0 #undef DDR_PHY_DCR_OFFSET #define DDR_PHY_DCR_OFFSET 0XFD080100 #undef DDR_PHY_DTPR0_OFFSET @@ -2338,6 +2658,8 @@ #define DDR_PHY_DTCR1_OFFSET 0XFD080204 #undef DDR_PHY_CATR0_OFFSET #define DDR_PHY_CATR0_OFFSET 0XFD080240 +#undef DDR_PHY_DQSDR0_OFFSET +#define DDR_PHY_DQSDR0_OFFSET 0XFD080250 #undef DDR_PHY_BISTLSR_OFFSET #define DDR_PHY_BISTLSR_OFFSET 0XFD080414 #undef DDR_PHY_RIOCR5_OFFSET @@ -2386,10 +2708,6 @@ #define DDR_PHY_DX0GCR5_OFFSET 0XFD080714 #undef DDR_PHY_DX0GCR6_OFFSET #define DDR_PHY_DX0GCR6_OFFSET 0XFD080718 -#undef DDR_PHY_DX0LCDLR2_OFFSET -#define DDR_PHY_DX0LCDLR2_OFFSET 0XFD080788 -#undef DDR_PHY_DX0GTR0_OFFSET -#define DDR_PHY_DX0GTR0_OFFSET 0XFD0807C0 #undef DDR_PHY_DX1GCR0_OFFSET #define DDR_PHY_DX1GCR0_OFFSET 0XFD080800 #undef DDR_PHY_DX1GCR4_OFFSET @@ -2398,10 +2716,6 @@ #define DDR_PHY_DX1GCR5_OFFSET 0XFD080814 #undef DDR_PHY_DX1GCR6_OFFSET #define DDR_PHY_DX1GCR6_OFFSET 0XFD080818 -#undef DDR_PHY_DX1LCDLR2_OFFSET -#define DDR_PHY_DX1LCDLR2_OFFSET 0XFD080888 -#undef DDR_PHY_DX1GTR0_OFFSET -#define DDR_PHY_DX1GTR0_OFFSET 0XFD0808C0 #undef DDR_PHY_DX2GCR0_OFFSET #define DDR_PHY_DX2GCR0_OFFSET 0XFD080900 #undef DDR_PHY_DX2GCR1_OFFSET @@ -2412,10 +2726,6 @@ #define DDR_PHY_DX2GCR5_OFFSET 0XFD080914 #undef DDR_PHY_DX2GCR6_OFFSET #define DDR_PHY_DX2GCR6_OFFSET 0XFD080918 -#undef DDR_PHY_DX2LCDLR2_OFFSET -#define DDR_PHY_DX2LCDLR2_OFFSET 0XFD080988 -#undef DDR_PHY_DX2GTR0_OFFSET -#define DDR_PHY_DX2GTR0_OFFSET 0XFD0809C0 #undef DDR_PHY_DX3GCR0_OFFSET #define DDR_PHY_DX3GCR0_OFFSET 0XFD080A00 #undef DDR_PHY_DX3GCR1_OFFSET @@ -2426,10 +2736,6 @@ #define DDR_PHY_DX3GCR5_OFFSET 0XFD080A14 #undef DDR_PHY_DX3GCR6_OFFSET #define DDR_PHY_DX3GCR6_OFFSET 0XFD080A18 -#undef DDR_PHY_DX3LCDLR2_OFFSET -#define DDR_PHY_DX3LCDLR2_OFFSET 0XFD080A88 -#undef DDR_PHY_DX3GTR0_OFFSET -#define DDR_PHY_DX3GTR0_OFFSET 0XFD080AC0 #undef DDR_PHY_DX4GCR0_OFFSET #define DDR_PHY_DX4GCR0_OFFSET 0XFD080B00 #undef DDR_PHY_DX4GCR1_OFFSET @@ -2440,10 +2746,6 @@ #define DDR_PHY_DX4GCR5_OFFSET 0XFD080B14 #undef DDR_PHY_DX4GCR6_OFFSET #define DDR_PHY_DX4GCR6_OFFSET 0XFD080B18 -#undef DDR_PHY_DX4LCDLR2_OFFSET -#define DDR_PHY_DX4LCDLR2_OFFSET 0XFD080B88 -#undef DDR_PHY_DX4GTR0_OFFSET -#define DDR_PHY_DX4GTR0_OFFSET 0XFD080BC0 #undef DDR_PHY_DX5GCR0_OFFSET #define DDR_PHY_DX5GCR0_OFFSET 0XFD080C00 #undef DDR_PHY_DX5GCR1_OFFSET @@ -2454,10 +2756,6 @@ #define DDR_PHY_DX5GCR5_OFFSET 0XFD080C14 #undef DDR_PHY_DX5GCR6_OFFSET #define DDR_PHY_DX5GCR6_OFFSET 0XFD080C18 -#undef DDR_PHY_DX5LCDLR2_OFFSET -#define DDR_PHY_DX5LCDLR2_OFFSET 0XFD080C88 -#undef DDR_PHY_DX5GTR0_OFFSET -#define DDR_PHY_DX5GTR0_OFFSET 0XFD080CC0 #undef DDR_PHY_DX6GCR0_OFFSET #define DDR_PHY_DX6GCR0_OFFSET 0XFD080D00 #undef DDR_PHY_DX6GCR1_OFFSET @@ -2468,10 +2766,6 @@ #define DDR_PHY_DX6GCR5_OFFSET 0XFD080D14 #undef DDR_PHY_DX6GCR6_OFFSET #define DDR_PHY_DX6GCR6_OFFSET 0XFD080D18 -#undef DDR_PHY_DX6LCDLR2_OFFSET -#define DDR_PHY_DX6LCDLR2_OFFSET 0XFD080D88 -#undef DDR_PHY_DX6GTR0_OFFSET -#define DDR_PHY_DX6GTR0_OFFSET 0XFD080DC0 #undef DDR_PHY_DX7GCR0_OFFSET #define DDR_PHY_DX7GCR0_OFFSET 0XFD080E00 #undef DDR_PHY_DX7GCR1_OFFSET @@ -2482,10 +2776,6 @@ #define DDR_PHY_DX7GCR5_OFFSET 0XFD080E14 #undef DDR_PHY_DX7GCR6_OFFSET #define DDR_PHY_DX7GCR6_OFFSET 0XFD080E18 -#undef DDR_PHY_DX7LCDLR2_OFFSET -#define DDR_PHY_DX7LCDLR2_OFFSET 0XFD080E88 -#undef DDR_PHY_DX7GTR0_OFFSET -#define DDR_PHY_DX7GTR0_OFFSET 0XFD080EC0 #undef DDR_PHY_DX8GCR0_OFFSET #define DDR_PHY_DX8GCR0_OFFSET 0XFD080F00 #undef DDR_PHY_DX8GCR1_OFFSET @@ -2496,12 +2786,10 @@ #define DDR_PHY_DX8GCR5_OFFSET 0XFD080F14 #undef DDR_PHY_DX8GCR6_OFFSET #define DDR_PHY_DX8GCR6_OFFSET 0XFD080F18 -#undef DDR_PHY_DX8LCDLR2_OFFSET -#define DDR_PHY_DX8LCDLR2_OFFSET 0XFD080F88 -#undef DDR_PHY_DX8GTR0_OFFSET -#define DDR_PHY_DX8GTR0_OFFSET 0XFD080FC0 #undef DDR_PHY_DX8SL0OSC_OFFSET #define DDR_PHY_DX8SL0OSC_OFFSET 0XFD081400 +#undef DDR_PHY_DX8SL0PLLCR0_OFFSET +#define DDR_PHY_DX8SL0PLLCR0_OFFSET 0XFD081404 #undef DDR_PHY_DX8SL0DQSCTL_OFFSET #define DDR_PHY_DX8SL0DQSCTL_OFFSET 0XFD08141C #undef DDR_PHY_DX8SL0DXCTL2_OFFSET @@ -2510,6 +2798,8 @@ #define DDR_PHY_DX8SL0IOCR_OFFSET 0XFD081430 #undef DDR_PHY_DX8SL1OSC_OFFSET #define DDR_PHY_DX8SL1OSC_OFFSET 0XFD081440 +#undef DDR_PHY_DX8SL1PLLCR0_OFFSET +#define DDR_PHY_DX8SL1PLLCR0_OFFSET 0XFD081444 #undef DDR_PHY_DX8SL1DQSCTL_OFFSET #define DDR_PHY_DX8SL1DQSCTL_OFFSET 0XFD08145C #undef DDR_PHY_DX8SL1DXCTL2_OFFSET @@ -2518,6 +2808,8 @@ #define DDR_PHY_DX8SL1IOCR_OFFSET 0XFD081470 #undef DDR_PHY_DX8SL2OSC_OFFSET #define DDR_PHY_DX8SL2OSC_OFFSET 0XFD081480 +#undef DDR_PHY_DX8SL2PLLCR0_OFFSET +#define DDR_PHY_DX8SL2PLLCR0_OFFSET 0XFD081484 #undef DDR_PHY_DX8SL2DQSCTL_OFFSET #define DDR_PHY_DX8SL2DQSCTL_OFFSET 0XFD08149C #undef DDR_PHY_DX8SL2DXCTL2_OFFSET @@ -2526,6 +2818,8 @@ #define DDR_PHY_DX8SL2IOCR_OFFSET 0XFD0814B0 #undef DDR_PHY_DX8SL3OSC_OFFSET #define DDR_PHY_DX8SL3OSC_OFFSET 0XFD0814C0 +#undef DDR_PHY_DX8SL3PLLCR0_OFFSET +#define DDR_PHY_DX8SL3PLLCR0_OFFSET 0XFD0814C4 #undef DDR_PHY_DX8SL3DQSCTL_OFFSET #define DDR_PHY_DX8SL3DQSCTL_OFFSET 0XFD0814DC #undef DDR_PHY_DX8SL3DXCTL2_OFFSET @@ -2534,14391 +2828,18570 @@ #define DDR_PHY_DX8SL3IOCR_OFFSET 0XFD0814F0 #undef DDR_PHY_DX8SL4OSC_OFFSET #define DDR_PHY_DX8SL4OSC_OFFSET 0XFD081500 +#undef DDR_PHY_DX8SL4PLLCR0_OFFSET +#define DDR_PHY_DX8SL4PLLCR0_OFFSET 0XFD081504 #undef DDR_PHY_DX8SL4DQSCTL_OFFSET #define DDR_PHY_DX8SL4DQSCTL_OFFSET 0XFD08151C #undef DDR_PHY_DX8SL4DXCTL2_OFFSET #define DDR_PHY_DX8SL4DXCTL2_OFFSET 0XFD08152C #undef DDR_PHY_DX8SL4IOCR_OFFSET #define DDR_PHY_DX8SL4IOCR_OFFSET 0XFD081530 +#undef DDR_PHY_DX8SLBPLLCR0_OFFSET +#define DDR_PHY_DX8SLBPLLCR0_OFFSET 0XFD0817C4 #undef DDR_PHY_DX8SLBDQSCTL_OFFSET #define DDR_PHY_DX8SLBDQSCTL_OFFSET 0XFD0817DC -#undef DDR_PHY_PIR_OFFSET -#define DDR_PHY_PIR_OFFSET 0XFD080004 -/*DDR block level reset inside of the DDR Sub System*/ +/* +* DDR block level reset inside of the DDR Sub System +*/ #undef CRF_APB_RST_DDR_SS_DDR_RESET_DEFVAL #undef CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT #undef CRF_APB_RST_DDR_SS_DDR_RESET_MASK -#define CRF_APB_RST_DDR_SS_DDR_RESET_DEFVAL 0x0000000F -#define CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT 3 -#define CRF_APB_RST_DDR_SS_DDR_RESET_MASK 0x00000008U +#define CRF_APB_RST_DDR_SS_DDR_RESET_DEFVAL 0x0000000F +#define CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT 3 +#define CRF_APB_RST_DDR_SS_DDR_RESET_MASK 0x00000008U -/*Indicates the configuration of the device used in the system. - 00 - x4 device - 01 - x8 device - 10 - x16 device - 11 - x32 - evice*/ +/* +* Indicates the configuration of the device used in the system. - 00 - x4 + * device - 01 - x8 device - 10 - x16 device - 11 - x32 device +*/ #undef DDRC_MSTR_DEVICE_CONFIG_DEFVAL #undef DDRC_MSTR_DEVICE_CONFIG_SHIFT #undef DDRC_MSTR_DEVICE_CONFIG_MASK -#define DDRC_MSTR_DEVICE_CONFIG_DEFVAL 0x03040001 -#define DDRC_MSTR_DEVICE_CONFIG_SHIFT 30 -#define DDRC_MSTR_DEVICE_CONFIG_MASK 0xC0000000U +#define DDRC_MSTR_DEVICE_CONFIG_DEFVAL 0x03040001 +#define DDRC_MSTR_DEVICE_CONFIG_SHIFT 30 +#define DDRC_MSTR_DEVICE_CONFIG_MASK 0xC0000000U -/*Choose which registers are used. - 0 - Original registers - 1 - Shadow registers*/ +/* +* Choose which registers are used. - 0 - Original registers - 1 - Shadow r + * egisters +*/ #undef DDRC_MSTR_FREQUENCY_MODE_DEFVAL #undef DDRC_MSTR_FREQUENCY_MODE_SHIFT #undef DDRC_MSTR_FREQUENCY_MODE_MASK -#define DDRC_MSTR_FREQUENCY_MODE_DEFVAL 0x03040001 -#define DDRC_MSTR_FREQUENCY_MODE_SHIFT 29 -#define DDRC_MSTR_FREQUENCY_MODE_MASK 0x20000000U +#define DDRC_MSTR_FREQUENCY_MODE_DEFVAL 0x03040001 +#define DDRC_MSTR_FREQUENCY_MODE_SHIFT 29 +#define DDRC_MSTR_FREQUENCY_MODE_MASK 0x20000000U -/*Only present for multi-rank configurations. Each bit represents one rank. For two-rank configurations, only bits[25:24] are p - esent. - 1 - populated - 0 - unpopulated LSB is the lowest rank number. For 2 ranks following combinations are legal: - 01 - - ne rank - 11 - Two ranks - Others - Reserved. For 4 ranks following combinations are legal: - 0001 - One rank - 0011 - Two ra - ks - 1111 - Four ranks*/ +/* +* Only present for multi-rank configurations. Each bit represents one rank + * . For two-rank configurations, only bits[25:24] are present. - 1 - popul + * ated - 0 - unpopulated LSB is the lowest rank number. For 2 ranks follow + * ing combinations are legal: - 01 - One rank - 11 - Two ranks - Others - + * Reserved. For 4 ranks following combinations are legal: - 0001 - One ran + * k - 0011 - Two ranks - 1111 - Four ranks +*/ #undef DDRC_MSTR_ACTIVE_RANKS_DEFVAL #undef DDRC_MSTR_ACTIVE_RANKS_SHIFT #undef DDRC_MSTR_ACTIVE_RANKS_MASK -#define DDRC_MSTR_ACTIVE_RANKS_DEFVAL 0x03040001 -#define DDRC_MSTR_ACTIVE_RANKS_SHIFT 24 -#define DDRC_MSTR_ACTIVE_RANKS_MASK 0x03000000U +#define DDRC_MSTR_ACTIVE_RANKS_DEFVAL 0x03040001 +#define DDRC_MSTR_ACTIVE_RANKS_SHIFT 24 +#define DDRC_MSTR_ACTIVE_RANKS_MASK 0x03000000U -/*SDRAM burst length used: - 0001 - Burst length of 2 (only supported for mDDR) - 0010 - Burst length of 4 - 0100 - Burst lengt - of 8 - 1000 - Burst length of 16 (only supported for mDDR, LPDDR2, and LPDDR4) All other values are reserved. This controls - he burst size used to access the SDRAM. This must match the burst length mode register setting in the SDRAM. (For BC4/8 on-th - -fly mode of DDR3 and DDR4, set this field to 0x0100) Burst length of 2 is not supported with AXI ports when MEMC_BURST_LENGT - is 8. Burst length of 2 is only supported with MEMC_FREQ_RATIO = 1*/ +/* +* SDRAM burst length used: - 0001 - Burst length of 2 (only supported for + * mDDR) - 0010 - Burst length of 4 - 0100 - Burst length of 8 - 1000 - Bur + * st length of 16 (only supported for mDDR, LPDDR2, and LPDDR4) All other + * values are reserved. This controls the burst size used to access the SDR + * AM. This must match the burst length mode register setting in the SDRAM. + * (For BC4/8 on-the-fly mode of DDR3 and DDR4, set this field to 0x0100) + * Burst length of 2 is not supported with AXI ports when MEMC_BURST_LENGTH + * is 8. Burst length of 2 is only supported with MEMC_FREQ_RATIO = 1 +*/ #undef DDRC_MSTR_BURST_RDWR_DEFVAL #undef DDRC_MSTR_BURST_RDWR_SHIFT #undef DDRC_MSTR_BURST_RDWR_MASK -#define DDRC_MSTR_BURST_RDWR_DEFVAL 0x03040001 -#define DDRC_MSTR_BURST_RDWR_SHIFT 16 -#define DDRC_MSTR_BURST_RDWR_MASK 0x000F0000U +#define DDRC_MSTR_BURST_RDWR_DEFVAL 0x03040001 +#define DDRC_MSTR_BURST_RDWR_SHIFT 16 +#define DDRC_MSTR_BURST_RDWR_MASK 0x000F0000U -/*Set to 1 when the uMCTL2 and DRAM has to be put in DLL-off mode for low frequency operation. Set to 0 to put uMCTL2 and DRAM - n DLL-on mode for normal frequency operation. If DDR4 CRC/parity retry is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), d - l_off_mode is not supported, and this bit must be set to '0'.*/ +/* +* Set to 1 when the uMCTL2 and DRAM has to be put in DLL-off mode for low + * frequency operation. Set to 0 to put uMCTL2 and DRAM in DLL-on mode for + * normal frequency operation. If DDR4 CRC/parity retry is enabled (CRCPARC + * TL1.crc_parity_retry_enable = 1), dll_off_mode is not supported, and thi + * s bit must be set to '0'. +*/ #undef DDRC_MSTR_DLL_OFF_MODE_DEFVAL #undef DDRC_MSTR_DLL_OFF_MODE_SHIFT #undef DDRC_MSTR_DLL_OFF_MODE_MASK -#define DDRC_MSTR_DLL_OFF_MODE_DEFVAL 0x03040001 -#define DDRC_MSTR_DLL_OFF_MODE_SHIFT 15 -#define DDRC_MSTR_DLL_OFF_MODE_MASK 0x00008000U +#define DDRC_MSTR_DLL_OFF_MODE_DEFVAL 0x03040001 +#define DDRC_MSTR_DLL_OFF_MODE_SHIFT 15 +#define DDRC_MSTR_DLL_OFF_MODE_MASK 0x00008000U -/*Selects proportion of DQ bus width that is used by the SDRAM - 00 - Full DQ bus width to SDRAM - 01 - Half DQ bus width to SD - AM - 10 - Quarter DQ bus width to SDRAM - 11 - Reserved. Note that half bus width mode is only supported when the SDRAM bus w - dth is a multiple of 16, and quarter bus width mode is only supported when the SDRAM bus width is a multiple of 32 and the co - figuration parameter MEMC_QBUS_SUPPORT is set. Bus width refers to DQ bus width (excluding any ECC width).*/ +/* +* Selects proportion of DQ bus width that is used by the SDRAM - 00 - Full + * DQ bus width to SDRAM - 01 - Half DQ bus width to SDRAM - 10 - Quarter + * DQ bus width to SDRAM - 11 - Reserved. Note that half bus width mode is + * only supported when the SDRAM bus width is a multiple of 16, and quarter + * bus width mode is only supported when the SDRAM bus width is a multiple + * of 32 and the configuration parameter MEMC_QBUS_SUPPORT is set. Bus wid + * th refers to DQ bus width (excluding any ECC width). +*/ #undef DDRC_MSTR_DATA_BUS_WIDTH_DEFVAL #undef DDRC_MSTR_DATA_BUS_WIDTH_SHIFT #undef DDRC_MSTR_DATA_BUS_WIDTH_MASK -#define DDRC_MSTR_DATA_BUS_WIDTH_DEFVAL 0x03040001 -#define DDRC_MSTR_DATA_BUS_WIDTH_SHIFT 12 -#define DDRC_MSTR_DATA_BUS_WIDTH_MASK 0x00003000U +#define DDRC_MSTR_DATA_BUS_WIDTH_DEFVAL 0x03040001 +#define DDRC_MSTR_DATA_BUS_WIDTH_SHIFT 12 +#define DDRC_MSTR_DATA_BUS_WIDTH_MASK 0x00003000U -/*1 indicates put the DRAM in geardown mode (2N) and 0 indicates put the DRAM in normal mode (1N). This register can be changed - only when the Controller is in self-refresh mode. This signal must be set the same value as MR3 bit A3. Note: Geardown mode - s not supported if the configuration parameter MEMC_CMD_RTN2IDLE is set*/ +/* +* 1 indicates put the DRAM in geardown mode (2N) and 0 indicates put the D + * RAM in normal mode (1N). This register can be changed, only when the Con + * troller is in self-refresh mode. This signal must be set the same value + * as MR3 bit A3. Note: Geardown mode is not supported if the configuration + * parameter MEMC_CMD_RTN2IDLE is set +*/ #undef DDRC_MSTR_GEARDOWN_MODE_DEFVAL #undef DDRC_MSTR_GEARDOWN_MODE_SHIFT #undef DDRC_MSTR_GEARDOWN_MODE_MASK -#define DDRC_MSTR_GEARDOWN_MODE_DEFVAL 0x03040001 -#define DDRC_MSTR_GEARDOWN_MODE_SHIFT 11 -#define DDRC_MSTR_GEARDOWN_MODE_MASK 0x00000800U +#define DDRC_MSTR_GEARDOWN_MODE_DEFVAL 0x03040001 +#define DDRC_MSTR_GEARDOWN_MODE_SHIFT 11 +#define DDRC_MSTR_GEARDOWN_MODE_MASK 0x00000800U -/*If 1, then uMCTL2 uses 2T timing. Otherwise, uses 1T timing. In 2T timing, all command signals (except chip select) are held - or 2 clocks on the SDRAM bus. Chip select is asserted on the second cycle of the command Note: 2T timing is not supported in - PDDR2/LPDDR3/LPDDR4 mode Note: 2T timing is not supported if the configuration parameter MEMC_CMD_RTN2IDLE is set Note: 2T ti - ing is not supported in DDR4 geardown mode.*/ +/* +* If 1, then uMCTL2 uses 2T timing. Otherwise, uses 1T timing. In 2T timin + * g, all command signals (except chip select) are held for 2 clocks on the + * SDRAM bus. Chip select is asserted on the second cycle of the command N + * ote: 2T timing is not supported in LPDDR2/LPDDR3/LPDDR4 mode Note: 2T ti + * ming is not supported if the configuration parameter MEMC_CMD_RTN2IDLE i + * s set Note: 2T timing is not supported in DDR4 geardown mode. +*/ #undef DDRC_MSTR_EN_2T_TIMING_MODE_DEFVAL #undef DDRC_MSTR_EN_2T_TIMING_MODE_SHIFT #undef DDRC_MSTR_EN_2T_TIMING_MODE_MASK -#define DDRC_MSTR_EN_2T_TIMING_MODE_DEFVAL 0x03040001 -#define DDRC_MSTR_EN_2T_TIMING_MODE_SHIFT 10 -#define DDRC_MSTR_EN_2T_TIMING_MODE_MASK 0x00000400U +#define DDRC_MSTR_EN_2T_TIMING_MODE_DEFVAL 0x03040001 +#define DDRC_MSTR_EN_2T_TIMING_MODE_SHIFT 10 +#define DDRC_MSTR_EN_2T_TIMING_MODE_MASK 0x00000400U -/*When set, enable burst-chop in DDR3/DDR4. Burst Chop for Reads is exercised only in HIF configurations (UMCTL2_INCL_ARB not s - t) and if in full bus width mode (MSTR.data_bus_width = 00). Burst Chop for Writes is exercised only if Partial Writes enable - (UMCTL2_PARTIAL_WR=1) and if CRC is disabled (CRCPARCTL1.crc_enable = 0). If DDR4 CRC/parity retry is enabled (CRCPARCTL1.cr - _parity_retry_enable = 1), burst chop is not supported, and this bit must be set to '0'*/ +/* +* When set, enable burst-chop in DDR3/DDR4. Burst Chop for Reads is exerci + * sed only in HIF configurations (UMCTL2_INCL_ARB not set) and if in full + * bus width mode (MSTR.data_bus_width = 00). Burst Chop for Writes is exer + * cised only if Partial Writes enabled (UMCTL2_PARTIAL_WR=1) and if CRC is + * disabled (CRCPARCTL1.crc_enable = 0). If DDR4 CRC/parity retry is enabl + * ed (CRCPARCTL1.crc_parity_retry_enable = 1), burst chop is not supported + * , and this bit must be set to '0' +*/ #undef DDRC_MSTR_BURSTCHOP_DEFVAL #undef DDRC_MSTR_BURSTCHOP_SHIFT #undef DDRC_MSTR_BURSTCHOP_MASK -#define DDRC_MSTR_BURSTCHOP_DEFVAL 0x03040001 -#define DDRC_MSTR_BURSTCHOP_SHIFT 9 -#define DDRC_MSTR_BURSTCHOP_MASK 0x00000200U +#define DDRC_MSTR_BURSTCHOP_DEFVAL 0x03040001 +#define DDRC_MSTR_BURSTCHOP_SHIFT 9 +#define DDRC_MSTR_BURSTCHOP_MASK 0x00000200U -/*Select LPDDR4 SDRAM - 1 - LPDDR4 SDRAM device in use. - 0 - non-LPDDR4 device in use Present only in designs configured to su - port LPDDR4.*/ +/* +* Select LPDDR4 SDRAM - 1 - LPDDR4 SDRAM device in use. - 0 - non-LPDDR4 d + * evice in use Present only in designs configured to support LPDDR4. +*/ #undef DDRC_MSTR_LPDDR4_DEFVAL #undef DDRC_MSTR_LPDDR4_SHIFT #undef DDRC_MSTR_LPDDR4_MASK -#define DDRC_MSTR_LPDDR4_DEFVAL 0x03040001 -#define DDRC_MSTR_LPDDR4_SHIFT 5 -#define DDRC_MSTR_LPDDR4_MASK 0x00000020U +#define DDRC_MSTR_LPDDR4_DEFVAL 0x03040001 +#define DDRC_MSTR_LPDDR4_SHIFT 5 +#define DDRC_MSTR_LPDDR4_MASK 0x00000020U -/*Select DDR4 SDRAM - 1 - DDR4 SDRAM device in use. - 0 - non-DDR4 device in use Present only in designs configured to support - DR4.*/ +/* +* Select DDR4 SDRAM - 1 - DDR4 SDRAM device in use. - 0 - non-DDR4 device + * in use Present only in designs configured to support DDR4. +*/ #undef DDRC_MSTR_DDR4_DEFVAL #undef DDRC_MSTR_DDR4_SHIFT #undef DDRC_MSTR_DDR4_MASK -#define DDRC_MSTR_DDR4_DEFVAL 0x03040001 -#define DDRC_MSTR_DDR4_SHIFT 4 -#define DDRC_MSTR_DDR4_MASK 0x00000010U +#define DDRC_MSTR_DDR4_DEFVAL 0x03040001 +#define DDRC_MSTR_DDR4_SHIFT 4 +#define DDRC_MSTR_DDR4_MASK 0x00000010U -/*Select LPDDR3 SDRAM - 1 - LPDDR3 SDRAM device in use. - 0 - non-LPDDR3 device in use Present only in designs configured to su - port LPDDR3.*/ +/* +* Select LPDDR3 SDRAM - 1 - LPDDR3 SDRAM device in use. - 0 - non-LPDDR3 d + * evice in use Present only in designs configured to support LPDDR3. +*/ #undef DDRC_MSTR_LPDDR3_DEFVAL #undef DDRC_MSTR_LPDDR3_SHIFT #undef DDRC_MSTR_LPDDR3_MASK -#define DDRC_MSTR_LPDDR3_DEFVAL 0x03040001 -#define DDRC_MSTR_LPDDR3_SHIFT 3 -#define DDRC_MSTR_LPDDR3_MASK 0x00000008U +#define DDRC_MSTR_LPDDR3_DEFVAL 0x03040001 +#define DDRC_MSTR_LPDDR3_SHIFT 3 +#define DDRC_MSTR_LPDDR3_MASK 0x00000008U -/*Select LPDDR2 SDRAM - 1 - LPDDR2 SDRAM device in use. - 0 - non-LPDDR2 device in use Present only in designs configured to su - port LPDDR2.*/ +/* +* Select LPDDR2 SDRAM - 1 - LPDDR2 SDRAM device in use. - 0 - non-LPDDR2 d + * evice in use Present only in designs configured to support LPDDR2. +*/ #undef DDRC_MSTR_LPDDR2_DEFVAL #undef DDRC_MSTR_LPDDR2_SHIFT #undef DDRC_MSTR_LPDDR2_MASK -#define DDRC_MSTR_LPDDR2_DEFVAL 0x03040001 -#define DDRC_MSTR_LPDDR2_SHIFT 2 -#define DDRC_MSTR_LPDDR2_MASK 0x00000004U +#define DDRC_MSTR_LPDDR2_DEFVAL 0x03040001 +#define DDRC_MSTR_LPDDR2_SHIFT 2 +#define DDRC_MSTR_LPDDR2_MASK 0x00000004U -/*Select DDR3 SDRAM - 1 - DDR3 SDRAM device in use - 0 - non-DDR3 SDRAM device in use Only present in designs that support DDR3 - */ +/* +* Select DDR3 SDRAM - 1 - DDR3 SDRAM device in use - 0 - non-DDR3 SDRAM de + * vice in use Only present in designs that support DDR3. +*/ #undef DDRC_MSTR_DDR3_DEFVAL #undef DDRC_MSTR_DDR3_SHIFT #undef DDRC_MSTR_DDR3_MASK -#define DDRC_MSTR_DDR3_DEFVAL 0x03040001 -#define DDRC_MSTR_DDR3_SHIFT 0 -#define DDRC_MSTR_DDR3_MASK 0x00000001U +#define DDRC_MSTR_DDR3_DEFVAL 0x03040001 +#define DDRC_MSTR_DDR3_SHIFT 0 +#define DDRC_MSTR_DDR3_MASK 0x00000001U -/*Setting this register bit to 1 triggers a mode register read or write operation. When the MR operation is complete, the uMCTL - automatically clears this bit. The other register fields of this register must be written in a separate APB transaction, bef - re setting this mr_wr bit. It is recommended NOT to set this signal if in Init, Deep power-down or MPSM operating modes.*/ +/* +* Setting this register bit to 1 triggers a mode register read or write op + * eration. When the MR operation is complete, the uMCTL2 automatically cle + * ars this bit. The other register fields of this register must be written + * in a separate APB transaction, before setting this mr_wr bit. It is rec + * ommended NOT to set this signal if in Init, Deep power-down or MPSM oper + * ating modes. +*/ #undef DDRC_MRCTRL0_MR_WR_DEFVAL #undef DDRC_MRCTRL0_MR_WR_SHIFT #undef DDRC_MRCTRL0_MR_WR_MASK -#define DDRC_MRCTRL0_MR_WR_DEFVAL 0x00000030 -#define DDRC_MRCTRL0_MR_WR_SHIFT 31 -#define DDRC_MRCTRL0_MR_WR_MASK 0x80000000U +#define DDRC_MRCTRL0_MR_WR_DEFVAL 0x00000030 +#define DDRC_MRCTRL0_MR_WR_SHIFT 31 +#define DDRC_MRCTRL0_MR_WR_MASK 0x80000000U -/*Address of the mode register that is to be written to. - 0000 - MR0 - 0001 - MR1 - 0010 - MR2 - 0011 - MR3 - 0100 - MR4 - 010 - - MR5 - 0110 - MR6 - 0111 - MR7 Don't Care for LPDDR2/LPDDR3/LPDDR4 (see MRCTRL1.mr_data for mode register addressing in LPD - R2/LPDDR3/LPDDR4) This signal is also used for writing to control words of RDIMMs. In that case, it corresponds to the bank a - dress bits sent to the RDIMM In case of DDR4, the bit[3:2] corresponds to the bank group bits. Therefore, the bit[3] as well - s the bit[2:0] must be set to an appropriate value which is considered both the Address Mirroring of UDIMMs/RDIMMs and the Ou - put Inversion of RDIMMs.*/ +/* +* Address of the mode register that is to be written to. - 0000 - MR0 - 00 + * 01 - MR1 - 0010 - MR2 - 0011 - MR3 - 0100 - MR4 - 0101 - MR5 - 0110 - MR + * 6 - 0111 - MR7 Don't Care for LPDDR2/LPDDR3/LPDDR4 (see MRCTRL1.mr_data + * for mode register addressing in LPDDR2/LPDDR3/LPDDR4) This signal is als + * o used for writing to control words of RDIMMs. In that case, it correspo + * nds to the bank address bits sent to the RDIMM In case of DDR4, the bit[ + * 3:2] corresponds to the bank group bits. Therefore, the bit[3] as well a + * s the bit[2:0] must be set to an appropriate value which is considered b + * oth the Address Mirroring of UDIMMs/RDIMMs and the Output Inversion of R + * DIMMs. +*/ #undef DDRC_MRCTRL0_MR_ADDR_DEFVAL #undef DDRC_MRCTRL0_MR_ADDR_SHIFT #undef DDRC_MRCTRL0_MR_ADDR_MASK -#define DDRC_MRCTRL0_MR_ADDR_DEFVAL 0x00000030 -#define DDRC_MRCTRL0_MR_ADDR_SHIFT 12 -#define DDRC_MRCTRL0_MR_ADDR_MASK 0x0000F000U +#define DDRC_MRCTRL0_MR_ADDR_DEFVAL 0x00000030 +#define DDRC_MRCTRL0_MR_ADDR_SHIFT 12 +#define DDRC_MRCTRL0_MR_ADDR_MASK 0x0000F000U -/*Controls which rank is accessed by MRCTRL0.mr_wr. Normally, it is desired to access all ranks, so all bits should be set to 1 - However, for multi-rank UDIMMs/RDIMMs which implement address mirroring, it may be necessary to access ranks individually. E - amples (assume uMCTL2 is configured for 4 ranks): - 0x1 - select rank 0 only - 0x2 - select rank 1 only - 0x5 - select ranks - and 2 - 0xA - select ranks 1 and 3 - 0xF - select ranks 0, 1, 2 and 3*/ +/* +* Controls which rank is accessed by MRCTRL0.mr_wr. Normally, it is desire + * d to access all ranks, so all bits should be set to 1. However, for mult + * i-rank UDIMMs/RDIMMs which implement address mirroring, it may be necess + * ary to access ranks individually. Examples (assume uMCTL2 is configured + * for 4 ranks): - 0x1 - select rank 0 only - 0x2 - select rank 1 only - 0x + * 5 - select ranks 0 and 2 - 0xA - select ranks 1 and 3 - 0xF - select ran + * ks 0, 1, 2 and 3 +*/ #undef DDRC_MRCTRL0_MR_RANK_DEFVAL #undef DDRC_MRCTRL0_MR_RANK_SHIFT #undef DDRC_MRCTRL0_MR_RANK_MASK -#define DDRC_MRCTRL0_MR_RANK_DEFVAL 0x00000030 -#define DDRC_MRCTRL0_MR_RANK_SHIFT 4 -#define DDRC_MRCTRL0_MR_RANK_MASK 0x00000030U +#define DDRC_MRCTRL0_MR_RANK_DEFVAL 0x00000030 +#define DDRC_MRCTRL0_MR_RANK_SHIFT 4 +#define DDRC_MRCTRL0_MR_RANK_MASK 0x00000030U -/*Indicates whether Software intervention is allowed via MRCTRL0/MRCTRL1 before automatic SDRAM initialization routine or not. - or DDR4, this bit can be used to initialize the DDR4 RCD (MR7) before automatic SDRAM initialization. For LPDDR4, this bit ca - be used to program additional mode registers before automatic SDRAM initialization if necessary. Note: This must be cleared - o 0 after completing Software operation. Otherwise, SDRAM initialization routine will not re-start. - 0 - Software interventi - n is not allowed - 1 - Software intervention is allowed*/ +/* +* Indicates whether Software intervention is allowed via MRCTRL0/MRCTRL1 b + * efore automatic SDRAM initialization routine or not. For DDR4, this bit + * can be used to initialize the DDR4 RCD (MR7) before automatic SDRAM init + * ialization. For LPDDR4, this bit can be used to program additional mode + * registers before automatic SDRAM initialization if necessary. Note: This + * must be cleared to 0 after completing Software operation. Otherwise, SD + * RAM initialization routine will not re-start. - 0 - Software interventio + * n is not allowed - 1 - Software intervention is allowed +*/ #undef DDRC_MRCTRL0_SW_INIT_INT_DEFVAL #undef DDRC_MRCTRL0_SW_INIT_INT_SHIFT #undef DDRC_MRCTRL0_SW_INIT_INT_MASK -#define DDRC_MRCTRL0_SW_INIT_INT_DEFVAL 0x00000030 -#define DDRC_MRCTRL0_SW_INIT_INT_SHIFT 3 -#define DDRC_MRCTRL0_SW_INIT_INT_MASK 0x00000008U +#define DDRC_MRCTRL0_SW_INIT_INT_DEFVAL 0x00000030 +#define DDRC_MRCTRL0_SW_INIT_INT_SHIFT 3 +#define DDRC_MRCTRL0_SW_INIT_INT_MASK 0x00000008U -/*Indicates whether the mode register operation is MRS in PDA mode or not - 0 - MRS - 1 - MRS in Per DRAM Addressability mode*/ +/* +* Indicates whether the mode register operation is MRS in PDA mode or not + * - 0 - MRS - 1 - MRS in Per DRAM Addressability mode +*/ #undef DDRC_MRCTRL0_PDA_EN_DEFVAL #undef DDRC_MRCTRL0_PDA_EN_SHIFT #undef DDRC_MRCTRL0_PDA_EN_MASK -#define DDRC_MRCTRL0_PDA_EN_DEFVAL 0x00000030 -#define DDRC_MRCTRL0_PDA_EN_SHIFT 2 -#define DDRC_MRCTRL0_PDA_EN_MASK 0x00000004U +#define DDRC_MRCTRL0_PDA_EN_DEFVAL 0x00000030 +#define DDRC_MRCTRL0_PDA_EN_SHIFT 2 +#define DDRC_MRCTRL0_PDA_EN_MASK 0x00000004U -/*Indicates whether the mode register operation is MRS or WR/RD for MPR (only supported for DDR4) - 0 - MRS - 1 - WR/RD for MPR*/ +/* +* Indicates whether the mode register operation is MRS or WR/RD for MPR (o + * nly supported for DDR4) - 0 - MRS - 1 - WR/RD for MPR +*/ #undef DDRC_MRCTRL0_MPR_EN_DEFVAL #undef DDRC_MRCTRL0_MPR_EN_SHIFT #undef DDRC_MRCTRL0_MPR_EN_MASK -#define DDRC_MRCTRL0_MPR_EN_DEFVAL 0x00000030 -#define DDRC_MRCTRL0_MPR_EN_SHIFT 1 -#define DDRC_MRCTRL0_MPR_EN_MASK 0x00000002U +#define DDRC_MRCTRL0_MPR_EN_DEFVAL 0x00000030 +#define DDRC_MRCTRL0_MPR_EN_SHIFT 1 +#define DDRC_MRCTRL0_MPR_EN_MASK 0x00000002U -/*Indicates whether the mode register operation is read or write. Only used for LPDDR2/LPDDR3/LPDDR4/DDR4. - 0 - Write - 1 - Re - d*/ +/* +* Indicates whether the mode register operation is read or write. Only use + * d for LPDDR2/LPDDR3/LPDDR4/DDR4. - 0 - Write - 1 - Read +*/ #undef DDRC_MRCTRL0_MR_TYPE_DEFVAL #undef DDRC_MRCTRL0_MR_TYPE_SHIFT #undef DDRC_MRCTRL0_MR_TYPE_MASK -#define DDRC_MRCTRL0_MR_TYPE_DEFVAL 0x00000030 -#define DDRC_MRCTRL0_MR_TYPE_SHIFT 0 -#define DDRC_MRCTRL0_MR_TYPE_MASK 0x00000001U +#define DDRC_MRCTRL0_MR_TYPE_DEFVAL 0x00000030 +#define DDRC_MRCTRL0_MR_TYPE_SHIFT 0 +#define DDRC_MRCTRL0_MR_TYPE_MASK 0x00000001U -/*Derate value of tRC for LPDDR4 - 0 - Derating uses +1. - 1 - Derating uses +2. - 2 - Derating uses +3. - 3 - Derating uses +4 - Present only in designs configured to support LPDDR4. The required number of cycles for derating can be determined by dividi - g 3.75ns by the core_ddrc_core_clk period, and rounding up the next integer.*/ +/* +* Derate value of tRC for LPDDR4 - 0 - Derating uses +1. - 1 - Derating us + * es +2. - 2 - Derating uses +3. - 3 - Derating uses +4. Present only in d + * esigns configured to support LPDDR4. The required number of cycles for d + * erating can be determined by dividing 3.75ns by the core_ddrc_core_clk p + * eriod, and rounding up the next integer. +*/ #undef DDRC_DERATEEN_RC_DERATE_VALUE_DEFVAL #undef DDRC_DERATEEN_RC_DERATE_VALUE_SHIFT #undef DDRC_DERATEEN_RC_DERATE_VALUE_MASK -#define DDRC_DERATEEN_RC_DERATE_VALUE_DEFVAL 0x00000000 -#define DDRC_DERATEEN_RC_DERATE_VALUE_SHIFT 8 -#define DDRC_DERATEEN_RC_DERATE_VALUE_MASK 0x00000300U +#define DDRC_DERATEEN_RC_DERATE_VALUE_DEFVAL 0x00000000 +#define DDRC_DERATEEN_RC_DERATE_VALUE_SHIFT 8 +#define DDRC_DERATEEN_RC_DERATE_VALUE_MASK 0x00000300U -/*Derate byte Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4 Indicates which byte of the MRR data is used f - r derating. The maximum valid value depends on MEMC_DRAM_TOTAL_DATA_WIDTH.*/ +/* +* Derate byte Present only in designs configured to support LPDDR2/LPDDR3/ + * LPDDR4 Indicates which byte of the MRR data is used for derating. The ma + * ximum valid value depends on MEMC_DRAM_TOTAL_DATA_WIDTH. +*/ #undef DDRC_DERATEEN_DERATE_BYTE_DEFVAL #undef DDRC_DERATEEN_DERATE_BYTE_SHIFT #undef DDRC_DERATEEN_DERATE_BYTE_MASK -#define DDRC_DERATEEN_DERATE_BYTE_DEFVAL 0x00000000 -#define DDRC_DERATEEN_DERATE_BYTE_SHIFT 4 -#define DDRC_DERATEEN_DERATE_BYTE_MASK 0x000000F0U +#define DDRC_DERATEEN_DERATE_BYTE_DEFVAL 0x00000000 +#define DDRC_DERATEEN_DERATE_BYTE_SHIFT 4 +#define DDRC_DERATEEN_DERATE_BYTE_MASK 0x000000F0U -/*Derate value - 0 - Derating uses +1. - 1 - Derating uses +2. Present only in designs configured to support LPDDR2/LPDDR3/LPDD - 4 Set to 0 for all LPDDR2 speed grades as derating value of +1.875 ns is less than a core_ddrc_core_clk period. Can be 0 or 1 - for LPDDR3/LPDDR4, depending if +1.875 ns is less than a core_ddrc_core_clk period or not.*/ +/* +* Derate value - 0 - Derating uses +1. - 1 - Derating uses +2. Present onl + * y in designs configured to support LPDDR2/LPDDR3/LPDDR4 Set to 0 for all + * LPDDR2 speed grades as derating value of +1.875 ns is less than a core_ + * ddrc_core_clk period. Can be 0 or 1 for LPDDR3/LPDDR4, depending if +1.8 + * 75 ns is less than a core_ddrc_core_clk period or not. +*/ #undef DDRC_DERATEEN_DERATE_VALUE_DEFVAL #undef DDRC_DERATEEN_DERATE_VALUE_SHIFT #undef DDRC_DERATEEN_DERATE_VALUE_MASK -#define DDRC_DERATEEN_DERATE_VALUE_DEFVAL 0x00000000 -#define DDRC_DERATEEN_DERATE_VALUE_SHIFT 1 -#define DDRC_DERATEEN_DERATE_VALUE_MASK 0x00000002U +#define DDRC_DERATEEN_DERATE_VALUE_DEFVAL 0x00000000 +#define DDRC_DERATEEN_DERATE_VALUE_SHIFT 1 +#define DDRC_DERATEEN_DERATE_VALUE_MASK 0x00000002U -/*Enables derating - 0 - Timing parameter derating is disabled - 1 - Timing parameter derating is enabled using MR4 read value. - Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4 This field must be set to '0' for non-LPDDR2/LPDDR3/LPDDR4 - mode.*/ +/* +* Enables derating - 0 - Timing parameter derating is disabled - 1 - Timin + * g parameter derating is enabled using MR4 read value. Present only in de + * signs configured to support LPDDR2/LPDDR3/LPDDR4 This field must be set + * to '0' for non-LPDDR2/LPDDR3/LPDDR4 mode. +*/ #undef DDRC_DERATEEN_DERATE_ENABLE_DEFVAL #undef DDRC_DERATEEN_DERATE_ENABLE_SHIFT #undef DDRC_DERATEEN_DERATE_ENABLE_MASK -#define DDRC_DERATEEN_DERATE_ENABLE_DEFVAL 0x00000000 -#define DDRC_DERATEEN_DERATE_ENABLE_SHIFT 0 -#define DDRC_DERATEEN_DERATE_ENABLE_MASK 0x00000001U +#define DDRC_DERATEEN_DERATE_ENABLE_DEFVAL 0x00000000 +#define DDRC_DERATEEN_DERATE_ENABLE_SHIFT 0 +#define DDRC_DERATEEN_DERATE_ENABLE_MASK 0x00000001U -/*Interval between two MR4 reads, used to derate the timing parameters. Present only in designs configured to support LPDDR2/LP - DR3/LPDDR4. This register must not be set to zero*/ +/* +* Interval between two MR4 reads, used to derate the timing parameters. Pr + * esent only in designs configured to support LPDDR2/LPDDR3/LPDDR4. This r + * egister must not be set to zero +*/ #undef DDRC_DERATEINT_MR4_READ_INTERVAL_DEFVAL #undef DDRC_DERATEINT_MR4_READ_INTERVAL_SHIFT #undef DDRC_DERATEINT_MR4_READ_INTERVAL_MASK -#define DDRC_DERATEINT_MR4_READ_INTERVAL_DEFVAL -#define DDRC_DERATEINT_MR4_READ_INTERVAL_SHIFT 0 -#define DDRC_DERATEINT_MR4_READ_INTERVAL_MASK 0xFFFFFFFFU +#define DDRC_DERATEINT_MR4_READ_INTERVAL_DEFVAL +#define DDRC_DERATEINT_MR4_READ_INTERVAL_SHIFT 0 +#define DDRC_DERATEINT_MR4_READ_INTERVAL_MASK 0xFFFFFFFFU -/*Self refresh state is an intermediate state to enter to Self refresh power down state or exit Self refresh power down state f - r LPDDR4. This register controls transition from the Self refresh state. - 1 - Prohibit transition from Self refresh state - - - Allow transition from Self refresh state*/ +/* +* Self refresh state is an intermediate state to enter to Self refresh pow + * er down state or exit Self refresh power down state for LPDDR4. This reg + * ister controls transition from the Self refresh state. - 1 - Prohibit tr + * ansition from Self refresh state - 0 - Allow transition from Self refres + * h state +*/ #undef DDRC_PWRCTL_STAY_IN_SELFREF_DEFVAL #undef DDRC_PWRCTL_STAY_IN_SELFREF_SHIFT #undef DDRC_PWRCTL_STAY_IN_SELFREF_MASK -#define DDRC_PWRCTL_STAY_IN_SELFREF_DEFVAL 0x00000000 -#define DDRC_PWRCTL_STAY_IN_SELFREF_SHIFT 6 -#define DDRC_PWRCTL_STAY_IN_SELFREF_MASK 0x00000040U +#define DDRC_PWRCTL_STAY_IN_SELFREF_DEFVAL 0x00000000 +#define DDRC_PWRCTL_STAY_IN_SELFREF_SHIFT 6 +#define DDRC_PWRCTL_STAY_IN_SELFREF_MASK 0x00000040U -/*A value of 1 to this register causes system to move to Self Refresh state immediately, as long as it is not in INIT or DPD/MP - M operating_mode. This is referred to as Software Entry/Exit to Self Refresh. - 1 - Software Entry to Self Refresh - 0 - Soft - are Exit from Self Refresh*/ +/* +* A value of 1 to this register causes system to move to Self Refresh stat + * e immediately, as long as it is not in INIT or DPD/MPSM operating_mode. + * This is referred to as Software Entry/Exit to Self Refresh. - 1 - Softwa + * re Entry to Self Refresh - 0 - Software Exit from Self Refresh +*/ #undef DDRC_PWRCTL_SELFREF_SW_DEFVAL #undef DDRC_PWRCTL_SELFREF_SW_SHIFT #undef DDRC_PWRCTL_SELFREF_SW_MASK -#define DDRC_PWRCTL_SELFREF_SW_DEFVAL 0x00000000 -#define DDRC_PWRCTL_SELFREF_SW_SHIFT 5 -#define DDRC_PWRCTL_SELFREF_SW_MASK 0x00000020U +#define DDRC_PWRCTL_SELFREF_SW_DEFVAL 0x00000000 +#define DDRC_PWRCTL_SELFREF_SW_SHIFT 5 +#define DDRC_PWRCTL_SELFREF_SW_MASK 0x00000020U -/*When this is 1, the uMCTL2 puts the SDRAM into maximum power saving mode when the transaction store is empty. This register m - st be reset to '0' to bring uMCTL2 out of maximum power saving mode. Present only in designs configured to support DDR4. For - on-DDR4, this register should not be set to 1. Note that MPSM is not supported when using a DWC DDR PHY, if the PHY parameter - DWC_AC_CS_USE is disabled, as the MPSM exit sequence requires the chip-select signal to toggle. FOR PERFORMANCE ONLY.*/ +/* +* When this is 1, the uMCTL2 puts the SDRAM into maximum power saving mode + * when the transaction store is empty. This register must be reset to '0' + * to bring uMCTL2 out of maximum power saving mode. Present only in desig + * ns configured to support DDR4. For non-DDR4, this register should not be + * set to 1. Note that MPSM is not supported when using a DWC DDR PHY, if + * the PHY parameter DWC_AC_CS_USE is disabled, as the MPSM exit sequence r + * equires the chip-select signal to toggle. FOR PERFORMANCE ONLY. +*/ #undef DDRC_PWRCTL_MPSM_EN_DEFVAL #undef DDRC_PWRCTL_MPSM_EN_SHIFT #undef DDRC_PWRCTL_MPSM_EN_MASK -#define DDRC_PWRCTL_MPSM_EN_DEFVAL 0x00000000 -#define DDRC_PWRCTL_MPSM_EN_SHIFT 4 -#define DDRC_PWRCTL_MPSM_EN_MASK 0x00000010U +#define DDRC_PWRCTL_MPSM_EN_DEFVAL 0x00000000 +#define DDRC_PWRCTL_MPSM_EN_SHIFT 4 +#define DDRC_PWRCTL_MPSM_EN_MASK 0x00000010U -/*Enable the assertion of dfi_dram_clk_disable whenever a clock is not required by the SDRAM. If set to 0, dfi_dram_clk_disable - is never asserted. Assertion of dfi_dram_clk_disable is as follows: In DDR2/DDR3, can only be asserted in Self Refresh. In DD - 4, can be asserted in following: - in Self Refresh. - in Maximum Power Saving Mode In mDDR/LPDDR2/LPDDR3, can be asserted in - ollowing: - in Self Refresh - in Power Down - in Deep Power Down - during Normal operation (Clock Stop) In LPDDR4, can be ass - rted in following: - in Self Refresh Power Down - in Power Down - during Normal operation (Clock Stop)*/ +/* +* Enable the assertion of dfi_dram_clk_disable whenever a clock is not req + * uired by the SDRAM. If set to 0, dfi_dram_clk_disable is never asserted. + * Assertion of dfi_dram_clk_disable is as follows: In DDR2/DDR3, can only + * be asserted in Self Refresh. In DDR4, can be asserted in following: - i + * n Self Refresh. - in Maximum Power Saving Mode In mDDR/LPDDR2/LPDDR3, ca + * n be asserted in following: - in Self Refresh - in Power Down - in Deep + * Power Down - during Normal operation (Clock Stop) In LPDDR4, can be asse + * rted in following: - in Self Refresh Power Down - in Power Down - during + * Normal operation (Clock Stop) +*/ #undef DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_DEFVAL #undef DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_SHIFT #undef DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_MASK -#define DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_DEFVAL 0x00000000 -#define DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_SHIFT 3 -#define DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_MASK 0x00000008U +#define DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_DEFVAL 0x00000000 +#define DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_SHIFT 3 +#define DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_MASK 0x00000008U -/*When this is 1, uMCTL2 puts the SDRAM into deep power-down mode when the transaction store is empty. This register must be re - et to '0' to bring uMCTL2 out of deep power-down mode. Controller performs automatic SDRAM initialization on deep power-down - xit. Present only in designs configured to support mDDR or LPDDR2 or LPDDR3. For non-mDDR/non-LPDDR2/non-LPDDR3, this registe - should not be set to 1. FOR PERFORMANCE ONLY.*/ +/* +* When this is 1, uMCTL2 puts the SDRAM into deep power-down mode when the + * transaction store is empty. This register must be reset to '0' to bring + * uMCTL2 out of deep power-down mode. Controller performs automatic SDRAM + * initialization on deep power-down exit. Present only in designs configu + * red to support mDDR or LPDDR2 or LPDDR3. For non-mDDR/non-LPDDR2/non-LPD + * DR3, this register should not be set to 1. FOR PERFORMANCE ONLY. +*/ #undef DDRC_PWRCTL_DEEPPOWERDOWN_EN_DEFVAL #undef DDRC_PWRCTL_DEEPPOWERDOWN_EN_SHIFT #undef DDRC_PWRCTL_DEEPPOWERDOWN_EN_MASK -#define DDRC_PWRCTL_DEEPPOWERDOWN_EN_DEFVAL 0x00000000 -#define DDRC_PWRCTL_DEEPPOWERDOWN_EN_SHIFT 2 -#define DDRC_PWRCTL_DEEPPOWERDOWN_EN_MASK 0x00000004U +#define DDRC_PWRCTL_DEEPPOWERDOWN_EN_DEFVAL 0x00000000 +#define DDRC_PWRCTL_DEEPPOWERDOWN_EN_SHIFT 2 +#define DDRC_PWRCTL_DEEPPOWERDOWN_EN_MASK 0x00000004U -/*If true then the uMCTL2 goes into power-down after a programmable number of cycles 'maximum idle clocks before power down' (P - RTMG.powerdown_to_x32). This register bit may be re-programmed during the course of normal operation.*/ +/* +* If true then the uMCTL2 goes into power-down after a programmable number + * of cycles 'maximum idle clocks before power down' (PWRTMG.powerdown_to_ + * x32). This register bit may be re-programmed during the course of normal + * operation. +*/ #undef DDRC_PWRCTL_POWERDOWN_EN_DEFVAL #undef DDRC_PWRCTL_POWERDOWN_EN_SHIFT #undef DDRC_PWRCTL_POWERDOWN_EN_MASK -#define DDRC_PWRCTL_POWERDOWN_EN_DEFVAL 0x00000000 -#define DDRC_PWRCTL_POWERDOWN_EN_SHIFT 1 -#define DDRC_PWRCTL_POWERDOWN_EN_MASK 0x00000002U +#define DDRC_PWRCTL_POWERDOWN_EN_DEFVAL 0x00000000 +#define DDRC_PWRCTL_POWERDOWN_EN_SHIFT 1 +#define DDRC_PWRCTL_POWERDOWN_EN_MASK 0x00000002U -/*If true then the uMCTL2 puts the SDRAM into Self Refresh after a programmable number of cycles 'maximum idle clocks before Se - f Refresh (PWRTMG.selfref_to_x32)'. This register bit may be re-programmed during the course of normal operation.*/ +/* +* If true then the uMCTL2 puts the SDRAM into Self Refresh after a program + * mable number of cycles 'maximum idle clocks before Self Refresh (PWRTMG. + * selfref_to_x32)'. This register bit may be re-programmed during the cour + * se of normal operation. +*/ #undef DDRC_PWRCTL_SELFREF_EN_DEFVAL #undef DDRC_PWRCTL_SELFREF_EN_SHIFT #undef DDRC_PWRCTL_SELFREF_EN_MASK -#define DDRC_PWRCTL_SELFREF_EN_DEFVAL 0x00000000 -#define DDRC_PWRCTL_SELFREF_EN_SHIFT 0 -#define DDRC_PWRCTL_SELFREF_EN_MASK 0x00000001U +#define DDRC_PWRCTL_SELFREF_EN_DEFVAL 0x00000000 +#define DDRC_PWRCTL_SELFREF_EN_SHIFT 0 +#define DDRC_PWRCTL_SELFREF_EN_MASK 0x00000001U -/*After this many clocks of NOP or deselect the uMCTL2 automatically puts the SDRAM into Self Refresh. This must be enabled in - he PWRCTL.selfref_en. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY.*/ +/* +* After this many clocks of NOP or deselect the uMCTL2 automatically puts + * the SDRAM into Self Refresh. This must be enabled in the PWRCTL.selfref_ + * en. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY. +*/ #undef DDRC_PWRTMG_SELFREF_TO_X32_DEFVAL #undef DDRC_PWRTMG_SELFREF_TO_X32_SHIFT #undef DDRC_PWRTMG_SELFREF_TO_X32_MASK -#define DDRC_PWRTMG_SELFREF_TO_X32_DEFVAL 0x00402010 -#define DDRC_PWRTMG_SELFREF_TO_X32_SHIFT 16 -#define DDRC_PWRTMG_SELFREF_TO_X32_MASK 0x00FF0000U +#define DDRC_PWRTMG_SELFREF_TO_X32_DEFVAL 0x00402010 +#define DDRC_PWRTMG_SELFREF_TO_X32_SHIFT 16 +#define DDRC_PWRTMG_SELFREF_TO_X32_MASK 0x00FF0000U -/*Minimum deep power-down time. For mDDR, value from the JEDEC specification is 0 as mDDR exits from deep power-down mode immed - ately after PWRCTL.deeppowerdown_en is de-asserted. For LPDDR2/LPDDR3, value from the JEDEC specification is 500us. Unit: Mul - iples of 4096 clocks. Present only in designs configured to support mDDR, LPDDR2 or LPDDR3. FOR PERFORMANCE ONLY.*/ +/* +* Minimum deep power-down time. For mDDR, value from the JEDEC specificati + * on is 0 as mDDR exits from deep power-down mode immediately after PWRCTL + * .deeppowerdown_en is de-asserted. For LPDDR2/LPDDR3, value from the JEDE + * C specification is 500us. Unit: Multiples of 4096 clocks. Present only i + * n designs configured to support mDDR, LPDDR2 or LPDDR3. FOR PERFORMANCE + * ONLY. +*/ #undef DDRC_PWRTMG_T_DPD_X4096_DEFVAL #undef DDRC_PWRTMG_T_DPD_X4096_SHIFT #undef DDRC_PWRTMG_T_DPD_X4096_MASK -#define DDRC_PWRTMG_T_DPD_X4096_DEFVAL 0x00402010 -#define DDRC_PWRTMG_T_DPD_X4096_SHIFT 8 -#define DDRC_PWRTMG_T_DPD_X4096_MASK 0x0000FF00U +#define DDRC_PWRTMG_T_DPD_X4096_DEFVAL 0x00402010 +#define DDRC_PWRTMG_T_DPD_X4096_SHIFT 8 +#define DDRC_PWRTMG_T_DPD_X4096_MASK 0x0000FF00U -/*After this many clocks of NOP or deselect the uMCTL2 automatically puts the SDRAM into power-down. This must be enabled in th - PWRCTL.powerdown_en. Unit: Multiples of 32 clocks FOR PERFORMANCE ONLY.*/ +/* +* After this many clocks of NOP or deselect the uMCTL2 automatically puts + * the SDRAM into power-down. This must be enabled in the PWRCTL.powerdown_ + * en. Unit: Multiples of 32 clocks FOR PERFORMANCE ONLY. +*/ #undef DDRC_PWRTMG_POWERDOWN_TO_X32_DEFVAL #undef DDRC_PWRTMG_POWERDOWN_TO_X32_SHIFT #undef DDRC_PWRTMG_POWERDOWN_TO_X32_MASK -#define DDRC_PWRTMG_POWERDOWN_TO_X32_DEFVAL 0x00402010 -#define DDRC_PWRTMG_POWERDOWN_TO_X32_SHIFT 0 -#define DDRC_PWRTMG_POWERDOWN_TO_X32_MASK 0x0000001FU +#define DDRC_PWRTMG_POWERDOWN_TO_X32_DEFVAL 0x00402010 +#define DDRC_PWRTMG_POWERDOWN_TO_X32_SHIFT 0 +#define DDRC_PWRTMG_POWERDOWN_TO_X32_MASK 0x0000001FU -/*Threshold value in number of clock cycles before the critical refresh or page timer expires. A critical refresh is to be issu - d before this threshold is reached. It is recommended that this not be changed from the default value, currently shown as 0x2 - It must always be less than internally used t_rfc_nom_x32. Note that, in LPDDR2/LPDDR3/LPDDR4, internally used t_rfc_nom_x32 - may be equal to RFSHTMG.t_rfc_nom_x32>>2 if derating is enabled (DERATEEN.derate_enable=1). Otherwise, internally used t_rfc_ - om_x32 will be equal to RFSHTMG.t_rfc_nom_x32. Unit: Multiples of 32 clocks.*/ +/* +* Threshold value in number of clock cycles before the critical refresh or + * page timer expires. A critical refresh is to be issued before this thre + * shold is reached. It is recommended that this not be changed from the de + * fault value, currently shown as 0x2. It must always be less than interna + * lly used t_rfc_nom_x32. Note that, in LPDDR2/LPDDR3/LPDDR4, internally u + * sed t_rfc_nom_x32 may be equal to RFSHTMG.t_rfc_nom_x32>>2 if derating i + * s enabled (DERATEEN.derate_enable=1). Otherwise, internally used t_rfc_n + * om_x32 will be equal to RFSHTMG.t_rfc_nom_x32. Unit: Multiples of 32 clo + * cks. +*/ #undef DDRC_RFSHCTL0_REFRESH_MARGIN_DEFVAL #undef DDRC_RFSHCTL0_REFRESH_MARGIN_SHIFT #undef DDRC_RFSHCTL0_REFRESH_MARGIN_MASK -#define DDRC_RFSHCTL0_REFRESH_MARGIN_DEFVAL 0x00210000 -#define DDRC_RFSHCTL0_REFRESH_MARGIN_SHIFT 20 -#define DDRC_RFSHCTL0_REFRESH_MARGIN_MASK 0x00F00000U +#define DDRC_RFSHCTL0_REFRESH_MARGIN_DEFVAL 0x00210000 +#define DDRC_RFSHCTL0_REFRESH_MARGIN_SHIFT 20 +#define DDRC_RFSHCTL0_REFRESH_MARGIN_MASK 0x00F00000U -/*If the refresh timer (tRFCnom, also known as tREFI) has expired at least once, but it has not expired (RFSHCTL0.refresh_burst - 1) times yet, then a speculative refresh may be performed. A speculative refresh is a refresh performed at a time when refres - would be useful, but before it is absolutely required. When the SDRAM bus is idle for a period of time determined by this RF - HCTL0.refresh_to_x32 and the refresh timer has expired at least once since the last refresh, then a speculative refresh is pe - formed. Speculative refreshes continues successively until there are no refreshes pending or until new reads or writes are is - ued to the uMCTL2. FOR PERFORMANCE ONLY.*/ +/* +* If the refresh timer (tRFCnom, also known as tREFI) has expired at least + * once, but it has not expired (RFSHCTL0.refresh_burst+1) times yet, then + * a speculative refresh may be performed. A speculative refresh is a refr + * esh performed at a time when refresh would be useful, but before it is a + * bsolutely required. When the SDRAM bus is idle for a period of time dete + * rmined by this RFSHCTL0.refresh_to_x32 and the refresh timer has expired + * at least once since the last refresh, then a speculative refresh is per + * formed. Speculative refreshes continues successively until there are no + * refreshes pending or until new reads or writes are issued to the uMCTL2. + * FOR PERFORMANCE ONLY. +*/ #undef DDRC_RFSHCTL0_REFRESH_TO_X32_DEFVAL #undef DDRC_RFSHCTL0_REFRESH_TO_X32_SHIFT #undef DDRC_RFSHCTL0_REFRESH_TO_X32_MASK -#define DDRC_RFSHCTL0_REFRESH_TO_X32_DEFVAL 0x00210000 -#define DDRC_RFSHCTL0_REFRESH_TO_X32_SHIFT 12 -#define DDRC_RFSHCTL0_REFRESH_TO_X32_MASK 0x0001F000U +#define DDRC_RFSHCTL0_REFRESH_TO_X32_DEFVAL 0x00210000 +#define DDRC_RFSHCTL0_REFRESH_TO_X32_SHIFT 12 +#define DDRC_RFSHCTL0_REFRESH_TO_X32_MASK 0x0001F000U -/*The programmed value + 1 is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the re - reshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of re - reshes. Therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for - RFSHCTL.refresh_burst slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshe - . - 0 - single refresh - 1 - burst-of-2 refresh - 7 - burst-of-8 refresh For information on burst refresh feature refer to se - tion 3.9 of DDR2 JEDEC specification - JESD79-2F.pdf. For DDR2/3, the refresh is always per-rank and not per-bank. The rank r - fresh can be accumulated over 8*tREFI cycles using the burst refresh feature. In DDR4 mode, according to Fine Granularity fea - ure, 8 refreshes can be postponed in 1X mode, 16 refreshes in 2X mode and 32 refreshes in 4X mode. If using PHY-initiated upd - tes, care must be taken in the setting of RFSHCTL0.refresh_burst, to ensure that tRFCmax is not violated due to a PHY-initiat - d update occurring shortly before a refresh burst was due. In this situation, the refresh burst will be delayed until the PHY - initiated update is complete.*/ +/* +* The programmed value + 1 is the number of refresh timeouts that is allow + * ed to accumulate before traffic is blocked and the refreshes are forced + * to execute. Closing pages to perform a refresh is a one-time penalty tha + * t must be paid for each group of refreshes. Therefore, performing refres + * hes in a burst reduces the per-refresh penalty of these page closings. H + * igher numbers for RFSHCTL.refresh_burst slightly increases utilization; + * lower numbers decreases the worst-case latency associated with refreshes + * . - 0 - single refresh - 1 - burst-of-2 refresh - 7 - burst-of-8 refresh + * For information on burst refresh feature refer to section 3.9 of DDR2 J + * EDEC specification - JESD79-2F.pdf. For DDR2/3, the refresh is always pe + * r-rank and not per-bank. The rank refresh can be accumulated over 8*tREF + * I cycles using the burst refresh feature. In DDR4 mode, according to Fin + * e Granularity feature, 8 refreshes can be postponed in 1X mode, 16 refre + * shes in 2X mode and 32 refreshes in 4X mode. If using PHY-initiated upda + * tes, care must be taken in the setting of RFSHCTL0.refresh_burst, to ens + * ure that tRFCmax is not violated due to a PHY-initiated update occurring + * shortly before a refresh burst was due. In this situation, the refresh + * burst will be delayed until the PHY-initiated update is complete. +*/ #undef DDRC_RFSHCTL0_REFRESH_BURST_DEFVAL #undef DDRC_RFSHCTL0_REFRESH_BURST_SHIFT #undef DDRC_RFSHCTL0_REFRESH_BURST_MASK -#define DDRC_RFSHCTL0_REFRESH_BURST_DEFVAL 0x00210000 -#define DDRC_RFSHCTL0_REFRESH_BURST_SHIFT 4 -#define DDRC_RFSHCTL0_REFRESH_BURST_MASK 0x000001F0U +#define DDRC_RFSHCTL0_REFRESH_BURST_DEFVAL 0x00210000 +#define DDRC_RFSHCTL0_REFRESH_BURST_SHIFT 4 +#define DDRC_RFSHCTL0_REFRESH_BURST_MASK 0x000001F0U -/*- 1 - Per bank refresh; - 0 - All bank refresh. Per bank refresh allows traffic to flow to other banks. Per bank refresh is n - t supported by all LPDDR2 devices but should be supported by all LPDDR3/LPDDR4 devices. Present only in designs configured to - support LPDDR2/LPDDR3/LPDDR4*/ +/* +* - 1 - Per bank refresh; - 0 - All bank refresh. Per bank refresh allows + * traffic to flow to other banks. Per bank refresh is not supported by all + * LPDDR2 devices but should be supported by all LPDDR3/LPDDR4 devices. Pr + * esent only in designs configured to support LPDDR2/LPDDR3/LPDDR4 +*/ #undef DDRC_RFSHCTL0_PER_BANK_REFRESH_DEFVAL #undef DDRC_RFSHCTL0_PER_BANK_REFRESH_SHIFT #undef DDRC_RFSHCTL0_PER_BANK_REFRESH_MASK -#define DDRC_RFSHCTL0_PER_BANK_REFRESH_DEFVAL 0x00210000 -#define DDRC_RFSHCTL0_PER_BANK_REFRESH_SHIFT 2 -#define DDRC_RFSHCTL0_PER_BANK_REFRESH_MASK 0x00000004U +#define DDRC_RFSHCTL0_PER_BANK_REFRESH_DEFVAL 0x00210000 +#define DDRC_RFSHCTL0_PER_BANK_REFRESH_SHIFT 2 +#define DDRC_RFSHCTL0_PER_BANK_REFRESH_MASK 0x00000004U -/*Fine Granularity Refresh Mode - 000 - Fixed 1x (Normal mode) - 001 - Fixed 2x - 010 - Fixed 4x - 101 - Enable on the fly 2x ( - ot supported) - 110 - Enable on the fly 4x (not supported) - Everything else - reserved Note: The on-the-fly modes is not sup - orted in this version of the uMCTL2. Note: This must be set up while the Controller is in reset or while the Controller is in - self-refresh mode. Changing this during normal operation is not allowed. Making this a dynamic register will be supported in - uture version of the uMCTL2.*/ +/* +* Refresh timer start for rank 1 (only present in multi-rank configuration + * s). This is useful in staggering the refreshes to multiple ranks to help + * traffic to proceed. This is explained in Refresh Controls section of ar + * chitecture chapter. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY. +*/ +#undef DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_DEFVAL +#undef DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_SHIFT +#undef DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_MASK +#define DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_DEFVAL 0x00000000 +#define DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_SHIFT 16 +#define DDRC_RFSHCTL1_REFRESH_TIMER1_START_VALUE_X32_MASK 0x0FFF0000U + +/* +* Refresh timer start for rank 0 (only present in multi-rank configuration + * s). This is useful in staggering the refreshes to multiple ranks to help + * traffic to proceed. This is explained in Refresh Controls section of ar + * chitecture chapter. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY. +*/ +#undef DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_DEFVAL +#undef DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_SHIFT +#undef DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_MASK +#define DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_DEFVAL 0x00000000 +#define DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_SHIFT 0 +#define DDRC_RFSHCTL1_REFRESH_TIMER0_START_VALUE_X32_MASK 0x00000FFFU + +/* +* Fine Granularity Refresh Mode - 000 - Fixed 1x (Normal mode) - 001 - Fix + * ed 2x - 010 - Fixed 4x - 101 - Enable on the fly 2x (not supported) - 11 + * 0 - Enable on the fly 4x (not supported) - Everything else - reserved No + * te: The on-the-fly modes is not supported in this version of the uMCTL2. + * Note: This must be set up while the Controller is in reset or while the + * Controller is in self-refresh mode. Changing this during normal operati + * on is not allowed. Making this a dynamic register will be supported in f + * uture version of the uMCTL2. +*/ #undef DDRC_RFSHCTL3_REFRESH_MODE_DEFVAL #undef DDRC_RFSHCTL3_REFRESH_MODE_SHIFT #undef DDRC_RFSHCTL3_REFRESH_MODE_MASK -#define DDRC_RFSHCTL3_REFRESH_MODE_DEFVAL 0x00000000 -#define DDRC_RFSHCTL3_REFRESH_MODE_SHIFT 4 -#define DDRC_RFSHCTL3_REFRESH_MODE_MASK 0x00000070U +#define DDRC_RFSHCTL3_REFRESH_MODE_DEFVAL 0x00000000 +#define DDRC_RFSHCTL3_REFRESH_MODE_SHIFT 4 +#define DDRC_RFSHCTL3_REFRESH_MODE_MASK 0x00000070U -/*Toggle this signal (either from 0 to 1 or from 1 to 0) to indicate that the refresh register(s) have been updated. The value - s automatically updated when exiting reset, so it does not need to be toggled initially.*/ +/* +* Toggle this signal (either from 0 to 1 or from 1 to 0) to indicate that + * the refresh register(s) have been updated. The value is automatically up + * dated when exiting reset, so it does not need to be toggled initially. +*/ #undef DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_DEFVAL #undef DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_SHIFT #undef DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_MASK -#define DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_DEFVAL 0x00000000 -#define DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_SHIFT 1 -#define DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_MASK 0x00000002U +#define DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_DEFVAL 0x00000000 +#define DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_SHIFT 1 +#define DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_MASK 0x00000002U -/*When '1', disable auto-refresh generated by the uMCTL2. When auto-refresh is disabled, the SoC core must generate refreshes u - ing the registers reg_ddrc_rank0_refresh, reg_ddrc_rank1_refresh, reg_ddrc_rank2_refresh and reg_ddrc_rank3_refresh. When dis - auto_refresh transitions from 0 to 1, any pending refreshes are immediately scheduled by the uMCTL2. If DDR4 CRC/parity retry - is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), disable auto-refresh is not supported, and this bit must be set to '0'. - his register field is changeable on the fly.*/ +/* +* When '1', disable auto-refresh generated by the uMCTL2. When auto-refres + * h is disabled, the SoC core must generate refreshes using the registers + * reg_ddrc_rank0_refresh, reg_ddrc_rank1_refresh, reg_ddrc_rank2_refresh a + * nd reg_ddrc_rank3_refresh. When dis_auto_refresh transitions from 0 to 1 + * , any pending refreshes are immediately scheduled by the uMCTL2. If DDR4 + * CRC/parity retry is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), d + * isable auto-refresh is not supported, and this bit must be set to '0'. T + * his register field is changeable on the fly. +*/ #undef DDRC_RFSHCTL3_DIS_AUTO_REFRESH_DEFVAL #undef DDRC_RFSHCTL3_DIS_AUTO_REFRESH_SHIFT #undef DDRC_RFSHCTL3_DIS_AUTO_REFRESH_MASK -#define DDRC_RFSHCTL3_DIS_AUTO_REFRESH_DEFVAL 0x00000000 -#define DDRC_RFSHCTL3_DIS_AUTO_REFRESH_SHIFT 0 -#define DDRC_RFSHCTL3_DIS_AUTO_REFRESH_MASK 0x00000001U +#define DDRC_RFSHCTL3_DIS_AUTO_REFRESH_DEFVAL 0x00000000 +#define DDRC_RFSHCTL3_DIS_AUTO_REFRESH_SHIFT 0 +#define DDRC_RFSHCTL3_DIS_AUTO_REFRESH_MASK 0x00000001U -/*tREFI: Average time interval between refreshes per rank (Specification: 7.8us for DDR2, DDR3 and DDR4. See JEDEC specificatio - for mDDR, LPDDR2, LPDDR3 and LPDDR4). For LPDDR2/LPDDR3/LPDDR4: - if using all-bank refreshes (RFSHCTL0.per_bank_refresh = 0 - , this register should be set to tREFIab - if using per-bank refreshes (RFSHCTL0.per_bank_refresh = 1), this register should - e set to tREFIpb For configurations with MEMC_FREQ_RATIO=2, program this to (tREFI/2), no rounding up. In DDR4 mode, tREFI va - ue is different depending on the refresh mode. The user should program the appropriate value from the spec based on the value - programmed in the refresh mode register. Note that RFSHTMG.t_rfc_nom_x32 * 32 must be greater than RFSHTMG.t_rfc_min, and RFS - TMG.t_rfc_nom_x32 must be greater than 0x1. Unit: Multiples of 32 clocks.*/ +/* +* tREFI: Average time interval between refreshes per rank (Specification: + * 7.8us for DDR2, DDR3 and DDR4. See JEDEC specification for mDDR, LPDDR2, + * LPDDR3 and LPDDR4). For LPDDR2/LPDDR3/LPDDR4: - if using all-bank refre + * shes (RFSHCTL0.per_bank_refresh = 0), this register should be set to tRE + * FIab - if using per-bank refreshes (RFSHCTL0.per_bank_refresh = 1), this + * register should be set to tREFIpb For configurations with MEMC_FREQ_RAT + * IO=2, program this to (tREFI/2), no rounding up. In DDR4 mode, tREFI val + * ue is different depending on the refresh mode. The user should program t + * he appropriate value from the spec based on the value programmed in the + * refresh mode register. Note that RFSHTMG.t_rfc_nom_x32 * 32 must be grea + * ter than RFSHTMG.t_rfc_min, and RFSHTMG.t_rfc_nom_x32 must be greater th + * an 0x1. Unit: Multiples of 32 clocks. +*/ #undef DDRC_RFSHTMG_T_RFC_NOM_X32_DEFVAL #undef DDRC_RFSHTMG_T_RFC_NOM_X32_SHIFT #undef DDRC_RFSHTMG_T_RFC_NOM_X32_MASK -#define DDRC_RFSHTMG_T_RFC_NOM_X32_DEFVAL 0x0062008C -#define DDRC_RFSHTMG_T_RFC_NOM_X32_SHIFT 16 -#define DDRC_RFSHTMG_T_RFC_NOM_X32_MASK 0x0FFF0000U +#define DDRC_RFSHTMG_T_RFC_NOM_X32_DEFVAL 0x0062008C +#define DDRC_RFSHTMG_T_RFC_NOM_X32_SHIFT 16 +#define DDRC_RFSHTMG_T_RFC_NOM_X32_MASK 0x0FFF0000U -/*Used only when LPDDR3 memory type is connected. Should only be changed when uMCTL2 is in reset. Specifies whether to use the - REFBW parameter (required by some LPDDR3 devices which comply with earlier versions of the LPDDR3 JEDEC specification) or not - - 0 - tREFBW parameter not used - 1 - tREFBW parameter used*/ +/* +* Used only when LPDDR3 memory type is connected. Should only be changed w + * hen uMCTL2 is in reset. Specifies whether to use the tREFBW parameter (r + * equired by some LPDDR3 devices which comply with earlier versions of the + * LPDDR3 JEDEC specification) or not: - 0 - tREFBW parameter not used - 1 + * - tREFBW parameter used +*/ #undef DDRC_RFSHTMG_LPDDR3_TREFBW_EN_DEFVAL #undef DDRC_RFSHTMG_LPDDR3_TREFBW_EN_SHIFT #undef DDRC_RFSHTMG_LPDDR3_TREFBW_EN_MASK -#define DDRC_RFSHTMG_LPDDR3_TREFBW_EN_DEFVAL 0x0062008C -#define DDRC_RFSHTMG_LPDDR3_TREFBW_EN_SHIFT 15 -#define DDRC_RFSHTMG_LPDDR3_TREFBW_EN_MASK 0x00008000U +#define DDRC_RFSHTMG_LPDDR3_TREFBW_EN_DEFVAL 0x0062008C +#define DDRC_RFSHTMG_LPDDR3_TREFBW_EN_SHIFT 15 +#define DDRC_RFSHTMG_LPDDR3_TREFBW_EN_MASK 0x00008000U -/*tRFC (min): Minimum time from refresh to refresh or activate. For MEMC_FREQ_RATIO=1 configurations, t_rfc_min should be set t - RoundUp(tRFCmin/tCK). For MEMC_FREQ_RATIO=2 configurations, t_rfc_min should be set to RoundUp(RoundUp(tRFCmin/tCK)/2). In L - DDR2/LPDDR3/LPDDR4 mode: - if using all-bank refreshes, the tRFCmin value in the above equations is equal to tRFCab - if usin - per-bank refreshes, the tRFCmin value in the above equations is equal to tRFCpb In DDR4 mode, the tRFCmin value in the above - equations is different depending on the refresh mode (fixed 1X,2X,4X) and the device density. The user should program the app - opriate value from the spec based on the 'refresh_mode' and the device density that is used. Unit: Clocks.*/ +/* +* tRFC (min): Minimum time from refresh to refresh or activate. For MEMC_F + * REQ_RATIO=1 configurations, t_rfc_min should be set to RoundUp(tRFCmin/t + * CK). For MEMC_FREQ_RATIO=2 configurations, t_rfc_min should be set to Ro + * undUp(RoundUp(tRFCmin/tCK)/2). In LPDDR2/LPDDR3/LPDDR4 mode: - if using + * all-bank refreshes, the tRFCmin value in the above equations is equal to + * tRFCab - if using per-bank refreshes, the tRFCmin value in the above eq + * uations is equal to tRFCpb In DDR4 mode, the tRFCmin value in the above + * equations is different depending on the refresh mode (fixed 1X,2X,4X) an + * d the device density. The user should program the appropriate value from + * the spec based on the 'refresh_mode' and the device density that is use + * d. Unit: Clocks. +*/ #undef DDRC_RFSHTMG_T_RFC_MIN_DEFVAL #undef DDRC_RFSHTMG_T_RFC_MIN_SHIFT #undef DDRC_RFSHTMG_T_RFC_MIN_MASK -#define DDRC_RFSHTMG_T_RFC_MIN_DEFVAL 0x0062008C -#define DDRC_RFSHTMG_T_RFC_MIN_SHIFT 0 -#define DDRC_RFSHTMG_T_RFC_MIN_MASK 0x000003FFU +#define DDRC_RFSHTMG_T_RFC_MIN_DEFVAL 0x0062008C +#define DDRC_RFSHTMG_T_RFC_MIN_SHIFT 0 +#define DDRC_RFSHTMG_T_RFC_MIN_MASK 0x000003FFU -/*Disable ECC scrubs. Valid only when ECCCFG0.ecc_mode = 3'b100 and MEMC_USE_RMW is defined*/ +/* +* Disable ECC scrubs. Valid only when ECCCFG0.ecc_mode = 3'b100 and MEMC_U + * SE_RMW is defined +*/ #undef DDRC_ECCCFG0_DIS_SCRUB_DEFVAL #undef DDRC_ECCCFG0_DIS_SCRUB_SHIFT #undef DDRC_ECCCFG0_DIS_SCRUB_MASK -#define DDRC_ECCCFG0_DIS_SCRUB_DEFVAL 0x00000000 -#define DDRC_ECCCFG0_DIS_SCRUB_SHIFT 4 -#define DDRC_ECCCFG0_DIS_SCRUB_MASK 0x00000010U +#define DDRC_ECCCFG0_DIS_SCRUB_DEFVAL 0x00000000 +#define DDRC_ECCCFG0_DIS_SCRUB_SHIFT 4 +#define DDRC_ECCCFG0_DIS_SCRUB_MASK 0x00000010U -/*ECC mode indicator - 000 - ECC disabled - 100 - ECC enabled - SEC/DED over 1 beat - all other settings are reserved for futur - use*/ +/* +* ECC mode indicator - 000 - ECC disabled - 100 - ECC enabled - SEC/DED ov + * er 1 beat - all other settings are reserved for future use +*/ #undef DDRC_ECCCFG0_ECC_MODE_DEFVAL #undef DDRC_ECCCFG0_ECC_MODE_SHIFT #undef DDRC_ECCCFG0_ECC_MODE_MASK -#define DDRC_ECCCFG0_ECC_MODE_DEFVAL 0x00000000 -#define DDRC_ECCCFG0_ECC_MODE_SHIFT 0 -#define DDRC_ECCCFG0_ECC_MODE_MASK 0x00000007U +#define DDRC_ECCCFG0_ECC_MODE_DEFVAL 0x00000000 +#define DDRC_ECCCFG0_ECC_MODE_SHIFT 0 +#define DDRC_ECCCFG0_ECC_MODE_MASK 0x00000007U -/*Selects whether to poison 1 or 2 bits - if 0 -> 2-bit (uncorrectable) data poisoning, if 1 -> 1-bit (correctable) data poison - ng, if ECCCFG1.data_poison_en=1*/ +/* +* Selects whether to poison 1 or 2 bits - if 0 -> 2-bit (uncorrectable) da + * ta poisoning, if 1 -> 1-bit (correctable) data poisoning, if ECCCFG1.dat + * a_poison_en=1 +*/ #undef DDRC_ECCCFG1_DATA_POISON_BIT_DEFVAL #undef DDRC_ECCCFG1_DATA_POISON_BIT_SHIFT #undef DDRC_ECCCFG1_DATA_POISON_BIT_MASK -#define DDRC_ECCCFG1_DATA_POISON_BIT_DEFVAL 0x00000000 -#define DDRC_ECCCFG1_DATA_POISON_BIT_SHIFT 1 -#define DDRC_ECCCFG1_DATA_POISON_BIT_MASK 0x00000002U +#define DDRC_ECCCFG1_DATA_POISON_BIT_DEFVAL 0x00000000 +#define DDRC_ECCCFG1_DATA_POISON_BIT_SHIFT 1 +#define DDRC_ECCCFG1_DATA_POISON_BIT_MASK 0x00000002U -/*Enable ECC data poisoning - introduces ECC errors on writes to address specified by the ECCPOISONADDR0/1 registers*/ +/* +* Enable ECC data poisoning - introduces ECC errors on writes to address s + * pecified by the ECCPOISONADDR0/1 registers +*/ #undef DDRC_ECCCFG1_DATA_POISON_EN_DEFVAL #undef DDRC_ECCCFG1_DATA_POISON_EN_SHIFT #undef DDRC_ECCCFG1_DATA_POISON_EN_MASK -#define DDRC_ECCCFG1_DATA_POISON_EN_DEFVAL 0x00000000 -#define DDRC_ECCCFG1_DATA_POISON_EN_SHIFT 0 -#define DDRC_ECCCFG1_DATA_POISON_EN_MASK 0x00000001U +#define DDRC_ECCCFG1_DATA_POISON_EN_DEFVAL 0x00000000 +#define DDRC_ECCCFG1_DATA_POISON_EN_SHIFT 0 +#define DDRC_ECCCFG1_DATA_POISON_EN_MASK 0x00000001U -/*The maximum number of DFI PHY clock cycles allowed from the assertion of the dfi_rddata_en signal to the assertion of each of - the corresponding bits of the dfi_rddata_valid signal. This corresponds to the DFI timing parameter tphy_rdlat. Refer to PHY - pecification for correct value. This value it only used for detecting read data timeout when DDR4 retry is enabled by CRCPARC - L1.crc_parity_retry_enable=1. Maximum supported value: - 1:1 Frequency mode : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_ - dlat < 'd114 - 1:2 Frequency mode ANDAND DFITMG0.dfi_rddata_use_sdr == 1 : CRCPARCTL1.dfi_t_phy_rdlat < 64 - 1:2 Frequency mo - e ANDAND DFITMG0.dfi_rddata_use_sdr == 0 : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_rdlat < 'd114 Unit: DFI Clocks*/ +/* +* The maximum number of DFI PHY clock cycles allowed from the assertion of + * the dfi_rddata_en signal to the assertion of each of the corresponding + * bits of the dfi_rddata_valid signal. This corresponds to the DFI timing + * parameter tphy_rdlat. Refer to PHY specification for correct value. This + * value it only used for detecting read data timeout when DDR4 retry is e + * nabled by CRCPARCTL1.crc_parity_retry_enable=1. Maximum supported value: + * - 1:1 Frequency mode : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_r + * dlat < 'd114 - 1:2 Frequency mode ANDAND DFITMG0.dfi_rddata_use_sdr == 1 + * : CRCPARCTL1.dfi_t_phy_rdlat < 64 - 1:2 Frequency mode ANDAND DFITMG0.d + * fi_rddata_use_sdr == 0 : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_ + * rdlat < 'd114 Unit: DFI Clocks +*/ #undef DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_DEFVAL #undef DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_SHIFT #undef DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_MASK -#define DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_DEFVAL 0x10000200 -#define DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_SHIFT 24 -#define DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_MASK 0x3F000000U +#define DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_DEFVAL 0x10000200 +#define DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_SHIFT 24 +#define DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_MASK 0x3F000000U -/*After a Parity or CRC error is flagged on dfi_alert_n signal, the software has an option to read the mode registers in the DR - M before the hardware begins the retry process - 1: Wait for software to read/write the mode registers before hardware begins - the retry. After software is done with its operations, it will clear the alert interrupt register bit - 0: Hardware can begin - the retry right away after the dfi_alert_n pulse goes away. The value on this register is valid only when retry is enabled (P - RCTRL.crc_parity_retry_enable = 1) If this register is set to 1 and if the software doesn't clear the interrupt register afte - handling the parity/CRC error, then the hardware will not begin the retry process and the system will hang. In the case of P - rity/CRC error, there are two possibilities when the software doesn't reset MR5[4] to 0. - (i) If 'Persistent parity' mode re - ister bit is NOT set: the commands sent during retry and normal operation are executed without parity checking. The value in - he Parity error log register MPR Page 1 is valid. - (ii) If 'Persistent parity' mode register bit is SET: Parity checking is - one for commands sent during retry and normal operation. If multiple errors occur before MR5[4] is cleared, the error log in - PR Page 1 should be treated as 'Don't care'.*/ +/* +* After a Parity or CRC error is flagged on dfi_alert_n signal, the softwa + * re has an option to read the mode registers in the DRAM before the hardw + * are begins the retry process - 1: Wait for software to read/write the mo + * de registers before hardware begins the retry. After software is done wi + * th its operations, it will clear the alert interrupt register bit - 0: H + * ardware can begin the retry right away after the dfi_alert_n pulse goes + * away. The value on this register is valid only when retry is enabled (PA + * RCTRL.crc_parity_retry_enable = 1) If this register is set to 1 and if t + * he software doesn't clear the interrupt register after handling the pari + * ty/CRC error, then the hardware will not begin the retry process and the + * system will hang. In the case of Parity/CRC error, there are two possib + * ilities when the software doesn't reset MR5[4] to 0. - (i) If 'Persisten + * t parity' mode register bit is NOT set: the commands sent during retry a + * nd normal operation are executed without parity checking. The value in t + * he Parity error log register MPR Page 1 is valid. - (ii) If 'Persistent + * parity' mode register bit is SET: Parity checking is done for commands s + * ent during retry and normal operation. If multiple errors occur before M + * R5[4] is cleared, the error log in MPR Page 1 should be treated as 'Don' + * t care'. +*/ #undef DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_DEFVAL #undef DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_SHIFT #undef DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_MASK -#define DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_DEFVAL 0x10000200 -#define DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_SHIFT 9 -#define DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_MASK 0x00000200U +#define DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_DEFVAL 0x10000200 +#define DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_SHIFT 9 +#define DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_MASK 0x00000200U -/*- 1: Enable command retry mechanism in case of C/A Parity or CRC error - 0: Disable command retry mechanism when C/A Parity o - CRC features are enabled. Note that retry functionality is not supported if burst chop is enabled (MSTR.burstchop = 1) and/o - disable auto-refresh is enabled (RFSHCTL3.dis_auto_refresh = 1)*/ +/* +* - 1: Enable command retry mechanism in case of C/A Parity or CRC error - + * 0: Disable command retry mechanism when C/A Parity or CRC features are + * enabled. Note that retry functionality is not supported if burst chop is + * enabled (MSTR.burstchop = 1) and/or disable auto-refresh is enabled (RF + * SHCTL3.dis_auto_refresh = 1) +*/ #undef DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_DEFVAL #undef DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_SHIFT #undef DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_MASK -#define DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_DEFVAL 0x10000200 -#define DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_SHIFT 8 -#define DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_MASK 0x00000100U +#define DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_DEFVAL 0x10000200 +#define DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_SHIFT 8 +#define DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_MASK 0x00000100U -/*CRC Calculation setting register - 1: CRC includes DM signal - 0: CRC not includes DM signal Present only in designs configur - d to support DDR4.*/ +/* +* CRC Calculation setting register - 1: CRC includes DM signal - 0: CRC no + * t includes DM signal Present only in designs configured to support DDR4. +*/ #undef DDRC_CRCPARCTL1_CRC_INC_DM_DEFVAL #undef DDRC_CRCPARCTL1_CRC_INC_DM_SHIFT #undef DDRC_CRCPARCTL1_CRC_INC_DM_MASK -#define DDRC_CRCPARCTL1_CRC_INC_DM_DEFVAL 0x10000200 -#define DDRC_CRCPARCTL1_CRC_INC_DM_SHIFT 7 -#define DDRC_CRCPARCTL1_CRC_INC_DM_MASK 0x00000080U +#define DDRC_CRCPARCTL1_CRC_INC_DM_DEFVAL 0x10000200 +#define DDRC_CRCPARCTL1_CRC_INC_DM_SHIFT 7 +#define DDRC_CRCPARCTL1_CRC_INC_DM_MASK 0x00000080U -/*CRC enable Register - 1: Enable generation of CRC - 0: Disable generation of CRC The setting of this register should match th - CRC mode register setting in the DRAM.*/ +/* +* CRC enable Register - 1: Enable generation of CRC - 0: Disable generatio + * n of CRC The setting of this register should match the CRC mode register + * setting in the DRAM. +*/ #undef DDRC_CRCPARCTL1_CRC_ENABLE_DEFVAL #undef DDRC_CRCPARCTL1_CRC_ENABLE_SHIFT #undef DDRC_CRCPARCTL1_CRC_ENABLE_MASK -#define DDRC_CRCPARCTL1_CRC_ENABLE_DEFVAL 0x10000200 -#define DDRC_CRCPARCTL1_CRC_ENABLE_SHIFT 4 -#define DDRC_CRCPARCTL1_CRC_ENABLE_MASK 0x00000010U +#define DDRC_CRCPARCTL1_CRC_ENABLE_DEFVAL 0x10000200 +#define DDRC_CRCPARCTL1_CRC_ENABLE_SHIFT 4 +#define DDRC_CRCPARCTL1_CRC_ENABLE_MASK 0x00000010U -/*C/A Parity enable register - 1: Enable generation of C/A parity and detection of C/A parity error - 0: Disable generation of - /A parity and disable detection of C/A parity error If RCD's parity error detection or SDRAM's parity detection is enabled, t - is register should be 1.*/ +/* +* C/A Parity enable register - 1: Enable generation of C/A parity and dete + * ction of C/A parity error - 0: Disable generation of C/A parity and disa + * ble detection of C/A parity error If RCD's parity error detection or SDR + * AM's parity detection is enabled, this register should be 1. +*/ #undef DDRC_CRCPARCTL1_PARITY_ENABLE_DEFVAL #undef DDRC_CRCPARCTL1_PARITY_ENABLE_SHIFT #undef DDRC_CRCPARCTL1_PARITY_ENABLE_MASK -#define DDRC_CRCPARCTL1_PARITY_ENABLE_DEFVAL 0x10000200 -#define DDRC_CRCPARCTL1_PARITY_ENABLE_SHIFT 0 -#define DDRC_CRCPARCTL1_PARITY_ENABLE_MASK 0x00000001U +#define DDRC_CRCPARCTL1_PARITY_ENABLE_DEFVAL 0x10000200 +#define DDRC_CRCPARCTL1_PARITY_ENABLE_SHIFT 0 +#define DDRC_CRCPARCTL1_PARITY_ENABLE_MASK 0x00000001U -/*Value from the DRAM spec indicating the maximum width of the dfi_alert_n pulse when a parity error occurs. Recommended values - - tPAR_ALERT_PW.MAX For configurations with MEMC_FREQ_RATIO=2, program this to tPAR_ALERT_PW.MAX/2 and round up to next inte - er value. Values of 0, 1 and 2 are illegal. This value must be greater than CRCPARCTL2.t_crc_alert_pw_max.*/ +/* +* Value from the DRAM spec indicating the maximum width of the dfi_alert_n + * pulse when a parity error occurs. Recommended values: - tPAR_ALERT_PW.M + * AX For configurations with MEMC_FREQ_RATIO=2, program this to tPAR_ALERT + * _PW.MAX/2 and round up to next integer value. Values of 0, 1 and 2 are i + * llegal. This value must be greater than CRCPARCTL2.t_crc_alert_pw_max. +*/ #undef DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_DEFVAL #undef DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_SHIFT #undef DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_MASK -#define DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_DEFVAL 0x0030050C -#define DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_SHIFT 16 -#define DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_MASK 0x01FF0000U +#define DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_DEFVAL 0x0030050C +#define DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_SHIFT 16 +#define DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_MASK 0x01FF0000U -/*Value from the DRAM spec indicating the maximum width of the dfi_alert_n pulse when a CRC error occurs. Recommended values: - - tCRC_ALERT_PW.MAX For configurations with MEMC_FREQ_RATIO=2, program this to tCRC_ALERT_PW.MAX/2 and round up to next integer - value. Values of 0, 1 and 2 are illegal. This value must be less than CRCPARCTL2.t_par_alert_pw_max.*/ +/* +* Value from the DRAM spec indicating the maximum width of the dfi_alert_n + * pulse when a CRC error occurs. Recommended values: - tCRC_ALERT_PW.MAX + * For configurations with MEMC_FREQ_RATIO=2, program this to tCRC_ALERT_PW + * .MAX/2 and round up to next integer value. Values of 0, 1 and 2 are ille + * gal. This value must be less than CRCPARCTL2.t_par_alert_pw_max. +*/ #undef DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_DEFVAL #undef DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_SHIFT #undef DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_MASK -#define DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_DEFVAL 0x0030050C -#define DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_SHIFT 8 -#define DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_MASK 0x00001F00U +#define DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_DEFVAL 0x0030050C +#define DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_SHIFT 8 +#define DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_MASK 0x00001F00U -/*Indicates the maximum duration in number of DRAM clock cycles for which a command should be held in the Command Retry FIFO be - ore it is popped out. Every location in the Command Retry FIFO has an associated down counting timer that will use this regis - er as the start value. The down counting starts when a command is loaded into the FIFO. The timer counts down every 4 DRAM cy - les. When the counter reaches zero, the entry is popped from the FIFO. All the counters are frozen, if a C/A Parity or CRC er - or occurs before the counter reaches zero. The counter is reset to 0, after all the commands in the FIFO are retried. Recomme - ded(minimum) values: - Only C/A Parity is enabled. RoundUp((PHY Command Latency(DRAM CLK) + CAL + RDIMM delay + tPAR_ALERT_ON - max + tPAR_UNKNOWN + PHY Alert Latency(DRAM CLK) + board delay) / 4) + 2 - Both C/A Parity and CRC is enabled/ Only CRC is en - bled. RoundUp((PHY Command Latency(DRAM CLK) + CAL + RDIMM delay + WL + 5(BL10)+ tCRC_ALERT.max + PHY Alert Latency(DRAM CLK) - + board delay) / 4) + 2 Note 1: All value (e.g. tPAR_ALERT_ON) should be in terms of DRAM Clock and round up Note 2: Board de - ay(Command/Alert_n) should be considered. Note 3: Use the worst case(longer) value for PHY Latencies/Board delay Note 4: The - ecommended values are minimum value to be set. For mode detail, See 'Calculation of FIFO Depth' section. Max value can be set - to this register is defined below: - MEMC_BURST_LENGTH == 16 Full bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH- - Full bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Half bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_D - PTH-4 Half bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-6 Quarter bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CM - _FIFO_DEPTH-8 Quarter bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-12 - MEMC_BURST_LENGTH != 16 Full bus Mode (C - C=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-1 Full bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mo - e (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Quarte - bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-4 Quarter bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEP - H-6 Values of 0, 1 and 2 are illegal.*/ +/* +* Indicates the maximum duration in number of DRAM clock cycles for which + * a command should be held in the Command Retry FIFO before it is popped o + * ut. Every location in the Command Retry FIFO has an associated down coun + * ting timer that will use this register as the start value. The down coun + * ting starts when a command is loaded into the FIFO. The timer counts dow + * n every 4 DRAM cycles. When the counter reaches zero, the entry is poppe + * d from the FIFO. All the counters are frozen, if a C/A Parity or CRC err + * or occurs before the counter reaches zero. The counter is reset to 0, af + * ter all the commands in the FIFO are retried. Recommended(minimum) value + * s: - Only C/A Parity is enabled. RoundUp((PHY Command Latency(DRAM CLK) + * + CAL + RDIMM delay + tPAR_ALERT_ON.max + tPAR_UNKNOWN + PHY Alert Laten + * cy(DRAM CLK) + board delay) / 4) + 2 - Both C/A Parity and CRC is enable + * d/ Only CRC is enabled. RoundUp((PHY Command Latency(DRAM CLK) + CAL + R + * DIMM delay + WL + 5(BL10)+ tCRC_ALERT.max + PHY Alert Latency(DRAM CLK) + * + board delay) / 4) + 2 Note 1: All value (e.g. tPAR_ALERT_ON) should be + * in terms of DRAM Clock and round up Note 2: Board delay(Command/Alert_n + * ) should be considered. Note 3: Use the worst case(longer) value for PHY + * Latencies/Board delay Note 4: The Recommended values are minimum value + * to be set. For mode detail, See 'Calculation of FIFO Depth' section. Max + * value can be set to this register is defined below: - MEMC_BURST_LENGTH + * == 16 Full bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 + * Full bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Half b + * us Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-4 Half bus Mod + * e (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-6 Quarter bus Mode (C + * RC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-8 Quarter bus Mode (CRC= + * ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-12 - MEMC_BURST_LENGTH != 16 + * Full bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-1 Full + * bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mod + * e (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mode (CRC + * =ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Quarter bus Mode (CRC=OFF + * ) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-4 Quarter bus Mode (CRC=ON) Ma + * x value = UMCTL2_RETRY_CMD_FIFO_DEPTH-6 Values of 0, 1 and 2 are illegal + * . +*/ #undef DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_DEFVAL #undef DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_SHIFT #undef DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_MASK -#define DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_DEFVAL 0x0030050C -#define DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_SHIFT 0 -#define DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_MASK 0x0000003FU +#define DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_DEFVAL 0x0030050C +#define DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_SHIFT 0 +#define DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_MASK 0x0000003FU -/*If lower bit is enabled the SDRAM initialization routine is skipped. The upper bit decides what state the controller starts u - in when reset is removed - 00 - SDRAM Intialization routine is run after power-up - 01 - SDRAM Intialization routine is skip - ed after power-up. Controller starts up in Normal Mode - 11 - SDRAM Intialization routine is skipped after power-up. Controll - r starts up in Self-refresh Mode - 10 - SDRAM Intialization routine is run after power-up. Note: The only 2'b00 is supported - or LPDDR4 in this version of the uMCTL2.*/ +/* +* If lower bit is enabled the SDRAM initialization routine is skipped. The + * upper bit decides what state the controller starts up in when reset is + * removed - 00 - SDRAM Intialization routine is run after power-up - 01 - + * SDRAM Intialization routine is skipped after power-up. Controller starts + * up in Normal Mode - 11 - SDRAM Intialization routine is skipped after p + * ower-up. Controller starts up in Self-refresh Mode - 10 - SDRAM Intializ + * ation routine is run after power-up. Note: The only 2'b00 is supported f + * or LPDDR4 in this version of the uMCTL2. +*/ #undef DDRC_INIT0_SKIP_DRAM_INIT_DEFVAL #undef DDRC_INIT0_SKIP_DRAM_INIT_SHIFT #undef DDRC_INIT0_SKIP_DRAM_INIT_MASK -#define DDRC_INIT0_SKIP_DRAM_INIT_DEFVAL 0x0002004E -#define DDRC_INIT0_SKIP_DRAM_INIT_SHIFT 30 -#define DDRC_INIT0_SKIP_DRAM_INIT_MASK 0xC0000000U +#define DDRC_INIT0_SKIP_DRAM_INIT_DEFVAL 0x0002004E +#define DDRC_INIT0_SKIP_DRAM_INIT_SHIFT 30 +#define DDRC_INIT0_SKIP_DRAM_INIT_MASK 0xC0000000U -/*Cycles to wait after driving CKE high to start the SDRAM initialization sequence. Unit: 1024 clocks. DDR2 typically requires - 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2/LPDDR3 typically requires this to be pr - grammed for a delay of 200 us. LPDDR4 typically requires this to be programmed for a delay of 2 us. For configurations with M - MC_FREQ_RATIO=2, program this to JEDEC spec value divided by 2, and round it up to next integer value.*/ +/* +* Cycles to wait after driving CKE high to start the SDRAM initialization + * sequence. Unit: 1024 clocks. DDR2 typically requires a 400 ns delay, req + * uiring this value to be programmed to 2 at all clock speeds. LPDDR2/LPDD + * R3 typically requires this to be programmed for a delay of 200 us. LPDDR + * 4 typically requires this to be programmed for a delay of 2 us. For conf + * igurations with MEMC_FREQ_RATIO=2, program this to JEDEC spec value divi + * ded by 2, and round it up to next integer value. +*/ #undef DDRC_INIT0_POST_CKE_X1024_DEFVAL #undef DDRC_INIT0_POST_CKE_X1024_SHIFT #undef DDRC_INIT0_POST_CKE_X1024_MASK -#define DDRC_INIT0_POST_CKE_X1024_DEFVAL 0x0002004E -#define DDRC_INIT0_POST_CKE_X1024_SHIFT 16 -#define DDRC_INIT0_POST_CKE_X1024_MASK 0x03FF0000U +#define DDRC_INIT0_POST_CKE_X1024_DEFVAL 0x0002004E +#define DDRC_INIT0_POST_CKE_X1024_SHIFT 16 +#define DDRC_INIT0_POST_CKE_X1024_MASK 0x03FF0000U -/*Cycles to wait after reset before driving CKE high to start the SDRAM initialization sequence. Unit: 1024 clock cycles. DDR2 - pecifications typically require this to be programmed for a delay of >= 200 us. LPDDR2/LPDDR3: tINIT1 of 100 ns (min) LPDDR4: - tINIT3 of 2 ms (min) For configurations with MEMC_FREQ_RATIO=2, program this to JEDEC spec value divided by 2, and round it u - to next integer value.*/ +/* +* Cycles to wait after reset before driving CKE high to start the SDRAM in + * itialization sequence. Unit: 1024 clock cycles. DDR2 specifications typi + * cally require this to be programmed for a delay of >= 200 us. LPDDR2/LPD + * DR3: tINIT1 of 100 ns (min) LPDDR4: tINIT3 of 2 ms (min) For configurati + * ons with MEMC_FREQ_RATIO=2, program this to JEDEC spec value divided by + * 2, and round it up to next integer value. +*/ #undef DDRC_INIT0_PRE_CKE_X1024_DEFVAL #undef DDRC_INIT0_PRE_CKE_X1024_SHIFT #undef DDRC_INIT0_PRE_CKE_X1024_MASK -#define DDRC_INIT0_PRE_CKE_X1024_DEFVAL 0x0002004E -#define DDRC_INIT0_PRE_CKE_X1024_SHIFT 0 -#define DDRC_INIT0_PRE_CKE_X1024_MASK 0x00000FFFU +#define DDRC_INIT0_PRE_CKE_X1024_DEFVAL 0x0002004E +#define DDRC_INIT0_PRE_CKE_X1024_SHIFT 0 +#define DDRC_INIT0_PRE_CKE_X1024_MASK 0x00000FFFU -/*Number of cycles to assert SDRAM reset signal during init sequence. This is only present for designs supporting DDR3, DDR4 or - LPDDR4 devices. For use with a DDR PHY, this should be set to a minimum of 1*/ +/* +* Number of cycles to assert SDRAM reset signal during init sequence. This + * is only present for designs supporting DDR3, DDR4 or LPDDR4 devices. Fo + * r use with a DDR PHY, this should be set to a minimum of 1 +*/ #undef DDRC_INIT1_DRAM_RSTN_X1024_DEFVAL #undef DDRC_INIT1_DRAM_RSTN_X1024_SHIFT #undef DDRC_INIT1_DRAM_RSTN_X1024_MASK -#define DDRC_INIT1_DRAM_RSTN_X1024_DEFVAL 0x00000000 -#define DDRC_INIT1_DRAM_RSTN_X1024_SHIFT 16 -#define DDRC_INIT1_DRAM_RSTN_X1024_MASK 0x01FF0000U +#define DDRC_INIT1_DRAM_RSTN_X1024_DEFVAL 0x00000000 +#define DDRC_INIT1_DRAM_RSTN_X1024_SHIFT 16 +#define DDRC_INIT1_DRAM_RSTN_X1024_MASK 0x01FF0000U -/*Cycles to wait after completing the SDRAM initialization sequence before starting the dynamic scheduler. Unit: Counts of a gl - bal timer that pulses every 32 clock cycles. There is no known specific requirement for this; it may be set to zero.*/ +/* +* Cycles to wait after completing the SDRAM initialization sequence before + * starting the dynamic scheduler. Unit: Counts of a global timer that pul + * ses every 32 clock cycles. There is no known specific requirement for th + * is; it may be set to zero. +*/ #undef DDRC_INIT1_FINAL_WAIT_X32_DEFVAL #undef DDRC_INIT1_FINAL_WAIT_X32_SHIFT #undef DDRC_INIT1_FINAL_WAIT_X32_MASK -#define DDRC_INIT1_FINAL_WAIT_X32_DEFVAL 0x00000000 -#define DDRC_INIT1_FINAL_WAIT_X32_SHIFT 8 -#define DDRC_INIT1_FINAL_WAIT_X32_MASK 0x00007F00U +#define DDRC_INIT1_FINAL_WAIT_X32_DEFVAL 0x00000000 +#define DDRC_INIT1_FINAL_WAIT_X32_SHIFT 8 +#define DDRC_INIT1_FINAL_WAIT_X32_MASK 0x00007F00U -/*Wait period before driving the OCD complete command to SDRAM. Unit: Counts of a global timer that pulses every 32 clock cycle - . There is no known specific requirement for this; it may be set to zero.*/ +/* +* Wait period before driving the OCD complete command to SDRAM. Unit: Coun + * ts of a global timer that pulses every 32 clock cycles. There is no know + * n specific requirement for this; it may be set to zero. +*/ #undef DDRC_INIT1_PRE_OCD_X32_DEFVAL #undef DDRC_INIT1_PRE_OCD_X32_SHIFT #undef DDRC_INIT1_PRE_OCD_X32_MASK -#define DDRC_INIT1_PRE_OCD_X32_DEFVAL 0x00000000 -#define DDRC_INIT1_PRE_OCD_X32_SHIFT 0 -#define DDRC_INIT1_PRE_OCD_X32_MASK 0x0000000FU +#define DDRC_INIT1_PRE_OCD_X32_DEFVAL 0x00000000 +#define DDRC_INIT1_PRE_OCD_X32_SHIFT 0 +#define DDRC_INIT1_PRE_OCD_X32_MASK 0x0000000FU -/*Idle time after the reset command, tINIT4. Present only in designs configured to support LPDDR2. Unit: 32 clock cycles.*/ +/* +* Idle time after the reset command, tINIT4. Present only in designs confi + * gured to support LPDDR2. Unit: 32 clock cycles. +*/ #undef DDRC_INIT2_IDLE_AFTER_RESET_X32_DEFVAL #undef DDRC_INIT2_IDLE_AFTER_RESET_X32_SHIFT #undef DDRC_INIT2_IDLE_AFTER_RESET_X32_MASK -#define DDRC_INIT2_IDLE_AFTER_RESET_X32_DEFVAL 0x00000D05 -#define DDRC_INIT2_IDLE_AFTER_RESET_X32_SHIFT 8 -#define DDRC_INIT2_IDLE_AFTER_RESET_X32_MASK 0x0000FF00U +#define DDRC_INIT2_IDLE_AFTER_RESET_X32_DEFVAL 0x00000D05 +#define DDRC_INIT2_IDLE_AFTER_RESET_X32_SHIFT 8 +#define DDRC_INIT2_IDLE_AFTER_RESET_X32_MASK 0x0000FF00U -/*Time to wait after the first CKE high, tINIT2. Present only in designs configured to support LPDDR2/LPDDR3. Unit: 1 clock cyc - e. LPDDR2/LPDDR3 typically requires 5 x tCK delay.*/ +/* +* Time to wait after the first CKE high, tINIT2. Present only in designs c + * onfigured to support LPDDR2/LPDDR3. Unit: 1 clock cycle. LPDDR2/LPDDR3 t + * ypically requires 5 x tCK delay. +*/ #undef DDRC_INIT2_MIN_STABLE_CLOCK_X1_DEFVAL #undef DDRC_INIT2_MIN_STABLE_CLOCK_X1_SHIFT #undef DDRC_INIT2_MIN_STABLE_CLOCK_X1_MASK -#define DDRC_INIT2_MIN_STABLE_CLOCK_X1_DEFVAL 0x00000D05 -#define DDRC_INIT2_MIN_STABLE_CLOCK_X1_SHIFT 0 -#define DDRC_INIT2_MIN_STABLE_CLOCK_X1_MASK 0x0000000FU +#define DDRC_INIT2_MIN_STABLE_CLOCK_X1_DEFVAL 0x00000D05 +#define DDRC_INIT2_MIN_STABLE_CLOCK_X1_SHIFT 0 +#define DDRC_INIT2_MIN_STABLE_CLOCK_X1_MASK 0x0000000FU -/*DDR2: Value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The uMCTL2 sets this bit appropriately - DDR3/DDR4: Value loaded into MR0 register. mDDR: Value to write to MR register. LPDDR2/LPDDR3/LPDDR4 - Value to write to MR1 - register*/ +/* +* DDR2: Value to write to MR register. Bit 8 is for DLL and the setting he + * re is ignored. The uMCTL2 sets this bit appropriately. DDR3/DDR4: Value + * loaded into MR0 register. mDDR: Value to write to MR register. LPDDR2/LP + * DDR3/LPDDR4 - Value to write to MR1 register +*/ #undef DDRC_INIT3_MR_DEFVAL #undef DDRC_INIT3_MR_SHIFT #undef DDRC_INIT3_MR_MASK -#define DDRC_INIT3_MR_DEFVAL 0x00000510 -#define DDRC_INIT3_MR_SHIFT 16 -#define DDRC_INIT3_MR_MASK 0xFFFF0000U +#define DDRC_INIT3_MR_DEFVAL 0x00000510 +#define DDRC_INIT3_MR_SHIFT 16 +#define DDRC_INIT3_MR_MASK 0xFFFF0000U -/*DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setting in this register is ignored. The uMCTL2 sets those - bits appropriately. DDR3/DDR4: Value to write to MR1 register Set bit 7 to 0. If PHY-evaluation mode training is enabled, thi - bit is set appropriately by the uMCTL2 during write leveling. mDDR: Value to write to EMR register. LPDDR2/LPDDR3/LPDDR4 - V - lue to write to MR2 register*/ +/* +* DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setti + * ng in this register is ignored. The uMCTL2 sets those bits appropriately + * . DDR3/DDR4: Value to write to MR1 register Set bit 7 to 0. If PHY-evalu + * ation mode training is enabled, this bit is set appropriately by the uMC + * TL2 during write leveling. mDDR: Value to write to EMR register. LPDDR2/ + * LPDDR3/LPDDR4 - Value to write to MR2 register +*/ #undef DDRC_INIT3_EMR_DEFVAL #undef DDRC_INIT3_EMR_SHIFT #undef DDRC_INIT3_EMR_MASK -#define DDRC_INIT3_EMR_DEFVAL 0x00000510 -#define DDRC_INIT3_EMR_SHIFT 0 -#define DDRC_INIT3_EMR_MASK 0x0000FFFFU +#define DDRC_INIT3_EMR_DEFVAL 0x00000510 +#define DDRC_INIT3_EMR_SHIFT 0 +#define DDRC_INIT3_EMR_MASK 0x0000FFFFU -/*DDR2: Value to write to EMR2 register. DDR3/DDR4: Value to write to MR2 register LPDDR2/LPDDR3/LPDDR4: Value to write to MR3 - egister mDDR: Unused*/ +/* +* DDR2: Value to write to EMR2 register. DDR3/DDR4: Value to write to MR2 + * register LPDDR2/LPDDR3/LPDDR4: Value to write to MR3 register mDDR: Unus + * ed +*/ #undef DDRC_INIT4_EMR2_DEFVAL #undef DDRC_INIT4_EMR2_SHIFT #undef DDRC_INIT4_EMR2_MASK -#define DDRC_INIT4_EMR2_DEFVAL 0x00000000 -#define DDRC_INIT4_EMR2_SHIFT 16 -#define DDRC_INIT4_EMR2_MASK 0xFFFF0000U +#define DDRC_INIT4_EMR2_DEFVAL 0x00000000 +#define DDRC_INIT4_EMR2_SHIFT 16 +#define DDRC_INIT4_EMR2_MASK 0xFFFF0000U -/*DDR2: Value to write to EMR3 register. DDR3/DDR4: Value to write to MR3 register mDDR/LPDDR2/LPDDR3: Unused LPDDR4: Value to - rite to MR13 register*/ +/* +* DDR2: Value to write to EMR3 register. DDR3/DDR4: Value to write to MR3 + * register mDDR/LPDDR2/LPDDR3: Unused LPDDR4: Value to write to MR13 regis + * ter +*/ #undef DDRC_INIT4_EMR3_DEFVAL #undef DDRC_INIT4_EMR3_SHIFT #undef DDRC_INIT4_EMR3_MASK -#define DDRC_INIT4_EMR3_DEFVAL 0x00000000 -#define DDRC_INIT4_EMR3_SHIFT 0 -#define DDRC_INIT4_EMR3_MASK 0x0000FFFFU +#define DDRC_INIT4_EMR3_DEFVAL 0x00000000 +#define DDRC_INIT4_EMR3_SHIFT 0 +#define DDRC_INIT4_EMR3_MASK 0x0000FFFFU -/*ZQ initial calibration, tZQINIT. Present only in designs configured to support DDR3 or DDR4 or LPDDR2/LPDDR3. Unit: 32 clock - ycles. DDR3 typically requires 512 clocks. DDR4 requires 1024 clocks. LPDDR2/LPDDR3 requires 1 us.*/ +/* +* ZQ initial calibration, tZQINIT. Present only in designs configured to s + * upport DDR3 or DDR4 or LPDDR2/LPDDR3. Unit: 32 clock cycles. DDR3 typica + * lly requires 512 clocks. DDR4 requires 1024 clocks. LPDDR2/LPDDR3 requir + * es 1 us. +*/ #undef DDRC_INIT5_DEV_ZQINIT_X32_DEFVAL #undef DDRC_INIT5_DEV_ZQINIT_X32_SHIFT #undef DDRC_INIT5_DEV_ZQINIT_X32_MASK -#define DDRC_INIT5_DEV_ZQINIT_X32_DEFVAL 0x00100004 -#define DDRC_INIT5_DEV_ZQINIT_X32_SHIFT 16 -#define DDRC_INIT5_DEV_ZQINIT_X32_MASK 0x00FF0000U +#define DDRC_INIT5_DEV_ZQINIT_X32_DEFVAL 0x00100004 +#define DDRC_INIT5_DEV_ZQINIT_X32_SHIFT 16 +#define DDRC_INIT5_DEV_ZQINIT_X32_MASK 0x00FF0000U -/*Maximum duration of the auto initialization, tINIT5. Present only in designs configured to support LPDDR2/LPDDR3. LPDDR2/LPDD - 3 typically requires 10 us.*/ +/* +* Maximum duration of the auto initialization, tINIT5. Present only in des + * igns configured to support LPDDR2/LPDDR3. LPDDR2/LPDDR3 typically requir + * es 10 us. +*/ #undef DDRC_INIT5_MAX_AUTO_INIT_X1024_DEFVAL #undef DDRC_INIT5_MAX_AUTO_INIT_X1024_SHIFT #undef DDRC_INIT5_MAX_AUTO_INIT_X1024_MASK -#define DDRC_INIT5_MAX_AUTO_INIT_X1024_DEFVAL 0x00100004 -#define DDRC_INIT5_MAX_AUTO_INIT_X1024_SHIFT 0 -#define DDRC_INIT5_MAX_AUTO_INIT_X1024_MASK 0x000003FFU +#define DDRC_INIT5_MAX_AUTO_INIT_X1024_DEFVAL 0x00100004 +#define DDRC_INIT5_MAX_AUTO_INIT_X1024_SHIFT 0 +#define DDRC_INIT5_MAX_AUTO_INIT_X1024_MASK 0x000003FFU -/*DDR4- Value to be loaded into SDRAM MR4 registers. Used in DDR4 designs only.*/ +/* +* DDR4- Value to be loaded into SDRAM MR4 registers. Used in DDR4 designs + * only. +*/ #undef DDRC_INIT6_MR4_DEFVAL #undef DDRC_INIT6_MR4_SHIFT #undef DDRC_INIT6_MR4_MASK -#define DDRC_INIT6_MR4_DEFVAL 0x00000000 -#define DDRC_INIT6_MR4_SHIFT 16 -#define DDRC_INIT6_MR4_MASK 0xFFFF0000U +#define DDRC_INIT6_MR4_DEFVAL 0x00000000 +#define DDRC_INIT6_MR4_SHIFT 16 +#define DDRC_INIT6_MR4_MASK 0xFFFF0000U -/*DDR4- Value to be loaded into SDRAM MR5 registers. Used in DDR4 designs only.*/ +/* +* DDR4- Value to be loaded into SDRAM MR5 registers. Used in DDR4 designs + * only. +*/ #undef DDRC_INIT6_MR5_DEFVAL #undef DDRC_INIT6_MR5_SHIFT #undef DDRC_INIT6_MR5_MASK -#define DDRC_INIT6_MR5_DEFVAL 0x00000000 -#define DDRC_INIT6_MR5_SHIFT 0 -#define DDRC_INIT6_MR5_MASK 0x0000FFFFU +#define DDRC_INIT6_MR5_DEFVAL 0x00000000 +#define DDRC_INIT6_MR5_SHIFT 0 +#define DDRC_INIT6_MR5_MASK 0x0000FFFFU -/*DDR4- Value to be loaded into SDRAM MR6 registers. Used in DDR4 designs only.*/ +/* +* DDR4- Value to be loaded into SDRAM MR6 registers. Used in DDR4 designs + * only. +*/ #undef DDRC_INIT7_MR6_DEFVAL #undef DDRC_INIT7_MR6_SHIFT #undef DDRC_INIT7_MR6_MASK -#define DDRC_INIT7_MR6_DEFVAL -#define DDRC_INIT7_MR6_SHIFT 16 -#define DDRC_INIT7_MR6_MASK 0xFFFF0000U +#define DDRC_INIT7_MR6_DEFVAL +#define DDRC_INIT7_MR6_SHIFT 16 +#define DDRC_INIT7_MR6_MASK 0xFFFF0000U -/*Disabling Address Mirroring for BG bits. When this is set to 1, BG0 and BG1 are NOT swapped even if Address Mirroring is enab - ed. This will be required for DDR4 DIMMs with x16 devices. - 1 - BG0 and BG1 are NOT swapped. - 0 - BG0 and BG1 are swapped i - address mirroring is enabled.*/ +/* +* Disabling Address Mirroring for BG bits. When this is set to 1, BG0 and + * BG1 are NOT swapped even if Address Mirroring is enabled. This will be r + * equired for DDR4 DIMMs with x16 devices. - 1 - BG0 and BG1 are NOT swapp + * ed. - 0 - BG0 and BG1 are swapped if address mirroring is enabled. +*/ #undef DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_DEFVAL #undef DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_SHIFT #undef DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_MASK -#define DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_DEFVAL 0x00000000 -#define DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_SHIFT 5 -#define DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_MASK 0x00000020U +#define DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_DEFVAL 0x00000000 +#define DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_SHIFT 5 +#define DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_MASK 0x00000020U -/*Enable for BG1 bit of MRS command. BG1 bit of the mode register address is specified as RFU (Reserved for Future Use) and mus - be programmed to 0 during MRS. In case where DRAMs which do not have BG1 are attached and both the CA parity and the Output - nversion are enabled, this must be set to 0, so that the calculation of CA parity will not include BG1 bit. Note: This has no - effect on the address of any other memory accesses, or of software-driven mode register accesses. If address mirroring is ena - led, this is applied to BG1 of even ranks and BG0 of odd ranks. - 1 - Enabled - 0 - Disabled*/ +/* +* Enable for BG1 bit of MRS command. BG1 bit of the mode register address + * is specified as RFU (Reserved for Future Use) and must be programmed to + * 0 during MRS. In case where DRAMs which do not have BG1 are attached and + * both the CA parity and the Output Inversion are enabled, this must be s + * et to 0, so that the calculation of CA parity will not include BG1 bit. + * Note: This has no effect on the address of any other memory accesses, or + * of software-driven mode register accesses. If address mirroring is enab + * led, this is applied to BG1 of even ranks and BG0 of odd ranks. - 1 - En + * abled - 0 - Disabled +*/ #undef DDRC_DIMMCTL_MRS_BG1_EN_DEFVAL #undef DDRC_DIMMCTL_MRS_BG1_EN_SHIFT #undef DDRC_DIMMCTL_MRS_BG1_EN_MASK -#define DDRC_DIMMCTL_MRS_BG1_EN_DEFVAL 0x00000000 -#define DDRC_DIMMCTL_MRS_BG1_EN_SHIFT 4 -#define DDRC_DIMMCTL_MRS_BG1_EN_MASK 0x00000010U +#define DDRC_DIMMCTL_MRS_BG1_EN_DEFVAL 0x00000000 +#define DDRC_DIMMCTL_MRS_BG1_EN_SHIFT 4 +#define DDRC_DIMMCTL_MRS_BG1_EN_MASK 0x00000010U -/*Enable for A17 bit of MRS command. A17 bit of the mode register address is specified as RFU (Reserved for Future Use) and mus - be programmed to 0 during MRS. In case where DRAMs which do not have A17 are attached and the Output Inversion are enabled, - his must be set to 0, so that the calculation of CA parity will not include A17 bit. Note: This has no effect on the address - f any other memory accesses, or of software-driven mode register accesses. - 1 - Enabled - 0 - Disabled*/ +/* +* Enable for A17 bit of MRS command. A17 bit of the mode register address + * is specified as RFU (Reserved for Future Use) and must be programmed to + * 0 during MRS. In case where DRAMs which do not have A17 are attached and + * the Output Inversion are enabled, this must be set to 0, so that the ca + * lculation of CA parity will not include A17 bit. Note: This has no effec + * t on the address of any other memory accesses, or of software-driven mod + * e register accesses. - 1 - Enabled - 0 - Disabled +*/ #undef DDRC_DIMMCTL_MRS_A17_EN_DEFVAL #undef DDRC_DIMMCTL_MRS_A17_EN_SHIFT #undef DDRC_DIMMCTL_MRS_A17_EN_MASK -#define DDRC_DIMMCTL_MRS_A17_EN_DEFVAL 0x00000000 -#define DDRC_DIMMCTL_MRS_A17_EN_SHIFT 3 -#define DDRC_DIMMCTL_MRS_A17_EN_MASK 0x00000008U +#define DDRC_DIMMCTL_MRS_A17_EN_DEFVAL 0x00000000 +#define DDRC_DIMMCTL_MRS_A17_EN_SHIFT 3 +#define DDRC_DIMMCTL_MRS_A17_EN_MASK 0x00000008U -/*Output Inversion Enable (for DDR4 RDIMM implementations only). DDR4 RDIMM implements the Output Inversion feature by default, - which means that the following address, bank address and bank group bits of B-side DRAMs are inverted: A3-A9, A11, A13, A17, - A0-BA1, BG0-BG1. Setting this bit ensures that, for mode register accesses generated by the uMCTL2 during the automatic initi - lization routine and enabling of a particular DDR4 feature, separate A-side and B-side mode register accesses are generated. - or B-side mode register accesses, these bits are inverted within the uMCTL2 to compensate for this RDIMM inversion. Note: Thi - has no effect on the address of any other memory accesses, or of software-driven mode register accesses. - 1 - Implement out - ut inversion for B-side DRAMs. - 0 - Do not implement output inversion for B-side DRAMs.*/ +/* +* Output Inversion Enable (for DDR4 RDIMM implementations only). DDR4 RDIM + * M implements the Output Inversion feature by default, which means that t + * he following address, bank address and bank group bits of B-side DRAMs a + * re inverted: A3-A9, A11, A13, A17, BA0-BA1, BG0-BG1. Setting this bit en + * sures that, for mode register accesses generated by the uMCTL2 during th + * e automatic initialization routine and enabling of a particular DDR4 fea + * ture, separate A-side and B-side mode register accesses are generated. F + * or B-side mode register accesses, these bits are inverted within the uMC + * TL2 to compensate for this RDIMM inversion. Note: This has no effect on + * the address of any other memory accesses, or of software-driven mode reg + * ister accesses. - 1 - Implement output inversion for B-side DRAMs. - 0 - + * Do not implement output inversion for B-side DRAMs. +*/ #undef DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_DEFVAL #undef DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_SHIFT #undef DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_MASK -#define DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_DEFVAL 0x00000000 -#define DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_SHIFT 2 -#define DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_MASK 0x00000004U +#define DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_DEFVAL 0x00000000 +#define DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_SHIFT 2 +#define DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_MASK 0x00000004U -/*Address Mirroring Enable (for multi-rank UDIMM implementations and multi-rank DDR4 RDIMM implementations). Some UDIMMs and DD - 4 RDIMMs implement address mirroring for odd ranks, which means that the following address, bank address and bank group bits - re swapped: (A3, A4), (A5, A6), (A7, A8), (BA0, BA1) and also (A11, A13), (BG0, BG1) for the DDR4. Setting this bit ensures t - at, for mode register accesses during the automatic initialization routine, these bits are swapped within the uMCTL2 to compe - sate for this UDIMM/RDIMM swapping. In addition to the automatic initialization routine, in case of DDR4 UDIMM/RDIMM, they ar - swapped during the automatic MRS access to enable/disable of a particular DDR4 feature. Note: This has no effect on the addr - ss of any other memory accesses, or of software-driven mode register accesses. This is not supported for mDDR, LPDDR2, LPDDR3 - or LPDDR4 SDRAMs. Note: In case of x16 DDR4 DIMMs, BG1 output of MRS for the odd ranks is same as BG0 because BG1 is invalid, - hence dimm_dis_bg_mirroring register must be set to 1. - 1 - For odd ranks, implement address mirroring for MRS commands to d - ring initialization and for any automatic DDR4 MRS commands (to be used if UDIMM/RDIMM implements address mirroring) - 0 - Do - not implement address mirroring*/ +/* +* Address Mirroring Enable (for multi-rank UDIMM implementations and multi + * -rank DDR4 RDIMM implementations). Some UDIMMs and DDR4 RDIMMs implement + * address mirroring for odd ranks, which means that the following address + * , bank address and bank group bits are swapped: (A3, A4), (A5, A6), (A7, + * A8), (BA0, BA1) and also (A11, A13), (BG0, BG1) for the DDR4. Setting t + * his bit ensures that, for mode register accesses during the automatic in + * itialization routine, these bits are swapped within the uMCTL2 to compen + * sate for this UDIMM/RDIMM swapping. In addition to the automatic initial + * ization routine, in case of DDR4 UDIMM/RDIMM, they are swapped during th + * e automatic MRS access to enable/disable of a particular DDR4 feature. N + * ote: This has no effect on the address of any other memory accesses, or + * of software-driven mode register accesses. This is not supported for mDD + * R, LPDDR2, LPDDR3 or LPDDR4 SDRAMs. Note: In case of x16 DDR4 DIMMs, BG1 + * output of MRS for the odd ranks is same as BG0 because BG1 is invalid, + * hence dimm_dis_bg_mirroring register must be set to 1. - 1 - For odd ran + * ks, implement address mirroring for MRS commands to during initializatio + * n and for any automatic DDR4 MRS commands (to be used if UDIMM/RDIMM imp + * lements address mirroring) - 0 - Do not implement address mirroring +*/ #undef DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_DEFVAL #undef DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_SHIFT #undef DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_MASK -#define DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_DEFVAL 0x00000000 -#define DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_SHIFT 1 -#define DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_MASK 0x00000002U +#define DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_DEFVAL 0x00000000 +#define DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_SHIFT 1 +#define DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_MASK 0x00000002U -/*Staggering enable for multi-rank accesses (for multi-rank UDIMM and RDIMM implementations only). This is not supported for mD - R, LPDDR2, LPDDR3 or LPDDR4 SDRAMs. Note: Even if this bit is set it does not take care of software driven MR commands (via M - CTRL0/MRCTRL1), where software is responsible to send them to seperate ranks as appropriate. - 1 - (DDR4) Send MRS commands t - each ranks seperately - 1 - (non-DDR4) Send all commands to even and odd ranks seperately - 0 - Do not stagger accesses*/ +/* +* Staggering enable for multi-rank accesses (for multi-rank UDIMM and RDIM + * M implementations only). This is not supported for mDDR, LPDDR2, LPDDR3 + * or LPDDR4 SDRAMs. Note: Even if this bit is set it does not take care of + * software driven MR commands (via MRCTRL0/MRCTRL1), where software is re + * sponsible to send them to seperate ranks as appropriate. - 1 - (DDR4) Se + * nd MRS commands to each ranks seperately - 1 - (non-DDR4) Send all comma + * nds to even and odd ranks seperately - 0 - Do not stagger accesses +*/ #undef DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_DEFVAL #undef DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_SHIFT #undef DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_MASK -#define DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_DEFVAL 0x00000000 -#define DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_SHIFT 0 -#define DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_MASK 0x00000001U +#define DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_DEFVAL 0x00000000 +#define DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_SHIFT 0 +#define DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_MASK 0x00000001U -/*Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecuti - e writes to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This value should c - nsider both PHY requirement and ODT requirement. - PHY requirement: tphy_wrcsgap + 1 (see PHY databook for value of tphy_wrcs - ap) If CRC feature is enabled, should be increased by 1. If write preamble is set to 2tCK(DDR4/LPDDR4 only), should be increa - ed by 1. If write postamble is set to 1.5tCK(LPDDR4 only), should be increased by 1. - ODT requirement: The value programmed - n this register takes care of the ODT switch off timing requirement when switching ranks during writes. For LPDDR4, the requi - ement is ODTLoff - ODTLon - BL/2 + 1 For configurations with MEMC_FREQ_RATIO=1, program this to the larger of PHY requirement - or ODT requirement. For configurations with MEMC_FREQ_RATIO=2, program this to the larger value divided by two and round it u - to the next integer.*/ +/* +* Only present for multi-rank configurations. Indicates the number of cloc + * ks of gap in data responses when performing consecutive writes to differ + * ent ranks. This is used to switch the delays in the PHY to match the ran + * k requirements. This value should consider both PHY requirement and ODT + * requirement. - PHY requirement: tphy_wrcsgap + 1 (see PHY databook for v + * alue of tphy_wrcsgap) If CRC feature is enabled, should be increased by + * 1. If write preamble is set to 2tCK(DDR4/LPDDR4 only), should be increas + * ed by 1. If write postamble is set to 1.5tCK(LPDDR4 only), should be inc + * reased by 1. - ODT requirement: The value programmed in this register ta + * kes care of the ODT switch off timing requirement when switching ranks d + * uring writes. For LPDDR4, the requirement is ODTLoff - ODTLon - BL/2 + 1 + * For configurations with MEMC_FREQ_RATIO=1, program this to the larger o + * f PHY requirement or ODT requirement. For configurations with MEMC_FREQ_ + * RATIO=2, program this to the larger value divided by two and round it up + * to the next integer. +*/ #undef DDRC_RANKCTL_DIFF_RANK_WR_GAP_DEFVAL #undef DDRC_RANKCTL_DIFF_RANK_WR_GAP_SHIFT #undef DDRC_RANKCTL_DIFF_RANK_WR_GAP_MASK -#define DDRC_RANKCTL_DIFF_RANK_WR_GAP_DEFVAL 0x0000066F -#define DDRC_RANKCTL_DIFF_RANK_WR_GAP_SHIFT 8 -#define DDRC_RANKCTL_DIFF_RANK_WR_GAP_MASK 0x00000F00U +#define DDRC_RANKCTL_DIFF_RANK_WR_GAP_DEFVAL 0x0000066F +#define DDRC_RANKCTL_DIFF_RANK_WR_GAP_SHIFT 8 +#define DDRC_RANKCTL_DIFF_RANK_WR_GAP_MASK 0x00000F00U -/*Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecuti - e reads to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This value should co - sider both PHY requirement and ODT requirement. - PHY requirement: tphy_rdcsgap + 1 (see PHY databook for value of tphy_rdcsg - p) If read preamble is set to 2tCK(DDR4/LPDDR4 only), should be increased by 1. If read postamble is set to 1.5tCK(LPDDR4 onl - ), should be increased by 1. - ODT requirement: The value programmed in this register takes care of the ODT switch off timing - requirement when switching ranks during reads. For configurations with MEMC_FREQ_RATIO=1, program this to the larger of PHY r - quirement or ODT requirement. For configurations with MEMC_FREQ_RATIO=2, program this to the larger value divided by two and - ound it up to the next integer.*/ +/* +* Only present for multi-rank configurations. Indicates the number of cloc + * ks of gap in data responses when performing consecutive reads to differe + * nt ranks. This is used to switch the delays in the PHY to match the rank + * requirements. This value should consider both PHY requirement and ODT r + * equirement. - PHY requirement: tphy_rdcsgap + 1 (see PHY databook for va + * lue of tphy_rdcsgap) If read preamble is set to 2tCK(DDR4/LPDDR4 only), + * should be increased by 1. If read postamble is set to 1.5tCK(LPDDR4 only + * ), should be increased by 1. - ODT requirement: The value programmed in + * this register takes care of the ODT switch off timing requirement when s + * witching ranks during reads. For configurations with MEMC_FREQ_RATIO=1, + * program this to the larger of PHY requirement or ODT requirement. For co + * nfigurations with MEMC_FREQ_RATIO=2, program this to the larger value di + * vided by two and round it up to the next integer. +*/ #undef DDRC_RANKCTL_DIFF_RANK_RD_GAP_DEFVAL #undef DDRC_RANKCTL_DIFF_RANK_RD_GAP_SHIFT #undef DDRC_RANKCTL_DIFF_RANK_RD_GAP_MASK -#define DDRC_RANKCTL_DIFF_RANK_RD_GAP_DEFVAL 0x0000066F -#define DDRC_RANKCTL_DIFF_RANK_RD_GAP_SHIFT 4 -#define DDRC_RANKCTL_DIFF_RANK_RD_GAP_MASK 0x000000F0U +#define DDRC_RANKCTL_DIFF_RANK_RD_GAP_DEFVAL 0x0000066F +#define DDRC_RANKCTL_DIFF_RANK_RD_GAP_SHIFT 4 +#define DDRC_RANKCTL_DIFF_RANK_RD_GAP_MASK 0x000000F0U -/*Only present for multi-rank configurations. Background: Reads to the same rank can be performed back-to-back. Reads to differ - nt ranks require additional gap dictated by the register RANKCTL.diff_rank_rd_gap. This is to avoid possible data bus content - on as well as to give PHY enough time to switch the delay when changing ranks. The uMCTL2 arbitrates for bus access on a cycl - -by-cycle basis; therefore after a read is scheduled, there are few clock cycles (determined by the value on RANKCTL.diff_ran - _rd_gap register) in which only reads from the same rank are eligible to be scheduled. This prevents reads from other ranks f - om having fair access to the data bus. This parameter represents the maximum number of reads that can be scheduled consecutiv - ly to the same rank. After this number is reached, a delay equal to RANKCTL.diff_rank_rd_gap is inserted by the scheduler to - llow all ranks a fair opportunity to be scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fair - ess. This feature can be DISABLED by setting this register to 0. When set to 0, the Controller will stay on the same rank as - ong as commands are available for it. Minimum programmable value is 0 (feature disabled) and maximum programmable value is 0x - . FOR PERFORMANCE ONLY.*/ +/* +* Only present for multi-rank configurations. Background: Reads to the sam + * e rank can be performed back-to-back. Reads to different ranks require a + * dditional gap dictated by the register RANKCTL.diff_rank_rd_gap. This is + * to avoid possible data bus contention as well as to give PHY enough tim + * e to switch the delay when changing ranks. The uMCTL2 arbitrates for bus + * access on a cycle-by-cycle basis; therefore after a read is scheduled, + * there are few clock cycles (determined by the value on RANKCTL.diff_rank + * _rd_gap register) in which only reads from the same rank are eligible to + * be scheduled. This prevents reads from other ranks from having fair acc + * ess to the data bus. This parameter represents the maximum number of rea + * ds that can be scheduled consecutively to the same rank. After this numb + * er is reached, a delay equal to RANKCTL.diff_rank_rd_gap is inserted by + * the scheduler to allow all ranks a fair opportunity to be scheduled. Hig + * her numbers increase bandwidth utilization, lower numbers increase fairn + * ess. This feature can be DISABLED by setting this register to 0. When se + * t to 0, the Controller will stay on the same rank as long as commands ar + * e available for it. Minimum programmable value is 0 (feature disabled) a + * nd maximum programmable value is 0xF. FOR PERFORMANCE ONLY. +*/ #undef DDRC_RANKCTL_MAX_RANK_RD_DEFVAL #undef DDRC_RANKCTL_MAX_RANK_RD_SHIFT #undef DDRC_RANKCTL_MAX_RANK_RD_MASK -#define DDRC_RANKCTL_MAX_RANK_RD_DEFVAL 0x0000066F -#define DDRC_RANKCTL_MAX_RANK_RD_SHIFT 0 -#define DDRC_RANKCTL_MAX_RANK_RD_MASK 0x0000000FU +#define DDRC_RANKCTL_MAX_RANK_RD_DEFVAL 0x0000066F +#define DDRC_RANKCTL_MAX_RANK_RD_SHIFT 0 +#define DDRC_RANKCTL_MAX_RANK_RD_MASK 0x0000000FU -/*Minimum time between write and precharge to same bank. Unit: Clocks Specifications: WL + BL/2 + tWR = approximately 8 cycles - 15 ns = 14 clocks @400MHz and less for lower frequencies where: - WL = write latency - BL = burst length. This must match th - value programmed in the BL bit of the mode register to the SDRAM. BST (burst terminate) is not supported at present. - tWR = - Write recovery time. This comes directly from the SDRAM specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 for this - arameter. For configurations with MEMC_FREQ_RATIO=2, 1T mode, divide the above value by 2. No rounding up. For configurations - with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, divide the above value by 2 and round it up to the next integer value.*/ +/* +* Minimum time between write and precharge to same bank. Unit: Clocks Spec + * ifications: WL + BL/2 + tWR = approximately 8 cycles + 15 ns = 14 clocks + * @400MHz and less for lower frequencies where: - WL = write latency - BL + * = burst length. This must match the value programmed in the BL bit of t + * he mode register to the SDRAM. BST (burst terminate) is not supported at + * present. - tWR = Write recovery time. This comes directly from the SDRA + * M specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 for this p + * arameter. For configurations with MEMC_FREQ_RATIO=2, 1T mode, divide the + * above value by 2. No rounding up. For configurations with MEMC_FREQ_RAT + * IO=2, 2T mode or LPDDR4 mode, divide the above value by 2 and round it u + * p to the next integer value. +*/ #undef DDRC_DRAMTMG0_WR2PRE_DEFVAL #undef DDRC_DRAMTMG0_WR2PRE_SHIFT #undef DDRC_DRAMTMG0_WR2PRE_MASK -#define DDRC_DRAMTMG0_WR2PRE_DEFVAL 0x0F101B0F -#define DDRC_DRAMTMG0_WR2PRE_SHIFT 24 -#define DDRC_DRAMTMG0_WR2PRE_MASK 0x7F000000U +#define DDRC_DRAMTMG0_WR2PRE_DEFVAL 0x0F101B0F +#define DDRC_DRAMTMG0_WR2PRE_SHIFT 24 +#define DDRC_DRAMTMG0_WR2PRE_MASK 0x7F000000U -/*tFAW Valid only when 8 or more banks(or banks x bank groups) are present. In 8-bank design, at most 4 banks must be activated - in a rolling window of tFAW cycles. For configurations with MEMC_FREQ_RATIO=2, program this to (tFAW/2) and round up to next - nteger value. In a 4-bank design, set this register to 0x1 independent of the MEMC_FREQ_RATIO configuration. Unit: Clocks*/ +/* +* tFAW Valid only when 8 or more banks(or banks x bank groups) are present + * . In 8-bank design, at most 4 banks must be activated in a rolling windo + * w of tFAW cycles. For configurations with MEMC_FREQ_RATIO=2, program thi + * s to (tFAW/2) and round up to next integer value. In a 4-bank design, se + * t this register to 0x1 independent of the MEMC_FREQ_RATIO configuration. + * Unit: Clocks +*/ #undef DDRC_DRAMTMG0_T_FAW_DEFVAL #undef DDRC_DRAMTMG0_T_FAW_SHIFT #undef DDRC_DRAMTMG0_T_FAW_MASK -#define DDRC_DRAMTMG0_T_FAW_DEFVAL 0x0F101B0F -#define DDRC_DRAMTMG0_T_FAW_SHIFT 16 -#define DDRC_DRAMTMG0_T_FAW_MASK 0x003F0000U +#define DDRC_DRAMTMG0_T_FAW_DEFVAL 0x0F101B0F +#define DDRC_DRAMTMG0_T_FAW_SHIFT 16 +#define DDRC_DRAMTMG0_T_FAW_MASK 0x003F0000U -/*tRAS(max): Maximum time between activate and precharge to same bank. This is the maximum time that a page can be kept open Mi - imum value of this register is 1. Zero is invalid. For configurations with MEMC_FREQ_RATIO=2, program this to (tRAS(max)-1)/2 - No rounding up. Unit: Multiples of 1024 clocks.*/ +/* +* tRAS(max): Maximum time between activate and precharge to same bank. Thi + * s is the maximum time that a page can be kept open Minimum value of this + * register is 1. Zero is invalid. For configurations with MEMC_FREQ_RATIO + * =2, program this to (tRAS(max)-1)/2. No rounding up. Unit: Multiples of + * 1024 clocks. +*/ #undef DDRC_DRAMTMG0_T_RAS_MAX_DEFVAL #undef DDRC_DRAMTMG0_T_RAS_MAX_SHIFT #undef DDRC_DRAMTMG0_T_RAS_MAX_MASK -#define DDRC_DRAMTMG0_T_RAS_MAX_DEFVAL 0x0F101B0F -#define DDRC_DRAMTMG0_T_RAS_MAX_SHIFT 8 -#define DDRC_DRAMTMG0_T_RAS_MAX_MASK 0x00007F00U +#define DDRC_DRAMTMG0_T_RAS_MAX_DEFVAL 0x0F101B0F +#define DDRC_DRAMTMG0_T_RAS_MAX_SHIFT 8 +#define DDRC_DRAMTMG0_T_RAS_MAX_MASK 0x00007F00U -/*tRAS(min): Minimum time between activate and precharge to the same bank. For configurations with MEMC_FREQ_RATIO=2, 1T mode, - rogram this to tRAS(min)/2. No rounding up. For configurations with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, program this t - (tRAS(min)/2) and round it up to the next integer value. Unit: Clocks*/ +/* +* tRAS(min): Minimum time between activate and precharge to the same bank. + * For configurations with MEMC_FREQ_RATIO=2, 1T mode, program this to tRA + * S(min)/2. No rounding up. For configurations with MEMC_FREQ_RATIO=2, 2T + * mode or LPDDR4 mode, program this to (tRAS(min)/2) and round it up to th + * e next integer value. Unit: Clocks +*/ #undef DDRC_DRAMTMG0_T_RAS_MIN_DEFVAL #undef DDRC_DRAMTMG0_T_RAS_MIN_SHIFT #undef DDRC_DRAMTMG0_T_RAS_MIN_MASK -#define DDRC_DRAMTMG0_T_RAS_MIN_DEFVAL 0x0F101B0F -#define DDRC_DRAMTMG0_T_RAS_MIN_SHIFT 0 -#define DDRC_DRAMTMG0_T_RAS_MIN_MASK 0x0000003FU +#define DDRC_DRAMTMG0_T_RAS_MIN_DEFVAL 0x0F101B0F +#define DDRC_DRAMTMG0_T_RAS_MIN_SHIFT 0 +#define DDRC_DRAMTMG0_T_RAS_MIN_MASK 0x0000003FU -/*tXP: Minimum time after power-down exit to any operation. For DDR3, this should be programmed to tXPDLL if slow powerdown exi - is selected in MR0[12]. If C/A parity for DDR4 is used, set to (tXP+PL) instead. For configurations with MEMC_FREQ_RATIO=2, - rogram this to (tXP/2) and round it up to the next integer value. Units: Clocks*/ +/* +* tXP: Minimum time after power-down exit to any operation. For DDR3, this + * should be programmed to tXPDLL if slow powerdown exit is selected in MR + * 0[12]. If C/A parity for DDR4 is used, set to (tXP+PL) instead. For conf + * igurations with MEMC_FREQ_RATIO=2, program this to (tXP/2) and round it + * up to the next integer value. Units: Clocks +*/ #undef DDRC_DRAMTMG1_T_XP_DEFVAL #undef DDRC_DRAMTMG1_T_XP_SHIFT #undef DDRC_DRAMTMG1_T_XP_MASK -#define DDRC_DRAMTMG1_T_XP_DEFVAL 0x00080414 -#define DDRC_DRAMTMG1_T_XP_SHIFT 16 -#define DDRC_DRAMTMG1_T_XP_MASK 0x001F0000U +#define DDRC_DRAMTMG1_T_XP_DEFVAL 0x00080414 +#define DDRC_DRAMTMG1_T_XP_SHIFT 16 +#define DDRC_DRAMTMG1_T_XP_MASK 0x001F0000U -/*tRTP: Minimum time from read to precharge of same bank. - DDR2: tAL + BL/2 + max(tRTP, 2) - 2 - DDR3: tAL + max (tRTP, 4) - D - R4: Max of following two equations: tAL + max (tRTP, 4) or, RL + BL/2 - tRP. - mDDR: BL/2 - LPDDR2: Depends on if it's LPDDR2 - S2 or LPDDR2-S4: LPDDR2-S2: BL/2 + tRTP - 1. LPDDR2-S4: BL/2 + max(tRTP,2) - 2. - LPDDR3: BL/2 + max(tRTP,4) - 4 - LPDDR4: BL - 2 + max(tRTP,8) - 8 For configurations with MEMC_FREQ_RATIO=2, 1T mode, divide the above value by 2. No rounding up. For conf - gurations with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, divide the above value by 2 and round it up to the next integer val - e. Unit: Clocks.*/ +/* +* tRTP: Minimum time from read to precharge of same bank. - DDR2: tAL + BL + * /2 + max(tRTP, 2) - 2 - DDR3: tAL + max (tRTP, 4) - DDR4: Max of followi + * ng two equations: tAL + max (tRTP, 4) or, RL + BL/2 - tRP. - mDDR: BL/2 + * - LPDDR2: Depends on if it's LPDDR2-S2 or LPDDR2-S4: LPDDR2-S2: BL/2 + t + * RTP - 1. LPDDR2-S4: BL/2 + max(tRTP,2) - 2. - LPDDR3: BL/2 + max(tRTP,4) + * - 4 - LPDDR4: BL/2 + max(tRTP,8) - 8 For configurations with MEMC_FREQ_ + * RATIO=2, 1T mode, divide the above value by 2. No rounding up. For confi + * gurations with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, divide the abo + * ve value by 2 and round it up to the next integer value. Unit: Clocks. +*/ #undef DDRC_DRAMTMG1_RD2PRE_DEFVAL #undef DDRC_DRAMTMG1_RD2PRE_SHIFT #undef DDRC_DRAMTMG1_RD2PRE_MASK -#define DDRC_DRAMTMG1_RD2PRE_DEFVAL 0x00080414 -#define DDRC_DRAMTMG1_RD2PRE_SHIFT 8 -#define DDRC_DRAMTMG1_RD2PRE_MASK 0x00001F00U +#define DDRC_DRAMTMG1_RD2PRE_DEFVAL 0x00080414 +#define DDRC_DRAMTMG1_RD2PRE_SHIFT 8 +#define DDRC_DRAMTMG1_RD2PRE_MASK 0x00001F00U -/*tRC: Minimum time between activates to same bank. For configurations with MEMC_FREQ_RATIO=2, program this to (tRC/2) and roun - up to next integer value. Unit: Clocks.*/ +/* +* tRC: Minimum time between activates to same bank. For configurations wit + * h MEMC_FREQ_RATIO=2, program this to (tRC/2) and round up to next intege + * r value. Unit: Clocks. +*/ #undef DDRC_DRAMTMG1_T_RC_DEFVAL #undef DDRC_DRAMTMG1_T_RC_SHIFT #undef DDRC_DRAMTMG1_T_RC_MASK -#define DDRC_DRAMTMG1_T_RC_DEFVAL 0x00080414 -#define DDRC_DRAMTMG1_T_RC_SHIFT 0 -#define DDRC_DRAMTMG1_T_RC_MASK 0x0000007FU +#define DDRC_DRAMTMG1_T_RC_DEFVAL 0x00080414 +#define DDRC_DRAMTMG1_T_RC_SHIFT 0 +#define DDRC_DRAMTMG1_T_RC_MASK 0x0000007FU -/*Set to WL Time from write command to write data on SDRAM interface. This must be set to WL. For mDDR, it should normally be s - t to 1. Note that, depending on the PHY, if using RDIMM, it may be necessary to use a value of WL + 1 to compensate for the e - tra cycle of latency through the RDIMM For configurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above - equation by 2, and round it up to next integer. This register field is not required for DDR2 and DDR3 (except if MEMC_TRAININ - is set), as the DFI read and write latencies defined in DFITMG0 and DFITMG1 are sufficient for those protocols Unit: clocks*/ +/* +* Set to WL Time from write command to write data on SDRAM interface. This + * must be set to WL. For mDDR, it should normally be set to 1. Note that, + * depending on the PHY, if using RDIMM, it may be necessary to use a valu + * e of WL + 1 to compensate for the extra cycle of latency through the RDI + * MM For configurations with MEMC_FREQ_RATIO=2, divide the value calculate + * d using the above equation by 2, and round it up to next integer. This r + * egister field is not required for DDR2 and DDR3 (except if MEMC_TRAINING + * is set), as the DFI read and write latencies defined in DFITMG0 and DFI + * TMG1 are sufficient for those protocols Unit: clocks +*/ #undef DDRC_DRAMTMG2_WRITE_LATENCY_DEFVAL #undef DDRC_DRAMTMG2_WRITE_LATENCY_SHIFT #undef DDRC_DRAMTMG2_WRITE_LATENCY_MASK -#define DDRC_DRAMTMG2_WRITE_LATENCY_DEFVAL 0x0305060D -#define DDRC_DRAMTMG2_WRITE_LATENCY_SHIFT 24 -#define DDRC_DRAMTMG2_WRITE_LATENCY_MASK 0x3F000000U +#define DDRC_DRAMTMG2_WRITE_LATENCY_DEFVAL 0x0305060D +#define DDRC_DRAMTMG2_WRITE_LATENCY_SHIFT 24 +#define DDRC_DRAMTMG2_WRITE_LATENCY_MASK 0x3F000000U -/*Set to RL Time from read command to read data on SDRAM interface. This must be set to RL. Note that, depending on the PHY, if - using RDIMM, it mat be necessary to use a value of RL + 1 to compensate for the extra cycle of latency through the RDIMM For - onfigurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next inte - er. This register field is not required for DDR2 and DDR3 (except if MEMC_TRAINING is set), as the DFI read and write latenci - s defined in DFITMG0 and DFITMG1 are sufficient for those protocols Unit: clocks*/ +/* +* Set to RL Time from read command to read data on SDRAM interface. This m + * ust be set to RL. Note that, depending on the PHY, if using RDIMM, it ma + * t be necessary to use a value of RL + 1 to compensate for the extra cycl + * e of latency through the RDIMM For configurations with MEMC_FREQ_RATIO=2 + * , divide the value calculated using the above equation by 2, and round i + * t up to next integer. This register field is not required for DDR2 and D + * DR3 (except if MEMC_TRAINING is set), as the DFI read and write latencie + * s defined in DFITMG0 and DFITMG1 are sufficient for those protocols Unit + * : clocks +*/ #undef DDRC_DRAMTMG2_READ_LATENCY_DEFVAL #undef DDRC_DRAMTMG2_READ_LATENCY_SHIFT #undef DDRC_DRAMTMG2_READ_LATENCY_MASK -#define DDRC_DRAMTMG2_READ_LATENCY_DEFVAL 0x0305060D -#define DDRC_DRAMTMG2_READ_LATENCY_SHIFT 16 -#define DDRC_DRAMTMG2_READ_LATENCY_MASK 0x003F0000U +#define DDRC_DRAMTMG2_READ_LATENCY_DEFVAL 0x0305060D +#define DDRC_DRAMTMG2_READ_LATENCY_SHIFT 16 +#define DDRC_DRAMTMG2_READ_LATENCY_MASK 0x003F0000U -/*DDR2/3/mDDR: RL + BL/2 + 2 - WL DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL LPDDR2/LPDDR3: RL + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL - PDDR4(DQ ODT is Disabled): RL + BL/2 + RU(tDQSCKmax/tCK) + WR_PREAMBLE + RD_POSTAMBLE - WL LPDDR4(DQ ODT is Enabled) : RL + B - /2 + RU(tDQSCKmax/tCK) + RD_POSTAMBLE - ODTLon - RU(tODTon(min)/tCK) Minimum time from read command to write command. Include - time for bus turnaround and all per-bank, per-rank, and global constraints. Unit: Clocks. Where: - WL = write latency - BL = - urst length. This must match the value programmed in the BL bit of the mode register to the SDRAM - RL = read latency = CAS l - tency - WR_PREAMBLE = write preamble. This is unique to DDR4 and LPDDR4. - RD_POSTAMBLE = read postamble. This is unique to L - DDR4. For LPDDR2/LPDDR3/LPDDR4, if derating is enabled (DERATEEN.derate_enable=1), derated tDQSCKmax should be used. For conf - gurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next integer.*/ +/* +* DDR2/3/mDDR: RL + BL/2 + 2 - WL DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL L + * PDDR2/LPDDR3: RL + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL LPDDR4(DQ ODT is Di + * sabled): RL + BL/2 + RU(tDQSCKmax/tCK) + WR_PREAMBLE + RD_POSTAMBLE - WL + * LPDDR4(DQ ODT is Enabled) : RL + BL/2 + RU(tDQSCKmax/tCK) + RD_POSTAMBL + * E - ODTLon - RU(tODTon(min)/tCK) Minimum time from read command to write + * command. Include time for bus turnaround and all per-bank, per-rank, an + * d global constraints. Unit: Clocks. Where: - WL = write latency - BL = b + * urst length. This must match the value programmed in the BL bit of the m + * ode register to the SDRAM - RL = read latency = CAS latency - WR_PREAMBL + * E = write preamble. This is unique to DDR4 and LPDDR4. - RD_POSTAMBLE = + * read postamble. This is unique to LPDDR4. For LPDDR2/LPDDR3/LPDDR4, if d + * erating is enabled (DERATEEN.derate_enable=1), derated tDQSCKmax should + * be used. For configurations with MEMC_FREQ_RATIO=2, divide the value cal + * culated using the above equation by 2, and round it up to next integer. +*/ #undef DDRC_DRAMTMG2_RD2WR_DEFVAL #undef DDRC_DRAMTMG2_RD2WR_SHIFT #undef DDRC_DRAMTMG2_RD2WR_MASK -#define DDRC_DRAMTMG2_RD2WR_DEFVAL 0x0305060D -#define DDRC_DRAMTMG2_RD2WR_SHIFT 8 -#define DDRC_DRAMTMG2_RD2WR_MASK 0x00003F00U +#define DDRC_DRAMTMG2_RD2WR_DEFVAL 0x0305060D +#define DDRC_DRAMTMG2_RD2WR_SHIFT 8 +#define DDRC_DRAMTMG2_RD2WR_MASK 0x00003F00U -/*DDR4: CWL + PL + BL/2 + tWTR_L Others: CWL + BL/2 + tWTR In DDR4, minimum time from write command to read command for same ba - k group. In others, minimum time from write command to read command. Includes time for bus turnaround, recovery times, and al - per-bank, per-rank, and global constraints. Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity latency - BL = burs - length. This must match the value programmed in the BL bit of the mode register to the SDRAM - tWTR_L = internal write to re - d command delay for same bank group. This comes directly from the SDRAM specification. - tWTR = internal write to read comman - delay. This comes directly from the SDRAM specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 operation. For configu - ations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next integer.*/ +/* +* DDR4: CWL + PL + BL/2 + tWTR_L Others: CWL + BL/2 + tWTR In DDR4, minimu + * m time from write command to read command for same bank group. In others + * , minimum time from write command to read command. Includes time for bus + * turnaround, recovery times, and all per-bank, per-rank, and global cons + * traints. Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity la + * tency - BL = burst length. This must match the value programmed in the B + * L bit of the mode register to the SDRAM - tWTR_L = internal write to rea + * d command delay for same bank group. This comes directly from the SDRAM + * specification. - tWTR = internal write to read command delay. This comes + * directly from the SDRAM specification. Add one extra cycle for LPDDR2/L + * PDDR3/LPDDR4 operation. For configurations with MEMC_FREQ_RATIO=2, divid + * e the value calculated using the above equation by 2, and round it up to + * next integer. +*/ #undef DDRC_DRAMTMG2_WR2RD_DEFVAL #undef DDRC_DRAMTMG2_WR2RD_SHIFT #undef DDRC_DRAMTMG2_WR2RD_MASK -#define DDRC_DRAMTMG2_WR2RD_DEFVAL 0x0305060D -#define DDRC_DRAMTMG2_WR2RD_SHIFT 0 -#define DDRC_DRAMTMG2_WR2RD_MASK 0x0000003FU +#define DDRC_DRAMTMG2_WR2RD_DEFVAL 0x0305060D +#define DDRC_DRAMTMG2_WR2RD_SHIFT 0 +#define DDRC_DRAMTMG2_WR2RD_MASK 0x0000003FU -/*Time to wait after a mode register write or read (MRW or MRR). Present only in designs configured to support LPDDR2, LPDDR3 o - LPDDR4. LPDDR2 typically requires value of 5. LPDDR3 typically requires value of 10. LPDDR4: Set this to the larger of tMRW - nd tMRWCKEL. For LPDDR2, this register is used for the time from a MRW/MRR to all other commands. For LDPDR3, this register i - used for the time from a MRW/MRR to a MRW/MRR.*/ +/* +* Time to wait after a mode register write or read (MRW or MRR). Present o + * nly in designs configured to support LPDDR2, LPDDR3 or LPDDR4. LPDDR2 ty + * pically requires value of 5. LPDDR3 typically requires value of 10. LPDD + * R4: Set this to the larger of tMRW and tMRWCKEL. For LPDDR2, this regist + * er is used for the time from a MRW/MRR to all other commands. For LDPDR3 + * , this register is used for the time from a MRW/MRR to a MRW/MRR. +*/ #undef DDRC_DRAMTMG3_T_MRW_DEFVAL #undef DDRC_DRAMTMG3_T_MRW_SHIFT #undef DDRC_DRAMTMG3_T_MRW_MASK -#define DDRC_DRAMTMG3_T_MRW_DEFVAL 0x0050400C -#define DDRC_DRAMTMG3_T_MRW_SHIFT 20 -#define DDRC_DRAMTMG3_T_MRW_MASK 0x3FF00000U +#define DDRC_DRAMTMG3_T_MRW_DEFVAL 0x0050400C +#define DDRC_DRAMTMG3_T_MRW_SHIFT 20 +#define DDRC_DRAMTMG3_T_MRW_MASK 0x3FF00000U -/*tMRD: Cycles to wait after a mode register write or read. Depending on the connected SDRAM, tMRD represents: DDR2/mDDR: Time - rom MRS to any command DDR3/4: Time from MRS to MRS command LPDDR2: not used LPDDR3/4: Time from MRS to non-MRS command For c - nfigurations with MEMC_FREQ_RATIO=2, program this to (tMRD/2) and round it up to the next integer value. If C/A parity for DD - 4 is used, set to tMRD_PAR(tMOD+PL) instead.*/ +/* +* tMRD: Cycles to wait after a mode register write or read. Depending on t + * he connected SDRAM, tMRD represents: DDR2/mDDR: Time from MRS to any com + * mand DDR3/4: Time from MRS to MRS command LPDDR2: not used LPDDR3/4: Tim + * e from MRS to non-MRS command For configurations with MEMC_FREQ_RATIO=2, + * program this to (tMRD/2) and round it up to the next integer value. If + * C/A parity for DDR4 is used, set to tMRD_PAR(tMOD+PL) instead. +*/ #undef DDRC_DRAMTMG3_T_MRD_DEFVAL #undef DDRC_DRAMTMG3_T_MRD_SHIFT #undef DDRC_DRAMTMG3_T_MRD_MASK -#define DDRC_DRAMTMG3_T_MRD_DEFVAL 0x0050400C -#define DDRC_DRAMTMG3_T_MRD_SHIFT 12 -#define DDRC_DRAMTMG3_T_MRD_MASK 0x0003F000U +#define DDRC_DRAMTMG3_T_MRD_DEFVAL 0x0050400C +#define DDRC_DRAMTMG3_T_MRD_SHIFT 12 +#define DDRC_DRAMTMG3_T_MRD_MASK 0x0003F000U -/*tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode command and following non-load mode command. If C/A pari - y for DDR4 is used, set to tMOD_PAR(tMOD+PL) instead. Set to tMOD if MEMC_FREQ_RATIO=1, or tMOD/2 (rounded up to next integer - if MEMC_FREQ_RATIO=2. Note that if using RDIMM, depending on the PHY, it may be necessary to use a value of tMOD + 1 or (tMO - + 1)/2 to compensate for the extra cycle of latency applied to mode register writes by the RDIMM chip.*/ +/* +* tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode com + * mand and following non-load mode command. If C/A parity for DDR4 is used + * , set to tMOD_PAR(tMOD+PL) instead. Set to tMOD if MEMC_FREQ_RATIO=1, or + * tMOD/2 (rounded up to next integer) if MEMC_FREQ_RATIO=2. Note that if + * using RDIMM, depending on the PHY, it may be necessary to use a value of + * tMOD + 1 or (tMOD + 1)/2 to compensate for the extra cycle of latency a + * pplied to mode register writes by the RDIMM chip. +*/ #undef DDRC_DRAMTMG3_T_MOD_DEFVAL #undef DDRC_DRAMTMG3_T_MOD_SHIFT #undef DDRC_DRAMTMG3_T_MOD_MASK -#define DDRC_DRAMTMG3_T_MOD_DEFVAL 0x0050400C -#define DDRC_DRAMTMG3_T_MOD_SHIFT 0 -#define DDRC_DRAMTMG3_T_MOD_MASK 0x000003FFU +#define DDRC_DRAMTMG3_T_MOD_DEFVAL 0x0050400C +#define DDRC_DRAMTMG3_T_MOD_SHIFT 0 +#define DDRC_DRAMTMG3_T_MOD_MASK 0x000003FFU -/*tRCD - tAL: Minimum time from activate to read or write command to same bank. For configurations with MEMC_FREQ_RATIO=2, prog - am this to ((tRCD - tAL)/2) and round it up to the next integer value. Minimum value allowed for this register is 1, which im - lies minimum (tRCD - tAL) value to be 2 in configurations with MEMC_FREQ_RATIO=2. Unit: Clocks.*/ +/* +* tRCD - tAL: Minimum time from activate to read or write command to same + * bank. For configurations with MEMC_FREQ_RATIO=2, program this to ((tRCD + * - tAL)/2) and round it up to the next integer value. Minimum value allow + * ed for this register is 1, which implies minimum (tRCD - tAL) value to b + * e 2 in configurations with MEMC_FREQ_RATIO=2. Unit: Clocks. +*/ #undef DDRC_DRAMTMG4_T_RCD_DEFVAL #undef DDRC_DRAMTMG4_T_RCD_SHIFT #undef DDRC_DRAMTMG4_T_RCD_MASK -#define DDRC_DRAMTMG4_T_RCD_DEFVAL 0x05040405 -#define DDRC_DRAMTMG4_T_RCD_SHIFT 24 -#define DDRC_DRAMTMG4_T_RCD_MASK 0x1F000000U +#define DDRC_DRAMTMG4_T_RCD_DEFVAL 0x05040405 +#define DDRC_DRAMTMG4_T_RCD_SHIFT 24 +#define DDRC_DRAMTMG4_T_RCD_MASK 0x1F000000U -/*DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank group. Others: tCCD: This is the minimum - time between two reads or two writes. For configurations with MEMC_FREQ_RATIO=2, program this to (tCCD_L/2 or tCCD/2) and rou - d it up to the next integer value. Unit: clocks.*/ +/* +* DDR4: tCCD_L: This is the minimum time between two reads or two writes f + * or same bank group. Others: tCCD: This is the minimum time between two r + * eads or two writes. For configurations with MEMC_FREQ_RATIO=2, program t + * his to (tCCD_L/2 or tCCD/2) and round it up to the next integer value. U + * nit: clocks. +*/ #undef DDRC_DRAMTMG4_T_CCD_DEFVAL #undef DDRC_DRAMTMG4_T_CCD_SHIFT #undef DDRC_DRAMTMG4_T_CCD_MASK -#define DDRC_DRAMTMG4_T_CCD_DEFVAL 0x05040405 -#define DDRC_DRAMTMG4_T_CCD_SHIFT 16 -#define DDRC_DRAMTMG4_T_CCD_MASK 0x000F0000U +#define DDRC_DRAMTMG4_T_CCD_DEFVAL 0x05040405 +#define DDRC_DRAMTMG4_T_CCD_SHIFT 16 +#define DDRC_DRAMTMG4_T_CCD_MASK 0x000F0000U -/*DDR4: tRRD_L: Minimum time between activates from bank 'a' to bank 'b' for same bank group. Others: tRRD: Minimum time betwee - activates from bank 'a' to bank 'b'For configurations with MEMC_FREQ_RATIO=2, program this to (tRRD_L/2 or tRRD/2) and round - it up to the next integer value. Unit: Clocks.*/ +/* +* DDR4: tRRD_L: Minimum time between activates from bank 'a' to bank 'b' f + * or same bank group. Others: tRRD: Minimum time between activates from ba + * nk 'a' to bank 'b'For configurations with MEMC_FREQ_RATIO=2, program thi + * s to (tRRD_L/2 or tRRD/2) and round it up to the next integer value. Uni + * t: Clocks. +*/ #undef DDRC_DRAMTMG4_T_RRD_DEFVAL #undef DDRC_DRAMTMG4_T_RRD_SHIFT #undef DDRC_DRAMTMG4_T_RRD_MASK -#define DDRC_DRAMTMG4_T_RRD_DEFVAL 0x05040405 -#define DDRC_DRAMTMG4_T_RRD_SHIFT 8 -#define DDRC_DRAMTMG4_T_RRD_MASK 0x00000F00U +#define DDRC_DRAMTMG4_T_RRD_DEFVAL 0x05040405 +#define DDRC_DRAMTMG4_T_RRD_SHIFT 8 +#define DDRC_DRAMTMG4_T_RRD_MASK 0x00000F00U -/*tRP: Minimum time from precharge to activate of same bank. For MEMC_FREQ_RATIO=1 configurations, t_rp should be set to RoundU - (tRP/tCK). For MEMC_FREQ_RATIO=2 configurations, t_rp should be set to RoundDown(RoundUp(tRP/tCK)/2) + 1. For MEMC_FREQ_RATIO - 2 configurations in LPDDR4, t_rp should be set to RoundUp(RoundUp(tRP/tCK)/2). Unit: Clocks.*/ +/* +* tRP: Minimum time from precharge to activate of same bank. For MEMC_FREQ + * _RATIO=1 configurations, t_rp should be set to RoundUp(tRP/tCK). For MEM + * C_FREQ_RATIO=2 configurations, t_rp should be set to RoundDown(RoundUp(t + * RP/tCK)/2) + 1. For MEMC_FREQ_RATIO=2 configurations in LPDDR4, t_rp sho + * uld be set to RoundUp(RoundUp(tRP/tCK)/2). Unit: Clocks. +*/ #undef DDRC_DRAMTMG4_T_RP_DEFVAL #undef DDRC_DRAMTMG4_T_RP_SHIFT #undef DDRC_DRAMTMG4_T_RP_MASK -#define DDRC_DRAMTMG4_T_RP_DEFVAL 0x05040405 -#define DDRC_DRAMTMG4_T_RP_SHIFT 0 -#define DDRC_DRAMTMG4_T_RP_MASK 0x0000001FU +#define DDRC_DRAMTMG4_T_RP_DEFVAL 0x05040405 +#define DDRC_DRAMTMG4_T_RP_SHIFT 0 +#define DDRC_DRAMTMG4_T_RP_MASK 0x0000001FU -/*This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stab - e time before SRX. Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEH - DDR2: 1 - DDR3: tCKSRX - DDR4: - tCKSRX For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it up to next in - eger.*/ +/* +* This is the time before Self Refresh Exit that CK is maintained as a val + * id clock before issuing SRX. Specifies the clock stable time before SRX. + * Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCK + * EH - DDR2: 1 - DDR3: tCKSRX - DDR4: tCKSRX For configurations with MEMC_ + * FREQ_RATIO=2, program this to recommended value divided by two and round + * it up to next integer. +*/ #undef DDRC_DRAMTMG5_T_CKSRX_DEFVAL #undef DDRC_DRAMTMG5_T_CKSRX_SHIFT #undef DDRC_DRAMTMG5_T_CKSRX_MASK -#define DDRC_DRAMTMG5_T_CKSRX_DEFVAL 0x05050403 -#define DDRC_DRAMTMG5_T_CKSRX_SHIFT 24 -#define DDRC_DRAMTMG5_T_CKSRX_MASK 0x0F000000U +#define DDRC_DRAMTMG5_T_CKSRX_DEFVAL 0x05050403 +#define DDRC_DRAMTMG5_T_CKSRX_SHIFT 24 +#define DDRC_DRAMTMG5_T_CKSRX_MASK 0x0F000000U -/*This is the time after Self Refresh Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay afte - SRE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL - DDR2: 1 - DDR3: max (10 ns, 5 tCK) - DDR4: - ax (10 ns, 5 tCK) For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it up - to next integer.*/ +/* +* This is the time after Self Refresh Down Entry that CK is maintained as + * a valid clock. Specifies the clock disable delay after SRE. Recommended + * settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL - DDR2: 1 + * - DDR3: max (10 ns, 5 tCK) - DDR4: max (10 ns, 5 tCK) For configurations + * with MEMC_FREQ_RATIO=2, program this to recommended value divided by tw + * o and round it up to next integer. +*/ #undef DDRC_DRAMTMG5_T_CKSRE_DEFVAL #undef DDRC_DRAMTMG5_T_CKSRE_SHIFT #undef DDRC_DRAMTMG5_T_CKSRE_MASK -#define DDRC_DRAMTMG5_T_CKSRE_DEFVAL 0x05050403 -#define DDRC_DRAMTMG5_T_CKSRE_SHIFT 16 -#define DDRC_DRAMTMG5_T_CKSRE_MASK 0x000F0000U +#define DDRC_DRAMTMG5_T_CKSRE_DEFVAL 0x05050403 +#define DDRC_DRAMTMG5_T_CKSRE_SHIFT 16 +#define DDRC_DRAMTMG5_T_CKSRE_MASK 0x000F0000U -/*Minimum CKE low width for Self refresh or Self refresh power down entry to exit timing in memory clock cycles. Recommended se - tings: - mDDR: tRFC - LPDDR2: tCKESR - LPDDR3: tCKESR - LPDDR4: max(tCKELPD, tSR) - DDR2: tCKE - DDR3: tCKE + 1 - DDR4: tCKE - 1 For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it up to next intege - .*/ +/* +* Minimum CKE low width for Self refresh or Self refresh power down entry + * to exit timing in memory clock cycles. Recommended settings: - mDDR: tRF + * C - LPDDR2: tCKESR - LPDDR3: tCKESR - LPDDR4: max(tCKELPD, tSR) - DDR2: + * tCKE - DDR3: tCKE + 1 - DDR4: tCKE + 1 For configurations with MEMC_FREQ + * _RATIO=2, program this to recommended value divided by two and round it + * up to next integer. +*/ #undef DDRC_DRAMTMG5_T_CKESR_DEFVAL #undef DDRC_DRAMTMG5_T_CKESR_SHIFT #undef DDRC_DRAMTMG5_T_CKESR_MASK -#define DDRC_DRAMTMG5_T_CKESR_DEFVAL 0x05050403 -#define DDRC_DRAMTMG5_T_CKESR_SHIFT 8 -#define DDRC_DRAMTMG5_T_CKESR_MASK 0x00003F00U +#define DDRC_DRAMTMG5_T_CKESR_DEFVAL 0x05050403 +#define DDRC_DRAMTMG5_T_CKESR_SHIFT 8 +#define DDRC_DRAMTMG5_T_CKESR_MASK 0x00003F00U -/*Minimum number of cycles of CKE HIGH/LOW during power-down and self refresh. - LPDDR2/LPDDR3 mode: Set this to the larger of - CKE or tCKESR - LPDDR4 mode: Set this to the larger of tCKE, tCKELPD or tSR. - Non-LPDDR2/non-LPDDR3/non-LPDDR4 designs: Set - his to tCKE value. For configurations with MEMC_FREQ_RATIO=2, program this to (value described above)/2 and round it up to th - next integer value. Unit: Clocks.*/ +/* +* Minimum number of cycles of CKE HIGH/LOW during power-down and self refr + * esh. - LPDDR2/LPDDR3 mode: Set this to the larger of tCKE or tCKESR - LP + * DDR4 mode: Set this to the larger of tCKE, tCKELPD or tSR. - Non-LPDDR2/ + * non-LPDDR3/non-LPDDR4 designs: Set this to tCKE value. For configuration + * s with MEMC_FREQ_RATIO=2, program this to (value described above)/2 and + * round it up to the next integer value. Unit: Clocks. +*/ #undef DDRC_DRAMTMG5_T_CKE_DEFVAL #undef DDRC_DRAMTMG5_T_CKE_SHIFT #undef DDRC_DRAMTMG5_T_CKE_MASK -#define DDRC_DRAMTMG5_T_CKE_DEFVAL 0x05050403 -#define DDRC_DRAMTMG5_T_CKE_SHIFT 0 -#define DDRC_DRAMTMG5_T_CKE_MASK 0x0000001FU +#define DDRC_DRAMTMG5_T_CKE_DEFVAL 0x05050403 +#define DDRC_DRAMTMG5_T_CKE_SHIFT 0 +#define DDRC_DRAMTMG5_T_CKE_MASK 0x0000001FU -/*This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after - PDE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 For configurations with MEMC_FREQ_RATIO=2, program this to recom - ended value divided by two and round it up to next integer. This is only present for designs supporting mDDR or LPDDR2/LPDDR3 - devices.*/ +/* +* This is the time after Deep Power Down Entry that CK is maintained as a + * valid clock. Specifies the clock disable delay after DPDE. Recommended s + * ettings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 For configurations with MEMC_ + * FREQ_RATIO=2, program this to recommended value divided by two and round + * it up to next integer. This is only present for designs supporting mDDR + * or LPDDR2/LPDDR3 devices. +*/ #undef DDRC_DRAMTMG6_T_CKDPDE_DEFVAL #undef DDRC_DRAMTMG6_T_CKDPDE_SHIFT #undef DDRC_DRAMTMG6_T_CKDPDE_MASK -#define DDRC_DRAMTMG6_T_CKDPDE_DEFVAL 0x02020005 -#define DDRC_DRAMTMG6_T_CKDPDE_SHIFT 24 -#define DDRC_DRAMTMG6_T_CKDPDE_MASK 0x0F000000U +#define DDRC_DRAMTMG6_T_CKDPDE_DEFVAL 0x02020005 +#define DDRC_DRAMTMG6_T_CKDPDE_SHIFT 24 +#define DDRC_DRAMTMG6_T_CKDPDE_MASK 0x0F000000U -/*This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock - table time before DPDX. Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 For configurations with MEMC_FREQ_RATIO=2, pr - gram this to recommended value divided by two and round it up to next integer. This is only present for designs supporting mD - R or LPDDR2 devices.*/ +/* +* This is the time before Deep Power Down Exit that CK is maintained as a + * valid clock before issuing DPDX. Specifies the clock stable time before + * DPDX. Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 For config + * urations with MEMC_FREQ_RATIO=2, program this to recommended value divid + * ed by two and round it up to next integer. This is only present for desi + * gns supporting mDDR or LPDDR2 devices. +*/ #undef DDRC_DRAMTMG6_T_CKDPDX_DEFVAL #undef DDRC_DRAMTMG6_T_CKDPDX_SHIFT #undef DDRC_DRAMTMG6_T_CKDPDX_MASK -#define DDRC_DRAMTMG6_T_CKDPDX_DEFVAL 0x02020005 -#define DDRC_DRAMTMG6_T_CKDPDX_SHIFT 16 -#define DDRC_DRAMTMG6_T_CKDPDX_MASK 0x000F0000U +#define DDRC_DRAMTMG6_T_CKDPDX_DEFVAL 0x02020005 +#define DDRC_DRAMTMG6_T_CKDPDX_SHIFT 16 +#define DDRC_DRAMTMG6_T_CKDPDX_MASK 0x000F0000U -/*This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing Clock Stop Exit. Specifies the - lock stable time before next command after Clock Stop Exit. Recommended settings: - mDDR: 1 - LPDDR2: tXP + 2 - LPDDR3: tXP + - 2 - LPDDR4: tXP + 2 For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it - p to next integer. This is only present for designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices.*/ +/* +* This is the time before Clock Stop Exit that CK is maintained as a valid + * clock before issuing Clock Stop Exit. Specifies the clock stable time b + * efore next command after Clock Stop Exit. Recommended settings: - mDDR: + * 1 - LPDDR2: tXP + 2 - LPDDR3: tXP + 2 - LPDDR4: tXP + 2 For configuratio + * ns with MEMC_FREQ_RATIO=2, program this to recommended value divided by + * two and round it up to next integer. This is only present for designs su + * pporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices. +*/ #undef DDRC_DRAMTMG6_T_CKCSX_DEFVAL #undef DDRC_DRAMTMG6_T_CKCSX_SHIFT #undef DDRC_DRAMTMG6_T_CKCSX_MASK -#define DDRC_DRAMTMG6_T_CKCSX_DEFVAL 0x02020005 -#define DDRC_DRAMTMG6_T_CKCSX_SHIFT 0 -#define DDRC_DRAMTMG6_T_CKCSX_MASK 0x0000000FU +#define DDRC_DRAMTMG6_T_CKCSX_DEFVAL 0x02020005 +#define DDRC_DRAMTMG6_T_CKCSX_SHIFT 0 +#define DDRC_DRAMTMG6_T_CKCSX_MASK 0x0000000FU -/*This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. - ecommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL For configurations with MEMC_FREQ_RATIO=2, program t - is to recommended value divided by two and round it up to next integer. This is only present for designs supporting mDDR or L - DDR2/LPDDR3/LPDDR4 devices.*/ +/* +* This is the time after Power Down Entry that CK is maintained as a valid + * clock. Specifies the clock disable delay after PDE. Recommended setting + * s: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL For configuration + * s with MEMC_FREQ_RATIO=2, program this to recommended value divided by t + * wo and round it up to next integer. This is only present for designs sup + * porting mDDR or LPDDR2/LPDDR3/LPDDR4 devices. +*/ #undef DDRC_DRAMTMG7_T_CKPDE_DEFVAL #undef DDRC_DRAMTMG7_T_CKPDE_SHIFT #undef DDRC_DRAMTMG7_T_CKPDE_MASK -#define DDRC_DRAMTMG7_T_CKPDE_DEFVAL 0x00000202 -#define DDRC_DRAMTMG7_T_CKPDE_SHIFT 8 -#define DDRC_DRAMTMG7_T_CKPDE_MASK 0x00000F00U +#define DDRC_DRAMTMG7_T_CKPDE_DEFVAL 0x00000202 +#define DDRC_DRAMTMG7_T_CKPDE_SHIFT 8 +#define DDRC_DRAMTMG7_T_CKPDE_MASK 0x00000F00U -/*This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable - time before PDX. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: 2 For configurations with MEMC_FREQ_RATIO= - , program this to recommended value divided by two and round it up to next integer. This is only present for designs supporti - g mDDR or LPDDR2/LPDDR3/LPDDR4 devices.*/ +/* +* This is the time before Power Down Exit that CK is maintained as a valid + * clock before issuing PDX. Specifies the clock stable time before PDX. R + * ecommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: 2 For c + * onfigurations with MEMC_FREQ_RATIO=2, program this to recommended value + * divided by two and round it up to next integer. This is only present for + * designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices. +*/ #undef DDRC_DRAMTMG7_T_CKPDX_DEFVAL #undef DDRC_DRAMTMG7_T_CKPDX_SHIFT #undef DDRC_DRAMTMG7_T_CKPDX_MASK -#define DDRC_DRAMTMG7_T_CKPDX_DEFVAL 0x00000202 -#define DDRC_DRAMTMG7_T_CKPDX_SHIFT 0 -#define DDRC_DRAMTMG7_T_CKPDX_MASK 0x0000000FU +#define DDRC_DRAMTMG7_T_CKPDX_DEFVAL 0x00000202 +#define DDRC_DRAMTMG7_T_CKPDX_SHIFT 0 +#define DDRC_DRAMTMG7_T_CKPDX_MASK 0x0000000FU -/*tXS_FAST: Exit Self Refresh to ZQCL, ZQCS and MRS (only CL, WR, RTP and Geardown mode). For configurations with MEMC_FREQ_RAT - O=2, program this to the above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: Thi - is applicable to only ZQCL/ZQCS commands. Note: Ensure this is less than or equal to t_xs_x32.*/ +/* +* tXS_FAST: Exit Self Refresh to ZQCL, ZQCS and MRS (only CL, WR, RTP and + * Geardown mode). For configurations with MEMC_FREQ_RATIO=2, program this + * to the above value divided by 2 and round up to next integer value. Unit + * : Multiples of 32 clocks. Note: This is applicable to only ZQCL/ZQCS com + * mands. Note: Ensure this is less than or equal to t_xs_x32. +*/ #undef DDRC_DRAMTMG8_T_XS_FAST_X32_DEFVAL #undef DDRC_DRAMTMG8_T_XS_FAST_X32_SHIFT #undef DDRC_DRAMTMG8_T_XS_FAST_X32_MASK -#define DDRC_DRAMTMG8_T_XS_FAST_X32_DEFVAL 0x03034405 -#define DDRC_DRAMTMG8_T_XS_FAST_X32_SHIFT 24 -#define DDRC_DRAMTMG8_T_XS_FAST_X32_MASK 0x7F000000U +#define DDRC_DRAMTMG8_T_XS_FAST_X32_DEFVAL 0x03034405 +#define DDRC_DRAMTMG8_T_XS_FAST_X32_SHIFT 24 +#define DDRC_DRAMTMG8_T_XS_FAST_X32_MASK 0x7F000000U -/*tXS_ABORT: Exit Self Refresh to commands not requiring a locked DLL in Self Refresh Abort. For configurations with MEMC_FREQ_ - ATIO=2, program this to the above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: - nsure this is less than or equal to t_xs_x32.*/ +/* +* tXS_ABORT: Exit Self Refresh to commands not requiring a locked DLL in S + * elf Refresh Abort. For configurations with MEMC_FREQ_RATIO=2, program th + * is to the above value divided by 2 and round up to next integer value. U + * nit: Multiples of 32 clocks. Note: Ensure this is less than or equal to + * t_xs_x32. +*/ #undef DDRC_DRAMTMG8_T_XS_ABORT_X32_DEFVAL #undef DDRC_DRAMTMG8_T_XS_ABORT_X32_SHIFT #undef DDRC_DRAMTMG8_T_XS_ABORT_X32_MASK -#define DDRC_DRAMTMG8_T_XS_ABORT_X32_DEFVAL 0x03034405 -#define DDRC_DRAMTMG8_T_XS_ABORT_X32_SHIFT 16 -#define DDRC_DRAMTMG8_T_XS_ABORT_X32_MASK 0x007F0000U +#define DDRC_DRAMTMG8_T_XS_ABORT_X32_DEFVAL 0x03034405 +#define DDRC_DRAMTMG8_T_XS_ABORT_X32_SHIFT 16 +#define DDRC_DRAMTMG8_T_XS_ABORT_X32_MASK 0x007F0000U -/*tXSDLL: Exit Self Refresh to commands requiring a locked DLL. For configurations with MEMC_FREQ_RATIO=2, program this to the - bove value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: Used only for DDR2, DDR3 and - DR4 SDRAMs.*/ +/* +* tXSDLL: Exit Self Refresh to commands requiring a locked DLL. For config + * urations with MEMC_FREQ_RATIO=2, program this to the above value divided + * by 2 and round up to next integer value. Unit: Multiples of 32 clocks. + * Note: Used only for DDR2, DDR3 and DDR4 SDRAMs. +*/ #undef DDRC_DRAMTMG8_T_XS_DLL_X32_DEFVAL #undef DDRC_DRAMTMG8_T_XS_DLL_X32_SHIFT #undef DDRC_DRAMTMG8_T_XS_DLL_X32_MASK -#define DDRC_DRAMTMG8_T_XS_DLL_X32_DEFVAL 0x03034405 -#define DDRC_DRAMTMG8_T_XS_DLL_X32_SHIFT 8 -#define DDRC_DRAMTMG8_T_XS_DLL_X32_MASK 0x00007F00U +#define DDRC_DRAMTMG8_T_XS_DLL_X32_DEFVAL 0x03034405 +#define DDRC_DRAMTMG8_T_XS_DLL_X32_SHIFT 8 +#define DDRC_DRAMTMG8_T_XS_DLL_X32_MASK 0x00007F00U -/*tXS: Exit Self Refresh to commands not requiring a locked DLL. For configurations with MEMC_FREQ_RATIO=2, program this to the - above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: Used only for DDR2, DDR3 and - DDR4 SDRAMs.*/ +/* +* tXS: Exit Self Refresh to commands not requiring a locked DLL. For confi + * gurations with MEMC_FREQ_RATIO=2, program this to the above value divide + * d by 2 and round up to next integer value. Unit: Multiples of 32 clocks. + * Note: Used only for DDR2, DDR3 and DDR4 SDRAMs. +*/ #undef DDRC_DRAMTMG8_T_XS_X32_DEFVAL #undef DDRC_DRAMTMG8_T_XS_X32_SHIFT #undef DDRC_DRAMTMG8_T_XS_X32_MASK -#define DDRC_DRAMTMG8_T_XS_X32_DEFVAL 0x03034405 -#define DDRC_DRAMTMG8_T_XS_X32_SHIFT 0 -#define DDRC_DRAMTMG8_T_XS_X32_MASK 0x0000007FU +#define DDRC_DRAMTMG8_T_XS_X32_DEFVAL 0x03034405 +#define DDRC_DRAMTMG8_T_XS_X32_SHIFT 0 +#define DDRC_DRAMTMG8_T_XS_X32_MASK 0x0000007FU -/*DDR4 Write preamble mode - 0: 1tCK preamble - 1: 2tCK preamble Present only with MEMC_FREQ_RATIO=2*/ +/* +* DDR4 Write preamble mode - 0: 1tCK preamble - 1: 2tCK preamble Present o + * nly with MEMC_FREQ_RATIO=2 +*/ #undef DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_DEFVAL #undef DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_SHIFT #undef DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_MASK -#define DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_DEFVAL 0x0004040D -#define DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_SHIFT 30 -#define DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_MASK 0x40000000U +#define DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_DEFVAL 0x0004040D +#define DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_SHIFT 30 +#define DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_MASK 0x40000000U -/*tCCD_S: This is the minimum time between two reads or two writes for different bank group. For bank switching (from bank 'a' - o bank 'b'), the minimum time is this value + 1. For configurations with MEMC_FREQ_RATIO=2, program this to (tCCD_S/2) and ro - nd it up to the next integer value. Present only in designs configured to support DDR4. Unit: clocks.*/ +/* +* tCCD_S: This is the minimum time between two reads or two writes for dif + * ferent bank group. For bank switching (from bank 'a' to bank 'b'), the m + * inimum time is this value + 1. For configurations with MEMC_FREQ_RATIO=2 + * , program this to (tCCD_S/2) and round it up to the next integer value. + * Present only in designs configured to support DDR4. Unit: clocks. +*/ #undef DDRC_DRAMTMG9_T_CCD_S_DEFVAL #undef DDRC_DRAMTMG9_T_CCD_S_SHIFT #undef DDRC_DRAMTMG9_T_CCD_S_MASK -#define DDRC_DRAMTMG9_T_CCD_S_DEFVAL 0x0004040D -#define DDRC_DRAMTMG9_T_CCD_S_SHIFT 16 -#define DDRC_DRAMTMG9_T_CCD_S_MASK 0x00070000U +#define DDRC_DRAMTMG9_T_CCD_S_DEFVAL 0x0004040D +#define DDRC_DRAMTMG9_T_CCD_S_SHIFT 16 +#define DDRC_DRAMTMG9_T_CCD_S_MASK 0x00070000U -/*tRRD_S: Minimum time between activates from bank 'a' to bank 'b' for different bank group. For configurations with MEMC_FREQ_ - ATIO=2, program this to (tRRD_S/2) and round it up to the next integer value. Present only in designs configured to support D - R4. Unit: Clocks.*/ +/* +* tRRD_S: Minimum time between activates from bank 'a' to bank 'b' for dif + * ferent bank group. For configurations with MEMC_FREQ_RATIO=2, program th + * is to (tRRD_S/2) and round it up to the next integer value. Present only + * in designs configured to support DDR4. Unit: Clocks. +*/ #undef DDRC_DRAMTMG9_T_RRD_S_DEFVAL #undef DDRC_DRAMTMG9_T_RRD_S_SHIFT #undef DDRC_DRAMTMG9_T_RRD_S_MASK -#define DDRC_DRAMTMG9_T_RRD_S_DEFVAL 0x0004040D -#define DDRC_DRAMTMG9_T_RRD_S_SHIFT 8 -#define DDRC_DRAMTMG9_T_RRD_S_MASK 0x00000F00U +#define DDRC_DRAMTMG9_T_RRD_S_DEFVAL 0x0004040D +#define DDRC_DRAMTMG9_T_RRD_S_SHIFT 8 +#define DDRC_DRAMTMG9_T_RRD_S_MASK 0x00000F00U -/*CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command for different bank group. Includes time for bus turn - round, recovery times, and all per-bank, per-rank, and global constraints. Present only in designs configured to support DDR4 - Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity latency - BL = burst length. This must match the value programm - d in the BL bit of the mode register to the SDRAM - tWTR_S = internal write to read command delay for different bank group. T - is comes directly from the SDRAM specification. For configurations with MEMC_FREQ_RATIO=2, divide the value calculated using - he above equation by 2, and round it up to next integer.*/ +/* +* CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command + * for different bank group. Includes time for bus turnaround, recovery ti + * mes, and all per-bank, per-rank, and global constraints. Present only in + * designs configured to support DDR4. Unit: Clocks. Where: - CWL = CAS wr + * ite latency - PL = Parity latency - BL = burst length. This must match t + * he value programmed in the BL bit of the mode register to the SDRAM - tW + * TR_S = internal write to read command delay for different bank group. Th + * is comes directly from the SDRAM specification. For configurations with + * MEMC_FREQ_RATIO=2, divide the value calculated using the above equation + * by 2, and round it up to next integer. +*/ #undef DDRC_DRAMTMG9_WR2RD_S_DEFVAL #undef DDRC_DRAMTMG9_WR2RD_S_SHIFT #undef DDRC_DRAMTMG9_WR2RD_S_MASK -#define DDRC_DRAMTMG9_WR2RD_S_DEFVAL 0x0004040D -#define DDRC_DRAMTMG9_WR2RD_S_SHIFT 0 -#define DDRC_DRAMTMG9_WR2RD_S_MASK 0x0000003FU +#define DDRC_DRAMTMG9_WR2RD_S_DEFVAL 0x0004040D +#define DDRC_DRAMTMG9_WR2RD_S_SHIFT 0 +#define DDRC_DRAMTMG9_WR2RD_S_MASK 0x0000003FU -/*tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DLL. For configurations with MEMC_FREQ_RATIO=2, program - this to (tXMPDLL/2) and round it up to the next integer value. Present only in designs configured to support DDR4. Unit: Mult - ples of 32 clocks.*/ +/* +* tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DL + * L. For configurations with MEMC_FREQ_RATIO=2, program this to (tXMPDLL/2 + * ) and round it up to the next integer value. Present only in designs con + * figured to support DDR4. Unit: Multiples of 32 clocks. +*/ #undef DDRC_DRAMTMG11_POST_MPSM_GAP_X32_DEFVAL #undef DDRC_DRAMTMG11_POST_MPSM_GAP_X32_SHIFT #undef DDRC_DRAMTMG11_POST_MPSM_GAP_X32_MASK -#define DDRC_DRAMTMG11_POST_MPSM_GAP_X32_DEFVAL 0x440C021C -#define DDRC_DRAMTMG11_POST_MPSM_GAP_X32_SHIFT 24 -#define DDRC_DRAMTMG11_POST_MPSM_GAP_X32_MASK 0x7F000000U +#define DDRC_DRAMTMG11_POST_MPSM_GAP_X32_DEFVAL 0x440C021C +#define DDRC_DRAMTMG11_POST_MPSM_GAP_X32_SHIFT 24 +#define DDRC_DRAMTMG11_POST_MPSM_GAP_X32_MASK 0x7F000000U -/*tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge. For configurations with MEMC_FREQ_RATIO=2, program this t - RoundUp(tMPX_LH/2)+1. Present only in designs configured to support DDR4. Unit: clocks.*/ +/* +* tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge. For + * configurations with MEMC_FREQ_RATIO=2, program this to RoundUp(tMPX_LH/2 + * )+1. Present only in designs configured to support DDR4. Unit: clocks. +*/ #undef DDRC_DRAMTMG11_T_MPX_LH_DEFVAL #undef DDRC_DRAMTMG11_T_MPX_LH_SHIFT #undef DDRC_DRAMTMG11_T_MPX_LH_MASK -#define DDRC_DRAMTMG11_T_MPX_LH_DEFVAL 0x440C021C -#define DDRC_DRAMTMG11_T_MPX_LH_SHIFT 16 -#define DDRC_DRAMTMG11_T_MPX_LH_MASK 0x001F0000U +#define DDRC_DRAMTMG11_T_MPX_LH_DEFVAL 0x440C021C +#define DDRC_DRAMTMG11_T_MPX_LH_SHIFT 16 +#define DDRC_DRAMTMG11_T_MPX_LH_MASK 0x001F0000U -/*tMPX_S: Minimum time CS setup time to CKE. For configurations with MEMC_FREQ_RATIO=2, program this to (tMPX_S/2) and round it - up to the next integer value. Present only in designs configured to support DDR4. Unit: Clocks.*/ +/* +* tMPX_S: Minimum time CS setup time to CKE. For configurations with MEMC_ + * FREQ_RATIO=2, program this to (tMPX_S/2) and round it up to the next int + * eger value. Present only in designs configured to support DDR4. Unit: Cl + * ocks. +*/ #undef DDRC_DRAMTMG11_T_MPX_S_DEFVAL #undef DDRC_DRAMTMG11_T_MPX_S_SHIFT #undef DDRC_DRAMTMG11_T_MPX_S_MASK -#define DDRC_DRAMTMG11_T_MPX_S_DEFVAL 0x440C021C -#define DDRC_DRAMTMG11_T_MPX_S_SHIFT 8 -#define DDRC_DRAMTMG11_T_MPX_S_MASK 0x00000300U +#define DDRC_DRAMTMG11_T_MPX_S_DEFVAL 0x440C021C +#define DDRC_DRAMTMG11_T_MPX_S_SHIFT 8 +#define DDRC_DRAMTMG11_T_MPX_S_MASK 0x00000300U -/*tCKMPE: Minimum valid clock requirement after MPSM entry. Present only in designs configured to support DDR4. Unit: Clocks. F - r configurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next i - teger.*/ +/* +* tCKMPE: Minimum valid clock requirement after MPSM entry. Present only i + * n designs configured to support DDR4. Unit: Clocks. For configurations w + * ith MEMC_FREQ_RATIO=2, divide the value calculated using the above equat + * ion by 2, and round it up to next integer. +*/ #undef DDRC_DRAMTMG11_T_CKMPE_DEFVAL #undef DDRC_DRAMTMG11_T_CKMPE_SHIFT #undef DDRC_DRAMTMG11_T_CKMPE_MASK -#define DDRC_DRAMTMG11_T_CKMPE_DEFVAL 0x440C021C -#define DDRC_DRAMTMG11_T_CKMPE_SHIFT 0 -#define DDRC_DRAMTMG11_T_CKMPE_MASK 0x0000001FU +#define DDRC_DRAMTMG11_T_CKMPE_DEFVAL 0x440C021C +#define DDRC_DRAMTMG11_T_CKMPE_SHIFT 0 +#define DDRC_DRAMTMG11_T_CKMPE_MASK 0x0000001FU -/*tCMDCKE: Delay from valid command to CKE input LOW. Set this to the larger of tESCKE or tCMDCKE For configurations with MEMC_ - REQ_RATIO=2, program this to (max(tESCKE, tCMDCKE)/2) and round it up to next integer value.*/ +/* +* tCMDCKE: Delay from valid command to CKE input LOW. Set this to the larg + * er of tESCKE or tCMDCKE For configurations with MEMC_FREQ_RATIO=2, progr + * am this to (max(tESCKE, tCMDCKE)/2) and round it up to next integer valu + * e. +*/ #undef DDRC_DRAMTMG12_T_CMDCKE_DEFVAL #undef DDRC_DRAMTMG12_T_CMDCKE_SHIFT #undef DDRC_DRAMTMG12_T_CMDCKE_MASK -#define DDRC_DRAMTMG12_T_CMDCKE_DEFVAL 0x00020610 -#define DDRC_DRAMTMG12_T_CMDCKE_SHIFT 16 -#define DDRC_DRAMTMG12_T_CMDCKE_MASK 0x00030000U +#define DDRC_DRAMTMG12_T_CMDCKE_DEFVAL 0x00020610 +#define DDRC_DRAMTMG12_T_CMDCKE_SHIFT 16 +#define DDRC_DRAMTMG12_T_CMDCKE_MASK 0x00030000U -/*tCKEHCMD: Valid command requirement after CKE input HIGH. For configurations with MEMC_FREQ_RATIO=2, program this to (tCKEHCM - /2) and round it up to next integer value.*/ +/* +* tCKEHCMD: Valid command requirement after CKE input HIGH. For configurat + * ions with MEMC_FREQ_RATIO=2, program this to (tCKEHCMD/2) and round it u + * p to next integer value. +*/ #undef DDRC_DRAMTMG12_T_CKEHCMD_DEFVAL #undef DDRC_DRAMTMG12_T_CKEHCMD_SHIFT #undef DDRC_DRAMTMG12_T_CKEHCMD_MASK -#define DDRC_DRAMTMG12_T_CKEHCMD_DEFVAL 0x00020610 -#define DDRC_DRAMTMG12_T_CKEHCMD_SHIFT 8 -#define DDRC_DRAMTMG12_T_CKEHCMD_MASK 0x00000F00U +#define DDRC_DRAMTMG12_T_CKEHCMD_DEFVAL 0x00020610 +#define DDRC_DRAMTMG12_T_CKEHCMD_SHIFT 8 +#define DDRC_DRAMTMG12_T_CKEHCMD_MASK 0x00000F00U -/*tMRD_PDA: This is the Mode Register Set command cycle time in PDA mode. For configurations with MEMC_FREQ_RATIO=2, program th - s to (tMRD_PDA/2) and round it up to next integer value.*/ +/* +* tMRD_PDA: This is the Mode Register Set command cycle time in PDA mode. + * For configurations with MEMC_FREQ_RATIO=2, program this to (tMRD_PDA/2) + * and round it up to next integer value. +*/ #undef DDRC_DRAMTMG12_T_MRD_PDA_DEFVAL #undef DDRC_DRAMTMG12_T_MRD_PDA_SHIFT #undef DDRC_DRAMTMG12_T_MRD_PDA_MASK -#define DDRC_DRAMTMG12_T_MRD_PDA_DEFVAL 0x00020610 -#define DDRC_DRAMTMG12_T_MRD_PDA_SHIFT 0 -#define DDRC_DRAMTMG12_T_MRD_PDA_MASK 0x0000001FU +#define DDRC_DRAMTMG12_T_MRD_PDA_DEFVAL 0x00020610 +#define DDRC_DRAMTMG12_T_MRD_PDA_SHIFT 0 +#define DDRC_DRAMTMG12_T_MRD_PDA_MASK 0x0000001FU -/*- 1 - Disable uMCTL2 generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used instead to is - ue ZQ calibration request from APB module. - 0 - Internally generate ZQCS/MPC(ZQ calibration) commands based on ZQCTL1.t_zq_s - ort_interval_x1024. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.*/ +/* +* - 1 - Disable uMCTL2 generation of ZQCS/MPC(ZQ calibration) command. Reg + * ister DBGCMD.zq_calib_short can be used instead to issue ZQ calibration + * request from APB module. - 0 - Internally generate ZQCS/MPC(ZQ calibrati + * on) commands based on ZQCTL1.t_zq_short_interval_x1024. This is only pre + * sent for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. +*/ #undef DDRC_ZQCTL0_DIS_AUTO_ZQ_DEFVAL #undef DDRC_ZQCTL0_DIS_AUTO_ZQ_SHIFT #undef DDRC_ZQCTL0_DIS_AUTO_ZQ_MASK -#define DDRC_ZQCTL0_DIS_AUTO_ZQ_DEFVAL 0x02000040 -#define DDRC_ZQCTL0_DIS_AUTO_ZQ_SHIFT 31 -#define DDRC_ZQCTL0_DIS_AUTO_ZQ_MASK 0x80000000U +#define DDRC_ZQCTL0_DIS_AUTO_ZQ_DEFVAL 0x02000040 +#define DDRC_ZQCTL0_DIS_AUTO_ZQ_SHIFT 31 +#define DDRC_ZQCTL0_DIS_AUTO_ZQ_MASK 0x80000000U -/*- 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable when run in DDR3 - or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. - 0 - Enable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Power - own exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. This is only present for designs suppo - ting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.*/ +/* +* - 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refres + * h/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 + * or LPDDR3 or LPDDR4 mode. - 0 - Enable issuing of ZQCL/MPC(ZQ calibratio + * n) command at Self-Refresh/SR-Powerdown exit. Only applicable when run i + * n DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. This is only present + * for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. +*/ #undef DDRC_ZQCTL0_DIS_SRX_ZQCL_DEFVAL #undef DDRC_ZQCTL0_DIS_SRX_ZQCL_SHIFT #undef DDRC_ZQCTL0_DIS_SRX_ZQCL_MASK -#define DDRC_ZQCTL0_DIS_SRX_ZQCL_DEFVAL 0x02000040 -#define DDRC_ZQCTL0_DIS_SRX_ZQCL_SHIFT 30 -#define DDRC_ZQCTL0_DIS_SRX_ZQCL_MASK 0x40000000U +#define DDRC_ZQCTL0_DIS_SRX_ZQCL_DEFVAL 0x02000040 +#define DDRC_ZQCTL0_DIS_SRX_ZQCL_SHIFT 30 +#define DDRC_ZQCTL0_DIS_SRX_ZQCL_MASK 0x40000000U -/*- 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are sent to one r - nk at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to different ranks do not ov - rlap. - 0 - ZQ resistor is not shared. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.*/ +/* +* - 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQC + * L/ZQCS/MPC(ZQ calibration) commands are sent to one rank at a time with + * tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that co + * mmands to different ranks do not overlap. - 0 - ZQ resistor is not share + * d. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR + * 3/LPDDR4 devices. +*/ #undef DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_DEFVAL #undef DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_SHIFT #undef DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_MASK -#define DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_DEFVAL 0x02000040 -#define DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_SHIFT 29 -#define DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_MASK 0x20000000U +#define DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_DEFVAL 0x02000040 +#define DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_SHIFT 29 +#define DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_MASK 0x20000000U -/*- 1 - Disable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode. - 0 - Enable - ssuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode. This is only present for des - gns supporting DDR4 devices.*/ +/* +* - 1 - Disable issuing of ZQCL command at Maximum Power Saving Mode exit. + * Only applicable when run in DDR4 mode. - 0 - Enable issuing of ZQCL com + * mand at Maximum Power Saving Mode exit. Only applicable when run in DDR4 + * mode. This is only present for designs supporting DDR4 devices. +*/ #undef DDRC_ZQCTL0_DIS_MPSMX_ZQCL_DEFVAL #undef DDRC_ZQCTL0_DIS_MPSMX_ZQCL_SHIFT #undef DDRC_ZQCTL0_DIS_MPSMX_ZQCL_MASK -#define DDRC_ZQCTL0_DIS_MPSMX_ZQCL_DEFVAL 0x02000040 -#define DDRC_ZQCTL0_DIS_MPSMX_ZQCL_SHIFT 28 -#define DDRC_ZQCTL0_DIS_MPSMX_ZQCL_MASK 0x10000000U +#define DDRC_ZQCTL0_DIS_MPSMX_ZQCL_DEFVAL 0x02000040 +#define DDRC_ZQCTL0_DIS_MPSMX_ZQCL_SHIFT 28 +#define DDRC_ZQCTL0_DIS_MPSMX_ZQCL_MASK 0x10000000U -/*tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Number of cycles of NOP required after a ZQCL (ZQ calibrat - on long)/MPC(ZQ Start) command is issued to SDRAM. For configurations with MEMC_FREQ_RATIO=2: DDR3/DDR4: program this to tZQo - er/2 and round it up to the next integer value. LPDDR2/LPDDR3: program this to tZQCL/2 and round it up to the next integer va - ue. LPDDR4: program this to tZQCAL/2 and round it up to the next integer value. Unit: Clock cycles. This is only present for - esigns supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.*/ +/* +* tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Numbe + * r of cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ St + * art) command is issued to SDRAM. For configurations with MEMC_FREQ_RATIO + * =2: DDR3/DDR4: program this to tZQoper/2 and round it up to the next int + * eger value. LPDDR2/LPDDR3: program this to tZQCL/2 and round it up to th + * e next integer value. LPDDR4: program this to tZQCAL/2 and round it up t + * o the next integer value. Unit: Clock cycles. This is only present for d + * esigns supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices. +*/ #undef DDRC_ZQCTL0_T_ZQ_LONG_NOP_DEFVAL #undef DDRC_ZQCTL0_T_ZQ_LONG_NOP_SHIFT #undef DDRC_ZQCTL0_T_ZQ_LONG_NOP_MASK -#define DDRC_ZQCTL0_T_ZQ_LONG_NOP_DEFVAL 0x02000040 -#define DDRC_ZQCTL0_T_ZQ_LONG_NOP_SHIFT 16 -#define DDRC_ZQCTL0_T_ZQ_LONG_NOP_MASK 0x07FF0000U +#define DDRC_ZQCTL0_T_ZQ_LONG_NOP_DEFVAL 0x02000040 +#define DDRC_ZQCTL0_T_ZQ_LONG_NOP_SHIFT 16 +#define DDRC_ZQCTL0_T_ZQ_LONG_NOP_MASK 0x07FF0000U -/*tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of cycles of NOP required after a ZQCS (ZQ calibration short)/MPC - ZQ Latch) command is issued to SDRAM. For configurations with MEMC_FREQ_RATIO=2, program this to tZQCS/2 and round it up to t - e next integer value. Unit: Clock cycles. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devic - s.*/ +/* +* tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of cycles of + * NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command + * is issued to SDRAM. For configurations with MEMC_FREQ_RATIO=2, program t + * his to tZQCS/2 and round it up to the next integer value. Unit: Clock cy + * cles. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LP + * DDR3/LPDDR4 devices. +*/ #undef DDRC_ZQCTL0_T_ZQ_SHORT_NOP_DEFVAL #undef DDRC_ZQCTL0_T_ZQ_SHORT_NOP_SHIFT #undef DDRC_ZQCTL0_T_ZQ_SHORT_NOP_MASK -#define DDRC_ZQCTL0_T_ZQ_SHORT_NOP_DEFVAL 0x02000040 -#define DDRC_ZQCTL0_T_ZQ_SHORT_NOP_SHIFT 0 -#define DDRC_ZQCTL0_T_ZQ_SHORT_NOP_MASK 0x000003FFU +#define DDRC_ZQCTL0_T_ZQ_SHORT_NOP_DEFVAL 0x02000040 +#define DDRC_ZQCTL0_T_ZQ_SHORT_NOP_SHIFT 0 +#define DDRC_ZQCTL0_T_ZQ_SHORT_NOP_MASK 0x000003FFU -/*tZQReset: Number of cycles of NOP required after a ZQReset (ZQ calibration Reset) command is issued to SDRAM. For configurati - ns with MEMC_FREQ_RATIO=2, program this to tZQReset/2 and round it up to the next integer value. Unit: Clock cycles. This is - nly present for designs supporting LPDDR2/LPDDR3/LPDDR4 devices.*/ +/* +* tZQReset: Number of cycles of NOP required after a ZQReset (ZQ calibrati + * on Reset) command is issued to SDRAM. For configurations with MEMC_FREQ_ + * RATIO=2, program this to tZQReset/2 and round it up to the next integer + * value. Unit: Clock cycles. This is only present for designs supporting L + * PDDR2/LPDDR3/LPDDR4 devices. +*/ #undef DDRC_ZQCTL1_T_ZQ_RESET_NOP_DEFVAL #undef DDRC_ZQCTL1_T_ZQ_RESET_NOP_SHIFT #undef DDRC_ZQCTL1_T_ZQ_RESET_NOP_MASK -#define DDRC_ZQCTL1_T_ZQ_RESET_NOP_DEFVAL 0x02000100 -#define DDRC_ZQCTL1_T_ZQ_RESET_NOP_SHIFT 20 -#define DDRC_ZQCTL1_T_ZQ_RESET_NOP_MASK 0x3FF00000U +#define DDRC_ZQCTL1_T_ZQ_RESET_NOP_DEFVAL 0x02000100 +#define DDRC_ZQCTL1_T_ZQ_RESET_NOP_SHIFT 20 +#define DDRC_ZQCTL1_T_ZQ_RESET_NOP_MASK 0x3FF00000U -/*Average interval to wait between automatically issuing ZQCS (ZQ calibration short)/MPC(ZQ calibration) commands to DDR3/DDR4/ - PDDR2/LPDDR3/LPDDR4 devices. Meaningless, if ZQCTL0.dis_auto_zq=1. Unit: 1024 clock cycles. This is only present for designs - upporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.*/ +/* +* Average interval to wait between automatically issuing ZQCS (ZQ calibrat + * ion short)/MPC(ZQ calibration) commands to DDR3/DDR4/LPDDR2/LPDDR3/LPDDR + * 4 devices. Meaningless, if ZQCTL0.dis_auto_zq=1. Unit: 1024 clock cycles + * . This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3 + * /LPDDR4 devices. +*/ #undef DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_DEFVAL #undef DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_SHIFT #undef DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_MASK -#define DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_DEFVAL 0x02000100 -#define DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_SHIFT 0 -#define DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_MASK 0x000FFFFFU +#define DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_DEFVAL 0x02000100 +#define DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_SHIFT 0 +#define DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_MASK 0x000FFFFFU -/*Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signa - s at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligne - , this timing parameter should be rounded up to the next integer value. Note that if using RDIMM, it is necessary to incremen - this parameter by RDIMM's extra cycle of latency in terms of DFI clock.*/ +/* +* Specifies the number of DFI clock cycles after an assertion or de-assert + * ion of the DFI control signals that the control signals at the PHY-DRAM + * interface reflect the assertion or de-assertion. If the DFI clock and th + * e memory clock are not phase-aligned, this timing parameter should be ro + * unded up to the next integer value. Note that if using RDIMM, it is nece + * ssary to increment this parameter by RDIMM's extra cycle of latency in t + * erms of DFI clock. +*/ #undef DDRC_DFITMG0_DFI_T_CTRL_DELAY_DEFVAL #undef DDRC_DFITMG0_DFI_T_CTRL_DELAY_SHIFT #undef DDRC_DFITMG0_DFI_T_CTRL_DELAY_MASK -#define DDRC_DFITMG0_DFI_T_CTRL_DELAY_DEFVAL 0x07020002 -#define DDRC_DFITMG0_DFI_T_CTRL_DELAY_SHIFT 24 -#define DDRC_DFITMG0_DFI_T_CTRL_DELAY_MASK 0x1F000000U +#define DDRC_DFITMG0_DFI_T_CTRL_DELAY_DEFVAL 0x07020002 +#define DDRC_DFITMG0_DFI_T_CTRL_DELAY_SHIFT 24 +#define DDRC_DFITMG0_DFI_T_CTRL_DELAY_MASK 0x1F000000U -/*Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR or SDR values Selects whether value in DFITM - 0.dfi_t_rddata_en is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles R - fer to PHY specification for correct value.*/ +/* +* Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated u + * sing HDR or SDR values Selects whether value in DFITMG0.dfi_t_rddata_en + * is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles + * - 1 in terms of SDR clock cycles Refer to PHY specification for correct + * value. +*/ #undef DDRC_DFITMG0_DFI_RDDATA_USE_SDR_DEFVAL #undef DDRC_DFITMG0_DFI_RDDATA_USE_SDR_SHIFT #undef DDRC_DFITMG0_DFI_RDDATA_USE_SDR_MASK -#define DDRC_DFITMG0_DFI_RDDATA_USE_SDR_DEFVAL 0x07020002 -#define DDRC_DFITMG0_DFI_RDDATA_USE_SDR_SHIFT 23 -#define DDRC_DFITMG0_DFI_RDDATA_USE_SDR_MASK 0x00800000U +#define DDRC_DFITMG0_DFI_RDDATA_USE_SDR_DEFVAL 0x07020002 +#define DDRC_DFITMG0_DFI_RDDATA_USE_SDR_SHIFT 23 +#define DDRC_DFITMG0_DFI_RDDATA_USE_SDR_MASK 0x00800000U -/*Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. Refer to PHY spe - ification for correct value. This corresponds to the DFI parameter trddata_en. Note that, depending on the PHY, if using RDIM - , it may be necessary to use the value (CL + 1) in the calculation of trddata_en. This is to compensate for the extra cycle o - latency through the RDIMM. Unit: Clocks*/ +/* +* Time from the assertion of a read command on the DFI interface to the as + * sertion of the dfi_rddata_en signal. Refer to PHY specification for corr + * ect value. This corresponds to the DFI parameter trddata_en. Note that, + * depending on the PHY, if using RDIMM, it may be necessary to use the val + * ue (CL + 1) in the calculation of trddata_en. This is to compensate for + * the extra cycle of latency through the RDIMM. Unit: Clocks +*/ #undef DDRC_DFITMG0_DFI_T_RDDATA_EN_DEFVAL #undef DDRC_DFITMG0_DFI_T_RDDATA_EN_SHIFT #undef DDRC_DFITMG0_DFI_T_RDDATA_EN_MASK -#define DDRC_DFITMG0_DFI_T_RDDATA_EN_DEFVAL 0x07020002 -#define DDRC_DFITMG0_DFI_T_RDDATA_EN_SHIFT 16 -#define DDRC_DFITMG0_DFI_T_RDDATA_EN_MASK 0x003F0000U +#define DDRC_DFITMG0_DFI_T_RDDATA_EN_DEFVAL 0x07020002 +#define DDRC_DFITMG0_DFI_T_RDDATA_EN_SHIFT 16 +#define DDRC_DFITMG0_DFI_T_RDDATA_EN_MASK 0x003F0000U -/*Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using HDR or SDR values Selects whether value in DFITMG - .dfi_tphy_wrlat is in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.dfi_tphy_wrdata is in terms of SDR or - HDR clock cycles - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles Refer to PHY specification for correct val - e.*/ +/* +* Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated us + * ing HDR or SDR values Selects whether value in DFITMG0.dfi_tphy_wrlat is + * in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.df + * i_tphy_wrdata is in terms of SDR or HDR clock cycles - 0 in terms of HDR + * clock cycles - 1 in terms of SDR clock cycles Refer to PHY specificatio + * n for correct value. +*/ #undef DDRC_DFITMG0_DFI_WRDATA_USE_SDR_DEFVAL #undef DDRC_DFITMG0_DFI_WRDATA_USE_SDR_SHIFT #undef DDRC_DFITMG0_DFI_WRDATA_USE_SDR_MASK -#define DDRC_DFITMG0_DFI_WRDATA_USE_SDR_DEFVAL 0x07020002 -#define DDRC_DFITMG0_DFI_WRDATA_USE_SDR_SHIFT 15 -#define DDRC_DFITMG0_DFI_WRDATA_USE_SDR_MASK 0x00008000U +#define DDRC_DFITMG0_DFI_WRDATA_USE_SDR_DEFVAL 0x07020002 +#define DDRC_DFITMG0_DFI_WRDATA_USE_SDR_SHIFT 15 +#define DDRC_DFITMG0_DFI_WRDATA_USE_SDR_MASK 0x00008000U -/*Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on th - dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. N - te, max supported value is 8. Unit: Clocks*/ +/* +* Specifies the number of clock cycles between when dfi_wrdata_en is asser + * ted to when the associated write data is driven on the dfi_wrdata signal + * . This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY + * specification for correct value. Note, max supported value is 8. Unit: + * Clocks +*/ #undef DDRC_DFITMG0_DFI_TPHY_WRDATA_DEFVAL #undef DDRC_DFITMG0_DFI_TPHY_WRDATA_SHIFT #undef DDRC_DFITMG0_DFI_TPHY_WRDATA_MASK -#define DDRC_DFITMG0_DFI_TPHY_WRDATA_DEFVAL 0x07020002 -#define DDRC_DFITMG0_DFI_TPHY_WRDATA_SHIFT 8 -#define DDRC_DFITMG0_DFI_TPHY_WRDATA_MASK 0x00003F00U +#define DDRC_DFITMG0_DFI_TPHY_WRDATA_DEFVAL 0x07020002 +#define DDRC_DFITMG0_DFI_TPHY_WRDATA_SHIFT 8 +#define DDRC_DFITMG0_DFI_TPHY_WRDATA_MASK 0x00003F00U -/*Write latency Number of clocks from the write command to write data enable (dfi_wrdata_en). This corresponds to the DFI timin - parameter tphy_wrlat. Refer to PHY specification for correct value.Note that, depending on the PHY, if using RDIMM, it may b - necessary to use the value (CL + 1) in the calculation of tphy_wrlat. This is to compensate for the extra cycle of latency t - rough the RDIMM.*/ +/* +* Write latency Number of clocks from the write command to write data enab + * le (dfi_wrdata_en). This corresponds to the DFI timing parameter tphy_wr + * lat. Refer to PHY specification for correct value.Note that, depending o + * n the PHY, if using RDIMM, it may be necessary to use the value (CL + 1) + * in the calculation of tphy_wrlat. This is to compensate for the extra c + * ycle of latency through the RDIMM. +*/ #undef DDRC_DFITMG0_DFI_TPHY_WRLAT_DEFVAL #undef DDRC_DFITMG0_DFI_TPHY_WRLAT_SHIFT #undef DDRC_DFITMG0_DFI_TPHY_WRLAT_MASK -#define DDRC_DFITMG0_DFI_TPHY_WRLAT_DEFVAL 0x07020002 -#define DDRC_DFITMG0_DFI_TPHY_WRLAT_SHIFT 0 -#define DDRC_DFITMG0_DFI_TPHY_WRLAT_MASK 0x0000003FU +#define DDRC_DFITMG0_DFI_TPHY_WRLAT_DEFVAL 0x07020002 +#define DDRC_DFITMG0_DFI_TPHY_WRLAT_SHIFT 0 +#define DDRC_DFITMG0_DFI_TPHY_WRLAT_MASK 0x0000003FU -/*Specifies the number of DFI PHY clocks between when the dfi_cs signal is asserted and when the associated command is driven. - his field is used for CAL mode, should be set to '0' or the value which matches the CAL mode register setting in the DRAM. If - the PHY can add the latency for CAL mode, this should be set to '0'. Valid Range: 0, 3, 4, 5, 6, and 8*/ +/* +* Specifies the number of DFI PHY clocks between when the dfi_cs signal is + * asserted and when the associated command is driven. This field is used + * for CAL mode, should be set to '0' or the value which matches the CAL mo + * de register setting in the DRAM. If the PHY can add the latency for CAL + * mode, this should be set to '0'. Valid Range: 0, 3, 4, 5, 6, and 8 +*/ #undef DDRC_DFITMG1_DFI_T_CMD_LAT_DEFVAL #undef DDRC_DFITMG1_DFI_T_CMD_LAT_SHIFT #undef DDRC_DFITMG1_DFI_T_CMD_LAT_MASK -#define DDRC_DFITMG1_DFI_T_CMD_LAT_DEFVAL 0x00000404 -#define DDRC_DFITMG1_DFI_T_CMD_LAT_SHIFT 28 -#define DDRC_DFITMG1_DFI_T_CMD_LAT_MASK 0xF0000000U +#define DDRC_DFITMG1_DFI_T_CMD_LAT_DEFVAL 0x00000404 +#define DDRC_DFITMG1_DFI_T_CMD_LAT_SHIFT 28 +#define DDRC_DFITMG1_DFI_T_CMD_LAT_MASK 0xF0000000U -/*Specifies the number of DFI PHY clocks between when the dfi_cs signal is asserted and when the associated dfi_parity_in signa - is driven.*/ +/* +* Specifies the number of DFI PHY clocks between when the dfi_cs signal is + * asserted and when the associated dfi_parity_in signal is driven. +*/ #undef DDRC_DFITMG1_DFI_T_PARIN_LAT_DEFVAL #undef DDRC_DFITMG1_DFI_T_PARIN_LAT_SHIFT #undef DDRC_DFITMG1_DFI_T_PARIN_LAT_MASK -#define DDRC_DFITMG1_DFI_T_PARIN_LAT_DEFVAL 0x00000404 -#define DDRC_DFITMG1_DFI_T_PARIN_LAT_SHIFT 24 -#define DDRC_DFITMG1_DFI_T_PARIN_LAT_MASK 0x03000000U +#define DDRC_DFITMG1_DFI_T_PARIN_LAT_DEFVAL 0x00000404 +#define DDRC_DFITMG1_DFI_T_PARIN_LAT_SHIFT 24 +#define DDRC_DFITMG1_DFI_T_PARIN_LAT_MASK 0x03000000U -/*Specifies the number of DFI clocks between when the dfi_wrdata_en signal is asserted and when the corresponding write data tr - nsfer is completed on the DRAM bus. This corresponds to the DFI timing parameter twrdata_delay. Refer to PHY specification fo - correct value. For DFI 3.0 PHY, set to twrdata_delay, a new timing parameter introduced in DFI 3.0. For DFI 2.1 PHY, set to - phy_wrdata + (delay of DFI write data to the DRAM). Value to be programmed is in terms of DFI clocks, not PHY clocks. In FREQ - RATIO=2, divide PHY's value by 2 and round up to next integer. If using DFITMG0.dfi_wrdata_use_sdr=1, add 1 to the value. Uni - : Clocks*/ +/* +* Specifies the number of DFI clocks between when the dfi_wrdata_en signal + * is asserted and when the corresponding write data transfer is completed + * on the DRAM bus. This corresponds to the DFI timing parameter twrdata_d + * elay. Refer to PHY specification for correct value. For DFI 3.0 PHY, set + * to twrdata_delay, a new timing parameter introduced in DFI 3.0. For DFI + * 2.1 PHY, set to tphy_wrdata + (delay of DFI write data to the DRAM). Va + * lue to be programmed is in terms of DFI clocks, not PHY clocks. In FREQ_ + * RATIO=2, divide PHY's value by 2 and round up to next integer. If using + * DFITMG0.dfi_wrdata_use_sdr=1, add 1 to the value. Unit: Clocks +*/ #undef DDRC_DFITMG1_DFI_T_WRDATA_DELAY_DEFVAL #undef DDRC_DFITMG1_DFI_T_WRDATA_DELAY_SHIFT #undef DDRC_DFITMG1_DFI_T_WRDATA_DELAY_MASK -#define DDRC_DFITMG1_DFI_T_WRDATA_DELAY_DEFVAL 0x00000404 -#define DDRC_DFITMG1_DFI_T_WRDATA_DELAY_SHIFT 16 -#define DDRC_DFITMG1_DFI_T_WRDATA_DELAY_MASK 0x001F0000U +#define DDRC_DFITMG1_DFI_T_WRDATA_DELAY_DEFVAL 0x00000404 +#define DDRC_DFITMG1_DFI_T_WRDATA_DELAY_SHIFT 16 +#define DDRC_DFITMG1_DFI_T_WRDATA_DELAY_MASK 0x001F0000U -/*Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to - he DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase - ligned, this timing parameter should be rounded up to the next integer value.*/ +/* +* Specifies the number of DFI clock cycles from the assertion of the dfi_d + * ram_clk_disable signal on the DFI until the clock to the DRAM memory dev + * ices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock + * and the memory clock are not phase aligned, this timing parameter should + * be rounded up to the next integer value. +*/ #undef DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_DEFVAL #undef DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_SHIFT #undef DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_MASK -#define DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_DEFVAL 0x00000404 -#define DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_SHIFT 8 -#define DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_MASK 0x00000F00U +#define DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_DEFVAL 0x00000404 +#define DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_SHIFT 8 +#define DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_MASK 0x00000F00U -/*Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first - alid rising edge of the clock to the DRAM memory devices, at the PHY-DRAM boundary. If the DFI clock and the memory clock are - not phase aligned, this timing parameter should be rounded up to the next integer value.*/ +/* +* Specifies the number of DFI clock cycles from the de-assertion of the df + * i_dram_clk_disable signal on the DFI until the first valid rising edge o + * f the clock to the DRAM memory devices, at the PHY-DRAM boundary. If the + * DFI clock and the memory clock are not phase aligned, this timing param + * eter should be rounded up to the next integer value. +*/ #undef DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_DEFVAL #undef DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_SHIFT #undef DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_MASK -#define DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_DEFVAL 0x00000404 -#define DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_SHIFT 0 -#define DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_MASK 0x0000000FU +#define DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_DEFVAL 0x00000404 +#define DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_SHIFT 0 +#define DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_MASK 0x0000000FU -/*Setting for DFI's tlp_resp time. Same value is used for both Power Down, Self Refresh, Deep Power Down and Maximum Power Savi - g modes. DFI 2.1 specification onwards, recommends using a fixed value of 7 always.*/ +/* +* Setting for DFI's tlp_resp time. Same value is used for both Power Down, + * Self Refresh, Deep Power Down and Maximum Power Saving modes. DFI 2.1 s + * pecification onwards, recommends using a fixed value of 7 always. +*/ #undef DDRC_DFILPCFG0_DFI_TLP_RESP_DEFVAL #undef DDRC_DFILPCFG0_DFI_TLP_RESP_SHIFT #undef DDRC_DFILPCFG0_DFI_TLP_RESP_MASK -#define DDRC_DFILPCFG0_DFI_TLP_RESP_DEFVAL 0x07000000 -#define DDRC_DFILPCFG0_DFI_TLP_RESP_SHIFT 24 -#define DDRC_DFILPCFG0_DFI_TLP_RESP_MASK 0x0F000000U +#define DDRC_DFILPCFG0_DFI_TLP_RESP_DEFVAL 0x07000000 +#define DDRC_DFILPCFG0_DFI_TLP_RESP_SHIFT 24 +#define DDRC_DFILPCFG0_DFI_TLP_RESP_MASK 0x0F000000U -/*Value to drive on dfi_lp_wakeup signal when Deep Power Down mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 - cycles - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles - 0x7 - - 2048 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0xD - - 31072 cycles - 0xE - 262144 cycles - 0xF - Unlimited This is only present for designs supporting mDDR or LPDDR2/LPDDR3 device - .*/ +/* +* Value to drive on dfi_lp_wakeup signal when Deep Power Down mode is ente + * red. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32 + * cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 5 + * 12 cycles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycles - + * 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 6553 + * 6 cycles - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited T + * his is only present for designs supporting mDDR or LPDDR2/LPDDR3 devices + * . +*/ #undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_DEFVAL #undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_SHIFT #undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_MASK -#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_DEFVAL 0x07000000 -#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_SHIFT 20 -#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_MASK 0x00F00000U +#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_DEFVAL 0x07000000 +#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_SHIFT 20 +#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_MASK 0x00F00000U -/*Enables DFI Low Power interface handshaking during Deep Power Down Entry/Exit. - 0 - Disabled - 1 - Enabled This is only pres - nt for designs supporting mDDR or LPDDR2/LPDDR3 devices.*/ +/* +* Enables DFI Low Power interface handshaking during Deep Power Down Entry + * /Exit. - 0 - Disabled - 1 - Enabled This is only present for designs sup + * porting mDDR or LPDDR2/LPDDR3 devices. +*/ #undef DDRC_DFILPCFG0_DFI_LP_EN_DPD_DEFVAL #undef DDRC_DFILPCFG0_DFI_LP_EN_DPD_SHIFT #undef DDRC_DFILPCFG0_DFI_LP_EN_DPD_MASK -#define DDRC_DFILPCFG0_DFI_LP_EN_DPD_DEFVAL 0x07000000 -#define DDRC_DFILPCFG0_DFI_LP_EN_DPD_SHIFT 16 -#define DDRC_DFILPCFG0_DFI_LP_EN_DPD_MASK 0x00010000U +#define DDRC_DFILPCFG0_DFI_LP_EN_DPD_DEFVAL 0x07000000 +#define DDRC_DFILPCFG0_DFI_LP_EN_DPD_SHIFT 16 +#define DDRC_DFILPCFG0_DFI_LP_EN_DPD_MASK 0x00010000U -/*Value to drive on dfi_lp_wakeup signal when Self Refresh mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cy - les - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles - 0x7 - - 048 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0xD - 131 - 72 cycles - 0xE - 262144 cycles - 0xF - Unlimited*/ +/* +* Value to drive on dfi_lp_wakeup signal when Self Refresh mode is entered + * . Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32 cyc + * les - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 + * cycles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycles - 0x9 + * - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 c + * ycles - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited +*/ #undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_DEFVAL #undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_SHIFT #undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_MASK -#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_DEFVAL 0x07000000 -#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_SHIFT 12 -#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_MASK 0x0000F000U +#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_DEFVAL 0x07000000 +#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_SHIFT 12 +#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_MASK 0x0000F000U -/*Enables DFI Low Power interface handshaking during Self Refresh Entry/Exit. - 0 - Disabled - 1 - Enabled*/ +/* +* Enables DFI Low Power interface handshaking during Self Refresh Entry/Ex + * it. - 0 - Disabled - 1 - Enabled +*/ #undef DDRC_DFILPCFG0_DFI_LP_EN_SR_DEFVAL #undef DDRC_DFILPCFG0_DFI_LP_EN_SR_SHIFT #undef DDRC_DFILPCFG0_DFI_LP_EN_SR_MASK -#define DDRC_DFILPCFG0_DFI_LP_EN_SR_DEFVAL 0x07000000 -#define DDRC_DFILPCFG0_DFI_LP_EN_SR_SHIFT 8 -#define DDRC_DFILPCFG0_DFI_LP_EN_SR_MASK 0x00000100U +#define DDRC_DFILPCFG0_DFI_LP_EN_SR_DEFVAL 0x07000000 +#define DDRC_DFILPCFG0_DFI_LP_EN_SR_SHIFT 8 +#define DDRC_DFILPCFG0_DFI_LP_EN_SR_MASK 0x00000100U -/*Value to drive on dfi_lp_wakeup signal when Power Down mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycl - s - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles - 0x7 - 20 - 8 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0xD - 13107 - cycles - 0xE - 262144 cycles - 0xF - Unlimited*/ +/* +* Value to drive on dfi_lp_wakeup signal when Power Down mode is entered. + * Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32 cycle + * s - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cy + * cles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycles - 0x9 - + * 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cyc + * les - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited +*/ #undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_DEFVAL #undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_SHIFT #undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_MASK -#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_DEFVAL 0x07000000 -#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_SHIFT 4 -#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_MASK 0x000000F0U +#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_DEFVAL 0x07000000 +#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_SHIFT 4 +#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_MASK 0x000000F0U -/*Enables DFI Low Power interface handshaking during Power Down Entry/Exit. - 0 - Disabled - 1 - Enabled*/ +/* +* Enables DFI Low Power interface handshaking during Power Down Entry/Exit + * . - 0 - Disabled - 1 - Enabled +*/ #undef DDRC_DFILPCFG0_DFI_LP_EN_PD_DEFVAL #undef DDRC_DFILPCFG0_DFI_LP_EN_PD_SHIFT #undef DDRC_DFILPCFG0_DFI_LP_EN_PD_MASK -#define DDRC_DFILPCFG0_DFI_LP_EN_PD_DEFVAL 0x07000000 -#define DDRC_DFILPCFG0_DFI_LP_EN_PD_SHIFT 0 -#define DDRC_DFILPCFG0_DFI_LP_EN_PD_MASK 0x00000001U +#define DDRC_DFILPCFG0_DFI_LP_EN_PD_DEFVAL 0x07000000 +#define DDRC_DFILPCFG0_DFI_LP_EN_PD_SHIFT 0 +#define DDRC_DFILPCFG0_DFI_LP_EN_PD_MASK 0x00000001U -/*Value to drive on dfi_lp_wakeup signal when Maximum Power Saving Mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - - 16 cycles - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0 - D - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited This is only present for designs supporting DDR4 devices.*/ +/* +* Value to drive on dfi_lp_wakeup signal when Maximum Power Saving Mode is + * entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 + * - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x + * 5 - 512 cycles - 0x6 - 1024 cycles - 0x7 - 2048 cycles - 0x8 - 4096 cycl + * es - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - + * 65536 cycles - 0xD - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimi + * ted This is only present for designs supporting DDR4 devices. +*/ #undef DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_DEFVAL #undef DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_SHIFT #undef DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_MASK -#define DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_DEFVAL 0x00000000 -#define DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_SHIFT 4 -#define DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_MASK 0x000000F0U +#define DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_DEFVAL 0x00000000 +#define DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_SHIFT 4 +#define DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_MASK 0x000000F0U -/*Enables DFI Low Power interface handshaking during Maximum Power Saving Mode Entry/Exit. - 0 - Disabled - 1 - Enabled This is - only present for designs supporting DDR4 devices.*/ +/* +* Enables DFI Low Power interface handshaking during Maximum Power Saving + * Mode Entry/Exit. - 0 - Disabled - 1 - Enabled This is only present for d + * esigns supporting DDR4 devices. +*/ #undef DDRC_DFILPCFG1_DFI_LP_EN_MPSM_DEFVAL #undef DDRC_DFILPCFG1_DFI_LP_EN_MPSM_SHIFT #undef DDRC_DFILPCFG1_DFI_LP_EN_MPSM_MASK -#define DDRC_DFILPCFG1_DFI_LP_EN_MPSM_DEFVAL 0x00000000 -#define DDRC_DFILPCFG1_DFI_LP_EN_MPSM_SHIFT 0 -#define DDRC_DFILPCFG1_DFI_LP_EN_MPSM_MASK 0x00000001U +#define DDRC_DFILPCFG1_DFI_LP_EN_MPSM_DEFVAL 0x00000000 +#define DDRC_DFILPCFG1_DFI_LP_EN_MPSM_SHIFT 0 +#define DDRC_DFILPCFG1_DFI_LP_EN_MPSM_MASK 0x00000001U -/*This is the minimum amount of time between uMCTL2 initiated DFI update requests (which is executed whenever the uMCTL2 is idl - ). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the fir - t read request when the uMCTL2 is idle. Unit: 1024 clocks*/ +/* +* When '1', disable the automatic dfi_ctrlupd_req generation by the uMCTL2 + * . The core must issue the dfi_ctrlupd_req signal using register reg_ddrc + * _ctrlupd. When '0', uMCTL2 issues dfi_ctrlupd_req periodically. +*/ +#undef DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_DEFVAL +#undef DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SHIFT +#undef DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_MASK +#define DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_DEFVAL 0x00400003 +#define DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SHIFT 31 +#define DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_MASK 0x80000000U + +/* +* When '1', disable the automatic dfi_ctrlupd_req generation by the uMCTL2 + * following a self-refresh exit. The core must issue the dfi_ctrlupd_req + * signal using register reg_ddrc_ctrlupd. When '0', uMCTL2 issues a dfi_ct + * rlupd_req after exiting self-refresh. +*/ +#undef DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_DEFVAL +#undef DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_SHIFT +#undef DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_MASK +#define DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_DEFVAL 0x00400003 +#define DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_SHIFT 30 +#define DDRC_DFIUPD0_DIS_AUTO_CTRLUPD_SRX_MASK 0x40000000U + +/* +* Specifies the maximum number of clock cycles that the dfi_ctrlupd_req si + * gnal can assert. Lowest value to assign to this variable is 0x40. Unit: + * Clocks +*/ +#undef DDRC_DFIUPD0_DFI_T_CTRLUP_MAX_DEFVAL +#undef DDRC_DFIUPD0_DFI_T_CTRLUP_MAX_SHIFT +#undef DDRC_DFIUPD0_DFI_T_CTRLUP_MAX_MASK +#define DDRC_DFIUPD0_DFI_T_CTRLUP_MAX_DEFVAL 0x00400003 +#define DDRC_DFIUPD0_DFI_T_CTRLUP_MAX_SHIFT 16 +#define DDRC_DFIUPD0_DFI_T_CTRLUP_MAX_MASK 0x03FF0000U + +/* +* Specifies the minimum number of clock cycles that the dfi_ctrlupd_req si + * gnal must be asserted. The uMCTL2 expects the PHY to respond within this + * time. If the PHY does not respond, the uMCTL2 will de-assert dfi_ctrlup + * d_req after dfi_t_ctrlup_min + 2 cycles. Lowest value to assign to this + * variable is 0x3. Unit: Clocks +*/ +#undef DDRC_DFIUPD0_DFI_T_CTRLUP_MIN_DEFVAL +#undef DDRC_DFIUPD0_DFI_T_CTRLUP_MIN_SHIFT +#undef DDRC_DFIUPD0_DFI_T_CTRLUP_MIN_MASK +#define DDRC_DFIUPD0_DFI_T_CTRLUP_MIN_DEFVAL 0x00400003 +#define DDRC_DFIUPD0_DFI_T_CTRLUP_MIN_SHIFT 0 +#define DDRC_DFIUPD0_DFI_T_CTRLUP_MIN_MASK 0x000003FFU + +/* +* This is the minimum amount of time between uMCTL2 initiated DFI update r + * equests (which is executed whenever the uMCTL2 is idle). Set this number + * higher to reduce the frequency of update requests, which can have a sma + * ll impact on the latency of the first read request when the uMCTL2 is id + * le. Unit: 1024 clocks +*/ #undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_DEFVAL #undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_SHIFT #undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_MASK -#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_DEFVAL 0x00000000 -#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_SHIFT 16 -#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_MASK 0x00FF0000U +#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_DEFVAL 0x00000000 +#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_SHIFT 16 +#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_MASK 0x00FF0000U -/*This is the maximum amount of time between uMCTL2 initiated DFI update requests. This timer resets with each update request; - hen the timer expires dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd_ackx is received. PHY can use this - idle time to recalibrate the delay lines to the DLLs. The DFI controller update is also used to reset PHY FIFO pointers in ca - e of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. - Note: Value programmed for DFIUPD1.dfi_t_ctrlupd_interval_max_x1024 must be greater than DFIUPD1.dfi_t_ctrlupd_interval_min_x - 024. Unit: 1024 clocks*/ +/* +* This is the maximum amount of time between uMCTL2 initiated DFI update r + * equests. This timer resets with each update request; when the timer expi + * res dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd + * _ackx is received. PHY can use this idle time to recalibrate the delay l + * ines to the DLLs. The DFI controller update is also used to reset PHY FI + * FO pointers in case of data capture errors. Updates are required to main + * tain calibration over PVT, but frequent updates may impact performance. + * Note: Value programmed for DFIUPD1.dfi_t_ctrlupd_interval_max_x1024 must + * be greater than DFIUPD1.dfi_t_ctrlupd_interval_min_x1024. Unit: 1024 cl + * ocks +*/ #undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_DEFVAL #undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_SHIFT #undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_MASK -#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_DEFVAL 0x00000000 -#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_SHIFT 0 -#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_MASK 0x000000FFU +#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_DEFVAL 0x00000000 +#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_SHIFT 0 +#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_MASK 0x000000FFU -/*Defines polarity of dfi_wrdata_cs and dfi_rddata_cs signals. - 0: Signals are active low - 1: Signals are active high*/ +/* +* Defines polarity of dfi_wrdata_cs and dfi_rddata_cs signals. - 0: Signal + * s are active low - 1: Signals are active high +*/ #undef DDRC_DFIMISC_DFI_DATA_CS_POLARITY_DEFVAL #undef DDRC_DFIMISC_DFI_DATA_CS_POLARITY_SHIFT #undef DDRC_DFIMISC_DFI_DATA_CS_POLARITY_MASK -#define DDRC_DFIMISC_DFI_DATA_CS_POLARITY_DEFVAL 0x00000001 -#define DDRC_DFIMISC_DFI_DATA_CS_POLARITY_SHIFT 2 -#define DDRC_DFIMISC_DFI_DATA_CS_POLARITY_MASK 0x00000004U +#define DDRC_DFIMISC_DFI_DATA_CS_POLARITY_DEFVAL 0x00000001 +#define DDRC_DFIMISC_DFI_DATA_CS_POLARITY_SHIFT 2 +#define DDRC_DFIMISC_DFI_DATA_CS_POLARITY_MASK 0x00000004U -/*DBI implemented in DDRC or PHY. - 0 - DDRC implements DBI functionality. - 1 - PHY implements DBI functionality. Present only - in designs configured to support DDR4 and LPDDR4.*/ +/* +* DBI implemented in DDRC or PHY. - 0 - DDRC implements DBI functionality. + * - 1 - PHY implements DBI functionality. Present only in designs configu + * red to support DDR4 and LPDDR4. +*/ #undef DDRC_DFIMISC_PHY_DBI_MODE_DEFVAL #undef DDRC_DFIMISC_PHY_DBI_MODE_SHIFT #undef DDRC_DFIMISC_PHY_DBI_MODE_MASK -#define DDRC_DFIMISC_PHY_DBI_MODE_DEFVAL 0x00000001 -#define DDRC_DFIMISC_PHY_DBI_MODE_SHIFT 1 -#define DDRC_DFIMISC_PHY_DBI_MODE_MASK 0x00000002U +#define DDRC_DFIMISC_PHY_DBI_MODE_DEFVAL 0x00000001 +#define DDRC_DFIMISC_PHY_DBI_MODE_SHIFT 1 +#define DDRC_DFIMISC_PHY_DBI_MODE_MASK 0x00000002U -/*PHY initialization complete enable signal. When asserted the dfi_init_complete signal can be used to trigger SDRAM initialisa - ion*/ +/* +* PHY initialization complete enable signal. When asserted the dfi_init_co + * mplete signal can be used to trigger SDRAM initialisation +*/ #undef DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_DEFVAL #undef DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_SHIFT #undef DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_MASK -#define DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_DEFVAL 0x00000001 -#define DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_SHIFT 0 -#define DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_MASK 0x00000001U +#define DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_DEFVAL 0x00000001 +#define DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_SHIFT 0 +#define DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_MASK 0x00000001U -/*>Number of clocks between when a read command is sent on the DFI control interface and when the associated dfi_rddata_cs sign - l is asserted. This corresponds to the DFI timing parameter tphy_rdcslat. Refer to PHY specification for correct value.*/ +/* +* >Number of clocks between when a read command is sent on the DFI control + * interface and when the associated dfi_rddata_cs signal is asserted. Thi + * s corresponds to the DFI timing parameter tphy_rdcslat. Refer to PHY spe + * cification for correct value. +*/ #undef DDRC_DFITMG2_DFI_TPHY_RDCSLAT_DEFVAL #undef DDRC_DFITMG2_DFI_TPHY_RDCSLAT_SHIFT #undef DDRC_DFITMG2_DFI_TPHY_RDCSLAT_MASK -#define DDRC_DFITMG2_DFI_TPHY_RDCSLAT_DEFVAL 0x00000202 -#define DDRC_DFITMG2_DFI_TPHY_RDCSLAT_SHIFT 8 -#define DDRC_DFITMG2_DFI_TPHY_RDCSLAT_MASK 0x00003F00U +#define DDRC_DFITMG2_DFI_TPHY_RDCSLAT_DEFVAL 0x00000202 +#define DDRC_DFITMG2_DFI_TPHY_RDCSLAT_SHIFT 8 +#define DDRC_DFITMG2_DFI_TPHY_RDCSLAT_MASK 0x00003F00U -/*Number of clocks between when a write command is sent on the DFI control interface and when the associated dfi_wrdata_cs sign - l is asserted. This corresponds to the DFI timing parameter tphy_wrcslat. Refer to PHY specification for correct value.*/ +/* +* Number of clocks between when a write command is sent on the DFI control + * interface and when the associated dfi_wrdata_cs signal is asserted. Thi + * s corresponds to the DFI timing parameter tphy_wrcslat. Refer to PHY spe + * cification for correct value. +*/ #undef DDRC_DFITMG2_DFI_TPHY_WRCSLAT_DEFVAL #undef DDRC_DFITMG2_DFI_TPHY_WRCSLAT_SHIFT #undef DDRC_DFITMG2_DFI_TPHY_WRCSLAT_MASK -#define DDRC_DFITMG2_DFI_TPHY_WRCSLAT_DEFVAL 0x00000202 -#define DDRC_DFITMG2_DFI_TPHY_WRCSLAT_SHIFT 0 -#define DDRC_DFITMG2_DFI_TPHY_WRCSLAT_MASK 0x0000003FU +#define DDRC_DFITMG2_DFI_TPHY_WRCSLAT_DEFVAL 0x00000202 +#define DDRC_DFITMG2_DFI_TPHY_WRCSLAT_SHIFT 0 +#define DDRC_DFITMG2_DFI_TPHY_WRCSLAT_MASK 0x0000003FU -/*Read DBI enable signal in DDRC. - 0 - Read DBI is disabled. - 1 - Read DBI is enabled. This signal must be set the same value - as DRAM's mode register. - DDR4: MR5 bit A12. When x4 devices are used, this signal must be set to 0. - LPDDR4: MR3[6]*/ +/* +* Read DBI enable signal in DDRC. - 0 - Read DBI is disabled. - 1 - Read D + * BI is enabled. This signal must be set the same value as DRAM's mode reg + * ister. - DDR4: MR5 bit A12. When x4 devices are used, this signal must b + * e set to 0. - LPDDR4: MR3[6] +*/ #undef DDRC_DBICTL_RD_DBI_EN_DEFVAL #undef DDRC_DBICTL_RD_DBI_EN_SHIFT #undef DDRC_DBICTL_RD_DBI_EN_MASK -#define DDRC_DBICTL_RD_DBI_EN_DEFVAL 0x00000001 -#define DDRC_DBICTL_RD_DBI_EN_SHIFT 2 -#define DDRC_DBICTL_RD_DBI_EN_MASK 0x00000004U +#define DDRC_DBICTL_RD_DBI_EN_DEFVAL 0x00000001 +#define DDRC_DBICTL_RD_DBI_EN_SHIFT 2 +#define DDRC_DBICTL_RD_DBI_EN_MASK 0x00000004U -/*Write DBI enable signal in DDRC. - 0 - Write DBI is disabled. - 1 - Write DBI is enabled. This signal must be set the same va - ue as DRAM's mode register. - DDR4: MR5 bit A11. When x4 devices are used, this signal must be set to 0. - LPDDR4: MR3[7]*/ +/* +* Write DBI enable signal in DDRC. - 0 - Write DBI is disabled. - 1 - Writ + * e DBI is enabled. This signal must be set the same value as DRAM's mode + * register. - DDR4: MR5 bit A11. When x4 devices are used, this signal mus + * t be set to 0. - LPDDR4: MR3[7] +*/ #undef DDRC_DBICTL_WR_DBI_EN_DEFVAL #undef DDRC_DBICTL_WR_DBI_EN_SHIFT #undef DDRC_DBICTL_WR_DBI_EN_MASK -#define DDRC_DBICTL_WR_DBI_EN_DEFVAL 0x00000001 -#define DDRC_DBICTL_WR_DBI_EN_SHIFT 1 -#define DDRC_DBICTL_WR_DBI_EN_MASK 0x00000002U +#define DDRC_DBICTL_WR_DBI_EN_DEFVAL 0x00000001 +#define DDRC_DBICTL_WR_DBI_EN_SHIFT 1 +#define DDRC_DBICTL_WR_DBI_EN_MASK 0x00000002U -/*DM enable signal in DDRC. - 0 - DM is disabled. - 1 - DM is enabled. This signal must be set the same logical value as DRAM's - mode register. - DDR4: Set this to same value as MR5 bit A10. When x4 devices are used, this signal must be set to 0. - LPDDR - : Set this to inverted value of MR13[5] which is opposite polarity from this signal*/ +/* +* DM enable signal in DDRC. - 0 - DM is disabled. - 1 - DM is enabled. Thi + * s signal must be set the same logical value as DRAM's mode register. - D + * DR4: Set this to same value as MR5 bit A10. When x4 devices are used, th + * is signal must be set to 0. - LPDDR4: Set this to inverted value of MR13 + * [5] which is opposite polarity from this signal +*/ #undef DDRC_DBICTL_DM_EN_DEFVAL #undef DDRC_DBICTL_DM_EN_SHIFT #undef DDRC_DBICTL_DM_EN_MASK -#define DDRC_DBICTL_DM_EN_DEFVAL 0x00000001 -#define DDRC_DBICTL_DM_EN_SHIFT 0 -#define DDRC_DBICTL_DM_EN_MASK 0x00000001U +#define DDRC_DBICTL_DM_EN_DEFVAL 0x00000001 +#define DDRC_DBICTL_DM_EN_SHIFT 0 +#define DDRC_DBICTL_DM_EN_MASK 0x00000001U -/*Selects the HIF address bit used as rank address bit 0. Valid Range: 0 to 27, and 31 Internal Base: 6 The selected HIF addres - bit is determined by adding the internal base to the value of this field. If set to 31, rank address bit 0 is set to 0.*/ +/* +* Selects the HIF address bit used as rank address bit 0. Valid Range: 0 t + * o 27, and 31 Internal Base: 6 The selected HIF address bit is determined + * by adding the internal base to the value of this field. If set to 31, r + * ank address bit 0 is set to 0. +*/ #undef DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_DEFVAL #undef DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_SHIFT #undef DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_MASK -#define DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_DEFVAL -#define DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_SHIFT 0 -#define DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_MASK 0x0000001FU +#define DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_DEFVAL +#define DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_SHIFT 0 +#define DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_MASK 0x0000001FU -/*Selects the HIF address bit used as bank address bit 2. Valid Range: 0 to 29 and 31 Internal Base: 4 The selected HIF address - bit is determined by adding the internal base to the value of this field. If set to 31, bank address bit 2 is set to 0.*/ +/* +* Selects the HIF address bit used as bank address bit 2. Valid Range: 0 t + * o 29 and 31 Internal Base: 4 The selected HIF address bit is determined + * by adding the internal base to the value of this field. If set to 31, ba + * nk address bit 2 is set to 0. +*/ #undef DDRC_ADDRMAP1_ADDRMAP_BANK_B2_DEFVAL #undef DDRC_ADDRMAP1_ADDRMAP_BANK_B2_SHIFT #undef DDRC_ADDRMAP1_ADDRMAP_BANK_B2_MASK -#define DDRC_ADDRMAP1_ADDRMAP_BANK_B2_DEFVAL 0x00000000 -#define DDRC_ADDRMAP1_ADDRMAP_BANK_B2_SHIFT 16 -#define DDRC_ADDRMAP1_ADDRMAP_BANK_B2_MASK 0x001F0000U +#define DDRC_ADDRMAP1_ADDRMAP_BANK_B2_DEFVAL 0x00000000 +#define DDRC_ADDRMAP1_ADDRMAP_BANK_B2_SHIFT 16 +#define DDRC_ADDRMAP1_ADDRMAP_BANK_B2_MASK 0x001F0000U -/*Selects the HIF address bits used as bank address bit 1. Valid Range: 0 to 30 Internal Base: 3 The selected HIF address bit f - r each of the bank address bits is determined by adding the internal base to the value of this field.*/ +/* +* Selects the HIF address bits used as bank address bit 1. Valid Range: 0 + * to 30 Internal Base: 3 The selected HIF address bit for each of the bank + * address bits is determined by adding the internal base to the value of + * this field. +*/ #undef DDRC_ADDRMAP1_ADDRMAP_BANK_B1_DEFVAL #undef DDRC_ADDRMAP1_ADDRMAP_BANK_B1_SHIFT #undef DDRC_ADDRMAP1_ADDRMAP_BANK_B1_MASK -#define DDRC_ADDRMAP1_ADDRMAP_BANK_B1_DEFVAL 0x00000000 -#define DDRC_ADDRMAP1_ADDRMAP_BANK_B1_SHIFT 8 -#define DDRC_ADDRMAP1_ADDRMAP_BANK_B1_MASK 0x00001F00U +#define DDRC_ADDRMAP1_ADDRMAP_BANK_B1_DEFVAL 0x00000000 +#define DDRC_ADDRMAP1_ADDRMAP_BANK_B1_SHIFT 8 +#define DDRC_ADDRMAP1_ADDRMAP_BANK_B1_MASK 0x00001F00U -/*Selects the HIF address bits used as bank address bit 0. Valid Range: 0 to 30 Internal Base: 2 The selected HIF address bit f - r each of the bank address bits is determined by adding the internal base to the value of this field.*/ +/* +* Selects the HIF address bits used as bank address bit 0. Valid Range: 0 + * to 30 Internal Base: 2 The selected HIF address bit for each of the bank + * address bits is determined by adding the internal base to the value of + * this field. +*/ #undef DDRC_ADDRMAP1_ADDRMAP_BANK_B0_DEFVAL #undef DDRC_ADDRMAP1_ADDRMAP_BANK_B0_SHIFT #undef DDRC_ADDRMAP1_ADDRMAP_BANK_B0_MASK -#define DDRC_ADDRMAP1_ADDRMAP_BANK_B0_DEFVAL 0x00000000 -#define DDRC_ADDRMAP1_ADDRMAP_BANK_B0_SHIFT 0 -#define DDRC_ADDRMAP1_ADDRMAP_BANK_B0_MASK 0x0000001FU +#define DDRC_ADDRMAP1_ADDRMAP_BANK_B0_DEFVAL 0x00000000 +#define DDRC_ADDRMAP1_ADDRMAP_BANK_B0_SHIFT 0 +#define DDRC_ADDRMAP1_ADDRMAP_BANK_B0_MASK 0x0000001FU -/*- Full bus width mode: Selects the HIF address bit used as column address bit 5. - Half bus width mode: Selects the HIF addre - s bit used as column address bit 6. - Quarter bus width mode: Selects the HIF address bit used as column address bit 7 . Vali - Range: 0 to 7, and 15 Internal Base: 5 The selected HIF address bit is determined by adding the internal base to the value o - this field. If set to 15, this column address bit is set to 0.*/ +/* +* - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 5. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 6. - Quarter bus width mode: Selects the HIF address bit + * used as column address bit 7 . Valid Range: 0 to 7, and 15 Internal Base + * : 5 The selected HIF address bit is determined by adding the internal ba + * se to the value of this field. If set to 15, this column address bit is + * set to 0. +*/ #undef DDRC_ADDRMAP2_ADDRMAP_COL_B5_DEFVAL #undef DDRC_ADDRMAP2_ADDRMAP_COL_B5_SHIFT #undef DDRC_ADDRMAP2_ADDRMAP_COL_B5_MASK -#define DDRC_ADDRMAP2_ADDRMAP_COL_B5_DEFVAL 0x00000000 -#define DDRC_ADDRMAP2_ADDRMAP_COL_B5_SHIFT 24 -#define DDRC_ADDRMAP2_ADDRMAP_COL_B5_MASK 0x0F000000U +#define DDRC_ADDRMAP2_ADDRMAP_COL_B5_DEFVAL 0x00000000 +#define DDRC_ADDRMAP2_ADDRMAP_COL_B5_SHIFT 24 +#define DDRC_ADDRMAP2_ADDRMAP_COL_B5_MASK 0x0F000000U -/*- Full bus width mode: Selects the HIF address bit used as column address bit 4. - Half bus width mode: Selects the HIF addre - s bit used as column address bit 5. - Quarter bus width mode: Selects the HIF address bit used as column address bit 6. Valid - Range: 0 to 7, and 15 Internal Base: 4 The selected HIF address bit is determined by adding the internal base to the value of - this field. If set to 15, this column address bit is set to 0.*/ +/* +* - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 4. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 5. - Quarter bus width mode: Selects the HIF address bit + * used as column address bit 6. Valid Range: 0 to 7, and 15 Internal Base: + * 4 The selected HIF address bit is determined by adding the internal bas + * e to the value of this field. If set to 15, this column address bit is s + * et to 0. +*/ #undef DDRC_ADDRMAP2_ADDRMAP_COL_B4_DEFVAL #undef DDRC_ADDRMAP2_ADDRMAP_COL_B4_SHIFT #undef DDRC_ADDRMAP2_ADDRMAP_COL_B4_MASK -#define DDRC_ADDRMAP2_ADDRMAP_COL_B4_DEFVAL 0x00000000 -#define DDRC_ADDRMAP2_ADDRMAP_COL_B4_SHIFT 16 -#define DDRC_ADDRMAP2_ADDRMAP_COL_B4_MASK 0x000F0000U +#define DDRC_ADDRMAP2_ADDRMAP_COL_B4_DEFVAL 0x00000000 +#define DDRC_ADDRMAP2_ADDRMAP_COL_B4_SHIFT 16 +#define DDRC_ADDRMAP2_ADDRMAP_COL_B4_MASK 0x000F0000U -/*- Full bus width mode: Selects the HIF address bit used as column address bit 3. - Half bus width mode: Selects the HIF addre - s bit used as column address bit 4. - Quarter bus width mode: Selects the HIF address bit used as column address bit 5. Valid - Range: 0 to 7 Internal Base: 3 The selected HIF address bit is determined by adding the internal base to the value of this fi - ld. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=16, it is required to program this to 0, hence register does not exist i - this case.*/ +/* +* - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 3. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 4. - Quarter bus width mode: Selects the HIF address bit + * used as column address bit 5. Valid Range: 0 to 7 Internal Base: 3 The s + * elected HIF address bit is determined by adding the internal base to the + * value of this field. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=1 + * 6, it is required to program this to 0, hence register does not exist in + * this case. +*/ #undef DDRC_ADDRMAP2_ADDRMAP_COL_B3_DEFVAL #undef DDRC_ADDRMAP2_ADDRMAP_COL_B3_SHIFT #undef DDRC_ADDRMAP2_ADDRMAP_COL_B3_MASK -#define DDRC_ADDRMAP2_ADDRMAP_COL_B3_DEFVAL 0x00000000 -#define DDRC_ADDRMAP2_ADDRMAP_COL_B3_SHIFT 8 -#define DDRC_ADDRMAP2_ADDRMAP_COL_B3_MASK 0x00000F00U +#define DDRC_ADDRMAP2_ADDRMAP_COL_B3_DEFVAL 0x00000000 +#define DDRC_ADDRMAP2_ADDRMAP_COL_B3_SHIFT 8 +#define DDRC_ADDRMAP2_ADDRMAP_COL_B3_MASK 0x00000F00U -/*- Full bus width mode: Selects the HIF address bit used as column address bit 2. - Half bus width mode: Selects the HIF addre - s bit used as column address bit 3. - Quarter bus width mode: Selects the HIF address bit used as column address bit 4. Valid - Range: 0 to 7 Internal Base: 2 The selected HIF address bit is determined by adding the internal base to the value of this fi - ld. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=8 or 16, it is required to program this to 0.*/ +/* +* - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 2. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 3. - Quarter bus width mode: Selects the HIF address bit + * used as column address bit 4. Valid Range: 0 to 7 Internal Base: 2 The s + * elected HIF address bit is determined by adding the internal base to the + * value of this field. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=8 + * or 16, it is required to program this to 0. +*/ #undef DDRC_ADDRMAP2_ADDRMAP_COL_B2_DEFVAL #undef DDRC_ADDRMAP2_ADDRMAP_COL_B2_SHIFT #undef DDRC_ADDRMAP2_ADDRMAP_COL_B2_MASK -#define DDRC_ADDRMAP2_ADDRMAP_COL_B2_DEFVAL 0x00000000 -#define DDRC_ADDRMAP2_ADDRMAP_COL_B2_SHIFT 0 -#define DDRC_ADDRMAP2_ADDRMAP_COL_B2_MASK 0x0000000FU +#define DDRC_ADDRMAP2_ADDRMAP_COL_B2_DEFVAL 0x00000000 +#define DDRC_ADDRMAP2_ADDRMAP_COL_B2_SHIFT 0 +#define DDRC_ADDRMAP2_ADDRMAP_COL_B2_MASK 0x0000000FU -/*- Full bus width mode: Selects the HIF address bit used as column address bit 9. - Half bus width mode: Selects the HIF addre - s bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). - Quarter bus width mode: Selects the HIF address bit used as - column address bit 13 (11 in LPDDR2/LPDDR3 mode). Valid Range: 0 to 7, and 15 Internal Base: 9 The selected HIF address bit i - determined by adding the internal base to the value of this field. If set to 15, this column address bit is set to 0. Note: - er JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source addr - ss bit can be mapped to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus an - hence column bit 10 is used.*/ +/* +* - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 9. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 11 (10 in LPDDR2/LPDDR3 mode). - Quarter bus width mode: + * Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/ + * LPDDR3 mode). Valid Range: 0 to 7, and 15 Internal Base: 9 The selected + * HIF address bit is determined by adding the internal base to the value o + * f this field. If set to 15, this column address bit is set to 0. Note: P + * er JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved fo + * r indicating auto-precharge, and hence no source address bit can be mapp + * ed to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit + * for auto-precharge in the CA bus and hence column bit 10 is used. +*/ #undef DDRC_ADDRMAP3_ADDRMAP_COL_B9_DEFVAL #undef DDRC_ADDRMAP3_ADDRMAP_COL_B9_SHIFT #undef DDRC_ADDRMAP3_ADDRMAP_COL_B9_MASK -#define DDRC_ADDRMAP3_ADDRMAP_COL_B9_DEFVAL 0x00000000 -#define DDRC_ADDRMAP3_ADDRMAP_COL_B9_SHIFT 24 -#define DDRC_ADDRMAP3_ADDRMAP_COL_B9_MASK 0x0F000000U +#define DDRC_ADDRMAP3_ADDRMAP_COL_B9_DEFVAL 0x00000000 +#define DDRC_ADDRMAP3_ADDRMAP_COL_B9_SHIFT 24 +#define DDRC_ADDRMAP3_ADDRMAP_COL_B9_MASK 0x0F000000U -/*- Full bus width mode: Selects the HIF address bit used as column address bit 8. - Half bus width mode: Selects the HIF addre - s bit used as column address bit 9. - Quarter bus width mode: Selects the HIF address bit used as column address bit 11 (10 i - LPDDR2/LPDDR3 mode). Valid Range: 0 to 7, and 15 Internal Base: 8 The selected HIF address bit is determined by adding the i - ternal base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specif - cation, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to col - mn address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and hence column bit 10 is use - .*/ +/* +* - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 8. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 9. - Quarter bus width mode: Selects the HIF address bit + * used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). Valid Range: 0 + * to 7, and 15 Internal Base: 8 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specifi + * cation, column address bit 10 is reserved for indicating auto-precharge, + * and hence no source address bit can be mapped to column address bit 10. + * In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA + * bus and hence column bit 10 is used. +*/ #undef DDRC_ADDRMAP3_ADDRMAP_COL_B8_DEFVAL #undef DDRC_ADDRMAP3_ADDRMAP_COL_B8_SHIFT #undef DDRC_ADDRMAP3_ADDRMAP_COL_B8_MASK -#define DDRC_ADDRMAP3_ADDRMAP_COL_B8_DEFVAL 0x00000000 -#define DDRC_ADDRMAP3_ADDRMAP_COL_B8_SHIFT 16 -#define DDRC_ADDRMAP3_ADDRMAP_COL_B8_MASK 0x000F0000U +#define DDRC_ADDRMAP3_ADDRMAP_COL_B8_DEFVAL 0x00000000 +#define DDRC_ADDRMAP3_ADDRMAP_COL_B8_SHIFT 16 +#define DDRC_ADDRMAP3_ADDRMAP_COL_B8_MASK 0x000F0000U -/*- Full bus width mode: Selects the HIF address bit used as column address bit 7. - Half bus width mode: Selects the HIF addre - s bit used as column address bit 8. - Quarter bus width mode: Selects the HIF address bit used as column address bit 9. Valid - Range: 0 to 7, and 15 Internal Base: 7 The selected HIF address bit is determined by adding the internal base to the value of - this field. If set to 15, this column address bit is set to 0.*/ +/* +* - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 7. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 8. - Quarter bus width mode: Selects the HIF address bit + * used as column address bit 9. Valid Range: 0 to 7, and 15 Internal Base: + * 7 The selected HIF address bit is determined by adding the internal bas + * e to the value of this field. If set to 15, this column address bit is s + * et to 0. +*/ #undef DDRC_ADDRMAP3_ADDRMAP_COL_B7_DEFVAL #undef DDRC_ADDRMAP3_ADDRMAP_COL_B7_SHIFT #undef DDRC_ADDRMAP3_ADDRMAP_COL_B7_MASK -#define DDRC_ADDRMAP3_ADDRMAP_COL_B7_DEFVAL 0x00000000 -#define DDRC_ADDRMAP3_ADDRMAP_COL_B7_SHIFT 8 -#define DDRC_ADDRMAP3_ADDRMAP_COL_B7_MASK 0x00000F00U +#define DDRC_ADDRMAP3_ADDRMAP_COL_B7_DEFVAL 0x00000000 +#define DDRC_ADDRMAP3_ADDRMAP_COL_B7_SHIFT 8 +#define DDRC_ADDRMAP3_ADDRMAP_COL_B7_MASK 0x00000F00U -/*- Full bus width mode: Selects the HIF address bit used as column address bit 6. - Half bus width mode: Selects the HIF addre - s bit used as column address bit 7. - Quarter bus width mode: Selects the HIF address bit used as column address bit 8. Valid - Range: 0 to 7, and 15 Internal Base: 6 The selected HIF address bit is determined by adding the internal base to the value of - this field. If set to 15, this column address bit is set to 0.*/ +/* +* - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 6. - Half bus width mode: Selects the HIF address bit used as colu + * mn address bit 7. - Quarter bus width mode: Selects the HIF address bit + * used as column address bit 8. Valid Range: 0 to 7, and 15 Internal Base: + * 6 The selected HIF address bit is determined by adding the internal bas + * e to the value of this field. If set to 15, this column address bit is s + * et to 0. +*/ #undef DDRC_ADDRMAP3_ADDRMAP_COL_B6_DEFVAL #undef DDRC_ADDRMAP3_ADDRMAP_COL_B6_SHIFT #undef DDRC_ADDRMAP3_ADDRMAP_COL_B6_MASK -#define DDRC_ADDRMAP3_ADDRMAP_COL_B6_DEFVAL 0x00000000 -#define DDRC_ADDRMAP3_ADDRMAP_COL_B6_SHIFT 0 -#define DDRC_ADDRMAP3_ADDRMAP_COL_B6_MASK 0x0000000FU +#define DDRC_ADDRMAP3_ADDRMAP_COL_B6_DEFVAL 0x00000000 +#define DDRC_ADDRMAP3_ADDRMAP_COL_B6_SHIFT 0 +#define DDRC_ADDRMAP3_ADDRMAP_COL_B6_MASK 0x0000000FU -/*- Full bus width mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode). - Half bus width - mode: Unused. To make it unused, this should be tied to 4'hF. - Quarter bus width mode: Unused. To make it unused, this must - e tied to 4'hF. Valid Range: 0 to 7, and 15 Internal Base: 11 The selected HIF address bit is determined by adding the intern - l base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specificati - n, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column a - dress bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and hence column bit 10 is used.*/ +/* +* - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 13 (11 in LPDDR2/LPDDR3 mode). - Half bus width mode: Unused. To m + * ake it unused, this should be tied to 4'hF. - Quarter bus width mode: Un + * used. To make it unused, this must be tied to 4'hF. Valid Range: 0 to 7, + * and 15 Internal Base: 11 The selected HIF address bit is determined by + * adding the internal base to the value of this field. If set to 15, this + * column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specificatio + * n, column address bit 10 is reserved for indicating auto-precharge, and + * hence no source address bit can be mapped to column address bit 10. In L + * PDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus + * and hence column bit 10 is used. +*/ #undef DDRC_ADDRMAP4_ADDRMAP_COL_B11_DEFVAL #undef DDRC_ADDRMAP4_ADDRMAP_COL_B11_SHIFT #undef DDRC_ADDRMAP4_ADDRMAP_COL_B11_MASK -#define DDRC_ADDRMAP4_ADDRMAP_COL_B11_DEFVAL 0x00000000 -#define DDRC_ADDRMAP4_ADDRMAP_COL_B11_SHIFT 8 -#define DDRC_ADDRMAP4_ADDRMAP_COL_B11_MASK 0x00000F00U +#define DDRC_ADDRMAP4_ADDRMAP_COL_B11_DEFVAL 0x00000000 +#define DDRC_ADDRMAP4_ADDRMAP_COL_B11_SHIFT 8 +#define DDRC_ADDRMAP4_ADDRMAP_COL_B11_MASK 0x00000F00U -/*- Full bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). - Half bus width - mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode). - Quarter bus width mode: UNUSED. - To make it unused, this must be tied to 4'hF. Valid Range: 0 to 7, and 15 Internal Base: 10 The selected HIF address bit is d - termined by adding the internal base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per - JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source address - bit can be mapped to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and h - nce column bit 10 is used.*/ +/* +* - Full bus width mode: Selects the HIF address bit used as column addres + * s bit 11 (10 in LPDDR2/LPDDR3 mode). - Half bus width mode: Selects the + * HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode) + * . - Quarter bus width mode: UNUSED. To make it unused, this must be tied + * to 4'hF. Valid Range: 0 to 7, and 15 Internal Base: 10 The selected HIF + * address bit is determined by adding the internal base to the value of t + * his field. If set to 15, this column address bit is set to 0. Note: Per + * JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for i + * ndicating auto-precharge, and hence no source address bit can be mapped + * to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for + * auto-precharge in the CA bus and hence column bit 10 is used. +*/ #undef DDRC_ADDRMAP4_ADDRMAP_COL_B10_DEFVAL #undef DDRC_ADDRMAP4_ADDRMAP_COL_B10_SHIFT #undef DDRC_ADDRMAP4_ADDRMAP_COL_B10_MASK -#define DDRC_ADDRMAP4_ADDRMAP_COL_B10_DEFVAL 0x00000000 -#define DDRC_ADDRMAP4_ADDRMAP_COL_B10_SHIFT 0 -#define DDRC_ADDRMAP4_ADDRMAP_COL_B10_MASK 0x0000000FU +#define DDRC_ADDRMAP4_ADDRMAP_COL_B10_DEFVAL 0x00000000 +#define DDRC_ADDRMAP4_ADDRMAP_COL_B10_SHIFT 0 +#define DDRC_ADDRMAP4_ADDRMAP_COL_B10_MASK 0x0000000FU -/*Selects the HIF address bit used as row address bit 11. Valid Range: 0 to 11, and 15 Internal Base: 17 The selected HIF addre - s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 11 is set to 0.*/ +/* +* Selects the HIF address bit used as row address bit 11. Valid Range: 0 t + * o 11, and 15 Internal Base: 17 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * row address bit 11 is set to 0. +*/ #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B11_DEFVAL #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B11_SHIFT #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B11_MASK -#define DDRC_ADDRMAP5_ADDRMAP_ROW_B11_DEFVAL 0x00000000 -#define DDRC_ADDRMAP5_ADDRMAP_ROW_B11_SHIFT 24 -#define DDRC_ADDRMAP5_ADDRMAP_ROW_B11_MASK 0x0F000000U +#define DDRC_ADDRMAP5_ADDRMAP_ROW_B11_DEFVAL 0x00000000 +#define DDRC_ADDRMAP5_ADDRMAP_ROW_B11_SHIFT 24 +#define DDRC_ADDRMAP5_ADDRMAP_ROW_B11_MASK 0x0F000000U -/*Selects the HIF address bits used as row address bits 2 to 10. Valid Range: 0 to 11, and 15 Internal Base: 8 (for row address - bit 2), 9 (for row address bit 3), 10 (for row address bit 4) etc increasing to 16 (for row address bit 10) The selected HIF - ddress bit for each of the row address bits is determined by adding the internal base to the value of this field. When value - 5 is used the values of row address bits 2 to 10 are defined by registers ADDRMAP9, ADDRMAP10, ADDRMAP11.*/ +/* +* Selects the HIF address bits used as row address bits 2 to 10. Valid Ran + * ge: 0 to 11, and 15 Internal Base: 8 (for row address bit 2), 9 (for row + * address bit 3), 10 (for row address bit 4) etc increasing to 16 (for ro + * w address bit 10) The selected HIF address bit for each of the row addre + * ss bits is determined by adding the internal base to the value of this f + * ield. When value 15 is used the values of row address bits 2 to 10 are d + * efined by registers ADDRMAP9, ADDRMAP10, ADDRMAP11. +*/ #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_DEFVAL #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_SHIFT #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_MASK -#define DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_DEFVAL 0x00000000 -#define DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_SHIFT 16 -#define DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_MASK 0x000F0000U +#define DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_DEFVAL 0x00000000 +#define DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_SHIFT 16 +#define DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_MASK 0x000F0000U -/*Selects the HIF address bits used as row address bit 1. Valid Range: 0 to 11 Internal Base: 7 The selected HIF address bit fo - each of the row address bits is determined by adding the internal base to the value of this field.*/ +/* +* Selects the HIF address bits used as row address bit 1. Valid Range: 0 t + * o 11 Internal Base: 7 The selected HIF address bit for each of the row a + * ddress bits is determined by adding the internal base to the value of th + * is field. +*/ #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B1_DEFVAL #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B1_SHIFT #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B1_MASK -#define DDRC_ADDRMAP5_ADDRMAP_ROW_B1_DEFVAL 0x00000000 -#define DDRC_ADDRMAP5_ADDRMAP_ROW_B1_SHIFT 8 -#define DDRC_ADDRMAP5_ADDRMAP_ROW_B1_MASK 0x00000F00U +#define DDRC_ADDRMAP5_ADDRMAP_ROW_B1_DEFVAL 0x00000000 +#define DDRC_ADDRMAP5_ADDRMAP_ROW_B1_SHIFT 8 +#define DDRC_ADDRMAP5_ADDRMAP_ROW_B1_MASK 0x00000F00U -/*Selects the HIF address bits used as row address bit 0. Valid Range: 0 to 11 Internal Base: 6 The selected HIF address bit fo - each of the row address bits is determined by adding the internal base to the value of this field.*/ +/* +* Selects the HIF address bits used as row address bit 0. Valid Range: 0 t + * o 11 Internal Base: 6 The selected HIF address bit for each of the row a + * ddress bits is determined by adding the internal base to the value of th + * is field. +*/ #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B0_DEFVAL #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B0_SHIFT #undef DDRC_ADDRMAP5_ADDRMAP_ROW_B0_MASK -#define DDRC_ADDRMAP5_ADDRMAP_ROW_B0_DEFVAL 0x00000000 -#define DDRC_ADDRMAP5_ADDRMAP_ROW_B0_SHIFT 0 -#define DDRC_ADDRMAP5_ADDRMAP_ROW_B0_MASK 0x0000000FU +#define DDRC_ADDRMAP5_ADDRMAP_ROW_B0_DEFVAL 0x00000000 +#define DDRC_ADDRMAP5_ADDRMAP_ROW_B0_SHIFT 0 +#define DDRC_ADDRMAP5_ADDRMAP_ROW_B0_MASK 0x0000000FU -/*Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use. - 1 - LPDDR3 SDRAM 6Gb/12Gb device in use. Every address - having row[14:13]==2'b11 is considered as invalid - 0 - non-LPDDR3 6Gb/12Gb device in use. All addresses are valid Present on - y in designs configured to support LPDDR3.*/ +/* +* Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use. - 1 + * - LPDDR3 SDRAM 6Gb/12Gb device in use. Every address having row[14:13]= + * =2'b11 is considered as invalid - 0 - non-LPDDR3 6Gb/12Gb device in use. + * All addresses are valid Present only in designs configured to support L + * PDDR3. +*/ #undef DDRC_ADDRMAP6_LPDDR3_6GB_12GB_DEFVAL #undef DDRC_ADDRMAP6_LPDDR3_6GB_12GB_SHIFT #undef DDRC_ADDRMAP6_LPDDR3_6GB_12GB_MASK -#define DDRC_ADDRMAP6_LPDDR3_6GB_12GB_DEFVAL 0x00000000 -#define DDRC_ADDRMAP6_LPDDR3_6GB_12GB_SHIFT 31 -#define DDRC_ADDRMAP6_LPDDR3_6GB_12GB_MASK 0x80000000U +#define DDRC_ADDRMAP6_LPDDR3_6GB_12GB_DEFVAL 0x00000000 +#define DDRC_ADDRMAP6_LPDDR3_6GB_12GB_SHIFT 31 +#define DDRC_ADDRMAP6_LPDDR3_6GB_12GB_MASK 0x80000000U -/*Selects the HIF address bit used as row address bit 15. Valid Range: 0 to 11, and 15 Internal Base: 21 The selected HIF addre - s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 15 is set to 0.*/ +/* +* Selects the HIF address bit used as row address bit 15. Valid Range: 0 t + * o 11, and 15 Internal Base: 21 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * row address bit 15 is set to 0. +*/ #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B15_DEFVAL #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B15_SHIFT #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B15_MASK -#define DDRC_ADDRMAP6_ADDRMAP_ROW_B15_DEFVAL 0x00000000 -#define DDRC_ADDRMAP6_ADDRMAP_ROW_B15_SHIFT 24 -#define DDRC_ADDRMAP6_ADDRMAP_ROW_B15_MASK 0x0F000000U +#define DDRC_ADDRMAP6_ADDRMAP_ROW_B15_DEFVAL 0x00000000 +#define DDRC_ADDRMAP6_ADDRMAP_ROW_B15_SHIFT 24 +#define DDRC_ADDRMAP6_ADDRMAP_ROW_B15_MASK 0x0F000000U -/*Selects the HIF address bit used as row address bit 14. Valid Range: 0 to 11, and 15 Internal Base: 20 The selected HIF addre - s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 14 is set to 0.*/ +/* +* Selects the HIF address bit used as row address bit 14. Valid Range: 0 t + * o 11, and 15 Internal Base: 20 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * row address bit 14 is set to 0. +*/ #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B14_DEFVAL #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B14_SHIFT #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B14_MASK -#define DDRC_ADDRMAP6_ADDRMAP_ROW_B14_DEFVAL 0x00000000 -#define DDRC_ADDRMAP6_ADDRMAP_ROW_B14_SHIFT 16 -#define DDRC_ADDRMAP6_ADDRMAP_ROW_B14_MASK 0x000F0000U +#define DDRC_ADDRMAP6_ADDRMAP_ROW_B14_DEFVAL 0x00000000 +#define DDRC_ADDRMAP6_ADDRMAP_ROW_B14_SHIFT 16 +#define DDRC_ADDRMAP6_ADDRMAP_ROW_B14_MASK 0x000F0000U -/*Selects the HIF address bit used as row address bit 13. Valid Range: 0 to 11, and 15 Internal Base: 19 The selected HIF addre - s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 13 is set to 0.*/ +/* +* Selects the HIF address bit used as row address bit 13. Valid Range: 0 t + * o 11, and 15 Internal Base: 19 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * row address bit 13 is set to 0. +*/ #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B13_DEFVAL #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B13_SHIFT #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B13_MASK -#define DDRC_ADDRMAP6_ADDRMAP_ROW_B13_DEFVAL 0x00000000 -#define DDRC_ADDRMAP6_ADDRMAP_ROW_B13_SHIFT 8 -#define DDRC_ADDRMAP6_ADDRMAP_ROW_B13_MASK 0x00000F00U +#define DDRC_ADDRMAP6_ADDRMAP_ROW_B13_DEFVAL 0x00000000 +#define DDRC_ADDRMAP6_ADDRMAP_ROW_B13_SHIFT 8 +#define DDRC_ADDRMAP6_ADDRMAP_ROW_B13_MASK 0x00000F00U -/*Selects the HIF address bit used as row address bit 12. Valid Range: 0 to 11, and 15 Internal Base: 18 The selected HIF addre - s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 12 is set to 0.*/ +/* +* Selects the HIF address bit used as row address bit 12. Valid Range: 0 t + * o 11, and 15 Internal Base: 18 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * row address bit 12 is set to 0. +*/ #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B12_DEFVAL #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B12_SHIFT #undef DDRC_ADDRMAP6_ADDRMAP_ROW_B12_MASK -#define DDRC_ADDRMAP6_ADDRMAP_ROW_B12_DEFVAL 0x00000000 -#define DDRC_ADDRMAP6_ADDRMAP_ROW_B12_SHIFT 0 -#define DDRC_ADDRMAP6_ADDRMAP_ROW_B12_MASK 0x0000000FU +#define DDRC_ADDRMAP6_ADDRMAP_ROW_B12_DEFVAL 0x00000000 +#define DDRC_ADDRMAP6_ADDRMAP_ROW_B12_SHIFT 0 +#define DDRC_ADDRMAP6_ADDRMAP_ROW_B12_MASK 0x0000000FU -/*Selects the HIF address bit used as row address bit 17. Valid Range: 0 to 10, and 15 Internal Base: 23 The selected HIF addre - s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 17 is set to 0.*/ +/* +* Selects the HIF address bit used as row address bit 17. Valid Range: 0 t + * o 10, and 15 Internal Base: 23 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * row address bit 17 is set to 0. +*/ #undef DDRC_ADDRMAP7_ADDRMAP_ROW_B17_DEFVAL #undef DDRC_ADDRMAP7_ADDRMAP_ROW_B17_SHIFT #undef DDRC_ADDRMAP7_ADDRMAP_ROW_B17_MASK -#define DDRC_ADDRMAP7_ADDRMAP_ROW_B17_DEFVAL 0x00000000 -#define DDRC_ADDRMAP7_ADDRMAP_ROW_B17_SHIFT 8 -#define DDRC_ADDRMAP7_ADDRMAP_ROW_B17_MASK 0x00000F00U +#define DDRC_ADDRMAP7_ADDRMAP_ROW_B17_DEFVAL 0x00000000 +#define DDRC_ADDRMAP7_ADDRMAP_ROW_B17_SHIFT 8 +#define DDRC_ADDRMAP7_ADDRMAP_ROW_B17_MASK 0x00000F00U -/*Selects the HIF address bit used as row address bit 16. Valid Range: 0 to 11, and 15 Internal Base: 22 The selected HIF addre - s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 16 is set to 0.*/ +/* +* Selects the HIF address bit used as row address bit 16. Valid Range: 0 t + * o 11, and 15 Internal Base: 22 The selected HIF address bit is determine + * d by adding the internal base to the value of this field. If set to 15, + * row address bit 16 is set to 0. +*/ #undef DDRC_ADDRMAP7_ADDRMAP_ROW_B16_DEFVAL #undef DDRC_ADDRMAP7_ADDRMAP_ROW_B16_SHIFT #undef DDRC_ADDRMAP7_ADDRMAP_ROW_B16_MASK -#define DDRC_ADDRMAP7_ADDRMAP_ROW_B16_DEFVAL 0x00000000 -#define DDRC_ADDRMAP7_ADDRMAP_ROW_B16_SHIFT 0 -#define DDRC_ADDRMAP7_ADDRMAP_ROW_B16_MASK 0x0000000FU +#define DDRC_ADDRMAP7_ADDRMAP_ROW_B16_DEFVAL 0x00000000 +#define DDRC_ADDRMAP7_ADDRMAP_ROW_B16_SHIFT 0 +#define DDRC_ADDRMAP7_ADDRMAP_ROW_B16_MASK 0x0000000FU -/*Selects the HIF address bits used as bank group address bit 1. Valid Range: 0 to 30, and 31 Internal Base: 3 The selected HIF - address bit for each of the bank group address bits is determined by adding the internal base to the value of this field. If - et to 31, bank group address bit 1 is set to 0.*/ +/* +* Selects the HIF address bits used as bank group address bit 1. Valid Ran + * ge: 0 to 30, and 31 Internal Base: 3 The selected HIF address bit for ea + * ch of the bank group address bits is determined by adding the internal b + * ase to the value of this field. If set to 31, bank group address bit 1 i + * s set to 0. +*/ #undef DDRC_ADDRMAP8_ADDRMAP_BG_B1_DEFVAL #undef DDRC_ADDRMAP8_ADDRMAP_BG_B1_SHIFT #undef DDRC_ADDRMAP8_ADDRMAP_BG_B1_MASK -#define DDRC_ADDRMAP8_ADDRMAP_BG_B1_DEFVAL 0x00000000 -#define DDRC_ADDRMAP8_ADDRMAP_BG_B1_SHIFT 8 -#define DDRC_ADDRMAP8_ADDRMAP_BG_B1_MASK 0x00001F00U +#define DDRC_ADDRMAP8_ADDRMAP_BG_B1_DEFVAL 0x00000000 +#define DDRC_ADDRMAP8_ADDRMAP_BG_B1_SHIFT 8 +#define DDRC_ADDRMAP8_ADDRMAP_BG_B1_MASK 0x00001F00U -/*Selects the HIF address bits used as bank group address bit 0. Valid Range: 0 to 30 Internal Base: 2 The selected HIF address - bit for each of the bank group address bits is determined by adding the internal base to the value of this field.*/ +/* +* Selects the HIF address bits used as bank group address bit 0. Valid Ran + * ge: 0 to 30 Internal Base: 2 The selected HIF address bit for each of th + * e bank group address bits is determined by adding the internal base to t + * he value of this field. +*/ #undef DDRC_ADDRMAP8_ADDRMAP_BG_B0_DEFVAL #undef DDRC_ADDRMAP8_ADDRMAP_BG_B0_SHIFT #undef DDRC_ADDRMAP8_ADDRMAP_BG_B0_MASK -#define DDRC_ADDRMAP8_ADDRMAP_BG_B0_DEFVAL 0x00000000 -#define DDRC_ADDRMAP8_ADDRMAP_BG_B0_SHIFT 0 -#define DDRC_ADDRMAP8_ADDRMAP_BG_B0_MASK 0x0000001FU +#define DDRC_ADDRMAP8_ADDRMAP_BG_B0_DEFVAL 0x00000000 +#define DDRC_ADDRMAP8_ADDRMAP_BG_B0_SHIFT 0 +#define DDRC_ADDRMAP8_ADDRMAP_BG_B0_MASK 0x0000001FU -/*Selects the HIF address bits used as row address bit 5. Valid Range: 0 to 11 Internal Base: 11 The selected HIF address bit f - r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u - ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/ +/* +* Selects the HIF address bits used as row address bit 5. Valid Range: 0 t + * o 11 Internal Base: 11 The selected HIF address bit for each of the row + * address bits is determined by adding the internal base to the value of t + * his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + * _10 is set to value 15. +*/ #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B5_DEFVAL #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B5_SHIFT #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B5_MASK -#define DDRC_ADDRMAP9_ADDRMAP_ROW_B5_DEFVAL 0x00000000 -#define DDRC_ADDRMAP9_ADDRMAP_ROW_B5_SHIFT 24 -#define DDRC_ADDRMAP9_ADDRMAP_ROW_B5_MASK 0x0F000000U +#define DDRC_ADDRMAP9_ADDRMAP_ROW_B5_DEFVAL 0x00000000 +#define DDRC_ADDRMAP9_ADDRMAP_ROW_B5_SHIFT 24 +#define DDRC_ADDRMAP9_ADDRMAP_ROW_B5_MASK 0x0F000000U -/*Selects the HIF address bits used as row address bit 4. Valid Range: 0 to 11 Internal Base: 10 The selected HIF address bit f - r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u - ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/ +/* +* Selects the HIF address bits used as row address bit 4. Valid Range: 0 t + * o 11 Internal Base: 10 The selected HIF address bit for each of the row + * address bits is determined by adding the internal base to the value of t + * his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + * _10 is set to value 15. +*/ #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B4_DEFVAL #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B4_SHIFT #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B4_MASK -#define DDRC_ADDRMAP9_ADDRMAP_ROW_B4_DEFVAL 0x00000000 -#define DDRC_ADDRMAP9_ADDRMAP_ROW_B4_SHIFT 16 -#define DDRC_ADDRMAP9_ADDRMAP_ROW_B4_MASK 0x000F0000U +#define DDRC_ADDRMAP9_ADDRMAP_ROW_B4_DEFVAL 0x00000000 +#define DDRC_ADDRMAP9_ADDRMAP_ROW_B4_SHIFT 16 +#define DDRC_ADDRMAP9_ADDRMAP_ROW_B4_MASK 0x000F0000U -/*Selects the HIF address bits used as row address bit 3. Valid Range: 0 to 11 Internal Base: 9 The selected HIF address bit fo - each of the row address bits is determined by adding the internal base to the value of this field. This register field is us - d only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/ +/* +* Selects the HIF address bits used as row address bit 3. Valid Range: 0 t + * o 11 Internal Base: 9 The selected HIF address bit for each of the row a + * ddress bits is determined by adding the internal base to the value of th + * is field. This register field is used only when ADDRMAP5.addrmap_row_b2_ + * 10 is set to value 15. +*/ #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B3_DEFVAL #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B3_SHIFT #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B3_MASK -#define DDRC_ADDRMAP9_ADDRMAP_ROW_B3_DEFVAL 0x00000000 -#define DDRC_ADDRMAP9_ADDRMAP_ROW_B3_SHIFT 8 -#define DDRC_ADDRMAP9_ADDRMAP_ROW_B3_MASK 0x00000F00U +#define DDRC_ADDRMAP9_ADDRMAP_ROW_B3_DEFVAL 0x00000000 +#define DDRC_ADDRMAP9_ADDRMAP_ROW_B3_SHIFT 8 +#define DDRC_ADDRMAP9_ADDRMAP_ROW_B3_MASK 0x00000F00U -/*Selects the HIF address bits used as row address bit 2. Valid Range: 0 to 11 Internal Base: 8 The selected HIF address bit fo - each of the row address bits is determined by adding the internal base to the value of this field. This register field is us - d only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/ +/* +* Selects the HIF address bits used as row address bit 2. Valid Range: 0 t + * o 11 Internal Base: 8 The selected HIF address bit for each of the row a + * ddress bits is determined by adding the internal base to the value of th + * is field. This register field is used only when ADDRMAP5.addrmap_row_b2_ + * 10 is set to value 15. +*/ #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B2_DEFVAL #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B2_SHIFT #undef DDRC_ADDRMAP9_ADDRMAP_ROW_B2_MASK -#define DDRC_ADDRMAP9_ADDRMAP_ROW_B2_DEFVAL 0x00000000 -#define DDRC_ADDRMAP9_ADDRMAP_ROW_B2_SHIFT 0 -#define DDRC_ADDRMAP9_ADDRMAP_ROW_B2_MASK 0x0000000FU +#define DDRC_ADDRMAP9_ADDRMAP_ROW_B2_DEFVAL 0x00000000 +#define DDRC_ADDRMAP9_ADDRMAP_ROW_B2_SHIFT 0 +#define DDRC_ADDRMAP9_ADDRMAP_ROW_B2_MASK 0x0000000FU -/*Selects the HIF address bits used as row address bit 9. Valid Range: 0 to 11 Internal Base: 15 The selected HIF address bit f - r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u - ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/ +/* +* Selects the HIF address bits used as row address bit 9. Valid Range: 0 t + * o 11 Internal Base: 15 The selected HIF address bit for each of the row + * address bits is determined by adding the internal base to the value of t + * his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + * _10 is set to value 15. +*/ #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B9_DEFVAL #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B9_SHIFT #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B9_MASK -#define DDRC_ADDRMAP10_ADDRMAP_ROW_B9_DEFVAL 0x00000000 -#define DDRC_ADDRMAP10_ADDRMAP_ROW_B9_SHIFT 24 -#define DDRC_ADDRMAP10_ADDRMAP_ROW_B9_MASK 0x0F000000U +#define DDRC_ADDRMAP10_ADDRMAP_ROW_B9_DEFVAL 0x00000000 +#define DDRC_ADDRMAP10_ADDRMAP_ROW_B9_SHIFT 24 +#define DDRC_ADDRMAP10_ADDRMAP_ROW_B9_MASK 0x0F000000U -/*Selects the HIF address bits used as row address bit 8. Valid Range: 0 to 11 Internal Base: 14 The selected HIF address bit f - r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u - ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/ +/* +* Selects the HIF address bits used as row address bit 8. Valid Range: 0 t + * o 11 Internal Base: 14 The selected HIF address bit for each of the row + * address bits is determined by adding the internal base to the value of t + * his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + * _10 is set to value 15. +*/ #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B8_DEFVAL #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B8_SHIFT #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B8_MASK -#define DDRC_ADDRMAP10_ADDRMAP_ROW_B8_DEFVAL 0x00000000 -#define DDRC_ADDRMAP10_ADDRMAP_ROW_B8_SHIFT 16 -#define DDRC_ADDRMAP10_ADDRMAP_ROW_B8_MASK 0x000F0000U +#define DDRC_ADDRMAP10_ADDRMAP_ROW_B8_DEFVAL 0x00000000 +#define DDRC_ADDRMAP10_ADDRMAP_ROW_B8_SHIFT 16 +#define DDRC_ADDRMAP10_ADDRMAP_ROW_B8_MASK 0x000F0000U -/*Selects the HIF address bits used as row address bit 7. Valid Range: 0 to 11 Internal Base: 13 The selected HIF address bit f - r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u - ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/ +/* +* Selects the HIF address bits used as row address bit 7. Valid Range: 0 t + * o 11 Internal Base: 13 The selected HIF address bit for each of the row + * address bits is determined by adding the internal base to the value of t + * his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + * _10 is set to value 15. +*/ #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B7_DEFVAL #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B7_SHIFT #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B7_MASK -#define DDRC_ADDRMAP10_ADDRMAP_ROW_B7_DEFVAL 0x00000000 -#define DDRC_ADDRMAP10_ADDRMAP_ROW_B7_SHIFT 8 -#define DDRC_ADDRMAP10_ADDRMAP_ROW_B7_MASK 0x00000F00U +#define DDRC_ADDRMAP10_ADDRMAP_ROW_B7_DEFVAL 0x00000000 +#define DDRC_ADDRMAP10_ADDRMAP_ROW_B7_SHIFT 8 +#define DDRC_ADDRMAP10_ADDRMAP_ROW_B7_MASK 0x00000F00U -/*Selects the HIF address bits used as row address bit 6. Valid Range: 0 to 11 Internal Base: 12 The selected HIF address bit f - r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u - ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/ +/* +* Selects the HIF address bits used as row address bit 6. Valid Range: 0 t + * o 11 Internal Base: 12 The selected HIF address bit for each of the row + * address bits is determined by adding the internal base to the value of t + * his field. This register field is used only when ADDRMAP5.addrmap_row_b2 + * _10 is set to value 15. +*/ #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B6_DEFVAL #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B6_SHIFT #undef DDRC_ADDRMAP10_ADDRMAP_ROW_B6_MASK -#define DDRC_ADDRMAP10_ADDRMAP_ROW_B6_DEFVAL 0x00000000 -#define DDRC_ADDRMAP10_ADDRMAP_ROW_B6_SHIFT 0 -#define DDRC_ADDRMAP10_ADDRMAP_ROW_B6_MASK 0x0000000FU +#define DDRC_ADDRMAP10_ADDRMAP_ROW_B6_DEFVAL 0x00000000 +#define DDRC_ADDRMAP10_ADDRMAP_ROW_B6_SHIFT 0 +#define DDRC_ADDRMAP10_ADDRMAP_ROW_B6_MASK 0x0000000FU -/*Selects the HIF address bits used as row address bit 10. Valid Range: 0 to 11 Internal Base: 16 The selected HIF address bit - or each of the row address bits is determined by adding the internal base to the value of this field. This register field is - sed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/ +/* +* Selects the HIF address bits used as row address bit 10. Valid Range: 0 + * to 11 Internal Base: 16 The selected HIF address bit for each of the row + * address bits is determined by adding the internal base to the value of + * this field. This register field is used only when ADDRMAP5.addrmap_row_b + * 2_10 is set to value 15. +*/ #undef DDRC_ADDRMAP11_ADDRMAP_ROW_B10_DEFVAL #undef DDRC_ADDRMAP11_ADDRMAP_ROW_B10_SHIFT #undef DDRC_ADDRMAP11_ADDRMAP_ROW_B10_MASK -#define DDRC_ADDRMAP11_ADDRMAP_ROW_B10_DEFVAL -#define DDRC_ADDRMAP11_ADDRMAP_ROW_B10_SHIFT 0 -#define DDRC_ADDRMAP11_ADDRMAP_ROW_B10_MASK 0x0000000FU +#define DDRC_ADDRMAP11_ADDRMAP_ROW_B10_DEFVAL +#define DDRC_ADDRMAP11_ADDRMAP_ROW_B10_SHIFT 0 +#define DDRC_ADDRMAP11_ADDRMAP_ROW_B10_MASK 0x0000000FU -/*Cycles to hold ODT for a write command. The minimum supported value is 2. Recommended values: DDR2: - BL8: 0x5 (DDR2-400/533/ - 67), 0x6 (DDR2-800), 0x7 (DDR2-1066) - BL4: 0x3 (DDR2-400/533/667), 0x4 (DDR2-800), 0x5 (DDR2-1066) DDR3: - BL8: 0x6 DDR4: - - L8: 5 + WR_PREAMBLE + CRC_MODE WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) CRC_MODE = 0 (not CRC mode), 1 - CRC mode) LPDDR3: - BL8: 7 + RU(tODTon(max)/tCK)*/ +/* +* Cycles to hold ODT for a write command. The minimum supported value is 2 + * . Recommended values: DDR2: - BL8: 0x5 (DDR2-400/533/667), 0x6 (DDR2-800 + * ), 0x7 (DDR2-1066) - BL4: 0x3 (DDR2-400/533/667), 0x4 (DDR2-800), 0x5 (D + * DR2-1066) DDR3: - BL8: 0x6 DDR4: - BL8: 5 + WR_PREAMBLE + CRC_MODE WR_PR + * EAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) CRC_MODE = 0 ( + * not CRC mode), 1 (CRC mode) LPDDR3: - BL8: 7 + RU(tODTon(max)/tCK) +*/ #undef DDRC_ODTCFG_WR_ODT_HOLD_DEFVAL #undef DDRC_ODTCFG_WR_ODT_HOLD_SHIFT #undef DDRC_ODTCFG_WR_ODT_HOLD_MASK -#define DDRC_ODTCFG_WR_ODT_HOLD_DEFVAL 0x04000400 -#define DDRC_ODTCFG_WR_ODT_HOLD_SHIFT 24 -#define DDRC_ODTCFG_WR_ODT_HOLD_MASK 0x0F000000U +#define DDRC_ODTCFG_WR_ODT_HOLD_DEFVAL 0x04000400 +#define DDRC_ODTCFG_WR_ODT_HOLD_SHIFT 24 +#define DDRC_ODTCFG_WR_ODT_HOLD_MASK 0x0F000000U -/*The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting must - remain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: - CWL + AL - 3 (DDR2-400/533/ - 67), CWL + AL - 4 (DDR2-800), CWL + AL - 5 (DDR2-1066) If (CWL + AL - 3 < 0), uMCTL2 does not support ODT for write operation - DDR3: - 0x0 DDR4: - DFITMG1.dfi_t_cmd_lat (to adjust for CAL mode) LPDDR3: - WL - 1 - RU(tODTon(max)/tCK))*/ +/* +* The delay, in clock cycles, from issuing a write command to setting ODT + * values associated with that command. ODT setting must remain constant fo + * r the entire time that DQS is driven by the uMCTL2. Recommended values: + * DDR2: - CWL + AL - 3 (DDR2-400/533/667), CWL + AL - 4 (DDR2-800), CWL + + * AL - 5 (DDR2-1066) If (CWL + AL - 3 < 0), uMCTL2 does not support ODT fo + * r write operation. DDR3: - 0x0 DDR4: - DFITMG1.dfi_t_cmd_lat (to adjust + * for CAL mode) LPDDR3: - WL - 1 - RU(tODTon(max)/tCK)) +*/ #undef DDRC_ODTCFG_WR_ODT_DELAY_DEFVAL #undef DDRC_ODTCFG_WR_ODT_DELAY_SHIFT #undef DDRC_ODTCFG_WR_ODT_DELAY_MASK -#define DDRC_ODTCFG_WR_ODT_DELAY_DEFVAL 0x04000400 -#define DDRC_ODTCFG_WR_ODT_DELAY_SHIFT 16 -#define DDRC_ODTCFG_WR_ODT_DELAY_MASK 0x001F0000U +#define DDRC_ODTCFG_WR_ODT_DELAY_DEFVAL 0x04000400 +#define DDRC_ODTCFG_WR_ODT_DELAY_SHIFT 16 +#define DDRC_ODTCFG_WR_ODT_DELAY_MASK 0x001F0000U -/*Cycles to hold ODT for a read command. The minimum supported value is 2. Recommended values: DDR2: - BL8: 0x6 (not DDR2-1066) - 0x7 (DDR2-1066) - BL4: 0x4 (not DDR2-1066), 0x5 (DDR2-1066) DDR3: - BL8 - 0x6 DDR4: - BL8: 5 + RD_PREAMBLE RD_PREAMBLE = 1 ( - tCK write preamble), 2 (2tCK write preamble) LPDDR3: - BL8: 5 + RU(tDQSCK(max)/tCK) - RD(tDQSCK(min)/tCK) + RU(tODTon(max)/tC - )*/ +/* +* Cycles to hold ODT for a read command. The minimum supported value is 2. + * Recommended values: DDR2: - BL8: 0x6 (not DDR2-1066), 0x7 (DDR2-1066) - + * BL4: 0x4 (not DDR2-1066), 0x5 (DDR2-1066) DDR3: - BL8 - 0x6 DDR4: - BL8 + * : 5 + RD_PREAMBLE RD_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write p + * reamble) LPDDR3: - BL8: 5 + RU(tDQSCK(max)/tCK) - RD(tDQSCK(min)/tCK) + + * RU(tODTon(max)/tCK) +*/ #undef DDRC_ODTCFG_RD_ODT_HOLD_DEFVAL #undef DDRC_ODTCFG_RD_ODT_HOLD_SHIFT #undef DDRC_ODTCFG_RD_ODT_HOLD_MASK -#define DDRC_ODTCFG_RD_ODT_HOLD_DEFVAL 0x04000400 -#define DDRC_ODTCFG_RD_ODT_HOLD_SHIFT 8 -#define DDRC_ODTCFG_RD_ODT_HOLD_MASK 0x00000F00U +#define DDRC_ODTCFG_RD_ODT_HOLD_DEFVAL 0x04000400 +#define DDRC_ODTCFG_RD_ODT_HOLD_SHIFT 8 +#define DDRC_ODTCFG_RD_ODT_HOLD_MASK 0x00000F00U -/*The delay, in clock cycles, from issuing a read command to setting ODT values associated with that command. ODT setting must - emain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: - CL + AL - 4 (not DDR2-1066), - CL + AL - 5 (DDR2-1066) If (CL + AL - 4 < 0), uMCTL2 does not support ODT for read operation. DDR3: - CL - CWL DDR4: - CL - C - L - RD_PREAMBLE + WR_PREAMBLE + DFITMG1.dfi_t_cmd_lat (to adjust for CAL mode) WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK - write preamble) RD_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) If (CL - CWL - RD_PREAMBLE + WR_PREAMBLE) < 0, - uMCTL2 does not support ODT for read operation. LPDDR3: - RL + RD(tDQSCK(min)/tCK) - 1 - RU(tODTon(max)/tCK)*/ +/* +* The delay, in clock cycles, from issuing a read command to setting ODT v + * alues associated with that command. ODT setting must remain constant for + * the entire time that DQS is driven by the uMCTL2. Recommended values: D + * DR2: - CL + AL - 4 (not DDR2-1066), CL + AL - 5 (DDR2-1066) If (CL + AL + * - 4 < 0), uMCTL2 does not support ODT for read operation. DDR3: - CL - C + * WL DDR4: - CL - CWL - RD_PREAMBLE + WR_PREAMBLE + DFITMG1.dfi_t_cmd_lat + * (to adjust for CAL mode) WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK + * write preamble) RD_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write pre + * amble) If (CL - CWL - RD_PREAMBLE + WR_PREAMBLE) < 0, uMCTL2 does not su + * pport ODT for read operation. LPDDR3: - RL + RD(tDQSCK(min)/tCK) - 1 - R + * U(tODTon(max)/tCK) +*/ #undef DDRC_ODTCFG_RD_ODT_DELAY_DEFVAL #undef DDRC_ODTCFG_RD_ODT_DELAY_SHIFT #undef DDRC_ODTCFG_RD_ODT_DELAY_MASK -#define DDRC_ODTCFG_RD_ODT_DELAY_DEFVAL 0x04000400 -#define DDRC_ODTCFG_RD_ODT_DELAY_SHIFT 2 -#define DDRC_ODTCFG_RD_ODT_DELAY_MASK 0x0000007CU +#define DDRC_ODTCFG_RD_ODT_DELAY_DEFVAL 0x04000400 +#define DDRC_ODTCFG_RD_ODT_DELAY_SHIFT 2 +#define DDRC_ODTCFG_RD_ODT_DELAY_MASK 0x0000007CU -/*Indicates which remote ODTs must be turned on during a read from rank 1. Each rank has a remote ODT (in the SDRAM) which can - e turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB - etc. For each rank, set its bit to 1 to enable its ODT. Present only in configurations that have 2 or more ranks*/ +/* +* Indicates which remote ODTs must be turned on during a read from rank 1. + * Each rank has a remote ODT (in the SDRAM) which can be turned on by set + * ting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 i + * s controlled by bit next to the LSB, etc. For each rank, set its bit to + * 1 to enable its ODT. Present only in configurations that have 2 or more + * ranks +*/ #undef DDRC_ODTMAP_RANK1_RD_ODT_DEFVAL #undef DDRC_ODTMAP_RANK1_RD_ODT_SHIFT #undef DDRC_ODTMAP_RANK1_RD_ODT_MASK -#define DDRC_ODTMAP_RANK1_RD_ODT_DEFVAL 0x00002211 -#define DDRC_ODTMAP_RANK1_RD_ODT_SHIFT 12 -#define DDRC_ODTMAP_RANK1_RD_ODT_MASK 0x00003000U +#define DDRC_ODTMAP_RANK1_RD_ODT_DEFVAL 0x00002211 +#define DDRC_ODTMAP_RANK1_RD_ODT_SHIFT 12 +#define DDRC_ODTMAP_RANK1_RD_ODT_MASK 0x00003000U -/*Indicates which remote ODTs must be turned on during a write to rank 1. Each rank has a remote ODT (in the SDRAM) which can b - turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB, - etc. For each rank, set its bit to 1 to enable its ODT. Present only in configurations that have 2 or more ranks*/ +/* +* Indicates which remote ODTs must be turned on during a write to rank 1. + * Each rank has a remote ODT (in the SDRAM) which can be turned on by sett + * ing the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is + * controlled by bit next to the LSB, etc. For each rank, set its bit to 1 + * to enable its ODT. Present only in configurations that have 2 or more r + * anks +*/ #undef DDRC_ODTMAP_RANK1_WR_ODT_DEFVAL #undef DDRC_ODTMAP_RANK1_WR_ODT_SHIFT #undef DDRC_ODTMAP_RANK1_WR_ODT_MASK -#define DDRC_ODTMAP_RANK1_WR_ODT_DEFVAL 0x00002211 -#define DDRC_ODTMAP_RANK1_WR_ODT_SHIFT 8 -#define DDRC_ODTMAP_RANK1_WR_ODT_MASK 0x00000300U +#define DDRC_ODTMAP_RANK1_WR_ODT_DEFVAL 0x00002211 +#define DDRC_ODTMAP_RANK1_WR_ODT_SHIFT 8 +#define DDRC_ODTMAP_RANK1_WR_ODT_MASK 0x00000300U -/*Indicates which remote ODTs must be turned on during a read from rank 0. Each rank has a remote ODT (in the SDRAM) which can - e turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB - etc. For each rank, set its bit to 1 to enable its ODT.*/ +/* +* Indicates which remote ODTs must be turned on during a read from rank 0. + * Each rank has a remote ODT (in the SDRAM) which can be turned on by set + * ting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 i + * s controlled by bit next to the LSB, etc. For each rank, set its bit to + * 1 to enable its ODT. +*/ #undef DDRC_ODTMAP_RANK0_RD_ODT_DEFVAL #undef DDRC_ODTMAP_RANK0_RD_ODT_SHIFT #undef DDRC_ODTMAP_RANK0_RD_ODT_MASK -#define DDRC_ODTMAP_RANK0_RD_ODT_DEFVAL 0x00002211 -#define DDRC_ODTMAP_RANK0_RD_ODT_SHIFT 4 -#define DDRC_ODTMAP_RANK0_RD_ODT_MASK 0x00000030U +#define DDRC_ODTMAP_RANK0_RD_ODT_DEFVAL 0x00002211 +#define DDRC_ODTMAP_RANK0_RD_ODT_SHIFT 4 +#define DDRC_ODTMAP_RANK0_RD_ODT_MASK 0x00000030U -/*Indicates which remote ODTs must be turned on during a write to rank 0. Each rank has a remote ODT (in the SDRAM) which can b - turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB, - etc. For each rank, set its bit to 1 to enable its ODT.*/ +/* +* Indicates which remote ODTs must be turned on during a write to rank 0. + * Each rank has a remote ODT (in the SDRAM) which can be turned on by sett + * ing the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is + * controlled by bit next to the LSB, etc. For each rank, set its bit to 1 + * to enable its ODT. +*/ #undef DDRC_ODTMAP_RANK0_WR_ODT_DEFVAL #undef DDRC_ODTMAP_RANK0_WR_ODT_SHIFT #undef DDRC_ODTMAP_RANK0_WR_ODT_MASK -#define DDRC_ODTMAP_RANK0_WR_ODT_DEFVAL 0x00002211 -#define DDRC_ODTMAP_RANK0_WR_ODT_SHIFT 0 -#define DDRC_ODTMAP_RANK0_WR_ODT_MASK 0x00000003U +#define DDRC_ODTMAP_RANK0_WR_ODT_DEFVAL 0x00002211 +#define DDRC_ODTMAP_RANK0_WR_ODT_SHIFT 0 +#define DDRC_ODTMAP_RANK0_WR_ODT_MASK 0x00000003U -/*When the preferred transaction store is empty for these many clock cycles, switch to the alternate transaction store if it is - non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write t - ansaction store is the alternative store. When prefer write over read is set this is reversed. 0x0 is a legal value for this - egister. When set to 0x0, the transaction store switching will happen immediately when the switching conditions become true. - OR PERFORMANCE ONLY*/ +/* +* When the preferred transaction store is empty for these many clock cycle + * s, switch to the alternate transaction store if it is non-empty. The rea + * d transaction store (both high and low priority) is the default preferre + * d transaction store and the write transaction store is the alternative s + * tore. When prefer write over read is set this is reversed. 0x0 is a lega + * l value for this register. When set to 0x0, the transaction store switch + * ing will happen immediately when the switching conditions become true. F + * OR PERFORMANCE ONLY +*/ #undef DDRC_SCHED_RDWR_IDLE_GAP_DEFVAL #undef DDRC_SCHED_RDWR_IDLE_GAP_SHIFT #undef DDRC_SCHED_RDWR_IDLE_GAP_MASK -#define DDRC_SCHED_RDWR_IDLE_GAP_DEFVAL 0x00002005 -#define DDRC_SCHED_RDWR_IDLE_GAP_SHIFT 24 -#define DDRC_SCHED_RDWR_IDLE_GAP_MASK 0x7F000000U +#define DDRC_SCHED_RDWR_IDLE_GAP_DEFVAL 0x00002005 +#define DDRC_SCHED_RDWR_IDLE_GAP_SHIFT 24 +#define DDRC_SCHED_RDWR_IDLE_GAP_MASK 0x7F000000U -/*UNUSED*/ +/* +* UNUSED +*/ #undef DDRC_SCHED_GO2CRITICAL_HYSTERESIS_DEFVAL #undef DDRC_SCHED_GO2CRITICAL_HYSTERESIS_SHIFT #undef DDRC_SCHED_GO2CRITICAL_HYSTERESIS_MASK -#define DDRC_SCHED_GO2CRITICAL_HYSTERESIS_DEFVAL 0x00002005 -#define DDRC_SCHED_GO2CRITICAL_HYSTERESIS_SHIFT 16 -#define DDRC_SCHED_GO2CRITICAL_HYSTERESIS_MASK 0x00FF0000U +#define DDRC_SCHED_GO2CRITICAL_HYSTERESIS_DEFVAL 0x00002005 +#define DDRC_SCHED_GO2CRITICAL_HYSTERESIS_SHIFT 16 +#define DDRC_SCHED_GO2CRITICAL_HYSTERESIS_MASK 0x00FF0000U -/*Number of entries in the low priority transaction store is this value + 1. (MEMC_NO_OF_ENTRY - (SCHED.lpr_num_entries + 1)) i - the number of entries available for the high priority transaction store. Setting this to maximum value allocates all entries - to low priority transaction store. Setting this to 0 allocates 1 entry to low priority transaction store and the rest to high - priority transaction store. Note: In ECC configurations, the numbers of write and low priority read credits issued is one les - than in the non-ECC case. One entry each is reserved in the write and low-priority read CAMs for storing the RMW requests ar - sing out of single bit error correction RMW operation.*/ +/* +* Number of entries in the low priority transaction store is this value + + * 1. (MEMC_NO_OF_ENTRY - (SCHED.lpr_num_entries + 1)) is the number of ent + * ries available for the high priority transaction store. Setting this to + * maximum value allocates all entries to low priority transaction store. S + * etting this to 0 allocates 1 entry to low priority transaction store and + * the rest to high priority transaction store. Note: In ECC configuration + * s, the numbers of write and low priority read credits issued is one less + * than in the non-ECC case. One entry each is reserved in the write and l + * ow-priority read CAMs for storing the RMW requests arising out of single + * bit error correction RMW operation. +*/ #undef DDRC_SCHED_LPR_NUM_ENTRIES_DEFVAL #undef DDRC_SCHED_LPR_NUM_ENTRIES_SHIFT #undef DDRC_SCHED_LPR_NUM_ENTRIES_MASK -#define DDRC_SCHED_LPR_NUM_ENTRIES_DEFVAL 0x00002005 -#define DDRC_SCHED_LPR_NUM_ENTRIES_SHIFT 8 -#define DDRC_SCHED_LPR_NUM_ENTRIES_MASK 0x00003F00U +#define DDRC_SCHED_LPR_NUM_ENTRIES_DEFVAL 0x00002005 +#define DDRC_SCHED_LPR_NUM_ENTRIES_SHIFT 8 +#define DDRC_SCHED_LPR_NUM_ENTRIES_MASK 0x00003F00U -/*If true, bank is kept open only while there are page hit transactions available in the CAM to that bank. The last read or wri - e command in the CAM with a bank and page hit will be executed with auto-precharge if SCHED1.pageclose_timer=0. Even if this - egister set to 1 and SCHED1.pageclose_timer is set to 0, explicit precharge (and not auto-precharge) may be issued in some ca - es where there is a mode switch between Write and Read or between LPR and HPR. The Read and Write commands that are executed - s part of the ECC scrub requests are also executed without auto-precharge. If false, the bank remains open until there is a n - ed to close it (to open a different page, or for page timeout or refresh timeout) - also known as open page policy. The open - age policy can be overridden by setting the per-command-autopre bit on the HIF interface (hif_cmd_autopre). The pageclose fea - ure provids a midway between Open and Close page policies. FOR PERFORMANCE ONLY.*/ +/* +* If true, bank is kept open only while there are page hit transactions av + * ailable in the CAM to that bank. The last read or write command in the C + * AM with a bank and page hit will be executed with auto-precharge if SCHE + * D1.pageclose_timer=0. Even if this register set to 1 and SCHED1.pageclos + * e_timer is set to 0, explicit precharge (and not auto-precharge) may be + * issued in some cases where there is a mode switch between Write and Read + * or between LPR and HPR. The Read and Write commands that are executed a + * s part of the ECC scrub requests are also executed without auto-precharg + * e. If false, the bank remains open until there is a need to close it (to + * open a different page, or for page timeout or refresh timeout) - also k + * nown as open page policy. The open page policy can be overridden by sett + * ing the per-command-autopre bit on the HIF interface (hif_cmd_autopre). + * The pageclose feature provids a midway between Open and Close page polic + * ies. FOR PERFORMANCE ONLY. +*/ #undef DDRC_SCHED_PAGECLOSE_DEFVAL #undef DDRC_SCHED_PAGECLOSE_SHIFT #undef DDRC_SCHED_PAGECLOSE_MASK -#define DDRC_SCHED_PAGECLOSE_DEFVAL 0x00002005 -#define DDRC_SCHED_PAGECLOSE_SHIFT 2 -#define DDRC_SCHED_PAGECLOSE_MASK 0x00000004U +#define DDRC_SCHED_PAGECLOSE_DEFVAL 0x00002005 +#define DDRC_SCHED_PAGECLOSE_SHIFT 2 +#define DDRC_SCHED_PAGECLOSE_MASK 0x00000004U -/*If set then the bank selector prefers writes over reads. FOR DEBUG ONLY.*/ +/* +* If set then the bank selector prefers writes over reads. FOR DEBUG ONLY. +*/ #undef DDRC_SCHED_PREFER_WRITE_DEFVAL #undef DDRC_SCHED_PREFER_WRITE_SHIFT #undef DDRC_SCHED_PREFER_WRITE_MASK -#define DDRC_SCHED_PREFER_WRITE_DEFVAL 0x00002005 -#define DDRC_SCHED_PREFER_WRITE_SHIFT 1 -#define DDRC_SCHED_PREFER_WRITE_MASK 0x00000002U +#define DDRC_SCHED_PREFER_WRITE_DEFVAL 0x00002005 +#define DDRC_SCHED_PREFER_WRITE_SHIFT 1 +#define DDRC_SCHED_PREFER_WRITE_MASK 0x00000002U -/*Active low signal. When asserted ('0'), all incoming transactions are forced to low priority. This implies that all High Prio - ity Read (HPR) and Variable Priority Read commands (VPR) will be treated as Low Priority Read (LPR) commands. On the write si - e, all Variable Priority Write (VPW) commands will be treated as Normal Priority Write (NPW) commands. Forcing the incoming t - ansactions to low priority implicitly turns off Bypass path for read commands. FOR PERFORMANCE ONLY.*/ +/* +* Active low signal. When asserted ('0'), all incoming transactions are fo + * rced to low priority. This implies that all High Priority Read (HPR) and + * Variable Priority Read commands (VPR) will be treated as Low Priority R + * ead (LPR) commands. On the write side, all Variable Priority Write (VPW) + * commands will be treated as Normal Priority Write (NPW) commands. Forci + * ng the incoming transactions to low priority implicitly turns off Bypass + * path for read commands. FOR PERFORMANCE ONLY. +*/ #undef DDRC_SCHED_FORCE_LOW_PRI_N_DEFVAL #undef DDRC_SCHED_FORCE_LOW_PRI_N_SHIFT #undef DDRC_SCHED_FORCE_LOW_PRI_N_MASK -#define DDRC_SCHED_FORCE_LOW_PRI_N_DEFVAL 0x00002005 -#define DDRC_SCHED_FORCE_LOW_PRI_N_SHIFT 0 -#define DDRC_SCHED_FORCE_LOW_PRI_N_MASK 0x00000001U +#define DDRC_SCHED_FORCE_LOW_PRI_N_DEFVAL 0x00002005 +#define DDRC_SCHED_FORCE_LOW_PRI_N_SHIFT 0 +#define DDRC_SCHED_FORCE_LOW_PRI_N_MASK 0x00000001U -/*Number of transactions that are serviced once the LPR queue goes critical is the smaller of: - (a) This number - (b) Number o - transactions available. Unit: Transaction. FOR PERFORMANCE ONLY.*/ +/* +* Number of transactions that are serviced once the LPR queue goes critica + * l is the smaller of: - (a) This number - (b) Number of transactions avai + * lable. Unit: Transaction. FOR PERFORMANCE ONLY. +*/ #undef DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_DEFVAL #undef DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_SHIFT #undef DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_MASK -#define DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_DEFVAL 0x0F00007F -#define DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_SHIFT 24 -#define DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_MASK 0xFF000000U +#define DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_DEFVAL 0x0F00007F +#define DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_SHIFT 24 +#define DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_MASK 0xFF000000U -/*Number of clocks that the LPR queue can be starved before it goes critical. The minimum valid functional value for this regis - er is 0x1. Programming it to 0x0 will disable the starvation functionality; during normal operation, this function should not - be disabled as it will cause excessive latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY.*/ +/* +* Number of clocks that the LPR queue can be starved before it goes critic + * al. The minimum valid functional value for this register is 0x1. Program + * ming it to 0x0 will disable the starvation functionality; during normal + * operation, this function should not be disabled as it will cause excessi + * ve latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY. +*/ #undef DDRC_PERFLPR1_LPR_MAX_STARVE_DEFVAL #undef DDRC_PERFLPR1_LPR_MAX_STARVE_SHIFT #undef DDRC_PERFLPR1_LPR_MAX_STARVE_MASK -#define DDRC_PERFLPR1_LPR_MAX_STARVE_DEFVAL 0x0F00007F -#define DDRC_PERFLPR1_LPR_MAX_STARVE_SHIFT 0 -#define DDRC_PERFLPR1_LPR_MAX_STARVE_MASK 0x0000FFFFU +#define DDRC_PERFLPR1_LPR_MAX_STARVE_DEFVAL 0x0F00007F +#define DDRC_PERFLPR1_LPR_MAX_STARVE_SHIFT 0 +#define DDRC_PERFLPR1_LPR_MAX_STARVE_MASK 0x0000FFFFU -/*Number of transactions that are serviced once the WR queue goes critical is the smaller of: - (a) This number - (b) Number of - transactions available. Unit: Transaction. FOR PERFORMANCE ONLY.*/ +/* +* Number of transactions that are serviced once the WR queue goes critical + * is the smaller of: - (a) This number - (b) Number of transactions avail + * able. Unit: Transaction. FOR PERFORMANCE ONLY. +*/ #undef DDRC_PERFWR1_W_XACT_RUN_LENGTH_DEFVAL #undef DDRC_PERFWR1_W_XACT_RUN_LENGTH_SHIFT #undef DDRC_PERFWR1_W_XACT_RUN_LENGTH_MASK -#define DDRC_PERFWR1_W_XACT_RUN_LENGTH_DEFVAL 0x0F00007F -#define DDRC_PERFWR1_W_XACT_RUN_LENGTH_SHIFT 24 -#define DDRC_PERFWR1_W_XACT_RUN_LENGTH_MASK 0xFF000000U +#define DDRC_PERFWR1_W_XACT_RUN_LENGTH_DEFVAL 0x0F00007F +#define DDRC_PERFWR1_W_XACT_RUN_LENGTH_SHIFT 24 +#define DDRC_PERFWR1_W_XACT_RUN_LENGTH_MASK 0xFF000000U -/*Number of clocks that the WR queue can be starved before it goes critical. The minimum valid functional value for this regist - r is 0x1. Programming it to 0x0 will disable the starvation functionality; during normal operation, this function should not - e disabled as it will cause excessive latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY.*/ +/* +* Number of clocks that the WR queue can be starved before it goes critica + * l. The minimum valid functional value for this register is 0x1. Programm + * ing it to 0x0 will disable the starvation functionality; during normal o + * peration, this function should not be disabled as it will cause excessiv + * e latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY. +*/ #undef DDRC_PERFWR1_W_MAX_STARVE_DEFVAL #undef DDRC_PERFWR1_W_MAX_STARVE_SHIFT #undef DDRC_PERFWR1_W_MAX_STARVE_MASK -#define DDRC_PERFWR1_W_MAX_STARVE_DEFVAL 0x0F00007F -#define DDRC_PERFWR1_W_MAX_STARVE_SHIFT 0 -#define DDRC_PERFWR1_W_MAX_STARVE_MASK 0x0000FFFFU +#define DDRC_PERFWR1_W_MAX_STARVE_DEFVAL 0x0F00007F +#define DDRC_PERFWR1_W_MAX_STARVE_SHIFT 0 +#define DDRC_PERFWR1_W_MAX_STARVE_MASK 0x0000FFFFU -/*All even ranks have the same DQ mapping controled by DQMAP0-4 register as rank 0. This register provides DQ swap function for - all odd ranks to support CRC feature. rank based DQ swapping is: swap bit 0 with 1, swap bit 2 with 3, swap bit 4 with 5 and - wap bit 6 with 7. 1: Disable rank based DQ swapping 0: Enable rank based DQ swapping Present only in designs configured to su - port DDR4.*/ +/* +* DQ nibble map for DQ bits [12-15] Present only in designs configured to + * support DDR4. +*/ +#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_12_15_DEFVAL +#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_12_15_SHIFT +#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_12_15_MASK +#define DDRC_DQMAP0_DQ_NIBBLE_MAP_12_15_DEFVAL 0x00000000 +#define DDRC_DQMAP0_DQ_NIBBLE_MAP_12_15_SHIFT 24 +#define DDRC_DQMAP0_DQ_NIBBLE_MAP_12_15_MASK 0xFF000000U + +/* +* DQ nibble map for DQ bits [8-11] Present only in designs configured to s + * upport DDR4. +*/ +#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_8_11_DEFVAL +#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_8_11_SHIFT +#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_8_11_MASK +#define DDRC_DQMAP0_DQ_NIBBLE_MAP_8_11_DEFVAL 0x00000000 +#define DDRC_DQMAP0_DQ_NIBBLE_MAP_8_11_SHIFT 16 +#define DDRC_DQMAP0_DQ_NIBBLE_MAP_8_11_MASK 0x00FF0000U + +/* +* DQ nibble map for DQ bits [4-7] Present only in designs configured to su + * pport DDR4. +*/ +#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_4_7_DEFVAL +#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_4_7_SHIFT +#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_4_7_MASK +#define DDRC_DQMAP0_DQ_NIBBLE_MAP_4_7_DEFVAL 0x00000000 +#define DDRC_DQMAP0_DQ_NIBBLE_MAP_4_7_SHIFT 8 +#define DDRC_DQMAP0_DQ_NIBBLE_MAP_4_7_MASK 0x0000FF00U + +/* +* DQ nibble map for DQ bits [0-3] Present only in designs configured to su + * pport DDR4. +*/ +#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_0_3_DEFVAL +#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_0_3_SHIFT +#undef DDRC_DQMAP0_DQ_NIBBLE_MAP_0_3_MASK +#define DDRC_DQMAP0_DQ_NIBBLE_MAP_0_3_DEFVAL 0x00000000 +#define DDRC_DQMAP0_DQ_NIBBLE_MAP_0_3_SHIFT 0 +#define DDRC_DQMAP0_DQ_NIBBLE_MAP_0_3_MASK 0x000000FFU + +/* +* DQ nibble map for DQ bits [28-31] Present only in designs configured to + * support DDR4. +*/ +#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_28_31_DEFVAL +#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_28_31_SHIFT +#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_28_31_MASK +#define DDRC_DQMAP1_DQ_NIBBLE_MAP_28_31_DEFVAL 0x00000000 +#define DDRC_DQMAP1_DQ_NIBBLE_MAP_28_31_SHIFT 24 +#define DDRC_DQMAP1_DQ_NIBBLE_MAP_28_31_MASK 0xFF000000U + +/* +* DQ nibble map for DQ bits [24-27] Present only in designs configured to + * support DDR4. +*/ +#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_24_27_DEFVAL +#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_24_27_SHIFT +#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_24_27_MASK +#define DDRC_DQMAP1_DQ_NIBBLE_MAP_24_27_DEFVAL 0x00000000 +#define DDRC_DQMAP1_DQ_NIBBLE_MAP_24_27_SHIFT 16 +#define DDRC_DQMAP1_DQ_NIBBLE_MAP_24_27_MASK 0x00FF0000U + +/* +* DQ nibble map for DQ bits [20-23] Present only in designs configured to + * support DDR4. +*/ +#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_20_23_DEFVAL +#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_20_23_SHIFT +#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_20_23_MASK +#define DDRC_DQMAP1_DQ_NIBBLE_MAP_20_23_DEFVAL 0x00000000 +#define DDRC_DQMAP1_DQ_NIBBLE_MAP_20_23_SHIFT 8 +#define DDRC_DQMAP1_DQ_NIBBLE_MAP_20_23_MASK 0x0000FF00U + +/* +* DQ nibble map for DQ bits [16-19] Present only in designs configured to + * support DDR4. +*/ +#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_16_19_DEFVAL +#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_16_19_SHIFT +#undef DDRC_DQMAP1_DQ_NIBBLE_MAP_16_19_MASK +#define DDRC_DQMAP1_DQ_NIBBLE_MAP_16_19_DEFVAL 0x00000000 +#define DDRC_DQMAP1_DQ_NIBBLE_MAP_16_19_SHIFT 0 +#define DDRC_DQMAP1_DQ_NIBBLE_MAP_16_19_MASK 0x000000FFU + +/* +* DQ nibble map for DQ bits [44-47] Present only in designs configured to + * support DDR4. +*/ +#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_44_47_DEFVAL +#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_44_47_SHIFT +#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_44_47_MASK +#define DDRC_DQMAP2_DQ_NIBBLE_MAP_44_47_DEFVAL 0x00000000 +#define DDRC_DQMAP2_DQ_NIBBLE_MAP_44_47_SHIFT 24 +#define DDRC_DQMAP2_DQ_NIBBLE_MAP_44_47_MASK 0xFF000000U + +/* +* DQ nibble map for DQ bits [40-43] Present only in designs configured to + * support DDR4. +*/ +#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_40_43_DEFVAL +#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_40_43_SHIFT +#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_40_43_MASK +#define DDRC_DQMAP2_DQ_NIBBLE_MAP_40_43_DEFVAL 0x00000000 +#define DDRC_DQMAP2_DQ_NIBBLE_MAP_40_43_SHIFT 16 +#define DDRC_DQMAP2_DQ_NIBBLE_MAP_40_43_MASK 0x00FF0000U + +/* +* DQ nibble map for DQ bits [36-39] Present only in designs configured to + * support DDR4. +*/ +#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_36_39_DEFVAL +#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_36_39_SHIFT +#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_36_39_MASK +#define DDRC_DQMAP2_DQ_NIBBLE_MAP_36_39_DEFVAL 0x00000000 +#define DDRC_DQMAP2_DQ_NIBBLE_MAP_36_39_SHIFT 8 +#define DDRC_DQMAP2_DQ_NIBBLE_MAP_36_39_MASK 0x0000FF00U + +/* +* DQ nibble map for DQ bits [32-35] Present only in designs configured to + * support DDR4. +*/ +#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_32_35_DEFVAL +#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_32_35_SHIFT +#undef DDRC_DQMAP2_DQ_NIBBLE_MAP_32_35_MASK +#define DDRC_DQMAP2_DQ_NIBBLE_MAP_32_35_DEFVAL 0x00000000 +#define DDRC_DQMAP2_DQ_NIBBLE_MAP_32_35_SHIFT 0 +#define DDRC_DQMAP2_DQ_NIBBLE_MAP_32_35_MASK 0x000000FFU + +/* +* DQ nibble map for DQ bits [60-63] Present only in designs configured to + * support DDR4. +*/ +#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_60_63_DEFVAL +#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_60_63_SHIFT +#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_60_63_MASK +#define DDRC_DQMAP3_DQ_NIBBLE_MAP_60_63_DEFVAL 0x00000000 +#define DDRC_DQMAP3_DQ_NIBBLE_MAP_60_63_SHIFT 24 +#define DDRC_DQMAP3_DQ_NIBBLE_MAP_60_63_MASK 0xFF000000U + +/* +* DQ nibble map for DQ bits [56-59] Present only in designs configured to + * support DDR4. +*/ +#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_56_59_DEFVAL +#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_56_59_SHIFT +#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_56_59_MASK +#define DDRC_DQMAP3_DQ_NIBBLE_MAP_56_59_DEFVAL 0x00000000 +#define DDRC_DQMAP3_DQ_NIBBLE_MAP_56_59_SHIFT 16 +#define DDRC_DQMAP3_DQ_NIBBLE_MAP_56_59_MASK 0x00FF0000U + +/* +* DQ nibble map for DQ bits [52-55] Present only in designs configured to + * support DDR4. +*/ +#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_52_55_DEFVAL +#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_52_55_SHIFT +#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_52_55_MASK +#define DDRC_DQMAP3_DQ_NIBBLE_MAP_52_55_DEFVAL 0x00000000 +#define DDRC_DQMAP3_DQ_NIBBLE_MAP_52_55_SHIFT 8 +#define DDRC_DQMAP3_DQ_NIBBLE_MAP_52_55_MASK 0x0000FF00U + +/* +* DQ nibble map for DQ bits [48-51] Present only in designs configured to + * support DDR4. +*/ +#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_48_51_DEFVAL +#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_48_51_SHIFT +#undef DDRC_DQMAP3_DQ_NIBBLE_MAP_48_51_MASK +#define DDRC_DQMAP3_DQ_NIBBLE_MAP_48_51_DEFVAL 0x00000000 +#define DDRC_DQMAP3_DQ_NIBBLE_MAP_48_51_SHIFT 0 +#define DDRC_DQMAP3_DQ_NIBBLE_MAP_48_51_MASK 0x000000FFU + +/* +* DQ nibble map for DIMM ECC check bits [4-7] Present only in designs conf + * igured to support DDR4. +*/ +#undef DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_4_7_DEFVAL +#undef DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_4_7_SHIFT +#undef DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_4_7_MASK +#define DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_4_7_DEFVAL 0x00000000 +#define DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_4_7_SHIFT 8 +#define DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_4_7_MASK 0x0000FF00U + +/* +* DQ nibble map for DIMM ECC check bits [0-3] Present only in designs conf + * igured to support DDR4. +*/ +#undef DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_0_3_DEFVAL +#undef DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_0_3_SHIFT +#undef DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_0_3_MASK +#define DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_0_3_DEFVAL 0x00000000 +#define DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_0_3_SHIFT 0 +#define DDRC_DQMAP4_DQ_NIBBLE_MAP_CB_0_3_MASK 0x000000FFU + +/* +* All even ranks have the same DQ mapping controled by DQMAP0-4 register a + * s rank 0. This register provides DQ swap function for all odd ranks to s + * upport CRC feature. rank based DQ swapping is: swap bit 0 with 1, swap b + * it 2 with 3, swap bit 4 with 5 and swap bit 6 with 7. 1: Disable rank ba + * sed DQ swapping 0: Enable rank based DQ swapping Present only in designs + * configured to support DDR4. +*/ #undef DDRC_DQMAP5_DIS_DQ_RANK_SWAP_DEFVAL #undef DDRC_DQMAP5_DIS_DQ_RANK_SWAP_SHIFT #undef DDRC_DQMAP5_DIS_DQ_RANK_SWAP_MASK -#define DDRC_DQMAP5_DIS_DQ_RANK_SWAP_DEFVAL -#define DDRC_DQMAP5_DIS_DQ_RANK_SWAP_SHIFT 0 -#define DDRC_DQMAP5_DIS_DQ_RANK_SWAP_MASK 0x00000001U +#define DDRC_DQMAP5_DIS_DQ_RANK_SWAP_DEFVAL +#define DDRC_DQMAP5_DIS_DQ_RANK_SWAP_SHIFT 0 +#define DDRC_DQMAP5_DIS_DQ_RANK_SWAP_MASK 0x00000001U -/*When this is set to '0', auto-precharge is disabled for the flushed command in a collision case. Collision cases are write fo - lowed by read to same address, read followed by write to same address, or write followed by write to same address with DBG0.d - s_wc bit = 1 (where same address comparisons exclude the two address bits representing critical word). FOR DEBUG ONLY.*/ +/* +* When this is set to '0', auto-precharge is disabled for the flushed comm + * and in a collision case. Collision cases are write followed by read to s + * ame address, read followed by write to same address, or write followed b + * y write to same address with DBG0.dis_wc bit = 1 (where same address com + * parisons exclude the two address bits representing critical word). FOR D + * EBUG ONLY. +*/ #undef DDRC_DBG0_DIS_COLLISION_PAGE_OPT_DEFVAL #undef DDRC_DBG0_DIS_COLLISION_PAGE_OPT_SHIFT #undef DDRC_DBG0_DIS_COLLISION_PAGE_OPT_MASK -#define DDRC_DBG0_DIS_COLLISION_PAGE_OPT_DEFVAL 0x00000000 -#define DDRC_DBG0_DIS_COLLISION_PAGE_OPT_SHIFT 4 -#define DDRC_DBG0_DIS_COLLISION_PAGE_OPT_MASK 0x00000010U +#define DDRC_DBG0_DIS_COLLISION_PAGE_OPT_DEFVAL 0x00000000 +#define DDRC_DBG0_DIS_COLLISION_PAGE_OPT_SHIFT 4 +#define DDRC_DBG0_DIS_COLLISION_PAGE_OPT_MASK 0x00000010U -/*When 1, disable write combine. FOR DEBUG ONLY*/ +/* +* When 1, disable write combine. FOR DEBUG ONLY +*/ #undef DDRC_DBG0_DIS_WC_DEFVAL #undef DDRC_DBG0_DIS_WC_SHIFT #undef DDRC_DBG0_DIS_WC_MASK -#define DDRC_DBG0_DIS_WC_DEFVAL 0x00000000 -#define DDRC_DBG0_DIS_WC_SHIFT 0 -#define DDRC_DBG0_DIS_WC_MASK 0x00000001U +#define DDRC_DBG0_DIS_WC_DEFVAL 0x00000000 +#define DDRC_DBG0_DIS_WC_SHIFT 0 +#define DDRC_DBG0_DIS_WC_MASK 0x00000001U -/*Setting this register bit to 1 allows refresh and ZQCS commands to be triggered from hardware via the IOs ext_*. If set to 1, - the fields DBGCMD.zq_calib_short and DBGCMD.rank*_refresh have no function, and are ignored by the uMCTL2 logic. Setting this - register bit to 0 allows refresh and ZQCS to be triggered from software, via the fields DBGCMD.zq_calib_short and DBGCMD.rank - _refresh. If set to 0, the hardware pins ext_* have no function, and are ignored by the uMCTL2 logic. This register is static - and may only be changed when the DDRC reset signal, core_ddrc_rstn, is asserted (0).*/ +/* +* Setting this register bit to 1 allows refresh and ZQCS commands to be tr + * iggered from hardware via the IOs ext_*. If set to 1, the fields DBGCMD. + * zq_calib_short and DBGCMD.rank*_refresh have no function, and are ignore + * d by the uMCTL2 logic. Setting this register bit to 0 allows refresh and + * ZQCS to be triggered from software, via the fields DBGCMD.zq_calib_shor + * t and DBGCMD.rank*_refresh. If set to 0, the hardware pins ext_* have no + * function, and are ignored by the uMCTL2 logic. This register is static, + * and may only be changed when the DDRC reset signal, core_ddrc_rstn, is + * asserted (0). +*/ #undef DDRC_DBGCMD_HW_REF_ZQ_EN_DEFVAL #undef DDRC_DBGCMD_HW_REF_ZQ_EN_SHIFT #undef DDRC_DBGCMD_HW_REF_ZQ_EN_MASK -#define DDRC_DBGCMD_HW_REF_ZQ_EN_DEFVAL 0x00000000 -#define DDRC_DBGCMD_HW_REF_ZQ_EN_SHIFT 31 -#define DDRC_DBGCMD_HW_REF_ZQ_EN_MASK 0x80000000U +#define DDRC_DBGCMD_HW_REF_ZQ_EN_DEFVAL 0x00000000 +#define DDRC_DBGCMD_HW_REF_ZQ_EN_SHIFT 31 +#define DDRC_DBGCMD_HW_REF_ZQ_EN_MASK 0x80000000U -/*Setting this register bit to 1 indicates to the uMCTL2 to issue a dfi_ctrlupd_req to the PHY. When this request is stored in - he uMCTL2, the bit is automatically cleared. This operation must only be performed when DFIUPD0.dis_auto_ctrlupd=1.*/ +/* +* Setting this register bit to 1 indicates to the uMCTL2 to issue a dfi_ct + * rlupd_req to the PHY. When this request is stored in the uMCTL2, the bit + * is automatically cleared. This operation must only be performed when DF + * IUPD0.dis_auto_ctrlupd=1. +*/ #undef DDRC_DBGCMD_CTRLUPD_DEFVAL #undef DDRC_DBGCMD_CTRLUPD_SHIFT #undef DDRC_DBGCMD_CTRLUPD_MASK -#define DDRC_DBGCMD_CTRLUPD_DEFVAL 0x00000000 -#define DDRC_DBGCMD_CTRLUPD_SHIFT 5 -#define DDRC_DBGCMD_CTRLUPD_MASK 0x00000020U +#define DDRC_DBGCMD_CTRLUPD_DEFVAL 0x00000000 +#define DDRC_DBGCMD_CTRLUPD_SHIFT 5 +#define DDRC_DBGCMD_CTRLUPD_MASK 0x00000020U -/*Setting this register bit to 1 indicates to the uMCTL2 to issue a ZQCS (ZQ calibration short)/MPC(ZQ calibration) command to - he SDRAM. When this request is stored in the uMCTL2, the bit is automatically cleared. This operation can be performed only w - en ZQCTL0.dis_auto_zq=1. It is recommended NOT to set this register bit if in Init operating mode. This register bit is ignor - d when in Self-Refresh(except LPDDR4) and SR-Powerdown(LPDDR4) and Deep power-down operating modes and Maximum Power Saving M - de.*/ +/* +* Setting this register bit to 1 indicates to the uMCTL2 to issue a ZQCS ( + * ZQ calibration short)/MPC(ZQ calibration) command to the SDRAM. When thi + * s request is stored in the uMCTL2, the bit is automatically cleared. Thi + * s operation can be performed only when ZQCTL0.dis_auto_zq=1. It is recom + * mended NOT to set this register bit if in Init operating mode. This regi + * ster bit is ignored when in Self-Refresh(except LPDDR4) and SR-Powerdown + * (LPDDR4) and Deep power-down operating modes and Maximum Power Saving Mo + * de. +*/ #undef DDRC_DBGCMD_ZQ_CALIB_SHORT_DEFVAL #undef DDRC_DBGCMD_ZQ_CALIB_SHORT_SHIFT #undef DDRC_DBGCMD_ZQ_CALIB_SHORT_MASK -#define DDRC_DBGCMD_ZQ_CALIB_SHORT_DEFVAL 0x00000000 -#define DDRC_DBGCMD_ZQ_CALIB_SHORT_SHIFT 4 -#define DDRC_DBGCMD_ZQ_CALIB_SHORT_MASK 0x00000010U +#define DDRC_DBGCMD_ZQ_CALIB_SHORT_DEFVAL 0x00000000 +#define DDRC_DBGCMD_ZQ_CALIB_SHORT_SHIFT 4 +#define DDRC_DBGCMD_ZQ_CALIB_SHORT_MASK 0x00000010U -/*Setting this register bit to 1 indicates to the uMCTL2 to issue a refresh to rank 1. Writing to this bit causes DBGSTAT.rank1 - refresh_busy to be set. When DBGSTAT.rank1_refresh_busy is cleared, the command has been stored in uMCTL2. This operation can - be performed only when RFSHCTL3.dis_auto_refresh=1. It is recommended NOT to set this register bit if in Init or Deep power-d - wn operating modes or Maximum Power Saving Mode.*/ +/* +* Setting this register bit to 1 indicates to the uMCTL2 to issue a refres + * h to rank 1. Writing to this bit causes DBGSTAT.rank1_refresh_busy to be + * set. When DBGSTAT.rank1_refresh_busy is cleared, the command has been s + * tored in uMCTL2. This operation can be performed only when RFSHCTL3.dis_ + * auto_refresh=1. It is recommended NOT to set this register bit if in Ini + * t or Deep power-down operating modes or Maximum Power Saving Mode. +*/ #undef DDRC_DBGCMD_RANK1_REFRESH_DEFVAL #undef DDRC_DBGCMD_RANK1_REFRESH_SHIFT #undef DDRC_DBGCMD_RANK1_REFRESH_MASK -#define DDRC_DBGCMD_RANK1_REFRESH_DEFVAL 0x00000000 -#define DDRC_DBGCMD_RANK1_REFRESH_SHIFT 1 -#define DDRC_DBGCMD_RANK1_REFRESH_MASK 0x00000002U +#define DDRC_DBGCMD_RANK1_REFRESH_DEFVAL 0x00000000 +#define DDRC_DBGCMD_RANK1_REFRESH_SHIFT 1 +#define DDRC_DBGCMD_RANK1_REFRESH_MASK 0x00000002U -/*Setting this register bit to 1 indicates to the uMCTL2 to issue a refresh to rank 0. Writing to this bit causes DBGSTAT.rank0 - refresh_busy to be set. When DBGSTAT.rank0_refresh_busy is cleared, the command has been stored in uMCTL2. This operation can - be performed only when RFSHCTL3.dis_auto_refresh=1. It is recommended NOT to set this register bit if in Init or Deep power-d - wn operating modes or Maximum Power Saving Mode.*/ +/* +* Setting this register bit to 1 indicates to the uMCTL2 to issue a refres + * h to rank 0. Writing to this bit causes DBGSTAT.rank0_refresh_busy to be + * set. When DBGSTAT.rank0_refresh_busy is cleared, the command has been s + * tored in uMCTL2. This operation can be performed only when RFSHCTL3.dis_ + * auto_refresh=1. It is recommended NOT to set this register bit if in Ini + * t or Deep power-down operating modes or Maximum Power Saving Mode. +*/ #undef DDRC_DBGCMD_RANK0_REFRESH_DEFVAL #undef DDRC_DBGCMD_RANK0_REFRESH_SHIFT #undef DDRC_DBGCMD_RANK0_REFRESH_MASK -#define DDRC_DBGCMD_RANK0_REFRESH_DEFVAL 0x00000000 -#define DDRC_DBGCMD_RANK0_REFRESH_SHIFT 0 -#define DDRC_DBGCMD_RANK0_REFRESH_MASK 0x00000001U +#define DDRC_DBGCMD_RANK0_REFRESH_DEFVAL 0x00000000 +#define DDRC_DBGCMD_RANK0_REFRESH_SHIFT 0 +#define DDRC_DBGCMD_RANK0_REFRESH_MASK 0x00000001U -/*Enable quasi-dynamic register programming outside reset. Program register to 0 to enable quasi-dynamic programming. Set back - egister to 1 once programming is done.*/ +/* +* Enable quasi-dynamic register programming outside reset. Program registe + * r to 0 to enable quasi-dynamic programming. Set back register to 1 once + * programming is done. +*/ #undef DDRC_SWCTL_SW_DONE_DEFVAL #undef DDRC_SWCTL_SW_DONE_SHIFT #undef DDRC_SWCTL_SW_DONE_MASK -#define DDRC_SWCTL_SW_DONE_DEFVAL -#define DDRC_SWCTL_SW_DONE_SHIFT 0 -#define DDRC_SWCTL_SW_DONE_MASK 0x00000001U +#define DDRC_SWCTL_SW_DONE_DEFVAL +#define DDRC_SWCTL_SW_DONE_SHIFT 0 +#define DDRC_SWCTL_SW_DONE_MASK 0x00000001U -/*Burst length expansion mode. By default (i.e. bl_exp_mode==0) XPI expands every AXI burst into multiple HIF commands, using t - e memory burst length as a unit. If set to 1, then XPI will use half of the memory burst length as a unit. This applies to bo - h reads and writes. When MSTR.data_bus_width==00, setting bl_exp_mode to 1 has no effect. This can be used in cases where Par - ial Writes is enabled (UMCTL2_PARTIAL_WR=1) and DBG0.dis_wc=1, in order to avoid or minimize t_ccd_l penalty in DDR4 and t_cc - _mw penalty in LPDDR4. Note that if DBICTL.reg_ddrc_dm_en=0, functionality is not supported in the following cases: - UMCTL2_ - ARTIAL_WR=0 - UMCTL2_PARTIAL_WR=1, MSTR.reg_ddrc_data_bus_width=01, MEMC_BURST_LENGTH=8 and MSTR.reg_ddrc_burst_rdwr=1000 (LP - DR4 only) - UMCTL2_PARTIAL_WR=1, MSTR.reg_ddrc_data_bus_width=01, MEMC_BURST_LENGTH=4 and MSTR.reg_ddrc_burst_rdwr=0100 (DDR4 - only), with either MSTR.reg_ddrc_burstchop=0 or CRCPARCTL1.reg_ddrc_crc_enable=1 Functionality is also not supported if Share - -AC is enabled*/ +/* +* Burst length expansion mode. By default (i.e. bl_exp_mode==0) XPI expand + * s every AXI burst into multiple HIF commands, using the memory burst len + * gth as a unit. If set to 1, then XPI will use half of the memory burst l + * ength as a unit. This applies to both reads and writes. When MSTR.data_b + * us_width==00, setting bl_exp_mode to 1 has no effect. This can be used i + * n cases where Partial Writes is enabled (UMCTL2_PARTIAL_WR=1) and DBG0.d + * is_wc=1, in order to avoid or minimize t_ccd_l penalty in DDR4 and t_ccd + * _mw penalty in LPDDR4. Note that if DBICTL.reg_ddrc_dm_en=0, functionali + * ty is not supported in the following cases: - UMCTL2_PARTIAL_WR=0 - UMCT + * L2_PARTIAL_WR=1, MSTR.reg_ddrc_data_bus_width=01, MEMC_BURST_LENGTH=8 an + * d MSTR.reg_ddrc_burst_rdwr=1000 (LPDDR4 only) - UMCTL2_PARTIAL_WR=1, MST + * R.reg_ddrc_data_bus_width=01, MEMC_BURST_LENGTH=4 and MSTR.reg_ddrc_burs + * t_rdwr=0100 (DDR4 only), with either MSTR.reg_ddrc_burstchop=0 or CRCPAR + * CTL1.reg_ddrc_crc_enable=1 Functionality is also not supported if Shared + * -AC is enabled +*/ #undef DDRC_PCCFG_BL_EXP_MODE_DEFVAL #undef DDRC_PCCFG_BL_EXP_MODE_SHIFT #undef DDRC_PCCFG_BL_EXP_MODE_MASK -#define DDRC_PCCFG_BL_EXP_MODE_DEFVAL 0x00000000 -#define DDRC_PCCFG_BL_EXP_MODE_SHIFT 8 -#define DDRC_PCCFG_BL_EXP_MODE_MASK 0x00000100U +#define DDRC_PCCFG_BL_EXP_MODE_DEFVAL 0x00000000 +#define DDRC_PCCFG_BL_EXP_MODE_SHIFT 8 +#define DDRC_PCCFG_BL_EXP_MODE_MASK 0x00000100U -/*Page match four limit. If set to 1, limits the number of consecutive same page DDRC transactions that can be granted by the P - rt Arbiter to four when Page Match feature is enabled. If set to 0, there is no limit imposed on number of consecutive same p - ge DDRC transactions.*/ +/* +* Page match four limit. If set to 1, limits the number of consecutive sam + * e page DDRC transactions that can be granted by the Port Arbiter to four + * when Page Match feature is enabled. If set to 0, there is no limit impo + * sed on number of consecutive same page DDRC transactions. +*/ #undef DDRC_PCCFG_PAGEMATCH_LIMIT_DEFVAL #undef DDRC_PCCFG_PAGEMATCH_LIMIT_SHIFT #undef DDRC_PCCFG_PAGEMATCH_LIMIT_MASK -#define DDRC_PCCFG_PAGEMATCH_LIMIT_DEFVAL 0x00000000 -#define DDRC_PCCFG_PAGEMATCH_LIMIT_SHIFT 4 -#define DDRC_PCCFG_PAGEMATCH_LIMIT_MASK 0x00000010U +#define DDRC_PCCFG_PAGEMATCH_LIMIT_DEFVAL 0x00000000 +#define DDRC_PCCFG_PAGEMATCH_LIMIT_SHIFT 4 +#define DDRC_PCCFG_PAGEMATCH_LIMIT_MASK 0x00000010U -/*If set to 1 (enabled), sets co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals going to DDRC based - n urgent input (awurgent, arurgent) coming from AXI master. If set to 0 (disabled), co_gs_go2critical_wr and co_gs_go2critica - _lpr/co_gs_go2critical_hpr signals at DDRC are driven to 1b'0.*/ +/* +* If set to 1 (enabled), sets co_gs_go2critical_wr and co_gs_go2critical_l + * pr/co_gs_go2critical_hpr signals going to DDRC based on urgent input (aw + * urgent, arurgent) coming from AXI master. If set to 0 (disabled), co_gs_ + * go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals a + * t DDRC are driven to 1b'0. +*/ #undef DDRC_PCCFG_GO2CRITICAL_EN_DEFVAL #undef DDRC_PCCFG_GO2CRITICAL_EN_SHIFT #undef DDRC_PCCFG_GO2CRITICAL_EN_MASK -#define DDRC_PCCFG_GO2CRITICAL_EN_DEFVAL 0x00000000 -#define DDRC_PCCFG_GO2CRITICAL_EN_SHIFT 0 -#define DDRC_PCCFG_GO2CRITICAL_EN_MASK 0x00000001U +#define DDRC_PCCFG_GO2CRITICAL_EN_DEFVAL 0x00000000 +#define DDRC_PCCFG_GO2CRITICAL_EN_SHIFT 0 +#define DDRC_PCCFG_GO2CRITICAL_EN_MASK 0x00000001U -/*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register.*/ +/* +* If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. +*/ #undef DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_DEFVAL #undef DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_SHIFT #undef DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_MASK -#define DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_DEFVAL 0x00000000 -#define DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_SHIFT 14 -#define DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_MASK 0x00004000U +#define DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_SHIFT 14 +#define DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_MASK 0x00004000U -/*If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG. - o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add - ess handshaking (it is not associated with any particular command).*/ +/* +* If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + * bled and arurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + * urgent signal can be asserted anytime and as long as required which is i + * ndependent of address handshaking (it is not associated with any particu + * lar command). +*/ #undef DDRC_PCFGR_0_RD_PORT_URGENT_EN_DEFVAL #undef DDRC_PCFGR_0_RD_PORT_URGENT_EN_SHIFT #undef DDRC_PCFGR_0_RD_PORT_URGENT_EN_MASK -#define DDRC_PCFGR_0_RD_PORT_URGENT_EN_DEFVAL 0x00000000 -#define DDRC_PCFGR_0_RD_PORT_URGENT_EN_SHIFT 13 -#define DDRC_PCFGR_0_RD_PORT_URGENT_EN_MASK 0x00002000U +#define DDRC_PCFGR_0_RD_PORT_URGENT_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_0_RD_PORT_URGENT_EN_SHIFT 13 +#define DDRC_PCFGR_0_RD_PORT_URGENT_EN_MASK 0x00002000U -/*If set to 1, enables aging function for the read channel of the port.*/ +/* +* If set to 1, enables aging function for the read channel of the port. +*/ #undef DDRC_PCFGR_0_RD_PORT_AGING_EN_DEFVAL #undef DDRC_PCFGR_0_RD_PORT_AGING_EN_SHIFT #undef DDRC_PCFGR_0_RD_PORT_AGING_EN_MASK -#define DDRC_PCFGR_0_RD_PORT_AGING_EN_DEFVAL 0x00000000 -#define DDRC_PCFGR_0_RD_PORT_AGING_EN_SHIFT 12 -#define DDRC_PCFGR_0_RD_PORT_AGING_EN_MASK 0x00001000U +#define DDRC_PCFGR_0_RD_PORT_AGING_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_0_RD_PORT_AGING_EN_SHIFT 12 +#define DDRC_PCFGR_0_RD_PORT_AGING_EN_MASK 0x00001000U -/*Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g - ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority - will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre - ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the - aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st - ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w - ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D - RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: - he two LSBs of this register field are tied internally to 2'b00.*/ +/* +* Determines the initial load value of read aging counters. These counters + * will be parallel loaded after reset, or after each grant to the corresp + * onding port. The aging counters down-count every clock cycle where the p + * ort is requesting but not granted. The higher significant 5-bits of the + * read aging counter sets the priority of the read channel of a given port + * . Port's priority will increase as the higher significant 5-bits of the + * counter starts to decrease. When the aging counter becomes 0, the corres + * ponding port channel will have the highest priority level (timeout condi + * tion - Priority0). For multi-port configurations, the aging counters can + * not be used to set port priorities when external dynamic priority inputs + * (arqos) are enabled (timeout is still applicable). For single port conf + * igurations, the aging counters are only used when they timeout (become 0 + * ) to force read-write direction switching. In this case, external dynami + * c priority input, arqos (for reads only) can still be used to set the DD + * RC read priority (2 priority levels: low priority read - LPR, high prior + * ity read - HPR) on a command by command basis. Note: The two LSBs of thi + * s register field are tied internally to 2'b00. +*/ #undef DDRC_PCFGR_0_RD_PORT_PRIORITY_DEFVAL #undef DDRC_PCFGR_0_RD_PORT_PRIORITY_SHIFT #undef DDRC_PCFGR_0_RD_PORT_PRIORITY_MASK -#define DDRC_PCFGR_0_RD_PORT_PRIORITY_DEFVAL 0x00000000 -#define DDRC_PCFGR_0_RD_PORT_PRIORITY_SHIFT 0 -#define DDRC_PCFGR_0_RD_PORT_PRIORITY_MASK 0x000003FFU +#define DDRC_PCFGR_0_RD_PORT_PRIORITY_DEFVAL 0x00000000 +#define DDRC_PCFGR_0_RD_PORT_PRIORITY_SHIFT 0 +#define DDRC_PCFGR_0_RD_PORT_PRIORITY_MASK 0x000003FFU -/*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register.*/ +/* +* If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. +*/ #undef DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_DEFVAL #undef DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_SHIFT #undef DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_MASK -#define DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_DEFVAL 0x00004000 -#define DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_SHIFT 14 -#define DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_MASK 0x00004000U +#define DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_SHIFT 14 +#define DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_MASK 0x00004000U -/*If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register - Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is - not associated with any particular command).*/ +/* +* If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + * bled and awurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + * serted anytime and as long as required which is independent of address h + * andshaking (it is not associated with any particular command). +*/ #undef DDRC_PCFGW_0_WR_PORT_URGENT_EN_DEFVAL #undef DDRC_PCFGW_0_WR_PORT_URGENT_EN_SHIFT #undef DDRC_PCFGW_0_WR_PORT_URGENT_EN_MASK -#define DDRC_PCFGW_0_WR_PORT_URGENT_EN_DEFVAL 0x00004000 -#define DDRC_PCFGW_0_WR_PORT_URGENT_EN_SHIFT 13 -#define DDRC_PCFGW_0_WR_PORT_URGENT_EN_MASK 0x00002000U +#define DDRC_PCFGW_0_WR_PORT_URGENT_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_0_WR_PORT_URGENT_EN_SHIFT 13 +#define DDRC_PCFGW_0_WR_PORT_URGENT_EN_MASK 0x00002000U -/*If set to 1, enables aging function for the write channel of the port.*/ +/* +* If set to 1, enables aging function for the write channel of the port. +*/ #undef DDRC_PCFGW_0_WR_PORT_AGING_EN_DEFVAL #undef DDRC_PCFGW_0_WR_PORT_AGING_EN_SHIFT #undef DDRC_PCFGW_0_WR_PORT_AGING_EN_MASK -#define DDRC_PCFGW_0_WR_PORT_AGING_EN_DEFVAL 0x00004000 -#define DDRC_PCFGW_0_WR_PORT_AGING_EN_SHIFT 12 -#define DDRC_PCFGW_0_WR_PORT_AGING_EN_MASK 0x00001000U +#define DDRC_PCFGW_0_WR_PORT_AGING_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_0_WR_PORT_AGING_EN_SHIFT 12 +#define DDRC_PCFGW_0_WR_PORT_AGING_EN_MASK 0x00001000U -/*Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each - rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port - s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0 - the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno - be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For - ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch - ng. Note: The two LSBs of this register field are tied internally to 2'b00.*/ +/* +* Determines the initial load value of write aging counters. These counter + * s will be parallel loaded after reset, or after each grant to the corres + * ponding port. The aging counters down-count every clock cycle where the + * port is requesting but not granted. The higher significant 5-bits of the + * write aging counter sets the initial priority of the write channel of a + * given port. Port's priority will increase as the higher significant 5-b + * its of the counter starts to decrease. When the aging counter becomes 0, + * the corresponding port channel will have the highest priority level. Fo + * r multi-port configurations, the aging counters cannot be used to set po + * rt priorities when external dynamic priority inputs (awqos) are enabled + * (timeout is still applicable). For single port configurations, the aging + * counters are only used when they timeout (become 0) to force read-write + * direction switching. Note: The two LSBs of this register field are tied + * internally to 2'b00. +*/ #undef DDRC_PCFGW_0_WR_PORT_PRIORITY_DEFVAL #undef DDRC_PCFGW_0_WR_PORT_PRIORITY_SHIFT #undef DDRC_PCFGW_0_WR_PORT_PRIORITY_MASK -#define DDRC_PCFGW_0_WR_PORT_PRIORITY_DEFVAL 0x00004000 -#define DDRC_PCFGW_0_WR_PORT_PRIORITY_SHIFT 0 -#define DDRC_PCFGW_0_WR_PORT_PRIORITY_MASK 0x000003FFU +#define DDRC_PCFGW_0_WR_PORT_PRIORITY_DEFVAL 0x00004000 +#define DDRC_PCFGW_0_WR_PORT_PRIORITY_SHIFT 0 +#define DDRC_PCFGW_0_WR_PORT_PRIORITY_MASK 0x000003FFU -/*Enables port n.*/ +/* +* Enables port n. +*/ #undef DDRC_PCTRL_0_PORT_EN_DEFVAL #undef DDRC_PCTRL_0_PORT_EN_SHIFT #undef DDRC_PCTRL_0_PORT_EN_MASK -#define DDRC_PCTRL_0_PORT_EN_DEFVAL -#define DDRC_PCTRL_0_PORT_EN_SHIFT 0 -#define DDRC_PCTRL_0_PORT_EN_MASK 0x00000001U +#define DDRC_PCTRL_0_PORT_EN_DEFVAL +#define DDRC_PCTRL_0_PORT_EN_SHIFT 0 +#define DDRC_PCTRL_0_PORT_EN_MASK 0x00000001U -/*This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf - gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is - disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/ +/* +* This bitfield indicates the traffic class of region 1. Valid values are: + * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + * maps to the blue address queue. In this case, valid values are 0: LPR a + * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. +*/ #undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_DEFVAL #undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_SHIFT #undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_MASK -#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_DEFVAL 0x00000000 -#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_SHIFT 20 -#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_MASK 0x00300000U +#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_DEFVAL 0x00000000 +#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_SHIFT 20 +#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_MASK 0x00300000U -/*This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi - urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i - disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/ +/* +* This bitfield indicates the traffic class of region 0. Valid values are: + * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + * maps to the blue address queue. In this case, valid values are: 0: LPR + * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. +*/ #undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_DEFVAL #undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_SHIFT #undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_MASK -#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_DEFVAL 0x00000000 -#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_SHIFT 16 -#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_MASK 0x00030000U +#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_DEFVAL 0x00000000 +#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_SHIFT 16 +#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_MASK 0x00030000U -/*Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d - al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio - ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc - values.*/ +/* +* Separation level1 indicating the end of region0 mapping; start of region + * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + * lues are used directly as port priorities, where the higher the value co + * rresponds to higher port priority. All of the map_level* registers must + * be set to distinct values. +*/ #undef DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_DEFVAL #undef DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_SHIFT #undef DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_MASK -#define DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_DEFVAL 0x00000000 -#define DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_SHIFT 0 -#define DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_MASK 0x0000000FU +#define DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_DEFVAL 0x00000000 +#define DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_SHIFT 0 +#define DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_MASK 0x0000000FU -/*Specifies the timeout value for transactions mapped to the red address queue.*/ +/* +* Specifies the timeout value for transactions mapped to the red address q + * ueue. +*/ #undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_DEFVAL #undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_SHIFT #undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_MASK -#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_DEFVAL 0x00000000 -#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_SHIFT 16 -#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_MASK 0x07FF0000U +#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_DEFVAL 0x00000000 +#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_SHIFT 16 +#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_MASK 0x07FF0000U -/*Specifies the timeout value for transactions mapped to the blue address queue.*/ +/* +* Specifies the timeout value for transactions mapped to the blue address + * queue. +*/ #undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_DEFVAL #undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_SHIFT #undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_MASK -#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_DEFVAL 0x00000000 -#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_SHIFT 0 -#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_MASK 0x000007FFU +#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_DEFVAL 0x00000000 +#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_SHIFT 0 +#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_MASK 0x000007FFU -/*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register.*/ +/* +* If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. +*/ #undef DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_DEFVAL #undef DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_SHIFT #undef DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_MASK -#define DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_DEFVAL 0x00000000 -#define DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_SHIFT 14 -#define DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_MASK 0x00004000U +#define DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_SHIFT 14 +#define DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_MASK 0x00004000U -/*If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG. - o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add - ess handshaking (it is not associated with any particular command).*/ +/* +* If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + * bled and arurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + * urgent signal can be asserted anytime and as long as required which is i + * ndependent of address handshaking (it is not associated with any particu + * lar command). +*/ #undef DDRC_PCFGR_1_RD_PORT_URGENT_EN_DEFVAL #undef DDRC_PCFGR_1_RD_PORT_URGENT_EN_SHIFT #undef DDRC_PCFGR_1_RD_PORT_URGENT_EN_MASK -#define DDRC_PCFGR_1_RD_PORT_URGENT_EN_DEFVAL 0x00000000 -#define DDRC_PCFGR_1_RD_PORT_URGENT_EN_SHIFT 13 -#define DDRC_PCFGR_1_RD_PORT_URGENT_EN_MASK 0x00002000U +#define DDRC_PCFGR_1_RD_PORT_URGENT_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_1_RD_PORT_URGENT_EN_SHIFT 13 +#define DDRC_PCFGR_1_RD_PORT_URGENT_EN_MASK 0x00002000U -/*If set to 1, enables aging function for the read channel of the port.*/ +/* +* If set to 1, enables aging function for the read channel of the port. +*/ #undef DDRC_PCFGR_1_RD_PORT_AGING_EN_DEFVAL #undef DDRC_PCFGR_1_RD_PORT_AGING_EN_SHIFT #undef DDRC_PCFGR_1_RD_PORT_AGING_EN_MASK -#define DDRC_PCFGR_1_RD_PORT_AGING_EN_DEFVAL 0x00000000 -#define DDRC_PCFGR_1_RD_PORT_AGING_EN_SHIFT 12 -#define DDRC_PCFGR_1_RD_PORT_AGING_EN_MASK 0x00001000U +#define DDRC_PCFGR_1_RD_PORT_AGING_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_1_RD_PORT_AGING_EN_SHIFT 12 +#define DDRC_PCFGR_1_RD_PORT_AGING_EN_MASK 0x00001000U -/*Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g - ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority - will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre - ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the - aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st - ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w - ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D - RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: - he two LSBs of this register field are tied internally to 2'b00.*/ +/* +* Determines the initial load value of read aging counters. These counters + * will be parallel loaded after reset, or after each grant to the corresp + * onding port. The aging counters down-count every clock cycle where the p + * ort is requesting but not granted. The higher significant 5-bits of the + * read aging counter sets the priority of the read channel of a given port + * . Port's priority will increase as the higher significant 5-bits of the + * counter starts to decrease. When the aging counter becomes 0, the corres + * ponding port channel will have the highest priority level (timeout condi + * tion - Priority0). For multi-port configurations, the aging counters can + * not be used to set port priorities when external dynamic priority inputs + * (arqos) are enabled (timeout is still applicable). For single port conf + * igurations, the aging counters are only used when they timeout (become 0 + * ) to force read-write direction switching. In this case, external dynami + * c priority input, arqos (for reads only) can still be used to set the DD + * RC read priority (2 priority levels: low priority read - LPR, high prior + * ity read - HPR) on a command by command basis. Note: The two LSBs of thi + * s register field are tied internally to 2'b00. +*/ #undef DDRC_PCFGR_1_RD_PORT_PRIORITY_DEFVAL #undef DDRC_PCFGR_1_RD_PORT_PRIORITY_SHIFT #undef DDRC_PCFGR_1_RD_PORT_PRIORITY_MASK -#define DDRC_PCFGR_1_RD_PORT_PRIORITY_DEFVAL 0x00000000 -#define DDRC_PCFGR_1_RD_PORT_PRIORITY_SHIFT 0 -#define DDRC_PCFGR_1_RD_PORT_PRIORITY_MASK 0x000003FFU +#define DDRC_PCFGR_1_RD_PORT_PRIORITY_DEFVAL 0x00000000 +#define DDRC_PCFGR_1_RD_PORT_PRIORITY_SHIFT 0 +#define DDRC_PCFGR_1_RD_PORT_PRIORITY_MASK 0x000003FFU -/*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register.*/ +/* +* If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. +*/ #undef DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_DEFVAL #undef DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_SHIFT #undef DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_MASK -#define DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_DEFVAL 0x00004000 -#define DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_SHIFT 14 -#define DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_MASK 0x00004000U +#define DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_SHIFT 14 +#define DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_MASK 0x00004000U -/*If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register - Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is - not associated with any particular command).*/ +/* +* If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + * bled and awurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + * serted anytime and as long as required which is independent of address h + * andshaking (it is not associated with any particular command). +*/ #undef DDRC_PCFGW_1_WR_PORT_URGENT_EN_DEFVAL #undef DDRC_PCFGW_1_WR_PORT_URGENT_EN_SHIFT #undef DDRC_PCFGW_1_WR_PORT_URGENT_EN_MASK -#define DDRC_PCFGW_1_WR_PORT_URGENT_EN_DEFVAL 0x00004000 -#define DDRC_PCFGW_1_WR_PORT_URGENT_EN_SHIFT 13 -#define DDRC_PCFGW_1_WR_PORT_URGENT_EN_MASK 0x00002000U +#define DDRC_PCFGW_1_WR_PORT_URGENT_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_1_WR_PORT_URGENT_EN_SHIFT 13 +#define DDRC_PCFGW_1_WR_PORT_URGENT_EN_MASK 0x00002000U -/*If set to 1, enables aging function for the write channel of the port.*/ +/* +* If set to 1, enables aging function for the write channel of the port. +*/ #undef DDRC_PCFGW_1_WR_PORT_AGING_EN_DEFVAL #undef DDRC_PCFGW_1_WR_PORT_AGING_EN_SHIFT #undef DDRC_PCFGW_1_WR_PORT_AGING_EN_MASK -#define DDRC_PCFGW_1_WR_PORT_AGING_EN_DEFVAL 0x00004000 -#define DDRC_PCFGW_1_WR_PORT_AGING_EN_SHIFT 12 -#define DDRC_PCFGW_1_WR_PORT_AGING_EN_MASK 0x00001000U +#define DDRC_PCFGW_1_WR_PORT_AGING_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_1_WR_PORT_AGING_EN_SHIFT 12 +#define DDRC_PCFGW_1_WR_PORT_AGING_EN_MASK 0x00001000U -/*Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each - rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port - s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0 - the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno - be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For - ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch - ng. Note: The two LSBs of this register field are tied internally to 2'b00.*/ +/* +* Determines the initial load value of write aging counters. These counter + * s will be parallel loaded after reset, or after each grant to the corres + * ponding port. The aging counters down-count every clock cycle where the + * port is requesting but not granted. The higher significant 5-bits of the + * write aging counter sets the initial priority of the write channel of a + * given port. Port's priority will increase as the higher significant 5-b + * its of the counter starts to decrease. When the aging counter becomes 0, + * the corresponding port channel will have the highest priority level. Fo + * r multi-port configurations, the aging counters cannot be used to set po + * rt priorities when external dynamic priority inputs (awqos) are enabled + * (timeout is still applicable). For single port configurations, the aging + * counters are only used when they timeout (become 0) to force read-write + * direction switching. Note: The two LSBs of this register field are tied + * internally to 2'b00. +*/ #undef DDRC_PCFGW_1_WR_PORT_PRIORITY_DEFVAL #undef DDRC_PCFGW_1_WR_PORT_PRIORITY_SHIFT #undef DDRC_PCFGW_1_WR_PORT_PRIORITY_MASK -#define DDRC_PCFGW_1_WR_PORT_PRIORITY_DEFVAL 0x00004000 -#define DDRC_PCFGW_1_WR_PORT_PRIORITY_SHIFT 0 -#define DDRC_PCFGW_1_WR_PORT_PRIORITY_MASK 0x000003FFU +#define DDRC_PCFGW_1_WR_PORT_PRIORITY_DEFVAL 0x00004000 +#define DDRC_PCFGW_1_WR_PORT_PRIORITY_SHIFT 0 +#define DDRC_PCFGW_1_WR_PORT_PRIORITY_MASK 0x000003FFU -/*Enables port n.*/ +/* +* Enables port n. +*/ #undef DDRC_PCTRL_1_PORT_EN_DEFVAL #undef DDRC_PCTRL_1_PORT_EN_SHIFT #undef DDRC_PCTRL_1_PORT_EN_MASK -#define DDRC_PCTRL_1_PORT_EN_DEFVAL -#define DDRC_PCTRL_1_PORT_EN_SHIFT 0 -#define DDRC_PCTRL_1_PORT_EN_MASK 0x00000001U +#define DDRC_PCTRL_1_PORT_EN_DEFVAL +#define DDRC_PCTRL_1_PORT_EN_SHIFT 0 +#define DDRC_PCTRL_1_PORT_EN_MASK 0x00000001U -/*This bitfield indicates the traffic class of region2. For dual address queue configurations, region2 maps to the red address - ueue. Valid values are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and traffic class of region2 - s set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/ +/* +* This bitfield indicates the traffic class of region2. For dual address q + * ueue configurations, region2 maps to the red address queue. Valid values + * are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN + * = 0) and traffic class of region2 is set to 1 (VPR), VPR traffic is ali + * ased to LPR traffic. +*/ #undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_DEFVAL #undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_SHIFT #undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_MASK -#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_DEFVAL 0x02000E00 -#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_SHIFT 24 -#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_MASK 0x03000000U +#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_DEFVAL 0x02000E00 +#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_SHIFT 24 +#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_MASK 0x03000000U -/*This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf - gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is - disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/ +/* +* This bitfield indicates the traffic class of region 1. Valid values are: + * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + * maps to the blue address queue. In this case, valid values are 0: LPR a + * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. +*/ #undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_DEFVAL #undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_SHIFT #undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_MASK -#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_DEFVAL 0x02000E00 -#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_SHIFT 20 -#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_MASK 0x00300000U +#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_DEFVAL 0x02000E00 +#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_SHIFT 20 +#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_MASK 0x00300000U -/*This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi - urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i - disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/ +/* +* This bitfield indicates the traffic class of region 0. Valid values are: + * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + * maps to the blue address queue. In this case, valid values are: 0: LPR + * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. +*/ #undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_DEFVAL #undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_SHIFT #undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_MASK -#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_DEFVAL 0x02000E00 -#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_SHIFT 16 -#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_MASK 0x00030000U +#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_DEFVAL 0x02000E00 +#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_SHIFT 16 +#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_MASK 0x00030000U -/*Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (le - el1 + 1) to 14 which corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note that for PA, arqos values are used - directly as port priorities, where the higher the value corresponds to higher port priority. All of the map_level* registers - ust be set to distinct values.*/ +/* +* Separation level2 indicating the end of region1 mapping; start of region + * 1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 whi + * ch corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note + * that for PA, arqos values are used directly as port priorities, where t + * he higher the value corresponds to higher port priority. All of the map_ + * level* registers must be set to distinct values. +*/ #undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_DEFVAL #undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_SHIFT #undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_MASK -#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_DEFVAL 0x02000E00 -#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_SHIFT 8 -#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_MASK 0x00000F00U +#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_DEFVAL 0x02000E00 +#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_SHIFT 8 +#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_MASK 0x00000F00U -/*Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d - al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio - ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc - values.*/ +/* +* Separation level1 indicating the end of region0 mapping; start of region + * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + * lues are used directly as port priorities, where the higher the value co + * rresponds to higher port priority. All of the map_level* registers must + * be set to distinct values. +*/ #undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_DEFVAL #undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_SHIFT #undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_MASK -#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_DEFVAL 0x02000E00 -#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_SHIFT 0 -#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_MASK 0x0000000FU +#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_DEFVAL 0x02000E00 +#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_SHIFT 0 +#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_MASK 0x0000000FU -/*Specifies the timeout value for transactions mapped to the red address queue.*/ +/* +* Specifies the timeout value for transactions mapped to the red address q + * ueue. +*/ #undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_DEFVAL #undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_SHIFT #undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_MASK -#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_DEFVAL 0x00000000 -#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_SHIFT 16 -#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_MASK 0x07FF0000U +#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_DEFVAL 0x00000000 +#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_SHIFT 16 +#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_MASK 0x07FF0000U -/*Specifies the timeout value for transactions mapped to the blue address queue.*/ +/* +* Specifies the timeout value for transactions mapped to the blue address + * queue. +*/ #undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_DEFVAL #undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_SHIFT #undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_MASK -#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_DEFVAL 0x00000000 -#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_SHIFT 0 -#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_MASK 0x000007FFU +#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_DEFVAL 0x00000000 +#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_SHIFT 0 +#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_MASK 0x000007FFU -/*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register.*/ +/* +* If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. +*/ #undef DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_DEFVAL #undef DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_SHIFT #undef DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_MASK -#define DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_DEFVAL 0x00000000 -#define DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_SHIFT 14 -#define DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_MASK 0x00004000U +#define DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_SHIFT 14 +#define DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_MASK 0x00004000U -/*If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG. - o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add - ess handshaking (it is not associated with any particular command).*/ +/* +* If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + * bled and arurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + * urgent signal can be asserted anytime and as long as required which is i + * ndependent of address handshaking (it is not associated with any particu + * lar command). +*/ #undef DDRC_PCFGR_2_RD_PORT_URGENT_EN_DEFVAL #undef DDRC_PCFGR_2_RD_PORT_URGENT_EN_SHIFT #undef DDRC_PCFGR_2_RD_PORT_URGENT_EN_MASK -#define DDRC_PCFGR_2_RD_PORT_URGENT_EN_DEFVAL 0x00000000 -#define DDRC_PCFGR_2_RD_PORT_URGENT_EN_SHIFT 13 -#define DDRC_PCFGR_2_RD_PORT_URGENT_EN_MASK 0x00002000U +#define DDRC_PCFGR_2_RD_PORT_URGENT_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_2_RD_PORT_URGENT_EN_SHIFT 13 +#define DDRC_PCFGR_2_RD_PORT_URGENT_EN_MASK 0x00002000U -/*If set to 1, enables aging function for the read channel of the port.*/ +/* +* If set to 1, enables aging function for the read channel of the port. +*/ #undef DDRC_PCFGR_2_RD_PORT_AGING_EN_DEFVAL #undef DDRC_PCFGR_2_RD_PORT_AGING_EN_SHIFT #undef DDRC_PCFGR_2_RD_PORT_AGING_EN_MASK -#define DDRC_PCFGR_2_RD_PORT_AGING_EN_DEFVAL 0x00000000 -#define DDRC_PCFGR_2_RD_PORT_AGING_EN_SHIFT 12 -#define DDRC_PCFGR_2_RD_PORT_AGING_EN_MASK 0x00001000U +#define DDRC_PCFGR_2_RD_PORT_AGING_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_2_RD_PORT_AGING_EN_SHIFT 12 +#define DDRC_PCFGR_2_RD_PORT_AGING_EN_MASK 0x00001000U -/*Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g - ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority - will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre - ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the - aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st - ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w - ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D - RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: - he two LSBs of this register field are tied internally to 2'b00.*/ +/* +* Determines the initial load value of read aging counters. These counters + * will be parallel loaded after reset, or after each grant to the corresp + * onding port. The aging counters down-count every clock cycle where the p + * ort is requesting but not granted. The higher significant 5-bits of the + * read aging counter sets the priority of the read channel of a given port + * . Port's priority will increase as the higher significant 5-bits of the + * counter starts to decrease. When the aging counter becomes 0, the corres + * ponding port channel will have the highest priority level (timeout condi + * tion - Priority0). For multi-port configurations, the aging counters can + * not be used to set port priorities when external dynamic priority inputs + * (arqos) are enabled (timeout is still applicable). For single port conf + * igurations, the aging counters are only used when they timeout (become 0 + * ) to force read-write direction switching. In this case, external dynami + * c priority input, arqos (for reads only) can still be used to set the DD + * RC read priority (2 priority levels: low priority read - LPR, high prior + * ity read - HPR) on a command by command basis. Note: The two LSBs of thi + * s register field are tied internally to 2'b00. +*/ #undef DDRC_PCFGR_2_RD_PORT_PRIORITY_DEFVAL #undef DDRC_PCFGR_2_RD_PORT_PRIORITY_SHIFT #undef DDRC_PCFGR_2_RD_PORT_PRIORITY_MASK -#define DDRC_PCFGR_2_RD_PORT_PRIORITY_DEFVAL 0x00000000 -#define DDRC_PCFGR_2_RD_PORT_PRIORITY_SHIFT 0 -#define DDRC_PCFGR_2_RD_PORT_PRIORITY_MASK 0x000003FFU +#define DDRC_PCFGR_2_RD_PORT_PRIORITY_DEFVAL 0x00000000 +#define DDRC_PCFGR_2_RD_PORT_PRIORITY_SHIFT 0 +#define DDRC_PCFGR_2_RD_PORT_PRIORITY_MASK 0x000003FFU -/*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register.*/ +/* +* If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. +*/ #undef DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_DEFVAL #undef DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_SHIFT #undef DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_MASK -#define DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_DEFVAL 0x00004000 -#define DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_SHIFT 14 -#define DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_MASK 0x00004000U +#define DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_SHIFT 14 +#define DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_MASK 0x00004000U -/*If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register - Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is - not associated with any particular command).*/ +/* +* If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + * bled and awurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + * serted anytime and as long as required which is independent of address h + * andshaking (it is not associated with any particular command). +*/ #undef DDRC_PCFGW_2_WR_PORT_URGENT_EN_DEFVAL #undef DDRC_PCFGW_2_WR_PORT_URGENT_EN_SHIFT #undef DDRC_PCFGW_2_WR_PORT_URGENT_EN_MASK -#define DDRC_PCFGW_2_WR_PORT_URGENT_EN_DEFVAL 0x00004000 -#define DDRC_PCFGW_2_WR_PORT_URGENT_EN_SHIFT 13 -#define DDRC_PCFGW_2_WR_PORT_URGENT_EN_MASK 0x00002000U +#define DDRC_PCFGW_2_WR_PORT_URGENT_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_2_WR_PORT_URGENT_EN_SHIFT 13 +#define DDRC_PCFGW_2_WR_PORT_URGENT_EN_MASK 0x00002000U -/*If set to 1, enables aging function for the write channel of the port.*/ +/* +* If set to 1, enables aging function for the write channel of the port. +*/ #undef DDRC_PCFGW_2_WR_PORT_AGING_EN_DEFVAL #undef DDRC_PCFGW_2_WR_PORT_AGING_EN_SHIFT #undef DDRC_PCFGW_2_WR_PORT_AGING_EN_MASK -#define DDRC_PCFGW_2_WR_PORT_AGING_EN_DEFVAL 0x00004000 -#define DDRC_PCFGW_2_WR_PORT_AGING_EN_SHIFT 12 -#define DDRC_PCFGW_2_WR_PORT_AGING_EN_MASK 0x00001000U +#define DDRC_PCFGW_2_WR_PORT_AGING_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_2_WR_PORT_AGING_EN_SHIFT 12 +#define DDRC_PCFGW_2_WR_PORT_AGING_EN_MASK 0x00001000U -/*Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each - rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port - s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0 - the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno - be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For - ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch - ng. Note: The two LSBs of this register field are tied internally to 2'b00.*/ +/* +* Determines the initial load value of write aging counters. These counter + * s will be parallel loaded after reset, or after each grant to the corres + * ponding port. The aging counters down-count every clock cycle where the + * port is requesting but not granted. The higher significant 5-bits of the + * write aging counter sets the initial priority of the write channel of a + * given port. Port's priority will increase as the higher significant 5-b + * its of the counter starts to decrease. When the aging counter becomes 0, + * the corresponding port channel will have the highest priority level. Fo + * r multi-port configurations, the aging counters cannot be used to set po + * rt priorities when external dynamic priority inputs (awqos) are enabled + * (timeout is still applicable). For single port configurations, the aging + * counters are only used when they timeout (become 0) to force read-write + * direction switching. Note: The two LSBs of this register field are tied + * internally to 2'b00. +*/ #undef DDRC_PCFGW_2_WR_PORT_PRIORITY_DEFVAL #undef DDRC_PCFGW_2_WR_PORT_PRIORITY_SHIFT #undef DDRC_PCFGW_2_WR_PORT_PRIORITY_MASK -#define DDRC_PCFGW_2_WR_PORT_PRIORITY_DEFVAL 0x00004000 -#define DDRC_PCFGW_2_WR_PORT_PRIORITY_SHIFT 0 -#define DDRC_PCFGW_2_WR_PORT_PRIORITY_MASK 0x000003FFU +#define DDRC_PCFGW_2_WR_PORT_PRIORITY_DEFVAL 0x00004000 +#define DDRC_PCFGW_2_WR_PORT_PRIORITY_SHIFT 0 +#define DDRC_PCFGW_2_WR_PORT_PRIORITY_MASK 0x000003FFU -/*Enables port n.*/ +/* +* Enables port n. +*/ #undef DDRC_PCTRL_2_PORT_EN_DEFVAL #undef DDRC_PCTRL_2_PORT_EN_SHIFT #undef DDRC_PCTRL_2_PORT_EN_MASK -#define DDRC_PCTRL_2_PORT_EN_DEFVAL -#define DDRC_PCTRL_2_PORT_EN_SHIFT 0 -#define DDRC_PCTRL_2_PORT_EN_MASK 0x00000001U +#define DDRC_PCTRL_2_PORT_EN_DEFVAL +#define DDRC_PCTRL_2_PORT_EN_SHIFT 0 +#define DDRC_PCTRL_2_PORT_EN_MASK 0x00000001U -/*This bitfield indicates the traffic class of region2. For dual address queue configurations, region2 maps to the red address - ueue. Valid values are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and traffic class of region2 - s set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/ +/* +* This bitfield indicates the traffic class of region2. For dual address q + * ueue configurations, region2 maps to the red address queue. Valid values + * are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN + * = 0) and traffic class of region2 is set to 1 (VPR), VPR traffic is ali + * ased to LPR traffic. +*/ #undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_DEFVAL #undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_SHIFT #undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_MASK -#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_DEFVAL 0x02000E00 -#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_SHIFT 24 -#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_MASK 0x03000000U +#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_DEFVAL 0x02000E00 +#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_SHIFT 24 +#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_MASK 0x03000000U -/*This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf - gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is - disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/ +/* +* This bitfield indicates the traffic class of region 1. Valid values are: + * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + * maps to the blue address queue. In this case, valid values are 0: LPR a + * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. +*/ #undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_DEFVAL #undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_SHIFT #undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_MASK -#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_DEFVAL 0x02000E00 -#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_SHIFT 20 -#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_MASK 0x00300000U +#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_DEFVAL 0x02000E00 +#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_SHIFT 20 +#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_MASK 0x00300000U -/*This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi - urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i - disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/ +/* +* This bitfield indicates the traffic class of region 0. Valid values are: + * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + * maps to the blue address queue. In this case, valid values are: 0: LPR + * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. +*/ #undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_DEFVAL #undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_SHIFT #undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_MASK -#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_DEFVAL 0x02000E00 -#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_SHIFT 16 -#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_MASK 0x00030000U +#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_DEFVAL 0x02000E00 +#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_SHIFT 16 +#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_MASK 0x00030000U -/*Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (le - el1 + 1) to 14 which corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note that for PA, arqos values are used - directly as port priorities, where the higher the value corresponds to higher port priority. All of the map_level* registers - ust be set to distinct values.*/ +/* +* Separation level2 indicating the end of region1 mapping; start of region + * 1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 whi + * ch corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note + * that for PA, arqos values are used directly as port priorities, where t + * he higher the value corresponds to higher port priority. All of the map_ + * level* registers must be set to distinct values. +*/ #undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_DEFVAL #undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_SHIFT #undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_MASK -#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_DEFVAL 0x02000E00 -#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_SHIFT 8 -#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_MASK 0x00000F00U +#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_DEFVAL 0x02000E00 +#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_SHIFT 8 +#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_MASK 0x00000F00U -/*Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d - al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio - ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc - values.*/ +/* +* Separation level1 indicating the end of region0 mapping; start of region + * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + * lues are used directly as port priorities, where the higher the value co + * rresponds to higher port priority. All of the map_level* registers must + * be set to distinct values. +*/ #undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_DEFVAL #undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_SHIFT #undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_MASK -#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_DEFVAL 0x02000E00 -#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_SHIFT 0 -#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_MASK 0x0000000FU +#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_DEFVAL 0x02000E00 +#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_SHIFT 0 +#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_MASK 0x0000000FU -/*Specifies the timeout value for transactions mapped to the red address queue.*/ +/* +* Specifies the timeout value for transactions mapped to the red address q + * ueue. +*/ #undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_DEFVAL #undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_SHIFT #undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_MASK -#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_DEFVAL 0x00000000 -#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_SHIFT 16 -#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_MASK 0x07FF0000U +#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_DEFVAL 0x00000000 +#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_SHIFT 16 +#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_MASK 0x07FF0000U -/*Specifies the timeout value for transactions mapped to the blue address queue.*/ +/* +* Specifies the timeout value for transactions mapped to the blue address + * queue. +*/ #undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_DEFVAL #undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_SHIFT #undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_MASK -#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_DEFVAL 0x00000000 -#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_SHIFT 0 -#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_MASK 0x000007FFU +#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_DEFVAL 0x00000000 +#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_SHIFT 0 +#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_MASK 0x000007FFU -/*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register.*/ +/* +* If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. +*/ #undef DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_DEFVAL #undef DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_SHIFT #undef DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_MASK -#define DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_DEFVAL 0x00000000 -#define DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_SHIFT 14 -#define DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_MASK 0x00004000U +#define DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_SHIFT 14 +#define DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_MASK 0x00004000U -/*If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG. - o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add - ess handshaking (it is not associated with any particular command).*/ +/* +* If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + * bled and arurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + * urgent signal can be asserted anytime and as long as required which is i + * ndependent of address handshaking (it is not associated with any particu + * lar command). +*/ #undef DDRC_PCFGR_3_RD_PORT_URGENT_EN_DEFVAL #undef DDRC_PCFGR_3_RD_PORT_URGENT_EN_SHIFT #undef DDRC_PCFGR_3_RD_PORT_URGENT_EN_MASK -#define DDRC_PCFGR_3_RD_PORT_URGENT_EN_DEFVAL 0x00000000 -#define DDRC_PCFGR_3_RD_PORT_URGENT_EN_SHIFT 13 -#define DDRC_PCFGR_3_RD_PORT_URGENT_EN_MASK 0x00002000U +#define DDRC_PCFGR_3_RD_PORT_URGENT_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_3_RD_PORT_URGENT_EN_SHIFT 13 +#define DDRC_PCFGR_3_RD_PORT_URGENT_EN_MASK 0x00002000U -/*If set to 1, enables aging function for the read channel of the port.*/ +/* +* If set to 1, enables aging function for the read channel of the port. +*/ #undef DDRC_PCFGR_3_RD_PORT_AGING_EN_DEFVAL #undef DDRC_PCFGR_3_RD_PORT_AGING_EN_SHIFT #undef DDRC_PCFGR_3_RD_PORT_AGING_EN_MASK -#define DDRC_PCFGR_3_RD_PORT_AGING_EN_DEFVAL 0x00000000 -#define DDRC_PCFGR_3_RD_PORT_AGING_EN_SHIFT 12 -#define DDRC_PCFGR_3_RD_PORT_AGING_EN_MASK 0x00001000U +#define DDRC_PCFGR_3_RD_PORT_AGING_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_3_RD_PORT_AGING_EN_SHIFT 12 +#define DDRC_PCFGR_3_RD_PORT_AGING_EN_MASK 0x00001000U -/*Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g - ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority - will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre - ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the - aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st - ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w - ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D - RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: - he two LSBs of this register field are tied internally to 2'b00.*/ +/* +* Determines the initial load value of read aging counters. These counters + * will be parallel loaded after reset, or after each grant to the corresp + * onding port. The aging counters down-count every clock cycle where the p + * ort is requesting but not granted. The higher significant 5-bits of the + * read aging counter sets the priority of the read channel of a given port + * . Port's priority will increase as the higher significant 5-bits of the + * counter starts to decrease. When the aging counter becomes 0, the corres + * ponding port channel will have the highest priority level (timeout condi + * tion - Priority0). For multi-port configurations, the aging counters can + * not be used to set port priorities when external dynamic priority inputs + * (arqos) are enabled (timeout is still applicable). For single port conf + * igurations, the aging counters are only used when they timeout (become 0 + * ) to force read-write direction switching. In this case, external dynami + * c priority input, arqos (for reads only) can still be used to set the DD + * RC read priority (2 priority levels: low priority read - LPR, high prior + * ity read - HPR) on a command by command basis. Note: The two LSBs of thi + * s register field are tied internally to 2'b00. +*/ #undef DDRC_PCFGR_3_RD_PORT_PRIORITY_DEFVAL #undef DDRC_PCFGR_3_RD_PORT_PRIORITY_SHIFT #undef DDRC_PCFGR_3_RD_PORT_PRIORITY_MASK -#define DDRC_PCFGR_3_RD_PORT_PRIORITY_DEFVAL 0x00000000 -#define DDRC_PCFGR_3_RD_PORT_PRIORITY_SHIFT 0 -#define DDRC_PCFGR_3_RD_PORT_PRIORITY_MASK 0x000003FFU +#define DDRC_PCFGR_3_RD_PORT_PRIORITY_DEFVAL 0x00000000 +#define DDRC_PCFGR_3_RD_PORT_PRIORITY_SHIFT 0 +#define DDRC_PCFGR_3_RD_PORT_PRIORITY_MASK 0x000003FFU -/*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register.*/ +/* +* If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. +*/ #undef DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_DEFVAL #undef DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_SHIFT #undef DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_MASK -#define DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_DEFVAL 0x00004000 -#define DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_SHIFT 14 -#define DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_MASK 0x00004000U +#define DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_SHIFT 14 +#define DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_MASK 0x00004000U -/*If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register - Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is - not associated with any particular command).*/ +/* +* If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + * bled and awurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + * serted anytime and as long as required which is independent of address h + * andshaking (it is not associated with any particular command). +*/ #undef DDRC_PCFGW_3_WR_PORT_URGENT_EN_DEFVAL #undef DDRC_PCFGW_3_WR_PORT_URGENT_EN_SHIFT #undef DDRC_PCFGW_3_WR_PORT_URGENT_EN_MASK -#define DDRC_PCFGW_3_WR_PORT_URGENT_EN_DEFVAL 0x00004000 -#define DDRC_PCFGW_3_WR_PORT_URGENT_EN_SHIFT 13 -#define DDRC_PCFGW_3_WR_PORT_URGENT_EN_MASK 0x00002000U +#define DDRC_PCFGW_3_WR_PORT_URGENT_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_3_WR_PORT_URGENT_EN_SHIFT 13 +#define DDRC_PCFGW_3_WR_PORT_URGENT_EN_MASK 0x00002000U -/*If set to 1, enables aging function for the write channel of the port.*/ +/* +* If set to 1, enables aging function for the write channel of the port. +*/ #undef DDRC_PCFGW_3_WR_PORT_AGING_EN_DEFVAL #undef DDRC_PCFGW_3_WR_PORT_AGING_EN_SHIFT #undef DDRC_PCFGW_3_WR_PORT_AGING_EN_MASK -#define DDRC_PCFGW_3_WR_PORT_AGING_EN_DEFVAL 0x00004000 -#define DDRC_PCFGW_3_WR_PORT_AGING_EN_SHIFT 12 -#define DDRC_PCFGW_3_WR_PORT_AGING_EN_MASK 0x00001000U +#define DDRC_PCFGW_3_WR_PORT_AGING_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_3_WR_PORT_AGING_EN_SHIFT 12 +#define DDRC_PCFGW_3_WR_PORT_AGING_EN_MASK 0x00001000U -/*Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each - rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port - s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0 - the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno - be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For - ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch - ng. Note: The two LSBs of this register field are tied internally to 2'b00.*/ +/* +* Determines the initial load value of write aging counters. These counter + * s will be parallel loaded after reset, or after each grant to the corres + * ponding port. The aging counters down-count every clock cycle where the + * port is requesting but not granted. The higher significant 5-bits of the + * write aging counter sets the initial priority of the write channel of a + * given port. Port's priority will increase as the higher significant 5-b + * its of the counter starts to decrease. When the aging counter becomes 0, + * the corresponding port channel will have the highest priority level. Fo + * r multi-port configurations, the aging counters cannot be used to set po + * rt priorities when external dynamic priority inputs (awqos) are enabled + * (timeout is still applicable). For single port configurations, the aging + * counters are only used when they timeout (become 0) to force read-write + * direction switching. Note: The two LSBs of this register field are tied + * internally to 2'b00. +*/ #undef DDRC_PCFGW_3_WR_PORT_PRIORITY_DEFVAL #undef DDRC_PCFGW_3_WR_PORT_PRIORITY_SHIFT #undef DDRC_PCFGW_3_WR_PORT_PRIORITY_MASK -#define DDRC_PCFGW_3_WR_PORT_PRIORITY_DEFVAL 0x00004000 -#define DDRC_PCFGW_3_WR_PORT_PRIORITY_SHIFT 0 -#define DDRC_PCFGW_3_WR_PORT_PRIORITY_MASK 0x000003FFU +#define DDRC_PCFGW_3_WR_PORT_PRIORITY_DEFVAL 0x00004000 +#define DDRC_PCFGW_3_WR_PORT_PRIORITY_SHIFT 0 +#define DDRC_PCFGW_3_WR_PORT_PRIORITY_MASK 0x000003FFU -/*Enables port n.*/ +/* +* Enables port n. +*/ #undef DDRC_PCTRL_3_PORT_EN_DEFVAL #undef DDRC_PCTRL_3_PORT_EN_SHIFT #undef DDRC_PCTRL_3_PORT_EN_MASK -#define DDRC_PCTRL_3_PORT_EN_DEFVAL -#define DDRC_PCTRL_3_PORT_EN_SHIFT 0 -#define DDRC_PCTRL_3_PORT_EN_MASK 0x00000001U +#define DDRC_PCTRL_3_PORT_EN_DEFVAL +#define DDRC_PCTRL_3_PORT_EN_SHIFT 0 +#define DDRC_PCTRL_3_PORT_EN_MASK 0x00000001U -/*This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf - gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is - disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/ +/* +* This bitfield indicates the traffic class of region 1. Valid values are: + * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + * maps to the blue address queue. In this case, valid values are 0: LPR a + * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. +*/ #undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_DEFVAL #undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_SHIFT #undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_MASK -#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_DEFVAL 0x00000000 -#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_SHIFT 20 -#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_MASK 0x00300000U +#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_DEFVAL 0x00000000 +#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_SHIFT 20 +#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_MASK 0x00300000U -/*This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi - urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i - disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/ +/* +* This bitfield indicates the traffic class of region 0. Valid values are: + * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + * maps to the blue address queue. In this case, valid values are: 0: LPR + * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. +*/ #undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_DEFVAL #undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_SHIFT #undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_MASK -#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_DEFVAL 0x00000000 -#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_SHIFT 16 -#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_MASK 0x00030000U +#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_DEFVAL 0x00000000 +#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_SHIFT 16 +#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_MASK 0x00030000U -/*Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d - al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio - ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc - values.*/ +/* +* Separation level1 indicating the end of region0 mapping; start of region + * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + * lues are used directly as port priorities, where the higher the value co + * rresponds to higher port priority. All of the map_level* registers must + * be set to distinct values. +*/ #undef DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_DEFVAL #undef DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_SHIFT #undef DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_MASK -#define DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_DEFVAL 0x00000000 -#define DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_SHIFT 0 -#define DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_MASK 0x0000000FU +#define DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_DEFVAL 0x00000000 +#define DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_SHIFT 0 +#define DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_MASK 0x0000000FU -/*Specifies the timeout value for transactions mapped to the red address queue.*/ +/* +* Specifies the timeout value for transactions mapped to the red address q + * ueue. +*/ #undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_DEFVAL #undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_SHIFT #undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_MASK -#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_DEFVAL 0x00000000 -#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_SHIFT 16 -#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_MASK 0x07FF0000U +#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_DEFVAL 0x00000000 +#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_SHIFT 16 +#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_MASK 0x07FF0000U -/*Specifies the timeout value for transactions mapped to the blue address queue.*/ +/* +* Specifies the timeout value for transactions mapped to the blue address + * queue. +*/ #undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_DEFVAL #undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_SHIFT #undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_MASK -#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_DEFVAL 0x00000000 -#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_SHIFT 0 -#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_MASK 0x000007FFU +#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_DEFVAL 0x00000000 +#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_SHIFT 0 +#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_MASK 0x000007FFU -/*This bitfield indicates the traffic class of region 1. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2 - VPW_EN = 0) and traffic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW traffic.*/ +/* +* This bitfield indicates the traffic class of region 1. Valid values are: + * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + * affic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW + * traffic. +*/ #undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_DEFVAL #undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_SHIFT #undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_MASK -#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_DEFVAL 0x00000000 -#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_SHIFT 20 -#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_MASK 0x00300000U +#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_DEFVAL 0x00000000 +#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_SHIFT 20 +#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_MASK 0x00300000U -/*This bitfield indicates the traffic class of region 0. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2 - VPW_EN = 0) and traffic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW traffic.*/ +/* +* This bitfield indicates the traffic class of region 0. Valid values are: + * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + * affic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW + * traffic. +*/ #undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_DEFVAL #undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_SHIFT #undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_MASK -#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_DEFVAL 0x00000000 -#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_SHIFT 16 -#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_MASK 0x00030000U +#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_DEFVAL 0x00000000 +#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_SHIFT 16 +#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_MASK 0x00030000U -/*Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 14 which c - rresponds to awqos. Note that for PA, awqos values are used directly as port priorities, where the higher the value correspon - s to higher port priority.*/ +/* +* Separation level indicating the end of region0 mapping; start of region0 + * is 0. Possible values for level1 are 0 to 14 which corresponds to awqos + * . Note that for PA, awqos values are used directly as port priorities, w + * here the higher the value corresponds to higher port priority. +*/ #undef DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_DEFVAL #undef DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_SHIFT #undef DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_MASK -#define DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_DEFVAL 0x00000000 -#define DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_SHIFT 0 -#define DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_MASK 0x0000000FU +#define DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_DEFVAL 0x00000000 +#define DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_SHIFT 0 +#define DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_MASK 0x0000000FU -/*Specifies the timeout value for write transactions.*/ +/* +* Specifies the timeout value for write transactions. +*/ #undef DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_DEFVAL #undef DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_SHIFT #undef DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_MASK -#define DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_DEFVAL -#define DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_SHIFT 0 -#define DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_MASK 0x000007FFU +#define DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_DEFVAL +#define DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_SHIFT 0 +#define DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_MASK 0x000007FFU -/*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register.*/ +/* +* If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. +*/ #undef DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_DEFVAL #undef DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_SHIFT #undef DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_MASK -#define DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_DEFVAL 0x00000000 -#define DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_SHIFT 14 -#define DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_MASK 0x00004000U +#define DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_SHIFT 14 +#define DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_MASK 0x00004000U -/*If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG. - o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add - ess handshaking (it is not associated with any particular command).*/ +/* +* If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + * bled and arurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + * urgent signal can be asserted anytime and as long as required which is i + * ndependent of address handshaking (it is not associated with any particu + * lar command). +*/ #undef DDRC_PCFGR_4_RD_PORT_URGENT_EN_DEFVAL #undef DDRC_PCFGR_4_RD_PORT_URGENT_EN_SHIFT #undef DDRC_PCFGR_4_RD_PORT_URGENT_EN_MASK -#define DDRC_PCFGR_4_RD_PORT_URGENT_EN_DEFVAL 0x00000000 -#define DDRC_PCFGR_4_RD_PORT_URGENT_EN_SHIFT 13 -#define DDRC_PCFGR_4_RD_PORT_URGENT_EN_MASK 0x00002000U +#define DDRC_PCFGR_4_RD_PORT_URGENT_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_4_RD_PORT_URGENT_EN_SHIFT 13 +#define DDRC_PCFGR_4_RD_PORT_URGENT_EN_MASK 0x00002000U -/*If set to 1, enables aging function for the read channel of the port.*/ +/* +* If set to 1, enables aging function for the read channel of the port. +*/ #undef DDRC_PCFGR_4_RD_PORT_AGING_EN_DEFVAL #undef DDRC_PCFGR_4_RD_PORT_AGING_EN_SHIFT #undef DDRC_PCFGR_4_RD_PORT_AGING_EN_MASK -#define DDRC_PCFGR_4_RD_PORT_AGING_EN_DEFVAL 0x00000000 -#define DDRC_PCFGR_4_RD_PORT_AGING_EN_SHIFT 12 -#define DDRC_PCFGR_4_RD_PORT_AGING_EN_MASK 0x00001000U +#define DDRC_PCFGR_4_RD_PORT_AGING_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_4_RD_PORT_AGING_EN_SHIFT 12 +#define DDRC_PCFGR_4_RD_PORT_AGING_EN_MASK 0x00001000U -/*Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g - ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority - will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre - ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the - aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st - ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w - ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D - RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: - he two LSBs of this register field are tied internally to 2'b00.*/ +/* +* Determines the initial load value of read aging counters. These counters + * will be parallel loaded after reset, or after each grant to the corresp + * onding port. The aging counters down-count every clock cycle where the p + * ort is requesting but not granted. The higher significant 5-bits of the + * read aging counter sets the priority of the read channel of a given port + * . Port's priority will increase as the higher significant 5-bits of the + * counter starts to decrease. When the aging counter becomes 0, the corres + * ponding port channel will have the highest priority level (timeout condi + * tion - Priority0). For multi-port configurations, the aging counters can + * not be used to set port priorities when external dynamic priority inputs + * (arqos) are enabled (timeout is still applicable). For single port conf + * igurations, the aging counters are only used when they timeout (become 0 + * ) to force read-write direction switching. In this case, external dynami + * c priority input, arqos (for reads only) can still be used to set the DD + * RC read priority (2 priority levels: low priority read - LPR, high prior + * ity read - HPR) on a command by command basis. Note: The two LSBs of thi + * s register field are tied internally to 2'b00. +*/ #undef DDRC_PCFGR_4_RD_PORT_PRIORITY_DEFVAL #undef DDRC_PCFGR_4_RD_PORT_PRIORITY_SHIFT #undef DDRC_PCFGR_4_RD_PORT_PRIORITY_MASK -#define DDRC_PCFGR_4_RD_PORT_PRIORITY_DEFVAL 0x00000000 -#define DDRC_PCFGR_4_RD_PORT_PRIORITY_SHIFT 0 -#define DDRC_PCFGR_4_RD_PORT_PRIORITY_MASK 0x000003FFU +#define DDRC_PCFGR_4_RD_PORT_PRIORITY_DEFVAL 0x00000000 +#define DDRC_PCFGR_4_RD_PORT_PRIORITY_SHIFT 0 +#define DDRC_PCFGR_4_RD_PORT_PRIORITY_MASK 0x000003FFU -/*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register.*/ +/* +* If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. +*/ #undef DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_DEFVAL #undef DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_SHIFT #undef DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_MASK -#define DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_DEFVAL 0x00004000 -#define DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_SHIFT 14 -#define DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_MASK 0x00004000U +#define DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_SHIFT 14 +#define DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_MASK 0x00004000U -/*If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register - Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is - not associated with any particular command).*/ +/* +* If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + * bled and awurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + * serted anytime and as long as required which is independent of address h + * andshaking (it is not associated with any particular command). +*/ #undef DDRC_PCFGW_4_WR_PORT_URGENT_EN_DEFVAL #undef DDRC_PCFGW_4_WR_PORT_URGENT_EN_SHIFT #undef DDRC_PCFGW_4_WR_PORT_URGENT_EN_MASK -#define DDRC_PCFGW_4_WR_PORT_URGENT_EN_DEFVAL 0x00004000 -#define DDRC_PCFGW_4_WR_PORT_URGENT_EN_SHIFT 13 -#define DDRC_PCFGW_4_WR_PORT_URGENT_EN_MASK 0x00002000U +#define DDRC_PCFGW_4_WR_PORT_URGENT_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_4_WR_PORT_URGENT_EN_SHIFT 13 +#define DDRC_PCFGW_4_WR_PORT_URGENT_EN_MASK 0x00002000U -/*If set to 1, enables aging function for the write channel of the port.*/ +/* +* If set to 1, enables aging function for the write channel of the port. +*/ #undef DDRC_PCFGW_4_WR_PORT_AGING_EN_DEFVAL #undef DDRC_PCFGW_4_WR_PORT_AGING_EN_SHIFT #undef DDRC_PCFGW_4_WR_PORT_AGING_EN_MASK -#define DDRC_PCFGW_4_WR_PORT_AGING_EN_DEFVAL 0x00004000 -#define DDRC_PCFGW_4_WR_PORT_AGING_EN_SHIFT 12 -#define DDRC_PCFGW_4_WR_PORT_AGING_EN_MASK 0x00001000U +#define DDRC_PCFGW_4_WR_PORT_AGING_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_4_WR_PORT_AGING_EN_SHIFT 12 +#define DDRC_PCFGW_4_WR_PORT_AGING_EN_MASK 0x00001000U -/*Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each - rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port - s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0 - the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno - be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For - ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch - ng. Note: The two LSBs of this register field are tied internally to 2'b00.*/ +/* +* Determines the initial load value of write aging counters. These counter + * s will be parallel loaded after reset, or after each grant to the corres + * ponding port. The aging counters down-count every clock cycle where the + * port is requesting but not granted. The higher significant 5-bits of the + * write aging counter sets the initial priority of the write channel of a + * given port. Port's priority will increase as the higher significant 5-b + * its of the counter starts to decrease. When the aging counter becomes 0, + * the corresponding port channel will have the highest priority level. Fo + * r multi-port configurations, the aging counters cannot be used to set po + * rt priorities when external dynamic priority inputs (awqos) are enabled + * (timeout is still applicable). For single port configurations, the aging + * counters are only used when they timeout (become 0) to force read-write + * direction switching. Note: The two LSBs of this register field are tied + * internally to 2'b00. +*/ #undef DDRC_PCFGW_4_WR_PORT_PRIORITY_DEFVAL #undef DDRC_PCFGW_4_WR_PORT_PRIORITY_SHIFT #undef DDRC_PCFGW_4_WR_PORT_PRIORITY_MASK -#define DDRC_PCFGW_4_WR_PORT_PRIORITY_DEFVAL 0x00004000 -#define DDRC_PCFGW_4_WR_PORT_PRIORITY_SHIFT 0 -#define DDRC_PCFGW_4_WR_PORT_PRIORITY_MASK 0x000003FFU +#define DDRC_PCFGW_4_WR_PORT_PRIORITY_DEFVAL 0x00004000 +#define DDRC_PCFGW_4_WR_PORT_PRIORITY_SHIFT 0 +#define DDRC_PCFGW_4_WR_PORT_PRIORITY_MASK 0x000003FFU -/*Enables port n.*/ +/* +* Enables port n. +*/ #undef DDRC_PCTRL_4_PORT_EN_DEFVAL #undef DDRC_PCTRL_4_PORT_EN_SHIFT #undef DDRC_PCTRL_4_PORT_EN_MASK -#define DDRC_PCTRL_4_PORT_EN_DEFVAL -#define DDRC_PCTRL_4_PORT_EN_SHIFT 0 -#define DDRC_PCTRL_4_PORT_EN_MASK 0x00000001U +#define DDRC_PCTRL_4_PORT_EN_DEFVAL +#define DDRC_PCTRL_4_PORT_EN_SHIFT 0 +#define DDRC_PCTRL_4_PORT_EN_MASK 0x00000001U -/*This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf - gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is - disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/ +/* +* This bitfield indicates the traffic class of region 1. Valid values are: + * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + * maps to the blue address queue. In this case, valid values are 0: LPR a + * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. +*/ #undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_DEFVAL #undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_SHIFT #undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_MASK -#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_DEFVAL 0x00000000 -#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_SHIFT 20 -#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_MASK 0x00300000U +#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_DEFVAL 0x00000000 +#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_SHIFT 20 +#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_MASK 0x00300000U -/*This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi - urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i - disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/ +/* +* This bitfield indicates the traffic class of region 0. Valid values are: + * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + * maps to the blue address queue. In this case, valid values are: 0: LPR + * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. +*/ #undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_DEFVAL #undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_SHIFT #undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_MASK -#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_DEFVAL 0x00000000 -#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_SHIFT 16 -#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_MASK 0x00030000U +#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_DEFVAL 0x00000000 +#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_SHIFT 16 +#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_MASK 0x00030000U -/*Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d - al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio - ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc - values.*/ +/* +* Separation level1 indicating the end of region0 mapping; start of region + * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + * lues are used directly as port priorities, where the higher the value co + * rresponds to higher port priority. All of the map_level* registers must + * be set to distinct values. +*/ #undef DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_DEFVAL #undef DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_SHIFT #undef DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_MASK -#define DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_DEFVAL 0x00000000 -#define DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_SHIFT 0 -#define DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_MASK 0x0000000FU +#define DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_DEFVAL 0x00000000 +#define DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_SHIFT 0 +#define DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_MASK 0x0000000FU -/*Specifies the timeout value for transactions mapped to the red address queue.*/ +/* +* Specifies the timeout value for transactions mapped to the red address q + * ueue. +*/ #undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_DEFVAL #undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_SHIFT #undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_MASK -#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_DEFVAL 0x00000000 -#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_SHIFT 16 -#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_MASK 0x07FF0000U +#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_DEFVAL 0x00000000 +#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_SHIFT 16 +#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_MASK 0x07FF0000U -/*Specifies the timeout value for transactions mapped to the blue address queue.*/ +/* +* Specifies the timeout value for transactions mapped to the blue address + * queue. +*/ #undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_DEFVAL #undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_SHIFT #undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_MASK -#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_DEFVAL 0x00000000 -#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_SHIFT 0 -#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_MASK 0x000007FFU +#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_DEFVAL 0x00000000 +#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_SHIFT 0 +#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_MASK 0x000007FFU -/*This bitfield indicates the traffic class of region 1. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2 - VPW_EN = 0) and traffic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW traffic.*/ +/* +* This bitfield indicates the traffic class of region 1. Valid values are: + * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + * affic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW + * traffic. +*/ #undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_DEFVAL #undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_SHIFT #undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_MASK -#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_DEFVAL 0x00000000 -#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_SHIFT 20 -#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_MASK 0x00300000U +#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_DEFVAL 0x00000000 +#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_SHIFT 20 +#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_MASK 0x00300000U -/*This bitfield indicates the traffic class of region 0. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2 - VPW_EN = 0) and traffic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW traffic.*/ +/* +* This bitfield indicates the traffic class of region 0. Valid values are: + * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + * affic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW + * traffic. +*/ #undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_DEFVAL #undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_SHIFT #undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_MASK -#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_DEFVAL 0x00000000 -#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_SHIFT 16 -#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_MASK 0x00030000U +#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_DEFVAL 0x00000000 +#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_SHIFT 16 +#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_MASK 0x00030000U -/*Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 14 which c - rresponds to awqos. Note that for PA, awqos values are used directly as port priorities, where the higher the value correspon - s to higher port priority.*/ +/* +* Separation level indicating the end of region0 mapping; start of region0 + * is 0. Possible values for level1 are 0 to 14 which corresponds to awqos + * . Note that for PA, awqos values are used directly as port priorities, w + * here the higher the value corresponds to higher port priority. +*/ #undef DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_DEFVAL #undef DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_SHIFT #undef DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_MASK -#define DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_DEFVAL 0x00000000 -#define DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_SHIFT 0 -#define DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_MASK 0x0000000FU +#define DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_DEFVAL 0x00000000 +#define DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_SHIFT 0 +#define DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_MASK 0x0000000FU -/*Specifies the timeout value for write transactions.*/ +/* +* Specifies the timeout value for write transactions. +*/ #undef DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_DEFVAL #undef DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_SHIFT #undef DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_MASK -#define DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_DEFVAL -#define DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_SHIFT 0 -#define DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_MASK 0x000007FFU +#define DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_DEFVAL +#define DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_SHIFT 0 +#define DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_MASK 0x000007FFU -/*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register.*/ +/* +* If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. +*/ #undef DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_DEFVAL #undef DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_SHIFT #undef DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_MASK -#define DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_DEFVAL 0x00000000 -#define DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_SHIFT 14 -#define DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_MASK 0x00004000U +#define DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_SHIFT 14 +#define DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_MASK 0x00004000U -/*If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG. - o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add - ess handshaking (it is not associated with any particular command).*/ +/* +* If set to 1, enables the AXI urgent sideband signal (arurgent). When ena + * bled and arurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DD + * RC is asserted if enabled in PCCFG.go2critical_en register. Note that ar + * urgent signal can be asserted anytime and as long as required which is i + * ndependent of address handshaking (it is not associated with any particu + * lar command). +*/ #undef DDRC_PCFGR_5_RD_PORT_URGENT_EN_DEFVAL #undef DDRC_PCFGR_5_RD_PORT_URGENT_EN_SHIFT #undef DDRC_PCFGR_5_RD_PORT_URGENT_EN_MASK -#define DDRC_PCFGR_5_RD_PORT_URGENT_EN_DEFVAL 0x00000000 -#define DDRC_PCFGR_5_RD_PORT_URGENT_EN_SHIFT 13 -#define DDRC_PCFGR_5_RD_PORT_URGENT_EN_MASK 0x00002000U +#define DDRC_PCFGR_5_RD_PORT_URGENT_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_5_RD_PORT_URGENT_EN_SHIFT 13 +#define DDRC_PCFGR_5_RD_PORT_URGENT_EN_MASK 0x00002000U -/*If set to 1, enables aging function for the read channel of the port.*/ +/* +* If set to 1, enables aging function for the read channel of the port. +*/ #undef DDRC_PCFGR_5_RD_PORT_AGING_EN_DEFVAL #undef DDRC_PCFGR_5_RD_PORT_AGING_EN_SHIFT #undef DDRC_PCFGR_5_RD_PORT_AGING_EN_MASK -#define DDRC_PCFGR_5_RD_PORT_AGING_EN_DEFVAL 0x00000000 -#define DDRC_PCFGR_5_RD_PORT_AGING_EN_SHIFT 12 -#define DDRC_PCFGR_5_RD_PORT_AGING_EN_MASK 0x00001000U +#define DDRC_PCFGR_5_RD_PORT_AGING_EN_DEFVAL 0x00000000 +#define DDRC_PCFGR_5_RD_PORT_AGING_EN_SHIFT 12 +#define DDRC_PCFGR_5_RD_PORT_AGING_EN_MASK 0x00001000U -/*Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g - ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority - will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre - ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the - aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st - ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w - ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D - RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: - he two LSBs of this register field are tied internally to 2'b00.*/ +/* +* Determines the initial load value of read aging counters. These counters + * will be parallel loaded after reset, or after each grant to the corresp + * onding port. The aging counters down-count every clock cycle where the p + * ort is requesting but not granted. The higher significant 5-bits of the + * read aging counter sets the priority of the read channel of a given port + * . Port's priority will increase as the higher significant 5-bits of the + * counter starts to decrease. When the aging counter becomes 0, the corres + * ponding port channel will have the highest priority level (timeout condi + * tion - Priority0). For multi-port configurations, the aging counters can + * not be used to set port priorities when external dynamic priority inputs + * (arqos) are enabled (timeout is still applicable). For single port conf + * igurations, the aging counters are only used when they timeout (become 0 + * ) to force read-write direction switching. In this case, external dynami + * c priority input, arqos (for reads only) can still be used to set the DD + * RC read priority (2 priority levels: low priority read - LPR, high prior + * ity read - HPR) on a command by command basis. Note: The two LSBs of thi + * s register field are tied internally to 2'b00. +*/ #undef DDRC_PCFGR_5_RD_PORT_PRIORITY_DEFVAL #undef DDRC_PCFGR_5_RD_PORT_PRIORITY_SHIFT #undef DDRC_PCFGR_5_RD_PORT_PRIORITY_MASK -#define DDRC_PCFGR_5_RD_PORT_PRIORITY_DEFVAL 0x00000000 -#define DDRC_PCFGR_5_RD_PORT_PRIORITY_SHIFT 0 -#define DDRC_PCFGR_5_RD_PORT_PRIORITY_MASK 0x000003FFU +#define DDRC_PCFGR_5_RD_PORT_PRIORITY_DEFVAL 0x00000000 +#define DDRC_PCFGR_5_RD_PORT_PRIORITY_SHIFT 0 +#define DDRC_PCFGR_5_RD_PORT_PRIORITY_MASK 0x000003FFU -/*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant - d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_ - imit register.*/ +/* +* If set to 1, enables the Page Match feature. If enabled, once a requesti + * ng port is granted, the port is continued to be granted if the following + * immediate commands are to the same memory page (same bank and same row) + * . See also related PCCFG.pagematch_limit register. +*/ #undef DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_DEFVAL #undef DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_SHIFT #undef DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_MASK -#define DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_DEFVAL 0x00004000 -#define DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_SHIFT 14 -#define DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_MASK 0x00004000U +#define DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_SHIFT 14 +#define DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_MASK 0x00004000U -/*If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por - becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register - Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is - not associated with any particular command).*/ +/* +* If set to 1, enables the AXI urgent sideband signal (awurgent). When ena + * bled and awurgent is asserted by the master, that port becomes the highe + * st priority and co_gs_go2critical_wr signal to DDRC is asserted if enabl + * ed in PCCFG.go2critical_en register. Note that awurgent signal can be as + * serted anytime and as long as required which is independent of address h + * andshaking (it is not associated with any particular command). +*/ #undef DDRC_PCFGW_5_WR_PORT_URGENT_EN_DEFVAL #undef DDRC_PCFGW_5_WR_PORT_URGENT_EN_SHIFT #undef DDRC_PCFGW_5_WR_PORT_URGENT_EN_MASK -#define DDRC_PCFGW_5_WR_PORT_URGENT_EN_DEFVAL 0x00004000 -#define DDRC_PCFGW_5_WR_PORT_URGENT_EN_SHIFT 13 -#define DDRC_PCFGW_5_WR_PORT_URGENT_EN_MASK 0x00002000U +#define DDRC_PCFGW_5_WR_PORT_URGENT_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_5_WR_PORT_URGENT_EN_SHIFT 13 +#define DDRC_PCFGW_5_WR_PORT_URGENT_EN_MASK 0x00002000U -/*If set to 1, enables aging function for the write channel of the port.*/ +/* +* If set to 1, enables aging function for the write channel of the port. +*/ #undef DDRC_PCFGW_5_WR_PORT_AGING_EN_DEFVAL #undef DDRC_PCFGW_5_WR_PORT_AGING_EN_SHIFT #undef DDRC_PCFGW_5_WR_PORT_AGING_EN_MASK -#define DDRC_PCFGW_5_WR_PORT_AGING_EN_DEFVAL 0x00004000 -#define DDRC_PCFGW_5_WR_PORT_AGING_EN_SHIFT 12 -#define DDRC_PCFGW_5_WR_PORT_AGING_EN_MASK 0x00001000U +#define DDRC_PCFGW_5_WR_PORT_AGING_EN_DEFVAL 0x00004000 +#define DDRC_PCFGW_5_WR_PORT_AGING_EN_SHIFT 12 +#define DDRC_PCFGW_5_WR_PORT_AGING_EN_MASK 0x00001000U -/*Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each - rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. - The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port - s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0 - the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno - be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For - ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch - ng. Note: The two LSBs of this register field are tied internally to 2'b00.*/ +/* +* Determines the initial load value of write aging counters. These counter + * s will be parallel loaded after reset, or after each grant to the corres + * ponding port. The aging counters down-count every clock cycle where the + * port is requesting but not granted. The higher significant 5-bits of the + * write aging counter sets the initial priority of the write channel of a + * given port. Port's priority will increase as the higher significant 5-b + * its of the counter starts to decrease. When the aging counter becomes 0, + * the corresponding port channel will have the highest priority level. Fo + * r multi-port configurations, the aging counters cannot be used to set po + * rt priorities when external dynamic priority inputs (awqos) are enabled + * (timeout is still applicable). For single port configurations, the aging + * counters are only used when they timeout (become 0) to force read-write + * direction switching. Note: The two LSBs of this register field are tied + * internally to 2'b00. +*/ #undef DDRC_PCFGW_5_WR_PORT_PRIORITY_DEFVAL #undef DDRC_PCFGW_5_WR_PORT_PRIORITY_SHIFT #undef DDRC_PCFGW_5_WR_PORT_PRIORITY_MASK -#define DDRC_PCFGW_5_WR_PORT_PRIORITY_DEFVAL 0x00004000 -#define DDRC_PCFGW_5_WR_PORT_PRIORITY_SHIFT 0 -#define DDRC_PCFGW_5_WR_PORT_PRIORITY_MASK 0x000003FFU +#define DDRC_PCFGW_5_WR_PORT_PRIORITY_DEFVAL 0x00004000 +#define DDRC_PCFGW_5_WR_PORT_PRIORITY_SHIFT 0 +#define DDRC_PCFGW_5_WR_PORT_PRIORITY_MASK 0x000003FFU -/*Enables port n.*/ +/* +* Enables port n. +*/ #undef DDRC_PCTRL_5_PORT_EN_DEFVAL #undef DDRC_PCTRL_5_PORT_EN_SHIFT #undef DDRC_PCTRL_5_PORT_EN_MASK -#define DDRC_PCTRL_5_PORT_EN_DEFVAL -#define DDRC_PCTRL_5_PORT_EN_SHIFT 0 -#define DDRC_PCTRL_5_PORT_EN_MASK 0x00000001U +#define DDRC_PCTRL_5_PORT_EN_DEFVAL +#define DDRC_PCTRL_5_PORT_EN_SHIFT 0 +#define DDRC_PCTRL_5_PORT_EN_MASK 0x00000001U -/*This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf - gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is - disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/ +/* +* This bitfield indicates the traffic class of region 1. Valid values are: + * 0 : LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 + * maps to the blue address queue. In this case, valid values are 0: LPR a + * nd 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tra + * ffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. +*/ #undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_DEFVAL #undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_SHIFT #undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_MASK -#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_DEFVAL 0x00000000 -#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_SHIFT 20 -#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_MASK 0x00300000U +#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_DEFVAL 0x00000000 +#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_SHIFT 20 +#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_MASK 0x00300000U -/*This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi - urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i - disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/ +/* +* This bitfield indicates the traffic class of region 0. Valid values are: + * 0: LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 + * maps to the blue address queue. In this case, valid values are: 0: LPR + * and 1: VPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and tr + * affic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR + * traffic. +*/ #undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_DEFVAL #undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_SHIFT #undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_MASK -#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_DEFVAL 0x00000000 -#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_SHIFT 16 -#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_MASK 0x00030000U +#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_DEFVAL 0x00000000 +#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_SHIFT 16 +#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_MASK 0x00030000U -/*Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d - al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio - ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc - values.*/ +/* +* Separation level1 indicating the end of region0 mapping; start of region + * 0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 + * (for single RAQ) which corresponds to arqos. Note that for PA, arqos va + * lues are used directly as port priorities, where the higher the value co + * rresponds to higher port priority. All of the map_level* registers must + * be set to distinct values. +*/ #undef DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_DEFVAL #undef DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_SHIFT #undef DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_MASK -#define DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_DEFVAL 0x00000000 -#define DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_SHIFT 0 -#define DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_MASK 0x0000000FU +#define DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_DEFVAL 0x00000000 +#define DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_SHIFT 0 +#define DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_MASK 0x0000000FU -/*Specifies the timeout value for transactions mapped to the red address queue.*/ +/* +* Specifies the timeout value for transactions mapped to the red address q + * ueue. +*/ #undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_DEFVAL #undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_SHIFT #undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_MASK -#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_DEFVAL 0x00000000 -#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_SHIFT 16 -#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_MASK 0x07FF0000U +#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_DEFVAL 0x00000000 +#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_SHIFT 16 +#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_MASK 0x07FF0000U -/*Specifies the timeout value for transactions mapped to the blue address queue.*/ +/* +* Specifies the timeout value for transactions mapped to the blue address + * queue. +*/ #undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_DEFVAL #undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_SHIFT #undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_MASK -#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_DEFVAL 0x00000000 -#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_SHIFT 0 -#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_MASK 0x000007FFU +#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_DEFVAL 0x00000000 +#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_SHIFT 0 +#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_MASK 0x000007FFU -/*This bitfield indicates the traffic class of region 1. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2 - VPW_EN = 0) and traffic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW traffic.*/ +/* +* This bitfield indicates the traffic class of region 1. Valid values are: + * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + * affic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW + * traffic. +*/ #undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_DEFVAL #undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_SHIFT #undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_MASK -#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_DEFVAL 0x00000000 -#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_SHIFT 20 -#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_MASK 0x00300000U +#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_DEFVAL 0x00000000 +#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_SHIFT 20 +#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_MASK 0x00300000U -/*This bitfield indicates the traffic class of region 0. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2 - VPW_EN = 0) and traffic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW traffic.*/ +/* +* This bitfield indicates the traffic class of region 0. Valid values are: + * 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and tr + * affic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW + * traffic. +*/ #undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_DEFVAL #undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_SHIFT #undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_MASK -#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_DEFVAL 0x00000000 -#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_SHIFT 16 -#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_MASK 0x00030000U +#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_DEFVAL 0x00000000 +#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_SHIFT 16 +#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_MASK 0x00030000U -/*Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 14 which c - rresponds to awqos. Note that for PA, awqos values are used directly as port priorities, where the higher the value correspon - s to higher port priority.*/ +/* +* Separation level indicating the end of region0 mapping; start of region0 + * is 0. Possible values for level1 are 0 to 14 which corresponds to awqos + * . Note that for PA, awqos values are used directly as port priorities, w + * here the higher the value corresponds to higher port priority. +*/ #undef DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_DEFVAL #undef DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_SHIFT #undef DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_MASK -#define DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_DEFVAL 0x00000000 -#define DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_SHIFT 0 -#define DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_MASK 0x0000000FU +#define DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_DEFVAL 0x00000000 +#define DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_SHIFT 0 +#define DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_MASK 0x0000000FU -/*Specifies the timeout value for write transactions.*/ +/* +* Specifies the timeout value for write transactions. +*/ #undef DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_DEFVAL #undef DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_SHIFT #undef DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_MASK -#define DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_DEFVAL -#define DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_SHIFT 0 -#define DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_MASK 0x000007FFU +#define DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_DEFVAL +#define DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_SHIFT 0 +#define DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_MASK 0x000007FFU -/*Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x] and araddr[UMCTL2_A_ADDRW-1:x] where x is determine - by the minimum block size parameter UMCTL2_SARMINSIZE: (x=log2(block size)).*/ +/* +* Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x + * ] and araddr[UMCTL2_A_ADDRW-1:x] where x is determined by the minimum bl + * ock size parameter UMCTL2_SARMINSIZE: (x=log2(block size)). +*/ #undef DDRC_SARBASE0_BASE_ADDR_DEFVAL #undef DDRC_SARBASE0_BASE_ADDR_SHIFT #undef DDRC_SARBASE0_BASE_ADDR_MASK -#define DDRC_SARBASE0_BASE_ADDR_DEFVAL -#define DDRC_SARBASE0_BASE_ADDR_SHIFT 0 -#define DDRC_SARBASE0_BASE_ADDR_MASK 0x000001FFU +#define DDRC_SARBASE0_BASE_ADDR_DEFVAL +#define DDRC_SARBASE0_BASE_ADDR_SHIFT 0 +#define DDRC_SARBASE0_BASE_ADDR_MASK 0x000001FFU -/*Number of blocks for address region n. This register determines the total size of the region in multiples of minimum block si - e as specified by the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded as number of blocks = nblocks + 1. - or example, if register is programmed to 0, region will have 1 block.*/ +/* +* Number of blocks for address region n. This register determines the tota + * l size of the region in multiples of minimum block size as specified by + * the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded + * as number of blocks = nblocks + 1. For example, if register is programme + * d to 0, region will have 1 block. +*/ #undef DDRC_SARSIZE0_NBLOCKS_DEFVAL #undef DDRC_SARSIZE0_NBLOCKS_SHIFT #undef DDRC_SARSIZE0_NBLOCKS_MASK -#define DDRC_SARSIZE0_NBLOCKS_DEFVAL -#define DDRC_SARSIZE0_NBLOCKS_SHIFT 0 -#define DDRC_SARSIZE0_NBLOCKS_MASK 0x000000FFU +#define DDRC_SARSIZE0_NBLOCKS_DEFVAL +#define DDRC_SARSIZE0_NBLOCKS_SHIFT 0 +#define DDRC_SARSIZE0_NBLOCKS_MASK 0x000000FFU -/*Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x] and araddr[UMCTL2_A_ADDRW-1:x] where x is determine - by the minimum block size parameter UMCTL2_SARMINSIZE: (x=log2(block size)).*/ +/* +* Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x + * ] and araddr[UMCTL2_A_ADDRW-1:x] where x is determined by the minimum bl + * ock size parameter UMCTL2_SARMINSIZE: (x=log2(block size)). +*/ #undef DDRC_SARBASE1_BASE_ADDR_DEFVAL #undef DDRC_SARBASE1_BASE_ADDR_SHIFT #undef DDRC_SARBASE1_BASE_ADDR_MASK -#define DDRC_SARBASE1_BASE_ADDR_DEFVAL -#define DDRC_SARBASE1_BASE_ADDR_SHIFT 0 -#define DDRC_SARBASE1_BASE_ADDR_MASK 0x000001FFU +#define DDRC_SARBASE1_BASE_ADDR_DEFVAL +#define DDRC_SARBASE1_BASE_ADDR_SHIFT 0 +#define DDRC_SARBASE1_BASE_ADDR_MASK 0x000001FFU -/*Number of blocks for address region n. This register determines the total size of the region in multiples of minimum block si - e as specified by the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded as number of blocks = nblocks + 1. - or example, if register is programmed to 0, region will have 1 block.*/ +/* +* Number of blocks for address region n. This register determines the tota + * l size of the region in multiples of minimum block size as specified by + * the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded + * as number of blocks = nblocks + 1. For example, if register is programme + * d to 0, region will have 1 block. +*/ #undef DDRC_SARSIZE1_NBLOCKS_DEFVAL #undef DDRC_SARSIZE1_NBLOCKS_SHIFT #undef DDRC_SARSIZE1_NBLOCKS_MASK -#define DDRC_SARSIZE1_NBLOCKS_DEFVAL -#define DDRC_SARSIZE1_NBLOCKS_SHIFT 0 -#define DDRC_SARSIZE1_NBLOCKS_MASK 0x000000FFU +#define DDRC_SARSIZE1_NBLOCKS_DEFVAL +#define DDRC_SARSIZE1_NBLOCKS_SHIFT 0 +#define DDRC_SARSIZE1_NBLOCKS_MASK 0x000000FFU -/*Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signa - s at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligne - , this timing parameter should be rounded up to the next integer value. Note that if using RDIMM, it is necessary to incremen - this parameter by RDIMM's extra cycle of latency in terms of DFI clock.*/ +/* +* Specifies the number of DFI clock cycles after an assertion or de-assert + * ion of the DFI control signals that the control signals at the PHY-DRAM + * interface reflect the assertion or de-assertion. If the DFI clock and th + * e memory clock are not phase-aligned, this timing parameter should be ro + * unded up to the next integer value. Note that if using RDIMM, it is nece + * ssary to increment this parameter by RDIMM's extra cycle of latency in t + * erms of DFI clock. +*/ #undef DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_DEFVAL #undef DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_SHIFT #undef DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_MASK -#define DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_DEFVAL 0x07020002 -#define DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_SHIFT 24 -#define DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_MASK 0x1F000000U +#define DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_DEFVAL 0x07020002 +#define DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_SHIFT 24 +#define DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_MASK 0x1F000000U -/*Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR or SDR values Selects whether value in DFITM - 0.dfi_t_rddata_en is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles R - fer to PHY specification for correct value.*/ +/* +* Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated u + * sing HDR or SDR values Selects whether value in DFITMG0.dfi_t_rddata_en + * is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles + * - 1 in terms of SDR clock cycles Refer to PHY specification for correct + * value. +*/ #undef DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_DEFVAL #undef DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_SHIFT #undef DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_MASK -#define DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_DEFVAL 0x07020002 -#define DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_SHIFT 23 -#define DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_MASK 0x00800000U +#define DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_DEFVAL 0x07020002 +#define DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_SHIFT 23 +#define DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_MASK 0x00800000U -/*Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. Refer to PHY spe - ification for correct value. This corresponds to the DFI parameter trddata_en. Note that, depending on the PHY, if using RDIM - , it may be necessary to use the value (CL + 1) in the calculation of trddata_en. This is to compensate for the extra cycle o - latency through the RDIMM. Unit: Clocks*/ +/* +* Time from the assertion of a read command on the DFI interface to the as + * sertion of the dfi_rddata_en signal. Refer to PHY specification for corr + * ect value. This corresponds to the DFI parameter trddata_en. Note that, + * depending on the PHY, if using RDIMM, it may be necessary to use the val + * ue (CL + 1) in the calculation of trddata_en. This is to compensate for + * the extra cycle of latency through the RDIMM. Unit: Clocks +*/ #undef DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_DEFVAL #undef DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_SHIFT #undef DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_MASK -#define DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_DEFVAL 0x07020002 -#define DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_SHIFT 16 -#define DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_MASK 0x003F0000U +#define DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_DEFVAL 0x07020002 +#define DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_SHIFT 16 +#define DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_MASK 0x003F0000U -/*Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using HDR or SDR values Selects whether value in DFITMG - .dfi_tphy_wrlat is in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.dfi_tphy_wrdata is in terms of SDR or - HDR clock cycles - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles Refer to PHY specification for correct val - e.*/ +/* +* Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated us + * ing HDR or SDR values Selects whether value in DFITMG0.dfi_tphy_wrlat is + * in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.df + * i_tphy_wrdata is in terms of SDR or HDR clock cycles - 0 in terms of HDR + * clock cycles - 1 in terms of SDR clock cycles Refer to PHY specificatio + * n for correct value. +*/ #undef DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_DEFVAL #undef DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_SHIFT #undef DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_MASK -#define DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_DEFVAL 0x07020002 -#define DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_SHIFT 15 -#define DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_MASK 0x00008000U +#define DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_DEFVAL 0x07020002 +#define DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_SHIFT 15 +#define DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_MASK 0x00008000U -/*Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on th - dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. N - te, max supported value is 8. Unit: Clocks*/ +/* +* Specifies the number of clock cycles between when dfi_wrdata_en is asser + * ted to when the associated write data is driven on the dfi_wrdata signal + * . This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY + * specification for correct value. Note, max supported value is 8. Unit: + * Clocks +*/ #undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_DEFVAL #undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_SHIFT #undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_MASK -#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_DEFVAL 0x07020002 -#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_SHIFT 8 -#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_MASK 0x00003F00U +#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_DEFVAL 0x07020002 +#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_SHIFT 8 +#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_MASK 0x00003F00U -/*Write latency Number of clocks from the write command to write data enable (dfi_wrdata_en). This corresponds to the DFI timin - parameter tphy_wrlat. Refer to PHY specification for correct value.Note that, depending on the PHY, if using RDIMM, it may b - necessary to use the value (CL + 1) in the calculation of tphy_wrlat. This is to compensate for the extra cycle of latency t - rough the RDIMM.*/ +/* +* Write latency Number of clocks from the write command to write data enab + * le (dfi_wrdata_en). This corresponds to the DFI timing parameter tphy_wr + * lat. Refer to PHY specification for correct value.Note that, depending o + * n the PHY, if using RDIMM, it may be necessary to use the value (CL + 1) + * in the calculation of tphy_wrlat. This is to compensate for the extra c + * ycle of latency through the RDIMM. +*/ #undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_DEFVAL #undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_SHIFT #undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_MASK -#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_DEFVAL 0x07020002 -#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_SHIFT 0 -#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_MASK 0x0000003FU +#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_DEFVAL 0x07020002 +#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_SHIFT 0 +#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_MASK 0x0000003FU -/*DDR block level reset inside of the DDR Sub System*/ +/* +* DDR block level reset inside of the DDR Sub System +*/ #undef CRF_APB_RST_DDR_SS_DDR_RESET_DEFVAL #undef CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT #undef CRF_APB_RST_DDR_SS_DDR_RESET_MASK -#define CRF_APB_RST_DDR_SS_DDR_RESET_DEFVAL 0x0000000F -#define CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT 3 -#define CRF_APB_RST_DDR_SS_DDR_RESET_MASK 0x00000008U +#define CRF_APB_RST_DDR_SS_DDR_RESET_DEFVAL 0x0000000F +#define CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT 3 +#define CRF_APB_RST_DDR_SS_DDR_RESET_MASK 0x00000008U -/*Address Copy*/ +/* +* APM block level reset inside of the DDR Sub System +*/ +#undef CRF_APB_RST_DDR_SS_APM_RESET_DEFVAL +#undef CRF_APB_RST_DDR_SS_APM_RESET_SHIFT +#undef CRF_APB_RST_DDR_SS_APM_RESET_MASK +#define CRF_APB_RST_DDR_SS_APM_RESET_DEFVAL 0x0000000F +#define CRF_APB_RST_DDR_SS_APM_RESET_SHIFT 2 +#define CRF_APB_RST_DDR_SS_APM_RESET_MASK 0x00000004U + +/* +* Address Copy +*/ #undef DDR_PHY_PGCR0_ADCP_DEFVAL #undef DDR_PHY_PGCR0_ADCP_SHIFT #undef DDR_PHY_PGCR0_ADCP_MASK -#define DDR_PHY_PGCR0_ADCP_DEFVAL 0x07001E00 -#define DDR_PHY_PGCR0_ADCP_SHIFT 31 -#define DDR_PHY_PGCR0_ADCP_MASK 0x80000000U +#define DDR_PHY_PGCR0_ADCP_DEFVAL 0x07001E00 +#define DDR_PHY_PGCR0_ADCP_SHIFT 31 +#define DDR_PHY_PGCR0_ADCP_MASK 0x80000000U -/*Reserved. Returns zeroes on reads.*/ +/* +* Reserved. Returns zeroes on reads. +*/ #undef DDR_PHY_PGCR0_RESERVED_30_27_DEFVAL #undef DDR_PHY_PGCR0_RESERVED_30_27_SHIFT #undef DDR_PHY_PGCR0_RESERVED_30_27_MASK -#define DDR_PHY_PGCR0_RESERVED_30_27_DEFVAL 0x07001E00 -#define DDR_PHY_PGCR0_RESERVED_30_27_SHIFT 27 -#define DDR_PHY_PGCR0_RESERVED_30_27_MASK 0x78000000U +#define DDR_PHY_PGCR0_RESERVED_30_27_DEFVAL 0x07001E00 +#define DDR_PHY_PGCR0_RESERVED_30_27_SHIFT 27 +#define DDR_PHY_PGCR0_RESERVED_30_27_MASK 0x78000000U -/*PHY FIFO Reset*/ +/* +* PHY FIFO Reset +*/ #undef DDR_PHY_PGCR0_PHYFRST_DEFVAL #undef DDR_PHY_PGCR0_PHYFRST_SHIFT #undef DDR_PHY_PGCR0_PHYFRST_MASK -#define DDR_PHY_PGCR0_PHYFRST_DEFVAL 0x07001E00 -#define DDR_PHY_PGCR0_PHYFRST_SHIFT 26 -#define DDR_PHY_PGCR0_PHYFRST_MASK 0x04000000U +#define DDR_PHY_PGCR0_PHYFRST_DEFVAL 0x07001E00 +#define DDR_PHY_PGCR0_PHYFRST_SHIFT 26 +#define DDR_PHY_PGCR0_PHYFRST_MASK 0x04000000U -/*Oscillator Mode Address/Command Delay Line Select*/ +/* +* Oscillator Mode Address/Command Delay Line Select +*/ #undef DDR_PHY_PGCR0_OSCACDL_DEFVAL #undef DDR_PHY_PGCR0_OSCACDL_SHIFT #undef DDR_PHY_PGCR0_OSCACDL_MASK -#define DDR_PHY_PGCR0_OSCACDL_DEFVAL 0x07001E00 -#define DDR_PHY_PGCR0_OSCACDL_SHIFT 24 -#define DDR_PHY_PGCR0_OSCACDL_MASK 0x03000000U +#define DDR_PHY_PGCR0_OSCACDL_DEFVAL 0x07001E00 +#define DDR_PHY_PGCR0_OSCACDL_SHIFT 24 +#define DDR_PHY_PGCR0_OSCACDL_MASK 0x03000000U -/*Reserved. Returns zeroes on reads.*/ +/* +* Reserved. Returns zeroes on reads. +*/ #undef DDR_PHY_PGCR0_RESERVED_23_19_DEFVAL #undef DDR_PHY_PGCR0_RESERVED_23_19_SHIFT #undef DDR_PHY_PGCR0_RESERVED_23_19_MASK -#define DDR_PHY_PGCR0_RESERVED_23_19_DEFVAL 0x07001E00 -#define DDR_PHY_PGCR0_RESERVED_23_19_SHIFT 19 -#define DDR_PHY_PGCR0_RESERVED_23_19_MASK 0x00F80000U +#define DDR_PHY_PGCR0_RESERVED_23_19_DEFVAL 0x07001E00 +#define DDR_PHY_PGCR0_RESERVED_23_19_SHIFT 19 +#define DDR_PHY_PGCR0_RESERVED_23_19_MASK 0x00F80000U -/*Digital Test Output Select*/ +/* +* Digital Test Output Select +*/ #undef DDR_PHY_PGCR0_DTOSEL_DEFVAL #undef DDR_PHY_PGCR0_DTOSEL_SHIFT #undef DDR_PHY_PGCR0_DTOSEL_MASK -#define DDR_PHY_PGCR0_DTOSEL_DEFVAL 0x07001E00 -#define DDR_PHY_PGCR0_DTOSEL_SHIFT 14 -#define DDR_PHY_PGCR0_DTOSEL_MASK 0x0007C000U +#define DDR_PHY_PGCR0_DTOSEL_DEFVAL 0x07001E00 +#define DDR_PHY_PGCR0_DTOSEL_SHIFT 14 +#define DDR_PHY_PGCR0_DTOSEL_MASK 0x0007C000U -/*Reserved. Returns zeroes on reads.*/ +/* +* Reserved. Returns zeroes on reads. +*/ #undef DDR_PHY_PGCR0_RESERVED_13_DEFVAL #undef DDR_PHY_PGCR0_RESERVED_13_SHIFT #undef DDR_PHY_PGCR0_RESERVED_13_MASK -#define DDR_PHY_PGCR0_RESERVED_13_DEFVAL 0x07001E00 -#define DDR_PHY_PGCR0_RESERVED_13_SHIFT 13 -#define DDR_PHY_PGCR0_RESERVED_13_MASK 0x00002000U +#define DDR_PHY_PGCR0_RESERVED_13_DEFVAL 0x07001E00 +#define DDR_PHY_PGCR0_RESERVED_13_SHIFT 13 +#define DDR_PHY_PGCR0_RESERVED_13_MASK 0x00002000U -/*Oscillator Mode Division*/ +/* +* Oscillator Mode Division +*/ #undef DDR_PHY_PGCR0_OSCDIV_DEFVAL #undef DDR_PHY_PGCR0_OSCDIV_SHIFT #undef DDR_PHY_PGCR0_OSCDIV_MASK -#define DDR_PHY_PGCR0_OSCDIV_DEFVAL 0x07001E00 -#define DDR_PHY_PGCR0_OSCDIV_SHIFT 9 -#define DDR_PHY_PGCR0_OSCDIV_MASK 0x00001E00U +#define DDR_PHY_PGCR0_OSCDIV_DEFVAL 0x07001E00 +#define DDR_PHY_PGCR0_OSCDIV_SHIFT 9 +#define DDR_PHY_PGCR0_OSCDIV_MASK 0x00001E00U -/*Oscillator Enable*/ +/* +* Oscillator Enable +*/ #undef DDR_PHY_PGCR0_OSCEN_DEFVAL #undef DDR_PHY_PGCR0_OSCEN_SHIFT #undef DDR_PHY_PGCR0_OSCEN_MASK -#define DDR_PHY_PGCR0_OSCEN_DEFVAL 0x07001E00 -#define DDR_PHY_PGCR0_OSCEN_SHIFT 8 -#define DDR_PHY_PGCR0_OSCEN_MASK 0x00000100U +#define DDR_PHY_PGCR0_OSCEN_DEFVAL 0x07001E00 +#define DDR_PHY_PGCR0_OSCEN_SHIFT 8 +#define DDR_PHY_PGCR0_OSCEN_MASK 0x00000100U -/*Reserved. Returns zeroes on reads.*/ +/* +* Reserved. Returns zeroes on reads. +*/ #undef DDR_PHY_PGCR0_RESERVED_7_0_DEFVAL #undef DDR_PHY_PGCR0_RESERVED_7_0_SHIFT #undef DDR_PHY_PGCR0_RESERVED_7_0_MASK -#define DDR_PHY_PGCR0_RESERVED_7_0_DEFVAL 0x07001E00 -#define DDR_PHY_PGCR0_RESERVED_7_0_SHIFT 0 -#define DDR_PHY_PGCR0_RESERVED_7_0_MASK 0x000000FFU +#define DDR_PHY_PGCR0_RESERVED_7_0_DEFVAL 0x07001E00 +#define DDR_PHY_PGCR0_RESERVED_7_0_SHIFT 0 +#define DDR_PHY_PGCR0_RESERVED_7_0_MASK 0x000000FFU -/*Clear Training Status Registers*/ +/* +* Clear Training Status Registers +*/ #undef DDR_PHY_PGCR2_CLRTSTAT_DEFVAL #undef DDR_PHY_PGCR2_CLRTSTAT_SHIFT #undef DDR_PHY_PGCR2_CLRTSTAT_MASK -#define DDR_PHY_PGCR2_CLRTSTAT_DEFVAL 0x00F12480 -#define DDR_PHY_PGCR2_CLRTSTAT_SHIFT 31 -#define DDR_PHY_PGCR2_CLRTSTAT_MASK 0x80000000U +#define DDR_PHY_PGCR2_CLRTSTAT_DEFVAL 0x00F12480 +#define DDR_PHY_PGCR2_CLRTSTAT_SHIFT 31 +#define DDR_PHY_PGCR2_CLRTSTAT_MASK 0x80000000U -/*Clear Impedance Calibration*/ +/* +* Clear Impedance Calibration +*/ #undef DDR_PHY_PGCR2_CLRZCAL_DEFVAL #undef DDR_PHY_PGCR2_CLRZCAL_SHIFT #undef DDR_PHY_PGCR2_CLRZCAL_MASK -#define DDR_PHY_PGCR2_CLRZCAL_DEFVAL 0x00F12480 -#define DDR_PHY_PGCR2_CLRZCAL_SHIFT 30 -#define DDR_PHY_PGCR2_CLRZCAL_MASK 0x40000000U +#define DDR_PHY_PGCR2_CLRZCAL_DEFVAL 0x00F12480 +#define DDR_PHY_PGCR2_CLRZCAL_SHIFT 30 +#define DDR_PHY_PGCR2_CLRZCAL_MASK 0x40000000U -/*Clear Parity Error*/ +/* +* Clear Parity Error +*/ #undef DDR_PHY_PGCR2_CLRPERR_DEFVAL #undef DDR_PHY_PGCR2_CLRPERR_SHIFT #undef DDR_PHY_PGCR2_CLRPERR_MASK -#define DDR_PHY_PGCR2_CLRPERR_DEFVAL 0x00F12480 -#define DDR_PHY_PGCR2_CLRPERR_SHIFT 29 -#define DDR_PHY_PGCR2_CLRPERR_MASK 0x20000000U +#define DDR_PHY_PGCR2_CLRPERR_DEFVAL 0x00F12480 +#define DDR_PHY_PGCR2_CLRPERR_SHIFT 29 +#define DDR_PHY_PGCR2_CLRPERR_MASK 0x20000000U -/*Initialization Complete Pin Configuration*/ +/* +* Initialization Complete Pin Configuration +*/ #undef DDR_PHY_PGCR2_ICPC_DEFVAL #undef DDR_PHY_PGCR2_ICPC_SHIFT #undef DDR_PHY_PGCR2_ICPC_MASK -#define DDR_PHY_PGCR2_ICPC_DEFVAL 0x00F12480 -#define DDR_PHY_PGCR2_ICPC_SHIFT 28 -#define DDR_PHY_PGCR2_ICPC_MASK 0x10000000U +#define DDR_PHY_PGCR2_ICPC_DEFVAL 0x00F12480 +#define DDR_PHY_PGCR2_ICPC_SHIFT 28 +#define DDR_PHY_PGCR2_ICPC_MASK 0x10000000U -/*Data Training PUB Mode Exit Timer*/ +/* +* Data Training PUB Mode Exit Timer +*/ #undef DDR_PHY_PGCR2_DTPMXTMR_DEFVAL #undef DDR_PHY_PGCR2_DTPMXTMR_SHIFT #undef DDR_PHY_PGCR2_DTPMXTMR_MASK -#define DDR_PHY_PGCR2_DTPMXTMR_DEFVAL 0x00F12480 -#define DDR_PHY_PGCR2_DTPMXTMR_SHIFT 20 -#define DDR_PHY_PGCR2_DTPMXTMR_MASK 0x0FF00000U +#define DDR_PHY_PGCR2_DTPMXTMR_DEFVAL 0x00F12480 +#define DDR_PHY_PGCR2_DTPMXTMR_SHIFT 20 +#define DDR_PHY_PGCR2_DTPMXTMR_MASK 0x0FF00000U -/*Initialization Bypass*/ +/* +* Initialization Bypass +*/ #undef DDR_PHY_PGCR2_INITFSMBYP_DEFVAL #undef DDR_PHY_PGCR2_INITFSMBYP_SHIFT #undef DDR_PHY_PGCR2_INITFSMBYP_MASK -#define DDR_PHY_PGCR2_INITFSMBYP_DEFVAL 0x00F12480 -#define DDR_PHY_PGCR2_INITFSMBYP_SHIFT 19 -#define DDR_PHY_PGCR2_INITFSMBYP_MASK 0x00080000U +#define DDR_PHY_PGCR2_INITFSMBYP_DEFVAL 0x00F12480 +#define DDR_PHY_PGCR2_INITFSMBYP_SHIFT 19 +#define DDR_PHY_PGCR2_INITFSMBYP_MASK 0x00080000U -/*PLL FSM Bypass*/ +/* +* PLL FSM Bypass +*/ #undef DDR_PHY_PGCR2_PLLFSMBYP_DEFVAL #undef DDR_PHY_PGCR2_PLLFSMBYP_SHIFT #undef DDR_PHY_PGCR2_PLLFSMBYP_MASK -#define DDR_PHY_PGCR2_PLLFSMBYP_DEFVAL 0x00F12480 -#define DDR_PHY_PGCR2_PLLFSMBYP_SHIFT 18 -#define DDR_PHY_PGCR2_PLLFSMBYP_MASK 0x00040000U +#define DDR_PHY_PGCR2_PLLFSMBYP_DEFVAL 0x00F12480 +#define DDR_PHY_PGCR2_PLLFSMBYP_SHIFT 18 +#define DDR_PHY_PGCR2_PLLFSMBYP_MASK 0x00040000U -/*Refresh Period*/ +/* +* Refresh Period +*/ #undef DDR_PHY_PGCR2_TREFPRD_DEFVAL #undef DDR_PHY_PGCR2_TREFPRD_SHIFT #undef DDR_PHY_PGCR2_TREFPRD_MASK -#define DDR_PHY_PGCR2_TREFPRD_DEFVAL 0x00F12480 -#define DDR_PHY_PGCR2_TREFPRD_SHIFT 0 -#define DDR_PHY_PGCR2_TREFPRD_MASK 0x0003FFFFU +#define DDR_PHY_PGCR2_TREFPRD_DEFVAL 0x00F12480 +#define DDR_PHY_PGCR2_TREFPRD_SHIFT 0 +#define DDR_PHY_PGCR2_TREFPRD_MASK 0x0003FFFFU -/*CKN Enable*/ +/* +* CKN Enable +*/ #undef DDR_PHY_PGCR3_CKNEN_DEFVAL #undef DDR_PHY_PGCR3_CKNEN_SHIFT #undef DDR_PHY_PGCR3_CKNEN_MASK -#define DDR_PHY_PGCR3_CKNEN_DEFVAL 0x55AA0080 -#define DDR_PHY_PGCR3_CKNEN_SHIFT 24 -#define DDR_PHY_PGCR3_CKNEN_MASK 0xFF000000U +#define DDR_PHY_PGCR3_CKNEN_DEFVAL 0x55AA0080 +#define DDR_PHY_PGCR3_CKNEN_SHIFT 24 +#define DDR_PHY_PGCR3_CKNEN_MASK 0xFF000000U -/*CK Enable*/ +/* +* CK Enable +*/ #undef DDR_PHY_PGCR3_CKEN_DEFVAL #undef DDR_PHY_PGCR3_CKEN_SHIFT #undef DDR_PHY_PGCR3_CKEN_MASK -#define DDR_PHY_PGCR3_CKEN_DEFVAL 0x55AA0080 -#define DDR_PHY_PGCR3_CKEN_SHIFT 16 -#define DDR_PHY_PGCR3_CKEN_MASK 0x00FF0000U +#define DDR_PHY_PGCR3_CKEN_DEFVAL 0x55AA0080 +#define DDR_PHY_PGCR3_CKEN_SHIFT 16 +#define DDR_PHY_PGCR3_CKEN_MASK 0x00FF0000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_PGCR3_RESERVED_15_DEFVAL #undef DDR_PHY_PGCR3_RESERVED_15_SHIFT #undef DDR_PHY_PGCR3_RESERVED_15_MASK -#define DDR_PHY_PGCR3_RESERVED_15_DEFVAL 0x55AA0080 -#define DDR_PHY_PGCR3_RESERVED_15_SHIFT 15 -#define DDR_PHY_PGCR3_RESERVED_15_MASK 0x00008000U +#define DDR_PHY_PGCR3_RESERVED_15_DEFVAL 0x55AA0080 +#define DDR_PHY_PGCR3_RESERVED_15_SHIFT 15 +#define DDR_PHY_PGCR3_RESERVED_15_MASK 0x00008000U -/*Enable Clock Gating for AC [0] ctl_rd_clk*/ +/* +* Enable Clock Gating for AC [0] ctl_rd_clk +*/ #undef DDR_PHY_PGCR3_GATEACRDCLK_DEFVAL #undef DDR_PHY_PGCR3_GATEACRDCLK_SHIFT #undef DDR_PHY_PGCR3_GATEACRDCLK_MASK -#define DDR_PHY_PGCR3_GATEACRDCLK_DEFVAL 0x55AA0080 -#define DDR_PHY_PGCR3_GATEACRDCLK_SHIFT 13 -#define DDR_PHY_PGCR3_GATEACRDCLK_MASK 0x00006000U +#define DDR_PHY_PGCR3_GATEACRDCLK_DEFVAL 0x55AA0080 +#define DDR_PHY_PGCR3_GATEACRDCLK_SHIFT 13 +#define DDR_PHY_PGCR3_GATEACRDCLK_MASK 0x00006000U -/*Enable Clock Gating for AC [0] ddr_clk*/ +/* +* Enable Clock Gating for AC [0] ddr_clk +*/ #undef DDR_PHY_PGCR3_GATEACDDRCLK_DEFVAL #undef DDR_PHY_PGCR3_GATEACDDRCLK_SHIFT #undef DDR_PHY_PGCR3_GATEACDDRCLK_MASK -#define DDR_PHY_PGCR3_GATEACDDRCLK_DEFVAL 0x55AA0080 -#define DDR_PHY_PGCR3_GATEACDDRCLK_SHIFT 11 -#define DDR_PHY_PGCR3_GATEACDDRCLK_MASK 0x00001800U +#define DDR_PHY_PGCR3_GATEACDDRCLK_DEFVAL 0x55AA0080 +#define DDR_PHY_PGCR3_GATEACDDRCLK_SHIFT 11 +#define DDR_PHY_PGCR3_GATEACDDRCLK_MASK 0x00001800U -/*Enable Clock Gating for AC [0] ctl_clk*/ +/* +* Enable Clock Gating for AC [0] ctl_clk +*/ #undef DDR_PHY_PGCR3_GATEACCTLCLK_DEFVAL #undef DDR_PHY_PGCR3_GATEACCTLCLK_SHIFT #undef DDR_PHY_PGCR3_GATEACCTLCLK_MASK -#define DDR_PHY_PGCR3_GATEACCTLCLK_DEFVAL 0x55AA0080 -#define DDR_PHY_PGCR3_GATEACCTLCLK_SHIFT 9 -#define DDR_PHY_PGCR3_GATEACCTLCLK_MASK 0x00000600U +#define DDR_PHY_PGCR3_GATEACCTLCLK_DEFVAL 0x55AA0080 +#define DDR_PHY_PGCR3_GATEACCTLCLK_SHIFT 9 +#define DDR_PHY_PGCR3_GATEACCTLCLK_MASK 0x00000600U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_PGCR3_RESERVED_8_DEFVAL #undef DDR_PHY_PGCR3_RESERVED_8_SHIFT #undef DDR_PHY_PGCR3_RESERVED_8_MASK -#define DDR_PHY_PGCR3_RESERVED_8_DEFVAL 0x55AA0080 -#define DDR_PHY_PGCR3_RESERVED_8_SHIFT 8 -#define DDR_PHY_PGCR3_RESERVED_8_MASK 0x00000100U +#define DDR_PHY_PGCR3_RESERVED_8_DEFVAL 0x55AA0080 +#define DDR_PHY_PGCR3_RESERVED_8_SHIFT 8 +#define DDR_PHY_PGCR3_RESERVED_8_MASK 0x00000100U -/*Controls DDL Bypass Modes*/ +/* +* Controls DDL Bypass Modes +*/ #undef DDR_PHY_PGCR3_DDLBYPMODE_DEFVAL #undef DDR_PHY_PGCR3_DDLBYPMODE_SHIFT #undef DDR_PHY_PGCR3_DDLBYPMODE_MASK -#define DDR_PHY_PGCR3_DDLBYPMODE_DEFVAL 0x55AA0080 -#define DDR_PHY_PGCR3_DDLBYPMODE_SHIFT 6 -#define DDR_PHY_PGCR3_DDLBYPMODE_MASK 0x000000C0U +#define DDR_PHY_PGCR3_DDLBYPMODE_DEFVAL 0x55AA0080 +#define DDR_PHY_PGCR3_DDLBYPMODE_SHIFT 6 +#define DDR_PHY_PGCR3_DDLBYPMODE_MASK 0x000000C0U -/*IO Loop-Back Select*/ +/* +* IO Loop-Back Select +*/ #undef DDR_PHY_PGCR3_IOLB_DEFVAL #undef DDR_PHY_PGCR3_IOLB_SHIFT #undef DDR_PHY_PGCR3_IOLB_MASK -#define DDR_PHY_PGCR3_IOLB_DEFVAL 0x55AA0080 -#define DDR_PHY_PGCR3_IOLB_SHIFT 5 -#define DDR_PHY_PGCR3_IOLB_MASK 0x00000020U +#define DDR_PHY_PGCR3_IOLB_DEFVAL 0x55AA0080 +#define DDR_PHY_PGCR3_IOLB_SHIFT 5 +#define DDR_PHY_PGCR3_IOLB_MASK 0x00000020U -/*AC Receive FIFO Read Mode*/ +/* +* AC Receive FIFO Read Mode +*/ #undef DDR_PHY_PGCR3_RDMODE_DEFVAL #undef DDR_PHY_PGCR3_RDMODE_SHIFT #undef DDR_PHY_PGCR3_RDMODE_MASK -#define DDR_PHY_PGCR3_RDMODE_DEFVAL 0x55AA0080 -#define DDR_PHY_PGCR3_RDMODE_SHIFT 3 -#define DDR_PHY_PGCR3_RDMODE_MASK 0x00000018U +#define DDR_PHY_PGCR3_RDMODE_DEFVAL 0x55AA0080 +#define DDR_PHY_PGCR3_RDMODE_SHIFT 3 +#define DDR_PHY_PGCR3_RDMODE_MASK 0x00000018U -/*Read FIFO Reset Disable*/ +/* +* Read FIFO Reset Disable +*/ #undef DDR_PHY_PGCR3_DISRST_DEFVAL #undef DDR_PHY_PGCR3_DISRST_SHIFT #undef DDR_PHY_PGCR3_DISRST_MASK -#define DDR_PHY_PGCR3_DISRST_DEFVAL 0x55AA0080 -#define DDR_PHY_PGCR3_DISRST_SHIFT 2 -#define DDR_PHY_PGCR3_DISRST_MASK 0x00000004U +#define DDR_PHY_PGCR3_DISRST_DEFVAL 0x55AA0080 +#define DDR_PHY_PGCR3_DISRST_SHIFT 2 +#define DDR_PHY_PGCR3_DISRST_MASK 0x00000004U -/*Clock Level when Clock Gating*/ +/* +* Clock Level when Clock Gating +*/ #undef DDR_PHY_PGCR3_CLKLEVEL_DEFVAL #undef DDR_PHY_PGCR3_CLKLEVEL_SHIFT #undef DDR_PHY_PGCR3_CLKLEVEL_MASK -#define DDR_PHY_PGCR3_CLKLEVEL_DEFVAL 0x55AA0080 -#define DDR_PHY_PGCR3_CLKLEVEL_SHIFT 0 -#define DDR_PHY_PGCR3_CLKLEVEL_MASK 0x00000003U +#define DDR_PHY_PGCR3_CLKLEVEL_DEFVAL 0x55AA0080 +#define DDR_PHY_PGCR3_CLKLEVEL_SHIFT 0 +#define DDR_PHY_PGCR3_CLKLEVEL_MASK 0x00000003U -/*Frequency B Ratio Term*/ +/* +* Frequency B Ratio Term +*/ #undef DDR_PHY_PGCR5_FRQBT_DEFVAL #undef DDR_PHY_PGCR5_FRQBT_SHIFT #undef DDR_PHY_PGCR5_FRQBT_MASK -#define DDR_PHY_PGCR5_FRQBT_DEFVAL 0x01010000 -#define DDR_PHY_PGCR5_FRQBT_SHIFT 24 -#define DDR_PHY_PGCR5_FRQBT_MASK 0xFF000000U +#define DDR_PHY_PGCR5_FRQBT_DEFVAL 0x01010000 +#define DDR_PHY_PGCR5_FRQBT_SHIFT 24 +#define DDR_PHY_PGCR5_FRQBT_MASK 0xFF000000U -/*Frequency A Ratio Term*/ +/* +* Frequency A Ratio Term +*/ #undef DDR_PHY_PGCR5_FRQAT_DEFVAL #undef DDR_PHY_PGCR5_FRQAT_SHIFT #undef DDR_PHY_PGCR5_FRQAT_MASK -#define DDR_PHY_PGCR5_FRQAT_DEFVAL 0x01010000 -#define DDR_PHY_PGCR5_FRQAT_SHIFT 16 -#define DDR_PHY_PGCR5_FRQAT_MASK 0x00FF0000U +#define DDR_PHY_PGCR5_FRQAT_DEFVAL 0x01010000 +#define DDR_PHY_PGCR5_FRQAT_SHIFT 16 +#define DDR_PHY_PGCR5_FRQAT_MASK 0x00FF0000U -/*DFI Disconnect Time Period*/ +/* +* DFI Disconnect Time Period +*/ #undef DDR_PHY_PGCR5_DISCNPERIOD_DEFVAL #undef DDR_PHY_PGCR5_DISCNPERIOD_SHIFT #undef DDR_PHY_PGCR5_DISCNPERIOD_MASK -#define DDR_PHY_PGCR5_DISCNPERIOD_DEFVAL 0x01010000 -#define DDR_PHY_PGCR5_DISCNPERIOD_SHIFT 8 -#define DDR_PHY_PGCR5_DISCNPERIOD_MASK 0x0000FF00U +#define DDR_PHY_PGCR5_DISCNPERIOD_DEFVAL 0x01010000 +#define DDR_PHY_PGCR5_DISCNPERIOD_SHIFT 8 +#define DDR_PHY_PGCR5_DISCNPERIOD_MASK 0x0000FF00U -/*Receiver bias core side control*/ +/* +* Receiver bias core side control +*/ #undef DDR_PHY_PGCR5_VREF_RBCTRL_DEFVAL #undef DDR_PHY_PGCR5_VREF_RBCTRL_SHIFT #undef DDR_PHY_PGCR5_VREF_RBCTRL_MASK -#define DDR_PHY_PGCR5_VREF_RBCTRL_DEFVAL 0x01010000 -#define DDR_PHY_PGCR5_VREF_RBCTRL_SHIFT 4 -#define DDR_PHY_PGCR5_VREF_RBCTRL_MASK 0x000000F0U +#define DDR_PHY_PGCR5_VREF_RBCTRL_DEFVAL 0x01010000 +#define DDR_PHY_PGCR5_VREF_RBCTRL_SHIFT 4 +#define DDR_PHY_PGCR5_VREF_RBCTRL_MASK 0x000000F0U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_PGCR5_RESERVED_3_DEFVAL #undef DDR_PHY_PGCR5_RESERVED_3_SHIFT #undef DDR_PHY_PGCR5_RESERVED_3_MASK -#define DDR_PHY_PGCR5_RESERVED_3_DEFVAL 0x01010000 -#define DDR_PHY_PGCR5_RESERVED_3_SHIFT 3 -#define DDR_PHY_PGCR5_RESERVED_3_MASK 0x00000008U +#define DDR_PHY_PGCR5_RESERVED_3_DEFVAL 0x01010000 +#define DDR_PHY_PGCR5_RESERVED_3_SHIFT 3 +#define DDR_PHY_PGCR5_RESERVED_3_MASK 0x00000008U -/*Internal VREF generator REFSEL ragne select*/ +/* +* Internal VREF generator REFSEL ragne select +*/ #undef DDR_PHY_PGCR5_DXREFISELRANGE_DEFVAL #undef DDR_PHY_PGCR5_DXREFISELRANGE_SHIFT #undef DDR_PHY_PGCR5_DXREFISELRANGE_MASK -#define DDR_PHY_PGCR5_DXREFISELRANGE_DEFVAL 0x01010000 -#define DDR_PHY_PGCR5_DXREFISELRANGE_SHIFT 2 -#define DDR_PHY_PGCR5_DXREFISELRANGE_MASK 0x00000004U +#define DDR_PHY_PGCR5_DXREFISELRANGE_DEFVAL 0x01010000 +#define DDR_PHY_PGCR5_DXREFISELRANGE_SHIFT 2 +#define DDR_PHY_PGCR5_DXREFISELRANGE_MASK 0x00000004U -/*DDL Page Read Write select*/ +/* +* DDL Page Read Write select +*/ #undef DDR_PHY_PGCR5_DDLPGACT_DEFVAL #undef DDR_PHY_PGCR5_DDLPGACT_SHIFT #undef DDR_PHY_PGCR5_DDLPGACT_MASK -#define DDR_PHY_PGCR5_DDLPGACT_DEFVAL 0x01010000 -#define DDR_PHY_PGCR5_DDLPGACT_SHIFT 1 -#define DDR_PHY_PGCR5_DDLPGACT_MASK 0x00000002U +#define DDR_PHY_PGCR5_DDLPGACT_DEFVAL 0x01010000 +#define DDR_PHY_PGCR5_DDLPGACT_SHIFT 1 +#define DDR_PHY_PGCR5_DDLPGACT_MASK 0x00000002U -/*DDL Page Read Write select*/ +/* +* DDL Page Read Write select +*/ #undef DDR_PHY_PGCR5_DDLPGRW_DEFVAL #undef DDR_PHY_PGCR5_DDLPGRW_SHIFT #undef DDR_PHY_PGCR5_DDLPGRW_MASK -#define DDR_PHY_PGCR5_DDLPGRW_DEFVAL 0x01010000 -#define DDR_PHY_PGCR5_DDLPGRW_SHIFT 0 -#define DDR_PHY_PGCR5_DDLPGRW_MASK 0x00000001U +#define DDR_PHY_PGCR5_DDLPGRW_DEFVAL 0x01010000 +#define DDR_PHY_PGCR5_DDLPGRW_SHIFT 0 +#define DDR_PHY_PGCR5_DDLPGRW_MASK 0x00000001U -/*PLL Power-Down Time*/ +/* +* PLL Power-Down Time +*/ #undef DDR_PHY_PTR0_TPLLPD_DEFVAL #undef DDR_PHY_PTR0_TPLLPD_SHIFT #undef DDR_PHY_PTR0_TPLLPD_MASK -#define DDR_PHY_PTR0_TPLLPD_DEFVAL 0x42C21590 -#define DDR_PHY_PTR0_TPLLPD_SHIFT 21 -#define DDR_PHY_PTR0_TPLLPD_MASK 0xFFE00000U +#define DDR_PHY_PTR0_TPLLPD_DEFVAL 0x42C21590 +#define DDR_PHY_PTR0_TPLLPD_SHIFT 21 +#define DDR_PHY_PTR0_TPLLPD_MASK 0xFFE00000U -/*PLL Gear Shift Time*/ +/* +* PLL Gear Shift Time +*/ #undef DDR_PHY_PTR0_TPLLGS_DEFVAL #undef DDR_PHY_PTR0_TPLLGS_SHIFT #undef DDR_PHY_PTR0_TPLLGS_MASK -#define DDR_PHY_PTR0_TPLLGS_DEFVAL 0x42C21590 -#define DDR_PHY_PTR0_TPLLGS_SHIFT 6 -#define DDR_PHY_PTR0_TPLLGS_MASK 0x001FFFC0U +#define DDR_PHY_PTR0_TPLLGS_DEFVAL 0x42C21590 +#define DDR_PHY_PTR0_TPLLGS_SHIFT 6 +#define DDR_PHY_PTR0_TPLLGS_MASK 0x001FFFC0U -/*PHY Reset Time*/ +/* +* PHY Reset Time +*/ #undef DDR_PHY_PTR0_TPHYRST_DEFVAL #undef DDR_PHY_PTR0_TPHYRST_SHIFT #undef DDR_PHY_PTR0_TPHYRST_MASK -#define DDR_PHY_PTR0_TPHYRST_DEFVAL 0x42C21590 -#define DDR_PHY_PTR0_TPHYRST_SHIFT 0 -#define DDR_PHY_PTR0_TPHYRST_MASK 0x0000003FU +#define DDR_PHY_PTR0_TPHYRST_DEFVAL 0x42C21590 +#define DDR_PHY_PTR0_TPHYRST_SHIFT 0 +#define DDR_PHY_PTR0_TPHYRST_MASK 0x0000003FU -/*PLL Lock Time*/ +/* +* PLL Lock Time +*/ #undef DDR_PHY_PTR1_TPLLLOCK_DEFVAL #undef DDR_PHY_PTR1_TPLLLOCK_SHIFT #undef DDR_PHY_PTR1_TPLLLOCK_MASK -#define DDR_PHY_PTR1_TPLLLOCK_DEFVAL 0xD05612C0 -#define DDR_PHY_PTR1_TPLLLOCK_SHIFT 16 -#define DDR_PHY_PTR1_TPLLLOCK_MASK 0xFFFF0000U +#define DDR_PHY_PTR1_TPLLLOCK_DEFVAL 0xD05612C0 +#define DDR_PHY_PTR1_TPLLLOCK_SHIFT 16 +#define DDR_PHY_PTR1_TPLLLOCK_MASK 0xFFFF0000U -/*Reserved. Returns zeroes on reads.*/ +/* +* Reserved. Returns zeroes on reads. +*/ #undef DDR_PHY_PTR1_RESERVED_15_13_DEFVAL #undef DDR_PHY_PTR1_RESERVED_15_13_SHIFT #undef DDR_PHY_PTR1_RESERVED_15_13_MASK -#define DDR_PHY_PTR1_RESERVED_15_13_DEFVAL 0xD05612C0 -#define DDR_PHY_PTR1_RESERVED_15_13_SHIFT 13 -#define DDR_PHY_PTR1_RESERVED_15_13_MASK 0x0000E000U +#define DDR_PHY_PTR1_RESERVED_15_13_DEFVAL 0xD05612C0 +#define DDR_PHY_PTR1_RESERVED_15_13_SHIFT 13 +#define DDR_PHY_PTR1_RESERVED_15_13_MASK 0x0000E000U -/*PLL Reset Time*/ +/* +* PLL Reset Time +*/ #undef DDR_PHY_PTR1_TPLLRST_DEFVAL #undef DDR_PHY_PTR1_TPLLRST_SHIFT #undef DDR_PHY_PTR1_TPLLRST_MASK -#define DDR_PHY_PTR1_TPLLRST_DEFVAL 0xD05612C0 -#define DDR_PHY_PTR1_TPLLRST_SHIFT 0 -#define DDR_PHY_PTR1_TPLLRST_MASK 0x00001FFFU +#define DDR_PHY_PTR1_TPLLRST_DEFVAL 0xD05612C0 +#define DDR_PHY_PTR1_TPLLRST_SHIFT 0 +#define DDR_PHY_PTR1_TPLLRST_MASK 0x00001FFFU -/*Reserved. Return zeroes on reads.*/ +/* +* PLL Bypass +*/ +#undef DDR_PHY_PLLCR0_PLLBYP_DEFVAL +#undef DDR_PHY_PLLCR0_PLLBYP_SHIFT +#undef DDR_PHY_PLLCR0_PLLBYP_MASK +#define DDR_PHY_PLLCR0_PLLBYP_DEFVAL 0x001C0000 +#define DDR_PHY_PLLCR0_PLLBYP_SHIFT 31 +#define DDR_PHY_PLLCR0_PLLBYP_MASK 0x80000000U + +/* +* PLL Reset +*/ +#undef DDR_PHY_PLLCR0_PLLRST_DEFVAL +#undef DDR_PHY_PLLCR0_PLLRST_SHIFT +#undef DDR_PHY_PLLCR0_PLLRST_MASK +#define DDR_PHY_PLLCR0_PLLRST_DEFVAL 0x001C0000 +#define DDR_PHY_PLLCR0_PLLRST_SHIFT 30 +#define DDR_PHY_PLLCR0_PLLRST_MASK 0x40000000U + +/* +* PLL Power Down +*/ +#undef DDR_PHY_PLLCR0_PLLPD_DEFVAL +#undef DDR_PHY_PLLCR0_PLLPD_SHIFT +#undef DDR_PHY_PLLCR0_PLLPD_MASK +#define DDR_PHY_PLLCR0_PLLPD_DEFVAL 0x001C0000 +#define DDR_PHY_PLLCR0_PLLPD_SHIFT 29 +#define DDR_PHY_PLLCR0_PLLPD_MASK 0x20000000U + +/* +* Reference Stop Mode +*/ +#undef DDR_PHY_PLLCR0_RSTOPM_DEFVAL +#undef DDR_PHY_PLLCR0_RSTOPM_SHIFT +#undef DDR_PHY_PLLCR0_RSTOPM_MASK +#define DDR_PHY_PLLCR0_RSTOPM_DEFVAL 0x001C0000 +#define DDR_PHY_PLLCR0_RSTOPM_SHIFT 28 +#define DDR_PHY_PLLCR0_RSTOPM_MASK 0x10000000U + +/* +* PLL Frequency Select +*/ +#undef DDR_PHY_PLLCR0_FRQSEL_DEFVAL +#undef DDR_PHY_PLLCR0_FRQSEL_SHIFT +#undef DDR_PHY_PLLCR0_FRQSEL_MASK +#define DDR_PHY_PLLCR0_FRQSEL_DEFVAL 0x001C0000 +#define DDR_PHY_PLLCR0_FRQSEL_SHIFT 24 +#define DDR_PHY_PLLCR0_FRQSEL_MASK 0x0F000000U + +/* +* Relock Mode +*/ +#undef DDR_PHY_PLLCR0_RLOCKM_DEFVAL +#undef DDR_PHY_PLLCR0_RLOCKM_SHIFT +#undef DDR_PHY_PLLCR0_RLOCKM_MASK +#define DDR_PHY_PLLCR0_RLOCKM_DEFVAL 0x001C0000 +#define DDR_PHY_PLLCR0_RLOCKM_SHIFT 23 +#define DDR_PHY_PLLCR0_RLOCKM_MASK 0x00800000U + +/* +* Charge Pump Proportional Current Control +*/ +#undef DDR_PHY_PLLCR0_CPPC_DEFVAL +#undef DDR_PHY_PLLCR0_CPPC_SHIFT +#undef DDR_PHY_PLLCR0_CPPC_MASK +#define DDR_PHY_PLLCR0_CPPC_DEFVAL 0x001C0000 +#define DDR_PHY_PLLCR0_CPPC_SHIFT 17 +#define DDR_PHY_PLLCR0_CPPC_MASK 0x007E0000U + +/* +* Charge Pump Integrating Current Control +*/ +#undef DDR_PHY_PLLCR0_CPIC_DEFVAL +#undef DDR_PHY_PLLCR0_CPIC_SHIFT +#undef DDR_PHY_PLLCR0_CPIC_MASK +#define DDR_PHY_PLLCR0_CPIC_DEFVAL 0x001C0000 +#define DDR_PHY_PLLCR0_CPIC_SHIFT 13 +#define DDR_PHY_PLLCR0_CPIC_MASK 0x0001E000U + +/* +* Gear Shift +*/ +#undef DDR_PHY_PLLCR0_GSHIFT_DEFVAL +#undef DDR_PHY_PLLCR0_GSHIFT_SHIFT +#undef DDR_PHY_PLLCR0_GSHIFT_MASK +#define DDR_PHY_PLLCR0_GSHIFT_DEFVAL 0x001C0000 +#define DDR_PHY_PLLCR0_GSHIFT_SHIFT 12 +#define DDR_PHY_PLLCR0_GSHIFT_MASK 0x00001000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_PLLCR0_RESERVED_11_9_DEFVAL +#undef DDR_PHY_PLLCR0_RESERVED_11_9_SHIFT +#undef DDR_PHY_PLLCR0_RESERVED_11_9_MASK +#define DDR_PHY_PLLCR0_RESERVED_11_9_DEFVAL 0x001C0000 +#define DDR_PHY_PLLCR0_RESERVED_11_9_SHIFT 9 +#define DDR_PHY_PLLCR0_RESERVED_11_9_MASK 0x00000E00U + +/* +* Analog Test Enable +*/ +#undef DDR_PHY_PLLCR0_ATOEN_DEFVAL +#undef DDR_PHY_PLLCR0_ATOEN_SHIFT +#undef DDR_PHY_PLLCR0_ATOEN_MASK +#define DDR_PHY_PLLCR0_ATOEN_DEFVAL 0x001C0000 +#define DDR_PHY_PLLCR0_ATOEN_SHIFT 8 +#define DDR_PHY_PLLCR0_ATOEN_MASK 0x00000100U + +/* +* Analog Test Control +*/ +#undef DDR_PHY_PLLCR0_ATC_DEFVAL +#undef DDR_PHY_PLLCR0_ATC_SHIFT +#undef DDR_PHY_PLLCR0_ATC_MASK +#define DDR_PHY_PLLCR0_ATC_DEFVAL 0x001C0000 +#define DDR_PHY_PLLCR0_ATC_SHIFT 4 +#define DDR_PHY_PLLCR0_ATC_MASK 0x000000F0U + +/* +* Digital Test Control +*/ +#undef DDR_PHY_PLLCR0_DTC_DEFVAL +#undef DDR_PHY_PLLCR0_DTC_SHIFT +#undef DDR_PHY_PLLCR0_DTC_MASK +#define DDR_PHY_PLLCR0_DTC_DEFVAL 0x001C0000 +#define DDR_PHY_PLLCR0_DTC_SHIFT 0 +#define DDR_PHY_PLLCR0_DTC_MASK 0x0000000FU + +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DSGCR_RESERVED_31_28_DEFVAL #undef DDR_PHY_DSGCR_RESERVED_31_28_SHIFT #undef DDR_PHY_DSGCR_RESERVED_31_28_MASK -#define DDR_PHY_DSGCR_RESERVED_31_28_DEFVAL 0x02A04101 -#define DDR_PHY_DSGCR_RESERVED_31_28_SHIFT 28 -#define DDR_PHY_DSGCR_RESERVED_31_28_MASK 0xF0000000U +#define DDR_PHY_DSGCR_RESERVED_31_28_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_RESERVED_31_28_SHIFT 28 +#define DDR_PHY_DSGCR_RESERVED_31_28_MASK 0xF0000000U -/*When RDBI enabled, this bit is used to select RDBI CL calculation, if it is 1b1, calculation will use RDBICL, otherwise use d - fault calculation.*/ +/* +* When RDBI enabled, this bit is used to select RDBI CL calculation, if it + * is 1b1, calculation will use RDBICL, otherwise use default calculation. +*/ #undef DDR_PHY_DSGCR_RDBICLSEL_DEFVAL #undef DDR_PHY_DSGCR_RDBICLSEL_SHIFT #undef DDR_PHY_DSGCR_RDBICLSEL_MASK -#define DDR_PHY_DSGCR_RDBICLSEL_DEFVAL 0x02A04101 -#define DDR_PHY_DSGCR_RDBICLSEL_SHIFT 27 -#define DDR_PHY_DSGCR_RDBICLSEL_MASK 0x08000000U +#define DDR_PHY_DSGCR_RDBICLSEL_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_RDBICLSEL_SHIFT 27 +#define DDR_PHY_DSGCR_RDBICLSEL_MASK 0x08000000U -/*When RDBI enabled, if RDBICLSEL is asserted, RDBI CL adjust using this value.*/ +/* +* When RDBI enabled, if RDBICLSEL is asserted, RDBI CL adjust using this v + * alue. +*/ #undef DDR_PHY_DSGCR_RDBICL_DEFVAL #undef DDR_PHY_DSGCR_RDBICL_SHIFT #undef DDR_PHY_DSGCR_RDBICL_MASK -#define DDR_PHY_DSGCR_RDBICL_DEFVAL 0x02A04101 -#define DDR_PHY_DSGCR_RDBICL_SHIFT 24 -#define DDR_PHY_DSGCR_RDBICL_MASK 0x07000000U +#define DDR_PHY_DSGCR_RDBICL_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_RDBICL_SHIFT 24 +#define DDR_PHY_DSGCR_RDBICL_MASK 0x07000000U -/*PHY Impedance Update Enable*/ +/* +* PHY Impedance Update Enable +*/ #undef DDR_PHY_DSGCR_PHYZUEN_DEFVAL #undef DDR_PHY_DSGCR_PHYZUEN_SHIFT #undef DDR_PHY_DSGCR_PHYZUEN_MASK -#define DDR_PHY_DSGCR_PHYZUEN_DEFVAL 0x02A04101 -#define DDR_PHY_DSGCR_PHYZUEN_SHIFT 23 -#define DDR_PHY_DSGCR_PHYZUEN_MASK 0x00800000U +#define DDR_PHY_DSGCR_PHYZUEN_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_PHYZUEN_SHIFT 23 +#define DDR_PHY_DSGCR_PHYZUEN_MASK 0x00800000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DSGCR_RESERVED_22_DEFVAL #undef DDR_PHY_DSGCR_RESERVED_22_SHIFT #undef DDR_PHY_DSGCR_RESERVED_22_MASK -#define DDR_PHY_DSGCR_RESERVED_22_DEFVAL 0x02A04101 -#define DDR_PHY_DSGCR_RESERVED_22_SHIFT 22 -#define DDR_PHY_DSGCR_RESERVED_22_MASK 0x00400000U +#define DDR_PHY_DSGCR_RESERVED_22_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_RESERVED_22_SHIFT 22 +#define DDR_PHY_DSGCR_RESERVED_22_MASK 0x00400000U -/*SDRAM Reset Output Enable*/ +/* +* SDRAM Reset Output Enable +*/ #undef DDR_PHY_DSGCR_RSTOE_DEFVAL #undef DDR_PHY_DSGCR_RSTOE_SHIFT #undef DDR_PHY_DSGCR_RSTOE_MASK -#define DDR_PHY_DSGCR_RSTOE_DEFVAL 0x02A04101 -#define DDR_PHY_DSGCR_RSTOE_SHIFT 21 -#define DDR_PHY_DSGCR_RSTOE_MASK 0x00200000U +#define DDR_PHY_DSGCR_RSTOE_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_RSTOE_SHIFT 21 +#define DDR_PHY_DSGCR_RSTOE_MASK 0x00200000U -/*Single Data Rate Mode*/ +/* +* Single Data Rate Mode +*/ #undef DDR_PHY_DSGCR_SDRMODE_DEFVAL #undef DDR_PHY_DSGCR_SDRMODE_SHIFT #undef DDR_PHY_DSGCR_SDRMODE_MASK -#define DDR_PHY_DSGCR_SDRMODE_DEFVAL 0x02A04101 -#define DDR_PHY_DSGCR_SDRMODE_SHIFT 19 -#define DDR_PHY_DSGCR_SDRMODE_MASK 0x00180000U +#define DDR_PHY_DSGCR_SDRMODE_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_SDRMODE_SHIFT 19 +#define DDR_PHY_DSGCR_SDRMODE_MASK 0x00180000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DSGCR_RESERVED_18_DEFVAL #undef DDR_PHY_DSGCR_RESERVED_18_SHIFT #undef DDR_PHY_DSGCR_RESERVED_18_MASK -#define DDR_PHY_DSGCR_RESERVED_18_DEFVAL 0x02A04101 -#define DDR_PHY_DSGCR_RESERVED_18_SHIFT 18 -#define DDR_PHY_DSGCR_RESERVED_18_MASK 0x00040000U +#define DDR_PHY_DSGCR_RESERVED_18_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_RESERVED_18_SHIFT 18 +#define DDR_PHY_DSGCR_RESERVED_18_MASK 0x00040000U -/*ATO Analog Test Enable*/ +/* +* ATO Analog Test Enable +*/ #undef DDR_PHY_DSGCR_ATOAE_DEFVAL #undef DDR_PHY_DSGCR_ATOAE_SHIFT #undef DDR_PHY_DSGCR_ATOAE_MASK -#define DDR_PHY_DSGCR_ATOAE_DEFVAL 0x02A04101 -#define DDR_PHY_DSGCR_ATOAE_SHIFT 17 -#define DDR_PHY_DSGCR_ATOAE_MASK 0x00020000U +#define DDR_PHY_DSGCR_ATOAE_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_ATOAE_SHIFT 17 +#define DDR_PHY_DSGCR_ATOAE_MASK 0x00020000U -/*DTO Output Enable*/ +/* +* DTO Output Enable +*/ #undef DDR_PHY_DSGCR_DTOOE_DEFVAL #undef DDR_PHY_DSGCR_DTOOE_SHIFT #undef DDR_PHY_DSGCR_DTOOE_MASK -#define DDR_PHY_DSGCR_DTOOE_DEFVAL 0x02A04101 -#define DDR_PHY_DSGCR_DTOOE_SHIFT 16 -#define DDR_PHY_DSGCR_DTOOE_MASK 0x00010000U +#define DDR_PHY_DSGCR_DTOOE_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_DTOOE_SHIFT 16 +#define DDR_PHY_DSGCR_DTOOE_MASK 0x00010000U -/*DTO I/O Mode*/ +/* +* DTO I/O Mode +*/ #undef DDR_PHY_DSGCR_DTOIOM_DEFVAL #undef DDR_PHY_DSGCR_DTOIOM_SHIFT #undef DDR_PHY_DSGCR_DTOIOM_MASK -#define DDR_PHY_DSGCR_DTOIOM_DEFVAL 0x02A04101 -#define DDR_PHY_DSGCR_DTOIOM_SHIFT 15 -#define DDR_PHY_DSGCR_DTOIOM_MASK 0x00008000U +#define DDR_PHY_DSGCR_DTOIOM_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_DTOIOM_SHIFT 15 +#define DDR_PHY_DSGCR_DTOIOM_MASK 0x00008000U -/*DTO Power Down Receiver*/ +/* +* DTO Power Down Receiver +*/ #undef DDR_PHY_DSGCR_DTOPDR_DEFVAL #undef DDR_PHY_DSGCR_DTOPDR_SHIFT #undef DDR_PHY_DSGCR_DTOPDR_MASK -#define DDR_PHY_DSGCR_DTOPDR_DEFVAL 0x02A04101 -#define DDR_PHY_DSGCR_DTOPDR_SHIFT 14 -#define DDR_PHY_DSGCR_DTOPDR_MASK 0x00004000U +#define DDR_PHY_DSGCR_DTOPDR_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_DTOPDR_SHIFT 14 +#define DDR_PHY_DSGCR_DTOPDR_MASK 0x00004000U -/*Reserved. Return zeroes on reads*/ +/* +* Reserved. Return zeroes on reads +*/ #undef DDR_PHY_DSGCR_RESERVED_13_DEFVAL #undef DDR_PHY_DSGCR_RESERVED_13_SHIFT #undef DDR_PHY_DSGCR_RESERVED_13_MASK -#define DDR_PHY_DSGCR_RESERVED_13_DEFVAL 0x02A04101 -#define DDR_PHY_DSGCR_RESERVED_13_SHIFT 13 -#define DDR_PHY_DSGCR_RESERVED_13_MASK 0x00002000U +#define DDR_PHY_DSGCR_RESERVED_13_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_RESERVED_13_SHIFT 13 +#define DDR_PHY_DSGCR_RESERVED_13_MASK 0x00002000U -/*DTO On-Die Termination*/ +/* +* DTO On-Die Termination +*/ #undef DDR_PHY_DSGCR_DTOODT_DEFVAL #undef DDR_PHY_DSGCR_DTOODT_SHIFT #undef DDR_PHY_DSGCR_DTOODT_MASK -#define DDR_PHY_DSGCR_DTOODT_DEFVAL 0x02A04101 -#define DDR_PHY_DSGCR_DTOODT_SHIFT 12 -#define DDR_PHY_DSGCR_DTOODT_MASK 0x00001000U +#define DDR_PHY_DSGCR_DTOODT_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_DTOODT_SHIFT 12 +#define DDR_PHY_DSGCR_DTOODT_MASK 0x00001000U -/*PHY Update Acknowledge Delay*/ +/* +* PHY Update Acknowledge Delay +*/ #undef DDR_PHY_DSGCR_PUAD_DEFVAL #undef DDR_PHY_DSGCR_PUAD_SHIFT #undef DDR_PHY_DSGCR_PUAD_MASK -#define DDR_PHY_DSGCR_PUAD_DEFVAL 0x02A04101 -#define DDR_PHY_DSGCR_PUAD_SHIFT 6 -#define DDR_PHY_DSGCR_PUAD_MASK 0x00000FC0U +#define DDR_PHY_DSGCR_PUAD_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_PUAD_SHIFT 6 +#define DDR_PHY_DSGCR_PUAD_MASK 0x00000FC0U -/*Controller Update Acknowledge Enable*/ +/* +* Controller Update Acknowledge Enable +*/ #undef DDR_PHY_DSGCR_CUAEN_DEFVAL #undef DDR_PHY_DSGCR_CUAEN_SHIFT #undef DDR_PHY_DSGCR_CUAEN_MASK -#define DDR_PHY_DSGCR_CUAEN_DEFVAL 0x02A04101 -#define DDR_PHY_DSGCR_CUAEN_SHIFT 5 -#define DDR_PHY_DSGCR_CUAEN_MASK 0x00000020U +#define DDR_PHY_DSGCR_CUAEN_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_CUAEN_SHIFT 5 +#define DDR_PHY_DSGCR_CUAEN_MASK 0x00000020U -/*Reserved. Return zeroes on reads*/ +/* +* Reserved. Return zeroes on reads +*/ #undef DDR_PHY_DSGCR_RESERVED_4_3_DEFVAL #undef DDR_PHY_DSGCR_RESERVED_4_3_SHIFT #undef DDR_PHY_DSGCR_RESERVED_4_3_MASK -#define DDR_PHY_DSGCR_RESERVED_4_3_DEFVAL 0x02A04101 -#define DDR_PHY_DSGCR_RESERVED_4_3_SHIFT 3 -#define DDR_PHY_DSGCR_RESERVED_4_3_MASK 0x00000018U +#define DDR_PHY_DSGCR_RESERVED_4_3_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_RESERVED_4_3_SHIFT 3 +#define DDR_PHY_DSGCR_RESERVED_4_3_MASK 0x00000018U -/*Controller Impedance Update Enable*/ +/* +* Controller Impedance Update Enable +*/ #undef DDR_PHY_DSGCR_CTLZUEN_DEFVAL #undef DDR_PHY_DSGCR_CTLZUEN_SHIFT #undef DDR_PHY_DSGCR_CTLZUEN_MASK -#define DDR_PHY_DSGCR_CTLZUEN_DEFVAL 0x02A04101 -#define DDR_PHY_DSGCR_CTLZUEN_SHIFT 2 -#define DDR_PHY_DSGCR_CTLZUEN_MASK 0x00000004U +#define DDR_PHY_DSGCR_CTLZUEN_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_CTLZUEN_SHIFT 2 +#define DDR_PHY_DSGCR_CTLZUEN_MASK 0x00000004U -/*Reserved. Return zeroes on reads*/ +/* +* Reserved. Return zeroes on reads +*/ #undef DDR_PHY_DSGCR_RESERVED_1_DEFVAL #undef DDR_PHY_DSGCR_RESERVED_1_SHIFT #undef DDR_PHY_DSGCR_RESERVED_1_MASK -#define DDR_PHY_DSGCR_RESERVED_1_DEFVAL 0x02A04101 -#define DDR_PHY_DSGCR_RESERVED_1_SHIFT 1 -#define DDR_PHY_DSGCR_RESERVED_1_MASK 0x00000002U +#define DDR_PHY_DSGCR_RESERVED_1_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_RESERVED_1_SHIFT 1 +#define DDR_PHY_DSGCR_RESERVED_1_MASK 0x00000002U -/*PHY Update Request Enable*/ +/* +* PHY Update Request Enable +*/ #undef DDR_PHY_DSGCR_PUREN_DEFVAL #undef DDR_PHY_DSGCR_PUREN_SHIFT #undef DDR_PHY_DSGCR_PUREN_MASK -#define DDR_PHY_DSGCR_PUREN_DEFVAL 0x02A04101 -#define DDR_PHY_DSGCR_PUREN_SHIFT 0 -#define DDR_PHY_DSGCR_PUREN_MASK 0x00000001U +#define DDR_PHY_DSGCR_PUREN_DEFVAL 0x02A04101 +#define DDR_PHY_DSGCR_PUREN_SHIFT 0 +#define DDR_PHY_DSGCR_PUREN_MASK 0x00000001U -/*DDR4 Gear Down Timing.*/ +/* +* General Purpose Register 0 +*/ +#undef DDR_PHY_GPR0_GPR0_DEFVAL +#undef DDR_PHY_GPR0_GPR0_SHIFT +#undef DDR_PHY_GPR0_GPR0_MASK +#define DDR_PHY_GPR0_GPR0_DEFVAL +#define DDR_PHY_GPR0_GPR0_SHIFT 0 +#define DDR_PHY_GPR0_GPR0_MASK 0xFFFFFFFFU + +/* +* DDR4 Gear Down Timing. +*/ #undef DDR_PHY_DCR_GEARDN_DEFVAL #undef DDR_PHY_DCR_GEARDN_SHIFT #undef DDR_PHY_DCR_GEARDN_MASK -#define DDR_PHY_DCR_GEARDN_DEFVAL 0x0000040D -#define DDR_PHY_DCR_GEARDN_SHIFT 31 -#define DDR_PHY_DCR_GEARDN_MASK 0x80000000U +#define DDR_PHY_DCR_GEARDN_DEFVAL 0x0000040D +#define DDR_PHY_DCR_GEARDN_SHIFT 31 +#define DDR_PHY_DCR_GEARDN_MASK 0x80000000U -/*Un-used Bank Group*/ +/* +* Un-used Bank Group +*/ #undef DDR_PHY_DCR_UBG_DEFVAL #undef DDR_PHY_DCR_UBG_SHIFT #undef DDR_PHY_DCR_UBG_MASK -#define DDR_PHY_DCR_UBG_DEFVAL 0x0000040D -#define DDR_PHY_DCR_UBG_SHIFT 30 -#define DDR_PHY_DCR_UBG_MASK 0x40000000U +#define DDR_PHY_DCR_UBG_DEFVAL 0x0000040D +#define DDR_PHY_DCR_UBG_SHIFT 30 +#define DDR_PHY_DCR_UBG_MASK 0x40000000U -/*Un-buffered DIMM Address Mirroring*/ +/* +* Un-buffered DIMM Address Mirroring +*/ #undef DDR_PHY_DCR_UDIMM_DEFVAL #undef DDR_PHY_DCR_UDIMM_SHIFT #undef DDR_PHY_DCR_UDIMM_MASK -#define DDR_PHY_DCR_UDIMM_DEFVAL 0x0000040D -#define DDR_PHY_DCR_UDIMM_SHIFT 29 -#define DDR_PHY_DCR_UDIMM_MASK 0x20000000U +#define DDR_PHY_DCR_UDIMM_DEFVAL 0x0000040D +#define DDR_PHY_DCR_UDIMM_SHIFT 29 +#define DDR_PHY_DCR_UDIMM_MASK 0x20000000U -/*DDR 2T Timing*/ +/* +* DDR 2T Timing +*/ #undef DDR_PHY_DCR_DDR2T_DEFVAL #undef DDR_PHY_DCR_DDR2T_SHIFT #undef DDR_PHY_DCR_DDR2T_MASK -#define DDR_PHY_DCR_DDR2T_DEFVAL 0x0000040D -#define DDR_PHY_DCR_DDR2T_SHIFT 28 -#define DDR_PHY_DCR_DDR2T_MASK 0x10000000U +#define DDR_PHY_DCR_DDR2T_DEFVAL 0x0000040D +#define DDR_PHY_DCR_DDR2T_SHIFT 28 +#define DDR_PHY_DCR_DDR2T_MASK 0x10000000U -/*No Simultaneous Rank Access*/ +/* +* No Simultaneous Rank Access +*/ #undef DDR_PHY_DCR_NOSRA_DEFVAL #undef DDR_PHY_DCR_NOSRA_SHIFT #undef DDR_PHY_DCR_NOSRA_MASK -#define DDR_PHY_DCR_NOSRA_DEFVAL 0x0000040D -#define DDR_PHY_DCR_NOSRA_SHIFT 27 -#define DDR_PHY_DCR_NOSRA_MASK 0x08000000U +#define DDR_PHY_DCR_NOSRA_DEFVAL 0x0000040D +#define DDR_PHY_DCR_NOSRA_SHIFT 27 +#define DDR_PHY_DCR_NOSRA_MASK 0x08000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DCR_RESERVED_26_18_DEFVAL #undef DDR_PHY_DCR_RESERVED_26_18_SHIFT #undef DDR_PHY_DCR_RESERVED_26_18_MASK -#define DDR_PHY_DCR_RESERVED_26_18_DEFVAL 0x0000040D -#define DDR_PHY_DCR_RESERVED_26_18_SHIFT 18 -#define DDR_PHY_DCR_RESERVED_26_18_MASK 0x07FC0000U +#define DDR_PHY_DCR_RESERVED_26_18_DEFVAL 0x0000040D +#define DDR_PHY_DCR_RESERVED_26_18_SHIFT 18 +#define DDR_PHY_DCR_RESERVED_26_18_MASK 0x07FC0000U -/*Byte Mask*/ +/* +* Byte Mask +*/ #undef DDR_PHY_DCR_BYTEMASK_DEFVAL #undef DDR_PHY_DCR_BYTEMASK_SHIFT #undef DDR_PHY_DCR_BYTEMASK_MASK -#define DDR_PHY_DCR_BYTEMASK_DEFVAL 0x0000040D -#define DDR_PHY_DCR_BYTEMASK_SHIFT 10 -#define DDR_PHY_DCR_BYTEMASK_MASK 0x0003FC00U +#define DDR_PHY_DCR_BYTEMASK_DEFVAL 0x0000040D +#define DDR_PHY_DCR_BYTEMASK_SHIFT 10 +#define DDR_PHY_DCR_BYTEMASK_MASK 0x0003FC00U -/*DDR Type*/ +/* +* DDR Type +*/ #undef DDR_PHY_DCR_DDRTYPE_DEFVAL #undef DDR_PHY_DCR_DDRTYPE_SHIFT #undef DDR_PHY_DCR_DDRTYPE_MASK -#define DDR_PHY_DCR_DDRTYPE_DEFVAL 0x0000040D -#define DDR_PHY_DCR_DDRTYPE_SHIFT 8 -#define DDR_PHY_DCR_DDRTYPE_MASK 0x00000300U +#define DDR_PHY_DCR_DDRTYPE_DEFVAL 0x0000040D +#define DDR_PHY_DCR_DDRTYPE_SHIFT 8 +#define DDR_PHY_DCR_DDRTYPE_MASK 0x00000300U -/*Multi-Purpose Register (MPR) DQ (DDR3 Only)*/ +/* +* Multi-Purpose Register (MPR) DQ (DDR3 Only) +*/ #undef DDR_PHY_DCR_MPRDQ_DEFVAL #undef DDR_PHY_DCR_MPRDQ_SHIFT #undef DDR_PHY_DCR_MPRDQ_MASK -#define DDR_PHY_DCR_MPRDQ_DEFVAL 0x0000040D -#define DDR_PHY_DCR_MPRDQ_SHIFT 7 -#define DDR_PHY_DCR_MPRDQ_MASK 0x00000080U +#define DDR_PHY_DCR_MPRDQ_DEFVAL 0x0000040D +#define DDR_PHY_DCR_MPRDQ_SHIFT 7 +#define DDR_PHY_DCR_MPRDQ_MASK 0x00000080U -/*Primary DQ (DDR3 Only)*/ +/* +* Primary DQ (DDR3 Only) +*/ #undef DDR_PHY_DCR_PDQ_DEFVAL #undef DDR_PHY_DCR_PDQ_SHIFT #undef DDR_PHY_DCR_PDQ_MASK -#define DDR_PHY_DCR_PDQ_DEFVAL 0x0000040D -#define DDR_PHY_DCR_PDQ_SHIFT 4 -#define DDR_PHY_DCR_PDQ_MASK 0x00000070U +#define DDR_PHY_DCR_PDQ_DEFVAL 0x0000040D +#define DDR_PHY_DCR_PDQ_SHIFT 4 +#define DDR_PHY_DCR_PDQ_MASK 0x00000070U -/*DDR 8-Bank*/ +/* +* DDR 8-Bank +*/ #undef DDR_PHY_DCR_DDR8BNK_DEFVAL #undef DDR_PHY_DCR_DDR8BNK_SHIFT #undef DDR_PHY_DCR_DDR8BNK_MASK -#define DDR_PHY_DCR_DDR8BNK_DEFVAL 0x0000040D -#define DDR_PHY_DCR_DDR8BNK_SHIFT 3 -#define DDR_PHY_DCR_DDR8BNK_MASK 0x00000008U +#define DDR_PHY_DCR_DDR8BNK_DEFVAL 0x0000040D +#define DDR_PHY_DCR_DDR8BNK_SHIFT 3 +#define DDR_PHY_DCR_DDR8BNK_MASK 0x00000008U -/*DDR Mode*/ +/* +* DDR Mode +*/ #undef DDR_PHY_DCR_DDRMD_DEFVAL #undef DDR_PHY_DCR_DDRMD_SHIFT #undef DDR_PHY_DCR_DDRMD_MASK -#define DDR_PHY_DCR_DDRMD_DEFVAL 0x0000040D -#define DDR_PHY_DCR_DDRMD_SHIFT 0 -#define DDR_PHY_DCR_DDRMD_MASK 0x00000007U +#define DDR_PHY_DCR_DDRMD_DEFVAL 0x0000040D +#define DDR_PHY_DCR_DDRMD_SHIFT 0 +#define DDR_PHY_DCR_DDRMD_MASK 0x00000007U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR0_RESERVED_31_29_DEFVAL #undef DDR_PHY_DTPR0_RESERVED_31_29_SHIFT #undef DDR_PHY_DTPR0_RESERVED_31_29_MASK -#define DDR_PHY_DTPR0_RESERVED_31_29_DEFVAL 0x105A2D08 -#define DDR_PHY_DTPR0_RESERVED_31_29_SHIFT 29 -#define DDR_PHY_DTPR0_RESERVED_31_29_MASK 0xE0000000U +#define DDR_PHY_DTPR0_RESERVED_31_29_DEFVAL 0x105A2D08 +#define DDR_PHY_DTPR0_RESERVED_31_29_SHIFT 29 +#define DDR_PHY_DTPR0_RESERVED_31_29_MASK 0xE0000000U -/*Activate to activate command delay (different banks)*/ +/* +* Activate to activate command delay (different banks) +*/ #undef DDR_PHY_DTPR0_TRRD_DEFVAL #undef DDR_PHY_DTPR0_TRRD_SHIFT #undef DDR_PHY_DTPR0_TRRD_MASK -#define DDR_PHY_DTPR0_TRRD_DEFVAL 0x105A2D08 -#define DDR_PHY_DTPR0_TRRD_SHIFT 24 -#define DDR_PHY_DTPR0_TRRD_MASK 0x1F000000U +#define DDR_PHY_DTPR0_TRRD_DEFVAL 0x105A2D08 +#define DDR_PHY_DTPR0_TRRD_SHIFT 24 +#define DDR_PHY_DTPR0_TRRD_MASK 0x1F000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR0_RESERVED_23_DEFVAL #undef DDR_PHY_DTPR0_RESERVED_23_SHIFT #undef DDR_PHY_DTPR0_RESERVED_23_MASK -#define DDR_PHY_DTPR0_RESERVED_23_DEFVAL 0x105A2D08 -#define DDR_PHY_DTPR0_RESERVED_23_SHIFT 23 -#define DDR_PHY_DTPR0_RESERVED_23_MASK 0x00800000U +#define DDR_PHY_DTPR0_RESERVED_23_DEFVAL 0x105A2D08 +#define DDR_PHY_DTPR0_RESERVED_23_SHIFT 23 +#define DDR_PHY_DTPR0_RESERVED_23_MASK 0x00800000U -/*Activate to precharge command delay*/ +/* +* Activate to precharge command delay +*/ #undef DDR_PHY_DTPR0_TRAS_DEFVAL #undef DDR_PHY_DTPR0_TRAS_SHIFT #undef DDR_PHY_DTPR0_TRAS_MASK -#define DDR_PHY_DTPR0_TRAS_DEFVAL 0x105A2D08 -#define DDR_PHY_DTPR0_TRAS_SHIFT 16 -#define DDR_PHY_DTPR0_TRAS_MASK 0x007F0000U +#define DDR_PHY_DTPR0_TRAS_DEFVAL 0x105A2D08 +#define DDR_PHY_DTPR0_TRAS_SHIFT 16 +#define DDR_PHY_DTPR0_TRAS_MASK 0x007F0000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR0_RESERVED_15_DEFVAL #undef DDR_PHY_DTPR0_RESERVED_15_SHIFT #undef DDR_PHY_DTPR0_RESERVED_15_MASK -#define DDR_PHY_DTPR0_RESERVED_15_DEFVAL 0x105A2D08 -#define DDR_PHY_DTPR0_RESERVED_15_SHIFT 15 -#define DDR_PHY_DTPR0_RESERVED_15_MASK 0x00008000U +#define DDR_PHY_DTPR0_RESERVED_15_DEFVAL 0x105A2D08 +#define DDR_PHY_DTPR0_RESERVED_15_SHIFT 15 +#define DDR_PHY_DTPR0_RESERVED_15_MASK 0x00008000U -/*Precharge command period*/ +/* +* Precharge command period +*/ #undef DDR_PHY_DTPR0_TRP_DEFVAL #undef DDR_PHY_DTPR0_TRP_SHIFT #undef DDR_PHY_DTPR0_TRP_MASK -#define DDR_PHY_DTPR0_TRP_DEFVAL 0x105A2D08 -#define DDR_PHY_DTPR0_TRP_SHIFT 8 -#define DDR_PHY_DTPR0_TRP_MASK 0x00007F00U +#define DDR_PHY_DTPR0_TRP_DEFVAL 0x105A2D08 +#define DDR_PHY_DTPR0_TRP_SHIFT 8 +#define DDR_PHY_DTPR0_TRP_MASK 0x00007F00U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR0_RESERVED_7_5_DEFVAL #undef DDR_PHY_DTPR0_RESERVED_7_5_SHIFT #undef DDR_PHY_DTPR0_RESERVED_7_5_MASK -#define DDR_PHY_DTPR0_RESERVED_7_5_DEFVAL 0x105A2D08 -#define DDR_PHY_DTPR0_RESERVED_7_5_SHIFT 5 -#define DDR_PHY_DTPR0_RESERVED_7_5_MASK 0x000000E0U +#define DDR_PHY_DTPR0_RESERVED_7_5_DEFVAL 0x105A2D08 +#define DDR_PHY_DTPR0_RESERVED_7_5_SHIFT 5 +#define DDR_PHY_DTPR0_RESERVED_7_5_MASK 0x000000E0U -/*Internal read to precharge command delay*/ +/* +* Internal read to precharge command delay +*/ #undef DDR_PHY_DTPR0_TRTP_DEFVAL #undef DDR_PHY_DTPR0_TRTP_SHIFT #undef DDR_PHY_DTPR0_TRTP_MASK -#define DDR_PHY_DTPR0_TRTP_DEFVAL 0x105A2D08 -#define DDR_PHY_DTPR0_TRTP_SHIFT 0 -#define DDR_PHY_DTPR0_TRTP_MASK 0x0000001FU +#define DDR_PHY_DTPR0_TRTP_DEFVAL 0x105A2D08 +#define DDR_PHY_DTPR0_TRTP_SHIFT 0 +#define DDR_PHY_DTPR0_TRTP_MASK 0x0000001FU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR1_RESERVED_31_DEFVAL #undef DDR_PHY_DTPR1_RESERVED_31_SHIFT #undef DDR_PHY_DTPR1_RESERVED_31_MASK -#define DDR_PHY_DTPR1_RESERVED_31_DEFVAL 0x5656041E -#define DDR_PHY_DTPR1_RESERVED_31_SHIFT 31 -#define DDR_PHY_DTPR1_RESERVED_31_MASK 0x80000000U +#define DDR_PHY_DTPR1_RESERVED_31_DEFVAL 0x5656041E +#define DDR_PHY_DTPR1_RESERVED_31_SHIFT 31 +#define DDR_PHY_DTPR1_RESERVED_31_MASK 0x80000000U -/*Minimum delay from when write leveling mode is programmed to the first DQS/DQS# rising edge.*/ +/* +* Minimum delay from when write leveling mode is programmed to the first D + * QS/DQS# rising edge. +*/ #undef DDR_PHY_DTPR1_TWLMRD_DEFVAL #undef DDR_PHY_DTPR1_TWLMRD_SHIFT #undef DDR_PHY_DTPR1_TWLMRD_MASK -#define DDR_PHY_DTPR1_TWLMRD_DEFVAL 0x5656041E -#define DDR_PHY_DTPR1_TWLMRD_SHIFT 24 -#define DDR_PHY_DTPR1_TWLMRD_MASK 0x7F000000U +#define DDR_PHY_DTPR1_TWLMRD_DEFVAL 0x5656041E +#define DDR_PHY_DTPR1_TWLMRD_SHIFT 24 +#define DDR_PHY_DTPR1_TWLMRD_MASK 0x7F000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR1_RESERVED_23_DEFVAL #undef DDR_PHY_DTPR1_RESERVED_23_SHIFT #undef DDR_PHY_DTPR1_RESERVED_23_MASK -#define DDR_PHY_DTPR1_RESERVED_23_DEFVAL 0x5656041E -#define DDR_PHY_DTPR1_RESERVED_23_SHIFT 23 -#define DDR_PHY_DTPR1_RESERVED_23_MASK 0x00800000U +#define DDR_PHY_DTPR1_RESERVED_23_DEFVAL 0x5656041E +#define DDR_PHY_DTPR1_RESERVED_23_SHIFT 23 +#define DDR_PHY_DTPR1_RESERVED_23_MASK 0x00800000U -/*4-bank activate period*/ +/* +* 4-bank activate period +*/ #undef DDR_PHY_DTPR1_TFAW_DEFVAL #undef DDR_PHY_DTPR1_TFAW_SHIFT #undef DDR_PHY_DTPR1_TFAW_MASK -#define DDR_PHY_DTPR1_TFAW_DEFVAL 0x5656041E -#define DDR_PHY_DTPR1_TFAW_SHIFT 16 -#define DDR_PHY_DTPR1_TFAW_MASK 0x007F0000U +#define DDR_PHY_DTPR1_TFAW_DEFVAL 0x5656041E +#define DDR_PHY_DTPR1_TFAW_SHIFT 16 +#define DDR_PHY_DTPR1_TFAW_MASK 0x007F0000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR1_RESERVED_15_11_DEFVAL #undef DDR_PHY_DTPR1_RESERVED_15_11_SHIFT #undef DDR_PHY_DTPR1_RESERVED_15_11_MASK -#define DDR_PHY_DTPR1_RESERVED_15_11_DEFVAL 0x5656041E -#define DDR_PHY_DTPR1_RESERVED_15_11_SHIFT 11 -#define DDR_PHY_DTPR1_RESERVED_15_11_MASK 0x0000F800U +#define DDR_PHY_DTPR1_RESERVED_15_11_DEFVAL 0x5656041E +#define DDR_PHY_DTPR1_RESERVED_15_11_SHIFT 11 +#define DDR_PHY_DTPR1_RESERVED_15_11_MASK 0x0000F800U -/*Load mode update delay (DDR4 and DDR3 only)*/ +/* +* Load mode update delay (DDR4 and DDR3 only) +*/ #undef DDR_PHY_DTPR1_TMOD_DEFVAL #undef DDR_PHY_DTPR1_TMOD_SHIFT #undef DDR_PHY_DTPR1_TMOD_MASK -#define DDR_PHY_DTPR1_TMOD_DEFVAL 0x5656041E -#define DDR_PHY_DTPR1_TMOD_SHIFT 8 -#define DDR_PHY_DTPR1_TMOD_MASK 0x00000700U +#define DDR_PHY_DTPR1_TMOD_DEFVAL 0x5656041E +#define DDR_PHY_DTPR1_TMOD_SHIFT 8 +#define DDR_PHY_DTPR1_TMOD_MASK 0x00000700U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR1_RESERVED_7_5_DEFVAL #undef DDR_PHY_DTPR1_RESERVED_7_5_SHIFT #undef DDR_PHY_DTPR1_RESERVED_7_5_MASK -#define DDR_PHY_DTPR1_RESERVED_7_5_DEFVAL 0x5656041E -#define DDR_PHY_DTPR1_RESERVED_7_5_SHIFT 5 -#define DDR_PHY_DTPR1_RESERVED_7_5_MASK 0x000000E0U +#define DDR_PHY_DTPR1_RESERVED_7_5_DEFVAL 0x5656041E +#define DDR_PHY_DTPR1_RESERVED_7_5_SHIFT 5 +#define DDR_PHY_DTPR1_RESERVED_7_5_MASK 0x000000E0U -/*Load mode cycle time*/ +/* +* Load mode cycle time +*/ #undef DDR_PHY_DTPR1_TMRD_DEFVAL #undef DDR_PHY_DTPR1_TMRD_SHIFT #undef DDR_PHY_DTPR1_TMRD_MASK -#define DDR_PHY_DTPR1_TMRD_DEFVAL 0x5656041E -#define DDR_PHY_DTPR1_TMRD_SHIFT 0 -#define DDR_PHY_DTPR1_TMRD_MASK 0x0000001FU +#define DDR_PHY_DTPR1_TMRD_DEFVAL 0x5656041E +#define DDR_PHY_DTPR1_TMRD_SHIFT 0 +#define DDR_PHY_DTPR1_TMRD_MASK 0x0000001FU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR2_RESERVED_31_29_DEFVAL #undef DDR_PHY_DTPR2_RESERVED_31_29_SHIFT #undef DDR_PHY_DTPR2_RESERVED_31_29_MASK -#define DDR_PHY_DTPR2_RESERVED_31_29_DEFVAL 0x000B01D0 -#define DDR_PHY_DTPR2_RESERVED_31_29_SHIFT 29 -#define DDR_PHY_DTPR2_RESERVED_31_29_MASK 0xE0000000U +#define DDR_PHY_DTPR2_RESERVED_31_29_DEFVAL 0x000B01D0 +#define DDR_PHY_DTPR2_RESERVED_31_29_SHIFT 29 +#define DDR_PHY_DTPR2_RESERVED_31_29_MASK 0xE0000000U -/*Read to Write command delay. Valid values are*/ +/* +* Read to Write command delay. Valid values are +*/ #undef DDR_PHY_DTPR2_TRTW_DEFVAL #undef DDR_PHY_DTPR2_TRTW_SHIFT #undef DDR_PHY_DTPR2_TRTW_MASK -#define DDR_PHY_DTPR2_TRTW_DEFVAL 0x000B01D0 -#define DDR_PHY_DTPR2_TRTW_SHIFT 28 -#define DDR_PHY_DTPR2_TRTW_MASK 0x10000000U +#define DDR_PHY_DTPR2_TRTW_DEFVAL 0x000B01D0 +#define DDR_PHY_DTPR2_TRTW_SHIFT 28 +#define DDR_PHY_DTPR2_TRTW_MASK 0x10000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR2_RESERVED_27_25_DEFVAL #undef DDR_PHY_DTPR2_RESERVED_27_25_SHIFT #undef DDR_PHY_DTPR2_RESERVED_27_25_MASK -#define DDR_PHY_DTPR2_RESERVED_27_25_DEFVAL 0x000B01D0 -#define DDR_PHY_DTPR2_RESERVED_27_25_SHIFT 25 -#define DDR_PHY_DTPR2_RESERVED_27_25_MASK 0x0E000000U +#define DDR_PHY_DTPR2_RESERVED_27_25_DEFVAL 0x000B01D0 +#define DDR_PHY_DTPR2_RESERVED_27_25_SHIFT 25 +#define DDR_PHY_DTPR2_RESERVED_27_25_MASK 0x0E000000U -/*Read to ODT delay (DDR3 only)*/ +/* +* Read to ODT delay (DDR3 only) +*/ #undef DDR_PHY_DTPR2_TRTODT_DEFVAL #undef DDR_PHY_DTPR2_TRTODT_SHIFT #undef DDR_PHY_DTPR2_TRTODT_MASK -#define DDR_PHY_DTPR2_TRTODT_DEFVAL 0x000B01D0 -#define DDR_PHY_DTPR2_TRTODT_SHIFT 24 -#define DDR_PHY_DTPR2_TRTODT_MASK 0x01000000U +#define DDR_PHY_DTPR2_TRTODT_DEFVAL 0x000B01D0 +#define DDR_PHY_DTPR2_TRTODT_SHIFT 24 +#define DDR_PHY_DTPR2_TRTODT_MASK 0x01000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR2_RESERVED_23_20_DEFVAL #undef DDR_PHY_DTPR2_RESERVED_23_20_SHIFT #undef DDR_PHY_DTPR2_RESERVED_23_20_MASK -#define DDR_PHY_DTPR2_RESERVED_23_20_DEFVAL 0x000B01D0 -#define DDR_PHY_DTPR2_RESERVED_23_20_SHIFT 20 -#define DDR_PHY_DTPR2_RESERVED_23_20_MASK 0x00F00000U +#define DDR_PHY_DTPR2_RESERVED_23_20_DEFVAL 0x000B01D0 +#define DDR_PHY_DTPR2_RESERVED_23_20_SHIFT 20 +#define DDR_PHY_DTPR2_RESERVED_23_20_MASK 0x00F00000U -/*CKE minimum pulse width*/ +/* +* CKE minimum pulse width +*/ #undef DDR_PHY_DTPR2_TCKE_DEFVAL #undef DDR_PHY_DTPR2_TCKE_SHIFT #undef DDR_PHY_DTPR2_TCKE_MASK -#define DDR_PHY_DTPR2_TCKE_DEFVAL 0x000B01D0 -#define DDR_PHY_DTPR2_TCKE_SHIFT 16 -#define DDR_PHY_DTPR2_TCKE_MASK 0x000F0000U +#define DDR_PHY_DTPR2_TCKE_DEFVAL 0x000B01D0 +#define DDR_PHY_DTPR2_TCKE_SHIFT 16 +#define DDR_PHY_DTPR2_TCKE_MASK 0x000F0000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR2_RESERVED_15_10_DEFVAL #undef DDR_PHY_DTPR2_RESERVED_15_10_SHIFT #undef DDR_PHY_DTPR2_RESERVED_15_10_MASK -#define DDR_PHY_DTPR2_RESERVED_15_10_DEFVAL 0x000B01D0 -#define DDR_PHY_DTPR2_RESERVED_15_10_SHIFT 10 -#define DDR_PHY_DTPR2_RESERVED_15_10_MASK 0x0000FC00U +#define DDR_PHY_DTPR2_RESERVED_15_10_DEFVAL 0x000B01D0 +#define DDR_PHY_DTPR2_RESERVED_15_10_SHIFT 10 +#define DDR_PHY_DTPR2_RESERVED_15_10_MASK 0x0000FC00U -/*Self refresh exit delay*/ +/* +* Self refresh exit delay +*/ #undef DDR_PHY_DTPR2_TXS_DEFVAL #undef DDR_PHY_DTPR2_TXS_SHIFT #undef DDR_PHY_DTPR2_TXS_MASK -#define DDR_PHY_DTPR2_TXS_DEFVAL 0x000B01D0 -#define DDR_PHY_DTPR2_TXS_SHIFT 0 -#define DDR_PHY_DTPR2_TXS_MASK 0x000003FFU +#define DDR_PHY_DTPR2_TXS_DEFVAL 0x000B01D0 +#define DDR_PHY_DTPR2_TXS_SHIFT 0 +#define DDR_PHY_DTPR2_TXS_MASK 0x000003FFU -/*ODT turn-off delay extension*/ +/* +* ODT turn-off delay extension +*/ #undef DDR_PHY_DTPR3_TOFDX_DEFVAL #undef DDR_PHY_DTPR3_TOFDX_SHIFT #undef DDR_PHY_DTPR3_TOFDX_MASK -#define DDR_PHY_DTPR3_TOFDX_DEFVAL 0x02000804 -#define DDR_PHY_DTPR3_TOFDX_SHIFT 29 -#define DDR_PHY_DTPR3_TOFDX_MASK 0xE0000000U +#define DDR_PHY_DTPR3_TOFDX_DEFVAL 0x02000804 +#define DDR_PHY_DTPR3_TOFDX_SHIFT 29 +#define DDR_PHY_DTPR3_TOFDX_MASK 0xE0000000U -/*Read to read and write to write command delay*/ +/* +* Read to read and write to write command delay +*/ #undef DDR_PHY_DTPR3_TCCD_DEFVAL #undef DDR_PHY_DTPR3_TCCD_SHIFT #undef DDR_PHY_DTPR3_TCCD_MASK -#define DDR_PHY_DTPR3_TCCD_DEFVAL 0x02000804 -#define DDR_PHY_DTPR3_TCCD_SHIFT 26 -#define DDR_PHY_DTPR3_TCCD_MASK 0x1C000000U +#define DDR_PHY_DTPR3_TCCD_DEFVAL 0x02000804 +#define DDR_PHY_DTPR3_TCCD_SHIFT 26 +#define DDR_PHY_DTPR3_TCCD_MASK 0x1C000000U -/*DLL locking time*/ +/* +* DLL locking time +*/ #undef DDR_PHY_DTPR3_TDLLK_DEFVAL #undef DDR_PHY_DTPR3_TDLLK_SHIFT #undef DDR_PHY_DTPR3_TDLLK_MASK -#define DDR_PHY_DTPR3_TDLLK_DEFVAL 0x02000804 -#define DDR_PHY_DTPR3_TDLLK_SHIFT 16 -#define DDR_PHY_DTPR3_TDLLK_MASK 0x03FF0000U +#define DDR_PHY_DTPR3_TDLLK_DEFVAL 0x02000804 +#define DDR_PHY_DTPR3_TDLLK_SHIFT 16 +#define DDR_PHY_DTPR3_TDLLK_MASK 0x03FF0000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR3_RESERVED_15_12_DEFVAL #undef DDR_PHY_DTPR3_RESERVED_15_12_SHIFT #undef DDR_PHY_DTPR3_RESERVED_15_12_MASK -#define DDR_PHY_DTPR3_RESERVED_15_12_DEFVAL 0x02000804 -#define DDR_PHY_DTPR3_RESERVED_15_12_SHIFT 12 -#define DDR_PHY_DTPR3_RESERVED_15_12_MASK 0x0000F000U +#define DDR_PHY_DTPR3_RESERVED_15_12_DEFVAL 0x02000804 +#define DDR_PHY_DTPR3_RESERVED_15_12_SHIFT 12 +#define DDR_PHY_DTPR3_RESERVED_15_12_MASK 0x0000F000U -/*Maximum DQS output access time from CK/CK# (LPDDR2/3 only)*/ +/* +* Maximum DQS output access time from CK/CK# (LPDDR2/3 only) +*/ #undef DDR_PHY_DTPR3_TDQSCKMAX_DEFVAL #undef DDR_PHY_DTPR3_TDQSCKMAX_SHIFT #undef DDR_PHY_DTPR3_TDQSCKMAX_MASK -#define DDR_PHY_DTPR3_TDQSCKMAX_DEFVAL 0x02000804 -#define DDR_PHY_DTPR3_TDQSCKMAX_SHIFT 8 -#define DDR_PHY_DTPR3_TDQSCKMAX_MASK 0x00000F00U +#define DDR_PHY_DTPR3_TDQSCKMAX_DEFVAL 0x02000804 +#define DDR_PHY_DTPR3_TDQSCKMAX_SHIFT 8 +#define DDR_PHY_DTPR3_TDQSCKMAX_MASK 0x00000F00U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR3_RESERVED_7_3_DEFVAL #undef DDR_PHY_DTPR3_RESERVED_7_3_SHIFT #undef DDR_PHY_DTPR3_RESERVED_7_3_MASK -#define DDR_PHY_DTPR3_RESERVED_7_3_DEFVAL 0x02000804 -#define DDR_PHY_DTPR3_RESERVED_7_3_SHIFT 3 -#define DDR_PHY_DTPR3_RESERVED_7_3_MASK 0x000000F8U +#define DDR_PHY_DTPR3_RESERVED_7_3_DEFVAL 0x02000804 +#define DDR_PHY_DTPR3_RESERVED_7_3_SHIFT 3 +#define DDR_PHY_DTPR3_RESERVED_7_3_MASK 0x000000F8U -/*DQS output access time from CK/CK# (LPDDR2/3 only)*/ +/* +* DQS output access time from CK/CK# (LPDDR2/3 only) +*/ #undef DDR_PHY_DTPR3_TDQSCK_DEFVAL #undef DDR_PHY_DTPR3_TDQSCK_SHIFT #undef DDR_PHY_DTPR3_TDQSCK_MASK -#define DDR_PHY_DTPR3_TDQSCK_DEFVAL 0x02000804 -#define DDR_PHY_DTPR3_TDQSCK_SHIFT 0 -#define DDR_PHY_DTPR3_TDQSCK_MASK 0x00000007U +#define DDR_PHY_DTPR3_TDQSCK_DEFVAL 0x02000804 +#define DDR_PHY_DTPR3_TDQSCK_SHIFT 0 +#define DDR_PHY_DTPR3_TDQSCK_MASK 0x00000007U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR4_RESERVED_31_30_DEFVAL #undef DDR_PHY_DTPR4_RESERVED_31_30_SHIFT #undef DDR_PHY_DTPR4_RESERVED_31_30_MASK -#define DDR_PHY_DTPR4_RESERVED_31_30_DEFVAL 0x01C02B10 -#define DDR_PHY_DTPR4_RESERVED_31_30_SHIFT 30 -#define DDR_PHY_DTPR4_RESERVED_31_30_MASK 0xC0000000U +#define DDR_PHY_DTPR4_RESERVED_31_30_DEFVAL 0x01C02B10 +#define DDR_PHY_DTPR4_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DTPR4_RESERVED_31_30_MASK 0xC0000000U -/*ODT turn-on/turn-off delays (DDR2 only)*/ +/* +* ODT turn-on/turn-off delays (DDR2 only) +*/ #undef DDR_PHY_DTPR4_TAOND_TAOFD_DEFVAL #undef DDR_PHY_DTPR4_TAOND_TAOFD_SHIFT #undef DDR_PHY_DTPR4_TAOND_TAOFD_MASK -#define DDR_PHY_DTPR4_TAOND_TAOFD_DEFVAL 0x01C02B10 -#define DDR_PHY_DTPR4_TAOND_TAOFD_SHIFT 28 -#define DDR_PHY_DTPR4_TAOND_TAOFD_MASK 0x30000000U +#define DDR_PHY_DTPR4_TAOND_TAOFD_DEFVAL 0x01C02B10 +#define DDR_PHY_DTPR4_TAOND_TAOFD_SHIFT 28 +#define DDR_PHY_DTPR4_TAOND_TAOFD_MASK 0x30000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR4_RESERVED_27_26_DEFVAL #undef DDR_PHY_DTPR4_RESERVED_27_26_SHIFT #undef DDR_PHY_DTPR4_RESERVED_27_26_MASK -#define DDR_PHY_DTPR4_RESERVED_27_26_DEFVAL 0x01C02B10 -#define DDR_PHY_DTPR4_RESERVED_27_26_SHIFT 26 -#define DDR_PHY_DTPR4_RESERVED_27_26_MASK 0x0C000000U +#define DDR_PHY_DTPR4_RESERVED_27_26_DEFVAL 0x01C02B10 +#define DDR_PHY_DTPR4_RESERVED_27_26_SHIFT 26 +#define DDR_PHY_DTPR4_RESERVED_27_26_MASK 0x0C000000U -/*Refresh-to-Refresh*/ +/* +* Refresh-to-Refresh +*/ #undef DDR_PHY_DTPR4_TRFC_DEFVAL #undef DDR_PHY_DTPR4_TRFC_SHIFT #undef DDR_PHY_DTPR4_TRFC_MASK -#define DDR_PHY_DTPR4_TRFC_DEFVAL 0x01C02B10 -#define DDR_PHY_DTPR4_TRFC_SHIFT 16 -#define DDR_PHY_DTPR4_TRFC_MASK 0x03FF0000U +#define DDR_PHY_DTPR4_TRFC_DEFVAL 0x01C02B10 +#define DDR_PHY_DTPR4_TRFC_SHIFT 16 +#define DDR_PHY_DTPR4_TRFC_MASK 0x03FF0000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR4_RESERVED_15_14_DEFVAL #undef DDR_PHY_DTPR4_RESERVED_15_14_SHIFT #undef DDR_PHY_DTPR4_RESERVED_15_14_MASK -#define DDR_PHY_DTPR4_RESERVED_15_14_DEFVAL 0x01C02B10 -#define DDR_PHY_DTPR4_RESERVED_15_14_SHIFT 14 -#define DDR_PHY_DTPR4_RESERVED_15_14_MASK 0x0000C000U +#define DDR_PHY_DTPR4_RESERVED_15_14_DEFVAL 0x01C02B10 +#define DDR_PHY_DTPR4_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_DTPR4_RESERVED_15_14_MASK 0x0000C000U -/*Write leveling output delay*/ +/* +* Write leveling output delay +*/ #undef DDR_PHY_DTPR4_TWLO_DEFVAL #undef DDR_PHY_DTPR4_TWLO_SHIFT #undef DDR_PHY_DTPR4_TWLO_MASK -#define DDR_PHY_DTPR4_TWLO_DEFVAL 0x01C02B10 -#define DDR_PHY_DTPR4_TWLO_SHIFT 8 -#define DDR_PHY_DTPR4_TWLO_MASK 0x00003F00U +#define DDR_PHY_DTPR4_TWLO_DEFVAL 0x01C02B10 +#define DDR_PHY_DTPR4_TWLO_SHIFT 8 +#define DDR_PHY_DTPR4_TWLO_MASK 0x00003F00U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR4_RESERVED_7_5_DEFVAL #undef DDR_PHY_DTPR4_RESERVED_7_5_SHIFT #undef DDR_PHY_DTPR4_RESERVED_7_5_MASK -#define DDR_PHY_DTPR4_RESERVED_7_5_DEFVAL 0x01C02B10 -#define DDR_PHY_DTPR4_RESERVED_7_5_SHIFT 5 -#define DDR_PHY_DTPR4_RESERVED_7_5_MASK 0x000000E0U +#define DDR_PHY_DTPR4_RESERVED_7_5_DEFVAL 0x01C02B10 +#define DDR_PHY_DTPR4_RESERVED_7_5_SHIFT 5 +#define DDR_PHY_DTPR4_RESERVED_7_5_MASK 0x000000E0U -/*Power down exit delay*/ +/* +* Power down exit delay +*/ #undef DDR_PHY_DTPR4_TXP_DEFVAL #undef DDR_PHY_DTPR4_TXP_SHIFT #undef DDR_PHY_DTPR4_TXP_MASK -#define DDR_PHY_DTPR4_TXP_DEFVAL 0x01C02B10 -#define DDR_PHY_DTPR4_TXP_SHIFT 0 -#define DDR_PHY_DTPR4_TXP_MASK 0x0000001FU +#define DDR_PHY_DTPR4_TXP_DEFVAL 0x01C02B10 +#define DDR_PHY_DTPR4_TXP_SHIFT 0 +#define DDR_PHY_DTPR4_TXP_MASK 0x0000001FU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR5_RESERVED_31_24_DEFVAL #undef DDR_PHY_DTPR5_RESERVED_31_24_SHIFT #undef DDR_PHY_DTPR5_RESERVED_31_24_MASK -#define DDR_PHY_DTPR5_RESERVED_31_24_DEFVAL 0x00872716 -#define DDR_PHY_DTPR5_RESERVED_31_24_SHIFT 24 -#define DDR_PHY_DTPR5_RESERVED_31_24_MASK 0xFF000000U +#define DDR_PHY_DTPR5_RESERVED_31_24_DEFVAL 0x00872716 +#define DDR_PHY_DTPR5_RESERVED_31_24_SHIFT 24 +#define DDR_PHY_DTPR5_RESERVED_31_24_MASK 0xFF000000U -/*Activate to activate command delay (same bank)*/ +/* +* Activate to activate command delay (same bank) +*/ #undef DDR_PHY_DTPR5_TRC_DEFVAL #undef DDR_PHY_DTPR5_TRC_SHIFT #undef DDR_PHY_DTPR5_TRC_MASK -#define DDR_PHY_DTPR5_TRC_DEFVAL 0x00872716 -#define DDR_PHY_DTPR5_TRC_SHIFT 16 -#define DDR_PHY_DTPR5_TRC_MASK 0x00FF0000U +#define DDR_PHY_DTPR5_TRC_DEFVAL 0x00872716 +#define DDR_PHY_DTPR5_TRC_SHIFT 16 +#define DDR_PHY_DTPR5_TRC_MASK 0x00FF0000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR5_RESERVED_15_DEFVAL #undef DDR_PHY_DTPR5_RESERVED_15_SHIFT #undef DDR_PHY_DTPR5_RESERVED_15_MASK -#define DDR_PHY_DTPR5_RESERVED_15_DEFVAL 0x00872716 -#define DDR_PHY_DTPR5_RESERVED_15_SHIFT 15 -#define DDR_PHY_DTPR5_RESERVED_15_MASK 0x00008000U +#define DDR_PHY_DTPR5_RESERVED_15_DEFVAL 0x00872716 +#define DDR_PHY_DTPR5_RESERVED_15_SHIFT 15 +#define DDR_PHY_DTPR5_RESERVED_15_MASK 0x00008000U -/*Activate to read or write delay*/ +/* +* Activate to read or write delay +*/ #undef DDR_PHY_DTPR5_TRCD_DEFVAL #undef DDR_PHY_DTPR5_TRCD_SHIFT #undef DDR_PHY_DTPR5_TRCD_MASK -#define DDR_PHY_DTPR5_TRCD_DEFVAL 0x00872716 -#define DDR_PHY_DTPR5_TRCD_SHIFT 8 -#define DDR_PHY_DTPR5_TRCD_MASK 0x00007F00U +#define DDR_PHY_DTPR5_TRCD_DEFVAL 0x00872716 +#define DDR_PHY_DTPR5_TRCD_SHIFT 8 +#define DDR_PHY_DTPR5_TRCD_MASK 0x00007F00U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR5_RESERVED_7_5_DEFVAL #undef DDR_PHY_DTPR5_RESERVED_7_5_SHIFT #undef DDR_PHY_DTPR5_RESERVED_7_5_MASK -#define DDR_PHY_DTPR5_RESERVED_7_5_DEFVAL 0x00872716 -#define DDR_PHY_DTPR5_RESERVED_7_5_SHIFT 5 -#define DDR_PHY_DTPR5_RESERVED_7_5_MASK 0x000000E0U +#define DDR_PHY_DTPR5_RESERVED_7_5_DEFVAL 0x00872716 +#define DDR_PHY_DTPR5_RESERVED_7_5_SHIFT 5 +#define DDR_PHY_DTPR5_RESERVED_7_5_MASK 0x000000E0U -/*Internal write to read command delay*/ +/* +* Internal write to read command delay +*/ #undef DDR_PHY_DTPR5_TWTR_DEFVAL #undef DDR_PHY_DTPR5_TWTR_SHIFT #undef DDR_PHY_DTPR5_TWTR_MASK -#define DDR_PHY_DTPR5_TWTR_DEFVAL 0x00872716 -#define DDR_PHY_DTPR5_TWTR_SHIFT 0 -#define DDR_PHY_DTPR5_TWTR_MASK 0x0000001FU +#define DDR_PHY_DTPR5_TWTR_DEFVAL 0x00872716 +#define DDR_PHY_DTPR5_TWTR_SHIFT 0 +#define DDR_PHY_DTPR5_TWTR_MASK 0x0000001FU -/*PUB Write Latency Enable*/ +/* +* PUB Write Latency Enable +*/ #undef DDR_PHY_DTPR6_PUBWLEN_DEFVAL #undef DDR_PHY_DTPR6_PUBWLEN_SHIFT #undef DDR_PHY_DTPR6_PUBWLEN_MASK -#define DDR_PHY_DTPR6_PUBWLEN_DEFVAL 0x00000505 -#define DDR_PHY_DTPR6_PUBWLEN_SHIFT 31 -#define DDR_PHY_DTPR6_PUBWLEN_MASK 0x80000000U +#define DDR_PHY_DTPR6_PUBWLEN_DEFVAL 0x00000505 +#define DDR_PHY_DTPR6_PUBWLEN_SHIFT 31 +#define DDR_PHY_DTPR6_PUBWLEN_MASK 0x80000000U -/*PUB Read Latency Enable*/ +/* +* PUB Read Latency Enable +*/ #undef DDR_PHY_DTPR6_PUBRLEN_DEFVAL #undef DDR_PHY_DTPR6_PUBRLEN_SHIFT #undef DDR_PHY_DTPR6_PUBRLEN_MASK -#define DDR_PHY_DTPR6_PUBRLEN_DEFVAL 0x00000505 -#define DDR_PHY_DTPR6_PUBRLEN_SHIFT 30 -#define DDR_PHY_DTPR6_PUBRLEN_MASK 0x40000000U +#define DDR_PHY_DTPR6_PUBRLEN_DEFVAL 0x00000505 +#define DDR_PHY_DTPR6_PUBRLEN_SHIFT 30 +#define DDR_PHY_DTPR6_PUBRLEN_MASK 0x40000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR6_RESERVED_29_14_DEFVAL #undef DDR_PHY_DTPR6_RESERVED_29_14_SHIFT #undef DDR_PHY_DTPR6_RESERVED_29_14_MASK -#define DDR_PHY_DTPR6_RESERVED_29_14_DEFVAL 0x00000505 -#define DDR_PHY_DTPR6_RESERVED_29_14_SHIFT 14 -#define DDR_PHY_DTPR6_RESERVED_29_14_MASK 0x3FFFC000U +#define DDR_PHY_DTPR6_RESERVED_29_14_DEFVAL 0x00000505 +#define DDR_PHY_DTPR6_RESERVED_29_14_SHIFT 14 +#define DDR_PHY_DTPR6_RESERVED_29_14_MASK 0x3FFFC000U -/*Write Latency*/ +/* +* Write Latency +*/ #undef DDR_PHY_DTPR6_PUBWL_DEFVAL #undef DDR_PHY_DTPR6_PUBWL_SHIFT #undef DDR_PHY_DTPR6_PUBWL_MASK -#define DDR_PHY_DTPR6_PUBWL_DEFVAL 0x00000505 -#define DDR_PHY_DTPR6_PUBWL_SHIFT 8 -#define DDR_PHY_DTPR6_PUBWL_MASK 0x00003F00U +#define DDR_PHY_DTPR6_PUBWL_DEFVAL 0x00000505 +#define DDR_PHY_DTPR6_PUBWL_SHIFT 8 +#define DDR_PHY_DTPR6_PUBWL_MASK 0x00003F00U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTPR6_RESERVED_7_6_DEFVAL #undef DDR_PHY_DTPR6_RESERVED_7_6_SHIFT #undef DDR_PHY_DTPR6_RESERVED_7_6_MASK -#define DDR_PHY_DTPR6_RESERVED_7_6_DEFVAL 0x00000505 -#define DDR_PHY_DTPR6_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_DTPR6_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_DTPR6_RESERVED_7_6_DEFVAL 0x00000505 +#define DDR_PHY_DTPR6_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DTPR6_RESERVED_7_6_MASK 0x000000C0U -/*Read Latency*/ +/* +* Read Latency +*/ #undef DDR_PHY_DTPR6_PUBRL_DEFVAL #undef DDR_PHY_DTPR6_PUBRL_SHIFT #undef DDR_PHY_DTPR6_PUBRL_MASK -#define DDR_PHY_DTPR6_PUBRL_DEFVAL 0x00000505 -#define DDR_PHY_DTPR6_PUBRL_SHIFT 0 -#define DDR_PHY_DTPR6_PUBRL_MASK 0x0000003FU +#define DDR_PHY_DTPR6_PUBRL_DEFVAL 0x00000505 +#define DDR_PHY_DTPR6_PUBRL_SHIFT 0 +#define DDR_PHY_DTPR6_PUBRL_MASK 0x0000003FU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_RDIMMGCR0_RESERVED_31_DEFVAL #undef DDR_PHY_RDIMMGCR0_RESERVED_31_SHIFT #undef DDR_PHY_RDIMMGCR0_RESERVED_31_MASK -#define DDR_PHY_RDIMMGCR0_RESERVED_31_DEFVAL 0x08400020 -#define DDR_PHY_RDIMMGCR0_RESERVED_31_SHIFT 31 -#define DDR_PHY_RDIMMGCR0_RESERVED_31_MASK 0x80000000U +#define DDR_PHY_RDIMMGCR0_RESERVED_31_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_RESERVED_31_SHIFT 31 +#define DDR_PHY_RDIMMGCR0_RESERVED_31_MASK 0x80000000U -/*RDMIMM Quad CS Enable*/ +/* +* RDMIMM Quad CS Enable +*/ #undef DDR_PHY_RDIMMGCR0_QCSEN_DEFVAL #undef DDR_PHY_RDIMMGCR0_QCSEN_SHIFT #undef DDR_PHY_RDIMMGCR0_QCSEN_MASK -#define DDR_PHY_RDIMMGCR0_QCSEN_DEFVAL 0x08400020 -#define DDR_PHY_RDIMMGCR0_QCSEN_SHIFT 30 -#define DDR_PHY_RDIMMGCR0_QCSEN_MASK 0x40000000U +#define DDR_PHY_RDIMMGCR0_QCSEN_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_QCSEN_SHIFT 30 +#define DDR_PHY_RDIMMGCR0_QCSEN_MASK 0x40000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_RDIMMGCR0_RESERVED_29_28_DEFVAL #undef DDR_PHY_RDIMMGCR0_RESERVED_29_28_SHIFT #undef DDR_PHY_RDIMMGCR0_RESERVED_29_28_MASK -#define DDR_PHY_RDIMMGCR0_RESERVED_29_28_DEFVAL 0x08400020 -#define DDR_PHY_RDIMMGCR0_RESERVED_29_28_SHIFT 28 -#define DDR_PHY_RDIMMGCR0_RESERVED_29_28_MASK 0x30000000U +#define DDR_PHY_RDIMMGCR0_RESERVED_29_28_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_RESERVED_29_28_SHIFT 28 +#define DDR_PHY_RDIMMGCR0_RESERVED_29_28_MASK 0x30000000U -/*RDIMM Outputs I/O Mode*/ +/* +* RDIMM Outputs I/O Mode +*/ #undef DDR_PHY_RDIMMGCR0_RDIMMIOM_DEFVAL #undef DDR_PHY_RDIMMGCR0_RDIMMIOM_SHIFT #undef DDR_PHY_RDIMMGCR0_RDIMMIOM_MASK -#define DDR_PHY_RDIMMGCR0_RDIMMIOM_DEFVAL 0x08400020 -#define DDR_PHY_RDIMMGCR0_RDIMMIOM_SHIFT 27 -#define DDR_PHY_RDIMMGCR0_RDIMMIOM_MASK 0x08000000U +#define DDR_PHY_RDIMMGCR0_RDIMMIOM_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_RDIMMIOM_SHIFT 27 +#define DDR_PHY_RDIMMGCR0_RDIMMIOM_MASK 0x08000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_RDIMMGCR0_RESERVED_26_24_DEFVAL #undef DDR_PHY_RDIMMGCR0_RESERVED_26_24_SHIFT #undef DDR_PHY_RDIMMGCR0_RESERVED_26_24_MASK -#define DDR_PHY_RDIMMGCR0_RESERVED_26_24_DEFVAL 0x08400020 -#define DDR_PHY_RDIMMGCR0_RESERVED_26_24_SHIFT 24 -#define DDR_PHY_RDIMMGCR0_RESERVED_26_24_MASK 0x07000000U +#define DDR_PHY_RDIMMGCR0_RESERVED_26_24_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_RESERVED_26_24_SHIFT 24 +#define DDR_PHY_RDIMMGCR0_RESERVED_26_24_MASK 0x07000000U -/*ERROUT# Output Enable*/ +/* +* ERROUT# Output Enable +*/ #undef DDR_PHY_RDIMMGCR0_ERROUTOE_DEFVAL #undef DDR_PHY_RDIMMGCR0_ERROUTOE_SHIFT #undef DDR_PHY_RDIMMGCR0_ERROUTOE_MASK -#define DDR_PHY_RDIMMGCR0_ERROUTOE_DEFVAL 0x08400020 -#define DDR_PHY_RDIMMGCR0_ERROUTOE_SHIFT 23 -#define DDR_PHY_RDIMMGCR0_ERROUTOE_MASK 0x00800000U +#define DDR_PHY_RDIMMGCR0_ERROUTOE_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_ERROUTOE_SHIFT 23 +#define DDR_PHY_RDIMMGCR0_ERROUTOE_MASK 0x00800000U -/*ERROUT# I/O Mode*/ +/* +* ERROUT# I/O Mode +*/ #undef DDR_PHY_RDIMMGCR0_ERROUTIOM_DEFVAL #undef DDR_PHY_RDIMMGCR0_ERROUTIOM_SHIFT #undef DDR_PHY_RDIMMGCR0_ERROUTIOM_MASK -#define DDR_PHY_RDIMMGCR0_ERROUTIOM_DEFVAL 0x08400020 -#define DDR_PHY_RDIMMGCR0_ERROUTIOM_SHIFT 22 -#define DDR_PHY_RDIMMGCR0_ERROUTIOM_MASK 0x00400000U +#define DDR_PHY_RDIMMGCR0_ERROUTIOM_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_ERROUTIOM_SHIFT 22 +#define DDR_PHY_RDIMMGCR0_ERROUTIOM_MASK 0x00400000U -/*ERROUT# Power Down Receiver*/ +/* +* ERROUT# Power Down Receiver +*/ #undef DDR_PHY_RDIMMGCR0_ERROUTPDR_DEFVAL #undef DDR_PHY_RDIMMGCR0_ERROUTPDR_SHIFT #undef DDR_PHY_RDIMMGCR0_ERROUTPDR_MASK -#define DDR_PHY_RDIMMGCR0_ERROUTPDR_DEFVAL 0x08400020 -#define DDR_PHY_RDIMMGCR0_ERROUTPDR_SHIFT 21 -#define DDR_PHY_RDIMMGCR0_ERROUTPDR_MASK 0x00200000U +#define DDR_PHY_RDIMMGCR0_ERROUTPDR_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_ERROUTPDR_SHIFT 21 +#define DDR_PHY_RDIMMGCR0_ERROUTPDR_MASK 0x00200000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_RDIMMGCR0_RESERVED_20_DEFVAL #undef DDR_PHY_RDIMMGCR0_RESERVED_20_SHIFT #undef DDR_PHY_RDIMMGCR0_RESERVED_20_MASK -#define DDR_PHY_RDIMMGCR0_RESERVED_20_DEFVAL 0x08400020 -#define DDR_PHY_RDIMMGCR0_RESERVED_20_SHIFT 20 -#define DDR_PHY_RDIMMGCR0_RESERVED_20_MASK 0x00100000U +#define DDR_PHY_RDIMMGCR0_RESERVED_20_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_RESERVED_20_SHIFT 20 +#define DDR_PHY_RDIMMGCR0_RESERVED_20_MASK 0x00100000U -/*ERROUT# On-Die Termination*/ +/* +* ERROUT# On-Die Termination +*/ #undef DDR_PHY_RDIMMGCR0_ERROUTODT_DEFVAL #undef DDR_PHY_RDIMMGCR0_ERROUTODT_SHIFT #undef DDR_PHY_RDIMMGCR0_ERROUTODT_MASK -#define DDR_PHY_RDIMMGCR0_ERROUTODT_DEFVAL 0x08400020 -#define DDR_PHY_RDIMMGCR0_ERROUTODT_SHIFT 19 -#define DDR_PHY_RDIMMGCR0_ERROUTODT_MASK 0x00080000U +#define DDR_PHY_RDIMMGCR0_ERROUTODT_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_ERROUTODT_SHIFT 19 +#define DDR_PHY_RDIMMGCR0_ERROUTODT_MASK 0x00080000U -/*Load Reduced DIMM*/ +/* +* Load Reduced DIMM +*/ #undef DDR_PHY_RDIMMGCR0_LRDIMM_DEFVAL #undef DDR_PHY_RDIMMGCR0_LRDIMM_SHIFT #undef DDR_PHY_RDIMMGCR0_LRDIMM_MASK -#define DDR_PHY_RDIMMGCR0_LRDIMM_DEFVAL 0x08400020 -#define DDR_PHY_RDIMMGCR0_LRDIMM_SHIFT 18 -#define DDR_PHY_RDIMMGCR0_LRDIMM_MASK 0x00040000U +#define DDR_PHY_RDIMMGCR0_LRDIMM_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_LRDIMM_SHIFT 18 +#define DDR_PHY_RDIMMGCR0_LRDIMM_MASK 0x00040000U -/*PAR_IN I/O Mode*/ +/* +* PAR_IN I/O Mode +*/ #undef DDR_PHY_RDIMMGCR0_PARINIOM_DEFVAL #undef DDR_PHY_RDIMMGCR0_PARINIOM_SHIFT #undef DDR_PHY_RDIMMGCR0_PARINIOM_MASK -#define DDR_PHY_RDIMMGCR0_PARINIOM_DEFVAL 0x08400020 -#define DDR_PHY_RDIMMGCR0_PARINIOM_SHIFT 17 -#define DDR_PHY_RDIMMGCR0_PARINIOM_MASK 0x00020000U +#define DDR_PHY_RDIMMGCR0_PARINIOM_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_PARINIOM_SHIFT 17 +#define DDR_PHY_RDIMMGCR0_PARINIOM_MASK 0x00020000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_RDIMMGCR0_RESERVED_16_8_DEFVAL #undef DDR_PHY_RDIMMGCR0_RESERVED_16_8_SHIFT #undef DDR_PHY_RDIMMGCR0_RESERVED_16_8_MASK -#define DDR_PHY_RDIMMGCR0_RESERVED_16_8_DEFVAL 0x08400020 -#define DDR_PHY_RDIMMGCR0_RESERVED_16_8_SHIFT 8 -#define DDR_PHY_RDIMMGCR0_RESERVED_16_8_MASK 0x0001FF00U +#define DDR_PHY_RDIMMGCR0_RESERVED_16_8_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_RESERVED_16_8_SHIFT 8 +#define DDR_PHY_RDIMMGCR0_RESERVED_16_8_MASK 0x0001FF00U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_DEFVAL #undef DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_SHIFT #undef DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_MASK -#define DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_DEFVAL 0x08400020 -#define DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_SHIFT 6 -#define DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_MASK 0x000000C0U +#define DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_SHIFT 6 +#define DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_MASK 0x000000C0U -/*Rank Mirror Enable.*/ +/* +* Rank Mirror Enable. +*/ #undef DDR_PHY_RDIMMGCR0_RNKMRREN_DEFVAL #undef DDR_PHY_RDIMMGCR0_RNKMRREN_SHIFT #undef DDR_PHY_RDIMMGCR0_RNKMRREN_MASK -#define DDR_PHY_RDIMMGCR0_RNKMRREN_DEFVAL 0x08400020 -#define DDR_PHY_RDIMMGCR0_RNKMRREN_SHIFT 4 -#define DDR_PHY_RDIMMGCR0_RNKMRREN_MASK 0x00000030U +#define DDR_PHY_RDIMMGCR0_RNKMRREN_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_RNKMRREN_SHIFT 4 +#define DDR_PHY_RDIMMGCR0_RNKMRREN_MASK 0x00000030U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_RDIMMGCR0_RESERVED_3_DEFVAL #undef DDR_PHY_RDIMMGCR0_RESERVED_3_SHIFT #undef DDR_PHY_RDIMMGCR0_RESERVED_3_MASK -#define DDR_PHY_RDIMMGCR0_RESERVED_3_DEFVAL 0x08400020 -#define DDR_PHY_RDIMMGCR0_RESERVED_3_SHIFT 3 -#define DDR_PHY_RDIMMGCR0_RESERVED_3_MASK 0x00000008U +#define DDR_PHY_RDIMMGCR0_RESERVED_3_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_RESERVED_3_SHIFT 3 +#define DDR_PHY_RDIMMGCR0_RESERVED_3_MASK 0x00000008U -/*Stop on Parity Error*/ +/* +* Stop on Parity Error +*/ #undef DDR_PHY_RDIMMGCR0_SOPERR_DEFVAL #undef DDR_PHY_RDIMMGCR0_SOPERR_SHIFT #undef DDR_PHY_RDIMMGCR0_SOPERR_MASK -#define DDR_PHY_RDIMMGCR0_SOPERR_DEFVAL 0x08400020 -#define DDR_PHY_RDIMMGCR0_SOPERR_SHIFT 2 -#define DDR_PHY_RDIMMGCR0_SOPERR_MASK 0x00000004U +#define DDR_PHY_RDIMMGCR0_SOPERR_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_SOPERR_SHIFT 2 +#define DDR_PHY_RDIMMGCR0_SOPERR_MASK 0x00000004U -/*Parity Error No Registering*/ +/* +* Parity Error No Registering +*/ #undef DDR_PHY_RDIMMGCR0_ERRNOREG_DEFVAL #undef DDR_PHY_RDIMMGCR0_ERRNOREG_SHIFT #undef DDR_PHY_RDIMMGCR0_ERRNOREG_MASK -#define DDR_PHY_RDIMMGCR0_ERRNOREG_DEFVAL 0x08400020 -#define DDR_PHY_RDIMMGCR0_ERRNOREG_SHIFT 1 -#define DDR_PHY_RDIMMGCR0_ERRNOREG_MASK 0x00000002U +#define DDR_PHY_RDIMMGCR0_ERRNOREG_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_ERRNOREG_SHIFT 1 +#define DDR_PHY_RDIMMGCR0_ERRNOREG_MASK 0x00000002U -/*Registered DIMM*/ +/* +* Registered DIMM +*/ #undef DDR_PHY_RDIMMGCR0_RDIMM_DEFVAL #undef DDR_PHY_RDIMMGCR0_RDIMM_SHIFT #undef DDR_PHY_RDIMMGCR0_RDIMM_MASK -#define DDR_PHY_RDIMMGCR0_RDIMM_DEFVAL 0x08400020 -#define DDR_PHY_RDIMMGCR0_RDIMM_SHIFT 0 -#define DDR_PHY_RDIMMGCR0_RDIMM_MASK 0x00000001U +#define DDR_PHY_RDIMMGCR0_RDIMM_DEFVAL 0x08400020 +#define DDR_PHY_RDIMMGCR0_RDIMM_SHIFT 0 +#define DDR_PHY_RDIMMGCR0_RDIMM_MASK 0x00000001U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_RDIMMGCR1_RESERVED_31_29_DEFVAL #undef DDR_PHY_RDIMMGCR1_RESERVED_31_29_SHIFT #undef DDR_PHY_RDIMMGCR1_RESERVED_31_29_MASK -#define DDR_PHY_RDIMMGCR1_RESERVED_31_29_DEFVAL 0x00000C80 -#define DDR_PHY_RDIMMGCR1_RESERVED_31_29_SHIFT 29 -#define DDR_PHY_RDIMMGCR1_RESERVED_31_29_MASK 0xE0000000U +#define DDR_PHY_RDIMMGCR1_RESERVED_31_29_DEFVAL 0x00000C80 +#define DDR_PHY_RDIMMGCR1_RESERVED_31_29_SHIFT 29 +#define DDR_PHY_RDIMMGCR1_RESERVED_31_29_MASK 0xE0000000U -/*Address [17] B-side Inversion Disable*/ +/* +* Address [17] B-side Inversion Disable +*/ #undef DDR_PHY_RDIMMGCR1_A17BID_DEFVAL #undef DDR_PHY_RDIMMGCR1_A17BID_SHIFT #undef DDR_PHY_RDIMMGCR1_A17BID_MASK -#define DDR_PHY_RDIMMGCR1_A17BID_DEFVAL 0x00000C80 -#define DDR_PHY_RDIMMGCR1_A17BID_SHIFT 28 -#define DDR_PHY_RDIMMGCR1_A17BID_MASK 0x10000000U +#define DDR_PHY_RDIMMGCR1_A17BID_DEFVAL 0x00000C80 +#define DDR_PHY_RDIMMGCR1_A17BID_SHIFT 28 +#define DDR_PHY_RDIMMGCR1_A17BID_MASK 0x10000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_RDIMMGCR1_RESERVED_27_DEFVAL #undef DDR_PHY_RDIMMGCR1_RESERVED_27_SHIFT #undef DDR_PHY_RDIMMGCR1_RESERVED_27_MASK -#define DDR_PHY_RDIMMGCR1_RESERVED_27_DEFVAL 0x00000C80 -#define DDR_PHY_RDIMMGCR1_RESERVED_27_SHIFT 27 -#define DDR_PHY_RDIMMGCR1_RESERVED_27_MASK 0x08000000U +#define DDR_PHY_RDIMMGCR1_RESERVED_27_DEFVAL 0x00000C80 +#define DDR_PHY_RDIMMGCR1_RESERVED_27_SHIFT 27 +#define DDR_PHY_RDIMMGCR1_RESERVED_27_MASK 0x08000000U -/*Command word to command word programming delay*/ +/* +* Command word to command word programming delay +*/ #undef DDR_PHY_RDIMMGCR1_TBCMRD_L2_DEFVAL #undef DDR_PHY_RDIMMGCR1_TBCMRD_L2_SHIFT #undef DDR_PHY_RDIMMGCR1_TBCMRD_L2_MASK -#define DDR_PHY_RDIMMGCR1_TBCMRD_L2_DEFVAL 0x00000C80 -#define DDR_PHY_RDIMMGCR1_TBCMRD_L2_SHIFT 24 -#define DDR_PHY_RDIMMGCR1_TBCMRD_L2_MASK 0x07000000U +#define DDR_PHY_RDIMMGCR1_TBCMRD_L2_DEFVAL 0x00000C80 +#define DDR_PHY_RDIMMGCR1_TBCMRD_L2_SHIFT 24 +#define DDR_PHY_RDIMMGCR1_TBCMRD_L2_MASK 0x07000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_RDIMMGCR1_RESERVED_23_DEFVAL #undef DDR_PHY_RDIMMGCR1_RESERVED_23_SHIFT #undef DDR_PHY_RDIMMGCR1_RESERVED_23_MASK -#define DDR_PHY_RDIMMGCR1_RESERVED_23_DEFVAL 0x00000C80 -#define DDR_PHY_RDIMMGCR1_RESERVED_23_SHIFT 23 -#define DDR_PHY_RDIMMGCR1_RESERVED_23_MASK 0x00800000U +#define DDR_PHY_RDIMMGCR1_RESERVED_23_DEFVAL 0x00000C80 +#define DDR_PHY_RDIMMGCR1_RESERVED_23_SHIFT 23 +#define DDR_PHY_RDIMMGCR1_RESERVED_23_MASK 0x00800000U -/*Command word to command word programming delay*/ +/* +* Command word to command word programming delay +*/ #undef DDR_PHY_RDIMMGCR1_TBCMRD_L_DEFVAL #undef DDR_PHY_RDIMMGCR1_TBCMRD_L_SHIFT #undef DDR_PHY_RDIMMGCR1_TBCMRD_L_MASK -#define DDR_PHY_RDIMMGCR1_TBCMRD_L_DEFVAL 0x00000C80 -#define DDR_PHY_RDIMMGCR1_TBCMRD_L_SHIFT 20 -#define DDR_PHY_RDIMMGCR1_TBCMRD_L_MASK 0x00700000U +#define DDR_PHY_RDIMMGCR1_TBCMRD_L_DEFVAL 0x00000C80 +#define DDR_PHY_RDIMMGCR1_TBCMRD_L_SHIFT 20 +#define DDR_PHY_RDIMMGCR1_TBCMRD_L_MASK 0x00700000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_RDIMMGCR1_RESERVED_19_DEFVAL #undef DDR_PHY_RDIMMGCR1_RESERVED_19_SHIFT #undef DDR_PHY_RDIMMGCR1_RESERVED_19_MASK -#define DDR_PHY_RDIMMGCR1_RESERVED_19_DEFVAL 0x00000C80 -#define DDR_PHY_RDIMMGCR1_RESERVED_19_SHIFT 19 -#define DDR_PHY_RDIMMGCR1_RESERVED_19_MASK 0x00080000U +#define DDR_PHY_RDIMMGCR1_RESERVED_19_DEFVAL 0x00000C80 +#define DDR_PHY_RDIMMGCR1_RESERVED_19_SHIFT 19 +#define DDR_PHY_RDIMMGCR1_RESERVED_19_MASK 0x00080000U -/*Command word to command word programming delay*/ +/* +* Command word to command word programming delay +*/ #undef DDR_PHY_RDIMMGCR1_TBCMRD_DEFVAL #undef DDR_PHY_RDIMMGCR1_TBCMRD_SHIFT #undef DDR_PHY_RDIMMGCR1_TBCMRD_MASK -#define DDR_PHY_RDIMMGCR1_TBCMRD_DEFVAL 0x00000C80 -#define DDR_PHY_RDIMMGCR1_TBCMRD_SHIFT 16 -#define DDR_PHY_RDIMMGCR1_TBCMRD_MASK 0x00070000U +#define DDR_PHY_RDIMMGCR1_TBCMRD_DEFVAL 0x00000C80 +#define DDR_PHY_RDIMMGCR1_TBCMRD_SHIFT 16 +#define DDR_PHY_RDIMMGCR1_TBCMRD_MASK 0x00070000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_RDIMMGCR1_RESERVED_15_14_DEFVAL #undef DDR_PHY_RDIMMGCR1_RESERVED_15_14_SHIFT #undef DDR_PHY_RDIMMGCR1_RESERVED_15_14_MASK -#define DDR_PHY_RDIMMGCR1_RESERVED_15_14_DEFVAL 0x00000C80 -#define DDR_PHY_RDIMMGCR1_RESERVED_15_14_SHIFT 14 -#define DDR_PHY_RDIMMGCR1_RESERVED_15_14_MASK 0x0000C000U +#define DDR_PHY_RDIMMGCR1_RESERVED_15_14_DEFVAL 0x00000C80 +#define DDR_PHY_RDIMMGCR1_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_RDIMMGCR1_RESERVED_15_14_MASK 0x0000C000U -/*Stabilization time*/ +/* +* Stabilization time +*/ #undef DDR_PHY_RDIMMGCR1_TBCSTAB_DEFVAL #undef DDR_PHY_RDIMMGCR1_TBCSTAB_SHIFT #undef DDR_PHY_RDIMMGCR1_TBCSTAB_MASK -#define DDR_PHY_RDIMMGCR1_TBCSTAB_DEFVAL 0x00000C80 -#define DDR_PHY_RDIMMGCR1_TBCSTAB_SHIFT 0 -#define DDR_PHY_RDIMMGCR1_TBCSTAB_MASK 0x00003FFFU +#define DDR_PHY_RDIMMGCR1_TBCSTAB_DEFVAL 0x00000C80 +#define DDR_PHY_RDIMMGCR1_TBCSTAB_SHIFT 0 +#define DDR_PHY_RDIMMGCR1_TBCSTAB_MASK 0x00003FFFU -/*DDR4/DDR3 Control Word 7*/ +/* +* DDR4/DDR3 Control Word 7 +*/ #undef DDR_PHY_RDIMMCR0_RC7_DEFVAL #undef DDR_PHY_RDIMMCR0_RC7_SHIFT #undef DDR_PHY_RDIMMCR0_RC7_MASK -#define DDR_PHY_RDIMMCR0_RC7_DEFVAL 0x00000000 -#define DDR_PHY_RDIMMCR0_RC7_SHIFT 28 -#define DDR_PHY_RDIMMCR0_RC7_MASK 0xF0000000U +#define DDR_PHY_RDIMMCR0_RC7_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR0_RC7_SHIFT 28 +#define DDR_PHY_RDIMMCR0_RC7_MASK 0xF0000000U -/*DDR4 Control Word 6 (Comman space Control Word) / DDR3 Reserved*/ +/* +* DDR4 Control Word 6 (Comman space Control Word) / DDR3 Reserved +*/ #undef DDR_PHY_RDIMMCR0_RC6_DEFVAL #undef DDR_PHY_RDIMMCR0_RC6_SHIFT #undef DDR_PHY_RDIMMCR0_RC6_MASK -#define DDR_PHY_RDIMMCR0_RC6_DEFVAL 0x00000000 -#define DDR_PHY_RDIMMCR0_RC6_SHIFT 24 -#define DDR_PHY_RDIMMCR0_RC6_MASK 0x0F000000U +#define DDR_PHY_RDIMMCR0_RC6_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR0_RC6_SHIFT 24 +#define DDR_PHY_RDIMMCR0_RC6_MASK 0x0F000000U -/*DDR4/DDR3 Control Word 5 (CK Driver Characteristics Control Word)*/ +/* +* DDR4/DDR3 Control Word 5 (CK Driver Characteristics Control Word) +*/ #undef DDR_PHY_RDIMMCR0_RC5_DEFVAL #undef DDR_PHY_RDIMMCR0_RC5_SHIFT #undef DDR_PHY_RDIMMCR0_RC5_MASK -#define DDR_PHY_RDIMMCR0_RC5_DEFVAL 0x00000000 -#define DDR_PHY_RDIMMCR0_RC5_SHIFT 20 -#define DDR_PHY_RDIMMCR0_RC5_MASK 0x00F00000U +#define DDR_PHY_RDIMMCR0_RC5_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR0_RC5_SHIFT 20 +#define DDR_PHY_RDIMMCR0_RC5_MASK 0x00F00000U -/*DDR4 Control Word 4 (ODT and CKE Signals Driver Characteristics Control Word) / DDR3 Control Word 4 (Control Signals Driver C - aracteristics Control Word)*/ +/* +* DDR4 Control Word 4 (ODT and CKE Signals Driver Characteristics Control + * Word) / DDR3 Control Word 4 (Control Signals Driver Characteristics Cont + * rol Word) +*/ #undef DDR_PHY_RDIMMCR0_RC4_DEFVAL #undef DDR_PHY_RDIMMCR0_RC4_SHIFT #undef DDR_PHY_RDIMMCR0_RC4_MASK -#define DDR_PHY_RDIMMCR0_RC4_DEFVAL 0x00000000 -#define DDR_PHY_RDIMMCR0_RC4_SHIFT 16 -#define DDR_PHY_RDIMMCR0_RC4_MASK 0x000F0000U +#define DDR_PHY_RDIMMCR0_RC4_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR0_RC4_SHIFT 16 +#define DDR_PHY_RDIMMCR0_RC4_MASK 0x000F0000U -/*DDR4 Control Word 3 (CA and CS Signals Driver Characteristics Control Word) / DDR3 Control Word 3 (Command/Address Signals Dr - ver Characteristrics Control Word)*/ +/* +* DDR4 Control Word 3 (CA and CS Signals Driver Characteristics Control Wo + * rd) / DDR3 Control Word 3 (Command/Address Signals Driver Characteristri + * cs Control Word) +*/ #undef DDR_PHY_RDIMMCR0_RC3_DEFVAL #undef DDR_PHY_RDIMMCR0_RC3_SHIFT #undef DDR_PHY_RDIMMCR0_RC3_MASK -#define DDR_PHY_RDIMMCR0_RC3_DEFVAL 0x00000000 -#define DDR_PHY_RDIMMCR0_RC3_SHIFT 12 -#define DDR_PHY_RDIMMCR0_RC3_MASK 0x0000F000U +#define DDR_PHY_RDIMMCR0_RC3_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR0_RC3_SHIFT 12 +#define DDR_PHY_RDIMMCR0_RC3_MASK 0x0000F000U -/*DDR4 Control Word 2 (Timing and IBT Control Word) / DDR3 Control Word 2 (Timing Control Word)*/ +/* +* DDR4 Control Word 2 (Timing and IBT Control Word) / DDR3 Control Word 2 + * (Timing Control Word) +*/ #undef DDR_PHY_RDIMMCR0_RC2_DEFVAL #undef DDR_PHY_RDIMMCR0_RC2_SHIFT #undef DDR_PHY_RDIMMCR0_RC2_MASK -#define DDR_PHY_RDIMMCR0_RC2_DEFVAL 0x00000000 -#define DDR_PHY_RDIMMCR0_RC2_SHIFT 8 -#define DDR_PHY_RDIMMCR0_RC2_MASK 0x00000F00U +#define DDR_PHY_RDIMMCR0_RC2_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR0_RC2_SHIFT 8 +#define DDR_PHY_RDIMMCR0_RC2_MASK 0x00000F00U -/*DDR4/DDR3 Control Word 1 (Clock Driver Enable Control Word)*/ +/* +* DDR4/DDR3 Control Word 1 (Clock Driver Enable Control Word) +*/ #undef DDR_PHY_RDIMMCR0_RC1_DEFVAL #undef DDR_PHY_RDIMMCR0_RC1_SHIFT #undef DDR_PHY_RDIMMCR0_RC1_MASK -#define DDR_PHY_RDIMMCR0_RC1_DEFVAL 0x00000000 -#define DDR_PHY_RDIMMCR0_RC1_SHIFT 4 -#define DDR_PHY_RDIMMCR0_RC1_MASK 0x000000F0U +#define DDR_PHY_RDIMMCR0_RC1_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR0_RC1_SHIFT 4 +#define DDR_PHY_RDIMMCR0_RC1_MASK 0x000000F0U -/*DDR4/DDR3 Control Word 0 (Global Features Control Word)*/ +/* +* DDR4/DDR3 Control Word 0 (Global Features Control Word) +*/ #undef DDR_PHY_RDIMMCR0_RC0_DEFVAL #undef DDR_PHY_RDIMMCR0_RC0_SHIFT #undef DDR_PHY_RDIMMCR0_RC0_MASK -#define DDR_PHY_RDIMMCR0_RC0_DEFVAL 0x00000000 -#define DDR_PHY_RDIMMCR0_RC0_SHIFT 0 -#define DDR_PHY_RDIMMCR0_RC0_MASK 0x0000000FU +#define DDR_PHY_RDIMMCR0_RC0_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR0_RC0_SHIFT 0 +#define DDR_PHY_RDIMMCR0_RC0_MASK 0x0000000FU -/*Control Word 15*/ +/* +* Control Word 15 +*/ #undef DDR_PHY_RDIMMCR1_RC15_DEFVAL #undef DDR_PHY_RDIMMCR1_RC15_SHIFT #undef DDR_PHY_RDIMMCR1_RC15_MASK -#define DDR_PHY_RDIMMCR1_RC15_DEFVAL 0x00000000 -#define DDR_PHY_RDIMMCR1_RC15_SHIFT 28 -#define DDR_PHY_RDIMMCR1_RC15_MASK 0xF0000000U +#define DDR_PHY_RDIMMCR1_RC15_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR1_RC15_SHIFT 28 +#define DDR_PHY_RDIMMCR1_RC15_MASK 0xF0000000U -/*DDR4 Control Word 14 (Parity Control Word) / DDR3 Reserved*/ +/* +* DDR4 Control Word 14 (Parity Control Word) / DDR3 Reserved +*/ #undef DDR_PHY_RDIMMCR1_RC14_DEFVAL #undef DDR_PHY_RDIMMCR1_RC14_SHIFT #undef DDR_PHY_RDIMMCR1_RC14_MASK -#define DDR_PHY_RDIMMCR1_RC14_DEFVAL 0x00000000 -#define DDR_PHY_RDIMMCR1_RC14_SHIFT 24 -#define DDR_PHY_RDIMMCR1_RC14_MASK 0x0F000000U +#define DDR_PHY_RDIMMCR1_RC14_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR1_RC14_SHIFT 24 +#define DDR_PHY_RDIMMCR1_RC14_MASK 0x0F000000U -/*DDR4 Control Word 13 (DIMM Configuration Control Word) / DDR3 Reserved*/ +/* +* DDR4 Control Word 13 (DIMM Configuration Control Word) / DDR3 Reserved +*/ #undef DDR_PHY_RDIMMCR1_RC13_DEFVAL #undef DDR_PHY_RDIMMCR1_RC13_SHIFT #undef DDR_PHY_RDIMMCR1_RC13_MASK -#define DDR_PHY_RDIMMCR1_RC13_DEFVAL 0x00000000 -#define DDR_PHY_RDIMMCR1_RC13_SHIFT 20 -#define DDR_PHY_RDIMMCR1_RC13_MASK 0x00F00000U +#define DDR_PHY_RDIMMCR1_RC13_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR1_RC13_SHIFT 20 +#define DDR_PHY_RDIMMCR1_RC13_MASK 0x00F00000U -/*DDR4 Control Word 12 (Training Control Word) / DDR3 Reserved*/ +/* +* DDR4 Control Word 12 (Training Control Word) / DDR3 Reserved +*/ #undef DDR_PHY_RDIMMCR1_RC12_DEFVAL #undef DDR_PHY_RDIMMCR1_RC12_SHIFT #undef DDR_PHY_RDIMMCR1_RC12_MASK -#define DDR_PHY_RDIMMCR1_RC12_DEFVAL 0x00000000 -#define DDR_PHY_RDIMMCR1_RC12_SHIFT 16 -#define DDR_PHY_RDIMMCR1_RC12_MASK 0x000F0000U +#define DDR_PHY_RDIMMCR1_RC12_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR1_RC12_SHIFT 16 +#define DDR_PHY_RDIMMCR1_RC12_MASK 0x000F0000U -/*DDR4 Control Word 11 (Operating Voltage VDD and VREFCA Source Control Word) / DDR3 Control Word 11 (Operation Voltage VDD Con - rol Word)*/ +/* +* DDR4 Control Word 11 (Operating Voltage VDD and VREFCA Source Control Wo + * rd) / DDR3 Control Word 11 (Operation Voltage VDD Control Word) +*/ #undef DDR_PHY_RDIMMCR1_RC11_DEFVAL #undef DDR_PHY_RDIMMCR1_RC11_SHIFT #undef DDR_PHY_RDIMMCR1_RC11_MASK -#define DDR_PHY_RDIMMCR1_RC11_DEFVAL 0x00000000 -#define DDR_PHY_RDIMMCR1_RC11_SHIFT 12 -#define DDR_PHY_RDIMMCR1_RC11_MASK 0x0000F000U +#define DDR_PHY_RDIMMCR1_RC11_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR1_RC11_SHIFT 12 +#define DDR_PHY_RDIMMCR1_RC11_MASK 0x0000F000U -/*DDR4/DDR3 Control Word 10 (RDIMM Operating Speed Control Word)*/ +/* +* DDR4/DDR3 Control Word 10 (RDIMM Operating Speed Control Word) +*/ #undef DDR_PHY_RDIMMCR1_RC10_DEFVAL #undef DDR_PHY_RDIMMCR1_RC10_SHIFT #undef DDR_PHY_RDIMMCR1_RC10_MASK -#define DDR_PHY_RDIMMCR1_RC10_DEFVAL 0x00000000 -#define DDR_PHY_RDIMMCR1_RC10_SHIFT 8 -#define DDR_PHY_RDIMMCR1_RC10_MASK 0x00000F00U +#define DDR_PHY_RDIMMCR1_RC10_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR1_RC10_SHIFT 8 +#define DDR_PHY_RDIMMCR1_RC10_MASK 0x00000F00U -/*DDR4/DDR3 Control Word 9 (Power Saving Settings Control Word)*/ +/* +* DDR4/DDR3 Control Word 9 (Power Saving Settings Control Word) +*/ #undef DDR_PHY_RDIMMCR1_RC9_DEFVAL #undef DDR_PHY_RDIMMCR1_RC9_SHIFT #undef DDR_PHY_RDIMMCR1_RC9_MASK -#define DDR_PHY_RDIMMCR1_RC9_DEFVAL 0x00000000 -#define DDR_PHY_RDIMMCR1_RC9_SHIFT 4 -#define DDR_PHY_RDIMMCR1_RC9_MASK 0x000000F0U +#define DDR_PHY_RDIMMCR1_RC9_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR1_RC9_SHIFT 4 +#define DDR_PHY_RDIMMCR1_RC9_MASK 0x000000F0U -/*DDR4 Control Word 8 (Input/Output Configuration Control Word) / DDR3 Control Word 8 (Additional Input Bus Termination Setting - Control Word)*/ +/* +* DDR4 Control Word 8 (Input/Output Configuration Control Word) / DDR3 Con + * trol Word 8 (Additional Input Bus Termination Setting Control Word) +*/ #undef DDR_PHY_RDIMMCR1_RC8_DEFVAL #undef DDR_PHY_RDIMMCR1_RC8_SHIFT #undef DDR_PHY_RDIMMCR1_RC8_MASK -#define DDR_PHY_RDIMMCR1_RC8_DEFVAL 0x00000000 -#define DDR_PHY_RDIMMCR1_RC8_SHIFT 0 -#define DDR_PHY_RDIMMCR1_RC8_MASK 0x0000000FU +#define DDR_PHY_RDIMMCR1_RC8_DEFVAL 0x00000000 +#define DDR_PHY_RDIMMCR1_RC8_SHIFT 0 +#define DDR_PHY_RDIMMCR1_RC8_MASK 0x0000000FU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_MR0_RESERVED_31_8_DEFVAL #undef DDR_PHY_MR0_RESERVED_31_8_SHIFT #undef DDR_PHY_MR0_RESERVED_31_8_MASK -#define DDR_PHY_MR0_RESERVED_31_8_DEFVAL 0x00000052 -#define DDR_PHY_MR0_RESERVED_31_8_SHIFT 8 -#define DDR_PHY_MR0_RESERVED_31_8_MASK 0xFFFFFF00U +#define DDR_PHY_MR0_RESERVED_31_8_DEFVAL 0x00000052 +#define DDR_PHY_MR0_RESERVED_31_8_SHIFT 8 +#define DDR_PHY_MR0_RESERVED_31_8_MASK 0xFFFFFF00U -/*CA Terminating Rank*/ +/* +* CA Terminating Rank +*/ #undef DDR_PHY_MR0_CATR_DEFVAL #undef DDR_PHY_MR0_CATR_SHIFT #undef DDR_PHY_MR0_CATR_MASK -#define DDR_PHY_MR0_CATR_DEFVAL 0x00000052 -#define DDR_PHY_MR0_CATR_SHIFT 7 -#define DDR_PHY_MR0_CATR_MASK 0x00000080U +#define DDR_PHY_MR0_CATR_DEFVAL 0x00000052 +#define DDR_PHY_MR0_CATR_SHIFT 7 +#define DDR_PHY_MR0_CATR_MASK 0x00000080U -/*Reserved. These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/ +/* +* Reserved. These are JEDEC reserved bits and are recommended by JEDEC to + * be programmed to 0x0. +*/ #undef DDR_PHY_MR0_RSVD_6_5_DEFVAL #undef DDR_PHY_MR0_RSVD_6_5_SHIFT #undef DDR_PHY_MR0_RSVD_6_5_MASK -#define DDR_PHY_MR0_RSVD_6_5_DEFVAL 0x00000052 -#define DDR_PHY_MR0_RSVD_6_5_SHIFT 5 -#define DDR_PHY_MR0_RSVD_6_5_MASK 0x00000060U +#define DDR_PHY_MR0_RSVD_6_5_DEFVAL 0x00000052 +#define DDR_PHY_MR0_RSVD_6_5_SHIFT 5 +#define DDR_PHY_MR0_RSVD_6_5_MASK 0x00000060U -/*Built-in Self-Test for RZQ*/ +/* +* Built-in Self-Test for RZQ +*/ #undef DDR_PHY_MR0_RZQI_DEFVAL #undef DDR_PHY_MR0_RZQI_SHIFT #undef DDR_PHY_MR0_RZQI_MASK -#define DDR_PHY_MR0_RZQI_DEFVAL 0x00000052 -#define DDR_PHY_MR0_RZQI_SHIFT 3 -#define DDR_PHY_MR0_RZQI_MASK 0x00000018U +#define DDR_PHY_MR0_RZQI_DEFVAL 0x00000052 +#define DDR_PHY_MR0_RZQI_SHIFT 3 +#define DDR_PHY_MR0_RZQI_MASK 0x00000018U -/*Reserved. These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/ +/* +* Reserved. These are JEDEC reserved bits and are recommended by JEDEC to + * be programmed to 0x0. +*/ #undef DDR_PHY_MR0_RSVD_2_0_DEFVAL #undef DDR_PHY_MR0_RSVD_2_0_SHIFT #undef DDR_PHY_MR0_RSVD_2_0_MASK -#define DDR_PHY_MR0_RSVD_2_0_DEFVAL 0x00000052 -#define DDR_PHY_MR0_RSVD_2_0_SHIFT 0 -#define DDR_PHY_MR0_RSVD_2_0_MASK 0x00000007U +#define DDR_PHY_MR0_RSVD_2_0_DEFVAL 0x00000052 +#define DDR_PHY_MR0_RSVD_2_0_SHIFT 0 +#define DDR_PHY_MR0_RSVD_2_0_MASK 0x00000007U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_MR1_RESERVED_31_8_DEFVAL #undef DDR_PHY_MR1_RESERVED_31_8_SHIFT #undef DDR_PHY_MR1_RESERVED_31_8_MASK -#define DDR_PHY_MR1_RESERVED_31_8_DEFVAL 0x00000004 -#define DDR_PHY_MR1_RESERVED_31_8_SHIFT 8 -#define DDR_PHY_MR1_RESERVED_31_8_MASK 0xFFFFFF00U +#define DDR_PHY_MR1_RESERVED_31_8_DEFVAL 0x00000004 +#define DDR_PHY_MR1_RESERVED_31_8_SHIFT 8 +#define DDR_PHY_MR1_RESERVED_31_8_MASK 0xFFFFFF00U -/*Read Postamble Length*/ +/* +* Read Postamble Length +*/ #undef DDR_PHY_MR1_RDPST_DEFVAL #undef DDR_PHY_MR1_RDPST_SHIFT #undef DDR_PHY_MR1_RDPST_MASK -#define DDR_PHY_MR1_RDPST_DEFVAL 0x00000004 -#define DDR_PHY_MR1_RDPST_SHIFT 7 -#define DDR_PHY_MR1_RDPST_MASK 0x00000080U +#define DDR_PHY_MR1_RDPST_DEFVAL 0x00000004 +#define DDR_PHY_MR1_RDPST_SHIFT 7 +#define DDR_PHY_MR1_RDPST_MASK 0x00000080U -/*Write-recovery for auto-precharge command*/ +/* +* Write-recovery for auto-precharge command +*/ #undef DDR_PHY_MR1_NWR_DEFVAL #undef DDR_PHY_MR1_NWR_SHIFT #undef DDR_PHY_MR1_NWR_MASK -#define DDR_PHY_MR1_NWR_DEFVAL 0x00000004 -#define DDR_PHY_MR1_NWR_SHIFT 4 -#define DDR_PHY_MR1_NWR_MASK 0x00000070U +#define DDR_PHY_MR1_NWR_DEFVAL 0x00000004 +#define DDR_PHY_MR1_NWR_SHIFT 4 +#define DDR_PHY_MR1_NWR_MASK 0x00000070U -/*Read Preamble Length*/ +/* +* Read Preamble Length +*/ #undef DDR_PHY_MR1_RDPRE_DEFVAL #undef DDR_PHY_MR1_RDPRE_SHIFT #undef DDR_PHY_MR1_RDPRE_MASK -#define DDR_PHY_MR1_RDPRE_DEFVAL 0x00000004 -#define DDR_PHY_MR1_RDPRE_SHIFT 3 -#define DDR_PHY_MR1_RDPRE_MASK 0x00000008U +#define DDR_PHY_MR1_RDPRE_DEFVAL 0x00000004 +#define DDR_PHY_MR1_RDPRE_SHIFT 3 +#define DDR_PHY_MR1_RDPRE_MASK 0x00000008U -/*Write Preamble Length*/ +/* +* Write Preamble Length +*/ #undef DDR_PHY_MR1_WRPRE_DEFVAL #undef DDR_PHY_MR1_WRPRE_SHIFT #undef DDR_PHY_MR1_WRPRE_MASK -#define DDR_PHY_MR1_WRPRE_DEFVAL 0x00000004 -#define DDR_PHY_MR1_WRPRE_SHIFT 2 -#define DDR_PHY_MR1_WRPRE_MASK 0x00000004U +#define DDR_PHY_MR1_WRPRE_DEFVAL 0x00000004 +#define DDR_PHY_MR1_WRPRE_SHIFT 2 +#define DDR_PHY_MR1_WRPRE_MASK 0x00000004U -/*Burst Length*/ +/* +* Burst Length +*/ #undef DDR_PHY_MR1_BL_DEFVAL #undef DDR_PHY_MR1_BL_SHIFT #undef DDR_PHY_MR1_BL_MASK -#define DDR_PHY_MR1_BL_DEFVAL 0x00000004 -#define DDR_PHY_MR1_BL_SHIFT 0 -#define DDR_PHY_MR1_BL_MASK 0x00000003U +#define DDR_PHY_MR1_BL_DEFVAL 0x00000004 +#define DDR_PHY_MR1_BL_SHIFT 0 +#define DDR_PHY_MR1_BL_MASK 0x00000003U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_MR2_RESERVED_31_8_DEFVAL #undef DDR_PHY_MR2_RESERVED_31_8_SHIFT #undef DDR_PHY_MR2_RESERVED_31_8_MASK -#define DDR_PHY_MR2_RESERVED_31_8_DEFVAL 0x00000000 -#define DDR_PHY_MR2_RESERVED_31_8_SHIFT 8 -#define DDR_PHY_MR2_RESERVED_31_8_MASK 0xFFFFFF00U +#define DDR_PHY_MR2_RESERVED_31_8_DEFVAL 0x00000000 +#define DDR_PHY_MR2_RESERVED_31_8_SHIFT 8 +#define DDR_PHY_MR2_RESERVED_31_8_MASK 0xFFFFFF00U -/*Write Leveling*/ +/* +* Write Leveling +*/ #undef DDR_PHY_MR2_WRL_DEFVAL #undef DDR_PHY_MR2_WRL_SHIFT #undef DDR_PHY_MR2_WRL_MASK -#define DDR_PHY_MR2_WRL_DEFVAL 0x00000000 -#define DDR_PHY_MR2_WRL_SHIFT 7 -#define DDR_PHY_MR2_WRL_MASK 0x00000080U +#define DDR_PHY_MR2_WRL_DEFVAL 0x00000000 +#define DDR_PHY_MR2_WRL_SHIFT 7 +#define DDR_PHY_MR2_WRL_MASK 0x00000080U -/*Write Latency Set*/ +/* +* Write Latency Set +*/ #undef DDR_PHY_MR2_WLS_DEFVAL #undef DDR_PHY_MR2_WLS_SHIFT #undef DDR_PHY_MR2_WLS_MASK -#define DDR_PHY_MR2_WLS_DEFVAL 0x00000000 -#define DDR_PHY_MR2_WLS_SHIFT 6 -#define DDR_PHY_MR2_WLS_MASK 0x00000040U +#define DDR_PHY_MR2_WLS_DEFVAL 0x00000000 +#define DDR_PHY_MR2_WLS_SHIFT 6 +#define DDR_PHY_MR2_WLS_MASK 0x00000040U -/*Write Latency*/ +/* +* Write Latency +*/ #undef DDR_PHY_MR2_WL_DEFVAL #undef DDR_PHY_MR2_WL_SHIFT #undef DDR_PHY_MR2_WL_MASK -#define DDR_PHY_MR2_WL_DEFVAL 0x00000000 -#define DDR_PHY_MR2_WL_SHIFT 3 -#define DDR_PHY_MR2_WL_MASK 0x00000038U +#define DDR_PHY_MR2_WL_DEFVAL 0x00000000 +#define DDR_PHY_MR2_WL_SHIFT 3 +#define DDR_PHY_MR2_WL_MASK 0x00000038U -/*Read Latency*/ +/* +* Read Latency +*/ #undef DDR_PHY_MR2_RL_DEFVAL #undef DDR_PHY_MR2_RL_SHIFT #undef DDR_PHY_MR2_RL_MASK -#define DDR_PHY_MR2_RL_DEFVAL 0x00000000 -#define DDR_PHY_MR2_RL_SHIFT 0 -#define DDR_PHY_MR2_RL_MASK 0x00000007U +#define DDR_PHY_MR2_RL_DEFVAL 0x00000000 +#define DDR_PHY_MR2_RL_SHIFT 0 +#define DDR_PHY_MR2_RL_MASK 0x00000007U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_MR3_RESERVED_31_8_DEFVAL #undef DDR_PHY_MR3_RESERVED_31_8_SHIFT #undef DDR_PHY_MR3_RESERVED_31_8_MASK -#define DDR_PHY_MR3_RESERVED_31_8_DEFVAL 0x00000031 -#define DDR_PHY_MR3_RESERVED_31_8_SHIFT 8 -#define DDR_PHY_MR3_RESERVED_31_8_MASK 0xFFFFFF00U +#define DDR_PHY_MR3_RESERVED_31_8_DEFVAL 0x00000031 +#define DDR_PHY_MR3_RESERVED_31_8_SHIFT 8 +#define DDR_PHY_MR3_RESERVED_31_8_MASK 0xFFFFFF00U -/*DBI-Write Enable*/ +/* +* DBI-Write Enable +*/ #undef DDR_PHY_MR3_DBIWR_DEFVAL #undef DDR_PHY_MR3_DBIWR_SHIFT #undef DDR_PHY_MR3_DBIWR_MASK -#define DDR_PHY_MR3_DBIWR_DEFVAL 0x00000031 -#define DDR_PHY_MR3_DBIWR_SHIFT 7 -#define DDR_PHY_MR3_DBIWR_MASK 0x00000080U +#define DDR_PHY_MR3_DBIWR_DEFVAL 0x00000031 +#define DDR_PHY_MR3_DBIWR_SHIFT 7 +#define DDR_PHY_MR3_DBIWR_MASK 0x00000080U -/*DBI-Read Enable*/ +/* +* DBI-Read Enable +*/ #undef DDR_PHY_MR3_DBIRD_DEFVAL #undef DDR_PHY_MR3_DBIRD_SHIFT #undef DDR_PHY_MR3_DBIRD_MASK -#define DDR_PHY_MR3_DBIRD_DEFVAL 0x00000031 -#define DDR_PHY_MR3_DBIRD_SHIFT 6 -#define DDR_PHY_MR3_DBIRD_MASK 0x00000040U +#define DDR_PHY_MR3_DBIRD_DEFVAL 0x00000031 +#define DDR_PHY_MR3_DBIRD_SHIFT 6 +#define DDR_PHY_MR3_DBIRD_MASK 0x00000040U -/*Pull-down Drive Strength*/ +/* +* Pull-down Drive Strength +*/ #undef DDR_PHY_MR3_PDDS_DEFVAL #undef DDR_PHY_MR3_PDDS_SHIFT #undef DDR_PHY_MR3_PDDS_MASK -#define DDR_PHY_MR3_PDDS_DEFVAL 0x00000031 -#define DDR_PHY_MR3_PDDS_SHIFT 3 -#define DDR_PHY_MR3_PDDS_MASK 0x00000038U +#define DDR_PHY_MR3_PDDS_DEFVAL 0x00000031 +#define DDR_PHY_MR3_PDDS_SHIFT 3 +#define DDR_PHY_MR3_PDDS_MASK 0x00000038U -/*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/ +/* +* These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. +*/ #undef DDR_PHY_MR3_RSVD_DEFVAL #undef DDR_PHY_MR3_RSVD_SHIFT #undef DDR_PHY_MR3_RSVD_MASK -#define DDR_PHY_MR3_RSVD_DEFVAL 0x00000031 -#define DDR_PHY_MR3_RSVD_SHIFT 2 -#define DDR_PHY_MR3_RSVD_MASK 0x00000004U +#define DDR_PHY_MR3_RSVD_DEFVAL 0x00000031 +#define DDR_PHY_MR3_RSVD_SHIFT 2 +#define DDR_PHY_MR3_RSVD_MASK 0x00000004U -/*Write Postamble Length*/ +/* +* Write Postamble Length +*/ #undef DDR_PHY_MR3_WRPST_DEFVAL #undef DDR_PHY_MR3_WRPST_SHIFT #undef DDR_PHY_MR3_WRPST_MASK -#define DDR_PHY_MR3_WRPST_DEFVAL 0x00000031 -#define DDR_PHY_MR3_WRPST_SHIFT 1 -#define DDR_PHY_MR3_WRPST_MASK 0x00000002U +#define DDR_PHY_MR3_WRPST_DEFVAL 0x00000031 +#define DDR_PHY_MR3_WRPST_SHIFT 1 +#define DDR_PHY_MR3_WRPST_MASK 0x00000002U -/*Pull-up Calibration Point*/ +/* +* Pull-up Calibration Point +*/ #undef DDR_PHY_MR3_PUCAL_DEFVAL #undef DDR_PHY_MR3_PUCAL_SHIFT #undef DDR_PHY_MR3_PUCAL_MASK -#define DDR_PHY_MR3_PUCAL_DEFVAL 0x00000031 -#define DDR_PHY_MR3_PUCAL_SHIFT 0 -#define DDR_PHY_MR3_PUCAL_MASK 0x00000001U +#define DDR_PHY_MR3_PUCAL_DEFVAL 0x00000031 +#define DDR_PHY_MR3_PUCAL_SHIFT 0 +#define DDR_PHY_MR3_PUCAL_MASK 0x00000001U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_MR4_RESERVED_31_16_DEFVAL #undef DDR_PHY_MR4_RESERVED_31_16_SHIFT #undef DDR_PHY_MR4_RESERVED_31_16_MASK -#define DDR_PHY_MR4_RESERVED_31_16_DEFVAL 0x00000000 -#define DDR_PHY_MR4_RESERVED_31_16_SHIFT 16 -#define DDR_PHY_MR4_RESERVED_31_16_MASK 0xFFFF0000U +#define DDR_PHY_MR4_RESERVED_31_16_DEFVAL 0x00000000 +#define DDR_PHY_MR4_RESERVED_31_16_SHIFT 16 +#define DDR_PHY_MR4_RESERVED_31_16_MASK 0xFFFF0000U -/*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/ +/* +* These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. +*/ #undef DDR_PHY_MR4_RSVD_15_13_DEFVAL #undef DDR_PHY_MR4_RSVD_15_13_SHIFT #undef DDR_PHY_MR4_RSVD_15_13_MASK -#define DDR_PHY_MR4_RSVD_15_13_DEFVAL 0x00000000 -#define DDR_PHY_MR4_RSVD_15_13_SHIFT 13 -#define DDR_PHY_MR4_RSVD_15_13_MASK 0x0000E000U +#define DDR_PHY_MR4_RSVD_15_13_DEFVAL 0x00000000 +#define DDR_PHY_MR4_RSVD_15_13_SHIFT 13 +#define DDR_PHY_MR4_RSVD_15_13_MASK 0x0000E000U -/*Write Preamble*/ +/* +* Write Preamble +*/ #undef DDR_PHY_MR4_WRP_DEFVAL #undef DDR_PHY_MR4_WRP_SHIFT #undef DDR_PHY_MR4_WRP_MASK -#define DDR_PHY_MR4_WRP_DEFVAL 0x00000000 -#define DDR_PHY_MR4_WRP_SHIFT 12 -#define DDR_PHY_MR4_WRP_MASK 0x00001000U +#define DDR_PHY_MR4_WRP_DEFVAL 0x00000000 +#define DDR_PHY_MR4_WRP_SHIFT 12 +#define DDR_PHY_MR4_WRP_MASK 0x00001000U -/*Read Preamble*/ +/* +* Read Preamble +*/ #undef DDR_PHY_MR4_RDP_DEFVAL #undef DDR_PHY_MR4_RDP_SHIFT #undef DDR_PHY_MR4_RDP_MASK -#define DDR_PHY_MR4_RDP_DEFVAL 0x00000000 -#define DDR_PHY_MR4_RDP_SHIFT 11 -#define DDR_PHY_MR4_RDP_MASK 0x00000800U +#define DDR_PHY_MR4_RDP_DEFVAL 0x00000000 +#define DDR_PHY_MR4_RDP_SHIFT 11 +#define DDR_PHY_MR4_RDP_MASK 0x00000800U -/*Read Preamble Training Mode*/ +/* +* Read Preamble Training Mode +*/ #undef DDR_PHY_MR4_RPTM_DEFVAL #undef DDR_PHY_MR4_RPTM_SHIFT #undef DDR_PHY_MR4_RPTM_MASK -#define DDR_PHY_MR4_RPTM_DEFVAL 0x00000000 -#define DDR_PHY_MR4_RPTM_SHIFT 10 -#define DDR_PHY_MR4_RPTM_MASK 0x00000400U +#define DDR_PHY_MR4_RPTM_DEFVAL 0x00000000 +#define DDR_PHY_MR4_RPTM_SHIFT 10 +#define DDR_PHY_MR4_RPTM_MASK 0x00000400U -/*Self Refresh Abort*/ +/* +* Self Refresh Abort +*/ #undef DDR_PHY_MR4_SRA_DEFVAL #undef DDR_PHY_MR4_SRA_SHIFT #undef DDR_PHY_MR4_SRA_MASK -#define DDR_PHY_MR4_SRA_DEFVAL 0x00000000 -#define DDR_PHY_MR4_SRA_SHIFT 9 -#define DDR_PHY_MR4_SRA_MASK 0x00000200U +#define DDR_PHY_MR4_SRA_DEFVAL 0x00000000 +#define DDR_PHY_MR4_SRA_SHIFT 9 +#define DDR_PHY_MR4_SRA_MASK 0x00000200U -/*CS to Command Latency Mode*/ +/* +* CS to Command Latency Mode +*/ #undef DDR_PHY_MR4_CS2CMDL_DEFVAL #undef DDR_PHY_MR4_CS2CMDL_SHIFT #undef DDR_PHY_MR4_CS2CMDL_MASK -#define DDR_PHY_MR4_CS2CMDL_DEFVAL 0x00000000 -#define DDR_PHY_MR4_CS2CMDL_SHIFT 6 -#define DDR_PHY_MR4_CS2CMDL_MASK 0x000001C0U +#define DDR_PHY_MR4_CS2CMDL_DEFVAL 0x00000000 +#define DDR_PHY_MR4_CS2CMDL_SHIFT 6 +#define DDR_PHY_MR4_CS2CMDL_MASK 0x000001C0U -/*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/ +/* +* These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. +*/ #undef DDR_PHY_MR4_RSVD1_DEFVAL #undef DDR_PHY_MR4_RSVD1_SHIFT #undef DDR_PHY_MR4_RSVD1_MASK -#define DDR_PHY_MR4_RSVD1_DEFVAL 0x00000000 -#define DDR_PHY_MR4_RSVD1_SHIFT 5 -#define DDR_PHY_MR4_RSVD1_MASK 0x00000020U +#define DDR_PHY_MR4_RSVD1_DEFVAL 0x00000000 +#define DDR_PHY_MR4_RSVD1_SHIFT 5 +#define DDR_PHY_MR4_RSVD1_MASK 0x00000020U -/*Internal VREF Monitor*/ +/* +* Internal VREF Monitor +*/ #undef DDR_PHY_MR4_IVM_DEFVAL #undef DDR_PHY_MR4_IVM_SHIFT #undef DDR_PHY_MR4_IVM_MASK -#define DDR_PHY_MR4_IVM_DEFVAL 0x00000000 -#define DDR_PHY_MR4_IVM_SHIFT 4 -#define DDR_PHY_MR4_IVM_MASK 0x00000010U +#define DDR_PHY_MR4_IVM_DEFVAL 0x00000000 +#define DDR_PHY_MR4_IVM_SHIFT 4 +#define DDR_PHY_MR4_IVM_MASK 0x00000010U -/*Temperature Controlled Refresh Mode*/ +/* +* Temperature Controlled Refresh Mode +*/ #undef DDR_PHY_MR4_TCRM_DEFVAL #undef DDR_PHY_MR4_TCRM_SHIFT #undef DDR_PHY_MR4_TCRM_MASK -#define DDR_PHY_MR4_TCRM_DEFVAL 0x00000000 -#define DDR_PHY_MR4_TCRM_SHIFT 3 -#define DDR_PHY_MR4_TCRM_MASK 0x00000008U +#define DDR_PHY_MR4_TCRM_DEFVAL 0x00000000 +#define DDR_PHY_MR4_TCRM_SHIFT 3 +#define DDR_PHY_MR4_TCRM_MASK 0x00000008U -/*Temperature Controlled Refresh Range*/ +/* +* Temperature Controlled Refresh Range +*/ #undef DDR_PHY_MR4_TCRR_DEFVAL #undef DDR_PHY_MR4_TCRR_SHIFT #undef DDR_PHY_MR4_TCRR_MASK -#define DDR_PHY_MR4_TCRR_DEFVAL 0x00000000 -#define DDR_PHY_MR4_TCRR_SHIFT 2 -#define DDR_PHY_MR4_TCRR_MASK 0x00000004U +#define DDR_PHY_MR4_TCRR_DEFVAL 0x00000000 +#define DDR_PHY_MR4_TCRR_SHIFT 2 +#define DDR_PHY_MR4_TCRR_MASK 0x00000004U -/*Maximum Power Down Mode*/ +/* +* Maximum Power Down Mode +*/ #undef DDR_PHY_MR4_MPDM_DEFVAL #undef DDR_PHY_MR4_MPDM_SHIFT #undef DDR_PHY_MR4_MPDM_MASK -#define DDR_PHY_MR4_MPDM_DEFVAL 0x00000000 -#define DDR_PHY_MR4_MPDM_SHIFT 1 -#define DDR_PHY_MR4_MPDM_MASK 0x00000002U +#define DDR_PHY_MR4_MPDM_DEFVAL 0x00000000 +#define DDR_PHY_MR4_MPDM_SHIFT 1 +#define DDR_PHY_MR4_MPDM_MASK 0x00000002U -/*This is a JEDEC reserved bit and is recommended by JEDEC to be programmed to 0x0.*/ +/* +* This is a JEDEC reserved bit and is recommended by JEDEC to be programme + * d to 0x0. +*/ #undef DDR_PHY_MR4_RSVD_0_DEFVAL #undef DDR_PHY_MR4_RSVD_0_SHIFT #undef DDR_PHY_MR4_RSVD_0_MASK -#define DDR_PHY_MR4_RSVD_0_DEFVAL 0x00000000 -#define DDR_PHY_MR4_RSVD_0_SHIFT 0 -#define DDR_PHY_MR4_RSVD_0_MASK 0x00000001U +#define DDR_PHY_MR4_RSVD_0_DEFVAL 0x00000000 +#define DDR_PHY_MR4_RSVD_0_SHIFT 0 +#define DDR_PHY_MR4_RSVD_0_MASK 0x00000001U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_MR5_RESERVED_31_16_DEFVAL #undef DDR_PHY_MR5_RESERVED_31_16_SHIFT #undef DDR_PHY_MR5_RESERVED_31_16_MASK -#define DDR_PHY_MR5_RESERVED_31_16_DEFVAL 0x00000000 -#define DDR_PHY_MR5_RESERVED_31_16_SHIFT 16 -#define DDR_PHY_MR5_RESERVED_31_16_MASK 0xFFFF0000U +#define DDR_PHY_MR5_RESERVED_31_16_DEFVAL 0x00000000 +#define DDR_PHY_MR5_RESERVED_31_16_SHIFT 16 +#define DDR_PHY_MR5_RESERVED_31_16_MASK 0xFFFF0000U -/*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/ +/* +* These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. +*/ #undef DDR_PHY_MR5_RSVD_DEFVAL #undef DDR_PHY_MR5_RSVD_SHIFT #undef DDR_PHY_MR5_RSVD_MASK -#define DDR_PHY_MR5_RSVD_DEFVAL 0x00000000 -#define DDR_PHY_MR5_RSVD_SHIFT 13 -#define DDR_PHY_MR5_RSVD_MASK 0x0000E000U +#define DDR_PHY_MR5_RSVD_DEFVAL 0x00000000 +#define DDR_PHY_MR5_RSVD_SHIFT 13 +#define DDR_PHY_MR5_RSVD_MASK 0x0000E000U -/*Read DBI*/ +/* +* Read DBI +*/ #undef DDR_PHY_MR5_RDBI_DEFVAL #undef DDR_PHY_MR5_RDBI_SHIFT #undef DDR_PHY_MR5_RDBI_MASK -#define DDR_PHY_MR5_RDBI_DEFVAL 0x00000000 -#define DDR_PHY_MR5_RDBI_SHIFT 12 -#define DDR_PHY_MR5_RDBI_MASK 0x00001000U +#define DDR_PHY_MR5_RDBI_DEFVAL 0x00000000 +#define DDR_PHY_MR5_RDBI_SHIFT 12 +#define DDR_PHY_MR5_RDBI_MASK 0x00001000U -/*Write DBI*/ +/* +* Write DBI +*/ #undef DDR_PHY_MR5_WDBI_DEFVAL #undef DDR_PHY_MR5_WDBI_SHIFT #undef DDR_PHY_MR5_WDBI_MASK -#define DDR_PHY_MR5_WDBI_DEFVAL 0x00000000 -#define DDR_PHY_MR5_WDBI_SHIFT 11 -#define DDR_PHY_MR5_WDBI_MASK 0x00000800U +#define DDR_PHY_MR5_WDBI_DEFVAL 0x00000000 +#define DDR_PHY_MR5_WDBI_SHIFT 11 +#define DDR_PHY_MR5_WDBI_MASK 0x00000800U -/*Data Mask*/ +/* +* Data Mask +*/ #undef DDR_PHY_MR5_DM_DEFVAL #undef DDR_PHY_MR5_DM_SHIFT #undef DDR_PHY_MR5_DM_MASK -#define DDR_PHY_MR5_DM_DEFVAL 0x00000000 -#define DDR_PHY_MR5_DM_SHIFT 10 -#define DDR_PHY_MR5_DM_MASK 0x00000400U +#define DDR_PHY_MR5_DM_DEFVAL 0x00000000 +#define DDR_PHY_MR5_DM_SHIFT 10 +#define DDR_PHY_MR5_DM_MASK 0x00000400U -/*CA Parity Persistent Error*/ +/* +* CA Parity Persistent Error +*/ #undef DDR_PHY_MR5_CAPPE_DEFVAL #undef DDR_PHY_MR5_CAPPE_SHIFT #undef DDR_PHY_MR5_CAPPE_MASK -#define DDR_PHY_MR5_CAPPE_DEFVAL 0x00000000 -#define DDR_PHY_MR5_CAPPE_SHIFT 9 -#define DDR_PHY_MR5_CAPPE_MASK 0x00000200U +#define DDR_PHY_MR5_CAPPE_DEFVAL 0x00000000 +#define DDR_PHY_MR5_CAPPE_SHIFT 9 +#define DDR_PHY_MR5_CAPPE_MASK 0x00000200U -/*RTT_PARK*/ +/* +* RTT_PARK +*/ #undef DDR_PHY_MR5_RTTPARK_DEFVAL #undef DDR_PHY_MR5_RTTPARK_SHIFT #undef DDR_PHY_MR5_RTTPARK_MASK -#define DDR_PHY_MR5_RTTPARK_DEFVAL 0x00000000 -#define DDR_PHY_MR5_RTTPARK_SHIFT 6 -#define DDR_PHY_MR5_RTTPARK_MASK 0x000001C0U +#define DDR_PHY_MR5_RTTPARK_DEFVAL 0x00000000 +#define DDR_PHY_MR5_RTTPARK_SHIFT 6 +#define DDR_PHY_MR5_RTTPARK_MASK 0x000001C0U -/*ODT Input Buffer during Power Down mode*/ +/* +* ODT Input Buffer during Power Down mode +*/ #undef DDR_PHY_MR5_ODTIBPD_DEFVAL #undef DDR_PHY_MR5_ODTIBPD_SHIFT #undef DDR_PHY_MR5_ODTIBPD_MASK -#define DDR_PHY_MR5_ODTIBPD_DEFVAL 0x00000000 -#define DDR_PHY_MR5_ODTIBPD_SHIFT 5 -#define DDR_PHY_MR5_ODTIBPD_MASK 0x00000020U +#define DDR_PHY_MR5_ODTIBPD_DEFVAL 0x00000000 +#define DDR_PHY_MR5_ODTIBPD_SHIFT 5 +#define DDR_PHY_MR5_ODTIBPD_MASK 0x00000020U -/*C/A Parity Error Status*/ +/* +* C/A Parity Error Status +*/ #undef DDR_PHY_MR5_CAPES_DEFVAL #undef DDR_PHY_MR5_CAPES_SHIFT #undef DDR_PHY_MR5_CAPES_MASK -#define DDR_PHY_MR5_CAPES_DEFVAL 0x00000000 -#define DDR_PHY_MR5_CAPES_SHIFT 4 -#define DDR_PHY_MR5_CAPES_MASK 0x00000010U +#define DDR_PHY_MR5_CAPES_DEFVAL 0x00000000 +#define DDR_PHY_MR5_CAPES_SHIFT 4 +#define DDR_PHY_MR5_CAPES_MASK 0x00000010U -/*CRC Error Clear*/ +/* +* CRC Error Clear +*/ #undef DDR_PHY_MR5_CRCEC_DEFVAL #undef DDR_PHY_MR5_CRCEC_SHIFT #undef DDR_PHY_MR5_CRCEC_MASK -#define DDR_PHY_MR5_CRCEC_DEFVAL 0x00000000 -#define DDR_PHY_MR5_CRCEC_SHIFT 3 -#define DDR_PHY_MR5_CRCEC_MASK 0x00000008U +#define DDR_PHY_MR5_CRCEC_DEFVAL 0x00000000 +#define DDR_PHY_MR5_CRCEC_SHIFT 3 +#define DDR_PHY_MR5_CRCEC_MASK 0x00000008U -/*C/A Parity Latency Mode*/ +/* +* C/A Parity Latency Mode +*/ #undef DDR_PHY_MR5_CAPM_DEFVAL #undef DDR_PHY_MR5_CAPM_SHIFT #undef DDR_PHY_MR5_CAPM_MASK -#define DDR_PHY_MR5_CAPM_DEFVAL 0x00000000 -#define DDR_PHY_MR5_CAPM_SHIFT 0 -#define DDR_PHY_MR5_CAPM_MASK 0x00000007U +#define DDR_PHY_MR5_CAPM_DEFVAL 0x00000000 +#define DDR_PHY_MR5_CAPM_SHIFT 0 +#define DDR_PHY_MR5_CAPM_MASK 0x00000007U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_MR6_RESERVED_31_16_DEFVAL #undef DDR_PHY_MR6_RESERVED_31_16_SHIFT #undef DDR_PHY_MR6_RESERVED_31_16_MASK -#define DDR_PHY_MR6_RESERVED_31_16_DEFVAL 0x00000000 -#define DDR_PHY_MR6_RESERVED_31_16_SHIFT 16 -#define DDR_PHY_MR6_RESERVED_31_16_MASK 0xFFFF0000U +#define DDR_PHY_MR6_RESERVED_31_16_DEFVAL 0x00000000 +#define DDR_PHY_MR6_RESERVED_31_16_SHIFT 16 +#define DDR_PHY_MR6_RESERVED_31_16_MASK 0xFFFF0000U -/*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/ +/* +* These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. +*/ #undef DDR_PHY_MR6_RSVD_15_13_DEFVAL #undef DDR_PHY_MR6_RSVD_15_13_SHIFT #undef DDR_PHY_MR6_RSVD_15_13_MASK -#define DDR_PHY_MR6_RSVD_15_13_DEFVAL 0x00000000 -#define DDR_PHY_MR6_RSVD_15_13_SHIFT 13 -#define DDR_PHY_MR6_RSVD_15_13_MASK 0x0000E000U +#define DDR_PHY_MR6_RSVD_15_13_DEFVAL 0x00000000 +#define DDR_PHY_MR6_RSVD_15_13_SHIFT 13 +#define DDR_PHY_MR6_RSVD_15_13_MASK 0x0000E000U -/*CAS_n to CAS_n command delay for same bank group (tCCD_L)*/ +/* +* CAS_n to CAS_n command delay for same bank group (tCCD_L) +*/ #undef DDR_PHY_MR6_TCCDL_DEFVAL #undef DDR_PHY_MR6_TCCDL_SHIFT #undef DDR_PHY_MR6_TCCDL_MASK -#define DDR_PHY_MR6_TCCDL_DEFVAL 0x00000000 -#define DDR_PHY_MR6_TCCDL_SHIFT 10 -#define DDR_PHY_MR6_TCCDL_MASK 0x00001C00U +#define DDR_PHY_MR6_TCCDL_DEFVAL 0x00000000 +#define DDR_PHY_MR6_TCCDL_SHIFT 10 +#define DDR_PHY_MR6_TCCDL_MASK 0x00001C00U -/*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/ +/* +* These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. +*/ #undef DDR_PHY_MR6_RSVD_9_8_DEFVAL #undef DDR_PHY_MR6_RSVD_9_8_SHIFT #undef DDR_PHY_MR6_RSVD_9_8_MASK -#define DDR_PHY_MR6_RSVD_9_8_DEFVAL 0x00000000 -#define DDR_PHY_MR6_RSVD_9_8_SHIFT 8 -#define DDR_PHY_MR6_RSVD_9_8_MASK 0x00000300U +#define DDR_PHY_MR6_RSVD_9_8_DEFVAL 0x00000000 +#define DDR_PHY_MR6_RSVD_9_8_SHIFT 8 +#define DDR_PHY_MR6_RSVD_9_8_MASK 0x00000300U -/*VrefDQ Training Enable*/ +/* +* VrefDQ Training Enable +*/ #undef DDR_PHY_MR6_VDDQTEN_DEFVAL #undef DDR_PHY_MR6_VDDQTEN_SHIFT #undef DDR_PHY_MR6_VDDQTEN_MASK -#define DDR_PHY_MR6_VDDQTEN_DEFVAL 0x00000000 -#define DDR_PHY_MR6_VDDQTEN_SHIFT 7 -#define DDR_PHY_MR6_VDDQTEN_MASK 0x00000080U +#define DDR_PHY_MR6_VDDQTEN_DEFVAL 0x00000000 +#define DDR_PHY_MR6_VDDQTEN_SHIFT 7 +#define DDR_PHY_MR6_VDDQTEN_MASK 0x00000080U -/*VrefDQ Training Range*/ +/* +* VrefDQ Training Range +*/ #undef DDR_PHY_MR6_VDQTRG_DEFVAL #undef DDR_PHY_MR6_VDQTRG_SHIFT #undef DDR_PHY_MR6_VDQTRG_MASK -#define DDR_PHY_MR6_VDQTRG_DEFVAL 0x00000000 -#define DDR_PHY_MR6_VDQTRG_SHIFT 6 -#define DDR_PHY_MR6_VDQTRG_MASK 0x00000040U +#define DDR_PHY_MR6_VDQTRG_DEFVAL 0x00000000 +#define DDR_PHY_MR6_VDQTRG_SHIFT 6 +#define DDR_PHY_MR6_VDQTRG_MASK 0x00000040U -/*VrefDQ Training Values*/ +/* +* VrefDQ Training Values +*/ #undef DDR_PHY_MR6_VDQTVAL_DEFVAL #undef DDR_PHY_MR6_VDQTVAL_SHIFT #undef DDR_PHY_MR6_VDQTVAL_MASK -#define DDR_PHY_MR6_VDQTVAL_DEFVAL 0x00000000 -#define DDR_PHY_MR6_VDQTVAL_SHIFT 0 -#define DDR_PHY_MR6_VDQTVAL_MASK 0x0000003FU +#define DDR_PHY_MR6_VDQTVAL_DEFVAL 0x00000000 +#define DDR_PHY_MR6_VDQTVAL_SHIFT 0 +#define DDR_PHY_MR6_VDQTVAL_MASK 0x0000003FU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_MR11_RESERVED_31_8_DEFVAL #undef DDR_PHY_MR11_RESERVED_31_8_SHIFT #undef DDR_PHY_MR11_RESERVED_31_8_MASK -#define DDR_PHY_MR11_RESERVED_31_8_DEFVAL 0x00000000 -#define DDR_PHY_MR11_RESERVED_31_8_SHIFT 8 -#define DDR_PHY_MR11_RESERVED_31_8_MASK 0xFFFFFF00U +#define DDR_PHY_MR11_RESERVED_31_8_DEFVAL 0x00000000 +#define DDR_PHY_MR11_RESERVED_31_8_SHIFT 8 +#define DDR_PHY_MR11_RESERVED_31_8_MASK 0xFFFFFF00U -/*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/ +/* +* These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. +*/ #undef DDR_PHY_MR11_RSVD_DEFVAL #undef DDR_PHY_MR11_RSVD_SHIFT #undef DDR_PHY_MR11_RSVD_MASK -#define DDR_PHY_MR11_RSVD_DEFVAL 0x00000000 -#define DDR_PHY_MR11_RSVD_SHIFT 3 -#define DDR_PHY_MR11_RSVD_MASK 0x000000F8U +#define DDR_PHY_MR11_RSVD_DEFVAL 0x00000000 +#define DDR_PHY_MR11_RSVD_SHIFT 3 +#define DDR_PHY_MR11_RSVD_MASK 0x000000F8U -/*Power Down Control*/ +/* +* Power Down Control +*/ #undef DDR_PHY_MR11_PDCTL_DEFVAL #undef DDR_PHY_MR11_PDCTL_SHIFT #undef DDR_PHY_MR11_PDCTL_MASK -#define DDR_PHY_MR11_PDCTL_DEFVAL 0x00000000 -#define DDR_PHY_MR11_PDCTL_SHIFT 2 -#define DDR_PHY_MR11_PDCTL_MASK 0x00000004U +#define DDR_PHY_MR11_PDCTL_DEFVAL 0x00000000 +#define DDR_PHY_MR11_PDCTL_SHIFT 2 +#define DDR_PHY_MR11_PDCTL_MASK 0x00000004U -/*DQ Bus Receiver On-Die-Termination*/ +/* +* DQ Bus Receiver On-Die-Termination +*/ #undef DDR_PHY_MR11_DQODT_DEFVAL #undef DDR_PHY_MR11_DQODT_SHIFT #undef DDR_PHY_MR11_DQODT_MASK -#define DDR_PHY_MR11_DQODT_DEFVAL 0x00000000 -#define DDR_PHY_MR11_DQODT_SHIFT 0 -#define DDR_PHY_MR11_DQODT_MASK 0x00000003U +#define DDR_PHY_MR11_DQODT_DEFVAL 0x00000000 +#define DDR_PHY_MR11_DQODT_SHIFT 0 +#define DDR_PHY_MR11_DQODT_MASK 0x00000003U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_MR12_RESERVED_31_8_DEFVAL #undef DDR_PHY_MR12_RESERVED_31_8_SHIFT #undef DDR_PHY_MR12_RESERVED_31_8_MASK -#define DDR_PHY_MR12_RESERVED_31_8_DEFVAL 0x0000004D -#define DDR_PHY_MR12_RESERVED_31_8_SHIFT 8 -#define DDR_PHY_MR12_RESERVED_31_8_MASK 0xFFFFFF00U +#define DDR_PHY_MR12_RESERVED_31_8_DEFVAL 0x0000004D +#define DDR_PHY_MR12_RESERVED_31_8_SHIFT 8 +#define DDR_PHY_MR12_RESERVED_31_8_MASK 0xFFFFFF00U -/*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/ +/* +* These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. +*/ #undef DDR_PHY_MR12_RSVD_DEFVAL #undef DDR_PHY_MR12_RSVD_SHIFT #undef DDR_PHY_MR12_RSVD_MASK -#define DDR_PHY_MR12_RSVD_DEFVAL 0x0000004D -#define DDR_PHY_MR12_RSVD_SHIFT 7 -#define DDR_PHY_MR12_RSVD_MASK 0x00000080U +#define DDR_PHY_MR12_RSVD_DEFVAL 0x0000004D +#define DDR_PHY_MR12_RSVD_SHIFT 7 +#define DDR_PHY_MR12_RSVD_MASK 0x00000080U -/*VREF_CA Range Select.*/ +/* +* VREF_CA Range Select. +*/ #undef DDR_PHY_MR12_VR_CA_DEFVAL #undef DDR_PHY_MR12_VR_CA_SHIFT #undef DDR_PHY_MR12_VR_CA_MASK -#define DDR_PHY_MR12_VR_CA_DEFVAL 0x0000004D -#define DDR_PHY_MR12_VR_CA_SHIFT 6 -#define DDR_PHY_MR12_VR_CA_MASK 0x00000040U +#define DDR_PHY_MR12_VR_CA_DEFVAL 0x0000004D +#define DDR_PHY_MR12_VR_CA_SHIFT 6 +#define DDR_PHY_MR12_VR_CA_MASK 0x00000040U -/*Controls the VREF(ca) levels for Frequency-Set-Point[1:0].*/ +/* +* Controls the VREF(ca) levels for Frequency-Set-Point[1:0]. +*/ #undef DDR_PHY_MR12_VREF_CA_DEFVAL #undef DDR_PHY_MR12_VREF_CA_SHIFT #undef DDR_PHY_MR12_VREF_CA_MASK -#define DDR_PHY_MR12_VREF_CA_DEFVAL 0x0000004D -#define DDR_PHY_MR12_VREF_CA_SHIFT 0 -#define DDR_PHY_MR12_VREF_CA_MASK 0x0000003FU +#define DDR_PHY_MR12_VREF_CA_DEFVAL 0x0000004D +#define DDR_PHY_MR12_VREF_CA_SHIFT 0 +#define DDR_PHY_MR12_VREF_CA_MASK 0x0000003FU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_MR13_RESERVED_31_8_DEFVAL #undef DDR_PHY_MR13_RESERVED_31_8_SHIFT #undef DDR_PHY_MR13_RESERVED_31_8_MASK -#define DDR_PHY_MR13_RESERVED_31_8_DEFVAL 0x00000000 -#define DDR_PHY_MR13_RESERVED_31_8_SHIFT 8 -#define DDR_PHY_MR13_RESERVED_31_8_MASK 0xFFFFFF00U +#define DDR_PHY_MR13_RESERVED_31_8_DEFVAL 0x00000000 +#define DDR_PHY_MR13_RESERVED_31_8_SHIFT 8 +#define DDR_PHY_MR13_RESERVED_31_8_MASK 0xFFFFFF00U -/*Frequency Set Point Operation Mode*/ +/* +* Frequency Set Point Operation Mode +*/ #undef DDR_PHY_MR13_FSPOP_DEFVAL #undef DDR_PHY_MR13_FSPOP_SHIFT #undef DDR_PHY_MR13_FSPOP_MASK -#define DDR_PHY_MR13_FSPOP_DEFVAL 0x00000000 -#define DDR_PHY_MR13_FSPOP_SHIFT 7 -#define DDR_PHY_MR13_FSPOP_MASK 0x00000080U +#define DDR_PHY_MR13_FSPOP_DEFVAL 0x00000000 +#define DDR_PHY_MR13_FSPOP_SHIFT 7 +#define DDR_PHY_MR13_FSPOP_MASK 0x00000080U -/*Frequency Set Point Write Enable*/ +/* +* Frequency Set Point Write Enable +*/ #undef DDR_PHY_MR13_FSPWR_DEFVAL #undef DDR_PHY_MR13_FSPWR_SHIFT #undef DDR_PHY_MR13_FSPWR_MASK -#define DDR_PHY_MR13_FSPWR_DEFVAL 0x00000000 -#define DDR_PHY_MR13_FSPWR_SHIFT 6 -#define DDR_PHY_MR13_FSPWR_MASK 0x00000040U +#define DDR_PHY_MR13_FSPWR_DEFVAL 0x00000000 +#define DDR_PHY_MR13_FSPWR_SHIFT 6 +#define DDR_PHY_MR13_FSPWR_MASK 0x00000040U -/*Data Mask Enable*/ +/* +* Data Mask Enable +*/ #undef DDR_PHY_MR13_DMD_DEFVAL #undef DDR_PHY_MR13_DMD_SHIFT #undef DDR_PHY_MR13_DMD_MASK -#define DDR_PHY_MR13_DMD_DEFVAL 0x00000000 -#define DDR_PHY_MR13_DMD_SHIFT 5 -#define DDR_PHY_MR13_DMD_MASK 0x00000020U +#define DDR_PHY_MR13_DMD_DEFVAL 0x00000000 +#define DDR_PHY_MR13_DMD_SHIFT 5 +#define DDR_PHY_MR13_DMD_MASK 0x00000020U -/*Refresh Rate Option*/ +/* +* Refresh Rate Option +*/ #undef DDR_PHY_MR13_RRO_DEFVAL #undef DDR_PHY_MR13_RRO_SHIFT #undef DDR_PHY_MR13_RRO_MASK -#define DDR_PHY_MR13_RRO_DEFVAL 0x00000000 -#define DDR_PHY_MR13_RRO_SHIFT 4 -#define DDR_PHY_MR13_RRO_MASK 0x00000010U +#define DDR_PHY_MR13_RRO_DEFVAL 0x00000000 +#define DDR_PHY_MR13_RRO_SHIFT 4 +#define DDR_PHY_MR13_RRO_MASK 0x00000010U -/*VREF Current Generator*/ +/* +* VREF Current Generator +*/ #undef DDR_PHY_MR13_VRCG_DEFVAL #undef DDR_PHY_MR13_VRCG_SHIFT #undef DDR_PHY_MR13_VRCG_MASK -#define DDR_PHY_MR13_VRCG_DEFVAL 0x00000000 -#define DDR_PHY_MR13_VRCG_SHIFT 3 -#define DDR_PHY_MR13_VRCG_MASK 0x00000008U +#define DDR_PHY_MR13_VRCG_DEFVAL 0x00000000 +#define DDR_PHY_MR13_VRCG_SHIFT 3 +#define DDR_PHY_MR13_VRCG_MASK 0x00000008U -/*VREF Output*/ +/* +* VREF Output +*/ #undef DDR_PHY_MR13_VRO_DEFVAL #undef DDR_PHY_MR13_VRO_SHIFT #undef DDR_PHY_MR13_VRO_MASK -#define DDR_PHY_MR13_VRO_DEFVAL 0x00000000 -#define DDR_PHY_MR13_VRO_SHIFT 2 -#define DDR_PHY_MR13_VRO_MASK 0x00000004U +#define DDR_PHY_MR13_VRO_DEFVAL 0x00000000 +#define DDR_PHY_MR13_VRO_SHIFT 2 +#define DDR_PHY_MR13_VRO_MASK 0x00000004U -/*Read Preamble Training Mode*/ +/* +* Read Preamble Training Mode +*/ #undef DDR_PHY_MR13_RPT_DEFVAL #undef DDR_PHY_MR13_RPT_SHIFT #undef DDR_PHY_MR13_RPT_MASK -#define DDR_PHY_MR13_RPT_DEFVAL 0x00000000 -#define DDR_PHY_MR13_RPT_SHIFT 1 -#define DDR_PHY_MR13_RPT_MASK 0x00000002U +#define DDR_PHY_MR13_RPT_DEFVAL 0x00000000 +#define DDR_PHY_MR13_RPT_SHIFT 1 +#define DDR_PHY_MR13_RPT_MASK 0x00000002U -/*Command Bus Training*/ +/* +* Command Bus Training +*/ #undef DDR_PHY_MR13_CBT_DEFVAL #undef DDR_PHY_MR13_CBT_SHIFT #undef DDR_PHY_MR13_CBT_MASK -#define DDR_PHY_MR13_CBT_DEFVAL 0x00000000 -#define DDR_PHY_MR13_CBT_SHIFT 0 -#define DDR_PHY_MR13_CBT_MASK 0x00000001U +#define DDR_PHY_MR13_CBT_DEFVAL 0x00000000 +#define DDR_PHY_MR13_CBT_SHIFT 0 +#define DDR_PHY_MR13_CBT_MASK 0x00000001U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_MR14_RESERVED_31_8_DEFVAL #undef DDR_PHY_MR14_RESERVED_31_8_SHIFT #undef DDR_PHY_MR14_RESERVED_31_8_MASK -#define DDR_PHY_MR14_RESERVED_31_8_DEFVAL 0x0000004D -#define DDR_PHY_MR14_RESERVED_31_8_SHIFT 8 -#define DDR_PHY_MR14_RESERVED_31_8_MASK 0xFFFFFF00U +#define DDR_PHY_MR14_RESERVED_31_8_DEFVAL 0x0000004D +#define DDR_PHY_MR14_RESERVED_31_8_SHIFT 8 +#define DDR_PHY_MR14_RESERVED_31_8_MASK 0xFFFFFF00U -/*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/ +/* +* These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. +*/ #undef DDR_PHY_MR14_RSVD_DEFVAL #undef DDR_PHY_MR14_RSVD_SHIFT #undef DDR_PHY_MR14_RSVD_MASK -#define DDR_PHY_MR14_RSVD_DEFVAL 0x0000004D -#define DDR_PHY_MR14_RSVD_SHIFT 7 -#define DDR_PHY_MR14_RSVD_MASK 0x00000080U +#define DDR_PHY_MR14_RSVD_DEFVAL 0x0000004D +#define DDR_PHY_MR14_RSVD_SHIFT 7 +#define DDR_PHY_MR14_RSVD_MASK 0x00000080U -/*VREFDQ Range Selects.*/ +/* +* VREFDQ Range Selects. +*/ #undef DDR_PHY_MR14_VR_DQ_DEFVAL #undef DDR_PHY_MR14_VR_DQ_SHIFT #undef DDR_PHY_MR14_VR_DQ_MASK -#define DDR_PHY_MR14_VR_DQ_DEFVAL 0x0000004D -#define DDR_PHY_MR14_VR_DQ_SHIFT 6 -#define DDR_PHY_MR14_VR_DQ_MASK 0x00000040U +#define DDR_PHY_MR14_VR_DQ_DEFVAL 0x0000004D +#define DDR_PHY_MR14_VR_DQ_SHIFT 6 +#define DDR_PHY_MR14_VR_DQ_MASK 0x00000040U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_MR14_VREF_DQ_DEFVAL #undef DDR_PHY_MR14_VREF_DQ_SHIFT #undef DDR_PHY_MR14_VREF_DQ_MASK -#define DDR_PHY_MR14_VREF_DQ_DEFVAL 0x0000004D -#define DDR_PHY_MR14_VREF_DQ_SHIFT 0 -#define DDR_PHY_MR14_VREF_DQ_MASK 0x0000003FU +#define DDR_PHY_MR14_VREF_DQ_DEFVAL 0x0000004D +#define DDR_PHY_MR14_VREF_DQ_SHIFT 0 +#define DDR_PHY_MR14_VREF_DQ_MASK 0x0000003FU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_MR22_RESERVED_31_8_DEFVAL #undef DDR_PHY_MR22_RESERVED_31_8_SHIFT #undef DDR_PHY_MR22_RESERVED_31_8_MASK -#define DDR_PHY_MR22_RESERVED_31_8_DEFVAL 0x00000000 -#define DDR_PHY_MR22_RESERVED_31_8_SHIFT 8 -#define DDR_PHY_MR22_RESERVED_31_8_MASK 0xFFFFFF00U +#define DDR_PHY_MR22_RESERVED_31_8_DEFVAL 0x00000000 +#define DDR_PHY_MR22_RESERVED_31_8_SHIFT 8 +#define DDR_PHY_MR22_RESERVED_31_8_MASK 0xFFFFFF00U -/*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/ +/* +* These are JEDEC reserved bits and are recommended by JEDEC to be program + * med to 0x0. +*/ #undef DDR_PHY_MR22_RSVD_DEFVAL #undef DDR_PHY_MR22_RSVD_SHIFT #undef DDR_PHY_MR22_RSVD_MASK -#define DDR_PHY_MR22_RSVD_DEFVAL 0x00000000 -#define DDR_PHY_MR22_RSVD_SHIFT 6 -#define DDR_PHY_MR22_RSVD_MASK 0x000000C0U +#define DDR_PHY_MR22_RSVD_DEFVAL 0x00000000 +#define DDR_PHY_MR22_RSVD_SHIFT 6 +#define DDR_PHY_MR22_RSVD_MASK 0x000000C0U -/*CA ODT termination disable.*/ +/* +* CA ODT termination disable. +*/ #undef DDR_PHY_MR22_ODTD_CA_DEFVAL #undef DDR_PHY_MR22_ODTD_CA_SHIFT #undef DDR_PHY_MR22_ODTD_CA_MASK -#define DDR_PHY_MR22_ODTD_CA_DEFVAL 0x00000000 -#define DDR_PHY_MR22_ODTD_CA_SHIFT 5 -#define DDR_PHY_MR22_ODTD_CA_MASK 0x00000020U +#define DDR_PHY_MR22_ODTD_CA_DEFVAL 0x00000000 +#define DDR_PHY_MR22_ODTD_CA_SHIFT 5 +#define DDR_PHY_MR22_ODTD_CA_MASK 0x00000020U -/*ODT CS override.*/ +/* +* ODT CS override. +*/ #undef DDR_PHY_MR22_ODTE_CS_DEFVAL #undef DDR_PHY_MR22_ODTE_CS_SHIFT #undef DDR_PHY_MR22_ODTE_CS_MASK -#define DDR_PHY_MR22_ODTE_CS_DEFVAL 0x00000000 -#define DDR_PHY_MR22_ODTE_CS_SHIFT 4 -#define DDR_PHY_MR22_ODTE_CS_MASK 0x00000010U +#define DDR_PHY_MR22_ODTE_CS_DEFVAL 0x00000000 +#define DDR_PHY_MR22_ODTE_CS_SHIFT 4 +#define DDR_PHY_MR22_ODTE_CS_MASK 0x00000010U -/*ODT CK override.*/ +/* +* ODT CK override. +*/ #undef DDR_PHY_MR22_ODTE_CK_DEFVAL #undef DDR_PHY_MR22_ODTE_CK_SHIFT #undef DDR_PHY_MR22_ODTE_CK_MASK -#define DDR_PHY_MR22_ODTE_CK_DEFVAL 0x00000000 -#define DDR_PHY_MR22_ODTE_CK_SHIFT 3 -#define DDR_PHY_MR22_ODTE_CK_MASK 0x00000008U +#define DDR_PHY_MR22_ODTE_CK_DEFVAL 0x00000000 +#define DDR_PHY_MR22_ODTE_CK_SHIFT 3 +#define DDR_PHY_MR22_ODTE_CK_MASK 0x00000008U -/*Controller ODT value for VOH calibration.*/ +/* +* Controller ODT value for VOH calibration. +*/ #undef DDR_PHY_MR22_CODT_DEFVAL #undef DDR_PHY_MR22_CODT_SHIFT #undef DDR_PHY_MR22_CODT_MASK -#define DDR_PHY_MR22_CODT_DEFVAL 0x00000000 -#define DDR_PHY_MR22_CODT_SHIFT 0 -#define DDR_PHY_MR22_CODT_MASK 0x00000007U +#define DDR_PHY_MR22_CODT_DEFVAL 0x00000000 +#define DDR_PHY_MR22_CODT_SHIFT 0 +#define DDR_PHY_MR22_CODT_MASK 0x00000007U -/*Refresh During Training*/ +/* +* Refresh During Training +*/ #undef DDR_PHY_DTCR0_RFSHDT_DEFVAL #undef DDR_PHY_DTCR0_RFSHDT_SHIFT #undef DDR_PHY_DTCR0_RFSHDT_MASK -#define DDR_PHY_DTCR0_RFSHDT_DEFVAL 0x800091C7 -#define DDR_PHY_DTCR0_RFSHDT_SHIFT 28 -#define DDR_PHY_DTCR0_RFSHDT_MASK 0xF0000000U +#define DDR_PHY_DTCR0_RFSHDT_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_RFSHDT_SHIFT 28 +#define DDR_PHY_DTCR0_RFSHDT_MASK 0xF0000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTCR0_RESERVED_27_26_DEFVAL #undef DDR_PHY_DTCR0_RESERVED_27_26_SHIFT #undef DDR_PHY_DTCR0_RESERVED_27_26_MASK -#define DDR_PHY_DTCR0_RESERVED_27_26_DEFVAL 0x800091C7 -#define DDR_PHY_DTCR0_RESERVED_27_26_SHIFT 26 -#define DDR_PHY_DTCR0_RESERVED_27_26_MASK 0x0C000000U +#define DDR_PHY_DTCR0_RESERVED_27_26_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_RESERVED_27_26_SHIFT 26 +#define DDR_PHY_DTCR0_RESERVED_27_26_MASK 0x0C000000U -/*Data Training Debug Rank Select*/ +/* +* Data Training Debug Rank Select +*/ #undef DDR_PHY_DTCR0_DTDRS_DEFVAL #undef DDR_PHY_DTCR0_DTDRS_SHIFT #undef DDR_PHY_DTCR0_DTDRS_MASK -#define DDR_PHY_DTCR0_DTDRS_DEFVAL 0x800091C7 -#define DDR_PHY_DTCR0_DTDRS_SHIFT 24 -#define DDR_PHY_DTCR0_DTDRS_MASK 0x03000000U +#define DDR_PHY_DTCR0_DTDRS_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_DTDRS_SHIFT 24 +#define DDR_PHY_DTCR0_DTDRS_MASK 0x03000000U -/*Data Training with Early/Extended Gate*/ +/* +* Data Training with Early/Extended Gate +*/ #undef DDR_PHY_DTCR0_DTEXG_DEFVAL #undef DDR_PHY_DTCR0_DTEXG_SHIFT #undef DDR_PHY_DTCR0_DTEXG_MASK -#define DDR_PHY_DTCR0_DTEXG_DEFVAL 0x800091C7 -#define DDR_PHY_DTCR0_DTEXG_SHIFT 23 -#define DDR_PHY_DTCR0_DTEXG_MASK 0x00800000U +#define DDR_PHY_DTCR0_DTEXG_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_DTEXG_SHIFT 23 +#define DDR_PHY_DTCR0_DTEXG_MASK 0x00800000U -/*Data Training Extended Write DQS*/ +/* +* Data Training Extended Write DQS +*/ #undef DDR_PHY_DTCR0_DTEXD_DEFVAL #undef DDR_PHY_DTCR0_DTEXD_SHIFT #undef DDR_PHY_DTCR0_DTEXD_MASK -#define DDR_PHY_DTCR0_DTEXD_DEFVAL 0x800091C7 -#define DDR_PHY_DTCR0_DTEXD_SHIFT 22 -#define DDR_PHY_DTCR0_DTEXD_MASK 0x00400000U +#define DDR_PHY_DTCR0_DTEXD_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_DTEXD_SHIFT 22 +#define DDR_PHY_DTCR0_DTEXD_MASK 0x00400000U -/*Data Training Debug Step*/ +/* +* Data Training Debug Step +*/ #undef DDR_PHY_DTCR0_DTDSTP_DEFVAL #undef DDR_PHY_DTCR0_DTDSTP_SHIFT #undef DDR_PHY_DTCR0_DTDSTP_MASK -#define DDR_PHY_DTCR0_DTDSTP_DEFVAL 0x800091C7 -#define DDR_PHY_DTCR0_DTDSTP_SHIFT 21 -#define DDR_PHY_DTCR0_DTDSTP_MASK 0x00200000U +#define DDR_PHY_DTCR0_DTDSTP_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_DTDSTP_SHIFT 21 +#define DDR_PHY_DTCR0_DTDSTP_MASK 0x00200000U -/*Data Training Debug Enable*/ +/* +* Data Training Debug Enable +*/ #undef DDR_PHY_DTCR0_DTDEN_DEFVAL #undef DDR_PHY_DTCR0_DTDEN_SHIFT #undef DDR_PHY_DTCR0_DTDEN_MASK -#define DDR_PHY_DTCR0_DTDEN_DEFVAL 0x800091C7 -#define DDR_PHY_DTCR0_DTDEN_SHIFT 20 -#define DDR_PHY_DTCR0_DTDEN_MASK 0x00100000U +#define DDR_PHY_DTCR0_DTDEN_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_DTDEN_SHIFT 20 +#define DDR_PHY_DTCR0_DTDEN_MASK 0x00100000U -/*Data Training Debug Byte Select*/ +/* +* Data Training Debug Byte Select +*/ #undef DDR_PHY_DTCR0_DTDBS_DEFVAL #undef DDR_PHY_DTCR0_DTDBS_SHIFT #undef DDR_PHY_DTCR0_DTDBS_MASK -#define DDR_PHY_DTCR0_DTDBS_DEFVAL 0x800091C7 -#define DDR_PHY_DTCR0_DTDBS_SHIFT 16 -#define DDR_PHY_DTCR0_DTDBS_MASK 0x000F0000U +#define DDR_PHY_DTCR0_DTDBS_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_DTDBS_SHIFT 16 +#define DDR_PHY_DTCR0_DTDBS_MASK 0x000F0000U -/*Data Training read DBI deskewing configuration*/ +/* +* Data Training read DBI deskewing configuration +*/ #undef DDR_PHY_DTCR0_DTRDBITR_DEFVAL #undef DDR_PHY_DTCR0_DTRDBITR_SHIFT #undef DDR_PHY_DTCR0_DTRDBITR_MASK -#define DDR_PHY_DTCR0_DTRDBITR_DEFVAL 0x800091C7 -#define DDR_PHY_DTCR0_DTRDBITR_SHIFT 14 -#define DDR_PHY_DTCR0_DTRDBITR_MASK 0x0000C000U +#define DDR_PHY_DTCR0_DTRDBITR_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_DTRDBITR_SHIFT 14 +#define DDR_PHY_DTCR0_DTRDBITR_MASK 0x0000C000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTCR0_RESERVED_13_DEFVAL #undef DDR_PHY_DTCR0_RESERVED_13_SHIFT #undef DDR_PHY_DTCR0_RESERVED_13_MASK -#define DDR_PHY_DTCR0_RESERVED_13_DEFVAL 0x800091C7 -#define DDR_PHY_DTCR0_RESERVED_13_SHIFT 13 -#define DDR_PHY_DTCR0_RESERVED_13_MASK 0x00002000U +#define DDR_PHY_DTCR0_RESERVED_13_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_RESERVED_13_SHIFT 13 +#define DDR_PHY_DTCR0_RESERVED_13_MASK 0x00002000U -/*Data Training Write Bit Deskew Data Mask*/ +/* +* Data Training Write Bit Deskew Data Mask +*/ #undef DDR_PHY_DTCR0_DTWBDDM_DEFVAL #undef DDR_PHY_DTCR0_DTWBDDM_SHIFT #undef DDR_PHY_DTCR0_DTWBDDM_MASK -#define DDR_PHY_DTCR0_DTWBDDM_DEFVAL 0x800091C7 -#define DDR_PHY_DTCR0_DTWBDDM_SHIFT 12 -#define DDR_PHY_DTCR0_DTWBDDM_MASK 0x00001000U +#define DDR_PHY_DTCR0_DTWBDDM_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_DTWBDDM_SHIFT 12 +#define DDR_PHY_DTCR0_DTWBDDM_MASK 0x00001000U -/*Refreshes Issued During Entry to Training*/ +/* +* Refreshes Issued During Entry to Training +*/ #undef DDR_PHY_DTCR0_RFSHEN_DEFVAL #undef DDR_PHY_DTCR0_RFSHEN_SHIFT #undef DDR_PHY_DTCR0_RFSHEN_MASK -#define DDR_PHY_DTCR0_RFSHEN_DEFVAL 0x800091C7 -#define DDR_PHY_DTCR0_RFSHEN_SHIFT 8 -#define DDR_PHY_DTCR0_RFSHEN_MASK 0x00000F00U +#define DDR_PHY_DTCR0_RFSHEN_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_RFSHEN_SHIFT 8 +#define DDR_PHY_DTCR0_RFSHEN_MASK 0x00000F00U -/*Data Training Compare Data*/ +/* +* Data Training Compare Data +*/ #undef DDR_PHY_DTCR0_DTCMPD_DEFVAL #undef DDR_PHY_DTCR0_DTCMPD_SHIFT #undef DDR_PHY_DTCR0_DTCMPD_MASK -#define DDR_PHY_DTCR0_DTCMPD_DEFVAL 0x800091C7 -#define DDR_PHY_DTCR0_DTCMPD_SHIFT 7 -#define DDR_PHY_DTCR0_DTCMPD_MASK 0x00000080U +#define DDR_PHY_DTCR0_DTCMPD_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_DTCMPD_SHIFT 7 +#define DDR_PHY_DTCR0_DTCMPD_MASK 0x00000080U -/*Data Training Using MPR*/ +/* +* Data Training Using MPR +*/ #undef DDR_PHY_DTCR0_DTMPR_DEFVAL #undef DDR_PHY_DTCR0_DTMPR_SHIFT #undef DDR_PHY_DTCR0_DTMPR_MASK -#define DDR_PHY_DTCR0_DTMPR_DEFVAL 0x800091C7 -#define DDR_PHY_DTCR0_DTMPR_SHIFT 6 -#define DDR_PHY_DTCR0_DTMPR_MASK 0x00000040U +#define DDR_PHY_DTCR0_DTMPR_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_DTMPR_SHIFT 6 +#define DDR_PHY_DTCR0_DTMPR_MASK 0x00000040U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTCR0_RESERVED_5_4_DEFVAL #undef DDR_PHY_DTCR0_RESERVED_5_4_SHIFT #undef DDR_PHY_DTCR0_RESERVED_5_4_MASK -#define DDR_PHY_DTCR0_RESERVED_5_4_DEFVAL 0x800091C7 -#define DDR_PHY_DTCR0_RESERVED_5_4_SHIFT 4 -#define DDR_PHY_DTCR0_RESERVED_5_4_MASK 0x00000030U +#define DDR_PHY_DTCR0_RESERVED_5_4_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_RESERVED_5_4_SHIFT 4 +#define DDR_PHY_DTCR0_RESERVED_5_4_MASK 0x00000030U -/*Data Training Repeat Number*/ +/* +* Data Training Repeat Number +*/ #undef DDR_PHY_DTCR0_DTRPTN_DEFVAL #undef DDR_PHY_DTCR0_DTRPTN_SHIFT #undef DDR_PHY_DTCR0_DTRPTN_MASK -#define DDR_PHY_DTCR0_DTRPTN_DEFVAL 0x800091C7 -#define DDR_PHY_DTCR0_DTRPTN_SHIFT 0 -#define DDR_PHY_DTCR0_DTRPTN_MASK 0x0000000FU +#define DDR_PHY_DTCR0_DTRPTN_DEFVAL 0x800091C7 +#define DDR_PHY_DTCR0_DTRPTN_SHIFT 0 +#define DDR_PHY_DTCR0_DTRPTN_MASK 0x0000000FU -/*Rank Enable.*/ +/* +* Rank Enable. +*/ #undef DDR_PHY_DTCR1_RANKEN_RSVD_DEFVAL #undef DDR_PHY_DTCR1_RANKEN_RSVD_SHIFT #undef DDR_PHY_DTCR1_RANKEN_RSVD_MASK -#define DDR_PHY_DTCR1_RANKEN_RSVD_DEFVAL 0x00030237 -#define DDR_PHY_DTCR1_RANKEN_RSVD_SHIFT 18 -#define DDR_PHY_DTCR1_RANKEN_RSVD_MASK 0xFFFC0000U +#define DDR_PHY_DTCR1_RANKEN_RSVD_DEFVAL 0x00030237 +#define DDR_PHY_DTCR1_RANKEN_RSVD_SHIFT 18 +#define DDR_PHY_DTCR1_RANKEN_RSVD_MASK 0xFFFC0000U -/*Rank Enable.*/ +/* +* Rank Enable. +*/ #undef DDR_PHY_DTCR1_RANKEN_DEFVAL #undef DDR_PHY_DTCR1_RANKEN_SHIFT #undef DDR_PHY_DTCR1_RANKEN_MASK -#define DDR_PHY_DTCR1_RANKEN_DEFVAL 0x00030237 -#define DDR_PHY_DTCR1_RANKEN_SHIFT 16 -#define DDR_PHY_DTCR1_RANKEN_MASK 0x00030000U +#define DDR_PHY_DTCR1_RANKEN_DEFVAL 0x00030237 +#define DDR_PHY_DTCR1_RANKEN_SHIFT 16 +#define DDR_PHY_DTCR1_RANKEN_MASK 0x00030000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTCR1_RESERVED_15_14_DEFVAL #undef DDR_PHY_DTCR1_RESERVED_15_14_SHIFT #undef DDR_PHY_DTCR1_RESERVED_15_14_MASK -#define DDR_PHY_DTCR1_RESERVED_15_14_DEFVAL 0x00030237 -#define DDR_PHY_DTCR1_RESERVED_15_14_SHIFT 14 -#define DDR_PHY_DTCR1_RESERVED_15_14_MASK 0x0000C000U +#define DDR_PHY_DTCR1_RESERVED_15_14_DEFVAL 0x00030237 +#define DDR_PHY_DTCR1_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_DTCR1_RESERVED_15_14_MASK 0x0000C000U -/*Data Training Rank*/ +/* +* Data Training Rank +*/ #undef DDR_PHY_DTCR1_DTRANK_DEFVAL #undef DDR_PHY_DTCR1_DTRANK_SHIFT #undef DDR_PHY_DTCR1_DTRANK_MASK -#define DDR_PHY_DTCR1_DTRANK_DEFVAL 0x00030237 -#define DDR_PHY_DTCR1_DTRANK_SHIFT 12 -#define DDR_PHY_DTCR1_DTRANK_MASK 0x00003000U +#define DDR_PHY_DTCR1_DTRANK_DEFVAL 0x00030237 +#define DDR_PHY_DTCR1_DTRANK_SHIFT 12 +#define DDR_PHY_DTCR1_DTRANK_MASK 0x00003000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTCR1_RESERVED_11_DEFVAL #undef DDR_PHY_DTCR1_RESERVED_11_SHIFT #undef DDR_PHY_DTCR1_RESERVED_11_MASK -#define DDR_PHY_DTCR1_RESERVED_11_DEFVAL 0x00030237 -#define DDR_PHY_DTCR1_RESERVED_11_SHIFT 11 -#define DDR_PHY_DTCR1_RESERVED_11_MASK 0x00000800U +#define DDR_PHY_DTCR1_RESERVED_11_DEFVAL 0x00030237 +#define DDR_PHY_DTCR1_RESERVED_11_SHIFT 11 +#define DDR_PHY_DTCR1_RESERVED_11_MASK 0x00000800U -/*Read Leveling Gate Sampling Difference*/ +/* +* Read Leveling Gate Sampling Difference +*/ #undef DDR_PHY_DTCR1_RDLVLGDIFF_DEFVAL #undef DDR_PHY_DTCR1_RDLVLGDIFF_SHIFT #undef DDR_PHY_DTCR1_RDLVLGDIFF_MASK -#define DDR_PHY_DTCR1_RDLVLGDIFF_DEFVAL 0x00030237 -#define DDR_PHY_DTCR1_RDLVLGDIFF_SHIFT 8 -#define DDR_PHY_DTCR1_RDLVLGDIFF_MASK 0x00000700U +#define DDR_PHY_DTCR1_RDLVLGDIFF_DEFVAL 0x00030237 +#define DDR_PHY_DTCR1_RDLVLGDIFF_SHIFT 8 +#define DDR_PHY_DTCR1_RDLVLGDIFF_MASK 0x00000700U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTCR1_RESERVED_7_DEFVAL #undef DDR_PHY_DTCR1_RESERVED_7_SHIFT #undef DDR_PHY_DTCR1_RESERVED_7_MASK -#define DDR_PHY_DTCR1_RESERVED_7_DEFVAL 0x00030237 -#define DDR_PHY_DTCR1_RESERVED_7_SHIFT 7 -#define DDR_PHY_DTCR1_RESERVED_7_MASK 0x00000080U +#define DDR_PHY_DTCR1_RESERVED_7_DEFVAL 0x00030237 +#define DDR_PHY_DTCR1_RESERVED_7_SHIFT 7 +#define DDR_PHY_DTCR1_RESERVED_7_MASK 0x00000080U -/*Read Leveling Gate Shift*/ +/* +* Read Leveling Gate Shift +*/ #undef DDR_PHY_DTCR1_RDLVLGS_DEFVAL #undef DDR_PHY_DTCR1_RDLVLGS_SHIFT #undef DDR_PHY_DTCR1_RDLVLGS_MASK -#define DDR_PHY_DTCR1_RDLVLGS_DEFVAL 0x00030237 -#define DDR_PHY_DTCR1_RDLVLGS_SHIFT 4 -#define DDR_PHY_DTCR1_RDLVLGS_MASK 0x00000070U +#define DDR_PHY_DTCR1_RDLVLGS_DEFVAL 0x00030237 +#define DDR_PHY_DTCR1_RDLVLGS_SHIFT 4 +#define DDR_PHY_DTCR1_RDLVLGS_MASK 0x00000070U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DTCR1_RESERVED_3_DEFVAL #undef DDR_PHY_DTCR1_RESERVED_3_SHIFT #undef DDR_PHY_DTCR1_RESERVED_3_MASK -#define DDR_PHY_DTCR1_RESERVED_3_DEFVAL 0x00030237 -#define DDR_PHY_DTCR1_RESERVED_3_SHIFT 3 -#define DDR_PHY_DTCR1_RESERVED_3_MASK 0x00000008U +#define DDR_PHY_DTCR1_RESERVED_3_DEFVAL 0x00030237 +#define DDR_PHY_DTCR1_RESERVED_3_SHIFT 3 +#define DDR_PHY_DTCR1_RESERVED_3_MASK 0x00000008U -/*Read Preamble Training enable*/ +/* +* Read Preamble Training enable +*/ #undef DDR_PHY_DTCR1_RDPRMVL_TRN_DEFVAL #undef DDR_PHY_DTCR1_RDPRMVL_TRN_SHIFT #undef DDR_PHY_DTCR1_RDPRMVL_TRN_MASK -#define DDR_PHY_DTCR1_RDPRMVL_TRN_DEFVAL 0x00030237 -#define DDR_PHY_DTCR1_RDPRMVL_TRN_SHIFT 2 -#define DDR_PHY_DTCR1_RDPRMVL_TRN_MASK 0x00000004U +#define DDR_PHY_DTCR1_RDPRMVL_TRN_DEFVAL 0x00030237 +#define DDR_PHY_DTCR1_RDPRMVL_TRN_SHIFT 2 +#define DDR_PHY_DTCR1_RDPRMVL_TRN_MASK 0x00000004U -/*Read Leveling Enable*/ +/* +* Read Leveling Enable +*/ #undef DDR_PHY_DTCR1_RDLVLEN_DEFVAL #undef DDR_PHY_DTCR1_RDLVLEN_SHIFT #undef DDR_PHY_DTCR1_RDLVLEN_MASK -#define DDR_PHY_DTCR1_RDLVLEN_DEFVAL 0x00030237 -#define DDR_PHY_DTCR1_RDLVLEN_SHIFT 1 -#define DDR_PHY_DTCR1_RDLVLEN_MASK 0x00000002U +#define DDR_PHY_DTCR1_RDLVLEN_DEFVAL 0x00030237 +#define DDR_PHY_DTCR1_RDLVLEN_SHIFT 1 +#define DDR_PHY_DTCR1_RDLVLEN_MASK 0x00000002U -/*Basic Gate Training Enable*/ +/* +* Basic Gate Training Enable +*/ #undef DDR_PHY_DTCR1_BSTEN_DEFVAL #undef DDR_PHY_DTCR1_BSTEN_SHIFT #undef DDR_PHY_DTCR1_BSTEN_MASK -#define DDR_PHY_DTCR1_BSTEN_DEFVAL 0x00030237 -#define DDR_PHY_DTCR1_BSTEN_SHIFT 0 -#define DDR_PHY_DTCR1_BSTEN_MASK 0x00000001U +#define DDR_PHY_DTCR1_BSTEN_DEFVAL 0x00030237 +#define DDR_PHY_DTCR1_BSTEN_SHIFT 0 +#define DDR_PHY_DTCR1_BSTEN_MASK 0x00000001U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_CATR0_RESERVED_31_21_DEFVAL #undef DDR_PHY_CATR0_RESERVED_31_21_SHIFT #undef DDR_PHY_CATR0_RESERVED_31_21_MASK -#define DDR_PHY_CATR0_RESERVED_31_21_DEFVAL 0x00141054 -#define DDR_PHY_CATR0_RESERVED_31_21_SHIFT 21 -#define DDR_PHY_CATR0_RESERVED_31_21_MASK 0xFFE00000U +#define DDR_PHY_CATR0_RESERVED_31_21_DEFVAL 0x00141054 +#define DDR_PHY_CATR0_RESERVED_31_21_SHIFT 21 +#define DDR_PHY_CATR0_RESERVED_31_21_MASK 0xFFE00000U -/*Minimum time (in terms of number of dram clocks) between two consectuve CA calibration command*/ +/* +* Minimum time (in terms of number of dram clocks) between two consectuve + * CA calibration command +*/ #undef DDR_PHY_CATR0_CACD_DEFVAL #undef DDR_PHY_CATR0_CACD_SHIFT #undef DDR_PHY_CATR0_CACD_MASK -#define DDR_PHY_CATR0_CACD_DEFVAL 0x00141054 -#define DDR_PHY_CATR0_CACD_SHIFT 16 -#define DDR_PHY_CATR0_CACD_MASK 0x001F0000U +#define DDR_PHY_CATR0_CACD_DEFVAL 0x00141054 +#define DDR_PHY_CATR0_CACD_SHIFT 16 +#define DDR_PHY_CATR0_CACD_MASK 0x001F0000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_CATR0_RESERVED_15_13_DEFVAL #undef DDR_PHY_CATR0_RESERVED_15_13_SHIFT #undef DDR_PHY_CATR0_RESERVED_15_13_MASK -#define DDR_PHY_CATR0_RESERVED_15_13_DEFVAL 0x00141054 -#define DDR_PHY_CATR0_RESERVED_15_13_SHIFT 13 -#define DDR_PHY_CATR0_RESERVED_15_13_MASK 0x0000E000U +#define DDR_PHY_CATR0_RESERVED_15_13_DEFVAL 0x00141054 +#define DDR_PHY_CATR0_RESERVED_15_13_SHIFT 13 +#define DDR_PHY_CATR0_RESERVED_15_13_MASK 0x0000E000U -/*Minimum time (in terms of number of dram clocks) PUB should wait before sampling the CA response after Calibration command ha - been sent to the memory*/ +/* +* Minimum time (in terms of number of dram clocks) PUB should wait before + * sampling the CA response after Calibration command has been sent to the + * memory +*/ #undef DDR_PHY_CATR0_CAADR_DEFVAL #undef DDR_PHY_CATR0_CAADR_SHIFT #undef DDR_PHY_CATR0_CAADR_MASK -#define DDR_PHY_CATR0_CAADR_DEFVAL 0x00141054 -#define DDR_PHY_CATR0_CAADR_SHIFT 8 -#define DDR_PHY_CATR0_CAADR_MASK 0x00001F00U +#define DDR_PHY_CATR0_CAADR_DEFVAL 0x00141054 +#define DDR_PHY_CATR0_CAADR_SHIFT 8 +#define DDR_PHY_CATR0_CAADR_MASK 0x00001F00U -/*CA_1 Response Byte Lane 1*/ +/* +* CA_1 Response Byte Lane 1 +*/ #undef DDR_PHY_CATR0_CA1BYTE1_DEFVAL #undef DDR_PHY_CATR0_CA1BYTE1_SHIFT #undef DDR_PHY_CATR0_CA1BYTE1_MASK -#define DDR_PHY_CATR0_CA1BYTE1_DEFVAL 0x00141054 -#define DDR_PHY_CATR0_CA1BYTE1_SHIFT 4 -#define DDR_PHY_CATR0_CA1BYTE1_MASK 0x000000F0U +#define DDR_PHY_CATR0_CA1BYTE1_DEFVAL 0x00141054 +#define DDR_PHY_CATR0_CA1BYTE1_SHIFT 4 +#define DDR_PHY_CATR0_CA1BYTE1_MASK 0x000000F0U -/*CA_1 Response Byte Lane 0*/ +/* +* CA_1 Response Byte Lane 0 +*/ #undef DDR_PHY_CATR0_CA1BYTE0_DEFVAL #undef DDR_PHY_CATR0_CA1BYTE0_SHIFT #undef DDR_PHY_CATR0_CA1BYTE0_MASK -#define DDR_PHY_CATR0_CA1BYTE0_DEFVAL 0x00141054 -#define DDR_PHY_CATR0_CA1BYTE0_SHIFT 0 -#define DDR_PHY_CATR0_CA1BYTE0_MASK 0x0000000FU +#define DDR_PHY_CATR0_CA1BYTE0_DEFVAL 0x00141054 +#define DDR_PHY_CATR0_CA1BYTE0_SHIFT 0 +#define DDR_PHY_CATR0_CA1BYTE0_MASK 0x0000000FU -/*LFSR seed for pseudo-random BIST patterns*/ +/* +* Number of delay taps by which the DQS gate LCDL will be updated when DQS + * drift is detected +*/ +#undef DDR_PHY_DQSDR0_DFTDLY_DEFVAL +#undef DDR_PHY_DQSDR0_DFTDLY_SHIFT +#undef DDR_PHY_DQSDR0_DFTDLY_MASK +#define DDR_PHY_DQSDR0_DFTDLY_DEFVAL 0x00088000 +#define DDR_PHY_DQSDR0_DFTDLY_SHIFT 28 +#define DDR_PHY_DQSDR0_DFTDLY_MASK 0xF0000000U + +/* +* Drift Impedance Update +*/ +#undef DDR_PHY_DQSDR0_DFTZQUP_DEFVAL +#undef DDR_PHY_DQSDR0_DFTZQUP_SHIFT +#undef DDR_PHY_DQSDR0_DFTZQUP_MASK +#define DDR_PHY_DQSDR0_DFTZQUP_DEFVAL 0x00088000 +#define DDR_PHY_DQSDR0_DFTZQUP_SHIFT 27 +#define DDR_PHY_DQSDR0_DFTZQUP_MASK 0x08000000U + +/* +* Drift DDL Update +*/ +#undef DDR_PHY_DQSDR0_DFTDDLUP_DEFVAL +#undef DDR_PHY_DQSDR0_DFTDDLUP_SHIFT +#undef DDR_PHY_DQSDR0_DFTDDLUP_MASK +#define DDR_PHY_DQSDR0_DFTDDLUP_DEFVAL 0x00088000 +#define DDR_PHY_DQSDR0_DFTDDLUP_SHIFT 26 +#define DDR_PHY_DQSDR0_DFTDDLUP_MASK 0x04000000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DQSDR0_RESERVED_25_22_DEFVAL +#undef DDR_PHY_DQSDR0_RESERVED_25_22_SHIFT +#undef DDR_PHY_DQSDR0_RESERVED_25_22_MASK +#define DDR_PHY_DQSDR0_RESERVED_25_22_DEFVAL 0x00088000 +#define DDR_PHY_DQSDR0_RESERVED_25_22_SHIFT 22 +#define DDR_PHY_DQSDR0_RESERVED_25_22_MASK 0x03C00000U + +/* +* Drift Read Spacing +*/ +#undef DDR_PHY_DQSDR0_DFTRDSPC_DEFVAL +#undef DDR_PHY_DQSDR0_DFTRDSPC_SHIFT +#undef DDR_PHY_DQSDR0_DFTRDSPC_MASK +#define DDR_PHY_DQSDR0_DFTRDSPC_DEFVAL 0x00088000 +#define DDR_PHY_DQSDR0_DFTRDSPC_SHIFT 20 +#define DDR_PHY_DQSDR0_DFTRDSPC_MASK 0x00300000U + +/* +* Drift Back-to-Back Reads +*/ +#undef DDR_PHY_DQSDR0_DFTB2BRD_DEFVAL +#undef DDR_PHY_DQSDR0_DFTB2BRD_SHIFT +#undef DDR_PHY_DQSDR0_DFTB2BRD_MASK +#define DDR_PHY_DQSDR0_DFTB2BRD_DEFVAL 0x00088000 +#define DDR_PHY_DQSDR0_DFTB2BRD_SHIFT 16 +#define DDR_PHY_DQSDR0_DFTB2BRD_MASK 0x000F0000U + +/* +* Drift Idle Reads +*/ +#undef DDR_PHY_DQSDR0_DFTIDLRD_DEFVAL +#undef DDR_PHY_DQSDR0_DFTIDLRD_SHIFT +#undef DDR_PHY_DQSDR0_DFTIDLRD_MASK +#define DDR_PHY_DQSDR0_DFTIDLRD_DEFVAL 0x00088000 +#define DDR_PHY_DQSDR0_DFTIDLRD_SHIFT 12 +#define DDR_PHY_DQSDR0_DFTIDLRD_MASK 0x0000F000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DQSDR0_RESERVED_11_8_DEFVAL +#undef DDR_PHY_DQSDR0_RESERVED_11_8_SHIFT +#undef DDR_PHY_DQSDR0_RESERVED_11_8_MASK +#define DDR_PHY_DQSDR0_RESERVED_11_8_DEFVAL 0x00088000 +#define DDR_PHY_DQSDR0_RESERVED_11_8_SHIFT 8 +#define DDR_PHY_DQSDR0_RESERVED_11_8_MASK 0x00000F00U + +/* +* Gate Pulse Enable +*/ +#undef DDR_PHY_DQSDR0_DFTGPULSE_DEFVAL +#undef DDR_PHY_DQSDR0_DFTGPULSE_SHIFT +#undef DDR_PHY_DQSDR0_DFTGPULSE_MASK +#define DDR_PHY_DQSDR0_DFTGPULSE_DEFVAL 0x00088000 +#define DDR_PHY_DQSDR0_DFTGPULSE_SHIFT 4 +#define DDR_PHY_DQSDR0_DFTGPULSE_MASK 0x000000F0U + +/* +* DQS Drift Update Mode +*/ +#undef DDR_PHY_DQSDR0_DFTUPMODE_DEFVAL +#undef DDR_PHY_DQSDR0_DFTUPMODE_SHIFT +#undef DDR_PHY_DQSDR0_DFTUPMODE_MASK +#define DDR_PHY_DQSDR0_DFTUPMODE_DEFVAL 0x00088000 +#define DDR_PHY_DQSDR0_DFTUPMODE_SHIFT 2 +#define DDR_PHY_DQSDR0_DFTUPMODE_MASK 0x0000000CU + +/* +* DQS Drift Detection Mode +*/ +#undef DDR_PHY_DQSDR0_DFTDTMODE_DEFVAL +#undef DDR_PHY_DQSDR0_DFTDTMODE_SHIFT +#undef DDR_PHY_DQSDR0_DFTDTMODE_MASK +#define DDR_PHY_DQSDR0_DFTDTMODE_DEFVAL 0x00088000 +#define DDR_PHY_DQSDR0_DFTDTMODE_SHIFT 1 +#define DDR_PHY_DQSDR0_DFTDTMODE_MASK 0x00000002U + +/* +* DQS Drift Detection Enable +*/ +#undef DDR_PHY_DQSDR0_DFTDTEN_DEFVAL +#undef DDR_PHY_DQSDR0_DFTDTEN_SHIFT +#undef DDR_PHY_DQSDR0_DFTDTEN_MASK +#define DDR_PHY_DQSDR0_DFTDTEN_DEFVAL 0x00088000 +#define DDR_PHY_DQSDR0_DFTDTEN_SHIFT 0 +#define DDR_PHY_DQSDR0_DFTDTEN_MASK 0x00000001U + +/* +* LFSR seed for pseudo-random BIST patterns +*/ #undef DDR_PHY_BISTLSR_SEED_DEFVAL #undef DDR_PHY_BISTLSR_SEED_SHIFT #undef DDR_PHY_BISTLSR_SEED_MASK -#define DDR_PHY_BISTLSR_SEED_DEFVAL -#define DDR_PHY_BISTLSR_SEED_SHIFT 0 -#define DDR_PHY_BISTLSR_SEED_MASK 0xFFFFFFFFU +#define DDR_PHY_BISTLSR_SEED_DEFVAL +#define DDR_PHY_BISTLSR_SEED_SHIFT 0 +#define DDR_PHY_BISTLSR_SEED_MASK 0xFFFFFFFFU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_RIOCR5_RESERVED_31_16_DEFVAL #undef DDR_PHY_RIOCR5_RESERVED_31_16_SHIFT #undef DDR_PHY_RIOCR5_RESERVED_31_16_MASK -#define DDR_PHY_RIOCR5_RESERVED_31_16_DEFVAL 0x00000005 -#define DDR_PHY_RIOCR5_RESERVED_31_16_SHIFT 16 -#define DDR_PHY_RIOCR5_RESERVED_31_16_MASK 0xFFFF0000U +#define DDR_PHY_RIOCR5_RESERVED_31_16_DEFVAL 0x00000005 +#define DDR_PHY_RIOCR5_RESERVED_31_16_SHIFT 16 +#define DDR_PHY_RIOCR5_RESERVED_31_16_MASK 0xFFFF0000U -/*Reserved. Return zeros on reads.*/ +/* +* Reserved. Return zeros on reads. +*/ #undef DDR_PHY_RIOCR5_ODTOEMODE_RSVD_DEFVAL #undef DDR_PHY_RIOCR5_ODTOEMODE_RSVD_SHIFT #undef DDR_PHY_RIOCR5_ODTOEMODE_RSVD_MASK -#define DDR_PHY_RIOCR5_ODTOEMODE_RSVD_DEFVAL 0x00000005 -#define DDR_PHY_RIOCR5_ODTOEMODE_RSVD_SHIFT 4 -#define DDR_PHY_RIOCR5_ODTOEMODE_RSVD_MASK 0x0000FFF0U +#define DDR_PHY_RIOCR5_ODTOEMODE_RSVD_DEFVAL 0x00000005 +#define DDR_PHY_RIOCR5_ODTOEMODE_RSVD_SHIFT 4 +#define DDR_PHY_RIOCR5_ODTOEMODE_RSVD_MASK 0x0000FFF0U -/*SDRAM On-die Termination Output Enable (OE) Mode Selection.*/ +/* +* SDRAM On-die Termination Output Enable (OE) Mode Selection. +*/ #undef DDR_PHY_RIOCR5_ODTOEMODE_DEFVAL #undef DDR_PHY_RIOCR5_ODTOEMODE_SHIFT #undef DDR_PHY_RIOCR5_ODTOEMODE_MASK -#define DDR_PHY_RIOCR5_ODTOEMODE_DEFVAL 0x00000005 -#define DDR_PHY_RIOCR5_ODTOEMODE_SHIFT 0 -#define DDR_PHY_RIOCR5_ODTOEMODE_MASK 0x0000000FU +#define DDR_PHY_RIOCR5_ODTOEMODE_DEFVAL 0x00000005 +#define DDR_PHY_RIOCR5_ODTOEMODE_SHIFT 0 +#define DDR_PHY_RIOCR5_ODTOEMODE_MASK 0x0000000FU -/*Address/Command Slew Rate (D3F I/O Only)*/ +/* +* Address/Command Slew Rate (D3F I/O Only) +*/ #undef DDR_PHY_ACIOCR0_ACSR_DEFVAL #undef DDR_PHY_ACIOCR0_ACSR_SHIFT #undef DDR_PHY_ACIOCR0_ACSR_MASK -#define DDR_PHY_ACIOCR0_ACSR_DEFVAL 0x30000000 -#define DDR_PHY_ACIOCR0_ACSR_SHIFT 30 -#define DDR_PHY_ACIOCR0_ACSR_MASK 0xC0000000U +#define DDR_PHY_ACIOCR0_ACSR_DEFVAL 0x30000000 +#define DDR_PHY_ACIOCR0_ACSR_SHIFT 30 +#define DDR_PHY_ACIOCR0_ACSR_MASK 0xC0000000U -/*SDRAM Reset I/O Mode*/ +/* +* SDRAM Reset I/O Mode +*/ #undef DDR_PHY_ACIOCR0_RSTIOM_DEFVAL #undef DDR_PHY_ACIOCR0_RSTIOM_SHIFT #undef DDR_PHY_ACIOCR0_RSTIOM_MASK -#define DDR_PHY_ACIOCR0_RSTIOM_DEFVAL 0x30000000 -#define DDR_PHY_ACIOCR0_RSTIOM_SHIFT 29 -#define DDR_PHY_ACIOCR0_RSTIOM_MASK 0x20000000U +#define DDR_PHY_ACIOCR0_RSTIOM_DEFVAL 0x30000000 +#define DDR_PHY_ACIOCR0_RSTIOM_SHIFT 29 +#define DDR_PHY_ACIOCR0_RSTIOM_MASK 0x20000000U -/*SDRAM Reset Power Down Receiver*/ +/* +* SDRAM Reset Power Down Receiver +*/ #undef DDR_PHY_ACIOCR0_RSTPDR_DEFVAL #undef DDR_PHY_ACIOCR0_RSTPDR_SHIFT #undef DDR_PHY_ACIOCR0_RSTPDR_MASK -#define DDR_PHY_ACIOCR0_RSTPDR_DEFVAL 0x30000000 -#define DDR_PHY_ACIOCR0_RSTPDR_SHIFT 28 -#define DDR_PHY_ACIOCR0_RSTPDR_MASK 0x10000000U +#define DDR_PHY_ACIOCR0_RSTPDR_DEFVAL 0x30000000 +#define DDR_PHY_ACIOCR0_RSTPDR_SHIFT 28 +#define DDR_PHY_ACIOCR0_RSTPDR_MASK 0x10000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACIOCR0_RESERVED_27_DEFVAL #undef DDR_PHY_ACIOCR0_RESERVED_27_SHIFT #undef DDR_PHY_ACIOCR0_RESERVED_27_MASK -#define DDR_PHY_ACIOCR0_RESERVED_27_DEFVAL 0x30000000 -#define DDR_PHY_ACIOCR0_RESERVED_27_SHIFT 27 -#define DDR_PHY_ACIOCR0_RESERVED_27_MASK 0x08000000U +#define DDR_PHY_ACIOCR0_RESERVED_27_DEFVAL 0x30000000 +#define DDR_PHY_ACIOCR0_RESERVED_27_SHIFT 27 +#define DDR_PHY_ACIOCR0_RESERVED_27_MASK 0x08000000U -/*SDRAM Reset On-Die Termination*/ +/* +* SDRAM Reset On-Die Termination +*/ #undef DDR_PHY_ACIOCR0_RSTODT_DEFVAL #undef DDR_PHY_ACIOCR0_RSTODT_SHIFT #undef DDR_PHY_ACIOCR0_RSTODT_MASK -#define DDR_PHY_ACIOCR0_RSTODT_DEFVAL 0x30000000 -#define DDR_PHY_ACIOCR0_RSTODT_SHIFT 26 -#define DDR_PHY_ACIOCR0_RSTODT_MASK 0x04000000U +#define DDR_PHY_ACIOCR0_RSTODT_DEFVAL 0x30000000 +#define DDR_PHY_ACIOCR0_RSTODT_SHIFT 26 +#define DDR_PHY_ACIOCR0_RSTODT_MASK 0x04000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACIOCR0_RESERVED_25_10_DEFVAL #undef DDR_PHY_ACIOCR0_RESERVED_25_10_SHIFT #undef DDR_PHY_ACIOCR0_RESERVED_25_10_MASK -#define DDR_PHY_ACIOCR0_RESERVED_25_10_DEFVAL 0x30000000 -#define DDR_PHY_ACIOCR0_RESERVED_25_10_SHIFT 10 -#define DDR_PHY_ACIOCR0_RESERVED_25_10_MASK 0x03FFFC00U +#define DDR_PHY_ACIOCR0_RESERVED_25_10_DEFVAL 0x30000000 +#define DDR_PHY_ACIOCR0_RESERVED_25_10_SHIFT 10 +#define DDR_PHY_ACIOCR0_RESERVED_25_10_MASK 0x03FFFC00U -/*CK Duty Cycle Correction*/ +/* +* CK Duty Cycle Correction +*/ #undef DDR_PHY_ACIOCR0_CKDCC_DEFVAL #undef DDR_PHY_ACIOCR0_CKDCC_SHIFT #undef DDR_PHY_ACIOCR0_CKDCC_MASK -#define DDR_PHY_ACIOCR0_CKDCC_DEFVAL 0x30000000 -#define DDR_PHY_ACIOCR0_CKDCC_SHIFT 6 -#define DDR_PHY_ACIOCR0_CKDCC_MASK 0x000003C0U +#define DDR_PHY_ACIOCR0_CKDCC_DEFVAL 0x30000000 +#define DDR_PHY_ACIOCR0_CKDCC_SHIFT 6 +#define DDR_PHY_ACIOCR0_CKDCC_MASK 0x000003C0U -/*AC Power Down Receiver Mode*/ +/* +* AC Power Down Receiver Mode +*/ #undef DDR_PHY_ACIOCR0_ACPDRMODE_DEFVAL #undef DDR_PHY_ACIOCR0_ACPDRMODE_SHIFT #undef DDR_PHY_ACIOCR0_ACPDRMODE_MASK -#define DDR_PHY_ACIOCR0_ACPDRMODE_DEFVAL 0x30000000 -#define DDR_PHY_ACIOCR0_ACPDRMODE_SHIFT 4 -#define DDR_PHY_ACIOCR0_ACPDRMODE_MASK 0x00000030U +#define DDR_PHY_ACIOCR0_ACPDRMODE_DEFVAL 0x30000000 +#define DDR_PHY_ACIOCR0_ACPDRMODE_SHIFT 4 +#define DDR_PHY_ACIOCR0_ACPDRMODE_MASK 0x00000030U -/*AC On-die Termination Mode*/ +/* +* AC On-die Termination Mode +*/ #undef DDR_PHY_ACIOCR0_ACODTMODE_DEFVAL #undef DDR_PHY_ACIOCR0_ACODTMODE_SHIFT #undef DDR_PHY_ACIOCR0_ACODTMODE_MASK -#define DDR_PHY_ACIOCR0_ACODTMODE_DEFVAL 0x30000000 -#define DDR_PHY_ACIOCR0_ACODTMODE_SHIFT 2 -#define DDR_PHY_ACIOCR0_ACODTMODE_MASK 0x0000000CU +#define DDR_PHY_ACIOCR0_ACODTMODE_DEFVAL 0x30000000 +#define DDR_PHY_ACIOCR0_ACODTMODE_SHIFT 2 +#define DDR_PHY_ACIOCR0_ACODTMODE_MASK 0x0000000CU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACIOCR0_RESERVED_1_DEFVAL #undef DDR_PHY_ACIOCR0_RESERVED_1_SHIFT #undef DDR_PHY_ACIOCR0_RESERVED_1_MASK -#define DDR_PHY_ACIOCR0_RESERVED_1_DEFVAL 0x30000000 -#define DDR_PHY_ACIOCR0_RESERVED_1_SHIFT 1 -#define DDR_PHY_ACIOCR0_RESERVED_1_MASK 0x00000002U +#define DDR_PHY_ACIOCR0_RESERVED_1_DEFVAL 0x30000000 +#define DDR_PHY_ACIOCR0_RESERVED_1_SHIFT 1 +#define DDR_PHY_ACIOCR0_RESERVED_1_MASK 0x00000002U -/*Control delayed or non-delayed clock to CS_N/ODT?CKE AC slices.*/ +/* +* Control delayed or non-delayed clock to CS_N/ODT?CKE AC slices. +*/ #undef DDR_PHY_ACIOCR0_ACRANKCLKSEL_DEFVAL #undef DDR_PHY_ACIOCR0_ACRANKCLKSEL_SHIFT #undef DDR_PHY_ACIOCR0_ACRANKCLKSEL_MASK -#define DDR_PHY_ACIOCR0_ACRANKCLKSEL_DEFVAL 0x30000000 -#define DDR_PHY_ACIOCR0_ACRANKCLKSEL_SHIFT 0 -#define DDR_PHY_ACIOCR0_ACRANKCLKSEL_MASK 0x00000001U +#define DDR_PHY_ACIOCR0_ACRANKCLKSEL_DEFVAL 0x30000000 +#define DDR_PHY_ACIOCR0_ACRANKCLKSEL_SHIFT 0 +#define DDR_PHY_ACIOCR0_ACRANKCLKSEL_MASK 0x00000001U -/*Clock gating for glue logic inside CLKGEN and glue logic inside CONTROL slice*/ +/* +* Clock gating for glue logic inside CLKGEN and glue logic inside CONTROL + * slice +*/ #undef DDR_PHY_ACIOCR2_CLKGENCLKGATE_DEFVAL #undef DDR_PHY_ACIOCR2_CLKGENCLKGATE_SHIFT #undef DDR_PHY_ACIOCR2_CLKGENCLKGATE_MASK -#define DDR_PHY_ACIOCR2_CLKGENCLKGATE_DEFVAL 0x00000000 -#define DDR_PHY_ACIOCR2_CLKGENCLKGATE_SHIFT 31 -#define DDR_PHY_ACIOCR2_CLKGENCLKGATE_MASK 0x80000000U +#define DDR_PHY_ACIOCR2_CLKGENCLKGATE_DEFVAL 0x00000000 +#define DDR_PHY_ACIOCR2_CLKGENCLKGATE_SHIFT 31 +#define DDR_PHY_ACIOCR2_CLKGENCLKGATE_MASK 0x80000000U -/*Clock gating for Output Enable D slices [0]*/ +/* +* Clock gating for Output Enable D slices [0] +*/ #undef DDR_PHY_ACIOCR2_ACOECLKGATE0_DEFVAL #undef DDR_PHY_ACIOCR2_ACOECLKGATE0_SHIFT #undef DDR_PHY_ACIOCR2_ACOECLKGATE0_MASK -#define DDR_PHY_ACIOCR2_ACOECLKGATE0_DEFVAL 0x00000000 -#define DDR_PHY_ACIOCR2_ACOECLKGATE0_SHIFT 30 -#define DDR_PHY_ACIOCR2_ACOECLKGATE0_MASK 0x40000000U +#define DDR_PHY_ACIOCR2_ACOECLKGATE0_DEFVAL 0x00000000 +#define DDR_PHY_ACIOCR2_ACOECLKGATE0_SHIFT 30 +#define DDR_PHY_ACIOCR2_ACOECLKGATE0_MASK 0x40000000U -/*Clock gating for Power Down Receiver D slices [0]*/ +/* +* Clock gating for Power Down Receiver D slices [0] +*/ #undef DDR_PHY_ACIOCR2_ACPDRCLKGATE0_DEFVAL #undef DDR_PHY_ACIOCR2_ACPDRCLKGATE0_SHIFT #undef DDR_PHY_ACIOCR2_ACPDRCLKGATE0_MASK -#define DDR_PHY_ACIOCR2_ACPDRCLKGATE0_DEFVAL 0x00000000 -#define DDR_PHY_ACIOCR2_ACPDRCLKGATE0_SHIFT 29 -#define DDR_PHY_ACIOCR2_ACPDRCLKGATE0_MASK 0x20000000U +#define DDR_PHY_ACIOCR2_ACPDRCLKGATE0_DEFVAL 0x00000000 +#define DDR_PHY_ACIOCR2_ACPDRCLKGATE0_SHIFT 29 +#define DDR_PHY_ACIOCR2_ACPDRCLKGATE0_MASK 0x20000000U -/*Clock gating for Termination Enable D slices [0]*/ +/* +* Clock gating for Termination Enable D slices [0] +*/ #undef DDR_PHY_ACIOCR2_ACTECLKGATE0_DEFVAL #undef DDR_PHY_ACIOCR2_ACTECLKGATE0_SHIFT #undef DDR_PHY_ACIOCR2_ACTECLKGATE0_MASK -#define DDR_PHY_ACIOCR2_ACTECLKGATE0_DEFVAL 0x00000000 -#define DDR_PHY_ACIOCR2_ACTECLKGATE0_SHIFT 28 -#define DDR_PHY_ACIOCR2_ACTECLKGATE0_MASK 0x10000000U +#define DDR_PHY_ACIOCR2_ACTECLKGATE0_DEFVAL 0x00000000 +#define DDR_PHY_ACIOCR2_ACTECLKGATE0_SHIFT 28 +#define DDR_PHY_ACIOCR2_ACTECLKGATE0_MASK 0x10000000U -/*Clock gating for CK# D slices [1:0]*/ +/* +* Clock gating for CK# D slices [1:0] +*/ #undef DDR_PHY_ACIOCR2_CKNCLKGATE0_DEFVAL #undef DDR_PHY_ACIOCR2_CKNCLKGATE0_SHIFT #undef DDR_PHY_ACIOCR2_CKNCLKGATE0_MASK -#define DDR_PHY_ACIOCR2_CKNCLKGATE0_DEFVAL 0x00000000 -#define DDR_PHY_ACIOCR2_CKNCLKGATE0_SHIFT 26 -#define DDR_PHY_ACIOCR2_CKNCLKGATE0_MASK 0x0C000000U +#define DDR_PHY_ACIOCR2_CKNCLKGATE0_DEFVAL 0x00000000 +#define DDR_PHY_ACIOCR2_CKNCLKGATE0_SHIFT 26 +#define DDR_PHY_ACIOCR2_CKNCLKGATE0_MASK 0x0C000000U -/*Clock gating for CK D slices [1:0]*/ +/* +* Clock gating for CK D slices [1:0] +*/ #undef DDR_PHY_ACIOCR2_CKCLKGATE0_DEFVAL #undef DDR_PHY_ACIOCR2_CKCLKGATE0_SHIFT #undef DDR_PHY_ACIOCR2_CKCLKGATE0_MASK -#define DDR_PHY_ACIOCR2_CKCLKGATE0_DEFVAL 0x00000000 -#define DDR_PHY_ACIOCR2_CKCLKGATE0_SHIFT 24 -#define DDR_PHY_ACIOCR2_CKCLKGATE0_MASK 0x03000000U +#define DDR_PHY_ACIOCR2_CKCLKGATE0_DEFVAL 0x00000000 +#define DDR_PHY_ACIOCR2_CKCLKGATE0_SHIFT 24 +#define DDR_PHY_ACIOCR2_CKCLKGATE0_MASK 0x03000000U -/*Clock gating for AC D slices [23:0]*/ +/* +* Clock gating for AC D slices [23:0] +*/ #undef DDR_PHY_ACIOCR2_ACCLKGATE0_DEFVAL #undef DDR_PHY_ACIOCR2_ACCLKGATE0_SHIFT #undef DDR_PHY_ACIOCR2_ACCLKGATE0_MASK -#define DDR_PHY_ACIOCR2_ACCLKGATE0_DEFVAL 0x00000000 -#define DDR_PHY_ACIOCR2_ACCLKGATE0_SHIFT 0 -#define DDR_PHY_ACIOCR2_ACCLKGATE0_MASK 0x00FFFFFFU +#define DDR_PHY_ACIOCR2_ACCLKGATE0_DEFVAL 0x00000000 +#define DDR_PHY_ACIOCR2_ACCLKGATE0_SHIFT 0 +#define DDR_PHY_ACIOCR2_ACCLKGATE0_MASK 0x00FFFFFFU -/*SDRAM Parity Output Enable (OE) Mode Selection*/ +/* +* SDRAM Parity Output Enable (OE) Mode Selection +*/ #undef DDR_PHY_ACIOCR3_PAROEMODE_DEFVAL #undef DDR_PHY_ACIOCR3_PAROEMODE_SHIFT #undef DDR_PHY_ACIOCR3_PAROEMODE_MASK -#define DDR_PHY_ACIOCR3_PAROEMODE_DEFVAL 0x00000005 -#define DDR_PHY_ACIOCR3_PAROEMODE_SHIFT 30 -#define DDR_PHY_ACIOCR3_PAROEMODE_MASK 0xC0000000U +#define DDR_PHY_ACIOCR3_PAROEMODE_DEFVAL 0x00000005 +#define DDR_PHY_ACIOCR3_PAROEMODE_SHIFT 30 +#define DDR_PHY_ACIOCR3_PAROEMODE_MASK 0xC0000000U -/*SDRAM Bank Group Output Enable (OE) Mode Selection*/ +/* +* SDRAM Bank Group Output Enable (OE) Mode Selection +*/ #undef DDR_PHY_ACIOCR3_BGOEMODE_DEFVAL #undef DDR_PHY_ACIOCR3_BGOEMODE_SHIFT #undef DDR_PHY_ACIOCR3_BGOEMODE_MASK -#define DDR_PHY_ACIOCR3_BGOEMODE_DEFVAL 0x00000005 -#define DDR_PHY_ACIOCR3_BGOEMODE_SHIFT 26 -#define DDR_PHY_ACIOCR3_BGOEMODE_MASK 0x3C000000U +#define DDR_PHY_ACIOCR3_BGOEMODE_DEFVAL 0x00000005 +#define DDR_PHY_ACIOCR3_BGOEMODE_SHIFT 26 +#define DDR_PHY_ACIOCR3_BGOEMODE_MASK 0x3C000000U -/*SDRAM Bank Address Output Enable (OE) Mode Selection*/ +/* +* SDRAM Bank Address Output Enable (OE) Mode Selection +*/ #undef DDR_PHY_ACIOCR3_BAOEMODE_DEFVAL #undef DDR_PHY_ACIOCR3_BAOEMODE_SHIFT #undef DDR_PHY_ACIOCR3_BAOEMODE_MASK -#define DDR_PHY_ACIOCR3_BAOEMODE_DEFVAL 0x00000005 -#define DDR_PHY_ACIOCR3_BAOEMODE_SHIFT 22 -#define DDR_PHY_ACIOCR3_BAOEMODE_MASK 0x03C00000U +#define DDR_PHY_ACIOCR3_BAOEMODE_DEFVAL 0x00000005 +#define DDR_PHY_ACIOCR3_BAOEMODE_SHIFT 22 +#define DDR_PHY_ACIOCR3_BAOEMODE_MASK 0x03C00000U -/*SDRAM A[17] Output Enable (OE) Mode Selection*/ +/* +* SDRAM A[17] Output Enable (OE) Mode Selection +*/ #undef DDR_PHY_ACIOCR3_A17OEMODE_DEFVAL #undef DDR_PHY_ACIOCR3_A17OEMODE_SHIFT #undef DDR_PHY_ACIOCR3_A17OEMODE_MASK -#define DDR_PHY_ACIOCR3_A17OEMODE_DEFVAL 0x00000005 -#define DDR_PHY_ACIOCR3_A17OEMODE_SHIFT 20 -#define DDR_PHY_ACIOCR3_A17OEMODE_MASK 0x00300000U +#define DDR_PHY_ACIOCR3_A17OEMODE_DEFVAL 0x00000005 +#define DDR_PHY_ACIOCR3_A17OEMODE_SHIFT 20 +#define DDR_PHY_ACIOCR3_A17OEMODE_MASK 0x00300000U -/*SDRAM A[16] / RAS_n Output Enable (OE) Mode Selection*/ +/* +* SDRAM A[16] / RAS_n Output Enable (OE) Mode Selection +*/ #undef DDR_PHY_ACIOCR3_A16OEMODE_DEFVAL #undef DDR_PHY_ACIOCR3_A16OEMODE_SHIFT #undef DDR_PHY_ACIOCR3_A16OEMODE_MASK -#define DDR_PHY_ACIOCR3_A16OEMODE_DEFVAL 0x00000005 -#define DDR_PHY_ACIOCR3_A16OEMODE_SHIFT 18 -#define DDR_PHY_ACIOCR3_A16OEMODE_MASK 0x000C0000U +#define DDR_PHY_ACIOCR3_A16OEMODE_DEFVAL 0x00000005 +#define DDR_PHY_ACIOCR3_A16OEMODE_SHIFT 18 +#define DDR_PHY_ACIOCR3_A16OEMODE_MASK 0x000C0000U -/*SDRAM ACT_n Output Enable (OE) Mode Selection (DDR4 only)*/ +/* +* SDRAM ACT_n Output Enable (OE) Mode Selection (DDR4 only) +*/ #undef DDR_PHY_ACIOCR3_ACTOEMODE_DEFVAL #undef DDR_PHY_ACIOCR3_ACTOEMODE_SHIFT #undef DDR_PHY_ACIOCR3_ACTOEMODE_MASK -#define DDR_PHY_ACIOCR3_ACTOEMODE_DEFVAL 0x00000005 -#define DDR_PHY_ACIOCR3_ACTOEMODE_SHIFT 16 -#define DDR_PHY_ACIOCR3_ACTOEMODE_MASK 0x00030000U +#define DDR_PHY_ACIOCR3_ACTOEMODE_DEFVAL 0x00000005 +#define DDR_PHY_ACIOCR3_ACTOEMODE_SHIFT 16 +#define DDR_PHY_ACIOCR3_ACTOEMODE_MASK 0x00030000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACIOCR3_RESERVED_15_8_DEFVAL #undef DDR_PHY_ACIOCR3_RESERVED_15_8_SHIFT #undef DDR_PHY_ACIOCR3_RESERVED_15_8_MASK -#define DDR_PHY_ACIOCR3_RESERVED_15_8_DEFVAL 0x00000005 -#define DDR_PHY_ACIOCR3_RESERVED_15_8_SHIFT 8 -#define DDR_PHY_ACIOCR3_RESERVED_15_8_MASK 0x0000FF00U +#define DDR_PHY_ACIOCR3_RESERVED_15_8_DEFVAL 0x00000005 +#define DDR_PHY_ACIOCR3_RESERVED_15_8_SHIFT 8 +#define DDR_PHY_ACIOCR3_RESERVED_15_8_MASK 0x0000FF00U -/*Reserved. Return zeros on reads.*/ +/* +* Reserved. Return zeros on reads. +*/ #undef DDR_PHY_ACIOCR3_CKOEMODE_RSVD_DEFVAL #undef DDR_PHY_ACIOCR3_CKOEMODE_RSVD_SHIFT #undef DDR_PHY_ACIOCR3_CKOEMODE_RSVD_MASK -#define DDR_PHY_ACIOCR3_CKOEMODE_RSVD_DEFVAL 0x00000005 -#define DDR_PHY_ACIOCR3_CKOEMODE_RSVD_SHIFT 4 -#define DDR_PHY_ACIOCR3_CKOEMODE_RSVD_MASK 0x000000F0U +#define DDR_PHY_ACIOCR3_CKOEMODE_RSVD_DEFVAL 0x00000005 +#define DDR_PHY_ACIOCR3_CKOEMODE_RSVD_SHIFT 4 +#define DDR_PHY_ACIOCR3_CKOEMODE_RSVD_MASK 0x000000F0U -/*SDRAM CK Output Enable (OE) Mode Selection.*/ +/* +* SDRAM CK Output Enable (OE) Mode Selection. +*/ #undef DDR_PHY_ACIOCR3_CKOEMODE_DEFVAL #undef DDR_PHY_ACIOCR3_CKOEMODE_SHIFT #undef DDR_PHY_ACIOCR3_CKOEMODE_MASK -#define DDR_PHY_ACIOCR3_CKOEMODE_DEFVAL 0x00000005 -#define DDR_PHY_ACIOCR3_CKOEMODE_SHIFT 0 -#define DDR_PHY_ACIOCR3_CKOEMODE_MASK 0x0000000FU +#define DDR_PHY_ACIOCR3_CKOEMODE_DEFVAL 0x00000005 +#define DDR_PHY_ACIOCR3_CKOEMODE_SHIFT 0 +#define DDR_PHY_ACIOCR3_CKOEMODE_MASK 0x0000000FU -/*Clock gating for AC LB slices and loopback read valid slices*/ +/* +* Clock gating for AC LB slices and loopback read valid slices +*/ #undef DDR_PHY_ACIOCR4_LBCLKGATE_DEFVAL #undef DDR_PHY_ACIOCR4_LBCLKGATE_SHIFT #undef DDR_PHY_ACIOCR4_LBCLKGATE_MASK -#define DDR_PHY_ACIOCR4_LBCLKGATE_DEFVAL 0x00000000 -#define DDR_PHY_ACIOCR4_LBCLKGATE_SHIFT 31 -#define DDR_PHY_ACIOCR4_LBCLKGATE_MASK 0x80000000U +#define DDR_PHY_ACIOCR4_LBCLKGATE_DEFVAL 0x00000000 +#define DDR_PHY_ACIOCR4_LBCLKGATE_SHIFT 31 +#define DDR_PHY_ACIOCR4_LBCLKGATE_MASK 0x80000000U -/*Clock gating for Output Enable D slices [1]*/ +/* +* Clock gating for Output Enable D slices [1] +*/ #undef DDR_PHY_ACIOCR4_ACOECLKGATE1_DEFVAL #undef DDR_PHY_ACIOCR4_ACOECLKGATE1_SHIFT #undef DDR_PHY_ACIOCR4_ACOECLKGATE1_MASK -#define DDR_PHY_ACIOCR4_ACOECLKGATE1_DEFVAL 0x00000000 -#define DDR_PHY_ACIOCR4_ACOECLKGATE1_SHIFT 30 -#define DDR_PHY_ACIOCR4_ACOECLKGATE1_MASK 0x40000000U +#define DDR_PHY_ACIOCR4_ACOECLKGATE1_DEFVAL 0x00000000 +#define DDR_PHY_ACIOCR4_ACOECLKGATE1_SHIFT 30 +#define DDR_PHY_ACIOCR4_ACOECLKGATE1_MASK 0x40000000U -/*Clock gating for Power Down Receiver D slices [1]*/ +/* +* Clock gating for Power Down Receiver D slices [1] +*/ #undef DDR_PHY_ACIOCR4_ACPDRCLKGATE1_DEFVAL #undef DDR_PHY_ACIOCR4_ACPDRCLKGATE1_SHIFT #undef DDR_PHY_ACIOCR4_ACPDRCLKGATE1_MASK -#define DDR_PHY_ACIOCR4_ACPDRCLKGATE1_DEFVAL 0x00000000 -#define DDR_PHY_ACIOCR4_ACPDRCLKGATE1_SHIFT 29 -#define DDR_PHY_ACIOCR4_ACPDRCLKGATE1_MASK 0x20000000U +#define DDR_PHY_ACIOCR4_ACPDRCLKGATE1_DEFVAL 0x00000000 +#define DDR_PHY_ACIOCR4_ACPDRCLKGATE1_SHIFT 29 +#define DDR_PHY_ACIOCR4_ACPDRCLKGATE1_MASK 0x20000000U -/*Clock gating for Termination Enable D slices [1]*/ +/* +* Clock gating for Termination Enable D slices [1] +*/ #undef DDR_PHY_ACIOCR4_ACTECLKGATE1_DEFVAL #undef DDR_PHY_ACIOCR4_ACTECLKGATE1_SHIFT #undef DDR_PHY_ACIOCR4_ACTECLKGATE1_MASK -#define DDR_PHY_ACIOCR4_ACTECLKGATE1_DEFVAL 0x00000000 -#define DDR_PHY_ACIOCR4_ACTECLKGATE1_SHIFT 28 -#define DDR_PHY_ACIOCR4_ACTECLKGATE1_MASK 0x10000000U +#define DDR_PHY_ACIOCR4_ACTECLKGATE1_DEFVAL 0x00000000 +#define DDR_PHY_ACIOCR4_ACTECLKGATE1_SHIFT 28 +#define DDR_PHY_ACIOCR4_ACTECLKGATE1_MASK 0x10000000U -/*Clock gating for CK# D slices [3:2]*/ +/* +* Clock gating for CK# D slices [3:2] +*/ #undef DDR_PHY_ACIOCR4_CKNCLKGATE1_DEFVAL #undef DDR_PHY_ACIOCR4_CKNCLKGATE1_SHIFT #undef DDR_PHY_ACIOCR4_CKNCLKGATE1_MASK -#define DDR_PHY_ACIOCR4_CKNCLKGATE1_DEFVAL 0x00000000 -#define DDR_PHY_ACIOCR4_CKNCLKGATE1_SHIFT 26 -#define DDR_PHY_ACIOCR4_CKNCLKGATE1_MASK 0x0C000000U +#define DDR_PHY_ACIOCR4_CKNCLKGATE1_DEFVAL 0x00000000 +#define DDR_PHY_ACIOCR4_CKNCLKGATE1_SHIFT 26 +#define DDR_PHY_ACIOCR4_CKNCLKGATE1_MASK 0x0C000000U -/*Clock gating for CK D slices [3:2]*/ +/* +* Clock gating for CK D slices [3:2] +*/ #undef DDR_PHY_ACIOCR4_CKCLKGATE1_DEFVAL #undef DDR_PHY_ACIOCR4_CKCLKGATE1_SHIFT #undef DDR_PHY_ACIOCR4_CKCLKGATE1_MASK -#define DDR_PHY_ACIOCR4_CKCLKGATE1_DEFVAL 0x00000000 -#define DDR_PHY_ACIOCR4_CKCLKGATE1_SHIFT 24 -#define DDR_PHY_ACIOCR4_CKCLKGATE1_MASK 0x03000000U +#define DDR_PHY_ACIOCR4_CKCLKGATE1_DEFVAL 0x00000000 +#define DDR_PHY_ACIOCR4_CKCLKGATE1_SHIFT 24 +#define DDR_PHY_ACIOCR4_CKCLKGATE1_MASK 0x03000000U -/*Clock gating for AC D slices [47:24]*/ +/* +* Clock gating for AC D slices [47:24] +*/ #undef DDR_PHY_ACIOCR4_ACCLKGATE1_DEFVAL #undef DDR_PHY_ACIOCR4_ACCLKGATE1_SHIFT #undef DDR_PHY_ACIOCR4_ACCLKGATE1_MASK -#define DDR_PHY_ACIOCR4_ACCLKGATE1_DEFVAL 0x00000000 -#define DDR_PHY_ACIOCR4_ACCLKGATE1_SHIFT 0 -#define DDR_PHY_ACIOCR4_ACCLKGATE1_MASK 0x00FFFFFFU +#define DDR_PHY_ACIOCR4_ACCLKGATE1_DEFVAL 0x00000000 +#define DDR_PHY_ACIOCR4_ACCLKGATE1_SHIFT 0 +#define DDR_PHY_ACIOCR4_ACCLKGATE1_MASK 0x00FFFFFFU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_IOVCR0_RESERVED_31_29_DEFVAL #undef DDR_PHY_IOVCR0_RESERVED_31_29_SHIFT #undef DDR_PHY_IOVCR0_RESERVED_31_29_MASK -#define DDR_PHY_IOVCR0_RESERVED_31_29_DEFVAL 0x0F000000 -#define DDR_PHY_IOVCR0_RESERVED_31_29_SHIFT 29 -#define DDR_PHY_IOVCR0_RESERVED_31_29_MASK 0xE0000000U +#define DDR_PHY_IOVCR0_RESERVED_31_29_DEFVAL 0x0F000000 +#define DDR_PHY_IOVCR0_RESERVED_31_29_SHIFT 29 +#define DDR_PHY_IOVCR0_RESERVED_31_29_MASK 0xE0000000U -/*Address/command lane VREF Pad Enable*/ +/* +* Address/command lane VREF Pad Enable +*/ #undef DDR_PHY_IOVCR0_ACREFPEN_DEFVAL #undef DDR_PHY_IOVCR0_ACREFPEN_SHIFT #undef DDR_PHY_IOVCR0_ACREFPEN_MASK -#define DDR_PHY_IOVCR0_ACREFPEN_DEFVAL 0x0F000000 -#define DDR_PHY_IOVCR0_ACREFPEN_SHIFT 28 -#define DDR_PHY_IOVCR0_ACREFPEN_MASK 0x10000000U +#define DDR_PHY_IOVCR0_ACREFPEN_DEFVAL 0x0F000000 +#define DDR_PHY_IOVCR0_ACREFPEN_SHIFT 28 +#define DDR_PHY_IOVCR0_ACREFPEN_MASK 0x10000000U -/*Address/command lane Internal VREF Enable*/ +/* +* Address/command lane Internal VREF Enable +*/ #undef DDR_PHY_IOVCR0_ACREFEEN_DEFVAL #undef DDR_PHY_IOVCR0_ACREFEEN_SHIFT #undef DDR_PHY_IOVCR0_ACREFEEN_MASK -#define DDR_PHY_IOVCR0_ACREFEEN_DEFVAL 0x0F000000 -#define DDR_PHY_IOVCR0_ACREFEEN_SHIFT 26 -#define DDR_PHY_IOVCR0_ACREFEEN_MASK 0x0C000000U +#define DDR_PHY_IOVCR0_ACREFEEN_DEFVAL 0x0F000000 +#define DDR_PHY_IOVCR0_ACREFEEN_SHIFT 26 +#define DDR_PHY_IOVCR0_ACREFEEN_MASK 0x0C000000U -/*Address/command lane Single-End VREF Enable*/ +/* +* Address/command lane Single-End VREF Enable +*/ #undef DDR_PHY_IOVCR0_ACREFSEN_DEFVAL #undef DDR_PHY_IOVCR0_ACREFSEN_SHIFT #undef DDR_PHY_IOVCR0_ACREFSEN_MASK -#define DDR_PHY_IOVCR0_ACREFSEN_DEFVAL 0x0F000000 -#define DDR_PHY_IOVCR0_ACREFSEN_SHIFT 25 -#define DDR_PHY_IOVCR0_ACREFSEN_MASK 0x02000000U +#define DDR_PHY_IOVCR0_ACREFSEN_DEFVAL 0x0F000000 +#define DDR_PHY_IOVCR0_ACREFSEN_SHIFT 25 +#define DDR_PHY_IOVCR0_ACREFSEN_MASK 0x02000000U -/*Address/command lane Internal VREF Enable*/ +/* +* Address/command lane Internal VREF Enable +*/ #undef DDR_PHY_IOVCR0_ACREFIEN_DEFVAL #undef DDR_PHY_IOVCR0_ACREFIEN_SHIFT #undef DDR_PHY_IOVCR0_ACREFIEN_MASK -#define DDR_PHY_IOVCR0_ACREFIEN_DEFVAL 0x0F000000 -#define DDR_PHY_IOVCR0_ACREFIEN_SHIFT 24 -#define DDR_PHY_IOVCR0_ACREFIEN_MASK 0x01000000U +#define DDR_PHY_IOVCR0_ACREFIEN_DEFVAL 0x0F000000 +#define DDR_PHY_IOVCR0_ACREFIEN_SHIFT 24 +#define DDR_PHY_IOVCR0_ACREFIEN_MASK 0x01000000U -/*External VREF generato REFSEL range select*/ +/* +* External VREF generato REFSEL range select +*/ #undef DDR_PHY_IOVCR0_ACREFESELRANGE_DEFVAL #undef DDR_PHY_IOVCR0_ACREFESELRANGE_SHIFT #undef DDR_PHY_IOVCR0_ACREFESELRANGE_MASK -#define DDR_PHY_IOVCR0_ACREFESELRANGE_DEFVAL 0x0F000000 -#define DDR_PHY_IOVCR0_ACREFESELRANGE_SHIFT 23 -#define DDR_PHY_IOVCR0_ACREFESELRANGE_MASK 0x00800000U +#define DDR_PHY_IOVCR0_ACREFESELRANGE_DEFVAL 0x0F000000 +#define DDR_PHY_IOVCR0_ACREFESELRANGE_SHIFT 23 +#define DDR_PHY_IOVCR0_ACREFESELRANGE_MASK 0x00800000U -/*Address/command lane External VREF Select*/ +/* +* Address/command lane External VREF Select +*/ #undef DDR_PHY_IOVCR0_ACREFESEL_DEFVAL #undef DDR_PHY_IOVCR0_ACREFESEL_SHIFT #undef DDR_PHY_IOVCR0_ACREFESEL_MASK -#define DDR_PHY_IOVCR0_ACREFESEL_DEFVAL 0x0F000000 -#define DDR_PHY_IOVCR0_ACREFESEL_SHIFT 16 -#define DDR_PHY_IOVCR0_ACREFESEL_MASK 0x007F0000U +#define DDR_PHY_IOVCR0_ACREFESEL_DEFVAL 0x0F000000 +#define DDR_PHY_IOVCR0_ACREFESEL_SHIFT 16 +#define DDR_PHY_IOVCR0_ACREFESEL_MASK 0x007F0000U -/*Single ended VREF generator REFSEL range select*/ +/* +* Single ended VREF generator REFSEL range select +*/ #undef DDR_PHY_IOVCR0_ACREFSSELRANGE_DEFVAL #undef DDR_PHY_IOVCR0_ACREFSSELRANGE_SHIFT #undef DDR_PHY_IOVCR0_ACREFSSELRANGE_MASK -#define DDR_PHY_IOVCR0_ACREFSSELRANGE_DEFVAL 0x0F000000 -#define DDR_PHY_IOVCR0_ACREFSSELRANGE_SHIFT 15 -#define DDR_PHY_IOVCR0_ACREFSSELRANGE_MASK 0x00008000U +#define DDR_PHY_IOVCR0_ACREFSSELRANGE_DEFVAL 0x0F000000 +#define DDR_PHY_IOVCR0_ACREFSSELRANGE_SHIFT 15 +#define DDR_PHY_IOVCR0_ACREFSSELRANGE_MASK 0x00008000U -/*Address/command lane Single-End VREF Select*/ +/* +* Address/command lane Single-End VREF Select +*/ #undef DDR_PHY_IOVCR0_ACREFSSEL_DEFVAL #undef DDR_PHY_IOVCR0_ACREFSSEL_SHIFT #undef DDR_PHY_IOVCR0_ACREFSSEL_MASK -#define DDR_PHY_IOVCR0_ACREFSSEL_DEFVAL 0x0F000000 -#define DDR_PHY_IOVCR0_ACREFSSEL_SHIFT 8 -#define DDR_PHY_IOVCR0_ACREFSSEL_MASK 0x00007F00U +#define DDR_PHY_IOVCR0_ACREFSSEL_DEFVAL 0x0F000000 +#define DDR_PHY_IOVCR0_ACREFSSEL_SHIFT 8 +#define DDR_PHY_IOVCR0_ACREFSSEL_MASK 0x00007F00U -/*Internal VREF generator REFSEL ragne select*/ +/* +* Internal VREF generator REFSEL ragne select +*/ #undef DDR_PHY_IOVCR0_ACVREFISELRANGE_DEFVAL #undef DDR_PHY_IOVCR0_ACVREFISELRANGE_SHIFT #undef DDR_PHY_IOVCR0_ACVREFISELRANGE_MASK -#define DDR_PHY_IOVCR0_ACVREFISELRANGE_DEFVAL 0x0F000000 -#define DDR_PHY_IOVCR0_ACVREFISELRANGE_SHIFT 7 -#define DDR_PHY_IOVCR0_ACVREFISELRANGE_MASK 0x00000080U +#define DDR_PHY_IOVCR0_ACVREFISELRANGE_DEFVAL 0x0F000000 +#define DDR_PHY_IOVCR0_ACVREFISELRANGE_SHIFT 7 +#define DDR_PHY_IOVCR0_ACVREFISELRANGE_MASK 0x00000080U -/*REFSEL Control for internal AC IOs*/ +/* +* REFSEL Control for internal AC IOs +*/ #undef DDR_PHY_IOVCR0_ACVREFISEL_DEFVAL #undef DDR_PHY_IOVCR0_ACVREFISEL_SHIFT #undef DDR_PHY_IOVCR0_ACVREFISEL_MASK -#define DDR_PHY_IOVCR0_ACVREFISEL_DEFVAL 0x0F000000 -#define DDR_PHY_IOVCR0_ACVREFISEL_SHIFT 0 -#define DDR_PHY_IOVCR0_ACVREFISEL_MASK 0x0000007FU +#define DDR_PHY_IOVCR0_ACVREFISEL_DEFVAL 0x0F000000 +#define DDR_PHY_IOVCR0_ACVREFISEL_SHIFT 0 +#define DDR_PHY_IOVCR0_ACVREFISEL_MASK 0x0000007FU -/*Number of ctl_clk required to meet (> 150ns) timing requirements during DRAM DQ VREF training*/ +/* +* Number of ctl_clk required to meet (> 150ns) timing requirements during + * DRAM DQ VREF training +*/ #undef DDR_PHY_VTCR0_TVREF_DEFVAL #undef DDR_PHY_VTCR0_TVREF_SHIFT #undef DDR_PHY_VTCR0_TVREF_MASK -#define DDR_PHY_VTCR0_TVREF_DEFVAL 0x70032019 -#define DDR_PHY_VTCR0_TVREF_SHIFT 29 -#define DDR_PHY_VTCR0_TVREF_MASK 0xE0000000U +#define DDR_PHY_VTCR0_TVREF_DEFVAL 0x70032019 +#define DDR_PHY_VTCR0_TVREF_SHIFT 29 +#define DDR_PHY_VTCR0_TVREF_MASK 0xE0000000U -/*DRM DQ VREF training Enable*/ +/* +* DRM DQ VREF training Enable +*/ #undef DDR_PHY_VTCR0_DVEN_DEFVAL #undef DDR_PHY_VTCR0_DVEN_SHIFT #undef DDR_PHY_VTCR0_DVEN_MASK -#define DDR_PHY_VTCR0_DVEN_DEFVAL 0x70032019 -#define DDR_PHY_VTCR0_DVEN_SHIFT 28 -#define DDR_PHY_VTCR0_DVEN_MASK 0x10000000U +#define DDR_PHY_VTCR0_DVEN_DEFVAL 0x70032019 +#define DDR_PHY_VTCR0_DVEN_SHIFT 28 +#define DDR_PHY_VTCR0_DVEN_MASK 0x10000000U -/*Per Device Addressability Enable*/ +/* +* Per Device Addressability Enable +*/ #undef DDR_PHY_VTCR0_PDAEN_DEFVAL #undef DDR_PHY_VTCR0_PDAEN_SHIFT #undef DDR_PHY_VTCR0_PDAEN_MASK -#define DDR_PHY_VTCR0_PDAEN_DEFVAL 0x70032019 -#define DDR_PHY_VTCR0_PDAEN_SHIFT 27 -#define DDR_PHY_VTCR0_PDAEN_MASK 0x08000000U +#define DDR_PHY_VTCR0_PDAEN_DEFVAL 0x70032019 +#define DDR_PHY_VTCR0_PDAEN_SHIFT 27 +#define DDR_PHY_VTCR0_PDAEN_MASK 0x08000000U -/*Reserved. Returns zeroes on reads.*/ +/* +* Reserved. Returns zeroes on reads. +*/ #undef DDR_PHY_VTCR0_RESERVED_26_DEFVAL #undef DDR_PHY_VTCR0_RESERVED_26_SHIFT #undef DDR_PHY_VTCR0_RESERVED_26_MASK -#define DDR_PHY_VTCR0_RESERVED_26_DEFVAL 0x70032019 -#define DDR_PHY_VTCR0_RESERVED_26_SHIFT 26 -#define DDR_PHY_VTCR0_RESERVED_26_MASK 0x04000000U +#define DDR_PHY_VTCR0_RESERVED_26_DEFVAL 0x70032019 +#define DDR_PHY_VTCR0_RESERVED_26_SHIFT 26 +#define DDR_PHY_VTCR0_RESERVED_26_MASK 0x04000000U -/*VREF Word Count*/ +/* +* VREF Word Count +*/ #undef DDR_PHY_VTCR0_VWCR_DEFVAL #undef DDR_PHY_VTCR0_VWCR_SHIFT #undef DDR_PHY_VTCR0_VWCR_MASK -#define DDR_PHY_VTCR0_VWCR_DEFVAL 0x70032019 -#define DDR_PHY_VTCR0_VWCR_SHIFT 22 -#define DDR_PHY_VTCR0_VWCR_MASK 0x03C00000U +#define DDR_PHY_VTCR0_VWCR_DEFVAL 0x70032019 +#define DDR_PHY_VTCR0_VWCR_SHIFT 22 +#define DDR_PHY_VTCR0_VWCR_MASK 0x03C00000U -/*DRAM DQ VREF step size used during DRAM VREF training*/ +/* +* DRAM DQ VREF step size used during DRAM VREF training +*/ #undef DDR_PHY_VTCR0_DVSS_DEFVAL #undef DDR_PHY_VTCR0_DVSS_SHIFT #undef DDR_PHY_VTCR0_DVSS_MASK -#define DDR_PHY_VTCR0_DVSS_DEFVAL 0x70032019 -#define DDR_PHY_VTCR0_DVSS_SHIFT 18 -#define DDR_PHY_VTCR0_DVSS_MASK 0x003C0000U +#define DDR_PHY_VTCR0_DVSS_DEFVAL 0x70032019 +#define DDR_PHY_VTCR0_DVSS_SHIFT 18 +#define DDR_PHY_VTCR0_DVSS_MASK 0x003C0000U -/*Maximum VREF limit value used during DRAM VREF training*/ +/* +* Maximum VREF limit value used during DRAM VREF training +*/ #undef DDR_PHY_VTCR0_DVMAX_DEFVAL #undef DDR_PHY_VTCR0_DVMAX_SHIFT #undef DDR_PHY_VTCR0_DVMAX_MASK -#define DDR_PHY_VTCR0_DVMAX_DEFVAL 0x70032019 -#define DDR_PHY_VTCR0_DVMAX_SHIFT 12 -#define DDR_PHY_VTCR0_DVMAX_MASK 0x0003F000U +#define DDR_PHY_VTCR0_DVMAX_DEFVAL 0x70032019 +#define DDR_PHY_VTCR0_DVMAX_SHIFT 12 +#define DDR_PHY_VTCR0_DVMAX_MASK 0x0003F000U -/*Minimum VREF limit value used during DRAM VREF training*/ +/* +* Minimum VREF limit value used during DRAM VREF training +*/ #undef DDR_PHY_VTCR0_DVMIN_DEFVAL #undef DDR_PHY_VTCR0_DVMIN_SHIFT #undef DDR_PHY_VTCR0_DVMIN_MASK -#define DDR_PHY_VTCR0_DVMIN_DEFVAL 0x70032019 -#define DDR_PHY_VTCR0_DVMIN_SHIFT 6 -#define DDR_PHY_VTCR0_DVMIN_MASK 0x00000FC0U +#define DDR_PHY_VTCR0_DVMIN_DEFVAL 0x70032019 +#define DDR_PHY_VTCR0_DVMIN_SHIFT 6 +#define DDR_PHY_VTCR0_DVMIN_MASK 0x00000FC0U -/*Initial DRAM DQ VREF value used during DRAM VREF training*/ +/* +* Initial DRAM DQ VREF value used during DRAM VREF training +*/ #undef DDR_PHY_VTCR0_DVINIT_DEFVAL #undef DDR_PHY_VTCR0_DVINIT_SHIFT #undef DDR_PHY_VTCR0_DVINIT_MASK -#define DDR_PHY_VTCR0_DVINIT_DEFVAL 0x70032019 -#define DDR_PHY_VTCR0_DVINIT_SHIFT 0 -#define DDR_PHY_VTCR0_DVINIT_MASK 0x0000003FU +#define DDR_PHY_VTCR0_DVINIT_DEFVAL 0x70032019 +#define DDR_PHY_VTCR0_DVINIT_SHIFT 0 +#define DDR_PHY_VTCR0_DVINIT_MASK 0x0000003FU -/*Host VREF step size used during VREF training. The register value of N indicates step size of (N+1)*/ +/* +* Host VREF step size used during VREF training. The register value of N i + * ndicates step size of (N+1) +*/ #undef DDR_PHY_VTCR1_HVSS_DEFVAL #undef DDR_PHY_VTCR1_HVSS_SHIFT #undef DDR_PHY_VTCR1_HVSS_MASK -#define DDR_PHY_VTCR1_HVSS_DEFVAL 0x07F00072 -#define DDR_PHY_VTCR1_HVSS_SHIFT 28 -#define DDR_PHY_VTCR1_HVSS_MASK 0xF0000000U +#define DDR_PHY_VTCR1_HVSS_DEFVAL 0x07F00072 +#define DDR_PHY_VTCR1_HVSS_SHIFT 28 +#define DDR_PHY_VTCR1_HVSS_MASK 0xF0000000U -/*Reserved. Returns zeroes on reads.*/ +/* +* Reserved. Returns zeroes on reads. +*/ #undef DDR_PHY_VTCR1_RESERVED_27_DEFVAL #undef DDR_PHY_VTCR1_RESERVED_27_SHIFT #undef DDR_PHY_VTCR1_RESERVED_27_MASK -#define DDR_PHY_VTCR1_RESERVED_27_DEFVAL 0x07F00072 -#define DDR_PHY_VTCR1_RESERVED_27_SHIFT 27 -#define DDR_PHY_VTCR1_RESERVED_27_MASK 0x08000000U +#define DDR_PHY_VTCR1_RESERVED_27_DEFVAL 0x07F00072 +#define DDR_PHY_VTCR1_RESERVED_27_SHIFT 27 +#define DDR_PHY_VTCR1_RESERVED_27_MASK 0x08000000U -/*Maximum VREF limit value used during DRAM VREF training.*/ +/* +* Maximum VREF limit value used during DRAM VREF training. +*/ #undef DDR_PHY_VTCR1_HVMAX_DEFVAL #undef DDR_PHY_VTCR1_HVMAX_SHIFT #undef DDR_PHY_VTCR1_HVMAX_MASK -#define DDR_PHY_VTCR1_HVMAX_DEFVAL 0x07F00072 -#define DDR_PHY_VTCR1_HVMAX_SHIFT 20 -#define DDR_PHY_VTCR1_HVMAX_MASK 0x07F00000U +#define DDR_PHY_VTCR1_HVMAX_DEFVAL 0x07F00072 +#define DDR_PHY_VTCR1_HVMAX_SHIFT 20 +#define DDR_PHY_VTCR1_HVMAX_MASK 0x07F00000U -/*Reserved. Returns zeroes on reads.*/ +/* +* Reserved. Returns zeroes on reads. +*/ #undef DDR_PHY_VTCR1_RESERVED_19_DEFVAL #undef DDR_PHY_VTCR1_RESERVED_19_SHIFT #undef DDR_PHY_VTCR1_RESERVED_19_MASK -#define DDR_PHY_VTCR1_RESERVED_19_DEFVAL 0x07F00072 -#define DDR_PHY_VTCR1_RESERVED_19_SHIFT 19 -#define DDR_PHY_VTCR1_RESERVED_19_MASK 0x00080000U +#define DDR_PHY_VTCR1_RESERVED_19_DEFVAL 0x07F00072 +#define DDR_PHY_VTCR1_RESERVED_19_SHIFT 19 +#define DDR_PHY_VTCR1_RESERVED_19_MASK 0x00080000U -/*Minimum VREF limit value used during DRAM VREF training.*/ +/* +* Minimum VREF limit value used during DRAM VREF training. +*/ #undef DDR_PHY_VTCR1_HVMIN_DEFVAL #undef DDR_PHY_VTCR1_HVMIN_SHIFT #undef DDR_PHY_VTCR1_HVMIN_MASK -#define DDR_PHY_VTCR1_HVMIN_DEFVAL 0x07F00072 -#define DDR_PHY_VTCR1_HVMIN_SHIFT 12 -#define DDR_PHY_VTCR1_HVMIN_MASK 0x0007F000U +#define DDR_PHY_VTCR1_HVMIN_DEFVAL 0x07F00072 +#define DDR_PHY_VTCR1_HVMIN_SHIFT 12 +#define DDR_PHY_VTCR1_HVMIN_MASK 0x0007F000U -/*Reserved. Returns zeroes on reads.*/ +/* +* Reserved. Returns zeroes on reads. +*/ #undef DDR_PHY_VTCR1_RESERVED_11_DEFVAL #undef DDR_PHY_VTCR1_RESERVED_11_SHIFT #undef DDR_PHY_VTCR1_RESERVED_11_MASK -#define DDR_PHY_VTCR1_RESERVED_11_DEFVAL 0x07F00072 -#define DDR_PHY_VTCR1_RESERVED_11_SHIFT 11 -#define DDR_PHY_VTCR1_RESERVED_11_MASK 0x00000800U +#define DDR_PHY_VTCR1_RESERVED_11_DEFVAL 0x07F00072 +#define DDR_PHY_VTCR1_RESERVED_11_SHIFT 11 +#define DDR_PHY_VTCR1_RESERVED_11_MASK 0x00000800U -/*Static Host Vref Rank Value*/ +/* +* Static Host Vref Rank Value +*/ #undef DDR_PHY_VTCR1_SHRNK_DEFVAL #undef DDR_PHY_VTCR1_SHRNK_SHIFT #undef DDR_PHY_VTCR1_SHRNK_MASK -#define DDR_PHY_VTCR1_SHRNK_DEFVAL 0x07F00072 -#define DDR_PHY_VTCR1_SHRNK_SHIFT 9 -#define DDR_PHY_VTCR1_SHRNK_MASK 0x00000600U +#define DDR_PHY_VTCR1_SHRNK_DEFVAL 0x07F00072 +#define DDR_PHY_VTCR1_SHRNK_SHIFT 9 +#define DDR_PHY_VTCR1_SHRNK_MASK 0x00000600U -/*Static Host Vref Rank Enable*/ +/* +* Static Host Vref Rank Enable +*/ #undef DDR_PHY_VTCR1_SHREN_DEFVAL #undef DDR_PHY_VTCR1_SHREN_SHIFT #undef DDR_PHY_VTCR1_SHREN_MASK -#define DDR_PHY_VTCR1_SHREN_DEFVAL 0x07F00072 -#define DDR_PHY_VTCR1_SHREN_SHIFT 8 -#define DDR_PHY_VTCR1_SHREN_MASK 0x00000100U +#define DDR_PHY_VTCR1_SHREN_DEFVAL 0x07F00072 +#define DDR_PHY_VTCR1_SHREN_SHIFT 8 +#define DDR_PHY_VTCR1_SHREN_MASK 0x00000100U -/*Number of ctl_clk required to meet (> 200ns) VREF Settling timing requirements during Host IO VREF training*/ +/* +* Number of ctl_clk required to meet (> 200ns) VREF Settling timing requir + * ements during Host IO VREF training +*/ #undef DDR_PHY_VTCR1_TVREFIO_DEFVAL #undef DDR_PHY_VTCR1_TVREFIO_SHIFT #undef DDR_PHY_VTCR1_TVREFIO_MASK -#define DDR_PHY_VTCR1_TVREFIO_DEFVAL 0x07F00072 -#define DDR_PHY_VTCR1_TVREFIO_SHIFT 5 -#define DDR_PHY_VTCR1_TVREFIO_MASK 0x000000E0U +#define DDR_PHY_VTCR1_TVREFIO_DEFVAL 0x07F00072 +#define DDR_PHY_VTCR1_TVREFIO_SHIFT 5 +#define DDR_PHY_VTCR1_TVREFIO_MASK 0x000000E0U -/*Eye LCDL Offset value for VREF training*/ +/* +* Eye LCDL Offset value for VREF training +*/ #undef DDR_PHY_VTCR1_EOFF_DEFVAL #undef DDR_PHY_VTCR1_EOFF_SHIFT #undef DDR_PHY_VTCR1_EOFF_MASK -#define DDR_PHY_VTCR1_EOFF_DEFVAL 0x07F00072 -#define DDR_PHY_VTCR1_EOFF_SHIFT 3 -#define DDR_PHY_VTCR1_EOFF_MASK 0x00000018U +#define DDR_PHY_VTCR1_EOFF_DEFVAL 0x07F00072 +#define DDR_PHY_VTCR1_EOFF_SHIFT 3 +#define DDR_PHY_VTCR1_EOFF_MASK 0x00000018U -/*Number of LCDL Eye points for which VREF training is repeated*/ +/* +* Number of LCDL Eye points for which VREF training is repeated +*/ #undef DDR_PHY_VTCR1_ENUM_DEFVAL #undef DDR_PHY_VTCR1_ENUM_SHIFT #undef DDR_PHY_VTCR1_ENUM_MASK -#define DDR_PHY_VTCR1_ENUM_DEFVAL 0x07F00072 -#define DDR_PHY_VTCR1_ENUM_SHIFT 2 -#define DDR_PHY_VTCR1_ENUM_MASK 0x00000004U +#define DDR_PHY_VTCR1_ENUM_DEFVAL 0x07F00072 +#define DDR_PHY_VTCR1_ENUM_SHIFT 2 +#define DDR_PHY_VTCR1_ENUM_MASK 0x00000004U -/*HOST (IO) internal VREF training Enable*/ +/* +* HOST (IO) internal VREF training Enable +*/ #undef DDR_PHY_VTCR1_HVEN_DEFVAL #undef DDR_PHY_VTCR1_HVEN_SHIFT #undef DDR_PHY_VTCR1_HVEN_MASK -#define DDR_PHY_VTCR1_HVEN_DEFVAL 0x07F00072 -#define DDR_PHY_VTCR1_HVEN_SHIFT 1 -#define DDR_PHY_VTCR1_HVEN_MASK 0x00000002U +#define DDR_PHY_VTCR1_HVEN_DEFVAL 0x07F00072 +#define DDR_PHY_VTCR1_HVEN_SHIFT 1 +#define DDR_PHY_VTCR1_HVEN_MASK 0x00000002U -/*Host IO Type Control*/ +/* +* Host IO Type Control +*/ #undef DDR_PHY_VTCR1_HVIO_DEFVAL #undef DDR_PHY_VTCR1_HVIO_SHIFT #undef DDR_PHY_VTCR1_HVIO_MASK -#define DDR_PHY_VTCR1_HVIO_DEFVAL 0x07F00072 -#define DDR_PHY_VTCR1_HVIO_SHIFT 0 -#define DDR_PHY_VTCR1_HVIO_MASK 0x00000001U +#define DDR_PHY_VTCR1_HVIO_DEFVAL 0x07F00072 +#define DDR_PHY_VTCR1_HVIO_SHIFT 0 +#define DDR_PHY_VTCR1_HVIO_MASK 0x00000001U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR1_RESERVED_31_30_DEFVAL #undef DDR_PHY_ACBDLR1_RESERVED_31_30_SHIFT #undef DDR_PHY_ACBDLR1_RESERVED_31_30_MASK -#define DDR_PHY_ACBDLR1_RESERVED_31_30_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR1_RESERVED_31_30_SHIFT 30 -#define DDR_PHY_ACBDLR1_RESERVED_31_30_MASK 0xC0000000U +#define DDR_PHY_ACBDLR1_RESERVED_31_30_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR1_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_ACBDLR1_RESERVED_31_30_MASK 0xC0000000U -/*Delay select for the BDL on Parity.*/ +/* +* Delay select for the BDL on Parity. +*/ #undef DDR_PHY_ACBDLR1_PARBD_DEFVAL #undef DDR_PHY_ACBDLR1_PARBD_SHIFT #undef DDR_PHY_ACBDLR1_PARBD_MASK -#define DDR_PHY_ACBDLR1_PARBD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR1_PARBD_SHIFT 24 -#define DDR_PHY_ACBDLR1_PARBD_MASK 0x3F000000U +#define DDR_PHY_ACBDLR1_PARBD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR1_PARBD_SHIFT 24 +#define DDR_PHY_ACBDLR1_PARBD_MASK 0x3F000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR1_RESERVED_23_22_DEFVAL #undef DDR_PHY_ACBDLR1_RESERVED_23_22_SHIFT #undef DDR_PHY_ACBDLR1_RESERVED_23_22_MASK -#define DDR_PHY_ACBDLR1_RESERVED_23_22_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR1_RESERVED_23_22_SHIFT 22 -#define DDR_PHY_ACBDLR1_RESERVED_23_22_MASK 0x00C00000U +#define DDR_PHY_ACBDLR1_RESERVED_23_22_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR1_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_ACBDLR1_RESERVED_23_22_MASK 0x00C00000U -/*Delay select for the BDL on Address A[16]. In DDR3 mode this pin is connected to WE.*/ +/* +* Delay select for the BDL on Address A[16]. In DDR3 mode this pin is conn + * ected to WE. +*/ #undef DDR_PHY_ACBDLR1_A16BD_DEFVAL #undef DDR_PHY_ACBDLR1_A16BD_SHIFT #undef DDR_PHY_ACBDLR1_A16BD_MASK -#define DDR_PHY_ACBDLR1_A16BD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR1_A16BD_SHIFT 16 -#define DDR_PHY_ACBDLR1_A16BD_MASK 0x003F0000U +#define DDR_PHY_ACBDLR1_A16BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR1_A16BD_SHIFT 16 +#define DDR_PHY_ACBDLR1_A16BD_MASK 0x003F0000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR1_RESERVED_15_14_DEFVAL #undef DDR_PHY_ACBDLR1_RESERVED_15_14_SHIFT #undef DDR_PHY_ACBDLR1_RESERVED_15_14_MASK -#define DDR_PHY_ACBDLR1_RESERVED_15_14_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR1_RESERVED_15_14_SHIFT 14 -#define DDR_PHY_ACBDLR1_RESERVED_15_14_MASK 0x0000C000U +#define DDR_PHY_ACBDLR1_RESERVED_15_14_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR1_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_ACBDLR1_RESERVED_15_14_MASK 0x0000C000U -/*Delay select for the BDL on Address A[17]. When not in DDR4 modemode this pin is connected to CAS.*/ +/* +* Delay select for the BDL on Address A[17]. When not in DDR4 modemode thi + * s pin is connected to CAS. +*/ #undef DDR_PHY_ACBDLR1_A17BD_DEFVAL #undef DDR_PHY_ACBDLR1_A17BD_SHIFT #undef DDR_PHY_ACBDLR1_A17BD_MASK -#define DDR_PHY_ACBDLR1_A17BD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR1_A17BD_SHIFT 8 -#define DDR_PHY_ACBDLR1_A17BD_MASK 0x00003F00U +#define DDR_PHY_ACBDLR1_A17BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR1_A17BD_SHIFT 8 +#define DDR_PHY_ACBDLR1_A17BD_MASK 0x00003F00U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR1_RESERVED_7_6_DEFVAL #undef DDR_PHY_ACBDLR1_RESERVED_7_6_SHIFT #undef DDR_PHY_ACBDLR1_RESERVED_7_6_MASK -#define DDR_PHY_ACBDLR1_RESERVED_7_6_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR1_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_ACBDLR1_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_ACBDLR1_RESERVED_7_6_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR1_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_ACBDLR1_RESERVED_7_6_MASK 0x000000C0U -/*Delay select for the BDL on ACTN.*/ +/* +* Delay select for the BDL on ACTN. +*/ #undef DDR_PHY_ACBDLR1_ACTBD_DEFVAL #undef DDR_PHY_ACBDLR1_ACTBD_SHIFT #undef DDR_PHY_ACBDLR1_ACTBD_MASK -#define DDR_PHY_ACBDLR1_ACTBD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR1_ACTBD_SHIFT 0 -#define DDR_PHY_ACBDLR1_ACTBD_MASK 0x0000003FU +#define DDR_PHY_ACBDLR1_ACTBD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR1_ACTBD_SHIFT 0 +#define DDR_PHY_ACBDLR1_ACTBD_MASK 0x0000003FU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR2_RESERVED_31_30_DEFVAL #undef DDR_PHY_ACBDLR2_RESERVED_31_30_SHIFT #undef DDR_PHY_ACBDLR2_RESERVED_31_30_MASK -#define DDR_PHY_ACBDLR2_RESERVED_31_30_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR2_RESERVED_31_30_SHIFT 30 -#define DDR_PHY_ACBDLR2_RESERVED_31_30_MASK 0xC0000000U +#define DDR_PHY_ACBDLR2_RESERVED_31_30_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR2_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_ACBDLR2_RESERVED_31_30_MASK 0xC0000000U -/*Delay select for the BDL on BG[1].*/ +/* +* Delay select for the BDL on BG[1]. +*/ #undef DDR_PHY_ACBDLR2_BG1BD_DEFVAL #undef DDR_PHY_ACBDLR2_BG1BD_SHIFT #undef DDR_PHY_ACBDLR2_BG1BD_MASK -#define DDR_PHY_ACBDLR2_BG1BD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR2_BG1BD_SHIFT 24 -#define DDR_PHY_ACBDLR2_BG1BD_MASK 0x3F000000U +#define DDR_PHY_ACBDLR2_BG1BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR2_BG1BD_SHIFT 24 +#define DDR_PHY_ACBDLR2_BG1BD_MASK 0x3F000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR2_RESERVED_23_22_DEFVAL #undef DDR_PHY_ACBDLR2_RESERVED_23_22_SHIFT #undef DDR_PHY_ACBDLR2_RESERVED_23_22_MASK -#define DDR_PHY_ACBDLR2_RESERVED_23_22_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR2_RESERVED_23_22_SHIFT 22 -#define DDR_PHY_ACBDLR2_RESERVED_23_22_MASK 0x00C00000U +#define DDR_PHY_ACBDLR2_RESERVED_23_22_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR2_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_ACBDLR2_RESERVED_23_22_MASK 0x00C00000U -/*Delay select for the BDL on BG[0].*/ +/* +* Delay select for the BDL on BG[0]. +*/ #undef DDR_PHY_ACBDLR2_BG0BD_DEFVAL #undef DDR_PHY_ACBDLR2_BG0BD_SHIFT #undef DDR_PHY_ACBDLR2_BG0BD_MASK -#define DDR_PHY_ACBDLR2_BG0BD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR2_BG0BD_SHIFT 16 -#define DDR_PHY_ACBDLR2_BG0BD_MASK 0x003F0000U +#define DDR_PHY_ACBDLR2_BG0BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR2_BG0BD_SHIFT 16 +#define DDR_PHY_ACBDLR2_BG0BD_MASK 0x003F0000U -/*Reser.ved Return zeroes on reads.*/ +/* +* Reser.ved Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR2_RESERVED_15_14_DEFVAL #undef DDR_PHY_ACBDLR2_RESERVED_15_14_SHIFT #undef DDR_PHY_ACBDLR2_RESERVED_15_14_MASK -#define DDR_PHY_ACBDLR2_RESERVED_15_14_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR2_RESERVED_15_14_SHIFT 14 -#define DDR_PHY_ACBDLR2_RESERVED_15_14_MASK 0x0000C000U +#define DDR_PHY_ACBDLR2_RESERVED_15_14_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR2_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_ACBDLR2_RESERVED_15_14_MASK 0x0000C000U -/*Delay select for the BDL on BA[1].*/ +/* +* Delay select for the BDL on BA[1]. +*/ #undef DDR_PHY_ACBDLR2_BA1BD_DEFVAL #undef DDR_PHY_ACBDLR2_BA1BD_SHIFT #undef DDR_PHY_ACBDLR2_BA1BD_MASK -#define DDR_PHY_ACBDLR2_BA1BD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR2_BA1BD_SHIFT 8 -#define DDR_PHY_ACBDLR2_BA1BD_MASK 0x00003F00U +#define DDR_PHY_ACBDLR2_BA1BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR2_BA1BD_SHIFT 8 +#define DDR_PHY_ACBDLR2_BA1BD_MASK 0x00003F00U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR2_RESERVED_7_6_DEFVAL #undef DDR_PHY_ACBDLR2_RESERVED_7_6_SHIFT #undef DDR_PHY_ACBDLR2_RESERVED_7_6_MASK -#define DDR_PHY_ACBDLR2_RESERVED_7_6_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR2_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_ACBDLR2_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_ACBDLR2_RESERVED_7_6_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR2_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_ACBDLR2_RESERVED_7_6_MASK 0x000000C0U -/*Delay select for the BDL on BA[0].*/ +/* +* Delay select for the BDL on BA[0]. +*/ #undef DDR_PHY_ACBDLR2_BA0BD_DEFVAL #undef DDR_PHY_ACBDLR2_BA0BD_SHIFT #undef DDR_PHY_ACBDLR2_BA0BD_MASK -#define DDR_PHY_ACBDLR2_BA0BD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR2_BA0BD_SHIFT 0 -#define DDR_PHY_ACBDLR2_BA0BD_MASK 0x0000003FU +#define DDR_PHY_ACBDLR2_BA0BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR2_BA0BD_SHIFT 0 +#define DDR_PHY_ACBDLR2_BA0BD_MASK 0x0000003FU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR6_RESERVED_31_30_DEFVAL #undef DDR_PHY_ACBDLR6_RESERVED_31_30_SHIFT #undef DDR_PHY_ACBDLR6_RESERVED_31_30_MASK -#define DDR_PHY_ACBDLR6_RESERVED_31_30_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR6_RESERVED_31_30_SHIFT 30 -#define DDR_PHY_ACBDLR6_RESERVED_31_30_MASK 0xC0000000U +#define DDR_PHY_ACBDLR6_RESERVED_31_30_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR6_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_ACBDLR6_RESERVED_31_30_MASK 0xC0000000U -/*Delay select for the BDL on Address A[3].*/ +/* +* Delay select for the BDL on Address A[3]. +*/ #undef DDR_PHY_ACBDLR6_A03BD_DEFVAL #undef DDR_PHY_ACBDLR6_A03BD_SHIFT #undef DDR_PHY_ACBDLR6_A03BD_MASK -#define DDR_PHY_ACBDLR6_A03BD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR6_A03BD_SHIFT 24 -#define DDR_PHY_ACBDLR6_A03BD_MASK 0x3F000000U +#define DDR_PHY_ACBDLR6_A03BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR6_A03BD_SHIFT 24 +#define DDR_PHY_ACBDLR6_A03BD_MASK 0x3F000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR6_RESERVED_23_22_DEFVAL #undef DDR_PHY_ACBDLR6_RESERVED_23_22_SHIFT #undef DDR_PHY_ACBDLR6_RESERVED_23_22_MASK -#define DDR_PHY_ACBDLR6_RESERVED_23_22_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR6_RESERVED_23_22_SHIFT 22 -#define DDR_PHY_ACBDLR6_RESERVED_23_22_MASK 0x00C00000U +#define DDR_PHY_ACBDLR6_RESERVED_23_22_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR6_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_ACBDLR6_RESERVED_23_22_MASK 0x00C00000U -/*Delay select for the BDL on Address A[2].*/ +/* +* Delay select for the BDL on Address A[2]. +*/ #undef DDR_PHY_ACBDLR6_A02BD_DEFVAL #undef DDR_PHY_ACBDLR6_A02BD_SHIFT #undef DDR_PHY_ACBDLR6_A02BD_MASK -#define DDR_PHY_ACBDLR6_A02BD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR6_A02BD_SHIFT 16 -#define DDR_PHY_ACBDLR6_A02BD_MASK 0x003F0000U +#define DDR_PHY_ACBDLR6_A02BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR6_A02BD_SHIFT 16 +#define DDR_PHY_ACBDLR6_A02BD_MASK 0x003F0000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR6_RESERVED_15_14_DEFVAL #undef DDR_PHY_ACBDLR6_RESERVED_15_14_SHIFT #undef DDR_PHY_ACBDLR6_RESERVED_15_14_MASK -#define DDR_PHY_ACBDLR6_RESERVED_15_14_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR6_RESERVED_15_14_SHIFT 14 -#define DDR_PHY_ACBDLR6_RESERVED_15_14_MASK 0x0000C000U +#define DDR_PHY_ACBDLR6_RESERVED_15_14_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR6_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_ACBDLR6_RESERVED_15_14_MASK 0x0000C000U -/*Delay select for the BDL on Address A[1].*/ +/* +* Delay select for the BDL on Address A[1]. +*/ #undef DDR_PHY_ACBDLR6_A01BD_DEFVAL #undef DDR_PHY_ACBDLR6_A01BD_SHIFT #undef DDR_PHY_ACBDLR6_A01BD_MASK -#define DDR_PHY_ACBDLR6_A01BD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR6_A01BD_SHIFT 8 -#define DDR_PHY_ACBDLR6_A01BD_MASK 0x00003F00U +#define DDR_PHY_ACBDLR6_A01BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR6_A01BD_SHIFT 8 +#define DDR_PHY_ACBDLR6_A01BD_MASK 0x00003F00U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR6_RESERVED_7_6_DEFVAL #undef DDR_PHY_ACBDLR6_RESERVED_7_6_SHIFT #undef DDR_PHY_ACBDLR6_RESERVED_7_6_MASK -#define DDR_PHY_ACBDLR6_RESERVED_7_6_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR6_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_ACBDLR6_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_ACBDLR6_RESERVED_7_6_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR6_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_ACBDLR6_RESERVED_7_6_MASK 0x000000C0U -/*Delay select for the BDL on Address A[0].*/ +/* +* Delay select for the BDL on Address A[0]. +*/ #undef DDR_PHY_ACBDLR6_A00BD_DEFVAL #undef DDR_PHY_ACBDLR6_A00BD_SHIFT #undef DDR_PHY_ACBDLR6_A00BD_MASK -#define DDR_PHY_ACBDLR6_A00BD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR6_A00BD_SHIFT 0 -#define DDR_PHY_ACBDLR6_A00BD_MASK 0x0000003FU +#define DDR_PHY_ACBDLR6_A00BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR6_A00BD_SHIFT 0 +#define DDR_PHY_ACBDLR6_A00BD_MASK 0x0000003FU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR7_RESERVED_31_30_DEFVAL #undef DDR_PHY_ACBDLR7_RESERVED_31_30_SHIFT #undef DDR_PHY_ACBDLR7_RESERVED_31_30_MASK -#define DDR_PHY_ACBDLR7_RESERVED_31_30_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR7_RESERVED_31_30_SHIFT 30 -#define DDR_PHY_ACBDLR7_RESERVED_31_30_MASK 0xC0000000U +#define DDR_PHY_ACBDLR7_RESERVED_31_30_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR7_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_ACBDLR7_RESERVED_31_30_MASK 0xC0000000U -/*Delay select for the BDL on Address A[7].*/ +/* +* Delay select for the BDL on Address A[7]. +*/ #undef DDR_PHY_ACBDLR7_A07BD_DEFVAL #undef DDR_PHY_ACBDLR7_A07BD_SHIFT #undef DDR_PHY_ACBDLR7_A07BD_MASK -#define DDR_PHY_ACBDLR7_A07BD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR7_A07BD_SHIFT 24 -#define DDR_PHY_ACBDLR7_A07BD_MASK 0x3F000000U +#define DDR_PHY_ACBDLR7_A07BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR7_A07BD_SHIFT 24 +#define DDR_PHY_ACBDLR7_A07BD_MASK 0x3F000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR7_RESERVED_23_22_DEFVAL #undef DDR_PHY_ACBDLR7_RESERVED_23_22_SHIFT #undef DDR_PHY_ACBDLR7_RESERVED_23_22_MASK -#define DDR_PHY_ACBDLR7_RESERVED_23_22_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR7_RESERVED_23_22_SHIFT 22 -#define DDR_PHY_ACBDLR7_RESERVED_23_22_MASK 0x00C00000U +#define DDR_PHY_ACBDLR7_RESERVED_23_22_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR7_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_ACBDLR7_RESERVED_23_22_MASK 0x00C00000U -/*Delay select for the BDL on Address A[6].*/ +/* +* Delay select for the BDL on Address A[6]. +*/ #undef DDR_PHY_ACBDLR7_A06BD_DEFVAL #undef DDR_PHY_ACBDLR7_A06BD_SHIFT #undef DDR_PHY_ACBDLR7_A06BD_MASK -#define DDR_PHY_ACBDLR7_A06BD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR7_A06BD_SHIFT 16 -#define DDR_PHY_ACBDLR7_A06BD_MASK 0x003F0000U +#define DDR_PHY_ACBDLR7_A06BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR7_A06BD_SHIFT 16 +#define DDR_PHY_ACBDLR7_A06BD_MASK 0x003F0000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR7_RESERVED_15_14_DEFVAL #undef DDR_PHY_ACBDLR7_RESERVED_15_14_SHIFT #undef DDR_PHY_ACBDLR7_RESERVED_15_14_MASK -#define DDR_PHY_ACBDLR7_RESERVED_15_14_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR7_RESERVED_15_14_SHIFT 14 -#define DDR_PHY_ACBDLR7_RESERVED_15_14_MASK 0x0000C000U +#define DDR_PHY_ACBDLR7_RESERVED_15_14_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR7_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_ACBDLR7_RESERVED_15_14_MASK 0x0000C000U -/*Delay select for the BDL on Address A[5].*/ +/* +* Delay select for the BDL on Address A[5]. +*/ #undef DDR_PHY_ACBDLR7_A05BD_DEFVAL #undef DDR_PHY_ACBDLR7_A05BD_SHIFT #undef DDR_PHY_ACBDLR7_A05BD_MASK -#define DDR_PHY_ACBDLR7_A05BD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR7_A05BD_SHIFT 8 -#define DDR_PHY_ACBDLR7_A05BD_MASK 0x00003F00U +#define DDR_PHY_ACBDLR7_A05BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR7_A05BD_SHIFT 8 +#define DDR_PHY_ACBDLR7_A05BD_MASK 0x00003F00U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR7_RESERVED_7_6_DEFVAL #undef DDR_PHY_ACBDLR7_RESERVED_7_6_SHIFT #undef DDR_PHY_ACBDLR7_RESERVED_7_6_MASK -#define DDR_PHY_ACBDLR7_RESERVED_7_6_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR7_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_ACBDLR7_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_ACBDLR7_RESERVED_7_6_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR7_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_ACBDLR7_RESERVED_7_6_MASK 0x000000C0U -/*Delay select for the BDL on Address A[4].*/ +/* +* Delay select for the BDL on Address A[4]. +*/ #undef DDR_PHY_ACBDLR7_A04BD_DEFVAL #undef DDR_PHY_ACBDLR7_A04BD_SHIFT #undef DDR_PHY_ACBDLR7_A04BD_MASK -#define DDR_PHY_ACBDLR7_A04BD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR7_A04BD_SHIFT 0 -#define DDR_PHY_ACBDLR7_A04BD_MASK 0x0000003FU +#define DDR_PHY_ACBDLR7_A04BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR7_A04BD_SHIFT 0 +#define DDR_PHY_ACBDLR7_A04BD_MASK 0x0000003FU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR8_RESERVED_31_30_DEFVAL #undef DDR_PHY_ACBDLR8_RESERVED_31_30_SHIFT #undef DDR_PHY_ACBDLR8_RESERVED_31_30_MASK -#define DDR_PHY_ACBDLR8_RESERVED_31_30_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR8_RESERVED_31_30_SHIFT 30 -#define DDR_PHY_ACBDLR8_RESERVED_31_30_MASK 0xC0000000U +#define DDR_PHY_ACBDLR8_RESERVED_31_30_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR8_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_ACBDLR8_RESERVED_31_30_MASK 0xC0000000U -/*Delay select for the BDL on Address A[11].*/ +/* +* Delay select for the BDL on Address A[11]. +*/ #undef DDR_PHY_ACBDLR8_A11BD_DEFVAL #undef DDR_PHY_ACBDLR8_A11BD_SHIFT #undef DDR_PHY_ACBDLR8_A11BD_MASK -#define DDR_PHY_ACBDLR8_A11BD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR8_A11BD_SHIFT 24 -#define DDR_PHY_ACBDLR8_A11BD_MASK 0x3F000000U +#define DDR_PHY_ACBDLR8_A11BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR8_A11BD_SHIFT 24 +#define DDR_PHY_ACBDLR8_A11BD_MASK 0x3F000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR8_RESERVED_23_22_DEFVAL #undef DDR_PHY_ACBDLR8_RESERVED_23_22_SHIFT #undef DDR_PHY_ACBDLR8_RESERVED_23_22_MASK -#define DDR_PHY_ACBDLR8_RESERVED_23_22_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR8_RESERVED_23_22_SHIFT 22 -#define DDR_PHY_ACBDLR8_RESERVED_23_22_MASK 0x00C00000U +#define DDR_PHY_ACBDLR8_RESERVED_23_22_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR8_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_ACBDLR8_RESERVED_23_22_MASK 0x00C00000U -/*Delay select for the BDL on Address A[10].*/ +/* +* Delay select for the BDL on Address A[10]. +*/ #undef DDR_PHY_ACBDLR8_A10BD_DEFVAL #undef DDR_PHY_ACBDLR8_A10BD_SHIFT #undef DDR_PHY_ACBDLR8_A10BD_MASK -#define DDR_PHY_ACBDLR8_A10BD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR8_A10BD_SHIFT 16 -#define DDR_PHY_ACBDLR8_A10BD_MASK 0x003F0000U +#define DDR_PHY_ACBDLR8_A10BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR8_A10BD_SHIFT 16 +#define DDR_PHY_ACBDLR8_A10BD_MASK 0x003F0000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR8_RESERVED_15_14_DEFVAL #undef DDR_PHY_ACBDLR8_RESERVED_15_14_SHIFT #undef DDR_PHY_ACBDLR8_RESERVED_15_14_MASK -#define DDR_PHY_ACBDLR8_RESERVED_15_14_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR8_RESERVED_15_14_SHIFT 14 -#define DDR_PHY_ACBDLR8_RESERVED_15_14_MASK 0x0000C000U +#define DDR_PHY_ACBDLR8_RESERVED_15_14_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR8_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_ACBDLR8_RESERVED_15_14_MASK 0x0000C000U -/*Delay select for the BDL on Address A[9].*/ +/* +* Delay select for the BDL on Address A[9]. +*/ #undef DDR_PHY_ACBDLR8_A09BD_DEFVAL #undef DDR_PHY_ACBDLR8_A09BD_SHIFT #undef DDR_PHY_ACBDLR8_A09BD_MASK -#define DDR_PHY_ACBDLR8_A09BD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR8_A09BD_SHIFT 8 -#define DDR_PHY_ACBDLR8_A09BD_MASK 0x00003F00U +#define DDR_PHY_ACBDLR8_A09BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR8_A09BD_SHIFT 8 +#define DDR_PHY_ACBDLR8_A09BD_MASK 0x00003F00U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR8_RESERVED_7_6_DEFVAL #undef DDR_PHY_ACBDLR8_RESERVED_7_6_SHIFT #undef DDR_PHY_ACBDLR8_RESERVED_7_6_MASK -#define DDR_PHY_ACBDLR8_RESERVED_7_6_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR8_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_ACBDLR8_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_ACBDLR8_RESERVED_7_6_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR8_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_ACBDLR8_RESERVED_7_6_MASK 0x000000C0U -/*Delay select for the BDL on Address A[8].*/ +/* +* Delay select for the BDL on Address A[8]. +*/ #undef DDR_PHY_ACBDLR8_A08BD_DEFVAL #undef DDR_PHY_ACBDLR8_A08BD_SHIFT #undef DDR_PHY_ACBDLR8_A08BD_MASK -#define DDR_PHY_ACBDLR8_A08BD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR8_A08BD_SHIFT 0 -#define DDR_PHY_ACBDLR8_A08BD_MASK 0x0000003FU +#define DDR_PHY_ACBDLR8_A08BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR8_A08BD_SHIFT 0 +#define DDR_PHY_ACBDLR8_A08BD_MASK 0x0000003FU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR9_RESERVED_31_30_DEFVAL #undef DDR_PHY_ACBDLR9_RESERVED_31_30_SHIFT #undef DDR_PHY_ACBDLR9_RESERVED_31_30_MASK -#define DDR_PHY_ACBDLR9_RESERVED_31_30_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR9_RESERVED_31_30_SHIFT 30 -#define DDR_PHY_ACBDLR9_RESERVED_31_30_MASK 0xC0000000U +#define DDR_PHY_ACBDLR9_RESERVED_31_30_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR9_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_ACBDLR9_RESERVED_31_30_MASK 0xC0000000U -/*Delay select for the BDL on Address A[15].*/ +/* +* Delay select for the BDL on Address A[15]. +*/ #undef DDR_PHY_ACBDLR9_A15BD_DEFVAL #undef DDR_PHY_ACBDLR9_A15BD_SHIFT #undef DDR_PHY_ACBDLR9_A15BD_MASK -#define DDR_PHY_ACBDLR9_A15BD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR9_A15BD_SHIFT 24 -#define DDR_PHY_ACBDLR9_A15BD_MASK 0x3F000000U +#define DDR_PHY_ACBDLR9_A15BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR9_A15BD_SHIFT 24 +#define DDR_PHY_ACBDLR9_A15BD_MASK 0x3F000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR9_RESERVED_23_22_DEFVAL #undef DDR_PHY_ACBDLR9_RESERVED_23_22_SHIFT #undef DDR_PHY_ACBDLR9_RESERVED_23_22_MASK -#define DDR_PHY_ACBDLR9_RESERVED_23_22_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR9_RESERVED_23_22_SHIFT 22 -#define DDR_PHY_ACBDLR9_RESERVED_23_22_MASK 0x00C00000U +#define DDR_PHY_ACBDLR9_RESERVED_23_22_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR9_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_ACBDLR9_RESERVED_23_22_MASK 0x00C00000U -/*Delay select for the BDL on Address A[14].*/ +/* +* Delay select for the BDL on Address A[14]. +*/ #undef DDR_PHY_ACBDLR9_A14BD_DEFVAL #undef DDR_PHY_ACBDLR9_A14BD_SHIFT #undef DDR_PHY_ACBDLR9_A14BD_MASK -#define DDR_PHY_ACBDLR9_A14BD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR9_A14BD_SHIFT 16 -#define DDR_PHY_ACBDLR9_A14BD_MASK 0x003F0000U +#define DDR_PHY_ACBDLR9_A14BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR9_A14BD_SHIFT 16 +#define DDR_PHY_ACBDLR9_A14BD_MASK 0x003F0000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR9_RESERVED_15_14_DEFVAL #undef DDR_PHY_ACBDLR9_RESERVED_15_14_SHIFT #undef DDR_PHY_ACBDLR9_RESERVED_15_14_MASK -#define DDR_PHY_ACBDLR9_RESERVED_15_14_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR9_RESERVED_15_14_SHIFT 14 -#define DDR_PHY_ACBDLR9_RESERVED_15_14_MASK 0x0000C000U +#define DDR_PHY_ACBDLR9_RESERVED_15_14_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR9_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_ACBDLR9_RESERVED_15_14_MASK 0x0000C000U -/*Delay select for the BDL on Address A[13].*/ +/* +* Delay select for the BDL on Address A[13]. +*/ #undef DDR_PHY_ACBDLR9_A13BD_DEFVAL #undef DDR_PHY_ACBDLR9_A13BD_SHIFT #undef DDR_PHY_ACBDLR9_A13BD_MASK -#define DDR_PHY_ACBDLR9_A13BD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR9_A13BD_SHIFT 8 -#define DDR_PHY_ACBDLR9_A13BD_MASK 0x00003F00U +#define DDR_PHY_ACBDLR9_A13BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR9_A13BD_SHIFT 8 +#define DDR_PHY_ACBDLR9_A13BD_MASK 0x00003F00U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ACBDLR9_RESERVED_7_6_DEFVAL #undef DDR_PHY_ACBDLR9_RESERVED_7_6_SHIFT #undef DDR_PHY_ACBDLR9_RESERVED_7_6_MASK -#define DDR_PHY_ACBDLR9_RESERVED_7_6_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR9_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_ACBDLR9_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_ACBDLR9_RESERVED_7_6_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR9_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_ACBDLR9_RESERVED_7_6_MASK 0x000000C0U -/*Delay select for the BDL on Address A[12].*/ +/* +* Delay select for the BDL on Address A[12]. +*/ #undef DDR_PHY_ACBDLR9_A12BD_DEFVAL #undef DDR_PHY_ACBDLR9_A12BD_SHIFT #undef DDR_PHY_ACBDLR9_A12BD_MASK -#define DDR_PHY_ACBDLR9_A12BD_DEFVAL 0x00000000 -#define DDR_PHY_ACBDLR9_A12BD_SHIFT 0 -#define DDR_PHY_ACBDLR9_A12BD_MASK 0x0000003FU +#define DDR_PHY_ACBDLR9_A12BD_DEFVAL 0x00000000 +#define DDR_PHY_ACBDLR9_A12BD_SHIFT 0 +#define DDR_PHY_ACBDLR9_A12BD_MASK 0x0000003FU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_ZQCR_RESERVED_31_26_DEFVAL #undef DDR_PHY_ZQCR_RESERVED_31_26_SHIFT #undef DDR_PHY_ZQCR_RESERVED_31_26_MASK -#define DDR_PHY_ZQCR_RESERVED_31_26_DEFVAL 0x008A2858 -#define DDR_PHY_ZQCR_RESERVED_31_26_SHIFT 26 -#define DDR_PHY_ZQCR_RESERVED_31_26_MASK 0xFC000000U +#define DDR_PHY_ZQCR_RESERVED_31_26_DEFVAL 0x008A2858 +#define DDR_PHY_ZQCR_RESERVED_31_26_SHIFT 26 +#define DDR_PHY_ZQCR_RESERVED_31_26_MASK 0xFC000000U -/*ZQ VREF Range*/ +/* +* ZQ VREF Range +*/ #undef DDR_PHY_ZQCR_ZQREFISELRANGE_DEFVAL #undef DDR_PHY_ZQCR_ZQREFISELRANGE_SHIFT #undef DDR_PHY_ZQCR_ZQREFISELRANGE_MASK -#define DDR_PHY_ZQCR_ZQREFISELRANGE_DEFVAL 0x008A2858 -#define DDR_PHY_ZQCR_ZQREFISELRANGE_SHIFT 25 -#define DDR_PHY_ZQCR_ZQREFISELRANGE_MASK 0x02000000U +#define DDR_PHY_ZQCR_ZQREFISELRANGE_DEFVAL 0x008A2858 +#define DDR_PHY_ZQCR_ZQREFISELRANGE_SHIFT 25 +#define DDR_PHY_ZQCR_ZQREFISELRANGE_MASK 0x02000000U -/*Programmable Wait for Frequency B*/ +/* +* Programmable Wait for Frequency B +*/ #undef DDR_PHY_ZQCR_PGWAIT_FRQB_DEFVAL #undef DDR_PHY_ZQCR_PGWAIT_FRQB_SHIFT #undef DDR_PHY_ZQCR_PGWAIT_FRQB_MASK -#define DDR_PHY_ZQCR_PGWAIT_FRQB_DEFVAL 0x008A2858 -#define DDR_PHY_ZQCR_PGWAIT_FRQB_SHIFT 19 -#define DDR_PHY_ZQCR_PGWAIT_FRQB_MASK 0x01F80000U +#define DDR_PHY_ZQCR_PGWAIT_FRQB_DEFVAL 0x008A2858 +#define DDR_PHY_ZQCR_PGWAIT_FRQB_SHIFT 19 +#define DDR_PHY_ZQCR_PGWAIT_FRQB_MASK 0x01F80000U -/*Programmable Wait for Frequency A*/ +/* +* Programmable Wait for Frequency A +*/ #undef DDR_PHY_ZQCR_PGWAIT_FRQA_DEFVAL #undef DDR_PHY_ZQCR_PGWAIT_FRQA_SHIFT #undef DDR_PHY_ZQCR_PGWAIT_FRQA_MASK -#define DDR_PHY_ZQCR_PGWAIT_FRQA_DEFVAL 0x008A2858 -#define DDR_PHY_ZQCR_PGWAIT_FRQA_SHIFT 13 -#define DDR_PHY_ZQCR_PGWAIT_FRQA_MASK 0x0007E000U +#define DDR_PHY_ZQCR_PGWAIT_FRQA_DEFVAL 0x008A2858 +#define DDR_PHY_ZQCR_PGWAIT_FRQA_SHIFT 13 +#define DDR_PHY_ZQCR_PGWAIT_FRQA_MASK 0x0007E000U -/*ZQ VREF Pad Enable*/ +/* +* ZQ VREF Pad Enable +*/ #undef DDR_PHY_ZQCR_ZQREFPEN_DEFVAL #undef DDR_PHY_ZQCR_ZQREFPEN_SHIFT #undef DDR_PHY_ZQCR_ZQREFPEN_MASK -#define DDR_PHY_ZQCR_ZQREFPEN_DEFVAL 0x008A2858 -#define DDR_PHY_ZQCR_ZQREFPEN_SHIFT 12 -#define DDR_PHY_ZQCR_ZQREFPEN_MASK 0x00001000U +#define DDR_PHY_ZQCR_ZQREFPEN_DEFVAL 0x008A2858 +#define DDR_PHY_ZQCR_ZQREFPEN_SHIFT 12 +#define DDR_PHY_ZQCR_ZQREFPEN_MASK 0x00001000U -/*ZQ Internal VREF Enable*/ +/* +* ZQ Internal VREF Enable +*/ #undef DDR_PHY_ZQCR_ZQREFIEN_DEFVAL #undef DDR_PHY_ZQCR_ZQREFIEN_SHIFT #undef DDR_PHY_ZQCR_ZQREFIEN_MASK -#define DDR_PHY_ZQCR_ZQREFIEN_DEFVAL 0x008A2858 -#define DDR_PHY_ZQCR_ZQREFIEN_SHIFT 11 -#define DDR_PHY_ZQCR_ZQREFIEN_MASK 0x00000800U +#define DDR_PHY_ZQCR_ZQREFIEN_DEFVAL 0x008A2858 +#define DDR_PHY_ZQCR_ZQREFIEN_SHIFT 11 +#define DDR_PHY_ZQCR_ZQREFIEN_MASK 0x00000800U -/*Choice of termination mode*/ +/* +* Choice of termination mode +*/ #undef DDR_PHY_ZQCR_ODT_MODE_DEFVAL #undef DDR_PHY_ZQCR_ODT_MODE_SHIFT #undef DDR_PHY_ZQCR_ODT_MODE_MASK -#define DDR_PHY_ZQCR_ODT_MODE_DEFVAL 0x008A2858 -#define DDR_PHY_ZQCR_ODT_MODE_SHIFT 9 -#define DDR_PHY_ZQCR_ODT_MODE_MASK 0x00000600U +#define DDR_PHY_ZQCR_ODT_MODE_DEFVAL 0x008A2858 +#define DDR_PHY_ZQCR_ODT_MODE_SHIFT 9 +#define DDR_PHY_ZQCR_ODT_MODE_MASK 0x00000600U -/*Force ZCAL VT update*/ +/* +* Force ZCAL VT update +*/ #undef DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_DEFVAL #undef DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_SHIFT #undef DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_MASK -#define DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_DEFVAL 0x008A2858 -#define DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_SHIFT 8 -#define DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_MASK 0x00000100U +#define DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_DEFVAL 0x008A2858 +#define DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_SHIFT 8 +#define DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_MASK 0x00000100U -/*IO VT Drift Limit*/ +/* +* IO VT Drift Limit +*/ #undef DDR_PHY_ZQCR_IODLMT_DEFVAL #undef DDR_PHY_ZQCR_IODLMT_SHIFT #undef DDR_PHY_ZQCR_IODLMT_MASK -#define DDR_PHY_ZQCR_IODLMT_DEFVAL 0x008A2858 -#define DDR_PHY_ZQCR_IODLMT_SHIFT 5 -#define DDR_PHY_ZQCR_IODLMT_MASK 0x000000E0U +#define DDR_PHY_ZQCR_IODLMT_DEFVAL 0x008A2858 +#define DDR_PHY_ZQCR_IODLMT_SHIFT 5 +#define DDR_PHY_ZQCR_IODLMT_MASK 0x000000E0U -/*Averaging algorithm enable, if set, enables averaging algorithm*/ +/* +* Averaging algorithm enable, if set, enables averaging algorithm +*/ #undef DDR_PHY_ZQCR_AVGEN_DEFVAL #undef DDR_PHY_ZQCR_AVGEN_SHIFT #undef DDR_PHY_ZQCR_AVGEN_MASK -#define DDR_PHY_ZQCR_AVGEN_DEFVAL 0x008A2858 -#define DDR_PHY_ZQCR_AVGEN_SHIFT 4 -#define DDR_PHY_ZQCR_AVGEN_MASK 0x00000010U +#define DDR_PHY_ZQCR_AVGEN_DEFVAL 0x008A2858 +#define DDR_PHY_ZQCR_AVGEN_SHIFT 4 +#define DDR_PHY_ZQCR_AVGEN_MASK 0x00000010U -/*Maximum number of averaging rounds to be used by averaging algorithm*/ +/* +* Maximum number of averaging rounds to be used by averaging algorithm +*/ #undef DDR_PHY_ZQCR_AVGMAX_DEFVAL #undef DDR_PHY_ZQCR_AVGMAX_SHIFT #undef DDR_PHY_ZQCR_AVGMAX_MASK -#define DDR_PHY_ZQCR_AVGMAX_DEFVAL 0x008A2858 -#define DDR_PHY_ZQCR_AVGMAX_SHIFT 2 -#define DDR_PHY_ZQCR_AVGMAX_MASK 0x0000000CU +#define DDR_PHY_ZQCR_AVGMAX_DEFVAL 0x008A2858 +#define DDR_PHY_ZQCR_AVGMAX_SHIFT 2 +#define DDR_PHY_ZQCR_AVGMAX_MASK 0x0000000CU -/*ZQ Calibration Type*/ +/* +* ZQ Calibration Type +*/ #undef DDR_PHY_ZQCR_ZCALT_DEFVAL #undef DDR_PHY_ZQCR_ZCALT_SHIFT #undef DDR_PHY_ZQCR_ZCALT_MASK -#define DDR_PHY_ZQCR_ZCALT_DEFVAL 0x008A2858 -#define DDR_PHY_ZQCR_ZCALT_SHIFT 1 -#define DDR_PHY_ZQCR_ZCALT_MASK 0x00000002U +#define DDR_PHY_ZQCR_ZCALT_DEFVAL 0x008A2858 +#define DDR_PHY_ZQCR_ZCALT_SHIFT 1 +#define DDR_PHY_ZQCR_ZCALT_MASK 0x00000002U -/*ZQ Power Down*/ +/* +* ZQ Power Down +*/ #undef DDR_PHY_ZQCR_ZQPD_DEFVAL #undef DDR_PHY_ZQCR_ZQPD_SHIFT #undef DDR_PHY_ZQCR_ZQPD_MASK -#define DDR_PHY_ZQCR_ZQPD_DEFVAL 0x008A2858 -#define DDR_PHY_ZQCR_ZQPD_SHIFT 0 -#define DDR_PHY_ZQCR_ZQPD_MASK 0x00000001U +#define DDR_PHY_ZQCR_ZQPD_DEFVAL 0x008A2858 +#define DDR_PHY_ZQCR_ZQPD_SHIFT 0 +#define DDR_PHY_ZQCR_ZQPD_MASK 0x00000001U -/*Pull-down drive strength ZCTRL over-ride enable*/ +/* +* Pull-down drive strength ZCTRL over-ride enable +*/ #undef DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_DEFVAL #undef DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_SHIFT #undef DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_MASK -#define DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_DEFVAL 0x000077BB -#define DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_SHIFT 31 -#define DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_MASK 0x80000000U +#define DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_DEFVAL 0x000077BB +#define DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_SHIFT 31 +#define DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_MASK 0x80000000U -/*Pull-up drive strength ZCTRL over-ride enable*/ +/* +* Pull-up drive strength ZCTRL over-ride enable +*/ #undef DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_DEFVAL #undef DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_SHIFT #undef DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_MASK -#define DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_DEFVAL 0x000077BB -#define DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_SHIFT 30 -#define DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_MASK 0x40000000U +#define DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_DEFVAL 0x000077BB +#define DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_SHIFT 30 +#define DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_MASK 0x40000000U -/*Pull-down termination ZCTRL over-ride enable*/ +/* +* Pull-down termination ZCTRL over-ride enable +*/ #undef DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_DEFVAL #undef DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_SHIFT #undef DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_MASK -#define DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_DEFVAL 0x000077BB -#define DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_SHIFT 29 -#define DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_MASK 0x20000000U +#define DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_DEFVAL 0x000077BB +#define DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_SHIFT 29 +#define DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_MASK 0x20000000U -/*Pull-up termination ZCTRL over-ride enable*/ +/* +* Pull-up termination ZCTRL over-ride enable +*/ #undef DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_DEFVAL #undef DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_SHIFT #undef DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_MASK -#define DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_DEFVAL 0x000077BB -#define DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_SHIFT 28 -#define DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_MASK 0x10000000U +#define DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_DEFVAL 0x000077BB +#define DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_SHIFT 28 +#define DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_MASK 0x10000000U -/*Calibration segment bypass*/ +/* +* Calibration segment bypass +*/ #undef DDR_PHY_ZQ0PR0_ZSEGBYP_DEFVAL #undef DDR_PHY_ZQ0PR0_ZSEGBYP_SHIFT #undef DDR_PHY_ZQ0PR0_ZSEGBYP_MASK -#define DDR_PHY_ZQ0PR0_ZSEGBYP_DEFVAL 0x000077BB -#define DDR_PHY_ZQ0PR0_ZSEGBYP_SHIFT 27 -#define DDR_PHY_ZQ0PR0_ZSEGBYP_MASK 0x08000000U +#define DDR_PHY_ZQ0PR0_ZSEGBYP_DEFVAL 0x000077BB +#define DDR_PHY_ZQ0PR0_ZSEGBYP_SHIFT 27 +#define DDR_PHY_ZQ0PR0_ZSEGBYP_MASK 0x08000000U -/*VREF latch mode controls the mode in which the ZLE pin of the PVREF cell is driven by the PUB*/ +/* +* VREF latch mode controls the mode in which the ZLE pin of the PVREF cell + * is driven by the PUB +*/ #undef DDR_PHY_ZQ0PR0_ZLE_MODE_DEFVAL #undef DDR_PHY_ZQ0PR0_ZLE_MODE_SHIFT #undef DDR_PHY_ZQ0PR0_ZLE_MODE_MASK -#define DDR_PHY_ZQ0PR0_ZLE_MODE_DEFVAL 0x000077BB -#define DDR_PHY_ZQ0PR0_ZLE_MODE_SHIFT 25 -#define DDR_PHY_ZQ0PR0_ZLE_MODE_MASK 0x06000000U +#define DDR_PHY_ZQ0PR0_ZLE_MODE_DEFVAL 0x000077BB +#define DDR_PHY_ZQ0PR0_ZLE_MODE_SHIFT 25 +#define DDR_PHY_ZQ0PR0_ZLE_MODE_MASK 0x06000000U -/*Termination adjustment*/ +/* +* Termination adjustment +*/ #undef DDR_PHY_ZQ0PR0_ODT_ADJUST_DEFVAL #undef DDR_PHY_ZQ0PR0_ODT_ADJUST_SHIFT #undef DDR_PHY_ZQ0PR0_ODT_ADJUST_MASK -#define DDR_PHY_ZQ0PR0_ODT_ADJUST_DEFVAL 0x000077BB -#define DDR_PHY_ZQ0PR0_ODT_ADJUST_SHIFT 22 -#define DDR_PHY_ZQ0PR0_ODT_ADJUST_MASK 0x01C00000U +#define DDR_PHY_ZQ0PR0_ODT_ADJUST_DEFVAL 0x000077BB +#define DDR_PHY_ZQ0PR0_ODT_ADJUST_SHIFT 22 +#define DDR_PHY_ZQ0PR0_ODT_ADJUST_MASK 0x01C00000U -/*Pulldown drive strength adjustment*/ +/* +* Pulldown drive strength adjustment +*/ #undef DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_DEFVAL #undef DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_SHIFT #undef DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_MASK -#define DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_DEFVAL 0x000077BB -#define DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_SHIFT 19 -#define DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_MASK 0x00380000U +#define DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_DEFVAL 0x000077BB +#define DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_SHIFT 19 +#define DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_MASK 0x00380000U -/*Pullup drive strength adjustment*/ +/* +* Pullup drive strength adjustment +*/ #undef DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_DEFVAL #undef DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_SHIFT #undef DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_MASK -#define DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_DEFVAL 0x000077BB -#define DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_SHIFT 16 -#define DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_MASK 0x00070000U +#define DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_DEFVAL 0x000077BB +#define DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_SHIFT 16 +#define DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_MASK 0x00070000U -/*DRAM Impedance Divide Ratio*/ +/* +* DRAM Impedance Divide Ratio +*/ #undef DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_DEFVAL #undef DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_SHIFT #undef DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_MASK -#define DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_DEFVAL 0x000077BB -#define DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_SHIFT 12 -#define DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_MASK 0x0000F000U +#define DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_DEFVAL 0x000077BB +#define DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_SHIFT 12 +#define DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_MASK 0x0000F000U -/*HOST Impedance Divide Ratio*/ +/* +* HOST Impedance Divide Ratio +*/ #undef DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_DEFVAL #undef DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_SHIFT #undef DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_MASK -#define DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_DEFVAL 0x000077BB -#define DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_SHIFT 8 -#define DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_MASK 0x00000F00U +#define DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_DEFVAL 0x000077BB +#define DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_SHIFT 8 +#define DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_MASK 0x00000F00U -/*Impedance Divide Ratio (pulldown drive calibration during asymmetric drive strength calibration)*/ +/* +* Impedance Divide Ratio (pulldown drive calibration during asymmetric dri + * ve strength calibration) +*/ #undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_DEFVAL #undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_SHIFT #undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_MASK -#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_DEFVAL 0x000077BB -#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_SHIFT 4 -#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_MASK 0x000000F0U +#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_DEFVAL 0x000077BB +#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_SHIFT 4 +#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_MASK 0x000000F0U -/*Impedance Divide Ratio (pullup drive calibration during asymmetric drive strength calibration)*/ +/* +* Impedance Divide Ratio (pullup drive calibration during asymmetric drive + * strength calibration) +*/ #undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_DEFVAL #undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_SHIFT #undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_MASK -#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_DEFVAL 0x000077BB -#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_SHIFT 0 -#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_MASK 0x0000000FU +#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_DEFVAL 0x000077BB +#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_SHIFT 0 +#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_MASK 0x0000000FU -/*Reserved. Return zeros on reads.*/ +/* +* Reserved. Return zeros on reads. +*/ #undef DDR_PHY_ZQ0OR0_RESERVED_31_26_DEFVAL #undef DDR_PHY_ZQ0OR0_RESERVED_31_26_SHIFT #undef DDR_PHY_ZQ0OR0_RESERVED_31_26_MASK -#define DDR_PHY_ZQ0OR0_RESERVED_31_26_DEFVAL 0x00000000 -#define DDR_PHY_ZQ0OR0_RESERVED_31_26_SHIFT 26 -#define DDR_PHY_ZQ0OR0_RESERVED_31_26_MASK 0xFC000000U +#define DDR_PHY_ZQ0OR0_RESERVED_31_26_DEFVAL 0x00000000 +#define DDR_PHY_ZQ0OR0_RESERVED_31_26_SHIFT 26 +#define DDR_PHY_ZQ0OR0_RESERVED_31_26_MASK 0xFC000000U -/*Override value for the pull-up output impedance*/ +/* +* Override value for the pull-up output impedance +*/ #undef DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_DEFVAL #undef DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_SHIFT #undef DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_MASK -#define DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_DEFVAL 0x00000000 -#define DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_SHIFT 16 -#define DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_MASK 0x03FF0000U +#define DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_DEFVAL 0x00000000 +#define DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_SHIFT 16 +#define DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_MASK 0x03FF0000U -/*Reserved. Return zeros on reads.*/ +/* +* Reserved. Return zeros on reads. +*/ #undef DDR_PHY_ZQ0OR0_RESERVED_15_10_DEFVAL #undef DDR_PHY_ZQ0OR0_RESERVED_15_10_SHIFT #undef DDR_PHY_ZQ0OR0_RESERVED_15_10_MASK -#define DDR_PHY_ZQ0OR0_RESERVED_15_10_DEFVAL 0x00000000 -#define DDR_PHY_ZQ0OR0_RESERVED_15_10_SHIFT 10 -#define DDR_PHY_ZQ0OR0_RESERVED_15_10_MASK 0x0000FC00U +#define DDR_PHY_ZQ0OR0_RESERVED_15_10_DEFVAL 0x00000000 +#define DDR_PHY_ZQ0OR0_RESERVED_15_10_SHIFT 10 +#define DDR_PHY_ZQ0OR0_RESERVED_15_10_MASK 0x0000FC00U -/*Override value for the pull-down output impedance*/ +/* +* Override value for the pull-down output impedance +*/ #undef DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_DEFVAL #undef DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_SHIFT #undef DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_MASK -#define DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_DEFVAL 0x00000000 -#define DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_SHIFT 0 -#define DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_MASK 0x000003FFU +#define DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_DEFVAL 0x00000000 +#define DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_SHIFT 0 +#define DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_MASK 0x000003FFU -/*Reserved. Return zeros on reads.*/ +/* +* Reserved. Return zeros on reads. +*/ #undef DDR_PHY_ZQ0OR1_RESERVED_31_26_DEFVAL #undef DDR_PHY_ZQ0OR1_RESERVED_31_26_SHIFT #undef DDR_PHY_ZQ0OR1_RESERVED_31_26_MASK -#define DDR_PHY_ZQ0OR1_RESERVED_31_26_DEFVAL 0x00000000 -#define DDR_PHY_ZQ0OR1_RESERVED_31_26_SHIFT 26 -#define DDR_PHY_ZQ0OR1_RESERVED_31_26_MASK 0xFC000000U +#define DDR_PHY_ZQ0OR1_RESERVED_31_26_DEFVAL 0x00000000 +#define DDR_PHY_ZQ0OR1_RESERVED_31_26_SHIFT 26 +#define DDR_PHY_ZQ0OR1_RESERVED_31_26_MASK 0xFC000000U -/*Override value for the pull-up termination*/ +/* +* Override value for the pull-up termination +*/ #undef DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_DEFVAL #undef DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_SHIFT #undef DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_MASK -#define DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_DEFVAL 0x00000000 -#define DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_SHIFT 16 -#define DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_MASK 0x03FF0000U +#define DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_DEFVAL 0x00000000 +#define DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_SHIFT 16 +#define DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_MASK 0x03FF0000U -/*Reserved. Return zeros on reads.*/ +/* +* Reserved. Return zeros on reads. +*/ #undef DDR_PHY_ZQ0OR1_RESERVED_15_10_DEFVAL #undef DDR_PHY_ZQ0OR1_RESERVED_15_10_SHIFT #undef DDR_PHY_ZQ0OR1_RESERVED_15_10_MASK -#define DDR_PHY_ZQ0OR1_RESERVED_15_10_DEFVAL 0x00000000 -#define DDR_PHY_ZQ0OR1_RESERVED_15_10_SHIFT 10 -#define DDR_PHY_ZQ0OR1_RESERVED_15_10_MASK 0x0000FC00U +#define DDR_PHY_ZQ0OR1_RESERVED_15_10_DEFVAL 0x00000000 +#define DDR_PHY_ZQ0OR1_RESERVED_15_10_SHIFT 10 +#define DDR_PHY_ZQ0OR1_RESERVED_15_10_MASK 0x0000FC00U -/*Override value for the pull-down termination*/ +/* +* Override value for the pull-down termination +*/ #undef DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_DEFVAL #undef DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_SHIFT #undef DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_MASK -#define DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_DEFVAL 0x00000000 -#define DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_SHIFT 0 -#define DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_MASK 0x000003FFU +#define DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_DEFVAL 0x00000000 +#define DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_SHIFT 0 +#define DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_MASK 0x000003FFU -/*Pull-down drive strength ZCTRL over-ride enable*/ +/* +* Pull-down drive strength ZCTRL over-ride enable +*/ #undef DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_DEFVAL #undef DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_SHIFT #undef DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_MASK -#define DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_DEFVAL 0x000077BB -#define DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_SHIFT 31 -#define DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_MASK 0x80000000U +#define DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_DEFVAL 0x000077BB +#define DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_SHIFT 31 +#define DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_MASK 0x80000000U -/*Pull-up drive strength ZCTRL over-ride enable*/ +/* +* Pull-up drive strength ZCTRL over-ride enable +*/ #undef DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_DEFVAL #undef DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_SHIFT #undef DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_MASK -#define DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_DEFVAL 0x000077BB -#define DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_SHIFT 30 -#define DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_MASK 0x40000000U +#define DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_DEFVAL 0x000077BB +#define DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_SHIFT 30 +#define DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_MASK 0x40000000U -/*Pull-down termination ZCTRL over-ride enable*/ +/* +* Pull-down termination ZCTRL over-ride enable +*/ #undef DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_DEFVAL #undef DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_SHIFT #undef DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_MASK -#define DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_DEFVAL 0x000077BB -#define DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_SHIFT 29 -#define DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_MASK 0x20000000U +#define DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_DEFVAL 0x000077BB +#define DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_SHIFT 29 +#define DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_MASK 0x20000000U -/*Pull-up termination ZCTRL over-ride enable*/ +/* +* Pull-up termination ZCTRL over-ride enable +*/ #undef DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_DEFVAL #undef DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_SHIFT #undef DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_MASK -#define DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_DEFVAL 0x000077BB -#define DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_SHIFT 28 -#define DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_MASK 0x10000000U +#define DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_DEFVAL 0x000077BB +#define DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_SHIFT 28 +#define DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_MASK 0x10000000U -/*Calibration segment bypass*/ +/* +* Calibration segment bypass +*/ #undef DDR_PHY_ZQ1PR0_ZSEGBYP_DEFVAL #undef DDR_PHY_ZQ1PR0_ZSEGBYP_SHIFT #undef DDR_PHY_ZQ1PR0_ZSEGBYP_MASK -#define DDR_PHY_ZQ1PR0_ZSEGBYP_DEFVAL 0x000077BB -#define DDR_PHY_ZQ1PR0_ZSEGBYP_SHIFT 27 -#define DDR_PHY_ZQ1PR0_ZSEGBYP_MASK 0x08000000U +#define DDR_PHY_ZQ1PR0_ZSEGBYP_DEFVAL 0x000077BB +#define DDR_PHY_ZQ1PR0_ZSEGBYP_SHIFT 27 +#define DDR_PHY_ZQ1PR0_ZSEGBYP_MASK 0x08000000U -/*VREF latch mode controls the mode in which the ZLE pin of the PVREF cell is driven by the PUB*/ +/* +* VREF latch mode controls the mode in which the ZLE pin of the PVREF cell + * is driven by the PUB +*/ #undef DDR_PHY_ZQ1PR0_ZLE_MODE_DEFVAL #undef DDR_PHY_ZQ1PR0_ZLE_MODE_SHIFT #undef DDR_PHY_ZQ1PR0_ZLE_MODE_MASK -#define DDR_PHY_ZQ1PR0_ZLE_MODE_DEFVAL 0x000077BB -#define DDR_PHY_ZQ1PR0_ZLE_MODE_SHIFT 25 -#define DDR_PHY_ZQ1PR0_ZLE_MODE_MASK 0x06000000U +#define DDR_PHY_ZQ1PR0_ZLE_MODE_DEFVAL 0x000077BB +#define DDR_PHY_ZQ1PR0_ZLE_MODE_SHIFT 25 +#define DDR_PHY_ZQ1PR0_ZLE_MODE_MASK 0x06000000U -/*Termination adjustment*/ +/* +* Termination adjustment +*/ #undef DDR_PHY_ZQ1PR0_ODT_ADJUST_DEFVAL #undef DDR_PHY_ZQ1PR0_ODT_ADJUST_SHIFT #undef DDR_PHY_ZQ1PR0_ODT_ADJUST_MASK -#define DDR_PHY_ZQ1PR0_ODT_ADJUST_DEFVAL 0x000077BB -#define DDR_PHY_ZQ1PR0_ODT_ADJUST_SHIFT 22 -#define DDR_PHY_ZQ1PR0_ODT_ADJUST_MASK 0x01C00000U +#define DDR_PHY_ZQ1PR0_ODT_ADJUST_DEFVAL 0x000077BB +#define DDR_PHY_ZQ1PR0_ODT_ADJUST_SHIFT 22 +#define DDR_PHY_ZQ1PR0_ODT_ADJUST_MASK 0x01C00000U -/*Pulldown drive strength adjustment*/ +/* +* Pulldown drive strength adjustment +*/ #undef DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_DEFVAL #undef DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_SHIFT #undef DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_MASK -#define DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_DEFVAL 0x000077BB -#define DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_SHIFT 19 -#define DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_MASK 0x00380000U +#define DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_DEFVAL 0x000077BB +#define DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_SHIFT 19 +#define DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_MASK 0x00380000U -/*Pullup drive strength adjustment*/ +/* +* Pullup drive strength adjustment +*/ #undef DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_DEFVAL #undef DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_SHIFT #undef DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_MASK -#define DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_DEFVAL 0x000077BB -#define DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_SHIFT 16 -#define DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_MASK 0x00070000U +#define DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_DEFVAL 0x000077BB +#define DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_SHIFT 16 +#define DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_MASK 0x00070000U -/*DRAM Impedance Divide Ratio*/ +/* +* DRAM Impedance Divide Ratio +*/ #undef DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_DEFVAL #undef DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_SHIFT #undef DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_MASK -#define DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_DEFVAL 0x000077BB -#define DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_SHIFT 12 -#define DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_MASK 0x0000F000U +#define DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_DEFVAL 0x000077BB +#define DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_SHIFT 12 +#define DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_MASK 0x0000F000U -/*HOST Impedance Divide Ratio*/ +/* +* HOST Impedance Divide Ratio +*/ #undef DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_DEFVAL #undef DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_SHIFT #undef DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_MASK -#define DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_DEFVAL 0x000077BB -#define DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_SHIFT 8 -#define DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_MASK 0x00000F00U +#define DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_DEFVAL 0x000077BB +#define DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_SHIFT 8 +#define DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_MASK 0x00000F00U -/*Impedance Divide Ratio (pulldown drive calibration during asymmetric drive strength calibration)*/ +/* +* Impedance Divide Ratio (pulldown drive calibration during asymmetric dri + * ve strength calibration) +*/ #undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_DEFVAL #undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_SHIFT #undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_MASK -#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_DEFVAL 0x000077BB -#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_SHIFT 4 -#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_MASK 0x000000F0U +#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_DEFVAL 0x000077BB +#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_SHIFT 4 +#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_MASK 0x000000F0U -/*Impedance Divide Ratio (pullup drive calibration during asymmetric drive strength calibration)*/ +/* +* Impedance Divide Ratio (pullup drive calibration during asymmetric drive + * strength calibration) +*/ #undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_DEFVAL #undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_SHIFT #undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_MASK -#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_DEFVAL 0x000077BB -#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_SHIFT 0 -#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_MASK 0x0000000FU +#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_DEFVAL 0x000077BB +#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_SHIFT 0 +#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_MASK 0x0000000FU -/*Calibration Bypass*/ +/* +* Calibration Bypass +*/ #undef DDR_PHY_DX0GCR0_CALBYP_DEFVAL #undef DDR_PHY_DX0GCR0_CALBYP_SHIFT #undef DDR_PHY_DX0GCR0_CALBYP_MASK -#define DDR_PHY_DX0GCR0_CALBYP_DEFVAL 0x40200204 -#define DDR_PHY_DX0GCR0_CALBYP_SHIFT 31 -#define DDR_PHY_DX0GCR0_CALBYP_MASK 0x80000000U +#define DDR_PHY_DX0GCR0_CALBYP_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_CALBYP_SHIFT 31 +#define DDR_PHY_DX0GCR0_CALBYP_MASK 0x80000000U -/*Master Delay Line Enable*/ +/* +* Master Delay Line Enable +*/ #undef DDR_PHY_DX0GCR0_MDLEN_DEFVAL #undef DDR_PHY_DX0GCR0_MDLEN_SHIFT #undef DDR_PHY_DX0GCR0_MDLEN_MASK -#define DDR_PHY_DX0GCR0_MDLEN_DEFVAL 0x40200204 -#define DDR_PHY_DX0GCR0_MDLEN_SHIFT 30 -#define DDR_PHY_DX0GCR0_MDLEN_MASK 0x40000000U +#define DDR_PHY_DX0GCR0_MDLEN_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_MDLEN_SHIFT 30 +#define DDR_PHY_DX0GCR0_MDLEN_MASK 0x40000000U -/*Configurable ODT(TE) Phase Shift*/ +/* +* Configurable ODT(TE) Phase Shift +*/ #undef DDR_PHY_DX0GCR0_CODTSHFT_DEFVAL #undef DDR_PHY_DX0GCR0_CODTSHFT_SHIFT #undef DDR_PHY_DX0GCR0_CODTSHFT_MASK -#define DDR_PHY_DX0GCR0_CODTSHFT_DEFVAL 0x40200204 -#define DDR_PHY_DX0GCR0_CODTSHFT_SHIFT 28 -#define DDR_PHY_DX0GCR0_CODTSHFT_MASK 0x30000000U +#define DDR_PHY_DX0GCR0_CODTSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_CODTSHFT_SHIFT 28 +#define DDR_PHY_DX0GCR0_CODTSHFT_MASK 0x30000000U -/*DQS Duty Cycle Correction*/ +/* +* DQS Duty Cycle Correction +*/ #undef DDR_PHY_DX0GCR0_DQSDCC_DEFVAL #undef DDR_PHY_DX0GCR0_DQSDCC_SHIFT #undef DDR_PHY_DX0GCR0_DQSDCC_MASK -#define DDR_PHY_DX0GCR0_DQSDCC_DEFVAL 0x40200204 -#define DDR_PHY_DX0GCR0_DQSDCC_SHIFT 24 -#define DDR_PHY_DX0GCR0_DQSDCC_MASK 0x0F000000U +#define DDR_PHY_DX0GCR0_DQSDCC_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_DQSDCC_SHIFT 24 +#define DDR_PHY_DX0GCR0_DQSDCC_MASK 0x0F000000U -/*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/ +/* +* Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY +*/ #undef DDR_PHY_DX0GCR0_RDDLY_DEFVAL #undef DDR_PHY_DX0GCR0_RDDLY_SHIFT #undef DDR_PHY_DX0GCR0_RDDLY_MASK -#define DDR_PHY_DX0GCR0_RDDLY_DEFVAL 0x40200204 -#define DDR_PHY_DX0GCR0_RDDLY_SHIFT 20 -#define DDR_PHY_DX0GCR0_RDDLY_MASK 0x00F00000U +#define DDR_PHY_DX0GCR0_RDDLY_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_RDDLY_SHIFT 20 +#define DDR_PHY_DX0GCR0_RDDLY_MASK 0x00F00000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX0GCR0_RESERVED_19_14_DEFVAL #undef DDR_PHY_DX0GCR0_RESERVED_19_14_SHIFT #undef DDR_PHY_DX0GCR0_RESERVED_19_14_MASK -#define DDR_PHY_DX0GCR0_RESERVED_19_14_DEFVAL 0x40200204 -#define DDR_PHY_DX0GCR0_RESERVED_19_14_SHIFT 14 -#define DDR_PHY_DX0GCR0_RESERVED_19_14_MASK 0x000FC000U +#define DDR_PHY_DX0GCR0_RESERVED_19_14_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_RESERVED_19_14_SHIFT 14 +#define DDR_PHY_DX0GCR0_RESERVED_19_14_MASK 0x000FC000U -/*DQSNSE Power Down Receiver*/ +/* +* DQSNSE Power Down Receiver +*/ #undef DDR_PHY_DX0GCR0_DQSNSEPDR_DEFVAL #undef DDR_PHY_DX0GCR0_DQSNSEPDR_SHIFT #undef DDR_PHY_DX0GCR0_DQSNSEPDR_MASK -#define DDR_PHY_DX0GCR0_DQSNSEPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX0GCR0_DQSNSEPDR_SHIFT 13 -#define DDR_PHY_DX0GCR0_DQSNSEPDR_MASK 0x00002000U +#define DDR_PHY_DX0GCR0_DQSNSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_DQSNSEPDR_SHIFT 13 +#define DDR_PHY_DX0GCR0_DQSNSEPDR_MASK 0x00002000U -/*DQSSE Power Down Receiver*/ +/* +* DQSSE Power Down Receiver +*/ #undef DDR_PHY_DX0GCR0_DQSSEPDR_DEFVAL #undef DDR_PHY_DX0GCR0_DQSSEPDR_SHIFT #undef DDR_PHY_DX0GCR0_DQSSEPDR_MASK -#define DDR_PHY_DX0GCR0_DQSSEPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX0GCR0_DQSSEPDR_SHIFT 12 -#define DDR_PHY_DX0GCR0_DQSSEPDR_MASK 0x00001000U +#define DDR_PHY_DX0GCR0_DQSSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_DQSSEPDR_SHIFT 12 +#define DDR_PHY_DX0GCR0_DQSSEPDR_MASK 0x00001000U -/*RTT On Additive Latency*/ +/* +* RTT On Additive Latency +*/ #undef DDR_PHY_DX0GCR0_RTTOAL_DEFVAL #undef DDR_PHY_DX0GCR0_RTTOAL_SHIFT #undef DDR_PHY_DX0GCR0_RTTOAL_MASK -#define DDR_PHY_DX0GCR0_RTTOAL_DEFVAL 0x40200204 -#define DDR_PHY_DX0GCR0_RTTOAL_SHIFT 11 -#define DDR_PHY_DX0GCR0_RTTOAL_MASK 0x00000800U +#define DDR_PHY_DX0GCR0_RTTOAL_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_RTTOAL_SHIFT 11 +#define DDR_PHY_DX0GCR0_RTTOAL_MASK 0x00000800U -/*RTT Output Hold*/ +/* +* RTT Output Hold +*/ #undef DDR_PHY_DX0GCR0_RTTOH_DEFVAL #undef DDR_PHY_DX0GCR0_RTTOH_SHIFT #undef DDR_PHY_DX0GCR0_RTTOH_MASK -#define DDR_PHY_DX0GCR0_RTTOH_DEFVAL 0x40200204 -#define DDR_PHY_DX0GCR0_RTTOH_SHIFT 9 -#define DDR_PHY_DX0GCR0_RTTOH_MASK 0x00000600U +#define DDR_PHY_DX0GCR0_RTTOH_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_RTTOH_SHIFT 9 +#define DDR_PHY_DX0GCR0_RTTOH_MASK 0x00000600U -/*Configurable PDR Phase Shift*/ +/* +* Configurable PDR Phase Shift +*/ #undef DDR_PHY_DX0GCR0_CPDRSHFT_DEFVAL #undef DDR_PHY_DX0GCR0_CPDRSHFT_SHIFT #undef DDR_PHY_DX0GCR0_CPDRSHFT_MASK -#define DDR_PHY_DX0GCR0_CPDRSHFT_DEFVAL 0x40200204 -#define DDR_PHY_DX0GCR0_CPDRSHFT_SHIFT 7 -#define DDR_PHY_DX0GCR0_CPDRSHFT_MASK 0x00000180U +#define DDR_PHY_DX0GCR0_CPDRSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_CPDRSHFT_SHIFT 7 +#define DDR_PHY_DX0GCR0_CPDRSHFT_MASK 0x00000180U -/*DQSR Power Down*/ +/* +* DQSR Power Down +*/ #undef DDR_PHY_DX0GCR0_DQSRPD_DEFVAL #undef DDR_PHY_DX0GCR0_DQSRPD_SHIFT #undef DDR_PHY_DX0GCR0_DQSRPD_MASK -#define DDR_PHY_DX0GCR0_DQSRPD_DEFVAL 0x40200204 -#define DDR_PHY_DX0GCR0_DQSRPD_SHIFT 6 -#define DDR_PHY_DX0GCR0_DQSRPD_MASK 0x00000040U +#define DDR_PHY_DX0GCR0_DQSRPD_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_DQSRPD_SHIFT 6 +#define DDR_PHY_DX0GCR0_DQSRPD_MASK 0x00000040U -/*DQSG Power Down Receiver*/ +/* +* DQSG Power Down Receiver +*/ #undef DDR_PHY_DX0GCR0_DQSGPDR_DEFVAL #undef DDR_PHY_DX0GCR0_DQSGPDR_SHIFT #undef DDR_PHY_DX0GCR0_DQSGPDR_MASK -#define DDR_PHY_DX0GCR0_DQSGPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX0GCR0_DQSGPDR_SHIFT 5 -#define DDR_PHY_DX0GCR0_DQSGPDR_MASK 0x00000020U +#define DDR_PHY_DX0GCR0_DQSGPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_DQSGPDR_SHIFT 5 +#define DDR_PHY_DX0GCR0_DQSGPDR_MASK 0x00000020U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX0GCR0_RESERVED_4_DEFVAL #undef DDR_PHY_DX0GCR0_RESERVED_4_SHIFT #undef DDR_PHY_DX0GCR0_RESERVED_4_MASK -#define DDR_PHY_DX0GCR0_RESERVED_4_DEFVAL 0x40200204 -#define DDR_PHY_DX0GCR0_RESERVED_4_SHIFT 4 -#define DDR_PHY_DX0GCR0_RESERVED_4_MASK 0x00000010U +#define DDR_PHY_DX0GCR0_RESERVED_4_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_RESERVED_4_SHIFT 4 +#define DDR_PHY_DX0GCR0_RESERVED_4_MASK 0x00000010U -/*DQSG On-Die Termination*/ +/* +* DQSG On-Die Termination +*/ #undef DDR_PHY_DX0GCR0_DQSGODT_DEFVAL #undef DDR_PHY_DX0GCR0_DQSGODT_SHIFT #undef DDR_PHY_DX0GCR0_DQSGODT_MASK -#define DDR_PHY_DX0GCR0_DQSGODT_DEFVAL 0x40200204 -#define DDR_PHY_DX0GCR0_DQSGODT_SHIFT 3 -#define DDR_PHY_DX0GCR0_DQSGODT_MASK 0x00000008U +#define DDR_PHY_DX0GCR0_DQSGODT_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_DQSGODT_SHIFT 3 +#define DDR_PHY_DX0GCR0_DQSGODT_MASK 0x00000008U -/*DQSG Output Enable*/ +/* +* DQSG Output Enable +*/ #undef DDR_PHY_DX0GCR0_DQSGOE_DEFVAL #undef DDR_PHY_DX0GCR0_DQSGOE_SHIFT #undef DDR_PHY_DX0GCR0_DQSGOE_MASK -#define DDR_PHY_DX0GCR0_DQSGOE_DEFVAL 0x40200204 -#define DDR_PHY_DX0GCR0_DQSGOE_SHIFT 2 -#define DDR_PHY_DX0GCR0_DQSGOE_MASK 0x00000004U +#define DDR_PHY_DX0GCR0_DQSGOE_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_DQSGOE_SHIFT 2 +#define DDR_PHY_DX0GCR0_DQSGOE_MASK 0x00000004U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX0GCR0_RESERVED_1_0_DEFVAL #undef DDR_PHY_DX0GCR0_RESERVED_1_0_SHIFT #undef DDR_PHY_DX0GCR0_RESERVED_1_0_MASK -#define DDR_PHY_DX0GCR0_RESERVED_1_0_DEFVAL 0x40200204 -#define DDR_PHY_DX0GCR0_RESERVED_1_0_SHIFT 0 -#define DDR_PHY_DX0GCR0_RESERVED_1_0_MASK 0x00000003U +#define DDR_PHY_DX0GCR0_RESERVED_1_0_DEFVAL 0x40200204 +#define DDR_PHY_DX0GCR0_RESERVED_1_0_SHIFT 0 +#define DDR_PHY_DX0GCR0_RESERVED_1_0_MASK 0x00000003U -/*Byte lane VREF IOM (Used only by D4MU IOs)*/ +/* +* Byte lane VREF IOM (Used only by D4MU IOs) +*/ #undef DDR_PHY_DX0GCR4_RESERVED_31_29_DEFVAL #undef DDR_PHY_DX0GCR4_RESERVED_31_29_SHIFT #undef DDR_PHY_DX0GCR4_RESERVED_31_29_MASK -#define DDR_PHY_DX0GCR4_RESERVED_31_29_DEFVAL 0x0E00003C -#define DDR_PHY_DX0GCR4_RESERVED_31_29_SHIFT 29 -#define DDR_PHY_DX0GCR4_RESERVED_31_29_MASK 0xE0000000U +#define DDR_PHY_DX0GCR4_RESERVED_31_29_DEFVAL 0x0E00003C +#define DDR_PHY_DX0GCR4_RESERVED_31_29_SHIFT 29 +#define DDR_PHY_DX0GCR4_RESERVED_31_29_MASK 0xE0000000U -/*Byte Lane VREF Pad Enable*/ +/* +* Byte Lane VREF Pad Enable +*/ #undef DDR_PHY_DX0GCR4_DXREFPEN_DEFVAL #undef DDR_PHY_DX0GCR4_DXREFPEN_SHIFT #undef DDR_PHY_DX0GCR4_DXREFPEN_MASK -#define DDR_PHY_DX0GCR4_DXREFPEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX0GCR4_DXREFPEN_SHIFT 28 -#define DDR_PHY_DX0GCR4_DXREFPEN_MASK 0x10000000U +#define DDR_PHY_DX0GCR4_DXREFPEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX0GCR4_DXREFPEN_SHIFT 28 +#define DDR_PHY_DX0GCR4_DXREFPEN_MASK 0x10000000U -/*Byte Lane Internal VREF Enable*/ +/* +* Byte Lane Internal VREF Enable +*/ #undef DDR_PHY_DX0GCR4_DXREFEEN_DEFVAL #undef DDR_PHY_DX0GCR4_DXREFEEN_SHIFT #undef DDR_PHY_DX0GCR4_DXREFEEN_MASK -#define DDR_PHY_DX0GCR4_DXREFEEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX0GCR4_DXREFEEN_SHIFT 26 -#define DDR_PHY_DX0GCR4_DXREFEEN_MASK 0x0C000000U +#define DDR_PHY_DX0GCR4_DXREFEEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX0GCR4_DXREFEEN_SHIFT 26 +#define DDR_PHY_DX0GCR4_DXREFEEN_MASK 0x0C000000U -/*Byte Lane Single-End VREF Enable*/ +/* +* Byte Lane Single-End VREF Enable +*/ #undef DDR_PHY_DX0GCR4_DXREFSEN_DEFVAL #undef DDR_PHY_DX0GCR4_DXREFSEN_SHIFT #undef DDR_PHY_DX0GCR4_DXREFSEN_MASK -#define DDR_PHY_DX0GCR4_DXREFSEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX0GCR4_DXREFSEN_SHIFT 25 -#define DDR_PHY_DX0GCR4_DXREFSEN_MASK 0x02000000U +#define DDR_PHY_DX0GCR4_DXREFSEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX0GCR4_DXREFSEN_SHIFT 25 +#define DDR_PHY_DX0GCR4_DXREFSEN_MASK 0x02000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX0GCR4_RESERVED_24_DEFVAL #undef DDR_PHY_DX0GCR4_RESERVED_24_SHIFT #undef DDR_PHY_DX0GCR4_RESERVED_24_MASK -#define DDR_PHY_DX0GCR4_RESERVED_24_DEFVAL 0x0E00003C -#define DDR_PHY_DX0GCR4_RESERVED_24_SHIFT 24 -#define DDR_PHY_DX0GCR4_RESERVED_24_MASK 0x01000000U +#define DDR_PHY_DX0GCR4_RESERVED_24_DEFVAL 0x0E00003C +#define DDR_PHY_DX0GCR4_RESERVED_24_SHIFT 24 +#define DDR_PHY_DX0GCR4_RESERVED_24_MASK 0x01000000U -/*External VREF generator REFSEL range select*/ +/* +* External VREF generator REFSEL range select +*/ #undef DDR_PHY_DX0GCR4_DXREFESELRANGE_DEFVAL #undef DDR_PHY_DX0GCR4_DXREFESELRANGE_SHIFT #undef DDR_PHY_DX0GCR4_DXREFESELRANGE_MASK -#define DDR_PHY_DX0GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C -#define DDR_PHY_DX0GCR4_DXREFESELRANGE_SHIFT 23 -#define DDR_PHY_DX0GCR4_DXREFESELRANGE_MASK 0x00800000U +#define DDR_PHY_DX0GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX0GCR4_DXREFESELRANGE_SHIFT 23 +#define DDR_PHY_DX0GCR4_DXREFESELRANGE_MASK 0x00800000U -/*Byte Lane External VREF Select*/ +/* +* Byte Lane External VREF Select +*/ #undef DDR_PHY_DX0GCR4_DXREFESEL_DEFVAL #undef DDR_PHY_DX0GCR4_DXREFESEL_SHIFT #undef DDR_PHY_DX0GCR4_DXREFESEL_MASK -#define DDR_PHY_DX0GCR4_DXREFESEL_DEFVAL 0x0E00003C -#define DDR_PHY_DX0GCR4_DXREFESEL_SHIFT 16 -#define DDR_PHY_DX0GCR4_DXREFESEL_MASK 0x007F0000U +#define DDR_PHY_DX0GCR4_DXREFESEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX0GCR4_DXREFESEL_SHIFT 16 +#define DDR_PHY_DX0GCR4_DXREFESEL_MASK 0x007F0000U -/*Single ended VREF generator REFSEL range select*/ +/* +* Single ended VREF generator REFSEL range select +*/ #undef DDR_PHY_DX0GCR4_DXREFSSELRANGE_DEFVAL #undef DDR_PHY_DX0GCR4_DXREFSSELRANGE_SHIFT #undef DDR_PHY_DX0GCR4_DXREFSSELRANGE_MASK -#define DDR_PHY_DX0GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C -#define DDR_PHY_DX0GCR4_DXREFSSELRANGE_SHIFT 15 -#define DDR_PHY_DX0GCR4_DXREFSSELRANGE_MASK 0x00008000U +#define DDR_PHY_DX0GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX0GCR4_DXREFSSELRANGE_SHIFT 15 +#define DDR_PHY_DX0GCR4_DXREFSSELRANGE_MASK 0x00008000U -/*Byte Lane Single-End VREF Select*/ +/* +* Byte Lane Single-End VREF Select +*/ #undef DDR_PHY_DX0GCR4_DXREFSSEL_DEFVAL #undef DDR_PHY_DX0GCR4_DXREFSSEL_SHIFT #undef DDR_PHY_DX0GCR4_DXREFSSEL_MASK -#define DDR_PHY_DX0GCR4_DXREFSSEL_DEFVAL 0x0E00003C -#define DDR_PHY_DX0GCR4_DXREFSSEL_SHIFT 8 -#define DDR_PHY_DX0GCR4_DXREFSSEL_MASK 0x00007F00U +#define DDR_PHY_DX0GCR4_DXREFSSEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX0GCR4_DXREFSSEL_SHIFT 8 +#define DDR_PHY_DX0GCR4_DXREFSSEL_MASK 0x00007F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX0GCR4_RESERVED_7_6_DEFVAL #undef DDR_PHY_DX0GCR4_RESERVED_7_6_SHIFT #undef DDR_PHY_DX0GCR4_RESERVED_7_6_MASK -#define DDR_PHY_DX0GCR4_RESERVED_7_6_DEFVAL 0x0E00003C -#define DDR_PHY_DX0GCR4_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_DX0GCR4_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_DX0GCR4_RESERVED_7_6_DEFVAL 0x0E00003C +#define DDR_PHY_DX0GCR4_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX0GCR4_RESERVED_7_6_MASK 0x000000C0U -/*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/ +/* +* VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. +*/ #undef DDR_PHY_DX0GCR4_DXREFIEN_DEFVAL #undef DDR_PHY_DX0GCR4_DXREFIEN_SHIFT #undef DDR_PHY_DX0GCR4_DXREFIEN_MASK -#define DDR_PHY_DX0GCR4_DXREFIEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX0GCR4_DXREFIEN_SHIFT 2 -#define DDR_PHY_DX0GCR4_DXREFIEN_MASK 0x0000003CU +#define DDR_PHY_DX0GCR4_DXREFIEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX0GCR4_DXREFIEN_SHIFT 2 +#define DDR_PHY_DX0GCR4_DXREFIEN_MASK 0x0000003CU -/*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/ +/* +* VRMON control for DQ IO (Single Ended) buffers of a byte lane. +*/ #undef DDR_PHY_DX0GCR4_DXREFIMON_DEFVAL #undef DDR_PHY_DX0GCR4_DXREFIMON_SHIFT #undef DDR_PHY_DX0GCR4_DXREFIMON_MASK -#define DDR_PHY_DX0GCR4_DXREFIMON_DEFVAL 0x0E00003C -#define DDR_PHY_DX0GCR4_DXREFIMON_SHIFT 0 -#define DDR_PHY_DX0GCR4_DXREFIMON_MASK 0x00000003U +#define DDR_PHY_DX0GCR4_DXREFIMON_DEFVAL 0x0E00003C +#define DDR_PHY_DX0GCR4_DXREFIMON_SHIFT 0 +#define DDR_PHY_DX0GCR4_DXREFIMON_MASK 0x00000003U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX0GCR5_RESERVED_31_DEFVAL #undef DDR_PHY_DX0GCR5_RESERVED_31_SHIFT #undef DDR_PHY_DX0GCR5_RESERVED_31_MASK -#define DDR_PHY_DX0GCR5_RESERVED_31_DEFVAL 0x09090909 -#define DDR_PHY_DX0GCR5_RESERVED_31_SHIFT 31 -#define DDR_PHY_DX0GCR5_RESERVED_31_MASK 0x80000000U +#define DDR_PHY_DX0GCR5_RESERVED_31_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR5_RESERVED_31_SHIFT 31 +#define DDR_PHY_DX0GCR5_RESERVED_31_MASK 0x80000000U -/*Byte Lane internal VREF Select for Rank 3*/ +/* +* Byte Lane internal VREF Select for Rank 3 +*/ #undef DDR_PHY_DX0GCR5_DXREFISELR3_DEFVAL #undef DDR_PHY_DX0GCR5_DXREFISELR3_SHIFT #undef DDR_PHY_DX0GCR5_DXREFISELR3_MASK -#define DDR_PHY_DX0GCR5_DXREFISELR3_DEFVAL 0x09090909 -#define DDR_PHY_DX0GCR5_DXREFISELR3_SHIFT 24 -#define DDR_PHY_DX0GCR5_DXREFISELR3_MASK 0x7F000000U +#define DDR_PHY_DX0GCR5_DXREFISELR3_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR5_DXREFISELR3_SHIFT 24 +#define DDR_PHY_DX0GCR5_DXREFISELR3_MASK 0x7F000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX0GCR5_RESERVED_23_DEFVAL #undef DDR_PHY_DX0GCR5_RESERVED_23_SHIFT #undef DDR_PHY_DX0GCR5_RESERVED_23_MASK -#define DDR_PHY_DX0GCR5_RESERVED_23_DEFVAL 0x09090909 -#define DDR_PHY_DX0GCR5_RESERVED_23_SHIFT 23 -#define DDR_PHY_DX0GCR5_RESERVED_23_MASK 0x00800000U +#define DDR_PHY_DX0GCR5_RESERVED_23_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR5_RESERVED_23_SHIFT 23 +#define DDR_PHY_DX0GCR5_RESERVED_23_MASK 0x00800000U -/*Byte Lane internal VREF Select for Rank 2*/ +/* +* Byte Lane internal VREF Select for Rank 2 +*/ #undef DDR_PHY_DX0GCR5_DXREFISELR2_DEFVAL #undef DDR_PHY_DX0GCR5_DXREFISELR2_SHIFT #undef DDR_PHY_DX0GCR5_DXREFISELR2_MASK -#define DDR_PHY_DX0GCR5_DXREFISELR2_DEFVAL 0x09090909 -#define DDR_PHY_DX0GCR5_DXREFISELR2_SHIFT 16 -#define DDR_PHY_DX0GCR5_DXREFISELR2_MASK 0x007F0000U +#define DDR_PHY_DX0GCR5_DXREFISELR2_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR5_DXREFISELR2_SHIFT 16 +#define DDR_PHY_DX0GCR5_DXREFISELR2_MASK 0x007F0000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX0GCR5_RESERVED_15_DEFVAL #undef DDR_PHY_DX0GCR5_RESERVED_15_SHIFT #undef DDR_PHY_DX0GCR5_RESERVED_15_MASK -#define DDR_PHY_DX0GCR5_RESERVED_15_DEFVAL 0x09090909 -#define DDR_PHY_DX0GCR5_RESERVED_15_SHIFT 15 -#define DDR_PHY_DX0GCR5_RESERVED_15_MASK 0x00008000U +#define DDR_PHY_DX0GCR5_RESERVED_15_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR5_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX0GCR5_RESERVED_15_MASK 0x00008000U -/*Byte Lane internal VREF Select for Rank 1*/ +/* +* Byte Lane internal VREF Select for Rank 1 +*/ #undef DDR_PHY_DX0GCR5_DXREFISELR1_DEFVAL #undef DDR_PHY_DX0GCR5_DXREFISELR1_SHIFT #undef DDR_PHY_DX0GCR5_DXREFISELR1_MASK -#define DDR_PHY_DX0GCR5_DXREFISELR1_DEFVAL 0x09090909 -#define DDR_PHY_DX0GCR5_DXREFISELR1_SHIFT 8 -#define DDR_PHY_DX0GCR5_DXREFISELR1_MASK 0x00007F00U +#define DDR_PHY_DX0GCR5_DXREFISELR1_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR5_DXREFISELR1_SHIFT 8 +#define DDR_PHY_DX0GCR5_DXREFISELR1_MASK 0x00007F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX0GCR5_RESERVED_7_DEFVAL #undef DDR_PHY_DX0GCR5_RESERVED_7_SHIFT #undef DDR_PHY_DX0GCR5_RESERVED_7_MASK -#define DDR_PHY_DX0GCR5_RESERVED_7_DEFVAL 0x09090909 -#define DDR_PHY_DX0GCR5_RESERVED_7_SHIFT 7 -#define DDR_PHY_DX0GCR5_RESERVED_7_MASK 0x00000080U +#define DDR_PHY_DX0GCR5_RESERVED_7_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR5_RESERVED_7_SHIFT 7 +#define DDR_PHY_DX0GCR5_RESERVED_7_MASK 0x00000080U -/*Byte Lane internal VREF Select for Rank 0*/ +/* +* Byte Lane internal VREF Select for Rank 0 +*/ #undef DDR_PHY_DX0GCR5_DXREFISELR0_DEFVAL #undef DDR_PHY_DX0GCR5_DXREFISELR0_SHIFT #undef DDR_PHY_DX0GCR5_DXREFISELR0_MASK -#define DDR_PHY_DX0GCR5_DXREFISELR0_DEFVAL 0x09090909 -#define DDR_PHY_DX0GCR5_DXREFISELR0_SHIFT 0 -#define DDR_PHY_DX0GCR5_DXREFISELR0_MASK 0x0000007FU +#define DDR_PHY_DX0GCR5_DXREFISELR0_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR5_DXREFISELR0_SHIFT 0 +#define DDR_PHY_DX0GCR5_DXREFISELR0_MASK 0x0000007FU -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX0GCR6_RESERVED_31_30_DEFVAL #undef DDR_PHY_DX0GCR6_RESERVED_31_30_SHIFT #undef DDR_PHY_DX0GCR6_RESERVED_31_30_MASK -#define DDR_PHY_DX0GCR6_RESERVED_31_30_DEFVAL 0x09090909 -#define DDR_PHY_DX0GCR6_RESERVED_31_30_SHIFT 30 -#define DDR_PHY_DX0GCR6_RESERVED_31_30_MASK 0xC0000000U +#define DDR_PHY_DX0GCR6_RESERVED_31_30_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR6_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX0GCR6_RESERVED_31_30_MASK 0xC0000000U -/*DRAM DQ VREF Select for Rank3*/ +/* +* DRAM DQ VREF Select for Rank3 +*/ #undef DDR_PHY_DX0GCR6_DXDQVREFR3_DEFVAL #undef DDR_PHY_DX0GCR6_DXDQVREFR3_SHIFT #undef DDR_PHY_DX0GCR6_DXDQVREFR3_MASK -#define DDR_PHY_DX0GCR6_DXDQVREFR3_DEFVAL 0x09090909 -#define DDR_PHY_DX0GCR6_DXDQVREFR3_SHIFT 24 -#define DDR_PHY_DX0GCR6_DXDQVREFR3_MASK 0x3F000000U +#define DDR_PHY_DX0GCR6_DXDQVREFR3_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR6_DXDQVREFR3_SHIFT 24 +#define DDR_PHY_DX0GCR6_DXDQVREFR3_MASK 0x3F000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX0GCR6_RESERVED_23_22_DEFVAL #undef DDR_PHY_DX0GCR6_RESERVED_23_22_SHIFT #undef DDR_PHY_DX0GCR6_RESERVED_23_22_MASK -#define DDR_PHY_DX0GCR6_RESERVED_23_22_DEFVAL 0x09090909 -#define DDR_PHY_DX0GCR6_RESERVED_23_22_SHIFT 22 -#define DDR_PHY_DX0GCR6_RESERVED_23_22_MASK 0x00C00000U +#define DDR_PHY_DX0GCR6_RESERVED_23_22_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR6_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX0GCR6_RESERVED_23_22_MASK 0x00C00000U -/*DRAM DQ VREF Select for Rank2*/ +/* +* DRAM DQ VREF Select for Rank2 +*/ #undef DDR_PHY_DX0GCR6_DXDQVREFR2_DEFVAL #undef DDR_PHY_DX0GCR6_DXDQVREFR2_SHIFT #undef DDR_PHY_DX0GCR6_DXDQVREFR2_MASK -#define DDR_PHY_DX0GCR6_DXDQVREFR2_DEFVAL 0x09090909 -#define DDR_PHY_DX0GCR6_DXDQVREFR2_SHIFT 16 -#define DDR_PHY_DX0GCR6_DXDQVREFR2_MASK 0x003F0000U +#define DDR_PHY_DX0GCR6_DXDQVREFR2_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR6_DXDQVREFR2_SHIFT 16 +#define DDR_PHY_DX0GCR6_DXDQVREFR2_MASK 0x003F0000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX0GCR6_RESERVED_15_14_DEFVAL #undef DDR_PHY_DX0GCR6_RESERVED_15_14_SHIFT #undef DDR_PHY_DX0GCR6_RESERVED_15_14_MASK -#define DDR_PHY_DX0GCR6_RESERVED_15_14_DEFVAL 0x09090909 -#define DDR_PHY_DX0GCR6_RESERVED_15_14_SHIFT 14 -#define DDR_PHY_DX0GCR6_RESERVED_15_14_MASK 0x0000C000U +#define DDR_PHY_DX0GCR6_RESERVED_15_14_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR6_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_DX0GCR6_RESERVED_15_14_MASK 0x0000C000U -/*DRAM DQ VREF Select for Rank1*/ +/* +* DRAM DQ VREF Select for Rank1 +*/ #undef DDR_PHY_DX0GCR6_DXDQVREFR1_DEFVAL #undef DDR_PHY_DX0GCR6_DXDQVREFR1_SHIFT #undef DDR_PHY_DX0GCR6_DXDQVREFR1_MASK -#define DDR_PHY_DX0GCR6_DXDQVREFR1_DEFVAL 0x09090909 -#define DDR_PHY_DX0GCR6_DXDQVREFR1_SHIFT 8 -#define DDR_PHY_DX0GCR6_DXDQVREFR1_MASK 0x00003F00U +#define DDR_PHY_DX0GCR6_DXDQVREFR1_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR6_DXDQVREFR1_SHIFT 8 +#define DDR_PHY_DX0GCR6_DXDQVREFR1_MASK 0x00003F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX0GCR6_RESERVED_7_6_DEFVAL #undef DDR_PHY_DX0GCR6_RESERVED_7_6_SHIFT #undef DDR_PHY_DX0GCR6_RESERVED_7_6_MASK -#define DDR_PHY_DX0GCR6_RESERVED_7_6_DEFVAL 0x09090909 -#define DDR_PHY_DX0GCR6_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_DX0GCR6_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_DX0GCR6_RESERVED_7_6_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR6_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX0GCR6_RESERVED_7_6_MASK 0x000000C0U -/*DRAM DQ VREF Select for Rank0*/ +/* +* DRAM DQ VREF Select for Rank0 +*/ #undef DDR_PHY_DX0GCR6_DXDQVREFR0_DEFVAL #undef DDR_PHY_DX0GCR6_DXDQVREFR0_SHIFT #undef DDR_PHY_DX0GCR6_DXDQVREFR0_MASK -#define DDR_PHY_DX0GCR6_DXDQVREFR0_DEFVAL 0x09090909 -#define DDR_PHY_DX0GCR6_DXDQVREFR0_SHIFT 0 -#define DDR_PHY_DX0GCR6_DXDQVREFR0_MASK 0x0000003FU +#define DDR_PHY_DX0GCR6_DXDQVREFR0_DEFVAL 0x09090909 +#define DDR_PHY_DX0GCR6_DXDQVREFR0_SHIFT 0 +#define DDR_PHY_DX0GCR6_DXDQVREFR0_MASK 0x0000003FU -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX0LCDLR2_RESERVED_31_25_DEFVAL -#undef DDR_PHY_DX0LCDLR2_RESERVED_31_25_SHIFT -#undef DDR_PHY_DX0LCDLR2_RESERVED_31_25_MASK -#define DDR_PHY_DX0LCDLR2_RESERVED_31_25_DEFVAL 0x00000000 -#define DDR_PHY_DX0LCDLR2_RESERVED_31_25_SHIFT 25 -#define DDR_PHY_DX0LCDLR2_RESERVED_31_25_MASK 0xFE000000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX0LCDLR2_RESERVED_24_16_DEFVAL -#undef DDR_PHY_DX0LCDLR2_RESERVED_24_16_SHIFT -#undef DDR_PHY_DX0LCDLR2_RESERVED_24_16_MASK -#define DDR_PHY_DX0LCDLR2_RESERVED_24_16_DEFVAL 0x00000000 -#define DDR_PHY_DX0LCDLR2_RESERVED_24_16_SHIFT 16 -#define DDR_PHY_DX0LCDLR2_RESERVED_24_16_MASK 0x01FF0000U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX0LCDLR2_RESERVED_15_9_DEFVAL -#undef DDR_PHY_DX0LCDLR2_RESERVED_15_9_SHIFT -#undef DDR_PHY_DX0LCDLR2_RESERVED_15_9_MASK -#define DDR_PHY_DX0LCDLR2_RESERVED_15_9_DEFVAL 0x00000000 -#define DDR_PHY_DX0LCDLR2_RESERVED_15_9_SHIFT 9 -#define DDR_PHY_DX0LCDLR2_RESERVED_15_9_MASK 0x0000FE00U - -/*Read DQS Gating Delay*/ -#undef DDR_PHY_DX0LCDLR2_DQSGD_DEFVAL -#undef DDR_PHY_DX0LCDLR2_DQSGD_SHIFT -#undef DDR_PHY_DX0LCDLR2_DQSGD_MASK -#define DDR_PHY_DX0LCDLR2_DQSGD_DEFVAL 0x00000000 -#define DDR_PHY_DX0LCDLR2_DQSGD_SHIFT 0 -#define DDR_PHY_DX0LCDLR2_DQSGD_MASK 0x000001FFU - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX0GTR0_RESERVED_31_24_DEFVAL -#undef DDR_PHY_DX0GTR0_RESERVED_31_24_SHIFT -#undef DDR_PHY_DX0GTR0_RESERVED_31_24_MASK -#define DDR_PHY_DX0GTR0_RESERVED_31_24_DEFVAL 0x00020000 -#define DDR_PHY_DX0GTR0_RESERVED_31_24_SHIFT 27 -#define DDR_PHY_DX0GTR0_RESERVED_31_24_MASK 0xF8000000U - -/*DQ Write Path Latency Pipeline*/ -#undef DDR_PHY_DX0GTR0_WDQSL_DEFVAL -#undef DDR_PHY_DX0GTR0_WDQSL_SHIFT -#undef DDR_PHY_DX0GTR0_WDQSL_MASK -#define DDR_PHY_DX0GTR0_WDQSL_DEFVAL 0x00020000 -#define DDR_PHY_DX0GTR0_WDQSL_SHIFT 24 -#define DDR_PHY_DX0GTR0_WDQSL_MASK 0x07000000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX0GTR0_RESERVED_23_20_DEFVAL -#undef DDR_PHY_DX0GTR0_RESERVED_23_20_SHIFT -#undef DDR_PHY_DX0GTR0_RESERVED_23_20_MASK -#define DDR_PHY_DX0GTR0_RESERVED_23_20_DEFVAL 0x00020000 -#define DDR_PHY_DX0GTR0_RESERVED_23_20_SHIFT 20 -#define DDR_PHY_DX0GTR0_RESERVED_23_20_MASK 0x00F00000U - -/*Write Leveling System Latency*/ -#undef DDR_PHY_DX0GTR0_WLSL_DEFVAL -#undef DDR_PHY_DX0GTR0_WLSL_SHIFT -#undef DDR_PHY_DX0GTR0_WLSL_MASK -#define DDR_PHY_DX0GTR0_WLSL_DEFVAL 0x00020000 -#define DDR_PHY_DX0GTR0_WLSL_SHIFT 16 -#define DDR_PHY_DX0GTR0_WLSL_MASK 0x000F0000U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX0GTR0_RESERVED_15_13_DEFVAL -#undef DDR_PHY_DX0GTR0_RESERVED_15_13_SHIFT -#undef DDR_PHY_DX0GTR0_RESERVED_15_13_MASK -#define DDR_PHY_DX0GTR0_RESERVED_15_13_DEFVAL 0x00020000 -#define DDR_PHY_DX0GTR0_RESERVED_15_13_SHIFT 13 -#define DDR_PHY_DX0GTR0_RESERVED_15_13_MASK 0x0000E000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX0GTR0_RESERVED_12_8_DEFVAL -#undef DDR_PHY_DX0GTR0_RESERVED_12_8_SHIFT -#undef DDR_PHY_DX0GTR0_RESERVED_12_8_MASK -#define DDR_PHY_DX0GTR0_RESERVED_12_8_DEFVAL 0x00020000 -#define DDR_PHY_DX0GTR0_RESERVED_12_8_SHIFT 8 -#define DDR_PHY_DX0GTR0_RESERVED_12_8_MASK 0x00001F00U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX0GTR0_RESERVED_7_5_DEFVAL -#undef DDR_PHY_DX0GTR0_RESERVED_7_5_SHIFT -#undef DDR_PHY_DX0GTR0_RESERVED_7_5_MASK -#define DDR_PHY_DX0GTR0_RESERVED_7_5_DEFVAL 0x00020000 -#define DDR_PHY_DX0GTR0_RESERVED_7_5_SHIFT 5 -#define DDR_PHY_DX0GTR0_RESERVED_7_5_MASK 0x000000E0U - -/*DQS Gating System Latency*/ -#undef DDR_PHY_DX0GTR0_DGSL_DEFVAL -#undef DDR_PHY_DX0GTR0_DGSL_SHIFT -#undef DDR_PHY_DX0GTR0_DGSL_MASK -#define DDR_PHY_DX0GTR0_DGSL_DEFVAL 0x00020000 -#define DDR_PHY_DX0GTR0_DGSL_SHIFT 0 -#define DDR_PHY_DX0GTR0_DGSL_MASK 0x0000001FU - -/*Calibration Bypass*/ +/* +* Calibration Bypass +*/ #undef DDR_PHY_DX1GCR0_CALBYP_DEFVAL #undef DDR_PHY_DX1GCR0_CALBYP_SHIFT #undef DDR_PHY_DX1GCR0_CALBYP_MASK -#define DDR_PHY_DX1GCR0_CALBYP_DEFVAL 0x40200204 -#define DDR_PHY_DX1GCR0_CALBYP_SHIFT 31 -#define DDR_PHY_DX1GCR0_CALBYP_MASK 0x80000000U +#define DDR_PHY_DX1GCR0_CALBYP_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_CALBYP_SHIFT 31 +#define DDR_PHY_DX1GCR0_CALBYP_MASK 0x80000000U -/*Master Delay Line Enable*/ +/* +* Master Delay Line Enable +*/ #undef DDR_PHY_DX1GCR0_MDLEN_DEFVAL #undef DDR_PHY_DX1GCR0_MDLEN_SHIFT #undef DDR_PHY_DX1GCR0_MDLEN_MASK -#define DDR_PHY_DX1GCR0_MDLEN_DEFVAL 0x40200204 -#define DDR_PHY_DX1GCR0_MDLEN_SHIFT 30 -#define DDR_PHY_DX1GCR0_MDLEN_MASK 0x40000000U +#define DDR_PHY_DX1GCR0_MDLEN_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_MDLEN_SHIFT 30 +#define DDR_PHY_DX1GCR0_MDLEN_MASK 0x40000000U -/*Configurable ODT(TE) Phase Shift*/ +/* +* Configurable ODT(TE) Phase Shift +*/ #undef DDR_PHY_DX1GCR0_CODTSHFT_DEFVAL #undef DDR_PHY_DX1GCR0_CODTSHFT_SHIFT #undef DDR_PHY_DX1GCR0_CODTSHFT_MASK -#define DDR_PHY_DX1GCR0_CODTSHFT_DEFVAL 0x40200204 -#define DDR_PHY_DX1GCR0_CODTSHFT_SHIFT 28 -#define DDR_PHY_DX1GCR0_CODTSHFT_MASK 0x30000000U +#define DDR_PHY_DX1GCR0_CODTSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_CODTSHFT_SHIFT 28 +#define DDR_PHY_DX1GCR0_CODTSHFT_MASK 0x30000000U -/*DQS Duty Cycle Correction*/ +/* +* DQS Duty Cycle Correction +*/ #undef DDR_PHY_DX1GCR0_DQSDCC_DEFVAL #undef DDR_PHY_DX1GCR0_DQSDCC_SHIFT #undef DDR_PHY_DX1GCR0_DQSDCC_MASK -#define DDR_PHY_DX1GCR0_DQSDCC_DEFVAL 0x40200204 -#define DDR_PHY_DX1GCR0_DQSDCC_SHIFT 24 -#define DDR_PHY_DX1GCR0_DQSDCC_MASK 0x0F000000U +#define DDR_PHY_DX1GCR0_DQSDCC_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_DQSDCC_SHIFT 24 +#define DDR_PHY_DX1GCR0_DQSDCC_MASK 0x0F000000U -/*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/ +/* +* Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY +*/ #undef DDR_PHY_DX1GCR0_RDDLY_DEFVAL #undef DDR_PHY_DX1GCR0_RDDLY_SHIFT #undef DDR_PHY_DX1GCR0_RDDLY_MASK -#define DDR_PHY_DX1GCR0_RDDLY_DEFVAL 0x40200204 -#define DDR_PHY_DX1GCR0_RDDLY_SHIFT 20 -#define DDR_PHY_DX1GCR0_RDDLY_MASK 0x00F00000U +#define DDR_PHY_DX1GCR0_RDDLY_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_RDDLY_SHIFT 20 +#define DDR_PHY_DX1GCR0_RDDLY_MASK 0x00F00000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX1GCR0_RESERVED_19_14_DEFVAL #undef DDR_PHY_DX1GCR0_RESERVED_19_14_SHIFT #undef DDR_PHY_DX1GCR0_RESERVED_19_14_MASK -#define DDR_PHY_DX1GCR0_RESERVED_19_14_DEFVAL 0x40200204 -#define DDR_PHY_DX1GCR0_RESERVED_19_14_SHIFT 14 -#define DDR_PHY_DX1GCR0_RESERVED_19_14_MASK 0x000FC000U +#define DDR_PHY_DX1GCR0_RESERVED_19_14_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_RESERVED_19_14_SHIFT 14 +#define DDR_PHY_DX1GCR0_RESERVED_19_14_MASK 0x000FC000U -/*DQSNSE Power Down Receiver*/ +/* +* DQSNSE Power Down Receiver +*/ #undef DDR_PHY_DX1GCR0_DQSNSEPDR_DEFVAL #undef DDR_PHY_DX1GCR0_DQSNSEPDR_SHIFT #undef DDR_PHY_DX1GCR0_DQSNSEPDR_MASK -#define DDR_PHY_DX1GCR0_DQSNSEPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX1GCR0_DQSNSEPDR_SHIFT 13 -#define DDR_PHY_DX1GCR0_DQSNSEPDR_MASK 0x00002000U +#define DDR_PHY_DX1GCR0_DQSNSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_DQSNSEPDR_SHIFT 13 +#define DDR_PHY_DX1GCR0_DQSNSEPDR_MASK 0x00002000U -/*DQSSE Power Down Receiver*/ +/* +* DQSSE Power Down Receiver +*/ #undef DDR_PHY_DX1GCR0_DQSSEPDR_DEFVAL #undef DDR_PHY_DX1GCR0_DQSSEPDR_SHIFT #undef DDR_PHY_DX1GCR0_DQSSEPDR_MASK -#define DDR_PHY_DX1GCR0_DQSSEPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX1GCR0_DQSSEPDR_SHIFT 12 -#define DDR_PHY_DX1GCR0_DQSSEPDR_MASK 0x00001000U +#define DDR_PHY_DX1GCR0_DQSSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_DQSSEPDR_SHIFT 12 +#define DDR_PHY_DX1GCR0_DQSSEPDR_MASK 0x00001000U -/*RTT On Additive Latency*/ +/* +* RTT On Additive Latency +*/ #undef DDR_PHY_DX1GCR0_RTTOAL_DEFVAL #undef DDR_PHY_DX1GCR0_RTTOAL_SHIFT #undef DDR_PHY_DX1GCR0_RTTOAL_MASK -#define DDR_PHY_DX1GCR0_RTTOAL_DEFVAL 0x40200204 -#define DDR_PHY_DX1GCR0_RTTOAL_SHIFT 11 -#define DDR_PHY_DX1GCR0_RTTOAL_MASK 0x00000800U +#define DDR_PHY_DX1GCR0_RTTOAL_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_RTTOAL_SHIFT 11 +#define DDR_PHY_DX1GCR0_RTTOAL_MASK 0x00000800U -/*RTT Output Hold*/ +/* +* RTT Output Hold +*/ #undef DDR_PHY_DX1GCR0_RTTOH_DEFVAL #undef DDR_PHY_DX1GCR0_RTTOH_SHIFT #undef DDR_PHY_DX1GCR0_RTTOH_MASK -#define DDR_PHY_DX1GCR0_RTTOH_DEFVAL 0x40200204 -#define DDR_PHY_DX1GCR0_RTTOH_SHIFT 9 -#define DDR_PHY_DX1GCR0_RTTOH_MASK 0x00000600U +#define DDR_PHY_DX1GCR0_RTTOH_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_RTTOH_SHIFT 9 +#define DDR_PHY_DX1GCR0_RTTOH_MASK 0x00000600U -/*Configurable PDR Phase Shift*/ +/* +* Configurable PDR Phase Shift +*/ #undef DDR_PHY_DX1GCR0_CPDRSHFT_DEFVAL #undef DDR_PHY_DX1GCR0_CPDRSHFT_SHIFT #undef DDR_PHY_DX1GCR0_CPDRSHFT_MASK -#define DDR_PHY_DX1GCR0_CPDRSHFT_DEFVAL 0x40200204 -#define DDR_PHY_DX1GCR0_CPDRSHFT_SHIFT 7 -#define DDR_PHY_DX1GCR0_CPDRSHFT_MASK 0x00000180U +#define DDR_PHY_DX1GCR0_CPDRSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_CPDRSHFT_SHIFT 7 +#define DDR_PHY_DX1GCR0_CPDRSHFT_MASK 0x00000180U -/*DQSR Power Down*/ +/* +* DQSR Power Down +*/ #undef DDR_PHY_DX1GCR0_DQSRPD_DEFVAL #undef DDR_PHY_DX1GCR0_DQSRPD_SHIFT #undef DDR_PHY_DX1GCR0_DQSRPD_MASK -#define DDR_PHY_DX1GCR0_DQSRPD_DEFVAL 0x40200204 -#define DDR_PHY_DX1GCR0_DQSRPD_SHIFT 6 -#define DDR_PHY_DX1GCR0_DQSRPD_MASK 0x00000040U +#define DDR_PHY_DX1GCR0_DQSRPD_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_DQSRPD_SHIFT 6 +#define DDR_PHY_DX1GCR0_DQSRPD_MASK 0x00000040U -/*DQSG Power Down Receiver*/ +/* +* DQSG Power Down Receiver +*/ #undef DDR_PHY_DX1GCR0_DQSGPDR_DEFVAL #undef DDR_PHY_DX1GCR0_DQSGPDR_SHIFT #undef DDR_PHY_DX1GCR0_DQSGPDR_MASK -#define DDR_PHY_DX1GCR0_DQSGPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX1GCR0_DQSGPDR_SHIFT 5 -#define DDR_PHY_DX1GCR0_DQSGPDR_MASK 0x00000020U +#define DDR_PHY_DX1GCR0_DQSGPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_DQSGPDR_SHIFT 5 +#define DDR_PHY_DX1GCR0_DQSGPDR_MASK 0x00000020U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX1GCR0_RESERVED_4_DEFVAL #undef DDR_PHY_DX1GCR0_RESERVED_4_SHIFT #undef DDR_PHY_DX1GCR0_RESERVED_4_MASK -#define DDR_PHY_DX1GCR0_RESERVED_4_DEFVAL 0x40200204 -#define DDR_PHY_DX1GCR0_RESERVED_4_SHIFT 4 -#define DDR_PHY_DX1GCR0_RESERVED_4_MASK 0x00000010U +#define DDR_PHY_DX1GCR0_RESERVED_4_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_RESERVED_4_SHIFT 4 +#define DDR_PHY_DX1GCR0_RESERVED_4_MASK 0x00000010U -/*DQSG On-Die Termination*/ +/* +* DQSG On-Die Termination +*/ #undef DDR_PHY_DX1GCR0_DQSGODT_DEFVAL #undef DDR_PHY_DX1GCR0_DQSGODT_SHIFT #undef DDR_PHY_DX1GCR0_DQSGODT_MASK -#define DDR_PHY_DX1GCR0_DQSGODT_DEFVAL 0x40200204 -#define DDR_PHY_DX1GCR0_DQSGODT_SHIFT 3 -#define DDR_PHY_DX1GCR0_DQSGODT_MASK 0x00000008U +#define DDR_PHY_DX1GCR0_DQSGODT_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_DQSGODT_SHIFT 3 +#define DDR_PHY_DX1GCR0_DQSGODT_MASK 0x00000008U -/*DQSG Output Enable*/ +/* +* DQSG Output Enable +*/ #undef DDR_PHY_DX1GCR0_DQSGOE_DEFVAL #undef DDR_PHY_DX1GCR0_DQSGOE_SHIFT #undef DDR_PHY_DX1GCR0_DQSGOE_MASK -#define DDR_PHY_DX1GCR0_DQSGOE_DEFVAL 0x40200204 -#define DDR_PHY_DX1GCR0_DQSGOE_SHIFT 2 -#define DDR_PHY_DX1GCR0_DQSGOE_MASK 0x00000004U +#define DDR_PHY_DX1GCR0_DQSGOE_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_DQSGOE_SHIFT 2 +#define DDR_PHY_DX1GCR0_DQSGOE_MASK 0x00000004U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX1GCR0_RESERVED_1_0_DEFVAL #undef DDR_PHY_DX1GCR0_RESERVED_1_0_SHIFT #undef DDR_PHY_DX1GCR0_RESERVED_1_0_MASK -#define DDR_PHY_DX1GCR0_RESERVED_1_0_DEFVAL 0x40200204 -#define DDR_PHY_DX1GCR0_RESERVED_1_0_SHIFT 0 -#define DDR_PHY_DX1GCR0_RESERVED_1_0_MASK 0x00000003U +#define DDR_PHY_DX1GCR0_RESERVED_1_0_DEFVAL 0x40200204 +#define DDR_PHY_DX1GCR0_RESERVED_1_0_SHIFT 0 +#define DDR_PHY_DX1GCR0_RESERVED_1_0_MASK 0x00000003U -/*Byte lane VREF IOM (Used only by D4MU IOs)*/ +/* +* Byte lane VREF IOM (Used only by D4MU IOs) +*/ #undef DDR_PHY_DX1GCR4_RESERVED_31_29_DEFVAL #undef DDR_PHY_DX1GCR4_RESERVED_31_29_SHIFT #undef DDR_PHY_DX1GCR4_RESERVED_31_29_MASK -#define DDR_PHY_DX1GCR4_RESERVED_31_29_DEFVAL 0x0E00003C -#define DDR_PHY_DX1GCR4_RESERVED_31_29_SHIFT 29 -#define DDR_PHY_DX1GCR4_RESERVED_31_29_MASK 0xE0000000U +#define DDR_PHY_DX1GCR4_RESERVED_31_29_DEFVAL 0x0E00003C +#define DDR_PHY_DX1GCR4_RESERVED_31_29_SHIFT 29 +#define DDR_PHY_DX1GCR4_RESERVED_31_29_MASK 0xE0000000U -/*Byte Lane VREF Pad Enable*/ +/* +* Byte Lane VREF Pad Enable +*/ #undef DDR_PHY_DX1GCR4_DXREFPEN_DEFVAL #undef DDR_PHY_DX1GCR4_DXREFPEN_SHIFT #undef DDR_PHY_DX1GCR4_DXREFPEN_MASK -#define DDR_PHY_DX1GCR4_DXREFPEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX1GCR4_DXREFPEN_SHIFT 28 -#define DDR_PHY_DX1GCR4_DXREFPEN_MASK 0x10000000U +#define DDR_PHY_DX1GCR4_DXREFPEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX1GCR4_DXREFPEN_SHIFT 28 +#define DDR_PHY_DX1GCR4_DXREFPEN_MASK 0x10000000U -/*Byte Lane Internal VREF Enable*/ +/* +* Byte Lane Internal VREF Enable +*/ #undef DDR_PHY_DX1GCR4_DXREFEEN_DEFVAL #undef DDR_PHY_DX1GCR4_DXREFEEN_SHIFT #undef DDR_PHY_DX1GCR4_DXREFEEN_MASK -#define DDR_PHY_DX1GCR4_DXREFEEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX1GCR4_DXREFEEN_SHIFT 26 -#define DDR_PHY_DX1GCR4_DXREFEEN_MASK 0x0C000000U +#define DDR_PHY_DX1GCR4_DXREFEEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX1GCR4_DXREFEEN_SHIFT 26 +#define DDR_PHY_DX1GCR4_DXREFEEN_MASK 0x0C000000U -/*Byte Lane Single-End VREF Enable*/ +/* +* Byte Lane Single-End VREF Enable +*/ #undef DDR_PHY_DX1GCR4_DXREFSEN_DEFVAL #undef DDR_PHY_DX1GCR4_DXREFSEN_SHIFT #undef DDR_PHY_DX1GCR4_DXREFSEN_MASK -#define DDR_PHY_DX1GCR4_DXREFSEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX1GCR4_DXREFSEN_SHIFT 25 -#define DDR_PHY_DX1GCR4_DXREFSEN_MASK 0x02000000U +#define DDR_PHY_DX1GCR4_DXREFSEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX1GCR4_DXREFSEN_SHIFT 25 +#define DDR_PHY_DX1GCR4_DXREFSEN_MASK 0x02000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX1GCR4_RESERVED_24_DEFVAL #undef DDR_PHY_DX1GCR4_RESERVED_24_SHIFT #undef DDR_PHY_DX1GCR4_RESERVED_24_MASK -#define DDR_PHY_DX1GCR4_RESERVED_24_DEFVAL 0x0E00003C -#define DDR_PHY_DX1GCR4_RESERVED_24_SHIFT 24 -#define DDR_PHY_DX1GCR4_RESERVED_24_MASK 0x01000000U +#define DDR_PHY_DX1GCR4_RESERVED_24_DEFVAL 0x0E00003C +#define DDR_PHY_DX1GCR4_RESERVED_24_SHIFT 24 +#define DDR_PHY_DX1GCR4_RESERVED_24_MASK 0x01000000U -/*External VREF generator REFSEL range select*/ +/* +* External VREF generator REFSEL range select +*/ #undef DDR_PHY_DX1GCR4_DXREFESELRANGE_DEFVAL #undef DDR_PHY_DX1GCR4_DXREFESELRANGE_SHIFT #undef DDR_PHY_DX1GCR4_DXREFESELRANGE_MASK -#define DDR_PHY_DX1GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C -#define DDR_PHY_DX1GCR4_DXREFESELRANGE_SHIFT 23 -#define DDR_PHY_DX1GCR4_DXREFESELRANGE_MASK 0x00800000U +#define DDR_PHY_DX1GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX1GCR4_DXREFESELRANGE_SHIFT 23 +#define DDR_PHY_DX1GCR4_DXREFESELRANGE_MASK 0x00800000U -/*Byte Lane External VREF Select*/ +/* +* Byte Lane External VREF Select +*/ #undef DDR_PHY_DX1GCR4_DXREFESEL_DEFVAL #undef DDR_PHY_DX1GCR4_DXREFESEL_SHIFT #undef DDR_PHY_DX1GCR4_DXREFESEL_MASK -#define DDR_PHY_DX1GCR4_DXREFESEL_DEFVAL 0x0E00003C -#define DDR_PHY_DX1GCR4_DXREFESEL_SHIFT 16 -#define DDR_PHY_DX1GCR4_DXREFESEL_MASK 0x007F0000U +#define DDR_PHY_DX1GCR4_DXREFESEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX1GCR4_DXREFESEL_SHIFT 16 +#define DDR_PHY_DX1GCR4_DXREFESEL_MASK 0x007F0000U -/*Single ended VREF generator REFSEL range select*/ +/* +* Single ended VREF generator REFSEL range select +*/ #undef DDR_PHY_DX1GCR4_DXREFSSELRANGE_DEFVAL #undef DDR_PHY_DX1GCR4_DXREFSSELRANGE_SHIFT #undef DDR_PHY_DX1GCR4_DXREFSSELRANGE_MASK -#define DDR_PHY_DX1GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C -#define DDR_PHY_DX1GCR4_DXREFSSELRANGE_SHIFT 15 -#define DDR_PHY_DX1GCR4_DXREFSSELRANGE_MASK 0x00008000U +#define DDR_PHY_DX1GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX1GCR4_DXREFSSELRANGE_SHIFT 15 +#define DDR_PHY_DX1GCR4_DXREFSSELRANGE_MASK 0x00008000U -/*Byte Lane Single-End VREF Select*/ +/* +* Byte Lane Single-End VREF Select +*/ #undef DDR_PHY_DX1GCR4_DXREFSSEL_DEFVAL #undef DDR_PHY_DX1GCR4_DXREFSSEL_SHIFT #undef DDR_PHY_DX1GCR4_DXREFSSEL_MASK -#define DDR_PHY_DX1GCR4_DXREFSSEL_DEFVAL 0x0E00003C -#define DDR_PHY_DX1GCR4_DXREFSSEL_SHIFT 8 -#define DDR_PHY_DX1GCR4_DXREFSSEL_MASK 0x00007F00U +#define DDR_PHY_DX1GCR4_DXREFSSEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX1GCR4_DXREFSSEL_SHIFT 8 +#define DDR_PHY_DX1GCR4_DXREFSSEL_MASK 0x00007F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX1GCR4_RESERVED_7_6_DEFVAL #undef DDR_PHY_DX1GCR4_RESERVED_7_6_SHIFT #undef DDR_PHY_DX1GCR4_RESERVED_7_6_MASK -#define DDR_PHY_DX1GCR4_RESERVED_7_6_DEFVAL 0x0E00003C -#define DDR_PHY_DX1GCR4_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_DX1GCR4_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_DX1GCR4_RESERVED_7_6_DEFVAL 0x0E00003C +#define DDR_PHY_DX1GCR4_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX1GCR4_RESERVED_7_6_MASK 0x000000C0U -/*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/ +/* +* VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. +*/ #undef DDR_PHY_DX1GCR4_DXREFIEN_DEFVAL #undef DDR_PHY_DX1GCR4_DXREFIEN_SHIFT #undef DDR_PHY_DX1GCR4_DXREFIEN_MASK -#define DDR_PHY_DX1GCR4_DXREFIEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX1GCR4_DXREFIEN_SHIFT 2 -#define DDR_PHY_DX1GCR4_DXREFIEN_MASK 0x0000003CU +#define DDR_PHY_DX1GCR4_DXREFIEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX1GCR4_DXREFIEN_SHIFT 2 +#define DDR_PHY_DX1GCR4_DXREFIEN_MASK 0x0000003CU -/*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/ +/* +* VRMON control for DQ IO (Single Ended) buffers of a byte lane. +*/ #undef DDR_PHY_DX1GCR4_DXREFIMON_DEFVAL #undef DDR_PHY_DX1GCR4_DXREFIMON_SHIFT #undef DDR_PHY_DX1GCR4_DXREFIMON_MASK -#define DDR_PHY_DX1GCR4_DXREFIMON_DEFVAL 0x0E00003C -#define DDR_PHY_DX1GCR4_DXREFIMON_SHIFT 0 -#define DDR_PHY_DX1GCR4_DXREFIMON_MASK 0x00000003U +#define DDR_PHY_DX1GCR4_DXREFIMON_DEFVAL 0x0E00003C +#define DDR_PHY_DX1GCR4_DXREFIMON_SHIFT 0 +#define DDR_PHY_DX1GCR4_DXREFIMON_MASK 0x00000003U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX1GCR5_RESERVED_31_DEFVAL #undef DDR_PHY_DX1GCR5_RESERVED_31_SHIFT #undef DDR_PHY_DX1GCR5_RESERVED_31_MASK -#define DDR_PHY_DX1GCR5_RESERVED_31_DEFVAL 0x09090909 -#define DDR_PHY_DX1GCR5_RESERVED_31_SHIFT 31 -#define DDR_PHY_DX1GCR5_RESERVED_31_MASK 0x80000000U +#define DDR_PHY_DX1GCR5_RESERVED_31_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR5_RESERVED_31_SHIFT 31 +#define DDR_PHY_DX1GCR5_RESERVED_31_MASK 0x80000000U -/*Byte Lane internal VREF Select for Rank 3*/ +/* +* Byte Lane internal VREF Select for Rank 3 +*/ #undef DDR_PHY_DX1GCR5_DXREFISELR3_DEFVAL #undef DDR_PHY_DX1GCR5_DXREFISELR3_SHIFT #undef DDR_PHY_DX1GCR5_DXREFISELR3_MASK -#define DDR_PHY_DX1GCR5_DXREFISELR3_DEFVAL 0x09090909 -#define DDR_PHY_DX1GCR5_DXREFISELR3_SHIFT 24 -#define DDR_PHY_DX1GCR5_DXREFISELR3_MASK 0x7F000000U +#define DDR_PHY_DX1GCR5_DXREFISELR3_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR5_DXREFISELR3_SHIFT 24 +#define DDR_PHY_DX1GCR5_DXREFISELR3_MASK 0x7F000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX1GCR5_RESERVED_23_DEFVAL #undef DDR_PHY_DX1GCR5_RESERVED_23_SHIFT #undef DDR_PHY_DX1GCR5_RESERVED_23_MASK -#define DDR_PHY_DX1GCR5_RESERVED_23_DEFVAL 0x09090909 -#define DDR_PHY_DX1GCR5_RESERVED_23_SHIFT 23 -#define DDR_PHY_DX1GCR5_RESERVED_23_MASK 0x00800000U +#define DDR_PHY_DX1GCR5_RESERVED_23_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR5_RESERVED_23_SHIFT 23 +#define DDR_PHY_DX1GCR5_RESERVED_23_MASK 0x00800000U -/*Byte Lane internal VREF Select for Rank 2*/ +/* +* Byte Lane internal VREF Select for Rank 2 +*/ #undef DDR_PHY_DX1GCR5_DXREFISELR2_DEFVAL #undef DDR_PHY_DX1GCR5_DXREFISELR2_SHIFT #undef DDR_PHY_DX1GCR5_DXREFISELR2_MASK -#define DDR_PHY_DX1GCR5_DXREFISELR2_DEFVAL 0x09090909 -#define DDR_PHY_DX1GCR5_DXREFISELR2_SHIFT 16 -#define DDR_PHY_DX1GCR5_DXREFISELR2_MASK 0x007F0000U +#define DDR_PHY_DX1GCR5_DXREFISELR2_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR5_DXREFISELR2_SHIFT 16 +#define DDR_PHY_DX1GCR5_DXREFISELR2_MASK 0x007F0000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX1GCR5_RESERVED_15_DEFVAL #undef DDR_PHY_DX1GCR5_RESERVED_15_SHIFT #undef DDR_PHY_DX1GCR5_RESERVED_15_MASK -#define DDR_PHY_DX1GCR5_RESERVED_15_DEFVAL 0x09090909 -#define DDR_PHY_DX1GCR5_RESERVED_15_SHIFT 15 -#define DDR_PHY_DX1GCR5_RESERVED_15_MASK 0x00008000U +#define DDR_PHY_DX1GCR5_RESERVED_15_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR5_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX1GCR5_RESERVED_15_MASK 0x00008000U -/*Byte Lane internal VREF Select for Rank 1*/ +/* +* Byte Lane internal VREF Select for Rank 1 +*/ #undef DDR_PHY_DX1GCR5_DXREFISELR1_DEFVAL #undef DDR_PHY_DX1GCR5_DXREFISELR1_SHIFT #undef DDR_PHY_DX1GCR5_DXREFISELR1_MASK -#define DDR_PHY_DX1GCR5_DXREFISELR1_DEFVAL 0x09090909 -#define DDR_PHY_DX1GCR5_DXREFISELR1_SHIFT 8 -#define DDR_PHY_DX1GCR5_DXREFISELR1_MASK 0x00007F00U +#define DDR_PHY_DX1GCR5_DXREFISELR1_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR5_DXREFISELR1_SHIFT 8 +#define DDR_PHY_DX1GCR5_DXREFISELR1_MASK 0x00007F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX1GCR5_RESERVED_7_DEFVAL #undef DDR_PHY_DX1GCR5_RESERVED_7_SHIFT #undef DDR_PHY_DX1GCR5_RESERVED_7_MASK -#define DDR_PHY_DX1GCR5_RESERVED_7_DEFVAL 0x09090909 -#define DDR_PHY_DX1GCR5_RESERVED_7_SHIFT 7 -#define DDR_PHY_DX1GCR5_RESERVED_7_MASK 0x00000080U +#define DDR_PHY_DX1GCR5_RESERVED_7_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR5_RESERVED_7_SHIFT 7 +#define DDR_PHY_DX1GCR5_RESERVED_7_MASK 0x00000080U -/*Byte Lane internal VREF Select for Rank 0*/ +/* +* Byte Lane internal VREF Select for Rank 0 +*/ #undef DDR_PHY_DX1GCR5_DXREFISELR0_DEFVAL #undef DDR_PHY_DX1GCR5_DXREFISELR0_SHIFT #undef DDR_PHY_DX1GCR5_DXREFISELR0_MASK -#define DDR_PHY_DX1GCR5_DXREFISELR0_DEFVAL 0x09090909 -#define DDR_PHY_DX1GCR5_DXREFISELR0_SHIFT 0 -#define DDR_PHY_DX1GCR5_DXREFISELR0_MASK 0x0000007FU +#define DDR_PHY_DX1GCR5_DXREFISELR0_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR5_DXREFISELR0_SHIFT 0 +#define DDR_PHY_DX1GCR5_DXREFISELR0_MASK 0x0000007FU -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX1GCR6_RESERVED_31_30_DEFVAL #undef DDR_PHY_DX1GCR6_RESERVED_31_30_SHIFT #undef DDR_PHY_DX1GCR6_RESERVED_31_30_MASK -#define DDR_PHY_DX1GCR6_RESERVED_31_30_DEFVAL 0x09090909 -#define DDR_PHY_DX1GCR6_RESERVED_31_30_SHIFT 30 -#define DDR_PHY_DX1GCR6_RESERVED_31_30_MASK 0xC0000000U +#define DDR_PHY_DX1GCR6_RESERVED_31_30_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR6_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX1GCR6_RESERVED_31_30_MASK 0xC0000000U -/*DRAM DQ VREF Select for Rank3*/ +/* +* DRAM DQ VREF Select for Rank3 +*/ #undef DDR_PHY_DX1GCR6_DXDQVREFR3_DEFVAL #undef DDR_PHY_DX1GCR6_DXDQVREFR3_SHIFT #undef DDR_PHY_DX1GCR6_DXDQVREFR3_MASK -#define DDR_PHY_DX1GCR6_DXDQVREFR3_DEFVAL 0x09090909 -#define DDR_PHY_DX1GCR6_DXDQVREFR3_SHIFT 24 -#define DDR_PHY_DX1GCR6_DXDQVREFR3_MASK 0x3F000000U +#define DDR_PHY_DX1GCR6_DXDQVREFR3_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR6_DXDQVREFR3_SHIFT 24 +#define DDR_PHY_DX1GCR6_DXDQVREFR3_MASK 0x3F000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX1GCR6_RESERVED_23_22_DEFVAL #undef DDR_PHY_DX1GCR6_RESERVED_23_22_SHIFT #undef DDR_PHY_DX1GCR6_RESERVED_23_22_MASK -#define DDR_PHY_DX1GCR6_RESERVED_23_22_DEFVAL 0x09090909 -#define DDR_PHY_DX1GCR6_RESERVED_23_22_SHIFT 22 -#define DDR_PHY_DX1GCR6_RESERVED_23_22_MASK 0x00C00000U +#define DDR_PHY_DX1GCR6_RESERVED_23_22_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR6_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX1GCR6_RESERVED_23_22_MASK 0x00C00000U -/*DRAM DQ VREF Select for Rank2*/ +/* +* DRAM DQ VREF Select for Rank2 +*/ #undef DDR_PHY_DX1GCR6_DXDQVREFR2_DEFVAL #undef DDR_PHY_DX1GCR6_DXDQVREFR2_SHIFT #undef DDR_PHY_DX1GCR6_DXDQVREFR2_MASK -#define DDR_PHY_DX1GCR6_DXDQVREFR2_DEFVAL 0x09090909 -#define DDR_PHY_DX1GCR6_DXDQVREFR2_SHIFT 16 -#define DDR_PHY_DX1GCR6_DXDQVREFR2_MASK 0x003F0000U +#define DDR_PHY_DX1GCR6_DXDQVREFR2_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR6_DXDQVREFR2_SHIFT 16 +#define DDR_PHY_DX1GCR6_DXDQVREFR2_MASK 0x003F0000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX1GCR6_RESERVED_15_14_DEFVAL #undef DDR_PHY_DX1GCR6_RESERVED_15_14_SHIFT #undef DDR_PHY_DX1GCR6_RESERVED_15_14_MASK -#define DDR_PHY_DX1GCR6_RESERVED_15_14_DEFVAL 0x09090909 -#define DDR_PHY_DX1GCR6_RESERVED_15_14_SHIFT 14 -#define DDR_PHY_DX1GCR6_RESERVED_15_14_MASK 0x0000C000U +#define DDR_PHY_DX1GCR6_RESERVED_15_14_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR6_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_DX1GCR6_RESERVED_15_14_MASK 0x0000C000U -/*DRAM DQ VREF Select for Rank1*/ +/* +* DRAM DQ VREF Select for Rank1 +*/ #undef DDR_PHY_DX1GCR6_DXDQVREFR1_DEFVAL #undef DDR_PHY_DX1GCR6_DXDQVREFR1_SHIFT #undef DDR_PHY_DX1GCR6_DXDQVREFR1_MASK -#define DDR_PHY_DX1GCR6_DXDQVREFR1_DEFVAL 0x09090909 -#define DDR_PHY_DX1GCR6_DXDQVREFR1_SHIFT 8 -#define DDR_PHY_DX1GCR6_DXDQVREFR1_MASK 0x00003F00U +#define DDR_PHY_DX1GCR6_DXDQVREFR1_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR6_DXDQVREFR1_SHIFT 8 +#define DDR_PHY_DX1GCR6_DXDQVREFR1_MASK 0x00003F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX1GCR6_RESERVED_7_6_DEFVAL #undef DDR_PHY_DX1GCR6_RESERVED_7_6_SHIFT #undef DDR_PHY_DX1GCR6_RESERVED_7_6_MASK -#define DDR_PHY_DX1GCR6_RESERVED_7_6_DEFVAL 0x09090909 -#define DDR_PHY_DX1GCR6_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_DX1GCR6_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_DX1GCR6_RESERVED_7_6_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR6_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX1GCR6_RESERVED_7_6_MASK 0x000000C0U -/*DRAM DQ VREF Select for Rank0*/ +/* +* DRAM DQ VREF Select for Rank0 +*/ #undef DDR_PHY_DX1GCR6_DXDQVREFR0_DEFVAL #undef DDR_PHY_DX1GCR6_DXDQVREFR0_SHIFT #undef DDR_PHY_DX1GCR6_DXDQVREFR0_MASK -#define DDR_PHY_DX1GCR6_DXDQVREFR0_DEFVAL 0x09090909 -#define DDR_PHY_DX1GCR6_DXDQVREFR0_SHIFT 0 -#define DDR_PHY_DX1GCR6_DXDQVREFR0_MASK 0x0000003FU +#define DDR_PHY_DX1GCR6_DXDQVREFR0_DEFVAL 0x09090909 +#define DDR_PHY_DX1GCR6_DXDQVREFR0_SHIFT 0 +#define DDR_PHY_DX1GCR6_DXDQVREFR0_MASK 0x0000003FU -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX1LCDLR2_RESERVED_31_25_DEFVAL -#undef DDR_PHY_DX1LCDLR2_RESERVED_31_25_SHIFT -#undef DDR_PHY_DX1LCDLR2_RESERVED_31_25_MASK -#define DDR_PHY_DX1LCDLR2_RESERVED_31_25_DEFVAL 0x00000000 -#define DDR_PHY_DX1LCDLR2_RESERVED_31_25_SHIFT 25 -#define DDR_PHY_DX1LCDLR2_RESERVED_31_25_MASK 0xFE000000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX1LCDLR2_RESERVED_24_16_DEFVAL -#undef DDR_PHY_DX1LCDLR2_RESERVED_24_16_SHIFT -#undef DDR_PHY_DX1LCDLR2_RESERVED_24_16_MASK -#define DDR_PHY_DX1LCDLR2_RESERVED_24_16_DEFVAL 0x00000000 -#define DDR_PHY_DX1LCDLR2_RESERVED_24_16_SHIFT 16 -#define DDR_PHY_DX1LCDLR2_RESERVED_24_16_MASK 0x01FF0000U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX1LCDLR2_RESERVED_15_9_DEFVAL -#undef DDR_PHY_DX1LCDLR2_RESERVED_15_9_SHIFT -#undef DDR_PHY_DX1LCDLR2_RESERVED_15_9_MASK -#define DDR_PHY_DX1LCDLR2_RESERVED_15_9_DEFVAL 0x00000000 -#define DDR_PHY_DX1LCDLR2_RESERVED_15_9_SHIFT 9 -#define DDR_PHY_DX1LCDLR2_RESERVED_15_9_MASK 0x0000FE00U - -/*Read DQS Gating Delay*/ -#undef DDR_PHY_DX1LCDLR2_DQSGD_DEFVAL -#undef DDR_PHY_DX1LCDLR2_DQSGD_SHIFT -#undef DDR_PHY_DX1LCDLR2_DQSGD_MASK -#define DDR_PHY_DX1LCDLR2_DQSGD_DEFVAL 0x00000000 -#define DDR_PHY_DX1LCDLR2_DQSGD_SHIFT 0 -#define DDR_PHY_DX1LCDLR2_DQSGD_MASK 0x000001FFU - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX1GTR0_RESERVED_31_24_DEFVAL -#undef DDR_PHY_DX1GTR0_RESERVED_31_24_SHIFT -#undef DDR_PHY_DX1GTR0_RESERVED_31_24_MASK -#define DDR_PHY_DX1GTR0_RESERVED_31_24_DEFVAL 0x00020000 -#define DDR_PHY_DX1GTR0_RESERVED_31_24_SHIFT 27 -#define DDR_PHY_DX1GTR0_RESERVED_31_24_MASK 0xF8000000U - -/*DQ Write Path Latency Pipeline*/ -#undef DDR_PHY_DX1GTR0_WDQSL_DEFVAL -#undef DDR_PHY_DX1GTR0_WDQSL_SHIFT -#undef DDR_PHY_DX1GTR0_WDQSL_MASK -#define DDR_PHY_DX1GTR0_WDQSL_DEFVAL 0x00020000 -#define DDR_PHY_DX1GTR0_WDQSL_SHIFT 24 -#define DDR_PHY_DX1GTR0_WDQSL_MASK 0x07000000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX1GTR0_RESERVED_23_20_DEFVAL -#undef DDR_PHY_DX1GTR0_RESERVED_23_20_SHIFT -#undef DDR_PHY_DX1GTR0_RESERVED_23_20_MASK -#define DDR_PHY_DX1GTR0_RESERVED_23_20_DEFVAL 0x00020000 -#define DDR_PHY_DX1GTR0_RESERVED_23_20_SHIFT 20 -#define DDR_PHY_DX1GTR0_RESERVED_23_20_MASK 0x00F00000U - -/*Write Leveling System Latency*/ -#undef DDR_PHY_DX1GTR0_WLSL_DEFVAL -#undef DDR_PHY_DX1GTR0_WLSL_SHIFT -#undef DDR_PHY_DX1GTR0_WLSL_MASK -#define DDR_PHY_DX1GTR0_WLSL_DEFVAL 0x00020000 -#define DDR_PHY_DX1GTR0_WLSL_SHIFT 16 -#define DDR_PHY_DX1GTR0_WLSL_MASK 0x000F0000U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX1GTR0_RESERVED_15_13_DEFVAL -#undef DDR_PHY_DX1GTR0_RESERVED_15_13_SHIFT -#undef DDR_PHY_DX1GTR0_RESERVED_15_13_MASK -#define DDR_PHY_DX1GTR0_RESERVED_15_13_DEFVAL 0x00020000 -#define DDR_PHY_DX1GTR0_RESERVED_15_13_SHIFT 13 -#define DDR_PHY_DX1GTR0_RESERVED_15_13_MASK 0x0000E000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX1GTR0_RESERVED_12_8_DEFVAL -#undef DDR_PHY_DX1GTR0_RESERVED_12_8_SHIFT -#undef DDR_PHY_DX1GTR0_RESERVED_12_8_MASK -#define DDR_PHY_DX1GTR0_RESERVED_12_8_DEFVAL 0x00020000 -#define DDR_PHY_DX1GTR0_RESERVED_12_8_SHIFT 8 -#define DDR_PHY_DX1GTR0_RESERVED_12_8_MASK 0x00001F00U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX1GTR0_RESERVED_7_5_DEFVAL -#undef DDR_PHY_DX1GTR0_RESERVED_7_5_SHIFT -#undef DDR_PHY_DX1GTR0_RESERVED_7_5_MASK -#define DDR_PHY_DX1GTR0_RESERVED_7_5_DEFVAL 0x00020000 -#define DDR_PHY_DX1GTR0_RESERVED_7_5_SHIFT 5 -#define DDR_PHY_DX1GTR0_RESERVED_7_5_MASK 0x000000E0U - -/*DQS Gating System Latency*/ -#undef DDR_PHY_DX1GTR0_DGSL_DEFVAL -#undef DDR_PHY_DX1GTR0_DGSL_SHIFT -#undef DDR_PHY_DX1GTR0_DGSL_MASK -#define DDR_PHY_DX1GTR0_DGSL_DEFVAL 0x00020000 -#define DDR_PHY_DX1GTR0_DGSL_SHIFT 0 -#define DDR_PHY_DX1GTR0_DGSL_MASK 0x0000001FU - -/*Calibration Bypass*/ +/* +* Calibration Bypass +*/ #undef DDR_PHY_DX2GCR0_CALBYP_DEFVAL #undef DDR_PHY_DX2GCR0_CALBYP_SHIFT #undef DDR_PHY_DX2GCR0_CALBYP_MASK -#define DDR_PHY_DX2GCR0_CALBYP_DEFVAL 0x40200204 -#define DDR_PHY_DX2GCR0_CALBYP_SHIFT 31 -#define DDR_PHY_DX2GCR0_CALBYP_MASK 0x80000000U +#define DDR_PHY_DX2GCR0_CALBYP_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_CALBYP_SHIFT 31 +#define DDR_PHY_DX2GCR0_CALBYP_MASK 0x80000000U -/*Master Delay Line Enable*/ +/* +* Master Delay Line Enable +*/ #undef DDR_PHY_DX2GCR0_MDLEN_DEFVAL #undef DDR_PHY_DX2GCR0_MDLEN_SHIFT #undef DDR_PHY_DX2GCR0_MDLEN_MASK -#define DDR_PHY_DX2GCR0_MDLEN_DEFVAL 0x40200204 -#define DDR_PHY_DX2GCR0_MDLEN_SHIFT 30 -#define DDR_PHY_DX2GCR0_MDLEN_MASK 0x40000000U +#define DDR_PHY_DX2GCR0_MDLEN_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_MDLEN_SHIFT 30 +#define DDR_PHY_DX2GCR0_MDLEN_MASK 0x40000000U -/*Configurable ODT(TE) Phase Shift*/ +/* +* Configurable ODT(TE) Phase Shift +*/ #undef DDR_PHY_DX2GCR0_CODTSHFT_DEFVAL #undef DDR_PHY_DX2GCR0_CODTSHFT_SHIFT #undef DDR_PHY_DX2GCR0_CODTSHFT_MASK -#define DDR_PHY_DX2GCR0_CODTSHFT_DEFVAL 0x40200204 -#define DDR_PHY_DX2GCR0_CODTSHFT_SHIFT 28 -#define DDR_PHY_DX2GCR0_CODTSHFT_MASK 0x30000000U +#define DDR_PHY_DX2GCR0_CODTSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_CODTSHFT_SHIFT 28 +#define DDR_PHY_DX2GCR0_CODTSHFT_MASK 0x30000000U -/*DQS Duty Cycle Correction*/ +/* +* DQS Duty Cycle Correction +*/ #undef DDR_PHY_DX2GCR0_DQSDCC_DEFVAL #undef DDR_PHY_DX2GCR0_DQSDCC_SHIFT #undef DDR_PHY_DX2GCR0_DQSDCC_MASK -#define DDR_PHY_DX2GCR0_DQSDCC_DEFVAL 0x40200204 -#define DDR_PHY_DX2GCR0_DQSDCC_SHIFT 24 -#define DDR_PHY_DX2GCR0_DQSDCC_MASK 0x0F000000U +#define DDR_PHY_DX2GCR0_DQSDCC_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_DQSDCC_SHIFT 24 +#define DDR_PHY_DX2GCR0_DQSDCC_MASK 0x0F000000U -/*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/ +/* +* Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY +*/ #undef DDR_PHY_DX2GCR0_RDDLY_DEFVAL #undef DDR_PHY_DX2GCR0_RDDLY_SHIFT #undef DDR_PHY_DX2GCR0_RDDLY_MASK -#define DDR_PHY_DX2GCR0_RDDLY_DEFVAL 0x40200204 -#define DDR_PHY_DX2GCR0_RDDLY_SHIFT 20 -#define DDR_PHY_DX2GCR0_RDDLY_MASK 0x00F00000U +#define DDR_PHY_DX2GCR0_RDDLY_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_RDDLY_SHIFT 20 +#define DDR_PHY_DX2GCR0_RDDLY_MASK 0x00F00000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX2GCR0_RESERVED_19_14_DEFVAL #undef DDR_PHY_DX2GCR0_RESERVED_19_14_SHIFT #undef DDR_PHY_DX2GCR0_RESERVED_19_14_MASK -#define DDR_PHY_DX2GCR0_RESERVED_19_14_DEFVAL 0x40200204 -#define DDR_PHY_DX2GCR0_RESERVED_19_14_SHIFT 14 -#define DDR_PHY_DX2GCR0_RESERVED_19_14_MASK 0x000FC000U +#define DDR_PHY_DX2GCR0_RESERVED_19_14_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_RESERVED_19_14_SHIFT 14 +#define DDR_PHY_DX2GCR0_RESERVED_19_14_MASK 0x000FC000U -/*DQSNSE Power Down Receiver*/ +/* +* DQSNSE Power Down Receiver +*/ #undef DDR_PHY_DX2GCR0_DQSNSEPDR_DEFVAL #undef DDR_PHY_DX2GCR0_DQSNSEPDR_SHIFT #undef DDR_PHY_DX2GCR0_DQSNSEPDR_MASK -#define DDR_PHY_DX2GCR0_DQSNSEPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX2GCR0_DQSNSEPDR_SHIFT 13 -#define DDR_PHY_DX2GCR0_DQSNSEPDR_MASK 0x00002000U +#define DDR_PHY_DX2GCR0_DQSNSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_DQSNSEPDR_SHIFT 13 +#define DDR_PHY_DX2GCR0_DQSNSEPDR_MASK 0x00002000U -/*DQSSE Power Down Receiver*/ +/* +* DQSSE Power Down Receiver +*/ #undef DDR_PHY_DX2GCR0_DQSSEPDR_DEFVAL #undef DDR_PHY_DX2GCR0_DQSSEPDR_SHIFT #undef DDR_PHY_DX2GCR0_DQSSEPDR_MASK -#define DDR_PHY_DX2GCR0_DQSSEPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX2GCR0_DQSSEPDR_SHIFT 12 -#define DDR_PHY_DX2GCR0_DQSSEPDR_MASK 0x00001000U +#define DDR_PHY_DX2GCR0_DQSSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_DQSSEPDR_SHIFT 12 +#define DDR_PHY_DX2GCR0_DQSSEPDR_MASK 0x00001000U -/*RTT On Additive Latency*/ +/* +* RTT On Additive Latency +*/ #undef DDR_PHY_DX2GCR0_RTTOAL_DEFVAL #undef DDR_PHY_DX2GCR0_RTTOAL_SHIFT #undef DDR_PHY_DX2GCR0_RTTOAL_MASK -#define DDR_PHY_DX2GCR0_RTTOAL_DEFVAL 0x40200204 -#define DDR_PHY_DX2GCR0_RTTOAL_SHIFT 11 -#define DDR_PHY_DX2GCR0_RTTOAL_MASK 0x00000800U +#define DDR_PHY_DX2GCR0_RTTOAL_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_RTTOAL_SHIFT 11 +#define DDR_PHY_DX2GCR0_RTTOAL_MASK 0x00000800U -/*RTT Output Hold*/ +/* +* RTT Output Hold +*/ #undef DDR_PHY_DX2GCR0_RTTOH_DEFVAL #undef DDR_PHY_DX2GCR0_RTTOH_SHIFT #undef DDR_PHY_DX2GCR0_RTTOH_MASK -#define DDR_PHY_DX2GCR0_RTTOH_DEFVAL 0x40200204 -#define DDR_PHY_DX2GCR0_RTTOH_SHIFT 9 -#define DDR_PHY_DX2GCR0_RTTOH_MASK 0x00000600U +#define DDR_PHY_DX2GCR0_RTTOH_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_RTTOH_SHIFT 9 +#define DDR_PHY_DX2GCR0_RTTOH_MASK 0x00000600U -/*Configurable PDR Phase Shift*/ +/* +* Configurable PDR Phase Shift +*/ #undef DDR_PHY_DX2GCR0_CPDRSHFT_DEFVAL #undef DDR_PHY_DX2GCR0_CPDRSHFT_SHIFT #undef DDR_PHY_DX2GCR0_CPDRSHFT_MASK -#define DDR_PHY_DX2GCR0_CPDRSHFT_DEFVAL 0x40200204 -#define DDR_PHY_DX2GCR0_CPDRSHFT_SHIFT 7 -#define DDR_PHY_DX2GCR0_CPDRSHFT_MASK 0x00000180U +#define DDR_PHY_DX2GCR0_CPDRSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_CPDRSHFT_SHIFT 7 +#define DDR_PHY_DX2GCR0_CPDRSHFT_MASK 0x00000180U -/*DQSR Power Down*/ +/* +* DQSR Power Down +*/ #undef DDR_PHY_DX2GCR0_DQSRPD_DEFVAL #undef DDR_PHY_DX2GCR0_DQSRPD_SHIFT #undef DDR_PHY_DX2GCR0_DQSRPD_MASK -#define DDR_PHY_DX2GCR0_DQSRPD_DEFVAL 0x40200204 -#define DDR_PHY_DX2GCR0_DQSRPD_SHIFT 6 -#define DDR_PHY_DX2GCR0_DQSRPD_MASK 0x00000040U +#define DDR_PHY_DX2GCR0_DQSRPD_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_DQSRPD_SHIFT 6 +#define DDR_PHY_DX2GCR0_DQSRPD_MASK 0x00000040U -/*DQSG Power Down Receiver*/ +/* +* DQSG Power Down Receiver +*/ #undef DDR_PHY_DX2GCR0_DQSGPDR_DEFVAL #undef DDR_PHY_DX2GCR0_DQSGPDR_SHIFT #undef DDR_PHY_DX2GCR0_DQSGPDR_MASK -#define DDR_PHY_DX2GCR0_DQSGPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX2GCR0_DQSGPDR_SHIFT 5 -#define DDR_PHY_DX2GCR0_DQSGPDR_MASK 0x00000020U +#define DDR_PHY_DX2GCR0_DQSGPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_DQSGPDR_SHIFT 5 +#define DDR_PHY_DX2GCR0_DQSGPDR_MASK 0x00000020U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX2GCR0_RESERVED_4_DEFVAL #undef DDR_PHY_DX2GCR0_RESERVED_4_SHIFT #undef DDR_PHY_DX2GCR0_RESERVED_4_MASK -#define DDR_PHY_DX2GCR0_RESERVED_4_DEFVAL 0x40200204 -#define DDR_PHY_DX2GCR0_RESERVED_4_SHIFT 4 -#define DDR_PHY_DX2GCR0_RESERVED_4_MASK 0x00000010U +#define DDR_PHY_DX2GCR0_RESERVED_4_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_RESERVED_4_SHIFT 4 +#define DDR_PHY_DX2GCR0_RESERVED_4_MASK 0x00000010U -/*DQSG On-Die Termination*/ +/* +* DQSG On-Die Termination +*/ #undef DDR_PHY_DX2GCR0_DQSGODT_DEFVAL #undef DDR_PHY_DX2GCR0_DQSGODT_SHIFT #undef DDR_PHY_DX2GCR0_DQSGODT_MASK -#define DDR_PHY_DX2GCR0_DQSGODT_DEFVAL 0x40200204 -#define DDR_PHY_DX2GCR0_DQSGODT_SHIFT 3 -#define DDR_PHY_DX2GCR0_DQSGODT_MASK 0x00000008U +#define DDR_PHY_DX2GCR0_DQSGODT_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_DQSGODT_SHIFT 3 +#define DDR_PHY_DX2GCR0_DQSGODT_MASK 0x00000008U -/*DQSG Output Enable*/ +/* +* DQSG Output Enable +*/ #undef DDR_PHY_DX2GCR0_DQSGOE_DEFVAL #undef DDR_PHY_DX2GCR0_DQSGOE_SHIFT #undef DDR_PHY_DX2GCR0_DQSGOE_MASK -#define DDR_PHY_DX2GCR0_DQSGOE_DEFVAL 0x40200204 -#define DDR_PHY_DX2GCR0_DQSGOE_SHIFT 2 -#define DDR_PHY_DX2GCR0_DQSGOE_MASK 0x00000004U +#define DDR_PHY_DX2GCR0_DQSGOE_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_DQSGOE_SHIFT 2 +#define DDR_PHY_DX2GCR0_DQSGOE_MASK 0x00000004U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX2GCR0_RESERVED_1_0_DEFVAL #undef DDR_PHY_DX2GCR0_RESERVED_1_0_SHIFT #undef DDR_PHY_DX2GCR0_RESERVED_1_0_MASK -#define DDR_PHY_DX2GCR0_RESERVED_1_0_DEFVAL 0x40200204 -#define DDR_PHY_DX2GCR0_RESERVED_1_0_SHIFT 0 -#define DDR_PHY_DX2GCR0_RESERVED_1_0_MASK 0x00000003U +#define DDR_PHY_DX2GCR0_RESERVED_1_0_DEFVAL 0x40200204 +#define DDR_PHY_DX2GCR0_RESERVED_1_0_SHIFT 0 +#define DDR_PHY_DX2GCR0_RESERVED_1_0_MASK 0x00000003U -/*Enables the PDR mode for DQ[7:0]*/ +/* +* Enables the PDR mode for DQ[7:0] +*/ #undef DDR_PHY_DX2GCR1_DXPDRMODE_DEFVAL #undef DDR_PHY_DX2GCR1_DXPDRMODE_SHIFT #undef DDR_PHY_DX2GCR1_DXPDRMODE_MASK -#define DDR_PHY_DX2GCR1_DXPDRMODE_DEFVAL 0x00007FFF -#define DDR_PHY_DX2GCR1_DXPDRMODE_SHIFT 16 -#define DDR_PHY_DX2GCR1_DXPDRMODE_MASK 0xFFFF0000U +#define DDR_PHY_DX2GCR1_DXPDRMODE_DEFVAL 0x00007FFF +#define DDR_PHY_DX2GCR1_DXPDRMODE_SHIFT 16 +#define DDR_PHY_DX2GCR1_DXPDRMODE_MASK 0xFFFF0000U -/*Reserved. Returns zeroes on reads.*/ +/* +* Reserved. Returns zeroes on reads. +*/ #undef DDR_PHY_DX2GCR1_RESERVED_15_DEFVAL #undef DDR_PHY_DX2GCR1_RESERVED_15_SHIFT #undef DDR_PHY_DX2GCR1_RESERVED_15_MASK -#define DDR_PHY_DX2GCR1_RESERVED_15_DEFVAL 0x00007FFF -#define DDR_PHY_DX2GCR1_RESERVED_15_SHIFT 15 -#define DDR_PHY_DX2GCR1_RESERVED_15_MASK 0x00008000U +#define DDR_PHY_DX2GCR1_RESERVED_15_DEFVAL 0x00007FFF +#define DDR_PHY_DX2GCR1_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX2GCR1_RESERVED_15_MASK 0x00008000U -/*Select the delayed or non-delayed read data strobe #*/ +/* +* Select the delayed or non-delayed read data strobe # +*/ #undef DDR_PHY_DX2GCR1_QSNSEL_DEFVAL #undef DDR_PHY_DX2GCR1_QSNSEL_SHIFT #undef DDR_PHY_DX2GCR1_QSNSEL_MASK -#define DDR_PHY_DX2GCR1_QSNSEL_DEFVAL 0x00007FFF -#define DDR_PHY_DX2GCR1_QSNSEL_SHIFT 14 -#define DDR_PHY_DX2GCR1_QSNSEL_MASK 0x00004000U +#define DDR_PHY_DX2GCR1_QSNSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX2GCR1_QSNSEL_SHIFT 14 +#define DDR_PHY_DX2GCR1_QSNSEL_MASK 0x00004000U -/*Select the delayed or non-delayed read data strobe*/ +/* +* Select the delayed or non-delayed read data strobe +*/ #undef DDR_PHY_DX2GCR1_QSSEL_DEFVAL #undef DDR_PHY_DX2GCR1_QSSEL_SHIFT #undef DDR_PHY_DX2GCR1_QSSEL_MASK -#define DDR_PHY_DX2GCR1_QSSEL_DEFVAL 0x00007FFF -#define DDR_PHY_DX2GCR1_QSSEL_SHIFT 13 -#define DDR_PHY_DX2GCR1_QSSEL_MASK 0x00002000U +#define DDR_PHY_DX2GCR1_QSSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX2GCR1_QSSEL_SHIFT 13 +#define DDR_PHY_DX2GCR1_QSSEL_MASK 0x00002000U -/*Enables Read Data Strobe in a byte lane*/ +/* +* Enables Read Data Strobe in a byte lane +*/ #undef DDR_PHY_DX2GCR1_OEEN_DEFVAL #undef DDR_PHY_DX2GCR1_OEEN_SHIFT #undef DDR_PHY_DX2GCR1_OEEN_MASK -#define DDR_PHY_DX2GCR1_OEEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX2GCR1_OEEN_SHIFT 12 -#define DDR_PHY_DX2GCR1_OEEN_MASK 0x00001000U +#define DDR_PHY_DX2GCR1_OEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX2GCR1_OEEN_SHIFT 12 +#define DDR_PHY_DX2GCR1_OEEN_MASK 0x00001000U -/*Enables PDR in a byte lane*/ +/* +* Enables PDR in a byte lane +*/ #undef DDR_PHY_DX2GCR1_PDREN_DEFVAL #undef DDR_PHY_DX2GCR1_PDREN_SHIFT #undef DDR_PHY_DX2GCR1_PDREN_MASK -#define DDR_PHY_DX2GCR1_PDREN_DEFVAL 0x00007FFF -#define DDR_PHY_DX2GCR1_PDREN_SHIFT 11 -#define DDR_PHY_DX2GCR1_PDREN_MASK 0x00000800U +#define DDR_PHY_DX2GCR1_PDREN_DEFVAL 0x00007FFF +#define DDR_PHY_DX2GCR1_PDREN_SHIFT 11 +#define DDR_PHY_DX2GCR1_PDREN_MASK 0x00000800U -/*Enables ODT/TE in a byte lane*/ +/* +* Enables ODT/TE in a byte lane +*/ #undef DDR_PHY_DX2GCR1_TEEN_DEFVAL #undef DDR_PHY_DX2GCR1_TEEN_SHIFT #undef DDR_PHY_DX2GCR1_TEEN_MASK -#define DDR_PHY_DX2GCR1_TEEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX2GCR1_TEEN_SHIFT 10 -#define DDR_PHY_DX2GCR1_TEEN_MASK 0x00000400U +#define DDR_PHY_DX2GCR1_TEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX2GCR1_TEEN_SHIFT 10 +#define DDR_PHY_DX2GCR1_TEEN_MASK 0x00000400U -/*Enables Write Data strobe in a byte lane*/ +/* +* Enables Write Data strobe in a byte lane +*/ #undef DDR_PHY_DX2GCR1_DSEN_DEFVAL #undef DDR_PHY_DX2GCR1_DSEN_SHIFT #undef DDR_PHY_DX2GCR1_DSEN_MASK -#define DDR_PHY_DX2GCR1_DSEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX2GCR1_DSEN_SHIFT 9 -#define DDR_PHY_DX2GCR1_DSEN_MASK 0x00000200U +#define DDR_PHY_DX2GCR1_DSEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX2GCR1_DSEN_SHIFT 9 +#define DDR_PHY_DX2GCR1_DSEN_MASK 0x00000200U -/*Enables DM pin in a byte lane*/ +/* +* Enables DM pin in a byte lane +*/ #undef DDR_PHY_DX2GCR1_DMEN_DEFVAL #undef DDR_PHY_DX2GCR1_DMEN_SHIFT #undef DDR_PHY_DX2GCR1_DMEN_MASK -#define DDR_PHY_DX2GCR1_DMEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX2GCR1_DMEN_SHIFT 8 -#define DDR_PHY_DX2GCR1_DMEN_MASK 0x00000100U +#define DDR_PHY_DX2GCR1_DMEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX2GCR1_DMEN_SHIFT 8 +#define DDR_PHY_DX2GCR1_DMEN_MASK 0x00000100U -/*Enables DQ corresponding to each bit in a byte*/ +/* +* Enables DQ corresponding to each bit in a byte +*/ #undef DDR_PHY_DX2GCR1_DQEN_DEFVAL #undef DDR_PHY_DX2GCR1_DQEN_SHIFT #undef DDR_PHY_DX2GCR1_DQEN_MASK -#define DDR_PHY_DX2GCR1_DQEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX2GCR1_DQEN_SHIFT 0 -#define DDR_PHY_DX2GCR1_DQEN_MASK 0x000000FFU +#define DDR_PHY_DX2GCR1_DQEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX2GCR1_DQEN_SHIFT 0 +#define DDR_PHY_DX2GCR1_DQEN_MASK 0x000000FFU -/*Byte lane VREF IOM (Used only by D4MU IOs)*/ +/* +* Byte lane VREF IOM (Used only by D4MU IOs) +*/ #undef DDR_PHY_DX2GCR4_RESERVED_31_29_DEFVAL #undef DDR_PHY_DX2GCR4_RESERVED_31_29_SHIFT #undef DDR_PHY_DX2GCR4_RESERVED_31_29_MASK -#define DDR_PHY_DX2GCR4_RESERVED_31_29_DEFVAL 0x0E00003C -#define DDR_PHY_DX2GCR4_RESERVED_31_29_SHIFT 29 -#define DDR_PHY_DX2GCR4_RESERVED_31_29_MASK 0xE0000000U +#define DDR_PHY_DX2GCR4_RESERVED_31_29_DEFVAL 0x0E00003C +#define DDR_PHY_DX2GCR4_RESERVED_31_29_SHIFT 29 +#define DDR_PHY_DX2GCR4_RESERVED_31_29_MASK 0xE0000000U -/*Byte Lane VREF Pad Enable*/ +/* +* Byte Lane VREF Pad Enable +*/ #undef DDR_PHY_DX2GCR4_DXREFPEN_DEFVAL #undef DDR_PHY_DX2GCR4_DXREFPEN_SHIFT #undef DDR_PHY_DX2GCR4_DXREFPEN_MASK -#define DDR_PHY_DX2GCR4_DXREFPEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX2GCR4_DXREFPEN_SHIFT 28 -#define DDR_PHY_DX2GCR4_DXREFPEN_MASK 0x10000000U +#define DDR_PHY_DX2GCR4_DXREFPEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX2GCR4_DXREFPEN_SHIFT 28 +#define DDR_PHY_DX2GCR4_DXREFPEN_MASK 0x10000000U -/*Byte Lane Internal VREF Enable*/ +/* +* Byte Lane Internal VREF Enable +*/ #undef DDR_PHY_DX2GCR4_DXREFEEN_DEFVAL #undef DDR_PHY_DX2GCR4_DXREFEEN_SHIFT #undef DDR_PHY_DX2GCR4_DXREFEEN_MASK -#define DDR_PHY_DX2GCR4_DXREFEEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX2GCR4_DXREFEEN_SHIFT 26 -#define DDR_PHY_DX2GCR4_DXREFEEN_MASK 0x0C000000U +#define DDR_PHY_DX2GCR4_DXREFEEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX2GCR4_DXREFEEN_SHIFT 26 +#define DDR_PHY_DX2GCR4_DXREFEEN_MASK 0x0C000000U -/*Byte Lane Single-End VREF Enable*/ +/* +* Byte Lane Single-End VREF Enable +*/ #undef DDR_PHY_DX2GCR4_DXREFSEN_DEFVAL #undef DDR_PHY_DX2GCR4_DXREFSEN_SHIFT #undef DDR_PHY_DX2GCR4_DXREFSEN_MASK -#define DDR_PHY_DX2GCR4_DXREFSEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX2GCR4_DXREFSEN_SHIFT 25 -#define DDR_PHY_DX2GCR4_DXREFSEN_MASK 0x02000000U +#define DDR_PHY_DX2GCR4_DXREFSEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX2GCR4_DXREFSEN_SHIFT 25 +#define DDR_PHY_DX2GCR4_DXREFSEN_MASK 0x02000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX2GCR4_RESERVED_24_DEFVAL #undef DDR_PHY_DX2GCR4_RESERVED_24_SHIFT #undef DDR_PHY_DX2GCR4_RESERVED_24_MASK -#define DDR_PHY_DX2GCR4_RESERVED_24_DEFVAL 0x0E00003C -#define DDR_PHY_DX2GCR4_RESERVED_24_SHIFT 24 -#define DDR_PHY_DX2GCR4_RESERVED_24_MASK 0x01000000U +#define DDR_PHY_DX2GCR4_RESERVED_24_DEFVAL 0x0E00003C +#define DDR_PHY_DX2GCR4_RESERVED_24_SHIFT 24 +#define DDR_PHY_DX2GCR4_RESERVED_24_MASK 0x01000000U -/*External VREF generator REFSEL range select*/ +/* +* External VREF generator REFSEL range select +*/ #undef DDR_PHY_DX2GCR4_DXREFESELRANGE_DEFVAL #undef DDR_PHY_DX2GCR4_DXREFESELRANGE_SHIFT #undef DDR_PHY_DX2GCR4_DXREFESELRANGE_MASK -#define DDR_PHY_DX2GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C -#define DDR_PHY_DX2GCR4_DXREFESELRANGE_SHIFT 23 -#define DDR_PHY_DX2GCR4_DXREFESELRANGE_MASK 0x00800000U +#define DDR_PHY_DX2GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX2GCR4_DXREFESELRANGE_SHIFT 23 +#define DDR_PHY_DX2GCR4_DXREFESELRANGE_MASK 0x00800000U -/*Byte Lane External VREF Select*/ +/* +* Byte Lane External VREF Select +*/ #undef DDR_PHY_DX2GCR4_DXREFESEL_DEFVAL #undef DDR_PHY_DX2GCR4_DXREFESEL_SHIFT #undef DDR_PHY_DX2GCR4_DXREFESEL_MASK -#define DDR_PHY_DX2GCR4_DXREFESEL_DEFVAL 0x0E00003C -#define DDR_PHY_DX2GCR4_DXREFESEL_SHIFT 16 -#define DDR_PHY_DX2GCR4_DXREFESEL_MASK 0x007F0000U +#define DDR_PHY_DX2GCR4_DXREFESEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX2GCR4_DXREFESEL_SHIFT 16 +#define DDR_PHY_DX2GCR4_DXREFESEL_MASK 0x007F0000U -/*Single ended VREF generator REFSEL range select*/ +/* +* Single ended VREF generator REFSEL range select +*/ #undef DDR_PHY_DX2GCR4_DXREFSSELRANGE_DEFVAL #undef DDR_PHY_DX2GCR4_DXREFSSELRANGE_SHIFT #undef DDR_PHY_DX2GCR4_DXREFSSELRANGE_MASK -#define DDR_PHY_DX2GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C -#define DDR_PHY_DX2GCR4_DXREFSSELRANGE_SHIFT 15 -#define DDR_PHY_DX2GCR4_DXREFSSELRANGE_MASK 0x00008000U +#define DDR_PHY_DX2GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX2GCR4_DXREFSSELRANGE_SHIFT 15 +#define DDR_PHY_DX2GCR4_DXREFSSELRANGE_MASK 0x00008000U -/*Byte Lane Single-End VREF Select*/ +/* +* Byte Lane Single-End VREF Select +*/ #undef DDR_PHY_DX2GCR4_DXREFSSEL_DEFVAL #undef DDR_PHY_DX2GCR4_DXREFSSEL_SHIFT #undef DDR_PHY_DX2GCR4_DXREFSSEL_MASK -#define DDR_PHY_DX2GCR4_DXREFSSEL_DEFVAL 0x0E00003C -#define DDR_PHY_DX2GCR4_DXREFSSEL_SHIFT 8 -#define DDR_PHY_DX2GCR4_DXREFSSEL_MASK 0x00007F00U +#define DDR_PHY_DX2GCR4_DXREFSSEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX2GCR4_DXREFSSEL_SHIFT 8 +#define DDR_PHY_DX2GCR4_DXREFSSEL_MASK 0x00007F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX2GCR4_RESERVED_7_6_DEFVAL #undef DDR_PHY_DX2GCR4_RESERVED_7_6_SHIFT #undef DDR_PHY_DX2GCR4_RESERVED_7_6_MASK -#define DDR_PHY_DX2GCR4_RESERVED_7_6_DEFVAL 0x0E00003C -#define DDR_PHY_DX2GCR4_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_DX2GCR4_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_DX2GCR4_RESERVED_7_6_DEFVAL 0x0E00003C +#define DDR_PHY_DX2GCR4_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX2GCR4_RESERVED_7_6_MASK 0x000000C0U -/*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/ +/* +* VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. +*/ #undef DDR_PHY_DX2GCR4_DXREFIEN_DEFVAL #undef DDR_PHY_DX2GCR4_DXREFIEN_SHIFT #undef DDR_PHY_DX2GCR4_DXREFIEN_MASK -#define DDR_PHY_DX2GCR4_DXREFIEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX2GCR4_DXREFIEN_SHIFT 2 -#define DDR_PHY_DX2GCR4_DXREFIEN_MASK 0x0000003CU +#define DDR_PHY_DX2GCR4_DXREFIEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX2GCR4_DXREFIEN_SHIFT 2 +#define DDR_PHY_DX2GCR4_DXREFIEN_MASK 0x0000003CU -/*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/ +/* +* VRMON control for DQ IO (Single Ended) buffers of a byte lane. +*/ #undef DDR_PHY_DX2GCR4_DXREFIMON_DEFVAL #undef DDR_PHY_DX2GCR4_DXREFIMON_SHIFT #undef DDR_PHY_DX2GCR4_DXREFIMON_MASK -#define DDR_PHY_DX2GCR4_DXREFIMON_DEFVAL 0x0E00003C -#define DDR_PHY_DX2GCR4_DXREFIMON_SHIFT 0 -#define DDR_PHY_DX2GCR4_DXREFIMON_MASK 0x00000003U +#define DDR_PHY_DX2GCR4_DXREFIMON_DEFVAL 0x0E00003C +#define DDR_PHY_DX2GCR4_DXREFIMON_SHIFT 0 +#define DDR_PHY_DX2GCR4_DXREFIMON_MASK 0x00000003U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX2GCR5_RESERVED_31_DEFVAL #undef DDR_PHY_DX2GCR5_RESERVED_31_SHIFT #undef DDR_PHY_DX2GCR5_RESERVED_31_MASK -#define DDR_PHY_DX2GCR5_RESERVED_31_DEFVAL 0x09090909 -#define DDR_PHY_DX2GCR5_RESERVED_31_SHIFT 31 -#define DDR_PHY_DX2GCR5_RESERVED_31_MASK 0x80000000U +#define DDR_PHY_DX2GCR5_RESERVED_31_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR5_RESERVED_31_SHIFT 31 +#define DDR_PHY_DX2GCR5_RESERVED_31_MASK 0x80000000U -/*Byte Lane internal VREF Select for Rank 3*/ +/* +* Byte Lane internal VREF Select for Rank 3 +*/ #undef DDR_PHY_DX2GCR5_DXREFISELR3_DEFVAL #undef DDR_PHY_DX2GCR5_DXREFISELR3_SHIFT #undef DDR_PHY_DX2GCR5_DXREFISELR3_MASK -#define DDR_PHY_DX2GCR5_DXREFISELR3_DEFVAL 0x09090909 -#define DDR_PHY_DX2GCR5_DXREFISELR3_SHIFT 24 -#define DDR_PHY_DX2GCR5_DXREFISELR3_MASK 0x7F000000U +#define DDR_PHY_DX2GCR5_DXREFISELR3_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR5_DXREFISELR3_SHIFT 24 +#define DDR_PHY_DX2GCR5_DXREFISELR3_MASK 0x7F000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX2GCR5_RESERVED_23_DEFVAL #undef DDR_PHY_DX2GCR5_RESERVED_23_SHIFT #undef DDR_PHY_DX2GCR5_RESERVED_23_MASK -#define DDR_PHY_DX2GCR5_RESERVED_23_DEFVAL 0x09090909 -#define DDR_PHY_DX2GCR5_RESERVED_23_SHIFT 23 -#define DDR_PHY_DX2GCR5_RESERVED_23_MASK 0x00800000U +#define DDR_PHY_DX2GCR5_RESERVED_23_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR5_RESERVED_23_SHIFT 23 +#define DDR_PHY_DX2GCR5_RESERVED_23_MASK 0x00800000U -/*Byte Lane internal VREF Select for Rank 2*/ +/* +* Byte Lane internal VREF Select for Rank 2 +*/ #undef DDR_PHY_DX2GCR5_DXREFISELR2_DEFVAL #undef DDR_PHY_DX2GCR5_DXREFISELR2_SHIFT #undef DDR_PHY_DX2GCR5_DXREFISELR2_MASK -#define DDR_PHY_DX2GCR5_DXREFISELR2_DEFVAL 0x09090909 -#define DDR_PHY_DX2GCR5_DXREFISELR2_SHIFT 16 -#define DDR_PHY_DX2GCR5_DXREFISELR2_MASK 0x007F0000U +#define DDR_PHY_DX2GCR5_DXREFISELR2_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR5_DXREFISELR2_SHIFT 16 +#define DDR_PHY_DX2GCR5_DXREFISELR2_MASK 0x007F0000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX2GCR5_RESERVED_15_DEFVAL #undef DDR_PHY_DX2GCR5_RESERVED_15_SHIFT #undef DDR_PHY_DX2GCR5_RESERVED_15_MASK -#define DDR_PHY_DX2GCR5_RESERVED_15_DEFVAL 0x09090909 -#define DDR_PHY_DX2GCR5_RESERVED_15_SHIFT 15 -#define DDR_PHY_DX2GCR5_RESERVED_15_MASK 0x00008000U +#define DDR_PHY_DX2GCR5_RESERVED_15_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR5_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX2GCR5_RESERVED_15_MASK 0x00008000U -/*Byte Lane internal VREF Select for Rank 1*/ +/* +* Byte Lane internal VREF Select for Rank 1 +*/ #undef DDR_PHY_DX2GCR5_DXREFISELR1_DEFVAL #undef DDR_PHY_DX2GCR5_DXREFISELR1_SHIFT #undef DDR_PHY_DX2GCR5_DXREFISELR1_MASK -#define DDR_PHY_DX2GCR5_DXREFISELR1_DEFVAL 0x09090909 -#define DDR_PHY_DX2GCR5_DXREFISELR1_SHIFT 8 -#define DDR_PHY_DX2GCR5_DXREFISELR1_MASK 0x00007F00U +#define DDR_PHY_DX2GCR5_DXREFISELR1_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR5_DXREFISELR1_SHIFT 8 +#define DDR_PHY_DX2GCR5_DXREFISELR1_MASK 0x00007F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX2GCR5_RESERVED_7_DEFVAL #undef DDR_PHY_DX2GCR5_RESERVED_7_SHIFT #undef DDR_PHY_DX2GCR5_RESERVED_7_MASK -#define DDR_PHY_DX2GCR5_RESERVED_7_DEFVAL 0x09090909 -#define DDR_PHY_DX2GCR5_RESERVED_7_SHIFT 7 -#define DDR_PHY_DX2GCR5_RESERVED_7_MASK 0x00000080U +#define DDR_PHY_DX2GCR5_RESERVED_7_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR5_RESERVED_7_SHIFT 7 +#define DDR_PHY_DX2GCR5_RESERVED_7_MASK 0x00000080U -/*Byte Lane internal VREF Select for Rank 0*/ +/* +* Byte Lane internal VREF Select for Rank 0 +*/ #undef DDR_PHY_DX2GCR5_DXREFISELR0_DEFVAL #undef DDR_PHY_DX2GCR5_DXREFISELR0_SHIFT #undef DDR_PHY_DX2GCR5_DXREFISELR0_MASK -#define DDR_PHY_DX2GCR5_DXREFISELR0_DEFVAL 0x09090909 -#define DDR_PHY_DX2GCR5_DXREFISELR0_SHIFT 0 -#define DDR_PHY_DX2GCR5_DXREFISELR0_MASK 0x0000007FU +#define DDR_PHY_DX2GCR5_DXREFISELR0_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR5_DXREFISELR0_SHIFT 0 +#define DDR_PHY_DX2GCR5_DXREFISELR0_MASK 0x0000007FU -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX2GCR6_RESERVED_31_30_DEFVAL #undef DDR_PHY_DX2GCR6_RESERVED_31_30_SHIFT #undef DDR_PHY_DX2GCR6_RESERVED_31_30_MASK -#define DDR_PHY_DX2GCR6_RESERVED_31_30_DEFVAL 0x09090909 -#define DDR_PHY_DX2GCR6_RESERVED_31_30_SHIFT 30 -#define DDR_PHY_DX2GCR6_RESERVED_31_30_MASK 0xC0000000U +#define DDR_PHY_DX2GCR6_RESERVED_31_30_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR6_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX2GCR6_RESERVED_31_30_MASK 0xC0000000U -/*DRAM DQ VREF Select for Rank3*/ +/* +* DRAM DQ VREF Select for Rank3 +*/ #undef DDR_PHY_DX2GCR6_DXDQVREFR3_DEFVAL #undef DDR_PHY_DX2GCR6_DXDQVREFR3_SHIFT #undef DDR_PHY_DX2GCR6_DXDQVREFR3_MASK -#define DDR_PHY_DX2GCR6_DXDQVREFR3_DEFVAL 0x09090909 -#define DDR_PHY_DX2GCR6_DXDQVREFR3_SHIFT 24 -#define DDR_PHY_DX2GCR6_DXDQVREFR3_MASK 0x3F000000U +#define DDR_PHY_DX2GCR6_DXDQVREFR3_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR6_DXDQVREFR3_SHIFT 24 +#define DDR_PHY_DX2GCR6_DXDQVREFR3_MASK 0x3F000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX2GCR6_RESERVED_23_22_DEFVAL #undef DDR_PHY_DX2GCR6_RESERVED_23_22_SHIFT #undef DDR_PHY_DX2GCR6_RESERVED_23_22_MASK -#define DDR_PHY_DX2GCR6_RESERVED_23_22_DEFVAL 0x09090909 -#define DDR_PHY_DX2GCR6_RESERVED_23_22_SHIFT 22 -#define DDR_PHY_DX2GCR6_RESERVED_23_22_MASK 0x00C00000U +#define DDR_PHY_DX2GCR6_RESERVED_23_22_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR6_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX2GCR6_RESERVED_23_22_MASK 0x00C00000U -/*DRAM DQ VREF Select for Rank2*/ +/* +* DRAM DQ VREF Select for Rank2 +*/ #undef DDR_PHY_DX2GCR6_DXDQVREFR2_DEFVAL #undef DDR_PHY_DX2GCR6_DXDQVREFR2_SHIFT #undef DDR_PHY_DX2GCR6_DXDQVREFR2_MASK -#define DDR_PHY_DX2GCR6_DXDQVREFR2_DEFVAL 0x09090909 -#define DDR_PHY_DX2GCR6_DXDQVREFR2_SHIFT 16 -#define DDR_PHY_DX2GCR6_DXDQVREFR2_MASK 0x003F0000U +#define DDR_PHY_DX2GCR6_DXDQVREFR2_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR6_DXDQVREFR2_SHIFT 16 +#define DDR_PHY_DX2GCR6_DXDQVREFR2_MASK 0x003F0000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX2GCR6_RESERVED_15_14_DEFVAL #undef DDR_PHY_DX2GCR6_RESERVED_15_14_SHIFT #undef DDR_PHY_DX2GCR6_RESERVED_15_14_MASK -#define DDR_PHY_DX2GCR6_RESERVED_15_14_DEFVAL 0x09090909 -#define DDR_PHY_DX2GCR6_RESERVED_15_14_SHIFT 14 -#define DDR_PHY_DX2GCR6_RESERVED_15_14_MASK 0x0000C000U +#define DDR_PHY_DX2GCR6_RESERVED_15_14_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR6_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_DX2GCR6_RESERVED_15_14_MASK 0x0000C000U -/*DRAM DQ VREF Select for Rank1*/ +/* +* DRAM DQ VREF Select for Rank1 +*/ #undef DDR_PHY_DX2GCR6_DXDQVREFR1_DEFVAL #undef DDR_PHY_DX2GCR6_DXDQVREFR1_SHIFT #undef DDR_PHY_DX2GCR6_DXDQVREFR1_MASK -#define DDR_PHY_DX2GCR6_DXDQVREFR1_DEFVAL 0x09090909 -#define DDR_PHY_DX2GCR6_DXDQVREFR1_SHIFT 8 -#define DDR_PHY_DX2GCR6_DXDQVREFR1_MASK 0x00003F00U +#define DDR_PHY_DX2GCR6_DXDQVREFR1_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR6_DXDQVREFR1_SHIFT 8 +#define DDR_PHY_DX2GCR6_DXDQVREFR1_MASK 0x00003F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX2GCR6_RESERVED_7_6_DEFVAL #undef DDR_PHY_DX2GCR6_RESERVED_7_6_SHIFT #undef DDR_PHY_DX2GCR6_RESERVED_7_6_MASK -#define DDR_PHY_DX2GCR6_RESERVED_7_6_DEFVAL 0x09090909 -#define DDR_PHY_DX2GCR6_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_DX2GCR6_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_DX2GCR6_RESERVED_7_6_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR6_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX2GCR6_RESERVED_7_6_MASK 0x000000C0U -/*DRAM DQ VREF Select for Rank0*/ +/* +* DRAM DQ VREF Select for Rank0 +*/ #undef DDR_PHY_DX2GCR6_DXDQVREFR0_DEFVAL #undef DDR_PHY_DX2GCR6_DXDQVREFR0_SHIFT #undef DDR_PHY_DX2GCR6_DXDQVREFR0_MASK -#define DDR_PHY_DX2GCR6_DXDQVREFR0_DEFVAL 0x09090909 -#define DDR_PHY_DX2GCR6_DXDQVREFR0_SHIFT 0 -#define DDR_PHY_DX2GCR6_DXDQVREFR0_MASK 0x0000003FU +#define DDR_PHY_DX2GCR6_DXDQVREFR0_DEFVAL 0x09090909 +#define DDR_PHY_DX2GCR6_DXDQVREFR0_SHIFT 0 +#define DDR_PHY_DX2GCR6_DXDQVREFR0_MASK 0x0000003FU -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX2LCDLR2_RESERVED_31_25_DEFVAL -#undef DDR_PHY_DX2LCDLR2_RESERVED_31_25_SHIFT -#undef DDR_PHY_DX2LCDLR2_RESERVED_31_25_MASK -#define DDR_PHY_DX2LCDLR2_RESERVED_31_25_DEFVAL 0x00000000 -#define DDR_PHY_DX2LCDLR2_RESERVED_31_25_SHIFT 25 -#define DDR_PHY_DX2LCDLR2_RESERVED_31_25_MASK 0xFE000000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX2LCDLR2_RESERVED_24_16_DEFVAL -#undef DDR_PHY_DX2LCDLR2_RESERVED_24_16_SHIFT -#undef DDR_PHY_DX2LCDLR2_RESERVED_24_16_MASK -#define DDR_PHY_DX2LCDLR2_RESERVED_24_16_DEFVAL 0x00000000 -#define DDR_PHY_DX2LCDLR2_RESERVED_24_16_SHIFT 16 -#define DDR_PHY_DX2LCDLR2_RESERVED_24_16_MASK 0x01FF0000U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX2LCDLR2_RESERVED_15_9_DEFVAL -#undef DDR_PHY_DX2LCDLR2_RESERVED_15_9_SHIFT -#undef DDR_PHY_DX2LCDLR2_RESERVED_15_9_MASK -#define DDR_PHY_DX2LCDLR2_RESERVED_15_9_DEFVAL 0x00000000 -#define DDR_PHY_DX2LCDLR2_RESERVED_15_9_SHIFT 9 -#define DDR_PHY_DX2LCDLR2_RESERVED_15_9_MASK 0x0000FE00U - -/*Read DQS Gating Delay*/ -#undef DDR_PHY_DX2LCDLR2_DQSGD_DEFVAL -#undef DDR_PHY_DX2LCDLR2_DQSGD_SHIFT -#undef DDR_PHY_DX2LCDLR2_DQSGD_MASK -#define DDR_PHY_DX2LCDLR2_DQSGD_DEFVAL 0x00000000 -#define DDR_PHY_DX2LCDLR2_DQSGD_SHIFT 0 -#define DDR_PHY_DX2LCDLR2_DQSGD_MASK 0x000001FFU - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX2GTR0_RESERVED_31_24_DEFVAL -#undef DDR_PHY_DX2GTR0_RESERVED_31_24_SHIFT -#undef DDR_PHY_DX2GTR0_RESERVED_31_24_MASK -#define DDR_PHY_DX2GTR0_RESERVED_31_24_DEFVAL 0x00020000 -#define DDR_PHY_DX2GTR0_RESERVED_31_24_SHIFT 27 -#define DDR_PHY_DX2GTR0_RESERVED_31_24_MASK 0xF8000000U - -/*DQ Write Path Latency Pipeline*/ -#undef DDR_PHY_DX2GTR0_WDQSL_DEFVAL -#undef DDR_PHY_DX2GTR0_WDQSL_SHIFT -#undef DDR_PHY_DX2GTR0_WDQSL_MASK -#define DDR_PHY_DX2GTR0_WDQSL_DEFVAL 0x00020000 -#define DDR_PHY_DX2GTR0_WDQSL_SHIFT 24 -#define DDR_PHY_DX2GTR0_WDQSL_MASK 0x07000000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX2GTR0_RESERVED_23_20_DEFVAL -#undef DDR_PHY_DX2GTR0_RESERVED_23_20_SHIFT -#undef DDR_PHY_DX2GTR0_RESERVED_23_20_MASK -#define DDR_PHY_DX2GTR0_RESERVED_23_20_DEFVAL 0x00020000 -#define DDR_PHY_DX2GTR0_RESERVED_23_20_SHIFT 20 -#define DDR_PHY_DX2GTR0_RESERVED_23_20_MASK 0x00F00000U - -/*Write Leveling System Latency*/ -#undef DDR_PHY_DX2GTR0_WLSL_DEFVAL -#undef DDR_PHY_DX2GTR0_WLSL_SHIFT -#undef DDR_PHY_DX2GTR0_WLSL_MASK -#define DDR_PHY_DX2GTR0_WLSL_DEFVAL 0x00020000 -#define DDR_PHY_DX2GTR0_WLSL_SHIFT 16 -#define DDR_PHY_DX2GTR0_WLSL_MASK 0x000F0000U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX2GTR0_RESERVED_15_13_DEFVAL -#undef DDR_PHY_DX2GTR0_RESERVED_15_13_SHIFT -#undef DDR_PHY_DX2GTR0_RESERVED_15_13_MASK -#define DDR_PHY_DX2GTR0_RESERVED_15_13_DEFVAL 0x00020000 -#define DDR_PHY_DX2GTR0_RESERVED_15_13_SHIFT 13 -#define DDR_PHY_DX2GTR0_RESERVED_15_13_MASK 0x0000E000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX2GTR0_RESERVED_12_8_DEFVAL -#undef DDR_PHY_DX2GTR0_RESERVED_12_8_SHIFT -#undef DDR_PHY_DX2GTR0_RESERVED_12_8_MASK -#define DDR_PHY_DX2GTR0_RESERVED_12_8_DEFVAL 0x00020000 -#define DDR_PHY_DX2GTR0_RESERVED_12_8_SHIFT 8 -#define DDR_PHY_DX2GTR0_RESERVED_12_8_MASK 0x00001F00U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX2GTR0_RESERVED_7_5_DEFVAL -#undef DDR_PHY_DX2GTR0_RESERVED_7_5_SHIFT -#undef DDR_PHY_DX2GTR0_RESERVED_7_5_MASK -#define DDR_PHY_DX2GTR0_RESERVED_7_5_DEFVAL 0x00020000 -#define DDR_PHY_DX2GTR0_RESERVED_7_5_SHIFT 5 -#define DDR_PHY_DX2GTR0_RESERVED_7_5_MASK 0x000000E0U - -/*DQS Gating System Latency*/ -#undef DDR_PHY_DX2GTR0_DGSL_DEFVAL -#undef DDR_PHY_DX2GTR0_DGSL_SHIFT -#undef DDR_PHY_DX2GTR0_DGSL_MASK -#define DDR_PHY_DX2GTR0_DGSL_DEFVAL 0x00020000 -#define DDR_PHY_DX2GTR0_DGSL_SHIFT 0 -#define DDR_PHY_DX2GTR0_DGSL_MASK 0x0000001FU - -/*Calibration Bypass*/ +/* +* Calibration Bypass +*/ #undef DDR_PHY_DX3GCR0_CALBYP_DEFVAL #undef DDR_PHY_DX3GCR0_CALBYP_SHIFT #undef DDR_PHY_DX3GCR0_CALBYP_MASK -#define DDR_PHY_DX3GCR0_CALBYP_DEFVAL 0x40200204 -#define DDR_PHY_DX3GCR0_CALBYP_SHIFT 31 -#define DDR_PHY_DX3GCR0_CALBYP_MASK 0x80000000U +#define DDR_PHY_DX3GCR0_CALBYP_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_CALBYP_SHIFT 31 +#define DDR_PHY_DX3GCR0_CALBYP_MASK 0x80000000U -/*Master Delay Line Enable*/ +/* +* Master Delay Line Enable +*/ #undef DDR_PHY_DX3GCR0_MDLEN_DEFVAL #undef DDR_PHY_DX3GCR0_MDLEN_SHIFT #undef DDR_PHY_DX3GCR0_MDLEN_MASK -#define DDR_PHY_DX3GCR0_MDLEN_DEFVAL 0x40200204 -#define DDR_PHY_DX3GCR0_MDLEN_SHIFT 30 -#define DDR_PHY_DX3GCR0_MDLEN_MASK 0x40000000U +#define DDR_PHY_DX3GCR0_MDLEN_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_MDLEN_SHIFT 30 +#define DDR_PHY_DX3GCR0_MDLEN_MASK 0x40000000U -/*Configurable ODT(TE) Phase Shift*/ +/* +* Configurable ODT(TE) Phase Shift +*/ #undef DDR_PHY_DX3GCR0_CODTSHFT_DEFVAL #undef DDR_PHY_DX3GCR0_CODTSHFT_SHIFT #undef DDR_PHY_DX3GCR0_CODTSHFT_MASK -#define DDR_PHY_DX3GCR0_CODTSHFT_DEFVAL 0x40200204 -#define DDR_PHY_DX3GCR0_CODTSHFT_SHIFT 28 -#define DDR_PHY_DX3GCR0_CODTSHFT_MASK 0x30000000U +#define DDR_PHY_DX3GCR0_CODTSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_CODTSHFT_SHIFT 28 +#define DDR_PHY_DX3GCR0_CODTSHFT_MASK 0x30000000U -/*DQS Duty Cycle Correction*/ +/* +* DQS Duty Cycle Correction +*/ #undef DDR_PHY_DX3GCR0_DQSDCC_DEFVAL #undef DDR_PHY_DX3GCR0_DQSDCC_SHIFT #undef DDR_PHY_DX3GCR0_DQSDCC_MASK -#define DDR_PHY_DX3GCR0_DQSDCC_DEFVAL 0x40200204 -#define DDR_PHY_DX3GCR0_DQSDCC_SHIFT 24 -#define DDR_PHY_DX3GCR0_DQSDCC_MASK 0x0F000000U +#define DDR_PHY_DX3GCR0_DQSDCC_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_DQSDCC_SHIFT 24 +#define DDR_PHY_DX3GCR0_DQSDCC_MASK 0x0F000000U -/*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/ +/* +* Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY +*/ #undef DDR_PHY_DX3GCR0_RDDLY_DEFVAL #undef DDR_PHY_DX3GCR0_RDDLY_SHIFT #undef DDR_PHY_DX3GCR0_RDDLY_MASK -#define DDR_PHY_DX3GCR0_RDDLY_DEFVAL 0x40200204 -#define DDR_PHY_DX3GCR0_RDDLY_SHIFT 20 -#define DDR_PHY_DX3GCR0_RDDLY_MASK 0x00F00000U +#define DDR_PHY_DX3GCR0_RDDLY_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_RDDLY_SHIFT 20 +#define DDR_PHY_DX3GCR0_RDDLY_MASK 0x00F00000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX3GCR0_RESERVED_19_14_DEFVAL #undef DDR_PHY_DX3GCR0_RESERVED_19_14_SHIFT #undef DDR_PHY_DX3GCR0_RESERVED_19_14_MASK -#define DDR_PHY_DX3GCR0_RESERVED_19_14_DEFVAL 0x40200204 -#define DDR_PHY_DX3GCR0_RESERVED_19_14_SHIFT 14 -#define DDR_PHY_DX3GCR0_RESERVED_19_14_MASK 0x000FC000U +#define DDR_PHY_DX3GCR0_RESERVED_19_14_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_RESERVED_19_14_SHIFT 14 +#define DDR_PHY_DX3GCR0_RESERVED_19_14_MASK 0x000FC000U -/*DQSNSE Power Down Receiver*/ +/* +* DQSNSE Power Down Receiver +*/ #undef DDR_PHY_DX3GCR0_DQSNSEPDR_DEFVAL #undef DDR_PHY_DX3GCR0_DQSNSEPDR_SHIFT #undef DDR_PHY_DX3GCR0_DQSNSEPDR_MASK -#define DDR_PHY_DX3GCR0_DQSNSEPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX3GCR0_DQSNSEPDR_SHIFT 13 -#define DDR_PHY_DX3GCR0_DQSNSEPDR_MASK 0x00002000U +#define DDR_PHY_DX3GCR0_DQSNSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_DQSNSEPDR_SHIFT 13 +#define DDR_PHY_DX3GCR0_DQSNSEPDR_MASK 0x00002000U -/*DQSSE Power Down Receiver*/ +/* +* DQSSE Power Down Receiver +*/ #undef DDR_PHY_DX3GCR0_DQSSEPDR_DEFVAL #undef DDR_PHY_DX3GCR0_DQSSEPDR_SHIFT #undef DDR_PHY_DX3GCR0_DQSSEPDR_MASK -#define DDR_PHY_DX3GCR0_DQSSEPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX3GCR0_DQSSEPDR_SHIFT 12 -#define DDR_PHY_DX3GCR0_DQSSEPDR_MASK 0x00001000U +#define DDR_PHY_DX3GCR0_DQSSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_DQSSEPDR_SHIFT 12 +#define DDR_PHY_DX3GCR0_DQSSEPDR_MASK 0x00001000U -/*RTT On Additive Latency*/ +/* +* RTT On Additive Latency +*/ #undef DDR_PHY_DX3GCR0_RTTOAL_DEFVAL #undef DDR_PHY_DX3GCR0_RTTOAL_SHIFT #undef DDR_PHY_DX3GCR0_RTTOAL_MASK -#define DDR_PHY_DX3GCR0_RTTOAL_DEFVAL 0x40200204 -#define DDR_PHY_DX3GCR0_RTTOAL_SHIFT 11 -#define DDR_PHY_DX3GCR0_RTTOAL_MASK 0x00000800U +#define DDR_PHY_DX3GCR0_RTTOAL_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_RTTOAL_SHIFT 11 +#define DDR_PHY_DX3GCR0_RTTOAL_MASK 0x00000800U -/*RTT Output Hold*/ +/* +* RTT Output Hold +*/ #undef DDR_PHY_DX3GCR0_RTTOH_DEFVAL #undef DDR_PHY_DX3GCR0_RTTOH_SHIFT #undef DDR_PHY_DX3GCR0_RTTOH_MASK -#define DDR_PHY_DX3GCR0_RTTOH_DEFVAL 0x40200204 -#define DDR_PHY_DX3GCR0_RTTOH_SHIFT 9 -#define DDR_PHY_DX3GCR0_RTTOH_MASK 0x00000600U +#define DDR_PHY_DX3GCR0_RTTOH_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_RTTOH_SHIFT 9 +#define DDR_PHY_DX3GCR0_RTTOH_MASK 0x00000600U -/*Configurable PDR Phase Shift*/ +/* +* Configurable PDR Phase Shift +*/ #undef DDR_PHY_DX3GCR0_CPDRSHFT_DEFVAL #undef DDR_PHY_DX3GCR0_CPDRSHFT_SHIFT #undef DDR_PHY_DX3GCR0_CPDRSHFT_MASK -#define DDR_PHY_DX3GCR0_CPDRSHFT_DEFVAL 0x40200204 -#define DDR_PHY_DX3GCR0_CPDRSHFT_SHIFT 7 -#define DDR_PHY_DX3GCR0_CPDRSHFT_MASK 0x00000180U +#define DDR_PHY_DX3GCR0_CPDRSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_CPDRSHFT_SHIFT 7 +#define DDR_PHY_DX3GCR0_CPDRSHFT_MASK 0x00000180U -/*DQSR Power Down*/ +/* +* DQSR Power Down +*/ #undef DDR_PHY_DX3GCR0_DQSRPD_DEFVAL #undef DDR_PHY_DX3GCR0_DQSRPD_SHIFT #undef DDR_PHY_DX3GCR0_DQSRPD_MASK -#define DDR_PHY_DX3GCR0_DQSRPD_DEFVAL 0x40200204 -#define DDR_PHY_DX3GCR0_DQSRPD_SHIFT 6 -#define DDR_PHY_DX3GCR0_DQSRPD_MASK 0x00000040U +#define DDR_PHY_DX3GCR0_DQSRPD_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_DQSRPD_SHIFT 6 +#define DDR_PHY_DX3GCR0_DQSRPD_MASK 0x00000040U -/*DQSG Power Down Receiver*/ +/* +* DQSG Power Down Receiver +*/ #undef DDR_PHY_DX3GCR0_DQSGPDR_DEFVAL #undef DDR_PHY_DX3GCR0_DQSGPDR_SHIFT #undef DDR_PHY_DX3GCR0_DQSGPDR_MASK -#define DDR_PHY_DX3GCR0_DQSGPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX3GCR0_DQSGPDR_SHIFT 5 -#define DDR_PHY_DX3GCR0_DQSGPDR_MASK 0x00000020U +#define DDR_PHY_DX3GCR0_DQSGPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_DQSGPDR_SHIFT 5 +#define DDR_PHY_DX3GCR0_DQSGPDR_MASK 0x00000020U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX3GCR0_RESERVED_4_DEFVAL #undef DDR_PHY_DX3GCR0_RESERVED_4_SHIFT #undef DDR_PHY_DX3GCR0_RESERVED_4_MASK -#define DDR_PHY_DX3GCR0_RESERVED_4_DEFVAL 0x40200204 -#define DDR_PHY_DX3GCR0_RESERVED_4_SHIFT 4 -#define DDR_PHY_DX3GCR0_RESERVED_4_MASK 0x00000010U +#define DDR_PHY_DX3GCR0_RESERVED_4_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_RESERVED_4_SHIFT 4 +#define DDR_PHY_DX3GCR0_RESERVED_4_MASK 0x00000010U -/*DQSG On-Die Termination*/ +/* +* DQSG On-Die Termination +*/ #undef DDR_PHY_DX3GCR0_DQSGODT_DEFVAL #undef DDR_PHY_DX3GCR0_DQSGODT_SHIFT #undef DDR_PHY_DX3GCR0_DQSGODT_MASK -#define DDR_PHY_DX3GCR0_DQSGODT_DEFVAL 0x40200204 -#define DDR_PHY_DX3GCR0_DQSGODT_SHIFT 3 -#define DDR_PHY_DX3GCR0_DQSGODT_MASK 0x00000008U +#define DDR_PHY_DX3GCR0_DQSGODT_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_DQSGODT_SHIFT 3 +#define DDR_PHY_DX3GCR0_DQSGODT_MASK 0x00000008U -/*DQSG Output Enable*/ +/* +* DQSG Output Enable +*/ #undef DDR_PHY_DX3GCR0_DQSGOE_DEFVAL #undef DDR_PHY_DX3GCR0_DQSGOE_SHIFT #undef DDR_PHY_DX3GCR0_DQSGOE_MASK -#define DDR_PHY_DX3GCR0_DQSGOE_DEFVAL 0x40200204 -#define DDR_PHY_DX3GCR0_DQSGOE_SHIFT 2 -#define DDR_PHY_DX3GCR0_DQSGOE_MASK 0x00000004U +#define DDR_PHY_DX3GCR0_DQSGOE_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_DQSGOE_SHIFT 2 +#define DDR_PHY_DX3GCR0_DQSGOE_MASK 0x00000004U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX3GCR0_RESERVED_1_0_DEFVAL #undef DDR_PHY_DX3GCR0_RESERVED_1_0_SHIFT #undef DDR_PHY_DX3GCR0_RESERVED_1_0_MASK -#define DDR_PHY_DX3GCR0_RESERVED_1_0_DEFVAL 0x40200204 -#define DDR_PHY_DX3GCR0_RESERVED_1_0_SHIFT 0 -#define DDR_PHY_DX3GCR0_RESERVED_1_0_MASK 0x00000003U +#define DDR_PHY_DX3GCR0_RESERVED_1_0_DEFVAL 0x40200204 +#define DDR_PHY_DX3GCR0_RESERVED_1_0_SHIFT 0 +#define DDR_PHY_DX3GCR0_RESERVED_1_0_MASK 0x00000003U -/*Enables the PDR mode for DQ[7:0]*/ +/* +* Enables the PDR mode for DQ[7:0] +*/ #undef DDR_PHY_DX3GCR1_DXPDRMODE_DEFVAL #undef DDR_PHY_DX3GCR1_DXPDRMODE_SHIFT #undef DDR_PHY_DX3GCR1_DXPDRMODE_MASK -#define DDR_PHY_DX3GCR1_DXPDRMODE_DEFVAL 0x00007FFF -#define DDR_PHY_DX3GCR1_DXPDRMODE_SHIFT 16 -#define DDR_PHY_DX3GCR1_DXPDRMODE_MASK 0xFFFF0000U +#define DDR_PHY_DX3GCR1_DXPDRMODE_DEFVAL 0x00007FFF +#define DDR_PHY_DX3GCR1_DXPDRMODE_SHIFT 16 +#define DDR_PHY_DX3GCR1_DXPDRMODE_MASK 0xFFFF0000U -/*Reserved. Returns zeroes on reads.*/ +/* +* Reserved. Returns zeroes on reads. +*/ #undef DDR_PHY_DX3GCR1_RESERVED_15_DEFVAL #undef DDR_PHY_DX3GCR1_RESERVED_15_SHIFT #undef DDR_PHY_DX3GCR1_RESERVED_15_MASK -#define DDR_PHY_DX3GCR1_RESERVED_15_DEFVAL 0x00007FFF -#define DDR_PHY_DX3GCR1_RESERVED_15_SHIFT 15 -#define DDR_PHY_DX3GCR1_RESERVED_15_MASK 0x00008000U +#define DDR_PHY_DX3GCR1_RESERVED_15_DEFVAL 0x00007FFF +#define DDR_PHY_DX3GCR1_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX3GCR1_RESERVED_15_MASK 0x00008000U -/*Select the delayed or non-delayed read data strobe #*/ +/* +* Select the delayed or non-delayed read data strobe # +*/ #undef DDR_PHY_DX3GCR1_QSNSEL_DEFVAL #undef DDR_PHY_DX3GCR1_QSNSEL_SHIFT #undef DDR_PHY_DX3GCR1_QSNSEL_MASK -#define DDR_PHY_DX3GCR1_QSNSEL_DEFVAL 0x00007FFF -#define DDR_PHY_DX3GCR1_QSNSEL_SHIFT 14 -#define DDR_PHY_DX3GCR1_QSNSEL_MASK 0x00004000U +#define DDR_PHY_DX3GCR1_QSNSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX3GCR1_QSNSEL_SHIFT 14 +#define DDR_PHY_DX3GCR1_QSNSEL_MASK 0x00004000U -/*Select the delayed or non-delayed read data strobe*/ +/* +* Select the delayed or non-delayed read data strobe +*/ #undef DDR_PHY_DX3GCR1_QSSEL_DEFVAL #undef DDR_PHY_DX3GCR1_QSSEL_SHIFT #undef DDR_PHY_DX3GCR1_QSSEL_MASK -#define DDR_PHY_DX3GCR1_QSSEL_DEFVAL 0x00007FFF -#define DDR_PHY_DX3GCR1_QSSEL_SHIFT 13 -#define DDR_PHY_DX3GCR1_QSSEL_MASK 0x00002000U +#define DDR_PHY_DX3GCR1_QSSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX3GCR1_QSSEL_SHIFT 13 +#define DDR_PHY_DX3GCR1_QSSEL_MASK 0x00002000U -/*Enables Read Data Strobe in a byte lane*/ +/* +* Enables Read Data Strobe in a byte lane +*/ #undef DDR_PHY_DX3GCR1_OEEN_DEFVAL #undef DDR_PHY_DX3GCR1_OEEN_SHIFT #undef DDR_PHY_DX3GCR1_OEEN_MASK -#define DDR_PHY_DX3GCR1_OEEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX3GCR1_OEEN_SHIFT 12 -#define DDR_PHY_DX3GCR1_OEEN_MASK 0x00001000U +#define DDR_PHY_DX3GCR1_OEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX3GCR1_OEEN_SHIFT 12 +#define DDR_PHY_DX3GCR1_OEEN_MASK 0x00001000U -/*Enables PDR in a byte lane*/ +/* +* Enables PDR in a byte lane +*/ #undef DDR_PHY_DX3GCR1_PDREN_DEFVAL #undef DDR_PHY_DX3GCR1_PDREN_SHIFT #undef DDR_PHY_DX3GCR1_PDREN_MASK -#define DDR_PHY_DX3GCR1_PDREN_DEFVAL 0x00007FFF -#define DDR_PHY_DX3GCR1_PDREN_SHIFT 11 -#define DDR_PHY_DX3GCR1_PDREN_MASK 0x00000800U +#define DDR_PHY_DX3GCR1_PDREN_DEFVAL 0x00007FFF +#define DDR_PHY_DX3GCR1_PDREN_SHIFT 11 +#define DDR_PHY_DX3GCR1_PDREN_MASK 0x00000800U -/*Enables ODT/TE in a byte lane*/ +/* +* Enables ODT/TE in a byte lane +*/ #undef DDR_PHY_DX3GCR1_TEEN_DEFVAL #undef DDR_PHY_DX3GCR1_TEEN_SHIFT #undef DDR_PHY_DX3GCR1_TEEN_MASK -#define DDR_PHY_DX3GCR1_TEEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX3GCR1_TEEN_SHIFT 10 -#define DDR_PHY_DX3GCR1_TEEN_MASK 0x00000400U +#define DDR_PHY_DX3GCR1_TEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX3GCR1_TEEN_SHIFT 10 +#define DDR_PHY_DX3GCR1_TEEN_MASK 0x00000400U -/*Enables Write Data strobe in a byte lane*/ +/* +* Enables Write Data strobe in a byte lane +*/ #undef DDR_PHY_DX3GCR1_DSEN_DEFVAL #undef DDR_PHY_DX3GCR1_DSEN_SHIFT #undef DDR_PHY_DX3GCR1_DSEN_MASK -#define DDR_PHY_DX3GCR1_DSEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX3GCR1_DSEN_SHIFT 9 -#define DDR_PHY_DX3GCR1_DSEN_MASK 0x00000200U +#define DDR_PHY_DX3GCR1_DSEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX3GCR1_DSEN_SHIFT 9 +#define DDR_PHY_DX3GCR1_DSEN_MASK 0x00000200U -/*Enables DM pin in a byte lane*/ +/* +* Enables DM pin in a byte lane +*/ #undef DDR_PHY_DX3GCR1_DMEN_DEFVAL #undef DDR_PHY_DX3GCR1_DMEN_SHIFT #undef DDR_PHY_DX3GCR1_DMEN_MASK -#define DDR_PHY_DX3GCR1_DMEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX3GCR1_DMEN_SHIFT 8 -#define DDR_PHY_DX3GCR1_DMEN_MASK 0x00000100U +#define DDR_PHY_DX3GCR1_DMEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX3GCR1_DMEN_SHIFT 8 +#define DDR_PHY_DX3GCR1_DMEN_MASK 0x00000100U -/*Enables DQ corresponding to each bit in a byte*/ +/* +* Enables DQ corresponding to each bit in a byte +*/ #undef DDR_PHY_DX3GCR1_DQEN_DEFVAL #undef DDR_PHY_DX3GCR1_DQEN_SHIFT #undef DDR_PHY_DX3GCR1_DQEN_MASK -#define DDR_PHY_DX3GCR1_DQEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX3GCR1_DQEN_SHIFT 0 -#define DDR_PHY_DX3GCR1_DQEN_MASK 0x000000FFU +#define DDR_PHY_DX3GCR1_DQEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX3GCR1_DQEN_SHIFT 0 +#define DDR_PHY_DX3GCR1_DQEN_MASK 0x000000FFU -/*Byte lane VREF IOM (Used only by D4MU IOs)*/ +/* +* Byte lane VREF IOM (Used only by D4MU IOs) +*/ #undef DDR_PHY_DX3GCR4_RESERVED_31_29_DEFVAL #undef DDR_PHY_DX3GCR4_RESERVED_31_29_SHIFT #undef DDR_PHY_DX3GCR4_RESERVED_31_29_MASK -#define DDR_PHY_DX3GCR4_RESERVED_31_29_DEFVAL 0x0E00003C -#define DDR_PHY_DX3GCR4_RESERVED_31_29_SHIFT 29 -#define DDR_PHY_DX3GCR4_RESERVED_31_29_MASK 0xE0000000U +#define DDR_PHY_DX3GCR4_RESERVED_31_29_DEFVAL 0x0E00003C +#define DDR_PHY_DX3GCR4_RESERVED_31_29_SHIFT 29 +#define DDR_PHY_DX3GCR4_RESERVED_31_29_MASK 0xE0000000U -/*Byte Lane VREF Pad Enable*/ +/* +* Byte Lane VREF Pad Enable +*/ #undef DDR_PHY_DX3GCR4_DXREFPEN_DEFVAL #undef DDR_PHY_DX3GCR4_DXREFPEN_SHIFT #undef DDR_PHY_DX3GCR4_DXREFPEN_MASK -#define DDR_PHY_DX3GCR4_DXREFPEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX3GCR4_DXREFPEN_SHIFT 28 -#define DDR_PHY_DX3GCR4_DXREFPEN_MASK 0x10000000U +#define DDR_PHY_DX3GCR4_DXREFPEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX3GCR4_DXREFPEN_SHIFT 28 +#define DDR_PHY_DX3GCR4_DXREFPEN_MASK 0x10000000U -/*Byte Lane Internal VREF Enable*/ +/* +* Byte Lane Internal VREF Enable +*/ #undef DDR_PHY_DX3GCR4_DXREFEEN_DEFVAL #undef DDR_PHY_DX3GCR4_DXREFEEN_SHIFT #undef DDR_PHY_DX3GCR4_DXREFEEN_MASK -#define DDR_PHY_DX3GCR4_DXREFEEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX3GCR4_DXREFEEN_SHIFT 26 -#define DDR_PHY_DX3GCR4_DXREFEEN_MASK 0x0C000000U +#define DDR_PHY_DX3GCR4_DXREFEEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX3GCR4_DXREFEEN_SHIFT 26 +#define DDR_PHY_DX3GCR4_DXREFEEN_MASK 0x0C000000U -/*Byte Lane Single-End VREF Enable*/ +/* +* Byte Lane Single-End VREF Enable +*/ #undef DDR_PHY_DX3GCR4_DXREFSEN_DEFVAL #undef DDR_PHY_DX3GCR4_DXREFSEN_SHIFT #undef DDR_PHY_DX3GCR4_DXREFSEN_MASK -#define DDR_PHY_DX3GCR4_DXREFSEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX3GCR4_DXREFSEN_SHIFT 25 -#define DDR_PHY_DX3GCR4_DXREFSEN_MASK 0x02000000U +#define DDR_PHY_DX3GCR4_DXREFSEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX3GCR4_DXREFSEN_SHIFT 25 +#define DDR_PHY_DX3GCR4_DXREFSEN_MASK 0x02000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX3GCR4_RESERVED_24_DEFVAL #undef DDR_PHY_DX3GCR4_RESERVED_24_SHIFT #undef DDR_PHY_DX3GCR4_RESERVED_24_MASK -#define DDR_PHY_DX3GCR4_RESERVED_24_DEFVAL 0x0E00003C -#define DDR_PHY_DX3GCR4_RESERVED_24_SHIFT 24 -#define DDR_PHY_DX3GCR4_RESERVED_24_MASK 0x01000000U +#define DDR_PHY_DX3GCR4_RESERVED_24_DEFVAL 0x0E00003C +#define DDR_PHY_DX3GCR4_RESERVED_24_SHIFT 24 +#define DDR_PHY_DX3GCR4_RESERVED_24_MASK 0x01000000U -/*External VREF generator REFSEL range select*/ +/* +* External VREF generator REFSEL range select +*/ #undef DDR_PHY_DX3GCR4_DXREFESELRANGE_DEFVAL #undef DDR_PHY_DX3GCR4_DXREFESELRANGE_SHIFT #undef DDR_PHY_DX3GCR4_DXREFESELRANGE_MASK -#define DDR_PHY_DX3GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C -#define DDR_PHY_DX3GCR4_DXREFESELRANGE_SHIFT 23 -#define DDR_PHY_DX3GCR4_DXREFESELRANGE_MASK 0x00800000U +#define DDR_PHY_DX3GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX3GCR4_DXREFESELRANGE_SHIFT 23 +#define DDR_PHY_DX3GCR4_DXREFESELRANGE_MASK 0x00800000U -/*Byte Lane External VREF Select*/ +/* +* Byte Lane External VREF Select +*/ #undef DDR_PHY_DX3GCR4_DXREFESEL_DEFVAL #undef DDR_PHY_DX3GCR4_DXREFESEL_SHIFT #undef DDR_PHY_DX3GCR4_DXREFESEL_MASK -#define DDR_PHY_DX3GCR4_DXREFESEL_DEFVAL 0x0E00003C -#define DDR_PHY_DX3GCR4_DXREFESEL_SHIFT 16 -#define DDR_PHY_DX3GCR4_DXREFESEL_MASK 0x007F0000U +#define DDR_PHY_DX3GCR4_DXREFESEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX3GCR4_DXREFESEL_SHIFT 16 +#define DDR_PHY_DX3GCR4_DXREFESEL_MASK 0x007F0000U -/*Single ended VREF generator REFSEL range select*/ +/* +* Single ended VREF generator REFSEL range select +*/ #undef DDR_PHY_DX3GCR4_DXREFSSELRANGE_DEFVAL #undef DDR_PHY_DX3GCR4_DXREFSSELRANGE_SHIFT #undef DDR_PHY_DX3GCR4_DXREFSSELRANGE_MASK -#define DDR_PHY_DX3GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C -#define DDR_PHY_DX3GCR4_DXREFSSELRANGE_SHIFT 15 -#define DDR_PHY_DX3GCR4_DXREFSSELRANGE_MASK 0x00008000U +#define DDR_PHY_DX3GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX3GCR4_DXREFSSELRANGE_SHIFT 15 +#define DDR_PHY_DX3GCR4_DXREFSSELRANGE_MASK 0x00008000U -/*Byte Lane Single-End VREF Select*/ +/* +* Byte Lane Single-End VREF Select +*/ #undef DDR_PHY_DX3GCR4_DXREFSSEL_DEFVAL #undef DDR_PHY_DX3GCR4_DXREFSSEL_SHIFT #undef DDR_PHY_DX3GCR4_DXREFSSEL_MASK -#define DDR_PHY_DX3GCR4_DXREFSSEL_DEFVAL 0x0E00003C -#define DDR_PHY_DX3GCR4_DXREFSSEL_SHIFT 8 -#define DDR_PHY_DX3GCR4_DXREFSSEL_MASK 0x00007F00U +#define DDR_PHY_DX3GCR4_DXREFSSEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX3GCR4_DXREFSSEL_SHIFT 8 +#define DDR_PHY_DX3GCR4_DXREFSSEL_MASK 0x00007F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX3GCR4_RESERVED_7_6_DEFVAL #undef DDR_PHY_DX3GCR4_RESERVED_7_6_SHIFT #undef DDR_PHY_DX3GCR4_RESERVED_7_6_MASK -#define DDR_PHY_DX3GCR4_RESERVED_7_6_DEFVAL 0x0E00003C -#define DDR_PHY_DX3GCR4_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_DX3GCR4_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_DX3GCR4_RESERVED_7_6_DEFVAL 0x0E00003C +#define DDR_PHY_DX3GCR4_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX3GCR4_RESERVED_7_6_MASK 0x000000C0U -/*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/ +/* +* VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. +*/ #undef DDR_PHY_DX3GCR4_DXREFIEN_DEFVAL #undef DDR_PHY_DX3GCR4_DXREFIEN_SHIFT #undef DDR_PHY_DX3GCR4_DXREFIEN_MASK -#define DDR_PHY_DX3GCR4_DXREFIEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX3GCR4_DXREFIEN_SHIFT 2 -#define DDR_PHY_DX3GCR4_DXREFIEN_MASK 0x0000003CU +#define DDR_PHY_DX3GCR4_DXREFIEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX3GCR4_DXREFIEN_SHIFT 2 +#define DDR_PHY_DX3GCR4_DXREFIEN_MASK 0x0000003CU -/*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/ +/* +* VRMON control for DQ IO (Single Ended) buffers of a byte lane. +*/ #undef DDR_PHY_DX3GCR4_DXREFIMON_DEFVAL #undef DDR_PHY_DX3GCR4_DXREFIMON_SHIFT #undef DDR_PHY_DX3GCR4_DXREFIMON_MASK -#define DDR_PHY_DX3GCR4_DXREFIMON_DEFVAL 0x0E00003C -#define DDR_PHY_DX3GCR4_DXREFIMON_SHIFT 0 -#define DDR_PHY_DX3GCR4_DXREFIMON_MASK 0x00000003U +#define DDR_PHY_DX3GCR4_DXREFIMON_DEFVAL 0x0E00003C +#define DDR_PHY_DX3GCR4_DXREFIMON_SHIFT 0 +#define DDR_PHY_DX3GCR4_DXREFIMON_MASK 0x00000003U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX3GCR5_RESERVED_31_DEFVAL #undef DDR_PHY_DX3GCR5_RESERVED_31_SHIFT #undef DDR_PHY_DX3GCR5_RESERVED_31_MASK -#define DDR_PHY_DX3GCR5_RESERVED_31_DEFVAL 0x09090909 -#define DDR_PHY_DX3GCR5_RESERVED_31_SHIFT 31 -#define DDR_PHY_DX3GCR5_RESERVED_31_MASK 0x80000000U +#define DDR_PHY_DX3GCR5_RESERVED_31_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR5_RESERVED_31_SHIFT 31 +#define DDR_PHY_DX3GCR5_RESERVED_31_MASK 0x80000000U -/*Byte Lane internal VREF Select for Rank 3*/ +/* +* Byte Lane internal VREF Select for Rank 3 +*/ #undef DDR_PHY_DX3GCR5_DXREFISELR3_DEFVAL #undef DDR_PHY_DX3GCR5_DXREFISELR3_SHIFT #undef DDR_PHY_DX3GCR5_DXREFISELR3_MASK -#define DDR_PHY_DX3GCR5_DXREFISELR3_DEFVAL 0x09090909 -#define DDR_PHY_DX3GCR5_DXREFISELR3_SHIFT 24 -#define DDR_PHY_DX3GCR5_DXREFISELR3_MASK 0x7F000000U +#define DDR_PHY_DX3GCR5_DXREFISELR3_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR5_DXREFISELR3_SHIFT 24 +#define DDR_PHY_DX3GCR5_DXREFISELR3_MASK 0x7F000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX3GCR5_RESERVED_23_DEFVAL #undef DDR_PHY_DX3GCR5_RESERVED_23_SHIFT #undef DDR_PHY_DX3GCR5_RESERVED_23_MASK -#define DDR_PHY_DX3GCR5_RESERVED_23_DEFVAL 0x09090909 -#define DDR_PHY_DX3GCR5_RESERVED_23_SHIFT 23 -#define DDR_PHY_DX3GCR5_RESERVED_23_MASK 0x00800000U +#define DDR_PHY_DX3GCR5_RESERVED_23_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR5_RESERVED_23_SHIFT 23 +#define DDR_PHY_DX3GCR5_RESERVED_23_MASK 0x00800000U -/*Byte Lane internal VREF Select for Rank 2*/ +/* +* Byte Lane internal VREF Select for Rank 2 +*/ #undef DDR_PHY_DX3GCR5_DXREFISELR2_DEFVAL #undef DDR_PHY_DX3GCR5_DXREFISELR2_SHIFT #undef DDR_PHY_DX3GCR5_DXREFISELR2_MASK -#define DDR_PHY_DX3GCR5_DXREFISELR2_DEFVAL 0x09090909 -#define DDR_PHY_DX3GCR5_DXREFISELR2_SHIFT 16 -#define DDR_PHY_DX3GCR5_DXREFISELR2_MASK 0x007F0000U +#define DDR_PHY_DX3GCR5_DXREFISELR2_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR5_DXREFISELR2_SHIFT 16 +#define DDR_PHY_DX3GCR5_DXREFISELR2_MASK 0x007F0000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX3GCR5_RESERVED_15_DEFVAL #undef DDR_PHY_DX3GCR5_RESERVED_15_SHIFT #undef DDR_PHY_DX3GCR5_RESERVED_15_MASK -#define DDR_PHY_DX3GCR5_RESERVED_15_DEFVAL 0x09090909 -#define DDR_PHY_DX3GCR5_RESERVED_15_SHIFT 15 -#define DDR_PHY_DX3GCR5_RESERVED_15_MASK 0x00008000U +#define DDR_PHY_DX3GCR5_RESERVED_15_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR5_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX3GCR5_RESERVED_15_MASK 0x00008000U -/*Byte Lane internal VREF Select for Rank 1*/ +/* +* Byte Lane internal VREF Select for Rank 1 +*/ #undef DDR_PHY_DX3GCR5_DXREFISELR1_DEFVAL #undef DDR_PHY_DX3GCR5_DXREFISELR1_SHIFT #undef DDR_PHY_DX3GCR5_DXREFISELR1_MASK -#define DDR_PHY_DX3GCR5_DXREFISELR1_DEFVAL 0x09090909 -#define DDR_PHY_DX3GCR5_DXREFISELR1_SHIFT 8 -#define DDR_PHY_DX3GCR5_DXREFISELR1_MASK 0x00007F00U +#define DDR_PHY_DX3GCR5_DXREFISELR1_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR5_DXREFISELR1_SHIFT 8 +#define DDR_PHY_DX3GCR5_DXREFISELR1_MASK 0x00007F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX3GCR5_RESERVED_7_DEFVAL #undef DDR_PHY_DX3GCR5_RESERVED_7_SHIFT #undef DDR_PHY_DX3GCR5_RESERVED_7_MASK -#define DDR_PHY_DX3GCR5_RESERVED_7_DEFVAL 0x09090909 -#define DDR_PHY_DX3GCR5_RESERVED_7_SHIFT 7 -#define DDR_PHY_DX3GCR5_RESERVED_7_MASK 0x00000080U +#define DDR_PHY_DX3GCR5_RESERVED_7_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR5_RESERVED_7_SHIFT 7 +#define DDR_PHY_DX3GCR5_RESERVED_7_MASK 0x00000080U -/*Byte Lane internal VREF Select for Rank 0*/ +/* +* Byte Lane internal VREF Select for Rank 0 +*/ #undef DDR_PHY_DX3GCR5_DXREFISELR0_DEFVAL #undef DDR_PHY_DX3GCR5_DXREFISELR0_SHIFT #undef DDR_PHY_DX3GCR5_DXREFISELR0_MASK -#define DDR_PHY_DX3GCR5_DXREFISELR0_DEFVAL 0x09090909 -#define DDR_PHY_DX3GCR5_DXREFISELR0_SHIFT 0 -#define DDR_PHY_DX3GCR5_DXREFISELR0_MASK 0x0000007FU +#define DDR_PHY_DX3GCR5_DXREFISELR0_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR5_DXREFISELR0_SHIFT 0 +#define DDR_PHY_DX3GCR5_DXREFISELR0_MASK 0x0000007FU -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX3GCR6_RESERVED_31_30_DEFVAL #undef DDR_PHY_DX3GCR6_RESERVED_31_30_SHIFT #undef DDR_PHY_DX3GCR6_RESERVED_31_30_MASK -#define DDR_PHY_DX3GCR6_RESERVED_31_30_DEFVAL 0x09090909 -#define DDR_PHY_DX3GCR6_RESERVED_31_30_SHIFT 30 -#define DDR_PHY_DX3GCR6_RESERVED_31_30_MASK 0xC0000000U +#define DDR_PHY_DX3GCR6_RESERVED_31_30_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR6_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX3GCR6_RESERVED_31_30_MASK 0xC0000000U -/*DRAM DQ VREF Select for Rank3*/ +/* +* DRAM DQ VREF Select for Rank3 +*/ #undef DDR_PHY_DX3GCR6_DXDQVREFR3_DEFVAL #undef DDR_PHY_DX3GCR6_DXDQVREFR3_SHIFT #undef DDR_PHY_DX3GCR6_DXDQVREFR3_MASK -#define DDR_PHY_DX3GCR6_DXDQVREFR3_DEFVAL 0x09090909 -#define DDR_PHY_DX3GCR6_DXDQVREFR3_SHIFT 24 -#define DDR_PHY_DX3GCR6_DXDQVREFR3_MASK 0x3F000000U +#define DDR_PHY_DX3GCR6_DXDQVREFR3_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR6_DXDQVREFR3_SHIFT 24 +#define DDR_PHY_DX3GCR6_DXDQVREFR3_MASK 0x3F000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX3GCR6_RESERVED_23_22_DEFVAL #undef DDR_PHY_DX3GCR6_RESERVED_23_22_SHIFT #undef DDR_PHY_DX3GCR6_RESERVED_23_22_MASK -#define DDR_PHY_DX3GCR6_RESERVED_23_22_DEFVAL 0x09090909 -#define DDR_PHY_DX3GCR6_RESERVED_23_22_SHIFT 22 -#define DDR_PHY_DX3GCR6_RESERVED_23_22_MASK 0x00C00000U +#define DDR_PHY_DX3GCR6_RESERVED_23_22_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR6_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX3GCR6_RESERVED_23_22_MASK 0x00C00000U -/*DRAM DQ VREF Select for Rank2*/ +/* +* DRAM DQ VREF Select for Rank2 +*/ #undef DDR_PHY_DX3GCR6_DXDQVREFR2_DEFVAL #undef DDR_PHY_DX3GCR6_DXDQVREFR2_SHIFT #undef DDR_PHY_DX3GCR6_DXDQVREFR2_MASK -#define DDR_PHY_DX3GCR6_DXDQVREFR2_DEFVAL 0x09090909 -#define DDR_PHY_DX3GCR6_DXDQVREFR2_SHIFT 16 -#define DDR_PHY_DX3GCR6_DXDQVREFR2_MASK 0x003F0000U +#define DDR_PHY_DX3GCR6_DXDQVREFR2_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR6_DXDQVREFR2_SHIFT 16 +#define DDR_PHY_DX3GCR6_DXDQVREFR2_MASK 0x003F0000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX3GCR6_RESERVED_15_14_DEFVAL #undef DDR_PHY_DX3GCR6_RESERVED_15_14_SHIFT #undef DDR_PHY_DX3GCR6_RESERVED_15_14_MASK -#define DDR_PHY_DX3GCR6_RESERVED_15_14_DEFVAL 0x09090909 -#define DDR_PHY_DX3GCR6_RESERVED_15_14_SHIFT 14 -#define DDR_PHY_DX3GCR6_RESERVED_15_14_MASK 0x0000C000U +#define DDR_PHY_DX3GCR6_RESERVED_15_14_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR6_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_DX3GCR6_RESERVED_15_14_MASK 0x0000C000U -/*DRAM DQ VREF Select for Rank1*/ +/* +* DRAM DQ VREF Select for Rank1 +*/ #undef DDR_PHY_DX3GCR6_DXDQVREFR1_DEFVAL #undef DDR_PHY_DX3GCR6_DXDQVREFR1_SHIFT #undef DDR_PHY_DX3GCR6_DXDQVREFR1_MASK -#define DDR_PHY_DX3GCR6_DXDQVREFR1_DEFVAL 0x09090909 -#define DDR_PHY_DX3GCR6_DXDQVREFR1_SHIFT 8 -#define DDR_PHY_DX3GCR6_DXDQVREFR1_MASK 0x00003F00U +#define DDR_PHY_DX3GCR6_DXDQVREFR1_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR6_DXDQVREFR1_SHIFT 8 +#define DDR_PHY_DX3GCR6_DXDQVREFR1_MASK 0x00003F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX3GCR6_RESERVED_7_6_DEFVAL #undef DDR_PHY_DX3GCR6_RESERVED_7_6_SHIFT #undef DDR_PHY_DX3GCR6_RESERVED_7_6_MASK -#define DDR_PHY_DX3GCR6_RESERVED_7_6_DEFVAL 0x09090909 -#define DDR_PHY_DX3GCR6_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_DX3GCR6_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_DX3GCR6_RESERVED_7_6_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR6_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX3GCR6_RESERVED_7_6_MASK 0x000000C0U -/*DRAM DQ VREF Select for Rank0*/ +/* +* DRAM DQ VREF Select for Rank0 +*/ #undef DDR_PHY_DX3GCR6_DXDQVREFR0_DEFVAL #undef DDR_PHY_DX3GCR6_DXDQVREFR0_SHIFT #undef DDR_PHY_DX3GCR6_DXDQVREFR0_MASK -#define DDR_PHY_DX3GCR6_DXDQVREFR0_DEFVAL 0x09090909 -#define DDR_PHY_DX3GCR6_DXDQVREFR0_SHIFT 0 -#define DDR_PHY_DX3GCR6_DXDQVREFR0_MASK 0x0000003FU +#define DDR_PHY_DX3GCR6_DXDQVREFR0_DEFVAL 0x09090909 +#define DDR_PHY_DX3GCR6_DXDQVREFR0_SHIFT 0 +#define DDR_PHY_DX3GCR6_DXDQVREFR0_MASK 0x0000003FU -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX3LCDLR2_RESERVED_31_25_DEFVAL -#undef DDR_PHY_DX3LCDLR2_RESERVED_31_25_SHIFT -#undef DDR_PHY_DX3LCDLR2_RESERVED_31_25_MASK -#define DDR_PHY_DX3LCDLR2_RESERVED_31_25_DEFVAL 0x00000000 -#define DDR_PHY_DX3LCDLR2_RESERVED_31_25_SHIFT 25 -#define DDR_PHY_DX3LCDLR2_RESERVED_31_25_MASK 0xFE000000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX3LCDLR2_RESERVED_24_16_DEFVAL -#undef DDR_PHY_DX3LCDLR2_RESERVED_24_16_SHIFT -#undef DDR_PHY_DX3LCDLR2_RESERVED_24_16_MASK -#define DDR_PHY_DX3LCDLR2_RESERVED_24_16_DEFVAL 0x00000000 -#define DDR_PHY_DX3LCDLR2_RESERVED_24_16_SHIFT 16 -#define DDR_PHY_DX3LCDLR2_RESERVED_24_16_MASK 0x01FF0000U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX3LCDLR2_RESERVED_15_9_DEFVAL -#undef DDR_PHY_DX3LCDLR2_RESERVED_15_9_SHIFT -#undef DDR_PHY_DX3LCDLR2_RESERVED_15_9_MASK -#define DDR_PHY_DX3LCDLR2_RESERVED_15_9_DEFVAL 0x00000000 -#define DDR_PHY_DX3LCDLR2_RESERVED_15_9_SHIFT 9 -#define DDR_PHY_DX3LCDLR2_RESERVED_15_9_MASK 0x0000FE00U - -/*Read DQS Gating Delay*/ -#undef DDR_PHY_DX3LCDLR2_DQSGD_DEFVAL -#undef DDR_PHY_DX3LCDLR2_DQSGD_SHIFT -#undef DDR_PHY_DX3LCDLR2_DQSGD_MASK -#define DDR_PHY_DX3LCDLR2_DQSGD_DEFVAL 0x00000000 -#define DDR_PHY_DX3LCDLR2_DQSGD_SHIFT 0 -#define DDR_PHY_DX3LCDLR2_DQSGD_MASK 0x000001FFU - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX3GTR0_RESERVED_31_24_DEFVAL -#undef DDR_PHY_DX3GTR0_RESERVED_31_24_SHIFT -#undef DDR_PHY_DX3GTR0_RESERVED_31_24_MASK -#define DDR_PHY_DX3GTR0_RESERVED_31_24_DEFVAL 0x00020000 -#define DDR_PHY_DX3GTR0_RESERVED_31_24_SHIFT 27 -#define DDR_PHY_DX3GTR0_RESERVED_31_24_MASK 0xF8000000U - -/*DQ Write Path Latency Pipeline*/ -#undef DDR_PHY_DX3GTR0_WDQSL_DEFVAL -#undef DDR_PHY_DX3GTR0_WDQSL_SHIFT -#undef DDR_PHY_DX3GTR0_WDQSL_MASK -#define DDR_PHY_DX3GTR0_WDQSL_DEFVAL 0x00020000 -#define DDR_PHY_DX3GTR0_WDQSL_SHIFT 24 -#define DDR_PHY_DX3GTR0_WDQSL_MASK 0x07000000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX3GTR0_RESERVED_23_20_DEFVAL -#undef DDR_PHY_DX3GTR0_RESERVED_23_20_SHIFT -#undef DDR_PHY_DX3GTR0_RESERVED_23_20_MASK -#define DDR_PHY_DX3GTR0_RESERVED_23_20_DEFVAL 0x00020000 -#define DDR_PHY_DX3GTR0_RESERVED_23_20_SHIFT 20 -#define DDR_PHY_DX3GTR0_RESERVED_23_20_MASK 0x00F00000U - -/*Write Leveling System Latency*/ -#undef DDR_PHY_DX3GTR0_WLSL_DEFVAL -#undef DDR_PHY_DX3GTR0_WLSL_SHIFT -#undef DDR_PHY_DX3GTR0_WLSL_MASK -#define DDR_PHY_DX3GTR0_WLSL_DEFVAL 0x00020000 -#define DDR_PHY_DX3GTR0_WLSL_SHIFT 16 -#define DDR_PHY_DX3GTR0_WLSL_MASK 0x000F0000U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX3GTR0_RESERVED_15_13_DEFVAL -#undef DDR_PHY_DX3GTR0_RESERVED_15_13_SHIFT -#undef DDR_PHY_DX3GTR0_RESERVED_15_13_MASK -#define DDR_PHY_DX3GTR0_RESERVED_15_13_DEFVAL 0x00020000 -#define DDR_PHY_DX3GTR0_RESERVED_15_13_SHIFT 13 -#define DDR_PHY_DX3GTR0_RESERVED_15_13_MASK 0x0000E000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX3GTR0_RESERVED_12_8_DEFVAL -#undef DDR_PHY_DX3GTR0_RESERVED_12_8_SHIFT -#undef DDR_PHY_DX3GTR0_RESERVED_12_8_MASK -#define DDR_PHY_DX3GTR0_RESERVED_12_8_DEFVAL 0x00020000 -#define DDR_PHY_DX3GTR0_RESERVED_12_8_SHIFT 8 -#define DDR_PHY_DX3GTR0_RESERVED_12_8_MASK 0x00001F00U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX3GTR0_RESERVED_7_5_DEFVAL -#undef DDR_PHY_DX3GTR0_RESERVED_7_5_SHIFT -#undef DDR_PHY_DX3GTR0_RESERVED_7_5_MASK -#define DDR_PHY_DX3GTR0_RESERVED_7_5_DEFVAL 0x00020000 -#define DDR_PHY_DX3GTR0_RESERVED_7_5_SHIFT 5 -#define DDR_PHY_DX3GTR0_RESERVED_7_5_MASK 0x000000E0U - -/*DQS Gating System Latency*/ -#undef DDR_PHY_DX3GTR0_DGSL_DEFVAL -#undef DDR_PHY_DX3GTR0_DGSL_SHIFT -#undef DDR_PHY_DX3GTR0_DGSL_MASK -#define DDR_PHY_DX3GTR0_DGSL_DEFVAL 0x00020000 -#define DDR_PHY_DX3GTR0_DGSL_SHIFT 0 -#define DDR_PHY_DX3GTR0_DGSL_MASK 0x0000001FU - -/*Calibration Bypass*/ +/* +* Calibration Bypass +*/ #undef DDR_PHY_DX4GCR0_CALBYP_DEFVAL #undef DDR_PHY_DX4GCR0_CALBYP_SHIFT #undef DDR_PHY_DX4GCR0_CALBYP_MASK -#define DDR_PHY_DX4GCR0_CALBYP_DEFVAL 0x40200204 -#define DDR_PHY_DX4GCR0_CALBYP_SHIFT 31 -#define DDR_PHY_DX4GCR0_CALBYP_MASK 0x80000000U +#define DDR_PHY_DX4GCR0_CALBYP_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_CALBYP_SHIFT 31 +#define DDR_PHY_DX4GCR0_CALBYP_MASK 0x80000000U -/*Master Delay Line Enable*/ +/* +* Master Delay Line Enable +*/ #undef DDR_PHY_DX4GCR0_MDLEN_DEFVAL #undef DDR_PHY_DX4GCR0_MDLEN_SHIFT #undef DDR_PHY_DX4GCR0_MDLEN_MASK -#define DDR_PHY_DX4GCR0_MDLEN_DEFVAL 0x40200204 -#define DDR_PHY_DX4GCR0_MDLEN_SHIFT 30 -#define DDR_PHY_DX4GCR0_MDLEN_MASK 0x40000000U +#define DDR_PHY_DX4GCR0_MDLEN_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_MDLEN_SHIFT 30 +#define DDR_PHY_DX4GCR0_MDLEN_MASK 0x40000000U -/*Configurable ODT(TE) Phase Shift*/ +/* +* Configurable ODT(TE) Phase Shift +*/ #undef DDR_PHY_DX4GCR0_CODTSHFT_DEFVAL #undef DDR_PHY_DX4GCR0_CODTSHFT_SHIFT #undef DDR_PHY_DX4GCR0_CODTSHFT_MASK -#define DDR_PHY_DX4GCR0_CODTSHFT_DEFVAL 0x40200204 -#define DDR_PHY_DX4GCR0_CODTSHFT_SHIFT 28 -#define DDR_PHY_DX4GCR0_CODTSHFT_MASK 0x30000000U +#define DDR_PHY_DX4GCR0_CODTSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_CODTSHFT_SHIFT 28 +#define DDR_PHY_DX4GCR0_CODTSHFT_MASK 0x30000000U -/*DQS Duty Cycle Correction*/ +/* +* DQS Duty Cycle Correction +*/ #undef DDR_PHY_DX4GCR0_DQSDCC_DEFVAL #undef DDR_PHY_DX4GCR0_DQSDCC_SHIFT #undef DDR_PHY_DX4GCR0_DQSDCC_MASK -#define DDR_PHY_DX4GCR0_DQSDCC_DEFVAL 0x40200204 -#define DDR_PHY_DX4GCR0_DQSDCC_SHIFT 24 -#define DDR_PHY_DX4GCR0_DQSDCC_MASK 0x0F000000U +#define DDR_PHY_DX4GCR0_DQSDCC_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_DQSDCC_SHIFT 24 +#define DDR_PHY_DX4GCR0_DQSDCC_MASK 0x0F000000U -/*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/ +/* +* Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY +*/ #undef DDR_PHY_DX4GCR0_RDDLY_DEFVAL #undef DDR_PHY_DX4GCR0_RDDLY_SHIFT #undef DDR_PHY_DX4GCR0_RDDLY_MASK -#define DDR_PHY_DX4GCR0_RDDLY_DEFVAL 0x40200204 -#define DDR_PHY_DX4GCR0_RDDLY_SHIFT 20 -#define DDR_PHY_DX4GCR0_RDDLY_MASK 0x00F00000U +#define DDR_PHY_DX4GCR0_RDDLY_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_RDDLY_SHIFT 20 +#define DDR_PHY_DX4GCR0_RDDLY_MASK 0x00F00000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX4GCR0_RESERVED_19_14_DEFVAL #undef DDR_PHY_DX4GCR0_RESERVED_19_14_SHIFT #undef DDR_PHY_DX4GCR0_RESERVED_19_14_MASK -#define DDR_PHY_DX4GCR0_RESERVED_19_14_DEFVAL 0x40200204 -#define DDR_PHY_DX4GCR0_RESERVED_19_14_SHIFT 14 -#define DDR_PHY_DX4GCR0_RESERVED_19_14_MASK 0x000FC000U +#define DDR_PHY_DX4GCR0_RESERVED_19_14_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_RESERVED_19_14_SHIFT 14 +#define DDR_PHY_DX4GCR0_RESERVED_19_14_MASK 0x000FC000U -/*DQSNSE Power Down Receiver*/ +/* +* DQSNSE Power Down Receiver +*/ #undef DDR_PHY_DX4GCR0_DQSNSEPDR_DEFVAL #undef DDR_PHY_DX4GCR0_DQSNSEPDR_SHIFT #undef DDR_PHY_DX4GCR0_DQSNSEPDR_MASK -#define DDR_PHY_DX4GCR0_DQSNSEPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX4GCR0_DQSNSEPDR_SHIFT 13 -#define DDR_PHY_DX4GCR0_DQSNSEPDR_MASK 0x00002000U +#define DDR_PHY_DX4GCR0_DQSNSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_DQSNSEPDR_SHIFT 13 +#define DDR_PHY_DX4GCR0_DQSNSEPDR_MASK 0x00002000U -/*DQSSE Power Down Receiver*/ +/* +* DQSSE Power Down Receiver +*/ #undef DDR_PHY_DX4GCR0_DQSSEPDR_DEFVAL #undef DDR_PHY_DX4GCR0_DQSSEPDR_SHIFT #undef DDR_PHY_DX4GCR0_DQSSEPDR_MASK -#define DDR_PHY_DX4GCR0_DQSSEPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX4GCR0_DQSSEPDR_SHIFT 12 -#define DDR_PHY_DX4GCR0_DQSSEPDR_MASK 0x00001000U +#define DDR_PHY_DX4GCR0_DQSSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_DQSSEPDR_SHIFT 12 +#define DDR_PHY_DX4GCR0_DQSSEPDR_MASK 0x00001000U -/*RTT On Additive Latency*/ +/* +* RTT On Additive Latency +*/ #undef DDR_PHY_DX4GCR0_RTTOAL_DEFVAL #undef DDR_PHY_DX4GCR0_RTTOAL_SHIFT #undef DDR_PHY_DX4GCR0_RTTOAL_MASK -#define DDR_PHY_DX4GCR0_RTTOAL_DEFVAL 0x40200204 -#define DDR_PHY_DX4GCR0_RTTOAL_SHIFT 11 -#define DDR_PHY_DX4GCR0_RTTOAL_MASK 0x00000800U +#define DDR_PHY_DX4GCR0_RTTOAL_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_RTTOAL_SHIFT 11 +#define DDR_PHY_DX4GCR0_RTTOAL_MASK 0x00000800U -/*RTT Output Hold*/ +/* +* RTT Output Hold +*/ #undef DDR_PHY_DX4GCR0_RTTOH_DEFVAL #undef DDR_PHY_DX4GCR0_RTTOH_SHIFT #undef DDR_PHY_DX4GCR0_RTTOH_MASK -#define DDR_PHY_DX4GCR0_RTTOH_DEFVAL 0x40200204 -#define DDR_PHY_DX4GCR0_RTTOH_SHIFT 9 -#define DDR_PHY_DX4GCR0_RTTOH_MASK 0x00000600U +#define DDR_PHY_DX4GCR0_RTTOH_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_RTTOH_SHIFT 9 +#define DDR_PHY_DX4GCR0_RTTOH_MASK 0x00000600U -/*Configurable PDR Phase Shift*/ +/* +* Configurable PDR Phase Shift +*/ #undef DDR_PHY_DX4GCR0_CPDRSHFT_DEFVAL #undef DDR_PHY_DX4GCR0_CPDRSHFT_SHIFT #undef DDR_PHY_DX4GCR0_CPDRSHFT_MASK -#define DDR_PHY_DX4GCR0_CPDRSHFT_DEFVAL 0x40200204 -#define DDR_PHY_DX4GCR0_CPDRSHFT_SHIFT 7 -#define DDR_PHY_DX4GCR0_CPDRSHFT_MASK 0x00000180U +#define DDR_PHY_DX4GCR0_CPDRSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_CPDRSHFT_SHIFT 7 +#define DDR_PHY_DX4GCR0_CPDRSHFT_MASK 0x00000180U -/*DQSR Power Down*/ +/* +* DQSR Power Down +*/ #undef DDR_PHY_DX4GCR0_DQSRPD_DEFVAL #undef DDR_PHY_DX4GCR0_DQSRPD_SHIFT #undef DDR_PHY_DX4GCR0_DQSRPD_MASK -#define DDR_PHY_DX4GCR0_DQSRPD_DEFVAL 0x40200204 -#define DDR_PHY_DX4GCR0_DQSRPD_SHIFT 6 -#define DDR_PHY_DX4GCR0_DQSRPD_MASK 0x00000040U +#define DDR_PHY_DX4GCR0_DQSRPD_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_DQSRPD_SHIFT 6 +#define DDR_PHY_DX4GCR0_DQSRPD_MASK 0x00000040U -/*DQSG Power Down Receiver*/ +/* +* DQSG Power Down Receiver +*/ #undef DDR_PHY_DX4GCR0_DQSGPDR_DEFVAL #undef DDR_PHY_DX4GCR0_DQSGPDR_SHIFT #undef DDR_PHY_DX4GCR0_DQSGPDR_MASK -#define DDR_PHY_DX4GCR0_DQSGPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX4GCR0_DQSGPDR_SHIFT 5 -#define DDR_PHY_DX4GCR0_DQSGPDR_MASK 0x00000020U +#define DDR_PHY_DX4GCR0_DQSGPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_DQSGPDR_SHIFT 5 +#define DDR_PHY_DX4GCR0_DQSGPDR_MASK 0x00000020U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX4GCR0_RESERVED_4_DEFVAL #undef DDR_PHY_DX4GCR0_RESERVED_4_SHIFT #undef DDR_PHY_DX4GCR0_RESERVED_4_MASK -#define DDR_PHY_DX4GCR0_RESERVED_4_DEFVAL 0x40200204 -#define DDR_PHY_DX4GCR0_RESERVED_4_SHIFT 4 -#define DDR_PHY_DX4GCR0_RESERVED_4_MASK 0x00000010U +#define DDR_PHY_DX4GCR0_RESERVED_4_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_RESERVED_4_SHIFT 4 +#define DDR_PHY_DX4GCR0_RESERVED_4_MASK 0x00000010U -/*DQSG On-Die Termination*/ +/* +* DQSG On-Die Termination +*/ #undef DDR_PHY_DX4GCR0_DQSGODT_DEFVAL #undef DDR_PHY_DX4GCR0_DQSGODT_SHIFT #undef DDR_PHY_DX4GCR0_DQSGODT_MASK -#define DDR_PHY_DX4GCR0_DQSGODT_DEFVAL 0x40200204 -#define DDR_PHY_DX4GCR0_DQSGODT_SHIFT 3 -#define DDR_PHY_DX4GCR0_DQSGODT_MASK 0x00000008U +#define DDR_PHY_DX4GCR0_DQSGODT_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_DQSGODT_SHIFT 3 +#define DDR_PHY_DX4GCR0_DQSGODT_MASK 0x00000008U -/*DQSG Output Enable*/ +/* +* DQSG Output Enable +*/ #undef DDR_PHY_DX4GCR0_DQSGOE_DEFVAL #undef DDR_PHY_DX4GCR0_DQSGOE_SHIFT #undef DDR_PHY_DX4GCR0_DQSGOE_MASK -#define DDR_PHY_DX4GCR0_DQSGOE_DEFVAL 0x40200204 -#define DDR_PHY_DX4GCR0_DQSGOE_SHIFT 2 -#define DDR_PHY_DX4GCR0_DQSGOE_MASK 0x00000004U +#define DDR_PHY_DX4GCR0_DQSGOE_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_DQSGOE_SHIFT 2 +#define DDR_PHY_DX4GCR0_DQSGOE_MASK 0x00000004U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX4GCR0_RESERVED_1_0_DEFVAL #undef DDR_PHY_DX4GCR0_RESERVED_1_0_SHIFT #undef DDR_PHY_DX4GCR0_RESERVED_1_0_MASK -#define DDR_PHY_DX4GCR0_RESERVED_1_0_DEFVAL 0x40200204 -#define DDR_PHY_DX4GCR0_RESERVED_1_0_SHIFT 0 -#define DDR_PHY_DX4GCR0_RESERVED_1_0_MASK 0x00000003U +#define DDR_PHY_DX4GCR0_RESERVED_1_0_DEFVAL 0x40200204 +#define DDR_PHY_DX4GCR0_RESERVED_1_0_SHIFT 0 +#define DDR_PHY_DX4GCR0_RESERVED_1_0_MASK 0x00000003U -/*Enables the PDR mode for DQ[7:0]*/ +/* +* Enables the PDR mode for DQ[7:0] +*/ #undef DDR_PHY_DX4GCR1_DXPDRMODE_DEFVAL #undef DDR_PHY_DX4GCR1_DXPDRMODE_SHIFT #undef DDR_PHY_DX4GCR1_DXPDRMODE_MASK -#define DDR_PHY_DX4GCR1_DXPDRMODE_DEFVAL 0x00007FFF -#define DDR_PHY_DX4GCR1_DXPDRMODE_SHIFT 16 -#define DDR_PHY_DX4GCR1_DXPDRMODE_MASK 0xFFFF0000U +#define DDR_PHY_DX4GCR1_DXPDRMODE_DEFVAL 0x00007FFF +#define DDR_PHY_DX4GCR1_DXPDRMODE_SHIFT 16 +#define DDR_PHY_DX4GCR1_DXPDRMODE_MASK 0xFFFF0000U -/*Reserved. Returns zeroes on reads.*/ +/* +* Reserved. Returns zeroes on reads. +*/ #undef DDR_PHY_DX4GCR1_RESERVED_15_DEFVAL #undef DDR_PHY_DX4GCR1_RESERVED_15_SHIFT #undef DDR_PHY_DX4GCR1_RESERVED_15_MASK -#define DDR_PHY_DX4GCR1_RESERVED_15_DEFVAL 0x00007FFF -#define DDR_PHY_DX4GCR1_RESERVED_15_SHIFT 15 -#define DDR_PHY_DX4GCR1_RESERVED_15_MASK 0x00008000U +#define DDR_PHY_DX4GCR1_RESERVED_15_DEFVAL 0x00007FFF +#define DDR_PHY_DX4GCR1_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX4GCR1_RESERVED_15_MASK 0x00008000U -/*Select the delayed or non-delayed read data strobe #*/ +/* +* Select the delayed or non-delayed read data strobe # +*/ #undef DDR_PHY_DX4GCR1_QSNSEL_DEFVAL #undef DDR_PHY_DX4GCR1_QSNSEL_SHIFT #undef DDR_PHY_DX4GCR1_QSNSEL_MASK -#define DDR_PHY_DX4GCR1_QSNSEL_DEFVAL 0x00007FFF -#define DDR_PHY_DX4GCR1_QSNSEL_SHIFT 14 -#define DDR_PHY_DX4GCR1_QSNSEL_MASK 0x00004000U +#define DDR_PHY_DX4GCR1_QSNSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX4GCR1_QSNSEL_SHIFT 14 +#define DDR_PHY_DX4GCR1_QSNSEL_MASK 0x00004000U -/*Select the delayed or non-delayed read data strobe*/ +/* +* Select the delayed or non-delayed read data strobe +*/ #undef DDR_PHY_DX4GCR1_QSSEL_DEFVAL #undef DDR_PHY_DX4GCR1_QSSEL_SHIFT #undef DDR_PHY_DX4GCR1_QSSEL_MASK -#define DDR_PHY_DX4GCR1_QSSEL_DEFVAL 0x00007FFF -#define DDR_PHY_DX4GCR1_QSSEL_SHIFT 13 -#define DDR_PHY_DX4GCR1_QSSEL_MASK 0x00002000U +#define DDR_PHY_DX4GCR1_QSSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX4GCR1_QSSEL_SHIFT 13 +#define DDR_PHY_DX4GCR1_QSSEL_MASK 0x00002000U -/*Enables Read Data Strobe in a byte lane*/ +/* +* Enables Read Data Strobe in a byte lane +*/ #undef DDR_PHY_DX4GCR1_OEEN_DEFVAL #undef DDR_PHY_DX4GCR1_OEEN_SHIFT #undef DDR_PHY_DX4GCR1_OEEN_MASK -#define DDR_PHY_DX4GCR1_OEEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX4GCR1_OEEN_SHIFT 12 -#define DDR_PHY_DX4GCR1_OEEN_MASK 0x00001000U +#define DDR_PHY_DX4GCR1_OEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX4GCR1_OEEN_SHIFT 12 +#define DDR_PHY_DX4GCR1_OEEN_MASK 0x00001000U -/*Enables PDR in a byte lane*/ +/* +* Enables PDR in a byte lane +*/ #undef DDR_PHY_DX4GCR1_PDREN_DEFVAL #undef DDR_PHY_DX4GCR1_PDREN_SHIFT #undef DDR_PHY_DX4GCR1_PDREN_MASK -#define DDR_PHY_DX4GCR1_PDREN_DEFVAL 0x00007FFF -#define DDR_PHY_DX4GCR1_PDREN_SHIFT 11 -#define DDR_PHY_DX4GCR1_PDREN_MASK 0x00000800U +#define DDR_PHY_DX4GCR1_PDREN_DEFVAL 0x00007FFF +#define DDR_PHY_DX4GCR1_PDREN_SHIFT 11 +#define DDR_PHY_DX4GCR1_PDREN_MASK 0x00000800U -/*Enables ODT/TE in a byte lane*/ +/* +* Enables ODT/TE in a byte lane +*/ #undef DDR_PHY_DX4GCR1_TEEN_DEFVAL #undef DDR_PHY_DX4GCR1_TEEN_SHIFT #undef DDR_PHY_DX4GCR1_TEEN_MASK -#define DDR_PHY_DX4GCR1_TEEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX4GCR1_TEEN_SHIFT 10 -#define DDR_PHY_DX4GCR1_TEEN_MASK 0x00000400U +#define DDR_PHY_DX4GCR1_TEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX4GCR1_TEEN_SHIFT 10 +#define DDR_PHY_DX4GCR1_TEEN_MASK 0x00000400U -/*Enables Write Data strobe in a byte lane*/ +/* +* Enables Write Data strobe in a byte lane +*/ #undef DDR_PHY_DX4GCR1_DSEN_DEFVAL #undef DDR_PHY_DX4GCR1_DSEN_SHIFT #undef DDR_PHY_DX4GCR1_DSEN_MASK -#define DDR_PHY_DX4GCR1_DSEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX4GCR1_DSEN_SHIFT 9 -#define DDR_PHY_DX4GCR1_DSEN_MASK 0x00000200U +#define DDR_PHY_DX4GCR1_DSEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX4GCR1_DSEN_SHIFT 9 +#define DDR_PHY_DX4GCR1_DSEN_MASK 0x00000200U -/*Enables DM pin in a byte lane*/ +/* +* Enables DM pin in a byte lane +*/ #undef DDR_PHY_DX4GCR1_DMEN_DEFVAL #undef DDR_PHY_DX4GCR1_DMEN_SHIFT #undef DDR_PHY_DX4GCR1_DMEN_MASK -#define DDR_PHY_DX4GCR1_DMEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX4GCR1_DMEN_SHIFT 8 -#define DDR_PHY_DX4GCR1_DMEN_MASK 0x00000100U +#define DDR_PHY_DX4GCR1_DMEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX4GCR1_DMEN_SHIFT 8 +#define DDR_PHY_DX4GCR1_DMEN_MASK 0x00000100U -/*Enables DQ corresponding to each bit in a byte*/ +/* +* Enables DQ corresponding to each bit in a byte +*/ #undef DDR_PHY_DX4GCR1_DQEN_DEFVAL #undef DDR_PHY_DX4GCR1_DQEN_SHIFT #undef DDR_PHY_DX4GCR1_DQEN_MASK -#define DDR_PHY_DX4GCR1_DQEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX4GCR1_DQEN_SHIFT 0 -#define DDR_PHY_DX4GCR1_DQEN_MASK 0x000000FFU +#define DDR_PHY_DX4GCR1_DQEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX4GCR1_DQEN_SHIFT 0 +#define DDR_PHY_DX4GCR1_DQEN_MASK 0x000000FFU -/*Byte lane VREF IOM (Used only by D4MU IOs)*/ +/* +* Byte lane VREF IOM (Used only by D4MU IOs) +*/ #undef DDR_PHY_DX4GCR4_RESERVED_31_29_DEFVAL #undef DDR_PHY_DX4GCR4_RESERVED_31_29_SHIFT #undef DDR_PHY_DX4GCR4_RESERVED_31_29_MASK -#define DDR_PHY_DX4GCR4_RESERVED_31_29_DEFVAL 0x0E00003C -#define DDR_PHY_DX4GCR4_RESERVED_31_29_SHIFT 29 -#define DDR_PHY_DX4GCR4_RESERVED_31_29_MASK 0xE0000000U +#define DDR_PHY_DX4GCR4_RESERVED_31_29_DEFVAL 0x0E00003C +#define DDR_PHY_DX4GCR4_RESERVED_31_29_SHIFT 29 +#define DDR_PHY_DX4GCR4_RESERVED_31_29_MASK 0xE0000000U -/*Byte Lane VREF Pad Enable*/ +/* +* Byte Lane VREF Pad Enable +*/ #undef DDR_PHY_DX4GCR4_DXREFPEN_DEFVAL #undef DDR_PHY_DX4GCR4_DXREFPEN_SHIFT #undef DDR_PHY_DX4GCR4_DXREFPEN_MASK -#define DDR_PHY_DX4GCR4_DXREFPEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX4GCR4_DXREFPEN_SHIFT 28 -#define DDR_PHY_DX4GCR4_DXREFPEN_MASK 0x10000000U +#define DDR_PHY_DX4GCR4_DXREFPEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX4GCR4_DXREFPEN_SHIFT 28 +#define DDR_PHY_DX4GCR4_DXREFPEN_MASK 0x10000000U -/*Byte Lane Internal VREF Enable*/ +/* +* Byte Lane Internal VREF Enable +*/ #undef DDR_PHY_DX4GCR4_DXREFEEN_DEFVAL #undef DDR_PHY_DX4GCR4_DXREFEEN_SHIFT #undef DDR_PHY_DX4GCR4_DXREFEEN_MASK -#define DDR_PHY_DX4GCR4_DXREFEEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX4GCR4_DXREFEEN_SHIFT 26 -#define DDR_PHY_DX4GCR4_DXREFEEN_MASK 0x0C000000U +#define DDR_PHY_DX4GCR4_DXREFEEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX4GCR4_DXREFEEN_SHIFT 26 +#define DDR_PHY_DX4GCR4_DXREFEEN_MASK 0x0C000000U -/*Byte Lane Single-End VREF Enable*/ +/* +* Byte Lane Single-End VREF Enable +*/ #undef DDR_PHY_DX4GCR4_DXREFSEN_DEFVAL #undef DDR_PHY_DX4GCR4_DXREFSEN_SHIFT #undef DDR_PHY_DX4GCR4_DXREFSEN_MASK -#define DDR_PHY_DX4GCR4_DXREFSEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX4GCR4_DXREFSEN_SHIFT 25 -#define DDR_PHY_DX4GCR4_DXREFSEN_MASK 0x02000000U +#define DDR_PHY_DX4GCR4_DXREFSEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX4GCR4_DXREFSEN_SHIFT 25 +#define DDR_PHY_DX4GCR4_DXREFSEN_MASK 0x02000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX4GCR4_RESERVED_24_DEFVAL #undef DDR_PHY_DX4GCR4_RESERVED_24_SHIFT #undef DDR_PHY_DX4GCR4_RESERVED_24_MASK -#define DDR_PHY_DX4GCR4_RESERVED_24_DEFVAL 0x0E00003C -#define DDR_PHY_DX4GCR4_RESERVED_24_SHIFT 24 -#define DDR_PHY_DX4GCR4_RESERVED_24_MASK 0x01000000U +#define DDR_PHY_DX4GCR4_RESERVED_24_DEFVAL 0x0E00003C +#define DDR_PHY_DX4GCR4_RESERVED_24_SHIFT 24 +#define DDR_PHY_DX4GCR4_RESERVED_24_MASK 0x01000000U -/*External VREF generator REFSEL range select*/ +/* +* External VREF generator REFSEL range select +*/ #undef DDR_PHY_DX4GCR4_DXREFESELRANGE_DEFVAL #undef DDR_PHY_DX4GCR4_DXREFESELRANGE_SHIFT #undef DDR_PHY_DX4GCR4_DXREFESELRANGE_MASK -#define DDR_PHY_DX4GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C -#define DDR_PHY_DX4GCR4_DXREFESELRANGE_SHIFT 23 -#define DDR_PHY_DX4GCR4_DXREFESELRANGE_MASK 0x00800000U +#define DDR_PHY_DX4GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX4GCR4_DXREFESELRANGE_SHIFT 23 +#define DDR_PHY_DX4GCR4_DXREFESELRANGE_MASK 0x00800000U -/*Byte Lane External VREF Select*/ +/* +* Byte Lane External VREF Select +*/ #undef DDR_PHY_DX4GCR4_DXREFESEL_DEFVAL #undef DDR_PHY_DX4GCR4_DXREFESEL_SHIFT #undef DDR_PHY_DX4GCR4_DXREFESEL_MASK -#define DDR_PHY_DX4GCR4_DXREFESEL_DEFVAL 0x0E00003C -#define DDR_PHY_DX4GCR4_DXREFESEL_SHIFT 16 -#define DDR_PHY_DX4GCR4_DXREFESEL_MASK 0x007F0000U +#define DDR_PHY_DX4GCR4_DXREFESEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX4GCR4_DXREFESEL_SHIFT 16 +#define DDR_PHY_DX4GCR4_DXREFESEL_MASK 0x007F0000U -/*Single ended VREF generator REFSEL range select*/ +/* +* Single ended VREF generator REFSEL range select +*/ #undef DDR_PHY_DX4GCR4_DXREFSSELRANGE_DEFVAL #undef DDR_PHY_DX4GCR4_DXREFSSELRANGE_SHIFT #undef DDR_PHY_DX4GCR4_DXREFSSELRANGE_MASK -#define DDR_PHY_DX4GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C -#define DDR_PHY_DX4GCR4_DXREFSSELRANGE_SHIFT 15 -#define DDR_PHY_DX4GCR4_DXREFSSELRANGE_MASK 0x00008000U +#define DDR_PHY_DX4GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX4GCR4_DXREFSSELRANGE_SHIFT 15 +#define DDR_PHY_DX4GCR4_DXREFSSELRANGE_MASK 0x00008000U -/*Byte Lane Single-End VREF Select*/ +/* +* Byte Lane Single-End VREF Select +*/ #undef DDR_PHY_DX4GCR4_DXREFSSEL_DEFVAL #undef DDR_PHY_DX4GCR4_DXREFSSEL_SHIFT #undef DDR_PHY_DX4GCR4_DXREFSSEL_MASK -#define DDR_PHY_DX4GCR4_DXREFSSEL_DEFVAL 0x0E00003C -#define DDR_PHY_DX4GCR4_DXREFSSEL_SHIFT 8 -#define DDR_PHY_DX4GCR4_DXREFSSEL_MASK 0x00007F00U +#define DDR_PHY_DX4GCR4_DXREFSSEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX4GCR4_DXREFSSEL_SHIFT 8 +#define DDR_PHY_DX4GCR4_DXREFSSEL_MASK 0x00007F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX4GCR4_RESERVED_7_6_DEFVAL #undef DDR_PHY_DX4GCR4_RESERVED_7_6_SHIFT #undef DDR_PHY_DX4GCR4_RESERVED_7_6_MASK -#define DDR_PHY_DX4GCR4_RESERVED_7_6_DEFVAL 0x0E00003C -#define DDR_PHY_DX4GCR4_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_DX4GCR4_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_DX4GCR4_RESERVED_7_6_DEFVAL 0x0E00003C +#define DDR_PHY_DX4GCR4_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX4GCR4_RESERVED_7_6_MASK 0x000000C0U -/*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/ +/* +* VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. +*/ #undef DDR_PHY_DX4GCR4_DXREFIEN_DEFVAL #undef DDR_PHY_DX4GCR4_DXREFIEN_SHIFT #undef DDR_PHY_DX4GCR4_DXREFIEN_MASK -#define DDR_PHY_DX4GCR4_DXREFIEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX4GCR4_DXREFIEN_SHIFT 2 -#define DDR_PHY_DX4GCR4_DXREFIEN_MASK 0x0000003CU +#define DDR_PHY_DX4GCR4_DXREFIEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX4GCR4_DXREFIEN_SHIFT 2 +#define DDR_PHY_DX4GCR4_DXREFIEN_MASK 0x0000003CU -/*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/ +/* +* VRMON control for DQ IO (Single Ended) buffers of a byte lane. +*/ #undef DDR_PHY_DX4GCR4_DXREFIMON_DEFVAL #undef DDR_PHY_DX4GCR4_DXREFIMON_SHIFT #undef DDR_PHY_DX4GCR4_DXREFIMON_MASK -#define DDR_PHY_DX4GCR4_DXREFIMON_DEFVAL 0x0E00003C -#define DDR_PHY_DX4GCR4_DXREFIMON_SHIFT 0 -#define DDR_PHY_DX4GCR4_DXREFIMON_MASK 0x00000003U +#define DDR_PHY_DX4GCR4_DXREFIMON_DEFVAL 0x0E00003C +#define DDR_PHY_DX4GCR4_DXREFIMON_SHIFT 0 +#define DDR_PHY_DX4GCR4_DXREFIMON_MASK 0x00000003U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX4GCR5_RESERVED_31_DEFVAL #undef DDR_PHY_DX4GCR5_RESERVED_31_SHIFT #undef DDR_PHY_DX4GCR5_RESERVED_31_MASK -#define DDR_PHY_DX4GCR5_RESERVED_31_DEFVAL 0x09090909 -#define DDR_PHY_DX4GCR5_RESERVED_31_SHIFT 31 -#define DDR_PHY_DX4GCR5_RESERVED_31_MASK 0x80000000U +#define DDR_PHY_DX4GCR5_RESERVED_31_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR5_RESERVED_31_SHIFT 31 +#define DDR_PHY_DX4GCR5_RESERVED_31_MASK 0x80000000U -/*Byte Lane internal VREF Select for Rank 3*/ +/* +* Byte Lane internal VREF Select for Rank 3 +*/ #undef DDR_PHY_DX4GCR5_DXREFISELR3_DEFVAL #undef DDR_PHY_DX4GCR5_DXREFISELR3_SHIFT #undef DDR_PHY_DX4GCR5_DXREFISELR3_MASK -#define DDR_PHY_DX4GCR5_DXREFISELR3_DEFVAL 0x09090909 -#define DDR_PHY_DX4GCR5_DXREFISELR3_SHIFT 24 -#define DDR_PHY_DX4GCR5_DXREFISELR3_MASK 0x7F000000U +#define DDR_PHY_DX4GCR5_DXREFISELR3_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR5_DXREFISELR3_SHIFT 24 +#define DDR_PHY_DX4GCR5_DXREFISELR3_MASK 0x7F000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX4GCR5_RESERVED_23_DEFVAL #undef DDR_PHY_DX4GCR5_RESERVED_23_SHIFT #undef DDR_PHY_DX4GCR5_RESERVED_23_MASK -#define DDR_PHY_DX4GCR5_RESERVED_23_DEFVAL 0x09090909 -#define DDR_PHY_DX4GCR5_RESERVED_23_SHIFT 23 -#define DDR_PHY_DX4GCR5_RESERVED_23_MASK 0x00800000U +#define DDR_PHY_DX4GCR5_RESERVED_23_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR5_RESERVED_23_SHIFT 23 +#define DDR_PHY_DX4GCR5_RESERVED_23_MASK 0x00800000U -/*Byte Lane internal VREF Select for Rank 2*/ +/* +* Byte Lane internal VREF Select for Rank 2 +*/ #undef DDR_PHY_DX4GCR5_DXREFISELR2_DEFVAL #undef DDR_PHY_DX4GCR5_DXREFISELR2_SHIFT #undef DDR_PHY_DX4GCR5_DXREFISELR2_MASK -#define DDR_PHY_DX4GCR5_DXREFISELR2_DEFVAL 0x09090909 -#define DDR_PHY_DX4GCR5_DXREFISELR2_SHIFT 16 -#define DDR_PHY_DX4GCR5_DXREFISELR2_MASK 0x007F0000U +#define DDR_PHY_DX4GCR5_DXREFISELR2_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR5_DXREFISELR2_SHIFT 16 +#define DDR_PHY_DX4GCR5_DXREFISELR2_MASK 0x007F0000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX4GCR5_RESERVED_15_DEFVAL #undef DDR_PHY_DX4GCR5_RESERVED_15_SHIFT #undef DDR_PHY_DX4GCR5_RESERVED_15_MASK -#define DDR_PHY_DX4GCR5_RESERVED_15_DEFVAL 0x09090909 -#define DDR_PHY_DX4GCR5_RESERVED_15_SHIFT 15 -#define DDR_PHY_DX4GCR5_RESERVED_15_MASK 0x00008000U +#define DDR_PHY_DX4GCR5_RESERVED_15_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR5_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX4GCR5_RESERVED_15_MASK 0x00008000U -/*Byte Lane internal VREF Select for Rank 1*/ +/* +* Byte Lane internal VREF Select for Rank 1 +*/ #undef DDR_PHY_DX4GCR5_DXREFISELR1_DEFVAL #undef DDR_PHY_DX4GCR5_DXREFISELR1_SHIFT #undef DDR_PHY_DX4GCR5_DXREFISELR1_MASK -#define DDR_PHY_DX4GCR5_DXREFISELR1_DEFVAL 0x09090909 -#define DDR_PHY_DX4GCR5_DXREFISELR1_SHIFT 8 -#define DDR_PHY_DX4GCR5_DXREFISELR1_MASK 0x00007F00U +#define DDR_PHY_DX4GCR5_DXREFISELR1_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR5_DXREFISELR1_SHIFT 8 +#define DDR_PHY_DX4GCR5_DXREFISELR1_MASK 0x00007F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX4GCR5_RESERVED_7_DEFVAL #undef DDR_PHY_DX4GCR5_RESERVED_7_SHIFT #undef DDR_PHY_DX4GCR5_RESERVED_7_MASK -#define DDR_PHY_DX4GCR5_RESERVED_7_DEFVAL 0x09090909 -#define DDR_PHY_DX4GCR5_RESERVED_7_SHIFT 7 -#define DDR_PHY_DX4GCR5_RESERVED_7_MASK 0x00000080U +#define DDR_PHY_DX4GCR5_RESERVED_7_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR5_RESERVED_7_SHIFT 7 +#define DDR_PHY_DX4GCR5_RESERVED_7_MASK 0x00000080U -/*Byte Lane internal VREF Select for Rank 0*/ +/* +* Byte Lane internal VREF Select for Rank 0 +*/ #undef DDR_PHY_DX4GCR5_DXREFISELR0_DEFVAL #undef DDR_PHY_DX4GCR5_DXREFISELR0_SHIFT #undef DDR_PHY_DX4GCR5_DXREFISELR0_MASK -#define DDR_PHY_DX4GCR5_DXREFISELR0_DEFVAL 0x09090909 -#define DDR_PHY_DX4GCR5_DXREFISELR0_SHIFT 0 -#define DDR_PHY_DX4GCR5_DXREFISELR0_MASK 0x0000007FU +#define DDR_PHY_DX4GCR5_DXREFISELR0_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR5_DXREFISELR0_SHIFT 0 +#define DDR_PHY_DX4GCR5_DXREFISELR0_MASK 0x0000007FU -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX4GCR6_RESERVED_31_30_DEFVAL #undef DDR_PHY_DX4GCR6_RESERVED_31_30_SHIFT #undef DDR_PHY_DX4GCR6_RESERVED_31_30_MASK -#define DDR_PHY_DX4GCR6_RESERVED_31_30_DEFVAL 0x09090909 -#define DDR_PHY_DX4GCR6_RESERVED_31_30_SHIFT 30 -#define DDR_PHY_DX4GCR6_RESERVED_31_30_MASK 0xC0000000U +#define DDR_PHY_DX4GCR6_RESERVED_31_30_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR6_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX4GCR6_RESERVED_31_30_MASK 0xC0000000U -/*DRAM DQ VREF Select for Rank3*/ +/* +* DRAM DQ VREF Select for Rank3 +*/ #undef DDR_PHY_DX4GCR6_DXDQVREFR3_DEFVAL #undef DDR_PHY_DX4GCR6_DXDQVREFR3_SHIFT #undef DDR_PHY_DX4GCR6_DXDQVREFR3_MASK -#define DDR_PHY_DX4GCR6_DXDQVREFR3_DEFVAL 0x09090909 -#define DDR_PHY_DX4GCR6_DXDQVREFR3_SHIFT 24 -#define DDR_PHY_DX4GCR6_DXDQVREFR3_MASK 0x3F000000U +#define DDR_PHY_DX4GCR6_DXDQVREFR3_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR6_DXDQVREFR3_SHIFT 24 +#define DDR_PHY_DX4GCR6_DXDQVREFR3_MASK 0x3F000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX4GCR6_RESERVED_23_22_DEFVAL #undef DDR_PHY_DX4GCR6_RESERVED_23_22_SHIFT #undef DDR_PHY_DX4GCR6_RESERVED_23_22_MASK -#define DDR_PHY_DX4GCR6_RESERVED_23_22_DEFVAL 0x09090909 -#define DDR_PHY_DX4GCR6_RESERVED_23_22_SHIFT 22 -#define DDR_PHY_DX4GCR6_RESERVED_23_22_MASK 0x00C00000U +#define DDR_PHY_DX4GCR6_RESERVED_23_22_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR6_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX4GCR6_RESERVED_23_22_MASK 0x00C00000U -/*DRAM DQ VREF Select for Rank2*/ +/* +* DRAM DQ VREF Select for Rank2 +*/ #undef DDR_PHY_DX4GCR6_DXDQVREFR2_DEFVAL #undef DDR_PHY_DX4GCR6_DXDQVREFR2_SHIFT #undef DDR_PHY_DX4GCR6_DXDQVREFR2_MASK -#define DDR_PHY_DX4GCR6_DXDQVREFR2_DEFVAL 0x09090909 -#define DDR_PHY_DX4GCR6_DXDQVREFR2_SHIFT 16 -#define DDR_PHY_DX4GCR6_DXDQVREFR2_MASK 0x003F0000U +#define DDR_PHY_DX4GCR6_DXDQVREFR2_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR6_DXDQVREFR2_SHIFT 16 +#define DDR_PHY_DX4GCR6_DXDQVREFR2_MASK 0x003F0000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX4GCR6_RESERVED_15_14_DEFVAL #undef DDR_PHY_DX4GCR6_RESERVED_15_14_SHIFT #undef DDR_PHY_DX4GCR6_RESERVED_15_14_MASK -#define DDR_PHY_DX4GCR6_RESERVED_15_14_DEFVAL 0x09090909 -#define DDR_PHY_DX4GCR6_RESERVED_15_14_SHIFT 14 -#define DDR_PHY_DX4GCR6_RESERVED_15_14_MASK 0x0000C000U +#define DDR_PHY_DX4GCR6_RESERVED_15_14_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR6_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_DX4GCR6_RESERVED_15_14_MASK 0x0000C000U -/*DRAM DQ VREF Select for Rank1*/ +/* +* DRAM DQ VREF Select for Rank1 +*/ #undef DDR_PHY_DX4GCR6_DXDQVREFR1_DEFVAL #undef DDR_PHY_DX4GCR6_DXDQVREFR1_SHIFT #undef DDR_PHY_DX4GCR6_DXDQVREFR1_MASK -#define DDR_PHY_DX4GCR6_DXDQVREFR1_DEFVAL 0x09090909 -#define DDR_PHY_DX4GCR6_DXDQVREFR1_SHIFT 8 -#define DDR_PHY_DX4GCR6_DXDQVREFR1_MASK 0x00003F00U +#define DDR_PHY_DX4GCR6_DXDQVREFR1_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR6_DXDQVREFR1_SHIFT 8 +#define DDR_PHY_DX4GCR6_DXDQVREFR1_MASK 0x00003F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX4GCR6_RESERVED_7_6_DEFVAL #undef DDR_PHY_DX4GCR6_RESERVED_7_6_SHIFT #undef DDR_PHY_DX4GCR6_RESERVED_7_6_MASK -#define DDR_PHY_DX4GCR6_RESERVED_7_6_DEFVAL 0x09090909 -#define DDR_PHY_DX4GCR6_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_DX4GCR6_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_DX4GCR6_RESERVED_7_6_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR6_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX4GCR6_RESERVED_7_6_MASK 0x000000C0U -/*DRAM DQ VREF Select for Rank0*/ +/* +* DRAM DQ VREF Select for Rank0 +*/ #undef DDR_PHY_DX4GCR6_DXDQVREFR0_DEFVAL #undef DDR_PHY_DX4GCR6_DXDQVREFR0_SHIFT #undef DDR_PHY_DX4GCR6_DXDQVREFR0_MASK -#define DDR_PHY_DX4GCR6_DXDQVREFR0_DEFVAL 0x09090909 -#define DDR_PHY_DX4GCR6_DXDQVREFR0_SHIFT 0 -#define DDR_PHY_DX4GCR6_DXDQVREFR0_MASK 0x0000003FU +#define DDR_PHY_DX4GCR6_DXDQVREFR0_DEFVAL 0x09090909 +#define DDR_PHY_DX4GCR6_DXDQVREFR0_SHIFT 0 +#define DDR_PHY_DX4GCR6_DXDQVREFR0_MASK 0x0000003FU -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX4LCDLR2_RESERVED_31_25_DEFVAL -#undef DDR_PHY_DX4LCDLR2_RESERVED_31_25_SHIFT -#undef DDR_PHY_DX4LCDLR2_RESERVED_31_25_MASK -#define DDR_PHY_DX4LCDLR2_RESERVED_31_25_DEFVAL 0x00000000 -#define DDR_PHY_DX4LCDLR2_RESERVED_31_25_SHIFT 25 -#define DDR_PHY_DX4LCDLR2_RESERVED_31_25_MASK 0xFE000000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX4LCDLR2_RESERVED_24_16_DEFVAL -#undef DDR_PHY_DX4LCDLR2_RESERVED_24_16_SHIFT -#undef DDR_PHY_DX4LCDLR2_RESERVED_24_16_MASK -#define DDR_PHY_DX4LCDLR2_RESERVED_24_16_DEFVAL 0x00000000 -#define DDR_PHY_DX4LCDLR2_RESERVED_24_16_SHIFT 16 -#define DDR_PHY_DX4LCDLR2_RESERVED_24_16_MASK 0x01FF0000U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX4LCDLR2_RESERVED_15_9_DEFVAL -#undef DDR_PHY_DX4LCDLR2_RESERVED_15_9_SHIFT -#undef DDR_PHY_DX4LCDLR2_RESERVED_15_9_MASK -#define DDR_PHY_DX4LCDLR2_RESERVED_15_9_DEFVAL 0x00000000 -#define DDR_PHY_DX4LCDLR2_RESERVED_15_9_SHIFT 9 -#define DDR_PHY_DX4LCDLR2_RESERVED_15_9_MASK 0x0000FE00U - -/*Read DQS Gating Delay*/ -#undef DDR_PHY_DX4LCDLR2_DQSGD_DEFVAL -#undef DDR_PHY_DX4LCDLR2_DQSGD_SHIFT -#undef DDR_PHY_DX4LCDLR2_DQSGD_MASK -#define DDR_PHY_DX4LCDLR2_DQSGD_DEFVAL 0x00000000 -#define DDR_PHY_DX4LCDLR2_DQSGD_SHIFT 0 -#define DDR_PHY_DX4LCDLR2_DQSGD_MASK 0x000001FFU - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX4GTR0_RESERVED_31_24_DEFVAL -#undef DDR_PHY_DX4GTR0_RESERVED_31_24_SHIFT -#undef DDR_PHY_DX4GTR0_RESERVED_31_24_MASK -#define DDR_PHY_DX4GTR0_RESERVED_31_24_DEFVAL 0x00020000 -#define DDR_PHY_DX4GTR0_RESERVED_31_24_SHIFT 27 -#define DDR_PHY_DX4GTR0_RESERVED_31_24_MASK 0xF8000000U - -/*DQ Write Path Latency Pipeline*/ -#undef DDR_PHY_DX4GTR0_WDQSL_DEFVAL -#undef DDR_PHY_DX4GTR0_WDQSL_SHIFT -#undef DDR_PHY_DX4GTR0_WDQSL_MASK -#define DDR_PHY_DX4GTR0_WDQSL_DEFVAL 0x00020000 -#define DDR_PHY_DX4GTR0_WDQSL_SHIFT 24 -#define DDR_PHY_DX4GTR0_WDQSL_MASK 0x07000000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX4GTR0_RESERVED_23_20_DEFVAL -#undef DDR_PHY_DX4GTR0_RESERVED_23_20_SHIFT -#undef DDR_PHY_DX4GTR0_RESERVED_23_20_MASK -#define DDR_PHY_DX4GTR0_RESERVED_23_20_DEFVAL 0x00020000 -#define DDR_PHY_DX4GTR0_RESERVED_23_20_SHIFT 20 -#define DDR_PHY_DX4GTR0_RESERVED_23_20_MASK 0x00F00000U - -/*Write Leveling System Latency*/ -#undef DDR_PHY_DX4GTR0_WLSL_DEFVAL -#undef DDR_PHY_DX4GTR0_WLSL_SHIFT -#undef DDR_PHY_DX4GTR0_WLSL_MASK -#define DDR_PHY_DX4GTR0_WLSL_DEFVAL 0x00020000 -#define DDR_PHY_DX4GTR0_WLSL_SHIFT 16 -#define DDR_PHY_DX4GTR0_WLSL_MASK 0x000F0000U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX4GTR0_RESERVED_15_13_DEFVAL -#undef DDR_PHY_DX4GTR0_RESERVED_15_13_SHIFT -#undef DDR_PHY_DX4GTR0_RESERVED_15_13_MASK -#define DDR_PHY_DX4GTR0_RESERVED_15_13_DEFVAL 0x00020000 -#define DDR_PHY_DX4GTR0_RESERVED_15_13_SHIFT 13 -#define DDR_PHY_DX4GTR0_RESERVED_15_13_MASK 0x0000E000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX4GTR0_RESERVED_12_8_DEFVAL -#undef DDR_PHY_DX4GTR0_RESERVED_12_8_SHIFT -#undef DDR_PHY_DX4GTR0_RESERVED_12_8_MASK -#define DDR_PHY_DX4GTR0_RESERVED_12_8_DEFVAL 0x00020000 -#define DDR_PHY_DX4GTR0_RESERVED_12_8_SHIFT 8 -#define DDR_PHY_DX4GTR0_RESERVED_12_8_MASK 0x00001F00U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX4GTR0_RESERVED_7_5_DEFVAL -#undef DDR_PHY_DX4GTR0_RESERVED_7_5_SHIFT -#undef DDR_PHY_DX4GTR0_RESERVED_7_5_MASK -#define DDR_PHY_DX4GTR0_RESERVED_7_5_DEFVAL 0x00020000 -#define DDR_PHY_DX4GTR0_RESERVED_7_5_SHIFT 5 -#define DDR_PHY_DX4GTR0_RESERVED_7_5_MASK 0x000000E0U - -/*DQS Gating System Latency*/ -#undef DDR_PHY_DX4GTR0_DGSL_DEFVAL -#undef DDR_PHY_DX4GTR0_DGSL_SHIFT -#undef DDR_PHY_DX4GTR0_DGSL_MASK -#define DDR_PHY_DX4GTR0_DGSL_DEFVAL 0x00020000 -#define DDR_PHY_DX4GTR0_DGSL_SHIFT 0 -#define DDR_PHY_DX4GTR0_DGSL_MASK 0x0000001FU - -/*Calibration Bypass*/ +/* +* Calibration Bypass +*/ #undef DDR_PHY_DX5GCR0_CALBYP_DEFVAL #undef DDR_PHY_DX5GCR0_CALBYP_SHIFT #undef DDR_PHY_DX5GCR0_CALBYP_MASK -#define DDR_PHY_DX5GCR0_CALBYP_DEFVAL 0x40200204 -#define DDR_PHY_DX5GCR0_CALBYP_SHIFT 31 -#define DDR_PHY_DX5GCR0_CALBYP_MASK 0x80000000U +#define DDR_PHY_DX5GCR0_CALBYP_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_CALBYP_SHIFT 31 +#define DDR_PHY_DX5GCR0_CALBYP_MASK 0x80000000U -/*Master Delay Line Enable*/ +/* +* Master Delay Line Enable +*/ #undef DDR_PHY_DX5GCR0_MDLEN_DEFVAL #undef DDR_PHY_DX5GCR0_MDLEN_SHIFT #undef DDR_PHY_DX5GCR0_MDLEN_MASK -#define DDR_PHY_DX5GCR0_MDLEN_DEFVAL 0x40200204 -#define DDR_PHY_DX5GCR0_MDLEN_SHIFT 30 -#define DDR_PHY_DX5GCR0_MDLEN_MASK 0x40000000U +#define DDR_PHY_DX5GCR0_MDLEN_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_MDLEN_SHIFT 30 +#define DDR_PHY_DX5GCR0_MDLEN_MASK 0x40000000U -/*Configurable ODT(TE) Phase Shift*/ +/* +* Configurable ODT(TE) Phase Shift +*/ #undef DDR_PHY_DX5GCR0_CODTSHFT_DEFVAL #undef DDR_PHY_DX5GCR0_CODTSHFT_SHIFT #undef DDR_PHY_DX5GCR0_CODTSHFT_MASK -#define DDR_PHY_DX5GCR0_CODTSHFT_DEFVAL 0x40200204 -#define DDR_PHY_DX5GCR0_CODTSHFT_SHIFT 28 -#define DDR_PHY_DX5GCR0_CODTSHFT_MASK 0x30000000U +#define DDR_PHY_DX5GCR0_CODTSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_CODTSHFT_SHIFT 28 +#define DDR_PHY_DX5GCR0_CODTSHFT_MASK 0x30000000U -/*DQS Duty Cycle Correction*/ +/* +* DQS Duty Cycle Correction +*/ #undef DDR_PHY_DX5GCR0_DQSDCC_DEFVAL #undef DDR_PHY_DX5GCR0_DQSDCC_SHIFT #undef DDR_PHY_DX5GCR0_DQSDCC_MASK -#define DDR_PHY_DX5GCR0_DQSDCC_DEFVAL 0x40200204 -#define DDR_PHY_DX5GCR0_DQSDCC_SHIFT 24 -#define DDR_PHY_DX5GCR0_DQSDCC_MASK 0x0F000000U +#define DDR_PHY_DX5GCR0_DQSDCC_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_DQSDCC_SHIFT 24 +#define DDR_PHY_DX5GCR0_DQSDCC_MASK 0x0F000000U -/*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/ +/* +* Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY +*/ #undef DDR_PHY_DX5GCR0_RDDLY_DEFVAL #undef DDR_PHY_DX5GCR0_RDDLY_SHIFT #undef DDR_PHY_DX5GCR0_RDDLY_MASK -#define DDR_PHY_DX5GCR0_RDDLY_DEFVAL 0x40200204 -#define DDR_PHY_DX5GCR0_RDDLY_SHIFT 20 -#define DDR_PHY_DX5GCR0_RDDLY_MASK 0x00F00000U +#define DDR_PHY_DX5GCR0_RDDLY_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_RDDLY_SHIFT 20 +#define DDR_PHY_DX5GCR0_RDDLY_MASK 0x00F00000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX5GCR0_RESERVED_19_14_DEFVAL #undef DDR_PHY_DX5GCR0_RESERVED_19_14_SHIFT #undef DDR_PHY_DX5GCR0_RESERVED_19_14_MASK -#define DDR_PHY_DX5GCR0_RESERVED_19_14_DEFVAL 0x40200204 -#define DDR_PHY_DX5GCR0_RESERVED_19_14_SHIFT 14 -#define DDR_PHY_DX5GCR0_RESERVED_19_14_MASK 0x000FC000U +#define DDR_PHY_DX5GCR0_RESERVED_19_14_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_RESERVED_19_14_SHIFT 14 +#define DDR_PHY_DX5GCR0_RESERVED_19_14_MASK 0x000FC000U -/*DQSNSE Power Down Receiver*/ +/* +* DQSNSE Power Down Receiver +*/ #undef DDR_PHY_DX5GCR0_DQSNSEPDR_DEFVAL #undef DDR_PHY_DX5GCR0_DQSNSEPDR_SHIFT #undef DDR_PHY_DX5GCR0_DQSNSEPDR_MASK -#define DDR_PHY_DX5GCR0_DQSNSEPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX5GCR0_DQSNSEPDR_SHIFT 13 -#define DDR_PHY_DX5GCR0_DQSNSEPDR_MASK 0x00002000U +#define DDR_PHY_DX5GCR0_DQSNSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_DQSNSEPDR_SHIFT 13 +#define DDR_PHY_DX5GCR0_DQSNSEPDR_MASK 0x00002000U -/*DQSSE Power Down Receiver*/ +/* +* DQSSE Power Down Receiver +*/ #undef DDR_PHY_DX5GCR0_DQSSEPDR_DEFVAL #undef DDR_PHY_DX5GCR0_DQSSEPDR_SHIFT #undef DDR_PHY_DX5GCR0_DQSSEPDR_MASK -#define DDR_PHY_DX5GCR0_DQSSEPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX5GCR0_DQSSEPDR_SHIFT 12 -#define DDR_PHY_DX5GCR0_DQSSEPDR_MASK 0x00001000U +#define DDR_PHY_DX5GCR0_DQSSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_DQSSEPDR_SHIFT 12 +#define DDR_PHY_DX5GCR0_DQSSEPDR_MASK 0x00001000U -/*RTT On Additive Latency*/ +/* +* RTT On Additive Latency +*/ #undef DDR_PHY_DX5GCR0_RTTOAL_DEFVAL #undef DDR_PHY_DX5GCR0_RTTOAL_SHIFT #undef DDR_PHY_DX5GCR0_RTTOAL_MASK -#define DDR_PHY_DX5GCR0_RTTOAL_DEFVAL 0x40200204 -#define DDR_PHY_DX5GCR0_RTTOAL_SHIFT 11 -#define DDR_PHY_DX5GCR0_RTTOAL_MASK 0x00000800U +#define DDR_PHY_DX5GCR0_RTTOAL_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_RTTOAL_SHIFT 11 +#define DDR_PHY_DX5GCR0_RTTOAL_MASK 0x00000800U -/*RTT Output Hold*/ +/* +* RTT Output Hold +*/ #undef DDR_PHY_DX5GCR0_RTTOH_DEFVAL #undef DDR_PHY_DX5GCR0_RTTOH_SHIFT #undef DDR_PHY_DX5GCR0_RTTOH_MASK -#define DDR_PHY_DX5GCR0_RTTOH_DEFVAL 0x40200204 -#define DDR_PHY_DX5GCR0_RTTOH_SHIFT 9 -#define DDR_PHY_DX5GCR0_RTTOH_MASK 0x00000600U +#define DDR_PHY_DX5GCR0_RTTOH_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_RTTOH_SHIFT 9 +#define DDR_PHY_DX5GCR0_RTTOH_MASK 0x00000600U -/*Configurable PDR Phase Shift*/ +/* +* Configurable PDR Phase Shift +*/ #undef DDR_PHY_DX5GCR0_CPDRSHFT_DEFVAL #undef DDR_PHY_DX5GCR0_CPDRSHFT_SHIFT #undef DDR_PHY_DX5GCR0_CPDRSHFT_MASK -#define DDR_PHY_DX5GCR0_CPDRSHFT_DEFVAL 0x40200204 -#define DDR_PHY_DX5GCR0_CPDRSHFT_SHIFT 7 -#define DDR_PHY_DX5GCR0_CPDRSHFT_MASK 0x00000180U +#define DDR_PHY_DX5GCR0_CPDRSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_CPDRSHFT_SHIFT 7 +#define DDR_PHY_DX5GCR0_CPDRSHFT_MASK 0x00000180U -/*DQSR Power Down*/ +/* +* DQSR Power Down +*/ #undef DDR_PHY_DX5GCR0_DQSRPD_DEFVAL #undef DDR_PHY_DX5GCR0_DQSRPD_SHIFT #undef DDR_PHY_DX5GCR0_DQSRPD_MASK -#define DDR_PHY_DX5GCR0_DQSRPD_DEFVAL 0x40200204 -#define DDR_PHY_DX5GCR0_DQSRPD_SHIFT 6 -#define DDR_PHY_DX5GCR0_DQSRPD_MASK 0x00000040U +#define DDR_PHY_DX5GCR0_DQSRPD_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_DQSRPD_SHIFT 6 +#define DDR_PHY_DX5GCR0_DQSRPD_MASK 0x00000040U -/*DQSG Power Down Receiver*/ +/* +* DQSG Power Down Receiver +*/ #undef DDR_PHY_DX5GCR0_DQSGPDR_DEFVAL #undef DDR_PHY_DX5GCR0_DQSGPDR_SHIFT #undef DDR_PHY_DX5GCR0_DQSGPDR_MASK -#define DDR_PHY_DX5GCR0_DQSGPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX5GCR0_DQSGPDR_SHIFT 5 -#define DDR_PHY_DX5GCR0_DQSGPDR_MASK 0x00000020U +#define DDR_PHY_DX5GCR0_DQSGPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_DQSGPDR_SHIFT 5 +#define DDR_PHY_DX5GCR0_DQSGPDR_MASK 0x00000020U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX5GCR0_RESERVED_4_DEFVAL #undef DDR_PHY_DX5GCR0_RESERVED_4_SHIFT #undef DDR_PHY_DX5GCR0_RESERVED_4_MASK -#define DDR_PHY_DX5GCR0_RESERVED_4_DEFVAL 0x40200204 -#define DDR_PHY_DX5GCR0_RESERVED_4_SHIFT 4 -#define DDR_PHY_DX5GCR0_RESERVED_4_MASK 0x00000010U +#define DDR_PHY_DX5GCR0_RESERVED_4_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_RESERVED_4_SHIFT 4 +#define DDR_PHY_DX5GCR0_RESERVED_4_MASK 0x00000010U -/*DQSG On-Die Termination*/ +/* +* DQSG On-Die Termination +*/ #undef DDR_PHY_DX5GCR0_DQSGODT_DEFVAL #undef DDR_PHY_DX5GCR0_DQSGODT_SHIFT #undef DDR_PHY_DX5GCR0_DQSGODT_MASK -#define DDR_PHY_DX5GCR0_DQSGODT_DEFVAL 0x40200204 -#define DDR_PHY_DX5GCR0_DQSGODT_SHIFT 3 -#define DDR_PHY_DX5GCR0_DQSGODT_MASK 0x00000008U +#define DDR_PHY_DX5GCR0_DQSGODT_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_DQSGODT_SHIFT 3 +#define DDR_PHY_DX5GCR0_DQSGODT_MASK 0x00000008U -/*DQSG Output Enable*/ +/* +* DQSG Output Enable +*/ #undef DDR_PHY_DX5GCR0_DQSGOE_DEFVAL #undef DDR_PHY_DX5GCR0_DQSGOE_SHIFT #undef DDR_PHY_DX5GCR0_DQSGOE_MASK -#define DDR_PHY_DX5GCR0_DQSGOE_DEFVAL 0x40200204 -#define DDR_PHY_DX5GCR0_DQSGOE_SHIFT 2 -#define DDR_PHY_DX5GCR0_DQSGOE_MASK 0x00000004U +#define DDR_PHY_DX5GCR0_DQSGOE_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_DQSGOE_SHIFT 2 +#define DDR_PHY_DX5GCR0_DQSGOE_MASK 0x00000004U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX5GCR0_RESERVED_1_0_DEFVAL #undef DDR_PHY_DX5GCR0_RESERVED_1_0_SHIFT #undef DDR_PHY_DX5GCR0_RESERVED_1_0_MASK -#define DDR_PHY_DX5GCR0_RESERVED_1_0_DEFVAL 0x40200204 -#define DDR_PHY_DX5GCR0_RESERVED_1_0_SHIFT 0 -#define DDR_PHY_DX5GCR0_RESERVED_1_0_MASK 0x00000003U +#define DDR_PHY_DX5GCR0_RESERVED_1_0_DEFVAL 0x40200204 +#define DDR_PHY_DX5GCR0_RESERVED_1_0_SHIFT 0 +#define DDR_PHY_DX5GCR0_RESERVED_1_0_MASK 0x00000003U -/*Enables the PDR mode for DQ[7:0]*/ +/* +* Enables the PDR mode for DQ[7:0] +*/ #undef DDR_PHY_DX5GCR1_DXPDRMODE_DEFVAL #undef DDR_PHY_DX5GCR1_DXPDRMODE_SHIFT #undef DDR_PHY_DX5GCR1_DXPDRMODE_MASK -#define DDR_PHY_DX5GCR1_DXPDRMODE_DEFVAL 0x00007FFF -#define DDR_PHY_DX5GCR1_DXPDRMODE_SHIFT 16 -#define DDR_PHY_DX5GCR1_DXPDRMODE_MASK 0xFFFF0000U +#define DDR_PHY_DX5GCR1_DXPDRMODE_DEFVAL 0x00007FFF +#define DDR_PHY_DX5GCR1_DXPDRMODE_SHIFT 16 +#define DDR_PHY_DX5GCR1_DXPDRMODE_MASK 0xFFFF0000U -/*Reserved. Returns zeroes on reads.*/ +/* +* Reserved. Returns zeroes on reads. +*/ #undef DDR_PHY_DX5GCR1_RESERVED_15_DEFVAL #undef DDR_PHY_DX5GCR1_RESERVED_15_SHIFT #undef DDR_PHY_DX5GCR1_RESERVED_15_MASK -#define DDR_PHY_DX5GCR1_RESERVED_15_DEFVAL 0x00007FFF -#define DDR_PHY_DX5GCR1_RESERVED_15_SHIFT 15 -#define DDR_PHY_DX5GCR1_RESERVED_15_MASK 0x00008000U +#define DDR_PHY_DX5GCR1_RESERVED_15_DEFVAL 0x00007FFF +#define DDR_PHY_DX5GCR1_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX5GCR1_RESERVED_15_MASK 0x00008000U -/*Select the delayed or non-delayed read data strobe #*/ +/* +* Select the delayed or non-delayed read data strobe # +*/ #undef DDR_PHY_DX5GCR1_QSNSEL_DEFVAL #undef DDR_PHY_DX5GCR1_QSNSEL_SHIFT #undef DDR_PHY_DX5GCR1_QSNSEL_MASK -#define DDR_PHY_DX5GCR1_QSNSEL_DEFVAL 0x00007FFF -#define DDR_PHY_DX5GCR1_QSNSEL_SHIFT 14 -#define DDR_PHY_DX5GCR1_QSNSEL_MASK 0x00004000U +#define DDR_PHY_DX5GCR1_QSNSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX5GCR1_QSNSEL_SHIFT 14 +#define DDR_PHY_DX5GCR1_QSNSEL_MASK 0x00004000U -/*Select the delayed or non-delayed read data strobe*/ +/* +* Select the delayed or non-delayed read data strobe +*/ #undef DDR_PHY_DX5GCR1_QSSEL_DEFVAL #undef DDR_PHY_DX5GCR1_QSSEL_SHIFT #undef DDR_PHY_DX5GCR1_QSSEL_MASK -#define DDR_PHY_DX5GCR1_QSSEL_DEFVAL 0x00007FFF -#define DDR_PHY_DX5GCR1_QSSEL_SHIFT 13 -#define DDR_PHY_DX5GCR1_QSSEL_MASK 0x00002000U +#define DDR_PHY_DX5GCR1_QSSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX5GCR1_QSSEL_SHIFT 13 +#define DDR_PHY_DX5GCR1_QSSEL_MASK 0x00002000U -/*Enables Read Data Strobe in a byte lane*/ +/* +* Enables Read Data Strobe in a byte lane +*/ #undef DDR_PHY_DX5GCR1_OEEN_DEFVAL #undef DDR_PHY_DX5GCR1_OEEN_SHIFT #undef DDR_PHY_DX5GCR1_OEEN_MASK -#define DDR_PHY_DX5GCR1_OEEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX5GCR1_OEEN_SHIFT 12 -#define DDR_PHY_DX5GCR1_OEEN_MASK 0x00001000U +#define DDR_PHY_DX5GCR1_OEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX5GCR1_OEEN_SHIFT 12 +#define DDR_PHY_DX5GCR1_OEEN_MASK 0x00001000U -/*Enables PDR in a byte lane*/ +/* +* Enables PDR in a byte lane +*/ #undef DDR_PHY_DX5GCR1_PDREN_DEFVAL #undef DDR_PHY_DX5GCR1_PDREN_SHIFT #undef DDR_PHY_DX5GCR1_PDREN_MASK -#define DDR_PHY_DX5GCR1_PDREN_DEFVAL 0x00007FFF -#define DDR_PHY_DX5GCR1_PDREN_SHIFT 11 -#define DDR_PHY_DX5GCR1_PDREN_MASK 0x00000800U +#define DDR_PHY_DX5GCR1_PDREN_DEFVAL 0x00007FFF +#define DDR_PHY_DX5GCR1_PDREN_SHIFT 11 +#define DDR_PHY_DX5GCR1_PDREN_MASK 0x00000800U -/*Enables ODT/TE in a byte lane*/ +/* +* Enables ODT/TE in a byte lane +*/ #undef DDR_PHY_DX5GCR1_TEEN_DEFVAL #undef DDR_PHY_DX5GCR1_TEEN_SHIFT #undef DDR_PHY_DX5GCR1_TEEN_MASK -#define DDR_PHY_DX5GCR1_TEEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX5GCR1_TEEN_SHIFT 10 -#define DDR_PHY_DX5GCR1_TEEN_MASK 0x00000400U +#define DDR_PHY_DX5GCR1_TEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX5GCR1_TEEN_SHIFT 10 +#define DDR_PHY_DX5GCR1_TEEN_MASK 0x00000400U -/*Enables Write Data strobe in a byte lane*/ +/* +* Enables Write Data strobe in a byte lane +*/ #undef DDR_PHY_DX5GCR1_DSEN_DEFVAL #undef DDR_PHY_DX5GCR1_DSEN_SHIFT #undef DDR_PHY_DX5GCR1_DSEN_MASK -#define DDR_PHY_DX5GCR1_DSEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX5GCR1_DSEN_SHIFT 9 -#define DDR_PHY_DX5GCR1_DSEN_MASK 0x00000200U +#define DDR_PHY_DX5GCR1_DSEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX5GCR1_DSEN_SHIFT 9 +#define DDR_PHY_DX5GCR1_DSEN_MASK 0x00000200U -/*Enables DM pin in a byte lane*/ +/* +* Enables DM pin in a byte lane +*/ #undef DDR_PHY_DX5GCR1_DMEN_DEFVAL #undef DDR_PHY_DX5GCR1_DMEN_SHIFT #undef DDR_PHY_DX5GCR1_DMEN_MASK -#define DDR_PHY_DX5GCR1_DMEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX5GCR1_DMEN_SHIFT 8 -#define DDR_PHY_DX5GCR1_DMEN_MASK 0x00000100U +#define DDR_PHY_DX5GCR1_DMEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX5GCR1_DMEN_SHIFT 8 +#define DDR_PHY_DX5GCR1_DMEN_MASK 0x00000100U -/*Enables DQ corresponding to each bit in a byte*/ +/* +* Enables DQ corresponding to each bit in a byte +*/ #undef DDR_PHY_DX5GCR1_DQEN_DEFVAL #undef DDR_PHY_DX5GCR1_DQEN_SHIFT #undef DDR_PHY_DX5GCR1_DQEN_MASK -#define DDR_PHY_DX5GCR1_DQEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX5GCR1_DQEN_SHIFT 0 -#define DDR_PHY_DX5GCR1_DQEN_MASK 0x000000FFU +#define DDR_PHY_DX5GCR1_DQEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX5GCR1_DQEN_SHIFT 0 +#define DDR_PHY_DX5GCR1_DQEN_MASK 0x000000FFU -/*Byte lane VREF IOM (Used only by D4MU IOs)*/ +/* +* Byte lane VREF IOM (Used only by D4MU IOs) +*/ #undef DDR_PHY_DX5GCR4_RESERVED_31_29_DEFVAL #undef DDR_PHY_DX5GCR4_RESERVED_31_29_SHIFT #undef DDR_PHY_DX5GCR4_RESERVED_31_29_MASK -#define DDR_PHY_DX5GCR4_RESERVED_31_29_DEFVAL 0x0E00003C -#define DDR_PHY_DX5GCR4_RESERVED_31_29_SHIFT 29 -#define DDR_PHY_DX5GCR4_RESERVED_31_29_MASK 0xE0000000U +#define DDR_PHY_DX5GCR4_RESERVED_31_29_DEFVAL 0x0E00003C +#define DDR_PHY_DX5GCR4_RESERVED_31_29_SHIFT 29 +#define DDR_PHY_DX5GCR4_RESERVED_31_29_MASK 0xE0000000U -/*Byte Lane VREF Pad Enable*/ +/* +* Byte Lane VREF Pad Enable +*/ #undef DDR_PHY_DX5GCR4_DXREFPEN_DEFVAL #undef DDR_PHY_DX5GCR4_DXREFPEN_SHIFT #undef DDR_PHY_DX5GCR4_DXREFPEN_MASK -#define DDR_PHY_DX5GCR4_DXREFPEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX5GCR4_DXREFPEN_SHIFT 28 -#define DDR_PHY_DX5GCR4_DXREFPEN_MASK 0x10000000U +#define DDR_PHY_DX5GCR4_DXREFPEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX5GCR4_DXREFPEN_SHIFT 28 +#define DDR_PHY_DX5GCR4_DXREFPEN_MASK 0x10000000U -/*Byte Lane Internal VREF Enable*/ +/* +* Byte Lane Internal VREF Enable +*/ #undef DDR_PHY_DX5GCR4_DXREFEEN_DEFVAL #undef DDR_PHY_DX5GCR4_DXREFEEN_SHIFT #undef DDR_PHY_DX5GCR4_DXREFEEN_MASK -#define DDR_PHY_DX5GCR4_DXREFEEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX5GCR4_DXREFEEN_SHIFT 26 -#define DDR_PHY_DX5GCR4_DXREFEEN_MASK 0x0C000000U +#define DDR_PHY_DX5GCR4_DXREFEEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX5GCR4_DXREFEEN_SHIFT 26 +#define DDR_PHY_DX5GCR4_DXREFEEN_MASK 0x0C000000U -/*Byte Lane Single-End VREF Enable*/ +/* +* Byte Lane Single-End VREF Enable +*/ #undef DDR_PHY_DX5GCR4_DXREFSEN_DEFVAL #undef DDR_PHY_DX5GCR4_DXREFSEN_SHIFT #undef DDR_PHY_DX5GCR4_DXREFSEN_MASK -#define DDR_PHY_DX5GCR4_DXREFSEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX5GCR4_DXREFSEN_SHIFT 25 -#define DDR_PHY_DX5GCR4_DXREFSEN_MASK 0x02000000U +#define DDR_PHY_DX5GCR4_DXREFSEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX5GCR4_DXREFSEN_SHIFT 25 +#define DDR_PHY_DX5GCR4_DXREFSEN_MASK 0x02000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX5GCR4_RESERVED_24_DEFVAL #undef DDR_PHY_DX5GCR4_RESERVED_24_SHIFT #undef DDR_PHY_DX5GCR4_RESERVED_24_MASK -#define DDR_PHY_DX5GCR4_RESERVED_24_DEFVAL 0x0E00003C -#define DDR_PHY_DX5GCR4_RESERVED_24_SHIFT 24 -#define DDR_PHY_DX5GCR4_RESERVED_24_MASK 0x01000000U +#define DDR_PHY_DX5GCR4_RESERVED_24_DEFVAL 0x0E00003C +#define DDR_PHY_DX5GCR4_RESERVED_24_SHIFT 24 +#define DDR_PHY_DX5GCR4_RESERVED_24_MASK 0x01000000U -/*External VREF generator REFSEL range select*/ +/* +* External VREF generator REFSEL range select +*/ #undef DDR_PHY_DX5GCR4_DXREFESELRANGE_DEFVAL #undef DDR_PHY_DX5GCR4_DXREFESELRANGE_SHIFT #undef DDR_PHY_DX5GCR4_DXREFESELRANGE_MASK -#define DDR_PHY_DX5GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C -#define DDR_PHY_DX5GCR4_DXREFESELRANGE_SHIFT 23 -#define DDR_PHY_DX5GCR4_DXREFESELRANGE_MASK 0x00800000U +#define DDR_PHY_DX5GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX5GCR4_DXREFESELRANGE_SHIFT 23 +#define DDR_PHY_DX5GCR4_DXREFESELRANGE_MASK 0x00800000U -/*Byte Lane External VREF Select*/ +/* +* Byte Lane External VREF Select +*/ #undef DDR_PHY_DX5GCR4_DXREFESEL_DEFVAL #undef DDR_PHY_DX5GCR4_DXREFESEL_SHIFT #undef DDR_PHY_DX5GCR4_DXREFESEL_MASK -#define DDR_PHY_DX5GCR4_DXREFESEL_DEFVAL 0x0E00003C -#define DDR_PHY_DX5GCR4_DXREFESEL_SHIFT 16 -#define DDR_PHY_DX5GCR4_DXREFESEL_MASK 0x007F0000U +#define DDR_PHY_DX5GCR4_DXREFESEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX5GCR4_DXREFESEL_SHIFT 16 +#define DDR_PHY_DX5GCR4_DXREFESEL_MASK 0x007F0000U -/*Single ended VREF generator REFSEL range select*/ +/* +* Single ended VREF generator REFSEL range select +*/ #undef DDR_PHY_DX5GCR4_DXREFSSELRANGE_DEFVAL #undef DDR_PHY_DX5GCR4_DXREFSSELRANGE_SHIFT #undef DDR_PHY_DX5GCR4_DXREFSSELRANGE_MASK -#define DDR_PHY_DX5GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C -#define DDR_PHY_DX5GCR4_DXREFSSELRANGE_SHIFT 15 -#define DDR_PHY_DX5GCR4_DXREFSSELRANGE_MASK 0x00008000U +#define DDR_PHY_DX5GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX5GCR4_DXREFSSELRANGE_SHIFT 15 +#define DDR_PHY_DX5GCR4_DXREFSSELRANGE_MASK 0x00008000U -/*Byte Lane Single-End VREF Select*/ +/* +* Byte Lane Single-End VREF Select +*/ #undef DDR_PHY_DX5GCR4_DXREFSSEL_DEFVAL #undef DDR_PHY_DX5GCR4_DXREFSSEL_SHIFT #undef DDR_PHY_DX5GCR4_DXREFSSEL_MASK -#define DDR_PHY_DX5GCR4_DXREFSSEL_DEFVAL 0x0E00003C -#define DDR_PHY_DX5GCR4_DXREFSSEL_SHIFT 8 -#define DDR_PHY_DX5GCR4_DXREFSSEL_MASK 0x00007F00U +#define DDR_PHY_DX5GCR4_DXREFSSEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX5GCR4_DXREFSSEL_SHIFT 8 +#define DDR_PHY_DX5GCR4_DXREFSSEL_MASK 0x00007F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX5GCR4_RESERVED_7_6_DEFVAL #undef DDR_PHY_DX5GCR4_RESERVED_7_6_SHIFT #undef DDR_PHY_DX5GCR4_RESERVED_7_6_MASK -#define DDR_PHY_DX5GCR4_RESERVED_7_6_DEFVAL 0x0E00003C -#define DDR_PHY_DX5GCR4_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_DX5GCR4_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_DX5GCR4_RESERVED_7_6_DEFVAL 0x0E00003C +#define DDR_PHY_DX5GCR4_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX5GCR4_RESERVED_7_6_MASK 0x000000C0U -/*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/ +/* +* VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. +*/ #undef DDR_PHY_DX5GCR4_DXREFIEN_DEFVAL #undef DDR_PHY_DX5GCR4_DXREFIEN_SHIFT #undef DDR_PHY_DX5GCR4_DXREFIEN_MASK -#define DDR_PHY_DX5GCR4_DXREFIEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX5GCR4_DXREFIEN_SHIFT 2 -#define DDR_PHY_DX5GCR4_DXREFIEN_MASK 0x0000003CU +#define DDR_PHY_DX5GCR4_DXREFIEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX5GCR4_DXREFIEN_SHIFT 2 +#define DDR_PHY_DX5GCR4_DXREFIEN_MASK 0x0000003CU -/*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/ +/* +* VRMON control for DQ IO (Single Ended) buffers of a byte lane. +*/ #undef DDR_PHY_DX5GCR4_DXREFIMON_DEFVAL #undef DDR_PHY_DX5GCR4_DXREFIMON_SHIFT #undef DDR_PHY_DX5GCR4_DXREFIMON_MASK -#define DDR_PHY_DX5GCR4_DXREFIMON_DEFVAL 0x0E00003C -#define DDR_PHY_DX5GCR4_DXREFIMON_SHIFT 0 -#define DDR_PHY_DX5GCR4_DXREFIMON_MASK 0x00000003U +#define DDR_PHY_DX5GCR4_DXREFIMON_DEFVAL 0x0E00003C +#define DDR_PHY_DX5GCR4_DXREFIMON_SHIFT 0 +#define DDR_PHY_DX5GCR4_DXREFIMON_MASK 0x00000003U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX5GCR5_RESERVED_31_DEFVAL #undef DDR_PHY_DX5GCR5_RESERVED_31_SHIFT #undef DDR_PHY_DX5GCR5_RESERVED_31_MASK -#define DDR_PHY_DX5GCR5_RESERVED_31_DEFVAL 0x09090909 -#define DDR_PHY_DX5GCR5_RESERVED_31_SHIFT 31 -#define DDR_PHY_DX5GCR5_RESERVED_31_MASK 0x80000000U +#define DDR_PHY_DX5GCR5_RESERVED_31_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR5_RESERVED_31_SHIFT 31 +#define DDR_PHY_DX5GCR5_RESERVED_31_MASK 0x80000000U -/*Byte Lane internal VREF Select for Rank 3*/ +/* +* Byte Lane internal VREF Select for Rank 3 +*/ #undef DDR_PHY_DX5GCR5_DXREFISELR3_DEFVAL #undef DDR_PHY_DX5GCR5_DXREFISELR3_SHIFT #undef DDR_PHY_DX5GCR5_DXREFISELR3_MASK -#define DDR_PHY_DX5GCR5_DXREFISELR3_DEFVAL 0x09090909 -#define DDR_PHY_DX5GCR5_DXREFISELR3_SHIFT 24 -#define DDR_PHY_DX5GCR5_DXREFISELR3_MASK 0x7F000000U +#define DDR_PHY_DX5GCR5_DXREFISELR3_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR5_DXREFISELR3_SHIFT 24 +#define DDR_PHY_DX5GCR5_DXREFISELR3_MASK 0x7F000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX5GCR5_RESERVED_23_DEFVAL #undef DDR_PHY_DX5GCR5_RESERVED_23_SHIFT #undef DDR_PHY_DX5GCR5_RESERVED_23_MASK -#define DDR_PHY_DX5GCR5_RESERVED_23_DEFVAL 0x09090909 -#define DDR_PHY_DX5GCR5_RESERVED_23_SHIFT 23 -#define DDR_PHY_DX5GCR5_RESERVED_23_MASK 0x00800000U +#define DDR_PHY_DX5GCR5_RESERVED_23_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR5_RESERVED_23_SHIFT 23 +#define DDR_PHY_DX5GCR5_RESERVED_23_MASK 0x00800000U -/*Byte Lane internal VREF Select for Rank 2*/ +/* +* Byte Lane internal VREF Select for Rank 2 +*/ #undef DDR_PHY_DX5GCR5_DXREFISELR2_DEFVAL #undef DDR_PHY_DX5GCR5_DXREFISELR2_SHIFT #undef DDR_PHY_DX5GCR5_DXREFISELR2_MASK -#define DDR_PHY_DX5GCR5_DXREFISELR2_DEFVAL 0x09090909 -#define DDR_PHY_DX5GCR5_DXREFISELR2_SHIFT 16 -#define DDR_PHY_DX5GCR5_DXREFISELR2_MASK 0x007F0000U +#define DDR_PHY_DX5GCR5_DXREFISELR2_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR5_DXREFISELR2_SHIFT 16 +#define DDR_PHY_DX5GCR5_DXREFISELR2_MASK 0x007F0000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX5GCR5_RESERVED_15_DEFVAL #undef DDR_PHY_DX5GCR5_RESERVED_15_SHIFT #undef DDR_PHY_DX5GCR5_RESERVED_15_MASK -#define DDR_PHY_DX5GCR5_RESERVED_15_DEFVAL 0x09090909 -#define DDR_PHY_DX5GCR5_RESERVED_15_SHIFT 15 -#define DDR_PHY_DX5GCR5_RESERVED_15_MASK 0x00008000U +#define DDR_PHY_DX5GCR5_RESERVED_15_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR5_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX5GCR5_RESERVED_15_MASK 0x00008000U -/*Byte Lane internal VREF Select for Rank 1*/ +/* +* Byte Lane internal VREF Select for Rank 1 +*/ #undef DDR_PHY_DX5GCR5_DXREFISELR1_DEFVAL #undef DDR_PHY_DX5GCR5_DXREFISELR1_SHIFT #undef DDR_PHY_DX5GCR5_DXREFISELR1_MASK -#define DDR_PHY_DX5GCR5_DXREFISELR1_DEFVAL 0x09090909 -#define DDR_PHY_DX5GCR5_DXREFISELR1_SHIFT 8 -#define DDR_PHY_DX5GCR5_DXREFISELR1_MASK 0x00007F00U +#define DDR_PHY_DX5GCR5_DXREFISELR1_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR5_DXREFISELR1_SHIFT 8 +#define DDR_PHY_DX5GCR5_DXREFISELR1_MASK 0x00007F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX5GCR5_RESERVED_7_DEFVAL #undef DDR_PHY_DX5GCR5_RESERVED_7_SHIFT #undef DDR_PHY_DX5GCR5_RESERVED_7_MASK -#define DDR_PHY_DX5GCR5_RESERVED_7_DEFVAL 0x09090909 -#define DDR_PHY_DX5GCR5_RESERVED_7_SHIFT 7 -#define DDR_PHY_DX5GCR5_RESERVED_7_MASK 0x00000080U +#define DDR_PHY_DX5GCR5_RESERVED_7_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR5_RESERVED_7_SHIFT 7 +#define DDR_PHY_DX5GCR5_RESERVED_7_MASK 0x00000080U -/*Byte Lane internal VREF Select for Rank 0*/ +/* +* Byte Lane internal VREF Select for Rank 0 +*/ #undef DDR_PHY_DX5GCR5_DXREFISELR0_DEFVAL #undef DDR_PHY_DX5GCR5_DXREFISELR0_SHIFT #undef DDR_PHY_DX5GCR5_DXREFISELR0_MASK -#define DDR_PHY_DX5GCR5_DXREFISELR0_DEFVAL 0x09090909 -#define DDR_PHY_DX5GCR5_DXREFISELR0_SHIFT 0 -#define DDR_PHY_DX5GCR5_DXREFISELR0_MASK 0x0000007FU +#define DDR_PHY_DX5GCR5_DXREFISELR0_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR5_DXREFISELR0_SHIFT 0 +#define DDR_PHY_DX5GCR5_DXREFISELR0_MASK 0x0000007FU -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX5GCR6_RESERVED_31_30_DEFVAL #undef DDR_PHY_DX5GCR6_RESERVED_31_30_SHIFT #undef DDR_PHY_DX5GCR6_RESERVED_31_30_MASK -#define DDR_PHY_DX5GCR6_RESERVED_31_30_DEFVAL 0x09090909 -#define DDR_PHY_DX5GCR6_RESERVED_31_30_SHIFT 30 -#define DDR_PHY_DX5GCR6_RESERVED_31_30_MASK 0xC0000000U +#define DDR_PHY_DX5GCR6_RESERVED_31_30_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR6_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX5GCR6_RESERVED_31_30_MASK 0xC0000000U -/*DRAM DQ VREF Select for Rank3*/ +/* +* DRAM DQ VREF Select for Rank3 +*/ #undef DDR_PHY_DX5GCR6_DXDQVREFR3_DEFVAL #undef DDR_PHY_DX5GCR6_DXDQVREFR3_SHIFT #undef DDR_PHY_DX5GCR6_DXDQVREFR3_MASK -#define DDR_PHY_DX5GCR6_DXDQVREFR3_DEFVAL 0x09090909 -#define DDR_PHY_DX5GCR6_DXDQVREFR3_SHIFT 24 -#define DDR_PHY_DX5GCR6_DXDQVREFR3_MASK 0x3F000000U +#define DDR_PHY_DX5GCR6_DXDQVREFR3_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR6_DXDQVREFR3_SHIFT 24 +#define DDR_PHY_DX5GCR6_DXDQVREFR3_MASK 0x3F000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX5GCR6_RESERVED_23_22_DEFVAL #undef DDR_PHY_DX5GCR6_RESERVED_23_22_SHIFT #undef DDR_PHY_DX5GCR6_RESERVED_23_22_MASK -#define DDR_PHY_DX5GCR6_RESERVED_23_22_DEFVAL 0x09090909 -#define DDR_PHY_DX5GCR6_RESERVED_23_22_SHIFT 22 -#define DDR_PHY_DX5GCR6_RESERVED_23_22_MASK 0x00C00000U +#define DDR_PHY_DX5GCR6_RESERVED_23_22_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR6_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX5GCR6_RESERVED_23_22_MASK 0x00C00000U -/*DRAM DQ VREF Select for Rank2*/ +/* +* DRAM DQ VREF Select for Rank2 +*/ #undef DDR_PHY_DX5GCR6_DXDQVREFR2_DEFVAL #undef DDR_PHY_DX5GCR6_DXDQVREFR2_SHIFT #undef DDR_PHY_DX5GCR6_DXDQVREFR2_MASK -#define DDR_PHY_DX5GCR6_DXDQVREFR2_DEFVAL 0x09090909 -#define DDR_PHY_DX5GCR6_DXDQVREFR2_SHIFT 16 -#define DDR_PHY_DX5GCR6_DXDQVREFR2_MASK 0x003F0000U +#define DDR_PHY_DX5GCR6_DXDQVREFR2_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR6_DXDQVREFR2_SHIFT 16 +#define DDR_PHY_DX5GCR6_DXDQVREFR2_MASK 0x003F0000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX5GCR6_RESERVED_15_14_DEFVAL #undef DDR_PHY_DX5GCR6_RESERVED_15_14_SHIFT #undef DDR_PHY_DX5GCR6_RESERVED_15_14_MASK -#define DDR_PHY_DX5GCR6_RESERVED_15_14_DEFVAL 0x09090909 -#define DDR_PHY_DX5GCR6_RESERVED_15_14_SHIFT 14 -#define DDR_PHY_DX5GCR6_RESERVED_15_14_MASK 0x0000C000U +#define DDR_PHY_DX5GCR6_RESERVED_15_14_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR6_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_DX5GCR6_RESERVED_15_14_MASK 0x0000C000U -/*DRAM DQ VREF Select for Rank1*/ +/* +* DRAM DQ VREF Select for Rank1 +*/ #undef DDR_PHY_DX5GCR6_DXDQVREFR1_DEFVAL #undef DDR_PHY_DX5GCR6_DXDQVREFR1_SHIFT #undef DDR_PHY_DX5GCR6_DXDQVREFR1_MASK -#define DDR_PHY_DX5GCR6_DXDQVREFR1_DEFVAL 0x09090909 -#define DDR_PHY_DX5GCR6_DXDQVREFR1_SHIFT 8 -#define DDR_PHY_DX5GCR6_DXDQVREFR1_MASK 0x00003F00U +#define DDR_PHY_DX5GCR6_DXDQVREFR1_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR6_DXDQVREFR1_SHIFT 8 +#define DDR_PHY_DX5GCR6_DXDQVREFR1_MASK 0x00003F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX5GCR6_RESERVED_7_6_DEFVAL #undef DDR_PHY_DX5GCR6_RESERVED_7_6_SHIFT #undef DDR_PHY_DX5GCR6_RESERVED_7_6_MASK -#define DDR_PHY_DX5GCR6_RESERVED_7_6_DEFVAL 0x09090909 -#define DDR_PHY_DX5GCR6_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_DX5GCR6_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_DX5GCR6_RESERVED_7_6_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR6_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX5GCR6_RESERVED_7_6_MASK 0x000000C0U -/*DRAM DQ VREF Select for Rank0*/ +/* +* DRAM DQ VREF Select for Rank0 +*/ #undef DDR_PHY_DX5GCR6_DXDQVREFR0_DEFVAL #undef DDR_PHY_DX5GCR6_DXDQVREFR0_SHIFT #undef DDR_PHY_DX5GCR6_DXDQVREFR0_MASK -#define DDR_PHY_DX5GCR6_DXDQVREFR0_DEFVAL 0x09090909 -#define DDR_PHY_DX5GCR6_DXDQVREFR0_SHIFT 0 -#define DDR_PHY_DX5GCR6_DXDQVREFR0_MASK 0x0000003FU +#define DDR_PHY_DX5GCR6_DXDQVREFR0_DEFVAL 0x09090909 +#define DDR_PHY_DX5GCR6_DXDQVREFR0_SHIFT 0 +#define DDR_PHY_DX5GCR6_DXDQVREFR0_MASK 0x0000003FU -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX5LCDLR2_RESERVED_31_25_DEFVAL -#undef DDR_PHY_DX5LCDLR2_RESERVED_31_25_SHIFT -#undef DDR_PHY_DX5LCDLR2_RESERVED_31_25_MASK -#define DDR_PHY_DX5LCDLR2_RESERVED_31_25_DEFVAL 0x00000000 -#define DDR_PHY_DX5LCDLR2_RESERVED_31_25_SHIFT 25 -#define DDR_PHY_DX5LCDLR2_RESERVED_31_25_MASK 0xFE000000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX5LCDLR2_RESERVED_24_16_DEFVAL -#undef DDR_PHY_DX5LCDLR2_RESERVED_24_16_SHIFT -#undef DDR_PHY_DX5LCDLR2_RESERVED_24_16_MASK -#define DDR_PHY_DX5LCDLR2_RESERVED_24_16_DEFVAL 0x00000000 -#define DDR_PHY_DX5LCDLR2_RESERVED_24_16_SHIFT 16 -#define DDR_PHY_DX5LCDLR2_RESERVED_24_16_MASK 0x01FF0000U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX5LCDLR2_RESERVED_15_9_DEFVAL -#undef DDR_PHY_DX5LCDLR2_RESERVED_15_9_SHIFT -#undef DDR_PHY_DX5LCDLR2_RESERVED_15_9_MASK -#define DDR_PHY_DX5LCDLR2_RESERVED_15_9_DEFVAL 0x00000000 -#define DDR_PHY_DX5LCDLR2_RESERVED_15_9_SHIFT 9 -#define DDR_PHY_DX5LCDLR2_RESERVED_15_9_MASK 0x0000FE00U - -/*Read DQS Gating Delay*/ -#undef DDR_PHY_DX5LCDLR2_DQSGD_DEFVAL -#undef DDR_PHY_DX5LCDLR2_DQSGD_SHIFT -#undef DDR_PHY_DX5LCDLR2_DQSGD_MASK -#define DDR_PHY_DX5LCDLR2_DQSGD_DEFVAL 0x00000000 -#define DDR_PHY_DX5LCDLR2_DQSGD_SHIFT 0 -#define DDR_PHY_DX5LCDLR2_DQSGD_MASK 0x000001FFU - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX5GTR0_RESERVED_31_24_DEFVAL -#undef DDR_PHY_DX5GTR0_RESERVED_31_24_SHIFT -#undef DDR_PHY_DX5GTR0_RESERVED_31_24_MASK -#define DDR_PHY_DX5GTR0_RESERVED_31_24_DEFVAL 0x00020000 -#define DDR_PHY_DX5GTR0_RESERVED_31_24_SHIFT 27 -#define DDR_PHY_DX5GTR0_RESERVED_31_24_MASK 0xF8000000U - -/*DQ Write Path Latency Pipeline*/ -#undef DDR_PHY_DX5GTR0_WDQSL_DEFVAL -#undef DDR_PHY_DX5GTR0_WDQSL_SHIFT -#undef DDR_PHY_DX5GTR0_WDQSL_MASK -#define DDR_PHY_DX5GTR0_WDQSL_DEFVAL 0x00020000 -#define DDR_PHY_DX5GTR0_WDQSL_SHIFT 24 -#define DDR_PHY_DX5GTR0_WDQSL_MASK 0x07000000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX5GTR0_RESERVED_23_20_DEFVAL -#undef DDR_PHY_DX5GTR0_RESERVED_23_20_SHIFT -#undef DDR_PHY_DX5GTR0_RESERVED_23_20_MASK -#define DDR_PHY_DX5GTR0_RESERVED_23_20_DEFVAL 0x00020000 -#define DDR_PHY_DX5GTR0_RESERVED_23_20_SHIFT 20 -#define DDR_PHY_DX5GTR0_RESERVED_23_20_MASK 0x00F00000U - -/*Write Leveling System Latency*/ -#undef DDR_PHY_DX5GTR0_WLSL_DEFVAL -#undef DDR_PHY_DX5GTR0_WLSL_SHIFT -#undef DDR_PHY_DX5GTR0_WLSL_MASK -#define DDR_PHY_DX5GTR0_WLSL_DEFVAL 0x00020000 -#define DDR_PHY_DX5GTR0_WLSL_SHIFT 16 -#define DDR_PHY_DX5GTR0_WLSL_MASK 0x000F0000U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX5GTR0_RESERVED_15_13_DEFVAL -#undef DDR_PHY_DX5GTR0_RESERVED_15_13_SHIFT -#undef DDR_PHY_DX5GTR0_RESERVED_15_13_MASK -#define DDR_PHY_DX5GTR0_RESERVED_15_13_DEFVAL 0x00020000 -#define DDR_PHY_DX5GTR0_RESERVED_15_13_SHIFT 13 -#define DDR_PHY_DX5GTR0_RESERVED_15_13_MASK 0x0000E000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX5GTR0_RESERVED_12_8_DEFVAL -#undef DDR_PHY_DX5GTR0_RESERVED_12_8_SHIFT -#undef DDR_PHY_DX5GTR0_RESERVED_12_8_MASK -#define DDR_PHY_DX5GTR0_RESERVED_12_8_DEFVAL 0x00020000 -#define DDR_PHY_DX5GTR0_RESERVED_12_8_SHIFT 8 -#define DDR_PHY_DX5GTR0_RESERVED_12_8_MASK 0x00001F00U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX5GTR0_RESERVED_7_5_DEFVAL -#undef DDR_PHY_DX5GTR0_RESERVED_7_5_SHIFT -#undef DDR_PHY_DX5GTR0_RESERVED_7_5_MASK -#define DDR_PHY_DX5GTR0_RESERVED_7_5_DEFVAL 0x00020000 -#define DDR_PHY_DX5GTR0_RESERVED_7_5_SHIFT 5 -#define DDR_PHY_DX5GTR0_RESERVED_7_5_MASK 0x000000E0U - -/*DQS Gating System Latency*/ -#undef DDR_PHY_DX5GTR0_DGSL_DEFVAL -#undef DDR_PHY_DX5GTR0_DGSL_SHIFT -#undef DDR_PHY_DX5GTR0_DGSL_MASK -#define DDR_PHY_DX5GTR0_DGSL_DEFVAL 0x00020000 -#define DDR_PHY_DX5GTR0_DGSL_SHIFT 0 -#define DDR_PHY_DX5GTR0_DGSL_MASK 0x0000001FU - -/*Calibration Bypass*/ +/* +* Calibration Bypass +*/ #undef DDR_PHY_DX6GCR0_CALBYP_DEFVAL #undef DDR_PHY_DX6GCR0_CALBYP_SHIFT #undef DDR_PHY_DX6GCR0_CALBYP_MASK -#define DDR_PHY_DX6GCR0_CALBYP_DEFVAL 0x40200204 -#define DDR_PHY_DX6GCR0_CALBYP_SHIFT 31 -#define DDR_PHY_DX6GCR0_CALBYP_MASK 0x80000000U +#define DDR_PHY_DX6GCR0_CALBYP_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_CALBYP_SHIFT 31 +#define DDR_PHY_DX6GCR0_CALBYP_MASK 0x80000000U -/*Master Delay Line Enable*/ +/* +* Master Delay Line Enable +*/ #undef DDR_PHY_DX6GCR0_MDLEN_DEFVAL #undef DDR_PHY_DX6GCR0_MDLEN_SHIFT #undef DDR_PHY_DX6GCR0_MDLEN_MASK -#define DDR_PHY_DX6GCR0_MDLEN_DEFVAL 0x40200204 -#define DDR_PHY_DX6GCR0_MDLEN_SHIFT 30 -#define DDR_PHY_DX6GCR0_MDLEN_MASK 0x40000000U +#define DDR_PHY_DX6GCR0_MDLEN_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_MDLEN_SHIFT 30 +#define DDR_PHY_DX6GCR0_MDLEN_MASK 0x40000000U -/*Configurable ODT(TE) Phase Shift*/ +/* +* Configurable ODT(TE) Phase Shift +*/ #undef DDR_PHY_DX6GCR0_CODTSHFT_DEFVAL #undef DDR_PHY_DX6GCR0_CODTSHFT_SHIFT #undef DDR_PHY_DX6GCR0_CODTSHFT_MASK -#define DDR_PHY_DX6GCR0_CODTSHFT_DEFVAL 0x40200204 -#define DDR_PHY_DX6GCR0_CODTSHFT_SHIFT 28 -#define DDR_PHY_DX6GCR0_CODTSHFT_MASK 0x30000000U +#define DDR_PHY_DX6GCR0_CODTSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_CODTSHFT_SHIFT 28 +#define DDR_PHY_DX6GCR0_CODTSHFT_MASK 0x30000000U -/*DQS Duty Cycle Correction*/ +/* +* DQS Duty Cycle Correction +*/ #undef DDR_PHY_DX6GCR0_DQSDCC_DEFVAL #undef DDR_PHY_DX6GCR0_DQSDCC_SHIFT #undef DDR_PHY_DX6GCR0_DQSDCC_MASK -#define DDR_PHY_DX6GCR0_DQSDCC_DEFVAL 0x40200204 -#define DDR_PHY_DX6GCR0_DQSDCC_SHIFT 24 -#define DDR_PHY_DX6GCR0_DQSDCC_MASK 0x0F000000U +#define DDR_PHY_DX6GCR0_DQSDCC_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_DQSDCC_SHIFT 24 +#define DDR_PHY_DX6GCR0_DQSDCC_MASK 0x0F000000U -/*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/ +/* +* Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY +*/ #undef DDR_PHY_DX6GCR0_RDDLY_DEFVAL #undef DDR_PHY_DX6GCR0_RDDLY_SHIFT #undef DDR_PHY_DX6GCR0_RDDLY_MASK -#define DDR_PHY_DX6GCR0_RDDLY_DEFVAL 0x40200204 -#define DDR_PHY_DX6GCR0_RDDLY_SHIFT 20 -#define DDR_PHY_DX6GCR0_RDDLY_MASK 0x00F00000U +#define DDR_PHY_DX6GCR0_RDDLY_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_RDDLY_SHIFT 20 +#define DDR_PHY_DX6GCR0_RDDLY_MASK 0x00F00000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX6GCR0_RESERVED_19_14_DEFVAL #undef DDR_PHY_DX6GCR0_RESERVED_19_14_SHIFT #undef DDR_PHY_DX6GCR0_RESERVED_19_14_MASK -#define DDR_PHY_DX6GCR0_RESERVED_19_14_DEFVAL 0x40200204 -#define DDR_PHY_DX6GCR0_RESERVED_19_14_SHIFT 14 -#define DDR_PHY_DX6GCR0_RESERVED_19_14_MASK 0x000FC000U +#define DDR_PHY_DX6GCR0_RESERVED_19_14_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_RESERVED_19_14_SHIFT 14 +#define DDR_PHY_DX6GCR0_RESERVED_19_14_MASK 0x000FC000U -/*DQSNSE Power Down Receiver*/ +/* +* DQSNSE Power Down Receiver +*/ #undef DDR_PHY_DX6GCR0_DQSNSEPDR_DEFVAL #undef DDR_PHY_DX6GCR0_DQSNSEPDR_SHIFT #undef DDR_PHY_DX6GCR0_DQSNSEPDR_MASK -#define DDR_PHY_DX6GCR0_DQSNSEPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX6GCR0_DQSNSEPDR_SHIFT 13 -#define DDR_PHY_DX6GCR0_DQSNSEPDR_MASK 0x00002000U +#define DDR_PHY_DX6GCR0_DQSNSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_DQSNSEPDR_SHIFT 13 +#define DDR_PHY_DX6GCR0_DQSNSEPDR_MASK 0x00002000U -/*DQSSE Power Down Receiver*/ +/* +* DQSSE Power Down Receiver +*/ #undef DDR_PHY_DX6GCR0_DQSSEPDR_DEFVAL #undef DDR_PHY_DX6GCR0_DQSSEPDR_SHIFT #undef DDR_PHY_DX6GCR0_DQSSEPDR_MASK -#define DDR_PHY_DX6GCR0_DQSSEPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX6GCR0_DQSSEPDR_SHIFT 12 -#define DDR_PHY_DX6GCR0_DQSSEPDR_MASK 0x00001000U +#define DDR_PHY_DX6GCR0_DQSSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_DQSSEPDR_SHIFT 12 +#define DDR_PHY_DX6GCR0_DQSSEPDR_MASK 0x00001000U -/*RTT On Additive Latency*/ +/* +* RTT On Additive Latency +*/ #undef DDR_PHY_DX6GCR0_RTTOAL_DEFVAL #undef DDR_PHY_DX6GCR0_RTTOAL_SHIFT #undef DDR_PHY_DX6GCR0_RTTOAL_MASK -#define DDR_PHY_DX6GCR0_RTTOAL_DEFVAL 0x40200204 -#define DDR_PHY_DX6GCR0_RTTOAL_SHIFT 11 -#define DDR_PHY_DX6GCR0_RTTOAL_MASK 0x00000800U +#define DDR_PHY_DX6GCR0_RTTOAL_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_RTTOAL_SHIFT 11 +#define DDR_PHY_DX6GCR0_RTTOAL_MASK 0x00000800U -/*RTT Output Hold*/ +/* +* RTT Output Hold +*/ #undef DDR_PHY_DX6GCR0_RTTOH_DEFVAL #undef DDR_PHY_DX6GCR0_RTTOH_SHIFT #undef DDR_PHY_DX6GCR0_RTTOH_MASK -#define DDR_PHY_DX6GCR0_RTTOH_DEFVAL 0x40200204 -#define DDR_PHY_DX6GCR0_RTTOH_SHIFT 9 -#define DDR_PHY_DX6GCR0_RTTOH_MASK 0x00000600U +#define DDR_PHY_DX6GCR0_RTTOH_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_RTTOH_SHIFT 9 +#define DDR_PHY_DX6GCR0_RTTOH_MASK 0x00000600U -/*Configurable PDR Phase Shift*/ +/* +* Configurable PDR Phase Shift +*/ #undef DDR_PHY_DX6GCR0_CPDRSHFT_DEFVAL #undef DDR_PHY_DX6GCR0_CPDRSHFT_SHIFT #undef DDR_PHY_DX6GCR0_CPDRSHFT_MASK -#define DDR_PHY_DX6GCR0_CPDRSHFT_DEFVAL 0x40200204 -#define DDR_PHY_DX6GCR0_CPDRSHFT_SHIFT 7 -#define DDR_PHY_DX6GCR0_CPDRSHFT_MASK 0x00000180U +#define DDR_PHY_DX6GCR0_CPDRSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_CPDRSHFT_SHIFT 7 +#define DDR_PHY_DX6GCR0_CPDRSHFT_MASK 0x00000180U -/*DQSR Power Down*/ +/* +* DQSR Power Down +*/ #undef DDR_PHY_DX6GCR0_DQSRPD_DEFVAL #undef DDR_PHY_DX6GCR0_DQSRPD_SHIFT #undef DDR_PHY_DX6GCR0_DQSRPD_MASK -#define DDR_PHY_DX6GCR0_DQSRPD_DEFVAL 0x40200204 -#define DDR_PHY_DX6GCR0_DQSRPD_SHIFT 6 -#define DDR_PHY_DX6GCR0_DQSRPD_MASK 0x00000040U +#define DDR_PHY_DX6GCR0_DQSRPD_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_DQSRPD_SHIFT 6 +#define DDR_PHY_DX6GCR0_DQSRPD_MASK 0x00000040U -/*DQSG Power Down Receiver*/ +/* +* DQSG Power Down Receiver +*/ #undef DDR_PHY_DX6GCR0_DQSGPDR_DEFVAL #undef DDR_PHY_DX6GCR0_DQSGPDR_SHIFT #undef DDR_PHY_DX6GCR0_DQSGPDR_MASK -#define DDR_PHY_DX6GCR0_DQSGPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX6GCR0_DQSGPDR_SHIFT 5 -#define DDR_PHY_DX6GCR0_DQSGPDR_MASK 0x00000020U +#define DDR_PHY_DX6GCR0_DQSGPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_DQSGPDR_SHIFT 5 +#define DDR_PHY_DX6GCR0_DQSGPDR_MASK 0x00000020U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX6GCR0_RESERVED_4_DEFVAL #undef DDR_PHY_DX6GCR0_RESERVED_4_SHIFT #undef DDR_PHY_DX6GCR0_RESERVED_4_MASK -#define DDR_PHY_DX6GCR0_RESERVED_4_DEFVAL 0x40200204 -#define DDR_PHY_DX6GCR0_RESERVED_4_SHIFT 4 -#define DDR_PHY_DX6GCR0_RESERVED_4_MASK 0x00000010U +#define DDR_PHY_DX6GCR0_RESERVED_4_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_RESERVED_4_SHIFT 4 +#define DDR_PHY_DX6GCR0_RESERVED_4_MASK 0x00000010U -/*DQSG On-Die Termination*/ +/* +* DQSG On-Die Termination +*/ #undef DDR_PHY_DX6GCR0_DQSGODT_DEFVAL #undef DDR_PHY_DX6GCR0_DQSGODT_SHIFT #undef DDR_PHY_DX6GCR0_DQSGODT_MASK -#define DDR_PHY_DX6GCR0_DQSGODT_DEFVAL 0x40200204 -#define DDR_PHY_DX6GCR0_DQSGODT_SHIFT 3 -#define DDR_PHY_DX6GCR0_DQSGODT_MASK 0x00000008U +#define DDR_PHY_DX6GCR0_DQSGODT_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_DQSGODT_SHIFT 3 +#define DDR_PHY_DX6GCR0_DQSGODT_MASK 0x00000008U -/*DQSG Output Enable*/ +/* +* DQSG Output Enable +*/ #undef DDR_PHY_DX6GCR0_DQSGOE_DEFVAL #undef DDR_PHY_DX6GCR0_DQSGOE_SHIFT #undef DDR_PHY_DX6GCR0_DQSGOE_MASK -#define DDR_PHY_DX6GCR0_DQSGOE_DEFVAL 0x40200204 -#define DDR_PHY_DX6GCR0_DQSGOE_SHIFT 2 -#define DDR_PHY_DX6GCR0_DQSGOE_MASK 0x00000004U +#define DDR_PHY_DX6GCR0_DQSGOE_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_DQSGOE_SHIFT 2 +#define DDR_PHY_DX6GCR0_DQSGOE_MASK 0x00000004U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX6GCR0_RESERVED_1_0_DEFVAL #undef DDR_PHY_DX6GCR0_RESERVED_1_0_SHIFT #undef DDR_PHY_DX6GCR0_RESERVED_1_0_MASK -#define DDR_PHY_DX6GCR0_RESERVED_1_0_DEFVAL 0x40200204 -#define DDR_PHY_DX6GCR0_RESERVED_1_0_SHIFT 0 -#define DDR_PHY_DX6GCR0_RESERVED_1_0_MASK 0x00000003U +#define DDR_PHY_DX6GCR0_RESERVED_1_0_DEFVAL 0x40200204 +#define DDR_PHY_DX6GCR0_RESERVED_1_0_SHIFT 0 +#define DDR_PHY_DX6GCR0_RESERVED_1_0_MASK 0x00000003U -/*Enables the PDR mode for DQ[7:0]*/ +/* +* Enables the PDR mode for DQ[7:0] +*/ #undef DDR_PHY_DX6GCR1_DXPDRMODE_DEFVAL #undef DDR_PHY_DX6GCR1_DXPDRMODE_SHIFT #undef DDR_PHY_DX6GCR1_DXPDRMODE_MASK -#define DDR_PHY_DX6GCR1_DXPDRMODE_DEFVAL 0x00007FFF -#define DDR_PHY_DX6GCR1_DXPDRMODE_SHIFT 16 -#define DDR_PHY_DX6GCR1_DXPDRMODE_MASK 0xFFFF0000U +#define DDR_PHY_DX6GCR1_DXPDRMODE_DEFVAL 0x00007FFF +#define DDR_PHY_DX6GCR1_DXPDRMODE_SHIFT 16 +#define DDR_PHY_DX6GCR1_DXPDRMODE_MASK 0xFFFF0000U -/*Reserved. Returns zeroes on reads.*/ +/* +* Reserved. Returns zeroes on reads. +*/ #undef DDR_PHY_DX6GCR1_RESERVED_15_DEFVAL #undef DDR_PHY_DX6GCR1_RESERVED_15_SHIFT #undef DDR_PHY_DX6GCR1_RESERVED_15_MASK -#define DDR_PHY_DX6GCR1_RESERVED_15_DEFVAL 0x00007FFF -#define DDR_PHY_DX6GCR1_RESERVED_15_SHIFT 15 -#define DDR_PHY_DX6GCR1_RESERVED_15_MASK 0x00008000U +#define DDR_PHY_DX6GCR1_RESERVED_15_DEFVAL 0x00007FFF +#define DDR_PHY_DX6GCR1_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX6GCR1_RESERVED_15_MASK 0x00008000U -/*Select the delayed or non-delayed read data strobe #*/ +/* +* Select the delayed or non-delayed read data strobe # +*/ #undef DDR_PHY_DX6GCR1_QSNSEL_DEFVAL #undef DDR_PHY_DX6GCR1_QSNSEL_SHIFT #undef DDR_PHY_DX6GCR1_QSNSEL_MASK -#define DDR_PHY_DX6GCR1_QSNSEL_DEFVAL 0x00007FFF -#define DDR_PHY_DX6GCR1_QSNSEL_SHIFT 14 -#define DDR_PHY_DX6GCR1_QSNSEL_MASK 0x00004000U +#define DDR_PHY_DX6GCR1_QSNSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX6GCR1_QSNSEL_SHIFT 14 +#define DDR_PHY_DX6GCR1_QSNSEL_MASK 0x00004000U -/*Select the delayed or non-delayed read data strobe*/ +/* +* Select the delayed or non-delayed read data strobe +*/ #undef DDR_PHY_DX6GCR1_QSSEL_DEFVAL #undef DDR_PHY_DX6GCR1_QSSEL_SHIFT #undef DDR_PHY_DX6GCR1_QSSEL_MASK -#define DDR_PHY_DX6GCR1_QSSEL_DEFVAL 0x00007FFF -#define DDR_PHY_DX6GCR1_QSSEL_SHIFT 13 -#define DDR_PHY_DX6GCR1_QSSEL_MASK 0x00002000U +#define DDR_PHY_DX6GCR1_QSSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX6GCR1_QSSEL_SHIFT 13 +#define DDR_PHY_DX6GCR1_QSSEL_MASK 0x00002000U -/*Enables Read Data Strobe in a byte lane*/ +/* +* Enables Read Data Strobe in a byte lane +*/ #undef DDR_PHY_DX6GCR1_OEEN_DEFVAL #undef DDR_PHY_DX6GCR1_OEEN_SHIFT #undef DDR_PHY_DX6GCR1_OEEN_MASK -#define DDR_PHY_DX6GCR1_OEEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX6GCR1_OEEN_SHIFT 12 -#define DDR_PHY_DX6GCR1_OEEN_MASK 0x00001000U +#define DDR_PHY_DX6GCR1_OEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX6GCR1_OEEN_SHIFT 12 +#define DDR_PHY_DX6GCR1_OEEN_MASK 0x00001000U -/*Enables PDR in a byte lane*/ +/* +* Enables PDR in a byte lane +*/ #undef DDR_PHY_DX6GCR1_PDREN_DEFVAL #undef DDR_PHY_DX6GCR1_PDREN_SHIFT #undef DDR_PHY_DX6GCR1_PDREN_MASK -#define DDR_PHY_DX6GCR1_PDREN_DEFVAL 0x00007FFF -#define DDR_PHY_DX6GCR1_PDREN_SHIFT 11 -#define DDR_PHY_DX6GCR1_PDREN_MASK 0x00000800U +#define DDR_PHY_DX6GCR1_PDREN_DEFVAL 0x00007FFF +#define DDR_PHY_DX6GCR1_PDREN_SHIFT 11 +#define DDR_PHY_DX6GCR1_PDREN_MASK 0x00000800U -/*Enables ODT/TE in a byte lane*/ +/* +* Enables ODT/TE in a byte lane +*/ #undef DDR_PHY_DX6GCR1_TEEN_DEFVAL #undef DDR_PHY_DX6GCR1_TEEN_SHIFT #undef DDR_PHY_DX6GCR1_TEEN_MASK -#define DDR_PHY_DX6GCR1_TEEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX6GCR1_TEEN_SHIFT 10 -#define DDR_PHY_DX6GCR1_TEEN_MASK 0x00000400U +#define DDR_PHY_DX6GCR1_TEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX6GCR1_TEEN_SHIFT 10 +#define DDR_PHY_DX6GCR1_TEEN_MASK 0x00000400U -/*Enables Write Data strobe in a byte lane*/ +/* +* Enables Write Data strobe in a byte lane +*/ #undef DDR_PHY_DX6GCR1_DSEN_DEFVAL #undef DDR_PHY_DX6GCR1_DSEN_SHIFT #undef DDR_PHY_DX6GCR1_DSEN_MASK -#define DDR_PHY_DX6GCR1_DSEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX6GCR1_DSEN_SHIFT 9 -#define DDR_PHY_DX6GCR1_DSEN_MASK 0x00000200U +#define DDR_PHY_DX6GCR1_DSEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX6GCR1_DSEN_SHIFT 9 +#define DDR_PHY_DX6GCR1_DSEN_MASK 0x00000200U -/*Enables DM pin in a byte lane*/ +/* +* Enables DM pin in a byte lane +*/ #undef DDR_PHY_DX6GCR1_DMEN_DEFVAL #undef DDR_PHY_DX6GCR1_DMEN_SHIFT #undef DDR_PHY_DX6GCR1_DMEN_MASK -#define DDR_PHY_DX6GCR1_DMEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX6GCR1_DMEN_SHIFT 8 -#define DDR_PHY_DX6GCR1_DMEN_MASK 0x00000100U +#define DDR_PHY_DX6GCR1_DMEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX6GCR1_DMEN_SHIFT 8 +#define DDR_PHY_DX6GCR1_DMEN_MASK 0x00000100U -/*Enables DQ corresponding to each bit in a byte*/ +/* +* Enables DQ corresponding to each bit in a byte +*/ #undef DDR_PHY_DX6GCR1_DQEN_DEFVAL #undef DDR_PHY_DX6GCR1_DQEN_SHIFT #undef DDR_PHY_DX6GCR1_DQEN_MASK -#define DDR_PHY_DX6GCR1_DQEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX6GCR1_DQEN_SHIFT 0 -#define DDR_PHY_DX6GCR1_DQEN_MASK 0x000000FFU +#define DDR_PHY_DX6GCR1_DQEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX6GCR1_DQEN_SHIFT 0 +#define DDR_PHY_DX6GCR1_DQEN_MASK 0x000000FFU -/*Byte lane VREF IOM (Used only by D4MU IOs)*/ +/* +* Byte lane VREF IOM (Used only by D4MU IOs) +*/ #undef DDR_PHY_DX6GCR4_RESERVED_31_29_DEFVAL #undef DDR_PHY_DX6GCR4_RESERVED_31_29_SHIFT #undef DDR_PHY_DX6GCR4_RESERVED_31_29_MASK -#define DDR_PHY_DX6GCR4_RESERVED_31_29_DEFVAL 0x0E00003C -#define DDR_PHY_DX6GCR4_RESERVED_31_29_SHIFT 29 -#define DDR_PHY_DX6GCR4_RESERVED_31_29_MASK 0xE0000000U +#define DDR_PHY_DX6GCR4_RESERVED_31_29_DEFVAL 0x0E00003C +#define DDR_PHY_DX6GCR4_RESERVED_31_29_SHIFT 29 +#define DDR_PHY_DX6GCR4_RESERVED_31_29_MASK 0xE0000000U -/*Byte Lane VREF Pad Enable*/ +/* +* Byte Lane VREF Pad Enable +*/ #undef DDR_PHY_DX6GCR4_DXREFPEN_DEFVAL #undef DDR_PHY_DX6GCR4_DXREFPEN_SHIFT #undef DDR_PHY_DX6GCR4_DXREFPEN_MASK -#define DDR_PHY_DX6GCR4_DXREFPEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX6GCR4_DXREFPEN_SHIFT 28 -#define DDR_PHY_DX6GCR4_DXREFPEN_MASK 0x10000000U +#define DDR_PHY_DX6GCR4_DXREFPEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX6GCR4_DXREFPEN_SHIFT 28 +#define DDR_PHY_DX6GCR4_DXREFPEN_MASK 0x10000000U -/*Byte Lane Internal VREF Enable*/ +/* +* Byte Lane Internal VREF Enable +*/ #undef DDR_PHY_DX6GCR4_DXREFEEN_DEFVAL #undef DDR_PHY_DX6GCR4_DXREFEEN_SHIFT #undef DDR_PHY_DX6GCR4_DXREFEEN_MASK -#define DDR_PHY_DX6GCR4_DXREFEEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX6GCR4_DXREFEEN_SHIFT 26 -#define DDR_PHY_DX6GCR4_DXREFEEN_MASK 0x0C000000U +#define DDR_PHY_DX6GCR4_DXREFEEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX6GCR4_DXREFEEN_SHIFT 26 +#define DDR_PHY_DX6GCR4_DXREFEEN_MASK 0x0C000000U -/*Byte Lane Single-End VREF Enable*/ +/* +* Byte Lane Single-End VREF Enable +*/ #undef DDR_PHY_DX6GCR4_DXREFSEN_DEFVAL #undef DDR_PHY_DX6GCR4_DXREFSEN_SHIFT #undef DDR_PHY_DX6GCR4_DXREFSEN_MASK -#define DDR_PHY_DX6GCR4_DXREFSEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX6GCR4_DXREFSEN_SHIFT 25 -#define DDR_PHY_DX6GCR4_DXREFSEN_MASK 0x02000000U +#define DDR_PHY_DX6GCR4_DXREFSEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX6GCR4_DXREFSEN_SHIFT 25 +#define DDR_PHY_DX6GCR4_DXREFSEN_MASK 0x02000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX6GCR4_RESERVED_24_DEFVAL #undef DDR_PHY_DX6GCR4_RESERVED_24_SHIFT #undef DDR_PHY_DX6GCR4_RESERVED_24_MASK -#define DDR_PHY_DX6GCR4_RESERVED_24_DEFVAL 0x0E00003C -#define DDR_PHY_DX6GCR4_RESERVED_24_SHIFT 24 -#define DDR_PHY_DX6GCR4_RESERVED_24_MASK 0x01000000U +#define DDR_PHY_DX6GCR4_RESERVED_24_DEFVAL 0x0E00003C +#define DDR_PHY_DX6GCR4_RESERVED_24_SHIFT 24 +#define DDR_PHY_DX6GCR4_RESERVED_24_MASK 0x01000000U -/*External VREF generator REFSEL range select*/ +/* +* External VREF generator REFSEL range select +*/ #undef DDR_PHY_DX6GCR4_DXREFESELRANGE_DEFVAL #undef DDR_PHY_DX6GCR4_DXREFESELRANGE_SHIFT #undef DDR_PHY_DX6GCR4_DXREFESELRANGE_MASK -#define DDR_PHY_DX6GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C -#define DDR_PHY_DX6GCR4_DXREFESELRANGE_SHIFT 23 -#define DDR_PHY_DX6GCR4_DXREFESELRANGE_MASK 0x00800000U +#define DDR_PHY_DX6GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX6GCR4_DXREFESELRANGE_SHIFT 23 +#define DDR_PHY_DX6GCR4_DXREFESELRANGE_MASK 0x00800000U -/*Byte Lane External VREF Select*/ +/* +* Byte Lane External VREF Select +*/ #undef DDR_PHY_DX6GCR4_DXREFESEL_DEFVAL #undef DDR_PHY_DX6GCR4_DXREFESEL_SHIFT #undef DDR_PHY_DX6GCR4_DXREFESEL_MASK -#define DDR_PHY_DX6GCR4_DXREFESEL_DEFVAL 0x0E00003C -#define DDR_PHY_DX6GCR4_DXREFESEL_SHIFT 16 -#define DDR_PHY_DX6GCR4_DXREFESEL_MASK 0x007F0000U +#define DDR_PHY_DX6GCR4_DXREFESEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX6GCR4_DXREFESEL_SHIFT 16 +#define DDR_PHY_DX6GCR4_DXREFESEL_MASK 0x007F0000U -/*Single ended VREF generator REFSEL range select*/ +/* +* Single ended VREF generator REFSEL range select +*/ #undef DDR_PHY_DX6GCR4_DXREFSSELRANGE_DEFVAL #undef DDR_PHY_DX6GCR4_DXREFSSELRANGE_SHIFT #undef DDR_PHY_DX6GCR4_DXREFSSELRANGE_MASK -#define DDR_PHY_DX6GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C -#define DDR_PHY_DX6GCR4_DXREFSSELRANGE_SHIFT 15 -#define DDR_PHY_DX6GCR4_DXREFSSELRANGE_MASK 0x00008000U +#define DDR_PHY_DX6GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX6GCR4_DXREFSSELRANGE_SHIFT 15 +#define DDR_PHY_DX6GCR4_DXREFSSELRANGE_MASK 0x00008000U -/*Byte Lane Single-End VREF Select*/ +/* +* Byte Lane Single-End VREF Select +*/ #undef DDR_PHY_DX6GCR4_DXREFSSEL_DEFVAL #undef DDR_PHY_DX6GCR4_DXREFSSEL_SHIFT #undef DDR_PHY_DX6GCR4_DXREFSSEL_MASK -#define DDR_PHY_DX6GCR4_DXREFSSEL_DEFVAL 0x0E00003C -#define DDR_PHY_DX6GCR4_DXREFSSEL_SHIFT 8 -#define DDR_PHY_DX6GCR4_DXREFSSEL_MASK 0x00007F00U +#define DDR_PHY_DX6GCR4_DXREFSSEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX6GCR4_DXREFSSEL_SHIFT 8 +#define DDR_PHY_DX6GCR4_DXREFSSEL_MASK 0x00007F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX6GCR4_RESERVED_7_6_DEFVAL #undef DDR_PHY_DX6GCR4_RESERVED_7_6_SHIFT #undef DDR_PHY_DX6GCR4_RESERVED_7_6_MASK -#define DDR_PHY_DX6GCR4_RESERVED_7_6_DEFVAL 0x0E00003C -#define DDR_PHY_DX6GCR4_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_DX6GCR4_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_DX6GCR4_RESERVED_7_6_DEFVAL 0x0E00003C +#define DDR_PHY_DX6GCR4_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX6GCR4_RESERVED_7_6_MASK 0x000000C0U -/*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/ +/* +* VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. +*/ #undef DDR_PHY_DX6GCR4_DXREFIEN_DEFVAL #undef DDR_PHY_DX6GCR4_DXREFIEN_SHIFT #undef DDR_PHY_DX6GCR4_DXREFIEN_MASK -#define DDR_PHY_DX6GCR4_DXREFIEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX6GCR4_DXREFIEN_SHIFT 2 -#define DDR_PHY_DX6GCR4_DXREFIEN_MASK 0x0000003CU +#define DDR_PHY_DX6GCR4_DXREFIEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX6GCR4_DXREFIEN_SHIFT 2 +#define DDR_PHY_DX6GCR4_DXREFIEN_MASK 0x0000003CU -/*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/ +/* +* VRMON control for DQ IO (Single Ended) buffers of a byte lane. +*/ #undef DDR_PHY_DX6GCR4_DXREFIMON_DEFVAL #undef DDR_PHY_DX6GCR4_DXREFIMON_SHIFT #undef DDR_PHY_DX6GCR4_DXREFIMON_MASK -#define DDR_PHY_DX6GCR4_DXREFIMON_DEFVAL 0x0E00003C -#define DDR_PHY_DX6GCR4_DXREFIMON_SHIFT 0 -#define DDR_PHY_DX6GCR4_DXREFIMON_MASK 0x00000003U +#define DDR_PHY_DX6GCR4_DXREFIMON_DEFVAL 0x0E00003C +#define DDR_PHY_DX6GCR4_DXREFIMON_SHIFT 0 +#define DDR_PHY_DX6GCR4_DXREFIMON_MASK 0x00000003U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX6GCR5_RESERVED_31_DEFVAL #undef DDR_PHY_DX6GCR5_RESERVED_31_SHIFT #undef DDR_PHY_DX6GCR5_RESERVED_31_MASK -#define DDR_PHY_DX6GCR5_RESERVED_31_DEFVAL 0x09090909 -#define DDR_PHY_DX6GCR5_RESERVED_31_SHIFT 31 -#define DDR_PHY_DX6GCR5_RESERVED_31_MASK 0x80000000U +#define DDR_PHY_DX6GCR5_RESERVED_31_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR5_RESERVED_31_SHIFT 31 +#define DDR_PHY_DX6GCR5_RESERVED_31_MASK 0x80000000U -/*Byte Lane internal VREF Select for Rank 3*/ +/* +* Byte Lane internal VREF Select for Rank 3 +*/ #undef DDR_PHY_DX6GCR5_DXREFISELR3_DEFVAL #undef DDR_PHY_DX6GCR5_DXREFISELR3_SHIFT #undef DDR_PHY_DX6GCR5_DXREFISELR3_MASK -#define DDR_PHY_DX6GCR5_DXREFISELR3_DEFVAL 0x09090909 -#define DDR_PHY_DX6GCR5_DXREFISELR3_SHIFT 24 -#define DDR_PHY_DX6GCR5_DXREFISELR3_MASK 0x7F000000U +#define DDR_PHY_DX6GCR5_DXREFISELR3_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR5_DXREFISELR3_SHIFT 24 +#define DDR_PHY_DX6GCR5_DXREFISELR3_MASK 0x7F000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX6GCR5_RESERVED_23_DEFVAL #undef DDR_PHY_DX6GCR5_RESERVED_23_SHIFT #undef DDR_PHY_DX6GCR5_RESERVED_23_MASK -#define DDR_PHY_DX6GCR5_RESERVED_23_DEFVAL 0x09090909 -#define DDR_PHY_DX6GCR5_RESERVED_23_SHIFT 23 -#define DDR_PHY_DX6GCR5_RESERVED_23_MASK 0x00800000U +#define DDR_PHY_DX6GCR5_RESERVED_23_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR5_RESERVED_23_SHIFT 23 +#define DDR_PHY_DX6GCR5_RESERVED_23_MASK 0x00800000U -/*Byte Lane internal VREF Select for Rank 2*/ +/* +* Byte Lane internal VREF Select for Rank 2 +*/ #undef DDR_PHY_DX6GCR5_DXREFISELR2_DEFVAL #undef DDR_PHY_DX6GCR5_DXREFISELR2_SHIFT #undef DDR_PHY_DX6GCR5_DXREFISELR2_MASK -#define DDR_PHY_DX6GCR5_DXREFISELR2_DEFVAL 0x09090909 -#define DDR_PHY_DX6GCR5_DXREFISELR2_SHIFT 16 -#define DDR_PHY_DX6GCR5_DXREFISELR2_MASK 0x007F0000U +#define DDR_PHY_DX6GCR5_DXREFISELR2_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR5_DXREFISELR2_SHIFT 16 +#define DDR_PHY_DX6GCR5_DXREFISELR2_MASK 0x007F0000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX6GCR5_RESERVED_15_DEFVAL #undef DDR_PHY_DX6GCR5_RESERVED_15_SHIFT #undef DDR_PHY_DX6GCR5_RESERVED_15_MASK -#define DDR_PHY_DX6GCR5_RESERVED_15_DEFVAL 0x09090909 -#define DDR_PHY_DX6GCR5_RESERVED_15_SHIFT 15 -#define DDR_PHY_DX6GCR5_RESERVED_15_MASK 0x00008000U +#define DDR_PHY_DX6GCR5_RESERVED_15_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR5_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX6GCR5_RESERVED_15_MASK 0x00008000U -/*Byte Lane internal VREF Select for Rank 1*/ +/* +* Byte Lane internal VREF Select for Rank 1 +*/ #undef DDR_PHY_DX6GCR5_DXREFISELR1_DEFVAL #undef DDR_PHY_DX6GCR5_DXREFISELR1_SHIFT #undef DDR_PHY_DX6GCR5_DXREFISELR1_MASK -#define DDR_PHY_DX6GCR5_DXREFISELR1_DEFVAL 0x09090909 -#define DDR_PHY_DX6GCR5_DXREFISELR1_SHIFT 8 -#define DDR_PHY_DX6GCR5_DXREFISELR1_MASK 0x00007F00U +#define DDR_PHY_DX6GCR5_DXREFISELR1_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR5_DXREFISELR1_SHIFT 8 +#define DDR_PHY_DX6GCR5_DXREFISELR1_MASK 0x00007F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX6GCR5_RESERVED_7_DEFVAL #undef DDR_PHY_DX6GCR5_RESERVED_7_SHIFT #undef DDR_PHY_DX6GCR5_RESERVED_7_MASK -#define DDR_PHY_DX6GCR5_RESERVED_7_DEFVAL 0x09090909 -#define DDR_PHY_DX6GCR5_RESERVED_7_SHIFT 7 -#define DDR_PHY_DX6GCR5_RESERVED_7_MASK 0x00000080U +#define DDR_PHY_DX6GCR5_RESERVED_7_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR5_RESERVED_7_SHIFT 7 +#define DDR_PHY_DX6GCR5_RESERVED_7_MASK 0x00000080U -/*Byte Lane internal VREF Select for Rank 0*/ +/* +* Byte Lane internal VREF Select for Rank 0 +*/ #undef DDR_PHY_DX6GCR5_DXREFISELR0_DEFVAL #undef DDR_PHY_DX6GCR5_DXREFISELR0_SHIFT #undef DDR_PHY_DX6GCR5_DXREFISELR0_MASK -#define DDR_PHY_DX6GCR5_DXREFISELR0_DEFVAL 0x09090909 -#define DDR_PHY_DX6GCR5_DXREFISELR0_SHIFT 0 -#define DDR_PHY_DX6GCR5_DXREFISELR0_MASK 0x0000007FU +#define DDR_PHY_DX6GCR5_DXREFISELR0_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR5_DXREFISELR0_SHIFT 0 +#define DDR_PHY_DX6GCR5_DXREFISELR0_MASK 0x0000007FU -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX6GCR6_RESERVED_31_30_DEFVAL #undef DDR_PHY_DX6GCR6_RESERVED_31_30_SHIFT #undef DDR_PHY_DX6GCR6_RESERVED_31_30_MASK -#define DDR_PHY_DX6GCR6_RESERVED_31_30_DEFVAL 0x09090909 -#define DDR_PHY_DX6GCR6_RESERVED_31_30_SHIFT 30 -#define DDR_PHY_DX6GCR6_RESERVED_31_30_MASK 0xC0000000U +#define DDR_PHY_DX6GCR6_RESERVED_31_30_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR6_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX6GCR6_RESERVED_31_30_MASK 0xC0000000U -/*DRAM DQ VREF Select for Rank3*/ +/* +* DRAM DQ VREF Select for Rank3 +*/ #undef DDR_PHY_DX6GCR6_DXDQVREFR3_DEFVAL #undef DDR_PHY_DX6GCR6_DXDQVREFR3_SHIFT #undef DDR_PHY_DX6GCR6_DXDQVREFR3_MASK -#define DDR_PHY_DX6GCR6_DXDQVREFR3_DEFVAL 0x09090909 -#define DDR_PHY_DX6GCR6_DXDQVREFR3_SHIFT 24 -#define DDR_PHY_DX6GCR6_DXDQVREFR3_MASK 0x3F000000U +#define DDR_PHY_DX6GCR6_DXDQVREFR3_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR6_DXDQVREFR3_SHIFT 24 +#define DDR_PHY_DX6GCR6_DXDQVREFR3_MASK 0x3F000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX6GCR6_RESERVED_23_22_DEFVAL #undef DDR_PHY_DX6GCR6_RESERVED_23_22_SHIFT #undef DDR_PHY_DX6GCR6_RESERVED_23_22_MASK -#define DDR_PHY_DX6GCR6_RESERVED_23_22_DEFVAL 0x09090909 -#define DDR_PHY_DX6GCR6_RESERVED_23_22_SHIFT 22 -#define DDR_PHY_DX6GCR6_RESERVED_23_22_MASK 0x00C00000U +#define DDR_PHY_DX6GCR6_RESERVED_23_22_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR6_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX6GCR6_RESERVED_23_22_MASK 0x00C00000U -/*DRAM DQ VREF Select for Rank2*/ +/* +* DRAM DQ VREF Select for Rank2 +*/ #undef DDR_PHY_DX6GCR6_DXDQVREFR2_DEFVAL #undef DDR_PHY_DX6GCR6_DXDQVREFR2_SHIFT #undef DDR_PHY_DX6GCR6_DXDQVREFR2_MASK -#define DDR_PHY_DX6GCR6_DXDQVREFR2_DEFVAL 0x09090909 -#define DDR_PHY_DX6GCR6_DXDQVREFR2_SHIFT 16 -#define DDR_PHY_DX6GCR6_DXDQVREFR2_MASK 0x003F0000U +#define DDR_PHY_DX6GCR6_DXDQVREFR2_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR6_DXDQVREFR2_SHIFT 16 +#define DDR_PHY_DX6GCR6_DXDQVREFR2_MASK 0x003F0000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX6GCR6_RESERVED_15_14_DEFVAL #undef DDR_PHY_DX6GCR6_RESERVED_15_14_SHIFT #undef DDR_PHY_DX6GCR6_RESERVED_15_14_MASK -#define DDR_PHY_DX6GCR6_RESERVED_15_14_DEFVAL 0x09090909 -#define DDR_PHY_DX6GCR6_RESERVED_15_14_SHIFT 14 -#define DDR_PHY_DX6GCR6_RESERVED_15_14_MASK 0x0000C000U +#define DDR_PHY_DX6GCR6_RESERVED_15_14_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR6_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_DX6GCR6_RESERVED_15_14_MASK 0x0000C000U -/*DRAM DQ VREF Select for Rank1*/ +/* +* DRAM DQ VREF Select for Rank1 +*/ #undef DDR_PHY_DX6GCR6_DXDQVREFR1_DEFVAL #undef DDR_PHY_DX6GCR6_DXDQVREFR1_SHIFT #undef DDR_PHY_DX6GCR6_DXDQVREFR1_MASK -#define DDR_PHY_DX6GCR6_DXDQVREFR1_DEFVAL 0x09090909 -#define DDR_PHY_DX6GCR6_DXDQVREFR1_SHIFT 8 -#define DDR_PHY_DX6GCR6_DXDQVREFR1_MASK 0x00003F00U +#define DDR_PHY_DX6GCR6_DXDQVREFR1_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR6_DXDQVREFR1_SHIFT 8 +#define DDR_PHY_DX6GCR6_DXDQVREFR1_MASK 0x00003F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX6GCR6_RESERVED_7_6_DEFVAL #undef DDR_PHY_DX6GCR6_RESERVED_7_6_SHIFT #undef DDR_PHY_DX6GCR6_RESERVED_7_6_MASK -#define DDR_PHY_DX6GCR6_RESERVED_7_6_DEFVAL 0x09090909 -#define DDR_PHY_DX6GCR6_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_DX6GCR6_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_DX6GCR6_RESERVED_7_6_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR6_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX6GCR6_RESERVED_7_6_MASK 0x000000C0U -/*DRAM DQ VREF Select for Rank0*/ +/* +* DRAM DQ VREF Select for Rank0 +*/ #undef DDR_PHY_DX6GCR6_DXDQVREFR0_DEFVAL #undef DDR_PHY_DX6GCR6_DXDQVREFR0_SHIFT #undef DDR_PHY_DX6GCR6_DXDQVREFR0_MASK -#define DDR_PHY_DX6GCR6_DXDQVREFR0_DEFVAL 0x09090909 -#define DDR_PHY_DX6GCR6_DXDQVREFR0_SHIFT 0 -#define DDR_PHY_DX6GCR6_DXDQVREFR0_MASK 0x0000003FU +#define DDR_PHY_DX6GCR6_DXDQVREFR0_DEFVAL 0x09090909 +#define DDR_PHY_DX6GCR6_DXDQVREFR0_SHIFT 0 +#define DDR_PHY_DX6GCR6_DXDQVREFR0_MASK 0x0000003FU -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX6LCDLR2_RESERVED_31_25_DEFVAL -#undef DDR_PHY_DX6LCDLR2_RESERVED_31_25_SHIFT -#undef DDR_PHY_DX6LCDLR2_RESERVED_31_25_MASK -#define DDR_PHY_DX6LCDLR2_RESERVED_31_25_DEFVAL 0x00000000 -#define DDR_PHY_DX6LCDLR2_RESERVED_31_25_SHIFT 25 -#define DDR_PHY_DX6LCDLR2_RESERVED_31_25_MASK 0xFE000000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX6LCDLR2_RESERVED_24_16_DEFVAL -#undef DDR_PHY_DX6LCDLR2_RESERVED_24_16_SHIFT -#undef DDR_PHY_DX6LCDLR2_RESERVED_24_16_MASK -#define DDR_PHY_DX6LCDLR2_RESERVED_24_16_DEFVAL 0x00000000 -#define DDR_PHY_DX6LCDLR2_RESERVED_24_16_SHIFT 16 -#define DDR_PHY_DX6LCDLR2_RESERVED_24_16_MASK 0x01FF0000U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX6LCDLR2_RESERVED_15_9_DEFVAL -#undef DDR_PHY_DX6LCDLR2_RESERVED_15_9_SHIFT -#undef DDR_PHY_DX6LCDLR2_RESERVED_15_9_MASK -#define DDR_PHY_DX6LCDLR2_RESERVED_15_9_DEFVAL 0x00000000 -#define DDR_PHY_DX6LCDLR2_RESERVED_15_9_SHIFT 9 -#define DDR_PHY_DX6LCDLR2_RESERVED_15_9_MASK 0x0000FE00U - -/*Read DQS Gating Delay*/ -#undef DDR_PHY_DX6LCDLR2_DQSGD_DEFVAL -#undef DDR_PHY_DX6LCDLR2_DQSGD_SHIFT -#undef DDR_PHY_DX6LCDLR2_DQSGD_MASK -#define DDR_PHY_DX6LCDLR2_DQSGD_DEFVAL 0x00000000 -#define DDR_PHY_DX6LCDLR2_DQSGD_SHIFT 0 -#define DDR_PHY_DX6LCDLR2_DQSGD_MASK 0x000001FFU - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX6GTR0_RESERVED_31_24_DEFVAL -#undef DDR_PHY_DX6GTR0_RESERVED_31_24_SHIFT -#undef DDR_PHY_DX6GTR0_RESERVED_31_24_MASK -#define DDR_PHY_DX6GTR0_RESERVED_31_24_DEFVAL 0x00020000 -#define DDR_PHY_DX6GTR0_RESERVED_31_24_SHIFT 27 -#define DDR_PHY_DX6GTR0_RESERVED_31_24_MASK 0xF8000000U - -/*DQ Write Path Latency Pipeline*/ -#undef DDR_PHY_DX6GTR0_WDQSL_DEFVAL -#undef DDR_PHY_DX6GTR0_WDQSL_SHIFT -#undef DDR_PHY_DX6GTR0_WDQSL_MASK -#define DDR_PHY_DX6GTR0_WDQSL_DEFVAL 0x00020000 -#define DDR_PHY_DX6GTR0_WDQSL_SHIFT 24 -#define DDR_PHY_DX6GTR0_WDQSL_MASK 0x07000000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX6GTR0_RESERVED_23_20_DEFVAL -#undef DDR_PHY_DX6GTR0_RESERVED_23_20_SHIFT -#undef DDR_PHY_DX6GTR0_RESERVED_23_20_MASK -#define DDR_PHY_DX6GTR0_RESERVED_23_20_DEFVAL 0x00020000 -#define DDR_PHY_DX6GTR0_RESERVED_23_20_SHIFT 20 -#define DDR_PHY_DX6GTR0_RESERVED_23_20_MASK 0x00F00000U - -/*Write Leveling System Latency*/ -#undef DDR_PHY_DX6GTR0_WLSL_DEFVAL -#undef DDR_PHY_DX6GTR0_WLSL_SHIFT -#undef DDR_PHY_DX6GTR0_WLSL_MASK -#define DDR_PHY_DX6GTR0_WLSL_DEFVAL 0x00020000 -#define DDR_PHY_DX6GTR0_WLSL_SHIFT 16 -#define DDR_PHY_DX6GTR0_WLSL_MASK 0x000F0000U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX6GTR0_RESERVED_15_13_DEFVAL -#undef DDR_PHY_DX6GTR0_RESERVED_15_13_SHIFT -#undef DDR_PHY_DX6GTR0_RESERVED_15_13_MASK -#define DDR_PHY_DX6GTR0_RESERVED_15_13_DEFVAL 0x00020000 -#define DDR_PHY_DX6GTR0_RESERVED_15_13_SHIFT 13 -#define DDR_PHY_DX6GTR0_RESERVED_15_13_MASK 0x0000E000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX6GTR0_RESERVED_12_8_DEFVAL -#undef DDR_PHY_DX6GTR0_RESERVED_12_8_SHIFT -#undef DDR_PHY_DX6GTR0_RESERVED_12_8_MASK -#define DDR_PHY_DX6GTR0_RESERVED_12_8_DEFVAL 0x00020000 -#define DDR_PHY_DX6GTR0_RESERVED_12_8_SHIFT 8 -#define DDR_PHY_DX6GTR0_RESERVED_12_8_MASK 0x00001F00U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX6GTR0_RESERVED_7_5_DEFVAL -#undef DDR_PHY_DX6GTR0_RESERVED_7_5_SHIFT -#undef DDR_PHY_DX6GTR0_RESERVED_7_5_MASK -#define DDR_PHY_DX6GTR0_RESERVED_7_5_DEFVAL 0x00020000 -#define DDR_PHY_DX6GTR0_RESERVED_7_5_SHIFT 5 -#define DDR_PHY_DX6GTR0_RESERVED_7_5_MASK 0x000000E0U - -/*DQS Gating System Latency*/ -#undef DDR_PHY_DX6GTR0_DGSL_DEFVAL -#undef DDR_PHY_DX6GTR0_DGSL_SHIFT -#undef DDR_PHY_DX6GTR0_DGSL_MASK -#define DDR_PHY_DX6GTR0_DGSL_DEFVAL 0x00020000 -#define DDR_PHY_DX6GTR0_DGSL_SHIFT 0 -#define DDR_PHY_DX6GTR0_DGSL_MASK 0x0000001FU - -/*Calibration Bypass*/ +/* +* Calibration Bypass +*/ #undef DDR_PHY_DX7GCR0_CALBYP_DEFVAL #undef DDR_PHY_DX7GCR0_CALBYP_SHIFT #undef DDR_PHY_DX7GCR0_CALBYP_MASK -#define DDR_PHY_DX7GCR0_CALBYP_DEFVAL 0x40200204 -#define DDR_PHY_DX7GCR0_CALBYP_SHIFT 31 -#define DDR_PHY_DX7GCR0_CALBYP_MASK 0x80000000U +#define DDR_PHY_DX7GCR0_CALBYP_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_CALBYP_SHIFT 31 +#define DDR_PHY_DX7GCR0_CALBYP_MASK 0x80000000U -/*Master Delay Line Enable*/ +/* +* Master Delay Line Enable +*/ #undef DDR_PHY_DX7GCR0_MDLEN_DEFVAL #undef DDR_PHY_DX7GCR0_MDLEN_SHIFT #undef DDR_PHY_DX7GCR0_MDLEN_MASK -#define DDR_PHY_DX7GCR0_MDLEN_DEFVAL 0x40200204 -#define DDR_PHY_DX7GCR0_MDLEN_SHIFT 30 -#define DDR_PHY_DX7GCR0_MDLEN_MASK 0x40000000U +#define DDR_PHY_DX7GCR0_MDLEN_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_MDLEN_SHIFT 30 +#define DDR_PHY_DX7GCR0_MDLEN_MASK 0x40000000U -/*Configurable ODT(TE) Phase Shift*/ +/* +* Configurable ODT(TE) Phase Shift +*/ #undef DDR_PHY_DX7GCR0_CODTSHFT_DEFVAL #undef DDR_PHY_DX7GCR0_CODTSHFT_SHIFT #undef DDR_PHY_DX7GCR0_CODTSHFT_MASK -#define DDR_PHY_DX7GCR0_CODTSHFT_DEFVAL 0x40200204 -#define DDR_PHY_DX7GCR0_CODTSHFT_SHIFT 28 -#define DDR_PHY_DX7GCR0_CODTSHFT_MASK 0x30000000U +#define DDR_PHY_DX7GCR0_CODTSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_CODTSHFT_SHIFT 28 +#define DDR_PHY_DX7GCR0_CODTSHFT_MASK 0x30000000U -/*DQS Duty Cycle Correction*/ +/* +* DQS Duty Cycle Correction +*/ #undef DDR_PHY_DX7GCR0_DQSDCC_DEFVAL #undef DDR_PHY_DX7GCR0_DQSDCC_SHIFT #undef DDR_PHY_DX7GCR0_DQSDCC_MASK -#define DDR_PHY_DX7GCR0_DQSDCC_DEFVAL 0x40200204 -#define DDR_PHY_DX7GCR0_DQSDCC_SHIFT 24 -#define DDR_PHY_DX7GCR0_DQSDCC_MASK 0x0F000000U +#define DDR_PHY_DX7GCR0_DQSDCC_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_DQSDCC_SHIFT 24 +#define DDR_PHY_DX7GCR0_DQSDCC_MASK 0x0F000000U -/*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/ +/* +* Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY +*/ #undef DDR_PHY_DX7GCR0_RDDLY_DEFVAL #undef DDR_PHY_DX7GCR0_RDDLY_SHIFT #undef DDR_PHY_DX7GCR0_RDDLY_MASK -#define DDR_PHY_DX7GCR0_RDDLY_DEFVAL 0x40200204 -#define DDR_PHY_DX7GCR0_RDDLY_SHIFT 20 -#define DDR_PHY_DX7GCR0_RDDLY_MASK 0x00F00000U +#define DDR_PHY_DX7GCR0_RDDLY_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_RDDLY_SHIFT 20 +#define DDR_PHY_DX7GCR0_RDDLY_MASK 0x00F00000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX7GCR0_RESERVED_19_14_DEFVAL #undef DDR_PHY_DX7GCR0_RESERVED_19_14_SHIFT #undef DDR_PHY_DX7GCR0_RESERVED_19_14_MASK -#define DDR_PHY_DX7GCR0_RESERVED_19_14_DEFVAL 0x40200204 -#define DDR_PHY_DX7GCR0_RESERVED_19_14_SHIFT 14 -#define DDR_PHY_DX7GCR0_RESERVED_19_14_MASK 0x000FC000U +#define DDR_PHY_DX7GCR0_RESERVED_19_14_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_RESERVED_19_14_SHIFT 14 +#define DDR_PHY_DX7GCR0_RESERVED_19_14_MASK 0x000FC000U -/*DQSNSE Power Down Receiver*/ +/* +* DQSNSE Power Down Receiver +*/ #undef DDR_PHY_DX7GCR0_DQSNSEPDR_DEFVAL #undef DDR_PHY_DX7GCR0_DQSNSEPDR_SHIFT #undef DDR_PHY_DX7GCR0_DQSNSEPDR_MASK -#define DDR_PHY_DX7GCR0_DQSNSEPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX7GCR0_DQSNSEPDR_SHIFT 13 -#define DDR_PHY_DX7GCR0_DQSNSEPDR_MASK 0x00002000U +#define DDR_PHY_DX7GCR0_DQSNSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_DQSNSEPDR_SHIFT 13 +#define DDR_PHY_DX7GCR0_DQSNSEPDR_MASK 0x00002000U -/*DQSSE Power Down Receiver*/ +/* +* DQSSE Power Down Receiver +*/ #undef DDR_PHY_DX7GCR0_DQSSEPDR_DEFVAL #undef DDR_PHY_DX7GCR0_DQSSEPDR_SHIFT #undef DDR_PHY_DX7GCR0_DQSSEPDR_MASK -#define DDR_PHY_DX7GCR0_DQSSEPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX7GCR0_DQSSEPDR_SHIFT 12 -#define DDR_PHY_DX7GCR0_DQSSEPDR_MASK 0x00001000U +#define DDR_PHY_DX7GCR0_DQSSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_DQSSEPDR_SHIFT 12 +#define DDR_PHY_DX7GCR0_DQSSEPDR_MASK 0x00001000U -/*RTT On Additive Latency*/ +/* +* RTT On Additive Latency +*/ #undef DDR_PHY_DX7GCR0_RTTOAL_DEFVAL #undef DDR_PHY_DX7GCR0_RTTOAL_SHIFT #undef DDR_PHY_DX7GCR0_RTTOAL_MASK -#define DDR_PHY_DX7GCR0_RTTOAL_DEFVAL 0x40200204 -#define DDR_PHY_DX7GCR0_RTTOAL_SHIFT 11 -#define DDR_PHY_DX7GCR0_RTTOAL_MASK 0x00000800U +#define DDR_PHY_DX7GCR0_RTTOAL_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_RTTOAL_SHIFT 11 +#define DDR_PHY_DX7GCR0_RTTOAL_MASK 0x00000800U -/*RTT Output Hold*/ +/* +* RTT Output Hold +*/ #undef DDR_PHY_DX7GCR0_RTTOH_DEFVAL #undef DDR_PHY_DX7GCR0_RTTOH_SHIFT #undef DDR_PHY_DX7GCR0_RTTOH_MASK -#define DDR_PHY_DX7GCR0_RTTOH_DEFVAL 0x40200204 -#define DDR_PHY_DX7GCR0_RTTOH_SHIFT 9 -#define DDR_PHY_DX7GCR0_RTTOH_MASK 0x00000600U +#define DDR_PHY_DX7GCR0_RTTOH_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_RTTOH_SHIFT 9 +#define DDR_PHY_DX7GCR0_RTTOH_MASK 0x00000600U -/*Configurable PDR Phase Shift*/ +/* +* Configurable PDR Phase Shift +*/ #undef DDR_PHY_DX7GCR0_CPDRSHFT_DEFVAL #undef DDR_PHY_DX7GCR0_CPDRSHFT_SHIFT #undef DDR_PHY_DX7GCR0_CPDRSHFT_MASK -#define DDR_PHY_DX7GCR0_CPDRSHFT_DEFVAL 0x40200204 -#define DDR_PHY_DX7GCR0_CPDRSHFT_SHIFT 7 -#define DDR_PHY_DX7GCR0_CPDRSHFT_MASK 0x00000180U +#define DDR_PHY_DX7GCR0_CPDRSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_CPDRSHFT_SHIFT 7 +#define DDR_PHY_DX7GCR0_CPDRSHFT_MASK 0x00000180U -/*DQSR Power Down*/ +/* +* DQSR Power Down +*/ #undef DDR_PHY_DX7GCR0_DQSRPD_DEFVAL #undef DDR_PHY_DX7GCR0_DQSRPD_SHIFT #undef DDR_PHY_DX7GCR0_DQSRPD_MASK -#define DDR_PHY_DX7GCR0_DQSRPD_DEFVAL 0x40200204 -#define DDR_PHY_DX7GCR0_DQSRPD_SHIFT 6 -#define DDR_PHY_DX7GCR0_DQSRPD_MASK 0x00000040U +#define DDR_PHY_DX7GCR0_DQSRPD_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_DQSRPD_SHIFT 6 +#define DDR_PHY_DX7GCR0_DQSRPD_MASK 0x00000040U -/*DQSG Power Down Receiver*/ +/* +* DQSG Power Down Receiver +*/ #undef DDR_PHY_DX7GCR0_DQSGPDR_DEFVAL #undef DDR_PHY_DX7GCR0_DQSGPDR_SHIFT #undef DDR_PHY_DX7GCR0_DQSGPDR_MASK -#define DDR_PHY_DX7GCR0_DQSGPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX7GCR0_DQSGPDR_SHIFT 5 -#define DDR_PHY_DX7GCR0_DQSGPDR_MASK 0x00000020U +#define DDR_PHY_DX7GCR0_DQSGPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_DQSGPDR_SHIFT 5 +#define DDR_PHY_DX7GCR0_DQSGPDR_MASK 0x00000020U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX7GCR0_RESERVED_4_DEFVAL #undef DDR_PHY_DX7GCR0_RESERVED_4_SHIFT #undef DDR_PHY_DX7GCR0_RESERVED_4_MASK -#define DDR_PHY_DX7GCR0_RESERVED_4_DEFVAL 0x40200204 -#define DDR_PHY_DX7GCR0_RESERVED_4_SHIFT 4 -#define DDR_PHY_DX7GCR0_RESERVED_4_MASK 0x00000010U +#define DDR_PHY_DX7GCR0_RESERVED_4_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_RESERVED_4_SHIFT 4 +#define DDR_PHY_DX7GCR0_RESERVED_4_MASK 0x00000010U -/*DQSG On-Die Termination*/ +/* +* DQSG On-Die Termination +*/ #undef DDR_PHY_DX7GCR0_DQSGODT_DEFVAL #undef DDR_PHY_DX7GCR0_DQSGODT_SHIFT #undef DDR_PHY_DX7GCR0_DQSGODT_MASK -#define DDR_PHY_DX7GCR0_DQSGODT_DEFVAL 0x40200204 -#define DDR_PHY_DX7GCR0_DQSGODT_SHIFT 3 -#define DDR_PHY_DX7GCR0_DQSGODT_MASK 0x00000008U +#define DDR_PHY_DX7GCR0_DQSGODT_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_DQSGODT_SHIFT 3 +#define DDR_PHY_DX7GCR0_DQSGODT_MASK 0x00000008U -/*DQSG Output Enable*/ +/* +* DQSG Output Enable +*/ #undef DDR_PHY_DX7GCR0_DQSGOE_DEFVAL #undef DDR_PHY_DX7GCR0_DQSGOE_SHIFT #undef DDR_PHY_DX7GCR0_DQSGOE_MASK -#define DDR_PHY_DX7GCR0_DQSGOE_DEFVAL 0x40200204 -#define DDR_PHY_DX7GCR0_DQSGOE_SHIFT 2 -#define DDR_PHY_DX7GCR0_DQSGOE_MASK 0x00000004U +#define DDR_PHY_DX7GCR0_DQSGOE_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_DQSGOE_SHIFT 2 +#define DDR_PHY_DX7GCR0_DQSGOE_MASK 0x00000004U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX7GCR0_RESERVED_1_0_DEFVAL #undef DDR_PHY_DX7GCR0_RESERVED_1_0_SHIFT #undef DDR_PHY_DX7GCR0_RESERVED_1_0_MASK -#define DDR_PHY_DX7GCR0_RESERVED_1_0_DEFVAL 0x40200204 -#define DDR_PHY_DX7GCR0_RESERVED_1_0_SHIFT 0 -#define DDR_PHY_DX7GCR0_RESERVED_1_0_MASK 0x00000003U +#define DDR_PHY_DX7GCR0_RESERVED_1_0_DEFVAL 0x40200204 +#define DDR_PHY_DX7GCR0_RESERVED_1_0_SHIFT 0 +#define DDR_PHY_DX7GCR0_RESERVED_1_0_MASK 0x00000003U -/*Enables the PDR mode for DQ[7:0]*/ +/* +* Enables the PDR mode for DQ[7:0] +*/ #undef DDR_PHY_DX7GCR1_DXPDRMODE_DEFVAL #undef DDR_PHY_DX7GCR1_DXPDRMODE_SHIFT #undef DDR_PHY_DX7GCR1_DXPDRMODE_MASK -#define DDR_PHY_DX7GCR1_DXPDRMODE_DEFVAL 0x00007FFF -#define DDR_PHY_DX7GCR1_DXPDRMODE_SHIFT 16 -#define DDR_PHY_DX7GCR1_DXPDRMODE_MASK 0xFFFF0000U +#define DDR_PHY_DX7GCR1_DXPDRMODE_DEFVAL 0x00007FFF +#define DDR_PHY_DX7GCR1_DXPDRMODE_SHIFT 16 +#define DDR_PHY_DX7GCR1_DXPDRMODE_MASK 0xFFFF0000U -/*Reserved. Returns zeroes on reads.*/ +/* +* Reserved. Returns zeroes on reads. +*/ #undef DDR_PHY_DX7GCR1_RESERVED_15_DEFVAL #undef DDR_PHY_DX7GCR1_RESERVED_15_SHIFT #undef DDR_PHY_DX7GCR1_RESERVED_15_MASK -#define DDR_PHY_DX7GCR1_RESERVED_15_DEFVAL 0x00007FFF -#define DDR_PHY_DX7GCR1_RESERVED_15_SHIFT 15 -#define DDR_PHY_DX7GCR1_RESERVED_15_MASK 0x00008000U +#define DDR_PHY_DX7GCR1_RESERVED_15_DEFVAL 0x00007FFF +#define DDR_PHY_DX7GCR1_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX7GCR1_RESERVED_15_MASK 0x00008000U -/*Select the delayed or non-delayed read data strobe #*/ +/* +* Select the delayed or non-delayed read data strobe # +*/ #undef DDR_PHY_DX7GCR1_QSNSEL_DEFVAL #undef DDR_PHY_DX7GCR1_QSNSEL_SHIFT #undef DDR_PHY_DX7GCR1_QSNSEL_MASK -#define DDR_PHY_DX7GCR1_QSNSEL_DEFVAL 0x00007FFF -#define DDR_PHY_DX7GCR1_QSNSEL_SHIFT 14 -#define DDR_PHY_DX7GCR1_QSNSEL_MASK 0x00004000U +#define DDR_PHY_DX7GCR1_QSNSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX7GCR1_QSNSEL_SHIFT 14 +#define DDR_PHY_DX7GCR1_QSNSEL_MASK 0x00004000U -/*Select the delayed or non-delayed read data strobe*/ +/* +* Select the delayed or non-delayed read data strobe +*/ #undef DDR_PHY_DX7GCR1_QSSEL_DEFVAL #undef DDR_PHY_DX7GCR1_QSSEL_SHIFT #undef DDR_PHY_DX7GCR1_QSSEL_MASK -#define DDR_PHY_DX7GCR1_QSSEL_DEFVAL 0x00007FFF -#define DDR_PHY_DX7GCR1_QSSEL_SHIFT 13 -#define DDR_PHY_DX7GCR1_QSSEL_MASK 0x00002000U +#define DDR_PHY_DX7GCR1_QSSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX7GCR1_QSSEL_SHIFT 13 +#define DDR_PHY_DX7GCR1_QSSEL_MASK 0x00002000U -/*Enables Read Data Strobe in a byte lane*/ +/* +* Enables Read Data Strobe in a byte lane +*/ #undef DDR_PHY_DX7GCR1_OEEN_DEFVAL #undef DDR_PHY_DX7GCR1_OEEN_SHIFT #undef DDR_PHY_DX7GCR1_OEEN_MASK -#define DDR_PHY_DX7GCR1_OEEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX7GCR1_OEEN_SHIFT 12 -#define DDR_PHY_DX7GCR1_OEEN_MASK 0x00001000U +#define DDR_PHY_DX7GCR1_OEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX7GCR1_OEEN_SHIFT 12 +#define DDR_PHY_DX7GCR1_OEEN_MASK 0x00001000U -/*Enables PDR in a byte lane*/ +/* +* Enables PDR in a byte lane +*/ #undef DDR_PHY_DX7GCR1_PDREN_DEFVAL #undef DDR_PHY_DX7GCR1_PDREN_SHIFT #undef DDR_PHY_DX7GCR1_PDREN_MASK -#define DDR_PHY_DX7GCR1_PDREN_DEFVAL 0x00007FFF -#define DDR_PHY_DX7GCR1_PDREN_SHIFT 11 -#define DDR_PHY_DX7GCR1_PDREN_MASK 0x00000800U +#define DDR_PHY_DX7GCR1_PDREN_DEFVAL 0x00007FFF +#define DDR_PHY_DX7GCR1_PDREN_SHIFT 11 +#define DDR_PHY_DX7GCR1_PDREN_MASK 0x00000800U -/*Enables ODT/TE in a byte lane*/ +/* +* Enables ODT/TE in a byte lane +*/ #undef DDR_PHY_DX7GCR1_TEEN_DEFVAL #undef DDR_PHY_DX7GCR1_TEEN_SHIFT #undef DDR_PHY_DX7GCR1_TEEN_MASK -#define DDR_PHY_DX7GCR1_TEEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX7GCR1_TEEN_SHIFT 10 -#define DDR_PHY_DX7GCR1_TEEN_MASK 0x00000400U +#define DDR_PHY_DX7GCR1_TEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX7GCR1_TEEN_SHIFT 10 +#define DDR_PHY_DX7GCR1_TEEN_MASK 0x00000400U -/*Enables Write Data strobe in a byte lane*/ +/* +* Enables Write Data strobe in a byte lane +*/ #undef DDR_PHY_DX7GCR1_DSEN_DEFVAL #undef DDR_PHY_DX7GCR1_DSEN_SHIFT #undef DDR_PHY_DX7GCR1_DSEN_MASK -#define DDR_PHY_DX7GCR1_DSEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX7GCR1_DSEN_SHIFT 9 -#define DDR_PHY_DX7GCR1_DSEN_MASK 0x00000200U +#define DDR_PHY_DX7GCR1_DSEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX7GCR1_DSEN_SHIFT 9 +#define DDR_PHY_DX7GCR1_DSEN_MASK 0x00000200U -/*Enables DM pin in a byte lane*/ +/* +* Enables DM pin in a byte lane +*/ #undef DDR_PHY_DX7GCR1_DMEN_DEFVAL #undef DDR_PHY_DX7GCR1_DMEN_SHIFT #undef DDR_PHY_DX7GCR1_DMEN_MASK -#define DDR_PHY_DX7GCR1_DMEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX7GCR1_DMEN_SHIFT 8 -#define DDR_PHY_DX7GCR1_DMEN_MASK 0x00000100U +#define DDR_PHY_DX7GCR1_DMEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX7GCR1_DMEN_SHIFT 8 +#define DDR_PHY_DX7GCR1_DMEN_MASK 0x00000100U -/*Enables DQ corresponding to each bit in a byte*/ +/* +* Enables DQ corresponding to each bit in a byte +*/ #undef DDR_PHY_DX7GCR1_DQEN_DEFVAL #undef DDR_PHY_DX7GCR1_DQEN_SHIFT #undef DDR_PHY_DX7GCR1_DQEN_MASK -#define DDR_PHY_DX7GCR1_DQEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX7GCR1_DQEN_SHIFT 0 -#define DDR_PHY_DX7GCR1_DQEN_MASK 0x000000FFU +#define DDR_PHY_DX7GCR1_DQEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX7GCR1_DQEN_SHIFT 0 +#define DDR_PHY_DX7GCR1_DQEN_MASK 0x000000FFU -/*Byte lane VREF IOM (Used only by D4MU IOs)*/ +/* +* Byte lane VREF IOM (Used only by D4MU IOs) +*/ #undef DDR_PHY_DX7GCR4_RESERVED_31_29_DEFVAL #undef DDR_PHY_DX7GCR4_RESERVED_31_29_SHIFT #undef DDR_PHY_DX7GCR4_RESERVED_31_29_MASK -#define DDR_PHY_DX7GCR4_RESERVED_31_29_DEFVAL 0x0E00003C -#define DDR_PHY_DX7GCR4_RESERVED_31_29_SHIFT 29 -#define DDR_PHY_DX7GCR4_RESERVED_31_29_MASK 0xE0000000U +#define DDR_PHY_DX7GCR4_RESERVED_31_29_DEFVAL 0x0E00003C +#define DDR_PHY_DX7GCR4_RESERVED_31_29_SHIFT 29 +#define DDR_PHY_DX7GCR4_RESERVED_31_29_MASK 0xE0000000U -/*Byte Lane VREF Pad Enable*/ +/* +* Byte Lane VREF Pad Enable +*/ #undef DDR_PHY_DX7GCR4_DXREFPEN_DEFVAL #undef DDR_PHY_DX7GCR4_DXREFPEN_SHIFT #undef DDR_PHY_DX7GCR4_DXREFPEN_MASK -#define DDR_PHY_DX7GCR4_DXREFPEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX7GCR4_DXREFPEN_SHIFT 28 -#define DDR_PHY_DX7GCR4_DXREFPEN_MASK 0x10000000U +#define DDR_PHY_DX7GCR4_DXREFPEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX7GCR4_DXREFPEN_SHIFT 28 +#define DDR_PHY_DX7GCR4_DXREFPEN_MASK 0x10000000U -/*Byte Lane Internal VREF Enable*/ +/* +* Byte Lane Internal VREF Enable +*/ #undef DDR_PHY_DX7GCR4_DXREFEEN_DEFVAL #undef DDR_PHY_DX7GCR4_DXREFEEN_SHIFT #undef DDR_PHY_DX7GCR4_DXREFEEN_MASK -#define DDR_PHY_DX7GCR4_DXREFEEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX7GCR4_DXREFEEN_SHIFT 26 -#define DDR_PHY_DX7GCR4_DXREFEEN_MASK 0x0C000000U +#define DDR_PHY_DX7GCR4_DXREFEEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX7GCR4_DXREFEEN_SHIFT 26 +#define DDR_PHY_DX7GCR4_DXREFEEN_MASK 0x0C000000U -/*Byte Lane Single-End VREF Enable*/ +/* +* Byte Lane Single-End VREF Enable +*/ #undef DDR_PHY_DX7GCR4_DXREFSEN_DEFVAL #undef DDR_PHY_DX7GCR4_DXREFSEN_SHIFT #undef DDR_PHY_DX7GCR4_DXREFSEN_MASK -#define DDR_PHY_DX7GCR4_DXREFSEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX7GCR4_DXREFSEN_SHIFT 25 -#define DDR_PHY_DX7GCR4_DXREFSEN_MASK 0x02000000U +#define DDR_PHY_DX7GCR4_DXREFSEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX7GCR4_DXREFSEN_SHIFT 25 +#define DDR_PHY_DX7GCR4_DXREFSEN_MASK 0x02000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX7GCR4_RESERVED_24_DEFVAL #undef DDR_PHY_DX7GCR4_RESERVED_24_SHIFT #undef DDR_PHY_DX7GCR4_RESERVED_24_MASK -#define DDR_PHY_DX7GCR4_RESERVED_24_DEFVAL 0x0E00003C -#define DDR_PHY_DX7GCR4_RESERVED_24_SHIFT 24 -#define DDR_PHY_DX7GCR4_RESERVED_24_MASK 0x01000000U +#define DDR_PHY_DX7GCR4_RESERVED_24_DEFVAL 0x0E00003C +#define DDR_PHY_DX7GCR4_RESERVED_24_SHIFT 24 +#define DDR_PHY_DX7GCR4_RESERVED_24_MASK 0x01000000U -/*External VREF generator REFSEL range select*/ +/* +* External VREF generator REFSEL range select +*/ #undef DDR_PHY_DX7GCR4_DXREFESELRANGE_DEFVAL #undef DDR_PHY_DX7GCR4_DXREFESELRANGE_SHIFT #undef DDR_PHY_DX7GCR4_DXREFESELRANGE_MASK -#define DDR_PHY_DX7GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C -#define DDR_PHY_DX7GCR4_DXREFESELRANGE_SHIFT 23 -#define DDR_PHY_DX7GCR4_DXREFESELRANGE_MASK 0x00800000U +#define DDR_PHY_DX7GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX7GCR4_DXREFESELRANGE_SHIFT 23 +#define DDR_PHY_DX7GCR4_DXREFESELRANGE_MASK 0x00800000U -/*Byte Lane External VREF Select*/ +/* +* Byte Lane External VREF Select +*/ #undef DDR_PHY_DX7GCR4_DXREFESEL_DEFVAL #undef DDR_PHY_DX7GCR4_DXREFESEL_SHIFT #undef DDR_PHY_DX7GCR4_DXREFESEL_MASK -#define DDR_PHY_DX7GCR4_DXREFESEL_DEFVAL 0x0E00003C -#define DDR_PHY_DX7GCR4_DXREFESEL_SHIFT 16 -#define DDR_PHY_DX7GCR4_DXREFESEL_MASK 0x007F0000U +#define DDR_PHY_DX7GCR4_DXREFESEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX7GCR4_DXREFESEL_SHIFT 16 +#define DDR_PHY_DX7GCR4_DXREFESEL_MASK 0x007F0000U -/*Single ended VREF generator REFSEL range select*/ +/* +* Single ended VREF generator REFSEL range select +*/ #undef DDR_PHY_DX7GCR4_DXREFSSELRANGE_DEFVAL #undef DDR_PHY_DX7GCR4_DXREFSSELRANGE_SHIFT #undef DDR_PHY_DX7GCR4_DXREFSSELRANGE_MASK -#define DDR_PHY_DX7GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C -#define DDR_PHY_DX7GCR4_DXREFSSELRANGE_SHIFT 15 -#define DDR_PHY_DX7GCR4_DXREFSSELRANGE_MASK 0x00008000U +#define DDR_PHY_DX7GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX7GCR4_DXREFSSELRANGE_SHIFT 15 +#define DDR_PHY_DX7GCR4_DXREFSSELRANGE_MASK 0x00008000U -/*Byte Lane Single-End VREF Select*/ +/* +* Byte Lane Single-End VREF Select +*/ #undef DDR_PHY_DX7GCR4_DXREFSSEL_DEFVAL #undef DDR_PHY_DX7GCR4_DXREFSSEL_SHIFT #undef DDR_PHY_DX7GCR4_DXREFSSEL_MASK -#define DDR_PHY_DX7GCR4_DXREFSSEL_DEFVAL 0x0E00003C -#define DDR_PHY_DX7GCR4_DXREFSSEL_SHIFT 8 -#define DDR_PHY_DX7GCR4_DXREFSSEL_MASK 0x00007F00U +#define DDR_PHY_DX7GCR4_DXREFSSEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX7GCR4_DXREFSSEL_SHIFT 8 +#define DDR_PHY_DX7GCR4_DXREFSSEL_MASK 0x00007F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX7GCR4_RESERVED_7_6_DEFVAL #undef DDR_PHY_DX7GCR4_RESERVED_7_6_SHIFT #undef DDR_PHY_DX7GCR4_RESERVED_7_6_MASK -#define DDR_PHY_DX7GCR4_RESERVED_7_6_DEFVAL 0x0E00003C -#define DDR_PHY_DX7GCR4_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_DX7GCR4_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_DX7GCR4_RESERVED_7_6_DEFVAL 0x0E00003C +#define DDR_PHY_DX7GCR4_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX7GCR4_RESERVED_7_6_MASK 0x000000C0U -/*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/ +/* +* VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. +*/ #undef DDR_PHY_DX7GCR4_DXREFIEN_DEFVAL #undef DDR_PHY_DX7GCR4_DXREFIEN_SHIFT #undef DDR_PHY_DX7GCR4_DXREFIEN_MASK -#define DDR_PHY_DX7GCR4_DXREFIEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX7GCR4_DXREFIEN_SHIFT 2 -#define DDR_PHY_DX7GCR4_DXREFIEN_MASK 0x0000003CU +#define DDR_PHY_DX7GCR4_DXREFIEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX7GCR4_DXREFIEN_SHIFT 2 +#define DDR_PHY_DX7GCR4_DXREFIEN_MASK 0x0000003CU -/*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/ +/* +* VRMON control for DQ IO (Single Ended) buffers of a byte lane. +*/ #undef DDR_PHY_DX7GCR4_DXREFIMON_DEFVAL #undef DDR_PHY_DX7GCR4_DXREFIMON_SHIFT #undef DDR_PHY_DX7GCR4_DXREFIMON_MASK -#define DDR_PHY_DX7GCR4_DXREFIMON_DEFVAL 0x0E00003C -#define DDR_PHY_DX7GCR4_DXREFIMON_SHIFT 0 -#define DDR_PHY_DX7GCR4_DXREFIMON_MASK 0x00000003U +#define DDR_PHY_DX7GCR4_DXREFIMON_DEFVAL 0x0E00003C +#define DDR_PHY_DX7GCR4_DXREFIMON_SHIFT 0 +#define DDR_PHY_DX7GCR4_DXREFIMON_MASK 0x00000003U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX7GCR5_RESERVED_31_DEFVAL #undef DDR_PHY_DX7GCR5_RESERVED_31_SHIFT #undef DDR_PHY_DX7GCR5_RESERVED_31_MASK -#define DDR_PHY_DX7GCR5_RESERVED_31_DEFVAL 0x09090909 -#define DDR_PHY_DX7GCR5_RESERVED_31_SHIFT 31 -#define DDR_PHY_DX7GCR5_RESERVED_31_MASK 0x80000000U +#define DDR_PHY_DX7GCR5_RESERVED_31_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR5_RESERVED_31_SHIFT 31 +#define DDR_PHY_DX7GCR5_RESERVED_31_MASK 0x80000000U -/*Byte Lane internal VREF Select for Rank 3*/ +/* +* Byte Lane internal VREF Select for Rank 3 +*/ #undef DDR_PHY_DX7GCR5_DXREFISELR3_DEFVAL #undef DDR_PHY_DX7GCR5_DXREFISELR3_SHIFT #undef DDR_PHY_DX7GCR5_DXREFISELR3_MASK -#define DDR_PHY_DX7GCR5_DXREFISELR3_DEFVAL 0x09090909 -#define DDR_PHY_DX7GCR5_DXREFISELR3_SHIFT 24 -#define DDR_PHY_DX7GCR5_DXREFISELR3_MASK 0x7F000000U +#define DDR_PHY_DX7GCR5_DXREFISELR3_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR5_DXREFISELR3_SHIFT 24 +#define DDR_PHY_DX7GCR5_DXREFISELR3_MASK 0x7F000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX7GCR5_RESERVED_23_DEFVAL #undef DDR_PHY_DX7GCR5_RESERVED_23_SHIFT #undef DDR_PHY_DX7GCR5_RESERVED_23_MASK -#define DDR_PHY_DX7GCR5_RESERVED_23_DEFVAL 0x09090909 -#define DDR_PHY_DX7GCR5_RESERVED_23_SHIFT 23 -#define DDR_PHY_DX7GCR5_RESERVED_23_MASK 0x00800000U +#define DDR_PHY_DX7GCR5_RESERVED_23_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR5_RESERVED_23_SHIFT 23 +#define DDR_PHY_DX7GCR5_RESERVED_23_MASK 0x00800000U -/*Byte Lane internal VREF Select for Rank 2*/ +/* +* Byte Lane internal VREF Select for Rank 2 +*/ #undef DDR_PHY_DX7GCR5_DXREFISELR2_DEFVAL #undef DDR_PHY_DX7GCR5_DXREFISELR2_SHIFT #undef DDR_PHY_DX7GCR5_DXREFISELR2_MASK -#define DDR_PHY_DX7GCR5_DXREFISELR2_DEFVAL 0x09090909 -#define DDR_PHY_DX7GCR5_DXREFISELR2_SHIFT 16 -#define DDR_PHY_DX7GCR5_DXREFISELR2_MASK 0x007F0000U +#define DDR_PHY_DX7GCR5_DXREFISELR2_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR5_DXREFISELR2_SHIFT 16 +#define DDR_PHY_DX7GCR5_DXREFISELR2_MASK 0x007F0000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX7GCR5_RESERVED_15_DEFVAL #undef DDR_PHY_DX7GCR5_RESERVED_15_SHIFT #undef DDR_PHY_DX7GCR5_RESERVED_15_MASK -#define DDR_PHY_DX7GCR5_RESERVED_15_DEFVAL 0x09090909 -#define DDR_PHY_DX7GCR5_RESERVED_15_SHIFT 15 -#define DDR_PHY_DX7GCR5_RESERVED_15_MASK 0x00008000U +#define DDR_PHY_DX7GCR5_RESERVED_15_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR5_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX7GCR5_RESERVED_15_MASK 0x00008000U -/*Byte Lane internal VREF Select for Rank 1*/ +/* +* Byte Lane internal VREF Select for Rank 1 +*/ #undef DDR_PHY_DX7GCR5_DXREFISELR1_DEFVAL #undef DDR_PHY_DX7GCR5_DXREFISELR1_SHIFT #undef DDR_PHY_DX7GCR5_DXREFISELR1_MASK -#define DDR_PHY_DX7GCR5_DXREFISELR1_DEFVAL 0x09090909 -#define DDR_PHY_DX7GCR5_DXREFISELR1_SHIFT 8 -#define DDR_PHY_DX7GCR5_DXREFISELR1_MASK 0x00007F00U +#define DDR_PHY_DX7GCR5_DXREFISELR1_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR5_DXREFISELR1_SHIFT 8 +#define DDR_PHY_DX7GCR5_DXREFISELR1_MASK 0x00007F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX7GCR5_RESERVED_7_DEFVAL #undef DDR_PHY_DX7GCR5_RESERVED_7_SHIFT #undef DDR_PHY_DX7GCR5_RESERVED_7_MASK -#define DDR_PHY_DX7GCR5_RESERVED_7_DEFVAL 0x09090909 -#define DDR_PHY_DX7GCR5_RESERVED_7_SHIFT 7 -#define DDR_PHY_DX7GCR5_RESERVED_7_MASK 0x00000080U +#define DDR_PHY_DX7GCR5_RESERVED_7_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR5_RESERVED_7_SHIFT 7 +#define DDR_PHY_DX7GCR5_RESERVED_7_MASK 0x00000080U -/*Byte Lane internal VREF Select for Rank 0*/ +/* +* Byte Lane internal VREF Select for Rank 0 +*/ #undef DDR_PHY_DX7GCR5_DXREFISELR0_DEFVAL #undef DDR_PHY_DX7GCR5_DXREFISELR0_SHIFT #undef DDR_PHY_DX7GCR5_DXREFISELR0_MASK -#define DDR_PHY_DX7GCR5_DXREFISELR0_DEFVAL 0x09090909 -#define DDR_PHY_DX7GCR5_DXREFISELR0_SHIFT 0 -#define DDR_PHY_DX7GCR5_DXREFISELR0_MASK 0x0000007FU +#define DDR_PHY_DX7GCR5_DXREFISELR0_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR5_DXREFISELR0_SHIFT 0 +#define DDR_PHY_DX7GCR5_DXREFISELR0_MASK 0x0000007FU -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX7GCR6_RESERVED_31_30_DEFVAL #undef DDR_PHY_DX7GCR6_RESERVED_31_30_SHIFT #undef DDR_PHY_DX7GCR6_RESERVED_31_30_MASK -#define DDR_PHY_DX7GCR6_RESERVED_31_30_DEFVAL 0x09090909 -#define DDR_PHY_DX7GCR6_RESERVED_31_30_SHIFT 30 -#define DDR_PHY_DX7GCR6_RESERVED_31_30_MASK 0xC0000000U +#define DDR_PHY_DX7GCR6_RESERVED_31_30_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR6_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX7GCR6_RESERVED_31_30_MASK 0xC0000000U -/*DRAM DQ VREF Select for Rank3*/ +/* +* DRAM DQ VREF Select for Rank3 +*/ #undef DDR_PHY_DX7GCR6_DXDQVREFR3_DEFVAL #undef DDR_PHY_DX7GCR6_DXDQVREFR3_SHIFT #undef DDR_PHY_DX7GCR6_DXDQVREFR3_MASK -#define DDR_PHY_DX7GCR6_DXDQVREFR3_DEFVAL 0x09090909 -#define DDR_PHY_DX7GCR6_DXDQVREFR3_SHIFT 24 -#define DDR_PHY_DX7GCR6_DXDQVREFR3_MASK 0x3F000000U +#define DDR_PHY_DX7GCR6_DXDQVREFR3_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR6_DXDQVREFR3_SHIFT 24 +#define DDR_PHY_DX7GCR6_DXDQVREFR3_MASK 0x3F000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX7GCR6_RESERVED_23_22_DEFVAL #undef DDR_PHY_DX7GCR6_RESERVED_23_22_SHIFT #undef DDR_PHY_DX7GCR6_RESERVED_23_22_MASK -#define DDR_PHY_DX7GCR6_RESERVED_23_22_DEFVAL 0x09090909 -#define DDR_PHY_DX7GCR6_RESERVED_23_22_SHIFT 22 -#define DDR_PHY_DX7GCR6_RESERVED_23_22_MASK 0x00C00000U +#define DDR_PHY_DX7GCR6_RESERVED_23_22_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR6_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX7GCR6_RESERVED_23_22_MASK 0x00C00000U -/*DRAM DQ VREF Select for Rank2*/ +/* +* DRAM DQ VREF Select for Rank2 +*/ #undef DDR_PHY_DX7GCR6_DXDQVREFR2_DEFVAL #undef DDR_PHY_DX7GCR6_DXDQVREFR2_SHIFT #undef DDR_PHY_DX7GCR6_DXDQVREFR2_MASK -#define DDR_PHY_DX7GCR6_DXDQVREFR2_DEFVAL 0x09090909 -#define DDR_PHY_DX7GCR6_DXDQVREFR2_SHIFT 16 -#define DDR_PHY_DX7GCR6_DXDQVREFR2_MASK 0x003F0000U +#define DDR_PHY_DX7GCR6_DXDQVREFR2_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR6_DXDQVREFR2_SHIFT 16 +#define DDR_PHY_DX7GCR6_DXDQVREFR2_MASK 0x003F0000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX7GCR6_RESERVED_15_14_DEFVAL #undef DDR_PHY_DX7GCR6_RESERVED_15_14_SHIFT #undef DDR_PHY_DX7GCR6_RESERVED_15_14_MASK -#define DDR_PHY_DX7GCR6_RESERVED_15_14_DEFVAL 0x09090909 -#define DDR_PHY_DX7GCR6_RESERVED_15_14_SHIFT 14 -#define DDR_PHY_DX7GCR6_RESERVED_15_14_MASK 0x0000C000U +#define DDR_PHY_DX7GCR6_RESERVED_15_14_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR6_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_DX7GCR6_RESERVED_15_14_MASK 0x0000C000U -/*DRAM DQ VREF Select for Rank1*/ +/* +* DRAM DQ VREF Select for Rank1 +*/ #undef DDR_PHY_DX7GCR6_DXDQVREFR1_DEFVAL #undef DDR_PHY_DX7GCR6_DXDQVREFR1_SHIFT #undef DDR_PHY_DX7GCR6_DXDQVREFR1_MASK -#define DDR_PHY_DX7GCR6_DXDQVREFR1_DEFVAL 0x09090909 -#define DDR_PHY_DX7GCR6_DXDQVREFR1_SHIFT 8 -#define DDR_PHY_DX7GCR6_DXDQVREFR1_MASK 0x00003F00U +#define DDR_PHY_DX7GCR6_DXDQVREFR1_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR6_DXDQVREFR1_SHIFT 8 +#define DDR_PHY_DX7GCR6_DXDQVREFR1_MASK 0x00003F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX7GCR6_RESERVED_7_6_DEFVAL #undef DDR_PHY_DX7GCR6_RESERVED_7_6_SHIFT #undef DDR_PHY_DX7GCR6_RESERVED_7_6_MASK -#define DDR_PHY_DX7GCR6_RESERVED_7_6_DEFVAL 0x09090909 -#define DDR_PHY_DX7GCR6_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_DX7GCR6_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_DX7GCR6_RESERVED_7_6_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR6_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX7GCR6_RESERVED_7_6_MASK 0x000000C0U -/*DRAM DQ VREF Select for Rank0*/ +/* +* DRAM DQ VREF Select for Rank0 +*/ #undef DDR_PHY_DX7GCR6_DXDQVREFR0_DEFVAL #undef DDR_PHY_DX7GCR6_DXDQVREFR0_SHIFT #undef DDR_PHY_DX7GCR6_DXDQVREFR0_MASK -#define DDR_PHY_DX7GCR6_DXDQVREFR0_DEFVAL 0x09090909 -#define DDR_PHY_DX7GCR6_DXDQVREFR0_SHIFT 0 -#define DDR_PHY_DX7GCR6_DXDQVREFR0_MASK 0x0000003FU +#define DDR_PHY_DX7GCR6_DXDQVREFR0_DEFVAL 0x09090909 +#define DDR_PHY_DX7GCR6_DXDQVREFR0_SHIFT 0 +#define DDR_PHY_DX7GCR6_DXDQVREFR0_MASK 0x0000003FU -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX7LCDLR2_RESERVED_31_25_DEFVAL -#undef DDR_PHY_DX7LCDLR2_RESERVED_31_25_SHIFT -#undef DDR_PHY_DX7LCDLR2_RESERVED_31_25_MASK -#define DDR_PHY_DX7LCDLR2_RESERVED_31_25_DEFVAL 0x00000000 -#define DDR_PHY_DX7LCDLR2_RESERVED_31_25_SHIFT 25 -#define DDR_PHY_DX7LCDLR2_RESERVED_31_25_MASK 0xFE000000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX7LCDLR2_RESERVED_24_16_DEFVAL -#undef DDR_PHY_DX7LCDLR2_RESERVED_24_16_SHIFT -#undef DDR_PHY_DX7LCDLR2_RESERVED_24_16_MASK -#define DDR_PHY_DX7LCDLR2_RESERVED_24_16_DEFVAL 0x00000000 -#define DDR_PHY_DX7LCDLR2_RESERVED_24_16_SHIFT 16 -#define DDR_PHY_DX7LCDLR2_RESERVED_24_16_MASK 0x01FF0000U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX7LCDLR2_RESERVED_15_9_DEFVAL -#undef DDR_PHY_DX7LCDLR2_RESERVED_15_9_SHIFT -#undef DDR_PHY_DX7LCDLR2_RESERVED_15_9_MASK -#define DDR_PHY_DX7LCDLR2_RESERVED_15_9_DEFVAL 0x00000000 -#define DDR_PHY_DX7LCDLR2_RESERVED_15_9_SHIFT 9 -#define DDR_PHY_DX7LCDLR2_RESERVED_15_9_MASK 0x0000FE00U - -/*Read DQS Gating Delay*/ -#undef DDR_PHY_DX7LCDLR2_DQSGD_DEFVAL -#undef DDR_PHY_DX7LCDLR2_DQSGD_SHIFT -#undef DDR_PHY_DX7LCDLR2_DQSGD_MASK -#define DDR_PHY_DX7LCDLR2_DQSGD_DEFVAL 0x00000000 -#define DDR_PHY_DX7LCDLR2_DQSGD_SHIFT 0 -#define DDR_PHY_DX7LCDLR2_DQSGD_MASK 0x000001FFU - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX7GTR0_RESERVED_31_24_DEFVAL -#undef DDR_PHY_DX7GTR0_RESERVED_31_24_SHIFT -#undef DDR_PHY_DX7GTR0_RESERVED_31_24_MASK -#define DDR_PHY_DX7GTR0_RESERVED_31_24_DEFVAL 0x00020000 -#define DDR_PHY_DX7GTR0_RESERVED_31_24_SHIFT 27 -#define DDR_PHY_DX7GTR0_RESERVED_31_24_MASK 0xF8000000U - -/*DQ Write Path Latency Pipeline*/ -#undef DDR_PHY_DX7GTR0_WDQSL_DEFVAL -#undef DDR_PHY_DX7GTR0_WDQSL_SHIFT -#undef DDR_PHY_DX7GTR0_WDQSL_MASK -#define DDR_PHY_DX7GTR0_WDQSL_DEFVAL 0x00020000 -#define DDR_PHY_DX7GTR0_WDQSL_SHIFT 24 -#define DDR_PHY_DX7GTR0_WDQSL_MASK 0x07000000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX7GTR0_RESERVED_23_20_DEFVAL -#undef DDR_PHY_DX7GTR0_RESERVED_23_20_SHIFT -#undef DDR_PHY_DX7GTR0_RESERVED_23_20_MASK -#define DDR_PHY_DX7GTR0_RESERVED_23_20_DEFVAL 0x00020000 -#define DDR_PHY_DX7GTR0_RESERVED_23_20_SHIFT 20 -#define DDR_PHY_DX7GTR0_RESERVED_23_20_MASK 0x00F00000U - -/*Write Leveling System Latency*/ -#undef DDR_PHY_DX7GTR0_WLSL_DEFVAL -#undef DDR_PHY_DX7GTR0_WLSL_SHIFT -#undef DDR_PHY_DX7GTR0_WLSL_MASK -#define DDR_PHY_DX7GTR0_WLSL_DEFVAL 0x00020000 -#define DDR_PHY_DX7GTR0_WLSL_SHIFT 16 -#define DDR_PHY_DX7GTR0_WLSL_MASK 0x000F0000U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX7GTR0_RESERVED_15_13_DEFVAL -#undef DDR_PHY_DX7GTR0_RESERVED_15_13_SHIFT -#undef DDR_PHY_DX7GTR0_RESERVED_15_13_MASK -#define DDR_PHY_DX7GTR0_RESERVED_15_13_DEFVAL 0x00020000 -#define DDR_PHY_DX7GTR0_RESERVED_15_13_SHIFT 13 -#define DDR_PHY_DX7GTR0_RESERVED_15_13_MASK 0x0000E000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX7GTR0_RESERVED_12_8_DEFVAL -#undef DDR_PHY_DX7GTR0_RESERVED_12_8_SHIFT -#undef DDR_PHY_DX7GTR0_RESERVED_12_8_MASK -#define DDR_PHY_DX7GTR0_RESERVED_12_8_DEFVAL 0x00020000 -#define DDR_PHY_DX7GTR0_RESERVED_12_8_SHIFT 8 -#define DDR_PHY_DX7GTR0_RESERVED_12_8_MASK 0x00001F00U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX7GTR0_RESERVED_7_5_DEFVAL -#undef DDR_PHY_DX7GTR0_RESERVED_7_5_SHIFT -#undef DDR_PHY_DX7GTR0_RESERVED_7_5_MASK -#define DDR_PHY_DX7GTR0_RESERVED_7_5_DEFVAL 0x00020000 -#define DDR_PHY_DX7GTR0_RESERVED_7_5_SHIFT 5 -#define DDR_PHY_DX7GTR0_RESERVED_7_5_MASK 0x000000E0U - -/*DQS Gating System Latency*/ -#undef DDR_PHY_DX7GTR0_DGSL_DEFVAL -#undef DDR_PHY_DX7GTR0_DGSL_SHIFT -#undef DDR_PHY_DX7GTR0_DGSL_MASK -#define DDR_PHY_DX7GTR0_DGSL_DEFVAL 0x00020000 -#define DDR_PHY_DX7GTR0_DGSL_SHIFT 0 -#define DDR_PHY_DX7GTR0_DGSL_MASK 0x0000001FU - -/*Calibration Bypass*/ +/* +* Calibration Bypass +*/ #undef DDR_PHY_DX8GCR0_CALBYP_DEFVAL #undef DDR_PHY_DX8GCR0_CALBYP_SHIFT #undef DDR_PHY_DX8GCR0_CALBYP_MASK -#define DDR_PHY_DX8GCR0_CALBYP_DEFVAL 0x40200204 -#define DDR_PHY_DX8GCR0_CALBYP_SHIFT 31 -#define DDR_PHY_DX8GCR0_CALBYP_MASK 0x80000000U +#define DDR_PHY_DX8GCR0_CALBYP_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_CALBYP_SHIFT 31 +#define DDR_PHY_DX8GCR0_CALBYP_MASK 0x80000000U -/*Master Delay Line Enable*/ +/* +* Master Delay Line Enable +*/ #undef DDR_PHY_DX8GCR0_MDLEN_DEFVAL #undef DDR_PHY_DX8GCR0_MDLEN_SHIFT #undef DDR_PHY_DX8GCR0_MDLEN_MASK -#define DDR_PHY_DX8GCR0_MDLEN_DEFVAL 0x40200204 -#define DDR_PHY_DX8GCR0_MDLEN_SHIFT 30 -#define DDR_PHY_DX8GCR0_MDLEN_MASK 0x40000000U +#define DDR_PHY_DX8GCR0_MDLEN_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_MDLEN_SHIFT 30 +#define DDR_PHY_DX8GCR0_MDLEN_MASK 0x40000000U -/*Configurable ODT(TE) Phase Shift*/ +/* +* Configurable ODT(TE) Phase Shift +*/ #undef DDR_PHY_DX8GCR0_CODTSHFT_DEFVAL #undef DDR_PHY_DX8GCR0_CODTSHFT_SHIFT #undef DDR_PHY_DX8GCR0_CODTSHFT_MASK -#define DDR_PHY_DX8GCR0_CODTSHFT_DEFVAL 0x40200204 -#define DDR_PHY_DX8GCR0_CODTSHFT_SHIFT 28 -#define DDR_PHY_DX8GCR0_CODTSHFT_MASK 0x30000000U +#define DDR_PHY_DX8GCR0_CODTSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_CODTSHFT_SHIFT 28 +#define DDR_PHY_DX8GCR0_CODTSHFT_MASK 0x30000000U -/*DQS Duty Cycle Correction*/ +/* +* DQS Duty Cycle Correction +*/ #undef DDR_PHY_DX8GCR0_DQSDCC_DEFVAL #undef DDR_PHY_DX8GCR0_DQSDCC_SHIFT #undef DDR_PHY_DX8GCR0_DQSDCC_MASK -#define DDR_PHY_DX8GCR0_DQSDCC_DEFVAL 0x40200204 -#define DDR_PHY_DX8GCR0_DQSDCC_SHIFT 24 -#define DDR_PHY_DX8GCR0_DQSDCC_MASK 0x0F000000U +#define DDR_PHY_DX8GCR0_DQSDCC_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_DQSDCC_SHIFT 24 +#define DDR_PHY_DX8GCR0_DQSDCC_MASK 0x0F000000U -/*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/ +/* +* Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd + * input for the respective bypte lane of the PHY +*/ #undef DDR_PHY_DX8GCR0_RDDLY_DEFVAL #undef DDR_PHY_DX8GCR0_RDDLY_SHIFT #undef DDR_PHY_DX8GCR0_RDDLY_MASK -#define DDR_PHY_DX8GCR0_RDDLY_DEFVAL 0x40200204 -#define DDR_PHY_DX8GCR0_RDDLY_SHIFT 20 -#define DDR_PHY_DX8GCR0_RDDLY_MASK 0x00F00000U +#define DDR_PHY_DX8GCR0_RDDLY_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_RDDLY_SHIFT 20 +#define DDR_PHY_DX8GCR0_RDDLY_MASK 0x00F00000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8GCR0_RESERVED_19_14_DEFVAL #undef DDR_PHY_DX8GCR0_RESERVED_19_14_SHIFT #undef DDR_PHY_DX8GCR0_RESERVED_19_14_MASK -#define DDR_PHY_DX8GCR0_RESERVED_19_14_DEFVAL 0x40200204 -#define DDR_PHY_DX8GCR0_RESERVED_19_14_SHIFT 14 -#define DDR_PHY_DX8GCR0_RESERVED_19_14_MASK 0x000FC000U +#define DDR_PHY_DX8GCR0_RESERVED_19_14_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_RESERVED_19_14_SHIFT 14 +#define DDR_PHY_DX8GCR0_RESERVED_19_14_MASK 0x000FC000U -/*DQSNSE Power Down Receiver*/ +/* +* DQSNSE Power Down Receiver +*/ #undef DDR_PHY_DX8GCR0_DQSNSEPDR_DEFVAL #undef DDR_PHY_DX8GCR0_DQSNSEPDR_SHIFT #undef DDR_PHY_DX8GCR0_DQSNSEPDR_MASK -#define DDR_PHY_DX8GCR0_DQSNSEPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX8GCR0_DQSNSEPDR_SHIFT 13 -#define DDR_PHY_DX8GCR0_DQSNSEPDR_MASK 0x00002000U +#define DDR_PHY_DX8GCR0_DQSNSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_DQSNSEPDR_SHIFT 13 +#define DDR_PHY_DX8GCR0_DQSNSEPDR_MASK 0x00002000U -/*DQSSE Power Down Receiver*/ +/* +* DQSSE Power Down Receiver +*/ #undef DDR_PHY_DX8GCR0_DQSSEPDR_DEFVAL #undef DDR_PHY_DX8GCR0_DQSSEPDR_SHIFT #undef DDR_PHY_DX8GCR0_DQSSEPDR_MASK -#define DDR_PHY_DX8GCR0_DQSSEPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX8GCR0_DQSSEPDR_SHIFT 12 -#define DDR_PHY_DX8GCR0_DQSSEPDR_MASK 0x00001000U +#define DDR_PHY_DX8GCR0_DQSSEPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_DQSSEPDR_SHIFT 12 +#define DDR_PHY_DX8GCR0_DQSSEPDR_MASK 0x00001000U -/*RTT On Additive Latency*/ +/* +* RTT On Additive Latency +*/ #undef DDR_PHY_DX8GCR0_RTTOAL_DEFVAL #undef DDR_PHY_DX8GCR0_RTTOAL_SHIFT #undef DDR_PHY_DX8GCR0_RTTOAL_MASK -#define DDR_PHY_DX8GCR0_RTTOAL_DEFVAL 0x40200204 -#define DDR_PHY_DX8GCR0_RTTOAL_SHIFT 11 -#define DDR_PHY_DX8GCR0_RTTOAL_MASK 0x00000800U +#define DDR_PHY_DX8GCR0_RTTOAL_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_RTTOAL_SHIFT 11 +#define DDR_PHY_DX8GCR0_RTTOAL_MASK 0x00000800U -/*RTT Output Hold*/ +/* +* RTT Output Hold +*/ #undef DDR_PHY_DX8GCR0_RTTOH_DEFVAL #undef DDR_PHY_DX8GCR0_RTTOH_SHIFT #undef DDR_PHY_DX8GCR0_RTTOH_MASK -#define DDR_PHY_DX8GCR0_RTTOH_DEFVAL 0x40200204 -#define DDR_PHY_DX8GCR0_RTTOH_SHIFT 9 -#define DDR_PHY_DX8GCR0_RTTOH_MASK 0x00000600U +#define DDR_PHY_DX8GCR0_RTTOH_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_RTTOH_SHIFT 9 +#define DDR_PHY_DX8GCR0_RTTOH_MASK 0x00000600U -/*Configurable PDR Phase Shift*/ +/* +* Configurable PDR Phase Shift +*/ #undef DDR_PHY_DX8GCR0_CPDRSHFT_DEFVAL #undef DDR_PHY_DX8GCR0_CPDRSHFT_SHIFT #undef DDR_PHY_DX8GCR0_CPDRSHFT_MASK -#define DDR_PHY_DX8GCR0_CPDRSHFT_DEFVAL 0x40200204 -#define DDR_PHY_DX8GCR0_CPDRSHFT_SHIFT 7 -#define DDR_PHY_DX8GCR0_CPDRSHFT_MASK 0x00000180U +#define DDR_PHY_DX8GCR0_CPDRSHFT_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_CPDRSHFT_SHIFT 7 +#define DDR_PHY_DX8GCR0_CPDRSHFT_MASK 0x00000180U -/*DQSR Power Down*/ +/* +* DQSR Power Down +*/ #undef DDR_PHY_DX8GCR0_DQSRPD_DEFVAL #undef DDR_PHY_DX8GCR0_DQSRPD_SHIFT #undef DDR_PHY_DX8GCR0_DQSRPD_MASK -#define DDR_PHY_DX8GCR0_DQSRPD_DEFVAL 0x40200204 -#define DDR_PHY_DX8GCR0_DQSRPD_SHIFT 6 -#define DDR_PHY_DX8GCR0_DQSRPD_MASK 0x00000040U +#define DDR_PHY_DX8GCR0_DQSRPD_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_DQSRPD_SHIFT 6 +#define DDR_PHY_DX8GCR0_DQSRPD_MASK 0x00000040U -/*DQSG Power Down Receiver*/ +/* +* DQSG Power Down Receiver +*/ #undef DDR_PHY_DX8GCR0_DQSGPDR_DEFVAL #undef DDR_PHY_DX8GCR0_DQSGPDR_SHIFT #undef DDR_PHY_DX8GCR0_DQSGPDR_MASK -#define DDR_PHY_DX8GCR0_DQSGPDR_DEFVAL 0x40200204 -#define DDR_PHY_DX8GCR0_DQSGPDR_SHIFT 5 -#define DDR_PHY_DX8GCR0_DQSGPDR_MASK 0x00000020U +#define DDR_PHY_DX8GCR0_DQSGPDR_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_DQSGPDR_SHIFT 5 +#define DDR_PHY_DX8GCR0_DQSGPDR_MASK 0x00000020U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8GCR0_RESERVED_4_DEFVAL #undef DDR_PHY_DX8GCR0_RESERVED_4_SHIFT #undef DDR_PHY_DX8GCR0_RESERVED_4_MASK -#define DDR_PHY_DX8GCR0_RESERVED_4_DEFVAL 0x40200204 -#define DDR_PHY_DX8GCR0_RESERVED_4_SHIFT 4 -#define DDR_PHY_DX8GCR0_RESERVED_4_MASK 0x00000010U +#define DDR_PHY_DX8GCR0_RESERVED_4_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_RESERVED_4_SHIFT 4 +#define DDR_PHY_DX8GCR0_RESERVED_4_MASK 0x00000010U -/*DQSG On-Die Termination*/ +/* +* DQSG On-Die Termination +*/ #undef DDR_PHY_DX8GCR0_DQSGODT_DEFVAL #undef DDR_PHY_DX8GCR0_DQSGODT_SHIFT #undef DDR_PHY_DX8GCR0_DQSGODT_MASK -#define DDR_PHY_DX8GCR0_DQSGODT_DEFVAL 0x40200204 -#define DDR_PHY_DX8GCR0_DQSGODT_SHIFT 3 -#define DDR_PHY_DX8GCR0_DQSGODT_MASK 0x00000008U +#define DDR_PHY_DX8GCR0_DQSGODT_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_DQSGODT_SHIFT 3 +#define DDR_PHY_DX8GCR0_DQSGODT_MASK 0x00000008U -/*DQSG Output Enable*/ +/* +* DQSG Output Enable +*/ #undef DDR_PHY_DX8GCR0_DQSGOE_DEFVAL #undef DDR_PHY_DX8GCR0_DQSGOE_SHIFT #undef DDR_PHY_DX8GCR0_DQSGOE_MASK -#define DDR_PHY_DX8GCR0_DQSGOE_DEFVAL 0x40200204 -#define DDR_PHY_DX8GCR0_DQSGOE_SHIFT 2 -#define DDR_PHY_DX8GCR0_DQSGOE_MASK 0x00000004U +#define DDR_PHY_DX8GCR0_DQSGOE_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_DQSGOE_SHIFT 2 +#define DDR_PHY_DX8GCR0_DQSGOE_MASK 0x00000004U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8GCR0_RESERVED_1_0_DEFVAL #undef DDR_PHY_DX8GCR0_RESERVED_1_0_SHIFT #undef DDR_PHY_DX8GCR0_RESERVED_1_0_MASK -#define DDR_PHY_DX8GCR0_RESERVED_1_0_DEFVAL 0x40200204 -#define DDR_PHY_DX8GCR0_RESERVED_1_0_SHIFT 0 -#define DDR_PHY_DX8GCR0_RESERVED_1_0_MASK 0x00000003U +#define DDR_PHY_DX8GCR0_RESERVED_1_0_DEFVAL 0x40200204 +#define DDR_PHY_DX8GCR0_RESERVED_1_0_SHIFT 0 +#define DDR_PHY_DX8GCR0_RESERVED_1_0_MASK 0x00000003U -/*Enables the PDR mode for DQ[7:0]*/ +/* +* Enables the PDR mode for DQ[7:0] +*/ #undef DDR_PHY_DX8GCR1_DXPDRMODE_DEFVAL #undef DDR_PHY_DX8GCR1_DXPDRMODE_SHIFT #undef DDR_PHY_DX8GCR1_DXPDRMODE_MASK -#define DDR_PHY_DX8GCR1_DXPDRMODE_DEFVAL 0x00007FFF -#define DDR_PHY_DX8GCR1_DXPDRMODE_SHIFT 16 -#define DDR_PHY_DX8GCR1_DXPDRMODE_MASK 0xFFFF0000U +#define DDR_PHY_DX8GCR1_DXPDRMODE_DEFVAL 0x00007FFF +#define DDR_PHY_DX8GCR1_DXPDRMODE_SHIFT 16 +#define DDR_PHY_DX8GCR1_DXPDRMODE_MASK 0xFFFF0000U -/*Reserved. Returns zeroes on reads.*/ +/* +* Reserved. Returns zeroes on reads. +*/ #undef DDR_PHY_DX8GCR1_RESERVED_15_DEFVAL #undef DDR_PHY_DX8GCR1_RESERVED_15_SHIFT #undef DDR_PHY_DX8GCR1_RESERVED_15_MASK -#define DDR_PHY_DX8GCR1_RESERVED_15_DEFVAL 0x00007FFF -#define DDR_PHY_DX8GCR1_RESERVED_15_SHIFT 15 -#define DDR_PHY_DX8GCR1_RESERVED_15_MASK 0x00008000U +#define DDR_PHY_DX8GCR1_RESERVED_15_DEFVAL 0x00007FFF +#define DDR_PHY_DX8GCR1_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX8GCR1_RESERVED_15_MASK 0x00008000U -/*Select the delayed or non-delayed read data strobe #*/ +/* +* Select the delayed or non-delayed read data strobe # +*/ #undef DDR_PHY_DX8GCR1_QSNSEL_DEFVAL #undef DDR_PHY_DX8GCR1_QSNSEL_SHIFT #undef DDR_PHY_DX8GCR1_QSNSEL_MASK -#define DDR_PHY_DX8GCR1_QSNSEL_DEFVAL 0x00007FFF -#define DDR_PHY_DX8GCR1_QSNSEL_SHIFT 14 -#define DDR_PHY_DX8GCR1_QSNSEL_MASK 0x00004000U +#define DDR_PHY_DX8GCR1_QSNSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX8GCR1_QSNSEL_SHIFT 14 +#define DDR_PHY_DX8GCR1_QSNSEL_MASK 0x00004000U -/*Select the delayed or non-delayed read data strobe*/ +/* +* Select the delayed or non-delayed read data strobe +*/ #undef DDR_PHY_DX8GCR1_QSSEL_DEFVAL #undef DDR_PHY_DX8GCR1_QSSEL_SHIFT #undef DDR_PHY_DX8GCR1_QSSEL_MASK -#define DDR_PHY_DX8GCR1_QSSEL_DEFVAL 0x00007FFF -#define DDR_PHY_DX8GCR1_QSSEL_SHIFT 13 -#define DDR_PHY_DX8GCR1_QSSEL_MASK 0x00002000U +#define DDR_PHY_DX8GCR1_QSSEL_DEFVAL 0x00007FFF +#define DDR_PHY_DX8GCR1_QSSEL_SHIFT 13 +#define DDR_PHY_DX8GCR1_QSSEL_MASK 0x00002000U -/*Enables Read Data Strobe in a byte lane*/ +/* +* Enables Read Data Strobe in a byte lane +*/ #undef DDR_PHY_DX8GCR1_OEEN_DEFVAL #undef DDR_PHY_DX8GCR1_OEEN_SHIFT #undef DDR_PHY_DX8GCR1_OEEN_MASK -#define DDR_PHY_DX8GCR1_OEEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX8GCR1_OEEN_SHIFT 12 -#define DDR_PHY_DX8GCR1_OEEN_MASK 0x00001000U +#define DDR_PHY_DX8GCR1_OEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX8GCR1_OEEN_SHIFT 12 +#define DDR_PHY_DX8GCR1_OEEN_MASK 0x00001000U -/*Enables PDR in a byte lane*/ +/* +* Enables PDR in a byte lane +*/ #undef DDR_PHY_DX8GCR1_PDREN_DEFVAL #undef DDR_PHY_DX8GCR1_PDREN_SHIFT #undef DDR_PHY_DX8GCR1_PDREN_MASK -#define DDR_PHY_DX8GCR1_PDREN_DEFVAL 0x00007FFF -#define DDR_PHY_DX8GCR1_PDREN_SHIFT 11 -#define DDR_PHY_DX8GCR1_PDREN_MASK 0x00000800U +#define DDR_PHY_DX8GCR1_PDREN_DEFVAL 0x00007FFF +#define DDR_PHY_DX8GCR1_PDREN_SHIFT 11 +#define DDR_PHY_DX8GCR1_PDREN_MASK 0x00000800U -/*Enables ODT/TE in a byte lane*/ +/* +* Enables ODT/TE in a byte lane +*/ #undef DDR_PHY_DX8GCR1_TEEN_DEFVAL #undef DDR_PHY_DX8GCR1_TEEN_SHIFT #undef DDR_PHY_DX8GCR1_TEEN_MASK -#define DDR_PHY_DX8GCR1_TEEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX8GCR1_TEEN_SHIFT 10 -#define DDR_PHY_DX8GCR1_TEEN_MASK 0x00000400U +#define DDR_PHY_DX8GCR1_TEEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX8GCR1_TEEN_SHIFT 10 +#define DDR_PHY_DX8GCR1_TEEN_MASK 0x00000400U -/*Enables Write Data strobe in a byte lane*/ +/* +* Enables Write Data strobe in a byte lane +*/ #undef DDR_PHY_DX8GCR1_DSEN_DEFVAL #undef DDR_PHY_DX8GCR1_DSEN_SHIFT #undef DDR_PHY_DX8GCR1_DSEN_MASK -#define DDR_PHY_DX8GCR1_DSEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX8GCR1_DSEN_SHIFT 9 -#define DDR_PHY_DX8GCR1_DSEN_MASK 0x00000200U +#define DDR_PHY_DX8GCR1_DSEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX8GCR1_DSEN_SHIFT 9 +#define DDR_PHY_DX8GCR1_DSEN_MASK 0x00000200U -/*Enables DM pin in a byte lane*/ +/* +* Enables DM pin in a byte lane +*/ #undef DDR_PHY_DX8GCR1_DMEN_DEFVAL #undef DDR_PHY_DX8GCR1_DMEN_SHIFT #undef DDR_PHY_DX8GCR1_DMEN_MASK -#define DDR_PHY_DX8GCR1_DMEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX8GCR1_DMEN_SHIFT 8 -#define DDR_PHY_DX8GCR1_DMEN_MASK 0x00000100U +#define DDR_PHY_DX8GCR1_DMEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX8GCR1_DMEN_SHIFT 8 +#define DDR_PHY_DX8GCR1_DMEN_MASK 0x00000100U -/*Enables DQ corresponding to each bit in a byte*/ +/* +* Enables DQ corresponding to each bit in a byte +*/ #undef DDR_PHY_DX8GCR1_DQEN_DEFVAL #undef DDR_PHY_DX8GCR1_DQEN_SHIFT #undef DDR_PHY_DX8GCR1_DQEN_MASK -#define DDR_PHY_DX8GCR1_DQEN_DEFVAL 0x00007FFF -#define DDR_PHY_DX8GCR1_DQEN_SHIFT 0 -#define DDR_PHY_DX8GCR1_DQEN_MASK 0x000000FFU +#define DDR_PHY_DX8GCR1_DQEN_DEFVAL 0x00007FFF +#define DDR_PHY_DX8GCR1_DQEN_SHIFT 0 +#define DDR_PHY_DX8GCR1_DQEN_MASK 0x000000FFU -/*Byte lane VREF IOM (Used only by D4MU IOs)*/ +/* +* Byte lane VREF IOM (Used only by D4MU IOs) +*/ #undef DDR_PHY_DX8GCR4_RESERVED_31_29_DEFVAL #undef DDR_PHY_DX8GCR4_RESERVED_31_29_SHIFT #undef DDR_PHY_DX8GCR4_RESERVED_31_29_MASK -#define DDR_PHY_DX8GCR4_RESERVED_31_29_DEFVAL 0x0E00003C -#define DDR_PHY_DX8GCR4_RESERVED_31_29_SHIFT 29 -#define DDR_PHY_DX8GCR4_RESERVED_31_29_MASK 0xE0000000U +#define DDR_PHY_DX8GCR4_RESERVED_31_29_DEFVAL 0x0E00003C +#define DDR_PHY_DX8GCR4_RESERVED_31_29_SHIFT 29 +#define DDR_PHY_DX8GCR4_RESERVED_31_29_MASK 0xE0000000U -/*Byte Lane VREF Pad Enable*/ +/* +* Byte Lane VREF Pad Enable +*/ #undef DDR_PHY_DX8GCR4_DXREFPEN_DEFVAL #undef DDR_PHY_DX8GCR4_DXREFPEN_SHIFT #undef DDR_PHY_DX8GCR4_DXREFPEN_MASK -#define DDR_PHY_DX8GCR4_DXREFPEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX8GCR4_DXREFPEN_SHIFT 28 -#define DDR_PHY_DX8GCR4_DXREFPEN_MASK 0x10000000U +#define DDR_PHY_DX8GCR4_DXREFPEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX8GCR4_DXREFPEN_SHIFT 28 +#define DDR_PHY_DX8GCR4_DXREFPEN_MASK 0x10000000U -/*Byte Lane Internal VREF Enable*/ +/* +* Byte Lane Internal VREF Enable +*/ #undef DDR_PHY_DX8GCR4_DXREFEEN_DEFVAL #undef DDR_PHY_DX8GCR4_DXREFEEN_SHIFT #undef DDR_PHY_DX8GCR4_DXREFEEN_MASK -#define DDR_PHY_DX8GCR4_DXREFEEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX8GCR4_DXREFEEN_SHIFT 26 -#define DDR_PHY_DX8GCR4_DXREFEEN_MASK 0x0C000000U +#define DDR_PHY_DX8GCR4_DXREFEEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX8GCR4_DXREFEEN_SHIFT 26 +#define DDR_PHY_DX8GCR4_DXREFEEN_MASK 0x0C000000U -/*Byte Lane Single-End VREF Enable*/ +/* +* Byte Lane Single-End VREF Enable +*/ #undef DDR_PHY_DX8GCR4_DXREFSEN_DEFVAL #undef DDR_PHY_DX8GCR4_DXREFSEN_SHIFT #undef DDR_PHY_DX8GCR4_DXREFSEN_MASK -#define DDR_PHY_DX8GCR4_DXREFSEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX8GCR4_DXREFSEN_SHIFT 25 -#define DDR_PHY_DX8GCR4_DXREFSEN_MASK 0x02000000U +#define DDR_PHY_DX8GCR4_DXREFSEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX8GCR4_DXREFSEN_SHIFT 25 +#define DDR_PHY_DX8GCR4_DXREFSEN_MASK 0x02000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX8GCR4_RESERVED_24_DEFVAL #undef DDR_PHY_DX8GCR4_RESERVED_24_SHIFT #undef DDR_PHY_DX8GCR4_RESERVED_24_MASK -#define DDR_PHY_DX8GCR4_RESERVED_24_DEFVAL 0x0E00003C -#define DDR_PHY_DX8GCR4_RESERVED_24_SHIFT 24 -#define DDR_PHY_DX8GCR4_RESERVED_24_MASK 0x01000000U +#define DDR_PHY_DX8GCR4_RESERVED_24_DEFVAL 0x0E00003C +#define DDR_PHY_DX8GCR4_RESERVED_24_SHIFT 24 +#define DDR_PHY_DX8GCR4_RESERVED_24_MASK 0x01000000U -/*External VREF generator REFSEL range select*/ +/* +* External VREF generator REFSEL range select +*/ #undef DDR_PHY_DX8GCR4_DXREFESELRANGE_DEFVAL #undef DDR_PHY_DX8GCR4_DXREFESELRANGE_SHIFT #undef DDR_PHY_DX8GCR4_DXREFESELRANGE_MASK -#define DDR_PHY_DX8GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C -#define DDR_PHY_DX8GCR4_DXREFESELRANGE_SHIFT 23 -#define DDR_PHY_DX8GCR4_DXREFESELRANGE_MASK 0x00800000U +#define DDR_PHY_DX8GCR4_DXREFESELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX8GCR4_DXREFESELRANGE_SHIFT 23 +#define DDR_PHY_DX8GCR4_DXREFESELRANGE_MASK 0x00800000U -/*Byte Lane External VREF Select*/ +/* +* Byte Lane External VREF Select +*/ #undef DDR_PHY_DX8GCR4_DXREFESEL_DEFVAL #undef DDR_PHY_DX8GCR4_DXREFESEL_SHIFT #undef DDR_PHY_DX8GCR4_DXREFESEL_MASK -#define DDR_PHY_DX8GCR4_DXREFESEL_DEFVAL 0x0E00003C -#define DDR_PHY_DX8GCR4_DXREFESEL_SHIFT 16 -#define DDR_PHY_DX8GCR4_DXREFESEL_MASK 0x007F0000U +#define DDR_PHY_DX8GCR4_DXREFESEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX8GCR4_DXREFESEL_SHIFT 16 +#define DDR_PHY_DX8GCR4_DXREFESEL_MASK 0x007F0000U -/*Single ended VREF generator REFSEL range select*/ +/* +* Single ended VREF generator REFSEL range select +*/ #undef DDR_PHY_DX8GCR4_DXREFSSELRANGE_DEFVAL #undef DDR_PHY_DX8GCR4_DXREFSSELRANGE_SHIFT #undef DDR_PHY_DX8GCR4_DXREFSSELRANGE_MASK -#define DDR_PHY_DX8GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C -#define DDR_PHY_DX8GCR4_DXREFSSELRANGE_SHIFT 15 -#define DDR_PHY_DX8GCR4_DXREFSSELRANGE_MASK 0x00008000U +#define DDR_PHY_DX8GCR4_DXREFSSELRANGE_DEFVAL 0x0E00003C +#define DDR_PHY_DX8GCR4_DXREFSSELRANGE_SHIFT 15 +#define DDR_PHY_DX8GCR4_DXREFSSELRANGE_MASK 0x00008000U -/*Byte Lane Single-End VREF Select*/ +/* +* Byte Lane Single-End VREF Select +*/ #undef DDR_PHY_DX8GCR4_DXREFSSEL_DEFVAL #undef DDR_PHY_DX8GCR4_DXREFSSEL_SHIFT #undef DDR_PHY_DX8GCR4_DXREFSSEL_MASK -#define DDR_PHY_DX8GCR4_DXREFSSEL_DEFVAL 0x0E00003C -#define DDR_PHY_DX8GCR4_DXREFSSEL_SHIFT 8 -#define DDR_PHY_DX8GCR4_DXREFSSEL_MASK 0x00007F00U +#define DDR_PHY_DX8GCR4_DXREFSSEL_DEFVAL 0x0E00003C +#define DDR_PHY_DX8GCR4_DXREFSSEL_SHIFT 8 +#define DDR_PHY_DX8GCR4_DXREFSSEL_MASK 0x00007F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX8GCR4_RESERVED_7_6_DEFVAL #undef DDR_PHY_DX8GCR4_RESERVED_7_6_SHIFT #undef DDR_PHY_DX8GCR4_RESERVED_7_6_MASK -#define DDR_PHY_DX8GCR4_RESERVED_7_6_DEFVAL 0x0E00003C -#define DDR_PHY_DX8GCR4_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_DX8GCR4_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_DX8GCR4_RESERVED_7_6_DEFVAL 0x0E00003C +#define DDR_PHY_DX8GCR4_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX8GCR4_RESERVED_7_6_MASK 0x000000C0U -/*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/ +/* +* VREF Enable control for DQ IO (Single Ended) buffers of a byte lane. +*/ #undef DDR_PHY_DX8GCR4_DXREFIEN_DEFVAL #undef DDR_PHY_DX8GCR4_DXREFIEN_SHIFT #undef DDR_PHY_DX8GCR4_DXREFIEN_MASK -#define DDR_PHY_DX8GCR4_DXREFIEN_DEFVAL 0x0E00003C -#define DDR_PHY_DX8GCR4_DXREFIEN_SHIFT 2 -#define DDR_PHY_DX8GCR4_DXREFIEN_MASK 0x0000003CU +#define DDR_PHY_DX8GCR4_DXREFIEN_DEFVAL 0x0E00003C +#define DDR_PHY_DX8GCR4_DXREFIEN_SHIFT 2 +#define DDR_PHY_DX8GCR4_DXREFIEN_MASK 0x0000003CU -/*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/ +/* +* VRMON control for DQ IO (Single Ended) buffers of a byte lane. +*/ #undef DDR_PHY_DX8GCR4_DXREFIMON_DEFVAL #undef DDR_PHY_DX8GCR4_DXREFIMON_SHIFT #undef DDR_PHY_DX8GCR4_DXREFIMON_MASK -#define DDR_PHY_DX8GCR4_DXREFIMON_DEFVAL 0x0E00003C -#define DDR_PHY_DX8GCR4_DXREFIMON_SHIFT 0 -#define DDR_PHY_DX8GCR4_DXREFIMON_MASK 0x00000003U +#define DDR_PHY_DX8GCR4_DXREFIMON_DEFVAL 0x0E00003C +#define DDR_PHY_DX8GCR4_DXREFIMON_SHIFT 0 +#define DDR_PHY_DX8GCR4_DXREFIMON_MASK 0x00000003U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX8GCR5_RESERVED_31_DEFVAL #undef DDR_PHY_DX8GCR5_RESERVED_31_SHIFT #undef DDR_PHY_DX8GCR5_RESERVED_31_MASK -#define DDR_PHY_DX8GCR5_RESERVED_31_DEFVAL 0x09090909 -#define DDR_PHY_DX8GCR5_RESERVED_31_SHIFT 31 -#define DDR_PHY_DX8GCR5_RESERVED_31_MASK 0x80000000U +#define DDR_PHY_DX8GCR5_RESERVED_31_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR5_RESERVED_31_SHIFT 31 +#define DDR_PHY_DX8GCR5_RESERVED_31_MASK 0x80000000U -/*Byte Lane internal VREF Select for Rank 3*/ +/* +* Byte Lane internal VREF Select for Rank 3 +*/ #undef DDR_PHY_DX8GCR5_DXREFISELR3_DEFVAL #undef DDR_PHY_DX8GCR5_DXREFISELR3_SHIFT #undef DDR_PHY_DX8GCR5_DXREFISELR3_MASK -#define DDR_PHY_DX8GCR5_DXREFISELR3_DEFVAL 0x09090909 -#define DDR_PHY_DX8GCR5_DXREFISELR3_SHIFT 24 -#define DDR_PHY_DX8GCR5_DXREFISELR3_MASK 0x7F000000U +#define DDR_PHY_DX8GCR5_DXREFISELR3_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR5_DXREFISELR3_SHIFT 24 +#define DDR_PHY_DX8GCR5_DXREFISELR3_MASK 0x7F000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX8GCR5_RESERVED_23_DEFVAL #undef DDR_PHY_DX8GCR5_RESERVED_23_SHIFT #undef DDR_PHY_DX8GCR5_RESERVED_23_MASK -#define DDR_PHY_DX8GCR5_RESERVED_23_DEFVAL 0x09090909 -#define DDR_PHY_DX8GCR5_RESERVED_23_SHIFT 23 -#define DDR_PHY_DX8GCR5_RESERVED_23_MASK 0x00800000U +#define DDR_PHY_DX8GCR5_RESERVED_23_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR5_RESERVED_23_SHIFT 23 +#define DDR_PHY_DX8GCR5_RESERVED_23_MASK 0x00800000U -/*Byte Lane internal VREF Select for Rank 2*/ +/* +* Byte Lane internal VREF Select for Rank 2 +*/ #undef DDR_PHY_DX8GCR5_DXREFISELR2_DEFVAL #undef DDR_PHY_DX8GCR5_DXREFISELR2_SHIFT #undef DDR_PHY_DX8GCR5_DXREFISELR2_MASK -#define DDR_PHY_DX8GCR5_DXREFISELR2_DEFVAL 0x09090909 -#define DDR_PHY_DX8GCR5_DXREFISELR2_SHIFT 16 -#define DDR_PHY_DX8GCR5_DXREFISELR2_MASK 0x007F0000U +#define DDR_PHY_DX8GCR5_DXREFISELR2_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR5_DXREFISELR2_SHIFT 16 +#define DDR_PHY_DX8GCR5_DXREFISELR2_MASK 0x007F0000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX8GCR5_RESERVED_15_DEFVAL #undef DDR_PHY_DX8GCR5_RESERVED_15_SHIFT #undef DDR_PHY_DX8GCR5_RESERVED_15_MASK -#define DDR_PHY_DX8GCR5_RESERVED_15_DEFVAL 0x09090909 -#define DDR_PHY_DX8GCR5_RESERVED_15_SHIFT 15 -#define DDR_PHY_DX8GCR5_RESERVED_15_MASK 0x00008000U +#define DDR_PHY_DX8GCR5_RESERVED_15_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR5_RESERVED_15_SHIFT 15 +#define DDR_PHY_DX8GCR5_RESERVED_15_MASK 0x00008000U -/*Byte Lane internal VREF Select for Rank 1*/ +/* +* Byte Lane internal VREF Select for Rank 1 +*/ #undef DDR_PHY_DX8GCR5_DXREFISELR1_DEFVAL #undef DDR_PHY_DX8GCR5_DXREFISELR1_SHIFT #undef DDR_PHY_DX8GCR5_DXREFISELR1_MASK -#define DDR_PHY_DX8GCR5_DXREFISELR1_DEFVAL 0x09090909 -#define DDR_PHY_DX8GCR5_DXREFISELR1_SHIFT 8 -#define DDR_PHY_DX8GCR5_DXREFISELR1_MASK 0x00007F00U +#define DDR_PHY_DX8GCR5_DXREFISELR1_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR5_DXREFISELR1_SHIFT 8 +#define DDR_PHY_DX8GCR5_DXREFISELR1_MASK 0x00007F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX8GCR5_RESERVED_7_DEFVAL #undef DDR_PHY_DX8GCR5_RESERVED_7_SHIFT #undef DDR_PHY_DX8GCR5_RESERVED_7_MASK -#define DDR_PHY_DX8GCR5_RESERVED_7_DEFVAL 0x09090909 -#define DDR_PHY_DX8GCR5_RESERVED_7_SHIFT 7 -#define DDR_PHY_DX8GCR5_RESERVED_7_MASK 0x00000080U +#define DDR_PHY_DX8GCR5_RESERVED_7_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR5_RESERVED_7_SHIFT 7 +#define DDR_PHY_DX8GCR5_RESERVED_7_MASK 0x00000080U -/*Byte Lane internal VREF Select for Rank 0*/ +/* +* Byte Lane internal VREF Select for Rank 0 +*/ #undef DDR_PHY_DX8GCR5_DXREFISELR0_DEFVAL #undef DDR_PHY_DX8GCR5_DXREFISELR0_SHIFT #undef DDR_PHY_DX8GCR5_DXREFISELR0_MASK -#define DDR_PHY_DX8GCR5_DXREFISELR0_DEFVAL 0x09090909 -#define DDR_PHY_DX8GCR5_DXREFISELR0_SHIFT 0 -#define DDR_PHY_DX8GCR5_DXREFISELR0_MASK 0x0000007FU +#define DDR_PHY_DX8GCR5_DXREFISELR0_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR5_DXREFISELR0_SHIFT 0 +#define DDR_PHY_DX8GCR5_DXREFISELR0_MASK 0x0000007FU -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX8GCR6_RESERVED_31_30_DEFVAL #undef DDR_PHY_DX8GCR6_RESERVED_31_30_SHIFT #undef DDR_PHY_DX8GCR6_RESERVED_31_30_MASK -#define DDR_PHY_DX8GCR6_RESERVED_31_30_DEFVAL 0x09090909 -#define DDR_PHY_DX8GCR6_RESERVED_31_30_SHIFT 30 -#define DDR_PHY_DX8GCR6_RESERVED_31_30_MASK 0xC0000000U +#define DDR_PHY_DX8GCR6_RESERVED_31_30_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR6_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX8GCR6_RESERVED_31_30_MASK 0xC0000000U -/*DRAM DQ VREF Select for Rank3*/ +/* +* DRAM DQ VREF Select for Rank3 +*/ #undef DDR_PHY_DX8GCR6_DXDQVREFR3_DEFVAL #undef DDR_PHY_DX8GCR6_DXDQVREFR3_SHIFT #undef DDR_PHY_DX8GCR6_DXDQVREFR3_MASK -#define DDR_PHY_DX8GCR6_DXDQVREFR3_DEFVAL 0x09090909 -#define DDR_PHY_DX8GCR6_DXDQVREFR3_SHIFT 24 -#define DDR_PHY_DX8GCR6_DXDQVREFR3_MASK 0x3F000000U +#define DDR_PHY_DX8GCR6_DXDQVREFR3_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR6_DXDQVREFR3_SHIFT 24 +#define DDR_PHY_DX8GCR6_DXDQVREFR3_MASK 0x3F000000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX8GCR6_RESERVED_23_22_DEFVAL #undef DDR_PHY_DX8GCR6_RESERVED_23_22_SHIFT #undef DDR_PHY_DX8GCR6_RESERVED_23_22_MASK -#define DDR_PHY_DX8GCR6_RESERVED_23_22_DEFVAL 0x09090909 -#define DDR_PHY_DX8GCR6_RESERVED_23_22_SHIFT 22 -#define DDR_PHY_DX8GCR6_RESERVED_23_22_MASK 0x00C00000U +#define DDR_PHY_DX8GCR6_RESERVED_23_22_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR6_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX8GCR6_RESERVED_23_22_MASK 0x00C00000U -/*DRAM DQ VREF Select for Rank2*/ +/* +* DRAM DQ VREF Select for Rank2 +*/ #undef DDR_PHY_DX8GCR6_DXDQVREFR2_DEFVAL #undef DDR_PHY_DX8GCR6_DXDQVREFR2_SHIFT #undef DDR_PHY_DX8GCR6_DXDQVREFR2_MASK -#define DDR_PHY_DX8GCR6_DXDQVREFR2_DEFVAL 0x09090909 -#define DDR_PHY_DX8GCR6_DXDQVREFR2_SHIFT 16 -#define DDR_PHY_DX8GCR6_DXDQVREFR2_MASK 0x003F0000U +#define DDR_PHY_DX8GCR6_DXDQVREFR2_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR6_DXDQVREFR2_SHIFT 16 +#define DDR_PHY_DX8GCR6_DXDQVREFR2_MASK 0x003F0000U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX8GCR6_RESERVED_15_14_DEFVAL #undef DDR_PHY_DX8GCR6_RESERVED_15_14_SHIFT #undef DDR_PHY_DX8GCR6_RESERVED_15_14_MASK -#define DDR_PHY_DX8GCR6_RESERVED_15_14_DEFVAL 0x09090909 -#define DDR_PHY_DX8GCR6_RESERVED_15_14_SHIFT 14 -#define DDR_PHY_DX8GCR6_RESERVED_15_14_MASK 0x0000C000U +#define DDR_PHY_DX8GCR6_RESERVED_15_14_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR6_RESERVED_15_14_SHIFT 14 +#define DDR_PHY_DX8GCR6_RESERVED_15_14_MASK 0x0000C000U -/*DRAM DQ VREF Select for Rank1*/ +/* +* DRAM DQ VREF Select for Rank1 +*/ #undef DDR_PHY_DX8GCR6_DXDQVREFR1_DEFVAL #undef DDR_PHY_DX8GCR6_DXDQVREFR1_SHIFT #undef DDR_PHY_DX8GCR6_DXDQVREFR1_MASK -#define DDR_PHY_DX8GCR6_DXDQVREFR1_DEFVAL 0x09090909 -#define DDR_PHY_DX8GCR6_DXDQVREFR1_SHIFT 8 -#define DDR_PHY_DX8GCR6_DXDQVREFR1_MASK 0x00003F00U +#define DDR_PHY_DX8GCR6_DXDQVREFR1_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR6_DXDQVREFR1_SHIFT 8 +#define DDR_PHY_DX8GCR6_DXDQVREFR1_MASK 0x00003F00U -/*Reserved. Returns zeros on reads.*/ +/* +* Reserved. Returns zeros on reads. +*/ #undef DDR_PHY_DX8GCR6_RESERVED_7_6_DEFVAL #undef DDR_PHY_DX8GCR6_RESERVED_7_6_SHIFT #undef DDR_PHY_DX8GCR6_RESERVED_7_6_MASK -#define DDR_PHY_DX8GCR6_RESERVED_7_6_DEFVAL 0x09090909 -#define DDR_PHY_DX8GCR6_RESERVED_7_6_SHIFT 6 -#define DDR_PHY_DX8GCR6_RESERVED_7_6_MASK 0x000000C0U +#define DDR_PHY_DX8GCR6_RESERVED_7_6_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR6_RESERVED_7_6_SHIFT 6 +#define DDR_PHY_DX8GCR6_RESERVED_7_6_MASK 0x000000C0U -/*DRAM DQ VREF Select for Rank0*/ +/* +* DRAM DQ VREF Select for Rank0 +*/ #undef DDR_PHY_DX8GCR6_DXDQVREFR0_DEFVAL #undef DDR_PHY_DX8GCR6_DXDQVREFR0_SHIFT #undef DDR_PHY_DX8GCR6_DXDQVREFR0_MASK -#define DDR_PHY_DX8GCR6_DXDQVREFR0_DEFVAL 0x09090909 -#define DDR_PHY_DX8GCR6_DXDQVREFR0_SHIFT 0 -#define DDR_PHY_DX8GCR6_DXDQVREFR0_MASK 0x0000003FU +#define DDR_PHY_DX8GCR6_DXDQVREFR0_DEFVAL 0x09090909 +#define DDR_PHY_DX8GCR6_DXDQVREFR0_SHIFT 0 +#define DDR_PHY_DX8GCR6_DXDQVREFR0_MASK 0x0000003FU -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX8LCDLR2_RESERVED_31_25_DEFVAL -#undef DDR_PHY_DX8LCDLR2_RESERVED_31_25_SHIFT -#undef DDR_PHY_DX8LCDLR2_RESERVED_31_25_MASK -#define DDR_PHY_DX8LCDLR2_RESERVED_31_25_DEFVAL 0x00000000 -#define DDR_PHY_DX8LCDLR2_RESERVED_31_25_SHIFT 25 -#define DDR_PHY_DX8LCDLR2_RESERVED_31_25_MASK 0xFE000000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX8LCDLR2_RESERVED_24_16_DEFVAL -#undef DDR_PHY_DX8LCDLR2_RESERVED_24_16_SHIFT -#undef DDR_PHY_DX8LCDLR2_RESERVED_24_16_MASK -#define DDR_PHY_DX8LCDLR2_RESERVED_24_16_DEFVAL 0x00000000 -#define DDR_PHY_DX8LCDLR2_RESERVED_24_16_SHIFT 16 -#define DDR_PHY_DX8LCDLR2_RESERVED_24_16_MASK 0x01FF0000U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX8LCDLR2_RESERVED_15_9_DEFVAL -#undef DDR_PHY_DX8LCDLR2_RESERVED_15_9_SHIFT -#undef DDR_PHY_DX8LCDLR2_RESERVED_15_9_MASK -#define DDR_PHY_DX8LCDLR2_RESERVED_15_9_DEFVAL 0x00000000 -#define DDR_PHY_DX8LCDLR2_RESERVED_15_9_SHIFT 9 -#define DDR_PHY_DX8LCDLR2_RESERVED_15_9_MASK 0x0000FE00U - -/*Read DQS Gating Delay*/ -#undef DDR_PHY_DX8LCDLR2_DQSGD_DEFVAL -#undef DDR_PHY_DX8LCDLR2_DQSGD_SHIFT -#undef DDR_PHY_DX8LCDLR2_DQSGD_MASK -#define DDR_PHY_DX8LCDLR2_DQSGD_DEFVAL 0x00000000 -#define DDR_PHY_DX8LCDLR2_DQSGD_SHIFT 0 -#define DDR_PHY_DX8LCDLR2_DQSGD_MASK 0x000001FFU - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX8GTR0_RESERVED_31_24_DEFVAL -#undef DDR_PHY_DX8GTR0_RESERVED_31_24_SHIFT -#undef DDR_PHY_DX8GTR0_RESERVED_31_24_MASK -#define DDR_PHY_DX8GTR0_RESERVED_31_24_DEFVAL 0x00020000 -#define DDR_PHY_DX8GTR0_RESERVED_31_24_SHIFT 27 -#define DDR_PHY_DX8GTR0_RESERVED_31_24_MASK 0xF8000000U - -/*DQ Write Path Latency Pipeline*/ -#undef DDR_PHY_DX8GTR0_WDQSL_DEFVAL -#undef DDR_PHY_DX8GTR0_WDQSL_SHIFT -#undef DDR_PHY_DX8GTR0_WDQSL_MASK -#define DDR_PHY_DX8GTR0_WDQSL_DEFVAL 0x00020000 -#define DDR_PHY_DX8GTR0_WDQSL_SHIFT 24 -#define DDR_PHY_DX8GTR0_WDQSL_MASK 0x07000000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX8GTR0_RESERVED_23_20_DEFVAL -#undef DDR_PHY_DX8GTR0_RESERVED_23_20_SHIFT -#undef DDR_PHY_DX8GTR0_RESERVED_23_20_MASK -#define DDR_PHY_DX8GTR0_RESERVED_23_20_DEFVAL 0x00020000 -#define DDR_PHY_DX8GTR0_RESERVED_23_20_SHIFT 20 -#define DDR_PHY_DX8GTR0_RESERVED_23_20_MASK 0x00F00000U - -/*Write Leveling System Latency*/ -#undef DDR_PHY_DX8GTR0_WLSL_DEFVAL -#undef DDR_PHY_DX8GTR0_WLSL_SHIFT -#undef DDR_PHY_DX8GTR0_WLSL_MASK -#define DDR_PHY_DX8GTR0_WLSL_DEFVAL 0x00020000 -#define DDR_PHY_DX8GTR0_WLSL_SHIFT 16 -#define DDR_PHY_DX8GTR0_WLSL_MASK 0x000F0000U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX8GTR0_RESERVED_15_13_DEFVAL -#undef DDR_PHY_DX8GTR0_RESERVED_15_13_SHIFT -#undef DDR_PHY_DX8GTR0_RESERVED_15_13_MASK -#define DDR_PHY_DX8GTR0_RESERVED_15_13_DEFVAL 0x00020000 -#define DDR_PHY_DX8GTR0_RESERVED_15_13_SHIFT 13 -#define DDR_PHY_DX8GTR0_RESERVED_15_13_MASK 0x0000E000U - -/*Reserved. Caution, do not write to this register field.*/ -#undef DDR_PHY_DX8GTR0_RESERVED_12_8_DEFVAL -#undef DDR_PHY_DX8GTR0_RESERVED_12_8_SHIFT -#undef DDR_PHY_DX8GTR0_RESERVED_12_8_MASK -#define DDR_PHY_DX8GTR0_RESERVED_12_8_DEFVAL 0x00020000 -#define DDR_PHY_DX8GTR0_RESERVED_12_8_SHIFT 8 -#define DDR_PHY_DX8GTR0_RESERVED_12_8_MASK 0x00001F00U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_DX8GTR0_RESERVED_7_5_DEFVAL -#undef DDR_PHY_DX8GTR0_RESERVED_7_5_SHIFT -#undef DDR_PHY_DX8GTR0_RESERVED_7_5_MASK -#define DDR_PHY_DX8GTR0_RESERVED_7_5_DEFVAL 0x00020000 -#define DDR_PHY_DX8GTR0_RESERVED_7_5_SHIFT 5 -#define DDR_PHY_DX8GTR0_RESERVED_7_5_MASK 0x000000E0U - -/*DQS Gating System Latency*/ -#undef DDR_PHY_DX8GTR0_DGSL_DEFVAL -#undef DDR_PHY_DX8GTR0_DGSL_SHIFT -#undef DDR_PHY_DX8GTR0_DGSL_MASK -#define DDR_PHY_DX8GTR0_DGSL_DEFVAL 0x00020000 -#define DDR_PHY_DX8GTR0_DGSL_SHIFT 0 -#define DDR_PHY_DX8GTR0_DGSL_MASK 0x0000001FU - -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL0OSC_RESERVED_31_30_DEFVAL #undef DDR_PHY_DX8SL0OSC_RESERVED_31_30_SHIFT #undef DDR_PHY_DX8SL0OSC_RESERVED_31_30_MASK -#define DDR_PHY_DX8SL0OSC_RESERVED_31_30_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL0OSC_RESERVED_31_30_SHIFT 30 -#define DDR_PHY_DX8SL0OSC_RESERVED_31_30_MASK 0xC0000000U +#define DDR_PHY_DX8SL0OSC_RESERVED_31_30_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX8SL0OSC_RESERVED_31_30_MASK 0xC0000000U -/*Enable Clock Gating for DX ddr_clk*/ +/* +* Enable Clock Gating for DX ddr_clk +*/ #undef DDR_PHY_DX8SL0OSC_GATEDXRDCLK_DEFVAL #undef DDR_PHY_DX8SL0OSC_GATEDXRDCLK_SHIFT #undef DDR_PHY_DX8SL0OSC_GATEDXRDCLK_MASK -#define DDR_PHY_DX8SL0OSC_GATEDXRDCLK_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL0OSC_GATEDXRDCLK_SHIFT 28 -#define DDR_PHY_DX8SL0OSC_GATEDXRDCLK_MASK 0x30000000U +#define DDR_PHY_DX8SL0OSC_GATEDXRDCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_GATEDXRDCLK_SHIFT 28 +#define DDR_PHY_DX8SL0OSC_GATEDXRDCLK_MASK 0x30000000U -/*Enable Clock Gating for DX ctl_rd_clk*/ +/* +* Enable Clock Gating for DX ctl_rd_clk +*/ #undef DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_DEFVAL #undef DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_SHIFT #undef DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_MASK -#define DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_SHIFT 26 -#define DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_MASK 0x0C000000U +#define DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_SHIFT 26 +#define DDR_PHY_DX8SL0OSC_GATEDXDDRCLK_MASK 0x0C000000U -/*Enable Clock Gating for DX ctl_clk*/ +/* +* Enable Clock Gating for DX ctl_clk +*/ #undef DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_DEFVAL #undef DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_SHIFT #undef DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_MASK -#define DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_SHIFT 24 -#define DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_MASK 0x03000000U +#define DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_SHIFT 24 +#define DDR_PHY_DX8SL0OSC_GATEDXCTLCLK_MASK 0x03000000U -/*Selects the level to which clocks will be stalled when clock gating is enabled.*/ +/* +* Selects the level to which clocks will be stalled when clock gating is e + * nabled. +*/ #undef DDR_PHY_DX8SL0OSC_CLKLEVEL_DEFVAL #undef DDR_PHY_DX8SL0OSC_CLKLEVEL_SHIFT #undef DDR_PHY_DX8SL0OSC_CLKLEVEL_MASK -#define DDR_PHY_DX8SL0OSC_CLKLEVEL_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL0OSC_CLKLEVEL_SHIFT 22 -#define DDR_PHY_DX8SL0OSC_CLKLEVEL_MASK 0x00C00000U +#define DDR_PHY_DX8SL0OSC_CLKLEVEL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_CLKLEVEL_SHIFT 22 +#define DDR_PHY_DX8SL0OSC_CLKLEVEL_MASK 0x00C00000U -/*Loopback Mode*/ +/* +* Loopback Mode +*/ #undef DDR_PHY_DX8SL0OSC_LBMODE_DEFVAL #undef DDR_PHY_DX8SL0OSC_LBMODE_SHIFT #undef DDR_PHY_DX8SL0OSC_LBMODE_MASK -#define DDR_PHY_DX8SL0OSC_LBMODE_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL0OSC_LBMODE_SHIFT 21 -#define DDR_PHY_DX8SL0OSC_LBMODE_MASK 0x00200000U +#define DDR_PHY_DX8SL0OSC_LBMODE_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_LBMODE_SHIFT 21 +#define DDR_PHY_DX8SL0OSC_LBMODE_MASK 0x00200000U -/*Load GSDQS LCDL with 2x the calibrated GSDQSPRD value*/ +/* +* Load GSDQS LCDL with 2x the calibrated GSDQSPRD value +*/ #undef DDR_PHY_DX8SL0OSC_LBGSDQS_DEFVAL #undef DDR_PHY_DX8SL0OSC_LBGSDQS_SHIFT #undef DDR_PHY_DX8SL0OSC_LBGSDQS_MASK -#define DDR_PHY_DX8SL0OSC_LBGSDQS_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL0OSC_LBGSDQS_SHIFT 20 -#define DDR_PHY_DX8SL0OSC_LBGSDQS_MASK 0x00100000U +#define DDR_PHY_DX8SL0OSC_LBGSDQS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_LBGSDQS_SHIFT 20 +#define DDR_PHY_DX8SL0OSC_LBGSDQS_MASK 0x00100000U -/*Loopback DQS Gating*/ +/* +* Loopback DQS Gating +*/ #undef DDR_PHY_DX8SL0OSC_LBGDQS_DEFVAL #undef DDR_PHY_DX8SL0OSC_LBGDQS_SHIFT #undef DDR_PHY_DX8SL0OSC_LBGDQS_MASK -#define DDR_PHY_DX8SL0OSC_LBGDQS_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL0OSC_LBGDQS_SHIFT 18 -#define DDR_PHY_DX8SL0OSC_LBGDQS_MASK 0x000C0000U +#define DDR_PHY_DX8SL0OSC_LBGDQS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_LBGDQS_SHIFT 18 +#define DDR_PHY_DX8SL0OSC_LBGDQS_MASK 0x000C0000U -/*Loopback DQS Shift*/ +/* +* Loopback DQS Shift +*/ #undef DDR_PHY_DX8SL0OSC_LBDQSS_DEFVAL #undef DDR_PHY_DX8SL0OSC_LBDQSS_SHIFT #undef DDR_PHY_DX8SL0OSC_LBDQSS_MASK -#define DDR_PHY_DX8SL0OSC_LBDQSS_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL0OSC_LBDQSS_SHIFT 17 -#define DDR_PHY_DX8SL0OSC_LBDQSS_MASK 0x00020000U +#define DDR_PHY_DX8SL0OSC_LBDQSS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_LBDQSS_SHIFT 17 +#define DDR_PHY_DX8SL0OSC_LBDQSS_MASK 0x00020000U -/*PHY High-Speed Reset*/ +/* +* PHY High-Speed Reset +*/ #undef DDR_PHY_DX8SL0OSC_PHYHRST_DEFVAL #undef DDR_PHY_DX8SL0OSC_PHYHRST_SHIFT #undef DDR_PHY_DX8SL0OSC_PHYHRST_MASK -#define DDR_PHY_DX8SL0OSC_PHYHRST_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL0OSC_PHYHRST_SHIFT 16 -#define DDR_PHY_DX8SL0OSC_PHYHRST_MASK 0x00010000U +#define DDR_PHY_DX8SL0OSC_PHYHRST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_PHYHRST_SHIFT 16 +#define DDR_PHY_DX8SL0OSC_PHYHRST_MASK 0x00010000U -/*PHY FIFO Reset*/ +/* +* PHY FIFO Reset +*/ #undef DDR_PHY_DX8SL0OSC_PHYFRST_DEFVAL #undef DDR_PHY_DX8SL0OSC_PHYFRST_SHIFT #undef DDR_PHY_DX8SL0OSC_PHYFRST_MASK -#define DDR_PHY_DX8SL0OSC_PHYFRST_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL0OSC_PHYFRST_SHIFT 15 -#define DDR_PHY_DX8SL0OSC_PHYFRST_MASK 0x00008000U +#define DDR_PHY_DX8SL0OSC_PHYFRST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_PHYFRST_SHIFT 15 +#define DDR_PHY_DX8SL0OSC_PHYFRST_MASK 0x00008000U -/*Delay Line Test Start*/ +/* +* Delay Line Test Start +*/ #undef DDR_PHY_DX8SL0OSC_DLTST_DEFVAL #undef DDR_PHY_DX8SL0OSC_DLTST_SHIFT #undef DDR_PHY_DX8SL0OSC_DLTST_MASK -#define DDR_PHY_DX8SL0OSC_DLTST_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL0OSC_DLTST_SHIFT 14 -#define DDR_PHY_DX8SL0OSC_DLTST_MASK 0x00004000U +#define DDR_PHY_DX8SL0OSC_DLTST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_DLTST_SHIFT 14 +#define DDR_PHY_DX8SL0OSC_DLTST_MASK 0x00004000U -/*Delay Line Test Mode*/ +/* +* Delay Line Test Mode +*/ #undef DDR_PHY_DX8SL0OSC_DLTMODE_DEFVAL #undef DDR_PHY_DX8SL0OSC_DLTMODE_SHIFT #undef DDR_PHY_DX8SL0OSC_DLTMODE_MASK -#define DDR_PHY_DX8SL0OSC_DLTMODE_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL0OSC_DLTMODE_SHIFT 13 -#define DDR_PHY_DX8SL0OSC_DLTMODE_MASK 0x00002000U +#define DDR_PHY_DX8SL0OSC_DLTMODE_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_DLTMODE_SHIFT 13 +#define DDR_PHY_DX8SL0OSC_DLTMODE_MASK 0x00002000U -/*Reserved. Caution, do not write to this register field.*/ +/* +* Reserved. Caution, do not write to this register field. +*/ #undef DDR_PHY_DX8SL0OSC_RESERVED_12_11_DEFVAL #undef DDR_PHY_DX8SL0OSC_RESERVED_12_11_SHIFT #undef DDR_PHY_DX8SL0OSC_RESERVED_12_11_MASK -#define DDR_PHY_DX8SL0OSC_RESERVED_12_11_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL0OSC_RESERVED_12_11_SHIFT 11 -#define DDR_PHY_DX8SL0OSC_RESERVED_12_11_MASK 0x00001800U +#define DDR_PHY_DX8SL0OSC_RESERVED_12_11_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_RESERVED_12_11_SHIFT 11 +#define DDR_PHY_DX8SL0OSC_RESERVED_12_11_MASK 0x00001800U -/*Oscillator Mode Write-Data Delay Line Select*/ +/* +* Oscillator Mode Write-Data Delay Line Select +*/ #undef DDR_PHY_DX8SL0OSC_OSCWDDL_DEFVAL #undef DDR_PHY_DX8SL0OSC_OSCWDDL_SHIFT #undef DDR_PHY_DX8SL0OSC_OSCWDDL_MASK -#define DDR_PHY_DX8SL0OSC_OSCWDDL_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL0OSC_OSCWDDL_SHIFT 9 -#define DDR_PHY_DX8SL0OSC_OSCWDDL_MASK 0x00000600U +#define DDR_PHY_DX8SL0OSC_OSCWDDL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_OSCWDDL_SHIFT 9 +#define DDR_PHY_DX8SL0OSC_OSCWDDL_MASK 0x00000600U -/*Reserved. Caution, do not write to this register field.*/ +/* +* Reserved. Caution, do not write to this register field. +*/ #undef DDR_PHY_DX8SL0OSC_RESERVED_8_7_DEFVAL #undef DDR_PHY_DX8SL0OSC_RESERVED_8_7_SHIFT #undef DDR_PHY_DX8SL0OSC_RESERVED_8_7_MASK -#define DDR_PHY_DX8SL0OSC_RESERVED_8_7_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL0OSC_RESERVED_8_7_SHIFT 7 -#define DDR_PHY_DX8SL0OSC_RESERVED_8_7_MASK 0x00000180U +#define DDR_PHY_DX8SL0OSC_RESERVED_8_7_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_RESERVED_8_7_SHIFT 7 +#define DDR_PHY_DX8SL0OSC_RESERVED_8_7_MASK 0x00000180U -/*Oscillator Mode Write-Leveling Delay Line Select*/ +/* +* Oscillator Mode Write-Leveling Delay Line Select +*/ #undef DDR_PHY_DX8SL0OSC_OSCWDL_DEFVAL #undef DDR_PHY_DX8SL0OSC_OSCWDL_SHIFT #undef DDR_PHY_DX8SL0OSC_OSCWDL_MASK -#define DDR_PHY_DX8SL0OSC_OSCWDL_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL0OSC_OSCWDL_SHIFT 5 -#define DDR_PHY_DX8SL0OSC_OSCWDL_MASK 0x00000060U +#define DDR_PHY_DX8SL0OSC_OSCWDL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_OSCWDL_SHIFT 5 +#define DDR_PHY_DX8SL0OSC_OSCWDL_MASK 0x00000060U -/*Oscillator Mode Division*/ +/* +* Oscillator Mode Division +*/ #undef DDR_PHY_DX8SL0OSC_OSCDIV_DEFVAL #undef DDR_PHY_DX8SL0OSC_OSCDIV_SHIFT #undef DDR_PHY_DX8SL0OSC_OSCDIV_MASK -#define DDR_PHY_DX8SL0OSC_OSCDIV_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL0OSC_OSCDIV_SHIFT 1 -#define DDR_PHY_DX8SL0OSC_OSCDIV_MASK 0x0000001EU +#define DDR_PHY_DX8SL0OSC_OSCDIV_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_OSCDIV_SHIFT 1 +#define DDR_PHY_DX8SL0OSC_OSCDIV_MASK 0x0000001EU -/*Oscillator Enable*/ +/* +* Oscillator Enable +*/ #undef DDR_PHY_DX8SL0OSC_OSCEN_DEFVAL #undef DDR_PHY_DX8SL0OSC_OSCEN_SHIFT #undef DDR_PHY_DX8SL0OSC_OSCEN_MASK -#define DDR_PHY_DX8SL0OSC_OSCEN_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL0OSC_OSCEN_SHIFT 0 -#define DDR_PHY_DX8SL0OSC_OSCEN_MASK 0x00000001U +#define DDR_PHY_DX8SL0OSC_OSCEN_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL0OSC_OSCEN_SHIFT 0 +#define DDR_PHY_DX8SL0OSC_OSCEN_MASK 0x00000001U -/*Reserved. Return zeroes on reads.*/ +/* +* PLL Bypass +*/ +#undef DDR_PHY_DX8SL0PLLCR0_PLLBYP_DEFVAL +#undef DDR_PHY_DX8SL0PLLCR0_PLLBYP_SHIFT +#undef DDR_PHY_DX8SL0PLLCR0_PLLBYP_MASK +#define DDR_PHY_DX8SL0PLLCR0_PLLBYP_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL0PLLCR0_PLLBYP_SHIFT 31 +#define DDR_PHY_DX8SL0PLLCR0_PLLBYP_MASK 0x80000000U + +/* +* PLL Reset +*/ +#undef DDR_PHY_DX8SL0PLLCR0_PLLRST_DEFVAL +#undef DDR_PHY_DX8SL0PLLCR0_PLLRST_SHIFT +#undef DDR_PHY_DX8SL0PLLCR0_PLLRST_MASK +#define DDR_PHY_DX8SL0PLLCR0_PLLRST_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL0PLLCR0_PLLRST_SHIFT 30 +#define DDR_PHY_DX8SL0PLLCR0_PLLRST_MASK 0x40000000U + +/* +* PLL Power Down +*/ +#undef DDR_PHY_DX8SL0PLLCR0_PLLPD_DEFVAL +#undef DDR_PHY_DX8SL0PLLCR0_PLLPD_SHIFT +#undef DDR_PHY_DX8SL0PLLCR0_PLLPD_MASK +#define DDR_PHY_DX8SL0PLLCR0_PLLPD_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL0PLLCR0_PLLPD_SHIFT 29 +#define DDR_PHY_DX8SL0PLLCR0_PLLPD_MASK 0x20000000U + +/* +* Reference Stop Mode +*/ +#undef DDR_PHY_DX8SL0PLLCR0_RSTOPM_DEFVAL +#undef DDR_PHY_DX8SL0PLLCR0_RSTOPM_SHIFT +#undef DDR_PHY_DX8SL0PLLCR0_RSTOPM_MASK +#define DDR_PHY_DX8SL0PLLCR0_RSTOPM_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL0PLLCR0_RSTOPM_SHIFT 28 +#define DDR_PHY_DX8SL0PLLCR0_RSTOPM_MASK 0x10000000U + +/* +* PLL Frequency Select +*/ +#undef DDR_PHY_DX8SL0PLLCR0_FRQSEL_DEFVAL +#undef DDR_PHY_DX8SL0PLLCR0_FRQSEL_SHIFT +#undef DDR_PHY_DX8SL0PLLCR0_FRQSEL_MASK +#define DDR_PHY_DX8SL0PLLCR0_FRQSEL_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL0PLLCR0_FRQSEL_SHIFT 24 +#define DDR_PHY_DX8SL0PLLCR0_FRQSEL_MASK 0x0F000000U + +/* +* Relock Mode +*/ +#undef DDR_PHY_DX8SL0PLLCR0_RLOCKM_DEFVAL +#undef DDR_PHY_DX8SL0PLLCR0_RLOCKM_SHIFT +#undef DDR_PHY_DX8SL0PLLCR0_RLOCKM_MASK +#define DDR_PHY_DX8SL0PLLCR0_RLOCKM_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL0PLLCR0_RLOCKM_SHIFT 23 +#define DDR_PHY_DX8SL0PLLCR0_RLOCKM_MASK 0x00800000U + +/* +* Charge Pump Proportional Current Control +*/ +#undef DDR_PHY_DX8SL0PLLCR0_CPPC_DEFVAL +#undef DDR_PHY_DX8SL0PLLCR0_CPPC_SHIFT +#undef DDR_PHY_DX8SL0PLLCR0_CPPC_MASK +#define DDR_PHY_DX8SL0PLLCR0_CPPC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL0PLLCR0_CPPC_SHIFT 17 +#define DDR_PHY_DX8SL0PLLCR0_CPPC_MASK 0x007E0000U + +/* +* Charge Pump Integrating Current Control +*/ +#undef DDR_PHY_DX8SL0PLLCR0_CPIC_DEFVAL +#undef DDR_PHY_DX8SL0PLLCR0_CPIC_SHIFT +#undef DDR_PHY_DX8SL0PLLCR0_CPIC_MASK +#define DDR_PHY_DX8SL0PLLCR0_CPIC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL0PLLCR0_CPIC_SHIFT 13 +#define DDR_PHY_DX8SL0PLLCR0_CPIC_MASK 0x0001E000U + +/* +* Gear Shift +*/ +#undef DDR_PHY_DX8SL0PLLCR0_GSHIFT_DEFVAL +#undef DDR_PHY_DX8SL0PLLCR0_GSHIFT_SHIFT +#undef DDR_PHY_DX8SL0PLLCR0_GSHIFT_MASK +#define DDR_PHY_DX8SL0PLLCR0_GSHIFT_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL0PLLCR0_GSHIFT_SHIFT 12 +#define DDR_PHY_DX8SL0PLLCR0_GSHIFT_MASK 0x00001000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL0PLLCR0_RESERVED_11_9_DEFVAL +#undef DDR_PHY_DX8SL0PLLCR0_RESERVED_11_9_SHIFT +#undef DDR_PHY_DX8SL0PLLCR0_RESERVED_11_9_MASK +#define DDR_PHY_DX8SL0PLLCR0_RESERVED_11_9_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL0PLLCR0_RESERVED_11_9_SHIFT 9 +#define DDR_PHY_DX8SL0PLLCR0_RESERVED_11_9_MASK 0x00000E00U + +/* +* Analog Test Enable (ATOEN) +*/ +#undef DDR_PHY_DX8SL0PLLCR0_ATOEN_DEFVAL +#undef DDR_PHY_DX8SL0PLLCR0_ATOEN_SHIFT +#undef DDR_PHY_DX8SL0PLLCR0_ATOEN_MASK +#define DDR_PHY_DX8SL0PLLCR0_ATOEN_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL0PLLCR0_ATOEN_SHIFT 8 +#define DDR_PHY_DX8SL0PLLCR0_ATOEN_MASK 0x00000100U + +/* +* Analog Test Control +*/ +#undef DDR_PHY_DX8SL0PLLCR0_ATC_DEFVAL +#undef DDR_PHY_DX8SL0PLLCR0_ATC_SHIFT +#undef DDR_PHY_DX8SL0PLLCR0_ATC_MASK +#define DDR_PHY_DX8SL0PLLCR0_ATC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL0PLLCR0_ATC_SHIFT 4 +#define DDR_PHY_DX8SL0PLLCR0_ATC_MASK 0x000000F0U + +/* +* Digital Test Control +*/ +#undef DDR_PHY_DX8SL0PLLCR0_DTC_DEFVAL +#undef DDR_PHY_DX8SL0PLLCR0_DTC_SHIFT +#undef DDR_PHY_DX8SL0PLLCR0_DTC_MASK +#define DDR_PHY_DX8SL0PLLCR0_DTC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL0PLLCR0_DTC_SHIFT 0 +#define DDR_PHY_DX8SL0PLLCR0_DTC_MASK 0x0000000FU + +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_DEFVAL #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_SHIFT #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_MASK -#define DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_SHIFT 25 -#define DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_MASK 0xFE000000U +#define DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_SHIFT 25 +#define DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_MASK 0xFE000000U -/*Read Path Rise-to-Rise Mode*/ +/* +* Read Path Rise-to-Rise Mode +*/ #undef DDR_PHY_DX8SL0DQSCTL_RRRMODE_DEFVAL #undef DDR_PHY_DX8SL0DQSCTL_RRRMODE_SHIFT #undef DDR_PHY_DX8SL0DQSCTL_RRRMODE_MASK -#define DDR_PHY_DX8SL0DQSCTL_RRRMODE_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL0DQSCTL_RRRMODE_SHIFT 24 -#define DDR_PHY_DX8SL0DQSCTL_RRRMODE_MASK 0x01000000U +#define DDR_PHY_DX8SL0DQSCTL_RRRMODE_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL0DQSCTL_RRRMODE_SHIFT 24 +#define DDR_PHY_DX8SL0DQSCTL_RRRMODE_MASK 0x01000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_DEFVAL #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_SHIFT #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_MASK -#define DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_SHIFT 22 -#define DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_MASK 0x00C00000U +#define DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_MASK 0x00C00000U -/*Write Path Rise-to-Rise Mode*/ +/* +* Write Path Rise-to-Rise Mode +*/ #undef DDR_PHY_DX8SL0DQSCTL_WRRMODE_DEFVAL #undef DDR_PHY_DX8SL0DQSCTL_WRRMODE_SHIFT #undef DDR_PHY_DX8SL0DQSCTL_WRRMODE_MASK -#define DDR_PHY_DX8SL0DQSCTL_WRRMODE_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL0DQSCTL_WRRMODE_SHIFT 21 -#define DDR_PHY_DX8SL0DQSCTL_WRRMODE_MASK 0x00200000U +#define DDR_PHY_DX8SL0DQSCTL_WRRMODE_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL0DQSCTL_WRRMODE_SHIFT 21 +#define DDR_PHY_DX8SL0DQSCTL_WRRMODE_MASK 0x00200000U -/*DQS Gate Extension*/ +/* +* DQS Gate Extension +*/ #undef DDR_PHY_DX8SL0DQSCTL_DQSGX_DEFVAL #undef DDR_PHY_DX8SL0DQSCTL_DQSGX_SHIFT #undef DDR_PHY_DX8SL0DQSCTL_DQSGX_MASK -#define DDR_PHY_DX8SL0DQSCTL_DQSGX_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL0DQSCTL_DQSGX_SHIFT 19 -#define DDR_PHY_DX8SL0DQSCTL_DQSGX_MASK 0x00180000U +#define DDR_PHY_DX8SL0DQSCTL_DQSGX_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL0DQSCTL_DQSGX_SHIFT 19 +#define DDR_PHY_DX8SL0DQSCTL_DQSGX_MASK 0x00180000U -/*Low Power PLL Power Down*/ +/* +* Low Power PLL Power Down +*/ #undef DDR_PHY_DX8SL0DQSCTL_LPPLLPD_DEFVAL #undef DDR_PHY_DX8SL0DQSCTL_LPPLLPD_SHIFT #undef DDR_PHY_DX8SL0DQSCTL_LPPLLPD_MASK -#define DDR_PHY_DX8SL0DQSCTL_LPPLLPD_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL0DQSCTL_LPPLLPD_SHIFT 18 -#define DDR_PHY_DX8SL0DQSCTL_LPPLLPD_MASK 0x00040000U +#define DDR_PHY_DX8SL0DQSCTL_LPPLLPD_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL0DQSCTL_LPPLLPD_SHIFT 18 +#define DDR_PHY_DX8SL0DQSCTL_LPPLLPD_MASK 0x00040000U -/*Low Power I/O Power Down*/ +/* +* Low Power I/O Power Down +*/ #undef DDR_PHY_DX8SL0DQSCTL_LPIOPD_DEFVAL #undef DDR_PHY_DX8SL0DQSCTL_LPIOPD_SHIFT #undef DDR_PHY_DX8SL0DQSCTL_LPIOPD_MASK -#define DDR_PHY_DX8SL0DQSCTL_LPIOPD_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL0DQSCTL_LPIOPD_SHIFT 17 -#define DDR_PHY_DX8SL0DQSCTL_LPIOPD_MASK 0x00020000U +#define DDR_PHY_DX8SL0DQSCTL_LPIOPD_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL0DQSCTL_LPIOPD_SHIFT 17 +#define DDR_PHY_DX8SL0DQSCTL_LPIOPD_MASK 0x00020000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_DEFVAL #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_SHIFT #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_MASK -#define DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_SHIFT 15 -#define DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_MASK 0x00018000U +#define DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_SHIFT 15 +#define DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_MASK 0x00018000U -/*QS Counter Enable*/ +/* +* QS Counter Enable +*/ #undef DDR_PHY_DX8SL0DQSCTL_QSCNTEN_DEFVAL #undef DDR_PHY_DX8SL0DQSCTL_QSCNTEN_SHIFT #undef DDR_PHY_DX8SL0DQSCTL_QSCNTEN_MASK -#define DDR_PHY_DX8SL0DQSCTL_QSCNTEN_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL0DQSCTL_QSCNTEN_SHIFT 14 -#define DDR_PHY_DX8SL0DQSCTL_QSCNTEN_MASK 0x00004000U +#define DDR_PHY_DX8SL0DQSCTL_QSCNTEN_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL0DQSCTL_QSCNTEN_SHIFT 14 +#define DDR_PHY_DX8SL0DQSCTL_QSCNTEN_MASK 0x00004000U -/*Unused DQ I/O Mode*/ +/* +* Unused DQ I/O Mode +*/ #undef DDR_PHY_DX8SL0DQSCTL_UDQIOM_DEFVAL #undef DDR_PHY_DX8SL0DQSCTL_UDQIOM_SHIFT #undef DDR_PHY_DX8SL0DQSCTL_UDQIOM_MASK -#define DDR_PHY_DX8SL0DQSCTL_UDQIOM_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL0DQSCTL_UDQIOM_SHIFT 13 -#define DDR_PHY_DX8SL0DQSCTL_UDQIOM_MASK 0x00002000U +#define DDR_PHY_DX8SL0DQSCTL_UDQIOM_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL0DQSCTL_UDQIOM_SHIFT 13 +#define DDR_PHY_DX8SL0DQSCTL_UDQIOM_MASK 0x00002000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_DEFVAL #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_SHIFT #undef DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_MASK -#define DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_SHIFT 10 -#define DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_MASK 0x00001C00U +#define DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_SHIFT 10 +#define DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_MASK 0x00001C00U -/*Data Slew Rate*/ +/* +* Data Slew Rate +*/ #undef DDR_PHY_DX8SL0DQSCTL_DXSR_DEFVAL #undef DDR_PHY_DX8SL0DQSCTL_DXSR_SHIFT #undef DDR_PHY_DX8SL0DQSCTL_DXSR_MASK -#define DDR_PHY_DX8SL0DQSCTL_DXSR_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL0DQSCTL_DXSR_SHIFT 8 -#define DDR_PHY_DX8SL0DQSCTL_DXSR_MASK 0x00000300U +#define DDR_PHY_DX8SL0DQSCTL_DXSR_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL0DQSCTL_DXSR_SHIFT 8 +#define DDR_PHY_DX8SL0DQSCTL_DXSR_MASK 0x00000300U -/*DQS_N Resistor*/ +/* +* DQS_N Resistor +*/ #undef DDR_PHY_DX8SL0DQSCTL_DQSNRES_DEFVAL #undef DDR_PHY_DX8SL0DQSCTL_DQSNRES_SHIFT #undef DDR_PHY_DX8SL0DQSCTL_DQSNRES_MASK -#define DDR_PHY_DX8SL0DQSCTL_DQSNRES_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL0DQSCTL_DQSNRES_SHIFT 4 -#define DDR_PHY_DX8SL0DQSCTL_DQSNRES_MASK 0x000000F0U +#define DDR_PHY_DX8SL0DQSCTL_DQSNRES_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL0DQSCTL_DQSNRES_SHIFT 4 +#define DDR_PHY_DX8SL0DQSCTL_DQSNRES_MASK 0x000000F0U -/*DQS Resistor*/ +/* +* DQS Resistor +*/ #undef DDR_PHY_DX8SL0DQSCTL_DQSRES_DEFVAL #undef DDR_PHY_DX8SL0DQSCTL_DQSRES_SHIFT #undef DDR_PHY_DX8SL0DQSCTL_DQSRES_MASK -#define DDR_PHY_DX8SL0DQSCTL_DQSRES_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL0DQSCTL_DQSRES_SHIFT 0 -#define DDR_PHY_DX8SL0DQSCTL_DQSRES_MASK 0x0000000FU +#define DDR_PHY_DX8SL0DQSCTL_DQSRES_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL0DQSCTL_DQSRES_SHIFT 0 +#define DDR_PHY_DX8SL0DQSCTL_DQSRES_MASK 0x0000000FU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_DEFVAL #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_SHIFT #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_MASK -#define DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_SHIFT 24 -#define DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_MASK 0xFF000000U +#define DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_SHIFT 24 +#define DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_MASK 0xFF000000U -/*Configurable Read Data Enable*/ +/* +* Configurable Read Data Enable +*/ #undef DDR_PHY_DX8SL0DXCTL2_CRDEN_DEFVAL #undef DDR_PHY_DX8SL0DXCTL2_CRDEN_SHIFT #undef DDR_PHY_DX8SL0DXCTL2_CRDEN_MASK -#define DDR_PHY_DX8SL0DXCTL2_CRDEN_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL0DXCTL2_CRDEN_SHIFT 23 -#define DDR_PHY_DX8SL0DXCTL2_CRDEN_MASK 0x00800000U +#define DDR_PHY_DX8SL0DXCTL2_CRDEN_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_CRDEN_SHIFT 23 +#define DDR_PHY_DX8SL0DXCTL2_CRDEN_MASK 0x00800000U -/*OX Extension during Post-amble*/ +/* +* OX Extension during Post-amble +*/ #undef DDR_PHY_DX8SL0DXCTL2_POSOEX_DEFVAL #undef DDR_PHY_DX8SL0DXCTL2_POSOEX_SHIFT #undef DDR_PHY_DX8SL0DXCTL2_POSOEX_MASK -#define DDR_PHY_DX8SL0DXCTL2_POSOEX_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL0DXCTL2_POSOEX_SHIFT 20 -#define DDR_PHY_DX8SL0DXCTL2_POSOEX_MASK 0x00700000U +#define DDR_PHY_DX8SL0DXCTL2_POSOEX_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_POSOEX_SHIFT 20 +#define DDR_PHY_DX8SL0DXCTL2_POSOEX_MASK 0x00700000U -/*OE Extension during Pre-amble*/ +/* +* OE Extension during Pre-amble +*/ #undef DDR_PHY_DX8SL0DXCTL2_PREOEX_DEFVAL #undef DDR_PHY_DX8SL0DXCTL2_PREOEX_SHIFT #undef DDR_PHY_DX8SL0DXCTL2_PREOEX_MASK -#define DDR_PHY_DX8SL0DXCTL2_PREOEX_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL0DXCTL2_PREOEX_SHIFT 18 -#define DDR_PHY_DX8SL0DXCTL2_PREOEX_MASK 0x000C0000U +#define DDR_PHY_DX8SL0DXCTL2_PREOEX_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_PREOEX_SHIFT 18 +#define DDR_PHY_DX8SL0DXCTL2_PREOEX_MASK 0x000C0000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_17_DEFVAL #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_17_SHIFT #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_17_MASK -#define DDR_PHY_DX8SL0DXCTL2_RESERVED_17_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL0DXCTL2_RESERVED_17_SHIFT 17 -#define DDR_PHY_DX8SL0DXCTL2_RESERVED_17_MASK 0x00020000U +#define DDR_PHY_DX8SL0DXCTL2_RESERVED_17_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_RESERVED_17_SHIFT 17 +#define DDR_PHY_DX8SL0DXCTL2_RESERVED_17_MASK 0x00020000U -/*I/O Assisted Gate Select*/ +/* +* I/O Assisted Gate Select +*/ #undef DDR_PHY_DX8SL0DXCTL2_IOAG_DEFVAL #undef DDR_PHY_DX8SL0DXCTL2_IOAG_SHIFT #undef DDR_PHY_DX8SL0DXCTL2_IOAG_MASK -#define DDR_PHY_DX8SL0DXCTL2_IOAG_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL0DXCTL2_IOAG_SHIFT 16 -#define DDR_PHY_DX8SL0DXCTL2_IOAG_MASK 0x00010000U +#define DDR_PHY_DX8SL0DXCTL2_IOAG_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_IOAG_SHIFT 16 +#define DDR_PHY_DX8SL0DXCTL2_IOAG_MASK 0x00010000U -/*I/O Loopback Select*/ +/* +* I/O Loopback Select +*/ #undef DDR_PHY_DX8SL0DXCTL2_IOLB_DEFVAL #undef DDR_PHY_DX8SL0DXCTL2_IOLB_SHIFT #undef DDR_PHY_DX8SL0DXCTL2_IOLB_MASK -#define DDR_PHY_DX8SL0DXCTL2_IOLB_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL0DXCTL2_IOLB_SHIFT 15 -#define DDR_PHY_DX8SL0DXCTL2_IOLB_MASK 0x00008000U +#define DDR_PHY_DX8SL0DXCTL2_IOLB_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_IOLB_SHIFT 15 +#define DDR_PHY_DX8SL0DXCTL2_IOLB_MASK 0x00008000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_DEFVAL #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_SHIFT #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_MASK -#define DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_SHIFT 13 -#define DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_MASK 0x00006000U +#define DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_SHIFT 13 +#define DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_MASK 0x00006000U -/*Low Power Wakeup Threshold*/ +/* +* Low Power Wakeup Threshold +*/ #undef DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_DEFVAL #undef DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_SHIFT #undef DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_MASK -#define DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_SHIFT 9 -#define DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_MASK 0x00001E00U +#define DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_SHIFT 9 +#define DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_MASK 0x00001E00U -/*Read Data Bus Inversion Enable*/ +/* +* Read Data Bus Inversion Enable +*/ #undef DDR_PHY_DX8SL0DXCTL2_RDBI_DEFVAL #undef DDR_PHY_DX8SL0DXCTL2_RDBI_SHIFT #undef DDR_PHY_DX8SL0DXCTL2_RDBI_MASK -#define DDR_PHY_DX8SL0DXCTL2_RDBI_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL0DXCTL2_RDBI_SHIFT 8 -#define DDR_PHY_DX8SL0DXCTL2_RDBI_MASK 0x00000100U +#define DDR_PHY_DX8SL0DXCTL2_RDBI_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_RDBI_SHIFT 8 +#define DDR_PHY_DX8SL0DXCTL2_RDBI_MASK 0x00000100U -/*Write Data Bus Inversion Enable*/ +/* +* Write Data Bus Inversion Enable +*/ #undef DDR_PHY_DX8SL0DXCTL2_WDBI_DEFVAL #undef DDR_PHY_DX8SL0DXCTL2_WDBI_SHIFT #undef DDR_PHY_DX8SL0DXCTL2_WDBI_MASK -#define DDR_PHY_DX8SL0DXCTL2_WDBI_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL0DXCTL2_WDBI_SHIFT 7 -#define DDR_PHY_DX8SL0DXCTL2_WDBI_MASK 0x00000080U +#define DDR_PHY_DX8SL0DXCTL2_WDBI_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_WDBI_SHIFT 7 +#define DDR_PHY_DX8SL0DXCTL2_WDBI_MASK 0x00000080U -/*PUB Read FIFO Bypass*/ +/* +* PUB Read FIFO Bypass +*/ #undef DDR_PHY_DX8SL0DXCTL2_PRFBYP_DEFVAL #undef DDR_PHY_DX8SL0DXCTL2_PRFBYP_SHIFT #undef DDR_PHY_DX8SL0DXCTL2_PRFBYP_MASK -#define DDR_PHY_DX8SL0DXCTL2_PRFBYP_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL0DXCTL2_PRFBYP_SHIFT 6 -#define DDR_PHY_DX8SL0DXCTL2_PRFBYP_MASK 0x00000040U +#define DDR_PHY_DX8SL0DXCTL2_PRFBYP_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_PRFBYP_SHIFT 6 +#define DDR_PHY_DX8SL0DXCTL2_PRFBYP_MASK 0x00000040U -/*DATX8 Receive FIFO Read Mode*/ +/* +* DATX8 Receive FIFO Read Mode +*/ #undef DDR_PHY_DX8SL0DXCTL2_RDMODE_DEFVAL #undef DDR_PHY_DX8SL0DXCTL2_RDMODE_SHIFT #undef DDR_PHY_DX8SL0DXCTL2_RDMODE_MASK -#define DDR_PHY_DX8SL0DXCTL2_RDMODE_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL0DXCTL2_RDMODE_SHIFT 4 -#define DDR_PHY_DX8SL0DXCTL2_RDMODE_MASK 0x00000030U +#define DDR_PHY_DX8SL0DXCTL2_RDMODE_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_RDMODE_SHIFT 4 +#define DDR_PHY_DX8SL0DXCTL2_RDMODE_MASK 0x00000030U -/*Disables the Read FIFO Reset*/ +/* +* Disables the Read FIFO Reset +*/ #undef DDR_PHY_DX8SL0DXCTL2_DISRST_DEFVAL #undef DDR_PHY_DX8SL0DXCTL2_DISRST_SHIFT #undef DDR_PHY_DX8SL0DXCTL2_DISRST_MASK -#define DDR_PHY_DX8SL0DXCTL2_DISRST_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL0DXCTL2_DISRST_SHIFT 3 -#define DDR_PHY_DX8SL0DXCTL2_DISRST_MASK 0x00000008U +#define DDR_PHY_DX8SL0DXCTL2_DISRST_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_DISRST_SHIFT 3 +#define DDR_PHY_DX8SL0DXCTL2_DISRST_MASK 0x00000008U -/*Read DQS Gate I/O Loopback*/ +/* +* Read DQS Gate I/O Loopback +*/ #undef DDR_PHY_DX8SL0DXCTL2_DQSGLB_DEFVAL #undef DDR_PHY_DX8SL0DXCTL2_DQSGLB_SHIFT #undef DDR_PHY_DX8SL0DXCTL2_DQSGLB_MASK -#define DDR_PHY_DX8SL0DXCTL2_DQSGLB_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL0DXCTL2_DQSGLB_SHIFT 1 -#define DDR_PHY_DX8SL0DXCTL2_DQSGLB_MASK 0x00000006U +#define DDR_PHY_DX8SL0DXCTL2_DQSGLB_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_DQSGLB_SHIFT 1 +#define DDR_PHY_DX8SL0DXCTL2_DQSGLB_MASK 0x00000006U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_0_DEFVAL #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_0_SHIFT #undef DDR_PHY_DX8SL0DXCTL2_RESERVED_0_MASK -#define DDR_PHY_DX8SL0DXCTL2_RESERVED_0_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL0DXCTL2_RESERVED_0_SHIFT 0 -#define DDR_PHY_DX8SL0DXCTL2_RESERVED_0_MASK 0x00000001U +#define DDR_PHY_DX8SL0DXCTL2_RESERVED_0_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL0DXCTL2_RESERVED_0_SHIFT 0 +#define DDR_PHY_DX8SL0DXCTL2_RESERVED_0_MASK 0x00000001U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL0IOCR_RESERVED_31_DEFVAL #undef DDR_PHY_DX8SL0IOCR_RESERVED_31_SHIFT #undef DDR_PHY_DX8SL0IOCR_RESERVED_31_MASK -#define DDR_PHY_DX8SL0IOCR_RESERVED_31_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL0IOCR_RESERVED_31_SHIFT 31 -#define DDR_PHY_DX8SL0IOCR_RESERVED_31_MASK 0x80000000U +#define DDR_PHY_DX8SL0IOCR_RESERVED_31_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL0IOCR_RESERVED_31_SHIFT 31 +#define DDR_PHY_DX8SL0IOCR_RESERVED_31_MASK 0x80000000U -/*PVREF_DAC REFSEL range select*/ +/* +* PVREF_DAC REFSEL range select +*/ #undef DDR_PHY_DX8SL0IOCR_DXDACRANGE_DEFVAL #undef DDR_PHY_DX8SL0IOCR_DXDACRANGE_SHIFT #undef DDR_PHY_DX8SL0IOCR_DXDACRANGE_MASK -#define DDR_PHY_DX8SL0IOCR_DXDACRANGE_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL0IOCR_DXDACRANGE_SHIFT 28 -#define DDR_PHY_DX8SL0IOCR_DXDACRANGE_MASK 0x70000000U +#define DDR_PHY_DX8SL0IOCR_DXDACRANGE_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL0IOCR_DXDACRANGE_SHIFT 28 +#define DDR_PHY_DX8SL0IOCR_DXDACRANGE_MASK 0x70000000U -/*IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring*/ +/* +* IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring +*/ #undef DDR_PHY_DX8SL0IOCR_DXVREFIOM_DEFVAL #undef DDR_PHY_DX8SL0IOCR_DXVREFIOM_SHIFT #undef DDR_PHY_DX8SL0IOCR_DXVREFIOM_MASK -#define DDR_PHY_DX8SL0IOCR_DXVREFIOM_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL0IOCR_DXVREFIOM_SHIFT 25 -#define DDR_PHY_DX8SL0IOCR_DXVREFIOM_MASK 0x0E000000U +#define DDR_PHY_DX8SL0IOCR_DXVREFIOM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL0IOCR_DXVREFIOM_SHIFT 25 +#define DDR_PHY_DX8SL0IOCR_DXVREFIOM_MASK 0x0E000000U -/*DX IO Mode*/ +/* +* DX IO Mode +*/ #undef DDR_PHY_DX8SL0IOCR_DXIOM_DEFVAL #undef DDR_PHY_DX8SL0IOCR_DXIOM_SHIFT #undef DDR_PHY_DX8SL0IOCR_DXIOM_MASK -#define DDR_PHY_DX8SL0IOCR_DXIOM_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL0IOCR_DXIOM_SHIFT 22 -#define DDR_PHY_DX8SL0IOCR_DXIOM_MASK 0x01C00000U +#define DDR_PHY_DX8SL0IOCR_DXIOM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL0IOCR_DXIOM_SHIFT 22 +#define DDR_PHY_DX8SL0IOCR_DXIOM_MASK 0x01C00000U -/*DX IO Transmitter Mode*/ +/* +* DX IO Transmitter Mode +*/ #undef DDR_PHY_DX8SL0IOCR_DXTXM_DEFVAL #undef DDR_PHY_DX8SL0IOCR_DXTXM_SHIFT #undef DDR_PHY_DX8SL0IOCR_DXTXM_MASK -#define DDR_PHY_DX8SL0IOCR_DXTXM_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL0IOCR_DXTXM_SHIFT 11 -#define DDR_PHY_DX8SL0IOCR_DXTXM_MASK 0x003FF800U +#define DDR_PHY_DX8SL0IOCR_DXTXM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL0IOCR_DXTXM_SHIFT 11 +#define DDR_PHY_DX8SL0IOCR_DXTXM_MASK 0x003FF800U -/*DX IO Receiver Mode*/ +/* +* DX IO Receiver Mode +*/ #undef DDR_PHY_DX8SL0IOCR_DXRXM_DEFVAL #undef DDR_PHY_DX8SL0IOCR_DXRXM_SHIFT #undef DDR_PHY_DX8SL0IOCR_DXRXM_MASK -#define DDR_PHY_DX8SL0IOCR_DXRXM_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL0IOCR_DXRXM_SHIFT 0 -#define DDR_PHY_DX8SL0IOCR_DXRXM_MASK 0x000007FFU +#define DDR_PHY_DX8SL0IOCR_DXRXM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL0IOCR_DXRXM_SHIFT 0 +#define DDR_PHY_DX8SL0IOCR_DXRXM_MASK 0x000007FFU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL1OSC_RESERVED_31_30_DEFVAL #undef DDR_PHY_DX8SL1OSC_RESERVED_31_30_SHIFT #undef DDR_PHY_DX8SL1OSC_RESERVED_31_30_MASK -#define DDR_PHY_DX8SL1OSC_RESERVED_31_30_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL1OSC_RESERVED_31_30_SHIFT 30 -#define DDR_PHY_DX8SL1OSC_RESERVED_31_30_MASK 0xC0000000U +#define DDR_PHY_DX8SL1OSC_RESERVED_31_30_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX8SL1OSC_RESERVED_31_30_MASK 0xC0000000U -/*Enable Clock Gating for DX ddr_clk*/ +/* +* Enable Clock Gating for DX ddr_clk +*/ #undef DDR_PHY_DX8SL1OSC_GATEDXRDCLK_DEFVAL #undef DDR_PHY_DX8SL1OSC_GATEDXRDCLK_SHIFT #undef DDR_PHY_DX8SL1OSC_GATEDXRDCLK_MASK -#define DDR_PHY_DX8SL1OSC_GATEDXRDCLK_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL1OSC_GATEDXRDCLK_SHIFT 28 -#define DDR_PHY_DX8SL1OSC_GATEDXRDCLK_MASK 0x30000000U +#define DDR_PHY_DX8SL1OSC_GATEDXRDCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_GATEDXRDCLK_SHIFT 28 +#define DDR_PHY_DX8SL1OSC_GATEDXRDCLK_MASK 0x30000000U -/*Enable Clock Gating for DX ctl_rd_clk*/ +/* +* Enable Clock Gating for DX ctl_rd_clk +*/ #undef DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_DEFVAL #undef DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_SHIFT #undef DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_MASK -#define DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_SHIFT 26 -#define DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_MASK 0x0C000000U +#define DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_SHIFT 26 +#define DDR_PHY_DX8SL1OSC_GATEDXDDRCLK_MASK 0x0C000000U -/*Enable Clock Gating for DX ctl_clk*/ +/* +* Enable Clock Gating for DX ctl_clk +*/ #undef DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_DEFVAL #undef DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_SHIFT #undef DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_MASK -#define DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_SHIFT 24 -#define DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_MASK 0x03000000U +#define DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_SHIFT 24 +#define DDR_PHY_DX8SL1OSC_GATEDXCTLCLK_MASK 0x03000000U -/*Selects the level to which clocks will be stalled when clock gating is enabled.*/ +/* +* Selects the level to which clocks will be stalled when clock gating is e + * nabled. +*/ #undef DDR_PHY_DX8SL1OSC_CLKLEVEL_DEFVAL #undef DDR_PHY_DX8SL1OSC_CLKLEVEL_SHIFT #undef DDR_PHY_DX8SL1OSC_CLKLEVEL_MASK -#define DDR_PHY_DX8SL1OSC_CLKLEVEL_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL1OSC_CLKLEVEL_SHIFT 22 -#define DDR_PHY_DX8SL1OSC_CLKLEVEL_MASK 0x00C00000U +#define DDR_PHY_DX8SL1OSC_CLKLEVEL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_CLKLEVEL_SHIFT 22 +#define DDR_PHY_DX8SL1OSC_CLKLEVEL_MASK 0x00C00000U -/*Loopback Mode*/ +/* +* Loopback Mode +*/ #undef DDR_PHY_DX8SL1OSC_LBMODE_DEFVAL #undef DDR_PHY_DX8SL1OSC_LBMODE_SHIFT #undef DDR_PHY_DX8SL1OSC_LBMODE_MASK -#define DDR_PHY_DX8SL1OSC_LBMODE_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL1OSC_LBMODE_SHIFT 21 -#define DDR_PHY_DX8SL1OSC_LBMODE_MASK 0x00200000U +#define DDR_PHY_DX8SL1OSC_LBMODE_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_LBMODE_SHIFT 21 +#define DDR_PHY_DX8SL1OSC_LBMODE_MASK 0x00200000U -/*Load GSDQS LCDL with 2x the calibrated GSDQSPRD value*/ +/* +* Load GSDQS LCDL with 2x the calibrated GSDQSPRD value +*/ #undef DDR_PHY_DX8SL1OSC_LBGSDQS_DEFVAL #undef DDR_PHY_DX8SL1OSC_LBGSDQS_SHIFT #undef DDR_PHY_DX8SL1OSC_LBGSDQS_MASK -#define DDR_PHY_DX8SL1OSC_LBGSDQS_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL1OSC_LBGSDQS_SHIFT 20 -#define DDR_PHY_DX8SL1OSC_LBGSDQS_MASK 0x00100000U +#define DDR_PHY_DX8SL1OSC_LBGSDQS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_LBGSDQS_SHIFT 20 +#define DDR_PHY_DX8SL1OSC_LBGSDQS_MASK 0x00100000U -/*Loopback DQS Gating*/ +/* +* Loopback DQS Gating +*/ #undef DDR_PHY_DX8SL1OSC_LBGDQS_DEFVAL #undef DDR_PHY_DX8SL1OSC_LBGDQS_SHIFT #undef DDR_PHY_DX8SL1OSC_LBGDQS_MASK -#define DDR_PHY_DX8SL1OSC_LBGDQS_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL1OSC_LBGDQS_SHIFT 18 -#define DDR_PHY_DX8SL1OSC_LBGDQS_MASK 0x000C0000U +#define DDR_PHY_DX8SL1OSC_LBGDQS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_LBGDQS_SHIFT 18 +#define DDR_PHY_DX8SL1OSC_LBGDQS_MASK 0x000C0000U -/*Loopback DQS Shift*/ +/* +* Loopback DQS Shift +*/ #undef DDR_PHY_DX8SL1OSC_LBDQSS_DEFVAL #undef DDR_PHY_DX8SL1OSC_LBDQSS_SHIFT #undef DDR_PHY_DX8SL1OSC_LBDQSS_MASK -#define DDR_PHY_DX8SL1OSC_LBDQSS_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL1OSC_LBDQSS_SHIFT 17 -#define DDR_PHY_DX8SL1OSC_LBDQSS_MASK 0x00020000U +#define DDR_PHY_DX8SL1OSC_LBDQSS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_LBDQSS_SHIFT 17 +#define DDR_PHY_DX8SL1OSC_LBDQSS_MASK 0x00020000U -/*PHY High-Speed Reset*/ +/* +* PHY High-Speed Reset +*/ #undef DDR_PHY_DX8SL1OSC_PHYHRST_DEFVAL #undef DDR_PHY_DX8SL1OSC_PHYHRST_SHIFT #undef DDR_PHY_DX8SL1OSC_PHYHRST_MASK -#define DDR_PHY_DX8SL1OSC_PHYHRST_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL1OSC_PHYHRST_SHIFT 16 -#define DDR_PHY_DX8SL1OSC_PHYHRST_MASK 0x00010000U +#define DDR_PHY_DX8SL1OSC_PHYHRST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_PHYHRST_SHIFT 16 +#define DDR_PHY_DX8SL1OSC_PHYHRST_MASK 0x00010000U -/*PHY FIFO Reset*/ +/* +* PHY FIFO Reset +*/ #undef DDR_PHY_DX8SL1OSC_PHYFRST_DEFVAL #undef DDR_PHY_DX8SL1OSC_PHYFRST_SHIFT #undef DDR_PHY_DX8SL1OSC_PHYFRST_MASK -#define DDR_PHY_DX8SL1OSC_PHYFRST_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL1OSC_PHYFRST_SHIFT 15 -#define DDR_PHY_DX8SL1OSC_PHYFRST_MASK 0x00008000U +#define DDR_PHY_DX8SL1OSC_PHYFRST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_PHYFRST_SHIFT 15 +#define DDR_PHY_DX8SL1OSC_PHYFRST_MASK 0x00008000U -/*Delay Line Test Start*/ +/* +* Delay Line Test Start +*/ #undef DDR_PHY_DX8SL1OSC_DLTST_DEFVAL #undef DDR_PHY_DX8SL1OSC_DLTST_SHIFT #undef DDR_PHY_DX8SL1OSC_DLTST_MASK -#define DDR_PHY_DX8SL1OSC_DLTST_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL1OSC_DLTST_SHIFT 14 -#define DDR_PHY_DX8SL1OSC_DLTST_MASK 0x00004000U +#define DDR_PHY_DX8SL1OSC_DLTST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_DLTST_SHIFT 14 +#define DDR_PHY_DX8SL1OSC_DLTST_MASK 0x00004000U -/*Delay Line Test Mode*/ +/* +* Delay Line Test Mode +*/ #undef DDR_PHY_DX8SL1OSC_DLTMODE_DEFVAL #undef DDR_PHY_DX8SL1OSC_DLTMODE_SHIFT #undef DDR_PHY_DX8SL1OSC_DLTMODE_MASK -#define DDR_PHY_DX8SL1OSC_DLTMODE_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL1OSC_DLTMODE_SHIFT 13 -#define DDR_PHY_DX8SL1OSC_DLTMODE_MASK 0x00002000U +#define DDR_PHY_DX8SL1OSC_DLTMODE_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_DLTMODE_SHIFT 13 +#define DDR_PHY_DX8SL1OSC_DLTMODE_MASK 0x00002000U -/*Reserved. Caution, do not write to this register field.*/ +/* +* Reserved. Caution, do not write to this register field. +*/ #undef DDR_PHY_DX8SL1OSC_RESERVED_12_11_DEFVAL #undef DDR_PHY_DX8SL1OSC_RESERVED_12_11_SHIFT #undef DDR_PHY_DX8SL1OSC_RESERVED_12_11_MASK -#define DDR_PHY_DX8SL1OSC_RESERVED_12_11_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL1OSC_RESERVED_12_11_SHIFT 11 -#define DDR_PHY_DX8SL1OSC_RESERVED_12_11_MASK 0x00001800U +#define DDR_PHY_DX8SL1OSC_RESERVED_12_11_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_RESERVED_12_11_SHIFT 11 +#define DDR_PHY_DX8SL1OSC_RESERVED_12_11_MASK 0x00001800U -/*Oscillator Mode Write-Data Delay Line Select*/ +/* +* Oscillator Mode Write-Data Delay Line Select +*/ #undef DDR_PHY_DX8SL1OSC_OSCWDDL_DEFVAL #undef DDR_PHY_DX8SL1OSC_OSCWDDL_SHIFT #undef DDR_PHY_DX8SL1OSC_OSCWDDL_MASK -#define DDR_PHY_DX8SL1OSC_OSCWDDL_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL1OSC_OSCWDDL_SHIFT 9 -#define DDR_PHY_DX8SL1OSC_OSCWDDL_MASK 0x00000600U +#define DDR_PHY_DX8SL1OSC_OSCWDDL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_OSCWDDL_SHIFT 9 +#define DDR_PHY_DX8SL1OSC_OSCWDDL_MASK 0x00000600U -/*Reserved. Caution, do not write to this register field.*/ +/* +* Reserved. Caution, do not write to this register field. +*/ #undef DDR_PHY_DX8SL1OSC_RESERVED_8_7_DEFVAL #undef DDR_PHY_DX8SL1OSC_RESERVED_8_7_SHIFT #undef DDR_PHY_DX8SL1OSC_RESERVED_8_7_MASK -#define DDR_PHY_DX8SL1OSC_RESERVED_8_7_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL1OSC_RESERVED_8_7_SHIFT 7 -#define DDR_PHY_DX8SL1OSC_RESERVED_8_7_MASK 0x00000180U +#define DDR_PHY_DX8SL1OSC_RESERVED_8_7_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_RESERVED_8_7_SHIFT 7 +#define DDR_PHY_DX8SL1OSC_RESERVED_8_7_MASK 0x00000180U -/*Oscillator Mode Write-Leveling Delay Line Select*/ +/* +* Oscillator Mode Write-Leveling Delay Line Select +*/ #undef DDR_PHY_DX8SL1OSC_OSCWDL_DEFVAL #undef DDR_PHY_DX8SL1OSC_OSCWDL_SHIFT #undef DDR_PHY_DX8SL1OSC_OSCWDL_MASK -#define DDR_PHY_DX8SL1OSC_OSCWDL_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL1OSC_OSCWDL_SHIFT 5 -#define DDR_PHY_DX8SL1OSC_OSCWDL_MASK 0x00000060U +#define DDR_PHY_DX8SL1OSC_OSCWDL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_OSCWDL_SHIFT 5 +#define DDR_PHY_DX8SL1OSC_OSCWDL_MASK 0x00000060U -/*Oscillator Mode Division*/ +/* +* Oscillator Mode Division +*/ #undef DDR_PHY_DX8SL1OSC_OSCDIV_DEFVAL #undef DDR_PHY_DX8SL1OSC_OSCDIV_SHIFT #undef DDR_PHY_DX8SL1OSC_OSCDIV_MASK -#define DDR_PHY_DX8SL1OSC_OSCDIV_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL1OSC_OSCDIV_SHIFT 1 -#define DDR_PHY_DX8SL1OSC_OSCDIV_MASK 0x0000001EU +#define DDR_PHY_DX8SL1OSC_OSCDIV_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_OSCDIV_SHIFT 1 +#define DDR_PHY_DX8SL1OSC_OSCDIV_MASK 0x0000001EU -/*Oscillator Enable*/ +/* +* Oscillator Enable +*/ #undef DDR_PHY_DX8SL1OSC_OSCEN_DEFVAL #undef DDR_PHY_DX8SL1OSC_OSCEN_SHIFT #undef DDR_PHY_DX8SL1OSC_OSCEN_MASK -#define DDR_PHY_DX8SL1OSC_OSCEN_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL1OSC_OSCEN_SHIFT 0 -#define DDR_PHY_DX8SL1OSC_OSCEN_MASK 0x00000001U +#define DDR_PHY_DX8SL1OSC_OSCEN_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL1OSC_OSCEN_SHIFT 0 +#define DDR_PHY_DX8SL1OSC_OSCEN_MASK 0x00000001U -/*Reserved. Return zeroes on reads.*/ +/* +* PLL Bypass +*/ +#undef DDR_PHY_DX8SL1PLLCR0_PLLBYP_DEFVAL +#undef DDR_PHY_DX8SL1PLLCR0_PLLBYP_SHIFT +#undef DDR_PHY_DX8SL1PLLCR0_PLLBYP_MASK +#define DDR_PHY_DX8SL1PLLCR0_PLLBYP_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL1PLLCR0_PLLBYP_SHIFT 31 +#define DDR_PHY_DX8SL1PLLCR0_PLLBYP_MASK 0x80000000U + +/* +* PLL Reset +*/ +#undef DDR_PHY_DX8SL1PLLCR0_PLLRST_DEFVAL +#undef DDR_PHY_DX8SL1PLLCR0_PLLRST_SHIFT +#undef DDR_PHY_DX8SL1PLLCR0_PLLRST_MASK +#define DDR_PHY_DX8SL1PLLCR0_PLLRST_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL1PLLCR0_PLLRST_SHIFT 30 +#define DDR_PHY_DX8SL1PLLCR0_PLLRST_MASK 0x40000000U + +/* +* PLL Power Down +*/ +#undef DDR_PHY_DX8SL1PLLCR0_PLLPD_DEFVAL +#undef DDR_PHY_DX8SL1PLLCR0_PLLPD_SHIFT +#undef DDR_PHY_DX8SL1PLLCR0_PLLPD_MASK +#define DDR_PHY_DX8SL1PLLCR0_PLLPD_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL1PLLCR0_PLLPD_SHIFT 29 +#define DDR_PHY_DX8SL1PLLCR0_PLLPD_MASK 0x20000000U + +/* +* Reference Stop Mode +*/ +#undef DDR_PHY_DX8SL1PLLCR0_RSTOPM_DEFVAL +#undef DDR_PHY_DX8SL1PLLCR0_RSTOPM_SHIFT +#undef DDR_PHY_DX8SL1PLLCR0_RSTOPM_MASK +#define DDR_PHY_DX8SL1PLLCR0_RSTOPM_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL1PLLCR0_RSTOPM_SHIFT 28 +#define DDR_PHY_DX8SL1PLLCR0_RSTOPM_MASK 0x10000000U + +/* +* PLL Frequency Select +*/ +#undef DDR_PHY_DX8SL1PLLCR0_FRQSEL_DEFVAL +#undef DDR_PHY_DX8SL1PLLCR0_FRQSEL_SHIFT +#undef DDR_PHY_DX8SL1PLLCR0_FRQSEL_MASK +#define DDR_PHY_DX8SL1PLLCR0_FRQSEL_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL1PLLCR0_FRQSEL_SHIFT 24 +#define DDR_PHY_DX8SL1PLLCR0_FRQSEL_MASK 0x0F000000U + +/* +* Relock Mode +*/ +#undef DDR_PHY_DX8SL1PLLCR0_RLOCKM_DEFVAL +#undef DDR_PHY_DX8SL1PLLCR0_RLOCKM_SHIFT +#undef DDR_PHY_DX8SL1PLLCR0_RLOCKM_MASK +#define DDR_PHY_DX8SL1PLLCR0_RLOCKM_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL1PLLCR0_RLOCKM_SHIFT 23 +#define DDR_PHY_DX8SL1PLLCR0_RLOCKM_MASK 0x00800000U + +/* +* Charge Pump Proportional Current Control +*/ +#undef DDR_PHY_DX8SL1PLLCR0_CPPC_DEFVAL +#undef DDR_PHY_DX8SL1PLLCR0_CPPC_SHIFT +#undef DDR_PHY_DX8SL1PLLCR0_CPPC_MASK +#define DDR_PHY_DX8SL1PLLCR0_CPPC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL1PLLCR0_CPPC_SHIFT 17 +#define DDR_PHY_DX8SL1PLLCR0_CPPC_MASK 0x007E0000U + +/* +* Charge Pump Integrating Current Control +*/ +#undef DDR_PHY_DX8SL1PLLCR0_CPIC_DEFVAL +#undef DDR_PHY_DX8SL1PLLCR0_CPIC_SHIFT +#undef DDR_PHY_DX8SL1PLLCR0_CPIC_MASK +#define DDR_PHY_DX8SL1PLLCR0_CPIC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL1PLLCR0_CPIC_SHIFT 13 +#define DDR_PHY_DX8SL1PLLCR0_CPIC_MASK 0x0001E000U + +/* +* Gear Shift +*/ +#undef DDR_PHY_DX8SL1PLLCR0_GSHIFT_DEFVAL +#undef DDR_PHY_DX8SL1PLLCR0_GSHIFT_SHIFT +#undef DDR_PHY_DX8SL1PLLCR0_GSHIFT_MASK +#define DDR_PHY_DX8SL1PLLCR0_GSHIFT_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL1PLLCR0_GSHIFT_SHIFT 12 +#define DDR_PHY_DX8SL1PLLCR0_GSHIFT_MASK 0x00001000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL1PLLCR0_RESERVED_11_9_DEFVAL +#undef DDR_PHY_DX8SL1PLLCR0_RESERVED_11_9_SHIFT +#undef DDR_PHY_DX8SL1PLLCR0_RESERVED_11_9_MASK +#define DDR_PHY_DX8SL1PLLCR0_RESERVED_11_9_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL1PLLCR0_RESERVED_11_9_SHIFT 9 +#define DDR_PHY_DX8SL1PLLCR0_RESERVED_11_9_MASK 0x00000E00U + +/* +* Analog Test Enable (ATOEN) +*/ +#undef DDR_PHY_DX8SL1PLLCR0_ATOEN_DEFVAL +#undef DDR_PHY_DX8SL1PLLCR0_ATOEN_SHIFT +#undef DDR_PHY_DX8SL1PLLCR0_ATOEN_MASK +#define DDR_PHY_DX8SL1PLLCR0_ATOEN_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL1PLLCR0_ATOEN_SHIFT 8 +#define DDR_PHY_DX8SL1PLLCR0_ATOEN_MASK 0x00000100U + +/* +* Analog Test Control +*/ +#undef DDR_PHY_DX8SL1PLLCR0_ATC_DEFVAL +#undef DDR_PHY_DX8SL1PLLCR0_ATC_SHIFT +#undef DDR_PHY_DX8SL1PLLCR0_ATC_MASK +#define DDR_PHY_DX8SL1PLLCR0_ATC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL1PLLCR0_ATC_SHIFT 4 +#define DDR_PHY_DX8SL1PLLCR0_ATC_MASK 0x000000F0U + +/* +* Digital Test Control +*/ +#undef DDR_PHY_DX8SL1PLLCR0_DTC_DEFVAL +#undef DDR_PHY_DX8SL1PLLCR0_DTC_SHIFT +#undef DDR_PHY_DX8SL1PLLCR0_DTC_MASK +#define DDR_PHY_DX8SL1PLLCR0_DTC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL1PLLCR0_DTC_SHIFT 0 +#define DDR_PHY_DX8SL1PLLCR0_DTC_MASK 0x0000000FU + +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_DEFVAL #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_SHIFT #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_MASK -#define DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_SHIFT 25 -#define DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_MASK 0xFE000000U +#define DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_SHIFT 25 +#define DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_MASK 0xFE000000U -/*Read Path Rise-to-Rise Mode*/ +/* +* Read Path Rise-to-Rise Mode +*/ #undef DDR_PHY_DX8SL1DQSCTL_RRRMODE_DEFVAL #undef DDR_PHY_DX8SL1DQSCTL_RRRMODE_SHIFT #undef DDR_PHY_DX8SL1DQSCTL_RRRMODE_MASK -#define DDR_PHY_DX8SL1DQSCTL_RRRMODE_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL1DQSCTL_RRRMODE_SHIFT 24 -#define DDR_PHY_DX8SL1DQSCTL_RRRMODE_MASK 0x01000000U +#define DDR_PHY_DX8SL1DQSCTL_RRRMODE_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL1DQSCTL_RRRMODE_SHIFT 24 +#define DDR_PHY_DX8SL1DQSCTL_RRRMODE_MASK 0x01000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_DEFVAL #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_SHIFT #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_MASK -#define DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_SHIFT 22 -#define DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_MASK 0x00C00000U +#define DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_MASK 0x00C00000U -/*Write Path Rise-to-Rise Mode*/ +/* +* Write Path Rise-to-Rise Mode +*/ #undef DDR_PHY_DX8SL1DQSCTL_WRRMODE_DEFVAL #undef DDR_PHY_DX8SL1DQSCTL_WRRMODE_SHIFT #undef DDR_PHY_DX8SL1DQSCTL_WRRMODE_MASK -#define DDR_PHY_DX8SL1DQSCTL_WRRMODE_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL1DQSCTL_WRRMODE_SHIFT 21 -#define DDR_PHY_DX8SL1DQSCTL_WRRMODE_MASK 0x00200000U +#define DDR_PHY_DX8SL1DQSCTL_WRRMODE_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL1DQSCTL_WRRMODE_SHIFT 21 +#define DDR_PHY_DX8SL1DQSCTL_WRRMODE_MASK 0x00200000U -/*DQS Gate Extension*/ +/* +* DQS Gate Extension +*/ #undef DDR_PHY_DX8SL1DQSCTL_DQSGX_DEFVAL #undef DDR_PHY_DX8SL1DQSCTL_DQSGX_SHIFT #undef DDR_PHY_DX8SL1DQSCTL_DQSGX_MASK -#define DDR_PHY_DX8SL1DQSCTL_DQSGX_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL1DQSCTL_DQSGX_SHIFT 19 -#define DDR_PHY_DX8SL1DQSCTL_DQSGX_MASK 0x00180000U +#define DDR_PHY_DX8SL1DQSCTL_DQSGX_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL1DQSCTL_DQSGX_SHIFT 19 +#define DDR_PHY_DX8SL1DQSCTL_DQSGX_MASK 0x00180000U -/*Low Power PLL Power Down*/ +/* +* Low Power PLL Power Down +*/ #undef DDR_PHY_DX8SL1DQSCTL_LPPLLPD_DEFVAL #undef DDR_PHY_DX8SL1DQSCTL_LPPLLPD_SHIFT #undef DDR_PHY_DX8SL1DQSCTL_LPPLLPD_MASK -#define DDR_PHY_DX8SL1DQSCTL_LPPLLPD_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL1DQSCTL_LPPLLPD_SHIFT 18 -#define DDR_PHY_DX8SL1DQSCTL_LPPLLPD_MASK 0x00040000U +#define DDR_PHY_DX8SL1DQSCTL_LPPLLPD_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL1DQSCTL_LPPLLPD_SHIFT 18 +#define DDR_PHY_DX8SL1DQSCTL_LPPLLPD_MASK 0x00040000U -/*Low Power I/O Power Down*/ +/* +* Low Power I/O Power Down +*/ #undef DDR_PHY_DX8SL1DQSCTL_LPIOPD_DEFVAL #undef DDR_PHY_DX8SL1DQSCTL_LPIOPD_SHIFT #undef DDR_PHY_DX8SL1DQSCTL_LPIOPD_MASK -#define DDR_PHY_DX8SL1DQSCTL_LPIOPD_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL1DQSCTL_LPIOPD_SHIFT 17 -#define DDR_PHY_DX8SL1DQSCTL_LPIOPD_MASK 0x00020000U +#define DDR_PHY_DX8SL1DQSCTL_LPIOPD_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL1DQSCTL_LPIOPD_SHIFT 17 +#define DDR_PHY_DX8SL1DQSCTL_LPIOPD_MASK 0x00020000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_DEFVAL #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_SHIFT #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_MASK -#define DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_SHIFT 15 -#define DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_MASK 0x00018000U +#define DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_SHIFT 15 +#define DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_MASK 0x00018000U -/*QS Counter Enable*/ +/* +* QS Counter Enable +*/ #undef DDR_PHY_DX8SL1DQSCTL_QSCNTEN_DEFVAL #undef DDR_PHY_DX8SL1DQSCTL_QSCNTEN_SHIFT #undef DDR_PHY_DX8SL1DQSCTL_QSCNTEN_MASK -#define DDR_PHY_DX8SL1DQSCTL_QSCNTEN_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL1DQSCTL_QSCNTEN_SHIFT 14 -#define DDR_PHY_DX8SL1DQSCTL_QSCNTEN_MASK 0x00004000U +#define DDR_PHY_DX8SL1DQSCTL_QSCNTEN_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL1DQSCTL_QSCNTEN_SHIFT 14 +#define DDR_PHY_DX8SL1DQSCTL_QSCNTEN_MASK 0x00004000U -/*Unused DQ I/O Mode*/ +/* +* Unused DQ I/O Mode +*/ #undef DDR_PHY_DX8SL1DQSCTL_UDQIOM_DEFVAL #undef DDR_PHY_DX8SL1DQSCTL_UDQIOM_SHIFT #undef DDR_PHY_DX8SL1DQSCTL_UDQIOM_MASK -#define DDR_PHY_DX8SL1DQSCTL_UDQIOM_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL1DQSCTL_UDQIOM_SHIFT 13 -#define DDR_PHY_DX8SL1DQSCTL_UDQIOM_MASK 0x00002000U +#define DDR_PHY_DX8SL1DQSCTL_UDQIOM_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL1DQSCTL_UDQIOM_SHIFT 13 +#define DDR_PHY_DX8SL1DQSCTL_UDQIOM_MASK 0x00002000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_DEFVAL #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_SHIFT #undef DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_MASK -#define DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_SHIFT 10 -#define DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_MASK 0x00001C00U +#define DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_SHIFT 10 +#define DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_MASK 0x00001C00U -/*Data Slew Rate*/ +/* +* Data Slew Rate +*/ #undef DDR_PHY_DX8SL1DQSCTL_DXSR_DEFVAL #undef DDR_PHY_DX8SL1DQSCTL_DXSR_SHIFT #undef DDR_PHY_DX8SL1DQSCTL_DXSR_MASK -#define DDR_PHY_DX8SL1DQSCTL_DXSR_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL1DQSCTL_DXSR_SHIFT 8 -#define DDR_PHY_DX8SL1DQSCTL_DXSR_MASK 0x00000300U +#define DDR_PHY_DX8SL1DQSCTL_DXSR_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL1DQSCTL_DXSR_SHIFT 8 +#define DDR_PHY_DX8SL1DQSCTL_DXSR_MASK 0x00000300U -/*DQS_N Resistor*/ +/* +* DQS_N Resistor +*/ #undef DDR_PHY_DX8SL1DQSCTL_DQSNRES_DEFVAL #undef DDR_PHY_DX8SL1DQSCTL_DQSNRES_SHIFT #undef DDR_PHY_DX8SL1DQSCTL_DQSNRES_MASK -#define DDR_PHY_DX8SL1DQSCTL_DQSNRES_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL1DQSCTL_DQSNRES_SHIFT 4 -#define DDR_PHY_DX8SL1DQSCTL_DQSNRES_MASK 0x000000F0U +#define DDR_PHY_DX8SL1DQSCTL_DQSNRES_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL1DQSCTL_DQSNRES_SHIFT 4 +#define DDR_PHY_DX8SL1DQSCTL_DQSNRES_MASK 0x000000F0U -/*DQS Resistor*/ +/* +* DQS Resistor +*/ #undef DDR_PHY_DX8SL1DQSCTL_DQSRES_DEFVAL #undef DDR_PHY_DX8SL1DQSCTL_DQSRES_SHIFT #undef DDR_PHY_DX8SL1DQSCTL_DQSRES_MASK -#define DDR_PHY_DX8SL1DQSCTL_DQSRES_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL1DQSCTL_DQSRES_SHIFT 0 -#define DDR_PHY_DX8SL1DQSCTL_DQSRES_MASK 0x0000000FU +#define DDR_PHY_DX8SL1DQSCTL_DQSRES_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL1DQSCTL_DQSRES_SHIFT 0 +#define DDR_PHY_DX8SL1DQSCTL_DQSRES_MASK 0x0000000FU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_DEFVAL #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_SHIFT #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_MASK -#define DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_SHIFT 24 -#define DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_MASK 0xFF000000U +#define DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_SHIFT 24 +#define DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_MASK 0xFF000000U -/*Configurable Read Data Enable*/ +/* +* Configurable Read Data Enable +*/ #undef DDR_PHY_DX8SL1DXCTL2_CRDEN_DEFVAL #undef DDR_PHY_DX8SL1DXCTL2_CRDEN_SHIFT #undef DDR_PHY_DX8SL1DXCTL2_CRDEN_MASK -#define DDR_PHY_DX8SL1DXCTL2_CRDEN_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL1DXCTL2_CRDEN_SHIFT 23 -#define DDR_PHY_DX8SL1DXCTL2_CRDEN_MASK 0x00800000U +#define DDR_PHY_DX8SL1DXCTL2_CRDEN_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_CRDEN_SHIFT 23 +#define DDR_PHY_DX8SL1DXCTL2_CRDEN_MASK 0x00800000U -/*OX Extension during Post-amble*/ +/* +* OX Extension during Post-amble +*/ #undef DDR_PHY_DX8SL1DXCTL2_POSOEX_DEFVAL #undef DDR_PHY_DX8SL1DXCTL2_POSOEX_SHIFT #undef DDR_PHY_DX8SL1DXCTL2_POSOEX_MASK -#define DDR_PHY_DX8SL1DXCTL2_POSOEX_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL1DXCTL2_POSOEX_SHIFT 20 -#define DDR_PHY_DX8SL1DXCTL2_POSOEX_MASK 0x00700000U +#define DDR_PHY_DX8SL1DXCTL2_POSOEX_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_POSOEX_SHIFT 20 +#define DDR_PHY_DX8SL1DXCTL2_POSOEX_MASK 0x00700000U -/*OE Extension during Pre-amble*/ +/* +* OE Extension during Pre-amble +*/ #undef DDR_PHY_DX8SL1DXCTL2_PREOEX_DEFVAL #undef DDR_PHY_DX8SL1DXCTL2_PREOEX_SHIFT #undef DDR_PHY_DX8SL1DXCTL2_PREOEX_MASK -#define DDR_PHY_DX8SL1DXCTL2_PREOEX_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL1DXCTL2_PREOEX_SHIFT 18 -#define DDR_PHY_DX8SL1DXCTL2_PREOEX_MASK 0x000C0000U +#define DDR_PHY_DX8SL1DXCTL2_PREOEX_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_PREOEX_SHIFT 18 +#define DDR_PHY_DX8SL1DXCTL2_PREOEX_MASK 0x000C0000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_17_DEFVAL #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_17_SHIFT #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_17_MASK -#define DDR_PHY_DX8SL1DXCTL2_RESERVED_17_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL1DXCTL2_RESERVED_17_SHIFT 17 -#define DDR_PHY_DX8SL1DXCTL2_RESERVED_17_MASK 0x00020000U +#define DDR_PHY_DX8SL1DXCTL2_RESERVED_17_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_RESERVED_17_SHIFT 17 +#define DDR_PHY_DX8SL1DXCTL2_RESERVED_17_MASK 0x00020000U -/*I/O Assisted Gate Select*/ +/* +* I/O Assisted Gate Select +*/ #undef DDR_PHY_DX8SL1DXCTL2_IOAG_DEFVAL #undef DDR_PHY_DX8SL1DXCTL2_IOAG_SHIFT #undef DDR_PHY_DX8SL1DXCTL2_IOAG_MASK -#define DDR_PHY_DX8SL1DXCTL2_IOAG_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL1DXCTL2_IOAG_SHIFT 16 -#define DDR_PHY_DX8SL1DXCTL2_IOAG_MASK 0x00010000U +#define DDR_PHY_DX8SL1DXCTL2_IOAG_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_IOAG_SHIFT 16 +#define DDR_PHY_DX8SL1DXCTL2_IOAG_MASK 0x00010000U -/*I/O Loopback Select*/ +/* +* I/O Loopback Select +*/ #undef DDR_PHY_DX8SL1DXCTL2_IOLB_DEFVAL #undef DDR_PHY_DX8SL1DXCTL2_IOLB_SHIFT #undef DDR_PHY_DX8SL1DXCTL2_IOLB_MASK -#define DDR_PHY_DX8SL1DXCTL2_IOLB_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL1DXCTL2_IOLB_SHIFT 15 -#define DDR_PHY_DX8SL1DXCTL2_IOLB_MASK 0x00008000U +#define DDR_PHY_DX8SL1DXCTL2_IOLB_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_IOLB_SHIFT 15 +#define DDR_PHY_DX8SL1DXCTL2_IOLB_MASK 0x00008000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_DEFVAL #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_SHIFT #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_MASK -#define DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_SHIFT 13 -#define DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_MASK 0x00006000U +#define DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_SHIFT 13 +#define DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_MASK 0x00006000U -/*Low Power Wakeup Threshold*/ +/* +* Low Power Wakeup Threshold +*/ #undef DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_DEFVAL #undef DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_SHIFT #undef DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_MASK -#define DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_SHIFT 9 -#define DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_MASK 0x00001E00U +#define DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_SHIFT 9 +#define DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_MASK 0x00001E00U -/*Read Data Bus Inversion Enable*/ +/* +* Read Data Bus Inversion Enable +*/ #undef DDR_PHY_DX8SL1DXCTL2_RDBI_DEFVAL #undef DDR_PHY_DX8SL1DXCTL2_RDBI_SHIFT #undef DDR_PHY_DX8SL1DXCTL2_RDBI_MASK -#define DDR_PHY_DX8SL1DXCTL2_RDBI_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL1DXCTL2_RDBI_SHIFT 8 -#define DDR_PHY_DX8SL1DXCTL2_RDBI_MASK 0x00000100U +#define DDR_PHY_DX8SL1DXCTL2_RDBI_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_RDBI_SHIFT 8 +#define DDR_PHY_DX8SL1DXCTL2_RDBI_MASK 0x00000100U -/*Write Data Bus Inversion Enable*/ +/* +* Write Data Bus Inversion Enable +*/ #undef DDR_PHY_DX8SL1DXCTL2_WDBI_DEFVAL #undef DDR_PHY_DX8SL1DXCTL2_WDBI_SHIFT #undef DDR_PHY_DX8SL1DXCTL2_WDBI_MASK -#define DDR_PHY_DX8SL1DXCTL2_WDBI_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL1DXCTL2_WDBI_SHIFT 7 -#define DDR_PHY_DX8SL1DXCTL2_WDBI_MASK 0x00000080U +#define DDR_PHY_DX8SL1DXCTL2_WDBI_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_WDBI_SHIFT 7 +#define DDR_PHY_DX8SL1DXCTL2_WDBI_MASK 0x00000080U -/*PUB Read FIFO Bypass*/ +/* +* PUB Read FIFO Bypass +*/ #undef DDR_PHY_DX8SL1DXCTL2_PRFBYP_DEFVAL #undef DDR_PHY_DX8SL1DXCTL2_PRFBYP_SHIFT #undef DDR_PHY_DX8SL1DXCTL2_PRFBYP_MASK -#define DDR_PHY_DX8SL1DXCTL2_PRFBYP_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL1DXCTL2_PRFBYP_SHIFT 6 -#define DDR_PHY_DX8SL1DXCTL2_PRFBYP_MASK 0x00000040U +#define DDR_PHY_DX8SL1DXCTL2_PRFBYP_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_PRFBYP_SHIFT 6 +#define DDR_PHY_DX8SL1DXCTL2_PRFBYP_MASK 0x00000040U -/*DATX8 Receive FIFO Read Mode*/ +/* +* DATX8 Receive FIFO Read Mode +*/ #undef DDR_PHY_DX8SL1DXCTL2_RDMODE_DEFVAL #undef DDR_PHY_DX8SL1DXCTL2_RDMODE_SHIFT #undef DDR_PHY_DX8SL1DXCTL2_RDMODE_MASK -#define DDR_PHY_DX8SL1DXCTL2_RDMODE_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL1DXCTL2_RDMODE_SHIFT 4 -#define DDR_PHY_DX8SL1DXCTL2_RDMODE_MASK 0x00000030U +#define DDR_PHY_DX8SL1DXCTL2_RDMODE_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_RDMODE_SHIFT 4 +#define DDR_PHY_DX8SL1DXCTL2_RDMODE_MASK 0x00000030U -/*Disables the Read FIFO Reset*/ +/* +* Disables the Read FIFO Reset +*/ #undef DDR_PHY_DX8SL1DXCTL2_DISRST_DEFVAL #undef DDR_PHY_DX8SL1DXCTL2_DISRST_SHIFT #undef DDR_PHY_DX8SL1DXCTL2_DISRST_MASK -#define DDR_PHY_DX8SL1DXCTL2_DISRST_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL1DXCTL2_DISRST_SHIFT 3 -#define DDR_PHY_DX8SL1DXCTL2_DISRST_MASK 0x00000008U +#define DDR_PHY_DX8SL1DXCTL2_DISRST_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_DISRST_SHIFT 3 +#define DDR_PHY_DX8SL1DXCTL2_DISRST_MASK 0x00000008U -/*Read DQS Gate I/O Loopback*/ +/* +* Read DQS Gate I/O Loopback +*/ #undef DDR_PHY_DX8SL1DXCTL2_DQSGLB_DEFVAL #undef DDR_PHY_DX8SL1DXCTL2_DQSGLB_SHIFT #undef DDR_PHY_DX8SL1DXCTL2_DQSGLB_MASK -#define DDR_PHY_DX8SL1DXCTL2_DQSGLB_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL1DXCTL2_DQSGLB_SHIFT 1 -#define DDR_PHY_DX8SL1DXCTL2_DQSGLB_MASK 0x00000006U +#define DDR_PHY_DX8SL1DXCTL2_DQSGLB_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_DQSGLB_SHIFT 1 +#define DDR_PHY_DX8SL1DXCTL2_DQSGLB_MASK 0x00000006U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_0_DEFVAL #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_0_SHIFT #undef DDR_PHY_DX8SL1DXCTL2_RESERVED_0_MASK -#define DDR_PHY_DX8SL1DXCTL2_RESERVED_0_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL1DXCTL2_RESERVED_0_SHIFT 0 -#define DDR_PHY_DX8SL1DXCTL2_RESERVED_0_MASK 0x00000001U +#define DDR_PHY_DX8SL1DXCTL2_RESERVED_0_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL1DXCTL2_RESERVED_0_SHIFT 0 +#define DDR_PHY_DX8SL1DXCTL2_RESERVED_0_MASK 0x00000001U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL1IOCR_RESERVED_31_DEFVAL #undef DDR_PHY_DX8SL1IOCR_RESERVED_31_SHIFT #undef DDR_PHY_DX8SL1IOCR_RESERVED_31_MASK -#define DDR_PHY_DX8SL1IOCR_RESERVED_31_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL1IOCR_RESERVED_31_SHIFT 31 -#define DDR_PHY_DX8SL1IOCR_RESERVED_31_MASK 0x80000000U +#define DDR_PHY_DX8SL1IOCR_RESERVED_31_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL1IOCR_RESERVED_31_SHIFT 31 +#define DDR_PHY_DX8SL1IOCR_RESERVED_31_MASK 0x80000000U -/*PVREF_DAC REFSEL range select*/ +/* +* PVREF_DAC REFSEL range select +*/ #undef DDR_PHY_DX8SL1IOCR_DXDACRANGE_DEFVAL #undef DDR_PHY_DX8SL1IOCR_DXDACRANGE_SHIFT #undef DDR_PHY_DX8SL1IOCR_DXDACRANGE_MASK -#define DDR_PHY_DX8SL1IOCR_DXDACRANGE_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL1IOCR_DXDACRANGE_SHIFT 28 -#define DDR_PHY_DX8SL1IOCR_DXDACRANGE_MASK 0x70000000U +#define DDR_PHY_DX8SL1IOCR_DXDACRANGE_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL1IOCR_DXDACRANGE_SHIFT 28 +#define DDR_PHY_DX8SL1IOCR_DXDACRANGE_MASK 0x70000000U -/*IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring*/ +/* +* IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring +*/ #undef DDR_PHY_DX8SL1IOCR_DXVREFIOM_DEFVAL #undef DDR_PHY_DX8SL1IOCR_DXVREFIOM_SHIFT #undef DDR_PHY_DX8SL1IOCR_DXVREFIOM_MASK -#define DDR_PHY_DX8SL1IOCR_DXVREFIOM_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL1IOCR_DXVREFIOM_SHIFT 25 -#define DDR_PHY_DX8SL1IOCR_DXVREFIOM_MASK 0x0E000000U +#define DDR_PHY_DX8SL1IOCR_DXVREFIOM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL1IOCR_DXVREFIOM_SHIFT 25 +#define DDR_PHY_DX8SL1IOCR_DXVREFIOM_MASK 0x0E000000U -/*DX IO Mode*/ +/* +* DX IO Mode +*/ #undef DDR_PHY_DX8SL1IOCR_DXIOM_DEFVAL #undef DDR_PHY_DX8SL1IOCR_DXIOM_SHIFT #undef DDR_PHY_DX8SL1IOCR_DXIOM_MASK -#define DDR_PHY_DX8SL1IOCR_DXIOM_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL1IOCR_DXIOM_SHIFT 22 -#define DDR_PHY_DX8SL1IOCR_DXIOM_MASK 0x01C00000U +#define DDR_PHY_DX8SL1IOCR_DXIOM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL1IOCR_DXIOM_SHIFT 22 +#define DDR_PHY_DX8SL1IOCR_DXIOM_MASK 0x01C00000U -/*DX IO Transmitter Mode*/ +/* +* DX IO Transmitter Mode +*/ #undef DDR_PHY_DX8SL1IOCR_DXTXM_DEFVAL #undef DDR_PHY_DX8SL1IOCR_DXTXM_SHIFT #undef DDR_PHY_DX8SL1IOCR_DXTXM_MASK -#define DDR_PHY_DX8SL1IOCR_DXTXM_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL1IOCR_DXTXM_SHIFT 11 -#define DDR_PHY_DX8SL1IOCR_DXTXM_MASK 0x003FF800U +#define DDR_PHY_DX8SL1IOCR_DXTXM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL1IOCR_DXTXM_SHIFT 11 +#define DDR_PHY_DX8SL1IOCR_DXTXM_MASK 0x003FF800U -/*DX IO Receiver Mode*/ +/* +* DX IO Receiver Mode +*/ #undef DDR_PHY_DX8SL1IOCR_DXRXM_DEFVAL #undef DDR_PHY_DX8SL1IOCR_DXRXM_SHIFT #undef DDR_PHY_DX8SL1IOCR_DXRXM_MASK -#define DDR_PHY_DX8SL1IOCR_DXRXM_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL1IOCR_DXRXM_SHIFT 0 -#define DDR_PHY_DX8SL1IOCR_DXRXM_MASK 0x000007FFU +#define DDR_PHY_DX8SL1IOCR_DXRXM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL1IOCR_DXRXM_SHIFT 0 +#define DDR_PHY_DX8SL1IOCR_DXRXM_MASK 0x000007FFU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL2OSC_RESERVED_31_30_DEFVAL #undef DDR_PHY_DX8SL2OSC_RESERVED_31_30_SHIFT #undef DDR_PHY_DX8SL2OSC_RESERVED_31_30_MASK -#define DDR_PHY_DX8SL2OSC_RESERVED_31_30_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL2OSC_RESERVED_31_30_SHIFT 30 -#define DDR_PHY_DX8SL2OSC_RESERVED_31_30_MASK 0xC0000000U +#define DDR_PHY_DX8SL2OSC_RESERVED_31_30_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX8SL2OSC_RESERVED_31_30_MASK 0xC0000000U -/*Enable Clock Gating for DX ddr_clk*/ +/* +* Enable Clock Gating for DX ddr_clk +*/ #undef DDR_PHY_DX8SL2OSC_GATEDXRDCLK_DEFVAL #undef DDR_PHY_DX8SL2OSC_GATEDXRDCLK_SHIFT #undef DDR_PHY_DX8SL2OSC_GATEDXRDCLK_MASK -#define DDR_PHY_DX8SL2OSC_GATEDXRDCLK_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL2OSC_GATEDXRDCLK_SHIFT 28 -#define DDR_PHY_DX8SL2OSC_GATEDXRDCLK_MASK 0x30000000U +#define DDR_PHY_DX8SL2OSC_GATEDXRDCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_GATEDXRDCLK_SHIFT 28 +#define DDR_PHY_DX8SL2OSC_GATEDXRDCLK_MASK 0x30000000U -/*Enable Clock Gating for DX ctl_rd_clk*/ +/* +* Enable Clock Gating for DX ctl_rd_clk +*/ #undef DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_DEFVAL #undef DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_SHIFT #undef DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_MASK -#define DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_SHIFT 26 -#define DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_MASK 0x0C000000U +#define DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_SHIFT 26 +#define DDR_PHY_DX8SL2OSC_GATEDXDDRCLK_MASK 0x0C000000U -/*Enable Clock Gating for DX ctl_clk*/ +/* +* Enable Clock Gating for DX ctl_clk +*/ #undef DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_DEFVAL #undef DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_SHIFT #undef DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_MASK -#define DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_SHIFT 24 -#define DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_MASK 0x03000000U +#define DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_SHIFT 24 +#define DDR_PHY_DX8SL2OSC_GATEDXCTLCLK_MASK 0x03000000U -/*Selects the level to which clocks will be stalled when clock gating is enabled.*/ +/* +* Selects the level to which clocks will be stalled when clock gating is e + * nabled. +*/ #undef DDR_PHY_DX8SL2OSC_CLKLEVEL_DEFVAL #undef DDR_PHY_DX8SL2OSC_CLKLEVEL_SHIFT #undef DDR_PHY_DX8SL2OSC_CLKLEVEL_MASK -#define DDR_PHY_DX8SL2OSC_CLKLEVEL_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL2OSC_CLKLEVEL_SHIFT 22 -#define DDR_PHY_DX8SL2OSC_CLKLEVEL_MASK 0x00C00000U +#define DDR_PHY_DX8SL2OSC_CLKLEVEL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_CLKLEVEL_SHIFT 22 +#define DDR_PHY_DX8SL2OSC_CLKLEVEL_MASK 0x00C00000U -/*Loopback Mode*/ +/* +* Loopback Mode +*/ #undef DDR_PHY_DX8SL2OSC_LBMODE_DEFVAL #undef DDR_PHY_DX8SL2OSC_LBMODE_SHIFT #undef DDR_PHY_DX8SL2OSC_LBMODE_MASK -#define DDR_PHY_DX8SL2OSC_LBMODE_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL2OSC_LBMODE_SHIFT 21 -#define DDR_PHY_DX8SL2OSC_LBMODE_MASK 0x00200000U +#define DDR_PHY_DX8SL2OSC_LBMODE_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_LBMODE_SHIFT 21 +#define DDR_PHY_DX8SL2OSC_LBMODE_MASK 0x00200000U -/*Load GSDQS LCDL with 2x the calibrated GSDQSPRD value*/ +/* +* Load GSDQS LCDL with 2x the calibrated GSDQSPRD value +*/ #undef DDR_PHY_DX8SL2OSC_LBGSDQS_DEFVAL #undef DDR_PHY_DX8SL2OSC_LBGSDQS_SHIFT #undef DDR_PHY_DX8SL2OSC_LBGSDQS_MASK -#define DDR_PHY_DX8SL2OSC_LBGSDQS_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL2OSC_LBGSDQS_SHIFT 20 -#define DDR_PHY_DX8SL2OSC_LBGSDQS_MASK 0x00100000U +#define DDR_PHY_DX8SL2OSC_LBGSDQS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_LBGSDQS_SHIFT 20 +#define DDR_PHY_DX8SL2OSC_LBGSDQS_MASK 0x00100000U -/*Loopback DQS Gating*/ +/* +* Loopback DQS Gating +*/ #undef DDR_PHY_DX8SL2OSC_LBGDQS_DEFVAL #undef DDR_PHY_DX8SL2OSC_LBGDQS_SHIFT #undef DDR_PHY_DX8SL2OSC_LBGDQS_MASK -#define DDR_PHY_DX8SL2OSC_LBGDQS_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL2OSC_LBGDQS_SHIFT 18 -#define DDR_PHY_DX8SL2OSC_LBGDQS_MASK 0x000C0000U +#define DDR_PHY_DX8SL2OSC_LBGDQS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_LBGDQS_SHIFT 18 +#define DDR_PHY_DX8SL2OSC_LBGDQS_MASK 0x000C0000U -/*Loopback DQS Shift*/ +/* +* Loopback DQS Shift +*/ #undef DDR_PHY_DX8SL2OSC_LBDQSS_DEFVAL #undef DDR_PHY_DX8SL2OSC_LBDQSS_SHIFT #undef DDR_PHY_DX8SL2OSC_LBDQSS_MASK -#define DDR_PHY_DX8SL2OSC_LBDQSS_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL2OSC_LBDQSS_SHIFT 17 -#define DDR_PHY_DX8SL2OSC_LBDQSS_MASK 0x00020000U +#define DDR_PHY_DX8SL2OSC_LBDQSS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_LBDQSS_SHIFT 17 +#define DDR_PHY_DX8SL2OSC_LBDQSS_MASK 0x00020000U -/*PHY High-Speed Reset*/ +/* +* PHY High-Speed Reset +*/ #undef DDR_PHY_DX8SL2OSC_PHYHRST_DEFVAL #undef DDR_PHY_DX8SL2OSC_PHYHRST_SHIFT #undef DDR_PHY_DX8SL2OSC_PHYHRST_MASK -#define DDR_PHY_DX8SL2OSC_PHYHRST_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL2OSC_PHYHRST_SHIFT 16 -#define DDR_PHY_DX8SL2OSC_PHYHRST_MASK 0x00010000U +#define DDR_PHY_DX8SL2OSC_PHYHRST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_PHYHRST_SHIFT 16 +#define DDR_PHY_DX8SL2OSC_PHYHRST_MASK 0x00010000U -/*PHY FIFO Reset*/ +/* +* PHY FIFO Reset +*/ #undef DDR_PHY_DX8SL2OSC_PHYFRST_DEFVAL #undef DDR_PHY_DX8SL2OSC_PHYFRST_SHIFT #undef DDR_PHY_DX8SL2OSC_PHYFRST_MASK -#define DDR_PHY_DX8SL2OSC_PHYFRST_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL2OSC_PHYFRST_SHIFT 15 -#define DDR_PHY_DX8SL2OSC_PHYFRST_MASK 0x00008000U +#define DDR_PHY_DX8SL2OSC_PHYFRST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_PHYFRST_SHIFT 15 +#define DDR_PHY_DX8SL2OSC_PHYFRST_MASK 0x00008000U -/*Delay Line Test Start*/ +/* +* Delay Line Test Start +*/ #undef DDR_PHY_DX8SL2OSC_DLTST_DEFVAL #undef DDR_PHY_DX8SL2OSC_DLTST_SHIFT #undef DDR_PHY_DX8SL2OSC_DLTST_MASK -#define DDR_PHY_DX8SL2OSC_DLTST_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL2OSC_DLTST_SHIFT 14 -#define DDR_PHY_DX8SL2OSC_DLTST_MASK 0x00004000U +#define DDR_PHY_DX8SL2OSC_DLTST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_DLTST_SHIFT 14 +#define DDR_PHY_DX8SL2OSC_DLTST_MASK 0x00004000U -/*Delay Line Test Mode*/ +/* +* Delay Line Test Mode +*/ #undef DDR_PHY_DX8SL2OSC_DLTMODE_DEFVAL #undef DDR_PHY_DX8SL2OSC_DLTMODE_SHIFT #undef DDR_PHY_DX8SL2OSC_DLTMODE_MASK -#define DDR_PHY_DX8SL2OSC_DLTMODE_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL2OSC_DLTMODE_SHIFT 13 -#define DDR_PHY_DX8SL2OSC_DLTMODE_MASK 0x00002000U +#define DDR_PHY_DX8SL2OSC_DLTMODE_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_DLTMODE_SHIFT 13 +#define DDR_PHY_DX8SL2OSC_DLTMODE_MASK 0x00002000U -/*Reserved. Caution, do not write to this register field.*/ +/* +* Reserved. Caution, do not write to this register field. +*/ #undef DDR_PHY_DX8SL2OSC_RESERVED_12_11_DEFVAL #undef DDR_PHY_DX8SL2OSC_RESERVED_12_11_SHIFT #undef DDR_PHY_DX8SL2OSC_RESERVED_12_11_MASK -#define DDR_PHY_DX8SL2OSC_RESERVED_12_11_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL2OSC_RESERVED_12_11_SHIFT 11 -#define DDR_PHY_DX8SL2OSC_RESERVED_12_11_MASK 0x00001800U +#define DDR_PHY_DX8SL2OSC_RESERVED_12_11_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_RESERVED_12_11_SHIFT 11 +#define DDR_PHY_DX8SL2OSC_RESERVED_12_11_MASK 0x00001800U -/*Oscillator Mode Write-Data Delay Line Select*/ +/* +* Oscillator Mode Write-Data Delay Line Select +*/ #undef DDR_PHY_DX8SL2OSC_OSCWDDL_DEFVAL #undef DDR_PHY_DX8SL2OSC_OSCWDDL_SHIFT #undef DDR_PHY_DX8SL2OSC_OSCWDDL_MASK -#define DDR_PHY_DX8SL2OSC_OSCWDDL_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL2OSC_OSCWDDL_SHIFT 9 -#define DDR_PHY_DX8SL2OSC_OSCWDDL_MASK 0x00000600U +#define DDR_PHY_DX8SL2OSC_OSCWDDL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_OSCWDDL_SHIFT 9 +#define DDR_PHY_DX8SL2OSC_OSCWDDL_MASK 0x00000600U -/*Reserved. Caution, do not write to this register field.*/ +/* +* Reserved. Caution, do not write to this register field. +*/ #undef DDR_PHY_DX8SL2OSC_RESERVED_8_7_DEFVAL #undef DDR_PHY_DX8SL2OSC_RESERVED_8_7_SHIFT #undef DDR_PHY_DX8SL2OSC_RESERVED_8_7_MASK -#define DDR_PHY_DX8SL2OSC_RESERVED_8_7_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL2OSC_RESERVED_8_7_SHIFT 7 -#define DDR_PHY_DX8SL2OSC_RESERVED_8_7_MASK 0x00000180U +#define DDR_PHY_DX8SL2OSC_RESERVED_8_7_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_RESERVED_8_7_SHIFT 7 +#define DDR_PHY_DX8SL2OSC_RESERVED_8_7_MASK 0x00000180U -/*Oscillator Mode Write-Leveling Delay Line Select*/ +/* +* Oscillator Mode Write-Leveling Delay Line Select +*/ #undef DDR_PHY_DX8SL2OSC_OSCWDL_DEFVAL #undef DDR_PHY_DX8SL2OSC_OSCWDL_SHIFT #undef DDR_PHY_DX8SL2OSC_OSCWDL_MASK -#define DDR_PHY_DX8SL2OSC_OSCWDL_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL2OSC_OSCWDL_SHIFT 5 -#define DDR_PHY_DX8SL2OSC_OSCWDL_MASK 0x00000060U +#define DDR_PHY_DX8SL2OSC_OSCWDL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_OSCWDL_SHIFT 5 +#define DDR_PHY_DX8SL2OSC_OSCWDL_MASK 0x00000060U -/*Oscillator Mode Division*/ +/* +* Oscillator Mode Division +*/ #undef DDR_PHY_DX8SL2OSC_OSCDIV_DEFVAL #undef DDR_PHY_DX8SL2OSC_OSCDIV_SHIFT #undef DDR_PHY_DX8SL2OSC_OSCDIV_MASK -#define DDR_PHY_DX8SL2OSC_OSCDIV_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL2OSC_OSCDIV_SHIFT 1 -#define DDR_PHY_DX8SL2OSC_OSCDIV_MASK 0x0000001EU +#define DDR_PHY_DX8SL2OSC_OSCDIV_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_OSCDIV_SHIFT 1 +#define DDR_PHY_DX8SL2OSC_OSCDIV_MASK 0x0000001EU -/*Oscillator Enable*/ +/* +* Oscillator Enable +*/ #undef DDR_PHY_DX8SL2OSC_OSCEN_DEFVAL #undef DDR_PHY_DX8SL2OSC_OSCEN_SHIFT #undef DDR_PHY_DX8SL2OSC_OSCEN_MASK -#define DDR_PHY_DX8SL2OSC_OSCEN_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL2OSC_OSCEN_SHIFT 0 -#define DDR_PHY_DX8SL2OSC_OSCEN_MASK 0x00000001U +#define DDR_PHY_DX8SL2OSC_OSCEN_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL2OSC_OSCEN_SHIFT 0 +#define DDR_PHY_DX8SL2OSC_OSCEN_MASK 0x00000001U -/*Reserved. Return zeroes on reads.*/ +/* +* PLL Bypass +*/ +#undef DDR_PHY_DX8SL2PLLCR0_PLLBYP_DEFVAL +#undef DDR_PHY_DX8SL2PLLCR0_PLLBYP_SHIFT +#undef DDR_PHY_DX8SL2PLLCR0_PLLBYP_MASK +#define DDR_PHY_DX8SL2PLLCR0_PLLBYP_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL2PLLCR0_PLLBYP_SHIFT 31 +#define DDR_PHY_DX8SL2PLLCR0_PLLBYP_MASK 0x80000000U + +/* +* PLL Reset +*/ +#undef DDR_PHY_DX8SL2PLLCR0_PLLRST_DEFVAL +#undef DDR_PHY_DX8SL2PLLCR0_PLLRST_SHIFT +#undef DDR_PHY_DX8SL2PLLCR0_PLLRST_MASK +#define DDR_PHY_DX8SL2PLLCR0_PLLRST_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL2PLLCR0_PLLRST_SHIFT 30 +#define DDR_PHY_DX8SL2PLLCR0_PLLRST_MASK 0x40000000U + +/* +* PLL Power Down +*/ +#undef DDR_PHY_DX8SL2PLLCR0_PLLPD_DEFVAL +#undef DDR_PHY_DX8SL2PLLCR0_PLLPD_SHIFT +#undef DDR_PHY_DX8SL2PLLCR0_PLLPD_MASK +#define DDR_PHY_DX8SL2PLLCR0_PLLPD_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL2PLLCR0_PLLPD_SHIFT 29 +#define DDR_PHY_DX8SL2PLLCR0_PLLPD_MASK 0x20000000U + +/* +* Reference Stop Mode +*/ +#undef DDR_PHY_DX8SL2PLLCR0_RSTOPM_DEFVAL +#undef DDR_PHY_DX8SL2PLLCR0_RSTOPM_SHIFT +#undef DDR_PHY_DX8SL2PLLCR0_RSTOPM_MASK +#define DDR_PHY_DX8SL2PLLCR0_RSTOPM_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL2PLLCR0_RSTOPM_SHIFT 28 +#define DDR_PHY_DX8SL2PLLCR0_RSTOPM_MASK 0x10000000U + +/* +* PLL Frequency Select +*/ +#undef DDR_PHY_DX8SL2PLLCR0_FRQSEL_DEFVAL +#undef DDR_PHY_DX8SL2PLLCR0_FRQSEL_SHIFT +#undef DDR_PHY_DX8SL2PLLCR0_FRQSEL_MASK +#define DDR_PHY_DX8SL2PLLCR0_FRQSEL_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL2PLLCR0_FRQSEL_SHIFT 24 +#define DDR_PHY_DX8SL2PLLCR0_FRQSEL_MASK 0x0F000000U + +/* +* Relock Mode +*/ +#undef DDR_PHY_DX8SL2PLLCR0_RLOCKM_DEFVAL +#undef DDR_PHY_DX8SL2PLLCR0_RLOCKM_SHIFT +#undef DDR_PHY_DX8SL2PLLCR0_RLOCKM_MASK +#define DDR_PHY_DX8SL2PLLCR0_RLOCKM_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL2PLLCR0_RLOCKM_SHIFT 23 +#define DDR_PHY_DX8SL2PLLCR0_RLOCKM_MASK 0x00800000U + +/* +* Charge Pump Proportional Current Control +*/ +#undef DDR_PHY_DX8SL2PLLCR0_CPPC_DEFVAL +#undef DDR_PHY_DX8SL2PLLCR0_CPPC_SHIFT +#undef DDR_PHY_DX8SL2PLLCR0_CPPC_MASK +#define DDR_PHY_DX8SL2PLLCR0_CPPC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL2PLLCR0_CPPC_SHIFT 17 +#define DDR_PHY_DX8SL2PLLCR0_CPPC_MASK 0x007E0000U + +/* +* Charge Pump Integrating Current Control +*/ +#undef DDR_PHY_DX8SL2PLLCR0_CPIC_DEFVAL +#undef DDR_PHY_DX8SL2PLLCR0_CPIC_SHIFT +#undef DDR_PHY_DX8SL2PLLCR0_CPIC_MASK +#define DDR_PHY_DX8SL2PLLCR0_CPIC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL2PLLCR0_CPIC_SHIFT 13 +#define DDR_PHY_DX8SL2PLLCR0_CPIC_MASK 0x0001E000U + +/* +* Gear Shift +*/ +#undef DDR_PHY_DX8SL2PLLCR0_GSHIFT_DEFVAL +#undef DDR_PHY_DX8SL2PLLCR0_GSHIFT_SHIFT +#undef DDR_PHY_DX8SL2PLLCR0_GSHIFT_MASK +#define DDR_PHY_DX8SL2PLLCR0_GSHIFT_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL2PLLCR0_GSHIFT_SHIFT 12 +#define DDR_PHY_DX8SL2PLLCR0_GSHIFT_MASK 0x00001000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL2PLLCR0_RESERVED_11_9_DEFVAL +#undef DDR_PHY_DX8SL2PLLCR0_RESERVED_11_9_SHIFT +#undef DDR_PHY_DX8SL2PLLCR0_RESERVED_11_9_MASK +#define DDR_PHY_DX8SL2PLLCR0_RESERVED_11_9_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL2PLLCR0_RESERVED_11_9_SHIFT 9 +#define DDR_PHY_DX8SL2PLLCR0_RESERVED_11_9_MASK 0x00000E00U + +/* +* Analog Test Enable (ATOEN) +*/ +#undef DDR_PHY_DX8SL2PLLCR0_ATOEN_DEFVAL +#undef DDR_PHY_DX8SL2PLLCR0_ATOEN_SHIFT +#undef DDR_PHY_DX8SL2PLLCR0_ATOEN_MASK +#define DDR_PHY_DX8SL2PLLCR0_ATOEN_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL2PLLCR0_ATOEN_SHIFT 8 +#define DDR_PHY_DX8SL2PLLCR0_ATOEN_MASK 0x00000100U + +/* +* Analog Test Control +*/ +#undef DDR_PHY_DX8SL2PLLCR0_ATC_DEFVAL +#undef DDR_PHY_DX8SL2PLLCR0_ATC_SHIFT +#undef DDR_PHY_DX8SL2PLLCR0_ATC_MASK +#define DDR_PHY_DX8SL2PLLCR0_ATC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL2PLLCR0_ATC_SHIFT 4 +#define DDR_PHY_DX8SL2PLLCR0_ATC_MASK 0x000000F0U + +/* +* Digital Test Control +*/ +#undef DDR_PHY_DX8SL2PLLCR0_DTC_DEFVAL +#undef DDR_PHY_DX8SL2PLLCR0_DTC_SHIFT +#undef DDR_PHY_DX8SL2PLLCR0_DTC_MASK +#define DDR_PHY_DX8SL2PLLCR0_DTC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL2PLLCR0_DTC_SHIFT 0 +#define DDR_PHY_DX8SL2PLLCR0_DTC_MASK 0x0000000FU + +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_DEFVAL #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_SHIFT #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_MASK -#define DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_SHIFT 25 -#define DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_MASK 0xFE000000U +#define DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_SHIFT 25 +#define DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_MASK 0xFE000000U -/*Read Path Rise-to-Rise Mode*/ +/* +* Read Path Rise-to-Rise Mode +*/ #undef DDR_PHY_DX8SL2DQSCTL_RRRMODE_DEFVAL #undef DDR_PHY_DX8SL2DQSCTL_RRRMODE_SHIFT #undef DDR_PHY_DX8SL2DQSCTL_RRRMODE_MASK -#define DDR_PHY_DX8SL2DQSCTL_RRRMODE_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL2DQSCTL_RRRMODE_SHIFT 24 -#define DDR_PHY_DX8SL2DQSCTL_RRRMODE_MASK 0x01000000U +#define DDR_PHY_DX8SL2DQSCTL_RRRMODE_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL2DQSCTL_RRRMODE_SHIFT 24 +#define DDR_PHY_DX8SL2DQSCTL_RRRMODE_MASK 0x01000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_DEFVAL #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_SHIFT #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_MASK -#define DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_SHIFT 22 -#define DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_MASK 0x00C00000U +#define DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_MASK 0x00C00000U -/*Write Path Rise-to-Rise Mode*/ +/* +* Write Path Rise-to-Rise Mode +*/ #undef DDR_PHY_DX8SL2DQSCTL_WRRMODE_DEFVAL #undef DDR_PHY_DX8SL2DQSCTL_WRRMODE_SHIFT #undef DDR_PHY_DX8SL2DQSCTL_WRRMODE_MASK -#define DDR_PHY_DX8SL2DQSCTL_WRRMODE_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL2DQSCTL_WRRMODE_SHIFT 21 -#define DDR_PHY_DX8SL2DQSCTL_WRRMODE_MASK 0x00200000U +#define DDR_PHY_DX8SL2DQSCTL_WRRMODE_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL2DQSCTL_WRRMODE_SHIFT 21 +#define DDR_PHY_DX8SL2DQSCTL_WRRMODE_MASK 0x00200000U -/*DQS Gate Extension*/ +/* +* DQS Gate Extension +*/ #undef DDR_PHY_DX8SL2DQSCTL_DQSGX_DEFVAL #undef DDR_PHY_DX8SL2DQSCTL_DQSGX_SHIFT #undef DDR_PHY_DX8SL2DQSCTL_DQSGX_MASK -#define DDR_PHY_DX8SL2DQSCTL_DQSGX_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL2DQSCTL_DQSGX_SHIFT 19 -#define DDR_PHY_DX8SL2DQSCTL_DQSGX_MASK 0x00180000U +#define DDR_PHY_DX8SL2DQSCTL_DQSGX_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL2DQSCTL_DQSGX_SHIFT 19 +#define DDR_PHY_DX8SL2DQSCTL_DQSGX_MASK 0x00180000U -/*Low Power PLL Power Down*/ +/* +* Low Power PLL Power Down +*/ #undef DDR_PHY_DX8SL2DQSCTL_LPPLLPD_DEFVAL #undef DDR_PHY_DX8SL2DQSCTL_LPPLLPD_SHIFT #undef DDR_PHY_DX8SL2DQSCTL_LPPLLPD_MASK -#define DDR_PHY_DX8SL2DQSCTL_LPPLLPD_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL2DQSCTL_LPPLLPD_SHIFT 18 -#define DDR_PHY_DX8SL2DQSCTL_LPPLLPD_MASK 0x00040000U +#define DDR_PHY_DX8SL2DQSCTL_LPPLLPD_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL2DQSCTL_LPPLLPD_SHIFT 18 +#define DDR_PHY_DX8SL2DQSCTL_LPPLLPD_MASK 0x00040000U -/*Low Power I/O Power Down*/ +/* +* Low Power I/O Power Down +*/ #undef DDR_PHY_DX8SL2DQSCTL_LPIOPD_DEFVAL #undef DDR_PHY_DX8SL2DQSCTL_LPIOPD_SHIFT #undef DDR_PHY_DX8SL2DQSCTL_LPIOPD_MASK -#define DDR_PHY_DX8SL2DQSCTL_LPIOPD_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL2DQSCTL_LPIOPD_SHIFT 17 -#define DDR_PHY_DX8SL2DQSCTL_LPIOPD_MASK 0x00020000U +#define DDR_PHY_DX8SL2DQSCTL_LPIOPD_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL2DQSCTL_LPIOPD_SHIFT 17 +#define DDR_PHY_DX8SL2DQSCTL_LPIOPD_MASK 0x00020000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_DEFVAL #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_SHIFT #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_MASK -#define DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_SHIFT 15 -#define DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_MASK 0x00018000U +#define DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_SHIFT 15 +#define DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_MASK 0x00018000U -/*QS Counter Enable*/ +/* +* QS Counter Enable +*/ #undef DDR_PHY_DX8SL2DQSCTL_QSCNTEN_DEFVAL #undef DDR_PHY_DX8SL2DQSCTL_QSCNTEN_SHIFT #undef DDR_PHY_DX8SL2DQSCTL_QSCNTEN_MASK -#define DDR_PHY_DX8SL2DQSCTL_QSCNTEN_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL2DQSCTL_QSCNTEN_SHIFT 14 -#define DDR_PHY_DX8SL2DQSCTL_QSCNTEN_MASK 0x00004000U +#define DDR_PHY_DX8SL2DQSCTL_QSCNTEN_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL2DQSCTL_QSCNTEN_SHIFT 14 +#define DDR_PHY_DX8SL2DQSCTL_QSCNTEN_MASK 0x00004000U -/*Unused DQ I/O Mode*/ +/* +* Unused DQ I/O Mode +*/ #undef DDR_PHY_DX8SL2DQSCTL_UDQIOM_DEFVAL #undef DDR_PHY_DX8SL2DQSCTL_UDQIOM_SHIFT #undef DDR_PHY_DX8SL2DQSCTL_UDQIOM_MASK -#define DDR_PHY_DX8SL2DQSCTL_UDQIOM_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL2DQSCTL_UDQIOM_SHIFT 13 -#define DDR_PHY_DX8SL2DQSCTL_UDQIOM_MASK 0x00002000U +#define DDR_PHY_DX8SL2DQSCTL_UDQIOM_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL2DQSCTL_UDQIOM_SHIFT 13 +#define DDR_PHY_DX8SL2DQSCTL_UDQIOM_MASK 0x00002000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_DEFVAL #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_SHIFT #undef DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_MASK -#define DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_SHIFT 10 -#define DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_MASK 0x00001C00U +#define DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_SHIFT 10 +#define DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_MASK 0x00001C00U -/*Data Slew Rate*/ +/* +* Data Slew Rate +*/ #undef DDR_PHY_DX8SL2DQSCTL_DXSR_DEFVAL #undef DDR_PHY_DX8SL2DQSCTL_DXSR_SHIFT #undef DDR_PHY_DX8SL2DQSCTL_DXSR_MASK -#define DDR_PHY_DX8SL2DQSCTL_DXSR_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL2DQSCTL_DXSR_SHIFT 8 -#define DDR_PHY_DX8SL2DQSCTL_DXSR_MASK 0x00000300U +#define DDR_PHY_DX8SL2DQSCTL_DXSR_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL2DQSCTL_DXSR_SHIFT 8 +#define DDR_PHY_DX8SL2DQSCTL_DXSR_MASK 0x00000300U -/*DQS_N Resistor*/ +/* +* DQS_N Resistor +*/ #undef DDR_PHY_DX8SL2DQSCTL_DQSNRES_DEFVAL #undef DDR_PHY_DX8SL2DQSCTL_DQSNRES_SHIFT #undef DDR_PHY_DX8SL2DQSCTL_DQSNRES_MASK -#define DDR_PHY_DX8SL2DQSCTL_DQSNRES_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL2DQSCTL_DQSNRES_SHIFT 4 -#define DDR_PHY_DX8SL2DQSCTL_DQSNRES_MASK 0x000000F0U +#define DDR_PHY_DX8SL2DQSCTL_DQSNRES_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL2DQSCTL_DQSNRES_SHIFT 4 +#define DDR_PHY_DX8SL2DQSCTL_DQSNRES_MASK 0x000000F0U -/*DQS Resistor*/ +/* +* DQS Resistor +*/ #undef DDR_PHY_DX8SL2DQSCTL_DQSRES_DEFVAL #undef DDR_PHY_DX8SL2DQSCTL_DQSRES_SHIFT #undef DDR_PHY_DX8SL2DQSCTL_DQSRES_MASK -#define DDR_PHY_DX8SL2DQSCTL_DQSRES_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL2DQSCTL_DQSRES_SHIFT 0 -#define DDR_PHY_DX8SL2DQSCTL_DQSRES_MASK 0x0000000FU +#define DDR_PHY_DX8SL2DQSCTL_DQSRES_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL2DQSCTL_DQSRES_SHIFT 0 +#define DDR_PHY_DX8SL2DQSCTL_DQSRES_MASK 0x0000000FU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_DEFVAL #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_SHIFT #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_MASK -#define DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_SHIFT 24 -#define DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_MASK 0xFF000000U +#define DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_SHIFT 24 +#define DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_MASK 0xFF000000U -/*Configurable Read Data Enable*/ +/* +* Configurable Read Data Enable +*/ #undef DDR_PHY_DX8SL2DXCTL2_CRDEN_DEFVAL #undef DDR_PHY_DX8SL2DXCTL2_CRDEN_SHIFT #undef DDR_PHY_DX8SL2DXCTL2_CRDEN_MASK -#define DDR_PHY_DX8SL2DXCTL2_CRDEN_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL2DXCTL2_CRDEN_SHIFT 23 -#define DDR_PHY_DX8SL2DXCTL2_CRDEN_MASK 0x00800000U +#define DDR_PHY_DX8SL2DXCTL2_CRDEN_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_CRDEN_SHIFT 23 +#define DDR_PHY_DX8SL2DXCTL2_CRDEN_MASK 0x00800000U -/*OX Extension during Post-amble*/ +/* +* OX Extension during Post-amble +*/ #undef DDR_PHY_DX8SL2DXCTL2_POSOEX_DEFVAL #undef DDR_PHY_DX8SL2DXCTL2_POSOEX_SHIFT #undef DDR_PHY_DX8SL2DXCTL2_POSOEX_MASK -#define DDR_PHY_DX8SL2DXCTL2_POSOEX_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL2DXCTL2_POSOEX_SHIFT 20 -#define DDR_PHY_DX8SL2DXCTL2_POSOEX_MASK 0x00700000U +#define DDR_PHY_DX8SL2DXCTL2_POSOEX_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_POSOEX_SHIFT 20 +#define DDR_PHY_DX8SL2DXCTL2_POSOEX_MASK 0x00700000U -/*OE Extension during Pre-amble*/ +/* +* OE Extension during Pre-amble +*/ #undef DDR_PHY_DX8SL2DXCTL2_PREOEX_DEFVAL #undef DDR_PHY_DX8SL2DXCTL2_PREOEX_SHIFT #undef DDR_PHY_DX8SL2DXCTL2_PREOEX_MASK -#define DDR_PHY_DX8SL2DXCTL2_PREOEX_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL2DXCTL2_PREOEX_SHIFT 18 -#define DDR_PHY_DX8SL2DXCTL2_PREOEX_MASK 0x000C0000U +#define DDR_PHY_DX8SL2DXCTL2_PREOEX_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_PREOEX_SHIFT 18 +#define DDR_PHY_DX8SL2DXCTL2_PREOEX_MASK 0x000C0000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_17_DEFVAL #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_17_SHIFT #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_17_MASK -#define DDR_PHY_DX8SL2DXCTL2_RESERVED_17_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL2DXCTL2_RESERVED_17_SHIFT 17 -#define DDR_PHY_DX8SL2DXCTL2_RESERVED_17_MASK 0x00020000U +#define DDR_PHY_DX8SL2DXCTL2_RESERVED_17_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_RESERVED_17_SHIFT 17 +#define DDR_PHY_DX8SL2DXCTL2_RESERVED_17_MASK 0x00020000U -/*I/O Assisted Gate Select*/ +/* +* I/O Assisted Gate Select +*/ #undef DDR_PHY_DX8SL2DXCTL2_IOAG_DEFVAL #undef DDR_PHY_DX8SL2DXCTL2_IOAG_SHIFT #undef DDR_PHY_DX8SL2DXCTL2_IOAG_MASK -#define DDR_PHY_DX8SL2DXCTL2_IOAG_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL2DXCTL2_IOAG_SHIFT 16 -#define DDR_PHY_DX8SL2DXCTL2_IOAG_MASK 0x00010000U +#define DDR_PHY_DX8SL2DXCTL2_IOAG_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_IOAG_SHIFT 16 +#define DDR_PHY_DX8SL2DXCTL2_IOAG_MASK 0x00010000U -/*I/O Loopback Select*/ +/* +* I/O Loopback Select +*/ #undef DDR_PHY_DX8SL2DXCTL2_IOLB_DEFVAL #undef DDR_PHY_DX8SL2DXCTL2_IOLB_SHIFT #undef DDR_PHY_DX8SL2DXCTL2_IOLB_MASK -#define DDR_PHY_DX8SL2DXCTL2_IOLB_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL2DXCTL2_IOLB_SHIFT 15 -#define DDR_PHY_DX8SL2DXCTL2_IOLB_MASK 0x00008000U +#define DDR_PHY_DX8SL2DXCTL2_IOLB_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_IOLB_SHIFT 15 +#define DDR_PHY_DX8SL2DXCTL2_IOLB_MASK 0x00008000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_DEFVAL #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_SHIFT #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_MASK -#define DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_SHIFT 13 -#define DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_MASK 0x00006000U +#define DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_SHIFT 13 +#define DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_MASK 0x00006000U -/*Low Power Wakeup Threshold*/ +/* +* Low Power Wakeup Threshold +*/ #undef DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_DEFVAL #undef DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_SHIFT #undef DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_MASK -#define DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_SHIFT 9 -#define DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_MASK 0x00001E00U +#define DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_SHIFT 9 +#define DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_MASK 0x00001E00U -/*Read Data Bus Inversion Enable*/ +/* +* Read Data Bus Inversion Enable +*/ #undef DDR_PHY_DX8SL2DXCTL2_RDBI_DEFVAL #undef DDR_PHY_DX8SL2DXCTL2_RDBI_SHIFT #undef DDR_PHY_DX8SL2DXCTL2_RDBI_MASK -#define DDR_PHY_DX8SL2DXCTL2_RDBI_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL2DXCTL2_RDBI_SHIFT 8 -#define DDR_PHY_DX8SL2DXCTL2_RDBI_MASK 0x00000100U +#define DDR_PHY_DX8SL2DXCTL2_RDBI_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_RDBI_SHIFT 8 +#define DDR_PHY_DX8SL2DXCTL2_RDBI_MASK 0x00000100U -/*Write Data Bus Inversion Enable*/ +/* +* Write Data Bus Inversion Enable +*/ #undef DDR_PHY_DX8SL2DXCTL2_WDBI_DEFVAL #undef DDR_PHY_DX8SL2DXCTL2_WDBI_SHIFT #undef DDR_PHY_DX8SL2DXCTL2_WDBI_MASK -#define DDR_PHY_DX8SL2DXCTL2_WDBI_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL2DXCTL2_WDBI_SHIFT 7 -#define DDR_PHY_DX8SL2DXCTL2_WDBI_MASK 0x00000080U +#define DDR_PHY_DX8SL2DXCTL2_WDBI_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_WDBI_SHIFT 7 +#define DDR_PHY_DX8SL2DXCTL2_WDBI_MASK 0x00000080U -/*PUB Read FIFO Bypass*/ +/* +* PUB Read FIFO Bypass +*/ #undef DDR_PHY_DX8SL2DXCTL2_PRFBYP_DEFVAL #undef DDR_PHY_DX8SL2DXCTL2_PRFBYP_SHIFT #undef DDR_PHY_DX8SL2DXCTL2_PRFBYP_MASK -#define DDR_PHY_DX8SL2DXCTL2_PRFBYP_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL2DXCTL2_PRFBYP_SHIFT 6 -#define DDR_PHY_DX8SL2DXCTL2_PRFBYP_MASK 0x00000040U +#define DDR_PHY_DX8SL2DXCTL2_PRFBYP_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_PRFBYP_SHIFT 6 +#define DDR_PHY_DX8SL2DXCTL2_PRFBYP_MASK 0x00000040U -/*DATX8 Receive FIFO Read Mode*/ +/* +* DATX8 Receive FIFO Read Mode +*/ #undef DDR_PHY_DX8SL2DXCTL2_RDMODE_DEFVAL #undef DDR_PHY_DX8SL2DXCTL2_RDMODE_SHIFT #undef DDR_PHY_DX8SL2DXCTL2_RDMODE_MASK -#define DDR_PHY_DX8SL2DXCTL2_RDMODE_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL2DXCTL2_RDMODE_SHIFT 4 -#define DDR_PHY_DX8SL2DXCTL2_RDMODE_MASK 0x00000030U +#define DDR_PHY_DX8SL2DXCTL2_RDMODE_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_RDMODE_SHIFT 4 +#define DDR_PHY_DX8SL2DXCTL2_RDMODE_MASK 0x00000030U -/*Disables the Read FIFO Reset*/ +/* +* Disables the Read FIFO Reset +*/ #undef DDR_PHY_DX8SL2DXCTL2_DISRST_DEFVAL #undef DDR_PHY_DX8SL2DXCTL2_DISRST_SHIFT #undef DDR_PHY_DX8SL2DXCTL2_DISRST_MASK -#define DDR_PHY_DX8SL2DXCTL2_DISRST_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL2DXCTL2_DISRST_SHIFT 3 -#define DDR_PHY_DX8SL2DXCTL2_DISRST_MASK 0x00000008U +#define DDR_PHY_DX8SL2DXCTL2_DISRST_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_DISRST_SHIFT 3 +#define DDR_PHY_DX8SL2DXCTL2_DISRST_MASK 0x00000008U -/*Read DQS Gate I/O Loopback*/ +/* +* Read DQS Gate I/O Loopback +*/ #undef DDR_PHY_DX8SL2DXCTL2_DQSGLB_DEFVAL #undef DDR_PHY_DX8SL2DXCTL2_DQSGLB_SHIFT #undef DDR_PHY_DX8SL2DXCTL2_DQSGLB_MASK -#define DDR_PHY_DX8SL2DXCTL2_DQSGLB_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL2DXCTL2_DQSGLB_SHIFT 1 -#define DDR_PHY_DX8SL2DXCTL2_DQSGLB_MASK 0x00000006U +#define DDR_PHY_DX8SL2DXCTL2_DQSGLB_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_DQSGLB_SHIFT 1 +#define DDR_PHY_DX8SL2DXCTL2_DQSGLB_MASK 0x00000006U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_0_DEFVAL #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_0_SHIFT #undef DDR_PHY_DX8SL2DXCTL2_RESERVED_0_MASK -#define DDR_PHY_DX8SL2DXCTL2_RESERVED_0_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL2DXCTL2_RESERVED_0_SHIFT 0 -#define DDR_PHY_DX8SL2DXCTL2_RESERVED_0_MASK 0x00000001U +#define DDR_PHY_DX8SL2DXCTL2_RESERVED_0_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL2DXCTL2_RESERVED_0_SHIFT 0 +#define DDR_PHY_DX8SL2DXCTL2_RESERVED_0_MASK 0x00000001U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL2IOCR_RESERVED_31_DEFVAL #undef DDR_PHY_DX8SL2IOCR_RESERVED_31_SHIFT #undef DDR_PHY_DX8SL2IOCR_RESERVED_31_MASK -#define DDR_PHY_DX8SL2IOCR_RESERVED_31_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL2IOCR_RESERVED_31_SHIFT 31 -#define DDR_PHY_DX8SL2IOCR_RESERVED_31_MASK 0x80000000U +#define DDR_PHY_DX8SL2IOCR_RESERVED_31_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL2IOCR_RESERVED_31_SHIFT 31 +#define DDR_PHY_DX8SL2IOCR_RESERVED_31_MASK 0x80000000U -/*PVREF_DAC REFSEL range select*/ +/* +* PVREF_DAC REFSEL range select +*/ #undef DDR_PHY_DX8SL2IOCR_DXDACRANGE_DEFVAL #undef DDR_PHY_DX8SL2IOCR_DXDACRANGE_SHIFT #undef DDR_PHY_DX8SL2IOCR_DXDACRANGE_MASK -#define DDR_PHY_DX8SL2IOCR_DXDACRANGE_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL2IOCR_DXDACRANGE_SHIFT 28 -#define DDR_PHY_DX8SL2IOCR_DXDACRANGE_MASK 0x70000000U +#define DDR_PHY_DX8SL2IOCR_DXDACRANGE_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL2IOCR_DXDACRANGE_SHIFT 28 +#define DDR_PHY_DX8SL2IOCR_DXDACRANGE_MASK 0x70000000U -/*IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring*/ +/* +* IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring +*/ #undef DDR_PHY_DX8SL2IOCR_DXVREFIOM_DEFVAL #undef DDR_PHY_DX8SL2IOCR_DXVREFIOM_SHIFT #undef DDR_PHY_DX8SL2IOCR_DXVREFIOM_MASK -#define DDR_PHY_DX8SL2IOCR_DXVREFIOM_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL2IOCR_DXVREFIOM_SHIFT 25 -#define DDR_PHY_DX8SL2IOCR_DXVREFIOM_MASK 0x0E000000U +#define DDR_PHY_DX8SL2IOCR_DXVREFIOM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL2IOCR_DXVREFIOM_SHIFT 25 +#define DDR_PHY_DX8SL2IOCR_DXVREFIOM_MASK 0x0E000000U -/*DX IO Mode*/ +/* +* DX IO Mode +*/ #undef DDR_PHY_DX8SL2IOCR_DXIOM_DEFVAL #undef DDR_PHY_DX8SL2IOCR_DXIOM_SHIFT #undef DDR_PHY_DX8SL2IOCR_DXIOM_MASK -#define DDR_PHY_DX8SL2IOCR_DXIOM_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL2IOCR_DXIOM_SHIFT 22 -#define DDR_PHY_DX8SL2IOCR_DXIOM_MASK 0x01C00000U +#define DDR_PHY_DX8SL2IOCR_DXIOM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL2IOCR_DXIOM_SHIFT 22 +#define DDR_PHY_DX8SL2IOCR_DXIOM_MASK 0x01C00000U -/*DX IO Transmitter Mode*/ +/* +* DX IO Transmitter Mode +*/ #undef DDR_PHY_DX8SL2IOCR_DXTXM_DEFVAL #undef DDR_PHY_DX8SL2IOCR_DXTXM_SHIFT #undef DDR_PHY_DX8SL2IOCR_DXTXM_MASK -#define DDR_PHY_DX8SL2IOCR_DXTXM_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL2IOCR_DXTXM_SHIFT 11 -#define DDR_PHY_DX8SL2IOCR_DXTXM_MASK 0x003FF800U +#define DDR_PHY_DX8SL2IOCR_DXTXM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL2IOCR_DXTXM_SHIFT 11 +#define DDR_PHY_DX8SL2IOCR_DXTXM_MASK 0x003FF800U -/*DX IO Receiver Mode*/ +/* +* DX IO Receiver Mode +*/ #undef DDR_PHY_DX8SL2IOCR_DXRXM_DEFVAL #undef DDR_PHY_DX8SL2IOCR_DXRXM_SHIFT #undef DDR_PHY_DX8SL2IOCR_DXRXM_MASK -#define DDR_PHY_DX8SL2IOCR_DXRXM_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL2IOCR_DXRXM_SHIFT 0 -#define DDR_PHY_DX8SL2IOCR_DXRXM_MASK 0x000007FFU +#define DDR_PHY_DX8SL2IOCR_DXRXM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL2IOCR_DXRXM_SHIFT 0 +#define DDR_PHY_DX8SL2IOCR_DXRXM_MASK 0x000007FFU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL3OSC_RESERVED_31_30_DEFVAL #undef DDR_PHY_DX8SL3OSC_RESERVED_31_30_SHIFT #undef DDR_PHY_DX8SL3OSC_RESERVED_31_30_MASK -#define DDR_PHY_DX8SL3OSC_RESERVED_31_30_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL3OSC_RESERVED_31_30_SHIFT 30 -#define DDR_PHY_DX8SL3OSC_RESERVED_31_30_MASK 0xC0000000U +#define DDR_PHY_DX8SL3OSC_RESERVED_31_30_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX8SL3OSC_RESERVED_31_30_MASK 0xC0000000U -/*Enable Clock Gating for DX ddr_clk*/ +/* +* Enable Clock Gating for DX ddr_clk +*/ #undef DDR_PHY_DX8SL3OSC_GATEDXRDCLK_DEFVAL #undef DDR_PHY_DX8SL3OSC_GATEDXRDCLK_SHIFT #undef DDR_PHY_DX8SL3OSC_GATEDXRDCLK_MASK -#define DDR_PHY_DX8SL3OSC_GATEDXRDCLK_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL3OSC_GATEDXRDCLK_SHIFT 28 -#define DDR_PHY_DX8SL3OSC_GATEDXRDCLK_MASK 0x30000000U +#define DDR_PHY_DX8SL3OSC_GATEDXRDCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_GATEDXRDCLK_SHIFT 28 +#define DDR_PHY_DX8SL3OSC_GATEDXRDCLK_MASK 0x30000000U -/*Enable Clock Gating for DX ctl_rd_clk*/ +/* +* Enable Clock Gating for DX ctl_rd_clk +*/ #undef DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_DEFVAL #undef DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_SHIFT #undef DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_MASK -#define DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_SHIFT 26 -#define DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_MASK 0x0C000000U +#define DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_SHIFT 26 +#define DDR_PHY_DX8SL3OSC_GATEDXDDRCLK_MASK 0x0C000000U -/*Enable Clock Gating for DX ctl_clk*/ +/* +* Enable Clock Gating for DX ctl_clk +*/ #undef DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_DEFVAL #undef DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_SHIFT #undef DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_MASK -#define DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_SHIFT 24 -#define DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_MASK 0x03000000U +#define DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_SHIFT 24 +#define DDR_PHY_DX8SL3OSC_GATEDXCTLCLK_MASK 0x03000000U -/*Selects the level to which clocks will be stalled when clock gating is enabled.*/ +/* +* Selects the level to which clocks will be stalled when clock gating is e + * nabled. +*/ #undef DDR_PHY_DX8SL3OSC_CLKLEVEL_DEFVAL #undef DDR_PHY_DX8SL3OSC_CLKLEVEL_SHIFT #undef DDR_PHY_DX8SL3OSC_CLKLEVEL_MASK -#define DDR_PHY_DX8SL3OSC_CLKLEVEL_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL3OSC_CLKLEVEL_SHIFT 22 -#define DDR_PHY_DX8SL3OSC_CLKLEVEL_MASK 0x00C00000U +#define DDR_PHY_DX8SL3OSC_CLKLEVEL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_CLKLEVEL_SHIFT 22 +#define DDR_PHY_DX8SL3OSC_CLKLEVEL_MASK 0x00C00000U -/*Loopback Mode*/ +/* +* Loopback Mode +*/ #undef DDR_PHY_DX8SL3OSC_LBMODE_DEFVAL #undef DDR_PHY_DX8SL3OSC_LBMODE_SHIFT #undef DDR_PHY_DX8SL3OSC_LBMODE_MASK -#define DDR_PHY_DX8SL3OSC_LBMODE_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL3OSC_LBMODE_SHIFT 21 -#define DDR_PHY_DX8SL3OSC_LBMODE_MASK 0x00200000U +#define DDR_PHY_DX8SL3OSC_LBMODE_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_LBMODE_SHIFT 21 +#define DDR_PHY_DX8SL3OSC_LBMODE_MASK 0x00200000U -/*Load GSDQS LCDL with 2x the calibrated GSDQSPRD value*/ +/* +* Load GSDQS LCDL with 2x the calibrated GSDQSPRD value +*/ #undef DDR_PHY_DX8SL3OSC_LBGSDQS_DEFVAL #undef DDR_PHY_DX8SL3OSC_LBGSDQS_SHIFT #undef DDR_PHY_DX8SL3OSC_LBGSDQS_MASK -#define DDR_PHY_DX8SL3OSC_LBGSDQS_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL3OSC_LBGSDQS_SHIFT 20 -#define DDR_PHY_DX8SL3OSC_LBGSDQS_MASK 0x00100000U +#define DDR_PHY_DX8SL3OSC_LBGSDQS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_LBGSDQS_SHIFT 20 +#define DDR_PHY_DX8SL3OSC_LBGSDQS_MASK 0x00100000U -/*Loopback DQS Gating*/ +/* +* Loopback DQS Gating +*/ #undef DDR_PHY_DX8SL3OSC_LBGDQS_DEFVAL #undef DDR_PHY_DX8SL3OSC_LBGDQS_SHIFT #undef DDR_PHY_DX8SL3OSC_LBGDQS_MASK -#define DDR_PHY_DX8SL3OSC_LBGDQS_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL3OSC_LBGDQS_SHIFT 18 -#define DDR_PHY_DX8SL3OSC_LBGDQS_MASK 0x000C0000U +#define DDR_PHY_DX8SL3OSC_LBGDQS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_LBGDQS_SHIFT 18 +#define DDR_PHY_DX8SL3OSC_LBGDQS_MASK 0x000C0000U -/*Loopback DQS Shift*/ +/* +* Loopback DQS Shift +*/ #undef DDR_PHY_DX8SL3OSC_LBDQSS_DEFVAL #undef DDR_PHY_DX8SL3OSC_LBDQSS_SHIFT #undef DDR_PHY_DX8SL3OSC_LBDQSS_MASK -#define DDR_PHY_DX8SL3OSC_LBDQSS_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL3OSC_LBDQSS_SHIFT 17 -#define DDR_PHY_DX8SL3OSC_LBDQSS_MASK 0x00020000U +#define DDR_PHY_DX8SL3OSC_LBDQSS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_LBDQSS_SHIFT 17 +#define DDR_PHY_DX8SL3OSC_LBDQSS_MASK 0x00020000U -/*PHY High-Speed Reset*/ +/* +* PHY High-Speed Reset +*/ #undef DDR_PHY_DX8SL3OSC_PHYHRST_DEFVAL #undef DDR_PHY_DX8SL3OSC_PHYHRST_SHIFT #undef DDR_PHY_DX8SL3OSC_PHYHRST_MASK -#define DDR_PHY_DX8SL3OSC_PHYHRST_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL3OSC_PHYHRST_SHIFT 16 -#define DDR_PHY_DX8SL3OSC_PHYHRST_MASK 0x00010000U +#define DDR_PHY_DX8SL3OSC_PHYHRST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_PHYHRST_SHIFT 16 +#define DDR_PHY_DX8SL3OSC_PHYHRST_MASK 0x00010000U -/*PHY FIFO Reset*/ +/* +* PHY FIFO Reset +*/ #undef DDR_PHY_DX8SL3OSC_PHYFRST_DEFVAL #undef DDR_PHY_DX8SL3OSC_PHYFRST_SHIFT #undef DDR_PHY_DX8SL3OSC_PHYFRST_MASK -#define DDR_PHY_DX8SL3OSC_PHYFRST_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL3OSC_PHYFRST_SHIFT 15 -#define DDR_PHY_DX8SL3OSC_PHYFRST_MASK 0x00008000U +#define DDR_PHY_DX8SL3OSC_PHYFRST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_PHYFRST_SHIFT 15 +#define DDR_PHY_DX8SL3OSC_PHYFRST_MASK 0x00008000U -/*Delay Line Test Start*/ +/* +* Delay Line Test Start +*/ #undef DDR_PHY_DX8SL3OSC_DLTST_DEFVAL #undef DDR_PHY_DX8SL3OSC_DLTST_SHIFT #undef DDR_PHY_DX8SL3OSC_DLTST_MASK -#define DDR_PHY_DX8SL3OSC_DLTST_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL3OSC_DLTST_SHIFT 14 -#define DDR_PHY_DX8SL3OSC_DLTST_MASK 0x00004000U +#define DDR_PHY_DX8SL3OSC_DLTST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_DLTST_SHIFT 14 +#define DDR_PHY_DX8SL3OSC_DLTST_MASK 0x00004000U -/*Delay Line Test Mode*/ +/* +* Delay Line Test Mode +*/ #undef DDR_PHY_DX8SL3OSC_DLTMODE_DEFVAL #undef DDR_PHY_DX8SL3OSC_DLTMODE_SHIFT #undef DDR_PHY_DX8SL3OSC_DLTMODE_MASK -#define DDR_PHY_DX8SL3OSC_DLTMODE_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL3OSC_DLTMODE_SHIFT 13 -#define DDR_PHY_DX8SL3OSC_DLTMODE_MASK 0x00002000U +#define DDR_PHY_DX8SL3OSC_DLTMODE_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_DLTMODE_SHIFT 13 +#define DDR_PHY_DX8SL3OSC_DLTMODE_MASK 0x00002000U -/*Reserved. Caution, do not write to this register field.*/ +/* +* Reserved. Caution, do not write to this register field. +*/ #undef DDR_PHY_DX8SL3OSC_RESERVED_12_11_DEFVAL #undef DDR_PHY_DX8SL3OSC_RESERVED_12_11_SHIFT #undef DDR_PHY_DX8SL3OSC_RESERVED_12_11_MASK -#define DDR_PHY_DX8SL3OSC_RESERVED_12_11_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL3OSC_RESERVED_12_11_SHIFT 11 -#define DDR_PHY_DX8SL3OSC_RESERVED_12_11_MASK 0x00001800U +#define DDR_PHY_DX8SL3OSC_RESERVED_12_11_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_RESERVED_12_11_SHIFT 11 +#define DDR_PHY_DX8SL3OSC_RESERVED_12_11_MASK 0x00001800U -/*Oscillator Mode Write-Data Delay Line Select*/ +/* +* Oscillator Mode Write-Data Delay Line Select +*/ #undef DDR_PHY_DX8SL3OSC_OSCWDDL_DEFVAL #undef DDR_PHY_DX8SL3OSC_OSCWDDL_SHIFT #undef DDR_PHY_DX8SL3OSC_OSCWDDL_MASK -#define DDR_PHY_DX8SL3OSC_OSCWDDL_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL3OSC_OSCWDDL_SHIFT 9 -#define DDR_PHY_DX8SL3OSC_OSCWDDL_MASK 0x00000600U +#define DDR_PHY_DX8SL3OSC_OSCWDDL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_OSCWDDL_SHIFT 9 +#define DDR_PHY_DX8SL3OSC_OSCWDDL_MASK 0x00000600U -/*Reserved. Caution, do not write to this register field.*/ +/* +* Reserved. Caution, do not write to this register field. +*/ #undef DDR_PHY_DX8SL3OSC_RESERVED_8_7_DEFVAL #undef DDR_PHY_DX8SL3OSC_RESERVED_8_7_SHIFT #undef DDR_PHY_DX8SL3OSC_RESERVED_8_7_MASK -#define DDR_PHY_DX8SL3OSC_RESERVED_8_7_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL3OSC_RESERVED_8_7_SHIFT 7 -#define DDR_PHY_DX8SL3OSC_RESERVED_8_7_MASK 0x00000180U +#define DDR_PHY_DX8SL3OSC_RESERVED_8_7_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_RESERVED_8_7_SHIFT 7 +#define DDR_PHY_DX8SL3OSC_RESERVED_8_7_MASK 0x00000180U -/*Oscillator Mode Write-Leveling Delay Line Select*/ +/* +* Oscillator Mode Write-Leveling Delay Line Select +*/ #undef DDR_PHY_DX8SL3OSC_OSCWDL_DEFVAL #undef DDR_PHY_DX8SL3OSC_OSCWDL_SHIFT #undef DDR_PHY_DX8SL3OSC_OSCWDL_MASK -#define DDR_PHY_DX8SL3OSC_OSCWDL_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL3OSC_OSCWDL_SHIFT 5 -#define DDR_PHY_DX8SL3OSC_OSCWDL_MASK 0x00000060U +#define DDR_PHY_DX8SL3OSC_OSCWDL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_OSCWDL_SHIFT 5 +#define DDR_PHY_DX8SL3OSC_OSCWDL_MASK 0x00000060U -/*Oscillator Mode Division*/ +/* +* Oscillator Mode Division +*/ #undef DDR_PHY_DX8SL3OSC_OSCDIV_DEFVAL #undef DDR_PHY_DX8SL3OSC_OSCDIV_SHIFT #undef DDR_PHY_DX8SL3OSC_OSCDIV_MASK -#define DDR_PHY_DX8SL3OSC_OSCDIV_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL3OSC_OSCDIV_SHIFT 1 -#define DDR_PHY_DX8SL3OSC_OSCDIV_MASK 0x0000001EU +#define DDR_PHY_DX8SL3OSC_OSCDIV_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_OSCDIV_SHIFT 1 +#define DDR_PHY_DX8SL3OSC_OSCDIV_MASK 0x0000001EU -/*Oscillator Enable*/ +/* +* Oscillator Enable +*/ #undef DDR_PHY_DX8SL3OSC_OSCEN_DEFVAL #undef DDR_PHY_DX8SL3OSC_OSCEN_SHIFT #undef DDR_PHY_DX8SL3OSC_OSCEN_MASK -#define DDR_PHY_DX8SL3OSC_OSCEN_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL3OSC_OSCEN_SHIFT 0 -#define DDR_PHY_DX8SL3OSC_OSCEN_MASK 0x00000001U +#define DDR_PHY_DX8SL3OSC_OSCEN_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL3OSC_OSCEN_SHIFT 0 +#define DDR_PHY_DX8SL3OSC_OSCEN_MASK 0x00000001U -/*Reserved. Return zeroes on reads.*/ +/* +* PLL Bypass +*/ +#undef DDR_PHY_DX8SL3PLLCR0_PLLBYP_DEFVAL +#undef DDR_PHY_DX8SL3PLLCR0_PLLBYP_SHIFT +#undef DDR_PHY_DX8SL3PLLCR0_PLLBYP_MASK +#define DDR_PHY_DX8SL3PLLCR0_PLLBYP_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL3PLLCR0_PLLBYP_SHIFT 31 +#define DDR_PHY_DX8SL3PLLCR0_PLLBYP_MASK 0x80000000U + +/* +* PLL Reset +*/ +#undef DDR_PHY_DX8SL3PLLCR0_PLLRST_DEFVAL +#undef DDR_PHY_DX8SL3PLLCR0_PLLRST_SHIFT +#undef DDR_PHY_DX8SL3PLLCR0_PLLRST_MASK +#define DDR_PHY_DX8SL3PLLCR0_PLLRST_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL3PLLCR0_PLLRST_SHIFT 30 +#define DDR_PHY_DX8SL3PLLCR0_PLLRST_MASK 0x40000000U + +/* +* PLL Power Down +*/ +#undef DDR_PHY_DX8SL3PLLCR0_PLLPD_DEFVAL +#undef DDR_PHY_DX8SL3PLLCR0_PLLPD_SHIFT +#undef DDR_PHY_DX8SL3PLLCR0_PLLPD_MASK +#define DDR_PHY_DX8SL3PLLCR0_PLLPD_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL3PLLCR0_PLLPD_SHIFT 29 +#define DDR_PHY_DX8SL3PLLCR0_PLLPD_MASK 0x20000000U + +/* +* Reference Stop Mode +*/ +#undef DDR_PHY_DX8SL3PLLCR0_RSTOPM_DEFVAL +#undef DDR_PHY_DX8SL3PLLCR0_RSTOPM_SHIFT +#undef DDR_PHY_DX8SL3PLLCR0_RSTOPM_MASK +#define DDR_PHY_DX8SL3PLLCR0_RSTOPM_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL3PLLCR0_RSTOPM_SHIFT 28 +#define DDR_PHY_DX8SL3PLLCR0_RSTOPM_MASK 0x10000000U + +/* +* PLL Frequency Select +*/ +#undef DDR_PHY_DX8SL3PLLCR0_FRQSEL_DEFVAL +#undef DDR_PHY_DX8SL3PLLCR0_FRQSEL_SHIFT +#undef DDR_PHY_DX8SL3PLLCR0_FRQSEL_MASK +#define DDR_PHY_DX8SL3PLLCR0_FRQSEL_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL3PLLCR0_FRQSEL_SHIFT 24 +#define DDR_PHY_DX8SL3PLLCR0_FRQSEL_MASK 0x0F000000U + +/* +* Relock Mode +*/ +#undef DDR_PHY_DX8SL3PLLCR0_RLOCKM_DEFVAL +#undef DDR_PHY_DX8SL3PLLCR0_RLOCKM_SHIFT +#undef DDR_PHY_DX8SL3PLLCR0_RLOCKM_MASK +#define DDR_PHY_DX8SL3PLLCR0_RLOCKM_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL3PLLCR0_RLOCKM_SHIFT 23 +#define DDR_PHY_DX8SL3PLLCR0_RLOCKM_MASK 0x00800000U + +/* +* Charge Pump Proportional Current Control +*/ +#undef DDR_PHY_DX8SL3PLLCR0_CPPC_DEFVAL +#undef DDR_PHY_DX8SL3PLLCR0_CPPC_SHIFT +#undef DDR_PHY_DX8SL3PLLCR0_CPPC_MASK +#define DDR_PHY_DX8SL3PLLCR0_CPPC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL3PLLCR0_CPPC_SHIFT 17 +#define DDR_PHY_DX8SL3PLLCR0_CPPC_MASK 0x007E0000U + +/* +* Charge Pump Integrating Current Control +*/ +#undef DDR_PHY_DX8SL3PLLCR0_CPIC_DEFVAL +#undef DDR_PHY_DX8SL3PLLCR0_CPIC_SHIFT +#undef DDR_PHY_DX8SL3PLLCR0_CPIC_MASK +#define DDR_PHY_DX8SL3PLLCR0_CPIC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL3PLLCR0_CPIC_SHIFT 13 +#define DDR_PHY_DX8SL3PLLCR0_CPIC_MASK 0x0001E000U + +/* +* Gear Shift +*/ +#undef DDR_PHY_DX8SL3PLLCR0_GSHIFT_DEFVAL +#undef DDR_PHY_DX8SL3PLLCR0_GSHIFT_SHIFT +#undef DDR_PHY_DX8SL3PLLCR0_GSHIFT_MASK +#define DDR_PHY_DX8SL3PLLCR0_GSHIFT_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL3PLLCR0_GSHIFT_SHIFT 12 +#define DDR_PHY_DX8SL3PLLCR0_GSHIFT_MASK 0x00001000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL3PLLCR0_RESERVED_11_9_DEFVAL +#undef DDR_PHY_DX8SL3PLLCR0_RESERVED_11_9_SHIFT +#undef DDR_PHY_DX8SL3PLLCR0_RESERVED_11_9_MASK +#define DDR_PHY_DX8SL3PLLCR0_RESERVED_11_9_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL3PLLCR0_RESERVED_11_9_SHIFT 9 +#define DDR_PHY_DX8SL3PLLCR0_RESERVED_11_9_MASK 0x00000E00U + +/* +* Analog Test Enable (ATOEN) +*/ +#undef DDR_PHY_DX8SL3PLLCR0_ATOEN_DEFVAL +#undef DDR_PHY_DX8SL3PLLCR0_ATOEN_SHIFT +#undef DDR_PHY_DX8SL3PLLCR0_ATOEN_MASK +#define DDR_PHY_DX8SL3PLLCR0_ATOEN_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL3PLLCR0_ATOEN_SHIFT 8 +#define DDR_PHY_DX8SL3PLLCR0_ATOEN_MASK 0x00000100U + +/* +* Analog Test Control +*/ +#undef DDR_PHY_DX8SL3PLLCR0_ATC_DEFVAL +#undef DDR_PHY_DX8SL3PLLCR0_ATC_SHIFT +#undef DDR_PHY_DX8SL3PLLCR0_ATC_MASK +#define DDR_PHY_DX8SL3PLLCR0_ATC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL3PLLCR0_ATC_SHIFT 4 +#define DDR_PHY_DX8SL3PLLCR0_ATC_MASK 0x000000F0U + +/* +* Digital Test Control +*/ +#undef DDR_PHY_DX8SL3PLLCR0_DTC_DEFVAL +#undef DDR_PHY_DX8SL3PLLCR0_DTC_SHIFT +#undef DDR_PHY_DX8SL3PLLCR0_DTC_MASK +#define DDR_PHY_DX8SL3PLLCR0_DTC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL3PLLCR0_DTC_SHIFT 0 +#define DDR_PHY_DX8SL3PLLCR0_DTC_MASK 0x0000000FU + +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_DEFVAL #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_SHIFT #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_MASK -#define DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_SHIFT 25 -#define DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_MASK 0xFE000000U +#define DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_SHIFT 25 +#define DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_MASK 0xFE000000U -/*Read Path Rise-to-Rise Mode*/ +/* +* Read Path Rise-to-Rise Mode +*/ #undef DDR_PHY_DX8SL3DQSCTL_RRRMODE_DEFVAL #undef DDR_PHY_DX8SL3DQSCTL_RRRMODE_SHIFT #undef DDR_PHY_DX8SL3DQSCTL_RRRMODE_MASK -#define DDR_PHY_DX8SL3DQSCTL_RRRMODE_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL3DQSCTL_RRRMODE_SHIFT 24 -#define DDR_PHY_DX8SL3DQSCTL_RRRMODE_MASK 0x01000000U +#define DDR_PHY_DX8SL3DQSCTL_RRRMODE_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL3DQSCTL_RRRMODE_SHIFT 24 +#define DDR_PHY_DX8SL3DQSCTL_RRRMODE_MASK 0x01000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_DEFVAL #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_SHIFT #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_MASK -#define DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_SHIFT 22 -#define DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_MASK 0x00C00000U +#define DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_MASK 0x00C00000U -/*Write Path Rise-to-Rise Mode*/ +/* +* Write Path Rise-to-Rise Mode +*/ #undef DDR_PHY_DX8SL3DQSCTL_WRRMODE_DEFVAL #undef DDR_PHY_DX8SL3DQSCTL_WRRMODE_SHIFT #undef DDR_PHY_DX8SL3DQSCTL_WRRMODE_MASK -#define DDR_PHY_DX8SL3DQSCTL_WRRMODE_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL3DQSCTL_WRRMODE_SHIFT 21 -#define DDR_PHY_DX8SL3DQSCTL_WRRMODE_MASK 0x00200000U +#define DDR_PHY_DX8SL3DQSCTL_WRRMODE_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL3DQSCTL_WRRMODE_SHIFT 21 +#define DDR_PHY_DX8SL3DQSCTL_WRRMODE_MASK 0x00200000U -/*DQS Gate Extension*/ +/* +* DQS Gate Extension +*/ #undef DDR_PHY_DX8SL3DQSCTL_DQSGX_DEFVAL #undef DDR_PHY_DX8SL3DQSCTL_DQSGX_SHIFT #undef DDR_PHY_DX8SL3DQSCTL_DQSGX_MASK -#define DDR_PHY_DX8SL3DQSCTL_DQSGX_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL3DQSCTL_DQSGX_SHIFT 19 -#define DDR_PHY_DX8SL3DQSCTL_DQSGX_MASK 0x00180000U +#define DDR_PHY_DX8SL3DQSCTL_DQSGX_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL3DQSCTL_DQSGX_SHIFT 19 +#define DDR_PHY_DX8SL3DQSCTL_DQSGX_MASK 0x00180000U -/*Low Power PLL Power Down*/ +/* +* Low Power PLL Power Down +*/ #undef DDR_PHY_DX8SL3DQSCTL_LPPLLPD_DEFVAL #undef DDR_PHY_DX8SL3DQSCTL_LPPLLPD_SHIFT #undef DDR_PHY_DX8SL3DQSCTL_LPPLLPD_MASK -#define DDR_PHY_DX8SL3DQSCTL_LPPLLPD_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL3DQSCTL_LPPLLPD_SHIFT 18 -#define DDR_PHY_DX8SL3DQSCTL_LPPLLPD_MASK 0x00040000U +#define DDR_PHY_DX8SL3DQSCTL_LPPLLPD_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL3DQSCTL_LPPLLPD_SHIFT 18 +#define DDR_PHY_DX8SL3DQSCTL_LPPLLPD_MASK 0x00040000U -/*Low Power I/O Power Down*/ +/* +* Low Power I/O Power Down +*/ #undef DDR_PHY_DX8SL3DQSCTL_LPIOPD_DEFVAL #undef DDR_PHY_DX8SL3DQSCTL_LPIOPD_SHIFT #undef DDR_PHY_DX8SL3DQSCTL_LPIOPD_MASK -#define DDR_PHY_DX8SL3DQSCTL_LPIOPD_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL3DQSCTL_LPIOPD_SHIFT 17 -#define DDR_PHY_DX8SL3DQSCTL_LPIOPD_MASK 0x00020000U +#define DDR_PHY_DX8SL3DQSCTL_LPIOPD_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL3DQSCTL_LPIOPD_SHIFT 17 +#define DDR_PHY_DX8SL3DQSCTL_LPIOPD_MASK 0x00020000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_DEFVAL #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_SHIFT #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_MASK -#define DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_SHIFT 15 -#define DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_MASK 0x00018000U +#define DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_SHIFT 15 +#define DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_MASK 0x00018000U -/*QS Counter Enable*/ +/* +* QS Counter Enable +*/ #undef DDR_PHY_DX8SL3DQSCTL_QSCNTEN_DEFVAL #undef DDR_PHY_DX8SL3DQSCTL_QSCNTEN_SHIFT #undef DDR_PHY_DX8SL3DQSCTL_QSCNTEN_MASK -#define DDR_PHY_DX8SL3DQSCTL_QSCNTEN_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL3DQSCTL_QSCNTEN_SHIFT 14 -#define DDR_PHY_DX8SL3DQSCTL_QSCNTEN_MASK 0x00004000U +#define DDR_PHY_DX8SL3DQSCTL_QSCNTEN_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL3DQSCTL_QSCNTEN_SHIFT 14 +#define DDR_PHY_DX8SL3DQSCTL_QSCNTEN_MASK 0x00004000U -/*Unused DQ I/O Mode*/ +/* +* Unused DQ I/O Mode +*/ #undef DDR_PHY_DX8SL3DQSCTL_UDQIOM_DEFVAL #undef DDR_PHY_DX8SL3DQSCTL_UDQIOM_SHIFT #undef DDR_PHY_DX8SL3DQSCTL_UDQIOM_MASK -#define DDR_PHY_DX8SL3DQSCTL_UDQIOM_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL3DQSCTL_UDQIOM_SHIFT 13 -#define DDR_PHY_DX8SL3DQSCTL_UDQIOM_MASK 0x00002000U +#define DDR_PHY_DX8SL3DQSCTL_UDQIOM_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL3DQSCTL_UDQIOM_SHIFT 13 +#define DDR_PHY_DX8SL3DQSCTL_UDQIOM_MASK 0x00002000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_DEFVAL #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_SHIFT #undef DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_MASK -#define DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_SHIFT 10 -#define DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_MASK 0x00001C00U +#define DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_SHIFT 10 +#define DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_MASK 0x00001C00U -/*Data Slew Rate*/ +/* +* Data Slew Rate +*/ #undef DDR_PHY_DX8SL3DQSCTL_DXSR_DEFVAL #undef DDR_PHY_DX8SL3DQSCTL_DXSR_SHIFT #undef DDR_PHY_DX8SL3DQSCTL_DXSR_MASK -#define DDR_PHY_DX8SL3DQSCTL_DXSR_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL3DQSCTL_DXSR_SHIFT 8 -#define DDR_PHY_DX8SL3DQSCTL_DXSR_MASK 0x00000300U +#define DDR_PHY_DX8SL3DQSCTL_DXSR_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL3DQSCTL_DXSR_SHIFT 8 +#define DDR_PHY_DX8SL3DQSCTL_DXSR_MASK 0x00000300U -/*DQS_N Resistor*/ +/* +* DQS_N Resistor +*/ #undef DDR_PHY_DX8SL3DQSCTL_DQSNRES_DEFVAL #undef DDR_PHY_DX8SL3DQSCTL_DQSNRES_SHIFT #undef DDR_PHY_DX8SL3DQSCTL_DQSNRES_MASK -#define DDR_PHY_DX8SL3DQSCTL_DQSNRES_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL3DQSCTL_DQSNRES_SHIFT 4 -#define DDR_PHY_DX8SL3DQSCTL_DQSNRES_MASK 0x000000F0U +#define DDR_PHY_DX8SL3DQSCTL_DQSNRES_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL3DQSCTL_DQSNRES_SHIFT 4 +#define DDR_PHY_DX8SL3DQSCTL_DQSNRES_MASK 0x000000F0U -/*DQS Resistor*/ +/* +* DQS Resistor +*/ #undef DDR_PHY_DX8SL3DQSCTL_DQSRES_DEFVAL #undef DDR_PHY_DX8SL3DQSCTL_DQSRES_SHIFT #undef DDR_PHY_DX8SL3DQSCTL_DQSRES_MASK -#define DDR_PHY_DX8SL3DQSCTL_DQSRES_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL3DQSCTL_DQSRES_SHIFT 0 -#define DDR_PHY_DX8SL3DQSCTL_DQSRES_MASK 0x0000000FU +#define DDR_PHY_DX8SL3DQSCTL_DQSRES_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL3DQSCTL_DQSRES_SHIFT 0 +#define DDR_PHY_DX8SL3DQSCTL_DQSRES_MASK 0x0000000FU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_DEFVAL #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_SHIFT #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_MASK -#define DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_SHIFT 24 -#define DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_MASK 0xFF000000U +#define DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_SHIFT 24 +#define DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_MASK 0xFF000000U -/*Configurable Read Data Enable*/ +/* +* Configurable Read Data Enable +*/ #undef DDR_PHY_DX8SL3DXCTL2_CRDEN_DEFVAL #undef DDR_PHY_DX8SL3DXCTL2_CRDEN_SHIFT #undef DDR_PHY_DX8SL3DXCTL2_CRDEN_MASK -#define DDR_PHY_DX8SL3DXCTL2_CRDEN_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL3DXCTL2_CRDEN_SHIFT 23 -#define DDR_PHY_DX8SL3DXCTL2_CRDEN_MASK 0x00800000U +#define DDR_PHY_DX8SL3DXCTL2_CRDEN_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_CRDEN_SHIFT 23 +#define DDR_PHY_DX8SL3DXCTL2_CRDEN_MASK 0x00800000U -/*OX Extension during Post-amble*/ +/* +* OX Extension during Post-amble +*/ #undef DDR_PHY_DX8SL3DXCTL2_POSOEX_DEFVAL #undef DDR_PHY_DX8SL3DXCTL2_POSOEX_SHIFT #undef DDR_PHY_DX8SL3DXCTL2_POSOEX_MASK -#define DDR_PHY_DX8SL3DXCTL2_POSOEX_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL3DXCTL2_POSOEX_SHIFT 20 -#define DDR_PHY_DX8SL3DXCTL2_POSOEX_MASK 0x00700000U +#define DDR_PHY_DX8SL3DXCTL2_POSOEX_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_POSOEX_SHIFT 20 +#define DDR_PHY_DX8SL3DXCTL2_POSOEX_MASK 0x00700000U -/*OE Extension during Pre-amble*/ +/* +* OE Extension during Pre-amble +*/ #undef DDR_PHY_DX8SL3DXCTL2_PREOEX_DEFVAL #undef DDR_PHY_DX8SL3DXCTL2_PREOEX_SHIFT #undef DDR_PHY_DX8SL3DXCTL2_PREOEX_MASK -#define DDR_PHY_DX8SL3DXCTL2_PREOEX_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL3DXCTL2_PREOEX_SHIFT 18 -#define DDR_PHY_DX8SL3DXCTL2_PREOEX_MASK 0x000C0000U +#define DDR_PHY_DX8SL3DXCTL2_PREOEX_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_PREOEX_SHIFT 18 +#define DDR_PHY_DX8SL3DXCTL2_PREOEX_MASK 0x000C0000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_17_DEFVAL #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_17_SHIFT #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_17_MASK -#define DDR_PHY_DX8SL3DXCTL2_RESERVED_17_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL3DXCTL2_RESERVED_17_SHIFT 17 -#define DDR_PHY_DX8SL3DXCTL2_RESERVED_17_MASK 0x00020000U +#define DDR_PHY_DX8SL3DXCTL2_RESERVED_17_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_RESERVED_17_SHIFT 17 +#define DDR_PHY_DX8SL3DXCTL2_RESERVED_17_MASK 0x00020000U -/*I/O Assisted Gate Select*/ +/* +* I/O Assisted Gate Select +*/ #undef DDR_PHY_DX8SL3DXCTL2_IOAG_DEFVAL #undef DDR_PHY_DX8SL3DXCTL2_IOAG_SHIFT #undef DDR_PHY_DX8SL3DXCTL2_IOAG_MASK -#define DDR_PHY_DX8SL3DXCTL2_IOAG_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL3DXCTL2_IOAG_SHIFT 16 -#define DDR_PHY_DX8SL3DXCTL2_IOAG_MASK 0x00010000U +#define DDR_PHY_DX8SL3DXCTL2_IOAG_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_IOAG_SHIFT 16 +#define DDR_PHY_DX8SL3DXCTL2_IOAG_MASK 0x00010000U -/*I/O Loopback Select*/ +/* +* I/O Loopback Select +*/ #undef DDR_PHY_DX8SL3DXCTL2_IOLB_DEFVAL #undef DDR_PHY_DX8SL3DXCTL2_IOLB_SHIFT #undef DDR_PHY_DX8SL3DXCTL2_IOLB_MASK -#define DDR_PHY_DX8SL3DXCTL2_IOLB_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL3DXCTL2_IOLB_SHIFT 15 -#define DDR_PHY_DX8SL3DXCTL2_IOLB_MASK 0x00008000U +#define DDR_PHY_DX8SL3DXCTL2_IOLB_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_IOLB_SHIFT 15 +#define DDR_PHY_DX8SL3DXCTL2_IOLB_MASK 0x00008000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_DEFVAL #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_SHIFT #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_MASK -#define DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_SHIFT 13 -#define DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_MASK 0x00006000U +#define DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_SHIFT 13 +#define DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_MASK 0x00006000U -/*Low Power Wakeup Threshold*/ +/* +* Low Power Wakeup Threshold +*/ #undef DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_DEFVAL #undef DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_SHIFT #undef DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_MASK -#define DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_SHIFT 9 -#define DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_MASK 0x00001E00U +#define DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_SHIFT 9 +#define DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_MASK 0x00001E00U -/*Read Data Bus Inversion Enable*/ +/* +* Read Data Bus Inversion Enable +*/ #undef DDR_PHY_DX8SL3DXCTL2_RDBI_DEFVAL #undef DDR_PHY_DX8SL3DXCTL2_RDBI_SHIFT #undef DDR_PHY_DX8SL3DXCTL2_RDBI_MASK -#define DDR_PHY_DX8SL3DXCTL2_RDBI_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL3DXCTL2_RDBI_SHIFT 8 -#define DDR_PHY_DX8SL3DXCTL2_RDBI_MASK 0x00000100U +#define DDR_PHY_DX8SL3DXCTL2_RDBI_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_RDBI_SHIFT 8 +#define DDR_PHY_DX8SL3DXCTL2_RDBI_MASK 0x00000100U -/*Write Data Bus Inversion Enable*/ +/* +* Write Data Bus Inversion Enable +*/ #undef DDR_PHY_DX8SL3DXCTL2_WDBI_DEFVAL #undef DDR_PHY_DX8SL3DXCTL2_WDBI_SHIFT #undef DDR_PHY_DX8SL3DXCTL2_WDBI_MASK -#define DDR_PHY_DX8SL3DXCTL2_WDBI_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL3DXCTL2_WDBI_SHIFT 7 -#define DDR_PHY_DX8SL3DXCTL2_WDBI_MASK 0x00000080U +#define DDR_PHY_DX8SL3DXCTL2_WDBI_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_WDBI_SHIFT 7 +#define DDR_PHY_DX8SL3DXCTL2_WDBI_MASK 0x00000080U -/*PUB Read FIFO Bypass*/ +/* +* PUB Read FIFO Bypass +*/ #undef DDR_PHY_DX8SL3DXCTL2_PRFBYP_DEFVAL #undef DDR_PHY_DX8SL3DXCTL2_PRFBYP_SHIFT #undef DDR_PHY_DX8SL3DXCTL2_PRFBYP_MASK -#define DDR_PHY_DX8SL3DXCTL2_PRFBYP_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL3DXCTL2_PRFBYP_SHIFT 6 -#define DDR_PHY_DX8SL3DXCTL2_PRFBYP_MASK 0x00000040U +#define DDR_PHY_DX8SL3DXCTL2_PRFBYP_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_PRFBYP_SHIFT 6 +#define DDR_PHY_DX8SL3DXCTL2_PRFBYP_MASK 0x00000040U -/*DATX8 Receive FIFO Read Mode*/ +/* +* DATX8 Receive FIFO Read Mode +*/ #undef DDR_PHY_DX8SL3DXCTL2_RDMODE_DEFVAL #undef DDR_PHY_DX8SL3DXCTL2_RDMODE_SHIFT #undef DDR_PHY_DX8SL3DXCTL2_RDMODE_MASK -#define DDR_PHY_DX8SL3DXCTL2_RDMODE_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL3DXCTL2_RDMODE_SHIFT 4 -#define DDR_PHY_DX8SL3DXCTL2_RDMODE_MASK 0x00000030U +#define DDR_PHY_DX8SL3DXCTL2_RDMODE_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_RDMODE_SHIFT 4 +#define DDR_PHY_DX8SL3DXCTL2_RDMODE_MASK 0x00000030U -/*Disables the Read FIFO Reset*/ +/* +* Disables the Read FIFO Reset +*/ #undef DDR_PHY_DX8SL3DXCTL2_DISRST_DEFVAL #undef DDR_PHY_DX8SL3DXCTL2_DISRST_SHIFT #undef DDR_PHY_DX8SL3DXCTL2_DISRST_MASK -#define DDR_PHY_DX8SL3DXCTL2_DISRST_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL3DXCTL2_DISRST_SHIFT 3 -#define DDR_PHY_DX8SL3DXCTL2_DISRST_MASK 0x00000008U +#define DDR_PHY_DX8SL3DXCTL2_DISRST_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_DISRST_SHIFT 3 +#define DDR_PHY_DX8SL3DXCTL2_DISRST_MASK 0x00000008U -/*Read DQS Gate I/O Loopback*/ +/* +* Read DQS Gate I/O Loopback +*/ #undef DDR_PHY_DX8SL3DXCTL2_DQSGLB_DEFVAL #undef DDR_PHY_DX8SL3DXCTL2_DQSGLB_SHIFT #undef DDR_PHY_DX8SL3DXCTL2_DQSGLB_MASK -#define DDR_PHY_DX8SL3DXCTL2_DQSGLB_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL3DXCTL2_DQSGLB_SHIFT 1 -#define DDR_PHY_DX8SL3DXCTL2_DQSGLB_MASK 0x00000006U +#define DDR_PHY_DX8SL3DXCTL2_DQSGLB_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_DQSGLB_SHIFT 1 +#define DDR_PHY_DX8SL3DXCTL2_DQSGLB_MASK 0x00000006U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_0_DEFVAL #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_0_SHIFT #undef DDR_PHY_DX8SL3DXCTL2_RESERVED_0_MASK -#define DDR_PHY_DX8SL3DXCTL2_RESERVED_0_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL3DXCTL2_RESERVED_0_SHIFT 0 -#define DDR_PHY_DX8SL3DXCTL2_RESERVED_0_MASK 0x00000001U +#define DDR_PHY_DX8SL3DXCTL2_RESERVED_0_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL3DXCTL2_RESERVED_0_SHIFT 0 +#define DDR_PHY_DX8SL3DXCTL2_RESERVED_0_MASK 0x00000001U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL3IOCR_RESERVED_31_DEFVAL #undef DDR_PHY_DX8SL3IOCR_RESERVED_31_SHIFT #undef DDR_PHY_DX8SL3IOCR_RESERVED_31_MASK -#define DDR_PHY_DX8SL3IOCR_RESERVED_31_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL3IOCR_RESERVED_31_SHIFT 31 -#define DDR_PHY_DX8SL3IOCR_RESERVED_31_MASK 0x80000000U +#define DDR_PHY_DX8SL3IOCR_RESERVED_31_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL3IOCR_RESERVED_31_SHIFT 31 +#define DDR_PHY_DX8SL3IOCR_RESERVED_31_MASK 0x80000000U -/*PVREF_DAC REFSEL range select*/ +/* +* PVREF_DAC REFSEL range select +*/ #undef DDR_PHY_DX8SL3IOCR_DXDACRANGE_DEFVAL #undef DDR_PHY_DX8SL3IOCR_DXDACRANGE_SHIFT #undef DDR_PHY_DX8SL3IOCR_DXDACRANGE_MASK -#define DDR_PHY_DX8SL3IOCR_DXDACRANGE_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL3IOCR_DXDACRANGE_SHIFT 28 -#define DDR_PHY_DX8SL3IOCR_DXDACRANGE_MASK 0x70000000U +#define DDR_PHY_DX8SL3IOCR_DXDACRANGE_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL3IOCR_DXDACRANGE_SHIFT 28 +#define DDR_PHY_DX8SL3IOCR_DXDACRANGE_MASK 0x70000000U -/*IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring*/ +/* +* IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring +*/ #undef DDR_PHY_DX8SL3IOCR_DXVREFIOM_DEFVAL #undef DDR_PHY_DX8SL3IOCR_DXVREFIOM_SHIFT #undef DDR_PHY_DX8SL3IOCR_DXVREFIOM_MASK -#define DDR_PHY_DX8SL3IOCR_DXVREFIOM_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL3IOCR_DXVREFIOM_SHIFT 25 -#define DDR_PHY_DX8SL3IOCR_DXVREFIOM_MASK 0x0E000000U +#define DDR_PHY_DX8SL3IOCR_DXVREFIOM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL3IOCR_DXVREFIOM_SHIFT 25 +#define DDR_PHY_DX8SL3IOCR_DXVREFIOM_MASK 0x0E000000U -/*DX IO Mode*/ +/* +* DX IO Mode +*/ #undef DDR_PHY_DX8SL3IOCR_DXIOM_DEFVAL #undef DDR_PHY_DX8SL3IOCR_DXIOM_SHIFT #undef DDR_PHY_DX8SL3IOCR_DXIOM_MASK -#define DDR_PHY_DX8SL3IOCR_DXIOM_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL3IOCR_DXIOM_SHIFT 22 -#define DDR_PHY_DX8SL3IOCR_DXIOM_MASK 0x01C00000U +#define DDR_PHY_DX8SL3IOCR_DXIOM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL3IOCR_DXIOM_SHIFT 22 +#define DDR_PHY_DX8SL3IOCR_DXIOM_MASK 0x01C00000U -/*DX IO Transmitter Mode*/ +/* +* DX IO Transmitter Mode +*/ #undef DDR_PHY_DX8SL3IOCR_DXTXM_DEFVAL #undef DDR_PHY_DX8SL3IOCR_DXTXM_SHIFT #undef DDR_PHY_DX8SL3IOCR_DXTXM_MASK -#define DDR_PHY_DX8SL3IOCR_DXTXM_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL3IOCR_DXTXM_SHIFT 11 -#define DDR_PHY_DX8SL3IOCR_DXTXM_MASK 0x003FF800U +#define DDR_PHY_DX8SL3IOCR_DXTXM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL3IOCR_DXTXM_SHIFT 11 +#define DDR_PHY_DX8SL3IOCR_DXTXM_MASK 0x003FF800U -/*DX IO Receiver Mode*/ +/* +* DX IO Receiver Mode +*/ #undef DDR_PHY_DX8SL3IOCR_DXRXM_DEFVAL #undef DDR_PHY_DX8SL3IOCR_DXRXM_SHIFT #undef DDR_PHY_DX8SL3IOCR_DXRXM_MASK -#define DDR_PHY_DX8SL3IOCR_DXRXM_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL3IOCR_DXRXM_SHIFT 0 -#define DDR_PHY_DX8SL3IOCR_DXRXM_MASK 0x000007FFU +#define DDR_PHY_DX8SL3IOCR_DXRXM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL3IOCR_DXRXM_SHIFT 0 +#define DDR_PHY_DX8SL3IOCR_DXRXM_MASK 0x000007FFU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL4OSC_RESERVED_31_30_DEFVAL #undef DDR_PHY_DX8SL4OSC_RESERVED_31_30_SHIFT #undef DDR_PHY_DX8SL4OSC_RESERVED_31_30_MASK -#define DDR_PHY_DX8SL4OSC_RESERVED_31_30_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL4OSC_RESERVED_31_30_SHIFT 30 -#define DDR_PHY_DX8SL4OSC_RESERVED_31_30_MASK 0xC0000000U +#define DDR_PHY_DX8SL4OSC_RESERVED_31_30_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_RESERVED_31_30_SHIFT 30 +#define DDR_PHY_DX8SL4OSC_RESERVED_31_30_MASK 0xC0000000U -/*Enable Clock Gating for DX ddr_clk*/ +/* +* Enable Clock Gating for DX ddr_clk +*/ #undef DDR_PHY_DX8SL4OSC_GATEDXRDCLK_DEFVAL #undef DDR_PHY_DX8SL4OSC_GATEDXRDCLK_SHIFT #undef DDR_PHY_DX8SL4OSC_GATEDXRDCLK_MASK -#define DDR_PHY_DX8SL4OSC_GATEDXRDCLK_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL4OSC_GATEDXRDCLK_SHIFT 28 -#define DDR_PHY_DX8SL4OSC_GATEDXRDCLK_MASK 0x30000000U +#define DDR_PHY_DX8SL4OSC_GATEDXRDCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_GATEDXRDCLK_SHIFT 28 +#define DDR_PHY_DX8SL4OSC_GATEDXRDCLK_MASK 0x30000000U -/*Enable Clock Gating for DX ctl_rd_clk*/ +/* +* Enable Clock Gating for DX ctl_rd_clk +*/ #undef DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_DEFVAL #undef DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_SHIFT #undef DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_MASK -#define DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_SHIFT 26 -#define DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_MASK 0x0C000000U +#define DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_SHIFT 26 +#define DDR_PHY_DX8SL4OSC_GATEDXDDRCLK_MASK 0x0C000000U -/*Enable Clock Gating for DX ctl_clk*/ +/* +* Enable Clock Gating for DX ctl_clk +*/ #undef DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_DEFVAL #undef DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_SHIFT #undef DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_MASK -#define DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_SHIFT 24 -#define DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_MASK 0x03000000U +#define DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_SHIFT 24 +#define DDR_PHY_DX8SL4OSC_GATEDXCTLCLK_MASK 0x03000000U -/*Selects the level to which clocks will be stalled when clock gating is enabled.*/ +/* +* Selects the level to which clocks will be stalled when clock gating is e + * nabled. +*/ #undef DDR_PHY_DX8SL4OSC_CLKLEVEL_DEFVAL #undef DDR_PHY_DX8SL4OSC_CLKLEVEL_SHIFT #undef DDR_PHY_DX8SL4OSC_CLKLEVEL_MASK -#define DDR_PHY_DX8SL4OSC_CLKLEVEL_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL4OSC_CLKLEVEL_SHIFT 22 -#define DDR_PHY_DX8SL4OSC_CLKLEVEL_MASK 0x00C00000U +#define DDR_PHY_DX8SL4OSC_CLKLEVEL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_CLKLEVEL_SHIFT 22 +#define DDR_PHY_DX8SL4OSC_CLKLEVEL_MASK 0x00C00000U -/*Loopback Mode*/ +/* +* Loopback Mode +*/ #undef DDR_PHY_DX8SL4OSC_LBMODE_DEFVAL #undef DDR_PHY_DX8SL4OSC_LBMODE_SHIFT #undef DDR_PHY_DX8SL4OSC_LBMODE_MASK -#define DDR_PHY_DX8SL4OSC_LBMODE_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL4OSC_LBMODE_SHIFT 21 -#define DDR_PHY_DX8SL4OSC_LBMODE_MASK 0x00200000U +#define DDR_PHY_DX8SL4OSC_LBMODE_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_LBMODE_SHIFT 21 +#define DDR_PHY_DX8SL4OSC_LBMODE_MASK 0x00200000U -/*Load GSDQS LCDL with 2x the calibrated GSDQSPRD value*/ +/* +* Load GSDQS LCDL with 2x the calibrated GSDQSPRD value +*/ #undef DDR_PHY_DX8SL4OSC_LBGSDQS_DEFVAL #undef DDR_PHY_DX8SL4OSC_LBGSDQS_SHIFT #undef DDR_PHY_DX8SL4OSC_LBGSDQS_MASK -#define DDR_PHY_DX8SL4OSC_LBGSDQS_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL4OSC_LBGSDQS_SHIFT 20 -#define DDR_PHY_DX8SL4OSC_LBGSDQS_MASK 0x00100000U +#define DDR_PHY_DX8SL4OSC_LBGSDQS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_LBGSDQS_SHIFT 20 +#define DDR_PHY_DX8SL4OSC_LBGSDQS_MASK 0x00100000U -/*Loopback DQS Gating*/ +/* +* Loopback DQS Gating +*/ #undef DDR_PHY_DX8SL4OSC_LBGDQS_DEFVAL #undef DDR_PHY_DX8SL4OSC_LBGDQS_SHIFT #undef DDR_PHY_DX8SL4OSC_LBGDQS_MASK -#define DDR_PHY_DX8SL4OSC_LBGDQS_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL4OSC_LBGDQS_SHIFT 18 -#define DDR_PHY_DX8SL4OSC_LBGDQS_MASK 0x000C0000U +#define DDR_PHY_DX8SL4OSC_LBGDQS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_LBGDQS_SHIFT 18 +#define DDR_PHY_DX8SL4OSC_LBGDQS_MASK 0x000C0000U -/*Loopback DQS Shift*/ +/* +* Loopback DQS Shift +*/ #undef DDR_PHY_DX8SL4OSC_LBDQSS_DEFVAL #undef DDR_PHY_DX8SL4OSC_LBDQSS_SHIFT #undef DDR_PHY_DX8SL4OSC_LBDQSS_MASK -#define DDR_PHY_DX8SL4OSC_LBDQSS_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL4OSC_LBDQSS_SHIFT 17 -#define DDR_PHY_DX8SL4OSC_LBDQSS_MASK 0x00020000U +#define DDR_PHY_DX8SL4OSC_LBDQSS_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_LBDQSS_SHIFT 17 +#define DDR_PHY_DX8SL4OSC_LBDQSS_MASK 0x00020000U -/*PHY High-Speed Reset*/ +/* +* PHY High-Speed Reset +*/ #undef DDR_PHY_DX8SL4OSC_PHYHRST_DEFVAL #undef DDR_PHY_DX8SL4OSC_PHYHRST_SHIFT #undef DDR_PHY_DX8SL4OSC_PHYHRST_MASK -#define DDR_PHY_DX8SL4OSC_PHYHRST_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL4OSC_PHYHRST_SHIFT 16 -#define DDR_PHY_DX8SL4OSC_PHYHRST_MASK 0x00010000U +#define DDR_PHY_DX8SL4OSC_PHYHRST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_PHYHRST_SHIFT 16 +#define DDR_PHY_DX8SL4OSC_PHYHRST_MASK 0x00010000U -/*PHY FIFO Reset*/ +/* +* PHY FIFO Reset +*/ #undef DDR_PHY_DX8SL4OSC_PHYFRST_DEFVAL #undef DDR_PHY_DX8SL4OSC_PHYFRST_SHIFT #undef DDR_PHY_DX8SL4OSC_PHYFRST_MASK -#define DDR_PHY_DX8SL4OSC_PHYFRST_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL4OSC_PHYFRST_SHIFT 15 -#define DDR_PHY_DX8SL4OSC_PHYFRST_MASK 0x00008000U +#define DDR_PHY_DX8SL4OSC_PHYFRST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_PHYFRST_SHIFT 15 +#define DDR_PHY_DX8SL4OSC_PHYFRST_MASK 0x00008000U -/*Delay Line Test Start*/ +/* +* Delay Line Test Start +*/ #undef DDR_PHY_DX8SL4OSC_DLTST_DEFVAL #undef DDR_PHY_DX8SL4OSC_DLTST_SHIFT #undef DDR_PHY_DX8SL4OSC_DLTST_MASK -#define DDR_PHY_DX8SL4OSC_DLTST_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL4OSC_DLTST_SHIFT 14 -#define DDR_PHY_DX8SL4OSC_DLTST_MASK 0x00004000U +#define DDR_PHY_DX8SL4OSC_DLTST_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_DLTST_SHIFT 14 +#define DDR_PHY_DX8SL4OSC_DLTST_MASK 0x00004000U -/*Delay Line Test Mode*/ +/* +* Delay Line Test Mode +*/ #undef DDR_PHY_DX8SL4OSC_DLTMODE_DEFVAL #undef DDR_PHY_DX8SL4OSC_DLTMODE_SHIFT #undef DDR_PHY_DX8SL4OSC_DLTMODE_MASK -#define DDR_PHY_DX8SL4OSC_DLTMODE_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL4OSC_DLTMODE_SHIFT 13 -#define DDR_PHY_DX8SL4OSC_DLTMODE_MASK 0x00002000U +#define DDR_PHY_DX8SL4OSC_DLTMODE_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_DLTMODE_SHIFT 13 +#define DDR_PHY_DX8SL4OSC_DLTMODE_MASK 0x00002000U -/*Reserved. Caution, do not write to this register field.*/ +/* +* Reserved. Caution, do not write to this register field. +*/ #undef DDR_PHY_DX8SL4OSC_RESERVED_12_11_DEFVAL #undef DDR_PHY_DX8SL4OSC_RESERVED_12_11_SHIFT #undef DDR_PHY_DX8SL4OSC_RESERVED_12_11_MASK -#define DDR_PHY_DX8SL4OSC_RESERVED_12_11_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL4OSC_RESERVED_12_11_SHIFT 11 -#define DDR_PHY_DX8SL4OSC_RESERVED_12_11_MASK 0x00001800U +#define DDR_PHY_DX8SL4OSC_RESERVED_12_11_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_RESERVED_12_11_SHIFT 11 +#define DDR_PHY_DX8SL4OSC_RESERVED_12_11_MASK 0x00001800U -/*Oscillator Mode Write-Data Delay Line Select*/ +/* +* Oscillator Mode Write-Data Delay Line Select +*/ #undef DDR_PHY_DX8SL4OSC_OSCWDDL_DEFVAL #undef DDR_PHY_DX8SL4OSC_OSCWDDL_SHIFT #undef DDR_PHY_DX8SL4OSC_OSCWDDL_MASK -#define DDR_PHY_DX8SL4OSC_OSCWDDL_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL4OSC_OSCWDDL_SHIFT 9 -#define DDR_PHY_DX8SL4OSC_OSCWDDL_MASK 0x00000600U +#define DDR_PHY_DX8SL4OSC_OSCWDDL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_OSCWDDL_SHIFT 9 +#define DDR_PHY_DX8SL4OSC_OSCWDDL_MASK 0x00000600U -/*Reserved. Caution, do not write to this register field.*/ +/* +* Reserved. Caution, do not write to this register field. +*/ #undef DDR_PHY_DX8SL4OSC_RESERVED_8_7_DEFVAL #undef DDR_PHY_DX8SL4OSC_RESERVED_8_7_SHIFT #undef DDR_PHY_DX8SL4OSC_RESERVED_8_7_MASK -#define DDR_PHY_DX8SL4OSC_RESERVED_8_7_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL4OSC_RESERVED_8_7_SHIFT 7 -#define DDR_PHY_DX8SL4OSC_RESERVED_8_7_MASK 0x00000180U +#define DDR_PHY_DX8SL4OSC_RESERVED_8_7_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_RESERVED_8_7_SHIFT 7 +#define DDR_PHY_DX8SL4OSC_RESERVED_8_7_MASK 0x00000180U -/*Oscillator Mode Write-Leveling Delay Line Select*/ +/* +* Oscillator Mode Write-Leveling Delay Line Select +*/ #undef DDR_PHY_DX8SL4OSC_OSCWDL_DEFVAL #undef DDR_PHY_DX8SL4OSC_OSCWDL_SHIFT #undef DDR_PHY_DX8SL4OSC_OSCWDL_MASK -#define DDR_PHY_DX8SL4OSC_OSCWDL_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL4OSC_OSCWDL_SHIFT 5 -#define DDR_PHY_DX8SL4OSC_OSCWDL_MASK 0x00000060U +#define DDR_PHY_DX8SL4OSC_OSCWDL_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_OSCWDL_SHIFT 5 +#define DDR_PHY_DX8SL4OSC_OSCWDL_MASK 0x00000060U -/*Oscillator Mode Division*/ +/* +* Oscillator Mode Division +*/ #undef DDR_PHY_DX8SL4OSC_OSCDIV_DEFVAL #undef DDR_PHY_DX8SL4OSC_OSCDIV_SHIFT #undef DDR_PHY_DX8SL4OSC_OSCDIV_MASK -#define DDR_PHY_DX8SL4OSC_OSCDIV_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL4OSC_OSCDIV_SHIFT 1 -#define DDR_PHY_DX8SL4OSC_OSCDIV_MASK 0x0000001EU +#define DDR_PHY_DX8SL4OSC_OSCDIV_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_OSCDIV_SHIFT 1 +#define DDR_PHY_DX8SL4OSC_OSCDIV_MASK 0x0000001EU -/*Oscillator Enable*/ +/* +* Oscillator Enable +*/ #undef DDR_PHY_DX8SL4OSC_OSCEN_DEFVAL #undef DDR_PHY_DX8SL4OSC_OSCEN_SHIFT #undef DDR_PHY_DX8SL4OSC_OSCEN_MASK -#define DDR_PHY_DX8SL4OSC_OSCEN_DEFVAL 0x00019FFE -#define DDR_PHY_DX8SL4OSC_OSCEN_SHIFT 0 -#define DDR_PHY_DX8SL4OSC_OSCEN_MASK 0x00000001U +#define DDR_PHY_DX8SL4OSC_OSCEN_DEFVAL 0x00019FFE +#define DDR_PHY_DX8SL4OSC_OSCEN_SHIFT 0 +#define DDR_PHY_DX8SL4OSC_OSCEN_MASK 0x00000001U -/*Reserved. Return zeroes on reads.*/ +/* +* PLL Bypass +*/ +#undef DDR_PHY_DX8SL4PLLCR0_PLLBYP_DEFVAL +#undef DDR_PHY_DX8SL4PLLCR0_PLLBYP_SHIFT +#undef DDR_PHY_DX8SL4PLLCR0_PLLBYP_MASK +#define DDR_PHY_DX8SL4PLLCR0_PLLBYP_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL4PLLCR0_PLLBYP_SHIFT 31 +#define DDR_PHY_DX8SL4PLLCR0_PLLBYP_MASK 0x80000000U + +/* +* PLL Reset +*/ +#undef DDR_PHY_DX8SL4PLLCR0_PLLRST_DEFVAL +#undef DDR_PHY_DX8SL4PLLCR0_PLLRST_SHIFT +#undef DDR_PHY_DX8SL4PLLCR0_PLLRST_MASK +#define DDR_PHY_DX8SL4PLLCR0_PLLRST_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL4PLLCR0_PLLRST_SHIFT 30 +#define DDR_PHY_DX8SL4PLLCR0_PLLRST_MASK 0x40000000U + +/* +* PLL Power Down +*/ +#undef DDR_PHY_DX8SL4PLLCR0_PLLPD_DEFVAL +#undef DDR_PHY_DX8SL4PLLCR0_PLLPD_SHIFT +#undef DDR_PHY_DX8SL4PLLCR0_PLLPD_MASK +#define DDR_PHY_DX8SL4PLLCR0_PLLPD_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL4PLLCR0_PLLPD_SHIFT 29 +#define DDR_PHY_DX8SL4PLLCR0_PLLPD_MASK 0x20000000U + +/* +* Reference Stop Mode +*/ +#undef DDR_PHY_DX8SL4PLLCR0_RSTOPM_DEFVAL +#undef DDR_PHY_DX8SL4PLLCR0_RSTOPM_SHIFT +#undef DDR_PHY_DX8SL4PLLCR0_RSTOPM_MASK +#define DDR_PHY_DX8SL4PLLCR0_RSTOPM_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL4PLLCR0_RSTOPM_SHIFT 28 +#define DDR_PHY_DX8SL4PLLCR0_RSTOPM_MASK 0x10000000U + +/* +* PLL Frequency Select +*/ +#undef DDR_PHY_DX8SL4PLLCR0_FRQSEL_DEFVAL +#undef DDR_PHY_DX8SL4PLLCR0_FRQSEL_SHIFT +#undef DDR_PHY_DX8SL4PLLCR0_FRQSEL_MASK +#define DDR_PHY_DX8SL4PLLCR0_FRQSEL_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL4PLLCR0_FRQSEL_SHIFT 24 +#define DDR_PHY_DX8SL4PLLCR0_FRQSEL_MASK 0x0F000000U + +/* +* Relock Mode +*/ +#undef DDR_PHY_DX8SL4PLLCR0_RLOCKM_DEFVAL +#undef DDR_PHY_DX8SL4PLLCR0_RLOCKM_SHIFT +#undef DDR_PHY_DX8SL4PLLCR0_RLOCKM_MASK +#define DDR_PHY_DX8SL4PLLCR0_RLOCKM_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL4PLLCR0_RLOCKM_SHIFT 23 +#define DDR_PHY_DX8SL4PLLCR0_RLOCKM_MASK 0x00800000U + +/* +* Charge Pump Proportional Current Control +*/ +#undef DDR_PHY_DX8SL4PLLCR0_CPPC_DEFVAL +#undef DDR_PHY_DX8SL4PLLCR0_CPPC_SHIFT +#undef DDR_PHY_DX8SL4PLLCR0_CPPC_MASK +#define DDR_PHY_DX8SL4PLLCR0_CPPC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL4PLLCR0_CPPC_SHIFT 17 +#define DDR_PHY_DX8SL4PLLCR0_CPPC_MASK 0x007E0000U + +/* +* Charge Pump Integrating Current Control +*/ +#undef DDR_PHY_DX8SL4PLLCR0_CPIC_DEFVAL +#undef DDR_PHY_DX8SL4PLLCR0_CPIC_SHIFT +#undef DDR_PHY_DX8SL4PLLCR0_CPIC_MASK +#define DDR_PHY_DX8SL4PLLCR0_CPIC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL4PLLCR0_CPIC_SHIFT 13 +#define DDR_PHY_DX8SL4PLLCR0_CPIC_MASK 0x0001E000U + +/* +* Gear Shift +*/ +#undef DDR_PHY_DX8SL4PLLCR0_GSHIFT_DEFVAL +#undef DDR_PHY_DX8SL4PLLCR0_GSHIFT_SHIFT +#undef DDR_PHY_DX8SL4PLLCR0_GSHIFT_MASK +#define DDR_PHY_DX8SL4PLLCR0_GSHIFT_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL4PLLCR0_GSHIFT_SHIFT 12 +#define DDR_PHY_DX8SL4PLLCR0_GSHIFT_MASK 0x00001000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SL4PLLCR0_RESERVED_11_9_DEFVAL +#undef DDR_PHY_DX8SL4PLLCR0_RESERVED_11_9_SHIFT +#undef DDR_PHY_DX8SL4PLLCR0_RESERVED_11_9_MASK +#define DDR_PHY_DX8SL4PLLCR0_RESERVED_11_9_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL4PLLCR0_RESERVED_11_9_SHIFT 9 +#define DDR_PHY_DX8SL4PLLCR0_RESERVED_11_9_MASK 0x00000E00U + +/* +* Analog Test Enable (ATOEN) +*/ +#undef DDR_PHY_DX8SL4PLLCR0_ATOEN_DEFVAL +#undef DDR_PHY_DX8SL4PLLCR0_ATOEN_SHIFT +#undef DDR_PHY_DX8SL4PLLCR0_ATOEN_MASK +#define DDR_PHY_DX8SL4PLLCR0_ATOEN_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL4PLLCR0_ATOEN_SHIFT 8 +#define DDR_PHY_DX8SL4PLLCR0_ATOEN_MASK 0x00000100U + +/* +* Analog Test Control +*/ +#undef DDR_PHY_DX8SL4PLLCR0_ATC_DEFVAL +#undef DDR_PHY_DX8SL4PLLCR0_ATC_SHIFT +#undef DDR_PHY_DX8SL4PLLCR0_ATC_MASK +#define DDR_PHY_DX8SL4PLLCR0_ATC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL4PLLCR0_ATC_SHIFT 4 +#define DDR_PHY_DX8SL4PLLCR0_ATC_MASK 0x000000F0U + +/* +* Digital Test Control +*/ +#undef DDR_PHY_DX8SL4PLLCR0_DTC_DEFVAL +#undef DDR_PHY_DX8SL4PLLCR0_DTC_SHIFT +#undef DDR_PHY_DX8SL4PLLCR0_DTC_MASK +#define DDR_PHY_DX8SL4PLLCR0_DTC_DEFVAL 0x001C0000 +#define DDR_PHY_DX8SL4PLLCR0_DTC_SHIFT 0 +#define DDR_PHY_DX8SL4PLLCR0_DTC_MASK 0x0000000FU + +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_DEFVAL #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_SHIFT #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_MASK -#define DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_SHIFT 25 -#define DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_MASK 0xFE000000U +#define DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_SHIFT 25 +#define DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_MASK 0xFE000000U -/*Read Path Rise-to-Rise Mode*/ +/* +* Read Path Rise-to-Rise Mode +*/ #undef DDR_PHY_DX8SL4DQSCTL_RRRMODE_DEFVAL #undef DDR_PHY_DX8SL4DQSCTL_RRRMODE_SHIFT #undef DDR_PHY_DX8SL4DQSCTL_RRRMODE_MASK -#define DDR_PHY_DX8SL4DQSCTL_RRRMODE_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL4DQSCTL_RRRMODE_SHIFT 24 -#define DDR_PHY_DX8SL4DQSCTL_RRRMODE_MASK 0x01000000U +#define DDR_PHY_DX8SL4DQSCTL_RRRMODE_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL4DQSCTL_RRRMODE_SHIFT 24 +#define DDR_PHY_DX8SL4DQSCTL_RRRMODE_MASK 0x01000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_DEFVAL #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_SHIFT #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_MASK -#define DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_SHIFT 22 -#define DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_MASK 0x00C00000U +#define DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_MASK 0x00C00000U -/*Write Path Rise-to-Rise Mode*/ +/* +* Write Path Rise-to-Rise Mode +*/ #undef DDR_PHY_DX8SL4DQSCTL_WRRMODE_DEFVAL #undef DDR_PHY_DX8SL4DQSCTL_WRRMODE_SHIFT #undef DDR_PHY_DX8SL4DQSCTL_WRRMODE_MASK -#define DDR_PHY_DX8SL4DQSCTL_WRRMODE_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL4DQSCTL_WRRMODE_SHIFT 21 -#define DDR_PHY_DX8SL4DQSCTL_WRRMODE_MASK 0x00200000U +#define DDR_PHY_DX8SL4DQSCTL_WRRMODE_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL4DQSCTL_WRRMODE_SHIFT 21 +#define DDR_PHY_DX8SL4DQSCTL_WRRMODE_MASK 0x00200000U -/*DQS Gate Extension*/ +/* +* DQS Gate Extension +*/ #undef DDR_PHY_DX8SL4DQSCTL_DQSGX_DEFVAL #undef DDR_PHY_DX8SL4DQSCTL_DQSGX_SHIFT #undef DDR_PHY_DX8SL4DQSCTL_DQSGX_MASK -#define DDR_PHY_DX8SL4DQSCTL_DQSGX_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL4DQSCTL_DQSGX_SHIFT 19 -#define DDR_PHY_DX8SL4DQSCTL_DQSGX_MASK 0x00180000U +#define DDR_PHY_DX8SL4DQSCTL_DQSGX_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL4DQSCTL_DQSGX_SHIFT 19 +#define DDR_PHY_DX8SL4DQSCTL_DQSGX_MASK 0x00180000U -/*Low Power PLL Power Down*/ +/* +* Low Power PLL Power Down +*/ #undef DDR_PHY_DX8SL4DQSCTL_LPPLLPD_DEFVAL #undef DDR_PHY_DX8SL4DQSCTL_LPPLLPD_SHIFT #undef DDR_PHY_DX8SL4DQSCTL_LPPLLPD_MASK -#define DDR_PHY_DX8SL4DQSCTL_LPPLLPD_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL4DQSCTL_LPPLLPD_SHIFT 18 -#define DDR_PHY_DX8SL4DQSCTL_LPPLLPD_MASK 0x00040000U +#define DDR_PHY_DX8SL4DQSCTL_LPPLLPD_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL4DQSCTL_LPPLLPD_SHIFT 18 +#define DDR_PHY_DX8SL4DQSCTL_LPPLLPD_MASK 0x00040000U -/*Low Power I/O Power Down*/ +/* +* Low Power I/O Power Down +*/ #undef DDR_PHY_DX8SL4DQSCTL_LPIOPD_DEFVAL #undef DDR_PHY_DX8SL4DQSCTL_LPIOPD_SHIFT #undef DDR_PHY_DX8SL4DQSCTL_LPIOPD_MASK -#define DDR_PHY_DX8SL4DQSCTL_LPIOPD_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL4DQSCTL_LPIOPD_SHIFT 17 -#define DDR_PHY_DX8SL4DQSCTL_LPIOPD_MASK 0x00020000U +#define DDR_PHY_DX8SL4DQSCTL_LPIOPD_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL4DQSCTL_LPIOPD_SHIFT 17 +#define DDR_PHY_DX8SL4DQSCTL_LPIOPD_MASK 0x00020000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_DEFVAL #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_SHIFT #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_MASK -#define DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_SHIFT 15 -#define DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_MASK 0x00018000U +#define DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_SHIFT 15 +#define DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_MASK 0x00018000U -/*QS Counter Enable*/ +/* +* QS Counter Enable +*/ #undef DDR_PHY_DX8SL4DQSCTL_QSCNTEN_DEFVAL #undef DDR_PHY_DX8SL4DQSCTL_QSCNTEN_SHIFT #undef DDR_PHY_DX8SL4DQSCTL_QSCNTEN_MASK -#define DDR_PHY_DX8SL4DQSCTL_QSCNTEN_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL4DQSCTL_QSCNTEN_SHIFT 14 -#define DDR_PHY_DX8SL4DQSCTL_QSCNTEN_MASK 0x00004000U +#define DDR_PHY_DX8SL4DQSCTL_QSCNTEN_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL4DQSCTL_QSCNTEN_SHIFT 14 +#define DDR_PHY_DX8SL4DQSCTL_QSCNTEN_MASK 0x00004000U -/*Unused DQ I/O Mode*/ +/* +* Unused DQ I/O Mode +*/ #undef DDR_PHY_DX8SL4DQSCTL_UDQIOM_DEFVAL #undef DDR_PHY_DX8SL4DQSCTL_UDQIOM_SHIFT #undef DDR_PHY_DX8SL4DQSCTL_UDQIOM_MASK -#define DDR_PHY_DX8SL4DQSCTL_UDQIOM_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL4DQSCTL_UDQIOM_SHIFT 13 -#define DDR_PHY_DX8SL4DQSCTL_UDQIOM_MASK 0x00002000U +#define DDR_PHY_DX8SL4DQSCTL_UDQIOM_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL4DQSCTL_UDQIOM_SHIFT 13 +#define DDR_PHY_DX8SL4DQSCTL_UDQIOM_MASK 0x00002000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_DEFVAL #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_SHIFT #undef DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_MASK -#define DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_SHIFT 10 -#define DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_MASK 0x00001C00U +#define DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_SHIFT 10 +#define DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_MASK 0x00001C00U -/*Data Slew Rate*/ +/* +* Data Slew Rate +*/ #undef DDR_PHY_DX8SL4DQSCTL_DXSR_DEFVAL #undef DDR_PHY_DX8SL4DQSCTL_DXSR_SHIFT #undef DDR_PHY_DX8SL4DQSCTL_DXSR_MASK -#define DDR_PHY_DX8SL4DQSCTL_DXSR_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL4DQSCTL_DXSR_SHIFT 8 -#define DDR_PHY_DX8SL4DQSCTL_DXSR_MASK 0x00000300U +#define DDR_PHY_DX8SL4DQSCTL_DXSR_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL4DQSCTL_DXSR_SHIFT 8 +#define DDR_PHY_DX8SL4DQSCTL_DXSR_MASK 0x00000300U -/*DQS_N Resistor*/ +/* +* DQS_N Resistor +*/ #undef DDR_PHY_DX8SL4DQSCTL_DQSNRES_DEFVAL #undef DDR_PHY_DX8SL4DQSCTL_DQSNRES_SHIFT #undef DDR_PHY_DX8SL4DQSCTL_DQSNRES_MASK -#define DDR_PHY_DX8SL4DQSCTL_DQSNRES_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL4DQSCTL_DQSNRES_SHIFT 4 -#define DDR_PHY_DX8SL4DQSCTL_DQSNRES_MASK 0x000000F0U +#define DDR_PHY_DX8SL4DQSCTL_DQSNRES_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL4DQSCTL_DQSNRES_SHIFT 4 +#define DDR_PHY_DX8SL4DQSCTL_DQSNRES_MASK 0x000000F0U -/*DQS Resistor*/ +/* +* DQS Resistor +*/ #undef DDR_PHY_DX8SL4DQSCTL_DQSRES_DEFVAL #undef DDR_PHY_DX8SL4DQSCTL_DQSRES_SHIFT #undef DDR_PHY_DX8SL4DQSCTL_DQSRES_MASK -#define DDR_PHY_DX8SL4DQSCTL_DQSRES_DEFVAL 0x01264000 -#define DDR_PHY_DX8SL4DQSCTL_DQSRES_SHIFT 0 -#define DDR_PHY_DX8SL4DQSCTL_DQSRES_MASK 0x0000000FU +#define DDR_PHY_DX8SL4DQSCTL_DQSRES_DEFVAL 0x01264000 +#define DDR_PHY_DX8SL4DQSCTL_DQSRES_SHIFT 0 +#define DDR_PHY_DX8SL4DQSCTL_DQSRES_MASK 0x0000000FU -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_DEFVAL #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_SHIFT #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_MASK -#define DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_SHIFT 24 -#define DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_MASK 0xFF000000U +#define DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_SHIFT 24 +#define DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_MASK 0xFF000000U -/*Configurable Read Data Enable*/ +/* +* Configurable Read Data Enable +*/ #undef DDR_PHY_DX8SL4DXCTL2_CRDEN_DEFVAL #undef DDR_PHY_DX8SL4DXCTL2_CRDEN_SHIFT #undef DDR_PHY_DX8SL4DXCTL2_CRDEN_MASK -#define DDR_PHY_DX8SL4DXCTL2_CRDEN_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL4DXCTL2_CRDEN_SHIFT 23 -#define DDR_PHY_DX8SL4DXCTL2_CRDEN_MASK 0x00800000U +#define DDR_PHY_DX8SL4DXCTL2_CRDEN_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_CRDEN_SHIFT 23 +#define DDR_PHY_DX8SL4DXCTL2_CRDEN_MASK 0x00800000U -/*OX Extension during Post-amble*/ +/* +* OX Extension during Post-amble +*/ #undef DDR_PHY_DX8SL4DXCTL2_POSOEX_DEFVAL #undef DDR_PHY_DX8SL4DXCTL2_POSOEX_SHIFT #undef DDR_PHY_DX8SL4DXCTL2_POSOEX_MASK -#define DDR_PHY_DX8SL4DXCTL2_POSOEX_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL4DXCTL2_POSOEX_SHIFT 20 -#define DDR_PHY_DX8SL4DXCTL2_POSOEX_MASK 0x00700000U +#define DDR_PHY_DX8SL4DXCTL2_POSOEX_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_POSOEX_SHIFT 20 +#define DDR_PHY_DX8SL4DXCTL2_POSOEX_MASK 0x00700000U -/*OE Extension during Pre-amble*/ +/* +* OE Extension during Pre-amble +*/ #undef DDR_PHY_DX8SL4DXCTL2_PREOEX_DEFVAL #undef DDR_PHY_DX8SL4DXCTL2_PREOEX_SHIFT #undef DDR_PHY_DX8SL4DXCTL2_PREOEX_MASK -#define DDR_PHY_DX8SL4DXCTL2_PREOEX_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL4DXCTL2_PREOEX_SHIFT 18 -#define DDR_PHY_DX8SL4DXCTL2_PREOEX_MASK 0x000C0000U +#define DDR_PHY_DX8SL4DXCTL2_PREOEX_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_PREOEX_SHIFT 18 +#define DDR_PHY_DX8SL4DXCTL2_PREOEX_MASK 0x000C0000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_17_DEFVAL #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_17_SHIFT #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_17_MASK -#define DDR_PHY_DX8SL4DXCTL2_RESERVED_17_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL4DXCTL2_RESERVED_17_SHIFT 17 -#define DDR_PHY_DX8SL4DXCTL2_RESERVED_17_MASK 0x00020000U +#define DDR_PHY_DX8SL4DXCTL2_RESERVED_17_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_RESERVED_17_SHIFT 17 +#define DDR_PHY_DX8SL4DXCTL2_RESERVED_17_MASK 0x00020000U -/*I/O Assisted Gate Select*/ +/* +* I/O Assisted Gate Select +*/ #undef DDR_PHY_DX8SL4DXCTL2_IOAG_DEFVAL #undef DDR_PHY_DX8SL4DXCTL2_IOAG_SHIFT #undef DDR_PHY_DX8SL4DXCTL2_IOAG_MASK -#define DDR_PHY_DX8SL4DXCTL2_IOAG_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL4DXCTL2_IOAG_SHIFT 16 -#define DDR_PHY_DX8SL4DXCTL2_IOAG_MASK 0x00010000U +#define DDR_PHY_DX8SL4DXCTL2_IOAG_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_IOAG_SHIFT 16 +#define DDR_PHY_DX8SL4DXCTL2_IOAG_MASK 0x00010000U -/*I/O Loopback Select*/ +/* +* I/O Loopback Select +*/ #undef DDR_PHY_DX8SL4DXCTL2_IOLB_DEFVAL #undef DDR_PHY_DX8SL4DXCTL2_IOLB_SHIFT #undef DDR_PHY_DX8SL4DXCTL2_IOLB_MASK -#define DDR_PHY_DX8SL4DXCTL2_IOLB_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL4DXCTL2_IOLB_SHIFT 15 -#define DDR_PHY_DX8SL4DXCTL2_IOLB_MASK 0x00008000U +#define DDR_PHY_DX8SL4DXCTL2_IOLB_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_IOLB_SHIFT 15 +#define DDR_PHY_DX8SL4DXCTL2_IOLB_MASK 0x00008000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_DEFVAL #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_SHIFT #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_MASK -#define DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_SHIFT 13 -#define DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_MASK 0x00006000U +#define DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_SHIFT 13 +#define DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_MASK 0x00006000U -/*Low Power Wakeup Threshold*/ +/* +* Low Power Wakeup Threshold +*/ #undef DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_DEFVAL #undef DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_SHIFT #undef DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_MASK -#define DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_SHIFT 9 -#define DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_MASK 0x00001E00U +#define DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_SHIFT 9 +#define DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_MASK 0x00001E00U -/*Read Data Bus Inversion Enable*/ +/* +* Read Data Bus Inversion Enable +*/ #undef DDR_PHY_DX8SL4DXCTL2_RDBI_DEFVAL #undef DDR_PHY_DX8SL4DXCTL2_RDBI_SHIFT #undef DDR_PHY_DX8SL4DXCTL2_RDBI_MASK -#define DDR_PHY_DX8SL4DXCTL2_RDBI_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL4DXCTL2_RDBI_SHIFT 8 -#define DDR_PHY_DX8SL4DXCTL2_RDBI_MASK 0x00000100U +#define DDR_PHY_DX8SL4DXCTL2_RDBI_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_RDBI_SHIFT 8 +#define DDR_PHY_DX8SL4DXCTL2_RDBI_MASK 0x00000100U -/*Write Data Bus Inversion Enable*/ +/* +* Write Data Bus Inversion Enable +*/ #undef DDR_PHY_DX8SL4DXCTL2_WDBI_DEFVAL #undef DDR_PHY_DX8SL4DXCTL2_WDBI_SHIFT #undef DDR_PHY_DX8SL4DXCTL2_WDBI_MASK -#define DDR_PHY_DX8SL4DXCTL2_WDBI_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL4DXCTL2_WDBI_SHIFT 7 -#define DDR_PHY_DX8SL4DXCTL2_WDBI_MASK 0x00000080U +#define DDR_PHY_DX8SL4DXCTL2_WDBI_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_WDBI_SHIFT 7 +#define DDR_PHY_DX8SL4DXCTL2_WDBI_MASK 0x00000080U -/*PUB Read FIFO Bypass*/ +/* +* PUB Read FIFO Bypass +*/ #undef DDR_PHY_DX8SL4DXCTL2_PRFBYP_DEFVAL #undef DDR_PHY_DX8SL4DXCTL2_PRFBYP_SHIFT #undef DDR_PHY_DX8SL4DXCTL2_PRFBYP_MASK -#define DDR_PHY_DX8SL4DXCTL2_PRFBYP_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL4DXCTL2_PRFBYP_SHIFT 6 -#define DDR_PHY_DX8SL4DXCTL2_PRFBYP_MASK 0x00000040U +#define DDR_PHY_DX8SL4DXCTL2_PRFBYP_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_PRFBYP_SHIFT 6 +#define DDR_PHY_DX8SL4DXCTL2_PRFBYP_MASK 0x00000040U -/*DATX8 Receive FIFO Read Mode*/ +/* +* DATX8 Receive FIFO Read Mode +*/ #undef DDR_PHY_DX8SL4DXCTL2_RDMODE_DEFVAL #undef DDR_PHY_DX8SL4DXCTL2_RDMODE_SHIFT #undef DDR_PHY_DX8SL4DXCTL2_RDMODE_MASK -#define DDR_PHY_DX8SL4DXCTL2_RDMODE_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL4DXCTL2_RDMODE_SHIFT 4 -#define DDR_PHY_DX8SL4DXCTL2_RDMODE_MASK 0x00000030U +#define DDR_PHY_DX8SL4DXCTL2_RDMODE_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_RDMODE_SHIFT 4 +#define DDR_PHY_DX8SL4DXCTL2_RDMODE_MASK 0x00000030U -/*Disables the Read FIFO Reset*/ +/* +* Disables the Read FIFO Reset +*/ #undef DDR_PHY_DX8SL4DXCTL2_DISRST_DEFVAL #undef DDR_PHY_DX8SL4DXCTL2_DISRST_SHIFT #undef DDR_PHY_DX8SL4DXCTL2_DISRST_MASK -#define DDR_PHY_DX8SL4DXCTL2_DISRST_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL4DXCTL2_DISRST_SHIFT 3 -#define DDR_PHY_DX8SL4DXCTL2_DISRST_MASK 0x00000008U +#define DDR_PHY_DX8SL4DXCTL2_DISRST_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_DISRST_SHIFT 3 +#define DDR_PHY_DX8SL4DXCTL2_DISRST_MASK 0x00000008U -/*Read DQS Gate I/O Loopback*/ +/* +* Read DQS Gate I/O Loopback +*/ #undef DDR_PHY_DX8SL4DXCTL2_DQSGLB_DEFVAL #undef DDR_PHY_DX8SL4DXCTL2_DQSGLB_SHIFT #undef DDR_PHY_DX8SL4DXCTL2_DQSGLB_MASK -#define DDR_PHY_DX8SL4DXCTL2_DQSGLB_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL4DXCTL2_DQSGLB_SHIFT 1 -#define DDR_PHY_DX8SL4DXCTL2_DQSGLB_MASK 0x00000006U +#define DDR_PHY_DX8SL4DXCTL2_DQSGLB_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_DQSGLB_SHIFT 1 +#define DDR_PHY_DX8SL4DXCTL2_DQSGLB_MASK 0x00000006U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_0_DEFVAL #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_0_SHIFT #undef DDR_PHY_DX8SL4DXCTL2_RESERVED_0_MASK -#define DDR_PHY_DX8SL4DXCTL2_RESERVED_0_DEFVAL 0x00141800 -#define DDR_PHY_DX8SL4DXCTL2_RESERVED_0_SHIFT 0 -#define DDR_PHY_DX8SL4DXCTL2_RESERVED_0_MASK 0x00000001U +#define DDR_PHY_DX8SL4DXCTL2_RESERVED_0_DEFVAL 0x00141800 +#define DDR_PHY_DX8SL4DXCTL2_RESERVED_0_SHIFT 0 +#define DDR_PHY_DX8SL4DXCTL2_RESERVED_0_MASK 0x00000001U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SL4IOCR_RESERVED_31_DEFVAL #undef DDR_PHY_DX8SL4IOCR_RESERVED_31_SHIFT #undef DDR_PHY_DX8SL4IOCR_RESERVED_31_MASK -#define DDR_PHY_DX8SL4IOCR_RESERVED_31_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL4IOCR_RESERVED_31_SHIFT 31 -#define DDR_PHY_DX8SL4IOCR_RESERVED_31_MASK 0x80000000U +#define DDR_PHY_DX8SL4IOCR_RESERVED_31_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL4IOCR_RESERVED_31_SHIFT 31 +#define DDR_PHY_DX8SL4IOCR_RESERVED_31_MASK 0x80000000U -/*PVREF_DAC REFSEL range select*/ +/* +* PVREF_DAC REFSEL range select +*/ #undef DDR_PHY_DX8SL4IOCR_DXDACRANGE_DEFVAL #undef DDR_PHY_DX8SL4IOCR_DXDACRANGE_SHIFT #undef DDR_PHY_DX8SL4IOCR_DXDACRANGE_MASK -#define DDR_PHY_DX8SL4IOCR_DXDACRANGE_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL4IOCR_DXDACRANGE_SHIFT 28 -#define DDR_PHY_DX8SL4IOCR_DXDACRANGE_MASK 0x70000000U +#define DDR_PHY_DX8SL4IOCR_DXDACRANGE_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL4IOCR_DXDACRANGE_SHIFT 28 +#define DDR_PHY_DX8SL4IOCR_DXDACRANGE_MASK 0x70000000U -/*IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring*/ +/* +* IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring +*/ #undef DDR_PHY_DX8SL4IOCR_DXVREFIOM_DEFVAL #undef DDR_PHY_DX8SL4IOCR_DXVREFIOM_SHIFT #undef DDR_PHY_DX8SL4IOCR_DXVREFIOM_MASK -#define DDR_PHY_DX8SL4IOCR_DXVREFIOM_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL4IOCR_DXVREFIOM_SHIFT 25 -#define DDR_PHY_DX8SL4IOCR_DXVREFIOM_MASK 0x0E000000U +#define DDR_PHY_DX8SL4IOCR_DXVREFIOM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL4IOCR_DXVREFIOM_SHIFT 25 +#define DDR_PHY_DX8SL4IOCR_DXVREFIOM_MASK 0x0E000000U -/*DX IO Mode*/ +/* +* DX IO Mode +*/ #undef DDR_PHY_DX8SL4IOCR_DXIOM_DEFVAL #undef DDR_PHY_DX8SL4IOCR_DXIOM_SHIFT #undef DDR_PHY_DX8SL4IOCR_DXIOM_MASK -#define DDR_PHY_DX8SL4IOCR_DXIOM_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL4IOCR_DXIOM_SHIFT 22 -#define DDR_PHY_DX8SL4IOCR_DXIOM_MASK 0x01C00000U +#define DDR_PHY_DX8SL4IOCR_DXIOM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL4IOCR_DXIOM_SHIFT 22 +#define DDR_PHY_DX8SL4IOCR_DXIOM_MASK 0x01C00000U -/*DX IO Transmitter Mode*/ +/* +* DX IO Transmitter Mode +*/ #undef DDR_PHY_DX8SL4IOCR_DXTXM_DEFVAL #undef DDR_PHY_DX8SL4IOCR_DXTXM_SHIFT #undef DDR_PHY_DX8SL4IOCR_DXTXM_MASK -#define DDR_PHY_DX8SL4IOCR_DXTXM_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL4IOCR_DXTXM_SHIFT 11 -#define DDR_PHY_DX8SL4IOCR_DXTXM_MASK 0x003FF800U +#define DDR_PHY_DX8SL4IOCR_DXTXM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL4IOCR_DXTXM_SHIFT 11 +#define DDR_PHY_DX8SL4IOCR_DXTXM_MASK 0x003FF800U -/*DX IO Receiver Mode*/ +/* +* DX IO Receiver Mode +*/ #undef DDR_PHY_DX8SL4IOCR_DXRXM_DEFVAL #undef DDR_PHY_DX8SL4IOCR_DXRXM_SHIFT #undef DDR_PHY_DX8SL4IOCR_DXRXM_MASK -#define DDR_PHY_DX8SL4IOCR_DXRXM_DEFVAL 0x00000000 -#define DDR_PHY_DX8SL4IOCR_DXRXM_SHIFT 0 -#define DDR_PHY_DX8SL4IOCR_DXRXM_MASK 0x000007FFU +#define DDR_PHY_DX8SL4IOCR_DXRXM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SL4IOCR_DXRXM_SHIFT 0 +#define DDR_PHY_DX8SL4IOCR_DXRXM_MASK 0x000007FFU -/*Reserved. Return zeroes on reads.*/ +/* +* PLL Bypass +*/ +#undef DDR_PHY_DX8SLBPLLCR0_PLLBYP_DEFVAL +#undef DDR_PHY_DX8SLBPLLCR0_PLLBYP_SHIFT +#undef DDR_PHY_DX8SLBPLLCR0_PLLBYP_MASK +#define DDR_PHY_DX8SLBPLLCR0_PLLBYP_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBPLLCR0_PLLBYP_SHIFT 31 +#define DDR_PHY_DX8SLBPLLCR0_PLLBYP_MASK 0x80000000U + +/* +* PLL Reset +*/ +#undef DDR_PHY_DX8SLBPLLCR0_PLLRST_DEFVAL +#undef DDR_PHY_DX8SLBPLLCR0_PLLRST_SHIFT +#undef DDR_PHY_DX8SLBPLLCR0_PLLRST_MASK +#define DDR_PHY_DX8SLBPLLCR0_PLLRST_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBPLLCR0_PLLRST_SHIFT 30 +#define DDR_PHY_DX8SLBPLLCR0_PLLRST_MASK 0x40000000U + +/* +* PLL Power Down +*/ +#undef DDR_PHY_DX8SLBPLLCR0_PLLPD_DEFVAL +#undef DDR_PHY_DX8SLBPLLCR0_PLLPD_SHIFT +#undef DDR_PHY_DX8SLBPLLCR0_PLLPD_MASK +#define DDR_PHY_DX8SLBPLLCR0_PLLPD_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBPLLCR0_PLLPD_SHIFT 29 +#define DDR_PHY_DX8SLBPLLCR0_PLLPD_MASK 0x20000000U + +/* +* Reference Stop Mode +*/ +#undef DDR_PHY_DX8SLBPLLCR0_RSTOPM_DEFVAL +#undef DDR_PHY_DX8SLBPLLCR0_RSTOPM_SHIFT +#undef DDR_PHY_DX8SLBPLLCR0_RSTOPM_MASK +#define DDR_PHY_DX8SLBPLLCR0_RSTOPM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBPLLCR0_RSTOPM_SHIFT 28 +#define DDR_PHY_DX8SLBPLLCR0_RSTOPM_MASK 0x10000000U + +/* +* PLL Frequency Select +*/ +#undef DDR_PHY_DX8SLBPLLCR0_FRQSEL_DEFVAL +#undef DDR_PHY_DX8SLBPLLCR0_FRQSEL_SHIFT +#undef DDR_PHY_DX8SLBPLLCR0_FRQSEL_MASK +#define DDR_PHY_DX8SLBPLLCR0_FRQSEL_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBPLLCR0_FRQSEL_SHIFT 24 +#define DDR_PHY_DX8SLBPLLCR0_FRQSEL_MASK 0x0F000000U + +/* +* Relock Mode +*/ +#undef DDR_PHY_DX8SLBPLLCR0_RLOCKM_DEFVAL +#undef DDR_PHY_DX8SLBPLLCR0_RLOCKM_SHIFT +#undef DDR_PHY_DX8SLBPLLCR0_RLOCKM_MASK +#define DDR_PHY_DX8SLBPLLCR0_RLOCKM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBPLLCR0_RLOCKM_SHIFT 23 +#define DDR_PHY_DX8SLBPLLCR0_RLOCKM_MASK 0x00800000U + +/* +* Charge Pump Proportional Current Control +*/ +#undef DDR_PHY_DX8SLBPLLCR0_CPPC_DEFVAL +#undef DDR_PHY_DX8SLBPLLCR0_CPPC_SHIFT +#undef DDR_PHY_DX8SLBPLLCR0_CPPC_MASK +#define DDR_PHY_DX8SLBPLLCR0_CPPC_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBPLLCR0_CPPC_SHIFT 17 +#define DDR_PHY_DX8SLBPLLCR0_CPPC_MASK 0x007E0000U + +/* +* Charge Pump Integrating Current Control +*/ +#undef DDR_PHY_DX8SLBPLLCR0_CPIC_DEFVAL +#undef DDR_PHY_DX8SLBPLLCR0_CPIC_SHIFT +#undef DDR_PHY_DX8SLBPLLCR0_CPIC_MASK +#define DDR_PHY_DX8SLBPLLCR0_CPIC_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBPLLCR0_CPIC_SHIFT 13 +#define DDR_PHY_DX8SLBPLLCR0_CPIC_MASK 0x0001E000U + +/* +* Gear Shift +*/ +#undef DDR_PHY_DX8SLBPLLCR0_GSHIFT_DEFVAL +#undef DDR_PHY_DX8SLBPLLCR0_GSHIFT_SHIFT +#undef DDR_PHY_DX8SLBPLLCR0_GSHIFT_MASK +#define DDR_PHY_DX8SLBPLLCR0_GSHIFT_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBPLLCR0_GSHIFT_SHIFT 12 +#define DDR_PHY_DX8SLBPLLCR0_GSHIFT_MASK 0x00001000U + +/* +* Reserved. Return zeroes on reads. +*/ +#undef DDR_PHY_DX8SLBPLLCR0_RESERVED_11_9_DEFVAL +#undef DDR_PHY_DX8SLBPLLCR0_RESERVED_11_9_SHIFT +#undef DDR_PHY_DX8SLBPLLCR0_RESERVED_11_9_MASK +#define DDR_PHY_DX8SLBPLLCR0_RESERVED_11_9_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBPLLCR0_RESERVED_11_9_SHIFT 9 +#define DDR_PHY_DX8SLBPLLCR0_RESERVED_11_9_MASK 0x00000E00U + +/* +* Analog Test Enable (ATOEN) +*/ +#undef DDR_PHY_DX8SLBPLLCR0_ATOEN_DEFVAL +#undef DDR_PHY_DX8SLBPLLCR0_ATOEN_SHIFT +#undef DDR_PHY_DX8SLBPLLCR0_ATOEN_MASK +#define DDR_PHY_DX8SLBPLLCR0_ATOEN_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBPLLCR0_ATOEN_SHIFT 8 +#define DDR_PHY_DX8SLBPLLCR0_ATOEN_MASK 0x00000100U + +/* +* Analog Test Control +*/ +#undef DDR_PHY_DX8SLBPLLCR0_ATC_DEFVAL +#undef DDR_PHY_DX8SLBPLLCR0_ATC_SHIFT +#undef DDR_PHY_DX8SLBPLLCR0_ATC_MASK +#define DDR_PHY_DX8SLBPLLCR0_ATC_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBPLLCR0_ATC_SHIFT 4 +#define DDR_PHY_DX8SLBPLLCR0_ATC_MASK 0x000000F0U + +/* +* Digital Test Control +*/ +#undef DDR_PHY_DX8SLBPLLCR0_DTC_DEFVAL +#undef DDR_PHY_DX8SLBPLLCR0_DTC_SHIFT +#undef DDR_PHY_DX8SLBPLLCR0_DTC_MASK +#define DDR_PHY_DX8SLBPLLCR0_DTC_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBPLLCR0_DTC_SHIFT 0 +#define DDR_PHY_DX8SLBPLLCR0_DTC_MASK 0x0000000FU + +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_DEFVAL #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_SHIFT #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_MASK -#define DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_DEFVAL 0x00000000 -#define DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_SHIFT 25 -#define DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_MASK 0xFE000000U +#define DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_SHIFT 25 +#define DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_MASK 0xFE000000U -/*Read Path Rise-to-Rise Mode*/ +/* +* Read Path Rise-to-Rise Mode +*/ #undef DDR_PHY_DX8SLBDQSCTL_RRRMODE_DEFVAL #undef DDR_PHY_DX8SLBDQSCTL_RRRMODE_SHIFT #undef DDR_PHY_DX8SLBDQSCTL_RRRMODE_MASK -#define DDR_PHY_DX8SLBDQSCTL_RRRMODE_DEFVAL 0x00000000 -#define DDR_PHY_DX8SLBDQSCTL_RRRMODE_SHIFT 24 -#define DDR_PHY_DX8SLBDQSCTL_RRRMODE_MASK 0x01000000U +#define DDR_PHY_DX8SLBDQSCTL_RRRMODE_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBDQSCTL_RRRMODE_SHIFT 24 +#define DDR_PHY_DX8SLBDQSCTL_RRRMODE_MASK 0x01000000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_DEFVAL #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_SHIFT #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_MASK -#define DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_DEFVAL 0x00000000 -#define DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_SHIFT 22 -#define DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_MASK 0x00C00000U +#define DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_SHIFT 22 +#define DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_MASK 0x00C00000U -/*Write Path Rise-to-Rise Mode*/ +/* +* Write Path Rise-to-Rise Mode +*/ #undef DDR_PHY_DX8SLBDQSCTL_WRRMODE_DEFVAL #undef DDR_PHY_DX8SLBDQSCTL_WRRMODE_SHIFT #undef DDR_PHY_DX8SLBDQSCTL_WRRMODE_MASK -#define DDR_PHY_DX8SLBDQSCTL_WRRMODE_DEFVAL 0x00000000 -#define DDR_PHY_DX8SLBDQSCTL_WRRMODE_SHIFT 21 -#define DDR_PHY_DX8SLBDQSCTL_WRRMODE_MASK 0x00200000U +#define DDR_PHY_DX8SLBDQSCTL_WRRMODE_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBDQSCTL_WRRMODE_SHIFT 21 +#define DDR_PHY_DX8SLBDQSCTL_WRRMODE_MASK 0x00200000U -/*DQS Gate Extension*/ +/* +* DQS Gate Extension +*/ #undef DDR_PHY_DX8SLBDQSCTL_DQSGX_DEFVAL #undef DDR_PHY_DX8SLBDQSCTL_DQSGX_SHIFT #undef DDR_PHY_DX8SLBDQSCTL_DQSGX_MASK -#define DDR_PHY_DX8SLBDQSCTL_DQSGX_DEFVAL 0x00000000 -#define DDR_PHY_DX8SLBDQSCTL_DQSGX_SHIFT 19 -#define DDR_PHY_DX8SLBDQSCTL_DQSGX_MASK 0x00180000U +#define DDR_PHY_DX8SLBDQSCTL_DQSGX_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBDQSCTL_DQSGX_SHIFT 19 +#define DDR_PHY_DX8SLBDQSCTL_DQSGX_MASK 0x00180000U -/*Low Power PLL Power Down*/ +/* +* Low Power PLL Power Down +*/ #undef DDR_PHY_DX8SLBDQSCTL_LPPLLPD_DEFVAL #undef DDR_PHY_DX8SLBDQSCTL_LPPLLPD_SHIFT #undef DDR_PHY_DX8SLBDQSCTL_LPPLLPD_MASK -#define DDR_PHY_DX8SLBDQSCTL_LPPLLPD_DEFVAL 0x00000000 -#define DDR_PHY_DX8SLBDQSCTL_LPPLLPD_SHIFT 18 -#define DDR_PHY_DX8SLBDQSCTL_LPPLLPD_MASK 0x00040000U +#define DDR_PHY_DX8SLBDQSCTL_LPPLLPD_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBDQSCTL_LPPLLPD_SHIFT 18 +#define DDR_PHY_DX8SLBDQSCTL_LPPLLPD_MASK 0x00040000U -/*Low Power I/O Power Down*/ +/* +* Low Power I/O Power Down +*/ #undef DDR_PHY_DX8SLBDQSCTL_LPIOPD_DEFVAL #undef DDR_PHY_DX8SLBDQSCTL_LPIOPD_SHIFT #undef DDR_PHY_DX8SLBDQSCTL_LPIOPD_MASK -#define DDR_PHY_DX8SLBDQSCTL_LPIOPD_DEFVAL 0x00000000 -#define DDR_PHY_DX8SLBDQSCTL_LPIOPD_SHIFT 17 -#define DDR_PHY_DX8SLBDQSCTL_LPIOPD_MASK 0x00020000U +#define DDR_PHY_DX8SLBDQSCTL_LPIOPD_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBDQSCTL_LPIOPD_SHIFT 17 +#define DDR_PHY_DX8SLBDQSCTL_LPIOPD_MASK 0x00020000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_DEFVAL #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_SHIFT #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_MASK -#define DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_DEFVAL 0x00000000 -#define DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_SHIFT 15 -#define DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_MASK 0x00018000U +#define DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_SHIFT 15 +#define DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_MASK 0x00018000U -/*QS Counter Enable*/ +/* +* QS Counter Enable +*/ #undef DDR_PHY_DX8SLBDQSCTL_QSCNTEN_DEFVAL #undef DDR_PHY_DX8SLBDQSCTL_QSCNTEN_SHIFT #undef DDR_PHY_DX8SLBDQSCTL_QSCNTEN_MASK -#define DDR_PHY_DX8SLBDQSCTL_QSCNTEN_DEFVAL 0x00000000 -#define DDR_PHY_DX8SLBDQSCTL_QSCNTEN_SHIFT 14 -#define DDR_PHY_DX8SLBDQSCTL_QSCNTEN_MASK 0x00004000U +#define DDR_PHY_DX8SLBDQSCTL_QSCNTEN_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBDQSCTL_QSCNTEN_SHIFT 14 +#define DDR_PHY_DX8SLBDQSCTL_QSCNTEN_MASK 0x00004000U -/*Unused DQ I/O Mode*/ +/* +* Unused DQ I/O Mode +*/ #undef DDR_PHY_DX8SLBDQSCTL_UDQIOM_DEFVAL #undef DDR_PHY_DX8SLBDQSCTL_UDQIOM_SHIFT #undef DDR_PHY_DX8SLBDQSCTL_UDQIOM_MASK -#define DDR_PHY_DX8SLBDQSCTL_UDQIOM_DEFVAL 0x00000000 -#define DDR_PHY_DX8SLBDQSCTL_UDQIOM_SHIFT 13 -#define DDR_PHY_DX8SLBDQSCTL_UDQIOM_MASK 0x00002000U +#define DDR_PHY_DX8SLBDQSCTL_UDQIOM_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBDQSCTL_UDQIOM_SHIFT 13 +#define DDR_PHY_DX8SLBDQSCTL_UDQIOM_MASK 0x00002000U -/*Reserved. Return zeroes on reads.*/ +/* +* Reserved. Return zeroes on reads. +*/ #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_DEFVAL #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_SHIFT #undef DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_MASK -#define DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_DEFVAL 0x00000000 -#define DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_SHIFT 10 -#define DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_MASK 0x00001C00U +#define DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_SHIFT 10 +#define DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_MASK 0x00001C00U -/*Data Slew Rate*/ +/* +* Data Slew Rate +*/ #undef DDR_PHY_DX8SLBDQSCTL_DXSR_DEFVAL #undef DDR_PHY_DX8SLBDQSCTL_DXSR_SHIFT #undef DDR_PHY_DX8SLBDQSCTL_DXSR_MASK -#define DDR_PHY_DX8SLBDQSCTL_DXSR_DEFVAL 0x00000000 -#define DDR_PHY_DX8SLBDQSCTL_DXSR_SHIFT 8 -#define DDR_PHY_DX8SLBDQSCTL_DXSR_MASK 0x00000300U +#define DDR_PHY_DX8SLBDQSCTL_DXSR_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBDQSCTL_DXSR_SHIFT 8 +#define DDR_PHY_DX8SLBDQSCTL_DXSR_MASK 0x00000300U -/*DQS# Resistor*/ +/* +* DQS# Resistor +*/ #undef DDR_PHY_DX8SLBDQSCTL_DQSNRES_DEFVAL #undef DDR_PHY_DX8SLBDQSCTL_DQSNRES_SHIFT #undef DDR_PHY_DX8SLBDQSCTL_DQSNRES_MASK -#define DDR_PHY_DX8SLBDQSCTL_DQSNRES_DEFVAL 0x00000000 -#define DDR_PHY_DX8SLBDQSCTL_DQSNRES_SHIFT 4 -#define DDR_PHY_DX8SLBDQSCTL_DQSNRES_MASK 0x000000F0U +#define DDR_PHY_DX8SLBDQSCTL_DQSNRES_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBDQSCTL_DQSNRES_SHIFT 4 +#define DDR_PHY_DX8SLBDQSCTL_DQSNRES_MASK 0x000000F0U -/*DQS Resistor*/ +/* +* DQS Resistor +*/ #undef DDR_PHY_DX8SLBDQSCTL_DQSRES_DEFVAL #undef DDR_PHY_DX8SLBDQSCTL_DQSRES_SHIFT #undef DDR_PHY_DX8SLBDQSCTL_DQSRES_MASK -#define DDR_PHY_DX8SLBDQSCTL_DQSRES_DEFVAL 0x00000000 -#define DDR_PHY_DX8SLBDQSCTL_DQSRES_SHIFT 0 -#define DDR_PHY_DX8SLBDQSCTL_DQSRES_MASK 0x0000000FU - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_PIR_RESERVED_31_DEFVAL -#undef DDR_PHY_PIR_RESERVED_31_SHIFT -#undef DDR_PHY_PIR_RESERVED_31_MASK -#define DDR_PHY_PIR_RESERVED_31_DEFVAL 0x00000000 -#define DDR_PHY_PIR_RESERVED_31_SHIFT 31 -#define DDR_PHY_PIR_RESERVED_31_MASK 0x80000000U - -/*Impedance Calibration Bypass*/ -#undef DDR_PHY_PIR_ZCALBYP_DEFVAL -#undef DDR_PHY_PIR_ZCALBYP_SHIFT -#undef DDR_PHY_PIR_ZCALBYP_MASK -#define DDR_PHY_PIR_ZCALBYP_DEFVAL 0x00000000 -#define DDR_PHY_PIR_ZCALBYP_SHIFT 30 -#define DDR_PHY_PIR_ZCALBYP_MASK 0x40000000U - -/*Digital Delay Line (DDL) Calibration Pause*/ -#undef DDR_PHY_PIR_DCALPSE_DEFVAL -#undef DDR_PHY_PIR_DCALPSE_SHIFT -#undef DDR_PHY_PIR_DCALPSE_MASK -#define DDR_PHY_PIR_DCALPSE_DEFVAL 0x00000000 -#define DDR_PHY_PIR_DCALPSE_SHIFT 29 -#define DDR_PHY_PIR_DCALPSE_MASK 0x20000000U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_PIR_RESERVED_28_21_DEFVAL -#undef DDR_PHY_PIR_RESERVED_28_21_SHIFT -#undef DDR_PHY_PIR_RESERVED_28_21_MASK -#define DDR_PHY_PIR_RESERVED_28_21_DEFVAL 0x00000000 -#define DDR_PHY_PIR_RESERVED_28_21_SHIFT 21 -#define DDR_PHY_PIR_RESERVED_28_21_MASK 0x1FE00000U - -/*Write DQS2DQ Training*/ -#undef DDR_PHY_PIR_DQS2DQ_DEFVAL -#undef DDR_PHY_PIR_DQS2DQ_SHIFT -#undef DDR_PHY_PIR_DQS2DQ_MASK -#define DDR_PHY_PIR_DQS2DQ_DEFVAL 0x00000000 -#define DDR_PHY_PIR_DQS2DQ_SHIFT 20 -#define DDR_PHY_PIR_DQS2DQ_MASK 0x00100000U - -/*RDIMM Initialization*/ -#undef DDR_PHY_PIR_RDIMMINIT_DEFVAL -#undef DDR_PHY_PIR_RDIMMINIT_SHIFT -#undef DDR_PHY_PIR_RDIMMINIT_MASK -#define DDR_PHY_PIR_RDIMMINIT_DEFVAL 0x00000000 -#define DDR_PHY_PIR_RDIMMINIT_SHIFT 19 -#define DDR_PHY_PIR_RDIMMINIT_MASK 0x00080000U - -/*Controller DRAM Initialization*/ -#undef DDR_PHY_PIR_CTLDINIT_DEFVAL -#undef DDR_PHY_PIR_CTLDINIT_SHIFT -#undef DDR_PHY_PIR_CTLDINIT_MASK -#define DDR_PHY_PIR_CTLDINIT_DEFVAL 0x00000000 -#define DDR_PHY_PIR_CTLDINIT_SHIFT 18 -#define DDR_PHY_PIR_CTLDINIT_MASK 0x00040000U - -/*VREF Training*/ -#undef DDR_PHY_PIR_VREF_DEFVAL -#undef DDR_PHY_PIR_VREF_SHIFT -#undef DDR_PHY_PIR_VREF_MASK -#define DDR_PHY_PIR_VREF_DEFVAL 0x00000000 -#define DDR_PHY_PIR_VREF_SHIFT 17 -#define DDR_PHY_PIR_VREF_MASK 0x00020000U - -/*Static Read Training*/ -#undef DDR_PHY_PIR_SRD_DEFVAL -#undef DDR_PHY_PIR_SRD_SHIFT -#undef DDR_PHY_PIR_SRD_MASK -#define DDR_PHY_PIR_SRD_DEFVAL 0x00000000 -#define DDR_PHY_PIR_SRD_SHIFT 16 -#define DDR_PHY_PIR_SRD_MASK 0x00010000U - -/*Write Data Eye Training*/ -#undef DDR_PHY_PIR_WREYE_DEFVAL -#undef DDR_PHY_PIR_WREYE_SHIFT -#undef DDR_PHY_PIR_WREYE_MASK -#define DDR_PHY_PIR_WREYE_DEFVAL 0x00000000 -#define DDR_PHY_PIR_WREYE_SHIFT 15 -#define DDR_PHY_PIR_WREYE_MASK 0x00008000U - -/*Read Data Eye Training*/ -#undef DDR_PHY_PIR_RDEYE_DEFVAL -#undef DDR_PHY_PIR_RDEYE_SHIFT -#undef DDR_PHY_PIR_RDEYE_MASK -#define DDR_PHY_PIR_RDEYE_DEFVAL 0x00000000 -#define DDR_PHY_PIR_RDEYE_SHIFT 14 -#define DDR_PHY_PIR_RDEYE_MASK 0x00004000U - -/*Write Data Bit Deskew*/ -#undef DDR_PHY_PIR_WRDSKW_DEFVAL -#undef DDR_PHY_PIR_WRDSKW_SHIFT -#undef DDR_PHY_PIR_WRDSKW_MASK -#define DDR_PHY_PIR_WRDSKW_DEFVAL 0x00000000 -#define DDR_PHY_PIR_WRDSKW_SHIFT 13 -#define DDR_PHY_PIR_WRDSKW_MASK 0x00002000U - -/*Read Data Bit Deskew*/ -#undef DDR_PHY_PIR_RDDSKW_DEFVAL -#undef DDR_PHY_PIR_RDDSKW_SHIFT -#undef DDR_PHY_PIR_RDDSKW_MASK -#define DDR_PHY_PIR_RDDSKW_DEFVAL 0x00000000 -#define DDR_PHY_PIR_RDDSKW_SHIFT 12 -#define DDR_PHY_PIR_RDDSKW_MASK 0x00001000U - -/*Write Leveling Adjust*/ -#undef DDR_PHY_PIR_WLADJ_DEFVAL -#undef DDR_PHY_PIR_WLADJ_SHIFT -#undef DDR_PHY_PIR_WLADJ_MASK -#define DDR_PHY_PIR_WLADJ_DEFVAL 0x00000000 -#define DDR_PHY_PIR_WLADJ_SHIFT 11 -#define DDR_PHY_PIR_WLADJ_MASK 0x00000800U - -/*Read DQS Gate Training*/ -#undef DDR_PHY_PIR_QSGATE_DEFVAL -#undef DDR_PHY_PIR_QSGATE_SHIFT -#undef DDR_PHY_PIR_QSGATE_MASK -#define DDR_PHY_PIR_QSGATE_DEFVAL 0x00000000 -#define DDR_PHY_PIR_QSGATE_SHIFT 10 -#define DDR_PHY_PIR_QSGATE_MASK 0x00000400U - -/*Write Leveling*/ -#undef DDR_PHY_PIR_WL_DEFVAL -#undef DDR_PHY_PIR_WL_SHIFT -#undef DDR_PHY_PIR_WL_MASK -#define DDR_PHY_PIR_WL_DEFVAL 0x00000000 -#define DDR_PHY_PIR_WL_SHIFT 9 -#define DDR_PHY_PIR_WL_MASK 0x00000200U - -/*DRAM Initialization*/ -#undef DDR_PHY_PIR_DRAMINIT_DEFVAL -#undef DDR_PHY_PIR_DRAMINIT_SHIFT -#undef DDR_PHY_PIR_DRAMINIT_MASK -#define DDR_PHY_PIR_DRAMINIT_DEFVAL 0x00000000 -#define DDR_PHY_PIR_DRAMINIT_SHIFT 8 -#define DDR_PHY_PIR_DRAMINIT_MASK 0x00000100U - -/*DRAM Reset (DDR3/DDR4/LPDDR4 Only)*/ -#undef DDR_PHY_PIR_DRAMRST_DEFVAL -#undef DDR_PHY_PIR_DRAMRST_SHIFT -#undef DDR_PHY_PIR_DRAMRST_MASK -#define DDR_PHY_PIR_DRAMRST_DEFVAL 0x00000000 -#define DDR_PHY_PIR_DRAMRST_SHIFT 7 -#define DDR_PHY_PIR_DRAMRST_MASK 0x00000080U - -/*PHY Reset*/ -#undef DDR_PHY_PIR_PHYRST_DEFVAL -#undef DDR_PHY_PIR_PHYRST_SHIFT -#undef DDR_PHY_PIR_PHYRST_MASK -#define DDR_PHY_PIR_PHYRST_DEFVAL 0x00000000 -#define DDR_PHY_PIR_PHYRST_SHIFT 6 -#define DDR_PHY_PIR_PHYRST_MASK 0x00000040U - -/*Digital Delay Line (DDL) Calibration*/ -#undef DDR_PHY_PIR_DCAL_DEFVAL -#undef DDR_PHY_PIR_DCAL_SHIFT -#undef DDR_PHY_PIR_DCAL_MASK -#define DDR_PHY_PIR_DCAL_DEFVAL 0x00000000 -#define DDR_PHY_PIR_DCAL_SHIFT 5 -#define DDR_PHY_PIR_DCAL_MASK 0x00000020U - -/*PLL Initialiazation*/ -#undef DDR_PHY_PIR_PLLINIT_DEFVAL -#undef DDR_PHY_PIR_PLLINIT_SHIFT -#undef DDR_PHY_PIR_PLLINIT_MASK -#define DDR_PHY_PIR_PLLINIT_DEFVAL 0x00000000 -#define DDR_PHY_PIR_PLLINIT_SHIFT 4 -#define DDR_PHY_PIR_PLLINIT_MASK 0x00000010U - -/*Reserved. Return zeroes on reads.*/ -#undef DDR_PHY_PIR_RESERVED_3_DEFVAL -#undef DDR_PHY_PIR_RESERVED_3_SHIFT -#undef DDR_PHY_PIR_RESERVED_3_MASK -#define DDR_PHY_PIR_RESERVED_3_DEFVAL 0x00000000 -#define DDR_PHY_PIR_RESERVED_3_SHIFT 3 -#define DDR_PHY_PIR_RESERVED_3_MASK 0x00000008U - -/*CA Training*/ -#undef DDR_PHY_PIR_CA_DEFVAL -#undef DDR_PHY_PIR_CA_SHIFT -#undef DDR_PHY_PIR_CA_MASK -#define DDR_PHY_PIR_CA_DEFVAL 0x00000000 -#define DDR_PHY_PIR_CA_SHIFT 2 -#define DDR_PHY_PIR_CA_MASK 0x00000004U - -/*Impedance Calibration*/ -#undef DDR_PHY_PIR_ZCAL_DEFVAL -#undef DDR_PHY_PIR_ZCAL_SHIFT -#undef DDR_PHY_PIR_ZCAL_MASK -#define DDR_PHY_PIR_ZCAL_DEFVAL 0x00000000 -#define DDR_PHY_PIR_ZCAL_SHIFT 1 -#define DDR_PHY_PIR_ZCAL_MASK 0x00000002U - -/*Initialization Trigger*/ -#undef DDR_PHY_PIR_INIT_DEFVAL -#undef DDR_PHY_PIR_INIT_SHIFT -#undef DDR_PHY_PIR_INIT_MASK -#define DDR_PHY_PIR_INIT_DEFVAL 0x00000000 -#define DDR_PHY_PIR_INIT_SHIFT 0 -#define DDR_PHY_PIR_INIT_MASK 0x00000001U +#define DDR_PHY_DX8SLBDQSCTL_DQSRES_DEFVAL 0x00000000 +#define DDR_PHY_DX8SLBDQSCTL_DQSRES_SHIFT 0 +#define DDR_PHY_DX8SLBDQSCTL_DQSRES_MASK 0x0000000FU #undef IOU_SLCR_MIO_PIN_0_OFFSET #define IOU_SLCR_MIO_PIN_0_OFFSET 0XFF180000 #undef IOU_SLCR_MIO_PIN_1_OFFSET @@ -17120,7308 +21593,9482 @@ #undef IOU_SLCR_MIO_LOOPBACK_OFFSET #define IOU_SLCR_MIO_LOOPBACK_OFFSET 0XFF180200 -/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out- (QSPI Clock)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out- + * (QSPI Clock) +*/ #undef IOU_SLCR_MIO_PIN_0_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_0_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_0_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_0_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_0_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_0_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_0_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_0_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_0_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_0_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_0_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_0_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_0_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_0_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_0_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_0_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_0_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_0_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[0]- (Test Scan Port) = test_scan, Outp - t, test_scan_out[0]- (Test Scan Port) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[0]- (Test Scan Port) = test_scan, Output, test_scan_out[0 + * ]- (Test Scan Port) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_0_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_0_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_0_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_0_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_0_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_0_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_0_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_0_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_0_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[0]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[0]- (GPIO bank 0) 1= can - , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa - ) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Cloc - ) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_ - lk- (Trace Port Clock)*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[0]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[0]- (GPIO bank 0) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG + * TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sc + * lk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Out + * put, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_c + * lk- (Trace Port Clock) +*/ #undef IOU_SLCR_MIO_PIN_0_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_0_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_0_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_0_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_0_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_0_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_0_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_0_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_0_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (QSPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Data - us)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (Q + * SPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Databus) +*/ #undef IOU_SLCR_MIO_PIN_1_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_1_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_1_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_1_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_1_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_1_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_1_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_1_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_1_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_1_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_1_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_1_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_1_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_1_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_1_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_1_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_1_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_1_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[1]- (Test Scan Port) = test_scan, Outp - t, test_scan_out[1]- (Test Scan Port) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[1]- (Test Scan Port) = test_scan, Output, test_scan_out[1 + * ]- (Test Scan Port) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_1_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_1_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_1_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_1_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_1_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_1_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_1_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_1_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_1_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[1]- (GPIO bank 0) 1= can - , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal - 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_o - t- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control - Signal)*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[1]- (GPIO bank 0) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG + * TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc3, Ou + * tput, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART + * receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control + * Signal) +*/ #undef IOU_SLCR_MIO_PIN_1_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_1_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_1_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_1_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_1_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_1_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_1_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_1_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_1_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI + * Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus) +*/ #undef IOU_SLCR_MIO_PIN_2_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_2_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_2_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_2_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_2_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_2_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_2_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_2_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_2_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_2_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_2_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_2_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_2_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_2_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_2_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_2_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_2_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_2_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[2]- (Test Scan Port) = test_scan, Outp - t, test_scan_out[2]- (Test Scan Port) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[2]- (Test Scan Port) = test_scan, Output, test_scan_out[2 + * ]- (Test Scan Port) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_2_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_2_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_2_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_2_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_2_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_2_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_2_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_2_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_2_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[2]- (GPIO bank 0) 1= can - , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal - 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc2, Input, ttc2_clk_in - (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[0]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[2]- (GPIO bank 0) 1= can0, Input, can0_phy_ + * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + * , Output, i2c0_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTAG + * TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc2, I + * nput, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver se + * rial input) 7= trace, Output, tracedq[0]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_2_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_2_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_2_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_2_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_2_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_2_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_2_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_2_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_2_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI + * Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus) +*/ #undef IOU_SLCR_MIO_PIN_3_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_3_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_3_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_3_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_3_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_3_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_3_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_3_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_3_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_3_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_3_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_3_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_3_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_3_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_3_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_3_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_3_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_3_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[3]- (Test Scan Port) = test_scan, Outp - t, test_scan_out[3]- (Test Scan Port) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[3]- (Test Scan Port) = test_scan, Output, test_scan_out[3 + * ]- (Test Scan Port) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_3_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_3_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_3_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_3_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_3_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_3_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_3_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_3_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_3_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[3]- (GPIO bank 0) 1= can - , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa - ) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0 - - (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial - output) 7= trace, Output, tracedq[1]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[3]- (GPIO bank 0) 1= can0, Output, can0_phy + * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + * 0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG + * TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output + * , spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- + * (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial + * output) 7= trace, Output, tracedq[1]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_3_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_3_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_3_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_3_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_3_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_3_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_3_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_3_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_3_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- (QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Data - us)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- ( + * QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Databus) +*/ #undef IOU_SLCR_MIO_PIN_4_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_4_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_4_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_4_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_4_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_4_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_4_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_4_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_4_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_4_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_4_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_4_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_4_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_4_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_4_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_4_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_4_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_4_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[4]- (Test Scan Port) = test_scan, Outp - t, test_scan_out[4]- (Test Scan Port) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[4]- (Test Scan Port) = test_scan, Output, test_scan_out[4 + * ]- (Test Scan Port) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_4_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_4_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_4_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_4_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_4_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_4_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_4_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_4_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_4_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[4]- (GPIO bank 0) 1= can - , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa - ) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_s - - (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, - utput, tracedq[2]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[4]- (GPIO bank 0) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Wa + * tch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi + * 0, Output, spi0_so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Cloc + * k) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, O + * utput, tracedq[2]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_4_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_4_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_4_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_4_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_4_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_4_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_4_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_4_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_4_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out- (QSPI Slave Select)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out- + * (QSPI Slave Select) +*/ #undef IOU_SLCR_MIO_PIN_5_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_5_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_5_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_5_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_5_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_5_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_5_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_5_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_5_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_5_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_5_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_5_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_5_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_5_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_5_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_5_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_5_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_5_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[5]- (Test Scan Port) = test_scan, Outp - t, test_scan_out[5]- (Test Scan Port) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[5]- (Test Scan Port) = test_scan, Output, test_scan_out[5 + * ]- (Test Scan Port) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_5_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_5_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_5_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_5_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_5_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_5_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_5_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_5_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_5_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[5]- (GPIO bank 0) 1= can - , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal - 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi0 - si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7 - trace, Output, tracedq[3]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[5]- (GPIO bank 0) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (W + * atch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= + * spi0, Input, spi0_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC + * Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= + * trace, Output, tracedq[3]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_5_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_5_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_5_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_5_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_5_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_5_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_5_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_5_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_5_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_clk_for_lpbk- (QSPI Clock to be fed-back)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_clk_for_l + * pbk- (QSPI Clock to be fed-back) +*/ #undef IOU_SLCR_MIO_PIN_6_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_6_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_6_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_6_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_6_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_6_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_6_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_6_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_6_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_6_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_6_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_6_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_6_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_6_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_6_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_6_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_6_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_6_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[6]- (Test Scan Port) = test_scan, Outp - t, test_scan_out[6]- (Test Scan Port) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[6]- (Test Scan Port) = test_scan, Output, test_scan_out[6 + * ]- (Test Scan Port) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_6_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_6_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_6_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_6_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_6_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_6_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_6_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_6_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_6_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[6]- (GPIO bank 0) 1= can - , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal - 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1 - sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, - Output, tracedq[4]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[6]- (GPIO bank 0) 1= can0, Input, can0_phy_ + * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + * , Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Wat + * ch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= s + * pi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TT + * C Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, + * Output, tracedq[4]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_6_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_6_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_6_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_6_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_6_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_6_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_6_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_6_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_6_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out_upper- (QSPI Slave Select upper)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out_ + * upper- (QSPI Slave Select upper) +*/ #undef IOU_SLCR_MIO_PIN_7_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_7_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_7_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_7_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_7_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_7_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_7_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_7_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_7_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_7_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_7_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_7_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_7_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_7_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_7_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_7_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_7_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_7_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[7]- (Test Scan Port) = test_scan, Outp - t, test_scan_out[7]- (Test Scan Port) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[7]- (Test Scan Port) = test_scan, Output, test_scan_out[7 + * ]- (Test Scan Port) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_7_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_7_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_7_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_7_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_7_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_7_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_7_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_7_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_7_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[7]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[7]- (GPIO bank 0) 1= can - , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa - ) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= - tc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, - racedq[5]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[7]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[7]- (GPIO bank 0) 1= can0, Output, can0_phy + * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + * 0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- ( + * Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Ma + * ster Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua + * 0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, t + * racedq[5]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_7_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_7_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_7_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_7_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_7_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_7_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_7_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_7_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_7_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[0]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe - [0]- (QSPI Upper Databus)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[0 + * ]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[0]- (QSPI Upper D + * atabus) +*/ #undef IOU_SLCR_MIO_PIN_8_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_8_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_8_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_8_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_8_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_8_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_8_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_8_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_8_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_8_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_8_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_8_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_8_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_8_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_8_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_8_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_8_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_8_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[8]- (Test Scan Port) = test_scan, Outp - t, test_scan_out[8]- (Test Scan Port) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[8]- (Test Scan Port) = test_scan, Output, test_scan_out[8 + * ]- (Test Scan Port) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_8_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_8_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_8_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_8_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_8_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_8_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_8_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_8_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_8_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[8]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[8]- (GPIO bank 0) 1= can - , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa - ) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc - , Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Tr - ce Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[8]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[8]- (GPIO bank 0) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Wa + * tch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Maste + * r Selects) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_ + * txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Tra + * ce Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_8_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_8_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_8_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_8_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_8_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_8_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_8_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_8_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_8_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[1]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe - [1]- (QSPI Upper Databus)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[1 + * ]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[1]- (QSPI Upper D + * atabus) +*/ #undef IOU_SLCR_MIO_PIN_9_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_9_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_9_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_9_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_9_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_9_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_9_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_9_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_9_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NAND chip enable)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NA + * ND chip enable) +*/ #undef IOU_SLCR_MIO_PIN_9_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_9_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_9_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_9_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_9_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_9_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_9_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_9_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_9_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[9]- (Test Scan Port) = test_scan, Outp - t, test_scan_out[9]- (Test Scan Port) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[9]- (Test Scan Port) = test_scan, Output, test_scan_out[9 + * ]- (Test Scan Port) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_9_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_9_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_9_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_9_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_9_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_9_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_9_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_9_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_9_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[9]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[9]- (GPIO bank 0) 1= can - , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal - 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, - utput, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (U - RT receiver serial input) 7= trace, Output, tracedq[7]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[9]- (GPIO bank 0) 0= g + * pio0, Output, gpio_0_pin_out[9]- (GPIO bank 0) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (W + * atch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master S + * elects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc3, + * Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UA + * RT receiver serial input) 7= trace, Output, tracedq[7]- (Trace Port Data + * bus) +*/ #undef IOU_SLCR_MIO_PIN_9_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_9_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_9_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_9_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_9_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_9_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_9_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_9_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_9_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[2]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe - [2]- (QSPI Upper Databus)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[2 + * ]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[2]- (QSPI Upper D + * atabus) +*/ #undef IOU_SLCR_MIO_PIN_10_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_10_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_10_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_10_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_10_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_10_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_10_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_10_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_10_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (NAND Ready/Busy)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (N + * AND Ready/Busy) +*/ #undef IOU_SLCR_MIO_PIN_10_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_10_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_10_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_10_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_10_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_10_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_10_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_10_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_10_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[10]- (Test Scan Port) = test_scan, Out - ut, test_scan_out[10]- (Test Scan Port) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[10]- (Test Scan Port) = test_scan, Output, test_scan_out[ + * 10]- (Test Scan Port) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_10_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_10_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_10_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_10_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_10_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_10_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_10_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_10_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_10_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[10]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[10]- (GPIO bank 0) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_ - o- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outp - t, tracedq[8]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[10]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[10]- (GPIO bank 0) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= sp + * i1, Output, spi1_so- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clo + * ck) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outpu + * t, tracedq[8]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_10_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_10_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_10_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_10_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_10_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_10_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_10_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_10_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_10_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[3]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe - [3]- (QSPI Upper Databus)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[3 + * ]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[3]- (QSPI Upper D + * atabus) +*/ #undef IOU_SLCR_MIO_PIN_11_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_11_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_11_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_11_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_11_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_11_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_11_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_11_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_11_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (NAND Ready/Busy)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (N + * AND Ready/Busy) +*/ #undef IOU_SLCR_MIO_PIN_11_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_11_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_11_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_11_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_11_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_11_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_11_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_11_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_11_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[11]- (Test Scan Port) = test_scan, Out - ut, test_scan_out[11]- (Test Scan Port) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[11]- (Test Scan Port) = test_scan, Output, test_scan_out[ + * 11]- (Test Scan Port) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_11_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_11_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_11_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_11_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_11_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_11_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_11_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_11_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_11_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s - i1_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o - tput) 7= trace, Output, tracedq[9]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) + * 4= spi1, Input, spi1_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- ( + * TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial ou + * tput) 7= trace, Output, tracedq[9]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_11_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_11_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_11_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_11_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_11_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_11_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_11_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_11_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_11_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out_upper- (QSPI Upper Clock)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out_ + * upper- (QSPI Upper Clock) +*/ #undef IOU_SLCR_MIO_PIN_12_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_12_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_12_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_12_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_12_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_12_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_12_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_12_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_12_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NAND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe - */ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NA + * ND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe) +*/ #undef IOU_SLCR_MIO_PIN_12_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_12_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_12_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_12_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_12_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_12_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_12_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_12_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_12_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[12]- (Test Scan Port) = test_scan, Out - ut, test_scan_out[12]- (Test Scan Port) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input + * , test_scan_in[12]- (Test Scan Port) = test_scan, Output, test_scan_out[ + * 12]- (Test Scan Port) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_12_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_12_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_12_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_12_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_12_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_12_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_12_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_12_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_12_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[12]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[12]- (GPIO bank 0) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Cl - ck) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trac - dq[10]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[12]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[12]- (GPIO bank 0) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJT + * AG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_ + * sclk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, O + * utput, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace + * dq[10]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_12_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_12_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_12_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_12_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_12_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_12_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_12_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_12_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_12_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_13_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_13_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_13_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_13_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_13_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_13_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_13_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_13_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_13_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[0]- (NAND chip enable)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[0]- (NA + * ND chip enable) +*/ #undef IOU_SLCR_MIO_PIN_13_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_13_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_13_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_13_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_13_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_13_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_13_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_13_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_13_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8 - bit Data bus) 2= test_scan, Input, test_scan_in[13]- (Test Scan Port) = test_scan, Output, test_scan_out[13]- (Test Scan Port - 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[13]- (Test Scan Port) = test_scan, Output, + * test_scan_out[13]- (Test Scan Port) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_13_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_13_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_13_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_13_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_13_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_13_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_13_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_13_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_13_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[13]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[13]- (GPIO bank 0) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave - out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq[11]- (Trace Port Dat - bus)*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[13]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[13]- (GPIO bank 0) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTA + * G TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, + * Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UAR + * T receiver serial input) 7= trace, Output, tracedq[11]- (Trace Port Data + * bus) +*/ #undef IOU_SLCR_MIO_PIN_13_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_13_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_13_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_13_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_13_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_13_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_13_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_13_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_13_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_14_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_14_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_14_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_14_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_14_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_14_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_14_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_14_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_14_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_cle- (NAND Command Latch Enable)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_cle- (NAND + * Command Latch Enable) +*/ #undef IOU_SLCR_MIO_PIN_14_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_14_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_14_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_14_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_14_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_14_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_14_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_14_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_14_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8 - bit Data bus) 2= test_scan, Input, test_scan_in[14]- (Test Scan Port) = test_scan, Output, test_scan_out[14]- (Test Scan Port - 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[14]- (Test Scan Port) = test_scan, Output, + * test_scan_out[14]- (Test Scan Port) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_14_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_14_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_14_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_14_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_14_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_14_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_14_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_14_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_14_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, Input, ttc0_clk_ - n- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJT + * AG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, + * Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver + * serial input) 7= trace, Output, tracedq[12]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_14_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_14_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_14_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_14_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_14_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_14_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_14_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_14_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_14_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_15_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_15_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_15_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_15_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_15_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_15_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_15_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_15_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_15_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ale- (NAND Address Latch Enable)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ale- (NAND + * Address Latch Enable) +*/ #undef IOU_SLCR_MIO_PIN_15_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_15_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_15_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_15_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_15_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_15_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_15_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_15_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_15_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8 - bit Data bus) 2= test_scan, Input, test_scan_in[15]- (Test Scan Port) = test_scan, Output, test_scan_out[15]- (Test Scan Port - 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[15]- (Test Scan Port) = test_scan, Output, + * test_scan_out[15]- (Test Scan Port) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_15_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_15_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_15_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_15_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_15_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_15_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_15_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_15_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_15_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[15]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[15]- (GPIO bank 0) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out - 0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter seri - l output) 7= trace, Output, tracedq[13]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[15]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[15]- (GPIO bank 0) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJT + * AG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Outp + * ut, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_ou + * t- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter seria + * l output) 7= trace, Output, tracedq[13]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_15_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_15_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_15_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_15_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_15_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_15_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_15_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_15_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_15_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_16_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_16_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_16_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_16_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_16_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_16_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_16_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_16_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_16_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[0]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[0]- (NAND - ata Bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[0]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[0]- (NAND Data Bus) +*/ #undef IOU_SLCR_MIO_PIN_16_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_16_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_16_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_16_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_16_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_16_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_16_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_16_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_16_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8 - bit Data bus) 2= test_scan, Input, test_scan_in[16]- (Test Scan Port) = test_scan, Output, test_scan_out[16]- (Test Scan Port - 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[16]- (Test Scan Port) = test_scan, Output, + * test_scan_out[16]- (Test Scan Port) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_16_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_16_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_16_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_16_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_16_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_16_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_16_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_16_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_16_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[16]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[16]- (GPIO bank 0) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0 - so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace - Output, tracedq[14]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[16]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[16]- (GPIO bank 0) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= s + * pi0, Output, spi0_so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Cl + * ock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, + * Output, tracedq[14]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_16_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_16_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_16_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_16_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_16_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_16_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_16_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_16_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_16_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_17_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_17_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_17_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_17_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_17_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_17_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_17_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_17_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_17_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[1]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[1]- (NAND - ata Bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[1]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[1]- (NAND Data Bus) +*/ #undef IOU_SLCR_MIO_PIN_17_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_17_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_17_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_17_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_17_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_17_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_17_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_17_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_17_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8 - bit Data bus) 2= test_scan, Input, test_scan_in[17]- (Test Scan Port) = test_scan, Output, test_scan_out[17]- (Test Scan Port - 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[17]- (Test Scan Port) = test_scan, Output, + * test_scan_out[17]- (Test Scan Port) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_17_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_17_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_17_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_17_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_17_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_17_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_17_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_17_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_17_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[17]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[17]- (GPIO bank 0) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, sp - 0_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) - 7= trace, Output, tracedq[15]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[17]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[17]- (GPIO bank 0) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4 + * = spi0, Input, spi0_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (T + * TC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) + * 7= trace, Output, tracedq[15]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_17_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_17_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_17_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_17_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_17_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_17_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_17_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_17_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_17_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_18_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_18_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_18_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_18_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_18_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_18_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_18_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_18_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_18_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[2]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[2]- (NAND - ata Bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[2]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[2]- (NAND Data Bus) +*/ #undef IOU_SLCR_MIO_PIN_18_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_18_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_18_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_18_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_18_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_18_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_18_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_18_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_18_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8 - bit Data bus) 2= test_scan, Input, test_scan_in[18]- (Test Scan Port) = test_scan, Output, test_scan_out[18]- (Test Scan Port - 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[18]- (Test Scan Port) = test_scan, Output, + * test_scan_out[18]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU + * Ext Tamper) +*/ #undef IOU_SLCR_MIO_PIN_18_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_18_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_18_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_18_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_18_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_18_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_18_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_18_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_18_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[18]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[18]- (GPIO bank 0) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_ - o- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[18]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[18]- (GPIO bank 0) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= sp + * i1, Output, spi1_so- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clo + * ck) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used +*/ #undef IOU_SLCR_MIO_PIN_18_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_18_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_18_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_18_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_18_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_18_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_18_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_18_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_18_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_19_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_19_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_19_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_19_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_19_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_19_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_19_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_19_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_19_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[3]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[3]- (NAND - ata Bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[3]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[3]- (NAND Data Bus) +*/ #undef IOU_SLCR_MIO_PIN_19_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_19_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_19_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_19_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_19_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_19_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_19_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_19_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_19_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8 - bit Data bus) 2= test_scan, Input, test_scan_in[19]- (Test Scan Port) = test_scan, Output, test_scan_out[19]- (Test Scan Port - 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[19]- (Test Scan Port) = test_scan, Output, + * test_scan_out[19]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU + * Ext Tamper) +*/ #undef IOU_SLCR_MIO_PIN_19_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_19_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_19_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_19_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_19_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_19_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_19_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_19_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_19_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[19]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[19]- (GPIO bank 0) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5 - ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[19]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[19]- (GPIO bank 0) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI + * Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= + * ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used +*/ #undef IOU_SLCR_MIO_PIN_19_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_19_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_19_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_19_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_19_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_19_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_19_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_19_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_19_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_20_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_20_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_20_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_20_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_20_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_20_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_20_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_20_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_20_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[4]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[4]- (NAND - ata Bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[4]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[4]- (NAND Data Bus) +*/ #undef IOU_SLCR_MIO_PIN_20_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_20_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_20_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_20_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_20_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_20_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_20_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_20_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_20_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8 - bit Data bus) 2= test_scan, Input, test_scan_in[20]- (Test Scan Port) = test_scan, Output, test_scan_out[20]- (Test Scan Port - 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8-bit Data bus) 2= t + * est_scan, Input, test_scan_in[20]- (Test Scan Port) = test_scan, Output, + * test_scan_out[20]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU + * Ext Tamper) +*/ #undef IOU_SLCR_MIO_PIN_20_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_20_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_20_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_20_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_20_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_20_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_20_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_20_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_20_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[20]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[20]- (GPIO bank 0) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= t - c1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Used*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[20]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[20]- (GPIO bank 0) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Mas + * ter Selects) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua + * 1_txd- (UART transmitter serial output) 7= Not Used +*/ #undef IOU_SLCR_MIO_PIN_20_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_20_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_20_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_20_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_20_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_20_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_20_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_20_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_20_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_21_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_21_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_21_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_21_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_21_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_21_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_21_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_21_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_21_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[5]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[5]- (NAND - ata Bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[5]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[5]- (NAND Data Bus) +*/ #undef IOU_SLCR_MIO_PIN_21_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_21_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_21_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_21_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_21_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_21_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_21_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_21_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_21_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Comman - Indicator) 2= test_scan, Input, test_scan_in[21]- (Test Scan Port) = test_scan, Output, test_scan_out[21]- (Test Scan Port) - = csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Com + * mand Indicator) = sd0, Output, sdio0_cmd_out- (Command Indicator) 2= tes + * t_scan, Input, test_scan_in[21]- (Test Scan Port) = test_scan, Output, t + * est_scan_out[21]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU E + * xt Tamper) +*/ #undef IOU_SLCR_MIO_PIN_21_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_21_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_21_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_21_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_21_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_21_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_21_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_21_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_21_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[21]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[21]- (GPIO bank 0) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1 - Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- - UART receiver serial input) 7= Not Used*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[21]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[21]- (GPIO bank 0) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master + * Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc + * 1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- ( + * UART receiver serial input) 7= Not Used +*/ #undef IOU_SLCR_MIO_PIN_21_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_21_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_21_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_21_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_21_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_21_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_21_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_21_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_21_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_22_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_22_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_22_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_22_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_22_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_22_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_22_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_22_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_22_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_we_b- (NAND Write Enable)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_we_b- (NAN + * D Write Enable) +*/ #undef IOU_SLCR_MIO_PIN_22_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_22_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_22_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_22_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_22_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_22_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_22_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_22_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_22_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= test_scan, Input, test_scan_in[22]- - (Test Scan Port) = test_scan, Output, test_scan_out[22]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- + * (SDSDIO clock) 2= test_scan, Input, test_scan_in[22]- (Test Scan Port) = + * test_scan, Output, test_scan_out[22]- (Test Scan Port) 3= csu, Input, c + * su_ext_tamper- (CSU Ext Tamper) +*/ #undef IOU_SLCR_MIO_PIN_22_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_22_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_22_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_22_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_22_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_22_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_22_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_22_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_22_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[22]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[22]- (GPIO bank 0) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, sp - 1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not - sed*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[22]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[22]- (GPIO bank 0) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= + * spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- ( + * TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not U + * sed +*/ #undef IOU_SLCR_MIO_PIN_22_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_22_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_22_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_22_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_22_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_22_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_22_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_22_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_22_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_23_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_23_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_23_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_23_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_23_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_23_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_23_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_23_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_23_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[6]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[6]- (NAND - ata Bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[6]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[6]- (NAND Data Bus) +*/ #undef IOU_SLCR_MIO_PIN_23_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_23_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_23_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_23_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_23_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_23_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_23_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_23_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_23_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= test_scan, Input, test_scan_in - 23]- (Test Scan Port) = test_scan, Output, test_scan_out[23]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper - */ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- + * (SD card bus power) 2= test_scan, Input, test_scan_in[23]- (Test Scan Po + * rt) = test_scan, Output, test_scan_out[23]- (Test Scan Port) 3= csu, Inp + * ut, csu_ext_tamper- (CSU Ext Tamper) +*/ #undef IOU_SLCR_MIO_PIN_23_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_23_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_23_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_23_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_23_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_23_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_23_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_23_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_23_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[23]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[23]- (GPIO bank 0) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s - i1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o - tput) 7= Not Used*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[23]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[23]- (GPIO bank 0) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) + * 4= spi1, Input, spi1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- ( + * TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial ou + * tput) 7= Not Used +*/ #undef IOU_SLCR_MIO_PIN_23_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_23_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_23_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_23_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_23_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_23_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_23_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_23_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_23_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_24_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_24_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_24_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_24_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_24_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_24_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_24_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_24_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_24_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[7]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[7]- (NAND - ata Bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[7]- ( + * NAND Data Bus) 1= nand, Output, nfc_dq_out[7]- (NAND Data Bus) +*/ #undef IOU_SLCR_MIO_PIN_24_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_24_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_24_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_24_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_24_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_24_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_24_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_24_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_24_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= test_scan, Input, test - scan_in[24]- (Test Scan Port) = test_scan, Output, test_scan_out[24]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ex - Tamper)*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD + * card detect from connector) 2= test_scan, Input, test_scan_in[24]- (Test + * Scan Port) = test_scan, Output, test_scan_out[24]- (Test Scan Port) 3= + * csu, Input, csu_ext_tamper- (CSU Ext Tamper) +*/ #undef IOU_SLCR_MIO_PIN_24_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_24_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_24_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_24_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_24_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_24_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_24_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_24_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_24_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[24]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[24]- (GPIO bank 0) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= Not Used 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, - Output, ua1_txd- (UART transmitter serial output) 7= Not Used*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[24]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[24]- (GPIO bank 0) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= Not Used 5= ttc3, Input, ttc3_clk_in- (T + * TC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= N + * ot Used +*/ #undef IOU_SLCR_MIO_PIN_24_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_24_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_24_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_24_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_24_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_24_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_24_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_24_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_24_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_25_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_25_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_25_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_25_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_25_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_25_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_25_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_25_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_25_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_re_n- (NAND Read Enable)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_re_n- (NAN + * D Read Enable) +*/ #undef IOU_SLCR_MIO_PIN_25_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_25_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_25_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_25_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_25_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_25_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_25_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_25_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_25_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= test_scan, Input, - test_scan_in[25]- (Test Scan Port) = test_scan, Output, test_scan_out[25]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (C - U Ext Tamper)*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD ca + * rd write protect from connector) 2= test_scan, Input, test_scan_in[25]- + * (Test Scan Port) = test_scan, Output, test_scan_out[25]- (Test Scan Port + * ) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper) +*/ #undef IOU_SLCR_MIO_PIN_25_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_25_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_25_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_25_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_25_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_25_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_25_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_25_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_25_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[25]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[25]- (GPIO bank 0) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= Not Used 5= ttc3, Output, ttc3_wave_out- (TTC Waveform - lock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used*/ +/* +* Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[25]- (GPIO bank 0) 0= + * gpio0, Output, gpio_0_pin_out[25]- (GPIO bank 0) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= Not Used 5= ttc3, Output, ttc3_wave_ou + * t- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial in + * put) 7= Not Used +*/ #undef IOU_SLCR_MIO_PIN_25_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_25_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_25_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_25_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_25_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_25_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_25_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_25_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_25_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_clk- (TX RGMII clock)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ + * clk- (TX RGMII clock) +*/ #undef IOU_SLCR_MIO_PIN_26_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_26_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_26_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_26_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_26_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_26_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_26_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_26_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_26_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NAND chip enable)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NA + * ND chip enable) +*/ #undef IOU_SLCR_MIO_PIN_26_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_26_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_26_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_26_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_26_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_26_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_26_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_26_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_26_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[0]- (PMU GPI) 2= test_scan, Input, test_scan_in[26]- (Test Sc - n Port) = test_scan, Output, test_scan_out[26]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[0]- (PMU + * GPI) 2= test_scan, Input, test_scan_in[26]- (Test Scan Port) = test_sca + * n, Output, test_scan_out[26]- (Test Scan Port) 3= csu, Input, csu_ext_ta + * mper- (CSU Ext Tamper) +*/ #undef IOU_SLCR_MIO_PIN_26_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_26_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_26_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_26_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_26_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_26_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_26_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_26_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_26_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[0]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[0]- (GPIO bank 1) 1= can - , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal - 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Clock - 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- - Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[0]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[0]- (GPIO bank 1) 1= can0, Input, can0_phy_ + * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + * , Output, i2c0_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG + * TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_scl + * k_out- (SPI Clock) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Inpu + * t, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- ( + * Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_26_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_26_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_26_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_26_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_26_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_26_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_26_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_26_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_26_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[0]- (TX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd + * [0]- (TX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_27_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_27_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_27_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_27_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_27_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_27_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_27_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_27_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_27_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (NAND Ready/Busy)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (N + * AND Ready/Busy) +*/ #undef IOU_SLCR_MIO_PIN_27_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_27_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_27_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_27_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_27_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_27_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_27_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_27_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_27_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[1]- (PMU GPI) 2= test_scan, Input, test_scan_in[27]- (Test Sc - n Port) = test_scan, Output, test_scan_out[27]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Outp - t, dp_aux_data_out- (Dp Aux Data)*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[1]- (PMU + * GPI) 2= test_scan, Input, test_scan_in[27]- (Test Scan Port) = test_sca + * n, Output, test_scan_out[27]- (Test Scan Port) 3= dpaux, Input, dp_aux_d + * ata_in- (Dp Aux Data) = dpaux, Output, dp_aux_data_out- (Dp Aux Data) +*/ #undef IOU_SLCR_MIO_PIN_27_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_27_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_27_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_27_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_27_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_27_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_27_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_27_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_27_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[1]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[1]- (GPIO bank 1) 1= can - , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa - ) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_ - ut- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port - atabus)*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[1]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[1]- (GPIO bank 1) 1= can0, Output, can0_phy + * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + * 0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG + * TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc2, O + * utput, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UAR + * T transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port D + * atabus) +*/ #undef IOU_SLCR_MIO_PIN_27_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_27_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_27_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_27_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_27_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_27_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_27_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_27_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_27_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[1]- (TX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd + * [1]- (TX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_28_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_28_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_28_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_28_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_28_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_28_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_28_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_28_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_28_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (NAND Ready/Busy)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (N + * AND Ready/Busy) +*/ #undef IOU_SLCR_MIO_PIN_28_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_28_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_28_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_28_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_28_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_28_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_28_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_28_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_28_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[2]- (PMU GPI) 2= test_scan, Input, test_scan_in[28]- (Test Sc - n Port) = test_scan, Output, test_scan_out[28]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[2]- (PMU + * GPI) 2= test_scan, Input, test_scan_in[28]- (Test Scan Port) = test_sca + * n, Output, test_scan_out[28]- (Test Scan Port) 3= dpaux, Input, dp_hot_p + * lug_detect- (Dp Aux Hot Plug) +*/ #undef IOU_SLCR_MIO_PIN_28_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_28_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_28_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_28_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_28_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_28_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_28_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_28_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_28_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[2]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[2]- (GPIO bank 1) 1= can - , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa - ) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc1, Input, ttc1_clk_i - - (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[2]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[2]- (GPIO bank 1) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTA + * G TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc1, + * Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitt + * er serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_28_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_28_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_28_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_28_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_28_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_28_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_28_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_28_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_28_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[2]- (TX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd + * [2]- (TX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_29_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_29_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_29_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_29_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_29_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_29_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_29_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_29_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_29_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + * PCIE Reset signal) +*/ #undef IOU_SLCR_MIO_PIN_29_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_29_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_29_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_29_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_29_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_29_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_29_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_29_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_29_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[3]- (PMU GPI) 2= test_scan, Input, test_scan_in[29]- (Test Sc - n Port) = test_scan, Output, test_scan_out[29]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Outp - t, dp_aux_data_out- (Dp Aux Data)*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[3]- (PMU + * GPI) 2= test_scan, Input, test_scan_in[29]- (Test Scan Port) = test_sca + * n, Output, test_scan_out[29]- (Test Scan Port) 3= dpaux, Input, dp_aux_d + * ata_in- (Dp Aux Data) = dpaux, Output, dp_aux_data_out- (Dp Aux Data) +*/ #undef IOU_SLCR_MIO_PIN_29_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_29_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_29_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_29_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_29_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_29_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_29_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_29_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_29_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[3]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[3]- (GPIO bank 1) 1= can - , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal - 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0] - (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial inpu - ) 7= trace, Output, tracedq[7]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[3]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[3]- (GPIO bank 1) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG + * TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, + * spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- + * (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input + * ) 7= trace, Output, tracedq[7]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_29_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_29_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_29_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_29_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_29_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_29_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_29_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_29_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_29_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[3]- (TX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd + * [3]- (TX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_30_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_30_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_30_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_30_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_30_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_30_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_30_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_30_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_30_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + * PCIE Reset signal) +*/ #undef IOU_SLCR_MIO_PIN_30_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_30_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_30_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_30_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_30_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_30_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_30_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_30_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_30_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[4]- (PMU GPI) 2= test_scan, Input, test_scan_in[30]- (Test Sc - n Port) = test_scan, Output, test_scan_out[30]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[4]- (PMU + * GPI) 2= test_scan, Input, test_scan_in[30]- (Test Scan Port) = test_sca + * n, Output, test_scan_out[30]- (Test Scan Port) 3= dpaux, Input, dp_hot_p + * lug_detect- (Dp Aux Hot Plug) +*/ #undef IOU_SLCR_MIO_PIN_30_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_30_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_30_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_30_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_30_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_30_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_30_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_30_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_30_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[4]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[4]- (GPIO bank 1) 1= can - , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal - 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_so - (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output - tracedq[8]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[4]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[4]- (GPIO bank 1) 1= can0, Input, can0_phy_ + * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + * , Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Wat + * ch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0 + * , Output, spi0_so- (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clock + * ) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, + * tracedq[8]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_30_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_30_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_30_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_30_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_30_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_30_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_30_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_30_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_30_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ctl- (TX RGMII control)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ + * ctl- (TX RGMII control) +*/ #undef IOU_SLCR_MIO_PIN_31_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_31_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_31_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_31_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_31_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_31_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_31_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_31_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_31_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + * PCIE Reset signal) +*/ #undef IOU_SLCR_MIO_PIN_31_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_31_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_31_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_31_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_31_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_31_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_31_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_31_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_31_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[5]- (PMU GPI) 2= test_scan, Input, test_scan_in[31]- (Test Sc - n Port) = test_scan, Output, test_scan_out[31]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[5]- (PMU + * GPI) 2= test_scan, Input, test_scan_in[31]- (Test Scan Port) = test_sca + * n, Output, test_scan_out[31]- (Test Scan Port) 3= csu, Input, csu_ext_ta + * mper- (CSU Ext Tamper) +*/ #undef IOU_SLCR_MIO_PIN_31_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_31_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_31_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_31_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_31_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_31_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_31_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_31_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_31_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[5]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[5]- (GPIO bank 1) 1= can - , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa - ) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi - _si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial out - ut) 7= trace, Output, tracedq[9]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[5]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[5]- (GPIO bank 1) 1= can0, Output, can0_phy + * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + * 0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- ( + * Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= + * spi0, Input, spi0_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TT + * C Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial outp + * ut) 7= trace, Output, tracedq[9]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_31_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_31_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_31_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_31_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_31_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_31_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_31_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_31_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_31_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_clk- (RX RGMII clock)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_c + * lk- (RX RGMII clock) +*/ #undef IOU_SLCR_MIO_PIN_32_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_32_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_32_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_32_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_32_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_32_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_32_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_32_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_32_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NAND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe - */ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NA + * ND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe) +*/ #undef IOU_SLCR_MIO_PIN_32_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_32_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_32_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_32_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_32_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_32_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_32_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_32_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_32_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[0]- (PMU GPI) 2= test_scan, Input, test_scan_in[32]- (Test S - an Port) = test_scan, Output, test_scan_out[32]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[0]- (PM + * U GPI) 2= test_scan, Input, test_scan_in[32]- (Test Scan Port) = test_sc + * an, Output, test_scan_out[32]- (Test Scan Port) 3= csu, Input, csu_ext_t + * amper- (CSU Ext Tamper) +*/ #undef IOU_SLCR_MIO_PIN_32_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_32_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_32_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_32_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_32_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_32_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_32_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_32_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_32_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[6]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[6]- (GPIO bank 1) 1= can - , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa - ) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi - _sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= - race, Output, tracedq[10]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[6]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[6]- (GPIO bank 1) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Wa + * tch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= + * spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (T + * TC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= t + * race, Output, tracedq[10]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_32_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_32_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_32_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_32_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_32_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_32_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_32_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_32_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_32_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[0]- (RX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[ + * 0]- (RX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_33_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_33_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_33_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_33_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_33_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_33_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_33_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_33_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_33_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + * PCIE Reset signal) +*/ #undef IOU_SLCR_MIO_PIN_33_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_33_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_33_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_33_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_33_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_33_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_33_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_33_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_33_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[1]- (PMU GPI) 2= test_scan, Input, test_scan_in[33]- (Test S - an Port) = test_scan, Output, test_scan_out[33]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[1]- (PM + * U GPI) 2= test_scan, Input, test_scan_in[33]- (Test Scan Port) = test_sc + * an, Output, test_scan_out[33]- (Test Scan Port) 3= csu, Input, csu_ext_t + * amper- (CSU Ext Tamper) +*/ #undef IOU_SLCR_MIO_PIN_33_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_33_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_33_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_33_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_33_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_33_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_33_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_33_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_33_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[7]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[7]- (GPIO bank 1) 1= can - , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal - 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= t - c3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, traced - [11]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[7]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[7]- (GPIO bank 1) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (W + * atch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Mas + * ter Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1 + * , Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq + * [11]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_33_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_33_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_33_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_33_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_33_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_33_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_33_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_33_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_33_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[1]- (RX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[ + * 1]- (RX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_34_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_34_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_34_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_34_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_34_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_34_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_34_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_34_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_34_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + * PCIE Reset signal) +*/ #undef IOU_SLCR_MIO_PIN_34_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_34_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_34_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_34_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_34_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_34_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_34_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_34_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_34_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[2]- (PMU GPI) 2= test_scan, Input, test_scan_in[34]- (Test S - an Port) = test_scan, Output, test_scan_out[34]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Out - ut, dp_aux_data_out- (Dp Aux Data)*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[2]- (PM + * U GPI) 2= test_scan, Input, test_scan_in[34]- (Test Scan Port) = test_sc + * an, Output, test_scan_out[34]- (Test Scan Port) 3= dpaux, Input, dp_aux_ + * data_in- (Dp Aux Data) = dpaux, Output, dp_aux_data_out- (Dp Aux Data) +*/ #undef IOU_SLCR_MIO_PIN_34_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_34_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_34_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_34_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_34_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_34_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_34_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_34_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_34_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[8]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[8]- (GPIO bank 1) 1= can - , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal - 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc2 - Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace P - rt Databus)*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[8]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[8]- (GPIO bank 1) 1= can0, Input, can0_phy_ + * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + * , Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (Wat + * ch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master + * Selects) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rx + * d- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace Po + * rt Databus) +*/ #undef IOU_SLCR_MIO_PIN_34_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_34_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_34_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_34_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_34_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_34_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_34_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_34_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_34_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[2]- (RX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[ + * 2]- (RX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_35_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_35_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_35_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_35_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_35_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_35_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_35_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_35_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_35_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + * PCIE Reset signal) +*/ #undef IOU_SLCR_MIO_PIN_35_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_35_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_35_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_35_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_35_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_35_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_35_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_35_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_35_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[3]- (PMU GPI) 2= test_scan, Input, test_scan_in[35]- (Test S - an Port) = test_scan, Output, test_scan_out[35]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[3]- (PM + * U GPI) 2= test_scan, Input, test_scan_in[35]- (Test Scan Port) = test_sc + * an, Output, test_scan_out[35]- (Test Scan Port) 3= dpaux, Input, dp_hot_ + * plug_detect- (Dp Aux Hot Plug) +*/ #undef IOU_SLCR_MIO_PIN_35_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_35_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_35_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_35_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_35_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_35_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_35_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_35_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_35_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[9]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[9]- (GPIO bank 1) 1= can - , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa - ) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, - Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- - UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[9]- (GPIO bank 1) 0= g + * pio1, Output, gpio_1_pin_out[9]- (GPIO bank 1) 1= can0, Output, can0_phy + * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + * 0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- ( + * Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master + * Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc2 + * , Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- ( + * UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace Po + * rt Databus) +*/ #undef IOU_SLCR_MIO_PIN_35_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_35_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_35_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_35_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_35_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_35_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_35_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_35_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_35_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[3]- (RX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[ + * 3]- (RX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_36_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_36_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_36_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_36_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_36_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_36_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_36_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_36_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_36_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + * PCIE Reset signal) +*/ #undef IOU_SLCR_MIO_PIN_36_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_36_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_36_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_36_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_36_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_36_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_36_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_36_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_36_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[4]- (PMU GPI) 2= test_scan, Input, test_scan_in[36]- (Test S - an Port) = test_scan, Output, test_scan_out[36]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Out - ut, dp_aux_data_out- (Dp Aux Data)*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[4]- (PM + * U GPI) 2= test_scan, Input, test_scan_in[36]- (Test Scan Port) = test_sc + * an, Output, test_scan_out[36]- (Test Scan Port) 3= dpaux, Input, dp_aux_ + * data_in- (Dp Aux Data) = dpaux, Output, dp_aux_data_out- (Dp Aux Data) +*/ #undef IOU_SLCR_MIO_PIN_36_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_36_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_36_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_36_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_36_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_36_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_36_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_36_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_36_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[10]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[10]- (GPIO bank 1) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1 - so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace - Output, tracedq[14]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[10]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[10]- (GPIO bank 1) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= s + * pi1, Output, spi1_so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Cl + * ock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, + * Output, tracedq[14]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_36_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_36_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_36_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_36_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_36_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_36_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_36_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_36_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_36_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_ctl- (RX RGMII control )*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_c + * tl- (RX RGMII control ) +*/ #undef IOU_SLCR_MIO_PIN_37_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_37_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_37_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_37_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_37_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_37_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_37_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_37_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_37_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- ( + * PCIE Reset signal) +*/ #undef IOU_SLCR_MIO_PIN_37_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_37_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_37_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_37_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_37_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_37_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_37_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_37_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_37_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[5]- (PMU GPI) 2= test_scan, Input, test_scan_in[37]- (Test S - an Port) = test_scan, Output, test_scan_out[37]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[5]- (PM + * U GPI) 2= test_scan, Input, test_scan_in[37]- (Test Scan Port) = test_sc + * an, Output, test_scan_out[37]- (Test Scan Port) 3= dpaux, Input, dp_hot_ + * plug_detect- (Dp Aux Hot Plug) +*/ #undef IOU_SLCR_MIO_PIN_37_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_37_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_37_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_37_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_37_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_37_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_37_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_37_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_37_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[11]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[11]- (GPIO bank 1) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, sp - 1_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) - 7= trace, Output, tracedq[15]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[11]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[11]- (GPIO bank 1) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4 + * = spi1, Input, spi1_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (T + * TC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) + * 7= trace, Output, tracedq[15]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_37_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_37_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_37_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_37_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_37_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_37_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_37_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_37_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_37_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_clk- (TX RGMII clock)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ + * clk- (TX RGMII clock) +*/ #undef IOU_SLCR_MIO_PIN_38_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_38_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_38_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_38_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_38_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_38_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_38_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_38_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_38_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_38_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_38_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_38_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_38_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_38_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_38_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_38_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_38_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_38_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= Not Used 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- + * (SDSDIO clock) 2= Not Used 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_38_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_38_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_38_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_38_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_38_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_38_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_38_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_38_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_38_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[12]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[12]- (GPIO bank 1) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Clo - k) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, trace_clk- - (Trace Port Clock)*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[12]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[12]- (GPIO bank 1) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTA + * G TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_s + * clk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, In + * put, ua0_rxd- (UART receiver serial input) 7= trace, Output, trace_clk- + * (Trace Port Clock) +*/ #undef IOU_SLCR_MIO_PIN_38_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_38_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_38_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_38_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_38_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_38_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_38_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_38_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_38_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[0]- (TX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd + * [0]- (TX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_39_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_39_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_39_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_39_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_39_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_39_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_39_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_39_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_39_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_39_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_39_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_39_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_39_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_39_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_39_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_39_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_39_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_39_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= sd1, Input, sd1_data_i - [4]- (8-bit Data bus) = sd1, Output, sdio1_data_out[4]- (8-bit Data bus) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD + * card detect from connector) 2= sd1, Input, sd1_data_in[4]- (8-bit Data b + * us) = sd1, Output, sdio1_data_out[4]- (8-bit Data bus) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_39_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_39_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_39_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_39_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_39_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_39_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_39_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_39_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_39_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[13]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[13]- (GPIO bank 1) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc0, Output, ttc0_wav - _out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, trace_ctl- (Trace Port - Control Signal)*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[13]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[13]- (GPIO bank 1) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJT + * AG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc0, + * Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (U + * ART transmitter serial output) 7= trace, Output, trace_ctl- (Trace Port + * Control Signal) +*/ #undef IOU_SLCR_MIO_PIN_39_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_39_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_39_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_39_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_39_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_39_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_39_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_39_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_39_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[1]- (TX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd + * [1]- (TX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_40_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_40_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_40_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_40_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_40_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_40_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_40_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_40_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_40_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_40_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_40_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_40_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_40_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_40_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_40_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_40_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_40_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_40_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Comman - Indicator) 2= sd1, Input, sd1_data_in[5]- (8-bit Data bus) = sd1, Output, sdio1_data_out[5]- (8-bit Data bus) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Com + * mand Indicator) = sd0, Output, sdio0_cmd_out- (Command Indicator) 2= sd1 + * , Input, sd1_data_in[5]- (8-bit Data bus) = sd1, Output, sdio1_data_out[ + * 5]- (8-bit Data bus) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_40_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_40_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_40_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_40_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_40_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_40_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_40_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_40_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_40_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[14]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[14]- (GPIO bank 1) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc3, Input, ttc3_clk - in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[0]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[14]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[14]- (GPIO bank 1) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJ + * TAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc3 + * , Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmi + * tter serial output) 7= trace, Output, tracedq[0]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_40_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_40_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_40_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_40_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_40_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_40_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_40_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_40_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_40_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[2]- (TX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd + * [2]- (TX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_41_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_41_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_41_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_41_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_41_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_41_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_41_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_41_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_41_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_41_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_41_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_41_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_41_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_41_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_41_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_41_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_41_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_41_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8 - bit Data bus) 2= sd1, Input, sd1_data_in[6]- (8-bit Data bus) = sd1, Output, sdio1_data_out[6]- (8-bit Data bus) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[6]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[6]- (8-bit Data bus) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_41_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_41_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_41_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_41_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_41_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_41_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_41_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_41_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_41_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[15]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[15]- (GPIO bank 1) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[ - ]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial in - ut) 7= trace, Output, tracedq[1]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[15]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[15]- (GPIO bank 1) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTA + * G TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Outpu + * t, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out + * - (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial inp + * ut) 7= trace, Output, tracedq[1]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_41_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_41_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_41_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_41_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_41_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_41_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_41_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_41_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_41_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[3]- (TX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd + * [3]- (TX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_42_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_42_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_42_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_42_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_42_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_42_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_42_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_42_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_42_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_42_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_42_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_42_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_42_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_42_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_42_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_42_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_42_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_42_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8 - bit Data bus) 2= sd1, Input, sd1_data_in[7]- (8-bit Data bus) = sd1, Output, sdio1_data_out[7]- (8-bit Data bus) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[7]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[7]- (8-bit Data bus) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_42_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_42_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_42_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_42_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_42_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_42_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_42_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_42_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_42_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_ - o- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outp - t, tracedq[2]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= sp + * i0, Output, spi0_so- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clo + * ck) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outpu + * t, tracedq[2]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_42_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_42_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_42_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_42_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_42_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_42_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_42_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_42_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_42_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ctl- (TX RGMII control)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ + * ctl- (TX RGMII control) +*/ #undef IOU_SLCR_MIO_PIN_43_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_43_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_43_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_43_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_43_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_43_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_43_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_43_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_43_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_43_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_43_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_43_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_43_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_43_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_43_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_43_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_43_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_43_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8 - bit Data bus) 2= sd1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8-bit Data bus) 2= s + * d1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_43_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_43_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_43_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_43_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_43_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_43_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_43_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_43_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_43_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, s - i0_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o - tput) 7= trace, Output, tracedq[3]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) + * 4= spi0, Input, spi0_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- ( + * TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial ou + * tput) 7= trace, Output, tracedq[3]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_43_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_43_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_43_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_43_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_43_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_43_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_43_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_43_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_43_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_clk- (RX RGMII clock)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_c + * lk- (RX RGMII clock) +*/ #undef IOU_SLCR_MIO_PIN_44_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_44_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_44_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_44_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_44_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_44_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_44_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_44_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_44_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_44_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_44_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_44_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_44_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_44_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_44_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_44_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_44_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_44_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8 - bit Data bus) 2= sd1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8-bit Data bus) 2= s + * d1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_44_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_44_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_44_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_44_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_44_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_44_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_44_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_44_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_44_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[18]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[18]- (GPIO bank 1) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, s - i1_sclk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7 - Not Used*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[18]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[18]- (GPIO bank 1) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4 + * = spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- + * (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= + * Not Used +*/ #undef IOU_SLCR_MIO_PIN_44_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_44_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_44_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_44_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_44_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_44_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_44_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_44_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_44_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[0]- (RX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[ + * 0]- (RX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_45_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_45_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_45_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_45_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_45_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_45_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_45_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_45_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_45_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_45_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_45_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_45_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_45_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_45_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_45_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_45_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_45_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_45_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8 - bit Data bus) 2= sd1, Input, sdio1_cd_n- (SD card detect from connector) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8-bit Data bus) 2= s + * d1, Input, sdio1_cd_n- (SD card detect from connector) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_45_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_45_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_45_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_45_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_45_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_45_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_45_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_45_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_45_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[19]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[19]- (GPIO bank 1) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= - ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[19]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[19]- (GPIO bank 1) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI M + * aster Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= u + * a1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used +*/ #undef IOU_SLCR_MIO_PIN_45_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_45_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_45_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_45_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_45_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_45_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_45_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_45_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_45_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[1]- (RX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[ + * 1]- (RX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_46_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_46_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_46_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_46_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_46_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_46_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_46_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_46_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_46_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_46_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_46_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_46_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_46_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_46_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_46_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_46_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_46_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_46_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8 - bit Data bus) 2= sd1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_out[0]- (8-bit Data bus) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[0]- (8-bit Data bus) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_46_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_46_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_46_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_46_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_46_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_46_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_46_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_46_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_46_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= tt - 0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Mast + * er Selects) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_ + * rxd- (UART receiver serial input) 7= Not Used +*/ #undef IOU_SLCR_MIO_PIN_46_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_46_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_46_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_46_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_46_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_46_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_46_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_46_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_46_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[2]- (RX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[ + * 2]- (RX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_47_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_47_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_47_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_47_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_47_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_47_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_47_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_47_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_47_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_47_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_47_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_47_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_47_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_47_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_47_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_47_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_47_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_47_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8 - bit Data bus) 2= sd1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_out[1]- (8-bit Data bus) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[1]- (8-bit Data bus) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_47_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_47_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_47_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_47_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_47_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_47_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_47_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_47_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_47_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi - , Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd - (UART transmitter serial output) 7= Not Used*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Maste + * r Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= tt + * c0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- + * (UART transmitter serial output) 7= Not Used +*/ #undef IOU_SLCR_MIO_PIN_47_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_47_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_47_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_47_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_47_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_47_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_47_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_47_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_47_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[3]- (RX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[ + * 3]- (RX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_48_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_48_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_48_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_48_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_48_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_48_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_48_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_48_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_48_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_48_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_48_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_48_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_48_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_48_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_48_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_48_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_48_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_48_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8 - bit Data bus) 2= sd1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_out[2]- (8-bit Data bus) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[2]- (8-bit Data bus) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_48_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_48_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_48_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_48_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_48_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_48_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_48_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_48_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_48_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[22]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[22]- (GPIO bank 1) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1 - so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not U - ed*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[22]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[22]- (GPIO bank 1) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= s + * pi1, Output, spi1_so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Cl + * ock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Us + * ed +*/ #undef IOU_SLCR_MIO_PIN_48_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_48_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_48_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_48_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_48_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_48_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_48_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_48_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_48_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_ctl- (RX RGMII control )*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_c + * tl- (RX RGMII control ) +*/ #undef IOU_SLCR_MIO_PIN_49_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_49_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_49_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_49_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_49_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_49_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_49_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_49_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_49_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_49_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_49_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_49_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_49_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_49_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_49_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_49_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_49_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_49_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= sd1, Input, sd1_data_in[3]- (8 - bit Data bus) = sd1, Output, sdio1_data_out[3]- (8-bit Data bus) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- + * (SD card bus power) 2= sd1, Input, sd1_data_in[3]- (8-bit Data bus) = sd + * 1, Output, sdio1_data_out[3]- (8-bit Data bus) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_49_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_49_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_49_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_49_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_49_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_49_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_49_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_49_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_49_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[23]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[23]- (GPIO bank 1) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, sp - 1_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) - 7= Not Used*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[23]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[23]- (GPIO bank 1) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4 + * = spi1, Input, spi1_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (T + * TC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) + * 7= Not Used +*/ #undef IOU_SLCR_MIO_PIN_49_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_49_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_49_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_49_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_49_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_49_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_49_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_49_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_49_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- (TSU clock)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- + * (TSU clock) +*/ #undef IOU_SLCR_MIO_PIN_50_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_50_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_50_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_50_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_50_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_50_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_50_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_50_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_50_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_50_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_50_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_50_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_50_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_50_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_50_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_50_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_50_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_50_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= sd1, Input, sd1_c - d_in- (Command Indicator) = sd1, Output, sdio1_cmd_out- (Command Indicator) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD ca + * rd write protect from connector) 2= sd1, Input, sd1_cmd_in- (Command Ind + * icator) = sd1, Output, sdio1_cmd_out- (Command Indicator) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_50_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_50_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_50_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_50_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_50_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_50_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_50_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_50_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_50_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[24]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[24]- (GPIO bank 1) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= ttc2, Input, ttc2 - clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[24]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[24]- (GPIO bank 1) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= + * ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART rece + * iver serial input) 7= Not Used +*/ #undef IOU_SLCR_MIO_PIN_50_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_50_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_50_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_50_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_50_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_50_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_50_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_50_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_50_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- (TSU clock)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- + * (TSU clock) +*/ #undef IOU_SLCR_MIO_PIN_51_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_51_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_51_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_51_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_51_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_51_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_51_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_51_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_51_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_51_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_51_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_51_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_51_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_51_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_51_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_51_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_51_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_51_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Output, sdio1_clk_out- (SDSDIO clock) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Output, sdi + * o1_clk_out- (SDSDIO clock) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_51_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_51_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_51_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_51_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_51_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_51_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_51_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_51_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_51_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[25]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[25]- (GPIO bank 1) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= mdio1, Input, gem1_mdio_in- (MDIO Data) 4= mdio1, Outp - t, gem1_mdio_out- (MDIO Data) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter - serial output) 7= Not Used*/ +/* +* Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[25]- (GPIO bank 1) 0= + * gpio1, Output, gpio_1_pin_out[25]- (GPIO bank 1) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= mdio1, Input, gem1_mdio_in- (MDIO Dat + * a) 4= mdio1, Output, gem1_mdio_out- (MDIO Data) 5= ttc2, Output, ttc2_wa + * ve_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter + * serial output) 7= Not Used +*/ #undef IOU_SLCR_MIO_PIN_51_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_51_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_51_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_51_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_51_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_51_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_51_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_51_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_51_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_clk- (TX RGMII clock)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_ + * clk- (TX RGMII clock) +*/ #undef IOU_SLCR_MIO_PIN_52_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_52_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_52_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_52_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_52_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_52_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_52_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_52_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_52_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_clk_in- (ULPI Clock)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_clk_i + * n- (ULPI Clock) +*/ #undef IOU_SLCR_MIO_PIN_52_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_52_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_52_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_52_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_52_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_52_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_52_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_52_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_52_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used +*/ #undef IOU_SLCR_MIO_PIN_52_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_52_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_52_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_52_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_52_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_52_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_52_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_52_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_52_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[0]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[0]- (GPIO bank 2) 1= can - , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa - ) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Cloc - ) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_ - lk- (Trace Port Clock)*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[0]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[0]- (GPIO bank 2) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG + * TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sc + * lk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Out + * put, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_c + * lk- (Trace Port Clock) +*/ #undef IOU_SLCR_MIO_PIN_52_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_52_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_52_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_52_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_52_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_52_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_52_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_52_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_52_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[0]- (TX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd + * [0]- (TX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_53_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_53_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_53_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_53_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_53_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_53_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_53_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_53_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_53_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_dir- (Data bus direction control)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_dir- + * (Data bus direction control) +*/ #undef IOU_SLCR_MIO_PIN_53_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_53_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_53_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_53_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_53_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_53_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_53_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_53_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_53_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used +*/ #undef IOU_SLCR_MIO_PIN_53_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_53_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_53_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_53_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_53_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_53_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_53_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_53_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_53_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[1]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[1]- (GPIO bank 2) 1= can - , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal - 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_o - t- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control - Signal)*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[1]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[1]- (GPIO bank 2) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG + * TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Ou + * tput, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART + * receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control + * Signal) +*/ #undef IOU_SLCR_MIO_PIN_53_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_53_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_53_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_53_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_53_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_53_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_53_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_53_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_53_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[1]- (TX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd + * [1]- (TX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_54_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_54_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_54_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_54_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_54_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_54_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_54_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_54_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_54_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[2]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_ - ata[2]- (ULPI data bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[2]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[2]- (ULPI data + * bus) +*/ #undef IOU_SLCR_MIO_PIN_54_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_54_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_54_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_54_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_54_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_54_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_54_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_54_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_54_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used +*/ #undef IOU_SLCR_MIO_PIN_54_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_54_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_54_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_54_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_54_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_54_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_54_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_54_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_54_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[2]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[2]- (GPIO bank 2) 1= can - , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal - 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, Input, ttc0_clk_in - (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[0]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[2]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[2]- (GPIO bank 2) 1= can0, Input, can0_phy_ + * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + * , Output, i2c0_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTAG + * TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, I + * nput, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver se + * rial input) 7= trace, Output, tracedq[0]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_54_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_54_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_54_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_54_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_54_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_54_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_54_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_54_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_54_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[2]- (TX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd + * [2]- (TX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_55_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_55_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_55_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_55_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_55_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_55_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_55_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_55_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_55_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_nxt- (Data flow control signal from the PHY)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_nxt- + * (Data flow control signal from the PHY) +*/ #undef IOU_SLCR_MIO_PIN_55_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_55_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_55_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_55_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_55_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_55_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_55_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_55_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_55_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used +*/ #undef IOU_SLCR_MIO_PIN_55_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_55_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_55_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_55_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_55_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_55_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_55_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_55_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_55_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[3]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[3]- (GPIO bank 2) 1= can - , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa - ) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0 - - (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial - output) 7= trace, Output, tracedq[1]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[3]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[3]- (GPIO bank 2) 1= can0, Output, can0_phy + * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + * 0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG + * TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output + * , spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- + * (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial + * output) 7= trace, Output, tracedq[1]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_55_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_55_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_55_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_55_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_55_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_55_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_55_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_55_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_55_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[3]- (TX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd + * [3]- (TX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_56_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_56_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_56_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_56_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_56_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_56_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_56_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_56_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_56_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[0]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_ - ata[0]- (ULPI data bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[0]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[0]- (ULPI data + * bus) +*/ #undef IOU_SLCR_MIO_PIN_56_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_56_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_56_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_56_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_56_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_56_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_56_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_56_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_56_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used +*/ #undef IOU_SLCR_MIO_PIN_56_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_56_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_56_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_56_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_56_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_56_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_56_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_56_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_56_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[4]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[4]- (GPIO bank 2) 1= can - , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa - ) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_s - - (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, - utput, tracedq[2]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[4]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[4]- (GPIO bank 2) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- (Wa + * tch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi + * 0, Output, spi0_so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Cloc + * k) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, O + * utput, tracedq[2]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_56_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_56_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_56_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_56_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_56_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_56_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_56_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_56_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_56_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_ctl- (TX RGMII control)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_ + * ctl- (TX RGMII control) +*/ #undef IOU_SLCR_MIO_PIN_57_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_57_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_57_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_57_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_57_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_57_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_57_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_57_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_57_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[1]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_ - ata[1]- (ULPI data bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[1]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[1]- (ULPI data + * bus) +*/ #undef IOU_SLCR_MIO_PIN_57_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_57_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_57_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_57_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_57_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_57_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_57_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_57_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_57_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used +*/ #undef IOU_SLCR_MIO_PIN_57_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_57_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_57_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_57_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_57_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_57_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_57_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_57_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_57_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[5]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[5]- (GPIO bank 2) 1= can - , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal - 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi0 - si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7 - trace, Output, tracedq[3]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[5]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[5]- (GPIO bank 2) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- (W + * atch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= + * spi0, Input, spi0_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC + * Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= + * trace, Output, tracedq[3]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_57_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_57_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_57_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_57_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_57_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_57_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_57_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_57_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_57_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_clk- (RX RGMII clock)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_c + * lk- (RX RGMII clock) +*/ #undef IOU_SLCR_MIO_PIN_58_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_58_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_58_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_58_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_58_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_58_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_58_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_58_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_58_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Output, usb0_ulpi_stp- (Asserted to end or interrupt transfers)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Output, usb0_ulpi_stp- + * (Asserted to end or interrupt transfers) +*/ #undef IOU_SLCR_MIO_PIN_58_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_58_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_58_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_58_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_58_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_58_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_58_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_58_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_58_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used +*/ #undef IOU_SLCR_MIO_PIN_58_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_58_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_58_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_58_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_58_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_58_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_58_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_58_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_58_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[6]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[6]- (GPIO bank 2) 1= can - , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal - 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1_sclk_out- (SPI Clock - 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- - Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[6]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[6]- (GPIO bank 2) 1= can0, Input, can0_phy_ + * rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0 + * , Output, i2c0_scl_out- (SCL signal) 3= pjtag, Input, pjtag_tck- (PJTAG + * TCK) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1_scl + * k_out- (SPI Clock) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Inpu + * t, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- ( + * Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_58_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_58_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_58_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_58_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_58_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_58_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_58_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_58_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_58_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[0]- (RX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[ + * 0]- (RX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_59_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_59_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_59_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_59_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_59_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_59_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_59_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_59_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_59_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[3]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_ - ata[3]- (ULPI data bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[3]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[3]- (ULPI data + * bus) +*/ #undef IOU_SLCR_MIO_PIN_59_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_59_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_59_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_59_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_59_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_59_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_59_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_59_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_59_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used +*/ #undef IOU_SLCR_MIO_PIN_59_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_59_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_59_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_59_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_59_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_59_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_59_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_59_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_59_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[7]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[7]- (GPIO bank 2) 1= can - , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa - ) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_ - ut- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port - atabus)*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[7]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[7]- (GPIO bank 2) 1= can0, Output, can0_phy + * _tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c + * 0, Output, i2c0_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tdi- (PJTAG + * TDI) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= ttc2, O + * utput, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UAR + * T transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port D + * atabus) +*/ #undef IOU_SLCR_MIO_PIN_59_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_59_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_59_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_59_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_59_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_59_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_59_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_59_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_59_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[1]- (RX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[ + * 1]- (RX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_60_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_60_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_60_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_60_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_60_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_60_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_60_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_60_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_60_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[4]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_ - ata[4]- (ULPI data bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[4]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[4]- (ULPI data + * bus) +*/ #undef IOU_SLCR_MIO_PIN_60_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_60_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_60_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_60_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_60_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_60_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_60_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_60_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_60_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used +*/ #undef IOU_SLCR_MIO_PIN_60_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_60_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_60_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_60_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_60_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_60_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_60_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_60_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_60_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[8]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[8]- (GPIO bank 2) 1= can - , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa - ) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc1, Input, ttc1_clk_i - - (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[8]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[8]- (GPIO bank 2) 1= can1, Output, can1_phy + * _tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c + * 1, Output, i2c1_scl_out- (SCL signal) 3= pjtag, Output, pjtag_tdo- (PJTA + * G TDO) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc1, + * Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitt + * er serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_60_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_60_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_60_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_60_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_60_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_60_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_60_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_60_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_60_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[2]- (RX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[ + * 2]- (RX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_61_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_61_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_61_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_61_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_61_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_61_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_61_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_61_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_61_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[5]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_ - ata[5]- (ULPI data bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[5]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[5]- (ULPI data + * bus) +*/ #undef IOU_SLCR_MIO_PIN_61_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_61_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_61_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_61_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_61_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_61_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_61_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_61_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_61_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used +*/ #undef IOU_SLCR_MIO_PIN_61_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_61_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_61_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_61_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_61_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_61_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_61_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_61_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_61_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[9]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[9]- (GPIO bank 2) 1= can - , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal - 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, Output, spi1_n_ss_out[0] - (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial inpu - ) 7= trace, Output, tracedq[7]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[9]- (GPIO bank 2) 0= g + * pio2, Output, gpio_2_pin_out[9]- (GPIO bank 2) 1= can1, Input, can1_phy_ + * rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1 + * , Output, i2c1_sda_out- (SDA signal) 3= pjtag, Input, pjtag_tms- (PJTAG + * TMS) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, Output, + * spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- + * (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input + * ) 7= trace, Output, tracedq[7]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_61_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_61_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_61_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_61_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_61_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_61_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_61_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_61_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_61_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[3]- (RX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[ + * 3]- (RX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_62_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_62_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_62_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_62_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_62_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_62_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_62_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_62_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_62_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[6]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_ - ata[6]- (ULPI data bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[6]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[6]- (ULPI data + * bus) +*/ #undef IOU_SLCR_MIO_PIN_62_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_62_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_62_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_62_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_62_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_62_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_62_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_62_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_62_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used +*/ #undef IOU_SLCR_MIO_PIN_62_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_62_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_62_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_62_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_62_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_62_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_62_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_62_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_62_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[10]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[10]- (GPIO bank 2) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_ - o- (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outp - t, tracedq[8]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[10]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[10]- (GPIO bank 2) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= sp + * i1, Output, spi1_so- (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clo + * ck) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outpu + * t, tracedq[8]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_62_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_62_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_62_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_62_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_62_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_62_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_62_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_62_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_62_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_ctl- (RX RGMII control )*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_c + * tl- (RX RGMII control ) +*/ #undef IOU_SLCR_MIO_PIN_63_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_63_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_63_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_63_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_63_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_63_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_63_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_63_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_63_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[7]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_ - ata[7]- (ULPI data bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_da + * ta[7]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[7]- (ULPI data + * bus) +*/ #undef IOU_SLCR_MIO_PIN_63_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_63_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_63_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_63_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_63_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_63_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_63_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_63_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_63_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not + * Used +*/ #undef IOU_SLCR_MIO_PIN_63_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_63_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_63_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_63_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_63_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_63_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_63_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_63_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_63_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[11]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[11]- (GPIO bank 2) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s - i1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o - tput) 7= trace, Output, tracedq[9]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[11]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[11]- (GPIO bank 2) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) + * 4= spi1, Input, spi1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- ( + * TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial ou + * tput) 7= trace, Output, tracedq[9]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_63_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_63_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_63_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_63_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_63_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_63_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_63_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_63_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_63_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_clk- (TX RGMII clock)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_ + * clk- (TX RGMII clock) +*/ #undef IOU_SLCR_MIO_PIN_64_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_64_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_64_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_64_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_64_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_64_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_64_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_64_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_64_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_clk_in- (ULPI Clock)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_clk_i + * n- (ULPI Clock) +*/ #undef IOU_SLCR_MIO_PIN_64_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_64_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_64_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_64_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_64_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_64_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_64_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_64_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_64_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= Not Used 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- + * (SDSDIO clock) 2= Not Used 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_64_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_64_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_64_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_64_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_64_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_64_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_64_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_64_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_64_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[12]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[12]- (GPIO bank 2) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, s - i0_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7 - trace, Output, tracedq[10]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[12]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[12]- (GPIO bank 2) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4 + * = spi0, Output, spi0_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- + * (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= + * trace, Output, tracedq[10]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_64_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_64_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_64_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_64_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_64_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_64_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_64_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_64_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_64_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[0]- (TX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd + * [0]- (TX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_65_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_65_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_65_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_65_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_65_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_65_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_65_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_65_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_65_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_dir- (Data bus direction control)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_dir- + * (Data bus direction control) +*/ #undef IOU_SLCR_MIO_PIN_65_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_65_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_65_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_65_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_65_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_65_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_65_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_65_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_65_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= Not Used 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD + * card detect from connector) 2= Not Used 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_65_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_65_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_65_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_65_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_65_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_65_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_65_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_65_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_65_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[13]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[13]- (GPIO bank 2) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= - ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trac - dq[11]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[13]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[13]- (GPIO bank 2) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi0, Output, spi0_n_ss_out[2]- (SPI M + * aster Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= u + * a1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trace + * dq[11]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_65_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_65_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_65_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_65_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_65_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_65_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_65_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_65_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_65_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[1]- (TX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd + * [1]- (TX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_66_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_66_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_66_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_66_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_66_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_66_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_66_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_66_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_66_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[2]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_ - ata[2]- (ULPI data bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[2]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[2]- (ULPI data + * bus) +*/ #undef IOU_SLCR_MIO_PIN_66_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_66_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_66_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_66_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_66_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_66_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_66_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_66_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_66_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Comman - Indicator) 2= Not Used 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Com + * mand Indicator) = sd0, Output, sdio0_cmd_out- (Command Indicator) 2= Not + * Used 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_66_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_66_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_66_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_66_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_66_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_66_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_66_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_66_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_66_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[14]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[14]- (GPIO bank 2) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= tt - 2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace - Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[14]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[14]- (GPIO bank 2) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Mast + * er Selects) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_ + * rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace + * Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_66_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_66_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_66_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_66_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_66_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_66_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_66_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_66_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_66_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[2]- (TX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd + * [2]- (TX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_67_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_67_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_67_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_67_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_67_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_67_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_67_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_67_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_67_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_nxt- (Data flow control signal from the PHY)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_nxt- + * (Data flow control signal from the PHY) +*/ #undef IOU_SLCR_MIO_PIN_67_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_67_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_67_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_67_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_67_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_67_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_67_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_67_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_67_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8 - bit Data bus) 2= Not Used 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8-bit Data bus) 2= N + * ot Used 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_67_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_67_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_67_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_67_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_67_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_67_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_67_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_67_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_67_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[15]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[15]- (GPIO bank 2) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi - , Output, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd - (UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[15]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[15]- (GPIO bank 2) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi0, Input, spi0_n_ss_in- (SPI Maste + * r Selects) 4= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 5= tt + * c2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- + * (UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace + * Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_67_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_67_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_67_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_67_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_67_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_67_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_67_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_67_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_67_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[3]- (TX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd + * [3]- (TX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_68_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_68_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_68_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_68_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_68_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_68_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_68_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_68_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_68_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[0]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_ - ata[0]- (ULPI data bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[0]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[0]- (ULPI data + * bus) +*/ #undef IOU_SLCR_MIO_PIN_68_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_68_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_68_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_68_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_68_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_68_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_68_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_68_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_68_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8 - bit Data bus) 2= Not Used 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8-bit Data bus) 2= N + * ot Used 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_68_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_68_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_68_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_68_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_68_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_68_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_68_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_68_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_68_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[16]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[16]- (GPIO bank 2) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0 - so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace - Output, tracedq[14]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[16]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[16]- (GPIO bank 2) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= s + * pi0, Output, spi0_so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Cl + * ock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, + * Output, tracedq[14]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_68_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_68_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_68_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_68_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_68_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_68_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_68_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_68_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_68_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_ctl- (TX RGMII control)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_ + * ctl- (TX RGMII control) +*/ #undef IOU_SLCR_MIO_PIN_69_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_69_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_69_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_69_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_69_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_69_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_69_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_69_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_69_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[1]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_ - ata[1]- (ULPI data bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[1]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[1]- (ULPI data + * bus) +*/ #undef IOU_SLCR_MIO_PIN_69_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_69_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_69_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_69_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_69_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_69_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_69_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_69_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_69_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8 - bit Data bus) 2= sd1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8-bit Data bus) 2= s + * d1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_69_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_69_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_69_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_69_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_69_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_69_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_69_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_69_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_69_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[17]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[17]- (GPIO bank 2) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, sp - 0_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) - 7= trace, Output, tracedq[15]- (Trace Port Databus)*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[17]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[17]- (GPIO bank 2) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4 + * = spi0, Input, spi0_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (T + * TC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) + * 7= trace, Output, tracedq[15]- (Trace Port Databus) +*/ #undef IOU_SLCR_MIO_PIN_69_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_69_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_69_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_69_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_69_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_69_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_69_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_69_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_69_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_clk- (RX RGMII clock)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_c + * lk- (RX RGMII clock) +*/ #undef IOU_SLCR_MIO_PIN_70_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_70_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_70_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_70_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_70_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_70_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_70_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_70_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_70_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Output, usb1_ulpi_stp- (Asserted to end or interrupt transfers)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Output, usb1_ulpi_stp- + * (Asserted to end or interrupt transfers) +*/ #undef IOU_SLCR_MIO_PIN_70_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_70_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_70_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_70_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_70_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_70_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_70_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_70_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_70_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8 - bit Data bus) 2= sd1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8-bit Data bus) 2= s + * d1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_70_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_70_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_70_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_70_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_70_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_70_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_70_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_70_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_70_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[18]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[18]- (GPIO bank 2) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, sp - 1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not - sed*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[18]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[18]- (GPIO bank 2) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= + * spi1, Output, spi1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- ( + * TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not U + * sed +*/ #undef IOU_SLCR_MIO_PIN_70_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_70_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_70_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_70_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_70_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_70_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_70_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_70_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_70_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[0]- (RX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[ + * 0]- (RX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_71_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_71_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_71_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_71_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_71_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_71_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_71_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_71_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_71_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[3]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_ - ata[3]- (ULPI data bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[3]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[3]- (ULPI data + * bus) +*/ #undef IOU_SLCR_MIO_PIN_71_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_71_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_71_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_71_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_71_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_71_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_71_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_71_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_71_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8 - bit Data bus) 2= sd1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_out[0]- (8-bit Data bus) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[0]- (8-bit Data bus) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_71_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_71_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_71_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_71_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_71_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_71_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_71_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_71_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_71_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[19]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[19]- (GPIO bank 2) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5 - ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[19]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[19]- (GPIO bank 2) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI + * Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= + * ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used +*/ #undef IOU_SLCR_MIO_PIN_71_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_71_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_71_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_71_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_71_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_71_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_71_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_71_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_71_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[1]- (RX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[ + * 1]- (RX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_72_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_72_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_72_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_72_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_72_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_72_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_72_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_72_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_72_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[4]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_ - ata[4]- (ULPI data bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[4]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[4]- (ULPI data + * bus) +*/ #undef IOU_SLCR_MIO_PIN_72_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_72_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_72_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_72_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_72_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_72_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_72_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_72_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_72_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8 - bit Data bus) 2= sd1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_out[1]- (8-bit Data bus) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[1]- (8-bit Data bus) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_72_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_72_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_72_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_72_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_72_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_72_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_72_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_72_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_72_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[20]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[20]- (GPIO bank 2) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= N - t Used 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Used*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[20]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[20]- (GPIO bank 2) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= swdt1, Input, swdt1_clk_in- ( + * Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Mas + * ter Selects) 5= Not Used 6= ua1, Output, ua1_txd- (UART transmitter seri + * al output) 7= Not Used +*/ #undef IOU_SLCR_MIO_PIN_72_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_72_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_72_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_72_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_72_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_72_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_72_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_72_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_72_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[2]- (RX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[ + * 2]- (RX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_73_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_73_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_73_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_73_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_73_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_73_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_73_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_73_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_73_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_ - ata[5]- (ULPI data bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[5]- (ULPI data + * bus) +*/ #undef IOU_SLCR_MIO_PIN_73_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_73_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_73_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_73_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_73_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_73_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_73_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_73_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_73_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8 - bit Data bus) 2= sd1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_out[2]- (8-bit Data bus) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[2]- (8-bit Data bus) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_73_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_73_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_73_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_73_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_73_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_73_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_73_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_73_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_73_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[21]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[21]- (GPIO bank 2) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1 - Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= Not Used 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[21]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[21]- (GPIO bank 2) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= swdt1, Output, swdt1_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master + * Selects) 4= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= Not + * Used 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used +*/ #undef IOU_SLCR_MIO_PIN_73_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_73_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_73_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_73_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_73_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_73_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_73_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_73_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_73_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[3]- (RX RGMII data)*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[ + * 3]- (RX RGMII data) +*/ #undef IOU_SLCR_MIO_PIN_74_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_74_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_74_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_74_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_74_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_74_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_74_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_74_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_74_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[6]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_ - ata[6]- (ULPI data bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[6]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[6]- (ULPI data + * bus) +*/ #undef IOU_SLCR_MIO_PIN_74_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_74_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_74_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_74_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_74_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_74_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_74_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_74_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_74_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8 - bit Data bus) 2= sd1, Input, sd1_data_in[3]- (8-bit Data bus) = sd1, Output, sdio1_data_out[3]- (8-bit Data bus) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- + * (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8-bit Data bus) 2= s + * d1, Input, sd1_data_in[3]- (8-bit Data bus) = sd1, Output, sdio1_data_ou + * t[3]- (8-bit Data bus) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_74_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_74_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_74_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_74_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_74_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_74_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_74_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_74_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_74_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[22]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[22]- (GPIO bank 2) 1= c - n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign - l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_ - o- (MISO signal) 5= Not Used 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[22]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[22]- (GPIO bank 2) 1= can0, Input, can0_ph + * y_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2 + * c0, Output, i2c0_scl_out- (SCL signal) 3= swdt0, Input, swdt0_clk_in- (W + * atch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= sp + * i1, Output, spi1_so- (MISO signal) 5= Not Used 6= ua0, Input, ua0_rxd- ( + * UART receiver serial input) 7= Not Used +*/ #undef IOU_SLCR_MIO_PIN_74_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_74_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_74_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_74_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_74_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_74_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_74_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_74_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_74_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_ctl- (RX RGMII control )*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_c + * tl- (RX RGMII control ) +*/ #undef IOU_SLCR_MIO_PIN_75_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_75_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_75_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_75_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_75_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_75_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_75_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_75_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_75_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[7]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_ - ata[7]- (ULPI data bus)*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_da + * ta[7]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[7]- (ULPI data + * bus) +*/ #undef IOU_SLCR_MIO_PIN_75_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_75_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_75_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_75_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_75_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_75_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_75_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_75_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_75_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= sd1, Input, sd1_cmd_in- (Comma - d Indicator) = sd1, Output, sdio1_cmd_out- (Command Indicator) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- + * (SD card bus power) 2= sd1, Input, sd1_cmd_in- (Command Indicator) = sd1 + * , Output, sdio1_cmd_out- (Command Indicator) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_75_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_75_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_75_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_75_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_75_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_75_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_75_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_75_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_75_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[23]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[23]- (GPIO bank 2) 1= c - n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig - al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s - i1_si- (MOSI signal) 5= Not Used 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[23]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[23]- (GPIO bank 2) 1= can0, Output, can0_p + * hy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i + * 2c0, Output, i2c0_sda_out- (SDA signal) 3= swdt0, Output, swdt0_rst_out- + * (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) + * 4= spi1, Input, spi1_si- (MOSI signal) 5= Not Used 6= ua0, Output, ua0_t + * xd- (UART transmitter serial output) 7= Not Used +*/ #undef IOU_SLCR_MIO_PIN_75_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_75_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_75_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_75_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_75_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_75_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_75_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_75_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_75_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_76_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_76_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_76_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_76_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_76_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_76_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_76_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_76_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_76_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_76_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_76_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_76_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_76_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_76_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_76_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_76_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_76_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_76_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= sd1, Output, sdio - _clk_out- (SDSDIO clock) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD ca + * rd write protect from connector) 2= sd1, Output, sdio1_clk_out- (SDSDIO + * clock) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_76_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_76_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_76_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_76_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_76_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_76_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_76_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_76_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_76_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[24]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[24]- (GPIO bank 2) 1= c - n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig - al) 3= mdio0, Output, gem0_mdc- (MDIO Clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= mdio2, Output, gem2_mdc- (MDIO Clock - 6= mdio3, Output, gem3_mdc- (MDIO Clock) 7= Not Used*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[24]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[24]- (GPIO bank 2) 1= can1, Output, can1_p + * hy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i + * 2c1, Output, i2c1_scl_out- (SCL signal) 3= mdio0, Output, gem0_mdc- (MDI + * O Clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= mdio2, Output, gem2 + * _mdc- (MDIO Clock) 6= mdio3, Output, gem3_mdc- (MDIO Clock) 7= Not Used +*/ #undef IOU_SLCR_MIO_PIN_76_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_76_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_76_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_76_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_76_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_76_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_76_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_76_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_76_L3_SEL_MASK 0x000000E0U -/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/ +/* +* Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_77_L0_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_77_L0_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_77_L0_SEL_MASK -#define IOU_SLCR_MIO_PIN_77_L0_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_77_L0_SEL_SHIFT 1 -#define IOU_SLCR_MIO_PIN_77_L0_SEL_MASK 0x00000002U +#define IOU_SLCR_MIO_PIN_77_L0_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_77_L0_SEL_SHIFT 1 +#define IOU_SLCR_MIO_PIN_77_L0_SEL_MASK 0x00000002U -/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/ +/* +* Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +*/ #undef IOU_SLCR_MIO_PIN_77_L1_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_77_L1_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_77_L1_SEL_MASK -#define IOU_SLCR_MIO_PIN_77_L1_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_77_L1_SEL_SHIFT 2 -#define IOU_SLCR_MIO_PIN_77_L1_SEL_MASK 0x00000004U +#define IOU_SLCR_MIO_PIN_77_L1_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_77_L1_SEL_SHIFT 2 +#define IOU_SLCR_MIO_PIN_77_L1_SEL_MASK 0x00000004U -/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Input, sdio1_cd_n- (SD card detect from connector) 3= Not Used*/ +/* +* Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Input, sdio + * 1_cd_n- (SD card detect from connector) 3= Not Used +*/ #undef IOU_SLCR_MIO_PIN_77_L2_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_77_L2_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_77_L2_SEL_MASK -#define IOU_SLCR_MIO_PIN_77_L2_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_77_L2_SEL_SHIFT 3 -#define IOU_SLCR_MIO_PIN_77_L2_SEL_MASK 0x00000018U +#define IOU_SLCR_MIO_PIN_77_L2_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_77_L2_SEL_SHIFT 3 +#define IOU_SLCR_MIO_PIN_77_L2_SEL_MASK 0x00000018U -/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[25]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[25]- (GPIO bank 2) 1= c - n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign - l) 3= mdio0, Input, gem0_mdio_in- (MDIO Data) 3= mdio0, Output, gem0_mdio_out- (MDIO Data) 4= mdio1, Input, gem1_mdio_in- (MD - O Data) 4= mdio1, Output, gem1_mdio_out- (MDIO Data) 5= mdio2, Input, gem2_mdio_in- (MDIO Data) 5= mdio2, Output, gem2_mdio_o - t- (MDIO Data) 6= mdio3, Input, gem3_mdio_in- (MDIO Data) 6= mdio3, Output, gem3_mdio_out- (MDIO Data) 7= Not Used*/ +/* +* Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[25]- (GPIO bank 2) 0= + * gpio2, Output, gpio_2_pin_out[25]- (GPIO bank 2) 1= can1, Input, can1_ph + * y_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2 + * c1, Output, i2c1_sda_out- (SDA signal) 3= mdio0, Input, gem0_mdio_in- (M + * DIO Data) 3= mdio0, Output, gem0_mdio_out- (MDIO Data) 4= mdio1, Input, + * gem1_mdio_in- (MDIO Data) 4= mdio1, Output, gem1_mdio_out- (MDIO Data) 5 + * = mdio2, Input, gem2_mdio_in- (MDIO Data) 5= mdio2, Output, gem2_mdio_ou + * t- (MDIO Data) 6= mdio3, Input, gem3_mdio_in- (MDIO Data) 6= mdio3, Outp + * ut, gem3_mdio_out- (MDIO Data) 7= Not Used +*/ #undef IOU_SLCR_MIO_PIN_77_L3_SEL_DEFVAL #undef IOU_SLCR_MIO_PIN_77_L3_SEL_SHIFT #undef IOU_SLCR_MIO_PIN_77_L3_SEL_MASK -#define IOU_SLCR_MIO_PIN_77_L3_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_PIN_77_L3_SEL_SHIFT 5 -#define IOU_SLCR_MIO_PIN_77_L3_SEL_MASK 0x000000E0U +#define IOU_SLCR_MIO_PIN_77_L3_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_PIN_77_L3_SEL_SHIFT 5 +#define IOU_SLCR_MIO_PIN_77_L3_SEL_MASK 0x000000E0U -/*Master Tri-state Enable for pin 0, active high*/ +/* +* Master Tri-state Enable for pin 0, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_SHIFT 0 -#define IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_MASK 0x00000001U +#define IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_SHIFT 0 +#define IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_MASK 0x00000001U -/*Master Tri-state Enable for pin 1, active high*/ +/* +* Master Tri-state Enable for pin 1, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_SHIFT 1 -#define IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_MASK 0x00000002U +#define IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_SHIFT 1 +#define IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_MASK 0x00000002U -/*Master Tri-state Enable for pin 2, active high*/ +/* +* Master Tri-state Enable for pin 2, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_SHIFT 2 -#define IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_MASK 0x00000004U +#define IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_SHIFT 2 +#define IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_MASK 0x00000004U -/*Master Tri-state Enable for pin 3, active high*/ +/* +* Master Tri-state Enable for pin 3, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_SHIFT 3 -#define IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_MASK 0x00000008U +#define IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_SHIFT 3 +#define IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_MASK 0x00000008U -/*Master Tri-state Enable for pin 4, active high*/ +/* +* Master Tri-state Enable for pin 4, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_SHIFT 4 -#define IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_MASK 0x00000010U +#define IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_SHIFT 4 +#define IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_MASK 0x00000010U -/*Master Tri-state Enable for pin 5, active high*/ +/* +* Master Tri-state Enable for pin 5, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_SHIFT 5 -#define IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_MASK 0x00000020U +#define IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_SHIFT 5 +#define IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_MASK 0x00000020U -/*Master Tri-state Enable for pin 6, active high*/ +/* +* Master Tri-state Enable for pin 6, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_SHIFT 6 -#define IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_MASK 0x00000040U +#define IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_SHIFT 6 +#define IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_MASK 0x00000040U -/*Master Tri-state Enable for pin 7, active high*/ +/* +* Master Tri-state Enable for pin 7, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_SHIFT 7 -#define IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_MASK 0x00000080U +#define IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_SHIFT 7 +#define IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_MASK 0x00000080U -/*Master Tri-state Enable for pin 8, active high*/ +/* +* Master Tri-state Enable for pin 8, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_SHIFT 8 -#define IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_MASK 0x00000100U +#define IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_SHIFT 8 +#define IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_MASK 0x00000100U -/*Master Tri-state Enable for pin 9, active high*/ +/* +* Master Tri-state Enable for pin 9, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_SHIFT 9 -#define IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_MASK 0x00000200U +#define IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_SHIFT 9 +#define IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_MASK 0x00000200U -/*Master Tri-state Enable for pin 10, active high*/ +/* +* Master Tri-state Enable for pin 10, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_SHIFT 10 -#define IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_MASK 0x00000400U +#define IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_SHIFT 10 +#define IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_MASK 0x00000400U -/*Master Tri-state Enable for pin 11, active high*/ +/* +* Master Tri-state Enable for pin 11, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_SHIFT 11 -#define IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_MASK 0x00000800U +#define IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_SHIFT 11 +#define IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_MASK 0x00000800U -/*Master Tri-state Enable for pin 12, active high*/ +/* +* Master Tri-state Enable for pin 12, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_SHIFT 12 -#define IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_MASK 0x00001000U +#define IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_SHIFT 12 +#define IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_MASK 0x00001000U -/*Master Tri-state Enable for pin 13, active high*/ +/* +* Master Tri-state Enable for pin 13, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_SHIFT 13 -#define IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_MASK 0x00002000U +#define IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_SHIFT 13 +#define IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_MASK 0x00002000U -/*Master Tri-state Enable for pin 14, active high*/ +/* +* Master Tri-state Enable for pin 14, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_SHIFT 14 -#define IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_MASK 0x00004000U +#define IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_SHIFT 14 +#define IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_MASK 0x00004000U -/*Master Tri-state Enable for pin 15, active high*/ +/* +* Master Tri-state Enable for pin 15, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_SHIFT 15 -#define IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_MASK 0x00008000U +#define IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_SHIFT 15 +#define IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_MASK 0x00008000U -/*Master Tri-state Enable for pin 16, active high*/ +/* +* Master Tri-state Enable for pin 16, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_SHIFT 16 -#define IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_MASK 0x00010000U +#define IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_SHIFT 16 +#define IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_MASK 0x00010000U -/*Master Tri-state Enable for pin 17, active high*/ +/* +* Master Tri-state Enable for pin 17, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_SHIFT 17 -#define IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_MASK 0x00020000U +#define IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_SHIFT 17 +#define IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_MASK 0x00020000U -/*Master Tri-state Enable for pin 18, active high*/ +/* +* Master Tri-state Enable for pin 18, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_SHIFT 18 -#define IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_MASK 0x00040000U +#define IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_SHIFT 18 +#define IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_MASK 0x00040000U -/*Master Tri-state Enable for pin 19, active high*/ +/* +* Master Tri-state Enable for pin 19, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_SHIFT 19 -#define IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_MASK 0x00080000U +#define IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_SHIFT 19 +#define IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_MASK 0x00080000U -/*Master Tri-state Enable for pin 20, active high*/ +/* +* Master Tri-state Enable for pin 20, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_SHIFT 20 -#define IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_MASK 0x00100000U +#define IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_SHIFT 20 +#define IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_MASK 0x00100000U -/*Master Tri-state Enable for pin 21, active high*/ +/* +* Master Tri-state Enable for pin 21, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_SHIFT 21 -#define IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_MASK 0x00200000U +#define IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_SHIFT 21 +#define IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_MASK 0x00200000U -/*Master Tri-state Enable for pin 22, active high*/ +/* +* Master Tri-state Enable for pin 22, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_SHIFT 22 -#define IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_MASK 0x00400000U +#define IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_SHIFT 22 +#define IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_MASK 0x00400000U -/*Master Tri-state Enable for pin 23, active high*/ +/* +* Master Tri-state Enable for pin 23, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_SHIFT 23 -#define IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_MASK 0x00800000U +#define IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_SHIFT 23 +#define IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_MASK 0x00800000U -/*Master Tri-state Enable for pin 24, active high*/ +/* +* Master Tri-state Enable for pin 24, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_SHIFT 24 -#define IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_MASK 0x01000000U +#define IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_SHIFT 24 +#define IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_MASK 0x01000000U -/*Master Tri-state Enable for pin 25, active high*/ +/* +* Master Tri-state Enable for pin 25, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_SHIFT 25 -#define IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_MASK 0x02000000U +#define IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_SHIFT 25 +#define IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_MASK 0x02000000U -/*Master Tri-state Enable for pin 26, active high*/ +/* +* Master Tri-state Enable for pin 26, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_SHIFT 26 -#define IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_MASK 0x04000000U +#define IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_SHIFT 26 +#define IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_MASK 0x04000000U -/*Master Tri-state Enable for pin 27, active high*/ +/* +* Master Tri-state Enable for pin 27, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_SHIFT 27 -#define IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_MASK 0x08000000U +#define IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_SHIFT 27 +#define IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_MASK 0x08000000U -/*Master Tri-state Enable for pin 28, active high*/ +/* +* Master Tri-state Enable for pin 28, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_SHIFT 28 -#define IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_MASK 0x10000000U +#define IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_SHIFT 28 +#define IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_MASK 0x10000000U -/*Master Tri-state Enable for pin 29, active high*/ +/* +* Master Tri-state Enable for pin 29, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_SHIFT 29 -#define IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_MASK 0x20000000U +#define IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_SHIFT 29 +#define IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_MASK 0x20000000U -/*Master Tri-state Enable for pin 30, active high*/ +/* +* Master Tri-state Enable for pin 30, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_SHIFT 30 -#define IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_MASK 0x40000000U +#define IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_SHIFT 30 +#define IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_MASK 0x40000000U -/*Master Tri-state Enable for pin 31, active high*/ +/* +* Master Tri-state Enable for pin 31, active high +*/ #undef IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_SHIFT 31 -#define IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_MASK 0x80000000U +#define IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_SHIFT 31 +#define IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_MASK 0x80000000U -/*Master Tri-state Enable for pin 32, active high*/ +/* +* Master Tri-state Enable for pin 32, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_SHIFT 0 -#define IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_MASK 0x00000001U +#define IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_SHIFT 0 +#define IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_MASK 0x00000001U -/*Master Tri-state Enable for pin 33, active high*/ +/* +* Master Tri-state Enable for pin 33, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_SHIFT 1 -#define IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_MASK 0x00000002U +#define IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_SHIFT 1 +#define IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_MASK 0x00000002U -/*Master Tri-state Enable for pin 34, active high*/ +/* +* Master Tri-state Enable for pin 34, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_SHIFT 2 -#define IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_MASK 0x00000004U +#define IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_SHIFT 2 +#define IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_MASK 0x00000004U -/*Master Tri-state Enable for pin 35, active high*/ +/* +* Master Tri-state Enable for pin 35, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_SHIFT 3 -#define IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_MASK 0x00000008U +#define IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_SHIFT 3 +#define IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_MASK 0x00000008U -/*Master Tri-state Enable for pin 36, active high*/ +/* +* Master Tri-state Enable for pin 36, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_SHIFT 4 -#define IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_MASK 0x00000010U +#define IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_SHIFT 4 +#define IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_MASK 0x00000010U -/*Master Tri-state Enable for pin 37, active high*/ +/* +* Master Tri-state Enable for pin 37, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_SHIFT 5 -#define IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_MASK 0x00000020U +#define IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_SHIFT 5 +#define IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_MASK 0x00000020U -/*Master Tri-state Enable for pin 38, active high*/ +/* +* Master Tri-state Enable for pin 38, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_SHIFT 6 -#define IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_MASK 0x00000040U +#define IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_SHIFT 6 +#define IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_MASK 0x00000040U -/*Master Tri-state Enable for pin 39, active high*/ +/* +* Master Tri-state Enable for pin 39, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_SHIFT 7 -#define IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_MASK 0x00000080U +#define IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_SHIFT 7 +#define IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_MASK 0x00000080U -/*Master Tri-state Enable for pin 40, active high*/ +/* +* Master Tri-state Enable for pin 40, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_SHIFT 8 -#define IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_MASK 0x00000100U +#define IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_SHIFT 8 +#define IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_MASK 0x00000100U -/*Master Tri-state Enable for pin 41, active high*/ +/* +* Master Tri-state Enable for pin 41, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_SHIFT 9 -#define IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_MASK 0x00000200U +#define IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_SHIFT 9 +#define IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_MASK 0x00000200U -/*Master Tri-state Enable for pin 42, active high*/ +/* +* Master Tri-state Enable for pin 42, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_SHIFT 10 -#define IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_MASK 0x00000400U +#define IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_SHIFT 10 +#define IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_MASK 0x00000400U -/*Master Tri-state Enable for pin 43, active high*/ +/* +* Master Tri-state Enable for pin 43, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_SHIFT 11 -#define IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_MASK 0x00000800U +#define IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_SHIFT 11 +#define IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_MASK 0x00000800U -/*Master Tri-state Enable for pin 44, active high*/ +/* +* Master Tri-state Enable for pin 44, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_SHIFT 12 -#define IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_MASK 0x00001000U +#define IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_SHIFT 12 +#define IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_MASK 0x00001000U -/*Master Tri-state Enable for pin 45, active high*/ +/* +* Master Tri-state Enable for pin 45, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_SHIFT 13 -#define IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_MASK 0x00002000U +#define IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_SHIFT 13 +#define IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_MASK 0x00002000U -/*Master Tri-state Enable for pin 46, active high*/ +/* +* Master Tri-state Enable for pin 46, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_SHIFT 14 -#define IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_MASK 0x00004000U +#define IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_SHIFT 14 +#define IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_MASK 0x00004000U -/*Master Tri-state Enable for pin 47, active high*/ +/* +* Master Tri-state Enable for pin 47, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_SHIFT 15 -#define IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_MASK 0x00008000U +#define IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_SHIFT 15 +#define IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_MASK 0x00008000U -/*Master Tri-state Enable for pin 48, active high*/ +/* +* Master Tri-state Enable for pin 48, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_SHIFT 16 -#define IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_MASK 0x00010000U +#define IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_SHIFT 16 +#define IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_MASK 0x00010000U -/*Master Tri-state Enable for pin 49, active high*/ +/* +* Master Tri-state Enable for pin 49, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_SHIFT 17 -#define IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_MASK 0x00020000U +#define IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_SHIFT 17 +#define IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_MASK 0x00020000U -/*Master Tri-state Enable for pin 50, active high*/ +/* +* Master Tri-state Enable for pin 50, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_SHIFT 18 -#define IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_MASK 0x00040000U +#define IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_SHIFT 18 +#define IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_MASK 0x00040000U -/*Master Tri-state Enable for pin 51, active high*/ +/* +* Master Tri-state Enable for pin 51, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_SHIFT 19 -#define IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_MASK 0x00080000U +#define IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_SHIFT 19 +#define IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_MASK 0x00080000U -/*Master Tri-state Enable for pin 52, active high*/ +/* +* Master Tri-state Enable for pin 52, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_SHIFT 20 -#define IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_MASK 0x00100000U +#define IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_SHIFT 20 +#define IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_MASK 0x00100000U -/*Master Tri-state Enable for pin 53, active high*/ +/* +* Master Tri-state Enable for pin 53, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_SHIFT 21 -#define IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_MASK 0x00200000U +#define IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_SHIFT 21 +#define IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_MASK 0x00200000U -/*Master Tri-state Enable for pin 54, active high*/ +/* +* Master Tri-state Enable for pin 54, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_SHIFT 22 -#define IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_MASK 0x00400000U +#define IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_SHIFT 22 +#define IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_MASK 0x00400000U -/*Master Tri-state Enable for pin 55, active high*/ +/* +* Master Tri-state Enable for pin 55, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_SHIFT 23 -#define IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_MASK 0x00800000U +#define IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_SHIFT 23 +#define IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_MASK 0x00800000U -/*Master Tri-state Enable for pin 56, active high*/ +/* +* Master Tri-state Enable for pin 56, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_SHIFT 24 -#define IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_MASK 0x01000000U +#define IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_SHIFT 24 +#define IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_MASK 0x01000000U -/*Master Tri-state Enable for pin 57, active high*/ +/* +* Master Tri-state Enable for pin 57, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_SHIFT 25 -#define IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_MASK 0x02000000U +#define IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_SHIFT 25 +#define IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_MASK 0x02000000U -/*Master Tri-state Enable for pin 58, active high*/ +/* +* Master Tri-state Enable for pin 58, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_SHIFT 26 -#define IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_MASK 0x04000000U +#define IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_SHIFT 26 +#define IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_MASK 0x04000000U -/*Master Tri-state Enable for pin 59, active high*/ +/* +* Master Tri-state Enable for pin 59, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_SHIFT 27 -#define IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_MASK 0x08000000U +#define IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_SHIFT 27 +#define IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_MASK 0x08000000U -/*Master Tri-state Enable for pin 60, active high*/ +/* +* Master Tri-state Enable for pin 60, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_SHIFT 28 -#define IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_MASK 0x10000000U +#define IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_SHIFT 28 +#define IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_MASK 0x10000000U -/*Master Tri-state Enable for pin 61, active high*/ +/* +* Master Tri-state Enable for pin 61, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_SHIFT 29 -#define IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_MASK 0x20000000U +#define IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_SHIFT 29 +#define IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_MASK 0x20000000U -/*Master Tri-state Enable for pin 62, active high*/ +/* +* Master Tri-state Enable for pin 62, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_SHIFT 30 -#define IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_MASK 0x40000000U +#define IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_SHIFT 30 +#define IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_MASK 0x40000000U -/*Master Tri-state Enable for pin 63, active high*/ +/* +* Master Tri-state Enable for pin 63, active high +*/ #undef IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_DEFVAL 0xFFFFFFFF -#define IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_SHIFT 31 -#define IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_MASK 0x80000000U +#define IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_DEFVAL 0xFFFFFFFF +#define IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_SHIFT 31 +#define IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_MASK 0x80000000U -/*Master Tri-state Enable for pin 64, active high*/ +/* +* Master Tri-state Enable for pin 64, active high +*/ #undef IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_DEFVAL 0x00003FFF -#define IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_SHIFT 0 -#define IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_MASK 0x00000001U +#define IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_DEFVAL 0x00003FFF +#define IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_SHIFT 0 +#define IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_MASK 0x00000001U -/*Master Tri-state Enable for pin 65, active high*/ +/* +* Master Tri-state Enable for pin 65, active high +*/ #undef IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_DEFVAL 0x00003FFF -#define IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_SHIFT 1 -#define IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_MASK 0x00000002U +#define IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_DEFVAL 0x00003FFF +#define IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_SHIFT 1 +#define IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_MASK 0x00000002U -/*Master Tri-state Enable for pin 66, active high*/ +/* +* Master Tri-state Enable for pin 66, active high +*/ #undef IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_DEFVAL 0x00003FFF -#define IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_SHIFT 2 -#define IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_MASK 0x00000004U +#define IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_DEFVAL 0x00003FFF +#define IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_SHIFT 2 +#define IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_MASK 0x00000004U -/*Master Tri-state Enable for pin 67, active high*/ +/* +* Master Tri-state Enable for pin 67, active high +*/ #undef IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_DEFVAL 0x00003FFF -#define IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_SHIFT 3 -#define IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_MASK 0x00000008U +#define IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_DEFVAL 0x00003FFF +#define IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_SHIFT 3 +#define IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_MASK 0x00000008U -/*Master Tri-state Enable for pin 68, active high*/ +/* +* Master Tri-state Enable for pin 68, active high +*/ #undef IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_DEFVAL 0x00003FFF -#define IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_SHIFT 4 -#define IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_MASK 0x00000010U +#define IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_DEFVAL 0x00003FFF +#define IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_SHIFT 4 +#define IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_MASK 0x00000010U -/*Master Tri-state Enable for pin 69, active high*/ +/* +* Master Tri-state Enable for pin 69, active high +*/ #undef IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_DEFVAL 0x00003FFF -#define IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_SHIFT 5 -#define IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_MASK 0x00000020U +#define IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_DEFVAL 0x00003FFF +#define IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_SHIFT 5 +#define IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_MASK 0x00000020U -/*Master Tri-state Enable for pin 70, active high*/ +/* +* Master Tri-state Enable for pin 70, active high +*/ #undef IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_DEFVAL 0x00003FFF -#define IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_SHIFT 6 -#define IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_MASK 0x00000040U +#define IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_DEFVAL 0x00003FFF +#define IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_SHIFT 6 +#define IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_MASK 0x00000040U -/*Master Tri-state Enable for pin 71, active high*/ +/* +* Master Tri-state Enable for pin 71, active high +*/ #undef IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_DEFVAL 0x00003FFF -#define IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_SHIFT 7 -#define IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_MASK 0x00000080U +#define IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_DEFVAL 0x00003FFF +#define IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_SHIFT 7 +#define IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_MASK 0x00000080U -/*Master Tri-state Enable for pin 72, active high*/ +/* +* Master Tri-state Enable for pin 72, active high +*/ #undef IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_DEFVAL 0x00003FFF -#define IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_SHIFT 8 -#define IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_MASK 0x00000100U +#define IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_DEFVAL 0x00003FFF +#define IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_SHIFT 8 +#define IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_MASK 0x00000100U -/*Master Tri-state Enable for pin 73, active high*/ +/* +* Master Tri-state Enable for pin 73, active high +*/ #undef IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_DEFVAL 0x00003FFF -#define IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_SHIFT 9 -#define IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_MASK 0x00000200U +#define IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_DEFVAL 0x00003FFF +#define IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_SHIFT 9 +#define IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_MASK 0x00000200U -/*Master Tri-state Enable for pin 74, active high*/ +/* +* Master Tri-state Enable for pin 74, active high +*/ #undef IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_DEFVAL 0x00003FFF -#define IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_SHIFT 10 -#define IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_MASK 0x00000400U +#define IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_DEFVAL 0x00003FFF +#define IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_SHIFT 10 +#define IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_MASK 0x00000400U -/*Master Tri-state Enable for pin 75, active high*/ +/* +* Master Tri-state Enable for pin 75, active high +*/ #undef IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_DEFVAL 0x00003FFF -#define IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_SHIFT 11 -#define IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_MASK 0x00000800U +#define IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_DEFVAL 0x00003FFF +#define IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_SHIFT 11 +#define IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_MASK 0x00000800U -/*Master Tri-state Enable for pin 76, active high*/ +/* +* Master Tri-state Enable for pin 76, active high +*/ #undef IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_DEFVAL 0x00003FFF -#define IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_SHIFT 12 -#define IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_MASK 0x00001000U +#define IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_DEFVAL 0x00003FFF +#define IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_SHIFT 12 +#define IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_MASK 0x00001000U -/*Master Tri-state Enable for pin 77, active high*/ +/* +* Master Tri-state Enable for pin 77, active high +*/ #undef IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_DEFVAL #undef IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_SHIFT #undef IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_MASK -#define IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_DEFVAL 0x00003FFF -#define IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_SHIFT 13 -#define IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_MASK 0x00002000U +#define IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_DEFVAL 0x00003FFF +#define IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_SHIFT 13 +#define IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_MASK 0x00002000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_SHIFT 0 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_MASK 0x00000001U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_MASK 0x00000001U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_SHIFT 1 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_MASK 0x00000002U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_MASK 0x00000002U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_SHIFT 2 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_MASK 0x00000004U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_MASK 0x00000004U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_SHIFT 3 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_MASK 0x00000008U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_MASK 0x00000008U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_SHIFT 4 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_MASK 0x00000010U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_MASK 0x00000010U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_SHIFT 5 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_MASK 0x00000020U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_MASK 0x00000020U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_SHIFT 6 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_MASK 0x00000040U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_MASK 0x00000040U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_SHIFT 7 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_MASK 0x00000080U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_MASK 0x00000080U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_SHIFT 8 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_MASK 0x00000100U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_MASK 0x00000100U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_SHIFT 9 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_MASK 0x00000200U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_MASK 0x00000200U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_SHIFT 10 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_MASK 0x00000400U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_MASK 0x00000400U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_SHIFT 11 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_MASK 0x00000800U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_MASK 0x00000800U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_SHIFT 12 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_MASK 0x00001000U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_MASK 0x00001000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_SHIFT 13 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_MASK 0x00002000U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_MASK 0x00002000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_SHIFT 14 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_MASK 0x00004000U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_MASK 0x00004000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_SHIFT 15 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_MASK 0x00008000U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_MASK 0x00008000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_SHIFT 16 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_MASK 0x00010000U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_MASK 0x00010000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_SHIFT 17 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_MASK 0x00020000U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_MASK 0x00020000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_SHIFT 18 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_MASK 0x00040000U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_MASK 0x00040000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_SHIFT 19 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_MASK 0x00080000U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_MASK 0x00080000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_SHIFT 20 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_MASK 0x00100000U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_MASK 0x00100000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_SHIFT 21 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_MASK 0x00200000U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_MASK 0x00200000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_SHIFT 22 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_MASK 0x00400000U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_MASK 0x00400000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_SHIFT 23 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_MASK 0x00800000U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_MASK 0x00800000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_SHIFT 24 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_MASK 0x01000000U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_MASK 0x01000000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_DEFVAL #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_SHIFT #undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_MASK -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_DEFVAL -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_SHIFT 25 -#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_MASK 0x02000000U +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_DEFVAL +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_MASK 0x02000000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_SHIFT 0 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_MASK 0x00000001U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_MASK 0x00000001U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_SHIFT 1 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_MASK 0x00000002U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_MASK 0x00000002U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_SHIFT 2 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_MASK 0x00000004U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_MASK 0x00000004U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_SHIFT 3 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_MASK 0x00000008U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_MASK 0x00000008U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_SHIFT 4 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_MASK 0x00000010U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_MASK 0x00000010U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_SHIFT 5 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_MASK 0x00000020U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_MASK 0x00000020U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_SHIFT 6 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_MASK 0x00000040U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_MASK 0x00000040U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_SHIFT 7 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_MASK 0x00000080U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_MASK 0x00000080U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_SHIFT 8 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_MASK 0x00000100U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_MASK 0x00000100U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_SHIFT 9 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_MASK 0x00000200U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_MASK 0x00000200U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_SHIFT 10 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_MASK 0x00000400U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_MASK 0x00000400U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_SHIFT 11 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_MASK 0x00000800U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_MASK 0x00000800U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_SHIFT 12 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_MASK 0x00001000U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_MASK 0x00001000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_SHIFT 13 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_MASK 0x00002000U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_MASK 0x00002000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_SHIFT 14 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_MASK 0x00004000U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_MASK 0x00004000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_SHIFT 15 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_MASK 0x00008000U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_MASK 0x00008000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_SHIFT 16 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_MASK 0x00010000U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_MASK 0x00010000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_SHIFT 17 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_MASK 0x00020000U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_MASK 0x00020000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_SHIFT 18 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_MASK 0x00040000U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_MASK 0x00040000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_SHIFT 19 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_MASK 0x00080000U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_MASK 0x00080000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_SHIFT 20 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_MASK 0x00100000U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_MASK 0x00100000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_SHIFT 21 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_MASK 0x00200000U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_MASK 0x00200000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_SHIFT 22 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_MASK 0x00400000U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_MASK 0x00400000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_SHIFT 23 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_MASK 0x00800000U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_MASK 0x00800000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_SHIFT 24 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_MASK 0x01000000U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_MASK 0x01000000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_DEFVAL #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_SHIFT #undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_MASK -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_DEFVAL -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_SHIFT 25 -#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_MASK 0x02000000U +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_DEFVAL +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_MASK 0x02000000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT 0 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK 0x00000001U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK 0x00000001U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT 1 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK 0x00000002U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK 0x00000002U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT 2 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK 0x00000004U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK 0x00000004U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT 3 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK 0x00000008U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK 0x00000008U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT 4 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK 0x00000010U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK 0x00000010U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT 5 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK 0x00000020U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK 0x00000020U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT 6 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK 0x00000040U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK 0x00000040U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT 7 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK 0x00000080U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK 0x00000080U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT 8 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK 0x00000100U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK 0x00000100U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT 9 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK 0x00000200U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK 0x00000200U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT 10 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK 0x00000400U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK 0x00000400U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT 11 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK 0x00000800U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK 0x00000800U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT 12 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK 0x00001000U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK 0x00001000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT 13 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK 0x00002000U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK 0x00002000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT 14 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK 0x00004000U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK 0x00004000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT 15 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK 0x00008000U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK 0x00008000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT 16 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK 0x00010000U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK 0x00010000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT 17 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK 0x00020000U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK 0x00020000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT 18 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK 0x00040000U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK 0x00040000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT 19 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK 0x00080000U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK 0x00080000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT 20 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK 0x00100000U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK 0x00100000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT 21 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK 0x00200000U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK 0x00200000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT 22 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK 0x00400000U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK 0x00400000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT 23 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK 0x00800000U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK 0x00800000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT 24 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK 0x01000000U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK 0x01000000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT #undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT 25 -#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK 0x02000000U +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK 0x02000000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT 0 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK 0x00000001U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK 0x00000001U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT 1 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK 0x00000002U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK 0x00000002U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT 2 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK 0x00000004U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK 0x00000004U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT 3 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK 0x00000008U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK 0x00000008U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT 4 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK 0x00000010U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK 0x00000010U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT 5 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK 0x00000020U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK 0x00000020U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT 6 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK 0x00000040U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK 0x00000040U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT 7 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK 0x00000080U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK 0x00000080U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT 8 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK 0x00000100U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK 0x00000100U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT 9 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK 0x00000200U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK 0x00000200U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT 10 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK 0x00000400U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK 0x00000400U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT 11 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK 0x00000800U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK 0x00000800U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT 12 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK 0x00001000U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK 0x00001000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT 13 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK 0x00002000U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK 0x00002000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT 14 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK 0x00004000U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK 0x00004000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT 15 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK 0x00008000U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK 0x00008000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT 16 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK 0x00010000U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK 0x00010000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT 17 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK 0x00020000U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK 0x00020000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT 18 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK 0x00040000U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK 0x00040000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT 19 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK 0x00080000U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK 0x00080000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT 20 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK 0x00100000U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK 0x00100000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT 21 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK 0x00200000U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK 0x00200000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT 22 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK 0x00400000U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK 0x00400000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT 23 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK 0x00800000U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK 0x00800000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT 24 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK 0x01000000U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK 0x01000000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT #undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT 25 -#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK 0x02000000U +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK 0x02000000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_SHIFT 0 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_MASK 0x00000001U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_MASK 0x00000001U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_SHIFT 1 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_MASK 0x00000002U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_MASK 0x00000002U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_SHIFT 2 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_MASK 0x00000004U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_MASK 0x00000004U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_SHIFT 3 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_MASK 0x00000008U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_MASK 0x00000008U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_SHIFT 4 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_MASK 0x00000010U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_MASK 0x00000010U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_SHIFT 5 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_MASK 0x00000020U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_MASK 0x00000020U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_SHIFT 6 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_MASK 0x00000040U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_MASK 0x00000040U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_SHIFT 7 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_MASK 0x00000080U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_MASK 0x00000080U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_SHIFT 8 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_MASK 0x00000100U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_MASK 0x00000100U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_SHIFT 9 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_MASK 0x00000200U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_MASK 0x00000200U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_SHIFT 10 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_MASK 0x00000400U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_MASK 0x00000400U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_SHIFT 11 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_MASK 0x00000800U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_MASK 0x00000800U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_SHIFT 12 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_MASK 0x00001000U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_MASK 0x00001000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_SHIFT 13 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_MASK 0x00002000U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_MASK 0x00002000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_SHIFT 14 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_MASK 0x00004000U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_MASK 0x00004000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_SHIFT 15 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_MASK 0x00008000U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_MASK 0x00008000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_SHIFT 16 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_MASK 0x00010000U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_MASK 0x00010000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_SHIFT 17 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_MASK 0x00020000U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_MASK 0x00020000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_SHIFT 18 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_MASK 0x00040000U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_MASK 0x00040000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_SHIFT 19 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_MASK 0x00080000U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_MASK 0x00080000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_SHIFT 20 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_MASK 0x00100000U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_MASK 0x00100000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_SHIFT 21 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_MASK 0x00200000U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_MASK 0x00200000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_SHIFT 22 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_MASK 0x00400000U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_MASK 0x00400000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_SHIFT 23 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_MASK 0x00800000U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_MASK 0x00800000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_SHIFT 24 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_MASK 0x01000000U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_MASK 0x01000000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_DEFVAL #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_SHIFT #undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_MASK -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_DEFVAL -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_SHIFT 25 -#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_MASK 0x02000000U +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_DEFVAL +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_MASK 0x02000000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT 0 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK 0x00000001U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK 0x00000001U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT 1 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK 0x00000002U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK 0x00000002U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT 2 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK 0x00000004U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK 0x00000004U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT 3 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK 0x00000008U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK 0x00000008U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT 4 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK 0x00000010U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK 0x00000010U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT 5 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK 0x00000020U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK 0x00000020U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT 6 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK 0x00000040U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK 0x00000040U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT 7 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK 0x00000080U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK 0x00000080U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT 8 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK 0x00000100U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK 0x00000100U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT 9 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK 0x00000200U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK 0x00000200U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT 10 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK 0x00000400U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK 0x00000400U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT 11 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK 0x00000800U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK 0x00000800U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT 12 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK 0x00001000U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK 0x00001000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT 13 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK 0x00002000U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK 0x00002000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT 14 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK 0x00004000U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK 0x00004000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT 15 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK 0x00008000U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK 0x00008000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT 16 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK 0x00010000U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK 0x00010000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT 17 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK 0x00020000U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK 0x00020000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT 18 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK 0x00040000U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK 0x00040000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT 19 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK 0x00080000U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK 0x00080000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT 20 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK 0x00100000U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK 0x00100000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT 21 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK 0x00200000U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK 0x00200000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT 22 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK 0x00400000U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK 0x00400000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT 23 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK 0x00800000U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK 0x00800000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT 24 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK 0x01000000U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK 0x01000000U -/*Each bit applies to a single IO. Bit 0 for MIO[0].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[0]. +*/ #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT #undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT 25 -#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK 0x02000000U +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK 0x02000000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_SHIFT 0 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_MASK 0x00000001U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_MASK 0x00000001U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_SHIFT 1 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_MASK 0x00000002U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_MASK 0x00000002U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_SHIFT 2 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_MASK 0x00000004U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_MASK 0x00000004U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_SHIFT 3 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_MASK 0x00000008U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_MASK 0x00000008U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_SHIFT 4 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_MASK 0x00000010U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_MASK 0x00000010U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_SHIFT 5 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_MASK 0x00000020U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_MASK 0x00000020U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_SHIFT 6 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_MASK 0x00000040U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_MASK 0x00000040U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_SHIFT 7 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_MASK 0x00000080U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_MASK 0x00000080U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_SHIFT 8 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_MASK 0x00000100U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_MASK 0x00000100U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_SHIFT 9 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_MASK 0x00000200U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_MASK 0x00000200U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_SHIFT 10 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_MASK 0x00000400U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_MASK 0x00000400U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_SHIFT 11 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_MASK 0x00000800U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_MASK 0x00000800U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_SHIFT 12 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_MASK 0x00001000U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_MASK 0x00001000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_SHIFT 13 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_MASK 0x00002000U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_MASK 0x00002000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_SHIFT 14 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_MASK 0x00004000U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_MASK 0x00004000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_SHIFT 15 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_MASK 0x00008000U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_MASK 0x00008000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_SHIFT 16 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_MASK 0x00010000U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_MASK 0x00010000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_SHIFT 17 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_MASK 0x00020000U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_MASK 0x00020000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_SHIFT 18 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_MASK 0x00040000U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_MASK 0x00040000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_SHIFT 19 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_MASK 0x00080000U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_MASK 0x00080000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_SHIFT 20 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_MASK 0x00100000U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_MASK 0x00100000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_SHIFT 21 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_MASK 0x00200000U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_MASK 0x00200000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_SHIFT 22 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_MASK 0x00400000U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_MASK 0x00400000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_SHIFT 23 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_MASK 0x00800000U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_MASK 0x00800000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_SHIFT 24 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_MASK 0x01000000U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_MASK 0x01000000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_DEFVAL #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_SHIFT #undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_MASK -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_DEFVAL -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_SHIFT 25 -#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_MASK 0x02000000U +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_DEFVAL +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_MASK 0x02000000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_SHIFT 0 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_MASK 0x00000001U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_MASK 0x00000001U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_SHIFT 1 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_MASK 0x00000002U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_MASK 0x00000002U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_SHIFT 2 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_MASK 0x00000004U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_MASK 0x00000004U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_SHIFT 3 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_MASK 0x00000008U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_MASK 0x00000008U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_SHIFT 4 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_MASK 0x00000010U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_MASK 0x00000010U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_SHIFT 5 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_MASK 0x00000020U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_MASK 0x00000020U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_SHIFT 6 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_MASK 0x00000040U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_MASK 0x00000040U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_SHIFT 7 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_MASK 0x00000080U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_MASK 0x00000080U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_SHIFT 8 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_MASK 0x00000100U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_MASK 0x00000100U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_SHIFT 9 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_MASK 0x00000200U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_MASK 0x00000200U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_SHIFT 10 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_MASK 0x00000400U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_MASK 0x00000400U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_SHIFT 11 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_MASK 0x00000800U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_MASK 0x00000800U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_SHIFT 12 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_MASK 0x00001000U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_MASK 0x00001000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_SHIFT 13 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_MASK 0x00002000U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_MASK 0x00002000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_SHIFT 14 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_MASK 0x00004000U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_MASK 0x00004000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_SHIFT 15 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_MASK 0x00008000U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_MASK 0x00008000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_SHIFT 16 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_MASK 0x00010000U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_MASK 0x00010000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_SHIFT 17 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_MASK 0x00020000U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_MASK 0x00020000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_SHIFT 18 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_MASK 0x00040000U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_MASK 0x00040000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_SHIFT 19 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_MASK 0x00080000U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_MASK 0x00080000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_SHIFT 20 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_MASK 0x00100000U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_MASK 0x00100000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_SHIFT 21 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_MASK 0x00200000U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_MASK 0x00200000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_SHIFT 22 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_MASK 0x00400000U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_MASK 0x00400000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_SHIFT 23 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_MASK 0x00800000U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_MASK 0x00800000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_SHIFT 24 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_MASK 0x01000000U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_MASK 0x01000000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_DEFVAL #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_SHIFT #undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_MASK -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_DEFVAL -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_SHIFT 25 -#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_MASK 0x02000000U +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_DEFVAL +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_MASK 0x02000000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT 0 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK 0x00000001U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK 0x00000001U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT 1 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK 0x00000002U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK 0x00000002U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT 2 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK 0x00000004U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK 0x00000004U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT 3 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK 0x00000008U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK 0x00000008U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT 4 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK 0x00000010U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK 0x00000010U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT 5 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK 0x00000020U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK 0x00000020U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT 6 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK 0x00000040U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK 0x00000040U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT 7 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK 0x00000080U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK 0x00000080U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT 8 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK 0x00000100U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK 0x00000100U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT 9 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK 0x00000200U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK 0x00000200U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT 10 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK 0x00000400U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK 0x00000400U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT 11 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK 0x00000800U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK 0x00000800U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT 12 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK 0x00001000U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK 0x00001000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT 13 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK 0x00002000U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK 0x00002000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT 14 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK 0x00004000U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK 0x00004000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT 15 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK 0x00008000U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK 0x00008000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT 16 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK 0x00010000U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK 0x00010000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT 17 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK 0x00020000U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK 0x00020000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT 18 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK 0x00040000U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK 0x00040000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT 19 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK 0x00080000U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK 0x00080000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT 20 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK 0x00100000U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK 0x00100000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT 21 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK 0x00200000U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK 0x00200000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT 22 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK 0x00400000U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK 0x00400000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT 23 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK 0x00800000U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK 0x00800000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT 24 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK 0x01000000U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK 0x01000000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT #undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT 25 -#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK 0x02000000U +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK 0x02000000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT 0 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK 0x00000001U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK 0x00000001U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT 1 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK 0x00000002U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK 0x00000002U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT 2 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK 0x00000004U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK 0x00000004U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT 3 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK 0x00000008U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK 0x00000008U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT 4 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK 0x00000010U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK 0x00000010U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT 5 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK 0x00000020U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK 0x00000020U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT 6 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK 0x00000040U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK 0x00000040U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT 7 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK 0x00000080U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK 0x00000080U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT 8 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK 0x00000100U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK 0x00000100U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT 9 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK 0x00000200U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK 0x00000200U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT 10 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK 0x00000400U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK 0x00000400U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT 11 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK 0x00000800U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK 0x00000800U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT 12 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK 0x00001000U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK 0x00001000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT 13 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK 0x00002000U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK 0x00002000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT 14 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK 0x00004000U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK 0x00004000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT 15 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK 0x00008000U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK 0x00008000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT 16 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK 0x00010000U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK 0x00010000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT 17 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK 0x00020000U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK 0x00020000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT 18 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK 0x00040000U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK 0x00040000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT 19 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK 0x00080000U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK 0x00080000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT 20 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK 0x00100000U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK 0x00100000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT 21 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK 0x00200000U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK 0x00200000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT 22 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK 0x00400000U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK 0x00400000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT 23 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK 0x00800000U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK 0x00800000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT 24 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK 0x01000000U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK 0x01000000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT #undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT 25 -#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK 0x02000000U +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK 0x02000000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_SHIFT 12 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_MASK 0x00001000U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_SHIFT 12 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_MASK 0x00001000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_SHIFT 13 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_MASK 0x00002000U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_SHIFT 13 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_MASK 0x00002000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_SHIFT 14 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_MASK 0x00004000U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_SHIFT 14 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_MASK 0x00004000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_SHIFT 15 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_MASK 0x00008000U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_SHIFT 15 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_MASK 0x00008000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_SHIFT 16 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_MASK 0x00010000U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_SHIFT 16 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_MASK 0x00010000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_SHIFT 17 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_MASK 0x00020000U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_SHIFT 17 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_MASK 0x00020000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_SHIFT 18 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_MASK 0x00040000U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_SHIFT 18 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_MASK 0x00040000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_SHIFT 19 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_MASK 0x00080000U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_SHIFT 19 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_MASK 0x00080000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_SHIFT 20 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_MASK 0x00100000U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_SHIFT 20 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_MASK 0x00100000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_SHIFT 21 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_MASK 0x00200000U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_SHIFT 21 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_MASK 0x00200000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_SHIFT 22 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_MASK 0x00400000U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_SHIFT 22 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_MASK 0x00400000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_SHIFT 23 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_MASK 0x00800000U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_SHIFT 23 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_MASK 0x00800000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_SHIFT 24 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_MASK 0x01000000U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_SHIFT 24 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_MASK 0x01000000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_SHIFT 25 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_MASK 0x02000000U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_SHIFT 25 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_MASK 0x02000000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_SHIFT 0 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_MASK 0x00000001U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_SHIFT 0 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_MASK 0x00000001U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_SHIFT 1 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_MASK 0x00000002U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_SHIFT 1 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_MASK 0x00000002U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_SHIFT 2 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_MASK 0x00000004U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_SHIFT 2 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_MASK 0x00000004U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_SHIFT 3 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_MASK 0x00000008U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_SHIFT 3 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_MASK 0x00000008U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_SHIFT 4 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_MASK 0x00000010U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_SHIFT 4 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_MASK 0x00000010U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_SHIFT 5 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_MASK 0x00000020U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_SHIFT 5 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_MASK 0x00000020U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_SHIFT 6 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_MASK 0x00000040U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_SHIFT 6 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_MASK 0x00000040U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_SHIFT 7 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_MASK 0x00000080U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_SHIFT 7 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_MASK 0x00000080U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_SHIFT 8 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_MASK 0x00000100U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_SHIFT 8 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_MASK 0x00000100U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_SHIFT 9 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_MASK 0x00000200U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_SHIFT 9 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_MASK 0x00000200U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_SHIFT 10 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_MASK 0x00000400U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_SHIFT 10 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_MASK 0x00000400U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_DEFVAL #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_SHIFT #undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_MASK -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_DEFVAL -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_SHIFT 11 -#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_MASK 0x00000800U +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_DEFVAL +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_SHIFT 11 +#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_MASK 0x00000800U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT 0 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK 0x00000001U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK 0x00000001U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT 1 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK 0x00000002U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK 0x00000002U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT 2 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK 0x00000004U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK 0x00000004U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT 3 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK 0x00000008U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK 0x00000008U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT 4 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK 0x00000010U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK 0x00000010U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT 5 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK 0x00000020U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK 0x00000020U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT 6 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK 0x00000040U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK 0x00000040U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT 7 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK 0x00000080U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK 0x00000080U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT 8 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK 0x00000100U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK 0x00000100U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT 9 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK 0x00000200U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK 0x00000200U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT 10 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK 0x00000400U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK 0x00000400U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT 11 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK 0x00000800U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK 0x00000800U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT 12 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK 0x00001000U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK 0x00001000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT 13 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK 0x00002000U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK 0x00002000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT 14 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK 0x00004000U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK 0x00004000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT 15 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK 0x00008000U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK 0x00008000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT 16 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK 0x00010000U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK 0x00010000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT 17 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK 0x00020000U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK 0x00020000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT 18 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK 0x00040000U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK 0x00040000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT 19 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK 0x00080000U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK 0x00080000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT 20 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK 0x00100000U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK 0x00100000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT 21 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK 0x00200000U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK 0x00200000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT 22 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK 0x00400000U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK 0x00400000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT 23 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK 0x00800000U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK 0x00800000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT 24 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK 0x01000000U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK 0x01000000U -/*Each bit applies to a single IO. Bit 0 for MIO[26].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[26]. +*/ #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT #undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT 25 -#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK 0x02000000U +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK 0x02000000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_SHIFT 0 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_MASK 0x00000001U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_MASK 0x00000001U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_SHIFT 1 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_MASK 0x00000002U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_MASK 0x00000002U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_SHIFT 2 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_MASK 0x00000004U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_MASK 0x00000004U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_SHIFT 3 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_MASK 0x00000008U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_MASK 0x00000008U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_SHIFT 4 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_MASK 0x00000010U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_MASK 0x00000010U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_SHIFT 5 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_MASK 0x00000020U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_MASK 0x00000020U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_SHIFT 6 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_MASK 0x00000040U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_MASK 0x00000040U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_SHIFT 7 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_MASK 0x00000080U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_MASK 0x00000080U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_SHIFT 8 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_MASK 0x00000100U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_MASK 0x00000100U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_SHIFT 9 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_MASK 0x00000200U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_MASK 0x00000200U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_SHIFT 10 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_MASK 0x00000400U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_MASK 0x00000400U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_SHIFT 11 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_MASK 0x00000800U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_MASK 0x00000800U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_SHIFT 12 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_MASK 0x00001000U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_MASK 0x00001000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_SHIFT 13 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_MASK 0x00002000U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_MASK 0x00002000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_SHIFT 14 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_MASK 0x00004000U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_MASK 0x00004000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_SHIFT 15 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_MASK 0x00008000U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_MASK 0x00008000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_SHIFT 16 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_MASK 0x00010000U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_MASK 0x00010000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_SHIFT 17 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_MASK 0x00020000U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_MASK 0x00020000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_SHIFT 18 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_MASK 0x00040000U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_MASK 0x00040000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_SHIFT 19 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_MASK 0x00080000U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_MASK 0x00080000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_SHIFT 20 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_MASK 0x00100000U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_MASK 0x00100000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_SHIFT 21 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_MASK 0x00200000U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_MASK 0x00200000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_SHIFT 22 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_MASK 0x00400000U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_MASK 0x00400000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_SHIFT 23 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_MASK 0x00800000U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_MASK 0x00800000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_SHIFT 24 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_MASK 0x01000000U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_MASK 0x01000000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_DEFVAL #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_SHIFT #undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_MASK -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_DEFVAL -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_SHIFT 25 -#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_MASK 0x02000000U +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_DEFVAL +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_MASK 0x02000000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_SHIFT 0 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_MASK 0x00000001U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_MASK 0x00000001U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_SHIFT 1 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_MASK 0x00000002U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_MASK 0x00000002U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_SHIFT 2 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_MASK 0x00000004U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_MASK 0x00000004U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_SHIFT 3 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_MASK 0x00000008U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_MASK 0x00000008U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_SHIFT 4 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_MASK 0x00000010U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_MASK 0x00000010U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_SHIFT 5 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_MASK 0x00000020U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_MASK 0x00000020U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_SHIFT 6 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_MASK 0x00000040U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_MASK 0x00000040U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_SHIFT 7 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_MASK 0x00000080U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_MASK 0x00000080U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_SHIFT 8 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_MASK 0x00000100U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_MASK 0x00000100U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_SHIFT 9 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_MASK 0x00000200U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_MASK 0x00000200U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_SHIFT 10 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_MASK 0x00000400U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_MASK 0x00000400U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_SHIFT 11 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_MASK 0x00000800U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_MASK 0x00000800U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_SHIFT 12 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_MASK 0x00001000U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_MASK 0x00001000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_SHIFT 13 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_MASK 0x00002000U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_MASK 0x00002000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_SHIFT 14 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_MASK 0x00004000U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_MASK 0x00004000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_SHIFT 15 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_MASK 0x00008000U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_MASK 0x00008000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_SHIFT 16 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_MASK 0x00010000U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_MASK 0x00010000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_SHIFT 17 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_MASK 0x00020000U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_MASK 0x00020000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_SHIFT 18 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_MASK 0x00040000U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_MASK 0x00040000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_SHIFT 19 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_MASK 0x00080000U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_MASK 0x00080000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_SHIFT 20 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_MASK 0x00100000U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_MASK 0x00100000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_SHIFT 21 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_MASK 0x00200000U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_MASK 0x00200000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_SHIFT 22 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_MASK 0x00400000U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_MASK 0x00400000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_SHIFT 23 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_MASK 0x00800000U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_MASK 0x00800000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_SHIFT 24 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_MASK 0x01000000U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_MASK 0x01000000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_DEFVAL #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_SHIFT #undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_MASK -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_DEFVAL -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_SHIFT 25 -#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_MASK 0x02000000U +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_DEFVAL +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_MASK 0x02000000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT 0 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK 0x00000001U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK 0x00000001U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT 1 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK 0x00000002U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK 0x00000002U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT 2 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK 0x00000004U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK 0x00000004U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT 3 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK 0x00000008U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK 0x00000008U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT 4 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK 0x00000010U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK 0x00000010U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT 5 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK 0x00000020U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK 0x00000020U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT 6 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK 0x00000040U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK 0x00000040U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT 7 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK 0x00000080U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK 0x00000080U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT 8 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK 0x00000100U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK 0x00000100U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT 9 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK 0x00000200U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK 0x00000200U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT 10 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK 0x00000400U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK 0x00000400U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT 11 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK 0x00000800U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK 0x00000800U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT 12 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK 0x00001000U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK 0x00001000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT 13 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK 0x00002000U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK 0x00002000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT 14 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK 0x00004000U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK 0x00004000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT 15 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK 0x00008000U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK 0x00008000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT 16 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK 0x00010000U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK 0x00010000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT 17 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK 0x00020000U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK 0x00020000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT 18 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK 0x00040000U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK 0x00040000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT 19 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK 0x00080000U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK 0x00080000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT 20 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK 0x00100000U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK 0x00100000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT 21 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK 0x00200000U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK 0x00200000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT 22 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK 0x00400000U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK 0x00400000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT 23 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK 0x00800000U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK 0x00800000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT 24 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK 0x01000000U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK 0x01000000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT #undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT 25 -#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK 0x02000000U +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK 0x02000000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT 0 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK 0x00000001U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK 0x00000001U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT 1 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK 0x00000002U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK 0x00000002U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT 2 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK 0x00000004U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK 0x00000004U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT 3 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK 0x00000008U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK 0x00000008U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT 4 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK 0x00000010U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK 0x00000010U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT 5 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK 0x00000020U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK 0x00000020U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT 6 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK 0x00000040U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK 0x00000040U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT 7 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK 0x00000080U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK 0x00000080U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT 8 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK 0x00000100U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK 0x00000100U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT 9 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK 0x00000200U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK 0x00000200U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT 10 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK 0x00000400U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK 0x00000400U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT 11 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK 0x00000800U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK 0x00000800U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT 12 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK 0x00001000U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK 0x00001000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT 13 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK 0x00002000U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK 0x00002000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT 14 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK 0x00004000U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK 0x00004000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT 15 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK 0x00008000U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK 0x00008000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT 16 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK 0x00010000U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK 0x00010000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT 17 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK 0x00020000U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK 0x00020000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT 18 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK 0x00040000U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK 0x00040000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT 19 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK 0x00080000U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK 0x00080000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT 20 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK 0x00100000U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK 0x00100000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT 21 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK 0x00200000U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK 0x00200000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT 22 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK 0x00400000U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK 0x00400000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT 23 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK 0x00800000U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK 0x00800000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT 24 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK 0x01000000U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK 0x01000000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT #undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT 25 -#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK 0x02000000U +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK 0x02000000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_SHIFT 0 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_MASK 0x00000001U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_MASK 0x00000001U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_SHIFT 1 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_MASK 0x00000002U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_MASK 0x00000002U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_SHIFT 2 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_MASK 0x00000004U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_MASK 0x00000004U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_SHIFT 3 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_MASK 0x00000008U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_MASK 0x00000008U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_SHIFT 4 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_MASK 0x00000010U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_MASK 0x00000010U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_SHIFT 5 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_MASK 0x00000020U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_MASK 0x00000020U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_SHIFT 6 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_MASK 0x00000040U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_MASK 0x00000040U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_SHIFT 7 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_MASK 0x00000080U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_MASK 0x00000080U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_SHIFT 8 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_MASK 0x00000100U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_MASK 0x00000100U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_SHIFT 9 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_MASK 0x00000200U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_MASK 0x00000200U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_SHIFT 10 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_MASK 0x00000400U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_MASK 0x00000400U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_SHIFT 11 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_MASK 0x00000800U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_MASK 0x00000800U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_SHIFT 12 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_MASK 0x00001000U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_MASK 0x00001000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_SHIFT 13 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_MASK 0x00002000U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_MASK 0x00002000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_SHIFT 14 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_MASK 0x00004000U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_MASK 0x00004000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_SHIFT 15 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_MASK 0x00008000U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_MASK 0x00008000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_SHIFT 16 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_MASK 0x00010000U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_MASK 0x00010000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_SHIFT 17 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_MASK 0x00020000U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_MASK 0x00020000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_SHIFT 18 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_MASK 0x00040000U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_MASK 0x00040000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_SHIFT 19 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_MASK 0x00080000U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_MASK 0x00080000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_SHIFT 20 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_MASK 0x00100000U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_MASK 0x00100000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_SHIFT 21 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_MASK 0x00200000U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_MASK 0x00200000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_SHIFT 22 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_MASK 0x00400000U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_MASK 0x00400000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_SHIFT 23 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_MASK 0x00800000U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_MASK 0x00800000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_SHIFT 24 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_MASK 0x01000000U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_MASK 0x01000000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_DEFVAL #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_SHIFT #undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_MASK -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_DEFVAL -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_SHIFT 25 -#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_MASK 0x02000000U +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_DEFVAL +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_MASK 0x02000000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT 0 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK 0x00000001U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT 0 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK 0x00000001U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT 1 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK 0x00000002U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT 1 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK 0x00000002U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT 2 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK 0x00000004U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT 2 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK 0x00000004U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT 3 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK 0x00000008U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT 3 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK 0x00000008U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT 4 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK 0x00000010U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT 4 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK 0x00000010U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT 5 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK 0x00000020U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT 5 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK 0x00000020U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT 6 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK 0x00000040U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT 6 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK 0x00000040U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT 7 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK 0x00000080U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT 7 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK 0x00000080U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT 8 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK 0x00000100U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT 8 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK 0x00000100U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT 9 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK 0x00000200U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT 9 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK 0x00000200U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT 10 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK 0x00000400U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT 10 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK 0x00000400U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT 11 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK 0x00000800U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT 11 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK 0x00000800U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT 12 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK 0x00001000U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT 12 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK 0x00001000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT 13 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK 0x00002000U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT 13 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK 0x00002000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT 14 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK 0x00004000U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT 14 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK 0x00004000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT 15 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK 0x00008000U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT 15 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK 0x00008000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT 16 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK 0x00010000U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT 16 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK 0x00010000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT 17 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK 0x00020000U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT 17 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK 0x00020000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT 18 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK 0x00040000U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT 18 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK 0x00040000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT 19 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK 0x00080000U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT 19 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK 0x00080000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT 20 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK 0x00100000U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT 20 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK 0x00100000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT 21 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK 0x00200000U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT 21 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK 0x00200000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT 22 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK 0x00400000U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT 22 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK 0x00400000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT 23 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK 0x00800000U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT 23 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK 0x00800000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT 24 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK 0x01000000U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT 24 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK 0x01000000U -/*Each bit applies to a single IO. Bit 0 for MIO[52].*/ +/* +* Each bit applies to a single IO. Bit 0 for MIO[52]. +*/ #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT #undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT 25 -#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK 0x02000000U +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT 25 +#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK 0x02000000U -/*I2C Loopback Control. 0 = Connect I2C inputs according to MIO mapping. 1 = Loop I2C 0 outputs to I2C 1 inputs, and I2C 1 outp - ts to I2C 0 inputs.*/ +/* +* I2C Loopback Control. 0 = Connect I2C inputs according to MIO mapping. 1 + * = Loop I2C 0 outputs to I2C 1 inputs, and I2C 1 outputs to I2C 0 inputs + * . +*/ #undef IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_DEFVAL #undef IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_SHIFT #undef IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_MASK -#define IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_SHIFT 3 -#define IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_MASK 0x00000008U +#define IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_SHIFT 3 +#define IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_MASK 0x00000008U -/*CAN Loopback Control. 0 = Connect CAN inputs according to MIO mapping. 1 = Loop CAN 0 Tx to CAN 1 Rx, and CAN 1 Tx to CAN 0 R - .*/ +/* +* CAN Loopback Control. 0 = Connect CAN inputs according to MIO mapping. 1 + * = Loop CAN 0 Tx to CAN 1 Rx, and CAN 1 Tx to CAN 0 Rx. +*/ #undef IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_DEFVAL #undef IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_SHIFT #undef IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_MASK -#define IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_SHIFT 2 -#define IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_MASK 0x00000004U +#define IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_SHIFT 2 +#define IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_MASK 0x00000004U -/*UART Loopback Control. 0 = Connect UART inputs according to MIO mapping. 1 = Loop UART 0 outputs to UART 1 inputs, and UART 1 - outputs to UART 0 inputs. RXD/TXD cross-connected. RTS/CTS cross-connected. DSR, DTR, DCD and RI not used.*/ +/* +* UART Loopback Control. 0 = Connect UART inputs according to MIO mapping. + * 1 = Loop UART 0 outputs to UART 1 inputs, and UART 1 outputs to UART 0 + * inputs. RXD/TXD cross-connected. RTS/CTS cross-connected. DSR, DTR, DCD + * and RI not used. +*/ #undef IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_DEFVAL #undef IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_SHIFT #undef IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_MASK -#define IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_SHIFT 1 -#define IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_MASK 0x00000002U +#define IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_SHIFT 1 +#define IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_MASK 0x00000002U -/*SPI Loopback Control. 0 = Connect SPI inputs according to MIO mapping. 1 = Loop SPI 0 outputs to SPI 1 inputs, and SPI 1 outp - ts to SPI 0 inputs. The other SPI core will appear on the LS Slave Select.*/ +/* +* SPI Loopback Control. 0 = Connect SPI inputs according to MIO mapping. 1 + * = Loop SPI 0 outputs to SPI 1 inputs, and SPI 1 outputs to SPI 0 inputs + * . The other SPI core will appear on the LS Slave Select. +*/ #undef IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_DEFVAL #undef IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_SHIFT #undef IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_MASK -#define IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_DEFVAL 0x00000000 -#define IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_SHIFT 0 -#define IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_MASK 0x00000001U +#define IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_DEFVAL 0x00000000 +#define IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_SHIFT 0 +#define IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_MASK 0x00000001U +#undef CRF_APB_RST_FPD_TOP_OFFSET +#define CRF_APB_RST_FPD_TOP_OFFSET 0XFD1A0100 #undef CRL_APB_RST_LPD_IOU2_OFFSET #define CRL_APB_RST_LPD_IOU2_OFFSET 0XFF5E0238 +#undef CRL_APB_RST_LPD_TOP_OFFSET +#define CRL_APB_RST_LPD_TOP_OFFSET 0XFF5E023C #undef CRL_APB_RST_LPD_IOU0_OFFSET #define CRL_APB_RST_LPD_IOU0_OFFSET 0XFF5E0230 #undef CRL_APB_RST_LPD_IOU2_OFFSET @@ -24430,8 +31077,10 @@ #define IOU_SLCR_IOU_TAPDLY_BYPASS_OFFSET 0XFF180390 #undef CRL_APB_RST_LPD_TOP_OFFSET #define CRL_APB_RST_LPD_TOP_OFFSET 0XFF5E023C -#undef CRF_APB_RST_FPD_TOP_OFFSET -#define CRF_APB_RST_FPD_TOP_OFFSET 0XFD1A0100 +#undef USB3_0_FPD_POWER_PRSNT_OFFSET +#define USB3_0_FPD_POWER_PRSNT_OFFSET 0XFF9D0080 +#undef USB3_0_FPD_PIPE_CLK_OFFSET +#define USB3_0_FPD_PIPE_CLK_OFFSET 0XFF9D007C #undef CRL_APB_RST_LPD_IOU2_OFFSET #define CRL_APB_RST_LPD_IOU2_OFFSET 0XFF5E0238 #undef IOU_SLCR_CTRL_REG_SD_OFFSET @@ -24440,6 +31089,8 @@ #define IOU_SLCR_SD_CONFIG_REG2_OFFSET 0XFF180320 #undef IOU_SLCR_SD_CONFIG_REG1_OFFSET #define IOU_SLCR_SD_CONFIG_REG1_OFFSET 0XFF18031C +#undef IOU_SLCR_SD_DLL_CTRL_OFFSET +#define IOU_SLCR_SD_DLL_CTRL_OFFSET 0XFF180358 #undef IOU_SLCR_SD_CONFIG_REG3_OFFSET #define IOU_SLCR_SD_CONFIG_REG3_OFFSET 0XFF180324 #undef CRL_APB_RST_LPD_IOU2_OFFSET @@ -24468,6 +31119,8 @@ #define UART1_CONTROL_REG0_OFFSET 0XFF010000 #undef UART1_MODE_REG0_OFFSET #define UART1_MODE_REG0_OFFSET 0XFF010004 +#undef CRL_APB_RST_LPD_IOU2_OFFSET +#define CRL_APB_RST_LPD_IOU2_OFFSET 0XFF5E0238 #undef LPD_SLCR_SECURE_SLCR_ADMA_OFFSET #define LPD_SLCR_SECURE_SLCR_ADMA_OFFSET 0XFF4B0024 #undef CSU_TAMPER_STATUS_OFFSET @@ -24480,782 +31133,1656 @@ #define IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_OFFSET 0XFF260020 #undef IOU_SCNTRS_COUNTER_CONTROL_REGISTER_OFFSET #define IOU_SCNTRS_COUNTER_CONTROL_REGISTER_OFFSET 0XFF260000 +#undef GPIO_DIRM_1_OFFSET +#define GPIO_DIRM_1_OFFSET 0XFF0A0244 +#undef GPIO_OEN_1_OFFSET +#define GPIO_OEN_1_OFFSET 0XFF0A0248 +#undef GPIO_MASK_DATA_1_LSW_OFFSET +#define GPIO_MASK_DATA_1_LSW_OFFSET 0XFF0A0008 +#undef GPIO_MASK_DATA_1_LSW_OFFSET +#define GPIO_MASK_DATA_1_LSW_OFFSET 0XFF0A0008 -/*Block level reset*/ -#undef CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_DEFVAL -#undef CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_SHIFT -#undef CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_MASK -#define CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_DEFVAL 0x0017FFFF -#define CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_SHIFT 20 -#define CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_MASK 0x00100000U - -/*GEM 3 reset*/ -#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL -#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT -#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK -#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL 0x0000000F -#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT 3 -#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK 0x00000008U - -/*Block level reset*/ -#undef CRL_APB_RST_LPD_IOU2_QSPI_RESET_DEFVAL -#undef CRL_APB_RST_LPD_IOU2_QSPI_RESET_SHIFT -#undef CRL_APB_RST_LPD_IOU2_QSPI_RESET_MASK -#define CRL_APB_RST_LPD_IOU2_QSPI_RESET_DEFVAL 0x0017FFFF -#define CRL_APB_RST_LPD_IOU2_QSPI_RESET_SHIFT 0 -#define CRL_APB_RST_LPD_IOU2_QSPI_RESET_MASK 0x00000001U - -/*0: Do not by pass the tap delays on the Rx clock signal of LQSPI 1: Bypass the Tap delay on the Rx clock signal of LQSPI*/ -#undef IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_DEFVAL -#undef IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_SHIFT -#undef IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_MASK -#define IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_DEFVAL 0x00000007 -#define IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_SHIFT 2 -#define IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_MASK 0x00000004U - -/*USB 0 reset for control registers*/ -#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL -#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT -#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK -#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL 0x00188FDF -#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT 10 -#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK 0x00000400U - -/*USB 0 sleep circuit reset*/ -#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL -#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT -#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK -#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL 0x00188FDF -#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT 8 -#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK 0x00000100U - -/*USB 0 reset*/ -#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL -#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT -#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK -#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL 0x00188FDF -#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT 6 -#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK 0x00000040U - -/*PCIE config reset*/ +/* +* PCIE config reset +*/ #undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL #undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT #undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK -#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL 0x000F9FFE -#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT 19 -#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK 0x00080000U +#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT 19 +#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK 0x00080000U -/*PCIE control block level reset*/ +/* +* PCIE control block level reset +*/ #undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL #undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT #undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK -#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL 0x000F9FFE -#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT 17 -#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK 0x00020000U +#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT 17 +#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK 0x00020000U -/*PCIE bridge block level reset (AXI interface)*/ +/* +* PCIE bridge block level reset (AXI interface) +*/ #undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL #undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT #undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK -#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL 0x000F9FFE -#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT 18 -#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK 0x00040000U +#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT 18 +#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK 0x00040000U -/*Display Port block level reset (includes DPDMA)*/ +/* +* Display Port block level reset (includes DPDMA) +*/ #undef CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL #undef CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT #undef CRF_APB_RST_FPD_TOP_DP_RESET_MASK -#define CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL 0x000F9FFE -#define CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT 16 -#define CRF_APB_RST_FPD_TOP_DP_RESET_MASK 0x00010000U +#define CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT 16 +#define CRF_APB_RST_FPD_TOP_DP_RESET_MASK 0x00010000U -/*FPD WDT reset*/ +/* +* FPD WDT reset +*/ #undef CRF_APB_RST_FPD_TOP_SWDT_RESET_DEFVAL #undef CRF_APB_RST_FPD_TOP_SWDT_RESET_SHIFT #undef CRF_APB_RST_FPD_TOP_SWDT_RESET_MASK -#define CRF_APB_RST_FPD_TOP_SWDT_RESET_DEFVAL 0x000F9FFE -#define CRF_APB_RST_FPD_TOP_SWDT_RESET_SHIFT 15 -#define CRF_APB_RST_FPD_TOP_SWDT_RESET_MASK 0x00008000U +#define CRF_APB_RST_FPD_TOP_SWDT_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_SWDT_RESET_SHIFT 15 +#define CRF_APB_RST_FPD_TOP_SWDT_RESET_MASK 0x00008000U -/*GDMA block level reset*/ +/* +* GDMA block level reset +*/ #undef CRF_APB_RST_FPD_TOP_GDMA_RESET_DEFVAL #undef CRF_APB_RST_FPD_TOP_GDMA_RESET_SHIFT #undef CRF_APB_RST_FPD_TOP_GDMA_RESET_MASK -#define CRF_APB_RST_FPD_TOP_GDMA_RESET_DEFVAL 0x000F9FFE -#define CRF_APB_RST_FPD_TOP_GDMA_RESET_SHIFT 6 -#define CRF_APB_RST_FPD_TOP_GDMA_RESET_MASK 0x00000040U +#define CRF_APB_RST_FPD_TOP_GDMA_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_GDMA_RESET_SHIFT 6 +#define CRF_APB_RST_FPD_TOP_GDMA_RESET_MASK 0x00000040U -/*Pixel Processor (submodule of GPU) block level reset*/ +/* +* Pixel Processor (submodule of GPU) block level reset +*/ #undef CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_DEFVAL #undef CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_SHIFT #undef CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_MASK -#define CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_DEFVAL 0x000F9FFE -#define CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_SHIFT 4 -#define CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_MASK 0x00000010U +#define CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_SHIFT 4 +#define CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_MASK 0x00000010U -/*Pixel Processor (submodule of GPU) block level reset*/ +/* +* Pixel Processor (submodule of GPU) block level reset +*/ #undef CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_DEFVAL #undef CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_SHIFT #undef CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_MASK -#define CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_DEFVAL 0x000F9FFE -#define CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_SHIFT 5 -#define CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_MASK 0x00000020U +#define CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_SHIFT 5 +#define CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_MASK 0x00000020U -/*GPU block level reset*/ +/* +* GPU block level reset +*/ #undef CRF_APB_RST_FPD_TOP_GPU_RESET_DEFVAL #undef CRF_APB_RST_FPD_TOP_GPU_RESET_SHIFT #undef CRF_APB_RST_FPD_TOP_GPU_RESET_MASK -#define CRF_APB_RST_FPD_TOP_GPU_RESET_DEFVAL 0x000F9FFE -#define CRF_APB_RST_FPD_TOP_GPU_RESET_SHIFT 3 -#define CRF_APB_RST_FPD_TOP_GPU_RESET_MASK 0x00000008U +#define CRF_APB_RST_FPD_TOP_GPU_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_GPU_RESET_SHIFT 3 +#define CRF_APB_RST_FPD_TOP_GPU_RESET_MASK 0x00000008U -/*GT block level reset*/ +/* +* GT block level reset +*/ #undef CRF_APB_RST_FPD_TOP_GT_RESET_DEFVAL #undef CRF_APB_RST_FPD_TOP_GT_RESET_SHIFT #undef CRF_APB_RST_FPD_TOP_GT_RESET_MASK -#define CRF_APB_RST_FPD_TOP_GT_RESET_DEFVAL 0x000F9FFE -#define CRF_APB_RST_FPD_TOP_GT_RESET_SHIFT 2 -#define CRF_APB_RST_FPD_TOP_GT_RESET_MASK 0x00000004U +#define CRF_APB_RST_FPD_TOP_GT_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_GT_RESET_SHIFT 2 +#define CRF_APB_RST_FPD_TOP_GT_RESET_MASK 0x00000004U -/*Sata block level reset*/ +/* +* Sata block level reset +*/ #undef CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL #undef CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT #undef CRF_APB_RST_FPD_TOP_SATA_RESET_MASK -#define CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL 0x000F9FFE -#define CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT 1 -#define CRF_APB_RST_FPD_TOP_SATA_RESET_MASK 0x00000002U +#define CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT 1 +#define CRF_APB_RST_FPD_TOP_SATA_RESET_MASK 0x00000002U -/*Block level reset*/ +/* +* Block level reset +*/ +#undef CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_DEFVAL +#undef CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_SHIFT +#undef CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_MASK +#define CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_SHIFT 20 +#define CRL_APB_RST_LPD_IOU2_TIMESTAMP_RESET_MASK 0x00100000U + +/* +* Block level reset +*/ +#undef CRL_APB_RST_LPD_IOU2_IOU_CC_RESET_DEFVAL +#undef CRL_APB_RST_LPD_IOU2_IOU_CC_RESET_SHIFT +#undef CRL_APB_RST_LPD_IOU2_IOU_CC_RESET_MASK +#define CRL_APB_RST_LPD_IOU2_IOU_CC_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_IOU_CC_RESET_SHIFT 19 +#define CRL_APB_RST_LPD_IOU2_IOU_CC_RESET_MASK 0x00080000U + +/* +* Block level reset +*/ +#undef CRL_APB_RST_LPD_IOU2_ADMA_RESET_DEFVAL +#undef CRL_APB_RST_LPD_IOU2_ADMA_RESET_SHIFT +#undef CRL_APB_RST_LPD_IOU2_ADMA_RESET_MASK +#define CRL_APB_RST_LPD_IOU2_ADMA_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_ADMA_RESET_SHIFT 17 +#define CRL_APB_RST_LPD_IOU2_ADMA_RESET_MASK 0x00020000U + +/* +* Reset entire full power domain. +*/ +#undef CRL_APB_RST_LPD_TOP_FPD_RESET_DEFVAL +#undef CRL_APB_RST_LPD_TOP_FPD_RESET_SHIFT +#undef CRL_APB_RST_LPD_TOP_FPD_RESET_MASK +#define CRL_APB_RST_LPD_TOP_FPD_RESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_FPD_RESET_SHIFT 23 +#define CRL_APB_RST_LPD_TOP_FPD_RESET_MASK 0x00800000U + +/* +* LPD SWDT +*/ +#undef CRL_APB_RST_LPD_TOP_LPD_SWDT_RESET_DEFVAL +#undef CRL_APB_RST_LPD_TOP_LPD_SWDT_RESET_SHIFT +#undef CRL_APB_RST_LPD_TOP_LPD_SWDT_RESET_MASK +#define CRL_APB_RST_LPD_TOP_LPD_SWDT_RESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_LPD_SWDT_RESET_SHIFT 20 +#define CRL_APB_RST_LPD_TOP_LPD_SWDT_RESET_MASK 0x00100000U + +/* +* Sysmonitor reset +*/ +#undef CRL_APB_RST_LPD_TOP_SYSMON_RESET_DEFVAL +#undef CRL_APB_RST_LPD_TOP_SYSMON_RESET_SHIFT +#undef CRL_APB_RST_LPD_TOP_SYSMON_RESET_MASK +#define CRL_APB_RST_LPD_TOP_SYSMON_RESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_SYSMON_RESET_SHIFT 17 +#define CRL_APB_RST_LPD_TOP_SYSMON_RESET_MASK 0x00020000U + +/* +* Real Time Clock reset +*/ +#undef CRL_APB_RST_LPD_TOP_RTC_RESET_DEFVAL +#undef CRL_APB_RST_LPD_TOP_RTC_RESET_SHIFT +#undef CRL_APB_RST_LPD_TOP_RTC_RESET_MASK +#define CRL_APB_RST_LPD_TOP_RTC_RESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_RTC_RESET_SHIFT 16 +#define CRL_APB_RST_LPD_TOP_RTC_RESET_MASK 0x00010000U + +/* +* APM reset +*/ +#undef CRL_APB_RST_LPD_TOP_APM_RESET_DEFVAL +#undef CRL_APB_RST_LPD_TOP_APM_RESET_SHIFT +#undef CRL_APB_RST_LPD_TOP_APM_RESET_MASK +#define CRL_APB_RST_LPD_TOP_APM_RESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_APM_RESET_SHIFT 15 +#define CRL_APB_RST_LPD_TOP_APM_RESET_MASK 0x00008000U + +/* +* IPI reset +*/ +#undef CRL_APB_RST_LPD_TOP_IPI_RESET_DEFVAL +#undef CRL_APB_RST_LPD_TOP_IPI_RESET_SHIFT +#undef CRL_APB_RST_LPD_TOP_IPI_RESET_MASK +#define CRL_APB_RST_LPD_TOP_IPI_RESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_IPI_RESET_SHIFT 14 +#define CRL_APB_RST_LPD_TOP_IPI_RESET_MASK 0x00004000U + +/* +* reset entire RPU power island +*/ +#undef CRL_APB_RST_LPD_TOP_RPU_PGE_RESET_DEFVAL +#undef CRL_APB_RST_LPD_TOP_RPU_PGE_RESET_SHIFT +#undef CRL_APB_RST_LPD_TOP_RPU_PGE_RESET_MASK +#define CRL_APB_RST_LPD_TOP_RPU_PGE_RESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_RPU_PGE_RESET_SHIFT 4 +#define CRL_APB_RST_LPD_TOP_RPU_PGE_RESET_MASK 0x00000010U + +/* +* reset ocm +*/ +#undef CRL_APB_RST_LPD_TOP_OCM_RESET_DEFVAL +#undef CRL_APB_RST_LPD_TOP_OCM_RESET_SHIFT +#undef CRL_APB_RST_LPD_TOP_OCM_RESET_MASK +#define CRL_APB_RST_LPD_TOP_OCM_RESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_OCM_RESET_SHIFT 3 +#define CRL_APB_RST_LPD_TOP_OCM_RESET_MASK 0x00000008U + +/* +* GEM 3 reset +*/ +#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL +#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT +#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK +#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL 0x0000000F +#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT 3 +#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK 0x00000008U + +/* +* Block level reset +*/ +#undef CRL_APB_RST_LPD_IOU2_QSPI_RESET_DEFVAL +#undef CRL_APB_RST_LPD_IOU2_QSPI_RESET_SHIFT +#undef CRL_APB_RST_LPD_IOU2_QSPI_RESET_MASK +#define CRL_APB_RST_LPD_IOU2_QSPI_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_QSPI_RESET_SHIFT 0 +#define CRL_APB_RST_LPD_IOU2_QSPI_RESET_MASK 0x00000001U + +/* +* 0: Do not by pass the tap delays on the Rx clock signal of LQSPI 1: Bypa + * ss the Tap delay on the Rx clock signal of LQSPI +*/ +#undef IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_DEFVAL +#undef IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_SHIFT +#undef IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_MASK +#define IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_DEFVAL 0x00000007 +#define IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_SHIFT 2 +#define IOU_SLCR_IOU_TAPDLY_BYPASS_LQSPI_RX_MASK 0x00000004U + +/* +* USB 0 reset for control registers +*/ +#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL +#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT +#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK +#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT 10 +#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK 0x00000400U + +/* +* USB 0 sleep circuit reset +*/ +#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL +#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT +#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK +#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT 8 +#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK 0x00000100U + +/* +* USB 0 reset +*/ +#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL +#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT +#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK +#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT 6 +#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK 0x00000040U + +/* +* This bit is used to choose between PIPE power present and 1'b1 +*/ +#undef USB3_0_FPD_POWER_PRSNT_OPTION_DEFVAL +#undef USB3_0_FPD_POWER_PRSNT_OPTION_SHIFT +#undef USB3_0_FPD_POWER_PRSNT_OPTION_MASK +#define USB3_0_FPD_POWER_PRSNT_OPTION_DEFVAL +#define USB3_0_FPD_POWER_PRSNT_OPTION_SHIFT 0 +#define USB3_0_FPD_POWER_PRSNT_OPTION_MASK 0x00000001U + +/* +* This bit is used to choose between PIPE clock coming from SerDes and the + * suspend clk +*/ +#undef USB3_0_FPD_PIPE_CLK_OPTION_DEFVAL +#undef USB3_0_FPD_PIPE_CLK_OPTION_SHIFT +#undef USB3_0_FPD_PIPE_CLK_OPTION_MASK +#define USB3_0_FPD_PIPE_CLK_OPTION_DEFVAL +#define USB3_0_FPD_PIPE_CLK_OPTION_SHIFT 0 +#define USB3_0_FPD_PIPE_CLK_OPTION_MASK 0x00000001U + +/* +* Block level reset +*/ #undef CRL_APB_RST_LPD_IOU2_SDIO1_RESET_DEFVAL #undef CRL_APB_RST_LPD_IOU2_SDIO1_RESET_SHIFT #undef CRL_APB_RST_LPD_IOU2_SDIO1_RESET_MASK -#define CRL_APB_RST_LPD_IOU2_SDIO1_RESET_DEFVAL 0x0017FFFF -#define CRL_APB_RST_LPD_IOU2_SDIO1_RESET_SHIFT 6 -#define CRL_APB_RST_LPD_IOU2_SDIO1_RESET_MASK 0x00000040U +#define CRL_APB_RST_LPD_IOU2_SDIO1_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_SDIO1_RESET_SHIFT 6 +#define CRL_APB_RST_LPD_IOU2_SDIO1_RESET_MASK 0x00000040U -/*SD or eMMC selection on SDIO1 0: SD enabled 1: eMMC enabled*/ +/* +* SD or eMMC selection on SDIO1 0: SD enabled 1: eMMC enabled +*/ #undef IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_DEFVAL #undef IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_SHIFT #undef IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_MASK -#define IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_DEFVAL 0x00000000 -#define IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_SHIFT 15 -#define IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_MASK 0x00008000U +#define IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_DEFVAL 0x00000000 +#define IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_SHIFT 15 +#define IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_MASK 0x00008000U -/*Should be set based on the final product usage 00 - Removable SCard Slot 01 - Embedded Slot for One Device 10 - Shared Bus Sl - t 11 - Reserved*/ +/* +* Should be set based on the final product usage 00 - Removable SCard Slot + * 01 - Embedded Slot for One Device 10 - Shared Bus Slot 11 - Reserved +*/ #undef IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_DEFVAL #undef IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_SHIFT #undef IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_MASK -#define IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_DEFVAL 0x0FFC0FFC -#define IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_SHIFT 28 -#define IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_MASK 0x30000000U +#define IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_DEFVAL 0x0FFC0FFC +#define IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_SHIFT 28 +#define IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_MASK 0x30000000U -/*1.8V Support 1: 1.8V supported 0: 1.8V not supported support*/ +/* +* 1.8V Support 1: 1.8V supported 0: 1.8V not supported support +*/ #undef IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_DEFVAL #undef IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_SHIFT #undef IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_MASK -#define IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_DEFVAL 0x0FFC0FFC -#define IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_SHIFT 25 -#define IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_MASK 0x02000000U +#define IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_DEFVAL 0x0FFC0FFC +#define IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_SHIFT 25 +#define IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_MASK 0x02000000U -/*3.0V Support 1: 3.0V supported 0: 3.0V not supported support*/ +/* +* 3.0V Support 1: 3.0V supported 0: 3.0V not supported support +*/ #undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_DEFVAL #undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_SHIFT #undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_MASK -#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_DEFVAL 0x0FFC0FFC -#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_SHIFT 24 -#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_MASK 0x01000000U +#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_DEFVAL 0x0FFC0FFC +#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_SHIFT 24 +#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_MASK 0x01000000U -/*3.3V Support 1: 3.3V supported 0: 3.3V not supported support*/ +/* +* 3.3V Support 1: 3.3V supported 0: 3.3V not supported support +*/ #undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_DEFVAL #undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_SHIFT #undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_MASK -#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_DEFVAL 0x0FFC0FFC -#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_SHIFT 23 -#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_MASK 0x00800000U +#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_DEFVAL 0x0FFC0FFC +#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_SHIFT 23 +#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_MASK 0x00800000U -/*Base Clock Frequency for SD Clock. This is the frequency of the xin_clk.*/ +/* +* Base Clock Frequency for SD Clock. This is the frequency of the xin_clk. +*/ #undef IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_DEFVAL #undef IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_SHIFT #undef IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_MASK -#define IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_DEFVAL 0x32403240 -#define IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_SHIFT 23 -#define IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_MASK 0x7F800000U +#define IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_DEFVAL 0x32403240 +#define IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_SHIFT 23 +#define IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_MASK 0x7F800000U -/*This is the Timer Count for Re-Tuning Timer for Re-Tuning Mode 1 to 3. Setting to 4'b0 disables Re-Tuning Timer. 0h - Get inf - rmation via other source 1h = 1 seconds 2h = 2 seconds 3h = 4 seconds 4h = 8 seconds -- n = 2(n-1) seconds -- Bh = 1024 secon - s Fh - Ch = Reserved*/ +/* +* Configures the Number of Taps (Phases) of the rxclk_in that is supported + * . +*/ +#undef IOU_SLCR_SD_CONFIG_REG1_SD1_TUNIGCOUNT_DEFVAL +#undef IOU_SLCR_SD_CONFIG_REG1_SD1_TUNIGCOUNT_SHIFT +#undef IOU_SLCR_SD_CONFIG_REG1_SD1_TUNIGCOUNT_MASK +#define IOU_SLCR_SD_CONFIG_REG1_SD1_TUNIGCOUNT_DEFVAL 0x32403240 +#define IOU_SLCR_SD_CONFIG_REG1_SD1_TUNIGCOUNT_SHIFT 17 +#define IOU_SLCR_SD_CONFIG_REG1_SD1_TUNIGCOUNT_MASK 0x007E0000U + +/* +* Reserved. +*/ +#undef IOU_SLCR_SD_DLL_CTRL_RESERVED_DEFVAL +#undef IOU_SLCR_SD_DLL_CTRL_RESERVED_SHIFT +#undef IOU_SLCR_SD_DLL_CTRL_RESERVED_MASK +#define IOU_SLCR_SD_DLL_CTRL_RESERVED_DEFVAL 0x00080008 +#define IOU_SLCR_SD_DLL_CTRL_RESERVED_SHIFT 3 +#define IOU_SLCR_SD_DLL_CTRL_RESERVED_MASK 0x00000008U + +/* +* This is the Timer Count for Re-Tuning Timer for Re-Tuning Mode 1 to 3. S + * etting to 4'b0 disables Re-Tuning Timer. 0h - Get information via other + * source 1h = 1 seconds 2h = 2 seconds 3h = 4 seconds 4h = 8 seconds -- n + * = 2(n-1) seconds -- Bh = 1024 seconds Fh - Ch = Reserved +*/ #undef IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_DEFVAL #undef IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_SHIFT #undef IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_MASK -#define IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_DEFVAL 0x06070607 -#define IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_SHIFT 22 -#define IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_MASK 0x03C00000U +#define IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_DEFVAL 0x06070607 +#define IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_SHIFT 22 +#define IOU_SLCR_SD_CONFIG_REG3_SD1_RETUNETMR_MASK 0x03C00000U -/*Block level reset*/ +/* +* Block level reset +*/ #undef CRL_APB_RST_LPD_IOU2_CAN1_RESET_DEFVAL #undef CRL_APB_RST_LPD_IOU2_CAN1_RESET_SHIFT #undef CRL_APB_RST_LPD_IOU2_CAN1_RESET_MASK -#define CRL_APB_RST_LPD_IOU2_CAN1_RESET_DEFVAL 0x0017FFFF -#define CRL_APB_RST_LPD_IOU2_CAN1_RESET_SHIFT 8 -#define CRL_APB_RST_LPD_IOU2_CAN1_RESET_MASK 0x00000100U +#define CRL_APB_RST_LPD_IOU2_CAN1_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_CAN1_RESET_SHIFT 8 +#define CRL_APB_RST_LPD_IOU2_CAN1_RESET_MASK 0x00000100U -/*Block level reset*/ +/* +* Block level reset +*/ #undef CRL_APB_RST_LPD_IOU2_I2C0_RESET_DEFVAL #undef CRL_APB_RST_LPD_IOU2_I2C0_RESET_SHIFT #undef CRL_APB_RST_LPD_IOU2_I2C0_RESET_MASK -#define CRL_APB_RST_LPD_IOU2_I2C0_RESET_DEFVAL 0x0017FFFF -#define CRL_APB_RST_LPD_IOU2_I2C0_RESET_SHIFT 9 -#define CRL_APB_RST_LPD_IOU2_I2C0_RESET_MASK 0x00000200U +#define CRL_APB_RST_LPD_IOU2_I2C0_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_I2C0_RESET_SHIFT 9 +#define CRL_APB_RST_LPD_IOU2_I2C0_RESET_MASK 0x00000200U -/*Block level reset*/ +/* +* Block level reset +*/ #undef CRL_APB_RST_LPD_IOU2_I2C1_RESET_DEFVAL #undef CRL_APB_RST_LPD_IOU2_I2C1_RESET_SHIFT #undef CRL_APB_RST_LPD_IOU2_I2C1_RESET_MASK -#define CRL_APB_RST_LPD_IOU2_I2C1_RESET_DEFVAL 0x0017FFFF -#define CRL_APB_RST_LPD_IOU2_I2C1_RESET_SHIFT 10 -#define CRL_APB_RST_LPD_IOU2_I2C1_RESET_MASK 0x00000400U +#define CRL_APB_RST_LPD_IOU2_I2C1_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_I2C1_RESET_SHIFT 10 +#define CRL_APB_RST_LPD_IOU2_I2C1_RESET_MASK 0x00000400U -/*Block level reset*/ +/* +* Block level reset +*/ #undef CRL_APB_RST_LPD_IOU2_SWDT_RESET_DEFVAL #undef CRL_APB_RST_LPD_IOU2_SWDT_RESET_SHIFT #undef CRL_APB_RST_LPD_IOU2_SWDT_RESET_MASK -#define CRL_APB_RST_LPD_IOU2_SWDT_RESET_DEFVAL 0x0017FFFF -#define CRL_APB_RST_LPD_IOU2_SWDT_RESET_SHIFT 15 -#define CRL_APB_RST_LPD_IOU2_SWDT_RESET_MASK 0x00008000U +#define CRL_APB_RST_LPD_IOU2_SWDT_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_SWDT_RESET_SHIFT 15 +#define CRL_APB_RST_LPD_IOU2_SWDT_RESET_MASK 0x00008000U -/*Block level reset*/ +/* +* Block level reset +*/ #undef CRL_APB_RST_LPD_IOU2_TTC0_RESET_DEFVAL #undef CRL_APB_RST_LPD_IOU2_TTC0_RESET_SHIFT #undef CRL_APB_RST_LPD_IOU2_TTC0_RESET_MASK -#define CRL_APB_RST_LPD_IOU2_TTC0_RESET_DEFVAL 0x0017FFFF -#define CRL_APB_RST_LPD_IOU2_TTC0_RESET_SHIFT 11 -#define CRL_APB_RST_LPD_IOU2_TTC0_RESET_MASK 0x00000800U +#define CRL_APB_RST_LPD_IOU2_TTC0_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_TTC0_RESET_SHIFT 11 +#define CRL_APB_RST_LPD_IOU2_TTC0_RESET_MASK 0x00000800U -/*Block level reset*/ +/* +* Block level reset +*/ #undef CRL_APB_RST_LPD_IOU2_TTC1_RESET_DEFVAL #undef CRL_APB_RST_LPD_IOU2_TTC1_RESET_SHIFT #undef CRL_APB_RST_LPD_IOU2_TTC1_RESET_MASK -#define CRL_APB_RST_LPD_IOU2_TTC1_RESET_DEFVAL 0x0017FFFF -#define CRL_APB_RST_LPD_IOU2_TTC1_RESET_SHIFT 12 -#define CRL_APB_RST_LPD_IOU2_TTC1_RESET_MASK 0x00001000U +#define CRL_APB_RST_LPD_IOU2_TTC1_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_TTC1_RESET_SHIFT 12 +#define CRL_APB_RST_LPD_IOU2_TTC1_RESET_MASK 0x00001000U -/*Block level reset*/ +/* +* Block level reset +*/ #undef CRL_APB_RST_LPD_IOU2_TTC2_RESET_DEFVAL #undef CRL_APB_RST_LPD_IOU2_TTC2_RESET_SHIFT #undef CRL_APB_RST_LPD_IOU2_TTC2_RESET_MASK -#define CRL_APB_RST_LPD_IOU2_TTC2_RESET_DEFVAL 0x0017FFFF -#define CRL_APB_RST_LPD_IOU2_TTC2_RESET_SHIFT 13 -#define CRL_APB_RST_LPD_IOU2_TTC2_RESET_MASK 0x00002000U +#define CRL_APB_RST_LPD_IOU2_TTC2_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_TTC2_RESET_SHIFT 13 +#define CRL_APB_RST_LPD_IOU2_TTC2_RESET_MASK 0x00002000U -/*Block level reset*/ +/* +* Block level reset +*/ #undef CRL_APB_RST_LPD_IOU2_TTC3_RESET_DEFVAL #undef CRL_APB_RST_LPD_IOU2_TTC3_RESET_SHIFT #undef CRL_APB_RST_LPD_IOU2_TTC3_RESET_MASK -#define CRL_APB_RST_LPD_IOU2_TTC3_RESET_DEFVAL 0x0017FFFF -#define CRL_APB_RST_LPD_IOU2_TTC3_RESET_SHIFT 14 -#define CRL_APB_RST_LPD_IOU2_TTC3_RESET_MASK 0x00004000U +#define CRL_APB_RST_LPD_IOU2_TTC3_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_TTC3_RESET_SHIFT 14 +#define CRL_APB_RST_LPD_IOU2_TTC3_RESET_MASK 0x00004000U -/*Block level reset*/ +/* +* Block level reset +*/ #undef CRL_APB_RST_LPD_IOU2_UART0_RESET_DEFVAL #undef CRL_APB_RST_LPD_IOU2_UART0_RESET_SHIFT #undef CRL_APB_RST_LPD_IOU2_UART0_RESET_MASK -#define CRL_APB_RST_LPD_IOU2_UART0_RESET_DEFVAL 0x0017FFFF -#define CRL_APB_RST_LPD_IOU2_UART0_RESET_SHIFT 1 -#define CRL_APB_RST_LPD_IOU2_UART0_RESET_MASK 0x00000002U +#define CRL_APB_RST_LPD_IOU2_UART0_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_UART0_RESET_SHIFT 1 +#define CRL_APB_RST_LPD_IOU2_UART0_RESET_MASK 0x00000002U -/*Block level reset*/ +/* +* Block level reset +*/ #undef CRL_APB_RST_LPD_IOU2_UART1_RESET_DEFVAL #undef CRL_APB_RST_LPD_IOU2_UART1_RESET_SHIFT #undef CRL_APB_RST_LPD_IOU2_UART1_RESET_MASK -#define CRL_APB_RST_LPD_IOU2_UART1_RESET_DEFVAL 0x0017FFFF -#define CRL_APB_RST_LPD_IOU2_UART1_RESET_SHIFT 2 -#define CRL_APB_RST_LPD_IOU2_UART1_RESET_MASK 0x00000004U +#define CRL_APB_RST_LPD_IOU2_UART1_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_UART1_RESET_SHIFT 2 +#define CRL_APB_RST_LPD_IOU2_UART1_RESET_MASK 0x00000004U -/*Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate*/ +/* +* Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate +*/ #undef UART0_BAUD_RATE_DIVIDER_REG0_BDIV_DEFVAL #undef UART0_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT #undef UART0_BAUD_RATE_DIVIDER_REG0_BDIV_MASK -#define UART0_BAUD_RATE_DIVIDER_REG0_BDIV_DEFVAL 0x0000000F -#define UART0_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT 0 -#define UART0_BAUD_RATE_DIVIDER_REG0_BDIV_MASK 0x000000FFU +#define UART0_BAUD_RATE_DIVIDER_REG0_BDIV_DEFVAL 0x0000000F +#define UART0_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT 0 +#define UART0_BAUD_RATE_DIVIDER_REG0_BDIV_MASK 0x000000FFU -/*Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample*/ +/* +* Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor + * bypass (baud_sample = sel_clk) 2 - 65535: baud_sample +*/ #undef UART0_BAUD_RATE_GEN_REG0_CD_DEFVAL #undef UART0_BAUD_RATE_GEN_REG0_CD_SHIFT #undef UART0_BAUD_RATE_GEN_REG0_CD_MASK -#define UART0_BAUD_RATE_GEN_REG0_CD_DEFVAL 0x0000028B -#define UART0_BAUD_RATE_GEN_REG0_CD_SHIFT 0 -#define UART0_BAUD_RATE_GEN_REG0_CD_MASK 0x0000FFFFU +#define UART0_BAUD_RATE_GEN_REG0_CD_DEFVAL 0x0000028B +#define UART0_BAUD_RATE_GEN_REG0_CD_SHIFT 0 +#define UART0_BAUD_RATE_GEN_REG0_CD_MASK 0x0000FFFFU -/*Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a - high level during 12 bit periods. It can be set regardless of the value of STTBRK.*/ +/* +* Stop transmitter break: 0: no affect 1: stop transmission of the break a + * fter a minimum of one character length and transmit a high level during + * 12 bit periods. It can be set regardless of the value of STTBRK. +*/ #undef UART0_CONTROL_REG0_STPBRK_DEFVAL #undef UART0_CONTROL_REG0_STPBRK_SHIFT #undef UART0_CONTROL_REG0_STPBRK_MASK -#define UART0_CONTROL_REG0_STPBRK_DEFVAL 0x00000128 -#define UART0_CONTROL_REG0_STPBRK_SHIFT 8 -#define UART0_CONTROL_REG0_STPBRK_MASK 0x00000100U +#define UART0_CONTROL_REG0_STPBRK_DEFVAL 0x00000128 +#define UART0_CONTROL_REG0_STPBRK_SHIFT 8 +#define UART0_CONTROL_REG0_STPBRK_MASK 0x00000100U -/*Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the - transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high.*/ +/* +* Start transmitter break: 0: no affect 1: start to transmit a break after + * the characters currently present in the FIFO and the transmit shift reg + * ister have been transmitted. It can only be set if STPBRK (Stop transmit + * ter break) is not high. +*/ #undef UART0_CONTROL_REG0_STTBRK_DEFVAL #undef UART0_CONTROL_REG0_STTBRK_SHIFT #undef UART0_CONTROL_REG0_STTBRK_MASK -#define UART0_CONTROL_REG0_STTBRK_DEFVAL 0x00000128 -#define UART0_CONTROL_REG0_STTBRK_SHIFT 7 -#define UART0_CONTROL_REG0_STTBRK_MASK 0x00000080U +#define UART0_CONTROL_REG0_STTBRK_DEFVAL 0x00000128 +#define UART0_CONTROL_REG0_STTBRK_SHIFT 7 +#define UART0_CONTROL_REG0_STTBRK_MASK 0x00000080U -/*Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has co - pleted.*/ +/* +* Restart receiver timeout counter: 1: receiver timeout counter is restart + * ed. This bit is self clearing once the restart has completed. +*/ #undef UART0_CONTROL_REG0_RSTTO_DEFVAL #undef UART0_CONTROL_REG0_RSTTO_SHIFT #undef UART0_CONTROL_REG0_RSTTO_MASK -#define UART0_CONTROL_REG0_RSTTO_DEFVAL 0x00000128 -#define UART0_CONTROL_REG0_RSTTO_SHIFT 6 -#define UART0_CONTROL_REG0_RSTTO_MASK 0x00000040U +#define UART0_CONTROL_REG0_RSTTO_DEFVAL 0x00000128 +#define UART0_CONTROL_REG0_RSTTO_SHIFT 6 +#define UART0_CONTROL_REG0_RSTTO_MASK 0x00000040U -/*Transmit disable: 0: enable transmitter 1: disable transmitter*/ +/* +* Transmit disable: 0: enable transmitter 1: disable transmitter +*/ #undef UART0_CONTROL_REG0_TXDIS_DEFVAL #undef UART0_CONTROL_REG0_TXDIS_SHIFT #undef UART0_CONTROL_REG0_TXDIS_MASK -#define UART0_CONTROL_REG0_TXDIS_DEFVAL 0x00000128 -#define UART0_CONTROL_REG0_TXDIS_SHIFT 5 -#define UART0_CONTROL_REG0_TXDIS_MASK 0x00000020U +#define UART0_CONTROL_REG0_TXDIS_DEFVAL 0x00000128 +#define UART0_CONTROL_REG0_TXDIS_SHIFT 5 +#define UART0_CONTROL_REG0_TXDIS_MASK 0x00000020U -/*Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0.*/ +/* +* Transmit enable: 0: disable transmitter 1: enable transmitter, provided + * the TXDIS field is set to 0. +*/ #undef UART0_CONTROL_REG0_TXEN_DEFVAL #undef UART0_CONTROL_REG0_TXEN_SHIFT #undef UART0_CONTROL_REG0_TXEN_MASK -#define UART0_CONTROL_REG0_TXEN_DEFVAL 0x00000128 -#define UART0_CONTROL_REG0_TXEN_SHIFT 4 -#define UART0_CONTROL_REG0_TXEN_MASK 0x00000010U +#define UART0_CONTROL_REG0_TXEN_DEFVAL 0x00000128 +#define UART0_CONTROL_REG0_TXEN_SHIFT 4 +#define UART0_CONTROL_REG0_TXEN_MASK 0x00000010U -/*Receive disable: 0: enable 1: disable, regardless of the value of RXEN*/ +/* +* Receive disable: 0: enable 1: disable, regardless of the value of RXEN +*/ #undef UART0_CONTROL_REG0_RXDIS_DEFVAL #undef UART0_CONTROL_REG0_RXDIS_SHIFT #undef UART0_CONTROL_REG0_RXDIS_MASK -#define UART0_CONTROL_REG0_RXDIS_DEFVAL 0x00000128 -#define UART0_CONTROL_REG0_RXDIS_SHIFT 3 -#define UART0_CONTROL_REG0_RXDIS_MASK 0x00000008U +#define UART0_CONTROL_REG0_RXDIS_DEFVAL 0x00000128 +#define UART0_CONTROL_REG0_RXDIS_SHIFT 3 +#define UART0_CONTROL_REG0_RXDIS_MASK 0x00000008U -/*Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero.*/ +/* +* Receive enable: 0: disable 1: enable When set to one, the receiver logic + * is enabled, provided the RXDIS field is set to zero. +*/ #undef UART0_CONTROL_REG0_RXEN_DEFVAL #undef UART0_CONTROL_REG0_RXEN_SHIFT #undef UART0_CONTROL_REG0_RXEN_MASK -#define UART0_CONTROL_REG0_RXEN_DEFVAL 0x00000128 -#define UART0_CONTROL_REG0_RXEN_SHIFT 2 -#define UART0_CONTROL_REG0_RXEN_MASK 0x00000004U +#define UART0_CONTROL_REG0_RXEN_DEFVAL 0x00000128 +#define UART0_CONTROL_REG0_RXEN_SHIFT 2 +#define UART0_CONTROL_REG0_RXEN_MASK 0x00000004U -/*Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded Thi - bit is self clearing once the reset has completed.*/ +/* +* Software reset for Tx data path: 0: no affect 1: transmitter logic is re + * set and all pending transmitter data is discarded This bit is self clear + * ing once the reset has completed. +*/ #undef UART0_CONTROL_REG0_TXRES_DEFVAL #undef UART0_CONTROL_REG0_TXRES_SHIFT #undef UART0_CONTROL_REG0_TXRES_MASK -#define UART0_CONTROL_REG0_TXRES_DEFVAL 0x00000128 -#define UART0_CONTROL_REG0_TXRES_SHIFT 1 -#define UART0_CONTROL_REG0_TXRES_MASK 0x00000002U +#define UART0_CONTROL_REG0_TXRES_DEFVAL 0x00000128 +#define UART0_CONTROL_REG0_TXRES_SHIFT 1 +#define UART0_CONTROL_REG0_TXRES_MASK 0x00000002U -/*Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit - is self clearing once the reset has completed.*/ +/* +* Software reset for Rx data path: 0: no affect 1: receiver logic is reset + * and all pending receiver data is discarded. This bit is self clearing o + * nce the reset has completed. +*/ #undef UART0_CONTROL_REG0_RXRES_DEFVAL #undef UART0_CONTROL_REG0_RXRES_SHIFT #undef UART0_CONTROL_REG0_RXRES_MASK -#define UART0_CONTROL_REG0_RXRES_DEFVAL 0x00000128 -#define UART0_CONTROL_REG0_RXRES_SHIFT 0 -#define UART0_CONTROL_REG0_RXRES_MASK 0x00000001U +#define UART0_CONTROL_REG0_RXRES_DEFVAL 0x00000128 +#define UART0_CONTROL_REG0_RXRES_SHIFT 0 +#define UART0_CONTROL_REG0_RXRES_MASK 0x00000001U -/*Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback*/ +/* +* Channel mode: Defines the mode of operation of the UART. 00: normal 01: + * automatic echo 10: local loopback 11: remote loopback +*/ #undef UART0_MODE_REG0_CHMODE_DEFVAL #undef UART0_MODE_REG0_CHMODE_SHIFT #undef UART0_MODE_REG0_CHMODE_MASK -#define UART0_MODE_REG0_CHMODE_DEFVAL 0x00000000 -#define UART0_MODE_REG0_CHMODE_SHIFT 8 -#define UART0_MODE_REG0_CHMODE_MASK 0x00000300U +#define UART0_MODE_REG0_CHMODE_DEFVAL 0x00000000 +#define UART0_MODE_REG0_CHMODE_SHIFT 8 +#define UART0_MODE_REG0_CHMODE_MASK 0x00000300U -/*Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5 - stop bits 10: 2 stop bits 11: reserved*/ +/* +* Number of stop bits: Defines the number of stop bits to detect on receiv + * e and to generate on transmit. 00: 1 stop bit 01: 1.5 stop bits 10: 2 st + * op bits 11: reserved +*/ #undef UART0_MODE_REG0_NBSTOP_DEFVAL #undef UART0_MODE_REG0_NBSTOP_SHIFT #undef UART0_MODE_REG0_NBSTOP_MASK -#define UART0_MODE_REG0_NBSTOP_DEFVAL 0x00000000 -#define UART0_MODE_REG0_NBSTOP_SHIFT 6 -#define UART0_MODE_REG0_NBSTOP_MASK 0x000000C0U +#define UART0_MODE_REG0_NBSTOP_DEFVAL 0x00000000 +#define UART0_MODE_REG0_NBSTOP_SHIFT 6 +#define UART0_MODE_REG0_NBSTOP_MASK 0x000000C0U -/*Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity - 01: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity*/ +/* +* Parity type select: Defines the expected parity to check on receive and + * the parity to generate on transmit. 000: even parity 001: odd parity 010 + * : forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no pari + * ty +*/ #undef UART0_MODE_REG0_PAR_DEFVAL #undef UART0_MODE_REG0_PAR_SHIFT #undef UART0_MODE_REG0_PAR_MASK -#define UART0_MODE_REG0_PAR_DEFVAL 0x00000000 -#define UART0_MODE_REG0_PAR_SHIFT 3 -#define UART0_MODE_REG0_PAR_MASK 0x00000038U +#define UART0_MODE_REG0_PAR_DEFVAL 0x00000000 +#define UART0_MODE_REG0_PAR_SHIFT 3 +#define UART0_MODE_REG0_PAR_MASK 0x00000038U -/*Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits*/ +/* +* Character length select: Defines the number of bits in each character. 1 + * 1: 6 bits 10: 7 bits 0x: 8 bits +*/ #undef UART0_MODE_REG0_CHRL_DEFVAL #undef UART0_MODE_REG0_CHRL_SHIFT #undef UART0_MODE_REG0_CHRL_MASK -#define UART0_MODE_REG0_CHRL_DEFVAL 0x00000000 -#define UART0_MODE_REG0_CHRL_SHIFT 1 -#define UART0_MODE_REG0_CHRL_MASK 0x00000006U +#define UART0_MODE_REG0_CHRL_DEFVAL 0x00000000 +#define UART0_MODE_REG0_CHRL_SHIFT 1 +#define UART0_MODE_REG0_CHRL_MASK 0x00000006U -/*Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock - source is uart_ref_clk 1: clock source is uart_ref_clk/8*/ +/* +* Clock source select: This field defines whether a pre-scalar of 8 is app + * lied to the baud rate generator input clock. 0: clock source is uart_ref + * _clk 1: clock source is uart_ref_clk/8 +*/ #undef UART0_MODE_REG0_CLKS_DEFVAL #undef UART0_MODE_REG0_CLKS_SHIFT #undef UART0_MODE_REG0_CLKS_MASK -#define UART0_MODE_REG0_CLKS_DEFVAL 0x00000000 -#define UART0_MODE_REG0_CLKS_SHIFT 0 -#define UART0_MODE_REG0_CLKS_MASK 0x00000001U +#define UART0_MODE_REG0_CLKS_DEFVAL 0x00000000 +#define UART0_MODE_REG0_CLKS_SHIFT 0 +#define UART0_MODE_REG0_CLKS_MASK 0x00000001U -/*Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate*/ +/* +* Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate +*/ #undef UART1_BAUD_RATE_DIVIDER_REG0_BDIV_DEFVAL #undef UART1_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT #undef UART1_BAUD_RATE_DIVIDER_REG0_BDIV_MASK -#define UART1_BAUD_RATE_DIVIDER_REG0_BDIV_DEFVAL 0x0000000F -#define UART1_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT 0 -#define UART1_BAUD_RATE_DIVIDER_REG0_BDIV_MASK 0x000000FFU +#define UART1_BAUD_RATE_DIVIDER_REG0_BDIV_DEFVAL 0x0000000F +#define UART1_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT 0 +#define UART1_BAUD_RATE_DIVIDER_REG0_BDIV_MASK 0x000000FFU -/*Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample*/ +/* +* Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor + * bypass (baud_sample = sel_clk) 2 - 65535: baud_sample +*/ #undef UART1_BAUD_RATE_GEN_REG0_CD_DEFVAL #undef UART1_BAUD_RATE_GEN_REG0_CD_SHIFT #undef UART1_BAUD_RATE_GEN_REG0_CD_MASK -#define UART1_BAUD_RATE_GEN_REG0_CD_DEFVAL 0x0000028B -#define UART1_BAUD_RATE_GEN_REG0_CD_SHIFT 0 -#define UART1_BAUD_RATE_GEN_REG0_CD_MASK 0x0000FFFFU +#define UART1_BAUD_RATE_GEN_REG0_CD_DEFVAL 0x0000028B +#define UART1_BAUD_RATE_GEN_REG0_CD_SHIFT 0 +#define UART1_BAUD_RATE_GEN_REG0_CD_MASK 0x0000FFFFU -/*Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a - high level during 12 bit periods. It can be set regardless of the value of STTBRK.*/ +/* +* Stop transmitter break: 0: no affect 1: stop transmission of the break a + * fter a minimum of one character length and transmit a high level during + * 12 bit periods. It can be set regardless of the value of STTBRK. +*/ #undef UART1_CONTROL_REG0_STPBRK_DEFVAL #undef UART1_CONTROL_REG0_STPBRK_SHIFT #undef UART1_CONTROL_REG0_STPBRK_MASK -#define UART1_CONTROL_REG0_STPBRK_DEFVAL 0x00000128 -#define UART1_CONTROL_REG0_STPBRK_SHIFT 8 -#define UART1_CONTROL_REG0_STPBRK_MASK 0x00000100U +#define UART1_CONTROL_REG0_STPBRK_DEFVAL 0x00000128 +#define UART1_CONTROL_REG0_STPBRK_SHIFT 8 +#define UART1_CONTROL_REG0_STPBRK_MASK 0x00000100U -/*Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the - transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high.*/ +/* +* Start transmitter break: 0: no affect 1: start to transmit a break after + * the characters currently present in the FIFO and the transmit shift reg + * ister have been transmitted. It can only be set if STPBRK (Stop transmit + * ter break) is not high. +*/ #undef UART1_CONTROL_REG0_STTBRK_DEFVAL #undef UART1_CONTROL_REG0_STTBRK_SHIFT #undef UART1_CONTROL_REG0_STTBRK_MASK -#define UART1_CONTROL_REG0_STTBRK_DEFVAL 0x00000128 -#define UART1_CONTROL_REG0_STTBRK_SHIFT 7 -#define UART1_CONTROL_REG0_STTBRK_MASK 0x00000080U +#define UART1_CONTROL_REG0_STTBRK_DEFVAL 0x00000128 +#define UART1_CONTROL_REG0_STTBRK_SHIFT 7 +#define UART1_CONTROL_REG0_STTBRK_MASK 0x00000080U -/*Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has co - pleted.*/ +/* +* Restart receiver timeout counter: 1: receiver timeout counter is restart + * ed. This bit is self clearing once the restart has completed. +*/ #undef UART1_CONTROL_REG0_RSTTO_DEFVAL #undef UART1_CONTROL_REG0_RSTTO_SHIFT #undef UART1_CONTROL_REG0_RSTTO_MASK -#define UART1_CONTROL_REG0_RSTTO_DEFVAL 0x00000128 -#define UART1_CONTROL_REG0_RSTTO_SHIFT 6 -#define UART1_CONTROL_REG0_RSTTO_MASK 0x00000040U +#define UART1_CONTROL_REG0_RSTTO_DEFVAL 0x00000128 +#define UART1_CONTROL_REG0_RSTTO_SHIFT 6 +#define UART1_CONTROL_REG0_RSTTO_MASK 0x00000040U -/*Transmit disable: 0: enable transmitter 1: disable transmitter*/ +/* +* Transmit disable: 0: enable transmitter 1: disable transmitter +*/ #undef UART1_CONTROL_REG0_TXDIS_DEFVAL #undef UART1_CONTROL_REG0_TXDIS_SHIFT #undef UART1_CONTROL_REG0_TXDIS_MASK -#define UART1_CONTROL_REG0_TXDIS_DEFVAL 0x00000128 -#define UART1_CONTROL_REG0_TXDIS_SHIFT 5 -#define UART1_CONTROL_REG0_TXDIS_MASK 0x00000020U +#define UART1_CONTROL_REG0_TXDIS_DEFVAL 0x00000128 +#define UART1_CONTROL_REG0_TXDIS_SHIFT 5 +#define UART1_CONTROL_REG0_TXDIS_MASK 0x00000020U -/*Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0.*/ +/* +* Transmit enable: 0: disable transmitter 1: enable transmitter, provided + * the TXDIS field is set to 0. +*/ #undef UART1_CONTROL_REG0_TXEN_DEFVAL #undef UART1_CONTROL_REG0_TXEN_SHIFT #undef UART1_CONTROL_REG0_TXEN_MASK -#define UART1_CONTROL_REG0_TXEN_DEFVAL 0x00000128 -#define UART1_CONTROL_REG0_TXEN_SHIFT 4 -#define UART1_CONTROL_REG0_TXEN_MASK 0x00000010U +#define UART1_CONTROL_REG0_TXEN_DEFVAL 0x00000128 +#define UART1_CONTROL_REG0_TXEN_SHIFT 4 +#define UART1_CONTROL_REG0_TXEN_MASK 0x00000010U -/*Receive disable: 0: enable 1: disable, regardless of the value of RXEN*/ +/* +* Receive disable: 0: enable 1: disable, regardless of the value of RXEN +*/ #undef UART1_CONTROL_REG0_RXDIS_DEFVAL #undef UART1_CONTROL_REG0_RXDIS_SHIFT #undef UART1_CONTROL_REG0_RXDIS_MASK -#define UART1_CONTROL_REG0_RXDIS_DEFVAL 0x00000128 -#define UART1_CONTROL_REG0_RXDIS_SHIFT 3 -#define UART1_CONTROL_REG0_RXDIS_MASK 0x00000008U +#define UART1_CONTROL_REG0_RXDIS_DEFVAL 0x00000128 +#define UART1_CONTROL_REG0_RXDIS_SHIFT 3 +#define UART1_CONTROL_REG0_RXDIS_MASK 0x00000008U -/*Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero.*/ +/* +* Receive enable: 0: disable 1: enable When set to one, the receiver logic + * is enabled, provided the RXDIS field is set to zero. +*/ #undef UART1_CONTROL_REG0_RXEN_DEFVAL #undef UART1_CONTROL_REG0_RXEN_SHIFT #undef UART1_CONTROL_REG0_RXEN_MASK -#define UART1_CONTROL_REG0_RXEN_DEFVAL 0x00000128 -#define UART1_CONTROL_REG0_RXEN_SHIFT 2 -#define UART1_CONTROL_REG0_RXEN_MASK 0x00000004U +#define UART1_CONTROL_REG0_RXEN_DEFVAL 0x00000128 +#define UART1_CONTROL_REG0_RXEN_SHIFT 2 +#define UART1_CONTROL_REG0_RXEN_MASK 0x00000004U -/*Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded Thi - bit is self clearing once the reset has completed.*/ +/* +* Software reset for Tx data path: 0: no affect 1: transmitter logic is re + * set and all pending transmitter data is discarded This bit is self clear + * ing once the reset has completed. +*/ #undef UART1_CONTROL_REG0_TXRES_DEFVAL #undef UART1_CONTROL_REG0_TXRES_SHIFT #undef UART1_CONTROL_REG0_TXRES_MASK -#define UART1_CONTROL_REG0_TXRES_DEFVAL 0x00000128 -#define UART1_CONTROL_REG0_TXRES_SHIFT 1 -#define UART1_CONTROL_REG0_TXRES_MASK 0x00000002U +#define UART1_CONTROL_REG0_TXRES_DEFVAL 0x00000128 +#define UART1_CONTROL_REG0_TXRES_SHIFT 1 +#define UART1_CONTROL_REG0_TXRES_MASK 0x00000002U -/*Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit - is self clearing once the reset has completed.*/ +/* +* Software reset for Rx data path: 0: no affect 1: receiver logic is reset + * and all pending receiver data is discarded. This bit is self clearing o + * nce the reset has completed. +*/ #undef UART1_CONTROL_REG0_RXRES_DEFVAL #undef UART1_CONTROL_REG0_RXRES_SHIFT #undef UART1_CONTROL_REG0_RXRES_MASK -#define UART1_CONTROL_REG0_RXRES_DEFVAL 0x00000128 -#define UART1_CONTROL_REG0_RXRES_SHIFT 0 -#define UART1_CONTROL_REG0_RXRES_MASK 0x00000001U +#define UART1_CONTROL_REG0_RXRES_DEFVAL 0x00000128 +#define UART1_CONTROL_REG0_RXRES_SHIFT 0 +#define UART1_CONTROL_REG0_RXRES_MASK 0x00000001U -/*Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback*/ +/* +* Channel mode: Defines the mode of operation of the UART. 00: normal 01: + * automatic echo 10: local loopback 11: remote loopback +*/ #undef UART1_MODE_REG0_CHMODE_DEFVAL #undef UART1_MODE_REG0_CHMODE_SHIFT #undef UART1_MODE_REG0_CHMODE_MASK -#define UART1_MODE_REG0_CHMODE_DEFVAL 0x00000000 -#define UART1_MODE_REG0_CHMODE_SHIFT 8 -#define UART1_MODE_REG0_CHMODE_MASK 0x00000300U +#define UART1_MODE_REG0_CHMODE_DEFVAL 0x00000000 +#define UART1_MODE_REG0_CHMODE_SHIFT 8 +#define UART1_MODE_REG0_CHMODE_MASK 0x00000300U -/*Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5 - stop bits 10: 2 stop bits 11: reserved*/ +/* +* Number of stop bits: Defines the number of stop bits to detect on receiv + * e and to generate on transmit. 00: 1 stop bit 01: 1.5 stop bits 10: 2 st + * op bits 11: reserved +*/ #undef UART1_MODE_REG0_NBSTOP_DEFVAL #undef UART1_MODE_REG0_NBSTOP_SHIFT #undef UART1_MODE_REG0_NBSTOP_MASK -#define UART1_MODE_REG0_NBSTOP_DEFVAL 0x00000000 -#define UART1_MODE_REG0_NBSTOP_SHIFT 6 -#define UART1_MODE_REG0_NBSTOP_MASK 0x000000C0U +#define UART1_MODE_REG0_NBSTOP_DEFVAL 0x00000000 +#define UART1_MODE_REG0_NBSTOP_SHIFT 6 +#define UART1_MODE_REG0_NBSTOP_MASK 0x000000C0U -/*Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity - 01: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity*/ +/* +* Parity type select: Defines the expected parity to check on receive and + * the parity to generate on transmit. 000: even parity 001: odd parity 010 + * : forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no pari + * ty +*/ #undef UART1_MODE_REG0_PAR_DEFVAL #undef UART1_MODE_REG0_PAR_SHIFT #undef UART1_MODE_REG0_PAR_MASK -#define UART1_MODE_REG0_PAR_DEFVAL 0x00000000 -#define UART1_MODE_REG0_PAR_SHIFT 3 -#define UART1_MODE_REG0_PAR_MASK 0x00000038U +#define UART1_MODE_REG0_PAR_DEFVAL 0x00000000 +#define UART1_MODE_REG0_PAR_SHIFT 3 +#define UART1_MODE_REG0_PAR_MASK 0x00000038U -/*Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits*/ +/* +* Character length select: Defines the number of bits in each character. 1 + * 1: 6 bits 10: 7 bits 0x: 8 bits +*/ #undef UART1_MODE_REG0_CHRL_DEFVAL #undef UART1_MODE_REG0_CHRL_SHIFT #undef UART1_MODE_REG0_CHRL_MASK -#define UART1_MODE_REG0_CHRL_DEFVAL 0x00000000 -#define UART1_MODE_REG0_CHRL_SHIFT 1 -#define UART1_MODE_REG0_CHRL_MASK 0x00000006U +#define UART1_MODE_REG0_CHRL_DEFVAL 0x00000000 +#define UART1_MODE_REG0_CHRL_SHIFT 1 +#define UART1_MODE_REG0_CHRL_MASK 0x00000006U -/*Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock - source is uart_ref_clk 1: clock source is uart_ref_clk/8*/ +/* +* Clock source select: This field defines whether a pre-scalar of 8 is app + * lied to the baud rate generator input clock. 0: clock source is uart_ref + * _clk 1: clock source is uart_ref_clk/8 +*/ #undef UART1_MODE_REG0_CLKS_DEFVAL #undef UART1_MODE_REG0_CLKS_SHIFT #undef UART1_MODE_REG0_CLKS_MASK -#define UART1_MODE_REG0_CLKS_DEFVAL 0x00000000 -#define UART1_MODE_REG0_CLKS_SHIFT 0 -#define UART1_MODE_REG0_CLKS_MASK 0x00000001U +#define UART1_MODE_REG0_CLKS_DEFVAL 0x00000000 +#define UART1_MODE_REG0_CLKS_SHIFT 0 +#define UART1_MODE_REG0_CLKS_MASK 0x00000001U -/*TrustZone Classification for ADMA*/ +/* +* Block level reset +*/ +#undef CRL_APB_RST_LPD_IOU2_GPIO_RESET_DEFVAL +#undef CRL_APB_RST_LPD_IOU2_GPIO_RESET_SHIFT +#undef CRL_APB_RST_LPD_IOU2_GPIO_RESET_MASK +#define CRL_APB_RST_LPD_IOU2_GPIO_RESET_DEFVAL 0x0017FFFF +#define CRL_APB_RST_LPD_IOU2_GPIO_RESET_SHIFT 18 +#define CRL_APB_RST_LPD_IOU2_GPIO_RESET_MASK 0x00040000U + +/* +* TrustZone Classification for ADMA +*/ #undef LPD_SLCR_SECURE_SLCR_ADMA_TZ_DEFVAL #undef LPD_SLCR_SECURE_SLCR_ADMA_TZ_SHIFT #undef LPD_SLCR_SECURE_SLCR_ADMA_TZ_MASK -#define LPD_SLCR_SECURE_SLCR_ADMA_TZ_DEFVAL -#define LPD_SLCR_SECURE_SLCR_ADMA_TZ_SHIFT 0 -#define LPD_SLCR_SECURE_SLCR_ADMA_TZ_MASK 0x000000FFU +#define LPD_SLCR_SECURE_SLCR_ADMA_TZ_DEFVAL +#define LPD_SLCR_SECURE_SLCR_ADMA_TZ_SHIFT 0 +#define LPD_SLCR_SECURE_SLCR_ADMA_TZ_MASK 0x000000FFU -/*CSU regsiter*/ +/* +* CSU regsiter +*/ #undef CSU_TAMPER_STATUS_TAMPER_0_DEFVAL #undef CSU_TAMPER_STATUS_TAMPER_0_SHIFT #undef CSU_TAMPER_STATUS_TAMPER_0_MASK -#define CSU_TAMPER_STATUS_TAMPER_0_DEFVAL 0x00000000 -#define CSU_TAMPER_STATUS_TAMPER_0_SHIFT 0 -#define CSU_TAMPER_STATUS_TAMPER_0_MASK 0x00000001U +#define CSU_TAMPER_STATUS_TAMPER_0_DEFVAL 0x00000000 +#define CSU_TAMPER_STATUS_TAMPER_0_SHIFT 0 +#define CSU_TAMPER_STATUS_TAMPER_0_MASK 0x00000001U -/*External MIO*/ +/* +* External MIO +*/ #undef CSU_TAMPER_STATUS_TAMPER_1_DEFVAL #undef CSU_TAMPER_STATUS_TAMPER_1_SHIFT #undef CSU_TAMPER_STATUS_TAMPER_1_MASK -#define CSU_TAMPER_STATUS_TAMPER_1_DEFVAL 0x00000000 -#define CSU_TAMPER_STATUS_TAMPER_1_SHIFT 1 -#define CSU_TAMPER_STATUS_TAMPER_1_MASK 0x00000002U +#define CSU_TAMPER_STATUS_TAMPER_1_DEFVAL 0x00000000 +#define CSU_TAMPER_STATUS_TAMPER_1_SHIFT 1 +#define CSU_TAMPER_STATUS_TAMPER_1_MASK 0x00000002U -/*JTAG toggle detect*/ +/* +* JTAG toggle detect +*/ #undef CSU_TAMPER_STATUS_TAMPER_2_DEFVAL #undef CSU_TAMPER_STATUS_TAMPER_2_SHIFT #undef CSU_TAMPER_STATUS_TAMPER_2_MASK -#define CSU_TAMPER_STATUS_TAMPER_2_DEFVAL 0x00000000 -#define CSU_TAMPER_STATUS_TAMPER_2_SHIFT 2 -#define CSU_TAMPER_STATUS_TAMPER_2_MASK 0x00000004U +#define CSU_TAMPER_STATUS_TAMPER_2_DEFVAL 0x00000000 +#define CSU_TAMPER_STATUS_TAMPER_2_SHIFT 2 +#define CSU_TAMPER_STATUS_TAMPER_2_MASK 0x00000004U -/*PL SEU error*/ +/* +* PL SEU error +*/ #undef CSU_TAMPER_STATUS_TAMPER_3_DEFVAL #undef CSU_TAMPER_STATUS_TAMPER_3_SHIFT #undef CSU_TAMPER_STATUS_TAMPER_3_MASK -#define CSU_TAMPER_STATUS_TAMPER_3_DEFVAL 0x00000000 -#define CSU_TAMPER_STATUS_TAMPER_3_SHIFT 3 -#define CSU_TAMPER_STATUS_TAMPER_3_MASK 0x00000008U +#define CSU_TAMPER_STATUS_TAMPER_3_DEFVAL 0x00000000 +#define CSU_TAMPER_STATUS_TAMPER_3_SHIFT 3 +#define CSU_TAMPER_STATUS_TAMPER_3_MASK 0x00000008U -/*AMS over temperature alarm for LPD*/ +/* +* AMS over temperature alarm for LPD +*/ #undef CSU_TAMPER_STATUS_TAMPER_4_DEFVAL #undef CSU_TAMPER_STATUS_TAMPER_4_SHIFT #undef CSU_TAMPER_STATUS_TAMPER_4_MASK -#define CSU_TAMPER_STATUS_TAMPER_4_DEFVAL 0x00000000 -#define CSU_TAMPER_STATUS_TAMPER_4_SHIFT 4 -#define CSU_TAMPER_STATUS_TAMPER_4_MASK 0x00000010U +#define CSU_TAMPER_STATUS_TAMPER_4_DEFVAL 0x00000000 +#define CSU_TAMPER_STATUS_TAMPER_4_SHIFT 4 +#define CSU_TAMPER_STATUS_TAMPER_4_MASK 0x00000010U -/*AMS over temperature alarm for APU*/ +/* +* AMS over temperature alarm for APU +*/ #undef CSU_TAMPER_STATUS_TAMPER_5_DEFVAL #undef CSU_TAMPER_STATUS_TAMPER_5_SHIFT #undef CSU_TAMPER_STATUS_TAMPER_5_MASK -#define CSU_TAMPER_STATUS_TAMPER_5_DEFVAL 0x00000000 -#define CSU_TAMPER_STATUS_TAMPER_5_SHIFT 5 -#define CSU_TAMPER_STATUS_TAMPER_5_MASK 0x00000020U +#define CSU_TAMPER_STATUS_TAMPER_5_DEFVAL 0x00000000 +#define CSU_TAMPER_STATUS_TAMPER_5_SHIFT 5 +#define CSU_TAMPER_STATUS_TAMPER_5_MASK 0x00000020U -/*AMS voltage alarm for VCCPINT_FPD*/ +/* +* AMS voltage alarm for VCCPINT_FPD +*/ #undef CSU_TAMPER_STATUS_TAMPER_6_DEFVAL #undef CSU_TAMPER_STATUS_TAMPER_6_SHIFT #undef CSU_TAMPER_STATUS_TAMPER_6_MASK -#define CSU_TAMPER_STATUS_TAMPER_6_DEFVAL 0x00000000 -#define CSU_TAMPER_STATUS_TAMPER_6_SHIFT 6 -#define CSU_TAMPER_STATUS_TAMPER_6_MASK 0x00000040U +#define CSU_TAMPER_STATUS_TAMPER_6_DEFVAL 0x00000000 +#define CSU_TAMPER_STATUS_TAMPER_6_SHIFT 6 +#define CSU_TAMPER_STATUS_TAMPER_6_MASK 0x00000040U -/*AMS voltage alarm for VCCPINT_LPD*/ +/* +* AMS voltage alarm for VCCPINT_LPD +*/ #undef CSU_TAMPER_STATUS_TAMPER_7_DEFVAL #undef CSU_TAMPER_STATUS_TAMPER_7_SHIFT #undef CSU_TAMPER_STATUS_TAMPER_7_MASK -#define CSU_TAMPER_STATUS_TAMPER_7_DEFVAL 0x00000000 -#define CSU_TAMPER_STATUS_TAMPER_7_SHIFT 7 -#define CSU_TAMPER_STATUS_TAMPER_7_MASK 0x00000080U +#define CSU_TAMPER_STATUS_TAMPER_7_DEFVAL 0x00000000 +#define CSU_TAMPER_STATUS_TAMPER_7_SHIFT 7 +#define CSU_TAMPER_STATUS_TAMPER_7_MASK 0x00000080U -/*AMS voltage alarm for VCCPAUX*/ +/* +* AMS voltage alarm for VCCPAUX +*/ #undef CSU_TAMPER_STATUS_TAMPER_8_DEFVAL #undef CSU_TAMPER_STATUS_TAMPER_8_SHIFT #undef CSU_TAMPER_STATUS_TAMPER_8_MASK -#define CSU_TAMPER_STATUS_TAMPER_8_DEFVAL 0x00000000 -#define CSU_TAMPER_STATUS_TAMPER_8_SHIFT 8 -#define CSU_TAMPER_STATUS_TAMPER_8_MASK 0x00000100U +#define CSU_TAMPER_STATUS_TAMPER_8_DEFVAL 0x00000000 +#define CSU_TAMPER_STATUS_TAMPER_8_SHIFT 8 +#define CSU_TAMPER_STATUS_TAMPER_8_MASK 0x00000100U -/*AMS voltage alarm for DDRPHY*/ +/* +* AMS voltage alarm for DDRPHY +*/ #undef CSU_TAMPER_STATUS_TAMPER_9_DEFVAL #undef CSU_TAMPER_STATUS_TAMPER_9_SHIFT #undef CSU_TAMPER_STATUS_TAMPER_9_MASK -#define CSU_TAMPER_STATUS_TAMPER_9_DEFVAL 0x00000000 -#define CSU_TAMPER_STATUS_TAMPER_9_SHIFT 9 -#define CSU_TAMPER_STATUS_TAMPER_9_MASK 0x00000200U +#define CSU_TAMPER_STATUS_TAMPER_9_DEFVAL 0x00000000 +#define CSU_TAMPER_STATUS_TAMPER_9_SHIFT 9 +#define CSU_TAMPER_STATUS_TAMPER_9_MASK 0x00000200U -/*AMS voltage alarm for PSIO bank 0/1/2*/ +/* +* AMS voltage alarm for PSIO bank 0/1/2 +*/ #undef CSU_TAMPER_STATUS_TAMPER_10_DEFVAL #undef CSU_TAMPER_STATUS_TAMPER_10_SHIFT #undef CSU_TAMPER_STATUS_TAMPER_10_MASK -#define CSU_TAMPER_STATUS_TAMPER_10_DEFVAL 0x00000000 -#define CSU_TAMPER_STATUS_TAMPER_10_SHIFT 10 -#define CSU_TAMPER_STATUS_TAMPER_10_MASK 0x00000400U +#define CSU_TAMPER_STATUS_TAMPER_10_DEFVAL 0x00000000 +#define CSU_TAMPER_STATUS_TAMPER_10_SHIFT 10 +#define CSU_TAMPER_STATUS_TAMPER_10_MASK 0x00000400U -/*AMS voltage alarm for PSIO bank 3 (dedicated pins)*/ +/* +* AMS voltage alarm for PSIO bank 3 (dedicated pins) +*/ #undef CSU_TAMPER_STATUS_TAMPER_11_DEFVAL #undef CSU_TAMPER_STATUS_TAMPER_11_SHIFT #undef CSU_TAMPER_STATUS_TAMPER_11_MASK -#define CSU_TAMPER_STATUS_TAMPER_11_DEFVAL 0x00000000 -#define CSU_TAMPER_STATUS_TAMPER_11_SHIFT 11 -#define CSU_TAMPER_STATUS_TAMPER_11_MASK 0x00000800U +#define CSU_TAMPER_STATUS_TAMPER_11_DEFVAL 0x00000000 +#define CSU_TAMPER_STATUS_TAMPER_11_SHIFT 11 +#define CSU_TAMPER_STATUS_TAMPER_11_MASK 0x00000800U -/*AMS voltaage alarm for GT*/ +/* +* AMS voltaage alarm for GT +*/ #undef CSU_TAMPER_STATUS_TAMPER_12_DEFVAL #undef CSU_TAMPER_STATUS_TAMPER_12_SHIFT #undef CSU_TAMPER_STATUS_TAMPER_12_MASK -#define CSU_TAMPER_STATUS_TAMPER_12_DEFVAL 0x00000000 -#define CSU_TAMPER_STATUS_TAMPER_12_SHIFT 12 -#define CSU_TAMPER_STATUS_TAMPER_12_MASK 0x00001000U +#define CSU_TAMPER_STATUS_TAMPER_12_DEFVAL 0x00000000 +#define CSU_TAMPER_STATUS_TAMPER_12_SHIFT 12 +#define CSU_TAMPER_STATUS_TAMPER_12_MASK 0x00001000U -/*Set ACE outgoing AWQOS value*/ +/* +* Set ACE outgoing AWQOS value +*/ #undef APU_ACE_CTRL_AWQOS_DEFVAL #undef APU_ACE_CTRL_AWQOS_SHIFT #undef APU_ACE_CTRL_AWQOS_MASK -#define APU_ACE_CTRL_AWQOS_DEFVAL 0x000F000F -#define APU_ACE_CTRL_AWQOS_SHIFT 16 -#define APU_ACE_CTRL_AWQOS_MASK 0x000F0000U +#define APU_ACE_CTRL_AWQOS_DEFVAL 0x000F000F +#define APU_ACE_CTRL_AWQOS_SHIFT 16 +#define APU_ACE_CTRL_AWQOS_MASK 0x000F0000U -/*Set ACE outgoing ARQOS value*/ +/* +* Set ACE outgoing ARQOS value +*/ #undef APU_ACE_CTRL_ARQOS_DEFVAL #undef APU_ACE_CTRL_ARQOS_SHIFT #undef APU_ACE_CTRL_ARQOS_MASK -#define APU_ACE_CTRL_ARQOS_DEFVAL 0x000F000F -#define APU_ACE_CTRL_ARQOS_SHIFT 0 -#define APU_ACE_CTRL_ARQOS_MASK 0x0000000FU +#define APU_ACE_CTRL_ARQOS_DEFVAL 0x000F000F +#define APU_ACE_CTRL_ARQOS_SHIFT 0 +#define APU_ACE_CTRL_ARQOS_MASK 0x0000000FU -/*Enables the RTC. By writing a 0 to this bit, RTC will be powered off and the only module that potentially draws current from - he battery will be BBRAM. The value read through this bit does not necessarily reflect whether RTC is enabled or not. It is e - pected that RTC is enabled every time it is being configured. If RTC is not used in the design, FSBL will disable it by writi - g a 0 to this bit.*/ +/* +* Enables the RTC. By writing a 0 to this bit, RTC will be powered off and + * the only module that potentially draws current from the battery will be + * BBRAM. The value read through this bit does not necessarily reflect whe + * ther RTC is enabled or not. It is expected that RTC is enabled every tim + * e it is being configured. If RTC is not used in the design, FSBL will di + * sable it by writing a 0 to this bit. +*/ #undef RTC_CONTROL_BATTERY_DISABLE_DEFVAL #undef RTC_CONTROL_BATTERY_DISABLE_SHIFT #undef RTC_CONTROL_BATTERY_DISABLE_MASK -#define RTC_CONTROL_BATTERY_DISABLE_DEFVAL 0x01000000 -#define RTC_CONTROL_BATTERY_DISABLE_SHIFT 31 -#define RTC_CONTROL_BATTERY_DISABLE_MASK 0x80000000U +#define RTC_CONTROL_BATTERY_DISABLE_DEFVAL 0x01000000 +#define RTC_CONTROL_BATTERY_DISABLE_SHIFT 31 +#define RTC_CONTROL_BATTERY_DISABLE_MASK 0x80000000U -/*Frequency in number of ticks per second. Valid range from 10 MHz to 100 MHz.*/ +/* +* Frequency in number of ticks per second. Valid range from 10 MHz to 100 + * MHz. +*/ #undef IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_DEFVAL #undef IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_SHIFT #undef IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_MASK -#define IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_DEFVAL -#define IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_SHIFT 0 -#define IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_MASK 0xFFFFFFFFU +#define IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_DEFVAL +#define IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_SHIFT 0 +#define IOU_SCNTRS_BASE_FREQUENCY_ID_REGISTER_FREQ_MASK 0xFFFFFFFFU -/*Enable 0: The counter is disabled and not incrementing. 1: The counter is enabled and is incrementing.*/ +/* +* Enable 0: The counter is disabled and not incrementing. 1: The counter i + * s enabled and is incrementing. +*/ #undef IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_DEFVAL #undef IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_SHIFT #undef IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_MASK -#define IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_DEFVAL 0x00000000 -#define IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_SHIFT 0 -#define IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_MASK 0x00000001U -#undef LPD_XPPU_CFG_IEN_OFFSET -#define LPD_XPPU_CFG_IEN_OFFSET 0XFF980018 +#define IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_DEFVAL 0x00000000 +#define IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_SHIFT 0 +#define IOU_SCNTRS_COUNTER_CONTROL_REGISTER_EN_MASK 0x00000001U -/*See Interuppt Status Register for details*/ -#undef LPD_XPPU_CFG_IEN_APER_PARITY_DEFVAL -#undef LPD_XPPU_CFG_IEN_APER_PARITY_SHIFT -#undef LPD_XPPU_CFG_IEN_APER_PARITY_MASK -#define LPD_XPPU_CFG_IEN_APER_PARITY_DEFVAL 0x00000000 -#define LPD_XPPU_CFG_IEN_APER_PARITY_SHIFT 7 -#define LPD_XPPU_CFG_IEN_APER_PARITY_MASK 0x00000080U +/* +* Operation is the same as DIRM_0[DIRECTION_0] +*/ +#undef GPIO_DIRM_1_DIRECTION_1_DEFVAL +#undef GPIO_DIRM_1_DIRECTION_1_SHIFT +#undef GPIO_DIRM_1_DIRECTION_1_MASK +#define GPIO_DIRM_1_DIRECTION_1_DEFVAL 0x00000000 +#define GPIO_DIRM_1_DIRECTION_1_SHIFT 0 +#define GPIO_DIRM_1_DIRECTION_1_MASK 0x03FFFFFFU -/*See Interuppt Status Register for details*/ -#undef LPD_XPPU_CFG_IEN_APER_TZ_DEFVAL -#undef LPD_XPPU_CFG_IEN_APER_TZ_SHIFT -#undef LPD_XPPU_CFG_IEN_APER_TZ_MASK -#define LPD_XPPU_CFG_IEN_APER_TZ_DEFVAL 0x00000000 -#define LPD_XPPU_CFG_IEN_APER_TZ_SHIFT 6 -#define LPD_XPPU_CFG_IEN_APER_TZ_MASK 0x00000040U +/* +* Operation is the same as OEN_0[OP_ENABLE_0] +*/ +#undef GPIO_OEN_1_OP_ENABLE_1_DEFVAL +#undef GPIO_OEN_1_OP_ENABLE_1_SHIFT +#undef GPIO_OEN_1_OP_ENABLE_1_MASK +#define GPIO_OEN_1_OP_ENABLE_1_DEFVAL 0x00000000 +#define GPIO_OEN_1_OP_ENABLE_1_SHIFT 0 +#define GPIO_OEN_1_OP_ENABLE_1_MASK 0x03FFFFFFU -/*See Interuppt Status Register for details*/ -#undef LPD_XPPU_CFG_IEN_APER_PERM_DEFVAL -#undef LPD_XPPU_CFG_IEN_APER_PERM_SHIFT -#undef LPD_XPPU_CFG_IEN_APER_PERM_MASK -#define LPD_XPPU_CFG_IEN_APER_PERM_DEFVAL 0x00000000 -#define LPD_XPPU_CFG_IEN_APER_PERM_SHIFT 5 -#define LPD_XPPU_CFG_IEN_APER_PERM_MASK 0x00000020U +/* +* Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW] +*/ +#undef GPIO_MASK_DATA_1_LSW_MASK_1_LSW_DEFVAL +#undef GPIO_MASK_DATA_1_LSW_MASK_1_LSW_SHIFT +#undef GPIO_MASK_DATA_1_LSW_MASK_1_LSW_MASK +#define GPIO_MASK_DATA_1_LSW_MASK_1_LSW_DEFVAL 0x00000000 +#define GPIO_MASK_DATA_1_LSW_MASK_1_LSW_SHIFT 16 +#define GPIO_MASK_DATA_1_LSW_MASK_1_LSW_MASK 0xFFFF0000U -/*See Interuppt Status Register for details*/ -#undef LPD_XPPU_CFG_IEN_MID_PARITY_DEFVAL -#undef LPD_XPPU_CFG_IEN_MID_PARITY_SHIFT -#undef LPD_XPPU_CFG_IEN_MID_PARITY_MASK -#define LPD_XPPU_CFG_IEN_MID_PARITY_DEFVAL 0x00000000 -#define LPD_XPPU_CFG_IEN_MID_PARITY_SHIFT 3 -#define LPD_XPPU_CFG_IEN_MID_PARITY_MASK 0x00000008U +/* +* Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW] +*/ +#undef GPIO_MASK_DATA_1_LSW_DATA_1_LSW_DEFVAL +#undef GPIO_MASK_DATA_1_LSW_DATA_1_LSW_SHIFT +#undef GPIO_MASK_DATA_1_LSW_DATA_1_LSW_MASK +#define GPIO_MASK_DATA_1_LSW_DATA_1_LSW_DEFVAL 0x00000000 +#define GPIO_MASK_DATA_1_LSW_DATA_1_LSW_SHIFT 0 +#define GPIO_MASK_DATA_1_LSW_DATA_1_LSW_MASK 0x0000FFFFU -/*See Interuppt Status Register for details*/ -#undef LPD_XPPU_CFG_IEN_MID_RO_DEFVAL -#undef LPD_XPPU_CFG_IEN_MID_RO_SHIFT -#undef LPD_XPPU_CFG_IEN_MID_RO_MASK -#define LPD_XPPU_CFG_IEN_MID_RO_DEFVAL 0x00000000 -#define LPD_XPPU_CFG_IEN_MID_RO_SHIFT 2 -#define LPD_XPPU_CFG_IEN_MID_RO_MASK 0x00000004U +/* +* Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW] +*/ +#undef GPIO_MASK_DATA_1_LSW_MASK_1_LSW_DEFVAL +#undef GPIO_MASK_DATA_1_LSW_MASK_1_LSW_SHIFT +#undef GPIO_MASK_DATA_1_LSW_MASK_1_LSW_MASK +#define GPIO_MASK_DATA_1_LSW_MASK_1_LSW_DEFVAL 0x00000000 +#define GPIO_MASK_DATA_1_LSW_MASK_1_LSW_SHIFT 16 +#define GPIO_MASK_DATA_1_LSW_MASK_1_LSW_MASK 0xFFFF0000U -/*See Interuppt Status Register for details*/ -#undef LPD_XPPU_CFG_IEN_MID_MISS_DEFVAL -#undef LPD_XPPU_CFG_IEN_MID_MISS_SHIFT -#undef LPD_XPPU_CFG_IEN_MID_MISS_MASK -#define LPD_XPPU_CFG_IEN_MID_MISS_DEFVAL 0x00000000 -#define LPD_XPPU_CFG_IEN_MID_MISS_SHIFT 1 -#define LPD_XPPU_CFG_IEN_MID_MISS_MASK 0x00000002U +/* +* Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW] +*/ +#undef GPIO_MASK_DATA_1_LSW_DATA_1_LSW_DEFVAL +#undef GPIO_MASK_DATA_1_LSW_DATA_1_LSW_SHIFT +#undef GPIO_MASK_DATA_1_LSW_DATA_1_LSW_MASK +#define GPIO_MASK_DATA_1_LSW_DATA_1_LSW_DEFVAL 0x00000000 +#define GPIO_MASK_DATA_1_LSW_DATA_1_LSW_SHIFT 0 +#define GPIO_MASK_DATA_1_LSW_DATA_1_LSW_MASK 0x0000FFFFU +#undef FPD_SLCR_SECURE_SLCR_DPDMA_OFFSET +#define FPD_SLCR_SECURE_SLCR_DPDMA_OFFSET 0XFD690040 +#undef FPD_SLCR_SECURE_SLCR_PCIE_OFFSET +#define FPD_SLCR_SECURE_SLCR_PCIE_OFFSET 0XFD690030 +#undef LPD_SLCR_SECURE_SLCR_USB_OFFSET +#define LPD_SLCR_SECURE_SLCR_USB_OFFSET 0XFF4B0034 +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_OFFSET +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_OFFSET 0XFF240004 +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET 0XFF240000 +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_OFFSET +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_OFFSET 0XFF240004 +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET 0XFF240000 +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET 0XFF240000 +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_OFFSET +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_OFFSET 0XFF240004 +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_OFFSET 0XFF240000 +#undef LPD_SLCR_SECURE_SLCR_ADMA_OFFSET +#define LPD_SLCR_SECURE_SLCR_ADMA_OFFSET 0XFF4B0024 +#undef FPD_SLCR_SECURE_SLCR_GDMA_OFFSET +#define FPD_SLCR_SECURE_SLCR_GDMA_OFFSET 0XFD690050 -/*See Interuppt Status Register for details*/ -#undef LPD_XPPU_CFG_IEN_INV_APB_DEFVAL -#undef LPD_XPPU_CFG_IEN_INV_APB_SHIFT -#undef LPD_XPPU_CFG_IEN_INV_APB_MASK -#define LPD_XPPU_CFG_IEN_INV_APB_DEFVAL 0x00000000 -#define LPD_XPPU_CFG_IEN_INV_APB_SHIFT 0 -#define LPD_XPPU_CFG_IEN_INV_APB_MASK 0x00000001U +/* +* TrustZone classification for DisplayPort DMA +*/ +#undef FPD_SLCR_SECURE_SLCR_DPDMA_TZ_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_DPDMA_TZ_SHIFT +#undef FPD_SLCR_SECURE_SLCR_DPDMA_TZ_MASK +#define FPD_SLCR_SECURE_SLCR_DPDMA_TZ_DEFVAL 0x00000001 +#define FPD_SLCR_SECURE_SLCR_DPDMA_TZ_SHIFT 0 +#define FPD_SLCR_SECURE_SLCR_DPDMA_TZ_MASK 0x00000001U + +/* +* TrustZone classification for DMA Channel 0 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_0_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_0_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_0_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_0_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_0_SHIFT 21 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_0_MASK 0x00200000U + +/* +* TrustZone classification for DMA Channel 1 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_1_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_1_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_1_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_1_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_1_SHIFT 22 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_1_MASK 0x00400000U + +/* +* TrustZone classification for DMA Channel 2 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_2_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_2_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_2_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_2_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_2_SHIFT 23 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_2_MASK 0x00800000U + +/* +* TrustZone classification for DMA Channel 3 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_3_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_3_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_3_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_3_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_3_SHIFT 24 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_3_MASK 0x01000000U + +/* +* TrustZone classification for Ingress Address Translation 0 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_0_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_0_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_0_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_0_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_0_SHIFT 13 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_0_MASK 0x00002000U + +/* +* TrustZone classification for Ingress Address Translation 1 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_1_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_1_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_1_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_1_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_1_SHIFT 14 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_1_MASK 0x00004000U + +/* +* TrustZone classification for Ingress Address Translation 2 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_2_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_2_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_2_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_2_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_2_SHIFT 15 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_2_MASK 0x00008000U + +/* +* TrustZone classification for Ingress Address Translation 3 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_3_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_3_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_3_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_3_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_3_SHIFT 16 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_3_MASK 0x00010000U + +/* +* TrustZone classification for Ingress Address Translation 4 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_4_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_4_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_4_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_4_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_4_SHIFT 17 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_4_MASK 0x00020000U + +/* +* TrustZone classification for Ingress Address Translation 5 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_5_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_5_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_5_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_5_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_5_SHIFT 18 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_5_MASK 0x00040000U + +/* +* TrustZone classification for Ingress Address Translation 6 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_6_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_6_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_6_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_6_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_6_SHIFT 19 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_6_MASK 0x00080000U + +/* +* TrustZone classification for Ingress Address Translation 7 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_7_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_7_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_7_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_7_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_7_SHIFT 20 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_INGR_7_MASK 0x00100000U + +/* +* TrustZone classification for Egress Address Translation 0 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_0_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_0_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_0_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_0_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_0_SHIFT 5 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_0_MASK 0x00000020U + +/* +* TrustZone classification for Egress Address Translation 1 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_1_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_1_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_1_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_1_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_1_SHIFT 6 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_1_MASK 0x00000040U + +/* +* TrustZone classification for Egress Address Translation 2 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_2_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_2_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_2_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_2_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_2_SHIFT 7 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_2_MASK 0x00000080U + +/* +* TrustZone classification for Egress Address Translation 3 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_3_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_3_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_3_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_3_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_3_SHIFT 8 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_3_MASK 0x00000100U + +/* +* TrustZone classification for Egress Address Translation 4 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_4_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_4_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_4_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_4_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_4_SHIFT 9 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_4_MASK 0x00000200U + +/* +* TrustZone classification for Egress Address Translation 5 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_5_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_5_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_5_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_5_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_5_SHIFT 10 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_5_MASK 0x00000400U + +/* +* TrustZone classification for Egress Address Translation 6 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_6_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_6_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_6_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_6_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_6_SHIFT 11 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_6_MASK 0x00000800U + +/* +* TrustZone classification for Egress Address Translation 7 +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_7_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_7_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_7_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_7_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_7_SHIFT 12 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_AT_EGR_7_MASK 0x00001000U + +/* +* TrustZone classification for DMA Registers +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_REGS_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_REGS_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_REGS_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_REGS_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_REGS_SHIFT 4 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_DMA_REGS_MASK 0x00000010U + +/* +* TrustZone classification for MSIx Table +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_TABLE_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_TABLE_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_TABLE_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_TABLE_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_TABLE_SHIFT 2 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_TABLE_MASK 0x00000004U + +/* +* TrustZone classification for MSIx PBA +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_PBA_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_PBA_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_PBA_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_PBA_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_PBA_SHIFT 3 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_MSIX_PBA_MASK 0x00000008U + +/* +* TrustZone classification for ECAM +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_ECAM_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_ECAM_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_ECAM_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_ECAM_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_ECAM_SHIFT 1 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_ECAM_MASK 0x00000002U + +/* +* TrustZone classification for Bridge Common Registers +*/ +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_BRIDGE_REGS_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_BRIDGE_REGS_SHIFT +#undef FPD_SLCR_SECURE_SLCR_PCIE_TZ_BRIDGE_REGS_MASK +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_BRIDGE_REGS_DEFVAL 0x01FFFFFF +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_BRIDGE_REGS_SHIFT 0 +#define FPD_SLCR_SECURE_SLCR_PCIE_TZ_BRIDGE_REGS_MASK 0x00000001U + +/* +* TrustZone Classification for USB3_0 +*/ +#undef LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_0_DEFVAL +#undef LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_0_SHIFT +#undef LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_0_MASK +#define LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_0_DEFVAL 0x00000003 +#define LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_0_SHIFT 0 +#define LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_0_MASK 0x00000001U + +/* +* TrustZone Classification for USB3_1 +*/ +#undef LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_1_DEFVAL +#undef LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_1_SHIFT +#undef LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_1_MASK +#define LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_1_DEFVAL 0x00000003 +#define LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_1_SHIFT 1 +#define LPD_SLCR_SECURE_SLCR_USB_TZ_USB3_1_MASK 0x00000002U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD0_AXI_ARPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD0_AXI_ARPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD0_AXI_ARPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD0_AXI_ARPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD0_AXI_ARPROT_SHIFT 16 +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD0_AXI_ARPROT_MASK 0x00070000U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD1_AXI_ARPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD1_AXI_ARPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD1_AXI_ARPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD1_AXI_ARPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD1_AXI_ARPROT_SHIFT 19 +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_SD1_AXI_ARPROT_MASK 0x00380000U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD0_AXI_AWPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD0_AXI_AWPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD0_AXI_AWPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD0_AXI_AWPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD0_AXI_AWPROT_SHIFT 16 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD0_AXI_AWPROT_MASK 0x00070000U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD1_AXI_AWPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD1_AXI_AWPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD1_AXI_AWPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD1_AXI_AWPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD1_AXI_AWPROT_SHIFT 19 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_SD1_AXI_AWPROT_MASK 0x00380000U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM0_AXI_ARPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM0_AXI_ARPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM0_AXI_ARPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM0_AXI_ARPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM0_AXI_ARPROT_SHIFT 0 +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM0_AXI_ARPROT_MASK 0x00000007U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM1_AXI_ARPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM1_AXI_ARPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM1_AXI_ARPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM1_AXI_ARPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM1_AXI_ARPROT_SHIFT 3 +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM1_AXI_ARPROT_MASK 0x00000038U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM2_AXI_ARPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM2_AXI_ARPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM2_AXI_ARPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM2_AXI_ARPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM2_AXI_ARPROT_SHIFT 6 +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM2_AXI_ARPROT_MASK 0x000001C0U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM3_AXI_ARPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM3_AXI_ARPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM3_AXI_ARPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM3_AXI_ARPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM3_AXI_ARPROT_SHIFT 9 +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_GEM3_AXI_ARPROT_MASK 0x00000E00U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM0_AXI_AWPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM0_AXI_AWPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM0_AXI_AWPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM0_AXI_AWPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM0_AXI_AWPROT_SHIFT 0 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM0_AXI_AWPROT_MASK 0x00000007U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM1_AXI_AWPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM1_AXI_AWPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM1_AXI_AWPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM1_AXI_AWPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM1_AXI_AWPROT_SHIFT 3 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM1_AXI_AWPROT_MASK 0x00000038U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM2_AXI_AWPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM2_AXI_AWPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM2_AXI_AWPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM2_AXI_AWPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM2_AXI_AWPROT_SHIFT 6 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM2_AXI_AWPROT_MASK 0x000001C0U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM3_AXI_AWPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM3_AXI_AWPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM3_AXI_AWPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM3_AXI_AWPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM3_AXI_AWPROT_SHIFT 9 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_GEM3_AXI_AWPROT_MASK 0x00000E00U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_QSPI_AXI_AWPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_QSPI_AXI_AWPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_QSPI_AXI_AWPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_QSPI_AXI_AWPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_QSPI_AXI_AWPROT_SHIFT 25 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_QSPI_AXI_AWPROT_MASK 0x0E000000U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_NAND_AXI_ARPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_NAND_AXI_ARPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_RPRTCN_NAND_AXI_ARPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_NAND_AXI_ARPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_NAND_AXI_ARPROT_SHIFT 22 +#define IOU_SECURE_SLCR_IOU_AXI_RPRTCN_NAND_AXI_ARPROT_MASK 0x01C00000U + +/* +* AXI protection [0] = '0' : Normal access [0] = '1' : Previleged access [ + * 1] = '0' : Secure access [1] = '1' : No secure access [2] = '0' : Data a + * ccess [2] = '1'' : Instruction access +*/ +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_NAND_AXI_AWPROT_DEFVAL +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_NAND_AXI_AWPROT_SHIFT +#undef IOU_SECURE_SLCR_IOU_AXI_WPRTCN_NAND_AXI_AWPROT_MASK +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_NAND_AXI_AWPROT_DEFVAL 0x00000000 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_NAND_AXI_AWPROT_SHIFT 22 +#define IOU_SECURE_SLCR_IOU_AXI_WPRTCN_NAND_AXI_AWPROT_MASK 0x01C00000U + +/* +* TrustZone Classification for ADMA +*/ +#undef LPD_SLCR_SECURE_SLCR_ADMA_TZ_DEFVAL +#undef LPD_SLCR_SECURE_SLCR_ADMA_TZ_SHIFT +#undef LPD_SLCR_SECURE_SLCR_ADMA_TZ_MASK +#define LPD_SLCR_SECURE_SLCR_ADMA_TZ_DEFVAL +#define LPD_SLCR_SECURE_SLCR_ADMA_TZ_SHIFT 0 +#define LPD_SLCR_SECURE_SLCR_ADMA_TZ_MASK 0x000000FFU + +/* +* TrustZone Classification for GDMA +*/ +#undef FPD_SLCR_SECURE_SLCR_GDMA_TZ_DEFVAL +#undef FPD_SLCR_SECURE_SLCR_GDMA_TZ_SHIFT +#undef FPD_SLCR_SECURE_SLCR_GDMA_TZ_MASK +#define FPD_SLCR_SECURE_SLCR_GDMA_TZ_DEFVAL +#define FPD_SLCR_SECURE_SLCR_GDMA_TZ_SHIFT 0 +#define FPD_SLCR_SECURE_SLCR_GDMA_TZ_MASK 0x000000FFU #undef SERDES_PLL_REF_SEL0_OFFSET #define SERDES_PLL_REF_SEL0_OFFSET 0XFD410000 #undef SERDES_PLL_REF_SEL1_OFFSET @@ -25320,8 +32847,6 @@ #define SERDES_L3_TM_DIG_6_OFFSET 0XFD40D06C #undef SERDES_L3_TX_DIG_TM_61_OFFSET #define SERDES_L3_TX_DIG_TM_61_OFFSET 0XFD40C0F4 -#undef SERDES_L3_TXPMA_ST_0_OFFSET -#define SERDES_L3_TXPMA_ST_0_OFFSET 0XFD40CB00 #undef SERDES_L0_TM_AUX_0_OFFSET #define SERDES_L0_TM_AUX_0_OFFSET 0XFD4010CC #undef SERDES_L2_TM_AUX_0_OFFSET @@ -25360,6 +32885,10 @@ #define SERDES_L0_TM_E_ILL8_OFFSET 0XFD401940 #undef SERDES_L0_TM_E_ILL9_OFFSET #define SERDES_L0_TM_E_ILL9_OFFSET 0XFD401944 +#undef SERDES_L0_TM_ILL13_OFFSET +#define SERDES_L0_TM_ILL13_OFFSET 0XFD401994 +#undef SERDES_L1_TM_ILL13_OFFSET +#define SERDES_L1_TM_ILL13_OFFSET 0XFD405994 #undef SERDES_L2_TM_MISC2_OFFSET #define SERDES_L2_TM_MISC2_OFFSET 0XFD40989C #undef SERDES_L2_TM_IQ_ILL1_OFFSET @@ -25386,6 +32915,8 @@ #define SERDES_L2_TM_E_ILL8_OFFSET 0XFD409940 #undef SERDES_L2_TM_E_ILL9_OFFSET #define SERDES_L2_TM_E_ILL9_OFFSET 0XFD409944 +#undef SERDES_L2_TM_ILL13_OFFSET +#define SERDES_L2_TM_ILL13_OFFSET 0XFD409994 #undef SERDES_L3_TM_MISC2_OFFSET #define SERDES_L3_TM_MISC2_OFFSET 0XFD40D89C #undef SERDES_L3_TM_IQ_ILL1_OFFSET @@ -25414,10 +32945,16 @@ #define SERDES_L3_TM_E_ILL8_OFFSET 0XFD40D940 #undef SERDES_L3_TM_E_ILL9_OFFSET #define SERDES_L3_TM_E_ILL9_OFFSET 0XFD40D944 -#undef SERDES_L0_TM_DIG_21_OFFSET -#define SERDES_L0_TM_DIG_21_OFFSET 0XFD4010A8 +#undef SERDES_L3_TM_ILL13_OFFSET +#define SERDES_L3_TM_ILL13_OFFSET 0XFD40D994 #undef SERDES_L0_TM_DIG_10_OFFSET #define SERDES_L0_TM_DIG_10_OFFSET 0XFD40107C +#undef SERDES_L1_TM_DIG_10_OFFSET +#define SERDES_L1_TM_DIG_10_OFFSET 0XFD40507C +#undef SERDES_L2_TM_DIG_10_OFFSET +#define SERDES_L2_TM_DIG_10_OFFSET 0XFD40907C +#undef SERDES_L3_TM_DIG_10_OFFSET +#define SERDES_L3_TM_DIG_10_OFFSET 0XFD40D07C #undef SERDES_L0_TM_RST_DLY_OFFSET #define SERDES_L0_TM_RST_DLY_OFFSET 0XFD4019A4 #undef SERDES_L0_TM_ANA_BYP_15_OFFSET @@ -25442,6 +32979,24 @@ #define SERDES_L3_TM_ANA_BYP_15_OFFSET 0XFD40D038 #undef SERDES_L3_TM_ANA_BYP_12_OFFSET #define SERDES_L3_TM_ANA_BYP_12_OFFSET 0XFD40D02C +#undef SERDES_L0_TM_MISC3_OFFSET +#define SERDES_L0_TM_MISC3_OFFSET 0XFD4019AC +#undef SERDES_L1_TM_MISC3_OFFSET +#define SERDES_L1_TM_MISC3_OFFSET 0XFD4059AC +#undef SERDES_L2_TM_MISC3_OFFSET +#define SERDES_L2_TM_MISC3_OFFSET 0XFD4099AC +#undef SERDES_L3_TM_MISC3_OFFSET +#define SERDES_L3_TM_MISC3_OFFSET 0XFD40D9AC +#undef SERDES_L0_TM_EQ11_OFFSET +#define SERDES_L0_TM_EQ11_OFFSET 0XFD401978 +#undef SERDES_L1_TM_EQ11_OFFSET +#define SERDES_L1_TM_EQ11_OFFSET 0XFD405978 +#undef SERDES_L2_TM_EQ11_OFFSET +#define SERDES_L2_TM_EQ11_OFFSET 0XFD409978 +#undef SERDES_L3_TM_EQ11_OFFSET +#define SERDES_L3_TM_EQ11_OFFSET 0XFD40D978 +#undef SIOU_ECO_0_OFFSET +#define SIOU_ECO_0_OFFSET 0XFD3D001C #undef SERDES_ICM_CFG0_OFFSET #define SERDES_ICM_CFG0_OFFSET 0XFD410010 #undef SERDES_ICM_CFG1_OFFSET @@ -25467,1055 +33022,1511 @@ #undef SERDES_L3_TX_ANA_TM_18_OFFSET #define SERDES_L3_TX_ANA_TM_18_OFFSET 0XFD40C048 -/*PLL0 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - - 4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135 - Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved*/ +/* +* PLL0 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 1 + * 2MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 24MHz, 0x8 - 26MHz, + * 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE + * - 108MHz, 0xF - 125MHz, 0x10 - 135MHz, 0x11 - 150 MHz. 0x12 to 0x1F - R + * eserved +*/ #undef SERDES_PLL_REF_SEL0_PLLREFSEL0_DEFVAL #undef SERDES_PLL_REF_SEL0_PLLREFSEL0_SHIFT #undef SERDES_PLL_REF_SEL0_PLLREFSEL0_MASK -#define SERDES_PLL_REF_SEL0_PLLREFSEL0_DEFVAL 0x0000000D -#define SERDES_PLL_REF_SEL0_PLLREFSEL0_SHIFT 0 -#define SERDES_PLL_REF_SEL0_PLLREFSEL0_MASK 0x0000001FU +#define SERDES_PLL_REF_SEL0_PLLREFSEL0_DEFVAL 0x0000000D +#define SERDES_PLL_REF_SEL0_PLLREFSEL0_SHIFT 0 +#define SERDES_PLL_REF_SEL0_PLLREFSEL0_MASK 0x0000001FU -/*PLL1 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - - 4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135 - Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved*/ +/* +* PLL1 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 1 + * 2MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 24MHz, 0x8 - 26MHz, + * 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE + * - 108MHz, 0xF - 125MHz, 0x10 - 135MHz, 0x11 - 150 MHz. 0x12 to 0x1F - R + * eserved +*/ #undef SERDES_PLL_REF_SEL1_PLLREFSEL1_DEFVAL #undef SERDES_PLL_REF_SEL1_PLLREFSEL1_SHIFT #undef SERDES_PLL_REF_SEL1_PLLREFSEL1_MASK -#define SERDES_PLL_REF_SEL1_PLLREFSEL1_DEFVAL 0x00000008 -#define SERDES_PLL_REF_SEL1_PLLREFSEL1_SHIFT 0 -#define SERDES_PLL_REF_SEL1_PLLREFSEL1_MASK 0x0000001FU +#define SERDES_PLL_REF_SEL1_PLLREFSEL1_DEFVAL 0x00000008 +#define SERDES_PLL_REF_SEL1_PLLREFSEL1_SHIFT 0 +#define SERDES_PLL_REF_SEL1_PLLREFSEL1_MASK 0x0000001FU -/*PLL2 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - - 4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135 - Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved*/ +/* +* PLL2 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 1 + * 2MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 24MHz, 0x8 - 26MHz, + * 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE + * - 108MHz, 0xF - 125MHz, 0x10 - 135MHz, 0x11 - 150 MHz. 0x12 to 0x1F - R + * eserved +*/ #undef SERDES_PLL_REF_SEL2_PLLREFSEL2_DEFVAL #undef SERDES_PLL_REF_SEL2_PLLREFSEL2_SHIFT #undef SERDES_PLL_REF_SEL2_PLLREFSEL2_MASK -#define SERDES_PLL_REF_SEL2_PLLREFSEL2_DEFVAL 0x0000000F -#define SERDES_PLL_REF_SEL2_PLLREFSEL2_SHIFT 0 -#define SERDES_PLL_REF_SEL2_PLLREFSEL2_MASK 0x0000001FU +#define SERDES_PLL_REF_SEL2_PLLREFSEL2_DEFVAL 0x0000000F +#define SERDES_PLL_REF_SEL2_PLLREFSEL2_SHIFT 0 +#define SERDES_PLL_REF_SEL2_PLLREFSEL2_MASK 0x0000001FU -/*PLL3 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - - 4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135 - Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved*/ +/* +* PLL3 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 1 + * 2MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 24MHz, 0x8 - 26MHz, + * 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE + * - 108MHz, 0xF - 125MHz, 0x10 - 135MHz, 0x11 - 150 MHz. 0x12 to 0x1F - R + * eserved +*/ #undef SERDES_PLL_REF_SEL3_PLLREFSEL3_DEFVAL #undef SERDES_PLL_REF_SEL3_PLLREFSEL3_SHIFT #undef SERDES_PLL_REF_SEL3_PLLREFSEL3_MASK -#define SERDES_PLL_REF_SEL3_PLLREFSEL3_DEFVAL 0x0000000E -#define SERDES_PLL_REF_SEL3_PLLREFSEL3_SHIFT 0 -#define SERDES_PLL_REF_SEL3_PLLREFSEL3_MASK 0x0000001FU +#define SERDES_PLL_REF_SEL3_PLLREFSEL3_DEFVAL 0x0000000E +#define SERDES_PLL_REF_SEL3_PLLREFSEL3_SHIFT 0 +#define SERDES_PLL_REF_SEL3_PLLREFSEL3_MASK 0x0000001FU -/*Sel of lane 0 ref clock local mux. Set to 1 to select lane 0 slicer output. Set to 0 to select lane0 ref clock mux output.*/ +/* +* Sel of lane 0 ref clock local mux. Set to 1 to select lane 0 slicer outp + * ut. Set to 0 to select lane0 ref clock mux output. +*/ #undef SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_DEFVAL #undef SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_SHIFT #undef SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_MASK -#define SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_DEFVAL 0x00000080 -#define SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_SHIFT 7 -#define SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_MASK 0x00000080U +#define SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_DEFVAL 0x00000080 +#define SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_SHIFT 7 +#define SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_MASK 0x00000080U -/*Sel of lane 1 ref clock local mux. Set to 1 to select lane 1 slicer output. Set to 0 to select lane1 ref clock mux output.*/ +/* +* Sel of lane 1 ref clock local mux. Set to 1 to select lane 1 slicer outp + * ut. Set to 0 to select lane1 ref clock mux output. +*/ #undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_DEFVAL #undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_SHIFT #undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_MASK -#define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_DEFVAL 0x00000080 -#define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_SHIFT 7 -#define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_MASK 0x00000080U +#define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_DEFVAL 0x00000080 +#define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_SHIFT 7 +#define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_MASK 0x00000080U -/*Bit 3 of lane 1 ref clock mux one hot sel. Set to 1 to select lane 3 slicer output from ref clock network*/ +/* +* Bit 3 of lane 1 ref clock mux one hot sel. Set to 1 to select lane 3 sli + * cer output from ref clock network +*/ #undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_DEFVAL #undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_SHIFT #undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_MASK -#define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_DEFVAL 0x00000080 -#define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_SHIFT 3 -#define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_MASK 0x00000008U +#define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_DEFVAL 0x00000080 +#define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_SHIFT 3 +#define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_MASK 0x00000008U -/*Sel of lane 2 ref clock local mux. Set to 1 to select lane 1 slicer output. Set to 0 to select lane2 ref clock mux output.*/ +/* +* Sel of lane 2 ref clock local mux. Set to 1 to select lane 1 slicer outp + * ut. Set to 0 to select lane2 ref clock mux output. +*/ #undef SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_DEFVAL #undef SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_SHIFT #undef SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_MASK -#define SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_DEFVAL 0x00000080 -#define SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_SHIFT 7 -#define SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_MASK 0x00000080U +#define SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_DEFVAL 0x00000080 +#define SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_SHIFT 7 +#define SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_MASK 0x00000080U -/*Sel of lane 3 ref clock local mux. Set to 1 to select lane 3 slicer output. Set to 0 to select lane3 ref clock mux output.*/ +/* +* Sel of lane 3 ref clock local mux. Set to 1 to select lane 3 slicer outp + * ut. Set to 0 to select lane3 ref clock mux output. +*/ #undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_DEFVAL #undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_SHIFT #undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_MASK -#define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_DEFVAL 0x00000080 -#define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_SHIFT 7 -#define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_MASK 0x00000080U +#define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_DEFVAL 0x00000080 +#define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_SHIFT 7 +#define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_MASK 0x00000080U -/*Bit 1 of lane 3 ref clock mux one hot sel. Set to 1 to select lane 1 slicer output from ref clock network*/ +/* +* Bit 1 of lane 3 ref clock mux one hot sel. Set to 1 to select lane 1 sli + * cer output from ref clock network +*/ #undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_DEFVAL #undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_SHIFT #undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_MASK -#define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_DEFVAL 0x00000080 -#define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_SHIFT 1 -#define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_MASK 0x00000002U +#define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_DEFVAL 0x00000080 +#define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_SHIFT 1 +#define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_MASK 0x00000002U -/*Enable/Disable coarse code satureation limiting logic*/ +/* +* Enable/Disable coarse code satureation limiting logic +*/ #undef SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_DEFVAL #undef SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_SHIFT #undef SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_MASK -#define SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_DEFVAL 0x00000000 -#define SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_SHIFT 4 -#define SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_MASK 0x00000010U +#define SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_DEFVAL 0x00000000 +#define SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_SHIFT 4 +#define SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_MASK 0x00000010U -/*Spread Spectrum No of Steps [7:0]*/ +/* +* Spread Spectrum No of Steps [7:0] +*/ #undef SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL #undef SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT #undef SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK -#define SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL 0x00000000 -#define SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT 0 -#define SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK 0x000000FFU +#define SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL 0x00000000 +#define SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT 0 +#define SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK 0x000000FFU -/*Spread Spectrum No of Steps [10:8]*/ +/* +* Spread Spectrum No of Steps [10:8] +*/ #undef SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL #undef SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT #undef SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK -#define SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL 0x00000000 -#define SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT 0 -#define SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK 0x00000007U +#define SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL 0x00000000 +#define SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT 0 +#define SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK 0x00000007U -/*Spread Spectrum No of Steps [7:0]*/ +/* +* Spread Spectrum No of Steps [7:0] +*/ #undef SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL #undef SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT #undef SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK -#define SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL 0x00000000 -#define SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT 0 -#define SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK 0x000000FFU +#define SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL 0x00000000 +#define SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT 0 +#define SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK 0x000000FFU -/*Spread Spectrum No of Steps [10:8]*/ +/* +* Spread Spectrum No of Steps [10:8] +*/ #undef SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL #undef SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT #undef SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK -#define SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL 0x00000000 -#define SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT 0 -#define SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK 0x00000007U +#define SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL 0x00000000 +#define SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT 0 +#define SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK 0x00000007U -/*Spread Spectrum No of Steps [7:0]*/ +/* +* Spread Spectrum No of Steps [7:0] +*/ #undef SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL #undef SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT #undef SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK -#define SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL 0x00000000 -#define SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT 0 -#define SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK 0x000000FFU +#define SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL 0x00000000 +#define SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT 0 +#define SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK 0x000000FFU -/*Spread Spectrum No of Steps [10:8]*/ +/* +* Spread Spectrum No of Steps [10:8] +*/ #undef SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL #undef SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT #undef SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK -#define SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL 0x00000000 -#define SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT 0 -#define SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK 0x00000007U +#define SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL 0x00000000 +#define SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT 0 +#define SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK 0x00000007U -/*Step Size for Spread Spectrum [7:0]*/ +/* +* Step Size for Spread Spectrum [7:0] +*/ #undef SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL #undef SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT #undef SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK -#define SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL 0x00000000 -#define SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT 0 -#define SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK 0x000000FFU +#define SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL 0x00000000 +#define SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT 0 +#define SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK 0x000000FFU -/*Step Size for Spread Spectrum [15:8]*/ +/* +* Step Size for Spread Spectrum [15:8] +*/ #undef SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL #undef SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT #undef SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK -#define SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL 0x00000000 -#define SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT 0 -#define SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK 0x000000FFU +#define SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL 0x00000000 +#define SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT 0 +#define SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK 0x000000FFU -/*Step Size for Spread Spectrum [23:16]*/ +/* +* Step Size for Spread Spectrum [23:16] +*/ #undef SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL #undef SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT #undef SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK -#define SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL 0x00000000 -#define SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT 0 -#define SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK 0x000000FFU +#define SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL 0x00000000 +#define SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT 0 +#define SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK 0x000000FFU -/*Step Size for Spread Spectrum [25:24]*/ +/* +* Step Size for Spread Spectrum [25:24] +*/ #undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL #undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT #undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK -#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL 0x00000000 -#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT 0 -#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK 0x00000003U +#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL 0x00000000 +#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT 0 +#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK 0x00000003U -/*Enable/Disable test mode force on SS step size*/ +/* +* Enable/Disable test mode force on SS step size +*/ #undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL #undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT #undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK -#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL 0x00000000 -#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT 4 -#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK 0x00000010U +#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL 0x00000000 +#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT 4 +#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK 0x00000010U -/*Enable/Disable test mode force on SS no of steps*/ +/* +* Enable/Disable test mode force on SS no of steps +*/ #undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL #undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT #undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK -#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL 0x00000000 -#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT 5 -#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK 0x00000020U +#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL 0x00000000 +#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT 5 +#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK 0x00000020U -/*Step Size for Spread Spectrum [7:0]*/ +/* +* Step Size for Spread Spectrum [7:0] +*/ #undef SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL #undef SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT #undef SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK -#define SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL 0x00000000 -#define SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT 0 -#define SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK 0x000000FFU +#define SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL 0x00000000 +#define SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT 0 +#define SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK 0x000000FFU -/*Step Size for Spread Spectrum [15:8]*/ +/* +* Step Size for Spread Spectrum [15:8] +*/ #undef SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL #undef SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT #undef SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK -#define SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL 0x00000000 -#define SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT 0 -#define SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK 0x000000FFU +#define SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL 0x00000000 +#define SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT 0 +#define SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK 0x000000FFU -/*Step Size for Spread Spectrum [23:16]*/ +/* +* Step Size for Spread Spectrum [23:16] +*/ #undef SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL #undef SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT #undef SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK -#define SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL 0x00000000 -#define SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT 0 -#define SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK 0x000000FFU +#define SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL 0x00000000 +#define SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT 0 +#define SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK 0x000000FFU -/*Step Size for Spread Spectrum [25:24]*/ +/* +* Step Size for Spread Spectrum [25:24] +*/ #undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL #undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT #undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK -#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL 0x00000000 -#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT 0 -#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK 0x00000003U +#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL 0x00000000 +#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT 0 +#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK 0x00000003U -/*Enable/Disable test mode force on SS step size*/ +/* +* Enable/Disable test mode force on SS step size +*/ #undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL #undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT #undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK -#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL 0x00000000 -#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT 4 -#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK 0x00000010U +#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL 0x00000000 +#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT 4 +#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK 0x00000010U -/*Enable/Disable test mode force on SS no of steps*/ +/* +* Enable/Disable test mode force on SS no of steps +*/ #undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL #undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT #undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK -#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL 0x00000000 -#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT 5 -#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK 0x00000020U +#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL 0x00000000 +#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT 5 +#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK 0x00000020U -/*Step Size for Spread Spectrum [7:0]*/ +/* +* Step Size for Spread Spectrum [7:0] +*/ #undef SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL #undef SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT #undef SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK -#define SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL 0x00000000 -#define SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT 0 -#define SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK 0x000000FFU +#define SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL 0x00000000 +#define SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT 0 +#define SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK 0x000000FFU -/*Step Size for Spread Spectrum [15:8]*/ +/* +* Step Size for Spread Spectrum [15:8] +*/ #undef SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL #undef SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT #undef SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK -#define SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL 0x00000000 -#define SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT 0 -#define SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK 0x000000FFU +#define SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL 0x00000000 +#define SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT 0 +#define SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK 0x000000FFU -/*Step Size for Spread Spectrum [23:16]*/ +/* +* Step Size for Spread Spectrum [23:16] +*/ #undef SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL #undef SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT #undef SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK -#define SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL 0x00000000 -#define SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT 0 -#define SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK 0x000000FFU +#define SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL 0x00000000 +#define SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT 0 +#define SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK 0x000000FFU -/*Step Size for Spread Spectrum [25:24]*/ +/* +* Step Size for Spread Spectrum [25:24] +*/ #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK -#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL 0x00000000 -#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT 0 -#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK 0x00000003U +#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL 0x00000000 +#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT 0 +#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK 0x00000003U -/*Enable/Disable test mode force on SS step size*/ +/* +* Enable/Disable test mode force on SS step size +*/ #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK -#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL 0x00000000 -#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT 4 -#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK 0x00000010U +#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL 0x00000000 +#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT 4 +#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK 0x00000010U -/*Enable/Disable test mode force on SS no of steps*/ +/* +* Enable/Disable test mode force on SS no of steps +*/ #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK -#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL 0x00000000 -#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT 5 -#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK 0x00000020U +#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL 0x00000000 +#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT 5 +#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK 0x00000020U -/*Enable test mode forcing on enable Spread Spectrum*/ +/* +* Enable test mode forcing on enable Spread Spectrum +*/ #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_DEFVAL #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_SHIFT #undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_MASK -#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_DEFVAL 0x00000000 -#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_SHIFT 7 -#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_MASK 0x00000080U +#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_DEFVAL 0x00000000 +#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_SHIFT 7 +#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_MASK 0x00000080U -/*Bypass Descrambler*/ +/* +* Bypass Descrambler +*/ #undef SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_DEFVAL #undef SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_SHIFT #undef SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_MASK -#define SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_DEFVAL 0x00000000 -#define SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_SHIFT 1 -#define SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_MASK 0x00000002U +#define SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_DEFVAL 0x00000000 +#define SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_SHIFT 1 +#define SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_MASK 0x00000002U -/*Enable Bypass for <1> TM_DIG_CTRL_6*/ +/* +* Enable Bypass for <1> TM_DIG_CTRL_6 +*/ #undef SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_DEFVAL #undef SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_SHIFT #undef SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_MASK -#define SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_DEFVAL 0x00000000 -#define SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_SHIFT 0 -#define SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_MASK 0x00000001U +#define SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_DEFVAL 0x00000000 +#define SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_SHIFT 0 +#define SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_MASK 0x00000001U -/*Bypass scrambler signal*/ +/* +* Bypass scrambler signal +*/ #undef SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_DEFVAL #undef SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_SHIFT #undef SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_MASK -#define SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_DEFVAL 0x00000000 -#define SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_SHIFT 1 -#define SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_MASK 0x00000002U +#define SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_DEFVAL 0x00000000 +#define SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_SHIFT 1 +#define SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_MASK 0x00000002U -/*Enable/disable scrambler bypass signal*/ +/* +* Enable/disable scrambler bypass signal +*/ #undef SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_DEFVAL #undef SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_SHIFT #undef SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_MASK -#define SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_DEFVAL 0x00000000 -#define SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_SHIFT 0 -#define SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_MASK 0x00000001U +#define SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_DEFVAL 0x00000000 +#define SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_SHIFT 0 +#define SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_MASK 0x00000001U -/*Enable test mode force on fractional mode enable*/ +/* +* Enable test mode force on fractional mode enable +*/ #undef SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_DEFVAL #undef SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_SHIFT #undef SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_MASK -#define SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_DEFVAL 0x00000000 -#define SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_SHIFT 6 -#define SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_MASK 0x00000040U +#define SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_DEFVAL 0x00000000 +#define SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_SHIFT 6 +#define SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_MASK 0x00000040U -/*Bypass 8b10b decoder*/ +/* +* Bypass 8b10b decoder +*/ #undef SERDES_L3_TM_DIG_6_BYPASS_DECODER_DEFVAL #undef SERDES_L3_TM_DIG_6_BYPASS_DECODER_SHIFT #undef SERDES_L3_TM_DIG_6_BYPASS_DECODER_MASK -#define SERDES_L3_TM_DIG_6_BYPASS_DECODER_DEFVAL 0x00000000 -#define SERDES_L3_TM_DIG_6_BYPASS_DECODER_SHIFT 3 -#define SERDES_L3_TM_DIG_6_BYPASS_DECODER_MASK 0x00000008U +#define SERDES_L3_TM_DIG_6_BYPASS_DECODER_DEFVAL 0x00000000 +#define SERDES_L3_TM_DIG_6_BYPASS_DECODER_SHIFT 3 +#define SERDES_L3_TM_DIG_6_BYPASS_DECODER_MASK 0x00000008U -/*Enable Bypass for <3> TM_DIG_CTRL_6*/ +/* +* Enable Bypass for <3> TM_DIG_CTRL_6 +*/ #undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_DEFVAL #undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_SHIFT #undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_MASK -#define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_DEFVAL 0x00000000 -#define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_SHIFT 2 -#define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_MASK 0x00000004U +#define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_DEFVAL 0x00000000 +#define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_SHIFT 2 +#define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_MASK 0x00000004U -/*Bypass Descrambler*/ +/* +* Bypass Descrambler +*/ #undef SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_DEFVAL #undef SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_SHIFT #undef SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_MASK -#define SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_DEFVAL 0x00000000 -#define SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_SHIFT 1 -#define SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_MASK 0x00000002U +#define SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_DEFVAL 0x00000000 +#define SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_SHIFT 1 +#define SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_MASK 0x00000002U -/*Enable Bypass for <1> TM_DIG_CTRL_6*/ +/* +* Enable Bypass for <1> TM_DIG_CTRL_6 +*/ #undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_DEFVAL #undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_SHIFT #undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_MASK -#define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_DEFVAL 0x00000000 -#define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_SHIFT 0 -#define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_MASK 0x00000001U +#define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_DEFVAL 0x00000000 +#define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_SHIFT 0 +#define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_MASK 0x00000001U -/*Enable/disable encoder bypass signal*/ +/* +* Enable/disable encoder bypass signal +*/ #undef SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_DEFVAL #undef SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_SHIFT #undef SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_MASK -#define SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_DEFVAL 0x00000000 -#define SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_SHIFT 3 -#define SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_MASK 0x00000008U +#define SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_DEFVAL 0x00000000 +#define SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_SHIFT 3 +#define SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_MASK 0x00000008U -/*Bypass scrambler signal*/ +/* +* Bypass scrambler signal +*/ #undef SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_DEFVAL #undef SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_SHIFT #undef SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_MASK -#define SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_DEFVAL 0x00000000 -#define SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_SHIFT 1 -#define SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_MASK 0x00000002U +#define SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_DEFVAL 0x00000000 +#define SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_SHIFT 1 +#define SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_MASK 0x00000002U -/*Enable/disable scrambler bypass signal*/ +/* +* Enable/disable scrambler bypass signal +*/ #undef SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_DEFVAL #undef SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_SHIFT #undef SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_MASK -#define SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_DEFVAL 0x00000000 -#define SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_SHIFT 0 -#define SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_MASK 0x00000001U +#define SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_DEFVAL 0x00000000 +#define SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_SHIFT 0 +#define SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_MASK 0x00000001U -/*PHY Mode: 4'b000 - PCIe, 4'b001 - USB3, 4'b0010 - SATA, 4'b0100 - SGMII, 4'b0101 - DP, 4'b1000 - MPHY*/ -#undef SERDES_L3_TXPMA_ST_0_TX_PHY_MODE_DEFVAL -#undef SERDES_L3_TXPMA_ST_0_TX_PHY_MODE_SHIFT -#undef SERDES_L3_TXPMA_ST_0_TX_PHY_MODE_MASK -#define SERDES_L3_TXPMA_ST_0_TX_PHY_MODE_DEFVAL 0x00000001 -#define SERDES_L3_TXPMA_ST_0_TX_PHY_MODE_SHIFT 4 -#define SERDES_L3_TXPMA_ST_0_TX_PHY_MODE_MASK 0x000000F0U - -/*Spare- not used*/ +/* +* Spare- not used +*/ #undef SERDES_L0_TM_AUX_0_BIT_2_DEFVAL #undef SERDES_L0_TM_AUX_0_BIT_2_SHIFT #undef SERDES_L0_TM_AUX_0_BIT_2_MASK -#define SERDES_L0_TM_AUX_0_BIT_2_DEFVAL 0x00000000 -#define SERDES_L0_TM_AUX_0_BIT_2_SHIFT 5 -#define SERDES_L0_TM_AUX_0_BIT_2_MASK 0x00000020U +#define SERDES_L0_TM_AUX_0_BIT_2_DEFVAL 0x00000000 +#define SERDES_L0_TM_AUX_0_BIT_2_SHIFT 5 +#define SERDES_L0_TM_AUX_0_BIT_2_MASK 0x00000020U -/*Spare- not used*/ +/* +* Spare- not used +*/ #undef SERDES_L2_TM_AUX_0_BIT_2_DEFVAL #undef SERDES_L2_TM_AUX_0_BIT_2_SHIFT #undef SERDES_L2_TM_AUX_0_BIT_2_MASK -#define SERDES_L2_TM_AUX_0_BIT_2_DEFVAL 0x00000000 -#define SERDES_L2_TM_AUX_0_BIT_2_SHIFT 5 -#define SERDES_L2_TM_AUX_0_BIT_2_MASK 0x00000020U +#define SERDES_L2_TM_AUX_0_BIT_2_DEFVAL 0x00000000 +#define SERDES_L2_TM_AUX_0_BIT_2_SHIFT 5 +#define SERDES_L2_TM_AUX_0_BIT_2_MASK 0x00000020U -/*Enable Eye Surf*/ +/* +* Enable Eye Surf +*/ #undef SERDES_L0_TM_DIG_8_EYESURF_ENABLE_DEFVAL #undef SERDES_L0_TM_DIG_8_EYESURF_ENABLE_SHIFT #undef SERDES_L0_TM_DIG_8_EYESURF_ENABLE_MASK -#define SERDES_L0_TM_DIG_8_EYESURF_ENABLE_DEFVAL 0x00000000 -#define SERDES_L0_TM_DIG_8_EYESURF_ENABLE_SHIFT 4 -#define SERDES_L0_TM_DIG_8_EYESURF_ENABLE_MASK 0x00000010U +#define SERDES_L0_TM_DIG_8_EYESURF_ENABLE_DEFVAL 0x00000000 +#define SERDES_L0_TM_DIG_8_EYESURF_ENABLE_SHIFT 4 +#define SERDES_L0_TM_DIG_8_EYESURF_ENABLE_MASK 0x00000010U -/*Enable Eye Surf*/ +/* +* Enable Eye Surf +*/ #undef SERDES_L1_TM_DIG_8_EYESURF_ENABLE_DEFVAL #undef SERDES_L1_TM_DIG_8_EYESURF_ENABLE_SHIFT #undef SERDES_L1_TM_DIG_8_EYESURF_ENABLE_MASK -#define SERDES_L1_TM_DIG_8_EYESURF_ENABLE_DEFVAL 0x00000000 -#define SERDES_L1_TM_DIG_8_EYESURF_ENABLE_SHIFT 4 -#define SERDES_L1_TM_DIG_8_EYESURF_ENABLE_MASK 0x00000010U +#define SERDES_L1_TM_DIG_8_EYESURF_ENABLE_DEFVAL 0x00000000 +#define SERDES_L1_TM_DIG_8_EYESURF_ENABLE_SHIFT 4 +#define SERDES_L1_TM_DIG_8_EYESURF_ENABLE_MASK 0x00000010U -/*Enable Eye Surf*/ +/* +* Enable Eye Surf +*/ #undef SERDES_L2_TM_DIG_8_EYESURF_ENABLE_DEFVAL #undef SERDES_L2_TM_DIG_8_EYESURF_ENABLE_SHIFT #undef SERDES_L2_TM_DIG_8_EYESURF_ENABLE_MASK -#define SERDES_L2_TM_DIG_8_EYESURF_ENABLE_DEFVAL 0x00000000 -#define SERDES_L2_TM_DIG_8_EYESURF_ENABLE_SHIFT 4 -#define SERDES_L2_TM_DIG_8_EYESURF_ENABLE_MASK 0x00000010U +#define SERDES_L2_TM_DIG_8_EYESURF_ENABLE_DEFVAL 0x00000000 +#define SERDES_L2_TM_DIG_8_EYESURF_ENABLE_SHIFT 4 +#define SERDES_L2_TM_DIG_8_EYESURF_ENABLE_MASK 0x00000010U -/*Enable Eye Surf*/ +/* +* Enable Eye Surf +*/ #undef SERDES_L3_TM_DIG_8_EYESURF_ENABLE_DEFVAL #undef SERDES_L3_TM_DIG_8_EYESURF_ENABLE_SHIFT #undef SERDES_L3_TM_DIG_8_EYESURF_ENABLE_MASK -#define SERDES_L3_TM_DIG_8_EYESURF_ENABLE_DEFVAL 0x00000000 -#define SERDES_L3_TM_DIG_8_EYESURF_ENABLE_SHIFT 4 -#define SERDES_L3_TM_DIG_8_EYESURF_ENABLE_MASK 0x00000010U +#define SERDES_L3_TM_DIG_8_EYESURF_ENABLE_DEFVAL 0x00000000 +#define SERDES_L3_TM_DIG_8_EYESURF_ENABLE_SHIFT 4 +#define SERDES_L3_TM_DIG_8_EYESURF_ENABLE_MASK 0x00000010U -/*ILL calib counts BYPASSED with calcode bits*/ +/* +* ILL calib counts BYPASSED with calcode bits +*/ #undef SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL #undef SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT #undef SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK -#define SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL 0x00000000 -#define SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT 7 -#define SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK 0x00000080U +#define SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL 0x00000000 +#define SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT 7 +#define SERDES_L0_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK 0x00000080U -/*IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS*/ +/* +* IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , + * USB3 : SS +*/ #undef SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL #undef SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT #undef SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK -#define SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL 0x00000000 -#define SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT 0 -#define SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK 0x000000FFU +#define SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL 0x00000000 +#define SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT 0 +#define SERDES_L0_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK 0x000000FFU -/*IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2*/ +/* +* IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 +*/ #undef SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL #undef SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT #undef SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK -#define SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL 0x00000000 -#define SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT 0 -#define SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK 0x000000FFU +#define SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL 0x00000000 +#define SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT 0 +#define SERDES_L0_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK 0x000000FFU -/*G1A pll ctr bypass value*/ +/* +* G1A pll ctr bypass value +*/ #undef SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL #undef SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT #undef SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK -#define SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL 0x00000000 -#define SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT 0 -#define SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK 0x000000FFU +#define SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL 0x00000000 +#define SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT 0 +#define SERDES_L0_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK 0x000000FFU -/*E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS*/ +/* +* E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , U + * SB3 : SS +*/ #undef SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL #undef SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT #undef SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK -#define SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL 0x00000000 -#define SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT 0 -#define SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK 0x000000FFU +#define SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL 0x00000000 +#define SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT 0 +#define SERDES_L0_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK 0x000000FFU -/*E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2*/ +/* +* E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 +*/ #undef SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL #undef SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT #undef SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK -#define SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL 0x00000000 -#define SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT 0 -#define SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK 0x000000FFU +#define SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL 0x00000000 +#define SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT 0 +#define SERDES_L0_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK 0x000000FFU -/*IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3*/ +/* +* IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 +*/ #undef SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL #undef SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT #undef SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK -#define SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL 0x00000000 -#define SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT 0 -#define SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK 0x000000FFU +#define SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL 0x00000000 +#define SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT 0 +#define SERDES_L0_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK 0x000000FFU -/*E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3*/ +/* +* E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 +*/ #undef SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL #undef SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT #undef SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK -#define SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL 0x00000000 -#define SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT 0 -#define SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK 0x000000FFU +#define SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL 0x00000000 +#define SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT 0 +#define SERDES_L0_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK 0x000000FFU -/*ILL calibration code change wait time*/ +/* +* ILL calibration code change wait time +*/ #undef SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL #undef SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT #undef SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_MASK -#define SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL 0x00000002 -#define SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT 0 -#define SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_MASK 0x000000FFU +#define SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL 0x00000002 +#define SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT 0 +#define SERDES_L0_TM_ILL8_ILL_CAL_ITER_WAIT_MASK 0x000000FFU -/*IQ ILL polytrim bypass value*/ +/* +* IQ ILL polytrim bypass value +*/ #undef SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL #undef SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT #undef SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK -#define SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL 0x00000000 -#define SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT 0 -#define SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK 0x000000FFU +#define SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL 0x00000000 +#define SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT 0 +#define SERDES_L0_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK 0x000000FFU -/*bypass IQ polytrim*/ +/* +* bypass IQ polytrim +*/ #undef SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL #undef SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT #undef SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK -#define SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL 0x00000000 -#define SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT 0 -#define SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK 0x00000001U +#define SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL 0x00000000 +#define SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT 0 +#define SERDES_L0_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK 0x00000001U -/*E ILL polytrim bypass value*/ +/* +* E ILL polytrim bypass value +*/ #undef SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL #undef SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT #undef SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK -#define SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL 0x00000000 -#define SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT 0 -#define SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK 0x000000FFU +#define SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL 0x00000000 +#define SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT 0 +#define SERDES_L0_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK 0x000000FFU -/*bypass E polytrim*/ +/* +* bypass E polytrim +*/ #undef SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL #undef SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT #undef SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK -#define SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL 0x00000000 -#define SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT 0 -#define SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK 0x00000001U +#define SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL 0x00000000 +#define SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT 0 +#define SERDES_L0_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK 0x00000001U -/*ILL calib counts BYPASSED with calcode bits*/ +/* +* ILL cal idle val refcnt +*/ +#undef SERDES_L0_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_DEFVAL +#undef SERDES_L0_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_SHIFT +#undef SERDES_L0_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_MASK +#define SERDES_L0_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_DEFVAL 0x00000001 +#define SERDES_L0_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_SHIFT 0 +#define SERDES_L0_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_MASK 0x00000007U + +/* +* ILL cal idle val refcnt +*/ +#undef SERDES_L1_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_DEFVAL +#undef SERDES_L1_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_SHIFT +#undef SERDES_L1_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_MASK +#define SERDES_L1_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_DEFVAL 0x00000001 +#define SERDES_L1_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_SHIFT 0 +#define SERDES_L1_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_MASK 0x00000007U + +/* +* ILL calib counts BYPASSED with calcode bits +*/ #undef SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL #undef SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT #undef SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK -#define SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL 0x00000000 -#define SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT 7 -#define SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK 0x00000080U +#define SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL 0x00000000 +#define SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT 7 +#define SERDES_L2_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK 0x00000080U -/*IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS*/ +/* +* IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , + * USB3 : SS +*/ #undef SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL #undef SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT #undef SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK -#define SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL 0x00000000 -#define SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT 0 -#define SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK 0x000000FFU +#define SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL 0x00000000 +#define SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT 0 +#define SERDES_L2_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK 0x000000FFU -/*IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2*/ +/* +* IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 +*/ #undef SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL #undef SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT #undef SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK -#define SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL 0x00000000 -#define SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT 0 -#define SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK 0x000000FFU +#define SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL 0x00000000 +#define SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT 0 +#define SERDES_L2_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK 0x000000FFU -/*G1A pll ctr bypass value*/ +/* +* G1A pll ctr bypass value +*/ #undef SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL #undef SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT #undef SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK -#define SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL 0x00000000 -#define SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT 0 -#define SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK 0x000000FFU +#define SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL 0x00000000 +#define SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT 0 +#define SERDES_L2_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK 0x000000FFU -/*E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS*/ +/* +* E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , U + * SB3 : SS +*/ #undef SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL #undef SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT #undef SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK -#define SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL 0x00000000 -#define SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT 0 -#define SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK 0x000000FFU +#define SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL 0x00000000 +#define SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT 0 +#define SERDES_L2_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK 0x000000FFU -/*E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2*/ +/* +* E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 +*/ #undef SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL #undef SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT #undef SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK -#define SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL 0x00000000 -#define SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT 0 -#define SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK 0x000000FFU +#define SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL 0x00000000 +#define SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT 0 +#define SERDES_L2_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK 0x000000FFU -/*IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3*/ +/* +* IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 +*/ #undef SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL #undef SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT #undef SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK -#define SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL 0x00000000 -#define SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT 0 -#define SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK 0x000000FFU +#define SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL 0x00000000 +#define SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT 0 +#define SERDES_L2_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK 0x000000FFU -/*E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3*/ +/* +* E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 +*/ #undef SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL #undef SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT #undef SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK -#define SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL 0x00000000 -#define SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT 0 -#define SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK 0x000000FFU +#define SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL 0x00000000 +#define SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT 0 +#define SERDES_L2_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK 0x000000FFU -/*ILL calibration code change wait time*/ +/* +* ILL calibration code change wait time +*/ #undef SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL #undef SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT #undef SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_MASK -#define SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL 0x00000002 -#define SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT 0 -#define SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_MASK 0x000000FFU +#define SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL 0x00000002 +#define SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT 0 +#define SERDES_L2_TM_ILL8_ILL_CAL_ITER_WAIT_MASK 0x000000FFU -/*IQ ILL polytrim bypass value*/ +/* +* IQ ILL polytrim bypass value +*/ #undef SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL #undef SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT #undef SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK -#define SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL 0x00000000 -#define SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT 0 -#define SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK 0x000000FFU +#define SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL 0x00000000 +#define SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT 0 +#define SERDES_L2_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK 0x000000FFU -/*bypass IQ polytrim*/ +/* +* bypass IQ polytrim +*/ #undef SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL #undef SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT #undef SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK -#define SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL 0x00000000 -#define SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT 0 -#define SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK 0x00000001U +#define SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL 0x00000000 +#define SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT 0 +#define SERDES_L2_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK 0x00000001U -/*E ILL polytrim bypass value*/ +/* +* E ILL polytrim bypass value +*/ #undef SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL #undef SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT #undef SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK -#define SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL 0x00000000 -#define SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT 0 -#define SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK 0x000000FFU +#define SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL 0x00000000 +#define SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT 0 +#define SERDES_L2_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK 0x000000FFU -/*bypass E polytrim*/ +/* +* bypass E polytrim +*/ #undef SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL #undef SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT #undef SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK -#define SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL 0x00000000 -#define SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT 0 -#define SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK 0x00000001U +#define SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL 0x00000000 +#define SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT 0 +#define SERDES_L2_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK 0x00000001U -/*ILL calib counts BYPASSED with calcode bits*/ +/* +* ILL cal idle val refcnt +*/ +#undef SERDES_L2_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_DEFVAL +#undef SERDES_L2_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_SHIFT +#undef SERDES_L2_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_MASK +#define SERDES_L2_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_DEFVAL 0x00000001 +#define SERDES_L2_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_SHIFT 0 +#define SERDES_L2_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_MASK 0x00000007U + +/* +* ILL calib counts BYPASSED with calcode bits +*/ #undef SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL #undef SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT #undef SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK -#define SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL 0x00000000 -#define SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT 7 -#define SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK 0x00000080U +#define SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_DEFVAL 0x00000000 +#define SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_SHIFT 7 +#define SERDES_L3_TM_MISC2_ILL_CAL_BYPASS_COUNTS_MASK 0x00000080U -/*IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS*/ +/* +* IQ ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , + * USB3 : SS +*/ #undef SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL #undef SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT #undef SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK -#define SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL 0x00000000 -#define SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT 0 -#define SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK 0x000000FFU +#define SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_DEFVAL 0x00000000 +#define SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_SHIFT 0 +#define SERDES_L3_TM_IQ_ILL1_ILL_BYPASS_IQ_CALCODE_F0_MASK 0x000000FFU -/*IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2*/ +/* +* IQ ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 +*/ #undef SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL #undef SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT #undef SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK -#define SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL 0x00000000 -#define SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT 0 -#define SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK 0x000000FFU +#define SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_DEFVAL 0x00000000 +#define SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_SHIFT 0 +#define SERDES_L3_TM_IQ_ILL2_ILL_BYPASS_IQ_CALCODE_F1_MASK 0x000000FFU -/*G1A pll ctr bypass value*/ +/* +* G1A pll ctr bypass value +*/ #undef SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL #undef SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT #undef SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK -#define SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL 0x00000000 -#define SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT 0 -#define SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK 0x000000FFU +#define SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_DEFVAL 0x00000000 +#define SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_SHIFT 0 +#define SERDES_L3_TM_ILL12_G1A_PLL_CTR_BYP_VAL_MASK 0x000000FFU -/*E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , USB3 : SS*/ +/* +* E ILL F0 CALCODE bypass value. MPHY : G1a, PCIE : Gen 1, SATA : Gen1 , U + * SB3 : SS +*/ #undef SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL #undef SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT #undef SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK -#define SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL 0x00000000 -#define SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT 0 -#define SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK 0x000000FFU +#define SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_DEFVAL 0x00000000 +#define SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_SHIFT 0 +#define SERDES_L3_TM_E_ILL1_ILL_BYPASS_E_CALCODE_F0_MASK 0x000000FFU -/*E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2*/ +/* +* E ILL F1 CALCODE bypass value. MPHY : G1b, PCIE : Gen2, SATA: Gen2 +*/ #undef SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL #undef SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT #undef SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK -#define SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL 0x00000000 -#define SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT 0 -#define SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK 0x000000FFU +#define SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_DEFVAL 0x00000000 +#define SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_SHIFT 0 +#define SERDES_L3_TM_E_ILL2_ILL_BYPASS_E_CALCODE_F1_MASK 0x000000FFU -/*G2A_PCIe1 PLL ctr bypass value*/ +/* +* G2A_PCIe1 PLL ctr bypass value +*/ #undef SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_DEFVAL #undef SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_SHIFT #undef SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_MASK -#define SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_DEFVAL 0x00000000 -#define SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_SHIFT 4 -#define SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_MASK 0x000000F0U +#define SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_DEFVAL 0x00000000 +#define SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_SHIFT 4 +#define SERDES_L3_TM_ILL11_G2A_PCIEG1_PLL_CTR_11_8_BYP_VAL_MASK 0x000000F0U -/*IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3*/ +/* +* IQ ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 +*/ #undef SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL #undef SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT #undef SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK -#define SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL 0x00000000 -#define SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT 0 -#define SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK 0x000000FFU +#define SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_DEFVAL 0x00000000 +#define SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_SHIFT 0 +#define SERDES_L3_TM_IQ_ILL3_ILL_BYPASS_IQ_CALCODE_F2_MASK 0x000000FFU -/*E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3*/ +/* +* E ILL F2CALCODE bypass value. MPHY : G2a, SATA : Gen3 +*/ #undef SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL #undef SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT #undef SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK -#define SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL 0x00000000 -#define SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT 0 -#define SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK 0x000000FFU +#define SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_DEFVAL 0x00000000 +#define SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_SHIFT 0 +#define SERDES_L3_TM_E_ILL3_ILL_BYPASS_E_CALCODE_F2_MASK 0x000000FFU -/*ILL calibration code change wait time*/ +/* +* ILL calibration code change wait time +*/ #undef SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL #undef SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT #undef SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_MASK -#define SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL 0x00000002 -#define SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT 0 -#define SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_MASK 0x000000FFU +#define SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_DEFVAL 0x00000002 +#define SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_SHIFT 0 +#define SERDES_L3_TM_ILL8_ILL_CAL_ITER_WAIT_MASK 0x000000FFU -/*IQ ILL polytrim bypass value*/ +/* +* IQ ILL polytrim bypass value +*/ #undef SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL #undef SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT #undef SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK -#define SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL 0x00000000 -#define SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT 0 -#define SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK 0x000000FFU +#define SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_DEFVAL 0x00000000 +#define SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_SHIFT 0 +#define SERDES_L3_TM_IQ_ILL8_ILL_BYPASS_IQ_POLYTRIM_VAL_MASK 0x000000FFU -/*bypass IQ polytrim*/ +/* +* bypass IQ polytrim +*/ #undef SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL #undef SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT #undef SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK -#define SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL 0x00000000 -#define SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT 0 -#define SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK 0x00000001U +#define SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_DEFVAL 0x00000000 +#define SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_SHIFT 0 +#define SERDES_L3_TM_IQ_ILL9_ILL_BYPASS_IQ_POLYTIM_MASK 0x00000001U -/*E ILL polytrim bypass value*/ +/* +* E ILL polytrim bypass value +*/ #undef SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL #undef SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT #undef SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK -#define SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL 0x00000000 -#define SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT 0 -#define SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK 0x000000FFU +#define SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_DEFVAL 0x00000000 +#define SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_SHIFT 0 +#define SERDES_L3_TM_E_ILL8_ILL_BYPASS_E_POLYTRIM_VAL_MASK 0x000000FFU -/*bypass E polytrim*/ +/* +* bypass E polytrim +*/ #undef SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL #undef SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT #undef SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK -#define SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL 0x00000000 -#define SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT 0 -#define SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK 0x00000001U +#define SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_DEFVAL 0x00000000 +#define SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_SHIFT 0 +#define SERDES_L3_TM_E_ILL9_ILL_BYPASS_E_POLYTIM_MASK 0x00000001U -/*pre lock comma count threshold. 2'b 00 : 3, 2'b 01 : 5, 2'b 10 : 10, 2'b 11 : 20*/ -#undef SERDES_L0_TM_DIG_21_COMMA_PRE_LOCK_THRESH_DEFVAL -#undef SERDES_L0_TM_DIG_21_COMMA_PRE_LOCK_THRESH_SHIFT -#undef SERDES_L0_TM_DIG_21_COMMA_PRE_LOCK_THRESH_MASK -#define SERDES_L0_TM_DIG_21_COMMA_PRE_LOCK_THRESH_DEFVAL 0x00000000 -#define SERDES_L0_TM_DIG_21_COMMA_PRE_LOCK_THRESH_SHIFT 0 -#define SERDES_L0_TM_DIG_21_COMMA_PRE_LOCK_THRESH_MASK 0x00000003U +/* +* ILL cal idle val refcnt +*/ +#undef SERDES_L3_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_DEFVAL +#undef SERDES_L3_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_SHIFT +#undef SERDES_L3_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_MASK +#define SERDES_L3_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_DEFVAL 0x00000001 +#define SERDES_L3_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_SHIFT 0 +#define SERDES_L3_TM_ILL13_ILL_CAL_IDLE_VAL_REFCNT_MASK 0x00000007U -/*CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001*/ +/* +* CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001 +*/ #undef SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL #undef SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT #undef SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK -#define SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL 0x00000001 -#define SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT 0 -#define SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK 0x0000000FU +#define SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL 0x00000001 +#define SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT 0 +#define SERDES_L0_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK 0x0000000FU -/*Delay apb reset by specified amount*/ +/* +* CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001 +*/ +#undef SERDES_L1_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL +#undef SERDES_L1_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT +#undef SERDES_L1_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK +#define SERDES_L1_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL 0x00000001 +#define SERDES_L1_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT 0 +#define SERDES_L1_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK 0x0000000FU + +/* +* CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001 +*/ +#undef SERDES_L2_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL +#undef SERDES_L2_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT +#undef SERDES_L2_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK +#define SERDES_L2_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL 0x00000001 +#define SERDES_L2_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT 0 +#define SERDES_L2_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK 0x0000000FU + +/* +* CDR lock wait time. (1-16 us). cdr_lock_wait_time = 4'b xxxx + 4'b 0001 +*/ +#undef SERDES_L3_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL +#undef SERDES_L3_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT +#undef SERDES_L3_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK +#define SERDES_L3_TM_DIG_10_CDR_BIT_LOCK_TIME_DEFVAL 0x00000001 +#define SERDES_L3_TM_DIG_10_CDR_BIT_LOCK_TIME_SHIFT 0 +#define SERDES_L3_TM_DIG_10_CDR_BIT_LOCK_TIME_MASK 0x0000000FU + +/* +* Delay apb reset by specified amount +*/ #undef SERDES_L0_TM_RST_DLY_APB_RST_DLY_DEFVAL #undef SERDES_L0_TM_RST_DLY_APB_RST_DLY_SHIFT #undef SERDES_L0_TM_RST_DLY_APB_RST_DLY_MASK -#define SERDES_L0_TM_RST_DLY_APB_RST_DLY_DEFVAL 0x00000000 -#define SERDES_L0_TM_RST_DLY_APB_RST_DLY_SHIFT 0 -#define SERDES_L0_TM_RST_DLY_APB_RST_DLY_MASK 0x000000FFU +#define SERDES_L0_TM_RST_DLY_APB_RST_DLY_DEFVAL 0x00000000 +#define SERDES_L0_TM_RST_DLY_APB_RST_DLY_SHIFT 0 +#define SERDES_L0_TM_RST_DLY_APB_RST_DLY_MASK 0x000000FFU -/*Enable Bypass for <7> of TM_ANA_BYPS_15*/ +/* +* Enable Bypass for <7> of TM_ANA_BYPS_15 +*/ #undef SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL #undef SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT #undef SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK -#define SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL 0x00000000 -#define SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT 6 -#define SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK 0x00000040U +#define SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL 0x00000000 +#define SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT 6 +#define SERDES_L0_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK 0x00000040U -/*Enable Bypass for <7> of TM_ANA_BYPS_12*/ +/* +* Enable Bypass for <7> of TM_ANA_BYPS_12 +*/ #undef SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL #undef SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT #undef SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK -#define SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL 0x00000000 -#define SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT 6 -#define SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK 0x00000040U +#define SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL 0x00000000 +#define SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT 6 +#define SERDES_L0_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK 0x00000040U -/*Delay apb reset by specified amount*/ +/* +* Delay apb reset by specified amount +*/ #undef SERDES_L1_TM_RST_DLY_APB_RST_DLY_DEFVAL #undef SERDES_L1_TM_RST_DLY_APB_RST_DLY_SHIFT #undef SERDES_L1_TM_RST_DLY_APB_RST_DLY_MASK -#define SERDES_L1_TM_RST_DLY_APB_RST_DLY_DEFVAL 0x00000000 -#define SERDES_L1_TM_RST_DLY_APB_RST_DLY_SHIFT 0 -#define SERDES_L1_TM_RST_DLY_APB_RST_DLY_MASK 0x000000FFU +#define SERDES_L1_TM_RST_DLY_APB_RST_DLY_DEFVAL 0x00000000 +#define SERDES_L1_TM_RST_DLY_APB_RST_DLY_SHIFT 0 +#define SERDES_L1_TM_RST_DLY_APB_RST_DLY_MASK 0x000000FFU -/*Enable Bypass for <7> of TM_ANA_BYPS_15*/ +/* +* Enable Bypass for <7> of TM_ANA_BYPS_15 +*/ #undef SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL #undef SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT #undef SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK -#define SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL 0x00000000 -#define SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT 6 -#define SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK 0x00000040U +#define SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL 0x00000000 +#define SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT 6 +#define SERDES_L1_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK 0x00000040U -/*Enable Bypass for <7> of TM_ANA_BYPS_12*/ +/* +* Enable Bypass for <7> of TM_ANA_BYPS_12 +*/ #undef SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL #undef SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT #undef SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK -#define SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL 0x00000000 -#define SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT 6 -#define SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK 0x00000040U +#define SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL 0x00000000 +#define SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT 6 +#define SERDES_L1_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK 0x00000040U -/*Delay apb reset by specified amount*/ +/* +* Delay apb reset by specified amount +*/ #undef SERDES_L2_TM_RST_DLY_APB_RST_DLY_DEFVAL #undef SERDES_L2_TM_RST_DLY_APB_RST_DLY_SHIFT #undef SERDES_L2_TM_RST_DLY_APB_RST_DLY_MASK -#define SERDES_L2_TM_RST_DLY_APB_RST_DLY_DEFVAL 0x00000000 -#define SERDES_L2_TM_RST_DLY_APB_RST_DLY_SHIFT 0 -#define SERDES_L2_TM_RST_DLY_APB_RST_DLY_MASK 0x000000FFU +#define SERDES_L2_TM_RST_DLY_APB_RST_DLY_DEFVAL 0x00000000 +#define SERDES_L2_TM_RST_DLY_APB_RST_DLY_SHIFT 0 +#define SERDES_L2_TM_RST_DLY_APB_RST_DLY_MASK 0x000000FFU -/*Enable Bypass for <7> of TM_ANA_BYPS_15*/ +/* +* Enable Bypass for <7> of TM_ANA_BYPS_15 +*/ #undef SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL #undef SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT #undef SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK -#define SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL 0x00000000 -#define SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT 6 -#define SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK 0x00000040U +#define SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL 0x00000000 +#define SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT 6 +#define SERDES_L2_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK 0x00000040U -/*Enable Bypass for <7> of TM_ANA_BYPS_12*/ +/* +* Enable Bypass for <7> of TM_ANA_BYPS_12 +*/ #undef SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL #undef SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT #undef SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK -#define SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL 0x00000000 -#define SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT 6 -#define SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK 0x00000040U +#define SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL 0x00000000 +#define SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT 6 +#define SERDES_L2_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK 0x00000040U -/*Delay apb reset by specified amount*/ +/* +* Delay apb reset by specified amount +*/ #undef SERDES_L3_TM_RST_DLY_APB_RST_DLY_DEFVAL #undef SERDES_L3_TM_RST_DLY_APB_RST_DLY_SHIFT #undef SERDES_L3_TM_RST_DLY_APB_RST_DLY_MASK -#define SERDES_L3_TM_RST_DLY_APB_RST_DLY_DEFVAL 0x00000000 -#define SERDES_L3_TM_RST_DLY_APB_RST_DLY_SHIFT 0 -#define SERDES_L3_TM_RST_DLY_APB_RST_DLY_MASK 0x000000FFU +#define SERDES_L3_TM_RST_DLY_APB_RST_DLY_DEFVAL 0x00000000 +#define SERDES_L3_TM_RST_DLY_APB_RST_DLY_SHIFT 0 +#define SERDES_L3_TM_RST_DLY_APB_RST_DLY_MASK 0x000000FFU -/*Enable Bypass for <7> of TM_ANA_BYPS_15*/ +/* +* Enable Bypass for <7> of TM_ANA_BYPS_15 +*/ #undef SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL #undef SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT #undef SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK -#define SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL 0x00000000 -#define SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT 6 -#define SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK 0x00000040U +#define SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_DEFVAL 0x00000000 +#define SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_SHIFT 6 +#define SERDES_L3_TM_ANA_BYP_15_FORCE_UPHY_ENABLE_LOW_LEAKAGE_MASK 0x00000040U -/*Enable Bypass for <7> of TM_ANA_BYPS_12*/ +/* +* Enable Bypass for <7> of TM_ANA_BYPS_12 +*/ #undef SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL #undef SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT #undef SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK -#define SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL 0x00000000 -#define SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT 6 -#define SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK 0x00000040U +#define SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_DEFVAL 0x00000000 +#define SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_SHIFT 6 +#define SERDES_L3_TM_ANA_BYP_12_FORCE_UPHY_PSO_HSRXDIG_MASK 0x00000040U -/*Controls UPHY Lane 0 protocol configuration. 0 - PowerDown, 1 - PCIe .0, 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII0, 6 - Unuse - , 7 - Unused*/ +/* +* CDR fast phase lock control +*/ +#undef SERDES_L0_TM_MISC3_CDR_EN_FPL_DEFVAL +#undef SERDES_L0_TM_MISC3_CDR_EN_FPL_SHIFT +#undef SERDES_L0_TM_MISC3_CDR_EN_FPL_MASK +#define SERDES_L0_TM_MISC3_CDR_EN_FPL_DEFVAL 0x00000003 +#define SERDES_L0_TM_MISC3_CDR_EN_FPL_SHIFT 1 +#define SERDES_L0_TM_MISC3_CDR_EN_FPL_MASK 0x00000002U + +/* +* CDR fast frequency lock control +*/ +#undef SERDES_L0_TM_MISC3_CDR_EN_FFL_DEFVAL +#undef SERDES_L0_TM_MISC3_CDR_EN_FFL_SHIFT +#undef SERDES_L0_TM_MISC3_CDR_EN_FFL_MASK +#define SERDES_L0_TM_MISC3_CDR_EN_FFL_DEFVAL 0x00000003 +#define SERDES_L0_TM_MISC3_CDR_EN_FFL_SHIFT 0 +#define SERDES_L0_TM_MISC3_CDR_EN_FFL_MASK 0x00000001U + +/* +* CDR fast phase lock control +*/ +#undef SERDES_L1_TM_MISC3_CDR_EN_FPL_DEFVAL +#undef SERDES_L1_TM_MISC3_CDR_EN_FPL_SHIFT +#undef SERDES_L1_TM_MISC3_CDR_EN_FPL_MASK +#define SERDES_L1_TM_MISC3_CDR_EN_FPL_DEFVAL 0x00000003 +#define SERDES_L1_TM_MISC3_CDR_EN_FPL_SHIFT 1 +#define SERDES_L1_TM_MISC3_CDR_EN_FPL_MASK 0x00000002U + +/* +* CDR fast frequency lock control +*/ +#undef SERDES_L1_TM_MISC3_CDR_EN_FFL_DEFVAL +#undef SERDES_L1_TM_MISC3_CDR_EN_FFL_SHIFT +#undef SERDES_L1_TM_MISC3_CDR_EN_FFL_MASK +#define SERDES_L1_TM_MISC3_CDR_EN_FFL_DEFVAL 0x00000003 +#define SERDES_L1_TM_MISC3_CDR_EN_FFL_SHIFT 0 +#define SERDES_L1_TM_MISC3_CDR_EN_FFL_MASK 0x00000001U + +/* +* CDR fast phase lock control +*/ +#undef SERDES_L2_TM_MISC3_CDR_EN_FPL_DEFVAL +#undef SERDES_L2_TM_MISC3_CDR_EN_FPL_SHIFT +#undef SERDES_L2_TM_MISC3_CDR_EN_FPL_MASK +#define SERDES_L2_TM_MISC3_CDR_EN_FPL_DEFVAL 0x00000003 +#define SERDES_L2_TM_MISC3_CDR_EN_FPL_SHIFT 1 +#define SERDES_L2_TM_MISC3_CDR_EN_FPL_MASK 0x00000002U + +/* +* CDR fast frequency lock control +*/ +#undef SERDES_L2_TM_MISC3_CDR_EN_FFL_DEFVAL +#undef SERDES_L2_TM_MISC3_CDR_EN_FFL_SHIFT +#undef SERDES_L2_TM_MISC3_CDR_EN_FFL_MASK +#define SERDES_L2_TM_MISC3_CDR_EN_FFL_DEFVAL 0x00000003 +#define SERDES_L2_TM_MISC3_CDR_EN_FFL_SHIFT 0 +#define SERDES_L2_TM_MISC3_CDR_EN_FFL_MASK 0x00000001U + +/* +* CDR fast phase lock control +*/ +#undef SERDES_L3_TM_MISC3_CDR_EN_FPL_DEFVAL +#undef SERDES_L3_TM_MISC3_CDR_EN_FPL_SHIFT +#undef SERDES_L3_TM_MISC3_CDR_EN_FPL_MASK +#define SERDES_L3_TM_MISC3_CDR_EN_FPL_DEFVAL 0x00000003 +#define SERDES_L3_TM_MISC3_CDR_EN_FPL_SHIFT 1 +#define SERDES_L3_TM_MISC3_CDR_EN_FPL_MASK 0x00000002U + +/* +* CDR fast frequency lock control +*/ +#undef SERDES_L3_TM_MISC3_CDR_EN_FFL_DEFVAL +#undef SERDES_L3_TM_MISC3_CDR_EN_FFL_SHIFT +#undef SERDES_L3_TM_MISC3_CDR_EN_FFL_MASK +#define SERDES_L3_TM_MISC3_CDR_EN_FFL_DEFVAL 0x00000003 +#define SERDES_L3_TM_MISC3_CDR_EN_FFL_SHIFT 0 +#define SERDES_L3_TM_MISC3_CDR_EN_FFL_MASK 0x00000001U + +/* +* Force EQ offset correction algo off if not forced on +*/ +#undef SERDES_L0_TM_EQ11_FORCE_EQ_OFFS_OFF_DEFVAL +#undef SERDES_L0_TM_EQ11_FORCE_EQ_OFFS_OFF_SHIFT +#undef SERDES_L0_TM_EQ11_FORCE_EQ_OFFS_OFF_MASK +#define SERDES_L0_TM_EQ11_FORCE_EQ_OFFS_OFF_DEFVAL 0x00000000 +#define SERDES_L0_TM_EQ11_FORCE_EQ_OFFS_OFF_SHIFT 4 +#define SERDES_L0_TM_EQ11_FORCE_EQ_OFFS_OFF_MASK 0x00000010U + +/* +* Force EQ offset correction algo off if not forced on +*/ +#undef SERDES_L1_TM_EQ11_FORCE_EQ_OFFS_OFF_DEFVAL +#undef SERDES_L1_TM_EQ11_FORCE_EQ_OFFS_OFF_SHIFT +#undef SERDES_L1_TM_EQ11_FORCE_EQ_OFFS_OFF_MASK +#define SERDES_L1_TM_EQ11_FORCE_EQ_OFFS_OFF_DEFVAL 0x00000000 +#define SERDES_L1_TM_EQ11_FORCE_EQ_OFFS_OFF_SHIFT 4 +#define SERDES_L1_TM_EQ11_FORCE_EQ_OFFS_OFF_MASK 0x00000010U + +/* +* Force EQ offset correction algo off if not forced on +*/ +#undef SERDES_L2_TM_EQ11_FORCE_EQ_OFFS_OFF_DEFVAL +#undef SERDES_L2_TM_EQ11_FORCE_EQ_OFFS_OFF_SHIFT +#undef SERDES_L2_TM_EQ11_FORCE_EQ_OFFS_OFF_MASK +#define SERDES_L2_TM_EQ11_FORCE_EQ_OFFS_OFF_DEFVAL 0x00000000 +#define SERDES_L2_TM_EQ11_FORCE_EQ_OFFS_OFF_SHIFT 4 +#define SERDES_L2_TM_EQ11_FORCE_EQ_OFFS_OFF_MASK 0x00000010U + +/* +* Force EQ offset correction algo off if not forced on +*/ +#undef SERDES_L3_TM_EQ11_FORCE_EQ_OFFS_OFF_DEFVAL +#undef SERDES_L3_TM_EQ11_FORCE_EQ_OFFS_OFF_SHIFT +#undef SERDES_L3_TM_EQ11_FORCE_EQ_OFFS_OFF_MASK +#define SERDES_L3_TM_EQ11_FORCE_EQ_OFFS_OFF_DEFVAL 0x00000000 +#define SERDES_L3_TM_EQ11_FORCE_EQ_OFFS_OFF_SHIFT 4 +#define SERDES_L3_TM_EQ11_FORCE_EQ_OFFS_OFF_MASK 0x00000010U + +/* +* For future use +*/ +#undef SIOU_ECO_0_FIELD_DEFVAL +#undef SIOU_ECO_0_FIELD_SHIFT +#undef SIOU_ECO_0_FIELD_MASK +#define SIOU_ECO_0_FIELD_DEFVAL +#define SIOU_ECO_0_FIELD_SHIFT 0 +#define SIOU_ECO_0_FIELD_MASK 0xFFFFFFFFU + +/* +* Controls UPHY Lane 0 protocol configuration. 0 - PowerDown, 1 - PCIe .0, + * 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII0, 6 - Unused, 7 - Unused +*/ #undef SERDES_ICM_CFG0_L0_ICM_CFG_DEFVAL #undef SERDES_ICM_CFG0_L0_ICM_CFG_SHIFT #undef SERDES_ICM_CFG0_L0_ICM_CFG_MASK -#define SERDES_ICM_CFG0_L0_ICM_CFG_DEFVAL 0x00000000 -#define SERDES_ICM_CFG0_L0_ICM_CFG_SHIFT 0 -#define SERDES_ICM_CFG0_L0_ICM_CFG_MASK 0x00000007U +#define SERDES_ICM_CFG0_L0_ICM_CFG_DEFVAL 0x00000000 +#define SERDES_ICM_CFG0_L0_ICM_CFG_SHIFT 0 +#define SERDES_ICM_CFG0_L0_ICM_CFG_MASK 0x00000007U -/*Controls UPHY Lane 1 protocol configuration. 0 - PowerDown, 1 - PCIe.1, 2 - Sata1, 3 - USB0, 4 - DP.0, 5 - SGMII1, 6 - Unused - 7 - Unused*/ +/* +* Controls UPHY Lane 1 protocol configuration. 0 - PowerDown, 1 - PCIe.1, + * 2 - Sata1, 3 - USB0, 4 - DP.0, 5 - SGMII1, 6 - Unused, 7 - Unused +*/ #undef SERDES_ICM_CFG0_L1_ICM_CFG_DEFVAL #undef SERDES_ICM_CFG0_L1_ICM_CFG_SHIFT #undef SERDES_ICM_CFG0_L1_ICM_CFG_MASK -#define SERDES_ICM_CFG0_L1_ICM_CFG_DEFVAL 0x00000000 -#define SERDES_ICM_CFG0_L1_ICM_CFG_SHIFT 4 -#define SERDES_ICM_CFG0_L1_ICM_CFG_MASK 0x00000070U +#define SERDES_ICM_CFG0_L1_ICM_CFG_DEFVAL 0x00000000 +#define SERDES_ICM_CFG0_L1_ICM_CFG_SHIFT 4 +#define SERDES_ICM_CFG0_L1_ICM_CFG_MASK 0x00000070U -/*Controls UPHY Lane 2 protocol configuration. 0 - PowerDown, 1 - PCIe.1, 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII2, 6 - Unused - 7 - Unused*/ +/* +* Controls UPHY Lane 2 protocol configuration. 0 - PowerDown, 1 - PCIe.1, + * 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII2, 6 - Unused, 7 - Unused +*/ #undef SERDES_ICM_CFG1_L2_ICM_CFG_DEFVAL #undef SERDES_ICM_CFG1_L2_ICM_CFG_SHIFT #undef SERDES_ICM_CFG1_L2_ICM_CFG_MASK -#define SERDES_ICM_CFG1_L2_ICM_CFG_DEFVAL 0x00000000 -#define SERDES_ICM_CFG1_L2_ICM_CFG_SHIFT 0 -#define SERDES_ICM_CFG1_L2_ICM_CFG_MASK 0x00000007U +#define SERDES_ICM_CFG1_L2_ICM_CFG_DEFVAL 0x00000000 +#define SERDES_ICM_CFG1_L2_ICM_CFG_SHIFT 0 +#define SERDES_ICM_CFG1_L2_ICM_CFG_MASK 0x00000007U -/*Controls UPHY Lane 3 protocol configuration. 0 - PowerDown, 1 - PCIe.3, 2 - Sata1, 3 - USB1, 4 - DP.0, 5 - SGMII3, 6 - Unused - 7 - Unused*/ +/* +* Controls UPHY Lane 3 protocol configuration. 0 - PowerDown, 1 - PCIe.3, + * 2 - Sata1, 3 - USB1, 4 - DP.0, 5 - SGMII3, 6 - Unused, 7 - Unused +*/ #undef SERDES_ICM_CFG1_L3_ICM_CFG_DEFVAL #undef SERDES_ICM_CFG1_L3_ICM_CFG_SHIFT #undef SERDES_ICM_CFG1_L3_ICM_CFG_MASK -#define SERDES_ICM_CFG1_L3_ICM_CFG_DEFVAL 0x00000000 -#define SERDES_ICM_CFG1_L3_ICM_CFG_SHIFT 4 -#define SERDES_ICM_CFG1_L3_ICM_CFG_MASK 0x00000070U +#define SERDES_ICM_CFG1_L3_ICM_CFG_DEFVAL 0x00000000 +#define SERDES_ICM_CFG1_L3_ICM_CFG_SHIFT 4 +#define SERDES_ICM_CFG1_L3_ICM_CFG_MASK 0x00000070U -/*Enable/disable DP post2 path*/ +/* +* Enable/disable DP post2 path +*/ #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_DEFVAL #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_SHIFT #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_MASK -#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_DEFVAL 0x00000000 -#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_SHIFT 5 -#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_MASK 0x00000020U +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_DEFVAL 0x00000000 +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_SHIFT 5 +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_MASK 0x00000020U -/*Override enable/disable of DP post2 path*/ +/* +* Override enable/disable of DP post2 path +*/ #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_DEFVAL #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_SHIFT #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_MASK -#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_DEFVAL 0x00000000 -#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_SHIFT 4 -#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_MASK 0x00000010U +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_DEFVAL 0x00000000 +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_SHIFT 4 +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_MASK 0x00000010U -/*Override enable/disable of DP post1 path*/ +/* +* Override enable/disable of DP post1 path +*/ #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_DEFVAL #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_SHIFT #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_MASK -#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_DEFVAL 0x00000000 -#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_SHIFT 2 -#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_MASK 0x00000004U +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_DEFVAL 0x00000000 +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_SHIFT 2 +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_MASK 0x00000004U -/*Enable/disable DP main path*/ +/* +* Enable/disable DP main path +*/ #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_DEFVAL #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_SHIFT #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_MASK -#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_DEFVAL 0x00000000 -#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_SHIFT 1 -#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_MASK 0x00000002U +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_DEFVAL 0x00000000 +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_SHIFT 1 +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_MASK 0x00000002U -/*Override enable/disable of DP main path*/ +/* +* Override enable/disable of DP main path +*/ #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_DEFVAL #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_SHIFT #undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_MASK -#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_DEFVAL 0x00000000 -#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_SHIFT 0 -#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_MASK 0x00000001U +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_DEFVAL 0x00000000 +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_SHIFT 0 +#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_MASK 0x00000001U -/*Test register force for enabling/disablign TX deemphasis bits <17:0>*/ +/* +* Test register force for enabling/disablign TX deemphasis bits <17:0> +*/ #undef SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_DEFVAL #undef SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT #undef SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK -#define SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_DEFVAL 0x00000000 -#define SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT 0 -#define SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK 0x00000001U +#define SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_DEFVAL 0x00000000 +#define SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT 0 +#define SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK 0x00000001U -/*Test register force for enabling/disablign TX deemphasis bits <17:0>*/ +/* +* Test register force for enabling/disablign TX deemphasis bits <17:0> +*/ #undef SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_DEFVAL #undef SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT #undef SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK -#define SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_DEFVAL 0x00000000 -#define SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT 0 -#define SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK 0x00000001U +#define SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_DEFVAL 0x00000000 +#define SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT 0 +#define SERDES_L3_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK 0x00000001U -/*FPHL FSM accumulate cycles*/ +/* +* FPHL FSM accumulate cycles +*/ #undef SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_DEFVAL #undef SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_SHIFT #undef SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_MASK -#define SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_DEFVAL 0x00000000 -#define SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_SHIFT 5 -#define SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_MASK 0x000000E0U +#define SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_DEFVAL 0x00000000 +#define SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_SHIFT 5 +#define SERDES_L3_TM_CDR5_FPHL_FSM_ACC_CYCLES_MASK 0x000000E0U -/*FFL Phase0 int gain aka 2ol SD update rate*/ +/* +* FFL Phase0 int gain aka 2ol SD update rate +*/ #undef SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_DEFVAL #undef SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_SHIFT #undef SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_MASK -#define SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_DEFVAL 0x00000000 -#define SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_SHIFT 0 -#define SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_MASK 0x0000001FU +#define SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_DEFVAL 0x00000000 +#define SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_SHIFT 0 +#define SERDES_L3_TM_CDR5_FFL_PH0_INT_GAIN_MASK 0x0000001FU -/*FFL Phase0 prop gain aka 1ol SD update rate*/ +/* +* FFL Phase0 prop gain aka 1ol SD update rate +*/ #undef SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_DEFVAL #undef SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_SHIFT #undef SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_MASK -#define SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_DEFVAL 0x00000000 -#define SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_SHIFT 0 -#define SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_MASK 0x0000001FU +#define SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_DEFVAL 0x00000000 +#define SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_SHIFT 0 +#define SERDES_L3_TM_CDR16_FFL_PH0_PROP_GAIN_MASK 0x0000001FU -/*EQ stg 2 controls BYPASSED*/ +/* +* EQ stg 2 controls BYPASSED +*/ #undef SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_DEFVAL #undef SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_SHIFT #undef SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_MASK -#define SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_DEFVAL 0x00000000 -#define SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_SHIFT 5 -#define SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_MASK 0x00000020U +#define SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_DEFVAL 0x00000000 +#define SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_SHIFT 5 +#define SERDES_L3_TM_EQ0_EQ_STG2_CTRL_BYP_MASK 0x00000020U -/*EQ STG2 RL PROG*/ +/* +* EQ STG2 RL PROG +*/ #undef SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_DEFVAL #undef SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_SHIFT #undef SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_MASK -#define SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_DEFVAL 0x00000000 -#define SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_SHIFT 0 -#define SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_MASK 0x00000003U +#define SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_DEFVAL 0x00000000 +#define SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_SHIFT 0 +#define SERDES_L3_TM_EQ1_EQ_STG2_RL_PROG_MASK 0x00000003U -/*EQ stg 2 preamp mode val*/ +/* +* EQ stg 2 preamp mode val +*/ #undef SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_DEFVAL #undef SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_SHIFT #undef SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_MASK -#define SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_DEFVAL 0x00000000 -#define SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_SHIFT 2 -#define SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_MASK 0x00000004U +#define SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_DEFVAL 0x00000000 +#define SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_SHIFT 2 +#define SERDES_L3_TM_EQ1_EQ_STG2_PREAMP_MODE_VAL_MASK 0x00000004U -/*Margining factor value*/ +/* +* Margining factor value +*/ #undef SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_DEFVAL #undef SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_SHIFT #undef SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_MASK -#define SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_DEFVAL 0x00000000 -#define SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_SHIFT 0 -#define SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_MASK 0x0000001FU +#define SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_DEFVAL 0x00000000 +#define SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_SHIFT 0 +#define SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_MASK 0x0000001FU -/*pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-emphasis, Others: reserved*/ +/* +* pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-em + * phasis, Others: reserved +*/ #undef SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_DEFVAL #undef SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT #undef SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK -#define SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_DEFVAL 0x00000002 -#define SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT 0 -#define SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK 0x000000FFU +#define SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_DEFVAL 0x00000002 +#define SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT 0 +#define SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK 0x000000FFU -/*pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-emphasis, Others: reserved*/ +/* +* pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-em + * phasis, Others: reserved +*/ #undef SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_DEFVAL #undef SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT #undef SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK -#define SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_DEFVAL 0x00000002 -#define SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT 0 -#define SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK 0x000000FFU +#define SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_DEFVAL 0x00000002 +#define SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT 0 +#define SERDES_L3_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK 0x000000FFU #undef CRL_APB_RST_LPD_TOP_OFFSET #define CRL_APB_RST_LPD_TOP_OFFSET 0XFF5E023C -#undef USB3_0_FPD_POWER_PRSNT_OFFSET -#define USB3_0_FPD_POWER_PRSNT_OFFSET 0XFF9D0080 -#undef USB3_0_FPD_PIPE_CLK_OFFSET -#define USB3_0_FPD_PIPE_CLK_OFFSET 0XFF9D007C #undef CRL_APB_RST_LPD_TOP_OFFSET #define CRL_APB_RST_LPD_TOP_OFFSET 0XFF5E023C #undef CRL_APB_RST_LPD_IOU0_OFFSET @@ -26536,6 +34547,10 @@ #define USB3_0_XHCI_GUSB2PHYCFG_OFFSET 0XFE20C200 #undef USB3_0_XHCI_GFLADJ_OFFSET #define USB3_0_XHCI_GFLADJ_OFFSET 0XFE20C630 +#undef USB3_0_XHCI_GUCTL1_OFFSET +#define USB3_0_XHCI_GUCTL1_OFFSET 0XFE20C11C +#undef USB3_0_XHCI_GUCTL_OFFSET +#define USB3_0_XHCI_GUCTL_OFFSET 0XFE20C12C #undef PCIE_ATTRIB_ATTR_25_OFFSET #define PCIE_ATTRIB_ATTR_25_OFFSET 0XFD480064 #undef PCIE_ATTRIB_ATTR_7_OFFSET @@ -26626,6 +34641,8 @@ #define PCIE_ATTRIB_ATTR_35_OFFSET 0XFD48008C #undef CRF_APB_RST_FPD_TOP_OFFSET #define CRF_APB_RST_FPD_TOP_OFFSET 0XFD1A0100 +#undef GPIO_MASK_DATA_1_LSW_OFFSET +#define GPIO_MASK_DATA_1_LSW_OFFSET 0XFF0A0008 #undef SATA_AHCI_VENDOR_PP2C_OFFSET #define SATA_AHCI_VENDOR_PP2C_OFFSET 0XFD0C00AC #undef SATA_AHCI_VENDOR_PP3C_OFFSET @@ -26635,1015 +34652,1462 @@ #undef SATA_AHCI_VENDOR_PP5C_OFFSET #define SATA_AHCI_VENDOR_PP5C_OFFSET 0XFD0C00B8 -/*USB 0 reset for control registers*/ +/* +* USB 0 reset for control registers +*/ #undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL #undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT #undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK -#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL 0x00188FDF -#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT 10 -#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK 0x00000400U +#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT 10 +#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK 0x00000400U -/*This bit is used to choose between PIPE power present and 1'b1*/ -#undef USB3_0_FPD_POWER_PRSNT_OPTION_DEFVAL -#undef USB3_0_FPD_POWER_PRSNT_OPTION_SHIFT -#undef USB3_0_FPD_POWER_PRSNT_OPTION_MASK -#define USB3_0_FPD_POWER_PRSNT_OPTION_DEFVAL -#define USB3_0_FPD_POWER_PRSNT_OPTION_SHIFT 0 -#define USB3_0_FPD_POWER_PRSNT_OPTION_MASK 0x00000001U - -/*This bit is used to choose between PIPE clock coming from SerDes and the suspend clk*/ -#undef USB3_0_FPD_PIPE_CLK_OPTION_DEFVAL -#undef USB3_0_FPD_PIPE_CLK_OPTION_SHIFT -#undef USB3_0_FPD_PIPE_CLK_OPTION_MASK -#define USB3_0_FPD_PIPE_CLK_OPTION_DEFVAL -#define USB3_0_FPD_PIPE_CLK_OPTION_SHIFT 0 -#define USB3_0_FPD_PIPE_CLK_OPTION_MASK 0x00000001U - -/*USB 0 sleep circuit reset*/ +/* +* USB 0 sleep circuit reset +*/ #undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL #undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT #undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK -#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL 0x00188FDF -#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT 8 -#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK 0x00000100U +#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT 8 +#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK 0x00000100U -/*USB 0 reset*/ +/* +* USB 0 reset +*/ #undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL #undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT #undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK -#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL 0x00188FDF -#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT 6 -#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK 0x00000040U +#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT 6 +#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK 0x00000040U -/*GEM 3 reset*/ +/* +* GEM 3 reset +*/ #undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL #undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT #undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK -#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL 0x0000000F -#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT 3 -#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK 0x00000008U +#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL 0x0000000F +#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT 3 +#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK 0x00000008U -/*Sata PM clock control select*/ +/* +* Sata PM clock control select +*/ #undef SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_DEFVAL #undef SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_SHIFT #undef SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_MASK -#define SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_DEFVAL -#define SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_SHIFT 0 -#define SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_MASK 0x00000003U +#define SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_DEFVAL +#define SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_SHIFT 0 +#define SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_MASK 0x00000003U -/*Sata block level reset*/ +/* +* Sata block level reset +*/ #undef CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL #undef CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT #undef CRF_APB_RST_FPD_TOP_SATA_RESET_MASK -#define CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL 0x000F9FFE -#define CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT 1 -#define CRF_APB_RST_FPD_TOP_SATA_RESET_MASK 0x00000002U +#define CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT 1 +#define CRF_APB_RST_FPD_TOP_SATA_RESET_MASK 0x00000002U -/*PCIE config reset*/ +/* +* PCIE config reset +*/ #undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL #undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT #undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK -#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL 0x000F9FFE -#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT 19 -#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK 0x00080000U +#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT 19 +#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK 0x00080000U -/*PCIE bridge block level reset (AXI interface)*/ +/* +* PCIE bridge block level reset (AXI interface) +*/ #undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL #undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT #undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK -#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL 0x000F9FFE -#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT 18 -#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK 0x00040000U +#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT 18 +#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK 0x00040000U -/*Display Port block level reset (includes DPDMA)*/ +/* +* Display Port block level reset (includes DPDMA) +*/ #undef CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL #undef CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT #undef CRF_APB_RST_FPD_TOP_DP_RESET_MASK -#define CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL 0x000F9FFE -#define CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT 16 -#define CRF_APB_RST_FPD_TOP_DP_RESET_MASK 0x00010000U +#define CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT 16 +#define CRF_APB_RST_FPD_TOP_DP_RESET_MASK 0x00010000U -/*Set to '1' to hold the GT in reset. Clear to release.*/ +/* +* Set to '1' to hold the GT in reset. Clear to release. +*/ #undef DP_DP_PHY_RESET_GT_RESET_DEFVAL #undef DP_DP_PHY_RESET_GT_RESET_SHIFT #undef DP_DP_PHY_RESET_GT_RESET_MASK -#define DP_DP_PHY_RESET_GT_RESET_DEFVAL 0x00010003 -#define DP_DP_PHY_RESET_GT_RESET_SHIFT 1 -#define DP_DP_PHY_RESET_GT_RESET_MASK 0x00000002U +#define DP_DP_PHY_RESET_GT_RESET_DEFVAL 0x00010003 +#define DP_DP_PHY_RESET_GT_RESET_SHIFT 1 +#define DP_DP_PHY_RESET_GT_RESET_MASK 0x00000002U -/*Two bits per lane. When set to 11, moves the GT to power down mode. When set to 00, GT will be in active state. bits [1:0] - - ane0 Bits [3:2] - lane 1*/ +/* +* Two bits per lane. When set to 11, moves the GT to power down mode. When + * set to 00, GT will be in active state. bits [1:0] - lane0 Bits [3:2] - + * lane 1 +*/ #undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_DEFVAL #undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT #undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK -#define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_DEFVAL 0x00000000 -#define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT 0 -#define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK 0x0000000FU +#define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_DEFVAL 0x00000000 +#define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT 0 +#define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK 0x0000000FU -/*USB 2.0 Turnaround Time (USBTrdTim) Sets the turnaround time in PHY clocks. Specifies the response time for a MAC request to - he Packet FIFO Controller (PFC) to fetch data from the DFIFO (SPRAM). The following are the required values for the minimum S - C bus frequency of 60 MHz. USB turnaround time is a critical certification criteria when using long cables and five hub level - . The required values for this field: - 4'h5: When the MAC interface is 16-bit UTMI+. - 4'h9: When the MAC interface is 8-bit - UTMI+/ULPI. If SoC bus clock is less than 60 MHz, and USB turnaround time is not critical, this field can be set to a larger - alue. Note: This field is valid only in device mode.*/ +/* +* USB 2.0 Turnaround Time (USBTrdTim) Sets the turnaround time in PHY cloc + * ks. Specifies the response time for a MAC request to the Packet FIFO Con + * troller (PFC) to fetch data from the DFIFO (SPRAM). The following are th + * e required values for the minimum SoC bus frequency of 60 MHz. USB turna + * round time is a critical certification criteria when using long cables a + * nd five hub levels. The required values for this field: - 4'h5: When the + * MAC interface is 16-bit UTMI+. - 4'h9: When the MAC interface is 8-bit + * UTMI+/ULPI. If SoC bus clock is less than 60 MHz, and USB turnaround tim + * e is not critical, this field can be set to a larger value. Note: This f + * ield is valid only in device mode. +*/ #undef USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_DEFVAL #undef USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_SHIFT #undef USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_MASK -#define USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_DEFVAL 0x00000000 -#define USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_SHIFT 10 -#define USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_MASK 0x00003C00U +#define USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_DEFVAL 0x00000000 +#define USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_SHIFT 10 +#define USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_MASK 0x00003C00U -/*Transceiver Delay: Enables a delay between the assertion of the UTMI/ULPI Transceiver Select signal (for HS) and the assertio - of the TxValid signal during a HS Chirp. When this bit is set to 1, a delay (of approximately 2.5 us) is introduced from the - time when the Transceiver Select is set to 2'b00 (HS) to the time the TxValid is driven to 0 for sending the chirp-K. This de - ay is required for some UTMI/ULPI PHYs. Note: - If you enable the hibernation feature when the device core comes out of power - off, you must re-initialize this bit with the appropriate value because the core does not save and restore this bit value dur - ng hibernation. - This bit is valid only in device mode.*/ +/* +* Transceiver Delay: Enables a delay between the assertion of the UTMI/ULP + * I Transceiver Select signal (for HS) and the assertion of the TxValid si + * gnal during a HS Chirp. When this bit is set to 1, a delay (of approxima + * tely 2.5 us) is introduced from the time when the Transceiver Select is + * set to 2'b00 (HS) to the time the TxValid is driven to 0 for sending the + * chirp-K. This delay is required for some UTMI/ULPI PHYs. Note: - If you + * enable the hibernation feature when the device core comes out of power- + * off, you must re-initialize this bit with the appropriate value because + * the core does not save and restore this bit value during hibernation. - + * This bit is valid only in device mode. +*/ #undef USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_DEFVAL #undef USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_SHIFT #undef USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_MASK -#define USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_DEFVAL 0x00000000 -#define USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_SHIFT 9 -#define USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_MASK 0x00000200U +#define USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_DEFVAL 0x00000000 +#define USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_SHIFT 9 +#define USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_MASK 0x00000200U -/*Enable utmi_sleep_n and utmi_l1_suspend_n (EnblSlpM) The application uses this bit to control utmi_sleep_n and utmi_l1_suspen - _n assertion to the PHY in the L1 state. - 1'b0: utmi_sleep_n and utmi_l1_suspend_n assertion from the core is not transferre - to the external PHY. - 1'b1: utmi_sleep_n and utmi_l1_suspend_n assertion from the core is transferred to the external PHY. - ote: This bit must be set high for Port0 if PHY is used. Note: In Device mode - Before issuing any device endpoint command wh - n operating in 2.0 speeds, disable this bit and enable it after the command completes. Without disabling this bit, if a comma - d is issued when the device is in L1 state and if mac2_clk (utmi_clk/ulpi_clk) is gated off, the command will not get complet - d.*/ +/* +* Enable utmi_sleep_n and utmi_l1_suspend_n (EnblSlpM) The application use + * s this bit to control utmi_sleep_n and utmi_l1_suspend_n assertion to th + * e PHY in the L1 state. - 1'b0: utmi_sleep_n and utmi_l1_suspend_n assert + * ion from the core is not transferred to the external PHY. - 1'b1: utmi_s + * leep_n and utmi_l1_suspend_n assertion from the core is transferred to t + * he external PHY. Note: This bit must be set high for Port0 if PHY is use + * d. Note: In Device mode - Before issuing any device endpoint command whe + * n operating in 2.0 speeds, disable this bit and enable it after the comm + * and completes. Without disabling this bit, if a command is issued when t + * he device is in L1 state and if mac2_clk (utmi_clk/ulpi_clk) is gated of + * f, the command will not get completed. +*/ #undef USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_DEFVAL #undef USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_SHIFT #undef USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_MASK -#define USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_DEFVAL 0x00000000 -#define USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_SHIFT 8 -#define USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_MASK 0x00000100U +#define USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_DEFVAL 0x00000000 +#define USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_SHIFT 8 +#define USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_MASK 0x00000100U -/*USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial Transceiver Select The application uses this bit to select a high-speed P - Y or a full-speed transceiver. - 1'b0: USB 2.0 high-speed UTMI+ or ULPI PHY. This bit is always 0, with Write Only access. - - 'b1: USB 1.1 full-speed serial transceiver. This bit is always 1, with Write Only access. If both interface types are selecte - in coreConsultant (that is, parameters' values are not zero), the application uses this bit to select the active interface i - active, with Read-Write bit access. Note: USB 1.1 full-serial transceiver is not supported. This bit always reads as 1'b0.*/ +/* +* USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial Transceiver Select T + * he application uses this bit to select a high-speed PHY or a full-speed + * transceiver. - 1'b0: USB 2.0 high-speed UTMI+ or ULPI PHY. This bit is a + * lways 0, with Write Only access. - 1'b1: USB 1.1 full-speed serial trans + * ceiver. This bit is always 1, with Write Only access. If both interface + * types are selected in coreConsultant (that is, parameters' values are no + * t zero), the application uses this bit to select the active interface is + * active, with Read-Write bit access. Note: USB 1.1 full-serial transceiv + * er is not supported. This bit always reads as 1'b0. +*/ #undef USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_DEFVAL #undef USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_SHIFT #undef USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_MASK -#define USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_DEFVAL 0x00000000 -#define USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_SHIFT 7 -#define USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_MASK 0x00000080U +#define USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_DEFVAL 0x00000000 +#define USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_SHIFT 7 +#define USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_MASK 0x00000080U -/*Full-Speed Serial Interface Select (FSIntf) The application uses this bit to select a unidirectional or bidirectional USB 1.1 - full-speed serial transceiver interface. - 1'b0: 6-pin unidirectional full-speed serial interface. This bit is set to 0 with - ead Only access. - 1'b1: 3-pin bidirectional full-speed serial interface. This bit is set to 0 with Read Only access. Note: U - B 1.1 full-speed serial interface is not supported. This bit always reads as 1'b0.*/ +/* +* Suspend USB2.0 HS/FS/LS PHY (SusPHY) When set, USB2.0 PHY enters Suspend + * mode if Suspend conditions are valid. For DRD/OTG configurations, it is + * recommended that this bit is set to 0 during coreConsultant configurati + * on. If it is set to 1, then the application must clear this bit after po + * wer-on reset. Application needs to set it to 1 after the core initializa + * tion completes. For all other configurations, this bit can be set to 1 d + * uring core configuration. Note: - In host mode, on reset, this bit is se + * t to 1. Software can override this bit after reset. - In device mode, be + * fore issuing any device endpoint command when operating in 2.0 speeds, d + * isable this bit and enable it after the command completes. If you issue + * a command without disabling this bit when the device is in L2 state and + * if mac2_clk (utmi_clk/ulpi_clk) is gated off, the command will not get c + * ompleted. +*/ +#undef USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_DEFVAL +#undef USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_SHIFT +#undef USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_MASK +#define USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_DEFVAL 0x00000000 +#define USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_SHIFT 6 +#define USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_MASK 0x00000040U + +/* +* Full-Speed Serial Interface Select (FSIntf) The application uses this bi + * t to select a unidirectional or bidirectional USB 1.1 full-speed serial + * transceiver interface. - 1'b0: 6-pin unidirectional full-speed serial in + * terface. This bit is set to 0 with Read Only access. - 1'b1: 3-pin bidir + * ectional full-speed serial interface. This bit is set to 0 with Read Onl + * y access. Note: USB 1.1 full-speed serial interface is not supported. Th + * is bit always reads as 1'b0. +*/ #undef USB3_0_XHCI_GUSB2PHYCFG_FSINTF_DEFVAL #undef USB3_0_XHCI_GUSB2PHYCFG_FSINTF_SHIFT #undef USB3_0_XHCI_GUSB2PHYCFG_FSINTF_MASK -#define USB3_0_XHCI_GUSB2PHYCFG_FSINTF_DEFVAL 0x00000000 -#define USB3_0_XHCI_GUSB2PHYCFG_FSINTF_SHIFT 5 -#define USB3_0_XHCI_GUSB2PHYCFG_FSINTF_MASK 0x00000020U +#define USB3_0_XHCI_GUSB2PHYCFG_FSINTF_DEFVAL 0x00000000 +#define USB3_0_XHCI_GUSB2PHYCFG_FSINTF_SHIFT 5 +#define USB3_0_XHCI_GUSB2PHYCFG_FSINTF_MASK 0x00000020U -/*ULPI or UTMI+ Select (ULPI_UTMI_Sel) The application uses this bit to select a UTMI+ or ULPI Interface. - 1'b0: UTMI+ Interfa - e - 1'b1: ULPI Interface This bit is writable only if UTMI+ and ULPI is specified for High-Speed PHY Interface(s) in coreCons - ltant configuration (DWC_USB3_HSPHY_INTERFACE = 3). Otherwise, this bit is read-only and the value depends on the interface s - lected through DWC_USB3_HSPHY_INTERFACE.*/ +/* +* ULPI or UTMI+ Select (ULPI_UTMI_Sel) The application uses this bit to se + * lect a UTMI+ or ULPI Interface. - 1'b0: UTMI+ Interface - 1'b1: ULPI Int + * erface This bit is writable only if UTMI+ and ULPI is specified for High + * -Speed PHY Interface(s) in coreConsultant configuration (DWC_USB3_HSPHY_ + * INTERFACE = 3). Otherwise, this bit is read-only and the value depends o + * n the interface selected through DWC_USB3_HSPHY_INTERFACE. +*/ #undef USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_DEFVAL #undef USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_SHIFT #undef USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_MASK -#define USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_DEFVAL 0x00000000 -#define USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_SHIFT 4 -#define USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_MASK 0x00000010U +#define USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_DEFVAL 0x00000000 +#define USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_SHIFT 4 +#define USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_MASK 0x00000010U -/*PHY Interface (PHYIf) If UTMI+ is selected, the application uses this bit to configure the core to support a UTMI+ PHY with a - 8- or 16-bit interface. - 1'b0: 8 bits - 1'b1: 16 bits ULPI Mode: 1'b0 Note: - All the enabled 2.0 ports must have the same - lock frequency as Port0 clock frequency (utmi_clk[0]). - The UTMI 8-bit and 16-bit modes cannot be used together for differen - ports at the same time (that is, all the ports must be in 8-bit mode, or all of them must be in 16-bit mode, at a time). - I - any of the USB 2.0 ports is selected as ULPI port for operation, then all the USB 2.0 ports must be operating at 60 MHz.*/ +/* +* PHY Interface (PHYIf) If UTMI+ is selected, the application uses this bi + * t to configure the core to support a UTMI+ PHY with an 8- or 16-bit inte + * rface. - 1'b0: 8 bits - 1'b1: 16 bits ULPI Mode: 1'b0 Note: - All the en + * abled 2.0 ports must have the same clock frequency as Port0 clock freque + * ncy (utmi_clk[0]). - The UTMI 8-bit and 16-bit modes cannot be used toge + * ther for different ports at the same time (that is, all the ports must b + * e in 8-bit mode, or all of them must be in 16-bit mode, at a time). - If + * any of the USB 2.0 ports is selected as ULPI port for operation, then a + * ll the USB 2.0 ports must be operating at 60 MHz. +*/ #undef USB3_0_XHCI_GUSB2PHYCFG_PHYIF_DEFVAL #undef USB3_0_XHCI_GUSB2PHYCFG_PHYIF_SHIFT #undef USB3_0_XHCI_GUSB2PHYCFG_PHYIF_MASK -#define USB3_0_XHCI_GUSB2PHYCFG_PHYIF_DEFVAL 0x00000000 -#define USB3_0_XHCI_GUSB2PHYCFG_PHYIF_SHIFT 3 -#define USB3_0_XHCI_GUSB2PHYCFG_PHYIF_MASK 0x00000008U +#define USB3_0_XHCI_GUSB2PHYCFG_PHYIF_DEFVAL 0x00000000 +#define USB3_0_XHCI_GUSB2PHYCFG_PHYIF_SHIFT 3 +#define USB3_0_XHCI_GUSB2PHYCFG_PHYIF_MASK 0x00000008U -/*HS/FS Timeout Calibration (TOutCal) The number of PHY clocks, as indicated by the application in this field, is multiplied by - a bit-time factor; this factor is added to the high-speed/full-speed interpacket timeout duration in the core to account for - dditional delays introduced by the PHY. This may be required, since the delay introduced by the PHY in generating the linesta - e condition may vary among PHYs. The USB standard timeout value for high-speed operation is 736 to 816 (inclusive) bit times. - The USB standard timeout value for full-speed operation is 16 to 18 (inclusive) bit times. The application must program this - ield based on the speed of connection. The number of bit times added per PHY clock are: High-speed operation: - One 30-MHz PH - clock = 16 bit times - One 60-MHz PHY clock = 8 bit times Full-speed operation: - One 30-MHz PHY clock = 0.4 bit times - One - 60-MHz PHY clock = 0.2 bit times - One 48-MHz PHY clock = 0.25 bit times*/ +/* +* HS/FS Timeout Calibration (TOutCal) The number of PHY clocks, as indicat + * ed by the application in this field, is multiplied by a bit-time factor; + * this factor is added to the high-speed/full-speed interpacket timeout d + * uration in the core to account for additional delays introduced by the P + * HY. This may be required, since the delay introduced by the PHY in gener + * ating the linestate condition may vary among PHYs. The USB standard time + * out value for high-speed operation is 736 to 816 (inclusive) bit times. + * The USB standard timeout value for full-speed operation is 16 to 18 (inc + * lusive) bit times. The application must program this field based on the + * speed of connection. The number of bit times added per PHY clock are: Hi + * gh-speed operation: - One 30-MHz PHY clock = 16 bit times - One 60-MHz P + * HY clock = 8 bit times Full-speed operation: - One 30-MHz PHY clock = 0. + * 4 bit times - One 60-MHz PHY clock = 0.2 bit times - One 48-MHz PHY cloc + * k = 0.25 bit times +*/ #undef USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_DEFVAL #undef USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_SHIFT #undef USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_MASK -#define USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_DEFVAL 0x00000000 -#define USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_SHIFT 0 -#define USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_MASK 0x00000007U +#define USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_DEFVAL 0x00000000 +#define USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_SHIFT 0 +#define USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_MASK 0x00000007U -/*This field indicates the frame length adjustment to be applied when SOF/ITP counter is running on the ref_clk. This register - alue is used to adjust the ITP interval when GCTL[SOFITPSYNC] is set to '1'; SOF and ITP interval when GLADJ.GFLADJ_REFCLK_LP - _SEL is set to '1'. This field must be programmed to a non-zero value only if GFLADJ_REFCLK_LPM_SEL is set to '1' or GCTL.SOF - TPSYNC is set to '1'. The value is derived as follows: FLADJ_REF_CLK_FLADJ=((125000/ref_clk_period_integer)-(125000/ref_clk_p - riod)) * ref_clk_period where - the ref_clk_period_integer is the integer value of the ref_clk period got by truncating the d - cimal (fractional) value that is programmed in the GUCTL.REF_CLK_PERIOD field. - the ref_clk_period is the ref_clk period inc - uding the fractional value. Examples: If the ref_clk is 24 MHz then - GUCTL.REF_CLK_PERIOD = 41 - GFLADJ.GLADJ_REFCLK_FLADJ = - ((125000/41)-(125000/41.6666))*41.6666 = 2032 (ignoring the fractional value) If the ref_clk is 48 MHz then - GUCTL.REF_CLK_P - RIOD = 20 - GFLADJ.GLADJ_REFCLK_FLADJ = ((125000/20)-(125000/20.8333))*20.8333 = 5208 (ignoring the fractional value)*/ +/* +* ULPI External VBUS Drive (ULPIExtVbusDrv) Selects supply source to drive + * 5V on VBUS, in the ULPI PHY. - 1'b0: PHY drives VBUS with internal char + * ge pump (default). - 1'b1: PHY drives VBUS with an external supply. (Onl + * y when RTL parameter DWC_USB3_HSPHY_INTERFACE = 2 or 3) +*/ +#undef USB3_0_XHCI_GUSB2PHYCFG_ULPIEXTVBUSDRV_DEFVAL +#undef USB3_0_XHCI_GUSB2PHYCFG_ULPIEXTVBUSDRV_SHIFT +#undef USB3_0_XHCI_GUSB2PHYCFG_ULPIEXTVBUSDRV_MASK +#define USB3_0_XHCI_GUSB2PHYCFG_ULPIEXTVBUSDRV_DEFVAL 0x00000000 +#define USB3_0_XHCI_GUSB2PHYCFG_ULPIEXTVBUSDRV_SHIFT 17 +#define USB3_0_XHCI_GUSB2PHYCFG_ULPIEXTVBUSDRV_MASK 0x00020000U + +/* +* This field indicates the frame length adjustment to be applied when SOF/ + * ITP counter is running on the ref_clk. This register value is used to ad + * just the ITP interval when GCTL[SOFITPSYNC] is set to '1'; SOF and ITP i + * nterval when GLADJ.GFLADJ_REFCLK_LPM_SEL is set to '1'. This field must + * be programmed to a non-zero value only if GFLADJ_REFCLK_LPM_SEL is set t + * o '1' or GCTL.SOFITPSYNC is set to '1'. The value is derived as follows: + * FLADJ_REF_CLK_FLADJ=((125000/ref_clk_period_integer)-(125000/ref_clk_pe + * riod)) * ref_clk_period where - the ref_clk_period_integer is the intege + * r value of the ref_clk period got by truncating the decimal (fractional) + * value that is programmed in the GUCTL.REF_CLK_PERIOD field. - the ref_c + * lk_period is the ref_clk period including the fractional value. Examples + * : If the ref_clk is 24 MHz then - GUCTL.REF_CLK_PERIOD = 41 - GFLADJ.GLA + * DJ_REFCLK_FLADJ = ((125000/41)-(125000/41.6666))*41.6666 = 2032 (ignorin + * g the fractional value) If the ref_clk is 48 MHz then - GUCTL.REF_CLK_PE + * RIOD = 20 - GFLADJ.GLADJ_REFCLK_FLADJ = ((125000/20)-(125000/20.8333))*2 + * 0.8333 = 5208 (ignoring the fractional value) +*/ #undef USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_DEFVAL #undef USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_SHIFT #undef USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_MASK -#define USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_DEFVAL 0x00000000 -#define USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_SHIFT 8 -#define USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_MASK 0x003FFF00U +#define USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_DEFVAL 0x00000000 +#define USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_SHIFT 8 +#define USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_MASK 0x003FFF00U -/*If TRUE Completion Timeout Disable is supported. This is required to be TRUE for Endpoint and either setting allowed for Root - ports. Drives Device Capability 2 [4]; EP=0x0001; RP=0x0001*/ +/* +* When this bit is set to '0', termsel, xcvrsel will become 0 during end o + * f resume while the opmode will become 0 once controller completes end of + * resume and enters U0 state (2 separate commandswill be issued). When th + * is bit is set to '1', all the termsel, xcvrsel, opmode becomes 0 during + * end of resume itself (only 1 command will be issued) +*/ +#undef USB3_0_XHCI_GUCTL1_RESUME_TERMSEL_XCVRSEL_UNIFY_DEFVAL +#undef USB3_0_XHCI_GUCTL1_RESUME_TERMSEL_XCVRSEL_UNIFY_SHIFT +#undef USB3_0_XHCI_GUCTL1_RESUME_TERMSEL_XCVRSEL_UNIFY_MASK +#define USB3_0_XHCI_GUCTL1_RESUME_TERMSEL_XCVRSEL_UNIFY_DEFVAL 0x00000000 +#define USB3_0_XHCI_GUCTL1_RESUME_TERMSEL_XCVRSEL_UNIFY_SHIFT 10 +#define USB3_0_XHCI_GUCTL1_RESUME_TERMSEL_XCVRSEL_UNIFY_MASK 0x00000400U + +/* +* Reserved +*/ +#undef USB3_0_XHCI_GUCTL1_RESERVED_9_DEFVAL +#undef USB3_0_XHCI_GUCTL1_RESERVED_9_SHIFT +#undef USB3_0_XHCI_GUCTL1_RESERVED_9_MASK +#define USB3_0_XHCI_GUCTL1_RESERVED_9_DEFVAL 0x00000000 +#define USB3_0_XHCI_GUCTL1_RESERVED_9_SHIFT 9 +#define USB3_0_XHCI_GUCTL1_RESERVED_9_MASK 0x00000200U + +/* +* Host IN Auto Retry (USBHstInAutoRetryEn) When set, this field enables th + * e Auto Retry feature. For IN transfers (non-isochronous) that encounter + * data packets with CRC errors or internal overrun scenarios, the auto ret + * ry feature causes the Host core to reply to the device with a non-termin + * ating retry ACK (that is, an ACK transaction packet with Retry = 1 and N + * umP != 0). If the Auto Retry feature is disabled (default), the core wil + * l respond with a terminating retry ACK (that is, an ACK transaction pack + * et with Retry = 1 and NumP = 0). - 1'b0: Auto Retry Disabled - 1'b1: Aut + * o Retry Enabled Note: This bit is also applicable to the device mode. +*/ +#undef USB3_0_XHCI_GUCTL_USBHSTINAUTORETRYEN_DEFVAL +#undef USB3_0_XHCI_GUCTL_USBHSTINAUTORETRYEN_SHIFT +#undef USB3_0_XHCI_GUCTL_USBHSTINAUTORETRYEN_MASK +#define USB3_0_XHCI_GUCTL_USBHSTINAUTORETRYEN_DEFVAL 0x00000000 +#define USB3_0_XHCI_GUCTL_USBHSTINAUTORETRYEN_SHIFT 14 +#define USB3_0_XHCI_GUCTL_USBHSTINAUTORETRYEN_MASK 0x00004000U + +/* +* If TRUE Completion Timeout Disable is supported. This is required to be + * TRUE for Endpoint and either setting allowed for Root ports. Drives Devi + * ce Capability 2 [4]; EP=0x0001; RP=0x0001 +*/ #undef PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_DEFVAL #undef PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_SHIFT #undef PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_MASK -#define PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_DEFVAL 0x00000905 -#define PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_SHIFT 9 -#define PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_MASK 0x00000200U +#define PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_DEFVAL 0x00000905 +#define PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_SHIFT 9 +#define PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_MASK 0x00000200U -/*Specifies mask/settings for Base Address Register (BAR) 0. If BAR is not to be implemented, set to 32'h00000000. Bits are def - ned as follows: Memory Space BAR [0] = Mem Space Indicator (set to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = - Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory a - erture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR1,BAR0\'7d to 1. IO Space BAR 0] = IO Space Indicator - set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o apert - re size in bytes.; EP=0x0004; RP=0x0000*/ +/* +* Specifies mask/settings for Base Address Register (BAR) 0. If BAR is not + * to be implemented, set to 32'h00000000. Bits are defined as follows: Me + * mory Space BAR [0] = Mem Space Indicator (set to 0) [2:1] = Type field ( + * 10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask + * for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to 1, w + * here 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63: + * n bits of \'7bBAR1,BAR0\'7d to 1. IO Space BAR 0] = IO Space Indicator ( + * set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of B + * AR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; + * EP=0x0004; RP=0x0000 +*/ #undef PCIE_ATTRIB_ATTR_7_ATTR_BAR0_DEFVAL #undef PCIE_ATTRIB_ATTR_7_ATTR_BAR0_SHIFT #undef PCIE_ATTRIB_ATTR_7_ATTR_BAR0_MASK -#define PCIE_ATTRIB_ATTR_7_ATTR_BAR0_DEFVAL -#define PCIE_ATTRIB_ATTR_7_ATTR_BAR0_SHIFT 0 -#define PCIE_ATTRIB_ATTR_7_ATTR_BAR0_MASK 0x0000FFFFU +#define PCIE_ATTRIB_ATTR_7_ATTR_BAR0_DEFVAL +#define PCIE_ATTRIB_ATTR_7_ATTR_BAR0_SHIFT 0 +#define PCIE_ATTRIB_ATTR_7_ATTR_BAR0_MASK 0x0000FFFFU -/*Specifies mask/settings for Base Address Register (BAR) 0. If BAR is not to be implemented, set to 32'h00000000. Bits are def - ned as follows: Memory Space BAR [0] = Mem Space Indicator (set to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = - Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory a - erture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR1,BAR0\'7d to 1. IO Space BAR 0] = IO Space Indicator - set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o apert - re size in bytes.; EP=0xFFF0; RP=0x0000*/ +/* +* Specifies mask/settings for Base Address Register (BAR) 0. If BAR is not + * to be implemented, set to 32'h00000000. Bits are defined as follows: Me + * mory Space BAR [0] = Mem Space Indicator (set to 0) [2:1] = Type field ( + * 10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask + * for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to 1, w + * here 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63: + * n bits of \'7bBAR1,BAR0\'7d to 1. IO Space BAR 0] = IO Space Indicator ( + * set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of B + * AR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; + * EP=0xFFF0; RP=0x0000 +*/ #undef PCIE_ATTRIB_ATTR_8_ATTR_BAR0_DEFVAL #undef PCIE_ATTRIB_ATTR_8_ATTR_BAR0_SHIFT #undef PCIE_ATTRIB_ATTR_8_ATTR_BAR0_MASK -#define PCIE_ATTRIB_ATTR_8_ATTR_BAR0_DEFVAL -#define PCIE_ATTRIB_ATTR_8_ATTR_BAR0_SHIFT 0 -#define PCIE_ATTRIB_ATTR_8_ATTR_BAR0_MASK 0x0000FFFFU +#define PCIE_ATTRIB_ATTR_8_ATTR_BAR0_DEFVAL +#define PCIE_ATTRIB_ATTR_8_ATTR_BAR0_SHIFT 0 +#define PCIE_ATTRIB_ATTR_8_ATTR_BAR0_MASK 0x0000FFFFU -/*Specifies mask/settings for Base Address Register (BAR) 1 if BAR0 is a 32-bit BAR, or the upper bits of \'7bBAR1,BAR0\'7d if - AR0 is a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR0 description if this functions as the uppe - bits of a 64-bit BAR. Bits are defined as follows: Memory Space BAR (not upper bits of BAR0) [0] = Mem Space Indicator (set - o 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if - 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of - '7bBAR2,BAR1\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable b - ts of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000*/ +/* +* Specifies mask/settings for Base Address Register (BAR) 1 if BAR0 is a 3 + * 2-bit BAR, or the upper bits of \'7bBAR1,BAR0\'7d if BAR0 is a 64-bit BA + * R. If BAR is not to be implemented, set to 32'h00000000. See BAR0 descri + * ption if this functions as the upper bits of a 64-bit BAR. Bits are defi + * ned as follows: Memory Space BAR (not upper bits of BAR0) [0] = Mem Spac + * e Indicator (set to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) + * [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if + * 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size + * in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR2,BAR1\'7d t + * o 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set + * to 0) [31:2] = Mask for writable bits of BAR; set uppermost 31:n bits t + * o 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000 +*/ #undef PCIE_ATTRIB_ATTR_9_ATTR_BAR1_DEFVAL #undef PCIE_ATTRIB_ATTR_9_ATTR_BAR1_SHIFT #undef PCIE_ATTRIB_ATTR_9_ATTR_BAR1_MASK -#define PCIE_ATTRIB_ATTR_9_ATTR_BAR1_DEFVAL -#define PCIE_ATTRIB_ATTR_9_ATTR_BAR1_SHIFT 0 -#define PCIE_ATTRIB_ATTR_9_ATTR_BAR1_MASK 0x0000FFFFU +#define PCIE_ATTRIB_ATTR_9_ATTR_BAR1_DEFVAL +#define PCIE_ATTRIB_ATTR_9_ATTR_BAR1_SHIFT 0 +#define PCIE_ATTRIB_ATTR_9_ATTR_BAR1_MASK 0x0000FFFFU -/*Specifies mask/settings for Base Address Register (BAR) 1 if BAR0 is a 32-bit BAR, or the upper bits of \'7bBAR1,BAR0\'7d if - AR0 is a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR0 description if this functions as the uppe - bits of a 64-bit BAR. Bits are defined as follows: Memory Space BAR (not upper bits of BAR0) [0] = Mem Space Indicator (set - o 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if - 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of - '7bBAR2,BAR1\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable b - ts of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000*/ +/* +* Specifies mask/settings for Base Address Register (BAR) 1 if BAR0 is a 3 + * 2-bit BAR, or the upper bits of \'7bBAR1,BAR0\'7d if BAR0 is a 64-bit BA + * R. If BAR is not to be implemented, set to 32'h00000000. See BAR0 descri + * ption if this functions as the upper bits of a 64-bit BAR. Bits are defi + * ned as follows: Memory Space BAR (not upper bits of BAR0) [0] = Mem Spac + * e Indicator (set to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) + * [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if + * 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size + * in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR2,BAR1\'7d t + * o 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set + * to 0) [31:2] = Mask for writable bits of BAR; set uppermost 31:n bits t + * o 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000 +*/ #undef PCIE_ATTRIB_ATTR_10_ATTR_BAR1_DEFVAL #undef PCIE_ATTRIB_ATTR_10_ATTR_BAR1_SHIFT #undef PCIE_ATTRIB_ATTR_10_ATTR_BAR1_MASK -#define PCIE_ATTRIB_ATTR_10_ATTR_BAR1_DEFVAL -#define PCIE_ATTRIB_ATTR_10_ATTR_BAR1_SHIFT 0 -#define PCIE_ATTRIB_ATTR_10_ATTR_BAR1_MASK 0x0000FFFFU +#define PCIE_ATTRIB_ATTR_10_ATTR_BAR1_DEFVAL +#define PCIE_ATTRIB_ATTR_10_ATTR_BAR1_SHIFT 0 +#define PCIE_ATTRIB_ATTR_10_ATTR_BAR1_MASK 0x0000FFFFU -/*For an endpoint, specifies mask/settings for Base Address Register (BAR) 2 if BAR1 is a 32-bit BAR, or the upper bits of \'7b - AR2,BAR1\'7d if BAR1 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR1 descri - tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to 00FF_FFFF. For an endpoin - , bits are defined as follows: Memory Space BAR (not upper bits of BAR1) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi - ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe - most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR3,BAR2\'7d to - . IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper - ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0x0004; RP=0xFFFF*/ +/* +* For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 2 if BAR1 is a 32-bit BAR, or the upper bits of \'7bBAR2,BAR1\'7d if BA + * R1 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR1 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root: This must be set to 00FF_FFF + * F. For an endpoint, bits are defined as follows: Memory Space BAR (not u + * pper bits of BAR1) [0] = Mem Space Indicator (set to 0) [2:1] = Type fie + * ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = M + * ask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to + * 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost + * 63:n bits of \'7bBAR3,BAR2\'7d to 1. IO Space BAR 0] = IO Space Indicat + * or (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits + * of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in byt + * es.; EP=0x0004; RP=0xFFFF +*/ #undef PCIE_ATTRIB_ATTR_11_ATTR_BAR2_DEFVAL #undef PCIE_ATTRIB_ATTR_11_ATTR_BAR2_SHIFT #undef PCIE_ATTRIB_ATTR_11_ATTR_BAR2_MASK -#define PCIE_ATTRIB_ATTR_11_ATTR_BAR2_DEFVAL -#define PCIE_ATTRIB_ATTR_11_ATTR_BAR2_SHIFT 0 -#define PCIE_ATTRIB_ATTR_11_ATTR_BAR2_MASK 0x0000FFFFU +#define PCIE_ATTRIB_ATTR_11_ATTR_BAR2_DEFVAL +#define PCIE_ATTRIB_ATTR_11_ATTR_BAR2_SHIFT 0 +#define PCIE_ATTRIB_ATTR_11_ATTR_BAR2_MASK 0x0000FFFFU -/*For an endpoint, specifies mask/settings for Base Address Register (BAR) 2 if BAR1 is a 32-bit BAR, or the upper bits of \'7b - AR2,BAR1\'7d if BAR1 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR1 descri - tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to 00FF_FFFF. For an endpoin - , bits are defined as follows: Memory Space BAR (not upper bits of BAR1) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi - ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe - most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR3,BAR2\'7d to - . IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper - ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFF0; RP=0x00FF*/ +/* +* For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 2 if BAR1 is a 32-bit BAR, or the upper bits of \'7bBAR2,BAR1\'7d if BA + * R1 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR1 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root: This must be set to 00FF_FFF + * F. For an endpoint, bits are defined as follows: Memory Space BAR (not u + * pper bits of BAR1) [0] = Mem Space Indicator (set to 0) [2:1] = Type fie + * ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = M + * ask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to + * 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost + * 63:n bits of \'7bBAR3,BAR2\'7d to 1. IO Space BAR 0] = IO Space Indicat + * or (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits + * of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in byt + * es.; EP=0xFFF0; RP=0x00FF +*/ #undef PCIE_ATTRIB_ATTR_12_ATTR_BAR2_DEFVAL #undef PCIE_ATTRIB_ATTR_12_ATTR_BAR2_SHIFT #undef PCIE_ATTRIB_ATTR_12_ATTR_BAR2_MASK -#define PCIE_ATTRIB_ATTR_12_ATTR_BAR2_DEFVAL -#define PCIE_ATTRIB_ATTR_12_ATTR_BAR2_SHIFT 0 -#define PCIE_ATTRIB_ATTR_12_ATTR_BAR2_MASK 0x0000FFFFU +#define PCIE_ATTRIB_ATTR_12_ATTR_BAR2_DEFVAL +#define PCIE_ATTRIB_ATTR_12_ATTR_BAR2_SHIFT 0 +#define PCIE_ATTRIB_ATTR_12_ATTR_BAR2_MASK 0x0000FFFFU -/*For an endpoint, specifies mask/settings for Base Address Register (BAR) 3 if BAR2 is a 32-bit BAR, or the upper bits of \'7b - AR3,BAR2\'7d if BAR2 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR2 descri - tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: FFFF_0000 = IO Limit/Bas - Registers not implemented FFFF_F0F0 = IO Limit/Base Registers use 16-bit decode FFFF_F1F1 = IO Limit/Base Registers use 32-b - t decode For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of BAR2) [0] = Mem Space Indicator (s - t to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; - if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits - f \'7bBAR4,BAR3\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writabl - bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000*/ +/* +* For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 3 if BAR2 is a 32-bit BAR, or the upper bits of \'7bBAR3,BAR2\'7d if BA + * R2 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR2 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root, this must be set to: FFFF_00 + * 00 = IO Limit/Base Registers not implemented FFFF_F0F0 = IO Limit/Base R + * egisters use 16-bit decode FFFF_F1F1 = IO Limit/Base Registers use 32-bi + * t decode For an endpoint, bits are defined as follows: Memory Space BAR + * (not upper bits of BAR2) [0] = Mem Space Indicator (set to 0) [2:1] = Ty + * pe field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31: + * 4] = Mask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bi + * ts to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set upp + * ermost 63:n bits of \'7bBAR4,BAR3\'7d to 1. IO Space BAR 0] = IO Space I + * ndicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable + * bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size + * in bytes.; EP=0xFFFF; RP=0x0000 +*/ #undef PCIE_ATTRIB_ATTR_13_ATTR_BAR3_DEFVAL #undef PCIE_ATTRIB_ATTR_13_ATTR_BAR3_SHIFT #undef PCIE_ATTRIB_ATTR_13_ATTR_BAR3_MASK -#define PCIE_ATTRIB_ATTR_13_ATTR_BAR3_DEFVAL -#define PCIE_ATTRIB_ATTR_13_ATTR_BAR3_SHIFT 0 -#define PCIE_ATTRIB_ATTR_13_ATTR_BAR3_MASK 0x0000FFFFU +#define PCIE_ATTRIB_ATTR_13_ATTR_BAR3_DEFVAL +#define PCIE_ATTRIB_ATTR_13_ATTR_BAR3_SHIFT 0 +#define PCIE_ATTRIB_ATTR_13_ATTR_BAR3_MASK 0x0000FFFFU -/*For an endpoint, specifies mask/settings for Base Address Register (BAR) 3 if BAR2 is a 32-bit BAR, or the upper bits of \'7b - AR3,BAR2\'7d if BAR2 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR2 descri - tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: FFFF_0000 = IO Limit/Bas - Registers not implemented FFFF_F0F0 = IO Limit/Base Registers use 16-bit decode FFFF_F1F1 = IO Limit/Base Registers use 32-b - t decode For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of BAR2) [0] = Mem Space Indicator (s - t to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; - if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits - f \'7bBAR4,BAR3\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writabl - bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0xFFFF*/ +/* +* For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 3 if BAR2 is a 32-bit BAR, or the upper bits of \'7bBAR3,BAR2\'7d if BA + * R2 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR2 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root, this must be set to: FFFF_00 + * 00 = IO Limit/Base Registers not implemented FFFF_F0F0 = IO Limit/Base R + * egisters use 16-bit decode FFFF_F1F1 = IO Limit/Base Registers use 32-bi + * t decode For an endpoint, bits are defined as follows: Memory Space BAR + * (not upper bits of BAR2) [0] = Mem Space Indicator (set to 0) [2:1] = Ty + * pe field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31: + * 4] = Mask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bi + * ts to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set upp + * ermost 63:n bits of \'7bBAR4,BAR3\'7d to 1. IO Space BAR 0] = IO Space I + * ndicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable + * bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size + * in bytes.; EP=0xFFFF; RP=0xFFFF +*/ #undef PCIE_ATTRIB_ATTR_14_ATTR_BAR3_DEFVAL #undef PCIE_ATTRIB_ATTR_14_ATTR_BAR3_SHIFT #undef PCIE_ATTRIB_ATTR_14_ATTR_BAR3_MASK -#define PCIE_ATTRIB_ATTR_14_ATTR_BAR3_DEFVAL -#define PCIE_ATTRIB_ATTR_14_ATTR_BAR3_SHIFT 0 -#define PCIE_ATTRIB_ATTR_14_ATTR_BAR3_MASK 0x0000FFFFU +#define PCIE_ATTRIB_ATTR_14_ATTR_BAR3_DEFVAL +#define PCIE_ATTRIB_ATTR_14_ATTR_BAR3_SHIFT 0 +#define PCIE_ATTRIB_ATTR_14_ATTR_BAR3_MASK 0x0000FFFFU -/*For an endpoint, specifies mask/settings for Base Address Register (BAR) 4 if BAR3 is a 32-bit BAR, or the upper bits of \'7b - AR4,BAR3\'7d if BAR3 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR3 descri - tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to FFF0_FFF0. For an endpoin - , bits are defined as follows: Memory Space BAR (not upper bits of BAR3) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi - ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe - most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR5,BAR4\'7d to - . IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper - ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0x0004; RP=0xFFF0*/ +/* +* For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 4 if BAR3 is a 32-bit BAR, or the upper bits of \'7bBAR4,BAR3\'7d if BA + * R3 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR3 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root: This must be set to FFF0_FFF + * 0. For an endpoint, bits are defined as follows: Memory Space BAR (not u + * pper bits of BAR3) [0] = Mem Space Indicator (set to 0) [2:1] = Type fie + * ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = M + * ask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to + * 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost + * 63:n bits of \'7bBAR5,BAR4\'7d to 1. IO Space BAR 0] = IO Space Indicat + * or (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits + * of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in byt + * es.; EP=0x0004; RP=0xFFF0 +*/ #undef PCIE_ATTRIB_ATTR_15_ATTR_BAR4_DEFVAL #undef PCIE_ATTRIB_ATTR_15_ATTR_BAR4_SHIFT #undef PCIE_ATTRIB_ATTR_15_ATTR_BAR4_MASK -#define PCIE_ATTRIB_ATTR_15_ATTR_BAR4_DEFVAL -#define PCIE_ATTRIB_ATTR_15_ATTR_BAR4_SHIFT 0 -#define PCIE_ATTRIB_ATTR_15_ATTR_BAR4_MASK 0x0000FFFFU +#define PCIE_ATTRIB_ATTR_15_ATTR_BAR4_DEFVAL +#define PCIE_ATTRIB_ATTR_15_ATTR_BAR4_SHIFT 0 +#define PCIE_ATTRIB_ATTR_15_ATTR_BAR4_MASK 0x0000FFFFU -/*For an endpoint, specifies mask/settings for Base Address Register (BAR) 4 if BAR3 is a 32-bit BAR, or the upper bits of \'7b - AR4,BAR3\'7d if BAR3 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR3 descri - tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to FFF0_FFF0. For an endpoin - , bits are defined as follows: Memory Space BAR (not upper bits of BAR3) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi - ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe - most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR5,BAR4\'7d to - . IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper - ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFF0; RP=0xFFF0*/ +/* +* For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 4 if BAR3 is a 32-bit BAR, or the upper bits of \'7bBAR4,BAR3\'7d if BA + * R3 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR3 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root: This must be set to FFF0_FFF + * 0. For an endpoint, bits are defined as follows: Memory Space BAR (not u + * pper bits of BAR3) [0] = Mem Space Indicator (set to 0) [2:1] = Type fie + * ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = M + * ask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to + * 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost + * 63:n bits of \'7bBAR5,BAR4\'7d to 1. IO Space BAR 0] = IO Space Indicat + * or (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits + * of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in byt + * es.; EP=0xFFF0; RP=0xFFF0 +*/ #undef PCIE_ATTRIB_ATTR_16_ATTR_BAR4_DEFVAL #undef PCIE_ATTRIB_ATTR_16_ATTR_BAR4_SHIFT #undef PCIE_ATTRIB_ATTR_16_ATTR_BAR4_MASK -#define PCIE_ATTRIB_ATTR_16_ATTR_BAR4_DEFVAL -#define PCIE_ATTRIB_ATTR_16_ATTR_BAR4_SHIFT 0 -#define PCIE_ATTRIB_ATTR_16_ATTR_BAR4_MASK 0x0000FFFFU +#define PCIE_ATTRIB_ATTR_16_ATTR_BAR4_DEFVAL +#define PCIE_ATTRIB_ATTR_16_ATTR_BAR4_SHIFT 0 +#define PCIE_ATTRIB_ATTR_16_ATTR_BAR4_MASK 0x0000FFFFU -/*For an endpoint, specifies mask/settings for Base Address Register (BAR) 5 if BAR4 is a 32-bit BAR, or the upper bits of \'7b - AR5,BAR4\'7d if BAR4 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR4 descri - tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: 0000_0000 = Prefetchable - Memory Limit/Base Registers not implemented FFF0_FFF0 = 32-bit Prefetchable Memory Limit/Base implemented FFF1_FFF1 = 64-bit - refetchable Memory Limit/Base implemented For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of B - R4) [0] = Mem Space Indicator (set to 0) [2:1] = Type field (00 for 32-bit; BAR5 cannot be lower part of a 64-bit BAR) [3] = - refetchable (0 or 1) [31:4] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=memory aperture size in - ytes. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set u - permost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0xFFF1*/ +/* +* For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 5 if BAR4 is a 32-bit BAR, or the upper bits of \'7bBAR5,BAR4\'7d if BA + * R4 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR4 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root, this must be set to: 0000_00 + * 00 = Prefetchable Memory Limit/Base Registers not implemented FFF0_FFF0 + * = 32-bit Prefetchable Memory Limit/Base implemented FFF1_FFF1 = 64-bit P + * refetchable Memory Limit/Base implemented For an endpoint, bits are defi + * ned as follows: Memory Space BAR (not upper bits of BAR4) [0] = Mem Spac + * e Indicator (set to 0) [2:1] = Type field (00 for 32-bit; BAR5 cannot be + * lower part of a 64-bit BAR) [3] = Prefetchable (0 or 1) [31:4] = Mask f + * or writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=memory + * aperture size in bytes. IO Space BAR 0] = IO Space Indicator (set to 1) + * [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set up + * permost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF + * ; RP=0xFFF1 +*/ #undef PCIE_ATTRIB_ATTR_17_ATTR_BAR5_DEFVAL #undef PCIE_ATTRIB_ATTR_17_ATTR_BAR5_SHIFT #undef PCIE_ATTRIB_ATTR_17_ATTR_BAR5_MASK -#define PCIE_ATTRIB_ATTR_17_ATTR_BAR5_DEFVAL -#define PCIE_ATTRIB_ATTR_17_ATTR_BAR5_SHIFT 0 -#define PCIE_ATTRIB_ATTR_17_ATTR_BAR5_MASK 0x0000FFFFU +#define PCIE_ATTRIB_ATTR_17_ATTR_BAR5_DEFVAL +#define PCIE_ATTRIB_ATTR_17_ATTR_BAR5_SHIFT 0 +#define PCIE_ATTRIB_ATTR_17_ATTR_BAR5_MASK 0x0000FFFFU -/*For an endpoint, specifies mask/settings for Base Address Register (BAR) 5 if BAR4 is a 32-bit BAR, or the upper bits of \'7b - AR5,BAR4\'7d if BAR4 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR4 descri - tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: 0000_0000 = Prefetchable - Memory Limit/Base Registers not implemented FFF0_FFF0 = 32-bit Prefetchable Memory Limit/Base implemented FFF1_FFF1 = 64-bit - refetchable Memory Limit/Base implemented For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of B - R4) [0] = Mem Space Indicator (set to 0) [2:1] = Type field (00 for 32-bit; BAR5 cannot be lower part of a 64-bit BAR) [3] = - refetchable (0 or 1) [31:4] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=memory aperture size in - ytes. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set u - permost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0xFFF1*/ +/* +* For an endpoint, specifies mask/settings for Base Address Register (BAR) + * 5 if BAR4 is a 32-bit BAR, or the upper bits of \'7bBAR5,BAR4\'7d if BA + * R4 is the lower part of a 64-bit BAR. If BAR is not to be implemented, s + * et to 32'h00000000. See BAR4 description if this functions as the upper + * bits of a 64-bit BAR. For a switch or root, this must be set to: 0000_00 + * 00 = Prefetchable Memory Limit/Base Registers not implemented FFF0_FFF0 + * = 32-bit Prefetchable Memory Limit/Base implemented FFF1_FFF1 = 64-bit P + * refetchable Memory Limit/Base implemented For an endpoint, bits are defi + * ned as follows: Memory Space BAR (not upper bits of BAR4) [0] = Mem Spac + * e Indicator (set to 0) [2:1] = Type field (00 for 32-bit; BAR5 cannot be + * lower part of a 64-bit BAR) [3] = Prefetchable (0 or 1) [31:4] = Mask f + * or writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=memory + * aperture size in bytes. IO Space BAR 0] = IO Space Indicator (set to 1) + * [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set up + * permost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF + * ; RP=0xFFF1 +*/ #undef PCIE_ATTRIB_ATTR_18_ATTR_BAR5_DEFVAL #undef PCIE_ATTRIB_ATTR_18_ATTR_BAR5_SHIFT #undef PCIE_ATTRIB_ATTR_18_ATTR_BAR5_MASK -#define PCIE_ATTRIB_ATTR_18_ATTR_BAR5_DEFVAL -#define PCIE_ATTRIB_ATTR_18_ATTR_BAR5_SHIFT 0 -#define PCIE_ATTRIB_ATTR_18_ATTR_BAR5_MASK 0x0000FFFFU +#define PCIE_ATTRIB_ATTR_18_ATTR_BAR5_DEFVAL +#define PCIE_ATTRIB_ATTR_18_ATTR_BAR5_SHIFT 0 +#define PCIE_ATTRIB_ATTR_18_ATTR_BAR5_MASK 0x0000FFFFU -/*Specifies maximum payload supported. Valid settings are: 0- 128 bytes, 1- 256 bytes, 2- 512 bytes, 3- 1024 bytes. Transferred - to the Device Capabilities register. The values: 4-2048 bytes, 5- 4096 bytes are not supported; EP=0x0001; RP=0x0001*/ +/* +* Specifies maximum payload supported. Valid settings are: 0- 128 bytes, 1 + * - 256 bytes, 2- 512 bytes, 3- 1024 bytes. Transferred to the Device Capa + * bilities register. The values: 4-2048 bytes, 5- 4096 bytes are not suppo + * rted; EP=0x0001; RP=0x0001 +*/ #undef PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_DEFVAL #undef PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_SHIFT #undef PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_MASK -#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_DEFVAL 0x00002138 -#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_SHIFT 8 -#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_MASK 0x00000700U +#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_DEFVAL 0x00002138 +#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_SHIFT 8 +#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_MASK 0x00000700U -/*Endpoint L1 Acceptable Latency. Records the latency that the endpoint can withstand on transitions from L1 state to L0 (if L1 - state supported). Valid settings are: 0h less than 1us, 1h 1 to 2us, 2h 2 to 4us, 3h 4 to 8us, 4h 8 to 16us, 5h 16 to 32us, 6 - 32 to 64us, 7h more than 64us. For Endpoints only. Must be 0h for other devices.; EP=0x0007; RP=0x0000*/ +/* +* Endpoint L1 Acceptable Latency. Records the latency that the endpoint ca + * n withstand on transitions from L1 state to L0 (if L1 state supported). + * Valid settings are: 0h less than 1us, 1h 1 to 2us, 2h 2 to 4us, 3h 4 to + * 8us, 4h 8 to 16us, 5h 16 to 32us, 6h 32 to 64us, 7h more than 64us. For + * Endpoints only. Must be 0h for other devices.; EP=0x0007; RP=0x0000 +*/ #undef PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_DEFVAL #undef PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_SHIFT #undef PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_MASK -#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_DEFVAL 0x00002138 -#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_SHIFT 3 -#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_MASK 0x00000038U +#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_DEFVAL 0x00002138 +#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_SHIFT 3 +#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_MASK 0x00000038U -/*Identifies the type of device/port as follows: 0000b PCI Express Endpoint device, 0001b Legacy PCI Express Endpoint device, 0 - 00b Root Port of PCI Express Root Complex, 0101b Upstream Port of PCI Express Switch, 0110b Downstream Port of PCI Express Sw - tch, 0111b PCIE Express to PCI/PCI-X Bridge, 1000b PCI/PCI-X to PCI Express Bridge. Transferred to PCI Express Capabilities r - gister. Must be consistent with IS_SWITCH and UPSTREAM_FACING settings.; EP=0x0000; RP=0x0004*/ +/* +* Identifies the type of device/port as follows: 0000b PCI Express Endpoin + * t device, 0001b Legacy PCI Express Endpoint device, 0100b Root Port of P + * CI Express Root Complex, 0101b Upstream Port of PCI Express Switch, 0110 + * b Downstream Port of PCI Express Switch, 0111b PCIE Express to PCI/PCI-X + * Bridge, 1000b PCI/PCI-X to PCI Express Bridge. Transferred to PCI Expre + * ss Capabilities register. Must be consistent with IS_SWITCH and UPSTREAM + * _FACING settings.; EP=0x0000; RP=0x0004 +*/ #undef PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_DEFVAL #undef PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_SHIFT #undef PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_MASK -#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_DEFVAL 0x00009C02 -#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_SHIFT 4 -#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_MASK 0x000000F0U +#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_DEFVAL 0x00009C02 +#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_SHIFT 4 +#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_MASK 0x000000F0U -/*PCIe Capability's Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capab - lity.; EP=0x009C; RP=0x0000*/ +/* +* PCIe Capability's Next Capability Offset pointer to the next item in the + * capabilities list, or 00h if this is the final capability.; EP=0x009C; + * RP=0x0000 +*/ #undef PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_DEFVAL #undef PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_SHIFT #undef PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_MASK -#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_DEFVAL 0x00009C02 -#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_SHIFT 8 -#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_MASK 0x0000FF00U +#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_DEFVAL 0x00009C02 +#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_SHIFT 8 +#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_MASK 0x0000FF00U -/*Number of credits that should be advertised for Completion data received on Virtual Channel 0. The bytes advertised must be l - ss than or equal to the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0172; RP=0x00CD*/ +/* +* Number of credits that should be advertised for Completion data received + * on Virtual Channel 0. The bytes advertised must be less than or equal t + * o the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0172; RP=0x00CD +*/ #undef PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_DEFVAL #undef PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_SHIFT #undef PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_MASK -#define PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_DEFVAL -#define PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_SHIFT 0 -#define PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_MASK 0x000007FFU +#define PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_DEFVAL +#define PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_SHIFT 0 +#define PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_MASK 0x000007FFU -/*Number of credits that should be advertised for Completion headers received on Virtual Channel 0. The sum of the posted, non - osted, and completion header credits must be <= 80; EP=0x0048; RP=0x0024*/ +/* +* Number of credits that should be advertised for Completion headers recei + * ved on Virtual Channel 0. The sum of the posted, non posted, and complet + * ion header credits must be <= 80; EP=0x0048; RP=0x0024 +*/ #undef PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_DEFVAL #undef PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_SHIFT #undef PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_MASK -#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_DEFVAL 0x00000248 -#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_SHIFT 0 -#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_MASK 0x0000007FU +#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_DEFVAL 0x00000248 +#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_SHIFT 0 +#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_MASK 0x0000007FU -/*Number of credits that should be advertised for Non-Posted headers received on Virtual Channel 0. The number of non posted da - a credits advertised by the block is equal to the number of non posted header credits. The sum of the posted, non posted, and - completion header credits must be <= 80; EP=0x0004; RP=0x000C*/ +/* +* Number of credits that should be advertised for Non-Posted headers recei + * ved on Virtual Channel 0. The number of non posted data credits advertis + * ed by the block is equal to the number of non posted header credits. The + * sum of the posted, non posted, and completion header credits must be <= + * 80; EP=0x0004; RP=0x000C +*/ #undef PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_DEFVAL #undef PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_SHIFT #undef PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_MASK -#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_DEFVAL 0x00000248 -#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_SHIFT 7 -#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_MASK 0x00003F80U +#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_DEFVAL 0x00000248 +#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_SHIFT 7 +#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_MASK 0x00003F80U -/*Number of credits that should be advertised for Non-Posted data received on Virtual Channel 0. The number of non posted data - redits advertised by the block is equal to two times the number of non posted header credits if atomic operations are support - d or is equal to the number of non posted header credits if atomic operations are not supported. The bytes advertised must be - less than or equal to the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0008; RP=0x0018*/ +/* +* Number of credits that should be advertised for Non-Posted data received + * on Virtual Channel 0. The number of non posted data credits advertised + * by the block is equal to two times the number of non posted header credi + * ts if atomic operations are supported or is equal to the number of non p + * osted header credits if atomic operations are not supported. The bytes a + * dvertised must be less than or equal to the bram bytes available. See VC + * 0_RX_RAM_LIMIT; EP=0x0008; RP=0x0018 +*/ #undef PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_DEFVAL #undef PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_SHIFT #undef PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_MASK -#define PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_DEFVAL -#define PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_SHIFT 0 -#define PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_MASK 0x000007FFU +#define PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_DEFVAL +#define PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_SHIFT 0 +#define PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_MASK 0x000007FFU -/*Number of credits that should be advertised for Posted data received on Virtual Channel 0. The bytes advertised must be less - han or equal to the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0020; RP=0x00B5*/ +/* +* Number of credits that should be advertised for Posted data received on + * Virtual Channel 0. The bytes advertised must be less than or equal to th + * e bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0020; RP=0x00B5 +*/ #undef PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_DEFVAL #undef PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_SHIFT #undef PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_MASK -#define PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_DEFVAL -#define PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_SHIFT 0 -#define PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_MASK 0x000007FFU +#define PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_DEFVAL +#define PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_SHIFT 0 +#define PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_MASK 0x000007FFU -/*Not currently in use. Invert ECRC generated by block when trn_tecrc_gen_n and trn_terrfwd_n are asserted.; EP=0x0000; RP=0x00 - 0*/ +/* +* Not currently in use. Invert ECRC generated by block when trn_tecrc_gen_ + * n and trn_terrfwd_n are asserted.; EP=0x0000; RP=0x0000 +*/ #undef PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_DEFVAL #undef PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_SHIFT #undef PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_MASK -#define PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_DEFVAL 0x00007E04 -#define PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_SHIFT 15 -#define PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_MASK 0x00008000U +#define PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_DEFVAL 0x00007E04 +#define PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_SHIFT 15 +#define PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_MASK 0x00008000U -/*Enables td bit clear and ECRC trim on received TLP's FALSE == don't trim TRUE == trim.; EP=0x0001; RP=0x0001*/ +/* +* Enables td bit clear and ECRC trim on received TLP's FALSE == don't trim + * TRUE == trim.; EP=0x0001; RP=0x0001 +*/ #undef PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_DEFVAL #undef PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_SHIFT #undef PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_MASK -#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_DEFVAL 0x00007E04 -#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_SHIFT 14 -#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_MASK 0x00004000U +#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_DEFVAL 0x00007E04 +#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_SHIFT 14 +#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_MASK 0x00004000U -/*Enables ECRC check on received TLP's 0 == don't check 1 == always check 3 == check if enabled by ECRC check enable bit of AER - cap structure; EP=0x0003; RP=0x0003*/ +/* +* Enables ECRC check on received TLP's 0 == don't check 1 == always check + * 3 == check if enabled by ECRC check enable bit of AER cap structure; EP= + * 0x0003; RP=0x0003 +*/ #undef PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_DEFVAL #undef PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_SHIFT #undef PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_MASK -#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_DEFVAL 0x00007E04 -#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_SHIFT 12 -#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_MASK 0x00003000U +#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_DEFVAL 0x00007E04 +#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_SHIFT 12 +#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_MASK 0x00003000U -/*Index of last packet buffer used by TX TLM (i.e. number of buffers - 1). Calculated from max payload size supported and the n - mber of brams configured for transmit; EP=0x001C; RP=0x001C*/ +/* +* Index of last packet buffer used by TX TLM (i.e. number of buffers - 1). + * Calculated from max payload size supported and the number of brams conf + * igured for transmit; EP=0x001C; RP=0x001C +*/ #undef PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_DEFVAL #undef PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_SHIFT #undef PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_MASK -#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_DEFVAL 0x00007E04 -#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_SHIFT 7 -#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_MASK 0x00000F80U +#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_DEFVAL 0x00007E04 +#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_SHIFT 7 +#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_MASK 0x00000F80U -/*Number of credits that should be advertised for Posted headers received on Virtual Channel 0. The sum of the posted, non post - d, and completion header credits must be <= 80; EP=0x0004; RP=0x0020*/ +/* +* Number of credits that should be advertised for Posted headers received + * on Virtual Channel 0. The sum of the posted, non posted, and completion + * header credits must be <= 80; EP=0x0004; RP=0x0020 +*/ #undef PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_DEFVAL #undef PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_SHIFT #undef PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_MASK -#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_DEFVAL 0x00007E04 -#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_SHIFT 0 -#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_MASK 0x0000007FU +#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_DEFVAL 0x00007E04 +#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_SHIFT 0 +#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_MASK 0x0000007FU -/*Specifies values to be transferred to Header Type register. Bit 7 should be set to '0' indicating single-function device. Bit - 0 identifies header as Type 0 or Type 1, with '0' indicating a Type 0 header.; EP=0x0000; RP=0x0001*/ +/* +* Specifies values to be transferred to Header Type register. Bit 7 should + * be set to '0' indicating single-function device. Bit 0 identifies heade + * r as Type 0 or Type 1, with '0' indicating a Type 0 header.; EP=0x0000; + * RP=0x0001 +*/ #undef PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_DEFVAL #undef PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_SHIFT #undef PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_MASK -#define PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_DEFVAL 0x00000100 -#define PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_SHIFT 0 -#define PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_MASK 0x000000FFU +#define PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_DEFVAL 0x00000100 +#define PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_SHIFT 0 +#define PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_MASK 0x000000FFU -/*PM Capability's Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capabil - ty.; EP=0x0048; RP=0x0060*/ +/* +* PM Capability's Next Capability Offset pointer to the next item in the c + * apabilities list, or 00h if this is the final capability.; EP=0x0048; RP + * =0x0060 +*/ #undef PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_DEFVAL #undef PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_SHIFT #undef PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_MASK -#define PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_DEFVAL 0x00003D48 -#define PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_SHIFT 0 -#define PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_MASK 0x000000FFU +#define PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_DEFVAL 0x00003D48 +#define PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_SHIFT 0 +#define PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_MASK 0x000000FFU -/*MSI Per-Vector Masking Capable. The value is transferred to the MSI Control Register[8]. When set, adds Mask and Pending Dwor - to Cap structure; EP=0x0000; RP=0x0000*/ +/* +* MSI Per-Vector Masking Capable. The value is transferred to the MSI Cont + * rol Register[8]. When set, adds Mask and Pending Dword to Cap structure; + * EP=0x0000; RP=0x0000 +*/ #undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_DEFVAL #undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_SHIFT #undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_MASK -#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_DEFVAL 0x00000160 -#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_SHIFT 9 -#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_MASK 0x00000200U +#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_DEFVAL 0x00000160 +#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_SHIFT 9 +#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_MASK 0x00000200U -/*Indicates that the MSI structures exists. If this is FALSE, then the MSI structure cannot be accessed via either the link or - he management port.; EP=0x0001; RP=0x0000*/ +/* +* Indicates that the MSI structures exists. If this is FALSE, then the MSI + * structure cannot be accessed via either the link or the management port + * .; EP=0x0001; RP=0x0000 +*/ #undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_DEFVAL #undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_SHIFT #undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_MASK -#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_DEFVAL 0x00000160 -#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_SHIFT 8 -#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_MASK 0x00000100U +#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_DEFVAL 0x00000160 +#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_SHIFT 8 +#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_MASK 0x00000100U -/*MSI Capability's Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capabi - ity.; EP=0x0060; RP=0x0000*/ +/* +* MSI Capability's Next Capability Offset pointer to the next item in the + * capabilities list, or 00h if this is the final capability.; EP=0x0060; R + * P=0x0000 +*/ #undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_DEFVAL #undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_SHIFT #undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_MASK -#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_DEFVAL 0x00000160 -#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_SHIFT 0 -#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_MASK 0x000000FFU +#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_DEFVAL 0x00000160 +#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_SHIFT 0 +#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_MASK 0x000000FFU -/*Indicates that the MSI structures exists. If this is FALSE, then the MSI structure cannot be accessed via either the link or - he management port.; EP=0x0001; RP=0x0000*/ +/* +* Indicates that the MSI structures exists. If this is FALSE, then the MSI + * structure cannot be accessed via either the link or the management port + * .; EP=0x0001; RP=0x0000 +*/ #undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_DEFVAL #undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_SHIFT #undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_MASK -#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_DEFVAL 0x00000160 -#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_SHIFT 8 -#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_MASK 0x00000100U +#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_DEFVAL 0x00000160 +#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_SHIFT 8 +#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_MASK 0x00000100U -/*Maximum Link Width. Valid settings are: 000001b x1, 000010b x2, 000100b x4, 001000b x8.; EP=0x0004; RP=0x0004*/ +/* +* Maximum Link Width. Valid settings are: 000001b x1, 000010b x2, 000100b + * x4, 001000b x8.; EP=0x0004; RP=0x0004 +*/ #undef PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_DEFVAL #undef PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_SHIFT #undef PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_MASK -#define PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_DEFVAL 0x00000104 -#define PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_SHIFT 0 -#define PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_MASK 0x0000003FU +#define PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_DEFVAL 0x00000104 +#define PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_SHIFT 0 +#define PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_MASK 0x0000003FU -/*Used by LTSSM to set Maximum Link Width. Valid settings are: 000001b [x1], 000010b [x2], 000100b [x4], 001000b [x8].; EP=0x00 - 4; RP=0x0004*/ +/* +* Used by LTSSM to set Maximum Link Width. Valid settings are: 000001b [x1 + * ], 000010b [x2], 000100b [x4], 001000b [x8].; EP=0x0004; RP=0x0004 +*/ #undef PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_DEFVAL #undef PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_SHIFT #undef PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_MASK -#define PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_DEFVAL 0x00000104 -#define PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_SHIFT 6 -#define PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_MASK 0x00000FC0U +#define PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_DEFVAL 0x00000104 +#define PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_SHIFT 6 +#define PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_MASK 0x00000FC0U -/*TRUE specifies upstream-facing port. FALSE specifies downstream-facing port.; EP=0x0001; RP=0x0000*/ +/* +* TRUE specifies upstream-facing port. FALSE specifies downstream-facing p + * ort.; EP=0x0001; RP=0x0000 +*/ #undef PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_DEFVAL #undef PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_SHIFT #undef PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_MASK -#define PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_DEFVAL 0x000000F0 -#define PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_SHIFT 6 -#define PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_MASK 0x00000040U +#define PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_DEFVAL 0x000000F0 +#define PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_SHIFT 6 +#define PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_MASK 0x00000040U -/*Enable the routing of message TLPs to the user through the TRN RX interface. A bit value of 1 enables routing of the message - LP to the user. Messages are always decoded by the message decoder. Bit 0 - ERR COR, Bit 1 - ERR NONFATAL, Bit 2 - ERR FATAL, - Bit 3 - INTA Bit 4 - INTB, Bit 5 - INTC, Bit 6 - INTD, Bit 7 PM_PME, Bit 8 - PME_TO_ACK, Bit 9 - unlock, Bit 10 PME_Turn_Off; - EP=0x0000; RP=0x07FF*/ +/* +* Enable the routing of message TLPs to the user through the TRN RX interf + * ace. A bit value of 1 enables routing of the message TLP to the user. Me + * ssages are always decoded by the message decoder. Bit 0 - ERR COR, Bit 1 + * - ERR NONFATAL, Bit 2 - ERR FATAL, Bit 3 - INTA Bit 4 - INTB, Bit 5 - I + * NTC, Bit 6 - INTD, Bit 7 PM_PME, Bit 8 - PME_TO_ACK, Bit 9 - unlock, Bit + * 10 PME_Turn_Off; EP=0x0000; RP=0x07FF +*/ #undef PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_DEFVAL #undef PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_SHIFT #undef PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_MASK -#define PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_DEFVAL 0x00000000 -#define PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_SHIFT 5 -#define PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_MASK 0x0000FFE0U +#define PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_DEFVAL 0x00000000 +#define PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_SHIFT 5 +#define PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_MASK 0x0000FFE0U -/*Disable BAR filtering. Does not change the behavior of the bar hit outputs; EP=0x0000; RP=0x0001*/ +/* +* Disable BAR filtering. Does not change the behavior of the bar hit outpu + * ts; EP=0x0000; RP=0x0001 +*/ #undef PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_DEFVAL #undef PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_SHIFT #undef PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_MASK -#define PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_DEFVAL 0x00000000 -#define PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_SHIFT 1 -#define PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_MASK 0x00000002U +#define PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_DEFVAL 0x00000000 +#define PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_SHIFT 1 +#define PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_MASK 0x00000002U -/*Link Bandwidth notification capability. Indicates support for the link bandwidth notification status and interrupt mechanism. - Required for Root.; EP=0x0000; RP=0x0001*/ +/* +* Link Bandwidth notification capability. Indicates support for the link b + * andwidth notification status and interrupt mechanism. Required for Root. + * ; EP=0x0000; RP=0x0001 +*/ #undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_DEFVAL #undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_SHIFT #undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_MASK -#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_DEFVAL 0x000009FF -#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_SHIFT 9 -#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_MASK 0x00000200U +#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_DEFVAL 0x000009FF +#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_SHIFT 9 +#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_MASK 0x00000200U -/*Sets the ASPM Optionality Compliance bit, to comply with the 2.1 ASPM Optionality ECN. Transferred to the Link Capabilities r - gister.; EP=0x0001; RP=0x0001*/ +/* +* Sets the ASPM Optionality Compliance bit, to comply with the 2.1 ASPM Op + * tionality ECN. Transferred to the Link Capabilities register.; EP=0x0001 + * ; RP=0x0001 +*/ #undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_DEFVAL #undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_SHIFT #undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_MASK -#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_DEFVAL 0x000009FF -#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_SHIFT 14 -#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_MASK 0x00004000U +#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_DEFVAL 0x000009FF +#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_SHIFT 14 +#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_MASK 0x00004000U -/*Enables the Replay Timer to use the user-defined LL_REPLAY_TIMEOUT value (or combined with the built-in value, depending on L - _REPLAY_TIMEOUT_FUNC). If FALSE, the built-in value is used.; EP=0x0000; RP=0x0000*/ +/* +* Enables the Replay Timer to use the user-defined LL_REPLAY_TIMEOUT value + * (or combined with the built-in value, depending on LL_REPLAY_TIMEOUT_FU + * NC). If FALSE, the built-in value is used.; EP=0x0000; RP=0x0000 +*/ #undef PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_DEFVAL #undef PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_SHIFT #undef PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_MASK -#define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_DEFVAL 0x00000000 -#define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_SHIFT 15 -#define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_MASK 0x00008000U +#define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_DEFVAL 0x00000000 +#define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_SHIFT 15 +#define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_MASK 0x00008000U -/*Sets a user-defined timeout for the Replay Timer to force cause the retransmission of unacknowledged TLPs; refer to LL_REPLAY - TIMEOUT_EN and LL_REPLAY_TIMEOUT_FUNC to see how this value is used. The unit for this attribute is in symbol times, which is - 4ns at GEN1 speeds and 2ns at GEN2.; EP=0x0000; RP=0x0000*/ +/* +* Sets a user-defined timeout for the Replay Timer to force cause the retr + * ansmission of unacknowledged TLPs; refer to LL_REPLAY_TIMEOUT_EN and LL_ + * REPLAY_TIMEOUT_FUNC to see how this value is used. The unit for this att + * ribute is in symbol times, which is 4ns at GEN1 speeds and 2ns at GEN2.; + * EP=0x0000; RP=0x0000 +*/ #undef PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_DEFVAL #undef PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_SHIFT #undef PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_MASK -#define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_DEFVAL 0x00000000 -#define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_SHIFT 0 -#define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_MASK 0x00007FFFU +#define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_DEFVAL 0x00000000 +#define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_SHIFT 0 +#define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_MASK 0x00007FFFU -/*Device ID for the the PCIe Cap Structure Device ID field*/ +/* +* Device ID for the the PCIe Cap Structure Device ID field +*/ #undef PCIE_ATTRIB_ID_CFG_DEV_ID_DEFVAL #undef PCIE_ATTRIB_ID_CFG_DEV_ID_SHIFT #undef PCIE_ATTRIB_ID_CFG_DEV_ID_MASK -#define PCIE_ATTRIB_ID_CFG_DEV_ID_DEFVAL 0x10EE7024 -#define PCIE_ATTRIB_ID_CFG_DEV_ID_SHIFT 0 -#define PCIE_ATTRIB_ID_CFG_DEV_ID_MASK 0x0000FFFFU +#define PCIE_ATTRIB_ID_CFG_DEV_ID_DEFVAL 0x10EE7024 +#define PCIE_ATTRIB_ID_CFG_DEV_ID_SHIFT 0 +#define PCIE_ATTRIB_ID_CFG_DEV_ID_MASK 0x0000FFFFU -/*Vendor ID for the PCIe Cap Structure Vendor ID field*/ +/* +* Vendor ID for the PCIe Cap Structure Vendor ID field +*/ #undef PCIE_ATTRIB_ID_CFG_VEND_ID_DEFVAL #undef PCIE_ATTRIB_ID_CFG_VEND_ID_SHIFT #undef PCIE_ATTRIB_ID_CFG_VEND_ID_MASK -#define PCIE_ATTRIB_ID_CFG_VEND_ID_DEFVAL 0x10EE7024 -#define PCIE_ATTRIB_ID_CFG_VEND_ID_SHIFT 16 -#define PCIE_ATTRIB_ID_CFG_VEND_ID_MASK 0xFFFF0000U +#define PCIE_ATTRIB_ID_CFG_VEND_ID_DEFVAL 0x10EE7024 +#define PCIE_ATTRIB_ID_CFG_VEND_ID_SHIFT 16 +#define PCIE_ATTRIB_ID_CFG_VEND_ID_MASK 0xFFFF0000U -/*Subsystem ID for the the PCIe Cap Structure Subsystem ID field*/ +/* +* Subsystem ID for the the PCIe Cap Structure Subsystem ID field +*/ #undef PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_DEFVAL #undef PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_SHIFT #undef PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_MASK -#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_DEFVAL 0x10EE0007 -#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_SHIFT 0 -#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_MASK 0x0000FFFFU +#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_DEFVAL 0x10EE0007 +#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_SHIFT 0 +#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_MASK 0x0000FFFFU -/*Subsystem Vendor ID for the PCIe Cap Structure Subsystem Vendor ID field*/ +/* +* Subsystem Vendor ID for the PCIe Cap Structure Subsystem Vendor ID field +*/ #undef PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_DEFVAL #undef PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_SHIFT #undef PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_MASK -#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_DEFVAL 0x10EE0007 -#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_SHIFT 16 -#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_MASK 0xFFFF0000U +#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_DEFVAL 0x10EE0007 +#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_SHIFT 16 +#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_MASK 0xFFFF0000U -/*Revision ID for the the PCIe Cap Structure*/ +/* +* Revision ID for the the PCIe Cap Structure +*/ #undef PCIE_ATTRIB_REV_ID_CFG_REV_ID_DEFVAL #undef PCIE_ATTRIB_REV_ID_CFG_REV_ID_SHIFT #undef PCIE_ATTRIB_REV_ID_CFG_REV_ID_MASK -#define PCIE_ATTRIB_REV_ID_CFG_REV_ID_DEFVAL -#define PCIE_ATTRIB_REV_ID_CFG_REV_ID_SHIFT 0 -#define PCIE_ATTRIB_REV_ID_CFG_REV_ID_MASK 0x000000FFU +#define PCIE_ATTRIB_REV_ID_CFG_REV_ID_DEFVAL +#define PCIE_ATTRIB_REV_ID_CFG_REV_ID_SHIFT 0 +#define PCIE_ATTRIB_REV_ID_CFG_REV_ID_MASK 0x000000FFU -/*Code identifying basic function, subclass and applicable programming interface. Transferred to the Class Code register.; EP=0 - 8000; RP=0x8000*/ +/* +* Code identifying basic function, subclass and applicable programming int + * erface. Transferred to the Class Code register.; EP=0x8000; RP=0x8000 +*/ #undef PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_DEFVAL #undef PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_SHIFT #undef PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_MASK -#define PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_DEFVAL -#define PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_SHIFT 0 -#define PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_MASK 0x0000FFFFU +#define PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_DEFVAL +#define PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_SHIFT 0 +#define PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_MASK 0x0000FFFFU -/*Code identifying basic function, subclass and applicable programming interface. Transferred to the Class Code register.; EP=0 - 0005; RP=0x0006*/ +/* +* Code identifying basic function, subclass and applicable programming int + * erface. Transferred to the Class Code register.; EP=0x0005; RP=0x0006 +*/ #undef PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_DEFVAL #undef PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_SHIFT #undef PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_MASK -#define PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_DEFVAL 0x00000905 -#define PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_SHIFT 0 -#define PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_MASK 0x000000FFU +#define PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_DEFVAL 0x00000905 +#define PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_SHIFT 0 +#define PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_MASK 0x000000FFU -/*INTX Interrupt Generation Capable. If FALSE, this will cause Command[10] to be hardwired to 0.; EP=0x0001; RP=0x0001*/ +/* +* INTX Interrupt Generation Capable. If FALSE, this will cause Command[10] + * to be hardwired to 0.; EP=0x0001; RP=0x0001 +*/ #undef PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_DEFVAL #undef PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_SHIFT #undef PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_MASK -#define PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_DEFVAL 0x00000905 -#define PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_SHIFT 8 -#define PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_MASK 0x00000100U +#define PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_DEFVAL 0x00000905 +#define PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_SHIFT 8 +#define PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_MASK 0x00000100U -/*Indicates that the AER structures exists. If this is FALSE, then the AER structure cannot be accessed via either the link or - he management port, and AER will be considered to not be present for error management tasks (such as what types of error mess - ges are sent if an error is detected).; EP=0x0001; RP=0x0001*/ +/* +* Indicates that the AER structures exists. If this is FALSE, then the AER + * structure cannot be accessed via either the link or the management port + * , and AER will be considered to not be present for error management task + * s (such as what types of error messages are sent if an error is detected + * ).; EP=0x0001; RP=0x0001 +*/ #undef PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_DEFVAL #undef PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_SHIFT #undef PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_MASK -#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_DEFVAL 0x00001000 -#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_SHIFT 12 -#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_MASK 0x00001000U +#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_DEFVAL 0x00001000 +#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_SHIFT 12 +#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_MASK 0x00001000U -/*Indicates that the AER structures exists. If this is FALSE, then the AER structure cannot be accessed via either the link or - he management port, and AER will be considered to not be present for error management tasks (such as what types of error mess - ges are sent if an error is detected).; EP=0x0001; RP=0x0001*/ +/* +* Indicates that the AER structures exists. If this is FALSE, then the AER + * structure cannot be accessed via either the link or the management port + * , and AER will be considered to not be present for error management task + * s (such as what types of error messages are sent if an error is detected + * ).; EP=0x0001; RP=0x0001 +*/ #undef PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_DEFVAL #undef PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_SHIFT #undef PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_MASK -#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_DEFVAL 0x00001000 -#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_SHIFT 12 -#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_MASK 0x00001000U +#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_DEFVAL 0x00001000 +#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_SHIFT 12 +#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_MASK 0x00001000U -/*VSEC's Next Capability Offset pointer to the next item in the capabilities list, or 000h if this is the final capability.; EP - 0x0140; RP=0x0140*/ +/* +* VSEC's Next Capability Offset pointer to the next item in the capabiliti + * es list, or 000h if this is the final capability.; EP=0x0140; RP=0x0140 +*/ #undef PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_DEFVAL #undef PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_SHIFT #undef PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_MASK -#define PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_DEFVAL 0x00002281 -#define PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_SHIFT 1 -#define PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_MASK 0x00001FFEU +#define PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_DEFVAL 0x00002281 +#define PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_SHIFT 1 +#define PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_MASK 0x00001FFEU -/*CRS SW Visibility. Indicates RC can return CRS to SW. Transferred to the Root Capabilities register.; EP=0x0000; RP=0x0000*/ +/* +* CRS SW Visibility. Indicates RC can return CRS to SW. Transferred to the + * Root Capabilities register.; EP=0x0000; RP=0x0000 +*/ #undef PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_DEFVAL #undef PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_SHIFT #undef PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_MASK -#define PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_DEFVAL 0x00000000 -#define PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_SHIFT 5 -#define PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_MASK 0x00000020U +#define PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_DEFVAL 0x00000000 +#define PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_SHIFT 5 +#define PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_MASK 0x00000020U -/*Indicates that the MSIX structures exists. If this is FALSE, then the MSIX structure cannot be accessed via either the link o - the management port.; EP=0x0001; RP=0x0000*/ +/* +* Indicates that the MSIX structures exists. If this is FALSE, then the MS + * IX structure cannot be accessed via either the link or the management po + * rt.; EP=0x0001; RP=0x0000 +*/ #undef PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_DEFVAL #undef PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_SHIFT #undef PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_MASK -#define PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_DEFVAL 0x00000100 -#define PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_SHIFT 8 -#define PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_MASK 0x00000100U +#define PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_DEFVAL 0x00000100 +#define PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_SHIFT 8 +#define PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_MASK 0x00000100U -/*MSI-X Table Size. This value is transferred to the MSI-X Message Control[10:0] field. Set to 0 if MSI-X is not enabled. Note - hat the core does not implement the table; that must be implemented in user logic.; EP=0x0003; RP=0x0000*/ +/* +* MSI-X Table Size. This value is transferred to the MSI-X Message Control + * [10:0] field. Set to 0 if MSI-X is not enabled. Note that the core does + * not implement the table; that must be implemented in user logic.; EP=0x0 + * 003; RP=0x0000 +*/ #undef PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_DEFVAL #undef PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_SHIFT #undef PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_MASK -#define PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_DEFVAL -#define PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_SHIFT 0 -#define PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_MASK 0x000007FFU +#define PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_DEFVAL +#define PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_SHIFT 0 +#define PCIE_ATTRIB_ATTR_48_ATTR_MSIX_CAP_TABLE_SIZE_MASK 0x000007FFU -/*MSI-X Table Offset. This value is transferred to the MSI-X Table Offset field. Set to 0 if MSI-X is not enabled.; EP=0x0001; - P=0x0000*/ +/* +* MSI-X Table Offset. This value is transferred to the MSI-X Table Offset + * field. Set to 0 if MSI-X is not enabled.; EP=0x0001; RP=0x0000 +*/ #undef PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_DEFVAL #undef PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_SHIFT #undef PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_MASK -#define PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_DEFVAL -#define PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_SHIFT 0 -#define PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_MASK 0x0000FFFFU +#define PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_DEFVAL +#define PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_SHIFT 0 +#define PCIE_ATTRIB_ATTR_46_ATTR_MSIX_CAP_TABLE_OFFSET_MASK 0x0000FFFFU -/*MSI-X Table Offset. This value is transferred to the MSI-X Table Offset field. Set to 0 if MSI-X is not enabled.; EP=0x0000; - P=0x0000*/ +/* +* MSI-X Table Offset. This value is transferred to the MSI-X Table Offset + * field. Set to 0 if MSI-X is not enabled.; EP=0x0000; RP=0x0000 +*/ #undef PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_DEFVAL #undef PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_SHIFT #undef PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_MASK -#define PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_DEFVAL -#define PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_SHIFT 0 -#define PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_MASK 0x00001FFFU +#define PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_DEFVAL +#define PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_SHIFT 0 +#define PCIE_ATTRIB_ATTR_47_ATTR_MSIX_CAP_TABLE_OFFSET_MASK 0x00001FFFU -/*MSI-X Pending Bit Array Offset This value is transferred to the MSI-X PBA Offset field. Set to 0 if MSI-X is not enabled.; EP - 0x0001; RP=0x0000*/ +/* +* MSI-X Pending Bit Array Offset This value is transferred to the MSI-X PB + * A Offset field. Set to 0 if MSI-X is not enabled.; EP=0x0001; RP=0x0000 +*/ #undef PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_DEFVAL #undef PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_SHIFT #undef PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_MASK -#define PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_DEFVAL -#define PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_SHIFT 0 -#define PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_MASK 0x0000FFFFU +#define PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_DEFVAL +#define PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_SHIFT 0 +#define PCIE_ATTRIB_ATTR_44_ATTR_MSIX_CAP_PBA_OFFSET_MASK 0x0000FFFFU -/*MSI-X Pending Bit Array Offset This value is transferred to the MSI-X PBA Offset field. Set to 0 if MSI-X is not enabled.; EP - 0x1000; RP=0x0000*/ +/* +* MSI-X Pending Bit Array Offset This value is transferred to the MSI-X PB + * A Offset field. Set to 0 if MSI-X is not enabled.; EP=0x1000; RP=0x0000 +*/ #undef PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_DEFVAL #undef PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_SHIFT #undef PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_MASK -#define PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_DEFVAL 0x00008000 -#define PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_SHIFT 3 -#define PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_MASK 0x0000FFF8U +#define PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_DEFVAL 0x00008000 +#define PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_SHIFT 3 +#define PCIE_ATTRIB_ATTR_45_ATTR_MSIX_CAP_PBA_OFFSET_MASK 0x0000FFF8U -/*DT837748 Enable*/ +/* +* DT837748 Enable +*/ #undef PCIE_ATTRIB_CB_CB1_DEFVAL #undef PCIE_ATTRIB_CB_CB1_SHIFT #undef PCIE_ATTRIB_CB_CB1_MASK -#define PCIE_ATTRIB_CB_CB1_DEFVAL 0x00000001 -#define PCIE_ATTRIB_CB_CB1_SHIFT 1 -#define PCIE_ATTRIB_CB_CB1_MASK 0x00000002U +#define PCIE_ATTRIB_CB_CB1_DEFVAL 0x00000001 +#define PCIE_ATTRIB_CB_CB1_SHIFT 1 +#define PCIE_ATTRIB_CB_CB1_MASK 0x00000002U -/*Active State PM Support. Indicates the level of active state power management supported by the selected PCI Express Link, enc - ded as follows: 0 Reserved, 1 L0s entry supported, 2 Reserved, 3 L0s and L1 entry supported.; EP=0x0001; RP=0x0001*/ +/* +* Active State PM Support. Indicates the level of active state power manag + * ement supported by the selected PCI Express Link, encoded as follows: 0 + * Reserved, 1 L0s entry supported, 2 Reserved, 3 L0s and L1 entry supporte + * d.; EP=0x0001; RP=0x0001 +*/ #undef PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_DEFVAL #undef PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_SHIFT #undef PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_MASK -#define PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_DEFVAL 0x00001FFD -#define PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_SHIFT 12 -#define PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_MASK 0x00003000U +#define PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_DEFVAL 0x00001FFD +#define PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_SHIFT 12 +#define PCIE_ATTRIB_ATTR_35_ATTR_LINK_CAP_ASPM_SUPPORT_MASK 0x00003000U -/*PCIE control block level reset*/ +/* +* PCIE control block level reset +*/ #undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL #undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT #undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK -#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL 0x000F9FFE -#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT 17 -#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK 0x00020000U +#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT 17 +#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK 0x00020000U -/*Status Read value of PLL Lock*/ +/* +* Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW] +*/ +#undef GPIO_MASK_DATA_1_LSW_MASK_1_LSW_DEFVAL +#undef GPIO_MASK_DATA_1_LSW_MASK_1_LSW_SHIFT +#undef GPIO_MASK_DATA_1_LSW_MASK_1_LSW_MASK +#define GPIO_MASK_DATA_1_LSW_MASK_1_LSW_DEFVAL 0x00000000 +#define GPIO_MASK_DATA_1_LSW_MASK_1_LSW_SHIFT 16 +#define GPIO_MASK_DATA_1_LSW_MASK_1_LSW_MASK 0xFFFF0000U + +/* +* Operation is the same as MASK_DATA_0_LSW[DATA_0_LSW] +*/ +#undef GPIO_MASK_DATA_1_LSW_DATA_1_LSW_DEFVAL +#undef GPIO_MASK_DATA_1_LSW_DATA_1_LSW_SHIFT +#undef GPIO_MASK_DATA_1_LSW_DATA_1_LSW_MASK +#define GPIO_MASK_DATA_1_LSW_DATA_1_LSW_DEFVAL 0x00000000 +#define GPIO_MASK_DATA_1_LSW_DATA_1_LSW_SHIFT 0 +#define GPIO_MASK_DATA_1_LSW_DATA_1_LSW_MASK 0x0000FFFFU + +/* +* Status Read value of PLL Lock +*/ #undef SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL #undef SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT #undef SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK -#define SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL 0x00000001 -#define SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT 4 -#define SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK 0x00000010U +#define SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL 0x00000001 +#define SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT 4 +#define SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK 0x00000010U #define SERDES_L0_PLL_STATUS_READ_1_OFFSET 0XFD4023E4 -/*Status Read value of PLL Lock*/ +/* +* Status Read value of PLL Lock +*/ #undef SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL #undef SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT #undef SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK -#define SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL 0x00000001 -#define SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT 4 -#define SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK 0x00000010U +#define SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL 0x00000001 +#define SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT 4 +#define SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK 0x00000010U #define SERDES_L1_PLL_STATUS_READ_1_OFFSET 0XFD4063E4 -/*Status Read value of PLL Lock*/ +/* +* Status Read value of PLL Lock +*/ #undef SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL #undef SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT #undef SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK -#define SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL 0x00000001 -#define SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT 4 -#define SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK 0x00000010U +#define SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL 0x00000001 +#define SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT 4 +#define SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK 0x00000010U #define SERDES_L2_PLL_STATUS_READ_1_OFFSET 0XFD40A3E4 -/*Status Read value of PLL Lock*/ +/* +* Status Read value of PLL Lock +*/ #undef SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL #undef SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT #undef SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK -#define SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL 0x00000001 -#define SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT 4 -#define SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK 0x00000010U +#define SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL 0x00000001 +#define SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT 4 +#define SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK 0x00000010U #define SERDES_L3_PLL_STATUS_READ_1_OFFSET 0XFD40E3E4 -/*CIBGMN: COMINIT Burst Gap Minimum.*/ +/* +* CIBGMN: COMINIT Burst Gap Minimum. +*/ #undef SATA_AHCI_VENDOR_PP2C_CIBGMN_DEFVAL #undef SATA_AHCI_VENDOR_PP2C_CIBGMN_SHIFT #undef SATA_AHCI_VENDOR_PP2C_CIBGMN_MASK -#define SATA_AHCI_VENDOR_PP2C_CIBGMN_DEFVAL 0x28184D1B -#define SATA_AHCI_VENDOR_PP2C_CIBGMN_SHIFT 0 -#define SATA_AHCI_VENDOR_PP2C_CIBGMN_MASK 0x000000FFU +#define SATA_AHCI_VENDOR_PP2C_CIBGMN_DEFVAL 0x28184D1B +#define SATA_AHCI_VENDOR_PP2C_CIBGMN_SHIFT 0 +#define SATA_AHCI_VENDOR_PP2C_CIBGMN_MASK 0x000000FFU -/*CIBGMX: COMINIT Burst Gap Maximum.*/ +/* +* CIBGMX: COMINIT Burst Gap Maximum. +*/ #undef SATA_AHCI_VENDOR_PP2C_CIBGMX_DEFVAL #undef SATA_AHCI_VENDOR_PP2C_CIBGMX_SHIFT #undef SATA_AHCI_VENDOR_PP2C_CIBGMX_MASK -#define SATA_AHCI_VENDOR_PP2C_CIBGMX_DEFVAL 0x28184D1B -#define SATA_AHCI_VENDOR_PP2C_CIBGMX_SHIFT 8 -#define SATA_AHCI_VENDOR_PP2C_CIBGMX_MASK 0x0000FF00U +#define SATA_AHCI_VENDOR_PP2C_CIBGMX_DEFVAL 0x28184D1B +#define SATA_AHCI_VENDOR_PP2C_CIBGMX_SHIFT 8 +#define SATA_AHCI_VENDOR_PP2C_CIBGMX_MASK 0x0000FF00U -/*CIBGN: COMINIT Burst Gap Nominal.*/ +/* +* CIBGN: COMINIT Burst Gap Nominal. +*/ #undef SATA_AHCI_VENDOR_PP2C_CIBGN_DEFVAL #undef SATA_AHCI_VENDOR_PP2C_CIBGN_SHIFT #undef SATA_AHCI_VENDOR_PP2C_CIBGN_MASK -#define SATA_AHCI_VENDOR_PP2C_CIBGN_DEFVAL 0x28184D1B -#define SATA_AHCI_VENDOR_PP2C_CIBGN_SHIFT 16 -#define SATA_AHCI_VENDOR_PP2C_CIBGN_MASK 0x00FF0000U +#define SATA_AHCI_VENDOR_PP2C_CIBGN_DEFVAL 0x28184D1B +#define SATA_AHCI_VENDOR_PP2C_CIBGN_SHIFT 16 +#define SATA_AHCI_VENDOR_PP2C_CIBGN_MASK 0x00FF0000U -/*CINMP: COMINIT Negate Minimum Period.*/ +/* +* CINMP: COMINIT Negate Minimum Period. +*/ #undef SATA_AHCI_VENDOR_PP2C_CINMP_DEFVAL #undef SATA_AHCI_VENDOR_PP2C_CINMP_SHIFT #undef SATA_AHCI_VENDOR_PP2C_CINMP_MASK -#define SATA_AHCI_VENDOR_PP2C_CINMP_DEFVAL 0x28184D1B -#define SATA_AHCI_VENDOR_PP2C_CINMP_SHIFT 24 -#define SATA_AHCI_VENDOR_PP2C_CINMP_MASK 0xFF000000U +#define SATA_AHCI_VENDOR_PP2C_CINMP_DEFVAL 0x28184D1B +#define SATA_AHCI_VENDOR_PP2C_CINMP_SHIFT 24 +#define SATA_AHCI_VENDOR_PP2C_CINMP_MASK 0xFF000000U -/*CWBGMN: COMWAKE Burst Gap Minimum.*/ +/* +* CWBGMN: COMWAKE Burst Gap Minimum. +*/ #undef SATA_AHCI_VENDOR_PP3C_CWBGMN_DEFVAL #undef SATA_AHCI_VENDOR_PP3C_CWBGMN_SHIFT #undef SATA_AHCI_VENDOR_PP3C_CWBGMN_MASK -#define SATA_AHCI_VENDOR_PP3C_CWBGMN_DEFVAL 0x0E081906 -#define SATA_AHCI_VENDOR_PP3C_CWBGMN_SHIFT 0 -#define SATA_AHCI_VENDOR_PP3C_CWBGMN_MASK 0x000000FFU +#define SATA_AHCI_VENDOR_PP3C_CWBGMN_DEFVAL 0x0E081906 +#define SATA_AHCI_VENDOR_PP3C_CWBGMN_SHIFT 0 +#define SATA_AHCI_VENDOR_PP3C_CWBGMN_MASK 0x000000FFU -/*CWBGMX: COMWAKE Burst Gap Maximum.*/ +/* +* CWBGMX: COMWAKE Burst Gap Maximum. +*/ #undef SATA_AHCI_VENDOR_PP3C_CWBGMX_DEFVAL #undef SATA_AHCI_VENDOR_PP3C_CWBGMX_SHIFT #undef SATA_AHCI_VENDOR_PP3C_CWBGMX_MASK -#define SATA_AHCI_VENDOR_PP3C_CWBGMX_DEFVAL 0x0E081906 -#define SATA_AHCI_VENDOR_PP3C_CWBGMX_SHIFT 8 -#define SATA_AHCI_VENDOR_PP3C_CWBGMX_MASK 0x0000FF00U +#define SATA_AHCI_VENDOR_PP3C_CWBGMX_DEFVAL 0x0E081906 +#define SATA_AHCI_VENDOR_PP3C_CWBGMX_SHIFT 8 +#define SATA_AHCI_VENDOR_PP3C_CWBGMX_MASK 0x0000FF00U -/*CWBGN: COMWAKE Burst Gap Nominal.*/ +/* +* CWBGN: COMWAKE Burst Gap Nominal. +*/ #undef SATA_AHCI_VENDOR_PP3C_CWBGN_DEFVAL #undef SATA_AHCI_VENDOR_PP3C_CWBGN_SHIFT #undef SATA_AHCI_VENDOR_PP3C_CWBGN_MASK -#define SATA_AHCI_VENDOR_PP3C_CWBGN_DEFVAL 0x0E081906 -#define SATA_AHCI_VENDOR_PP3C_CWBGN_SHIFT 16 -#define SATA_AHCI_VENDOR_PP3C_CWBGN_MASK 0x00FF0000U +#define SATA_AHCI_VENDOR_PP3C_CWBGN_DEFVAL 0x0E081906 +#define SATA_AHCI_VENDOR_PP3C_CWBGN_SHIFT 16 +#define SATA_AHCI_VENDOR_PP3C_CWBGN_MASK 0x00FF0000U -/*CWNMP: COMWAKE Negate Minimum Period.*/ +/* +* CWNMP: COMWAKE Negate Minimum Period. +*/ #undef SATA_AHCI_VENDOR_PP3C_CWNMP_DEFVAL #undef SATA_AHCI_VENDOR_PP3C_CWNMP_SHIFT #undef SATA_AHCI_VENDOR_PP3C_CWNMP_MASK -#define SATA_AHCI_VENDOR_PP3C_CWNMP_DEFVAL 0x0E081906 -#define SATA_AHCI_VENDOR_PP3C_CWNMP_SHIFT 24 -#define SATA_AHCI_VENDOR_PP3C_CWNMP_MASK 0xFF000000U +#define SATA_AHCI_VENDOR_PP3C_CWNMP_DEFVAL 0x0E081906 +#define SATA_AHCI_VENDOR_PP3C_CWNMP_SHIFT 24 +#define SATA_AHCI_VENDOR_PP3C_CWNMP_MASK 0xFF000000U -/*BMX: COM Burst Maximum.*/ +/* +* BMX: COM Burst Maximum. +*/ #undef SATA_AHCI_VENDOR_PP4C_BMX_DEFVAL #undef SATA_AHCI_VENDOR_PP4C_BMX_SHIFT #undef SATA_AHCI_VENDOR_PP4C_BMX_MASK -#define SATA_AHCI_VENDOR_PP4C_BMX_DEFVAL 0x064A0813 -#define SATA_AHCI_VENDOR_PP4C_BMX_SHIFT 0 -#define SATA_AHCI_VENDOR_PP4C_BMX_MASK 0x000000FFU +#define SATA_AHCI_VENDOR_PP4C_BMX_DEFVAL 0x064A0813 +#define SATA_AHCI_VENDOR_PP4C_BMX_SHIFT 0 +#define SATA_AHCI_VENDOR_PP4C_BMX_MASK 0x000000FFU -/*BNM: COM Burst Nominal.*/ +/* +* BNM: COM Burst Nominal. +*/ #undef SATA_AHCI_VENDOR_PP4C_BNM_DEFVAL #undef SATA_AHCI_VENDOR_PP4C_BNM_SHIFT #undef SATA_AHCI_VENDOR_PP4C_BNM_MASK -#define SATA_AHCI_VENDOR_PP4C_BNM_DEFVAL 0x064A0813 -#define SATA_AHCI_VENDOR_PP4C_BNM_SHIFT 8 -#define SATA_AHCI_VENDOR_PP4C_BNM_MASK 0x0000FF00U +#define SATA_AHCI_VENDOR_PP4C_BNM_DEFVAL 0x064A0813 +#define SATA_AHCI_VENDOR_PP4C_BNM_SHIFT 8 +#define SATA_AHCI_VENDOR_PP4C_BNM_MASK 0x0000FF00U -/*SFD: Signal Failure Detection, if the signal detection de-asserts for a time greater than this then the OOB detector will det - rmine this is a line idle and cause the PhyInit state machine to exit the Phy Ready State. A value of zero disables the Signa - Failure Detector. The value is based on the OOB Detector Clock typically (PMCLK Clock Period) * SFD giving a nominal time of - 500ns based on a 150MHz PMCLK.*/ +/* +* SFD: Signal Failure Detection, if the signal detection de-asserts for a + * time greater than this then the OOB detector will determine this is a li + * ne idle and cause the PhyInit state machine to exit the Phy Ready State. + * A value of zero disables the Signal Failure Detector. The value is base + * d on the OOB Detector Clock typically (PMCLK Clock Period) * SFD giving + * a nominal time of 500ns based on a 150MHz PMCLK. +*/ #undef SATA_AHCI_VENDOR_PP4C_SFD_DEFVAL #undef SATA_AHCI_VENDOR_PP4C_SFD_SHIFT #undef SATA_AHCI_VENDOR_PP4C_SFD_MASK -#define SATA_AHCI_VENDOR_PP4C_SFD_DEFVAL 0x064A0813 -#define SATA_AHCI_VENDOR_PP4C_SFD_SHIFT 16 -#define SATA_AHCI_VENDOR_PP4C_SFD_MASK 0x00FF0000U +#define SATA_AHCI_VENDOR_PP4C_SFD_DEFVAL 0x064A0813 +#define SATA_AHCI_VENDOR_PP4C_SFD_SHIFT 16 +#define SATA_AHCI_VENDOR_PP4C_SFD_MASK 0x00FF0000U -/*PTST: Partial to Slumber timer value, specific delay the controller should apply while in partial before entering slumber. Th - value is bases on the system clock divided by 128, total delay = (Sys Clock Period) * PTST * 128*/ +/* +* PTST: Partial to Slumber timer value, specific delay the controller shou + * ld apply while in partial before entering slumber. The value is bases on + * the system clock divided by 128, total delay = (Sys Clock Period) * PTS + * T * 128 +*/ #undef SATA_AHCI_VENDOR_PP4C_PTST_DEFVAL #undef SATA_AHCI_VENDOR_PP4C_PTST_SHIFT #undef SATA_AHCI_VENDOR_PP4C_PTST_MASK -#define SATA_AHCI_VENDOR_PP4C_PTST_DEFVAL 0x064A0813 -#define SATA_AHCI_VENDOR_PP4C_PTST_SHIFT 24 -#define SATA_AHCI_VENDOR_PP4C_PTST_MASK 0xFF000000U +#define SATA_AHCI_VENDOR_PP4C_PTST_DEFVAL 0x064A0813 +#define SATA_AHCI_VENDOR_PP4C_PTST_SHIFT 24 +#define SATA_AHCI_VENDOR_PP4C_PTST_MASK 0xFF000000U -/*RIT: Retry Interval Timer. The calculated value divided by two, the lower digit of precision is not needed.*/ +/* +* RIT: Retry Interval Timer. The calculated value divided by two, the lowe + * r digit of precision is not needed. +*/ #undef SATA_AHCI_VENDOR_PP5C_RIT_DEFVAL #undef SATA_AHCI_VENDOR_PP5C_RIT_SHIFT #undef SATA_AHCI_VENDOR_PP5C_RIT_MASK -#define SATA_AHCI_VENDOR_PP5C_RIT_DEFVAL 0x3FFC96A4 -#define SATA_AHCI_VENDOR_PP5C_RIT_SHIFT 0 -#define SATA_AHCI_VENDOR_PP5C_RIT_MASK 0x000FFFFFU +#define SATA_AHCI_VENDOR_PP5C_RIT_DEFVAL 0x3FFC96A4 +#define SATA_AHCI_VENDOR_PP5C_RIT_SHIFT 0 +#define SATA_AHCI_VENDOR_PP5C_RIT_MASK 0x000FFFFFU -/*RCT: Rate Change Timer, a value based on the 54.2us for which a SATA device will transmit at a fixed rate ALIGNp after OOB ha - completed, for a fast SERDES it is suggested that this value be 54.2us / 4*/ +/* +* RCT: Rate Change Timer, a value based on the 54.2us for which a SATA dev + * ice will transmit at a fixed rate ALIGNp after OOB has completed, for a + * fast SERDES it is suggested that this value be 54.2us / 4 +*/ #undef SATA_AHCI_VENDOR_PP5C_RCT_DEFVAL #undef SATA_AHCI_VENDOR_PP5C_RCT_SHIFT #undef SATA_AHCI_VENDOR_PP5C_RCT_MASK -#define SATA_AHCI_VENDOR_PP5C_RCT_DEFVAL 0x3FFC96A4 -#define SATA_AHCI_VENDOR_PP5C_RCT_SHIFT 20 -#define SATA_AHCI_VENDOR_PP5C_RCT_MASK 0xFFF00000U +#define SATA_AHCI_VENDOR_PP5C_RCT_DEFVAL 0x3FFC96A4 +#define SATA_AHCI_VENDOR_PP5C_RCT_SHIFT 20 +#define SATA_AHCI_VENDOR_PP5C_RCT_MASK 0xFFF00000U #undef CRL_APB_RST_LPD_TOP_OFFSET #define CRL_APB_RST_LPD_TOP_OFFSET 0XFF5E023C #undef CRL_APB_RST_LPD_IOU0_OFFSET @@ -27659,123 +36123,252 @@ #undef CRF_APB_RST_FPD_TOP_OFFSET #define CRF_APB_RST_FPD_TOP_OFFSET 0XFD1A0100 -/*USB 0 reset for control registers*/ +/* +* USB 0 reset for control registers +*/ #undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL #undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT #undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK -#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL 0x00188FDF -#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT 10 -#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK 0x00000400U +#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT 10 +#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK 0x00000400U -/*USB 0 sleep circuit reset*/ +/* +* USB 0 sleep circuit reset +*/ #undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL #undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT #undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK -#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL 0x00188FDF -#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT 8 -#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK 0x00000100U +#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT 8 +#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK 0x00000100U -/*USB 0 reset*/ +/* +* USB 0 reset +*/ #undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL #undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT #undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK -#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL 0x00188FDF -#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT 6 -#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK 0x00000040U +#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT 6 +#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK 0x00000040U -/*GEM 3 reset*/ +/* +* GEM 3 reset +*/ #undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL #undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT #undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK -#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL 0x0000000F -#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT 3 -#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK 0x00000008U +#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL 0x0000000F +#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT 3 +#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK 0x00000008U -/*Sata block level reset*/ +/* +* Sata block level reset +*/ #undef CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL #undef CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT #undef CRF_APB_RST_FPD_TOP_SATA_RESET_MASK -#define CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL 0x000F9FFE -#define CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT 1 -#define CRF_APB_RST_FPD_TOP_SATA_RESET_MASK 0x00000002U +#define CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT 1 +#define CRF_APB_RST_FPD_TOP_SATA_RESET_MASK 0x00000002U -/*PCIE config reset*/ +/* +* PCIE config reset +*/ #undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL #undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT #undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK -#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL 0x000F9FFE -#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT 19 -#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK 0x00080000U +#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT 19 +#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK 0x00080000U -/*PCIE control block level reset*/ +/* +* PCIE control block level reset +*/ #undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL #undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT #undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK -#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL 0x000F9FFE -#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT 17 -#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK 0x00020000U +#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT 17 +#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK 0x00020000U -/*PCIE bridge block level reset (AXI interface)*/ +/* +* PCIE bridge block level reset (AXI interface) +*/ #undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL #undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT #undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK -#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL 0x000F9FFE -#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT 18 -#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK 0x00040000U +#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT 18 +#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK 0x00040000U -/*Two bits per lane. When set to 11, moves the GT to power down mode. When set to 00, GT will be in active state. bits [1:0] - - ane0 Bits [3:2] - lane 1*/ +/* +* Two bits per lane. When set to 11, moves the GT to power down mode. When + * set to 00, GT will be in active state. bits [1:0] - lane0 Bits [3:2] - + * lane 1 +*/ #undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_DEFVAL #undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT #undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK -#define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_DEFVAL 0x00000000 -#define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT 0 -#define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK 0x0000000FU +#define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_DEFVAL 0x00000000 +#define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT 0 +#define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK 0x0000000FU -/*Set to '1' to hold the GT in reset. Clear to release.*/ +/* +* Set to '1' to hold the GT in reset. Clear to release. +*/ #undef DP_DP_PHY_RESET_GT_RESET_DEFVAL #undef DP_DP_PHY_RESET_GT_RESET_SHIFT #undef DP_DP_PHY_RESET_GT_RESET_MASK -#define DP_DP_PHY_RESET_GT_RESET_DEFVAL 0x00010003 -#define DP_DP_PHY_RESET_GT_RESET_SHIFT 1 -#define DP_DP_PHY_RESET_GT_RESET_MASK 0x00000002U +#define DP_DP_PHY_RESET_GT_RESET_DEFVAL 0x00010003 +#define DP_DP_PHY_RESET_GT_RESET_SHIFT 1 +#define DP_DP_PHY_RESET_GT_RESET_MASK 0x00000002U -/*Display Port block level reset (includes DPDMA)*/ +/* +* Display Port block level reset (includes DPDMA) +*/ #undef CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL #undef CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT #undef CRF_APB_RST_FPD_TOP_DP_RESET_MASK -#define CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL 0x000F9FFE -#define CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT 16 -#define CRF_APB_RST_FPD_TOP_DP_RESET_MASK 0x00010000U +#define CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT 16 +#define CRF_APB_RST_FPD_TOP_DP_RESET_MASK 0x00010000U #undef PMU_GLOBAL_REQ_PWRUP_INT_EN_OFFSET #define PMU_GLOBAL_REQ_PWRUP_INT_EN_OFFSET 0XFFD80118 #undef PMU_GLOBAL_REQ_PWRUP_TRIG_OFFSET #define PMU_GLOBAL_REQ_PWRUP_TRIG_OFFSET 0XFFD80120 -/*Power-up Request Interrupt Enable for PL*/ +/* +* Power-up Request Interrupt Enable for PL +*/ #undef PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_DEFVAL #undef PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_SHIFT #undef PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_MASK -#define PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_DEFVAL 0x00000000 -#define PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_SHIFT 23 -#define PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_MASK 0x00800000U +#define PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_DEFVAL 0x00000000 +#define PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_SHIFT 23 +#define PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_MASK 0x00800000U -/*Power-up Request Trigger for PL*/ +/* +* Power-up Request Trigger for PL +*/ #undef PMU_GLOBAL_REQ_PWRUP_TRIG_PL_DEFVAL #undef PMU_GLOBAL_REQ_PWRUP_TRIG_PL_SHIFT #undef PMU_GLOBAL_REQ_PWRUP_TRIG_PL_MASK -#define PMU_GLOBAL_REQ_PWRUP_TRIG_PL_DEFVAL 0x00000000 -#define PMU_GLOBAL_REQ_PWRUP_TRIG_PL_SHIFT 23 -#define PMU_GLOBAL_REQ_PWRUP_TRIG_PL_MASK 0x00800000U +#define PMU_GLOBAL_REQ_PWRUP_TRIG_PL_DEFVAL 0x00000000 +#define PMU_GLOBAL_REQ_PWRUP_TRIG_PL_SHIFT 23 +#define PMU_GLOBAL_REQ_PWRUP_TRIG_PL_MASK 0x00800000U -/*Power-up Request Status for PL*/ +/* +* Power-up Request Status for PL +*/ #undef PMU_GLOBAL_REQ_PWRUP_STATUS_PL_DEFVAL #undef PMU_GLOBAL_REQ_PWRUP_STATUS_PL_SHIFT #undef PMU_GLOBAL_REQ_PWRUP_STATUS_PL_MASK -#define PMU_GLOBAL_REQ_PWRUP_STATUS_PL_DEFVAL 0x00000000 -#define PMU_GLOBAL_REQ_PWRUP_STATUS_PL_SHIFT 23 -#define PMU_GLOBAL_REQ_PWRUP_STATUS_PL_MASK 0x00800000U +#define PMU_GLOBAL_REQ_PWRUP_STATUS_PL_DEFVAL 0x00000000 +#define PMU_GLOBAL_REQ_PWRUP_STATUS_PL_SHIFT 23 +#define PMU_GLOBAL_REQ_PWRUP_STATUS_PL_MASK 0x00800000U #define PMU_GLOBAL_REQ_PWRUP_STATUS_OFFSET 0XFFD80110 +#undef CRF_APB_RST_FPD_TOP_OFFSET +#define CRF_APB_RST_FPD_TOP_OFFSET 0XFD1A0100 +#undef CRL_APB_RST_LPD_TOP_OFFSET +#define CRL_APB_RST_LPD_TOP_OFFSET 0XFF5E023C +#undef FPD_SLCR_AFI_FS_OFFSET +#define FPD_SLCR_AFI_FS_OFFSET 0XFD615000 + +/* +* AF_FM0 block level reset +*/ +#undef CRF_APB_RST_FPD_TOP_AFI_FM0_RESET_DEFVAL +#undef CRF_APB_RST_FPD_TOP_AFI_FM0_RESET_SHIFT +#undef CRF_APB_RST_FPD_TOP_AFI_FM0_RESET_MASK +#define CRF_APB_RST_FPD_TOP_AFI_FM0_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_AFI_FM0_RESET_SHIFT 7 +#define CRF_APB_RST_FPD_TOP_AFI_FM0_RESET_MASK 0x00000080U + +/* +* AF_FM1 block level reset +*/ +#undef CRF_APB_RST_FPD_TOP_AFI_FM1_RESET_DEFVAL +#undef CRF_APB_RST_FPD_TOP_AFI_FM1_RESET_SHIFT +#undef CRF_APB_RST_FPD_TOP_AFI_FM1_RESET_MASK +#define CRF_APB_RST_FPD_TOP_AFI_FM1_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_AFI_FM1_RESET_SHIFT 8 +#define CRF_APB_RST_FPD_TOP_AFI_FM1_RESET_MASK 0x00000100U + +/* +* AF_FM2 block level reset +*/ +#undef CRF_APB_RST_FPD_TOP_AFI_FM2_RESET_DEFVAL +#undef CRF_APB_RST_FPD_TOP_AFI_FM2_RESET_SHIFT +#undef CRF_APB_RST_FPD_TOP_AFI_FM2_RESET_MASK +#define CRF_APB_RST_FPD_TOP_AFI_FM2_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_AFI_FM2_RESET_SHIFT 9 +#define CRF_APB_RST_FPD_TOP_AFI_FM2_RESET_MASK 0x00000200U + +/* +* AF_FM3 block level reset +*/ +#undef CRF_APB_RST_FPD_TOP_AFI_FM3_RESET_DEFVAL +#undef CRF_APB_RST_FPD_TOP_AFI_FM3_RESET_SHIFT +#undef CRF_APB_RST_FPD_TOP_AFI_FM3_RESET_MASK +#define CRF_APB_RST_FPD_TOP_AFI_FM3_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_AFI_FM3_RESET_SHIFT 10 +#define CRF_APB_RST_FPD_TOP_AFI_FM3_RESET_MASK 0x00000400U + +/* +* AF_FM4 block level reset +*/ +#undef CRF_APB_RST_FPD_TOP_AFI_FM4_RESET_DEFVAL +#undef CRF_APB_RST_FPD_TOP_AFI_FM4_RESET_SHIFT +#undef CRF_APB_RST_FPD_TOP_AFI_FM4_RESET_MASK +#define CRF_APB_RST_FPD_TOP_AFI_FM4_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_AFI_FM4_RESET_SHIFT 11 +#define CRF_APB_RST_FPD_TOP_AFI_FM4_RESET_MASK 0x00000800U + +/* +* AF_FM5 block level reset +*/ +#undef CRF_APB_RST_FPD_TOP_AFI_FM5_RESET_DEFVAL +#undef CRF_APB_RST_FPD_TOP_AFI_FM5_RESET_SHIFT +#undef CRF_APB_RST_FPD_TOP_AFI_FM5_RESET_MASK +#define CRF_APB_RST_FPD_TOP_AFI_FM5_RESET_DEFVAL 0x000F9FFE +#define CRF_APB_RST_FPD_TOP_AFI_FM5_RESET_SHIFT 12 +#define CRF_APB_RST_FPD_TOP_AFI_FM5_RESET_MASK 0x00001000U + +/* +* AFI FM 6 +*/ +#undef CRL_APB_RST_LPD_TOP_AFI_FM6_RESET_DEFVAL +#undef CRL_APB_RST_LPD_TOP_AFI_FM6_RESET_SHIFT +#undef CRL_APB_RST_LPD_TOP_AFI_FM6_RESET_MASK +#define CRL_APB_RST_LPD_TOP_AFI_FM6_RESET_DEFVAL 0x00188FDF +#define CRL_APB_RST_LPD_TOP_AFI_FM6_RESET_SHIFT 19 +#define CRL_APB_RST_LPD_TOP_AFI_FM6_RESET_MASK 0x00080000U + +/* +* Select the 32/64/128-bit data width selection for the Slave 0 00: 32-bit + * AXI data width (default) 01: 64-bit AXI data width 10: 128-bit AXI data + * width 11: reserved +*/ +#undef FPD_SLCR_AFI_FS_DW_SS0_SEL_DEFVAL +#undef FPD_SLCR_AFI_FS_DW_SS0_SEL_SHIFT +#undef FPD_SLCR_AFI_FS_DW_SS0_SEL_MASK +#define FPD_SLCR_AFI_FS_DW_SS0_SEL_DEFVAL 0x00000A00 +#define FPD_SLCR_AFI_FS_DW_SS0_SEL_SHIFT 8 +#define FPD_SLCR_AFI_FS_DW_SS0_SEL_MASK 0x00000300U + +/* +* Select the 32/64/128-bit data width selection for the Slave 1 00: 32-bit + * AXI data width (default) 01: 64-bit AXI data width 10: 128-bit AXI data + * width 11: reserved +*/ +#undef FPD_SLCR_AFI_FS_DW_SS1_SEL_DEFVAL +#undef FPD_SLCR_AFI_FS_DW_SS1_SEL_SHIFT +#undef FPD_SLCR_AFI_FS_DW_SS1_SEL_MASK +#define FPD_SLCR_AFI_FS_DW_SS1_SEL_DEFVAL 0x00000A00 +#define FPD_SLCR_AFI_FS_DW_SS1_SEL_SHIFT 10 +#define FPD_SLCR_AFI_FS_DW_SS1_SEL_MASK 0x00000C00U #undef GPIO_MASK_DATA_5_MSW_OFFSET #define GPIO_MASK_DATA_5_MSW_OFFSET 0XFF0A002C #undef GPIO_DIRM_5_OFFSET @@ -27789,53 +36382,65 @@ #undef GPIO_DATA_5_OFFSET #define GPIO_DATA_5_OFFSET 0XFF0A0054 -/*Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW]*/ +/* +* Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW] +*/ #undef GPIO_MASK_DATA_5_MSW_MASK_5_MSW_DEFVAL #undef GPIO_MASK_DATA_5_MSW_MASK_5_MSW_SHIFT #undef GPIO_MASK_DATA_5_MSW_MASK_5_MSW_MASK -#define GPIO_MASK_DATA_5_MSW_MASK_5_MSW_DEFVAL 0x00000000 -#define GPIO_MASK_DATA_5_MSW_MASK_5_MSW_SHIFT 16 -#define GPIO_MASK_DATA_5_MSW_MASK_5_MSW_MASK 0xFFFF0000U +#define GPIO_MASK_DATA_5_MSW_MASK_5_MSW_DEFVAL 0x00000000 +#define GPIO_MASK_DATA_5_MSW_MASK_5_MSW_SHIFT 16 +#define GPIO_MASK_DATA_5_MSW_MASK_5_MSW_MASK 0xFFFF0000U -/*Operation is the same as DIRM_0[DIRECTION_0]*/ +/* +* Operation is the same as DIRM_0[DIRECTION_0] +*/ #undef GPIO_DIRM_5_DIRECTION_5_DEFVAL #undef GPIO_DIRM_5_DIRECTION_5_SHIFT #undef GPIO_DIRM_5_DIRECTION_5_MASK -#define GPIO_DIRM_5_DIRECTION_5_DEFVAL -#define GPIO_DIRM_5_DIRECTION_5_SHIFT 0 -#define GPIO_DIRM_5_DIRECTION_5_MASK 0xFFFFFFFFU +#define GPIO_DIRM_5_DIRECTION_5_DEFVAL +#define GPIO_DIRM_5_DIRECTION_5_SHIFT 0 +#define GPIO_DIRM_5_DIRECTION_5_MASK 0xFFFFFFFFU -/*Operation is the same as OEN_0[OP_ENABLE_0]*/ +/* +* Operation is the same as OEN_0[OP_ENABLE_0] +*/ #undef GPIO_OEN_5_OP_ENABLE_5_DEFVAL #undef GPIO_OEN_5_OP_ENABLE_5_SHIFT #undef GPIO_OEN_5_OP_ENABLE_5_MASK -#define GPIO_OEN_5_OP_ENABLE_5_DEFVAL -#define GPIO_OEN_5_OP_ENABLE_5_SHIFT 0 -#define GPIO_OEN_5_OP_ENABLE_5_MASK 0xFFFFFFFFU +#define GPIO_OEN_5_OP_ENABLE_5_DEFVAL +#define GPIO_OEN_5_OP_ENABLE_5_SHIFT 0 +#define GPIO_OEN_5_OP_ENABLE_5_MASK 0xFFFFFFFFU -/*Output Data*/ +/* +* Output Data +*/ #undef GPIO_DATA_5_DATA_5_DEFVAL #undef GPIO_DATA_5_DATA_5_SHIFT #undef GPIO_DATA_5_DATA_5_MASK -#define GPIO_DATA_5_DATA_5_DEFVAL -#define GPIO_DATA_5_DATA_5_SHIFT 0 -#define GPIO_DATA_5_DATA_5_MASK 0xFFFFFFFFU +#define GPIO_DATA_5_DATA_5_DEFVAL +#define GPIO_DATA_5_DATA_5_SHIFT 0 +#define GPIO_DATA_5_DATA_5_MASK 0xFFFFFFFFU -/*Output Data*/ +/* +* Output Data +*/ #undef GPIO_DATA_5_DATA_5_DEFVAL #undef GPIO_DATA_5_DATA_5_SHIFT #undef GPIO_DATA_5_DATA_5_MASK -#define GPIO_DATA_5_DATA_5_DEFVAL -#define GPIO_DATA_5_DATA_5_SHIFT 0 -#define GPIO_DATA_5_DATA_5_MASK 0xFFFFFFFFU +#define GPIO_DATA_5_DATA_5_DEFVAL +#define GPIO_DATA_5_DATA_5_SHIFT 0 +#define GPIO_DATA_5_DATA_5_MASK 0xFFFFFFFFU -/*Output Data*/ +/* +* Output Data +*/ #undef GPIO_DATA_5_DATA_5_DEFVAL #undef GPIO_DATA_5_DATA_5_SHIFT #undef GPIO_DATA_5_DATA_5_MASK -#define GPIO_DATA_5_DATA_5_DEFVAL -#define GPIO_DATA_5_DATA_5_SHIFT 0 -#define GPIO_DATA_5_DATA_5_MASK 0xFFFFFFFFU +#define GPIO_DATA_5_DATA_5_DEFVAL +#define GPIO_DATA_5_DATA_5_SHIFT 0 +#define GPIO_DATA_5_DATA_5_MASK 0xFFFFFFFFU #ifdef __cplusplus extern "C" { #endif @@ -27848,6 +36453,7 @@ extern "C" { int psu_ddr_protection(); int psu_lpd_protection(); int psu_protection_lock(); + unsigned long psu_ddr_qos_init_data(void); unsigned long psu_apply_master_tz(); #ifdef __cplusplus } diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/system.hdf b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/system.hdf index 01f637605..8502f0d4b 100644 Binary files a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/system.hdf and b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/system.hdf differ